pax_global_header00006660000000000000000000000064151600170720014511gustar00rootroot0000000000000052 comment=cfe6dd5ed7fff8b7c7ad1e90c2a2cad151948620 diff-1.0.1/000077500000000000000000000000001516001707200124205ustar00rootroot00000000000000diff-1.0.1/.github/000077500000000000000000000000001516001707200137605ustar00rootroot00000000000000diff-1.0.1/.github/workflows/000077500000000000000000000000001516001707200160155ustar00rootroot00000000000000diff-1.0.1/.github/workflows/go.yml000066400000000000000000000022071516001707200171460ustar00rootroot00000000000000# This workflow will build a golang project # For more information see: https://docs.github.com/en/actions/automating-builds-and-tests/building-and-testing-go name: Go on: push: branches: [ "main" ] pull_request: branches: [ "main" ] jobs: test: runs-on: ubuntu-latest steps: - uses: actions/checkout@v5 - name: Set up Go uses: actions/setup-go@v6 with: go-version-file: 'go.mod' - name: Build run: go build -v ./... - name: Test run: go test -v -vet=off ./... lint: runs-on: ubuntu-latest steps: - uses: actions/checkout@v5 - name: Set up Go uses: actions/setup-go@v6 with: go-version-file: 'go.mod' - name: Go Format run: gofmt -s -w . && git diff --exit-code - name: Verify dependencies run: go mod verify - name: Go Mod Tidy run: go mod tidy && git diff --exit-code - name: Go Vet run: go vet ./... - name: Go Generate run: go generate ./... && git diff --exit-code vulncheck: runs-on: ubuntu-latest steps: - name: Go Vulncheck uses: golang/govulncheck-action@v1diff-1.0.1/.github/workflows/latest-deps.yml000066400000000000000000000006721516001707200207720ustar00rootroot00000000000000name: Test Latest Deps on: schedule: - cron: '0 13 * * *' # daily at 1pm UTC workflow_dispatch: jobs: test-latest: runs-on: ubuntu-latest steps: - uses: actions/checkout@v5 - name: Set up Go uses: actions/setup-go@v6 with: go-version: stable - name: Update all dependencies run: go get -t -u ./... - name: Tidy run: go mod tidy - name: Test run: go test ./... diff-1.0.1/.github/workflows/vuln.yml000066400000000000000000000006251516001707200175270ustar00rootroot00000000000000name: Vulncheck on: schedule: - cron: '0 12 * * *' # daily at noon UTC workflow_dispatch: jobs: govulncheck: runs-on: ubuntu-latest steps: - uses: actions/checkout@v5 - name: Set up Go uses: actions/setup-go@v6 with: go-version-file: 'go.mod' - name: Run govulncheck run: go install golang.org/x/vuln/cmd/govulncheck@latest && govulncheck ./... diff-1.0.1/LICENSE000066400000000000000000000261351516001707200134340ustar00rootroot00000000000000 Apache License Version 2.0, January 2004 http://www.apache.org/licenses/ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 1. 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See the License for the specific language governing permissions and limitations under the License. diff-1.0.1/README.md000066400000000000000000000251101516001707200136760ustar00rootroot00000000000000# znkr.io/diff [![Go Reference](https://pkg.go.dev/badge/znkr.io/diff.svg)](https://pkg.go.dev/znkr.io/diff) [![Go Report Card](https://goreportcard.com/badge/znkr.io/diff)](https://goreportcard.com/report/znkr.io/diff) A high-performance difference algorithm module for Go. Difference algorithms compare two inputs and find the edits that transform one to the other. This is very useful to understand changes, for example when comparing a test result with the expected result or to understand which changes have been made to a file. This module provides diffing for arbitrary Go slices and text. I wrote a bit about the background and the design decisions that went into this module on [flo.znkr.io/diff](https://flo.znkr.io/diff). ## Installation To use this module in your Go project, run: ```bash go get znkr.io/diff ``` ## API Documentation Full documentation available at [pkg.go.dev/znkr.io/diff](https://pkg.go.dev/znkr.io/diff). ## Examples ### Comparing Slices Diffing two slices produces either the full list of edits ```go x := strings.Fields("calm seas reflect the sky") y := strings.Fields("restless seas reflect the sky defiantly") edits := diff.Edits(x, y) for i, edit := range edits { if i > 0 { fmt.Print(" ") } switch edit.Op { case diff.Match: fmt.Printf("%s", edit.X) case diff.Delete: fmt.Printf("[-%s-]", edit.X) case diff.Insert: fmt.Printf("{+%s+}", edit.Y) default: panic("never reached") } } // Output: // [-calm-] {+restless+} seas reflect the sky {+defiantly+} ``` or a list of hunks representing consecutive edits ```go x := strings.Fields("calm seas reflect the sky") y := strings.Fields("restless seas reflect the sky defiantly") hunks := diff.Hunks(x, y, diff.Context(1)) for i, h := range hunks { if i > 0 { fmt.Print(" … ") } for i, edit := range h.Edits { if i > 0 { fmt.Print(" ") } switch edit.Op { case diff.Match: fmt.Printf("%s", edit.X) case diff.Delete: fmt.Printf("[-%s-]", edit.X) case diff.Insert: fmt.Printf("{+%s+}", edit.Y) default: panic("never reached") } } } // Output: // [-calm-] {+restless+} seas … sky {+defiantly+} ``` For both functions, a `...Func` variant exists that works with arbitrary slices by taking an equality function. ### Comparing Text Because of its importance, comparing text line by line has special support and produces output in the unified diff format: ```go x := `this paragraph is not changed and barely long enough to create a new hunk this paragraph is going to be removed ` y := `this is a new paragraph that is inserted at the top this paragraph is not changed and barely long enough to create a new hunk ` fmt.Print(textdiff.Unified(x, y)) // Output: // @@ -1,3 +1,6 @@ // +this is a new paragraph // +that is inserted at the top // + // this paragraph // is not // changed and // @@ -5,7 +8,3 @@ // enough to // create a // new hunk // - // -this paragraph // -is going to be // -removed ``` ## Stability **API: Stable** - The API is stable and follows the Go module compatibility [guidelines](https://go.dev/doc/modules/version-policy). The exact diff output is not guaranteed to be stable: performance and quality improvements will likely change the output of a diff. Committing to a stable diff result would be too limiting. ## Diff Readability Diffs produced by this module are intended to be readable by humans. Readable diffs have been the subject of a lot of discussions and have even resulted in some new diffing algorithms like the patience or histogram algorithms in git. However, the best work about diff readability by far is [diff-slider-tools](https://github.com/mhagger/diff-slider-tools) by [Michael Haggerty](https://github.com/mhagger). He implemented a heuristic that's applied in a post-processing step to improve the readability. This module implements this heuristic in the [textdiff](https://pkg.go.dev/znkr.io/diff/textdiff) package. For example: ```go x := `// ... ["foo", "bar", "baz"].map do |i| i.upcase end ` y := `// ... ["foo", "bar", "baz"].map do |i| i end ["foo", "bar", "baz"].map do |i| i.upcase end ` fmt.Println("With textdiff.IndentHeuristic:") fmt.Print(textdiff.Unified(x, y, textdiff.IndentHeuristic())) fmt.Println() fmt.Println("Without textdiff.IndentHeuristic:") fmt.Print(textdiff.Unified(x, y)) // Output: // With textdiff.IndentHeuristic: // @@ -1,4 +1,8 @@ // // ... // +["foo", "bar", "baz"].map do |i| // + i // +end // + // ["foo", "bar", "baz"].map do |i| // i.upcase // end // // Without textdiff.IndentHeuristic: // @@ -1,4 +1,8 @@ // // ... // ["foo", "bar", "baz"].map do |i| // + i // +end // + // +["foo", "bar", "baz"].map do |i| // i.upcase // end ``` ## Performance By default, the underlying diff algorithm used is Myers' algorithm augmented by a number of heuristics to speed up the algorithm in exchange for non-minimal diffs. The `diff.Minimal` option is provided to skip these heuristics to get a minimal diff independent of the costs and `diff.Fast` to use a fast heuristic to get a non-minimal diff as fast as possible. On an M1 Mac, the default settings almost always result in runtimes < 1 ms, but truly large diffs (e.g. caused by changing generators for generated files) can result in runtimes of almost 100 ms. Below is the distribution of runtimes applying `textdiff.Unified` to every commit in the [Go repository](http://go.googlesource.com/go) (y-axis is in log scale): ![histogram of textdiff.Unified runtime](plots/perf_go_repo.png) ### Comparison with other Implementations Comparing the performance with other Go modules that implement the same features is always interesting, because it can surface missed optimization opportunities. This is especially interesting for larger inputs where superlinear growth can become a problem. Below are benchmarks of `znkr.io/diff` against other popular Go diff modules: - **znkr**: Default configuration with performance optimizations enabled - **znkr-minimal**: With `diff.Minimal()` option for minimal diffs - **znkr-fast**: With `diff.Fast()` option for fastest possible diffing - **go-internal**: Patience diff algorithm from [`github.com/rogpeppe/go-internal`](https://github.com/rogpeppe/go-internal) - **diffmatchpatch**: Implementation from [`github.com/sergi/go-diff`](https://github.com/sergi/go-diff) - **godebug**: Implementation from [`golang.org/x/tools/godebug`](https://pkg.go.dev/golang.org/x/tools/godebug) - **mb0**: Implementation from [`github.com/mb0/diff`](https://github.com/mb0/diff) - **udiff**: Implementation from [`github.com/aymanbagabas/go-udiff`](https://github.com/aymanbagabas/go-udiff) **Note:** It's possible that the benchmark is using `diffmatchpatch` incorrectly, the benchmark numbers certainly look suspiciously high. However, the way it's used in the benchmark is used in at least one large open source project. #### Runtime Performance (seconds per operation) On the benchmarks used for this comparison znkr.io/diff almost always outperforms the other implementations. However, there's one case where go-internal is significantly faster, but the resulting diff is 10% larger (see numbers below). | Test Case | znkr (baseline) | znkr-minimal | znkr-fast | go-internal | diffmatchpatch | godebug | mb0 | udiff | |-----------|-----------------|--------------|-----------|-------------|----------------|---------|-----|-------| | **large_01** | 2.707ms | 10.993ms
(+306.14%) | 2.642ms
(-2.40%) | 4.928ms
(+82.04%) | 43.205ms
(+1496.15%) | 181.374ms
(+6600.66%) | 84.950ms
(+3038.39%) | 7.915ms
(+192.40%) | | **large_02** | 20.591ms | 49.798ms
(+141.84%) | 1.840ms
(-91.06%) | 4.139ms
(-79.90%) | 623.986ms
(+2930.32%) | 3000.340ms
(+14470.84%) | 1513.701ms
(+7251.13%) | 6.457ms
(-68.64%) | | **large_03** | 3.210ms | 15.138ms
(+371.61%) | 3.130ms
(-2.49%) | 4.688ms
(+46.04%) | 31.851ms
(+892.26%) | 187.093ms
(+5728.54%) | 105.379ms
(+3182.89%) | 10.057ms
(+213.31%) | | **large_04** | 7.125ms | 249.229ms
(+3397.94%) | 5.557ms
(-22.01%) | 8.656ms
(+21.49%) | 1012.579ms
(+14111.61%) | 13230.536ms
(+185591.43%) | 2229.906ms
(+31196.87%) | 15.818ms
(+122.01%) | | **medium** | 26.79µs | 27.38µs
(+2.23%) | 27.54µs
(+2.81%) | 64.70µs
(+141.55%) | 258.27µs
(+864.18%) | 705.62µs
(+2534.24%) | 269.56µs
(+906.34%) | 290.81µs
(+985.66%) | | **small** | 18.30µs | 18.49µs
(+1.05%) | 18.43µs
(±0%) | 38.06µs
(+107.97%) | 78.23µs
(+327.41%) | 200.04µs
(+992.97%) | 52.86µs
(+188.83%) | 106.99µs
(+484.55%) | #### Diff Minimality (number of edits produced) | Test Case | znkr (baseline) | znkr-minimal | znkr-fast | go-internal | diffmatchpatch | godebug | mb0 | udiff | |-----------|----------------|---------------|-----------|-------------|----------------|---------|-----|-------| | **large_01** | 5.615k edits | 5.615k edits
(±0%) | 5.615k edits
(±0%) | 5.617k edits
(+0.04%) | 5.615k edits
(±0%) | 5.615k edits
(±0%) | 5.615k edits
(±0%) | 35.805k edits
(+537.67%) | | **large_02** | 28.87k edits | 28.83k edits
(-0.15%) | 31.80k edits
(+10.15%) | 31.81k edits
(+10.17%) | 28.83k edits
(-0.14%) | 28.83k edits
(-0.15%) | 28.83k edits
(-0.15%) | 31.80k edits
(+10.13%) | | **large_03** | 5.504k edits | 5.504k edits
(±0%) | 5.504k edits
(±0%) | 5.506k edits
(+0.04%) | 5.504k edits
(±0%) | 5.504k edits
(±0%) | 5.504k edits
(±0%) | 55.738k edits
(+912.68%) | | **large_04** | 26.99k edits | 26.99k edits
(-0.01%) | 27.80k edits
(+2.99%) | 27.80k edits
(+2.99%) | 60.36k edits
(+123.65%) | 26.99k edits
(-0.01%) | 26.99k edits
(-0.01%) | 103.22k edits
(+282.45%) | | **medium** | 277 edits | 277 edits
(±0%) | 277 edits
(±0%) | 283 edits
(+2.17%) | 277 edits
(±0%) | 277 edits
(±0%) | 277 edits
(±0%) | 431 edits
(+55.60%) | | **small** | 108 edits | 108 edits
(±0%) | 114 edits
(+5.56%) | 120 edits
(+11.11%) | 108 edits
(±0%) | 108 edits
(±0%) | 108 edits
(±0%) | 280 edits
(+159.26%) | ## Correctness I tested this diff implementation against every commit in the [Go repository](http://go.googlesource.com/go) using the standard unix `patch` tool to ensure that all diff results are correct. This test is part of the test suite for this module and can be run with ``` go run ./internal/cmd/eval -repo ``` ## License This module is distributed under the [Apache License, Version 2.0](https://www.apache.org/licenses/LICENSE-2.0), see [LICENSE](LICENSE) for more information. diff-1.0.1/diff.go000066400000000000000000000162331516001707200136640ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package diff import ( "slices" "znkr.io/diff/internal/config" "znkr.io/diff/internal/impl" "znkr.io/diff/internal/rvecs" ) // Op describes an edit operation. // //go:generate go tool golang.org/x/tools/cmd/stringer -type=Op type Op int const ( Match Op = iota // Two slice elements match Delete // A deletion from an element on the left slice Insert // An insertion of an element from the right side ) // Edit describes a single edit of a diff. // // - For Match, both X and Y contain the matching element. PosX and PosY contain their respective // positions in the input. // - For Delete, X contains the deleted element and Y is unset (zero value). PosX contains its // position in the input and PosY is -1. // - For Insert, Y contains the inserted element and X is unset (zero value). PosY contains its // position in the input and PosX is -1. type Edit[T any] struct { Op Op PosX, PosY int X, Y T } // Hunk describes a sequence of consecutive edits. type Hunk[T any] struct { PosX, EndX int // Start and end position in x. PosY, EndY int // Start and end position in y. Edits []Edit[T] // Edits to transform x[PosX:EndX] to y[PosY:EndY] } // Hunks compares the contents of x and y and returns the changes necessary to convert from one to // the other. // // The output is a sequence of hunks. A hunk represents a contiguous block of changes (insertions // and deletions) along with some surrounding context. The amount of context can be configured using // [Context]. // // If x and y are identical, the output has length zero. // // The following options are supported: [Context], [Minimal], [Fast] // // Important: The output is not guaranteed to be stable and may change with minor version upgrades. // DO NOT rely on the output being stable. func Hunks[T comparable](x, y []T, opts ...Option) []Hunk[T] { cfg := config.FromOptions(opts, config.Context|config.Minimal|config.Fast) rx, ry := impl.Diff(x, y, cfg) return hunks(x, y, rx, ry, cfg) } // HunksFunc compares the contents of x and y using the provided equality comparison and returns the // changes necessary to convert from one to the other. // // The output is a sequence of hunks that each describe a number of consecutive edits. Hunks include // a number of matching elements before and after the last delete or insert operation. The number of // elements can be configured using [Context]. // // If x and y are identical, the output has length zero. // // The following options are supported: [Context], [Minimal] // // Note that this function has generally worse performance than [Hunks] for diffs with many changes. // // Important: The output is not guaranteed to be stable and may change with minor version upgrades. // DO NOT rely on the output being stable. func HunksFunc[T any](x, y []T, eq func(a, b T) bool, opts ...Option) []Hunk[T] { cfg := config.FromOptions(opts, config.Context|config.Minimal) rx, ry := impl.DiffFunc(x, y, eq, cfg) return hunks(x, y, rx, ry, cfg) } func hunks[T any](x, y []T, rx, ry []bool, cfg config.Config) []Hunk[T] { // Compute the number of hunks and edits, this is relatively cheap and allows us to preallocate // the return values. var nhunks, nedits int for hunk := range rvecs.Hunks(rx, ry, cfg) { nhunks++ nedits += hunk.Edits } if nhunks == 0 { return nil } eout := make([]Edit[T], 0, nedits) hout := make([]Hunk[T], 0, nhunks) for hunk := range rvecs.Hunks(rx, ry, cfg) { for s, t := hunk.S0, hunk.T0; s < hunk.S1 || t < hunk.T1; { for s < hunk.S1 && rx[s] { eout = append(eout, Edit[T]{ Op: Delete, X: x[s], PosX: s, PosY: -1, }) s++ } for t < hunk.T1 && ry[t] { eout = append(eout, Edit[T]{ Op: Insert, Y: y[t], PosX: -1, PosY: t, }) t++ } for s < hunk.S1 && t < hunk.T1 && !rx[s] && !ry[t] { eout = append(eout, Edit[T]{ Op: Match, X: x[s], Y: y[t], PosX: s, PosY: t, }) s++ t++ } } hout = append(hout, Hunk[T]{ PosX: hunk.S0, EndX: hunk.S1, PosY: hunk.T0, EndY: hunk.T1, Edits: slices.Clip(eout), }) eout = eout[len(eout):] } return hout } // Edits compares the contents of x and y and returns the changes necessary to convert from one to // the other. // // Edits returns one edit for every element in the input slices. If x and y are identical, the // output will consist of a match edit for every input element. // // The following option is supported: [Minimal], [Fast] // // Important: The output is not guaranteed to be stable and may change with minor version upgrades. // DO NOT rely on the output being stable. func Edits[T comparable](x, y []T, opts ...Option) []Edit[T] { cfg := config.FromOptions(opts, config.Minimal|config.Fast) rx, ry := impl.Diff(x, y, cfg) return edits(x, y, rx, ry) } // EditsFunc compares the contents of x and y using the provided equality comparison and returns the // changes necessary to convert from one to the other. // // EditsFunc returns edits for every element in the input. If both x and y are identical, the output // will consist of a match edit for every input element. // // The following option is supported: [Minimal] // // Note that this function has generally worse performance than [Edits] for diffs with many changes. // // Important: The output is not guaranteed to be stable and may change with minor version upgrades. // DO NOT rely on the output being stable. func EditsFunc[T any](x, y []T, eq func(a, b T) bool, opts ...Option) []Edit[T] { cfg := config.FromOptions(opts, config.Minimal) rx, ry := impl.DiffFunc(x, y, eq, cfg) return edits(x, y, rx, ry) } func edits[T any](x, y []T, rx, ry []bool) []Edit[T] { // Compute the number of edits, this is relatively cheap and allows us to preallocate the return // value. n, m := len(rx)-1, len(ry)-1 var nedits int for s, t := 0, 0; s < n || t < m; { for s < n && rx[s] { nedits++ s++ } for t < m && ry[t] { nedits++ t++ } for s < n && t < m && !rx[s] && !ry[t] { nedits++ s++ t++ } } if nedits == 0 { return nil } eout := make([]Edit[T], 0, nedits) for s, t := 0, 0; s < n || t < m; { for s < n && rx[s] { eout = append(eout, Edit[T]{ Op: Delete, X: x[s], PosX: s, PosY: -1, }) s++ } for t < m && ry[t] { eout = append(eout, Edit[T]{ Op: Insert, Y: y[t], PosX: -1, PosY: t, }) t++ } for s < n && t < m && !rx[s] && !ry[t] { eout = append(eout, Edit[T]{ Op: Match, X: x[s], Y: y[t], PosX: s, PosY: t, }) s++ t++ } } return eout } diff-1.0.1/diff_test.go000066400000000000000000000247321516001707200147260ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package diff import ( "crypto/sha256" "fmt" "math/rand/v2" "strings" "testing" "github.com/google/go-cmp/cmp" ) func TestHunks(t *testing.T) { tests := []struct { name string x, y []string opts []Option want []Hunk[string] }{ { name: "identical", x: []string{"foo", "bar", "baz"}, y: []string{"foo", "bar", "baz"}, want: nil, }, { name: "empty", x: nil, y: nil, want: nil, }, { name: "x-empty", x: nil, y: []string{"foo", "bar", "baz"}, want: []Hunk[string]{ { PosX: 0, PosY: 0, EndX: 0, EndY: 3, Edits: []Edit[string]{ {Insert, -1, 0, "", "foo"}, {Insert, -1, 1, "", "bar"}, {Insert, -1, 2, "", "baz"}, }, }, }, }, { name: "y-empty", x: []string{"foo", "bar", "baz"}, y: nil, want: []Hunk[string]{ { PosX: 0, PosY: 0, EndX: 3, EndY: 0, Edits: []Edit[string]{ {Delete, 0, -1, "foo", ""}, {Delete, 1, -1, "bar", ""}, {Delete, 2, -1, "baz", ""}, }, }, }, }, { name: "same-prefix", x: []string{"foo", "bar"}, y: []string{"foo", "baz"}, want: []Hunk[string]{ { PosX: 0, EndX: 2, PosY: 0, EndY: 2, Edits: []Edit[string]{ {Match, 0, 0, "foo", "foo"}, {Delete, 1, -1, "bar", ""}, {Insert, -1, 1, "", "baz"}, }, }, }, }, { name: "same-suffix", x: []string{"foo", "bar"}, y: []string{"loo", "bar"}, want: []Hunk[string]{ { PosX: 0, EndX: 2, PosY: 0, EndY: 2, Edits: []Edit[string]{ {Delete, 0, -1, "foo", ""}, {Insert, -1, 0, "", "loo"}, {Match, 1, 1, "bar", "bar"}, }, }, }, }, { name: "ABCABBA_to_CBABAC", x: strings.Split("ABCABBA", ""), y: strings.Split("CBABAC", ""), want: []Hunk[string]{ { PosX: 0, PosY: 0, EndX: 7, EndY: 6, Edits: []Edit[string]{ {Delete, 0, -1, "A", ""}, {Insert, -1, 0, "", "C"}, {Match, 1, 1, "B", "B"}, {Delete, 2, -1, "C", ""}, {Match, 3, 2, "A", "A"}, {Match, 4, 3, "B", "B"}, {Delete, 5, -1, "B", ""}, {Match, 6, 4, "A", "A"}, {Insert, -1, 5, "", "C"}, }, }, }, }, { name: "ABCABBA_to_CBABAC_no_context", x: strings.Split("ABCABBA", ""), y: strings.Split("CBABAC", ""), opts: []Option{Context(0)}, want: []Hunk[string]{ { PosX: 0, PosY: 0, EndX: 1, EndY: 1, Edits: []Edit[string]{ {Delete, 0, -1, "A", ""}, {Insert, -1, 0, "", "C"}, }, }, { PosX: 2, PosY: 2, EndX: 3, EndY: 2, Edits: []Edit[string]{ {Delete, 2, -1, "C", ""}, }, }, { PosX: 5, PosY: 4, EndX: 6, EndY: 4, Edits: []Edit[string]{ {Delete, 5, -1, "B", ""}, }, }, { PosX: 7, PosY: 5, EndX: 7, EndY: 6, Edits: []Edit[string]{ {Insert, -1, 5, "", "C"}, }, }, }, }, { name: "two-hunks", x: []string{ "this paragraph", "is not", "changed and", "barely long", "enough to", "create a", "new hunk", "", "this paragraph", "is going to be", "removed", }, y: []string{ "this is a new paragraph", "that is inserted at the top", "", "this paragraph", "is not", "changed and", "barely long", "enough to", "create a", "new hunk", }, want: []Hunk[string]{ { PosX: 0, EndX: 3, PosY: 0, EndY: 6, Edits: []Edit[string]{ {Insert, -1, 0, "", "this is a new paragraph"}, {Insert, -1, 1, "", "that is inserted at the top"}, {Insert, -1, 2, "", ""}, {Match, 0, 3, "this paragraph", "this paragraph"}, {Match, 1, 4, "is not", "is not"}, {Match, 2, 5, "changed and", "changed and"}, }, }, { PosX: 4, EndX: 11, PosY: 7, EndY: 10, Edits: []Edit[string]{ {Match, 4, 7, "enough to", "enough to"}, {Match, 5, 8, "create a", "create a"}, {Match, 6, 9, "new hunk", "new hunk"}, {Delete, 7, -1, "", ""}, {Delete, 8, -1, "this paragraph", ""}, {Delete, 9, -1, "is going to be", ""}, {Delete, 10, -1, "removed", ""}, }, }, }, }, { name: "overlapping-consecutive-hunks-are-merged", x: []string{ "this paragraph", "stays but is", "not long enough", "to create a", "new hunk", "", "this paragraph", "is going to be", "removed", }, y: []string{ "this is a new paragraph", "that is inserted at the top", "", "this paragraph", "stays but is", "not long enough", "to create a", "new hunk", }, want: []Hunk[string]{ { PosX: 0, EndX: 9, PosY: 0, EndY: 8, Edits: []Edit[string]{ {Insert, -1, 0, "", "this is a new paragraph"}, {Insert, -1, 1, "", "that is inserted at the top"}, {Insert, -1, 2, "", ""}, {Match, 0, 3, "this paragraph", "this paragraph"}, {Match, 1, 4, "stays but is", "stays but is"}, {Match, 2, 5, "not long enough", "not long enough"}, {Match, 3, 6, "to create a", "to create a"}, {Match, 4, 7, "new hunk", "new hunk"}, {Delete, 5, -1, "", ""}, {Delete, 6, -1, "this paragraph", ""}, {Delete, 7, -1, "is going to be", ""}, {Delete, 8, -1, "removed", ""}, }, }, }, }, } for _, tt := range tests { t.Run(tt.name, func(t *testing.T) { { got := Hunks(tt.x, tt.y, tt.opts...) if diff := cmp.Diff(tt.want, got); diff != "" { t.Errorf("Hunks(...) result is different [-want, +got]:\n%s", diff) } } { got := HunksFunc(tt.x, tt.y, func(a, b string) bool { return a == b }, tt.opts...) if diff := cmp.Diff(tt.want, got); diff != "" { t.Errorf("HunksFunc(...) result is different [-want, +got]:\n%s", diff) } } }) } } func TestEdits(t *testing.T) { tests := []struct { name string x, y []string want []Edit[string] }{ { name: "identical", x: []string{"foo", "bar", "baz"}, y: []string{"foo", "bar", "baz"}, want: []Edit[string]{ {Match, 0, 0, "foo", "foo"}, {Match, 1, 1, "bar", "bar"}, {Match, 2, 2, "baz", "baz"}, }, }, { name: "empty", }, { name: "x-empty", y: []string{"foo", "bar", "baz"}, want: []Edit[string]{ {Insert, -1, 0, "", "foo"}, {Insert, -1, 1, "", "bar"}, {Insert, -1, 2, "", "baz"}, }, }, { name: "y-empty", x: []string{"foo", "bar", "baz"}, want: []Edit[string]{ {Delete, 0, -1, "foo", ""}, {Delete, 1, -1, "bar", ""}, {Delete, 2, -1, "baz", ""}, }, }, { name: "ABCABBA_to_CBABAC", x: strings.Split("ABCABBA", ""), y: strings.Split("CBABAC", ""), want: []Edit[string]{ {Delete, 0, -1, "A", ""}, {Insert, -1, 0, "", "C"}, {Match, 1, 1, "B", "B"}, {Delete, 2, -1, "C", ""}, {Match, 3, 2, "A", "A"}, {Match, 4, 3, "B", "B"}, {Delete, 5, -1, "B", ""}, {Match, 6, 4, "A", "A"}, {Insert, -1, 5, "", "C"}, }, }, { name: "same-prefix", x: []string{"foo", "bar"}, y: []string{"foo", "baz"}, want: []Edit[string]{ {Match, 0, 0, "foo", "foo"}, {Delete, 1, -1, "bar", ""}, {Insert, -1, 1, "", "baz"}, }, }, { name: "same-suffix", x: []string{"foo", "bar"}, y: []string{"loo", "bar"}, want: []Edit[string]{ {Delete, 0, -1, "foo", ""}, {Insert, -1, 0, "", "loo"}, {Match, 1, 1, "bar", "bar"}, }, }, } for _, tt := range tests { t.Run(tt.name, func(t *testing.T) { { got := Edits(tt.x, tt.y) if diff := cmp.Diff(tt.want, got); diff != "" { t.Errorf("Edits(...) result is different (-want, +got):\n%s", diff) } } { got := EditsFunc(tt.x, tt.y, func(a, b string) bool { return a == b }) if diff := cmp.Diff(tt.want, got); diff != "" { t.Errorf("EditsFunc(...) result is different (-want, +got):\n%s", diff) } } }) } } func BenchmarkHunks(b *testing.B) { for _, s := range benchmarkSpecs { b.Run(s.name(), func(b *testing.B) { b.ReportAllocs() x, y := s.generate([]byte{}) for b.Loop() { _ = Hunks(x, y) } }) } } func BenchmarkHunksFunc(b *testing.B) { for _, s := range benchmarkSpecs { b.Run(s.name(), func(b *testing.B) { b.ReportAllocs() x, y := s.generate([]byte{}) for b.Loop() { _ = HunksFunc(x, y, func(a, b int) bool { return a == b }) } }) } } func BenchmarkEdits(b *testing.B) { for _, s := range benchmarkSpecs { b.Run(s.name(), func(b *testing.B) { b.ReportAllocs() x, y := s.generate([]byte{}) for b.Loop() { _ = Edits(x, y) } }) } } func BenchmarkEditsFunc(b *testing.B) { for _, s := range benchmarkSpecs { b.Run(s.name(), func(b *testing.B) { b.ReportAllocs() x, y := s.generate([]byte{}) for b.Loop() { _ = EditsFunc(x, y, func(a, b int) bool { return a == b }) } }) } } type spec struct { N, M int // Length of x and y respectively D int // Number of edits (besides edits due to size differences) } var benchmarkSpecs = []spec{ {50, 50, 10}, {500, 50, 10}, {50, 500, 10}, {500, 500, 10}, {500, 500, 100}, {5000, 5500, 100}, } func (s spec) name() string { return fmt.Sprintf("N=%d_M=%d_D=%d", s.N, s.M, s.D) } func (s spec) generate(seed []byte) (x, y []int) { rng := rand.New(rand.NewChaCha8(sha256.Sum256(seed))) // Construct inputs based on the N, M, D specification. flipped := false n, m := s.N, s.M if n < m { n, m = m, n flipped = true } x = make([]int, n) for i := range x { x[i] = rng.IntN(100) } y = make([]int, m) delta := 0 if n != m { delta = rng.IntN((n - m) / 2) } for i := range y { y[i] = x[i+delta] } // We might already have some changes due to the different sizes for N and M, add D // additional changes. for d := s.D; d > 0; { i := rng.IntN(len(y)) if y[i] >= 0 { y[i] = -y[i] d-- } } if flipped { x, y = y, x } return } diff-1.0.1/doc.go000066400000000000000000000026641516001707200135240ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // Package diff provides functions to efficiently compare two slices similar to the Unix diff // command line tool to compare files. // // The main functions are [Hunks], which groups changes into contextual blocks, and [Edits], which // returns every individual change. By default, the algorithms are optimized for performance and may // use heuristics for very large inputs. Use [Minimal] to disable these heuristics when you need the // shortest possible diff. // // Performance: Default complexity is O(N^1.5 log N) time and O(N) space. With [Minimal], time // complexity is O(ND) where N = len(x) + len(y) and D is the number of edits. With [Fast], time // complexity is O(N log N). // // Note: For a line-by-line diff of text, please see [znkr.io/diff/textdiff]. // // [znkr.io/diff/textdiff]: https://pkg.go.dev/znkr.io/diff/textdiff package diff diff-1.0.1/example_test.go000066400000000000000000000072611516001707200154470ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package diff_test import ( "fmt" "strings" "znkr.io/diff" ) // Compare to strings line by line and output the difference as a pseudo-unified diff output (i.e. // it's similar to what diff -u would produce). The format is not a correct unified diff though, in // particular line endings (esp. at the end of the input) are handled differently. // // More generally, comparing text line by line is better solved with the textdiff subpackage. func ExampleHunks_pseudoUnified() { x := `this paragraph is not changed and barely long enough to create a new hunk this paragraph is going to be removed` y := `this is a new paragraph that is inserted at the top this paragraph is not changed and barely long enough to create a new hunk` xlines := strings.Split(x, "\n") ylines := strings.Split(y, "\n") hunks := diff.Hunks(xlines, ylines) for _, h := range hunks { fmt.Printf("@@ -%d,%d +%d,%d @@\n", h.PosX+1, h.EndX-h.PosX, h.PosY+1, h.EndY-h.PosY) for _, edit := range h.Edits { switch edit.Op { case diff.Match: fmt.Printf(" %s\n", edit.X) case diff.Delete: fmt.Printf("-%s\n", edit.X) case diff.Insert: fmt.Printf("+%s\n", edit.Y) default: panic("never reached") } } } // Output: // @@ -1,3 +1,6 @@ // +this is a new paragraph // +that is inserted at the top // + // this paragraph // is not // changed and // @@ -5,7 +8,3 @@ // enough to // create a // new hunk // - // -this paragraph // -is going to be // -removed } // Compare two strings rune by rune. func ExampleEdits_runes() { x := []rune("Hello, World") y := []rune("Hello, 世界") edits := diff.Edits(x, y) for _, edit := range edits { switch edit.Op { case diff.Match: fmt.Printf("%s", string(edit.X)) case diff.Delete: fmt.Printf("[-%s-]", string(edit.X)) case diff.Insert: fmt.Printf("{+%s+}", string(edit.Y)) default: panic("never reached") } } // Output: // Hello, [-W-][-o-][-r-][-l-][-d-]{+世+}{+界+} } // Compare two strings word by word. func ExampleEdits_words() { x := strings.Fields("calm seas reflect the sky") y := strings.Fields("restless seas reflect the sky defiantly") edits := diff.Edits(x, y) for i, edit := range edits { if i > 0 { fmt.Print(" ") } switch edit.Op { case diff.Match: fmt.Printf("%s", edit.X) case diff.Delete: fmt.Printf("[-%s-]", edit.X) case diff.Insert: fmt.Printf("{+%s+}", edit.Y) default: panic("never reached") } } // Output: // [-calm-] {+restless+} seas reflect the sky {+defiantly+} } func ExampleContext() { x := strings.Fields("calm seas reflect the sky") y := strings.Fields("restless seas reflect the sky defiantly") hunks := diff.Hunks(x, y, diff.Context(1)) for i, h := range hunks { if i > 0 { fmt.Print(" … ") } for i, edit := range h.Edits { if i > 0 { fmt.Print(" ") } switch edit.Op { case diff.Match: fmt.Printf("%s", edit.X) case diff.Delete: fmt.Printf("[-%s-]", edit.X) case diff.Insert: fmt.Printf("{+%s+}", edit.Y) default: panic("never reached") } } } // Output: // [-calm-] {+restless+} seas … sky {+defiantly+} } diff-1.0.1/go.mod000066400000000000000000000004321516001707200135250ustar00rootroot00000000000000module znkr.io/diff go 1.24.13 tool ( golang.org/x/tools/cmd/stringer znkr.io/diff/internal/cmd/specializemyers ) require ( github.com/google/go-cmp v0.7.0 golang.org/x/tools v0.42.0 ) require ( golang.org/x/mod v0.33.0 // indirect golang.org/x/sync v0.19.0 // indirect ) diff-1.0.1/go.sum000066400000000000000000000011701516001707200135520ustar00rootroot00000000000000github.com/google/go-cmp v0.7.0 h1:wk8382ETsv4JYUZwIsn6YpYiWiBsYLSJiTsyBybVuN8= github.com/google/go-cmp v0.7.0/go.mod h1:pXiqmnSA92OHEEa9HXL2W4E7lf9JzCmGVUdgjX3N/iU= golang.org/x/mod v0.33.0 h1:tHFzIWbBifEmbwtGz65eaWyGiGZatSrT9prnU8DbVL8= golang.org/x/mod v0.33.0/go.mod h1:swjeQEj+6r7fODbD2cqrnje9PnziFuw4bmLbBZFrQ5w= golang.org/x/sync v0.19.0 h1:vV+1eWNmZ5geRlYjzm2adRgW2/mcpevXNg50YZtPCE4= golang.org/x/sync v0.19.0/go.mod h1:9KTHXmSnoGruLpwFjVSX0lNNA75CykiMECbovNTZqGI= golang.org/x/tools v0.42.0 h1:uNgphsn75Tdz5Ji2q36v/nsFSfR/9BRFvqhGBaJGd5k= golang.org/x/tools v0.42.0/go.mod h1:Ma6lCIwGZvHK6XtgbswSoWroEkhugApmsXyrUmBhfr0= diff-1.0.1/internal/000077500000000000000000000000001516001707200142345ustar00rootroot00000000000000diff-1.0.1/internal/benchmarks/000077500000000000000000000000001516001707200163515ustar00rootroot00000000000000diff-1.0.1/internal/benchmarks/README.md000066400000000000000000000002571516001707200176340ustar00rootroot00000000000000# Comparison of znkr.io/diff with other implementations Run this command to produce the comparison: ``` go test -count 10 -bench=. . | benchstat -col /impl -row /name - ``` diff-1.0.1/internal/benchmarks/benchmark_test.go000066400000000000000000000032171516001707200216740ustar00rootroot00000000000000package benchmarks import ( "bytes" "path/filepath" "strings" "testing" "golang.org/x/tools/txtar" "znkr.io/diff" "znkr.io/diff/textdiff" ) type testdata struct { name string x, y []byte } func loadTestdata(t testing.TB) []testdata { t.Helper() testFiles, err := filepath.Glob("testdata/*.test") if err != nil { t.Fatalf("Failed to read testdata: %v", err) } var tests []testdata for _, filename := range testFiles { ar, err := txtar.ParseFile(filename) if err != nil { t.Fatalf("failed to parse test case: %v", err) } name := strings.TrimPrefix(filename, "testdata/") test := testdata{ name: name, } for _, f := range ar.Files { switch f.Name { case "x": test.x = f.Data case "y": test.y = f.Data default: t.Fatalf("unknown file in archive: %v", f) } } tests = append(tests, test) } return tests } func BenchmarkDiffs(b *testing.B) { optD := make(map[string]int) for _, td := range loadTestdata(b) { edits := textdiff.Edits(td.x, td.y, diff.Minimal()) d := 0 for _, edit := range edits { if edit.Op != diff.Match { d++ } } optD[td.name] = d } for _, impl := range Impls { b.Run("impl="+impl.Name, func(b *testing.B) { for _, td := range loadTestdata(b) { b.Run("name="+td.name, func(b *testing.B) { for b.Loop() { _ = impl.Diff(td.x, td.y) } b.StopTimer() out := impl.Diff(td.x, td.y) edits := 0 for _, line := range bytes.Split(out, []byte("\n")) { if bytes.HasPrefix(line, []byte{'+'}) || bytes.HasPrefix(line, []byte{'-'}) { edits++ } } b.ReportMetric(float64(edits), "edits") }) } }) } } diff-1.0.1/internal/benchmarks/cmd/000077500000000000000000000000001516001707200171145ustar00rootroot00000000000000diff-1.0.1/internal/benchmarks/cmd/diff/000077500000000000000000000000001516001707200200245ustar00rootroot00000000000000diff-1.0.1/internal/benchmarks/cmd/diff/main.go000066400000000000000000000030411516001707200212750ustar00rootroot00000000000000// diff is a small CLI to manually run the diffing implementations used for benchmarking. package main import ( "flag" "fmt" "os" "golang.org/x/tools/txtar" "znkr.io/diff/internal/benchmarks" ) type config struct { lib string x, y string txtar string } func main() { var cfg config flag.StringVar(&cfg.lib, "lib", "znkr", "library to use for diffing") flag.StringVar(&cfg.txtar, "txtar", "", "use testdata txtar file instead of two input files") flag.Parse() if cfg.txtar != "" { if flag.CommandLine.NArg() != 0 { fmt.Fprintf(os.Stderr, "error: usage: diff -txtar \n") os.Exit(1) } } else { if flag.CommandLine.NArg() != 2 { fmt.Fprintf(os.Stderr, "error: usage: diff \n") os.Exit(1) } cfg.x = flag.CommandLine.Arg(0) cfg.y = flag.CommandLine.Arg(1) } if err := run(cfg); err != nil { fmt.Fprintf(os.Stderr, "error: %v\n", err) os.Exit(1) } } func run(cfg config) error { var lib *benchmarks.Impl for _, l := range benchmarks.Impls { if l.Name == cfg.lib { lib = &l } } if lib == nil { return fmt.Errorf("lib not found %q", cfg.lib) } var x, y []byte if cfg.txtar != "" { ar, err := txtar.ParseFile(cfg.txtar) if err != nil { return err } for _, f := range ar.Files { switch f.Name { case "x": x = f.Data case "y": y = f.Data } } } else { var err error x, err = os.ReadFile(cfg.x) if err != nil { return err } y, err = os.ReadFile(cfg.y) if err != nil { return err } } out := lib.Diff(x, y) os.Stdout.Write(out) return nil } diff-1.0.1/internal/benchmarks/go.mod000066400000000000000000000005751516001707200174660ustar00rootroot00000000000000module znkr.io/diff/internal/benchmarks go 1.24.0 require ( github.com/aymanbagabas/go-udiff v0.3.1 github.com/kylelemons/godebug v1.1.0 github.com/mb0/diff v0.0.0-20131118162322-d8d9a906c24d github.com/rogpeppe/go-internal v1.14.1 github.com/sergi/go-diff v1.4.0 golang.org/x/tools v0.37.0 znkr.io/diff v0.0.0-20250814195549-58fd23adf4e1 ) replace znkr.io/diff => ../.. diff-1.0.1/internal/benchmarks/go.sum000066400000000000000000000051121516001707200175030ustar00rootroot00000000000000github.com/aymanbagabas/go-udiff v0.3.1 h1:LV+qyBQ2pqe0u42ZsUEtPiCaUoqgA9gYRDs3vj1nolY= github.com/aymanbagabas/go-udiff v0.3.1/go.mod h1:G0fsKmG+P6ylD0r6N/KgQD/nWzgfnl8ZBcNLgcbrw8E= github.com/davecgh/go-spew v1.1.0/go.mod h1:J7Y8YcW2NihsgmVo/mv3lAwl/skON4iLHjSsI+c5H38= github.com/davecgh/go-spew v1.1.1 h1:vj9j/u1bqnvCEfJOwUhtlOARqs3+rkHYY13jYWTU97c= github.com/davecgh/go-spew v1.1.1/go.mod h1:J7Y8YcW2NihsgmVo/mv3lAwl/skON4iLHjSsI+c5H38= github.com/google/go-cmp v0.7.0 h1:wk8382ETsv4JYUZwIsn6YpYiWiBsYLSJiTsyBybVuN8= github.com/google/go-cmp v0.7.0/go.mod h1:pXiqmnSA92OHEEa9HXL2W4E7lf9JzCmGVUdgjX3N/iU= github.com/kr/pretty v0.1.0/go.mod h1:dAy3ld7l9f0ibDNOQOHHMYYIIbhfbHSm3C4ZsoJORNo= github.com/kr/pty v1.1.1/go.mod h1:pFQYn66WHrOpPYNljwOMqo10TkYh1fy3cYio2l3bCsQ= github.com/kr/text v0.1.0/go.mod h1:4Jbv+DJW3UT/LiOwJeYQe1efqtUx/iVham/4vfdArNI= github.com/kylelemons/godebug v1.1.0 h1:RPNrshWIDI6G2gRW9EHilWtl7Z6Sb1BR0xunSBf0SNc= github.com/kylelemons/godebug v1.1.0/go.mod h1:9/0rRGxNHcop5bhtWyNeEfOS8JIWk580+fNqagV/RAw= github.com/mb0/diff v0.0.0-20131118162322-d8d9a906c24d h1:eAS2t2Vy+6psf9LZ4T5WXWsbkBt3Tu5PWekJy5AGyEU= github.com/mb0/diff v0.0.0-20131118162322-d8d9a906c24d/go.mod h1:3YMHqrw2Qu3Liy82v4QdAG17e9k91HZ7w3hqlpWqhDo= github.com/pmezard/go-difflib v1.0.0 h1:4DBwDE0NGyQoBHbLQYPwSUPoCMWR5BEzIk/f1lZbAQM= github.com/pmezard/go-difflib v1.0.0/go.mod h1:iKH77koFhYxTK1pcRnkKkqfTogsbg7gZNVY4sRDYZ/4= github.com/rogpeppe/go-internal v1.14.1 h1:UQB4HGPB6osV0SQTLymcB4TgvyWu6ZyliaW0tI/otEQ= github.com/rogpeppe/go-internal v1.14.1/go.mod h1:MaRKkUm5W0goXpeCfT7UZI6fk/L7L7so1lCWt35ZSgc= github.com/sergi/go-diff v1.4.0 h1:n/SP9D5ad1fORl+llWyN+D6qoUETXNZARKjyY2/KVCw= github.com/sergi/go-diff v1.4.0/go.mod h1:A0bzQcvG0E7Rwjx0REVgAGH58e96+X0MeOfepqsbeW4= github.com/stretchr/objx v0.1.0/go.mod h1:HFkY916IF+rwdDfMAkV7OtwuqBVzrE8GR6GFx+wExME= github.com/stretchr/testify v1.4.0 h1:2E4SXV/wtOkTonXsotYi4li6zVWxYlZuYNCXe9XRJyk= github.com/stretchr/testify v1.4.0/go.mod h1:j7eGeouHqKxXV5pUuKE4zz7dFj8WfuZ+81PSLYec5m4= golang.org/x/tools v0.37.0 h1:DVSRzp7FwePZW356yEAChSdNcQo6Nsp+fex1SUW09lE= golang.org/x/tools v0.37.0/go.mod h1:MBN5QPQtLMHVdvsbtarmTNukZDdgwdwlO5qGacAzF0w= gopkg.in/check.v1 v0.0.0-20161208181325-20d25e280405/go.mod h1:Co6ibVJAznAaIkqp8huTwlJQCZ016jof/cbN4VW5Yz0= gopkg.in/check.v1 v1.0.0-20190902080502-41f04d3bba15/go.mod h1:Co6ibVJAznAaIkqp8huTwlJQCZ016jof/cbN4VW5Yz0= gopkg.in/yaml.v2 v2.2.2/go.mod h1:hI93XBmqTisBFMUTm0b8Fm+jr3Dg1NNxqwp+5A1VGuI= gopkg.in/yaml.v2 v2.4.0 h1:D8xgwECY7CYvx+Y2n4sBz93Jn9JRvxdiyyo8CTfuKaY= gopkg.in/yaml.v2 v2.4.0/go.mod h1:RDklbk79AGWmwhnvt/jBztapEOGDOx6ZbXqjP6csGnQ= diff-1.0.1/internal/benchmarks/libraries.go000066400000000000000000000064301516001707200206570ustar00rootroot00000000000000package benchmarks import ( "bytes" "strings" "github.com/aymanbagabas/go-udiff" godebug "github.com/kylelemons/godebug/diff" mb0 "github.com/mb0/diff" gointernal "github.com/rogpeppe/go-internal/diff" "github.com/sergi/go-diff/diffmatchpatch" "znkr.io/diff" "znkr.io/diff/textdiff" ) type Impl struct { Name string Diff func(x, y []byte) []byte } var Impls = []Impl{ { Name: "znkr", Diff: func(x, y []byte) []byte { return textdiff.Unified(x, y, textdiff.IndentHeuristic()) }, }, { Name: "znkr-minimal", Diff: func(x, y []byte) []byte { return textdiff.Unified(x, y, diff.Minimal(), textdiff.IndentHeuristic()) }, }, { Name: "znkr-fast", Diff: func(x, y []byte) []byte { return textdiff.Unified(x, y, diff.Fast(), textdiff.IndentHeuristic()) }, }, { Name: "go-internal", Diff: func(x, y []byte) []byte { return gointernal.Diff("x", x, "y", y) }, }, { Name: "diffmatchpatch", Diff: func(x, y []byte) []byte { // This function is not exactly creating a unified diff, but it's close enough to be // comparable. dmp := diffmatchpatch.New() rx, ry, lines := dmp.DiffLinesToRunes(string(x), string(y)) diffs := dmp.DiffMainRunes(rx, ry, false) diffs = dmp.DiffCharsToLines(diffs, lines) var buf bytes.Buffer for _, diff := range diffs { text := diff.Text switch diff.Type { case diffmatchpatch.DiffInsert: lines := strings.SplitAfter(text, "\n") for _, line := range lines { if line == "" { continue } buf.WriteString("+") buf.WriteString(line) } case diffmatchpatch.DiffDelete: lines := strings.SplitAfter(text, "\n") for _, line := range lines { if line == "" { continue } buf.WriteString("-") buf.WriteString(line) } case diffmatchpatch.DiffEqual: lines := strings.SplitAfter(text, "\n") for _, line := range lines { if line == "" { continue } buf.WriteString(" ") buf.WriteString(line) } } } return buf.Bytes() }, }, { Name: "godebug", Diff: func(x, y []byte) []byte { // This function is not exactly creating a unified diff, but it's close enough to be // comparable. return []byte(godebug.Diff(string(x), string(y))) }, }, { Name: "mb0", Diff: func(x, y []byte) []byte { // This function is not exactly creating a unified diff, but it's close enough to be // comparable. d := mb0lines{ x: bytes.SplitAfter(x, []byte("\n")), y: bytes.SplitAfter(y, []byte("\n")), } changes := mb0.Diff(len(d.x), len(d.y), d) var buf bytes.Buffer a, b := 0, 0 for _, ch := range changes { for a < ch.A { buf.WriteString(" ") buf.Write(d.x[a]) a++ b++ } for i := range ch.Del { buf.WriteString("-") buf.Write(d.x[ch.A+i]) a++ } for i := range ch.Ins { buf.WriteString("+") buf.Write(d.y[ch.B+i]) b++ } } for a < len(d.x) { buf.WriteString(" ") buf.Write(d.x[a]) a++ } return buf.Bytes() }, }, { Name: "udiff", Diff: func(x, y []byte) []byte { return []byte(udiff.Unified("x", "y", string(x), string(y))) }, }, } type mb0lines struct { x [][]byte y [][]byte } func (d mb0lines) Equal(i, j int) bool { return bytes.Equal(d.x[i], d.y[j]) } diff-1.0.1/internal/benchmarks/testdata/000077500000000000000000000000001516001707200201625ustar00rootroot00000000000000diff-1.0.1/internal/benchmarks/testdata/large_01.test000066400000000000000000053601271516001707200224730ustar00rootroot00000000000000From https://go.googlesource.com/go commit cedf5008a84d3726f98fac551a4016bf0a91157f file src/cmd/compile/internal/ssa/rewriteARM64.go -- x -- // Code generated from _gen/ARM64.rules using 'go generate'; DO NOT EDIT. package ssa import "cmd/compile/internal/types" func rewriteValueARM64(v *Value) bool { switch v.Op { case OpARM64ADCSflags: return rewriteValueARM64_OpARM64ADCSflags(v) case OpARM64ADD: return rewriteValueARM64_OpARM64ADD(v) case OpARM64ADDSflags: return rewriteValueARM64_OpARM64ADDSflags(v) case OpARM64ADDconst: return rewriteValueARM64_OpARM64ADDconst(v) case OpARM64ADDshiftLL: return rewriteValueARM64_OpARM64ADDshiftLL(v) case OpARM64ADDshiftRA: return rewriteValueARM64_OpARM64ADDshiftRA(v) case OpARM64ADDshiftRL: return rewriteValueARM64_OpARM64ADDshiftRL(v) case OpARM64AND: return rewriteValueARM64_OpARM64AND(v) case OpARM64ANDconst: return rewriteValueARM64_OpARM64ANDconst(v) case OpARM64ANDshiftLL: return rewriteValueARM64_OpARM64ANDshiftLL(v) case OpARM64ANDshiftRA: return rewriteValueARM64_OpARM64ANDshiftRA(v) case OpARM64ANDshiftRL: return rewriteValueARM64_OpARM64ANDshiftRL(v) case OpARM64ANDshiftRO: return rewriteValueARM64_OpARM64ANDshiftRO(v) case OpARM64BIC: return rewriteValueARM64_OpARM64BIC(v) case OpARM64BICshiftLL: return rewriteValueARM64_OpARM64BICshiftLL(v) case OpARM64BICshiftRA: return rewriteValueARM64_OpARM64BICshiftRA(v) case OpARM64BICshiftRL: return rewriteValueARM64_OpARM64BICshiftRL(v) case OpARM64BICshiftRO: return rewriteValueARM64_OpARM64BICshiftRO(v) case OpARM64CMN: return rewriteValueARM64_OpARM64CMN(v) case OpARM64CMNW: return rewriteValueARM64_OpARM64CMNW(v) case OpARM64CMNWconst: return rewriteValueARM64_OpARM64CMNWconst(v) case OpARM64CMNconst: return rewriteValueARM64_OpARM64CMNconst(v) case OpARM64CMNshiftLL: return rewriteValueARM64_OpARM64CMNshiftLL(v) case OpARM64CMNshiftRA: return rewriteValueARM64_OpARM64CMNshiftRA(v) case OpARM64CMNshiftRL: return rewriteValueARM64_OpARM64CMNshiftRL(v) case OpARM64CMP: return rewriteValueARM64_OpARM64CMP(v) case OpARM64CMPW: return rewriteValueARM64_OpARM64CMPW(v) case OpARM64CMPWconst: return rewriteValueARM64_OpARM64CMPWconst(v) case OpARM64CMPconst: return rewriteValueARM64_OpARM64CMPconst(v) case OpARM64CMPshiftLL: return rewriteValueARM64_OpARM64CMPshiftLL(v) case OpARM64CMPshiftRA: return rewriteValueARM64_OpARM64CMPshiftRA(v) case OpARM64CMPshiftRL: return rewriteValueARM64_OpARM64CMPshiftRL(v) case OpARM64CSEL: return rewriteValueARM64_OpARM64CSEL(v) case OpARM64CSEL0: return rewriteValueARM64_OpARM64CSEL0(v) case OpARM64CSETM: return rewriteValueARM64_OpARM64CSETM(v) case OpARM64CSINC: return rewriteValueARM64_OpARM64CSINC(v) case OpARM64CSINV: return rewriteValueARM64_OpARM64CSINV(v) case OpARM64CSNEG: return rewriteValueARM64_OpARM64CSNEG(v) case OpARM64DIV: return rewriteValueARM64_OpARM64DIV(v) case OpARM64DIVW: return rewriteValueARM64_OpARM64DIVW(v) case OpARM64EON: return rewriteValueARM64_OpARM64EON(v) case OpARM64EONshiftLL: return rewriteValueARM64_OpARM64EONshiftLL(v) case OpARM64EONshiftRA: return rewriteValueARM64_OpARM64EONshiftRA(v) case OpARM64EONshiftRL: return rewriteValueARM64_OpARM64EONshiftRL(v) case OpARM64EONshiftRO: return rewriteValueARM64_OpARM64EONshiftRO(v) case OpARM64Equal: return rewriteValueARM64_OpARM64Equal(v) case OpARM64FADDD: return rewriteValueARM64_OpARM64FADDD(v) case OpARM64FADDS: return rewriteValueARM64_OpARM64FADDS(v) case OpARM64FCMPD: return rewriteValueARM64_OpARM64FCMPD(v) case OpARM64FCMPS: return rewriteValueARM64_OpARM64FCMPS(v) case OpARM64FMOVDfpgp: return rewriteValueARM64_OpARM64FMOVDfpgp(v) case OpARM64FMOVDgpfp: return rewriteValueARM64_OpARM64FMOVDgpfp(v) case OpARM64FMOVDload: return rewriteValueARM64_OpARM64FMOVDload(v) case OpARM64FMOVDloadidx: return rewriteValueARM64_OpARM64FMOVDloadidx(v) case OpARM64FMOVDloadidx8: return rewriteValueARM64_OpARM64FMOVDloadidx8(v) case OpARM64FMOVDstore: return rewriteValueARM64_OpARM64FMOVDstore(v) case OpARM64FMOVDstoreidx: return rewriteValueARM64_OpARM64FMOVDstoreidx(v) case OpARM64FMOVDstoreidx8: return rewriteValueARM64_OpARM64FMOVDstoreidx8(v) case OpARM64FMOVSload: return rewriteValueARM64_OpARM64FMOVSload(v) case OpARM64FMOVSloadidx: return rewriteValueARM64_OpARM64FMOVSloadidx(v) case OpARM64FMOVSloadidx4: return rewriteValueARM64_OpARM64FMOVSloadidx4(v) case OpARM64FMOVSstore: return rewriteValueARM64_OpARM64FMOVSstore(v) case OpARM64FMOVSstoreidx: return rewriteValueARM64_OpARM64FMOVSstoreidx(v) case OpARM64FMOVSstoreidx4: return rewriteValueARM64_OpARM64FMOVSstoreidx4(v) case OpARM64FMULD: return rewriteValueARM64_OpARM64FMULD(v) case OpARM64FMULS: return rewriteValueARM64_OpARM64FMULS(v) case OpARM64FNEGD: return rewriteValueARM64_OpARM64FNEGD(v) case OpARM64FNEGS: return rewriteValueARM64_OpARM64FNEGS(v) case OpARM64FNMULD: return rewriteValueARM64_OpARM64FNMULD(v) case OpARM64FNMULS: return rewriteValueARM64_OpARM64FNMULS(v) case OpARM64FSUBD: return rewriteValueARM64_OpARM64FSUBD(v) case OpARM64FSUBS: return rewriteValueARM64_OpARM64FSUBS(v) case OpARM64GreaterEqual: return rewriteValueARM64_OpARM64GreaterEqual(v) case OpARM64GreaterEqualF: return rewriteValueARM64_OpARM64GreaterEqualF(v) case OpARM64GreaterEqualU: return rewriteValueARM64_OpARM64GreaterEqualU(v) case OpARM64GreaterThan: return rewriteValueARM64_OpARM64GreaterThan(v) case OpARM64GreaterThanF: return rewriteValueARM64_OpARM64GreaterThanF(v) case OpARM64GreaterThanU: return rewriteValueARM64_OpARM64GreaterThanU(v) case OpARM64LDP: return rewriteValueARM64_OpARM64LDP(v) case OpARM64LessEqual: return rewriteValueARM64_OpARM64LessEqual(v) case OpARM64LessEqualF: return rewriteValueARM64_OpARM64LessEqualF(v) case OpARM64LessEqualU: return rewriteValueARM64_OpARM64LessEqualU(v) case OpARM64LessThan: return rewriteValueARM64_OpARM64LessThan(v) case OpARM64LessThanF: return rewriteValueARM64_OpARM64LessThanF(v) case OpARM64LessThanU: return rewriteValueARM64_OpARM64LessThanU(v) case OpARM64MADD: return rewriteValueARM64_OpARM64MADD(v) case OpARM64MADDW: return rewriteValueARM64_OpARM64MADDW(v) case OpARM64MNEG: return rewriteValueARM64_OpARM64MNEG(v) case OpARM64MNEGW: return rewriteValueARM64_OpARM64MNEGW(v) case OpARM64MOD: return rewriteValueARM64_OpARM64MOD(v) case OpARM64MODW: return rewriteValueARM64_OpARM64MODW(v) case OpARM64MOVBUload: return rewriteValueARM64_OpARM64MOVBUload(v) case OpARM64MOVBUloadidx: return rewriteValueARM64_OpARM64MOVBUloadidx(v) case OpARM64MOVBUreg: return rewriteValueARM64_OpARM64MOVBUreg(v) case OpARM64MOVBload: return rewriteValueARM64_OpARM64MOVBload(v) case OpARM64MOVBloadidx: return rewriteValueARM64_OpARM64MOVBloadidx(v) case OpARM64MOVBreg: return rewriteValueARM64_OpARM64MOVBreg(v) case OpARM64MOVBstore: return rewriteValueARM64_OpARM64MOVBstore(v) case OpARM64MOVBstoreidx: return rewriteValueARM64_OpARM64MOVBstoreidx(v) case OpARM64MOVBstorezero: return rewriteValueARM64_OpARM64MOVBstorezero(v) case OpARM64MOVBstorezeroidx: return rewriteValueARM64_OpARM64MOVBstorezeroidx(v) case OpARM64MOVDload: return rewriteValueARM64_OpARM64MOVDload(v) case OpARM64MOVDloadidx: return rewriteValueARM64_OpARM64MOVDloadidx(v) case OpARM64MOVDloadidx8: return rewriteValueARM64_OpARM64MOVDloadidx8(v) case OpARM64MOVDnop: return rewriteValueARM64_OpARM64MOVDnop(v) case OpARM64MOVDreg: return rewriteValueARM64_OpARM64MOVDreg(v) case OpARM64MOVDstore: return rewriteValueARM64_OpARM64MOVDstore(v) case OpARM64MOVDstoreidx: return rewriteValueARM64_OpARM64MOVDstoreidx(v) case OpARM64MOVDstoreidx8: return rewriteValueARM64_OpARM64MOVDstoreidx8(v) case OpARM64MOVDstorezero: return rewriteValueARM64_OpARM64MOVDstorezero(v) case OpARM64MOVDstorezeroidx: return rewriteValueARM64_OpARM64MOVDstorezeroidx(v) case OpARM64MOVDstorezeroidx8: return rewriteValueARM64_OpARM64MOVDstorezeroidx8(v) case OpARM64MOVHUload: return rewriteValueARM64_OpARM64MOVHUload(v) case OpARM64MOVHUloadidx: return rewriteValueARM64_OpARM64MOVHUloadidx(v) case OpARM64MOVHUloadidx2: return rewriteValueARM64_OpARM64MOVHUloadidx2(v) case OpARM64MOVHUreg: return rewriteValueARM64_OpARM64MOVHUreg(v) case OpARM64MOVHload: return rewriteValueARM64_OpARM64MOVHload(v) case OpARM64MOVHloadidx: return rewriteValueARM64_OpARM64MOVHloadidx(v) case OpARM64MOVHloadidx2: return rewriteValueARM64_OpARM64MOVHloadidx2(v) case OpARM64MOVHreg: return rewriteValueARM64_OpARM64MOVHreg(v) case OpARM64MOVHstore: return rewriteValueARM64_OpARM64MOVHstore(v) case OpARM64MOVHstoreidx: return rewriteValueARM64_OpARM64MOVHstoreidx(v) case OpARM64MOVHstoreidx2: return rewriteValueARM64_OpARM64MOVHstoreidx2(v) case OpARM64MOVHstorezero: return rewriteValueARM64_OpARM64MOVHstorezero(v) case OpARM64MOVHstorezeroidx: return rewriteValueARM64_OpARM64MOVHstorezeroidx(v) case OpARM64MOVHstorezeroidx2: return rewriteValueARM64_OpARM64MOVHstorezeroidx2(v) case OpARM64MOVQstorezero: return rewriteValueARM64_OpARM64MOVQstorezero(v) case OpARM64MOVWUload: return rewriteValueARM64_OpARM64MOVWUload(v) case OpARM64MOVWUloadidx: return rewriteValueARM64_OpARM64MOVWUloadidx(v) case OpARM64MOVWUloadidx4: return rewriteValueARM64_OpARM64MOVWUloadidx4(v) case OpARM64MOVWUreg: return rewriteValueARM64_OpARM64MOVWUreg(v) case OpARM64MOVWload: return rewriteValueARM64_OpARM64MOVWload(v) case OpARM64MOVWloadidx: return rewriteValueARM64_OpARM64MOVWloadidx(v) case OpARM64MOVWloadidx4: return rewriteValueARM64_OpARM64MOVWloadidx4(v) case OpARM64MOVWreg: return rewriteValueARM64_OpARM64MOVWreg(v) case OpARM64MOVWstore: return rewriteValueARM64_OpARM64MOVWstore(v) case OpARM64MOVWstoreidx: return rewriteValueARM64_OpARM64MOVWstoreidx(v) case OpARM64MOVWstoreidx4: return rewriteValueARM64_OpARM64MOVWstoreidx4(v) case OpARM64MOVWstorezero: return rewriteValueARM64_OpARM64MOVWstorezero(v) case OpARM64MOVWstorezeroidx: return rewriteValueARM64_OpARM64MOVWstorezeroidx(v) case OpARM64MOVWstorezeroidx4: return rewriteValueARM64_OpARM64MOVWstorezeroidx4(v) case OpARM64MSUB: return rewriteValueARM64_OpARM64MSUB(v) case OpARM64MSUBW: return rewriteValueARM64_OpARM64MSUBW(v) case OpARM64MUL: return rewriteValueARM64_OpARM64MUL(v) case OpARM64MULW: return rewriteValueARM64_OpARM64MULW(v) case OpARM64MVN: return rewriteValueARM64_OpARM64MVN(v) case OpARM64MVNshiftLL: return rewriteValueARM64_OpARM64MVNshiftLL(v) case OpARM64MVNshiftRA: return rewriteValueARM64_OpARM64MVNshiftRA(v) case OpARM64MVNshiftRL: return rewriteValueARM64_OpARM64MVNshiftRL(v) case OpARM64MVNshiftRO: return rewriteValueARM64_OpARM64MVNshiftRO(v) case OpARM64NEG: return rewriteValueARM64_OpARM64NEG(v) case OpARM64NEGshiftLL: return rewriteValueARM64_OpARM64NEGshiftLL(v) case OpARM64NEGshiftRA: return rewriteValueARM64_OpARM64NEGshiftRA(v) case OpARM64NEGshiftRL: return rewriteValueARM64_OpARM64NEGshiftRL(v) case OpARM64NotEqual: return rewriteValueARM64_OpARM64NotEqual(v) case OpARM64OR: return rewriteValueARM64_OpARM64OR(v) case OpARM64ORN: return rewriteValueARM64_OpARM64ORN(v) case OpARM64ORNshiftLL: return rewriteValueARM64_OpARM64ORNshiftLL(v) case OpARM64ORNshiftRA: return rewriteValueARM64_OpARM64ORNshiftRA(v) case OpARM64ORNshiftRL: return rewriteValueARM64_OpARM64ORNshiftRL(v) case OpARM64ORNshiftRO: return rewriteValueARM64_OpARM64ORNshiftRO(v) case OpARM64ORconst: return rewriteValueARM64_OpARM64ORconst(v) case OpARM64ORshiftLL: return rewriteValueARM64_OpARM64ORshiftLL(v) case OpARM64ORshiftRA: return rewriteValueARM64_OpARM64ORshiftRA(v) case OpARM64ORshiftRL: return rewriteValueARM64_OpARM64ORshiftRL(v) case OpARM64ORshiftRO: return rewriteValueARM64_OpARM64ORshiftRO(v) case OpARM64REV: return rewriteValueARM64_OpARM64REV(v) case OpARM64REVW: return rewriteValueARM64_OpARM64REVW(v) case OpARM64ROR: return rewriteValueARM64_OpARM64ROR(v) case OpARM64RORW: return rewriteValueARM64_OpARM64RORW(v) case OpARM64SBCSflags: return rewriteValueARM64_OpARM64SBCSflags(v) case OpARM64SLL: return rewriteValueARM64_OpARM64SLL(v) case OpARM64SLLconst: return rewriteValueARM64_OpARM64SLLconst(v) case OpARM64SRA: return rewriteValueARM64_OpARM64SRA(v) case OpARM64SRAconst: return rewriteValueARM64_OpARM64SRAconst(v) case OpARM64SRL: return rewriteValueARM64_OpARM64SRL(v) case OpARM64SRLconst: return rewriteValueARM64_OpARM64SRLconst(v) case OpARM64STP: return rewriteValueARM64_OpARM64STP(v) case OpARM64SUB: return rewriteValueARM64_OpARM64SUB(v) case OpARM64SUBconst: return rewriteValueARM64_OpARM64SUBconst(v) case OpARM64SUBshiftLL: return rewriteValueARM64_OpARM64SUBshiftLL(v) case OpARM64SUBshiftRA: return rewriteValueARM64_OpARM64SUBshiftRA(v) case OpARM64SUBshiftRL: return rewriteValueARM64_OpARM64SUBshiftRL(v) case OpARM64TST: return rewriteValueARM64_OpARM64TST(v) case OpARM64TSTW: return rewriteValueARM64_OpARM64TSTW(v) case OpARM64TSTWconst: return rewriteValueARM64_OpARM64TSTWconst(v) case OpARM64TSTconst: return rewriteValueARM64_OpARM64TSTconst(v) case OpARM64TSTshiftLL: return rewriteValueARM64_OpARM64TSTshiftLL(v) case OpARM64TSTshiftRA: return rewriteValueARM64_OpARM64TSTshiftRA(v) case OpARM64TSTshiftRL: return rewriteValueARM64_OpARM64TSTshiftRL(v) case OpARM64TSTshiftRO: return rewriteValueARM64_OpARM64TSTshiftRO(v) case OpARM64UBFIZ: return rewriteValueARM64_OpARM64UBFIZ(v) case OpARM64UBFX: return rewriteValueARM64_OpARM64UBFX(v) case OpARM64UDIV: return rewriteValueARM64_OpARM64UDIV(v) case OpARM64UDIVW: return rewriteValueARM64_OpARM64UDIVW(v) case OpARM64UMOD: return rewriteValueARM64_OpARM64UMOD(v) case OpARM64UMODW: return rewriteValueARM64_OpARM64UMODW(v) case OpARM64XOR: return rewriteValueARM64_OpARM64XOR(v) case OpARM64XORconst: return rewriteValueARM64_OpARM64XORconst(v) case OpARM64XORshiftLL: return rewriteValueARM64_OpARM64XORshiftLL(v) case OpARM64XORshiftRA: return rewriteValueARM64_OpARM64XORshiftRA(v) case OpARM64XORshiftRL: return rewriteValueARM64_OpARM64XORshiftRL(v) case OpARM64XORshiftRO: return rewriteValueARM64_OpARM64XORshiftRO(v) case OpAbs: v.Op = OpARM64FABSD return true case OpAdd16: v.Op = OpARM64ADD return true case OpAdd32: v.Op = OpARM64ADD return true case OpAdd32F: v.Op = OpARM64FADDS return true case OpAdd64: v.Op = OpARM64ADD return true case OpAdd64F: v.Op = OpARM64FADDD return true case OpAdd8: v.Op = OpARM64ADD return true case OpAddPtr: v.Op = OpARM64ADD return true case OpAddr: return rewriteValueARM64_OpAddr(v) case OpAnd16: v.Op = OpARM64AND return true case OpAnd32: v.Op = OpARM64AND return true case OpAnd64: v.Op = OpARM64AND return true case OpAnd8: v.Op = OpARM64AND return true case OpAndB: v.Op = OpARM64AND return true case OpAtomicAdd32: v.Op = OpARM64LoweredAtomicAdd32 return true case OpAtomicAdd32Variant: v.Op = OpARM64LoweredAtomicAdd32Variant return true case OpAtomicAdd64: v.Op = OpARM64LoweredAtomicAdd64 return true case OpAtomicAdd64Variant: v.Op = OpARM64LoweredAtomicAdd64Variant return true case OpAtomicAnd32: return rewriteValueARM64_OpAtomicAnd32(v) case OpAtomicAnd32Variant: return rewriteValueARM64_OpAtomicAnd32Variant(v) case OpAtomicAnd8: return rewriteValueARM64_OpAtomicAnd8(v) case OpAtomicAnd8Variant: return rewriteValueARM64_OpAtomicAnd8Variant(v) case OpAtomicCompareAndSwap32: v.Op = OpARM64LoweredAtomicCas32 return true case OpAtomicCompareAndSwap32Variant: v.Op = OpARM64LoweredAtomicCas32Variant return true case OpAtomicCompareAndSwap64: v.Op = OpARM64LoweredAtomicCas64 return true case OpAtomicCompareAndSwap64Variant: v.Op = OpARM64LoweredAtomicCas64Variant return true case OpAtomicExchange32: v.Op = OpARM64LoweredAtomicExchange32 return true case OpAtomicExchange32Variant: v.Op = OpARM64LoweredAtomicExchange32Variant return true case OpAtomicExchange64: v.Op = OpARM64LoweredAtomicExchange64 return true case OpAtomicExchange64Variant: v.Op = OpARM64LoweredAtomicExchange64Variant return true case OpAtomicLoad32: v.Op = OpARM64LDARW return true case OpAtomicLoad64: v.Op = OpARM64LDAR return true case OpAtomicLoad8: v.Op = OpARM64LDARB return true case OpAtomicLoadPtr: v.Op = OpARM64LDAR return true case OpAtomicOr32: return rewriteValueARM64_OpAtomicOr32(v) case OpAtomicOr32Variant: return rewriteValueARM64_OpAtomicOr32Variant(v) case OpAtomicOr8: return rewriteValueARM64_OpAtomicOr8(v) case OpAtomicOr8Variant: return rewriteValueARM64_OpAtomicOr8Variant(v) case OpAtomicStore32: v.Op = OpARM64STLRW return true case OpAtomicStore64: v.Op = OpARM64STLR return true case OpAtomicStore8: v.Op = OpARM64STLRB return true case OpAtomicStorePtrNoWB: v.Op = OpARM64STLR return true case OpAvg64u: return rewriteValueARM64_OpAvg64u(v) case OpBitLen32: return rewriteValueARM64_OpBitLen32(v) case OpBitLen64: return rewriteValueARM64_OpBitLen64(v) case OpBitRev16: return rewriteValueARM64_OpBitRev16(v) case OpBitRev32: v.Op = OpARM64RBITW return true case OpBitRev64: v.Op = OpARM64RBIT return true case OpBitRev8: return rewriteValueARM64_OpBitRev8(v) case OpBswap32: v.Op = OpARM64REVW return true case OpBswap64: v.Op = OpARM64REV return true case OpCeil: v.Op = OpARM64FRINTPD return true case OpClosureCall: v.Op = OpARM64CALLclosure return true case OpCom16: v.Op = OpARM64MVN return true case OpCom32: v.Op = OpARM64MVN return true case OpCom64: v.Op = OpARM64MVN return true case OpCom8: v.Op = OpARM64MVN return true case OpCondSelect: return rewriteValueARM64_OpCondSelect(v) case OpConst16: return rewriteValueARM64_OpConst16(v) case OpConst32: return rewriteValueARM64_OpConst32(v) case OpConst32F: return rewriteValueARM64_OpConst32F(v) case OpConst64: return rewriteValueARM64_OpConst64(v) case OpConst64F: return rewriteValueARM64_OpConst64F(v) case OpConst8: return rewriteValueARM64_OpConst8(v) case OpConstBool: return rewriteValueARM64_OpConstBool(v) case OpConstNil: return rewriteValueARM64_OpConstNil(v) case OpCtz16: return rewriteValueARM64_OpCtz16(v) case OpCtz16NonZero: v.Op = OpCtz32 return true case OpCtz32: return rewriteValueARM64_OpCtz32(v) case OpCtz32NonZero: v.Op = OpCtz32 return true case OpCtz64: return rewriteValueARM64_OpCtz64(v) case OpCtz64NonZero: v.Op = OpCtz64 return true case OpCtz8: return rewriteValueARM64_OpCtz8(v) case OpCtz8NonZero: v.Op = OpCtz32 return true case OpCvt32Fto32: v.Op = OpARM64FCVTZSSW return true case OpCvt32Fto32U: v.Op = OpARM64FCVTZUSW return true case OpCvt32Fto64: v.Op = OpARM64FCVTZSS return true case OpCvt32Fto64F: v.Op = OpARM64FCVTSD return true case OpCvt32Fto64U: v.Op = OpARM64FCVTZUS return true case OpCvt32Uto32F: v.Op = OpARM64UCVTFWS return true case OpCvt32Uto64F: v.Op = OpARM64UCVTFWD return true case OpCvt32to32F: v.Op = OpARM64SCVTFWS return true case OpCvt32to64F: v.Op = OpARM64SCVTFWD return true case OpCvt64Fto32: v.Op = OpARM64FCVTZSDW return true case OpCvt64Fto32F: v.Op = OpARM64FCVTDS return true case OpCvt64Fto32U: v.Op = OpARM64FCVTZUDW return true case OpCvt64Fto64: v.Op = OpARM64FCVTZSD return true case OpCvt64Fto64U: v.Op = OpARM64FCVTZUD return true case OpCvt64Uto32F: v.Op = OpARM64UCVTFS return true case OpCvt64Uto64F: v.Op = OpARM64UCVTFD return true case OpCvt64to32F: v.Op = OpARM64SCVTFS return true case OpCvt64to64F: v.Op = OpARM64SCVTFD return true case OpCvtBoolToUint8: v.Op = OpCopy return true case OpDiv16: return rewriteValueARM64_OpDiv16(v) case OpDiv16u: return rewriteValueARM64_OpDiv16u(v) case OpDiv32: return rewriteValueARM64_OpDiv32(v) case OpDiv32F: v.Op = OpARM64FDIVS return true case OpDiv32u: v.Op = OpARM64UDIVW return true case OpDiv64: return rewriteValueARM64_OpDiv64(v) case OpDiv64F: v.Op = OpARM64FDIVD return true case OpDiv64u: v.Op = OpARM64UDIV return true case OpDiv8: return rewriteValueARM64_OpDiv8(v) case OpDiv8u: return rewriteValueARM64_OpDiv8u(v) case OpEq16: return rewriteValueARM64_OpEq16(v) case OpEq32: return rewriteValueARM64_OpEq32(v) case OpEq32F: return rewriteValueARM64_OpEq32F(v) case OpEq64: return rewriteValueARM64_OpEq64(v) case OpEq64F: return rewriteValueARM64_OpEq64F(v) case OpEq8: return rewriteValueARM64_OpEq8(v) case OpEqB: return rewriteValueARM64_OpEqB(v) case OpEqPtr: return rewriteValueARM64_OpEqPtr(v) case OpFMA: return rewriteValueARM64_OpFMA(v) case OpFloor: v.Op = OpARM64FRINTMD return true case OpGetCallerPC: v.Op = OpARM64LoweredGetCallerPC return true case OpGetCallerSP: v.Op = OpARM64LoweredGetCallerSP return true case OpGetClosurePtr: v.Op = OpARM64LoweredGetClosurePtr return true case OpHmul32: return rewriteValueARM64_OpHmul32(v) case OpHmul32u: return rewriteValueARM64_OpHmul32u(v) case OpHmul64: v.Op = OpARM64MULH return true case OpHmul64u: v.Op = OpARM64UMULH return true case OpInterCall: v.Op = OpARM64CALLinter return true case OpIsInBounds: return rewriteValueARM64_OpIsInBounds(v) case OpIsNonNil: return rewriteValueARM64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueARM64_OpIsSliceInBounds(v) case OpLeq16: return rewriteValueARM64_OpLeq16(v) case OpLeq16U: return rewriteValueARM64_OpLeq16U(v) case OpLeq32: return rewriteValueARM64_OpLeq32(v) case OpLeq32F: return rewriteValueARM64_OpLeq32F(v) case OpLeq32U: return rewriteValueARM64_OpLeq32U(v) case OpLeq64: return rewriteValueARM64_OpLeq64(v) case OpLeq64F: return rewriteValueARM64_OpLeq64F(v) case OpLeq64U: return rewriteValueARM64_OpLeq64U(v) case OpLeq8: return rewriteValueARM64_OpLeq8(v) case OpLeq8U: return rewriteValueARM64_OpLeq8U(v) case OpLess16: return rewriteValueARM64_OpLess16(v) case OpLess16U: return rewriteValueARM64_OpLess16U(v) case OpLess32: return rewriteValueARM64_OpLess32(v) case OpLess32F: return rewriteValueARM64_OpLess32F(v) case OpLess32U: return rewriteValueARM64_OpLess32U(v) case OpLess64: return rewriteValueARM64_OpLess64(v) case OpLess64F: return rewriteValueARM64_OpLess64F(v) case OpLess64U: return rewriteValueARM64_OpLess64U(v) case OpLess8: return rewriteValueARM64_OpLess8(v) case OpLess8U: return rewriteValueARM64_OpLess8U(v) case OpLoad: return rewriteValueARM64_OpLoad(v) case OpLocalAddr: return rewriteValueARM64_OpLocalAddr(v) case OpLsh16x16: return rewriteValueARM64_OpLsh16x16(v) case OpLsh16x32: return rewriteValueARM64_OpLsh16x32(v) case OpLsh16x64: return rewriteValueARM64_OpLsh16x64(v) case OpLsh16x8: return rewriteValueARM64_OpLsh16x8(v) case OpLsh32x16: return rewriteValueARM64_OpLsh32x16(v) case OpLsh32x32: return rewriteValueARM64_OpLsh32x32(v) case OpLsh32x64: return rewriteValueARM64_OpLsh32x64(v) case OpLsh32x8: return rewriteValueARM64_OpLsh32x8(v) case OpLsh64x16: return rewriteValueARM64_OpLsh64x16(v) case OpLsh64x32: return rewriteValueARM64_OpLsh64x32(v) case OpLsh64x64: return rewriteValueARM64_OpLsh64x64(v) case OpLsh64x8: return rewriteValueARM64_OpLsh64x8(v) case OpLsh8x16: return rewriteValueARM64_OpLsh8x16(v) case OpLsh8x32: return rewriteValueARM64_OpLsh8x32(v) case OpLsh8x64: return rewriteValueARM64_OpLsh8x64(v) case OpLsh8x8: return rewriteValueARM64_OpLsh8x8(v) case OpMod16: return rewriteValueARM64_OpMod16(v) case OpMod16u: return rewriteValueARM64_OpMod16u(v) case OpMod32: return rewriteValueARM64_OpMod32(v) case OpMod32u: v.Op = OpARM64UMODW return true case OpMod64: return rewriteValueARM64_OpMod64(v) case OpMod64u: v.Op = OpARM64UMOD return true case OpMod8: return rewriteValueARM64_OpMod8(v) case OpMod8u: return rewriteValueARM64_OpMod8u(v) case OpMove: return rewriteValueARM64_OpMove(v) case OpMul16: v.Op = OpARM64MULW return true case OpMul32: v.Op = OpARM64MULW return true case OpMul32F: v.Op = OpARM64FMULS return true case OpMul64: v.Op = OpARM64MUL return true case OpMul64F: v.Op = OpARM64FMULD return true case OpMul8: v.Op = OpARM64MULW return true case OpNeg16: v.Op = OpARM64NEG return true case OpNeg32: v.Op = OpARM64NEG return true case OpNeg32F: v.Op = OpARM64FNEGS return true case OpNeg64: v.Op = OpARM64NEG return true case OpNeg64F: v.Op = OpARM64FNEGD return true case OpNeg8: v.Op = OpARM64NEG return true case OpNeq16: return rewriteValueARM64_OpNeq16(v) case OpNeq32: return rewriteValueARM64_OpNeq32(v) case OpNeq32F: return rewriteValueARM64_OpNeq32F(v) case OpNeq64: return rewriteValueARM64_OpNeq64(v) case OpNeq64F: return rewriteValueARM64_OpNeq64F(v) case OpNeq8: return rewriteValueARM64_OpNeq8(v) case OpNeqB: v.Op = OpARM64XOR return true case OpNeqPtr: return rewriteValueARM64_OpNeqPtr(v) case OpNilCheck: v.Op = OpARM64LoweredNilCheck return true case OpNot: return rewriteValueARM64_OpNot(v) case OpOffPtr: return rewriteValueARM64_OpOffPtr(v) case OpOr16: v.Op = OpARM64OR return true case OpOr32: v.Op = OpARM64OR return true case OpOr64: v.Op = OpARM64OR return true case OpOr8: v.Op = OpARM64OR return true case OpOrB: v.Op = OpARM64OR return true case OpPanicBounds: return rewriteValueARM64_OpPanicBounds(v) case OpPopCount16: return rewriteValueARM64_OpPopCount16(v) case OpPopCount32: return rewriteValueARM64_OpPopCount32(v) case OpPopCount64: return rewriteValueARM64_OpPopCount64(v) case OpPrefetchCache: return rewriteValueARM64_OpPrefetchCache(v) case OpPrefetchCacheStreamed: return rewriteValueARM64_OpPrefetchCacheStreamed(v) case OpPubBarrier: return rewriteValueARM64_OpPubBarrier(v) case OpRotateLeft16: return rewriteValueARM64_OpRotateLeft16(v) case OpRotateLeft32: return rewriteValueARM64_OpRotateLeft32(v) case OpRotateLeft64: return rewriteValueARM64_OpRotateLeft64(v) case OpRotateLeft8: return rewriteValueARM64_OpRotateLeft8(v) case OpRound: v.Op = OpARM64FRINTAD return true case OpRound32F: v.Op = OpARM64LoweredRound32F return true case OpRound64F: v.Op = OpARM64LoweredRound64F return true case OpRoundToEven: v.Op = OpARM64FRINTND return true case OpRsh16Ux16: return rewriteValueARM64_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValueARM64_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValueARM64_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValueARM64_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValueARM64_OpRsh16x16(v) case OpRsh16x32: return rewriteValueARM64_OpRsh16x32(v) case OpRsh16x64: return rewriteValueARM64_OpRsh16x64(v) case OpRsh16x8: return rewriteValueARM64_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValueARM64_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValueARM64_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValueARM64_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValueARM64_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValueARM64_OpRsh32x16(v) case OpRsh32x32: return rewriteValueARM64_OpRsh32x32(v) case OpRsh32x64: return rewriteValueARM64_OpRsh32x64(v) case OpRsh32x8: return rewriteValueARM64_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValueARM64_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValueARM64_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValueARM64_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValueARM64_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValueARM64_OpRsh64x16(v) case OpRsh64x32: return rewriteValueARM64_OpRsh64x32(v) case OpRsh64x64: return rewriteValueARM64_OpRsh64x64(v) case OpRsh64x8: return rewriteValueARM64_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValueARM64_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValueARM64_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValueARM64_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValueARM64_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValueARM64_OpRsh8x16(v) case OpRsh8x32: return rewriteValueARM64_OpRsh8x32(v) case OpRsh8x64: return rewriteValueARM64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueARM64_OpRsh8x8(v) case OpSelect0: return rewriteValueARM64_OpSelect0(v) case OpSelect1: return rewriteValueARM64_OpSelect1(v) case OpSelectN: return rewriteValueARM64_OpSelectN(v) case OpSignExt16to32: v.Op = OpARM64MOVHreg return true case OpSignExt16to64: v.Op = OpARM64MOVHreg return true case OpSignExt32to64: v.Op = OpARM64MOVWreg return true case OpSignExt8to16: v.Op = OpARM64MOVBreg return true case OpSignExt8to32: v.Op = OpARM64MOVBreg return true case OpSignExt8to64: v.Op = OpARM64MOVBreg return true case OpSlicemask: return rewriteValueARM64_OpSlicemask(v) case OpSqrt: v.Op = OpARM64FSQRTD return true case OpSqrt32: v.Op = OpARM64FSQRTS return true case OpStaticCall: v.Op = OpARM64CALLstatic return true case OpStore: return rewriteValueARM64_OpStore(v) case OpSub16: v.Op = OpARM64SUB return true case OpSub32: v.Op = OpARM64SUB return true case OpSub32F: v.Op = OpARM64FSUBS return true case OpSub64: v.Op = OpARM64SUB return true case OpSub64F: v.Op = OpARM64FSUBD return true case OpSub8: v.Op = OpARM64SUB return true case OpSubPtr: v.Op = OpARM64SUB return true case OpTailCall: v.Op = OpARM64CALLtail return true case OpTrunc: v.Op = OpARM64FRINTZD return true case OpTrunc16to8: v.Op = OpCopy return true case OpTrunc32to16: v.Op = OpCopy return true case OpTrunc32to8: v.Op = OpCopy return true case OpTrunc64to16: v.Op = OpCopy return true case OpTrunc64to32: v.Op = OpCopy return true case OpTrunc64to8: v.Op = OpCopy return true case OpWB: v.Op = OpARM64LoweredWB return true case OpXor16: v.Op = OpARM64XOR return true case OpXor32: v.Op = OpARM64XOR return true case OpXor64: v.Op = OpARM64XOR return true case OpXor8: v.Op = OpARM64XOR return true case OpZero: return rewriteValueARM64_OpZero(v) case OpZeroExt16to32: v.Op = OpARM64MOVHUreg return true case OpZeroExt16to64: v.Op = OpARM64MOVHUreg return true case OpZeroExt32to64: v.Op = OpARM64MOVWUreg return true case OpZeroExt8to16: v.Op = OpARM64MOVBUreg return true case OpZeroExt8to32: v.Op = OpARM64MOVBUreg return true case OpZeroExt8to64: v.Op = OpARM64MOVBUreg return true } return false } func rewriteValueARM64_OpARM64ADCSflags(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADCSflags x y (Select1 (ADDSconstflags [-1] (ADCzerocarry c)))) // result: (ADCSflags x y c) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64ADDSconstflags || auxIntToInt64(v_2_0.AuxInt) != -1 { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64ADCzerocarry || v_2_0_0.Type != typ.UInt64 { break } c := v_2_0_0.Args[0] v.reset(OpARM64ADCSflags) v.AddArg3(x, y, c) return true } // match: (ADCSflags x y (Select1 (ADDSconstflags [-1] (MOVDconst [0])))) // result: (ADDSflags x y) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64ADDSconstflags || auxIntToInt64(v_2_0.AuxInt) != -1 { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64MOVDconst || auxIntToInt64(v_2_0_0.AuxInt) != 0 { break } v.reset(OpARM64ADDSflags) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64ADD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADD x (MOVDconst [c])) // cond: !t.IsPtr() // result: (ADDconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(!t.IsPtr()) { continue } v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADD a l:(MUL x y)) // cond: l.Uses==1 && clobber(l) // result: (MADD a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MUL { continue } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MADD) v.AddArg3(a, x, y) return true } break } // match: (ADD a l:(MNEG x y)) // cond: l.Uses==1 && clobber(l) // result: (MSUB a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MNEG { continue } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MSUB) v.AddArg3(a, x, y) return true } break } // match: (ADD a l:(MULW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MADDW a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MULW { continue } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MADDW) v.AddArg3(a, x, y) return true } break } // match: (ADD a l:(MNEGW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MSUBW a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MNEGW { continue } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MSUBW) v.AddArg3(a, x, y) return true } break } // match: (ADD x (NEG y)) // result: (SUB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64NEG { continue } y := v_1.Args[0] v.reset(OpARM64SUB) v.AddArg2(x, y) return true } break } // match: (ADD x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ADDshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (ADD x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ADDshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ADDshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (ADD x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ADDshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ADDshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64ADDSflags(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSflags x (MOVDconst [c])) // result: (ADDSconstflags [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ADDSconstflags) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } return false } func rewriteValueARM64_OpARM64ADDconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDconst [off1] (MOVDaddr [off2] {sym} ptr)) // cond: is32Bit(off1+int64(off2)) // result: (MOVDaddr [int32(off1)+off2] {sym} ptr) for { off1 := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) ptr := v_0.Args[0] if !(is32Bit(off1 + int64(off2))) { break } v.reset(OpARM64MOVDaddr) v.AuxInt = int32ToAuxInt(int32(off1) + off2) v.Aux = symToAux(sym) v.AddArg(ptr) return true } // match: (ADDconst [c] y) // cond: c < 0 // result: (SUBconst [-c] y) for { c := auxIntToInt64(v.AuxInt) y := v_0 if !(c < 0) { break } v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(-c) v.AddArg(y) return true } // match: (ADDconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ADDconst [c] (MOVDconst [d])) // result: (MOVDconst [c+d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c + d) return true } // match: (ADDconst [c] (ADDconst [d] x)) // result: (ADDconst [c+d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ADDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDconst [c] (SUBconst [d] x)) // result: (ADDconst [c-d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SUBconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c - d) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ADDshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDshiftLL (MOVDconst [c]) x [d]) // result: (ADDconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftLL x (MOVDconst [c]) [d]) // result: (ADDconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) // result: (REV16W x) for { if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ADDshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff // result: (REV16W x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ADDshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) // result: (REV16 x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { break } v.reset(OpARM64REV16) v.AddArg(x) return true } // match: (ADDshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) // result: (REV16 (ANDconst [0xffffffff] x)) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16) v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) v0.AuxInt = int64ToAuxInt(0xffffffff) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftLL [c] (SRLconst x [64-c]) x2) // result: (EXTRconst [64-c] x2 x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { break } x := v_0.Args[0] x2 := v_1 v.reset(OpARM64EXTRconst) v.AuxInt = int64ToAuxInt(64 - c) v.AddArg2(x2, x) return true } // match: (ADDshiftLL [c] (UBFX [bfc] x) x2) // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) // result: (EXTRWconst [32-c] x2 x) for { t := v.Type c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] x2 := v_1 if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { break } v.reset(OpARM64EXTRWconst) v.AuxInt = int64ToAuxInt(32 - c) v.AddArg2(x2, x) return true } return false } func rewriteValueARM64_OpARM64ADDshiftRA(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ADDshiftRA (MOVDconst [c]) x [d]) // result: (ADDconst [c] (SRAconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftRA x (MOVDconst [c]) [d]) // result: (ADDconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ADDshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ADDshiftRL (MOVDconst [c]) x [d]) // result: (ADDconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftRL x (MOVDconst [c]) [d]) // result: (ADDconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64AND(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (AND x (MOVDconst [c])) // result: (ANDconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (AND x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (AND x (MVN y)) // result: (BIC x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MVN { continue } y := v_1.Args[0] v.reset(OpARM64BIC) v.AddArg2(x, y) return true } break } // match: (AND x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (AND x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (AND x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (AND x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64ANDconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDconst [0] _) // result: (MOVDconst [0]) for { if auxIntToInt64(v.AuxInt) != 0 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (ANDconst [-1] x) // result: x for { if auxIntToInt64(v.AuxInt) != -1 { break } x := v_0 v.copyOf(x) return true } // match: (ANDconst [c] (MOVDconst [d])) // result: (MOVDconst [c&d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c & d) return true } // match: (ANDconst [c] (ANDconst [d] x)) // result: (ANDconst [c&d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDconst [c] (MOVWUreg x)) // result: (ANDconst [c&(1<<32-1)] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg { break } x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<32 - 1)) v.AddArg(x) return true } // match: (ANDconst [c] (MOVHUreg x)) // result: (ANDconst [c&(1<<16-1)] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg { break } x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<16 - 1)) v.AddArg(x) return true } // match: (ANDconst [c] (MOVBUreg x)) // result: (ANDconst [c&(1<<8-1)] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg { break } x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<8 - 1)) v.AddArg(x) return true } // match: (ANDconst [ac] (SLLconst [sc] x)) // cond: isARM64BFMask(sc, ac, sc) // result: (UBFIZ [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x) for { ac := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(sc, ac, sc)) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc, arm64BFWidth(ac, sc))) v.AddArg(x) return true } // match: (ANDconst [ac] (SRLconst [sc] x)) // cond: isARM64BFMask(sc, ac, 0) // result: (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, 0))] x) for { ac := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(sc, ac, 0)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc, arm64BFWidth(ac, 0))) v.AddArg(x) return true } // match: (ANDconst [c] (UBFX [bfc] x)) // cond: isARM64BFMask(0, c, 0) // result: (UBFX [armBFAuxInt(bfc.getARM64BFlsb(), min(bfc.getARM64BFwidth(), arm64BFWidth(c, 0)))] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(0, c, 0)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb(), min(bfc.getARM64BFwidth(), arm64BFWidth(c, 0)))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ANDshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ANDshiftLL (MOVDconst [c]) x [d]) // result: (ANDconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftLL x (MOVDconst [c]) [d]) // result: (ANDconst x [int64(uint64(c)< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftRA x (MOVDconst [c]) [d]) // result: (ANDconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (ANDshiftRA y:(SRAconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRAconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64ANDshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ANDshiftRL (MOVDconst [c]) x [d]) // result: (ANDconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftRL x (MOVDconst [c]) [d]) // result: (ANDconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (ANDshiftRL y:(SRLconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRLconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64ANDshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ANDshiftRO (MOVDconst [c]) x [d]) // result: (ANDconst [c] (RORconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftRO x (MOVDconst [c]) [d]) // result: (ANDconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } // match: (ANDshiftRO y:(RORconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64RORconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64BIC(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BIC x (MOVDconst [c])) // result: (ANDconst [^c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^c) v.AddArg(x) return true } // match: (BIC x x) // result: (MOVDconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (BIC x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (BIC x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (BIC x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (BIC x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftRO x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64BICshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BICshiftLL x (MOVDconst [c]) [d]) // result: (ANDconst x [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) v.AddArg(x) return true } // match: (BICshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64BICshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BICshiftRL x (MOVDconst [c]) [d]) // result: (ANDconst x [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (BICshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64BICshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BICshiftRO x (MOVDconst [c]) [d]) // result: (ANDconst x [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) v.AddArg(x) return true } // match: (BICshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64CMN(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMN x (MOVDconst [c])) // result: (CMNconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (CMN x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMNshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64CMNshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (CMN x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMNshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64CMNshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (CMN x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (CMNshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64CMNshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64CMNW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMNW x (MOVDconst [c])) // result: (CMNWconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNWconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueARM64_OpARM64CMNWconst(v *Value) bool { v_0 := v.Args[0] // match: (CMNWconst [c] y) // cond: c < 0 && c != -1<<31 // result: (CMPWconst [-c] y) for { c := auxIntToInt32(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<31) { break } v.reset(OpARM64CMPWconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(y) return true } // match: (CMNWconst (MOVDconst [x]) [y]) // result: (FlagConstant [addFlags32(int32(x),y)]) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(addFlags32(int32(x), y)) return true } return false } func rewriteValueARM64_OpARM64CMNconst(v *Value) bool { v_0 := v.Args[0] // match: (CMNconst [c] y) // cond: c < 0 && c != -1<<63 // result: (CMPconst [-c] y) for { c := auxIntToInt64(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<63) { break } v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(-c) v.AddArg(y) return true } // match: (CMNconst (MOVDconst [x]) [y]) // result: (FlagConstant [addFlags64(x,y)]) for { y := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(addFlags64(x, y)) return true } return false } func rewriteValueARM64_OpARM64CMNshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMNshiftLL (MOVDconst [c]) x [d]) // result: (CMNconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMNshiftLL x (MOVDconst [c]) [d]) // result: (CMNconst x [int64(uint64(c)< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMNshiftRA x (MOVDconst [c]) [d]) // result: (CMNconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CMNshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMNshiftRL (MOVDconst [c]) x [d]) // result: (CMNconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMNshiftRL x (MOVDconst [c]) [d]) // result: (CMNconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CMP(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMP x (MOVDconst [c])) // result: (CMPconst [c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (CMP (MOVDconst [c]) x) // result: (InvertFlags (CMPconst [c] x)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMP x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMP y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMP x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMPshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64CMPshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (CMP x0:(SLLconst [c] y) x1) // cond: clobberIfDead(x0) // result: (InvertFlags (CMPshiftLL x1 y [c])) for { x0 := v_0 if x0.Op != OpARM64SLLconst { break } c := auxIntToInt64(x0.AuxInt) y := x0.Args[0] x1 := v_1 if !(clobberIfDead(x0)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPshiftLL, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg2(x1, y) v.AddArg(v0) return true } // match: (CMP x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMPshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64CMPshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (CMP x0:(SRLconst [c] y) x1) // cond: clobberIfDead(x0) // result: (InvertFlags (CMPshiftRL x1 y [c])) for { x0 := v_0 if x0.Op != OpARM64SRLconst { break } c := auxIntToInt64(x0.AuxInt) y := x0.Args[0] x1 := v_1 if !(clobberIfDead(x0)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRL, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg2(x1, y) v.AddArg(v0) return true } // match: (CMP x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (CMPshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64CMPshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (CMP x0:(SRAconst [c] y) x1) // cond: clobberIfDead(x0) // result: (InvertFlags (CMPshiftRA x1 y [c])) for { x0 := v_0 if x0.Op != OpARM64SRAconst { break } c := auxIntToInt64(x0.AuxInt) y := x0.Args[0] x1 := v_1 if !(clobberIfDead(x0)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRA, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg2(x1, y) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64CMPW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPW x (MOVDconst [c])) // result: (CMPWconst [int32(c)] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPWconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } // match: (CMPW (MOVDconst [c]) x) // result: (InvertFlags (CMPWconst [int32(c)] x)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPW x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPW y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64CMPWconst(v *Value) bool { v_0 := v.Args[0] // match: (CMPWconst [c] y) // cond: c < 0 && c != -1<<31 // result: (CMNWconst [-c] y) for { c := auxIntToInt32(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<31) { break } v.reset(OpARM64CMNWconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(y) return true } // match: (CMPWconst (MOVDconst [x]) [y]) // result: (FlagConstant [subFlags32(int32(x),y)]) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags32(int32(x), y)) return true } // match: (CMPWconst (MOVBUreg _) [c]) // cond: 0xff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVBUreg || !(0xff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPWconst (MOVHUreg _) [c]) // cond: 0xffff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVHUreg || !(0xffff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } return false } func rewriteValueARM64_OpARM64CMPconst(v *Value) bool { v_0 := v.Args[0] // match: (CMPconst [c] y) // cond: c < 0 && c != -1<<63 // result: (CMNconst [-c] y) for { c := auxIntToInt64(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<63) { break } v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(-c) v.AddArg(y) return true } // match: (CMPconst (MOVDconst [x]) [y]) // result: (FlagConstant [subFlags64(x,y)]) for { y := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(x, y)) return true } // match: (CMPconst (MOVBUreg _) [c]) // cond: 0xff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg || !(0xff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (MOVHUreg _) [c]) // cond: 0xffff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg || !(0xffff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (MOVWUreg _) [c]) // cond: 0xffffffff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg || !(0xffffffff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (ANDconst _ [m]) [n]) // cond: 0 <= m && m < n // result: (FlagConstant [subFlags64(0,1)]) for { n := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } m := auxIntToInt64(v_0.AuxInt) if !(0 <= m && m < n) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (SRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 63 && (1< x [d]))) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v1 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v1.AuxInt = int64ToAuxInt(d) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (CMPshiftLL x (MOVDconst [c]) [d]) // result: (CMPconst x [int64(uint64(c)< x [d]))) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v1 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v1.AuxInt = int64ToAuxInt(d) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (CMPshiftRA x (MOVDconst [c]) [d]) // result: (CMPconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CMPshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPshiftRL (MOVDconst [c]) x [d]) // result: (InvertFlags (CMPconst [c] (SRLconst x [d]))) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v1 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v1.AuxInt = int64ToAuxInt(d) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (CMPshiftRL x (MOVDconst [c]) [d]) // result: (CMPconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CSEL(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSEL [cc] (MOVDconst [-1]) (MOVDconst [0]) flag) // result: (CSETM [cc] flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != -1 || v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } flag := v_2 v.reset(OpARM64CSETM) v.AuxInt = opToAuxInt(cc) v.AddArg(flag) return true } // match: (CSEL [cc] (MOVDconst [0]) (MOVDconst [-1]) flag) // result: (CSETM [arm64Negate(cc)] flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 0 || v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { break } flag := v_2 v.reset(OpARM64CSETM) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg(flag) return true } // match: (CSEL [cc] x (MOVDconst [0]) flag) // result: (CSEL0 [cc] x flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } flag := v_2 v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(cc) v.AddArg2(x, flag) return true } // match: (CSEL [cc] (MOVDconst [0]) y flag) // result: (CSEL0 [arm64Negate(cc)] y flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 0 { break } y := v_1 flag := v_2 v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg2(y, flag) return true } // match: (CSEL [cc] x (ADDconst [1] a) flag) // result: (CSINC [cc] x a flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } a := v_1.Args[0] flag := v_2 v.reset(OpARM64CSINC) v.AuxInt = opToAuxInt(cc) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] (ADDconst [1] a) x flag) // result: (CSINC [arm64Negate(cc)] x a flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64ADDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } a := v_0.Args[0] x := v_1 flag := v_2 v.reset(OpARM64CSINC) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] x (MVN a) flag) // result: (CSINV [cc] x a flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64MVN { break } a := v_1.Args[0] flag := v_2 v.reset(OpARM64CSINV) v.AuxInt = opToAuxInt(cc) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] (MVN a) x flag) // result: (CSINV [arm64Negate(cc)] x a flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MVN { break } a := v_0.Args[0] x := v_1 flag := v_2 v.reset(OpARM64CSINV) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] x (NEG a) flag) // result: (CSNEG [cc] x a flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64NEG { break } a := v_1.Args[0] flag := v_2 v.reset(OpARM64CSNEG) v.AuxInt = opToAuxInt(cc) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] (NEG a) x flag) // result: (CSNEG [arm64Negate(cc)] x a flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64NEG { break } a := v_0.Args[0] x := v_1 flag := v_2 v.reset(OpARM64CSNEG) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] x y (InvertFlags cmp)) // result: (CSEL [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSEL [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSEL [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: y for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.copyOf(y) return true } // match: (CSEL [cc] x y (CMPWconst [0] boolval)) // cond: cc == OpARM64NotEqual && flagArg(boolval) != nil // result: (CSEL [boolval.Op] x y flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64CMPWconst || auxIntToInt32(v_2.AuxInt) != 0 { break } boolval := v_2.Args[0] if !(cc == OpARM64NotEqual && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(boolval.Op) v.AddArg3(x, y, flagArg(boolval)) return true } // match: (CSEL [cc] x y (CMPWconst [0] boolval)) // cond: cc == OpARM64Equal && flagArg(boolval) != nil // result: (CSEL [arm64Negate(boolval.Op)] x y flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64CMPWconst || auxIntToInt32(v_2.AuxInt) != 0 { break } boolval := v_2.Args[0] if !(cc == OpARM64Equal && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(arm64Negate(boolval.Op)) v.AddArg3(x, y, flagArg(boolval)) return true } return false } func rewriteValueARM64_OpARM64CSEL0(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSEL0 [cc] x (InvertFlags cmp)) // result: (CSEL0 [arm64Invert(cc)] x cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64InvertFlags { break } cmp := v_1.Args[0] v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg2(x, cmp) return true } // match: (CSEL0 [cc] x flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_1 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSEL0 [cc] _ flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (MOVDconst [0]) for { cc := auxIntToOp(v.AuxInt) flag := v_1 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (CSEL0 [cc] x (CMPWconst [0] boolval)) // cond: cc == OpARM64NotEqual && flagArg(boolval) != nil // result: (CSEL0 [boolval.Op] x flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64CMPWconst || auxIntToInt32(v_1.AuxInt) != 0 { break } boolval := v_1.Args[0] if !(cc == OpARM64NotEqual && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(boolval.Op) v.AddArg2(x, flagArg(boolval)) return true } // match: (CSEL0 [cc] x (CMPWconst [0] boolval)) // cond: cc == OpARM64Equal && flagArg(boolval) != nil // result: (CSEL0 [arm64Negate(boolval.Op)] x flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64CMPWconst || auxIntToInt32(v_1.AuxInt) != 0 { break } boolval := v_1.Args[0] if !(cc == OpARM64Equal && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(arm64Negate(boolval.Op)) v.AddArg2(x, flagArg(boolval)) return true } return false } func rewriteValueARM64_OpARM64CSETM(v *Value) bool { v_0 := v.Args[0] // match: (CSETM [cc] (InvertFlags cmp)) // result: (CSETM [arm64Invert(cc)] cmp) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64InvertFlags { break } cmp := v_0.Args[0] v.reset(OpARM64CSETM) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg(cmp) return true } // match: (CSETM [cc] flag) // cond: ccARM64Eval(cc, flag) > 0 // result: (MOVDconst [-1]) for { cc := auxIntToOp(v.AuxInt) flag := v_0 if !(ccARM64Eval(cc, flag) > 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (CSETM [cc] flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (MOVDconst [0]) for { cc := auxIntToOp(v.AuxInt) flag := v_0 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64CSINC(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSINC [cc] x y (InvertFlags cmp)) // result: (CSINC [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSINC) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSINC [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSINC [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (ADDconst [1] y) for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(1) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64CSINV(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSINV [cc] x y (InvertFlags cmp)) // result: (CSINV [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSINV) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSINV [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSINV [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (Not y) for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpNot) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64CSNEG(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSNEG [cc] x y (InvertFlags cmp)) // result: (CSNEG [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSNEG) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSNEG [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSNEG [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (NEG y) for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64NEG) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64DIV(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIV (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [c/d]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c / d) return true } return false } func rewriteValueARM64_OpARM64DIVW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(int32(c)/int32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) / int32(d))) return true } return false } func rewriteValueARM64_OpARM64EON(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EON x (MOVDconst [c])) // result: (XORconst [^c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^c) v.AddArg(x) return true } // match: (EON x x) // result: (MOVDconst [-1]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (EON x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (EON x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (EON x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (EON x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftRO x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64EONshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EONshiftLL x (MOVDconst [c]) [d]) // result: (XORconst x [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) v.AddArg(x) return true } // match: (EONshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64EONshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EONshiftRL x (MOVDconst [c]) [d]) // result: (XORconst x [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (EONshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64EONshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EONshiftRO x (MOVDconst [c]) [d]) // result: (XORconst x [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) v.AddArg(x) return true } // match: (EONshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64Equal(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Equal (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (Equal (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (Equal (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMP x z:(NEG y))) // cond: z.Uses == 1 // result: (Equal (CMN x y)) for { if v_0.Op != OpARM64CMP { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPW x z:(NEG y))) // cond: z.Uses == 1 // result: (Equal (CMNW x y)) for { if v_0.Op != OpARM64CMPW { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (Equal (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (Equal (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (Equal (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (Equal (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (Equal (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (Equal (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.eq())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.eq())) return true } // match: (Equal (InvertFlags x)) // result: (Equal x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64Equal) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64FADDD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FADDD a (FMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDD a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FMULD { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMADDD) v.AddArg3(a, x, y) return true } break } // match: (FADDD a (FNMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBD a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FNMULD { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMSUBD) v.AddArg3(a, x, y) return true } break } return false } func rewriteValueARM64_OpARM64FADDS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FADDS a (FMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDS a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FMULS { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMADDS) v.AddArg3(a, x, y) return true } break } // match: (FADDS a (FNMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBS a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FNMULS { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMSUBS) v.AddArg3(a, x, y) return true } break } return false } func rewriteValueARM64_OpARM64FCMPD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (FCMPD x (FMOVDconst [0])) // result: (FCMPD0 x) for { x := v_0 if v_1.Op != OpARM64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != 0 { break } v.reset(OpARM64FCMPD0) v.AddArg(x) return true } // match: (FCMPD (FMOVDconst [0]) x) // result: (InvertFlags (FCMPD0 x)) for { if v_0.Op != OpARM64FMOVDconst || auxIntToFloat64(v_0.AuxInt) != 0 { break } x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64FCMPD0, types.TypeFlags) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64FCMPS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (FCMPS x (FMOVSconst [0])) // result: (FCMPS0 x) for { x := v_0 if v_1.Op != OpARM64FMOVSconst || auxIntToFloat64(v_1.AuxInt) != 0 { break } v.reset(OpARM64FCMPS0) v.AddArg(x) return true } // match: (FCMPS (FMOVSconst [0]) x) // result: (InvertFlags (FCMPS0 x)) for { if v_0.Op != OpARM64FMOVSconst || auxIntToFloat64(v_0.AuxInt) != 0 { break } x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64FCMPS0, types.TypeFlags) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64FMOVDfpgp(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (FMOVDfpgp (Arg [off] {sym})) // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueARM64_OpARM64FMOVDgpfp(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (FMOVDgpfp (Arg [off] {sym})) // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueARM64_OpARM64FMOVDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _)) // result: (FMOVDgpfp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVDgpfp) v.AddArg(val) return true } // match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (FMOVDload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVDloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVDloadidx8 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (FMOVDload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVDloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (FMOVDload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVDloadidx ptr (SLLconst [3] idx) mem) // result: (FMOVDloadidx8 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVDloadidx (SLLconst [3] idx) ptr mem) // result: (FMOVDloadidx8 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64FMOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDloadidx8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDloadidx8 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<3) // result: (FMOVDload ptr [int32(c)<<3] mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 3)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVDstore [off] {sym} ptr (FMOVDgpfp val) mem) // result: (MOVDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVDgpfp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVDstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVDstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVDstoreidx8 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (FMOVDstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (FMOVDstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (FMOVDstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (FMOVDstoreidx ptr (SLLconst [3] idx) val mem) // result: (FMOVDstoreidx8 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64FMOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVDstoreidx (SLLconst [3] idx) ptr val mem) // result: (FMOVDstoreidx8 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64FMOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDstoreidx8(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDstoreidx8 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<3) // result: (FMOVDstore [int32(c)<<3] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 3)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVSload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) // result: (FMOVSgpfp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVSgpfp) v.AddArg(val) return true } // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (FMOVSload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVSloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVSload [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVSloadidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (FMOVSload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVSloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (FMOVSload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVSloadidx ptr (SLLconst [2] idx) mem) // result: (FMOVSloadidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVSloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVSloadidx (SLLconst [2] idx) ptr mem) // result: (FMOVSloadidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64FMOVSloadidx4) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSloadidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSloadidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (FMOVSload ptr [int32(c)<<2] mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVSstore [off] {sym} ptr (FMOVSgpfp val) mem) // result: (MOVWstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVSgpfp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVSstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVSstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVSstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVSstoreidx4 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (FMOVSstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (FMOVSstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (FMOVSstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (FMOVSstoreidx ptr (SLLconst [2] idx) val mem) // result: (FMOVSstoreidx4 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64FMOVSstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVSstoreidx (SLLconst [2] idx) ptr val mem) // result: (FMOVSstoreidx4 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64FMOVSstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSstoreidx4(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSstoreidx4 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<2) // result: (FMOVSstore [int32(c)<<2] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 2)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMULD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMULD (FNEGD x) y) // result: (FNMULD x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGD { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FNMULD) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FMULS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMULS (FNEGS x) y) // result: (FNMULS x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGS { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FNMULS) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FNEGD(v *Value) bool { v_0 := v.Args[0] // match: (FNEGD (FMULD x y)) // result: (FNMULD x y) for { if v_0.Op != OpARM64FMULD { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FNMULD) v.AddArg2(x, y) return true } // match: (FNEGD (FNMULD x y)) // result: (FMULD x y) for { if v_0.Op != OpARM64FNMULD { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FMULD) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64FNEGS(v *Value) bool { v_0 := v.Args[0] // match: (FNEGS (FMULS x y)) // result: (FNMULS x y) for { if v_0.Op != OpARM64FMULS { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FNMULS) v.AddArg2(x, y) return true } // match: (FNEGS (FNMULS x y)) // result: (FMULS x y) for { if v_0.Op != OpARM64FNMULS { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FMULS) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64FNMULD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FNMULD (FNEGD x) y) // result: (FMULD x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGD { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FMULD) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FNMULS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FNMULS (FNEGS x) y) // result: (FMULS x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGS { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FMULS) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FSUBD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FSUBD a (FMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBD a x y) for { a := v_0 if v_1.Op != OpARM64FMULD { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMSUBD) v.AddArg3(a, x, y) return true } // match: (FSUBD (FMULD x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMSUBD a x y) for { if v_0.Op != OpARM64FMULD { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMSUBD) v.AddArg3(a, x, y) return true } // match: (FSUBD a (FNMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDD a x y) for { a := v_0 if v_1.Op != OpARM64FNMULD { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMADDD) v.AddArg3(a, x, y) return true } // match: (FSUBD (FNMULD x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMADDD a x y) for { if v_0.Op != OpARM64FNMULD { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMADDD) v.AddArg3(a, x, y) return true } return false } func rewriteValueARM64_OpARM64FSUBS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FSUBS a (FMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBS a x y) for { a := v_0 if v_1.Op != OpARM64FMULS { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMSUBS) v.AddArg3(a, x, y) return true } // match: (FSUBS (FMULS x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMSUBS a x y) for { if v_0.Op != OpARM64FMULS { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMSUBS) v.AddArg3(a, x, y) return true } // match: (FSUBS a (FNMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDS a x y) for { a := v_0 if v_1.Op != OpARM64FNMULS { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMADDS) v.AddArg3(a, x, y) return true } // match: (FSUBS (FNMULS x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMADDS a x y) for { if v_0.Op != OpARM64FNMULS { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMADDS) v.AddArg3(a, x, y) return true } return false } func rewriteValueARM64_OpARM64GreaterEqual(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (GreaterEqual (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterEqual (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqual (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterEqual (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqual (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqualNoov (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqualNoov (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ge())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ge())) return true } // match: (GreaterEqual (InvertFlags x)) // result: (LessEqual x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessEqual) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterEqualF(v *Value) bool { v_0 := v.Args[0] // match: (GreaterEqualF (InvertFlags x)) // result: (LessEqualF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessEqualF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterEqualU(v *Value) bool { v_0 := v.Args[0] // match: (GreaterEqualU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.uge())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.uge())) return true } // match: (GreaterEqualU (InvertFlags x)) // result: (LessEqualU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessEqualU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterThan(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (GreaterThan (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterThan (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterThan (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterThan (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterThan (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterThan (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterThan (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterThan (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterThan (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.gt())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.gt())) return true } // match: (GreaterThan (InvertFlags x)) // result: (LessThan x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessThan) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterThanF(v *Value) bool { v_0 := v.Args[0] // match: (GreaterThanF (InvertFlags x)) // result: (LessThanF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessThanF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterThanU(v *Value) bool { v_0 := v.Args[0] // match: (GreaterThanU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ugt())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ugt())) return true } // match: (GreaterThanU (InvertFlags x)) // result: (LessThanU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessThanU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LDP(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (LDP [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (LDP [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64LDP) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (LDP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (LDP [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64LDP) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64LessEqual(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (LessEqual (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessEqual (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessEqual (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessEqual (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessEqual (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessEqual (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessEqual (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessEqual (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessEqual (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.le())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.le())) return true } // match: (LessEqual (InvertFlags x)) // result: (GreaterEqual x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterEqual) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessEqualF(v *Value) bool { v_0 := v.Args[0] // match: (LessEqualF (InvertFlags x)) // result: (GreaterEqualF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterEqualF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessEqualU(v *Value) bool { v_0 := v.Args[0] // match: (LessEqualU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ule())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ule())) return true } // match: (LessEqualU (InvertFlags x)) // result: (GreaterEqualU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterEqualU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessThan(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (LessThan (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessThan (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessThan (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessThan (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessThan (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (LessThanNoov (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (LessThanNoov (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.lt())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.lt())) return true } // match: (LessThan (InvertFlags x)) // result: (GreaterThan x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterThan) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessThanF(v *Value) bool { v_0 := v.Args[0] // match: (LessThanF (InvertFlags x)) // result: (GreaterThanF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterThanF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessThanU(v *Value) bool { v_0 := v.Args[0] // match: (LessThanU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ult())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ult())) return true } // match: (LessThanU (InvertFlags x)) // result: (GreaterThanU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterThanU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MADD(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MADD a x (MOVDconst [-1])) // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != -1 { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADD a _ (MOVDconst [0])) // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MADD a x (MOVDconst [1])) // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 1 { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADD a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADD a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [-1]) x) // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { break } x := v_2 v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADD a (MOVDconst [0]) _) // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MADD a (MOVDconst [1]) x) // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } x := v_2 v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADD a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADD a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD (MOVDconst [c]) x y) // result: (ADDconst [c] (MUL x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MADD a (MOVDconst [c]) (MOVDconst [d])) // result: (ADDconst [c*d] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c * d) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MADDW(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MADDW a x (MOVDconst [c])) // cond: int32(c)==-1 // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == -1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADDW a _ (MOVDconst [c])) // cond: int32(c)==0 // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MADDW a x (MOVDconst [c])) // cond: int32(c)==1 // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADDW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADDW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: int32(c)==-1 // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == -1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADDW a (MOVDconst [c]) _) // cond: int32(c)==0 // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: int32(c)==1 // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == 1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW (MOVDconst [c]) x y) // result: (ADDconst [c] (MULW x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MADDW a (MOVDconst [c]) (MOVDconst [d])) // result: (ADDconst [int64(int32(c)*int32(d))] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) * int32(d))) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MNEG(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MNEG x (MOVDconst [-1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { continue } v.copyOf(x) return true } break } // match: (MNEG _ (MOVDconst [0])) // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MNEG x (MOVDconst [1])) // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (NEG (SLLconst [log64(c)] x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c)) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c >= 3 // result: (NEG (ADDshiftLL x x [log64(c-1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c >= 7 // result: (NEG (ADDshiftLL (NEG x) x [log64(c+1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SLLconst [log64(c/3)] (SUBshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (NEG (SLLconst [log64(c/5)] (ADDshiftLL x x [2]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 5)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(2) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SLLconst [log64(c/7)] (SUBshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (NEG (SLLconst [log64(c/9)] (ADDshiftLL x x [3]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 9)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(3) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEG (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [-c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-c * d) return true } break } return false } func rewriteValueARM64_OpARM64MNEGW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MNEGW x (MOVDconst [c])) // cond: int32(c)==-1 // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == -1) { continue } v.copyOf(x) return true } break } // match: (MNEGW _ (MOVDconst [c])) // cond: int32(c)==0 // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: int32(c)==1 // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 1) { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (NEG (SLLconst [log64(c)] x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c)) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c) >= 3 // result: (NEG (ADDshiftLL x x [log64(c-1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c) >= 7 // result: (NEG (ADDshiftLL (NEG x) x [log64(c+1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SLLconst [log64(c/3)] (SUBshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (NEG (SLLconst [log64(c/5)] (ADDshiftLL x x [2]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 5)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(2) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SLLconst [log64(c/7)] (SUBshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (NEG (SLLconst [log64(c/9)] (ADDshiftLL x x [3]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 9)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(3) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEGW (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [-int64(int32(c)*int32(d))]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-int64(int32(c) * int32(d))) return true } break } return false } func rewriteValueARM64_OpARM64MOD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOD (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [c%d]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c % d) return true } return false } func rewriteValueARM64_OpARM64MODW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MODW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(int32(c)%int32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) % int32(d))) return true } return false } func rewriteValueARM64_OpARM64MOVBUload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBUload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBUload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVBUloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBUloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBUload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVBUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read8(sym, int64(off)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read8(sym, int64(off)))) return true } return false } func rewriteValueARM64_OpARM64MOVBUloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBUloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVBUload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBUloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVBUload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBUloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVBUreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVBUreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<8-1)] x) for { if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<8 - 1)) v.AddArg(x) return true } // match: (MOVBUreg (MOVDconst [c])) // result: (MOVDconst [int64(uint8(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint8(c))) return true } // match: (MOVBUreg x:(Equal _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64Equal { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(NotEqual _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64NotEqual { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessThan _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessThan { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessThanU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessThanU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessThanF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessThanF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessEqual _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessEqual { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessEqualU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessEqualU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessEqualF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessEqualF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterThan _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterThan { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterThanU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterThanU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterThanF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterThanF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterEqual _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterEqual { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterEqualU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterEqualU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterEqualF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterEqualF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg (SLLconst [lc] x)) // cond: lc >= 8 // result: (MOVDconst [0]) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) if !(lc >= 8) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVBUreg (SLLconst [lc] x)) // cond: lc < 8 // result: (UBFIZ [armBFAuxInt(lc, 8-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 8) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 8-lc)) v.AddArg(x) return true } // match: (MOVBUreg (SRLconst [rc] x)) // cond: rc < 8 // result: (UBFX [armBFAuxInt(rc, 8)] x) for { if v_0.Op != OpARM64SRLconst { break } rc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(rc < 8) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8)) v.AddArg(x) return true } // match: (MOVBUreg (UBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 8 // result: (UBFX [bfc] x) for { if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 8) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVBloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVBloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVBload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVBload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVBreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVBreg x:(MOVBload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBreg x:(MOVBloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBreg x:(MOVBreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBreg (MOVDconst [c])) // result: (MOVDconst [int64(int8(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int8(c))) return true } // match: (MOVBreg (ANDconst x [c])) // cond: uint64(c) & uint64(0xffffffffffffff80) == 0 // result: (ANDconst x [c]) for { t := v.Type if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(uint64(c)&uint64(0xffffffffffffff80) == 0) { break } v.reset(OpARM64ANDconst) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (MOVBreg (SLLconst [lc] x)) // cond: lc < 8 // result: (SBFIZ [armBFAuxInt(lc, 8-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 8) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 8-lc)) v.AddArg(x) return true } // match: (MOVBreg (SBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 8 // result: (SBFX [bfc] x) for { if v_0.Op != OpARM64SBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 8) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVBstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVBstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [i] {s} ptr0 (SRLconst [8] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] w) x:(MOVBstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { continue } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVBstore [i] {s} ptr0 (UBFX [armBFAuxInt(8, 8)] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 8) { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 8)] w) x:(MOVBstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 8) { continue } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVBstore [i] {s} ptr0 (UBFX [armBFAuxInt(8, 24)] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 24) { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 24)] w) x:(MOVBstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 24) { continue } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVBstore [i] {s} ptr0 (SRLconst [8] (MOVDreg w)) x:(MOVBstore [i-1] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { break } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { continue } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVBstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVBstore [i-1] {s} ptr1 w0:(SRLconst [j-8] w) mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst { break } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] w0 := x.Args[1] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w0 mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst { continue } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w0, mem) return true } break } // match: (MOVBstore [i] {s} ptr0 (UBFX [bfc] w) x:(MOVBstore [i-1] {s} ptr1 w0:(UBFX [bfc2] w) mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && bfc.getARM64BFwidth() == 32 - bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32 - bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb() - 8 && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] w0 := x.Args[1] if w0.Op != OpARM64UBFX { break } bfc2 := auxIntToArm64BitField(w0.AuxInt) if w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && bfc.getARM64BFwidth() == 32-bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32-bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb()-8 && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [bfc] w) x:(MOVBstoreidx ptr1 idx1 w0:(UBFX [bfc2] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && bfc.getARM64BFwidth() == 32 - bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32 - bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb() - 8 && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w0 mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64UBFX { continue } bfc := auxIntToArm64BitField(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64UBFX { continue } bfc2 := auxIntToArm64BitField(w0.AuxInt) if w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && bfc.getARM64BFwidth() == 32-bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32-bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb()-8 && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w0, mem) return true } break } // match: (MOVBstore [i] {s} ptr0 (SRLconst [j] (MOVDreg w)) x:(MOVBstore [i-1] {s} ptr1 w0:(SRLconst [j-8] (MOVDreg w)) mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst { break } j := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { break } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] w0 := x.Args[1] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 { break } w0_0 := w0.Args[0] if w0_0.Op != OpARM64MOVDreg || w != w0_0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] (MOVDreg w)) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w0 mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst { continue } j := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { continue } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 { continue } w0_0 := w0.Args[0] if w0_0.Op != OpARM64MOVDreg || w != w0_0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] w) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] w) x3:(MOVBstore [i-4] {s} ptr (SRLconst [32] w) x4:(MOVBstore [i-5] {s} ptr (SRLconst [40] w) x5:(MOVBstore [i-6] {s} ptr (SRLconst [48] w) x6:(MOVBstore [i-7] {s} ptr (SRLconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVDstore [i-7] {s} ptr (REV w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if ptr != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpARM64MOVBstore || auxIntToInt32(x3.AuxInt) != i-4 || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] if ptr != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpARM64SRLconst || auxIntToInt64(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x4 := x3.Args[2] if x4.Op != OpARM64MOVBstore || auxIntToInt32(x4.AuxInt) != i-5 || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] if ptr != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpARM64SRLconst || auxIntToInt64(x4_1.AuxInt) != 40 || w != x4_1.Args[0] { break } x5 := x4.Args[2] if x5.Op != OpARM64MOVBstore || auxIntToInt32(x5.AuxInt) != i-6 || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] if ptr != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpARM64SRLconst || auxIntToInt64(x5_1.AuxInt) != 48 || w != x5_1.Args[0] { break } x6 := x5.Args[2] if x6.Op != OpARM64MOVBstore || auxIntToInt32(x6.AuxInt) != i-7 || auxToSym(x6.Aux) != s { break } mem := x6.Args[2] if ptr != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpARM64SRLconst || auxIntToInt64(x6_1.AuxInt) != 56 || w != x6_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(i - 7) v.Aux = symToAux(s) v0 := b.NewValue0(x6.Pos, OpARM64REV, typ.UInt64) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [7] {s} p w x0:(MOVBstore [6] {s} p (SRLconst [8] w) x1:(MOVBstore [5] {s} p (SRLconst [16] w) x2:(MOVBstore [4] {s} p (SRLconst [24] w) x3:(MOVBstore [3] {s} p (SRLconst [32] w) x4:(MOVBstore [2] {s} p (SRLconst [40] w) x5:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [48] w) x6:(MOVBstoreidx ptr0 idx0 (SRLconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVDstoreidx ptr0 idx0 (REV w) mem) for { if auxIntToInt32(v.AuxInt) != 7 { break } s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 6 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 5 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != 4 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpARM64MOVBstore || auxIntToInt32(x3.AuxInt) != 3 || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpARM64SRLconst || auxIntToInt64(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x4 := x3.Args[2] if x4.Op != OpARM64MOVBstore || auxIntToInt32(x4.AuxInt) != 2 || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpARM64SRLconst || auxIntToInt64(x4_1.AuxInt) != 40 || w != x4_1.Args[0] { break } x5 := x4.Args[2] if x5.Op != OpARM64MOVBstore || auxIntToInt32(x5.AuxInt) != 1 || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] p1 := x5.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 x5_1 := x5.Args[1] if x5_1.Op != OpARM64SRLconst || auxIntToInt64(x5_1.AuxInt) != 48 || w != x5_1.Args[0] { continue } x6 := x5.Args[2] if x6.Op != OpARM64MOVBstoreidx { continue } mem := x6.Args[3] ptr0 := x6.Args[0] idx0 := x6.Args[1] x6_2 := x6.Args[2] if x6_2.Op != OpARM64SRLconst || auxIntToInt64(x6_2.AuxInt) != 56 || w != x6_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6)) { continue } v.reset(OpARM64MOVDstoreidx) v0 := b.NewValue0(x5.Pos, OpARM64REV, typ.UInt64) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstore [i-2] {s} ptr (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstore [i-3] {s} ptr (UBFX [armBFAuxInt(24, 8)] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVWstore [i-3] {s} ptr (REVW w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if ptr != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64UBFX || auxIntToArm64BitField(x0_1.AuxInt) != armBFAuxInt(8, 24) || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64UBFX || auxIntToArm64BitField(x1_1.AuxInt) != armBFAuxInt(16, 16) || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { break } mem := x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64UBFX || auxIntToArm64BitField(x2_1.AuxInt) != armBFAuxInt(24, 8) || w != x2_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 3) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(24, 8)] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2) // result: (MOVWstoreidx ptr0 idx0 (REVW w) mem) for { if auxIntToInt32(v.AuxInt) != 3 { break } s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 2 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64UBFX || auxIntToArm64BitField(x0_1.AuxInt) != armBFAuxInt(8, 24) || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 x1_1 := x1.Args[1] if x1_1.Op != OpARM64UBFX || auxIntToArm64BitField(x1_1.AuxInt) != armBFAuxInt(16, 16) || w != x1_1.Args[0] { continue } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstoreidx { continue } mem := x2.Args[3] ptr0 := x2.Args[0] idx0 := x2.Args[1] x2_2 := x2.Args[2] if x2_2.Op != OpARM64UBFX || auxIntToArm64BitField(x2_2.AuxInt) != armBFAuxInt(24, 8) || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2)) { continue } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(x1.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] (MOVDreg w)) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] (MOVDreg w)) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVWstore [i-3] {s} ptr (REVW w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if ptr != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 { break } x0_1_0 := x0_1.Args[0] if x0_1_0.Op != OpARM64MOVDreg || w != x0_1_0.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 { break } x1_1_0 := x1_1.Args[0] if x1_1_0.Op != OpARM64MOVDreg || w != x1_1_0.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { break } mem := x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 { break } x2_1_0 := x2_1.Args[0] if x2_1_0.Op != OpARM64MOVDreg || w != x2_1_0.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 3) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] (MOVDreg w)) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] (MOVDreg w)) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] (MOVDreg w)) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2) // result: (MOVWstoreidx ptr0 idx0 (REVW w) mem) for { if auxIntToInt32(v.AuxInt) != 3 { break } s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 2 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 { break } x0_1_0 := x0_1.Args[0] if x0_1_0.Op != OpARM64MOVDreg || w != x0_1_0.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 x1_1 := x1.Args[1] if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 { continue } x1_1_0 := x1_1.Args[0] if x1_1_0.Op != OpARM64MOVDreg || w != x1_1_0.Args[0] { continue } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstoreidx { continue } mem := x2.Args[3] ptr0 := x2.Args[0] idx0 := x2.Args[1] x2_2 := x2.Args[2] if x2_2.Op != OpARM64SRLconst || auxIntToInt64(x2_2.AuxInt) != 24 { continue } x2_2_0 := x2_2.Args[0] if x2_2_0.Op != OpARM64MOVDreg || w != x2_2_0.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2)) { continue } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(x1.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] w) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVWstore [i-3] {s} ptr (REVW w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if ptr != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { break } mem := x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 || w != x2_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 3) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] w) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2) // result: (MOVWstoreidx ptr0 idx0 (REVW w) mem) for { if auxIntToInt32(v.AuxInt) != 3 { break } s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 2 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 x1_1 := x1.Args[1] if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { continue } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstoreidx { continue } mem := x2.Args[3] ptr0 := x2.Args[0] idx0 := x2.Args[1] x2_2 := x2.Args[2] if x2_2.Op != OpARM64SRLconst || auxIntToInt64(x2_2.AuxInt) != 24 || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2)) { continue } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(x1.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if ptr != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpARM64SRLconst || auxIntToInt64(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr1 := v_0_0 idx1 := v_0_1 w := v_1 x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr0 := x.Args[0] idx0 := x.Args[1] x_2 := x.Args[2] if x_2.Op != OpARM64SRLconst || auxIntToInt64(x_2.AuxInt) != 8 || w != x_2.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 8)] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if ptr != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpARM64UBFX || auxIntToArm64BitField(x_1.AuxInt) != armBFAuxInt(8, 8) || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 8)] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr1 := v_0_0 idx1 := v_0_1 w := v_1 x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr0 := x.Args[0] idx0 := x.Args[1] x_2 := x.Args[2] if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 8) || w != x_2.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if ptr != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpARM64SRLconst || auxIntToInt64(x_1.AuxInt) != 8 { break } x_1_0 := x_1.Args[0] if x_1_0.Op != OpARM64MOVDreg || w != x_1_0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] (MOVDreg w)) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr1 := v_0_0 idx1 := v_0_1 w := v_1 x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr0 := x.Args[0] idx0 := x.Args[1] x_2 := x.Args[2] if x_2.Op != OpARM64SRLconst || auxIntToInt64(x_2.AuxInt) != 8 { continue } x_2_0 := x_2.Args[0] if x_2_0.Op != OpARM64MOVDreg || w != x_2_0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 24)] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if ptr != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpARM64UBFX || auxIntToArm64BitField(x_1.AuxInt) != armBFAuxInt(8, 24) || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 24)] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr1 := v_0_0 idx1 := v_0_1 w := v_1 x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr0 := x.Args[0] idx0 := x.Args[1] x_2 := x.Args[2] if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 24) || w != x_2.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } return false } func rewriteValueARM64_OpARM64MOVBstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVBstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVBstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVBstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVBstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVBstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVBstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBstoreidx ptr idx (MOVBreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVBUreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVHreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVHUreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVWreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVWUreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr (ADDconst [1] idx) (SRLconst [8] w) x:(MOVBstoreidx ptr idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstoreidx ptr idx w mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] if v_2.Op != OpARM64SRLconst || auxIntToInt64(v_2.AuxInt) != 8 { break } w := v_2.Args[0] x := v_3 if x.Op != OpARM64MOVBstoreidx { break } mem := x.Args[3] if ptr != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, w, mem) return true } // match: (MOVBstoreidx ptr (ADDconst [3] idx) w x0:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(24, 8)] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVWstoreidx ptr idx (REVW w) mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] w := v_2 x0 := v_3 if x0.Op != OpARM64MOVBstoreidx { break } _ = x0.Args[3] if ptr != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 2 || idx != x0_1.Args[0] { break } x0_2 := x0.Args[2] if x0_2.Op != OpARM64UBFX || auxIntToArm64BitField(x0_2.AuxInt) != armBFAuxInt(8, 24) || w != x0_2.Args[0] { break } x1 := x0.Args[3] if x1.Op != OpARM64MOVBstoreidx { break } _ = x1.Args[3] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] { break } x1_2 := x1.Args[2] if x1_2.Op != OpARM64UBFX || auxIntToArm64BitField(x1_2.AuxInt) != armBFAuxInt(16, 16) || w != x1_2.Args[0] { break } x2 := x1.Args[3] if x2.Op != OpARM64MOVBstoreidx { break } mem := x2.Args[3] if ptr != x2.Args[0] || idx != x2.Args[1] { break } x2_2 := x2.Args[2] if x2_2.Op != OpARM64UBFX || auxIntToArm64BitField(x2_2.AuxInt) != armBFAuxInt(24, 8) || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(v.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg4(ptr, idx, v0, mem) return true } // match: (MOVBstoreidx ptr idx w x0:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr (ADDconst [3] idx) (UBFX [armBFAuxInt(24, 8)] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVWstoreidx ptr idx w mem) for { ptr := v_0 idx := v_1 w := v_2 x0 := v_3 if x0.Op != OpARM64MOVBstoreidx { break } _ = x0.Args[3] if ptr != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 1 || idx != x0_1.Args[0] { break } x0_2 := x0.Args[2] if x0_2.Op != OpARM64UBFX || auxIntToArm64BitField(x0_2.AuxInt) != armBFAuxInt(8, 24) || w != x0_2.Args[0] { break } x1 := x0.Args[3] if x1.Op != OpARM64MOVBstoreidx { break } _ = x1.Args[3] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 2 || idx != x1_1.Args[0] { break } x1_2 := x1.Args[2] if x1_2.Op != OpARM64UBFX || auxIntToArm64BitField(x1_2.AuxInt) != armBFAuxInt(16, 16) || w != x1_2.Args[0] { break } x2 := x1.Args[3] if x2.Op != OpARM64MOVBstoreidx { break } mem := x2.Args[3] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 3 || idx != x2_1.Args[0] { break } x2_2 := x2.Args[2] if x2_2.Op != OpARM64UBFX || auxIntToArm64BitField(x2_2.AuxInt) != armBFAuxInt(24, 8) || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, w, mem) return true } // match: (MOVBstoreidx ptr (ADDconst [1] idx) w x:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(8, 8)] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstoreidx ptr idx (REV16W w) mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] w := v_2 x := v_3 if x.Op != OpARM64MOVBstoreidx { break } mem := x.Args[3] if ptr != x.Args[0] || idx != x.Args[1] { break } x_2 := x.Args[2] if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 8) || w != x_2.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstoreidx) v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg4(ptr, idx, v0, mem) return true } // match: (MOVBstoreidx ptr idx w x:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 8)] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstoreidx ptr idx w mem) for { ptr := v_0 idx := v_1 w := v_2 x := v_3 if x.Op != OpARM64MOVBstoreidx { break } mem := x.Args[3] if ptr != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpARM64ADDconst || auxIntToInt64(x_1.AuxInt) != 1 || idx != x_1.Args[0] { break } x_2 := x.Args[2] if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 8) || w != x_2.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, w, mem) return true } return false } func rewriteValueARM64_OpARM64MOVBstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVBstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBstorezero [i] {s} ptr0 x:(MOVBstorezero [j] {s} ptr1 mem)) // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),1) && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 x := v_1 if x.Op != OpARM64MOVBstorezero { break } j := auxIntToInt32(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] ptr1 := x.Args[0] if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 1) && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) v.Aux = symToAux(s) v.AddArg2(ptr0, mem) return true } // match: (MOVBstorezero [1] {s} (ADD ptr0 idx0) x:(MOVBstorezeroidx ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstorezeroidx ptr1 idx1 mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 x := v_1 if x.Op != OpARM64MOVBstorezeroidx { continue } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstorezeroidx) v.AddArg3(ptr1, idx1, mem) return true } break } return false } func rewriteValueARM64_OpARM64MOVBstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVBstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVBstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVBstorezeroidx ptr (ADDconst [1] idx) x:(MOVBstorezeroidx ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstorezeroidx ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstorezeroidx { break } mem := x.Args[2] if ptr != x.Args[0] || idx != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstorezeroidx) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr val _)) // result: (FMOVDfpgp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVDfpgp) v.AddArg(val) return true } // match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVDload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDloadidx8 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVDload [off] {sym} ptr (MOVDstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVDload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueARM64_OpARM64MOVDloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVDload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVDloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVDload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVDloadidx ptr (SLLconst [3] idx) mem) // result: (MOVDloadidx8 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDloadidx (SLLconst [3] idx) ptr mem) // result: (MOVDloadidx8 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDloadidx ptr idx (MOVDstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVDloadidx8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDloadidx8 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<3) // result: (MOVDload [int32(c)<<3] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 3)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg2(ptr, mem) return true } // match: (MOVDloadidx8 ptr idx (MOVDstorezeroidx8 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDstorezeroidx8 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVDnop(v *Value) bool { v_0 := v.Args[0] // match: (MOVDnop (MOVDconst [c])) // result: (MOVDconst [c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValueARM64_OpARM64MOVDreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVDreg x) // cond: x.Uses == 1 // result: (MOVDnop x) for { x := v_0 if !(x.Uses == 1) { break } v.reset(OpARM64MOVDnop) v.AddArg(x) return true } // match: (MOVDreg (MOVDconst [c])) // result: (MOVDconst [c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValueARM64_OpARM64MOVDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVDstore [off] {sym} ptr (FMOVDfpgp val) mem) // result: (FMOVDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVDfpgp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVDstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVDstoreidx8 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVDstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVDstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVDstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVDstoreidx ptr (SLLconst [3] idx) val mem) // result: (MOVDstoreidx8 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64MOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstoreidx (SLLconst [3] idx) ptr val mem) // result: (MOVDstoreidx8 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVDstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVDstorezeroidx) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstoreidx8(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstoreidx8 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<3) // result: (MOVDstore [int32(c)<<3] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 3)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstoreidx8 ptr idx (MOVDconst [0]) mem) // result: (MOVDstorezeroidx8 ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDstorezero [off] {sym} (ADDshiftLL [3] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDstorezeroidx8 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDstorezero [i] {s} ptr0 x:(MOVDstorezero [j] {s} ptr1 mem)) // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),8) && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVQstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 x := v_1 if x.Op != OpARM64MOVDstorezero { break } j := auxIntToInt32(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] ptr1 := x.Args[0] if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 8) && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) v.Aux = symToAux(s) v.AddArg2(ptr0, mem) return true } // match: (MOVDstorezero [8] {s} p0:(ADD ptr0 idx0) x:(MOVDstorezeroidx ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVQstorezero [0] {s} p0 mem) for { if auxIntToInt32(v.AuxInt) != 8 { break } s := auxToSym(v.Aux) p0 := v_0 if p0.Op != OpARM64ADD { break } _ = p0.Args[1] p0_0 := p0.Args[0] p0_1 := p0.Args[1] for _i0 := 0; _i0 <= 1; _i0, p0_0, p0_1 = _i0+1, p0_1, p0_0 { ptr0 := p0_0 idx0 := p0_1 x := v_1 if x.Op != OpARM64MOVDstorezeroidx { continue } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(0) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } break } // match: (MOVDstorezero [8] {s} p0:(ADDshiftLL [3] ptr0 idx0) x:(MOVDstorezeroidx8 ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVQstorezero [0] {s} p0 mem) for { if auxIntToInt32(v.AuxInt) != 8 { break } s := auxToSym(v.Aux) p0 := v_0 if p0.Op != OpARM64ADDshiftLL || auxIntToInt64(p0.AuxInt) != 3 { break } idx0 := p0.Args[1] ptr0 := p0.Args[0] x := v_1 if x.Op != OpARM64MOVDstorezeroidx8 { break } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(0) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVDstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVDstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVDstorezeroidx ptr (SLLconst [3] idx) mem) // result: (MOVDstorezeroidx8 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDstorezeroidx (SLLconst [3] idx) ptr mem) // result: (MOVDstorezeroidx8 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstorezeroidx8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstorezeroidx8 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<3) // result: (MOVDstorezero [int32(c<<3)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 3)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(c << 3)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHUload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHUload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHUload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHUloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHUloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUload [off] {sym} (ADDshiftLL [1] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHUloadidx2 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVHUload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVHUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueARM64_OpARM64MOVHUloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHUloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVHUload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHUloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVHUload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHUloadidx ptr (SLLconst [1] idx) mem) // result: (MOVHUloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUloadidx ptr (ADD idx idx) mem) // result: (MOVHUloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } mem := v_2 v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUloadidx (ADD idx idx) ptr mem) // result: (MOVHUloadidx2 ptr idx mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 mem := v_2 v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHUloadidx2(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHUloadidx2 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<1) // result: (MOVHUload [int32(c)<<1] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(int32(c) << 1) v.AddArg2(ptr, mem) return true } // match: (MOVHUloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx2 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHUreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVHUreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<16-1)] x) for { if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<16 - 1)) v.AddArg(x) return true } // match: (MOVHUreg (MOVDconst [c])) // result: (MOVDconst [int64(uint16(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint16(c))) return true } // match: (MOVHUreg (SLLconst [lc] x)) // cond: lc >= 16 // result: (MOVDconst [0]) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) if !(lc >= 16) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVHUreg (SLLconst [lc] x)) // cond: lc < 16 // result: (UBFIZ [armBFAuxInt(lc, 16-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 16) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 16-lc)) v.AddArg(x) return true } // match: (MOVHUreg (SRLconst [rc] x)) // cond: rc < 16 // result: (UBFX [armBFAuxInt(rc, 16)] x) for { if v_0.Op != OpARM64SRLconst { break } rc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(rc < 16) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 16)) v.AddArg(x) return true } // match: (MOVHUreg (UBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 16 // result: (UBFX [bfc] x) for { if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 16) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVHload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHload [off] {sym} (ADDshiftLL [1] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHloadidx2 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVHload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVHload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVHload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHloadidx ptr (SLLconst [1] idx) mem) // result: (MOVHloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHloadidx ptr (ADD idx idx) mem) // result: (MOVHloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } mem := v_2 v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHloadidx (ADD idx idx) ptr mem) // result: (MOVHloadidx2 ptr idx mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 mem := v_2 v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHloadidx2(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHloadidx2 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<1) // result: (MOVHload [int32(c)<<1] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(int32(c) << 1) v.AddArg2(ptr, mem) return true } // match: (MOVHloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx2 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVHreg x:(MOVBload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg (MOVDconst [c])) // result: (MOVDconst [int64(int16(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int16(c))) return true } // match: (MOVHreg (ANDconst x [c])) // cond: uint64(c) & uint64(0xffffffffffff8000) == 0 // result: (ANDconst x [c]) for { t := v.Type if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(uint64(c)&uint64(0xffffffffffff8000) == 0) { break } v.reset(OpARM64ANDconst) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (MOVHreg (SLLconst [lc] x)) // cond: lc < 16 // result: (SBFIZ [armBFAuxInt(lc, 16-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 16) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 16-lc)) v.AddArg(x) return true } // match: (MOVHreg (SBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 16 // result: (SBFX [bfc] x) for { if v_0.Op != OpARM64SBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 16) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVHstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVHstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstore [off] {sym} (ADDshiftLL [1] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVHstoreidx2 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVHstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [i] {s} ptr0 (SRLconst [16] w) x:(MOVHstore [i-2] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVWstore [i-2] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [16] w) x:(MOVHstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVWstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { continue } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [16] w) x:(MOVHstoreidx2 ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx2 { break } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg(idx1) v.AddArg4(ptr1, v0, w, mem) return true } // match: (MOVHstore [i] {s} ptr0 (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstore [i-2] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVWstore [i-2] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(16, 16) { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVWstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(16, 16) { continue } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstoreidx2 ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(16, 16) { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx2 { break } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg(idx1) v.AddArg4(ptr1, v0, w, mem) return true } // match: (MOVHstore [i] {s} ptr0 (SRLconst [16] (MOVDreg w)) x:(MOVHstore [i-2] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVWstore [i-2] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { break } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [16] (MOVDreg w)) x:(MOVHstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVWstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { continue } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [16] (MOVDreg w)) x:(MOVHstoreidx2 ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { break } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx2 { break } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg(idx1) v.AddArg4(ptr1, v0, w, mem) return true } // match: (MOVHstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVHstore [i-2] {s} ptr1 w0:(SRLconst [j-16] w) mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVWstore [i-2] {s} ptr0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst { break } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] w0 := x.Args[1] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(ptr0, w0, mem) return true } // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVHstoreidx ptr1 idx1 w0:(SRLconst [j-16] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVWstoreidx ptr1 idx1 w0 mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst { continue } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr1, idx1, w0, mem) return true } break } // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [j] w) x:(MOVHstoreidx2 ptr1 idx1 w0:(SRLconst [j-16] w) mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w0 mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] if v_1.Op != OpARM64SRLconst { break } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx2 { break } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg(idx1) v.AddArg4(ptr1, v0, w0, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVHstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVHstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVHstoreidx ptr (SLLconst [1] idx) val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx ptr (ADD idx idx) val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx (SLLconst [1] idx) ptr val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx (ADD idx idx) ptr val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVHstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVHstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstoreidx ptr idx (MOVHreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr idx (MOVHUreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr idx (MOVWreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr idx (MOVWUreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr (ADDconst [2] idx) (SRLconst [16] w) x:(MOVHstoreidx ptr idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx ptr idx w mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] if v_2.Op != OpARM64SRLconst || auxIntToInt64(v_2.AuxInt) != 16 { break } w := v_2.Args[0] x := v_3 if x.Op != OpARM64MOVHstoreidx { break } mem := x.Args[3] if ptr != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, w, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstoreidx2(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstoreidx2 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<1) // result: (MOVHstore [int32(c)<<1] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(int32(c) << 1) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVDconst [0]) mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVHreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVHUreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVWreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVWUreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVHstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezero [off] {sym} (ADDshiftLL [1] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHstorezeroidx2 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezero [i] {s} ptr0 x:(MOVHstorezero [j] {s} ptr1 mem)) // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),2) && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVWstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 x := v_1 if x.Op != OpARM64MOVHstorezero { break } j := auxIntToInt32(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] ptr1 := x.Args[0] if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 2) && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) v.Aux = symToAux(s) v.AddArg2(ptr0, mem) return true } // match: (MOVHstorezero [2] {s} (ADD ptr0 idx0) x:(MOVHstorezeroidx ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVWstorezeroidx ptr1 idx1 mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 x := v_1 if x.Op != OpARM64MOVHstorezeroidx { continue } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVWstorezeroidx) v.AddArg3(ptr1, idx1, mem) return true } break } // match: (MOVHstorezero [2] {s} (ADDshiftLL [1] ptr0 idx0) x:(MOVHstorezeroidx2 ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVWstorezeroidx ptr1 (SLLconst [1] idx1) mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] x := v_1 if x.Op != OpARM64MOVHstorezeroidx2 { break } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVWstorezeroidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg(idx1) v.AddArg3(ptr1, v0, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVHstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVHstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVHstorezeroidx ptr (SLLconst [1] idx) mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx ptr (ADD idx idx) mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx (SLLconst [1] idx) ptr mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx (ADD idx idx) ptr mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx ptr (ADDconst [2] idx) x:(MOVHstorezeroidx ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstorezeroidx ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstorezeroidx { break } mem := x.Args[2] if ptr != x.Args[0] || idx != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVWstorezeroidx) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstorezeroidx2(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstorezeroidx2 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<1) // result: (MOVHstorezero [int32(c<<1)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(c << 1)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVQstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVQstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWUload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWUload [off] {sym} ptr (FMOVSstore [off] {sym} ptr val _)) // result: (FMOVSfpgp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVSfpgp) v.AddArg(val) return true } // match: (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWUload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWUload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWUloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWUloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUload [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWUloadidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWUloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWUload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVWUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueARM64_OpARM64MOVWUloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWUloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVWUload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWUloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVWUload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWUloadidx ptr (SLLconst [2] idx) mem) // result: (MOVWUloadidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWUloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUloadidx (SLLconst [2] idx) ptr mem) // result: (MOVWUloadidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVWUloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWUloadidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWUloadidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (MOVWUload [int32(c)<<2] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg2(ptr, mem) return true } // match: (MOVWUloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx4 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWUreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVWUreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUloadidx4 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUloadidx4 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<32-1)] x) for { if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<32 - 1)) v.AddArg(x) return true } // match: (MOVWUreg (MOVDconst [c])) // result: (MOVDconst [int64(uint32(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint32(c))) return true } // match: (MOVWUreg x) // cond: zeroUpper32Bits(x, 3) // result: x for { x := v_0 if !(zeroUpper32Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVWUreg (SLLconst [lc] x)) // cond: lc >= 32 // result: (MOVDconst [0]) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) if !(lc >= 32) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVWUreg (SLLconst [lc] x)) // cond: lc < 32 // result: (UBFIZ [armBFAuxInt(lc, 32-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 32) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 32-lc)) v.AddArg(x) return true } // match: (MOVWUreg (SRLconst [rc] x)) // cond: rc < 32 // result: (UBFX [armBFAuxInt(rc, 32)] x) for { if v_0.Op != OpARM64SRLconst { break } rc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(rc < 32) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 32)) v.AddArg(x) return true } // match: (MOVWUreg (UBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 32 // result: (UBFX [bfc] x) for { if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 32) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWload [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWloadidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVWload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVWload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWloadidx ptr (SLLconst [2] idx) mem) // result: (MOVWloadidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWloadidx (SLLconst [2] idx) ptr mem) // result: (MOVWloadidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVWloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWloadidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWloadidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (MOVWload [int32(c)<<2] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg2(ptr, mem) return true } // match: (MOVWloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx4 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVWreg x:(MOVBload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHUloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWloadidx4 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWloadidx4 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg (MOVDconst [c])) // result: (MOVDconst [int64(int32(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c))) return true } // match: (MOVWreg (ANDconst x [c])) // cond: uint64(c) & uint64(0xffffffff80000000) == 0 // result: (ANDconst x [c]) for { t := v.Type if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(uint64(c)&uint64(0xffffffff80000000) == 0) { break } v.reset(OpARM64ANDconst) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (MOVWreg (SLLconst [lc] x)) // cond: lc < 32 // result: (SBFIZ [armBFAuxInt(lc, 32-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 32) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 32-lc)) v.AddArg(x) return true } // match: (MOVWreg (SBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 32 // result: (SBFX [bfc] x) for { if v_0.Op != OpARM64SBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 32) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWstore [off] {sym} ptr (FMOVSfpgp val) mem) // result: (FMOVSstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVSfpgp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVWstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVWstoreidx4 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVWstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [i] {s} ptr0 (SRLconst [32] w) x:(MOVWstore [i-4] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVDstore [i-4] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVWstore [4] {s} (ADD ptr0 idx0) (SRLconst [32] w) x:(MOVWstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVDstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 4 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 32 { continue } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVDstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVWstore [4] {s} (ADDshiftLL [2] ptr0 idx0) (SRLconst [32] w) x:(MOVWstoreidx4 ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVDstoreidx ptr1 (SLLconst [2] idx1) w mem) for { if auxIntToInt32(v.AuxInt) != 4 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstoreidx4 { break } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVDstoreidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg(idx1) v.AddArg4(ptr1, v0, w, mem) return true } // match: (MOVWstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVWstore [i-4] {s} ptr1 w0:(SRLconst [j-32] w) mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVDstore [i-4] {s} ptr0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst { break } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] w0 := x.Args[1] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(ptr0, w0, mem) return true } // match: (MOVWstore [4] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVWstoreidx ptr1 idx1 w0:(SRLconst [j-32] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVDstoreidx ptr1 idx1 w0 mem) for { if auxIntToInt32(v.AuxInt) != 4 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst { continue } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVDstoreidx) v.AddArg4(ptr1, idx1, w0, mem) return true } break } // match: (MOVWstore [4] {s} (ADDshiftLL [2] ptr0 idx0) (SRLconst [j] w) x:(MOVWstoreidx4 ptr1 idx1 w0:(SRLconst [j-32] w) mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVDstoreidx ptr1 (SLLconst [2] idx1) w0 mem) for { if auxIntToInt32(v.AuxInt) != 4 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] if v_1.Op != OpARM64SRLconst { break } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstoreidx4 { break } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVDstoreidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg(idx1) v.AddArg4(ptr1, v0, w0, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVWstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVWstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVWstoreidx ptr (SLLconst [2] idx) val mem) // result: (MOVWstoreidx4 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstoreidx (SLLconst [2] idx) ptr val mem) // result: (MOVWstoreidx4 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVWstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVWstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstoreidx ptr idx (MOVWreg x) mem) // result: (MOVWstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVWstoreidx ptr idx (MOVWUreg x) mem) // result: (MOVWstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVWstoreidx ptr (ADDconst [4] idx) (SRLconst [32] w) x:(MOVWstoreidx ptr idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVDstoreidx ptr idx w mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 4 { break } idx := v_1.Args[0] if v_2.Op != OpARM64SRLconst || auxIntToInt64(v_2.AuxInt) != 32 { break } w := v_2.Args[0] x := v_3 if x.Op != OpARM64MOVWstoreidx { break } mem := x.Args[3] if ptr != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVDstoreidx) v.AddArg4(ptr, idx, w, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstoreidx4(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreidx4 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<2) // result: (MOVWstore [int32(c)<<2] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstoreidx4 ptr idx (MOVDconst [0]) mem) // result: (MOVWstorezeroidx4 ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstoreidx4 ptr idx (MOVWreg x) mem) // result: (MOVWstoreidx4 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVWstoreidx4 ptr idx (MOVWUreg x) mem) // result: (MOVWstoreidx4 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstorezero [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWstorezeroidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstorezero [i] {s} ptr0 x:(MOVWstorezero [j] {s} ptr1 mem)) // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),4) && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVDstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 x := v_1 if x.Op != OpARM64MOVWstorezero { break } j := auxIntToInt32(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] ptr1 := x.Args[0] if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 4) && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) v.Aux = symToAux(s) v.AddArg2(ptr0, mem) return true } // match: (MOVWstorezero [4] {s} (ADD ptr0 idx0) x:(MOVWstorezeroidx ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVDstorezeroidx ptr1 idx1 mem) for { if auxIntToInt32(v.AuxInt) != 4 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 x := v_1 if x.Op != OpARM64MOVWstorezeroidx { continue } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVDstorezeroidx) v.AddArg3(ptr1, idx1, mem) return true } break } // match: (MOVWstorezero [4] {s} (ADDshiftLL [2] ptr0 idx0) x:(MOVWstorezeroidx4 ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVDstorezeroidx ptr1 (SLLconst [2] idx1) mem) for { if auxIntToInt32(v.AuxInt) != 4 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] x := v_1 if x.Op != OpARM64MOVWstorezeroidx4 { break } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVDstorezeroidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg(idx1) v.AddArg3(ptr1, v0, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVWstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVWstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVWstorezeroidx ptr (SLLconst [2] idx) mem) // result: (MOVWstorezeroidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstorezeroidx (SLLconst [2] idx) ptr mem) // result: (MOVWstorezeroidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstorezeroidx ptr (ADDconst [4] idx) x:(MOVWstorezeroidx ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVDstorezeroidx ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 4 { break } idx := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstorezeroidx { break } mem := x.Args[2] if ptr != x.Args[0] || idx != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVDstorezeroidx) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstorezeroidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstorezeroidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (MOVWstorezero [int32(c<<2)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(c << 2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MSUB(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MSUB a x (MOVDconst [-1])) // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != -1 { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUB a _ (MOVDconst [0])) // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MSUB a x (MOVDconst [1])) // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 1 { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUB a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUB a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [-1]) x) // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { break } x := v_2 v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUB a (MOVDconst [0]) _) // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MSUB a (MOVDconst [1]) x) // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } x := v_2 v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB (MOVDconst [c]) x y) // result: (ADDconst [c] (MNEG x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MNEG, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MSUB a (MOVDconst [c]) (MOVDconst [d])) // result: (SUBconst [c*d] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(c * d) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MSUBW(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MSUBW a x (MOVDconst [c])) // cond: int32(c)==-1 // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == -1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUBW a _ (MOVDconst [c])) // cond: int32(c)==0 // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: int32(c)==1 // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: int32(c)==-1 // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == -1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUBW a (MOVDconst [c]) _) // cond: int32(c)==0 // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: int32(c)==1 // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == 1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW (MOVDconst [c]) x y) // result: (ADDconst [c] (MNEGW x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MNEGW, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MSUBW a (MOVDconst [c]) (MOVDconst [d])) // result: (SUBconst [int64(int32(c)*int32(d))] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(int64(int32(c) * int32(d))) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MUL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MUL (NEG x) y) // result: (MNEG x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64NEG { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64MNEG) v.AddArg2(x, y) return true } break } // match: (MUL x (MOVDconst [-1])) // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MUL _ (MOVDconst [0])) // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MUL x (MOVDconst [1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { continue } v.copyOf(x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SLLconst [log64(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c >= 3 // result: (ADDshiftLL x x [log64(c-1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c - 1)) v.AddArg2(x, x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c >= 7 // result: (ADDshiftLL (NEG x) x [log64(c+1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c + 1)) v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v0.AddArg(x) v.AddArg2(v0, x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SLLconst [log64(c/3)] (ADDshiftLL x x [1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (SLLconst [log64(c/5)] (ADDshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SLLconst [log64(c/7)] (ADDshiftLL (NEG x) x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (SLLconst [log64(c/9)] (ADDshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MUL (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c * d) return true } break } return false } func rewriteValueARM64_OpARM64MULW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MULW (NEG x) y) // result: (MNEGW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64NEG { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64MNEGW) v.AddArg2(x, y) return true } break } // match: (MULW x (MOVDconst [c])) // cond: int32(c)==-1 // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == -1) { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MULW _ (MOVDconst [c])) // cond: int32(c)==0 // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: int32(c)==1 // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 1) { continue } v.copyOf(x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SLLconst [log64(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c) >= 3 // result: (ADDshiftLL x x [log64(c-1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c - 1)) v.AddArg2(x, x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c) >= 7 // result: (ADDshiftLL (NEG x) x [log64(c+1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c + 1)) v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v0.AddArg(x) v.AddArg2(v0, x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SLLconst [log64(c/3)] (ADDshiftLL x x [1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (SLLconst [log64(c/5)] (ADDshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SLLconst [log64(c/7)] (ADDshiftLL (NEG x) x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (SLLconst [log64(c/9)] (ADDshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MULW (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [int64(int32(c)*int32(d))]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) * int32(d))) return true } break } return false } func rewriteValueARM64_OpARM64MVN(v *Value) bool { v_0 := v.Args[0] // match: (MVN (XOR x y)) // result: (EON x y) for { if v_0.Op != OpARM64XOR { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64EON) v.AddArg2(x, y) return true } // match: (MVN (MOVDconst [c])) // result: (MOVDconst [^c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^c) return true } // match: (MVN x:(SLLconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftLL [c] y) for { x := v_0 if x.Op != OpARM64SLLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (MVN x:(SRLconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftRL [c] y) for { x := v_0 if x.Op != OpARM64SRLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (MVN x:(SRAconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftRA [c] y) for { x := v_0 if x.Op != OpARM64SRAconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (MVN x:(RORconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftRO [c] y) for { x := v_0 if x.Op != OpARM64RORconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64MVNshiftLL(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftLL (MOVDconst [c]) [d]) // result: (MOVDconst [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64MVNshiftRL(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftRL (MOVDconst [c]) [d]) // result: (MOVDconst [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64MVNshiftRO(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftRO (MOVDconst [c]) [d]) // result: (MOVDconst [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) return true } return false } func rewriteValueARM64_OpARM64NEG(v *Value) bool { v_0 := v.Args[0] // match: (NEG (MUL x y)) // result: (MNEG x y) for { if v_0.Op != OpARM64MUL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MNEG) v.AddArg2(x, y) return true } // match: (NEG (MULW x y)) // result: (MNEGW x y) for { if v_0.Op != OpARM64MULW { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MNEGW) v.AddArg2(x, y) return true } // match: (NEG (NEG x)) // result: x for { if v_0.Op != OpARM64NEG { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEG (MOVDconst [c])) // result: (MOVDconst [-c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-c) return true } // match: (NEG x:(SLLconst [c] y)) // cond: clobberIfDead(x) // result: (NEGshiftLL [c] y) for { x := v_0 if x.Op != OpARM64SLLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64NEGshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (NEG x:(SRLconst [c] y)) // cond: clobberIfDead(x) // result: (NEGshiftRL [c] y) for { x := v_0 if x.Op != OpARM64SRLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64NEGshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (NEG x:(SRAconst [c] y)) // cond: clobberIfDead(x) // result: (NEGshiftRA [c] y) for { x := v_0 if x.Op != OpARM64SRAconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64NEGshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64NEGshiftLL(v *Value) bool { v_0 := v.Args[0] // match: (NEGshiftLL (MOVDconst [c]) [d]) // result: (MOVDconst [-int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-(c >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64NEGshiftRL(v *Value) bool { v_0 := v.Args[0] // match: (NEGshiftRL (MOVDconst [c]) [d]) // result: (MOVDconst [-int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-int64(uint64(c) >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64NotEqual(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (NotEqual (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (NotEqual (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (NotEqual (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMP x z:(NEG y))) // cond: z.Uses == 1 // result: (NotEqual (CMN x y)) for { if v_0.Op != OpARM64CMP { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPW x z:(NEG y))) // cond: z.Uses == 1 // result: (NotEqual (CMNW x y)) for { if v_0.Op != OpARM64CMPW { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (NotEqual (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (NotEqual (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ne())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ne())) return true } // match: (NotEqual (InvertFlags x)) // result: (NotEqual x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64NotEqual) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64OR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (OR x (MOVDconst [c])) // result: (ORconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (OR x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (OR x (MVN y)) // result: (ORN x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MVN { continue } y := v_1.Args[0] v.reset(OpARM64ORN) v.AddArg2(x, y) return true } break } // match: (OR x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR (UBFIZ [bfc] x) (ANDconst [ac] y)) // cond: ac == ^((1< o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [i3] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i1] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i0] {s} p mem))) // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUload {s} (OffPtr [int64(i0)] p) mem) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] s0 := o1.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload { continue } i3 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o1.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { continue } i2 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y2 := o0.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { continue } i1 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { continue } y3 := v_1 if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload { continue } i0 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3) v0 := b.NewValue0(x3.Pos, OpARM64MOVWUload, t) v.copyOf(v0) v0.Aux = symToAux(s) v1 := b.NewValue0(x3.Pos, OpOffPtr, p.Type) v1.AuxInt = int64ToAuxInt(int64(i0)) v1.AddArg(p) v0.AddArg2(v1, mem) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [3] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr0 idx0 mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUloadidx ptr0 idx0 mem) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] s0 := o1.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload || auxIntToInt32(x0.AuxInt) != 3 { continue } s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o1.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 2 || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y2 := o0.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 1 || auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] p1 := x2.Args[0] if p1.Op != OpARM64ADD { continue } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x2.Args[1] { continue } y3 := v_1 if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { continue } _ = x3.Args[2] ptr0 := x3.Args[0] idx0 := x3.Args[1] if mem != x3.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3) v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) v.copyOf(v0) v0.AddArg3(ptr0, idx0, mem) return true } } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr idx mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUloadidx ptr idx mem) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] s0 := o1.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { continue } mem := x0.Args[2] ptr := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 3 { continue } idx := x0_1.Args[0] y1 := o1.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { continue } _ = x1.Args[2] if ptr != x1.Args[0] { continue } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 2 || idx != x1_1.Args[0] || mem != x1.Args[2] { continue } y2 := o0.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { continue } _ = x2.Args[2] if ptr != x2.Args[0] { continue } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 1 || idx != x2_1.Args[0] || mem != x2.Args[2] { continue } y3 := v_1 if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { continue } _ = x3.Args[2] if ptr != x3.Args[0] || idx != x3.Args[1] || mem != x3.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3) v0 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) v.copyOf(v0) v0.AddArg3(ptr, idx, mem) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUload [i7] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i6] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i4] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i3] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [i2] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [i1] {s} p mem))) y7:(MOVDnop x7:(MOVBUload [i0] {s} p mem))) // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} (OffPtr [int64(i0)] p) mem) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { continue } _ = o2.Args[1] o3 := o2.Args[0] if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { continue } _ = o3.Args[1] o4 := o3.Args[0] if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { continue } _ = o4.Args[1] o5 := o4.Args[0] if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { continue } _ = o5.Args[1] s0 := o5.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload { continue } i7 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o5.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { continue } i6 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y2 := o4.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { continue } i5 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { continue } y3 := o3.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload { continue } i4 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { continue } y4 := o2.Args[1] if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload { continue } i3 := auxIntToInt32(x4.AuxInt) if auxToSym(x4.Aux) != s { continue } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { continue } y5 := o1.Args[1] if y5.Op != OpARM64MOVDnop { continue } x5 := y5.Args[0] if x5.Op != OpARM64MOVBUload { continue } i2 := auxIntToInt32(x5.AuxInt) if auxToSym(x5.Aux) != s { continue } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { continue } y6 := o0.Args[1] if y6.Op != OpARM64MOVDnop { continue } x6 := y6.Args[0] if x6.Op != OpARM64MOVBUload { continue } i1 := auxIntToInt32(x6.AuxInt) if auxToSym(x6.Aux) != s { continue } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { continue } y7 := v_1 if y7.Op != OpARM64MOVDnop { continue } x7 := y7.Args[0] if x7.Op != OpARM64MOVBUload { continue } i0 := auxIntToInt32(x7.AuxInt) if auxToSym(x7.Aux) != s { continue } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpARM64MOVDload, t) v.copyOf(v0) v0.Aux = symToAux(s) v1 := b.NewValue0(x7.Pos, OpOffPtr, p.Type) v1.AuxInt = int64ToAuxInt(int64(i0)) v1.AddArg(p) v0.AddArg2(v1, mem) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUload [7] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [6] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [4] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [3] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [2] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y7:(MOVDnop x7:(MOVBUloadidx ptr0 idx0 mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDloadidx ptr0 idx0 mem) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { continue } _ = o2.Args[1] o3 := o2.Args[0] if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { continue } _ = o3.Args[1] o4 := o3.Args[0] if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { continue } _ = o4.Args[1] o5 := o4.Args[0] if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { continue } _ = o5.Args[1] s0 := o5.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload || auxIntToInt32(x0.AuxInt) != 7 { continue } s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o5.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 6 || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y2 := o4.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 5 || auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { continue } y3 := o3.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 4 || auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { continue } y4 := o2.Args[1] if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 3 || auxToSym(x4.Aux) != s { continue } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { continue } y5 := o1.Args[1] if y5.Op != OpARM64MOVDnop { continue } x5 := y5.Args[0] if x5.Op != OpARM64MOVBUload || auxIntToInt32(x5.AuxInt) != 2 || auxToSym(x5.Aux) != s { continue } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { continue } y6 := o0.Args[1] if y6.Op != OpARM64MOVDnop { continue } x6 := y6.Args[0] if x6.Op != OpARM64MOVBUload || auxIntToInt32(x6.AuxInt) != 1 || auxToSym(x6.Aux) != s { continue } _ = x6.Args[1] p1 := x6.Args[0] if p1.Op != OpARM64ADD { continue } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x6.Args[1] { continue } y7 := v_1 if y7.Op != OpARM64MOVDnop { continue } x7 := y7.Args[0] if x7.Op != OpARM64MOVBUloadidx { continue } _ = x7.Args[2] ptr0 := x7.Args[0] idx0 := x7.Args[1] if mem != x7.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpARM64MOVDloadidx, t) v.copyOf(v0) v0.AddArg3(ptr0, idx0, mem) return true } } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [7] idx) mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [6] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [5] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [4] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y5:(MOVDnop x5:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y6:(MOVDnop x6:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y7:(MOVDnop x7:(MOVBUloadidx ptr idx mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDloadidx ptr idx mem) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { continue } _ = o2.Args[1] o3 := o2.Args[0] if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { continue } _ = o3.Args[1] o4 := o3.Args[0] if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { continue } _ = o4.Args[1] o5 := o4.Args[0] if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { continue } _ = o5.Args[1] s0 := o5.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { continue } mem := x0.Args[2] ptr := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 7 { continue } idx := x0_1.Args[0] y1 := o5.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { continue } _ = x1.Args[2] if ptr != x1.Args[0] { continue } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 6 || idx != x1_1.Args[0] || mem != x1.Args[2] { continue } y2 := o4.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { continue } _ = x2.Args[2] if ptr != x2.Args[0] { continue } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 5 || idx != x2_1.Args[0] || mem != x2.Args[2] { continue } y3 := o3.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { continue } _ = x3.Args[2] if ptr != x3.Args[0] { continue } x3_1 := x3.Args[1] if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 4 || idx != x3_1.Args[0] || mem != x3.Args[2] { continue } y4 := o2.Args[1] if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUloadidx { continue } _ = x4.Args[2] if ptr != x4.Args[0] { continue } x4_1 := x4.Args[1] if x4_1.Op != OpARM64ADDconst || auxIntToInt64(x4_1.AuxInt) != 3 || idx != x4_1.Args[0] || mem != x4.Args[2] { continue } y5 := o1.Args[1] if y5.Op != OpARM64MOVDnop { continue } x5 := y5.Args[0] if x5.Op != OpARM64MOVBUloadidx { continue } _ = x5.Args[2] if ptr != x5.Args[0] { continue } x5_1 := x5.Args[1] if x5_1.Op != OpARM64ADDconst || auxIntToInt64(x5_1.AuxInt) != 2 || idx != x5_1.Args[0] || mem != x5.Args[2] { continue } y6 := o0.Args[1] if y6.Op != OpARM64MOVDnop { continue } x6 := y6.Args[0] if x6.Op != OpARM64MOVBUloadidx { continue } _ = x6.Args[2] if ptr != x6.Args[0] { continue } x6_1 := x6.Args[1] if x6_1.Op != OpARM64ADDconst || auxIntToInt64(x6_1.AuxInt) != 1 || idx != x6_1.Args[0] || mem != x6.Args[2] { continue } y7 := v_1 if y7.Op != OpARM64MOVDnop { continue } x7 := y7.Args[0] if x7.Op != OpARM64MOVBUloadidx { continue } _ = x7.Args[2] if ptr != x7.Args[0] || idx != x7.Args[1] || mem != x7.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) v.copyOf(v0) v0.AddArg3(ptr, idx, mem) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [i0] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i3] {s} p mem))) // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) // result: @mergePoint(b,x0,x1,x2,x3) (REVW (MOVWUload {s} (OffPtr [int64(i0)] p) mem)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] s0 := o1.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o1.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y2 := o0.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { continue } i2 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { continue } y3 := v_1 if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload { continue } i3 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3) v0 := b.NewValue0(x3.Pos, OpARM64REVW, t) v.copyOf(v0) v1 := b.NewValue0(x3.Pos, OpARM64MOVWUload, t) v1.Aux = symToAux(s) v2 := b.NewValue0(x3.Pos, OpOffPtr, p.Type) v2.AuxInt = int64ToAuxInt(int64(i0)) v2.AddArg(p) v1.AddArg2(v2, mem) v0.AddArg(v1) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr0 idx0 mem))) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [3] {s} p mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) // result: @mergePoint(b,x0,x1,x2,x3) (REVW (MOVWUloadidx ptr0 idx0 mem)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] s0 := o1.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { continue } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := o1.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 { continue } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADD { continue } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x1.Args[1] { continue } y2 := o0.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 2 || auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] p := x2.Args[0] if mem != x2.Args[1] { continue } y3 := v_1 if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 3 || auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3) v0 := b.NewValue0(x3.Pos, OpARM64REVW, t) v.copyOf(v0) v1 := b.NewValue0(x3.Pos, OpARM64MOVWUloadidx, t) v1.AddArg3(ptr0, idx0, mem) v0.AddArg(v1) return true } } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr idx mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) // result: @mergePoint(b,x0,x1,x2,x3) (REVW (MOVWUloadidx ptr idx mem)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] s0 := o1.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { continue } mem := x0.Args[2] ptr := x0.Args[0] idx := x0.Args[1] y1 := o1.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { continue } _ = x1.Args[2] if ptr != x1.Args[0] { continue } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] { continue } y2 := o0.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { continue } _ = x2.Args[2] if ptr != x2.Args[0] { continue } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 2 || idx != x2_1.Args[0] || mem != x2.Args[2] { continue } y3 := v_1 if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { continue } _ = x3.Args[2] if ptr != x3.Args[0] { continue } x3_1 := x3.Args[1] if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 3 || idx != x3_1.Args[0] || mem != x3.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3) v0 := b.NewValue0(v.Pos, OpARM64REVW, t) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) v1.AddArg3(ptr, idx, mem) v0.AddArg(v1) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUload [i0] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i3] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i4] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [i5] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [i6] {s} p mem))) y7:(MOVDnop x7:(MOVBUload [i7] {s} p mem))) // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (REV (MOVDload {s} (OffPtr [int64(i0)] p) mem)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { continue } _ = o2.Args[1] o3 := o2.Args[0] if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { continue } _ = o3.Args[1] o4 := o3.Args[0] if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { continue } _ = o4.Args[1] o5 := o4.Args[0] if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { continue } _ = o5.Args[1] s0 := o5.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o5.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y2 := o4.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { continue } i2 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { continue } y3 := o3.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload { continue } i3 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { continue } y4 := o2.Args[1] if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload { continue } i4 := auxIntToInt32(x4.AuxInt) if auxToSym(x4.Aux) != s { continue } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { continue } y5 := o1.Args[1] if y5.Op != OpARM64MOVDnop { continue } x5 := y5.Args[0] if x5.Op != OpARM64MOVBUload { continue } i5 := auxIntToInt32(x5.AuxInt) if auxToSym(x5.Aux) != s { continue } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { continue } y6 := o0.Args[1] if y6.Op != OpARM64MOVDnop { continue } x6 := y6.Args[0] if x6.Op != OpARM64MOVBUload { continue } i6 := auxIntToInt32(x6.AuxInt) if auxToSym(x6.Aux) != s { continue } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { continue } y7 := v_1 if y7.Op != OpARM64MOVDnop { continue } x7 := y7.Args[0] if x7.Op != OpARM64MOVBUload { continue } i7 := auxIntToInt32(x7.AuxInt) if auxToSym(x7.Aux) != s { continue } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpARM64REV, t) v.copyOf(v0) v1 := b.NewValue0(x7.Pos, OpARM64MOVDload, t) v1.Aux = symToAux(s) v2 := b.NewValue0(x7.Pos, OpOffPtr, p.Type) v2.AuxInt = int64ToAuxInt(int64(i0)) v2.AddArg(p) v1.AddArg2(v2, mem) v0.AddArg(v1) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUloadidx ptr0 idx0 mem))) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [3] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [4] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [5] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [6] {s} p mem))) y7:(MOVDnop x7:(MOVBUload [7] {s} p mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (REV (MOVDloadidx ptr0 idx0 mem)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { continue } _ = o2.Args[1] o3 := o2.Args[0] if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { continue } _ = o3.Args[1] o4 := o3.Args[0] if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { continue } _ = o4.Args[1] o5 := o4.Args[0] if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { continue } _ = o5.Args[1] s0 := o5.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { continue } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := o5.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 { continue } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADD { continue } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x1.Args[1] { continue } y2 := o4.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 2 || auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] p := x2.Args[0] if mem != x2.Args[1] { continue } y3 := o3.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 3 || auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { continue } y4 := o2.Args[1] if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 4 || auxToSym(x4.Aux) != s { continue } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { continue } y5 := o1.Args[1] if y5.Op != OpARM64MOVDnop { continue } x5 := y5.Args[0] if x5.Op != OpARM64MOVBUload || auxIntToInt32(x5.AuxInt) != 5 || auxToSym(x5.Aux) != s { continue } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { continue } y6 := o0.Args[1] if y6.Op != OpARM64MOVDnop { continue } x6 := y6.Args[0] if x6.Op != OpARM64MOVBUload || auxIntToInt32(x6.AuxInt) != 6 || auxToSym(x6.Aux) != s { continue } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { continue } y7 := v_1 if y7.Op != OpARM64MOVDnop { continue } x7 := y7.Args[0] if x7.Op != OpARM64MOVBUload || auxIntToInt32(x7.AuxInt) != 7 || auxToSym(x7.Aux) != s { continue } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpARM64REV, t) v.copyOf(v0) v1 := b.NewValue0(x7.Pos, OpARM64MOVDloadidx, t) v1.AddArg3(ptr0, idx0, mem) v0.AddArg(v1) return true } } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUloadidx ptr idx mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr (ADDconst [4] idx) mem))) y5:(MOVDnop x5:(MOVBUloadidx ptr (ADDconst [5] idx) mem))) y6:(MOVDnop x6:(MOVBUloadidx ptr (ADDconst [6] idx) mem))) y7:(MOVDnop x7:(MOVBUloadidx ptr (ADDconst [7] idx) mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (REV (MOVDloadidx ptr idx mem)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { continue } _ = o2.Args[1] o3 := o2.Args[0] if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { continue } _ = o3.Args[1] o4 := o3.Args[0] if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { continue } _ = o4.Args[1] o5 := o4.Args[0] if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { continue } _ = o5.Args[1] s0 := o5.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { continue } mem := x0.Args[2] ptr := x0.Args[0] idx := x0.Args[1] y1 := o5.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { continue } _ = x1.Args[2] if ptr != x1.Args[0] { continue } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] { continue } y2 := o4.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { continue } _ = x2.Args[2] if ptr != x2.Args[0] { continue } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 2 || idx != x2_1.Args[0] || mem != x2.Args[2] { continue } y3 := o3.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { continue } _ = x3.Args[2] if ptr != x3.Args[0] { continue } x3_1 := x3.Args[1] if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 3 || idx != x3_1.Args[0] || mem != x3.Args[2] { continue } y4 := o2.Args[1] if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUloadidx { continue } _ = x4.Args[2] if ptr != x4.Args[0] { continue } x4_1 := x4.Args[1] if x4_1.Op != OpARM64ADDconst || auxIntToInt64(x4_1.AuxInt) != 4 || idx != x4_1.Args[0] || mem != x4.Args[2] { continue } y5 := o1.Args[1] if y5.Op != OpARM64MOVDnop { continue } x5 := y5.Args[0] if x5.Op != OpARM64MOVBUloadidx { continue } _ = x5.Args[2] if ptr != x5.Args[0] { continue } x5_1 := x5.Args[1] if x5_1.Op != OpARM64ADDconst || auxIntToInt64(x5_1.AuxInt) != 5 || idx != x5_1.Args[0] || mem != x5.Args[2] { continue } y6 := o0.Args[1] if y6.Op != OpARM64MOVDnop { continue } x6 := y6.Args[0] if x6.Op != OpARM64MOVBUloadidx { continue } _ = x6.Args[2] if ptr != x6.Args[0] { continue } x6_1 := x6.Args[1] if x6_1.Op != OpARM64ADDconst || auxIntToInt64(x6_1.AuxInt) != 6 || idx != x6_1.Args[0] || mem != x6.Args[2] { continue } y7 := v_1 if y7.Op != OpARM64MOVDnop { continue } x7 := y7.Args[0] if x7.Op != OpARM64MOVBUloadidx { continue } _ = x7.Args[2] if ptr != x7.Args[0] { continue } x7_1 := x7.Args[1] if x7_1.Op != OpARM64ADDconst || auxIntToInt64(x7_1.AuxInt) != 7 || idx != x7_1.Args[0] || mem != x7.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpARM64REV, t) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) v1.AddArg3(ptr, idx, mem) v0.AddArg(v1) return true } break } return false } func rewriteValueARM64_OpARM64ORN(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ORN x (MOVDconst [c])) // result: (ORconst [^c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^c) v.AddArg(x) return true } // match: (ORN x x) // result: (MOVDconst [-1]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (ORN x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ORNshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64ORNshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (ORN x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ORNshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64ORNshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (ORN x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ORNshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64ORNshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (ORN x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (ORNshiftRO x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64ORNshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64ORNshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ORNshiftLL x (MOVDconst [c]) [d]) // result: (ORconst x [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) v.AddArg(x) return true } // match: (ORNshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64ORNshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ORNshiftRL x (MOVDconst [c]) [d]) // result: (ORconst x [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (ORNshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64ORNshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ORNshiftRO x (MOVDconst [c]) [d]) // result: (ORconst x [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) v.AddArg(x) return true } // match: (ORNshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64ORconst(v *Value) bool { v_0 := v.Args[0] // match: (ORconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ORconst [-1] _) // result: (MOVDconst [-1]) for { if auxIntToInt64(v.AuxInt) != -1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (ORconst [c] (MOVDconst [d])) // result: (MOVDconst [c|d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c | d) return true } // match: (ORconst [c] (ORconst [d] x)) // result: (ORconst [c|d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ORconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORconst [c1] (ANDconst [c2] x)) // cond: c2|c1 == ^0 // result: (ORconst [c1] x) for { c1 := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(c2|c1 == ^0) { break } v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c1) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ORshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ORshiftLL (MOVDconst [c]) x [d]) // result: (ORconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftLL x (MOVDconst [c]) [d]) // result: (ORconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) // result: (REV16W x) for { if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ORshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff // result: (REV16W x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) // result: (REV16 x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { break } v.reset(OpARM64REV16) v.AddArg(x) return true } // match: (ORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) // result: (REV16 (ANDconst [0xffffffff] x)) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16) v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) v0.AuxInt = int64ToAuxInt(0xffffffff) v0.AddArg(x) v.AddArg(v0) return true } // match: ( ORshiftLL [c] (SRLconst x [64-c]) x2) // result: (EXTRconst [64-c] x2 x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { break } x := v_0.Args[0] x2 := v_1 v.reset(OpARM64EXTRconst) v.AuxInt = int64ToAuxInt(64 - c) v.AddArg2(x2, x) return true } // match: ( ORshiftLL [c] (UBFX [bfc] x) x2) // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) // result: (EXTRWconst [32-c] x2 x) for { t := v.Type c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] x2 := v_1 if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { break } v.reset(OpARM64EXTRWconst) v.AuxInt = int64ToAuxInt(32 - c) v.AddArg2(x2, x) return true } // match: (ORshiftLL [sc] (UBFX [bfc] x) (SRLconst [sc] y)) // cond: sc == bfc.getARM64BFwidth() // result: (BFXIL [bfc] y x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != sc { break } y := v_1.Args[0] if !(sc == bfc.getARM64BFwidth()) { break } v.reset(OpARM64BFXIL) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg2(y, x) return true } // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUload [i0] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) // result: @mergePoint(b,x0,x1) (MOVHUload {s} (OffPtr [int64(i0)] p) mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 8 { break } y0 := v_0 if y0.Op != OpARM64MOVDnop { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload { break } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := v_1 if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { break } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpARM64MOVHUload, t) v.copyOf(v0) v0.Aux = symToAux(s) v1 := b.NewValue0(x1.Pos, OpOffPtr, p.Type) v1.AuxInt = int64ToAuxInt(int64(i0)) v1.AddArg(p) v0.AddArg2(v1, mem) return true } // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUloadidx ptr0 idx0 mem)) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1) // result: @mergePoint(b,x0,x1) (MOVHUloadidx ptr0 idx0 mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 8 { break } y0 := v_0 if y0.Op != OpARM64MOVDnop { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { break } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := v_1 if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 { break } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x1.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpARM64MOVHUloadidx, t) v.copyOf(v0) v0.AddArg3(ptr0, idx0, mem) return true } break } // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUloadidx ptr idx mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) // result: @mergePoint(b,x0,x1) (MOVHUloadidx ptr idx mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 8 { break } y0 := v_0 if y0.Op != OpARM64MOVDnop { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { break } mem := x0.Args[2] ptr := x0.Args[0] idx := x0.Args[1] y1 := v_1 if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpARM64MOVHUloadidx, t) v.copyOf(v0) v0.AddArg3(ptr, idx, mem) return true } // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUload [i0] {s} p mem) y1:(MOVDnop x1:(MOVBUload [i2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i3] {s} p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (MOVWUload {s} (OffPtr [int64(i0)] p) mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpARM64MOVHUload { break } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { break } i2 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } y2 := v_1 if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { break } i3 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y1, y2, o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpARM64MOVWUload, t) v.copyOf(v0) v0.Aux = symToAux(s) v1 := b.NewValue0(x2.Pos, OpOffPtr, p.Type) v1.AuxInt = int64ToAuxInt(int64(i0)) v1.AddArg(p) v0.AddArg2(v1, mem) return true } // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [2] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [3] {s} p mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (MOVWUloadidx ptr0 idx0 mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpARM64MOVHUloadidx { break } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 2 { break } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x1.Args[1] { continue } y2 := v_1 if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 3 || auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] p := x2.Args[0] if mem != x2.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0)) { continue } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) v.copyOf(v0) v0.AddArg3(ptr0, idx0, mem) return true } break } // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx ptr idx mem) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (MOVWUloadidx ptr idx mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpARM64MOVHUloadidx { break } mem := x0.Args[2] ptr := x0.Args[0] idx := x0.Args[1] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 2 || idx != x1_1.Args[0] || mem != x1.Args[2] { break } y2 := v_1 if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { break } _ = x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 3 || idx != x2_1.Args[0] || mem != x2.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y1, y2, o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) v.copyOf(v0) v0.AddArg3(ptr, idx, mem) return true } // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx2 ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [2] {s} p1:(ADDshiftLL [1] ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [3] {s} p mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (MOVWUloadidx ptr0 (SLLconst [1] idx0) mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpARM64MOVHUloadidx2 { break } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 2 { break } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADDshiftLL || auxIntToInt64(p1.AuxInt) != 1 { break } idx1 := p1.Args[1] ptr1 := p1.Args[0] if mem != x1.Args[1] { break } y2 := v_1 if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 3 || auxToSym(x2.Aux) != s { break } _ = x2.Args[1] p := x2.Args[0] if mem != x2.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) v.copyOf(v0) v1 := b.NewValue0(x2.Pos, OpARM64SLLconst, idx0.Type) v1.AuxInt = int64ToAuxInt(1) v1.AddArg(idx0) v0.AddArg3(ptr0, v1, mem) return true } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUload [i0] {s} p mem) y1:(MOVDnop x1:(MOVBUload [i4] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i7] {s} p mem))) // cond: i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDload {s} (OffPtr [int64(i0)] p) mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] x0 := o2.Args[0] if x0.Op != OpARM64MOVWUload { break } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { break } i4 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { break } i5 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { break } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload { break } i6 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } y4 := v_1 if y4.Op != OpARM64MOVDnop { break } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload { break } i7 := auxIntToInt32(x4.AuxInt) if auxToSym(x4.Aux) != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] || !(i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x4.Pos, OpARM64MOVDload, t) v.copyOf(v0) v0.Aux = symToAux(s) v1 := b.NewValue0(x4.Pos, OpOffPtr, p.Type) v1.AuxInt = int64ToAuxInt(int64(i0)) v1.AddArg(p) v0.AddArg2(v1, mem) return true } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [4] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [7] {s} p mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDloadidx ptr0 idx0 mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] x0 := o2.Args[0] if x0.Op != OpARM64MOVWUloadidx { break } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 4 { break } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x1.Args[1] { continue } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 5 || auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] p := x2.Args[0] if mem != x2.Args[1] { continue } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 6 || auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { continue } y4 := v_1 if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 7 || auxToSym(x4.Aux) != s { continue } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x4.Pos, OpARM64MOVDloadidx, t) v.copyOf(v0) v0.AddArg3(ptr0, idx0, mem) return true } break } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx4 ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [4] {s} p1:(ADDshiftLL [2] ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [7] {s} p mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDloadidx ptr0 (SLLconst [2] idx0) mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] x0 := o2.Args[0] if x0.Op != OpARM64MOVWUloadidx4 { break } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 4 { break } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADDshiftLL || auxIntToInt64(p1.AuxInt) != 2 { break } idx1 := p1.Args[1] ptr1 := p1.Args[0] if mem != x1.Args[1] { break } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 5 || auxToSym(x2.Aux) != s { break } _ = x2.Args[1] p := x2.Args[0] if mem != x2.Args[1] { break } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { break } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 6 || auxToSym(x3.Aux) != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } y4 := v_1 if y4.Op != OpARM64MOVDnop { break } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 7 || auxToSym(x4.Aux) != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x4.Pos, OpARM64MOVDloadidx, t) v.copyOf(v0) v1 := b.NewValue0(x4.Pos, OpARM64SLLconst, idx0.Type) v1.AuxInt = int64ToAuxInt(2) v1.AddArg(idx0) v0.AddArg3(ptr0, v1, mem) return true } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx ptr idx mem) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [4] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [5] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [6] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr (ADDconst [7] idx) mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDloadidx ptr idx mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] x0 := o2.Args[0] if x0.Op != OpARM64MOVWUloadidx { break } mem := x0.Args[2] ptr := x0.Args[0] idx := x0.Args[1] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 4 || idx != x1_1.Args[0] || mem != x1.Args[2] { break } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { break } _ = x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 5 || idx != x2_1.Args[0] || mem != x2.Args[2] { break } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { break } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { break } _ = x3.Args[2] if ptr != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 6 || idx != x3_1.Args[0] || mem != x3.Args[2] { break } y4 := v_1 if y4.Op != OpARM64MOVDnop { break } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUloadidx { break } _ = x4.Args[2] if ptr != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpARM64ADDconst || auxIntToInt64(x4_1.AuxInt) != 7 || idx != x4_1.Args[0] || mem != x4.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) v.copyOf(v0) v0.AddArg3(ptr, idx, mem) return true } // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUload [i1] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) // result: @mergePoint(b,x0,x1) (REV16W (MOVHUload [i0] {s} p mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 8 { break } y0 := v_0 if y0.Op != OpARM64MOVDnop { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload { break } i1 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := v_1 if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { break } i0 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpARM64REV16W, t) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpARM64MOVHUload, t) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr0 idx0 mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1) // result: @mergePoint(b,x0,x1) (REV16W (MOVHUloadidx ptr0 idx0 mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 8 { break } y0 := v_0 if y0.Op != OpARM64MOVDnop { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload || auxIntToInt32(x0.AuxInt) != 1 { break } s := auxToSym(x0.Aux) mem := x0.Args[1] p1 := x0.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 y1 := v_1 if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { continue } _ = x1.Args[2] ptr0 := x1.Args[0] idx0 := x1.Args[1] if mem != x1.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpARM64REV16W, t) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpARM64MOVHUloadidx, t) v1.AddArg3(ptr0, idx0, mem) v0.AddArg(v1) return true } break } // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [1] idx) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr idx mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) // result: @mergePoint(b,x0,x1) (REV16W (MOVHUloadidx ptr idx mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 8 { break } y0 := v_0 if y0.Op != OpARM64MOVDnop { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { break } mem := x0.Args[2] ptr := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 1 { break } idx := x0_1.Args[0] y1 := v_1 if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { break } _ = x1.Args[2] if ptr != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpARM64REV16W, t) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpARM64MOVHUloadidx, t) v1.AddArg3(ptr, idx, mem) v0.AddArg(v1) return true } // match: (ORshiftLL [24] o0:(ORshiftLL [16] y0:(REV16W x0:(MOVHUload [i2] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i0] {s} p mem))) // cond: i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (REVW (MOVWUload {s} (OffPtr [int64(i0)] p) mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] y0 := o0.Args[0] if y0.Op != OpARM64REV16W { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVHUload { break } i2 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { break } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } y2 := v_1 if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { break } i0 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpARM64REVW, t) v.copyOf(v0) v1 := b.NewValue0(x2.Pos, OpARM64MOVWUload, t) v1.Aux = symToAux(s) v2 := b.NewValue0(x2.Pos, OpOffPtr, p.Type) v2.AuxInt = int64ToAuxInt(int64(i0)) v2.AddArg(p) v1.AddArg2(v2, mem) v0.AddArg(v1) return true } // match: (ORshiftLL [24] o0:(ORshiftLL [16] y0:(REV16W x0:(MOVHUload [2] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr0 idx0 mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y0, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (REVW (MOVWUloadidx ptr0 idx0 mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] y0 := o0.Args[0] if y0.Op != OpARM64REV16W { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVHUload || auxIntToInt32(x0.AuxInt) != 2 { break } s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { break } _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x1.Args[1] { continue } y2 := v_1 if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { continue } _ = x2.Args[2] ptr0 := x2.Args[0] idx0 := x2.Args[1] if mem != x2.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y0, y1, y2, o0)) { continue } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x1.Pos, OpARM64REVW, t) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpARM64MOVWUloadidx, t) v1.AddArg3(ptr0, idx0, mem) v0.AddArg(v1) return true } break } // match: (ORshiftLL [24] o0:(ORshiftLL [16] y0:(REV16W x0:(MOVHUloadidx ptr (ADDconst [2] idx) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr idx mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (REVW (MOVWUloadidx ptr idx mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] y0 := o0.Args[0] if y0.Op != OpARM64REV16W { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVHUloadidx { break } mem := x0.Args[2] ptr := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 2 { break } idx := x0_1.Args[0] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] { break } y2 := v_1 if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { break } _ = x2.Args[2] if ptr != x2.Args[0] || idx != x2.Args[1] || mem != x2.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, OpARM64REVW, t) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) v1.AddArg3(ptr, idx, mem) v0.AddArg(v1) return true } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] y0:(REVW x0:(MOVWUload [i4] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i3] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i1] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i0] {s} p mem))) // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (REV (MOVDload {s} (OffPtr [int64(i0)] p) mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] y0 := o2.Args[0] if y0.Op != OpARM64REVW { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVWUload { break } i4 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { break } i3 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { break } i2 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { break } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload { break } i1 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } y4 := v_1 if y4.Op != OpARM64MOVDnop { break } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload { break } i0 := auxIntToInt32(x4.AuxInt) if auxToSym(x4.Aux) != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x4.Pos, OpARM64REV, t) v.copyOf(v0) v1 := b.NewValue0(x4.Pos, OpARM64MOVDload, t) v1.Aux = symToAux(s) v2 := b.NewValue0(x4.Pos, OpOffPtr, p.Type) v2.AuxInt = int64ToAuxInt(int64(i0)) v2.AddArg(p) v1.AddArg2(v2, mem) v0.AddArg(v1) return true } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] y0:(REVW x0:(MOVWUload [4] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [3] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr0 idx0 mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (REV (MOVDloadidx ptr0 idx0 mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] y0 := o2.Args[0] if y0.Op != OpARM64REVW { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVWUload || auxIntToInt32(x0.AuxInt) != 4 { break } s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 3 || auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 2 || auxToSym(x2.Aux) != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { break } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 1 || auxToSym(x3.Aux) != s { break } _ = x3.Args[1] p1 := x3.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x3.Args[1] { continue } y4 := v_1 if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUloadidx { continue } _ = x4.Args[2] ptr0 := x4.Args[0] idx0 := x4.Args[1] if mem != x4.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x3.Pos, OpARM64REV, t) v.copyOf(v0) v1 := b.NewValue0(x3.Pos, OpARM64MOVDloadidx, t) v1.AddArg3(ptr0, idx0, mem) v0.AddArg(v1) return true } break } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] y0:(REVW x0:(MOVWUloadidx ptr (ADDconst [4] idx) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr idx mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (REV (MOVDloadidx ptr idx mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] y0 := o2.Args[0] if y0.Op != OpARM64REVW { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVWUloadidx { break } mem := x0.Args[2] ptr := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 4 { break } idx := x0_1.Args[0] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 3 || idx != x1_1.Args[0] || mem != x1.Args[2] { break } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { break } _ = x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 2 || idx != x2_1.Args[0] || mem != x2.Args[2] { break } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { break } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { break } _ = x3.Args[2] if ptr != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 1 || idx != x3_1.Args[0] || mem != x3.Args[2] { break } y4 := v_1 if y4.Op != OpARM64MOVDnop { break } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUloadidx { break } _ = x4.Args[2] if ptr != x4.Args[0] || idx != x4.Args[1] || mem != x4.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(v.Pos, OpARM64REV, t) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) v1.AddArg3(ptr, idx, mem) v0.AddArg(v1) return true } return false } func rewriteValueARM64_OpARM64ORshiftRA(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ORshiftRA (MOVDconst [c]) x [d]) // result: (ORconst [c] (SRAconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftRA x (MOVDconst [c]) [d]) // result: (ORconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (ORshiftRA y:(SRAconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRAconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64ORshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ORshiftRL (MOVDconst [c]) x [d]) // result: (ORconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftRL x (MOVDconst [c]) [d]) // result: (ORconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (ORshiftRL y:(SRLconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRLconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } // match: (ORshiftRL [rc] (ANDconst [ac] x) (SLLconst [lc] y)) // cond: lc > rc && ac == ^((1< rc && ac == ^((1< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftRO x (MOVDconst [c]) [d]) // result: (ORconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } // match: (ORshiftRO y:(RORconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64RORconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64REV(v *Value) bool { v_0 := v.Args[0] // match: (REV (REV p)) // result: p for { if v_0.Op != OpARM64REV { break } p := v_0.Args[0] v.copyOf(p) return true } return false } func rewriteValueARM64_OpARM64REVW(v *Value) bool { v_0 := v.Args[0] // match: (REVW (REVW p)) // result: p for { if v_0.Op != OpARM64REVW { break } p := v_0.Args[0] v.copyOf(p) return true } return false } func rewriteValueARM64_OpARM64ROR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ROR x (MOVDconst [c])) // result: (RORconst x [c&63]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64RORconst) v.AuxInt = int64ToAuxInt(c & 63) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64RORW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (RORW x (MOVDconst [c])) // result: (RORWconst x [c&31]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64RORWconst) v.AuxInt = int64ToAuxInt(c & 31) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64SBCSflags(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SBCSflags x y (Select1 (NEGSflags (NEG (NGCzerocarry bo))))) // result: (SBCSflags x y bo) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64NEGSflags { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64NEG || v_2_0_0.Type != typ.UInt64 { break } v_2_0_0_0 := v_2_0_0.Args[0] if v_2_0_0_0.Op != OpARM64NGCzerocarry || v_2_0_0_0.Type != typ.UInt64 { break } bo := v_2_0_0_0.Args[0] v.reset(OpARM64SBCSflags) v.AddArg3(x, y, bo) return true } // match: (SBCSflags x y (Select1 (NEGSflags (MOVDconst [0])))) // result: (SUBSflags x y) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64NEGSflags { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64MOVDconst || auxIntToInt64(v_2_0_0.AuxInt) != 0 { break } v.reset(OpARM64SUBSflags) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64SLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SLL x (MOVDconst [c])) // result: (SLLconst x [c&63]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(c & 63) v.AddArg(x) return true } // match: (SLL x (ANDconst [63] y)) // result: (SLL x y) for { x := v_0 if v_1.Op != OpARM64ANDconst || auxIntToInt64(v_1.AuxInt) != 63 { break } y := v_1.Args[0] v.reset(OpARM64SLL) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64SLLconst(v *Value) bool { v_0 := v.Args[0] // match: (SLLconst [c] (MOVDconst [d])) // result: (MOVDconst [d<>uint64(c)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(d >> uint64(c)) return true } // match: (SRAconst [rc] (SLLconst [lc] x)) // cond: lc > rc // result: (SBFIZ [armBFAuxInt(lc-rc, 64-lc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc > rc) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc-rc, 64-lc)) v.AddArg(x) return true } // match: (SRAconst [rc] (SLLconst [lc] x)) // cond: lc <= rc // result: (SBFX [armBFAuxInt(rc-lc, 64-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc <= rc) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc-lc, 64-rc)) v.AddArg(x) return true } // match: (SRAconst [rc] (MOVWreg x)) // cond: rc < 32 // result: (SBFX [armBFAuxInt(rc, 32-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWreg { break } x := v_0.Args[0] if !(rc < 32) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 32-rc)) v.AddArg(x) return true } // match: (SRAconst [rc] (MOVHreg x)) // cond: rc < 16 // result: (SBFX [armBFAuxInt(rc, 16-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHreg { break } x := v_0.Args[0] if !(rc < 16) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 16-rc)) v.AddArg(x) return true } // match: (SRAconst [rc] (MOVBreg x)) // cond: rc < 8 // result: (SBFX [armBFAuxInt(rc, 8-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBreg { break } x := v_0.Args[0] if !(rc < 8) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8-rc)) v.AddArg(x) return true } // match: (SRAconst [sc] (SBFIZ [bfc] x)) // cond: sc < bfc.getARM64BFlsb() // result: (SBFIZ [armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SBFIZ { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc < bfc.getARM64BFlsb()) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())) v.AddArg(x) return true } // match: (SRAconst [sc] (SBFIZ [bfc] x)) // cond: sc >= bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() // result: (SBFX [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SBFIZ { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc >= bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth()) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64SRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SRL x (MOVDconst [c])) // result: (SRLconst x [c&63]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(c & 63) v.AddArg(x) return true } // match: (SRL x (ANDconst [63] y)) // result: (SRL x y) for { x := v_0 if v_1.Op != OpARM64ANDconst || auxIntToInt64(v_1.AuxInt) != 63 { break } y := v_1.Args[0] v.reset(OpARM64SRL) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64SRLconst(v *Value) bool { v_0 := v.Args[0] // match: (SRLconst [c] (MOVDconst [d])) // result: (MOVDconst [int64(uint64(d)>>uint64(c))]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint64(d) >> uint64(c))) return true } // match: (SRLconst [c] (SLLconst [c] x)) // cond: 0 < c && c < 64 // result: (ANDconst [1<= 32 // result: (MOVDconst [0]) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg { break } if !(rc >= 32) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SRLconst [rc] (MOVHUreg x)) // cond: rc >= 16 // result: (MOVDconst [0]) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg { break } if !(rc >= 16) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SRLconst [rc] (MOVBUreg x)) // cond: rc >= 8 // result: (MOVDconst [0]) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg { break } if !(rc >= 8) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SRLconst [rc] (SLLconst [lc] x)) // cond: lc > rc // result: (UBFIZ [armBFAuxInt(lc-rc, 64-lc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc > rc) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc-rc, 64-lc)) v.AddArg(x) return true } // match: (SRLconst [rc] (SLLconst [lc] x)) // cond: lc < rc // result: (UBFX [armBFAuxInt(rc-lc, 64-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < rc) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc-lc, 64-rc)) v.AddArg(x) return true } // match: (SRLconst [rc] (MOVWUreg x)) // cond: rc < 32 // result: (UBFX [armBFAuxInt(rc, 32-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg { break } x := v_0.Args[0] if !(rc < 32) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 32-rc)) v.AddArg(x) return true } // match: (SRLconst [rc] (MOVHUreg x)) // cond: rc < 16 // result: (UBFX [armBFAuxInt(rc, 16-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg { break } x := v_0.Args[0] if !(rc < 16) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 16-rc)) v.AddArg(x) return true } // match: (SRLconst [rc] (MOVBUreg x)) // cond: rc < 8 // result: (UBFX [armBFAuxInt(rc, 8-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg { break } x := v_0.Args[0] if !(rc < 8) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8-rc)) v.AddArg(x) return true } // match: (SRLconst [sc] (ANDconst [ac] x)) // cond: isARM64BFMask(sc, ac, sc) // result: (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } ac := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(sc, ac, sc)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc, arm64BFWidth(ac, sc))) v.AddArg(x) return true } // match: (SRLconst [sc] (UBFX [bfc] x)) // cond: sc < bfc.getARM64BFwidth() // result: (UBFX [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc < bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } // match: (SRLconst [sc] (UBFIZ [bfc] x)) // cond: sc == bfc.getARM64BFlsb() // result: (ANDconst [1< bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() // result: (UBFX [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFIZ { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc > bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64STP(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (STP [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (STP [off1+int32(off2)] {sym} ptr val1 val2 mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val1 := v_1 val2 := v_2 mem := v_3 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg4(ptr, val1, val2, mem) return true } // match: (STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (STP [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val1 := v_1 val2 := v_2 mem := v_3 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg4(ptr, val1, val2, mem) return true } // match: (STP [off] {sym} ptr (MOVDconst [0]) (MOVDconst [0]) mem) // result: (MOVQstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 || v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64SUB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUB x (MOVDconst [c])) // result: (SUBconst [c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (SUB a l:(MUL x y)) // cond: l.Uses==1 && clobber(l) // result: (MSUB a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MUL { break } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MSUB) v.AddArg3(a, x, y) return true } // match: (SUB a l:(MNEG x y)) // cond: l.Uses==1 && clobber(l) // result: (MADD a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MNEG { break } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MADD) v.AddArg3(a, x, y) return true } // match: (SUB a l:(MULW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MSUBW a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MULW { break } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MSUBW) v.AddArg3(a, x, y) return true } // match: (SUB a l:(MNEGW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MADDW a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MNEGW { break } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MADDW) v.AddArg3(a, x, y) return true } // match: (SUB x x) // result: (MOVDconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SUB x (SUB y z)) // result: (SUB (ADD x z) y) for { x := v_0 if v_1.Op != OpARM64SUB { break } z := v_1.Args[1] y := v_1.Args[0] v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADD, v.Type) v0.AddArg2(x, z) v.AddArg2(v0, y) return true } // match: (SUB (SUB x y) z) // result: (SUB x (ADD y z)) for { if v_0.Op != OpARM64SUB { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADD, y.Type) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } // match: (SUB x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (SUBshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (SUB x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (SUBshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64SUBshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (SUB x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (SUBshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64SUBshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64SUBconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SUBconst [c] (MOVDconst [d])) // result: (MOVDconst [d-c]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(d - c) return true } // match: (SUBconst [c] (SUBconst [d] x)) // result: (ADDconst [-c-d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SUBconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(-c - d) v.AddArg(x) return true } // match: (SUBconst [c] (ADDconst [d] x)) // result: (ADDconst [-c+d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ADDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(-c + d) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64SUBshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBshiftLL x (MOVDconst [c]) [d]) // result: (SUBconst x [int64(uint64(c)<>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (SUBshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64SUBshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBshiftRL x (MOVDconst [c]) [d]) // result: (SUBconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (SUBshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64TST(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (TST x (MOVDconst [c])) // result: (TSTconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (TST x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (TST x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (TST x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (TST x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64TSTW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (TSTW x (MOVDconst [c])) // result: (TSTWconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTWconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueARM64_OpARM64TSTWconst(v *Value) bool { v_0 := v.Args[0] // match: (TSTWconst (MOVDconst [x]) [y]) // result: (FlagConstant [logicFlags32(int32(x)&y)]) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(logicFlags32(int32(x) & y)) return true } return false } func rewriteValueARM64_OpARM64TSTconst(v *Value) bool { v_0 := v.Args[0] // match: (TSTconst (MOVDconst [x]) [y]) // result: (FlagConstant [logicFlags64(x&y)]) for { y := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(logicFlags64(x & y)) return true } return false } func rewriteValueARM64_OpARM64TSTshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TSTshiftLL (MOVDconst [c]) x [d]) // result: (TSTconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftLL x (MOVDconst [c]) [d]) // result: (TSTconst x [int64(uint64(c)< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftRA x (MOVDconst [c]) [d]) // result: (TSTconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64TSTshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TSTshiftRL (MOVDconst [c]) x [d]) // result: (TSTconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftRL x (MOVDconst [c]) [d]) // result: (TSTconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64TSTshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TSTshiftRO (MOVDconst [c]) x [d]) // result: (TSTconst [c] (RORconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftRO x (MOVDconst [c]) [d]) // result: (TSTconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64UBFIZ(v *Value) bool { v_0 := v.Args[0] // match: (UBFIZ [bfc] (SLLconst [sc] x)) // cond: sc < bfc.getARM64BFwidth() // result: (UBFIZ [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(sc < bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64UBFX(v *Value) bool { v_0 := v.Args[0] // match: (UBFX [bfc] (ANDconst [c] x)) // cond: isARM64BFMask(0, c, 0) && bfc.getARM64BFlsb() + bfc.getARM64BFwidth() <= arm64BFWidth(c, 0) // result: (UBFX [bfc] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(0, c, 0) && bfc.getARM64BFlsb()+bfc.getARM64BFwidth() <= arm64BFWidth(c, 0)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } // match: (UBFX [bfc] (SRLconst [sc] x)) // cond: sc+bfc.getARM64BFwidth()+bfc.getARM64BFlsb() < 64 // result: (UBFX [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth())] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64SRLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(sc+bfc.getARM64BFwidth()+bfc.getARM64BFlsb() < 64) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth())) v.AddArg(x) return true } // match: (UBFX [bfc] (SLLconst [sc] x)) // cond: sc == bfc.getARM64BFlsb() // result: (ANDconst [1< bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() // result: (UBFIZ [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(sc > bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64UDIV(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (UDIV x (MOVDconst [1])) // result: x for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.copyOf(x) return true } // match: (UDIV x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SRLconst [log64(c)] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } // match: (UDIV (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint64(c)/uint64(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) / uint64(d))) return true } return false } func rewriteValueARM64_OpARM64UDIVW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (UDIVW x (MOVDconst [c])) // cond: uint32(c)==1 // result: x for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(uint32(c) == 1) { break } v.copyOf(x) return true } // match: (UDIVW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) && is32Bit(c) // result: (SRLconst [log64(c)] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c) && is32Bit(c)) { break } v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } // match: (UDIVW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint32(c)/uint32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint32(c) / uint32(d))) return true } return false } func rewriteValueARM64_OpARM64UMOD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (UMOD x y) // result: (MSUB x y (UDIV x y)) for { if v.Type != typ.UInt64 { break } x := v_0 y := v_1 v.reset(OpARM64MSUB) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64UDIV, typ.UInt64) v0.AddArg2(x, y) v.AddArg3(x, y, v0) return true } // match: (UMOD _ (MOVDconst [1])) // result: (MOVDconst [0]) for { if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (UMOD x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (ANDconst [c-1] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c - 1) v.AddArg(x) return true } // match: (UMOD (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint64(c)%uint64(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) % uint64(d))) return true } return false } func rewriteValueARM64_OpARM64UMODW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (UMODW x y) // result: (MSUBW x y (UDIVW x y)) for { if v.Type != typ.UInt32 { break } x := v_0 y := v_1 v.reset(OpARM64MSUBW) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpARM64UDIVW, typ.UInt32) v0.AddArg2(x, y) v.AddArg3(x, y, v0) return true } // match: (UMODW _ (MOVDconst [c])) // cond: uint32(c)==1 // result: (MOVDconst [0]) for { if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(uint32(c) == 1) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (UMODW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) && is32Bit(c) // result: (ANDconst [c-1] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c) && is32Bit(c)) { break } v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c - 1) v.AddArg(x) return true } // match: (UMODW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint32(c)%uint32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint32(c) % uint32(d))) return true } return false } func rewriteValueARM64_OpARM64XOR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (XOR x (MOVDconst [c])) // result: (XORconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (XOR x x) // result: (MOVDconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (XOR x (MVN y)) // result: (EON x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MVN { continue } y := v_1.Args[0] v.reset(OpARM64EON) v.AddArg2(x, y) return true } break } // match: (XOR x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (XOR x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (XOR x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (XOR x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64XORconst(v *Value) bool { v_0 := v.Args[0] // match: (XORconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (XORconst [-1] x) // result: (MVN x) for { if auxIntToInt64(v.AuxInt) != -1 { break } x := v_0 v.reset(OpARM64MVN) v.AddArg(x) return true } // match: (XORconst [c] (MOVDconst [d])) // result: (MOVDconst [c^d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c ^ d) return true } // match: (XORconst [c] (XORconst [d] x)) // result: (XORconst [c^d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64XORconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c ^ d) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64XORshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (XORshiftLL (MOVDconst [c]) x [d]) // result: (XORconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftLL x (MOVDconst [c]) [d]) // result: (XORconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) // result: (REV16W x) for { if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (XORshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff // result: (REV16W x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (XORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) // result: (REV16 x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { break } v.reset(OpARM64REV16) v.AddArg(x) return true } // match: (XORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) // result: (REV16 (ANDconst [0xffffffff] x)) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16) v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) v0.AuxInt = int64ToAuxInt(0xffffffff) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftLL [c] (SRLconst x [64-c]) x2) // result: (EXTRconst [64-c] x2 x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { break } x := v_0.Args[0] x2 := v_1 v.reset(OpARM64EXTRconst) v.AuxInt = int64ToAuxInt(64 - c) v.AddArg2(x2, x) return true } // match: (XORshiftLL [c] (UBFX [bfc] x) x2) // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) // result: (EXTRWconst [32-c] x2 x) for { t := v.Type c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] x2 := v_1 if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { break } v.reset(OpARM64EXTRWconst) v.AuxInt = int64ToAuxInt(32 - c) v.AddArg2(x2, x) return true } return false } func rewriteValueARM64_OpARM64XORshiftRA(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (XORshiftRA (MOVDconst [c]) x [d]) // result: (XORconst [c] (SRAconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftRA x (MOVDconst [c]) [d]) // result: (XORconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (XORshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64XORshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (XORshiftRL (MOVDconst [c]) x [d]) // result: (XORconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftRL x (MOVDconst [c]) [d]) // result: (XORconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (XORshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64XORshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (XORshiftRO (MOVDconst [c]) x [d]) // result: (XORconst [c] (RORconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftRO x (MOVDconst [c]) [d]) // result: (XORconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } // match: (XORshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpAddr(v *Value) bool { v_0 := v.Args[0] // match: (Addr {sym} base) // result: (MOVDaddr {sym} base) for { sym := auxToSym(v.Aux) base := v_0 v.reset(OpARM64MOVDaddr) v.Aux = symToAux(sym) v.AddArg(base) return true } } func rewriteValueARM64_OpAtomicAnd32(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd32 ptr val mem) // result: (Select1 (LoweredAtomicAnd32 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd32, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicAnd32Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd32Variant ptr val mem) // result: (Select1 (LoweredAtomicAnd32Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd32Variant, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicAnd8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd8 ptr val mem) // result: (Select1 (LoweredAtomicAnd8 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd8, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicAnd8Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd8Variant ptr val mem) // result: (Select1 (LoweredAtomicAnd8Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd8Variant, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr32(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr32 ptr val mem) // result: (Select1 (LoweredAtomicOr32 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr32, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr32Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr32Variant ptr val mem) // result: (Select1 (LoweredAtomicOr32Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr32Variant, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr8 ptr val mem) // result: (Select1 (LoweredAtomicOr8 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr8, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr8Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr8Variant ptr val mem) // result: (Select1 (LoweredAtomicOr8Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr8Variant, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAvg64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Avg64u x y) // result: (ADD (SRLconst (SUB x y) [1]) y) for { t := v.Type x := v_0 y := v_1 v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, t) v0.AuxInt = int64ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpARM64SUB, t) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg2(v0, y) return true } } func rewriteValueARM64_OpBitLen32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // result: (SUB (MOVDconst [32]) (CLZW x)) for { x := v_0 v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(32) v1 := b.NewValue0(v.Pos, OpARM64CLZW, typ.Int) v1.AddArg(x) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpBitLen64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // result: (SUB (MOVDconst [64]) (CLZ x)) for { x := v_0 v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(64) v1 := b.NewValue0(v.Pos, OpARM64CLZ, typ.Int) v1.AddArg(x) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpBitRev16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitRev16 x) // result: (SRLconst [48] (RBIT x)) for { x := v_0 v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(48) v0 := b.NewValue0(v.Pos, OpARM64RBIT, typ.UInt64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpBitRev8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitRev8 x) // result: (SRLconst [56] (RBIT x)) for { x := v_0 v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(56) v0 := b.NewValue0(v.Pos, OpARM64RBIT, typ.UInt64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CondSelect x y boolval) // cond: flagArg(boolval) != nil // result: (CSEL [boolval.Op] x y flagArg(boolval)) for { x := v_0 y := v_1 boolval := v_2 if !(flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(boolval.Op) v.AddArg3(x, y, flagArg(boolval)) return true } // match: (CondSelect x y boolval) // cond: flagArg(boolval) == nil // result: (CSEL [OpARM64NotEqual] x y (TSTWconst [1] boolval)) for { x := v_0 y := v_1 boolval := v_2 if !(flagArg(boolval) == nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(1) v0.AddArg(boolval) v.AddArg3(x, y, v0) return true } return false } func rewriteValueARM64_OpConst16(v *Value) bool { // match: (Const16 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt16(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConst32(v *Value) bool { // match: (Const32 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt32(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConst32F(v *Value) bool { // match: (Const32F [val]) // result: (FMOVSconst [float64(val)]) for { val := auxIntToFloat32(v.AuxInt) v.reset(OpARM64FMOVSconst) v.AuxInt = float64ToAuxInt(float64(val)) return true } } func rewriteValueARM64_OpConst64(v *Value) bool { // match: (Const64 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt64(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConst64F(v *Value) bool { // match: (Const64F [val]) // result: (FMOVDconst [float64(val)]) for { val := auxIntToFloat64(v.AuxInt) v.reset(OpARM64FMOVDconst) v.AuxInt = float64ToAuxInt(float64(val)) return true } } func rewriteValueARM64_OpConst8(v *Value) bool { // match: (Const8 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt8(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConstBool(v *Value) bool { // match: (ConstBool [t]) // result: (MOVDconst [b2i(t)]) for { t := auxIntToBool(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(t)) return true } } func rewriteValueARM64_OpConstNil(v *Value) bool { // match: (ConstNil) // result: (MOVDconst [0]) for { v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } } func rewriteValueARM64_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (CLZW (RBITW (ORconst [0x10000] x))) for { t := v.Type x := v_0 v.reset(OpARM64CLZW) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64RBITW, typ.UInt32) v1 := b.NewValue0(v.Pos, OpARM64ORconst, typ.UInt32) v1.AuxInt = int64ToAuxInt(0x10000) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Ctz32 x) // result: (CLZW (RBITW x)) for { t := v.Type x := v_0 v.reset(OpARM64CLZW) v0 := b.NewValue0(v.Pos, OpARM64RBITW, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Ctz64 x) // result: (CLZ (RBIT x)) for { t := v.Type x := v_0 v.reset(OpARM64CLZ) v0 := b.NewValue0(v.Pos, OpARM64RBIT, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (CLZW (RBITW (ORconst [0x100] x))) for { t := v.Type x := v_0 v.reset(OpARM64CLZW) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64RBITW, typ.UInt32) v1 := b.NewValue0(v.Pos, OpARM64ORconst, typ.UInt32) v1.AuxInt = int64ToAuxInt(0x100) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 [false] x y) // result: (DIVW (SignExt16to32 x) (SignExt16to32 y)) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpARM64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (UDIVW (ZeroExt16to32 x) (ZeroExt16to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UDIVW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Div32 [false] x y) // result: (DIVW x y) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpARM64DIVW) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Div64 [false] x y) // result: (DIV x y) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpARM64DIV) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (DIVW (SignExt8to32 x) (SignExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (UDIVW (ZeroExt8to32 x) (ZeroExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UDIVW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq16 x y) // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32 x y) // result: (Equal (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32F x y) // result: (Equal (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64 x y) // result: (Equal (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64F x y) // result: (Equal (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq8 x y) // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqB x y) // result: (XOR (MOVDconst [1]) (XOR x y)) for { x := v_0 y := v_1 v.reset(OpARM64XOR) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpARM64XOR, typ.Bool) v1.AddArg2(x, y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqPtr x y) // result: (Equal (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpFMA(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMA x y z) // result: (FMADDD z x y) for { x := v_0 y := v_1 z := v_2 v.reset(OpARM64FMADDD) v.AddArg3(z, x, y) return true } } func rewriteValueARM64_OpHmul32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Hmul32 x y) // result: (SRAconst (MULL x y) [32]) for { x := v_0 y := v_1 v.reset(OpARM64SRAconst) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpARM64MULL, typ.Int64) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpHmul32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Hmul32u x y) // result: (SRAconst (UMULL x y) [32]) for { x := v_0 y := v_1 v.reset(OpARM64SRAconst) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpARM64UMULL, typ.UInt64) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsInBounds idx len) // result: (LessThanU (CMP idx len)) for { idx := v_0 len := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueARM64_OpIsNonNil(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (IsNonNil ptr) // result: (NotEqual (CMPconst [0] ptr)) for { ptr := v_0 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(0) v0.AddArg(ptr) v.AddArg(v0) return true } } func rewriteValueARM64_OpIsSliceInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsSliceInBounds idx len) // result: (LessEqualU (CMP idx len)) for { idx := v_0 len := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq16 x y) // result: (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq16U x zero:(MOVDconst [0])) // result: (Eq16 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq16) v.AddArg2(x, zero) return true } // match: (Leq16U (MOVDconst [1]) x) // result: (Neq16 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq16U x y) // result: (LessEqualU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32 x y) // result: (LessEqual (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32F x y) // result: (LessEqualF (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualF) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq32U x zero:(MOVDconst [0])) // result: (Eq32 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq32) v.AddArg2(x, zero) return true } // match: (Leq32U (MOVDconst [1]) x) // result: (Neq32 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq32U x y) // result: (LessEqualU (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64 x y) // result: (LessEqual (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64F x y) // result: (LessEqualF (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualF) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq64U x zero:(MOVDconst [0])) // result: (Eq64 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq64) v.AddArg2(x, zero) return true } // match: (Leq64U (MOVDconst [1]) x) // result: (Neq64 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq64U x y) // result: (LessEqualU (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq8 x y) // result: (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq8U x zero:(MOVDconst [0])) // result: (Eq8 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq8) v.AddArg2(x, zero) return true } // match: (Leq8U (MOVDconst [1]) x) // result: (Neq8 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq8U x y) // result: (LessEqualU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less16 x y) // result: (LessThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less16U zero:(MOVDconst [0]) x) // result: (Neq16 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq16) v.AddArg2(zero, x) return true } // match: (Less16U x (MOVDconst [1])) // result: (Eq16 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less16U x y) // result: (LessThanU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 x y) // result: (LessThan (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32F x y) // result: (LessThanF (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanF) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less32U zero:(MOVDconst [0]) x) // result: (Neq32 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq32) v.AddArg2(zero, x) return true } // match: (Less32U x (MOVDconst [1])) // result: (Eq32 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less32U x y) // result: (LessThanU (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 x y) // result: (LessThan (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64F x y) // result: (LessThanF (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanF) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less64U zero:(MOVDconst [0]) x) // result: (Neq64 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq64) v.AddArg2(zero, x) return true } // match: (Less64U x (MOVDconst [1])) // result: (Eq64 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less64U x y) // result: (LessThanU (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less8 x y) // result: (LessThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less8U zero:(MOVDconst [0]) x) // result: (Neq8 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq8) v.AddArg2(zero, x) return true } // match: (Less8U x (MOVDconst [1])) // result: (Eq8 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less8U x y) // result: (LessThanU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Load ptr mem) // cond: t.IsBoolean() // result: (MOVBUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsBoolean()) { break } v.reset(OpARM64MOVBUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is8BitInt(t) && t.IsSigned()) // result: (MOVBload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is8BitInt(t) && t.IsSigned()) { break } v.reset(OpARM64MOVBload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is8BitInt(t) && !t.IsSigned()) // result: (MOVBUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is8BitInt(t) && !t.IsSigned()) { break } v.reset(OpARM64MOVBUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is16BitInt(t) && t.IsSigned()) // result: (MOVHload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t) && t.IsSigned()) { break } v.reset(OpARM64MOVHload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is16BitInt(t) && !t.IsSigned()) // result: (MOVHUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t) && !t.IsSigned()) { break } v.reset(OpARM64MOVHUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is32BitInt(t) && t.IsSigned()) // result: (MOVWload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t) && t.IsSigned()) { break } v.reset(OpARM64MOVWload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is32BitInt(t) && !t.IsSigned()) // result: (MOVWUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t) && !t.IsSigned()) { break } v.reset(OpARM64MOVWUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpARM64MOVDload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (FMOVSload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitFloat(t)) { break } v.reset(OpARM64FMOVSload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (FMOVDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitFloat(t)) { break } v.reset(OpARM64FMOVDload) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpLocalAddr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (LocalAddr {sym} base mem) // cond: t.Elem().HasPointers() // result: (MOVDaddr {sym} (SPanchored base mem)) for { t := v.Type sym := auxToSym(v.Aux) base := v_0 mem := v_1 if !(t.Elem().HasPointers()) { break } v.reset(OpARM64MOVDaddr) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr) v0.AddArg2(base, mem) v.AddArg(v0) return true } // match: (LocalAddr {sym} base _) // cond: !t.Elem().HasPointers() // result: (MOVDaddr {sym} base) for { t := v.Type sym := auxToSym(v.Aux) base := v_0 if !(!t.Elem().HasPointers()) { break } v.reset(OpARM64MOVDaddr) v.Aux = symToAux(sym) v.AddArg(base) return true } return false } func rewriteValueARM64_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16 x y) // result: (MODW (SignExt16to32 x) (SignExt16to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64MODW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (UMODW (ZeroExt16to32 x) (ZeroExt16to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UMODW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mod32 x y) // result: (MODW x y) for { x := v_0 y := v_1 v.reset(OpARM64MODW) v.AddArg2(x, y) return true } } func rewriteValueARM64_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mod64 x y) // result: (MOD x y) for { x := v_0 y := v_1 v.reset(OpARM64MOD) v.AddArg2(x, y) return true } } func rewriteValueARM64_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (MODW (SignExt8to32 x) (SignExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64MODW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (UMODW (ZeroExt8to32 x) (ZeroExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UMODW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBUload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [2] dst src mem) // result: (MOVHstore dst (MOVHUload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVHstore) v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBUload [2] src mem) (MOVHstore dst (MOVHUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AuxInt = int32ToAuxInt(2) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [4] dst src mem) // result: (MOVWstore dst (MOVWUload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVWstore) v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBUload [4] src mem) (MOVWstore dst (MOVWUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [6] dst src mem) // result: (MOVHstore [4] dst (MOVHUload [4] src mem) (MOVWstore dst (MOVWUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [7] dst src mem) // result: (MOVWstore [3] dst (MOVWUload [3] src mem) (MOVWstore dst (MOVWUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [8] dst src mem) // result: (MOVDstore dst (MOVDload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBUload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [10] dst src mem) // result: (MOVHstore [8] dst (MOVHUload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [11] dst src mem) // result: (MOVDstore [3] dst (MOVDload [3] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 11 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [12] dst src mem) // result: (MOVWstore [8] dst (MOVWUload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [13] dst src mem) // result: (MOVDstore [5] dst (MOVDload [5] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 13 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(5) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(5) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [14] dst src mem) // result: (MOVDstore [6] dst (MOVDload [6] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 14 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(6) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(6) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [15] dst src mem) // result: (MOVDstore [7] dst (MOVDload [7] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 15 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(7) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(7) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [16] dst src mem) // result: (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v.AddArg4(dst, v0, v2, mem) return true } // match: (Move [32] dst src mem) // result: (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AuxInt = int32ToAuxInt(16) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v5.AddArg2(src, mem) v4.AddArg(v5) v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v6.AddArg(v5) v3.AddArg4(dst, v4, v6, mem) v.AddArg4(dst, v0, v2, v3) return true } // match: (Move [48] dst src mem) // result: (STP [32] dst (Select0 (LDP [32] src mem)) (Select1 (LDP [32] src mem)) (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AuxInt = int32ToAuxInt(32) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v3.AuxInt = int32ToAuxInt(16) v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v5.AuxInt = int32ToAuxInt(16) v5.AddArg2(src, mem) v4.AddArg(v5) v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v6.AddArg(v5) v7 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v9 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v9.AddArg2(src, mem) v8.AddArg(v9) v10 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v10.AddArg(v9) v7.AddArg4(dst, v8, v10, mem) v3.AddArg4(dst, v4, v6, v7) v.AddArg4(dst, v0, v2, v3) return true } // match: (Move [64] dst src mem) // result: (STP [48] dst (Select0 (LDP [48] src mem)) (Select1 (LDP [48] src mem)) (STP [32] dst (Select0 (LDP [32] src mem)) (Select1 (LDP [32] src mem)) (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(48) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AuxInt = int32ToAuxInt(48) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v3.AuxInt = int32ToAuxInt(32) v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v5.AuxInt = int32ToAuxInt(32) v5.AddArg2(src, mem) v4.AddArg(v5) v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v6.AddArg(v5) v7 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v7.AuxInt = int32ToAuxInt(16) v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v9 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v9.AuxInt = int32ToAuxInt(16) v9.AddArg2(src, mem) v8.AddArg(v9) v10 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v10.AddArg(v9) v11 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v12 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v13 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v13.AddArg2(src, mem) v12.AddArg(v13) v14 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v14.AddArg(v13) v11.AddArg4(dst, v12, v14, mem) v7.AddArg4(dst, v8, v10, v11) v3.AddArg4(dst, v4, v6, v7) v.AddArg4(dst, v0, v2, v3) return true } // match: (Move [s] dst src mem) // cond: s%16 != 0 && s%16 <= 8 && s > 16 // result: (Move [8] (OffPtr dst [s-8]) (OffPtr src [s-8]) (Move [s-s%16] dst src mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s%16 != 0 && s%16 <= 8 && s > 16) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s - 8) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s - 8) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(s - s%16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s%16 != 0 && s%16 > 8 && s > 16 // result: (Move [16] (OffPtr dst [s-16]) (OffPtr src [s-16]) (Move [s-s%16] dst src mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s%16 != 0 && s%16 > 8 && s > 16) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s - 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(s - s%16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s) // result: (DUFFCOPY [8 * (64 - s/16)] dst src mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s)) { break } v.reset(OpARM64DUFFCOPY) v.AuxInt = int64ToAuxInt(8 * (64 - s/16)) v.AddArg3(dst, src, mem) return true } // match: (Move [s] dst src mem) // cond: s%16 == 0 && (s > 16*64 || config.noDuffDevice) && logLargeCopy(v, s) // result: (LoweredMove dst src (ADDconst src [s-16]) mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s%16 == 0 && (s > 16*64 || config.noDuffDevice) && logLargeCopy(v, s)) { break } v.reset(OpARM64LoweredMove) v0 := b.NewValue0(v.Pos, OpARM64ADDconst, src.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(src) v.AddArg4(dst, src, v0, mem) return true } return false } func rewriteValueARM64_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq16 x y) // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32 x y) // result: (NotEqual (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32F x y) // result: (NotEqual (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64 x y) // result: (NotEqual (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64F x y) // result: (NotEqual (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq8 x y) // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqPtr x y) // result: (NotEqual (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNot(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Not x) // result: (XOR (MOVDconst [1]) x) for { x := v_0 v.reset(OpARM64XOR) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(1) v.AddArg2(v0, x) return true } } func rewriteValueARM64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] // match: (OffPtr [off] ptr:(SP)) // cond: is32Bit(off) // result: (MOVDaddr [int32(off)] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 if ptr.Op != OpSP || !(is32Bit(off)) { break } v.reset(OpARM64MOVDaddr) v.AuxInt = int32ToAuxInt(int32(off)) v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDconst [off] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(off) v.AddArg(ptr) return true } } func rewriteValueARM64_OpPanicBounds(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 0) { break } v.reset(OpARM64LoweredPanicBoundsA) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 1) { break } v.reset(OpARM64LoweredPanicBoundsB) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 2) { break } v.reset(OpARM64LoweredPanicBoundsC) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } return false } func rewriteValueARM64_OpPopCount16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (FMOVDfpgp (VUADDLV (VCNT (FMOVDgpfp (ZeroExt16to64 x))))) for { t := v.Type x := v_0 v.reset(OpARM64FMOVDfpgp) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64) v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64) v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(x) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpPopCount32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount32 x) // result: (FMOVDfpgp (VUADDLV (VCNT (FMOVDgpfp (ZeroExt32to64 x))))) for { t := v.Type x := v_0 v.reset(OpARM64FMOVDfpgp) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64) v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64) v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpPopCount64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount64 x) // result: (FMOVDfpgp (VUADDLV (VCNT (FMOVDgpfp x)))) for { t := v.Type x := v_0 v.reset(OpARM64FMOVDfpgp) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64) v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64) v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpPrefetchCache(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (PrefetchCache addr mem) // result: (PRFM [0] addr mem) for { addr := v_0 mem := v_1 v.reset(OpARM64PRFM) v.AuxInt = int64ToAuxInt(0) v.AddArg2(addr, mem) return true } } func rewriteValueARM64_OpPrefetchCacheStreamed(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (PrefetchCacheStreamed addr mem) // result: (PRFM [1] addr mem) for { addr := v_0 mem := v_1 v.reset(OpARM64PRFM) v.AuxInt = int64ToAuxInt(1) v.AddArg2(addr, mem) return true } } func rewriteValueARM64_OpPubBarrier(v *Value) bool { v_0 := v.Args[0] // match: (PubBarrier mem) // result: (DMB [0xe] mem) for { mem := v_0 v.reset(OpARM64DMB) v.AuxInt = int64ToAuxInt(0xe) v.AddArg(mem) return true } } func rewriteValueARM64_OpRotateLeft16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (RotateLeft16 x (MOVDconst [c])) // result: (Or16 (Lsh16x64 x (MOVDconst [c&15])) (Rsh16Ux64 x (MOVDconst [-c&15]))) for { t := v.Type x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(c & 15) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpRsh16Ux64, t) v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v3.AuxInt = int64ToAuxInt(-c & 15) v2.AddArg2(x, v3) v.AddArg2(v0, v2) return true } // match: (RotateLeft16 x y) // result: (RORW (ORshiftLL (ZeroExt16to32 x) (ZeroExt16to32 x) [16]) (NEG y)) for { t := v.Type x := v_0 y := v_1 v.reset(OpARM64RORW) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64ORshiftLL, typ.UInt32) v0.AuxInt = int64ToAuxInt(16) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v2 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) v2.AddArg(y) v.AddArg2(v0, v2) return true } } func rewriteValueARM64_OpRotateLeft32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (RotateLeft32 x y) // result: (RORW x (NEG y)) for { x := v_0 y := v_1 v.reset(OpARM64RORW) v0 := b.NewValue0(v.Pos, OpARM64NEG, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } } func rewriteValueARM64_OpRotateLeft64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (RotateLeft64 x y) // result: (ROR x (NEG y)) for { x := v_0 y := v_1 v.reset(OpARM64ROR) v0 := b.NewValue0(v.Pos, OpARM64NEG, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } } func rewriteValueARM64_OpRotateLeft8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (RotateLeft8 x (MOVDconst [c])) // result: (Or8 (Lsh8x64 x (MOVDconst [c&7])) (Rsh8Ux64 x (MOVDconst [-c&7]))) for { t := v.Type x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(c & 7) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpRsh8Ux64, t) v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v3.AuxInt = int64ToAuxInt(-c & 7) v2.AddArg2(x, v3) v.AddArg2(v0, v2) return true } // match: (RotateLeft8 x y) // result: (OR (SLL x (ANDconst [7] y)) (SRL (ZeroExt8to64 x) (ANDconst [7] (NEG y)))) for { t := v.Type x := v_0 y := v_1 v.reset(OpARM64OR) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v1 := b.NewValue0(v.Pos, OpARM64ANDconst, typ.Int64) v1.AuxInt = int64ToAuxInt(7) v1.AddArg(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpARM64SRL, t) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(x) v4 := b.NewValue0(v.Pos, OpARM64ANDconst, typ.Int64) v4.AuxInt = int64ToAuxInt(7) v5 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) v5.AddArg(y) v4.AddArg(v5) v2.AddArg2(v3, v4) v.AddArg2(v0, v2) return true } } func rewriteValueARM64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpSelect0(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uhilo x y)) // result: (UMULH x y) for { if v_0.Op != OpMul64uhilo { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64UMULH) v.AddArg2(x, y) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCSflags x y (Select1 (ADDSconstflags [-1] c)))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64ADCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpARM64ADDSconstflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AuxInt = int64ToAuxInt(-1) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y bo)) // result: (Select0 (SBCSflags x y (Select1 (NEGSflags bo)))) for { if v_0.Op != OpSub64borrow { break } bo := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64SBCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpARM64NEGSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(bo) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Mul64uover x y)) // result: (MUL x y) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MUL) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpSelect1(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uhilo x y)) // result: (MUL x y) for { if v_0.Op != OpMul64uhilo { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MUL) v.AddArg2(x, y) return true } // match: (Select1 (Add64carry x y c)) // result: (ADCzerocarry (Select1 (ADCSflags x y (Select1 (ADDSconstflags [-1] c))))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpARM64ADCzerocarry) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64ADCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v2 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v3 := b.NewValue0(v.Pos, OpARM64ADDSconstflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v3.AuxInt = int64ToAuxInt(-1) v3.AddArg(c) v2.AddArg(v3) v1.AddArg3(x, y, v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y bo)) // result: (NEG (NGCzerocarry (Select1 (SBCSflags x y (Select1 (NEGSflags bo)))))) for { if v_0.Op != OpSub64borrow { break } bo := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpARM64NEG) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64NGCzerocarry, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpARM64SBCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpARM64NEGSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v4.AddArg(bo) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul64uover x y)) // result: (NotEqual (CMPconst (UMULH x y) [0])) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64UMULH, typ.UInt64) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVDstore _ (MOVDconst [sz]) s2:(MOVDstore _ src s3:(MOVDstore {t} _ dst mem))))) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(s1, s2, s3, call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpARM64CALLstatic || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpARM64MOVDstore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpARM64MOVDconst { break } sz := auxIntToInt64(s1_1.AuxInt) s2 := s1.Args[2] if s2.Op != OpARM64MOVDstore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpARM64MOVDstore { break } mem := s3.Args[2] dst := s3.Args[1] if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVDconst [sz]) mem)) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpARM64CALLstatic || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpARM64MOVDconst { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } return false } func rewriteValueARM64_OpSlicemask(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Slicemask x) // result: (SRAconst (NEG x) [63]) for { t := v.Type x := v_0 v.reset(OpARM64SRAconst) v.AuxInt = int64ToAuxInt(63) v0 := b.NewValue0(v.Pos, OpARM64NEG, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (Store {t} ptr val mem) // cond: t.Size() == 1 // result: (MOVBstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 1) { break } v.reset(OpARM64MOVBstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 2 // result: (MOVHstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 2) { break } v.reset(OpARM64MOVHstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && !t.IsFloat() // result: (MOVWstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && !t.IsFloat()) { break } v.reset(OpARM64MOVWstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && !t.IsFloat() // result: (MOVDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && !t.IsFloat()) { break } v.reset(OpARM64MOVDstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && t.IsFloat() // result: (FMOVSstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && t.IsFloat()) { break } v.reset(OpARM64FMOVSstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && t.IsFloat() // result: (FMOVDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && t.IsFloat()) { break } v.reset(OpARM64FMOVDstore) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [0] _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_1 v.copyOf(mem) return true } // match: (Zero [1] ptr mem) // result: (MOVBstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [2] ptr mem) // result: (MOVHstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVHstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [4] ptr mem) // result: (MOVWstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVWstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [3] ptr mem) // result: (MOVBstore [2] ptr (MOVDconst [0]) (MOVHstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [5] ptr mem) // result: (MOVBstore [4] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [6] ptr mem) // result: (MOVHstore [4] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [7] ptr mem) // result: (MOVWstore [3] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [8] ptr mem) // result: (MOVDstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [9] ptr mem) // result: (MOVBstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [10] ptr mem) // result: (MOVHstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [11] ptr mem) // result: (MOVDstore [3] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 11 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [12] ptr mem) // result: (MOVWstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [13] ptr mem) // result: (MOVDstore [5] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 13 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(5) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [14] ptr mem) // result: (MOVDstore [6] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 14 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(6) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [15] ptr mem) // result: (MOVDstore [7] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 15 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(7) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [16] ptr mem) // result: (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(0) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg4(ptr, v0, v0, mem) return true } // match: (Zero [32] ptr mem) // result: (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v1.AuxInt = int32ToAuxInt(0) v1.AddArg4(ptr, v0, v0, mem) v.AddArg4(ptr, v0, v0, v1) return true } // match: (Zero [48] ptr mem) // result: (STP [32] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v1.AuxInt = int32ToAuxInt(16) v2 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v2.AuxInt = int32ToAuxInt(0) v2.AddArg4(ptr, v0, v0, mem) v1.AddArg4(ptr, v0, v0, v2) v.AddArg4(ptr, v0, v0, v1) return true } // match: (Zero [64] ptr mem) // result: (STP [48] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [32] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(48) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v1.AuxInt = int32ToAuxInt(32) v2 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v2.AuxInt = int32ToAuxInt(16) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v3.AuxInt = int32ToAuxInt(0) v3.AddArg4(ptr, v0, v0, mem) v2.AddArg4(ptr, v0, v0, v3) v1.AddArg4(ptr, v0, v0, v2) v.AddArg4(ptr, v0, v0, v1) return true } // match: (Zero [s] ptr mem) // cond: s%16 != 0 && s%16 <= 8 && s > 16 // result: (Zero [8] (OffPtr ptr [s-8]) (Zero [s-s%16] ptr mem)) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 != 0 && s%16 <= 8 && s > 16) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpOffPtr, ptr.Type) v0.AuxInt = int64ToAuxInt(s - 8) v0.AddArg(ptr) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(s - s%16) v1.AddArg2(ptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] ptr mem) // cond: s%16 != 0 && s%16 > 8 && s > 16 // result: (Zero [16] (OffPtr ptr [s-16]) (Zero [s-s%16] ptr mem)) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 != 0 && s%16 > 8 && s > 16) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, ptr.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(ptr) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(s - s%16) v1.AddArg2(ptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] ptr mem) // cond: s%16 == 0 && s > 64 && s <= 16*64 && !config.noDuffDevice // result: (DUFFZERO [4 * (64 - s/16)] ptr mem) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 == 0 && s > 64 && s <= 16*64 && !config.noDuffDevice) { break } v.reset(OpARM64DUFFZERO) v.AuxInt = int64ToAuxInt(4 * (64 - s/16)) v.AddArg2(ptr, mem) return true } // match: (Zero [s] ptr mem) // cond: s%16 == 0 && (s > 16*64 || config.noDuffDevice) // result: (LoweredZero ptr (ADDconst [s-16] ptr) mem) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 == 0 && (s > 16*64 || config.noDuffDevice)) { break } v.reset(OpARM64LoweredZero) v0 := b.NewValue0(v.Pos, OpARM64ADDconst, ptr.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(ptr) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteBlockARM64(b *Block) bool { typ := &b.Func.Config.Types switch b.Kind { case BlockARM64EQ: // match: (EQ (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (EQ (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (EQ (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMP x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMP { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPW x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPW { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] x) yes no) // result: (Z x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64Z, x) return true } // match: (EQ (CMPWconst [0] x) yes no) // result: (ZW x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64ZW, x) return true } // match: (EQ (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (TSTconst [c] x) yes no) // cond: oneBit(c) // result: (TBZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64TSTconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (EQ (TSTWconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64TSTWconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (EQ (FlagConstant [fc]) yes no) // cond: fc.eq() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.eq()) { break } b.Reset(BlockFirst) return true } // match: (EQ (FlagConstant [fc]) yes no) // cond: !fc.eq() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.eq()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64EQ, cmp) return true } case BlockARM64FGE: // match: (FGE (InvertFlags cmp) yes no) // result: (FLE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FLE, cmp) return true } case BlockARM64FGT: // match: (FGT (InvertFlags cmp) yes no) // result: (FLT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FLT, cmp) return true } case BlockARM64FLE: // match: (FLE (InvertFlags cmp) yes no) // result: (FGE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FGE, cmp) return true } case BlockARM64FLT: // match: (FLT (InvertFlags cmp) yes no) // result: (FGT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FGT, cmp) return true } case BlockARM64GE: // match: (GE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GE (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GE, v0) return true } break } // match: (GE (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GE (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GE, v0) return true } // match: (GE (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GE (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GE, v0) return true } break } // match: (GE (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GE (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GE, v0) return true } // match: (GE (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GEnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GEnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GEnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GEnoov, v0) return true } break } // match: (GE (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GEnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GEnoov, v0) return true } break } // match: (GE (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] x) yes no) // result: (TBZ [31] x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(31) return true } // match: (GE (CMPconst [0] x) yes no) // result: (TBZ [63] x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(63) return true } // match: (GE (FlagConstant [fc]) yes no) // cond: fc.ge() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ge()) { break } b.Reset(BlockFirst) return true } // match: (GE (FlagConstant [fc]) yes no) // cond: !fc.ge() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ge()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LE, cmp) return true } case BlockARM64GEnoov: // match: (GEnoov (FlagConstant [fc]) yes no) // cond: fc.geNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.geNoov()) { break } b.Reset(BlockFirst) return true } // match: (GEnoov (FlagConstant [fc]) yes no) // cond: !fc.geNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.geNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GEnoov (InvertFlags cmp) yes no) // result: (LEnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LEnoov, cmp) return true } case BlockARM64GT: // match: (GT (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GT (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GT, v0) return true } break } // match: (GT (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GT (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GT, v0) return true } // match: (GT (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GT (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GT, v0) return true } break } // match: (GT (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GT (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GT, v0) return true } // match: (GT (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GTnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GTnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GTnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GTnoov, v0) return true } break } // match: (GT (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GTnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GTnoov, v0) return true } break } // match: (GT (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (FlagConstant [fc]) yes no) // cond: fc.gt() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.gt()) { break } b.Reset(BlockFirst) return true } // match: (GT (FlagConstant [fc]) yes no) // cond: !fc.gt() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.gt()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LT, cmp) return true } case BlockARM64GTnoov: // match: (GTnoov (FlagConstant [fc]) yes no) // cond: fc.gtNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.gtNoov()) { break } b.Reset(BlockFirst) return true } // match: (GTnoov (FlagConstant [fc]) yes no) // cond: !fc.gtNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.gtNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GTnoov (InvertFlags cmp) yes no) // result: (LTnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LTnoov, cmp) return true } case BlockIf: // match: (If (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpARM64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64EQ, cc) return true } // match: (If (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpARM64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64NE, cc) return true } // match: (If (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpARM64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LT, cc) return true } // match: (If (LessThanU cc) yes no) // result: (ULT cc yes no) for b.Controls[0].Op == OpARM64LessThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULT, cc) return true } // match: (If (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpARM64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LE, cc) return true } // match: (If (LessEqualU cc) yes no) // result: (ULE cc yes no) for b.Controls[0].Op == OpARM64LessEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULE, cc) return true } // match: (If (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpARM64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GT, cc) return true } // match: (If (GreaterThanU cc) yes no) // result: (UGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGT, cc) return true } // match: (If (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GE, cc) return true } // match: (If (GreaterEqualU cc) yes no) // result: (UGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGE, cc) return true } // match: (If (LessThanF cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpARM64LessThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLT, cc) return true } // match: (If (LessEqualF cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpARM64LessEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLE, cc) return true } // match: (If (GreaterThanF cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGT, cc) return true } // match: (If (GreaterEqualF cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGE, cc) return true } // match: (If cond yes no) // result: (TBNZ [0] cond yes no) for { cond := b.Controls[0] b.resetWithControl(BlockARM64TBNZ, cond) b.AuxInt = int64ToAuxInt(0) return true } case BlockJumpTable: // match: (JumpTable idx) // result: (JUMPTABLE {makeJumpTableSym(b)} idx (MOVDaddr {makeJumpTableSym(b)} (SB))) for { idx := b.Controls[0] v0 := b.NewValue0(b.Pos, OpARM64MOVDaddr, typ.Uintptr) v0.Aux = symToAux(makeJumpTableSym(b)) v1 := b.NewValue0(b.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) b.resetWithControl2(BlockARM64JUMPTABLE, idx, v0) b.Aux = symToAux(makeJumpTableSym(b)) return true } case BlockARM64LE: // match: (LE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LE (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LE, v0) return true } break } // match: (LE (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LE (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LE, v0) return true } // match: (LE (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LE (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LE, v0) return true } break } // match: (LE (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LE (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LE, v0) return true } // match: (LE (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LEnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LEnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LEnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LEnoov, v0) return true } break } // match: (LE (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LEnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LEnoov, v0) return true } break } // match: (LE (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (FlagConstant [fc]) yes no) // cond: fc.le() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.le()) { break } b.Reset(BlockFirst) return true } // match: (LE (FlagConstant [fc]) yes no) // cond: !fc.le() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.le()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GE, cmp) return true } case BlockARM64LEnoov: // match: (LEnoov (FlagConstant [fc]) yes no) // cond: fc.leNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.leNoov()) { break } b.Reset(BlockFirst) return true } // match: (LEnoov (FlagConstant [fc]) yes no) // cond: !fc.leNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.leNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LEnoov (InvertFlags cmp) yes no) // result: (GEnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GEnoov, cmp) return true } case BlockARM64LT: // match: (LT (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LT (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LT, v0) return true } break } // match: (LT (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LT (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LT, v0) return true } // match: (LT (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LT (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LT, v0) return true } break } // match: (LT (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LT (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LT, v0) return true } // match: (LT (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LTnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LTnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LTnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LTnoov, v0) return true } break } // match: (LT (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LTnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LTnoov, v0) return true } break } // match: (LT (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] x) yes no) // result: (TBNZ [31] x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(31) return true } // match: (LT (CMPconst [0] x) yes no) // result: (TBNZ [63] x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(63) return true } // match: (LT (FlagConstant [fc]) yes no) // cond: fc.lt() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.lt()) { break } b.Reset(BlockFirst) return true } // match: (LT (FlagConstant [fc]) yes no) // cond: !fc.lt() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.lt()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GT, cmp) return true } case BlockARM64LTnoov: // match: (LTnoov (FlagConstant [fc]) yes no) // cond: fc.ltNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ltNoov()) { break } b.Reset(BlockFirst) return true } // match: (LTnoov (FlagConstant [fc]) yes no) // cond: !fc.ltNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ltNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LTnoov (InvertFlags cmp) yes no) // result: (GTnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GTnoov, cmp) return true } case BlockARM64NE: // match: (NE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (NE (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (NE (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (NE (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (NE (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMP x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (NE (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMP { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPW x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (NE (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPW { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] x) yes no) // result: (NZ x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64NZ, x) return true } // match: (NE (CMPWconst [0] x) yes no) // result: (NZW x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64NZW, x) return true } // match: (NE (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (TSTconst [c] x) yes no) // cond: oneBit(c) // result: (TBNZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64TSTconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (NE (TSTWconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBNZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64TSTWconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (NE (FlagConstant [fc]) yes no) // cond: fc.ne() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ne()) { break } b.Reset(BlockFirst) return true } // match: (NE (FlagConstant [fc]) yes no) // cond: !fc.ne() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ne()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64NE, cmp) return true } case BlockARM64NZ: // match: (NZ (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpARM64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64EQ, cc) return true } // match: (NZ (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpARM64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64NE, cc) return true } // match: (NZ (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpARM64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LT, cc) return true } // match: (NZ (LessThanU cc) yes no) // result: (ULT cc yes no) for b.Controls[0].Op == OpARM64LessThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULT, cc) return true } // match: (NZ (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpARM64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LE, cc) return true } // match: (NZ (LessEqualU cc) yes no) // result: (ULE cc yes no) for b.Controls[0].Op == OpARM64LessEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULE, cc) return true } // match: (NZ (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpARM64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GT, cc) return true } // match: (NZ (GreaterThanU cc) yes no) // result: (UGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGT, cc) return true } // match: (NZ (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GE, cc) return true } // match: (NZ (GreaterEqualU cc) yes no) // result: (UGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGE, cc) return true } // match: (NZ (LessThanF cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpARM64LessThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLT, cc) return true } // match: (NZ (LessEqualF cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpARM64LessEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLE, cc) return true } // match: (NZ (GreaterThanF cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGT, cc) return true } // match: (NZ (GreaterEqualF cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGE, cc) return true } // match: (NZ (ANDconst [c] x) yes no) // cond: oneBit(c) // result: (TBNZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (NZ (MOVDconst [0]) yes no) // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NZ (MOVDconst [c]) yes no) // cond: c != 0 // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(c != 0) { break } b.Reset(BlockFirst) return true } case BlockARM64NZW: // match: (NZW (ANDconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBNZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (NZW (MOVDconst [c]) yes no) // cond: int32(c) == 0 // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) == 0) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NZW (MOVDconst [c]) yes no) // cond: int32(c) != 0 // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) != 0) { break } b.Reset(BlockFirst) return true } case BlockARM64TBNZ: // match: (TBNZ [0] (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpARM64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64EQ, cc) return true } // match: (TBNZ [0] (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpARM64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64NE, cc) return true } // match: (TBNZ [0] (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpARM64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64LT, cc) return true } // match: (TBNZ [0] (LessThanU cc) yes no) // result: (ULT cc yes no) for b.Controls[0].Op == OpARM64LessThanU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64ULT, cc) return true } // match: (TBNZ [0] (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpARM64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64LE, cc) return true } // match: (TBNZ [0] (LessEqualU cc) yes no) // result: (ULE cc yes no) for b.Controls[0].Op == OpARM64LessEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64ULE, cc) return true } // match: (TBNZ [0] (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpARM64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64GT, cc) return true } // match: (TBNZ [0] (GreaterThanU cc) yes no) // result: (UGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64UGT, cc) return true } // match: (TBNZ [0] (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64GE, cc) return true } // match: (TBNZ [0] (GreaterEqualU cc) yes no) // result: (UGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64UGE, cc) return true } // match: (TBNZ [0] (LessThanF cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpARM64LessThanF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FLT, cc) return true } // match: (TBNZ [0] (LessEqualF cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpARM64LessEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FLE, cc) return true } // match: (TBNZ [0] (GreaterThanF cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FGT, cc) return true } // match: (TBNZ [0] (GreaterEqualF cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FGE, cc) return true } case BlockARM64UGE: // match: (UGE (FlagConstant [fc]) yes no) // cond: fc.uge() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.uge()) { break } b.Reset(BlockFirst) return true } // match: (UGE (FlagConstant [fc]) yes no) // cond: !fc.uge() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.uge()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64ULE, cmp) return true } case BlockARM64UGT: // match: (UGT (FlagConstant [fc]) yes no) // cond: fc.ugt() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ugt()) { break } b.Reset(BlockFirst) return true } // match: (UGT (FlagConstant [fc]) yes no) // cond: !fc.ugt() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ugt()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64ULT, cmp) return true } case BlockARM64ULE: // match: (ULE (FlagConstant [fc]) yes no) // cond: fc.ule() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ule()) { break } b.Reset(BlockFirst) return true } // match: (ULE (FlagConstant [fc]) yes no) // cond: !fc.ule() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ule()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64UGE, cmp) return true } case BlockARM64ULT: // match: (ULT (FlagConstant [fc]) yes no) // cond: fc.ult() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ult()) { break } b.Reset(BlockFirst) return true } // match: (ULT (FlagConstant [fc]) yes no) // cond: !fc.ult() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ult()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64UGT, cmp) return true } case BlockARM64Z: // match: (Z (ANDconst [c] x) yes no) // cond: oneBit(c) // result: (TBZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (Z (MOVDconst [0]) yes no) // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } b.Reset(BlockFirst) return true } // match: (Z (MOVDconst [c]) yes no) // cond: c != 0 // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(c != 0) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockARM64ZW: // match: (ZW (ANDconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (ZW (MOVDconst [c]) yes no) // cond: int32(c) == 0 // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) == 0) { break } b.Reset(BlockFirst) return true } // match: (ZW (MOVDconst [c]) yes no) // cond: int32(c) != 0 // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) != 0) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- y -- // Code generated from _gen/ARM64.rules using 'go generate'; DO NOT EDIT. package ssa import "cmd/compile/internal/types" func rewriteValueARM64(v *Value) bool { switch v.Op { case OpARM64ADCSflags: return rewriteValueARM64_OpARM64ADCSflags(v) case OpARM64ADD: return rewriteValueARM64_OpARM64ADD(v) case OpARM64ADDSflags: return rewriteValueARM64_OpARM64ADDSflags(v) case OpARM64ADDconst: return rewriteValueARM64_OpARM64ADDconst(v) case OpARM64ADDshiftLL: return rewriteValueARM64_OpARM64ADDshiftLL(v) case OpARM64ADDshiftRA: return rewriteValueARM64_OpARM64ADDshiftRA(v) case OpARM64ADDshiftRL: return rewriteValueARM64_OpARM64ADDshiftRL(v) case OpARM64AND: return rewriteValueARM64_OpARM64AND(v) case OpARM64ANDconst: return rewriteValueARM64_OpARM64ANDconst(v) case OpARM64ANDshiftLL: return rewriteValueARM64_OpARM64ANDshiftLL(v) case OpARM64ANDshiftRA: return rewriteValueARM64_OpARM64ANDshiftRA(v) case OpARM64ANDshiftRL: return rewriteValueARM64_OpARM64ANDshiftRL(v) case OpARM64ANDshiftRO: return rewriteValueARM64_OpARM64ANDshiftRO(v) case OpARM64BIC: return rewriteValueARM64_OpARM64BIC(v) case OpARM64BICshiftLL: return rewriteValueARM64_OpARM64BICshiftLL(v) case OpARM64BICshiftRA: return rewriteValueARM64_OpARM64BICshiftRA(v) case OpARM64BICshiftRL: return rewriteValueARM64_OpARM64BICshiftRL(v) case OpARM64BICshiftRO: return rewriteValueARM64_OpARM64BICshiftRO(v) case OpARM64CMN: return rewriteValueARM64_OpARM64CMN(v) case OpARM64CMNW: return rewriteValueARM64_OpARM64CMNW(v) case OpARM64CMNWconst: return rewriteValueARM64_OpARM64CMNWconst(v) case OpARM64CMNconst: return rewriteValueARM64_OpARM64CMNconst(v) case OpARM64CMNshiftLL: return rewriteValueARM64_OpARM64CMNshiftLL(v) case OpARM64CMNshiftRA: return rewriteValueARM64_OpARM64CMNshiftRA(v) case OpARM64CMNshiftRL: return rewriteValueARM64_OpARM64CMNshiftRL(v) case OpARM64CMP: return rewriteValueARM64_OpARM64CMP(v) case OpARM64CMPW: return rewriteValueARM64_OpARM64CMPW(v) case OpARM64CMPWconst: return rewriteValueARM64_OpARM64CMPWconst(v) case OpARM64CMPconst: return rewriteValueARM64_OpARM64CMPconst(v) case OpARM64CMPshiftLL: return rewriteValueARM64_OpARM64CMPshiftLL(v) case OpARM64CMPshiftRA: return rewriteValueARM64_OpARM64CMPshiftRA(v) case OpARM64CMPshiftRL: return rewriteValueARM64_OpARM64CMPshiftRL(v) case OpARM64CSEL: return rewriteValueARM64_OpARM64CSEL(v) case OpARM64CSEL0: return rewriteValueARM64_OpARM64CSEL0(v) case OpARM64CSETM: return rewriteValueARM64_OpARM64CSETM(v) case OpARM64CSINC: return rewriteValueARM64_OpARM64CSINC(v) case OpARM64CSINV: return rewriteValueARM64_OpARM64CSINV(v) case OpARM64CSNEG: return rewriteValueARM64_OpARM64CSNEG(v) case OpARM64DIV: return rewriteValueARM64_OpARM64DIV(v) case OpARM64DIVW: return rewriteValueARM64_OpARM64DIVW(v) case OpARM64EON: return rewriteValueARM64_OpARM64EON(v) case OpARM64EONshiftLL: return rewriteValueARM64_OpARM64EONshiftLL(v) case OpARM64EONshiftRA: return rewriteValueARM64_OpARM64EONshiftRA(v) case OpARM64EONshiftRL: return rewriteValueARM64_OpARM64EONshiftRL(v) case OpARM64EONshiftRO: return rewriteValueARM64_OpARM64EONshiftRO(v) case OpARM64Equal: return rewriteValueARM64_OpARM64Equal(v) case OpARM64FADDD: return rewriteValueARM64_OpARM64FADDD(v) case OpARM64FADDS: return rewriteValueARM64_OpARM64FADDS(v) case OpARM64FCMPD: return rewriteValueARM64_OpARM64FCMPD(v) case OpARM64FCMPS: return rewriteValueARM64_OpARM64FCMPS(v) case OpARM64FMOVDfpgp: return rewriteValueARM64_OpARM64FMOVDfpgp(v) case OpARM64FMOVDgpfp: return rewriteValueARM64_OpARM64FMOVDgpfp(v) case OpARM64FMOVDload: return rewriteValueARM64_OpARM64FMOVDload(v) case OpARM64FMOVDloadidx: return rewriteValueARM64_OpARM64FMOVDloadidx(v) case OpARM64FMOVDloadidx8: return rewriteValueARM64_OpARM64FMOVDloadidx8(v) case OpARM64FMOVDstore: return rewriteValueARM64_OpARM64FMOVDstore(v) case OpARM64FMOVDstoreidx: return rewriteValueARM64_OpARM64FMOVDstoreidx(v) case OpARM64FMOVDstoreidx8: return rewriteValueARM64_OpARM64FMOVDstoreidx8(v) case OpARM64FMOVSload: return rewriteValueARM64_OpARM64FMOVSload(v) case OpARM64FMOVSloadidx: return rewriteValueARM64_OpARM64FMOVSloadidx(v) case OpARM64FMOVSloadidx4: return rewriteValueARM64_OpARM64FMOVSloadidx4(v) case OpARM64FMOVSstore: return rewriteValueARM64_OpARM64FMOVSstore(v) case OpARM64FMOVSstoreidx: return rewriteValueARM64_OpARM64FMOVSstoreidx(v) case OpARM64FMOVSstoreidx4: return rewriteValueARM64_OpARM64FMOVSstoreidx4(v) case OpARM64FMULD: return rewriteValueARM64_OpARM64FMULD(v) case OpARM64FMULS: return rewriteValueARM64_OpARM64FMULS(v) case OpARM64FNEGD: return rewriteValueARM64_OpARM64FNEGD(v) case OpARM64FNEGS: return rewriteValueARM64_OpARM64FNEGS(v) case OpARM64FNMULD: return rewriteValueARM64_OpARM64FNMULD(v) case OpARM64FNMULS: return rewriteValueARM64_OpARM64FNMULS(v) case OpARM64FSUBD: return rewriteValueARM64_OpARM64FSUBD(v) case OpARM64FSUBS: return rewriteValueARM64_OpARM64FSUBS(v) case OpARM64GreaterEqual: return rewriteValueARM64_OpARM64GreaterEqual(v) case OpARM64GreaterEqualF: return rewriteValueARM64_OpARM64GreaterEqualF(v) case OpARM64GreaterEqualU: return rewriteValueARM64_OpARM64GreaterEqualU(v) case OpARM64GreaterThan: return rewriteValueARM64_OpARM64GreaterThan(v) case OpARM64GreaterThanF: return rewriteValueARM64_OpARM64GreaterThanF(v) case OpARM64GreaterThanU: return rewriteValueARM64_OpARM64GreaterThanU(v) case OpARM64LDP: return rewriteValueARM64_OpARM64LDP(v) case OpARM64LessEqual: return rewriteValueARM64_OpARM64LessEqual(v) case OpARM64LessEqualF: return rewriteValueARM64_OpARM64LessEqualF(v) case OpARM64LessEqualU: return rewriteValueARM64_OpARM64LessEqualU(v) case OpARM64LessThan: return rewriteValueARM64_OpARM64LessThan(v) case OpARM64LessThanF: return rewriteValueARM64_OpARM64LessThanF(v) case OpARM64LessThanU: return rewriteValueARM64_OpARM64LessThanU(v) case OpARM64MADD: return rewriteValueARM64_OpARM64MADD(v) case OpARM64MADDW: return rewriteValueARM64_OpARM64MADDW(v) case OpARM64MNEG: return rewriteValueARM64_OpARM64MNEG(v) case OpARM64MNEGW: return rewriteValueARM64_OpARM64MNEGW(v) case OpARM64MOD: return rewriteValueARM64_OpARM64MOD(v) case OpARM64MODW: return rewriteValueARM64_OpARM64MODW(v) case OpARM64MOVBUload: return rewriteValueARM64_OpARM64MOVBUload(v) case OpARM64MOVBUloadidx: return rewriteValueARM64_OpARM64MOVBUloadidx(v) case OpARM64MOVBUreg: return rewriteValueARM64_OpARM64MOVBUreg(v) case OpARM64MOVBload: return rewriteValueARM64_OpARM64MOVBload(v) case OpARM64MOVBloadidx: return rewriteValueARM64_OpARM64MOVBloadidx(v) case OpARM64MOVBreg: return rewriteValueARM64_OpARM64MOVBreg(v) case OpARM64MOVBstore: return rewriteValueARM64_OpARM64MOVBstore(v) case OpARM64MOVBstoreidx: return rewriteValueARM64_OpARM64MOVBstoreidx(v) case OpARM64MOVBstorezero: return rewriteValueARM64_OpARM64MOVBstorezero(v) case OpARM64MOVBstorezeroidx: return rewriteValueARM64_OpARM64MOVBstorezeroidx(v) case OpARM64MOVDload: return rewriteValueARM64_OpARM64MOVDload(v) case OpARM64MOVDloadidx: return rewriteValueARM64_OpARM64MOVDloadidx(v) case OpARM64MOVDloadidx8: return rewriteValueARM64_OpARM64MOVDloadidx8(v) case OpARM64MOVDnop: return rewriteValueARM64_OpARM64MOVDnop(v) case OpARM64MOVDreg: return rewriteValueARM64_OpARM64MOVDreg(v) case OpARM64MOVDstore: return rewriteValueARM64_OpARM64MOVDstore(v) case OpARM64MOVDstoreidx: return rewriteValueARM64_OpARM64MOVDstoreidx(v) case OpARM64MOVDstoreidx8: return rewriteValueARM64_OpARM64MOVDstoreidx8(v) case OpARM64MOVDstorezero: return rewriteValueARM64_OpARM64MOVDstorezero(v) case OpARM64MOVDstorezeroidx: return rewriteValueARM64_OpARM64MOVDstorezeroidx(v) case OpARM64MOVDstorezeroidx8: return rewriteValueARM64_OpARM64MOVDstorezeroidx8(v) case OpARM64MOVHUload: return rewriteValueARM64_OpARM64MOVHUload(v) case OpARM64MOVHUloadidx: return rewriteValueARM64_OpARM64MOVHUloadidx(v) case OpARM64MOVHUloadidx2: return rewriteValueARM64_OpARM64MOVHUloadidx2(v) case OpARM64MOVHUreg: return rewriteValueARM64_OpARM64MOVHUreg(v) case OpARM64MOVHload: return rewriteValueARM64_OpARM64MOVHload(v) case OpARM64MOVHloadidx: return rewriteValueARM64_OpARM64MOVHloadidx(v) case OpARM64MOVHloadidx2: return rewriteValueARM64_OpARM64MOVHloadidx2(v) case OpARM64MOVHreg: return rewriteValueARM64_OpARM64MOVHreg(v) case OpARM64MOVHstore: return rewriteValueARM64_OpARM64MOVHstore(v) case OpARM64MOVHstoreidx: return rewriteValueARM64_OpARM64MOVHstoreidx(v) case OpARM64MOVHstoreidx2: return rewriteValueARM64_OpARM64MOVHstoreidx2(v) case OpARM64MOVHstorezero: return rewriteValueARM64_OpARM64MOVHstorezero(v) case OpARM64MOVHstorezeroidx: return rewriteValueARM64_OpARM64MOVHstorezeroidx(v) case OpARM64MOVHstorezeroidx2: return rewriteValueARM64_OpARM64MOVHstorezeroidx2(v) case OpARM64MOVQstorezero: return rewriteValueARM64_OpARM64MOVQstorezero(v) case OpARM64MOVWUload: return rewriteValueARM64_OpARM64MOVWUload(v) case OpARM64MOVWUloadidx: return rewriteValueARM64_OpARM64MOVWUloadidx(v) case OpARM64MOVWUloadidx4: return rewriteValueARM64_OpARM64MOVWUloadidx4(v) case OpARM64MOVWUreg: return rewriteValueARM64_OpARM64MOVWUreg(v) case OpARM64MOVWload: return rewriteValueARM64_OpARM64MOVWload(v) case OpARM64MOVWloadidx: return rewriteValueARM64_OpARM64MOVWloadidx(v) case OpARM64MOVWloadidx4: return rewriteValueARM64_OpARM64MOVWloadidx4(v) case OpARM64MOVWreg: return rewriteValueARM64_OpARM64MOVWreg(v) case OpARM64MOVWstore: return rewriteValueARM64_OpARM64MOVWstore(v) case OpARM64MOVWstoreidx: return rewriteValueARM64_OpARM64MOVWstoreidx(v) case OpARM64MOVWstoreidx4: return rewriteValueARM64_OpARM64MOVWstoreidx4(v) case OpARM64MOVWstorezero: return rewriteValueARM64_OpARM64MOVWstorezero(v) case OpARM64MOVWstorezeroidx: return rewriteValueARM64_OpARM64MOVWstorezeroidx(v) case OpARM64MOVWstorezeroidx4: return rewriteValueARM64_OpARM64MOVWstorezeroidx4(v) case OpARM64MSUB: return rewriteValueARM64_OpARM64MSUB(v) case OpARM64MSUBW: return rewriteValueARM64_OpARM64MSUBW(v) case OpARM64MUL: return rewriteValueARM64_OpARM64MUL(v) case OpARM64MULW: return rewriteValueARM64_OpARM64MULW(v) case OpARM64MVN: return rewriteValueARM64_OpARM64MVN(v) case OpARM64MVNshiftLL: return rewriteValueARM64_OpARM64MVNshiftLL(v) case OpARM64MVNshiftRA: return rewriteValueARM64_OpARM64MVNshiftRA(v) case OpARM64MVNshiftRL: return rewriteValueARM64_OpARM64MVNshiftRL(v) case OpARM64MVNshiftRO: return rewriteValueARM64_OpARM64MVNshiftRO(v) case OpARM64NEG: return rewriteValueARM64_OpARM64NEG(v) case OpARM64NEGshiftLL: return rewriteValueARM64_OpARM64NEGshiftLL(v) case OpARM64NEGshiftRA: return rewriteValueARM64_OpARM64NEGshiftRA(v) case OpARM64NEGshiftRL: return rewriteValueARM64_OpARM64NEGshiftRL(v) case OpARM64NotEqual: return rewriteValueARM64_OpARM64NotEqual(v) case OpARM64OR: return rewriteValueARM64_OpARM64OR(v) case OpARM64ORN: return rewriteValueARM64_OpARM64ORN(v) case OpARM64ORNshiftLL: return rewriteValueARM64_OpARM64ORNshiftLL(v) case OpARM64ORNshiftRA: return rewriteValueARM64_OpARM64ORNshiftRA(v) case OpARM64ORNshiftRL: return rewriteValueARM64_OpARM64ORNshiftRL(v) case OpARM64ORNshiftRO: return rewriteValueARM64_OpARM64ORNshiftRO(v) case OpARM64ORconst: return rewriteValueARM64_OpARM64ORconst(v) case OpARM64ORshiftLL: return rewriteValueARM64_OpARM64ORshiftLL(v) case OpARM64ORshiftRA: return rewriteValueARM64_OpARM64ORshiftRA(v) case OpARM64ORshiftRL: return rewriteValueARM64_OpARM64ORshiftRL(v) case OpARM64ORshiftRO: return rewriteValueARM64_OpARM64ORshiftRO(v) case OpARM64REV: return rewriteValueARM64_OpARM64REV(v) case OpARM64REVW: return rewriteValueARM64_OpARM64REVW(v) case OpARM64ROR: return rewriteValueARM64_OpARM64ROR(v) case OpARM64RORW: return rewriteValueARM64_OpARM64RORW(v) case OpARM64SBCSflags: return rewriteValueARM64_OpARM64SBCSflags(v) case OpARM64SLL: return rewriteValueARM64_OpARM64SLL(v) case OpARM64SLLconst: return rewriteValueARM64_OpARM64SLLconst(v) case OpARM64SRA: return rewriteValueARM64_OpARM64SRA(v) case OpARM64SRAconst: return rewriteValueARM64_OpARM64SRAconst(v) case OpARM64SRL: return rewriteValueARM64_OpARM64SRL(v) case OpARM64SRLconst: return rewriteValueARM64_OpARM64SRLconst(v) case OpARM64STP: return rewriteValueARM64_OpARM64STP(v) case OpARM64SUB: return rewriteValueARM64_OpARM64SUB(v) case OpARM64SUBconst: return rewriteValueARM64_OpARM64SUBconst(v) case OpARM64SUBshiftLL: return rewriteValueARM64_OpARM64SUBshiftLL(v) case OpARM64SUBshiftRA: return rewriteValueARM64_OpARM64SUBshiftRA(v) case OpARM64SUBshiftRL: return rewriteValueARM64_OpARM64SUBshiftRL(v) case OpARM64TST: return rewriteValueARM64_OpARM64TST(v) case OpARM64TSTW: return rewriteValueARM64_OpARM64TSTW(v) case OpARM64TSTWconst: return rewriteValueARM64_OpARM64TSTWconst(v) case OpARM64TSTconst: return rewriteValueARM64_OpARM64TSTconst(v) case OpARM64TSTshiftLL: return rewriteValueARM64_OpARM64TSTshiftLL(v) case OpARM64TSTshiftRA: return rewriteValueARM64_OpARM64TSTshiftRA(v) case OpARM64TSTshiftRL: return rewriteValueARM64_OpARM64TSTshiftRL(v) case OpARM64TSTshiftRO: return rewriteValueARM64_OpARM64TSTshiftRO(v) case OpARM64UBFIZ: return rewriteValueARM64_OpARM64UBFIZ(v) case OpARM64UBFX: return rewriteValueARM64_OpARM64UBFX(v) case OpARM64UDIV: return rewriteValueARM64_OpARM64UDIV(v) case OpARM64UDIVW: return rewriteValueARM64_OpARM64UDIVW(v) case OpARM64UMOD: return rewriteValueARM64_OpARM64UMOD(v) case OpARM64UMODW: return rewriteValueARM64_OpARM64UMODW(v) case OpARM64XOR: return rewriteValueARM64_OpARM64XOR(v) case OpARM64XORconst: return rewriteValueARM64_OpARM64XORconst(v) case OpARM64XORshiftLL: return rewriteValueARM64_OpARM64XORshiftLL(v) case OpARM64XORshiftRA: return rewriteValueARM64_OpARM64XORshiftRA(v) case OpARM64XORshiftRL: return rewriteValueARM64_OpARM64XORshiftRL(v) case OpARM64XORshiftRO: return rewriteValueARM64_OpARM64XORshiftRO(v) case OpAbs: v.Op = OpARM64FABSD return true case OpAdd16: v.Op = OpARM64ADD return true case OpAdd32: v.Op = OpARM64ADD return true case OpAdd32F: v.Op = OpARM64FADDS return true case OpAdd64: v.Op = OpARM64ADD return true case OpAdd64F: v.Op = OpARM64FADDD return true case OpAdd8: v.Op = OpARM64ADD return true case OpAddPtr: v.Op = OpARM64ADD return true case OpAddr: return rewriteValueARM64_OpAddr(v) case OpAnd16: v.Op = OpARM64AND return true case OpAnd32: v.Op = OpARM64AND return true case OpAnd64: v.Op = OpARM64AND return true case OpAnd8: v.Op = OpARM64AND return true case OpAndB: v.Op = OpARM64AND return true case OpAtomicAdd32: v.Op = OpARM64LoweredAtomicAdd32 return true case OpAtomicAdd32Variant: v.Op = OpARM64LoweredAtomicAdd32Variant return true case OpAtomicAdd64: v.Op = OpARM64LoweredAtomicAdd64 return true case OpAtomicAdd64Variant: v.Op = OpARM64LoweredAtomicAdd64Variant return true case OpAtomicAnd32: return rewriteValueARM64_OpAtomicAnd32(v) case OpAtomicAnd32Variant: return rewriteValueARM64_OpAtomicAnd32Variant(v) case OpAtomicAnd8: return rewriteValueARM64_OpAtomicAnd8(v) case OpAtomicAnd8Variant: return rewriteValueARM64_OpAtomicAnd8Variant(v) case OpAtomicCompareAndSwap32: v.Op = OpARM64LoweredAtomicCas32 return true case OpAtomicCompareAndSwap32Variant: v.Op = OpARM64LoweredAtomicCas32Variant return true case OpAtomicCompareAndSwap64: v.Op = OpARM64LoweredAtomicCas64 return true case OpAtomicCompareAndSwap64Variant: v.Op = OpARM64LoweredAtomicCas64Variant return true case OpAtomicExchange32: v.Op = OpARM64LoweredAtomicExchange32 return true case OpAtomicExchange32Variant: v.Op = OpARM64LoweredAtomicExchange32Variant return true case OpAtomicExchange64: v.Op = OpARM64LoweredAtomicExchange64 return true case OpAtomicExchange64Variant: v.Op = OpARM64LoweredAtomicExchange64Variant return true case OpAtomicLoad32: v.Op = OpARM64LDARW return true case OpAtomicLoad64: v.Op = OpARM64LDAR return true case OpAtomicLoad8: v.Op = OpARM64LDARB return true case OpAtomicLoadPtr: v.Op = OpARM64LDAR return true case OpAtomicOr32: return rewriteValueARM64_OpAtomicOr32(v) case OpAtomicOr32Variant: return rewriteValueARM64_OpAtomicOr32Variant(v) case OpAtomicOr8: return rewriteValueARM64_OpAtomicOr8(v) case OpAtomicOr8Variant: return rewriteValueARM64_OpAtomicOr8Variant(v) case OpAtomicStore32: v.Op = OpARM64STLRW return true case OpAtomicStore64: v.Op = OpARM64STLR return true case OpAtomicStore8: v.Op = OpARM64STLRB return true case OpAtomicStorePtrNoWB: v.Op = OpARM64STLR return true case OpAvg64u: return rewriteValueARM64_OpAvg64u(v) case OpBitLen32: return rewriteValueARM64_OpBitLen32(v) case OpBitLen64: return rewriteValueARM64_OpBitLen64(v) case OpBitRev16: return rewriteValueARM64_OpBitRev16(v) case OpBitRev32: v.Op = OpARM64RBITW return true case OpBitRev64: v.Op = OpARM64RBIT return true case OpBitRev8: return rewriteValueARM64_OpBitRev8(v) case OpBswap16: v.Op = OpARM64REV16W return true case OpBswap32: v.Op = OpARM64REVW return true case OpBswap64: v.Op = OpARM64REV return true case OpCeil: v.Op = OpARM64FRINTPD return true case OpClosureCall: v.Op = OpARM64CALLclosure return true case OpCom16: v.Op = OpARM64MVN return true case OpCom32: v.Op = OpARM64MVN return true case OpCom64: v.Op = OpARM64MVN return true case OpCom8: v.Op = OpARM64MVN return true case OpCondSelect: return rewriteValueARM64_OpCondSelect(v) case OpConst16: return rewriteValueARM64_OpConst16(v) case OpConst32: return rewriteValueARM64_OpConst32(v) case OpConst32F: return rewriteValueARM64_OpConst32F(v) case OpConst64: return rewriteValueARM64_OpConst64(v) case OpConst64F: return rewriteValueARM64_OpConst64F(v) case OpConst8: return rewriteValueARM64_OpConst8(v) case OpConstBool: return rewriteValueARM64_OpConstBool(v) case OpConstNil: return rewriteValueARM64_OpConstNil(v) case OpCtz16: return rewriteValueARM64_OpCtz16(v) case OpCtz16NonZero: v.Op = OpCtz32 return true case OpCtz32: return rewriteValueARM64_OpCtz32(v) case OpCtz32NonZero: v.Op = OpCtz32 return true case OpCtz64: return rewriteValueARM64_OpCtz64(v) case OpCtz64NonZero: v.Op = OpCtz64 return true case OpCtz8: return rewriteValueARM64_OpCtz8(v) case OpCtz8NonZero: v.Op = OpCtz32 return true case OpCvt32Fto32: v.Op = OpARM64FCVTZSSW return true case OpCvt32Fto32U: v.Op = OpARM64FCVTZUSW return true case OpCvt32Fto64: v.Op = OpARM64FCVTZSS return true case OpCvt32Fto64F: v.Op = OpARM64FCVTSD return true case OpCvt32Fto64U: v.Op = OpARM64FCVTZUS return true case OpCvt32Uto32F: v.Op = OpARM64UCVTFWS return true case OpCvt32Uto64F: v.Op = OpARM64UCVTFWD return true case OpCvt32to32F: v.Op = OpARM64SCVTFWS return true case OpCvt32to64F: v.Op = OpARM64SCVTFWD return true case OpCvt64Fto32: v.Op = OpARM64FCVTZSDW return true case OpCvt64Fto32F: v.Op = OpARM64FCVTDS return true case OpCvt64Fto32U: v.Op = OpARM64FCVTZUDW return true case OpCvt64Fto64: v.Op = OpARM64FCVTZSD return true case OpCvt64Fto64U: v.Op = OpARM64FCVTZUD return true case OpCvt64Uto32F: v.Op = OpARM64UCVTFS return true case OpCvt64Uto64F: v.Op = OpARM64UCVTFD return true case OpCvt64to32F: v.Op = OpARM64SCVTFS return true case OpCvt64to64F: v.Op = OpARM64SCVTFD return true case OpCvtBoolToUint8: v.Op = OpCopy return true case OpDiv16: return rewriteValueARM64_OpDiv16(v) case OpDiv16u: return rewriteValueARM64_OpDiv16u(v) case OpDiv32: return rewriteValueARM64_OpDiv32(v) case OpDiv32F: v.Op = OpARM64FDIVS return true case OpDiv32u: v.Op = OpARM64UDIVW return true case OpDiv64: return rewriteValueARM64_OpDiv64(v) case OpDiv64F: v.Op = OpARM64FDIVD return true case OpDiv64u: v.Op = OpARM64UDIV return true case OpDiv8: return rewriteValueARM64_OpDiv8(v) case OpDiv8u: return rewriteValueARM64_OpDiv8u(v) case OpEq16: return rewriteValueARM64_OpEq16(v) case OpEq32: return rewriteValueARM64_OpEq32(v) case OpEq32F: return rewriteValueARM64_OpEq32F(v) case OpEq64: return rewriteValueARM64_OpEq64(v) case OpEq64F: return rewriteValueARM64_OpEq64F(v) case OpEq8: return rewriteValueARM64_OpEq8(v) case OpEqB: return rewriteValueARM64_OpEqB(v) case OpEqPtr: return rewriteValueARM64_OpEqPtr(v) case OpFMA: return rewriteValueARM64_OpFMA(v) case OpFloor: v.Op = OpARM64FRINTMD return true case OpGetCallerPC: v.Op = OpARM64LoweredGetCallerPC return true case OpGetCallerSP: v.Op = OpARM64LoweredGetCallerSP return true case OpGetClosurePtr: v.Op = OpARM64LoweredGetClosurePtr return true case OpHmul32: return rewriteValueARM64_OpHmul32(v) case OpHmul32u: return rewriteValueARM64_OpHmul32u(v) case OpHmul64: v.Op = OpARM64MULH return true case OpHmul64u: v.Op = OpARM64UMULH return true case OpInterCall: v.Op = OpARM64CALLinter return true case OpIsInBounds: return rewriteValueARM64_OpIsInBounds(v) case OpIsNonNil: return rewriteValueARM64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueARM64_OpIsSliceInBounds(v) case OpLeq16: return rewriteValueARM64_OpLeq16(v) case OpLeq16U: return rewriteValueARM64_OpLeq16U(v) case OpLeq32: return rewriteValueARM64_OpLeq32(v) case OpLeq32F: return rewriteValueARM64_OpLeq32F(v) case OpLeq32U: return rewriteValueARM64_OpLeq32U(v) case OpLeq64: return rewriteValueARM64_OpLeq64(v) case OpLeq64F: return rewriteValueARM64_OpLeq64F(v) case OpLeq64U: return rewriteValueARM64_OpLeq64U(v) case OpLeq8: return rewriteValueARM64_OpLeq8(v) case OpLeq8U: return rewriteValueARM64_OpLeq8U(v) case OpLess16: return rewriteValueARM64_OpLess16(v) case OpLess16U: return rewriteValueARM64_OpLess16U(v) case OpLess32: return rewriteValueARM64_OpLess32(v) case OpLess32F: return rewriteValueARM64_OpLess32F(v) case OpLess32U: return rewriteValueARM64_OpLess32U(v) case OpLess64: return rewriteValueARM64_OpLess64(v) case OpLess64F: return rewriteValueARM64_OpLess64F(v) case OpLess64U: return rewriteValueARM64_OpLess64U(v) case OpLess8: return rewriteValueARM64_OpLess8(v) case OpLess8U: return rewriteValueARM64_OpLess8U(v) case OpLoad: return rewriteValueARM64_OpLoad(v) case OpLocalAddr: return rewriteValueARM64_OpLocalAddr(v) case OpLsh16x16: return rewriteValueARM64_OpLsh16x16(v) case OpLsh16x32: return rewriteValueARM64_OpLsh16x32(v) case OpLsh16x64: return rewriteValueARM64_OpLsh16x64(v) case OpLsh16x8: return rewriteValueARM64_OpLsh16x8(v) case OpLsh32x16: return rewriteValueARM64_OpLsh32x16(v) case OpLsh32x32: return rewriteValueARM64_OpLsh32x32(v) case OpLsh32x64: return rewriteValueARM64_OpLsh32x64(v) case OpLsh32x8: return rewriteValueARM64_OpLsh32x8(v) case OpLsh64x16: return rewriteValueARM64_OpLsh64x16(v) case OpLsh64x32: return rewriteValueARM64_OpLsh64x32(v) case OpLsh64x64: return rewriteValueARM64_OpLsh64x64(v) case OpLsh64x8: return rewriteValueARM64_OpLsh64x8(v) case OpLsh8x16: return rewriteValueARM64_OpLsh8x16(v) case OpLsh8x32: return rewriteValueARM64_OpLsh8x32(v) case OpLsh8x64: return rewriteValueARM64_OpLsh8x64(v) case OpLsh8x8: return rewriteValueARM64_OpLsh8x8(v) case OpMod16: return rewriteValueARM64_OpMod16(v) case OpMod16u: return rewriteValueARM64_OpMod16u(v) case OpMod32: return rewriteValueARM64_OpMod32(v) case OpMod32u: v.Op = OpARM64UMODW return true case OpMod64: return rewriteValueARM64_OpMod64(v) case OpMod64u: v.Op = OpARM64UMOD return true case OpMod8: return rewriteValueARM64_OpMod8(v) case OpMod8u: return rewriteValueARM64_OpMod8u(v) case OpMove: return rewriteValueARM64_OpMove(v) case OpMul16: v.Op = OpARM64MULW return true case OpMul32: v.Op = OpARM64MULW return true case OpMul32F: v.Op = OpARM64FMULS return true case OpMul64: v.Op = OpARM64MUL return true case OpMul64F: v.Op = OpARM64FMULD return true case OpMul8: v.Op = OpARM64MULW return true case OpNeg16: v.Op = OpARM64NEG return true case OpNeg32: v.Op = OpARM64NEG return true case OpNeg32F: v.Op = OpARM64FNEGS return true case OpNeg64: v.Op = OpARM64NEG return true case OpNeg64F: v.Op = OpARM64FNEGD return true case OpNeg8: v.Op = OpARM64NEG return true case OpNeq16: return rewriteValueARM64_OpNeq16(v) case OpNeq32: return rewriteValueARM64_OpNeq32(v) case OpNeq32F: return rewriteValueARM64_OpNeq32F(v) case OpNeq64: return rewriteValueARM64_OpNeq64(v) case OpNeq64F: return rewriteValueARM64_OpNeq64F(v) case OpNeq8: return rewriteValueARM64_OpNeq8(v) case OpNeqB: v.Op = OpARM64XOR return true case OpNeqPtr: return rewriteValueARM64_OpNeqPtr(v) case OpNilCheck: v.Op = OpARM64LoweredNilCheck return true case OpNot: return rewriteValueARM64_OpNot(v) case OpOffPtr: return rewriteValueARM64_OpOffPtr(v) case OpOr16: v.Op = OpARM64OR return true case OpOr32: v.Op = OpARM64OR return true case OpOr64: v.Op = OpARM64OR return true case OpOr8: v.Op = OpARM64OR return true case OpOrB: v.Op = OpARM64OR return true case OpPanicBounds: return rewriteValueARM64_OpPanicBounds(v) case OpPopCount16: return rewriteValueARM64_OpPopCount16(v) case OpPopCount32: return rewriteValueARM64_OpPopCount32(v) case OpPopCount64: return rewriteValueARM64_OpPopCount64(v) case OpPrefetchCache: return rewriteValueARM64_OpPrefetchCache(v) case OpPrefetchCacheStreamed: return rewriteValueARM64_OpPrefetchCacheStreamed(v) case OpPubBarrier: return rewriteValueARM64_OpPubBarrier(v) case OpRotateLeft16: return rewriteValueARM64_OpRotateLeft16(v) case OpRotateLeft32: return rewriteValueARM64_OpRotateLeft32(v) case OpRotateLeft64: return rewriteValueARM64_OpRotateLeft64(v) case OpRotateLeft8: return rewriteValueARM64_OpRotateLeft8(v) case OpRound: v.Op = OpARM64FRINTAD return true case OpRound32F: v.Op = OpARM64LoweredRound32F return true case OpRound64F: v.Op = OpARM64LoweredRound64F return true case OpRoundToEven: v.Op = OpARM64FRINTND return true case OpRsh16Ux16: return rewriteValueARM64_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValueARM64_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValueARM64_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValueARM64_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValueARM64_OpRsh16x16(v) case OpRsh16x32: return rewriteValueARM64_OpRsh16x32(v) case OpRsh16x64: return rewriteValueARM64_OpRsh16x64(v) case OpRsh16x8: return rewriteValueARM64_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValueARM64_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValueARM64_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValueARM64_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValueARM64_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValueARM64_OpRsh32x16(v) case OpRsh32x32: return rewriteValueARM64_OpRsh32x32(v) case OpRsh32x64: return rewriteValueARM64_OpRsh32x64(v) case OpRsh32x8: return rewriteValueARM64_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValueARM64_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValueARM64_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValueARM64_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValueARM64_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValueARM64_OpRsh64x16(v) case OpRsh64x32: return rewriteValueARM64_OpRsh64x32(v) case OpRsh64x64: return rewriteValueARM64_OpRsh64x64(v) case OpRsh64x8: return rewriteValueARM64_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValueARM64_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValueARM64_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValueARM64_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValueARM64_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValueARM64_OpRsh8x16(v) case OpRsh8x32: return rewriteValueARM64_OpRsh8x32(v) case OpRsh8x64: return rewriteValueARM64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueARM64_OpRsh8x8(v) case OpSelect0: return rewriteValueARM64_OpSelect0(v) case OpSelect1: return rewriteValueARM64_OpSelect1(v) case OpSelectN: return rewriteValueARM64_OpSelectN(v) case OpSignExt16to32: v.Op = OpARM64MOVHreg return true case OpSignExt16to64: v.Op = OpARM64MOVHreg return true case OpSignExt32to64: v.Op = OpARM64MOVWreg return true case OpSignExt8to16: v.Op = OpARM64MOVBreg return true case OpSignExt8to32: v.Op = OpARM64MOVBreg return true case OpSignExt8to64: v.Op = OpARM64MOVBreg return true case OpSlicemask: return rewriteValueARM64_OpSlicemask(v) case OpSqrt: v.Op = OpARM64FSQRTD return true case OpSqrt32: v.Op = OpARM64FSQRTS return true case OpStaticCall: v.Op = OpARM64CALLstatic return true case OpStore: return rewriteValueARM64_OpStore(v) case OpSub16: v.Op = OpARM64SUB return true case OpSub32: v.Op = OpARM64SUB return true case OpSub32F: v.Op = OpARM64FSUBS return true case OpSub64: v.Op = OpARM64SUB return true case OpSub64F: v.Op = OpARM64FSUBD return true case OpSub8: v.Op = OpARM64SUB return true case OpSubPtr: v.Op = OpARM64SUB return true case OpTailCall: v.Op = OpARM64CALLtail return true case OpTrunc: v.Op = OpARM64FRINTZD return true case OpTrunc16to8: v.Op = OpCopy return true case OpTrunc32to16: v.Op = OpCopy return true case OpTrunc32to8: v.Op = OpCopy return true case OpTrunc64to16: v.Op = OpCopy return true case OpTrunc64to32: v.Op = OpCopy return true case OpTrunc64to8: v.Op = OpCopy return true case OpWB: v.Op = OpARM64LoweredWB return true case OpXor16: v.Op = OpARM64XOR return true case OpXor32: v.Op = OpARM64XOR return true case OpXor64: v.Op = OpARM64XOR return true case OpXor8: v.Op = OpARM64XOR return true case OpZero: return rewriteValueARM64_OpZero(v) case OpZeroExt16to32: v.Op = OpARM64MOVHUreg return true case OpZeroExt16to64: v.Op = OpARM64MOVHUreg return true case OpZeroExt32to64: v.Op = OpARM64MOVWUreg return true case OpZeroExt8to16: v.Op = OpARM64MOVBUreg return true case OpZeroExt8to32: v.Op = OpARM64MOVBUreg return true case OpZeroExt8to64: v.Op = OpARM64MOVBUreg return true } return false } func rewriteValueARM64_OpARM64ADCSflags(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADCSflags x y (Select1 (ADDSconstflags [-1] (ADCzerocarry c)))) // result: (ADCSflags x y c) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64ADDSconstflags || auxIntToInt64(v_2_0.AuxInt) != -1 { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64ADCzerocarry || v_2_0_0.Type != typ.UInt64 { break } c := v_2_0_0.Args[0] v.reset(OpARM64ADCSflags) v.AddArg3(x, y, c) return true } // match: (ADCSflags x y (Select1 (ADDSconstflags [-1] (MOVDconst [0])))) // result: (ADDSflags x y) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64ADDSconstflags || auxIntToInt64(v_2_0.AuxInt) != -1 { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64MOVDconst || auxIntToInt64(v_2_0_0.AuxInt) != 0 { break } v.reset(OpARM64ADDSflags) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64ADD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADD x (MOVDconst [c])) // cond: !t.IsPtr() // result: (ADDconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(!t.IsPtr()) { continue } v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADD a l:(MUL x y)) // cond: l.Uses==1 && clobber(l) // result: (MADD a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MUL { continue } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MADD) v.AddArg3(a, x, y) return true } break } // match: (ADD a l:(MNEG x y)) // cond: l.Uses==1 && clobber(l) // result: (MSUB a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MNEG { continue } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MSUB) v.AddArg3(a, x, y) return true } break } // match: (ADD a l:(MULW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MADDW a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MULW { continue } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MADDW) v.AddArg3(a, x, y) return true } break } // match: (ADD a l:(MNEGW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MSUBW a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MNEGW { continue } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MSUBW) v.AddArg3(a, x, y) return true } break } // match: (ADD x (NEG y)) // result: (SUB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64NEG { continue } y := v_1.Args[0] v.reset(OpARM64SUB) v.AddArg2(x, y) return true } break } // match: (ADD x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ADDshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (ADD x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ADDshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ADDshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (ADD x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ADDshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ADDshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64ADDSflags(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSflags x (MOVDconst [c])) // result: (ADDSconstflags [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ADDSconstflags) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } return false } func rewriteValueARM64_OpARM64ADDconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDconst [off1] (MOVDaddr [off2] {sym} ptr)) // cond: is32Bit(off1+int64(off2)) // result: (MOVDaddr [int32(off1)+off2] {sym} ptr) for { off1 := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) ptr := v_0.Args[0] if !(is32Bit(off1 + int64(off2))) { break } v.reset(OpARM64MOVDaddr) v.AuxInt = int32ToAuxInt(int32(off1) + off2) v.Aux = symToAux(sym) v.AddArg(ptr) return true } // match: (ADDconst [c] y) // cond: c < 0 // result: (SUBconst [-c] y) for { c := auxIntToInt64(v.AuxInt) y := v_0 if !(c < 0) { break } v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(-c) v.AddArg(y) return true } // match: (ADDconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ADDconst [c] (MOVDconst [d])) // result: (MOVDconst [c+d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c + d) return true } // match: (ADDconst [c] (ADDconst [d] x)) // result: (ADDconst [c+d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ADDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDconst [c] (SUBconst [d] x)) // result: (ADDconst [c-d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SUBconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c - d) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ADDshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDshiftLL (MOVDconst [c]) x [d]) // result: (ADDconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftLL x (MOVDconst [c]) [d]) // result: (ADDconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) // result: (REV16W x) for { if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ADDshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff // result: (REV16W x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ADDshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) // result: (REV16 x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { break } v.reset(OpARM64REV16) v.AddArg(x) return true } // match: (ADDshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) // result: (REV16 (ANDconst [0xffffffff] x)) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16) v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) v0.AuxInt = int64ToAuxInt(0xffffffff) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftLL [c] (SRLconst x [64-c]) x2) // result: (EXTRconst [64-c] x2 x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { break } x := v_0.Args[0] x2 := v_1 v.reset(OpARM64EXTRconst) v.AuxInt = int64ToAuxInt(64 - c) v.AddArg2(x2, x) return true } // match: (ADDshiftLL [c] (UBFX [bfc] x) x2) // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) // result: (EXTRWconst [32-c] x2 x) for { t := v.Type c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] x2 := v_1 if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { break } v.reset(OpARM64EXTRWconst) v.AuxInt = int64ToAuxInt(32 - c) v.AddArg2(x2, x) return true } return false } func rewriteValueARM64_OpARM64ADDshiftRA(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ADDshiftRA (MOVDconst [c]) x [d]) // result: (ADDconst [c] (SRAconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftRA x (MOVDconst [c]) [d]) // result: (ADDconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ADDshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ADDshiftRL (MOVDconst [c]) x [d]) // result: (ADDconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftRL x (MOVDconst [c]) [d]) // result: (ADDconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64AND(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (AND x (MOVDconst [c])) // result: (ANDconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (AND x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (AND x (MVN y)) // result: (BIC x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MVN { continue } y := v_1.Args[0] v.reset(OpARM64BIC) v.AddArg2(x, y) return true } break } // match: (AND x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (AND x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (AND x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (AND x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64ANDconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDconst [0] _) // result: (MOVDconst [0]) for { if auxIntToInt64(v.AuxInt) != 0 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (ANDconst [-1] x) // result: x for { if auxIntToInt64(v.AuxInt) != -1 { break } x := v_0 v.copyOf(x) return true } // match: (ANDconst [c] (MOVDconst [d])) // result: (MOVDconst [c&d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c & d) return true } // match: (ANDconst [c] (ANDconst [d] x)) // result: (ANDconst [c&d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDconst [c] (MOVWUreg x)) // result: (ANDconst [c&(1<<32-1)] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg { break } x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<32 - 1)) v.AddArg(x) return true } // match: (ANDconst [c] (MOVHUreg x)) // result: (ANDconst [c&(1<<16-1)] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg { break } x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<16 - 1)) v.AddArg(x) return true } // match: (ANDconst [c] (MOVBUreg x)) // result: (ANDconst [c&(1<<8-1)] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg { break } x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<8 - 1)) v.AddArg(x) return true } // match: (ANDconst [ac] (SLLconst [sc] x)) // cond: isARM64BFMask(sc, ac, sc) // result: (UBFIZ [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x) for { ac := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(sc, ac, sc)) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc, arm64BFWidth(ac, sc))) v.AddArg(x) return true } // match: (ANDconst [ac] (SRLconst [sc] x)) // cond: isARM64BFMask(sc, ac, 0) // result: (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, 0))] x) for { ac := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(sc, ac, 0)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc, arm64BFWidth(ac, 0))) v.AddArg(x) return true } // match: (ANDconst [c] (UBFX [bfc] x)) // cond: isARM64BFMask(0, c, 0) // result: (UBFX [armBFAuxInt(bfc.getARM64BFlsb(), min(bfc.getARM64BFwidth(), arm64BFWidth(c, 0)))] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(0, c, 0)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb(), min(bfc.getARM64BFwidth(), arm64BFWidth(c, 0)))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ANDshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ANDshiftLL (MOVDconst [c]) x [d]) // result: (ANDconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftLL x (MOVDconst [c]) [d]) // result: (ANDconst x [int64(uint64(c)< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftRA x (MOVDconst [c]) [d]) // result: (ANDconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (ANDshiftRA y:(SRAconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRAconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64ANDshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ANDshiftRL (MOVDconst [c]) x [d]) // result: (ANDconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftRL x (MOVDconst [c]) [d]) // result: (ANDconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (ANDshiftRL y:(SRLconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRLconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64ANDshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ANDshiftRO (MOVDconst [c]) x [d]) // result: (ANDconst [c] (RORconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftRO x (MOVDconst [c]) [d]) // result: (ANDconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } // match: (ANDshiftRO y:(RORconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64RORconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64BIC(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BIC x (MOVDconst [c])) // result: (ANDconst [^c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^c) v.AddArg(x) return true } // match: (BIC x x) // result: (MOVDconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (BIC x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (BIC x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (BIC x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (BIC x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftRO x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64BICshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BICshiftLL x (MOVDconst [c]) [d]) // result: (ANDconst x [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) v.AddArg(x) return true } // match: (BICshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64BICshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BICshiftRL x (MOVDconst [c]) [d]) // result: (ANDconst x [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (BICshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64BICshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BICshiftRO x (MOVDconst [c]) [d]) // result: (ANDconst x [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) v.AddArg(x) return true } // match: (BICshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64CMN(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMN x (MOVDconst [c])) // result: (CMNconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (CMN x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMNshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64CMNshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (CMN x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMNshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64CMNshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (CMN x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (CMNshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64CMNshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64CMNW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMNW x (MOVDconst [c])) // result: (CMNWconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNWconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueARM64_OpARM64CMNWconst(v *Value) bool { v_0 := v.Args[0] // match: (CMNWconst [c] y) // cond: c < 0 && c != -1<<31 // result: (CMPWconst [-c] y) for { c := auxIntToInt32(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<31) { break } v.reset(OpARM64CMPWconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(y) return true } // match: (CMNWconst (MOVDconst [x]) [y]) // result: (FlagConstant [addFlags32(int32(x),y)]) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(addFlags32(int32(x), y)) return true } return false } func rewriteValueARM64_OpARM64CMNconst(v *Value) bool { v_0 := v.Args[0] // match: (CMNconst [c] y) // cond: c < 0 && c != -1<<63 // result: (CMPconst [-c] y) for { c := auxIntToInt64(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<63) { break } v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(-c) v.AddArg(y) return true } // match: (CMNconst (MOVDconst [x]) [y]) // result: (FlagConstant [addFlags64(x,y)]) for { y := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(addFlags64(x, y)) return true } return false } func rewriteValueARM64_OpARM64CMNshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMNshiftLL (MOVDconst [c]) x [d]) // result: (CMNconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMNshiftLL x (MOVDconst [c]) [d]) // result: (CMNconst x [int64(uint64(c)< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMNshiftRA x (MOVDconst [c]) [d]) // result: (CMNconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CMNshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMNshiftRL (MOVDconst [c]) x [d]) // result: (CMNconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMNshiftRL x (MOVDconst [c]) [d]) // result: (CMNconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CMP(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMP x (MOVDconst [c])) // result: (CMPconst [c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (CMP (MOVDconst [c]) x) // result: (InvertFlags (CMPconst [c] x)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMP x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMP y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMP x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMPshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64CMPshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (CMP x0:(SLLconst [c] y) x1) // cond: clobberIfDead(x0) // result: (InvertFlags (CMPshiftLL x1 y [c])) for { x0 := v_0 if x0.Op != OpARM64SLLconst { break } c := auxIntToInt64(x0.AuxInt) y := x0.Args[0] x1 := v_1 if !(clobberIfDead(x0)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPshiftLL, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg2(x1, y) v.AddArg(v0) return true } // match: (CMP x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMPshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64CMPshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (CMP x0:(SRLconst [c] y) x1) // cond: clobberIfDead(x0) // result: (InvertFlags (CMPshiftRL x1 y [c])) for { x0 := v_0 if x0.Op != OpARM64SRLconst { break } c := auxIntToInt64(x0.AuxInt) y := x0.Args[0] x1 := v_1 if !(clobberIfDead(x0)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRL, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg2(x1, y) v.AddArg(v0) return true } // match: (CMP x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (CMPshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64CMPshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (CMP x0:(SRAconst [c] y) x1) // cond: clobberIfDead(x0) // result: (InvertFlags (CMPshiftRA x1 y [c])) for { x0 := v_0 if x0.Op != OpARM64SRAconst { break } c := auxIntToInt64(x0.AuxInt) y := x0.Args[0] x1 := v_1 if !(clobberIfDead(x0)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRA, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg2(x1, y) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64CMPW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPW x (MOVDconst [c])) // result: (CMPWconst [int32(c)] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPWconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } // match: (CMPW (MOVDconst [c]) x) // result: (InvertFlags (CMPWconst [int32(c)] x)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPW x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPW y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64CMPWconst(v *Value) bool { v_0 := v.Args[0] // match: (CMPWconst [c] y) // cond: c < 0 && c != -1<<31 // result: (CMNWconst [-c] y) for { c := auxIntToInt32(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<31) { break } v.reset(OpARM64CMNWconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(y) return true } // match: (CMPWconst (MOVDconst [x]) [y]) // result: (FlagConstant [subFlags32(int32(x),y)]) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags32(int32(x), y)) return true } // match: (CMPWconst (MOVBUreg _) [c]) // cond: 0xff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVBUreg || !(0xff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPWconst (MOVHUreg _) [c]) // cond: 0xffff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVHUreg || !(0xffff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } return false } func rewriteValueARM64_OpARM64CMPconst(v *Value) bool { v_0 := v.Args[0] // match: (CMPconst [c] y) // cond: c < 0 && c != -1<<63 // result: (CMNconst [-c] y) for { c := auxIntToInt64(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<63) { break } v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(-c) v.AddArg(y) return true } // match: (CMPconst (MOVDconst [x]) [y]) // result: (FlagConstant [subFlags64(x,y)]) for { y := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(x, y)) return true } // match: (CMPconst (MOVBUreg _) [c]) // cond: 0xff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg || !(0xff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (MOVHUreg _) [c]) // cond: 0xffff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg || !(0xffff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (MOVWUreg _) [c]) // cond: 0xffffffff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg || !(0xffffffff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (ANDconst _ [m]) [n]) // cond: 0 <= m && m < n // result: (FlagConstant [subFlags64(0,1)]) for { n := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } m := auxIntToInt64(v_0.AuxInt) if !(0 <= m && m < n) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (SRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 63 && (1< x [d]))) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v1 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v1.AuxInt = int64ToAuxInt(d) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (CMPshiftLL x (MOVDconst [c]) [d]) // result: (CMPconst x [int64(uint64(c)< x [d]))) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v1 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v1.AuxInt = int64ToAuxInt(d) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (CMPshiftRA x (MOVDconst [c]) [d]) // result: (CMPconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CMPshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPshiftRL (MOVDconst [c]) x [d]) // result: (InvertFlags (CMPconst [c] (SRLconst x [d]))) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v1 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v1.AuxInt = int64ToAuxInt(d) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (CMPshiftRL x (MOVDconst [c]) [d]) // result: (CMPconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CSEL(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSEL [cc] (MOVDconst [-1]) (MOVDconst [0]) flag) // result: (CSETM [cc] flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != -1 || v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } flag := v_2 v.reset(OpARM64CSETM) v.AuxInt = opToAuxInt(cc) v.AddArg(flag) return true } // match: (CSEL [cc] (MOVDconst [0]) (MOVDconst [-1]) flag) // result: (CSETM [arm64Negate(cc)] flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 0 || v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { break } flag := v_2 v.reset(OpARM64CSETM) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg(flag) return true } // match: (CSEL [cc] x (MOVDconst [0]) flag) // result: (CSEL0 [cc] x flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } flag := v_2 v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(cc) v.AddArg2(x, flag) return true } // match: (CSEL [cc] (MOVDconst [0]) y flag) // result: (CSEL0 [arm64Negate(cc)] y flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 0 { break } y := v_1 flag := v_2 v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg2(y, flag) return true } // match: (CSEL [cc] x (ADDconst [1] a) flag) // result: (CSINC [cc] x a flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } a := v_1.Args[0] flag := v_2 v.reset(OpARM64CSINC) v.AuxInt = opToAuxInt(cc) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] (ADDconst [1] a) x flag) // result: (CSINC [arm64Negate(cc)] x a flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64ADDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } a := v_0.Args[0] x := v_1 flag := v_2 v.reset(OpARM64CSINC) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] x (MVN a) flag) // result: (CSINV [cc] x a flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64MVN { break } a := v_1.Args[0] flag := v_2 v.reset(OpARM64CSINV) v.AuxInt = opToAuxInt(cc) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] (MVN a) x flag) // result: (CSINV [arm64Negate(cc)] x a flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MVN { break } a := v_0.Args[0] x := v_1 flag := v_2 v.reset(OpARM64CSINV) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] x (NEG a) flag) // result: (CSNEG [cc] x a flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64NEG { break } a := v_1.Args[0] flag := v_2 v.reset(OpARM64CSNEG) v.AuxInt = opToAuxInt(cc) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] (NEG a) x flag) // result: (CSNEG [arm64Negate(cc)] x a flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64NEG { break } a := v_0.Args[0] x := v_1 flag := v_2 v.reset(OpARM64CSNEG) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] x y (InvertFlags cmp)) // result: (CSEL [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSEL [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSEL [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: y for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.copyOf(y) return true } // match: (CSEL [cc] x y (CMPWconst [0] boolval)) // cond: cc == OpARM64NotEqual && flagArg(boolval) != nil // result: (CSEL [boolval.Op] x y flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64CMPWconst || auxIntToInt32(v_2.AuxInt) != 0 { break } boolval := v_2.Args[0] if !(cc == OpARM64NotEqual && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(boolval.Op) v.AddArg3(x, y, flagArg(boolval)) return true } // match: (CSEL [cc] x y (CMPWconst [0] boolval)) // cond: cc == OpARM64Equal && flagArg(boolval) != nil // result: (CSEL [arm64Negate(boolval.Op)] x y flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64CMPWconst || auxIntToInt32(v_2.AuxInt) != 0 { break } boolval := v_2.Args[0] if !(cc == OpARM64Equal && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(arm64Negate(boolval.Op)) v.AddArg3(x, y, flagArg(boolval)) return true } return false } func rewriteValueARM64_OpARM64CSEL0(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSEL0 [cc] x (InvertFlags cmp)) // result: (CSEL0 [arm64Invert(cc)] x cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64InvertFlags { break } cmp := v_1.Args[0] v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg2(x, cmp) return true } // match: (CSEL0 [cc] x flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_1 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSEL0 [cc] _ flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (MOVDconst [0]) for { cc := auxIntToOp(v.AuxInt) flag := v_1 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (CSEL0 [cc] x (CMPWconst [0] boolval)) // cond: cc == OpARM64NotEqual && flagArg(boolval) != nil // result: (CSEL0 [boolval.Op] x flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64CMPWconst || auxIntToInt32(v_1.AuxInt) != 0 { break } boolval := v_1.Args[0] if !(cc == OpARM64NotEqual && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(boolval.Op) v.AddArg2(x, flagArg(boolval)) return true } // match: (CSEL0 [cc] x (CMPWconst [0] boolval)) // cond: cc == OpARM64Equal && flagArg(boolval) != nil // result: (CSEL0 [arm64Negate(boolval.Op)] x flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64CMPWconst || auxIntToInt32(v_1.AuxInt) != 0 { break } boolval := v_1.Args[0] if !(cc == OpARM64Equal && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(arm64Negate(boolval.Op)) v.AddArg2(x, flagArg(boolval)) return true } return false } func rewriteValueARM64_OpARM64CSETM(v *Value) bool { v_0 := v.Args[0] // match: (CSETM [cc] (InvertFlags cmp)) // result: (CSETM [arm64Invert(cc)] cmp) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64InvertFlags { break } cmp := v_0.Args[0] v.reset(OpARM64CSETM) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg(cmp) return true } // match: (CSETM [cc] flag) // cond: ccARM64Eval(cc, flag) > 0 // result: (MOVDconst [-1]) for { cc := auxIntToOp(v.AuxInt) flag := v_0 if !(ccARM64Eval(cc, flag) > 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (CSETM [cc] flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (MOVDconst [0]) for { cc := auxIntToOp(v.AuxInt) flag := v_0 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64CSINC(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSINC [cc] x y (InvertFlags cmp)) // result: (CSINC [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSINC) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSINC [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSINC [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (ADDconst [1] y) for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(1) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64CSINV(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSINV [cc] x y (InvertFlags cmp)) // result: (CSINV [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSINV) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSINV [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSINV [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (Not y) for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpNot) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64CSNEG(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSNEG [cc] x y (InvertFlags cmp)) // result: (CSNEG [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSNEG) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSNEG [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSNEG [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (NEG y) for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64NEG) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64DIV(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIV (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [c/d]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c / d) return true } return false } func rewriteValueARM64_OpARM64DIVW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(int32(c)/int32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) / int32(d))) return true } return false } func rewriteValueARM64_OpARM64EON(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EON x (MOVDconst [c])) // result: (XORconst [^c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^c) v.AddArg(x) return true } // match: (EON x x) // result: (MOVDconst [-1]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (EON x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (EON x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (EON x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (EON x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftRO x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64EONshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EONshiftLL x (MOVDconst [c]) [d]) // result: (XORconst x [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) v.AddArg(x) return true } // match: (EONshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64EONshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EONshiftRL x (MOVDconst [c]) [d]) // result: (XORconst x [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (EONshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64EONshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EONshiftRO x (MOVDconst [c]) [d]) // result: (XORconst x [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) v.AddArg(x) return true } // match: (EONshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64Equal(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Equal (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (Equal (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (Equal (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMP x z:(NEG y))) // cond: z.Uses == 1 // result: (Equal (CMN x y)) for { if v_0.Op != OpARM64CMP { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPW x z:(NEG y))) // cond: z.Uses == 1 // result: (Equal (CMNW x y)) for { if v_0.Op != OpARM64CMPW { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (Equal (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (Equal (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (Equal (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (Equal (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (Equal (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (Equal (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.eq())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.eq())) return true } // match: (Equal (InvertFlags x)) // result: (Equal x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64Equal) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64FADDD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FADDD a (FMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDD a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FMULD { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMADDD) v.AddArg3(a, x, y) return true } break } // match: (FADDD a (FNMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBD a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FNMULD { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMSUBD) v.AddArg3(a, x, y) return true } break } return false } func rewriteValueARM64_OpARM64FADDS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FADDS a (FMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDS a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FMULS { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMADDS) v.AddArg3(a, x, y) return true } break } // match: (FADDS a (FNMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBS a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FNMULS { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMSUBS) v.AddArg3(a, x, y) return true } break } return false } func rewriteValueARM64_OpARM64FCMPD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (FCMPD x (FMOVDconst [0])) // result: (FCMPD0 x) for { x := v_0 if v_1.Op != OpARM64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != 0 { break } v.reset(OpARM64FCMPD0) v.AddArg(x) return true } // match: (FCMPD (FMOVDconst [0]) x) // result: (InvertFlags (FCMPD0 x)) for { if v_0.Op != OpARM64FMOVDconst || auxIntToFloat64(v_0.AuxInt) != 0 { break } x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64FCMPD0, types.TypeFlags) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64FCMPS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (FCMPS x (FMOVSconst [0])) // result: (FCMPS0 x) for { x := v_0 if v_1.Op != OpARM64FMOVSconst || auxIntToFloat64(v_1.AuxInt) != 0 { break } v.reset(OpARM64FCMPS0) v.AddArg(x) return true } // match: (FCMPS (FMOVSconst [0]) x) // result: (InvertFlags (FCMPS0 x)) for { if v_0.Op != OpARM64FMOVSconst || auxIntToFloat64(v_0.AuxInt) != 0 { break } x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64FCMPS0, types.TypeFlags) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64FMOVDfpgp(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (FMOVDfpgp (Arg [off] {sym})) // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueARM64_OpARM64FMOVDgpfp(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (FMOVDgpfp (Arg [off] {sym})) // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueARM64_OpARM64FMOVDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _)) // result: (FMOVDgpfp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVDgpfp) v.AddArg(val) return true } // match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (FMOVDload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVDloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVDloadidx8 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (FMOVDload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVDloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (FMOVDload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVDloadidx ptr (SLLconst [3] idx) mem) // result: (FMOVDloadidx8 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVDloadidx (SLLconst [3] idx) ptr mem) // result: (FMOVDloadidx8 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64FMOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDloadidx8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDloadidx8 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<3) // result: (FMOVDload ptr [int32(c)<<3] mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 3)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVDstore [off] {sym} ptr (FMOVDgpfp val) mem) // result: (MOVDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVDgpfp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVDstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVDstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVDstoreidx8 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (FMOVDstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (FMOVDstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (FMOVDstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (FMOVDstoreidx ptr (SLLconst [3] idx) val mem) // result: (FMOVDstoreidx8 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64FMOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVDstoreidx (SLLconst [3] idx) ptr val mem) // result: (FMOVDstoreidx8 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64FMOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDstoreidx8(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDstoreidx8 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<3) // result: (FMOVDstore [int32(c)<<3] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 3)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVSload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) // result: (FMOVSgpfp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVSgpfp) v.AddArg(val) return true } // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (FMOVSload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVSloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVSload [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVSloadidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (FMOVSload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVSloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (FMOVSload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVSloadidx ptr (SLLconst [2] idx) mem) // result: (FMOVSloadidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVSloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVSloadidx (SLLconst [2] idx) ptr mem) // result: (FMOVSloadidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64FMOVSloadidx4) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSloadidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSloadidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (FMOVSload ptr [int32(c)<<2] mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVSstore [off] {sym} ptr (FMOVSgpfp val) mem) // result: (MOVWstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVSgpfp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVSstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVSstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVSstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVSstoreidx4 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (FMOVSstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (FMOVSstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (FMOVSstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (FMOVSstoreidx ptr (SLLconst [2] idx) val mem) // result: (FMOVSstoreidx4 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64FMOVSstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVSstoreidx (SLLconst [2] idx) ptr val mem) // result: (FMOVSstoreidx4 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64FMOVSstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSstoreidx4(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSstoreidx4 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<2) // result: (FMOVSstore [int32(c)<<2] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 2)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMULD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMULD (FNEGD x) y) // result: (FNMULD x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGD { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FNMULD) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FMULS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMULS (FNEGS x) y) // result: (FNMULS x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGS { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FNMULS) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FNEGD(v *Value) bool { v_0 := v.Args[0] // match: (FNEGD (FMULD x y)) // result: (FNMULD x y) for { if v_0.Op != OpARM64FMULD { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FNMULD) v.AddArg2(x, y) return true } // match: (FNEGD (FNMULD x y)) // result: (FMULD x y) for { if v_0.Op != OpARM64FNMULD { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FMULD) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64FNEGS(v *Value) bool { v_0 := v.Args[0] // match: (FNEGS (FMULS x y)) // result: (FNMULS x y) for { if v_0.Op != OpARM64FMULS { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FNMULS) v.AddArg2(x, y) return true } // match: (FNEGS (FNMULS x y)) // result: (FMULS x y) for { if v_0.Op != OpARM64FNMULS { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FMULS) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64FNMULD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FNMULD (FNEGD x) y) // result: (FMULD x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGD { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FMULD) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FNMULS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FNMULS (FNEGS x) y) // result: (FMULS x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGS { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FMULS) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FSUBD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FSUBD a (FMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBD a x y) for { a := v_0 if v_1.Op != OpARM64FMULD { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMSUBD) v.AddArg3(a, x, y) return true } // match: (FSUBD (FMULD x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMSUBD a x y) for { if v_0.Op != OpARM64FMULD { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMSUBD) v.AddArg3(a, x, y) return true } // match: (FSUBD a (FNMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDD a x y) for { a := v_0 if v_1.Op != OpARM64FNMULD { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMADDD) v.AddArg3(a, x, y) return true } // match: (FSUBD (FNMULD x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMADDD a x y) for { if v_0.Op != OpARM64FNMULD { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMADDD) v.AddArg3(a, x, y) return true } return false } func rewriteValueARM64_OpARM64FSUBS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FSUBS a (FMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBS a x y) for { a := v_0 if v_1.Op != OpARM64FMULS { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMSUBS) v.AddArg3(a, x, y) return true } // match: (FSUBS (FMULS x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMSUBS a x y) for { if v_0.Op != OpARM64FMULS { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMSUBS) v.AddArg3(a, x, y) return true } // match: (FSUBS a (FNMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDS a x y) for { a := v_0 if v_1.Op != OpARM64FNMULS { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMADDS) v.AddArg3(a, x, y) return true } // match: (FSUBS (FNMULS x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMADDS a x y) for { if v_0.Op != OpARM64FNMULS { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMADDS) v.AddArg3(a, x, y) return true } return false } func rewriteValueARM64_OpARM64GreaterEqual(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (GreaterEqual (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterEqual (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqual (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterEqual (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqual (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqualNoov (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqualNoov (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ge())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ge())) return true } // match: (GreaterEqual (InvertFlags x)) // result: (LessEqual x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessEqual) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterEqualF(v *Value) bool { v_0 := v.Args[0] // match: (GreaterEqualF (InvertFlags x)) // result: (LessEqualF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessEqualF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterEqualU(v *Value) bool { v_0 := v.Args[0] // match: (GreaterEqualU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.uge())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.uge())) return true } // match: (GreaterEqualU (InvertFlags x)) // result: (LessEqualU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessEqualU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterThan(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (GreaterThan (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterThan (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterThan (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterThan (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterThan (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterThan (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterThan (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterThan (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterThan (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.gt())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.gt())) return true } // match: (GreaterThan (InvertFlags x)) // result: (LessThan x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessThan) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterThanF(v *Value) bool { v_0 := v.Args[0] // match: (GreaterThanF (InvertFlags x)) // result: (LessThanF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessThanF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterThanU(v *Value) bool { v_0 := v.Args[0] // match: (GreaterThanU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ugt())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ugt())) return true } // match: (GreaterThanU (InvertFlags x)) // result: (LessThanU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessThanU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LDP(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (LDP [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (LDP [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64LDP) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (LDP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (LDP [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64LDP) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64LessEqual(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (LessEqual (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessEqual (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessEqual (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessEqual (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessEqual (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessEqual (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessEqual (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessEqual (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessEqual (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.le())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.le())) return true } // match: (LessEqual (InvertFlags x)) // result: (GreaterEqual x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterEqual) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessEqualF(v *Value) bool { v_0 := v.Args[0] // match: (LessEqualF (InvertFlags x)) // result: (GreaterEqualF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterEqualF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessEqualU(v *Value) bool { v_0 := v.Args[0] // match: (LessEqualU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ule())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ule())) return true } // match: (LessEqualU (InvertFlags x)) // result: (GreaterEqualU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterEqualU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessThan(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (LessThan (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessThan (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessThan (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessThan (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessThan (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (LessThanNoov (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (LessThanNoov (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.lt())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.lt())) return true } // match: (LessThan (InvertFlags x)) // result: (GreaterThan x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterThan) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessThanF(v *Value) bool { v_0 := v.Args[0] // match: (LessThanF (InvertFlags x)) // result: (GreaterThanF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterThanF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessThanU(v *Value) bool { v_0 := v.Args[0] // match: (LessThanU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ult())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ult())) return true } // match: (LessThanU (InvertFlags x)) // result: (GreaterThanU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterThanU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MADD(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MADD a x (MOVDconst [-1])) // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != -1 { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADD a _ (MOVDconst [0])) // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MADD a x (MOVDconst [1])) // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 1 { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADD a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADD a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [-1]) x) // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { break } x := v_2 v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADD a (MOVDconst [0]) _) // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MADD a (MOVDconst [1]) x) // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } x := v_2 v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADD a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADD a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD (MOVDconst [c]) x y) // result: (ADDconst [c] (MUL x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MADD a (MOVDconst [c]) (MOVDconst [d])) // result: (ADDconst [c*d] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c * d) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MADDW(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MADDW a x (MOVDconst [c])) // cond: int32(c)==-1 // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == -1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADDW a _ (MOVDconst [c])) // cond: int32(c)==0 // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MADDW a x (MOVDconst [c])) // cond: int32(c)==1 // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADDW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADDW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: int32(c)==-1 // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == -1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADDW a (MOVDconst [c]) _) // cond: int32(c)==0 // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: int32(c)==1 // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == 1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW (MOVDconst [c]) x y) // result: (ADDconst [c] (MULW x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MADDW a (MOVDconst [c]) (MOVDconst [d])) // result: (ADDconst [int64(int32(c)*int32(d))] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) * int32(d))) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MNEG(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MNEG x (MOVDconst [-1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { continue } v.copyOf(x) return true } break } // match: (MNEG _ (MOVDconst [0])) // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MNEG x (MOVDconst [1])) // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (NEG (SLLconst [log64(c)] x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c)) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c >= 3 // result: (NEG (ADDshiftLL x x [log64(c-1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c >= 7 // result: (NEG (ADDshiftLL (NEG x) x [log64(c+1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SLLconst [log64(c/3)] (SUBshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (NEG (SLLconst [log64(c/5)] (ADDshiftLL x x [2]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 5)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(2) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SLLconst [log64(c/7)] (SUBshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (NEG (SLLconst [log64(c/9)] (ADDshiftLL x x [3]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 9)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(3) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEG (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [-c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-c * d) return true } break } return false } func rewriteValueARM64_OpARM64MNEGW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MNEGW x (MOVDconst [c])) // cond: int32(c)==-1 // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == -1) { continue } v.copyOf(x) return true } break } // match: (MNEGW _ (MOVDconst [c])) // cond: int32(c)==0 // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: int32(c)==1 // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 1) { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (NEG (SLLconst [log64(c)] x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c)) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c) >= 3 // result: (NEG (ADDshiftLL x x [log64(c-1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c) >= 7 // result: (NEG (ADDshiftLL (NEG x) x [log64(c+1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SLLconst [log64(c/3)] (SUBshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (NEG (SLLconst [log64(c/5)] (ADDshiftLL x x [2]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 5)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(2) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SLLconst [log64(c/7)] (SUBshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (NEG (SLLconst [log64(c/9)] (ADDshiftLL x x [3]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 9)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(3) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEGW (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [-int64(int32(c)*int32(d))]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-int64(int32(c) * int32(d))) return true } break } return false } func rewriteValueARM64_OpARM64MOD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOD (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [c%d]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c % d) return true } return false } func rewriteValueARM64_OpARM64MODW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MODW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(int32(c)%int32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) % int32(d))) return true } return false } func rewriteValueARM64_OpARM64MOVBUload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBUload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBUload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVBUloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBUloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBUload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVBUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read8(sym, int64(off)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read8(sym, int64(off)))) return true } return false } func rewriteValueARM64_OpARM64MOVBUloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBUloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVBUload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBUloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVBUload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBUloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVBUreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVBUreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<8-1)] x) for { if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<8 - 1)) v.AddArg(x) return true } // match: (MOVBUreg (MOVDconst [c])) // result: (MOVDconst [int64(uint8(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint8(c))) return true } // match: (MOVBUreg x:(Equal _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64Equal { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(NotEqual _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64NotEqual { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessThan _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessThan { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessThanU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessThanU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessThanF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessThanF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessEqual _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessEqual { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessEqualU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessEqualU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessEqualF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessEqualF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterThan _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterThan { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterThanU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterThanU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterThanF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterThanF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterEqual _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterEqual { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterEqualU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterEqualU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterEqualF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterEqualF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg (SLLconst [lc] x)) // cond: lc >= 8 // result: (MOVDconst [0]) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) if !(lc >= 8) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVBUreg (SLLconst [lc] x)) // cond: lc < 8 // result: (UBFIZ [armBFAuxInt(lc, 8-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 8) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 8-lc)) v.AddArg(x) return true } // match: (MOVBUreg (SRLconst [rc] x)) // cond: rc < 8 // result: (UBFX [armBFAuxInt(rc, 8)] x) for { if v_0.Op != OpARM64SRLconst { break } rc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(rc < 8) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8)) v.AddArg(x) return true } // match: (MOVBUreg (UBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 8 // result: (UBFX [bfc] x) for { if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 8) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVBloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVBloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVBload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVBload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVBreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVBreg x:(MOVBload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBreg x:(MOVBloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBreg x:(MOVBreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBreg (MOVDconst [c])) // result: (MOVDconst [int64(int8(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int8(c))) return true } // match: (MOVBreg (ANDconst x [c])) // cond: uint64(c) & uint64(0xffffffffffffff80) == 0 // result: (ANDconst x [c]) for { t := v.Type if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(uint64(c)&uint64(0xffffffffffffff80) == 0) { break } v.reset(OpARM64ANDconst) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (MOVBreg (SLLconst [lc] x)) // cond: lc < 8 // result: (SBFIZ [armBFAuxInt(lc, 8-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 8) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 8-lc)) v.AddArg(x) return true } // match: (MOVBreg (SBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 8 // result: (SBFX [bfc] x) for { if v_0.Op != OpARM64SBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 8) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVBstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVBstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVBstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVBstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVBstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVBstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVBstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVBstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBstoreidx ptr idx (MOVBreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVBUreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVHreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVHUreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVWreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVWUreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVBstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVBstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBstorezeroidx) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVBstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVBstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVBstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr val _)) // result: (FMOVDfpgp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVDfpgp) v.AddArg(val) return true } // match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVDload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDloadidx8 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVDload [off] {sym} ptr (MOVDstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVDload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueARM64_OpARM64MOVDloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVDload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVDloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVDload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVDloadidx ptr (SLLconst [3] idx) mem) // result: (MOVDloadidx8 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDloadidx (SLLconst [3] idx) ptr mem) // result: (MOVDloadidx8 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDloadidx ptr idx (MOVDstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVDloadidx8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDloadidx8 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<3) // result: (MOVDload [int32(c)<<3] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 3)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg2(ptr, mem) return true } // match: (MOVDloadidx8 ptr idx (MOVDstorezeroidx8 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDstorezeroidx8 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVDnop(v *Value) bool { v_0 := v.Args[0] // match: (MOVDnop (MOVDconst [c])) // result: (MOVDconst [c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValueARM64_OpARM64MOVDreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVDreg x) // cond: x.Uses == 1 // result: (MOVDnop x) for { x := v_0 if !(x.Uses == 1) { break } v.reset(OpARM64MOVDnop) v.AddArg(x) return true } // match: (MOVDreg (MOVDconst [c])) // result: (MOVDconst [c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValueARM64_OpARM64MOVDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVDstore [off] {sym} ptr (FMOVDfpgp val) mem) // result: (FMOVDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVDfpgp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVDstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVDstoreidx8 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVDstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVDstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVDstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVDstoreidx ptr (SLLconst [3] idx) val mem) // result: (MOVDstoreidx8 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64MOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstoreidx (SLLconst [3] idx) ptr val mem) // result: (MOVDstoreidx8 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVDstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVDstorezeroidx) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstoreidx8(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstoreidx8 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<3) // result: (MOVDstore [int32(c)<<3] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 3)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstoreidx8 ptr idx (MOVDconst [0]) mem) // result: (MOVDstorezeroidx8 ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVDstorezero {s} [i] ptr x:(MOVDstorezero {s} [i+8] ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstorezero {s} [i] ptr mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 x := v_1 if x.Op != OpARM64MOVDstorezero || auxIntToInt32(x.AuxInt) != i+8 || auxToSym(x.Aux) != s { break } mem := x.Args[1] if ptr != x.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezero {s} [i] ptr x:(MOVDstorezero {s} [i-8] ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstorezero {s} [i-8] ptr mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 x := v_1 if x.Op != OpARM64MOVDstorezero || auxIntToInt32(x.AuxInt) != i-8 || auxToSym(x.Aux) != s { break } mem := x.Args[1] if ptr != x.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(i - 8) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDstorezero [off] {sym} (ADDshiftLL [3] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDstorezeroidx8 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVDstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVDstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVDstorezeroidx ptr (SLLconst [3] idx) mem) // result: (MOVDstorezeroidx8 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDstorezeroidx (SLLconst [3] idx) ptr mem) // result: (MOVDstorezeroidx8 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstorezeroidx8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstorezeroidx8 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<3) // result: (MOVDstorezero [int32(c<<3)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 3)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(c << 3)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHUload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHUload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHUload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHUloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHUloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUload [off] {sym} (ADDshiftLL [1] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHUloadidx2 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVHUload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVHUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueARM64_OpARM64MOVHUloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHUloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVHUload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHUloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVHUload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHUloadidx ptr (SLLconst [1] idx) mem) // result: (MOVHUloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUloadidx ptr (ADD idx idx) mem) // result: (MOVHUloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } mem := v_2 v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUloadidx (ADD idx idx) ptr mem) // result: (MOVHUloadidx2 ptr idx mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 mem := v_2 v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHUloadidx2(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHUloadidx2 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<1) // result: (MOVHUload [int32(c)<<1] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(int32(c) << 1) v.AddArg2(ptr, mem) return true } // match: (MOVHUloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx2 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHUreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVHUreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<16-1)] x) for { if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<16 - 1)) v.AddArg(x) return true } // match: (MOVHUreg (MOVDconst [c])) // result: (MOVDconst [int64(uint16(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint16(c))) return true } // match: (MOVHUreg (SLLconst [lc] x)) // cond: lc >= 16 // result: (MOVDconst [0]) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) if !(lc >= 16) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVHUreg (SLLconst [lc] x)) // cond: lc < 16 // result: (UBFIZ [armBFAuxInt(lc, 16-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 16) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 16-lc)) v.AddArg(x) return true } // match: (MOVHUreg (SRLconst [rc] x)) // cond: rc < 16 // result: (UBFX [armBFAuxInt(rc, 16)] x) for { if v_0.Op != OpARM64SRLconst { break } rc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(rc < 16) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 16)) v.AddArg(x) return true } // match: (MOVHUreg (UBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 16 // result: (UBFX [bfc] x) for { if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 16) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVHload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHload [off] {sym} (ADDshiftLL [1] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHloadidx2 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVHload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVHload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVHload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHloadidx ptr (SLLconst [1] idx) mem) // result: (MOVHloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHloadidx ptr (ADD idx idx) mem) // result: (MOVHloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } mem := v_2 v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHloadidx (ADD idx idx) ptr mem) // result: (MOVHloadidx2 ptr idx mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 mem := v_2 v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHloadidx2(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHloadidx2 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<1) // result: (MOVHload [int32(c)<<1] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(int32(c) << 1) v.AddArg2(ptr, mem) return true } // match: (MOVHloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx2 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVHreg x:(MOVBload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg (MOVDconst [c])) // result: (MOVDconst [int64(int16(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int16(c))) return true } // match: (MOVHreg (ANDconst x [c])) // cond: uint64(c) & uint64(0xffffffffffff8000) == 0 // result: (ANDconst x [c]) for { t := v.Type if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(uint64(c)&uint64(0xffffffffffff8000) == 0) { break } v.reset(OpARM64ANDconst) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (MOVHreg (SLLconst [lc] x)) // cond: lc < 16 // result: (SBFIZ [armBFAuxInt(lc, 16-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 16) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 16-lc)) v.AddArg(x) return true } // match: (MOVHreg (SBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 16 // result: (SBFX [bfc] x) for { if v_0.Op != OpARM64SBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 16) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVHstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVHstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstore [off] {sym} (ADDshiftLL [1] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVHstoreidx2 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVHstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVHstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVHstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVHstoreidx ptr (SLLconst [1] idx) val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx ptr (ADD idx idx) val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx (SLLconst [1] idx) ptr val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx (ADD idx idx) ptr val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVHstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVHstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstoreidx ptr idx (MOVHreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr idx (MOVHUreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr idx (MOVWreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr idx (MOVWUreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstoreidx2(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstoreidx2 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<1) // result: (MOVHstore [int32(c)<<1] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(int32(c) << 1) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVDconst [0]) mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVHreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVHUreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVWreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVWUreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVHstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezero [off] {sym} (ADDshiftLL [1] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHstorezeroidx2 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVHstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVHstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVHstorezeroidx ptr (SLLconst [1] idx) mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx ptr (ADD idx idx) mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx (SLLconst [1] idx) ptr mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx (ADD idx idx) ptr mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstorezeroidx2(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstorezeroidx2 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<1) // result: (MOVHstorezero [int32(c<<1)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(c << 1)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVQstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVQstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWUload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWUload [off] {sym} ptr (FMOVSstore [off] {sym} ptr val _)) // result: (FMOVSfpgp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVSfpgp) v.AddArg(val) return true } // match: (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWUload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWUload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWUloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWUloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUload [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWUloadidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWUloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWUload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVWUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueARM64_OpARM64MOVWUloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWUloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVWUload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWUloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVWUload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWUloadidx ptr (SLLconst [2] idx) mem) // result: (MOVWUloadidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWUloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUloadidx (SLLconst [2] idx) ptr mem) // result: (MOVWUloadidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVWUloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWUloadidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWUloadidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (MOVWUload [int32(c)<<2] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg2(ptr, mem) return true } // match: (MOVWUloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx4 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWUreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVWUreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUloadidx4 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUloadidx4 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<32-1)] x) for { if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<32 - 1)) v.AddArg(x) return true } // match: (MOVWUreg (MOVDconst [c])) // result: (MOVDconst [int64(uint32(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint32(c))) return true } // match: (MOVWUreg x) // cond: zeroUpper32Bits(x, 3) // result: x for { x := v_0 if !(zeroUpper32Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVWUreg (SLLconst [lc] x)) // cond: lc >= 32 // result: (MOVDconst [0]) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) if !(lc >= 32) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVWUreg (SLLconst [lc] x)) // cond: lc < 32 // result: (UBFIZ [armBFAuxInt(lc, 32-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 32) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 32-lc)) v.AddArg(x) return true } // match: (MOVWUreg (SRLconst [rc] x)) // cond: rc < 32 // result: (UBFX [armBFAuxInt(rc, 32)] x) for { if v_0.Op != OpARM64SRLconst { break } rc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(rc < 32) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 32)) v.AddArg(x) return true } // match: (MOVWUreg (UBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 32 // result: (UBFX [bfc] x) for { if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 32) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWload [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWloadidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVWload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVWload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWloadidx ptr (SLLconst [2] idx) mem) // result: (MOVWloadidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWloadidx (SLLconst [2] idx) ptr mem) // result: (MOVWloadidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVWloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWloadidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWloadidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (MOVWload [int32(c)<<2] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg2(ptr, mem) return true } // match: (MOVWloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx4 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVWreg x:(MOVBload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHUloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWloadidx4 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWloadidx4 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg (MOVDconst [c])) // result: (MOVDconst [int64(int32(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c))) return true } // match: (MOVWreg (ANDconst x [c])) // cond: uint64(c) & uint64(0xffffffff80000000) == 0 // result: (ANDconst x [c]) for { t := v.Type if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(uint64(c)&uint64(0xffffffff80000000) == 0) { break } v.reset(OpARM64ANDconst) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (MOVWreg (SLLconst [lc] x)) // cond: lc < 32 // result: (SBFIZ [armBFAuxInt(lc, 32-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 32) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 32-lc)) v.AddArg(x) return true } // match: (MOVWreg (SBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 32 // result: (SBFX [bfc] x) for { if v_0.Op != OpARM64SBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 32) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWstore [off] {sym} ptr (FMOVSfpgp val) mem) // result: (FMOVSstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVSfpgp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVWstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVWstoreidx4 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVWstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVWstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVWstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVWstoreidx ptr (SLLconst [2] idx) val mem) // result: (MOVWstoreidx4 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstoreidx (SLLconst [2] idx) ptr val mem) // result: (MOVWstoreidx4 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVWstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVWstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstoreidx ptr idx (MOVWreg x) mem) // result: (MOVWstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVWstoreidx ptr idx (MOVWUreg x) mem) // result: (MOVWstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstoreidx4(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreidx4 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<2) // result: (MOVWstore [int32(c)<<2] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstoreidx4 ptr idx (MOVDconst [0]) mem) // result: (MOVWstorezeroidx4 ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstoreidx4 ptr idx (MOVWreg x) mem) // result: (MOVWstoreidx4 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVWstoreidx4 ptr idx (MOVWUreg x) mem) // result: (MOVWstoreidx4 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstorezero [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWstorezeroidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVWstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVWstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVWstorezeroidx ptr (SLLconst [2] idx) mem) // result: (MOVWstorezeroidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstorezeroidx (SLLconst [2] idx) ptr mem) // result: (MOVWstorezeroidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstorezeroidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstorezeroidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (MOVWstorezero [int32(c<<2)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(c << 2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MSUB(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MSUB a x (MOVDconst [-1])) // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != -1 { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUB a _ (MOVDconst [0])) // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MSUB a x (MOVDconst [1])) // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 1 { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUB a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUB a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [-1]) x) // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { break } x := v_2 v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUB a (MOVDconst [0]) _) // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MSUB a (MOVDconst [1]) x) // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } x := v_2 v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB (MOVDconst [c]) x y) // result: (ADDconst [c] (MNEG x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MNEG, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MSUB a (MOVDconst [c]) (MOVDconst [d])) // result: (SUBconst [c*d] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(c * d) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MSUBW(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MSUBW a x (MOVDconst [c])) // cond: int32(c)==-1 // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == -1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUBW a _ (MOVDconst [c])) // cond: int32(c)==0 // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: int32(c)==1 // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: int32(c)==-1 // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == -1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUBW a (MOVDconst [c]) _) // cond: int32(c)==0 // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: int32(c)==1 // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == 1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW (MOVDconst [c]) x y) // result: (ADDconst [c] (MNEGW x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MNEGW, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MSUBW a (MOVDconst [c]) (MOVDconst [d])) // result: (SUBconst [int64(int32(c)*int32(d))] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(int64(int32(c) * int32(d))) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MUL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MUL (NEG x) y) // result: (MNEG x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64NEG { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64MNEG) v.AddArg2(x, y) return true } break } // match: (MUL x (MOVDconst [-1])) // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MUL _ (MOVDconst [0])) // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MUL x (MOVDconst [1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { continue } v.copyOf(x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SLLconst [log64(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c >= 3 // result: (ADDshiftLL x x [log64(c-1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c - 1)) v.AddArg2(x, x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c >= 7 // result: (ADDshiftLL (NEG x) x [log64(c+1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c + 1)) v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v0.AddArg(x) v.AddArg2(v0, x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SLLconst [log64(c/3)] (ADDshiftLL x x [1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (SLLconst [log64(c/5)] (ADDshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SLLconst [log64(c/7)] (ADDshiftLL (NEG x) x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (SLLconst [log64(c/9)] (ADDshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MUL (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c * d) return true } break } return false } func rewriteValueARM64_OpARM64MULW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MULW (NEG x) y) // result: (MNEGW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64NEG { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64MNEGW) v.AddArg2(x, y) return true } break } // match: (MULW x (MOVDconst [c])) // cond: int32(c)==-1 // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == -1) { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MULW _ (MOVDconst [c])) // cond: int32(c)==0 // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: int32(c)==1 // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 1) { continue } v.copyOf(x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SLLconst [log64(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c) >= 3 // result: (ADDshiftLL x x [log64(c-1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c - 1)) v.AddArg2(x, x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c) >= 7 // result: (ADDshiftLL (NEG x) x [log64(c+1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c + 1)) v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v0.AddArg(x) v.AddArg2(v0, x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SLLconst [log64(c/3)] (ADDshiftLL x x [1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (SLLconst [log64(c/5)] (ADDshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SLLconst [log64(c/7)] (ADDshiftLL (NEG x) x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (SLLconst [log64(c/9)] (ADDshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MULW (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [int64(int32(c)*int32(d))]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) * int32(d))) return true } break } return false } func rewriteValueARM64_OpARM64MVN(v *Value) bool { v_0 := v.Args[0] // match: (MVN (XOR x y)) // result: (EON x y) for { if v_0.Op != OpARM64XOR { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64EON) v.AddArg2(x, y) return true } // match: (MVN (MOVDconst [c])) // result: (MOVDconst [^c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^c) return true } // match: (MVN x:(SLLconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftLL [c] y) for { x := v_0 if x.Op != OpARM64SLLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (MVN x:(SRLconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftRL [c] y) for { x := v_0 if x.Op != OpARM64SRLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (MVN x:(SRAconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftRA [c] y) for { x := v_0 if x.Op != OpARM64SRAconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (MVN x:(RORconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftRO [c] y) for { x := v_0 if x.Op != OpARM64RORconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64MVNshiftLL(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftLL (MOVDconst [c]) [d]) // result: (MOVDconst [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64MVNshiftRL(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftRL (MOVDconst [c]) [d]) // result: (MOVDconst [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64MVNshiftRO(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftRO (MOVDconst [c]) [d]) // result: (MOVDconst [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) return true } return false } func rewriteValueARM64_OpARM64NEG(v *Value) bool { v_0 := v.Args[0] // match: (NEG (MUL x y)) // result: (MNEG x y) for { if v_0.Op != OpARM64MUL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MNEG) v.AddArg2(x, y) return true } // match: (NEG (MULW x y)) // result: (MNEGW x y) for { if v_0.Op != OpARM64MULW { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MNEGW) v.AddArg2(x, y) return true } // match: (NEG (NEG x)) // result: x for { if v_0.Op != OpARM64NEG { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEG (MOVDconst [c])) // result: (MOVDconst [-c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-c) return true } // match: (NEG x:(SLLconst [c] y)) // cond: clobberIfDead(x) // result: (NEGshiftLL [c] y) for { x := v_0 if x.Op != OpARM64SLLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64NEGshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (NEG x:(SRLconst [c] y)) // cond: clobberIfDead(x) // result: (NEGshiftRL [c] y) for { x := v_0 if x.Op != OpARM64SRLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64NEGshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (NEG x:(SRAconst [c] y)) // cond: clobberIfDead(x) // result: (NEGshiftRA [c] y) for { x := v_0 if x.Op != OpARM64SRAconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64NEGshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64NEGshiftLL(v *Value) bool { v_0 := v.Args[0] // match: (NEGshiftLL (MOVDconst [c]) [d]) // result: (MOVDconst [-int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-(c >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64NEGshiftRL(v *Value) bool { v_0 := v.Args[0] // match: (NEGshiftRL (MOVDconst [c]) [d]) // result: (MOVDconst [-int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-int64(uint64(c) >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64NotEqual(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (NotEqual (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (NotEqual (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (NotEqual (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMP x z:(NEG y))) // cond: z.Uses == 1 // result: (NotEqual (CMN x y)) for { if v_0.Op != OpARM64CMP { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPW x z:(NEG y))) // cond: z.Uses == 1 // result: (NotEqual (CMNW x y)) for { if v_0.Op != OpARM64CMPW { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (NotEqual (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (NotEqual (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ne())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ne())) return true } // match: (NotEqual (InvertFlags x)) // result: (NotEqual x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64NotEqual) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64OR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (OR x (MOVDconst [c])) // result: (ORconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (OR x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (OR x (MVN y)) // result: (ORN x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MVN { continue } y := v_1.Args[0] v.reset(OpARM64ORN) v.AddArg2(x, y) return true } break } // match: (OR x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR (UBFIZ [bfc] x) (ANDconst [ac] y)) // cond: ac == ^((1<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) v.AddArg(x) return true } // match: (ORNshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64ORNshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ORNshiftRL x (MOVDconst [c]) [d]) // result: (ORconst x [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (ORNshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64ORNshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ORNshiftRO x (MOVDconst [c]) [d]) // result: (ORconst x [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) v.AddArg(x) return true } // match: (ORNshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64ORconst(v *Value) bool { v_0 := v.Args[0] // match: (ORconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ORconst [-1] _) // result: (MOVDconst [-1]) for { if auxIntToInt64(v.AuxInt) != -1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (ORconst [c] (MOVDconst [d])) // result: (MOVDconst [c|d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c | d) return true } // match: (ORconst [c] (ORconst [d] x)) // result: (ORconst [c|d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ORconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORconst [c1] (ANDconst [c2] x)) // cond: c2|c1 == ^0 // result: (ORconst [c1] x) for { c1 := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(c2|c1 == ^0) { break } v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c1) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ORshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ORshiftLL (MOVDconst [c]) x [d]) // result: (ORconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftLL x (MOVDconst [c]) [d]) // result: (ORconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) // result: (REV16W x) for { if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ORshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff // result: (REV16W x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) // result: (REV16 x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { break } v.reset(OpARM64REV16) v.AddArg(x) return true } // match: (ORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) // result: (REV16 (ANDconst [0xffffffff] x)) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16) v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) v0.AuxInt = int64ToAuxInt(0xffffffff) v0.AddArg(x) v.AddArg(v0) return true } // match: ( ORshiftLL [c] (SRLconst x [64-c]) x2) // result: (EXTRconst [64-c] x2 x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { break } x := v_0.Args[0] x2 := v_1 v.reset(OpARM64EXTRconst) v.AuxInt = int64ToAuxInt(64 - c) v.AddArg2(x2, x) return true } // match: ( ORshiftLL [c] (UBFX [bfc] x) x2) // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) // result: (EXTRWconst [32-c] x2 x) for { t := v.Type c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] x2 := v_1 if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { break } v.reset(OpARM64EXTRWconst) v.AuxInt = int64ToAuxInt(32 - c) v.AddArg2(x2, x) return true } // match: (ORshiftLL [sc] (UBFX [bfc] x) (SRLconst [sc] y)) // cond: sc == bfc.getARM64BFwidth() // result: (BFXIL [bfc] y x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != sc { break } y := v_1.Args[0] if !(sc == bfc.getARM64BFwidth()) { break } v.reset(OpARM64BFXIL) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg2(y, x) return true } return false } func rewriteValueARM64_OpARM64ORshiftRA(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ORshiftRA (MOVDconst [c]) x [d]) // result: (ORconst [c] (SRAconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftRA x (MOVDconst [c]) [d]) // result: (ORconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (ORshiftRA y:(SRAconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRAconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64ORshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ORshiftRL (MOVDconst [c]) x [d]) // result: (ORconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftRL x (MOVDconst [c]) [d]) // result: (ORconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (ORshiftRL y:(SRLconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRLconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } // match: (ORshiftRL [rc] (ANDconst [ac] x) (SLLconst [lc] y)) // cond: lc > rc && ac == ^((1< rc && ac == ^((1< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftRO x (MOVDconst [c]) [d]) // result: (ORconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } // match: (ORshiftRO y:(RORconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64RORconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64REV(v *Value) bool { v_0 := v.Args[0] // match: (REV (REV p)) // result: p for { if v_0.Op != OpARM64REV { break } p := v_0.Args[0] v.copyOf(p) return true } return false } func rewriteValueARM64_OpARM64REVW(v *Value) bool { v_0 := v.Args[0] // match: (REVW (REVW p)) // result: p for { if v_0.Op != OpARM64REVW { break } p := v_0.Args[0] v.copyOf(p) return true } return false } func rewriteValueARM64_OpARM64ROR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ROR x (MOVDconst [c])) // result: (RORconst x [c&63]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64RORconst) v.AuxInt = int64ToAuxInt(c & 63) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64RORW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (RORW x (MOVDconst [c])) // result: (RORWconst x [c&31]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64RORWconst) v.AuxInt = int64ToAuxInt(c & 31) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64SBCSflags(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SBCSflags x y (Select1 (NEGSflags (NEG (NGCzerocarry bo))))) // result: (SBCSflags x y bo) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64NEGSflags { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64NEG || v_2_0_0.Type != typ.UInt64 { break } v_2_0_0_0 := v_2_0_0.Args[0] if v_2_0_0_0.Op != OpARM64NGCzerocarry || v_2_0_0_0.Type != typ.UInt64 { break } bo := v_2_0_0_0.Args[0] v.reset(OpARM64SBCSflags) v.AddArg3(x, y, bo) return true } // match: (SBCSflags x y (Select1 (NEGSflags (MOVDconst [0])))) // result: (SUBSflags x y) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64NEGSflags { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64MOVDconst || auxIntToInt64(v_2_0_0.AuxInt) != 0 { break } v.reset(OpARM64SUBSflags) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64SLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SLL x (MOVDconst [c])) // result: (SLLconst x [c&63]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(c & 63) v.AddArg(x) return true } // match: (SLL x (ANDconst [63] y)) // result: (SLL x y) for { x := v_0 if v_1.Op != OpARM64ANDconst || auxIntToInt64(v_1.AuxInt) != 63 { break } y := v_1.Args[0] v.reset(OpARM64SLL) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64SLLconst(v *Value) bool { v_0 := v.Args[0] // match: (SLLconst [c] (MOVDconst [d])) // result: (MOVDconst [d<>uint64(c)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(d >> uint64(c)) return true } // match: (SRAconst [rc] (SLLconst [lc] x)) // cond: lc > rc // result: (SBFIZ [armBFAuxInt(lc-rc, 64-lc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc > rc) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc-rc, 64-lc)) v.AddArg(x) return true } // match: (SRAconst [rc] (SLLconst [lc] x)) // cond: lc <= rc // result: (SBFX [armBFAuxInt(rc-lc, 64-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc <= rc) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc-lc, 64-rc)) v.AddArg(x) return true } // match: (SRAconst [rc] (MOVWreg x)) // cond: rc < 32 // result: (SBFX [armBFAuxInt(rc, 32-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWreg { break } x := v_0.Args[0] if !(rc < 32) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 32-rc)) v.AddArg(x) return true } // match: (SRAconst [rc] (MOVHreg x)) // cond: rc < 16 // result: (SBFX [armBFAuxInt(rc, 16-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHreg { break } x := v_0.Args[0] if !(rc < 16) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 16-rc)) v.AddArg(x) return true } // match: (SRAconst [rc] (MOVBreg x)) // cond: rc < 8 // result: (SBFX [armBFAuxInt(rc, 8-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBreg { break } x := v_0.Args[0] if !(rc < 8) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8-rc)) v.AddArg(x) return true } // match: (SRAconst [sc] (SBFIZ [bfc] x)) // cond: sc < bfc.getARM64BFlsb() // result: (SBFIZ [armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SBFIZ { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc < bfc.getARM64BFlsb()) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())) v.AddArg(x) return true } // match: (SRAconst [sc] (SBFIZ [bfc] x)) // cond: sc >= bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() // result: (SBFX [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SBFIZ { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc >= bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth()) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64SRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SRL x (MOVDconst [c])) // result: (SRLconst x [c&63]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(c & 63) v.AddArg(x) return true } // match: (SRL x (ANDconst [63] y)) // result: (SRL x y) for { x := v_0 if v_1.Op != OpARM64ANDconst || auxIntToInt64(v_1.AuxInt) != 63 { break } y := v_1.Args[0] v.reset(OpARM64SRL) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64SRLconst(v *Value) bool { v_0 := v.Args[0] // match: (SRLconst [c] (MOVDconst [d])) // result: (MOVDconst [int64(uint64(d)>>uint64(c))]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint64(d) >> uint64(c))) return true } // match: (SRLconst [c] (SLLconst [c] x)) // cond: 0 < c && c < 64 // result: (ANDconst [1<= 32 // result: (MOVDconst [0]) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg { break } if !(rc >= 32) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SRLconst [rc] (MOVHUreg x)) // cond: rc >= 16 // result: (MOVDconst [0]) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg { break } if !(rc >= 16) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SRLconst [rc] (MOVBUreg x)) // cond: rc >= 8 // result: (MOVDconst [0]) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg { break } if !(rc >= 8) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SRLconst [rc] (SLLconst [lc] x)) // cond: lc > rc // result: (UBFIZ [armBFAuxInt(lc-rc, 64-lc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc > rc) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc-rc, 64-lc)) v.AddArg(x) return true } // match: (SRLconst [rc] (SLLconst [lc] x)) // cond: lc < rc // result: (UBFX [armBFAuxInt(rc-lc, 64-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < rc) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc-lc, 64-rc)) v.AddArg(x) return true } // match: (SRLconst [rc] (MOVWUreg x)) // cond: rc < 32 // result: (UBFX [armBFAuxInt(rc, 32-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg { break } x := v_0.Args[0] if !(rc < 32) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 32-rc)) v.AddArg(x) return true } // match: (SRLconst [rc] (MOVHUreg x)) // cond: rc < 16 // result: (UBFX [armBFAuxInt(rc, 16-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg { break } x := v_0.Args[0] if !(rc < 16) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 16-rc)) v.AddArg(x) return true } // match: (SRLconst [rc] (MOVBUreg x)) // cond: rc < 8 // result: (UBFX [armBFAuxInt(rc, 8-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg { break } x := v_0.Args[0] if !(rc < 8) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8-rc)) v.AddArg(x) return true } // match: (SRLconst [sc] (ANDconst [ac] x)) // cond: isARM64BFMask(sc, ac, sc) // result: (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } ac := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(sc, ac, sc)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc, arm64BFWidth(ac, sc))) v.AddArg(x) return true } // match: (SRLconst [sc] (UBFX [bfc] x)) // cond: sc < bfc.getARM64BFwidth() // result: (UBFX [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc < bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } // match: (SRLconst [sc] (UBFIZ [bfc] x)) // cond: sc == bfc.getARM64BFlsb() // result: (ANDconst [1< bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() // result: (UBFX [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFIZ { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc > bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64STP(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (STP [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (STP [off1+int32(off2)] {sym} ptr val1 val2 mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val1 := v_1 val2 := v_2 mem := v_3 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg4(ptr, val1, val2, mem) return true } // match: (STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (STP [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val1 := v_1 val2 := v_2 mem := v_3 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg4(ptr, val1, val2, mem) return true } // match: (STP [off] {sym} ptr (MOVDconst [0]) (MOVDconst [0]) mem) // result: (MOVQstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 || v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64SUB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUB x (MOVDconst [c])) // result: (SUBconst [c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (SUB a l:(MUL x y)) // cond: l.Uses==1 && clobber(l) // result: (MSUB a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MUL { break } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MSUB) v.AddArg3(a, x, y) return true } // match: (SUB a l:(MNEG x y)) // cond: l.Uses==1 && clobber(l) // result: (MADD a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MNEG { break } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MADD) v.AddArg3(a, x, y) return true } // match: (SUB a l:(MULW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MSUBW a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MULW { break } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MSUBW) v.AddArg3(a, x, y) return true } // match: (SUB a l:(MNEGW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MADDW a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MNEGW { break } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MADDW) v.AddArg3(a, x, y) return true } // match: (SUB x x) // result: (MOVDconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SUB x (SUB y z)) // result: (SUB (ADD x z) y) for { x := v_0 if v_1.Op != OpARM64SUB { break } z := v_1.Args[1] y := v_1.Args[0] v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADD, v.Type) v0.AddArg2(x, z) v.AddArg2(v0, y) return true } // match: (SUB (SUB x y) z) // result: (SUB x (ADD y z)) for { if v_0.Op != OpARM64SUB { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADD, y.Type) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } // match: (SUB x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (SUBshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (SUB x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (SUBshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64SUBshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (SUB x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (SUBshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64SUBshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64SUBconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SUBconst [c] (MOVDconst [d])) // result: (MOVDconst [d-c]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(d - c) return true } // match: (SUBconst [c] (SUBconst [d] x)) // result: (ADDconst [-c-d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SUBconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(-c - d) v.AddArg(x) return true } // match: (SUBconst [c] (ADDconst [d] x)) // result: (ADDconst [-c+d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ADDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(-c + d) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64SUBshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBshiftLL x (MOVDconst [c]) [d]) // result: (SUBconst x [int64(uint64(c)<>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (SUBshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64SUBshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBshiftRL x (MOVDconst [c]) [d]) // result: (SUBconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (SUBshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64TST(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (TST x (MOVDconst [c])) // result: (TSTconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (TST x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (TST x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (TST x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (TST x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64TSTW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (TSTW x (MOVDconst [c])) // result: (TSTWconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTWconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueARM64_OpARM64TSTWconst(v *Value) bool { v_0 := v.Args[0] // match: (TSTWconst (MOVDconst [x]) [y]) // result: (FlagConstant [logicFlags32(int32(x)&y)]) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(logicFlags32(int32(x) & y)) return true } return false } func rewriteValueARM64_OpARM64TSTconst(v *Value) bool { v_0 := v.Args[0] // match: (TSTconst (MOVDconst [x]) [y]) // result: (FlagConstant [logicFlags64(x&y)]) for { y := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(logicFlags64(x & y)) return true } return false } func rewriteValueARM64_OpARM64TSTshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TSTshiftLL (MOVDconst [c]) x [d]) // result: (TSTconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftLL x (MOVDconst [c]) [d]) // result: (TSTconst x [int64(uint64(c)< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftRA x (MOVDconst [c]) [d]) // result: (TSTconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64TSTshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TSTshiftRL (MOVDconst [c]) x [d]) // result: (TSTconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftRL x (MOVDconst [c]) [d]) // result: (TSTconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64TSTshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TSTshiftRO (MOVDconst [c]) x [d]) // result: (TSTconst [c] (RORconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftRO x (MOVDconst [c]) [d]) // result: (TSTconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64UBFIZ(v *Value) bool { v_0 := v.Args[0] // match: (UBFIZ [bfc] (SLLconst [sc] x)) // cond: sc < bfc.getARM64BFwidth() // result: (UBFIZ [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(sc < bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64UBFX(v *Value) bool { v_0 := v.Args[0] // match: (UBFX [bfc] (ANDconst [c] x)) // cond: isARM64BFMask(0, c, 0) && bfc.getARM64BFlsb() + bfc.getARM64BFwidth() <= arm64BFWidth(c, 0) // result: (UBFX [bfc] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(0, c, 0) && bfc.getARM64BFlsb()+bfc.getARM64BFwidth() <= arm64BFWidth(c, 0)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } // match: (UBFX [bfc] (SRLconst [sc] x)) // cond: sc+bfc.getARM64BFwidth()+bfc.getARM64BFlsb() < 64 // result: (UBFX [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth())] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64SRLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(sc+bfc.getARM64BFwidth()+bfc.getARM64BFlsb() < 64) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth())) v.AddArg(x) return true } // match: (UBFX [bfc] (SLLconst [sc] x)) // cond: sc == bfc.getARM64BFlsb() // result: (ANDconst [1< bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() // result: (UBFIZ [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(sc > bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64UDIV(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (UDIV x (MOVDconst [1])) // result: x for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.copyOf(x) return true } // match: (UDIV x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SRLconst [log64(c)] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } // match: (UDIV (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint64(c)/uint64(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) / uint64(d))) return true } return false } func rewriteValueARM64_OpARM64UDIVW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (UDIVW x (MOVDconst [c])) // cond: uint32(c)==1 // result: x for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(uint32(c) == 1) { break } v.copyOf(x) return true } // match: (UDIVW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) && is32Bit(c) // result: (SRLconst [log64(c)] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c) && is32Bit(c)) { break } v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } // match: (UDIVW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint32(c)/uint32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint32(c) / uint32(d))) return true } return false } func rewriteValueARM64_OpARM64UMOD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (UMOD x y) // result: (MSUB x y (UDIV x y)) for { if v.Type != typ.UInt64 { break } x := v_0 y := v_1 v.reset(OpARM64MSUB) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64UDIV, typ.UInt64) v0.AddArg2(x, y) v.AddArg3(x, y, v0) return true } // match: (UMOD _ (MOVDconst [1])) // result: (MOVDconst [0]) for { if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (UMOD x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (ANDconst [c-1] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c - 1) v.AddArg(x) return true } // match: (UMOD (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint64(c)%uint64(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) % uint64(d))) return true } return false } func rewriteValueARM64_OpARM64UMODW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (UMODW x y) // result: (MSUBW x y (UDIVW x y)) for { if v.Type != typ.UInt32 { break } x := v_0 y := v_1 v.reset(OpARM64MSUBW) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpARM64UDIVW, typ.UInt32) v0.AddArg2(x, y) v.AddArg3(x, y, v0) return true } // match: (UMODW _ (MOVDconst [c])) // cond: uint32(c)==1 // result: (MOVDconst [0]) for { if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(uint32(c) == 1) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (UMODW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) && is32Bit(c) // result: (ANDconst [c-1] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c) && is32Bit(c)) { break } v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c - 1) v.AddArg(x) return true } // match: (UMODW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint32(c)%uint32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint32(c) % uint32(d))) return true } return false } func rewriteValueARM64_OpARM64XOR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (XOR x (MOVDconst [c])) // result: (XORconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (XOR x x) // result: (MOVDconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (XOR x (MVN y)) // result: (EON x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MVN { continue } y := v_1.Args[0] v.reset(OpARM64EON) v.AddArg2(x, y) return true } break } // match: (XOR x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (XOR x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (XOR x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (XOR x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64XORconst(v *Value) bool { v_0 := v.Args[0] // match: (XORconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (XORconst [-1] x) // result: (MVN x) for { if auxIntToInt64(v.AuxInt) != -1 { break } x := v_0 v.reset(OpARM64MVN) v.AddArg(x) return true } // match: (XORconst [c] (MOVDconst [d])) // result: (MOVDconst [c^d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c ^ d) return true } // match: (XORconst [c] (XORconst [d] x)) // result: (XORconst [c^d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64XORconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c ^ d) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64XORshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (XORshiftLL (MOVDconst [c]) x [d]) // result: (XORconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftLL x (MOVDconst [c]) [d]) // result: (XORconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) // result: (REV16W x) for { if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (XORshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff // result: (REV16W x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (XORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) // result: (REV16 x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { break } v.reset(OpARM64REV16) v.AddArg(x) return true } // match: (XORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) // result: (REV16 (ANDconst [0xffffffff] x)) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16) v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) v0.AuxInt = int64ToAuxInt(0xffffffff) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftLL [c] (SRLconst x [64-c]) x2) // result: (EXTRconst [64-c] x2 x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { break } x := v_0.Args[0] x2 := v_1 v.reset(OpARM64EXTRconst) v.AuxInt = int64ToAuxInt(64 - c) v.AddArg2(x2, x) return true } // match: (XORshiftLL [c] (UBFX [bfc] x) x2) // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) // result: (EXTRWconst [32-c] x2 x) for { t := v.Type c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] x2 := v_1 if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { break } v.reset(OpARM64EXTRWconst) v.AuxInt = int64ToAuxInt(32 - c) v.AddArg2(x2, x) return true } return false } func rewriteValueARM64_OpARM64XORshiftRA(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (XORshiftRA (MOVDconst [c]) x [d]) // result: (XORconst [c] (SRAconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftRA x (MOVDconst [c]) [d]) // result: (XORconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (XORshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64XORshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (XORshiftRL (MOVDconst [c]) x [d]) // result: (XORconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftRL x (MOVDconst [c]) [d]) // result: (XORconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (XORshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64XORshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (XORshiftRO (MOVDconst [c]) x [d]) // result: (XORconst [c] (RORconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftRO x (MOVDconst [c]) [d]) // result: (XORconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } // match: (XORshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpAddr(v *Value) bool { v_0 := v.Args[0] // match: (Addr {sym} base) // result: (MOVDaddr {sym} base) for { sym := auxToSym(v.Aux) base := v_0 v.reset(OpARM64MOVDaddr) v.Aux = symToAux(sym) v.AddArg(base) return true } } func rewriteValueARM64_OpAtomicAnd32(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd32 ptr val mem) // result: (Select1 (LoweredAtomicAnd32 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd32, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicAnd32Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd32Variant ptr val mem) // result: (Select1 (LoweredAtomicAnd32Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd32Variant, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicAnd8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd8 ptr val mem) // result: (Select1 (LoweredAtomicAnd8 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd8, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicAnd8Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd8Variant ptr val mem) // result: (Select1 (LoweredAtomicAnd8Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd8Variant, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr32(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr32 ptr val mem) // result: (Select1 (LoweredAtomicOr32 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr32, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr32Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr32Variant ptr val mem) // result: (Select1 (LoweredAtomicOr32Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr32Variant, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr8 ptr val mem) // result: (Select1 (LoweredAtomicOr8 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr8, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr8Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr8Variant ptr val mem) // result: (Select1 (LoweredAtomicOr8Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr8Variant, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAvg64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Avg64u x y) // result: (ADD (SRLconst (SUB x y) [1]) y) for { t := v.Type x := v_0 y := v_1 v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, t) v0.AuxInt = int64ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpARM64SUB, t) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg2(v0, y) return true } } func rewriteValueARM64_OpBitLen32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // result: (SUB (MOVDconst [32]) (CLZW x)) for { x := v_0 v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(32) v1 := b.NewValue0(v.Pos, OpARM64CLZW, typ.Int) v1.AddArg(x) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpBitLen64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // result: (SUB (MOVDconst [64]) (CLZ x)) for { x := v_0 v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(64) v1 := b.NewValue0(v.Pos, OpARM64CLZ, typ.Int) v1.AddArg(x) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpBitRev16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitRev16 x) // result: (SRLconst [48] (RBIT x)) for { x := v_0 v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(48) v0 := b.NewValue0(v.Pos, OpARM64RBIT, typ.UInt64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpBitRev8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitRev8 x) // result: (SRLconst [56] (RBIT x)) for { x := v_0 v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(56) v0 := b.NewValue0(v.Pos, OpARM64RBIT, typ.UInt64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CondSelect x y boolval) // cond: flagArg(boolval) != nil // result: (CSEL [boolval.Op] x y flagArg(boolval)) for { x := v_0 y := v_1 boolval := v_2 if !(flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(boolval.Op) v.AddArg3(x, y, flagArg(boolval)) return true } // match: (CondSelect x y boolval) // cond: flagArg(boolval) == nil // result: (CSEL [OpARM64NotEqual] x y (TSTWconst [1] boolval)) for { x := v_0 y := v_1 boolval := v_2 if !(flagArg(boolval) == nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(1) v0.AddArg(boolval) v.AddArg3(x, y, v0) return true } return false } func rewriteValueARM64_OpConst16(v *Value) bool { // match: (Const16 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt16(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConst32(v *Value) bool { // match: (Const32 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt32(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConst32F(v *Value) bool { // match: (Const32F [val]) // result: (FMOVSconst [float64(val)]) for { val := auxIntToFloat32(v.AuxInt) v.reset(OpARM64FMOVSconst) v.AuxInt = float64ToAuxInt(float64(val)) return true } } func rewriteValueARM64_OpConst64(v *Value) bool { // match: (Const64 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt64(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConst64F(v *Value) bool { // match: (Const64F [val]) // result: (FMOVDconst [float64(val)]) for { val := auxIntToFloat64(v.AuxInt) v.reset(OpARM64FMOVDconst) v.AuxInt = float64ToAuxInt(float64(val)) return true } } func rewriteValueARM64_OpConst8(v *Value) bool { // match: (Const8 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt8(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConstBool(v *Value) bool { // match: (ConstBool [t]) // result: (MOVDconst [b2i(t)]) for { t := auxIntToBool(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(t)) return true } } func rewriteValueARM64_OpConstNil(v *Value) bool { // match: (ConstNil) // result: (MOVDconst [0]) for { v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } } func rewriteValueARM64_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (CLZW (RBITW (ORconst [0x10000] x))) for { t := v.Type x := v_0 v.reset(OpARM64CLZW) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64RBITW, typ.UInt32) v1 := b.NewValue0(v.Pos, OpARM64ORconst, typ.UInt32) v1.AuxInt = int64ToAuxInt(0x10000) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Ctz32 x) // result: (CLZW (RBITW x)) for { t := v.Type x := v_0 v.reset(OpARM64CLZW) v0 := b.NewValue0(v.Pos, OpARM64RBITW, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Ctz64 x) // result: (CLZ (RBIT x)) for { t := v.Type x := v_0 v.reset(OpARM64CLZ) v0 := b.NewValue0(v.Pos, OpARM64RBIT, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (CLZW (RBITW (ORconst [0x100] x))) for { t := v.Type x := v_0 v.reset(OpARM64CLZW) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64RBITW, typ.UInt32) v1 := b.NewValue0(v.Pos, OpARM64ORconst, typ.UInt32) v1.AuxInt = int64ToAuxInt(0x100) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 [false] x y) // result: (DIVW (SignExt16to32 x) (SignExt16to32 y)) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpARM64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (UDIVW (ZeroExt16to32 x) (ZeroExt16to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UDIVW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Div32 [false] x y) // result: (DIVW x y) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpARM64DIVW) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Div64 [false] x y) // result: (DIV x y) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpARM64DIV) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (DIVW (SignExt8to32 x) (SignExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (UDIVW (ZeroExt8to32 x) (ZeroExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UDIVW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq16 x y) // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32 x y) // result: (Equal (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32F x y) // result: (Equal (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64 x y) // result: (Equal (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64F x y) // result: (Equal (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq8 x y) // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqB x y) // result: (XOR (MOVDconst [1]) (XOR x y)) for { x := v_0 y := v_1 v.reset(OpARM64XOR) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpARM64XOR, typ.Bool) v1.AddArg2(x, y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqPtr x y) // result: (Equal (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpFMA(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMA x y z) // result: (FMADDD z x y) for { x := v_0 y := v_1 z := v_2 v.reset(OpARM64FMADDD) v.AddArg3(z, x, y) return true } } func rewriteValueARM64_OpHmul32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Hmul32 x y) // result: (SRAconst (MULL x y) [32]) for { x := v_0 y := v_1 v.reset(OpARM64SRAconst) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpARM64MULL, typ.Int64) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpHmul32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Hmul32u x y) // result: (SRAconst (UMULL x y) [32]) for { x := v_0 y := v_1 v.reset(OpARM64SRAconst) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpARM64UMULL, typ.UInt64) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsInBounds idx len) // result: (LessThanU (CMP idx len)) for { idx := v_0 len := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueARM64_OpIsNonNil(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (IsNonNil ptr) // result: (NotEqual (CMPconst [0] ptr)) for { ptr := v_0 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(0) v0.AddArg(ptr) v.AddArg(v0) return true } } func rewriteValueARM64_OpIsSliceInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsSliceInBounds idx len) // result: (LessEqualU (CMP idx len)) for { idx := v_0 len := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq16 x y) // result: (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq16U x zero:(MOVDconst [0])) // result: (Eq16 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq16) v.AddArg2(x, zero) return true } // match: (Leq16U (MOVDconst [1]) x) // result: (Neq16 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq16U x y) // result: (LessEqualU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32 x y) // result: (LessEqual (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32F x y) // result: (LessEqualF (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualF) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq32U x zero:(MOVDconst [0])) // result: (Eq32 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq32) v.AddArg2(x, zero) return true } // match: (Leq32U (MOVDconst [1]) x) // result: (Neq32 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq32U x y) // result: (LessEqualU (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64 x y) // result: (LessEqual (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64F x y) // result: (LessEqualF (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualF) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq64U x zero:(MOVDconst [0])) // result: (Eq64 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq64) v.AddArg2(x, zero) return true } // match: (Leq64U (MOVDconst [1]) x) // result: (Neq64 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq64U x y) // result: (LessEqualU (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq8 x y) // result: (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq8U x zero:(MOVDconst [0])) // result: (Eq8 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq8) v.AddArg2(x, zero) return true } // match: (Leq8U (MOVDconst [1]) x) // result: (Neq8 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq8U x y) // result: (LessEqualU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less16 x y) // result: (LessThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less16U zero:(MOVDconst [0]) x) // result: (Neq16 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq16) v.AddArg2(zero, x) return true } // match: (Less16U x (MOVDconst [1])) // result: (Eq16 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less16U x y) // result: (LessThanU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 x y) // result: (LessThan (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32F x y) // result: (LessThanF (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanF) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less32U zero:(MOVDconst [0]) x) // result: (Neq32 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq32) v.AddArg2(zero, x) return true } // match: (Less32U x (MOVDconst [1])) // result: (Eq32 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less32U x y) // result: (LessThanU (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 x y) // result: (LessThan (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64F x y) // result: (LessThanF (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanF) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less64U zero:(MOVDconst [0]) x) // result: (Neq64 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq64) v.AddArg2(zero, x) return true } // match: (Less64U x (MOVDconst [1])) // result: (Eq64 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less64U x y) // result: (LessThanU (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less8 x y) // result: (LessThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less8U zero:(MOVDconst [0]) x) // result: (Neq8 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq8) v.AddArg2(zero, x) return true } // match: (Less8U x (MOVDconst [1])) // result: (Eq8 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less8U x y) // result: (LessThanU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Load ptr mem) // cond: t.IsBoolean() // result: (MOVBUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsBoolean()) { break } v.reset(OpARM64MOVBUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is8BitInt(t) && t.IsSigned()) // result: (MOVBload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is8BitInt(t) && t.IsSigned()) { break } v.reset(OpARM64MOVBload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is8BitInt(t) && !t.IsSigned()) // result: (MOVBUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is8BitInt(t) && !t.IsSigned()) { break } v.reset(OpARM64MOVBUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is16BitInt(t) && t.IsSigned()) // result: (MOVHload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t) && t.IsSigned()) { break } v.reset(OpARM64MOVHload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is16BitInt(t) && !t.IsSigned()) // result: (MOVHUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t) && !t.IsSigned()) { break } v.reset(OpARM64MOVHUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is32BitInt(t) && t.IsSigned()) // result: (MOVWload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t) && t.IsSigned()) { break } v.reset(OpARM64MOVWload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is32BitInt(t) && !t.IsSigned()) // result: (MOVWUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t) && !t.IsSigned()) { break } v.reset(OpARM64MOVWUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpARM64MOVDload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (FMOVSload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitFloat(t)) { break } v.reset(OpARM64FMOVSload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (FMOVDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitFloat(t)) { break } v.reset(OpARM64FMOVDload) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpLocalAddr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (LocalAddr {sym} base mem) // cond: t.Elem().HasPointers() // result: (MOVDaddr {sym} (SPanchored base mem)) for { t := v.Type sym := auxToSym(v.Aux) base := v_0 mem := v_1 if !(t.Elem().HasPointers()) { break } v.reset(OpARM64MOVDaddr) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr) v0.AddArg2(base, mem) v.AddArg(v0) return true } // match: (LocalAddr {sym} base _) // cond: !t.Elem().HasPointers() // result: (MOVDaddr {sym} base) for { t := v.Type sym := auxToSym(v.Aux) base := v_0 if !(!t.Elem().HasPointers()) { break } v.reset(OpARM64MOVDaddr) v.Aux = symToAux(sym) v.AddArg(base) return true } return false } func rewriteValueARM64_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16 x y) // result: (MODW (SignExt16to32 x) (SignExt16to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64MODW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (UMODW (ZeroExt16to32 x) (ZeroExt16to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UMODW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mod32 x y) // result: (MODW x y) for { x := v_0 y := v_1 v.reset(OpARM64MODW) v.AddArg2(x, y) return true } } func rewriteValueARM64_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mod64 x y) // result: (MOD x y) for { x := v_0 y := v_1 v.reset(OpARM64MOD) v.AddArg2(x, y) return true } } func rewriteValueARM64_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (MODW (SignExt8to32 x) (SignExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64MODW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (UMODW (ZeroExt8to32 x) (ZeroExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UMODW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBUload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [2] dst src mem) // result: (MOVHstore dst (MOVHUload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVHstore) v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBUload [2] src mem) (MOVHstore dst (MOVHUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AuxInt = int32ToAuxInt(2) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [4] dst src mem) // result: (MOVWstore dst (MOVWUload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVWstore) v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBUload [4] src mem) (MOVWstore dst (MOVWUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [6] dst src mem) // result: (MOVHstore [4] dst (MOVHUload [4] src mem) (MOVWstore dst (MOVWUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [7] dst src mem) // result: (MOVWstore [3] dst (MOVWUload [3] src mem) (MOVWstore dst (MOVWUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [8] dst src mem) // result: (MOVDstore dst (MOVDload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBUload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [10] dst src mem) // result: (MOVHstore [8] dst (MOVHUload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [11] dst src mem) // result: (MOVDstore [3] dst (MOVDload [3] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 11 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [12] dst src mem) // result: (MOVWstore [8] dst (MOVWUload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [13] dst src mem) // result: (MOVDstore [5] dst (MOVDload [5] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 13 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(5) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(5) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [14] dst src mem) // result: (MOVDstore [6] dst (MOVDload [6] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 14 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(6) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(6) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [15] dst src mem) // result: (MOVDstore [7] dst (MOVDload [7] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 15 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(7) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(7) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [16] dst src mem) // result: (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v.AddArg4(dst, v0, v2, mem) return true } // match: (Move [32] dst src mem) // result: (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AuxInt = int32ToAuxInt(16) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v5.AddArg2(src, mem) v4.AddArg(v5) v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v6.AddArg(v5) v3.AddArg4(dst, v4, v6, mem) v.AddArg4(dst, v0, v2, v3) return true } // match: (Move [48] dst src mem) // result: (STP [32] dst (Select0 (LDP [32] src mem)) (Select1 (LDP [32] src mem)) (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AuxInt = int32ToAuxInt(32) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v3.AuxInt = int32ToAuxInt(16) v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v5.AuxInt = int32ToAuxInt(16) v5.AddArg2(src, mem) v4.AddArg(v5) v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v6.AddArg(v5) v7 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v9 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v9.AddArg2(src, mem) v8.AddArg(v9) v10 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v10.AddArg(v9) v7.AddArg4(dst, v8, v10, mem) v3.AddArg4(dst, v4, v6, v7) v.AddArg4(dst, v0, v2, v3) return true } // match: (Move [64] dst src mem) // result: (STP [48] dst (Select0 (LDP [48] src mem)) (Select1 (LDP [48] src mem)) (STP [32] dst (Select0 (LDP [32] src mem)) (Select1 (LDP [32] src mem)) (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(48) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AuxInt = int32ToAuxInt(48) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v3.AuxInt = int32ToAuxInt(32) v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v5.AuxInt = int32ToAuxInt(32) v5.AddArg2(src, mem) v4.AddArg(v5) v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v6.AddArg(v5) v7 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v7.AuxInt = int32ToAuxInt(16) v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v9 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v9.AuxInt = int32ToAuxInt(16) v9.AddArg2(src, mem) v8.AddArg(v9) v10 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v10.AddArg(v9) v11 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v12 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v13 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v13.AddArg2(src, mem) v12.AddArg(v13) v14 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v14.AddArg(v13) v11.AddArg4(dst, v12, v14, mem) v7.AddArg4(dst, v8, v10, v11) v3.AddArg4(dst, v4, v6, v7) v.AddArg4(dst, v0, v2, v3) return true } // match: (Move [s] dst src mem) // cond: s%16 != 0 && s%16 <= 8 && s > 16 // result: (Move [8] (OffPtr dst [s-8]) (OffPtr src [s-8]) (Move [s-s%16] dst src mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s%16 != 0 && s%16 <= 8 && s > 16) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s - 8) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s - 8) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(s - s%16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s%16 != 0 && s%16 > 8 && s > 16 // result: (Move [16] (OffPtr dst [s-16]) (OffPtr src [s-16]) (Move [s-s%16] dst src mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s%16 != 0 && s%16 > 8 && s > 16) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s - 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(s - s%16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s) // result: (DUFFCOPY [8 * (64 - s/16)] dst src mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s)) { break } v.reset(OpARM64DUFFCOPY) v.AuxInt = int64ToAuxInt(8 * (64 - s/16)) v.AddArg3(dst, src, mem) return true } // match: (Move [s] dst src mem) // cond: s%16 == 0 && (s > 16*64 || config.noDuffDevice) && logLargeCopy(v, s) // result: (LoweredMove dst src (ADDconst src [s-16]) mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s%16 == 0 && (s > 16*64 || config.noDuffDevice) && logLargeCopy(v, s)) { break } v.reset(OpARM64LoweredMove) v0 := b.NewValue0(v.Pos, OpARM64ADDconst, src.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(src) v.AddArg4(dst, src, v0, mem) return true } return false } func rewriteValueARM64_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq16 x y) // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32 x y) // result: (NotEqual (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32F x y) // result: (NotEqual (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64 x y) // result: (NotEqual (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64F x y) // result: (NotEqual (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq8 x y) // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqPtr x y) // result: (NotEqual (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNot(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Not x) // result: (XOR (MOVDconst [1]) x) for { x := v_0 v.reset(OpARM64XOR) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(1) v.AddArg2(v0, x) return true } } func rewriteValueARM64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] // match: (OffPtr [off] ptr:(SP)) // cond: is32Bit(off) // result: (MOVDaddr [int32(off)] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 if ptr.Op != OpSP || !(is32Bit(off)) { break } v.reset(OpARM64MOVDaddr) v.AuxInt = int32ToAuxInt(int32(off)) v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDconst [off] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(off) v.AddArg(ptr) return true } } func rewriteValueARM64_OpPanicBounds(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 0) { break } v.reset(OpARM64LoweredPanicBoundsA) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 1) { break } v.reset(OpARM64LoweredPanicBoundsB) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 2) { break } v.reset(OpARM64LoweredPanicBoundsC) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } return false } func rewriteValueARM64_OpPopCount16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (FMOVDfpgp (VUADDLV (VCNT (FMOVDgpfp (ZeroExt16to64 x))))) for { t := v.Type x := v_0 v.reset(OpARM64FMOVDfpgp) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64) v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64) v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(x) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpPopCount32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount32 x) // result: (FMOVDfpgp (VUADDLV (VCNT (FMOVDgpfp (ZeroExt32to64 x))))) for { t := v.Type x := v_0 v.reset(OpARM64FMOVDfpgp) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64) v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64) v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpPopCount64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount64 x) // result: (FMOVDfpgp (VUADDLV (VCNT (FMOVDgpfp x)))) for { t := v.Type x := v_0 v.reset(OpARM64FMOVDfpgp) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64) v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64) v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpPrefetchCache(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (PrefetchCache addr mem) // result: (PRFM [0] addr mem) for { addr := v_0 mem := v_1 v.reset(OpARM64PRFM) v.AuxInt = int64ToAuxInt(0) v.AddArg2(addr, mem) return true } } func rewriteValueARM64_OpPrefetchCacheStreamed(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (PrefetchCacheStreamed addr mem) // result: (PRFM [1] addr mem) for { addr := v_0 mem := v_1 v.reset(OpARM64PRFM) v.AuxInt = int64ToAuxInt(1) v.AddArg2(addr, mem) return true } } func rewriteValueARM64_OpPubBarrier(v *Value) bool { v_0 := v.Args[0] // match: (PubBarrier mem) // result: (DMB [0xe] mem) for { mem := v_0 v.reset(OpARM64DMB) v.AuxInt = int64ToAuxInt(0xe) v.AddArg(mem) return true } } func rewriteValueARM64_OpRotateLeft16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (RotateLeft16 x (MOVDconst [c])) // result: (Or16 (Lsh16x64 x (MOVDconst [c&15])) (Rsh16Ux64 x (MOVDconst [-c&15]))) for { t := v.Type x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(c & 15) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpRsh16Ux64, t) v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v3.AuxInt = int64ToAuxInt(-c & 15) v2.AddArg2(x, v3) v.AddArg2(v0, v2) return true } // match: (RotateLeft16 x y) // result: (RORW (ORshiftLL (ZeroExt16to32 x) (ZeroExt16to32 x) [16]) (NEG y)) for { t := v.Type x := v_0 y := v_1 v.reset(OpARM64RORW) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64ORshiftLL, typ.UInt32) v0.AuxInt = int64ToAuxInt(16) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v2 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) v2.AddArg(y) v.AddArg2(v0, v2) return true } } func rewriteValueARM64_OpRotateLeft32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (RotateLeft32 x y) // result: (RORW x (NEG y)) for { x := v_0 y := v_1 v.reset(OpARM64RORW) v0 := b.NewValue0(v.Pos, OpARM64NEG, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } } func rewriteValueARM64_OpRotateLeft64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (RotateLeft64 x y) // result: (ROR x (NEG y)) for { x := v_0 y := v_1 v.reset(OpARM64ROR) v0 := b.NewValue0(v.Pos, OpARM64NEG, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } } func rewriteValueARM64_OpRotateLeft8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (RotateLeft8 x (MOVDconst [c])) // result: (Or8 (Lsh8x64 x (MOVDconst [c&7])) (Rsh8Ux64 x (MOVDconst [-c&7]))) for { t := v.Type x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(c & 7) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpRsh8Ux64, t) v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v3.AuxInt = int64ToAuxInt(-c & 7) v2.AddArg2(x, v3) v.AddArg2(v0, v2) return true } // match: (RotateLeft8 x y) // result: (OR (SLL x (ANDconst [7] y)) (SRL (ZeroExt8to64 x) (ANDconst [7] (NEG y)))) for { t := v.Type x := v_0 y := v_1 v.reset(OpARM64OR) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v1 := b.NewValue0(v.Pos, OpARM64ANDconst, typ.Int64) v1.AuxInt = int64ToAuxInt(7) v1.AddArg(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpARM64SRL, t) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(x) v4 := b.NewValue0(v.Pos, OpARM64ANDconst, typ.Int64) v4.AuxInt = int64ToAuxInt(7) v5 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) v5.AddArg(y) v4.AddArg(v5) v2.AddArg2(v3, v4) v.AddArg2(v0, v2) return true } } func rewriteValueARM64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpSelect0(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uhilo x y)) // result: (UMULH x y) for { if v_0.Op != OpMul64uhilo { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64UMULH) v.AddArg2(x, y) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCSflags x y (Select1 (ADDSconstflags [-1] c)))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64ADCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpARM64ADDSconstflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AuxInt = int64ToAuxInt(-1) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y bo)) // result: (Select0 (SBCSflags x y (Select1 (NEGSflags bo)))) for { if v_0.Op != OpSub64borrow { break } bo := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64SBCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpARM64NEGSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(bo) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Mul64uover x y)) // result: (MUL x y) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MUL) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpSelect1(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uhilo x y)) // result: (MUL x y) for { if v_0.Op != OpMul64uhilo { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MUL) v.AddArg2(x, y) return true } // match: (Select1 (Add64carry x y c)) // result: (ADCzerocarry (Select1 (ADCSflags x y (Select1 (ADDSconstflags [-1] c))))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpARM64ADCzerocarry) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64ADCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v2 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v3 := b.NewValue0(v.Pos, OpARM64ADDSconstflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v3.AuxInt = int64ToAuxInt(-1) v3.AddArg(c) v2.AddArg(v3) v1.AddArg3(x, y, v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y bo)) // result: (NEG (NGCzerocarry (Select1 (SBCSflags x y (Select1 (NEGSflags bo)))))) for { if v_0.Op != OpSub64borrow { break } bo := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpARM64NEG) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64NGCzerocarry, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpARM64SBCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpARM64NEGSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v4.AddArg(bo) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul64uover x y)) // result: (NotEqual (CMPconst (UMULH x y) [0])) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64UMULH, typ.UInt64) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVDstore _ (MOVDconst [sz]) s2:(MOVDstore _ src s3:(MOVDstore {t} _ dst mem))))) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(s1, s2, s3, call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpARM64CALLstatic || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpARM64MOVDstore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpARM64MOVDconst { break } sz := auxIntToInt64(s1_1.AuxInt) s2 := s1.Args[2] if s2.Op != OpARM64MOVDstore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpARM64MOVDstore { break } mem := s3.Args[2] dst := s3.Args[1] if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVDconst [sz]) mem)) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpARM64CALLstatic || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpARM64MOVDconst { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } return false } func rewriteValueARM64_OpSlicemask(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Slicemask x) // result: (SRAconst (NEG x) [63]) for { t := v.Type x := v_0 v.reset(OpARM64SRAconst) v.AuxInt = int64ToAuxInt(63) v0 := b.NewValue0(v.Pos, OpARM64NEG, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (Store {t} ptr val mem) // cond: t.Size() == 1 // result: (MOVBstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 1) { break } v.reset(OpARM64MOVBstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 2 // result: (MOVHstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 2) { break } v.reset(OpARM64MOVHstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && !t.IsFloat() // result: (MOVWstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && !t.IsFloat()) { break } v.reset(OpARM64MOVWstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && !t.IsFloat() // result: (MOVDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && !t.IsFloat()) { break } v.reset(OpARM64MOVDstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && t.IsFloat() // result: (FMOVSstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && t.IsFloat()) { break } v.reset(OpARM64FMOVSstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && t.IsFloat() // result: (FMOVDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && t.IsFloat()) { break } v.reset(OpARM64FMOVDstore) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [0] _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_1 v.copyOf(mem) return true } // match: (Zero [1] ptr mem) // result: (MOVBstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [2] ptr mem) // result: (MOVHstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVHstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [4] ptr mem) // result: (MOVWstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVWstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [3] ptr mem) // result: (MOVBstore [2] ptr (MOVDconst [0]) (MOVHstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [5] ptr mem) // result: (MOVBstore [4] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [6] ptr mem) // result: (MOVHstore [4] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [7] ptr mem) // result: (MOVWstore [3] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [8] ptr mem) // result: (MOVDstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [9] ptr mem) // result: (MOVBstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [10] ptr mem) // result: (MOVHstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [11] ptr mem) // result: (MOVDstore [3] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 11 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [12] ptr mem) // result: (MOVWstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [13] ptr mem) // result: (MOVDstore [5] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 13 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(5) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [14] ptr mem) // result: (MOVDstore [6] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 14 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(6) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [15] ptr mem) // result: (MOVDstore [7] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 15 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(7) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [16] ptr mem) // result: (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(0) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg4(ptr, v0, v0, mem) return true } // match: (Zero [32] ptr mem) // result: (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v1.AuxInt = int32ToAuxInt(0) v1.AddArg4(ptr, v0, v0, mem) v.AddArg4(ptr, v0, v0, v1) return true } // match: (Zero [48] ptr mem) // result: (STP [32] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v1.AuxInt = int32ToAuxInt(16) v2 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v2.AuxInt = int32ToAuxInt(0) v2.AddArg4(ptr, v0, v0, mem) v1.AddArg4(ptr, v0, v0, v2) v.AddArg4(ptr, v0, v0, v1) return true } // match: (Zero [64] ptr mem) // result: (STP [48] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [32] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(48) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v1.AuxInt = int32ToAuxInt(32) v2 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v2.AuxInt = int32ToAuxInt(16) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v3.AuxInt = int32ToAuxInt(0) v3.AddArg4(ptr, v0, v0, mem) v2.AddArg4(ptr, v0, v0, v3) v1.AddArg4(ptr, v0, v0, v2) v.AddArg4(ptr, v0, v0, v1) return true } // match: (Zero [s] ptr mem) // cond: s%16 != 0 && s%16 <= 8 && s > 16 // result: (Zero [8] (OffPtr ptr [s-8]) (Zero [s-s%16] ptr mem)) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 != 0 && s%16 <= 8 && s > 16) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpOffPtr, ptr.Type) v0.AuxInt = int64ToAuxInt(s - 8) v0.AddArg(ptr) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(s - s%16) v1.AddArg2(ptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] ptr mem) // cond: s%16 != 0 && s%16 > 8 && s > 16 // result: (Zero [16] (OffPtr ptr [s-16]) (Zero [s-s%16] ptr mem)) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 != 0 && s%16 > 8 && s > 16) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, ptr.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(ptr) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(s - s%16) v1.AddArg2(ptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] ptr mem) // cond: s%16 == 0 && s > 64 && s <= 16*64 && !config.noDuffDevice // result: (DUFFZERO [4 * (64 - s/16)] ptr mem) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 == 0 && s > 64 && s <= 16*64 && !config.noDuffDevice) { break } v.reset(OpARM64DUFFZERO) v.AuxInt = int64ToAuxInt(4 * (64 - s/16)) v.AddArg2(ptr, mem) return true } // match: (Zero [s] ptr mem) // cond: s%16 == 0 && (s > 16*64 || config.noDuffDevice) // result: (LoweredZero ptr (ADDconst [s-16] ptr) mem) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 == 0 && (s > 16*64 || config.noDuffDevice)) { break } v.reset(OpARM64LoweredZero) v0 := b.NewValue0(v.Pos, OpARM64ADDconst, ptr.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(ptr) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteBlockARM64(b *Block) bool { typ := &b.Func.Config.Types switch b.Kind { case BlockARM64EQ: // match: (EQ (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (EQ (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (EQ (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMP x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMP { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPW x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPW { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] x) yes no) // result: (Z x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64Z, x) return true } // match: (EQ (CMPWconst [0] x) yes no) // result: (ZW x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64ZW, x) return true } // match: (EQ (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (TSTconst [c] x) yes no) // cond: oneBit(c) // result: (TBZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64TSTconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (EQ (TSTWconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64TSTWconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (EQ (FlagConstant [fc]) yes no) // cond: fc.eq() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.eq()) { break } b.Reset(BlockFirst) return true } // match: (EQ (FlagConstant [fc]) yes no) // cond: !fc.eq() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.eq()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64EQ, cmp) return true } case BlockARM64FGE: // match: (FGE (InvertFlags cmp) yes no) // result: (FLE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FLE, cmp) return true } case BlockARM64FGT: // match: (FGT (InvertFlags cmp) yes no) // result: (FLT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FLT, cmp) return true } case BlockARM64FLE: // match: (FLE (InvertFlags cmp) yes no) // result: (FGE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FGE, cmp) return true } case BlockARM64FLT: // match: (FLT (InvertFlags cmp) yes no) // result: (FGT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FGT, cmp) return true } case BlockARM64GE: // match: (GE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GE (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GE, v0) return true } break } // match: (GE (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GE (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GE, v0) return true } // match: (GE (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GE (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GE, v0) return true } break } // match: (GE (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GE (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GE, v0) return true } // match: (GE (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GEnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GEnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GEnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GEnoov, v0) return true } break } // match: (GE (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GEnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GEnoov, v0) return true } break } // match: (GE (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] x) yes no) // result: (TBZ [31] x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(31) return true } // match: (GE (CMPconst [0] x) yes no) // result: (TBZ [63] x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(63) return true } // match: (GE (FlagConstant [fc]) yes no) // cond: fc.ge() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ge()) { break } b.Reset(BlockFirst) return true } // match: (GE (FlagConstant [fc]) yes no) // cond: !fc.ge() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ge()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LE, cmp) return true } case BlockARM64GEnoov: // match: (GEnoov (FlagConstant [fc]) yes no) // cond: fc.geNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.geNoov()) { break } b.Reset(BlockFirst) return true } // match: (GEnoov (FlagConstant [fc]) yes no) // cond: !fc.geNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.geNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GEnoov (InvertFlags cmp) yes no) // result: (LEnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LEnoov, cmp) return true } case BlockARM64GT: // match: (GT (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GT (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GT, v0) return true } break } // match: (GT (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GT (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GT, v0) return true } // match: (GT (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GT (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GT, v0) return true } break } // match: (GT (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GT (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GT, v0) return true } // match: (GT (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GTnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GTnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GTnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GTnoov, v0) return true } break } // match: (GT (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GTnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GTnoov, v0) return true } break } // match: (GT (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (FlagConstant [fc]) yes no) // cond: fc.gt() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.gt()) { break } b.Reset(BlockFirst) return true } // match: (GT (FlagConstant [fc]) yes no) // cond: !fc.gt() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.gt()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LT, cmp) return true } case BlockARM64GTnoov: // match: (GTnoov (FlagConstant [fc]) yes no) // cond: fc.gtNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.gtNoov()) { break } b.Reset(BlockFirst) return true } // match: (GTnoov (FlagConstant [fc]) yes no) // cond: !fc.gtNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.gtNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GTnoov (InvertFlags cmp) yes no) // result: (LTnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LTnoov, cmp) return true } case BlockIf: // match: (If (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpARM64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64EQ, cc) return true } // match: (If (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpARM64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64NE, cc) return true } // match: (If (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpARM64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LT, cc) return true } // match: (If (LessThanU cc) yes no) // result: (ULT cc yes no) for b.Controls[0].Op == OpARM64LessThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULT, cc) return true } // match: (If (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpARM64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LE, cc) return true } // match: (If (LessEqualU cc) yes no) // result: (ULE cc yes no) for b.Controls[0].Op == OpARM64LessEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULE, cc) return true } // match: (If (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpARM64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GT, cc) return true } // match: (If (GreaterThanU cc) yes no) // result: (UGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGT, cc) return true } // match: (If (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GE, cc) return true } // match: (If (GreaterEqualU cc) yes no) // result: (UGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGE, cc) return true } // match: (If (LessThanF cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpARM64LessThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLT, cc) return true } // match: (If (LessEqualF cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpARM64LessEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLE, cc) return true } // match: (If (GreaterThanF cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGT, cc) return true } // match: (If (GreaterEqualF cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGE, cc) return true } // match: (If cond yes no) // result: (TBNZ [0] cond yes no) for { cond := b.Controls[0] b.resetWithControl(BlockARM64TBNZ, cond) b.AuxInt = int64ToAuxInt(0) return true } case BlockJumpTable: // match: (JumpTable idx) // result: (JUMPTABLE {makeJumpTableSym(b)} idx (MOVDaddr {makeJumpTableSym(b)} (SB))) for { idx := b.Controls[0] v0 := b.NewValue0(b.Pos, OpARM64MOVDaddr, typ.Uintptr) v0.Aux = symToAux(makeJumpTableSym(b)) v1 := b.NewValue0(b.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) b.resetWithControl2(BlockARM64JUMPTABLE, idx, v0) b.Aux = symToAux(makeJumpTableSym(b)) return true } case BlockARM64LE: // match: (LE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LE (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LE, v0) return true } break } // match: (LE (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LE (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LE, v0) return true } // match: (LE (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LE (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LE, v0) return true } break } // match: (LE (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LE (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LE, v0) return true } // match: (LE (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LEnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LEnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LEnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LEnoov, v0) return true } break } // match: (LE (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LEnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LEnoov, v0) return true } break } // match: (LE (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (FlagConstant [fc]) yes no) // cond: fc.le() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.le()) { break } b.Reset(BlockFirst) return true } // match: (LE (FlagConstant [fc]) yes no) // cond: !fc.le() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.le()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GE, cmp) return true } case BlockARM64LEnoov: // match: (LEnoov (FlagConstant [fc]) yes no) // cond: fc.leNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.leNoov()) { break } b.Reset(BlockFirst) return true } // match: (LEnoov (FlagConstant [fc]) yes no) // cond: !fc.leNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.leNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LEnoov (InvertFlags cmp) yes no) // result: (GEnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GEnoov, cmp) return true } case BlockARM64LT: // match: (LT (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LT (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LT, v0) return true } break } // match: (LT (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LT (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LT, v0) return true } // match: (LT (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LT (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LT, v0) return true } break } // match: (LT (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LT (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LT, v0) return true } // match: (LT (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LTnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LTnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LTnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LTnoov, v0) return true } break } // match: (LT (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LTnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LTnoov, v0) return true } break } // match: (LT (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] x) yes no) // result: (TBNZ [31] x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(31) return true } // match: (LT (CMPconst [0] x) yes no) // result: (TBNZ [63] x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(63) return true } // match: (LT (FlagConstant [fc]) yes no) // cond: fc.lt() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.lt()) { break } b.Reset(BlockFirst) return true } // match: (LT (FlagConstant [fc]) yes no) // cond: !fc.lt() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.lt()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GT, cmp) return true } case BlockARM64LTnoov: // match: (LTnoov (FlagConstant [fc]) yes no) // cond: fc.ltNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ltNoov()) { break } b.Reset(BlockFirst) return true } // match: (LTnoov (FlagConstant [fc]) yes no) // cond: !fc.ltNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ltNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LTnoov (InvertFlags cmp) yes no) // result: (GTnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GTnoov, cmp) return true } case BlockARM64NE: // match: (NE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (NE (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (NE (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (NE (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (NE (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMP x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (NE (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMP { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPW x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (NE (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPW { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] x) yes no) // result: (NZ x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64NZ, x) return true } // match: (NE (CMPWconst [0] x) yes no) // result: (NZW x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64NZW, x) return true } // match: (NE (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (TSTconst [c] x) yes no) // cond: oneBit(c) // result: (TBNZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64TSTconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (NE (TSTWconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBNZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64TSTWconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (NE (FlagConstant [fc]) yes no) // cond: fc.ne() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ne()) { break } b.Reset(BlockFirst) return true } // match: (NE (FlagConstant [fc]) yes no) // cond: !fc.ne() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ne()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64NE, cmp) return true } case BlockARM64NZ: // match: (NZ (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpARM64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64EQ, cc) return true } // match: (NZ (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpARM64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64NE, cc) return true } // match: (NZ (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpARM64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LT, cc) return true } // match: (NZ (LessThanU cc) yes no) // result: (ULT cc yes no) for b.Controls[0].Op == OpARM64LessThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULT, cc) return true } // match: (NZ (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpARM64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LE, cc) return true } // match: (NZ (LessEqualU cc) yes no) // result: (ULE cc yes no) for b.Controls[0].Op == OpARM64LessEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULE, cc) return true } // match: (NZ (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpARM64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GT, cc) return true } // match: (NZ (GreaterThanU cc) yes no) // result: (UGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGT, cc) return true } // match: (NZ (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GE, cc) return true } // match: (NZ (GreaterEqualU cc) yes no) // result: (UGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGE, cc) return true } // match: (NZ (LessThanF cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpARM64LessThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLT, cc) return true } // match: (NZ (LessEqualF cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpARM64LessEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLE, cc) return true } // match: (NZ (GreaterThanF cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGT, cc) return true } // match: (NZ (GreaterEqualF cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGE, cc) return true } // match: (NZ (ANDconst [c] x) yes no) // cond: oneBit(c) // result: (TBNZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (NZ (MOVDconst [0]) yes no) // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NZ (MOVDconst [c]) yes no) // cond: c != 0 // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(c != 0) { break } b.Reset(BlockFirst) return true } case BlockARM64NZW: // match: (NZW (ANDconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBNZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (NZW (MOVDconst [c]) yes no) // cond: int32(c) == 0 // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) == 0) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NZW (MOVDconst [c]) yes no) // cond: int32(c) != 0 // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) != 0) { break } b.Reset(BlockFirst) return true } case BlockARM64TBNZ: // match: (TBNZ [0] (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpARM64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64EQ, cc) return true } // match: (TBNZ [0] (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpARM64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64NE, cc) return true } // match: (TBNZ [0] (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpARM64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64LT, cc) return true } // match: (TBNZ [0] (LessThanU cc) yes no) // result: (ULT cc yes no) for b.Controls[0].Op == OpARM64LessThanU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64ULT, cc) return true } // match: (TBNZ [0] (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpARM64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64LE, cc) return true } // match: (TBNZ [0] (LessEqualU cc) yes no) // result: (ULE cc yes no) for b.Controls[0].Op == OpARM64LessEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64ULE, cc) return true } // match: (TBNZ [0] (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpARM64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64GT, cc) return true } // match: (TBNZ [0] (GreaterThanU cc) yes no) // result: (UGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64UGT, cc) return true } // match: (TBNZ [0] (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64GE, cc) return true } // match: (TBNZ [0] (GreaterEqualU cc) yes no) // result: (UGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64UGE, cc) return true } // match: (TBNZ [0] (LessThanF cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpARM64LessThanF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FLT, cc) return true } // match: (TBNZ [0] (LessEqualF cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpARM64LessEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FLE, cc) return true } // match: (TBNZ [0] (GreaterThanF cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FGT, cc) return true } // match: (TBNZ [0] (GreaterEqualF cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FGE, cc) return true } case BlockARM64UGE: // match: (UGE (FlagConstant [fc]) yes no) // cond: fc.uge() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.uge()) { break } b.Reset(BlockFirst) return true } // match: (UGE (FlagConstant [fc]) yes no) // cond: !fc.uge() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.uge()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64ULE, cmp) return true } case BlockARM64UGT: // match: (UGT (FlagConstant [fc]) yes no) // cond: fc.ugt() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ugt()) { break } b.Reset(BlockFirst) return true } // match: (UGT (FlagConstant [fc]) yes no) // cond: !fc.ugt() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ugt()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64ULT, cmp) return true } case BlockARM64ULE: // match: (ULE (FlagConstant [fc]) yes no) // cond: fc.ule() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ule()) { break } b.Reset(BlockFirst) return true } // match: (ULE (FlagConstant [fc]) yes no) // cond: !fc.ule() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ule()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64UGE, cmp) return true } case BlockARM64ULT: // match: (ULT (FlagConstant [fc]) yes no) // cond: fc.ult() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ult()) { break } b.Reset(BlockFirst) return true } // match: (ULT (FlagConstant [fc]) yes no) // cond: !fc.ult() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ult()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64UGT, cmp) return true } case BlockARM64Z: // match: (Z (ANDconst [c] x) yes no) // cond: oneBit(c) // result: (TBZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (Z (MOVDconst [0]) yes no) // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } b.Reset(BlockFirst) return true } // match: (Z (MOVDconst [c]) yes no) // cond: c != 0 // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(c != 0) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockARM64ZW: // match: (ZW (ANDconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (ZW (MOVDconst [c]) yes no) // cond: int32(c) == 0 // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) == 0) { break } b.Reset(BlockFirst) return true } // match: (ZW (MOVDconst [c]) yes no) // cond: int32(c) != 0 // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) != 0) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } diff-1.0.1/internal/benchmarks/testdata/large_02.test000066400000000000000000043524701516001707200224750ustar00rootroot00000000000000From https://go.googlesource.com/go commit 8623503fe54642a21854c551129d550139f3bbac file src/cmd/compile/internal/gc/testdata/arithConst.go -- x -- // run // Code generated by gen/arithConstGen.go. DO NOT EDIT. package main import "fmt" //go:noinline func add_uint64_0_ssa(a uint64) uint64 { return a + 0 } //go:noinline func add_0_uint64_ssa(a uint64) uint64 { return 0 + a } //go:noinline func add_uint64_1_ssa(a uint64) uint64 { return a + 1 } //go:noinline func add_1_uint64_ssa(a uint64) uint64 { return 1 + a } //go:noinline func add_uint64_4294967296_ssa(a uint64) uint64 { return a + 4294967296 } //go:noinline func add_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 + a } //go:noinline func add_uint64_9223372036854775808_ssa(a uint64) uint64 { return a + 9223372036854775808 } //go:noinline func add_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 + a } //go:noinline func add_uint64_18446744073709551615_ssa(a uint64) uint64 { return a + 18446744073709551615 } //go:noinline func add_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 + a } //go:noinline func sub_uint64_0_ssa(a uint64) uint64 { return a - 0 } //go:noinline func sub_0_uint64_ssa(a uint64) uint64 { return 0 - a } //go:noinline func sub_uint64_1_ssa(a uint64) uint64 { return a - 1 } //go:noinline func sub_1_uint64_ssa(a uint64) uint64 { return 1 - a } //go:noinline func sub_uint64_4294967296_ssa(a uint64) uint64 { return a - 4294967296 } //go:noinline func sub_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 - a } //go:noinline func sub_uint64_9223372036854775808_ssa(a uint64) uint64 { return a - 9223372036854775808 } //go:noinline func sub_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 - a } //go:noinline func sub_uint64_18446744073709551615_ssa(a uint64) uint64 { return a - 18446744073709551615 } //go:noinline func sub_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 - a } //go:noinline func div_0_uint64_ssa(a uint64) uint64 { return 0 / a } //go:noinline func div_uint64_1_ssa(a uint64) uint64 { return a / 1 } //go:noinline func div_1_uint64_ssa(a uint64) uint64 { return 1 / a } //go:noinline func div_uint64_4294967296_ssa(a uint64) uint64 { return a / 4294967296 } //go:noinline func div_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 / a } //go:noinline func div_uint64_9223372036854775808_ssa(a uint64) uint64 { return a / 9223372036854775808 } //go:noinline func div_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 / a } //go:noinline func div_uint64_18446744073709551615_ssa(a uint64) uint64 { return a / 18446744073709551615 } //go:noinline func div_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 / a } //go:noinline func mul_uint64_0_ssa(a uint64) uint64 { return a * 0 } //go:noinline func mul_0_uint64_ssa(a uint64) uint64 { return 0 * a } //go:noinline func mul_uint64_1_ssa(a uint64) uint64 { return a * 1 } //go:noinline func mul_1_uint64_ssa(a uint64) uint64 { return 1 * a } //go:noinline func mul_uint64_4294967296_ssa(a uint64) uint64 { return a * 4294967296 } //go:noinline func mul_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 * a } //go:noinline func mul_uint64_9223372036854775808_ssa(a uint64) uint64 { return a * 9223372036854775808 } //go:noinline func mul_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 * a } //go:noinline func mul_uint64_18446744073709551615_ssa(a uint64) uint64 { return a * 18446744073709551615 } //go:noinline func mul_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 * a } //go:noinline func lsh_uint64_0_ssa(a uint64) uint64 { return a << 0 } //go:noinline func lsh_0_uint64_ssa(a uint64) uint64 { return 0 << a } //go:noinline func lsh_uint64_1_ssa(a uint64) uint64 { return a << 1 } //go:noinline func lsh_1_uint64_ssa(a uint64) uint64 { return 1 << a } //go:noinline func lsh_uint64_4294967296_ssa(a uint64) uint64 { return a << uint64(4294967296) } //go:noinline func lsh_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 << a } //go:noinline func lsh_uint64_9223372036854775808_ssa(a uint64) uint64 { return a << uint64(9223372036854775808) } //go:noinline func lsh_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 << a } //go:noinline func lsh_uint64_18446744073709551615_ssa(a uint64) uint64 { return a << uint64(18446744073709551615) } //go:noinline func lsh_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 << a } //go:noinline func rsh_uint64_0_ssa(a uint64) uint64 { return a >> 0 } //go:noinline func rsh_0_uint64_ssa(a uint64) uint64 { return 0 >> a } //go:noinline func rsh_uint64_1_ssa(a uint64) uint64 { return a >> 1 } //go:noinline func rsh_1_uint64_ssa(a uint64) uint64 { return 1 >> a } //go:noinline func rsh_uint64_4294967296_ssa(a uint64) uint64 { return a >> uint64(4294967296) } //go:noinline func rsh_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 >> a } //go:noinline func rsh_uint64_9223372036854775808_ssa(a uint64) uint64 { return a >> uint64(9223372036854775808) } //go:noinline func rsh_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 >> a } //go:noinline func rsh_uint64_18446744073709551615_ssa(a uint64) uint64 { return a >> uint64(18446744073709551615) } //go:noinline func rsh_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 >> a } //go:noinline func mod_0_uint64_ssa(a uint64) uint64 { return 0 % a } //go:noinline func mod_uint64_1_ssa(a uint64) uint64 { return a % 1 } //go:noinline func mod_1_uint64_ssa(a uint64) uint64 { return 1 % a } //go:noinline func mod_uint64_4294967296_ssa(a uint64) uint64 { return a % 4294967296 } //go:noinline func mod_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 % a } //go:noinline func mod_uint64_9223372036854775808_ssa(a uint64) uint64 { return a % 9223372036854775808 } //go:noinline func mod_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 % a } //go:noinline func mod_uint64_18446744073709551615_ssa(a uint64) uint64 { return a % 18446744073709551615 } //go:noinline func mod_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 % a } //go:noinline func and_uint64_0_ssa(a uint64) uint64 { return a & 0 } //go:noinline func and_0_uint64_ssa(a uint64) uint64 { return 0 & a } //go:noinline func and_uint64_1_ssa(a uint64) uint64 { return a & 1 } //go:noinline func and_1_uint64_ssa(a uint64) uint64 { return 1 & a } //go:noinline func and_uint64_4294967296_ssa(a uint64) uint64 { return a & 4294967296 } //go:noinline func and_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 & a } //go:noinline func and_uint64_9223372036854775808_ssa(a uint64) uint64 { return a & 9223372036854775808 } //go:noinline func and_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 & a } //go:noinline func and_uint64_18446744073709551615_ssa(a uint64) uint64 { return a & 18446744073709551615 } //go:noinline func and_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 & a } //go:noinline func or_uint64_0_ssa(a uint64) uint64 { return a | 0 } //go:noinline func or_0_uint64_ssa(a uint64) uint64 { return 0 | a } //go:noinline func or_uint64_1_ssa(a uint64) uint64 { return a | 1 } //go:noinline func or_1_uint64_ssa(a uint64) uint64 { return 1 | a } //go:noinline func or_uint64_4294967296_ssa(a uint64) uint64 { return a | 4294967296 } //go:noinline func or_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 | a } //go:noinline func or_uint64_9223372036854775808_ssa(a uint64) uint64 { return a | 9223372036854775808 } //go:noinline func or_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 | a } //go:noinline func or_uint64_18446744073709551615_ssa(a uint64) uint64 { return a | 18446744073709551615 } //go:noinline func or_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 | a } //go:noinline func xor_uint64_0_ssa(a uint64) uint64 { return a ^ 0 } //go:noinline func xor_0_uint64_ssa(a uint64) uint64 { return 0 ^ a } //go:noinline func xor_uint64_1_ssa(a uint64) uint64 { return a ^ 1 } //go:noinline func xor_1_uint64_ssa(a uint64) uint64 { return 1 ^ a } //go:noinline func xor_uint64_4294967296_ssa(a uint64) uint64 { return a ^ 4294967296 } //go:noinline func xor_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 ^ a } //go:noinline func xor_uint64_9223372036854775808_ssa(a uint64) uint64 { return a ^ 9223372036854775808 } //go:noinline func xor_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 ^ a } //go:noinline func xor_uint64_18446744073709551615_ssa(a uint64) uint64 { return a ^ 18446744073709551615 } //go:noinline func xor_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 ^ a } //go:noinline func add_int64_Neg9223372036854775808_ssa(a int64) int64 { return a + -9223372036854775808 } //go:noinline func add_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 + a } //go:noinline func add_int64_Neg9223372036854775807_ssa(a int64) int64 { return a + -9223372036854775807 } //go:noinline func add_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 + a } //go:noinline func add_int64_Neg4294967296_ssa(a int64) int64 { return a + -4294967296 } //go:noinline func add_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 + a } //go:noinline func add_int64_Neg1_ssa(a int64) int64 { return a + -1 } //go:noinline func add_Neg1_int64_ssa(a int64) int64 { return -1 + a } //go:noinline func add_int64_0_ssa(a int64) int64 { return a + 0 } //go:noinline func add_0_int64_ssa(a int64) int64 { return 0 + a } //go:noinline func add_int64_1_ssa(a int64) int64 { return a + 1 } //go:noinline func add_1_int64_ssa(a int64) int64 { return 1 + a } //go:noinline func add_int64_4294967296_ssa(a int64) int64 { return a + 4294967296 } //go:noinline func add_4294967296_int64_ssa(a int64) int64 { return 4294967296 + a } //go:noinline func add_int64_9223372036854775806_ssa(a int64) int64 { return a + 9223372036854775806 } //go:noinline func add_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 + a } //go:noinline func add_int64_9223372036854775807_ssa(a int64) int64 { return a + 9223372036854775807 } //go:noinline func add_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 + a } //go:noinline func sub_int64_Neg9223372036854775808_ssa(a int64) int64 { return a - -9223372036854775808 } //go:noinline func sub_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 - a } //go:noinline func sub_int64_Neg9223372036854775807_ssa(a int64) int64 { return a - -9223372036854775807 } //go:noinline func sub_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 - a } //go:noinline func sub_int64_Neg4294967296_ssa(a int64) int64 { return a - -4294967296 } //go:noinline func sub_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 - a } //go:noinline func sub_int64_Neg1_ssa(a int64) int64 { return a - -1 } //go:noinline func sub_Neg1_int64_ssa(a int64) int64 { return -1 - a } //go:noinline func sub_int64_0_ssa(a int64) int64 { return a - 0 } //go:noinline func sub_0_int64_ssa(a int64) int64 { return 0 - a } //go:noinline func sub_int64_1_ssa(a int64) int64 { return a - 1 } //go:noinline func sub_1_int64_ssa(a int64) int64 { return 1 - a } //go:noinline func sub_int64_4294967296_ssa(a int64) int64 { return a - 4294967296 } //go:noinline func sub_4294967296_int64_ssa(a int64) int64 { return 4294967296 - a } //go:noinline func sub_int64_9223372036854775806_ssa(a int64) int64 { return a - 9223372036854775806 } //go:noinline func sub_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 - a } //go:noinline func sub_int64_9223372036854775807_ssa(a int64) int64 { return a - 9223372036854775807 } //go:noinline func sub_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 - a } //go:noinline func div_int64_Neg9223372036854775808_ssa(a int64) int64 { return a / -9223372036854775808 } //go:noinline func div_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 / a } //go:noinline func div_int64_Neg9223372036854775807_ssa(a int64) int64 { return a / -9223372036854775807 } //go:noinline func div_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 / a } //go:noinline func div_int64_Neg4294967296_ssa(a int64) int64 { return a / -4294967296 } //go:noinline func div_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 / a } //go:noinline func div_int64_Neg1_ssa(a int64) int64 { return a / -1 } //go:noinline func div_Neg1_int64_ssa(a int64) int64 { return -1 / a } //go:noinline func div_0_int64_ssa(a int64) int64 { return 0 / a } //go:noinline func div_int64_1_ssa(a int64) int64 { return a / 1 } //go:noinline func div_1_int64_ssa(a int64) int64 { return 1 / a } //go:noinline func div_int64_4294967296_ssa(a int64) int64 { return a / 4294967296 } //go:noinline func div_4294967296_int64_ssa(a int64) int64 { return 4294967296 / a } //go:noinline func div_int64_9223372036854775806_ssa(a int64) int64 { return a / 9223372036854775806 } //go:noinline func div_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 / a } //go:noinline func div_int64_9223372036854775807_ssa(a int64) int64 { return a / 9223372036854775807 } //go:noinline func div_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 / a } //go:noinline func mul_int64_Neg9223372036854775808_ssa(a int64) int64 { return a * -9223372036854775808 } //go:noinline func mul_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 * a } //go:noinline func mul_int64_Neg9223372036854775807_ssa(a int64) int64 { return a * -9223372036854775807 } //go:noinline func mul_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 * a } //go:noinline func mul_int64_Neg4294967296_ssa(a int64) int64 { return a * -4294967296 } //go:noinline func mul_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 * a } //go:noinline func mul_int64_Neg1_ssa(a int64) int64 { return a * -1 } //go:noinline func mul_Neg1_int64_ssa(a int64) int64 { return -1 * a } //go:noinline func mul_int64_0_ssa(a int64) int64 { return a * 0 } //go:noinline func mul_0_int64_ssa(a int64) int64 { return 0 * a } //go:noinline func mul_int64_1_ssa(a int64) int64 { return a * 1 } //go:noinline func mul_1_int64_ssa(a int64) int64 { return 1 * a } //go:noinline func mul_int64_4294967296_ssa(a int64) int64 { return a * 4294967296 } //go:noinline func mul_4294967296_int64_ssa(a int64) int64 { return 4294967296 * a } //go:noinline func mul_int64_9223372036854775806_ssa(a int64) int64 { return a * 9223372036854775806 } //go:noinline func mul_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 * a } //go:noinline func mul_int64_9223372036854775807_ssa(a int64) int64 { return a * 9223372036854775807 } //go:noinline func mul_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 * a } //go:noinline func mod_int64_Neg9223372036854775808_ssa(a int64) int64 { return a % -9223372036854775808 } //go:noinline func mod_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 % a } //go:noinline func mod_int64_Neg9223372036854775807_ssa(a int64) int64 { return a % -9223372036854775807 } //go:noinline func mod_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 % a } //go:noinline func mod_int64_Neg4294967296_ssa(a int64) int64 { return a % -4294967296 } //go:noinline func mod_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 % a } //go:noinline func mod_int64_Neg1_ssa(a int64) int64 { return a % -1 } //go:noinline func mod_Neg1_int64_ssa(a int64) int64 { return -1 % a } //go:noinline func mod_0_int64_ssa(a int64) int64 { return 0 % a } //go:noinline func mod_int64_1_ssa(a int64) int64 { return a % 1 } //go:noinline func mod_1_int64_ssa(a int64) int64 { return 1 % a } //go:noinline func mod_int64_4294967296_ssa(a int64) int64 { return a % 4294967296 } //go:noinline func mod_4294967296_int64_ssa(a int64) int64 { return 4294967296 % a } //go:noinline func mod_int64_9223372036854775806_ssa(a int64) int64 { return a % 9223372036854775806 } //go:noinline func mod_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 % a } //go:noinline func mod_int64_9223372036854775807_ssa(a int64) int64 { return a % 9223372036854775807 } //go:noinline func mod_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 % a } //go:noinline func and_int64_Neg9223372036854775808_ssa(a int64) int64 { return a & -9223372036854775808 } //go:noinline func and_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 & a } //go:noinline func and_int64_Neg9223372036854775807_ssa(a int64) int64 { return a & -9223372036854775807 } //go:noinline func and_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 & a } //go:noinline func and_int64_Neg4294967296_ssa(a int64) int64 { return a & -4294967296 } //go:noinline func and_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 & a } //go:noinline func and_int64_Neg1_ssa(a int64) int64 { return a & -1 } //go:noinline func and_Neg1_int64_ssa(a int64) int64 { return -1 & a } //go:noinline func and_int64_0_ssa(a int64) int64 { return a & 0 } //go:noinline func and_0_int64_ssa(a int64) int64 { return 0 & a } //go:noinline func and_int64_1_ssa(a int64) int64 { return a & 1 } //go:noinline func and_1_int64_ssa(a int64) int64 { return 1 & a } //go:noinline func and_int64_4294967296_ssa(a int64) int64 { return a & 4294967296 } //go:noinline func and_4294967296_int64_ssa(a int64) int64 { return 4294967296 & a } //go:noinline func and_int64_9223372036854775806_ssa(a int64) int64 { return a & 9223372036854775806 } //go:noinline func and_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 & a } //go:noinline func and_int64_9223372036854775807_ssa(a int64) int64 { return a & 9223372036854775807 } //go:noinline func and_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 & a } //go:noinline func or_int64_Neg9223372036854775808_ssa(a int64) int64 { return a | -9223372036854775808 } //go:noinline func or_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 | a } //go:noinline func or_int64_Neg9223372036854775807_ssa(a int64) int64 { return a | -9223372036854775807 } //go:noinline func or_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 | a } //go:noinline func or_int64_Neg4294967296_ssa(a int64) int64 { return a | -4294967296 } //go:noinline func or_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 | a } //go:noinline func or_int64_Neg1_ssa(a int64) int64 { return a | -1 } //go:noinline func or_Neg1_int64_ssa(a int64) int64 { return -1 | a } //go:noinline func or_int64_0_ssa(a int64) int64 { return a | 0 } //go:noinline func or_0_int64_ssa(a int64) int64 { return 0 | a } //go:noinline func or_int64_1_ssa(a int64) int64 { return a | 1 } //go:noinline func or_1_int64_ssa(a int64) int64 { return 1 | a } //go:noinline func or_int64_4294967296_ssa(a int64) int64 { return a | 4294967296 } //go:noinline func or_4294967296_int64_ssa(a int64) int64 { return 4294967296 | a } //go:noinline func or_int64_9223372036854775806_ssa(a int64) int64 { return a | 9223372036854775806 } //go:noinline func or_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 | a } //go:noinline func or_int64_9223372036854775807_ssa(a int64) int64 { return a | 9223372036854775807 } //go:noinline func or_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 | a } //go:noinline func xor_int64_Neg9223372036854775808_ssa(a int64) int64 { return a ^ -9223372036854775808 } //go:noinline func xor_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 ^ a } //go:noinline func xor_int64_Neg9223372036854775807_ssa(a int64) int64 { return a ^ -9223372036854775807 } //go:noinline func xor_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 ^ a } //go:noinline func xor_int64_Neg4294967296_ssa(a int64) int64 { return a ^ -4294967296 } //go:noinline func xor_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 ^ a } //go:noinline func xor_int64_Neg1_ssa(a int64) int64 { return a ^ -1 } //go:noinline func xor_Neg1_int64_ssa(a int64) int64 { return -1 ^ a } //go:noinline func xor_int64_0_ssa(a int64) int64 { return a ^ 0 } //go:noinline func xor_0_int64_ssa(a int64) int64 { return 0 ^ a } //go:noinline func xor_int64_1_ssa(a int64) int64 { return a ^ 1 } //go:noinline func xor_1_int64_ssa(a int64) int64 { return 1 ^ a } //go:noinline func xor_int64_4294967296_ssa(a int64) int64 { return a ^ 4294967296 } //go:noinline func xor_4294967296_int64_ssa(a int64) int64 { return 4294967296 ^ a } //go:noinline func xor_int64_9223372036854775806_ssa(a int64) int64 { return a ^ 9223372036854775806 } //go:noinline func xor_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 ^ a } //go:noinline func xor_int64_9223372036854775807_ssa(a int64) int64 { return a ^ 9223372036854775807 } //go:noinline func xor_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 ^ a } //go:noinline func add_uint32_0_ssa(a uint32) uint32 { return a + 0 } //go:noinline func add_0_uint32_ssa(a uint32) uint32 { return 0 + a } //go:noinline func add_uint32_1_ssa(a uint32) uint32 { return a + 1 } //go:noinline func add_1_uint32_ssa(a uint32) uint32 { return 1 + a } //go:noinline func add_uint32_4294967295_ssa(a uint32) uint32 { return a + 4294967295 } //go:noinline func add_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 + a } //go:noinline func sub_uint32_0_ssa(a uint32) uint32 { return a - 0 } //go:noinline func sub_0_uint32_ssa(a uint32) uint32 { return 0 - a } //go:noinline func sub_uint32_1_ssa(a uint32) uint32 { return a - 1 } //go:noinline func sub_1_uint32_ssa(a uint32) uint32 { return 1 - a } //go:noinline func sub_uint32_4294967295_ssa(a uint32) uint32 { return a - 4294967295 } //go:noinline func sub_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 - a } //go:noinline func div_0_uint32_ssa(a uint32) uint32 { return 0 / a } //go:noinline func div_uint32_1_ssa(a uint32) uint32 { return a / 1 } //go:noinline func div_1_uint32_ssa(a uint32) uint32 { return 1 / a } //go:noinline func div_uint32_4294967295_ssa(a uint32) uint32 { return a / 4294967295 } //go:noinline func div_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 / a } //go:noinline func mul_uint32_0_ssa(a uint32) uint32 { return a * 0 } //go:noinline func mul_0_uint32_ssa(a uint32) uint32 { return 0 * a } //go:noinline func mul_uint32_1_ssa(a uint32) uint32 { return a * 1 } //go:noinline func mul_1_uint32_ssa(a uint32) uint32 { return 1 * a } //go:noinline func mul_uint32_4294967295_ssa(a uint32) uint32 { return a * 4294967295 } //go:noinline func mul_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 * a } //go:noinline func lsh_uint32_0_ssa(a uint32) uint32 { return a << 0 } //go:noinline func lsh_0_uint32_ssa(a uint32) uint32 { return 0 << a } //go:noinline func lsh_uint32_1_ssa(a uint32) uint32 { return a << 1 } //go:noinline func lsh_1_uint32_ssa(a uint32) uint32 { return 1 << a } //go:noinline func lsh_uint32_4294967295_ssa(a uint32) uint32 { return a << 4294967295 } //go:noinline func lsh_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 << a } //go:noinline func rsh_uint32_0_ssa(a uint32) uint32 { return a >> 0 } //go:noinline func rsh_0_uint32_ssa(a uint32) uint32 { return 0 >> a } //go:noinline func rsh_uint32_1_ssa(a uint32) uint32 { return a >> 1 } //go:noinline func rsh_1_uint32_ssa(a uint32) uint32 { return 1 >> a } //go:noinline func rsh_uint32_4294967295_ssa(a uint32) uint32 { return a >> 4294967295 } //go:noinline func rsh_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 >> a } //go:noinline func mod_0_uint32_ssa(a uint32) uint32 { return 0 % a } //go:noinline func mod_uint32_1_ssa(a uint32) uint32 { return a % 1 } //go:noinline func mod_1_uint32_ssa(a uint32) uint32 { return 1 % a } //go:noinline func mod_uint32_4294967295_ssa(a uint32) uint32 { return a % 4294967295 } //go:noinline func mod_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 % a } //go:noinline func and_uint32_0_ssa(a uint32) uint32 { return a & 0 } //go:noinline func and_0_uint32_ssa(a uint32) uint32 { return 0 & a } //go:noinline func and_uint32_1_ssa(a uint32) uint32 { return a & 1 } //go:noinline func and_1_uint32_ssa(a uint32) uint32 { return 1 & a } //go:noinline func and_uint32_4294967295_ssa(a uint32) uint32 { return a & 4294967295 } //go:noinline func and_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 & a } //go:noinline func or_uint32_0_ssa(a uint32) uint32 { return a | 0 } //go:noinline func or_0_uint32_ssa(a uint32) uint32 { return 0 | a } //go:noinline func or_uint32_1_ssa(a uint32) uint32 { return a | 1 } //go:noinline func or_1_uint32_ssa(a uint32) uint32 { return 1 | a } //go:noinline func or_uint32_4294967295_ssa(a uint32) uint32 { return a | 4294967295 } //go:noinline func or_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 | a } //go:noinline func xor_uint32_0_ssa(a uint32) uint32 { return a ^ 0 } //go:noinline func xor_0_uint32_ssa(a uint32) uint32 { return 0 ^ a } //go:noinline func xor_uint32_1_ssa(a uint32) uint32 { return a ^ 1 } //go:noinline func xor_1_uint32_ssa(a uint32) uint32 { return 1 ^ a } //go:noinline func xor_uint32_4294967295_ssa(a uint32) uint32 { return a ^ 4294967295 } //go:noinline func xor_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 ^ a } //go:noinline func add_int32_Neg2147483648_ssa(a int32) int32 { return a + -2147483648 } //go:noinline func add_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 + a } //go:noinline func add_int32_Neg2147483647_ssa(a int32) int32 { return a + -2147483647 } //go:noinline func add_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 + a } //go:noinline func add_int32_Neg1_ssa(a int32) int32 { return a + -1 } //go:noinline func add_Neg1_int32_ssa(a int32) int32 { return -1 + a } //go:noinline func add_int32_0_ssa(a int32) int32 { return a + 0 } //go:noinline func add_0_int32_ssa(a int32) int32 { return 0 + a } //go:noinline func add_int32_1_ssa(a int32) int32 { return a + 1 } //go:noinline func add_1_int32_ssa(a int32) int32 { return 1 + a } //go:noinline func add_int32_2147483647_ssa(a int32) int32 { return a + 2147483647 } //go:noinline func add_2147483647_int32_ssa(a int32) int32 { return 2147483647 + a } //go:noinline func sub_int32_Neg2147483648_ssa(a int32) int32 { return a - -2147483648 } //go:noinline func sub_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 - a } //go:noinline func sub_int32_Neg2147483647_ssa(a int32) int32 { return a - -2147483647 } //go:noinline func sub_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 - a } //go:noinline func sub_int32_Neg1_ssa(a int32) int32 { return a - -1 } //go:noinline func sub_Neg1_int32_ssa(a int32) int32 { return -1 - a } //go:noinline func sub_int32_0_ssa(a int32) int32 { return a - 0 } //go:noinline func sub_0_int32_ssa(a int32) int32 { return 0 - a } //go:noinline func sub_int32_1_ssa(a int32) int32 { return a - 1 } //go:noinline func sub_1_int32_ssa(a int32) int32 { return 1 - a } //go:noinline func sub_int32_2147483647_ssa(a int32) int32 { return a - 2147483647 } //go:noinline func sub_2147483647_int32_ssa(a int32) int32 { return 2147483647 - a } //go:noinline func div_int32_Neg2147483648_ssa(a int32) int32 { return a / -2147483648 } //go:noinline func div_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 / a } //go:noinline func div_int32_Neg2147483647_ssa(a int32) int32 { return a / -2147483647 } //go:noinline func div_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 / a } //go:noinline func div_int32_Neg1_ssa(a int32) int32 { return a / -1 } //go:noinline func div_Neg1_int32_ssa(a int32) int32 { return -1 / a } //go:noinline func div_0_int32_ssa(a int32) int32 { return 0 / a } //go:noinline func div_int32_1_ssa(a int32) int32 { return a / 1 } //go:noinline func div_1_int32_ssa(a int32) int32 { return 1 / a } //go:noinline func div_int32_2147483647_ssa(a int32) int32 { return a / 2147483647 } //go:noinline func div_2147483647_int32_ssa(a int32) int32 { return 2147483647 / a } //go:noinline func mul_int32_Neg2147483648_ssa(a int32) int32 { return a * -2147483648 } //go:noinline func mul_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 * a } //go:noinline func mul_int32_Neg2147483647_ssa(a int32) int32 { return a * -2147483647 } //go:noinline func mul_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 * a } //go:noinline func mul_int32_Neg1_ssa(a int32) int32 { return a * -1 } //go:noinline func mul_Neg1_int32_ssa(a int32) int32 { return -1 * a } //go:noinline func mul_int32_0_ssa(a int32) int32 { return a * 0 } //go:noinline func mul_0_int32_ssa(a int32) int32 { return 0 * a } //go:noinline func mul_int32_1_ssa(a int32) int32 { return a * 1 } //go:noinline func mul_1_int32_ssa(a int32) int32 { return 1 * a } //go:noinline func mul_int32_2147483647_ssa(a int32) int32 { return a * 2147483647 } //go:noinline func mul_2147483647_int32_ssa(a int32) int32 { return 2147483647 * a } //go:noinline func mod_int32_Neg2147483648_ssa(a int32) int32 { return a % -2147483648 } //go:noinline func mod_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 % a } //go:noinline func mod_int32_Neg2147483647_ssa(a int32) int32 { return a % -2147483647 } //go:noinline func mod_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 % a } //go:noinline func mod_int32_Neg1_ssa(a int32) int32 { return a % -1 } //go:noinline func mod_Neg1_int32_ssa(a int32) int32 { return -1 % a } //go:noinline func mod_0_int32_ssa(a int32) int32 { return 0 % a } //go:noinline func mod_int32_1_ssa(a int32) int32 { return a % 1 } //go:noinline func mod_1_int32_ssa(a int32) int32 { return 1 % a } //go:noinline func mod_int32_2147483647_ssa(a int32) int32 { return a % 2147483647 } //go:noinline func mod_2147483647_int32_ssa(a int32) int32 { return 2147483647 % a } //go:noinline func and_int32_Neg2147483648_ssa(a int32) int32 { return a & -2147483648 } //go:noinline func and_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 & a } //go:noinline func and_int32_Neg2147483647_ssa(a int32) int32 { return a & -2147483647 } //go:noinline func and_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 & a } //go:noinline func and_int32_Neg1_ssa(a int32) int32 { return a & -1 } //go:noinline func and_Neg1_int32_ssa(a int32) int32 { return -1 & a } //go:noinline func and_int32_0_ssa(a int32) int32 { return a & 0 } //go:noinline func and_0_int32_ssa(a int32) int32 { return 0 & a } //go:noinline func and_int32_1_ssa(a int32) int32 { return a & 1 } //go:noinline func and_1_int32_ssa(a int32) int32 { return 1 & a } //go:noinline func and_int32_2147483647_ssa(a int32) int32 { return a & 2147483647 } //go:noinline func and_2147483647_int32_ssa(a int32) int32 { return 2147483647 & a } //go:noinline func or_int32_Neg2147483648_ssa(a int32) int32 { return a | -2147483648 } //go:noinline func or_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 | a } //go:noinline func or_int32_Neg2147483647_ssa(a int32) int32 { return a | -2147483647 } //go:noinline func or_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 | a } //go:noinline func or_int32_Neg1_ssa(a int32) int32 { return a | -1 } //go:noinline func or_Neg1_int32_ssa(a int32) int32 { return -1 | a } //go:noinline func or_int32_0_ssa(a int32) int32 { return a | 0 } //go:noinline func or_0_int32_ssa(a int32) int32 { return 0 | a } //go:noinline func or_int32_1_ssa(a int32) int32 { return a | 1 } //go:noinline func or_1_int32_ssa(a int32) int32 { return 1 | a } //go:noinline func or_int32_2147483647_ssa(a int32) int32 { return a | 2147483647 } //go:noinline func or_2147483647_int32_ssa(a int32) int32 { return 2147483647 | a } //go:noinline func xor_int32_Neg2147483648_ssa(a int32) int32 { return a ^ -2147483648 } //go:noinline func xor_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 ^ a } //go:noinline func xor_int32_Neg2147483647_ssa(a int32) int32 { return a ^ -2147483647 } //go:noinline func xor_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 ^ a } //go:noinline func xor_int32_Neg1_ssa(a int32) int32 { return a ^ -1 } //go:noinline func xor_Neg1_int32_ssa(a int32) int32 { return -1 ^ a } //go:noinline func xor_int32_0_ssa(a int32) int32 { return a ^ 0 } //go:noinline func xor_0_int32_ssa(a int32) int32 { return 0 ^ a } //go:noinline func xor_int32_1_ssa(a int32) int32 { return a ^ 1 } //go:noinline func xor_1_int32_ssa(a int32) int32 { return 1 ^ a } //go:noinline func xor_int32_2147483647_ssa(a int32) int32 { return a ^ 2147483647 } //go:noinline func xor_2147483647_int32_ssa(a int32) int32 { return 2147483647 ^ a } //go:noinline func add_uint16_0_ssa(a uint16) uint16 { return a + 0 } //go:noinline func add_0_uint16_ssa(a uint16) uint16 { return 0 + a } //go:noinline func add_uint16_1_ssa(a uint16) uint16 { return a + 1 } //go:noinline func add_1_uint16_ssa(a uint16) uint16 { return 1 + a } //go:noinline func add_uint16_65535_ssa(a uint16) uint16 { return a + 65535 } //go:noinline func add_65535_uint16_ssa(a uint16) uint16 { return 65535 + a } //go:noinline func sub_uint16_0_ssa(a uint16) uint16 { return a - 0 } //go:noinline func sub_0_uint16_ssa(a uint16) uint16 { return 0 - a } //go:noinline func sub_uint16_1_ssa(a uint16) uint16 { return a - 1 } //go:noinline func sub_1_uint16_ssa(a uint16) uint16 { return 1 - a } //go:noinline func sub_uint16_65535_ssa(a uint16) uint16 { return a - 65535 } //go:noinline func sub_65535_uint16_ssa(a uint16) uint16 { return 65535 - a } //go:noinline func div_0_uint16_ssa(a uint16) uint16 { return 0 / a } //go:noinline func div_uint16_1_ssa(a uint16) uint16 { return a / 1 } //go:noinline func div_1_uint16_ssa(a uint16) uint16 { return 1 / a } //go:noinline func div_uint16_65535_ssa(a uint16) uint16 { return a / 65535 } //go:noinline func div_65535_uint16_ssa(a uint16) uint16 { return 65535 / a } //go:noinline func mul_uint16_0_ssa(a uint16) uint16 { return a * 0 } //go:noinline func mul_0_uint16_ssa(a uint16) uint16 { return 0 * a } //go:noinline func mul_uint16_1_ssa(a uint16) uint16 { return a * 1 } //go:noinline func mul_1_uint16_ssa(a uint16) uint16 { return 1 * a } //go:noinline func mul_uint16_65535_ssa(a uint16) uint16 { return a * 65535 } //go:noinline func mul_65535_uint16_ssa(a uint16) uint16 { return 65535 * a } //go:noinline func lsh_uint16_0_ssa(a uint16) uint16 { return a << 0 } //go:noinline func lsh_0_uint16_ssa(a uint16) uint16 { return 0 << a } //go:noinline func lsh_uint16_1_ssa(a uint16) uint16 { return a << 1 } //go:noinline func lsh_1_uint16_ssa(a uint16) uint16 { return 1 << a } //go:noinline func lsh_uint16_65535_ssa(a uint16) uint16 { return a << 65535 } //go:noinline func lsh_65535_uint16_ssa(a uint16) uint16 { return 65535 << a } //go:noinline func rsh_uint16_0_ssa(a uint16) uint16 { return a >> 0 } //go:noinline func rsh_0_uint16_ssa(a uint16) uint16 { return 0 >> a } //go:noinline func rsh_uint16_1_ssa(a uint16) uint16 { return a >> 1 } //go:noinline func rsh_1_uint16_ssa(a uint16) uint16 { return 1 >> a } //go:noinline func rsh_uint16_65535_ssa(a uint16) uint16 { return a >> 65535 } //go:noinline func rsh_65535_uint16_ssa(a uint16) uint16 { return 65535 >> a } //go:noinline func mod_0_uint16_ssa(a uint16) uint16 { return 0 % a } //go:noinline func mod_uint16_1_ssa(a uint16) uint16 { return a % 1 } //go:noinline func mod_1_uint16_ssa(a uint16) uint16 { return 1 % a } //go:noinline func mod_uint16_65535_ssa(a uint16) uint16 { return a % 65535 } //go:noinline func mod_65535_uint16_ssa(a uint16) uint16 { return 65535 % a } //go:noinline func and_uint16_0_ssa(a uint16) uint16 { return a & 0 } //go:noinline func and_0_uint16_ssa(a uint16) uint16 { return 0 & a } //go:noinline func and_uint16_1_ssa(a uint16) uint16 { return a & 1 } //go:noinline func and_1_uint16_ssa(a uint16) uint16 { return 1 & a } //go:noinline func and_uint16_65535_ssa(a uint16) uint16 { return a & 65535 } //go:noinline func and_65535_uint16_ssa(a uint16) uint16 { return 65535 & a } //go:noinline func or_uint16_0_ssa(a uint16) uint16 { return a | 0 } //go:noinline func or_0_uint16_ssa(a uint16) uint16 { return 0 | a } //go:noinline func or_uint16_1_ssa(a uint16) uint16 { return a | 1 } //go:noinline func or_1_uint16_ssa(a uint16) uint16 { return 1 | a } //go:noinline func or_uint16_65535_ssa(a uint16) uint16 { return a | 65535 } //go:noinline func or_65535_uint16_ssa(a uint16) uint16 { return 65535 | a } //go:noinline func xor_uint16_0_ssa(a uint16) uint16 { return a ^ 0 } //go:noinline func xor_0_uint16_ssa(a uint16) uint16 { return 0 ^ a } //go:noinline func xor_uint16_1_ssa(a uint16) uint16 { return a ^ 1 } //go:noinline func xor_1_uint16_ssa(a uint16) uint16 { return 1 ^ a } //go:noinline func xor_uint16_65535_ssa(a uint16) uint16 { return a ^ 65535 } //go:noinline func xor_65535_uint16_ssa(a uint16) uint16 { return 65535 ^ a } //go:noinline func add_int16_Neg32768_ssa(a int16) int16 { return a + -32768 } //go:noinline func add_Neg32768_int16_ssa(a int16) int16 { return -32768 + a } //go:noinline func add_int16_Neg32767_ssa(a int16) int16 { return a + -32767 } //go:noinline func add_Neg32767_int16_ssa(a int16) int16 { return -32767 + a } //go:noinline func add_int16_Neg1_ssa(a int16) int16 { return a + -1 } //go:noinline func add_Neg1_int16_ssa(a int16) int16 { return -1 + a } //go:noinline func add_int16_0_ssa(a int16) int16 { return a + 0 } //go:noinline func add_0_int16_ssa(a int16) int16 { return 0 + a } //go:noinline func add_int16_1_ssa(a int16) int16 { return a + 1 } //go:noinline func add_1_int16_ssa(a int16) int16 { return 1 + a } //go:noinline func add_int16_32766_ssa(a int16) int16 { return a + 32766 } //go:noinline func add_32766_int16_ssa(a int16) int16 { return 32766 + a } //go:noinline func add_int16_32767_ssa(a int16) int16 { return a + 32767 } //go:noinline func add_32767_int16_ssa(a int16) int16 { return 32767 + a } //go:noinline func sub_int16_Neg32768_ssa(a int16) int16 { return a - -32768 } //go:noinline func sub_Neg32768_int16_ssa(a int16) int16 { return -32768 - a } //go:noinline func sub_int16_Neg32767_ssa(a int16) int16 { return a - -32767 } //go:noinline func sub_Neg32767_int16_ssa(a int16) int16 { return -32767 - a } //go:noinline func sub_int16_Neg1_ssa(a int16) int16 { return a - -1 } //go:noinline func sub_Neg1_int16_ssa(a int16) int16 { return -1 - a } //go:noinline func sub_int16_0_ssa(a int16) int16 { return a - 0 } //go:noinline func sub_0_int16_ssa(a int16) int16 { return 0 - a } //go:noinline func sub_int16_1_ssa(a int16) int16 { return a - 1 } //go:noinline func sub_1_int16_ssa(a int16) int16 { return 1 - a } //go:noinline func sub_int16_32766_ssa(a int16) int16 { return a - 32766 } //go:noinline func sub_32766_int16_ssa(a int16) int16 { return 32766 - a } //go:noinline func sub_int16_32767_ssa(a int16) int16 { return a - 32767 } //go:noinline func sub_32767_int16_ssa(a int16) int16 { return 32767 - a } //go:noinline func div_int16_Neg32768_ssa(a int16) int16 { return a / -32768 } //go:noinline func div_Neg32768_int16_ssa(a int16) int16 { return -32768 / a } //go:noinline func div_int16_Neg32767_ssa(a int16) int16 { return a / -32767 } //go:noinline func div_Neg32767_int16_ssa(a int16) int16 { return -32767 / a } //go:noinline func div_int16_Neg1_ssa(a int16) int16 { return a / -1 } //go:noinline func div_Neg1_int16_ssa(a int16) int16 { return -1 / a } //go:noinline func div_0_int16_ssa(a int16) int16 { return 0 / a } //go:noinline func div_int16_1_ssa(a int16) int16 { return a / 1 } //go:noinline func div_1_int16_ssa(a int16) int16 { return 1 / a } //go:noinline func div_int16_32766_ssa(a int16) int16 { return a / 32766 } //go:noinline func div_32766_int16_ssa(a int16) int16 { return 32766 / a } //go:noinline func div_int16_32767_ssa(a int16) int16 { return a / 32767 } //go:noinline func div_32767_int16_ssa(a int16) int16 { return 32767 / a } //go:noinline func mul_int16_Neg32768_ssa(a int16) int16 { return a * -32768 } //go:noinline func mul_Neg32768_int16_ssa(a int16) int16 { return -32768 * a } //go:noinline func mul_int16_Neg32767_ssa(a int16) int16 { return a * -32767 } //go:noinline func mul_Neg32767_int16_ssa(a int16) int16 { return -32767 * a } //go:noinline func mul_int16_Neg1_ssa(a int16) int16 { return a * -1 } //go:noinline func mul_Neg1_int16_ssa(a int16) int16 { return -1 * a } //go:noinline func mul_int16_0_ssa(a int16) int16 { return a * 0 } //go:noinline func mul_0_int16_ssa(a int16) int16 { return 0 * a } //go:noinline func mul_int16_1_ssa(a int16) int16 { return a * 1 } //go:noinline func mul_1_int16_ssa(a int16) int16 { return 1 * a } //go:noinline func mul_int16_32766_ssa(a int16) int16 { return a * 32766 } //go:noinline func mul_32766_int16_ssa(a int16) int16 { return 32766 * a } //go:noinline func mul_int16_32767_ssa(a int16) int16 { return a * 32767 } //go:noinline func mul_32767_int16_ssa(a int16) int16 { return 32767 * a } //go:noinline func mod_int16_Neg32768_ssa(a int16) int16 { return a % -32768 } //go:noinline func mod_Neg32768_int16_ssa(a int16) int16 { return -32768 % a } //go:noinline func mod_int16_Neg32767_ssa(a int16) int16 { return a % -32767 } //go:noinline func mod_Neg32767_int16_ssa(a int16) int16 { return -32767 % a } //go:noinline func mod_int16_Neg1_ssa(a int16) int16 { return a % -1 } //go:noinline func mod_Neg1_int16_ssa(a int16) int16 { return -1 % a } //go:noinline func mod_0_int16_ssa(a int16) int16 { return 0 % a } //go:noinline func mod_int16_1_ssa(a int16) int16 { return a % 1 } //go:noinline func mod_1_int16_ssa(a int16) int16 { return 1 % a } //go:noinline func mod_int16_32766_ssa(a int16) int16 { return a % 32766 } //go:noinline func mod_32766_int16_ssa(a int16) int16 { return 32766 % a } //go:noinline func mod_int16_32767_ssa(a int16) int16 { return a % 32767 } //go:noinline func mod_32767_int16_ssa(a int16) int16 { return 32767 % a } //go:noinline func and_int16_Neg32768_ssa(a int16) int16 { return a & -32768 } //go:noinline func and_Neg32768_int16_ssa(a int16) int16 { return -32768 & a } //go:noinline func and_int16_Neg32767_ssa(a int16) int16 { return a & -32767 } //go:noinline func and_Neg32767_int16_ssa(a int16) int16 { return -32767 & a } //go:noinline func and_int16_Neg1_ssa(a int16) int16 { return a & -1 } //go:noinline func and_Neg1_int16_ssa(a int16) int16 { return -1 & a } //go:noinline func and_int16_0_ssa(a int16) int16 { return a & 0 } //go:noinline func and_0_int16_ssa(a int16) int16 { return 0 & a } //go:noinline func and_int16_1_ssa(a int16) int16 { return a & 1 } //go:noinline func and_1_int16_ssa(a int16) int16 { return 1 & a } //go:noinline func and_int16_32766_ssa(a int16) int16 { return a & 32766 } //go:noinline func and_32766_int16_ssa(a int16) int16 { return 32766 & a } //go:noinline func and_int16_32767_ssa(a int16) int16 { return a & 32767 } //go:noinline func and_32767_int16_ssa(a int16) int16 { return 32767 & a } //go:noinline func or_int16_Neg32768_ssa(a int16) int16 { return a | -32768 } //go:noinline func or_Neg32768_int16_ssa(a int16) int16 { return -32768 | a } //go:noinline func or_int16_Neg32767_ssa(a int16) int16 { return a | -32767 } //go:noinline func or_Neg32767_int16_ssa(a int16) int16 { return -32767 | a } //go:noinline func or_int16_Neg1_ssa(a int16) int16 { return a | -1 } //go:noinline func or_Neg1_int16_ssa(a int16) int16 { return -1 | a } //go:noinline func or_int16_0_ssa(a int16) int16 { return a | 0 } //go:noinline func or_0_int16_ssa(a int16) int16 { return 0 | a } //go:noinline func or_int16_1_ssa(a int16) int16 { return a | 1 } //go:noinline func or_1_int16_ssa(a int16) int16 { return 1 | a } //go:noinline func or_int16_32766_ssa(a int16) int16 { return a | 32766 } //go:noinline func or_32766_int16_ssa(a int16) int16 { return 32766 | a } //go:noinline func or_int16_32767_ssa(a int16) int16 { return a | 32767 } //go:noinline func or_32767_int16_ssa(a int16) int16 { return 32767 | a } //go:noinline func xor_int16_Neg32768_ssa(a int16) int16 { return a ^ -32768 } //go:noinline func xor_Neg32768_int16_ssa(a int16) int16 { return -32768 ^ a } //go:noinline func xor_int16_Neg32767_ssa(a int16) int16 { return a ^ -32767 } //go:noinline func xor_Neg32767_int16_ssa(a int16) int16 { return -32767 ^ a } //go:noinline func xor_int16_Neg1_ssa(a int16) int16 { return a ^ -1 } //go:noinline func xor_Neg1_int16_ssa(a int16) int16 { return -1 ^ a } //go:noinline func xor_int16_0_ssa(a int16) int16 { return a ^ 0 } //go:noinline func xor_0_int16_ssa(a int16) int16 { return 0 ^ a } //go:noinline func xor_int16_1_ssa(a int16) int16 { return a ^ 1 } //go:noinline func xor_1_int16_ssa(a int16) int16 { return 1 ^ a } //go:noinline func xor_int16_32766_ssa(a int16) int16 { return a ^ 32766 } //go:noinline func xor_32766_int16_ssa(a int16) int16 { return 32766 ^ a } //go:noinline func xor_int16_32767_ssa(a int16) int16 { return a ^ 32767 } //go:noinline func xor_32767_int16_ssa(a int16) int16 { return 32767 ^ a } //go:noinline func add_uint8_0_ssa(a uint8) uint8 { return a + 0 } //go:noinline func add_0_uint8_ssa(a uint8) uint8 { return 0 + a } //go:noinline func add_uint8_1_ssa(a uint8) uint8 { return a + 1 } //go:noinline func add_1_uint8_ssa(a uint8) uint8 { return 1 + a } //go:noinline func add_uint8_255_ssa(a uint8) uint8 { return a + 255 } //go:noinline func add_255_uint8_ssa(a uint8) uint8 { return 255 + a } //go:noinline func sub_uint8_0_ssa(a uint8) uint8 { return a - 0 } //go:noinline func sub_0_uint8_ssa(a uint8) uint8 { return 0 - a } //go:noinline func sub_uint8_1_ssa(a uint8) uint8 { return a - 1 } //go:noinline func sub_1_uint8_ssa(a uint8) uint8 { return 1 - a } //go:noinline func sub_uint8_255_ssa(a uint8) uint8 { return a - 255 } //go:noinline func sub_255_uint8_ssa(a uint8) uint8 { return 255 - a } //go:noinline func div_0_uint8_ssa(a uint8) uint8 { return 0 / a } //go:noinline func div_uint8_1_ssa(a uint8) uint8 { return a / 1 } //go:noinline func div_1_uint8_ssa(a uint8) uint8 { return 1 / a } //go:noinline func div_uint8_255_ssa(a uint8) uint8 { return a / 255 } //go:noinline func div_255_uint8_ssa(a uint8) uint8 { return 255 / a } //go:noinline func mul_uint8_0_ssa(a uint8) uint8 { return a * 0 } //go:noinline func mul_0_uint8_ssa(a uint8) uint8 { return 0 * a } //go:noinline func mul_uint8_1_ssa(a uint8) uint8 { return a * 1 } //go:noinline func mul_1_uint8_ssa(a uint8) uint8 { return 1 * a } //go:noinline func mul_uint8_255_ssa(a uint8) uint8 { return a * 255 } //go:noinline func mul_255_uint8_ssa(a uint8) uint8 { return 255 * a } //go:noinline func lsh_uint8_0_ssa(a uint8) uint8 { return a << 0 } //go:noinline func lsh_0_uint8_ssa(a uint8) uint8 { return 0 << a } //go:noinline func lsh_uint8_1_ssa(a uint8) uint8 { return a << 1 } //go:noinline func lsh_1_uint8_ssa(a uint8) uint8 { return 1 << a } //go:noinline func lsh_uint8_255_ssa(a uint8) uint8 { return a << 255 } //go:noinline func lsh_255_uint8_ssa(a uint8) uint8 { return 255 << a } //go:noinline func rsh_uint8_0_ssa(a uint8) uint8 { return a >> 0 } //go:noinline func rsh_0_uint8_ssa(a uint8) uint8 { return 0 >> a } //go:noinline func rsh_uint8_1_ssa(a uint8) uint8 { return a >> 1 } //go:noinline func rsh_1_uint8_ssa(a uint8) uint8 { return 1 >> a } //go:noinline func rsh_uint8_255_ssa(a uint8) uint8 { return a >> 255 } //go:noinline func rsh_255_uint8_ssa(a uint8) uint8 { return 255 >> a } //go:noinline func mod_0_uint8_ssa(a uint8) uint8 { return 0 % a } //go:noinline func mod_uint8_1_ssa(a uint8) uint8 { return a % 1 } //go:noinline func mod_1_uint8_ssa(a uint8) uint8 { return 1 % a } //go:noinline func mod_uint8_255_ssa(a uint8) uint8 { return a % 255 } //go:noinline func mod_255_uint8_ssa(a uint8) uint8 { return 255 % a } //go:noinline func and_uint8_0_ssa(a uint8) uint8 { return a & 0 } //go:noinline func and_0_uint8_ssa(a uint8) uint8 { return 0 & a } //go:noinline func and_uint8_1_ssa(a uint8) uint8 { return a & 1 } //go:noinline func and_1_uint8_ssa(a uint8) uint8 { return 1 & a } //go:noinline func and_uint8_255_ssa(a uint8) uint8 { return a & 255 } //go:noinline func and_255_uint8_ssa(a uint8) uint8 { return 255 & a } //go:noinline func or_uint8_0_ssa(a uint8) uint8 { return a | 0 } //go:noinline func or_0_uint8_ssa(a uint8) uint8 { return 0 | a } //go:noinline func or_uint8_1_ssa(a uint8) uint8 { return a | 1 } //go:noinline func or_1_uint8_ssa(a uint8) uint8 { return 1 | a } //go:noinline func or_uint8_255_ssa(a uint8) uint8 { return a | 255 } //go:noinline func or_255_uint8_ssa(a uint8) uint8 { return 255 | a } //go:noinline func xor_uint8_0_ssa(a uint8) uint8 { return a ^ 0 } //go:noinline func xor_0_uint8_ssa(a uint8) uint8 { return 0 ^ a } //go:noinline func xor_uint8_1_ssa(a uint8) uint8 { return a ^ 1 } //go:noinline func xor_1_uint8_ssa(a uint8) uint8 { return 1 ^ a } //go:noinline func xor_uint8_255_ssa(a uint8) uint8 { return a ^ 255 } //go:noinline func xor_255_uint8_ssa(a uint8) uint8 { return 255 ^ a } //go:noinline func add_int8_Neg128_ssa(a int8) int8 { return a + -128 } //go:noinline func add_Neg128_int8_ssa(a int8) int8 { return -128 + a } //go:noinline func add_int8_Neg127_ssa(a int8) int8 { return a + -127 } //go:noinline func add_Neg127_int8_ssa(a int8) int8 { return -127 + a } //go:noinline func add_int8_Neg1_ssa(a int8) int8 { return a + -1 } //go:noinline func add_Neg1_int8_ssa(a int8) int8 { return -1 + a } //go:noinline func add_int8_0_ssa(a int8) int8 { return a + 0 } //go:noinline func add_0_int8_ssa(a int8) int8 { return 0 + a } //go:noinline func add_int8_1_ssa(a int8) int8 { return a + 1 } //go:noinline func add_1_int8_ssa(a int8) int8 { return 1 + a } //go:noinline func add_int8_126_ssa(a int8) int8 { return a + 126 } //go:noinline func add_126_int8_ssa(a int8) int8 { return 126 + a } //go:noinline func add_int8_127_ssa(a int8) int8 { return a + 127 } //go:noinline func add_127_int8_ssa(a int8) int8 { return 127 + a } //go:noinline func sub_int8_Neg128_ssa(a int8) int8 { return a - -128 } //go:noinline func sub_Neg128_int8_ssa(a int8) int8 { return -128 - a } //go:noinline func sub_int8_Neg127_ssa(a int8) int8 { return a - -127 } //go:noinline func sub_Neg127_int8_ssa(a int8) int8 { return -127 - a } //go:noinline func sub_int8_Neg1_ssa(a int8) int8 { return a - -1 } //go:noinline func sub_Neg1_int8_ssa(a int8) int8 { return -1 - a } //go:noinline func sub_int8_0_ssa(a int8) int8 { return a - 0 } //go:noinline func sub_0_int8_ssa(a int8) int8 { return 0 - a } //go:noinline func sub_int8_1_ssa(a int8) int8 { return a - 1 } //go:noinline func sub_1_int8_ssa(a int8) int8 { return 1 - a } //go:noinline func sub_int8_126_ssa(a int8) int8 { return a - 126 } //go:noinline func sub_126_int8_ssa(a int8) int8 { return 126 - a } //go:noinline func sub_int8_127_ssa(a int8) int8 { return a - 127 } //go:noinline func sub_127_int8_ssa(a int8) int8 { return 127 - a } //go:noinline func div_int8_Neg128_ssa(a int8) int8 { return a / -128 } //go:noinline func div_Neg128_int8_ssa(a int8) int8 { return -128 / a } //go:noinline func div_int8_Neg127_ssa(a int8) int8 { return a / -127 } //go:noinline func div_Neg127_int8_ssa(a int8) int8 { return -127 / a } //go:noinline func div_int8_Neg1_ssa(a int8) int8 { return a / -1 } //go:noinline func div_Neg1_int8_ssa(a int8) int8 { return -1 / a } //go:noinline func div_0_int8_ssa(a int8) int8 { return 0 / a } //go:noinline func div_int8_1_ssa(a int8) int8 { return a / 1 } //go:noinline func div_1_int8_ssa(a int8) int8 { return 1 / a } //go:noinline func div_int8_126_ssa(a int8) int8 { return a / 126 } //go:noinline func div_126_int8_ssa(a int8) int8 { return 126 / a } //go:noinline func div_int8_127_ssa(a int8) int8 { return a / 127 } //go:noinline func div_127_int8_ssa(a int8) int8 { return 127 / a } //go:noinline func mul_int8_Neg128_ssa(a int8) int8 { return a * -128 } //go:noinline func mul_Neg128_int8_ssa(a int8) int8 { return -128 * a } //go:noinline func mul_int8_Neg127_ssa(a int8) int8 { return a * -127 } //go:noinline func mul_Neg127_int8_ssa(a int8) int8 { return -127 * a } //go:noinline func mul_int8_Neg1_ssa(a int8) int8 { return a * -1 } //go:noinline func mul_Neg1_int8_ssa(a int8) int8 { return -1 * a } //go:noinline func mul_int8_0_ssa(a int8) int8 { return a * 0 } //go:noinline func mul_0_int8_ssa(a int8) int8 { return 0 * a } //go:noinline func mul_int8_1_ssa(a int8) int8 { return a * 1 } //go:noinline func mul_1_int8_ssa(a int8) int8 { return 1 * a } //go:noinline func mul_int8_126_ssa(a int8) int8 { return a * 126 } //go:noinline func mul_126_int8_ssa(a int8) int8 { return 126 * a } //go:noinline func mul_int8_127_ssa(a int8) int8 { return a * 127 } //go:noinline func mul_127_int8_ssa(a int8) int8 { return 127 * a } //go:noinline func mod_int8_Neg128_ssa(a int8) int8 { return a % -128 } //go:noinline func mod_Neg128_int8_ssa(a int8) int8 { return -128 % a } //go:noinline func mod_int8_Neg127_ssa(a int8) int8 { return a % -127 } //go:noinline func mod_Neg127_int8_ssa(a int8) int8 { return -127 % a } //go:noinline func mod_int8_Neg1_ssa(a int8) int8 { return a % -1 } //go:noinline func mod_Neg1_int8_ssa(a int8) int8 { return -1 % a } //go:noinline func mod_0_int8_ssa(a int8) int8 { return 0 % a } //go:noinline func mod_int8_1_ssa(a int8) int8 { return a % 1 } //go:noinline func mod_1_int8_ssa(a int8) int8 { return 1 % a } //go:noinline func mod_int8_126_ssa(a int8) int8 { return a % 126 } //go:noinline func mod_126_int8_ssa(a int8) int8 { return 126 % a } //go:noinline func mod_int8_127_ssa(a int8) int8 { return a % 127 } //go:noinline func mod_127_int8_ssa(a int8) int8 { return 127 % a } //go:noinline func and_int8_Neg128_ssa(a int8) int8 { return a & -128 } //go:noinline func and_Neg128_int8_ssa(a int8) int8 { return -128 & a } //go:noinline func and_int8_Neg127_ssa(a int8) int8 { return a & -127 } //go:noinline func and_Neg127_int8_ssa(a int8) int8 { return -127 & a } //go:noinline func and_int8_Neg1_ssa(a int8) int8 { return a & -1 } //go:noinline func and_Neg1_int8_ssa(a int8) int8 { return -1 & a } //go:noinline func and_int8_0_ssa(a int8) int8 { return a & 0 } //go:noinline func and_0_int8_ssa(a int8) int8 { return 0 & a } //go:noinline func and_int8_1_ssa(a int8) int8 { return a & 1 } //go:noinline func and_1_int8_ssa(a int8) int8 { return 1 & a } //go:noinline func and_int8_126_ssa(a int8) int8 { return a & 126 } //go:noinline func and_126_int8_ssa(a int8) int8 { return 126 & a } //go:noinline func and_int8_127_ssa(a int8) int8 { return a & 127 } //go:noinline func and_127_int8_ssa(a int8) int8 { return 127 & a } //go:noinline func or_int8_Neg128_ssa(a int8) int8 { return a | -128 } //go:noinline func or_Neg128_int8_ssa(a int8) int8 { return -128 | a } //go:noinline func or_int8_Neg127_ssa(a int8) int8 { return a | -127 } //go:noinline func or_Neg127_int8_ssa(a int8) int8 { return -127 | a } //go:noinline func or_int8_Neg1_ssa(a int8) int8 { return a | -1 } //go:noinline func or_Neg1_int8_ssa(a int8) int8 { return -1 | a } //go:noinline func or_int8_0_ssa(a int8) int8 { return a | 0 } //go:noinline func or_0_int8_ssa(a int8) int8 { return 0 | a } //go:noinline func or_int8_1_ssa(a int8) int8 { return a | 1 } //go:noinline func or_1_int8_ssa(a int8) int8 { return 1 | a } //go:noinline func or_int8_126_ssa(a int8) int8 { return a | 126 } //go:noinline func or_126_int8_ssa(a int8) int8 { return 126 | a } //go:noinline func or_int8_127_ssa(a int8) int8 { return a | 127 } //go:noinline func or_127_int8_ssa(a int8) int8 { return 127 | a } //go:noinline func xor_int8_Neg128_ssa(a int8) int8 { return a ^ -128 } //go:noinline func xor_Neg128_int8_ssa(a int8) int8 { return -128 ^ a } //go:noinline func xor_int8_Neg127_ssa(a int8) int8 { return a ^ -127 } //go:noinline func xor_Neg127_int8_ssa(a int8) int8 { return -127 ^ a } //go:noinline func xor_int8_Neg1_ssa(a int8) int8 { return a ^ -1 } //go:noinline func xor_Neg1_int8_ssa(a int8) int8 { return -1 ^ a } //go:noinline func xor_int8_0_ssa(a int8) int8 { return a ^ 0 } //go:noinline func xor_0_int8_ssa(a int8) int8 { return 0 ^ a } //go:noinline func xor_int8_1_ssa(a int8) int8 { return a ^ 1 } //go:noinline func xor_1_int8_ssa(a int8) int8 { return 1 ^ a } //go:noinline func xor_int8_126_ssa(a int8) int8 { return a ^ 126 } //go:noinline func xor_126_int8_ssa(a int8) int8 { return 126 ^ a } //go:noinline func xor_int8_127_ssa(a int8) int8 { return a ^ 127 } //go:noinline func xor_127_int8_ssa(a int8) int8 { return 127 ^ a } var failed bool func main() { if got := add_0_uint64_ssa(0); got != 0 { fmt.Printf("add_uint64 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint64_0_ssa(0); got != 0 { fmt.Printf("add_uint64 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_uint64_ssa(1); got != 1 { fmt.Printf("add_uint64 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint64_0_ssa(1); got != 1 { fmt.Printf("add_uint64 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("add_uint64 0%s4294967296 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_uint64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("add_uint64 4294967296%s0 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_0_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("add_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `+`, got) failed = true } if got := add_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("add_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `+`, got) failed = true } if got := add_0_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("add_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `+`, got) failed = true } if got := add_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("add_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `+`, got) failed = true } if got := add_1_uint64_ssa(0); got != 1 { fmt.Printf("add_uint64 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint64_1_ssa(0); got != 1 { fmt.Printf("add_uint64 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_uint64_ssa(1); got != 2 { fmt.Printf("add_uint64 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_uint64_1_ssa(1); got != 2 { fmt.Printf("add_uint64 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_uint64_ssa(4294967296); got != 4294967297 { fmt.Printf("add_uint64 1%s4294967296 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_uint64_1_ssa(4294967296); got != 4294967297 { fmt.Printf("add_uint64 4294967296%s1 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_1_uint64_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("add_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `+`, got) failed = true } if got := add_uint64_1_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("add_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `+`, got) failed = true } if got := add_1_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("add_uint64 1%s18446744073709551615 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint64_1_ssa(18446744073709551615); got != 0 { fmt.Printf("add_uint64 18446744073709551615%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_4294967296_uint64_ssa(0); got != 4294967296 { fmt.Printf("add_uint64 4294967296%s0 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_uint64_4294967296_ssa(0); got != 4294967296 { fmt.Printf("add_uint64 0%s4294967296 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_4294967296_uint64_ssa(1); got != 4294967297 { fmt.Printf("add_uint64 4294967296%s1 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_uint64_4294967296_ssa(1); got != 4294967297 { fmt.Printf("add_uint64 1%s4294967296 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_4294967296_uint64_ssa(4294967296); got != 8589934592 { fmt.Printf("add_uint64 4294967296%s4294967296 = %d, wanted 8589934592\n", `+`, got) failed = true } if got := add_uint64_4294967296_ssa(4294967296); got != 8589934592 { fmt.Printf("add_uint64 4294967296%s4294967296 = %d, wanted 8589934592\n", `+`, got) failed = true } if got := add_4294967296_uint64_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("add_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `+`, got) failed = true } if got := add_uint64_4294967296_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("add_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `+`, got) failed = true } if got := add_4294967296_uint64_ssa(18446744073709551615); got != 4294967295 { fmt.Printf("add_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_uint64_4294967296_ssa(18446744073709551615); got != 4294967295 { fmt.Printf("add_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { fmt.Printf("add_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `+`, got) failed = true } if got := add_uint64_9223372036854775808_ssa(0); got != 9223372036854775808 { fmt.Printf("add_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `+`, got) failed = true } if got := add_9223372036854775808_uint64_ssa(1); got != 9223372036854775809 { fmt.Printf("add_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `+`, got) failed = true } if got := add_uint64_9223372036854775808_ssa(1); got != 9223372036854775809 { fmt.Printf("add_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `+`, got) failed = true } if got := add_9223372036854775808_uint64_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("add_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `+`, got) failed = true } if got := add_uint64_9223372036854775808_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("add_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `+`, got) failed = true } if got := add_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("add_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("add_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `+`, got) failed = true } if got := add_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("add_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("add_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { fmt.Printf("add_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `+`, got) failed = true } if got := add_uint64_18446744073709551615_ssa(0); got != 18446744073709551615 { fmt.Printf("add_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `+`, got) failed = true } if got := add_18446744073709551615_uint64_ssa(1); got != 0 { fmt.Printf("add_uint64 18446744073709551615%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint64_18446744073709551615_ssa(1); got != 0 { fmt.Printf("add_uint64 1%s18446744073709551615 = %d, wanted 0\n", `+`, got) failed = true } if got := add_18446744073709551615_uint64_ssa(4294967296); got != 4294967295 { fmt.Printf("add_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_uint64_18446744073709551615_ssa(4294967296); got != 4294967295 { fmt.Printf("add_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("add_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("add_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_18446744073709551615_uint64_ssa(18446744073709551615); got != 18446744073709551614 { fmt.Printf("add_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551614\n", `+`, got) failed = true } if got := add_uint64_18446744073709551615_ssa(18446744073709551615); got != 18446744073709551614 { fmt.Printf("add_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551614\n", `+`, got) failed = true } if got := sub_0_uint64_ssa(0); got != 0 { fmt.Printf("sub_uint64 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint64_0_ssa(0); got != 0 { fmt.Printf("sub_uint64 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_uint64_ssa(1); got != 18446744073709551615 { fmt.Printf("sub_uint64 0%s1 = %d, wanted 18446744073709551615\n", `-`, got) failed = true } if got := sub_uint64_0_ssa(1); got != 1 { fmt.Printf("sub_uint64 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_uint64_ssa(4294967296); got != 18446744069414584320 { fmt.Printf("sub_uint64 0%s4294967296 = %d, wanted 18446744069414584320\n", `-`, got) failed = true } if got := sub_uint64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("sub_uint64 4294967296%s0 = %d, wanted 4294967296\n", `-`, got) failed = true } if got := sub_0_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("sub_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `-`, got) failed = true } if got := sub_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("sub_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `-`, got) failed = true } if got := sub_0_uint64_ssa(18446744073709551615); got != 1 { fmt.Printf("sub_uint64 0%s18446744073709551615 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("sub_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `-`, got) failed = true } if got := sub_1_uint64_ssa(0); got != 1 { fmt.Printf("sub_uint64 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint64_1_ssa(0); got != 18446744073709551615 { fmt.Printf("sub_uint64 0%s1 = %d, wanted 18446744073709551615\n", `-`, got) failed = true } if got := sub_1_uint64_ssa(1); got != 0 { fmt.Printf("sub_uint64 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint64_1_ssa(1); got != 0 { fmt.Printf("sub_uint64 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_uint64_ssa(4294967296); got != 18446744069414584321 { fmt.Printf("sub_uint64 1%s4294967296 = %d, wanted 18446744069414584321\n", `-`, got) failed = true } if got := sub_uint64_1_ssa(4294967296); got != 4294967295 { fmt.Printf("sub_uint64 4294967296%s1 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_1_uint64_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("sub_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `-`, got) failed = true } if got := sub_uint64_1_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("sub_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_1_uint64_ssa(18446744073709551615); got != 2 { fmt.Printf("sub_uint64 1%s18446744073709551615 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_uint64_1_ssa(18446744073709551615); got != 18446744073709551614 { fmt.Printf("sub_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `-`, got) failed = true } if got := sub_4294967296_uint64_ssa(0); got != 4294967296 { fmt.Printf("sub_uint64 4294967296%s0 = %d, wanted 4294967296\n", `-`, got) failed = true } if got := sub_uint64_4294967296_ssa(0); got != 18446744069414584320 { fmt.Printf("sub_uint64 0%s4294967296 = %d, wanted 18446744069414584320\n", `-`, got) failed = true } if got := sub_4294967296_uint64_ssa(1); got != 4294967295 { fmt.Printf("sub_uint64 4294967296%s1 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_uint64_4294967296_ssa(1); got != 18446744069414584321 { fmt.Printf("sub_uint64 1%s4294967296 = %d, wanted 18446744069414584321\n", `-`, got) failed = true } if got := sub_4294967296_uint64_ssa(4294967296); got != 0 { fmt.Printf("sub_uint64 4294967296%s4294967296 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("sub_uint64 4294967296%s4294967296 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_4294967296_uint64_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("sub_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `-`, got) failed = true } if got := sub_uint64_4294967296_ssa(9223372036854775808); got != 9223372032559808512 { fmt.Printf("sub_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372032559808512\n", `-`, got) failed = true } if got := sub_4294967296_uint64_ssa(18446744073709551615); got != 4294967297 { fmt.Printf("sub_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967297\n", `-`, got) failed = true } if got := sub_uint64_4294967296_ssa(18446744073709551615); got != 18446744069414584319 { fmt.Printf("sub_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584319\n", `-`, got) failed = true } if got := sub_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { fmt.Printf("sub_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `-`, got) failed = true } if got := sub_uint64_9223372036854775808_ssa(0); got != 9223372036854775808 { fmt.Printf("sub_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `-`, got) failed = true } if got := sub_9223372036854775808_uint64_ssa(1); got != 9223372036854775807 { fmt.Printf("sub_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_uint64_9223372036854775808_ssa(1); got != 9223372036854775809 { fmt.Printf("sub_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `-`, got) failed = true } if got := sub_9223372036854775808_uint64_ssa(4294967296); got != 9223372032559808512 { fmt.Printf("sub_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372032559808512\n", `-`, got) failed = true } if got := sub_uint64_9223372036854775808_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("sub_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `-`, got) failed = true } if got := sub_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("sub_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("sub_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775809 { fmt.Printf("sub_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775809\n", `-`, got) failed = true } if got := sub_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("sub_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { fmt.Printf("sub_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `-`, got) failed = true } if got := sub_uint64_18446744073709551615_ssa(0); got != 1 { fmt.Printf("sub_uint64 0%s18446744073709551615 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_18446744073709551615_uint64_ssa(1); got != 18446744073709551614 { fmt.Printf("sub_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `-`, got) failed = true } if got := sub_uint64_18446744073709551615_ssa(1); got != 2 { fmt.Printf("sub_uint64 1%s18446744073709551615 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_18446744073709551615_uint64_ssa(4294967296); got != 18446744069414584319 { fmt.Printf("sub_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584319\n", `-`, got) failed = true } if got := sub_uint64_18446744073709551615_ssa(4294967296); got != 4294967297 { fmt.Printf("sub_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967297\n", `-`, got) failed = true } if got := sub_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("sub_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("sub_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775809\n", `-`, got) failed = true } if got := sub_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("sub_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { fmt.Printf("sub_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `-`, got) failed = true } if got := div_0_uint64_ssa(1); got != 0 { fmt.Printf("div_uint64 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_uint64_ssa(4294967296); got != 0 { fmt.Printf("div_uint64 0%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("div_uint64 0%s9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("div_uint64 0%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_1_ssa(0); got != 0 { fmt.Printf("div_uint64 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_uint64_ssa(1); got != 1 { fmt.Printf("div_uint64 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint64_1_ssa(1); got != 1 { fmt.Printf("div_uint64 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_uint64_ssa(4294967296); got != 0 { fmt.Printf("div_uint64 1%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_1_ssa(4294967296); got != 4294967296 { fmt.Printf("div_uint64 4294967296%s1 = %d, wanted 4294967296\n", `/`, got) failed = true } if got := div_1_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("div_uint64 1%s9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_1_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("div_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775808\n", `/`, got) failed = true } if got := div_1_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("div_uint64 1%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_1_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("div_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `/`, got) failed = true } if got := div_uint64_4294967296_ssa(0); got != 0 { fmt.Printf("div_uint64 0%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_4294967296_uint64_ssa(1); got != 4294967296 { fmt.Printf("div_uint64 4294967296%s1 = %d, wanted 4294967296\n", `/`, got) failed = true } if got := div_uint64_4294967296_ssa(1); got != 0 { fmt.Printf("div_uint64 1%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_4294967296_uint64_ssa(4294967296); got != 1 { fmt.Printf("div_uint64 4294967296%s4294967296 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint64_4294967296_ssa(4294967296); got != 1 { fmt.Printf("div_uint64 4294967296%s4294967296 = %d, wanted 1\n", `/`, got) failed = true } if got := div_4294967296_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("div_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_4294967296_ssa(9223372036854775808); got != 2147483648 { fmt.Printf("div_uint64 9223372036854775808%s4294967296 = %d, wanted 2147483648\n", `/`, got) failed = true } if got := div_4294967296_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("div_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_4294967296_ssa(18446744073709551615); got != 4294967295 { fmt.Printf("div_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `/`, got) failed = true } if got := div_uint64_9223372036854775808_ssa(0); got != 0 { fmt.Printf("div_uint64 0%s9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775808_uint64_ssa(1); got != 9223372036854775808 { fmt.Printf("div_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775808\n", `/`, got) failed = true } if got := div_uint64_9223372036854775808_ssa(1); got != 0 { fmt.Printf("div_uint64 1%s9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775808_uint64_ssa(4294967296); got != 2147483648 { fmt.Printf("div_uint64 9223372036854775808%s4294967296 = %d, wanted 2147483648\n", `/`, got) failed = true } if got := div_uint64_9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("div_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775808_uint64_ssa(9223372036854775808); got != 1 { fmt.Printf("div_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint64_9223372036854775808_ssa(9223372036854775808); got != 1 { fmt.Printf("div_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 1\n", `/`, got) failed = true } if got := div_9223372036854775808_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("div_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_9223372036854775808_ssa(18446744073709551615); got != 1 { fmt.Printf("div_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint64_18446744073709551615_ssa(0); got != 0 { fmt.Printf("div_uint64 0%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_18446744073709551615_uint64_ssa(1); got != 18446744073709551615 { fmt.Printf("div_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `/`, got) failed = true } if got := div_uint64_18446744073709551615_ssa(1); got != 0 { fmt.Printf("div_uint64 1%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_18446744073709551615_uint64_ssa(4294967296); got != 4294967295 { fmt.Printf("div_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `/`, got) failed = true } if got := div_uint64_18446744073709551615_ssa(4294967296); got != 0 { fmt.Printf("div_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_18446744073709551615_uint64_ssa(9223372036854775808); got != 1 { fmt.Printf("div_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint64_18446744073709551615_ssa(9223372036854775808); got != 0 { fmt.Printf("div_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_18446744073709551615_uint64_ssa(18446744073709551615); got != 1 { fmt.Printf("div_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint64_18446744073709551615_ssa(18446744073709551615); got != 1 { fmt.Printf("div_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_0_uint64_ssa(0); got != 0 { fmt.Printf("mul_uint64 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_0_ssa(0); got != 0 { fmt.Printf("mul_uint64 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint64_ssa(1); got != 0 { fmt.Printf("mul_uint64 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_0_ssa(1); got != 0 { fmt.Printf("mul_uint64 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint64_ssa(4294967296); got != 0 { fmt.Printf("mul_uint64 0%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_0_ssa(4294967296); got != 0 { fmt.Printf("mul_uint64 4294967296%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("mul_uint64 0%s9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_0_ssa(9223372036854775808); got != 0 { fmt.Printf("mul_uint64 9223372036854775808%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("mul_uint64 0%s18446744073709551615 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_0_ssa(18446744073709551615); got != 0 { fmt.Printf("mul_uint64 18446744073709551615%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint64_ssa(0); got != 0 { fmt.Printf("mul_uint64 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_1_ssa(0); got != 0 { fmt.Printf("mul_uint64 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint64_ssa(1); got != 1 { fmt.Printf("mul_uint64 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint64_1_ssa(1); got != 1 { fmt.Printf("mul_uint64 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("mul_uint64 1%s4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_uint64_1_ssa(4294967296); got != 4294967296 { fmt.Printf("mul_uint64 4294967296%s1 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_1_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("mul_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_uint64_1_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("mul_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_1_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("mul_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551615\n", `*`, got) failed = true } if got := mul_uint64_1_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("mul_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `*`, got) failed = true } if got := mul_4294967296_uint64_ssa(0); got != 0 { fmt.Printf("mul_uint64 4294967296%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_4294967296_ssa(0); got != 0 { fmt.Printf("mul_uint64 0%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_uint64_ssa(1); got != 4294967296 { fmt.Printf("mul_uint64 4294967296%s1 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_uint64_4294967296_ssa(1); got != 4294967296 { fmt.Printf("mul_uint64 1%s4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_4294967296_uint64_ssa(4294967296); got != 0 { fmt.Printf("mul_uint64 4294967296%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("mul_uint64 4294967296%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("mul_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_4294967296_ssa(9223372036854775808); got != 0 { fmt.Printf("mul_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_uint64_ssa(18446744073709551615); got != 18446744069414584320 { fmt.Printf("mul_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744069414584320\n", `*`, got) failed = true } if got := mul_uint64_4294967296_ssa(18446744073709551615); got != 18446744069414584320 { fmt.Printf("mul_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584320\n", `*`, got) failed = true } if got := mul_9223372036854775808_uint64_ssa(0); got != 0 { fmt.Printf("mul_uint64 9223372036854775808%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_9223372036854775808_ssa(0); got != 0 { fmt.Printf("mul_uint64 0%s9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_9223372036854775808_uint64_ssa(1); got != 9223372036854775808 { fmt.Printf("mul_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_uint64_9223372036854775808_ssa(1); got != 9223372036854775808 { fmt.Printf("mul_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_9223372036854775808_uint64_ssa(4294967296); got != 0 { fmt.Printf("mul_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("mul_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("mul_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("mul_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775808 { fmt.Printf("mul_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775808 { fmt.Printf("mul_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_18446744073709551615_uint64_ssa(0); got != 0 { fmt.Printf("mul_uint64 18446744073709551615%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_18446744073709551615_ssa(0); got != 0 { fmt.Printf("mul_uint64 0%s18446744073709551615 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_18446744073709551615_uint64_ssa(1); got != 18446744073709551615 { fmt.Printf("mul_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `*`, got) failed = true } if got := mul_uint64_18446744073709551615_ssa(1); got != 18446744073709551615 { fmt.Printf("mul_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551615\n", `*`, got) failed = true } if got := mul_18446744073709551615_uint64_ssa(4294967296); got != 18446744069414584320 { fmt.Printf("mul_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584320\n", `*`, got) failed = true } if got := mul_uint64_18446744073709551615_ssa(4294967296); got != 18446744069414584320 { fmt.Printf("mul_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744069414584320\n", `*`, got) failed = true } if got := mul_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("mul_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("mul_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_18446744073709551615_uint64_ssa(18446744073709551615); got != 1 { fmt.Printf("mul_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint64_18446744073709551615_ssa(18446744073709551615); got != 1 { fmt.Printf("mul_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 1\n", `*`, got) failed = true } if got := lsh_0_uint64_ssa(0); got != 0 { fmt.Printf("lsh_uint64 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_0_ssa(0); got != 0 { fmt.Printf("lsh_uint64 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_0_uint64_ssa(1); got != 0 { fmt.Printf("lsh_uint64 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_0_ssa(1); got != 1 { fmt.Printf("lsh_uint64 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_0_uint64_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 0%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("lsh_uint64 4294967296%s0 = %d, wanted 4294967296\n", `<<`, got) failed = true } if got := lsh_0_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 0%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("lsh_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `<<`, got) failed = true } if got := lsh_0_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 0%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("lsh_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `<<`, got) failed = true } if got := lsh_1_uint64_ssa(0); got != 1 { fmt.Printf("lsh_uint64 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_uint64_1_ssa(0); got != 0 { fmt.Printf("lsh_uint64 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_1_uint64_ssa(1); got != 2 { fmt.Printf("lsh_uint64 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_uint64_1_ssa(1); got != 2 { fmt.Printf("lsh_uint64 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_1_uint64_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 1%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_1_ssa(4294967296); got != 8589934592 { fmt.Printf("lsh_uint64 4294967296%s1 = %d, wanted 8589934592\n", `<<`, got) failed = true } if got := lsh_1_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 1%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_1_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_1_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 1%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_1_ssa(18446744073709551615); got != 18446744073709551614 { fmt.Printf("lsh_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `<<`, got) failed = true } if got := lsh_4294967296_uint64_ssa(0); got != 4294967296 { fmt.Printf("lsh_uint64 4294967296%s0 = %d, wanted 4294967296\n", `<<`, got) failed = true } if got := lsh_uint64_4294967296_ssa(0); got != 0 { fmt.Printf("lsh_uint64 0%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_4294967296_uint64_ssa(1); got != 8589934592 { fmt.Printf("lsh_uint64 4294967296%s1 = %d, wanted 8589934592\n", `<<`, got) failed = true } if got := lsh_uint64_4294967296_ssa(1); got != 0 { fmt.Printf("lsh_uint64 1%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_4294967296_uint64_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 4294967296%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 4294967296%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_4294967296_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_4294967296_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_4294967296_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_4294967296_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 18446744073709551615%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { fmt.Printf("lsh_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `<<`, got) failed = true } if got := lsh_uint64_9223372036854775808_ssa(0); got != 0 { fmt.Printf("lsh_uint64 0%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_9223372036854775808_uint64_ssa(1); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_9223372036854775808_ssa(1); got != 0 { fmt.Printf("lsh_uint64 1%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_9223372036854775808_uint64_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_9223372036854775808_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_9223372036854775808_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { fmt.Printf("lsh_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `<<`, got) failed = true } if got := lsh_uint64_18446744073709551615_ssa(0); got != 0 { fmt.Printf("lsh_uint64 0%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_18446744073709551615_uint64_ssa(1); got != 18446744073709551614 { fmt.Printf("lsh_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `<<`, got) failed = true } if got := lsh_uint64_18446744073709551615_ssa(1); got != 0 { fmt.Printf("lsh_uint64 1%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_18446744073709551615_uint64_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 18446744073709551615%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_18446744073709551615_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_18446744073709551615_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_18446744073709551615_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := rsh_0_uint64_ssa(0); got != 0 { fmt.Printf("rsh_uint64 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_0_ssa(0); got != 0 { fmt.Printf("rsh_uint64 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_0_uint64_ssa(1); got != 0 { fmt.Printf("rsh_uint64 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_0_ssa(1); got != 1 { fmt.Printf("rsh_uint64 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_0_uint64_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 0%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("rsh_uint64 4294967296%s0 = %d, wanted 4294967296\n", `>>`, got) failed = true } if got := rsh_0_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 0%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("rsh_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `>>`, got) failed = true } if got := rsh_0_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 0%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("rsh_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `>>`, got) failed = true } if got := rsh_1_uint64_ssa(0); got != 1 { fmt.Printf("rsh_uint64 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_uint64_1_ssa(0); got != 0 { fmt.Printf("rsh_uint64 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint64_ssa(1); got != 0 { fmt.Printf("rsh_uint64 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_1_ssa(1); got != 0 { fmt.Printf("rsh_uint64 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint64_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 1%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_1_ssa(4294967296); got != 2147483648 { fmt.Printf("rsh_uint64 4294967296%s1 = %d, wanted 2147483648\n", `>>`, got) failed = true } if got := rsh_1_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 1%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_1_ssa(9223372036854775808); got != 4611686018427387904 { fmt.Printf("rsh_uint64 9223372036854775808%s1 = %d, wanted 4611686018427387904\n", `>>`, got) failed = true } if got := rsh_1_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 1%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_1_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("rsh_uint64 18446744073709551615%s1 = %d, wanted 9223372036854775807\n", `>>`, got) failed = true } if got := rsh_4294967296_uint64_ssa(0); got != 4294967296 { fmt.Printf("rsh_uint64 4294967296%s0 = %d, wanted 4294967296\n", `>>`, got) failed = true } if got := rsh_uint64_4294967296_ssa(0); got != 0 { fmt.Printf("rsh_uint64 0%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_4294967296_uint64_ssa(1); got != 2147483648 { fmt.Printf("rsh_uint64 4294967296%s1 = %d, wanted 2147483648\n", `>>`, got) failed = true } if got := rsh_uint64_4294967296_ssa(1); got != 0 { fmt.Printf("rsh_uint64 1%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_4294967296_uint64_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 4294967296%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 4294967296%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_4294967296_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_4294967296_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_4294967296_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_4294967296_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 18446744073709551615%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { fmt.Printf("rsh_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `>>`, got) failed = true } if got := rsh_uint64_9223372036854775808_ssa(0); got != 0 { fmt.Printf("rsh_uint64 0%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_9223372036854775808_uint64_ssa(1); got != 4611686018427387904 { fmt.Printf("rsh_uint64 9223372036854775808%s1 = %d, wanted 4611686018427387904\n", `>>`, got) failed = true } if got := rsh_uint64_9223372036854775808_ssa(1); got != 0 { fmt.Printf("rsh_uint64 1%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_9223372036854775808_uint64_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_9223372036854775808_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_9223372036854775808_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { fmt.Printf("rsh_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `>>`, got) failed = true } if got := rsh_uint64_18446744073709551615_ssa(0); got != 0 { fmt.Printf("rsh_uint64 0%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_18446744073709551615_uint64_ssa(1); got != 9223372036854775807 { fmt.Printf("rsh_uint64 18446744073709551615%s1 = %d, wanted 9223372036854775807\n", `>>`, got) failed = true } if got := rsh_uint64_18446744073709551615_ssa(1); got != 0 { fmt.Printf("rsh_uint64 1%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_18446744073709551615_uint64_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 18446744073709551615%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_18446744073709551615_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_18446744073709551615_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_18446744073709551615_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := mod_0_uint64_ssa(1); got != 0 { fmt.Printf("mod_uint64 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_uint64_ssa(4294967296); got != 0 { fmt.Printf("mod_uint64 0%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("mod_uint64 0%s9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("mod_uint64 0%s18446744073709551615 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_1_ssa(0); got != 0 { fmt.Printf("mod_uint64 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint64_ssa(1); got != 0 { fmt.Printf("mod_uint64 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_1_ssa(1); got != 0 { fmt.Printf("mod_uint64 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint64_ssa(4294967296); got != 1 { fmt.Printf("mod_uint64 1%s4294967296 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_uint64_1_ssa(4294967296); got != 0 { fmt.Printf("mod_uint64 4294967296%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint64_ssa(9223372036854775808); got != 1 { fmt.Printf("mod_uint64 1%s9223372036854775808 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_uint64_1_ssa(9223372036854775808); got != 0 { fmt.Printf("mod_uint64 9223372036854775808%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint64_ssa(18446744073709551615); got != 1 { fmt.Printf("mod_uint64 1%s18446744073709551615 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_uint64_1_ssa(18446744073709551615); got != 0 { fmt.Printf("mod_uint64 18446744073709551615%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_4294967296_ssa(0); got != 0 { fmt.Printf("mod_uint64 0%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_uint64_ssa(1); got != 0 { fmt.Printf("mod_uint64 4294967296%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_4294967296_ssa(1); got != 1 { fmt.Printf("mod_uint64 1%s4294967296 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_4294967296_uint64_ssa(4294967296); got != 0 { fmt.Printf("mod_uint64 4294967296%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("mod_uint64 4294967296%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_uint64_ssa(9223372036854775808); got != 4294967296 { fmt.Printf("mod_uint64 4294967296%s9223372036854775808 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_uint64_4294967296_ssa(9223372036854775808); got != 0 { fmt.Printf("mod_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_uint64_ssa(18446744073709551615); got != 4294967296 { fmt.Printf("mod_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_uint64_4294967296_ssa(18446744073709551615); got != 4294967295 { fmt.Printf("mod_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `%`, got) failed = true } if got := mod_uint64_9223372036854775808_ssa(0); got != 0 { fmt.Printf("mod_uint64 0%s9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_9223372036854775808_uint64_ssa(1); got != 0 { fmt.Printf("mod_uint64 9223372036854775808%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_9223372036854775808_ssa(1); got != 1 { fmt.Printf("mod_uint64 1%s9223372036854775808 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_9223372036854775808_uint64_ssa(4294967296); got != 0 { fmt.Printf("mod_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_9223372036854775808_ssa(4294967296); got != 4294967296 { fmt.Printf("mod_uint64 4294967296%s9223372036854775808 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("mod_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("mod_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775808 { fmt.Printf("mod_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `%`, got) failed = true } if got := mod_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("mod_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `%`, got) failed = true } if got := mod_uint64_18446744073709551615_ssa(0); got != 0 { fmt.Printf("mod_uint64 0%s18446744073709551615 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_18446744073709551615_uint64_ssa(1); got != 0 { fmt.Printf("mod_uint64 18446744073709551615%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_18446744073709551615_ssa(1); got != 1 { fmt.Printf("mod_uint64 1%s18446744073709551615 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_18446744073709551615_uint64_ssa(4294967296); got != 4294967295 { fmt.Printf("mod_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `%`, got) failed = true } if got := mod_uint64_18446744073709551615_ssa(4294967296); got != 4294967296 { fmt.Printf("mod_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("mod_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `%`, got) failed = true } if got := mod_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("mod_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `%`, got) failed = true } if got := mod_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("mod_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { fmt.Printf("mod_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `%`, got) failed = true } if got := and_0_uint64_ssa(0); got != 0 { fmt.Printf("and_uint64 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_0_ssa(0); got != 0 { fmt.Printf("and_uint64 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint64_ssa(1); got != 0 { fmt.Printf("and_uint64 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_0_ssa(1); got != 0 { fmt.Printf("and_uint64 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint64_ssa(4294967296); got != 0 { fmt.Printf("and_uint64 0%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_0_ssa(4294967296); got != 0 { fmt.Printf("and_uint64 4294967296%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("and_uint64 0%s9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_0_ssa(9223372036854775808); got != 0 { fmt.Printf("and_uint64 9223372036854775808%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("and_uint64 0%s18446744073709551615 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_0_ssa(18446744073709551615); got != 0 { fmt.Printf("and_uint64 18446744073709551615%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint64_ssa(0); got != 0 { fmt.Printf("and_uint64 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_1_ssa(0); got != 0 { fmt.Printf("and_uint64 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint64_ssa(1); got != 1 { fmt.Printf("and_uint64 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint64_1_ssa(1); got != 1 { fmt.Printf("and_uint64 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_uint64_ssa(4294967296); got != 0 { fmt.Printf("and_uint64 1%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_1_ssa(4294967296); got != 0 { fmt.Printf("and_uint64 4294967296%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("and_uint64 1%s9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_1_ssa(9223372036854775808); got != 0 { fmt.Printf("and_uint64 9223372036854775808%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint64_ssa(18446744073709551615); got != 1 { fmt.Printf("and_uint64 1%s18446744073709551615 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint64_1_ssa(18446744073709551615); got != 1 { fmt.Printf("and_uint64 18446744073709551615%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_4294967296_uint64_ssa(0); got != 0 { fmt.Printf("and_uint64 4294967296%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_4294967296_ssa(0); got != 0 { fmt.Printf("and_uint64 0%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_uint64_ssa(1); got != 0 { fmt.Printf("and_uint64 4294967296%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_4294967296_ssa(1); got != 0 { fmt.Printf("and_uint64 1%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_uint64 4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_uint64_4294967296_ssa(4294967296); got != 4294967296 { fmt.Printf("and_uint64 4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_4294967296_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("and_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_4294967296_ssa(9223372036854775808); got != 0 { fmt.Printf("and_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_uint64_ssa(18446744073709551615); got != 4294967296 { fmt.Printf("and_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_uint64_4294967296_ssa(18446744073709551615); got != 4294967296 { fmt.Printf("and_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_9223372036854775808_uint64_ssa(0); got != 0 { fmt.Printf("and_uint64 9223372036854775808%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_9223372036854775808_ssa(0); got != 0 { fmt.Printf("and_uint64 0%s9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775808_uint64_ssa(1); got != 0 { fmt.Printf("and_uint64 9223372036854775808%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_9223372036854775808_ssa(1); got != 0 { fmt.Printf("and_uint64 1%s9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775808_uint64_ssa(4294967296); got != 0 { fmt.Printf("and_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("and_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775808_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("and_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 9223372036854775808\n", `&`, got) failed = true } if got := and_uint64_9223372036854775808_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("and_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 9223372036854775808\n", `&`, got) failed = true } if got := and_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775808 { fmt.Printf("and_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `&`, got) failed = true } if got := and_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775808 { fmt.Printf("and_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775808\n", `&`, got) failed = true } if got := and_18446744073709551615_uint64_ssa(0); got != 0 { fmt.Printf("and_uint64 18446744073709551615%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_18446744073709551615_ssa(0); got != 0 { fmt.Printf("and_uint64 0%s18446744073709551615 = %d, wanted 0\n", `&`, got) failed = true } if got := and_18446744073709551615_uint64_ssa(1); got != 1 { fmt.Printf("and_uint64 18446744073709551615%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint64_18446744073709551615_ssa(1); got != 1 { fmt.Printf("and_uint64 1%s18446744073709551615 = %d, wanted 1\n", `&`, got) failed = true } if got := and_18446744073709551615_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_uint64_18446744073709551615_ssa(4294967296); got != 4294967296 { fmt.Printf("and_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("and_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775808\n", `&`, got) failed = true } if got := and_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("and_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `&`, got) failed = true } if got := and_18446744073709551615_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("and_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551615\n", `&`, got) failed = true } if got := and_uint64_18446744073709551615_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("and_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551615\n", `&`, got) failed = true } if got := or_0_uint64_ssa(0); got != 0 { fmt.Printf("or_uint64 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_uint64_0_ssa(0); got != 0 { fmt.Printf("or_uint64 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_uint64_ssa(1); got != 1 { fmt.Printf("or_uint64 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint64_0_ssa(1); got != 1 { fmt.Printf("or_uint64 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("or_uint64 0%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_uint64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("or_uint64 4294967296%s0 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_0_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("or_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `|`, got) failed = true } if got := or_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("or_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `|`, got) failed = true } if got := or_0_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_1_uint64_ssa(0); got != 1 { fmt.Printf("or_uint64 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint64_1_ssa(0); got != 1 { fmt.Printf("or_uint64 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint64_ssa(1); got != 1 { fmt.Printf("or_uint64 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint64_1_ssa(1); got != 1 { fmt.Printf("or_uint64 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint64_ssa(4294967296); got != 4294967297 { fmt.Printf("or_uint64 1%s4294967296 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_uint64_1_ssa(4294967296); got != 4294967297 { fmt.Printf("or_uint64 4294967296%s1 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_1_uint64_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("or_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `|`, got) failed = true } if got := or_uint64_1_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("or_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `|`, got) failed = true } if got := or_1_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_1_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_4294967296_uint64_ssa(0); got != 4294967296 { fmt.Printf("or_uint64 4294967296%s0 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_uint64_4294967296_ssa(0); got != 4294967296 { fmt.Printf("or_uint64 0%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_4294967296_uint64_ssa(1); got != 4294967297 { fmt.Printf("or_uint64 4294967296%s1 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_uint64_4294967296_ssa(1); got != 4294967297 { fmt.Printf("or_uint64 1%s4294967296 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_4294967296_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("or_uint64 4294967296%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_uint64_4294967296_ssa(4294967296); got != 4294967296 { fmt.Printf("or_uint64 4294967296%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_4294967296_uint64_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("or_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `|`, got) failed = true } if got := or_uint64_4294967296_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("or_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `|`, got) failed = true } if got := or_4294967296_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_4294967296_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { fmt.Printf("or_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `|`, got) failed = true } if got := or_uint64_9223372036854775808_ssa(0); got != 9223372036854775808 { fmt.Printf("or_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `|`, got) failed = true } if got := or_9223372036854775808_uint64_ssa(1); got != 9223372036854775809 { fmt.Printf("or_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `|`, got) failed = true } if got := or_uint64_9223372036854775808_ssa(1); got != 9223372036854775809 { fmt.Printf("or_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `|`, got) failed = true } if got := or_9223372036854775808_uint64_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("or_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `|`, got) failed = true } if got := or_uint64_9223372036854775808_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("or_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `|`, got) failed = true } if got := or_9223372036854775808_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("or_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 9223372036854775808\n", `|`, got) failed = true } if got := or_uint64_9223372036854775808_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("or_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 9223372036854775808\n", `|`, got) failed = true } if got := or_9223372036854775808_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_9223372036854775808_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_18446744073709551615_ssa(0); got != 18446744073709551615 { fmt.Printf("or_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_18446744073709551615_uint64_ssa(1); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_18446744073709551615_ssa(1); got != 18446744073709551615 { fmt.Printf("or_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_18446744073709551615_uint64_ssa(4294967296); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_18446744073709551615_ssa(4294967296); got != 18446744073709551615 { fmt.Printf("or_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_18446744073709551615_uint64_ssa(9223372036854775808); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_18446744073709551615_ssa(9223372036854775808); got != 18446744073709551615 { fmt.Printf("or_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_18446744073709551615_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_18446744073709551615_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := xor_0_uint64_ssa(0); got != 0 { fmt.Printf("xor_uint64 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint64_0_ssa(0); got != 0 { fmt.Printf("xor_uint64 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_uint64_ssa(1); got != 1 { fmt.Printf("xor_uint64 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint64_0_ssa(1); got != 1 { fmt.Printf("xor_uint64 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("xor_uint64 0%s4294967296 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_uint64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("xor_uint64 4294967296%s0 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_0_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("xor_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `^`, got) failed = true } if got := xor_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("xor_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `^`, got) failed = true } if got := xor_0_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("xor_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `^`, got) failed = true } if got := xor_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("xor_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `^`, got) failed = true } if got := xor_1_uint64_ssa(0); got != 1 { fmt.Printf("xor_uint64 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint64_1_ssa(0); got != 1 { fmt.Printf("xor_uint64 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_uint64_ssa(1); got != 0 { fmt.Printf("xor_uint64 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint64_1_ssa(1); got != 0 { fmt.Printf("xor_uint64 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_uint64_ssa(4294967296); got != 4294967297 { fmt.Printf("xor_uint64 1%s4294967296 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_uint64_1_ssa(4294967296); got != 4294967297 { fmt.Printf("xor_uint64 4294967296%s1 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_1_uint64_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("xor_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `^`, got) failed = true } if got := xor_uint64_1_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("xor_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `^`, got) failed = true } if got := xor_1_uint64_ssa(18446744073709551615); got != 18446744073709551614 { fmt.Printf("xor_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551614\n", `^`, got) failed = true } if got := xor_uint64_1_ssa(18446744073709551615); got != 18446744073709551614 { fmt.Printf("xor_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `^`, got) failed = true } if got := xor_4294967296_uint64_ssa(0); got != 4294967296 { fmt.Printf("xor_uint64 4294967296%s0 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_uint64_4294967296_ssa(0); got != 4294967296 { fmt.Printf("xor_uint64 0%s4294967296 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_4294967296_uint64_ssa(1); got != 4294967297 { fmt.Printf("xor_uint64 4294967296%s1 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_uint64_4294967296_ssa(1); got != 4294967297 { fmt.Printf("xor_uint64 1%s4294967296 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_4294967296_uint64_ssa(4294967296); got != 0 { fmt.Printf("xor_uint64 4294967296%s4294967296 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("xor_uint64 4294967296%s4294967296 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_4294967296_uint64_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("xor_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `^`, got) failed = true } if got := xor_uint64_4294967296_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("xor_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `^`, got) failed = true } if got := xor_4294967296_uint64_ssa(18446744073709551615); got != 18446744069414584319 { fmt.Printf("xor_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744069414584319\n", `^`, got) failed = true } if got := xor_uint64_4294967296_ssa(18446744073709551615); got != 18446744069414584319 { fmt.Printf("xor_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584319\n", `^`, got) failed = true } if got := xor_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { fmt.Printf("xor_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `^`, got) failed = true } if got := xor_uint64_9223372036854775808_ssa(0); got != 9223372036854775808 { fmt.Printf("xor_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `^`, got) failed = true } if got := xor_9223372036854775808_uint64_ssa(1); got != 9223372036854775809 { fmt.Printf("xor_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `^`, got) failed = true } if got := xor_uint64_9223372036854775808_ssa(1); got != 9223372036854775809 { fmt.Printf("xor_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `^`, got) failed = true } if got := xor_9223372036854775808_uint64_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("xor_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `^`, got) failed = true } if got := xor_uint64_9223372036854775808_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("xor_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `^`, got) failed = true } if got := xor_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("xor_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("xor_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("xor_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("xor_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { fmt.Printf("xor_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `^`, got) failed = true } if got := xor_uint64_18446744073709551615_ssa(0); got != 18446744073709551615 { fmt.Printf("xor_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `^`, got) failed = true } if got := xor_18446744073709551615_uint64_ssa(1); got != 18446744073709551614 { fmt.Printf("xor_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `^`, got) failed = true } if got := xor_uint64_18446744073709551615_ssa(1); got != 18446744073709551614 { fmt.Printf("xor_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551614\n", `^`, got) failed = true } if got := xor_18446744073709551615_uint64_ssa(4294967296); got != 18446744069414584319 { fmt.Printf("xor_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584319\n", `^`, got) failed = true } if got := xor_uint64_18446744073709551615_ssa(4294967296); got != 18446744069414584319 { fmt.Printf("xor_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744069414584319\n", `^`, got) failed = true } if got := xor_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("xor_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("xor_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("xor_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { fmt.Printf("xor_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `^`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("add_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { fmt.Printf("add_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("add_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != 1 { fmt.Printf("add_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("add_int64 -9223372036854775808%s-4294967296 = %d, wanted 9223372032559808512\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("add_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(-1); got != 9223372036854775807 { fmt.Printf("add_int64 -9223372036854775808%s-1 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(-1); got != 9223372036854775807 { fmt.Printf("add_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(0); got != -9223372036854775808 { fmt.Printf("add_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(0); got != -9223372036854775808 { fmt.Printf("add_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775807 { fmt.Printf("add_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775807 { fmt.Printf("add_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("add_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("add_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -2 { fmt.Printf("add_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(9223372036854775806); got != -2 { fmt.Printf("add_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("add_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -1 { fmt.Printf("add_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != 1 { fmt.Printf("add_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != 1 { fmt.Printf("add_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 2 { fmt.Printf("add_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 2 { fmt.Printf("add_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 2\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(-4294967296); got != 9223372032559808513 { fmt.Printf("add_int64 -9223372036854775807%s-4294967296 = %d, wanted 9223372032559808513\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(-4294967296); got != 9223372032559808513 { fmt.Printf("add_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808513\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(-1); got != -9223372036854775808 { fmt.Printf("add_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(-1); got != -9223372036854775808 { fmt.Printf("add_int64 -1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(0); got != -9223372036854775807 { fmt.Printf("add_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(0); got != -9223372036854775807 { fmt.Printf("add_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775806 { fmt.Printf("add_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775806\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775806 { fmt.Printf("add_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775806\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("add_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("add_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("add_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(9223372036854775806); got != -1 { fmt.Printf("add_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("add_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(9223372036854775807); got != 0 { fmt.Printf("add_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(-9223372036854775808); got != 9223372032559808512 { fmt.Printf("add_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(-9223372036854775808); got != 9223372032559808512 { fmt.Printf("add_int64 -9223372036854775808%s-4294967296 = %d, wanted 9223372032559808512\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(-9223372036854775807); got != 9223372032559808513 { fmt.Printf("add_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808513\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(-9223372036854775807); got != 9223372032559808513 { fmt.Printf("add_int64 -9223372036854775807%s-4294967296 = %d, wanted 9223372032559808513\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(-4294967296); got != -8589934592 { fmt.Printf("add_int64 -4294967296%s-4294967296 = %d, wanted -8589934592\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(-4294967296); got != -8589934592 { fmt.Printf("add_int64 -4294967296%s-4294967296 = %d, wanted -8589934592\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(-1); got != -4294967297 { fmt.Printf("add_int64 -4294967296%s-1 = %d, wanted -4294967297\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(-1); got != -4294967297 { fmt.Printf("add_int64 -1%s-4294967296 = %d, wanted -4294967297\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(0); got != -4294967296 { fmt.Printf("add_int64 -4294967296%s0 = %d, wanted -4294967296\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(0); got != -4294967296 { fmt.Printf("add_int64 0%s-4294967296 = %d, wanted -4294967296\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(1); got != -4294967295 { fmt.Printf("add_int64 -4294967296%s1 = %d, wanted -4294967295\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(1); got != -4294967295 { fmt.Printf("add_int64 1%s-4294967296 = %d, wanted -4294967295\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("add_int64 -4294967296%s4294967296 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(4294967296); got != 0 { fmt.Printf("add_int64 4294967296%s-4294967296 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(9223372036854775806); got != 9223372032559808510 { fmt.Printf("add_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808510\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(9223372036854775806); got != 9223372032559808510 { fmt.Printf("add_int64 9223372036854775806%s-4294967296 = %d, wanted 9223372032559808510\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(9223372036854775807); got != 9223372032559808511 { fmt.Printf("add_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808511\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(9223372036854775807); got != 9223372032559808511 { fmt.Printf("add_int64 9223372036854775807%s-4294967296 = %d, wanted 9223372032559808511\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("add_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("add_int64 -9223372036854775808%s-1 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("add_int64 -1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("add_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(-4294967296); got != -4294967297 { fmt.Printf("add_int64 -1%s-4294967296 = %d, wanted -4294967297\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(-4294967296); got != -4294967297 { fmt.Printf("add_int64 -4294967296%s-1 = %d, wanted -4294967297\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(-1); got != -2 { fmt.Printf("add_int64 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(-1); got != -2 { fmt.Printf("add_int64 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(0); got != -1 { fmt.Printf("add_int64 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(0); got != -1 { fmt.Printf("add_int64 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(1); got != 0 { fmt.Printf("add_int64 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(1); got != 0 { fmt.Printf("add_int64 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(4294967296); got != 4294967295 { fmt.Printf("add_int64 -1%s4294967296 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(4294967296); got != 4294967295 { fmt.Printf("add_int64 4294967296%s-1 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(9223372036854775806); got != 9223372036854775805 { fmt.Printf("add_int64 -1%s9223372036854775806 = %d, wanted 9223372036854775805\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(9223372036854775806); got != 9223372036854775805 { fmt.Printf("add_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775805\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("add_int64 -1%s9223372036854775807 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("add_int64 9223372036854775807%s-1 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_0_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("add_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_int64_0_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("add_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_0_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("add_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_int64_0_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("add_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_0_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("add_int64 0%s-4294967296 = %d, wanted -4294967296\n", `+`, got) failed = true } if got := add_int64_0_ssa(-4294967296); got != -4294967296 { fmt.Printf("add_int64 -4294967296%s0 = %d, wanted -4294967296\n", `+`, got) failed = true } if got := add_0_int64_ssa(-1); got != -1 { fmt.Printf("add_int64 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int64_0_ssa(-1); got != -1 { fmt.Printf("add_int64 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_0_int64_ssa(0); got != 0 { fmt.Printf("add_int64 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_0_ssa(0); got != 0 { fmt.Printf("add_int64 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_int64_ssa(1); got != 1 { fmt.Printf("add_int64 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int64_0_ssa(1); got != 1 { fmt.Printf("add_int64 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("add_int64 0%s4294967296 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_int64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("add_int64 4294967296%s0 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_0_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("add_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_int64_0_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("add_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_0_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("add_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_int64_0_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("add_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_1_int64_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("add_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_int64_1_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("add_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_1_int64_ssa(-9223372036854775807); got != -9223372036854775806 { fmt.Printf("add_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775806\n", `+`, got) failed = true } if got := add_int64_1_ssa(-9223372036854775807); got != -9223372036854775806 { fmt.Printf("add_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775806\n", `+`, got) failed = true } if got := add_1_int64_ssa(-4294967296); got != -4294967295 { fmt.Printf("add_int64 1%s-4294967296 = %d, wanted -4294967295\n", `+`, got) failed = true } if got := add_int64_1_ssa(-4294967296); got != -4294967295 { fmt.Printf("add_int64 -4294967296%s1 = %d, wanted -4294967295\n", `+`, got) failed = true } if got := add_1_int64_ssa(-1); got != 0 { fmt.Printf("add_int64 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_1_ssa(-1); got != 0 { fmt.Printf("add_int64 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_1_int64_ssa(0); got != 1 { fmt.Printf("add_int64 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int64_1_ssa(0); got != 1 { fmt.Printf("add_int64 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_int64_ssa(1); got != 2 { fmt.Printf("add_int64 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int64_1_ssa(1); got != 2 { fmt.Printf("add_int64 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_int64_ssa(4294967296); got != 4294967297 { fmt.Printf("add_int64 1%s4294967296 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_int64_1_ssa(4294967296); got != 4294967297 { fmt.Printf("add_int64 4294967296%s1 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_1_int64_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("add_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_int64_1_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("add_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_1_int64_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("add_int64 1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_int64_1_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("add_int64 9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("add_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("add_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("add_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("add_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("add_int64 4294967296%s-4294967296 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(-4294967296); got != 0 { fmt.Printf("add_int64 -4294967296%s4294967296 = %d, wanted 0\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(-1); got != 4294967295 { fmt.Printf("add_int64 4294967296%s-1 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(-1); got != 4294967295 { fmt.Printf("add_int64 -1%s4294967296 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(0); got != 4294967296 { fmt.Printf("add_int64 4294967296%s0 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(0); got != 4294967296 { fmt.Printf("add_int64 0%s4294967296 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(1); got != 4294967297 { fmt.Printf("add_int64 4294967296%s1 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(1); got != 4294967297 { fmt.Printf("add_int64 1%s4294967296 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(4294967296); got != 8589934592 { fmt.Printf("add_int64 4294967296%s4294967296 = %d, wanted 8589934592\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(4294967296); got != 8589934592 { fmt.Printf("add_int64 4294967296%s4294967296 = %d, wanted 8589934592\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(9223372036854775806); got != -9223372032559808514 { fmt.Printf("add_int64 4294967296%s9223372036854775806 = %d, wanted -9223372032559808514\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(9223372036854775806); got != -9223372032559808514 { fmt.Printf("add_int64 9223372036854775806%s4294967296 = %d, wanted -9223372032559808514\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(9223372036854775807); got != -9223372032559808513 { fmt.Printf("add_int64 4294967296%s9223372036854775807 = %d, wanted -9223372032559808513\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(9223372036854775807); got != -9223372032559808513 { fmt.Printf("add_int64 9223372036854775807%s4294967296 = %d, wanted -9223372032559808513\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(-9223372036854775808); got != -2 { fmt.Printf("add_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(-9223372036854775808); got != -2 { fmt.Printf("add_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("add_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { fmt.Printf("add_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(-4294967296); got != 9223372032559808510 { fmt.Printf("add_int64 9223372036854775806%s-4294967296 = %d, wanted 9223372032559808510\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(-4294967296); got != 9223372032559808510 { fmt.Printf("add_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808510\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(-1); got != 9223372036854775805 { fmt.Printf("add_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775805\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(-1); got != 9223372036854775805 { fmt.Printf("add_int64 -1%s9223372036854775806 = %d, wanted 9223372036854775805\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(0); got != 9223372036854775806 { fmt.Printf("add_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(0); got != 9223372036854775806 { fmt.Printf("add_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("add_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(1); got != 9223372036854775807 { fmt.Printf("add_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(4294967296); got != -9223372032559808514 { fmt.Printf("add_int64 9223372036854775806%s4294967296 = %d, wanted -9223372032559808514\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(4294967296); got != -9223372032559808514 { fmt.Printf("add_int64 4294967296%s9223372036854775806 = %d, wanted -9223372032559808514\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(9223372036854775806); got != -4 { fmt.Printf("add_int64 9223372036854775806%s9223372036854775806 = %d, wanted -4\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(9223372036854775806); got != -4 { fmt.Printf("add_int64 9223372036854775806%s9223372036854775806 = %d, wanted -4\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(9223372036854775807); got != -3 { fmt.Printf("add_int64 9223372036854775806%s9223372036854775807 = %d, wanted -3\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(9223372036854775807); got != -3 { fmt.Printf("add_int64 9223372036854775807%s9223372036854775806 = %d, wanted -3\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(-9223372036854775808); got != -1 { fmt.Printf("add_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("add_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("add_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(-9223372036854775807); got != 0 { fmt.Printf("add_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(-4294967296); got != 9223372032559808511 { fmt.Printf("add_int64 9223372036854775807%s-4294967296 = %d, wanted 9223372032559808511\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(-4294967296); got != 9223372032559808511 { fmt.Printf("add_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808511\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(-1); got != 9223372036854775806 { fmt.Printf("add_int64 9223372036854775807%s-1 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(-1); got != 9223372036854775806 { fmt.Printf("add_int64 -1%s9223372036854775807 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(0); got != 9223372036854775807 { fmt.Printf("add_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(0); got != 9223372036854775807 { fmt.Printf("add_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(1); got != -9223372036854775808 { fmt.Printf("add_int64 9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(1); got != -9223372036854775808 { fmt.Printf("add_int64 1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(4294967296); got != -9223372032559808513 { fmt.Printf("add_int64 9223372036854775807%s4294967296 = %d, wanted -9223372032559808513\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(4294967296); got != -9223372032559808513 { fmt.Printf("add_int64 4294967296%s9223372036854775807 = %d, wanted -9223372032559808513\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(9223372036854775806); got != -3 { fmt.Printf("add_int64 9223372036854775807%s9223372036854775806 = %d, wanted -3\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(9223372036854775806); got != -3 { fmt.Printf("add_int64 9223372036854775806%s9223372036854775807 = %d, wanted -3\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(9223372036854775807); got != -2 { fmt.Printf("add_int64 9223372036854775807%s9223372036854775807 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(9223372036854775807); got != -2 { fmt.Printf("add_int64 9223372036854775807%s9223372036854775807 = %d, wanted -2\n", `+`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("sub_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { fmt.Printf("sub_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("sub_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != 1 { fmt.Printf("sub_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(-4294967296); got != -9223372032559808512 { fmt.Printf("sub_int64 -9223372036854775808%s-4294967296 = %d, wanted -9223372032559808512\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("sub_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(-1); got != -9223372036854775807 { fmt.Printf("sub_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(-1); got != 9223372036854775807 { fmt.Printf("sub_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(0); got != -9223372036854775808 { fmt.Printf("sub_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(0); got != -9223372036854775808 { fmt.Printf("sub_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("sub_int64 -9223372036854775808%s1 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775807 { fmt.Printf("sub_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(4294967296); got != 9223372032559808512 { fmt.Printf("sub_int64 -9223372036854775808%s4294967296 = %d, wanted 9223372032559808512\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("sub_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(9223372036854775806); got != 2 { fmt.Printf("sub_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(9223372036854775806); got != -2 { fmt.Printf("sub_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("sub_int64 -9223372036854775808%s9223372036854775807 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -1 { fmt.Printf("sub_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != 1 { fmt.Printf("sub_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("sub_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("sub_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 0 { fmt.Printf("sub_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(-4294967296); got != -9223372032559808511 { fmt.Printf("sub_int64 -9223372036854775807%s-4294967296 = %d, wanted -9223372032559808511\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(-4294967296); got != 9223372032559808511 { fmt.Printf("sub_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808511\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(-1); got != -9223372036854775806 { fmt.Printf("sub_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775806\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(-1); got != 9223372036854775806 { fmt.Printf("sub_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(0); got != -9223372036854775807 { fmt.Printf("sub_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(0); got != 9223372036854775807 { fmt.Printf("sub_int64 0%s-9223372036854775807 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775808 { fmt.Printf("sub_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775808 { fmt.Printf("sub_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(4294967296); got != 9223372032559808513 { fmt.Printf("sub_int64 -9223372036854775807%s4294967296 = %d, wanted 9223372032559808513\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(4294967296); got != -9223372032559808513 { fmt.Printf("sub_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808513\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(9223372036854775806); got != 3 { fmt.Printf("sub_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 3\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(9223372036854775806); got != -3 { fmt.Printf("sub_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -3\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(9223372036854775807); got != 2 { fmt.Printf("sub_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -2 { fmt.Printf("sub_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(-9223372036854775808); got != 9223372032559808512 { fmt.Printf("sub_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("sub_int64 -9223372036854775808%s-4294967296 = %d, wanted -9223372032559808512\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(-9223372036854775807); got != 9223372032559808511 { fmt.Printf("sub_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808511\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("sub_int64 -9223372036854775807%s-4294967296 = %d, wanted -9223372032559808511\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("sub_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(-4294967296); got != 0 { fmt.Printf("sub_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(-1); got != -4294967295 { fmt.Printf("sub_int64 -4294967296%s-1 = %d, wanted -4294967295\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(-1); got != 4294967295 { fmt.Printf("sub_int64 -1%s-4294967296 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(0); got != -4294967296 { fmt.Printf("sub_int64 -4294967296%s0 = %d, wanted -4294967296\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(0); got != 4294967296 { fmt.Printf("sub_int64 0%s-4294967296 = %d, wanted 4294967296\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(1); got != -4294967297 { fmt.Printf("sub_int64 -4294967296%s1 = %d, wanted -4294967297\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(1); got != 4294967297 { fmt.Printf("sub_int64 1%s-4294967296 = %d, wanted 4294967297\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(4294967296); got != -8589934592 { fmt.Printf("sub_int64 -4294967296%s4294967296 = %d, wanted -8589934592\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(4294967296); got != 8589934592 { fmt.Printf("sub_int64 4294967296%s-4294967296 = %d, wanted 8589934592\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(9223372036854775806); got != 9223372032559808514 { fmt.Printf("sub_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808514\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(9223372036854775806); got != -9223372032559808514 { fmt.Printf("sub_int64 9223372036854775806%s-4294967296 = %d, wanted -9223372032559808514\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(9223372036854775807); got != 9223372032559808513 { fmt.Printf("sub_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808513\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(9223372036854775807); got != -9223372032559808513 { fmt.Printf("sub_int64 9223372036854775807%s-4294967296 = %d, wanted -9223372032559808513\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("sub_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("sub_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(-9223372036854775807); got != 9223372036854775806 { fmt.Printf("sub_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(-9223372036854775807); got != -9223372036854775806 { fmt.Printf("sub_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775806\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(-4294967296); got != 4294967295 { fmt.Printf("sub_int64 -1%s-4294967296 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(-4294967296); got != -4294967295 { fmt.Printf("sub_int64 -4294967296%s-1 = %d, wanted -4294967295\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(-1); got != 0 { fmt.Printf("sub_int64 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(-1); got != 0 { fmt.Printf("sub_int64 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(0); got != -1 { fmt.Printf("sub_int64 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(0); got != 1 { fmt.Printf("sub_int64 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(1); got != -2 { fmt.Printf("sub_int64 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(1); got != 2 { fmt.Printf("sub_int64 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(4294967296); got != -4294967297 { fmt.Printf("sub_int64 -1%s4294967296 = %d, wanted -4294967297\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(4294967296); got != 4294967297 { fmt.Printf("sub_int64 4294967296%s-1 = %d, wanted 4294967297\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(9223372036854775806); got != -9223372036854775807 { fmt.Printf("sub_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("sub_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("sub_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("sub_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_0_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("sub_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_int64_0_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("sub_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_0_int64_ssa(-9223372036854775807); got != 9223372036854775807 { fmt.Printf("sub_int64 0%s-9223372036854775807 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_0_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("sub_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_0_int64_ssa(-4294967296); got != 4294967296 { fmt.Printf("sub_int64 0%s-4294967296 = %d, wanted 4294967296\n", `-`, got) failed = true } if got := sub_int64_0_ssa(-4294967296); got != -4294967296 { fmt.Printf("sub_int64 -4294967296%s0 = %d, wanted -4294967296\n", `-`, got) failed = true } if got := sub_0_int64_ssa(-1); got != 1 { fmt.Printf("sub_int64 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int64_0_ssa(-1); got != -1 { fmt.Printf("sub_int64 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_0_int64_ssa(0); got != 0 { fmt.Printf("sub_int64 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_0_ssa(0); got != 0 { fmt.Printf("sub_int64 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_int64_ssa(1); got != -1 { fmt.Printf("sub_int64 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int64_0_ssa(1); got != 1 { fmt.Printf("sub_int64 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_int64_ssa(4294967296); got != -4294967296 { fmt.Printf("sub_int64 0%s4294967296 = %d, wanted -4294967296\n", `-`, got) failed = true } if got := sub_int64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("sub_int64 4294967296%s0 = %d, wanted 4294967296\n", `-`, got) failed = true } if got := sub_0_int64_ssa(9223372036854775806); got != -9223372036854775806 { fmt.Printf("sub_int64 0%s9223372036854775806 = %d, wanted -9223372036854775806\n", `-`, got) failed = true } if got := sub_int64_0_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("sub_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `-`, got) failed = true } if got := sub_0_int64_ssa(9223372036854775807); got != -9223372036854775807 { fmt.Printf("sub_int64 0%s9223372036854775807 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_0_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("sub_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_1_int64_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("sub_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_1_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("sub_int64 -9223372036854775808%s1 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_1_int64_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("sub_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_int64_1_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("sub_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_1_int64_ssa(-4294967296); got != 4294967297 { fmt.Printf("sub_int64 1%s-4294967296 = %d, wanted 4294967297\n", `-`, got) failed = true } if got := sub_int64_1_ssa(-4294967296); got != -4294967297 { fmt.Printf("sub_int64 -4294967296%s1 = %d, wanted -4294967297\n", `-`, got) failed = true } if got := sub_1_int64_ssa(-1); got != 2 { fmt.Printf("sub_int64 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int64_1_ssa(-1); got != -2 { fmt.Printf("sub_int64 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_1_int64_ssa(0); got != 1 { fmt.Printf("sub_int64 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int64_1_ssa(0); got != -1 { fmt.Printf("sub_int64 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_1_int64_ssa(1); got != 0 { fmt.Printf("sub_int64 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_1_ssa(1); got != 0 { fmt.Printf("sub_int64 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_int64_ssa(4294967296); got != -4294967295 { fmt.Printf("sub_int64 1%s4294967296 = %d, wanted -4294967295\n", `-`, got) failed = true } if got := sub_int64_1_ssa(4294967296); got != 4294967295 { fmt.Printf("sub_int64 4294967296%s1 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_1_int64_ssa(9223372036854775806); got != -9223372036854775805 { fmt.Printf("sub_int64 1%s9223372036854775806 = %d, wanted -9223372036854775805\n", `-`, got) failed = true } if got := sub_int64_1_ssa(9223372036854775806); got != 9223372036854775805 { fmt.Printf("sub_int64 9223372036854775806%s1 = %d, wanted 9223372036854775805\n", `-`, got) failed = true } if got := sub_1_int64_ssa(9223372036854775807); got != -9223372036854775806 { fmt.Printf("sub_int64 1%s9223372036854775807 = %d, wanted -9223372036854775806\n", `-`, got) failed = true } if got := sub_int64_1_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("sub_int64 9223372036854775807%s1 = %d, wanted 9223372036854775806\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("sub_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(-9223372036854775808); got != 9223372032559808512 { fmt.Printf("sub_int64 -9223372036854775808%s4294967296 = %d, wanted 9223372032559808512\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(-9223372036854775807); got != -9223372032559808513 { fmt.Printf("sub_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808513\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(-9223372036854775807); got != 9223372032559808513 { fmt.Printf("sub_int64 -9223372036854775807%s4294967296 = %d, wanted 9223372032559808513\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(-4294967296); got != 8589934592 { fmt.Printf("sub_int64 4294967296%s-4294967296 = %d, wanted 8589934592\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(-4294967296); got != -8589934592 { fmt.Printf("sub_int64 -4294967296%s4294967296 = %d, wanted -8589934592\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(-1); got != 4294967297 { fmt.Printf("sub_int64 4294967296%s-1 = %d, wanted 4294967297\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(-1); got != -4294967297 { fmt.Printf("sub_int64 -1%s4294967296 = %d, wanted -4294967297\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(0); got != 4294967296 { fmt.Printf("sub_int64 4294967296%s0 = %d, wanted 4294967296\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(0); got != -4294967296 { fmt.Printf("sub_int64 0%s4294967296 = %d, wanted -4294967296\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(1); got != 4294967295 { fmt.Printf("sub_int64 4294967296%s1 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(1); got != -4294967295 { fmt.Printf("sub_int64 1%s4294967296 = %d, wanted -4294967295\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("sub_int64 4294967296%s4294967296 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("sub_int64 4294967296%s4294967296 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(9223372036854775806); got != -9223372032559808510 { fmt.Printf("sub_int64 4294967296%s9223372036854775806 = %d, wanted -9223372032559808510\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(9223372036854775806); got != 9223372032559808510 { fmt.Printf("sub_int64 9223372036854775806%s4294967296 = %d, wanted 9223372032559808510\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(9223372036854775807); got != -9223372032559808511 { fmt.Printf("sub_int64 4294967296%s9223372036854775807 = %d, wanted -9223372032559808511\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(9223372036854775807); got != 9223372032559808511 { fmt.Printf("sub_int64 9223372036854775807%s4294967296 = %d, wanted 9223372032559808511\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(-9223372036854775808); got != -2 { fmt.Printf("sub_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(-9223372036854775808); got != 2 { fmt.Printf("sub_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(-9223372036854775807); got != -3 { fmt.Printf("sub_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -3\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(-9223372036854775807); got != 3 { fmt.Printf("sub_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 3\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(-4294967296); got != -9223372032559808514 { fmt.Printf("sub_int64 9223372036854775806%s-4294967296 = %d, wanted -9223372032559808514\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(-4294967296); got != 9223372032559808514 { fmt.Printf("sub_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808514\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(-1); got != 9223372036854775807 { fmt.Printf("sub_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(-1); got != -9223372036854775807 { fmt.Printf("sub_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(0); got != 9223372036854775806 { fmt.Printf("sub_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(0); got != -9223372036854775806 { fmt.Printf("sub_int64 0%s9223372036854775806 = %d, wanted -9223372036854775806\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(1); got != 9223372036854775805 { fmt.Printf("sub_int64 9223372036854775806%s1 = %d, wanted 9223372036854775805\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(1); got != -9223372036854775805 { fmt.Printf("sub_int64 1%s9223372036854775806 = %d, wanted -9223372036854775805\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(4294967296); got != 9223372032559808510 { fmt.Printf("sub_int64 9223372036854775806%s4294967296 = %d, wanted 9223372032559808510\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(4294967296); got != -9223372032559808510 { fmt.Printf("sub_int64 4294967296%s9223372036854775806 = %d, wanted -9223372032559808510\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("sub_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(9223372036854775806); got != 0 { fmt.Printf("sub_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("sub_int64 9223372036854775806%s9223372036854775807 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(9223372036854775807); got != 1 { fmt.Printf("sub_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(-9223372036854775808); got != -1 { fmt.Printf("sub_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(-9223372036854775808); got != 1 { fmt.Printf("sub_int64 -9223372036854775808%s9223372036854775807 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(-9223372036854775807); got != -2 { fmt.Printf("sub_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(-9223372036854775807); got != 2 { fmt.Printf("sub_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(-4294967296); got != -9223372032559808513 { fmt.Printf("sub_int64 9223372036854775807%s-4294967296 = %d, wanted -9223372032559808513\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(-4294967296); got != 9223372032559808513 { fmt.Printf("sub_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808513\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(-1); got != -9223372036854775808 { fmt.Printf("sub_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(-1); got != -9223372036854775808 { fmt.Printf("sub_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(0); got != 9223372036854775807 { fmt.Printf("sub_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(0); got != -9223372036854775807 { fmt.Printf("sub_int64 0%s9223372036854775807 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(1); got != 9223372036854775806 { fmt.Printf("sub_int64 9223372036854775807%s1 = %d, wanted 9223372036854775806\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(1); got != -9223372036854775806 { fmt.Printf("sub_int64 1%s9223372036854775807 = %d, wanted -9223372036854775806\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(4294967296); got != 9223372032559808511 { fmt.Printf("sub_int64 9223372036854775807%s4294967296 = %d, wanted 9223372032559808511\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("sub_int64 4294967296%s9223372036854775807 = %d, wanted -9223372032559808511\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(9223372036854775806); got != 1 { fmt.Printf("sub_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(9223372036854775806); got != -1 { fmt.Printf("sub_int64 9223372036854775806%s9223372036854775807 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("sub_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(9223372036854775807); got != 0 { fmt.Printf("sub_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `-`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 1 { fmt.Printf("div_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 1 { fmt.Printf("div_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("div_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(-4294967296); got != 2147483648 { fmt.Printf("div_int64 -9223372036854775808%s-4294967296 = %d, wanted 2147483648\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 -4294967296%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(-1); got != -9223372036854775808 { fmt.Printf("div_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(-1); got != 0 { fmt.Printf("div_int64 -1%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(0); got != 0 { fmt.Printf("div_int64 0%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775808 { fmt.Printf("div_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775808\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(1); got != 0 { fmt.Printf("div_int64 1%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(4294967296); got != -2147483648 { fmt.Printf("div_int64 -9223372036854775808%s4294967296 = %d, wanted -2147483648\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("div_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("div_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("div_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != 1 { fmt.Printf("div_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("div_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 1 { fmt.Printf("div_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(-4294967296); got != 2147483647 { fmt.Printf("div_int64 -9223372036854775807%s-4294967296 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 -4294967296%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(-1); got != 9223372036854775807 { fmt.Printf("div_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(-1); got != 0 { fmt.Printf("div_int64 -1%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(0); got != 0 { fmt.Printf("div_int64 0%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775807 { fmt.Printf("div_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(1); got != 0 { fmt.Printf("div_int64 1%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(4294967296); got != -2147483647 { fmt.Printf("div_int64 -9223372036854775807%s4294967296 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(4294967296); got != 0 { fmt.Printf("div_int64 4294967296%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("div_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("div_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -1 { fmt.Printf("div_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 -4294967296%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(-9223372036854775808); got != 2147483648 { fmt.Printf("div_int64 -9223372036854775808%s-4294967296 = %d, wanted 2147483648\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 -4294967296%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(-9223372036854775807); got != 2147483647 { fmt.Printf("div_int64 -9223372036854775807%s-4294967296 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(-4294967296); got != 1 { fmt.Printf("div_int64 -4294967296%s-4294967296 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(-4294967296); got != 1 { fmt.Printf("div_int64 -4294967296%s-4294967296 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(-1); got != 4294967296 { fmt.Printf("div_int64 -4294967296%s-1 = %d, wanted 4294967296\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(-1); got != 0 { fmt.Printf("div_int64 -1%s-4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(0); got != 0 { fmt.Printf("div_int64 0%s-4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(1); got != -4294967296 { fmt.Printf("div_int64 -4294967296%s1 = %d, wanted -4294967296\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(1); got != 0 { fmt.Printf("div_int64 1%s-4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(4294967296); got != -1 { fmt.Printf("div_int64 -4294967296%s4294967296 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(4294967296); got != -1 { fmt.Printf("div_int64 4294967296%s-4294967296 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 -4294967296%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(9223372036854775806); got != -2147483647 { fmt.Printf("div_int64 9223372036854775806%s-4294967296 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 -4294967296%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(9223372036854775807); got != -2147483647 { fmt.Printf("div_int64 9223372036854775807%s-4294967296 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 -1%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("div_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 -1%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(-9223372036854775807); got != 9223372036854775807 { fmt.Printf("div_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 -1%s-4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(-4294967296); got != 4294967296 { fmt.Printf("div_int64 -4294967296%s-1 = %d, wanted 4294967296\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(-1); got != 1 { fmt.Printf("div_int64 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(-1); got != 1 { fmt.Printf("div_int64 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(0); got != 0 { fmt.Printf("div_int64 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(1); got != -1 { fmt.Printf("div_int64 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(1); got != -1 { fmt.Printf("div_int64 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(4294967296); got != 0 { fmt.Printf("div_int64 -1%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(4294967296); got != -4294967296 { fmt.Printf("div_int64 4294967296%s-1 = %d, wanted -4294967296\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 -1%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(9223372036854775806); got != -9223372036854775806 { fmt.Printf("div_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775806\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 -1%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(9223372036854775807); got != -9223372036854775807 { fmt.Printf("div_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `/`, got) failed = true } if got := div_0_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 0%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 0%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 0%s-4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(-1); got != 0 { fmt.Printf("div_int64 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(1); got != 0 { fmt.Printf("div_int64 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(4294967296); got != 0 { fmt.Printf("div_int64 0%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 0%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 0%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 1%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_1_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("div_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775808\n", `/`, got) failed = true } if got := div_1_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 1%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_1_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("div_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `/`, got) failed = true } if got := div_1_int64_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 1%s-4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_1_ssa(-4294967296); got != -4294967296 { fmt.Printf("div_int64 -4294967296%s1 = %d, wanted -4294967296\n", `/`, got) failed = true } if got := div_1_int64_ssa(-1); got != -1 { fmt.Printf("div_int64 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_1_ssa(-1); got != -1 { fmt.Printf("div_int64 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_1_ssa(0); got != 0 { fmt.Printf("div_int64 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int64_ssa(1); got != 1 { fmt.Printf("div_int64 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_1_ssa(1); got != 1 { fmt.Printf("div_int64 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_int64_ssa(4294967296); got != 0 { fmt.Printf("div_int64 1%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_1_ssa(4294967296); got != 4294967296 { fmt.Printf("div_int64 4294967296%s1 = %d, wanted 4294967296\n", `/`, got) failed = true } if got := div_1_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 1%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_1_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("div_int64 9223372036854775806%s1 = %d, wanted 9223372036854775806\n", `/`, got) failed = true } if got := div_1_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 1%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_1_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("div_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(-9223372036854775808); got != -2147483648 { fmt.Printf("div_int64 -9223372036854775808%s4294967296 = %d, wanted -2147483648\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 4294967296%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(-9223372036854775807); got != -2147483647 { fmt.Printf("div_int64 -9223372036854775807%s4294967296 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(-4294967296); got != -1 { fmt.Printf("div_int64 4294967296%s-4294967296 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(-4294967296); got != -1 { fmt.Printf("div_int64 -4294967296%s4294967296 = %d, wanted -1\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(-1); got != -4294967296 { fmt.Printf("div_int64 4294967296%s-1 = %d, wanted -4294967296\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(-1); got != 0 { fmt.Printf("div_int64 -1%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(0); got != 0 { fmt.Printf("div_int64 0%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(1); got != 4294967296 { fmt.Printf("div_int64 4294967296%s1 = %d, wanted 4294967296\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(1); got != 0 { fmt.Printf("div_int64 1%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(4294967296); got != 1 { fmt.Printf("div_int64 4294967296%s4294967296 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(4294967296); got != 1 { fmt.Printf("div_int64 4294967296%s4294967296 = %d, wanted 1\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 4294967296%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(9223372036854775806); got != 2147483647 { fmt.Printf("div_int64 9223372036854775806%s4294967296 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 4294967296%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(9223372036854775807); got != 2147483647 { fmt.Printf("div_int64 9223372036854775807%s4294967296 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(-9223372036854775808); got != -1 { fmt.Printf("div_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -1\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { fmt.Printf("div_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(-4294967296); got != -2147483647 { fmt.Printf("div_int64 9223372036854775806%s-4294967296 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 -4294967296%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(-1); got != -9223372036854775806 { fmt.Printf("div_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775806\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(-1); got != 0 { fmt.Printf("div_int64 -1%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(0); got != 0 { fmt.Printf("div_int64 0%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(1); got != 9223372036854775806 { fmt.Printf("div_int64 9223372036854775806%s1 = %d, wanted 9223372036854775806\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(1); got != 0 { fmt.Printf("div_int64 1%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(4294967296); got != 2147483647 { fmt.Printf("div_int64 9223372036854775806%s4294967296 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(4294967296); got != 0 { fmt.Printf("div_int64 4294967296%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(9223372036854775806); got != 1 { fmt.Printf("div_int64 9223372036854775806%s9223372036854775806 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(9223372036854775806); got != 1 { fmt.Printf("div_int64 9223372036854775806%s9223372036854775806 = %d, wanted 1\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 9223372036854775806%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(9223372036854775807); got != 1 { fmt.Printf("div_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("div_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("div_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(-9223372036854775807); got != -1 { fmt.Printf("div_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(-4294967296); got != -2147483647 { fmt.Printf("div_int64 9223372036854775807%s-4294967296 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 -4294967296%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(-1); got != -9223372036854775807 { fmt.Printf("div_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(-1); got != 0 { fmt.Printf("div_int64 -1%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(0); got != 0 { fmt.Printf("div_int64 0%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("div_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(1); got != 0 { fmt.Printf("div_int64 1%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(4294967296); got != 2147483647 { fmt.Printf("div_int64 9223372036854775807%s4294967296 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(4294967296); got != 0 { fmt.Printf("div_int64 4294967296%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(9223372036854775806); got != 1 { fmt.Printf("div_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 9223372036854775806%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("div_int64 9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(9223372036854775807); got != 1 { fmt.Printf("div_int64 9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 -4294967296%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(-1); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(-1); got != -9223372036854775808 { fmt.Printf("mul_int64 -1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775808 { fmt.Printf("mul_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(9223372036854775806); got != 0 { fmt.Printf("mul_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("mul_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("mul_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 1 { fmt.Printf("mul_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("mul_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(-4294967296); got != -4294967296 { fmt.Printf("mul_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(-1); got != 9223372036854775807 { fmt.Printf("mul_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(-1); got != 9223372036854775807 { fmt.Printf("mul_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 -9223372036854775807%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s-9223372036854775807 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775807 { fmt.Printf("mul_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775807 { fmt.Printf("mul_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("mul_int64 -9223372036854775807%s4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(4294967296); got != 4294967296 { fmt.Printf("mul_int64 4294967296%s-9223372036854775807 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mul_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("mul_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -1 { fmt.Printf("mul_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -4294967296%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(-9223372036854775807); got != -4294967296 { fmt.Printf("mul_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(-9223372036854775807); got != -4294967296 { fmt.Printf("mul_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(-1); got != 4294967296 { fmt.Printf("mul_int64 -4294967296%s-1 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(-1); got != 4294967296 { fmt.Printf("mul_int64 -1%s-4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 -4294967296%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(1); got != -4294967296 { fmt.Printf("mul_int64 -4294967296%s1 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(1); got != -4294967296 { fmt.Printf("mul_int64 1%s-4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 -4294967296%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 4294967296%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(9223372036854775806); got != 8589934592 { fmt.Printf("mul_int64 -4294967296%s9223372036854775806 = %d, wanted 8589934592\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(9223372036854775806); got != 8589934592 { fmt.Printf("mul_int64 9223372036854775806%s-4294967296 = %d, wanted 8589934592\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(9223372036854775807); got != 4294967296 { fmt.Printf("mul_int64 -4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(9223372036854775807); got != 4294967296 { fmt.Printf("mul_int64 9223372036854775807%s-4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 -1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(-9223372036854775807); got != 9223372036854775807 { fmt.Printf("mul_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(-9223372036854775807); got != 9223372036854775807 { fmt.Printf("mul_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(-4294967296); got != 4294967296 { fmt.Printf("mul_int64 -1%s-4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(-4294967296); got != 4294967296 { fmt.Printf("mul_int64 -4294967296%s-1 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(-1); got != 1 { fmt.Printf("mul_int64 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(-1); got != 1 { fmt.Printf("mul_int64 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(1); got != -1 { fmt.Printf("mul_int64 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(1); got != -1 { fmt.Printf("mul_int64 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(4294967296); got != -4294967296 { fmt.Printf("mul_int64 -1%s4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(4294967296); got != -4294967296 { fmt.Printf("mul_int64 4294967296%s-1 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(9223372036854775806); got != -9223372036854775806 { fmt.Printf("mul_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(9223372036854775806); got != -9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(9223372036854775807); got != -9223372036854775807 { fmt.Printf("mul_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(9223372036854775807); got != -9223372036854775807 { fmt.Printf("mul_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_0_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 0%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("mul_int64 0%s-9223372036854775807 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(-9223372036854775807); got != 0 { fmt.Printf("mul_int64 -9223372036854775807%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 0%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 -4294967296%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(-1); got != 0 { fmt.Printf("mul_int64 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(-1); got != 0 { fmt.Printf("mul_int64 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(1); got != 0 { fmt.Printf("mul_int64 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(1); got != 0 { fmt.Printf("mul_int64 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 0%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 4294967296%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("mul_int64 0%s9223372036854775806 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(9223372036854775806); got != 0 { fmt.Printf("mul_int64 9223372036854775806%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("mul_int64 0%s9223372036854775807 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(9223372036854775807); got != 0 { fmt.Printf("mul_int64 9223372036854775807%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_1_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_1_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("mul_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_1_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("mul_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_1_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("mul_int64 1%s-4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_1_ssa(-4294967296); got != -4294967296 { fmt.Printf("mul_int64 -4294967296%s1 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_1_int64_ssa(-1); got != -1 { fmt.Printf("mul_int64 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int64_1_ssa(-1); got != -1 { fmt.Printf("mul_int64 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_1_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_1_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int64_ssa(1); got != 1 { fmt.Printf("mul_int64 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int64_1_ssa(1); got != 1 { fmt.Printf("mul_int64 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("mul_int64 1%s4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_1_ssa(4294967296); got != 4294967296 { fmt.Printf("mul_int64 4294967296%s1 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_1_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mul_int64 1%s9223372036854775806 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_1_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s1 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_1_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("mul_int64 1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_1_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("mul_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(-9223372036854775807); got != 4294967296 { fmt.Printf("mul_int64 4294967296%s-9223372036854775807 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(-9223372036854775807); got != 4294967296 { fmt.Printf("mul_int64 -9223372036854775807%s4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 4294967296%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 -4294967296%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(-1); got != -4294967296 { fmt.Printf("mul_int64 4294967296%s-1 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(-1); got != -4294967296 { fmt.Printf("mul_int64 -1%s4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 4294967296%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(1); got != 4294967296 { fmt.Printf("mul_int64 4294967296%s1 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(1); got != 4294967296 { fmt.Printf("mul_int64 1%s4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 4294967296%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 4294967296%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(9223372036854775806); got != -8589934592 { fmt.Printf("mul_int64 4294967296%s9223372036854775806 = %d, wanted -8589934592\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(9223372036854775806); got != -8589934592 { fmt.Printf("mul_int64 9223372036854775806%s4294967296 = %d, wanted -8589934592\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(9223372036854775807); got != -4294967296 { fmt.Printf("mul_int64 4294967296%s9223372036854775807 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(9223372036854775807); got != -4294967296 { fmt.Printf("mul_int64 9223372036854775807%s4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(-9223372036854775807); got != 9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(-9223372036854775807); got != 9223372036854775806 { fmt.Printf("mul_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(-4294967296); got != 8589934592 { fmt.Printf("mul_int64 9223372036854775806%s-4294967296 = %d, wanted 8589934592\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(-4294967296); got != 8589934592 { fmt.Printf("mul_int64 -4294967296%s9223372036854775806 = %d, wanted 8589934592\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(-1); got != -9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(-1); got != -9223372036854775806 { fmt.Printf("mul_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 9223372036854775806%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s9223372036854775806 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(1); got != 9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s1 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(1); got != 9223372036854775806 { fmt.Printf("mul_int64 1%s9223372036854775806 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(4294967296); got != -8589934592 { fmt.Printf("mul_int64 9223372036854775806%s4294967296 = %d, wanted -8589934592\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(4294967296); got != -8589934592 { fmt.Printf("mul_int64 4294967296%s9223372036854775806 = %d, wanted -8589934592\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(9223372036854775806); got != 4 { fmt.Printf("mul_int64 9223372036854775806%s9223372036854775806 = %d, wanted 4\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(9223372036854775806); got != 4 { fmt.Printf("mul_int64 9223372036854775806%s9223372036854775806 = %d, wanted 4\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(9223372036854775807); got != -9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s9223372036854775807 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(9223372036854775807); got != -9223372036854775806 { fmt.Printf("mul_int64 9223372036854775807%s9223372036854775806 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("mul_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(-9223372036854775807); got != -1 { fmt.Printf("mul_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(-4294967296); got != 4294967296 { fmt.Printf("mul_int64 9223372036854775807%s-4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(-4294967296); got != 4294967296 { fmt.Printf("mul_int64 -4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(-1); got != -9223372036854775807 { fmt.Printf("mul_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(-1); got != -9223372036854775807 { fmt.Printf("mul_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 9223372036854775807%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s9223372036854775807 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("mul_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(1); got != 9223372036854775807 { fmt.Printf("mul_int64 1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(4294967296); got != -4294967296 { fmt.Printf("mul_int64 9223372036854775807%s4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(4294967296); got != -4294967296 { fmt.Printf("mul_int64 4294967296%s9223372036854775807 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(9223372036854775806); got != -9223372036854775806 { fmt.Printf("mul_int64 9223372036854775807%s9223372036854775806 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(9223372036854775806); got != -9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s9223372036854775807 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("mul_int64 9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(9223372036854775807); got != 1 { fmt.Printf("mul_int64 9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `*`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("mod_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("mod_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(-4294967296); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s-9223372036854775808 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(-1); got != -1 { fmt.Printf("mod_int64 -1%s-9223372036854775808 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s-9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(1); got != 1 { fmt.Printf("mod_int64 1%s-9223372036854775808 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(4294967296); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s-9223372036854775808 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -2 { fmt.Printf("mod_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mod_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 9223372036854775806\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("mod_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("mod_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("mod_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("mod_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(-4294967296); got != -4294967295 { fmt.Printf("mod_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967295\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(-4294967296); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(-1); got != -1 { fmt.Printf("mod_int64 -1%s-9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s-9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(1); got != 1 { fmt.Printf("mod_int64 1%s-9223372036854775807 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(4294967296); got != -4294967295 { fmt.Printf("mod_int64 -9223372036854775807%s4294967296 = %d, wanted -4294967295\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(4294967296); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s-9223372036854775807 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("mod_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mod_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(-9223372036854775808); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s-9223372036854775808 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(-9223372036854775807); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(-9223372036854775807); got != -4294967295 { fmt.Printf("mod_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967295\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 -4294967296%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(-1); got != -1 { fmt.Printf("mod_int64 -1%s-4294967296 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 -4294967296%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(1); got != 1 { fmt.Printf("mod_int64 1%s-4294967296 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 -4294967296%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 4294967296%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(9223372036854775806); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s9223372036854775806 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(9223372036854775806); got != 4294967294 { fmt.Printf("mod_int64 9223372036854775806%s-4294967296 = %d, wanted 4294967294\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(9223372036854775807); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s9223372036854775807 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(9223372036854775807); got != 4294967295 { fmt.Printf("mod_int64 9223372036854775807%s-4294967296 = %d, wanted 4294967295\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(-9223372036854775808); got != -1 { fmt.Printf("mod_int64 -1%s-9223372036854775808 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("mod_int64 -1%s-9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(-4294967296); got != -1 { fmt.Printf("mod_int64 -1%s-4294967296 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 -4294967296%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(-1); got != 0 { fmt.Printf("mod_int64 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(1); got != 0 { fmt.Printf("mod_int64 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(4294967296); got != -1 { fmt.Printf("mod_int64 -1%s4294967296 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 4294967296%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("mod_int64 -1%s9223372036854775806 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(9223372036854775806); got != 0 { fmt.Printf("mod_int64 9223372036854775806%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("mod_int64 -1%s9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 0%s-9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 0%s-9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 0%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 0%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("mod_int64 0%s9223372036854775806 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 0%s9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(-9223372036854775808); got != 1 { fmt.Printf("mod_int64 1%s-9223372036854775808 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_1_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("mod_int64 1%s-9223372036854775807 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_1_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(-4294967296); got != 1 { fmt.Printf("mod_int64 1%s-4294967296 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_1_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 -4294967296%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_1_ssa(-1); got != 0 { fmt.Printf("mod_int64 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_1_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_1_ssa(1); got != 0 { fmt.Printf("mod_int64 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(4294967296); got != 1 { fmt.Printf("mod_int64 1%s4294967296 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_1_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 4294967296%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(9223372036854775806); got != 1 { fmt.Printf("mod_int64 1%s9223372036854775806 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_1_ssa(9223372036854775806); got != 0 { fmt.Printf("mod_int64 9223372036854775806%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("mod_int64 1%s9223372036854775807 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_1_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(-9223372036854775808); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s-9223372036854775808 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(-9223372036854775807); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s-9223372036854775807 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(-9223372036854775807); got != -4294967295 { fmt.Printf("mod_int64 -9223372036854775807%s4294967296 = %d, wanted -4294967295\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 4294967296%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 -4294967296%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 4294967296%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(-1); got != -1 { fmt.Printf("mod_int64 -1%s4294967296 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 4294967296%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(1); got != 1 { fmt.Printf("mod_int64 1%s4294967296 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 4294967296%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 4294967296%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(9223372036854775806); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s9223372036854775806 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(9223372036854775806); got != 4294967294 { fmt.Printf("mod_int64 9223372036854775806%s4294967296 = %d, wanted 4294967294\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(9223372036854775807); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(9223372036854775807); got != 4294967295 { fmt.Printf("mod_int64 9223372036854775807%s4294967296 = %d, wanted 4294967295\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(-9223372036854775808); got != 9223372036854775806 { fmt.Printf("mod_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 9223372036854775806\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(-9223372036854775808); got != -2 { fmt.Printf("mod_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(-9223372036854775807); got != 9223372036854775806 { fmt.Printf("mod_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { fmt.Printf("mod_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(-4294967296); got != 4294967294 { fmt.Printf("mod_int64 9223372036854775806%s-4294967296 = %d, wanted 4294967294\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(-4294967296); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s9223372036854775806 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 9223372036854775806%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(-1); got != -1 { fmt.Printf("mod_int64 -1%s9223372036854775806 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s9223372036854775806 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 9223372036854775806%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(1); got != 1 { fmt.Printf("mod_int64 1%s9223372036854775806 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(4294967296); got != 4294967294 { fmt.Printf("mod_int64 9223372036854775806%s4294967296 = %d, wanted 4294967294\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(4294967296); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s9223372036854775806 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("mod_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(9223372036854775806); got != 0 { fmt.Printf("mod_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("mod_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775806\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(9223372036854775807); got != 1 { fmt.Printf("mod_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("mod_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("mod_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(-4294967296); got != 4294967295 { fmt.Printf("mod_int64 9223372036854775807%s-4294967296 = %d, wanted 4294967295\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(-4294967296); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s9223372036854775807 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(-1); got != -1 { fmt.Printf("mod_int64 -1%s9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(1); got != 1 { fmt.Printf("mod_int64 1%s9223372036854775807 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(4294967296); got != 4294967295 { fmt.Printf("mod_int64 9223372036854775807%s4294967296 = %d, wanted 4294967295\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(4294967296); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(9223372036854775806); got != 1 { fmt.Printf("mod_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mod_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775806\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(-4294967296); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-4294967296 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(-4294967296); got != -9223372036854775808 { fmt.Printf("and_int64 -4294967296%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(-1); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(-1); got != -9223372036854775808 { fmt.Printf("and_int64 -1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(0); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(0); got != 0 { fmt.Printf("and_int64 0%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(1); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(1); got != 0 { fmt.Printf("and_int64 1%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(4294967296); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("and_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(9223372036854775807); got != 0 { fmt.Printf("and_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("and_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("and_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(-4294967296); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775807%s-4294967296 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(-4294967296); got != -9223372036854775808 { fmt.Printf("and_int64 -4294967296%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(-1); got != -9223372036854775807 { fmt.Printf("and_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(-1); got != -9223372036854775807 { fmt.Printf("and_int64 -1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(0); got != 0 { fmt.Printf("and_int64 -9223372036854775807%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(0); got != 0 { fmt.Printf("and_int64 0%s-9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(1); got != 1 { fmt.Printf("and_int64 -9223372036854775807%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(1); got != 1 { fmt.Printf("and_int64 1%s-9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(4294967296); got != 0 { fmt.Printf("and_int64 -9223372036854775807%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(4294967296); got != 0 { fmt.Printf("and_int64 4294967296%s-9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("and_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(9223372036854775807); got != 1 { fmt.Printf("and_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -4294967296%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-4294967296 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("and_int64 -4294967296%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775807%s-4294967296 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("and_int64 -4294967296%s-4294967296 = %d, wanted -4294967296\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(-4294967296); got != -4294967296 { fmt.Printf("and_int64 -4294967296%s-4294967296 = %d, wanted -4294967296\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(-1); got != -4294967296 { fmt.Printf("and_int64 -4294967296%s-1 = %d, wanted -4294967296\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(-1); got != -4294967296 { fmt.Printf("and_int64 -1%s-4294967296 = %d, wanted -4294967296\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(0); got != 0 { fmt.Printf("and_int64 -4294967296%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(0); got != 0 { fmt.Printf("and_int64 0%s-4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(1); got != 0 { fmt.Printf("and_int64 -4294967296%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(1); got != 0 { fmt.Printf("and_int64 1%s-4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 -4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s-4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(9223372036854775806); got != 9223372032559808512 { fmt.Printf("and_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(9223372036854775806); got != 9223372032559808512 { fmt.Printf("and_int64 9223372036854775806%s-4294967296 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(9223372036854775807); got != 9223372032559808512 { fmt.Printf("and_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(9223372036854775807); got != 9223372032559808512 { fmt.Printf("and_int64 9223372036854775807%s-4294967296 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("and_int64 -1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("and_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("and_int64 -1%s-4294967296 = %d, wanted -4294967296\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(-4294967296); got != -4294967296 { fmt.Printf("and_int64 -4294967296%s-1 = %d, wanted -4294967296\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(-1); got != -1 { fmt.Printf("and_int64 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(-1); got != -1 { fmt.Printf("and_int64 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(0); got != 0 { fmt.Printf("and_int64 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(0); got != 0 { fmt.Printf("and_int64 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(1); got != 1 { fmt.Printf("and_int64 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(1); got != 1 { fmt.Printf("and_int64 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 -1%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s-1 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("and_int64 -1%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("and_int64 -1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("and_int64 9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `&`, got) failed = true } if got := and_0_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 0%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("and_int64 0%s-9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(-9223372036854775807); got != 0 { fmt.Printf("and_int64 -9223372036854775807%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(-4294967296); got != 0 { fmt.Printf("and_int64 0%s-4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(-4294967296); got != 0 { fmt.Printf("and_int64 -4294967296%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(-1); got != 0 { fmt.Printf("and_int64 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(-1); got != 0 { fmt.Printf("and_int64 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(0); got != 0 { fmt.Printf("and_int64 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(0); got != 0 { fmt.Printf("and_int64 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(1); got != 0 { fmt.Printf("and_int64 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(1); got != 0 { fmt.Printf("and_int64 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(4294967296); got != 0 { fmt.Printf("and_int64 0%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(4294967296); got != 0 { fmt.Printf("and_int64 4294967296%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 0%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 9223372036854775806%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("and_int64 0%s9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(9223372036854775807); got != 0 { fmt.Printf("and_int64 9223372036854775807%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 1%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_1_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("and_int64 1%s-9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_1_ssa(-9223372036854775807); got != 1 { fmt.Printf("and_int64 -9223372036854775807%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int64_ssa(-4294967296); got != 0 { fmt.Printf("and_int64 1%s-4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_1_ssa(-4294967296); got != 0 { fmt.Printf("and_int64 -4294967296%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int64_ssa(-1); got != 1 { fmt.Printf("and_int64 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_1_ssa(-1); got != 1 { fmt.Printf("and_int64 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int64_ssa(0); got != 0 { fmt.Printf("and_int64 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_1_ssa(0); got != 0 { fmt.Printf("and_int64 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int64_ssa(1); got != 1 { fmt.Printf("and_int64 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_1_ssa(1); got != 1 { fmt.Printf("and_int64 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int64_ssa(4294967296); got != 0 { fmt.Printf("and_int64 1%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_1_ssa(4294967296); got != 0 { fmt.Printf("and_int64 4294967296%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 1%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_1_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 9223372036854775806%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("and_int64 1%s9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_1_ssa(9223372036854775807); got != 1 { fmt.Printf("and_int64 9223372036854775807%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("and_int64 4294967296%s-9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(-9223372036854775807); got != 0 { fmt.Printf("and_int64 -9223372036854775807%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(-4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s-4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(-4294967296); got != 4294967296 { fmt.Printf("and_int64 -4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(-1); got != 4294967296 { fmt.Printf("and_int64 4294967296%s-1 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(-1); got != 4294967296 { fmt.Printf("and_int64 -1%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(0); got != 0 { fmt.Printf("and_int64 4294967296%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(0); got != 0 { fmt.Printf("and_int64 0%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(1); got != 0 { fmt.Printf("and_int64 4294967296%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(1); got != 0 { fmt.Printf("and_int64 1%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(9223372036854775806); got != 4294967296 { fmt.Printf("and_int64 4294967296%s9223372036854775806 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(9223372036854775806); got != 4294967296 { fmt.Printf("and_int64 9223372036854775806%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(9223372036854775807); got != 4294967296 { fmt.Printf("and_int64 4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(9223372036854775807); got != 4294967296 { fmt.Printf("and_int64 9223372036854775807%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("and_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(-9223372036854775807); got != 0 { fmt.Printf("and_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("and_int64 9223372036854775806%s-4294967296 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("and_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(-1); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(-1); got != 9223372036854775806 { fmt.Printf("and_int64 -1%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(0); got != 0 { fmt.Printf("and_int64 9223372036854775806%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(0); got != 0 { fmt.Printf("and_int64 0%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(1); got != 0 { fmt.Printf("and_int64 9223372036854775806%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(1); got != 0 { fmt.Printf("and_int64 1%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 9223372036854775806%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s9223372036854775806 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775806%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775806%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("and_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(-9223372036854775807); got != 1 { fmt.Printf("and_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("and_int64 9223372036854775807%s-4294967296 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("and_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(-1); got != 9223372036854775807 { fmt.Printf("and_int64 9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(-1); got != 9223372036854775807 { fmt.Printf("and_int64 -1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(0); got != 0 { fmt.Printf("and_int64 9223372036854775807%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(0); got != 0 { fmt.Printf("and_int64 0%s9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(1); got != 1 { fmt.Printf("and_int64 9223372036854775807%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(1); got != 1 { fmt.Printf("and_int64 1%s9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 9223372036854775807%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("and_int64 9223372036854775807%s9223372036854775807 = %d, wanted 9223372036854775807\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("and_int64 9223372036854775807%s9223372036854775807 = %d, wanted 9223372036854775807\n", `&`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("or_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("or_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 -9223372036854775808%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s-9223372036854775808 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 -9223372036854775808%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s-9223372036854775808 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(0); got != -9223372036854775808 { fmt.Printf("or_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(0); got != -9223372036854775808 { fmt.Printf("or_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775807 { fmt.Printf("or_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("or_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("or_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -2 { fmt.Printf("or_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(9223372036854775806); got != -2 { fmt.Printf("or_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(-4294967296); got != -4294967295 { fmt.Printf("or_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(-4294967296); got != -4294967295 { fmt.Printf("or_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 -9223372036854775807%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s-9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(0); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(0); got != -9223372036854775807 { fmt.Printf("or_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775807 { fmt.Printf("or_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("or_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("or_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("or_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(9223372036854775806); got != -1 { fmt.Printf("or_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(-9223372036854775808); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s-9223372036854775808 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(-9223372036854775808); got != -4294967296 { fmt.Printf("or_int64 -9223372036854775808%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(-9223372036854775807); got != -4294967295 { fmt.Printf("or_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(-9223372036854775807); got != -4294967295 { fmt.Printf("or_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 -4294967296%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s-4294967296 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(0); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s0 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(0); got != -4294967296 { fmt.Printf("or_int64 0%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(1); got != -4294967295 { fmt.Printf("or_int64 -4294967296%s1 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(1); got != -4294967295 { fmt.Printf("or_int64 1%s-4294967296 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(4294967296); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(4294967296); got != -4294967296 { fmt.Printf("or_int64 4294967296%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(9223372036854775806); got != -2 { fmt.Printf("or_int64 -4294967296%s9223372036854775806 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(9223372036854775806); got != -2 { fmt.Printf("or_int64 9223372036854775806%s-4294967296 = %d, wanted -2\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 -4294967296%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-4294967296 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(-9223372036854775808); got != -1 { fmt.Printf("or_int64 -1%s-9223372036854775808 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(-9223372036854775808); got != -1 { fmt.Printf("or_int64 -9223372036854775808%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("or_int64 -1%s-9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(-9223372036854775807); got != -1 { fmt.Printf("or_int64 -9223372036854775807%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(-4294967296); got != -1 { fmt.Printf("or_int64 -1%s-4294967296 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(-4294967296); got != -1 { fmt.Printf("or_int64 -4294967296%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(0); got != -1 { fmt.Printf("or_int64 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(0); got != -1 { fmt.Printf("or_int64 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(1); got != -1 { fmt.Printf("or_int64 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(1); got != -1 { fmt.Printf("or_int64 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(4294967296); got != -1 { fmt.Printf("or_int64 -1%s4294967296 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(4294967296); got != -1 { fmt.Printf("or_int64 4294967296%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("or_int64 -1%s9223372036854775806 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(9223372036854775806); got != -1 { fmt.Printf("or_int64 9223372036854775806%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 -1%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("or_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `|`, got) failed = true } if got := or_int64_0_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("or_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `|`, got) failed = true } if got := or_0_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_0_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_0_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 0%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_0_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s0 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_0_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_0_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int64_ssa(0); got != 0 { fmt.Printf("or_int64 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_int64_0_ssa(0); got != 0 { fmt.Printf("or_int64 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_int64_ssa(1); got != 1 { fmt.Printf("or_int64 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int64_0_ssa(1); got != 1 { fmt.Printf("or_int64 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("or_int64 0%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_int64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("or_int64 4294967296%s0 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_0_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("or_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_int64_0_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("or_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_0_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_0_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_1_int64_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("or_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_1_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_1_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_1_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_1_int64_ssa(-4294967296); got != -4294967295 { fmt.Printf("or_int64 1%s-4294967296 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_int64_1_ssa(-4294967296); got != -4294967295 { fmt.Printf("or_int64 -4294967296%s1 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_1_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_1_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_1_int64_ssa(0); got != 1 { fmt.Printf("or_int64 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int64_1_ssa(0); got != 1 { fmt.Printf("or_int64 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int64_ssa(1); got != 1 { fmt.Printf("or_int64 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int64_1_ssa(1); got != 1 { fmt.Printf("or_int64 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int64_ssa(4294967296); got != 4294967297 { fmt.Printf("or_int64 1%s4294967296 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_int64_1_ssa(4294967296); got != 4294967297 { fmt.Printf("or_int64 4294967296%s1 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_1_int64_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("or_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_1_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_1_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_1_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("or_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("or_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("or_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("or_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 4294967296%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 4294967296%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s4294967296 = %d, wanted -1\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(0); got != 4294967296 { fmt.Printf("or_int64 4294967296%s0 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(0); got != 4294967296 { fmt.Printf("or_int64 0%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(1); got != 4294967297 { fmt.Printf("or_int64 4294967296%s1 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(1); got != 4294967297 { fmt.Printf("or_int64 1%s4294967296 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("or_int64 4294967296%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(4294967296); got != 4294967296 { fmt.Printf("or_int64 4294967296%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("or_int64 4294967296%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("or_int64 9223372036854775806%s4294967296 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 4294967296%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s4294967296 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(-9223372036854775808); got != -2 { fmt.Printf("or_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(-9223372036854775808); got != -2 { fmt.Printf("or_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("or_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { fmt.Printf("or_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(-4294967296); got != -2 { fmt.Printf("or_int64 9223372036854775806%s-4294967296 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(-4294967296); got != -2 { fmt.Printf("or_int64 -4294967296%s9223372036854775806 = %d, wanted -2\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 9223372036854775806%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s9223372036854775806 = %d, wanted -1\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(0); got != 9223372036854775806 { fmt.Printf("or_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(0); got != 9223372036854775806 { fmt.Printf("or_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(1); got != 9223372036854775807 { fmt.Printf("or_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(4294967296); got != 9223372036854775806 { fmt.Printf("or_int64 9223372036854775806%s4294967296 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(4294967296); got != 9223372036854775806 { fmt.Printf("or_int64 4294967296%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("or_int64 9223372036854775806%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("or_int64 9223372036854775806%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(-9223372036854775808); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("or_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(-9223372036854775807); got != -1 { fmt.Printf("or_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(-4294967296); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-4294967296 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(-4294967296); got != -1 { fmt.Printf("or_int64 -4294967296%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(0); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(0); got != 9223372036854775807 { fmt.Printf("or_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(1); got != 9223372036854775807 { fmt.Printf("or_int64 1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(4294967296); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s4294967296 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(4294967296); got != 9223372036854775807 { fmt.Printf("or_int64 4294967296%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("xor_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { fmt.Printf("xor_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("xor_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != 1 { fmt.Printf("xor_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("xor_int64 -9223372036854775808%s-4294967296 = %d, wanted 9223372032559808512\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("xor_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(-1); got != 9223372036854775807 { fmt.Printf("xor_int64 -9223372036854775808%s-1 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(-1); got != 9223372036854775807 { fmt.Printf("xor_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(0); got != -9223372036854775808 { fmt.Printf("xor_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(0); got != -9223372036854775808 { fmt.Printf("xor_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775807 { fmt.Printf("xor_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775807 { fmt.Printf("xor_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("xor_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("xor_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -2 { fmt.Printf("xor_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(9223372036854775806); got != -2 { fmt.Printf("xor_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("xor_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -1 { fmt.Printf("xor_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != 1 { fmt.Printf("xor_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != 1 { fmt.Printf("xor_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("xor_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 0 { fmt.Printf("xor_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(-4294967296); got != 9223372032559808513 { fmt.Printf("xor_int64 -9223372036854775807%s-4294967296 = %d, wanted 9223372032559808513\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(-4294967296); got != 9223372032559808513 { fmt.Printf("xor_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808513\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(-1); got != 9223372036854775806 { fmt.Printf("xor_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(-1); got != 9223372036854775806 { fmt.Printf("xor_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(0); got != -9223372036854775807 { fmt.Printf("xor_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(0); got != -9223372036854775807 { fmt.Printf("xor_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775808 { fmt.Printf("xor_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775808 { fmt.Printf("xor_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("xor_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("xor_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("xor_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(9223372036854775806); got != -1 { fmt.Printf("xor_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(9223372036854775807); got != -2 { fmt.Printf("xor_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -2 { fmt.Printf("xor_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(-9223372036854775808); got != 9223372032559808512 { fmt.Printf("xor_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(-9223372036854775808); got != 9223372032559808512 { fmt.Printf("xor_int64 -9223372036854775808%s-4294967296 = %d, wanted 9223372032559808512\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(-9223372036854775807); got != 9223372032559808513 { fmt.Printf("xor_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808513\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(-9223372036854775807); got != 9223372032559808513 { fmt.Printf("xor_int64 -9223372036854775807%s-4294967296 = %d, wanted 9223372032559808513\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("xor_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(-4294967296); got != 0 { fmt.Printf("xor_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(-1); got != 4294967295 { fmt.Printf("xor_int64 -4294967296%s-1 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(-1); got != 4294967295 { fmt.Printf("xor_int64 -1%s-4294967296 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(0); got != -4294967296 { fmt.Printf("xor_int64 -4294967296%s0 = %d, wanted -4294967296\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(0); got != -4294967296 { fmt.Printf("xor_int64 0%s-4294967296 = %d, wanted -4294967296\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(1); got != -4294967295 { fmt.Printf("xor_int64 -4294967296%s1 = %d, wanted -4294967295\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(1); got != -4294967295 { fmt.Printf("xor_int64 1%s-4294967296 = %d, wanted -4294967295\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(4294967296); got != -8589934592 { fmt.Printf("xor_int64 -4294967296%s4294967296 = %d, wanted -8589934592\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(4294967296); got != -8589934592 { fmt.Printf("xor_int64 4294967296%s-4294967296 = %d, wanted -8589934592\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(9223372036854775806); got != -9223372032559808514 { fmt.Printf("xor_int64 -4294967296%s9223372036854775806 = %d, wanted -9223372032559808514\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(9223372036854775806); got != -9223372032559808514 { fmt.Printf("xor_int64 9223372036854775806%s-4294967296 = %d, wanted -9223372032559808514\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(9223372036854775807); got != -9223372032559808513 { fmt.Printf("xor_int64 -4294967296%s9223372036854775807 = %d, wanted -9223372032559808513\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(9223372036854775807); got != -9223372032559808513 { fmt.Printf("xor_int64 9223372036854775807%s-4294967296 = %d, wanted -9223372032559808513\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("xor_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("xor_int64 -9223372036854775808%s-1 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(-9223372036854775807); got != 9223372036854775806 { fmt.Printf("xor_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(-9223372036854775807); got != 9223372036854775806 { fmt.Printf("xor_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(-4294967296); got != 4294967295 { fmt.Printf("xor_int64 -1%s-4294967296 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(-4294967296); got != 4294967295 { fmt.Printf("xor_int64 -4294967296%s-1 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(-1); got != 0 { fmt.Printf("xor_int64 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(-1); got != 0 { fmt.Printf("xor_int64 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(0); got != -1 { fmt.Printf("xor_int64 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(0); got != -1 { fmt.Printf("xor_int64 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(1); got != -2 { fmt.Printf("xor_int64 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(1); got != -2 { fmt.Printf("xor_int64 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(4294967296); got != -4294967297 { fmt.Printf("xor_int64 -1%s4294967296 = %d, wanted -4294967297\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(4294967296); got != -4294967297 { fmt.Printf("xor_int64 4294967296%s-1 = %d, wanted -4294967297\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(9223372036854775806); got != -9223372036854775807 { fmt.Printf("xor_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(9223372036854775806); got != -9223372036854775807 { fmt.Printf("xor_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("xor_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("xor_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_0_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("xor_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_int64_0_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("xor_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_0_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("xor_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_0_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("xor_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_0_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("xor_int64 0%s-4294967296 = %d, wanted -4294967296\n", `^`, got) failed = true } if got := xor_int64_0_ssa(-4294967296); got != -4294967296 { fmt.Printf("xor_int64 -4294967296%s0 = %d, wanted -4294967296\n", `^`, got) failed = true } if got := xor_0_int64_ssa(-1); got != -1 { fmt.Printf("xor_int64 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int64_0_ssa(-1); got != -1 { fmt.Printf("xor_int64 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_0_int64_ssa(0); got != 0 { fmt.Printf("xor_int64 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_0_ssa(0); got != 0 { fmt.Printf("xor_int64 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_int64_ssa(1); got != 1 { fmt.Printf("xor_int64 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int64_0_ssa(1); got != 1 { fmt.Printf("xor_int64 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("xor_int64 0%s4294967296 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_int64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("xor_int64 4294967296%s0 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_0_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("xor_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_int64_0_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("xor_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_0_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("xor_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_0_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("xor_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_1_int64_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("xor_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_1_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("xor_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_1_int64_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("xor_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_int64_1_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("xor_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_1_int64_ssa(-4294967296); got != -4294967295 { fmt.Printf("xor_int64 1%s-4294967296 = %d, wanted -4294967295\n", `^`, got) failed = true } if got := xor_int64_1_ssa(-4294967296); got != -4294967295 { fmt.Printf("xor_int64 -4294967296%s1 = %d, wanted -4294967295\n", `^`, got) failed = true } if got := xor_1_int64_ssa(-1); got != -2 { fmt.Printf("xor_int64 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int64_1_ssa(-1); got != -2 { fmt.Printf("xor_int64 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_1_int64_ssa(0); got != 1 { fmt.Printf("xor_int64 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int64_1_ssa(0); got != 1 { fmt.Printf("xor_int64 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_int64_ssa(1); got != 0 { fmt.Printf("xor_int64 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_1_ssa(1); got != 0 { fmt.Printf("xor_int64 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_int64_ssa(4294967296); got != 4294967297 { fmt.Printf("xor_int64 1%s4294967296 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_int64_1_ssa(4294967296); got != 4294967297 { fmt.Printf("xor_int64 4294967296%s1 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_1_int64_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("xor_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_1_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("xor_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_1_int64_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("xor_int64 1%s9223372036854775807 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_int64_1_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("xor_int64 9223372036854775807%s1 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("xor_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("xor_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("xor_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("xor_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(-4294967296); got != -8589934592 { fmt.Printf("xor_int64 4294967296%s-4294967296 = %d, wanted -8589934592\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(-4294967296); got != -8589934592 { fmt.Printf("xor_int64 -4294967296%s4294967296 = %d, wanted -8589934592\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(-1); got != -4294967297 { fmt.Printf("xor_int64 4294967296%s-1 = %d, wanted -4294967297\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(-1); got != -4294967297 { fmt.Printf("xor_int64 -1%s4294967296 = %d, wanted -4294967297\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(0); got != 4294967296 { fmt.Printf("xor_int64 4294967296%s0 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(0); got != 4294967296 { fmt.Printf("xor_int64 0%s4294967296 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(1); got != 4294967297 { fmt.Printf("xor_int64 4294967296%s1 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(1); got != 4294967297 { fmt.Printf("xor_int64 1%s4294967296 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("xor_int64 4294967296%s4294967296 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("xor_int64 4294967296%s4294967296 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(9223372036854775806); got != 9223372032559808510 { fmt.Printf("xor_int64 4294967296%s9223372036854775806 = %d, wanted 9223372032559808510\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(9223372036854775806); got != 9223372032559808510 { fmt.Printf("xor_int64 9223372036854775806%s4294967296 = %d, wanted 9223372032559808510\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(9223372036854775807); got != 9223372032559808511 { fmt.Printf("xor_int64 4294967296%s9223372036854775807 = %d, wanted 9223372032559808511\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(9223372036854775807); got != 9223372032559808511 { fmt.Printf("xor_int64 9223372036854775807%s4294967296 = %d, wanted 9223372032559808511\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(-9223372036854775808); got != -2 { fmt.Printf("xor_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(-9223372036854775808); got != -2 { fmt.Printf("xor_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("xor_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { fmt.Printf("xor_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(-4294967296); got != -9223372032559808514 { fmt.Printf("xor_int64 9223372036854775806%s-4294967296 = %d, wanted -9223372032559808514\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(-4294967296); got != -9223372032559808514 { fmt.Printf("xor_int64 -4294967296%s9223372036854775806 = %d, wanted -9223372032559808514\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(-1); got != -9223372036854775807 { fmt.Printf("xor_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(-1); got != -9223372036854775807 { fmt.Printf("xor_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(0); got != 9223372036854775806 { fmt.Printf("xor_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(0); got != 9223372036854775806 { fmt.Printf("xor_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("xor_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(1); got != 9223372036854775807 { fmt.Printf("xor_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(4294967296); got != 9223372032559808510 { fmt.Printf("xor_int64 9223372036854775806%s4294967296 = %d, wanted 9223372032559808510\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(4294967296); got != 9223372032559808510 { fmt.Printf("xor_int64 4294967296%s9223372036854775806 = %d, wanted 9223372032559808510\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("xor_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(9223372036854775806); got != 0 { fmt.Printf("xor_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("xor_int64 9223372036854775806%s9223372036854775807 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(9223372036854775807); got != 1 { fmt.Printf("xor_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(-9223372036854775808); got != -1 { fmt.Printf("xor_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("xor_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(-9223372036854775807); got != -2 { fmt.Printf("xor_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(-9223372036854775807); got != -2 { fmt.Printf("xor_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(-4294967296); got != -9223372032559808513 { fmt.Printf("xor_int64 9223372036854775807%s-4294967296 = %d, wanted -9223372032559808513\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(-4294967296); got != -9223372032559808513 { fmt.Printf("xor_int64 -4294967296%s9223372036854775807 = %d, wanted -9223372032559808513\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(-1); got != -9223372036854775808 { fmt.Printf("xor_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(-1); got != -9223372036854775808 { fmt.Printf("xor_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(0); got != 9223372036854775807 { fmt.Printf("xor_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(0); got != 9223372036854775807 { fmt.Printf("xor_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(1); got != 9223372036854775806 { fmt.Printf("xor_int64 9223372036854775807%s1 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(1); got != 9223372036854775806 { fmt.Printf("xor_int64 1%s9223372036854775807 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(4294967296); got != 9223372032559808511 { fmt.Printf("xor_int64 9223372036854775807%s4294967296 = %d, wanted 9223372032559808511\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(4294967296); got != 9223372032559808511 { fmt.Printf("xor_int64 4294967296%s9223372036854775807 = %d, wanted 9223372032559808511\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(9223372036854775806); got != 1 { fmt.Printf("xor_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(9223372036854775806); got != 1 { fmt.Printf("xor_int64 9223372036854775806%s9223372036854775807 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("xor_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(9223372036854775807); got != 0 { fmt.Printf("xor_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `^`, got) failed = true } if got := add_0_uint32_ssa(0); got != 0 { fmt.Printf("add_uint32 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint32_0_ssa(0); got != 0 { fmt.Printf("add_uint32 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_uint32_ssa(1); got != 1 { fmt.Printf("add_uint32 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint32_0_ssa(1); got != 1 { fmt.Printf("add_uint32 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("add_uint32 0%s4294967295 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_uint32_0_ssa(4294967295); got != 4294967295 { fmt.Printf("add_uint32 4294967295%s0 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_1_uint32_ssa(0); got != 1 { fmt.Printf("add_uint32 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint32_1_ssa(0); got != 1 { fmt.Printf("add_uint32 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_uint32_ssa(1); got != 2 { fmt.Printf("add_uint32 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_uint32_1_ssa(1); got != 2 { fmt.Printf("add_uint32 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_uint32_ssa(4294967295); got != 0 { fmt.Printf("add_uint32 1%s4294967295 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint32_1_ssa(4294967295); got != 0 { fmt.Printf("add_uint32 4294967295%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_4294967295_uint32_ssa(0); got != 4294967295 { fmt.Printf("add_uint32 4294967295%s0 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_uint32_4294967295_ssa(0); got != 4294967295 { fmt.Printf("add_uint32 0%s4294967295 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_4294967295_uint32_ssa(1); got != 0 { fmt.Printf("add_uint32 4294967295%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint32_4294967295_ssa(1); got != 0 { fmt.Printf("add_uint32 1%s4294967295 = %d, wanted 0\n", `+`, got) failed = true } if got := add_4294967295_uint32_ssa(4294967295); got != 4294967294 { fmt.Printf("add_uint32 4294967295%s4294967295 = %d, wanted 4294967294\n", `+`, got) failed = true } if got := add_uint32_4294967295_ssa(4294967295); got != 4294967294 { fmt.Printf("add_uint32 4294967295%s4294967295 = %d, wanted 4294967294\n", `+`, got) failed = true } if got := sub_0_uint32_ssa(0); got != 0 { fmt.Printf("sub_uint32 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint32_0_ssa(0); got != 0 { fmt.Printf("sub_uint32 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_uint32_ssa(1); got != 4294967295 { fmt.Printf("sub_uint32 0%s1 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_uint32_0_ssa(1); got != 1 { fmt.Printf("sub_uint32 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_uint32_ssa(4294967295); got != 1 { fmt.Printf("sub_uint32 0%s4294967295 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint32_0_ssa(4294967295); got != 4294967295 { fmt.Printf("sub_uint32 4294967295%s0 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_1_uint32_ssa(0); got != 1 { fmt.Printf("sub_uint32 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint32_1_ssa(0); got != 4294967295 { fmt.Printf("sub_uint32 0%s1 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_1_uint32_ssa(1); got != 0 { fmt.Printf("sub_uint32 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint32_1_ssa(1); got != 0 { fmt.Printf("sub_uint32 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_uint32_ssa(4294967295); got != 2 { fmt.Printf("sub_uint32 1%s4294967295 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_uint32_1_ssa(4294967295); got != 4294967294 { fmt.Printf("sub_uint32 4294967295%s1 = %d, wanted 4294967294\n", `-`, got) failed = true } if got := sub_4294967295_uint32_ssa(0); got != 4294967295 { fmt.Printf("sub_uint32 4294967295%s0 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_uint32_4294967295_ssa(0); got != 1 { fmt.Printf("sub_uint32 0%s4294967295 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_4294967295_uint32_ssa(1); got != 4294967294 { fmt.Printf("sub_uint32 4294967295%s1 = %d, wanted 4294967294\n", `-`, got) failed = true } if got := sub_uint32_4294967295_ssa(1); got != 2 { fmt.Printf("sub_uint32 1%s4294967295 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_4294967295_uint32_ssa(4294967295); got != 0 { fmt.Printf("sub_uint32 4294967295%s4294967295 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint32_4294967295_ssa(4294967295); got != 0 { fmt.Printf("sub_uint32 4294967295%s4294967295 = %d, wanted 0\n", `-`, got) failed = true } if got := div_0_uint32_ssa(1); got != 0 { fmt.Printf("div_uint32 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_uint32_ssa(4294967295); got != 0 { fmt.Printf("div_uint32 0%s4294967295 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint32_1_ssa(0); got != 0 { fmt.Printf("div_uint32 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_uint32_ssa(1); got != 1 { fmt.Printf("div_uint32 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint32_1_ssa(1); got != 1 { fmt.Printf("div_uint32 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_uint32_ssa(4294967295); got != 0 { fmt.Printf("div_uint32 1%s4294967295 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint32_1_ssa(4294967295); got != 4294967295 { fmt.Printf("div_uint32 4294967295%s1 = %d, wanted 4294967295\n", `/`, got) failed = true } if got := div_uint32_4294967295_ssa(0); got != 0 { fmt.Printf("div_uint32 0%s4294967295 = %d, wanted 0\n", `/`, got) failed = true } if got := div_4294967295_uint32_ssa(1); got != 4294967295 { fmt.Printf("div_uint32 4294967295%s1 = %d, wanted 4294967295\n", `/`, got) failed = true } if got := div_uint32_4294967295_ssa(1); got != 0 { fmt.Printf("div_uint32 1%s4294967295 = %d, wanted 0\n", `/`, got) failed = true } if got := div_4294967295_uint32_ssa(4294967295); got != 1 { fmt.Printf("div_uint32 4294967295%s4294967295 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint32_4294967295_ssa(4294967295); got != 1 { fmt.Printf("div_uint32 4294967295%s4294967295 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_0_uint32_ssa(0); got != 0 { fmt.Printf("mul_uint32 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint32_0_ssa(0); got != 0 { fmt.Printf("mul_uint32 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint32_ssa(1); got != 0 { fmt.Printf("mul_uint32 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint32_0_ssa(1); got != 0 { fmt.Printf("mul_uint32 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint32_ssa(4294967295); got != 0 { fmt.Printf("mul_uint32 0%s4294967295 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint32_0_ssa(4294967295); got != 0 { fmt.Printf("mul_uint32 4294967295%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint32_ssa(0); got != 0 { fmt.Printf("mul_uint32 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint32_1_ssa(0); got != 0 { fmt.Printf("mul_uint32 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint32_ssa(1); got != 1 { fmt.Printf("mul_uint32 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint32_1_ssa(1); got != 1 { fmt.Printf("mul_uint32 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("mul_uint32 1%s4294967295 = %d, wanted 4294967295\n", `*`, got) failed = true } if got := mul_uint32_1_ssa(4294967295); got != 4294967295 { fmt.Printf("mul_uint32 4294967295%s1 = %d, wanted 4294967295\n", `*`, got) failed = true } if got := mul_4294967295_uint32_ssa(0); got != 0 { fmt.Printf("mul_uint32 4294967295%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint32_4294967295_ssa(0); got != 0 { fmt.Printf("mul_uint32 0%s4294967295 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967295_uint32_ssa(1); got != 4294967295 { fmt.Printf("mul_uint32 4294967295%s1 = %d, wanted 4294967295\n", `*`, got) failed = true } if got := mul_uint32_4294967295_ssa(1); got != 4294967295 { fmt.Printf("mul_uint32 1%s4294967295 = %d, wanted 4294967295\n", `*`, got) failed = true } if got := mul_4294967295_uint32_ssa(4294967295); got != 1 { fmt.Printf("mul_uint32 4294967295%s4294967295 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint32_4294967295_ssa(4294967295); got != 1 { fmt.Printf("mul_uint32 4294967295%s4294967295 = %d, wanted 1\n", `*`, got) failed = true } if got := lsh_0_uint32_ssa(0); got != 0 { fmt.Printf("lsh_uint32 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint32_0_ssa(0); got != 0 { fmt.Printf("lsh_uint32 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_0_uint32_ssa(1); got != 0 { fmt.Printf("lsh_uint32 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint32_0_ssa(1); got != 1 { fmt.Printf("lsh_uint32 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_0_uint32_ssa(4294967295); got != 0 { fmt.Printf("lsh_uint32 0%s4294967295 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint32_0_ssa(4294967295); got != 4294967295 { fmt.Printf("lsh_uint32 4294967295%s0 = %d, wanted 4294967295\n", `<<`, got) failed = true } if got := lsh_1_uint32_ssa(0); got != 1 { fmt.Printf("lsh_uint32 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_uint32_1_ssa(0); got != 0 { fmt.Printf("lsh_uint32 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_1_uint32_ssa(1); got != 2 { fmt.Printf("lsh_uint32 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_uint32_1_ssa(1); got != 2 { fmt.Printf("lsh_uint32 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_1_uint32_ssa(4294967295); got != 0 { fmt.Printf("lsh_uint32 1%s4294967295 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint32_1_ssa(4294967295); got != 4294967294 { fmt.Printf("lsh_uint32 4294967295%s1 = %d, wanted 4294967294\n", `<<`, got) failed = true } if got := lsh_4294967295_uint32_ssa(0); got != 4294967295 { fmt.Printf("lsh_uint32 4294967295%s0 = %d, wanted 4294967295\n", `<<`, got) failed = true } if got := lsh_uint32_4294967295_ssa(0); got != 0 { fmt.Printf("lsh_uint32 0%s4294967295 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_4294967295_uint32_ssa(1); got != 4294967294 { fmt.Printf("lsh_uint32 4294967295%s1 = %d, wanted 4294967294\n", `<<`, got) failed = true } if got := lsh_uint32_4294967295_ssa(1); got != 0 { fmt.Printf("lsh_uint32 1%s4294967295 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_4294967295_uint32_ssa(4294967295); got != 0 { fmt.Printf("lsh_uint32 4294967295%s4294967295 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint32_4294967295_ssa(4294967295); got != 0 { fmt.Printf("lsh_uint32 4294967295%s4294967295 = %d, wanted 0\n", `<<`, got) failed = true } if got := rsh_0_uint32_ssa(0); got != 0 { fmt.Printf("rsh_uint32 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint32_0_ssa(0); got != 0 { fmt.Printf("rsh_uint32 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_0_uint32_ssa(1); got != 0 { fmt.Printf("rsh_uint32 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint32_0_ssa(1); got != 1 { fmt.Printf("rsh_uint32 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_0_uint32_ssa(4294967295); got != 0 { fmt.Printf("rsh_uint32 0%s4294967295 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint32_0_ssa(4294967295); got != 4294967295 { fmt.Printf("rsh_uint32 4294967295%s0 = %d, wanted 4294967295\n", `>>`, got) failed = true } if got := rsh_1_uint32_ssa(0); got != 1 { fmt.Printf("rsh_uint32 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_uint32_1_ssa(0); got != 0 { fmt.Printf("rsh_uint32 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint32_ssa(1); got != 0 { fmt.Printf("rsh_uint32 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint32_1_ssa(1); got != 0 { fmt.Printf("rsh_uint32 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint32_ssa(4294967295); got != 0 { fmt.Printf("rsh_uint32 1%s4294967295 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint32_1_ssa(4294967295); got != 2147483647 { fmt.Printf("rsh_uint32 4294967295%s1 = %d, wanted 2147483647\n", `>>`, got) failed = true } if got := rsh_4294967295_uint32_ssa(0); got != 4294967295 { fmt.Printf("rsh_uint32 4294967295%s0 = %d, wanted 4294967295\n", `>>`, got) failed = true } if got := rsh_uint32_4294967295_ssa(0); got != 0 { fmt.Printf("rsh_uint32 0%s4294967295 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_4294967295_uint32_ssa(1); got != 2147483647 { fmt.Printf("rsh_uint32 4294967295%s1 = %d, wanted 2147483647\n", `>>`, got) failed = true } if got := rsh_uint32_4294967295_ssa(1); got != 0 { fmt.Printf("rsh_uint32 1%s4294967295 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_4294967295_uint32_ssa(4294967295); got != 0 { fmt.Printf("rsh_uint32 4294967295%s4294967295 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint32_4294967295_ssa(4294967295); got != 0 { fmt.Printf("rsh_uint32 4294967295%s4294967295 = %d, wanted 0\n", `>>`, got) failed = true } if got := mod_0_uint32_ssa(1); got != 0 { fmt.Printf("mod_uint32 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_uint32_ssa(4294967295); got != 0 { fmt.Printf("mod_uint32 0%s4294967295 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint32_1_ssa(0); got != 0 { fmt.Printf("mod_uint32 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint32_ssa(1); got != 0 { fmt.Printf("mod_uint32 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint32_1_ssa(1); got != 0 { fmt.Printf("mod_uint32 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint32_ssa(4294967295); got != 1 { fmt.Printf("mod_uint32 1%s4294967295 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_uint32_1_ssa(4294967295); got != 0 { fmt.Printf("mod_uint32 4294967295%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint32_4294967295_ssa(0); got != 0 { fmt.Printf("mod_uint32 0%s4294967295 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967295_uint32_ssa(1); got != 0 { fmt.Printf("mod_uint32 4294967295%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint32_4294967295_ssa(1); got != 1 { fmt.Printf("mod_uint32 1%s4294967295 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_4294967295_uint32_ssa(4294967295); got != 0 { fmt.Printf("mod_uint32 4294967295%s4294967295 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint32_4294967295_ssa(4294967295); got != 0 { fmt.Printf("mod_uint32 4294967295%s4294967295 = %d, wanted 0\n", `%`, got) failed = true } if got := and_0_uint32_ssa(0); got != 0 { fmt.Printf("and_uint32 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint32_0_ssa(0); got != 0 { fmt.Printf("and_uint32 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint32_ssa(1); got != 0 { fmt.Printf("and_uint32 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint32_0_ssa(1); got != 0 { fmt.Printf("and_uint32 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint32_ssa(4294967295); got != 0 { fmt.Printf("and_uint32 0%s4294967295 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint32_0_ssa(4294967295); got != 0 { fmt.Printf("and_uint32 4294967295%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint32_ssa(0); got != 0 { fmt.Printf("and_uint32 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint32_1_ssa(0); got != 0 { fmt.Printf("and_uint32 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint32_ssa(1); got != 1 { fmt.Printf("and_uint32 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint32_1_ssa(1); got != 1 { fmt.Printf("and_uint32 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_uint32_ssa(4294967295); got != 1 { fmt.Printf("and_uint32 1%s4294967295 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint32_1_ssa(4294967295); got != 1 { fmt.Printf("and_uint32 4294967295%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_4294967295_uint32_ssa(0); got != 0 { fmt.Printf("and_uint32 4294967295%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint32_4294967295_ssa(0); got != 0 { fmt.Printf("and_uint32 0%s4294967295 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967295_uint32_ssa(1); got != 1 { fmt.Printf("and_uint32 4294967295%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint32_4294967295_ssa(1); got != 1 { fmt.Printf("and_uint32 1%s4294967295 = %d, wanted 1\n", `&`, got) failed = true } if got := and_4294967295_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("and_uint32 4294967295%s4294967295 = %d, wanted 4294967295\n", `&`, got) failed = true } if got := and_uint32_4294967295_ssa(4294967295); got != 4294967295 { fmt.Printf("and_uint32 4294967295%s4294967295 = %d, wanted 4294967295\n", `&`, got) failed = true } if got := or_0_uint32_ssa(0); got != 0 { fmt.Printf("or_uint32 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_uint32_0_ssa(0); got != 0 { fmt.Printf("or_uint32 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_uint32_ssa(1); got != 1 { fmt.Printf("or_uint32 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint32_0_ssa(1); got != 1 { fmt.Printf("or_uint32 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("or_uint32 0%s4294967295 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_uint32_0_ssa(4294967295); got != 4294967295 { fmt.Printf("or_uint32 4294967295%s0 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_1_uint32_ssa(0); got != 1 { fmt.Printf("or_uint32 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint32_1_ssa(0); got != 1 { fmt.Printf("or_uint32 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint32_ssa(1); got != 1 { fmt.Printf("or_uint32 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint32_1_ssa(1); got != 1 { fmt.Printf("or_uint32 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("or_uint32 1%s4294967295 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_uint32_1_ssa(4294967295); got != 4294967295 { fmt.Printf("or_uint32 4294967295%s1 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_4294967295_uint32_ssa(0); got != 4294967295 { fmt.Printf("or_uint32 4294967295%s0 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_uint32_4294967295_ssa(0); got != 4294967295 { fmt.Printf("or_uint32 0%s4294967295 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_4294967295_uint32_ssa(1); got != 4294967295 { fmt.Printf("or_uint32 4294967295%s1 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_uint32_4294967295_ssa(1); got != 4294967295 { fmt.Printf("or_uint32 1%s4294967295 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_4294967295_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("or_uint32 4294967295%s4294967295 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_uint32_4294967295_ssa(4294967295); got != 4294967295 { fmt.Printf("or_uint32 4294967295%s4294967295 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := xor_0_uint32_ssa(0); got != 0 { fmt.Printf("xor_uint32 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint32_0_ssa(0); got != 0 { fmt.Printf("xor_uint32 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_uint32_ssa(1); got != 1 { fmt.Printf("xor_uint32 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint32_0_ssa(1); got != 1 { fmt.Printf("xor_uint32 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("xor_uint32 0%s4294967295 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_uint32_0_ssa(4294967295); got != 4294967295 { fmt.Printf("xor_uint32 4294967295%s0 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_1_uint32_ssa(0); got != 1 { fmt.Printf("xor_uint32 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint32_1_ssa(0); got != 1 { fmt.Printf("xor_uint32 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_uint32_ssa(1); got != 0 { fmt.Printf("xor_uint32 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint32_1_ssa(1); got != 0 { fmt.Printf("xor_uint32 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_uint32_ssa(4294967295); got != 4294967294 { fmt.Printf("xor_uint32 1%s4294967295 = %d, wanted 4294967294\n", `^`, got) failed = true } if got := xor_uint32_1_ssa(4294967295); got != 4294967294 { fmt.Printf("xor_uint32 4294967295%s1 = %d, wanted 4294967294\n", `^`, got) failed = true } if got := xor_4294967295_uint32_ssa(0); got != 4294967295 { fmt.Printf("xor_uint32 4294967295%s0 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_uint32_4294967295_ssa(0); got != 4294967295 { fmt.Printf("xor_uint32 0%s4294967295 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_4294967295_uint32_ssa(1); got != 4294967294 { fmt.Printf("xor_uint32 4294967295%s1 = %d, wanted 4294967294\n", `^`, got) failed = true } if got := xor_uint32_4294967295_ssa(1); got != 4294967294 { fmt.Printf("xor_uint32 1%s4294967295 = %d, wanted 4294967294\n", `^`, got) failed = true } if got := xor_4294967295_uint32_ssa(4294967295); got != 0 { fmt.Printf("xor_uint32 4294967295%s4294967295 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint32_4294967295_ssa(4294967295); got != 0 { fmt.Printf("xor_uint32 4294967295%s4294967295 = %d, wanted 0\n", `^`, got) failed = true } if got := add_Neg2147483648_int32_ssa(-2147483648); got != 0 { fmt.Printf("add_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int32_Neg2147483648_ssa(-2147483648); got != 0 { fmt.Printf("add_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg2147483648_int32_ssa(-2147483647); got != 1 { fmt.Printf("add_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int32_Neg2147483648_ssa(-2147483647); got != 1 { fmt.Printf("add_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg2147483648_int32_ssa(-1); got != 2147483647 { fmt.Printf("add_int32 -2147483648%s-1 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_int32_Neg2147483648_ssa(-1); got != 2147483647 { fmt.Printf("add_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_Neg2147483648_int32_ssa(0); got != -2147483648 { fmt.Printf("add_int32 -2147483648%s0 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_int32_Neg2147483648_ssa(0); got != -2147483648 { fmt.Printf("add_int32 0%s-2147483648 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_Neg2147483648_int32_ssa(1); got != -2147483647 { fmt.Printf("add_int32 -2147483648%s1 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_int32_Neg2147483648_ssa(1); got != -2147483647 { fmt.Printf("add_int32 1%s-2147483648 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_Neg2147483648_int32_ssa(2147483647); got != -1 { fmt.Printf("add_int32 -2147483648%s2147483647 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int32_Neg2147483648_ssa(2147483647); got != -1 { fmt.Printf("add_int32 2147483647%s-2147483648 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg2147483647_int32_ssa(-2147483648); got != 1 { fmt.Printf("add_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int32_Neg2147483647_ssa(-2147483648); got != 1 { fmt.Printf("add_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg2147483647_int32_ssa(-2147483647); got != 2 { fmt.Printf("add_int32 -2147483647%s-2147483647 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int32_Neg2147483647_ssa(-2147483647); got != 2 { fmt.Printf("add_int32 -2147483647%s-2147483647 = %d, wanted 2\n", `+`, got) failed = true } if got := add_Neg2147483647_int32_ssa(-1); got != -2147483648 { fmt.Printf("add_int32 -2147483647%s-1 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_int32_Neg2147483647_ssa(-1); got != -2147483648 { fmt.Printf("add_int32 -1%s-2147483647 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_Neg2147483647_int32_ssa(0); got != -2147483647 { fmt.Printf("add_int32 -2147483647%s0 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_int32_Neg2147483647_ssa(0); got != -2147483647 { fmt.Printf("add_int32 0%s-2147483647 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_Neg2147483647_int32_ssa(1); got != -2147483646 { fmt.Printf("add_int32 -2147483647%s1 = %d, wanted -2147483646\n", `+`, got) failed = true } if got := add_int32_Neg2147483647_ssa(1); got != -2147483646 { fmt.Printf("add_int32 1%s-2147483647 = %d, wanted -2147483646\n", `+`, got) failed = true } if got := add_Neg2147483647_int32_ssa(2147483647); got != 0 { fmt.Printf("add_int32 -2147483647%s2147483647 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int32_Neg2147483647_ssa(2147483647); got != 0 { fmt.Printf("add_int32 2147483647%s-2147483647 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int32_ssa(-2147483648); got != 2147483647 { fmt.Printf("add_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_int32_Neg1_ssa(-2147483648); got != 2147483647 { fmt.Printf("add_int32 -2147483648%s-1 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_Neg1_int32_ssa(-2147483647); got != -2147483648 { fmt.Printf("add_int32 -1%s-2147483647 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_int32_Neg1_ssa(-2147483647); got != -2147483648 { fmt.Printf("add_int32 -2147483647%s-1 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_Neg1_int32_ssa(-1); got != -2 { fmt.Printf("add_int32 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int32_Neg1_ssa(-1); got != -2 { fmt.Printf("add_int32 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg1_int32_ssa(0); got != -1 { fmt.Printf("add_int32 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int32_Neg1_ssa(0); got != -1 { fmt.Printf("add_int32 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg1_int32_ssa(1); got != 0 { fmt.Printf("add_int32 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int32_Neg1_ssa(1); got != 0 { fmt.Printf("add_int32 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int32_ssa(2147483647); got != 2147483646 { fmt.Printf("add_int32 -1%s2147483647 = %d, wanted 2147483646\n", `+`, got) failed = true } if got := add_int32_Neg1_ssa(2147483647); got != 2147483646 { fmt.Printf("add_int32 2147483647%s-1 = %d, wanted 2147483646\n", `+`, got) failed = true } if got := add_0_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("add_int32 0%s-2147483648 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_int32_0_ssa(-2147483648); got != -2147483648 { fmt.Printf("add_int32 -2147483648%s0 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_0_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("add_int32 0%s-2147483647 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_int32_0_ssa(-2147483647); got != -2147483647 { fmt.Printf("add_int32 -2147483647%s0 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_0_int32_ssa(-1); got != -1 { fmt.Printf("add_int32 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int32_0_ssa(-1); got != -1 { fmt.Printf("add_int32 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_0_int32_ssa(0); got != 0 { fmt.Printf("add_int32 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int32_0_ssa(0); got != 0 { fmt.Printf("add_int32 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_int32_ssa(1); got != 1 { fmt.Printf("add_int32 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int32_0_ssa(1); got != 1 { fmt.Printf("add_int32 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("add_int32 0%s2147483647 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_int32_0_ssa(2147483647); got != 2147483647 { fmt.Printf("add_int32 2147483647%s0 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_1_int32_ssa(-2147483648); got != -2147483647 { fmt.Printf("add_int32 1%s-2147483648 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_int32_1_ssa(-2147483648); got != -2147483647 { fmt.Printf("add_int32 -2147483648%s1 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_1_int32_ssa(-2147483647); got != -2147483646 { fmt.Printf("add_int32 1%s-2147483647 = %d, wanted -2147483646\n", `+`, got) failed = true } if got := add_int32_1_ssa(-2147483647); got != -2147483646 { fmt.Printf("add_int32 -2147483647%s1 = %d, wanted -2147483646\n", `+`, got) failed = true } if got := add_1_int32_ssa(-1); got != 0 { fmt.Printf("add_int32 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int32_1_ssa(-1); got != 0 { fmt.Printf("add_int32 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_1_int32_ssa(0); got != 1 { fmt.Printf("add_int32 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int32_1_ssa(0); got != 1 { fmt.Printf("add_int32 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_int32_ssa(1); got != 2 { fmt.Printf("add_int32 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int32_1_ssa(1); got != 2 { fmt.Printf("add_int32 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_int32_ssa(2147483647); got != -2147483648 { fmt.Printf("add_int32 1%s2147483647 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_int32_1_ssa(2147483647); got != -2147483648 { fmt.Printf("add_int32 2147483647%s1 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_2147483647_int32_ssa(-2147483648); got != -1 { fmt.Printf("add_int32 2147483647%s-2147483648 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int32_2147483647_ssa(-2147483648); got != -1 { fmt.Printf("add_int32 -2147483648%s2147483647 = %d, wanted -1\n", `+`, got) failed = true } if got := add_2147483647_int32_ssa(-2147483647); got != 0 { fmt.Printf("add_int32 2147483647%s-2147483647 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int32_2147483647_ssa(-2147483647); got != 0 { fmt.Printf("add_int32 -2147483647%s2147483647 = %d, wanted 0\n", `+`, got) failed = true } if got := add_2147483647_int32_ssa(-1); got != 2147483646 { fmt.Printf("add_int32 2147483647%s-1 = %d, wanted 2147483646\n", `+`, got) failed = true } if got := add_int32_2147483647_ssa(-1); got != 2147483646 { fmt.Printf("add_int32 -1%s2147483647 = %d, wanted 2147483646\n", `+`, got) failed = true } if got := add_2147483647_int32_ssa(0); got != 2147483647 { fmt.Printf("add_int32 2147483647%s0 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_int32_2147483647_ssa(0); got != 2147483647 { fmt.Printf("add_int32 0%s2147483647 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_2147483647_int32_ssa(1); got != -2147483648 { fmt.Printf("add_int32 2147483647%s1 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_int32_2147483647_ssa(1); got != -2147483648 { fmt.Printf("add_int32 1%s2147483647 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_2147483647_int32_ssa(2147483647); got != -2 { fmt.Printf("add_int32 2147483647%s2147483647 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int32_2147483647_ssa(2147483647); got != -2 { fmt.Printf("add_int32 2147483647%s2147483647 = %d, wanted -2\n", `+`, got) failed = true } if got := sub_Neg2147483648_int32_ssa(-2147483648); got != 0 { fmt.Printf("sub_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int32_Neg2147483648_ssa(-2147483648); got != 0 { fmt.Printf("sub_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg2147483648_int32_ssa(-2147483647); got != -1 { fmt.Printf("sub_int32 -2147483648%s-2147483647 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int32_Neg2147483648_ssa(-2147483647); got != 1 { fmt.Printf("sub_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg2147483648_int32_ssa(-1); got != -2147483647 { fmt.Printf("sub_int32 -2147483648%s-1 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_int32_Neg2147483648_ssa(-1); got != 2147483647 { fmt.Printf("sub_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_Neg2147483648_int32_ssa(0); got != -2147483648 { fmt.Printf("sub_int32 -2147483648%s0 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_int32_Neg2147483648_ssa(0); got != -2147483648 { fmt.Printf("sub_int32 0%s-2147483648 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_Neg2147483648_int32_ssa(1); got != 2147483647 { fmt.Printf("sub_int32 -2147483648%s1 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_int32_Neg2147483648_ssa(1); got != -2147483647 { fmt.Printf("sub_int32 1%s-2147483648 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_Neg2147483648_int32_ssa(2147483647); got != 1 { fmt.Printf("sub_int32 -2147483648%s2147483647 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int32_Neg2147483648_ssa(2147483647); got != -1 { fmt.Printf("sub_int32 2147483647%s-2147483648 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg2147483647_int32_ssa(-2147483648); got != 1 { fmt.Printf("sub_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int32_Neg2147483647_ssa(-2147483648); got != -1 { fmt.Printf("sub_int32 -2147483648%s-2147483647 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg2147483647_int32_ssa(-2147483647); got != 0 { fmt.Printf("sub_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int32_Neg2147483647_ssa(-2147483647); got != 0 { fmt.Printf("sub_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg2147483647_int32_ssa(-1); got != -2147483646 { fmt.Printf("sub_int32 -2147483647%s-1 = %d, wanted -2147483646\n", `-`, got) failed = true } if got := sub_int32_Neg2147483647_ssa(-1); got != 2147483646 { fmt.Printf("sub_int32 -1%s-2147483647 = %d, wanted 2147483646\n", `-`, got) failed = true } if got := sub_Neg2147483647_int32_ssa(0); got != -2147483647 { fmt.Printf("sub_int32 -2147483647%s0 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_int32_Neg2147483647_ssa(0); got != 2147483647 { fmt.Printf("sub_int32 0%s-2147483647 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_Neg2147483647_int32_ssa(1); got != -2147483648 { fmt.Printf("sub_int32 -2147483647%s1 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_int32_Neg2147483647_ssa(1); got != -2147483648 { fmt.Printf("sub_int32 1%s-2147483647 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_Neg2147483647_int32_ssa(2147483647); got != 2 { fmt.Printf("sub_int32 -2147483647%s2147483647 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int32_Neg2147483647_ssa(2147483647); got != -2 { fmt.Printf("sub_int32 2147483647%s-2147483647 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg1_int32_ssa(-2147483648); got != 2147483647 { fmt.Printf("sub_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_int32_Neg1_ssa(-2147483648); got != -2147483647 { fmt.Printf("sub_int32 -2147483648%s-1 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_Neg1_int32_ssa(-2147483647); got != 2147483646 { fmt.Printf("sub_int32 -1%s-2147483647 = %d, wanted 2147483646\n", `-`, got) failed = true } if got := sub_int32_Neg1_ssa(-2147483647); got != -2147483646 { fmt.Printf("sub_int32 -2147483647%s-1 = %d, wanted -2147483646\n", `-`, got) failed = true } if got := sub_Neg1_int32_ssa(-1); got != 0 { fmt.Printf("sub_int32 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int32_Neg1_ssa(-1); got != 0 { fmt.Printf("sub_int32 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg1_int32_ssa(0); got != -1 { fmt.Printf("sub_int32 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int32_Neg1_ssa(0); got != 1 { fmt.Printf("sub_int32 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg1_int32_ssa(1); got != -2 { fmt.Printf("sub_int32 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int32_Neg1_ssa(1); got != 2 { fmt.Printf("sub_int32 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_Neg1_int32_ssa(2147483647); got != -2147483648 { fmt.Printf("sub_int32 -1%s2147483647 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_int32_Neg1_ssa(2147483647); got != -2147483648 { fmt.Printf("sub_int32 2147483647%s-1 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_0_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("sub_int32 0%s-2147483648 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_int32_0_ssa(-2147483648); got != -2147483648 { fmt.Printf("sub_int32 -2147483648%s0 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_0_int32_ssa(-2147483647); got != 2147483647 { fmt.Printf("sub_int32 0%s-2147483647 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_int32_0_ssa(-2147483647); got != -2147483647 { fmt.Printf("sub_int32 -2147483647%s0 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_0_int32_ssa(-1); got != 1 { fmt.Printf("sub_int32 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int32_0_ssa(-1); got != -1 { fmt.Printf("sub_int32 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_0_int32_ssa(0); got != 0 { fmt.Printf("sub_int32 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int32_0_ssa(0); got != 0 { fmt.Printf("sub_int32 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_int32_ssa(1); got != -1 { fmt.Printf("sub_int32 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int32_0_ssa(1); got != 1 { fmt.Printf("sub_int32 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_int32_ssa(2147483647); got != -2147483647 { fmt.Printf("sub_int32 0%s2147483647 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_int32_0_ssa(2147483647); got != 2147483647 { fmt.Printf("sub_int32 2147483647%s0 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_1_int32_ssa(-2147483648); got != -2147483647 { fmt.Printf("sub_int32 1%s-2147483648 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_int32_1_ssa(-2147483648); got != 2147483647 { fmt.Printf("sub_int32 -2147483648%s1 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_1_int32_ssa(-2147483647); got != -2147483648 { fmt.Printf("sub_int32 1%s-2147483647 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_int32_1_ssa(-2147483647); got != -2147483648 { fmt.Printf("sub_int32 -2147483647%s1 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_1_int32_ssa(-1); got != 2 { fmt.Printf("sub_int32 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int32_1_ssa(-1); got != -2 { fmt.Printf("sub_int32 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_1_int32_ssa(0); got != 1 { fmt.Printf("sub_int32 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int32_1_ssa(0); got != -1 { fmt.Printf("sub_int32 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_1_int32_ssa(1); got != 0 { fmt.Printf("sub_int32 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int32_1_ssa(1); got != 0 { fmt.Printf("sub_int32 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_int32_ssa(2147483647); got != -2147483646 { fmt.Printf("sub_int32 1%s2147483647 = %d, wanted -2147483646\n", `-`, got) failed = true } if got := sub_int32_1_ssa(2147483647); got != 2147483646 { fmt.Printf("sub_int32 2147483647%s1 = %d, wanted 2147483646\n", `-`, got) failed = true } if got := sub_2147483647_int32_ssa(-2147483648); got != -1 { fmt.Printf("sub_int32 2147483647%s-2147483648 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int32_2147483647_ssa(-2147483648); got != 1 { fmt.Printf("sub_int32 -2147483648%s2147483647 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_2147483647_int32_ssa(-2147483647); got != -2 { fmt.Printf("sub_int32 2147483647%s-2147483647 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int32_2147483647_ssa(-2147483647); got != 2 { fmt.Printf("sub_int32 -2147483647%s2147483647 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_2147483647_int32_ssa(-1); got != -2147483648 { fmt.Printf("sub_int32 2147483647%s-1 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_int32_2147483647_ssa(-1); got != -2147483648 { fmt.Printf("sub_int32 -1%s2147483647 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_2147483647_int32_ssa(0); got != 2147483647 { fmt.Printf("sub_int32 2147483647%s0 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_int32_2147483647_ssa(0); got != -2147483647 { fmt.Printf("sub_int32 0%s2147483647 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_2147483647_int32_ssa(1); got != 2147483646 { fmt.Printf("sub_int32 2147483647%s1 = %d, wanted 2147483646\n", `-`, got) failed = true } if got := sub_int32_2147483647_ssa(1); got != -2147483646 { fmt.Printf("sub_int32 1%s2147483647 = %d, wanted -2147483646\n", `-`, got) failed = true } if got := sub_2147483647_int32_ssa(2147483647); got != 0 { fmt.Printf("sub_int32 2147483647%s2147483647 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int32_2147483647_ssa(2147483647); got != 0 { fmt.Printf("sub_int32 2147483647%s2147483647 = %d, wanted 0\n", `-`, got) failed = true } if got := div_Neg2147483648_int32_ssa(-2147483648); got != 1 { fmt.Printf("div_int32 -2147483648%s-2147483648 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_Neg2147483648_ssa(-2147483648); got != 1 { fmt.Printf("div_int32 -2147483648%s-2147483648 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg2147483648_int32_ssa(-2147483647); got != 1 { fmt.Printf("div_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_Neg2147483648_ssa(-2147483647); got != 0 { fmt.Printf("div_int32 -2147483647%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg2147483648_int32_ssa(-1); got != -2147483648 { fmt.Printf("div_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `/`, got) failed = true } if got := div_int32_Neg2147483648_ssa(-1); got != 0 { fmt.Printf("div_int32 -1%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_Neg2147483648_ssa(0); got != 0 { fmt.Printf("div_int32 0%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg2147483648_int32_ssa(1); got != -2147483648 { fmt.Printf("div_int32 -2147483648%s1 = %d, wanted -2147483648\n", `/`, got) failed = true } if got := div_int32_Neg2147483648_ssa(1); got != 0 { fmt.Printf("div_int32 1%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg2147483648_int32_ssa(2147483647); got != -1 { fmt.Printf("div_int32 -2147483648%s2147483647 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int32_Neg2147483648_ssa(2147483647); got != 0 { fmt.Printf("div_int32 2147483647%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg2147483647_int32_ssa(-2147483648); got != 0 { fmt.Printf("div_int32 -2147483647%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_Neg2147483647_ssa(-2147483648); got != 1 { fmt.Printf("div_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg2147483647_int32_ssa(-2147483647); got != 1 { fmt.Printf("div_int32 -2147483647%s-2147483647 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_Neg2147483647_ssa(-2147483647); got != 1 { fmt.Printf("div_int32 -2147483647%s-2147483647 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg2147483647_int32_ssa(-1); got != 2147483647 { fmt.Printf("div_int32 -2147483647%s-1 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_int32_Neg2147483647_ssa(-1); got != 0 { fmt.Printf("div_int32 -1%s-2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_Neg2147483647_ssa(0); got != 0 { fmt.Printf("div_int32 0%s-2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg2147483647_int32_ssa(1); got != -2147483647 { fmt.Printf("div_int32 -2147483647%s1 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_int32_Neg2147483647_ssa(1); got != 0 { fmt.Printf("div_int32 1%s-2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg2147483647_int32_ssa(2147483647); got != -1 { fmt.Printf("div_int32 -2147483647%s2147483647 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int32_Neg2147483647_ssa(2147483647); got != -1 { fmt.Printf("div_int32 2147483647%s-2147483647 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int32_ssa(-2147483648); got != 0 { fmt.Printf("div_int32 -1%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_Neg1_ssa(-2147483648); got != -2147483648 { fmt.Printf("div_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `/`, got) failed = true } if got := div_Neg1_int32_ssa(-2147483647); got != 0 { fmt.Printf("div_int32 -1%s-2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_Neg1_ssa(-2147483647); got != 2147483647 { fmt.Printf("div_int32 -2147483647%s-1 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_Neg1_int32_ssa(-1); got != 1 { fmt.Printf("div_int32 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_Neg1_ssa(-1); got != 1 { fmt.Printf("div_int32 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_Neg1_ssa(0); got != 0 { fmt.Printf("div_int32 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg1_int32_ssa(1); got != -1 { fmt.Printf("div_int32 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int32_Neg1_ssa(1); got != -1 { fmt.Printf("div_int32 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int32_ssa(2147483647); got != 0 { fmt.Printf("div_int32 -1%s2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_Neg1_ssa(2147483647); got != -2147483647 { fmt.Printf("div_int32 2147483647%s-1 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_0_int32_ssa(-2147483648); got != 0 { fmt.Printf("div_int32 0%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int32_ssa(-2147483647); got != 0 { fmt.Printf("div_int32 0%s-2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int32_ssa(-1); got != 0 { fmt.Printf("div_int32 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int32_ssa(1); got != 0 { fmt.Printf("div_int32 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int32_ssa(2147483647); got != 0 { fmt.Printf("div_int32 0%s2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int32_ssa(-2147483648); got != 0 { fmt.Printf("div_int32 1%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_1_ssa(-2147483648); got != -2147483648 { fmt.Printf("div_int32 -2147483648%s1 = %d, wanted -2147483648\n", `/`, got) failed = true } if got := div_1_int32_ssa(-2147483647); got != 0 { fmt.Printf("div_int32 1%s-2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_1_ssa(-2147483647); got != -2147483647 { fmt.Printf("div_int32 -2147483647%s1 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_1_int32_ssa(-1); got != -1 { fmt.Printf("div_int32 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int32_1_ssa(-1); got != -1 { fmt.Printf("div_int32 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int32_1_ssa(0); got != 0 { fmt.Printf("div_int32 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int32_ssa(1); got != 1 { fmt.Printf("div_int32 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_1_ssa(1); got != 1 { fmt.Printf("div_int32 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_int32_ssa(2147483647); got != 0 { fmt.Printf("div_int32 1%s2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_1_ssa(2147483647); got != 2147483647 { fmt.Printf("div_int32 2147483647%s1 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_2147483647_int32_ssa(-2147483648); got != 0 { fmt.Printf("div_int32 2147483647%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_2147483647_ssa(-2147483648); got != -1 { fmt.Printf("div_int32 -2147483648%s2147483647 = %d, wanted -1\n", `/`, got) failed = true } if got := div_2147483647_int32_ssa(-2147483647); got != -1 { fmt.Printf("div_int32 2147483647%s-2147483647 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int32_2147483647_ssa(-2147483647); got != -1 { fmt.Printf("div_int32 -2147483647%s2147483647 = %d, wanted -1\n", `/`, got) failed = true } if got := div_2147483647_int32_ssa(-1); got != -2147483647 { fmt.Printf("div_int32 2147483647%s-1 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_int32_2147483647_ssa(-1); got != 0 { fmt.Printf("div_int32 -1%s2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_2147483647_ssa(0); got != 0 { fmt.Printf("div_int32 0%s2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_2147483647_int32_ssa(1); got != 2147483647 { fmt.Printf("div_int32 2147483647%s1 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_int32_2147483647_ssa(1); got != 0 { fmt.Printf("div_int32 1%s2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_2147483647_int32_ssa(2147483647); got != 1 { fmt.Printf("div_int32 2147483647%s2147483647 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_2147483647_ssa(2147483647); got != 1 { fmt.Printf("div_int32 2147483647%s2147483647 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_Neg2147483648_int32_ssa(-2147483648); got != 0 { fmt.Printf("mul_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_Neg2147483648_ssa(-2147483648); got != 0 { fmt.Printf("mul_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg2147483648_int32_ssa(-2147483647); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s-2147483647 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_Neg2147483648_ssa(-2147483647); got != -2147483648 { fmt.Printf("mul_int32 -2147483647%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_Neg2147483648_int32_ssa(-1); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_Neg2147483648_ssa(-1); got != -2147483648 { fmt.Printf("mul_int32 -1%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_Neg2147483648_int32_ssa(0); got != 0 { fmt.Printf("mul_int32 -2147483648%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_Neg2147483648_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s-2147483648 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg2147483648_int32_ssa(1); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s1 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_Neg2147483648_ssa(1); got != -2147483648 { fmt.Printf("mul_int32 1%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_Neg2147483648_int32_ssa(2147483647); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s2147483647 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_Neg2147483648_ssa(2147483647); got != -2147483648 { fmt.Printf("mul_int32 2147483647%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_Neg2147483647_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 -2147483647%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_Neg2147483647_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s-2147483647 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_Neg2147483647_int32_ssa(-2147483647); got != 1 { fmt.Printf("mul_int32 -2147483647%s-2147483647 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int32_Neg2147483647_ssa(-2147483647); got != 1 { fmt.Printf("mul_int32 -2147483647%s-2147483647 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg2147483647_int32_ssa(-1); got != 2147483647 { fmt.Printf("mul_int32 -2147483647%s-1 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_int32_Neg2147483647_ssa(-1); got != 2147483647 { fmt.Printf("mul_int32 -1%s-2147483647 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_Neg2147483647_int32_ssa(0); got != 0 { fmt.Printf("mul_int32 -2147483647%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_Neg2147483647_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s-2147483647 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg2147483647_int32_ssa(1); got != -2147483647 { fmt.Printf("mul_int32 -2147483647%s1 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_int32_Neg2147483647_ssa(1); got != -2147483647 { fmt.Printf("mul_int32 1%s-2147483647 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_Neg2147483647_int32_ssa(2147483647); got != -1 { fmt.Printf("mul_int32 -2147483647%s2147483647 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int32_Neg2147483647_ssa(2147483647); got != -1 { fmt.Printf("mul_int32 2147483647%s-2147483647 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 -1%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_Neg1_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_Neg1_int32_ssa(-2147483647); got != 2147483647 { fmt.Printf("mul_int32 -1%s-2147483647 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_int32_Neg1_ssa(-2147483647); got != 2147483647 { fmt.Printf("mul_int32 -2147483647%s-1 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_Neg1_int32_ssa(-1); got != 1 { fmt.Printf("mul_int32 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int32_Neg1_ssa(-1); got != 1 { fmt.Printf("mul_int32 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg1_int32_ssa(0); got != 0 { fmt.Printf("mul_int32 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_Neg1_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg1_int32_ssa(1); got != -1 { fmt.Printf("mul_int32 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int32_Neg1_ssa(1); got != -1 { fmt.Printf("mul_int32 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int32_ssa(2147483647); got != -2147483647 { fmt.Printf("mul_int32 -1%s2147483647 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_int32_Neg1_ssa(2147483647); got != -2147483647 { fmt.Printf("mul_int32 2147483647%s-1 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_0_int32_ssa(-2147483648); got != 0 { fmt.Printf("mul_int32 0%s-2147483648 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_0_ssa(-2147483648); got != 0 { fmt.Printf("mul_int32 -2147483648%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int32_ssa(-2147483647); got != 0 { fmt.Printf("mul_int32 0%s-2147483647 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_0_ssa(-2147483647); got != 0 { fmt.Printf("mul_int32 -2147483647%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int32_ssa(-1); got != 0 { fmt.Printf("mul_int32 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_0_ssa(-1); got != 0 { fmt.Printf("mul_int32 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int32_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_0_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int32_ssa(1); got != 0 { fmt.Printf("mul_int32 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_0_ssa(1); got != 0 { fmt.Printf("mul_int32 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int32_ssa(2147483647); got != 0 { fmt.Printf("mul_int32 0%s2147483647 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_0_ssa(2147483647); got != 0 { fmt.Printf("mul_int32 2147483647%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 1%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_1_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s1 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_1_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("mul_int32 1%s-2147483647 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_int32_1_ssa(-2147483647); got != -2147483647 { fmt.Printf("mul_int32 -2147483647%s1 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_1_int32_ssa(-1); got != -1 { fmt.Printf("mul_int32 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int32_1_ssa(-1); got != -1 { fmt.Printf("mul_int32 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_1_int32_ssa(0); got != 0 { fmt.Printf("mul_int32 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_1_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int32_ssa(1); got != 1 { fmt.Printf("mul_int32 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int32_1_ssa(1); got != 1 { fmt.Printf("mul_int32 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("mul_int32 1%s2147483647 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_int32_1_ssa(2147483647); got != 2147483647 { fmt.Printf("mul_int32 2147483647%s1 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_2147483647_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 2147483647%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_2147483647_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s2147483647 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_2147483647_int32_ssa(-2147483647); got != -1 { fmt.Printf("mul_int32 2147483647%s-2147483647 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int32_2147483647_ssa(-2147483647); got != -1 { fmt.Printf("mul_int32 -2147483647%s2147483647 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_2147483647_int32_ssa(-1); got != -2147483647 { fmt.Printf("mul_int32 2147483647%s-1 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_int32_2147483647_ssa(-1); got != -2147483647 { fmt.Printf("mul_int32 -1%s2147483647 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_2147483647_int32_ssa(0); got != 0 { fmt.Printf("mul_int32 2147483647%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_2147483647_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s2147483647 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_2147483647_int32_ssa(1); got != 2147483647 { fmt.Printf("mul_int32 2147483647%s1 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_int32_2147483647_ssa(1); got != 2147483647 { fmt.Printf("mul_int32 1%s2147483647 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_2147483647_int32_ssa(2147483647); got != 1 { fmt.Printf("mul_int32 2147483647%s2147483647 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int32_2147483647_ssa(2147483647); got != 1 { fmt.Printf("mul_int32 2147483647%s2147483647 = %d, wanted 1\n", `*`, got) failed = true } if got := mod_Neg2147483648_int32_ssa(-2147483648); got != 0 { fmt.Printf("mod_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483648_ssa(-2147483648); got != 0 { fmt.Printf("mod_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg2147483648_int32_ssa(-2147483647); got != -1 { fmt.Printf("mod_int32 -2147483648%s-2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg2147483648_ssa(-2147483647); got != -2147483647 { fmt.Printf("mod_int32 -2147483647%s-2147483648 = %d, wanted -2147483647\n", `%`, got) failed = true } if got := mod_Neg2147483648_int32_ssa(-1); got != 0 { fmt.Printf("mod_int32 -2147483648%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483648_ssa(-1); got != -1 { fmt.Printf("mod_int32 -1%s-2147483648 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg2147483648_ssa(0); got != 0 { fmt.Printf("mod_int32 0%s-2147483648 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg2147483648_int32_ssa(1); got != 0 { fmt.Printf("mod_int32 -2147483648%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483648_ssa(1); got != 1 { fmt.Printf("mod_int32 1%s-2147483648 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg2147483648_int32_ssa(2147483647); got != -1 { fmt.Printf("mod_int32 -2147483648%s2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg2147483648_ssa(2147483647); got != 2147483647 { fmt.Printf("mod_int32 2147483647%s-2147483648 = %d, wanted 2147483647\n", `%`, got) failed = true } if got := mod_Neg2147483647_int32_ssa(-2147483648); got != -2147483647 { fmt.Printf("mod_int32 -2147483647%s-2147483648 = %d, wanted -2147483647\n", `%`, got) failed = true } if got := mod_int32_Neg2147483647_ssa(-2147483648); got != -1 { fmt.Printf("mod_int32 -2147483648%s-2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_Neg2147483647_int32_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483647_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg2147483647_int32_ssa(-1); got != 0 { fmt.Printf("mod_int32 -2147483647%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483647_ssa(-1); got != -1 { fmt.Printf("mod_int32 -1%s-2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg2147483647_ssa(0); got != 0 { fmt.Printf("mod_int32 0%s-2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg2147483647_int32_ssa(1); got != 0 { fmt.Printf("mod_int32 -2147483647%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483647_ssa(1); got != 1 { fmt.Printf("mod_int32 1%s-2147483647 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg2147483647_int32_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 -2147483647%s2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483647_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 2147483647%s-2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int32_ssa(-2147483648); got != -1 { fmt.Printf("mod_int32 -1%s-2147483648 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg1_ssa(-2147483648); got != 0 { fmt.Printf("mod_int32 -2147483648%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int32_ssa(-2147483647); got != -1 { fmt.Printf("mod_int32 -1%s-2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg1_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 -2147483647%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int32_ssa(-1); got != 0 { fmt.Printf("mod_int32 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg1_ssa(-1); got != 0 { fmt.Printf("mod_int32 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg1_ssa(0); got != 0 { fmt.Printf("mod_int32 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int32_ssa(1); got != 0 { fmt.Printf("mod_int32 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg1_ssa(1); got != 0 { fmt.Printf("mod_int32 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int32_ssa(2147483647); got != -1 { fmt.Printf("mod_int32 -1%s2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg1_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 2147483647%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int32_ssa(-2147483648); got != 0 { fmt.Printf("mod_int32 0%s-2147483648 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int32_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 0%s-2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int32_ssa(-1); got != 0 { fmt.Printf("mod_int32 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int32_ssa(1); got != 0 { fmt.Printf("mod_int32 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int32_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 0%s2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int32_ssa(-2147483648); got != 1 { fmt.Printf("mod_int32 1%s-2147483648 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int32_1_ssa(-2147483648); got != 0 { fmt.Printf("mod_int32 -2147483648%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int32_ssa(-2147483647); got != 1 { fmt.Printf("mod_int32 1%s-2147483647 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int32_1_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 -2147483647%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int32_ssa(-1); got != 0 { fmt.Printf("mod_int32 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_1_ssa(-1); got != 0 { fmt.Printf("mod_int32 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_1_ssa(0); got != 0 { fmt.Printf("mod_int32 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int32_ssa(1); got != 0 { fmt.Printf("mod_int32 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_1_ssa(1); got != 0 { fmt.Printf("mod_int32 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int32_ssa(2147483647); got != 1 { fmt.Printf("mod_int32 1%s2147483647 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int32_1_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 2147483647%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_2147483647_int32_ssa(-2147483648); got != 2147483647 { fmt.Printf("mod_int32 2147483647%s-2147483648 = %d, wanted 2147483647\n", `%`, got) failed = true } if got := mod_int32_2147483647_ssa(-2147483648); got != -1 { fmt.Printf("mod_int32 -2147483648%s2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_2147483647_int32_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 2147483647%s-2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_2147483647_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 -2147483647%s2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_2147483647_int32_ssa(-1); got != 0 { fmt.Printf("mod_int32 2147483647%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_2147483647_ssa(-1); got != -1 { fmt.Printf("mod_int32 -1%s2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_2147483647_ssa(0); got != 0 { fmt.Printf("mod_int32 0%s2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_2147483647_int32_ssa(1); got != 0 { fmt.Printf("mod_int32 2147483647%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_2147483647_ssa(1); got != 1 { fmt.Printf("mod_int32 1%s2147483647 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_2147483647_int32_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 2147483647%s2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_2147483647_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 2147483647%s2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := and_Neg2147483648_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("and_int32 -2147483648%s-2147483648 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_int32_Neg2147483648_ssa(-2147483648); got != -2147483648 { fmt.Printf("and_int32 -2147483648%s-2147483648 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_Neg2147483648_int32_ssa(-2147483647); got != -2147483648 { fmt.Printf("and_int32 -2147483648%s-2147483647 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_int32_Neg2147483648_ssa(-2147483647); got != -2147483648 { fmt.Printf("and_int32 -2147483647%s-2147483648 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_Neg2147483648_int32_ssa(-1); got != -2147483648 { fmt.Printf("and_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_int32_Neg2147483648_ssa(-1); got != -2147483648 { fmt.Printf("and_int32 -1%s-2147483648 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_Neg2147483648_int32_ssa(0); got != 0 { fmt.Printf("and_int32 -2147483648%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_Neg2147483648_ssa(0); got != 0 { fmt.Printf("and_int32 0%s-2147483648 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg2147483648_int32_ssa(1); got != 0 { fmt.Printf("and_int32 -2147483648%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_Neg2147483648_ssa(1); got != 0 { fmt.Printf("and_int32 1%s-2147483648 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg2147483648_int32_ssa(2147483647); got != 0 { fmt.Printf("and_int32 -2147483648%s2147483647 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_Neg2147483648_ssa(2147483647); got != 0 { fmt.Printf("and_int32 2147483647%s-2147483648 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg2147483647_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("and_int32 -2147483647%s-2147483648 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_int32_Neg2147483647_ssa(-2147483648); got != -2147483648 { fmt.Printf("and_int32 -2147483648%s-2147483647 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_Neg2147483647_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("and_int32 -2147483647%s-2147483647 = %d, wanted -2147483647\n", `&`, got) failed = true } if got := and_int32_Neg2147483647_ssa(-2147483647); got != -2147483647 { fmt.Printf("and_int32 -2147483647%s-2147483647 = %d, wanted -2147483647\n", `&`, got) failed = true } if got := and_Neg2147483647_int32_ssa(-1); got != -2147483647 { fmt.Printf("and_int32 -2147483647%s-1 = %d, wanted -2147483647\n", `&`, got) failed = true } if got := and_int32_Neg2147483647_ssa(-1); got != -2147483647 { fmt.Printf("and_int32 -1%s-2147483647 = %d, wanted -2147483647\n", `&`, got) failed = true } if got := and_Neg2147483647_int32_ssa(0); got != 0 { fmt.Printf("and_int32 -2147483647%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_Neg2147483647_ssa(0); got != 0 { fmt.Printf("and_int32 0%s-2147483647 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg2147483647_int32_ssa(1); got != 1 { fmt.Printf("and_int32 -2147483647%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_Neg2147483647_ssa(1); got != 1 { fmt.Printf("and_int32 1%s-2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg2147483647_int32_ssa(2147483647); got != 1 { fmt.Printf("and_int32 -2147483647%s2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_Neg2147483647_ssa(2147483647); got != 1 { fmt.Printf("and_int32 2147483647%s-2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("and_int32 -1%s-2147483648 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_int32_Neg1_ssa(-2147483648); got != -2147483648 { fmt.Printf("and_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_Neg1_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("and_int32 -1%s-2147483647 = %d, wanted -2147483647\n", `&`, got) failed = true } if got := and_int32_Neg1_ssa(-2147483647); got != -2147483647 { fmt.Printf("and_int32 -2147483647%s-1 = %d, wanted -2147483647\n", `&`, got) failed = true } if got := and_Neg1_int32_ssa(-1); got != -1 { fmt.Printf("and_int32 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_int32_Neg1_ssa(-1); got != -1 { fmt.Printf("and_int32 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_Neg1_int32_ssa(0); got != 0 { fmt.Printf("and_int32 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_Neg1_ssa(0); got != 0 { fmt.Printf("and_int32 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg1_int32_ssa(1); got != 1 { fmt.Printf("and_int32 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_Neg1_ssa(1); got != 1 { fmt.Printf("and_int32 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("and_int32 -1%s2147483647 = %d, wanted 2147483647\n", `&`, got) failed = true } if got := and_int32_Neg1_ssa(2147483647); got != 2147483647 { fmt.Printf("and_int32 2147483647%s-1 = %d, wanted 2147483647\n", `&`, got) failed = true } if got := and_0_int32_ssa(-2147483648); got != 0 { fmt.Printf("and_int32 0%s-2147483648 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_0_ssa(-2147483648); got != 0 { fmt.Printf("and_int32 -2147483648%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int32_ssa(-2147483647); got != 0 { fmt.Printf("and_int32 0%s-2147483647 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_0_ssa(-2147483647); got != 0 { fmt.Printf("and_int32 -2147483647%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int32_ssa(-1); got != 0 { fmt.Printf("and_int32 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_0_ssa(-1); got != 0 { fmt.Printf("and_int32 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int32_ssa(0); got != 0 { fmt.Printf("and_int32 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_0_ssa(0); got != 0 { fmt.Printf("and_int32 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int32_ssa(1); got != 0 { fmt.Printf("and_int32 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_0_ssa(1); got != 0 { fmt.Printf("and_int32 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int32_ssa(2147483647); got != 0 { fmt.Printf("and_int32 0%s2147483647 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_0_ssa(2147483647); got != 0 { fmt.Printf("and_int32 2147483647%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int32_ssa(-2147483648); got != 0 { fmt.Printf("and_int32 1%s-2147483648 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_1_ssa(-2147483648); got != 0 { fmt.Printf("and_int32 -2147483648%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int32_ssa(-2147483647); got != 1 { fmt.Printf("and_int32 1%s-2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_1_ssa(-2147483647); got != 1 { fmt.Printf("and_int32 -2147483647%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int32_ssa(-1); got != 1 { fmt.Printf("and_int32 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_1_ssa(-1); got != 1 { fmt.Printf("and_int32 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int32_ssa(0); got != 0 { fmt.Printf("and_int32 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_1_ssa(0); got != 0 { fmt.Printf("and_int32 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int32_ssa(1); got != 1 { fmt.Printf("and_int32 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_1_ssa(1); got != 1 { fmt.Printf("and_int32 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int32_ssa(2147483647); got != 1 { fmt.Printf("and_int32 1%s2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_1_ssa(2147483647); got != 1 { fmt.Printf("and_int32 2147483647%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_2147483647_int32_ssa(-2147483648); got != 0 { fmt.Printf("and_int32 2147483647%s-2147483648 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_2147483647_ssa(-2147483648); got != 0 { fmt.Printf("and_int32 -2147483648%s2147483647 = %d, wanted 0\n", `&`, got) failed = true } if got := and_2147483647_int32_ssa(-2147483647); got != 1 { fmt.Printf("and_int32 2147483647%s-2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_2147483647_ssa(-2147483647); got != 1 { fmt.Printf("and_int32 -2147483647%s2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_2147483647_int32_ssa(-1); got != 2147483647 { fmt.Printf("and_int32 2147483647%s-1 = %d, wanted 2147483647\n", `&`, got) failed = true } if got := and_int32_2147483647_ssa(-1); got != 2147483647 { fmt.Printf("and_int32 -1%s2147483647 = %d, wanted 2147483647\n", `&`, got) failed = true } if got := and_2147483647_int32_ssa(0); got != 0 { fmt.Printf("and_int32 2147483647%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_2147483647_ssa(0); got != 0 { fmt.Printf("and_int32 0%s2147483647 = %d, wanted 0\n", `&`, got) failed = true } if got := and_2147483647_int32_ssa(1); got != 1 { fmt.Printf("and_int32 2147483647%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_2147483647_ssa(1); got != 1 { fmt.Printf("and_int32 1%s2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_2147483647_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("and_int32 2147483647%s2147483647 = %d, wanted 2147483647\n", `&`, got) failed = true } if got := and_int32_2147483647_ssa(2147483647); got != 2147483647 { fmt.Printf("and_int32 2147483647%s2147483647 = %d, wanted 2147483647\n", `&`, got) failed = true } if got := or_Neg2147483648_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("or_int32 -2147483648%s-2147483648 = %d, wanted -2147483648\n", `|`, got) failed = true } if got := or_int32_Neg2147483648_ssa(-2147483648); got != -2147483648 { fmt.Printf("or_int32 -2147483648%s-2147483648 = %d, wanted -2147483648\n", `|`, got) failed = true } if got := or_Neg2147483648_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 -2147483648%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_Neg2147483648_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s-2147483648 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_Neg2147483648_int32_ssa(-1); got != -1 { fmt.Printf("or_int32 -2147483648%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg2147483648_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s-2147483648 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg2147483648_int32_ssa(0); got != -2147483648 { fmt.Printf("or_int32 -2147483648%s0 = %d, wanted -2147483648\n", `|`, got) failed = true } if got := or_int32_Neg2147483648_ssa(0); got != -2147483648 { fmt.Printf("or_int32 0%s-2147483648 = %d, wanted -2147483648\n", `|`, got) failed = true } if got := or_Neg2147483648_int32_ssa(1); got != -2147483647 { fmt.Printf("or_int32 -2147483648%s1 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_Neg2147483648_ssa(1); got != -2147483647 { fmt.Printf("or_int32 1%s-2147483648 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_Neg2147483648_int32_ssa(2147483647); got != -1 { fmt.Printf("or_int32 -2147483648%s2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg2147483648_ssa(2147483647); got != -1 { fmt.Printf("or_int32 2147483647%s-2147483648 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg2147483647_int32_ssa(-2147483648); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s-2147483648 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_Neg2147483647_ssa(-2147483648); got != -2147483647 { fmt.Printf("or_int32 -2147483648%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_Neg2147483647_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_Neg2147483647_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_Neg2147483647_int32_ssa(-1); got != -1 { fmt.Printf("or_int32 -2147483647%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg2147483647_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s-2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg2147483647_int32_ssa(0); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s0 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_Neg2147483647_ssa(0); got != -2147483647 { fmt.Printf("or_int32 0%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_Neg2147483647_int32_ssa(1); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s1 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_Neg2147483647_ssa(1); got != -2147483647 { fmt.Printf("or_int32 1%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_Neg2147483647_int32_ssa(2147483647); got != -1 { fmt.Printf("or_int32 -2147483647%s2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg2147483647_ssa(2147483647); got != -1 { fmt.Printf("or_int32 2147483647%s-2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int32_ssa(-2147483648); got != -1 { fmt.Printf("or_int32 -1%s-2147483648 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg1_ssa(-2147483648); got != -1 { fmt.Printf("or_int32 -2147483648%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int32_ssa(-2147483647); got != -1 { fmt.Printf("or_int32 -1%s-2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg1_ssa(-2147483647); got != -1 { fmt.Printf("or_int32 -2147483647%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int32_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg1_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int32_ssa(0); got != -1 { fmt.Printf("or_int32 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg1_ssa(0); got != -1 { fmt.Printf("or_int32 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int32_ssa(1); got != -1 { fmt.Printf("or_int32 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg1_ssa(1); got != -1 { fmt.Printf("or_int32 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int32_ssa(2147483647); got != -1 { fmt.Printf("or_int32 -1%s2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg1_ssa(2147483647); got != -1 { fmt.Printf("or_int32 2147483647%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("or_int32 0%s-2147483648 = %d, wanted -2147483648\n", `|`, got) failed = true } if got := or_int32_0_ssa(-2147483648); got != -2147483648 { fmt.Printf("or_int32 -2147483648%s0 = %d, wanted -2147483648\n", `|`, got) failed = true } if got := or_0_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 0%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_0_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s0 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_0_int32_ssa(-1); got != -1 { fmt.Printf("or_int32 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_0_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int32_ssa(0); got != 0 { fmt.Printf("or_int32 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_int32_0_ssa(0); got != 0 { fmt.Printf("or_int32 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_int32_ssa(1); got != 1 { fmt.Printf("or_int32 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int32_0_ssa(1); got != 1 { fmt.Printf("or_int32 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("or_int32 0%s2147483647 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_int32_0_ssa(2147483647); got != 2147483647 { fmt.Printf("or_int32 2147483647%s0 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_1_int32_ssa(-2147483648); got != -2147483647 { fmt.Printf("or_int32 1%s-2147483648 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_1_ssa(-2147483648); got != -2147483647 { fmt.Printf("or_int32 -2147483648%s1 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_1_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 1%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_1_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s1 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_1_int32_ssa(-1); got != -1 { fmt.Printf("or_int32 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_1_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_1_int32_ssa(0); got != 1 { fmt.Printf("or_int32 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int32_1_ssa(0); got != 1 { fmt.Printf("or_int32 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int32_ssa(1); got != 1 { fmt.Printf("or_int32 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int32_1_ssa(1); got != 1 { fmt.Printf("or_int32 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("or_int32 1%s2147483647 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_int32_1_ssa(2147483647); got != 2147483647 { fmt.Printf("or_int32 2147483647%s1 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_2147483647_int32_ssa(-2147483648); got != -1 { fmt.Printf("or_int32 2147483647%s-2147483648 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_2147483647_ssa(-2147483648); got != -1 { fmt.Printf("or_int32 -2147483648%s2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_2147483647_int32_ssa(-2147483647); got != -1 { fmt.Printf("or_int32 2147483647%s-2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_2147483647_ssa(-2147483647); got != -1 { fmt.Printf("or_int32 -2147483647%s2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_2147483647_int32_ssa(-1); got != -1 { fmt.Printf("or_int32 2147483647%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_2147483647_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_2147483647_int32_ssa(0); got != 2147483647 { fmt.Printf("or_int32 2147483647%s0 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_int32_2147483647_ssa(0); got != 2147483647 { fmt.Printf("or_int32 0%s2147483647 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_2147483647_int32_ssa(1); got != 2147483647 { fmt.Printf("or_int32 2147483647%s1 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_int32_2147483647_ssa(1); got != 2147483647 { fmt.Printf("or_int32 1%s2147483647 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_2147483647_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("or_int32 2147483647%s2147483647 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_int32_2147483647_ssa(2147483647); got != 2147483647 { fmt.Printf("or_int32 2147483647%s2147483647 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := xor_Neg2147483648_int32_ssa(-2147483648); got != 0 { fmt.Printf("xor_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int32_Neg2147483648_ssa(-2147483648); got != 0 { fmt.Printf("xor_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg2147483648_int32_ssa(-2147483647); got != 1 { fmt.Printf("xor_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int32_Neg2147483648_ssa(-2147483647); got != 1 { fmt.Printf("xor_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg2147483648_int32_ssa(-1); got != 2147483647 { fmt.Printf("xor_int32 -2147483648%s-1 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_int32_Neg2147483648_ssa(-1); got != 2147483647 { fmt.Printf("xor_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_Neg2147483648_int32_ssa(0); got != -2147483648 { fmt.Printf("xor_int32 -2147483648%s0 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_int32_Neg2147483648_ssa(0); got != -2147483648 { fmt.Printf("xor_int32 0%s-2147483648 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_Neg2147483648_int32_ssa(1); got != -2147483647 { fmt.Printf("xor_int32 -2147483648%s1 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_int32_Neg2147483648_ssa(1); got != -2147483647 { fmt.Printf("xor_int32 1%s-2147483648 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_Neg2147483648_int32_ssa(2147483647); got != -1 { fmt.Printf("xor_int32 -2147483648%s2147483647 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int32_Neg2147483648_ssa(2147483647); got != -1 { fmt.Printf("xor_int32 2147483647%s-2147483648 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg2147483647_int32_ssa(-2147483648); got != 1 { fmt.Printf("xor_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int32_Neg2147483647_ssa(-2147483648); got != 1 { fmt.Printf("xor_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg2147483647_int32_ssa(-2147483647); got != 0 { fmt.Printf("xor_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int32_Neg2147483647_ssa(-2147483647); got != 0 { fmt.Printf("xor_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg2147483647_int32_ssa(-1); got != 2147483646 { fmt.Printf("xor_int32 -2147483647%s-1 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_int32_Neg2147483647_ssa(-1); got != 2147483646 { fmt.Printf("xor_int32 -1%s-2147483647 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_Neg2147483647_int32_ssa(0); got != -2147483647 { fmt.Printf("xor_int32 -2147483647%s0 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_int32_Neg2147483647_ssa(0); got != -2147483647 { fmt.Printf("xor_int32 0%s-2147483647 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_Neg2147483647_int32_ssa(1); got != -2147483648 { fmt.Printf("xor_int32 -2147483647%s1 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_int32_Neg2147483647_ssa(1); got != -2147483648 { fmt.Printf("xor_int32 1%s-2147483647 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_Neg2147483647_int32_ssa(2147483647); got != -2 { fmt.Printf("xor_int32 -2147483647%s2147483647 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int32_Neg2147483647_ssa(2147483647); got != -2 { fmt.Printf("xor_int32 2147483647%s-2147483647 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int32_ssa(-2147483648); got != 2147483647 { fmt.Printf("xor_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_int32_Neg1_ssa(-2147483648); got != 2147483647 { fmt.Printf("xor_int32 -2147483648%s-1 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_Neg1_int32_ssa(-2147483647); got != 2147483646 { fmt.Printf("xor_int32 -1%s-2147483647 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_int32_Neg1_ssa(-2147483647); got != 2147483646 { fmt.Printf("xor_int32 -2147483647%s-1 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_Neg1_int32_ssa(-1); got != 0 { fmt.Printf("xor_int32 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int32_Neg1_ssa(-1); got != 0 { fmt.Printf("xor_int32 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg1_int32_ssa(0); got != -1 { fmt.Printf("xor_int32 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int32_Neg1_ssa(0); got != -1 { fmt.Printf("xor_int32 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg1_int32_ssa(1); got != -2 { fmt.Printf("xor_int32 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int32_Neg1_ssa(1); got != -2 { fmt.Printf("xor_int32 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int32_ssa(2147483647); got != -2147483648 { fmt.Printf("xor_int32 -1%s2147483647 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_int32_Neg1_ssa(2147483647); got != -2147483648 { fmt.Printf("xor_int32 2147483647%s-1 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_0_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("xor_int32 0%s-2147483648 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_int32_0_ssa(-2147483648); got != -2147483648 { fmt.Printf("xor_int32 -2147483648%s0 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_0_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("xor_int32 0%s-2147483647 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_int32_0_ssa(-2147483647); got != -2147483647 { fmt.Printf("xor_int32 -2147483647%s0 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_0_int32_ssa(-1); got != -1 { fmt.Printf("xor_int32 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int32_0_ssa(-1); got != -1 { fmt.Printf("xor_int32 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_0_int32_ssa(0); got != 0 { fmt.Printf("xor_int32 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int32_0_ssa(0); got != 0 { fmt.Printf("xor_int32 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_int32_ssa(1); got != 1 { fmt.Printf("xor_int32 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int32_0_ssa(1); got != 1 { fmt.Printf("xor_int32 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("xor_int32 0%s2147483647 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_int32_0_ssa(2147483647); got != 2147483647 { fmt.Printf("xor_int32 2147483647%s0 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_1_int32_ssa(-2147483648); got != -2147483647 { fmt.Printf("xor_int32 1%s-2147483648 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_int32_1_ssa(-2147483648); got != -2147483647 { fmt.Printf("xor_int32 -2147483648%s1 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_1_int32_ssa(-2147483647); got != -2147483648 { fmt.Printf("xor_int32 1%s-2147483647 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_int32_1_ssa(-2147483647); got != -2147483648 { fmt.Printf("xor_int32 -2147483647%s1 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_1_int32_ssa(-1); got != -2 { fmt.Printf("xor_int32 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int32_1_ssa(-1); got != -2 { fmt.Printf("xor_int32 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_1_int32_ssa(0); got != 1 { fmt.Printf("xor_int32 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int32_1_ssa(0); got != 1 { fmt.Printf("xor_int32 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_int32_ssa(1); got != 0 { fmt.Printf("xor_int32 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int32_1_ssa(1); got != 0 { fmt.Printf("xor_int32 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_int32_ssa(2147483647); got != 2147483646 { fmt.Printf("xor_int32 1%s2147483647 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_int32_1_ssa(2147483647); got != 2147483646 { fmt.Printf("xor_int32 2147483647%s1 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_2147483647_int32_ssa(-2147483648); got != -1 { fmt.Printf("xor_int32 2147483647%s-2147483648 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int32_2147483647_ssa(-2147483648); got != -1 { fmt.Printf("xor_int32 -2147483648%s2147483647 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_2147483647_int32_ssa(-2147483647); got != -2 { fmt.Printf("xor_int32 2147483647%s-2147483647 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int32_2147483647_ssa(-2147483647); got != -2 { fmt.Printf("xor_int32 -2147483647%s2147483647 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_2147483647_int32_ssa(-1); got != -2147483648 { fmt.Printf("xor_int32 2147483647%s-1 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_int32_2147483647_ssa(-1); got != -2147483648 { fmt.Printf("xor_int32 -1%s2147483647 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_2147483647_int32_ssa(0); got != 2147483647 { fmt.Printf("xor_int32 2147483647%s0 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_int32_2147483647_ssa(0); got != 2147483647 { fmt.Printf("xor_int32 0%s2147483647 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_2147483647_int32_ssa(1); got != 2147483646 { fmt.Printf("xor_int32 2147483647%s1 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_int32_2147483647_ssa(1); got != 2147483646 { fmt.Printf("xor_int32 1%s2147483647 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_2147483647_int32_ssa(2147483647); got != 0 { fmt.Printf("xor_int32 2147483647%s2147483647 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int32_2147483647_ssa(2147483647); got != 0 { fmt.Printf("xor_int32 2147483647%s2147483647 = %d, wanted 0\n", `^`, got) failed = true } if got := add_0_uint16_ssa(0); got != 0 { fmt.Printf("add_uint16 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint16_0_ssa(0); got != 0 { fmt.Printf("add_uint16 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_uint16_ssa(1); got != 1 { fmt.Printf("add_uint16 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint16_0_ssa(1); got != 1 { fmt.Printf("add_uint16 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_uint16_ssa(65535); got != 65535 { fmt.Printf("add_uint16 0%s65535 = %d, wanted 65535\n", `+`, got) failed = true } if got := add_uint16_0_ssa(65535); got != 65535 { fmt.Printf("add_uint16 65535%s0 = %d, wanted 65535\n", `+`, got) failed = true } if got := add_1_uint16_ssa(0); got != 1 { fmt.Printf("add_uint16 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint16_1_ssa(0); got != 1 { fmt.Printf("add_uint16 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_uint16_ssa(1); got != 2 { fmt.Printf("add_uint16 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_uint16_1_ssa(1); got != 2 { fmt.Printf("add_uint16 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_uint16_ssa(65535); got != 0 { fmt.Printf("add_uint16 1%s65535 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint16_1_ssa(65535); got != 0 { fmt.Printf("add_uint16 65535%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_65535_uint16_ssa(0); got != 65535 { fmt.Printf("add_uint16 65535%s0 = %d, wanted 65535\n", `+`, got) failed = true } if got := add_uint16_65535_ssa(0); got != 65535 { fmt.Printf("add_uint16 0%s65535 = %d, wanted 65535\n", `+`, got) failed = true } if got := add_65535_uint16_ssa(1); got != 0 { fmt.Printf("add_uint16 65535%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint16_65535_ssa(1); got != 0 { fmt.Printf("add_uint16 1%s65535 = %d, wanted 0\n", `+`, got) failed = true } if got := add_65535_uint16_ssa(65535); got != 65534 { fmt.Printf("add_uint16 65535%s65535 = %d, wanted 65534\n", `+`, got) failed = true } if got := add_uint16_65535_ssa(65535); got != 65534 { fmt.Printf("add_uint16 65535%s65535 = %d, wanted 65534\n", `+`, got) failed = true } if got := sub_0_uint16_ssa(0); got != 0 { fmt.Printf("sub_uint16 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint16_0_ssa(0); got != 0 { fmt.Printf("sub_uint16 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_uint16_ssa(1); got != 65535 { fmt.Printf("sub_uint16 0%s1 = %d, wanted 65535\n", `-`, got) failed = true } if got := sub_uint16_0_ssa(1); got != 1 { fmt.Printf("sub_uint16 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_uint16_ssa(65535); got != 1 { fmt.Printf("sub_uint16 0%s65535 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint16_0_ssa(65535); got != 65535 { fmt.Printf("sub_uint16 65535%s0 = %d, wanted 65535\n", `-`, got) failed = true } if got := sub_1_uint16_ssa(0); got != 1 { fmt.Printf("sub_uint16 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint16_1_ssa(0); got != 65535 { fmt.Printf("sub_uint16 0%s1 = %d, wanted 65535\n", `-`, got) failed = true } if got := sub_1_uint16_ssa(1); got != 0 { fmt.Printf("sub_uint16 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint16_1_ssa(1); got != 0 { fmt.Printf("sub_uint16 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_uint16_ssa(65535); got != 2 { fmt.Printf("sub_uint16 1%s65535 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_uint16_1_ssa(65535); got != 65534 { fmt.Printf("sub_uint16 65535%s1 = %d, wanted 65534\n", `-`, got) failed = true } if got := sub_65535_uint16_ssa(0); got != 65535 { fmt.Printf("sub_uint16 65535%s0 = %d, wanted 65535\n", `-`, got) failed = true } if got := sub_uint16_65535_ssa(0); got != 1 { fmt.Printf("sub_uint16 0%s65535 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_65535_uint16_ssa(1); got != 65534 { fmt.Printf("sub_uint16 65535%s1 = %d, wanted 65534\n", `-`, got) failed = true } if got := sub_uint16_65535_ssa(1); got != 2 { fmt.Printf("sub_uint16 1%s65535 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_65535_uint16_ssa(65535); got != 0 { fmt.Printf("sub_uint16 65535%s65535 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint16_65535_ssa(65535); got != 0 { fmt.Printf("sub_uint16 65535%s65535 = %d, wanted 0\n", `-`, got) failed = true } if got := div_0_uint16_ssa(1); got != 0 { fmt.Printf("div_uint16 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_uint16_ssa(65535); got != 0 { fmt.Printf("div_uint16 0%s65535 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint16_1_ssa(0); got != 0 { fmt.Printf("div_uint16 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_uint16_ssa(1); got != 1 { fmt.Printf("div_uint16 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint16_1_ssa(1); got != 1 { fmt.Printf("div_uint16 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_uint16_ssa(65535); got != 0 { fmt.Printf("div_uint16 1%s65535 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint16_1_ssa(65535); got != 65535 { fmt.Printf("div_uint16 65535%s1 = %d, wanted 65535\n", `/`, got) failed = true } if got := div_uint16_65535_ssa(0); got != 0 { fmt.Printf("div_uint16 0%s65535 = %d, wanted 0\n", `/`, got) failed = true } if got := div_65535_uint16_ssa(1); got != 65535 { fmt.Printf("div_uint16 65535%s1 = %d, wanted 65535\n", `/`, got) failed = true } if got := div_uint16_65535_ssa(1); got != 0 { fmt.Printf("div_uint16 1%s65535 = %d, wanted 0\n", `/`, got) failed = true } if got := div_65535_uint16_ssa(65535); got != 1 { fmt.Printf("div_uint16 65535%s65535 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint16_65535_ssa(65535); got != 1 { fmt.Printf("div_uint16 65535%s65535 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_0_uint16_ssa(0); got != 0 { fmt.Printf("mul_uint16 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint16_0_ssa(0); got != 0 { fmt.Printf("mul_uint16 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint16_ssa(1); got != 0 { fmt.Printf("mul_uint16 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint16_0_ssa(1); got != 0 { fmt.Printf("mul_uint16 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint16_ssa(65535); got != 0 { fmt.Printf("mul_uint16 0%s65535 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint16_0_ssa(65535); got != 0 { fmt.Printf("mul_uint16 65535%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint16_ssa(0); got != 0 { fmt.Printf("mul_uint16 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint16_1_ssa(0); got != 0 { fmt.Printf("mul_uint16 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint16_ssa(1); got != 1 { fmt.Printf("mul_uint16 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint16_1_ssa(1); got != 1 { fmt.Printf("mul_uint16 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_uint16_ssa(65535); got != 65535 { fmt.Printf("mul_uint16 1%s65535 = %d, wanted 65535\n", `*`, got) failed = true } if got := mul_uint16_1_ssa(65535); got != 65535 { fmt.Printf("mul_uint16 65535%s1 = %d, wanted 65535\n", `*`, got) failed = true } if got := mul_65535_uint16_ssa(0); got != 0 { fmt.Printf("mul_uint16 65535%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint16_65535_ssa(0); got != 0 { fmt.Printf("mul_uint16 0%s65535 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_65535_uint16_ssa(1); got != 65535 { fmt.Printf("mul_uint16 65535%s1 = %d, wanted 65535\n", `*`, got) failed = true } if got := mul_uint16_65535_ssa(1); got != 65535 { fmt.Printf("mul_uint16 1%s65535 = %d, wanted 65535\n", `*`, got) failed = true } if got := mul_65535_uint16_ssa(65535); got != 1 { fmt.Printf("mul_uint16 65535%s65535 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint16_65535_ssa(65535); got != 1 { fmt.Printf("mul_uint16 65535%s65535 = %d, wanted 1\n", `*`, got) failed = true } if got := lsh_0_uint16_ssa(0); got != 0 { fmt.Printf("lsh_uint16 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint16_0_ssa(0); got != 0 { fmt.Printf("lsh_uint16 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_0_uint16_ssa(1); got != 0 { fmt.Printf("lsh_uint16 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint16_0_ssa(1); got != 1 { fmt.Printf("lsh_uint16 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_0_uint16_ssa(65535); got != 0 { fmt.Printf("lsh_uint16 0%s65535 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint16_0_ssa(65535); got != 65535 { fmt.Printf("lsh_uint16 65535%s0 = %d, wanted 65535\n", `<<`, got) failed = true } if got := lsh_1_uint16_ssa(0); got != 1 { fmt.Printf("lsh_uint16 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_uint16_1_ssa(0); got != 0 { fmt.Printf("lsh_uint16 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_1_uint16_ssa(1); got != 2 { fmt.Printf("lsh_uint16 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_uint16_1_ssa(1); got != 2 { fmt.Printf("lsh_uint16 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_1_uint16_ssa(65535); got != 0 { fmt.Printf("lsh_uint16 1%s65535 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint16_1_ssa(65535); got != 65534 { fmt.Printf("lsh_uint16 65535%s1 = %d, wanted 65534\n", `<<`, got) failed = true } if got := lsh_65535_uint16_ssa(0); got != 65535 { fmt.Printf("lsh_uint16 65535%s0 = %d, wanted 65535\n", `<<`, got) failed = true } if got := lsh_uint16_65535_ssa(0); got != 0 { fmt.Printf("lsh_uint16 0%s65535 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_65535_uint16_ssa(1); got != 65534 { fmt.Printf("lsh_uint16 65535%s1 = %d, wanted 65534\n", `<<`, got) failed = true } if got := lsh_uint16_65535_ssa(1); got != 0 { fmt.Printf("lsh_uint16 1%s65535 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_65535_uint16_ssa(65535); got != 0 { fmt.Printf("lsh_uint16 65535%s65535 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint16_65535_ssa(65535); got != 0 { fmt.Printf("lsh_uint16 65535%s65535 = %d, wanted 0\n", `<<`, got) failed = true } if got := rsh_0_uint16_ssa(0); got != 0 { fmt.Printf("rsh_uint16 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint16_0_ssa(0); got != 0 { fmt.Printf("rsh_uint16 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_0_uint16_ssa(1); got != 0 { fmt.Printf("rsh_uint16 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint16_0_ssa(1); got != 1 { fmt.Printf("rsh_uint16 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_0_uint16_ssa(65535); got != 0 { fmt.Printf("rsh_uint16 0%s65535 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint16_0_ssa(65535); got != 65535 { fmt.Printf("rsh_uint16 65535%s0 = %d, wanted 65535\n", `>>`, got) failed = true } if got := rsh_1_uint16_ssa(0); got != 1 { fmt.Printf("rsh_uint16 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_uint16_1_ssa(0); got != 0 { fmt.Printf("rsh_uint16 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint16_ssa(1); got != 0 { fmt.Printf("rsh_uint16 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint16_1_ssa(1); got != 0 { fmt.Printf("rsh_uint16 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint16_ssa(65535); got != 0 { fmt.Printf("rsh_uint16 1%s65535 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint16_1_ssa(65535); got != 32767 { fmt.Printf("rsh_uint16 65535%s1 = %d, wanted 32767\n", `>>`, got) failed = true } if got := rsh_65535_uint16_ssa(0); got != 65535 { fmt.Printf("rsh_uint16 65535%s0 = %d, wanted 65535\n", `>>`, got) failed = true } if got := rsh_uint16_65535_ssa(0); got != 0 { fmt.Printf("rsh_uint16 0%s65535 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_65535_uint16_ssa(1); got != 32767 { fmt.Printf("rsh_uint16 65535%s1 = %d, wanted 32767\n", `>>`, got) failed = true } if got := rsh_uint16_65535_ssa(1); got != 0 { fmt.Printf("rsh_uint16 1%s65535 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_65535_uint16_ssa(65535); got != 0 { fmt.Printf("rsh_uint16 65535%s65535 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint16_65535_ssa(65535); got != 0 { fmt.Printf("rsh_uint16 65535%s65535 = %d, wanted 0\n", `>>`, got) failed = true } if got := mod_0_uint16_ssa(1); got != 0 { fmt.Printf("mod_uint16 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_uint16_ssa(65535); got != 0 { fmt.Printf("mod_uint16 0%s65535 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint16_1_ssa(0); got != 0 { fmt.Printf("mod_uint16 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint16_ssa(1); got != 0 { fmt.Printf("mod_uint16 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint16_1_ssa(1); got != 0 { fmt.Printf("mod_uint16 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint16_ssa(65535); got != 1 { fmt.Printf("mod_uint16 1%s65535 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_uint16_1_ssa(65535); got != 0 { fmt.Printf("mod_uint16 65535%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint16_65535_ssa(0); got != 0 { fmt.Printf("mod_uint16 0%s65535 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_65535_uint16_ssa(1); got != 0 { fmt.Printf("mod_uint16 65535%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint16_65535_ssa(1); got != 1 { fmt.Printf("mod_uint16 1%s65535 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_65535_uint16_ssa(65535); got != 0 { fmt.Printf("mod_uint16 65535%s65535 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint16_65535_ssa(65535); got != 0 { fmt.Printf("mod_uint16 65535%s65535 = %d, wanted 0\n", `%`, got) failed = true } if got := and_0_uint16_ssa(0); got != 0 { fmt.Printf("and_uint16 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint16_0_ssa(0); got != 0 { fmt.Printf("and_uint16 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint16_ssa(1); got != 0 { fmt.Printf("and_uint16 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint16_0_ssa(1); got != 0 { fmt.Printf("and_uint16 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint16_ssa(65535); got != 0 { fmt.Printf("and_uint16 0%s65535 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint16_0_ssa(65535); got != 0 { fmt.Printf("and_uint16 65535%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint16_ssa(0); got != 0 { fmt.Printf("and_uint16 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint16_1_ssa(0); got != 0 { fmt.Printf("and_uint16 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint16_ssa(1); got != 1 { fmt.Printf("and_uint16 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint16_1_ssa(1); got != 1 { fmt.Printf("and_uint16 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_uint16_ssa(65535); got != 1 { fmt.Printf("and_uint16 1%s65535 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint16_1_ssa(65535); got != 1 { fmt.Printf("and_uint16 65535%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_65535_uint16_ssa(0); got != 0 { fmt.Printf("and_uint16 65535%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint16_65535_ssa(0); got != 0 { fmt.Printf("and_uint16 0%s65535 = %d, wanted 0\n", `&`, got) failed = true } if got := and_65535_uint16_ssa(1); got != 1 { fmt.Printf("and_uint16 65535%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint16_65535_ssa(1); got != 1 { fmt.Printf("and_uint16 1%s65535 = %d, wanted 1\n", `&`, got) failed = true } if got := and_65535_uint16_ssa(65535); got != 65535 { fmt.Printf("and_uint16 65535%s65535 = %d, wanted 65535\n", `&`, got) failed = true } if got := and_uint16_65535_ssa(65535); got != 65535 { fmt.Printf("and_uint16 65535%s65535 = %d, wanted 65535\n", `&`, got) failed = true } if got := or_0_uint16_ssa(0); got != 0 { fmt.Printf("or_uint16 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_uint16_0_ssa(0); got != 0 { fmt.Printf("or_uint16 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_uint16_ssa(1); got != 1 { fmt.Printf("or_uint16 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint16_0_ssa(1); got != 1 { fmt.Printf("or_uint16 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_uint16_ssa(65535); got != 65535 { fmt.Printf("or_uint16 0%s65535 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_uint16_0_ssa(65535); got != 65535 { fmt.Printf("or_uint16 65535%s0 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_1_uint16_ssa(0); got != 1 { fmt.Printf("or_uint16 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint16_1_ssa(0); got != 1 { fmt.Printf("or_uint16 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint16_ssa(1); got != 1 { fmt.Printf("or_uint16 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint16_1_ssa(1); got != 1 { fmt.Printf("or_uint16 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint16_ssa(65535); got != 65535 { fmt.Printf("or_uint16 1%s65535 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_uint16_1_ssa(65535); got != 65535 { fmt.Printf("or_uint16 65535%s1 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_65535_uint16_ssa(0); got != 65535 { fmt.Printf("or_uint16 65535%s0 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_uint16_65535_ssa(0); got != 65535 { fmt.Printf("or_uint16 0%s65535 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_65535_uint16_ssa(1); got != 65535 { fmt.Printf("or_uint16 65535%s1 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_uint16_65535_ssa(1); got != 65535 { fmt.Printf("or_uint16 1%s65535 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_65535_uint16_ssa(65535); got != 65535 { fmt.Printf("or_uint16 65535%s65535 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_uint16_65535_ssa(65535); got != 65535 { fmt.Printf("or_uint16 65535%s65535 = %d, wanted 65535\n", `|`, got) failed = true } if got := xor_0_uint16_ssa(0); got != 0 { fmt.Printf("xor_uint16 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint16_0_ssa(0); got != 0 { fmt.Printf("xor_uint16 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_uint16_ssa(1); got != 1 { fmt.Printf("xor_uint16 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint16_0_ssa(1); got != 1 { fmt.Printf("xor_uint16 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_uint16_ssa(65535); got != 65535 { fmt.Printf("xor_uint16 0%s65535 = %d, wanted 65535\n", `^`, got) failed = true } if got := xor_uint16_0_ssa(65535); got != 65535 { fmt.Printf("xor_uint16 65535%s0 = %d, wanted 65535\n", `^`, got) failed = true } if got := xor_1_uint16_ssa(0); got != 1 { fmt.Printf("xor_uint16 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint16_1_ssa(0); got != 1 { fmt.Printf("xor_uint16 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_uint16_ssa(1); got != 0 { fmt.Printf("xor_uint16 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint16_1_ssa(1); got != 0 { fmt.Printf("xor_uint16 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_uint16_ssa(65535); got != 65534 { fmt.Printf("xor_uint16 1%s65535 = %d, wanted 65534\n", `^`, got) failed = true } if got := xor_uint16_1_ssa(65535); got != 65534 { fmt.Printf("xor_uint16 65535%s1 = %d, wanted 65534\n", `^`, got) failed = true } if got := xor_65535_uint16_ssa(0); got != 65535 { fmt.Printf("xor_uint16 65535%s0 = %d, wanted 65535\n", `^`, got) failed = true } if got := xor_uint16_65535_ssa(0); got != 65535 { fmt.Printf("xor_uint16 0%s65535 = %d, wanted 65535\n", `^`, got) failed = true } if got := xor_65535_uint16_ssa(1); got != 65534 { fmt.Printf("xor_uint16 65535%s1 = %d, wanted 65534\n", `^`, got) failed = true } if got := xor_uint16_65535_ssa(1); got != 65534 { fmt.Printf("xor_uint16 1%s65535 = %d, wanted 65534\n", `^`, got) failed = true } if got := xor_65535_uint16_ssa(65535); got != 0 { fmt.Printf("xor_uint16 65535%s65535 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint16_65535_ssa(65535); got != 0 { fmt.Printf("xor_uint16 65535%s65535 = %d, wanted 0\n", `^`, got) failed = true } if got := add_Neg32768_int16_ssa(-32768); got != 0 { fmt.Printf("add_int16 -32768%s-32768 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(-32768); got != 0 { fmt.Printf("add_int16 -32768%s-32768 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg32768_int16_ssa(-32767); got != 1 { fmt.Printf("add_int16 -32768%s-32767 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(-32767); got != 1 { fmt.Printf("add_int16 -32767%s-32768 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg32768_int16_ssa(-1); got != 32767 { fmt.Printf("add_int16 -32768%s-1 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(-1); got != 32767 { fmt.Printf("add_int16 -1%s-32768 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_Neg32768_int16_ssa(0); got != -32768 { fmt.Printf("add_int16 -32768%s0 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(0); got != -32768 { fmt.Printf("add_int16 0%s-32768 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_Neg32768_int16_ssa(1); got != -32767 { fmt.Printf("add_int16 -32768%s1 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(1); got != -32767 { fmt.Printf("add_int16 1%s-32768 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_Neg32768_int16_ssa(32766); got != -2 { fmt.Printf("add_int16 -32768%s32766 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(32766); got != -2 { fmt.Printf("add_int16 32766%s-32768 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg32768_int16_ssa(32767); got != -1 { fmt.Printf("add_int16 -32768%s32767 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(32767); got != -1 { fmt.Printf("add_int16 32767%s-32768 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(-32768); got != 1 { fmt.Printf("add_int16 -32767%s-32768 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(-32768); got != 1 { fmt.Printf("add_int16 -32768%s-32767 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(-32767); got != 2 { fmt.Printf("add_int16 -32767%s-32767 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(-32767); got != 2 { fmt.Printf("add_int16 -32767%s-32767 = %d, wanted 2\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(-1); got != -32768 { fmt.Printf("add_int16 -32767%s-1 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(-1); got != -32768 { fmt.Printf("add_int16 -1%s-32767 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(0); got != -32767 { fmt.Printf("add_int16 -32767%s0 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(0); got != -32767 { fmt.Printf("add_int16 0%s-32767 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(1); got != -32766 { fmt.Printf("add_int16 -32767%s1 = %d, wanted -32766\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(1); got != -32766 { fmt.Printf("add_int16 1%s-32767 = %d, wanted -32766\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(32766); got != -1 { fmt.Printf("add_int16 -32767%s32766 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(32766); got != -1 { fmt.Printf("add_int16 32766%s-32767 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(32767); got != 0 { fmt.Printf("add_int16 -32767%s32767 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(32767); got != 0 { fmt.Printf("add_int16 32767%s-32767 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(-32768); got != 32767 { fmt.Printf("add_int16 -1%s-32768 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(-32768); got != 32767 { fmt.Printf("add_int16 -32768%s-1 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(-32767); got != -32768 { fmt.Printf("add_int16 -1%s-32767 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(-32767); got != -32768 { fmt.Printf("add_int16 -32767%s-1 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(-1); got != -2 { fmt.Printf("add_int16 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(-1); got != -2 { fmt.Printf("add_int16 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(0); got != -1 { fmt.Printf("add_int16 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(0); got != -1 { fmt.Printf("add_int16 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(1); got != 0 { fmt.Printf("add_int16 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(1); got != 0 { fmt.Printf("add_int16 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(32766); got != 32765 { fmt.Printf("add_int16 -1%s32766 = %d, wanted 32765\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(32766); got != 32765 { fmt.Printf("add_int16 32766%s-1 = %d, wanted 32765\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(32767); got != 32766 { fmt.Printf("add_int16 -1%s32767 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(32767); got != 32766 { fmt.Printf("add_int16 32767%s-1 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_0_int16_ssa(-32768); got != -32768 { fmt.Printf("add_int16 0%s-32768 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_int16_0_ssa(-32768); got != -32768 { fmt.Printf("add_int16 -32768%s0 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_0_int16_ssa(-32767); got != -32767 { fmt.Printf("add_int16 0%s-32767 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_int16_0_ssa(-32767); got != -32767 { fmt.Printf("add_int16 -32767%s0 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_0_int16_ssa(-1); got != -1 { fmt.Printf("add_int16 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int16_0_ssa(-1); got != -1 { fmt.Printf("add_int16 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_0_int16_ssa(0); got != 0 { fmt.Printf("add_int16 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int16_0_ssa(0); got != 0 { fmt.Printf("add_int16 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_int16_ssa(1); got != 1 { fmt.Printf("add_int16 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int16_0_ssa(1); got != 1 { fmt.Printf("add_int16 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_int16_ssa(32766); got != 32766 { fmt.Printf("add_int16 0%s32766 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_int16_0_ssa(32766); got != 32766 { fmt.Printf("add_int16 32766%s0 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_0_int16_ssa(32767); got != 32767 { fmt.Printf("add_int16 0%s32767 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_int16_0_ssa(32767); got != 32767 { fmt.Printf("add_int16 32767%s0 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_1_int16_ssa(-32768); got != -32767 { fmt.Printf("add_int16 1%s-32768 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_int16_1_ssa(-32768); got != -32767 { fmt.Printf("add_int16 -32768%s1 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_1_int16_ssa(-32767); got != -32766 { fmt.Printf("add_int16 1%s-32767 = %d, wanted -32766\n", `+`, got) failed = true } if got := add_int16_1_ssa(-32767); got != -32766 { fmt.Printf("add_int16 -32767%s1 = %d, wanted -32766\n", `+`, got) failed = true } if got := add_1_int16_ssa(-1); got != 0 { fmt.Printf("add_int16 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int16_1_ssa(-1); got != 0 { fmt.Printf("add_int16 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_1_int16_ssa(0); got != 1 { fmt.Printf("add_int16 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int16_1_ssa(0); got != 1 { fmt.Printf("add_int16 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_int16_ssa(1); got != 2 { fmt.Printf("add_int16 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int16_1_ssa(1); got != 2 { fmt.Printf("add_int16 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_int16_ssa(32766); got != 32767 { fmt.Printf("add_int16 1%s32766 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_int16_1_ssa(32766); got != 32767 { fmt.Printf("add_int16 32766%s1 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_1_int16_ssa(32767); got != -32768 { fmt.Printf("add_int16 1%s32767 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_int16_1_ssa(32767); got != -32768 { fmt.Printf("add_int16 32767%s1 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_32766_int16_ssa(-32768); got != -2 { fmt.Printf("add_int16 32766%s-32768 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int16_32766_ssa(-32768); got != -2 { fmt.Printf("add_int16 -32768%s32766 = %d, wanted -2\n", `+`, got) failed = true } if got := add_32766_int16_ssa(-32767); got != -1 { fmt.Printf("add_int16 32766%s-32767 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int16_32766_ssa(-32767); got != -1 { fmt.Printf("add_int16 -32767%s32766 = %d, wanted -1\n", `+`, got) failed = true } if got := add_32766_int16_ssa(-1); got != 32765 { fmt.Printf("add_int16 32766%s-1 = %d, wanted 32765\n", `+`, got) failed = true } if got := add_int16_32766_ssa(-1); got != 32765 { fmt.Printf("add_int16 -1%s32766 = %d, wanted 32765\n", `+`, got) failed = true } if got := add_32766_int16_ssa(0); got != 32766 { fmt.Printf("add_int16 32766%s0 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_int16_32766_ssa(0); got != 32766 { fmt.Printf("add_int16 0%s32766 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_32766_int16_ssa(1); got != 32767 { fmt.Printf("add_int16 32766%s1 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_int16_32766_ssa(1); got != 32767 { fmt.Printf("add_int16 1%s32766 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_32766_int16_ssa(32766); got != -4 { fmt.Printf("add_int16 32766%s32766 = %d, wanted -4\n", `+`, got) failed = true } if got := add_int16_32766_ssa(32766); got != -4 { fmt.Printf("add_int16 32766%s32766 = %d, wanted -4\n", `+`, got) failed = true } if got := add_32766_int16_ssa(32767); got != -3 { fmt.Printf("add_int16 32766%s32767 = %d, wanted -3\n", `+`, got) failed = true } if got := add_int16_32766_ssa(32767); got != -3 { fmt.Printf("add_int16 32767%s32766 = %d, wanted -3\n", `+`, got) failed = true } if got := add_32767_int16_ssa(-32768); got != -1 { fmt.Printf("add_int16 32767%s-32768 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int16_32767_ssa(-32768); got != -1 { fmt.Printf("add_int16 -32768%s32767 = %d, wanted -1\n", `+`, got) failed = true } if got := add_32767_int16_ssa(-32767); got != 0 { fmt.Printf("add_int16 32767%s-32767 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int16_32767_ssa(-32767); got != 0 { fmt.Printf("add_int16 -32767%s32767 = %d, wanted 0\n", `+`, got) failed = true } if got := add_32767_int16_ssa(-1); got != 32766 { fmt.Printf("add_int16 32767%s-1 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_int16_32767_ssa(-1); got != 32766 { fmt.Printf("add_int16 -1%s32767 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_32767_int16_ssa(0); got != 32767 { fmt.Printf("add_int16 32767%s0 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_int16_32767_ssa(0); got != 32767 { fmt.Printf("add_int16 0%s32767 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_32767_int16_ssa(1); got != -32768 { fmt.Printf("add_int16 32767%s1 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_int16_32767_ssa(1); got != -32768 { fmt.Printf("add_int16 1%s32767 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_32767_int16_ssa(32766); got != -3 { fmt.Printf("add_int16 32767%s32766 = %d, wanted -3\n", `+`, got) failed = true } if got := add_int16_32767_ssa(32766); got != -3 { fmt.Printf("add_int16 32766%s32767 = %d, wanted -3\n", `+`, got) failed = true } if got := add_32767_int16_ssa(32767); got != -2 { fmt.Printf("add_int16 32767%s32767 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int16_32767_ssa(32767); got != -2 { fmt.Printf("add_int16 32767%s32767 = %d, wanted -2\n", `+`, got) failed = true } if got := sub_Neg32768_int16_ssa(-32768); got != 0 { fmt.Printf("sub_int16 -32768%s-32768 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(-32768); got != 0 { fmt.Printf("sub_int16 -32768%s-32768 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg32768_int16_ssa(-32767); got != -1 { fmt.Printf("sub_int16 -32768%s-32767 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(-32767); got != 1 { fmt.Printf("sub_int16 -32767%s-32768 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg32768_int16_ssa(-1); got != -32767 { fmt.Printf("sub_int16 -32768%s-1 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(-1); got != 32767 { fmt.Printf("sub_int16 -1%s-32768 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_Neg32768_int16_ssa(0); got != -32768 { fmt.Printf("sub_int16 -32768%s0 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(0); got != -32768 { fmt.Printf("sub_int16 0%s-32768 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_Neg32768_int16_ssa(1); got != 32767 { fmt.Printf("sub_int16 -32768%s1 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(1); got != -32767 { fmt.Printf("sub_int16 1%s-32768 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_Neg32768_int16_ssa(32766); got != 2 { fmt.Printf("sub_int16 -32768%s32766 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(32766); got != -2 { fmt.Printf("sub_int16 32766%s-32768 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg32768_int16_ssa(32767); got != 1 { fmt.Printf("sub_int16 -32768%s32767 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(32767); got != -1 { fmt.Printf("sub_int16 32767%s-32768 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(-32768); got != 1 { fmt.Printf("sub_int16 -32767%s-32768 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(-32768); got != -1 { fmt.Printf("sub_int16 -32768%s-32767 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(-32767); got != 0 { fmt.Printf("sub_int16 -32767%s-32767 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(-32767); got != 0 { fmt.Printf("sub_int16 -32767%s-32767 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(-1); got != -32766 { fmt.Printf("sub_int16 -32767%s-1 = %d, wanted -32766\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(-1); got != 32766 { fmt.Printf("sub_int16 -1%s-32767 = %d, wanted 32766\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(0); got != -32767 { fmt.Printf("sub_int16 -32767%s0 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(0); got != 32767 { fmt.Printf("sub_int16 0%s-32767 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(1); got != -32768 { fmt.Printf("sub_int16 -32767%s1 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(1); got != -32768 { fmt.Printf("sub_int16 1%s-32767 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(32766); got != 3 { fmt.Printf("sub_int16 -32767%s32766 = %d, wanted 3\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(32766); got != -3 { fmt.Printf("sub_int16 32766%s-32767 = %d, wanted -3\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(32767); got != 2 { fmt.Printf("sub_int16 -32767%s32767 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(32767); got != -2 { fmt.Printf("sub_int16 32767%s-32767 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(-32768); got != 32767 { fmt.Printf("sub_int16 -1%s-32768 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(-32768); got != -32767 { fmt.Printf("sub_int16 -32768%s-1 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(-32767); got != 32766 { fmt.Printf("sub_int16 -1%s-32767 = %d, wanted 32766\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(-32767); got != -32766 { fmt.Printf("sub_int16 -32767%s-1 = %d, wanted -32766\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(-1); got != 0 { fmt.Printf("sub_int16 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(-1); got != 0 { fmt.Printf("sub_int16 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(0); got != -1 { fmt.Printf("sub_int16 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(0); got != 1 { fmt.Printf("sub_int16 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(1); got != -2 { fmt.Printf("sub_int16 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(1); got != 2 { fmt.Printf("sub_int16 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(32766); got != -32767 { fmt.Printf("sub_int16 -1%s32766 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(32766); got != 32767 { fmt.Printf("sub_int16 32766%s-1 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(32767); got != -32768 { fmt.Printf("sub_int16 -1%s32767 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(32767); got != -32768 { fmt.Printf("sub_int16 32767%s-1 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_0_int16_ssa(-32768); got != -32768 { fmt.Printf("sub_int16 0%s-32768 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_int16_0_ssa(-32768); got != -32768 { fmt.Printf("sub_int16 -32768%s0 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_0_int16_ssa(-32767); got != 32767 { fmt.Printf("sub_int16 0%s-32767 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_int16_0_ssa(-32767); got != -32767 { fmt.Printf("sub_int16 -32767%s0 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_0_int16_ssa(-1); got != 1 { fmt.Printf("sub_int16 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int16_0_ssa(-1); got != -1 { fmt.Printf("sub_int16 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_0_int16_ssa(0); got != 0 { fmt.Printf("sub_int16 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_0_ssa(0); got != 0 { fmt.Printf("sub_int16 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_int16_ssa(1); got != -1 { fmt.Printf("sub_int16 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int16_0_ssa(1); got != 1 { fmt.Printf("sub_int16 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_int16_ssa(32766); got != -32766 { fmt.Printf("sub_int16 0%s32766 = %d, wanted -32766\n", `-`, got) failed = true } if got := sub_int16_0_ssa(32766); got != 32766 { fmt.Printf("sub_int16 32766%s0 = %d, wanted 32766\n", `-`, got) failed = true } if got := sub_0_int16_ssa(32767); got != -32767 { fmt.Printf("sub_int16 0%s32767 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_int16_0_ssa(32767); got != 32767 { fmt.Printf("sub_int16 32767%s0 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_1_int16_ssa(-32768); got != -32767 { fmt.Printf("sub_int16 1%s-32768 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_int16_1_ssa(-32768); got != 32767 { fmt.Printf("sub_int16 -32768%s1 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_1_int16_ssa(-32767); got != -32768 { fmt.Printf("sub_int16 1%s-32767 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_int16_1_ssa(-32767); got != -32768 { fmt.Printf("sub_int16 -32767%s1 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_1_int16_ssa(-1); got != 2 { fmt.Printf("sub_int16 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int16_1_ssa(-1); got != -2 { fmt.Printf("sub_int16 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_1_int16_ssa(0); got != 1 { fmt.Printf("sub_int16 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int16_1_ssa(0); got != -1 { fmt.Printf("sub_int16 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_1_int16_ssa(1); got != 0 { fmt.Printf("sub_int16 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_1_ssa(1); got != 0 { fmt.Printf("sub_int16 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_int16_ssa(32766); got != -32765 { fmt.Printf("sub_int16 1%s32766 = %d, wanted -32765\n", `-`, got) failed = true } if got := sub_int16_1_ssa(32766); got != 32765 { fmt.Printf("sub_int16 32766%s1 = %d, wanted 32765\n", `-`, got) failed = true } if got := sub_1_int16_ssa(32767); got != -32766 { fmt.Printf("sub_int16 1%s32767 = %d, wanted -32766\n", `-`, got) failed = true } if got := sub_int16_1_ssa(32767); got != 32766 { fmt.Printf("sub_int16 32767%s1 = %d, wanted 32766\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(-32768); got != -2 { fmt.Printf("sub_int16 32766%s-32768 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(-32768); got != 2 { fmt.Printf("sub_int16 -32768%s32766 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(-32767); got != -3 { fmt.Printf("sub_int16 32766%s-32767 = %d, wanted -3\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(-32767); got != 3 { fmt.Printf("sub_int16 -32767%s32766 = %d, wanted 3\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(-1); got != 32767 { fmt.Printf("sub_int16 32766%s-1 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(-1); got != -32767 { fmt.Printf("sub_int16 -1%s32766 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(0); got != 32766 { fmt.Printf("sub_int16 32766%s0 = %d, wanted 32766\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(0); got != -32766 { fmt.Printf("sub_int16 0%s32766 = %d, wanted -32766\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(1); got != 32765 { fmt.Printf("sub_int16 32766%s1 = %d, wanted 32765\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(1); got != -32765 { fmt.Printf("sub_int16 1%s32766 = %d, wanted -32765\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(32766); got != 0 { fmt.Printf("sub_int16 32766%s32766 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(32766); got != 0 { fmt.Printf("sub_int16 32766%s32766 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(32767); got != -1 { fmt.Printf("sub_int16 32766%s32767 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(32767); got != 1 { fmt.Printf("sub_int16 32767%s32766 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(-32768); got != -1 { fmt.Printf("sub_int16 32767%s-32768 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(-32768); got != 1 { fmt.Printf("sub_int16 -32768%s32767 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(-32767); got != -2 { fmt.Printf("sub_int16 32767%s-32767 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(-32767); got != 2 { fmt.Printf("sub_int16 -32767%s32767 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(-1); got != -32768 { fmt.Printf("sub_int16 32767%s-1 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(-1); got != -32768 { fmt.Printf("sub_int16 -1%s32767 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(0); got != 32767 { fmt.Printf("sub_int16 32767%s0 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(0); got != -32767 { fmt.Printf("sub_int16 0%s32767 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(1); got != 32766 { fmt.Printf("sub_int16 32767%s1 = %d, wanted 32766\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(1); got != -32766 { fmt.Printf("sub_int16 1%s32767 = %d, wanted -32766\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(32766); got != 1 { fmt.Printf("sub_int16 32767%s32766 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(32766); got != -1 { fmt.Printf("sub_int16 32766%s32767 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(32767); got != 0 { fmt.Printf("sub_int16 32767%s32767 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(32767); got != 0 { fmt.Printf("sub_int16 32767%s32767 = %d, wanted 0\n", `-`, got) failed = true } if got := div_Neg32768_int16_ssa(-32768); got != 1 { fmt.Printf("div_int16 -32768%s-32768 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(-32768); got != 1 { fmt.Printf("div_int16 -32768%s-32768 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg32768_int16_ssa(-32767); got != 1 { fmt.Printf("div_int16 -32768%s-32767 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(-32767); got != 0 { fmt.Printf("div_int16 -32767%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32768_int16_ssa(-1); got != -32768 { fmt.Printf("div_int16 -32768%s-1 = %d, wanted -32768\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(-1); got != 0 { fmt.Printf("div_int16 -1%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(0); got != 0 { fmt.Printf("div_int16 0%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32768_int16_ssa(1); got != -32768 { fmt.Printf("div_int16 -32768%s1 = %d, wanted -32768\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(1); got != 0 { fmt.Printf("div_int16 1%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32768_int16_ssa(32766); got != -1 { fmt.Printf("div_int16 -32768%s32766 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(32766); got != 0 { fmt.Printf("div_int16 32766%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32768_int16_ssa(32767); got != -1 { fmt.Printf("div_int16 -32768%s32767 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(32767); got != 0 { fmt.Printf("div_int16 32767%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32767_int16_ssa(-32768); got != 0 { fmt.Printf("div_int16 -32767%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(-32768); got != 1 { fmt.Printf("div_int16 -32768%s-32767 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg32767_int16_ssa(-32767); got != 1 { fmt.Printf("div_int16 -32767%s-32767 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(-32767); got != 1 { fmt.Printf("div_int16 -32767%s-32767 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg32767_int16_ssa(-1); got != 32767 { fmt.Printf("div_int16 -32767%s-1 = %d, wanted 32767\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(-1); got != 0 { fmt.Printf("div_int16 -1%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(0); got != 0 { fmt.Printf("div_int16 0%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32767_int16_ssa(1); got != -32767 { fmt.Printf("div_int16 -32767%s1 = %d, wanted -32767\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(1); got != 0 { fmt.Printf("div_int16 1%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32767_int16_ssa(32766); got != -1 { fmt.Printf("div_int16 -32767%s32766 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(32766); got != 0 { fmt.Printf("div_int16 32766%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32767_int16_ssa(32767); got != -1 { fmt.Printf("div_int16 -32767%s32767 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(32767); got != -1 { fmt.Printf("div_int16 32767%s-32767 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int16_ssa(-32768); got != 0 { fmt.Printf("div_int16 -1%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(-32768); got != -32768 { fmt.Printf("div_int16 -32768%s-1 = %d, wanted -32768\n", `/`, got) failed = true } if got := div_Neg1_int16_ssa(-32767); got != 0 { fmt.Printf("div_int16 -1%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(-32767); got != 32767 { fmt.Printf("div_int16 -32767%s-1 = %d, wanted 32767\n", `/`, got) failed = true } if got := div_Neg1_int16_ssa(-1); got != 1 { fmt.Printf("div_int16 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(-1); got != 1 { fmt.Printf("div_int16 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(0); got != 0 { fmt.Printf("div_int16 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg1_int16_ssa(1); got != -1 { fmt.Printf("div_int16 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(1); got != -1 { fmt.Printf("div_int16 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int16_ssa(32766); got != 0 { fmt.Printf("div_int16 -1%s32766 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(32766); got != -32766 { fmt.Printf("div_int16 32766%s-1 = %d, wanted -32766\n", `/`, got) failed = true } if got := div_Neg1_int16_ssa(32767); got != 0 { fmt.Printf("div_int16 -1%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(32767); got != -32767 { fmt.Printf("div_int16 32767%s-1 = %d, wanted -32767\n", `/`, got) failed = true } if got := div_0_int16_ssa(-32768); got != 0 { fmt.Printf("div_int16 0%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int16_ssa(-32767); got != 0 { fmt.Printf("div_int16 0%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int16_ssa(-1); got != 0 { fmt.Printf("div_int16 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int16_ssa(1); got != 0 { fmt.Printf("div_int16 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int16_ssa(32766); got != 0 { fmt.Printf("div_int16 0%s32766 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int16_ssa(32767); got != 0 { fmt.Printf("div_int16 0%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int16_ssa(-32768); got != 0 { fmt.Printf("div_int16 1%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_1_ssa(-32768); got != -32768 { fmt.Printf("div_int16 -32768%s1 = %d, wanted -32768\n", `/`, got) failed = true } if got := div_1_int16_ssa(-32767); got != 0 { fmt.Printf("div_int16 1%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_1_ssa(-32767); got != -32767 { fmt.Printf("div_int16 -32767%s1 = %d, wanted -32767\n", `/`, got) failed = true } if got := div_1_int16_ssa(-1); got != -1 { fmt.Printf("div_int16 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_1_ssa(-1); got != -1 { fmt.Printf("div_int16 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_1_ssa(0); got != 0 { fmt.Printf("div_int16 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int16_ssa(1); got != 1 { fmt.Printf("div_int16 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_1_ssa(1); got != 1 { fmt.Printf("div_int16 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_int16_ssa(32766); got != 0 { fmt.Printf("div_int16 1%s32766 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_1_ssa(32766); got != 32766 { fmt.Printf("div_int16 32766%s1 = %d, wanted 32766\n", `/`, got) failed = true } if got := div_1_int16_ssa(32767); got != 0 { fmt.Printf("div_int16 1%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_1_ssa(32767); got != 32767 { fmt.Printf("div_int16 32767%s1 = %d, wanted 32767\n", `/`, got) failed = true } if got := div_32766_int16_ssa(-32768); got != 0 { fmt.Printf("div_int16 32766%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_32766_ssa(-32768); got != -1 { fmt.Printf("div_int16 -32768%s32766 = %d, wanted -1\n", `/`, got) failed = true } if got := div_32766_int16_ssa(-32767); got != 0 { fmt.Printf("div_int16 32766%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_32766_ssa(-32767); got != -1 { fmt.Printf("div_int16 -32767%s32766 = %d, wanted -1\n", `/`, got) failed = true } if got := div_32766_int16_ssa(-1); got != -32766 { fmt.Printf("div_int16 32766%s-1 = %d, wanted -32766\n", `/`, got) failed = true } if got := div_int16_32766_ssa(-1); got != 0 { fmt.Printf("div_int16 -1%s32766 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_32766_ssa(0); got != 0 { fmt.Printf("div_int16 0%s32766 = %d, wanted 0\n", `/`, got) failed = true } if got := div_32766_int16_ssa(1); got != 32766 { fmt.Printf("div_int16 32766%s1 = %d, wanted 32766\n", `/`, got) failed = true } if got := div_int16_32766_ssa(1); got != 0 { fmt.Printf("div_int16 1%s32766 = %d, wanted 0\n", `/`, got) failed = true } if got := div_32766_int16_ssa(32766); got != 1 { fmt.Printf("div_int16 32766%s32766 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_32766_ssa(32766); got != 1 { fmt.Printf("div_int16 32766%s32766 = %d, wanted 1\n", `/`, got) failed = true } if got := div_32766_int16_ssa(32767); got != 0 { fmt.Printf("div_int16 32766%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_32766_ssa(32767); got != 1 { fmt.Printf("div_int16 32767%s32766 = %d, wanted 1\n", `/`, got) failed = true } if got := div_32767_int16_ssa(-32768); got != 0 { fmt.Printf("div_int16 32767%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_32767_ssa(-32768); got != -1 { fmt.Printf("div_int16 -32768%s32767 = %d, wanted -1\n", `/`, got) failed = true } if got := div_32767_int16_ssa(-32767); got != -1 { fmt.Printf("div_int16 32767%s-32767 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_32767_ssa(-32767); got != -1 { fmt.Printf("div_int16 -32767%s32767 = %d, wanted -1\n", `/`, got) failed = true } if got := div_32767_int16_ssa(-1); got != -32767 { fmt.Printf("div_int16 32767%s-1 = %d, wanted -32767\n", `/`, got) failed = true } if got := div_int16_32767_ssa(-1); got != 0 { fmt.Printf("div_int16 -1%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_32767_ssa(0); got != 0 { fmt.Printf("div_int16 0%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_32767_int16_ssa(1); got != 32767 { fmt.Printf("div_int16 32767%s1 = %d, wanted 32767\n", `/`, got) failed = true } if got := div_int16_32767_ssa(1); got != 0 { fmt.Printf("div_int16 1%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_32767_int16_ssa(32766); got != 1 { fmt.Printf("div_int16 32767%s32766 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_32767_ssa(32766); got != 0 { fmt.Printf("div_int16 32766%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_32767_int16_ssa(32767); got != 1 { fmt.Printf("div_int16 32767%s32767 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_32767_ssa(32767); got != 1 { fmt.Printf("div_int16 32767%s32767 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_Neg32768_int16_ssa(-32768); got != 0 { fmt.Printf("mul_int16 -32768%s-32768 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(-32768); got != 0 { fmt.Printf("mul_int16 -32768%s-32768 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg32768_int16_ssa(-32767); got != -32768 { fmt.Printf("mul_int16 -32768%s-32767 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(-32767); got != -32768 { fmt.Printf("mul_int16 -32767%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_Neg32768_int16_ssa(-1); got != -32768 { fmt.Printf("mul_int16 -32768%s-1 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(-1); got != -32768 { fmt.Printf("mul_int16 -1%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_Neg32768_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 -32768%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s-32768 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg32768_int16_ssa(1); got != -32768 { fmt.Printf("mul_int16 -32768%s1 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(1); got != -32768 { fmt.Printf("mul_int16 1%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_Neg32768_int16_ssa(32766); got != 0 { fmt.Printf("mul_int16 -32768%s32766 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(32766); got != 0 { fmt.Printf("mul_int16 32766%s-32768 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg32768_int16_ssa(32767); got != -32768 { fmt.Printf("mul_int16 -32768%s32767 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(32767); got != -32768 { fmt.Printf("mul_int16 32767%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 -32767%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 -32768%s-32767 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(-32767); got != 1 { fmt.Printf("mul_int16 -32767%s-32767 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(-32767); got != 1 { fmt.Printf("mul_int16 -32767%s-32767 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(-1); got != 32767 { fmt.Printf("mul_int16 -32767%s-1 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(-1); got != 32767 { fmt.Printf("mul_int16 -1%s-32767 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 -32767%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s-32767 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(1); got != -32767 { fmt.Printf("mul_int16 -32767%s1 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(1); got != -32767 { fmt.Printf("mul_int16 1%s-32767 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(32766); got != 32766 { fmt.Printf("mul_int16 -32767%s32766 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(32766); got != 32766 { fmt.Printf("mul_int16 32766%s-32767 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(32767); got != -1 { fmt.Printf("mul_int16 -32767%s32767 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(32767); got != -1 { fmt.Printf("mul_int16 32767%s-32767 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 -1%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 -32768%s-1 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(-32767); got != 32767 { fmt.Printf("mul_int16 -1%s-32767 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(-32767); got != 32767 { fmt.Printf("mul_int16 -32767%s-1 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(-1); got != 1 { fmt.Printf("mul_int16 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(-1); got != 1 { fmt.Printf("mul_int16 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(1); got != -1 { fmt.Printf("mul_int16 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(1); got != -1 { fmt.Printf("mul_int16 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(32766); got != -32766 { fmt.Printf("mul_int16 -1%s32766 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(32766); got != -32766 { fmt.Printf("mul_int16 32766%s-1 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(32767); got != -32767 { fmt.Printf("mul_int16 -1%s32767 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(32767); got != -32767 { fmt.Printf("mul_int16 32767%s-1 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_0_int16_ssa(-32768); got != 0 { fmt.Printf("mul_int16 0%s-32768 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(-32768); got != 0 { fmt.Printf("mul_int16 -32768%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int16_ssa(-32767); got != 0 { fmt.Printf("mul_int16 0%s-32767 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(-32767); got != 0 { fmt.Printf("mul_int16 -32767%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int16_ssa(-1); got != 0 { fmt.Printf("mul_int16 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(-1); got != 0 { fmt.Printf("mul_int16 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int16_ssa(1); got != 0 { fmt.Printf("mul_int16 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(1); got != 0 { fmt.Printf("mul_int16 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int16_ssa(32766); got != 0 { fmt.Printf("mul_int16 0%s32766 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(32766); got != 0 { fmt.Printf("mul_int16 32766%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int16_ssa(32767); got != 0 { fmt.Printf("mul_int16 0%s32767 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(32767); got != 0 { fmt.Printf("mul_int16 32767%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int16_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 1%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_1_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 -32768%s1 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_1_int16_ssa(-32767); got != -32767 { fmt.Printf("mul_int16 1%s-32767 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_int16_1_ssa(-32767); got != -32767 { fmt.Printf("mul_int16 -32767%s1 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_1_int16_ssa(-1); got != -1 { fmt.Printf("mul_int16 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int16_1_ssa(-1); got != -1 { fmt.Printf("mul_int16 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_1_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_1_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int16_ssa(1); got != 1 { fmt.Printf("mul_int16 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int16_1_ssa(1); got != 1 { fmt.Printf("mul_int16 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_int16_ssa(32766); got != 32766 { fmt.Printf("mul_int16 1%s32766 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_int16_1_ssa(32766); got != 32766 { fmt.Printf("mul_int16 32766%s1 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_1_int16_ssa(32767); got != 32767 { fmt.Printf("mul_int16 1%s32767 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_int16_1_ssa(32767); got != 32767 { fmt.Printf("mul_int16 32767%s1 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(-32768); got != 0 { fmt.Printf("mul_int16 32766%s-32768 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(-32768); got != 0 { fmt.Printf("mul_int16 -32768%s32766 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(-32767); got != 32766 { fmt.Printf("mul_int16 32766%s-32767 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(-32767); got != 32766 { fmt.Printf("mul_int16 -32767%s32766 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(-1); got != -32766 { fmt.Printf("mul_int16 32766%s-1 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(-1); got != -32766 { fmt.Printf("mul_int16 -1%s32766 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 32766%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s32766 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(1); got != 32766 { fmt.Printf("mul_int16 32766%s1 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(1); got != 32766 { fmt.Printf("mul_int16 1%s32766 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(32766); got != 4 { fmt.Printf("mul_int16 32766%s32766 = %d, wanted 4\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(32766); got != 4 { fmt.Printf("mul_int16 32766%s32766 = %d, wanted 4\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(32767); got != -32766 { fmt.Printf("mul_int16 32766%s32767 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(32767); got != -32766 { fmt.Printf("mul_int16 32767%s32766 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 32767%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 -32768%s32767 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(-32767); got != -1 { fmt.Printf("mul_int16 32767%s-32767 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(-32767); got != -1 { fmt.Printf("mul_int16 -32767%s32767 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(-1); got != -32767 { fmt.Printf("mul_int16 32767%s-1 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(-1); got != -32767 { fmt.Printf("mul_int16 -1%s32767 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 32767%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s32767 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(1); got != 32767 { fmt.Printf("mul_int16 32767%s1 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(1); got != 32767 { fmt.Printf("mul_int16 1%s32767 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(32766); got != -32766 { fmt.Printf("mul_int16 32767%s32766 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(32766); got != -32766 { fmt.Printf("mul_int16 32766%s32767 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(32767); got != 1 { fmt.Printf("mul_int16 32767%s32767 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(32767); got != 1 { fmt.Printf("mul_int16 32767%s32767 = %d, wanted 1\n", `*`, got) failed = true } if got := mod_Neg32768_int16_ssa(-32768); got != 0 { fmt.Printf("mod_int16 -32768%s-32768 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(-32768); got != 0 { fmt.Printf("mod_int16 -32768%s-32768 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg32768_int16_ssa(-32767); got != -1 { fmt.Printf("mod_int16 -32768%s-32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(-32767); got != -32767 { fmt.Printf("mod_int16 -32767%s-32768 = %d, wanted -32767\n", `%`, got) failed = true } if got := mod_Neg32768_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 -32768%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(-1); got != -1 { fmt.Printf("mod_int16 -1%s-32768 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(0); got != 0 { fmt.Printf("mod_int16 0%s-32768 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg32768_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 -32768%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(1); got != 1 { fmt.Printf("mod_int16 1%s-32768 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg32768_int16_ssa(32766); got != -2 { fmt.Printf("mod_int16 -32768%s32766 = %d, wanted -2\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(32766); got != 32766 { fmt.Printf("mod_int16 32766%s-32768 = %d, wanted 32766\n", `%`, got) failed = true } if got := mod_Neg32768_int16_ssa(32767); got != -1 { fmt.Printf("mod_int16 -32768%s32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(32767); got != 32767 { fmt.Printf("mod_int16 32767%s-32768 = %d, wanted 32767\n", `%`, got) failed = true } if got := mod_Neg32767_int16_ssa(-32768); got != -32767 { fmt.Printf("mod_int16 -32767%s-32768 = %d, wanted -32767\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(-32768); got != -1 { fmt.Printf("mod_int16 -32768%s-32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_Neg32767_int16_ssa(-32767); got != 0 { fmt.Printf("mod_int16 -32767%s-32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(-32767); got != 0 { fmt.Printf("mod_int16 -32767%s-32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg32767_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 -32767%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(-1); got != -1 { fmt.Printf("mod_int16 -1%s-32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(0); got != 0 { fmt.Printf("mod_int16 0%s-32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg32767_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 -32767%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(1); got != 1 { fmt.Printf("mod_int16 1%s-32767 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg32767_int16_ssa(32766); got != -1 { fmt.Printf("mod_int16 -32767%s32766 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(32766); got != 32766 { fmt.Printf("mod_int16 32766%s-32767 = %d, wanted 32766\n", `%`, got) failed = true } if got := mod_Neg32767_int16_ssa(32767); got != 0 { fmt.Printf("mod_int16 -32767%s32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(32767); got != 0 { fmt.Printf("mod_int16 32767%s-32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int16_ssa(-32768); got != -1 { fmt.Printf("mod_int16 -1%s-32768 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(-32768); got != 0 { fmt.Printf("mod_int16 -32768%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int16_ssa(-32767); got != -1 { fmt.Printf("mod_int16 -1%s-32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(-32767); got != 0 { fmt.Printf("mod_int16 -32767%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(-1); got != 0 { fmt.Printf("mod_int16 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(0); got != 0 { fmt.Printf("mod_int16 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(1); got != 0 { fmt.Printf("mod_int16 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int16_ssa(32766); got != -1 { fmt.Printf("mod_int16 -1%s32766 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(32766); got != 0 { fmt.Printf("mod_int16 32766%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int16_ssa(32767); got != -1 { fmt.Printf("mod_int16 -1%s32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(32767); got != 0 { fmt.Printf("mod_int16 32767%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int16_ssa(-32768); got != 0 { fmt.Printf("mod_int16 0%s-32768 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int16_ssa(-32767); got != 0 { fmt.Printf("mod_int16 0%s-32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int16_ssa(32766); got != 0 { fmt.Printf("mod_int16 0%s32766 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int16_ssa(32767); got != 0 { fmt.Printf("mod_int16 0%s32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int16_ssa(-32768); got != 1 { fmt.Printf("mod_int16 1%s-32768 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int16_1_ssa(-32768); got != 0 { fmt.Printf("mod_int16 -32768%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int16_ssa(-32767); got != 1 { fmt.Printf("mod_int16 1%s-32767 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int16_1_ssa(-32767); got != 0 { fmt.Printf("mod_int16 -32767%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_1_ssa(-1); got != 0 { fmt.Printf("mod_int16 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_1_ssa(0); got != 0 { fmt.Printf("mod_int16 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_1_ssa(1); got != 0 { fmt.Printf("mod_int16 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int16_ssa(32766); got != 1 { fmt.Printf("mod_int16 1%s32766 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int16_1_ssa(32766); got != 0 { fmt.Printf("mod_int16 32766%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int16_ssa(32767); got != 1 { fmt.Printf("mod_int16 1%s32767 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int16_1_ssa(32767); got != 0 { fmt.Printf("mod_int16 32767%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_32766_int16_ssa(-32768); got != 32766 { fmt.Printf("mod_int16 32766%s-32768 = %d, wanted 32766\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(-32768); got != -2 { fmt.Printf("mod_int16 -32768%s32766 = %d, wanted -2\n", `%`, got) failed = true } if got := mod_32766_int16_ssa(-32767); got != 32766 { fmt.Printf("mod_int16 32766%s-32767 = %d, wanted 32766\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(-32767); got != -1 { fmt.Printf("mod_int16 -32767%s32766 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_32766_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 32766%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(-1); got != -1 { fmt.Printf("mod_int16 -1%s32766 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(0); got != 0 { fmt.Printf("mod_int16 0%s32766 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_32766_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 32766%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(1); got != 1 { fmt.Printf("mod_int16 1%s32766 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_32766_int16_ssa(32766); got != 0 { fmt.Printf("mod_int16 32766%s32766 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(32766); got != 0 { fmt.Printf("mod_int16 32766%s32766 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_32766_int16_ssa(32767); got != 32766 { fmt.Printf("mod_int16 32766%s32767 = %d, wanted 32766\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(32767); got != 1 { fmt.Printf("mod_int16 32767%s32766 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_32767_int16_ssa(-32768); got != 32767 { fmt.Printf("mod_int16 32767%s-32768 = %d, wanted 32767\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(-32768); got != -1 { fmt.Printf("mod_int16 -32768%s32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_32767_int16_ssa(-32767); got != 0 { fmt.Printf("mod_int16 32767%s-32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(-32767); got != 0 { fmt.Printf("mod_int16 -32767%s32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_32767_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 32767%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(-1); got != -1 { fmt.Printf("mod_int16 -1%s32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(0); got != 0 { fmt.Printf("mod_int16 0%s32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_32767_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 32767%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(1); got != 1 { fmt.Printf("mod_int16 1%s32767 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_32767_int16_ssa(32766); got != 1 { fmt.Printf("mod_int16 32767%s32766 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(32766); got != 32766 { fmt.Printf("mod_int16 32766%s32767 = %d, wanted 32766\n", `%`, got) failed = true } if got := mod_32767_int16_ssa(32767); got != 0 { fmt.Printf("mod_int16 32767%s32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(32767); got != 0 { fmt.Printf("mod_int16 32767%s32767 = %d, wanted 0\n", `%`, got) failed = true } if got := and_Neg32768_int16_ssa(-32768); got != -32768 { fmt.Printf("and_int16 -32768%s-32768 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(-32768); got != -32768 { fmt.Printf("and_int16 -32768%s-32768 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_Neg32768_int16_ssa(-32767); got != -32768 { fmt.Printf("and_int16 -32768%s-32767 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(-32767); got != -32768 { fmt.Printf("and_int16 -32767%s-32768 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_Neg32768_int16_ssa(-1); got != -32768 { fmt.Printf("and_int16 -32768%s-1 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(-1); got != -32768 { fmt.Printf("and_int16 -1%s-32768 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_Neg32768_int16_ssa(0); got != 0 { fmt.Printf("and_int16 -32768%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(0); got != 0 { fmt.Printf("and_int16 0%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg32768_int16_ssa(1); got != 0 { fmt.Printf("and_int16 -32768%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(1); got != 0 { fmt.Printf("and_int16 1%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg32768_int16_ssa(32766); got != 0 { fmt.Printf("and_int16 -32768%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(32766); got != 0 { fmt.Printf("and_int16 32766%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg32768_int16_ssa(32767); got != 0 { fmt.Printf("and_int16 -32768%s32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(32767); got != 0 { fmt.Printf("and_int16 32767%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(-32768); got != -32768 { fmt.Printf("and_int16 -32767%s-32768 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(-32768); got != -32768 { fmt.Printf("and_int16 -32768%s-32767 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(-32767); got != -32767 { fmt.Printf("and_int16 -32767%s-32767 = %d, wanted -32767\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(-32767); got != -32767 { fmt.Printf("and_int16 -32767%s-32767 = %d, wanted -32767\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(-1); got != -32767 { fmt.Printf("and_int16 -32767%s-1 = %d, wanted -32767\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(-1); got != -32767 { fmt.Printf("and_int16 -1%s-32767 = %d, wanted -32767\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(0); got != 0 { fmt.Printf("and_int16 -32767%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(0); got != 0 { fmt.Printf("and_int16 0%s-32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(1); got != 1 { fmt.Printf("and_int16 -32767%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(1); got != 1 { fmt.Printf("and_int16 1%s-32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(32766); got != 0 { fmt.Printf("and_int16 -32767%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(32766); got != 0 { fmt.Printf("and_int16 32766%s-32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(32767); got != 1 { fmt.Printf("and_int16 -32767%s32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(32767); got != 1 { fmt.Printf("and_int16 32767%s-32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(-32768); got != -32768 { fmt.Printf("and_int16 -1%s-32768 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(-32768); got != -32768 { fmt.Printf("and_int16 -32768%s-1 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(-32767); got != -32767 { fmt.Printf("and_int16 -1%s-32767 = %d, wanted -32767\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(-32767); got != -32767 { fmt.Printf("and_int16 -32767%s-1 = %d, wanted -32767\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(-1); got != -1 { fmt.Printf("and_int16 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(-1); got != -1 { fmt.Printf("and_int16 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(0); got != 0 { fmt.Printf("and_int16 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(0); got != 0 { fmt.Printf("and_int16 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(1); got != 1 { fmt.Printf("and_int16 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(1); got != 1 { fmt.Printf("and_int16 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(32766); got != 32766 { fmt.Printf("and_int16 -1%s32766 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(32766); got != 32766 { fmt.Printf("and_int16 32766%s-1 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(32767); got != 32767 { fmt.Printf("and_int16 -1%s32767 = %d, wanted 32767\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(32767); got != 32767 { fmt.Printf("and_int16 32767%s-1 = %d, wanted 32767\n", `&`, got) failed = true } if got := and_0_int16_ssa(-32768); got != 0 { fmt.Printf("and_int16 0%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(-32768); got != 0 { fmt.Printf("and_int16 -32768%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int16_ssa(-32767); got != 0 { fmt.Printf("and_int16 0%s-32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(-32767); got != 0 { fmt.Printf("and_int16 -32767%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int16_ssa(-1); got != 0 { fmt.Printf("and_int16 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(-1); got != 0 { fmt.Printf("and_int16 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int16_ssa(0); got != 0 { fmt.Printf("and_int16 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(0); got != 0 { fmt.Printf("and_int16 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int16_ssa(1); got != 0 { fmt.Printf("and_int16 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(1); got != 0 { fmt.Printf("and_int16 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int16_ssa(32766); got != 0 { fmt.Printf("and_int16 0%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(32766); got != 0 { fmt.Printf("and_int16 32766%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int16_ssa(32767); got != 0 { fmt.Printf("and_int16 0%s32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(32767); got != 0 { fmt.Printf("and_int16 32767%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int16_ssa(-32768); got != 0 { fmt.Printf("and_int16 1%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_1_ssa(-32768); got != 0 { fmt.Printf("and_int16 -32768%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int16_ssa(-32767); got != 1 { fmt.Printf("and_int16 1%s-32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_1_ssa(-32767); got != 1 { fmt.Printf("and_int16 -32767%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int16_ssa(-1); got != 1 { fmt.Printf("and_int16 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_1_ssa(-1); got != 1 { fmt.Printf("and_int16 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int16_ssa(0); got != 0 { fmt.Printf("and_int16 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_1_ssa(0); got != 0 { fmt.Printf("and_int16 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int16_ssa(1); got != 1 { fmt.Printf("and_int16 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_1_ssa(1); got != 1 { fmt.Printf("and_int16 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int16_ssa(32766); got != 0 { fmt.Printf("and_int16 1%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_1_ssa(32766); got != 0 { fmt.Printf("and_int16 32766%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int16_ssa(32767); got != 1 { fmt.Printf("and_int16 1%s32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_1_ssa(32767); got != 1 { fmt.Printf("and_int16 32767%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_32766_int16_ssa(-32768); got != 0 { fmt.Printf("and_int16 32766%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_32766_ssa(-32768); got != 0 { fmt.Printf("and_int16 -32768%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_32766_int16_ssa(-32767); got != 0 { fmt.Printf("and_int16 32766%s-32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_32766_ssa(-32767); got != 0 { fmt.Printf("and_int16 -32767%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_32766_int16_ssa(-1); got != 32766 { fmt.Printf("and_int16 32766%s-1 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_int16_32766_ssa(-1); got != 32766 { fmt.Printf("and_int16 -1%s32766 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_32766_int16_ssa(0); got != 0 { fmt.Printf("and_int16 32766%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_32766_ssa(0); got != 0 { fmt.Printf("and_int16 0%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_32766_int16_ssa(1); got != 0 { fmt.Printf("and_int16 32766%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_32766_ssa(1); got != 0 { fmt.Printf("and_int16 1%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_32766_int16_ssa(32766); got != 32766 { fmt.Printf("and_int16 32766%s32766 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_int16_32766_ssa(32766); got != 32766 { fmt.Printf("and_int16 32766%s32766 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_32766_int16_ssa(32767); got != 32766 { fmt.Printf("and_int16 32766%s32767 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_int16_32766_ssa(32767); got != 32766 { fmt.Printf("and_int16 32767%s32766 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_32767_int16_ssa(-32768); got != 0 { fmt.Printf("and_int16 32767%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_32767_ssa(-32768); got != 0 { fmt.Printf("and_int16 -32768%s32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_32767_int16_ssa(-32767); got != 1 { fmt.Printf("and_int16 32767%s-32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_32767_ssa(-32767); got != 1 { fmt.Printf("and_int16 -32767%s32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_32767_int16_ssa(-1); got != 32767 { fmt.Printf("and_int16 32767%s-1 = %d, wanted 32767\n", `&`, got) failed = true } if got := and_int16_32767_ssa(-1); got != 32767 { fmt.Printf("and_int16 -1%s32767 = %d, wanted 32767\n", `&`, got) failed = true } if got := and_32767_int16_ssa(0); got != 0 { fmt.Printf("and_int16 32767%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_32767_ssa(0); got != 0 { fmt.Printf("and_int16 0%s32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_32767_int16_ssa(1); got != 1 { fmt.Printf("and_int16 32767%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_32767_ssa(1); got != 1 { fmt.Printf("and_int16 1%s32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_32767_int16_ssa(32766); got != 32766 { fmt.Printf("and_int16 32767%s32766 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_int16_32767_ssa(32766); got != 32766 { fmt.Printf("and_int16 32766%s32767 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_32767_int16_ssa(32767); got != 32767 { fmt.Printf("and_int16 32767%s32767 = %d, wanted 32767\n", `&`, got) failed = true } if got := and_int16_32767_ssa(32767); got != 32767 { fmt.Printf("and_int16 32767%s32767 = %d, wanted 32767\n", `&`, got) failed = true } if got := or_Neg32768_int16_ssa(-32768); got != -32768 { fmt.Printf("or_int16 -32768%s-32768 = %d, wanted -32768\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(-32768); got != -32768 { fmt.Printf("or_int16 -32768%s-32768 = %d, wanted -32768\n", `|`, got) failed = true } if got := or_Neg32768_int16_ssa(-32767); got != -32767 { fmt.Printf("or_int16 -32768%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(-32767); got != -32767 { fmt.Printf("or_int16 -32767%s-32768 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_Neg32768_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 -32768%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s-32768 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg32768_int16_ssa(0); got != -32768 { fmt.Printf("or_int16 -32768%s0 = %d, wanted -32768\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(0); got != -32768 { fmt.Printf("or_int16 0%s-32768 = %d, wanted -32768\n", `|`, got) failed = true } if got := or_Neg32768_int16_ssa(1); got != -32767 { fmt.Printf("or_int16 -32768%s1 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(1); got != -32767 { fmt.Printf("or_int16 1%s-32768 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_Neg32768_int16_ssa(32766); got != -2 { fmt.Printf("or_int16 -32768%s32766 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(32766); got != -2 { fmt.Printf("or_int16 32766%s-32768 = %d, wanted -2\n", `|`, got) failed = true } if got := or_Neg32768_int16_ssa(32767); got != -1 { fmt.Printf("or_int16 -32768%s32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(32767); got != -1 { fmt.Printf("or_int16 32767%s-32768 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(-32768); got != -32767 { fmt.Printf("or_int16 -32767%s-32768 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(-32768); got != -32767 { fmt.Printf("or_int16 -32768%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(-32767); got != -32767 { fmt.Printf("or_int16 -32767%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(-32767); got != -32767 { fmt.Printf("or_int16 -32767%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 -32767%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s-32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(0); got != -32767 { fmt.Printf("or_int16 -32767%s0 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(0); got != -32767 { fmt.Printf("or_int16 0%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(1); got != -32767 { fmt.Printf("or_int16 -32767%s1 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(1); got != -32767 { fmt.Printf("or_int16 1%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(32766); got != -1 { fmt.Printf("or_int16 -32767%s32766 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(32766); got != -1 { fmt.Printf("or_int16 32766%s-32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(32767); got != -1 { fmt.Printf("or_int16 -32767%s32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(32767); got != -1 { fmt.Printf("or_int16 32767%s-32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(-32768); got != -1 { fmt.Printf("or_int16 -1%s-32768 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(-32768); got != -1 { fmt.Printf("or_int16 -32768%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(-32767); got != -1 { fmt.Printf("or_int16 -1%s-32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(-32767); got != -1 { fmt.Printf("or_int16 -32767%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(0); got != -1 { fmt.Printf("or_int16 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(0); got != -1 { fmt.Printf("or_int16 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(1); got != -1 { fmt.Printf("or_int16 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(1); got != -1 { fmt.Printf("or_int16 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(32766); got != -1 { fmt.Printf("or_int16 -1%s32766 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(32766); got != -1 { fmt.Printf("or_int16 32766%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(32767); got != -1 { fmt.Printf("or_int16 -1%s32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(32767); got != -1 { fmt.Printf("or_int16 32767%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int16_ssa(-32768); got != -32768 { fmt.Printf("or_int16 0%s-32768 = %d, wanted -32768\n", `|`, got) failed = true } if got := or_int16_0_ssa(-32768); got != -32768 { fmt.Printf("or_int16 -32768%s0 = %d, wanted -32768\n", `|`, got) failed = true } if got := or_0_int16_ssa(-32767); got != -32767 { fmt.Printf("or_int16 0%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_0_ssa(-32767); got != -32767 { fmt.Printf("or_int16 -32767%s0 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_0_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_0_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int16_ssa(0); got != 0 { fmt.Printf("or_int16 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_int16_0_ssa(0); got != 0 { fmt.Printf("or_int16 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_int16_ssa(1); got != 1 { fmt.Printf("or_int16 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int16_0_ssa(1); got != 1 { fmt.Printf("or_int16 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_int16_ssa(32766); got != 32766 { fmt.Printf("or_int16 0%s32766 = %d, wanted 32766\n", `|`, got) failed = true } if got := or_int16_0_ssa(32766); got != 32766 { fmt.Printf("or_int16 32766%s0 = %d, wanted 32766\n", `|`, got) failed = true } if got := or_0_int16_ssa(32767); got != 32767 { fmt.Printf("or_int16 0%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_0_ssa(32767); got != 32767 { fmt.Printf("or_int16 32767%s0 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_1_int16_ssa(-32768); got != -32767 { fmt.Printf("or_int16 1%s-32768 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_1_ssa(-32768); got != -32767 { fmt.Printf("or_int16 -32768%s1 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_1_int16_ssa(-32767); got != -32767 { fmt.Printf("or_int16 1%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_1_ssa(-32767); got != -32767 { fmt.Printf("or_int16 -32767%s1 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_1_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_1_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_1_int16_ssa(0); got != 1 { fmt.Printf("or_int16 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int16_1_ssa(0); got != 1 { fmt.Printf("or_int16 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int16_ssa(1); got != 1 { fmt.Printf("or_int16 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int16_1_ssa(1); got != 1 { fmt.Printf("or_int16 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int16_ssa(32766); got != 32767 { fmt.Printf("or_int16 1%s32766 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_1_ssa(32766); got != 32767 { fmt.Printf("or_int16 32766%s1 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_1_int16_ssa(32767); got != 32767 { fmt.Printf("or_int16 1%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_1_ssa(32767); got != 32767 { fmt.Printf("or_int16 32767%s1 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_32766_int16_ssa(-32768); got != -2 { fmt.Printf("or_int16 32766%s-32768 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int16_32766_ssa(-32768); got != -2 { fmt.Printf("or_int16 -32768%s32766 = %d, wanted -2\n", `|`, got) failed = true } if got := or_32766_int16_ssa(-32767); got != -1 { fmt.Printf("or_int16 32766%s-32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_32766_ssa(-32767); got != -1 { fmt.Printf("or_int16 -32767%s32766 = %d, wanted -1\n", `|`, got) failed = true } if got := or_32766_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 32766%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_32766_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s32766 = %d, wanted -1\n", `|`, got) failed = true } if got := or_32766_int16_ssa(0); got != 32766 { fmt.Printf("or_int16 32766%s0 = %d, wanted 32766\n", `|`, got) failed = true } if got := or_int16_32766_ssa(0); got != 32766 { fmt.Printf("or_int16 0%s32766 = %d, wanted 32766\n", `|`, got) failed = true } if got := or_32766_int16_ssa(1); got != 32767 { fmt.Printf("or_int16 32766%s1 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_32766_ssa(1); got != 32767 { fmt.Printf("or_int16 1%s32766 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_32766_int16_ssa(32766); got != 32766 { fmt.Printf("or_int16 32766%s32766 = %d, wanted 32766\n", `|`, got) failed = true } if got := or_int16_32766_ssa(32766); got != 32766 { fmt.Printf("or_int16 32766%s32766 = %d, wanted 32766\n", `|`, got) failed = true } if got := or_32766_int16_ssa(32767); got != 32767 { fmt.Printf("or_int16 32766%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_32766_ssa(32767); got != 32767 { fmt.Printf("or_int16 32767%s32766 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_32767_int16_ssa(-32768); got != -1 { fmt.Printf("or_int16 32767%s-32768 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_32767_ssa(-32768); got != -1 { fmt.Printf("or_int16 -32768%s32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_32767_int16_ssa(-32767); got != -1 { fmt.Printf("or_int16 32767%s-32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_32767_ssa(-32767); got != -1 { fmt.Printf("or_int16 -32767%s32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_32767_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 32767%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_32767_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_32767_int16_ssa(0); got != 32767 { fmt.Printf("or_int16 32767%s0 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_32767_ssa(0); got != 32767 { fmt.Printf("or_int16 0%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_32767_int16_ssa(1); got != 32767 { fmt.Printf("or_int16 32767%s1 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_32767_ssa(1); got != 32767 { fmt.Printf("or_int16 1%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_32767_int16_ssa(32766); got != 32767 { fmt.Printf("or_int16 32767%s32766 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_32767_ssa(32766); got != 32767 { fmt.Printf("or_int16 32766%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_32767_int16_ssa(32767); got != 32767 { fmt.Printf("or_int16 32767%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_32767_ssa(32767); got != 32767 { fmt.Printf("or_int16 32767%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := xor_Neg32768_int16_ssa(-32768); got != 0 { fmt.Printf("xor_int16 -32768%s-32768 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(-32768); got != 0 { fmt.Printf("xor_int16 -32768%s-32768 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg32768_int16_ssa(-32767); got != 1 { fmt.Printf("xor_int16 -32768%s-32767 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(-32767); got != 1 { fmt.Printf("xor_int16 -32767%s-32768 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg32768_int16_ssa(-1); got != 32767 { fmt.Printf("xor_int16 -32768%s-1 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(-1); got != 32767 { fmt.Printf("xor_int16 -1%s-32768 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_Neg32768_int16_ssa(0); got != -32768 { fmt.Printf("xor_int16 -32768%s0 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(0); got != -32768 { fmt.Printf("xor_int16 0%s-32768 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_Neg32768_int16_ssa(1); got != -32767 { fmt.Printf("xor_int16 -32768%s1 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(1); got != -32767 { fmt.Printf("xor_int16 1%s-32768 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_Neg32768_int16_ssa(32766); got != -2 { fmt.Printf("xor_int16 -32768%s32766 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(32766); got != -2 { fmt.Printf("xor_int16 32766%s-32768 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg32768_int16_ssa(32767); got != -1 { fmt.Printf("xor_int16 -32768%s32767 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(32767); got != -1 { fmt.Printf("xor_int16 32767%s-32768 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(-32768); got != 1 { fmt.Printf("xor_int16 -32767%s-32768 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(-32768); got != 1 { fmt.Printf("xor_int16 -32768%s-32767 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(-32767); got != 0 { fmt.Printf("xor_int16 -32767%s-32767 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(-32767); got != 0 { fmt.Printf("xor_int16 -32767%s-32767 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(-1); got != 32766 { fmt.Printf("xor_int16 -32767%s-1 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(-1); got != 32766 { fmt.Printf("xor_int16 -1%s-32767 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(0); got != -32767 { fmt.Printf("xor_int16 -32767%s0 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(0); got != -32767 { fmt.Printf("xor_int16 0%s-32767 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(1); got != -32768 { fmt.Printf("xor_int16 -32767%s1 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(1); got != -32768 { fmt.Printf("xor_int16 1%s-32767 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(32766); got != -1 { fmt.Printf("xor_int16 -32767%s32766 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(32766); got != -1 { fmt.Printf("xor_int16 32766%s-32767 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(32767); got != -2 { fmt.Printf("xor_int16 -32767%s32767 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(32767); got != -2 { fmt.Printf("xor_int16 32767%s-32767 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(-32768); got != 32767 { fmt.Printf("xor_int16 -1%s-32768 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(-32768); got != 32767 { fmt.Printf("xor_int16 -32768%s-1 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(-32767); got != 32766 { fmt.Printf("xor_int16 -1%s-32767 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(-32767); got != 32766 { fmt.Printf("xor_int16 -32767%s-1 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(-1); got != 0 { fmt.Printf("xor_int16 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(-1); got != 0 { fmt.Printf("xor_int16 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(0); got != -1 { fmt.Printf("xor_int16 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(0); got != -1 { fmt.Printf("xor_int16 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(1); got != -2 { fmt.Printf("xor_int16 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(1); got != -2 { fmt.Printf("xor_int16 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(32766); got != -32767 { fmt.Printf("xor_int16 -1%s32766 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(32766); got != -32767 { fmt.Printf("xor_int16 32766%s-1 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(32767); got != -32768 { fmt.Printf("xor_int16 -1%s32767 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(32767); got != -32768 { fmt.Printf("xor_int16 32767%s-1 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_0_int16_ssa(-32768); got != -32768 { fmt.Printf("xor_int16 0%s-32768 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_int16_0_ssa(-32768); got != -32768 { fmt.Printf("xor_int16 -32768%s0 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_0_int16_ssa(-32767); got != -32767 { fmt.Printf("xor_int16 0%s-32767 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_int16_0_ssa(-32767); got != -32767 { fmt.Printf("xor_int16 -32767%s0 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_0_int16_ssa(-1); got != -1 { fmt.Printf("xor_int16 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int16_0_ssa(-1); got != -1 { fmt.Printf("xor_int16 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_0_int16_ssa(0); got != 0 { fmt.Printf("xor_int16 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_0_ssa(0); got != 0 { fmt.Printf("xor_int16 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_int16_ssa(1); got != 1 { fmt.Printf("xor_int16 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int16_0_ssa(1); got != 1 { fmt.Printf("xor_int16 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_int16_ssa(32766); got != 32766 { fmt.Printf("xor_int16 0%s32766 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_int16_0_ssa(32766); got != 32766 { fmt.Printf("xor_int16 32766%s0 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_0_int16_ssa(32767); got != 32767 { fmt.Printf("xor_int16 0%s32767 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_int16_0_ssa(32767); got != 32767 { fmt.Printf("xor_int16 32767%s0 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_1_int16_ssa(-32768); got != -32767 { fmt.Printf("xor_int16 1%s-32768 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_int16_1_ssa(-32768); got != -32767 { fmt.Printf("xor_int16 -32768%s1 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_1_int16_ssa(-32767); got != -32768 { fmt.Printf("xor_int16 1%s-32767 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_int16_1_ssa(-32767); got != -32768 { fmt.Printf("xor_int16 -32767%s1 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_1_int16_ssa(-1); got != -2 { fmt.Printf("xor_int16 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int16_1_ssa(-1); got != -2 { fmt.Printf("xor_int16 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_1_int16_ssa(0); got != 1 { fmt.Printf("xor_int16 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int16_1_ssa(0); got != 1 { fmt.Printf("xor_int16 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_int16_ssa(1); got != 0 { fmt.Printf("xor_int16 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_1_ssa(1); got != 0 { fmt.Printf("xor_int16 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_int16_ssa(32766); got != 32767 { fmt.Printf("xor_int16 1%s32766 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_int16_1_ssa(32766); got != 32767 { fmt.Printf("xor_int16 32766%s1 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_1_int16_ssa(32767); got != 32766 { fmt.Printf("xor_int16 1%s32767 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_int16_1_ssa(32767); got != 32766 { fmt.Printf("xor_int16 32767%s1 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(-32768); got != -2 { fmt.Printf("xor_int16 32766%s-32768 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(-32768); got != -2 { fmt.Printf("xor_int16 -32768%s32766 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(-32767); got != -1 { fmt.Printf("xor_int16 32766%s-32767 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(-32767); got != -1 { fmt.Printf("xor_int16 -32767%s32766 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(-1); got != -32767 { fmt.Printf("xor_int16 32766%s-1 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(-1); got != -32767 { fmt.Printf("xor_int16 -1%s32766 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(0); got != 32766 { fmt.Printf("xor_int16 32766%s0 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(0); got != 32766 { fmt.Printf("xor_int16 0%s32766 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(1); got != 32767 { fmt.Printf("xor_int16 32766%s1 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(1); got != 32767 { fmt.Printf("xor_int16 1%s32766 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(32766); got != 0 { fmt.Printf("xor_int16 32766%s32766 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(32766); got != 0 { fmt.Printf("xor_int16 32766%s32766 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(32767); got != 1 { fmt.Printf("xor_int16 32766%s32767 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(32767); got != 1 { fmt.Printf("xor_int16 32767%s32766 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(-32768); got != -1 { fmt.Printf("xor_int16 32767%s-32768 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(-32768); got != -1 { fmt.Printf("xor_int16 -32768%s32767 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(-32767); got != -2 { fmt.Printf("xor_int16 32767%s-32767 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(-32767); got != -2 { fmt.Printf("xor_int16 -32767%s32767 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(-1); got != -32768 { fmt.Printf("xor_int16 32767%s-1 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(-1); got != -32768 { fmt.Printf("xor_int16 -1%s32767 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(0); got != 32767 { fmt.Printf("xor_int16 32767%s0 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(0); got != 32767 { fmt.Printf("xor_int16 0%s32767 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(1); got != 32766 { fmt.Printf("xor_int16 32767%s1 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(1); got != 32766 { fmt.Printf("xor_int16 1%s32767 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(32766); got != 1 { fmt.Printf("xor_int16 32767%s32766 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(32766); got != 1 { fmt.Printf("xor_int16 32766%s32767 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(32767); got != 0 { fmt.Printf("xor_int16 32767%s32767 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(32767); got != 0 { fmt.Printf("xor_int16 32767%s32767 = %d, wanted 0\n", `^`, got) failed = true } if got := add_0_uint8_ssa(0); got != 0 { fmt.Printf("add_uint8 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint8_0_ssa(0); got != 0 { fmt.Printf("add_uint8 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_uint8_ssa(1); got != 1 { fmt.Printf("add_uint8 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint8_0_ssa(1); got != 1 { fmt.Printf("add_uint8 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_uint8_ssa(255); got != 255 { fmt.Printf("add_uint8 0%s255 = %d, wanted 255\n", `+`, got) failed = true } if got := add_uint8_0_ssa(255); got != 255 { fmt.Printf("add_uint8 255%s0 = %d, wanted 255\n", `+`, got) failed = true } if got := add_1_uint8_ssa(0); got != 1 { fmt.Printf("add_uint8 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint8_1_ssa(0); got != 1 { fmt.Printf("add_uint8 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_uint8_ssa(1); got != 2 { fmt.Printf("add_uint8 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_uint8_1_ssa(1); got != 2 { fmt.Printf("add_uint8 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_uint8_ssa(255); got != 0 { fmt.Printf("add_uint8 1%s255 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint8_1_ssa(255); got != 0 { fmt.Printf("add_uint8 255%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_255_uint8_ssa(0); got != 255 { fmt.Printf("add_uint8 255%s0 = %d, wanted 255\n", `+`, got) failed = true } if got := add_uint8_255_ssa(0); got != 255 { fmt.Printf("add_uint8 0%s255 = %d, wanted 255\n", `+`, got) failed = true } if got := add_255_uint8_ssa(1); got != 0 { fmt.Printf("add_uint8 255%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint8_255_ssa(1); got != 0 { fmt.Printf("add_uint8 1%s255 = %d, wanted 0\n", `+`, got) failed = true } if got := add_255_uint8_ssa(255); got != 254 { fmt.Printf("add_uint8 255%s255 = %d, wanted 254\n", `+`, got) failed = true } if got := add_uint8_255_ssa(255); got != 254 { fmt.Printf("add_uint8 255%s255 = %d, wanted 254\n", `+`, got) failed = true } if got := sub_0_uint8_ssa(0); got != 0 { fmt.Printf("sub_uint8 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint8_0_ssa(0); got != 0 { fmt.Printf("sub_uint8 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_uint8_ssa(1); got != 255 { fmt.Printf("sub_uint8 0%s1 = %d, wanted 255\n", `-`, got) failed = true } if got := sub_uint8_0_ssa(1); got != 1 { fmt.Printf("sub_uint8 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_uint8_ssa(255); got != 1 { fmt.Printf("sub_uint8 0%s255 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint8_0_ssa(255); got != 255 { fmt.Printf("sub_uint8 255%s0 = %d, wanted 255\n", `-`, got) failed = true } if got := sub_1_uint8_ssa(0); got != 1 { fmt.Printf("sub_uint8 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint8_1_ssa(0); got != 255 { fmt.Printf("sub_uint8 0%s1 = %d, wanted 255\n", `-`, got) failed = true } if got := sub_1_uint8_ssa(1); got != 0 { fmt.Printf("sub_uint8 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint8_1_ssa(1); got != 0 { fmt.Printf("sub_uint8 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_uint8_ssa(255); got != 2 { fmt.Printf("sub_uint8 1%s255 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_uint8_1_ssa(255); got != 254 { fmt.Printf("sub_uint8 255%s1 = %d, wanted 254\n", `-`, got) failed = true } if got := sub_255_uint8_ssa(0); got != 255 { fmt.Printf("sub_uint8 255%s0 = %d, wanted 255\n", `-`, got) failed = true } if got := sub_uint8_255_ssa(0); got != 1 { fmt.Printf("sub_uint8 0%s255 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_255_uint8_ssa(1); got != 254 { fmt.Printf("sub_uint8 255%s1 = %d, wanted 254\n", `-`, got) failed = true } if got := sub_uint8_255_ssa(1); got != 2 { fmt.Printf("sub_uint8 1%s255 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_255_uint8_ssa(255); got != 0 { fmt.Printf("sub_uint8 255%s255 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint8_255_ssa(255); got != 0 { fmt.Printf("sub_uint8 255%s255 = %d, wanted 0\n", `-`, got) failed = true } if got := div_0_uint8_ssa(1); got != 0 { fmt.Printf("div_uint8 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_uint8_ssa(255); got != 0 { fmt.Printf("div_uint8 0%s255 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint8_1_ssa(0); got != 0 { fmt.Printf("div_uint8 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_uint8_ssa(1); got != 1 { fmt.Printf("div_uint8 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint8_1_ssa(1); got != 1 { fmt.Printf("div_uint8 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_uint8_ssa(255); got != 0 { fmt.Printf("div_uint8 1%s255 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint8_1_ssa(255); got != 255 { fmt.Printf("div_uint8 255%s1 = %d, wanted 255\n", `/`, got) failed = true } if got := div_uint8_255_ssa(0); got != 0 { fmt.Printf("div_uint8 0%s255 = %d, wanted 0\n", `/`, got) failed = true } if got := div_255_uint8_ssa(1); got != 255 { fmt.Printf("div_uint8 255%s1 = %d, wanted 255\n", `/`, got) failed = true } if got := div_uint8_255_ssa(1); got != 0 { fmt.Printf("div_uint8 1%s255 = %d, wanted 0\n", `/`, got) failed = true } if got := div_255_uint8_ssa(255); got != 1 { fmt.Printf("div_uint8 255%s255 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint8_255_ssa(255); got != 1 { fmt.Printf("div_uint8 255%s255 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_0_uint8_ssa(0); got != 0 { fmt.Printf("mul_uint8 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint8_0_ssa(0); got != 0 { fmt.Printf("mul_uint8 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint8_ssa(1); got != 0 { fmt.Printf("mul_uint8 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint8_0_ssa(1); got != 0 { fmt.Printf("mul_uint8 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint8_ssa(255); got != 0 { fmt.Printf("mul_uint8 0%s255 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint8_0_ssa(255); got != 0 { fmt.Printf("mul_uint8 255%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint8_ssa(0); got != 0 { fmt.Printf("mul_uint8 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint8_1_ssa(0); got != 0 { fmt.Printf("mul_uint8 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint8_ssa(1); got != 1 { fmt.Printf("mul_uint8 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint8_1_ssa(1); got != 1 { fmt.Printf("mul_uint8 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_uint8_ssa(255); got != 255 { fmt.Printf("mul_uint8 1%s255 = %d, wanted 255\n", `*`, got) failed = true } if got := mul_uint8_1_ssa(255); got != 255 { fmt.Printf("mul_uint8 255%s1 = %d, wanted 255\n", `*`, got) failed = true } if got := mul_255_uint8_ssa(0); got != 0 { fmt.Printf("mul_uint8 255%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint8_255_ssa(0); got != 0 { fmt.Printf("mul_uint8 0%s255 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_255_uint8_ssa(1); got != 255 { fmt.Printf("mul_uint8 255%s1 = %d, wanted 255\n", `*`, got) failed = true } if got := mul_uint8_255_ssa(1); got != 255 { fmt.Printf("mul_uint8 1%s255 = %d, wanted 255\n", `*`, got) failed = true } if got := mul_255_uint8_ssa(255); got != 1 { fmt.Printf("mul_uint8 255%s255 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint8_255_ssa(255); got != 1 { fmt.Printf("mul_uint8 255%s255 = %d, wanted 1\n", `*`, got) failed = true } if got := lsh_0_uint8_ssa(0); got != 0 { fmt.Printf("lsh_uint8 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint8_0_ssa(0); got != 0 { fmt.Printf("lsh_uint8 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_0_uint8_ssa(1); got != 0 { fmt.Printf("lsh_uint8 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint8_0_ssa(1); got != 1 { fmt.Printf("lsh_uint8 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_0_uint8_ssa(255); got != 0 { fmt.Printf("lsh_uint8 0%s255 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint8_0_ssa(255); got != 255 { fmt.Printf("lsh_uint8 255%s0 = %d, wanted 255\n", `<<`, got) failed = true } if got := lsh_1_uint8_ssa(0); got != 1 { fmt.Printf("lsh_uint8 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_uint8_1_ssa(0); got != 0 { fmt.Printf("lsh_uint8 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_1_uint8_ssa(1); got != 2 { fmt.Printf("lsh_uint8 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_uint8_1_ssa(1); got != 2 { fmt.Printf("lsh_uint8 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_1_uint8_ssa(255); got != 0 { fmt.Printf("lsh_uint8 1%s255 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint8_1_ssa(255); got != 254 { fmt.Printf("lsh_uint8 255%s1 = %d, wanted 254\n", `<<`, got) failed = true } if got := lsh_255_uint8_ssa(0); got != 255 { fmt.Printf("lsh_uint8 255%s0 = %d, wanted 255\n", `<<`, got) failed = true } if got := lsh_uint8_255_ssa(0); got != 0 { fmt.Printf("lsh_uint8 0%s255 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_255_uint8_ssa(1); got != 254 { fmt.Printf("lsh_uint8 255%s1 = %d, wanted 254\n", `<<`, got) failed = true } if got := lsh_uint8_255_ssa(1); got != 0 { fmt.Printf("lsh_uint8 1%s255 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_255_uint8_ssa(255); got != 0 { fmt.Printf("lsh_uint8 255%s255 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint8_255_ssa(255); got != 0 { fmt.Printf("lsh_uint8 255%s255 = %d, wanted 0\n", `<<`, got) failed = true } if got := rsh_0_uint8_ssa(0); got != 0 { fmt.Printf("rsh_uint8 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint8_0_ssa(0); got != 0 { fmt.Printf("rsh_uint8 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_0_uint8_ssa(1); got != 0 { fmt.Printf("rsh_uint8 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint8_0_ssa(1); got != 1 { fmt.Printf("rsh_uint8 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_0_uint8_ssa(255); got != 0 { fmt.Printf("rsh_uint8 0%s255 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint8_0_ssa(255); got != 255 { fmt.Printf("rsh_uint8 255%s0 = %d, wanted 255\n", `>>`, got) failed = true } if got := rsh_1_uint8_ssa(0); got != 1 { fmt.Printf("rsh_uint8 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_uint8_1_ssa(0); got != 0 { fmt.Printf("rsh_uint8 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint8_ssa(1); got != 0 { fmt.Printf("rsh_uint8 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint8_1_ssa(1); got != 0 { fmt.Printf("rsh_uint8 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint8_ssa(255); got != 0 { fmt.Printf("rsh_uint8 1%s255 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint8_1_ssa(255); got != 127 { fmt.Printf("rsh_uint8 255%s1 = %d, wanted 127\n", `>>`, got) failed = true } if got := rsh_255_uint8_ssa(0); got != 255 { fmt.Printf("rsh_uint8 255%s0 = %d, wanted 255\n", `>>`, got) failed = true } if got := rsh_uint8_255_ssa(0); got != 0 { fmt.Printf("rsh_uint8 0%s255 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_255_uint8_ssa(1); got != 127 { fmt.Printf("rsh_uint8 255%s1 = %d, wanted 127\n", `>>`, got) failed = true } if got := rsh_uint8_255_ssa(1); got != 0 { fmt.Printf("rsh_uint8 1%s255 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_255_uint8_ssa(255); got != 0 { fmt.Printf("rsh_uint8 255%s255 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint8_255_ssa(255); got != 0 { fmt.Printf("rsh_uint8 255%s255 = %d, wanted 0\n", `>>`, got) failed = true } if got := mod_0_uint8_ssa(1); got != 0 { fmt.Printf("mod_uint8 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_uint8_ssa(255); got != 0 { fmt.Printf("mod_uint8 0%s255 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint8_1_ssa(0); got != 0 { fmt.Printf("mod_uint8 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint8_ssa(1); got != 0 { fmt.Printf("mod_uint8 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint8_1_ssa(1); got != 0 { fmt.Printf("mod_uint8 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint8_ssa(255); got != 1 { fmt.Printf("mod_uint8 1%s255 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_uint8_1_ssa(255); got != 0 { fmt.Printf("mod_uint8 255%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint8_255_ssa(0); got != 0 { fmt.Printf("mod_uint8 0%s255 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_255_uint8_ssa(1); got != 0 { fmt.Printf("mod_uint8 255%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint8_255_ssa(1); got != 1 { fmt.Printf("mod_uint8 1%s255 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_255_uint8_ssa(255); got != 0 { fmt.Printf("mod_uint8 255%s255 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint8_255_ssa(255); got != 0 { fmt.Printf("mod_uint8 255%s255 = %d, wanted 0\n", `%`, got) failed = true } if got := and_0_uint8_ssa(0); got != 0 { fmt.Printf("and_uint8 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint8_0_ssa(0); got != 0 { fmt.Printf("and_uint8 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint8_ssa(1); got != 0 { fmt.Printf("and_uint8 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint8_0_ssa(1); got != 0 { fmt.Printf("and_uint8 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint8_ssa(255); got != 0 { fmt.Printf("and_uint8 0%s255 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint8_0_ssa(255); got != 0 { fmt.Printf("and_uint8 255%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint8_ssa(0); got != 0 { fmt.Printf("and_uint8 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint8_1_ssa(0); got != 0 { fmt.Printf("and_uint8 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint8_ssa(1); got != 1 { fmt.Printf("and_uint8 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint8_1_ssa(1); got != 1 { fmt.Printf("and_uint8 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_uint8_ssa(255); got != 1 { fmt.Printf("and_uint8 1%s255 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint8_1_ssa(255); got != 1 { fmt.Printf("and_uint8 255%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_255_uint8_ssa(0); got != 0 { fmt.Printf("and_uint8 255%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint8_255_ssa(0); got != 0 { fmt.Printf("and_uint8 0%s255 = %d, wanted 0\n", `&`, got) failed = true } if got := and_255_uint8_ssa(1); got != 1 { fmt.Printf("and_uint8 255%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint8_255_ssa(1); got != 1 { fmt.Printf("and_uint8 1%s255 = %d, wanted 1\n", `&`, got) failed = true } if got := and_255_uint8_ssa(255); got != 255 { fmt.Printf("and_uint8 255%s255 = %d, wanted 255\n", `&`, got) failed = true } if got := and_uint8_255_ssa(255); got != 255 { fmt.Printf("and_uint8 255%s255 = %d, wanted 255\n", `&`, got) failed = true } if got := or_0_uint8_ssa(0); got != 0 { fmt.Printf("or_uint8 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_uint8_0_ssa(0); got != 0 { fmt.Printf("or_uint8 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_uint8_ssa(1); got != 1 { fmt.Printf("or_uint8 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint8_0_ssa(1); got != 1 { fmt.Printf("or_uint8 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_uint8_ssa(255); got != 255 { fmt.Printf("or_uint8 0%s255 = %d, wanted 255\n", `|`, got) failed = true } if got := or_uint8_0_ssa(255); got != 255 { fmt.Printf("or_uint8 255%s0 = %d, wanted 255\n", `|`, got) failed = true } if got := or_1_uint8_ssa(0); got != 1 { fmt.Printf("or_uint8 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint8_1_ssa(0); got != 1 { fmt.Printf("or_uint8 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint8_ssa(1); got != 1 { fmt.Printf("or_uint8 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint8_1_ssa(1); got != 1 { fmt.Printf("or_uint8 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint8_ssa(255); got != 255 { fmt.Printf("or_uint8 1%s255 = %d, wanted 255\n", `|`, got) failed = true } if got := or_uint8_1_ssa(255); got != 255 { fmt.Printf("or_uint8 255%s1 = %d, wanted 255\n", `|`, got) failed = true } if got := or_255_uint8_ssa(0); got != 255 { fmt.Printf("or_uint8 255%s0 = %d, wanted 255\n", `|`, got) failed = true } if got := or_uint8_255_ssa(0); got != 255 { fmt.Printf("or_uint8 0%s255 = %d, wanted 255\n", `|`, got) failed = true } if got := or_255_uint8_ssa(1); got != 255 { fmt.Printf("or_uint8 255%s1 = %d, wanted 255\n", `|`, got) failed = true } if got := or_uint8_255_ssa(1); got != 255 { fmt.Printf("or_uint8 1%s255 = %d, wanted 255\n", `|`, got) failed = true } if got := or_255_uint8_ssa(255); got != 255 { fmt.Printf("or_uint8 255%s255 = %d, wanted 255\n", `|`, got) failed = true } if got := or_uint8_255_ssa(255); got != 255 { fmt.Printf("or_uint8 255%s255 = %d, wanted 255\n", `|`, got) failed = true } if got := xor_0_uint8_ssa(0); got != 0 { fmt.Printf("xor_uint8 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint8_0_ssa(0); got != 0 { fmt.Printf("xor_uint8 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_uint8_ssa(1); got != 1 { fmt.Printf("xor_uint8 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint8_0_ssa(1); got != 1 { fmt.Printf("xor_uint8 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_uint8_ssa(255); got != 255 { fmt.Printf("xor_uint8 0%s255 = %d, wanted 255\n", `^`, got) failed = true } if got := xor_uint8_0_ssa(255); got != 255 { fmt.Printf("xor_uint8 255%s0 = %d, wanted 255\n", `^`, got) failed = true } if got := xor_1_uint8_ssa(0); got != 1 { fmt.Printf("xor_uint8 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint8_1_ssa(0); got != 1 { fmt.Printf("xor_uint8 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_uint8_ssa(1); got != 0 { fmt.Printf("xor_uint8 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint8_1_ssa(1); got != 0 { fmt.Printf("xor_uint8 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_uint8_ssa(255); got != 254 { fmt.Printf("xor_uint8 1%s255 = %d, wanted 254\n", `^`, got) failed = true } if got := xor_uint8_1_ssa(255); got != 254 { fmt.Printf("xor_uint8 255%s1 = %d, wanted 254\n", `^`, got) failed = true } if got := xor_255_uint8_ssa(0); got != 255 { fmt.Printf("xor_uint8 255%s0 = %d, wanted 255\n", `^`, got) failed = true } if got := xor_uint8_255_ssa(0); got != 255 { fmt.Printf("xor_uint8 0%s255 = %d, wanted 255\n", `^`, got) failed = true } if got := xor_255_uint8_ssa(1); got != 254 { fmt.Printf("xor_uint8 255%s1 = %d, wanted 254\n", `^`, got) failed = true } if got := xor_uint8_255_ssa(1); got != 254 { fmt.Printf("xor_uint8 1%s255 = %d, wanted 254\n", `^`, got) failed = true } if got := xor_255_uint8_ssa(255); got != 0 { fmt.Printf("xor_uint8 255%s255 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint8_255_ssa(255); got != 0 { fmt.Printf("xor_uint8 255%s255 = %d, wanted 0\n", `^`, got) failed = true } if got := add_Neg128_int8_ssa(-128); got != 0 { fmt.Printf("add_int8 -128%s-128 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(-128); got != 0 { fmt.Printf("add_int8 -128%s-128 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg128_int8_ssa(-127); got != 1 { fmt.Printf("add_int8 -128%s-127 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(-127); got != 1 { fmt.Printf("add_int8 -127%s-128 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg128_int8_ssa(-1); got != 127 { fmt.Printf("add_int8 -128%s-1 = %d, wanted 127\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(-1); got != 127 { fmt.Printf("add_int8 -1%s-128 = %d, wanted 127\n", `+`, got) failed = true } if got := add_Neg128_int8_ssa(0); got != -128 { fmt.Printf("add_int8 -128%s0 = %d, wanted -128\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(0); got != -128 { fmt.Printf("add_int8 0%s-128 = %d, wanted -128\n", `+`, got) failed = true } if got := add_Neg128_int8_ssa(1); got != -127 { fmt.Printf("add_int8 -128%s1 = %d, wanted -127\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(1); got != -127 { fmt.Printf("add_int8 1%s-128 = %d, wanted -127\n", `+`, got) failed = true } if got := add_Neg128_int8_ssa(126); got != -2 { fmt.Printf("add_int8 -128%s126 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(126); got != -2 { fmt.Printf("add_int8 126%s-128 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg128_int8_ssa(127); got != -1 { fmt.Printf("add_int8 -128%s127 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(127); got != -1 { fmt.Printf("add_int8 127%s-128 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(-128); got != 1 { fmt.Printf("add_int8 -127%s-128 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(-128); got != 1 { fmt.Printf("add_int8 -128%s-127 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(-127); got != 2 { fmt.Printf("add_int8 -127%s-127 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(-127); got != 2 { fmt.Printf("add_int8 -127%s-127 = %d, wanted 2\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(-1); got != -128 { fmt.Printf("add_int8 -127%s-1 = %d, wanted -128\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(-1); got != -128 { fmt.Printf("add_int8 -1%s-127 = %d, wanted -128\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(0); got != -127 { fmt.Printf("add_int8 -127%s0 = %d, wanted -127\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(0); got != -127 { fmt.Printf("add_int8 0%s-127 = %d, wanted -127\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(1); got != -126 { fmt.Printf("add_int8 -127%s1 = %d, wanted -126\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(1); got != -126 { fmt.Printf("add_int8 1%s-127 = %d, wanted -126\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(126); got != -1 { fmt.Printf("add_int8 -127%s126 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(126); got != -1 { fmt.Printf("add_int8 126%s-127 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(127); got != 0 { fmt.Printf("add_int8 -127%s127 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(127); got != 0 { fmt.Printf("add_int8 127%s-127 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(-128); got != 127 { fmt.Printf("add_int8 -1%s-128 = %d, wanted 127\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(-128); got != 127 { fmt.Printf("add_int8 -128%s-1 = %d, wanted 127\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(-127); got != -128 { fmt.Printf("add_int8 -1%s-127 = %d, wanted -128\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(-127); got != -128 { fmt.Printf("add_int8 -127%s-1 = %d, wanted -128\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(-1); got != -2 { fmt.Printf("add_int8 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(-1); got != -2 { fmt.Printf("add_int8 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(0); got != -1 { fmt.Printf("add_int8 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(0); got != -1 { fmt.Printf("add_int8 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(1); got != 0 { fmt.Printf("add_int8 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(1); got != 0 { fmt.Printf("add_int8 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(126); got != 125 { fmt.Printf("add_int8 -1%s126 = %d, wanted 125\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(126); got != 125 { fmt.Printf("add_int8 126%s-1 = %d, wanted 125\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(127); got != 126 { fmt.Printf("add_int8 -1%s127 = %d, wanted 126\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(127); got != 126 { fmt.Printf("add_int8 127%s-1 = %d, wanted 126\n", `+`, got) failed = true } if got := add_0_int8_ssa(-128); got != -128 { fmt.Printf("add_int8 0%s-128 = %d, wanted -128\n", `+`, got) failed = true } if got := add_int8_0_ssa(-128); got != -128 { fmt.Printf("add_int8 -128%s0 = %d, wanted -128\n", `+`, got) failed = true } if got := add_0_int8_ssa(-127); got != -127 { fmt.Printf("add_int8 0%s-127 = %d, wanted -127\n", `+`, got) failed = true } if got := add_int8_0_ssa(-127); got != -127 { fmt.Printf("add_int8 -127%s0 = %d, wanted -127\n", `+`, got) failed = true } if got := add_0_int8_ssa(-1); got != -1 { fmt.Printf("add_int8 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int8_0_ssa(-1); got != -1 { fmt.Printf("add_int8 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_0_int8_ssa(0); got != 0 { fmt.Printf("add_int8 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int8_0_ssa(0); got != 0 { fmt.Printf("add_int8 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_int8_ssa(1); got != 1 { fmt.Printf("add_int8 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int8_0_ssa(1); got != 1 { fmt.Printf("add_int8 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_int8_ssa(126); got != 126 { fmt.Printf("add_int8 0%s126 = %d, wanted 126\n", `+`, got) failed = true } if got := add_int8_0_ssa(126); got != 126 { fmt.Printf("add_int8 126%s0 = %d, wanted 126\n", `+`, got) failed = true } if got := add_0_int8_ssa(127); got != 127 { fmt.Printf("add_int8 0%s127 = %d, wanted 127\n", `+`, got) failed = true } if got := add_int8_0_ssa(127); got != 127 { fmt.Printf("add_int8 127%s0 = %d, wanted 127\n", `+`, got) failed = true } if got := add_1_int8_ssa(-128); got != -127 { fmt.Printf("add_int8 1%s-128 = %d, wanted -127\n", `+`, got) failed = true } if got := add_int8_1_ssa(-128); got != -127 { fmt.Printf("add_int8 -128%s1 = %d, wanted -127\n", `+`, got) failed = true } if got := add_1_int8_ssa(-127); got != -126 { fmt.Printf("add_int8 1%s-127 = %d, wanted -126\n", `+`, got) failed = true } if got := add_int8_1_ssa(-127); got != -126 { fmt.Printf("add_int8 -127%s1 = %d, wanted -126\n", `+`, got) failed = true } if got := add_1_int8_ssa(-1); got != 0 { fmt.Printf("add_int8 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int8_1_ssa(-1); got != 0 { fmt.Printf("add_int8 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_1_int8_ssa(0); got != 1 { fmt.Printf("add_int8 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int8_1_ssa(0); got != 1 { fmt.Printf("add_int8 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_int8_ssa(1); got != 2 { fmt.Printf("add_int8 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int8_1_ssa(1); got != 2 { fmt.Printf("add_int8 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_int8_ssa(126); got != 127 { fmt.Printf("add_int8 1%s126 = %d, wanted 127\n", `+`, got) failed = true } if got := add_int8_1_ssa(126); got != 127 { fmt.Printf("add_int8 126%s1 = %d, wanted 127\n", `+`, got) failed = true } if got := add_1_int8_ssa(127); got != -128 { fmt.Printf("add_int8 1%s127 = %d, wanted -128\n", `+`, got) failed = true } if got := add_int8_1_ssa(127); got != -128 { fmt.Printf("add_int8 127%s1 = %d, wanted -128\n", `+`, got) failed = true } if got := add_126_int8_ssa(-128); got != -2 { fmt.Printf("add_int8 126%s-128 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int8_126_ssa(-128); got != -2 { fmt.Printf("add_int8 -128%s126 = %d, wanted -2\n", `+`, got) failed = true } if got := add_126_int8_ssa(-127); got != -1 { fmt.Printf("add_int8 126%s-127 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int8_126_ssa(-127); got != -1 { fmt.Printf("add_int8 -127%s126 = %d, wanted -1\n", `+`, got) failed = true } if got := add_126_int8_ssa(-1); got != 125 { fmt.Printf("add_int8 126%s-1 = %d, wanted 125\n", `+`, got) failed = true } if got := add_int8_126_ssa(-1); got != 125 { fmt.Printf("add_int8 -1%s126 = %d, wanted 125\n", `+`, got) failed = true } if got := add_126_int8_ssa(0); got != 126 { fmt.Printf("add_int8 126%s0 = %d, wanted 126\n", `+`, got) failed = true } if got := add_int8_126_ssa(0); got != 126 { fmt.Printf("add_int8 0%s126 = %d, wanted 126\n", `+`, got) failed = true } if got := add_126_int8_ssa(1); got != 127 { fmt.Printf("add_int8 126%s1 = %d, wanted 127\n", `+`, got) failed = true } if got := add_int8_126_ssa(1); got != 127 { fmt.Printf("add_int8 1%s126 = %d, wanted 127\n", `+`, got) failed = true } if got := add_126_int8_ssa(126); got != -4 { fmt.Printf("add_int8 126%s126 = %d, wanted -4\n", `+`, got) failed = true } if got := add_int8_126_ssa(126); got != -4 { fmt.Printf("add_int8 126%s126 = %d, wanted -4\n", `+`, got) failed = true } if got := add_126_int8_ssa(127); got != -3 { fmt.Printf("add_int8 126%s127 = %d, wanted -3\n", `+`, got) failed = true } if got := add_int8_126_ssa(127); got != -3 { fmt.Printf("add_int8 127%s126 = %d, wanted -3\n", `+`, got) failed = true } if got := add_127_int8_ssa(-128); got != -1 { fmt.Printf("add_int8 127%s-128 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int8_127_ssa(-128); got != -1 { fmt.Printf("add_int8 -128%s127 = %d, wanted -1\n", `+`, got) failed = true } if got := add_127_int8_ssa(-127); got != 0 { fmt.Printf("add_int8 127%s-127 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int8_127_ssa(-127); got != 0 { fmt.Printf("add_int8 -127%s127 = %d, wanted 0\n", `+`, got) failed = true } if got := add_127_int8_ssa(-1); got != 126 { fmt.Printf("add_int8 127%s-1 = %d, wanted 126\n", `+`, got) failed = true } if got := add_int8_127_ssa(-1); got != 126 { fmt.Printf("add_int8 -1%s127 = %d, wanted 126\n", `+`, got) failed = true } if got := add_127_int8_ssa(0); got != 127 { fmt.Printf("add_int8 127%s0 = %d, wanted 127\n", `+`, got) failed = true } if got := add_int8_127_ssa(0); got != 127 { fmt.Printf("add_int8 0%s127 = %d, wanted 127\n", `+`, got) failed = true } if got := add_127_int8_ssa(1); got != -128 { fmt.Printf("add_int8 127%s1 = %d, wanted -128\n", `+`, got) failed = true } if got := add_int8_127_ssa(1); got != -128 { fmt.Printf("add_int8 1%s127 = %d, wanted -128\n", `+`, got) failed = true } if got := add_127_int8_ssa(126); got != -3 { fmt.Printf("add_int8 127%s126 = %d, wanted -3\n", `+`, got) failed = true } if got := add_int8_127_ssa(126); got != -3 { fmt.Printf("add_int8 126%s127 = %d, wanted -3\n", `+`, got) failed = true } if got := add_127_int8_ssa(127); got != -2 { fmt.Printf("add_int8 127%s127 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int8_127_ssa(127); got != -2 { fmt.Printf("add_int8 127%s127 = %d, wanted -2\n", `+`, got) failed = true } if got := sub_Neg128_int8_ssa(-128); got != 0 { fmt.Printf("sub_int8 -128%s-128 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(-128); got != 0 { fmt.Printf("sub_int8 -128%s-128 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg128_int8_ssa(-127); got != -1 { fmt.Printf("sub_int8 -128%s-127 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(-127); got != 1 { fmt.Printf("sub_int8 -127%s-128 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg128_int8_ssa(-1); got != -127 { fmt.Printf("sub_int8 -128%s-1 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(-1); got != 127 { fmt.Printf("sub_int8 -1%s-128 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_Neg128_int8_ssa(0); got != -128 { fmt.Printf("sub_int8 -128%s0 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(0); got != -128 { fmt.Printf("sub_int8 0%s-128 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_Neg128_int8_ssa(1); got != 127 { fmt.Printf("sub_int8 -128%s1 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(1); got != -127 { fmt.Printf("sub_int8 1%s-128 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_Neg128_int8_ssa(126); got != 2 { fmt.Printf("sub_int8 -128%s126 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(126); got != -2 { fmt.Printf("sub_int8 126%s-128 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg128_int8_ssa(127); got != 1 { fmt.Printf("sub_int8 -128%s127 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(127); got != -1 { fmt.Printf("sub_int8 127%s-128 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(-128); got != 1 { fmt.Printf("sub_int8 -127%s-128 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(-128); got != -1 { fmt.Printf("sub_int8 -128%s-127 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(-127); got != 0 { fmt.Printf("sub_int8 -127%s-127 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(-127); got != 0 { fmt.Printf("sub_int8 -127%s-127 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(-1); got != -126 { fmt.Printf("sub_int8 -127%s-1 = %d, wanted -126\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(-1); got != 126 { fmt.Printf("sub_int8 -1%s-127 = %d, wanted 126\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(0); got != -127 { fmt.Printf("sub_int8 -127%s0 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(0); got != 127 { fmt.Printf("sub_int8 0%s-127 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(1); got != -128 { fmt.Printf("sub_int8 -127%s1 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(1); got != -128 { fmt.Printf("sub_int8 1%s-127 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(126); got != 3 { fmt.Printf("sub_int8 -127%s126 = %d, wanted 3\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(126); got != -3 { fmt.Printf("sub_int8 126%s-127 = %d, wanted -3\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(127); got != 2 { fmt.Printf("sub_int8 -127%s127 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(127); got != -2 { fmt.Printf("sub_int8 127%s-127 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(-128); got != 127 { fmt.Printf("sub_int8 -1%s-128 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(-128); got != -127 { fmt.Printf("sub_int8 -128%s-1 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(-127); got != 126 { fmt.Printf("sub_int8 -1%s-127 = %d, wanted 126\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(-127); got != -126 { fmt.Printf("sub_int8 -127%s-1 = %d, wanted -126\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(-1); got != 0 { fmt.Printf("sub_int8 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(-1); got != 0 { fmt.Printf("sub_int8 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(0); got != -1 { fmt.Printf("sub_int8 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(0); got != 1 { fmt.Printf("sub_int8 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(1); got != -2 { fmt.Printf("sub_int8 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(1); got != 2 { fmt.Printf("sub_int8 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(126); got != -127 { fmt.Printf("sub_int8 -1%s126 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(126); got != 127 { fmt.Printf("sub_int8 126%s-1 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(127); got != -128 { fmt.Printf("sub_int8 -1%s127 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(127); got != -128 { fmt.Printf("sub_int8 127%s-1 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_0_int8_ssa(-128); got != -128 { fmt.Printf("sub_int8 0%s-128 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_int8_0_ssa(-128); got != -128 { fmt.Printf("sub_int8 -128%s0 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_0_int8_ssa(-127); got != 127 { fmt.Printf("sub_int8 0%s-127 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_int8_0_ssa(-127); got != -127 { fmt.Printf("sub_int8 -127%s0 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_0_int8_ssa(-1); got != 1 { fmt.Printf("sub_int8 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int8_0_ssa(-1); got != -1 { fmt.Printf("sub_int8 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_0_int8_ssa(0); got != 0 { fmt.Printf("sub_int8 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_0_ssa(0); got != 0 { fmt.Printf("sub_int8 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_int8_ssa(1); got != -1 { fmt.Printf("sub_int8 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int8_0_ssa(1); got != 1 { fmt.Printf("sub_int8 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_int8_ssa(126); got != -126 { fmt.Printf("sub_int8 0%s126 = %d, wanted -126\n", `-`, got) failed = true } if got := sub_int8_0_ssa(126); got != 126 { fmt.Printf("sub_int8 126%s0 = %d, wanted 126\n", `-`, got) failed = true } if got := sub_0_int8_ssa(127); got != -127 { fmt.Printf("sub_int8 0%s127 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_int8_0_ssa(127); got != 127 { fmt.Printf("sub_int8 127%s0 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_1_int8_ssa(-128); got != -127 { fmt.Printf("sub_int8 1%s-128 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_int8_1_ssa(-128); got != 127 { fmt.Printf("sub_int8 -128%s1 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_1_int8_ssa(-127); got != -128 { fmt.Printf("sub_int8 1%s-127 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_int8_1_ssa(-127); got != -128 { fmt.Printf("sub_int8 -127%s1 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_1_int8_ssa(-1); got != 2 { fmt.Printf("sub_int8 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int8_1_ssa(-1); got != -2 { fmt.Printf("sub_int8 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_1_int8_ssa(0); got != 1 { fmt.Printf("sub_int8 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int8_1_ssa(0); got != -1 { fmt.Printf("sub_int8 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_1_int8_ssa(1); got != 0 { fmt.Printf("sub_int8 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_1_ssa(1); got != 0 { fmt.Printf("sub_int8 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_int8_ssa(126); got != -125 { fmt.Printf("sub_int8 1%s126 = %d, wanted -125\n", `-`, got) failed = true } if got := sub_int8_1_ssa(126); got != 125 { fmt.Printf("sub_int8 126%s1 = %d, wanted 125\n", `-`, got) failed = true } if got := sub_1_int8_ssa(127); got != -126 { fmt.Printf("sub_int8 1%s127 = %d, wanted -126\n", `-`, got) failed = true } if got := sub_int8_1_ssa(127); got != 126 { fmt.Printf("sub_int8 127%s1 = %d, wanted 126\n", `-`, got) failed = true } if got := sub_126_int8_ssa(-128); got != -2 { fmt.Printf("sub_int8 126%s-128 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int8_126_ssa(-128); got != 2 { fmt.Printf("sub_int8 -128%s126 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_126_int8_ssa(-127); got != -3 { fmt.Printf("sub_int8 126%s-127 = %d, wanted -3\n", `-`, got) failed = true } if got := sub_int8_126_ssa(-127); got != 3 { fmt.Printf("sub_int8 -127%s126 = %d, wanted 3\n", `-`, got) failed = true } if got := sub_126_int8_ssa(-1); got != 127 { fmt.Printf("sub_int8 126%s-1 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_int8_126_ssa(-1); got != -127 { fmt.Printf("sub_int8 -1%s126 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_126_int8_ssa(0); got != 126 { fmt.Printf("sub_int8 126%s0 = %d, wanted 126\n", `-`, got) failed = true } if got := sub_int8_126_ssa(0); got != -126 { fmt.Printf("sub_int8 0%s126 = %d, wanted -126\n", `-`, got) failed = true } if got := sub_126_int8_ssa(1); got != 125 { fmt.Printf("sub_int8 126%s1 = %d, wanted 125\n", `-`, got) failed = true } if got := sub_int8_126_ssa(1); got != -125 { fmt.Printf("sub_int8 1%s126 = %d, wanted -125\n", `-`, got) failed = true } if got := sub_126_int8_ssa(126); got != 0 { fmt.Printf("sub_int8 126%s126 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_126_ssa(126); got != 0 { fmt.Printf("sub_int8 126%s126 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_126_int8_ssa(127); got != -1 { fmt.Printf("sub_int8 126%s127 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int8_126_ssa(127); got != 1 { fmt.Printf("sub_int8 127%s126 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_127_int8_ssa(-128); got != -1 { fmt.Printf("sub_int8 127%s-128 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int8_127_ssa(-128); got != 1 { fmt.Printf("sub_int8 -128%s127 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_127_int8_ssa(-127); got != -2 { fmt.Printf("sub_int8 127%s-127 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int8_127_ssa(-127); got != 2 { fmt.Printf("sub_int8 -127%s127 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_127_int8_ssa(-1); got != -128 { fmt.Printf("sub_int8 127%s-1 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_int8_127_ssa(-1); got != -128 { fmt.Printf("sub_int8 -1%s127 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_127_int8_ssa(0); got != 127 { fmt.Printf("sub_int8 127%s0 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_int8_127_ssa(0); got != -127 { fmt.Printf("sub_int8 0%s127 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_127_int8_ssa(1); got != 126 { fmt.Printf("sub_int8 127%s1 = %d, wanted 126\n", `-`, got) failed = true } if got := sub_int8_127_ssa(1); got != -126 { fmt.Printf("sub_int8 1%s127 = %d, wanted -126\n", `-`, got) failed = true } if got := sub_127_int8_ssa(126); got != 1 { fmt.Printf("sub_int8 127%s126 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int8_127_ssa(126); got != -1 { fmt.Printf("sub_int8 126%s127 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_127_int8_ssa(127); got != 0 { fmt.Printf("sub_int8 127%s127 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_127_ssa(127); got != 0 { fmt.Printf("sub_int8 127%s127 = %d, wanted 0\n", `-`, got) failed = true } if got := div_Neg128_int8_ssa(-128); got != 1 { fmt.Printf("div_int8 -128%s-128 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(-128); got != 1 { fmt.Printf("div_int8 -128%s-128 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg128_int8_ssa(-127); got != 1 { fmt.Printf("div_int8 -128%s-127 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(-127); got != 0 { fmt.Printf("div_int8 -127%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg128_int8_ssa(-1); got != -128 { fmt.Printf("div_int8 -128%s-1 = %d, wanted -128\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(-1); got != 0 { fmt.Printf("div_int8 -1%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(0); got != 0 { fmt.Printf("div_int8 0%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg128_int8_ssa(1); got != -128 { fmt.Printf("div_int8 -128%s1 = %d, wanted -128\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(1); got != 0 { fmt.Printf("div_int8 1%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg128_int8_ssa(126); got != -1 { fmt.Printf("div_int8 -128%s126 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(126); got != 0 { fmt.Printf("div_int8 126%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg128_int8_ssa(127); got != -1 { fmt.Printf("div_int8 -128%s127 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(127); got != 0 { fmt.Printf("div_int8 127%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg127_int8_ssa(-128); got != 0 { fmt.Printf("div_int8 -127%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(-128); got != 1 { fmt.Printf("div_int8 -128%s-127 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg127_int8_ssa(-127); got != 1 { fmt.Printf("div_int8 -127%s-127 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(-127); got != 1 { fmt.Printf("div_int8 -127%s-127 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg127_int8_ssa(-1); got != 127 { fmt.Printf("div_int8 -127%s-1 = %d, wanted 127\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(-1); got != 0 { fmt.Printf("div_int8 -1%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(0); got != 0 { fmt.Printf("div_int8 0%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg127_int8_ssa(1); got != -127 { fmt.Printf("div_int8 -127%s1 = %d, wanted -127\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(1); got != 0 { fmt.Printf("div_int8 1%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg127_int8_ssa(126); got != -1 { fmt.Printf("div_int8 -127%s126 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(126); got != 0 { fmt.Printf("div_int8 126%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg127_int8_ssa(127); got != -1 { fmt.Printf("div_int8 -127%s127 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(127); got != -1 { fmt.Printf("div_int8 127%s-127 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int8_ssa(-128); got != 0 { fmt.Printf("div_int8 -1%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(-128); got != -128 { fmt.Printf("div_int8 -128%s-1 = %d, wanted -128\n", `/`, got) failed = true } if got := div_Neg1_int8_ssa(-127); got != 0 { fmt.Printf("div_int8 -1%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(-127); got != 127 { fmt.Printf("div_int8 -127%s-1 = %d, wanted 127\n", `/`, got) failed = true } if got := div_Neg1_int8_ssa(-1); got != 1 { fmt.Printf("div_int8 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(-1); got != 1 { fmt.Printf("div_int8 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(0); got != 0 { fmt.Printf("div_int8 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg1_int8_ssa(1); got != -1 { fmt.Printf("div_int8 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(1); got != -1 { fmt.Printf("div_int8 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int8_ssa(126); got != 0 { fmt.Printf("div_int8 -1%s126 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(126); got != -126 { fmt.Printf("div_int8 126%s-1 = %d, wanted -126\n", `/`, got) failed = true } if got := div_Neg1_int8_ssa(127); got != 0 { fmt.Printf("div_int8 -1%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(127); got != -127 { fmt.Printf("div_int8 127%s-1 = %d, wanted -127\n", `/`, got) failed = true } if got := div_0_int8_ssa(-128); got != 0 { fmt.Printf("div_int8 0%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int8_ssa(-127); got != 0 { fmt.Printf("div_int8 0%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int8_ssa(-1); got != 0 { fmt.Printf("div_int8 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int8_ssa(1); got != 0 { fmt.Printf("div_int8 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int8_ssa(126); got != 0 { fmt.Printf("div_int8 0%s126 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int8_ssa(127); got != 0 { fmt.Printf("div_int8 0%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int8_ssa(-128); got != 0 { fmt.Printf("div_int8 1%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_1_ssa(-128); got != -128 { fmt.Printf("div_int8 -128%s1 = %d, wanted -128\n", `/`, got) failed = true } if got := div_1_int8_ssa(-127); got != 0 { fmt.Printf("div_int8 1%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_1_ssa(-127); got != -127 { fmt.Printf("div_int8 -127%s1 = %d, wanted -127\n", `/`, got) failed = true } if got := div_1_int8_ssa(-1); got != -1 { fmt.Printf("div_int8 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_1_ssa(-1); got != -1 { fmt.Printf("div_int8 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_1_ssa(0); got != 0 { fmt.Printf("div_int8 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int8_ssa(1); got != 1 { fmt.Printf("div_int8 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_1_ssa(1); got != 1 { fmt.Printf("div_int8 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_int8_ssa(126); got != 0 { fmt.Printf("div_int8 1%s126 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_1_ssa(126); got != 126 { fmt.Printf("div_int8 126%s1 = %d, wanted 126\n", `/`, got) failed = true } if got := div_1_int8_ssa(127); got != 0 { fmt.Printf("div_int8 1%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_1_ssa(127); got != 127 { fmt.Printf("div_int8 127%s1 = %d, wanted 127\n", `/`, got) failed = true } if got := div_126_int8_ssa(-128); got != 0 { fmt.Printf("div_int8 126%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_126_ssa(-128); got != -1 { fmt.Printf("div_int8 -128%s126 = %d, wanted -1\n", `/`, got) failed = true } if got := div_126_int8_ssa(-127); got != 0 { fmt.Printf("div_int8 126%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_126_ssa(-127); got != -1 { fmt.Printf("div_int8 -127%s126 = %d, wanted -1\n", `/`, got) failed = true } if got := div_126_int8_ssa(-1); got != -126 { fmt.Printf("div_int8 126%s-1 = %d, wanted -126\n", `/`, got) failed = true } if got := div_int8_126_ssa(-1); got != 0 { fmt.Printf("div_int8 -1%s126 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_126_ssa(0); got != 0 { fmt.Printf("div_int8 0%s126 = %d, wanted 0\n", `/`, got) failed = true } if got := div_126_int8_ssa(1); got != 126 { fmt.Printf("div_int8 126%s1 = %d, wanted 126\n", `/`, got) failed = true } if got := div_int8_126_ssa(1); got != 0 { fmt.Printf("div_int8 1%s126 = %d, wanted 0\n", `/`, got) failed = true } if got := div_126_int8_ssa(126); got != 1 { fmt.Printf("div_int8 126%s126 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_126_ssa(126); got != 1 { fmt.Printf("div_int8 126%s126 = %d, wanted 1\n", `/`, got) failed = true } if got := div_126_int8_ssa(127); got != 0 { fmt.Printf("div_int8 126%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_126_ssa(127); got != 1 { fmt.Printf("div_int8 127%s126 = %d, wanted 1\n", `/`, got) failed = true } if got := div_127_int8_ssa(-128); got != 0 { fmt.Printf("div_int8 127%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_127_ssa(-128); got != -1 { fmt.Printf("div_int8 -128%s127 = %d, wanted -1\n", `/`, got) failed = true } if got := div_127_int8_ssa(-127); got != -1 { fmt.Printf("div_int8 127%s-127 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_127_ssa(-127); got != -1 { fmt.Printf("div_int8 -127%s127 = %d, wanted -1\n", `/`, got) failed = true } if got := div_127_int8_ssa(-1); got != -127 { fmt.Printf("div_int8 127%s-1 = %d, wanted -127\n", `/`, got) failed = true } if got := div_int8_127_ssa(-1); got != 0 { fmt.Printf("div_int8 -1%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_127_ssa(0); got != 0 { fmt.Printf("div_int8 0%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_127_int8_ssa(1); got != 127 { fmt.Printf("div_int8 127%s1 = %d, wanted 127\n", `/`, got) failed = true } if got := div_int8_127_ssa(1); got != 0 { fmt.Printf("div_int8 1%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_127_int8_ssa(126); got != 1 { fmt.Printf("div_int8 127%s126 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_127_ssa(126); got != 0 { fmt.Printf("div_int8 126%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_127_int8_ssa(127); got != 1 { fmt.Printf("div_int8 127%s127 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_127_ssa(127); got != 1 { fmt.Printf("div_int8 127%s127 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_Neg128_int8_ssa(-128); got != 0 { fmt.Printf("mul_int8 -128%s-128 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(-128); got != 0 { fmt.Printf("mul_int8 -128%s-128 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg128_int8_ssa(-127); got != -128 { fmt.Printf("mul_int8 -128%s-127 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(-127); got != -128 { fmt.Printf("mul_int8 -127%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_Neg128_int8_ssa(-1); got != -128 { fmt.Printf("mul_int8 -128%s-1 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(-1); got != -128 { fmt.Printf("mul_int8 -1%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_Neg128_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 -128%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s-128 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg128_int8_ssa(1); got != -128 { fmt.Printf("mul_int8 -128%s1 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(1); got != -128 { fmt.Printf("mul_int8 1%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_Neg128_int8_ssa(126); got != 0 { fmt.Printf("mul_int8 -128%s126 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(126); got != 0 { fmt.Printf("mul_int8 126%s-128 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg128_int8_ssa(127); got != -128 { fmt.Printf("mul_int8 -128%s127 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(127); got != -128 { fmt.Printf("mul_int8 127%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(-128); got != -128 { fmt.Printf("mul_int8 -127%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(-128); got != -128 { fmt.Printf("mul_int8 -128%s-127 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(-127); got != 1 { fmt.Printf("mul_int8 -127%s-127 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(-127); got != 1 { fmt.Printf("mul_int8 -127%s-127 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(-1); got != 127 { fmt.Printf("mul_int8 -127%s-1 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(-1); got != 127 { fmt.Printf("mul_int8 -1%s-127 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 -127%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s-127 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(1); got != -127 { fmt.Printf("mul_int8 -127%s1 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(1); got != -127 { fmt.Printf("mul_int8 1%s-127 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(126); got != 126 { fmt.Printf("mul_int8 -127%s126 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(126); got != 126 { fmt.Printf("mul_int8 126%s-127 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(127); got != -1 { fmt.Printf("mul_int8 -127%s127 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(127); got != -1 { fmt.Printf("mul_int8 127%s-127 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(-128); got != -128 { fmt.Printf("mul_int8 -1%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(-128); got != -128 { fmt.Printf("mul_int8 -128%s-1 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(-127); got != 127 { fmt.Printf("mul_int8 -1%s-127 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(-127); got != 127 { fmt.Printf("mul_int8 -127%s-1 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(-1); got != 1 { fmt.Printf("mul_int8 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(-1); got != 1 { fmt.Printf("mul_int8 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(1); got != -1 { fmt.Printf("mul_int8 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(1); got != -1 { fmt.Printf("mul_int8 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(126); got != -126 { fmt.Printf("mul_int8 -1%s126 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(126); got != -126 { fmt.Printf("mul_int8 126%s-1 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(127); got != -127 { fmt.Printf("mul_int8 -1%s127 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(127); got != -127 { fmt.Printf("mul_int8 127%s-1 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_0_int8_ssa(-128); got != 0 { fmt.Printf("mul_int8 0%s-128 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(-128); got != 0 { fmt.Printf("mul_int8 -128%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int8_ssa(-127); got != 0 { fmt.Printf("mul_int8 0%s-127 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(-127); got != 0 { fmt.Printf("mul_int8 -127%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int8_ssa(-1); got != 0 { fmt.Printf("mul_int8 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(-1); got != 0 { fmt.Printf("mul_int8 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int8_ssa(1); got != 0 { fmt.Printf("mul_int8 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(1); got != 0 { fmt.Printf("mul_int8 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int8_ssa(126); got != 0 { fmt.Printf("mul_int8 0%s126 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(126); got != 0 { fmt.Printf("mul_int8 126%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int8_ssa(127); got != 0 { fmt.Printf("mul_int8 0%s127 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(127); got != 0 { fmt.Printf("mul_int8 127%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int8_ssa(-128); got != -128 { fmt.Printf("mul_int8 1%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_1_ssa(-128); got != -128 { fmt.Printf("mul_int8 -128%s1 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_1_int8_ssa(-127); got != -127 { fmt.Printf("mul_int8 1%s-127 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_int8_1_ssa(-127); got != -127 { fmt.Printf("mul_int8 -127%s1 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_1_int8_ssa(-1); got != -1 { fmt.Printf("mul_int8 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int8_1_ssa(-1); got != -1 { fmt.Printf("mul_int8 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_1_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_1_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int8_ssa(1); got != 1 { fmt.Printf("mul_int8 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int8_1_ssa(1); got != 1 { fmt.Printf("mul_int8 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_int8_ssa(126); got != 126 { fmt.Printf("mul_int8 1%s126 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_int8_1_ssa(126); got != 126 { fmt.Printf("mul_int8 126%s1 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_1_int8_ssa(127); got != 127 { fmt.Printf("mul_int8 1%s127 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_int8_1_ssa(127); got != 127 { fmt.Printf("mul_int8 127%s1 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_126_int8_ssa(-128); got != 0 { fmt.Printf("mul_int8 126%s-128 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_126_ssa(-128); got != 0 { fmt.Printf("mul_int8 -128%s126 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_126_int8_ssa(-127); got != 126 { fmt.Printf("mul_int8 126%s-127 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_int8_126_ssa(-127); got != 126 { fmt.Printf("mul_int8 -127%s126 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_126_int8_ssa(-1); got != -126 { fmt.Printf("mul_int8 126%s-1 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_int8_126_ssa(-1); got != -126 { fmt.Printf("mul_int8 -1%s126 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_126_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 126%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_126_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s126 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_126_int8_ssa(1); got != 126 { fmt.Printf("mul_int8 126%s1 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_int8_126_ssa(1); got != 126 { fmt.Printf("mul_int8 1%s126 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_126_int8_ssa(126); got != 4 { fmt.Printf("mul_int8 126%s126 = %d, wanted 4\n", `*`, got) failed = true } if got := mul_int8_126_ssa(126); got != 4 { fmt.Printf("mul_int8 126%s126 = %d, wanted 4\n", `*`, got) failed = true } if got := mul_126_int8_ssa(127); got != -126 { fmt.Printf("mul_int8 126%s127 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_int8_126_ssa(127); got != -126 { fmt.Printf("mul_int8 127%s126 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_127_int8_ssa(-128); got != -128 { fmt.Printf("mul_int8 127%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_127_ssa(-128); got != -128 { fmt.Printf("mul_int8 -128%s127 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_127_int8_ssa(-127); got != -1 { fmt.Printf("mul_int8 127%s-127 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int8_127_ssa(-127); got != -1 { fmt.Printf("mul_int8 -127%s127 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_127_int8_ssa(-1); got != -127 { fmt.Printf("mul_int8 127%s-1 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_int8_127_ssa(-1); got != -127 { fmt.Printf("mul_int8 -1%s127 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_127_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 127%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_127_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s127 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_127_int8_ssa(1); got != 127 { fmt.Printf("mul_int8 127%s1 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_int8_127_ssa(1); got != 127 { fmt.Printf("mul_int8 1%s127 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_127_int8_ssa(126); got != -126 { fmt.Printf("mul_int8 127%s126 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_int8_127_ssa(126); got != -126 { fmt.Printf("mul_int8 126%s127 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_127_int8_ssa(127); got != 1 { fmt.Printf("mul_int8 127%s127 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int8_127_ssa(127); got != 1 { fmt.Printf("mul_int8 127%s127 = %d, wanted 1\n", `*`, got) failed = true } if got := mod_Neg128_int8_ssa(-128); got != 0 { fmt.Printf("mod_int8 -128%s-128 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(-128); got != 0 { fmt.Printf("mod_int8 -128%s-128 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg128_int8_ssa(-127); got != -1 { fmt.Printf("mod_int8 -128%s-127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(-127); got != -127 { fmt.Printf("mod_int8 -127%s-128 = %d, wanted -127\n", `%`, got) failed = true } if got := mod_Neg128_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 -128%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(-1); got != -1 { fmt.Printf("mod_int8 -1%s-128 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(0); got != 0 { fmt.Printf("mod_int8 0%s-128 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg128_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 -128%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(1); got != 1 { fmt.Printf("mod_int8 1%s-128 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg128_int8_ssa(126); got != -2 { fmt.Printf("mod_int8 -128%s126 = %d, wanted -2\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(126); got != 126 { fmt.Printf("mod_int8 126%s-128 = %d, wanted 126\n", `%`, got) failed = true } if got := mod_Neg128_int8_ssa(127); got != -1 { fmt.Printf("mod_int8 -128%s127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(127); got != 127 { fmt.Printf("mod_int8 127%s-128 = %d, wanted 127\n", `%`, got) failed = true } if got := mod_Neg127_int8_ssa(-128); got != -127 { fmt.Printf("mod_int8 -127%s-128 = %d, wanted -127\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(-128); got != -1 { fmt.Printf("mod_int8 -128%s-127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_Neg127_int8_ssa(-127); got != 0 { fmt.Printf("mod_int8 -127%s-127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(-127); got != 0 { fmt.Printf("mod_int8 -127%s-127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg127_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 -127%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(-1); got != -1 { fmt.Printf("mod_int8 -1%s-127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(0); got != 0 { fmt.Printf("mod_int8 0%s-127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg127_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 -127%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(1); got != 1 { fmt.Printf("mod_int8 1%s-127 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg127_int8_ssa(126); got != -1 { fmt.Printf("mod_int8 -127%s126 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(126); got != 126 { fmt.Printf("mod_int8 126%s-127 = %d, wanted 126\n", `%`, got) failed = true } if got := mod_Neg127_int8_ssa(127); got != 0 { fmt.Printf("mod_int8 -127%s127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(127); got != 0 { fmt.Printf("mod_int8 127%s-127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int8_ssa(-128); got != -1 { fmt.Printf("mod_int8 -1%s-128 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(-128); got != 0 { fmt.Printf("mod_int8 -128%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int8_ssa(-127); got != -1 { fmt.Printf("mod_int8 -1%s-127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(-127); got != 0 { fmt.Printf("mod_int8 -127%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(-1); got != 0 { fmt.Printf("mod_int8 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(0); got != 0 { fmt.Printf("mod_int8 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(1); got != 0 { fmt.Printf("mod_int8 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int8_ssa(126); got != -1 { fmt.Printf("mod_int8 -1%s126 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(126); got != 0 { fmt.Printf("mod_int8 126%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int8_ssa(127); got != -1 { fmt.Printf("mod_int8 -1%s127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(127); got != 0 { fmt.Printf("mod_int8 127%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int8_ssa(-128); got != 0 { fmt.Printf("mod_int8 0%s-128 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int8_ssa(-127); got != 0 { fmt.Printf("mod_int8 0%s-127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int8_ssa(126); got != 0 { fmt.Printf("mod_int8 0%s126 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int8_ssa(127); got != 0 { fmt.Printf("mod_int8 0%s127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int8_ssa(-128); got != 1 { fmt.Printf("mod_int8 1%s-128 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int8_1_ssa(-128); got != 0 { fmt.Printf("mod_int8 -128%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int8_ssa(-127); got != 1 { fmt.Printf("mod_int8 1%s-127 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int8_1_ssa(-127); got != 0 { fmt.Printf("mod_int8 -127%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_1_ssa(-1); got != 0 { fmt.Printf("mod_int8 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_1_ssa(0); got != 0 { fmt.Printf("mod_int8 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_1_ssa(1); got != 0 { fmt.Printf("mod_int8 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int8_ssa(126); got != 1 { fmt.Printf("mod_int8 1%s126 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int8_1_ssa(126); got != 0 { fmt.Printf("mod_int8 126%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int8_ssa(127); got != 1 { fmt.Printf("mod_int8 1%s127 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int8_1_ssa(127); got != 0 { fmt.Printf("mod_int8 127%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_126_int8_ssa(-128); got != 126 { fmt.Printf("mod_int8 126%s-128 = %d, wanted 126\n", `%`, got) failed = true } if got := mod_int8_126_ssa(-128); got != -2 { fmt.Printf("mod_int8 -128%s126 = %d, wanted -2\n", `%`, got) failed = true } if got := mod_126_int8_ssa(-127); got != 126 { fmt.Printf("mod_int8 126%s-127 = %d, wanted 126\n", `%`, got) failed = true } if got := mod_int8_126_ssa(-127); got != -1 { fmt.Printf("mod_int8 -127%s126 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_126_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 126%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_126_ssa(-1); got != -1 { fmt.Printf("mod_int8 -1%s126 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_126_ssa(0); got != 0 { fmt.Printf("mod_int8 0%s126 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_126_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 126%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_126_ssa(1); got != 1 { fmt.Printf("mod_int8 1%s126 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_126_int8_ssa(126); got != 0 { fmt.Printf("mod_int8 126%s126 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_126_ssa(126); got != 0 { fmt.Printf("mod_int8 126%s126 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_126_int8_ssa(127); got != 126 { fmt.Printf("mod_int8 126%s127 = %d, wanted 126\n", `%`, got) failed = true } if got := mod_int8_126_ssa(127); got != 1 { fmt.Printf("mod_int8 127%s126 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_127_int8_ssa(-128); got != 127 { fmt.Printf("mod_int8 127%s-128 = %d, wanted 127\n", `%`, got) failed = true } if got := mod_int8_127_ssa(-128); got != -1 { fmt.Printf("mod_int8 -128%s127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_127_int8_ssa(-127); got != 0 { fmt.Printf("mod_int8 127%s-127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_127_ssa(-127); got != 0 { fmt.Printf("mod_int8 -127%s127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_127_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 127%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_127_ssa(-1); got != -1 { fmt.Printf("mod_int8 -1%s127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_127_ssa(0); got != 0 { fmt.Printf("mod_int8 0%s127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_127_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 127%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_127_ssa(1); got != 1 { fmt.Printf("mod_int8 1%s127 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_127_int8_ssa(126); got != 1 { fmt.Printf("mod_int8 127%s126 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int8_127_ssa(126); got != 126 { fmt.Printf("mod_int8 126%s127 = %d, wanted 126\n", `%`, got) failed = true } if got := mod_127_int8_ssa(127); got != 0 { fmt.Printf("mod_int8 127%s127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_127_ssa(127); got != 0 { fmt.Printf("mod_int8 127%s127 = %d, wanted 0\n", `%`, got) failed = true } if got := and_Neg128_int8_ssa(-128); got != -128 { fmt.Printf("and_int8 -128%s-128 = %d, wanted -128\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(-128); got != -128 { fmt.Printf("and_int8 -128%s-128 = %d, wanted -128\n", `&`, got) failed = true } if got := and_Neg128_int8_ssa(-127); got != -128 { fmt.Printf("and_int8 -128%s-127 = %d, wanted -128\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(-127); got != -128 { fmt.Printf("and_int8 -127%s-128 = %d, wanted -128\n", `&`, got) failed = true } if got := and_Neg128_int8_ssa(-1); got != -128 { fmt.Printf("and_int8 -128%s-1 = %d, wanted -128\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(-1); got != -128 { fmt.Printf("and_int8 -1%s-128 = %d, wanted -128\n", `&`, got) failed = true } if got := and_Neg128_int8_ssa(0); got != 0 { fmt.Printf("and_int8 -128%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(0); got != 0 { fmt.Printf("and_int8 0%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg128_int8_ssa(1); got != 0 { fmt.Printf("and_int8 -128%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(1); got != 0 { fmt.Printf("and_int8 1%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg128_int8_ssa(126); got != 0 { fmt.Printf("and_int8 -128%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(126); got != 0 { fmt.Printf("and_int8 126%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg128_int8_ssa(127); got != 0 { fmt.Printf("and_int8 -128%s127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(127); got != 0 { fmt.Printf("and_int8 127%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(-128); got != -128 { fmt.Printf("and_int8 -127%s-128 = %d, wanted -128\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(-128); got != -128 { fmt.Printf("and_int8 -128%s-127 = %d, wanted -128\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(-127); got != -127 { fmt.Printf("and_int8 -127%s-127 = %d, wanted -127\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(-127); got != -127 { fmt.Printf("and_int8 -127%s-127 = %d, wanted -127\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(-1); got != -127 { fmt.Printf("and_int8 -127%s-1 = %d, wanted -127\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(-1); got != -127 { fmt.Printf("and_int8 -1%s-127 = %d, wanted -127\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(0); got != 0 { fmt.Printf("and_int8 -127%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(0); got != 0 { fmt.Printf("and_int8 0%s-127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(1); got != 1 { fmt.Printf("and_int8 -127%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(1); got != 1 { fmt.Printf("and_int8 1%s-127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(126); got != 0 { fmt.Printf("and_int8 -127%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(126); got != 0 { fmt.Printf("and_int8 126%s-127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(127); got != 1 { fmt.Printf("and_int8 -127%s127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(127); got != 1 { fmt.Printf("and_int8 127%s-127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(-128); got != -128 { fmt.Printf("and_int8 -1%s-128 = %d, wanted -128\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(-128); got != -128 { fmt.Printf("and_int8 -128%s-1 = %d, wanted -128\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(-127); got != -127 { fmt.Printf("and_int8 -1%s-127 = %d, wanted -127\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(-127); got != -127 { fmt.Printf("and_int8 -127%s-1 = %d, wanted -127\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(-1); got != -1 { fmt.Printf("and_int8 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(-1); got != -1 { fmt.Printf("and_int8 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(0); got != 0 { fmt.Printf("and_int8 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(0); got != 0 { fmt.Printf("and_int8 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(1); got != 1 { fmt.Printf("and_int8 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(1); got != 1 { fmt.Printf("and_int8 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(126); got != 126 { fmt.Printf("and_int8 -1%s126 = %d, wanted 126\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(126); got != 126 { fmt.Printf("and_int8 126%s-1 = %d, wanted 126\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(127); got != 127 { fmt.Printf("and_int8 -1%s127 = %d, wanted 127\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(127); got != 127 { fmt.Printf("and_int8 127%s-1 = %d, wanted 127\n", `&`, got) failed = true } if got := and_0_int8_ssa(-128); got != 0 { fmt.Printf("and_int8 0%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(-128); got != 0 { fmt.Printf("and_int8 -128%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int8_ssa(-127); got != 0 { fmt.Printf("and_int8 0%s-127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(-127); got != 0 { fmt.Printf("and_int8 -127%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int8_ssa(-1); got != 0 { fmt.Printf("and_int8 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(-1); got != 0 { fmt.Printf("and_int8 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int8_ssa(0); got != 0 { fmt.Printf("and_int8 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(0); got != 0 { fmt.Printf("and_int8 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int8_ssa(1); got != 0 { fmt.Printf("and_int8 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(1); got != 0 { fmt.Printf("and_int8 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int8_ssa(126); got != 0 { fmt.Printf("and_int8 0%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(126); got != 0 { fmt.Printf("and_int8 126%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int8_ssa(127); got != 0 { fmt.Printf("and_int8 0%s127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(127); got != 0 { fmt.Printf("and_int8 127%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int8_ssa(-128); got != 0 { fmt.Printf("and_int8 1%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_1_ssa(-128); got != 0 { fmt.Printf("and_int8 -128%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int8_ssa(-127); got != 1 { fmt.Printf("and_int8 1%s-127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_1_ssa(-127); got != 1 { fmt.Printf("and_int8 -127%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int8_ssa(-1); got != 1 { fmt.Printf("and_int8 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_1_ssa(-1); got != 1 { fmt.Printf("and_int8 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int8_ssa(0); got != 0 { fmt.Printf("and_int8 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_1_ssa(0); got != 0 { fmt.Printf("and_int8 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int8_ssa(1); got != 1 { fmt.Printf("and_int8 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_1_ssa(1); got != 1 { fmt.Printf("and_int8 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int8_ssa(126); got != 0 { fmt.Printf("and_int8 1%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_1_ssa(126); got != 0 { fmt.Printf("and_int8 126%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int8_ssa(127); got != 1 { fmt.Printf("and_int8 1%s127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_1_ssa(127); got != 1 { fmt.Printf("and_int8 127%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_126_int8_ssa(-128); got != 0 { fmt.Printf("and_int8 126%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_126_ssa(-128); got != 0 { fmt.Printf("and_int8 -128%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_126_int8_ssa(-127); got != 0 { fmt.Printf("and_int8 126%s-127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_126_ssa(-127); got != 0 { fmt.Printf("and_int8 -127%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_126_int8_ssa(-1); got != 126 { fmt.Printf("and_int8 126%s-1 = %d, wanted 126\n", `&`, got) failed = true } if got := and_int8_126_ssa(-1); got != 126 { fmt.Printf("and_int8 -1%s126 = %d, wanted 126\n", `&`, got) failed = true } if got := and_126_int8_ssa(0); got != 0 { fmt.Printf("and_int8 126%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_126_ssa(0); got != 0 { fmt.Printf("and_int8 0%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_126_int8_ssa(1); got != 0 { fmt.Printf("and_int8 126%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_126_ssa(1); got != 0 { fmt.Printf("and_int8 1%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_126_int8_ssa(126); got != 126 { fmt.Printf("and_int8 126%s126 = %d, wanted 126\n", `&`, got) failed = true } if got := and_int8_126_ssa(126); got != 126 { fmt.Printf("and_int8 126%s126 = %d, wanted 126\n", `&`, got) failed = true } if got := and_126_int8_ssa(127); got != 126 { fmt.Printf("and_int8 126%s127 = %d, wanted 126\n", `&`, got) failed = true } if got := and_int8_126_ssa(127); got != 126 { fmt.Printf("and_int8 127%s126 = %d, wanted 126\n", `&`, got) failed = true } if got := and_127_int8_ssa(-128); got != 0 { fmt.Printf("and_int8 127%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_127_ssa(-128); got != 0 { fmt.Printf("and_int8 -128%s127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_127_int8_ssa(-127); got != 1 { fmt.Printf("and_int8 127%s-127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_127_ssa(-127); got != 1 { fmt.Printf("and_int8 -127%s127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_127_int8_ssa(-1); got != 127 { fmt.Printf("and_int8 127%s-1 = %d, wanted 127\n", `&`, got) failed = true } if got := and_int8_127_ssa(-1); got != 127 { fmt.Printf("and_int8 -1%s127 = %d, wanted 127\n", `&`, got) failed = true } if got := and_127_int8_ssa(0); got != 0 { fmt.Printf("and_int8 127%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_127_ssa(0); got != 0 { fmt.Printf("and_int8 0%s127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_127_int8_ssa(1); got != 1 { fmt.Printf("and_int8 127%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_127_ssa(1); got != 1 { fmt.Printf("and_int8 1%s127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_127_int8_ssa(126); got != 126 { fmt.Printf("and_int8 127%s126 = %d, wanted 126\n", `&`, got) failed = true } if got := and_int8_127_ssa(126); got != 126 { fmt.Printf("and_int8 126%s127 = %d, wanted 126\n", `&`, got) failed = true } if got := and_127_int8_ssa(127); got != 127 { fmt.Printf("and_int8 127%s127 = %d, wanted 127\n", `&`, got) failed = true } if got := and_int8_127_ssa(127); got != 127 { fmt.Printf("and_int8 127%s127 = %d, wanted 127\n", `&`, got) failed = true } if got := or_Neg128_int8_ssa(-128); got != -128 { fmt.Printf("or_int8 -128%s-128 = %d, wanted -128\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(-128); got != -128 { fmt.Printf("or_int8 -128%s-128 = %d, wanted -128\n", `|`, got) failed = true } if got := or_Neg128_int8_ssa(-127); got != -127 { fmt.Printf("or_int8 -128%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(-127); got != -127 { fmt.Printf("or_int8 -127%s-128 = %d, wanted -127\n", `|`, got) failed = true } if got := or_Neg128_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 -128%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s-128 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg128_int8_ssa(0); got != -128 { fmt.Printf("or_int8 -128%s0 = %d, wanted -128\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(0); got != -128 { fmt.Printf("or_int8 0%s-128 = %d, wanted -128\n", `|`, got) failed = true } if got := or_Neg128_int8_ssa(1); got != -127 { fmt.Printf("or_int8 -128%s1 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(1); got != -127 { fmt.Printf("or_int8 1%s-128 = %d, wanted -127\n", `|`, got) failed = true } if got := or_Neg128_int8_ssa(126); got != -2 { fmt.Printf("or_int8 -128%s126 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(126); got != -2 { fmt.Printf("or_int8 126%s-128 = %d, wanted -2\n", `|`, got) failed = true } if got := or_Neg128_int8_ssa(127); got != -1 { fmt.Printf("or_int8 -128%s127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(127); got != -1 { fmt.Printf("or_int8 127%s-128 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(-128); got != -127 { fmt.Printf("or_int8 -127%s-128 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(-128); got != -127 { fmt.Printf("or_int8 -128%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(-127); got != -127 { fmt.Printf("or_int8 -127%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(-127); got != -127 { fmt.Printf("or_int8 -127%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 -127%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s-127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(0); got != -127 { fmt.Printf("or_int8 -127%s0 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(0); got != -127 { fmt.Printf("or_int8 0%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(1); got != -127 { fmt.Printf("or_int8 -127%s1 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(1); got != -127 { fmt.Printf("or_int8 1%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(126); got != -1 { fmt.Printf("or_int8 -127%s126 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(126); got != -1 { fmt.Printf("or_int8 126%s-127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(127); got != -1 { fmt.Printf("or_int8 -127%s127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(127); got != -1 { fmt.Printf("or_int8 127%s-127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(-128); got != -1 { fmt.Printf("or_int8 -1%s-128 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(-128); got != -1 { fmt.Printf("or_int8 -128%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(-127); got != -1 { fmt.Printf("or_int8 -1%s-127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(-127); got != -1 { fmt.Printf("or_int8 -127%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(0); got != -1 { fmt.Printf("or_int8 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(0); got != -1 { fmt.Printf("or_int8 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(1); got != -1 { fmt.Printf("or_int8 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(1); got != -1 { fmt.Printf("or_int8 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(126); got != -1 { fmt.Printf("or_int8 -1%s126 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(126); got != -1 { fmt.Printf("or_int8 126%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(127); got != -1 { fmt.Printf("or_int8 -1%s127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(127); got != -1 { fmt.Printf("or_int8 127%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int8_ssa(-128); got != -128 { fmt.Printf("or_int8 0%s-128 = %d, wanted -128\n", `|`, got) failed = true } if got := or_int8_0_ssa(-128); got != -128 { fmt.Printf("or_int8 -128%s0 = %d, wanted -128\n", `|`, got) failed = true } if got := or_0_int8_ssa(-127); got != -127 { fmt.Printf("or_int8 0%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_0_ssa(-127); got != -127 { fmt.Printf("or_int8 -127%s0 = %d, wanted -127\n", `|`, got) failed = true } if got := or_0_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_0_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int8_ssa(0); got != 0 { fmt.Printf("or_int8 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_int8_0_ssa(0); got != 0 { fmt.Printf("or_int8 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_int8_ssa(1); got != 1 { fmt.Printf("or_int8 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int8_0_ssa(1); got != 1 { fmt.Printf("or_int8 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_int8_ssa(126); got != 126 { fmt.Printf("or_int8 0%s126 = %d, wanted 126\n", `|`, got) failed = true } if got := or_int8_0_ssa(126); got != 126 { fmt.Printf("or_int8 126%s0 = %d, wanted 126\n", `|`, got) failed = true } if got := or_0_int8_ssa(127); got != 127 { fmt.Printf("or_int8 0%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_0_ssa(127); got != 127 { fmt.Printf("or_int8 127%s0 = %d, wanted 127\n", `|`, got) failed = true } if got := or_1_int8_ssa(-128); got != -127 { fmt.Printf("or_int8 1%s-128 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_1_ssa(-128); got != -127 { fmt.Printf("or_int8 -128%s1 = %d, wanted -127\n", `|`, got) failed = true } if got := or_1_int8_ssa(-127); got != -127 { fmt.Printf("or_int8 1%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_1_ssa(-127); got != -127 { fmt.Printf("or_int8 -127%s1 = %d, wanted -127\n", `|`, got) failed = true } if got := or_1_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_1_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_1_int8_ssa(0); got != 1 { fmt.Printf("or_int8 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int8_1_ssa(0); got != 1 { fmt.Printf("or_int8 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int8_ssa(1); got != 1 { fmt.Printf("or_int8 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int8_1_ssa(1); got != 1 { fmt.Printf("or_int8 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int8_ssa(126); got != 127 { fmt.Printf("or_int8 1%s126 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_1_ssa(126); got != 127 { fmt.Printf("or_int8 126%s1 = %d, wanted 127\n", `|`, got) failed = true } if got := or_1_int8_ssa(127); got != 127 { fmt.Printf("or_int8 1%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_1_ssa(127); got != 127 { fmt.Printf("or_int8 127%s1 = %d, wanted 127\n", `|`, got) failed = true } if got := or_126_int8_ssa(-128); got != -2 { fmt.Printf("or_int8 126%s-128 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int8_126_ssa(-128); got != -2 { fmt.Printf("or_int8 -128%s126 = %d, wanted -2\n", `|`, got) failed = true } if got := or_126_int8_ssa(-127); got != -1 { fmt.Printf("or_int8 126%s-127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_126_ssa(-127); got != -1 { fmt.Printf("or_int8 -127%s126 = %d, wanted -1\n", `|`, got) failed = true } if got := or_126_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 126%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_126_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s126 = %d, wanted -1\n", `|`, got) failed = true } if got := or_126_int8_ssa(0); got != 126 { fmt.Printf("or_int8 126%s0 = %d, wanted 126\n", `|`, got) failed = true } if got := or_int8_126_ssa(0); got != 126 { fmt.Printf("or_int8 0%s126 = %d, wanted 126\n", `|`, got) failed = true } if got := or_126_int8_ssa(1); got != 127 { fmt.Printf("or_int8 126%s1 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_126_ssa(1); got != 127 { fmt.Printf("or_int8 1%s126 = %d, wanted 127\n", `|`, got) failed = true } if got := or_126_int8_ssa(126); got != 126 { fmt.Printf("or_int8 126%s126 = %d, wanted 126\n", `|`, got) failed = true } if got := or_int8_126_ssa(126); got != 126 { fmt.Printf("or_int8 126%s126 = %d, wanted 126\n", `|`, got) failed = true } if got := or_126_int8_ssa(127); got != 127 { fmt.Printf("or_int8 126%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_126_ssa(127); got != 127 { fmt.Printf("or_int8 127%s126 = %d, wanted 127\n", `|`, got) failed = true } if got := or_127_int8_ssa(-128); got != -1 { fmt.Printf("or_int8 127%s-128 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_127_ssa(-128); got != -1 { fmt.Printf("or_int8 -128%s127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_127_int8_ssa(-127); got != -1 { fmt.Printf("or_int8 127%s-127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_127_ssa(-127); got != -1 { fmt.Printf("or_int8 -127%s127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_127_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 127%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_127_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_127_int8_ssa(0); got != 127 { fmt.Printf("or_int8 127%s0 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_127_ssa(0); got != 127 { fmt.Printf("or_int8 0%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_127_int8_ssa(1); got != 127 { fmt.Printf("or_int8 127%s1 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_127_ssa(1); got != 127 { fmt.Printf("or_int8 1%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_127_int8_ssa(126); got != 127 { fmt.Printf("or_int8 127%s126 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_127_ssa(126); got != 127 { fmt.Printf("or_int8 126%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_127_int8_ssa(127); got != 127 { fmt.Printf("or_int8 127%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_127_ssa(127); got != 127 { fmt.Printf("or_int8 127%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := xor_Neg128_int8_ssa(-128); got != 0 { fmt.Printf("xor_int8 -128%s-128 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(-128); got != 0 { fmt.Printf("xor_int8 -128%s-128 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg128_int8_ssa(-127); got != 1 { fmt.Printf("xor_int8 -128%s-127 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(-127); got != 1 { fmt.Printf("xor_int8 -127%s-128 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg128_int8_ssa(-1); got != 127 { fmt.Printf("xor_int8 -128%s-1 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(-1); got != 127 { fmt.Printf("xor_int8 -1%s-128 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_Neg128_int8_ssa(0); got != -128 { fmt.Printf("xor_int8 -128%s0 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(0); got != -128 { fmt.Printf("xor_int8 0%s-128 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_Neg128_int8_ssa(1); got != -127 { fmt.Printf("xor_int8 -128%s1 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(1); got != -127 { fmt.Printf("xor_int8 1%s-128 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_Neg128_int8_ssa(126); got != -2 { fmt.Printf("xor_int8 -128%s126 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(126); got != -2 { fmt.Printf("xor_int8 126%s-128 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg128_int8_ssa(127); got != -1 { fmt.Printf("xor_int8 -128%s127 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(127); got != -1 { fmt.Printf("xor_int8 127%s-128 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(-128); got != 1 { fmt.Printf("xor_int8 -127%s-128 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(-128); got != 1 { fmt.Printf("xor_int8 -128%s-127 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(-127); got != 0 { fmt.Printf("xor_int8 -127%s-127 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(-127); got != 0 { fmt.Printf("xor_int8 -127%s-127 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(-1); got != 126 { fmt.Printf("xor_int8 -127%s-1 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(-1); got != 126 { fmt.Printf("xor_int8 -1%s-127 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(0); got != -127 { fmt.Printf("xor_int8 -127%s0 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(0); got != -127 { fmt.Printf("xor_int8 0%s-127 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(1); got != -128 { fmt.Printf("xor_int8 -127%s1 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(1); got != -128 { fmt.Printf("xor_int8 1%s-127 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(126); got != -1 { fmt.Printf("xor_int8 -127%s126 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(126); got != -1 { fmt.Printf("xor_int8 126%s-127 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(127); got != -2 { fmt.Printf("xor_int8 -127%s127 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(127); got != -2 { fmt.Printf("xor_int8 127%s-127 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(-128); got != 127 { fmt.Printf("xor_int8 -1%s-128 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(-128); got != 127 { fmt.Printf("xor_int8 -128%s-1 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(-127); got != 126 { fmt.Printf("xor_int8 -1%s-127 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(-127); got != 126 { fmt.Printf("xor_int8 -127%s-1 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(-1); got != 0 { fmt.Printf("xor_int8 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(-1); got != 0 { fmt.Printf("xor_int8 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(0); got != -1 { fmt.Printf("xor_int8 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(0); got != -1 { fmt.Printf("xor_int8 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(1); got != -2 { fmt.Printf("xor_int8 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(1); got != -2 { fmt.Printf("xor_int8 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(126); got != -127 { fmt.Printf("xor_int8 -1%s126 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(126); got != -127 { fmt.Printf("xor_int8 126%s-1 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(127); got != -128 { fmt.Printf("xor_int8 -1%s127 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(127); got != -128 { fmt.Printf("xor_int8 127%s-1 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_0_int8_ssa(-128); got != -128 { fmt.Printf("xor_int8 0%s-128 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_int8_0_ssa(-128); got != -128 { fmt.Printf("xor_int8 -128%s0 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_0_int8_ssa(-127); got != -127 { fmt.Printf("xor_int8 0%s-127 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_int8_0_ssa(-127); got != -127 { fmt.Printf("xor_int8 -127%s0 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_0_int8_ssa(-1); got != -1 { fmt.Printf("xor_int8 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int8_0_ssa(-1); got != -1 { fmt.Printf("xor_int8 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_0_int8_ssa(0); got != 0 { fmt.Printf("xor_int8 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_0_ssa(0); got != 0 { fmt.Printf("xor_int8 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_int8_ssa(1); got != 1 { fmt.Printf("xor_int8 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int8_0_ssa(1); got != 1 { fmt.Printf("xor_int8 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_int8_ssa(126); got != 126 { fmt.Printf("xor_int8 0%s126 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_int8_0_ssa(126); got != 126 { fmt.Printf("xor_int8 126%s0 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_0_int8_ssa(127); got != 127 { fmt.Printf("xor_int8 0%s127 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_int8_0_ssa(127); got != 127 { fmt.Printf("xor_int8 127%s0 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_1_int8_ssa(-128); got != -127 { fmt.Printf("xor_int8 1%s-128 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_int8_1_ssa(-128); got != -127 { fmt.Printf("xor_int8 -128%s1 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_1_int8_ssa(-127); got != -128 { fmt.Printf("xor_int8 1%s-127 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_int8_1_ssa(-127); got != -128 { fmt.Printf("xor_int8 -127%s1 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_1_int8_ssa(-1); got != -2 { fmt.Printf("xor_int8 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int8_1_ssa(-1); got != -2 { fmt.Printf("xor_int8 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_1_int8_ssa(0); got != 1 { fmt.Printf("xor_int8 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int8_1_ssa(0); got != 1 { fmt.Printf("xor_int8 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_int8_ssa(1); got != 0 { fmt.Printf("xor_int8 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_1_ssa(1); got != 0 { fmt.Printf("xor_int8 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_int8_ssa(126); got != 127 { fmt.Printf("xor_int8 1%s126 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_int8_1_ssa(126); got != 127 { fmt.Printf("xor_int8 126%s1 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_1_int8_ssa(127); got != 126 { fmt.Printf("xor_int8 1%s127 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_int8_1_ssa(127); got != 126 { fmt.Printf("xor_int8 127%s1 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_126_int8_ssa(-128); got != -2 { fmt.Printf("xor_int8 126%s-128 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int8_126_ssa(-128); got != -2 { fmt.Printf("xor_int8 -128%s126 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_126_int8_ssa(-127); got != -1 { fmt.Printf("xor_int8 126%s-127 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int8_126_ssa(-127); got != -1 { fmt.Printf("xor_int8 -127%s126 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_126_int8_ssa(-1); got != -127 { fmt.Printf("xor_int8 126%s-1 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_int8_126_ssa(-1); got != -127 { fmt.Printf("xor_int8 -1%s126 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_126_int8_ssa(0); got != 126 { fmt.Printf("xor_int8 126%s0 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_int8_126_ssa(0); got != 126 { fmt.Printf("xor_int8 0%s126 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_126_int8_ssa(1); got != 127 { fmt.Printf("xor_int8 126%s1 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_int8_126_ssa(1); got != 127 { fmt.Printf("xor_int8 1%s126 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_126_int8_ssa(126); got != 0 { fmt.Printf("xor_int8 126%s126 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_126_ssa(126); got != 0 { fmt.Printf("xor_int8 126%s126 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_126_int8_ssa(127); got != 1 { fmt.Printf("xor_int8 126%s127 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int8_126_ssa(127); got != 1 { fmt.Printf("xor_int8 127%s126 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_127_int8_ssa(-128); got != -1 { fmt.Printf("xor_int8 127%s-128 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int8_127_ssa(-128); got != -1 { fmt.Printf("xor_int8 -128%s127 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_127_int8_ssa(-127); got != -2 { fmt.Printf("xor_int8 127%s-127 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int8_127_ssa(-127); got != -2 { fmt.Printf("xor_int8 -127%s127 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_127_int8_ssa(-1); got != -128 { fmt.Printf("xor_int8 127%s-1 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_int8_127_ssa(-1); got != -128 { fmt.Printf("xor_int8 -1%s127 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_127_int8_ssa(0); got != 127 { fmt.Printf("xor_int8 127%s0 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_int8_127_ssa(0); got != 127 { fmt.Printf("xor_int8 0%s127 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_127_int8_ssa(1); got != 126 { fmt.Printf("xor_int8 127%s1 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_int8_127_ssa(1); got != 126 { fmt.Printf("xor_int8 1%s127 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_127_int8_ssa(126); got != 1 { fmt.Printf("xor_int8 127%s126 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int8_127_ssa(126); got != 1 { fmt.Printf("xor_int8 126%s127 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_127_int8_ssa(127); got != 0 { fmt.Printf("xor_int8 127%s127 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_127_ssa(127); got != 0 { fmt.Printf("xor_int8 127%s127 = %d, wanted 0\n", `^`, got) failed = true } if failed { panic("tests failed") } } -- y -- // run // Code generated by gen/arithConstGen.go. DO NOT EDIT. package main import "fmt" import "os" //go:noinline func add_uint64_0(a uint64) uint64 { return a + 0 } //go:noinline func add_0_uint64(a uint64) uint64 { return 0 + a } //go:noinline func add_uint64_1(a uint64) uint64 { return a + 1 } //go:noinline func add_1_uint64(a uint64) uint64 { return 1 + a } //go:noinline func add_uint64_4294967296(a uint64) uint64 { return a + 4294967296 } //go:noinline func add_4294967296_uint64(a uint64) uint64 { return 4294967296 + a } //go:noinline func add_uint64_9223372036854775808(a uint64) uint64 { return a + 9223372036854775808 } //go:noinline func add_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 + a } //go:noinline func add_uint64_18446744073709551615(a uint64) uint64 { return a + 18446744073709551615 } //go:noinline func add_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 + a } //go:noinline func sub_uint64_0(a uint64) uint64 { return a - 0 } //go:noinline func sub_0_uint64(a uint64) uint64 { return 0 - a } //go:noinline func sub_uint64_1(a uint64) uint64 { return a - 1 } //go:noinline func sub_1_uint64(a uint64) uint64 { return 1 - a } //go:noinline func sub_uint64_4294967296(a uint64) uint64 { return a - 4294967296 } //go:noinline func sub_4294967296_uint64(a uint64) uint64 { return 4294967296 - a } //go:noinline func sub_uint64_9223372036854775808(a uint64) uint64 { return a - 9223372036854775808 } //go:noinline func sub_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 - a } //go:noinline func sub_uint64_18446744073709551615(a uint64) uint64 { return a - 18446744073709551615 } //go:noinline func sub_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 - a } //go:noinline func div_0_uint64(a uint64) uint64 { return 0 / a } //go:noinline func div_uint64_1(a uint64) uint64 { return a / 1 } //go:noinline func div_1_uint64(a uint64) uint64 { return 1 / a } //go:noinline func div_uint64_4294967296(a uint64) uint64 { return a / 4294967296 } //go:noinline func div_4294967296_uint64(a uint64) uint64 { return 4294967296 / a } //go:noinline func div_uint64_9223372036854775808(a uint64) uint64 { return a / 9223372036854775808 } //go:noinline func div_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 / a } //go:noinline func div_uint64_18446744073709551615(a uint64) uint64 { return a / 18446744073709551615 } //go:noinline func div_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 / a } //go:noinline func mul_uint64_0(a uint64) uint64 { return a * 0 } //go:noinline func mul_0_uint64(a uint64) uint64 { return 0 * a } //go:noinline func mul_uint64_1(a uint64) uint64 { return a * 1 } //go:noinline func mul_1_uint64(a uint64) uint64 { return 1 * a } //go:noinline func mul_uint64_4294967296(a uint64) uint64 { return a * 4294967296 } //go:noinline func mul_4294967296_uint64(a uint64) uint64 { return 4294967296 * a } //go:noinline func mul_uint64_9223372036854775808(a uint64) uint64 { return a * 9223372036854775808 } //go:noinline func mul_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 * a } //go:noinline func mul_uint64_18446744073709551615(a uint64) uint64 { return a * 18446744073709551615 } //go:noinline func mul_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 * a } //go:noinline func lsh_uint64_0(a uint64) uint64 { return a << 0 } //go:noinline func lsh_0_uint64(a uint64) uint64 { return 0 << a } //go:noinline func lsh_uint64_1(a uint64) uint64 { return a << 1 } //go:noinline func lsh_1_uint64(a uint64) uint64 { return 1 << a } //go:noinline func lsh_uint64_4294967296(a uint64) uint64 { return a << uint64(4294967296) } //go:noinline func lsh_4294967296_uint64(a uint64) uint64 { return 4294967296 << a } //go:noinline func lsh_uint64_9223372036854775808(a uint64) uint64 { return a << uint64(9223372036854775808) } //go:noinline func lsh_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 << a } //go:noinline func lsh_uint64_18446744073709551615(a uint64) uint64 { return a << uint64(18446744073709551615) } //go:noinline func lsh_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 << a } //go:noinline func rsh_uint64_0(a uint64) uint64 { return a >> 0 } //go:noinline func rsh_0_uint64(a uint64) uint64 { return 0 >> a } //go:noinline func rsh_uint64_1(a uint64) uint64 { return a >> 1 } //go:noinline func rsh_1_uint64(a uint64) uint64 { return 1 >> a } //go:noinline func rsh_uint64_4294967296(a uint64) uint64 { return a >> uint64(4294967296) } //go:noinline func rsh_4294967296_uint64(a uint64) uint64 { return 4294967296 >> a } //go:noinline func rsh_uint64_9223372036854775808(a uint64) uint64 { return a >> uint64(9223372036854775808) } //go:noinline func rsh_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 >> a } //go:noinline func rsh_uint64_18446744073709551615(a uint64) uint64 { return a >> uint64(18446744073709551615) } //go:noinline func rsh_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 >> a } //go:noinline func mod_0_uint64(a uint64) uint64 { return 0 % a } //go:noinline func mod_uint64_1(a uint64) uint64 { return a % 1 } //go:noinline func mod_1_uint64(a uint64) uint64 { return 1 % a } //go:noinline func mod_uint64_4294967296(a uint64) uint64 { return a % 4294967296 } //go:noinline func mod_4294967296_uint64(a uint64) uint64 { return 4294967296 % a } //go:noinline func mod_uint64_9223372036854775808(a uint64) uint64 { return a % 9223372036854775808 } //go:noinline func mod_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 % a } //go:noinline func mod_uint64_18446744073709551615(a uint64) uint64 { return a % 18446744073709551615 } //go:noinline func mod_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 % a } //go:noinline func and_uint64_0(a uint64) uint64 { return a & 0 } //go:noinline func and_0_uint64(a uint64) uint64 { return 0 & a } //go:noinline func and_uint64_1(a uint64) uint64 { return a & 1 } //go:noinline func and_1_uint64(a uint64) uint64 { return 1 & a } //go:noinline func and_uint64_4294967296(a uint64) uint64 { return a & 4294967296 } //go:noinline func and_4294967296_uint64(a uint64) uint64 { return 4294967296 & a } //go:noinline func and_uint64_9223372036854775808(a uint64) uint64 { return a & 9223372036854775808 } //go:noinline func and_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 & a } //go:noinline func and_uint64_18446744073709551615(a uint64) uint64 { return a & 18446744073709551615 } //go:noinline func and_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 & a } //go:noinline func or_uint64_0(a uint64) uint64 { return a | 0 } //go:noinline func or_0_uint64(a uint64) uint64 { return 0 | a } //go:noinline func or_uint64_1(a uint64) uint64 { return a | 1 } //go:noinline func or_1_uint64(a uint64) uint64 { return 1 | a } //go:noinline func or_uint64_4294967296(a uint64) uint64 { return a | 4294967296 } //go:noinline func or_4294967296_uint64(a uint64) uint64 { return 4294967296 | a } //go:noinline func or_uint64_9223372036854775808(a uint64) uint64 { return a | 9223372036854775808 } //go:noinline func or_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 | a } //go:noinline func or_uint64_18446744073709551615(a uint64) uint64 { return a | 18446744073709551615 } //go:noinline func or_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 | a } //go:noinline func xor_uint64_0(a uint64) uint64 { return a ^ 0 } //go:noinline func xor_0_uint64(a uint64) uint64 { return 0 ^ a } //go:noinline func xor_uint64_1(a uint64) uint64 { return a ^ 1 } //go:noinline func xor_1_uint64(a uint64) uint64 { return 1 ^ a } //go:noinline func xor_uint64_4294967296(a uint64) uint64 { return a ^ 4294967296 } //go:noinline func xor_4294967296_uint64(a uint64) uint64 { return 4294967296 ^ a } //go:noinline func xor_uint64_9223372036854775808(a uint64) uint64 { return a ^ 9223372036854775808 } //go:noinline func xor_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 ^ a } //go:noinline func xor_uint64_18446744073709551615(a uint64) uint64 { return a ^ 18446744073709551615 } //go:noinline func xor_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 ^ a } //go:noinline func add_int64_Neg9223372036854775808(a int64) int64 { return a + -9223372036854775808 } //go:noinline func add_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 + a } //go:noinline func add_int64_Neg9223372036854775807(a int64) int64 { return a + -9223372036854775807 } //go:noinline func add_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 + a } //go:noinline func add_int64_Neg4294967296(a int64) int64 { return a + -4294967296 } //go:noinline func add_Neg4294967296_int64(a int64) int64 { return -4294967296 + a } //go:noinline func add_int64_Neg1(a int64) int64 { return a + -1 } //go:noinline func add_Neg1_int64(a int64) int64 { return -1 + a } //go:noinline func add_int64_0(a int64) int64 { return a + 0 } //go:noinline func add_0_int64(a int64) int64 { return 0 + a } //go:noinline func add_int64_1(a int64) int64 { return a + 1 } //go:noinline func add_1_int64(a int64) int64 { return 1 + a } //go:noinline func add_int64_4294967296(a int64) int64 { return a + 4294967296 } //go:noinline func add_4294967296_int64(a int64) int64 { return 4294967296 + a } //go:noinline func add_int64_9223372036854775806(a int64) int64 { return a + 9223372036854775806 } //go:noinline func add_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 + a } //go:noinline func add_int64_9223372036854775807(a int64) int64 { return a + 9223372036854775807 } //go:noinline func add_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 + a } //go:noinline func sub_int64_Neg9223372036854775808(a int64) int64 { return a - -9223372036854775808 } //go:noinline func sub_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 - a } //go:noinline func sub_int64_Neg9223372036854775807(a int64) int64 { return a - -9223372036854775807 } //go:noinline func sub_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 - a } //go:noinline func sub_int64_Neg4294967296(a int64) int64 { return a - -4294967296 } //go:noinline func sub_Neg4294967296_int64(a int64) int64 { return -4294967296 - a } //go:noinline func sub_int64_Neg1(a int64) int64 { return a - -1 } //go:noinline func sub_Neg1_int64(a int64) int64 { return -1 - a } //go:noinline func sub_int64_0(a int64) int64 { return a - 0 } //go:noinline func sub_0_int64(a int64) int64 { return 0 - a } //go:noinline func sub_int64_1(a int64) int64 { return a - 1 } //go:noinline func sub_1_int64(a int64) int64 { return 1 - a } //go:noinline func sub_int64_4294967296(a int64) int64 { return a - 4294967296 } //go:noinline func sub_4294967296_int64(a int64) int64 { return 4294967296 - a } //go:noinline func sub_int64_9223372036854775806(a int64) int64 { return a - 9223372036854775806 } //go:noinline func sub_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 - a } //go:noinline func sub_int64_9223372036854775807(a int64) int64 { return a - 9223372036854775807 } //go:noinline func sub_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 - a } //go:noinline func div_int64_Neg9223372036854775808(a int64) int64 { return a / -9223372036854775808 } //go:noinline func div_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 / a } //go:noinline func div_int64_Neg9223372036854775807(a int64) int64 { return a / -9223372036854775807 } //go:noinline func div_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 / a } //go:noinline func div_int64_Neg4294967296(a int64) int64 { return a / -4294967296 } //go:noinline func div_Neg4294967296_int64(a int64) int64 { return -4294967296 / a } //go:noinline func div_int64_Neg1(a int64) int64 { return a / -1 } //go:noinline func div_Neg1_int64(a int64) int64 { return -1 / a } //go:noinline func div_0_int64(a int64) int64 { return 0 / a } //go:noinline func div_int64_1(a int64) int64 { return a / 1 } //go:noinline func div_1_int64(a int64) int64 { return 1 / a } //go:noinline func div_int64_4294967296(a int64) int64 { return a / 4294967296 } //go:noinline func div_4294967296_int64(a int64) int64 { return 4294967296 / a } //go:noinline func div_int64_9223372036854775806(a int64) int64 { return a / 9223372036854775806 } //go:noinline func div_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 / a } //go:noinline func div_int64_9223372036854775807(a int64) int64 { return a / 9223372036854775807 } //go:noinline func div_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 / a } //go:noinline func mul_int64_Neg9223372036854775808(a int64) int64 { return a * -9223372036854775808 } //go:noinline func mul_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 * a } //go:noinline func mul_int64_Neg9223372036854775807(a int64) int64 { return a * -9223372036854775807 } //go:noinline func mul_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 * a } //go:noinline func mul_int64_Neg4294967296(a int64) int64 { return a * -4294967296 } //go:noinline func mul_Neg4294967296_int64(a int64) int64 { return -4294967296 * a } //go:noinline func mul_int64_Neg1(a int64) int64 { return a * -1 } //go:noinline func mul_Neg1_int64(a int64) int64 { return -1 * a } //go:noinline func mul_int64_0(a int64) int64 { return a * 0 } //go:noinline func mul_0_int64(a int64) int64 { return 0 * a } //go:noinline func mul_int64_1(a int64) int64 { return a * 1 } //go:noinline func mul_1_int64(a int64) int64 { return 1 * a } //go:noinline func mul_int64_4294967296(a int64) int64 { return a * 4294967296 } //go:noinline func mul_4294967296_int64(a int64) int64 { return 4294967296 * a } //go:noinline func mul_int64_9223372036854775806(a int64) int64 { return a * 9223372036854775806 } //go:noinline func mul_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 * a } //go:noinline func mul_int64_9223372036854775807(a int64) int64 { return a * 9223372036854775807 } //go:noinline func mul_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 * a } //go:noinline func mod_int64_Neg9223372036854775808(a int64) int64 { return a % -9223372036854775808 } //go:noinline func mod_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 % a } //go:noinline func mod_int64_Neg9223372036854775807(a int64) int64 { return a % -9223372036854775807 } //go:noinline func mod_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 % a } //go:noinline func mod_int64_Neg4294967296(a int64) int64 { return a % -4294967296 } //go:noinline func mod_Neg4294967296_int64(a int64) int64 { return -4294967296 % a } //go:noinline func mod_int64_Neg1(a int64) int64 { return a % -1 } //go:noinline func mod_Neg1_int64(a int64) int64 { return -1 % a } //go:noinline func mod_0_int64(a int64) int64 { return 0 % a } //go:noinline func mod_int64_1(a int64) int64 { return a % 1 } //go:noinline func mod_1_int64(a int64) int64 { return 1 % a } //go:noinline func mod_int64_4294967296(a int64) int64 { return a % 4294967296 } //go:noinline func mod_4294967296_int64(a int64) int64 { return 4294967296 % a } //go:noinline func mod_int64_9223372036854775806(a int64) int64 { return a % 9223372036854775806 } //go:noinline func mod_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 % a } //go:noinline func mod_int64_9223372036854775807(a int64) int64 { return a % 9223372036854775807 } //go:noinline func mod_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 % a } //go:noinline func and_int64_Neg9223372036854775808(a int64) int64 { return a & -9223372036854775808 } //go:noinline func and_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 & a } //go:noinline func and_int64_Neg9223372036854775807(a int64) int64 { return a & -9223372036854775807 } //go:noinline func and_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 & a } //go:noinline func and_int64_Neg4294967296(a int64) int64 { return a & -4294967296 } //go:noinline func and_Neg4294967296_int64(a int64) int64 { return -4294967296 & a } //go:noinline func and_int64_Neg1(a int64) int64 { return a & -1 } //go:noinline func and_Neg1_int64(a int64) int64 { return -1 & a } //go:noinline func and_int64_0(a int64) int64 { return a & 0 } //go:noinline func and_0_int64(a int64) int64 { return 0 & a } //go:noinline func and_int64_1(a int64) int64 { return a & 1 } //go:noinline func and_1_int64(a int64) int64 { return 1 & a } //go:noinline func and_int64_4294967296(a int64) int64 { return a & 4294967296 } //go:noinline func and_4294967296_int64(a int64) int64 { return 4294967296 & a } //go:noinline func and_int64_9223372036854775806(a int64) int64 { return a & 9223372036854775806 } //go:noinline func and_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 & a } //go:noinline func and_int64_9223372036854775807(a int64) int64 { return a & 9223372036854775807 } //go:noinline func and_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 & a } //go:noinline func or_int64_Neg9223372036854775808(a int64) int64 { return a | -9223372036854775808 } //go:noinline func or_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 | a } //go:noinline func or_int64_Neg9223372036854775807(a int64) int64 { return a | -9223372036854775807 } //go:noinline func or_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 | a } //go:noinline func or_int64_Neg4294967296(a int64) int64 { return a | -4294967296 } //go:noinline func or_Neg4294967296_int64(a int64) int64 { return -4294967296 | a } //go:noinline func or_int64_Neg1(a int64) int64 { return a | -1 } //go:noinline func or_Neg1_int64(a int64) int64 { return -1 | a } //go:noinline func or_int64_0(a int64) int64 { return a | 0 } //go:noinline func or_0_int64(a int64) int64 { return 0 | a } //go:noinline func or_int64_1(a int64) int64 { return a | 1 } //go:noinline func or_1_int64(a int64) int64 { return 1 | a } //go:noinline func or_int64_4294967296(a int64) int64 { return a | 4294967296 } //go:noinline func or_4294967296_int64(a int64) int64 { return 4294967296 | a } //go:noinline func or_int64_9223372036854775806(a int64) int64 { return a | 9223372036854775806 } //go:noinline func or_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 | a } //go:noinline func or_int64_9223372036854775807(a int64) int64 { return a | 9223372036854775807 } //go:noinline func or_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 | a } //go:noinline func xor_int64_Neg9223372036854775808(a int64) int64 { return a ^ -9223372036854775808 } //go:noinline func xor_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 ^ a } //go:noinline func xor_int64_Neg9223372036854775807(a int64) int64 { return a ^ -9223372036854775807 } //go:noinline func xor_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 ^ a } //go:noinline func xor_int64_Neg4294967296(a int64) int64 { return a ^ -4294967296 } //go:noinline func xor_Neg4294967296_int64(a int64) int64 { return -4294967296 ^ a } //go:noinline func xor_int64_Neg1(a int64) int64 { return a ^ -1 } //go:noinline func xor_Neg1_int64(a int64) int64 { return -1 ^ a } //go:noinline func xor_int64_0(a int64) int64 { return a ^ 0 } //go:noinline func xor_0_int64(a int64) int64 { return 0 ^ a } //go:noinline func xor_int64_1(a int64) int64 { return a ^ 1 } //go:noinline func xor_1_int64(a int64) int64 { return 1 ^ a } //go:noinline func xor_int64_4294967296(a int64) int64 { return a ^ 4294967296 } //go:noinline func xor_4294967296_int64(a int64) int64 { return 4294967296 ^ a } //go:noinline func xor_int64_9223372036854775806(a int64) int64 { return a ^ 9223372036854775806 } //go:noinline func xor_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 ^ a } //go:noinline func xor_int64_9223372036854775807(a int64) int64 { return a ^ 9223372036854775807 } //go:noinline func xor_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 ^ a } //go:noinline func add_uint32_0(a uint32) uint32 { return a + 0 } //go:noinline func add_0_uint32(a uint32) uint32 { return 0 + a } //go:noinline func add_uint32_1(a uint32) uint32 { return a + 1 } //go:noinline func add_1_uint32(a uint32) uint32 { return 1 + a } //go:noinline func add_uint32_4294967295(a uint32) uint32 { return a + 4294967295 } //go:noinline func add_4294967295_uint32(a uint32) uint32 { return 4294967295 + a } //go:noinline func sub_uint32_0(a uint32) uint32 { return a - 0 } //go:noinline func sub_0_uint32(a uint32) uint32 { return 0 - a } //go:noinline func sub_uint32_1(a uint32) uint32 { return a - 1 } //go:noinline func sub_1_uint32(a uint32) uint32 { return 1 - a } //go:noinline func sub_uint32_4294967295(a uint32) uint32 { return a - 4294967295 } //go:noinline func sub_4294967295_uint32(a uint32) uint32 { return 4294967295 - a } //go:noinline func div_0_uint32(a uint32) uint32 { return 0 / a } //go:noinline func div_uint32_1(a uint32) uint32 { return a / 1 } //go:noinline func div_1_uint32(a uint32) uint32 { return 1 / a } //go:noinline func div_uint32_4294967295(a uint32) uint32 { return a / 4294967295 } //go:noinline func div_4294967295_uint32(a uint32) uint32 { return 4294967295 / a } //go:noinline func mul_uint32_0(a uint32) uint32 { return a * 0 } //go:noinline func mul_0_uint32(a uint32) uint32 { return 0 * a } //go:noinline func mul_uint32_1(a uint32) uint32 { return a * 1 } //go:noinline func mul_1_uint32(a uint32) uint32 { return 1 * a } //go:noinline func mul_uint32_4294967295(a uint32) uint32 { return a * 4294967295 } //go:noinline func mul_4294967295_uint32(a uint32) uint32 { return 4294967295 * a } //go:noinline func lsh_uint32_0(a uint32) uint32 { return a << 0 } //go:noinline func lsh_0_uint32(a uint32) uint32 { return 0 << a } //go:noinline func lsh_uint32_1(a uint32) uint32 { return a << 1 } //go:noinline func lsh_1_uint32(a uint32) uint32 { return 1 << a } //go:noinline func lsh_uint32_4294967295(a uint32) uint32 { return a << 4294967295 } //go:noinline func lsh_4294967295_uint32(a uint32) uint32 { return 4294967295 << a } //go:noinline func rsh_uint32_0(a uint32) uint32 { return a >> 0 } //go:noinline func rsh_0_uint32(a uint32) uint32 { return 0 >> a } //go:noinline func rsh_uint32_1(a uint32) uint32 { return a >> 1 } //go:noinline func rsh_1_uint32(a uint32) uint32 { return 1 >> a } //go:noinline func rsh_uint32_4294967295(a uint32) uint32 { return a >> 4294967295 } //go:noinline func rsh_4294967295_uint32(a uint32) uint32 { return 4294967295 >> a } //go:noinline func mod_0_uint32(a uint32) uint32 { return 0 % a } //go:noinline func mod_uint32_1(a uint32) uint32 { return a % 1 } //go:noinline func mod_1_uint32(a uint32) uint32 { return 1 % a } //go:noinline func mod_uint32_4294967295(a uint32) uint32 { return a % 4294967295 } //go:noinline func mod_4294967295_uint32(a uint32) uint32 { return 4294967295 % a } //go:noinline func and_uint32_0(a uint32) uint32 { return a & 0 } //go:noinline func and_0_uint32(a uint32) uint32 { return 0 & a } //go:noinline func and_uint32_1(a uint32) uint32 { return a & 1 } //go:noinline func and_1_uint32(a uint32) uint32 { return 1 & a } //go:noinline func and_uint32_4294967295(a uint32) uint32 { return a & 4294967295 } //go:noinline func and_4294967295_uint32(a uint32) uint32 { return 4294967295 & a } //go:noinline func or_uint32_0(a uint32) uint32 { return a | 0 } //go:noinline func or_0_uint32(a uint32) uint32 { return 0 | a } //go:noinline func or_uint32_1(a uint32) uint32 { return a | 1 } //go:noinline func or_1_uint32(a uint32) uint32 { return 1 | a } //go:noinline func or_uint32_4294967295(a uint32) uint32 { return a | 4294967295 } //go:noinline func or_4294967295_uint32(a uint32) uint32 { return 4294967295 | a } //go:noinline func xor_uint32_0(a uint32) uint32 { return a ^ 0 } //go:noinline func xor_0_uint32(a uint32) uint32 { return 0 ^ a } //go:noinline func xor_uint32_1(a uint32) uint32 { return a ^ 1 } //go:noinline func xor_1_uint32(a uint32) uint32 { return 1 ^ a } //go:noinline func xor_uint32_4294967295(a uint32) uint32 { return a ^ 4294967295 } //go:noinline func xor_4294967295_uint32(a uint32) uint32 { return 4294967295 ^ a } //go:noinline func add_int32_Neg2147483648(a int32) int32 { return a + -2147483648 } //go:noinline func add_Neg2147483648_int32(a int32) int32 { return -2147483648 + a } //go:noinline func add_int32_Neg2147483647(a int32) int32 { return a + -2147483647 } //go:noinline func add_Neg2147483647_int32(a int32) int32 { return -2147483647 + a } //go:noinline func add_int32_Neg1(a int32) int32 { return a + -1 } //go:noinline func add_Neg1_int32(a int32) int32 { return -1 + a } //go:noinline func add_int32_0(a int32) int32 { return a + 0 } //go:noinline func add_0_int32(a int32) int32 { return 0 + a } //go:noinline func add_int32_1(a int32) int32 { return a + 1 } //go:noinline func add_1_int32(a int32) int32 { return 1 + a } //go:noinline func add_int32_2147483647(a int32) int32 { return a + 2147483647 } //go:noinline func add_2147483647_int32(a int32) int32 { return 2147483647 + a } //go:noinline func sub_int32_Neg2147483648(a int32) int32 { return a - -2147483648 } //go:noinline func sub_Neg2147483648_int32(a int32) int32 { return -2147483648 - a } //go:noinline func sub_int32_Neg2147483647(a int32) int32 { return a - -2147483647 } //go:noinline func sub_Neg2147483647_int32(a int32) int32 { return -2147483647 - a } //go:noinline func sub_int32_Neg1(a int32) int32 { return a - -1 } //go:noinline func sub_Neg1_int32(a int32) int32 { return -1 - a } //go:noinline func sub_int32_0(a int32) int32 { return a - 0 } //go:noinline func sub_0_int32(a int32) int32 { return 0 - a } //go:noinline func sub_int32_1(a int32) int32 { return a - 1 } //go:noinline func sub_1_int32(a int32) int32 { return 1 - a } //go:noinline func sub_int32_2147483647(a int32) int32 { return a - 2147483647 } //go:noinline func sub_2147483647_int32(a int32) int32 { return 2147483647 - a } //go:noinline func div_int32_Neg2147483648(a int32) int32 { return a / -2147483648 } //go:noinline func div_Neg2147483648_int32(a int32) int32 { return -2147483648 / a } //go:noinline func div_int32_Neg2147483647(a int32) int32 { return a / -2147483647 } //go:noinline func div_Neg2147483647_int32(a int32) int32 { return -2147483647 / a } //go:noinline func div_int32_Neg1(a int32) int32 { return a / -1 } //go:noinline func div_Neg1_int32(a int32) int32 { return -1 / a } //go:noinline func div_0_int32(a int32) int32 { return 0 / a } //go:noinline func div_int32_1(a int32) int32 { return a / 1 } //go:noinline func div_1_int32(a int32) int32 { return 1 / a } //go:noinline func div_int32_2147483647(a int32) int32 { return a / 2147483647 } //go:noinline func div_2147483647_int32(a int32) int32 { return 2147483647 / a } //go:noinline func mul_int32_Neg2147483648(a int32) int32 { return a * -2147483648 } //go:noinline func mul_Neg2147483648_int32(a int32) int32 { return -2147483648 * a } //go:noinline func mul_int32_Neg2147483647(a int32) int32 { return a * -2147483647 } //go:noinline func mul_Neg2147483647_int32(a int32) int32 { return -2147483647 * a } //go:noinline func mul_int32_Neg1(a int32) int32 { return a * -1 } //go:noinline func mul_Neg1_int32(a int32) int32 { return -1 * a } //go:noinline func mul_int32_0(a int32) int32 { return a * 0 } //go:noinline func mul_0_int32(a int32) int32 { return 0 * a } //go:noinline func mul_int32_1(a int32) int32 { return a * 1 } //go:noinline func mul_1_int32(a int32) int32 { return 1 * a } //go:noinline func mul_int32_2147483647(a int32) int32 { return a * 2147483647 } //go:noinline func mul_2147483647_int32(a int32) int32 { return 2147483647 * a } //go:noinline func mod_int32_Neg2147483648(a int32) int32 { return a % -2147483648 } //go:noinline func mod_Neg2147483648_int32(a int32) int32 { return -2147483648 % a } //go:noinline func mod_int32_Neg2147483647(a int32) int32 { return a % -2147483647 } //go:noinline func mod_Neg2147483647_int32(a int32) int32 { return -2147483647 % a } //go:noinline func mod_int32_Neg1(a int32) int32 { return a % -1 } //go:noinline func mod_Neg1_int32(a int32) int32 { return -1 % a } //go:noinline func mod_0_int32(a int32) int32 { return 0 % a } //go:noinline func mod_int32_1(a int32) int32 { return a % 1 } //go:noinline func mod_1_int32(a int32) int32 { return 1 % a } //go:noinline func mod_int32_2147483647(a int32) int32 { return a % 2147483647 } //go:noinline func mod_2147483647_int32(a int32) int32 { return 2147483647 % a } //go:noinline func and_int32_Neg2147483648(a int32) int32 { return a & -2147483648 } //go:noinline func and_Neg2147483648_int32(a int32) int32 { return -2147483648 & a } //go:noinline func and_int32_Neg2147483647(a int32) int32 { return a & -2147483647 } //go:noinline func and_Neg2147483647_int32(a int32) int32 { return -2147483647 & a } //go:noinline func and_int32_Neg1(a int32) int32 { return a & -1 } //go:noinline func and_Neg1_int32(a int32) int32 { return -1 & a } //go:noinline func and_int32_0(a int32) int32 { return a & 0 } //go:noinline func and_0_int32(a int32) int32 { return 0 & a } //go:noinline func and_int32_1(a int32) int32 { return a & 1 } //go:noinline func and_1_int32(a int32) int32 { return 1 & a } //go:noinline func and_int32_2147483647(a int32) int32 { return a & 2147483647 } //go:noinline func and_2147483647_int32(a int32) int32 { return 2147483647 & a } //go:noinline func or_int32_Neg2147483648(a int32) int32 { return a | -2147483648 } //go:noinline func or_Neg2147483648_int32(a int32) int32 { return -2147483648 | a } //go:noinline func or_int32_Neg2147483647(a int32) int32 { return a | -2147483647 } //go:noinline func or_Neg2147483647_int32(a int32) int32 { return -2147483647 | a } //go:noinline func or_int32_Neg1(a int32) int32 { return a | -1 } //go:noinline func or_Neg1_int32(a int32) int32 { return -1 | a } //go:noinline func or_int32_0(a int32) int32 { return a | 0 } //go:noinline func or_0_int32(a int32) int32 { return 0 | a } //go:noinline func or_int32_1(a int32) int32 { return a | 1 } //go:noinline func or_1_int32(a int32) int32 { return 1 | a } //go:noinline func or_int32_2147483647(a int32) int32 { return a | 2147483647 } //go:noinline func or_2147483647_int32(a int32) int32 { return 2147483647 | a } //go:noinline func xor_int32_Neg2147483648(a int32) int32 { return a ^ -2147483648 } //go:noinline func xor_Neg2147483648_int32(a int32) int32 { return -2147483648 ^ a } //go:noinline func xor_int32_Neg2147483647(a int32) int32 { return a ^ -2147483647 } //go:noinline func xor_Neg2147483647_int32(a int32) int32 { return -2147483647 ^ a } //go:noinline func xor_int32_Neg1(a int32) int32 { return a ^ -1 } //go:noinline func xor_Neg1_int32(a int32) int32 { return -1 ^ a } //go:noinline func xor_int32_0(a int32) int32 { return a ^ 0 } //go:noinline func xor_0_int32(a int32) int32 { return 0 ^ a } //go:noinline func xor_int32_1(a int32) int32 { return a ^ 1 } //go:noinline func xor_1_int32(a int32) int32 { return 1 ^ a } //go:noinline func xor_int32_2147483647(a int32) int32 { return a ^ 2147483647 } //go:noinline func xor_2147483647_int32(a int32) int32 { return 2147483647 ^ a } //go:noinline func add_uint16_0(a uint16) uint16 { return a + 0 } //go:noinline func add_0_uint16(a uint16) uint16 { return 0 + a } //go:noinline func add_uint16_1(a uint16) uint16 { return a + 1 } //go:noinline func add_1_uint16(a uint16) uint16 { return 1 + a } //go:noinline func add_uint16_65535(a uint16) uint16 { return a + 65535 } //go:noinline func add_65535_uint16(a uint16) uint16 { return 65535 + a } //go:noinline func sub_uint16_0(a uint16) uint16 { return a - 0 } //go:noinline func sub_0_uint16(a uint16) uint16 { return 0 - a } //go:noinline func sub_uint16_1(a uint16) uint16 { return a - 1 } //go:noinline func sub_1_uint16(a uint16) uint16 { return 1 - a } //go:noinline func sub_uint16_65535(a uint16) uint16 { return a - 65535 } //go:noinline func sub_65535_uint16(a uint16) uint16 { return 65535 - a } //go:noinline func div_0_uint16(a uint16) uint16 { return 0 / a } //go:noinline func div_uint16_1(a uint16) uint16 { return a / 1 } //go:noinline func div_1_uint16(a uint16) uint16 { return 1 / a } //go:noinline func div_uint16_65535(a uint16) uint16 { return a / 65535 } //go:noinline func div_65535_uint16(a uint16) uint16 { return 65535 / a } //go:noinline func mul_uint16_0(a uint16) uint16 { return a * 0 } //go:noinline func mul_0_uint16(a uint16) uint16 { return 0 * a } //go:noinline func mul_uint16_1(a uint16) uint16 { return a * 1 } //go:noinline func mul_1_uint16(a uint16) uint16 { return 1 * a } //go:noinline func mul_uint16_65535(a uint16) uint16 { return a * 65535 } //go:noinline func mul_65535_uint16(a uint16) uint16 { return 65535 * a } //go:noinline func lsh_uint16_0(a uint16) uint16 { return a << 0 } //go:noinline func lsh_0_uint16(a uint16) uint16 { return 0 << a } //go:noinline func lsh_uint16_1(a uint16) uint16 { return a << 1 } //go:noinline func lsh_1_uint16(a uint16) uint16 { return 1 << a } //go:noinline func lsh_uint16_65535(a uint16) uint16 { return a << 65535 } //go:noinline func lsh_65535_uint16(a uint16) uint16 { return 65535 << a } //go:noinline func rsh_uint16_0(a uint16) uint16 { return a >> 0 } //go:noinline func rsh_0_uint16(a uint16) uint16 { return 0 >> a } //go:noinline func rsh_uint16_1(a uint16) uint16 { return a >> 1 } //go:noinline func rsh_1_uint16(a uint16) uint16 { return 1 >> a } //go:noinline func rsh_uint16_65535(a uint16) uint16 { return a >> 65535 } //go:noinline func rsh_65535_uint16(a uint16) uint16 { return 65535 >> a } //go:noinline func mod_0_uint16(a uint16) uint16 { return 0 % a } //go:noinline func mod_uint16_1(a uint16) uint16 { return a % 1 } //go:noinline func mod_1_uint16(a uint16) uint16 { return 1 % a } //go:noinline func mod_uint16_65535(a uint16) uint16 { return a % 65535 } //go:noinline func mod_65535_uint16(a uint16) uint16 { return 65535 % a } //go:noinline func and_uint16_0(a uint16) uint16 { return a & 0 } //go:noinline func and_0_uint16(a uint16) uint16 { return 0 & a } //go:noinline func and_uint16_1(a uint16) uint16 { return a & 1 } //go:noinline func and_1_uint16(a uint16) uint16 { return 1 & a } //go:noinline func and_uint16_65535(a uint16) uint16 { return a & 65535 } //go:noinline func and_65535_uint16(a uint16) uint16 { return 65535 & a } //go:noinline func or_uint16_0(a uint16) uint16 { return a | 0 } //go:noinline func or_0_uint16(a uint16) uint16 { return 0 | a } //go:noinline func or_uint16_1(a uint16) uint16 { return a | 1 } //go:noinline func or_1_uint16(a uint16) uint16 { return 1 | a } //go:noinline func or_uint16_65535(a uint16) uint16 { return a | 65535 } //go:noinline func or_65535_uint16(a uint16) uint16 { return 65535 | a } //go:noinline func xor_uint16_0(a uint16) uint16 { return a ^ 0 } //go:noinline func xor_0_uint16(a uint16) uint16 { return 0 ^ a } //go:noinline func xor_uint16_1(a uint16) uint16 { return a ^ 1 } //go:noinline func xor_1_uint16(a uint16) uint16 { return 1 ^ a } //go:noinline func xor_uint16_65535(a uint16) uint16 { return a ^ 65535 } //go:noinline func xor_65535_uint16(a uint16) uint16 { return 65535 ^ a } //go:noinline func add_int16_Neg32768(a int16) int16 { return a + -32768 } //go:noinline func add_Neg32768_int16(a int16) int16 { return -32768 + a } //go:noinline func add_int16_Neg32767(a int16) int16 { return a + -32767 } //go:noinline func add_Neg32767_int16(a int16) int16 { return -32767 + a } //go:noinline func add_int16_Neg1(a int16) int16 { return a + -1 } //go:noinline func add_Neg1_int16(a int16) int16 { return -1 + a } //go:noinline func add_int16_0(a int16) int16 { return a + 0 } //go:noinline func add_0_int16(a int16) int16 { return 0 + a } //go:noinline func add_int16_1(a int16) int16 { return a + 1 } //go:noinline func add_1_int16(a int16) int16 { return 1 + a } //go:noinline func add_int16_32766(a int16) int16 { return a + 32766 } //go:noinline func add_32766_int16(a int16) int16 { return 32766 + a } //go:noinline func add_int16_32767(a int16) int16 { return a + 32767 } //go:noinline func add_32767_int16(a int16) int16 { return 32767 + a } //go:noinline func sub_int16_Neg32768(a int16) int16 { return a - -32768 } //go:noinline func sub_Neg32768_int16(a int16) int16 { return -32768 - a } //go:noinline func sub_int16_Neg32767(a int16) int16 { return a - -32767 } //go:noinline func sub_Neg32767_int16(a int16) int16 { return -32767 - a } //go:noinline func sub_int16_Neg1(a int16) int16 { return a - -1 } //go:noinline func sub_Neg1_int16(a int16) int16 { return -1 - a } //go:noinline func sub_int16_0(a int16) int16 { return a - 0 } //go:noinline func sub_0_int16(a int16) int16 { return 0 - a } //go:noinline func sub_int16_1(a int16) int16 { return a - 1 } //go:noinline func sub_1_int16(a int16) int16 { return 1 - a } //go:noinline func sub_int16_32766(a int16) int16 { return a - 32766 } //go:noinline func sub_32766_int16(a int16) int16 { return 32766 - a } //go:noinline func sub_int16_32767(a int16) int16 { return a - 32767 } //go:noinline func sub_32767_int16(a int16) int16 { return 32767 - a } //go:noinline func div_int16_Neg32768(a int16) int16 { return a / -32768 } //go:noinline func div_Neg32768_int16(a int16) int16 { return -32768 / a } //go:noinline func div_int16_Neg32767(a int16) int16 { return a / -32767 } //go:noinline func div_Neg32767_int16(a int16) int16 { return -32767 / a } //go:noinline func div_int16_Neg1(a int16) int16 { return a / -1 } //go:noinline func div_Neg1_int16(a int16) int16 { return -1 / a } //go:noinline func div_0_int16(a int16) int16 { return 0 / a } //go:noinline func div_int16_1(a int16) int16 { return a / 1 } //go:noinline func div_1_int16(a int16) int16 { return 1 / a } //go:noinline func div_int16_32766(a int16) int16 { return a / 32766 } //go:noinline func div_32766_int16(a int16) int16 { return 32766 / a } //go:noinline func div_int16_32767(a int16) int16 { return a / 32767 } //go:noinline func div_32767_int16(a int16) int16 { return 32767 / a } //go:noinline func mul_int16_Neg32768(a int16) int16 { return a * -32768 } //go:noinline func mul_Neg32768_int16(a int16) int16 { return -32768 * a } //go:noinline func mul_int16_Neg32767(a int16) int16 { return a * -32767 } //go:noinline func mul_Neg32767_int16(a int16) int16 { return -32767 * a } //go:noinline func mul_int16_Neg1(a int16) int16 { return a * -1 } //go:noinline func mul_Neg1_int16(a int16) int16 { return -1 * a } //go:noinline func mul_int16_0(a int16) int16 { return a * 0 } //go:noinline func mul_0_int16(a int16) int16 { return 0 * a } //go:noinline func mul_int16_1(a int16) int16 { return a * 1 } //go:noinline func mul_1_int16(a int16) int16 { return 1 * a } //go:noinline func mul_int16_32766(a int16) int16 { return a * 32766 } //go:noinline func mul_32766_int16(a int16) int16 { return 32766 * a } //go:noinline func mul_int16_32767(a int16) int16 { return a * 32767 } //go:noinline func mul_32767_int16(a int16) int16 { return 32767 * a } //go:noinline func mod_int16_Neg32768(a int16) int16 { return a % -32768 } //go:noinline func mod_Neg32768_int16(a int16) int16 { return -32768 % a } //go:noinline func mod_int16_Neg32767(a int16) int16 { return a % -32767 } //go:noinline func mod_Neg32767_int16(a int16) int16 { return -32767 % a } //go:noinline func mod_int16_Neg1(a int16) int16 { return a % -1 } //go:noinline func mod_Neg1_int16(a int16) int16 { return -1 % a } //go:noinline func mod_0_int16(a int16) int16 { return 0 % a } //go:noinline func mod_int16_1(a int16) int16 { return a % 1 } //go:noinline func mod_1_int16(a int16) int16 { return 1 % a } //go:noinline func mod_int16_32766(a int16) int16 { return a % 32766 } //go:noinline func mod_32766_int16(a int16) int16 { return 32766 % a } //go:noinline func mod_int16_32767(a int16) int16 { return a % 32767 } //go:noinline func mod_32767_int16(a int16) int16 { return 32767 % a } //go:noinline func and_int16_Neg32768(a int16) int16 { return a & -32768 } //go:noinline func and_Neg32768_int16(a int16) int16 { return -32768 & a } //go:noinline func and_int16_Neg32767(a int16) int16 { return a & -32767 } //go:noinline func and_Neg32767_int16(a int16) int16 { return -32767 & a } //go:noinline func and_int16_Neg1(a int16) int16 { return a & -1 } //go:noinline func and_Neg1_int16(a int16) int16 { return -1 & a } //go:noinline func and_int16_0(a int16) int16 { return a & 0 } //go:noinline func and_0_int16(a int16) int16 { return 0 & a } //go:noinline func and_int16_1(a int16) int16 { return a & 1 } //go:noinline func and_1_int16(a int16) int16 { return 1 & a } //go:noinline func and_int16_32766(a int16) int16 { return a & 32766 } //go:noinline func and_32766_int16(a int16) int16 { return 32766 & a } //go:noinline func and_int16_32767(a int16) int16 { return a & 32767 } //go:noinline func and_32767_int16(a int16) int16 { return 32767 & a } //go:noinline func or_int16_Neg32768(a int16) int16 { return a | -32768 } //go:noinline func or_Neg32768_int16(a int16) int16 { return -32768 | a } //go:noinline func or_int16_Neg32767(a int16) int16 { return a | -32767 } //go:noinline func or_Neg32767_int16(a int16) int16 { return -32767 | a } //go:noinline func or_int16_Neg1(a int16) int16 { return a | -1 } //go:noinline func or_Neg1_int16(a int16) int16 { return -1 | a } //go:noinline func or_int16_0(a int16) int16 { return a | 0 } //go:noinline func or_0_int16(a int16) int16 { return 0 | a } //go:noinline func or_int16_1(a int16) int16 { return a | 1 } //go:noinline func or_1_int16(a int16) int16 { return 1 | a } //go:noinline func or_int16_32766(a int16) int16 { return a | 32766 } //go:noinline func or_32766_int16(a int16) int16 { return 32766 | a } //go:noinline func or_int16_32767(a int16) int16 { return a | 32767 } //go:noinline func or_32767_int16(a int16) int16 { return 32767 | a } //go:noinline func xor_int16_Neg32768(a int16) int16 { return a ^ -32768 } //go:noinline func xor_Neg32768_int16(a int16) int16 { return -32768 ^ a } //go:noinline func xor_int16_Neg32767(a int16) int16 { return a ^ -32767 } //go:noinline func xor_Neg32767_int16(a int16) int16 { return -32767 ^ a } //go:noinline func xor_int16_Neg1(a int16) int16 { return a ^ -1 } //go:noinline func xor_Neg1_int16(a int16) int16 { return -1 ^ a } //go:noinline func xor_int16_0(a int16) int16 { return a ^ 0 } //go:noinline func xor_0_int16(a int16) int16 { return 0 ^ a } //go:noinline func xor_int16_1(a int16) int16 { return a ^ 1 } //go:noinline func xor_1_int16(a int16) int16 { return 1 ^ a } //go:noinline func xor_int16_32766(a int16) int16 { return a ^ 32766 } //go:noinline func xor_32766_int16(a int16) int16 { return 32766 ^ a } //go:noinline func xor_int16_32767(a int16) int16 { return a ^ 32767 } //go:noinline func xor_32767_int16(a int16) int16 { return 32767 ^ a } //go:noinline func add_uint8_0(a uint8) uint8 { return a + 0 } //go:noinline func add_0_uint8(a uint8) uint8 { return 0 + a } //go:noinline func add_uint8_1(a uint8) uint8 { return a + 1 } //go:noinline func add_1_uint8(a uint8) uint8 { return 1 + a } //go:noinline func add_uint8_255(a uint8) uint8 { return a + 255 } //go:noinline func add_255_uint8(a uint8) uint8 { return 255 + a } //go:noinline func sub_uint8_0(a uint8) uint8 { return a - 0 } //go:noinline func sub_0_uint8(a uint8) uint8 { return 0 - a } //go:noinline func sub_uint8_1(a uint8) uint8 { return a - 1 } //go:noinline func sub_1_uint8(a uint8) uint8 { return 1 - a } //go:noinline func sub_uint8_255(a uint8) uint8 { return a - 255 } //go:noinline func sub_255_uint8(a uint8) uint8 { return 255 - a } //go:noinline func div_0_uint8(a uint8) uint8 { return 0 / a } //go:noinline func div_uint8_1(a uint8) uint8 { return a / 1 } //go:noinline func div_1_uint8(a uint8) uint8 { return 1 / a } //go:noinline func div_uint8_255(a uint8) uint8 { return a / 255 } //go:noinline func div_255_uint8(a uint8) uint8 { return 255 / a } //go:noinline func mul_uint8_0(a uint8) uint8 { return a * 0 } //go:noinline func mul_0_uint8(a uint8) uint8 { return 0 * a } //go:noinline func mul_uint8_1(a uint8) uint8 { return a * 1 } //go:noinline func mul_1_uint8(a uint8) uint8 { return 1 * a } //go:noinline func mul_uint8_255(a uint8) uint8 { return a * 255 } //go:noinline func mul_255_uint8(a uint8) uint8 { return 255 * a } //go:noinline func lsh_uint8_0(a uint8) uint8 { return a << 0 } //go:noinline func lsh_0_uint8(a uint8) uint8 { return 0 << a } //go:noinline func lsh_uint8_1(a uint8) uint8 { return a << 1 } //go:noinline func lsh_1_uint8(a uint8) uint8 { return 1 << a } //go:noinline func lsh_uint8_255(a uint8) uint8 { return a << 255 } //go:noinline func lsh_255_uint8(a uint8) uint8 { return 255 << a } //go:noinline func rsh_uint8_0(a uint8) uint8 { return a >> 0 } //go:noinline func rsh_0_uint8(a uint8) uint8 { return 0 >> a } //go:noinline func rsh_uint8_1(a uint8) uint8 { return a >> 1 } //go:noinline func rsh_1_uint8(a uint8) uint8 { return 1 >> a } //go:noinline func rsh_uint8_255(a uint8) uint8 { return a >> 255 } //go:noinline func rsh_255_uint8(a uint8) uint8 { return 255 >> a } //go:noinline func mod_0_uint8(a uint8) uint8 { return 0 % a } //go:noinline func mod_uint8_1(a uint8) uint8 { return a % 1 } //go:noinline func mod_1_uint8(a uint8) uint8 { return 1 % a } //go:noinline func mod_uint8_255(a uint8) uint8 { return a % 255 } //go:noinline func mod_255_uint8(a uint8) uint8 { return 255 % a } //go:noinline func and_uint8_0(a uint8) uint8 { return a & 0 } //go:noinline func and_0_uint8(a uint8) uint8 { return 0 & a } //go:noinline func and_uint8_1(a uint8) uint8 { return a & 1 } //go:noinline func and_1_uint8(a uint8) uint8 { return 1 & a } //go:noinline func and_uint8_255(a uint8) uint8 { return a & 255 } //go:noinline func and_255_uint8(a uint8) uint8 { return 255 & a } //go:noinline func or_uint8_0(a uint8) uint8 { return a | 0 } //go:noinline func or_0_uint8(a uint8) uint8 { return 0 | a } //go:noinline func or_uint8_1(a uint8) uint8 { return a | 1 } //go:noinline func or_1_uint8(a uint8) uint8 { return 1 | a } //go:noinline func or_uint8_255(a uint8) uint8 { return a | 255 } //go:noinline func or_255_uint8(a uint8) uint8 { return 255 | a } //go:noinline func xor_uint8_0(a uint8) uint8 { return a ^ 0 } //go:noinline func xor_0_uint8(a uint8) uint8 { return 0 ^ a } //go:noinline func xor_uint8_1(a uint8) uint8 { return a ^ 1 } //go:noinline func xor_1_uint8(a uint8) uint8 { return 1 ^ a } //go:noinline func xor_uint8_255(a uint8) uint8 { return a ^ 255 } //go:noinline func xor_255_uint8(a uint8) uint8 { return 255 ^ a } //go:noinline func add_int8_Neg128(a int8) int8 { return a + -128 } //go:noinline func add_Neg128_int8(a int8) int8 { return -128 + a } //go:noinline func add_int8_Neg127(a int8) int8 { return a + -127 } //go:noinline func add_Neg127_int8(a int8) int8 { return -127 + a } //go:noinline func add_int8_Neg1(a int8) int8 { return a + -1 } //go:noinline func add_Neg1_int8(a int8) int8 { return -1 + a } //go:noinline func add_int8_0(a int8) int8 { return a + 0 } //go:noinline func add_0_int8(a int8) int8 { return 0 + a } //go:noinline func add_int8_1(a int8) int8 { return a + 1 } //go:noinline func add_1_int8(a int8) int8 { return 1 + a } //go:noinline func add_int8_126(a int8) int8 { return a + 126 } //go:noinline func add_126_int8(a int8) int8 { return 126 + a } //go:noinline func add_int8_127(a int8) int8 { return a + 127 } //go:noinline func add_127_int8(a int8) int8 { return 127 + a } //go:noinline func sub_int8_Neg128(a int8) int8 { return a - -128 } //go:noinline func sub_Neg128_int8(a int8) int8 { return -128 - a } //go:noinline func sub_int8_Neg127(a int8) int8 { return a - -127 } //go:noinline func sub_Neg127_int8(a int8) int8 { return -127 - a } //go:noinline func sub_int8_Neg1(a int8) int8 { return a - -1 } //go:noinline func sub_Neg1_int8(a int8) int8 { return -1 - a } //go:noinline func sub_int8_0(a int8) int8 { return a - 0 } //go:noinline func sub_0_int8(a int8) int8 { return 0 - a } //go:noinline func sub_int8_1(a int8) int8 { return a - 1 } //go:noinline func sub_1_int8(a int8) int8 { return 1 - a } //go:noinline func sub_int8_126(a int8) int8 { return a - 126 } //go:noinline func sub_126_int8(a int8) int8 { return 126 - a } //go:noinline func sub_int8_127(a int8) int8 { return a - 127 } //go:noinline func sub_127_int8(a int8) int8 { return 127 - a } //go:noinline func div_int8_Neg128(a int8) int8 { return a / -128 } //go:noinline func div_Neg128_int8(a int8) int8 { return -128 / a } //go:noinline func div_int8_Neg127(a int8) int8 { return a / -127 } //go:noinline func div_Neg127_int8(a int8) int8 { return -127 / a } //go:noinline func div_int8_Neg1(a int8) int8 { return a / -1 } //go:noinline func div_Neg1_int8(a int8) int8 { return -1 / a } //go:noinline func div_0_int8(a int8) int8 { return 0 / a } //go:noinline func div_int8_1(a int8) int8 { return a / 1 } //go:noinline func div_1_int8(a int8) int8 { return 1 / a } //go:noinline func div_int8_126(a int8) int8 { return a / 126 } //go:noinline func div_126_int8(a int8) int8 { return 126 / a } //go:noinline func div_int8_127(a int8) int8 { return a / 127 } //go:noinline func div_127_int8(a int8) int8 { return 127 / a } //go:noinline func mul_int8_Neg128(a int8) int8 { return a * -128 } //go:noinline func mul_Neg128_int8(a int8) int8 { return -128 * a } //go:noinline func mul_int8_Neg127(a int8) int8 { return a * -127 } //go:noinline func mul_Neg127_int8(a int8) int8 { return -127 * a } //go:noinline func mul_int8_Neg1(a int8) int8 { return a * -1 } //go:noinline func mul_Neg1_int8(a int8) int8 { return -1 * a } //go:noinline func mul_int8_0(a int8) int8 { return a * 0 } //go:noinline func mul_0_int8(a int8) int8 { return 0 * a } //go:noinline func mul_int8_1(a int8) int8 { return a * 1 } //go:noinline func mul_1_int8(a int8) int8 { return 1 * a } //go:noinline func mul_int8_126(a int8) int8 { return a * 126 } //go:noinline func mul_126_int8(a int8) int8 { return 126 * a } //go:noinline func mul_int8_127(a int8) int8 { return a * 127 } //go:noinline func mul_127_int8(a int8) int8 { return 127 * a } //go:noinline func mod_int8_Neg128(a int8) int8 { return a % -128 } //go:noinline func mod_Neg128_int8(a int8) int8 { return -128 % a } //go:noinline func mod_int8_Neg127(a int8) int8 { return a % -127 } //go:noinline func mod_Neg127_int8(a int8) int8 { return -127 % a } //go:noinline func mod_int8_Neg1(a int8) int8 { return a % -1 } //go:noinline func mod_Neg1_int8(a int8) int8 { return -1 % a } //go:noinline func mod_0_int8(a int8) int8 { return 0 % a } //go:noinline func mod_int8_1(a int8) int8 { return a % 1 } //go:noinline func mod_1_int8(a int8) int8 { return 1 % a } //go:noinline func mod_int8_126(a int8) int8 { return a % 126 } //go:noinline func mod_126_int8(a int8) int8 { return 126 % a } //go:noinline func mod_int8_127(a int8) int8 { return a % 127 } //go:noinline func mod_127_int8(a int8) int8 { return 127 % a } //go:noinline func and_int8_Neg128(a int8) int8 { return a & -128 } //go:noinline func and_Neg128_int8(a int8) int8 { return -128 & a } //go:noinline func and_int8_Neg127(a int8) int8 { return a & -127 } //go:noinline func and_Neg127_int8(a int8) int8 { return -127 & a } //go:noinline func and_int8_Neg1(a int8) int8 { return a & -1 } //go:noinline func and_Neg1_int8(a int8) int8 { return -1 & a } //go:noinline func and_int8_0(a int8) int8 { return a & 0 } //go:noinline func and_0_int8(a int8) int8 { return 0 & a } //go:noinline func and_int8_1(a int8) int8 { return a & 1 } //go:noinline func and_1_int8(a int8) int8 { return 1 & a } //go:noinline func and_int8_126(a int8) int8 { return a & 126 } //go:noinline func and_126_int8(a int8) int8 { return 126 & a } //go:noinline func and_int8_127(a int8) int8 { return a & 127 } //go:noinline func and_127_int8(a int8) int8 { return 127 & a } //go:noinline func or_int8_Neg128(a int8) int8 { return a | -128 } //go:noinline func or_Neg128_int8(a int8) int8 { return -128 | a } //go:noinline func or_int8_Neg127(a int8) int8 { return a | -127 } //go:noinline func or_Neg127_int8(a int8) int8 { return -127 | a } //go:noinline func or_int8_Neg1(a int8) int8 { return a | -1 } //go:noinline func or_Neg1_int8(a int8) int8 { return -1 | a } //go:noinline func or_int8_0(a int8) int8 { return a | 0 } //go:noinline func or_0_int8(a int8) int8 { return 0 | a } //go:noinline func or_int8_1(a int8) int8 { return a | 1 } //go:noinline func or_1_int8(a int8) int8 { return 1 | a } //go:noinline func or_int8_126(a int8) int8 { return a | 126 } //go:noinline func or_126_int8(a int8) int8 { return 126 | a } //go:noinline func or_int8_127(a int8) int8 { return a | 127 } //go:noinline func or_127_int8(a int8) int8 { return 127 | a } //go:noinline func xor_int8_Neg128(a int8) int8 { return a ^ -128 } //go:noinline func xor_Neg128_int8(a int8) int8 { return -128 ^ a } //go:noinline func xor_int8_Neg127(a int8) int8 { return a ^ -127 } //go:noinline func xor_Neg127_int8(a int8) int8 { return -127 ^ a } //go:noinline func xor_int8_Neg1(a int8) int8 { return a ^ -1 } //go:noinline func xor_Neg1_int8(a int8) int8 { return -1 ^ a } //go:noinline func xor_int8_0(a int8) int8 { return a ^ 0 } //go:noinline func xor_0_int8(a int8) int8 { return 0 ^ a } //go:noinline func xor_int8_1(a int8) int8 { return a ^ 1 } //go:noinline func xor_1_int8(a int8) int8 { return 1 ^ a } //go:noinline func xor_int8_126(a int8) int8 { return a ^ 126 } //go:noinline func xor_126_int8(a int8) int8 { return 126 ^ a } //go:noinline func xor_int8_127(a int8) int8 { return a ^ 127 } //go:noinline func xor_127_int8(a int8) int8 { return 127 ^ a } type test_uint64 struct { fn func(uint64) uint64 fnname string in uint64 want uint64 } var tests_uint64 = []test_uint64{ test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 0, want: 0}, test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 0, want: 0}, test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 1, want: 1}, test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 1, want: 1}, test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 4294967296, want: 4294967296}, test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 0, want: 1}, test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 0, want: 1}, test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 1, want: 2}, test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 1, want: 2}, test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 4294967296, want: 4294967297}, test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 4294967296, want: 4294967297}, test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 18446744073709551615, want: 0}, test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 0, want: 4294967296}, test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 0, want: 4294967296}, test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 1, want: 4294967297}, test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 1, want: 4294967297}, test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 4294967296, want: 8589934592}, test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 4294967296, want: 8589934592}, test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 18446744073709551615, want: 4294967295}, test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 18446744073709551615, want: 4294967295}, test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 0, want: 9223372036854775808}, test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 1, want: 9223372036854775809}, test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 1, want: 9223372036854775809}, test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 0, want: 18446744073709551615}, test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 1, want: 0}, test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 1, want: 0}, test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 4294967296, want: 4294967295}, test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 4294967296, want: 4294967295}, test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 18446744073709551615, want: 18446744073709551614}, test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 18446744073709551615, want: 18446744073709551614}, test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 0, want: 0}, test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 0, want: 0}, test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 1, want: 18446744073709551615}, test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 1, want: 1}, test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 4294967296, want: 18446744069414584320}, test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 4294967296, want: 4294967296}, test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 18446744073709551615, want: 1}, test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 0, want: 1}, test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 0, want: 18446744073709551615}, test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 1, want: 0}, test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 1, want: 0}, test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 4294967296, want: 18446744069414584321}, test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 4294967296, want: 4294967295}, test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 18446744073709551615, want: 2}, test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 18446744073709551615, want: 18446744073709551614}, test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 0, want: 4294967296}, test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 0, want: 18446744069414584320}, test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 1, want: 4294967295}, test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 1, want: 18446744069414584321}, test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 4294967296, want: 0}, test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 4294967296, want: 0}, test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 9223372036854775808, want: 9223372032559808512}, test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 18446744073709551615, want: 4294967297}, test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 18446744073709551615, want: 18446744069414584319}, test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 0, want: 9223372036854775808}, test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 1, want: 9223372036854775807}, test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 1, want: 9223372036854775809}, test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 4294967296, want: 9223372032559808512}, test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775809}, test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 0, want: 1}, test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 1, want: 18446744073709551614}, test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 1, want: 2}, test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 4294967296, want: 18446744069414584319}, test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 4294967296, want: 4294967297}, test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 18446744073709551615, want: 0}, test_uint64{fn: div_0_uint64, fnname: "div_0_uint64", in: 1, want: 0}, test_uint64{fn: div_0_uint64, fnname: "div_0_uint64", in: 4294967296, want: 0}, test_uint64{fn: div_0_uint64, fnname: "div_0_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: div_0_uint64, fnname: "div_0_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 0, want: 0}, test_uint64{fn: div_1_uint64, fnname: "div_1_uint64", in: 1, want: 1}, test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 1, want: 1}, test_uint64{fn: div_1_uint64, fnname: "div_1_uint64", in: 4294967296, want: 0}, test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 4294967296, want: 4294967296}, test_uint64{fn: div_1_uint64, fnname: "div_1_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: div_1_uint64, fnname: "div_1_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 0, want: 0}, test_uint64{fn: div_4294967296_uint64, fnname: "div_4294967296_uint64", in: 1, want: 4294967296}, test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 1, want: 0}, test_uint64{fn: div_4294967296_uint64, fnname: "div_4294967296_uint64", in: 4294967296, want: 1}, test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 4294967296, want: 1}, test_uint64{fn: div_4294967296_uint64, fnname: "div_4294967296_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 9223372036854775808, want: 2147483648}, test_uint64{fn: div_4294967296_uint64, fnname: "div_4294967296_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 18446744073709551615, want: 4294967295}, test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 0, want: 0}, test_uint64{fn: div_9223372036854775808_uint64, fnname: "div_9223372036854775808_uint64", in: 1, want: 9223372036854775808}, test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 1, want: 0}, test_uint64{fn: div_9223372036854775808_uint64, fnname: "div_9223372036854775808_uint64", in: 4294967296, want: 2147483648}, test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 4294967296, want: 0}, test_uint64{fn: div_9223372036854775808_uint64, fnname: "div_9223372036854775808_uint64", in: 9223372036854775808, want: 1}, test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 9223372036854775808, want: 1}, test_uint64{fn: div_9223372036854775808_uint64, fnname: "div_9223372036854775808_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 18446744073709551615, want: 1}, test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 0, want: 0}, test_uint64{fn: div_18446744073709551615_uint64, fnname: "div_18446744073709551615_uint64", in: 1, want: 18446744073709551615}, test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 1, want: 0}, test_uint64{fn: div_18446744073709551615_uint64, fnname: "div_18446744073709551615_uint64", in: 4294967296, want: 4294967295}, test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 4294967296, want: 0}, test_uint64{fn: div_18446744073709551615_uint64, fnname: "div_18446744073709551615_uint64", in: 9223372036854775808, want: 1}, test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 9223372036854775808, want: 0}, test_uint64{fn: div_18446744073709551615_uint64, fnname: "div_18446744073709551615_uint64", in: 18446744073709551615, want: 1}, test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 18446744073709551615, want: 1}, test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 0, want: 0}, test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 0, want: 0}, test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 1, want: 0}, test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 1, want: 0}, test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 4294967296, want: 0}, test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 4294967296, want: 0}, test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 9223372036854775808, want: 0}, test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 18446744073709551615, want: 0}, test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 0, want: 0}, test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 0, want: 0}, test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 1, want: 1}, test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 1, want: 1}, test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 4294967296, want: 4294967296}, test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 0, want: 0}, test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 0, want: 0}, test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 1, want: 4294967296}, test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 1, want: 4294967296}, test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 4294967296, want: 0}, test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 4294967296, want: 0}, test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 9223372036854775808, want: 0}, test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 18446744073709551615, want: 18446744069414584320}, test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 18446744073709551615, want: 18446744069414584320}, test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 0, want: 0}, test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 0, want: 0}, test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 1, want: 9223372036854775808}, test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 1, want: 9223372036854775808}, test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 4294967296, want: 0}, test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 4294967296, want: 0}, test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775808}, test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775808}, test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 0, want: 0}, test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 0, want: 0}, test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 1, want: 18446744073709551615}, test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 1, want: 18446744073709551615}, test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 4294967296, want: 18446744069414584320}, test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 4294967296, want: 18446744069414584320}, test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 18446744073709551615, want: 1}, test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 18446744073709551615, want: 1}, test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 0, want: 0}, test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 0, want: 0}, test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 1, want: 0}, test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 1, want: 1}, test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 4294967296, want: 0}, test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 4294967296, want: 4294967296}, test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 0, want: 1}, test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 0, want: 0}, test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 1, want: 2}, test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 1, want: 2}, test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 4294967296, want: 0}, test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 4294967296, want: 8589934592}, test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 18446744073709551615, want: 18446744073709551614}, test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 0, want: 4294967296}, test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 0, want: 0}, test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 1, want: 8589934592}, test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 1, want: 0}, test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 4294967296, want: 0}, test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 4294967296, want: 0}, test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 0, want: 0}, test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 1, want: 0}, test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 1, want: 0}, test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 4294967296, want: 0}, test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 4294967296, want: 0}, test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 0, want: 0}, test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 1, want: 18446744073709551614}, test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 1, want: 0}, test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 4294967296, want: 0}, test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 4294967296, want: 0}, test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 0, want: 0}, test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 0, want: 0}, test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 1, want: 0}, test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 1, want: 1}, test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 4294967296, want: 0}, test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 4294967296, want: 4294967296}, test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 0, want: 1}, test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 0, want: 0}, test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 1, want: 0}, test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 1, want: 0}, test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 4294967296, want: 0}, test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 4294967296, want: 2147483648}, test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 9223372036854775808, want: 4611686018427387904}, test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 0, want: 4294967296}, test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 0, want: 0}, test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 1, want: 2147483648}, test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 1, want: 0}, test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 4294967296, want: 0}, test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 4294967296, want: 0}, test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 0, want: 0}, test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 1, want: 4611686018427387904}, test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 1, want: 0}, test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 4294967296, want: 0}, test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 4294967296, want: 0}, test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 0, want: 0}, test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 1, want: 9223372036854775807}, test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 1, want: 0}, test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 4294967296, want: 0}, test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 4294967296, want: 0}, test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 18446744073709551615, want: 0}, test_uint64{fn: mod_0_uint64, fnname: "mod_0_uint64", in: 1, want: 0}, test_uint64{fn: mod_0_uint64, fnname: "mod_0_uint64", in: 4294967296, want: 0}, test_uint64{fn: mod_0_uint64, fnname: "mod_0_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: mod_0_uint64, fnname: "mod_0_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 0, want: 0}, test_uint64{fn: mod_1_uint64, fnname: "mod_1_uint64", in: 1, want: 0}, test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 1, want: 0}, test_uint64{fn: mod_1_uint64, fnname: "mod_1_uint64", in: 4294967296, want: 1}, test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 4294967296, want: 0}, test_uint64{fn: mod_1_uint64, fnname: "mod_1_uint64", in: 9223372036854775808, want: 1}, test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 9223372036854775808, want: 0}, test_uint64{fn: mod_1_uint64, fnname: "mod_1_uint64", in: 18446744073709551615, want: 1}, test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 18446744073709551615, want: 0}, test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 0, want: 0}, test_uint64{fn: mod_4294967296_uint64, fnname: "mod_4294967296_uint64", in: 1, want: 0}, test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 1, want: 1}, test_uint64{fn: mod_4294967296_uint64, fnname: "mod_4294967296_uint64", in: 4294967296, want: 0}, test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 4294967296, want: 0}, test_uint64{fn: mod_4294967296_uint64, fnname: "mod_4294967296_uint64", in: 9223372036854775808, want: 4294967296}, test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 9223372036854775808, want: 0}, test_uint64{fn: mod_4294967296_uint64, fnname: "mod_4294967296_uint64", in: 18446744073709551615, want: 4294967296}, test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 18446744073709551615, want: 4294967295}, test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 0, want: 0}, test_uint64{fn: mod_9223372036854775808_uint64, fnname: "mod_9223372036854775808_uint64", in: 1, want: 0}, test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 1, want: 1}, test_uint64{fn: mod_9223372036854775808_uint64, fnname: "mod_9223372036854775808_uint64", in: 4294967296, want: 0}, test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 4294967296, want: 4294967296}, test_uint64{fn: mod_9223372036854775808_uint64, fnname: "mod_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: mod_9223372036854775808_uint64, fnname: "mod_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775808}, test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 0, want: 0}, test_uint64{fn: mod_18446744073709551615_uint64, fnname: "mod_18446744073709551615_uint64", in: 1, want: 0}, test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 1, want: 1}, test_uint64{fn: mod_18446744073709551615_uint64, fnname: "mod_18446744073709551615_uint64", in: 4294967296, want: 4294967295}, test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 4294967296, want: 4294967296}, test_uint64{fn: mod_18446744073709551615_uint64, fnname: "mod_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: mod_18446744073709551615_uint64, fnname: "mod_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 18446744073709551615, want: 0}, test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 0, want: 0}, test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 0, want: 0}, test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 1, want: 0}, test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 1, want: 0}, test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 4294967296, want: 0}, test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 4294967296, want: 0}, test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 9223372036854775808, want: 0}, test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 18446744073709551615, want: 0}, test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 0, want: 0}, test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 0, want: 0}, test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 1, want: 1}, test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 1, want: 1}, test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 4294967296, want: 0}, test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 4294967296, want: 0}, test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 9223372036854775808, want: 0}, test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 18446744073709551615, want: 1}, test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 18446744073709551615, want: 1}, test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 0, want: 0}, test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 0, want: 0}, test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 1, want: 0}, test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 1, want: 0}, test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 4294967296, want: 4294967296}, test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 9223372036854775808, want: 0}, test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 18446744073709551615, want: 4294967296}, test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 18446744073709551615, want: 4294967296}, test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 0, want: 0}, test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 0, want: 0}, test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 1, want: 0}, test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 1, want: 0}, test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 4294967296, want: 0}, test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 4294967296, want: 0}, test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775808}, test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775808}, test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 0, want: 0}, test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 0, want: 0}, test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 1, want: 1}, test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 1, want: 1}, test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 4294967296, want: 4294967296}, test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 0, want: 0}, test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 0, want: 0}, test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 1, want: 1}, test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 1, want: 1}, test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 4294967296, want: 4294967296}, test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 0, want: 1}, test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 0, want: 1}, test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 1, want: 1}, test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 1, want: 1}, test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 4294967296, want: 4294967297}, test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 4294967296, want: 4294967297}, test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 0, want: 4294967296}, test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 0, want: 4294967296}, test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 1, want: 4294967297}, test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 1, want: 4294967297}, test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 4294967296, want: 4294967296}, test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 0, want: 9223372036854775808}, test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 1, want: 9223372036854775809}, test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 1, want: 9223372036854775809}, test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 0, want: 18446744073709551615}, test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 1, want: 18446744073709551615}, test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 1, want: 18446744073709551615}, test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 4294967296, want: 18446744073709551615}, test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 4294967296, want: 18446744073709551615}, test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 9223372036854775808, want: 18446744073709551615}, test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 9223372036854775808, want: 18446744073709551615}, test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 0, want: 0}, test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 0, want: 0}, test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 1, want: 1}, test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 1, want: 1}, test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 4294967296, want: 4294967296}, test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 0, want: 1}, test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 0, want: 1}, test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 1, want: 0}, test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 1, want: 0}, test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 4294967296, want: 4294967297}, test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 4294967296, want: 4294967297}, test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 18446744073709551615, want: 18446744073709551614}, test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 18446744073709551615, want: 18446744073709551614}, test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 0, want: 4294967296}, test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 0, want: 4294967296}, test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 1, want: 4294967297}, test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 1, want: 4294967297}, test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 4294967296, want: 0}, test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 4294967296, want: 0}, test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 18446744073709551615, want: 18446744069414584319}, test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 18446744073709551615, want: 18446744069414584319}, test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 0, want: 9223372036854775808}, test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 1, want: 9223372036854775809}, test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 1, want: 9223372036854775809}, test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 0, want: 18446744073709551615}, test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 1, want: 18446744073709551614}, test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 1, want: 18446744073709551614}, test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 4294967296, want: 18446744069414584319}, test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 4294967296, want: 18446744069414584319}, test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 18446744073709551615, want: 0}} type test_int64 struct { fn func(int64) int64 fnname string in int64 want int64 } var tests_int64 = []test_int64{ test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: -9223372036854775807, want: 1}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: -9223372036854775807, want: 1}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: -4294967296, want: 9223372032559808512}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: -4294967296, want: 9223372032559808512}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: -1, want: 9223372036854775807}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: -1, want: 9223372036854775807}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 0, want: -9223372036854775808}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 0, want: -9223372036854775808}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 1, want: -9223372036854775807}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 1, want: -9223372036854775807}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 4294967296, want: -9223372032559808512}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 4294967296, want: -9223372032559808512}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 9223372036854775806, want: -2}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 9223372036854775806, want: -2}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 9223372036854775807, want: -1}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: -9223372036854775808, want: 1}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: -9223372036854775808, want: 1}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: -9223372036854775807, want: 2}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: -9223372036854775807, want: 2}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: -4294967296, want: 9223372032559808513}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: -4294967296, want: 9223372032559808513}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: -1, want: -9223372036854775808}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: -1, want: -9223372036854775808}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 0, want: -9223372036854775807}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 0, want: -9223372036854775807}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 1, want: -9223372036854775806}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 1, want: -9223372036854775806}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 4294967296, want: -9223372032559808511}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 4294967296, want: -9223372032559808511}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 9223372036854775806, want: -1}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 9223372036854775807, want: 0}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 9223372036854775807, want: 0}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: -9223372036854775808, want: 9223372032559808512}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: -9223372036854775808, want: 9223372032559808512}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: -9223372036854775807, want: 9223372032559808513}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: -9223372036854775807, want: 9223372032559808513}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: -4294967296, want: -8589934592}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: -4294967296, want: -8589934592}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: -1, want: -4294967297}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: -1, want: -4294967297}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 0, want: -4294967296}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 0, want: -4294967296}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 1, want: -4294967295}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 1, want: -4294967295}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 4294967296, want: 0}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 9223372036854775806, want: 9223372032559808510}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 9223372036854775806, want: 9223372032559808510}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 9223372036854775807, want: 9223372032559808511}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 9223372036854775807, want: 9223372032559808511}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: -4294967296, want: -4294967297}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: -4294967296, want: -4294967297}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: -1, want: -2}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: -1, want: -2}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 0, want: -1}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 0, want: -1}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 1, want: 0}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 1, want: 0}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 4294967296, want: 4294967295}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 4294967296, want: 4294967295}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 9223372036854775806, want: 9223372036854775805}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 9223372036854775806, want: 9223372036854775805}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: -4294967296, want: -4294967296}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: -4294967296, want: -4294967296}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: -1, want: -1}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: -1, want: -1}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 0, want: 0}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 0, want: 0}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 1, want: 1}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 1, want: 1}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 4294967296, want: 4294967296}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 4294967296, want: 4294967296}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: -9223372036854775807, want: -9223372036854775806}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: -9223372036854775807, want: -9223372036854775806}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: -4294967296, want: -4294967295}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: -4294967296, want: -4294967295}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: -1, want: 0}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: -1, want: 0}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 0, want: 1}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 0, want: 1}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 1, want: 2}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 1, want: 2}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 4294967296, want: 4294967297}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 4294967296, want: 4294967297}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: -4294967296, want: 0}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: -1, want: 4294967295}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: -1, want: 4294967295}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 0, want: 4294967296}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 0, want: 4294967296}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 1, want: 4294967297}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 1, want: 4294967297}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 4294967296, want: 8589934592}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 4294967296, want: 8589934592}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 9223372036854775806, want: -9223372032559808514}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 9223372036854775806, want: -9223372032559808514}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 9223372036854775807, want: -9223372032559808513}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 9223372036854775807, want: -9223372032559808513}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: -9223372036854775808, want: -2}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: -9223372036854775808, want: -2}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: -9223372036854775807, want: -1}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: -9223372036854775807, want: -1}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: -4294967296, want: 9223372032559808510}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: -4294967296, want: 9223372032559808510}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: -1, want: 9223372036854775805}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: -1, want: 9223372036854775805}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 0, want: 9223372036854775806}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 0, want: 9223372036854775806}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 1, want: 9223372036854775807}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 1, want: 9223372036854775807}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 4294967296, want: -9223372032559808514}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 4294967296, want: -9223372032559808514}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 9223372036854775806, want: -4}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 9223372036854775806, want: -4}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 9223372036854775807, want: -3}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 9223372036854775807, want: -3}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: -9223372036854775808, want: -1}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: -9223372036854775807, want: 0}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: -9223372036854775807, want: 0}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: -4294967296, want: 9223372032559808511}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: -4294967296, want: 9223372032559808511}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: -1, want: 9223372036854775806}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: -1, want: 9223372036854775806}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 0, want: 9223372036854775807}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 0, want: 9223372036854775807}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 1, want: -9223372036854775808}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 1, want: -9223372036854775808}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 4294967296, want: -9223372032559808513}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 4294967296, want: -9223372032559808513}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 9223372036854775806, want: -3}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 9223372036854775806, want: -3}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 9223372036854775807, want: -2}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 9223372036854775807, want: -2}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: -9223372036854775807, want: -1}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: -9223372036854775807, want: 1}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: -4294967296, want: -9223372032559808512}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: -4294967296, want: 9223372032559808512}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: -1, want: -9223372036854775807}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: -1, want: 9223372036854775807}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 0, want: -9223372036854775808}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 0, want: -9223372036854775808}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 1, want: 9223372036854775807}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 1, want: -9223372036854775807}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 4294967296, want: 9223372032559808512}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 4294967296, want: -9223372032559808512}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 9223372036854775806, want: 2}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 9223372036854775806, want: -2}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 9223372036854775807, want: 1}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 9223372036854775807, want: -1}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: -9223372036854775808, want: 1}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: -9223372036854775807, want: 0}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: -9223372036854775807, want: 0}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: -4294967296, want: -9223372032559808511}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: -4294967296, want: 9223372032559808511}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: -1, want: -9223372036854775806}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: -1, want: 9223372036854775806}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 0, want: -9223372036854775807}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 0, want: 9223372036854775807}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 1, want: -9223372036854775808}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 1, want: -9223372036854775808}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 4294967296, want: 9223372032559808513}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 4294967296, want: -9223372032559808513}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 9223372036854775806, want: 3}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 9223372036854775806, want: -3}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 9223372036854775807, want: 2}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 9223372036854775807, want: -2}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: -9223372036854775808, want: 9223372032559808512}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: -9223372036854775807, want: 9223372032559808511}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: -4294967296, want: 0}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: -1, want: -4294967295}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: -1, want: 4294967295}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 0, want: -4294967296}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 0, want: 4294967296}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 1, want: -4294967297}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 1, want: 4294967297}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 4294967296, want: -8589934592}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 4294967296, want: 8589934592}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 9223372036854775806, want: 9223372032559808514}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 9223372036854775806, want: -9223372032559808514}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 9223372036854775807, want: 9223372032559808513}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 9223372036854775807, want: -9223372032559808513}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: -9223372036854775807, want: 9223372036854775806}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: -9223372036854775807, want: -9223372036854775806}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: -4294967296, want: 4294967295}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: -4294967296, want: -4294967295}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: -1, want: 0}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: -1, want: 0}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 0, want: -1}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 0, want: 1}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 1, want: -2}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 1, want: 2}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 4294967296, want: -4294967297}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 4294967296, want: 4294967297}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 9223372036854775806, want: -9223372036854775807}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: -9223372036854775807, want: 9223372036854775807}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: -4294967296, want: 4294967296}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: -4294967296, want: -4294967296}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: -1, want: 1}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: -1, want: -1}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 0, want: 0}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 0, want: 0}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 1, want: -1}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 1, want: 1}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 4294967296, want: -4294967296}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 4294967296, want: 4294967296}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 9223372036854775806, want: -9223372036854775806}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 9223372036854775807, want: -9223372036854775807}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: -4294967296, want: 4294967297}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: -4294967296, want: -4294967297}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: -1, want: 2}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: -1, want: -2}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 0, want: 1}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 0, want: -1}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 1, want: 0}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 1, want: 0}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 4294967296, want: -4294967295}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 4294967296, want: 4294967295}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 9223372036854775806, want: -9223372036854775805}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 9223372036854775806, want: 9223372036854775805}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 9223372036854775807, want: -9223372036854775806}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: -9223372036854775808, want: 9223372032559808512}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: -9223372036854775807, want: -9223372032559808513}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: -9223372036854775807, want: 9223372032559808513}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: -4294967296, want: 8589934592}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: -4294967296, want: -8589934592}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: -1, want: 4294967297}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: -1, want: -4294967297}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 0, want: 4294967296}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 0, want: -4294967296}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 1, want: 4294967295}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 1, want: -4294967295}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 4294967296, want: 0}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 9223372036854775806, want: -9223372032559808510}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 9223372036854775806, want: 9223372032559808510}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 9223372036854775807, want: -9223372032559808511}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 9223372036854775807, want: 9223372032559808511}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: -9223372036854775808, want: -2}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: -9223372036854775808, want: 2}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: -9223372036854775807, want: -3}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: -9223372036854775807, want: 3}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: -4294967296, want: -9223372032559808514}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: -4294967296, want: 9223372032559808514}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: -1, want: 9223372036854775807}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: -1, want: -9223372036854775807}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 0, want: 9223372036854775806}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 0, want: -9223372036854775806}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 1, want: 9223372036854775805}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 1, want: -9223372036854775805}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 4294967296, want: 9223372032559808510}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 4294967296, want: -9223372032559808510}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 9223372036854775806, want: 0}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 9223372036854775806, want: 0}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 9223372036854775807, want: -1}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 9223372036854775807, want: 1}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: -9223372036854775808, want: -1}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: -9223372036854775808, want: 1}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: -9223372036854775807, want: -2}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: -9223372036854775807, want: 2}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: -4294967296, want: -9223372032559808513}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: -4294967296, want: 9223372032559808513}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: -1, want: -9223372036854775808}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: -1, want: -9223372036854775808}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 0, want: 9223372036854775807}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 0, want: -9223372036854775807}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 1, want: 9223372036854775806}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 1, want: -9223372036854775806}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 4294967296, want: 9223372032559808511}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 4294967296, want: -9223372032559808511}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 9223372036854775806, want: 1}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 9223372036854775806, want: -1}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 9223372036854775807, want: 0}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 9223372036854775807, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: -9223372036854775808, want: 1}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: -9223372036854775808, want: 1}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: -9223372036854775807, want: 1}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: -9223372036854775807, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: -4294967296, want: 2147483648}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: -4294967296, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: -1, want: -9223372036854775808}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: -1, want: 0}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 0, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: 1, want: -9223372036854775808}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 1, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: 4294967296, want: -2147483648}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 4294967296, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: 9223372036854775806, want: -1}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 9223372036854775806, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 9223372036854775807, want: 0}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: -9223372036854775808, want: 1}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: -9223372036854775807, want: 1}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: -9223372036854775807, want: 1}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: -4294967296, want: 2147483647}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: -4294967296, want: 0}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: -1, want: 9223372036854775807}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: -1, want: 0}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 0, want: 0}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: 1, want: -9223372036854775807}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 1, want: 0}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: 4294967296, want: -2147483647}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 4294967296, want: 0}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 9223372036854775806, want: 0}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: 9223372036854775807, want: -1}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 9223372036854775807, want: -1}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: -9223372036854775808, want: 2147483648}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: -9223372036854775807, want: 0}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: -9223372036854775807, want: 2147483647}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: -4294967296, want: 1}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: -4294967296, want: 1}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: -1, want: 4294967296}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: -1, want: 0}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 0, want: 0}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: 1, want: -4294967296}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 1, want: 0}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: 4294967296, want: -1}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 4294967296, want: -1}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: 9223372036854775806, want: 0}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 9223372036854775806, want: -2147483647}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: 9223372036854775807, want: 0}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 9223372036854775807, want: -2147483647}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: -9223372036854775807, want: 0}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: -9223372036854775807, want: 9223372036854775807}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: -4294967296, want: 0}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: -4294967296, want: 4294967296}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: -1, want: 1}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: -1, want: 1}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 0, want: 0}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: 1, want: -1}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 1, want: -1}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: 4294967296, want: 0}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 4294967296, want: -4294967296}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: 9223372036854775806, want: 0}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 9223372036854775806, want: -9223372036854775806}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: 9223372036854775807, want: 0}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 9223372036854775807, want: -9223372036854775807}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: -9223372036854775807, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: -4294967296, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: -1, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: 1, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: 4294967296, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: 9223372036854775806, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: 9223372036854775807, want: 0}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: -9223372036854775807, want: 0}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: -4294967296, want: 0}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: -4294967296, want: -4294967296}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: -1, want: -1}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: -1, want: -1}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 0, want: 0}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: 1, want: 1}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 1, want: 1}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: 4294967296, want: 0}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 4294967296, want: 4294967296}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: 9223372036854775806, want: 0}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: 9223372036854775807, want: 0}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: -9223372036854775808, want: -2147483648}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: -9223372036854775807, want: 0}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: -9223372036854775807, want: -2147483647}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: -4294967296, want: -1}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: -4294967296, want: -1}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: -1, want: -4294967296}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: -1, want: 0}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 0, want: 0}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: 1, want: 4294967296}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 1, want: 0}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: 4294967296, want: 1}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 4294967296, want: 1}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: 9223372036854775806, want: 0}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 9223372036854775806, want: 2147483647}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: 9223372036854775807, want: 0}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 9223372036854775807, want: 2147483647}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: -9223372036854775808, want: -1}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: -9223372036854775807, want: 0}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: -9223372036854775807, want: -1}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: -4294967296, want: -2147483647}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: -4294967296, want: 0}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: -1, want: -9223372036854775806}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: -1, want: 0}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 0, want: 0}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: 1, want: 9223372036854775806}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 1, want: 0}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: 4294967296, want: 2147483647}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 4294967296, want: 0}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: 9223372036854775806, want: 1}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 9223372036854775806, want: 1}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: 9223372036854775807, want: 0}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 9223372036854775807, want: 1}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: -9223372036854775807, want: -1}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: -9223372036854775807, want: -1}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: -4294967296, want: -2147483647}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: -4294967296, want: 0}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: -1, want: -9223372036854775807}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: -1, want: 0}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 0, want: 0}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: 1, want: 9223372036854775807}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 1, want: 0}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: 4294967296, want: 2147483647}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 4294967296, want: 0}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: 9223372036854775806, want: 1}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 9223372036854775806, want: 0}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: 9223372036854775807, want: 1}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 9223372036854775807, want: 1}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: -4294967296, want: 0}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: -4294967296, want: 0}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: -1, want: -9223372036854775808}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: -1, want: -9223372036854775808}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 0, want: 0}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 0, want: 0}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 1, want: -9223372036854775808}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 1, want: -9223372036854775808}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 4294967296, want: 0}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 4294967296, want: 0}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 9223372036854775806, want: 0}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 9223372036854775806, want: 0}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: -9223372036854775807, want: 1}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: -9223372036854775807, want: 1}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: -4294967296, want: -4294967296}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: -4294967296, want: -4294967296}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: -1, want: 9223372036854775807}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: -1, want: 9223372036854775807}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 0, want: 0}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 0, want: 0}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 1, want: -9223372036854775807}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 1, want: -9223372036854775807}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 4294967296, want: 4294967296}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 4294967296, want: 4294967296}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 9223372036854775807, want: -1}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 9223372036854775807, want: -1}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: -9223372036854775808, want: 0}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: -9223372036854775807, want: -4294967296}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: -9223372036854775807, want: -4294967296}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: -4294967296, want: 0}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: -1, want: 4294967296}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: -1, want: 4294967296}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 0, want: 0}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 0, want: 0}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 1, want: -4294967296}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 1, want: -4294967296}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 4294967296, want: 0}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 9223372036854775806, want: 8589934592}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 9223372036854775806, want: 8589934592}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 9223372036854775807, want: 4294967296}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 9223372036854775807, want: 4294967296}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: -9223372036854775807, want: 9223372036854775807}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: -9223372036854775807, want: 9223372036854775807}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: -4294967296, want: 4294967296}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: -4294967296, want: 4294967296}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: -1, want: 1}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: -1, want: 1}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 0, want: 0}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 0, want: 0}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 1, want: -1}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 1, want: -1}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 4294967296, want: -4294967296}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 4294967296, want: -4294967296}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 9223372036854775806, want: -9223372036854775806}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 9223372036854775806, want: -9223372036854775806}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 9223372036854775807, want: -9223372036854775807}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 9223372036854775807, want: -9223372036854775807}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: -9223372036854775808, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: -9223372036854775807, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: -9223372036854775807, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: -4294967296, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: -4294967296, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: -1, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: -1, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 0, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 0, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 1, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 1, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 4294967296, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 4294967296, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 9223372036854775806, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 9223372036854775806, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 9223372036854775807, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 9223372036854775807, want: 0}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: -4294967296, want: -4294967296}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: -4294967296, want: -4294967296}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: -1, want: -1}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: -1, want: -1}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 0, want: 0}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 0, want: 0}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 1, want: 1}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 1, want: 1}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 4294967296, want: 4294967296}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 4294967296, want: 4294967296}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: -9223372036854775808, want: 0}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: -9223372036854775807, want: 4294967296}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: -9223372036854775807, want: 4294967296}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: -4294967296, want: 0}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: -1, want: -4294967296}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: -1, want: -4294967296}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 0, want: 0}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 0, want: 0}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 1, want: 4294967296}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 1, want: 4294967296}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 4294967296, want: 0}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 9223372036854775806, want: -8589934592}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 9223372036854775806, want: -8589934592}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 9223372036854775807, want: -4294967296}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 9223372036854775807, want: -4294967296}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: -9223372036854775808, want: 0}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: -9223372036854775807, want: 9223372036854775806}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: -9223372036854775807, want: 9223372036854775806}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: -4294967296, want: 8589934592}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: -4294967296, want: 8589934592}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: -1, want: -9223372036854775806}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: -1, want: -9223372036854775806}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 0, want: 0}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 0, want: 0}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 1, want: 9223372036854775806}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 1, want: 9223372036854775806}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 4294967296, want: -8589934592}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 4294967296, want: -8589934592}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 9223372036854775806, want: 4}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 9223372036854775806, want: 4}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 9223372036854775807, want: -9223372036854775806}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 9223372036854775807, want: -9223372036854775806}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: -9223372036854775807, want: -1}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: -9223372036854775807, want: -1}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: -4294967296, want: 4294967296}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: -4294967296, want: 4294967296}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: -1, want: -9223372036854775807}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: -1, want: -9223372036854775807}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 0, want: 0}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 0, want: 0}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 1, want: 9223372036854775807}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 1, want: 9223372036854775807}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 4294967296, want: -4294967296}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 4294967296, want: -4294967296}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 9223372036854775806, want: -9223372036854775806}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 9223372036854775806, want: -9223372036854775806}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 9223372036854775807, want: 1}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 9223372036854775807, want: 1}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: -9223372036854775807, want: -1}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: -4294967296, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: -4294967296, want: -4294967296}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: -1, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: -1, want: -1}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 0, want: 0}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: 1, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 1, want: 1}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: 4294967296, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 4294967296, want: 4294967296}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: 9223372036854775806, want: -2}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: -9223372036854775807, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: -9223372036854775807, want: 0}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: -4294967296, want: -4294967295}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: -4294967296, want: -4294967296}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: -1, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: -1, want: -1}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 0, want: 0}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: 1, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 1, want: 1}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: 4294967296, want: -4294967295}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 4294967296, want: 4294967296}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: 9223372036854775807, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 9223372036854775807, want: 0}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: -9223372036854775808, want: -4294967296}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: -9223372036854775808, want: 0}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: -9223372036854775807, want: -4294967296}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: -9223372036854775807, want: -4294967295}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: -4294967296, want: 0}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: -1, want: 0}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: -1, want: -1}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 0, want: 0}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: 1, want: 0}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 1, want: 1}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 4294967296, want: 0}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: 9223372036854775806, want: -4294967296}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 9223372036854775806, want: 4294967294}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: 9223372036854775807, want: -4294967296}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 9223372036854775807, want: 4294967295}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: -9223372036854775808, want: -1}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: -9223372036854775808, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: -9223372036854775807, want: -1}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: -9223372036854775807, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: -4294967296, want: -1}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: -4294967296, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: -1, want: 0}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: -1, want: 0}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 0, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: 1, want: 0}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 1, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: 4294967296, want: -1}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 4294967296, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: 9223372036854775806, want: -1}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 9223372036854775806, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: 9223372036854775807, want: -1}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 9223372036854775807, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: -9223372036854775807, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: -4294967296, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: -1, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: 1, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: 4294967296, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: 9223372036854775806, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: 9223372036854775807, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: -9223372036854775808, want: 1}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: -9223372036854775808, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: -9223372036854775807, want: 1}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: -9223372036854775807, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: -4294967296, want: 1}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: -4294967296, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: -1, want: 0}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: -1, want: 0}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 0, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: 1, want: 0}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 1, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: 4294967296, want: 1}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 4294967296, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: 9223372036854775806, want: 1}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 9223372036854775806, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: 9223372036854775807, want: 1}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 9223372036854775807, want: 0}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: -9223372036854775808, want: 4294967296}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: -9223372036854775808, want: 0}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: -9223372036854775807, want: 4294967296}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: -9223372036854775807, want: -4294967295}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: -4294967296, want: 0}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: -1, want: 0}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: -1, want: -1}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 0, want: 0}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: 1, want: 0}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 1, want: 1}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 4294967296, want: 0}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: 9223372036854775806, want: 4294967296}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 9223372036854775806, want: 4294967294}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: 9223372036854775807, want: 4294967296}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 9223372036854775807, want: 4294967295}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: -9223372036854775808, want: 9223372036854775806}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: -9223372036854775808, want: -2}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: -9223372036854775807, want: 9223372036854775806}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: -9223372036854775807, want: -1}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: -4294967296, want: 4294967294}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: -4294967296, want: -4294967296}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: -1, want: 0}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: -1, want: -1}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 0, want: 0}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: 1, want: 0}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 1, want: 1}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: 4294967296, want: 4294967294}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 4294967296, want: 4294967296}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: 9223372036854775806, want: 0}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 9223372036854775806, want: 0}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 9223372036854775807, want: 1}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: -9223372036854775807, want: 0}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: -9223372036854775807, want: 0}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: -4294967296, want: 4294967295}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: -4294967296, want: -4294967296}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: -1, want: 0}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: -1, want: -1}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 0, want: 0}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: 1, want: 0}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 1, want: 1}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: 4294967296, want: 4294967295}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 4294967296, want: 4294967296}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: 9223372036854775806, want: 1}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: 9223372036854775807, want: 0}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 9223372036854775807, want: 0}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: -4294967296, want: -9223372036854775808}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: -4294967296, want: -9223372036854775808}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: -1, want: -9223372036854775808}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: -1, want: -9223372036854775808}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 0, want: 0}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 0, want: 0}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 1, want: 0}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 1, want: 0}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 4294967296, want: 0}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 4294967296, want: 0}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 9223372036854775806, want: 0}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 9223372036854775806, want: 0}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 9223372036854775807, want: 0}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 9223372036854775807, want: 0}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: -4294967296, want: -9223372036854775808}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: -4294967296, want: -9223372036854775808}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: -1, want: -9223372036854775807}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: -1, want: -9223372036854775807}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 0, want: 0}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 0, want: 0}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 1, want: 1}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 1, want: 1}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 4294967296, want: 0}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 4294967296, want: 0}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 9223372036854775806, want: 0}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 9223372036854775806, want: 0}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 9223372036854775807, want: 1}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 9223372036854775807, want: 1}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: -4294967296, want: -4294967296}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: -4294967296, want: -4294967296}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: -1, want: -4294967296}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: -1, want: -4294967296}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 0, want: 0}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 0, want: 0}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 1, want: 0}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 1, want: 0}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 4294967296, want: 4294967296}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 4294967296, want: 4294967296}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 9223372036854775806, want: 9223372032559808512}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 9223372036854775806, want: 9223372032559808512}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 9223372036854775807, want: 9223372032559808512}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 9223372036854775807, want: 9223372032559808512}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: -4294967296, want: -4294967296}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: -4294967296, want: -4294967296}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: -1, want: -1}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: -1, want: -1}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 0, want: 0}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 0, want: 0}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 1, want: 1}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 1, want: 1}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 4294967296, want: 4294967296}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 4294967296, want: 4294967296}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: -9223372036854775808, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: -9223372036854775808, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: -9223372036854775807, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: -9223372036854775807, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: -4294967296, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: -4294967296, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: -1, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: -1, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 0, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 0, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 1, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 1, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 4294967296, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 4294967296, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 9223372036854775806, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 9223372036854775806, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 9223372036854775807, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 9223372036854775807, want: 0}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: -9223372036854775808, want: 0}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: -9223372036854775808, want: 0}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: -9223372036854775807, want: 1}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: -9223372036854775807, want: 1}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: -4294967296, want: 0}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: -4294967296, want: 0}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: -1, want: 1}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: -1, want: 1}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 0, want: 0}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 0, want: 0}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 1, want: 1}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 1, want: 1}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 4294967296, want: 0}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 4294967296, want: 0}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 9223372036854775806, want: 0}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 9223372036854775806, want: 0}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 9223372036854775807, want: 1}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 9223372036854775807, want: 1}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: -9223372036854775808, want: 0}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: -9223372036854775808, want: 0}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: -9223372036854775807, want: 0}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: -9223372036854775807, want: 0}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: -4294967296, want: 4294967296}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: -4294967296, want: 4294967296}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: -1, want: 4294967296}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: -1, want: 4294967296}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 0, want: 0}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 0, want: 0}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 1, want: 0}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 1, want: 0}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 4294967296, want: 4294967296}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 4294967296, want: 4294967296}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 9223372036854775806, want: 4294967296}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 9223372036854775806, want: 4294967296}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 9223372036854775807, want: 4294967296}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 9223372036854775807, want: 4294967296}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: -9223372036854775808, want: 0}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: -9223372036854775808, want: 0}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: -9223372036854775807, want: 0}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: -9223372036854775807, want: 0}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: -4294967296, want: 9223372032559808512}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: -4294967296, want: 9223372032559808512}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: -1, want: 9223372036854775806}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: -1, want: 9223372036854775806}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 0, want: 0}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 0, want: 0}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 1, want: 0}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 1, want: 0}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 4294967296, want: 4294967296}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 4294967296, want: 4294967296}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: -9223372036854775808, want: 0}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: -9223372036854775808, want: 0}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: -9223372036854775807, want: 1}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: -9223372036854775807, want: 1}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: -4294967296, want: 9223372032559808512}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: -4294967296, want: 9223372032559808512}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: -1, want: 9223372036854775807}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: -1, want: 9223372036854775807}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 0, want: 0}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 0, want: 0}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 1, want: 1}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 1, want: 1}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 4294967296, want: 4294967296}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 4294967296, want: 4294967296}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: -4294967296, want: -4294967296}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: -4294967296, want: -4294967296}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: -1, want: -1}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: -1, want: -1}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 0, want: -9223372036854775808}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 0, want: -9223372036854775808}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 1, want: -9223372036854775807}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 1, want: -9223372036854775807}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 4294967296, want: -9223372032559808512}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 4294967296, want: -9223372032559808512}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 9223372036854775806, want: -2}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 9223372036854775806, want: -2}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 9223372036854775807, want: -1}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: -4294967296, want: -4294967295}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: -4294967296, want: -4294967295}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: -1, want: -1}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: -1, want: -1}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 0, want: -9223372036854775807}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 0, want: -9223372036854775807}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 1, want: -9223372036854775807}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 1, want: -9223372036854775807}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 4294967296, want: -9223372032559808511}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 4294967296, want: -9223372032559808511}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 9223372036854775806, want: -1}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 9223372036854775807, want: -1}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 9223372036854775807, want: -1}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: -9223372036854775808, want: -4294967296}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: -9223372036854775808, want: -4294967296}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: -9223372036854775807, want: -4294967295}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: -9223372036854775807, want: -4294967295}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: -4294967296, want: -4294967296}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: -4294967296, want: -4294967296}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: -1, want: -1}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: -1, want: -1}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 0, want: -4294967296}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 0, want: -4294967296}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 1, want: -4294967295}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 1, want: -4294967295}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 4294967296, want: -4294967296}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 4294967296, want: -4294967296}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 9223372036854775806, want: -2}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 9223372036854775806, want: -2}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 9223372036854775807, want: -1}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 9223372036854775807, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: -9223372036854775808, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: -9223372036854775808, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: -9223372036854775807, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: -9223372036854775807, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: -4294967296, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: -4294967296, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: -1, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: -1, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 0, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 0, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 1, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 1, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 4294967296, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 4294967296, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 9223372036854775806, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 9223372036854775806, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 9223372036854775807, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 9223372036854775807, want: -1}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: -4294967296, want: -4294967296}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: -4294967296, want: -4294967296}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: -1, want: -1}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: -1, want: -1}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 0, want: 0}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 0, want: 0}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 1, want: 1}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 1, want: 1}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 4294967296, want: 4294967296}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 4294967296, want: 4294967296}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: -4294967296, want: -4294967295}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: -4294967296, want: -4294967295}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: -1, want: -1}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: -1, want: -1}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 0, want: 1}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 0, want: 1}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 1, want: 1}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 1, want: 1}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 4294967296, want: 4294967297}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 4294967296, want: 4294967297}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: -4294967296, want: -4294967296}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: -4294967296, want: -4294967296}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: -1, want: -1}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: -1, want: -1}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 0, want: 4294967296}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 0, want: 4294967296}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 1, want: 4294967297}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 1, want: 4294967297}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 4294967296, want: 4294967296}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 4294967296, want: 4294967296}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: -9223372036854775808, want: -2}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: -9223372036854775808, want: -2}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: -9223372036854775807, want: -1}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: -9223372036854775807, want: -1}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: -4294967296, want: -2}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: -4294967296, want: -2}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: -1, want: -1}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: -1, want: -1}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 0, want: 9223372036854775806}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 0, want: 9223372036854775806}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 1, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 1, want: 9223372036854775807}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 4294967296, want: 9223372036854775806}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 4294967296, want: 9223372036854775806}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: -9223372036854775808, want: -1}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: -9223372036854775807, want: -1}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: -9223372036854775807, want: -1}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: -4294967296, want: -1}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: -4294967296, want: -1}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: -1, want: -1}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: -1, want: -1}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 0, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 0, want: 9223372036854775807}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 1, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 1, want: 9223372036854775807}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 4294967296, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 4294967296, want: 9223372036854775807}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: -9223372036854775807, want: 1}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: -9223372036854775807, want: 1}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: -4294967296, want: 9223372032559808512}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: -4294967296, want: 9223372032559808512}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: -1, want: 9223372036854775807}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: -1, want: 9223372036854775807}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 0, want: -9223372036854775808}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 0, want: -9223372036854775808}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 1, want: -9223372036854775807}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 1, want: -9223372036854775807}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 4294967296, want: -9223372032559808512}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 4294967296, want: -9223372032559808512}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 9223372036854775806, want: -2}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 9223372036854775806, want: -2}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 9223372036854775807, want: -1}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: -9223372036854775808, want: 1}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: -9223372036854775808, want: 1}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: -9223372036854775807, want: 0}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: -9223372036854775807, want: 0}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: -4294967296, want: 9223372032559808513}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: -4294967296, want: 9223372032559808513}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: -1, want: 9223372036854775806}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: -1, want: 9223372036854775806}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 0, want: -9223372036854775807}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 0, want: -9223372036854775807}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 1, want: -9223372036854775808}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 1, want: -9223372036854775808}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 4294967296, want: -9223372032559808511}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 4294967296, want: -9223372032559808511}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 9223372036854775806, want: -1}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 9223372036854775807, want: -2}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 9223372036854775807, want: -2}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: -9223372036854775808, want: 9223372032559808512}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: -9223372036854775808, want: 9223372032559808512}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: -9223372036854775807, want: 9223372032559808513}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: -9223372036854775807, want: 9223372032559808513}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: -4294967296, want: 0}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: -1, want: 4294967295}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: -1, want: 4294967295}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 0, want: -4294967296}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 0, want: -4294967296}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 1, want: -4294967295}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 1, want: -4294967295}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 4294967296, want: -8589934592}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 4294967296, want: -8589934592}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 9223372036854775806, want: -9223372032559808514}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 9223372036854775806, want: -9223372032559808514}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 9223372036854775807, want: -9223372032559808513}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 9223372036854775807, want: -9223372032559808513}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: -9223372036854775807, want: 9223372036854775806}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: -9223372036854775807, want: 9223372036854775806}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: -4294967296, want: 4294967295}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: -4294967296, want: 4294967295}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: -1, want: 0}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: -1, want: 0}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 0, want: -1}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 0, want: -1}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 1, want: -2}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 1, want: -2}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 4294967296, want: -4294967297}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 4294967296, want: -4294967297}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 9223372036854775806, want: -9223372036854775807}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 9223372036854775806, want: -9223372036854775807}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: -4294967296, want: -4294967296}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: -4294967296, want: -4294967296}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: -1, want: -1}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: -1, want: -1}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 0, want: 0}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 0, want: 0}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 1, want: 1}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 1, want: 1}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 4294967296, want: 4294967296}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 4294967296, want: 4294967296}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: -4294967296, want: -4294967295}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: -4294967296, want: -4294967295}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: -1, want: -2}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: -1, want: -2}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 0, want: 1}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 0, want: 1}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 1, want: 0}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 1, want: 0}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 4294967296, want: 4294967297}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 4294967296, want: 4294967297}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: -4294967296, want: -8589934592}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: -4294967296, want: -8589934592}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: -1, want: -4294967297}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: -1, want: -4294967297}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 0, want: 4294967296}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 0, want: 4294967296}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 1, want: 4294967297}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 1, want: 4294967297}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 4294967296, want: 0}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 9223372036854775806, want: 9223372032559808510}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 9223372036854775806, want: 9223372032559808510}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 9223372036854775807, want: 9223372032559808511}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 9223372036854775807, want: 9223372032559808511}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: -9223372036854775808, want: -2}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: -9223372036854775808, want: -2}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: -9223372036854775807, want: -1}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: -9223372036854775807, want: -1}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: -4294967296, want: -9223372032559808514}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: -4294967296, want: -9223372032559808514}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: -1, want: -9223372036854775807}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: -1, want: -9223372036854775807}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 0, want: 9223372036854775806}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 0, want: 9223372036854775806}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 1, want: 9223372036854775807}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 1, want: 9223372036854775807}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 4294967296, want: 9223372032559808510}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 4294967296, want: 9223372032559808510}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 9223372036854775806, want: 0}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 9223372036854775806, want: 0}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 9223372036854775807, want: 1}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 9223372036854775807, want: 1}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: -9223372036854775808, want: -1}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: -9223372036854775807, want: -2}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: -9223372036854775807, want: -2}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: -4294967296, want: -9223372032559808513}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: -4294967296, want: -9223372032559808513}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: -1, want: -9223372036854775808}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: -1, want: -9223372036854775808}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 0, want: 9223372036854775807}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 0, want: 9223372036854775807}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 1, want: 9223372036854775806}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 1, want: 9223372036854775806}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 4294967296, want: 9223372032559808511}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 4294967296, want: 9223372032559808511}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 9223372036854775806, want: 1}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 9223372036854775806, want: 1}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 9223372036854775807, want: 0}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 9223372036854775807, want: 0}} type test_uint32 struct { fn func(uint32) uint32 fnname string in uint32 want uint32 } var tests_uint32 = []test_uint32{ test_uint32{fn: add_0_uint32, fnname: "add_0_uint32", in: 0, want: 0}, test_uint32{fn: add_uint32_0, fnname: "add_uint32_0", in: 0, want: 0}, test_uint32{fn: add_0_uint32, fnname: "add_0_uint32", in: 1, want: 1}, test_uint32{fn: add_uint32_0, fnname: "add_uint32_0", in: 1, want: 1}, test_uint32{fn: add_0_uint32, fnname: "add_0_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: add_uint32_0, fnname: "add_uint32_0", in: 4294967295, want: 4294967295}, test_uint32{fn: add_1_uint32, fnname: "add_1_uint32", in: 0, want: 1}, test_uint32{fn: add_uint32_1, fnname: "add_uint32_1", in: 0, want: 1}, test_uint32{fn: add_1_uint32, fnname: "add_1_uint32", in: 1, want: 2}, test_uint32{fn: add_uint32_1, fnname: "add_uint32_1", in: 1, want: 2}, test_uint32{fn: add_1_uint32, fnname: "add_1_uint32", in: 4294967295, want: 0}, test_uint32{fn: add_uint32_1, fnname: "add_uint32_1", in: 4294967295, want: 0}, test_uint32{fn: add_4294967295_uint32, fnname: "add_4294967295_uint32", in: 0, want: 4294967295}, test_uint32{fn: add_uint32_4294967295, fnname: "add_uint32_4294967295", in: 0, want: 4294967295}, test_uint32{fn: add_4294967295_uint32, fnname: "add_4294967295_uint32", in: 1, want: 0}, test_uint32{fn: add_uint32_4294967295, fnname: "add_uint32_4294967295", in: 1, want: 0}, test_uint32{fn: add_4294967295_uint32, fnname: "add_4294967295_uint32", in: 4294967295, want: 4294967294}, test_uint32{fn: add_uint32_4294967295, fnname: "add_uint32_4294967295", in: 4294967295, want: 4294967294}, test_uint32{fn: sub_0_uint32, fnname: "sub_0_uint32", in: 0, want: 0}, test_uint32{fn: sub_uint32_0, fnname: "sub_uint32_0", in: 0, want: 0}, test_uint32{fn: sub_0_uint32, fnname: "sub_0_uint32", in: 1, want: 4294967295}, test_uint32{fn: sub_uint32_0, fnname: "sub_uint32_0", in: 1, want: 1}, test_uint32{fn: sub_0_uint32, fnname: "sub_0_uint32", in: 4294967295, want: 1}, test_uint32{fn: sub_uint32_0, fnname: "sub_uint32_0", in: 4294967295, want: 4294967295}, test_uint32{fn: sub_1_uint32, fnname: "sub_1_uint32", in: 0, want: 1}, test_uint32{fn: sub_uint32_1, fnname: "sub_uint32_1", in: 0, want: 4294967295}, test_uint32{fn: sub_1_uint32, fnname: "sub_1_uint32", in: 1, want: 0}, test_uint32{fn: sub_uint32_1, fnname: "sub_uint32_1", in: 1, want: 0}, test_uint32{fn: sub_1_uint32, fnname: "sub_1_uint32", in: 4294967295, want: 2}, test_uint32{fn: sub_uint32_1, fnname: "sub_uint32_1", in: 4294967295, want: 4294967294}, test_uint32{fn: sub_4294967295_uint32, fnname: "sub_4294967295_uint32", in: 0, want: 4294967295}, test_uint32{fn: sub_uint32_4294967295, fnname: "sub_uint32_4294967295", in: 0, want: 1}, test_uint32{fn: sub_4294967295_uint32, fnname: "sub_4294967295_uint32", in: 1, want: 4294967294}, test_uint32{fn: sub_uint32_4294967295, fnname: "sub_uint32_4294967295", in: 1, want: 2}, test_uint32{fn: sub_4294967295_uint32, fnname: "sub_4294967295_uint32", in: 4294967295, want: 0}, test_uint32{fn: sub_uint32_4294967295, fnname: "sub_uint32_4294967295", in: 4294967295, want: 0}, test_uint32{fn: div_0_uint32, fnname: "div_0_uint32", in: 1, want: 0}, test_uint32{fn: div_0_uint32, fnname: "div_0_uint32", in: 4294967295, want: 0}, test_uint32{fn: div_uint32_1, fnname: "div_uint32_1", in: 0, want: 0}, test_uint32{fn: div_1_uint32, fnname: "div_1_uint32", in: 1, want: 1}, test_uint32{fn: div_uint32_1, fnname: "div_uint32_1", in: 1, want: 1}, test_uint32{fn: div_1_uint32, fnname: "div_1_uint32", in: 4294967295, want: 0}, test_uint32{fn: div_uint32_1, fnname: "div_uint32_1", in: 4294967295, want: 4294967295}, test_uint32{fn: div_uint32_4294967295, fnname: "div_uint32_4294967295", in: 0, want: 0}, test_uint32{fn: div_4294967295_uint32, fnname: "div_4294967295_uint32", in: 1, want: 4294967295}, test_uint32{fn: div_uint32_4294967295, fnname: "div_uint32_4294967295", in: 1, want: 0}, test_uint32{fn: div_4294967295_uint32, fnname: "div_4294967295_uint32", in: 4294967295, want: 1}, test_uint32{fn: div_uint32_4294967295, fnname: "div_uint32_4294967295", in: 4294967295, want: 1}, test_uint32{fn: mul_0_uint32, fnname: "mul_0_uint32", in: 0, want: 0}, test_uint32{fn: mul_uint32_0, fnname: "mul_uint32_0", in: 0, want: 0}, test_uint32{fn: mul_0_uint32, fnname: "mul_0_uint32", in: 1, want: 0}, test_uint32{fn: mul_uint32_0, fnname: "mul_uint32_0", in: 1, want: 0}, test_uint32{fn: mul_0_uint32, fnname: "mul_0_uint32", in: 4294967295, want: 0}, test_uint32{fn: mul_uint32_0, fnname: "mul_uint32_0", in: 4294967295, want: 0}, test_uint32{fn: mul_1_uint32, fnname: "mul_1_uint32", in: 0, want: 0}, test_uint32{fn: mul_uint32_1, fnname: "mul_uint32_1", in: 0, want: 0}, test_uint32{fn: mul_1_uint32, fnname: "mul_1_uint32", in: 1, want: 1}, test_uint32{fn: mul_uint32_1, fnname: "mul_uint32_1", in: 1, want: 1}, test_uint32{fn: mul_1_uint32, fnname: "mul_1_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: mul_uint32_1, fnname: "mul_uint32_1", in: 4294967295, want: 4294967295}, test_uint32{fn: mul_4294967295_uint32, fnname: "mul_4294967295_uint32", in: 0, want: 0}, test_uint32{fn: mul_uint32_4294967295, fnname: "mul_uint32_4294967295", in: 0, want: 0}, test_uint32{fn: mul_4294967295_uint32, fnname: "mul_4294967295_uint32", in: 1, want: 4294967295}, test_uint32{fn: mul_uint32_4294967295, fnname: "mul_uint32_4294967295", in: 1, want: 4294967295}, test_uint32{fn: mul_4294967295_uint32, fnname: "mul_4294967295_uint32", in: 4294967295, want: 1}, test_uint32{fn: mul_uint32_4294967295, fnname: "mul_uint32_4294967295", in: 4294967295, want: 1}, test_uint32{fn: lsh_0_uint32, fnname: "lsh_0_uint32", in: 0, want: 0}, test_uint32{fn: lsh_uint32_0, fnname: "lsh_uint32_0", in: 0, want: 0}, test_uint32{fn: lsh_0_uint32, fnname: "lsh_0_uint32", in: 1, want: 0}, test_uint32{fn: lsh_uint32_0, fnname: "lsh_uint32_0", in: 1, want: 1}, test_uint32{fn: lsh_0_uint32, fnname: "lsh_0_uint32", in: 4294967295, want: 0}, test_uint32{fn: lsh_uint32_0, fnname: "lsh_uint32_0", in: 4294967295, want: 4294967295}, test_uint32{fn: lsh_1_uint32, fnname: "lsh_1_uint32", in: 0, want: 1}, test_uint32{fn: lsh_uint32_1, fnname: "lsh_uint32_1", in: 0, want: 0}, test_uint32{fn: lsh_1_uint32, fnname: "lsh_1_uint32", in: 1, want: 2}, test_uint32{fn: lsh_uint32_1, fnname: "lsh_uint32_1", in: 1, want: 2}, test_uint32{fn: lsh_1_uint32, fnname: "lsh_1_uint32", in: 4294967295, want: 0}, test_uint32{fn: lsh_uint32_1, fnname: "lsh_uint32_1", in: 4294967295, want: 4294967294}, test_uint32{fn: lsh_4294967295_uint32, fnname: "lsh_4294967295_uint32", in: 0, want: 4294967295}, test_uint32{fn: lsh_uint32_4294967295, fnname: "lsh_uint32_4294967295", in: 0, want: 0}, test_uint32{fn: lsh_4294967295_uint32, fnname: "lsh_4294967295_uint32", in: 1, want: 4294967294}, test_uint32{fn: lsh_uint32_4294967295, fnname: "lsh_uint32_4294967295", in: 1, want: 0}, test_uint32{fn: lsh_4294967295_uint32, fnname: "lsh_4294967295_uint32", in: 4294967295, want: 0}, test_uint32{fn: lsh_uint32_4294967295, fnname: "lsh_uint32_4294967295", in: 4294967295, want: 0}, test_uint32{fn: rsh_0_uint32, fnname: "rsh_0_uint32", in: 0, want: 0}, test_uint32{fn: rsh_uint32_0, fnname: "rsh_uint32_0", in: 0, want: 0}, test_uint32{fn: rsh_0_uint32, fnname: "rsh_0_uint32", in: 1, want: 0}, test_uint32{fn: rsh_uint32_0, fnname: "rsh_uint32_0", in: 1, want: 1}, test_uint32{fn: rsh_0_uint32, fnname: "rsh_0_uint32", in: 4294967295, want: 0}, test_uint32{fn: rsh_uint32_0, fnname: "rsh_uint32_0", in: 4294967295, want: 4294967295}, test_uint32{fn: rsh_1_uint32, fnname: "rsh_1_uint32", in: 0, want: 1}, test_uint32{fn: rsh_uint32_1, fnname: "rsh_uint32_1", in: 0, want: 0}, test_uint32{fn: rsh_1_uint32, fnname: "rsh_1_uint32", in: 1, want: 0}, test_uint32{fn: rsh_uint32_1, fnname: "rsh_uint32_1", in: 1, want: 0}, test_uint32{fn: rsh_1_uint32, fnname: "rsh_1_uint32", in: 4294967295, want: 0}, test_uint32{fn: rsh_uint32_1, fnname: "rsh_uint32_1", in: 4294967295, want: 2147483647}, test_uint32{fn: rsh_4294967295_uint32, fnname: "rsh_4294967295_uint32", in: 0, want: 4294967295}, test_uint32{fn: rsh_uint32_4294967295, fnname: "rsh_uint32_4294967295", in: 0, want: 0}, test_uint32{fn: rsh_4294967295_uint32, fnname: "rsh_4294967295_uint32", in: 1, want: 2147483647}, test_uint32{fn: rsh_uint32_4294967295, fnname: "rsh_uint32_4294967295", in: 1, want: 0}, test_uint32{fn: rsh_4294967295_uint32, fnname: "rsh_4294967295_uint32", in: 4294967295, want: 0}, test_uint32{fn: rsh_uint32_4294967295, fnname: "rsh_uint32_4294967295", in: 4294967295, want: 0}, test_uint32{fn: mod_0_uint32, fnname: "mod_0_uint32", in: 1, want: 0}, test_uint32{fn: mod_0_uint32, fnname: "mod_0_uint32", in: 4294967295, want: 0}, test_uint32{fn: mod_uint32_1, fnname: "mod_uint32_1", in: 0, want: 0}, test_uint32{fn: mod_1_uint32, fnname: "mod_1_uint32", in: 1, want: 0}, test_uint32{fn: mod_uint32_1, fnname: "mod_uint32_1", in: 1, want: 0}, test_uint32{fn: mod_1_uint32, fnname: "mod_1_uint32", in: 4294967295, want: 1}, test_uint32{fn: mod_uint32_1, fnname: "mod_uint32_1", in: 4294967295, want: 0}, test_uint32{fn: mod_uint32_4294967295, fnname: "mod_uint32_4294967295", in: 0, want: 0}, test_uint32{fn: mod_4294967295_uint32, fnname: "mod_4294967295_uint32", in: 1, want: 0}, test_uint32{fn: mod_uint32_4294967295, fnname: "mod_uint32_4294967295", in: 1, want: 1}, test_uint32{fn: mod_4294967295_uint32, fnname: "mod_4294967295_uint32", in: 4294967295, want: 0}, test_uint32{fn: mod_uint32_4294967295, fnname: "mod_uint32_4294967295", in: 4294967295, want: 0}, test_uint32{fn: and_0_uint32, fnname: "and_0_uint32", in: 0, want: 0}, test_uint32{fn: and_uint32_0, fnname: "and_uint32_0", in: 0, want: 0}, test_uint32{fn: and_0_uint32, fnname: "and_0_uint32", in: 1, want: 0}, test_uint32{fn: and_uint32_0, fnname: "and_uint32_0", in: 1, want: 0}, test_uint32{fn: and_0_uint32, fnname: "and_0_uint32", in: 4294967295, want: 0}, test_uint32{fn: and_uint32_0, fnname: "and_uint32_0", in: 4294967295, want: 0}, test_uint32{fn: and_1_uint32, fnname: "and_1_uint32", in: 0, want: 0}, test_uint32{fn: and_uint32_1, fnname: "and_uint32_1", in: 0, want: 0}, test_uint32{fn: and_1_uint32, fnname: "and_1_uint32", in: 1, want: 1}, test_uint32{fn: and_uint32_1, fnname: "and_uint32_1", in: 1, want: 1}, test_uint32{fn: and_1_uint32, fnname: "and_1_uint32", in: 4294967295, want: 1}, test_uint32{fn: and_uint32_1, fnname: "and_uint32_1", in: 4294967295, want: 1}, test_uint32{fn: and_4294967295_uint32, fnname: "and_4294967295_uint32", in: 0, want: 0}, test_uint32{fn: and_uint32_4294967295, fnname: "and_uint32_4294967295", in: 0, want: 0}, test_uint32{fn: and_4294967295_uint32, fnname: "and_4294967295_uint32", in: 1, want: 1}, test_uint32{fn: and_uint32_4294967295, fnname: "and_uint32_4294967295", in: 1, want: 1}, test_uint32{fn: and_4294967295_uint32, fnname: "and_4294967295_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: and_uint32_4294967295, fnname: "and_uint32_4294967295", in: 4294967295, want: 4294967295}, test_uint32{fn: or_0_uint32, fnname: "or_0_uint32", in: 0, want: 0}, test_uint32{fn: or_uint32_0, fnname: "or_uint32_0", in: 0, want: 0}, test_uint32{fn: or_0_uint32, fnname: "or_0_uint32", in: 1, want: 1}, test_uint32{fn: or_uint32_0, fnname: "or_uint32_0", in: 1, want: 1}, test_uint32{fn: or_0_uint32, fnname: "or_0_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: or_uint32_0, fnname: "or_uint32_0", in: 4294967295, want: 4294967295}, test_uint32{fn: or_1_uint32, fnname: "or_1_uint32", in: 0, want: 1}, test_uint32{fn: or_uint32_1, fnname: "or_uint32_1", in: 0, want: 1}, test_uint32{fn: or_1_uint32, fnname: "or_1_uint32", in: 1, want: 1}, test_uint32{fn: or_uint32_1, fnname: "or_uint32_1", in: 1, want: 1}, test_uint32{fn: or_1_uint32, fnname: "or_1_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: or_uint32_1, fnname: "or_uint32_1", in: 4294967295, want: 4294967295}, test_uint32{fn: or_4294967295_uint32, fnname: "or_4294967295_uint32", in: 0, want: 4294967295}, test_uint32{fn: or_uint32_4294967295, fnname: "or_uint32_4294967295", in: 0, want: 4294967295}, test_uint32{fn: or_4294967295_uint32, fnname: "or_4294967295_uint32", in: 1, want: 4294967295}, test_uint32{fn: or_uint32_4294967295, fnname: "or_uint32_4294967295", in: 1, want: 4294967295}, test_uint32{fn: or_4294967295_uint32, fnname: "or_4294967295_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: or_uint32_4294967295, fnname: "or_uint32_4294967295", in: 4294967295, want: 4294967295}, test_uint32{fn: xor_0_uint32, fnname: "xor_0_uint32", in: 0, want: 0}, test_uint32{fn: xor_uint32_0, fnname: "xor_uint32_0", in: 0, want: 0}, test_uint32{fn: xor_0_uint32, fnname: "xor_0_uint32", in: 1, want: 1}, test_uint32{fn: xor_uint32_0, fnname: "xor_uint32_0", in: 1, want: 1}, test_uint32{fn: xor_0_uint32, fnname: "xor_0_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: xor_uint32_0, fnname: "xor_uint32_0", in: 4294967295, want: 4294967295}, test_uint32{fn: xor_1_uint32, fnname: "xor_1_uint32", in: 0, want: 1}, test_uint32{fn: xor_uint32_1, fnname: "xor_uint32_1", in: 0, want: 1}, test_uint32{fn: xor_1_uint32, fnname: "xor_1_uint32", in: 1, want: 0}, test_uint32{fn: xor_uint32_1, fnname: "xor_uint32_1", in: 1, want: 0}, test_uint32{fn: xor_1_uint32, fnname: "xor_1_uint32", in: 4294967295, want: 4294967294}, test_uint32{fn: xor_uint32_1, fnname: "xor_uint32_1", in: 4294967295, want: 4294967294}, test_uint32{fn: xor_4294967295_uint32, fnname: "xor_4294967295_uint32", in: 0, want: 4294967295}, test_uint32{fn: xor_uint32_4294967295, fnname: "xor_uint32_4294967295", in: 0, want: 4294967295}, test_uint32{fn: xor_4294967295_uint32, fnname: "xor_4294967295_uint32", in: 1, want: 4294967294}, test_uint32{fn: xor_uint32_4294967295, fnname: "xor_uint32_4294967295", in: 1, want: 4294967294}, test_uint32{fn: xor_4294967295_uint32, fnname: "xor_4294967295_uint32", in: 4294967295, want: 0}, test_uint32{fn: xor_uint32_4294967295, fnname: "xor_uint32_4294967295", in: 4294967295, want: 0}} type test_int32 struct { fn func(int32) int32 fnname string in int32 want int32 } var tests_int32 = []test_int32{ test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: -2147483648, want: 0}, test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: -2147483648, want: 0}, test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: -2147483647, want: 1}, test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: -2147483647, want: 1}, test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: -1, want: 2147483647}, test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: -1, want: 2147483647}, test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: 0, want: -2147483648}, test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: 0, want: -2147483648}, test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: 1, want: -2147483647}, test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: 1, want: -2147483647}, test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: 2147483647, want: -1}, test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: 2147483647, want: -1}, test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: -2147483648, want: 1}, test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: -2147483648, want: 1}, test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: -2147483647, want: 2}, test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: -2147483647, want: 2}, test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: -1, want: -2147483648}, test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: -1, want: -2147483648}, test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: 0, want: -2147483647}, test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: 0, want: -2147483647}, test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: 1, want: -2147483646}, test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: 1, want: -2147483646}, test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: 2147483647, want: 0}, test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: 2147483647, want: 0}, test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: -2147483648, want: 2147483647}, test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: -2147483648, want: 2147483647}, test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: -2147483647, want: -2147483648}, test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: -2147483647, want: -2147483648}, test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: -1, want: -2}, test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: -1, want: -2}, test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: 0, want: -1}, test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: 0, want: -1}, test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: 1, want: 0}, test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: 1, want: 0}, test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: 2147483647, want: 2147483646}, test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: 2147483647, want: 2147483646}, test_int32{fn: add_0_int32, fnname: "add_0_int32", in: -2147483648, want: -2147483648}, test_int32{fn: add_int32_0, fnname: "add_int32_0", in: -2147483648, want: -2147483648}, test_int32{fn: add_0_int32, fnname: "add_0_int32", in: -2147483647, want: -2147483647}, test_int32{fn: add_int32_0, fnname: "add_int32_0", in: -2147483647, want: -2147483647}, test_int32{fn: add_0_int32, fnname: "add_0_int32", in: -1, want: -1}, test_int32{fn: add_int32_0, fnname: "add_int32_0", in: -1, want: -1}, test_int32{fn: add_0_int32, fnname: "add_0_int32", in: 0, want: 0}, test_int32{fn: add_int32_0, fnname: "add_int32_0", in: 0, want: 0}, test_int32{fn: add_0_int32, fnname: "add_0_int32", in: 1, want: 1}, test_int32{fn: add_int32_0, fnname: "add_int32_0", in: 1, want: 1}, test_int32{fn: add_0_int32, fnname: "add_0_int32", in: 2147483647, want: 2147483647}, test_int32{fn: add_int32_0, fnname: "add_int32_0", in: 2147483647, want: 2147483647}, test_int32{fn: add_1_int32, fnname: "add_1_int32", in: -2147483648, want: -2147483647}, test_int32{fn: add_int32_1, fnname: "add_int32_1", in: -2147483648, want: -2147483647}, test_int32{fn: add_1_int32, fnname: "add_1_int32", in: -2147483647, want: -2147483646}, test_int32{fn: add_int32_1, fnname: "add_int32_1", in: -2147483647, want: -2147483646}, test_int32{fn: add_1_int32, fnname: "add_1_int32", in: -1, want: 0}, test_int32{fn: add_int32_1, fnname: "add_int32_1", in: -1, want: 0}, test_int32{fn: add_1_int32, fnname: "add_1_int32", in: 0, want: 1}, test_int32{fn: add_int32_1, fnname: "add_int32_1", in: 0, want: 1}, test_int32{fn: add_1_int32, fnname: "add_1_int32", in: 1, want: 2}, test_int32{fn: add_int32_1, fnname: "add_int32_1", in: 1, want: 2}, test_int32{fn: add_1_int32, fnname: "add_1_int32", in: 2147483647, want: -2147483648}, test_int32{fn: add_int32_1, fnname: "add_int32_1", in: 2147483647, want: -2147483648}, test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: -2147483648, want: -1}, test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: -2147483648, want: -1}, test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: -2147483647, want: 0}, test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: -2147483647, want: 0}, test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: -1, want: 2147483646}, test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: -1, want: 2147483646}, test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: 0, want: 2147483647}, test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: 0, want: 2147483647}, test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: 1, want: -2147483648}, test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: 1, want: -2147483648}, test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: 2147483647, want: -2}, test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: 2147483647, want: -2}, test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: -2147483648, want: 0}, test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: -2147483648, want: 0}, test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: -2147483647, want: -1}, test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: -2147483647, want: 1}, test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: -1, want: -2147483647}, test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: -1, want: 2147483647}, test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: 0, want: -2147483648}, test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: 0, want: -2147483648}, test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: 1, want: 2147483647}, test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: 1, want: -2147483647}, test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: 2147483647, want: 1}, test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: 2147483647, want: -1}, test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: -2147483648, want: 1}, test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: -2147483648, want: -1}, test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: -2147483647, want: 0}, test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: -2147483647, want: 0}, test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: -1, want: -2147483646}, test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: -1, want: 2147483646}, test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: 0, want: -2147483647}, test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: 0, want: 2147483647}, test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: 1, want: -2147483648}, test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: 1, want: -2147483648}, test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: 2147483647, want: 2}, test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: 2147483647, want: -2}, test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: -2147483648, want: 2147483647}, test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: -2147483648, want: -2147483647}, test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: -2147483647, want: 2147483646}, test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: -2147483647, want: -2147483646}, test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: -1, want: 0}, test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: -1, want: 0}, test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: 0, want: -1}, test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: 0, want: 1}, test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: 1, want: -2}, test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: 1, want: 2}, test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: 2147483647, want: -2147483648}, test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: 2147483647, want: -2147483648}, test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: -2147483648, want: -2147483648}, test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: -2147483648, want: -2147483648}, test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: -2147483647, want: 2147483647}, test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: -2147483647, want: -2147483647}, test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: -1, want: 1}, test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: -1, want: -1}, test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: 0, want: 0}, test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: 0, want: 0}, test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: 1, want: -1}, test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: 1, want: 1}, test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: 2147483647, want: -2147483647}, test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: 2147483647, want: 2147483647}, test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: -2147483648, want: -2147483647}, test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: -2147483648, want: 2147483647}, test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: -2147483647, want: -2147483648}, test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: -2147483647, want: -2147483648}, test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: -1, want: 2}, test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: -1, want: -2}, test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: 0, want: 1}, test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: 0, want: -1}, test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: 1, want: 0}, test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: 1, want: 0}, test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: 2147483647, want: -2147483646}, test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: 2147483647, want: 2147483646}, test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: -2147483648, want: -1}, test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: -2147483648, want: 1}, test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: -2147483647, want: -2}, test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: -2147483647, want: 2}, test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: -1, want: -2147483648}, test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: -1, want: -2147483648}, test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: 0, want: 2147483647}, test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: 0, want: -2147483647}, test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: 1, want: 2147483646}, test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: 1, want: -2147483646}, test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: 2147483647, want: 0}, test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: 2147483647, want: 0}, test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: -2147483648, want: 1}, test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: -2147483648, want: 1}, test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: -2147483647, want: 1}, test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: -2147483647, want: 0}, test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: -1, want: -2147483648}, test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: -1, want: 0}, test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: 0, want: 0}, test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: 1, want: -2147483648}, test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: 1, want: 0}, test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: 2147483647, want: -1}, test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: 2147483647, want: 0}, test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: -2147483648, want: 0}, test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: -2147483648, want: 1}, test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: -2147483647, want: 1}, test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: -2147483647, want: 1}, test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: -1, want: 2147483647}, test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: -1, want: 0}, test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: 0, want: 0}, test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: 1, want: -2147483647}, test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: 1, want: 0}, test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: 2147483647, want: -1}, test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: 2147483647, want: -1}, test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: -2147483648, want: 0}, test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: -2147483648, want: -2147483648}, test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: -2147483647, want: 0}, test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: -2147483647, want: 2147483647}, test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: -1, want: 1}, test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: -1, want: 1}, test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: 0, want: 0}, test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: 1, want: -1}, test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: 1, want: -1}, test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: 2147483647, want: 0}, test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: 2147483647, want: -2147483647}, test_int32{fn: div_0_int32, fnname: "div_0_int32", in: -2147483648, want: 0}, test_int32{fn: div_0_int32, fnname: "div_0_int32", in: -2147483647, want: 0}, test_int32{fn: div_0_int32, fnname: "div_0_int32", in: -1, want: 0}, test_int32{fn: div_0_int32, fnname: "div_0_int32", in: 1, want: 0}, test_int32{fn: div_0_int32, fnname: "div_0_int32", in: 2147483647, want: 0}, test_int32{fn: div_1_int32, fnname: "div_1_int32", in: -2147483648, want: 0}, test_int32{fn: div_int32_1, fnname: "div_int32_1", in: -2147483648, want: -2147483648}, test_int32{fn: div_1_int32, fnname: "div_1_int32", in: -2147483647, want: 0}, test_int32{fn: div_int32_1, fnname: "div_int32_1", in: -2147483647, want: -2147483647}, test_int32{fn: div_1_int32, fnname: "div_1_int32", in: -1, want: -1}, test_int32{fn: div_int32_1, fnname: "div_int32_1", in: -1, want: -1}, test_int32{fn: div_int32_1, fnname: "div_int32_1", in: 0, want: 0}, test_int32{fn: div_1_int32, fnname: "div_1_int32", in: 1, want: 1}, test_int32{fn: div_int32_1, fnname: "div_int32_1", in: 1, want: 1}, test_int32{fn: div_1_int32, fnname: "div_1_int32", in: 2147483647, want: 0}, test_int32{fn: div_int32_1, fnname: "div_int32_1", in: 2147483647, want: 2147483647}, test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: -2147483648, want: 0}, test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: -2147483648, want: -1}, test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: -2147483647, want: -1}, test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: -2147483647, want: -1}, test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: -1, want: -2147483647}, test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: -1, want: 0}, test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: 0, want: 0}, test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: 1, want: 2147483647}, test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: 1, want: 0}, test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: 2147483647, want: 1}, test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: 2147483647, want: 1}, test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: -2147483648, want: 0}, test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: -2147483648, want: 0}, test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: -2147483647, want: -2147483648}, test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: -2147483647, want: -2147483648}, test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: -1, want: -2147483648}, test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: -1, want: -2147483648}, test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: 0, want: 0}, test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: 0, want: 0}, test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: 1, want: -2147483648}, test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: 1, want: -2147483648}, test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: 2147483647, want: -2147483648}, test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: 2147483647, want: -2147483648}, test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: -2147483648, want: -2147483648}, test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: -2147483648, want: -2147483648}, test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: -2147483647, want: 1}, test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: -2147483647, want: 1}, test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: -1, want: 2147483647}, test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: -1, want: 2147483647}, test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: 0, want: 0}, test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: 0, want: 0}, test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: 1, want: -2147483647}, test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: 1, want: -2147483647}, test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: 2147483647, want: -1}, test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: 2147483647, want: -1}, test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: -2147483648, want: -2147483648}, test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: -2147483648, want: -2147483648}, test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: -2147483647, want: 2147483647}, test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: -2147483647, want: 2147483647}, test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: -1, want: 1}, test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: -1, want: 1}, test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: 0, want: 0}, test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: 0, want: 0}, test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: 1, want: -1}, test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: 1, want: -1}, test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: 2147483647, want: -2147483647}, test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: 2147483647, want: -2147483647}, test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: -2147483648, want: 0}, test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: -2147483648, want: 0}, test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: -2147483647, want: 0}, test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: -2147483647, want: 0}, test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: -1, want: 0}, test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: -1, want: 0}, test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: 0, want: 0}, test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: 0, want: 0}, test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: 1, want: 0}, test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: 1, want: 0}, test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: 2147483647, want: 0}, test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: 2147483647, want: 0}, test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: -2147483648, want: -2147483648}, test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: -2147483648, want: -2147483648}, test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: -2147483647, want: -2147483647}, test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: -2147483647, want: -2147483647}, test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: -1, want: -1}, test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: -1, want: -1}, test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: 0, want: 0}, test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: 0, want: 0}, test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: 1, want: 1}, test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: 1, want: 1}, test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: 2147483647, want: 2147483647}, test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: 2147483647, want: 2147483647}, test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: -2147483648, want: -2147483648}, test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: -2147483648, want: -2147483648}, test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: -2147483647, want: -1}, test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: -2147483647, want: -1}, test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: -1, want: -2147483647}, test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: -1, want: -2147483647}, test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: 0, want: 0}, test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: 0, want: 0}, test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: 1, want: 2147483647}, test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: 1, want: 2147483647}, test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: 2147483647, want: 1}, test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: 2147483647, want: 1}, test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: -2147483648, want: 0}, test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: -2147483648, want: 0}, test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: -2147483647, want: -1}, test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: -2147483647, want: -2147483647}, test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: -1, want: 0}, test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: -1, want: -1}, test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: 0, want: 0}, test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: 1, want: 0}, test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: 1, want: 1}, test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: 2147483647, want: -1}, test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: 2147483647, want: 2147483647}, test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: -2147483648, want: -2147483647}, test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: -2147483648, want: -1}, test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: -2147483647, want: 0}, test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: -2147483647, want: 0}, test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: -1, want: 0}, test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: -1, want: -1}, test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: 0, want: 0}, test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: 1, want: 0}, test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: 1, want: 1}, test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: 2147483647, want: 0}, test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: 2147483647, want: 0}, test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: -2147483648, want: -1}, test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: -2147483648, want: 0}, test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: -2147483647, want: -1}, test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: -2147483647, want: 0}, test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: -1, want: 0}, test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: -1, want: 0}, test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: 0, want: 0}, test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: 1, want: 0}, test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: 1, want: 0}, test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: 2147483647, want: -1}, test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: 2147483647, want: 0}, test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: -2147483648, want: 0}, test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: -2147483647, want: 0}, test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: -1, want: 0}, test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: 1, want: 0}, test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: 2147483647, want: 0}, test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: -2147483648, want: 1}, test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: -2147483648, want: 0}, test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: -2147483647, want: 1}, test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: -2147483647, want: 0}, test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: -1, want: 0}, test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: -1, want: 0}, test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: 0, want: 0}, test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: 1, want: 0}, test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: 1, want: 0}, test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: 2147483647, want: 1}, test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: 2147483647, want: 0}, test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: -2147483648, want: 2147483647}, test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: -2147483648, want: -1}, test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: -2147483647, want: 0}, test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: -2147483647, want: 0}, test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: -1, want: 0}, test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: -1, want: -1}, test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: 0, want: 0}, test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: 1, want: 0}, test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: 1, want: 1}, test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: 2147483647, want: 0}, test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: 2147483647, want: 0}, test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: -2147483648, want: -2147483648}, test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: -2147483648, want: -2147483648}, test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: -2147483647, want: -2147483648}, test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: -2147483647, want: -2147483648}, test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: -1, want: -2147483648}, test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: -1, want: -2147483648}, test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: 0, want: 0}, test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: 0, want: 0}, test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: 1, want: 0}, test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: 1, want: 0}, test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: 2147483647, want: 0}, test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: 2147483647, want: 0}, test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: -2147483648, want: -2147483648}, test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: -2147483648, want: -2147483648}, test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: -2147483647, want: -2147483647}, test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: -2147483647, want: -2147483647}, test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: -1, want: -2147483647}, test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: -1, want: -2147483647}, test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: 0, want: 0}, test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: 0, want: 0}, test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: 1, want: 1}, test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: 1, want: 1}, test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: 2147483647, want: 1}, test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: 2147483647, want: 1}, test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: -2147483648, want: -2147483648}, test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: -2147483648, want: -2147483648}, test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: -2147483647, want: -2147483647}, test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: -2147483647, want: -2147483647}, test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: -1, want: -1}, test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: -1, want: -1}, test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: 0, want: 0}, test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: 0, want: 0}, test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: 1, want: 1}, test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: 1, want: 1}, test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: 2147483647, want: 2147483647}, test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: 2147483647, want: 2147483647}, test_int32{fn: and_0_int32, fnname: "and_0_int32", in: -2147483648, want: 0}, test_int32{fn: and_int32_0, fnname: "and_int32_0", in: -2147483648, want: 0}, test_int32{fn: and_0_int32, fnname: "and_0_int32", in: -2147483647, want: 0}, test_int32{fn: and_int32_0, fnname: "and_int32_0", in: -2147483647, want: 0}, test_int32{fn: and_0_int32, fnname: "and_0_int32", in: -1, want: 0}, test_int32{fn: and_int32_0, fnname: "and_int32_0", in: -1, want: 0}, test_int32{fn: and_0_int32, fnname: "and_0_int32", in: 0, want: 0}, test_int32{fn: and_int32_0, fnname: "and_int32_0", in: 0, want: 0}, test_int32{fn: and_0_int32, fnname: "and_0_int32", in: 1, want: 0}, test_int32{fn: and_int32_0, fnname: "and_int32_0", in: 1, want: 0}, test_int32{fn: and_0_int32, fnname: "and_0_int32", in: 2147483647, want: 0}, test_int32{fn: and_int32_0, fnname: "and_int32_0", in: 2147483647, want: 0}, test_int32{fn: and_1_int32, fnname: "and_1_int32", in: -2147483648, want: 0}, test_int32{fn: and_int32_1, fnname: "and_int32_1", in: -2147483648, want: 0}, test_int32{fn: and_1_int32, fnname: "and_1_int32", in: -2147483647, want: 1}, test_int32{fn: and_int32_1, fnname: "and_int32_1", in: -2147483647, want: 1}, test_int32{fn: and_1_int32, fnname: "and_1_int32", in: -1, want: 1}, test_int32{fn: and_int32_1, fnname: "and_int32_1", in: -1, want: 1}, test_int32{fn: and_1_int32, fnname: "and_1_int32", in: 0, want: 0}, test_int32{fn: and_int32_1, fnname: "and_int32_1", in: 0, want: 0}, test_int32{fn: and_1_int32, fnname: "and_1_int32", in: 1, want: 1}, test_int32{fn: and_int32_1, fnname: "and_int32_1", in: 1, want: 1}, test_int32{fn: and_1_int32, fnname: "and_1_int32", in: 2147483647, want: 1}, test_int32{fn: and_int32_1, fnname: "and_int32_1", in: 2147483647, want: 1}, test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: -2147483648, want: 0}, test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: -2147483648, want: 0}, test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: -2147483647, want: 1}, test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: -2147483647, want: 1}, test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: -1, want: 2147483647}, test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: -1, want: 2147483647}, test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: 0, want: 0}, test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: 0, want: 0}, test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: 1, want: 1}, test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: 1, want: 1}, test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: 2147483647, want: 2147483647}, test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: 2147483647, want: 2147483647}, test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: -2147483648, want: -2147483648}, test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: -2147483648, want: -2147483648}, test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: -2147483647, want: -2147483647}, test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: -2147483647, want: -2147483647}, test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: -1, want: -1}, test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: -1, want: -1}, test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: 0, want: -2147483648}, test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: 0, want: -2147483648}, test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: 1, want: -2147483647}, test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: 1, want: -2147483647}, test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: 2147483647, want: -1}, test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: 2147483647, want: -1}, test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: -2147483648, want: -2147483647}, test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: -2147483648, want: -2147483647}, test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: -2147483647, want: -2147483647}, test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: -2147483647, want: -2147483647}, test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: -1, want: -1}, test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: -1, want: -1}, test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: 0, want: -2147483647}, test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: 0, want: -2147483647}, test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: 1, want: -2147483647}, test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: 1, want: -2147483647}, test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: 2147483647, want: -1}, test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: 2147483647, want: -1}, test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: -2147483648, want: -1}, test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: -2147483648, want: -1}, test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: -2147483647, want: -1}, test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: -2147483647, want: -1}, test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: -1, want: -1}, test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: -1, want: -1}, test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: 0, want: -1}, test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: 0, want: -1}, test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: 1, want: -1}, test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: 1, want: -1}, test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: 2147483647, want: -1}, test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: 2147483647, want: -1}, test_int32{fn: or_0_int32, fnname: "or_0_int32", in: -2147483648, want: -2147483648}, test_int32{fn: or_int32_0, fnname: "or_int32_0", in: -2147483648, want: -2147483648}, test_int32{fn: or_0_int32, fnname: "or_0_int32", in: -2147483647, want: -2147483647}, test_int32{fn: or_int32_0, fnname: "or_int32_0", in: -2147483647, want: -2147483647}, test_int32{fn: or_0_int32, fnname: "or_0_int32", in: -1, want: -1}, test_int32{fn: or_int32_0, fnname: "or_int32_0", in: -1, want: -1}, test_int32{fn: or_0_int32, fnname: "or_0_int32", in: 0, want: 0}, test_int32{fn: or_int32_0, fnname: "or_int32_0", in: 0, want: 0}, test_int32{fn: or_0_int32, fnname: "or_0_int32", in: 1, want: 1}, test_int32{fn: or_int32_0, fnname: "or_int32_0", in: 1, want: 1}, test_int32{fn: or_0_int32, fnname: "or_0_int32", in: 2147483647, want: 2147483647}, test_int32{fn: or_int32_0, fnname: "or_int32_0", in: 2147483647, want: 2147483647}, test_int32{fn: or_1_int32, fnname: "or_1_int32", in: -2147483648, want: -2147483647}, test_int32{fn: or_int32_1, fnname: "or_int32_1", in: -2147483648, want: -2147483647}, test_int32{fn: or_1_int32, fnname: "or_1_int32", in: -2147483647, want: -2147483647}, test_int32{fn: or_int32_1, fnname: "or_int32_1", in: -2147483647, want: -2147483647}, test_int32{fn: or_1_int32, fnname: "or_1_int32", in: -1, want: -1}, test_int32{fn: or_int32_1, fnname: "or_int32_1", in: -1, want: -1}, test_int32{fn: or_1_int32, fnname: "or_1_int32", in: 0, want: 1}, test_int32{fn: or_int32_1, fnname: "or_int32_1", in: 0, want: 1}, test_int32{fn: or_1_int32, fnname: "or_1_int32", in: 1, want: 1}, test_int32{fn: or_int32_1, fnname: "or_int32_1", in: 1, want: 1}, test_int32{fn: or_1_int32, fnname: "or_1_int32", in: 2147483647, want: 2147483647}, test_int32{fn: or_int32_1, fnname: "or_int32_1", in: 2147483647, want: 2147483647}, test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: -2147483648, want: -1}, test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: -2147483648, want: -1}, test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: -2147483647, want: -1}, test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: -2147483647, want: -1}, test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: -1, want: -1}, test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: -1, want: -1}, test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: 0, want: 2147483647}, test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: 0, want: 2147483647}, test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: 1, want: 2147483647}, test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: 1, want: 2147483647}, test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: 2147483647, want: 2147483647}, test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: 2147483647, want: 2147483647}, test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: -2147483648, want: 0}, test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: -2147483648, want: 0}, test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: -2147483647, want: 1}, test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: -2147483647, want: 1}, test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: -1, want: 2147483647}, test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: -1, want: 2147483647}, test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: 0, want: -2147483648}, test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: 0, want: -2147483648}, test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: 1, want: -2147483647}, test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: 1, want: -2147483647}, test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: 2147483647, want: -1}, test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: 2147483647, want: -1}, test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: -2147483648, want: 1}, test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: -2147483648, want: 1}, test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: -2147483647, want: 0}, test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: -2147483647, want: 0}, test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: -1, want: 2147483646}, test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: -1, want: 2147483646}, test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: 0, want: -2147483647}, test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: 0, want: -2147483647}, test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: 1, want: -2147483648}, test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: 1, want: -2147483648}, test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: 2147483647, want: -2}, test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: 2147483647, want: -2}, test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: -2147483648, want: 2147483647}, test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: -2147483648, want: 2147483647}, test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: -2147483647, want: 2147483646}, test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: -2147483647, want: 2147483646}, test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: -1, want: 0}, test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: -1, want: 0}, test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: 0, want: -1}, test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: 0, want: -1}, test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: 1, want: -2}, test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: 1, want: -2}, test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: 2147483647, want: -2147483648}, test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: 2147483647, want: -2147483648}, test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: -2147483648, want: -2147483648}, test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: -2147483648, want: -2147483648}, test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: -2147483647, want: -2147483647}, test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: -2147483647, want: -2147483647}, test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: -1, want: -1}, test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: -1, want: -1}, test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: 0, want: 0}, test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: 0, want: 0}, test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: 1, want: 1}, test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: 1, want: 1}, test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: 2147483647, want: 2147483647}, test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: 2147483647, want: 2147483647}, test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: -2147483648, want: -2147483647}, test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: -2147483648, want: -2147483647}, test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: -2147483647, want: -2147483648}, test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: -2147483647, want: -2147483648}, test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: -1, want: -2}, test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: -1, want: -2}, test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: 0, want: 1}, test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: 0, want: 1}, test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: 1, want: 0}, test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: 1, want: 0}, test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: 2147483647, want: 2147483646}, test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: 2147483647, want: 2147483646}, test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: -2147483648, want: -1}, test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: -2147483648, want: -1}, test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: -2147483647, want: -2}, test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: -2147483647, want: -2}, test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: -1, want: -2147483648}, test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: -1, want: -2147483648}, test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: 0, want: 2147483647}, test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: 0, want: 2147483647}, test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: 1, want: 2147483646}, test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: 1, want: 2147483646}, test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: 2147483647, want: 0}, test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: 2147483647, want: 0}} type test_uint16 struct { fn func(uint16) uint16 fnname string in uint16 want uint16 } var tests_uint16 = []test_uint16{ test_uint16{fn: add_0_uint16, fnname: "add_0_uint16", in: 0, want: 0}, test_uint16{fn: add_uint16_0, fnname: "add_uint16_0", in: 0, want: 0}, test_uint16{fn: add_0_uint16, fnname: "add_0_uint16", in: 1, want: 1}, test_uint16{fn: add_uint16_0, fnname: "add_uint16_0", in: 1, want: 1}, test_uint16{fn: add_0_uint16, fnname: "add_0_uint16", in: 65535, want: 65535}, test_uint16{fn: add_uint16_0, fnname: "add_uint16_0", in: 65535, want: 65535}, test_uint16{fn: add_1_uint16, fnname: "add_1_uint16", in: 0, want: 1}, test_uint16{fn: add_uint16_1, fnname: "add_uint16_1", in: 0, want: 1}, test_uint16{fn: add_1_uint16, fnname: "add_1_uint16", in: 1, want: 2}, test_uint16{fn: add_uint16_1, fnname: "add_uint16_1", in: 1, want: 2}, test_uint16{fn: add_1_uint16, fnname: "add_1_uint16", in: 65535, want: 0}, test_uint16{fn: add_uint16_1, fnname: "add_uint16_1", in: 65535, want: 0}, test_uint16{fn: add_65535_uint16, fnname: "add_65535_uint16", in: 0, want: 65535}, test_uint16{fn: add_uint16_65535, fnname: "add_uint16_65535", in: 0, want: 65535}, test_uint16{fn: add_65535_uint16, fnname: "add_65535_uint16", in: 1, want: 0}, test_uint16{fn: add_uint16_65535, fnname: "add_uint16_65535", in: 1, want: 0}, test_uint16{fn: add_65535_uint16, fnname: "add_65535_uint16", in: 65535, want: 65534}, test_uint16{fn: add_uint16_65535, fnname: "add_uint16_65535", in: 65535, want: 65534}, test_uint16{fn: sub_0_uint16, fnname: "sub_0_uint16", in: 0, want: 0}, test_uint16{fn: sub_uint16_0, fnname: "sub_uint16_0", in: 0, want: 0}, test_uint16{fn: sub_0_uint16, fnname: "sub_0_uint16", in: 1, want: 65535}, test_uint16{fn: sub_uint16_0, fnname: "sub_uint16_0", in: 1, want: 1}, test_uint16{fn: sub_0_uint16, fnname: "sub_0_uint16", in: 65535, want: 1}, test_uint16{fn: sub_uint16_0, fnname: "sub_uint16_0", in: 65535, want: 65535}, test_uint16{fn: sub_1_uint16, fnname: "sub_1_uint16", in: 0, want: 1}, test_uint16{fn: sub_uint16_1, fnname: "sub_uint16_1", in: 0, want: 65535}, test_uint16{fn: sub_1_uint16, fnname: "sub_1_uint16", in: 1, want: 0}, test_uint16{fn: sub_uint16_1, fnname: "sub_uint16_1", in: 1, want: 0}, test_uint16{fn: sub_1_uint16, fnname: "sub_1_uint16", in: 65535, want: 2}, test_uint16{fn: sub_uint16_1, fnname: "sub_uint16_1", in: 65535, want: 65534}, test_uint16{fn: sub_65535_uint16, fnname: "sub_65535_uint16", in: 0, want: 65535}, test_uint16{fn: sub_uint16_65535, fnname: "sub_uint16_65535", in: 0, want: 1}, test_uint16{fn: sub_65535_uint16, fnname: "sub_65535_uint16", in: 1, want: 65534}, test_uint16{fn: sub_uint16_65535, fnname: "sub_uint16_65535", in: 1, want: 2}, test_uint16{fn: sub_65535_uint16, fnname: "sub_65535_uint16", in: 65535, want: 0}, test_uint16{fn: sub_uint16_65535, fnname: "sub_uint16_65535", in: 65535, want: 0}, test_uint16{fn: div_0_uint16, fnname: "div_0_uint16", in: 1, want: 0}, test_uint16{fn: div_0_uint16, fnname: "div_0_uint16", in: 65535, want: 0}, test_uint16{fn: div_uint16_1, fnname: "div_uint16_1", in: 0, want: 0}, test_uint16{fn: div_1_uint16, fnname: "div_1_uint16", in: 1, want: 1}, test_uint16{fn: div_uint16_1, fnname: "div_uint16_1", in: 1, want: 1}, test_uint16{fn: div_1_uint16, fnname: "div_1_uint16", in: 65535, want: 0}, test_uint16{fn: div_uint16_1, fnname: "div_uint16_1", in: 65535, want: 65535}, test_uint16{fn: div_uint16_65535, fnname: "div_uint16_65535", in: 0, want: 0}, test_uint16{fn: div_65535_uint16, fnname: "div_65535_uint16", in: 1, want: 65535}, test_uint16{fn: div_uint16_65535, fnname: "div_uint16_65535", in: 1, want: 0}, test_uint16{fn: div_65535_uint16, fnname: "div_65535_uint16", in: 65535, want: 1}, test_uint16{fn: div_uint16_65535, fnname: "div_uint16_65535", in: 65535, want: 1}, test_uint16{fn: mul_0_uint16, fnname: "mul_0_uint16", in: 0, want: 0}, test_uint16{fn: mul_uint16_0, fnname: "mul_uint16_0", in: 0, want: 0}, test_uint16{fn: mul_0_uint16, fnname: "mul_0_uint16", in: 1, want: 0}, test_uint16{fn: mul_uint16_0, fnname: "mul_uint16_0", in: 1, want: 0}, test_uint16{fn: mul_0_uint16, fnname: "mul_0_uint16", in: 65535, want: 0}, test_uint16{fn: mul_uint16_0, fnname: "mul_uint16_0", in: 65535, want: 0}, test_uint16{fn: mul_1_uint16, fnname: "mul_1_uint16", in: 0, want: 0}, test_uint16{fn: mul_uint16_1, fnname: "mul_uint16_1", in: 0, want: 0}, test_uint16{fn: mul_1_uint16, fnname: "mul_1_uint16", in: 1, want: 1}, test_uint16{fn: mul_uint16_1, fnname: "mul_uint16_1", in: 1, want: 1}, test_uint16{fn: mul_1_uint16, fnname: "mul_1_uint16", in: 65535, want: 65535}, test_uint16{fn: mul_uint16_1, fnname: "mul_uint16_1", in: 65535, want: 65535}, test_uint16{fn: mul_65535_uint16, fnname: "mul_65535_uint16", in: 0, want: 0}, test_uint16{fn: mul_uint16_65535, fnname: "mul_uint16_65535", in: 0, want: 0}, test_uint16{fn: mul_65535_uint16, fnname: "mul_65535_uint16", in: 1, want: 65535}, test_uint16{fn: mul_uint16_65535, fnname: "mul_uint16_65535", in: 1, want: 65535}, test_uint16{fn: mul_65535_uint16, fnname: "mul_65535_uint16", in: 65535, want: 1}, test_uint16{fn: mul_uint16_65535, fnname: "mul_uint16_65535", in: 65535, want: 1}, test_uint16{fn: lsh_0_uint16, fnname: "lsh_0_uint16", in: 0, want: 0}, test_uint16{fn: lsh_uint16_0, fnname: "lsh_uint16_0", in: 0, want: 0}, test_uint16{fn: lsh_0_uint16, fnname: "lsh_0_uint16", in: 1, want: 0}, test_uint16{fn: lsh_uint16_0, fnname: "lsh_uint16_0", in: 1, want: 1}, test_uint16{fn: lsh_0_uint16, fnname: "lsh_0_uint16", in: 65535, want: 0}, test_uint16{fn: lsh_uint16_0, fnname: "lsh_uint16_0", in: 65535, want: 65535}, test_uint16{fn: lsh_1_uint16, fnname: "lsh_1_uint16", in: 0, want: 1}, test_uint16{fn: lsh_uint16_1, fnname: "lsh_uint16_1", in: 0, want: 0}, test_uint16{fn: lsh_1_uint16, fnname: "lsh_1_uint16", in: 1, want: 2}, test_uint16{fn: lsh_uint16_1, fnname: "lsh_uint16_1", in: 1, want: 2}, test_uint16{fn: lsh_1_uint16, fnname: "lsh_1_uint16", in: 65535, want: 0}, test_uint16{fn: lsh_uint16_1, fnname: "lsh_uint16_1", in: 65535, want: 65534}, test_uint16{fn: lsh_65535_uint16, fnname: "lsh_65535_uint16", in: 0, want: 65535}, test_uint16{fn: lsh_uint16_65535, fnname: "lsh_uint16_65535", in: 0, want: 0}, test_uint16{fn: lsh_65535_uint16, fnname: "lsh_65535_uint16", in: 1, want: 65534}, test_uint16{fn: lsh_uint16_65535, fnname: "lsh_uint16_65535", in: 1, want: 0}, test_uint16{fn: lsh_65535_uint16, fnname: "lsh_65535_uint16", in: 65535, want: 0}, test_uint16{fn: lsh_uint16_65535, fnname: "lsh_uint16_65535", in: 65535, want: 0}, test_uint16{fn: rsh_0_uint16, fnname: "rsh_0_uint16", in: 0, want: 0}, test_uint16{fn: rsh_uint16_0, fnname: "rsh_uint16_0", in: 0, want: 0}, test_uint16{fn: rsh_0_uint16, fnname: "rsh_0_uint16", in: 1, want: 0}, test_uint16{fn: rsh_uint16_0, fnname: "rsh_uint16_0", in: 1, want: 1}, test_uint16{fn: rsh_0_uint16, fnname: "rsh_0_uint16", in: 65535, want: 0}, test_uint16{fn: rsh_uint16_0, fnname: "rsh_uint16_0", in: 65535, want: 65535}, test_uint16{fn: rsh_1_uint16, fnname: "rsh_1_uint16", in: 0, want: 1}, test_uint16{fn: rsh_uint16_1, fnname: "rsh_uint16_1", in: 0, want: 0}, test_uint16{fn: rsh_1_uint16, fnname: "rsh_1_uint16", in: 1, want: 0}, test_uint16{fn: rsh_uint16_1, fnname: "rsh_uint16_1", in: 1, want: 0}, test_uint16{fn: rsh_1_uint16, fnname: "rsh_1_uint16", in: 65535, want: 0}, test_uint16{fn: rsh_uint16_1, fnname: "rsh_uint16_1", in: 65535, want: 32767}, test_uint16{fn: rsh_65535_uint16, fnname: "rsh_65535_uint16", in: 0, want: 65535}, test_uint16{fn: rsh_uint16_65535, fnname: "rsh_uint16_65535", in: 0, want: 0}, test_uint16{fn: rsh_65535_uint16, fnname: "rsh_65535_uint16", in: 1, want: 32767}, test_uint16{fn: rsh_uint16_65535, fnname: "rsh_uint16_65535", in: 1, want: 0}, test_uint16{fn: rsh_65535_uint16, fnname: "rsh_65535_uint16", in: 65535, want: 0}, test_uint16{fn: rsh_uint16_65535, fnname: "rsh_uint16_65535", in: 65535, want: 0}, test_uint16{fn: mod_0_uint16, fnname: "mod_0_uint16", in: 1, want: 0}, test_uint16{fn: mod_0_uint16, fnname: "mod_0_uint16", in: 65535, want: 0}, test_uint16{fn: mod_uint16_1, fnname: "mod_uint16_1", in: 0, want: 0}, test_uint16{fn: mod_1_uint16, fnname: "mod_1_uint16", in: 1, want: 0}, test_uint16{fn: mod_uint16_1, fnname: "mod_uint16_1", in: 1, want: 0}, test_uint16{fn: mod_1_uint16, fnname: "mod_1_uint16", in: 65535, want: 1}, test_uint16{fn: mod_uint16_1, fnname: "mod_uint16_1", in: 65535, want: 0}, test_uint16{fn: mod_uint16_65535, fnname: "mod_uint16_65535", in: 0, want: 0}, test_uint16{fn: mod_65535_uint16, fnname: "mod_65535_uint16", in: 1, want: 0}, test_uint16{fn: mod_uint16_65535, fnname: "mod_uint16_65535", in: 1, want: 1}, test_uint16{fn: mod_65535_uint16, fnname: "mod_65535_uint16", in: 65535, want: 0}, test_uint16{fn: mod_uint16_65535, fnname: "mod_uint16_65535", in: 65535, want: 0}, test_uint16{fn: and_0_uint16, fnname: "and_0_uint16", in: 0, want: 0}, test_uint16{fn: and_uint16_0, fnname: "and_uint16_0", in: 0, want: 0}, test_uint16{fn: and_0_uint16, fnname: "and_0_uint16", in: 1, want: 0}, test_uint16{fn: and_uint16_0, fnname: "and_uint16_0", in: 1, want: 0}, test_uint16{fn: and_0_uint16, fnname: "and_0_uint16", in: 65535, want: 0}, test_uint16{fn: and_uint16_0, fnname: "and_uint16_0", in: 65535, want: 0}, test_uint16{fn: and_1_uint16, fnname: "and_1_uint16", in: 0, want: 0}, test_uint16{fn: and_uint16_1, fnname: "and_uint16_1", in: 0, want: 0}, test_uint16{fn: and_1_uint16, fnname: "and_1_uint16", in: 1, want: 1}, test_uint16{fn: and_uint16_1, fnname: "and_uint16_1", in: 1, want: 1}, test_uint16{fn: and_1_uint16, fnname: "and_1_uint16", in: 65535, want: 1}, test_uint16{fn: and_uint16_1, fnname: "and_uint16_1", in: 65535, want: 1}, test_uint16{fn: and_65535_uint16, fnname: "and_65535_uint16", in: 0, want: 0}, test_uint16{fn: and_uint16_65535, fnname: "and_uint16_65535", in: 0, want: 0}, test_uint16{fn: and_65535_uint16, fnname: "and_65535_uint16", in: 1, want: 1}, test_uint16{fn: and_uint16_65535, fnname: "and_uint16_65535", in: 1, want: 1}, test_uint16{fn: and_65535_uint16, fnname: "and_65535_uint16", in: 65535, want: 65535}, test_uint16{fn: and_uint16_65535, fnname: "and_uint16_65535", in: 65535, want: 65535}, test_uint16{fn: or_0_uint16, fnname: "or_0_uint16", in: 0, want: 0}, test_uint16{fn: or_uint16_0, fnname: "or_uint16_0", in: 0, want: 0}, test_uint16{fn: or_0_uint16, fnname: "or_0_uint16", in: 1, want: 1}, test_uint16{fn: or_uint16_0, fnname: "or_uint16_0", in: 1, want: 1}, test_uint16{fn: or_0_uint16, fnname: "or_0_uint16", in: 65535, want: 65535}, test_uint16{fn: or_uint16_0, fnname: "or_uint16_0", in: 65535, want: 65535}, test_uint16{fn: or_1_uint16, fnname: "or_1_uint16", in: 0, want: 1}, test_uint16{fn: or_uint16_1, fnname: "or_uint16_1", in: 0, want: 1}, test_uint16{fn: or_1_uint16, fnname: "or_1_uint16", in: 1, want: 1}, test_uint16{fn: or_uint16_1, fnname: "or_uint16_1", in: 1, want: 1}, test_uint16{fn: or_1_uint16, fnname: "or_1_uint16", in: 65535, want: 65535}, test_uint16{fn: or_uint16_1, fnname: "or_uint16_1", in: 65535, want: 65535}, test_uint16{fn: or_65535_uint16, fnname: "or_65535_uint16", in: 0, want: 65535}, test_uint16{fn: or_uint16_65535, fnname: "or_uint16_65535", in: 0, want: 65535}, test_uint16{fn: or_65535_uint16, fnname: "or_65535_uint16", in: 1, want: 65535}, test_uint16{fn: or_uint16_65535, fnname: "or_uint16_65535", in: 1, want: 65535}, test_uint16{fn: or_65535_uint16, fnname: "or_65535_uint16", in: 65535, want: 65535}, test_uint16{fn: or_uint16_65535, fnname: "or_uint16_65535", in: 65535, want: 65535}, test_uint16{fn: xor_0_uint16, fnname: "xor_0_uint16", in: 0, want: 0}, test_uint16{fn: xor_uint16_0, fnname: "xor_uint16_0", in: 0, want: 0}, test_uint16{fn: xor_0_uint16, fnname: "xor_0_uint16", in: 1, want: 1}, test_uint16{fn: xor_uint16_0, fnname: "xor_uint16_0", in: 1, want: 1}, test_uint16{fn: xor_0_uint16, fnname: "xor_0_uint16", in: 65535, want: 65535}, test_uint16{fn: xor_uint16_0, fnname: "xor_uint16_0", in: 65535, want: 65535}, test_uint16{fn: xor_1_uint16, fnname: "xor_1_uint16", in: 0, want: 1}, test_uint16{fn: xor_uint16_1, fnname: "xor_uint16_1", in: 0, want: 1}, test_uint16{fn: xor_1_uint16, fnname: "xor_1_uint16", in: 1, want: 0}, test_uint16{fn: xor_uint16_1, fnname: "xor_uint16_1", in: 1, want: 0}, test_uint16{fn: xor_1_uint16, fnname: "xor_1_uint16", in: 65535, want: 65534}, test_uint16{fn: xor_uint16_1, fnname: "xor_uint16_1", in: 65535, want: 65534}, test_uint16{fn: xor_65535_uint16, fnname: "xor_65535_uint16", in: 0, want: 65535}, test_uint16{fn: xor_uint16_65535, fnname: "xor_uint16_65535", in: 0, want: 65535}, test_uint16{fn: xor_65535_uint16, fnname: "xor_65535_uint16", in: 1, want: 65534}, test_uint16{fn: xor_uint16_65535, fnname: "xor_uint16_65535", in: 1, want: 65534}, test_uint16{fn: xor_65535_uint16, fnname: "xor_65535_uint16", in: 65535, want: 0}, test_uint16{fn: xor_uint16_65535, fnname: "xor_uint16_65535", in: 65535, want: 0}} type test_int16 struct { fn func(int16) int16 fnname string in int16 want int16 } var tests_int16 = []test_int16{ test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: -32768, want: 0}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: -32768, want: 0}, test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: -32767, want: 1}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: -32767, want: 1}, test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: -1, want: 32767}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: -1, want: 32767}, test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: 0, want: -32768}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: 0, want: -32768}, test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: 1, want: -32767}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: 1, want: -32767}, test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: 32766, want: -2}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: 32766, want: -2}, test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: 32767, want: -1}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: 32767, want: -1}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: -32768, want: 1}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: -32768, want: 1}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: -32767, want: 2}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: -32767, want: 2}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: -1, want: -32768}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: -1, want: -32768}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: 0, want: -32767}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: 0, want: -32767}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: 1, want: -32766}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: 1, want: -32766}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: 32766, want: -1}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: 32766, want: -1}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: 32767, want: 0}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: 32767, want: 0}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: -32768, want: 32767}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: -32768, want: 32767}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: -32767, want: -32768}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: -32767, want: -32768}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: -1, want: -2}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: -1, want: -2}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: 0, want: -1}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: 0, want: -1}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: 1, want: 0}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: 1, want: 0}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: 32766, want: 32765}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: 32766, want: 32765}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: 32767, want: 32766}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: 32767, want: 32766}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: -32768, want: -32768}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: -32768, want: -32768}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: -32767, want: -32767}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: -32767, want: -32767}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: -1, want: -1}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: -1, want: -1}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: 0, want: 0}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: 0, want: 0}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: 1, want: 1}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: 1, want: 1}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: 32766, want: 32766}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: 32766, want: 32766}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: 32767, want: 32767}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: 32767, want: 32767}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: -32768, want: -32767}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: -32768, want: -32767}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: -32767, want: -32766}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: -32767, want: -32766}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: -1, want: 0}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: -1, want: 0}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: 0, want: 1}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: 0, want: 1}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: 1, want: 2}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: 1, want: 2}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: 32766, want: 32767}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: 32766, want: 32767}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: 32767, want: -32768}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: 32767, want: -32768}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: -32768, want: -2}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: -32768, want: -2}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: -32767, want: -1}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: -32767, want: -1}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: -1, want: 32765}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: -1, want: 32765}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: 0, want: 32766}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: 0, want: 32766}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: 1, want: 32767}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: 1, want: 32767}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: 32766, want: -4}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: 32766, want: -4}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: 32767, want: -3}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: 32767, want: -3}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: -32768, want: -1}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: -32768, want: -1}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: -32767, want: 0}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: -32767, want: 0}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: -1, want: 32766}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: -1, want: 32766}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: 0, want: 32767}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: 0, want: 32767}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: 1, want: -32768}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: 1, want: -32768}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: 32766, want: -3}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: 32766, want: -3}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: 32767, want: -2}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: 32767, want: -2}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: -32768, want: 0}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: -32768, want: 0}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: -32767, want: -1}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: -32767, want: 1}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: -1, want: -32767}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: -1, want: 32767}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: 0, want: -32768}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: 0, want: -32768}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: 1, want: 32767}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: 1, want: -32767}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: 32766, want: 2}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: 32766, want: -2}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: 32767, want: 1}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: 32767, want: -1}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: -32768, want: 1}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: -32768, want: -1}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: -32767, want: 0}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: -32767, want: 0}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: -1, want: -32766}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: -1, want: 32766}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: 0, want: -32767}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: 0, want: 32767}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: 1, want: -32768}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: 1, want: -32768}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: 32766, want: 3}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: 32766, want: -3}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: 32767, want: 2}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: 32767, want: -2}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: -32768, want: 32767}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: -32768, want: -32767}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: -32767, want: 32766}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: -32767, want: -32766}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: -1, want: 0}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: -1, want: 0}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: 0, want: -1}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: 0, want: 1}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: 1, want: -2}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: 1, want: 2}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: 32766, want: -32767}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: 32766, want: 32767}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: 32767, want: -32768}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: 32767, want: -32768}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: -32768, want: -32768}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: -32768, want: -32768}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: -32767, want: 32767}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: -32767, want: -32767}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: -1, want: 1}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: -1, want: -1}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: 0, want: 0}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: 0, want: 0}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: 1, want: -1}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: 1, want: 1}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: 32766, want: -32766}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: 32766, want: 32766}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: 32767, want: -32767}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: 32767, want: 32767}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: -32768, want: -32767}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: -32768, want: 32767}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: -32767, want: -32768}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: -32767, want: -32768}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: -1, want: 2}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: -1, want: -2}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: 0, want: 1}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: 0, want: -1}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: 1, want: 0}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: 1, want: 0}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: 32766, want: -32765}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: 32766, want: 32765}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: 32767, want: -32766}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: 32767, want: 32766}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: -32768, want: -2}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: -32768, want: 2}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: -32767, want: -3}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: -32767, want: 3}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: -1, want: 32767}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: -1, want: -32767}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: 0, want: 32766}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: 0, want: -32766}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: 1, want: 32765}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: 1, want: -32765}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: 32766, want: 0}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: 32766, want: 0}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: 32767, want: -1}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: 32767, want: 1}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: -32768, want: -1}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: -32768, want: 1}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: -32767, want: -2}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: -32767, want: 2}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: -1, want: -32768}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: -1, want: -32768}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: 0, want: 32767}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: 0, want: -32767}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: 1, want: 32766}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: 1, want: -32766}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: 32766, want: 1}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: 32766, want: -1}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: 32767, want: 0}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: 32767, want: 0}, test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: -32768, want: 1}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: -32768, want: 1}, test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: -32767, want: 1}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: -32767, want: 0}, test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: -1, want: -32768}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: -1, want: 0}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: 0, want: 0}, test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: 1, want: -32768}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: 1, want: 0}, test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: 32766, want: -1}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: 32766, want: 0}, test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: 32767, want: -1}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: 32767, want: 0}, test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: -32768, want: 0}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: -32768, want: 1}, test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: -32767, want: 1}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: -32767, want: 1}, test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: -1, want: 32767}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: -1, want: 0}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: 0, want: 0}, test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: 1, want: -32767}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: 1, want: 0}, test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: 32766, want: -1}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: 32766, want: 0}, test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: 32767, want: -1}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: 32767, want: -1}, test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: -32768, want: 0}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: -32768, want: -32768}, test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: -32767, want: 0}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: -32767, want: 32767}, test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: -1, want: 1}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: -1, want: 1}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: 0, want: 0}, test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: 1, want: -1}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: 1, want: -1}, test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: 32766, want: 0}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: 32766, want: -32766}, test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: 32767, want: 0}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: 32767, want: -32767}, test_int16{fn: div_0_int16, fnname: "div_0_int16", in: -32768, want: 0}, test_int16{fn: div_0_int16, fnname: "div_0_int16", in: -32767, want: 0}, test_int16{fn: div_0_int16, fnname: "div_0_int16", in: -1, want: 0}, test_int16{fn: div_0_int16, fnname: "div_0_int16", in: 1, want: 0}, test_int16{fn: div_0_int16, fnname: "div_0_int16", in: 32766, want: 0}, test_int16{fn: div_0_int16, fnname: "div_0_int16", in: 32767, want: 0}, test_int16{fn: div_1_int16, fnname: "div_1_int16", in: -32768, want: 0}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: -32768, want: -32768}, test_int16{fn: div_1_int16, fnname: "div_1_int16", in: -32767, want: 0}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: -32767, want: -32767}, test_int16{fn: div_1_int16, fnname: "div_1_int16", in: -1, want: -1}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: -1, want: -1}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: 0, want: 0}, test_int16{fn: div_1_int16, fnname: "div_1_int16", in: 1, want: 1}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: 1, want: 1}, test_int16{fn: div_1_int16, fnname: "div_1_int16", in: 32766, want: 0}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: 32766, want: 32766}, test_int16{fn: div_1_int16, fnname: "div_1_int16", in: 32767, want: 0}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: 32767, want: 32767}, test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: -32768, want: 0}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: -32768, want: -1}, test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: -32767, want: 0}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: -32767, want: -1}, test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: -1, want: -32766}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: -1, want: 0}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: 0, want: 0}, test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: 1, want: 32766}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: 1, want: 0}, test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: 32766, want: 1}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: 32766, want: 1}, test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: 32767, want: 0}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: 32767, want: 1}, test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: -32768, want: 0}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: -32768, want: -1}, test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: -32767, want: -1}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: -32767, want: -1}, test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: -1, want: -32767}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: -1, want: 0}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: 0, want: 0}, test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: 1, want: 32767}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: 1, want: 0}, test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: 32766, want: 1}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: 32766, want: 0}, test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: 32767, want: 1}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: 32767, want: 1}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: -32768, want: 0}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: -32768, want: 0}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: -32767, want: -32768}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: -32767, want: -32768}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: -1, want: -32768}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: -1, want: -32768}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: 0, want: 0}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: 0, want: 0}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: 1, want: -32768}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: 1, want: -32768}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: 32766, want: 0}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: 32766, want: 0}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: 32767, want: -32768}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: 32767, want: -32768}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: -32768, want: -32768}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: -32768, want: -32768}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: -32767, want: 1}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: -32767, want: 1}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: -1, want: 32767}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: -1, want: 32767}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: 0, want: 0}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: 0, want: 0}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: 1, want: -32767}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: 1, want: -32767}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: 32766, want: 32766}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: 32766, want: 32766}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: 32767, want: -1}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: 32767, want: -1}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: -32768, want: -32768}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: -32768, want: -32768}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: -32767, want: 32767}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: -32767, want: 32767}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: -1, want: 1}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: -1, want: 1}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: 0, want: 0}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: 0, want: 0}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: 1, want: -1}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: 1, want: -1}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: 32766, want: -32766}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: 32766, want: -32766}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: 32767, want: -32767}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: 32767, want: -32767}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: -32768, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: -32768, want: 0}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: -32767, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: -32767, want: 0}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: -1, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: -1, want: 0}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: 0, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: 0, want: 0}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: 1, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: 1, want: 0}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: 32766, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: 32766, want: 0}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: 32767, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: 32767, want: 0}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: -32768, want: -32768}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: -32768, want: -32768}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: -32767, want: -32767}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: -32767, want: -32767}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: -1, want: -1}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: -1, want: -1}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: 0, want: 0}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: 0, want: 0}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: 1, want: 1}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: 1, want: 1}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: 32766, want: 32766}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: 32766, want: 32766}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: 32767, want: 32767}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: 32767, want: 32767}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: -32768, want: 0}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: -32768, want: 0}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: -32767, want: 32766}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: -32767, want: 32766}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: -1, want: -32766}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: -1, want: -32766}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: 0, want: 0}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: 0, want: 0}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: 1, want: 32766}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: 1, want: 32766}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: 32766, want: 4}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: 32766, want: 4}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: 32767, want: -32766}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: 32767, want: -32766}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: -32768, want: -32768}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: -32768, want: -32768}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: -32767, want: -1}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: -32767, want: -1}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: -1, want: -32767}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: -1, want: -32767}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: 0, want: 0}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: 0, want: 0}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: 1, want: 32767}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: 1, want: 32767}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: 32766, want: -32766}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: 32766, want: -32766}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: 32767, want: 1}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: 32767, want: 1}, test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: -32768, want: 0}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: -32768, want: 0}, test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: -32767, want: -1}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: -32767, want: -32767}, test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: -1, want: 0}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: -1, want: -1}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: 0, want: 0}, test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: 1, want: 0}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: 1, want: 1}, test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: 32766, want: -2}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: 32766, want: 32766}, test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: 32767, want: -1}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: 32767, want: 32767}, test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: -32768, want: -32767}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: -32768, want: -1}, test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: -32767, want: 0}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: -32767, want: 0}, test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: -1, want: 0}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: -1, want: -1}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: 0, want: 0}, test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: 1, want: 0}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: 1, want: 1}, test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: 32766, want: -1}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: 32766, want: 32766}, test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: 32767, want: 0}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: 32767, want: 0}, test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: -32768, want: -1}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: -32768, want: 0}, test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: -32767, want: -1}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: -32767, want: 0}, test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: -1, want: 0}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: -1, want: 0}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: 0, want: 0}, test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: 1, want: 0}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: 1, want: 0}, test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: 32766, want: -1}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: 32766, want: 0}, test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: 32767, want: -1}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: 32767, want: 0}, test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: -32768, want: 0}, test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: -32767, want: 0}, test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: -1, want: 0}, test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: 1, want: 0}, test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: 32766, want: 0}, test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: 32767, want: 0}, test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: -32768, want: 1}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: -32768, want: 0}, test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: -32767, want: 1}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: -32767, want: 0}, test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: -1, want: 0}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: -1, want: 0}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: 0, want: 0}, test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: 1, want: 0}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: 1, want: 0}, test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: 32766, want: 1}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: 32766, want: 0}, test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: 32767, want: 1}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: 32767, want: 0}, test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: -32768, want: 32766}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: -32768, want: -2}, test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: -32767, want: 32766}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: -32767, want: -1}, test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: -1, want: 0}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: -1, want: -1}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: 0, want: 0}, test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: 1, want: 0}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: 1, want: 1}, test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: 32766, want: 0}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: 32766, want: 0}, test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: 32767, want: 32766}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: 32767, want: 1}, test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: -32768, want: 32767}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: -32768, want: -1}, test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: -32767, want: 0}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: -32767, want: 0}, test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: -1, want: 0}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: -1, want: -1}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: 0, want: 0}, test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: 1, want: 0}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: 1, want: 1}, test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: 32766, want: 1}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: 32766, want: 32766}, test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: 32767, want: 0}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: 32767, want: 0}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: -32768, want: -32768}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: -32768, want: -32768}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: -32767, want: -32768}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: -32767, want: -32768}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: -1, want: -32768}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: -1, want: -32768}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: 0, want: 0}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: 0, want: 0}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: 1, want: 0}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: 1, want: 0}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: 32766, want: 0}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: 32766, want: 0}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: 32767, want: 0}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: 32767, want: 0}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: -32768, want: -32768}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: -32768, want: -32768}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: -32767, want: -32767}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: -32767, want: -32767}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: -1, want: -32767}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: -1, want: -32767}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: 0, want: 0}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: 0, want: 0}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: 1, want: 1}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: 1, want: 1}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: 32766, want: 0}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: 32766, want: 0}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: 32767, want: 1}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: 32767, want: 1}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: -32768, want: -32768}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: -32768, want: -32768}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: -32767, want: -32767}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: -32767, want: -32767}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: -1, want: -1}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: -1, want: -1}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: 0, want: 0}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: 0, want: 0}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: 1, want: 1}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: 1, want: 1}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: 32766, want: 32766}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: 32766, want: 32766}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: 32767, want: 32767}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: 32767, want: 32767}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: -32768, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: -32768, want: 0}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: -32767, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: -32767, want: 0}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: -1, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: -1, want: 0}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: 0, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: 0, want: 0}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: 1, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: 1, want: 0}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: 32766, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: 32766, want: 0}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: 32767, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: 32767, want: 0}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: -32768, want: 0}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: -32768, want: 0}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: -32767, want: 1}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: -32767, want: 1}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: -1, want: 1}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: -1, want: 1}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: 0, want: 0}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: 0, want: 0}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: 1, want: 1}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: 1, want: 1}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: 32766, want: 0}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: 32766, want: 0}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: 32767, want: 1}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: 32767, want: 1}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: -32768, want: 0}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: -32768, want: 0}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: -32767, want: 0}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: -32767, want: 0}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: -1, want: 32766}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: -1, want: 32766}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: 0, want: 0}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: 0, want: 0}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: 1, want: 0}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: 1, want: 0}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: 32766, want: 32766}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: 32766, want: 32766}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: 32767, want: 32766}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: 32767, want: 32766}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: -32768, want: 0}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: -32768, want: 0}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: -32767, want: 1}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: -32767, want: 1}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: -1, want: 32767}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: -1, want: 32767}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: 0, want: 0}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: 0, want: 0}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: 1, want: 1}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: 1, want: 1}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: 32766, want: 32766}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: 32766, want: 32766}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: 32767, want: 32767}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: 32767, want: 32767}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: -32768, want: -32768}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: -32768, want: -32768}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: -32767, want: -32767}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: -32767, want: -32767}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: -1, want: -1}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: -1, want: -1}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: 0, want: -32768}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: 0, want: -32768}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: 1, want: -32767}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: 1, want: -32767}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: 32766, want: -2}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: 32766, want: -2}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: 32767, want: -1}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: 32767, want: -1}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: -32768, want: -32767}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: -32768, want: -32767}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: -32767, want: -32767}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: -32767, want: -32767}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: -1, want: -1}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: -1, want: -1}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: 0, want: -32767}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: 0, want: -32767}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: 1, want: -32767}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: 1, want: -32767}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: 32766, want: -1}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: 32766, want: -1}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: 32767, want: -1}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: 32767, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: -32768, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: -32768, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: -32767, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: -32767, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: -1, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: -1, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: 0, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: 0, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: 1, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: 1, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: 32766, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: 32766, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: 32767, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: 32767, want: -1}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: -32768, want: -32768}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: -32768, want: -32768}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: -32767, want: -32767}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: -32767, want: -32767}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: -1, want: -1}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: -1, want: -1}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: 0, want: 0}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: 0, want: 0}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: 1, want: 1}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: 1, want: 1}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: 32766, want: 32766}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: 32766, want: 32766}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: 32767, want: 32767}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: 32767, want: 32767}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: -32768, want: -32767}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: -32768, want: -32767}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: -32767, want: -32767}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: -32767, want: -32767}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: -1, want: -1}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: -1, want: -1}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: 0, want: 1}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: 0, want: 1}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: 1, want: 1}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: 1, want: 1}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: 32766, want: 32767}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: 32766, want: 32767}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: 32767, want: 32767}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: 32767, want: 32767}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: -32768, want: -2}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: -32768, want: -2}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: -32767, want: -1}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: -32767, want: -1}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: -1, want: -1}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: -1, want: -1}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: 0, want: 32766}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: 0, want: 32766}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: 1, want: 32767}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: 1, want: 32767}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: 32766, want: 32766}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: 32766, want: 32766}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: 32767, want: 32767}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: 32767, want: 32767}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: -32768, want: -1}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: -32768, want: -1}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: -32767, want: -1}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: -32767, want: -1}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: -1, want: -1}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: -1, want: -1}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: 0, want: 32767}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: 0, want: 32767}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: 1, want: 32767}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: 1, want: 32767}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: 32766, want: 32767}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: 32766, want: 32767}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: 32767, want: 32767}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: 32767, want: 32767}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: -32768, want: 0}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: -32768, want: 0}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: -32767, want: 1}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: -32767, want: 1}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: -1, want: 32767}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: -1, want: 32767}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: 0, want: -32768}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: 0, want: -32768}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: 1, want: -32767}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: 1, want: -32767}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: 32766, want: -2}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: 32766, want: -2}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: 32767, want: -1}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: 32767, want: -1}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: -32768, want: 1}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: -32768, want: 1}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: -32767, want: 0}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: -32767, want: 0}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: -1, want: 32766}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: -1, want: 32766}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: 0, want: -32767}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: 0, want: -32767}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: 1, want: -32768}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: 1, want: -32768}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: 32766, want: -1}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: 32766, want: -1}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: 32767, want: -2}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: 32767, want: -2}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: -32768, want: 32767}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: -32768, want: 32767}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: -32767, want: 32766}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: -32767, want: 32766}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: -1, want: 0}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: -1, want: 0}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: 0, want: -1}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: 0, want: -1}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: 1, want: -2}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: 1, want: -2}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: 32766, want: -32767}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: 32766, want: -32767}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: 32767, want: -32768}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: 32767, want: -32768}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: -32768, want: -32768}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: -32768, want: -32768}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: -32767, want: -32767}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: -32767, want: -32767}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: -1, want: -1}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: -1, want: -1}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: 0, want: 0}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: 0, want: 0}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: 1, want: 1}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: 1, want: 1}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: 32766, want: 32766}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: 32766, want: 32766}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: 32767, want: 32767}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: 32767, want: 32767}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: -32768, want: -32767}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: -32768, want: -32767}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: -32767, want: -32768}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: -32767, want: -32768}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: -1, want: -2}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: -1, want: -2}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: 0, want: 1}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: 0, want: 1}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: 1, want: 0}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: 1, want: 0}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: 32766, want: 32767}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: 32766, want: 32767}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: 32767, want: 32766}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: 32767, want: 32766}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: -32768, want: -2}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: -32768, want: -2}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: -32767, want: -1}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: -32767, want: -1}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: -1, want: -32767}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: -1, want: -32767}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: 0, want: 32766}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: 0, want: 32766}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: 1, want: 32767}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: 1, want: 32767}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: 32766, want: 0}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: 32766, want: 0}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: 32767, want: 1}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: 32767, want: 1}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: -32768, want: -1}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: -32768, want: -1}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: -32767, want: -2}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: -32767, want: -2}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: -1, want: -32768}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: -1, want: -32768}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: 0, want: 32767}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: 0, want: 32767}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: 1, want: 32766}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: 1, want: 32766}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: 32766, want: 1}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: 32766, want: 1}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: 32767, want: 0}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: 32767, want: 0}} type test_uint8 struct { fn func(uint8) uint8 fnname string in uint8 want uint8 } var tests_uint8 = []test_uint8{ test_uint8{fn: add_0_uint8, fnname: "add_0_uint8", in: 0, want: 0}, test_uint8{fn: add_uint8_0, fnname: "add_uint8_0", in: 0, want: 0}, test_uint8{fn: add_0_uint8, fnname: "add_0_uint8", in: 1, want: 1}, test_uint8{fn: add_uint8_0, fnname: "add_uint8_0", in: 1, want: 1}, test_uint8{fn: add_0_uint8, fnname: "add_0_uint8", in: 255, want: 255}, test_uint8{fn: add_uint8_0, fnname: "add_uint8_0", in: 255, want: 255}, test_uint8{fn: add_1_uint8, fnname: "add_1_uint8", in: 0, want: 1}, test_uint8{fn: add_uint8_1, fnname: "add_uint8_1", in: 0, want: 1}, test_uint8{fn: add_1_uint8, fnname: "add_1_uint8", in: 1, want: 2}, test_uint8{fn: add_uint8_1, fnname: "add_uint8_1", in: 1, want: 2}, test_uint8{fn: add_1_uint8, fnname: "add_1_uint8", in: 255, want: 0}, test_uint8{fn: add_uint8_1, fnname: "add_uint8_1", in: 255, want: 0}, test_uint8{fn: add_255_uint8, fnname: "add_255_uint8", in: 0, want: 255}, test_uint8{fn: add_uint8_255, fnname: "add_uint8_255", in: 0, want: 255}, test_uint8{fn: add_255_uint8, fnname: "add_255_uint8", in: 1, want: 0}, test_uint8{fn: add_uint8_255, fnname: "add_uint8_255", in: 1, want: 0}, test_uint8{fn: add_255_uint8, fnname: "add_255_uint8", in: 255, want: 254}, test_uint8{fn: add_uint8_255, fnname: "add_uint8_255", in: 255, want: 254}, test_uint8{fn: sub_0_uint8, fnname: "sub_0_uint8", in: 0, want: 0}, test_uint8{fn: sub_uint8_0, fnname: "sub_uint8_0", in: 0, want: 0}, test_uint8{fn: sub_0_uint8, fnname: "sub_0_uint8", in: 1, want: 255}, test_uint8{fn: sub_uint8_0, fnname: "sub_uint8_0", in: 1, want: 1}, test_uint8{fn: sub_0_uint8, fnname: "sub_0_uint8", in: 255, want: 1}, test_uint8{fn: sub_uint8_0, fnname: "sub_uint8_0", in: 255, want: 255}, test_uint8{fn: sub_1_uint8, fnname: "sub_1_uint8", in: 0, want: 1}, test_uint8{fn: sub_uint8_1, fnname: "sub_uint8_1", in: 0, want: 255}, test_uint8{fn: sub_1_uint8, fnname: "sub_1_uint8", in: 1, want: 0}, test_uint8{fn: sub_uint8_1, fnname: "sub_uint8_1", in: 1, want: 0}, test_uint8{fn: sub_1_uint8, fnname: "sub_1_uint8", in: 255, want: 2}, test_uint8{fn: sub_uint8_1, fnname: "sub_uint8_1", in: 255, want: 254}, test_uint8{fn: sub_255_uint8, fnname: "sub_255_uint8", in: 0, want: 255}, test_uint8{fn: sub_uint8_255, fnname: "sub_uint8_255", in: 0, want: 1}, test_uint8{fn: sub_255_uint8, fnname: "sub_255_uint8", in: 1, want: 254}, test_uint8{fn: sub_uint8_255, fnname: "sub_uint8_255", in: 1, want: 2}, test_uint8{fn: sub_255_uint8, fnname: "sub_255_uint8", in: 255, want: 0}, test_uint8{fn: sub_uint8_255, fnname: "sub_uint8_255", in: 255, want: 0}, test_uint8{fn: div_0_uint8, fnname: "div_0_uint8", in: 1, want: 0}, test_uint8{fn: div_0_uint8, fnname: "div_0_uint8", in: 255, want: 0}, test_uint8{fn: div_uint8_1, fnname: "div_uint8_1", in: 0, want: 0}, test_uint8{fn: div_1_uint8, fnname: "div_1_uint8", in: 1, want: 1}, test_uint8{fn: div_uint8_1, fnname: "div_uint8_1", in: 1, want: 1}, test_uint8{fn: div_1_uint8, fnname: "div_1_uint8", in: 255, want: 0}, test_uint8{fn: div_uint8_1, fnname: "div_uint8_1", in: 255, want: 255}, test_uint8{fn: div_uint8_255, fnname: "div_uint8_255", in: 0, want: 0}, test_uint8{fn: div_255_uint8, fnname: "div_255_uint8", in: 1, want: 255}, test_uint8{fn: div_uint8_255, fnname: "div_uint8_255", in: 1, want: 0}, test_uint8{fn: div_255_uint8, fnname: "div_255_uint8", in: 255, want: 1}, test_uint8{fn: div_uint8_255, fnname: "div_uint8_255", in: 255, want: 1}, test_uint8{fn: mul_0_uint8, fnname: "mul_0_uint8", in: 0, want: 0}, test_uint8{fn: mul_uint8_0, fnname: "mul_uint8_0", in: 0, want: 0}, test_uint8{fn: mul_0_uint8, fnname: "mul_0_uint8", in: 1, want: 0}, test_uint8{fn: mul_uint8_0, fnname: "mul_uint8_0", in: 1, want: 0}, test_uint8{fn: mul_0_uint8, fnname: "mul_0_uint8", in: 255, want: 0}, test_uint8{fn: mul_uint8_0, fnname: "mul_uint8_0", in: 255, want: 0}, test_uint8{fn: mul_1_uint8, fnname: "mul_1_uint8", in: 0, want: 0}, test_uint8{fn: mul_uint8_1, fnname: "mul_uint8_1", in: 0, want: 0}, test_uint8{fn: mul_1_uint8, fnname: "mul_1_uint8", in: 1, want: 1}, test_uint8{fn: mul_uint8_1, fnname: "mul_uint8_1", in: 1, want: 1}, test_uint8{fn: mul_1_uint8, fnname: "mul_1_uint8", in: 255, want: 255}, test_uint8{fn: mul_uint8_1, fnname: "mul_uint8_1", in: 255, want: 255}, test_uint8{fn: mul_255_uint8, fnname: "mul_255_uint8", in: 0, want: 0}, test_uint8{fn: mul_uint8_255, fnname: "mul_uint8_255", in: 0, want: 0}, test_uint8{fn: mul_255_uint8, fnname: "mul_255_uint8", in: 1, want: 255}, test_uint8{fn: mul_uint8_255, fnname: "mul_uint8_255", in: 1, want: 255}, test_uint8{fn: mul_255_uint8, fnname: "mul_255_uint8", in: 255, want: 1}, test_uint8{fn: mul_uint8_255, fnname: "mul_uint8_255", in: 255, want: 1}, test_uint8{fn: lsh_0_uint8, fnname: "lsh_0_uint8", in: 0, want: 0}, test_uint8{fn: lsh_uint8_0, fnname: "lsh_uint8_0", in: 0, want: 0}, test_uint8{fn: lsh_0_uint8, fnname: "lsh_0_uint8", in: 1, want: 0}, test_uint8{fn: lsh_uint8_0, fnname: "lsh_uint8_0", in: 1, want: 1}, test_uint8{fn: lsh_0_uint8, fnname: "lsh_0_uint8", in: 255, want: 0}, test_uint8{fn: lsh_uint8_0, fnname: "lsh_uint8_0", in: 255, want: 255}, test_uint8{fn: lsh_1_uint8, fnname: "lsh_1_uint8", in: 0, want: 1}, test_uint8{fn: lsh_uint8_1, fnname: "lsh_uint8_1", in: 0, want: 0}, test_uint8{fn: lsh_1_uint8, fnname: "lsh_1_uint8", in: 1, want: 2}, test_uint8{fn: lsh_uint8_1, fnname: "lsh_uint8_1", in: 1, want: 2}, test_uint8{fn: lsh_1_uint8, fnname: "lsh_1_uint8", in: 255, want: 0}, test_uint8{fn: lsh_uint8_1, fnname: "lsh_uint8_1", in: 255, want: 254}, test_uint8{fn: lsh_255_uint8, fnname: "lsh_255_uint8", in: 0, want: 255}, test_uint8{fn: lsh_uint8_255, fnname: "lsh_uint8_255", in: 0, want: 0}, test_uint8{fn: lsh_255_uint8, fnname: "lsh_255_uint8", in: 1, want: 254}, test_uint8{fn: lsh_uint8_255, fnname: "lsh_uint8_255", in: 1, want: 0}, test_uint8{fn: lsh_255_uint8, fnname: "lsh_255_uint8", in: 255, want: 0}, test_uint8{fn: lsh_uint8_255, fnname: "lsh_uint8_255", in: 255, want: 0}, test_uint8{fn: rsh_0_uint8, fnname: "rsh_0_uint8", in: 0, want: 0}, test_uint8{fn: rsh_uint8_0, fnname: "rsh_uint8_0", in: 0, want: 0}, test_uint8{fn: rsh_0_uint8, fnname: "rsh_0_uint8", in: 1, want: 0}, test_uint8{fn: rsh_uint8_0, fnname: "rsh_uint8_0", in: 1, want: 1}, test_uint8{fn: rsh_0_uint8, fnname: "rsh_0_uint8", in: 255, want: 0}, test_uint8{fn: rsh_uint8_0, fnname: "rsh_uint8_0", in: 255, want: 255}, test_uint8{fn: rsh_1_uint8, fnname: "rsh_1_uint8", in: 0, want: 1}, test_uint8{fn: rsh_uint8_1, fnname: "rsh_uint8_1", in: 0, want: 0}, test_uint8{fn: rsh_1_uint8, fnname: "rsh_1_uint8", in: 1, want: 0}, test_uint8{fn: rsh_uint8_1, fnname: "rsh_uint8_1", in: 1, want: 0}, test_uint8{fn: rsh_1_uint8, fnname: "rsh_1_uint8", in: 255, want: 0}, test_uint8{fn: rsh_uint8_1, fnname: "rsh_uint8_1", in: 255, want: 127}, test_uint8{fn: rsh_255_uint8, fnname: "rsh_255_uint8", in: 0, want: 255}, test_uint8{fn: rsh_uint8_255, fnname: "rsh_uint8_255", in: 0, want: 0}, test_uint8{fn: rsh_255_uint8, fnname: "rsh_255_uint8", in: 1, want: 127}, test_uint8{fn: rsh_uint8_255, fnname: "rsh_uint8_255", in: 1, want: 0}, test_uint8{fn: rsh_255_uint8, fnname: "rsh_255_uint8", in: 255, want: 0}, test_uint8{fn: rsh_uint8_255, fnname: "rsh_uint8_255", in: 255, want: 0}, test_uint8{fn: mod_0_uint8, fnname: "mod_0_uint8", in: 1, want: 0}, test_uint8{fn: mod_0_uint8, fnname: "mod_0_uint8", in: 255, want: 0}, test_uint8{fn: mod_uint8_1, fnname: "mod_uint8_1", in: 0, want: 0}, test_uint8{fn: mod_1_uint8, fnname: "mod_1_uint8", in: 1, want: 0}, test_uint8{fn: mod_uint8_1, fnname: "mod_uint8_1", in: 1, want: 0}, test_uint8{fn: mod_1_uint8, fnname: "mod_1_uint8", in: 255, want: 1}, test_uint8{fn: mod_uint8_1, fnname: "mod_uint8_1", in: 255, want: 0}, test_uint8{fn: mod_uint8_255, fnname: "mod_uint8_255", in: 0, want: 0}, test_uint8{fn: mod_255_uint8, fnname: "mod_255_uint8", in: 1, want: 0}, test_uint8{fn: mod_uint8_255, fnname: "mod_uint8_255", in: 1, want: 1}, test_uint8{fn: mod_255_uint8, fnname: "mod_255_uint8", in: 255, want: 0}, test_uint8{fn: mod_uint8_255, fnname: "mod_uint8_255", in: 255, want: 0}, test_uint8{fn: and_0_uint8, fnname: "and_0_uint8", in: 0, want: 0}, test_uint8{fn: and_uint8_0, fnname: "and_uint8_0", in: 0, want: 0}, test_uint8{fn: and_0_uint8, fnname: "and_0_uint8", in: 1, want: 0}, test_uint8{fn: and_uint8_0, fnname: "and_uint8_0", in: 1, want: 0}, test_uint8{fn: and_0_uint8, fnname: "and_0_uint8", in: 255, want: 0}, test_uint8{fn: and_uint8_0, fnname: "and_uint8_0", in: 255, want: 0}, test_uint8{fn: and_1_uint8, fnname: "and_1_uint8", in: 0, want: 0}, test_uint8{fn: and_uint8_1, fnname: "and_uint8_1", in: 0, want: 0}, test_uint8{fn: and_1_uint8, fnname: "and_1_uint8", in: 1, want: 1}, test_uint8{fn: and_uint8_1, fnname: "and_uint8_1", in: 1, want: 1}, test_uint8{fn: and_1_uint8, fnname: "and_1_uint8", in: 255, want: 1}, test_uint8{fn: and_uint8_1, fnname: "and_uint8_1", in: 255, want: 1}, test_uint8{fn: and_255_uint8, fnname: "and_255_uint8", in: 0, want: 0}, test_uint8{fn: and_uint8_255, fnname: "and_uint8_255", in: 0, want: 0}, test_uint8{fn: and_255_uint8, fnname: "and_255_uint8", in: 1, want: 1}, test_uint8{fn: and_uint8_255, fnname: "and_uint8_255", in: 1, want: 1}, test_uint8{fn: and_255_uint8, fnname: "and_255_uint8", in: 255, want: 255}, test_uint8{fn: and_uint8_255, fnname: "and_uint8_255", in: 255, want: 255}, test_uint8{fn: or_0_uint8, fnname: "or_0_uint8", in: 0, want: 0}, test_uint8{fn: or_uint8_0, fnname: "or_uint8_0", in: 0, want: 0}, test_uint8{fn: or_0_uint8, fnname: "or_0_uint8", in: 1, want: 1}, test_uint8{fn: or_uint8_0, fnname: "or_uint8_0", in: 1, want: 1}, test_uint8{fn: or_0_uint8, fnname: "or_0_uint8", in: 255, want: 255}, test_uint8{fn: or_uint8_0, fnname: "or_uint8_0", in: 255, want: 255}, test_uint8{fn: or_1_uint8, fnname: "or_1_uint8", in: 0, want: 1}, test_uint8{fn: or_uint8_1, fnname: "or_uint8_1", in: 0, want: 1}, test_uint8{fn: or_1_uint8, fnname: "or_1_uint8", in: 1, want: 1}, test_uint8{fn: or_uint8_1, fnname: "or_uint8_1", in: 1, want: 1}, test_uint8{fn: or_1_uint8, fnname: "or_1_uint8", in: 255, want: 255}, test_uint8{fn: or_uint8_1, fnname: "or_uint8_1", in: 255, want: 255}, test_uint8{fn: or_255_uint8, fnname: "or_255_uint8", in: 0, want: 255}, test_uint8{fn: or_uint8_255, fnname: "or_uint8_255", in: 0, want: 255}, test_uint8{fn: or_255_uint8, fnname: "or_255_uint8", in: 1, want: 255}, test_uint8{fn: or_uint8_255, fnname: "or_uint8_255", in: 1, want: 255}, test_uint8{fn: or_255_uint8, fnname: "or_255_uint8", in: 255, want: 255}, test_uint8{fn: or_uint8_255, fnname: "or_uint8_255", in: 255, want: 255}, test_uint8{fn: xor_0_uint8, fnname: "xor_0_uint8", in: 0, want: 0}, test_uint8{fn: xor_uint8_0, fnname: "xor_uint8_0", in: 0, want: 0}, test_uint8{fn: xor_0_uint8, fnname: "xor_0_uint8", in: 1, want: 1}, test_uint8{fn: xor_uint8_0, fnname: "xor_uint8_0", in: 1, want: 1}, test_uint8{fn: xor_0_uint8, fnname: "xor_0_uint8", in: 255, want: 255}, test_uint8{fn: xor_uint8_0, fnname: "xor_uint8_0", in: 255, want: 255}, test_uint8{fn: xor_1_uint8, fnname: "xor_1_uint8", in: 0, want: 1}, test_uint8{fn: xor_uint8_1, fnname: "xor_uint8_1", in: 0, want: 1}, test_uint8{fn: xor_1_uint8, fnname: "xor_1_uint8", in: 1, want: 0}, test_uint8{fn: xor_uint8_1, fnname: "xor_uint8_1", in: 1, want: 0}, test_uint8{fn: xor_1_uint8, fnname: "xor_1_uint8", in: 255, want: 254}, test_uint8{fn: xor_uint8_1, fnname: "xor_uint8_1", in: 255, want: 254}, test_uint8{fn: xor_255_uint8, fnname: "xor_255_uint8", in: 0, want: 255}, test_uint8{fn: xor_uint8_255, fnname: "xor_uint8_255", in: 0, want: 255}, test_uint8{fn: xor_255_uint8, fnname: "xor_255_uint8", in: 1, want: 254}, test_uint8{fn: xor_uint8_255, fnname: "xor_uint8_255", in: 1, want: 254}, test_uint8{fn: xor_255_uint8, fnname: "xor_255_uint8", in: 255, want: 0}, test_uint8{fn: xor_uint8_255, fnname: "xor_uint8_255", in: 255, want: 0}} type test_int8 struct { fn func(int8) int8 fnname string in int8 want int8 } var tests_int8 = []test_int8{ test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: -128, want: 0}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: -128, want: 0}, test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: -127, want: 1}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: -127, want: 1}, test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: -1, want: 127}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: -1, want: 127}, test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: 0, want: -128}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: 0, want: -128}, test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: 1, want: -127}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: 1, want: -127}, test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: 126, want: -2}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: 126, want: -2}, test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: 127, want: -1}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: 127, want: -1}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: -128, want: 1}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: -128, want: 1}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: -127, want: 2}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: -127, want: 2}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: -1, want: -128}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: -1, want: -128}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: 0, want: -127}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: 0, want: -127}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: 1, want: -126}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: 1, want: -126}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: 126, want: -1}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: 126, want: -1}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: 127, want: 0}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: 127, want: 0}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: -128, want: 127}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: -128, want: 127}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: -127, want: -128}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: -127, want: -128}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: -1, want: -2}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: -1, want: -2}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: 0, want: -1}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: 0, want: -1}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: 1, want: 0}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: 1, want: 0}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: 126, want: 125}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: 126, want: 125}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: 127, want: 126}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: 127, want: 126}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: -128, want: -128}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: -128, want: -128}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: -127, want: -127}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: -127, want: -127}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: -1, want: -1}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: -1, want: -1}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: 0, want: 0}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: 0, want: 0}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: 1, want: 1}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: 1, want: 1}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: 126, want: 126}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: 126, want: 126}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: 127, want: 127}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: 127, want: 127}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: -128, want: -127}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: -128, want: -127}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: -127, want: -126}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: -127, want: -126}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: -1, want: 0}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: -1, want: 0}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: 0, want: 1}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: 0, want: 1}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: 1, want: 2}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: 1, want: 2}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: 126, want: 127}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: 126, want: 127}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: 127, want: -128}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: 127, want: -128}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: -128, want: -2}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: -128, want: -2}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: -127, want: -1}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: -127, want: -1}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: -1, want: 125}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: -1, want: 125}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: 0, want: 126}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: 0, want: 126}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: 1, want: 127}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: 1, want: 127}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: 126, want: -4}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: 126, want: -4}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: 127, want: -3}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: 127, want: -3}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: -128, want: -1}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: -128, want: -1}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: -127, want: 0}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: -127, want: 0}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: -1, want: 126}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: -1, want: 126}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: 0, want: 127}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: 0, want: 127}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: 1, want: -128}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: 1, want: -128}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: 126, want: -3}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: 126, want: -3}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: 127, want: -2}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: 127, want: -2}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: -128, want: 0}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: -128, want: 0}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: -127, want: -1}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: -127, want: 1}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: -1, want: -127}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: -1, want: 127}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: 0, want: -128}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: 0, want: -128}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: 1, want: 127}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: 1, want: -127}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: 126, want: 2}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: 126, want: -2}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: 127, want: 1}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: 127, want: -1}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: -128, want: 1}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: -128, want: -1}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: -127, want: 0}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: -127, want: 0}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: -1, want: -126}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: -1, want: 126}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: 0, want: -127}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: 0, want: 127}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: 1, want: -128}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: 1, want: -128}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: 126, want: 3}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: 126, want: -3}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: 127, want: 2}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: 127, want: -2}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: -128, want: 127}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: -128, want: -127}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: -127, want: 126}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: -127, want: -126}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: -1, want: 0}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: -1, want: 0}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: 0, want: -1}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: 0, want: 1}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: 1, want: -2}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: 1, want: 2}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: 126, want: -127}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: 126, want: 127}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: 127, want: -128}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: 127, want: -128}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: -128, want: -128}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: -128, want: -128}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: -127, want: 127}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: -127, want: -127}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: -1, want: 1}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: -1, want: -1}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: 0, want: 0}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: 0, want: 0}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: 1, want: -1}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: 1, want: 1}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: 126, want: -126}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: 126, want: 126}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: 127, want: -127}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: 127, want: 127}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: -128, want: -127}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: -128, want: 127}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: -127, want: -128}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: -127, want: -128}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: -1, want: 2}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: -1, want: -2}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: 0, want: 1}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: 0, want: -1}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: 1, want: 0}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: 1, want: 0}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: 126, want: -125}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: 126, want: 125}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: 127, want: -126}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: 127, want: 126}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: -128, want: -2}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: -128, want: 2}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: -127, want: -3}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: -127, want: 3}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: -1, want: 127}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: -1, want: -127}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: 0, want: 126}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: 0, want: -126}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: 1, want: 125}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: 1, want: -125}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: 126, want: 0}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: 126, want: 0}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: 127, want: -1}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: 127, want: 1}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: -128, want: -1}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: -128, want: 1}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: -127, want: -2}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: -127, want: 2}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: -1, want: -128}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: -1, want: -128}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: 0, want: 127}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: 0, want: -127}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: 1, want: 126}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: 1, want: -126}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: 126, want: 1}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: 126, want: -1}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: 127, want: 0}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: 127, want: 0}, test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: -128, want: 1}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: -128, want: 1}, test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: -127, want: 1}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: -127, want: 0}, test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: -1, want: -128}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: -1, want: 0}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: 0, want: 0}, test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: 1, want: -128}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: 1, want: 0}, test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: 126, want: -1}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: 126, want: 0}, test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: 127, want: -1}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: 127, want: 0}, test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: -128, want: 0}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: -128, want: 1}, test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: -127, want: 1}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: -127, want: 1}, test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: -1, want: 127}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: -1, want: 0}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: 0, want: 0}, test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: 1, want: -127}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: 1, want: 0}, test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: 126, want: -1}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: 126, want: 0}, test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: 127, want: -1}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: 127, want: -1}, test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: -128, want: 0}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: -128, want: -128}, test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: -127, want: 0}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: -127, want: 127}, test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: -1, want: 1}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: -1, want: 1}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: 0, want: 0}, test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: 1, want: -1}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: 1, want: -1}, test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: 126, want: 0}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: 126, want: -126}, test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: 127, want: 0}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: 127, want: -127}, test_int8{fn: div_0_int8, fnname: "div_0_int8", in: -128, want: 0}, test_int8{fn: div_0_int8, fnname: "div_0_int8", in: -127, want: 0}, test_int8{fn: div_0_int8, fnname: "div_0_int8", in: -1, want: 0}, test_int8{fn: div_0_int8, fnname: "div_0_int8", in: 1, want: 0}, test_int8{fn: div_0_int8, fnname: "div_0_int8", in: 126, want: 0}, test_int8{fn: div_0_int8, fnname: "div_0_int8", in: 127, want: 0}, test_int8{fn: div_1_int8, fnname: "div_1_int8", in: -128, want: 0}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: -128, want: -128}, test_int8{fn: div_1_int8, fnname: "div_1_int8", in: -127, want: 0}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: -127, want: -127}, test_int8{fn: div_1_int8, fnname: "div_1_int8", in: -1, want: -1}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: -1, want: -1}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: 0, want: 0}, test_int8{fn: div_1_int8, fnname: "div_1_int8", in: 1, want: 1}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: 1, want: 1}, test_int8{fn: div_1_int8, fnname: "div_1_int8", in: 126, want: 0}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: 126, want: 126}, test_int8{fn: div_1_int8, fnname: "div_1_int8", in: 127, want: 0}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: 127, want: 127}, test_int8{fn: div_126_int8, fnname: "div_126_int8", in: -128, want: 0}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: -128, want: -1}, test_int8{fn: div_126_int8, fnname: "div_126_int8", in: -127, want: 0}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: -127, want: -1}, test_int8{fn: div_126_int8, fnname: "div_126_int8", in: -1, want: -126}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: -1, want: 0}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: 0, want: 0}, test_int8{fn: div_126_int8, fnname: "div_126_int8", in: 1, want: 126}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: 1, want: 0}, test_int8{fn: div_126_int8, fnname: "div_126_int8", in: 126, want: 1}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: 126, want: 1}, test_int8{fn: div_126_int8, fnname: "div_126_int8", in: 127, want: 0}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: 127, want: 1}, test_int8{fn: div_127_int8, fnname: "div_127_int8", in: -128, want: 0}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: -128, want: -1}, test_int8{fn: div_127_int8, fnname: "div_127_int8", in: -127, want: -1}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: -127, want: -1}, test_int8{fn: div_127_int8, fnname: "div_127_int8", in: -1, want: -127}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: -1, want: 0}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: 0, want: 0}, test_int8{fn: div_127_int8, fnname: "div_127_int8", in: 1, want: 127}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: 1, want: 0}, test_int8{fn: div_127_int8, fnname: "div_127_int8", in: 126, want: 1}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: 126, want: 0}, test_int8{fn: div_127_int8, fnname: "div_127_int8", in: 127, want: 1}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: 127, want: 1}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: -128, want: 0}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: -128, want: 0}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: -127, want: -128}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: -127, want: -128}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: -1, want: -128}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: -1, want: -128}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: 0, want: 0}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: 0, want: 0}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: 1, want: -128}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: 1, want: -128}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: 126, want: 0}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: 126, want: 0}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: 127, want: -128}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: 127, want: -128}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: -128, want: -128}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: -128, want: -128}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: -127, want: 1}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: -127, want: 1}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: -1, want: 127}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: -1, want: 127}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: 0, want: 0}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: 0, want: 0}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: 1, want: -127}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: 1, want: -127}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: 126, want: 126}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: 126, want: 126}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: 127, want: -1}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: 127, want: -1}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: -128, want: -128}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: -128, want: -128}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: -127, want: 127}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: -127, want: 127}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: -1, want: 1}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: -1, want: 1}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: 0, want: 0}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: 0, want: 0}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: 1, want: -1}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: 1, want: -1}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: 126, want: -126}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: 126, want: -126}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: 127, want: -127}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: 127, want: -127}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: -128, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: -128, want: 0}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: -127, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: -127, want: 0}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: -1, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: -1, want: 0}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: 0, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: 0, want: 0}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: 1, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: 1, want: 0}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: 126, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: 126, want: 0}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: 127, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: 127, want: 0}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: -128, want: -128}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: -128, want: -128}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: -127, want: -127}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: -127, want: -127}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: -1, want: -1}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: -1, want: -1}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: 0, want: 0}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: 0, want: 0}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: 1, want: 1}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: 1, want: 1}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: 126, want: 126}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: 126, want: 126}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: 127, want: 127}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: 127, want: 127}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: -128, want: 0}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: -128, want: 0}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: -127, want: 126}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: -127, want: 126}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: -1, want: -126}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: -1, want: -126}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: 0, want: 0}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: 0, want: 0}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: 1, want: 126}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: 1, want: 126}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: 126, want: 4}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: 126, want: 4}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: 127, want: -126}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: 127, want: -126}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: -128, want: -128}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: -128, want: -128}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: -127, want: -1}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: -127, want: -1}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: -1, want: -127}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: -1, want: -127}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: 0, want: 0}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: 0, want: 0}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: 1, want: 127}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: 1, want: 127}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: 126, want: -126}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: 126, want: -126}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: 127, want: 1}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: 127, want: 1}, test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: -128, want: 0}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: -128, want: 0}, test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: -127, want: -1}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: -127, want: -127}, test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: -1, want: 0}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: -1, want: -1}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: 0, want: 0}, test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: 1, want: 0}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: 1, want: 1}, test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: 126, want: -2}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: 126, want: 126}, test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: 127, want: -1}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: 127, want: 127}, test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: -128, want: -127}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: -128, want: -1}, test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: -127, want: 0}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: -127, want: 0}, test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: -1, want: 0}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: -1, want: -1}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: 0, want: 0}, test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: 1, want: 0}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: 1, want: 1}, test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: 126, want: -1}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: 126, want: 126}, test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: 127, want: 0}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: 127, want: 0}, test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: -128, want: -1}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: -128, want: 0}, test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: -127, want: -1}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: -127, want: 0}, test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: -1, want: 0}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: -1, want: 0}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: 0, want: 0}, test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: 1, want: 0}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: 1, want: 0}, test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: 126, want: -1}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: 126, want: 0}, test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: 127, want: -1}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: 127, want: 0}, test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: -128, want: 0}, test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: -127, want: 0}, test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: -1, want: 0}, test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: 1, want: 0}, test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: 126, want: 0}, test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: 127, want: 0}, test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: -128, want: 1}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: -128, want: 0}, test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: -127, want: 1}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: -127, want: 0}, test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: -1, want: 0}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: -1, want: 0}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: 0, want: 0}, test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: 1, want: 0}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: 1, want: 0}, test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: 126, want: 1}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: 126, want: 0}, test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: 127, want: 1}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: 127, want: 0}, test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: -128, want: 126}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: -128, want: -2}, test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: -127, want: 126}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: -127, want: -1}, test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: -1, want: 0}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: -1, want: -1}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: 0, want: 0}, test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: 1, want: 0}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: 1, want: 1}, test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: 126, want: 0}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: 126, want: 0}, test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: 127, want: 126}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: 127, want: 1}, test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: -128, want: 127}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: -128, want: -1}, test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: -127, want: 0}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: -127, want: 0}, test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: -1, want: 0}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: -1, want: -1}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: 0, want: 0}, test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: 1, want: 0}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: 1, want: 1}, test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: 126, want: 1}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: 126, want: 126}, test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: 127, want: 0}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: 127, want: 0}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: -128, want: -128}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: -128, want: -128}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: -127, want: -128}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: -127, want: -128}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: -1, want: -128}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: -1, want: -128}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: 0, want: 0}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: 0, want: 0}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: 1, want: 0}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: 1, want: 0}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: 126, want: 0}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: 126, want: 0}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: 127, want: 0}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: 127, want: 0}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: -128, want: -128}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: -128, want: -128}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: -127, want: -127}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: -127, want: -127}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: -1, want: -127}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: -1, want: -127}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: 0, want: 0}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: 0, want: 0}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: 1, want: 1}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: 1, want: 1}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: 126, want: 0}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: 126, want: 0}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: 127, want: 1}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: 127, want: 1}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: -128, want: -128}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: -128, want: -128}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: -127, want: -127}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: -127, want: -127}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: -1, want: -1}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: -1, want: -1}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: 0, want: 0}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: 0, want: 0}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: 1, want: 1}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: 1, want: 1}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: 126, want: 126}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: 126, want: 126}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: 127, want: 127}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: 127, want: 127}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: -128, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: -128, want: 0}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: -127, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: -127, want: 0}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: -1, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: -1, want: 0}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: 0, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: 0, want: 0}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: 1, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: 1, want: 0}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: 126, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: 126, want: 0}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: 127, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: 127, want: 0}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: -128, want: 0}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: -128, want: 0}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: -127, want: 1}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: -127, want: 1}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: -1, want: 1}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: -1, want: 1}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: 0, want: 0}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: 0, want: 0}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: 1, want: 1}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: 1, want: 1}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: 126, want: 0}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: 126, want: 0}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: 127, want: 1}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: 127, want: 1}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: -128, want: 0}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: -128, want: 0}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: -127, want: 0}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: -127, want: 0}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: -1, want: 126}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: -1, want: 126}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: 0, want: 0}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: 0, want: 0}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: 1, want: 0}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: 1, want: 0}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: 126, want: 126}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: 126, want: 126}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: 127, want: 126}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: 127, want: 126}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: -128, want: 0}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: -128, want: 0}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: -127, want: 1}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: -127, want: 1}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: -1, want: 127}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: -1, want: 127}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: 0, want: 0}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: 0, want: 0}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: 1, want: 1}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: 1, want: 1}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: 126, want: 126}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: 126, want: 126}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: 127, want: 127}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: 127, want: 127}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: -128, want: -128}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: -128, want: -128}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: -127, want: -127}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: -127, want: -127}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: -1, want: -1}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: -1, want: -1}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: 0, want: -128}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: 0, want: -128}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: 1, want: -127}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: 1, want: -127}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: 126, want: -2}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: 126, want: -2}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: 127, want: -1}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: 127, want: -1}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: -128, want: -127}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: -128, want: -127}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: -127, want: -127}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: -127, want: -127}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: -1, want: -1}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: -1, want: -1}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: 0, want: -127}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: 0, want: -127}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: 1, want: -127}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: 1, want: -127}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: 126, want: -1}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: 126, want: -1}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: 127, want: -1}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: 127, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: -128, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: -128, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: -127, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: -127, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: -1, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: -1, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: 0, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: 0, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: 1, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: 1, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: 126, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: 126, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: 127, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: 127, want: -1}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: -128, want: -128}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: -128, want: -128}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: -127, want: -127}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: -127, want: -127}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: -1, want: -1}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: -1, want: -1}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: 0, want: 0}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: 0, want: 0}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: 1, want: 1}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: 1, want: 1}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: 126, want: 126}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: 126, want: 126}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: 127, want: 127}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: 127, want: 127}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: -128, want: -127}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: -128, want: -127}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: -127, want: -127}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: -127, want: -127}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: -1, want: -1}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: -1, want: -1}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: 0, want: 1}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: 0, want: 1}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: 1, want: 1}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: 1, want: 1}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: 126, want: 127}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: 126, want: 127}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: 127, want: 127}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: 127, want: 127}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: -128, want: -2}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: -128, want: -2}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: -127, want: -1}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: -127, want: -1}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: -1, want: -1}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: -1, want: -1}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: 0, want: 126}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: 0, want: 126}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: 1, want: 127}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: 1, want: 127}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: 126, want: 126}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: 126, want: 126}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: 127, want: 127}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: 127, want: 127}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: -128, want: -1}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: -128, want: -1}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: -127, want: -1}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: -127, want: -1}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: -1, want: -1}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: -1, want: -1}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: 0, want: 127}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: 0, want: 127}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: 1, want: 127}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: 1, want: 127}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: 126, want: 127}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: 126, want: 127}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: 127, want: 127}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: 127, want: 127}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: -128, want: 0}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: -128, want: 0}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: -127, want: 1}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: -127, want: 1}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: -1, want: 127}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: -1, want: 127}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: 0, want: -128}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: 0, want: -128}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: 1, want: -127}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: 1, want: -127}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: 126, want: -2}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: 126, want: -2}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: 127, want: -1}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: 127, want: -1}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: -128, want: 1}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: -128, want: 1}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: -127, want: 0}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: -127, want: 0}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: -1, want: 126}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: -1, want: 126}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: 0, want: -127}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: 0, want: -127}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: 1, want: -128}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: 1, want: -128}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: 126, want: -1}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: 126, want: -1}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: 127, want: -2}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: 127, want: -2}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: -128, want: 127}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: -128, want: 127}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: -127, want: 126}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: -127, want: 126}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: -1, want: 0}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: -1, want: 0}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: 0, want: -1}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: 0, want: -1}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: 1, want: -2}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: 1, want: -2}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: 126, want: -127}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: 126, want: -127}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: 127, want: -128}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: 127, want: -128}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: -128, want: -128}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: -128, want: -128}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: -127, want: -127}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: -127, want: -127}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: -1, want: -1}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: -1, want: -1}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: 0, want: 0}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: 0, want: 0}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: 1, want: 1}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: 1, want: 1}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: 126, want: 126}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: 126, want: 126}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: 127, want: 127}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: 127, want: 127}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: -128, want: -127}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: -128, want: -127}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: -127, want: -128}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: -127, want: -128}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: -1, want: -2}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: -1, want: -2}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: 0, want: 1}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: 0, want: 1}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: 1, want: 0}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: 1, want: 0}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: 126, want: 127}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: 126, want: 127}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: 127, want: 126}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: 127, want: 126}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: -128, want: -2}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: -128, want: -2}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: -127, want: -1}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: -127, want: -1}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: -1, want: -127}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: -1, want: -127}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: 0, want: 126}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: 0, want: 126}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: 1, want: 127}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: 1, want: 127}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: 126, want: 0}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: 126, want: 0}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: 127, want: 1}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: 127, want: 1}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: -128, want: -1}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: -128, want: -1}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: -127, want: -2}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: -127, want: -2}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: -1, want: -128}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: -1, want: -128}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: 0, want: 127}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: 0, want: 127}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: 1, want: 126}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: 1, want: 126}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: 126, want: 1}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: 126, want: 1}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: 127, want: 0}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: 127, want: 0}} var failed bool func main() { for _, test := range tests_uint64 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_int64 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_uint32 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_int32 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_uint16 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_int16 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_uint8 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_int8 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } if failed { os.Exit(1) } }diff-1.0.1/internal/benchmarks/testdata/large_03.test000066400000000000000000052627301516001707200224760ustar00rootroot00000000000000From https://go.googlesource.com/go commit 60ad3c48f59c35981dd872ed5dfe74e4d6becab2 file src/cmd/compile/internal/ssa/rewritegeneric.go -- x -- // Code generated from gen/generic.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/compile/internal/types" func rewriteValuegeneric(v *Value) bool { switch v.Op { case OpAdd16: return rewriteValuegeneric_OpAdd16(v) case OpAdd32: return rewriteValuegeneric_OpAdd32(v) case OpAdd32F: return rewriteValuegeneric_OpAdd32F(v) case OpAdd64: return rewriteValuegeneric_OpAdd64(v) case OpAdd64F: return rewriteValuegeneric_OpAdd64F(v) case OpAdd8: return rewriteValuegeneric_OpAdd8(v) case OpAddPtr: return rewriteValuegeneric_OpAddPtr(v) case OpAnd16: return rewriteValuegeneric_OpAnd16(v) case OpAnd32: return rewriteValuegeneric_OpAnd32(v) case OpAnd64: return rewriteValuegeneric_OpAnd64(v) case OpAnd8: return rewriteValuegeneric_OpAnd8(v) case OpAndB: return rewriteValuegeneric_OpAndB(v) case OpArraySelect: return rewriteValuegeneric_OpArraySelect(v) case OpCom16: return rewriteValuegeneric_OpCom16(v) case OpCom32: return rewriteValuegeneric_OpCom32(v) case OpCom64: return rewriteValuegeneric_OpCom64(v) case OpCom8: return rewriteValuegeneric_OpCom8(v) case OpConstInterface: return rewriteValuegeneric_OpConstInterface(v) case OpConstSlice: return rewriteValuegeneric_OpConstSlice(v) case OpConstString: return rewriteValuegeneric_OpConstString(v) case OpConvert: return rewriteValuegeneric_OpConvert(v) case OpCtz16: return rewriteValuegeneric_OpCtz16(v) case OpCtz32: return rewriteValuegeneric_OpCtz32(v) case OpCtz64: return rewriteValuegeneric_OpCtz64(v) case OpCtz8: return rewriteValuegeneric_OpCtz8(v) case OpCvt32Fto32: return rewriteValuegeneric_OpCvt32Fto32(v) case OpCvt32Fto64: return rewriteValuegeneric_OpCvt32Fto64(v) case OpCvt32Fto64F: return rewriteValuegeneric_OpCvt32Fto64F(v) case OpCvt32to32F: return rewriteValuegeneric_OpCvt32to32F(v) case OpCvt32to64F: return rewriteValuegeneric_OpCvt32to64F(v) case OpCvt64Fto32: return rewriteValuegeneric_OpCvt64Fto32(v) case OpCvt64Fto32F: return rewriteValuegeneric_OpCvt64Fto32F(v) case OpCvt64Fto64: return rewriteValuegeneric_OpCvt64Fto64(v) case OpCvt64to32F: return rewriteValuegeneric_OpCvt64to32F(v) case OpCvt64to64F: return rewriteValuegeneric_OpCvt64to64F(v) case OpCvtBoolToUint8: return rewriteValuegeneric_OpCvtBoolToUint8(v) case OpDiv16: return rewriteValuegeneric_OpDiv16(v) case OpDiv16u: return rewriteValuegeneric_OpDiv16u(v) case OpDiv32: return rewriteValuegeneric_OpDiv32(v) case OpDiv32F: return rewriteValuegeneric_OpDiv32F(v) case OpDiv32u: return rewriteValuegeneric_OpDiv32u(v) case OpDiv64: return rewriteValuegeneric_OpDiv64(v) case OpDiv64F: return rewriteValuegeneric_OpDiv64F(v) case OpDiv64u: return rewriteValuegeneric_OpDiv64u(v) case OpDiv8: return rewriteValuegeneric_OpDiv8(v) case OpDiv8u: return rewriteValuegeneric_OpDiv8u(v) case OpEq16: return rewriteValuegeneric_OpEq16(v) case OpEq32: return rewriteValuegeneric_OpEq32(v) case OpEq32F: return rewriteValuegeneric_OpEq32F(v) case OpEq64: return rewriteValuegeneric_OpEq64(v) case OpEq64F: return rewriteValuegeneric_OpEq64F(v) case OpEq8: return rewriteValuegeneric_OpEq8(v) case OpEqB: return rewriteValuegeneric_OpEqB(v) case OpEqInter: return rewriteValuegeneric_OpEqInter(v) case OpEqPtr: return rewriteValuegeneric_OpEqPtr(v) case OpEqSlice: return rewriteValuegeneric_OpEqSlice(v) case OpIMake: return rewriteValuegeneric_OpIMake(v) case OpInterLECall: return rewriteValuegeneric_OpInterLECall(v) case OpIsInBounds: return rewriteValuegeneric_OpIsInBounds(v) case OpIsNonNil: return rewriteValuegeneric_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValuegeneric_OpIsSliceInBounds(v) case OpLeq16: return rewriteValuegeneric_OpLeq16(v) case OpLeq16U: return rewriteValuegeneric_OpLeq16U(v) case OpLeq32: return rewriteValuegeneric_OpLeq32(v) case OpLeq32F: return rewriteValuegeneric_OpLeq32F(v) case OpLeq32U: return rewriteValuegeneric_OpLeq32U(v) case OpLeq64: return rewriteValuegeneric_OpLeq64(v) case OpLeq64F: return rewriteValuegeneric_OpLeq64F(v) case OpLeq64U: return rewriteValuegeneric_OpLeq64U(v) case OpLeq8: return rewriteValuegeneric_OpLeq8(v) case OpLeq8U: return rewriteValuegeneric_OpLeq8U(v) case OpLess16: return rewriteValuegeneric_OpLess16(v) case OpLess16U: return rewriteValuegeneric_OpLess16U(v) case OpLess32: return rewriteValuegeneric_OpLess32(v) case OpLess32F: return rewriteValuegeneric_OpLess32F(v) case OpLess32U: return rewriteValuegeneric_OpLess32U(v) case OpLess64: return rewriteValuegeneric_OpLess64(v) case OpLess64F: return rewriteValuegeneric_OpLess64F(v) case OpLess64U: return rewriteValuegeneric_OpLess64U(v) case OpLess8: return rewriteValuegeneric_OpLess8(v) case OpLess8U: return rewriteValuegeneric_OpLess8U(v) case OpLoad: return rewriteValuegeneric_OpLoad(v) case OpLsh16x16: return rewriteValuegeneric_OpLsh16x16(v) case OpLsh16x32: return rewriteValuegeneric_OpLsh16x32(v) case OpLsh16x64: return rewriteValuegeneric_OpLsh16x64(v) case OpLsh16x8: return rewriteValuegeneric_OpLsh16x8(v) case OpLsh32x16: return rewriteValuegeneric_OpLsh32x16(v) case OpLsh32x32: return rewriteValuegeneric_OpLsh32x32(v) case OpLsh32x64: return rewriteValuegeneric_OpLsh32x64(v) case OpLsh32x8: return rewriteValuegeneric_OpLsh32x8(v) case OpLsh64x16: return rewriteValuegeneric_OpLsh64x16(v) case OpLsh64x32: return rewriteValuegeneric_OpLsh64x32(v) case OpLsh64x64: return rewriteValuegeneric_OpLsh64x64(v) case OpLsh64x8: return rewriteValuegeneric_OpLsh64x8(v) case OpLsh8x16: return rewriteValuegeneric_OpLsh8x16(v) case OpLsh8x32: return rewriteValuegeneric_OpLsh8x32(v) case OpLsh8x64: return rewriteValuegeneric_OpLsh8x64(v) case OpLsh8x8: return rewriteValuegeneric_OpLsh8x8(v) case OpMod16: return rewriteValuegeneric_OpMod16(v) case OpMod16u: return rewriteValuegeneric_OpMod16u(v) case OpMod32: return rewriteValuegeneric_OpMod32(v) case OpMod32u: return rewriteValuegeneric_OpMod32u(v) case OpMod64: return rewriteValuegeneric_OpMod64(v) case OpMod64u: return rewriteValuegeneric_OpMod64u(v) case OpMod8: return rewriteValuegeneric_OpMod8(v) case OpMod8u: return rewriteValuegeneric_OpMod8u(v) case OpMove: return rewriteValuegeneric_OpMove(v) case OpMul16: return rewriteValuegeneric_OpMul16(v) case OpMul32: return rewriteValuegeneric_OpMul32(v) case OpMul32F: return rewriteValuegeneric_OpMul32F(v) case OpMul64: return rewriteValuegeneric_OpMul64(v) case OpMul64F: return rewriteValuegeneric_OpMul64F(v) case OpMul8: return rewriteValuegeneric_OpMul8(v) case OpNeg16: return rewriteValuegeneric_OpNeg16(v) case OpNeg32: return rewriteValuegeneric_OpNeg32(v) case OpNeg32F: return rewriteValuegeneric_OpNeg32F(v) case OpNeg64: return rewriteValuegeneric_OpNeg64(v) case OpNeg64F: return rewriteValuegeneric_OpNeg64F(v) case OpNeg8: return rewriteValuegeneric_OpNeg8(v) case OpNeq16: return rewriteValuegeneric_OpNeq16(v) case OpNeq32: return rewriteValuegeneric_OpNeq32(v) case OpNeq32F: return rewriteValuegeneric_OpNeq32F(v) case OpNeq64: return rewriteValuegeneric_OpNeq64(v) case OpNeq64F: return rewriteValuegeneric_OpNeq64F(v) case OpNeq8: return rewriteValuegeneric_OpNeq8(v) case OpNeqB: return rewriteValuegeneric_OpNeqB(v) case OpNeqInter: return rewriteValuegeneric_OpNeqInter(v) case OpNeqPtr: return rewriteValuegeneric_OpNeqPtr(v) case OpNeqSlice: return rewriteValuegeneric_OpNeqSlice(v) case OpNilCheck: return rewriteValuegeneric_OpNilCheck(v) case OpNot: return rewriteValuegeneric_OpNot(v) case OpOffPtr: return rewriteValuegeneric_OpOffPtr(v) case OpOr16: return rewriteValuegeneric_OpOr16(v) case OpOr32: return rewriteValuegeneric_OpOr32(v) case OpOr64: return rewriteValuegeneric_OpOr64(v) case OpOr8: return rewriteValuegeneric_OpOr8(v) case OpOrB: return rewriteValuegeneric_OpOrB(v) case OpPhi: return rewriteValuegeneric_OpPhi(v) case OpPtrIndex: return rewriteValuegeneric_OpPtrIndex(v) case OpRotateLeft16: return rewriteValuegeneric_OpRotateLeft16(v) case OpRotateLeft32: return rewriteValuegeneric_OpRotateLeft32(v) case OpRotateLeft64: return rewriteValuegeneric_OpRotateLeft64(v) case OpRotateLeft8: return rewriteValuegeneric_OpRotateLeft8(v) case OpRound32F: return rewriteValuegeneric_OpRound32F(v) case OpRound64F: return rewriteValuegeneric_OpRound64F(v) case OpRsh16Ux16: return rewriteValuegeneric_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValuegeneric_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValuegeneric_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValuegeneric_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValuegeneric_OpRsh16x16(v) case OpRsh16x32: return rewriteValuegeneric_OpRsh16x32(v) case OpRsh16x64: return rewriteValuegeneric_OpRsh16x64(v) case OpRsh16x8: return rewriteValuegeneric_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValuegeneric_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValuegeneric_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValuegeneric_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValuegeneric_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValuegeneric_OpRsh32x16(v) case OpRsh32x32: return rewriteValuegeneric_OpRsh32x32(v) case OpRsh32x64: return rewriteValuegeneric_OpRsh32x64(v) case OpRsh32x8: return rewriteValuegeneric_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValuegeneric_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValuegeneric_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValuegeneric_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValuegeneric_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValuegeneric_OpRsh64x16(v) case OpRsh64x32: return rewriteValuegeneric_OpRsh64x32(v) case OpRsh64x64: return rewriteValuegeneric_OpRsh64x64(v) case OpRsh64x8: return rewriteValuegeneric_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValuegeneric_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValuegeneric_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValuegeneric_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValuegeneric_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValuegeneric_OpRsh8x16(v) case OpRsh8x32: return rewriteValuegeneric_OpRsh8x32(v) case OpRsh8x64: return rewriteValuegeneric_OpRsh8x64(v) case OpRsh8x8: return rewriteValuegeneric_OpRsh8x8(v) case OpSelect0: return rewriteValuegeneric_OpSelect0(v) case OpSelect1: return rewriteValuegeneric_OpSelect1(v) case OpSelectN: return rewriteValuegeneric_OpSelectN(v) case OpSignExt16to32: return rewriteValuegeneric_OpSignExt16to32(v) case OpSignExt16to64: return rewriteValuegeneric_OpSignExt16to64(v) case OpSignExt32to64: return rewriteValuegeneric_OpSignExt32to64(v) case OpSignExt8to16: return rewriteValuegeneric_OpSignExt8to16(v) case OpSignExt8to32: return rewriteValuegeneric_OpSignExt8to32(v) case OpSignExt8to64: return rewriteValuegeneric_OpSignExt8to64(v) case OpSliceCap: return rewriteValuegeneric_OpSliceCap(v) case OpSliceLen: return rewriteValuegeneric_OpSliceLen(v) case OpSlicePtr: return rewriteValuegeneric_OpSlicePtr(v) case OpSlicemask: return rewriteValuegeneric_OpSlicemask(v) case OpSqrt: return rewriteValuegeneric_OpSqrt(v) case OpStaticLECall: return rewriteValuegeneric_OpStaticLECall(v) case OpStore: return rewriteValuegeneric_OpStore(v) case OpStringLen: return rewriteValuegeneric_OpStringLen(v) case OpStringPtr: return rewriteValuegeneric_OpStringPtr(v) case OpStructSelect: return rewriteValuegeneric_OpStructSelect(v) case OpSub16: return rewriteValuegeneric_OpSub16(v) case OpSub32: return rewriteValuegeneric_OpSub32(v) case OpSub32F: return rewriteValuegeneric_OpSub32F(v) case OpSub64: return rewriteValuegeneric_OpSub64(v) case OpSub64F: return rewriteValuegeneric_OpSub64F(v) case OpSub8: return rewriteValuegeneric_OpSub8(v) case OpTrunc16to8: return rewriteValuegeneric_OpTrunc16to8(v) case OpTrunc32to16: return rewriteValuegeneric_OpTrunc32to16(v) case OpTrunc32to8: return rewriteValuegeneric_OpTrunc32to8(v) case OpTrunc64to16: return rewriteValuegeneric_OpTrunc64to16(v) case OpTrunc64to32: return rewriteValuegeneric_OpTrunc64to32(v) case OpTrunc64to8: return rewriteValuegeneric_OpTrunc64to8(v) case OpXor16: return rewriteValuegeneric_OpXor16(v) case OpXor32: return rewriteValuegeneric_OpXor32(v) case OpXor64: return rewriteValuegeneric_OpXor64(v) case OpXor8: return rewriteValuegeneric_OpXor8(v) case OpZero: return rewriteValuegeneric_OpZero(v) case OpZeroExt16to32: return rewriteValuegeneric_OpZeroExt16to32(v) case OpZeroExt16to64: return rewriteValuegeneric_OpZeroExt16to64(v) case OpZeroExt32to64: return rewriteValuegeneric_OpZeroExt32to64(v) case OpZeroExt8to16: return rewriteValuegeneric_OpZeroExt8to16(v) case OpZeroExt8to32: return rewriteValuegeneric_OpZeroExt8to32(v) case OpZeroExt8to64: return rewriteValuegeneric_OpZeroExt8to64(v) } return false } func rewriteValuegeneric_OpAdd16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Add16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c + d) return true } break } // match: (Add16 (Mul16 x y) (Mul16 x z)) // result: (Mul16 x (Add16 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add16 (Const16 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add16 x (Neg16 y)) // result: (Sub16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg16 { continue } y := v_1.Args[0] v.reset(OpSub16) v.AddArg2(x, y) return true } break } // match: (Add16 (Com16 x) x) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Add16 (Const16 [1]) (Com16 x)) // result: (Neg16 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 1 || v_1.Op != OpCom16 { continue } x := v_1.Args[0] v.reset(OpNeg16) v.AddArg(x) return true } break } // match: (Add16 x (Sub16 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub16 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add16 x (Add16 y (Sub16 z x))) // result: (Add16 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub16 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd16) v.AddArg2(y, z) return true } } break } // match: (Add16 (Add16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Add16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add16 (Sub16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub16 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { continue } t := i.Type x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Add16 (Const16 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add16 (Const16 [c]) (Sub16 (Const16 [d]) x)) // result: (Sub16 (Const16 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpSub16 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpAdd32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Add32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c + d) return true } break } // match: (Add32 (Mul32 x y) (Mul32 x z)) // result: (Mul32 x (Add32 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add32 (Const32 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add32 x (Neg32 y)) // result: (Sub32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg32 { continue } y := v_1.Args[0] v.reset(OpSub32) v.AddArg2(x, y) return true } break } // match: (Add32 (Com32 x) x) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Add32 (Const32 [1]) (Com32 x)) // result: (Neg32 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 1 || v_1.Op != OpCom32 { continue } x := v_1.Args[0] v.reset(OpNeg32) v.AddArg(x) return true } break } // match: (Add32 x (Sub32 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub32 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add32 x (Add32 y (Sub32 z x))) // result: (Add32 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd32) v.AddArg2(y, z) return true } } break } // match: (Add32 (Add32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Add32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add32 (Sub32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub32 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { continue } t := i.Type x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Add32 (Const32 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add32 (Const32 [c]) (Sub32 (Const32 [d]) x)) // result: (Sub32 (Const32 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpSub32 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpAdd32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Add32F (Const32F [c]) (Const32F [d])) // cond: c+d == c+d // result: (Const32F [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) if !(c+d == c+d) { continue } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c + d) return true } break } return false } func rewriteValuegeneric_OpAdd64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Add64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c + d) return true } break } // match: (Add64 (Mul64 x y) (Mul64 x z)) // result: (Mul64 x (Add64 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add64 (Const64 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add64 x (Neg64 y)) // result: (Sub64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg64 { continue } y := v_1.Args[0] v.reset(OpSub64) v.AddArg2(x, y) return true } break } // match: (Add64 (Com64 x) x) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Add64 (Const64 [1]) (Com64 x)) // result: (Neg64 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 1 || v_1.Op != OpCom64 { continue } x := v_1.Args[0] v.reset(OpNeg64) v.AddArg(x) return true } break } // match: (Add64 x (Sub64 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub64 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add64 x (Add64 y (Sub64 z x))) // result: (Add64 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub64 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd64) v.AddArg2(y, z) return true } } break } // match: (Add64 (Add64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Add64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add64 (Sub64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub64 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { continue } t := i.Type x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Add64 (Const64 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add64 (Const64 [c]) (Sub64 (Const64 [d]) x)) // result: (Sub64 (Const64 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpSub64 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpAdd64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Add64F (Const64F [c]) (Const64F [d])) // cond: c+d == c+d // result: (Const64F [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) if !(c+d == c+d) { continue } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c + d) return true } break } return false } func rewriteValuegeneric_OpAdd8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Add8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c + d) return true } break } // match: (Add8 (Mul8 x y) (Mul8 x z)) // result: (Mul8 x (Add8 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add8 (Const8 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add8 x (Neg8 y)) // result: (Sub8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg8 { continue } y := v_1.Args[0] v.reset(OpSub8) v.AddArg2(x, y) return true } break } // match: (Add8 (Com8 x) x) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Add8 (Const8 [1]) (Com8 x)) // result: (Neg8 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 1 || v_1.Op != OpCom8 { continue } x := v_1.Args[0] v.reset(OpNeg8) v.AddArg(x) return true } break } // match: (Add8 x (Sub8 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub8 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add8 x (Add8 y (Sub8 z x))) // result: (Add8 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub8 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd8) v.AddArg2(y, z) return true } } break } // match: (Add8 (Add8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Add8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add8 (Sub8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub8 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { continue } t := i.Type x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Add8 (Const8 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add8 (Const8 [c]) (Sub8 (Const8 [d]) x)) // result: (Sub8 (Const8 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpSub8 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpAddPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (AddPtr x (Const64 [c])) // result: (OffPtr x [c]) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpOffPtr) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (AddPtr x (Const32 [c])) // result: (OffPtr x [int64(c)]) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpOffPtr) v.Type = t v.AuxInt = int64ToAuxInt(int64(c)) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c & d) return true } break } // match: (And16 (Const16 [m]) (Rsh16Ux64 _ (Const64 [c]))) // cond: c >= int64(16-ntz16(m)) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } m := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpRsh16Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(16-ntz16(m))) { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 (Const16 [m]) (Lsh16x64 _ (Const64 [c]))) // cond: c >= int64(16-nlz16(m)) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } m := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpLsh16x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(16-nlz16(m))) { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And16 (Const16 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And16 (Const16 [0]) _) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 (Com16 x) x) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 x (And16 x y)) // result: (And16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd16) v.AddArg2(x, y) return true } } break } // match: (And16 (And16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (And16 i (And16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And16 (Const16 [c]) (And16 (Const16 [d]) x)) // result: (And16 (Const16 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAnd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAnd32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c & d) return true } break } // match: (And32 (Const32 [m]) (Rsh32Ux64 _ (Const64 [c]))) // cond: c >= int64(32-ntz32(m)) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } m := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpRsh32Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(32-ntz32(m))) { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 (Const32 [m]) (Lsh32x64 _ (Const64 [c]))) // cond: c >= int64(32-nlz32(m)) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } m := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpLsh32x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(32-nlz32(m))) { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And32 (Const32 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And32 (Const32 [0]) _) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 (Com32 x) x) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 x (And32 x y)) // result: (And32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd32) v.AddArg2(x, y) return true } } break } // match: (And32 (And32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (And32 i (And32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And32 (Const32 [c]) (And32 (Const32 [d]) x)) // result: (And32 (Const32 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAnd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAnd64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c & d) return true } break } // match: (And64 (Const64 [m]) (Rsh64Ux64 _ (Const64 [c]))) // cond: c >= int64(64-ntz64(m)) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } m := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpRsh64Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(64-ntz64(m))) { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 (Const64 [m]) (Lsh64x64 _ (Const64 [c]))) // cond: c >= int64(64-nlz64(m)) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } m := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpLsh64x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(64-nlz64(m))) { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And64 (Const64 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And64 (Const64 [0]) _) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 (Com64 x) x) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 x (And64 x y)) // result: (And64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd64) v.AddArg2(x, y) return true } } break } // match: (And64 (And64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (And64 i (And64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And64 (Const64 [c]) (And64 (Const64 [d]) x)) // result: (And64 (Const64 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAnd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAnd8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c & d) return true } break } // match: (And8 (Const8 [m]) (Rsh8Ux64 _ (Const64 [c]))) // cond: c >= int64(8-ntz8(m)) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } m := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpRsh8Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(8-ntz8(m))) { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 (Const8 [m]) (Lsh8x64 _ (Const64 [c]))) // cond: c >= int64(8-nlz8(m)) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } m := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpLsh8x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(8-nlz8(m))) { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And8 (Const8 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And8 (Const8 [0]) _) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 (Com8 x) x) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 x (And8 x y)) // result: (And8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd8) v.AddArg2(x, y) return true } } break } // match: (And8 (And8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (And8 i (And8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And8 (Const8 [c]) (And8 (Const8 [d]) x)) // result: (And8 (Const8 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAnd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAndB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (AndB (Leq64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: d >= c // result: (Less64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: d >= c // result: (Leq64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: d >= c // result: (Less32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: d >= c // result: (Leq32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: d >= c // result: (Less16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: d >= c // result: (Leq16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: d >= c // result: (Less8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: d >= c // result: (Leq8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c) // result: (Less64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c) // result: (Leq64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c) // result: (Less32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c) // result: (Leq32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c) // result: (Less16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c) // result: (Leq16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c) // result: (Less8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c) // result: (Leq8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c) // result: (Less64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c) // result: (Leq64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c) // result: (Less32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c) // result: (Leq32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c) // result: (Less16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c) // result: (Leq16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c) // result: (Less8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c) // result: (Leq8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } return false } func rewriteValuegeneric_OpArraySelect(v *Value) bool { v_0 := v.Args[0] // match: (ArraySelect (ArrayMake1 x)) // result: x for { if v_0.Op != OpArrayMake1 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (ArraySelect [0] (IData x)) // result: (IData x) for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpIData { break } x := v_0.Args[0] v.reset(OpIData) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpCom16(v *Value) bool { v_0 := v.Args[0] // match: (Com16 (Com16 x)) // result: x for { if v_0.Op != OpCom16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com16 (Const16 [c])) // result: (Const16 [^c]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(^c) return true } // match: (Com16 (Add16 (Const16 [-1]) x)) // result: (Neg16 x) for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst16 || auxIntToInt16(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg16) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpCom32(v *Value) bool { v_0 := v.Args[0] // match: (Com32 (Com32 x)) // result: x for { if v_0.Op != OpCom32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com32 (Const32 [c])) // result: (Const32 [^c]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(^c) return true } // match: (Com32 (Add32 (Const32 [-1]) x)) // result: (Neg32 x) for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg32) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpCom64(v *Value) bool { v_0 := v.Args[0] // match: (Com64 (Com64 x)) // result: x for { if v_0.Op != OpCom64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com64 (Const64 [c])) // result: (Const64 [^c]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(^c) return true } // match: (Com64 (Add64 (Const64 [-1]) x)) // result: (Neg64 x) for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg64) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpCom8(v *Value) bool { v_0 := v.Args[0] // match: (Com8 (Com8 x)) // result: x for { if v_0.Op != OpCom8 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com8 (Const8 [c])) // result: (Const8 [^c]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(^c) return true } // match: (Com8 (Add8 (Const8 [-1]) x)) // result: (Neg8 x) for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst8 || auxIntToInt8(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpConstInterface(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ConstInterface) // result: (IMake (ConstNil ) (ConstNil )) for { v.reset(OpIMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.Uintptr) v1 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpConstSlice(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (ConstSlice) // cond: config.PtrSize == 4 // result: (SliceMake (ConstNil ) (Const32 [0]) (Const32 [0])) for { if !(config.PtrSize == 4) { break } v.reset(OpSliceMake) v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = int32ToAuxInt(0) v.AddArg3(v0, v1, v1) return true } // match: (ConstSlice) // cond: config.PtrSize == 8 // result: (SliceMake (ConstNil ) (Const64 [0]) (Const64 [0])) for { if !(config.PtrSize == 8) { break } v.reset(OpSliceMake) v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = int64ToAuxInt(0) v.AddArg3(v0, v1, v1) return true } return false } func rewriteValuegeneric_OpConstString(v *Value) bool { b := v.Block config := b.Func.Config fe := b.Func.fe typ := &b.Func.Config.Types // match: (ConstString {str}) // cond: config.PtrSize == 4 && str == "" // result: (StringMake (ConstNil) (Const32 [0])) for { str := auxToString(v.Aux) if !(config.PtrSize == 4 && str == "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v1) return true } // match: (ConstString {str}) // cond: config.PtrSize == 8 && str == "" // result: (StringMake (ConstNil) (Const64 [0])) for { str := auxToString(v.Aux) if !(config.PtrSize == 8 && str == "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, v1) return true } // match: (ConstString {str}) // cond: config.PtrSize == 4 && str != "" // result: (StringMake (Addr {fe.StringData(str)} (SB)) (Const32 [int32(len(str))])) for { str := auxToString(v.Aux) if !(config.PtrSize == 4 && str != "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) v0.Aux = symToAux(fe.StringData(str)) v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int) v2.AuxInt = int32ToAuxInt(int32(len(str))) v.AddArg2(v0, v2) return true } // match: (ConstString {str}) // cond: config.PtrSize == 8 && str != "" // result: (StringMake (Addr {fe.StringData(str)} (SB)) (Const64 [int64(len(str))])) for { str := auxToString(v.Aux) if !(config.PtrSize == 8 && str != "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) v0.Aux = symToAux(fe.StringData(str)) v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.Int) v2.AuxInt = int64ToAuxInt(int64(len(str))) v.AddArg2(v0, v2) return true } return false } func rewriteValuegeneric_OpConvert(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Convert (Add64 (Convert ptr mem) off) mem) // result: (AddPtr ptr off) for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConvert { continue } mem := v_0_0.Args[1] ptr := v_0_0.Args[0] off := v_0_1 if mem != v_1 { continue } v.reset(OpAddPtr) v.AddArg2(ptr, off) return true } break } // match: (Convert (Add32 (Convert ptr mem) off) mem) // result: (AddPtr ptr off) for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConvert { continue } mem := v_0_0.Args[1] ptr := v_0_0.Args[0] off := v_0_1 if mem != v_1 { continue } v.reset(OpAddPtr) v.AddArg2(ptr, off) return true } break } // match: (Convert (Convert ptr mem) mem) // result: ptr for { if v_0.Op != OpConvert { break } mem := v_0.Args[1] ptr := v_0.Args[0] if mem != v_1 { break } v.copyOf(ptr) return true } return false } func rewriteValuegeneric_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz16 (Const16 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz16(c))) return true } // match: (Ctz16 (Const16 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz16(c))) return true } return false } func rewriteValuegeneric_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz32 (Const32 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz32(c))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz32(c))) return true } // match: (Ctz32 (Const32 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz32(c))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz32(c))) return true } return false } func rewriteValuegeneric_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz64 (Const64 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz64(c))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz64(c))) return true } // match: (Ctz64 (Const64 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz64(c))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } return false } func rewriteValuegeneric_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz8 (Const8 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz8(c))) return true } // match: (Ctz8 (Const8 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz8(c))) return true } return false } func rewriteValuegeneric_OpCvt32Fto32(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32Fto32 (Const32F [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } return false } func rewriteValuegeneric_OpCvt32Fto64(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32Fto64 (Const32F [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } return false } func rewriteValuegeneric_OpCvt32Fto64F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32Fto64F (Const32F [c])) // result: (Const64F [float64(c)]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(float64(c)) return true } return false } func rewriteValuegeneric_OpCvt32to32F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32to32F (Const32 [c])) // result: (Const32F [float32(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(float32(c)) return true } return false } func rewriteValuegeneric_OpCvt32to64F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32to64F (Const32 [c])) // result: (Const64F [float64(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(float64(c)) return true } return false } func rewriteValuegeneric_OpCvt64Fto32(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64Fto32 (Const64F [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } return false } func rewriteValuegeneric_OpCvt64Fto32F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64Fto32F (Const64F [c])) // result: (Const32F [float32(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(float32(c)) return true } // match: (Cvt64Fto32F sqrt0:(Sqrt (Cvt32Fto64F x))) // cond: sqrt0.Uses==1 // result: (Sqrt32 x) for { sqrt0 := v_0 if sqrt0.Op != OpSqrt { break } sqrt0_0 := sqrt0.Args[0] if sqrt0_0.Op != OpCvt32Fto64F { break } x := sqrt0_0.Args[0] if !(sqrt0.Uses == 1) { break } v.reset(OpSqrt32) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpCvt64Fto64(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64Fto64 (Const64F [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } return false } func rewriteValuegeneric_OpCvt64to32F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64to32F (Const64 [c])) // result: (Const32F [float32(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(float32(c)) return true } return false } func rewriteValuegeneric_OpCvt64to64F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64to64F (Const64 [c])) // result: (Const64F [float64(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(float64(c)) return true } return false } func rewriteValuegeneric_OpCvtBoolToUint8(v *Value) bool { v_0 := v.Args[0] // match: (CvtBoolToUint8 (ConstBool [false])) // result: (Const8 [0]) for { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != false { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (CvtBoolToUint8 (ConstBool [true])) // result: (Const8 [1]) for { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != true { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(1) return true } return false } func rewriteValuegeneric_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [c/d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c / d) return true } // match: (Div16 n (Const16 [c])) // cond: isNonNegative(n) && isPowerOfTwo16(c) // result: (Rsh16Ux64 n (Const64 [log16(c)])) for { n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo16(c)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log16(c)) v.AddArg2(n, v0) return true } // match: (Div16 n (Const16 [c])) // cond: c < 0 && c != -1<<15 // result: (Neg16 (Div16 n (Const16 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(c < 0 && c != -1<<15) { break } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpDiv16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div16 x (Const16 [-1<<15])) // result: (Rsh16Ux64 (And16 x (Neg16 x)) (Const64 [15])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != -1<<15 { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpNeg16, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(15) v.AddArg2(v0, v2) return true } // match: (Div16 n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [int64(16-log16(c))]))) (Const64 [int64(log16(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { break } v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpAdd16, t) v1 := b.NewValue0(v.Pos, OpRsh16Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh16x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(15) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(16 - log16(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log16(c))) v.AddArg2(v0, v5) return true } // match: (Div16 x (Const16 [c])) // cond: smagicOK16(c) // result: (Sub16 (Rsh32x64 (Mul32 (Const32 [int32(smagic16(c).m)]) (SignExt16to32 x)) (Const64 [16+smagic16(c).s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(smagicOK16(c)) { break } v.reset(OpSub16) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(smagic16(c).m)) v3 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16 + smagic16(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(31) v5.AddArg2(v3, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div16u (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int16(uint16(c)/uint16(d))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint16(c) / uint16(d))) return true } // match: (Div16u n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (Rsh16Ux64 n (Const64 [log16(c)])) for { n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log16(c)) v.AddArg2(n, v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 8 // result: (Trunc64to16 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<16+umagic16(c).m)]) (ZeroExt16to64 x)) (Const64 [16+umagic16(c).s]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 8) { break } v.reset(OpTrunc64to16) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(1<<16 + umagic16(c).m)) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16 + umagic16(c).s) v0.AddArg2(v1, v4) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 4 && umagic16(c).m&1 == 0 // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<15+umagic16(c).m/2)]) (ZeroExt16to32 x)) (Const64 [16+umagic16(c).s-1]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 4 && umagic16(c).m&1 == 0) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(1<<15 + umagic16(c).m/2)) v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 1) v0.AddArg2(v1, v4) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 4 && c&1 == 0 // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<15+(umagic16(c).m+1)/2)]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [16+umagic16(c).s-2]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 4 && c&1 == 0) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(1<<15 + (umagic16(c).m+1)/2)) v3 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v4.AddArg(x) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(1) v3.AddArg2(v4, v5) v1.AddArg2(v2, v3) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 2) v0.AddArg2(v1, v6) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 4 && config.useAvg // result: (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) (Mul32 (Const32 [int32(umagic16(c).m)]) (ZeroExt16to32 x))) (Const64 [16+umagic16(c).s-1]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 4 && config.useAvg) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) v2 := b.NewValue0(v.Pos, OpLsh32x64, typ.UInt32) v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v3.AddArg(x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16) v2.AddArg2(v3, v4) v5 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(umagic16(c).m)) v5.AddArg2(v6, v3) v1.AddArg2(v2, v5) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 1) v0.AddArg2(v1, v7) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32 (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [c/d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c / d) return true } // match: (Div32 n (Const32 [c])) // cond: isNonNegative(n) && isPowerOfTwo32(c) // result: (Rsh32Ux64 n (Const64 [log32(c)])) for { n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo32(c)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log32(c)) v.AddArg2(n, v0) return true } // match: (Div32 n (Const32 [c])) // cond: c < 0 && c != -1<<31 // result: (Neg32 (Div32 n (Const32 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(c < 0 && c != -1<<31) { break } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpDiv32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div32 x (Const32 [-1<<31])) // result: (Rsh32Ux64 (And32 x (Neg32 x)) (Const64 [31])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != -1<<31 { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpNeg32, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(31) v.AddArg2(v0, v2) return true } // match: (Div32 n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [int64(32-log32(c))]))) (Const64 [int64(log32(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { break } v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpAdd32, t) v1 := b.NewValue0(v.Pos, OpRsh32Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh32x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(31) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(32 - log32(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log32(c))) v.AddArg2(v0, v5) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK32(c) && config.RegSize == 8 // result: (Sub32 (Rsh64x64 (Mul64 (Const64 [int64(smagic32(c).m)]) (SignExt32to64 x)) (Const64 [32+smagic32(c).s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(smagicOK32(c) && config.RegSize == 8) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(smagic32(c).m)) v3 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(32 + smagic32(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh64x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(63) v5.AddArg2(v3, v6) v.AddArg2(v0, v5) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0 && config.useHmul // result: (Sub32 (Rsh32x64 (Hmul32 (Const32 [int32(smagic32(c).m/2)]) x) (Const64 [smagic32(c).s-1])) (Rsh32x64 x (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0 && config.useHmul) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpHmul32, t) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(smagic32(c).m / 2)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(smagic32(c).s - 1) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpRsh32x64, t) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(31) v4.AddArg2(x, v5) v.AddArg2(v0, v4) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0 && config.useHmul // result: (Sub32 (Rsh32x64 (Add32 (Hmul32 (Const32 [int32(smagic32(c).m)]) x) x) (Const64 [smagic32(c).s])) (Rsh32x64 x (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0 && config.useHmul) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpAdd32, t) v2 := b.NewValue0(v.Pos, OpHmul32, t) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(smagic32(c).m)) v2.AddArg2(v3, x) v1.AddArg2(v2, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(smagic32(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(31) v5.AddArg2(x, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Div32F (Const32F [c]) (Const32F [d])) // cond: c/d == c/d // result: (Const32F [c/d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) if !(c/d == c/d) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c / d) return true } // match: (Div32F x (Const32F [c])) // cond: reciprocalExact32(c) // result: (Mul32F x (Const32F [1/c])) for { x := v_0 if v_1.Op != OpConst32F { break } t := v_1.Type c := auxIntToFloat32(v_1.AuxInt) if !(reciprocalExact32(c)) { break } v.reset(OpMul32F) v0 := b.NewValue0(v.Pos, OpConst32F, t) v0.AuxInt = float32ToAuxInt(1 / c) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpDiv32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32u (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int32(uint32(c)/uint32(d))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint32(c) / uint32(d))) return true } // match: (Div32u n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (Rsh32Ux64 n (Const64 [log32(c)])) for { n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log32(c)) v.AddArg2(n, v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 4 && umagic32(c).m&1 == 0 && config.useHmul // result: (Rsh32Ux64 (Hmul32u (Const32 [int32(1<<31+umagic32(c).m/2)]) x) (Const64 [umagic32(c).s-1])) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 4 && umagic32(c).m&1 == 0 && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v1.AuxInt = int32ToAuxInt(int32(1<<31 + umagic32(c).m/2)) v0.AddArg2(v1, x) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(umagic32(c).s - 1) v.AddArg2(v0, v2) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 4 && c&1 == 0 && config.useHmul // result: (Rsh32Ux64 (Hmul32u (Const32 [int32(1<<31+(umagic32(c).m+1)/2)]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [umagic32(c).s-2])) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 4 && c&1 == 0 && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v1.AuxInt = int32ToAuxInt(int32(1<<31 + (umagic32(c).m+1)/2)) v2 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(1) v2.AddArg2(x, v3) v0.AddArg2(v1, v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(umagic32(c).s - 2) v.AddArg2(v0, v4) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 4 && config.useAvg && config.useHmul // result: (Rsh32Ux64 (Avg32u x (Hmul32u (Const32 [int32(umagic32(c).m)]) x)) (Const64 [umagic32(c).s-1])) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 4 && config.useAvg && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(umagic32(c).m)) v1.AddArg2(v2, x) v0.AddArg2(x, v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(umagic32(c).s - 1) v.AddArg2(v0, v3) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 8 && umagic32(c).m&1 == 0 // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+umagic32(c).m/2)]) (ZeroExt32to64 x)) (Const64 [32+umagic32(c).s-1]))) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 8 && umagic32(c).m&1 == 0) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(1<<31 + umagic32(c).m/2)) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 1) v0.AddArg2(v1, v4) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 8 && c&1 == 0 // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+(umagic32(c).m+1)/2)]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [32+umagic32(c).s-2]))) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 8 && c&1 == 0) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(1<<31 + (umagic32(c).m+1)/2)) v3 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(x) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(1) v3.AddArg2(v4, v5) v1.AddArg2(v2, v3) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 2) v0.AddArg2(v1, v6) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 8 && config.useAvg // result: (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) (Mul64 (Const64 [int64(umagic32(c).m)]) (ZeroExt32to64 x))) (Const64 [32+umagic32(c).s-1]))) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 8 && config.useAvg) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(32) v2.AddArg2(v3, v4) v5 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt32) v6.AuxInt = int64ToAuxInt(int64(umagic32(c).m)) v5.AddArg2(v6, v3) v1.AddArg2(v2, v5) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 1) v0.AddArg2(v1, v7) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64 (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [c/d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c / d) return true } // match: (Div64 n (Const64 [c])) // cond: isNonNegative(n) && isPowerOfTwo64(c) // result: (Rsh64Ux64 n (Const64 [log64(c)])) for { n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo64(c)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(n, v0) return true } // match: (Div64 n (Const64 [-1<<63])) // cond: isNonNegative(n) // result: (Const64 [0]) for { n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 || !(isNonNegative(n)) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Div64 n (Const64 [c])) // cond: c < 0 && c != -1<<63 // result: (Neg64 (Div64 n (Const64 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c < 0 && c != -1<<63) { break } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpDiv64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div64 x (Const64 [-1<<63])) // result: (Rsh64Ux64 (And64 x (Neg64 x)) (Const64 [63])) for { t := v.Type x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpNeg64, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(63) v.AddArg2(v0, v2) return true } // match: (Div64 n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [int64(64-log64(c))]))) (Const64 [int64(log64(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v1 := b.NewValue0(v.Pos, OpRsh64Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh64x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(63) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(64 - log64(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log64(c))) v.AddArg2(v0, v5) return true } // match: (Div64 x (Const64 [c])) // cond: smagicOK64(c) && smagic64(c).m&1 == 0 && config.useHmul // result: (Sub64 (Rsh64x64 (Hmul64 (Const64 [int64(smagic64(c).m/2)]) x) (Const64 [smagic64(c).s-1])) (Rsh64x64 x (Const64 [63]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(smagicOK64(c) && smagic64(c).m&1 == 0 && config.useHmul) { break } v.reset(OpSub64) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpHmul64, t) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(smagic64(c).m / 2)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(smagic64(c).s - 1) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpRsh64x64, t) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(63) v4.AddArg2(x, v5) v.AddArg2(v0, v4) return true } // match: (Div64 x (Const64 [c])) // cond: smagicOK64(c) && smagic64(c).m&1 != 0 && config.useHmul // result: (Sub64 (Rsh64x64 (Add64 (Hmul64 (Const64 [int64(smagic64(c).m)]) x) x) (Const64 [smagic64(c).s])) (Rsh64x64 x (Const64 [63]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(smagicOK64(c) && smagic64(c).m&1 != 0 && config.useHmul) { break } v.reset(OpSub64) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpAdd64, t) v2 := b.NewValue0(v.Pos, OpHmul64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(int64(smagic64(c).m)) v2.AddArg2(v3, x) v1.AddArg2(v2, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(smagic64(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh64x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(63) v5.AddArg2(x, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Div64F (Const64F [c]) (Const64F [d])) // cond: c/d == c/d // result: (Const64F [c/d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) if !(c/d == c/d) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c / d) return true } // match: (Div64F x (Const64F [c])) // cond: reciprocalExact64(c) // result: (Mul64F x (Const64F [1/c])) for { x := v_0 if v_1.Op != OpConst64F { break } t := v_1.Type c := auxIntToFloat64(v_1.AuxInt) if !(reciprocalExact64(c)) { break } v.reset(OpMul64F) v0 := b.NewValue0(v.Pos, OpConst64F, t) v0.AuxInt = float64ToAuxInt(1 / c) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpDiv64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64u (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [int64(uint64(c)/uint64(d))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint64(c) / uint64(d))) return true } // match: (Div64u n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (Rsh64Ux64 n (Const64 [log64(c)])) for { n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(n, v0) return true } // match: (Div64u n (Const64 [-1<<63])) // result: (Rsh64Ux64 n (Const64 [63])) for { n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(63) v.AddArg2(n, v0) return true } // match: (Div64u x (Const64 [c])) // cond: c > 0 && c <= 0xFFFF && umagicOK32(int32(c)) && config.RegSize == 4 && config.useHmul // result: (Add64 (Add64 (Add64 (Lsh64x64 (ZeroExt32to64 (Div32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)]))) (Const64 [32])) (ZeroExt32to64 (Div32u (Trunc64to32 x) (Const32 [int32(c)])))) (Mul64 (ZeroExt32to64 (Mod32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)]))) (Const64 [int64((1<<32)/c)]))) (ZeroExt32to64 (Div32u (Add32 (Mod32u (Trunc64to32 x) (Const32 [int32(c)])) (Mul32 (Mod32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)])) (Const32 [int32((1<<32)%c)]))) (Const32 [int32(c)])))) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c > 0 && c <= 0xFFFF && umagicOK32(int32(c)) && config.RegSize == 4 && config.useHmul) { break } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) v5 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v6 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = int64ToAuxInt(32) v6.AddArg2(x, v7) v5.AddArg(v6) v8 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v8.AuxInt = int32ToAuxInt(int32(c)) v4.AddArg2(v5, v8) v3.AddArg(v4) v2.AddArg2(v3, v7) v9 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v10 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) v11 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v11.AddArg(x) v10.AddArg2(v11, v8) v9.AddArg(v10) v1.AddArg2(v2, v9) v12 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v13 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v14 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v14.AddArg2(v5, v8) v13.AddArg(v14) v15 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v15.AuxInt = int64ToAuxInt(int64((1 << 32) / c)) v12.AddArg2(v13, v15) v0.AddArg2(v1, v12) v16 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v17 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) v18 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v19 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v19.AddArg2(v11, v8) v20 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v21 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v21.AuxInt = int32ToAuxInt(int32((1 << 32) % c)) v20.AddArg2(v14, v21) v18.AddArg2(v19, v20) v17.AddArg2(v18, v8) v16.AddArg(v17) v.AddArg2(v0, v16) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK64(c) && config.RegSize == 8 && umagic64(c).m&1 == 0 && config.useHmul // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+umagic64(c).m/2)]) x) (Const64 [umagic64(c).s-1])) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(umagicOK64(c) && config.RegSize == 8 && umagic64(c).m&1 == 0 && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(int64(1<<63 + umagic64(c).m/2)) v0.AddArg2(v1, x) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(umagic64(c).s - 1) v.AddArg2(v0, v2) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK64(c) && config.RegSize == 8 && c&1 == 0 && config.useHmul // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+(umagic64(c).m+1)/2)]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [umagic64(c).s-2])) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(umagicOK64(c) && config.RegSize == 8 && c&1 == 0 && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(int64(1<<63 + (umagic64(c).m+1)/2)) v2 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(1) v2.AddArg2(x, v3) v0.AddArg2(v1, v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(umagic64(c).s - 2) v.AddArg2(v0, v4) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK64(c) && config.RegSize == 8 && config.useAvg && config.useHmul // result: (Rsh64Ux64 (Avg64u x (Hmul64u (Const64 [int64(umagic64(c).m)]) x)) (Const64 [umagic64(c).s-1])) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(umagicOK64(c) && config.RegSize == 8 && config.useAvg && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(umagic64(c).m)) v1.AddArg2(v2, x) v0.AddArg2(x, v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(umagic64(c).s - 1) v.AddArg2(v0, v3) return true } return false } func rewriteValuegeneric_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [c/d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c / d) return true } // match: (Div8 n (Const8 [c])) // cond: isNonNegative(n) && isPowerOfTwo8(c) // result: (Rsh8Ux64 n (Const64 [log8(c)])) for { n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo8(c)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log8(c)) v.AddArg2(n, v0) return true } // match: (Div8 n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Neg8 (Div8 n (Const8 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(c < 0 && c != -1<<7) { break } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpDiv8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div8 x (Const8 [-1<<7 ])) // result: (Rsh8Ux64 (And8 x (Neg8 x)) (Const64 [7 ])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != -1<<7 { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpNeg8, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(7) v.AddArg2(v0, v2) return true } // match: (Div8 n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [int64( 8-log8(c))]))) (Const64 [int64(log8(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { break } v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpAdd8, t) v1 := b.NewValue0(v.Pos, OpRsh8Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh8x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(7) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(8 - log8(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log8(c))) v.AddArg2(v0, v5) return true } // match: (Div8 x (Const8 [c])) // cond: smagicOK8(c) // result: (Sub8 (Rsh32x64 (Mul32 (Const32 [int32(smagic8(c).m)]) (SignExt8to32 x)) (Const64 [8+smagic8(c).s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(smagicOK8(c)) { break } v.reset(OpSub8) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(smagic8(c).m)) v3 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(8 + smagic8(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(31) v5.AddArg2(v3, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int8(uint8(c)/uint8(d))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(uint8(c) / uint8(d))) return true } // match: (Div8u n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (Rsh8Ux64 n (Const64 [log8(c)])) for { n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log8(c)) v.AddArg2(n, v0) return true } // match: (Div8u x (Const8 [c])) // cond: umagicOK8(c) // result: (Trunc32to8 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<8+umagic8(c).m)]) (ZeroExt8to32 x)) (Const64 [8+umagic8(c).s]))) for { x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(umagicOK8(c)) { break } v.reset(OpTrunc32to8) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(1<<8 + umagic8(c).m)) v3 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(8 + umagic8(c).s) v0.AddArg2(v1, v4) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Eq16 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Eq16 (Const16 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq16 (Const16 [c]) (Const16 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq16 (Mod16u x (Const16 [c])) (Const16 [0])) // cond: x.Op != OpConst16 && udivisibleOK16(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt16to32 x) (Const32 [int32(uint16(c))])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod16u { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 || !(x.Op != OpConst16 && udivisibleOK16(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(uint16(c))) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq16 (Mod16 x (Const16 [c])) (Const16 [0])) // cond: x.Op != OpConst16 && sdivisibleOK16(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32 (SignExt16to32 x) (Const32 [int32(c)])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod16 { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 || !(x.Op != OpConst16 && sdivisibleOK16(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic16(c).m) && s == 16+umagic16(c).s && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpZeroExt16to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic16(c).m) && s == 16+umagic16(c).s && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+umagic16(c).m/2) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpZeroExt16to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+umagic16(c).m/2) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+(umagic16(c).m+1)/2) && s == 16+umagic16(c).s-2 && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpRsh32Ux64 { continue } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt16to32 || x != mul_1_0.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+(umagic16(c).m+1)/2) && s == 16+umagic16(c).s-2 && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic16(c).m) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg32u { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh32x64 { continue } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt16to32 || x != v_1_1_0_0_0_0.Args[0] { continue } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 || auxIntToInt64(v_1_1_0_0_0_1.AuxInt) != 16 { continue } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpZeroExt16to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic16(c).m) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic16(c).m) && s == 16+smagic16(c).s && x.Op != OpConst16 && sdivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int16(sdivisible16(c).m)]) x) (Const16 [int16(sdivisible16(c).a)]) ) (Const16 [int16(16-sdivisible16(c).k)]) ) (Const16 [int16(sdivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpSub16 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpSignExt16to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt16to32 || x != v_1_1_1_0.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic16(c).m) && s == 16+smagic16(c).s && x.Op != OpConst16 && sdivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(sdivisible16(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(sdivisible16(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v5.AuxInt = int16ToAuxInt(int16(16 - sdivisible16(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v6.AuxInt = int16ToAuxInt(int16(sdivisible16(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh16x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh16x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd16 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh16Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh16x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 15 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 15 && kbar == 16-k) { continue } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(1< x (Const16 [y])) (Const16 [y])) // cond: oneBit16(y) // result: (Neq16 (And16 x (Const16 [y])) (Const16 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst16 || v_0_1.Type != t { continue } y := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || v_1.Type != t || auxIntToInt16(v_1.AuxInt) != y || !(oneBit16(y)) { continue } v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq32 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Eq32 (Const32 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) x) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+umagic32(c).m/2) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpRsh32Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+umagic32(c).m/2) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+(umagic32(c).m+1)/2) && s == umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpRsh32Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 || mul_0.Type != typ.UInt32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpRsh32Ux64 { continue } _ = mul_1.Args[1] if x != mul_1.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+(umagic32(c).m+1)/2) && s == umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 (Avg32u x mul:(Hmul32u (Const32 [m]) x)) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic32(c).m) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpRsh32Ux64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg32u { continue } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { continue } mul := v_1_1_0.Args[1] if mul.Op != OpHmul32u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic32(c).m) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic32(c).m/2) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to32 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpZeroExt32to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic32(c).m/2) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic32(c).m+1)/2) && s == 32+umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to32 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpRsh64Ux64 { continue } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt32to64 || x != mul_1_0.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic32(c).m+1)/2) && s == 32+umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic32(c).m) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to32 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg64u { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh64x64 { continue } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt32to64 || x != v_1_1_0_0_0_0.Args[0] { continue } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 || auxIntToInt64(v_1_1_0_0_0_1.AuxInt) != 32 { continue } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpZeroExt32to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic32(c).m) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic32(c).m) && s == 32+smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpSignExt32to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { continue } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt32to64 || x != v_1_1_1_0.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic32(c).m) && s == 32+smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m/2) && s == smagic32(c).s-1 && x.Op != OpConst32 && sdivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpHmul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m/2) && s == smagic32(c).s-1 && x.Op != OpConst32 && sdivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m) && s == smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd32 { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] v_1_1_0_0_1 := v_1_1_0_0.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_1_0_0_0, v_1_1_0_0_1 = _i2+1, v_1_1_0_0_1, v_1_1_0_0_0 { mul := v_1_1_0_0_0 if mul.Op != OpHmul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i3 := 0; _i3 <= 1; _i3, mul_0, mul_1 = _i3+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 || x != v_1_1_0_0_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m) && s == smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) v.AddArg2(v0, v6) return true } } } } break } // match: (Eq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh32x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd32 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh32Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh32x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 31 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 31 && kbar == 32-k) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(1< x (Const32 [y])) (Const32 [y])) // cond: oneBit32(y) // result: (Neq32 (And32 x (Const32 [y])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst32 || v_0_1.Type != t { continue } y := auxIntToInt32(v_0_1.AuxInt) if v_1.Op != OpConst32 || v_1.Type != t || auxIntToInt32(v_1.AuxInt) != y || !(oneBit32(y)) { continue } v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Eq32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } return false } func rewriteValuegeneric_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq64 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Eq64 (Const64 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) x) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic64(c).m/2) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpRsh64Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic64(c).m/2) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic64(c).m+1)/2) && s == umagic64(c).s-2 && x.Op != OpConst64 && udivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpRsh64Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpRsh64Ux64 { continue } _ = mul_1.Args[1] if x != mul_1.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic64(c).m+1)/2) && s == umagic64(c).s-2 && x.Op != OpConst64 && udivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 (Avg64u x mul:(Hmul64u (Const64 [m]) x)) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic64(c).m) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpRsh64Ux64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg64u { continue } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { continue } mul := v_1_1_0.Args[1] if mul.Op != OpHmul64u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic64(c).m) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m/2) && s == smagic64(c).s-1 && x.Op != OpConst64 && sdivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible64(c).m)]) x) (Const64 [int64(sdivisible64(c).a)]) ) (Const64 [64-sdivisible64(c).k]) ) (Const64 [int64(sdivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpSub64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpHmul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m/2) && s == smagic64(c).s-1 && x.Op != OpConst64 && sdivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(int64(sdivisible64(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(sdivisible64(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(64 - sdivisible64(c).k) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(int64(sdivisible64(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m) && s == smagic64(c).s && x.Op != OpConst64 && sdivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible64(c).m)]) x) (Const64 [int64(sdivisible64(c).a)]) ) (Const64 [64-sdivisible64(c).k]) ) (Const64 [int64(sdivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpSub64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd64 { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] v_1_1_0_0_1 := v_1_1_0_0.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_1_0_0_0, v_1_1_0_0_1 = _i2+1, v_1_1_0_0_1, v_1_1_0_0_0 { mul := v_1_1_0_0_0 if mul.Op != OpHmul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i3 := 0; _i3 <= 1; _i3, mul_0, mul_1 = _i3+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 || x != v_1_1_0_0_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m) && s == smagic64(c).s && x.Op != OpConst64 && sdivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(int64(sdivisible64(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(sdivisible64(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(64 - sdivisible64(c).k) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(int64(sdivisible64(c).max)) v.AddArg2(v0, v6) return true } } } } break } // match: (Eq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh64x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd64 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh64Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh64x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 63 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 63 && kbar == 64-k) { continue } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(1< x (Const64 [y])) (Const64 [y])) // cond: oneBit64(y) // result: (Neq64 (And64 x (Const64 [y])) (Const64 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst64 || v_0_1.Type != t { continue } y := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 || v_1.Type != t || auxIntToInt64(v_1.AuxInt) != y || !(oneBit64(y)) { continue } v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Eq64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } return false } func rewriteValuegeneric_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Eq8 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Eq8 (Const8 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq8 (Mod8u x (Const8 [c])) (Const8 [0])) // cond: x.Op != OpConst8 && udivisibleOK8(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt8to32 x) (Const32 [int32(uint8(c))])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod8u { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 || !(x.Op != OpConst8 && udivisibleOK8(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(uint8(c))) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq8 (Mod8 x (Const8 [c])) (Const8 [0])) // cond: x.Op != OpConst8 && sdivisibleOK8(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32 (SignExt8to32 x) (Const32 [int32(c)])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod8 { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 || !(x.Op != OpConst8 && sdivisibleOK8(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<8+umagic8(c).m) && s == 8+umagic8(c).s && x.Op != OpConst8 && udivisibleOK8(c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int8(udivisible8(c).m)]) x) (Const8 [int8(8-udivisible8(c).k)]) ) (Const8 [int8(udivisible8(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to8 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpZeroExt8to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<8+umagic8(c).m) && s == 8+umagic8(c).s && x.Op != OpConst8 && udivisibleOK8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int8ToAuxInt(int8(udivisible8(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int8ToAuxInt(int8(8 - udivisible8(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int8ToAuxInt(int8(udivisible8(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq8 x (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic8(c).m) && s == 8+smagic8(c).s && x.Op != OpConst8 && sdivisibleOK8(c) // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int8(sdivisible8(c).m)]) x) (Const8 [int8(sdivisible8(c).a)]) ) (Const8 [int8(8-sdivisible8(c).k)]) ) (Const8 [int8(sdivisible8(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0.AuxInt) if v_1_1.Op != OpSub8 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpSignExt8to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt8to32 || x != v_1_1_1_0.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic8(c).m) && s == 8+smagic8(c).s && x.Op != OpConst8 && sdivisibleOK8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int8ToAuxInt(int8(sdivisible8(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int8ToAuxInt(int8(sdivisible8(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v5.AuxInt = int8ToAuxInt(int8(8 - sdivisible8(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v6.AuxInt = int8ToAuxInt(int8(sdivisible8(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh8x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh8x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd8 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh8Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh8x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 7 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 7 && kbar == 8-k) { continue } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(1< x (Const8 [y])) (Const8 [y])) // cond: oneBit8(y) // result: (Neq8 (And8 x (Const8 [y])) (Const8 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst8 || v_0_1.Type != t { continue } y := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || v_1.Type != t || auxIntToInt8(v_1.AuxInt) != y || !(oneBit8(y)) { continue } v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EqB (ConstBool [c]) (ConstBool [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool { continue } c := auxIntToBool(v_0.AuxInt) if v_1.Op != OpConstBool { continue } d := auxIntToBool(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (EqB (ConstBool [false]) x) // result: (Not x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != false { continue } x := v_1 v.reset(OpNot) v.AddArg(x) return true } break } // match: (EqB (ConstBool [true]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != true { continue } x := v_1 v.copyOf(x) return true } break } return false } func rewriteValuegeneric_OpEqInter(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqInter x y) // result: (EqPtr (ITab x) (ITab y)) for { x := v_0 y := v_1 v.reset(OpEqPtr) v0 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqPtr x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (EqPtr (Addr {x} _) (Addr {y} _)) // result: (ConstBool [x == y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y) return true } break } // match: (EqPtr (Addr {x} _) (OffPtr [o] (Addr {y} _))) // result: (ConstBool [x == y && o == 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o == 0) return true } break } // match: (EqPtr (OffPtr [o1] (Addr {x} _)) (OffPtr [o2] (Addr {y} _))) // result: (ConstBool [x == y && o1 == o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o1 == o2) return true } break } // match: (EqPtr (LocalAddr {x} _ _) (LocalAddr {y} _ _)) // result: (ConstBool [x == y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpLocalAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y) return true } break } // match: (EqPtr (LocalAddr {x} _ _) (OffPtr [o] (LocalAddr {y} _ _))) // result: (ConstBool [x == y && o == 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o == 0) return true } break } // match: (EqPtr (OffPtr [o1] (LocalAddr {x} _ _)) (OffPtr [o2] (LocalAddr {y} _ _))) // result: (ConstBool [x == y && o1 == o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o1 == o2) return true } break } // match: (EqPtr (OffPtr [o1] p1) p2) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 == 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 == 0) return true } break } // match: (EqPtr (OffPtr [o1] p1) (OffPtr [o2] p2)) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 == o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 == o2) return true } break } // match: (EqPtr (Const32 [c]) (Const32 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (EqPtr (Const64 [c]) (Const64 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (EqPtr (LocalAddr _ _) (Addr _)) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (OffPtr (LocalAddr _ _)) (Addr _)) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (LocalAddr _ _) (OffPtr (Addr _))) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (OffPtr (LocalAddr _ _)) (OffPtr (Addr _))) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (AddPtr p1 o1) p2) // cond: isSamePtr(p1, p2) // result: (Not (IsNonNil o1)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddPtr { continue } o1 := v_0.Args[1] p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(o1) v.AddArg(v0) return true } break } // match: (EqPtr (Const32 [0]) p) // result: (Not (IsNonNil p)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(p) v.AddArg(v0) return true } break } // match: (EqPtr (Const64 [0]) p) // result: (Not (IsNonNil p)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(p) v.AddArg(v0) return true } break } // match: (EqPtr (ConstNil) p) // result: (Not (IsNonNil p)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstNil { continue } p := v_1 v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(p) v.AddArg(v0) return true } break } return false } func rewriteValuegeneric_OpEqSlice(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqSlice x y) // result: (EqPtr (SlicePtr x) (SlicePtr y)) for { x := v_0 y := v_1 v.reset(OpEqPtr) v0 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpIMake(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (IMake _typ (StructMake1 val)) // result: (IMake _typ val) for { _typ := v_0 if v_1.Op != OpStructMake1 { break } val := v_1.Args[0] v.reset(OpIMake) v.AddArg2(_typ, val) return true } // match: (IMake _typ (ArrayMake1 val)) // result: (IMake _typ val) for { _typ := v_0 if v_1.Op != OpArrayMake1 { break } val := v_1.Args[0] v.reset(OpIMake) v.AddArg2(_typ, val) return true } return false } func rewriteValuegeneric_OpInterLECall(v *Value) bool { // match: (InterLECall [argsize] {auxCall} (Load (OffPtr [off] (ITab (IMake (Addr {itab} (SB)) _))) _) ___) // cond: devirtLESym(v, auxCall, itab, off) != nil // result: devirtLECall(v, devirtLESym(v, auxCall, itab, off)) for { if len(v.Args) < 1 { break } auxCall := auxToCall(v.Aux) v_0 := v.Args[0] if v_0.Op != OpLoad { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpOffPtr { break } off := auxIntToInt64(v_0_0.AuxInt) v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpITab { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpIMake { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAddr { break } itab := auxToSym(v_0_0_0_0_0.Aux) v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpSB || !(devirtLESym(v, auxCall, itab, off) != nil) { break } v.copyOf(devirtLECall(v, devirtLESym(v, auxCall, itab, off))) return true } return false } func rewriteValuegeneric_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (IsInBounds (ZeroExt8to32 _) (Const32 [c])) // cond: (1 << 8) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to32 || v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !((1 << 8) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt8to64 _) (Const64 [c])) // cond: (1 << 8) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to64 || v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !((1 << 8) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt16to32 _) (Const32 [c])) // cond: (1 << 16) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to32 || v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !((1 << 16) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt16to64 _) (Const64 [c])) // cond: (1 << 16) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to64 || v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !((1 << 16) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (IsInBounds (And8 (Const8 [c]) _) (Const8 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd8 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt8to16 (And8 (Const8 [c]) _)) (Const16 [d])) // cond: 0 <= c && int16(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) if !(0 <= c && int16(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt8to32 (And8 (Const8 [c]) _)) (Const32 [d])) // cond: 0 <= c && int32(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) if !(0 <= c && int32(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt8to64 (And8 (Const8 [c]) _)) (Const64 [d])) // cond: 0 <= c && int64(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && int64(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (And16 (Const16 [c]) _) (Const16 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd16 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt16to32 (And16 (Const16 [c]) _)) (Const32 [d])) // cond: 0 <= c && int32(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) if !(0 <= c && int32(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt16to64 (And16 (Const16 [c]) _)) (Const64 [d])) // cond: 0 <= c && int64(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && int64(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (And32 (Const32 [c]) _) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd32 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt32to64 (And32 (Const32 [c]) _)) (Const64 [d])) // cond: 0 <= c && int64(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt32to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd32 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && int64(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (And64 (Const64 [c]) _) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd64 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (Const32 [c]) (Const32 [d])) // result: (ConstBool [0 <= c && c < d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(0 <= c && c < d) return true } // match: (IsInBounds (Const64 [c]) (Const64 [d])) // result: (ConstBool [0 <= c && c < d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(0 <= c && c < d) return true } // match: (IsInBounds (Mod32u _ y) y) // result: (ConstBool [true]) for { if v_0.Op != OpMod32u { break } y := v_0.Args[1] if y != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (Mod64u _ y) y) // result: (ConstBool [true]) for { if v_0.Op != OpMod64u { break } y := v_0.Args[1] if y != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt8to64 (Rsh8Ux64 _ (Const64 [c]))) (Const64 [d])) // cond: 0 < c && c < 8 && 1<= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 || v_1.Op != OpAnd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq16 (Const16 [0]) (Rsh16Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 || v_1.Op != OpRsh16Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq16U (Const16 [c]) (Const16 [d])) // result: (ConstBool [uint16(c) <= uint16(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint16(c) <= uint16(d)) return true } // match: (Leq16U (Const16 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } // match: (Leq32 (Const32 [0]) (And32 _ (Const32 [c]))) // cond: c >= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 || v_1.Op != OpAnd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq32 (Const32 [0]) (Rsh32Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 || v_1.Op != OpRsh32Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } return false } func rewriteValuegeneric_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq32U (Const32 [c]) (Const32 [d])) // result: (ConstBool [uint32(c) <= uint32(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint32(c) <= uint32(d)) return true } // match: (Leq32U (Const32 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } // match: (Leq64 (Const64 [0]) (And64 _ (Const64 [c]))) // cond: c >= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 || v_1.Op != OpAnd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq64 (Const64 [0]) (Rsh64Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 || v_1.Op != OpRsh64Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } return false } func rewriteValuegeneric_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq64U (Const64 [c]) (Const64 [d])) // result: (ConstBool [uint64(c) <= uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint64(c) <= uint64(d)) return true } // match: (Leq64U (Const64 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } // match: (Leq8 (Const8 [0]) (And8 _ (Const8 [c]))) // cond: c >= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 || v_1.Op != OpAnd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq8 (Const8 [0]) (Rsh8Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 || v_1.Op != OpRsh8Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq8U (Const8 [c]) (Const8 [d])) // result: (ConstBool [ uint8(c) <= uint8(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint8(c) <= uint8(d)) return true } // match: (Leq8U (Const8 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16 (Const16 [c]) (Const16 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less16 (Const16 [0]) x) // cond: isNonNegative(x) // result: (Neq16 (Const16 [0]) x) for { if v_0.Op != OpConst16 { break } t := v_0.Type if auxIntToInt16(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less16 x (Const16 [1])) // cond: isNonNegative(x) // result: (Eq16 (Const16 [0]) x) for { x := v_0 if v_1.Op != OpConst16 { break } t := v_1.Type if auxIntToInt16(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less16U (Const16 [c]) (Const16 [d])) // result: (ConstBool [uint16(c) < uint16(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint16(c) < uint16(d)) return true } // match: (Less16U _ (Const16 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less32 (Const32 [0]) x) // cond: isNonNegative(x) // result: (Neq32 (Const32 [0]) x) for { if v_0.Op != OpConst32 { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less32 x (Const32 [1])) // cond: isNonNegative(x) // result: (Eq32 (Const32 [0]) x) for { x := v_0 if v_1.Op != OpConst32 { break } t := v_1.Type if auxIntToInt32(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } return false } func rewriteValuegeneric_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less32U (Const32 [c]) (Const32 [d])) // result: (ConstBool [uint32(c) < uint32(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint32(c) < uint32(d)) return true } // match: (Less32U _ (Const32 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less64 (Const64 [0]) x) // cond: isNonNegative(x) // result: (Neq64 (Const64 [0]) x) for { if v_0.Op != OpConst64 { break } t := v_0.Type if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less64 x (Const64 [1])) // cond: isNonNegative(x) // result: (Eq64 (Const64 [0]) x) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } return false } func rewriteValuegeneric_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less64U (Const64 [c]) (Const64 [d])) // result: (ConstBool [uint64(c) < uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint64(c) < uint64(d)) return true } // match: (Less64U _ (Const64 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less8 (Const8 [0]) x) // cond: isNonNegative(x) // result: (Neq8 (Const8 [0]) x) for { if v_0.Op != OpConst8 { break } t := v_0.Type if auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less8 x (Const8 [1])) // cond: isNonNegative(x) // result: (Eq8 (Const8 [0]) x) for { x := v_0 if v_1.Op != OpConst8 { break } t := v_1.Type if auxIntToInt8(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less8U (Const8 [c]) (Const8 [d])) // result: (ConstBool [ uint8(c) < uint8(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint8(c) < uint8(d)) return true } // match: (Less8U _ (Const8 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (Load p1 (Store {t2} p2 x _)) // cond: isSamePtr(p1, p2) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) x := v_1.Args[1] p2 := v_1.Args[0] if !(isSamePtr(p1, p2) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size()) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 x _))) // cond: isSamePtr(p1, p3) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p3, t3.Size(), p2, t2.Size()) // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) x := v_1_2.Args[1] p3 := v_1_2.Args[0] if !(isSamePtr(p1, p3) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p3, t3.Size(), p2, t2.Size())) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 x _)))) // cond: isSamePtr(p1, p4) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p4, t4.Size(), p2, t2.Size()) && disjoint(p4, t4.Size(), p3, t3.Size()) // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) x := v_1_2_2.Args[1] p4 := v_1_2_2.Args[0] if !(isSamePtr(p1, p4) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p4, t4.Size(), p2, t2.Size()) && disjoint(p4, t4.Size(), p3, t3.Size())) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 x _))))) // cond: isSamePtr(p1, p5) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p5, t5.Size(), p2, t2.Size()) && disjoint(p5, t5.Size(), p3, t3.Size()) && disjoint(p5, t5.Size(), p4, t4.Size()) // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] v_1_2_2_2 := v_1_2_2.Args[2] if v_1_2_2_2.Op != OpStore { break } t5 := auxToType(v_1_2_2_2.Aux) x := v_1_2_2_2.Args[1] p5 := v_1_2_2_2.Args[0] if !(isSamePtr(p1, p5) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p5, t5.Size(), p2, t2.Size()) && disjoint(p5, t5.Size(), p3, t3.Size()) && disjoint(p5, t5.Size(), p4, t4.Size())) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 (Const64 [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x))) // result: (Const64F [math.Float64frombits(uint64(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } x := auxIntToInt64(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x)))) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(math.Float64frombits(uint64(x))) return true } // match: (Load p1 (Store {t2} p2 (Const32 [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x)))) // result: (Const32F [math.Float32frombits(uint32(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } x := auxIntToInt32(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x))))) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(math.Float32frombits(uint32(x))) return true } // match: (Load p1 (Store {t2} p2 (Const64F [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitInt(t1) // result: (Const64 [int64(math.Float64bits(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64F { break } x := auxIntToFloat64(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitInt(t1)) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(math.Float64bits(x))) return true } // match: (Load p1 (Store {t2} p2 (Const32F [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitInt(t1) // result: (Const32 [int32(math.Float32bits(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32F { break } x := auxIntToFloat32(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitInt(t1)) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(math.Float32bits(x))) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ mem:(Zero [n] p3 _))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p3) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) // result: @mem.Block (Load (OffPtr [o1] p3) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] mem := v_1.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p3 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p3) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p3) v0.AddArg2(v1, mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ mem:(Zero [n] p4 _)))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p4) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) // result: @mem.Block (Load (OffPtr [o1] p4) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] mem := v_1_2.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p4 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p4) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p4) v0.AddArg2(v1, mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ mem:(Zero [n] p5 _))))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p5) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) // result: @mem.Block (Load (OffPtr [o1] p5) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] mem := v_1_2_2.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p5 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p5) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p5) v0.AddArg2(v1, mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 _ mem:(Zero [n] p6 _)))))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p6) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) && disjoint(op, t1.Size(), p5, t5.Size()) // result: @mem.Block (Load (OffPtr [o1] p6) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] v_1_2_2_2 := v_1_2_2.Args[2] if v_1_2_2_2.Op != OpStore { break } t5 := auxToType(v_1_2_2_2.Aux) _ = v_1_2_2_2.Args[2] p5 := v_1_2_2_2.Args[0] mem := v_1_2_2_2.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p6 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p6) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) && disjoint(op, t1.Size(), p5, t5.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p6) v0.AddArg2(v1, mem) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: t1.IsBoolean() && isSamePtr(p1, p2) && n >= o + 1 // result: (ConstBool [false]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(t1.IsBoolean() && isSamePtr(p1, p2) && n >= o+1) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is8BitInt(t1) && isSamePtr(p1, p2) && n >= o + 1 // result: (Const8 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is8BitInt(t1) && isSamePtr(p1, p2) && n >= o+1) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is16BitInt(t1) && isSamePtr(p1, p2) && n >= o + 2 // result: (Const16 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is16BitInt(t1) && isSamePtr(p1, p2) && n >= o+2) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is32BitInt(t1) && isSamePtr(p1, p2) && n >= o + 4 // result: (Const32 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is32BitInt(t1) && isSamePtr(p1, p2) && n >= o+4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is64BitInt(t1) && isSamePtr(p1, p2) && n >= o + 8 // result: (Const64 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is64BitInt(t1) && isSamePtr(p1, p2) && n >= o+8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is32BitFloat(t1) && isSamePtr(p1, p2) && n >= o + 4 // result: (Const32F [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is32BitFloat(t1) && isSamePtr(p1, p2) && n >= o+4) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is64BitFloat(t1) && isSamePtr(p1, p2) && n >= o + 8 // result: (Const64F [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is64BitFloat(t1) && isSamePtr(p1, p2) && n >= o+8) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(0) return true } // match: (Load _ _) // cond: t.IsStruct() && t.NumFields() == 0 && fe.CanSSA(t) // result: (StructMake0) for { t := v.Type if !(t.IsStruct() && t.NumFields() == 0 && fe.CanSSA(t)) { break } v.reset(OpStructMake0) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 1 && fe.CanSSA(t) // result: (StructMake1 (Load (OffPtr [0] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 1 && fe.CanSSA(t)) { break } v.reset(OpStructMake1) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v.AddArg(v0) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 2 && fe.CanSSA(t) // result: (StructMake2 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 2 && fe.CanSSA(t)) { break } v.reset(OpStructMake2) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = int64ToAuxInt(t.FieldOff(1)) v3.AddArg(ptr) v2.AddArg2(v3, mem) v.AddArg2(v0, v2) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 3 && fe.CanSSA(t) // result: (StructMake3 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem) (Load (OffPtr [t.FieldOff(2)] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 3 && fe.CanSSA(t)) { break } v.reset(OpStructMake3) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = int64ToAuxInt(t.FieldOff(1)) v3.AddArg(ptr) v2.AddArg2(v3, mem) v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2)) v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v5.AuxInt = int64ToAuxInt(t.FieldOff(2)) v5.AddArg(ptr) v4.AddArg2(v5, mem) v.AddArg3(v0, v2, v4) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 4 && fe.CanSSA(t) // result: (StructMake4 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem) (Load (OffPtr [t.FieldOff(2)] ptr) mem) (Load (OffPtr [t.FieldOff(3)] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 4 && fe.CanSSA(t)) { break } v.reset(OpStructMake4) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = int64ToAuxInt(t.FieldOff(1)) v3.AddArg(ptr) v2.AddArg2(v3, mem) v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2)) v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v5.AuxInt = int64ToAuxInt(t.FieldOff(2)) v5.AddArg(ptr) v4.AddArg2(v5, mem) v6 := b.NewValue0(v.Pos, OpLoad, t.FieldType(3)) v7 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo()) v7.AuxInt = int64ToAuxInt(t.FieldOff(3)) v7.AddArg(ptr) v6.AddArg2(v7, mem) v.AddArg4(v0, v2, v4, v6) return true } // match: (Load _ _) // cond: t.IsArray() && t.NumElem() == 0 // result: (ArrayMake0) for { t := v.Type if !(t.IsArray() && t.NumElem() == 0) { break } v.reset(OpArrayMake0) return true } // match: (Load ptr mem) // cond: t.IsArray() && t.NumElem() == 1 && fe.CanSSA(t) // result: (ArrayMake1 (Load ptr mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsArray() && t.NumElem() == 1 && fe.CanSSA(t)) { break } v.reset(OpArrayMake1) v0 := b.NewValue0(v.Pos, OpLoad, t.Elem()) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x16 x (Const16 [c])) // result: (Lsh16x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh16x16 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x32 x (Const32 [c])) // result: (Lsh16x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh16x32 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x64 (Const16 [c]) (Const64 [d])) // result: (Const16 [c << uint64(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c << uint64(d)) return true } // match: (Lsh16x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh16x64 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Lsh16x64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Lsh16x64 (Lsh16x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh16x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh16x64 (Rsh16Ux64 (Lsh16x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh16x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh16x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x8 x (Const8 [c])) // result: (Lsh16x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh16x8 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x16 x (Const16 [c])) // result: (Lsh32x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh32x16 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x32 x (Const32 [c])) // result: (Lsh32x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh32x32 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x64 (Const32 [c]) (Const64 [d])) // result: (Const32 [c << uint64(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c << uint64(d)) return true } // match: (Lsh32x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh32x64 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Lsh32x64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Lsh32x64 (Lsh32x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh32x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh32x64 (Rsh32Ux64 (Lsh32x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh32x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh32x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x8 x (Const8 [c])) // result: (Lsh32x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh32x8 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x16 x (Const16 [c])) // result: (Lsh64x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh64x16 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x32 x (Const32 [c])) // result: (Lsh64x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh64x32 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c << uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c << uint64(d)) return true } // match: (Lsh64x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh64x64 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Lsh64x64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (Const64 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 64) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Lsh64x64 (Lsh64x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh64x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh64x64 (Rsh64Ux64 (Lsh64x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh64x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh64x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x8 x (Const8 [c])) // result: (Lsh64x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh64x8 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x16 x (Const16 [c])) // result: (Lsh8x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh8x16 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x32 x (Const32 [c])) // result: (Lsh8x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh8x32 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x64 (Const8 [c]) (Const64 [d])) // result: (Const8 [c << uint64(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c << uint64(d)) return true } // match: (Lsh8x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh8x64 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Lsh8x64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Lsh8x64 (Lsh8x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh8x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh8x64 (Rsh8Ux64 (Lsh8x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh8x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh8x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x8 x (Const8 [c])) // result: (Lsh8x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh8x8 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod16 (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [c % d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c % d) return true } // match: (Mod16 n (Const16 [c])) // cond: isNonNegative(n) && isPowerOfTwo16(c) // result: (And16 n (Const16 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo16(c)) { break } v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod16 n (Const16 [c])) // cond: c < 0 && c != -1<<15 // result: (Mod16 n (Const16 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(c < 0 && c != -1<<15) { break } v.reset(OpMod16) v.Type = t v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod16 x (Const16 [c])) // cond: x.Op != OpConst16 && (c > 0 || c == -1<<15) // result: (Sub16 x (Mul16 (Div16 x (Const16 [c])) (Const16 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(x.Op != OpConst16 && (c > 0 || c == -1<<15)) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpMul16, t) v1 := b.NewValue0(v.Pos, OpDiv16, t) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod16u (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int16(uint16(c) % uint16(d))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint16(c) % uint16(d))) return true } // match: (Mod16u n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (And16 n (Const16 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { break } v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod16u x (Const16 [c])) // cond: x.Op != OpConst16 && c > 0 && umagicOK16(c) // result: (Sub16 x (Mul16 (Div16u x (Const16 [c])) (Const16 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(x.Op != OpConst16 && c > 0 && umagicOK16(c)) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpMul16, t) v1 := b.NewValue0(v.Pos, OpDiv16u, t) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod32 (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [c % d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c % d) return true } // match: (Mod32 n (Const32 [c])) // cond: isNonNegative(n) && isPowerOfTwo32(c) // result: (And32 n (Const32 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo32(c)) { break } v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod32 n (Const32 [c])) // cond: c < 0 && c != -1<<31 // result: (Mod32 n (Const32 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(c < 0 && c != -1<<31) { break } v.reset(OpMod32) v.Type = t v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod32 x (Const32 [c])) // cond: x.Op != OpConst32 && (c > 0 || c == -1<<31) // result: (Sub32 x (Mul32 (Div32 x (Const32 [c])) (Const32 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(x.Op != OpConst32 && (c > 0 || c == -1<<31)) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpMul32, t) v1 := b.NewValue0(v.Pos, OpDiv32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod32u (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int32(uint32(c) % uint32(d))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint32(c) % uint32(d))) return true } // match: (Mod32u n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (And32 n (Const32 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { break } v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod32u x (Const32 [c])) // cond: x.Op != OpConst32 && c > 0 && umagicOK32(c) // result: (Sub32 x (Mul32 (Div32u x (Const32 [c])) (Const32 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(x.Op != OpConst32 && c > 0 && umagicOK32(c)) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpMul32, t) v1 := b.NewValue0(v.Pos, OpDiv32u, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod64 (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [c % d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c % d) return true } // match: (Mod64 n (Const64 [c])) // cond: isNonNegative(n) && isPowerOfTwo64(c) // result: (And64 n (Const64 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo64(c)) { break } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod64 n (Const64 [-1<<63])) // cond: isNonNegative(n) // result: n for { n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 || !(isNonNegative(n)) { break } v.copyOf(n) return true } // match: (Mod64 n (Const64 [c])) // cond: c < 0 && c != -1<<63 // result: (Mod64 n (Const64 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c < 0 && c != -1<<63) { break } v.reset(OpMod64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod64 x (Const64 [c])) // cond: x.Op != OpConst64 && (c > 0 || c == -1<<63) // result: (Sub64 x (Mul64 (Div64 x (Const64 [c])) (Const64 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(x.Op != OpConst64 && (c > 0 || c == -1<<63)) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpMul64, t) v1 := b.NewValue0(v.Pos, OpDiv64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod64u (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [int64(uint64(c) % uint64(d))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint64(c) % uint64(d))) return true } // match: (Mod64u n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (And64 n (Const64 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod64u n (Const64 [-1<<63])) // result: (And64 n (Const64 [1<<63-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 { break } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(1<<63 - 1) v.AddArg2(n, v0) return true } // match: (Mod64u x (Const64 [c])) // cond: x.Op != OpConst64 && c > 0 && umagicOK64(c) // result: (Sub64 x (Mul64 (Div64u x (Const64 [c])) (Const64 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(x.Op != OpConst64 && c > 0 && umagicOK64(c)) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpMul64, t) v1 := b.NewValue0(v.Pos, OpDiv64u, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod8 (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [c % d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c % d) return true } // match: (Mod8 n (Const8 [c])) // cond: isNonNegative(n) && isPowerOfTwo8(c) // result: (And8 n (Const8 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo8(c)) { break } v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod8 n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Mod8 n (Const8 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(c < 0 && c != -1<<7) { break } v.reset(OpMod8) v.Type = t v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod8 x (Const8 [c])) // cond: x.Op != OpConst8 && (c > 0 || c == -1<<7) // result: (Sub8 x (Mul8 (Div8 x (Const8 [c])) (Const8 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(x.Op != OpConst8 && (c > 0 || c == -1<<7)) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpMul8, t) v1 := b.NewValue0(v.Pos, OpDiv8, t) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod8u (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int8(uint8(c) % uint8(d))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(uint8(c) % uint8(d))) return true } // match: (Mod8u n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (And8 n (Const8 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { break } v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod8u x (Const8 [c])) // cond: x.Op != OpConst8 && c > 0 && umagicOK8( c) // result: (Sub8 x (Mul8 (Div8u x (Const8 [c])) (Const8 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(x.Op != OpConst8 && c > 0 && umagicOK8(c)) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpMul8, t) v1 := b.NewValue0(v.Pos, OpDiv8u, t) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Move {t} [n] dst1 src mem:(Zero {t} [n] dst2 _)) // cond: isSamePtr(src, dst2) // result: (Zero {t} [n] dst1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src := v_1 mem := v_2 if mem.Op != OpZero || auxIntToInt64(mem.AuxInt) != n || auxToType(mem.Aux) != t { break } dst2 := mem.Args[0] if !(isSamePtr(src, dst2)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst1, mem) return true } // match: (Move {t} [n] dst1 src mem:(VarDef (Zero {t} [n] dst0 _))) // cond: isSamePtr(src, dst0) // result: (Zero {t} [n] dst1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpZero || auxIntToInt64(mem_0.AuxInt) != n || auxToType(mem_0.Aux) != t { break } dst0 := mem_0.Args[0] if !(isSamePtr(src, dst0)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst1, mem) return true } // match: (Move {t} [n] dst (Addr {sym} (SB)) mem) // cond: symIsROZero(sym) // result: (Zero {t} [n] dst mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst := v_0 if v_1.Op != OpAddr { break } sym := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } mem := v_2 if !(symIsROZero(sym)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst, mem) return true } // match: (Move {t1} [n] dst1 src1 store:(Store {t2} op:(OffPtr [o2] dst2) _ mem)) // cond: isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2 + t2.Size() && disjoint(src1, n, op, t2.Size()) && clobber(store) // result: (Move {t1} [n] dst1 src1 mem) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst1 := v_0 src1 := v_1 store := v_2 if store.Op != OpStore { break } t2 := auxToType(store.Aux) mem := store.Args[2] op := store.Args[0] if op.Op != OpOffPtr { break } o2 := auxIntToInt64(op.AuxInt) dst2 := op.Args[0] if !(isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2+t2.Size() && disjoint(src1, n, op, t2.Size()) && clobber(store)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t1) v.AddArg3(dst1, src1, mem) return true } // match: (Move {t} [n] dst1 src1 move:(Move {t} [n] dst2 _ mem)) // cond: move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move) // result: (Move {t} [n] dst1 src1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 move := v_2 if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg3(dst1, src1, mem) return true } // match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem))) // cond: move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move, vardef) // result: (Move {t} [n] dst1 src1 (VarDef {x} mem)) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 vardef := v_2 if vardef.Op != OpVarDef { break } x := auxToSym(vardef.Aux) move := vardef.Args[0] if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move, vardef)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg3(dst1, src1, v0) return true } // match: (Move {t} [n] dst1 src1 zero:(Zero {t} [n] dst2 mem)) // cond: zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero) // result: (Move {t} [n] dst1 src1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 zero := v_2 if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != n || auxToType(zero.Aux) != t { break } mem := zero.Args[1] dst2 := zero.Args[0] if !(zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg3(dst1, src1, mem) return true } // match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} zero:(Zero {t} [n] dst2 mem))) // cond: zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero, vardef) // result: (Move {t} [n] dst1 src1 (VarDef {x} mem)) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 vardef := v_2 if vardef.Op != OpVarDef { break } x := auxToSym(vardef.Aux) zero := vardef.Args[0] if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != n || auxToType(zero.Aux) != t { break } mem := zero.Args[1] dst2 := zero.Args[0] if !(zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero, vardef)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg3(dst1, src1, v0) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [0] p3) d2 _))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size() + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [0] dst) d2 mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) d2 := mem_2.Args[1] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type if auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size()+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(0) v2.AddArg(dst) v1.AddArg3(v2, d2, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [0] p4) d3 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [0] dst) d3 mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) d3 := mem_2_2.Args[1] op4 := mem_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type if auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(0) v4.AddArg(dst) v3.AddArg3(v4, d3, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [o4] p4) d3 (Store {t5} op5:(OffPtr [0] p5) d4 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [0] dst) d4 mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] op4 := mem_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type o4 := auxIntToInt64(op4.AuxInt) p4 := op4.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpStore { break } t5 := auxToType(mem_2_2_2.Aux) d4 := mem_2_2_2.Args[1] op5 := mem_2_2_2.Args[0] if op5.Op != OpOffPtr { break } tt5 := op5.Type if auxIntToInt64(op5.AuxInt) != 0 { break } p5 := op5.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(0) v6.AddArg(dst) v5.AddArg3(v6, d4, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [0] p3) d2 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size() + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [0] dst) d2 mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) d2 := mem_0_2.Args[1] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type if auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size()+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(0) v2.AddArg(dst) v1.AddArg3(v2, d2, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [0] p4) d3 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [0] dst) d3 mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) d3 := mem_0_2_2.Args[1] op4 := mem_0_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type if auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(0) v4.AddArg(dst) v3.AddArg3(v4, d3, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [o4] p4) d3 (Store {t5} op5:(OffPtr [0] p5) d4 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [0] dst) d4 mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) _ = mem_0_2_2.Args[2] op4 := mem_0_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type o4 := auxIntToInt64(op4.AuxInt) p4 := op4.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpStore { break } t5 := auxToType(mem_0_2_2_2.Aux) d4 := mem_0_2_2_2.Args[1] op5 := mem_0_2_2_2.Args[0] if op5.Op != OpOffPtr { break } tt5 := op5.Type if auxIntToInt64(op5.AuxInt) != 0 { break } p5 := op5.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(0) v6.AddArg(dst) v5.AddArg3(v6, d4, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Zero {t3} [n] p3 _))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2 + t2.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Zero {t1} [n] dst mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpZero || auxIntToInt64(mem_2.AuxInt) != n { break } t3 := auxToType(mem_2.Aux) p3 := mem_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2+t2.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(n) v1.Aux = typeToAux(t1) v1.AddArg2(dst, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Zero {t4} [n] p4 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + t2.Size() && n >= o3 + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Zero {t1} [n] dst mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := auxIntToInt64(mem_0.AuxInt) p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := auxIntToInt64(mem_2_0.AuxInt) p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpZero || auxIntToInt64(mem_2_2.AuxInt) != n { break } t4 := auxToType(mem_2_2.Aux) p4 := mem_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2+t2.Size() && n >= o3+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v3.AuxInt = int64ToAuxInt(n) v3.Aux = typeToAux(t1) v3.AddArg2(dst, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Zero {t5} [n] p5 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Zero {t1} [n] dst mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := auxIntToInt64(mem_0.AuxInt) p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := auxIntToInt64(mem_2_0.AuxInt) p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] mem_2_2_0 := mem_2_2.Args[0] if mem_2_2_0.Op != OpOffPtr { break } tt4 := mem_2_2_0.Type o4 := auxIntToInt64(mem_2_2_0.AuxInt) p4 := mem_2_2_0.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpZero || auxIntToInt64(mem_2_2_2.AuxInt) != n { break } t5 := auxToType(mem_2_2_2.Aux) p5 := mem_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v5.AuxInt = int64ToAuxInt(n) v5.Aux = typeToAux(t1) v5.AddArg2(dst, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Store {t5} (OffPtr [o5] p5) d4 (Zero {t6} [n] p6 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() && n >= o5 + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [o5] dst) d4 (Zero {t1} [n] dst mem))))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := auxIntToInt64(mem_0.AuxInt) p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := auxIntToInt64(mem_2_0.AuxInt) p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] mem_2_2_0 := mem_2_2.Args[0] if mem_2_2_0.Op != OpOffPtr { break } tt4 := mem_2_2_0.Type o4 := auxIntToInt64(mem_2_2_0.AuxInt) p4 := mem_2_2_0.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpStore { break } t5 := auxToType(mem_2_2_2.Aux) _ = mem_2_2_2.Args[2] mem_2_2_2_0 := mem_2_2_2.Args[0] if mem_2_2_2_0.Op != OpOffPtr { break } tt5 := mem_2_2_2_0.Type o5 := auxIntToInt64(mem_2_2_2_0.AuxInt) p5 := mem_2_2_2_0.Args[0] d4 := mem_2_2_2.Args[1] mem_2_2_2_2 := mem_2_2_2.Args[2] if mem_2_2_2_2.Op != OpZero || auxIntToInt64(mem_2_2_2_2.AuxInt) != n { break } t6 := auxToType(mem_2_2_2_2.Aux) p6 := mem_2_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size() && n >= o5+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(o5) v6.AddArg(dst) v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v7.AuxInt = int64ToAuxInt(n) v7.Aux = typeToAux(t1) v7.AddArg2(dst, mem) v5.AddArg3(v6, d4, v7) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Zero {t3} [n] p3 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2 + t2.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Zero {t1} [n] dst mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpZero || auxIntToInt64(mem_0_2.AuxInt) != n { break } t3 := auxToType(mem_0_2.Aux) p3 := mem_0_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2+t2.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(n) v1.Aux = typeToAux(t1) v1.AddArg2(dst, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Zero {t4} [n] p4 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + t2.Size() && n >= o3 + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Zero {t1} [n] dst mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := auxIntToInt64(mem_0_0.AuxInt) p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := auxIntToInt64(mem_0_2_0.AuxInt) p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2.AuxInt) != n { break } t4 := auxToType(mem_0_2_2.Aux) p4 := mem_0_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2+t2.Size() && n >= o3+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v3.AuxInt = int64ToAuxInt(n) v3.Aux = typeToAux(t1) v3.AddArg2(dst, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Zero {t5} [n] p5 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Zero {t1} [n] dst mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := auxIntToInt64(mem_0_0.AuxInt) p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := auxIntToInt64(mem_0_2_0.AuxInt) p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) _ = mem_0_2_2.Args[2] mem_0_2_2_0 := mem_0_2_2.Args[0] if mem_0_2_2_0.Op != OpOffPtr { break } tt4 := mem_0_2_2_0.Type o4 := auxIntToInt64(mem_0_2_2_0.AuxInt) p4 := mem_0_2_2_0.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2_2.AuxInt) != n { break } t5 := auxToType(mem_0_2_2_2.Aux) p5 := mem_0_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v5.AuxInt = int64ToAuxInt(n) v5.Aux = typeToAux(t1) v5.AddArg2(dst, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Store {t5} (OffPtr [o5] p5) d4 (Zero {t6} [n] p6 _))))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() && n >= o5 + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [o5] dst) d4 (Zero {t1} [n] dst mem))))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := auxIntToInt64(mem_0_0.AuxInt) p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := auxIntToInt64(mem_0_2_0.AuxInt) p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) _ = mem_0_2_2.Args[2] mem_0_2_2_0 := mem_0_2_2.Args[0] if mem_0_2_2_0.Op != OpOffPtr { break } tt4 := mem_0_2_2_0.Type o4 := auxIntToInt64(mem_0_2_2_0.AuxInt) p4 := mem_0_2_2_0.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpStore { break } t5 := auxToType(mem_0_2_2_2.Aux) _ = mem_0_2_2_2.Args[2] mem_0_2_2_2_0 := mem_0_2_2_2.Args[0] if mem_0_2_2_2_0.Op != OpOffPtr { break } tt5 := mem_0_2_2_2_0.Type o5 := auxIntToInt64(mem_0_2_2_2_0.AuxInt) p5 := mem_0_2_2_2_0.Args[0] d4 := mem_0_2_2_2.Args[1] mem_0_2_2_2_2 := mem_0_2_2_2.Args[2] if mem_0_2_2_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2_2_2.AuxInt) != n { break } t6 := auxToType(mem_0_2_2_2_2.Aux) p6 := mem_0_2_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size() && n >= o5+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(o5) v6.AddArg(dst) v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v7.AuxInt = int64ToAuxInt(n) v7.Aux = typeToAux(t1) v7.AddArg2(dst, mem) v5.AddArg3(v6, d4, v7) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [s] dst tmp1 midmem:(Move {t2} [s] tmp2 src _)) // cond: t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config)) // result: (Move {t1} [s] dst src midmem) for { s := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 tmp1 := v_1 midmem := v_2 if midmem.Op != OpMove || auxIntToInt64(midmem.AuxInt) != s { break } t2 := auxToType(midmem.Aux) src := midmem.Args[1] tmp2 := midmem.Args[0] if !(t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s) v.Aux = typeToAux(t1) v.AddArg3(dst, src, midmem) return true } // match: (Move {t1} [s] dst tmp1 midmem:(VarDef (Move {t2} [s] tmp2 src _))) // cond: t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config)) // result: (Move {t1} [s] dst src midmem) for { s := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 tmp1 := v_1 midmem := v_2 if midmem.Op != OpVarDef { break } midmem_0 := midmem.Args[0] if midmem_0.Op != OpMove || auxIntToInt64(midmem_0.AuxInt) != s { break } t2 := auxToType(midmem_0.Aux) src := midmem_0.Args[1] tmp2 := midmem_0.Args[0] if !(t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s) v.Aux = typeToAux(t1) v.AddArg3(dst, src, midmem) return true } // match: (Move dst src mem) // cond: isSamePtr(dst, src) // result: mem for { dst := v_0 src := v_1 mem := v_2 if !(isSamePtr(dst, src)) { break } v.copyOf(mem) return true } return false } func rewriteValuegeneric_OpMul16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c * d) return true } break } // match: (Mul16 (Const16 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul16 (Const16 [-1]) x) // result: (Neg16 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg16) v.AddArg(x) return true } break } // match: (Mul16 n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (Lsh16x64 n (Const64 [log16(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { continue } v.reset(OpLsh16x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log16(c)) v.AddArg2(n, v0) return true } break } // match: (Mul16 n (Const16 [c])) // cond: t.IsSigned() && isPowerOfTwo16(-c) // result: (Neg16 (Lsh16x64 n (Const64 [log16(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo16(-c)) { continue } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log16(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul16 (Const16 [0]) _) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (Mul16 (Mul16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Mul16 i (Mul16 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpMul16, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul16 (Const16 [c]) (Mul16 (Const16 [d]) x)) // result: (Mul16 (Const16 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpMul32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c * d) return true } break } // match: (Mul32 (Const32 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul32 (Const32 [-1]) x) // result: (Neg32 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg32) v.AddArg(x) return true } break } // match: (Mul32 n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (Lsh32x64 n (Const64 [log32(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { continue } v.reset(OpLsh32x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log32(c)) v.AddArg2(n, v0) return true } break } // match: (Mul32 n (Const32 [c])) // cond: t.IsSigned() && isPowerOfTwo32(-c) // result: (Neg32 (Lsh32x64 n (Const64 [log32(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo32(-c)) { continue } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpLsh32x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log32(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Add32 (Const32 [c*d]) (Mul32 (Const32 [c]) x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 || v_1.Type != t { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c * d) v1 := b.NewValue0(v.Pos, OpMul32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(c) v1.AddArg2(v2, x) v.AddArg2(v0, v1) return true } } break } // match: (Mul32 (Const32 [0]) _) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (Mul32 (Mul32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Mul32 i (Mul32 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpMul32, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul32 (Const32 [c]) (Mul32 (Const32 [d]) x)) // result: (Mul32 (Const32 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpMul32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mul32F (Const32F [c]) (Const32F [d])) // cond: c*d == c*d // result: (Const32F [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) if !(c*d == c*d) { continue } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c * d) return true } break } // match: (Mul32F x (Const32F [1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst32F || auxIntToFloat32(v_1.AuxInt) != 1 { continue } v.copyOf(x) return true } break } // match: (Mul32F x (Const32F [-1])) // result: (Neg32F x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst32F || auxIntToFloat32(v_1.AuxInt) != -1 { continue } v.reset(OpNeg32F) v.AddArg(x) return true } break } // match: (Mul32F x (Const32F [2])) // result: (Add32F x x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst32F || auxIntToFloat32(v_1.AuxInt) != 2 { continue } v.reset(OpAdd32F) v.AddArg2(x, x) return true } break } return false } func rewriteValuegeneric_OpMul64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c * d) return true } break } // match: (Mul64 (Const64 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul64 (Const64 [-1]) x) // result: (Neg64 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg64) v.AddArg(x) return true } break } // match: (Mul64 n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (Lsh64x64 n (Const64 [log64(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpLsh64x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(n, v0) return true } break } // match: (Mul64 n (Const64 [c])) // cond: t.IsSigned() && isPowerOfTwo64(-c) // result: (Neg64 (Lsh64x64 n (Const64 [log64(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo64(-c)) { continue } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpLsh64x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log64(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 || v_1.Type != t { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c * d) v1 := b.NewValue0(v.Pos, OpMul64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(c) v1.AddArg2(v2, x) v.AddArg2(v0, v1) return true } } break } // match: (Mul64 (Const64 [0]) _) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (Mul64 (Mul64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Mul64 i (Mul64 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpMul64, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul64 (Const64 [c]) (Mul64 (Const64 [d]) x)) // result: (Mul64 (Const64 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpMul64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mul64F (Const64F [c]) (Const64F [d])) // cond: c*d == c*d // result: (Const64F [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) if !(c*d == c*d) { continue } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c * d) return true } break } // match: (Mul64F x (Const64F [1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst64F || auxIntToFloat64(v_1.AuxInt) != 1 { continue } v.copyOf(x) return true } break } // match: (Mul64F x (Const64F [-1])) // result: (Neg64F x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst64F || auxIntToFloat64(v_1.AuxInt) != -1 { continue } v.reset(OpNeg64F) v.AddArg(x) return true } break } // match: (Mul64F x (Const64F [2])) // result: (Add64F x x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst64F || auxIntToFloat64(v_1.AuxInt) != 2 { continue } v.reset(OpAdd64F) v.AddArg2(x, x) return true } break } return false } func rewriteValuegeneric_OpMul8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c * d) return true } break } // match: (Mul8 (Const8 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul8 (Const8 [-1]) x) // result: (Neg8 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg8) v.AddArg(x) return true } break } // match: (Mul8 n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (Lsh8x64 n (Const64 [log8(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { continue } v.reset(OpLsh8x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log8(c)) v.AddArg2(n, v0) return true } break } // match: (Mul8 n (Const8 [c])) // cond: t.IsSigned() && isPowerOfTwo8(-c) // result: (Neg8 (Lsh8x64 n (Const64 [log8(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo8(-c)) { continue } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log8(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul8 (Const8 [0]) _) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (Mul8 (Mul8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Mul8 i (Mul8 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpMul8, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul8 (Const8 [c]) (Mul8 (Const8 [d]) x)) // result: (Mul8 (Const8 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpNeg16(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg16 (Const16 [c])) // result: (Const16 [-c]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-c) return true } // match: (Neg16 (Sub16 x y)) // result: (Sub16 y x) for { if v_0.Op != OpSub16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub16) v.AddArg2(y, x) return true } // match: (Neg16 (Neg16 x)) // result: x for { if v_0.Op != OpNeg16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg16 (Com16 x)) // result: (Add16 (Const16 [1]) x) for { t := v.Type if v_0.Op != OpCom16 { break } x := v_0.Args[0] v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeg32(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg32 (Const32 [c])) // result: (Const32 [-c]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-c) return true } // match: (Neg32 (Sub32 x y)) // result: (Sub32 y x) for { if v_0.Op != OpSub32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub32) v.AddArg2(y, x) return true } // match: (Neg32 (Neg32 x)) // result: x for { if v_0.Op != OpNeg32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg32 (Com32 x)) // result: (Add32 (Const32 [1]) x) for { t := v.Type if v_0.Op != OpCom32 { break } x := v_0.Args[0] v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeg32F(v *Value) bool { v_0 := v.Args[0] // match: (Neg32F (Const32F [c])) // cond: c != 0 // result: (Const32F [-c]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if !(c != 0) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(-c) return true } return false } func rewriteValuegeneric_OpNeg64(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg64 (Const64 [c])) // result: (Const64 [-c]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-c) return true } // match: (Neg64 (Sub64 x y)) // result: (Sub64 y x) for { if v_0.Op != OpSub64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub64) v.AddArg2(y, x) return true } // match: (Neg64 (Neg64 x)) // result: x for { if v_0.Op != OpNeg64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg64 (Com64 x)) // result: (Add64 (Const64 [1]) x) for { t := v.Type if v_0.Op != OpCom64 { break } x := v_0.Args[0] v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeg64F(v *Value) bool { v_0 := v.Args[0] // match: (Neg64F (Const64F [c])) // cond: c != 0 // result: (Const64F [-c]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if !(c != 0) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(-c) return true } return false } func rewriteValuegeneric_OpNeg8(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg8 (Const8 [c])) // result: (Const8 [-c]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-c) return true } // match: (Neg8 (Sub8 x y)) // result: (Sub8 y x) for { if v_0.Op != OpSub8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub8) v.AddArg2(y, x) return true } // match: (Neg8 (Neg8 x)) // result: x for { if v_0.Op != OpNeg8 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg8 (Com8 x)) // result: (Add8 (Const8 [1]) x) for { t := v.Type if v_0.Op != OpCom8 { break } x := v_0.Args[0] v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq16 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Neq16 (Const16 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq16 (Const16 [c]) (Const16 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Neq16 (And16 n (Const16 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh16x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh16x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd16 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh16Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh16x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 15 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 15 && kbar == 16-k) { continue } v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(1< x (Const16 [y])) (Const16 [y])) // cond: oneBit16(y) // result: (Eq16 (And16 x (Const16 [y])) (Const16 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst16 || v_0_1.Type != t { continue } y := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || v_1.Type != t || auxIntToInt16(v_1.AuxInt) != y || !(oneBit16(y)) { continue } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq32 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Neq32 (Const32 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Neq32 (And32 n (Const32 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh32x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd32 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh32Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh32x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 31 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 31 && kbar == 32-k) { continue } v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(1< x (Const32 [y])) (Const32 [y])) // cond: oneBit32(y) // result: (Eq32 (And32 x (Const32 [y])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst32 || v_0_1.Type != t { continue } y := auxIntToInt32(v_0_1.AuxInt) if v_1.Op != OpConst32 || v_1.Type != t || auxIntToInt32(v_1.AuxInt) != y || !(oneBit32(y)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Neq32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } return false } func rewriteValuegeneric_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq64 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Neq64 (Const64 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Neq64 (And64 n (Const64 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh64x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd64 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh64Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh64x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 63 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 63 && kbar == 64-k) { continue } v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(1< x (Const64 [y])) (Const64 [y])) // cond: oneBit64(y) // result: (Eq64 (And64 x (Const64 [y])) (Const64 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst64 || v_0_1.Type != t { continue } y := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 || v_1.Type != t || auxIntToInt64(v_1.AuxInt) != y || !(oneBit64(y)) { continue } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Neq64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } return false } func rewriteValuegeneric_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq8 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Neq8 (Const8 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Neq8 (And8 n (Const8 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh8x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh8x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd8 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh8Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh8x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 7 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 7 && kbar == 8-k) { continue } v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(1< x (Const8 [y])) (Const8 [y])) // cond: oneBit8(y) // result: (Eq8 (And8 x (Const8 [y])) (Const8 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst8 || v_0_1.Type != t { continue } y := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || v_1.Type != t || auxIntToInt8(v_1.AuxInt) != y || !(oneBit8(y)) { continue } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (NeqB (ConstBool [c]) (ConstBool [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool { continue } c := auxIntToBool(v_0.AuxInt) if v_1.Op != OpConstBool { continue } d := auxIntToBool(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (NeqB (ConstBool [false]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != false { continue } x := v_1 v.copyOf(x) return true } break } // match: (NeqB (ConstBool [true]) x) // result: (Not x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != true { continue } x := v_1 v.reset(OpNot) v.AddArg(x) return true } break } // match: (NeqB (Not x) (Not y)) // result: (NeqB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpNot { continue } x := v_0.Args[0] if v_1.Op != OpNot { continue } y := v_1.Args[0] v.reset(OpNeqB) v.AddArg2(x, y) return true } break } return false } func rewriteValuegeneric_OpNeqInter(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (NeqInter x y) // result: (NeqPtr (ITab x) (ITab y)) for { x := v_0 y := v_1 v.reset(OpNeqPtr) v0 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (NeqPtr x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (NeqPtr (Addr {x} _) (Addr {y} _)) // result: (ConstBool [x != y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y) return true } break } // match: (NeqPtr (Addr {x} _) (OffPtr [o] (Addr {y} _))) // result: (ConstBool [x != y || o != 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o != 0) return true } break } // match: (NeqPtr (OffPtr [o1] (Addr {x} _)) (OffPtr [o2] (Addr {y} _))) // result: (ConstBool [x != y || o1 != o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o1 != o2) return true } break } // match: (NeqPtr (LocalAddr {x} _ _) (LocalAddr {y} _ _)) // result: (ConstBool [x != y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpLocalAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y) return true } break } // match: (NeqPtr (LocalAddr {x} _ _) (OffPtr [o] (LocalAddr {y} _ _))) // result: (ConstBool [x != y || o != 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o != 0) return true } break } // match: (NeqPtr (OffPtr [o1] (LocalAddr {x} _ _)) (OffPtr [o2] (LocalAddr {y} _ _))) // result: (ConstBool [x != y || o1 != o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o1 != o2) return true } break } // match: (NeqPtr (OffPtr [o1] p1) p2) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 != 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 != 0) return true } break } // match: (NeqPtr (OffPtr [o1] p1) (OffPtr [o2] p2)) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 != o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 != o2) return true } break } // match: (NeqPtr (Const32 [c]) (Const32 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (NeqPtr (Const64 [c]) (Const64 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (NeqPtr (LocalAddr _ _) (Addr _)) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (OffPtr (LocalAddr _ _)) (Addr _)) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (LocalAddr _ _) (OffPtr (Addr _))) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (OffPtr (LocalAddr _ _)) (OffPtr (Addr _))) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (AddPtr p1 o1) p2) // cond: isSamePtr(p1, p2) // result: (IsNonNil o1) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddPtr { continue } o1 := v_0.Args[1] p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpIsNonNil) v.AddArg(o1) return true } break } // match: (NeqPtr (Const32 [0]) p) // result: (IsNonNil p) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpIsNonNil) v.AddArg(p) return true } break } // match: (NeqPtr (Const64 [0]) p) // result: (IsNonNil p) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpIsNonNil) v.AddArg(p) return true } break } // match: (NeqPtr (ConstNil) p) // result: (IsNonNil p) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstNil { continue } p := v_1 v.reset(OpIsNonNil) v.AddArg(p) return true } break } return false } func rewriteValuegeneric_OpNeqSlice(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (NeqSlice x y) // result: (NeqPtr (SlicePtr x) (SlicePtr y)) for { x := v_0 y := v_1 v.reset(OpNeqPtr) v0 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpNilCheck(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (NilCheck (GetG mem) mem) // result: mem for { if v_0.Op != OpGetG { break } mem := v_0.Args[0] if mem != v_1 { break } v.copyOf(mem) return true } // match: (NilCheck (SelectN [0] call:(StaticLECall _ _)) _) // cond: isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check") // result: (Invalid) for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { break } call := v_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 || !(isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check")) { break } v.reset(OpInvalid) return true } // match: (NilCheck (OffPtr (SelectN [0] call:(StaticLECall _ _))) _) // cond: isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check") // result: (Invalid) for { if v_0.Op != OpOffPtr { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpSelectN || auxIntToInt64(v_0_0.AuxInt) != 0 { break } call := v_0_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 || !(isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check")) { break } v.reset(OpInvalid) return true } return false } func rewriteValuegeneric_OpNot(v *Value) bool { v_0 := v.Args[0] // match: (Not (ConstBool [c])) // result: (ConstBool [!c]) for { if v_0.Op != OpConstBool { break } c := auxIntToBool(v_0.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(!c) return true } // match: (Not (Eq64 x y)) // result: (Neq64 x y) for { if v_0.Op != OpEq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq64) v.AddArg2(x, y) return true } // match: (Not (Eq32 x y)) // result: (Neq32 x y) for { if v_0.Op != OpEq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq32) v.AddArg2(x, y) return true } // match: (Not (Eq16 x y)) // result: (Neq16 x y) for { if v_0.Op != OpEq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq16) v.AddArg2(x, y) return true } // match: (Not (Eq8 x y)) // result: (Neq8 x y) for { if v_0.Op != OpEq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq8) v.AddArg2(x, y) return true } // match: (Not (EqB x y)) // result: (NeqB x y) for { if v_0.Op != OpEqB { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeqB) v.AddArg2(x, y) return true } // match: (Not (EqPtr x y)) // result: (NeqPtr x y) for { if v_0.Op != OpEqPtr { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeqPtr) v.AddArg2(x, y) return true } // match: (Not (Eq64F x y)) // result: (Neq64F x y) for { if v_0.Op != OpEq64F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq64F) v.AddArg2(x, y) return true } // match: (Not (Eq32F x y)) // result: (Neq32F x y) for { if v_0.Op != OpEq32F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq32F) v.AddArg2(x, y) return true } // match: (Not (Neq64 x y)) // result: (Eq64 x y) for { if v_0.Op != OpNeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq64) v.AddArg2(x, y) return true } // match: (Not (Neq32 x y)) // result: (Eq32 x y) for { if v_0.Op != OpNeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq32) v.AddArg2(x, y) return true } // match: (Not (Neq16 x y)) // result: (Eq16 x y) for { if v_0.Op != OpNeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq16) v.AddArg2(x, y) return true } // match: (Not (Neq8 x y)) // result: (Eq8 x y) for { if v_0.Op != OpNeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq8) v.AddArg2(x, y) return true } // match: (Not (NeqB x y)) // result: (EqB x y) for { if v_0.Op != OpNeqB { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEqB) v.AddArg2(x, y) return true } // match: (Not (NeqPtr x y)) // result: (EqPtr x y) for { if v_0.Op != OpNeqPtr { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEqPtr) v.AddArg2(x, y) return true } // match: (Not (Neq64F x y)) // result: (Eq64F x y) for { if v_0.Op != OpNeq64F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq64F) v.AddArg2(x, y) return true } // match: (Not (Neq32F x y)) // result: (Eq32F x y) for { if v_0.Op != OpNeq32F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq32F) v.AddArg2(x, y) return true } // match: (Not (Less64 x y)) // result: (Leq64 y x) for { if v_0.Op != OpLess64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq64) v.AddArg2(y, x) return true } // match: (Not (Less32 x y)) // result: (Leq32 y x) for { if v_0.Op != OpLess32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq32) v.AddArg2(y, x) return true } // match: (Not (Less16 x y)) // result: (Leq16 y x) for { if v_0.Op != OpLess16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq16) v.AddArg2(y, x) return true } // match: (Not (Less8 x y)) // result: (Leq8 y x) for { if v_0.Op != OpLess8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq8) v.AddArg2(y, x) return true } // match: (Not (Less64U x y)) // result: (Leq64U y x) for { if v_0.Op != OpLess64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq64U) v.AddArg2(y, x) return true } // match: (Not (Less32U x y)) // result: (Leq32U y x) for { if v_0.Op != OpLess32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq32U) v.AddArg2(y, x) return true } // match: (Not (Less16U x y)) // result: (Leq16U y x) for { if v_0.Op != OpLess16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq16U) v.AddArg2(y, x) return true } // match: (Not (Less8U x y)) // result: (Leq8U y x) for { if v_0.Op != OpLess8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq8U) v.AddArg2(y, x) return true } // match: (Not (Leq64 x y)) // result: (Less64 y x) for { if v_0.Op != OpLeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess64) v.AddArg2(y, x) return true } // match: (Not (Leq32 x y)) // result: (Less32 y x) for { if v_0.Op != OpLeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess32) v.AddArg2(y, x) return true } // match: (Not (Leq16 x y)) // result: (Less16 y x) for { if v_0.Op != OpLeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess16) v.AddArg2(y, x) return true } // match: (Not (Leq8 x y)) // result: (Less8 y x) for { if v_0.Op != OpLeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess8) v.AddArg2(y, x) return true } // match: (Not (Leq64U x y)) // result: (Less64U y x) for { if v_0.Op != OpLeq64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess64U) v.AddArg2(y, x) return true } // match: (Not (Leq32U x y)) // result: (Less32U y x) for { if v_0.Op != OpLeq32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess32U) v.AddArg2(y, x) return true } // match: (Not (Leq16U x y)) // result: (Less16U y x) for { if v_0.Op != OpLeq16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess16U) v.AddArg2(y, x) return true } // match: (Not (Leq8U x y)) // result: (Less8U y x) for { if v_0.Op != OpLeq8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess8U) v.AddArg2(y, x) return true } return false } func rewriteValuegeneric_OpOffPtr(v *Value) bool { v_0 := v.Args[0] // match: (OffPtr (OffPtr p [y]) [x]) // result: (OffPtr p [x+y]) for { x := auxIntToInt64(v.AuxInt) if v_0.Op != OpOffPtr { break } y := auxIntToInt64(v_0.AuxInt) p := v_0.Args[0] v.reset(OpOffPtr) v.AuxInt = int64ToAuxInt(x + y) v.AddArg(p) return true } // match: (OffPtr p [0]) // cond: v.Type.Compare(p.Type) == types.CMPeq // result: p for { if auxIntToInt64(v.AuxInt) != 0 { break } p := v_0 if !(v.Type.Compare(p.Type) == types.CMPeq) { break } v.copyOf(p) return true } return false } func rewriteValuegeneric_OpOr16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Or16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c | d) return true } break } // match: (Or16 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or16 (Const16 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or16 (Const16 [-1]) _) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Or16 (Com16 x) x) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Or16 x (Or16 x y)) // result: (Or16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr16) v.AddArg2(x, y) return true } } break } // match: (Or16 (And16 x (Const16 [c2])) (Const16 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or16 (Const16 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst16 { continue } c2 := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 { continue } t := v_1.Type c1 := auxIntToInt16(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or16 (Or16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Or16 i (Or16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpOr16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or16 (Const16 [c]) (Or16 (Const16 [d]) x)) // result: (Or16 (Const16 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpOr16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpOr32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Or32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c | d) return true } break } // match: (Or32 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or32 (Const32 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or32 (Const32 [-1]) _) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Or32 (Com32 x) x) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Or32 x (Or32 x y)) // result: (Or32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr32) v.AddArg2(x, y) return true } } break } // match: (Or32 (And32 x (Const32 [c2])) (Const32 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or32 (Const32 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst32 { continue } c2 := auxIntToInt32(v_0_1.AuxInt) if v_1.Op != OpConst32 { continue } t := v_1.Type c1 := auxIntToInt32(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or32 (Or32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Or32 i (Or32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpOr32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or32 (Const32 [c]) (Or32 (Const32 [d]) x)) // result: (Or32 (Const32 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpOr32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpOr64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Or64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c | d) return true } break } // match: (Or64 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or64 (Const64 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or64 (Const64 [-1]) _) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Or64 (Com64 x) x) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Or64 x (Or64 x y)) // result: (Or64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr64) v.AddArg2(x, y) return true } } break } // match: (Or64 (And64 x (Const64 [c2])) (Const64 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or64 (Const64 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst64 { continue } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { continue } t := v_1.Type c1 := auxIntToInt64(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or64 (Or64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Or64 i (Or64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpOr64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or64 (Const64 [c]) (Or64 (Const64 [d]) x)) // result: (Or64 (Const64 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpOr64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpOr8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Or8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c | d) return true } break } // match: (Or8 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or8 (Const8 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or8 (Const8 [-1]) _) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Or8 (Com8 x) x) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Or8 x (Or8 x y)) // result: (Or8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr8) v.AddArg2(x, y) return true } } break } // match: (Or8 (And8 x (Const8 [c2])) (Const8 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or8 (Const8 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst8 { continue } c2 := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 { continue } t := v_1.Type c1 := auxIntToInt8(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or8 (Or8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Or8 i (Or8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpOr8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or8 (Const8 [c]) (Or8 (Const8 [d]) x)) // result: (Or8 (Const8 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpOr8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpOrB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (OrB (Less64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: c >= d // result: (Less64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: c >= d // result: (Leq64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: c >= d // result: (Less32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: c >= d // result: (Leq32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: c >= d // result: (Less16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: c >= d // result: (Leq16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: c >= d // result: (Less8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: c >= d // result: (Leq8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d) // result: (Less64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d) // result: (Leq64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d) // result: (Less32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d) // result: (Leq32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d) // result: (Less16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d) // result: (Leq16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d) // result: (Less8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d) // result: (Leq8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d) // result: (Less64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d) // result: (Leq64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d) // result: (Less32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d) // result: (Leq32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d) // result: (Less16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d) // result: (Leq16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d) // result: (Less8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d) // result: (Leq8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } return false } func rewriteValuegeneric_OpPhi(v *Value) bool { // match: (Phi (Const8 [c]) (Const8 [c])) // result: (Const8 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != c { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c) return true } // match: (Phi (Const16 [c]) (Const16 [c])) // result: (Const16 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != c { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c) return true } // match: (Phi (Const32 [c]) (Const32 [c])) // result: (Const32 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != c { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c) return true } // match: (Phi (Const64 [c]) (Const64 [c])) // result: (Const64 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != c { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValuegeneric_OpPtrIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (PtrIndex ptr idx) // cond: config.PtrSize == 4 && is32Bit(t.Elem().Size()) // result: (AddPtr ptr (Mul32 idx (Const32 [int32(t.Elem().Size())]))) for { t := v.Type ptr := v_0 idx := v_1 if !(config.PtrSize == 4 && is32Bit(t.Elem().Size())) { break } v.reset(OpAddPtr) v0 := b.NewValue0(v.Pos, OpMul32, typ.Int) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = int32ToAuxInt(int32(t.Elem().Size())) v0.AddArg2(idx, v1) v.AddArg2(ptr, v0) return true } // match: (PtrIndex ptr idx) // cond: config.PtrSize == 8 // result: (AddPtr ptr (Mul64 idx (Const64 [t.Elem().Size()]))) for { t := v.Type ptr := v_0 idx := v_1 if !(config.PtrSize == 8) { break } v.reset(OpAddPtr) v0 := b.NewValue0(v.Pos, OpMul64, typ.Int) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = int64ToAuxInt(t.Elem().Size()) v0.AddArg2(idx, v1) v.AddArg2(ptr, v0) return true } return false } func rewriteValuegeneric_OpRotateLeft16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (RotateLeft16 x (Const16 [c])) // cond: c%16 == 0 // result: x for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(c%16 == 0) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRotateLeft32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (RotateLeft32 x (Const32 [c])) // cond: c%32 == 0 // result: x for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(c%32 == 0) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRotateLeft64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (RotateLeft64 x (Const64 [c])) // cond: c%64 == 0 // result: x for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c%64 == 0) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRotateLeft8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (RotateLeft8 x (Const8 [c])) // cond: c%8 == 0 // result: x for { x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(c%8 == 0) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRound32F(v *Value) bool { v_0 := v.Args[0] // match: (Round32F x:(Const32F)) // result: x for { x := v_0 if x.Op != OpConst32F { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRound64F(v *Value) bool { v_0 := v.Args[0] // match: (Round64F x:(Const64F)) // result: x for { x := v_0 if x.Op != OpConst64F { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux16 x (Const16 [c])) // result: (Rsh16Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh16Ux16 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux32 x (Const32 [c])) // result: (Rsh16Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh16Ux32 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux64 (Const16 [c]) (Const64 [d])) // result: (Const16 [int16(uint16(c) >> uint64(d))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint16(c) >> uint64(d))) return true } // match: (Rsh16Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh16Ux64 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Rsh16Ux64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Rsh16Ux64 (Rsh16Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh16Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh16Ux64 (Rsh16x64 x _) (Const64 [15])) // result: (Rsh16Ux64 x (Const64 [15])) for { if v_0.Op != OpRsh16x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 15 { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(15) v.AddArg2(x, v0) return true } // match: (Rsh16Ux64 (Lsh16x64 (Rsh16Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh16Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh16Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } // match: (Rsh16Ux64 (Lsh16x64 x (Const64 [8])) (Const64 [8])) // result: (ZeroExt8to16 (Trunc16to8 x)) for { if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 8 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 8 { break } v.reset(OpZeroExt8to16) v0 := b.NewValue0(v.Pos, OpTrunc16to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux8 x (Const8 [c])) // result: (Rsh16Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh16Ux8 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x16 x (Const16 [c])) // result: (Rsh16x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh16x16 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x32 x (Const32 [c])) // result: (Rsh16x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh16x32 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x64 (Const16 [c]) (Const64 [d])) // result: (Const16 [c >> uint64(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c >> uint64(d)) return true } // match: (Rsh16x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh16x64 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Rsh16x64 (Rsh16x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh16x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh16x64 (Lsh16x64 x (Const64 [8])) (Const64 [8])) // result: (SignExt8to16 (Trunc16to8 x)) for { if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 8 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 8 { break } v.reset(OpSignExt8to16) v0 := b.NewValue0(v.Pos, OpTrunc16to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x8 x (Const8 [c])) // result: (Rsh16x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh16x8 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux16 x (Const16 [c])) // result: (Rsh32Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh32Ux16 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux32 x (Const32 [c])) // result: (Rsh32Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh32Ux32 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux64 (Const32 [c]) (Const64 [d])) // result: (Const32 [int32(uint32(c) >> uint64(d))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint32(c) >> uint64(d))) return true } // match: (Rsh32Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh32Ux64 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Rsh32Ux64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Rsh32Ux64 (Rsh32Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh32Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh32Ux64 (Rsh32x64 x _) (Const64 [31])) // result: (Rsh32Ux64 x (Const64 [31])) for { if v_0.Op != OpRsh32x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 31 { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(31) v.AddArg2(x, v0) return true } // match: (Rsh32Ux64 (Lsh32x64 (Rsh32Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh32Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } // match: (Rsh32Ux64 (Lsh32x64 x (Const64 [24])) (Const64 [24])) // result: (ZeroExt8to32 (Trunc32to8 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 24 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 24 { break } v.reset(OpZeroExt8to32) v0 := b.NewValue0(v.Pos, OpTrunc32to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh32Ux64 (Lsh32x64 x (Const64 [16])) (Const64 [16])) // result: (ZeroExt16to32 (Trunc32to16 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 16 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 16 { break } v.reset(OpZeroExt16to32) v0 := b.NewValue0(v.Pos, OpTrunc32to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux8 x (Const8 [c])) // result: (Rsh32Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh32Ux8 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x16 x (Const16 [c])) // result: (Rsh32x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh32x16 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x32 x (Const32 [c])) // result: (Rsh32x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh32x32 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x64 (Const32 [c]) (Const64 [d])) // result: (Const32 [c >> uint64(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c >> uint64(d)) return true } // match: (Rsh32x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh32x64 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Rsh32x64 (Rsh32x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh32x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh32x64 (Lsh32x64 x (Const64 [24])) (Const64 [24])) // result: (SignExt8to32 (Trunc32to8 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 24 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 24 { break } v.reset(OpSignExt8to32) v0 := b.NewValue0(v.Pos, OpTrunc32to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh32x64 (Lsh32x64 x (Const64 [16])) (Const64 [16])) // result: (SignExt16to32 (Trunc32to16 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 16 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 16 { break } v.reset(OpSignExt16to32) v0 := b.NewValue0(v.Pos, OpTrunc32to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x8 x (Const8 [c])) // result: (Rsh32x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh32x8 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux16 x (Const16 [c])) // result: (Rsh64Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh64Ux16 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux32 x (Const32 [c])) // result: (Rsh64Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh64Ux32 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux64 (Const64 [c]) (Const64 [d])) // result: (Const64 [int64(uint64(c) >> uint64(d))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) return true } // match: (Rsh64Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh64Ux64 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Rsh64Ux64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (Const64 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 64) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Rsh64Ux64 (Rsh64Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh64Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh64Ux64 (Rsh64x64 x _) (Const64 [63])) // result: (Rsh64Ux64 x (Const64 [63])) for { if v_0.Op != OpRsh64x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(63) v.AddArg2(x, v0) return true } // match: (Rsh64Ux64 (Lsh64x64 (Rsh64Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh64Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [56])) (Const64 [56])) // result: (ZeroExt8to64 (Trunc64to8 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 56 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 56 { break } v.reset(OpZeroExt8to64) v0 := b.NewValue0(v.Pos, OpTrunc64to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [48])) (Const64 [48])) // result: (ZeroExt16to64 (Trunc64to16 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 48 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 48 { break } v.reset(OpZeroExt16to64) v0 := b.NewValue0(v.Pos, OpTrunc64to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [32])) (Const64 [32])) // result: (ZeroExt32to64 (Trunc64to32 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 32 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 32 { break } v.reset(OpZeroExt32to64) v0 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux8 x (Const8 [c])) // result: (Rsh64Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh64Ux8 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x16 x (Const16 [c])) // result: (Rsh64x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh64x16 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x32 x (Const32 [c])) // result: (Rsh64x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh64x32 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c >> uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c >> uint64(d)) return true } // match: (Rsh64x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh64x64 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Rsh64x64 (Rsh64x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh64x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [56])) (Const64 [56])) // result: (SignExt8to64 (Trunc64to8 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 56 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 56 { break } v.reset(OpSignExt8to64) v0 := b.NewValue0(v.Pos, OpTrunc64to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [48])) (Const64 [48])) // result: (SignExt16to64 (Trunc64to16 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 48 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 48 { break } v.reset(OpSignExt16to64) v0 := b.NewValue0(v.Pos, OpTrunc64to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [32])) (Const64 [32])) // result: (SignExt32to64 (Trunc64to32 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 32 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 32 { break } v.reset(OpSignExt32to64) v0 := b.NewValue0(v.Pos, OpTrunc64to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x8 x (Const8 [c])) // result: (Rsh64x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh64x8 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux16 x (Const16 [c])) // result: (Rsh8Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh8Ux16 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux32 x (Const32 [c])) // result: (Rsh8Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh8Ux32 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux64 (Const8 [c]) (Const64 [d])) // result: (Const8 [int8(uint8(c) >> uint64(d))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(uint8(c) >> uint64(d))) return true } // match: (Rsh8Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh8Ux64 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Rsh8Ux64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Rsh8Ux64 (Rsh8Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh8Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh8Ux64 (Rsh8x64 x _) (Const64 [7] )) // result: (Rsh8Ux64 x (Const64 [7] )) for { if v_0.Op != OpRsh8x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 7 { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(7) v.AddArg2(x, v0) return true } // match: (Rsh8Ux64 (Lsh8x64 (Rsh8Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh8Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh8Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux8 x (Const8 [c])) // result: (Rsh8Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh8Ux8 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x16 x (Const16 [c])) // result: (Rsh8x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh8x16 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x32 x (Const32 [c])) // result: (Rsh8x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh8x32 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x64 (Const8 [c]) (Const64 [d])) // result: (Const8 [c >> uint64(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c >> uint64(d)) return true } // match: (Rsh8x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh8x64 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Rsh8x64 (Rsh8x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh8x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x8 x (Const8 [c])) // result: (Rsh8x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh8x8 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpSelect0(v *Value) bool { v_0 := v.Args[0] // match: (Select0 (Div128u (Const64 [0]) lo y)) // result: (Div64u lo y) for { if v_0.Op != OpDiv128u { break } y := v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { break } lo := v_0.Args[1] v.reset(OpDiv64u) v.AddArg2(lo, y) return true } // match: (Select0 (Mul32uover (Const32 [1]) x)) // result: x for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_0_1 v.copyOf(x) return true } break } // match: (Select0 (Mul64uover (Const64 [1]) x)) // result: x for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 1 { continue } x := v_0_1 v.copyOf(x) return true } break } // match: (Select0 (Mul64uover (Const64 [0]) x)) // result: (Const64 [0]) for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (Select0 (Mul32uover (Const32 [0]) x)) // result: (Const32 [0]) for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 0 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } return false } func rewriteValuegeneric_OpSelect1(v *Value) bool { v_0 := v.Args[0] // match: (Select1 (Div128u (Const64 [0]) lo y)) // result: (Mod64u lo y) for { if v_0.Op != OpDiv128u { break } y := v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { break } lo := v_0.Args[1] v.reset(OpMod64u) v.AddArg2(lo, y) return true } // match: (Select1 (Mul32uover (Const32 [1]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (Select1 (Mul64uover (Const64 [1]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 1 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (Select1 (Mul64uover (Const64 [0]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (Select1 (Mul32uover (Const32 [0]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 0 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } return false } func rewriteValuegeneric_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] (MakeResult x ___)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpMakeResult || len(v_0.Args) < 1 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (SelectN [1] (MakeResult x y ___)) // result: y for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpMakeResult || len(v_0.Args) < 2 { break } y := v_0.Args[1] v.copyOf(y) return true } // match: (SelectN [2] (MakeResult x y z ___)) // result: z for { if auxIntToInt64(v.AuxInt) != 2 || v_0.Op != OpMakeResult || len(v_0.Args) < 3 { break } z := v_0.Args[2] v.copyOf(z) return true } // match: (SelectN [0] call:(StaticCall {sym} s1:(Store _ (Const64 [sz]) s2:(Store _ src s3:(Store {t} _ dst mem))))) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call) // result: (Move {t.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpStore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpConst64 { break } sz := auxIntToInt64(s1_1.AuxInt) s2 := s1.Args[2] if s2.Op != OpStore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpStore { break } t := auxToType(s3.Aux) mem := s3.Args[2] dst := s3.Args[1] if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(t.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticCall {sym} s1:(Store _ (Const32 [sz]) s2:(Store _ src s3:(Store {t} _ dst mem))))) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call) // result: (Move {t.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpStore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpConst32 { break } sz := auxIntToInt32(s1_1.AuxInt) s2 := s1.Args[2] if s2.Op != OpStore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpStore { break } t := auxToType(s3.Aux) mem := s3.Args[2] dst := s3.Args[1] if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(t.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticCall {sym} dst src (Const64 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst64 { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticCall {sym} dst src (Const32 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst32 { break } sz := auxIntToInt32(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticLECall {sym} dst src (Const64 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst64 { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticLECall {sym} dst src (Const32 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst32 { break } sz := auxIntToInt32(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticLECall {sym} a x)) // cond: needRaceCleanup(sym, call) && clobber(call) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 2 { break } sym := auxToCall(call.Aux) x := call.Args[1] if !(needRaceCleanup(sym, call) && clobber(call)) { break } v.copyOf(x) return true } // match: (SelectN [0] call:(StaticLECall {sym} x)) // cond: needRaceCleanup(sym, call) && clobber(call) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) x := call.Args[0] if !(needRaceCleanup(sym, call) && clobber(call)) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt16to32(v *Value) bool { v_0 := v.Args[0] // match: (SignExt16to32 (Const16 [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } // match: (SignExt16to32 (Trunc32to16 x:(Rsh32x64 _ (Const64 [s])))) // cond: s >= 16 // result: x for { if v_0.Op != OpTrunc32to16 { break } x := v_0.Args[0] if x.Op != OpRsh32x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 16) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt16to64(v *Value) bool { v_0 := v.Args[0] // match: (SignExt16to64 (Const16 [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } // match: (SignExt16to64 (Trunc64to16 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 48 // result: x for { if v_0.Op != OpTrunc64to16 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 48) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt32to64(v *Value) bool { v_0 := v.Args[0] // match: (SignExt32to64 (Const32 [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } // match: (SignExt32to64 (Trunc64to32 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 32 // result: x for { if v_0.Op != OpTrunc64to32 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 32) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt8to16(v *Value) bool { v_0 := v.Args[0] // match: (SignExt8to16 (Const8 [c])) // result: (Const16 [int16(c)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(c)) return true } // match: (SignExt8to16 (Trunc16to8 x:(Rsh16x64 _ (Const64 [s])))) // cond: s >= 8 // result: x for { if v_0.Op != OpTrunc16to8 { break } x := v_0.Args[0] if x.Op != OpRsh16x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 8) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt8to32(v *Value) bool { v_0 := v.Args[0] // match: (SignExt8to32 (Const8 [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } // match: (SignExt8to32 (Trunc32to8 x:(Rsh32x64 _ (Const64 [s])))) // cond: s >= 24 // result: x for { if v_0.Op != OpTrunc32to8 { break } x := v_0.Args[0] if x.Op != OpRsh32x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 24) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt8to64(v *Value) bool { v_0 := v.Args[0] // match: (SignExt8to64 (Const8 [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } // match: (SignExt8to64 (Trunc64to8 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 56 // result: x for { if v_0.Op != OpTrunc64to8 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 56) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSliceCap(v *Value) bool { v_0 := v.Args[0] // match: (SliceCap (SliceMake _ _ (Const64 [c]))) // result: (Const64 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpConst64 { break } t := v_0_2.Type c := auxIntToInt64(v_0_2.AuxInt) v.reset(OpConst64) v.Type = t v.AuxInt = int64ToAuxInt(c) return true } // match: (SliceCap (SliceMake _ _ (Const32 [c]))) // result: (Const32 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpConst32 { break } t := v_0_2.Type c := auxIntToInt32(v_0_2.AuxInt) v.reset(OpConst32) v.Type = t v.AuxInt = int32ToAuxInt(c) return true } // match: (SliceCap (SliceMake _ _ (SliceCap x))) // result: (SliceCap x) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpSliceCap { break } x := v_0_2.Args[0] v.reset(OpSliceCap) v.AddArg(x) return true } // match: (SliceCap (SliceMake _ _ (SliceLen x))) // result: (SliceLen x) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpSliceLen { break } x := v_0_2.Args[0] v.reset(OpSliceLen) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSliceLen(v *Value) bool { v_0 := v.Args[0] // match: (SliceLen (SliceMake _ (Const64 [c]) _)) // result: (Const64 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type c := auxIntToInt64(v_0_1.AuxInt) v.reset(OpConst64) v.Type = t v.AuxInt = int64ToAuxInt(c) return true } // match: (SliceLen (SliceMake _ (Const32 [c]) _)) // result: (Const32 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type c := auxIntToInt32(v_0_1.AuxInt) v.reset(OpConst32) v.Type = t v.AuxInt = int32ToAuxInt(c) return true } // match: (SliceLen (SliceMake _ (SliceLen x) _)) // result: (SliceLen x) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpSliceLen { break } x := v_0_1.Args[0] v.reset(OpSliceLen) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSlicePtr(v *Value) bool { v_0 := v.Args[0] // match: (SlicePtr (SliceMake (SlicePtr x) _ _)) // result: (SlicePtr x) for { if v_0.Op != OpSliceMake { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpSlicePtr { break } x := v_0_0.Args[0] v.reset(OpSlicePtr) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSlicemask(v *Value) bool { v_0 := v.Args[0] // match: (Slicemask (Const32 [x])) // cond: x > 0 // result: (Const32 [-1]) for { if v_0.Op != OpConst32 { break } x := auxIntToInt32(v_0.AuxInt) if !(x > 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } // match: (Slicemask (Const32 [0])) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Slicemask (Const64 [x])) // cond: x > 0 // result: (Const64 [-1]) for { if v_0.Op != OpConst64 { break } x := auxIntToInt64(v_0.AuxInt) if !(x > 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } // match: (Slicemask (Const64 [0])) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpSqrt(v *Value) bool { v_0 := v.Args[0] // match: (Sqrt (Const64F [c])) // cond: !math.IsNaN(math.Sqrt(c)) // result: (Const64F [math.Sqrt(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if !(!math.IsNaN(math.Sqrt(c))) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(math.Sqrt(c)) return true } return false } func rewriteValuegeneric_OpStaticLECall(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [1]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) // result: (MakeResult (Eq8 (Load sptr mem) (Const8 [int8(read8(scon,0))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 1 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon)) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq8, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int8) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst8, typ.Int8) v2.AuxInt = int8ToAuxInt(int8(read8(scon, 0))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [2]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) // result: (MakeResult (Eq16 (Load sptr mem) (Const16 [int16(read16(scon,0,config.ctxt.Arch.ByteOrder))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 2 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config)) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq16, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int16) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst16, typ.Int16) v2.AuxInt = int16ToAuxInt(int16(read16(scon, 0, config.ctxt.Arch.ByteOrder))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [4]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) // result: (MakeResult (Eq32 (Load sptr mem) (Const32 [int32(read32(scon,0,config.ctxt.Arch.ByteOrder))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 4 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config)) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq32, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int32) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = int32ToAuxInt(int32(read32(scon, 0, config.ctxt.Arch.ByteOrder))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [8]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) && config.PtrSize == 8 // result: (MakeResult (Eq64 (Load sptr mem) (Const64 [int64(read64(scon,0,config.ctxt.Arch.ByteOrder))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 8 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) && config.PtrSize == 8) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq64, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int64) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst64, typ.Int64) v2.AuxInt = int64ToAuxInt(int64(read64(scon, 0, config.ctxt.Arch.ByteOrder))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } return false } func rewriteValuegeneric_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (Store {t1} p1 (Load p2 mem) mem) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type mem := v_1.Args[1] p2 := v_1.Args[0] if mem != v_2 || !(isSamePtr(p1, p2) && t2.Size() == t1.Size()) { break } v.copyOf(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ oldmem)) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v_2 if mem.Op != OpStore { break } t3 := auxToType(mem.Aux) _ = mem.Args[2] p3 := mem.Args[0] if oldmem != mem.Args[2] || !(isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ (Store {t4} p4 _ oldmem))) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size()) // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v_2 if mem.Op != OpStore { break } t3 := auxToType(mem.Aux) _ = mem.Args[2] p3 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t4 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p4 := mem_2.Args[0] if oldmem != mem_2.Args[2] || !(isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 _ oldmem)))) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size()) && disjoint(p1, t1.Size(), p5, t5.Size()) // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v_2 if mem.Op != OpStore { break } t3 := auxToType(mem.Aux) _ = mem.Args[2] p3 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t4 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p4 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t5 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] p5 := mem_2_2.Args[0] if oldmem != mem_2_2.Args[2] || !(isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size()) && disjoint(p1, t1.Size(), p5, t5.Size())) { break } v.copyOf(mem) return true } // match: (Store {t} (OffPtr [o] p1) x mem:(Zero [n] p2 _)) // cond: isConstZero(x) && o >= 0 && t.Size() + o <= n && isSamePtr(p1, p2) // result: mem for { t := auxToType(v.Aux) if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] x := v_1 mem := v_2 if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p2 := mem.Args[0] if !(isConstZero(x) && o >= 0 && t.Size()+o <= n && isSamePtr(p1, p2)) { break } v.copyOf(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Zero [n] p3 _))) // cond: isConstZero(x) && o1 >= 0 && t1.Size() + o1 <= n && isSamePtr(p1, p3) && disjoint(op, t1.Size(), p2, t2.Size()) // result: mem for { t1 := auxToType(v.Aux) op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] x := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpZero { break } n := auxIntToInt64(mem_2.AuxInt) p3 := mem_2.Args[0] if !(isConstZero(x) && o1 >= 0 && t1.Size()+o1 <= n && isSamePtr(p1, p3) && disjoint(op, t1.Size(), p2, t2.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Store {t3} p3 _ (Zero [n] p4 _)))) // cond: isConstZero(x) && o1 >= 0 && t1.Size() + o1 <= n && isSamePtr(p1, p4) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) // result: mem for { t1 := auxToType(v.Aux) op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] x := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p3 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpZero { break } n := auxIntToInt64(mem_2_2.AuxInt) p4 := mem_2_2.Args[0] if !(isConstZero(x) && o1 >= 0 && t1.Size()+o1 <= n && isSamePtr(p1, p4) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Zero [n] p5 _))))) // cond: isConstZero(x) && o1 >= 0 && t1.Size() + o1 <= n && isSamePtr(p1, p5) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) // result: mem for { t1 := auxToType(v.Aux) op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] x := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p3 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] p4 := mem_2_2.Args[0] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpZero { break } n := auxIntToInt64(mem_2_2_2.AuxInt) p5 := mem_2_2_2.Args[0] if !(isConstZero(x) && o1 >= 0 && t1.Size()+o1 <= n && isSamePtr(p1, p5) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size())) { break } v.copyOf(mem) return true } // match: (Store _ (StructMake0) mem) // result: mem for { if v_1.Op != OpStructMake0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Store dst (StructMake1 f0) mem) // result: (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem) for { dst := v_0 if v_1.Op != OpStructMake1 { break } t := v_1.Type f0 := v_1.Args[0] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(0)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v0.AuxInt = int64ToAuxInt(0) v0.AddArg(dst) v.AddArg3(v0, f0, mem) return true } // match: (Store dst (StructMake2 f0 f1) mem) // result: (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem)) for { dst := v_0 if v_1.Op != OpStructMake2 { break } t := v_1.Type f1 := v_1.Args[1] f0 := v_1.Args[0] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(1)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v0.AuxInt = int64ToAuxInt(t.FieldOff(1)) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t.FieldType(0)) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v2.AuxInt = int64ToAuxInt(0) v2.AddArg(dst) v1.AddArg3(v2, f0, mem) v.AddArg3(v0, f1, v1) return true } // match: (Store dst (StructMake3 f0 f1 f2) mem) // result: (Store {t.FieldType(2)} (OffPtr [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem))) for { dst := v_0 if v_1.Op != OpStructMake3 { break } t := v_1.Type f2 := v_1.Args[2] f0 := v_1.Args[0] f1 := v_1.Args[1] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(2)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v0.AuxInt = int64ToAuxInt(t.FieldOff(2)) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t.FieldType(1)) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v2.AuxInt = int64ToAuxInt(t.FieldOff(1)) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t.FieldType(0)) v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v4.AuxInt = int64ToAuxInt(0) v4.AddArg(dst) v3.AddArg3(v4, f0, mem) v1.AddArg3(v2, f1, v3) v.AddArg3(v0, f2, v1) return true } // match: (Store dst (StructMake4 f0 f1 f2 f3) mem) // result: (Store {t.FieldType(3)} (OffPtr [t.FieldOff(3)] dst) f3 (Store {t.FieldType(2)} (OffPtr [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem)))) for { dst := v_0 if v_1.Op != OpStructMake4 { break } t := v_1.Type f3 := v_1.Args[3] f0 := v_1.Args[0] f1 := v_1.Args[1] f2 := v_1.Args[2] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(3)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo()) v0.AuxInt = int64ToAuxInt(t.FieldOff(3)) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t.FieldType(2)) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v2.AuxInt = int64ToAuxInt(t.FieldOff(2)) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t.FieldType(1)) v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v4.AuxInt = int64ToAuxInt(t.FieldOff(1)) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t.FieldType(0)) v6 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v6.AuxInt = int64ToAuxInt(0) v6.AddArg(dst) v5.AddArg3(v6, f0, mem) v3.AddArg3(v4, f1, v5) v1.AddArg3(v2, f2, v3) v.AddArg3(v0, f3, v1) return true } // match: (Store {t} dst (Load src mem) mem) // cond: !fe.CanSSA(t) // result: (Move {t} [t.Size()] dst src mem) for { t := auxToType(v.Aux) dst := v_0 if v_1.Op != OpLoad { break } mem := v_1.Args[1] src := v_1.Args[0] if mem != v_2 || !(!fe.CanSSA(t)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(t.Size()) v.Aux = typeToAux(t) v.AddArg3(dst, src, mem) return true } // match: (Store {t} dst (Load src mem) (VarDef {x} mem)) // cond: !fe.CanSSA(t) // result: (Move {t} [t.Size()] dst src (VarDef {x} mem)) for { t := auxToType(v.Aux) dst := v_0 if v_1.Op != OpLoad { break } mem := v_1.Args[1] src := v_1.Args[0] if v_2.Op != OpVarDef { break } x := auxToSym(v_2.Aux) if mem != v_2.Args[0] || !(!fe.CanSSA(t)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(t.Size()) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg3(dst, src, v0) return true } // match: (Store _ (ArrayMake0) mem) // result: mem for { if v_1.Op != OpArrayMake0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Store dst (ArrayMake1 e) mem) // result: (Store {e.Type} dst e mem) for { dst := v_0 if v_1.Op != OpArrayMake1 { break } e := v_1.Args[0] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(e.Type) v.AddArg3(dst, e, mem) return true } // match: (Store (SelectN [0] call:(StaticLECall _ _)) x mem:(SelectN [1] call)) // cond: isConstZero(x) && isSameCall(call.Aux, "runtime.newobject") // result: mem for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { break } call := v_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 { break } x := v_1 mem := v_2 if mem.Op != OpSelectN || auxIntToInt64(mem.AuxInt) != 1 || call != mem.Args[0] || !(isConstZero(x) && isSameCall(call.Aux, "runtime.newobject")) { break } v.copyOf(mem) return true } // match: (Store (OffPtr (SelectN [0] call:(StaticLECall _ _))) x mem:(SelectN [1] call)) // cond: isConstZero(x) && isSameCall(call.Aux, "runtime.newobject") // result: mem for { if v_0.Op != OpOffPtr { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpSelectN || auxIntToInt64(v_0_0.AuxInt) != 0 { break } call := v_0_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 { break } x := v_1 mem := v_2 if mem.Op != OpSelectN || auxIntToInt64(mem.AuxInt) != 1 || call != mem.Args[0] || !(isConstZero(x) && isSameCall(call.Aux, "runtime.newobject")) { break } v.copyOf(mem) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [0] p2) d2 m3:(Move [n] p3 _ mem))) // cond: m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 mem)) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr || auxIntToInt64(op2.AuxInt) != 0 { break } p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpMove { break } n := auxIntToInt64(m3.AuxInt) mem := m3.Args[2] p3 := m3.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v0.AddArg3(op2, d2, mem) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Move [n] p4 _ mem)))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 mem))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr || auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpMove { break } n := auxIntToInt64(m4.AuxInt) mem := m4.Args[2] p4 := m4.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v1.AddArg3(op3, d3, mem) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Move [n] p5 _ mem))))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size() + t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 (Store {t4} op4 d4 mem)))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpStore { break } t4 := auxToType(m4.Aux) _ = m4.Args[2] op4 := m4.Args[0] if op4.Op != OpOffPtr || auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] d4 := m4.Args[1] m5 := m4.Args[2] if m5.Op != OpMove { break } n := auxIntToInt64(m5.AuxInt) mem := m5.Args[2] p5 := m5.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size()+t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v2.Aux = typeToAux(t4) v2.AddArg3(op4, d4, mem) v1.AddArg3(op3, d3, v2) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [0] p2) d2 m3:(Zero [n] p3 mem))) // cond: m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 mem)) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr || auxIntToInt64(op2.AuxInt) != 0 { break } p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpZero { break } n := auxIntToInt64(m3.AuxInt) mem := m3.Args[1] p3 := m3.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v0.AddArg3(op2, d2, mem) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Zero [n] p4 mem)))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 mem))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr || auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpZero { break } n := auxIntToInt64(m4.AuxInt) mem := m4.Args[1] p4 := m4.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v1.AddArg3(op3, d3, mem) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Zero [n] p5 mem))))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size() + t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 (Store {t4} op4 d4 mem)))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpStore { break } t4 := auxToType(m4.Aux) _ = m4.Args[2] op4 := m4.Args[0] if op4.Op != OpOffPtr || auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] d4 := m4.Args[1] m5 := m4.Args[2] if m5.Op != OpZero { break } n := auxIntToInt64(m5.AuxInt) mem := m5.Args[1] p5 := m5.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size()+t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v2.Aux = typeToAux(t4) v2.AddArg3(op4, d4, mem) v1.AddArg3(op3, d3, v2) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } return false } func rewriteValuegeneric_OpStringLen(v *Value) bool { v_0 := v.Args[0] // match: (StringLen (StringMake _ (Const64 [c]))) // result: (Const64 [c]) for { if v_0.Op != OpStringMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type c := auxIntToInt64(v_0_1.AuxInt) v.reset(OpConst64) v.Type = t v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValuegeneric_OpStringPtr(v *Value) bool { v_0 := v.Args[0] // match: (StringPtr (StringMake (Addr {s} base) _)) // result: (Addr {s} base) for { if v_0.Op != OpStringMake { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { break } t := v_0_0.Type s := auxToSym(v_0_0.Aux) base := v_0_0.Args[0] v.reset(OpAddr) v.Type = t v.Aux = symToAux(s) v.AddArg(base) return true } return false } func rewriteValuegeneric_OpStructSelect(v *Value) bool { v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (StructSelect (StructMake1 x)) // result: x for { if v_0.Op != OpStructMake1 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [0] (StructMake2 x _)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpStructMake2 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [1] (StructMake2 _ x)) // result: x for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStructMake2 { break } x := v_0.Args[1] v.copyOf(x) return true } // match: (StructSelect [0] (StructMake3 x _ _)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpStructMake3 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [1] (StructMake3 _ x _)) // result: x for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStructMake3 { break } x := v_0.Args[1] v.copyOf(x) return true } // match: (StructSelect [2] (StructMake3 _ _ x)) // result: x for { if auxIntToInt64(v.AuxInt) != 2 || v_0.Op != OpStructMake3 { break } x := v_0.Args[2] v.copyOf(x) return true } // match: (StructSelect [0] (StructMake4 x _ _ _)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpStructMake4 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [1] (StructMake4 _ x _ _)) // result: x for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStructMake4 { break } x := v_0.Args[1] v.copyOf(x) return true } // match: (StructSelect [2] (StructMake4 _ _ x _)) // result: x for { if auxIntToInt64(v.AuxInt) != 2 || v_0.Op != OpStructMake4 { break } x := v_0.Args[2] v.copyOf(x) return true } // match: (StructSelect [3] (StructMake4 _ _ _ x)) // result: x for { if auxIntToInt64(v.AuxInt) != 3 || v_0.Op != OpStructMake4 { break } x := v_0.Args[3] v.copyOf(x) return true } // match: (StructSelect [i] x:(Load ptr mem)) // cond: !fe.CanSSA(t) // result: @x.Block (Load (OffPtr [t.FieldOff(int(i))] ptr) mem) for { i := auxIntToInt64(v.AuxInt) x := v_0 if x.Op != OpLoad { break } t := x.Type mem := x.Args[1] ptr := x.Args[0] if !(!fe.CanSSA(t)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpLoad, v.Type) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, v.Type.PtrTo()) v1.AuxInt = int64ToAuxInt(t.FieldOff(int(i))) v1.AddArg(ptr) v0.AddArg2(v1, mem) return true } // match: (StructSelect [0] (IData x)) // result: (IData x) for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpIData { break } x := v_0.Args[0] v.reset(OpIData) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c-d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c - d) return true } // match: (Sub16 x (Const16 [c])) // cond: x.Op != OpConst16 // result: (Add16 (Const16 [-c]) x) for { x := v_0 if v_1.Op != OpConst16 { break } t := v_1.Type c := auxIntToInt16(v_1.AuxInt) if !(x.Op != OpConst16) { break } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub16 (Mul16 x y) (Mul16 x z)) // result: (Mul16 x (Sub16 y z)) for { t := v.Type if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub16 x x) // result: (Const16 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Sub16 (Neg16 x) (Com16 x)) // result: (Const16 [1]) for { if v_0.Op != OpNeg16 { break } x := v_0.Args[0] if v_1.Op != OpCom16 || x != v_1.Args[0] { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(1) return true } // match: (Sub16 (Com16 x) (Neg16 x)) // result: (Const16 [-1]) for { if v_0.Op != OpCom16 { break } x := v_0.Args[0] if v_1.Op != OpNeg16 || x != v_1.Args[0] { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } // match: (Sub16 (Add16 x y) x) // result: y for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub16 (Add16 x y) y) // result: x for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub16 (Sub16 x y) x) // result: (Neg16 y) for { if v_0.Op != OpSub16 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg16) v.AddArg(y) return true } // match: (Sub16 x (Add16 x y)) // result: (Neg16 y) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg16) v.AddArg(y) return true } break } // match: (Sub16 x (Sub16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { x := v_0 if v_1.Op != OpSub16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub16 x (Add16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Sub16 x z) i) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst16 { continue } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub16 (Sub16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 i (Add16 z x)) for { if v_0.Op != OpSub16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub16 (Add16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 z x)) for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst16 { continue } t := i.Type x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub16 (Const16 [c]) (Sub16 (Const16 [d]) x)) // result: (Add16 (Const16 [c-d]) x) for { if v_0.Op != OpConst16 { break } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpSub16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 || v_1_0.Type != t { break } d := auxIntToInt16(v_1_0.AuxInt) v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Sub16 (Const16 [c-d]) x) for { if v_0.Op != OpConst16 { break } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpSub32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c-d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c - d) return true } // match: (Sub32 x (Const32 [c])) // cond: x.Op != OpConst32 // result: (Add32 (Const32 [-c]) x) for { x := v_0 if v_1.Op != OpConst32 { break } t := v_1.Type c := auxIntToInt32(v_1.AuxInt) if !(x.Op != OpConst32) { break } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub32 (Mul32 x y) (Mul32 x z)) // result: (Mul32 x (Sub32 y z)) for { t := v.Type if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub32 x x) // result: (Const32 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Sub32 (Neg32 x) (Com32 x)) // result: (Const32 [1]) for { if v_0.Op != OpNeg32 { break } x := v_0.Args[0] if v_1.Op != OpCom32 || x != v_1.Args[0] { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(1) return true } // match: (Sub32 (Com32 x) (Neg32 x)) // result: (Const32 [-1]) for { if v_0.Op != OpCom32 { break } x := v_0.Args[0] if v_1.Op != OpNeg32 || x != v_1.Args[0] { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } // match: (Sub32 (Add32 x y) x) // result: y for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub32 (Add32 x y) y) // result: x for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub32 (Sub32 x y) x) // result: (Neg32 y) for { if v_0.Op != OpSub32 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg32) v.AddArg(y) return true } // match: (Sub32 x (Add32 x y)) // result: (Neg32 y) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg32) v.AddArg(y) return true } break } // match: (Sub32 x (Sub32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { x := v_0 if v_1.Op != OpSub32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub32 x (Add32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Sub32 x z) i) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst32 { continue } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub32 (Sub32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 i (Add32 z x)) for { if v_0.Op != OpSub32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub32 (Add32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 z x)) for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst32 { continue } t := i.Type x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub32 (Const32 [c]) (Sub32 (Const32 [d]) x)) // result: (Add32 (Const32 [c-d]) x) for { if v_0.Op != OpConst32 { break } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpSub32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 || v_1_0.Type != t { break } d := auxIntToInt32(v_1_0.AuxInt) v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Sub32 (Const32 [c-d]) x) for { if v_0.Op != OpConst32 { break } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpSub32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Sub32F (Const32F [c]) (Const32F [d])) // cond: c-d == c-d // result: (Const32F [c-d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) if !(c-d == c-d) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c - d) return true } return false } func rewriteValuegeneric_OpSub64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c-d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c - d) return true } // match: (Sub64 x (Const64 [c])) // cond: x.Op != OpConst64 // result: (Add64 (Const64 [-c]) x) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(x.Op != OpConst64) { break } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub64 (Mul64 x y) (Mul64 x z)) // result: (Mul64 x (Sub64 y z)) for { t := v.Type if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub64 x x) // result: (Const64 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Sub64 (Neg64 x) (Com64 x)) // result: (Const64 [1]) for { if v_0.Op != OpNeg64 { break } x := v_0.Args[0] if v_1.Op != OpCom64 || x != v_1.Args[0] { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(1) return true } // match: (Sub64 (Com64 x) (Neg64 x)) // result: (Const64 [-1]) for { if v_0.Op != OpCom64 { break } x := v_0.Args[0] if v_1.Op != OpNeg64 || x != v_1.Args[0] { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } // match: (Sub64 (Add64 x y) x) // result: y for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub64 (Add64 x y) y) // result: x for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub64 (Sub64 x y) x) // result: (Neg64 y) for { if v_0.Op != OpSub64 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg64) v.AddArg(y) return true } // match: (Sub64 x (Add64 x y)) // result: (Neg64 y) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg64) v.AddArg(y) return true } break } // match: (Sub64 x (Sub64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { x := v_0 if v_1.Op != OpSub64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub64 x (Add64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Sub64 x z) i) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst64 { continue } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub64 (Sub64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 i (Add64 z x)) for { if v_0.Op != OpSub64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub64 (Add64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 z x)) for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst64 { continue } t := i.Type x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub64 (Const64 [c]) (Sub64 (Const64 [d]) x)) // result: (Add64 (Const64 [c-d]) x) for { if v_0.Op != OpConst64 { break } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpSub64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 || v_1_0.Type != t { break } d := auxIntToInt64(v_1_0.AuxInt) v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Sub64 (Const64 [c-d]) x) for { if v_0.Op != OpConst64 { break } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpSub64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Sub64F (Const64F [c]) (Const64F [d])) // cond: c-d == c-d // result: (Const64F [c-d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) if !(c-d == c-d) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c - d) return true } return false } func rewriteValuegeneric_OpSub8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c-d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c - d) return true } // match: (Sub8 x (Const8 [c])) // cond: x.Op != OpConst8 // result: (Add8 (Const8 [-c]) x) for { x := v_0 if v_1.Op != OpConst8 { break } t := v_1.Type c := auxIntToInt8(v_1.AuxInt) if !(x.Op != OpConst8) { break } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub8 (Mul8 x y) (Mul8 x z)) // result: (Mul8 x (Sub8 y z)) for { t := v.Type if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub8 x x) // result: (Const8 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Sub8 (Neg8 x) (Com8 x)) // result: (Const8 [1]) for { if v_0.Op != OpNeg8 { break } x := v_0.Args[0] if v_1.Op != OpCom8 || x != v_1.Args[0] { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(1) return true } // match: (Sub8 (Com8 x) (Neg8 x)) // result: (Const8 [-1]) for { if v_0.Op != OpCom8 { break } x := v_0.Args[0] if v_1.Op != OpNeg8 || x != v_1.Args[0] { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } // match: (Sub8 (Add8 x y) x) // result: y for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub8 (Add8 x y) y) // result: x for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub8 (Sub8 x y) x) // result: (Neg8 y) for { if v_0.Op != OpSub8 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg8) v.AddArg(y) return true } // match: (Sub8 x (Add8 x y)) // result: (Neg8 y) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg8) v.AddArg(y) return true } break } // match: (Sub8 x (Sub8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { x := v_0 if v_1.Op != OpSub8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub8 x (Add8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Sub8 x z) i) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst8 { continue } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub8 (Sub8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 i (Add8 z x)) for { if v_0.Op != OpSub8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub8 (Add8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 z x)) for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst8 { continue } t := i.Type x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub8 (Const8 [c]) (Sub8 (Const8 [d]) x)) // result: (Add8 (Const8 [c-d]) x) for { if v_0.Op != OpConst8 { break } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpSub8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 || v_1_0.Type != t { break } d := auxIntToInt8(v_1_0.AuxInt) v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Sub8 (Const8 [c-d]) x) for { if v_0.Op != OpConst8 { break } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpTrunc16to8(v *Value) bool { v_0 := v.Args[0] // match: (Trunc16to8 (Const16 [c])) // result: (Const8 [int8(c)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(c)) return true } // match: (Trunc16to8 (ZeroExt8to16 x)) // result: x for { if v_0.Op != OpZeroExt8to16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc16to8 (SignExt8to16 x)) // result: x for { if v_0.Op != OpSignExt8to16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc16to8 (And16 (Const16 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc16to8 x) for { if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst16 { continue } y := auxIntToInt16(v_0_0.AuxInt) x := v_0_1 if !(y&0xFF == 0xFF) { continue } v.reset(OpTrunc16to8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc32to16(v *Value) bool { v_0 := v.Args[0] // match: (Trunc32to16 (Const32 [c])) // result: (Const16 [int16(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(c)) return true } // match: (Trunc32to16 (ZeroExt8to32 x)) // result: (ZeroExt8to16 x) for { if v_0.Op != OpZeroExt8to32 { break } x := v_0.Args[0] v.reset(OpZeroExt8to16) v.AddArg(x) return true } // match: (Trunc32to16 (ZeroExt16to32 x)) // result: x for { if v_0.Op != OpZeroExt16to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to16 (SignExt8to32 x)) // result: (SignExt8to16 x) for { if v_0.Op != OpSignExt8to32 { break } x := v_0.Args[0] v.reset(OpSignExt8to16) v.AddArg(x) return true } // match: (Trunc32to16 (SignExt16to32 x)) // result: x for { if v_0.Op != OpSignExt16to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to16 (And32 (Const32 [y]) x)) // cond: y&0xFFFF == 0xFFFF // result: (Trunc32to16 x) for { if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 { continue } y := auxIntToInt32(v_0_0.AuxInt) x := v_0_1 if !(y&0xFFFF == 0xFFFF) { continue } v.reset(OpTrunc32to16) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc32to8(v *Value) bool { v_0 := v.Args[0] // match: (Trunc32to8 (Const32 [c])) // result: (Const8 [int8(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(c)) return true } // match: (Trunc32to8 (ZeroExt8to32 x)) // result: x for { if v_0.Op != OpZeroExt8to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to8 (SignExt8to32 x)) // result: x for { if v_0.Op != OpSignExt8to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to8 (And32 (Const32 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc32to8 x) for { if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 { continue } y := auxIntToInt32(v_0_0.AuxInt) x := v_0_1 if !(y&0xFF == 0xFF) { continue } v.reset(OpTrunc32to8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc64to16(v *Value) bool { v_0 := v.Args[0] // match: (Trunc64to16 (Const64 [c])) // result: (Const16 [int16(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(c)) return true } // match: (Trunc64to16 (ZeroExt8to64 x)) // result: (ZeroExt8to16 x) for { if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpZeroExt8to16) v.AddArg(x) return true } // match: (Trunc64to16 (ZeroExt16to64 x)) // result: x for { if v_0.Op != OpZeroExt16to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to16 (SignExt8to64 x)) // result: (SignExt8to16 x) for { if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpSignExt8to16) v.AddArg(x) return true } // match: (Trunc64to16 (SignExt16to64 x)) // result: x for { if v_0.Op != OpSignExt16to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to16 (And64 (Const64 [y]) x)) // cond: y&0xFFFF == 0xFFFF // result: (Trunc64to16 x) for { if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } y := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(y&0xFFFF == 0xFFFF) { continue } v.reset(OpTrunc64to16) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc64to32(v *Value) bool { v_0 := v.Args[0] // match: (Trunc64to32 (Const64 [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } // match: (Trunc64to32 (ZeroExt8to64 x)) // result: (ZeroExt8to32 x) for { if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpZeroExt8to32) v.AddArg(x) return true } // match: (Trunc64to32 (ZeroExt16to64 x)) // result: (ZeroExt16to32 x) for { if v_0.Op != OpZeroExt16to64 { break } x := v_0.Args[0] v.reset(OpZeroExt16to32) v.AddArg(x) return true } // match: (Trunc64to32 (ZeroExt32to64 x)) // result: x for { if v_0.Op != OpZeroExt32to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to32 (SignExt8to64 x)) // result: (SignExt8to32 x) for { if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpSignExt8to32) v.AddArg(x) return true } // match: (Trunc64to32 (SignExt16to64 x)) // result: (SignExt16to32 x) for { if v_0.Op != OpSignExt16to64 { break } x := v_0.Args[0] v.reset(OpSignExt16to32) v.AddArg(x) return true } // match: (Trunc64to32 (SignExt32to64 x)) // result: x for { if v_0.Op != OpSignExt32to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to32 (And64 (Const64 [y]) x)) // cond: y&0xFFFFFFFF == 0xFFFFFFFF // result: (Trunc64to32 x) for { if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } y := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(y&0xFFFFFFFF == 0xFFFFFFFF) { continue } v.reset(OpTrunc64to32) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc64to8(v *Value) bool { v_0 := v.Args[0] // match: (Trunc64to8 (Const64 [c])) // result: (Const8 [int8(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(c)) return true } // match: (Trunc64to8 (ZeroExt8to64 x)) // result: x for { if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to8 (SignExt8to64 x)) // result: x for { if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to8 (And64 (Const64 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc64to8 x) for { if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } y := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(y&0xFF == 0xFF) { continue } v.reset(OpTrunc64to8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpXor16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Xor16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c ^ d) return true } break } // match: (Xor16 x x) // result: (Const16 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Xor16 (Const16 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor16 (Com16 x) x) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Xor16 (Const16 [-1]) x) // result: (Com16 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom16) v.AddArg(x) return true } break } // match: (Xor16 x (Xor16 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor16 (Xor16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Xor16 i (Xor16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpXor16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor16 (Const16 [c]) (Xor16 (Const16 [d]) x)) // result: (Xor16 (Const16 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpXor16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpXor32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Xor32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c ^ d) return true } break } // match: (Xor32 x x) // result: (Const32 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Xor32 (Const32 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor32 (Com32 x) x) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Xor32 (Const32 [-1]) x) // result: (Com32 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom32) v.AddArg(x) return true } break } // match: (Xor32 x (Xor32 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor32 (Xor32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Xor32 i (Xor32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpXor32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor32 (Const32 [c]) (Xor32 (Const32 [d]) x)) // result: (Xor32 (Const32 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpXor32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpXor64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Xor64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c ^ d) return true } break } // match: (Xor64 x x) // result: (Const64 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Xor64 (Const64 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor64 (Com64 x) x) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Xor64 (Const64 [-1]) x) // result: (Com64 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom64) v.AddArg(x) return true } break } // match: (Xor64 x (Xor64 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor64 (Xor64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Xor64 i (Xor64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpXor64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor64 (Const64 [c]) (Xor64 (Const64 [d]) x)) // result: (Xor64 (Const64 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpXor64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpXor8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Xor8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c ^ d) return true } break } // match: (Xor8 x x) // result: (Const8 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Xor8 (Const8 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor8 (Com8 x) x) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Xor8 (Const8 [-1]) x) // result: (Com8 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom8) v.AddArg(x) return true } break } // match: (Xor8 x (Xor8 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor8 (Xor8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Xor8 i (Xor8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpXor8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor8 (Const8 [c]) (Xor8 (Const8 [d]) x)) // result: (Xor8 (Const8 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpXor8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Zero (SelectN [0] call:(StaticLECall _ _)) mem:(SelectN [1] call)) // cond: isSameCall(call.Aux, "runtime.newobject") // result: mem for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { break } call := v_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 { break } mem := v_1 if mem.Op != OpSelectN || auxIntToInt64(mem.AuxInt) != 1 || call != mem.Args[0] || !(isSameCall(call.Aux, "runtime.newobject")) { break } v.copyOf(mem) return true } // match: (Zero {t1} [n] p1 store:(Store {t2} (OffPtr [o2] p2) _ mem)) // cond: isSamePtr(p1, p2) && store.Uses == 1 && n >= o2 + t2.Size() && clobber(store) // result: (Zero {t1} [n] p1 mem) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) p1 := v_0 store := v_1 if store.Op != OpStore { break } t2 := auxToType(store.Aux) mem := store.Args[2] store_0 := store.Args[0] if store_0.Op != OpOffPtr { break } o2 := auxIntToInt64(store_0.AuxInt) p2 := store_0.Args[0] if !(isSamePtr(p1, p2) && store.Uses == 1 && n >= o2+t2.Size() && clobber(store)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t1) v.AddArg2(p1, mem) return true } // match: (Zero {t} [n] dst1 move:(Move {t} [n] dst2 _ mem)) // cond: move.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move) // result: (Zero {t} [n] dst1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 move := v_1 if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst1, mem) return true } // match: (Zero {t} [n] dst1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem))) // cond: move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move, vardef) // result: (Zero {t} [n] dst1 (VarDef {x} mem)) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 vardef := v_1 if vardef.Op != OpVarDef { break } x := auxToSym(vardef.Aux) move := vardef.Args[0] if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move, vardef)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg2(dst1, v0) return true } // match: (Zero {t} [s] dst1 zero:(Zero {t} [s] dst2 _)) // cond: isSamePtr(dst1, dst2) // result: zero for { s := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 zero := v_1 if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != s || auxToType(zero.Aux) != t { break } dst2 := zero.Args[0] if !(isSamePtr(dst1, dst2)) { break } v.copyOf(zero) return true } // match: (Zero {t} [s] dst1 vardef:(VarDef (Zero {t} [s] dst2 _))) // cond: isSamePtr(dst1, dst2) // result: vardef for { s := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 vardef := v_1 if vardef.Op != OpVarDef { break } vardef_0 := vardef.Args[0] if vardef_0.Op != OpZero || auxIntToInt64(vardef_0.AuxInt) != s || auxToType(vardef_0.Aux) != t { break } dst2 := vardef_0.Args[0] if !(isSamePtr(dst1, dst2)) { break } v.copyOf(vardef) return true } return false } func rewriteValuegeneric_OpZeroExt16to32(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt16to32 (Const16 [c])) // result: (Const32 [int32(uint16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint16(c))) return true } // match: (ZeroExt16to32 (Trunc32to16 x:(Rsh32Ux64 _ (Const64 [s])))) // cond: s >= 16 // result: x for { if v_0.Op != OpTrunc32to16 { break } x := v_0.Args[0] if x.Op != OpRsh32Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 16) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt16to64(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt16to64 (Const16 [c])) // result: (Const64 [int64(uint16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint16(c))) return true } // match: (ZeroExt16to64 (Trunc64to16 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 48 // result: x for { if v_0.Op != OpTrunc64to16 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 48) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt32to64(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt32to64 (Const32 [c])) // result: (Const64 [int64(uint32(c))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint32(c))) return true } // match: (ZeroExt32to64 (Trunc64to32 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 32 // result: x for { if v_0.Op != OpTrunc64to32 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 32) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to16(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt8to16 (Const8 [c])) // result: (Const16 [int16( uint8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint8(c))) return true } // match: (ZeroExt8to16 (Trunc16to8 x:(Rsh16Ux64 _ (Const64 [s])))) // cond: s >= 8 // result: x for { if v_0.Op != OpTrunc16to8 { break } x := v_0.Args[0] if x.Op != OpRsh16Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 8) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to32(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt8to32 (Const8 [c])) // result: (Const32 [int32( uint8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint8(c))) return true } // match: (ZeroExt8to32 (Trunc32to8 x:(Rsh32Ux64 _ (Const64 [s])))) // cond: s >= 24 // result: x for { if v_0.Op != OpTrunc32to8 { break } x := v_0.Args[0] if x.Op != OpRsh32Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 24) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to64(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt8to64 (Const8 [c])) // result: (Const64 [int64( uint8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint8(c))) return true } // match: (ZeroExt8to64 (Trunc64to8 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 56 // result: x for { if v_0.Op != OpTrunc64to8 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 56) { break } v.copyOf(x) return true } return false } func rewriteBlockgeneric(b *Block) bool { switch b.Kind { case BlockIf: // match: (If (Not cond) yes no) // result: (If cond no yes) for b.Controls[0].Op == OpNot { v_0 := b.Controls[0] cond := v_0.Args[0] b.resetWithControl(BlockIf, cond) b.swapSuccessors() return true } // match: (If (ConstBool [c]) yes no) // cond: c // result: (First yes no) for b.Controls[0].Op == OpConstBool { v_0 := b.Controls[0] c := auxIntToBool(v_0.AuxInt) if !(c) { break } b.Reset(BlockFirst) return true } // match: (If (ConstBool [c]) yes no) // cond: !c // result: (First no yes) for b.Controls[0].Op == OpConstBool { v_0 := b.Controls[0] c := auxIntToBool(v_0.AuxInt) if !(!c) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- y -- // Code generated from gen/generic.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/compile/internal/types" func rewriteValuegeneric(v *Value) bool { switch v.Op { case OpAdd16: return rewriteValuegeneric_OpAdd16(v) case OpAdd32: return rewriteValuegeneric_OpAdd32(v) case OpAdd32F: return rewriteValuegeneric_OpAdd32F(v) case OpAdd64: return rewriteValuegeneric_OpAdd64(v) case OpAdd64F: return rewriteValuegeneric_OpAdd64F(v) case OpAdd8: return rewriteValuegeneric_OpAdd8(v) case OpAddPtr: return rewriteValuegeneric_OpAddPtr(v) case OpAnd16: return rewriteValuegeneric_OpAnd16(v) case OpAnd32: return rewriteValuegeneric_OpAnd32(v) case OpAnd64: return rewriteValuegeneric_OpAnd64(v) case OpAnd8: return rewriteValuegeneric_OpAnd8(v) case OpAndB: return rewriteValuegeneric_OpAndB(v) case OpArraySelect: return rewriteValuegeneric_OpArraySelect(v) case OpCom16: return rewriteValuegeneric_OpCom16(v) case OpCom32: return rewriteValuegeneric_OpCom32(v) case OpCom64: return rewriteValuegeneric_OpCom64(v) case OpCom8: return rewriteValuegeneric_OpCom8(v) case OpConstInterface: return rewriteValuegeneric_OpConstInterface(v) case OpConstSlice: return rewriteValuegeneric_OpConstSlice(v) case OpConstString: return rewriteValuegeneric_OpConstString(v) case OpConvert: return rewriteValuegeneric_OpConvert(v) case OpCtz16: return rewriteValuegeneric_OpCtz16(v) case OpCtz32: return rewriteValuegeneric_OpCtz32(v) case OpCtz64: return rewriteValuegeneric_OpCtz64(v) case OpCtz8: return rewriteValuegeneric_OpCtz8(v) case OpCvt32Fto32: return rewriteValuegeneric_OpCvt32Fto32(v) case OpCvt32Fto64: return rewriteValuegeneric_OpCvt32Fto64(v) case OpCvt32Fto64F: return rewriteValuegeneric_OpCvt32Fto64F(v) case OpCvt32to32F: return rewriteValuegeneric_OpCvt32to32F(v) case OpCvt32to64F: return rewriteValuegeneric_OpCvt32to64F(v) case OpCvt64Fto32: return rewriteValuegeneric_OpCvt64Fto32(v) case OpCvt64Fto32F: return rewriteValuegeneric_OpCvt64Fto32F(v) case OpCvt64Fto64: return rewriteValuegeneric_OpCvt64Fto64(v) case OpCvt64to32F: return rewriteValuegeneric_OpCvt64to32F(v) case OpCvt64to64F: return rewriteValuegeneric_OpCvt64to64F(v) case OpCvtBoolToUint8: return rewriteValuegeneric_OpCvtBoolToUint8(v) case OpDiv16: return rewriteValuegeneric_OpDiv16(v) case OpDiv16u: return rewriteValuegeneric_OpDiv16u(v) case OpDiv32: return rewriteValuegeneric_OpDiv32(v) case OpDiv32F: return rewriteValuegeneric_OpDiv32F(v) case OpDiv32u: return rewriteValuegeneric_OpDiv32u(v) case OpDiv64: return rewriteValuegeneric_OpDiv64(v) case OpDiv64F: return rewriteValuegeneric_OpDiv64F(v) case OpDiv64u: return rewriteValuegeneric_OpDiv64u(v) case OpDiv8: return rewriteValuegeneric_OpDiv8(v) case OpDiv8u: return rewriteValuegeneric_OpDiv8u(v) case OpEq16: return rewriteValuegeneric_OpEq16(v) case OpEq32: return rewriteValuegeneric_OpEq32(v) case OpEq32F: return rewriteValuegeneric_OpEq32F(v) case OpEq64: return rewriteValuegeneric_OpEq64(v) case OpEq64F: return rewriteValuegeneric_OpEq64F(v) case OpEq8: return rewriteValuegeneric_OpEq8(v) case OpEqB: return rewriteValuegeneric_OpEqB(v) case OpEqInter: return rewriteValuegeneric_OpEqInter(v) case OpEqPtr: return rewriteValuegeneric_OpEqPtr(v) case OpEqSlice: return rewriteValuegeneric_OpEqSlice(v) case OpIMake: return rewriteValuegeneric_OpIMake(v) case OpInterLECall: return rewriteValuegeneric_OpInterLECall(v) case OpIsInBounds: return rewriteValuegeneric_OpIsInBounds(v) case OpIsNonNil: return rewriteValuegeneric_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValuegeneric_OpIsSliceInBounds(v) case OpLeq16: return rewriteValuegeneric_OpLeq16(v) case OpLeq16U: return rewriteValuegeneric_OpLeq16U(v) case OpLeq32: return rewriteValuegeneric_OpLeq32(v) case OpLeq32F: return rewriteValuegeneric_OpLeq32F(v) case OpLeq32U: return rewriteValuegeneric_OpLeq32U(v) case OpLeq64: return rewriteValuegeneric_OpLeq64(v) case OpLeq64F: return rewriteValuegeneric_OpLeq64F(v) case OpLeq64U: return rewriteValuegeneric_OpLeq64U(v) case OpLeq8: return rewriteValuegeneric_OpLeq8(v) case OpLeq8U: return rewriteValuegeneric_OpLeq8U(v) case OpLess16: return rewriteValuegeneric_OpLess16(v) case OpLess16U: return rewriteValuegeneric_OpLess16U(v) case OpLess32: return rewriteValuegeneric_OpLess32(v) case OpLess32F: return rewriteValuegeneric_OpLess32F(v) case OpLess32U: return rewriteValuegeneric_OpLess32U(v) case OpLess64: return rewriteValuegeneric_OpLess64(v) case OpLess64F: return rewriteValuegeneric_OpLess64F(v) case OpLess64U: return rewriteValuegeneric_OpLess64U(v) case OpLess8: return rewriteValuegeneric_OpLess8(v) case OpLess8U: return rewriteValuegeneric_OpLess8U(v) case OpLoad: return rewriteValuegeneric_OpLoad(v) case OpLsh16x16: return rewriteValuegeneric_OpLsh16x16(v) case OpLsh16x32: return rewriteValuegeneric_OpLsh16x32(v) case OpLsh16x64: return rewriteValuegeneric_OpLsh16x64(v) case OpLsh16x8: return rewriteValuegeneric_OpLsh16x8(v) case OpLsh32x16: return rewriteValuegeneric_OpLsh32x16(v) case OpLsh32x32: return rewriteValuegeneric_OpLsh32x32(v) case OpLsh32x64: return rewriteValuegeneric_OpLsh32x64(v) case OpLsh32x8: return rewriteValuegeneric_OpLsh32x8(v) case OpLsh64x16: return rewriteValuegeneric_OpLsh64x16(v) case OpLsh64x32: return rewriteValuegeneric_OpLsh64x32(v) case OpLsh64x64: return rewriteValuegeneric_OpLsh64x64(v) case OpLsh64x8: return rewriteValuegeneric_OpLsh64x8(v) case OpLsh8x16: return rewriteValuegeneric_OpLsh8x16(v) case OpLsh8x32: return rewriteValuegeneric_OpLsh8x32(v) case OpLsh8x64: return rewriteValuegeneric_OpLsh8x64(v) case OpLsh8x8: return rewriteValuegeneric_OpLsh8x8(v) case OpMod16: return rewriteValuegeneric_OpMod16(v) case OpMod16u: return rewriteValuegeneric_OpMod16u(v) case OpMod32: return rewriteValuegeneric_OpMod32(v) case OpMod32u: return rewriteValuegeneric_OpMod32u(v) case OpMod64: return rewriteValuegeneric_OpMod64(v) case OpMod64u: return rewriteValuegeneric_OpMod64u(v) case OpMod8: return rewriteValuegeneric_OpMod8(v) case OpMod8u: return rewriteValuegeneric_OpMod8u(v) case OpMove: return rewriteValuegeneric_OpMove(v) case OpMul16: return rewriteValuegeneric_OpMul16(v) case OpMul32: return rewriteValuegeneric_OpMul32(v) case OpMul32F: return rewriteValuegeneric_OpMul32F(v) case OpMul64: return rewriteValuegeneric_OpMul64(v) case OpMul64F: return rewriteValuegeneric_OpMul64F(v) case OpMul8: return rewriteValuegeneric_OpMul8(v) case OpNeg16: return rewriteValuegeneric_OpNeg16(v) case OpNeg32: return rewriteValuegeneric_OpNeg32(v) case OpNeg32F: return rewriteValuegeneric_OpNeg32F(v) case OpNeg64: return rewriteValuegeneric_OpNeg64(v) case OpNeg64F: return rewriteValuegeneric_OpNeg64F(v) case OpNeg8: return rewriteValuegeneric_OpNeg8(v) case OpNeq16: return rewriteValuegeneric_OpNeq16(v) case OpNeq32: return rewriteValuegeneric_OpNeq32(v) case OpNeq32F: return rewriteValuegeneric_OpNeq32F(v) case OpNeq64: return rewriteValuegeneric_OpNeq64(v) case OpNeq64F: return rewriteValuegeneric_OpNeq64F(v) case OpNeq8: return rewriteValuegeneric_OpNeq8(v) case OpNeqB: return rewriteValuegeneric_OpNeqB(v) case OpNeqInter: return rewriteValuegeneric_OpNeqInter(v) case OpNeqPtr: return rewriteValuegeneric_OpNeqPtr(v) case OpNeqSlice: return rewriteValuegeneric_OpNeqSlice(v) case OpNilCheck: return rewriteValuegeneric_OpNilCheck(v) case OpNot: return rewriteValuegeneric_OpNot(v) case OpOffPtr: return rewriteValuegeneric_OpOffPtr(v) case OpOr16: return rewriteValuegeneric_OpOr16(v) case OpOr32: return rewriteValuegeneric_OpOr32(v) case OpOr64: return rewriteValuegeneric_OpOr64(v) case OpOr8: return rewriteValuegeneric_OpOr8(v) case OpOrB: return rewriteValuegeneric_OpOrB(v) case OpPhi: return rewriteValuegeneric_OpPhi(v) case OpPtrIndex: return rewriteValuegeneric_OpPtrIndex(v) case OpRotateLeft16: return rewriteValuegeneric_OpRotateLeft16(v) case OpRotateLeft32: return rewriteValuegeneric_OpRotateLeft32(v) case OpRotateLeft64: return rewriteValuegeneric_OpRotateLeft64(v) case OpRotateLeft8: return rewriteValuegeneric_OpRotateLeft8(v) case OpRound32F: return rewriteValuegeneric_OpRound32F(v) case OpRound64F: return rewriteValuegeneric_OpRound64F(v) case OpRsh16Ux16: return rewriteValuegeneric_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValuegeneric_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValuegeneric_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValuegeneric_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValuegeneric_OpRsh16x16(v) case OpRsh16x32: return rewriteValuegeneric_OpRsh16x32(v) case OpRsh16x64: return rewriteValuegeneric_OpRsh16x64(v) case OpRsh16x8: return rewriteValuegeneric_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValuegeneric_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValuegeneric_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValuegeneric_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValuegeneric_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValuegeneric_OpRsh32x16(v) case OpRsh32x32: return rewriteValuegeneric_OpRsh32x32(v) case OpRsh32x64: return rewriteValuegeneric_OpRsh32x64(v) case OpRsh32x8: return rewriteValuegeneric_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValuegeneric_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValuegeneric_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValuegeneric_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValuegeneric_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValuegeneric_OpRsh64x16(v) case OpRsh64x32: return rewriteValuegeneric_OpRsh64x32(v) case OpRsh64x64: return rewriteValuegeneric_OpRsh64x64(v) case OpRsh64x8: return rewriteValuegeneric_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValuegeneric_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValuegeneric_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValuegeneric_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValuegeneric_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValuegeneric_OpRsh8x16(v) case OpRsh8x32: return rewriteValuegeneric_OpRsh8x32(v) case OpRsh8x64: return rewriteValuegeneric_OpRsh8x64(v) case OpRsh8x8: return rewriteValuegeneric_OpRsh8x8(v) case OpSelect0: return rewriteValuegeneric_OpSelect0(v) case OpSelect1: return rewriteValuegeneric_OpSelect1(v) case OpSelectN: return rewriteValuegeneric_OpSelectN(v) case OpSignExt16to32: return rewriteValuegeneric_OpSignExt16to32(v) case OpSignExt16to64: return rewriteValuegeneric_OpSignExt16to64(v) case OpSignExt32to64: return rewriteValuegeneric_OpSignExt32to64(v) case OpSignExt8to16: return rewriteValuegeneric_OpSignExt8to16(v) case OpSignExt8to32: return rewriteValuegeneric_OpSignExt8to32(v) case OpSignExt8to64: return rewriteValuegeneric_OpSignExt8to64(v) case OpSliceCap: return rewriteValuegeneric_OpSliceCap(v) case OpSliceLen: return rewriteValuegeneric_OpSliceLen(v) case OpSlicePtr: return rewriteValuegeneric_OpSlicePtr(v) case OpSlicemask: return rewriteValuegeneric_OpSlicemask(v) case OpSqrt: return rewriteValuegeneric_OpSqrt(v) case OpStaticLECall: return rewriteValuegeneric_OpStaticLECall(v) case OpStore: return rewriteValuegeneric_OpStore(v) case OpStringLen: return rewriteValuegeneric_OpStringLen(v) case OpStringPtr: return rewriteValuegeneric_OpStringPtr(v) case OpStructSelect: return rewriteValuegeneric_OpStructSelect(v) case OpSub16: return rewriteValuegeneric_OpSub16(v) case OpSub32: return rewriteValuegeneric_OpSub32(v) case OpSub32F: return rewriteValuegeneric_OpSub32F(v) case OpSub64: return rewriteValuegeneric_OpSub64(v) case OpSub64F: return rewriteValuegeneric_OpSub64F(v) case OpSub8: return rewriteValuegeneric_OpSub8(v) case OpTrunc16to8: return rewriteValuegeneric_OpTrunc16to8(v) case OpTrunc32to16: return rewriteValuegeneric_OpTrunc32to16(v) case OpTrunc32to8: return rewriteValuegeneric_OpTrunc32to8(v) case OpTrunc64to16: return rewriteValuegeneric_OpTrunc64to16(v) case OpTrunc64to32: return rewriteValuegeneric_OpTrunc64to32(v) case OpTrunc64to8: return rewriteValuegeneric_OpTrunc64to8(v) case OpXor16: return rewriteValuegeneric_OpXor16(v) case OpXor32: return rewriteValuegeneric_OpXor32(v) case OpXor64: return rewriteValuegeneric_OpXor64(v) case OpXor8: return rewriteValuegeneric_OpXor8(v) case OpZero: return rewriteValuegeneric_OpZero(v) case OpZeroExt16to32: return rewriteValuegeneric_OpZeroExt16to32(v) case OpZeroExt16to64: return rewriteValuegeneric_OpZeroExt16to64(v) case OpZeroExt32to64: return rewriteValuegeneric_OpZeroExt32to64(v) case OpZeroExt8to16: return rewriteValuegeneric_OpZeroExt8to16(v) case OpZeroExt8to32: return rewriteValuegeneric_OpZeroExt8to32(v) case OpZeroExt8to64: return rewriteValuegeneric_OpZeroExt8to64(v) } return false } func rewriteValuegeneric_OpAdd16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Add16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c + d) return true } break } // match: (Add16 (Mul16 x y) (Mul16 x z)) // result: (Mul16 x (Add16 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add16 (Const16 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add16 x (Neg16 y)) // result: (Sub16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg16 { continue } y := v_1.Args[0] v.reset(OpSub16) v.AddArg2(x, y) return true } break } // match: (Add16 (Com16 x) x) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Add16 (Const16 [1]) (Com16 x)) // result: (Neg16 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 1 || v_1.Op != OpCom16 { continue } x := v_1.Args[0] v.reset(OpNeg16) v.AddArg(x) return true } break } // match: (Add16 x (Sub16 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub16 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add16 x (Add16 y (Sub16 z x))) // result: (Add16 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub16 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd16) v.AddArg2(y, z) return true } } break } // match: (Add16 (Add16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Add16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add16 (Sub16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub16 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { continue } t := i.Type x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Add16 (Const16 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add16 (Const16 [c]) (Sub16 (Const16 [d]) x)) // result: (Sub16 (Const16 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpSub16 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } // match: (Add16 (Lsh16x64 x z:(Const64 [c])) (Rsh16Ux64 x (Const64 [d]))) // cond: c < 16 && d == 16-c && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh16x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh16Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 16 && d == 16-c && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Add16 left:(Lsh16x64 x y) right:(Rsh16Ux64 x (Sub64 (Const64 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Add16 left:(Lsh16x32 x y) right:(Rsh16Ux32 x (Sub32 (Const32 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Add16 left:(Lsh16x16 x y) right:(Rsh16Ux16 x (Sub16 (Const16 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Add16 left:(Lsh16x8 x y) right:(Rsh16Ux8 x (Sub8 (Const8 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Add16 right:(Rsh16Ux64 x y) left:(Lsh16x64 x z:(Sub64 (Const64 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Add16 right:(Rsh16Ux32 x y) left:(Lsh16x32 x z:(Sub32 (Const32 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Add16 right:(Rsh16Ux16 x y) left:(Lsh16x16 x z:(Sub16 (Const16 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Add16 right:(Rsh16Ux8 x y) left:(Lsh16x8 x z:(Sub8 (Const8 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpAdd32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Add32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c + d) return true } break } // match: (Add32 (Mul32 x y) (Mul32 x z)) // result: (Mul32 x (Add32 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add32 (Const32 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add32 x (Neg32 y)) // result: (Sub32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg32 { continue } y := v_1.Args[0] v.reset(OpSub32) v.AddArg2(x, y) return true } break } // match: (Add32 (Com32 x) x) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Add32 (Const32 [1]) (Com32 x)) // result: (Neg32 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 1 || v_1.Op != OpCom32 { continue } x := v_1.Args[0] v.reset(OpNeg32) v.AddArg(x) return true } break } // match: (Add32 x (Sub32 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub32 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add32 x (Add32 y (Sub32 z x))) // result: (Add32 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd32) v.AddArg2(y, z) return true } } break } // match: (Add32 (Add32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Add32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add32 (Sub32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub32 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { continue } t := i.Type x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Add32 (Const32 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add32 (Const32 [c]) (Sub32 (Const32 [d]) x)) // result: (Sub32 (Const32 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpSub32 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } // match: (Add32 (Lsh32x64 x z:(Const64 [c])) (Rsh32Ux64 x (Const64 [d]))) // cond: c < 32 && d == 32-c && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh32x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh32Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 32 && d == 32-c && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Add32 left:(Lsh32x64 x y) right:(Rsh32Ux64 x (Sub64 (Const64 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Add32 left:(Lsh32x32 x y) right:(Rsh32Ux32 x (Sub32 (Const32 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Add32 left:(Lsh32x16 x y) right:(Rsh32Ux16 x (Sub16 (Const16 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Add32 left:(Lsh32x8 x y) right:(Rsh32Ux8 x (Sub8 (Const8 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Add32 right:(Rsh32Ux64 x y) left:(Lsh32x64 x z:(Sub64 (Const64 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Add32 right:(Rsh32Ux32 x y) left:(Lsh32x32 x z:(Sub32 (Const32 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Add32 right:(Rsh32Ux16 x y) left:(Lsh32x16 x z:(Sub16 (Const16 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Add32 right:(Rsh32Ux8 x y) left:(Lsh32x8 x z:(Sub8 (Const8 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpAdd32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Add32F (Const32F [c]) (Const32F [d])) // cond: c+d == c+d // result: (Const32F [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) if !(c+d == c+d) { continue } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c + d) return true } break } return false } func rewriteValuegeneric_OpAdd64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Add64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c + d) return true } break } // match: (Add64 (Mul64 x y) (Mul64 x z)) // result: (Mul64 x (Add64 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add64 (Const64 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add64 x (Neg64 y)) // result: (Sub64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg64 { continue } y := v_1.Args[0] v.reset(OpSub64) v.AddArg2(x, y) return true } break } // match: (Add64 (Com64 x) x) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Add64 (Const64 [1]) (Com64 x)) // result: (Neg64 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 1 || v_1.Op != OpCom64 { continue } x := v_1.Args[0] v.reset(OpNeg64) v.AddArg(x) return true } break } // match: (Add64 x (Sub64 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub64 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add64 x (Add64 y (Sub64 z x))) // result: (Add64 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub64 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd64) v.AddArg2(y, z) return true } } break } // match: (Add64 (Add64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Add64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add64 (Sub64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub64 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { continue } t := i.Type x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Add64 (Const64 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add64 (Const64 [c]) (Sub64 (Const64 [d]) x)) // result: (Sub64 (Const64 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpSub64 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } // match: (Add64 (Lsh64x64 x z:(Const64 [c])) (Rsh64Ux64 x (Const64 [d]))) // cond: c < 64 && d == 64-c && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh64x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh64Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 64 && d == 64-c && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Add64 left:(Lsh64x64 x y) right:(Rsh64Ux64 x (Sub64 (Const64 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Add64 left:(Lsh64x32 x y) right:(Rsh64Ux32 x (Sub32 (Const32 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Add64 left:(Lsh64x16 x y) right:(Rsh64Ux16 x (Sub16 (Const16 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Add64 left:(Lsh64x8 x y) right:(Rsh64Ux8 x (Sub8 (Const8 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Add64 right:(Rsh64Ux64 x y) left:(Lsh64x64 x z:(Sub64 (Const64 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Add64 right:(Rsh64Ux32 x y) left:(Lsh64x32 x z:(Sub32 (Const32 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Add64 right:(Rsh64Ux16 x y) left:(Lsh64x16 x z:(Sub16 (Const16 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Add64 right:(Rsh64Ux8 x y) left:(Lsh64x8 x z:(Sub8 (Const8 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpAdd64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Add64F (Const64F [c]) (Const64F [d])) // cond: c+d == c+d // result: (Const64F [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) if !(c+d == c+d) { continue } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c + d) return true } break } return false } func rewriteValuegeneric_OpAdd8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Add8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c + d) return true } break } // match: (Add8 (Mul8 x y) (Mul8 x z)) // result: (Mul8 x (Add8 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add8 (Const8 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add8 x (Neg8 y)) // result: (Sub8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg8 { continue } y := v_1.Args[0] v.reset(OpSub8) v.AddArg2(x, y) return true } break } // match: (Add8 (Com8 x) x) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Add8 (Const8 [1]) (Com8 x)) // result: (Neg8 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 1 || v_1.Op != OpCom8 { continue } x := v_1.Args[0] v.reset(OpNeg8) v.AddArg(x) return true } break } // match: (Add8 x (Sub8 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub8 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add8 x (Add8 y (Sub8 z x))) // result: (Add8 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub8 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd8) v.AddArg2(y, z) return true } } break } // match: (Add8 (Add8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Add8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add8 (Sub8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub8 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { continue } t := i.Type x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Add8 (Const8 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add8 (Const8 [c]) (Sub8 (Const8 [d]) x)) // result: (Sub8 (Const8 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpSub8 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } // match: (Add8 (Lsh8x64 x z:(Const64 [c])) (Rsh8Ux64 x (Const64 [d]))) // cond: c < 8 && d == 8-c && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh8x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh8Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 8 && d == 8-c && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Add8 left:(Lsh8x64 x y) right:(Rsh8Ux64 x (Sub64 (Const64 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Add8 left:(Lsh8x32 x y) right:(Rsh8Ux32 x (Sub32 (Const32 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Add8 left:(Lsh8x16 x y) right:(Rsh8Ux16 x (Sub16 (Const16 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Add8 left:(Lsh8x8 x y) right:(Rsh8Ux8 x (Sub8 (Const8 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Add8 right:(Rsh8Ux64 x y) left:(Lsh8x64 x z:(Sub64 (Const64 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Add8 right:(Rsh8Ux32 x y) left:(Lsh8x32 x z:(Sub32 (Const32 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Add8 right:(Rsh8Ux16 x y) left:(Lsh8x16 x z:(Sub16 (Const16 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Add8 right:(Rsh8Ux8 x y) left:(Lsh8x8 x z:(Sub8 (Const8 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpAddPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (AddPtr x (Const64 [c])) // result: (OffPtr x [c]) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpOffPtr) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (AddPtr x (Const32 [c])) // result: (OffPtr x [int64(c)]) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpOffPtr) v.Type = t v.AuxInt = int64ToAuxInt(int64(c)) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c & d) return true } break } // match: (And16 (Const16 [m]) (Rsh16Ux64 _ (Const64 [c]))) // cond: c >= int64(16-ntz16(m)) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } m := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpRsh16Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(16-ntz16(m))) { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 (Const16 [m]) (Lsh16x64 _ (Const64 [c]))) // cond: c >= int64(16-nlz16(m)) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } m := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpLsh16x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(16-nlz16(m))) { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And16 (Const16 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And16 (Const16 [0]) _) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 (Com16 x) x) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 x (And16 x y)) // result: (And16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd16) v.AddArg2(x, y) return true } } break } // match: (And16 (And16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (And16 i (And16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And16 (Const16 [c]) (And16 (Const16 [d]) x)) // result: (And16 (Const16 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAnd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAnd32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c & d) return true } break } // match: (And32 (Const32 [m]) (Rsh32Ux64 _ (Const64 [c]))) // cond: c >= int64(32-ntz32(m)) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } m := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpRsh32Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(32-ntz32(m))) { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 (Const32 [m]) (Lsh32x64 _ (Const64 [c]))) // cond: c >= int64(32-nlz32(m)) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } m := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpLsh32x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(32-nlz32(m))) { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And32 (Const32 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And32 (Const32 [0]) _) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 (Com32 x) x) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 x (And32 x y)) // result: (And32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd32) v.AddArg2(x, y) return true } } break } // match: (And32 (And32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (And32 i (And32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And32 (Const32 [c]) (And32 (Const32 [d]) x)) // result: (And32 (Const32 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAnd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAnd64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c & d) return true } break } // match: (And64 (Const64 [m]) (Rsh64Ux64 _ (Const64 [c]))) // cond: c >= int64(64-ntz64(m)) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } m := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpRsh64Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(64-ntz64(m))) { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 (Const64 [m]) (Lsh64x64 _ (Const64 [c]))) // cond: c >= int64(64-nlz64(m)) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } m := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpLsh64x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(64-nlz64(m))) { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And64 (Const64 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And64 (Const64 [0]) _) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 (Com64 x) x) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 x (And64 x y)) // result: (And64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd64) v.AddArg2(x, y) return true } } break } // match: (And64 (And64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (And64 i (And64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And64 (Const64 [c]) (And64 (Const64 [d]) x)) // result: (And64 (Const64 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAnd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAnd8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c & d) return true } break } // match: (And8 (Const8 [m]) (Rsh8Ux64 _ (Const64 [c]))) // cond: c >= int64(8-ntz8(m)) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } m := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpRsh8Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(8-ntz8(m))) { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 (Const8 [m]) (Lsh8x64 _ (Const64 [c]))) // cond: c >= int64(8-nlz8(m)) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } m := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpLsh8x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(8-nlz8(m))) { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And8 (Const8 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And8 (Const8 [0]) _) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 (Com8 x) x) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 x (And8 x y)) // result: (And8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd8) v.AddArg2(x, y) return true } } break } // match: (And8 (And8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (And8 i (And8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And8 (Const8 [c]) (And8 (Const8 [d]) x)) // result: (And8 (Const8 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAnd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAndB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (AndB (Leq64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: d >= c // result: (Less64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: d >= c // result: (Leq64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: d >= c // result: (Less32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: d >= c // result: (Leq32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: d >= c // result: (Less16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: d >= c // result: (Leq16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: d >= c // result: (Less8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: d >= c // result: (Leq8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c) // result: (Less64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c) // result: (Leq64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c) // result: (Less32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c) // result: (Leq32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c) // result: (Less16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c) // result: (Leq16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c) // result: (Less8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c) // result: (Leq8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c) // result: (Less64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c) // result: (Leq64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c) // result: (Less32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c) // result: (Leq32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c) // result: (Less16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c) // result: (Leq16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c) // result: (Less8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c) // result: (Leq8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } return false } func rewriteValuegeneric_OpArraySelect(v *Value) bool { v_0 := v.Args[0] // match: (ArraySelect (ArrayMake1 x)) // result: x for { if v_0.Op != OpArrayMake1 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (ArraySelect [0] (IData x)) // result: (IData x) for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpIData { break } x := v_0.Args[0] v.reset(OpIData) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpCom16(v *Value) bool { v_0 := v.Args[0] // match: (Com16 (Com16 x)) // result: x for { if v_0.Op != OpCom16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com16 (Const16 [c])) // result: (Const16 [^c]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(^c) return true } // match: (Com16 (Add16 (Const16 [-1]) x)) // result: (Neg16 x) for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst16 || auxIntToInt16(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg16) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpCom32(v *Value) bool { v_0 := v.Args[0] // match: (Com32 (Com32 x)) // result: x for { if v_0.Op != OpCom32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com32 (Const32 [c])) // result: (Const32 [^c]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(^c) return true } // match: (Com32 (Add32 (Const32 [-1]) x)) // result: (Neg32 x) for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg32) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpCom64(v *Value) bool { v_0 := v.Args[0] // match: (Com64 (Com64 x)) // result: x for { if v_0.Op != OpCom64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com64 (Const64 [c])) // result: (Const64 [^c]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(^c) return true } // match: (Com64 (Add64 (Const64 [-1]) x)) // result: (Neg64 x) for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg64) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpCom8(v *Value) bool { v_0 := v.Args[0] // match: (Com8 (Com8 x)) // result: x for { if v_0.Op != OpCom8 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com8 (Const8 [c])) // result: (Const8 [^c]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(^c) return true } // match: (Com8 (Add8 (Const8 [-1]) x)) // result: (Neg8 x) for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst8 || auxIntToInt8(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpConstInterface(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ConstInterface) // result: (IMake (ConstNil ) (ConstNil )) for { v.reset(OpIMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.Uintptr) v1 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpConstSlice(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (ConstSlice) // cond: config.PtrSize == 4 // result: (SliceMake (ConstNil ) (Const32 [0]) (Const32 [0])) for { if !(config.PtrSize == 4) { break } v.reset(OpSliceMake) v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = int32ToAuxInt(0) v.AddArg3(v0, v1, v1) return true } // match: (ConstSlice) // cond: config.PtrSize == 8 // result: (SliceMake (ConstNil ) (Const64 [0]) (Const64 [0])) for { if !(config.PtrSize == 8) { break } v.reset(OpSliceMake) v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = int64ToAuxInt(0) v.AddArg3(v0, v1, v1) return true } return false } func rewriteValuegeneric_OpConstString(v *Value) bool { b := v.Block config := b.Func.Config fe := b.Func.fe typ := &b.Func.Config.Types // match: (ConstString {str}) // cond: config.PtrSize == 4 && str == "" // result: (StringMake (ConstNil) (Const32 [0])) for { str := auxToString(v.Aux) if !(config.PtrSize == 4 && str == "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v1) return true } // match: (ConstString {str}) // cond: config.PtrSize == 8 && str == "" // result: (StringMake (ConstNil) (Const64 [0])) for { str := auxToString(v.Aux) if !(config.PtrSize == 8 && str == "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, v1) return true } // match: (ConstString {str}) // cond: config.PtrSize == 4 && str != "" // result: (StringMake (Addr {fe.StringData(str)} (SB)) (Const32 [int32(len(str))])) for { str := auxToString(v.Aux) if !(config.PtrSize == 4 && str != "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) v0.Aux = symToAux(fe.StringData(str)) v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int) v2.AuxInt = int32ToAuxInt(int32(len(str))) v.AddArg2(v0, v2) return true } // match: (ConstString {str}) // cond: config.PtrSize == 8 && str != "" // result: (StringMake (Addr {fe.StringData(str)} (SB)) (Const64 [int64(len(str))])) for { str := auxToString(v.Aux) if !(config.PtrSize == 8 && str != "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) v0.Aux = symToAux(fe.StringData(str)) v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.Int) v2.AuxInt = int64ToAuxInt(int64(len(str))) v.AddArg2(v0, v2) return true } return false } func rewriteValuegeneric_OpConvert(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Convert (Add64 (Convert ptr mem) off) mem) // result: (AddPtr ptr off) for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConvert { continue } mem := v_0_0.Args[1] ptr := v_0_0.Args[0] off := v_0_1 if mem != v_1 { continue } v.reset(OpAddPtr) v.AddArg2(ptr, off) return true } break } // match: (Convert (Add32 (Convert ptr mem) off) mem) // result: (AddPtr ptr off) for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConvert { continue } mem := v_0_0.Args[1] ptr := v_0_0.Args[0] off := v_0_1 if mem != v_1 { continue } v.reset(OpAddPtr) v.AddArg2(ptr, off) return true } break } // match: (Convert (Convert ptr mem) mem) // result: ptr for { if v_0.Op != OpConvert { break } mem := v_0.Args[1] ptr := v_0.Args[0] if mem != v_1 { break } v.copyOf(ptr) return true } return false } func rewriteValuegeneric_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz16 (Const16 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz16(c))) return true } // match: (Ctz16 (Const16 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz16(c))) return true } return false } func rewriteValuegeneric_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz32 (Const32 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz32(c))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz32(c))) return true } // match: (Ctz32 (Const32 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz32(c))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz32(c))) return true } return false } func rewriteValuegeneric_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz64 (Const64 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz64(c))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz64(c))) return true } // match: (Ctz64 (Const64 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz64(c))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } return false } func rewriteValuegeneric_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz8 (Const8 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz8(c))) return true } // match: (Ctz8 (Const8 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz8(c))) return true } return false } func rewriteValuegeneric_OpCvt32Fto32(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32Fto32 (Const32F [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } return false } func rewriteValuegeneric_OpCvt32Fto64(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32Fto64 (Const32F [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } return false } func rewriteValuegeneric_OpCvt32Fto64F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32Fto64F (Const32F [c])) // result: (Const64F [float64(c)]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(float64(c)) return true } return false } func rewriteValuegeneric_OpCvt32to32F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32to32F (Const32 [c])) // result: (Const32F [float32(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(float32(c)) return true } return false } func rewriteValuegeneric_OpCvt32to64F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32to64F (Const32 [c])) // result: (Const64F [float64(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(float64(c)) return true } return false } func rewriteValuegeneric_OpCvt64Fto32(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64Fto32 (Const64F [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } return false } func rewriteValuegeneric_OpCvt64Fto32F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64Fto32F (Const64F [c])) // result: (Const32F [float32(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(float32(c)) return true } // match: (Cvt64Fto32F sqrt0:(Sqrt (Cvt32Fto64F x))) // cond: sqrt0.Uses==1 // result: (Sqrt32 x) for { sqrt0 := v_0 if sqrt0.Op != OpSqrt { break } sqrt0_0 := sqrt0.Args[0] if sqrt0_0.Op != OpCvt32Fto64F { break } x := sqrt0_0.Args[0] if !(sqrt0.Uses == 1) { break } v.reset(OpSqrt32) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpCvt64Fto64(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64Fto64 (Const64F [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } return false } func rewriteValuegeneric_OpCvt64to32F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64to32F (Const64 [c])) // result: (Const32F [float32(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(float32(c)) return true } return false } func rewriteValuegeneric_OpCvt64to64F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64to64F (Const64 [c])) // result: (Const64F [float64(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(float64(c)) return true } return false } func rewriteValuegeneric_OpCvtBoolToUint8(v *Value) bool { v_0 := v.Args[0] // match: (CvtBoolToUint8 (ConstBool [false])) // result: (Const8 [0]) for { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != false { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (CvtBoolToUint8 (ConstBool [true])) // result: (Const8 [1]) for { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != true { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(1) return true } return false } func rewriteValuegeneric_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [c/d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c / d) return true } // match: (Div16 n (Const16 [c])) // cond: isNonNegative(n) && isPowerOfTwo16(c) // result: (Rsh16Ux64 n (Const64 [log16(c)])) for { n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo16(c)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log16(c)) v.AddArg2(n, v0) return true } // match: (Div16 n (Const16 [c])) // cond: c < 0 && c != -1<<15 // result: (Neg16 (Div16 n (Const16 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(c < 0 && c != -1<<15) { break } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpDiv16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div16 x (Const16 [-1<<15])) // result: (Rsh16Ux64 (And16 x (Neg16 x)) (Const64 [15])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != -1<<15 { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpNeg16, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(15) v.AddArg2(v0, v2) return true } // match: (Div16 n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [int64(16-log16(c))]))) (Const64 [int64(log16(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { break } v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpAdd16, t) v1 := b.NewValue0(v.Pos, OpRsh16Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh16x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(15) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(16 - log16(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log16(c))) v.AddArg2(v0, v5) return true } // match: (Div16 x (Const16 [c])) // cond: smagicOK16(c) // result: (Sub16 (Rsh32x64 (Mul32 (Const32 [int32(smagic16(c).m)]) (SignExt16to32 x)) (Const64 [16+smagic16(c).s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(smagicOK16(c)) { break } v.reset(OpSub16) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(smagic16(c).m)) v3 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16 + smagic16(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(31) v5.AddArg2(v3, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div16u (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int16(uint16(c)/uint16(d))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint16(c) / uint16(d))) return true } // match: (Div16u n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (Rsh16Ux64 n (Const64 [log16(c)])) for { n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log16(c)) v.AddArg2(n, v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 8 // result: (Trunc64to16 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<16+umagic16(c).m)]) (ZeroExt16to64 x)) (Const64 [16+umagic16(c).s]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 8) { break } v.reset(OpTrunc64to16) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(1<<16 + umagic16(c).m)) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16 + umagic16(c).s) v0.AddArg2(v1, v4) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 4 && umagic16(c).m&1 == 0 // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<15+umagic16(c).m/2)]) (ZeroExt16to32 x)) (Const64 [16+umagic16(c).s-1]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 4 && umagic16(c).m&1 == 0) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(1<<15 + umagic16(c).m/2)) v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 1) v0.AddArg2(v1, v4) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 4 && c&1 == 0 // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<15+(umagic16(c).m+1)/2)]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [16+umagic16(c).s-2]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 4 && c&1 == 0) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(1<<15 + (umagic16(c).m+1)/2)) v3 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v4.AddArg(x) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(1) v3.AddArg2(v4, v5) v1.AddArg2(v2, v3) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 2) v0.AddArg2(v1, v6) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 4 && config.useAvg // result: (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) (Mul32 (Const32 [int32(umagic16(c).m)]) (ZeroExt16to32 x))) (Const64 [16+umagic16(c).s-1]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 4 && config.useAvg) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) v2 := b.NewValue0(v.Pos, OpLsh32x64, typ.UInt32) v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v3.AddArg(x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16) v2.AddArg2(v3, v4) v5 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(umagic16(c).m)) v5.AddArg2(v6, v3) v1.AddArg2(v2, v5) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 1) v0.AddArg2(v1, v7) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32 (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [c/d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c / d) return true } // match: (Div32 n (Const32 [c])) // cond: isNonNegative(n) && isPowerOfTwo32(c) // result: (Rsh32Ux64 n (Const64 [log32(c)])) for { n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo32(c)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log32(c)) v.AddArg2(n, v0) return true } // match: (Div32 n (Const32 [c])) // cond: c < 0 && c != -1<<31 // result: (Neg32 (Div32 n (Const32 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(c < 0 && c != -1<<31) { break } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpDiv32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div32 x (Const32 [-1<<31])) // result: (Rsh32Ux64 (And32 x (Neg32 x)) (Const64 [31])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != -1<<31 { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpNeg32, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(31) v.AddArg2(v0, v2) return true } // match: (Div32 n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [int64(32-log32(c))]))) (Const64 [int64(log32(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { break } v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpAdd32, t) v1 := b.NewValue0(v.Pos, OpRsh32Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh32x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(31) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(32 - log32(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log32(c))) v.AddArg2(v0, v5) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK32(c) && config.RegSize == 8 // result: (Sub32 (Rsh64x64 (Mul64 (Const64 [int64(smagic32(c).m)]) (SignExt32to64 x)) (Const64 [32+smagic32(c).s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(smagicOK32(c) && config.RegSize == 8) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(smagic32(c).m)) v3 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(32 + smagic32(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh64x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(63) v5.AddArg2(v3, v6) v.AddArg2(v0, v5) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0 && config.useHmul // result: (Sub32 (Rsh32x64 (Hmul32 (Const32 [int32(smagic32(c).m/2)]) x) (Const64 [smagic32(c).s-1])) (Rsh32x64 x (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0 && config.useHmul) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpHmul32, t) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(smagic32(c).m / 2)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(smagic32(c).s - 1) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpRsh32x64, t) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(31) v4.AddArg2(x, v5) v.AddArg2(v0, v4) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0 && config.useHmul // result: (Sub32 (Rsh32x64 (Add32 (Hmul32 (Const32 [int32(smagic32(c).m)]) x) x) (Const64 [smagic32(c).s])) (Rsh32x64 x (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0 && config.useHmul) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpAdd32, t) v2 := b.NewValue0(v.Pos, OpHmul32, t) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(smagic32(c).m)) v2.AddArg2(v3, x) v1.AddArg2(v2, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(smagic32(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(31) v5.AddArg2(x, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Div32F (Const32F [c]) (Const32F [d])) // cond: c/d == c/d // result: (Const32F [c/d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) if !(c/d == c/d) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c / d) return true } // match: (Div32F x (Const32F [c])) // cond: reciprocalExact32(c) // result: (Mul32F x (Const32F [1/c])) for { x := v_0 if v_1.Op != OpConst32F { break } t := v_1.Type c := auxIntToFloat32(v_1.AuxInt) if !(reciprocalExact32(c)) { break } v.reset(OpMul32F) v0 := b.NewValue0(v.Pos, OpConst32F, t) v0.AuxInt = float32ToAuxInt(1 / c) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpDiv32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32u (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int32(uint32(c)/uint32(d))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint32(c) / uint32(d))) return true } // match: (Div32u n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (Rsh32Ux64 n (Const64 [log32(c)])) for { n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log32(c)) v.AddArg2(n, v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 4 && umagic32(c).m&1 == 0 && config.useHmul // result: (Rsh32Ux64 (Hmul32u (Const32 [int32(1<<31+umagic32(c).m/2)]) x) (Const64 [umagic32(c).s-1])) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 4 && umagic32(c).m&1 == 0 && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v1.AuxInt = int32ToAuxInt(int32(1<<31 + umagic32(c).m/2)) v0.AddArg2(v1, x) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(umagic32(c).s - 1) v.AddArg2(v0, v2) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 4 && c&1 == 0 && config.useHmul // result: (Rsh32Ux64 (Hmul32u (Const32 [int32(1<<31+(umagic32(c).m+1)/2)]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [umagic32(c).s-2])) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 4 && c&1 == 0 && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v1.AuxInt = int32ToAuxInt(int32(1<<31 + (umagic32(c).m+1)/2)) v2 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(1) v2.AddArg2(x, v3) v0.AddArg2(v1, v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(umagic32(c).s - 2) v.AddArg2(v0, v4) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 4 && config.useAvg && config.useHmul // result: (Rsh32Ux64 (Avg32u x (Hmul32u (Const32 [int32(umagic32(c).m)]) x)) (Const64 [umagic32(c).s-1])) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 4 && config.useAvg && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(umagic32(c).m)) v1.AddArg2(v2, x) v0.AddArg2(x, v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(umagic32(c).s - 1) v.AddArg2(v0, v3) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 8 && umagic32(c).m&1 == 0 // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+umagic32(c).m/2)]) (ZeroExt32to64 x)) (Const64 [32+umagic32(c).s-1]))) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 8 && umagic32(c).m&1 == 0) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(1<<31 + umagic32(c).m/2)) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 1) v0.AddArg2(v1, v4) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 8 && c&1 == 0 // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+(umagic32(c).m+1)/2)]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [32+umagic32(c).s-2]))) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 8 && c&1 == 0) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(1<<31 + (umagic32(c).m+1)/2)) v3 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(x) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(1) v3.AddArg2(v4, v5) v1.AddArg2(v2, v3) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 2) v0.AddArg2(v1, v6) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 8 && config.useAvg // result: (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) (Mul64 (Const64 [int64(umagic32(c).m)]) (ZeroExt32to64 x))) (Const64 [32+umagic32(c).s-1]))) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 8 && config.useAvg) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(32) v2.AddArg2(v3, v4) v5 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt32) v6.AuxInt = int64ToAuxInt(int64(umagic32(c).m)) v5.AddArg2(v6, v3) v1.AddArg2(v2, v5) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 1) v0.AddArg2(v1, v7) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64 (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [c/d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c / d) return true } // match: (Div64 n (Const64 [c])) // cond: isNonNegative(n) && isPowerOfTwo64(c) // result: (Rsh64Ux64 n (Const64 [log64(c)])) for { n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo64(c)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(n, v0) return true } // match: (Div64 n (Const64 [-1<<63])) // cond: isNonNegative(n) // result: (Const64 [0]) for { n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 || !(isNonNegative(n)) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Div64 n (Const64 [c])) // cond: c < 0 && c != -1<<63 // result: (Neg64 (Div64 n (Const64 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c < 0 && c != -1<<63) { break } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpDiv64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div64 x (Const64 [-1<<63])) // result: (Rsh64Ux64 (And64 x (Neg64 x)) (Const64 [63])) for { t := v.Type x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpNeg64, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(63) v.AddArg2(v0, v2) return true } // match: (Div64 n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [int64(64-log64(c))]))) (Const64 [int64(log64(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v1 := b.NewValue0(v.Pos, OpRsh64Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh64x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(63) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(64 - log64(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log64(c))) v.AddArg2(v0, v5) return true } // match: (Div64 x (Const64 [c])) // cond: smagicOK64(c) && smagic64(c).m&1 == 0 && config.useHmul // result: (Sub64 (Rsh64x64 (Hmul64 (Const64 [int64(smagic64(c).m/2)]) x) (Const64 [smagic64(c).s-1])) (Rsh64x64 x (Const64 [63]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(smagicOK64(c) && smagic64(c).m&1 == 0 && config.useHmul) { break } v.reset(OpSub64) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpHmul64, t) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(smagic64(c).m / 2)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(smagic64(c).s - 1) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpRsh64x64, t) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(63) v4.AddArg2(x, v5) v.AddArg2(v0, v4) return true } // match: (Div64 x (Const64 [c])) // cond: smagicOK64(c) && smagic64(c).m&1 != 0 && config.useHmul // result: (Sub64 (Rsh64x64 (Add64 (Hmul64 (Const64 [int64(smagic64(c).m)]) x) x) (Const64 [smagic64(c).s])) (Rsh64x64 x (Const64 [63]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(smagicOK64(c) && smagic64(c).m&1 != 0 && config.useHmul) { break } v.reset(OpSub64) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpAdd64, t) v2 := b.NewValue0(v.Pos, OpHmul64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(int64(smagic64(c).m)) v2.AddArg2(v3, x) v1.AddArg2(v2, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(smagic64(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh64x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(63) v5.AddArg2(x, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Div64F (Const64F [c]) (Const64F [d])) // cond: c/d == c/d // result: (Const64F [c/d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) if !(c/d == c/d) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c / d) return true } // match: (Div64F x (Const64F [c])) // cond: reciprocalExact64(c) // result: (Mul64F x (Const64F [1/c])) for { x := v_0 if v_1.Op != OpConst64F { break } t := v_1.Type c := auxIntToFloat64(v_1.AuxInt) if !(reciprocalExact64(c)) { break } v.reset(OpMul64F) v0 := b.NewValue0(v.Pos, OpConst64F, t) v0.AuxInt = float64ToAuxInt(1 / c) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpDiv64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64u (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [int64(uint64(c)/uint64(d))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint64(c) / uint64(d))) return true } // match: (Div64u n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (Rsh64Ux64 n (Const64 [log64(c)])) for { n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(n, v0) return true } // match: (Div64u n (Const64 [-1<<63])) // result: (Rsh64Ux64 n (Const64 [63])) for { n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(63) v.AddArg2(n, v0) return true } // match: (Div64u x (Const64 [c])) // cond: c > 0 && c <= 0xFFFF && umagicOK32(int32(c)) && config.RegSize == 4 && config.useHmul // result: (Add64 (Add64 (Add64 (Lsh64x64 (ZeroExt32to64 (Div32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)]))) (Const64 [32])) (ZeroExt32to64 (Div32u (Trunc64to32 x) (Const32 [int32(c)])))) (Mul64 (ZeroExt32to64 (Mod32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)]))) (Const64 [int64((1<<32)/c)]))) (ZeroExt32to64 (Div32u (Add32 (Mod32u (Trunc64to32 x) (Const32 [int32(c)])) (Mul32 (Mod32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)])) (Const32 [int32((1<<32)%c)]))) (Const32 [int32(c)])))) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c > 0 && c <= 0xFFFF && umagicOK32(int32(c)) && config.RegSize == 4 && config.useHmul) { break } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) v5 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v6 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = int64ToAuxInt(32) v6.AddArg2(x, v7) v5.AddArg(v6) v8 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v8.AuxInt = int32ToAuxInt(int32(c)) v4.AddArg2(v5, v8) v3.AddArg(v4) v2.AddArg2(v3, v7) v9 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v10 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) v11 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v11.AddArg(x) v10.AddArg2(v11, v8) v9.AddArg(v10) v1.AddArg2(v2, v9) v12 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v13 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v14 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v14.AddArg2(v5, v8) v13.AddArg(v14) v15 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v15.AuxInt = int64ToAuxInt(int64((1 << 32) / c)) v12.AddArg2(v13, v15) v0.AddArg2(v1, v12) v16 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v17 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) v18 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v19 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v19.AddArg2(v11, v8) v20 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v21 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v21.AuxInt = int32ToAuxInt(int32((1 << 32) % c)) v20.AddArg2(v14, v21) v18.AddArg2(v19, v20) v17.AddArg2(v18, v8) v16.AddArg(v17) v.AddArg2(v0, v16) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK64(c) && config.RegSize == 8 && umagic64(c).m&1 == 0 && config.useHmul // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+umagic64(c).m/2)]) x) (Const64 [umagic64(c).s-1])) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(umagicOK64(c) && config.RegSize == 8 && umagic64(c).m&1 == 0 && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(int64(1<<63 + umagic64(c).m/2)) v0.AddArg2(v1, x) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(umagic64(c).s - 1) v.AddArg2(v0, v2) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK64(c) && config.RegSize == 8 && c&1 == 0 && config.useHmul // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+(umagic64(c).m+1)/2)]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [umagic64(c).s-2])) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(umagicOK64(c) && config.RegSize == 8 && c&1 == 0 && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(int64(1<<63 + (umagic64(c).m+1)/2)) v2 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(1) v2.AddArg2(x, v3) v0.AddArg2(v1, v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(umagic64(c).s - 2) v.AddArg2(v0, v4) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK64(c) && config.RegSize == 8 && config.useAvg && config.useHmul // result: (Rsh64Ux64 (Avg64u x (Hmul64u (Const64 [int64(umagic64(c).m)]) x)) (Const64 [umagic64(c).s-1])) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(umagicOK64(c) && config.RegSize == 8 && config.useAvg && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(umagic64(c).m)) v1.AddArg2(v2, x) v0.AddArg2(x, v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(umagic64(c).s - 1) v.AddArg2(v0, v3) return true } return false } func rewriteValuegeneric_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [c/d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c / d) return true } // match: (Div8 n (Const8 [c])) // cond: isNonNegative(n) && isPowerOfTwo8(c) // result: (Rsh8Ux64 n (Const64 [log8(c)])) for { n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo8(c)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log8(c)) v.AddArg2(n, v0) return true } // match: (Div8 n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Neg8 (Div8 n (Const8 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(c < 0 && c != -1<<7) { break } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpDiv8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div8 x (Const8 [-1<<7 ])) // result: (Rsh8Ux64 (And8 x (Neg8 x)) (Const64 [7 ])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != -1<<7 { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpNeg8, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(7) v.AddArg2(v0, v2) return true } // match: (Div8 n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [int64( 8-log8(c))]))) (Const64 [int64(log8(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { break } v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpAdd8, t) v1 := b.NewValue0(v.Pos, OpRsh8Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh8x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(7) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(8 - log8(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log8(c))) v.AddArg2(v0, v5) return true } // match: (Div8 x (Const8 [c])) // cond: smagicOK8(c) // result: (Sub8 (Rsh32x64 (Mul32 (Const32 [int32(smagic8(c).m)]) (SignExt8to32 x)) (Const64 [8+smagic8(c).s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(smagicOK8(c)) { break } v.reset(OpSub8) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(smagic8(c).m)) v3 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(8 + smagic8(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(31) v5.AddArg2(v3, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int8(uint8(c)/uint8(d))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(uint8(c) / uint8(d))) return true } // match: (Div8u n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (Rsh8Ux64 n (Const64 [log8(c)])) for { n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log8(c)) v.AddArg2(n, v0) return true } // match: (Div8u x (Const8 [c])) // cond: umagicOK8(c) // result: (Trunc32to8 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<8+umagic8(c).m)]) (ZeroExt8to32 x)) (Const64 [8+umagic8(c).s]))) for { x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(umagicOK8(c)) { break } v.reset(OpTrunc32to8) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(1<<8 + umagic8(c).m)) v3 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(8 + umagic8(c).s) v0.AddArg2(v1, v4) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Eq16 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Eq16 (Const16 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq16 (Const16 [c]) (Const16 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq16 (Mod16u x (Const16 [c])) (Const16 [0])) // cond: x.Op != OpConst16 && udivisibleOK16(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt16to32 x) (Const32 [int32(uint16(c))])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod16u { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 || !(x.Op != OpConst16 && udivisibleOK16(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(uint16(c))) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq16 (Mod16 x (Const16 [c])) (Const16 [0])) // cond: x.Op != OpConst16 && sdivisibleOK16(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32 (SignExt16to32 x) (Const32 [int32(c)])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod16 { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 || !(x.Op != OpConst16 && sdivisibleOK16(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic16(c).m) && s == 16+umagic16(c).s && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpZeroExt16to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic16(c).m) && s == 16+umagic16(c).s && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+umagic16(c).m/2) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpZeroExt16to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+umagic16(c).m/2) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+(umagic16(c).m+1)/2) && s == 16+umagic16(c).s-2 && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpRsh32Ux64 { continue } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt16to32 || x != mul_1_0.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+(umagic16(c).m+1)/2) && s == 16+umagic16(c).s-2 && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic16(c).m) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg32u { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh32x64 { continue } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt16to32 || x != v_1_1_0_0_0_0.Args[0] { continue } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 || auxIntToInt64(v_1_1_0_0_0_1.AuxInt) != 16 { continue } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpZeroExt16to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic16(c).m) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic16(c).m) && s == 16+smagic16(c).s && x.Op != OpConst16 && sdivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int16(sdivisible16(c).m)]) x) (Const16 [int16(sdivisible16(c).a)]) ) (Const16 [int16(16-sdivisible16(c).k)]) ) (Const16 [int16(sdivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpSub16 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpSignExt16to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt16to32 || x != v_1_1_1_0.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic16(c).m) && s == 16+smagic16(c).s && x.Op != OpConst16 && sdivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(sdivisible16(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(sdivisible16(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v5.AuxInt = int16ToAuxInt(int16(16 - sdivisible16(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v6.AuxInt = int16ToAuxInt(int16(sdivisible16(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh16x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh16x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd16 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh16Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh16x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 15 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 15 && kbar == 16-k) { continue } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(1< x (Const16 [y])) (Const16 [y])) // cond: oneBit16(y) // result: (Neq16 (And16 x (Const16 [y])) (Const16 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst16 || v_0_1.Type != t { continue } y := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || v_1.Type != t || auxIntToInt16(v_1.AuxInt) != y || !(oneBit16(y)) { continue } v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq32 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Eq32 (Const32 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) x) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+umagic32(c).m/2) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpRsh32Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+umagic32(c).m/2) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+(umagic32(c).m+1)/2) && s == umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpRsh32Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 || mul_0.Type != typ.UInt32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpRsh32Ux64 { continue } _ = mul_1.Args[1] if x != mul_1.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+(umagic32(c).m+1)/2) && s == umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 (Avg32u x mul:(Hmul32u (Const32 [m]) x)) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic32(c).m) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpRsh32Ux64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg32u { continue } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { continue } mul := v_1_1_0.Args[1] if mul.Op != OpHmul32u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic32(c).m) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic32(c).m/2) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to32 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpZeroExt32to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic32(c).m/2) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic32(c).m+1)/2) && s == 32+umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to32 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpRsh64Ux64 { continue } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt32to64 || x != mul_1_0.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic32(c).m+1)/2) && s == 32+umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic32(c).m) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to32 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg64u { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh64x64 { continue } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt32to64 || x != v_1_1_0_0_0_0.Args[0] { continue } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 || auxIntToInt64(v_1_1_0_0_0_1.AuxInt) != 32 { continue } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpZeroExt32to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic32(c).m) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic32(c).m) && s == 32+smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpSignExt32to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { continue } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt32to64 || x != v_1_1_1_0.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic32(c).m) && s == 32+smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m/2) && s == smagic32(c).s-1 && x.Op != OpConst32 && sdivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpHmul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m/2) && s == smagic32(c).s-1 && x.Op != OpConst32 && sdivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m) && s == smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd32 { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] v_1_1_0_0_1 := v_1_1_0_0.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_1_0_0_0, v_1_1_0_0_1 = _i2+1, v_1_1_0_0_1, v_1_1_0_0_0 { mul := v_1_1_0_0_0 if mul.Op != OpHmul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i3 := 0; _i3 <= 1; _i3, mul_0, mul_1 = _i3+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 || x != v_1_1_0_0_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m) && s == smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) v.AddArg2(v0, v6) return true } } } } break } // match: (Eq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh32x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd32 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh32Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh32x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 31 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 31 && kbar == 32-k) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(1< x (Const32 [y])) (Const32 [y])) // cond: oneBit32(y) // result: (Neq32 (And32 x (Const32 [y])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst32 || v_0_1.Type != t { continue } y := auxIntToInt32(v_0_1.AuxInt) if v_1.Op != OpConst32 || v_1.Type != t || auxIntToInt32(v_1.AuxInt) != y || !(oneBit32(y)) { continue } v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Eq32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } return false } func rewriteValuegeneric_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq64 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Eq64 (Const64 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) x) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic64(c).m/2) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpRsh64Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic64(c).m/2) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic64(c).m+1)/2) && s == umagic64(c).s-2 && x.Op != OpConst64 && udivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpRsh64Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpRsh64Ux64 { continue } _ = mul_1.Args[1] if x != mul_1.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic64(c).m+1)/2) && s == umagic64(c).s-2 && x.Op != OpConst64 && udivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 (Avg64u x mul:(Hmul64u (Const64 [m]) x)) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic64(c).m) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpRsh64Ux64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg64u { continue } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { continue } mul := v_1_1_0.Args[1] if mul.Op != OpHmul64u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic64(c).m) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m/2) && s == smagic64(c).s-1 && x.Op != OpConst64 && sdivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible64(c).m)]) x) (Const64 [int64(sdivisible64(c).a)]) ) (Const64 [64-sdivisible64(c).k]) ) (Const64 [int64(sdivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpSub64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpHmul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m/2) && s == smagic64(c).s-1 && x.Op != OpConst64 && sdivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(int64(sdivisible64(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(sdivisible64(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(64 - sdivisible64(c).k) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(int64(sdivisible64(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m) && s == smagic64(c).s && x.Op != OpConst64 && sdivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible64(c).m)]) x) (Const64 [int64(sdivisible64(c).a)]) ) (Const64 [64-sdivisible64(c).k]) ) (Const64 [int64(sdivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpSub64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd64 { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] v_1_1_0_0_1 := v_1_1_0_0.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_1_0_0_0, v_1_1_0_0_1 = _i2+1, v_1_1_0_0_1, v_1_1_0_0_0 { mul := v_1_1_0_0_0 if mul.Op != OpHmul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i3 := 0; _i3 <= 1; _i3, mul_0, mul_1 = _i3+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 || x != v_1_1_0_0_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m) && s == smagic64(c).s && x.Op != OpConst64 && sdivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(int64(sdivisible64(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(sdivisible64(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(64 - sdivisible64(c).k) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(int64(sdivisible64(c).max)) v.AddArg2(v0, v6) return true } } } } break } // match: (Eq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh64x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd64 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh64Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh64x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 63 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 63 && kbar == 64-k) { continue } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(1< x (Const64 [y])) (Const64 [y])) // cond: oneBit64(y) // result: (Neq64 (And64 x (Const64 [y])) (Const64 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst64 || v_0_1.Type != t { continue } y := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 || v_1.Type != t || auxIntToInt64(v_1.AuxInt) != y || !(oneBit64(y)) { continue } v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Eq64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } return false } func rewriteValuegeneric_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Eq8 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Eq8 (Const8 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq8 (Mod8u x (Const8 [c])) (Const8 [0])) // cond: x.Op != OpConst8 && udivisibleOK8(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt8to32 x) (Const32 [int32(uint8(c))])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod8u { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 || !(x.Op != OpConst8 && udivisibleOK8(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(uint8(c))) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq8 (Mod8 x (Const8 [c])) (Const8 [0])) // cond: x.Op != OpConst8 && sdivisibleOK8(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32 (SignExt8to32 x) (Const32 [int32(c)])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod8 { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 || !(x.Op != OpConst8 && sdivisibleOK8(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<8+umagic8(c).m) && s == 8+umagic8(c).s && x.Op != OpConst8 && udivisibleOK8(c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int8(udivisible8(c).m)]) x) (Const8 [int8(8-udivisible8(c).k)]) ) (Const8 [int8(udivisible8(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to8 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpZeroExt8to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<8+umagic8(c).m) && s == 8+umagic8(c).s && x.Op != OpConst8 && udivisibleOK8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int8ToAuxInt(int8(udivisible8(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int8ToAuxInt(int8(8 - udivisible8(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int8ToAuxInt(int8(udivisible8(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq8 x (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic8(c).m) && s == 8+smagic8(c).s && x.Op != OpConst8 && sdivisibleOK8(c) // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int8(sdivisible8(c).m)]) x) (Const8 [int8(sdivisible8(c).a)]) ) (Const8 [int8(8-sdivisible8(c).k)]) ) (Const8 [int8(sdivisible8(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0.AuxInt) if v_1_1.Op != OpSub8 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpSignExt8to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt8to32 || x != v_1_1_1_0.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic8(c).m) && s == 8+smagic8(c).s && x.Op != OpConst8 && sdivisibleOK8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int8ToAuxInt(int8(sdivisible8(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int8ToAuxInt(int8(sdivisible8(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v5.AuxInt = int8ToAuxInt(int8(8 - sdivisible8(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v6.AuxInt = int8ToAuxInt(int8(sdivisible8(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh8x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh8x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd8 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh8Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh8x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 7 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 7 && kbar == 8-k) { continue } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(1< x (Const8 [y])) (Const8 [y])) // cond: oneBit8(y) // result: (Neq8 (And8 x (Const8 [y])) (Const8 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst8 || v_0_1.Type != t { continue } y := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || v_1.Type != t || auxIntToInt8(v_1.AuxInt) != y || !(oneBit8(y)) { continue } v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EqB (ConstBool [c]) (ConstBool [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool { continue } c := auxIntToBool(v_0.AuxInt) if v_1.Op != OpConstBool { continue } d := auxIntToBool(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (EqB (ConstBool [false]) x) // result: (Not x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != false { continue } x := v_1 v.reset(OpNot) v.AddArg(x) return true } break } // match: (EqB (ConstBool [true]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != true { continue } x := v_1 v.copyOf(x) return true } break } return false } func rewriteValuegeneric_OpEqInter(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqInter x y) // result: (EqPtr (ITab x) (ITab y)) for { x := v_0 y := v_1 v.reset(OpEqPtr) v0 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqPtr x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (EqPtr (Addr {x} _) (Addr {y} _)) // result: (ConstBool [x == y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y) return true } break } // match: (EqPtr (Addr {x} _) (OffPtr [o] (Addr {y} _))) // result: (ConstBool [x == y && o == 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o == 0) return true } break } // match: (EqPtr (OffPtr [o1] (Addr {x} _)) (OffPtr [o2] (Addr {y} _))) // result: (ConstBool [x == y && o1 == o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o1 == o2) return true } break } // match: (EqPtr (LocalAddr {x} _ _) (LocalAddr {y} _ _)) // result: (ConstBool [x == y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpLocalAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y) return true } break } // match: (EqPtr (LocalAddr {x} _ _) (OffPtr [o] (LocalAddr {y} _ _))) // result: (ConstBool [x == y && o == 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o == 0) return true } break } // match: (EqPtr (OffPtr [o1] (LocalAddr {x} _ _)) (OffPtr [o2] (LocalAddr {y} _ _))) // result: (ConstBool [x == y && o1 == o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o1 == o2) return true } break } // match: (EqPtr (OffPtr [o1] p1) p2) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 == 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 == 0) return true } break } // match: (EqPtr (OffPtr [o1] p1) (OffPtr [o2] p2)) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 == o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 == o2) return true } break } // match: (EqPtr (Const32 [c]) (Const32 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (EqPtr (Const64 [c]) (Const64 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (EqPtr (LocalAddr _ _) (Addr _)) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (OffPtr (LocalAddr _ _)) (Addr _)) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (LocalAddr _ _) (OffPtr (Addr _))) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (OffPtr (LocalAddr _ _)) (OffPtr (Addr _))) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (AddPtr p1 o1) p2) // cond: isSamePtr(p1, p2) // result: (Not (IsNonNil o1)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddPtr { continue } o1 := v_0.Args[1] p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(o1) v.AddArg(v0) return true } break } // match: (EqPtr (Const32 [0]) p) // result: (Not (IsNonNil p)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(p) v.AddArg(v0) return true } break } // match: (EqPtr (Const64 [0]) p) // result: (Not (IsNonNil p)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(p) v.AddArg(v0) return true } break } // match: (EqPtr (ConstNil) p) // result: (Not (IsNonNil p)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstNil { continue } p := v_1 v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(p) v.AddArg(v0) return true } break } return false } func rewriteValuegeneric_OpEqSlice(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqSlice x y) // result: (EqPtr (SlicePtr x) (SlicePtr y)) for { x := v_0 y := v_1 v.reset(OpEqPtr) v0 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpIMake(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (IMake _typ (StructMake1 val)) // result: (IMake _typ val) for { _typ := v_0 if v_1.Op != OpStructMake1 { break } val := v_1.Args[0] v.reset(OpIMake) v.AddArg2(_typ, val) return true } // match: (IMake _typ (ArrayMake1 val)) // result: (IMake _typ val) for { _typ := v_0 if v_1.Op != OpArrayMake1 { break } val := v_1.Args[0] v.reset(OpIMake) v.AddArg2(_typ, val) return true } return false } func rewriteValuegeneric_OpInterLECall(v *Value) bool { // match: (InterLECall [argsize] {auxCall} (Load (OffPtr [off] (ITab (IMake (Addr {itab} (SB)) _))) _) ___) // cond: devirtLESym(v, auxCall, itab, off) != nil // result: devirtLECall(v, devirtLESym(v, auxCall, itab, off)) for { if len(v.Args) < 1 { break } auxCall := auxToCall(v.Aux) v_0 := v.Args[0] if v_0.Op != OpLoad { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpOffPtr { break } off := auxIntToInt64(v_0_0.AuxInt) v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpITab { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpIMake { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAddr { break } itab := auxToSym(v_0_0_0_0_0.Aux) v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpSB || !(devirtLESym(v, auxCall, itab, off) != nil) { break } v.copyOf(devirtLECall(v, devirtLESym(v, auxCall, itab, off))) return true } return false } func rewriteValuegeneric_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (IsInBounds (ZeroExt8to32 _) (Const32 [c])) // cond: (1 << 8) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to32 || v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !((1 << 8) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt8to64 _) (Const64 [c])) // cond: (1 << 8) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to64 || v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !((1 << 8) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt16to32 _) (Const32 [c])) // cond: (1 << 16) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to32 || v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !((1 << 16) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt16to64 _) (Const64 [c])) // cond: (1 << 16) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to64 || v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !((1 << 16) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (IsInBounds (And8 (Const8 [c]) _) (Const8 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd8 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt8to16 (And8 (Const8 [c]) _)) (Const16 [d])) // cond: 0 <= c && int16(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) if !(0 <= c && int16(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt8to32 (And8 (Const8 [c]) _)) (Const32 [d])) // cond: 0 <= c && int32(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) if !(0 <= c && int32(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt8to64 (And8 (Const8 [c]) _)) (Const64 [d])) // cond: 0 <= c && int64(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && int64(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (And16 (Const16 [c]) _) (Const16 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd16 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt16to32 (And16 (Const16 [c]) _)) (Const32 [d])) // cond: 0 <= c && int32(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) if !(0 <= c && int32(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt16to64 (And16 (Const16 [c]) _)) (Const64 [d])) // cond: 0 <= c && int64(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && int64(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (And32 (Const32 [c]) _) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd32 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt32to64 (And32 (Const32 [c]) _)) (Const64 [d])) // cond: 0 <= c && int64(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt32to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd32 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && int64(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (And64 (Const64 [c]) _) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd64 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (Const32 [c]) (Const32 [d])) // result: (ConstBool [0 <= c && c < d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(0 <= c && c < d) return true } // match: (IsInBounds (Const64 [c]) (Const64 [d])) // result: (ConstBool [0 <= c && c < d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(0 <= c && c < d) return true } // match: (IsInBounds (Mod32u _ y) y) // result: (ConstBool [true]) for { if v_0.Op != OpMod32u { break } y := v_0.Args[1] if y != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (Mod64u _ y) y) // result: (ConstBool [true]) for { if v_0.Op != OpMod64u { break } y := v_0.Args[1] if y != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt8to64 (Rsh8Ux64 _ (Const64 [c]))) (Const64 [d])) // cond: 0 < c && c < 8 && 1<= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 || v_1.Op != OpAnd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq16 (Const16 [0]) (Rsh16Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 || v_1.Op != OpRsh16Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq16U (Const16 [c]) (Const16 [d])) // result: (ConstBool [uint16(c) <= uint16(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint16(c) <= uint16(d)) return true } // match: (Leq16U (Const16 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } // match: (Leq32 (Const32 [0]) (And32 _ (Const32 [c]))) // cond: c >= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 || v_1.Op != OpAnd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq32 (Const32 [0]) (Rsh32Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 || v_1.Op != OpRsh32Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } return false } func rewriteValuegeneric_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq32U (Const32 [c]) (Const32 [d])) // result: (ConstBool [uint32(c) <= uint32(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint32(c) <= uint32(d)) return true } // match: (Leq32U (Const32 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } // match: (Leq64 (Const64 [0]) (And64 _ (Const64 [c]))) // cond: c >= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 || v_1.Op != OpAnd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq64 (Const64 [0]) (Rsh64Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 || v_1.Op != OpRsh64Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } return false } func rewriteValuegeneric_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq64U (Const64 [c]) (Const64 [d])) // result: (ConstBool [uint64(c) <= uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint64(c) <= uint64(d)) return true } // match: (Leq64U (Const64 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } // match: (Leq8 (Const8 [0]) (And8 _ (Const8 [c]))) // cond: c >= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 || v_1.Op != OpAnd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq8 (Const8 [0]) (Rsh8Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 || v_1.Op != OpRsh8Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq8U (Const8 [c]) (Const8 [d])) // result: (ConstBool [ uint8(c) <= uint8(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint8(c) <= uint8(d)) return true } // match: (Leq8U (Const8 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16 (Const16 [c]) (Const16 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less16 (Const16 [0]) x) // cond: isNonNegative(x) // result: (Neq16 (Const16 [0]) x) for { if v_0.Op != OpConst16 { break } t := v_0.Type if auxIntToInt16(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less16 x (Const16 [1])) // cond: isNonNegative(x) // result: (Eq16 (Const16 [0]) x) for { x := v_0 if v_1.Op != OpConst16 { break } t := v_1.Type if auxIntToInt16(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less16U (Const16 [c]) (Const16 [d])) // result: (ConstBool [uint16(c) < uint16(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint16(c) < uint16(d)) return true } // match: (Less16U _ (Const16 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less32 (Const32 [0]) x) // cond: isNonNegative(x) // result: (Neq32 (Const32 [0]) x) for { if v_0.Op != OpConst32 { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less32 x (Const32 [1])) // cond: isNonNegative(x) // result: (Eq32 (Const32 [0]) x) for { x := v_0 if v_1.Op != OpConst32 { break } t := v_1.Type if auxIntToInt32(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } return false } func rewriteValuegeneric_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less32U (Const32 [c]) (Const32 [d])) // result: (ConstBool [uint32(c) < uint32(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint32(c) < uint32(d)) return true } // match: (Less32U _ (Const32 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less64 (Const64 [0]) x) // cond: isNonNegative(x) // result: (Neq64 (Const64 [0]) x) for { if v_0.Op != OpConst64 { break } t := v_0.Type if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less64 x (Const64 [1])) // cond: isNonNegative(x) // result: (Eq64 (Const64 [0]) x) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } return false } func rewriteValuegeneric_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less64U (Const64 [c]) (Const64 [d])) // result: (ConstBool [uint64(c) < uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint64(c) < uint64(d)) return true } // match: (Less64U _ (Const64 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less8 (Const8 [0]) x) // cond: isNonNegative(x) // result: (Neq8 (Const8 [0]) x) for { if v_0.Op != OpConst8 { break } t := v_0.Type if auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less8 x (Const8 [1])) // cond: isNonNegative(x) // result: (Eq8 (Const8 [0]) x) for { x := v_0 if v_1.Op != OpConst8 { break } t := v_1.Type if auxIntToInt8(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less8U (Const8 [c]) (Const8 [d])) // result: (ConstBool [ uint8(c) < uint8(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint8(c) < uint8(d)) return true } // match: (Less8U _ (Const8 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (Load p1 (Store {t2} p2 x _)) // cond: isSamePtr(p1, p2) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) x := v_1.Args[1] p2 := v_1.Args[0] if !(isSamePtr(p1, p2) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size()) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 x _))) // cond: isSamePtr(p1, p3) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p3, t3.Size(), p2, t2.Size()) // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) x := v_1_2.Args[1] p3 := v_1_2.Args[0] if !(isSamePtr(p1, p3) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p3, t3.Size(), p2, t2.Size())) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 x _)))) // cond: isSamePtr(p1, p4) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p4, t4.Size(), p2, t2.Size()) && disjoint(p4, t4.Size(), p3, t3.Size()) // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) x := v_1_2_2.Args[1] p4 := v_1_2_2.Args[0] if !(isSamePtr(p1, p4) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p4, t4.Size(), p2, t2.Size()) && disjoint(p4, t4.Size(), p3, t3.Size())) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 x _))))) // cond: isSamePtr(p1, p5) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p5, t5.Size(), p2, t2.Size()) && disjoint(p5, t5.Size(), p3, t3.Size()) && disjoint(p5, t5.Size(), p4, t4.Size()) // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] v_1_2_2_2 := v_1_2_2.Args[2] if v_1_2_2_2.Op != OpStore { break } t5 := auxToType(v_1_2_2_2.Aux) x := v_1_2_2_2.Args[1] p5 := v_1_2_2_2.Args[0] if !(isSamePtr(p1, p5) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p5, t5.Size(), p2, t2.Size()) && disjoint(p5, t5.Size(), p3, t3.Size()) && disjoint(p5, t5.Size(), p4, t4.Size())) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 (Const64 [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x))) // result: (Const64F [math.Float64frombits(uint64(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } x := auxIntToInt64(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x)))) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(math.Float64frombits(uint64(x))) return true } // match: (Load p1 (Store {t2} p2 (Const32 [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x)))) // result: (Const32F [math.Float32frombits(uint32(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } x := auxIntToInt32(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x))))) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(math.Float32frombits(uint32(x))) return true } // match: (Load p1 (Store {t2} p2 (Const64F [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitInt(t1) // result: (Const64 [int64(math.Float64bits(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64F { break } x := auxIntToFloat64(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitInt(t1)) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(math.Float64bits(x))) return true } // match: (Load p1 (Store {t2} p2 (Const32F [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitInt(t1) // result: (Const32 [int32(math.Float32bits(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32F { break } x := auxIntToFloat32(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitInt(t1)) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(math.Float32bits(x))) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ mem:(Zero [n] p3 _))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p3) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) // result: @mem.Block (Load (OffPtr [o1] p3) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] mem := v_1.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p3 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p3) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p3) v0.AddArg2(v1, mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ mem:(Zero [n] p4 _)))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p4) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) // result: @mem.Block (Load (OffPtr [o1] p4) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] mem := v_1_2.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p4 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p4) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p4) v0.AddArg2(v1, mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ mem:(Zero [n] p5 _))))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p5) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) // result: @mem.Block (Load (OffPtr [o1] p5) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] mem := v_1_2_2.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p5 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p5) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p5) v0.AddArg2(v1, mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 _ mem:(Zero [n] p6 _)))))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p6) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) && disjoint(op, t1.Size(), p5, t5.Size()) // result: @mem.Block (Load (OffPtr [o1] p6) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] v_1_2_2_2 := v_1_2_2.Args[2] if v_1_2_2_2.Op != OpStore { break } t5 := auxToType(v_1_2_2_2.Aux) _ = v_1_2_2_2.Args[2] p5 := v_1_2_2_2.Args[0] mem := v_1_2_2_2.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p6 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p6) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) && disjoint(op, t1.Size(), p5, t5.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p6) v0.AddArg2(v1, mem) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: t1.IsBoolean() && isSamePtr(p1, p2) && n >= o + 1 // result: (ConstBool [false]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(t1.IsBoolean() && isSamePtr(p1, p2) && n >= o+1) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is8BitInt(t1) && isSamePtr(p1, p2) && n >= o + 1 // result: (Const8 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is8BitInt(t1) && isSamePtr(p1, p2) && n >= o+1) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is16BitInt(t1) && isSamePtr(p1, p2) && n >= o + 2 // result: (Const16 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is16BitInt(t1) && isSamePtr(p1, p2) && n >= o+2) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is32BitInt(t1) && isSamePtr(p1, p2) && n >= o + 4 // result: (Const32 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is32BitInt(t1) && isSamePtr(p1, p2) && n >= o+4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is64BitInt(t1) && isSamePtr(p1, p2) && n >= o + 8 // result: (Const64 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is64BitInt(t1) && isSamePtr(p1, p2) && n >= o+8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is32BitFloat(t1) && isSamePtr(p1, p2) && n >= o + 4 // result: (Const32F [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is32BitFloat(t1) && isSamePtr(p1, p2) && n >= o+4) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is64BitFloat(t1) && isSamePtr(p1, p2) && n >= o + 8 // result: (Const64F [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is64BitFloat(t1) && isSamePtr(p1, p2) && n >= o+8) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(0) return true } // match: (Load _ _) // cond: t.IsStruct() && t.NumFields() == 0 && fe.CanSSA(t) // result: (StructMake0) for { t := v.Type if !(t.IsStruct() && t.NumFields() == 0 && fe.CanSSA(t)) { break } v.reset(OpStructMake0) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 1 && fe.CanSSA(t) // result: (StructMake1 (Load (OffPtr [0] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 1 && fe.CanSSA(t)) { break } v.reset(OpStructMake1) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v.AddArg(v0) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 2 && fe.CanSSA(t) // result: (StructMake2 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 2 && fe.CanSSA(t)) { break } v.reset(OpStructMake2) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = int64ToAuxInt(t.FieldOff(1)) v3.AddArg(ptr) v2.AddArg2(v3, mem) v.AddArg2(v0, v2) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 3 && fe.CanSSA(t) // result: (StructMake3 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem) (Load (OffPtr [t.FieldOff(2)] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 3 && fe.CanSSA(t)) { break } v.reset(OpStructMake3) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = int64ToAuxInt(t.FieldOff(1)) v3.AddArg(ptr) v2.AddArg2(v3, mem) v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2)) v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v5.AuxInt = int64ToAuxInt(t.FieldOff(2)) v5.AddArg(ptr) v4.AddArg2(v5, mem) v.AddArg3(v0, v2, v4) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 4 && fe.CanSSA(t) // result: (StructMake4 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem) (Load (OffPtr [t.FieldOff(2)] ptr) mem) (Load (OffPtr [t.FieldOff(3)] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 4 && fe.CanSSA(t)) { break } v.reset(OpStructMake4) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = int64ToAuxInt(t.FieldOff(1)) v3.AddArg(ptr) v2.AddArg2(v3, mem) v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2)) v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v5.AuxInt = int64ToAuxInt(t.FieldOff(2)) v5.AddArg(ptr) v4.AddArg2(v5, mem) v6 := b.NewValue0(v.Pos, OpLoad, t.FieldType(3)) v7 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo()) v7.AuxInt = int64ToAuxInt(t.FieldOff(3)) v7.AddArg(ptr) v6.AddArg2(v7, mem) v.AddArg4(v0, v2, v4, v6) return true } // match: (Load _ _) // cond: t.IsArray() && t.NumElem() == 0 // result: (ArrayMake0) for { t := v.Type if !(t.IsArray() && t.NumElem() == 0) { break } v.reset(OpArrayMake0) return true } // match: (Load ptr mem) // cond: t.IsArray() && t.NumElem() == 1 && fe.CanSSA(t) // result: (ArrayMake1 (Load ptr mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsArray() && t.NumElem() == 1 && fe.CanSSA(t)) { break } v.reset(OpArrayMake1) v0 := b.NewValue0(v.Pos, OpLoad, t.Elem()) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x16 x (Const16 [c])) // result: (Lsh16x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh16x16 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x32 x (Const32 [c])) // result: (Lsh16x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh16x32 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x64 (Const16 [c]) (Const64 [d])) // result: (Const16 [c << uint64(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c << uint64(d)) return true } // match: (Lsh16x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh16x64 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Lsh16x64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Lsh16x64 (Lsh16x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh16x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh16x64 (Rsh16Ux64 (Lsh16x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh16x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh16x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x8 x (Const8 [c])) // result: (Lsh16x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh16x8 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x16 x (Const16 [c])) // result: (Lsh32x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh32x16 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x32 x (Const32 [c])) // result: (Lsh32x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh32x32 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x64 (Const32 [c]) (Const64 [d])) // result: (Const32 [c << uint64(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c << uint64(d)) return true } // match: (Lsh32x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh32x64 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Lsh32x64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Lsh32x64 (Lsh32x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh32x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh32x64 (Rsh32Ux64 (Lsh32x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh32x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh32x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x8 x (Const8 [c])) // result: (Lsh32x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh32x8 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x16 x (Const16 [c])) // result: (Lsh64x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh64x16 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x32 x (Const32 [c])) // result: (Lsh64x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh64x32 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c << uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c << uint64(d)) return true } // match: (Lsh64x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh64x64 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Lsh64x64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (Const64 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 64) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Lsh64x64 (Lsh64x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh64x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh64x64 (Rsh64Ux64 (Lsh64x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh64x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh64x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x8 x (Const8 [c])) // result: (Lsh64x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh64x8 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x16 x (Const16 [c])) // result: (Lsh8x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh8x16 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x32 x (Const32 [c])) // result: (Lsh8x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh8x32 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x64 (Const8 [c]) (Const64 [d])) // result: (Const8 [c << uint64(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c << uint64(d)) return true } // match: (Lsh8x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh8x64 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Lsh8x64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Lsh8x64 (Lsh8x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh8x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh8x64 (Rsh8Ux64 (Lsh8x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh8x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh8x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x8 x (Const8 [c])) // result: (Lsh8x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh8x8 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod16 (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [c % d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c % d) return true } // match: (Mod16 n (Const16 [c])) // cond: isNonNegative(n) && isPowerOfTwo16(c) // result: (And16 n (Const16 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo16(c)) { break } v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod16 n (Const16 [c])) // cond: c < 0 && c != -1<<15 // result: (Mod16 n (Const16 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(c < 0 && c != -1<<15) { break } v.reset(OpMod16) v.Type = t v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod16 x (Const16 [c])) // cond: x.Op != OpConst16 && (c > 0 || c == -1<<15) // result: (Sub16 x (Mul16 (Div16 x (Const16 [c])) (Const16 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(x.Op != OpConst16 && (c > 0 || c == -1<<15)) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpMul16, t) v1 := b.NewValue0(v.Pos, OpDiv16, t) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod16u (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int16(uint16(c) % uint16(d))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint16(c) % uint16(d))) return true } // match: (Mod16u n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (And16 n (Const16 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { break } v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod16u x (Const16 [c])) // cond: x.Op != OpConst16 && c > 0 && umagicOK16(c) // result: (Sub16 x (Mul16 (Div16u x (Const16 [c])) (Const16 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(x.Op != OpConst16 && c > 0 && umagicOK16(c)) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpMul16, t) v1 := b.NewValue0(v.Pos, OpDiv16u, t) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod32 (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [c % d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c % d) return true } // match: (Mod32 n (Const32 [c])) // cond: isNonNegative(n) && isPowerOfTwo32(c) // result: (And32 n (Const32 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo32(c)) { break } v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod32 n (Const32 [c])) // cond: c < 0 && c != -1<<31 // result: (Mod32 n (Const32 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(c < 0 && c != -1<<31) { break } v.reset(OpMod32) v.Type = t v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod32 x (Const32 [c])) // cond: x.Op != OpConst32 && (c > 0 || c == -1<<31) // result: (Sub32 x (Mul32 (Div32 x (Const32 [c])) (Const32 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(x.Op != OpConst32 && (c > 0 || c == -1<<31)) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpMul32, t) v1 := b.NewValue0(v.Pos, OpDiv32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod32u (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int32(uint32(c) % uint32(d))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint32(c) % uint32(d))) return true } // match: (Mod32u n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (And32 n (Const32 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { break } v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod32u x (Const32 [c])) // cond: x.Op != OpConst32 && c > 0 && umagicOK32(c) // result: (Sub32 x (Mul32 (Div32u x (Const32 [c])) (Const32 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(x.Op != OpConst32 && c > 0 && umagicOK32(c)) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpMul32, t) v1 := b.NewValue0(v.Pos, OpDiv32u, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod64 (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [c % d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c % d) return true } // match: (Mod64 n (Const64 [c])) // cond: isNonNegative(n) && isPowerOfTwo64(c) // result: (And64 n (Const64 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo64(c)) { break } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod64 n (Const64 [-1<<63])) // cond: isNonNegative(n) // result: n for { n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 || !(isNonNegative(n)) { break } v.copyOf(n) return true } // match: (Mod64 n (Const64 [c])) // cond: c < 0 && c != -1<<63 // result: (Mod64 n (Const64 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c < 0 && c != -1<<63) { break } v.reset(OpMod64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod64 x (Const64 [c])) // cond: x.Op != OpConst64 && (c > 0 || c == -1<<63) // result: (Sub64 x (Mul64 (Div64 x (Const64 [c])) (Const64 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(x.Op != OpConst64 && (c > 0 || c == -1<<63)) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpMul64, t) v1 := b.NewValue0(v.Pos, OpDiv64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod64u (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [int64(uint64(c) % uint64(d))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint64(c) % uint64(d))) return true } // match: (Mod64u n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (And64 n (Const64 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod64u n (Const64 [-1<<63])) // result: (And64 n (Const64 [1<<63-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 { break } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(1<<63 - 1) v.AddArg2(n, v0) return true } // match: (Mod64u x (Const64 [c])) // cond: x.Op != OpConst64 && c > 0 && umagicOK64(c) // result: (Sub64 x (Mul64 (Div64u x (Const64 [c])) (Const64 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(x.Op != OpConst64 && c > 0 && umagicOK64(c)) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpMul64, t) v1 := b.NewValue0(v.Pos, OpDiv64u, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod8 (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [c % d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c % d) return true } // match: (Mod8 n (Const8 [c])) // cond: isNonNegative(n) && isPowerOfTwo8(c) // result: (And8 n (Const8 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo8(c)) { break } v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod8 n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Mod8 n (Const8 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(c < 0 && c != -1<<7) { break } v.reset(OpMod8) v.Type = t v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod8 x (Const8 [c])) // cond: x.Op != OpConst8 && (c > 0 || c == -1<<7) // result: (Sub8 x (Mul8 (Div8 x (Const8 [c])) (Const8 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(x.Op != OpConst8 && (c > 0 || c == -1<<7)) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpMul8, t) v1 := b.NewValue0(v.Pos, OpDiv8, t) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod8u (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int8(uint8(c) % uint8(d))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(uint8(c) % uint8(d))) return true } // match: (Mod8u n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (And8 n (Const8 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { break } v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod8u x (Const8 [c])) // cond: x.Op != OpConst8 && c > 0 && umagicOK8( c) // result: (Sub8 x (Mul8 (Div8u x (Const8 [c])) (Const8 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(x.Op != OpConst8 && c > 0 && umagicOK8(c)) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpMul8, t) v1 := b.NewValue0(v.Pos, OpDiv8u, t) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Move {t} [n] dst1 src mem:(Zero {t} [n] dst2 _)) // cond: isSamePtr(src, dst2) // result: (Zero {t} [n] dst1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src := v_1 mem := v_2 if mem.Op != OpZero || auxIntToInt64(mem.AuxInt) != n || auxToType(mem.Aux) != t { break } dst2 := mem.Args[0] if !(isSamePtr(src, dst2)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst1, mem) return true } // match: (Move {t} [n] dst1 src mem:(VarDef (Zero {t} [n] dst0 _))) // cond: isSamePtr(src, dst0) // result: (Zero {t} [n] dst1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpZero || auxIntToInt64(mem_0.AuxInt) != n || auxToType(mem_0.Aux) != t { break } dst0 := mem_0.Args[0] if !(isSamePtr(src, dst0)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst1, mem) return true } // match: (Move {t} [n] dst (Addr {sym} (SB)) mem) // cond: symIsROZero(sym) // result: (Zero {t} [n] dst mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst := v_0 if v_1.Op != OpAddr { break } sym := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } mem := v_2 if !(symIsROZero(sym)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst, mem) return true } // match: (Move {t1} [n] dst1 src1 store:(Store {t2} op:(OffPtr [o2] dst2) _ mem)) // cond: isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2 + t2.Size() && disjoint(src1, n, op, t2.Size()) && clobber(store) // result: (Move {t1} [n] dst1 src1 mem) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst1 := v_0 src1 := v_1 store := v_2 if store.Op != OpStore { break } t2 := auxToType(store.Aux) mem := store.Args[2] op := store.Args[0] if op.Op != OpOffPtr { break } o2 := auxIntToInt64(op.AuxInt) dst2 := op.Args[0] if !(isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2+t2.Size() && disjoint(src1, n, op, t2.Size()) && clobber(store)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t1) v.AddArg3(dst1, src1, mem) return true } // match: (Move {t} [n] dst1 src1 move:(Move {t} [n] dst2 _ mem)) // cond: move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move) // result: (Move {t} [n] dst1 src1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 move := v_2 if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg3(dst1, src1, mem) return true } // match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem))) // cond: move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move, vardef) // result: (Move {t} [n] dst1 src1 (VarDef {x} mem)) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 vardef := v_2 if vardef.Op != OpVarDef { break } x := auxToSym(vardef.Aux) move := vardef.Args[0] if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move, vardef)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg3(dst1, src1, v0) return true } // match: (Move {t} [n] dst1 src1 zero:(Zero {t} [n] dst2 mem)) // cond: zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero) // result: (Move {t} [n] dst1 src1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 zero := v_2 if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != n || auxToType(zero.Aux) != t { break } mem := zero.Args[1] dst2 := zero.Args[0] if !(zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg3(dst1, src1, mem) return true } // match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} zero:(Zero {t} [n] dst2 mem))) // cond: zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero, vardef) // result: (Move {t} [n] dst1 src1 (VarDef {x} mem)) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 vardef := v_2 if vardef.Op != OpVarDef { break } x := auxToSym(vardef.Aux) zero := vardef.Args[0] if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != n || auxToType(zero.Aux) != t { break } mem := zero.Args[1] dst2 := zero.Args[0] if !(zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero, vardef)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg3(dst1, src1, v0) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [0] p3) d2 _))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size() + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [0] dst) d2 mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) d2 := mem_2.Args[1] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type if auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size()+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(0) v2.AddArg(dst) v1.AddArg3(v2, d2, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [0] p4) d3 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [0] dst) d3 mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) d3 := mem_2_2.Args[1] op4 := mem_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type if auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(0) v4.AddArg(dst) v3.AddArg3(v4, d3, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [o4] p4) d3 (Store {t5} op5:(OffPtr [0] p5) d4 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [0] dst) d4 mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] op4 := mem_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type o4 := auxIntToInt64(op4.AuxInt) p4 := op4.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpStore { break } t5 := auxToType(mem_2_2_2.Aux) d4 := mem_2_2_2.Args[1] op5 := mem_2_2_2.Args[0] if op5.Op != OpOffPtr { break } tt5 := op5.Type if auxIntToInt64(op5.AuxInt) != 0 { break } p5 := op5.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(0) v6.AddArg(dst) v5.AddArg3(v6, d4, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [0] p3) d2 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size() + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [0] dst) d2 mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) d2 := mem_0_2.Args[1] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type if auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size()+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(0) v2.AddArg(dst) v1.AddArg3(v2, d2, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [0] p4) d3 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [0] dst) d3 mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) d3 := mem_0_2_2.Args[1] op4 := mem_0_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type if auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(0) v4.AddArg(dst) v3.AddArg3(v4, d3, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [o4] p4) d3 (Store {t5} op5:(OffPtr [0] p5) d4 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [0] dst) d4 mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) _ = mem_0_2_2.Args[2] op4 := mem_0_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type o4 := auxIntToInt64(op4.AuxInt) p4 := op4.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpStore { break } t5 := auxToType(mem_0_2_2_2.Aux) d4 := mem_0_2_2_2.Args[1] op5 := mem_0_2_2_2.Args[0] if op5.Op != OpOffPtr { break } tt5 := op5.Type if auxIntToInt64(op5.AuxInt) != 0 { break } p5 := op5.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(0) v6.AddArg(dst) v5.AddArg3(v6, d4, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Zero {t3} [n] p3 _))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2 + t2.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Zero {t1} [n] dst mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpZero || auxIntToInt64(mem_2.AuxInt) != n { break } t3 := auxToType(mem_2.Aux) p3 := mem_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2+t2.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(n) v1.Aux = typeToAux(t1) v1.AddArg2(dst, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Zero {t4} [n] p4 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + t2.Size() && n >= o3 + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Zero {t1} [n] dst mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := auxIntToInt64(mem_0.AuxInt) p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := auxIntToInt64(mem_2_0.AuxInt) p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpZero || auxIntToInt64(mem_2_2.AuxInt) != n { break } t4 := auxToType(mem_2_2.Aux) p4 := mem_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2+t2.Size() && n >= o3+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v3.AuxInt = int64ToAuxInt(n) v3.Aux = typeToAux(t1) v3.AddArg2(dst, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Zero {t5} [n] p5 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Zero {t1} [n] dst mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := auxIntToInt64(mem_0.AuxInt) p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := auxIntToInt64(mem_2_0.AuxInt) p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] mem_2_2_0 := mem_2_2.Args[0] if mem_2_2_0.Op != OpOffPtr { break } tt4 := mem_2_2_0.Type o4 := auxIntToInt64(mem_2_2_0.AuxInt) p4 := mem_2_2_0.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpZero || auxIntToInt64(mem_2_2_2.AuxInt) != n { break } t5 := auxToType(mem_2_2_2.Aux) p5 := mem_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v5.AuxInt = int64ToAuxInt(n) v5.Aux = typeToAux(t1) v5.AddArg2(dst, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Store {t5} (OffPtr [o5] p5) d4 (Zero {t6} [n] p6 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() && n >= o5 + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [o5] dst) d4 (Zero {t1} [n] dst mem))))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := auxIntToInt64(mem_0.AuxInt) p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := auxIntToInt64(mem_2_0.AuxInt) p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] mem_2_2_0 := mem_2_2.Args[0] if mem_2_2_0.Op != OpOffPtr { break } tt4 := mem_2_2_0.Type o4 := auxIntToInt64(mem_2_2_0.AuxInt) p4 := mem_2_2_0.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpStore { break } t5 := auxToType(mem_2_2_2.Aux) _ = mem_2_2_2.Args[2] mem_2_2_2_0 := mem_2_2_2.Args[0] if mem_2_2_2_0.Op != OpOffPtr { break } tt5 := mem_2_2_2_0.Type o5 := auxIntToInt64(mem_2_2_2_0.AuxInt) p5 := mem_2_2_2_0.Args[0] d4 := mem_2_2_2.Args[1] mem_2_2_2_2 := mem_2_2_2.Args[2] if mem_2_2_2_2.Op != OpZero || auxIntToInt64(mem_2_2_2_2.AuxInt) != n { break } t6 := auxToType(mem_2_2_2_2.Aux) p6 := mem_2_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size() && n >= o5+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(o5) v6.AddArg(dst) v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v7.AuxInt = int64ToAuxInt(n) v7.Aux = typeToAux(t1) v7.AddArg2(dst, mem) v5.AddArg3(v6, d4, v7) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Zero {t3} [n] p3 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2 + t2.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Zero {t1} [n] dst mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpZero || auxIntToInt64(mem_0_2.AuxInt) != n { break } t3 := auxToType(mem_0_2.Aux) p3 := mem_0_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2+t2.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(n) v1.Aux = typeToAux(t1) v1.AddArg2(dst, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Zero {t4} [n] p4 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + t2.Size() && n >= o3 + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Zero {t1} [n] dst mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := auxIntToInt64(mem_0_0.AuxInt) p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := auxIntToInt64(mem_0_2_0.AuxInt) p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2.AuxInt) != n { break } t4 := auxToType(mem_0_2_2.Aux) p4 := mem_0_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2+t2.Size() && n >= o3+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v3.AuxInt = int64ToAuxInt(n) v3.Aux = typeToAux(t1) v3.AddArg2(dst, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Zero {t5} [n] p5 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Zero {t1} [n] dst mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := auxIntToInt64(mem_0_0.AuxInt) p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := auxIntToInt64(mem_0_2_0.AuxInt) p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) _ = mem_0_2_2.Args[2] mem_0_2_2_0 := mem_0_2_2.Args[0] if mem_0_2_2_0.Op != OpOffPtr { break } tt4 := mem_0_2_2_0.Type o4 := auxIntToInt64(mem_0_2_2_0.AuxInt) p4 := mem_0_2_2_0.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2_2.AuxInt) != n { break } t5 := auxToType(mem_0_2_2_2.Aux) p5 := mem_0_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v5.AuxInt = int64ToAuxInt(n) v5.Aux = typeToAux(t1) v5.AddArg2(dst, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Store {t5} (OffPtr [o5] p5) d4 (Zero {t6} [n] p6 _))))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() && n >= o5 + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [o5] dst) d4 (Zero {t1} [n] dst mem))))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := auxIntToInt64(mem_0_0.AuxInt) p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := auxIntToInt64(mem_0_2_0.AuxInt) p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) _ = mem_0_2_2.Args[2] mem_0_2_2_0 := mem_0_2_2.Args[0] if mem_0_2_2_0.Op != OpOffPtr { break } tt4 := mem_0_2_2_0.Type o4 := auxIntToInt64(mem_0_2_2_0.AuxInt) p4 := mem_0_2_2_0.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpStore { break } t5 := auxToType(mem_0_2_2_2.Aux) _ = mem_0_2_2_2.Args[2] mem_0_2_2_2_0 := mem_0_2_2_2.Args[0] if mem_0_2_2_2_0.Op != OpOffPtr { break } tt5 := mem_0_2_2_2_0.Type o5 := auxIntToInt64(mem_0_2_2_2_0.AuxInt) p5 := mem_0_2_2_2_0.Args[0] d4 := mem_0_2_2_2.Args[1] mem_0_2_2_2_2 := mem_0_2_2_2.Args[2] if mem_0_2_2_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2_2_2.AuxInt) != n { break } t6 := auxToType(mem_0_2_2_2_2.Aux) p6 := mem_0_2_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size() && n >= o5+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(o5) v6.AddArg(dst) v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v7.AuxInt = int64ToAuxInt(n) v7.Aux = typeToAux(t1) v7.AddArg2(dst, mem) v5.AddArg3(v6, d4, v7) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [s] dst tmp1 midmem:(Move {t2} [s] tmp2 src _)) // cond: t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config)) // result: (Move {t1} [s] dst src midmem) for { s := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 tmp1 := v_1 midmem := v_2 if midmem.Op != OpMove || auxIntToInt64(midmem.AuxInt) != s { break } t2 := auxToType(midmem.Aux) src := midmem.Args[1] tmp2 := midmem.Args[0] if !(t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s) v.Aux = typeToAux(t1) v.AddArg3(dst, src, midmem) return true } // match: (Move {t1} [s] dst tmp1 midmem:(VarDef (Move {t2} [s] tmp2 src _))) // cond: t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config)) // result: (Move {t1} [s] dst src midmem) for { s := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 tmp1 := v_1 midmem := v_2 if midmem.Op != OpVarDef { break } midmem_0 := midmem.Args[0] if midmem_0.Op != OpMove || auxIntToInt64(midmem_0.AuxInt) != s { break } t2 := auxToType(midmem_0.Aux) src := midmem_0.Args[1] tmp2 := midmem_0.Args[0] if !(t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s) v.Aux = typeToAux(t1) v.AddArg3(dst, src, midmem) return true } // match: (Move dst src mem) // cond: isSamePtr(dst, src) // result: mem for { dst := v_0 src := v_1 mem := v_2 if !(isSamePtr(dst, src)) { break } v.copyOf(mem) return true } return false } func rewriteValuegeneric_OpMul16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c * d) return true } break } // match: (Mul16 (Const16 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul16 (Const16 [-1]) x) // result: (Neg16 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg16) v.AddArg(x) return true } break } // match: (Mul16 n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (Lsh16x64 n (Const64 [log16(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { continue } v.reset(OpLsh16x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log16(c)) v.AddArg2(n, v0) return true } break } // match: (Mul16 n (Const16 [c])) // cond: t.IsSigned() && isPowerOfTwo16(-c) // result: (Neg16 (Lsh16x64 n (Const64 [log16(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo16(-c)) { continue } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log16(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul16 (Const16 [0]) _) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (Mul16 (Mul16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Mul16 i (Mul16 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpMul16, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul16 (Const16 [c]) (Mul16 (Const16 [d]) x)) // result: (Mul16 (Const16 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpMul32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c * d) return true } break } // match: (Mul32 (Const32 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul32 (Const32 [-1]) x) // result: (Neg32 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg32) v.AddArg(x) return true } break } // match: (Mul32 n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (Lsh32x64 n (Const64 [log32(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { continue } v.reset(OpLsh32x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log32(c)) v.AddArg2(n, v0) return true } break } // match: (Mul32 n (Const32 [c])) // cond: t.IsSigned() && isPowerOfTwo32(-c) // result: (Neg32 (Lsh32x64 n (Const64 [log32(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo32(-c)) { continue } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpLsh32x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log32(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Add32 (Const32 [c*d]) (Mul32 (Const32 [c]) x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 || v_1.Type != t { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c * d) v1 := b.NewValue0(v.Pos, OpMul32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(c) v1.AddArg2(v2, x) v.AddArg2(v0, v1) return true } } break } // match: (Mul32 (Const32 [0]) _) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (Mul32 (Mul32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Mul32 i (Mul32 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpMul32, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul32 (Const32 [c]) (Mul32 (Const32 [d]) x)) // result: (Mul32 (Const32 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpMul32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mul32F (Const32F [c]) (Const32F [d])) // cond: c*d == c*d // result: (Const32F [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) if !(c*d == c*d) { continue } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c * d) return true } break } // match: (Mul32F x (Const32F [1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst32F || auxIntToFloat32(v_1.AuxInt) != 1 { continue } v.copyOf(x) return true } break } // match: (Mul32F x (Const32F [-1])) // result: (Neg32F x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst32F || auxIntToFloat32(v_1.AuxInt) != -1 { continue } v.reset(OpNeg32F) v.AddArg(x) return true } break } // match: (Mul32F x (Const32F [2])) // result: (Add32F x x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst32F || auxIntToFloat32(v_1.AuxInt) != 2 { continue } v.reset(OpAdd32F) v.AddArg2(x, x) return true } break } return false } func rewriteValuegeneric_OpMul64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c * d) return true } break } // match: (Mul64 (Const64 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul64 (Const64 [-1]) x) // result: (Neg64 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg64) v.AddArg(x) return true } break } // match: (Mul64 n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (Lsh64x64 n (Const64 [log64(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpLsh64x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(n, v0) return true } break } // match: (Mul64 n (Const64 [c])) // cond: t.IsSigned() && isPowerOfTwo64(-c) // result: (Neg64 (Lsh64x64 n (Const64 [log64(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo64(-c)) { continue } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpLsh64x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log64(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 || v_1.Type != t { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c * d) v1 := b.NewValue0(v.Pos, OpMul64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(c) v1.AddArg2(v2, x) v.AddArg2(v0, v1) return true } } break } // match: (Mul64 (Const64 [0]) _) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (Mul64 (Mul64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Mul64 i (Mul64 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpMul64, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul64 (Const64 [c]) (Mul64 (Const64 [d]) x)) // result: (Mul64 (Const64 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpMul64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mul64F (Const64F [c]) (Const64F [d])) // cond: c*d == c*d // result: (Const64F [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) if !(c*d == c*d) { continue } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c * d) return true } break } // match: (Mul64F x (Const64F [1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst64F || auxIntToFloat64(v_1.AuxInt) != 1 { continue } v.copyOf(x) return true } break } // match: (Mul64F x (Const64F [-1])) // result: (Neg64F x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst64F || auxIntToFloat64(v_1.AuxInt) != -1 { continue } v.reset(OpNeg64F) v.AddArg(x) return true } break } // match: (Mul64F x (Const64F [2])) // result: (Add64F x x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst64F || auxIntToFloat64(v_1.AuxInt) != 2 { continue } v.reset(OpAdd64F) v.AddArg2(x, x) return true } break } return false } func rewriteValuegeneric_OpMul8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c * d) return true } break } // match: (Mul8 (Const8 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul8 (Const8 [-1]) x) // result: (Neg8 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg8) v.AddArg(x) return true } break } // match: (Mul8 n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (Lsh8x64 n (Const64 [log8(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { continue } v.reset(OpLsh8x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log8(c)) v.AddArg2(n, v0) return true } break } // match: (Mul8 n (Const8 [c])) // cond: t.IsSigned() && isPowerOfTwo8(-c) // result: (Neg8 (Lsh8x64 n (Const64 [log8(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo8(-c)) { continue } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log8(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul8 (Const8 [0]) _) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (Mul8 (Mul8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Mul8 i (Mul8 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpMul8, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul8 (Const8 [c]) (Mul8 (Const8 [d]) x)) // result: (Mul8 (Const8 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpNeg16(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg16 (Const16 [c])) // result: (Const16 [-c]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-c) return true } // match: (Neg16 (Sub16 x y)) // result: (Sub16 y x) for { if v_0.Op != OpSub16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub16) v.AddArg2(y, x) return true } // match: (Neg16 (Neg16 x)) // result: x for { if v_0.Op != OpNeg16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg16 (Com16 x)) // result: (Add16 (Const16 [1]) x) for { t := v.Type if v_0.Op != OpCom16 { break } x := v_0.Args[0] v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeg32(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg32 (Const32 [c])) // result: (Const32 [-c]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-c) return true } // match: (Neg32 (Sub32 x y)) // result: (Sub32 y x) for { if v_0.Op != OpSub32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub32) v.AddArg2(y, x) return true } // match: (Neg32 (Neg32 x)) // result: x for { if v_0.Op != OpNeg32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg32 (Com32 x)) // result: (Add32 (Const32 [1]) x) for { t := v.Type if v_0.Op != OpCom32 { break } x := v_0.Args[0] v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeg32F(v *Value) bool { v_0 := v.Args[0] // match: (Neg32F (Const32F [c])) // cond: c != 0 // result: (Const32F [-c]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if !(c != 0) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(-c) return true } return false } func rewriteValuegeneric_OpNeg64(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg64 (Const64 [c])) // result: (Const64 [-c]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-c) return true } // match: (Neg64 (Sub64 x y)) // result: (Sub64 y x) for { if v_0.Op != OpSub64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub64) v.AddArg2(y, x) return true } // match: (Neg64 (Neg64 x)) // result: x for { if v_0.Op != OpNeg64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg64 (Com64 x)) // result: (Add64 (Const64 [1]) x) for { t := v.Type if v_0.Op != OpCom64 { break } x := v_0.Args[0] v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeg64F(v *Value) bool { v_0 := v.Args[0] // match: (Neg64F (Const64F [c])) // cond: c != 0 // result: (Const64F [-c]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if !(c != 0) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(-c) return true } return false } func rewriteValuegeneric_OpNeg8(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg8 (Const8 [c])) // result: (Const8 [-c]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-c) return true } // match: (Neg8 (Sub8 x y)) // result: (Sub8 y x) for { if v_0.Op != OpSub8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub8) v.AddArg2(y, x) return true } // match: (Neg8 (Neg8 x)) // result: x for { if v_0.Op != OpNeg8 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg8 (Com8 x)) // result: (Add8 (Const8 [1]) x) for { t := v.Type if v_0.Op != OpCom8 { break } x := v_0.Args[0] v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq16 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Neq16 (Const16 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq16 (Const16 [c]) (Const16 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Neq16 (And16 n (Const16 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh16x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh16x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd16 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh16Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh16x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 15 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 15 && kbar == 16-k) { continue } v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(1< x (Const16 [y])) (Const16 [y])) // cond: oneBit16(y) // result: (Eq16 (And16 x (Const16 [y])) (Const16 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst16 || v_0_1.Type != t { continue } y := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || v_1.Type != t || auxIntToInt16(v_1.AuxInt) != y || !(oneBit16(y)) { continue } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq32 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Neq32 (Const32 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Neq32 (And32 n (Const32 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh32x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd32 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh32Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh32x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 31 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 31 && kbar == 32-k) { continue } v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(1< x (Const32 [y])) (Const32 [y])) // cond: oneBit32(y) // result: (Eq32 (And32 x (Const32 [y])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst32 || v_0_1.Type != t { continue } y := auxIntToInt32(v_0_1.AuxInt) if v_1.Op != OpConst32 || v_1.Type != t || auxIntToInt32(v_1.AuxInt) != y || !(oneBit32(y)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Neq32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } return false } func rewriteValuegeneric_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq64 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Neq64 (Const64 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Neq64 (And64 n (Const64 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh64x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd64 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh64Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh64x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 63 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 63 && kbar == 64-k) { continue } v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(1< x (Const64 [y])) (Const64 [y])) // cond: oneBit64(y) // result: (Eq64 (And64 x (Const64 [y])) (Const64 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst64 || v_0_1.Type != t { continue } y := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 || v_1.Type != t || auxIntToInt64(v_1.AuxInt) != y || !(oneBit64(y)) { continue } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Neq64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } return false } func rewriteValuegeneric_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq8 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Neq8 (Const8 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Neq8 (And8 n (Const8 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh8x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh8x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd8 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh8Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh8x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 7 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 7 && kbar == 8-k) { continue } v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(1< x (Const8 [y])) (Const8 [y])) // cond: oneBit8(y) // result: (Eq8 (And8 x (Const8 [y])) (Const8 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst8 || v_0_1.Type != t { continue } y := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || v_1.Type != t || auxIntToInt8(v_1.AuxInt) != y || !(oneBit8(y)) { continue } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (NeqB (ConstBool [c]) (ConstBool [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool { continue } c := auxIntToBool(v_0.AuxInt) if v_1.Op != OpConstBool { continue } d := auxIntToBool(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (NeqB (ConstBool [false]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != false { continue } x := v_1 v.copyOf(x) return true } break } // match: (NeqB (ConstBool [true]) x) // result: (Not x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != true { continue } x := v_1 v.reset(OpNot) v.AddArg(x) return true } break } // match: (NeqB (Not x) (Not y)) // result: (NeqB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpNot { continue } x := v_0.Args[0] if v_1.Op != OpNot { continue } y := v_1.Args[0] v.reset(OpNeqB) v.AddArg2(x, y) return true } break } return false } func rewriteValuegeneric_OpNeqInter(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (NeqInter x y) // result: (NeqPtr (ITab x) (ITab y)) for { x := v_0 y := v_1 v.reset(OpNeqPtr) v0 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (NeqPtr x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (NeqPtr (Addr {x} _) (Addr {y} _)) // result: (ConstBool [x != y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y) return true } break } // match: (NeqPtr (Addr {x} _) (OffPtr [o] (Addr {y} _))) // result: (ConstBool [x != y || o != 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o != 0) return true } break } // match: (NeqPtr (OffPtr [o1] (Addr {x} _)) (OffPtr [o2] (Addr {y} _))) // result: (ConstBool [x != y || o1 != o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o1 != o2) return true } break } // match: (NeqPtr (LocalAddr {x} _ _) (LocalAddr {y} _ _)) // result: (ConstBool [x != y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpLocalAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y) return true } break } // match: (NeqPtr (LocalAddr {x} _ _) (OffPtr [o] (LocalAddr {y} _ _))) // result: (ConstBool [x != y || o != 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o != 0) return true } break } // match: (NeqPtr (OffPtr [o1] (LocalAddr {x} _ _)) (OffPtr [o2] (LocalAddr {y} _ _))) // result: (ConstBool [x != y || o1 != o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o1 != o2) return true } break } // match: (NeqPtr (OffPtr [o1] p1) p2) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 != 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 != 0) return true } break } // match: (NeqPtr (OffPtr [o1] p1) (OffPtr [o2] p2)) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 != o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 != o2) return true } break } // match: (NeqPtr (Const32 [c]) (Const32 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (NeqPtr (Const64 [c]) (Const64 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (NeqPtr (LocalAddr _ _) (Addr _)) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (OffPtr (LocalAddr _ _)) (Addr _)) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (LocalAddr _ _) (OffPtr (Addr _))) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (OffPtr (LocalAddr _ _)) (OffPtr (Addr _))) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (AddPtr p1 o1) p2) // cond: isSamePtr(p1, p2) // result: (IsNonNil o1) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddPtr { continue } o1 := v_0.Args[1] p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpIsNonNil) v.AddArg(o1) return true } break } // match: (NeqPtr (Const32 [0]) p) // result: (IsNonNil p) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpIsNonNil) v.AddArg(p) return true } break } // match: (NeqPtr (Const64 [0]) p) // result: (IsNonNil p) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpIsNonNil) v.AddArg(p) return true } break } // match: (NeqPtr (ConstNil) p) // result: (IsNonNil p) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstNil { continue } p := v_1 v.reset(OpIsNonNil) v.AddArg(p) return true } break } return false } func rewriteValuegeneric_OpNeqSlice(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (NeqSlice x y) // result: (NeqPtr (SlicePtr x) (SlicePtr y)) for { x := v_0 y := v_1 v.reset(OpNeqPtr) v0 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpNilCheck(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (NilCheck (GetG mem) mem) // result: mem for { if v_0.Op != OpGetG { break } mem := v_0.Args[0] if mem != v_1 { break } v.copyOf(mem) return true } // match: (NilCheck (SelectN [0] call:(StaticLECall _ _)) _) // cond: isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check") // result: (Invalid) for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { break } call := v_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 || !(isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check")) { break } v.reset(OpInvalid) return true } // match: (NilCheck (OffPtr (SelectN [0] call:(StaticLECall _ _))) _) // cond: isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check") // result: (Invalid) for { if v_0.Op != OpOffPtr { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpSelectN || auxIntToInt64(v_0_0.AuxInt) != 0 { break } call := v_0_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 || !(isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check")) { break } v.reset(OpInvalid) return true } return false } func rewriteValuegeneric_OpNot(v *Value) bool { v_0 := v.Args[0] // match: (Not (ConstBool [c])) // result: (ConstBool [!c]) for { if v_0.Op != OpConstBool { break } c := auxIntToBool(v_0.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(!c) return true } // match: (Not (Eq64 x y)) // result: (Neq64 x y) for { if v_0.Op != OpEq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq64) v.AddArg2(x, y) return true } // match: (Not (Eq32 x y)) // result: (Neq32 x y) for { if v_0.Op != OpEq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq32) v.AddArg2(x, y) return true } // match: (Not (Eq16 x y)) // result: (Neq16 x y) for { if v_0.Op != OpEq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq16) v.AddArg2(x, y) return true } // match: (Not (Eq8 x y)) // result: (Neq8 x y) for { if v_0.Op != OpEq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq8) v.AddArg2(x, y) return true } // match: (Not (EqB x y)) // result: (NeqB x y) for { if v_0.Op != OpEqB { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeqB) v.AddArg2(x, y) return true } // match: (Not (EqPtr x y)) // result: (NeqPtr x y) for { if v_0.Op != OpEqPtr { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeqPtr) v.AddArg2(x, y) return true } // match: (Not (Eq64F x y)) // result: (Neq64F x y) for { if v_0.Op != OpEq64F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq64F) v.AddArg2(x, y) return true } // match: (Not (Eq32F x y)) // result: (Neq32F x y) for { if v_0.Op != OpEq32F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq32F) v.AddArg2(x, y) return true } // match: (Not (Neq64 x y)) // result: (Eq64 x y) for { if v_0.Op != OpNeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq64) v.AddArg2(x, y) return true } // match: (Not (Neq32 x y)) // result: (Eq32 x y) for { if v_0.Op != OpNeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq32) v.AddArg2(x, y) return true } // match: (Not (Neq16 x y)) // result: (Eq16 x y) for { if v_0.Op != OpNeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq16) v.AddArg2(x, y) return true } // match: (Not (Neq8 x y)) // result: (Eq8 x y) for { if v_0.Op != OpNeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq8) v.AddArg2(x, y) return true } // match: (Not (NeqB x y)) // result: (EqB x y) for { if v_0.Op != OpNeqB { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEqB) v.AddArg2(x, y) return true } // match: (Not (NeqPtr x y)) // result: (EqPtr x y) for { if v_0.Op != OpNeqPtr { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEqPtr) v.AddArg2(x, y) return true } // match: (Not (Neq64F x y)) // result: (Eq64F x y) for { if v_0.Op != OpNeq64F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq64F) v.AddArg2(x, y) return true } // match: (Not (Neq32F x y)) // result: (Eq32F x y) for { if v_0.Op != OpNeq32F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq32F) v.AddArg2(x, y) return true } // match: (Not (Less64 x y)) // result: (Leq64 y x) for { if v_0.Op != OpLess64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq64) v.AddArg2(y, x) return true } // match: (Not (Less32 x y)) // result: (Leq32 y x) for { if v_0.Op != OpLess32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq32) v.AddArg2(y, x) return true } // match: (Not (Less16 x y)) // result: (Leq16 y x) for { if v_0.Op != OpLess16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq16) v.AddArg2(y, x) return true } // match: (Not (Less8 x y)) // result: (Leq8 y x) for { if v_0.Op != OpLess8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq8) v.AddArg2(y, x) return true } // match: (Not (Less64U x y)) // result: (Leq64U y x) for { if v_0.Op != OpLess64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq64U) v.AddArg2(y, x) return true } // match: (Not (Less32U x y)) // result: (Leq32U y x) for { if v_0.Op != OpLess32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq32U) v.AddArg2(y, x) return true } // match: (Not (Less16U x y)) // result: (Leq16U y x) for { if v_0.Op != OpLess16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq16U) v.AddArg2(y, x) return true } // match: (Not (Less8U x y)) // result: (Leq8U y x) for { if v_0.Op != OpLess8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq8U) v.AddArg2(y, x) return true } // match: (Not (Leq64 x y)) // result: (Less64 y x) for { if v_0.Op != OpLeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess64) v.AddArg2(y, x) return true } // match: (Not (Leq32 x y)) // result: (Less32 y x) for { if v_0.Op != OpLeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess32) v.AddArg2(y, x) return true } // match: (Not (Leq16 x y)) // result: (Less16 y x) for { if v_0.Op != OpLeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess16) v.AddArg2(y, x) return true } // match: (Not (Leq8 x y)) // result: (Less8 y x) for { if v_0.Op != OpLeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess8) v.AddArg2(y, x) return true } // match: (Not (Leq64U x y)) // result: (Less64U y x) for { if v_0.Op != OpLeq64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess64U) v.AddArg2(y, x) return true } // match: (Not (Leq32U x y)) // result: (Less32U y x) for { if v_0.Op != OpLeq32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess32U) v.AddArg2(y, x) return true } // match: (Not (Leq16U x y)) // result: (Less16U y x) for { if v_0.Op != OpLeq16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess16U) v.AddArg2(y, x) return true } // match: (Not (Leq8U x y)) // result: (Less8U y x) for { if v_0.Op != OpLeq8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess8U) v.AddArg2(y, x) return true } return false } func rewriteValuegeneric_OpOffPtr(v *Value) bool { v_0 := v.Args[0] // match: (OffPtr (OffPtr p [y]) [x]) // result: (OffPtr p [x+y]) for { x := auxIntToInt64(v.AuxInt) if v_0.Op != OpOffPtr { break } y := auxIntToInt64(v_0.AuxInt) p := v_0.Args[0] v.reset(OpOffPtr) v.AuxInt = int64ToAuxInt(x + y) v.AddArg(p) return true } // match: (OffPtr p [0]) // cond: v.Type.Compare(p.Type) == types.CMPeq // result: p for { if auxIntToInt64(v.AuxInt) != 0 { break } p := v_0 if !(v.Type.Compare(p.Type) == types.CMPeq) { break } v.copyOf(p) return true } return false } func rewriteValuegeneric_OpOr16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Or16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c | d) return true } break } // match: (Or16 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or16 (Const16 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or16 (Const16 [-1]) _) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Or16 (Com16 x) x) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Or16 x (Or16 x y)) // result: (Or16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr16) v.AddArg2(x, y) return true } } break } // match: (Or16 (And16 x (Const16 [c2])) (Const16 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or16 (Const16 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst16 { continue } c2 := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 { continue } t := v_1.Type c1 := auxIntToInt16(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or16 (Or16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Or16 i (Or16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpOr16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or16 (Const16 [c]) (Or16 (Const16 [d]) x)) // result: (Or16 (Const16 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpOr16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } // match: (Or16 (Lsh16x64 x z:(Const64 [c])) (Rsh16Ux64 x (Const64 [d]))) // cond: c < 16 && d == 16-c && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh16x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh16Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 16 && d == 16-c && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Or16 left:(Lsh16x64 x y) right:(Rsh16Ux64 x (Sub64 (Const64 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Or16 left:(Lsh16x32 x y) right:(Rsh16Ux32 x (Sub32 (Const32 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Or16 left:(Lsh16x16 x y) right:(Rsh16Ux16 x (Sub16 (Const16 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Or16 left:(Lsh16x8 x y) right:(Rsh16Ux8 x (Sub8 (Const8 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Or16 right:(Rsh16Ux64 x y) left:(Lsh16x64 x z:(Sub64 (Const64 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Or16 right:(Rsh16Ux32 x y) left:(Lsh16x32 x z:(Sub32 (Const32 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Or16 right:(Rsh16Ux16 x y) left:(Lsh16x16 x z:(Sub16 (Const16 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Or16 right:(Rsh16Ux8 x y) left:(Lsh16x8 x z:(Sub8 (Const8 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpOr32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Or32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c | d) return true } break } // match: (Or32 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or32 (Const32 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or32 (Const32 [-1]) _) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Or32 (Com32 x) x) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Or32 x (Or32 x y)) // result: (Or32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr32) v.AddArg2(x, y) return true } } break } // match: (Or32 (And32 x (Const32 [c2])) (Const32 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or32 (Const32 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst32 { continue } c2 := auxIntToInt32(v_0_1.AuxInt) if v_1.Op != OpConst32 { continue } t := v_1.Type c1 := auxIntToInt32(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or32 (Or32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Or32 i (Or32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpOr32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or32 (Const32 [c]) (Or32 (Const32 [d]) x)) // result: (Or32 (Const32 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpOr32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } // match: (Or32 (Lsh32x64 x z:(Const64 [c])) (Rsh32Ux64 x (Const64 [d]))) // cond: c < 32 && d == 32-c && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh32x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh32Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 32 && d == 32-c && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Or32 left:(Lsh32x64 x y) right:(Rsh32Ux64 x (Sub64 (Const64 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Or32 left:(Lsh32x32 x y) right:(Rsh32Ux32 x (Sub32 (Const32 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Or32 left:(Lsh32x16 x y) right:(Rsh32Ux16 x (Sub16 (Const16 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Or32 left:(Lsh32x8 x y) right:(Rsh32Ux8 x (Sub8 (Const8 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Or32 right:(Rsh32Ux64 x y) left:(Lsh32x64 x z:(Sub64 (Const64 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Or32 right:(Rsh32Ux32 x y) left:(Lsh32x32 x z:(Sub32 (Const32 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Or32 right:(Rsh32Ux16 x y) left:(Lsh32x16 x z:(Sub16 (Const16 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Or32 right:(Rsh32Ux8 x y) left:(Lsh32x8 x z:(Sub8 (Const8 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpOr64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Or64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c | d) return true } break } // match: (Or64 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or64 (Const64 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or64 (Const64 [-1]) _) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Or64 (Com64 x) x) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Or64 x (Or64 x y)) // result: (Or64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr64) v.AddArg2(x, y) return true } } break } // match: (Or64 (And64 x (Const64 [c2])) (Const64 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or64 (Const64 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst64 { continue } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { continue } t := v_1.Type c1 := auxIntToInt64(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or64 (Or64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Or64 i (Or64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpOr64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or64 (Const64 [c]) (Or64 (Const64 [d]) x)) // result: (Or64 (Const64 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpOr64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } // match: (Or64 (Lsh64x64 x z:(Const64 [c])) (Rsh64Ux64 x (Const64 [d]))) // cond: c < 64 && d == 64-c && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh64x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh64Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 64 && d == 64-c && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Or64 left:(Lsh64x64 x y) right:(Rsh64Ux64 x (Sub64 (Const64 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Or64 left:(Lsh64x32 x y) right:(Rsh64Ux32 x (Sub32 (Const32 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Or64 left:(Lsh64x16 x y) right:(Rsh64Ux16 x (Sub16 (Const16 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Or64 left:(Lsh64x8 x y) right:(Rsh64Ux8 x (Sub8 (Const8 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Or64 right:(Rsh64Ux64 x y) left:(Lsh64x64 x z:(Sub64 (Const64 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Or64 right:(Rsh64Ux32 x y) left:(Lsh64x32 x z:(Sub32 (Const32 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Or64 right:(Rsh64Ux16 x y) left:(Lsh64x16 x z:(Sub16 (Const16 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Or64 right:(Rsh64Ux8 x y) left:(Lsh64x8 x z:(Sub8 (Const8 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpOr8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Or8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c | d) return true } break } // match: (Or8 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or8 (Const8 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or8 (Const8 [-1]) _) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Or8 (Com8 x) x) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Or8 x (Or8 x y)) // result: (Or8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr8) v.AddArg2(x, y) return true } } break } // match: (Or8 (And8 x (Const8 [c2])) (Const8 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or8 (Const8 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst8 { continue } c2 := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 { continue } t := v_1.Type c1 := auxIntToInt8(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or8 (Or8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Or8 i (Or8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpOr8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or8 (Const8 [c]) (Or8 (Const8 [d]) x)) // result: (Or8 (Const8 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpOr8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } // match: (Or8 (Lsh8x64 x z:(Const64 [c])) (Rsh8Ux64 x (Const64 [d]))) // cond: c < 8 && d == 8-c && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh8x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh8Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 8 && d == 8-c && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Or8 left:(Lsh8x64 x y) right:(Rsh8Ux64 x (Sub64 (Const64 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Or8 left:(Lsh8x32 x y) right:(Rsh8Ux32 x (Sub32 (Const32 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Or8 left:(Lsh8x16 x y) right:(Rsh8Ux16 x (Sub16 (Const16 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Or8 left:(Lsh8x8 x y) right:(Rsh8Ux8 x (Sub8 (Const8 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Or8 right:(Rsh8Ux64 x y) left:(Lsh8x64 x z:(Sub64 (Const64 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Or8 right:(Rsh8Ux32 x y) left:(Lsh8x32 x z:(Sub32 (Const32 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Or8 right:(Rsh8Ux16 x y) left:(Lsh8x16 x z:(Sub16 (Const16 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Or8 right:(Rsh8Ux8 x y) left:(Lsh8x8 x z:(Sub8 (Const8 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpOrB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (OrB (Less64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: c >= d // result: (Less64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: c >= d // result: (Leq64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: c >= d // result: (Less32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: c >= d // result: (Leq32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: c >= d // result: (Less16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: c >= d // result: (Leq16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: c >= d // result: (Less8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: c >= d // result: (Leq8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d) // result: (Less64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d) // result: (Leq64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d) // result: (Less32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d) // result: (Leq32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d) // result: (Less16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d) // result: (Leq16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d) // result: (Less8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d) // result: (Leq8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d) // result: (Less64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d) // result: (Leq64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d) // result: (Less32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d) // result: (Leq32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d) // result: (Less16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d) // result: (Leq16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d) // result: (Less8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d) // result: (Leq8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } return false } func rewriteValuegeneric_OpPhi(v *Value) bool { // match: (Phi (Const8 [c]) (Const8 [c])) // result: (Const8 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != c { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c) return true } // match: (Phi (Const16 [c]) (Const16 [c])) // result: (Const16 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != c { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c) return true } // match: (Phi (Const32 [c]) (Const32 [c])) // result: (Const32 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != c { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c) return true } // match: (Phi (Const64 [c]) (Const64 [c])) // result: (Const64 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != c { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValuegeneric_OpPtrIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (PtrIndex ptr idx) // cond: config.PtrSize == 4 && is32Bit(t.Elem().Size()) // result: (AddPtr ptr (Mul32 idx (Const32 [int32(t.Elem().Size())]))) for { t := v.Type ptr := v_0 idx := v_1 if !(config.PtrSize == 4 && is32Bit(t.Elem().Size())) { break } v.reset(OpAddPtr) v0 := b.NewValue0(v.Pos, OpMul32, typ.Int) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = int32ToAuxInt(int32(t.Elem().Size())) v0.AddArg2(idx, v1) v.AddArg2(ptr, v0) return true } // match: (PtrIndex ptr idx) // cond: config.PtrSize == 8 // result: (AddPtr ptr (Mul64 idx (Const64 [t.Elem().Size()]))) for { t := v.Type ptr := v_0 idx := v_1 if !(config.PtrSize == 8) { break } v.reset(OpAddPtr) v0 := b.NewValue0(v.Pos, OpMul64, typ.Int) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = int64ToAuxInt(t.Elem().Size()) v0.AddArg2(idx, v1) v.AddArg2(ptr, v0) return true } return false } func rewriteValuegeneric_OpRotateLeft16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (RotateLeft16 x (Const16 [c])) // cond: c%16 == 0 // result: x for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(c%16 == 0) { break } v.copyOf(x) return true } // match: (RotateLeft16 x (And64 y (Const64 [c]))) // cond: c&15 == 15 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (And32 y (Const32 [c]))) // cond: c&15 == 15 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (And16 y (Const16 [c]))) // cond: c&15 == 15 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (And8 y (Const8 [c]))) // cond: c&15 == 15 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (Neg64 (And64 y (Const64 [c])))) // cond: c&15 == 15 // result: (RotateLeft16 x (Neg64 y)) for { x := v_0 if v_1.Op != OpNeg64 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft16 x (Neg32 (And32 y (Const32 [c])))) // cond: c&15 == 15 // result: (RotateLeft16 x (Neg32 y)) for { x := v_0 if v_1.Op != OpNeg32 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft16 x (Neg16 (And16 y (Const16 [c])))) // cond: c&15 == 15 // result: (RotateLeft16 x (Neg16 y)) for { x := v_0 if v_1.Op != OpNeg16 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd16 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft16 x (Neg8 (And8 y (Const8 [c])))) // cond: c&15 == 15 // result: (RotateLeft16 x (Neg8 y)) for { x := v_0 if v_1.Op != OpNeg8 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd8 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft16 x (Add64 y (Const64 [c]))) // cond: c&15 == 0 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&15 == 0) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (Add32 y (Const32 [c]))) // cond: c&15 == 0 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&15 == 0) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (Add16 y (Const16 [c]))) // cond: c&15 == 0 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&15 == 0) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (Add8 y (Const8 [c]))) // cond: c&15 == 0 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&15 == 0) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (Sub64 (Const64 [c]) y)) // cond: c&15 == 0 // result: (RotateLeft16 x (Neg64 y)) for { x := v_0 if v_1.Op != OpSub64 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := auxIntToInt64(v_1_0.AuxInt) if !(c&15 == 0) { break } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft16 x (Sub32 (Const32 [c]) y)) // cond: c&15 == 0 // result: (RotateLeft16 x (Neg32 y)) for { x := v_0 if v_1.Op != OpSub32 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := auxIntToInt32(v_1_0.AuxInt) if !(c&15 == 0) { break } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft16 x (Sub16 (Const16 [c]) y)) // cond: c&15 == 0 // result: (RotateLeft16 x (Neg16 y)) for { x := v_0 if v_1.Op != OpSub16 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := auxIntToInt16(v_1_0.AuxInt) if !(c&15 == 0) { break } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft16 x (Sub8 (Const8 [c]) y)) // cond: c&15 == 0 // result: (RotateLeft16 x (Neg8 y)) for { x := v_0 if v_1.Op != OpSub8 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := auxIntToInt8(v_1_0.AuxInt) if !(c&15 == 0) { break } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft16 x (Const64 [c])) // cond: config.PtrSize == 4 // result: (RotateLeft16 x (Const32 [int32(c)])) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRotateLeft32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (RotateLeft32 x (Const32 [c])) // cond: c%32 == 0 // result: x for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(c%32 == 0) { break } v.copyOf(x) return true } // match: (RotateLeft32 x (And64 y (Const64 [c]))) // cond: c&31 == 31 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (And32 y (Const32 [c]))) // cond: c&31 == 31 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (And16 y (Const16 [c]))) // cond: c&31 == 31 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (And8 y (Const8 [c]))) // cond: c&31 == 31 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (Neg64 (And64 y (Const64 [c])))) // cond: c&31 == 31 // result: (RotateLeft32 x (Neg64 y)) for { x := v_0 if v_1.Op != OpNeg64 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft32 x (Neg32 (And32 y (Const32 [c])))) // cond: c&31 == 31 // result: (RotateLeft32 x (Neg32 y)) for { x := v_0 if v_1.Op != OpNeg32 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft32 x (Neg16 (And16 y (Const16 [c])))) // cond: c&31 == 31 // result: (RotateLeft32 x (Neg16 y)) for { x := v_0 if v_1.Op != OpNeg16 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd16 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft32 x (Neg8 (And8 y (Const8 [c])))) // cond: c&31 == 31 // result: (RotateLeft32 x (Neg8 y)) for { x := v_0 if v_1.Op != OpNeg8 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd8 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft32 x (Add64 y (Const64 [c]))) // cond: c&31 == 0 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&31 == 0) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (Add32 y (Const32 [c]))) // cond: c&31 == 0 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&31 == 0) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (Add16 y (Const16 [c]))) // cond: c&31 == 0 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&31 == 0) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (Add8 y (Const8 [c]))) // cond: c&31 == 0 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&31 == 0) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (Sub64 (Const64 [c]) y)) // cond: c&31 == 0 // result: (RotateLeft32 x (Neg64 y)) for { x := v_0 if v_1.Op != OpSub64 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := auxIntToInt64(v_1_0.AuxInt) if !(c&31 == 0) { break } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft32 x (Sub32 (Const32 [c]) y)) // cond: c&31 == 0 // result: (RotateLeft32 x (Neg32 y)) for { x := v_0 if v_1.Op != OpSub32 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := auxIntToInt32(v_1_0.AuxInt) if !(c&31 == 0) { break } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft32 x (Sub16 (Const16 [c]) y)) // cond: c&31 == 0 // result: (RotateLeft32 x (Neg16 y)) for { x := v_0 if v_1.Op != OpSub16 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := auxIntToInt16(v_1_0.AuxInt) if !(c&31 == 0) { break } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft32 x (Sub8 (Const8 [c]) y)) // cond: c&31 == 0 // result: (RotateLeft32 x (Neg8 y)) for { x := v_0 if v_1.Op != OpSub8 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := auxIntToInt8(v_1_0.AuxInt) if !(c&31 == 0) { break } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft32 x (Const64 [c])) // cond: config.PtrSize == 4 // result: (RotateLeft32 x (Const32 [int32(c)])) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRotateLeft64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (RotateLeft64 x (Const64 [c])) // cond: c%64 == 0 // result: x for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c%64 == 0) { break } v.copyOf(x) return true } // match: (RotateLeft64 x (And64 y (Const64 [c]))) // cond: c&63 == 63 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (And32 y (Const32 [c]))) // cond: c&63 == 63 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (And16 y (Const16 [c]))) // cond: c&63 == 63 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (And8 y (Const8 [c]))) // cond: c&63 == 63 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (Neg64 (And64 y (Const64 [c])))) // cond: c&63 == 63 // result: (RotateLeft64 x (Neg64 y)) for { x := v_0 if v_1.Op != OpNeg64 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft64 x (Neg32 (And32 y (Const32 [c])))) // cond: c&63 == 63 // result: (RotateLeft64 x (Neg32 y)) for { x := v_0 if v_1.Op != OpNeg32 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft64 x (Neg16 (And16 y (Const16 [c])))) // cond: c&63 == 63 // result: (RotateLeft64 x (Neg16 y)) for { x := v_0 if v_1.Op != OpNeg16 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd16 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft64 x (Neg8 (And8 y (Const8 [c])))) // cond: c&63 == 63 // result: (RotateLeft64 x (Neg8 y)) for { x := v_0 if v_1.Op != OpNeg8 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd8 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft64 x (Add64 y (Const64 [c]))) // cond: c&63 == 0 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&63 == 0) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (Add32 y (Const32 [c]))) // cond: c&63 == 0 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&63 == 0) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (Add16 y (Const16 [c]))) // cond: c&63 == 0 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&63 == 0) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (Add8 y (Const8 [c]))) // cond: c&63 == 0 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&63 == 0) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (Sub64 (Const64 [c]) y)) // cond: c&63 == 0 // result: (RotateLeft64 x (Neg64 y)) for { x := v_0 if v_1.Op != OpSub64 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := auxIntToInt64(v_1_0.AuxInt) if !(c&63 == 0) { break } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft64 x (Sub32 (Const32 [c]) y)) // cond: c&63 == 0 // result: (RotateLeft64 x (Neg32 y)) for { x := v_0 if v_1.Op != OpSub32 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := auxIntToInt32(v_1_0.AuxInt) if !(c&63 == 0) { break } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft64 x (Sub16 (Const16 [c]) y)) // cond: c&63 == 0 // result: (RotateLeft64 x (Neg16 y)) for { x := v_0 if v_1.Op != OpSub16 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := auxIntToInt16(v_1_0.AuxInt) if !(c&63 == 0) { break } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft64 x (Sub8 (Const8 [c]) y)) // cond: c&63 == 0 // result: (RotateLeft64 x (Neg8 y)) for { x := v_0 if v_1.Op != OpSub8 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := auxIntToInt8(v_1_0.AuxInt) if !(c&63 == 0) { break } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft64 x (Const64 [c])) // cond: config.PtrSize == 4 // result: (RotateLeft64 x (Const32 [int32(c)])) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRotateLeft8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (RotateLeft8 x (Const8 [c])) // cond: c%8 == 0 // result: x for { x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(c%8 == 0) { break } v.copyOf(x) return true } // match: (RotateLeft8 x (And64 y (Const64 [c]))) // cond: c&7 == 7 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (And32 y (Const32 [c]))) // cond: c&7 == 7 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (And16 y (Const16 [c]))) // cond: c&7 == 7 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (And8 y (Const8 [c]))) // cond: c&7 == 7 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (Neg64 (And64 y (Const64 [c])))) // cond: c&7 == 7 // result: (RotateLeft8 x (Neg64 y)) for { x := v_0 if v_1.Op != OpNeg64 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft8 x (Neg32 (And32 y (Const32 [c])))) // cond: c&7 == 7 // result: (RotateLeft8 x (Neg32 y)) for { x := v_0 if v_1.Op != OpNeg32 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft8 x (Neg16 (And16 y (Const16 [c])))) // cond: c&7 == 7 // result: (RotateLeft8 x (Neg16 y)) for { x := v_0 if v_1.Op != OpNeg16 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd16 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft8 x (Neg8 (And8 y (Const8 [c])))) // cond: c&7 == 7 // result: (RotateLeft8 x (Neg8 y)) for { x := v_0 if v_1.Op != OpNeg8 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd8 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft8 x (Add64 y (Const64 [c]))) // cond: c&7 == 0 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&7 == 0) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (Add32 y (Const32 [c]))) // cond: c&7 == 0 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&7 == 0) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (Add16 y (Const16 [c]))) // cond: c&7 == 0 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&7 == 0) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (Add8 y (Const8 [c]))) // cond: c&7 == 0 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&7 == 0) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (Sub64 (Const64 [c]) y)) // cond: c&7 == 0 // result: (RotateLeft8 x (Neg64 y)) for { x := v_0 if v_1.Op != OpSub64 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := auxIntToInt64(v_1_0.AuxInt) if !(c&7 == 0) { break } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft8 x (Sub32 (Const32 [c]) y)) // cond: c&7 == 0 // result: (RotateLeft8 x (Neg32 y)) for { x := v_0 if v_1.Op != OpSub32 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := auxIntToInt32(v_1_0.AuxInt) if !(c&7 == 0) { break } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft8 x (Sub16 (Const16 [c]) y)) // cond: c&7 == 0 // result: (RotateLeft8 x (Neg16 y)) for { x := v_0 if v_1.Op != OpSub16 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := auxIntToInt16(v_1_0.AuxInt) if !(c&7 == 0) { break } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft8 x (Sub8 (Const8 [c]) y)) // cond: c&7 == 0 // result: (RotateLeft8 x (Neg8 y)) for { x := v_0 if v_1.Op != OpSub8 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := auxIntToInt8(v_1_0.AuxInt) if !(c&7 == 0) { break } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft8 x (Const64 [c])) // cond: config.PtrSize == 4 // result: (RotateLeft8 x (Const32 [int32(c)])) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRound32F(v *Value) bool { v_0 := v.Args[0] // match: (Round32F x:(Const32F)) // result: x for { x := v_0 if x.Op != OpConst32F { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRound64F(v *Value) bool { v_0 := v.Args[0] // match: (Round64F x:(Const64F)) // result: x for { x := v_0 if x.Op != OpConst64F { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux16 x (Const16 [c])) // result: (Rsh16Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh16Ux16 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux32 x (Const32 [c])) // result: (Rsh16Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh16Ux32 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux64 (Const16 [c]) (Const64 [d])) // result: (Const16 [int16(uint16(c) >> uint64(d))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint16(c) >> uint64(d))) return true } // match: (Rsh16Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh16Ux64 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Rsh16Ux64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Rsh16Ux64 (Rsh16Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh16Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh16Ux64 (Rsh16x64 x _) (Const64 [15])) // result: (Rsh16Ux64 x (Const64 [15])) for { if v_0.Op != OpRsh16x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 15 { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(15) v.AddArg2(x, v0) return true } // match: (Rsh16Ux64 (Lsh16x64 (Rsh16Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh16Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh16Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } // match: (Rsh16Ux64 (Lsh16x64 x (Const64 [8])) (Const64 [8])) // result: (ZeroExt8to16 (Trunc16to8 x)) for { if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 8 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 8 { break } v.reset(OpZeroExt8to16) v0 := b.NewValue0(v.Pos, OpTrunc16to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux8 x (Const8 [c])) // result: (Rsh16Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh16Ux8 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x16 x (Const16 [c])) // result: (Rsh16x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh16x16 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x32 x (Const32 [c])) // result: (Rsh16x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh16x32 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x64 (Const16 [c]) (Const64 [d])) // result: (Const16 [c >> uint64(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c >> uint64(d)) return true } // match: (Rsh16x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh16x64 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Rsh16x64 (Rsh16x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh16x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh16x64 (Lsh16x64 x (Const64 [8])) (Const64 [8])) // result: (SignExt8to16 (Trunc16to8 x)) for { if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 8 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 8 { break } v.reset(OpSignExt8to16) v0 := b.NewValue0(v.Pos, OpTrunc16to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x8 x (Const8 [c])) // result: (Rsh16x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh16x8 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux16 x (Const16 [c])) // result: (Rsh32Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh32Ux16 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux32 x (Const32 [c])) // result: (Rsh32Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh32Ux32 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux64 (Const32 [c]) (Const64 [d])) // result: (Const32 [int32(uint32(c) >> uint64(d))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint32(c) >> uint64(d))) return true } // match: (Rsh32Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh32Ux64 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Rsh32Ux64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Rsh32Ux64 (Rsh32Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh32Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh32Ux64 (Rsh32x64 x _) (Const64 [31])) // result: (Rsh32Ux64 x (Const64 [31])) for { if v_0.Op != OpRsh32x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 31 { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(31) v.AddArg2(x, v0) return true } // match: (Rsh32Ux64 (Lsh32x64 (Rsh32Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh32Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } // match: (Rsh32Ux64 (Lsh32x64 x (Const64 [24])) (Const64 [24])) // result: (ZeroExt8to32 (Trunc32to8 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 24 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 24 { break } v.reset(OpZeroExt8to32) v0 := b.NewValue0(v.Pos, OpTrunc32to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh32Ux64 (Lsh32x64 x (Const64 [16])) (Const64 [16])) // result: (ZeroExt16to32 (Trunc32to16 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 16 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 16 { break } v.reset(OpZeroExt16to32) v0 := b.NewValue0(v.Pos, OpTrunc32to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux8 x (Const8 [c])) // result: (Rsh32Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh32Ux8 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x16 x (Const16 [c])) // result: (Rsh32x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh32x16 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x32 x (Const32 [c])) // result: (Rsh32x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh32x32 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x64 (Const32 [c]) (Const64 [d])) // result: (Const32 [c >> uint64(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c >> uint64(d)) return true } // match: (Rsh32x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh32x64 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Rsh32x64 (Rsh32x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh32x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh32x64 (Lsh32x64 x (Const64 [24])) (Const64 [24])) // result: (SignExt8to32 (Trunc32to8 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 24 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 24 { break } v.reset(OpSignExt8to32) v0 := b.NewValue0(v.Pos, OpTrunc32to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh32x64 (Lsh32x64 x (Const64 [16])) (Const64 [16])) // result: (SignExt16to32 (Trunc32to16 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 16 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 16 { break } v.reset(OpSignExt16to32) v0 := b.NewValue0(v.Pos, OpTrunc32to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x8 x (Const8 [c])) // result: (Rsh32x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh32x8 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux16 x (Const16 [c])) // result: (Rsh64Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh64Ux16 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux32 x (Const32 [c])) // result: (Rsh64Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh64Ux32 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux64 (Const64 [c]) (Const64 [d])) // result: (Const64 [int64(uint64(c) >> uint64(d))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) return true } // match: (Rsh64Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh64Ux64 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Rsh64Ux64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (Const64 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 64) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Rsh64Ux64 (Rsh64Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh64Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh64Ux64 (Rsh64x64 x _) (Const64 [63])) // result: (Rsh64Ux64 x (Const64 [63])) for { if v_0.Op != OpRsh64x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(63) v.AddArg2(x, v0) return true } // match: (Rsh64Ux64 (Lsh64x64 (Rsh64Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh64Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [56])) (Const64 [56])) // result: (ZeroExt8to64 (Trunc64to8 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 56 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 56 { break } v.reset(OpZeroExt8to64) v0 := b.NewValue0(v.Pos, OpTrunc64to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [48])) (Const64 [48])) // result: (ZeroExt16to64 (Trunc64to16 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 48 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 48 { break } v.reset(OpZeroExt16to64) v0 := b.NewValue0(v.Pos, OpTrunc64to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [32])) (Const64 [32])) // result: (ZeroExt32to64 (Trunc64to32 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 32 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 32 { break } v.reset(OpZeroExt32to64) v0 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux8 x (Const8 [c])) // result: (Rsh64Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh64Ux8 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x16 x (Const16 [c])) // result: (Rsh64x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh64x16 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x32 x (Const32 [c])) // result: (Rsh64x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh64x32 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c >> uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c >> uint64(d)) return true } // match: (Rsh64x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh64x64 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Rsh64x64 (Rsh64x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh64x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [56])) (Const64 [56])) // result: (SignExt8to64 (Trunc64to8 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 56 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 56 { break } v.reset(OpSignExt8to64) v0 := b.NewValue0(v.Pos, OpTrunc64to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [48])) (Const64 [48])) // result: (SignExt16to64 (Trunc64to16 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 48 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 48 { break } v.reset(OpSignExt16to64) v0 := b.NewValue0(v.Pos, OpTrunc64to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [32])) (Const64 [32])) // result: (SignExt32to64 (Trunc64to32 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 32 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 32 { break } v.reset(OpSignExt32to64) v0 := b.NewValue0(v.Pos, OpTrunc64to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x8 x (Const8 [c])) // result: (Rsh64x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh64x8 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux16 x (Const16 [c])) // result: (Rsh8Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh8Ux16 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux32 x (Const32 [c])) // result: (Rsh8Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh8Ux32 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux64 (Const8 [c]) (Const64 [d])) // result: (Const8 [int8(uint8(c) >> uint64(d))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(uint8(c) >> uint64(d))) return true } // match: (Rsh8Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh8Ux64 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Rsh8Ux64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Rsh8Ux64 (Rsh8Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh8Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh8Ux64 (Rsh8x64 x _) (Const64 [7] )) // result: (Rsh8Ux64 x (Const64 [7] )) for { if v_0.Op != OpRsh8x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 7 { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(7) v.AddArg2(x, v0) return true } // match: (Rsh8Ux64 (Lsh8x64 (Rsh8Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh8Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh8Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux8 x (Const8 [c])) // result: (Rsh8Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh8Ux8 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x16 x (Const16 [c])) // result: (Rsh8x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh8x16 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x32 x (Const32 [c])) // result: (Rsh8x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh8x32 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x64 (Const8 [c]) (Const64 [d])) // result: (Const8 [c >> uint64(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c >> uint64(d)) return true } // match: (Rsh8x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh8x64 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Rsh8x64 (Rsh8x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh8x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x8 x (Const8 [c])) // result: (Rsh8x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh8x8 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpSelect0(v *Value) bool { v_0 := v.Args[0] // match: (Select0 (Div128u (Const64 [0]) lo y)) // result: (Div64u lo y) for { if v_0.Op != OpDiv128u { break } y := v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { break } lo := v_0.Args[1] v.reset(OpDiv64u) v.AddArg2(lo, y) return true } // match: (Select0 (Mul32uover (Const32 [1]) x)) // result: x for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_0_1 v.copyOf(x) return true } break } // match: (Select0 (Mul64uover (Const64 [1]) x)) // result: x for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 1 { continue } x := v_0_1 v.copyOf(x) return true } break } // match: (Select0 (Mul64uover (Const64 [0]) x)) // result: (Const64 [0]) for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (Select0 (Mul32uover (Const32 [0]) x)) // result: (Const32 [0]) for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 0 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } return false } func rewriteValuegeneric_OpSelect1(v *Value) bool { v_0 := v.Args[0] // match: (Select1 (Div128u (Const64 [0]) lo y)) // result: (Mod64u lo y) for { if v_0.Op != OpDiv128u { break } y := v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { break } lo := v_0.Args[1] v.reset(OpMod64u) v.AddArg2(lo, y) return true } // match: (Select1 (Mul32uover (Const32 [1]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (Select1 (Mul64uover (Const64 [1]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 1 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (Select1 (Mul64uover (Const64 [0]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (Select1 (Mul32uover (Const32 [0]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 0 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } return false } func rewriteValuegeneric_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] (MakeResult x ___)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpMakeResult || len(v_0.Args) < 1 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (SelectN [1] (MakeResult x y ___)) // result: y for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpMakeResult || len(v_0.Args) < 2 { break } y := v_0.Args[1] v.copyOf(y) return true } // match: (SelectN [2] (MakeResult x y z ___)) // result: z for { if auxIntToInt64(v.AuxInt) != 2 || v_0.Op != OpMakeResult || len(v_0.Args) < 3 { break } z := v_0.Args[2] v.copyOf(z) return true } // match: (SelectN [0] call:(StaticCall {sym} s1:(Store _ (Const64 [sz]) s2:(Store _ src s3:(Store {t} _ dst mem))))) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call) // result: (Move {t.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpStore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpConst64 { break } sz := auxIntToInt64(s1_1.AuxInt) s2 := s1.Args[2] if s2.Op != OpStore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpStore { break } t := auxToType(s3.Aux) mem := s3.Args[2] dst := s3.Args[1] if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(t.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticCall {sym} s1:(Store _ (Const32 [sz]) s2:(Store _ src s3:(Store {t} _ dst mem))))) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call) // result: (Move {t.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpStore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpConst32 { break } sz := auxIntToInt32(s1_1.AuxInt) s2 := s1.Args[2] if s2.Op != OpStore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpStore { break } t := auxToType(s3.Aux) mem := s3.Args[2] dst := s3.Args[1] if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(t.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticCall {sym} dst src (Const64 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst64 { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticCall {sym} dst src (Const32 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst32 { break } sz := auxIntToInt32(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticLECall {sym} dst src (Const64 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst64 { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticLECall {sym} dst src (Const32 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst32 { break } sz := auxIntToInt32(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticLECall {sym} a x)) // cond: needRaceCleanup(sym, call) && clobber(call) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 2 { break } sym := auxToCall(call.Aux) x := call.Args[1] if !(needRaceCleanup(sym, call) && clobber(call)) { break } v.copyOf(x) return true } // match: (SelectN [0] call:(StaticLECall {sym} x)) // cond: needRaceCleanup(sym, call) && clobber(call) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) x := call.Args[0] if !(needRaceCleanup(sym, call) && clobber(call)) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt16to32(v *Value) bool { v_0 := v.Args[0] // match: (SignExt16to32 (Const16 [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } // match: (SignExt16to32 (Trunc32to16 x:(Rsh32x64 _ (Const64 [s])))) // cond: s >= 16 // result: x for { if v_0.Op != OpTrunc32to16 { break } x := v_0.Args[0] if x.Op != OpRsh32x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 16) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt16to64(v *Value) bool { v_0 := v.Args[0] // match: (SignExt16to64 (Const16 [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } // match: (SignExt16to64 (Trunc64to16 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 48 // result: x for { if v_0.Op != OpTrunc64to16 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 48) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt32to64(v *Value) bool { v_0 := v.Args[0] // match: (SignExt32to64 (Const32 [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } // match: (SignExt32to64 (Trunc64to32 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 32 // result: x for { if v_0.Op != OpTrunc64to32 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 32) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt8to16(v *Value) bool { v_0 := v.Args[0] // match: (SignExt8to16 (Const8 [c])) // result: (Const16 [int16(c)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(c)) return true } // match: (SignExt8to16 (Trunc16to8 x:(Rsh16x64 _ (Const64 [s])))) // cond: s >= 8 // result: x for { if v_0.Op != OpTrunc16to8 { break } x := v_0.Args[0] if x.Op != OpRsh16x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 8) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt8to32(v *Value) bool { v_0 := v.Args[0] // match: (SignExt8to32 (Const8 [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } // match: (SignExt8to32 (Trunc32to8 x:(Rsh32x64 _ (Const64 [s])))) // cond: s >= 24 // result: x for { if v_0.Op != OpTrunc32to8 { break } x := v_0.Args[0] if x.Op != OpRsh32x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 24) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt8to64(v *Value) bool { v_0 := v.Args[0] // match: (SignExt8to64 (Const8 [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } // match: (SignExt8to64 (Trunc64to8 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 56 // result: x for { if v_0.Op != OpTrunc64to8 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 56) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSliceCap(v *Value) bool { v_0 := v.Args[0] // match: (SliceCap (SliceMake _ _ (Const64 [c]))) // result: (Const64 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpConst64 { break } t := v_0_2.Type c := auxIntToInt64(v_0_2.AuxInt) v.reset(OpConst64) v.Type = t v.AuxInt = int64ToAuxInt(c) return true } // match: (SliceCap (SliceMake _ _ (Const32 [c]))) // result: (Const32 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpConst32 { break } t := v_0_2.Type c := auxIntToInt32(v_0_2.AuxInt) v.reset(OpConst32) v.Type = t v.AuxInt = int32ToAuxInt(c) return true } // match: (SliceCap (SliceMake _ _ (SliceCap x))) // result: (SliceCap x) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpSliceCap { break } x := v_0_2.Args[0] v.reset(OpSliceCap) v.AddArg(x) return true } // match: (SliceCap (SliceMake _ _ (SliceLen x))) // result: (SliceLen x) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpSliceLen { break } x := v_0_2.Args[0] v.reset(OpSliceLen) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSliceLen(v *Value) bool { v_0 := v.Args[0] // match: (SliceLen (SliceMake _ (Const64 [c]) _)) // result: (Const64 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type c := auxIntToInt64(v_0_1.AuxInt) v.reset(OpConst64) v.Type = t v.AuxInt = int64ToAuxInt(c) return true } // match: (SliceLen (SliceMake _ (Const32 [c]) _)) // result: (Const32 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type c := auxIntToInt32(v_0_1.AuxInt) v.reset(OpConst32) v.Type = t v.AuxInt = int32ToAuxInt(c) return true } // match: (SliceLen (SliceMake _ (SliceLen x) _)) // result: (SliceLen x) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpSliceLen { break } x := v_0_1.Args[0] v.reset(OpSliceLen) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSlicePtr(v *Value) bool { v_0 := v.Args[0] // match: (SlicePtr (SliceMake (SlicePtr x) _ _)) // result: (SlicePtr x) for { if v_0.Op != OpSliceMake { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpSlicePtr { break } x := v_0_0.Args[0] v.reset(OpSlicePtr) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSlicemask(v *Value) bool { v_0 := v.Args[0] // match: (Slicemask (Const32 [x])) // cond: x > 0 // result: (Const32 [-1]) for { if v_0.Op != OpConst32 { break } x := auxIntToInt32(v_0.AuxInt) if !(x > 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } // match: (Slicemask (Const32 [0])) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Slicemask (Const64 [x])) // cond: x > 0 // result: (Const64 [-1]) for { if v_0.Op != OpConst64 { break } x := auxIntToInt64(v_0.AuxInt) if !(x > 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } // match: (Slicemask (Const64 [0])) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpSqrt(v *Value) bool { v_0 := v.Args[0] // match: (Sqrt (Const64F [c])) // cond: !math.IsNaN(math.Sqrt(c)) // result: (Const64F [math.Sqrt(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if !(!math.IsNaN(math.Sqrt(c))) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(math.Sqrt(c)) return true } return false } func rewriteValuegeneric_OpStaticLECall(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [1]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) // result: (MakeResult (Eq8 (Load sptr mem) (Const8 [int8(read8(scon,0))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 1 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon)) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq8, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int8) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst8, typ.Int8) v2.AuxInt = int8ToAuxInt(int8(read8(scon, 0))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [2]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) // result: (MakeResult (Eq16 (Load sptr mem) (Const16 [int16(read16(scon,0,config.ctxt.Arch.ByteOrder))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 2 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config)) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq16, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int16) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst16, typ.Int16) v2.AuxInt = int16ToAuxInt(int16(read16(scon, 0, config.ctxt.Arch.ByteOrder))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [4]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) // result: (MakeResult (Eq32 (Load sptr mem) (Const32 [int32(read32(scon,0,config.ctxt.Arch.ByteOrder))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 4 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config)) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq32, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int32) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = int32ToAuxInt(int32(read32(scon, 0, config.ctxt.Arch.ByteOrder))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [8]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) && config.PtrSize == 8 // result: (MakeResult (Eq64 (Load sptr mem) (Const64 [int64(read64(scon,0,config.ctxt.Arch.ByteOrder))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 8 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) && config.PtrSize == 8) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq64, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int64) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst64, typ.Int64) v2.AuxInt = int64ToAuxInt(int64(read64(scon, 0, config.ctxt.Arch.ByteOrder))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } return false } func rewriteValuegeneric_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (Store {t1} p1 (Load p2 mem) mem) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type mem := v_1.Args[1] p2 := v_1.Args[0] if mem != v_2 || !(isSamePtr(p1, p2) && t2.Size() == t1.Size()) { break } v.copyOf(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ oldmem)) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v_2 if mem.Op != OpStore { break } t3 := auxToType(mem.Aux) _ = mem.Args[2] p3 := mem.Args[0] if oldmem != mem.Args[2] || !(isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ (Store {t4} p4 _ oldmem))) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size()) // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v_2 if mem.Op != OpStore { break } t3 := auxToType(mem.Aux) _ = mem.Args[2] p3 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t4 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p4 := mem_2.Args[0] if oldmem != mem_2.Args[2] || !(isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 _ oldmem)))) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size()) && disjoint(p1, t1.Size(), p5, t5.Size()) // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v_2 if mem.Op != OpStore { break } t3 := auxToType(mem.Aux) _ = mem.Args[2] p3 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t4 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p4 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t5 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] p5 := mem_2_2.Args[0] if oldmem != mem_2_2.Args[2] || !(isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size()) && disjoint(p1, t1.Size(), p5, t5.Size())) { break } v.copyOf(mem) return true } // match: (Store {t} (OffPtr [o] p1) x mem:(Zero [n] p2 _)) // cond: isConstZero(x) && o >= 0 && t.Size() + o <= n && isSamePtr(p1, p2) // result: mem for { t := auxToType(v.Aux) if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] x := v_1 mem := v_2 if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p2 := mem.Args[0] if !(isConstZero(x) && o >= 0 && t.Size()+o <= n && isSamePtr(p1, p2)) { break } v.copyOf(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Zero [n] p3 _))) // cond: isConstZero(x) && o1 >= 0 && t1.Size() + o1 <= n && isSamePtr(p1, p3) && disjoint(op, t1.Size(), p2, t2.Size()) // result: mem for { t1 := auxToType(v.Aux) op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] x := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpZero { break } n := auxIntToInt64(mem_2.AuxInt) p3 := mem_2.Args[0] if !(isConstZero(x) && o1 >= 0 && t1.Size()+o1 <= n && isSamePtr(p1, p3) && disjoint(op, t1.Size(), p2, t2.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Store {t3} p3 _ (Zero [n] p4 _)))) // cond: isConstZero(x) && o1 >= 0 && t1.Size() + o1 <= n && isSamePtr(p1, p4) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) // result: mem for { t1 := auxToType(v.Aux) op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] x := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p3 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpZero { break } n := auxIntToInt64(mem_2_2.AuxInt) p4 := mem_2_2.Args[0] if !(isConstZero(x) && o1 >= 0 && t1.Size()+o1 <= n && isSamePtr(p1, p4) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Zero [n] p5 _))))) // cond: isConstZero(x) && o1 >= 0 && t1.Size() + o1 <= n && isSamePtr(p1, p5) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) // result: mem for { t1 := auxToType(v.Aux) op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] x := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p3 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] p4 := mem_2_2.Args[0] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpZero { break } n := auxIntToInt64(mem_2_2_2.AuxInt) p5 := mem_2_2_2.Args[0] if !(isConstZero(x) && o1 >= 0 && t1.Size()+o1 <= n && isSamePtr(p1, p5) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size())) { break } v.copyOf(mem) return true } // match: (Store _ (StructMake0) mem) // result: mem for { if v_1.Op != OpStructMake0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Store dst (StructMake1 f0) mem) // result: (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem) for { dst := v_0 if v_1.Op != OpStructMake1 { break } t := v_1.Type f0 := v_1.Args[0] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(0)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v0.AuxInt = int64ToAuxInt(0) v0.AddArg(dst) v.AddArg3(v0, f0, mem) return true } // match: (Store dst (StructMake2 f0 f1) mem) // result: (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem)) for { dst := v_0 if v_1.Op != OpStructMake2 { break } t := v_1.Type f1 := v_1.Args[1] f0 := v_1.Args[0] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(1)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v0.AuxInt = int64ToAuxInt(t.FieldOff(1)) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t.FieldType(0)) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v2.AuxInt = int64ToAuxInt(0) v2.AddArg(dst) v1.AddArg3(v2, f0, mem) v.AddArg3(v0, f1, v1) return true } // match: (Store dst (StructMake3 f0 f1 f2) mem) // result: (Store {t.FieldType(2)} (OffPtr [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem))) for { dst := v_0 if v_1.Op != OpStructMake3 { break } t := v_1.Type f2 := v_1.Args[2] f0 := v_1.Args[0] f1 := v_1.Args[1] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(2)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v0.AuxInt = int64ToAuxInt(t.FieldOff(2)) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t.FieldType(1)) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v2.AuxInt = int64ToAuxInt(t.FieldOff(1)) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t.FieldType(0)) v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v4.AuxInt = int64ToAuxInt(0) v4.AddArg(dst) v3.AddArg3(v4, f0, mem) v1.AddArg3(v2, f1, v3) v.AddArg3(v0, f2, v1) return true } // match: (Store dst (StructMake4 f0 f1 f2 f3) mem) // result: (Store {t.FieldType(3)} (OffPtr [t.FieldOff(3)] dst) f3 (Store {t.FieldType(2)} (OffPtr [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem)))) for { dst := v_0 if v_1.Op != OpStructMake4 { break } t := v_1.Type f3 := v_1.Args[3] f0 := v_1.Args[0] f1 := v_1.Args[1] f2 := v_1.Args[2] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(3)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo()) v0.AuxInt = int64ToAuxInt(t.FieldOff(3)) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t.FieldType(2)) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v2.AuxInt = int64ToAuxInt(t.FieldOff(2)) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t.FieldType(1)) v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v4.AuxInt = int64ToAuxInt(t.FieldOff(1)) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t.FieldType(0)) v6 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v6.AuxInt = int64ToAuxInt(0) v6.AddArg(dst) v5.AddArg3(v6, f0, mem) v3.AddArg3(v4, f1, v5) v1.AddArg3(v2, f2, v3) v.AddArg3(v0, f3, v1) return true } // match: (Store {t} dst (Load src mem) mem) // cond: !fe.CanSSA(t) // result: (Move {t} [t.Size()] dst src mem) for { t := auxToType(v.Aux) dst := v_0 if v_1.Op != OpLoad { break } mem := v_1.Args[1] src := v_1.Args[0] if mem != v_2 || !(!fe.CanSSA(t)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(t.Size()) v.Aux = typeToAux(t) v.AddArg3(dst, src, mem) return true } // match: (Store {t} dst (Load src mem) (VarDef {x} mem)) // cond: !fe.CanSSA(t) // result: (Move {t} [t.Size()] dst src (VarDef {x} mem)) for { t := auxToType(v.Aux) dst := v_0 if v_1.Op != OpLoad { break } mem := v_1.Args[1] src := v_1.Args[0] if v_2.Op != OpVarDef { break } x := auxToSym(v_2.Aux) if mem != v_2.Args[0] || !(!fe.CanSSA(t)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(t.Size()) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg3(dst, src, v0) return true } // match: (Store _ (ArrayMake0) mem) // result: mem for { if v_1.Op != OpArrayMake0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Store dst (ArrayMake1 e) mem) // result: (Store {e.Type} dst e mem) for { dst := v_0 if v_1.Op != OpArrayMake1 { break } e := v_1.Args[0] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(e.Type) v.AddArg3(dst, e, mem) return true } // match: (Store (SelectN [0] call:(StaticLECall _ _)) x mem:(SelectN [1] call)) // cond: isConstZero(x) && isSameCall(call.Aux, "runtime.newobject") // result: mem for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { break } call := v_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 { break } x := v_1 mem := v_2 if mem.Op != OpSelectN || auxIntToInt64(mem.AuxInt) != 1 || call != mem.Args[0] || !(isConstZero(x) && isSameCall(call.Aux, "runtime.newobject")) { break } v.copyOf(mem) return true } // match: (Store (OffPtr (SelectN [0] call:(StaticLECall _ _))) x mem:(SelectN [1] call)) // cond: isConstZero(x) && isSameCall(call.Aux, "runtime.newobject") // result: mem for { if v_0.Op != OpOffPtr { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpSelectN || auxIntToInt64(v_0_0.AuxInt) != 0 { break } call := v_0_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 { break } x := v_1 mem := v_2 if mem.Op != OpSelectN || auxIntToInt64(mem.AuxInt) != 1 || call != mem.Args[0] || !(isConstZero(x) && isSameCall(call.Aux, "runtime.newobject")) { break } v.copyOf(mem) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [0] p2) d2 m3:(Move [n] p3 _ mem))) // cond: m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 mem)) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr || auxIntToInt64(op2.AuxInt) != 0 { break } p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpMove { break } n := auxIntToInt64(m3.AuxInt) mem := m3.Args[2] p3 := m3.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v0.AddArg3(op2, d2, mem) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Move [n] p4 _ mem)))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 mem))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr || auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpMove { break } n := auxIntToInt64(m4.AuxInt) mem := m4.Args[2] p4 := m4.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v1.AddArg3(op3, d3, mem) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Move [n] p5 _ mem))))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size() + t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 (Store {t4} op4 d4 mem)))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpStore { break } t4 := auxToType(m4.Aux) _ = m4.Args[2] op4 := m4.Args[0] if op4.Op != OpOffPtr || auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] d4 := m4.Args[1] m5 := m4.Args[2] if m5.Op != OpMove { break } n := auxIntToInt64(m5.AuxInt) mem := m5.Args[2] p5 := m5.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size()+t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v2.Aux = typeToAux(t4) v2.AddArg3(op4, d4, mem) v1.AddArg3(op3, d3, v2) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [0] p2) d2 m3:(Zero [n] p3 mem))) // cond: m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 mem)) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr || auxIntToInt64(op2.AuxInt) != 0 { break } p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpZero { break } n := auxIntToInt64(m3.AuxInt) mem := m3.Args[1] p3 := m3.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v0.AddArg3(op2, d2, mem) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Zero [n] p4 mem)))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 mem))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr || auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpZero { break } n := auxIntToInt64(m4.AuxInt) mem := m4.Args[1] p4 := m4.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v1.AddArg3(op3, d3, mem) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Zero [n] p5 mem))))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size() + t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 (Store {t4} op4 d4 mem)))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpStore { break } t4 := auxToType(m4.Aux) _ = m4.Args[2] op4 := m4.Args[0] if op4.Op != OpOffPtr || auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] d4 := m4.Args[1] m5 := m4.Args[2] if m5.Op != OpZero { break } n := auxIntToInt64(m5.AuxInt) mem := m5.Args[1] p5 := m5.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size()+t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v2.Aux = typeToAux(t4) v2.AddArg3(op4, d4, mem) v1.AddArg3(op3, d3, v2) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } return false } func rewriteValuegeneric_OpStringLen(v *Value) bool { v_0 := v.Args[0] // match: (StringLen (StringMake _ (Const64 [c]))) // result: (Const64 [c]) for { if v_0.Op != OpStringMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type c := auxIntToInt64(v_0_1.AuxInt) v.reset(OpConst64) v.Type = t v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValuegeneric_OpStringPtr(v *Value) bool { v_0 := v.Args[0] // match: (StringPtr (StringMake (Addr {s} base) _)) // result: (Addr {s} base) for { if v_0.Op != OpStringMake { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { break } t := v_0_0.Type s := auxToSym(v_0_0.Aux) base := v_0_0.Args[0] v.reset(OpAddr) v.Type = t v.Aux = symToAux(s) v.AddArg(base) return true } return false } func rewriteValuegeneric_OpStructSelect(v *Value) bool { v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (StructSelect (StructMake1 x)) // result: x for { if v_0.Op != OpStructMake1 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [0] (StructMake2 x _)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpStructMake2 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [1] (StructMake2 _ x)) // result: x for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStructMake2 { break } x := v_0.Args[1] v.copyOf(x) return true } // match: (StructSelect [0] (StructMake3 x _ _)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpStructMake3 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [1] (StructMake3 _ x _)) // result: x for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStructMake3 { break } x := v_0.Args[1] v.copyOf(x) return true } // match: (StructSelect [2] (StructMake3 _ _ x)) // result: x for { if auxIntToInt64(v.AuxInt) != 2 || v_0.Op != OpStructMake3 { break } x := v_0.Args[2] v.copyOf(x) return true } // match: (StructSelect [0] (StructMake4 x _ _ _)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpStructMake4 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [1] (StructMake4 _ x _ _)) // result: x for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStructMake4 { break } x := v_0.Args[1] v.copyOf(x) return true } // match: (StructSelect [2] (StructMake4 _ _ x _)) // result: x for { if auxIntToInt64(v.AuxInt) != 2 || v_0.Op != OpStructMake4 { break } x := v_0.Args[2] v.copyOf(x) return true } // match: (StructSelect [3] (StructMake4 _ _ _ x)) // result: x for { if auxIntToInt64(v.AuxInt) != 3 || v_0.Op != OpStructMake4 { break } x := v_0.Args[3] v.copyOf(x) return true } // match: (StructSelect [i] x:(Load ptr mem)) // cond: !fe.CanSSA(t) // result: @x.Block (Load (OffPtr [t.FieldOff(int(i))] ptr) mem) for { i := auxIntToInt64(v.AuxInt) x := v_0 if x.Op != OpLoad { break } t := x.Type mem := x.Args[1] ptr := x.Args[0] if !(!fe.CanSSA(t)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpLoad, v.Type) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, v.Type.PtrTo()) v1.AuxInt = int64ToAuxInt(t.FieldOff(int(i))) v1.AddArg(ptr) v0.AddArg2(v1, mem) return true } // match: (StructSelect [0] (IData x)) // result: (IData x) for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpIData { break } x := v_0.Args[0] v.reset(OpIData) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c-d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c - d) return true } // match: (Sub16 x (Const16 [c])) // cond: x.Op != OpConst16 // result: (Add16 (Const16 [-c]) x) for { x := v_0 if v_1.Op != OpConst16 { break } t := v_1.Type c := auxIntToInt16(v_1.AuxInt) if !(x.Op != OpConst16) { break } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub16 (Mul16 x y) (Mul16 x z)) // result: (Mul16 x (Sub16 y z)) for { t := v.Type if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub16 x x) // result: (Const16 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Sub16 (Neg16 x) (Com16 x)) // result: (Const16 [1]) for { if v_0.Op != OpNeg16 { break } x := v_0.Args[0] if v_1.Op != OpCom16 || x != v_1.Args[0] { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(1) return true } // match: (Sub16 (Com16 x) (Neg16 x)) // result: (Const16 [-1]) for { if v_0.Op != OpCom16 { break } x := v_0.Args[0] if v_1.Op != OpNeg16 || x != v_1.Args[0] { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } // match: (Sub16 (Add16 x y) x) // result: y for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub16 (Add16 x y) y) // result: x for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub16 (Sub16 x y) x) // result: (Neg16 y) for { if v_0.Op != OpSub16 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg16) v.AddArg(y) return true } // match: (Sub16 x (Add16 x y)) // result: (Neg16 y) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg16) v.AddArg(y) return true } break } // match: (Sub16 x (Sub16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { x := v_0 if v_1.Op != OpSub16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub16 x (Add16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Sub16 x z) i) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst16 { continue } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub16 (Sub16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 i (Add16 z x)) for { if v_0.Op != OpSub16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub16 (Add16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 z x)) for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst16 { continue } t := i.Type x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub16 (Const16 [c]) (Sub16 (Const16 [d]) x)) // result: (Add16 (Const16 [c-d]) x) for { if v_0.Op != OpConst16 { break } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpSub16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 || v_1_0.Type != t { break } d := auxIntToInt16(v_1_0.AuxInt) v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Sub16 (Const16 [c-d]) x) for { if v_0.Op != OpConst16 { break } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpSub32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c-d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c - d) return true } // match: (Sub32 x (Const32 [c])) // cond: x.Op != OpConst32 // result: (Add32 (Const32 [-c]) x) for { x := v_0 if v_1.Op != OpConst32 { break } t := v_1.Type c := auxIntToInt32(v_1.AuxInt) if !(x.Op != OpConst32) { break } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub32 (Mul32 x y) (Mul32 x z)) // result: (Mul32 x (Sub32 y z)) for { t := v.Type if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub32 x x) // result: (Const32 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Sub32 (Neg32 x) (Com32 x)) // result: (Const32 [1]) for { if v_0.Op != OpNeg32 { break } x := v_0.Args[0] if v_1.Op != OpCom32 || x != v_1.Args[0] { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(1) return true } // match: (Sub32 (Com32 x) (Neg32 x)) // result: (Const32 [-1]) for { if v_0.Op != OpCom32 { break } x := v_0.Args[0] if v_1.Op != OpNeg32 || x != v_1.Args[0] { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } // match: (Sub32 (Add32 x y) x) // result: y for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub32 (Add32 x y) y) // result: x for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub32 (Sub32 x y) x) // result: (Neg32 y) for { if v_0.Op != OpSub32 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg32) v.AddArg(y) return true } // match: (Sub32 x (Add32 x y)) // result: (Neg32 y) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg32) v.AddArg(y) return true } break } // match: (Sub32 x (Sub32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { x := v_0 if v_1.Op != OpSub32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub32 x (Add32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Sub32 x z) i) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst32 { continue } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub32 (Sub32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 i (Add32 z x)) for { if v_0.Op != OpSub32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub32 (Add32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 z x)) for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst32 { continue } t := i.Type x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub32 (Const32 [c]) (Sub32 (Const32 [d]) x)) // result: (Add32 (Const32 [c-d]) x) for { if v_0.Op != OpConst32 { break } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpSub32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 || v_1_0.Type != t { break } d := auxIntToInt32(v_1_0.AuxInt) v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Sub32 (Const32 [c-d]) x) for { if v_0.Op != OpConst32 { break } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpSub32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Sub32F (Const32F [c]) (Const32F [d])) // cond: c-d == c-d // result: (Const32F [c-d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) if !(c-d == c-d) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c - d) return true } return false } func rewriteValuegeneric_OpSub64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c-d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c - d) return true } // match: (Sub64 x (Const64 [c])) // cond: x.Op != OpConst64 // result: (Add64 (Const64 [-c]) x) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(x.Op != OpConst64) { break } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub64 (Mul64 x y) (Mul64 x z)) // result: (Mul64 x (Sub64 y z)) for { t := v.Type if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub64 x x) // result: (Const64 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Sub64 (Neg64 x) (Com64 x)) // result: (Const64 [1]) for { if v_0.Op != OpNeg64 { break } x := v_0.Args[0] if v_1.Op != OpCom64 || x != v_1.Args[0] { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(1) return true } // match: (Sub64 (Com64 x) (Neg64 x)) // result: (Const64 [-1]) for { if v_0.Op != OpCom64 { break } x := v_0.Args[0] if v_1.Op != OpNeg64 || x != v_1.Args[0] { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } // match: (Sub64 (Add64 x y) x) // result: y for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub64 (Add64 x y) y) // result: x for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub64 (Sub64 x y) x) // result: (Neg64 y) for { if v_0.Op != OpSub64 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg64) v.AddArg(y) return true } // match: (Sub64 x (Add64 x y)) // result: (Neg64 y) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg64) v.AddArg(y) return true } break } // match: (Sub64 x (Sub64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { x := v_0 if v_1.Op != OpSub64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub64 x (Add64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Sub64 x z) i) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst64 { continue } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub64 (Sub64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 i (Add64 z x)) for { if v_0.Op != OpSub64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub64 (Add64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 z x)) for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst64 { continue } t := i.Type x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub64 (Const64 [c]) (Sub64 (Const64 [d]) x)) // result: (Add64 (Const64 [c-d]) x) for { if v_0.Op != OpConst64 { break } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpSub64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 || v_1_0.Type != t { break } d := auxIntToInt64(v_1_0.AuxInt) v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Sub64 (Const64 [c-d]) x) for { if v_0.Op != OpConst64 { break } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpSub64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Sub64F (Const64F [c]) (Const64F [d])) // cond: c-d == c-d // result: (Const64F [c-d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) if !(c-d == c-d) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c - d) return true } return false } func rewriteValuegeneric_OpSub8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c-d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c - d) return true } // match: (Sub8 x (Const8 [c])) // cond: x.Op != OpConst8 // result: (Add8 (Const8 [-c]) x) for { x := v_0 if v_1.Op != OpConst8 { break } t := v_1.Type c := auxIntToInt8(v_1.AuxInt) if !(x.Op != OpConst8) { break } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub8 (Mul8 x y) (Mul8 x z)) // result: (Mul8 x (Sub8 y z)) for { t := v.Type if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub8 x x) // result: (Const8 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Sub8 (Neg8 x) (Com8 x)) // result: (Const8 [1]) for { if v_0.Op != OpNeg8 { break } x := v_0.Args[0] if v_1.Op != OpCom8 || x != v_1.Args[0] { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(1) return true } // match: (Sub8 (Com8 x) (Neg8 x)) // result: (Const8 [-1]) for { if v_0.Op != OpCom8 { break } x := v_0.Args[0] if v_1.Op != OpNeg8 || x != v_1.Args[0] { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } // match: (Sub8 (Add8 x y) x) // result: y for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub8 (Add8 x y) y) // result: x for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub8 (Sub8 x y) x) // result: (Neg8 y) for { if v_0.Op != OpSub8 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg8) v.AddArg(y) return true } // match: (Sub8 x (Add8 x y)) // result: (Neg8 y) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg8) v.AddArg(y) return true } break } // match: (Sub8 x (Sub8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { x := v_0 if v_1.Op != OpSub8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub8 x (Add8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Sub8 x z) i) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst8 { continue } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub8 (Sub8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 i (Add8 z x)) for { if v_0.Op != OpSub8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub8 (Add8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 z x)) for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst8 { continue } t := i.Type x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub8 (Const8 [c]) (Sub8 (Const8 [d]) x)) // result: (Add8 (Const8 [c-d]) x) for { if v_0.Op != OpConst8 { break } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpSub8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 || v_1_0.Type != t { break } d := auxIntToInt8(v_1_0.AuxInt) v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Sub8 (Const8 [c-d]) x) for { if v_0.Op != OpConst8 { break } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpTrunc16to8(v *Value) bool { v_0 := v.Args[0] // match: (Trunc16to8 (Const16 [c])) // result: (Const8 [int8(c)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(c)) return true } // match: (Trunc16to8 (ZeroExt8to16 x)) // result: x for { if v_0.Op != OpZeroExt8to16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc16to8 (SignExt8to16 x)) // result: x for { if v_0.Op != OpSignExt8to16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc16to8 (And16 (Const16 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc16to8 x) for { if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst16 { continue } y := auxIntToInt16(v_0_0.AuxInt) x := v_0_1 if !(y&0xFF == 0xFF) { continue } v.reset(OpTrunc16to8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc32to16(v *Value) bool { v_0 := v.Args[0] // match: (Trunc32to16 (Const32 [c])) // result: (Const16 [int16(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(c)) return true } // match: (Trunc32to16 (ZeroExt8to32 x)) // result: (ZeroExt8to16 x) for { if v_0.Op != OpZeroExt8to32 { break } x := v_0.Args[0] v.reset(OpZeroExt8to16) v.AddArg(x) return true } // match: (Trunc32to16 (ZeroExt16to32 x)) // result: x for { if v_0.Op != OpZeroExt16to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to16 (SignExt8to32 x)) // result: (SignExt8to16 x) for { if v_0.Op != OpSignExt8to32 { break } x := v_0.Args[0] v.reset(OpSignExt8to16) v.AddArg(x) return true } // match: (Trunc32to16 (SignExt16to32 x)) // result: x for { if v_0.Op != OpSignExt16to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to16 (And32 (Const32 [y]) x)) // cond: y&0xFFFF == 0xFFFF // result: (Trunc32to16 x) for { if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 { continue } y := auxIntToInt32(v_0_0.AuxInt) x := v_0_1 if !(y&0xFFFF == 0xFFFF) { continue } v.reset(OpTrunc32to16) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc32to8(v *Value) bool { v_0 := v.Args[0] // match: (Trunc32to8 (Const32 [c])) // result: (Const8 [int8(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(c)) return true } // match: (Trunc32to8 (ZeroExt8to32 x)) // result: x for { if v_0.Op != OpZeroExt8to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to8 (SignExt8to32 x)) // result: x for { if v_0.Op != OpSignExt8to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to8 (And32 (Const32 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc32to8 x) for { if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 { continue } y := auxIntToInt32(v_0_0.AuxInt) x := v_0_1 if !(y&0xFF == 0xFF) { continue } v.reset(OpTrunc32to8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc64to16(v *Value) bool { v_0 := v.Args[0] // match: (Trunc64to16 (Const64 [c])) // result: (Const16 [int16(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(c)) return true } // match: (Trunc64to16 (ZeroExt8to64 x)) // result: (ZeroExt8to16 x) for { if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpZeroExt8to16) v.AddArg(x) return true } // match: (Trunc64to16 (ZeroExt16to64 x)) // result: x for { if v_0.Op != OpZeroExt16to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to16 (SignExt8to64 x)) // result: (SignExt8to16 x) for { if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpSignExt8to16) v.AddArg(x) return true } // match: (Trunc64to16 (SignExt16to64 x)) // result: x for { if v_0.Op != OpSignExt16to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to16 (And64 (Const64 [y]) x)) // cond: y&0xFFFF == 0xFFFF // result: (Trunc64to16 x) for { if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } y := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(y&0xFFFF == 0xFFFF) { continue } v.reset(OpTrunc64to16) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc64to32(v *Value) bool { v_0 := v.Args[0] // match: (Trunc64to32 (Const64 [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } // match: (Trunc64to32 (ZeroExt8to64 x)) // result: (ZeroExt8to32 x) for { if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpZeroExt8to32) v.AddArg(x) return true } // match: (Trunc64to32 (ZeroExt16to64 x)) // result: (ZeroExt16to32 x) for { if v_0.Op != OpZeroExt16to64 { break } x := v_0.Args[0] v.reset(OpZeroExt16to32) v.AddArg(x) return true } // match: (Trunc64to32 (ZeroExt32to64 x)) // result: x for { if v_0.Op != OpZeroExt32to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to32 (SignExt8to64 x)) // result: (SignExt8to32 x) for { if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpSignExt8to32) v.AddArg(x) return true } // match: (Trunc64to32 (SignExt16to64 x)) // result: (SignExt16to32 x) for { if v_0.Op != OpSignExt16to64 { break } x := v_0.Args[0] v.reset(OpSignExt16to32) v.AddArg(x) return true } // match: (Trunc64to32 (SignExt32to64 x)) // result: x for { if v_0.Op != OpSignExt32to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to32 (And64 (Const64 [y]) x)) // cond: y&0xFFFFFFFF == 0xFFFFFFFF // result: (Trunc64to32 x) for { if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } y := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(y&0xFFFFFFFF == 0xFFFFFFFF) { continue } v.reset(OpTrunc64to32) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc64to8(v *Value) bool { v_0 := v.Args[0] // match: (Trunc64to8 (Const64 [c])) // result: (Const8 [int8(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(c)) return true } // match: (Trunc64to8 (ZeroExt8to64 x)) // result: x for { if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to8 (SignExt8to64 x)) // result: x for { if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to8 (And64 (Const64 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc64to8 x) for { if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } y := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(y&0xFF == 0xFF) { continue } v.reset(OpTrunc64to8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpXor16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Xor16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c ^ d) return true } break } // match: (Xor16 x x) // result: (Const16 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Xor16 (Const16 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor16 (Com16 x) x) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Xor16 (Const16 [-1]) x) // result: (Com16 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom16) v.AddArg(x) return true } break } // match: (Xor16 x (Xor16 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor16 (Xor16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Xor16 i (Xor16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpXor16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor16 (Const16 [c]) (Xor16 (Const16 [d]) x)) // result: (Xor16 (Const16 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpXor16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } // match: (Xor16 (Lsh16x64 x z:(Const64 [c])) (Rsh16Ux64 x (Const64 [d]))) // cond: c < 16 && d == 16-c && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh16x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh16Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 16 && d == 16-c && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Xor16 left:(Lsh16x64 x y) right:(Rsh16Ux64 x (Sub64 (Const64 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Xor16 left:(Lsh16x32 x y) right:(Rsh16Ux32 x (Sub32 (Const32 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Xor16 left:(Lsh16x16 x y) right:(Rsh16Ux16 x (Sub16 (Const16 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Xor16 left:(Lsh16x8 x y) right:(Rsh16Ux8 x (Sub8 (Const8 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Xor16 right:(Rsh16Ux64 x y) left:(Lsh16x64 x z:(Sub64 (Const64 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Xor16 right:(Rsh16Ux32 x y) left:(Lsh16x32 x z:(Sub32 (Const32 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Xor16 right:(Rsh16Ux16 x y) left:(Lsh16x16 x z:(Sub16 (Const16 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Xor16 right:(Rsh16Ux8 x y) left:(Lsh16x8 x z:(Sub8 (Const8 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpXor32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Xor32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c ^ d) return true } break } // match: (Xor32 x x) // result: (Const32 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Xor32 (Const32 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor32 (Com32 x) x) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Xor32 (Const32 [-1]) x) // result: (Com32 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom32) v.AddArg(x) return true } break } // match: (Xor32 x (Xor32 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor32 (Xor32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Xor32 i (Xor32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpXor32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor32 (Const32 [c]) (Xor32 (Const32 [d]) x)) // result: (Xor32 (Const32 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpXor32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } // match: (Xor32 (Lsh32x64 x z:(Const64 [c])) (Rsh32Ux64 x (Const64 [d]))) // cond: c < 32 && d == 32-c && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh32x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh32Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 32 && d == 32-c && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Xor32 left:(Lsh32x64 x y) right:(Rsh32Ux64 x (Sub64 (Const64 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Xor32 left:(Lsh32x32 x y) right:(Rsh32Ux32 x (Sub32 (Const32 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Xor32 left:(Lsh32x16 x y) right:(Rsh32Ux16 x (Sub16 (Const16 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Xor32 left:(Lsh32x8 x y) right:(Rsh32Ux8 x (Sub8 (Const8 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Xor32 right:(Rsh32Ux64 x y) left:(Lsh32x64 x z:(Sub64 (Const64 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Xor32 right:(Rsh32Ux32 x y) left:(Lsh32x32 x z:(Sub32 (Const32 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Xor32 right:(Rsh32Ux16 x y) left:(Lsh32x16 x z:(Sub16 (Const16 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Xor32 right:(Rsh32Ux8 x y) left:(Lsh32x8 x z:(Sub8 (Const8 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpXor64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Xor64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c ^ d) return true } break } // match: (Xor64 x x) // result: (Const64 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Xor64 (Const64 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor64 (Com64 x) x) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Xor64 (Const64 [-1]) x) // result: (Com64 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom64) v.AddArg(x) return true } break } // match: (Xor64 x (Xor64 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor64 (Xor64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Xor64 i (Xor64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpXor64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor64 (Const64 [c]) (Xor64 (Const64 [d]) x)) // result: (Xor64 (Const64 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpXor64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } // match: (Xor64 (Lsh64x64 x z:(Const64 [c])) (Rsh64Ux64 x (Const64 [d]))) // cond: c < 64 && d == 64-c && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh64x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh64Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 64 && d == 64-c && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Xor64 left:(Lsh64x64 x y) right:(Rsh64Ux64 x (Sub64 (Const64 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Xor64 left:(Lsh64x32 x y) right:(Rsh64Ux32 x (Sub32 (Const32 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Xor64 left:(Lsh64x16 x y) right:(Rsh64Ux16 x (Sub16 (Const16 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Xor64 left:(Lsh64x8 x y) right:(Rsh64Ux8 x (Sub8 (Const8 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Xor64 right:(Rsh64Ux64 x y) left:(Lsh64x64 x z:(Sub64 (Const64 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Xor64 right:(Rsh64Ux32 x y) left:(Lsh64x32 x z:(Sub32 (Const32 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Xor64 right:(Rsh64Ux16 x y) left:(Lsh64x16 x z:(Sub16 (Const16 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Xor64 right:(Rsh64Ux8 x y) left:(Lsh64x8 x z:(Sub8 (Const8 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpXor8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Xor8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c ^ d) return true } break } // match: (Xor8 x x) // result: (Const8 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Xor8 (Const8 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor8 (Com8 x) x) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Xor8 (Const8 [-1]) x) // result: (Com8 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom8) v.AddArg(x) return true } break } // match: (Xor8 x (Xor8 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor8 (Xor8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Xor8 i (Xor8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpXor8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor8 (Const8 [c]) (Xor8 (Const8 [d]) x)) // result: (Xor8 (Const8 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpXor8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } // match: (Xor8 (Lsh8x64 x z:(Const64 [c])) (Rsh8Ux64 x (Const64 [d]))) // cond: c < 8 && d == 8-c && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh8x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh8Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 8 && d == 8-c && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Xor8 left:(Lsh8x64 x y) right:(Rsh8Ux64 x (Sub64 (Const64 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Xor8 left:(Lsh8x32 x y) right:(Rsh8Ux32 x (Sub32 (Const32 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Xor8 left:(Lsh8x16 x y) right:(Rsh8Ux16 x (Sub16 (Const16 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Xor8 left:(Lsh8x8 x y) right:(Rsh8Ux8 x (Sub8 (Const8 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Xor8 right:(Rsh8Ux64 x y) left:(Lsh8x64 x z:(Sub64 (Const64 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Xor8 right:(Rsh8Ux32 x y) left:(Lsh8x32 x z:(Sub32 (Const32 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Xor8 right:(Rsh8Ux16 x y) left:(Lsh8x16 x z:(Sub16 (Const16 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Xor8 right:(Rsh8Ux8 x y) left:(Lsh8x8 x z:(Sub8 (Const8 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Zero (SelectN [0] call:(StaticLECall _ _)) mem:(SelectN [1] call)) // cond: isSameCall(call.Aux, "runtime.newobject") // result: mem for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { break } call := v_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 { break } mem := v_1 if mem.Op != OpSelectN || auxIntToInt64(mem.AuxInt) != 1 || call != mem.Args[0] || !(isSameCall(call.Aux, "runtime.newobject")) { break } v.copyOf(mem) return true } // match: (Zero {t1} [n] p1 store:(Store {t2} (OffPtr [o2] p2) _ mem)) // cond: isSamePtr(p1, p2) && store.Uses == 1 && n >= o2 + t2.Size() && clobber(store) // result: (Zero {t1} [n] p1 mem) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) p1 := v_0 store := v_1 if store.Op != OpStore { break } t2 := auxToType(store.Aux) mem := store.Args[2] store_0 := store.Args[0] if store_0.Op != OpOffPtr { break } o2 := auxIntToInt64(store_0.AuxInt) p2 := store_0.Args[0] if !(isSamePtr(p1, p2) && store.Uses == 1 && n >= o2+t2.Size() && clobber(store)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t1) v.AddArg2(p1, mem) return true } // match: (Zero {t} [n] dst1 move:(Move {t} [n] dst2 _ mem)) // cond: move.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move) // result: (Zero {t} [n] dst1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 move := v_1 if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst1, mem) return true } // match: (Zero {t} [n] dst1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem))) // cond: move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move, vardef) // result: (Zero {t} [n] dst1 (VarDef {x} mem)) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 vardef := v_1 if vardef.Op != OpVarDef { break } x := auxToSym(vardef.Aux) move := vardef.Args[0] if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move, vardef)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg2(dst1, v0) return true } // match: (Zero {t} [s] dst1 zero:(Zero {t} [s] dst2 _)) // cond: isSamePtr(dst1, dst2) // result: zero for { s := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 zero := v_1 if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != s || auxToType(zero.Aux) != t { break } dst2 := zero.Args[0] if !(isSamePtr(dst1, dst2)) { break } v.copyOf(zero) return true } // match: (Zero {t} [s] dst1 vardef:(VarDef (Zero {t} [s] dst2 _))) // cond: isSamePtr(dst1, dst2) // result: vardef for { s := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 vardef := v_1 if vardef.Op != OpVarDef { break } vardef_0 := vardef.Args[0] if vardef_0.Op != OpZero || auxIntToInt64(vardef_0.AuxInt) != s || auxToType(vardef_0.Aux) != t { break } dst2 := vardef_0.Args[0] if !(isSamePtr(dst1, dst2)) { break } v.copyOf(vardef) return true } return false } func rewriteValuegeneric_OpZeroExt16to32(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt16to32 (Const16 [c])) // result: (Const32 [int32(uint16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint16(c))) return true } // match: (ZeroExt16to32 (Trunc32to16 x:(Rsh32Ux64 _ (Const64 [s])))) // cond: s >= 16 // result: x for { if v_0.Op != OpTrunc32to16 { break } x := v_0.Args[0] if x.Op != OpRsh32Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 16) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt16to64(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt16to64 (Const16 [c])) // result: (Const64 [int64(uint16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint16(c))) return true } // match: (ZeroExt16to64 (Trunc64to16 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 48 // result: x for { if v_0.Op != OpTrunc64to16 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 48) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt32to64(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt32to64 (Const32 [c])) // result: (Const64 [int64(uint32(c))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint32(c))) return true } // match: (ZeroExt32to64 (Trunc64to32 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 32 // result: x for { if v_0.Op != OpTrunc64to32 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 32) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to16(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt8to16 (Const8 [c])) // result: (Const16 [int16( uint8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint8(c))) return true } // match: (ZeroExt8to16 (Trunc16to8 x:(Rsh16Ux64 _ (Const64 [s])))) // cond: s >= 8 // result: x for { if v_0.Op != OpTrunc16to8 { break } x := v_0.Args[0] if x.Op != OpRsh16Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 8) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to32(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt8to32 (Const8 [c])) // result: (Const32 [int32( uint8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint8(c))) return true } // match: (ZeroExt8to32 (Trunc32to8 x:(Rsh32Ux64 _ (Const64 [s])))) // cond: s >= 24 // result: x for { if v_0.Op != OpTrunc32to8 { break } x := v_0.Args[0] if x.Op != OpRsh32Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 24) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to64(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt8to64 (Const8 [c])) // result: (Const64 [int64( uint8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint8(c))) return true } // match: (ZeroExt8to64 (Trunc64to8 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 56 // result: x for { if v_0.Op != OpTrunc64to8 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 56) { break } v.copyOf(x) return true } return false } func rewriteBlockgeneric(b *Block) bool { switch b.Kind { case BlockIf: // match: (If (Not cond) yes no) // result: (If cond no yes) for b.Controls[0].Op == OpNot { v_0 := b.Controls[0] cond := v_0.Args[0] b.resetWithControl(BlockIf, cond) b.swapSuccessors() return true } // match: (If (ConstBool [c]) yes no) // cond: c // result: (First yes no) for b.Controls[0].Op == OpConstBool { v_0 := b.Controls[0] c := auxIntToBool(v_0.AuxInt) if !(c) { break } b.Reset(BlockFirst) return true } // match: (If (ConstBool [c]) yes no) // cond: !c // result: (First no yes) for b.Controls[0].Op == OpConstBool { v_0 := b.Controls[0] c := auxIntToBool(v_0.AuxInt) if !(!c) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } diff-1.0.1/internal/benchmarks/testdata/large_04.test000066400000000000000000107207501516001707200224740ustar00rootroot00000000000000From https://go.googlesource.com/go commit bd6d78ef37b5a607abfb530f3e353cfa653492f1 file testdata/go_bd6d78ef37b5a607abfb530f3e353cfa653492f1_src_cmd_compile_internal_ssa_rewriteAMD64.go.test -- x -- // Code generated from gen/AMD64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/compile/internal/types" func rewriteValueAMD64(v *Value) bool { switch v.Op { case OpAMD64ADCQ: return rewriteValueAMD64_OpAMD64ADCQ_0(v) case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst_0(v) case OpAMD64ADDL: return rewriteValueAMD64_OpAMD64ADDL_0(v) || rewriteValueAMD64_OpAMD64ADDL_10(v) || rewriteValueAMD64_OpAMD64ADDL_20(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst_0(v) || rewriteValueAMD64_OpAMD64ADDLconst_10(v) case OpAMD64ADDLconstmodify: return rewriteValueAMD64_OpAMD64ADDLconstmodify_0(v) case OpAMD64ADDLload: return rewriteValueAMD64_OpAMD64ADDLload_0(v) case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify_0(v) case OpAMD64ADDQ: return rewriteValueAMD64_OpAMD64ADDQ_0(v) || rewriteValueAMD64_OpAMD64ADDQ_10(v) || rewriteValueAMD64_OpAMD64ADDQ_20(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry_0(v) case OpAMD64ADDQconst: return rewriteValueAMD64_OpAMD64ADDQconst_0(v) || rewriteValueAMD64_OpAMD64ADDQconst_10(v) case OpAMD64ADDQconstmodify: return rewriteValueAMD64_OpAMD64ADDQconstmodify_0(v) case OpAMD64ADDQload: return rewriteValueAMD64_OpAMD64ADDQload_0(v) case OpAMD64ADDQmodify: return rewriteValueAMD64_OpAMD64ADDQmodify_0(v) case OpAMD64ADDSD: return rewriteValueAMD64_OpAMD64ADDSD_0(v) case OpAMD64ADDSDload: return rewriteValueAMD64_OpAMD64ADDSDload_0(v) case OpAMD64ADDSS: return rewriteValueAMD64_OpAMD64ADDSS_0(v) case OpAMD64ADDSSload: return rewriteValueAMD64_OpAMD64ADDSSload_0(v) case OpAMD64ANDL: return rewriteValueAMD64_OpAMD64ANDL_0(v) case OpAMD64ANDLconst: return rewriteValueAMD64_OpAMD64ANDLconst_0(v) case OpAMD64ANDLconstmodify: return rewriteValueAMD64_OpAMD64ANDLconstmodify_0(v) case OpAMD64ANDLload: return rewriteValueAMD64_OpAMD64ANDLload_0(v) case OpAMD64ANDLmodify: return rewriteValueAMD64_OpAMD64ANDLmodify_0(v) case OpAMD64ANDQ: return rewriteValueAMD64_OpAMD64ANDQ_0(v) case OpAMD64ANDQconst: return rewriteValueAMD64_OpAMD64ANDQconst_0(v) case OpAMD64ANDQconstmodify: return rewriteValueAMD64_OpAMD64ANDQconstmodify_0(v) case OpAMD64ANDQload: return rewriteValueAMD64_OpAMD64ANDQload_0(v) case OpAMD64ANDQmodify: return rewriteValueAMD64_OpAMD64ANDQmodify_0(v) case OpAMD64BSFQ: return rewriteValueAMD64_OpAMD64BSFQ_0(v) case OpAMD64BTCLconst: return rewriteValueAMD64_OpAMD64BTCLconst_0(v) case OpAMD64BTCLconstmodify: return rewriteValueAMD64_OpAMD64BTCLconstmodify_0(v) case OpAMD64BTCLmodify: return rewriteValueAMD64_OpAMD64BTCLmodify_0(v) case OpAMD64BTCQconst: return rewriteValueAMD64_OpAMD64BTCQconst_0(v) case OpAMD64BTCQconstmodify: return rewriteValueAMD64_OpAMD64BTCQconstmodify_0(v) case OpAMD64BTCQmodify: return rewriteValueAMD64_OpAMD64BTCQmodify_0(v) case OpAMD64BTLconst: return rewriteValueAMD64_OpAMD64BTLconst_0(v) case OpAMD64BTQconst: return rewriteValueAMD64_OpAMD64BTQconst_0(v) case OpAMD64BTRLconst: return rewriteValueAMD64_OpAMD64BTRLconst_0(v) case OpAMD64BTRLconstmodify: return rewriteValueAMD64_OpAMD64BTRLconstmodify_0(v) case OpAMD64BTRLmodify: return rewriteValueAMD64_OpAMD64BTRLmodify_0(v) case OpAMD64BTRQconst: return rewriteValueAMD64_OpAMD64BTRQconst_0(v) case OpAMD64BTRQconstmodify: return rewriteValueAMD64_OpAMD64BTRQconstmodify_0(v) case OpAMD64BTRQmodify: return rewriteValueAMD64_OpAMD64BTRQmodify_0(v) case OpAMD64BTSLconst: return rewriteValueAMD64_OpAMD64BTSLconst_0(v) case OpAMD64BTSLconstmodify: return rewriteValueAMD64_OpAMD64BTSLconstmodify_0(v) case OpAMD64BTSLmodify: return rewriteValueAMD64_OpAMD64BTSLmodify_0(v) case OpAMD64BTSQconst: return rewriteValueAMD64_OpAMD64BTSQconst_0(v) case OpAMD64BTSQconstmodify: return rewriteValueAMD64_OpAMD64BTSQconstmodify_0(v) case OpAMD64BTSQmodify: return rewriteValueAMD64_OpAMD64BTSQmodify_0(v) case OpAMD64CMOVLCC: return rewriteValueAMD64_OpAMD64CMOVLCC_0(v) case OpAMD64CMOVLCS: return rewriteValueAMD64_OpAMD64CMOVLCS_0(v) case OpAMD64CMOVLEQ: return rewriteValueAMD64_OpAMD64CMOVLEQ_0(v) case OpAMD64CMOVLGE: return rewriteValueAMD64_OpAMD64CMOVLGE_0(v) case OpAMD64CMOVLGT: return rewriteValueAMD64_OpAMD64CMOVLGT_0(v) case OpAMD64CMOVLHI: return rewriteValueAMD64_OpAMD64CMOVLHI_0(v) case OpAMD64CMOVLLE: return rewriteValueAMD64_OpAMD64CMOVLLE_0(v) case OpAMD64CMOVLLS: return rewriteValueAMD64_OpAMD64CMOVLLS_0(v) case OpAMD64CMOVLLT: return rewriteValueAMD64_OpAMD64CMOVLLT_0(v) case OpAMD64CMOVLNE: return rewriteValueAMD64_OpAMD64CMOVLNE_0(v) case OpAMD64CMOVQCC: return rewriteValueAMD64_OpAMD64CMOVQCC_0(v) case OpAMD64CMOVQCS: return rewriteValueAMD64_OpAMD64CMOVQCS_0(v) case OpAMD64CMOVQEQ: return rewriteValueAMD64_OpAMD64CMOVQEQ_0(v) case OpAMD64CMOVQGE: return rewriteValueAMD64_OpAMD64CMOVQGE_0(v) case OpAMD64CMOVQGT: return rewriteValueAMD64_OpAMD64CMOVQGT_0(v) case OpAMD64CMOVQHI: return rewriteValueAMD64_OpAMD64CMOVQHI_0(v) case OpAMD64CMOVQLE: return rewriteValueAMD64_OpAMD64CMOVQLE_0(v) case OpAMD64CMOVQLS: return rewriteValueAMD64_OpAMD64CMOVQLS_0(v) case OpAMD64CMOVQLT: return rewriteValueAMD64_OpAMD64CMOVQLT_0(v) case OpAMD64CMOVQNE: return rewriteValueAMD64_OpAMD64CMOVQNE_0(v) case OpAMD64CMOVWCC: return rewriteValueAMD64_OpAMD64CMOVWCC_0(v) case OpAMD64CMOVWCS: return rewriteValueAMD64_OpAMD64CMOVWCS_0(v) case OpAMD64CMOVWEQ: return rewriteValueAMD64_OpAMD64CMOVWEQ_0(v) case OpAMD64CMOVWGE: return rewriteValueAMD64_OpAMD64CMOVWGE_0(v) case OpAMD64CMOVWGT: return rewriteValueAMD64_OpAMD64CMOVWGT_0(v) case OpAMD64CMOVWHI: return rewriteValueAMD64_OpAMD64CMOVWHI_0(v) case OpAMD64CMOVWLE: return rewriteValueAMD64_OpAMD64CMOVWLE_0(v) case OpAMD64CMOVWLS: return rewriteValueAMD64_OpAMD64CMOVWLS_0(v) case OpAMD64CMOVWLT: return rewriteValueAMD64_OpAMD64CMOVWLT_0(v) case OpAMD64CMOVWNE: return rewriteValueAMD64_OpAMD64CMOVWNE_0(v) case OpAMD64CMPB: return rewriteValueAMD64_OpAMD64CMPB_0(v) case OpAMD64CMPBconst: return rewriteValueAMD64_OpAMD64CMPBconst_0(v) case OpAMD64CMPBconstload: return rewriteValueAMD64_OpAMD64CMPBconstload_0(v) case OpAMD64CMPBload: return rewriteValueAMD64_OpAMD64CMPBload_0(v) case OpAMD64CMPL: return rewriteValueAMD64_OpAMD64CMPL_0(v) case OpAMD64CMPLconst: return rewriteValueAMD64_OpAMD64CMPLconst_0(v) || rewriteValueAMD64_OpAMD64CMPLconst_10(v) case OpAMD64CMPLconstload: return rewriteValueAMD64_OpAMD64CMPLconstload_0(v) case OpAMD64CMPLload: return rewriteValueAMD64_OpAMD64CMPLload_0(v) case OpAMD64CMPQ: return rewriteValueAMD64_OpAMD64CMPQ_0(v) case OpAMD64CMPQconst: return rewriteValueAMD64_OpAMD64CMPQconst_0(v) || rewriteValueAMD64_OpAMD64CMPQconst_10(v) case OpAMD64CMPQconstload: return rewriteValueAMD64_OpAMD64CMPQconstload_0(v) case OpAMD64CMPQload: return rewriteValueAMD64_OpAMD64CMPQload_0(v) case OpAMD64CMPW: return rewriteValueAMD64_OpAMD64CMPW_0(v) case OpAMD64CMPWconst: return rewriteValueAMD64_OpAMD64CMPWconst_0(v) case OpAMD64CMPWconstload: return rewriteValueAMD64_OpAMD64CMPWconstload_0(v) case OpAMD64CMPWload: return rewriteValueAMD64_OpAMD64CMPWload_0(v) case OpAMD64CMPXCHGLlock: return rewriteValueAMD64_OpAMD64CMPXCHGLlock_0(v) case OpAMD64CMPXCHGQlock: return rewriteValueAMD64_OpAMD64CMPXCHGQlock_0(v) case OpAMD64DIVSD: return rewriteValueAMD64_OpAMD64DIVSD_0(v) case OpAMD64DIVSDload: return rewriteValueAMD64_OpAMD64DIVSDload_0(v) case OpAMD64DIVSS: return rewriteValueAMD64_OpAMD64DIVSS_0(v) case OpAMD64DIVSSload: return rewriteValueAMD64_OpAMD64DIVSSload_0(v) case OpAMD64HMULL: return rewriteValueAMD64_OpAMD64HMULL_0(v) case OpAMD64HMULLU: return rewriteValueAMD64_OpAMD64HMULLU_0(v) case OpAMD64HMULQ: return rewriteValueAMD64_OpAMD64HMULQ_0(v) case OpAMD64HMULQU: return rewriteValueAMD64_OpAMD64HMULQU_0(v) case OpAMD64LEAL: return rewriteValueAMD64_OpAMD64LEAL_0(v) case OpAMD64LEAL1: return rewriteValueAMD64_OpAMD64LEAL1_0(v) case OpAMD64LEAL2: return rewriteValueAMD64_OpAMD64LEAL2_0(v) case OpAMD64LEAL4: return rewriteValueAMD64_OpAMD64LEAL4_0(v) case OpAMD64LEAL8: return rewriteValueAMD64_OpAMD64LEAL8_0(v) case OpAMD64LEAQ: return rewriteValueAMD64_OpAMD64LEAQ_0(v) case OpAMD64LEAQ1: return rewriteValueAMD64_OpAMD64LEAQ1_0(v) case OpAMD64LEAQ2: return rewriteValueAMD64_OpAMD64LEAQ2_0(v) case OpAMD64LEAQ4: return rewriteValueAMD64_OpAMD64LEAQ4_0(v) case OpAMD64LEAQ8: return rewriteValueAMD64_OpAMD64LEAQ8_0(v) case OpAMD64MOVBQSX: return rewriteValueAMD64_OpAMD64MOVBQSX_0(v) case OpAMD64MOVBQSXload: return rewriteValueAMD64_OpAMD64MOVBQSXload_0(v) case OpAMD64MOVBQZX: return rewriteValueAMD64_OpAMD64MOVBQZX_0(v) case OpAMD64MOVBatomicload: return rewriteValueAMD64_OpAMD64MOVBatomicload_0(v) case OpAMD64MOVBload: return rewriteValueAMD64_OpAMD64MOVBload_0(v) case OpAMD64MOVBloadidx1: return rewriteValueAMD64_OpAMD64MOVBloadidx1_0(v) case OpAMD64MOVBstore: return rewriteValueAMD64_OpAMD64MOVBstore_0(v) || rewriteValueAMD64_OpAMD64MOVBstore_10(v) || rewriteValueAMD64_OpAMD64MOVBstore_20(v) || rewriteValueAMD64_OpAMD64MOVBstore_30(v) case OpAMD64MOVBstoreconst: return rewriteValueAMD64_OpAMD64MOVBstoreconst_0(v) case OpAMD64MOVBstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVBstoreconstidx1_0(v) case OpAMD64MOVBstoreidx1: return rewriteValueAMD64_OpAMD64MOVBstoreidx1_0(v) || rewriteValueAMD64_OpAMD64MOVBstoreidx1_10(v) case OpAMD64MOVLQSX: return rewriteValueAMD64_OpAMD64MOVLQSX_0(v) case OpAMD64MOVLQSXload: return rewriteValueAMD64_OpAMD64MOVLQSXload_0(v) case OpAMD64MOVLQZX: return rewriteValueAMD64_OpAMD64MOVLQZX_0(v) case OpAMD64MOVLatomicload: return rewriteValueAMD64_OpAMD64MOVLatomicload_0(v) case OpAMD64MOVLf2i: return rewriteValueAMD64_OpAMD64MOVLf2i_0(v) case OpAMD64MOVLi2f: return rewriteValueAMD64_OpAMD64MOVLi2f_0(v) case OpAMD64MOVLload: return rewriteValueAMD64_OpAMD64MOVLload_0(v) || rewriteValueAMD64_OpAMD64MOVLload_10(v) case OpAMD64MOVLloadidx1: return rewriteValueAMD64_OpAMD64MOVLloadidx1_0(v) case OpAMD64MOVLloadidx4: return rewriteValueAMD64_OpAMD64MOVLloadidx4_0(v) case OpAMD64MOVLloadidx8: return rewriteValueAMD64_OpAMD64MOVLloadidx8_0(v) case OpAMD64MOVLstore: return rewriteValueAMD64_OpAMD64MOVLstore_0(v) || rewriteValueAMD64_OpAMD64MOVLstore_10(v) || rewriteValueAMD64_OpAMD64MOVLstore_20(v) || rewriteValueAMD64_OpAMD64MOVLstore_30(v) case OpAMD64MOVLstoreconst: return rewriteValueAMD64_OpAMD64MOVLstoreconst_0(v) case OpAMD64MOVLstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVLstoreconstidx1_0(v) case OpAMD64MOVLstoreconstidx4: return rewriteValueAMD64_OpAMD64MOVLstoreconstidx4_0(v) case OpAMD64MOVLstoreidx1: return rewriteValueAMD64_OpAMD64MOVLstoreidx1_0(v) case OpAMD64MOVLstoreidx4: return rewriteValueAMD64_OpAMD64MOVLstoreidx4_0(v) case OpAMD64MOVLstoreidx8: return rewriteValueAMD64_OpAMD64MOVLstoreidx8_0(v) case OpAMD64MOVOload: return rewriteValueAMD64_OpAMD64MOVOload_0(v) case OpAMD64MOVOstore: return rewriteValueAMD64_OpAMD64MOVOstore_0(v) case OpAMD64MOVQatomicload: return rewriteValueAMD64_OpAMD64MOVQatomicload_0(v) case OpAMD64MOVQf2i: return rewriteValueAMD64_OpAMD64MOVQf2i_0(v) case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f_0(v) case OpAMD64MOVQload: return rewriteValueAMD64_OpAMD64MOVQload_0(v) || rewriteValueAMD64_OpAMD64MOVQload_10(v) case OpAMD64MOVQloadidx1: return rewriteValueAMD64_OpAMD64MOVQloadidx1_0(v) case OpAMD64MOVQloadidx8: return rewriteValueAMD64_OpAMD64MOVQloadidx8_0(v) case OpAMD64MOVQstore: return rewriteValueAMD64_OpAMD64MOVQstore_0(v) || rewriteValueAMD64_OpAMD64MOVQstore_10(v) || rewriteValueAMD64_OpAMD64MOVQstore_20(v) || rewriteValueAMD64_OpAMD64MOVQstore_30(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst_0(v) case OpAMD64MOVQstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVQstoreconstidx1_0(v) case OpAMD64MOVQstoreconstidx8: return rewriteValueAMD64_OpAMD64MOVQstoreconstidx8_0(v) case OpAMD64MOVQstoreidx1: return rewriteValueAMD64_OpAMD64MOVQstoreidx1_0(v) case OpAMD64MOVQstoreidx8: return rewriteValueAMD64_OpAMD64MOVQstoreidx8_0(v) case OpAMD64MOVSDload: return rewriteValueAMD64_OpAMD64MOVSDload_0(v) case OpAMD64MOVSDloadidx1: return rewriteValueAMD64_OpAMD64MOVSDloadidx1_0(v) case OpAMD64MOVSDloadidx8: return rewriteValueAMD64_OpAMD64MOVSDloadidx8_0(v) case OpAMD64MOVSDstore: return rewriteValueAMD64_OpAMD64MOVSDstore_0(v) case OpAMD64MOVSDstoreidx1: return rewriteValueAMD64_OpAMD64MOVSDstoreidx1_0(v) case OpAMD64MOVSDstoreidx8: return rewriteValueAMD64_OpAMD64MOVSDstoreidx8_0(v) case OpAMD64MOVSSload: return rewriteValueAMD64_OpAMD64MOVSSload_0(v) case OpAMD64MOVSSloadidx1: return rewriteValueAMD64_OpAMD64MOVSSloadidx1_0(v) case OpAMD64MOVSSloadidx4: return rewriteValueAMD64_OpAMD64MOVSSloadidx4_0(v) case OpAMD64MOVSSstore: return rewriteValueAMD64_OpAMD64MOVSSstore_0(v) case OpAMD64MOVSSstoreidx1: return rewriteValueAMD64_OpAMD64MOVSSstoreidx1_0(v) case OpAMD64MOVSSstoreidx4: return rewriteValueAMD64_OpAMD64MOVSSstoreidx4_0(v) case OpAMD64MOVWQSX: return rewriteValueAMD64_OpAMD64MOVWQSX_0(v) case OpAMD64MOVWQSXload: return rewriteValueAMD64_OpAMD64MOVWQSXload_0(v) case OpAMD64MOVWQZX: return rewriteValueAMD64_OpAMD64MOVWQZX_0(v) case OpAMD64MOVWload: return rewriteValueAMD64_OpAMD64MOVWload_0(v) case OpAMD64MOVWloadidx1: return rewriteValueAMD64_OpAMD64MOVWloadidx1_0(v) case OpAMD64MOVWloadidx2: return rewriteValueAMD64_OpAMD64MOVWloadidx2_0(v) case OpAMD64MOVWstore: return rewriteValueAMD64_OpAMD64MOVWstore_0(v) || rewriteValueAMD64_OpAMD64MOVWstore_10(v) case OpAMD64MOVWstoreconst: return rewriteValueAMD64_OpAMD64MOVWstoreconst_0(v) case OpAMD64MOVWstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVWstoreconstidx1_0(v) case OpAMD64MOVWstoreconstidx2: return rewriteValueAMD64_OpAMD64MOVWstoreconstidx2_0(v) case OpAMD64MOVWstoreidx1: return rewriteValueAMD64_OpAMD64MOVWstoreidx1_0(v) case OpAMD64MOVWstoreidx2: return rewriteValueAMD64_OpAMD64MOVWstoreidx2_0(v) case OpAMD64MULL: return rewriteValueAMD64_OpAMD64MULL_0(v) case OpAMD64MULLconst: return rewriteValueAMD64_OpAMD64MULLconst_0(v) || rewriteValueAMD64_OpAMD64MULLconst_10(v) || rewriteValueAMD64_OpAMD64MULLconst_20(v) || rewriteValueAMD64_OpAMD64MULLconst_30(v) case OpAMD64MULQ: return rewriteValueAMD64_OpAMD64MULQ_0(v) case OpAMD64MULQconst: return rewriteValueAMD64_OpAMD64MULQconst_0(v) || rewriteValueAMD64_OpAMD64MULQconst_10(v) || rewriteValueAMD64_OpAMD64MULQconst_20(v) || rewriteValueAMD64_OpAMD64MULQconst_30(v) case OpAMD64MULSD: return rewriteValueAMD64_OpAMD64MULSD_0(v) case OpAMD64MULSDload: return rewriteValueAMD64_OpAMD64MULSDload_0(v) case OpAMD64MULSS: return rewriteValueAMD64_OpAMD64MULSS_0(v) case OpAMD64MULSSload: return rewriteValueAMD64_OpAMD64MULSSload_0(v) case OpAMD64NEGL: return rewriteValueAMD64_OpAMD64NEGL_0(v) case OpAMD64NEGQ: return rewriteValueAMD64_OpAMD64NEGQ_0(v) case OpAMD64NOTL: return rewriteValueAMD64_OpAMD64NOTL_0(v) case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ_0(v) case OpAMD64ORL: return rewriteValueAMD64_OpAMD64ORL_0(v) || rewriteValueAMD64_OpAMD64ORL_10(v) || rewriteValueAMD64_OpAMD64ORL_20(v) || rewriteValueAMD64_OpAMD64ORL_30(v) || rewriteValueAMD64_OpAMD64ORL_40(v) || rewriteValueAMD64_OpAMD64ORL_50(v) || rewriteValueAMD64_OpAMD64ORL_60(v) || rewriteValueAMD64_OpAMD64ORL_70(v) || rewriteValueAMD64_OpAMD64ORL_80(v) || rewriteValueAMD64_OpAMD64ORL_90(v) || rewriteValueAMD64_OpAMD64ORL_100(v) || rewriteValueAMD64_OpAMD64ORL_110(v) || rewriteValueAMD64_OpAMD64ORL_120(v) || rewriteValueAMD64_OpAMD64ORL_130(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst_0(v) case OpAMD64ORLconstmodify: return rewriteValueAMD64_OpAMD64ORLconstmodify_0(v) case OpAMD64ORLload: return rewriteValueAMD64_OpAMD64ORLload_0(v) case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify_0(v) case OpAMD64ORQ: return rewriteValueAMD64_OpAMD64ORQ_0(v) || rewriteValueAMD64_OpAMD64ORQ_10(v) || rewriteValueAMD64_OpAMD64ORQ_20(v) || rewriteValueAMD64_OpAMD64ORQ_30(v) || rewriteValueAMD64_OpAMD64ORQ_40(v) || rewriteValueAMD64_OpAMD64ORQ_50(v) || rewriteValueAMD64_OpAMD64ORQ_60(v) || rewriteValueAMD64_OpAMD64ORQ_70(v) || rewriteValueAMD64_OpAMD64ORQ_80(v) || rewriteValueAMD64_OpAMD64ORQ_90(v) || rewriteValueAMD64_OpAMD64ORQ_100(v) || rewriteValueAMD64_OpAMD64ORQ_110(v) || rewriteValueAMD64_OpAMD64ORQ_120(v) || rewriteValueAMD64_OpAMD64ORQ_130(v) || rewriteValueAMD64_OpAMD64ORQ_140(v) || rewriteValueAMD64_OpAMD64ORQ_150(v) || rewriteValueAMD64_OpAMD64ORQ_160(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst_0(v) case OpAMD64ORQconstmodify: return rewriteValueAMD64_OpAMD64ORQconstmodify_0(v) case OpAMD64ORQload: return rewriteValueAMD64_OpAMD64ORQload_0(v) case OpAMD64ORQmodify: return rewriteValueAMD64_OpAMD64ORQmodify_0(v) case OpAMD64ROLB: return rewriteValueAMD64_OpAMD64ROLB_0(v) case OpAMD64ROLBconst: return rewriteValueAMD64_OpAMD64ROLBconst_0(v) case OpAMD64ROLL: return rewriteValueAMD64_OpAMD64ROLL_0(v) case OpAMD64ROLLconst: return rewriteValueAMD64_OpAMD64ROLLconst_0(v) case OpAMD64ROLQ: return rewriteValueAMD64_OpAMD64ROLQ_0(v) case OpAMD64ROLQconst: return rewriteValueAMD64_OpAMD64ROLQconst_0(v) case OpAMD64ROLW: return rewriteValueAMD64_OpAMD64ROLW_0(v) case OpAMD64ROLWconst: return rewriteValueAMD64_OpAMD64ROLWconst_0(v) case OpAMD64RORB: return rewriteValueAMD64_OpAMD64RORB_0(v) case OpAMD64RORL: return rewriteValueAMD64_OpAMD64RORL_0(v) case OpAMD64RORQ: return rewriteValueAMD64_OpAMD64RORQ_0(v) case OpAMD64RORW: return rewriteValueAMD64_OpAMD64RORW_0(v) case OpAMD64SARB: return rewriteValueAMD64_OpAMD64SARB_0(v) case OpAMD64SARBconst: return rewriteValueAMD64_OpAMD64SARBconst_0(v) case OpAMD64SARL: return rewriteValueAMD64_OpAMD64SARL_0(v) case OpAMD64SARLconst: return rewriteValueAMD64_OpAMD64SARLconst_0(v) case OpAMD64SARQ: return rewriteValueAMD64_OpAMD64SARQ_0(v) case OpAMD64SARQconst: return rewriteValueAMD64_OpAMD64SARQconst_0(v) case OpAMD64SARW: return rewriteValueAMD64_OpAMD64SARW_0(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst_0(v) case OpAMD64SBBLcarrymask: return rewriteValueAMD64_OpAMD64SBBLcarrymask_0(v) case OpAMD64SBBQ: return rewriteValueAMD64_OpAMD64SBBQ_0(v) case OpAMD64SBBQcarrymask: return rewriteValueAMD64_OpAMD64SBBQcarrymask_0(v) case OpAMD64SBBQconst: return rewriteValueAMD64_OpAMD64SBBQconst_0(v) case OpAMD64SETA: return rewriteValueAMD64_OpAMD64SETA_0(v) case OpAMD64SETAE: return rewriteValueAMD64_OpAMD64SETAE_0(v) case OpAMD64SETAEstore: return rewriteValueAMD64_OpAMD64SETAEstore_0(v) case OpAMD64SETAstore: return rewriteValueAMD64_OpAMD64SETAstore_0(v) case OpAMD64SETB: return rewriteValueAMD64_OpAMD64SETB_0(v) case OpAMD64SETBE: return rewriteValueAMD64_OpAMD64SETBE_0(v) case OpAMD64SETBEstore: return rewriteValueAMD64_OpAMD64SETBEstore_0(v) case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore_0(v) case OpAMD64SETEQ: return rewriteValueAMD64_OpAMD64SETEQ_0(v) || rewriteValueAMD64_OpAMD64SETEQ_10(v) || rewriteValueAMD64_OpAMD64SETEQ_20(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore_0(v) || rewriteValueAMD64_OpAMD64SETEQstore_10(v) || rewriteValueAMD64_OpAMD64SETEQstore_20(v) case OpAMD64SETG: return rewriteValueAMD64_OpAMD64SETG_0(v) case OpAMD64SETGE: return rewriteValueAMD64_OpAMD64SETGE_0(v) case OpAMD64SETGEstore: return rewriteValueAMD64_OpAMD64SETGEstore_0(v) case OpAMD64SETGstore: return rewriteValueAMD64_OpAMD64SETGstore_0(v) case OpAMD64SETL: return rewriteValueAMD64_OpAMD64SETL_0(v) case OpAMD64SETLE: return rewriteValueAMD64_OpAMD64SETLE_0(v) case OpAMD64SETLEstore: return rewriteValueAMD64_OpAMD64SETLEstore_0(v) case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore_0(v) case OpAMD64SETNE: return rewriteValueAMD64_OpAMD64SETNE_0(v) || rewriteValueAMD64_OpAMD64SETNE_10(v) || rewriteValueAMD64_OpAMD64SETNE_20(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore_0(v) || rewriteValueAMD64_OpAMD64SETNEstore_10(v) || rewriteValueAMD64_OpAMD64SETNEstore_20(v) case OpAMD64SHLL: return rewriteValueAMD64_OpAMD64SHLL_0(v) case OpAMD64SHLLconst: return rewriteValueAMD64_OpAMD64SHLLconst_0(v) case OpAMD64SHLQ: return rewriteValueAMD64_OpAMD64SHLQ_0(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst_0(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB_0(v) case OpAMD64SHRBconst: return rewriteValueAMD64_OpAMD64SHRBconst_0(v) case OpAMD64SHRL: return rewriteValueAMD64_OpAMD64SHRL_0(v) case OpAMD64SHRLconst: return rewriteValueAMD64_OpAMD64SHRLconst_0(v) case OpAMD64SHRQ: return rewriteValueAMD64_OpAMD64SHRQ_0(v) case OpAMD64SHRQconst: return rewriteValueAMD64_OpAMD64SHRQconst_0(v) case OpAMD64SHRW: return rewriteValueAMD64_OpAMD64SHRW_0(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst_0(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL_0(v) case OpAMD64SUBLconst: return rewriteValueAMD64_OpAMD64SUBLconst_0(v) case OpAMD64SUBLload: return rewriteValueAMD64_OpAMD64SUBLload_0(v) case OpAMD64SUBLmodify: return rewriteValueAMD64_OpAMD64SUBLmodify_0(v) case OpAMD64SUBQ: return rewriteValueAMD64_OpAMD64SUBQ_0(v) case OpAMD64SUBQborrow: return rewriteValueAMD64_OpAMD64SUBQborrow_0(v) case OpAMD64SUBQconst: return rewriteValueAMD64_OpAMD64SUBQconst_0(v) case OpAMD64SUBQload: return rewriteValueAMD64_OpAMD64SUBQload_0(v) case OpAMD64SUBQmodify: return rewriteValueAMD64_OpAMD64SUBQmodify_0(v) case OpAMD64SUBSD: return rewriteValueAMD64_OpAMD64SUBSD_0(v) case OpAMD64SUBSDload: return rewriteValueAMD64_OpAMD64SUBSDload_0(v) case OpAMD64SUBSS: return rewriteValueAMD64_OpAMD64SUBSS_0(v) case OpAMD64SUBSSload: return rewriteValueAMD64_OpAMD64SUBSSload_0(v) case OpAMD64TESTB: return rewriteValueAMD64_OpAMD64TESTB_0(v) case OpAMD64TESTBconst: return rewriteValueAMD64_OpAMD64TESTBconst_0(v) case OpAMD64TESTL: return rewriteValueAMD64_OpAMD64TESTL_0(v) case OpAMD64TESTLconst: return rewriteValueAMD64_OpAMD64TESTLconst_0(v) case OpAMD64TESTQ: return rewriteValueAMD64_OpAMD64TESTQ_0(v) case OpAMD64TESTQconst: return rewriteValueAMD64_OpAMD64TESTQconst_0(v) case OpAMD64TESTW: return rewriteValueAMD64_OpAMD64TESTW_0(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst_0(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock_0(v) case OpAMD64XADDQlock: return rewriteValueAMD64_OpAMD64XADDQlock_0(v) case OpAMD64XCHGL: return rewriteValueAMD64_OpAMD64XCHGL_0(v) case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ_0(v) case OpAMD64XORL: return rewriteValueAMD64_OpAMD64XORL_0(v) || rewriteValueAMD64_OpAMD64XORL_10(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst_0(v) || rewriteValueAMD64_OpAMD64XORLconst_10(v) case OpAMD64XORLconstmodify: return rewriteValueAMD64_OpAMD64XORLconstmodify_0(v) case OpAMD64XORLload: return rewriteValueAMD64_OpAMD64XORLload_0(v) case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify_0(v) case OpAMD64XORQ: return rewriteValueAMD64_OpAMD64XORQ_0(v) || rewriteValueAMD64_OpAMD64XORQ_10(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst_0(v) case OpAMD64XORQconstmodify: return rewriteValueAMD64_OpAMD64XORQconstmodify_0(v) case OpAMD64XORQload: return rewriteValueAMD64_OpAMD64XORQload_0(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify_0(v) case OpAdd16: return rewriteValueAMD64_OpAdd16_0(v) case OpAdd32: return rewriteValueAMD64_OpAdd32_0(v) case OpAdd32F: return rewriteValueAMD64_OpAdd32F_0(v) case OpAdd64: return rewriteValueAMD64_OpAdd64_0(v) case OpAdd64F: return rewriteValueAMD64_OpAdd64F_0(v) case OpAdd8: return rewriteValueAMD64_OpAdd8_0(v) case OpAddPtr: return rewriteValueAMD64_OpAddPtr_0(v) case OpAddr: return rewriteValueAMD64_OpAddr_0(v) case OpAnd16: return rewriteValueAMD64_OpAnd16_0(v) case OpAnd32: return rewriteValueAMD64_OpAnd32_0(v) case OpAnd64: return rewriteValueAMD64_OpAnd64_0(v) case OpAnd8: return rewriteValueAMD64_OpAnd8_0(v) case OpAndB: return rewriteValueAMD64_OpAndB_0(v) case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32_0(v) case OpAtomicAdd64: return rewriteValueAMD64_OpAtomicAdd64_0(v) case OpAtomicAnd8: return rewriteValueAMD64_OpAtomicAnd8_0(v) case OpAtomicCompareAndSwap32: return rewriteValueAMD64_OpAtomicCompareAndSwap32_0(v) case OpAtomicCompareAndSwap64: return rewriteValueAMD64_OpAtomicCompareAndSwap64_0(v) case OpAtomicExchange32: return rewriteValueAMD64_OpAtomicExchange32_0(v) case OpAtomicExchange64: return rewriteValueAMD64_OpAtomicExchange64_0(v) case OpAtomicLoad32: return rewriteValueAMD64_OpAtomicLoad32_0(v) case OpAtomicLoad64: return rewriteValueAMD64_OpAtomicLoad64_0(v) case OpAtomicLoad8: return rewriteValueAMD64_OpAtomicLoad8_0(v) case OpAtomicLoadPtr: return rewriteValueAMD64_OpAtomicLoadPtr_0(v) case OpAtomicOr8: return rewriteValueAMD64_OpAtomicOr8_0(v) case OpAtomicStore32: return rewriteValueAMD64_OpAtomicStore32_0(v) case OpAtomicStore64: return rewriteValueAMD64_OpAtomicStore64_0(v) case OpAtomicStore8: return rewriteValueAMD64_OpAtomicStore8_0(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB_0(v) case OpAvg64u: return rewriteValueAMD64_OpAvg64u_0(v) case OpBitLen16: return rewriteValueAMD64_OpBitLen16_0(v) case OpBitLen32: return rewriteValueAMD64_OpBitLen32_0(v) case OpBitLen64: return rewriteValueAMD64_OpBitLen64_0(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8_0(v) case OpBswap32: return rewriteValueAMD64_OpBswap32_0(v) case OpBswap64: return rewriteValueAMD64_OpBswap64_0(v) case OpCeil: return rewriteValueAMD64_OpCeil_0(v) case OpClosureCall: return rewriteValueAMD64_OpClosureCall_0(v) case OpCom16: return rewriteValueAMD64_OpCom16_0(v) case OpCom32: return rewriteValueAMD64_OpCom32_0(v) case OpCom64: return rewriteValueAMD64_OpCom64_0(v) case OpCom8: return rewriteValueAMD64_OpCom8_0(v) case OpCondSelect: return rewriteValueAMD64_OpCondSelect_0(v) || rewriteValueAMD64_OpCondSelect_10(v) || rewriteValueAMD64_OpCondSelect_20(v) || rewriteValueAMD64_OpCondSelect_30(v) || rewriteValueAMD64_OpCondSelect_40(v) case OpConst16: return rewriteValueAMD64_OpConst16_0(v) case OpConst32: return rewriteValueAMD64_OpConst32_0(v) case OpConst32F: return rewriteValueAMD64_OpConst32F_0(v) case OpConst64: return rewriteValueAMD64_OpConst64_0(v) case OpConst64F: return rewriteValueAMD64_OpConst64F_0(v) case OpConst8: return rewriteValueAMD64_OpConst8_0(v) case OpConstBool: return rewriteValueAMD64_OpConstBool_0(v) case OpConstNil: return rewriteValueAMD64_OpConstNil_0(v) case OpCtz16: return rewriteValueAMD64_OpCtz16_0(v) case OpCtz16NonZero: return rewriteValueAMD64_OpCtz16NonZero_0(v) case OpCtz32: return rewriteValueAMD64_OpCtz32_0(v) case OpCtz32NonZero: return rewriteValueAMD64_OpCtz32NonZero_0(v) case OpCtz64: return rewriteValueAMD64_OpCtz64_0(v) case OpCtz64NonZero: return rewriteValueAMD64_OpCtz64NonZero_0(v) case OpCtz8: return rewriteValueAMD64_OpCtz8_0(v) case OpCtz8NonZero: return rewriteValueAMD64_OpCtz8NonZero_0(v) case OpCvt32Fto32: return rewriteValueAMD64_OpCvt32Fto32_0(v) case OpCvt32Fto64: return rewriteValueAMD64_OpCvt32Fto64_0(v) case OpCvt32Fto64F: return rewriteValueAMD64_OpCvt32Fto64F_0(v) case OpCvt32to32F: return rewriteValueAMD64_OpCvt32to32F_0(v) case OpCvt32to64F: return rewriteValueAMD64_OpCvt32to64F_0(v) case OpCvt64Fto32: return rewriteValueAMD64_OpCvt64Fto32_0(v) case OpCvt64Fto32F: return rewriteValueAMD64_OpCvt64Fto32F_0(v) case OpCvt64Fto64: return rewriteValueAMD64_OpCvt64Fto64_0(v) case OpCvt64to32F: return rewriteValueAMD64_OpCvt64to32F_0(v) case OpCvt64to64F: return rewriteValueAMD64_OpCvt64to64F_0(v) case OpDiv128u: return rewriteValueAMD64_OpDiv128u_0(v) case OpDiv16: return rewriteValueAMD64_OpDiv16_0(v) case OpDiv16u: return rewriteValueAMD64_OpDiv16u_0(v) case OpDiv32: return rewriteValueAMD64_OpDiv32_0(v) case OpDiv32F: return rewriteValueAMD64_OpDiv32F_0(v) case OpDiv32u: return rewriteValueAMD64_OpDiv32u_0(v) case OpDiv64: return rewriteValueAMD64_OpDiv64_0(v) case OpDiv64F: return rewriteValueAMD64_OpDiv64F_0(v) case OpDiv64u: return rewriteValueAMD64_OpDiv64u_0(v) case OpDiv8: return rewriteValueAMD64_OpDiv8_0(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u_0(v) case OpEq16: return rewriteValueAMD64_OpEq16_0(v) case OpEq32: return rewriteValueAMD64_OpEq32_0(v) case OpEq32F: return rewriteValueAMD64_OpEq32F_0(v) case OpEq64: return rewriteValueAMD64_OpEq64_0(v) case OpEq64F: return rewriteValueAMD64_OpEq64F_0(v) case OpEq8: return rewriteValueAMD64_OpEq8_0(v) case OpEqB: return rewriteValueAMD64_OpEqB_0(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr_0(v) case OpFMA: return rewriteValueAMD64_OpFMA_0(v) case OpFloor: return rewriteValueAMD64_OpFloor_0(v) case OpGeq16: return rewriteValueAMD64_OpGeq16_0(v) case OpGeq16U: return rewriteValueAMD64_OpGeq16U_0(v) case OpGeq32: return rewriteValueAMD64_OpGeq32_0(v) case OpGeq32F: return rewriteValueAMD64_OpGeq32F_0(v) case OpGeq32U: return rewriteValueAMD64_OpGeq32U_0(v) case OpGeq64: return rewriteValueAMD64_OpGeq64_0(v) case OpGeq64F: return rewriteValueAMD64_OpGeq64F_0(v) case OpGeq64U: return rewriteValueAMD64_OpGeq64U_0(v) case OpGeq8: return rewriteValueAMD64_OpGeq8_0(v) case OpGeq8U: return rewriteValueAMD64_OpGeq8U_0(v) case OpGetCallerPC: return rewriteValueAMD64_OpGetCallerPC_0(v) case OpGetCallerSP: return rewriteValueAMD64_OpGetCallerSP_0(v) case OpGetClosurePtr: return rewriteValueAMD64_OpGetClosurePtr_0(v) case OpGetG: return rewriteValueAMD64_OpGetG_0(v) case OpGreater16: return rewriteValueAMD64_OpGreater16_0(v) case OpGreater16U: return rewriteValueAMD64_OpGreater16U_0(v) case OpGreater32: return rewriteValueAMD64_OpGreater32_0(v) case OpGreater32F: return rewriteValueAMD64_OpGreater32F_0(v) case OpGreater32U: return rewriteValueAMD64_OpGreater32U_0(v) case OpGreater64: return rewriteValueAMD64_OpGreater64_0(v) case OpGreater64F: return rewriteValueAMD64_OpGreater64F_0(v) case OpGreater64U: return rewriteValueAMD64_OpGreater64U_0(v) case OpGreater8: return rewriteValueAMD64_OpGreater8_0(v) case OpGreater8U: return rewriteValueAMD64_OpGreater8U_0(v) case OpHmul32: return rewriteValueAMD64_OpHmul32_0(v) case OpHmul32u: return rewriteValueAMD64_OpHmul32u_0(v) case OpHmul64: return rewriteValueAMD64_OpHmul64_0(v) case OpHmul64u: return rewriteValueAMD64_OpHmul64u_0(v) case OpInterCall: return rewriteValueAMD64_OpInterCall_0(v) case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds_0(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil_0(v) case OpIsSliceInBounds: return rewriteValueAMD64_OpIsSliceInBounds_0(v) case OpLeq16: return rewriteValueAMD64_OpLeq16_0(v) case OpLeq16U: return rewriteValueAMD64_OpLeq16U_0(v) case OpLeq32: return rewriteValueAMD64_OpLeq32_0(v) case OpLeq32F: return rewriteValueAMD64_OpLeq32F_0(v) case OpLeq32U: return rewriteValueAMD64_OpLeq32U_0(v) case OpLeq64: return rewriteValueAMD64_OpLeq64_0(v) case OpLeq64F: return rewriteValueAMD64_OpLeq64F_0(v) case OpLeq64U: return rewriteValueAMD64_OpLeq64U_0(v) case OpLeq8: return rewriteValueAMD64_OpLeq8_0(v) case OpLeq8U: return rewriteValueAMD64_OpLeq8U_0(v) case OpLess16: return rewriteValueAMD64_OpLess16_0(v) case OpLess16U: return rewriteValueAMD64_OpLess16U_0(v) case OpLess32: return rewriteValueAMD64_OpLess32_0(v) case OpLess32F: return rewriteValueAMD64_OpLess32F_0(v) case OpLess32U: return rewriteValueAMD64_OpLess32U_0(v) case OpLess64: return rewriteValueAMD64_OpLess64_0(v) case OpLess64F: return rewriteValueAMD64_OpLess64F_0(v) case OpLess64U: return rewriteValueAMD64_OpLess64U_0(v) case OpLess8: return rewriteValueAMD64_OpLess8_0(v) case OpLess8U: return rewriteValueAMD64_OpLess8U_0(v) case OpLoad: return rewriteValueAMD64_OpLoad_0(v) case OpLocalAddr: return rewriteValueAMD64_OpLocalAddr_0(v) case OpLsh16x16: return rewriteValueAMD64_OpLsh16x16_0(v) case OpLsh16x32: return rewriteValueAMD64_OpLsh16x32_0(v) case OpLsh16x64: return rewriteValueAMD64_OpLsh16x64_0(v) case OpLsh16x8: return rewriteValueAMD64_OpLsh16x8_0(v) case OpLsh32x16: return rewriteValueAMD64_OpLsh32x16_0(v) case OpLsh32x32: return rewriteValueAMD64_OpLsh32x32_0(v) case OpLsh32x64: return rewriteValueAMD64_OpLsh32x64_0(v) case OpLsh32x8: return rewriteValueAMD64_OpLsh32x8_0(v) case OpLsh64x16: return rewriteValueAMD64_OpLsh64x16_0(v) case OpLsh64x32: return rewriteValueAMD64_OpLsh64x32_0(v) case OpLsh64x64: return rewriteValueAMD64_OpLsh64x64_0(v) case OpLsh64x8: return rewriteValueAMD64_OpLsh64x8_0(v) case OpLsh8x16: return rewriteValueAMD64_OpLsh8x16_0(v) case OpLsh8x32: return rewriteValueAMD64_OpLsh8x32_0(v) case OpLsh8x64: return rewriteValueAMD64_OpLsh8x64_0(v) case OpLsh8x8: return rewriteValueAMD64_OpLsh8x8_0(v) case OpMod16: return rewriteValueAMD64_OpMod16_0(v) case OpMod16u: return rewriteValueAMD64_OpMod16u_0(v) case OpMod32: return rewriteValueAMD64_OpMod32_0(v) case OpMod32u: return rewriteValueAMD64_OpMod32u_0(v) case OpMod64: return rewriteValueAMD64_OpMod64_0(v) case OpMod64u: return rewriteValueAMD64_OpMod64u_0(v) case OpMod8: return rewriteValueAMD64_OpMod8_0(v) case OpMod8u: return rewriteValueAMD64_OpMod8u_0(v) case OpMove: return rewriteValueAMD64_OpMove_0(v) || rewriteValueAMD64_OpMove_10(v) || rewriteValueAMD64_OpMove_20(v) case OpMul16: return rewriteValueAMD64_OpMul16_0(v) case OpMul32: return rewriteValueAMD64_OpMul32_0(v) case OpMul32F: return rewriteValueAMD64_OpMul32F_0(v) case OpMul64: return rewriteValueAMD64_OpMul64_0(v) case OpMul64F: return rewriteValueAMD64_OpMul64F_0(v) case OpMul64uhilo: return rewriteValueAMD64_OpMul64uhilo_0(v) case OpMul8: return rewriteValueAMD64_OpMul8_0(v) case OpNeg16: return rewriteValueAMD64_OpNeg16_0(v) case OpNeg32: return rewriteValueAMD64_OpNeg32_0(v) case OpNeg32F: return rewriteValueAMD64_OpNeg32F_0(v) case OpNeg64: return rewriteValueAMD64_OpNeg64_0(v) case OpNeg64F: return rewriteValueAMD64_OpNeg64F_0(v) case OpNeg8: return rewriteValueAMD64_OpNeg8_0(v) case OpNeq16: return rewriteValueAMD64_OpNeq16_0(v) case OpNeq32: return rewriteValueAMD64_OpNeq32_0(v) case OpNeq32F: return rewriteValueAMD64_OpNeq32F_0(v) case OpNeq64: return rewriteValueAMD64_OpNeq64_0(v) case OpNeq64F: return rewriteValueAMD64_OpNeq64F_0(v) case OpNeq8: return rewriteValueAMD64_OpNeq8_0(v) case OpNeqB: return rewriteValueAMD64_OpNeqB_0(v) case OpNeqPtr: return rewriteValueAMD64_OpNeqPtr_0(v) case OpNilCheck: return rewriteValueAMD64_OpNilCheck_0(v) case OpNot: return rewriteValueAMD64_OpNot_0(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr_0(v) case OpOr16: return rewriteValueAMD64_OpOr16_0(v) case OpOr32: return rewriteValueAMD64_OpOr32_0(v) case OpOr64: return rewriteValueAMD64_OpOr64_0(v) case OpOr8: return rewriteValueAMD64_OpOr8_0(v) case OpOrB: return rewriteValueAMD64_OpOrB_0(v) case OpPanicBounds: return rewriteValueAMD64_OpPanicBounds_0(v) case OpPopCount16: return rewriteValueAMD64_OpPopCount16_0(v) case OpPopCount32: return rewriteValueAMD64_OpPopCount32_0(v) case OpPopCount64: return rewriteValueAMD64_OpPopCount64_0(v) case OpPopCount8: return rewriteValueAMD64_OpPopCount8_0(v) case OpRotateLeft16: return rewriteValueAMD64_OpRotateLeft16_0(v) case OpRotateLeft32: return rewriteValueAMD64_OpRotateLeft32_0(v) case OpRotateLeft64: return rewriteValueAMD64_OpRotateLeft64_0(v) case OpRotateLeft8: return rewriteValueAMD64_OpRotateLeft8_0(v) case OpRound32F: return rewriteValueAMD64_OpRound32F_0(v) case OpRound64F: return rewriteValueAMD64_OpRound64F_0(v) case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven_0(v) case OpRsh16Ux16: return rewriteValueAMD64_OpRsh16Ux16_0(v) case OpRsh16Ux32: return rewriteValueAMD64_OpRsh16Ux32_0(v) case OpRsh16Ux64: return rewriteValueAMD64_OpRsh16Ux64_0(v) case OpRsh16Ux8: return rewriteValueAMD64_OpRsh16Ux8_0(v) case OpRsh16x16: return rewriteValueAMD64_OpRsh16x16_0(v) case OpRsh16x32: return rewriteValueAMD64_OpRsh16x32_0(v) case OpRsh16x64: return rewriteValueAMD64_OpRsh16x64_0(v) case OpRsh16x8: return rewriteValueAMD64_OpRsh16x8_0(v) case OpRsh32Ux16: return rewriteValueAMD64_OpRsh32Ux16_0(v) case OpRsh32Ux32: return rewriteValueAMD64_OpRsh32Ux32_0(v) case OpRsh32Ux64: return rewriteValueAMD64_OpRsh32Ux64_0(v) case OpRsh32Ux8: return rewriteValueAMD64_OpRsh32Ux8_0(v) case OpRsh32x16: return rewriteValueAMD64_OpRsh32x16_0(v) case OpRsh32x32: return rewriteValueAMD64_OpRsh32x32_0(v) case OpRsh32x64: return rewriteValueAMD64_OpRsh32x64_0(v) case OpRsh32x8: return rewriteValueAMD64_OpRsh32x8_0(v) case OpRsh64Ux16: return rewriteValueAMD64_OpRsh64Ux16_0(v) case OpRsh64Ux32: return rewriteValueAMD64_OpRsh64Ux32_0(v) case OpRsh64Ux64: return rewriteValueAMD64_OpRsh64Ux64_0(v) case OpRsh64Ux8: return rewriteValueAMD64_OpRsh64Ux8_0(v) case OpRsh64x16: return rewriteValueAMD64_OpRsh64x16_0(v) case OpRsh64x32: return rewriteValueAMD64_OpRsh64x32_0(v) case OpRsh64x64: return rewriteValueAMD64_OpRsh64x64_0(v) case OpRsh64x8: return rewriteValueAMD64_OpRsh64x8_0(v) case OpRsh8Ux16: return rewriteValueAMD64_OpRsh8Ux16_0(v) case OpRsh8Ux32: return rewriteValueAMD64_OpRsh8Ux32_0(v) case OpRsh8Ux64: return rewriteValueAMD64_OpRsh8Ux64_0(v) case OpRsh8Ux8: return rewriteValueAMD64_OpRsh8Ux8_0(v) case OpRsh8x16: return rewriteValueAMD64_OpRsh8x16_0(v) case OpRsh8x32: return rewriteValueAMD64_OpRsh8x32_0(v) case OpRsh8x64: return rewriteValueAMD64_OpRsh8x64_0(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8_0(v) case OpSelect0: return rewriteValueAMD64_OpSelect0_0(v) case OpSelect1: return rewriteValueAMD64_OpSelect1_0(v) case OpSignExt16to32: return rewriteValueAMD64_OpSignExt16to32_0(v) case OpSignExt16to64: return rewriteValueAMD64_OpSignExt16to64_0(v) case OpSignExt32to64: return rewriteValueAMD64_OpSignExt32to64_0(v) case OpSignExt8to16: return rewriteValueAMD64_OpSignExt8to16_0(v) case OpSignExt8to32: return rewriteValueAMD64_OpSignExt8to32_0(v) case OpSignExt8to64: return rewriteValueAMD64_OpSignExt8to64_0(v) case OpSlicemask: return rewriteValueAMD64_OpSlicemask_0(v) case OpSqrt: return rewriteValueAMD64_OpSqrt_0(v) case OpStaticCall: return rewriteValueAMD64_OpStaticCall_0(v) case OpStore: return rewriteValueAMD64_OpStore_0(v) case OpSub16: return rewriteValueAMD64_OpSub16_0(v) case OpSub32: return rewriteValueAMD64_OpSub32_0(v) case OpSub32F: return rewriteValueAMD64_OpSub32F_0(v) case OpSub64: return rewriteValueAMD64_OpSub64_0(v) case OpSub64F: return rewriteValueAMD64_OpSub64F_0(v) case OpSub8: return rewriteValueAMD64_OpSub8_0(v) case OpSubPtr: return rewriteValueAMD64_OpSubPtr_0(v) case OpTrunc: return rewriteValueAMD64_OpTrunc_0(v) case OpTrunc16to8: return rewriteValueAMD64_OpTrunc16to8_0(v) case OpTrunc32to16: return rewriteValueAMD64_OpTrunc32to16_0(v) case OpTrunc32to8: return rewriteValueAMD64_OpTrunc32to8_0(v) case OpTrunc64to16: return rewriteValueAMD64_OpTrunc64to16_0(v) case OpTrunc64to32: return rewriteValueAMD64_OpTrunc64to32_0(v) case OpTrunc64to8: return rewriteValueAMD64_OpTrunc64to8_0(v) case OpWB: return rewriteValueAMD64_OpWB_0(v) case OpXor16: return rewriteValueAMD64_OpXor16_0(v) case OpXor32: return rewriteValueAMD64_OpXor32_0(v) case OpXor64: return rewriteValueAMD64_OpXor64_0(v) case OpXor8: return rewriteValueAMD64_OpXor8_0(v) case OpZero: return rewriteValueAMD64_OpZero_0(v) || rewriteValueAMD64_OpZero_10(v) || rewriteValueAMD64_OpZero_20(v) case OpZeroExt16to32: return rewriteValueAMD64_OpZeroExt16to32_0(v) case OpZeroExt16to64: return rewriteValueAMD64_OpZeroExt16to64_0(v) case OpZeroExt32to64: return rewriteValueAMD64_OpZeroExt32to64_0(v) case OpZeroExt8to16: return rewriteValueAMD64_OpZeroExt8to16_0(v) case OpZeroExt8to32: return rewriteValueAMD64_OpZeroExt8to32_0(v) case OpZeroExt8to64: return rewriteValueAMD64_OpZeroExt8to64_0(v) } return false } func rewriteValueAMD64_OpAMD64ADCQ_0(v *Value) bool { // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) // result: (ADCQconst x [c] carry) for { carry := v.Args[2] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ADCQconst) v.AuxInt = c v.AddArg(x) v.AddArg(carry) return true } // match: (ADCQ (MOVQconst [c]) x carry) // cond: is32Bit(c) // result: (ADCQconst x [c] carry) for { carry := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt x := v.Args[1] if !(is32Bit(c)) { break } v.reset(OpAMD64ADCQconst) v.AuxInt = c v.AddArg(x) v.AddArg(carry) return true } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) for { _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQcarry) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ADCQconst_0(v *Value) bool { // match: (ADCQconst x [c] (FlagEQ)) // result: (ADDQconstcarry x [c]) for { c := v.AuxInt _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL_0(v *Value) bool { // match: (ADDL x (MOVLconst [c])) // result: (ADDLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64ADDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (MOVLconst [c]) x) // result: (ADDLconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64ADDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHRLconst x [d]) (SHLLconst x [c])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { break } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHRWconst x [d]) (SHLLconst x [c])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { break } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRBconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { break } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHRBconst x [d]) (SHLLconst x [c])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRBconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { break } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (SHLLconst [3] y) x) // result: (LEAL8 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 3 { break } y := v_0.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ADDL_10(v *Value) bool { // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (SHLLconst [2] y) x) // result: (LEAL4 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 2 { break } y := v_0.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (SHLLconst [1] y) x) // result: (LEAL2 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { break } y := v_0.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDL { break } y := v_1.Args[1] if y != v_1.Args[0] { break } v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (ADDL y y) x) // result: (LEAL2 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] if y != v_0.Args[0] { break } v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDL { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpAMD64LEAL2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDL x (ADDL y x)) // result: (LEAL2 y x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDL { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpAMD64LEAL2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDL (ADDL x y) x) // result: (LEAL2 y x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpAMD64LEAL2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDL (ADDL y x) x) // result: (LEAL2 y x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpAMD64LEAL2) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL_20(v *Value) bool { // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDL y (ADDLconst [c] x)) // result: (LEAL1 [c] x y) for { _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt x := v_1.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAL { break } c := v_1.AuxInt s := v_1.Aux y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (LEAL [c] {s} y) x) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } c := v_0.AuxInt s := v_0.Aux y := v_0.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } y := v_1.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (NEGL y) x) // result: (SUBL x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64NEGL { break } y := v_0.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconst_0(v *Value) bool { // match: (ADDLconst [c] (ADDL x y)) // result: (LEAL1 [c] x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (SHLLconst [1] x)) // result: (LEAL1 [c] x x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(c+d) // result: (LEAL [c+d] {s} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } d := v_0.AuxInt s := v_0.Aux x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL1 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL2 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL2 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL4 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL4 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL8 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL8 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] x) // cond: int32(c)==0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // result: (MOVLconst [int64(int32(c+d))]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = int64(int32(c + d)) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // result: (ADDLconst [int64(int32(c+d))] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int64(int32(c + d)) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconst_10(v *Value) bool { // match: (ADDLconst [off] x:(SP)) // result: (LEAL [off] x) for { off := v.AuxInt x := v.Args[0] if x.Op != OpSP { break } v.reset(OpAMD64LEAL) v.AuxInt = off v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconstmodify_0(v *Value) bool { // match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (ADDL x (MOVLf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSSstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDL) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDLmodify_0(v *Value) bool { // match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ_0(v *Value) bool { // match: (ADDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (ADDQconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDQ (SHRQconst x [d]) (SHLQconst x [c])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ (SHLQconst [3] y) x) // result: (LEAQ8 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { break } y := v_0.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ (SHLQconst [2] y) x) // result: (LEAQ4 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 { break } y := v_0.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ (SHLQconst [1] y) x) // result: (LEAQ2 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } y := v_0.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ_10(v *Value) bool { // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQ { break } y := v_1.Args[1] if y != v_1.Args[0] { break } v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ (ADDQ y y) x) // result: (LEAQ2 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] if y != v_0.Args[0] { break } v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQ { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpAMD64LEAQ2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDQ x (ADDQ y x)) // result: (LEAQ2 y x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQ { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpAMD64LEAQ2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDQ (ADDQ x y) x) // result: (LEAQ2 y x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpAMD64LEAQ2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDQ (ADDQ y x) x) // result: (LEAQ2 y x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpAMD64LEAQ2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ y (ADDQconst [c] x)) // result: (LEAQ1 [c] x y) for { _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt x := v_1.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } c := v_1.AuxInt s := v_1.Aux y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ (LEAQ [c] {s} y) x) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } c := v_0.AuxInt s := v_0.Aux y := v_0.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ_20(v *Value) bool { // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } y := v_1.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ (NEGQ y) x) // result: (SUBQ x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64NEGQ { break } y := v_0.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQcarry_0(v *Value) bool { // match: (ADDQcarry x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconstcarry x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = c v.AddArg(x) return true } // match: (ADDQcarry (MOVQconst [c]) x) // cond: is32Bit(c) // result: (ADDQconstcarry x [c]) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconst_0(v *Value) bool { // match: (ADDQconst [c] (ADDQ x y)) // result: (LEAQ1 [c] x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (SHLQconst [1] x)) // result: (LEAQ1 [c] x x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ [d] {s} x)) // cond: is32Bit(c+d) // result: (LEAQ [c+d] {s} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } d := v_0.AuxInt s := v_0.Aux x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ1 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ1 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (LEAQ2 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ2 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (LEAQ4 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ4 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (LEAQ8 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ8 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDQconst [c] (MOVQconst [d])) // result: (MOVQconst [c+d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = c + d return true } // match: (ADDQconst [c] (ADDQconst [d] x)) // cond: is32Bit(c+d) // result: (ADDQconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = c + d v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconst_10(v *Value) bool { // match: (ADDQconst [off] x:(SP)) // result: (LEAQ [off] x) for { off := v.AuxInt x := v.Args[0] if x.Op != OpSP { break } v.reset(OpAMD64LEAQ) v.AuxInt = off v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconstmodify_0(v *Value) bool { // match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ADDQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (ADDQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDQload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (ADDQ x (MOVQf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSDstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDQ) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDQmodify_0(v *Value) bool { // match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ADDQmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSD_0(v *Value) bool { // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDSD l:(MOVSDload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSDload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (ADDSD x (MOVQi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVQstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDSD) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDSS_0(v *Value) bool { // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDSS l:(MOVSSload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSSload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (ADDSS x (MOVLi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVLstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDSS) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ANDL_0(v *Value) bool { // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64NOTL { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { break } v.reset(OpAMD64BTRL) v.AddArg(x) v.AddArg(y) return true } // match: (ANDL x (NOTL (SHLL (MOVLconst [1]) y))) // result: (BTRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NOTL { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLL { break } y := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { break } v.reset(OpAMD64BTRL) v.AddArg(x) v.AddArg(y) return true } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRLconst [log2uint32(^c)] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = log2uint32(^c) v.AddArg(x) return true } // match: (ANDL x (MOVLconst [c])) // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRLconst [log2uint32(^c)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = log2uint32(^c) v.AddArg(x) return true } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64ANDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ANDL (MOVLconst [c]) x) // result: (ANDLconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64ANDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ANDL x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ANDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ANDL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ANDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ANDLconst_0(v *Value) bool { // match: (ANDLconst [c] x) // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRLconst [log2uint32(^c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = log2uint32(^c) v.AddArg(x) return true } // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDLconst [c] (BTRLconst [d] x)) // result: (ANDLconst [c &^ (1<= 128 // result: (BTRQconst [log2(^c)] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = log2(^c) v.AddArg(x) return true } // match: (ANDQ x (MOVQconst [c])) // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRQconst [log2(^c)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = log2(^c) v.AddArg(x) return true } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ANDQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ANDQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (ANDQconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ANDQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ANDQ x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ANDQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ANDQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ANDQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ANDQconst_0(v *Value) bool { // match: (ANDQconst [c] x) // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRQconst [log2(^c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = log2(^c) v.AddArg(x) return true } // match: (ANDQconst [c] (ANDQconst [d] x)) // result: (ANDQconst [c & d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDQconst [c] (BTRQconst [d] x)) // result: (ANDQconst [c &^ (1< [1<<8] (MOVBQZX x))) // result: (BSFQ (ORQconst [1<<8] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if v_0.AuxInt != 1<<8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVBQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = 1 << 8 v0.AddArg(x) v.AddArg(v0) return true } // match: (BSFQ (ORQconst [1<<16] (MOVWQZX x))) // result: (BSFQ (ORQconst [1<<16] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if v_0.AuxInt != 1<<16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVWQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = 1 << 16 v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64BTCLconst_0(v *Value) bool { // match: (BTCLconst [c] (XORLconst [d] x)) // result: (XORLconst [d ^ 1<d // result: (BTLconst [c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = c - d v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if v.AuxInt != 0 { break } s := v.Args[0] if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg(y) v.AddArg(x) return true } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !((c + d) < 32) { break } v.reset(OpAMD64BTLconst) v.AuxInt = c + d v.AddArg(x) return true } // match: (BTLconst [c] (SHLLconst [d] x)) // cond: c>d // result: (BTLconst [c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = c - d v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRL x y)) // result: (BTL y x) for { if v.AuxInt != 0 { break } s := v.Args[0] if s.Op != OpAMD64SHRL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64BTQconst_0(v *Value) bool { // match: (BTQconst [c] (SHRQconst [d] x)) // cond: (c+d)<64 // result: (BTQconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !((c + d) < 64) { break } v.reset(OpAMD64BTQconst) v.AuxInt = c + d v.AddArg(x) return true } // match: (BTQconst [c] (SHLQconst [d] x)) // cond: c>d // result: (BTQconst [c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTQconst) v.AuxInt = c - d v.AddArg(x) return true } // match: (BTQconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if v.AuxInt != 0 { break } s := v.Args[0] if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64BTRLconst_0(v *Value) bool { // match: (BTRLconst [c] (BTSLconst [c] x)) // result: (BTRLconst [c] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64BTSLconst || v_0.AuxInt != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = c v.AddArg(x) return true } // match: (BTRLconst [c] (BTCLconst [c] x)) // result: (BTRLconst [c] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64BTCLconst || v_0.AuxInt != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = c v.AddArg(x) return true } // match: (BTRLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [d &^ (1<uint8(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int8(x) < int8(y) && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>int8(y) && uint8(x) int8(y) && uint8(x) < uint8(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>int8(y) && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int8(x) > int8(y) && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < int8(n) // result: (FlagLT_ULT) for { n := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } m := v_0.AuxInt if !(0 <= int8(m) && int8(m) < int8(n)) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPBconst (ANDL x y) [0]) // result: (TESTB x y) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64TESTB) v.AddArg(x) v.AddArg(y) return true } // match: (CMPBconst (ANDLconst [c] x) [0]) // result: (TESTBconst [int64(int8(c))] x) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64TESTBconst) v.AuxInt = int64(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // result: (TESTB x x) for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpAMD64TESTB) v.AddArg(x) v.AddArg(x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(c,off)] ptr mem) for { c := v.AuxInt l := v.Args[0] if l.Op != OpAMD64MOVBload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(c, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconstload_0(v *Value) bool { // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (CMPBconstload [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (CMPBconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBload_0(v *Value) bool { // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (CMPBload [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // cond: validValAndOff(int64(int8(c)),off) // result: (CMPBconstload {sym} [makeValAndOff(int64(int8(c)),off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validValAndOff(int64(int8(c)), off)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPL_0(v *Value) bool { b := v.Block // match: (CMPL x (MOVLconst [c])) // result: (CMPLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64CMPLconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // result: (InvertFlags (CMPLconst x [c])) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPLload) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(x) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPLconst_0(v *Value) bool { // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)uint32(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int32(x) < int32(y) && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)>int32(y) && uint32(x) int32(y) && uint32(x) < uint32(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)>int32(y) && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int32(x) > int32(y) && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } x := v_0.AuxInt if !(x < y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>y && uint64(x)>uint64(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } x := v_0.AuxInt if !(x > y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQconst (MOVBQZX _) [c]) // cond: 0xFF < c // result: (FlagLT_ULT) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVWQZX _) [c]) // cond: 0xFFFF < c // result: (FlagLT_ULT) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVLQZX _) [c]) // cond: 0xFFFFFFFF < c // result: (FlagLT_ULT) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLQZX || !(0xFFFFFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } return false } func rewriteValueAMD64_OpAMD64CMPQconst_10(v *Value) bool { b := v.Block // match: (CMPQconst (SHRQconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 64 && (1<uint16(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int16(x) < int16(y) && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>int16(y) && uint16(x) int16(y) && uint16(x) < uint16(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>int16(y) && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int16(x) > int16(y) && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < int16(n) // result: (FlagLT_ULT) for { n := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } m := v_0.AuxInt if !(0 <= int16(m) && int16(m) < int16(n)) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPWconst (ANDL x y) [0]) // result: (TESTW x y) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64TESTW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWconst (ANDLconst [c] x) [0]) // result: (TESTWconst [int64(int16(c))] x) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64TESTWconst) v.AuxInt = int64(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // result: (TESTW x x) for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpAMD64TESTW) v.AddArg(x) v.AddArg(x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(c,off)] ptr mem) for { c := v.AuxInt l := v.Args[0] if l.Op != OpAMD64MOVWload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(c, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWconstload_0(v *Value) bool { // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (CMPWconstload [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (CMPWconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWload_0(v *Value) bool { // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (CMPWload [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // cond: validValAndOff(int64(int16(c)),off) // result: (CMPWconstload {sym} [makeValAndOff(int64(int16(c)),off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validValAndOff(int64(int16(c)), off)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGLlock_0(v *Value) bool { // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(off1+off2) // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] old := v.Args[1] new_ := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPXCHGLlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGQlock_0(v *Value) bool { // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(off1+off2) // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] old := v.Args[1] new_ := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPXCHGQlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSD_0(v *Value) bool { // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSDload_0(v *Value) bool { // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSS_0(v *Value) bool { // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSSload_0(v *Value) bool { // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64HMULL_0(v *Value) bool { // match: (HMULL x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULL y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULL) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64HMULLU_0(v *Value) bool { // match: (HMULLU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULLU y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULLU) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQ_0(v *Value) bool { // match: (HMULQ x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQ y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQ) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQU_0(v *Value) bool { // match: (HMULQU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQU y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQU) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAL_0(v *Value) bool { // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(c+d) // result: (LEAL [c+d] {s} x) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL [c] {s} (ADDL y x)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } x := v_0.Args[1] y := v_0.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL1_0(v *Value) bool { // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} y (ADDLconst [d] x)) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt x := v_1.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} (SHLLconst [1] y) x) // result: (LEAL2 [c] {s} x y) for { c := v.AuxInt s := v.Aux x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { break } y := v_0.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} (SHLLconst [2] y) x) // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 2 { break } y := v_0.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} (SHLLconst [3] y) x) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 3 { break } y := v_0.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL2_0(v *Value) bool { // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+2*d) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+2*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = c + 2*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL4_0(v *Value) bool { // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+4*d) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+4*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = c + 4*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL8_0(v *Value) bool { // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+8*d) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+8*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = c + 8*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ_0(v *Value) bool { // match: (LEAQ [c] {s} (ADDQconst [d] x)) // cond: is32Bit(c+d) // result: (LEAQ [c+d] {s} x) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (LEAQ [c] {s} (ADDQ x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [c] {s} (ADDQ y x)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } x := v_0.Args[1] y := v_0.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) return true } // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ1_0(v *Value) bool { // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} y (ADDQconst [d] x)) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt x := v_1.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} (SHLQconst [1] y) x) // result: (LEAQ2 [c] {s} x y) for { c := v.AuxInt s := v.Aux x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } y := v_0.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} (SHLQconst [2] y) x) // result: (LEAQ4 [c] {s} x y) for { c := v.AuxInt s := v.Aux x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 { break } y := v_0.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} (SHLQconst [3] y) x) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { break } y := v_0.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [off1] {sym1} y (LEAQ [off2] {sym2} x)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux x := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ2_0(v *Value) bool { // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ2 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(c+2*d) && y.Op != OpSB // result: (LEAQ2 [c+2*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+2*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = c + 2*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ4_0(v *Value) bool { // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ4 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(c+4*d) && y.Op != OpSB // result: (LEAQ4 [c+4*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+4*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = c + 4*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ4 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ8_0(v *Value) bool { // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ8 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(c+8*d) && y.Op != OpSB // result: (LEAQ8 [c+8*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+8*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = c + 8*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSX_0(v *Value) bool { b := v.Block // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVBload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0x7f v.AddArg(x) return true } // match: (MOVBQSX (MOVBQSX x)) // result: (MOVBQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSXload_0(v *Value) bool { // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBQSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQZX_0(v *Value) bool { b := v.Block // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVBload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x) // cond: zeroUpper56Bits(x,3) // result: x for { x := v.Args[0] if !(zeroUpper56Bits(x, 3)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVBQZX x:(MOVBloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVBloadidx1 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVBloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVBQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0xff v.AddArg(x) return true } // match: (MOVBQZX (MOVBQZX x)) // result: (MOVBQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBatomicload_0(v *Value) bool { // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBatomicload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBload_0(v *Value) bool { // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVBloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (ADDQ idx ptr) mem) // cond: ptr.Op != OpSB // result: (MOVBloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(read8(sym, off))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int64(read8(sym, off)) return true } return false } func rewriteValueAMD64_OpAMD64MOVBloadidx1_0(v *Value) bool { // match: (MOVBloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) // cond: is32Bit(c+d) // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) // cond: is32Bit(c+d) // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVBload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVBloadidx1 [i] {s} (MOVQconst [c]) p mem) // cond: is32Bit(i+c) // result: (MOVBload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt p := v.Args[1] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_0(v *Value) bool { // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) // cond: y.Uses == 1 // result: (SETLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETL { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) // cond: y.Uses == 1 // result: (SETLEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETLE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) // cond: y.Uses == 1 // result: (SETGstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETG { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETGstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) // cond: y.Uses == 1 // result: (SETGEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETGE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) // cond: y.Uses == 1 // result: (SETEQstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETEQ { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) // cond: y.Uses == 1 // result: (SETNEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETNE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) // cond: y.Uses == 1 // result: (SETBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETB { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) // cond: y.Uses == 1 // result: (SETBEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETBE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) // cond: y.Uses == 1 // result: (SETAstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETA { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETAstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) // cond: y.Uses == 1 // result: (SETAEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETAE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_10(v *Value) bool { b := v.Block // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBQSX { break } x := v_1.Args[0] v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBQZX { break } x := v_1.Args[0] v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validOff(off) // result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVBstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} (ADDQ idx ptr) val mem) // cond: ptr.Op != OpSB // result: (MOVBstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstore [i-1] {s} p (ROLWconst [8] w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x0 := v.Args[2] if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-1 || x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || x0_1.AuxInt != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = 8 v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_20(v *Value) bool { b := v.Block // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x2 := v.Args[2] if x2.Op != OpAMD64MOVBstore || x2.AuxInt != i-1 || x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || x2_1.AuxInt != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || x1.AuxInt != i-2 || x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || x1_1.AuxInt != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-3 || x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || x0_1.AuxInt != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 3 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x6 := v.Args[2] if x6.Op != OpAMD64MOVBstore || x6.AuxInt != i-1 || x6.Aux != s { break } _ = x6.Args[2] if p != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || x6_1.AuxInt != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || x5.AuxInt != i-2 || x5.Aux != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || x5_1.AuxInt != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || x4.AuxInt != i-3 || x4.Aux != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || x4_1.AuxInt != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || x3.AuxInt != i-4 || x3.Aux != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || x3_1.AuxInt != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || x2.AuxInt != i-5 || x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || x2_1.AuxInt != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || x1.AuxInt != i-6 || x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || x1_1.AuxInt != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-7 || x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || x0_1.AuxInt != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 7 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRWconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVBload { break } j := x1.AuxInt s2 := x1.Aux mem := x1.Args[1] p2 := x1.Args[0] mem2 := v.Args[2] if mem2.Op != OpAMD64MOVBstore || mem2.AuxInt != i-1 || mem2.Aux != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVBload || x2.AuxInt != j-1 || x2.Aux != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = j - 1 v0.Aux = s2 v0.AddArg(p2) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconst_0(v *Value) bool { // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVBstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVBstoreconst { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVBstoreconst [a] {s} p x:(MOVBstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem) for { a := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVBstoreconst { break } c := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconstidx1_0(v *Value) bool { // match: (MOVBstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconstidx1 [c] {s} p i x:(MOVBstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p i mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(i) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreidx1_0(v *Value) bool { b := v.Block // match: (MOVBstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x0:(MOVBstoreidx1 [i-1] {s} p idx (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstoreidx1 [i-1] {s} p idx (ROLWconst [8] w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x0 := v.Args[3] if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-1 || x0.Aux != s { break } mem := x0.Args[3] if p != x0.Args[0] || idx != x0.Args[1] { break } x0_2 := x0.Args[2] if x0_2.Op != OpAMD64SHRWconst || x0_2.AuxInt != 8 || w != x0_2.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = 8 v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x2:(MOVBstoreidx1 [i-1] {s} p idx (SHRLconst [8] w) x1:(MOVBstoreidx1 [i-2] {s} p idx (SHRLconst [16] w) x0:(MOVBstoreidx1 [i-3] {s} p idx (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) // result: (MOVLstoreidx1 [i-3] {s} p idx (BSWAPL w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x2 := v.Args[3] if x2.Op != OpAMD64MOVBstoreidx1 || x2.AuxInt != i-1 || x2.Aux != s { break } _ = x2.Args[3] if p != x2.Args[0] || idx != x2.Args[1] { break } x2_2 := x2.Args[2] if x2_2.Op != OpAMD64SHRLconst || x2_2.AuxInt != 8 || w != x2_2.Args[0] { break } x1 := x2.Args[3] if x1.Op != OpAMD64MOVBstoreidx1 || x1.AuxInt != i-2 || x1.Aux != s { break } _ = x1.Args[3] if p != x1.Args[0] || idx != x1.Args[1] { break } x1_2 := x1.Args[2] if x1_2.Op != OpAMD64SHRLconst || x1_2.AuxInt != 16 || w != x1_2.Args[0] { break } x0 := x1.Args[3] if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-3 || x0.Aux != s { break } mem := x0.Args[3] if p != x0.Args[0] || idx != x0.Args[1] { break } x0_2 := x0.Args[2] if x0_2.Op != OpAMD64SHRLconst || x0_2.AuxInt != 24 || w != x0_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 3 v.Aux = s v.AddArg(p) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x6:(MOVBstoreidx1 [i-1] {s} p idx (SHRQconst [8] w) x5:(MOVBstoreidx1 [i-2] {s} p idx (SHRQconst [16] w) x4:(MOVBstoreidx1 [i-3] {s} p idx (SHRQconst [24] w) x3:(MOVBstoreidx1 [i-4] {s} p idx (SHRQconst [32] w) x2:(MOVBstoreidx1 [i-5] {s} p idx (SHRQconst [40] w) x1:(MOVBstoreidx1 [i-6] {s} p idx (SHRQconst [48] w) x0:(MOVBstoreidx1 [i-7] {s} p idx (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) // result: (MOVQstoreidx1 [i-7] {s} p idx (BSWAPQ w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x6 := v.Args[3] if x6.Op != OpAMD64MOVBstoreidx1 || x6.AuxInt != i-1 || x6.Aux != s { break } _ = x6.Args[3] if p != x6.Args[0] || idx != x6.Args[1] { break } x6_2 := x6.Args[2] if x6_2.Op != OpAMD64SHRQconst || x6_2.AuxInt != 8 || w != x6_2.Args[0] { break } x5 := x6.Args[3] if x5.Op != OpAMD64MOVBstoreidx1 || x5.AuxInt != i-2 || x5.Aux != s { break } _ = x5.Args[3] if p != x5.Args[0] || idx != x5.Args[1] { break } x5_2 := x5.Args[2] if x5_2.Op != OpAMD64SHRQconst || x5_2.AuxInt != 16 || w != x5_2.Args[0] { break } x4 := x5.Args[3] if x4.Op != OpAMD64MOVBstoreidx1 || x4.AuxInt != i-3 || x4.Aux != s { break } _ = x4.Args[3] if p != x4.Args[0] || idx != x4.Args[1] { break } x4_2 := x4.Args[2] if x4_2.Op != OpAMD64SHRQconst || x4_2.AuxInt != 24 || w != x4_2.Args[0] { break } x3 := x4.Args[3] if x3.Op != OpAMD64MOVBstoreidx1 || x3.AuxInt != i-4 || x3.Aux != s { break } _ = x3.Args[3] if p != x3.Args[0] || idx != x3.Args[1] { break } x3_2 := x3.Args[2] if x3_2.Op != OpAMD64SHRQconst || x3_2.AuxInt != 32 || w != x3_2.Args[0] { break } x2 := x3.Args[3] if x2.Op != OpAMD64MOVBstoreidx1 || x2.AuxInt != i-5 || x2.Aux != s { break } _ = x2.Args[3] if p != x2.Args[0] || idx != x2.Args[1] { break } x2_2 := x2.Args[2] if x2_2.Op != OpAMD64SHRQconst || x2_2.AuxInt != 40 || w != x2_2.Args[0] { break } x1 := x2.Args[3] if x1.Op != OpAMD64MOVBstoreidx1 || x1.AuxInt != i-6 || x1.Aux != s { break } _ = x1.Args[3] if p != x1.Args[0] || idx != x1.Args[1] { break } x1_2 := x1.Args[2] if x1_2.Op != OpAMD64SHRQconst || x1_2.AuxInt != 48 || w != x1_2.Args[0] { break } x0 := x1.Args[3] if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-7 || x0.Aux != s { break } mem := x0.Args[3] if p != x0.Args[0] || idx != x0.Args[1] { break } x0_2 := x0.Args[2] if x0_2.Op != OpAMD64SHRQconst || x0_2.AuxInt != 56 || w != x0_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 7 v.Aux = s v.AddArg(p) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRWconst || v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst || v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRQconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreidx1_10(v *Value) bool { // match: (MOVBstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVBstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSX_0(v *Value) bool { b := v.Block // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQSX (ANDLconst [c] x)) // cond: c & 0x80000000 == 0 // result: (ANDLconst [c & 0x7fffffff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x80000000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0x7fffffff v.AddArg(x) return true } // match: (MOVLQSX (MOVLQSX x)) // result: (MOVLQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVWQSX x)) // result: (MOVWQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVBQSX x)) // result: (MOVBQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSXload_0(v *Value) bool { // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLQSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQZX_0(v *Value) bool { b := v.Block // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQZX x) // cond: zeroUpper32Bits(x,3) // result: x for { x := v.Args[0] if !(zeroUpper32Bits(x, 3)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVLQZX x:(MOVLloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLloadidx1 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVLQZX x:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLloadidx4 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLloadidx4 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx4, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVLQZX (ANDLconst [c] x)) // result: (ANDLconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVLQZX (MOVLQZX x)) // result: (MOVLQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVWQZX x)) // result: (MOVWQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVBQZX x)) // result: (MOVBQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLatomicload_0(v *Value) bool { // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLatomicload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLf2i_0(v *Value) bool { b := v.Block // match: (MOVLf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVLi2f_0(v *Value) bool { b := v.Block // match: (MOVLi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVLload_0(v *Value) bool { // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVLloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off] {sym} (ADDQ idx ptr) mem) // cond: ptr.Op != OpSB // result: (MOVLloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLload_10(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVSSstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVLf2i) v.AddArg(val) return true } // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64(read32(sym, off, config.BigEndian)) return true } return false } func rewriteValueAMD64_OpAMD64MOVLloadidx1_0(v *Value) bool { // match: (MOVLloadidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) // result: (MOVLloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (SHLQconst [2] idx) ptr mem) // result: (MOVLloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 { break } idx := v_0.Args[0] ptr := v.Args[1] v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVLloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (SHLQconst [3] idx) ptr mem) // result: (MOVLloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { break } idx := v_0.Args[0] ptr := v.Args[1] v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) // cond: is32Bit(c+d) // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) // cond: is32Bit(c+d) // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVLload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVLloadidx1 [i] {s} (MOVQconst [c]) p mem) // cond: is32Bit(i+c) // result: (MOVLload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt p := v.Args[1] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLloadidx4_0(v *Value) bool { // match: (MOVLloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVLloadidx4 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+4*d) // result: (MOVLloadidx4 [c+4*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx4 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+4*c) // result: (MOVLload [i+4*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLloadidx8_0(v *Value) bool { // match: (MOVLloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVLloadidx8 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+8*d) // result: (MOVLloadidx8 [c+8*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx8 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+8*c) // result: (MOVLload [i+8*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore_0(v *Value) bool { // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLQSX { break } x := v_1.Args[0] v.reset(OpAMD64MOVLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLQZX { break } x := v_1.Args[0] v.reset(OpAMD64MOVLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(int64(int32(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validOff(off) // result: (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(int64(int32(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVLstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstore [off] {sym} (ADDQ idx ptr) val mem) // cond: ptr.Op != OpSB // result: (MOVLstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst || v_1.AuxInt != 32 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVLstore || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVLstore || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVLload { break } j := x1.AuxInt s2 := x1.Aux mem := x1.Args[1] p2 := x1.Args[0] mem2 := v.Args[2] if mem2.Op != OpAMD64MOVLstore || mem2.AuxInt != i-4 || mem2.Aux != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVLload || x2.AuxInt != j-4 || x2.Aux != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x2.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = j - 4 v0.Aux = s2 v0.AddArg(p2) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore_20(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SUBL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(BTCL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTCLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTCL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTCLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore_30(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(BTRL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTRLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTRL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTRLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(BTSL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTSLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTSL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTSLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ADDLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ADDLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ANDLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ANDLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ANDLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ORLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ORLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ORLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (XORLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64XORLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64XORLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(BTCLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTCLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTCLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTCLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(BTRLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTRLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTRLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTRLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(BTSLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTSLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTSLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTSLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) // result: (MOVSSstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLf2i { break } val := v_1.Args[0] v.reset(OpAMD64MOVSSstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconst_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym1} (LEAQ4 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVLstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [c] {s} p x:(MOVLstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstore [ValAndOff(a).Off()] {s} p (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVLstoreconst { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVLstoreconst [a] {s} p x:(MOVLstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstore [ValAndOff(a).Off()] {s} p (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { a := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVLstoreconst { break } c := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconstidx1_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconstidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) // result: (MOVLstoreconstidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [c] {s} p i x:(MOVLstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstoreidx1 [ValAndOff(a).Off()] {s} p i (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVLstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconstidx4_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconstidx4 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx4 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(4*c) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(4*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(4 * c)) { break } v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(4 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx4 [c] {s} p i x:(MOVLstoreconstidx4 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstoreidx1 [ValAndOff(a).Off()] {s} p (SHLQconst [2] i) (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVLstoreconstidx4 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, i.Type) v0.AuxInt = 2 v0.AddArg(i) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v1) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreidx1_0(v *Value) bool { // match: (MOVLstoreidx1 [c] {sym} ptr (SHLQconst [2] idx) val mem) // result: (MOVLstoreidx4 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) // result: (MOVLstoreidx8 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [i] {s} p idx (SHRQconst [32] w) x:(MOVLstoreidx1 [i-4] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 32 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx1 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVLstoreidx1 [i-4] {s} p idx w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx1 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVLstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreidx4_0(v *Value) bool { b := v.Block // match: (MOVLstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx4 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+4*d) // result: (MOVLstoreidx4 [c+4*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [i] {s} p idx (SHRQconst [32] w) x:(MOVLstoreidx4 [i-4] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p (SHLQconst [2] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 32 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx4 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 2 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [i] {s} p idx (SHRQconst [j] w) x:(MOVLstoreidx4 [i-4] {s} p idx w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p (SHLQconst [2] idx) w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx4 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 2 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+4*c) // result: (MOVLstore [i+4*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreidx8_0(v *Value) bool { // match: (MOVLstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx8 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+8*d) // result: (MOVLstoreidx8 [c+8*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx8 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+8*c) // result: (MOVLstore [i+8*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOload_0(v *Value) bool { // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVOload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstore_0(v *Value) bool { // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVOstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQatomicload_0(v *Value) bool { // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVQatomicload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQf2i_0(v *Value) bool { b := v.Block // match: (MOVQf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVQi2f_0(v *Value) bool { b := v.Block // match: (MOVQi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVQload_0(v *Value) bool { // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVQloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQload [off] {sym} (ADDQ idx ptr) mem) // cond: ptr.Op != OpSB // result: (MOVQloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) // result: (MOVQf2i val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVSDstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVQf2i) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVQload_10(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64(read64(sym, off, config.BigEndian)) return true } return false } func rewriteValueAMD64_OpAMD64MOVQloadidx1_0(v *Value) bool { // match: (MOVQloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVQloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx1 [c] {sym} (SHLQconst [3] idx) ptr mem) // result: (MOVQloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { break } idx := v_0.Args[0] ptr := v.Args[1] v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) // cond: is32Bit(c+d) // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) // cond: is32Bit(c+d) // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVQload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVQloadidx1 [i] {s} (MOVQconst [c]) p mem) // cond: is32Bit(i+c) // result: (MOVQload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt p := v.Args[1] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQloadidx8_0(v *Value) bool { // match: (MOVQloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVQloadidx8 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+8*d) // result: (MOVQloadidx8 [c+8*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx8 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+8*c) // result: (MOVQload [i+8*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_0(v *Value) bool { // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validValAndOff(c,off) // result: (MOVQstoreconst [makeValAndOff(c,off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validValAndOff(c, off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVQstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} (ADDQ idx ptr) val mem) // cond: ptr.Op != OpSB // result: (MOVQstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_10(v *Value) bool { // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ x l:(MOVQload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDQ { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SUBQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ x l:(MOVQload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDQ { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQ x l:(MOVQload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORQ { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_20(v *Value) bool { // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQ x l:(MOVQload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORQ { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(BTCQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTCQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTCQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTCQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(BTRQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTRQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTRQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTRQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(BTSQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTSQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTSQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTSQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ADDQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ADDQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ANDQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ANDQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ANDQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ORQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ORQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ORQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (XORQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64XORQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64XORQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(BTCQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTCQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTCQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTCQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_30(v *Value) bool { // match: (MOVQstore [off] {sym} ptr a:(BTRQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTRQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTRQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTRQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(BTSQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTSQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTSQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTSQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) // result: (MOVSDstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQf2i { break } val := v_1.Args[0] v.reset(OpAMD64MOVSDstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconst_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVQstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconst [x] {sym1} (LEAQ8 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVQstoreconstidx8 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVQstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconst [c] {s} p x:(MOVQstoreconst [c2] {s} p mem)) // cond: config.useSSE && x.Uses == 1 && ValAndOff(c2).Off() + 8 == ValAndOff(c).Off() && ValAndOff(c).Val() == 0 && ValAndOff(c2).Val() == 0 && clobber(x) // result: (MOVOstore [ValAndOff(c2).Off()] {s} p (MOVOconst [0]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVQstoreconst { break } c2 := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(config.useSSE && x.Uses == 1 && ValAndOff(c2).Off()+8 == ValAndOff(c).Off() && ValAndOff(c).Val() == 0 && ValAndOff(c2).Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = ValAndOff(c2).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(x.Pos, OpAMD64MOVOconst, types.TypeInt128) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconstidx1_0(v *Value) bool { // match: (MOVQstoreconstidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVQstoreconstidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVQstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVQstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconstidx8_0(v *Value) bool { // match: (MOVQstoreconstidx8 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVQstoreconstidx8 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconstidx8 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(8*c) // result: (MOVQstoreconstidx8 [ValAndOff(x).add(8*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(8 * c)) { break } v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = ValAndOff(x).add(8 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreidx1_0(v *Value) bool { // match: (MOVQstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) // result: (MOVQstoreidx8 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVQstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVQstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVQstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreidx8_0(v *Value) bool { // match: (MOVQstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVQstoreidx8 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+8*d) // result: (MOVQstoreidx8 [c+8*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx8 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+8*c) // result: (MOVQstore [i+8*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDload_0(v *Value) bool { // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVSDloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off] {sym} (ADDQ idx ptr) mem) // cond: ptr.Op != OpSB // result: (MOVSDloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVQi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDloadidx1_0(v *Value) bool { // match: (MOVSDloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVSDloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSDloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVSDloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVSDload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDloadidx8_0(v *Value) bool { // match: (MOVSDloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSDloadidx8 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+8*d) // result: (MOVSDloadidx8 [c+8*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx8 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+8*c) // result: (MOVSDload [i+8*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstore_0(v *Value) bool { // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVSDstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off] {sym} (ADDQ idx ptr) val mem) // cond: ptr.Op != OpSB // result: (MOVSDstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQi2f { break } val := v_1.Args[0] v.reset(OpAMD64MOVQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstoreidx1_0(v *Value) bool { // match: (MOVSDstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) // result: (MOVSDstoreidx8 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSDstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVSDstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVSDstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstoreidx8_0(v *Value) bool { // match: (MOVSDstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSDstoreidx8 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+8*d) // result: (MOVSDstoreidx8 [c+8*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx8 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+8*c) // result: (MOVSDstore [i+8*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSload_0(v *Value) bool { // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVSSloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off] {sym} (ADDQ idx ptr) mem) // cond: ptr.Op != OpSB // result: (MOVSSloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVLi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSloadidx1_0(v *Value) bool { // match: (MOVSSloadidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) // result: (MOVSSloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSSloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVSSloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVSSload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSloadidx4_0(v *Value) bool { // match: (MOVSSloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSSloadidx4 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+4*d) // result: (MOVSSloadidx4 [c+4*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx4 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+4*c) // result: (MOVSSload [i+4*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstore_0(v *Value) bool { // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVSSstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off] {sym} (ADDQ idx ptr) val mem) // cond: ptr.Op != OpSB // result: (MOVSSstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLi2f { break } val := v_1.Args[0] v.reset(OpAMD64MOVLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstoreidx1_0(v *Value) bool { // match: (MOVSSstoreidx1 [c] {sym} ptr (SHLQconst [2] idx) val mem) // result: (MOVSSstoreidx4 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSSstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVSSstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVSSstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstoreidx4_0(v *Value) bool { // match: (MOVSSstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSSstoreidx4 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+4*d) // result: (MOVSSstoreidx4 [c+4*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx4 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+4*c) // result: (MOVSSstore [i+4*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSX_0(v *Value) bool { b := v.Block // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0x7fff v.AddArg(x) return true } // match: (MOVWQSX (MOVWQSX x)) // result: (MOVWQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSX (MOVBQSX x)) // result: (MOVBQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSXload_0(v *Value) bool { // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWQSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQZX_0(v *Value) bool { b := v.Block // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQZX x) // cond: zeroUpper48Bits(x,3) // result: x for { x := v.Args[0] if !(zeroUpper48Bits(x, 3)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWQZX x:(MOVWloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWloadidx1 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVWQZX x:(MOVWloadidx2 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWloadidx2 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWloadidx2 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx2, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVWQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xffff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0xffff v.AddArg(x) return true } // match: (MOVWQZX (MOVWQZX x)) // result: (MOVWQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWQZX (MOVBQZX x)) // result: (MOVBQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWload_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWloadidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWloadidx2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVWloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (ADDQ idx ptr) mem) // cond: ptr.Op != OpSB // result: (MOVWloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(read16(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int64(read16(sym, off, config.BigEndian)) return true } return false } func rewriteValueAMD64_OpAMD64MOVWloadidx1_0(v *Value) bool { // match: (MOVWloadidx1 [c] {sym} ptr (SHLQconst [1] idx) mem) // result: (MOVWloadidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} (SHLQconst [1] idx) ptr mem) // result: (MOVWloadidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } idx := v_0.Args[0] ptr := v.Args[1] v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) // cond: is32Bit(c+d) // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) // cond: is32Bit(c+d) // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVWload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVWloadidx1 [i] {s} (MOVQconst [c]) p mem) // cond: is32Bit(i+c) // result: (MOVWload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt p := v.Args[1] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWloadidx2_0(v *Value) bool { // match: (MOVWloadidx2 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVWloadidx2 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx2 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+2*d) // result: (MOVWloadidx2 [c+2*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 2*d)) { break } v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c + 2*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx2 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+2*c) // result: (MOVWload [i+2*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 2*c)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = i + 2*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore_0(v *Value) bool { // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWQSX { break } x := v_1.Args[0] v.reset(OpAMD64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWQZX { break } x := v_1.Args[0] v.reset(OpAMD64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validOff(off) // result: (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstoreidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVWstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} (ADDQ idx ptr) val mem) // cond: ptr.Op != OpSB // result: (MOVWstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst || v_1.AuxInt != 16 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst || v_1.AuxInt != 16 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVWload { break } j := x1.AuxInt s2 := x1.Aux mem := x1.Args[1] p2 := x1.Args[0] mem2 := v.Args[2] if mem2.Op != OpAMD64MOVWstore || mem2.AuxInt != i-2 || mem2.Aux != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVWload || x2.AuxInt != j-2 || x2.Aux != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x2.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = j - 2 v0.Aux = s2 v0.AddArg(p2) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconst_0(v *Value) bool { // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym1} (LEAQ2 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVWstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVWstoreconst { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVWstoreconst [a] {s} p x:(MOVWstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem) for { a := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVWstoreconst { break } c := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconstidx1_0(v *Value) bool { // match: (MOVWstoreconstidx1 [c] {sym} ptr (SHLQconst [1] idx) mem) // result: (MOVWstoreconstidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [c] {s} p i x:(MOVWstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p i mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVWstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(i) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconstidx2_0(v *Value) bool { b := v.Block // match: (MOVWstoreconstidx2 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx2 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(2*c) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(2*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(2 * c)) { break } v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(2 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx2 [c] {s} p i x:(MOVWstoreconstidx2 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p (SHLQconst [1] i) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVWstoreconstidx2 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, i.Type) v0.AuxInt = 1 v0.AddArg(i) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreidx1_0(v *Value) bool { // match: (MOVWstoreidx1 [c] {sym} ptr (SHLQconst [1] idx) val mem) // result: (MOVWstoreidx2 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVWstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVWstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRQconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVWstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreidx2_0(v *Value) bool { b := v.Block // match: (MOVWstoreidx2 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVWstoreidx2 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+2*d) // result: (MOVWstoreidx2 [c+2*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 2*d)) { break } v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = c + 2*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLQconst [1] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx2 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRQconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLQconst [1] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx2 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRQconst [j] w) x:(MOVWstoreidx2 [i-2] {s} p idx w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLQconst [1] idx) w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx2 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+2*c) // result: (MOVWstore [i+2*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 2*c)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i + 2*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MULL_0(v *Value) bool { // match: (MULL x (MOVLconst [c])) // result: (MULLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64MULLconst) v.AuxInt = c v.AddArg(x) return true } // match: (MULL (MOVLconst [c]) x) // result: (MULLconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64MULLconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_0(v *Value) bool { b := v.Block // match: (MULLconst [c] (MULLconst [d] x)) // result: (MULLconst [int64(int32(c * d))] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MULLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64MULLconst) v.AuxInt = int64(int32(c * d)) v.AddArg(x) return true } // match: (MULLconst [-9] x) // result: (NEGL (LEAL8 x x)) for { if v.AuxInt != -9 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // result: (NEGL (LEAL4 x x)) for { if v.AuxInt != -5 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // result: (NEGL (LEAL2 x x)) for { if v.AuxInt != -3 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // result: (NEGL x) for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } // match: (MULLconst [ 0] _) // result: (MOVLconst [0]) for { if v.AuxInt != 0 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (MULLconst [ 1] x) // result: x for { if v.AuxInt != 1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MULLconst [ 3] x) // result: (LEAL2 x x) for { if v.AuxInt != 3 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [ 5] x) // result: (LEAL4 x x) for { if v.AuxInt != 5 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [ 7] x) // result: (LEAL2 x (LEAL2 x x)) for { if v.AuxInt != 7 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_10(v *Value) bool { b := v.Block // match: (MULLconst [ 9] x) // result: (LEAL8 x x) for { if v.AuxInt != 9 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [11] x) // result: (LEAL2 x (LEAL4 x x)) for { if v.AuxInt != 11 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [13] x) // result: (LEAL4 x (LEAL2 x x)) for { if v.AuxInt != 13 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [19] x) // result: (LEAL2 x (LEAL8 x x)) for { if v.AuxInt != 19 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [21] x) // result: (LEAL4 x (LEAL4 x x)) for { if v.AuxInt != 21 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [25] x) // result: (LEAL8 x (LEAL2 x x)) for { if v.AuxInt != 25 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [27] x) // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if v.AuxInt != 27 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULLconst [37] x) // result: (LEAL4 x (LEAL8 x x)) for { if v.AuxInt != 37 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [41] x) // result: (LEAL8 x (LEAL4 x x)) for { if v.AuxInt != 41 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [45] x) // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if v.AuxInt != 45 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_20(v *Value) bool { b := v.Block // match: (MULLconst [73] x) // result: (LEAL8 x (LEAL8 x x)) for { if v.AuxInt != 73 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [81] x) // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if v.AuxInt != 81 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c+1) && c >= 15 // result: (SUBL (SHLLconst [log2(c+1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c+1) && c >= 15) { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c + 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [log2(c-1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-1) && c >= 17) { break } v.reset(OpAMD64LEAL1) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [log2(c-2)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-2) && c >= 34) { break } v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 2) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [log2(c-4)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-4) && c >= 68) { break } v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 4) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [log2(c-8)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-8) && c >= 136) { break } v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 8) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo(c/3) // result: (SHLLconst [log2(c/3)] (LEAL2 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%3 == 0 && isPowerOfTwo(c/3)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = log2(c / 3) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo(c/5) // result: (SHLLconst [log2(c/5)] (LEAL4 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%5 == 0 && isPowerOfTwo(c/5)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = log2(c / 5) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo(c/9) // result: (SHLLconst [log2(c/9)] (LEAL8 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%9 == 0 && isPowerOfTwo(c/9)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = log2(c / 9) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_30(v *Value) bool { // match: (MULLconst [c] (MOVLconst [d])) // result: (MOVLconst [int64(int32(c*d))]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = int64(int32(c * d)) return true } return false } func rewriteValueAMD64_OpAMD64MULQ_0(v *Value) bool { // match: (MULQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (MULQconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = c v.AddArg(x) return true } // match: (MULQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (MULQconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_0(v *Value) bool { b := v.Block // match: (MULQconst [c] (MULQconst [d] x)) // cond: is32Bit(c*d) // result: (MULQconst [c * d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MULQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c * d)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = c * d v.AddArg(x) return true } // match: (MULQconst [-9] x) // result: (NEGQ (LEAQ8 x x)) for { if v.AuxInt != -9 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [-5] x) // result: (NEGQ (LEAQ4 x x)) for { if v.AuxInt != -5 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [-3] x) // result: (NEGQ (LEAQ2 x x)) for { if v.AuxInt != -3 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [-1] x) // result: (NEGQ x) for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v.AddArg(x) return true } // match: (MULQconst [ 0] _) // result: (MOVQconst [0]) for { if v.AuxInt != 0 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (MULQconst [ 1] x) // result: x for { if v.AuxInt != 1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MULQconst [ 3] x) // result: (LEAQ2 x x) for { if v.AuxInt != 3 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(x) return true } // match: (MULQconst [ 5] x) // result: (LEAQ4 x x) for { if v.AuxInt != 5 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v.AddArg(x) return true } // match: (MULQconst [ 7] x) // result: (LEAQ2 x (LEAQ2 x x)) for { if v.AuxInt != 7 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_10(v *Value) bool { b := v.Block // match: (MULQconst [ 9] x) // result: (LEAQ8 x x) for { if v.AuxInt != 9 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v.AddArg(x) return true } // match: (MULQconst [11] x) // result: (LEAQ2 x (LEAQ4 x x)) for { if v.AuxInt != 11 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [13] x) // result: (LEAQ4 x (LEAQ2 x x)) for { if v.AuxInt != 13 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [19] x) // result: (LEAQ2 x (LEAQ8 x x)) for { if v.AuxInt != 19 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [21] x) // result: (LEAQ4 x (LEAQ4 x x)) for { if v.AuxInt != 21 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [25] x) // result: (LEAQ8 x (LEAQ2 x x)) for { if v.AuxInt != 25 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [27] x) // result: (LEAQ8 (LEAQ2 x x) (LEAQ2 x x)) for { if v.AuxInt != 27 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULQconst [37] x) // result: (LEAQ4 x (LEAQ8 x x)) for { if v.AuxInt != 37 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [41] x) // result: (LEAQ8 x (LEAQ4 x x)) for { if v.AuxInt != 41 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [45] x) // result: (LEAQ8 (LEAQ4 x x) (LEAQ4 x x)) for { if v.AuxInt != 45 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_20(v *Value) bool { b := v.Block // match: (MULQconst [73] x) // result: (LEAQ8 x (LEAQ8 x x)) for { if v.AuxInt != 73 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [81] x) // result: (LEAQ8 (LEAQ8 x x) (LEAQ8 x x)) for { if v.AuxInt != 81 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c+1) && c >= 15 // result: (SUBQ (SHLQconst [log2(c+1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c+1) && c >= 15) { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c + 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-1) && c >= 17 // result: (LEAQ1 (SHLQconst [log2(c-1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-1) && c >= 17) { break } v.reset(OpAMD64LEAQ1) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-2) && c >= 34 // result: (LEAQ2 (SHLQconst [log2(c-2)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-2) && c >= 34) { break } v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 2) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-4) && c >= 68 // result: (LEAQ4 (SHLQconst [log2(c-4)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-4) && c >= 68) { break } v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 4) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-8) && c >= 136 // result: (LEAQ8 (SHLQconst [log2(c-8)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-8) && c >= 136) { break } v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 8) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: c%3 == 0 && isPowerOfTwo(c/3) // result: (SHLQconst [log2(c/3)] (LEAQ2 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%3 == 0 && isPowerOfTwo(c/3)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = log2(c / 3) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%5 == 0 && isPowerOfTwo(c/5) // result: (SHLQconst [log2(c/5)] (LEAQ4 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%5 == 0 && isPowerOfTwo(c/5)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = log2(c / 5) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%9 == 0 && isPowerOfTwo(c/9) // result: (SHLQconst [log2(c/9)] (LEAQ8 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%9 == 0 && isPowerOfTwo(c/9)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = log2(c / 9) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_30(v *Value) bool { // match: (MULQconst [c] (MOVQconst [d])) // result: (MOVQconst [c*d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = c * d return true } // match: (MULQconst [c] (NEGQ x)) // cond: c != -(1<<31) // result: (MULQconst [-c] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = -c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULSD_0(v *Value) bool { // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MULSD l:(MOVSDload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MULSDload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (MULSD x (MOVQi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVQstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64MULSD) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULSS_0(v *Value) bool { // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MULSS l:(MOVSSload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MULSSload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (MULSS x (MOVLi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVLstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64MULSS) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64NEGL_0(v *Value) bool { // match: (NEGL (NEGL x)) // result: x for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGL { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (NEGL s:(SUBL x y)) // cond: s.Uses == 1 // result: (SUBL y x) for { s := v.Args[0] if s.Op != OpAMD64SUBL { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBL) v.AddArg(y) v.AddArg(x) return true } // match: (NEGL (MOVLconst [c])) // result: (MOVLconst [int64(int32(-c))]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = int64(int32(-c)) return true } return false } func rewriteValueAMD64_OpAMD64NEGQ_0(v *Value) bool { // match: (NEGQ (NEGQ x)) // result: x for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (NEGQ s:(SUBQ x y)) // cond: s.Uses == 1 // result: (SUBQ y x) for { s := v.Args[0] if s.Op != OpAMD64SUBQ { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBQ) v.AddArg(y) v.AddArg(x) return true } // match: (NEGQ (MOVQconst [c])) // result: (MOVQconst [-c]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = -c return true } // match: (NEGQ (ADDQconst [c] (NEGQ x))) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } x := v_0_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = -c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64NOTL_0(v *Value) bool { // match: (NOTL (MOVLconst [c])) // result: (MOVLconst [^c]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = ^c return true } return false } func rewriteValueAMD64_OpAMD64NOTQ_0(v *Value) bool { // match: (NOTQ (MOVQconst [c])) // result: (MOVQconst [^c]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = ^c return true } return false } func rewriteValueAMD64_OpAMD64ORL_0(v *Value) bool { // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { break } v.reset(OpAMD64BTSL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL x (SHLL (MOVLconst [1]) y)) // result: (BTSL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64MOVLconst || v_1_0.AuxInt != 1 { break } v.reset(OpAMD64BTSL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSLconst [log2uint32(c)] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (ORL x (MOVLconst [c])) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSLconst [log2uint32(c)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64ORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (MOVLconst [c]) x) // result: (ORLconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64ORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHRLconst x [d]) (SHLLconst x [c])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { break } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHRWconst x [d]) (SHLLconst x [c])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { break } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ORL_10(v *Value) bool { // match: (ORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRBconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { break } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHRBconst x [d]) (SHLLconst x [c])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRBconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { break } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRL { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x y) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHRL x (NEGQ y)))) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 32 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGQ { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -32 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRL { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32]))) (SHLL x y)) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRL { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGQ { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 32 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGQ { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -32 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHRL x (NEGQ y))) (SHLL x y)) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 32 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGQ { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -32 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 31 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRL { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRL { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x y) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHRL x (NEGL y)))) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 32 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGL { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -32 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRL { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32]))) (SHLL x y)) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRL { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGL { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 32 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGL { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -32 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHRL x (NEGL y))) (SHLL x y)) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 32 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGL { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -32 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 31 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRL { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_20(v *Value) bool { // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLL { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHRL x y) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHLL x (NEGQ y)))) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 32 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGQ { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -32 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLL { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32]))) (SHRL x y)) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGQ { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 32 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGQ { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -32 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHLL x (NEGQ y))) (SHRL x y)) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 32 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGQ { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -32 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 31 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLL { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLL { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHRL x y) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHLL x (NEGL y)))) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 32 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGL { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -32 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLL { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32]))) (SHRL x y)) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGL { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 32 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGL { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -32 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHLL x (NEGL y))) (SHRL x y)) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 32 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGL { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -32 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 31 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLL { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRW { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { break } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -16 { break } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 16 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -16 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])) (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 16 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGQ { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -16 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 15 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRW { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGQ { break } v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpAMD64ADDQconst || v_1_1_1_0.AuxInt != -16 { break } v_1_1_1_0_0 := v_1_1_1_0.Args[0] if v_1_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_1_0_0.AuxInt != 15 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_30(v *Value) bool { // match: (ORL (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16]))) (SHLL x (ANDQconst y [15]))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRW { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGQ { break } v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpAMD64ADDQconst || v_0_0_1_0.AuxInt != -16 { break } v_0_0_1_0_0 := v_0_0_1_0.Args[0] if v_0_0_1_0_0.Op != OpAMD64ANDQconst || v_0_0_1_0_0.AuxInt != 15 { break } y := v_0_0_1_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 16 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGQ { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -16 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 15 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])) (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) (SHLL x (ANDQconst y [15]))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 16 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGQ { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -16 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 15 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRW { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGQ { break } v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpAMD64ADDQconst || v_0_1_1_0.AuxInt != -16 { break } v_0_1_1_0_0 := v_0_1_1_0.Args[0] if v_0_1_1_0_0.Op != OpAMD64ANDQconst || v_0_1_1_0_0.AuxInt != 15 || y != v_0_1_1_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRW { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { break } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -16 { break } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 16 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -16 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])) (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 16 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGL { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -16 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 15 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRW { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGL { break } v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpAMD64ADDLconst || v_1_1_1_0.AuxInt != -16 { break } v_1_1_1_0_0 := v_1_1_1_0.Args[0] if v_1_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_1_0_0.AuxInt != 15 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16]))) (SHLL x (ANDLconst y [15]))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRW { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGL { break } v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpAMD64ADDLconst || v_0_0_1_0.AuxInt != -16 { break } v_0_0_1_0_0 := v_0_0_1_0.Args[0] if v_0_0_1_0_0.Op != OpAMD64ANDLconst || v_0_0_1_0_0.AuxInt != 15 { break } y := v_0_0_1_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 16 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGL { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -16 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 15 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])) (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) (SHLL x (ANDLconst y [15]))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 16 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGL { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -16 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 15 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRW { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGL { break } v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpAMD64ADDLconst || v_0_1_1_0.AuxInt != -16 { break } v_0_1_1_0_0 := v_0_1_1_0.Args[0] if v_0_1_1_0_0.Op != OpAMD64ANDLconst || v_0_1_1_0_0.AuxInt != 15 || y != v_0_1_1_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHRW x (ANDQconst y [15])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -16 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64RORW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SHRW x (ANDQconst y [15]))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64NEGQ { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64ADDQconst || v_0_1_0.AuxInt != -16 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0.AuxInt != 15 { break } y := v_0_1_0_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64RORW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHRW x (ANDLconst y [15])) (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -16 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64RORW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SHRW x (ANDLconst y [15]))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64NEGL { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64ADDLconst || v_0_1_0.AuxInt != -16 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0.AuxInt != 15 { break } y := v_0_1_0_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64RORW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_40(v *Value) bool { // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRB { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { break } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -8 { break } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 8 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -8 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 8 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGQ { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -8 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 7 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRB { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGQ { break } v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpAMD64ADDQconst || v_1_1_1_0.AuxInt != -8 { break } v_1_1_1_0_0 := v_1_1_1_0.Args[0] if v_1_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_1_0_0.AuxInt != 7 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8]))) (SHLL x (ANDQconst y [ 7]))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRB { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGQ { break } v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpAMD64ADDQconst || v_0_0_1_0.AuxInt != -8 { break } v_0_0_1_0_0 := v_0_0_1_0.Args[0] if v_0_0_1_0_0.Op != OpAMD64ANDQconst || v_0_0_1_0_0.AuxInt != 7 { break } y := v_0_0_1_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 8 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGQ { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -8 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 7 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) (SHLL x (ANDQconst y [ 7]))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 8 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGQ { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -8 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 7 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRB { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGQ { break } v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpAMD64ADDQconst || v_0_1_1_0.AuxInt != -8 { break } v_0_1_1_0_0 := v_0_1_1_0.Args[0] if v_0_1_1_0_0.Op != OpAMD64ANDQconst || v_0_1_1_0_0.AuxInt != 7 || y != v_0_1_1_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRB { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { break } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -8 { break } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 8 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -8 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 8 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGL { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -8 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 7 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRB { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGL { break } v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpAMD64ADDLconst || v_1_1_1_0.AuxInt != -8 { break } v_1_1_1_0_0 := v_1_1_1_0.Args[0] if v_1_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_1_0_0.AuxInt != 7 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8]))) (SHLL x (ANDLconst y [ 7]))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRB { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGL { break } v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpAMD64ADDLconst || v_0_0_1_0.AuxInt != -8 { break } v_0_0_1_0_0 := v_0_0_1_0.Args[0] if v_0_0_1_0_0.Op != OpAMD64ANDLconst || v_0_0_1_0_0.AuxInt != 7 { break } y := v_0_0_1_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 8 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGL { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -8 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 7 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) (SHLL x (ANDLconst y [ 7]))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 8 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGL { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -8 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 7 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRB { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGL { break } v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpAMD64ADDLconst || v_0_1_1_0.AuxInt != -8 { break } v_0_1_1_0_0 := v_0_1_1_0.Args[0] if v_0_1_1_0_0.Op != OpAMD64ANDLconst || v_0_1_1_0_0.AuxInt != 7 || y != v_0_1_1_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRB { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -8 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64RORB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SHRB x (ANDQconst y [ 7]))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64NEGQ { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64ADDQconst || v_0_1_0.AuxInt != -8 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0.AuxInt != 7 { break } y := v_0_1_0_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRB { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64RORB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_50(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRB { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -8 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64RORB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SHRB x (ANDLconst y [ 7]))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64NEGL { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64ADDLconst || v_0_1_0.AuxInt != -8 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0.AuxInt != 7 { break } y := v_0_1_0_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRB { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64RORB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ORL x0:(MOVBload [i0] {s} p mem) sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem)) x0:(MOVBload [i0] {s} p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem)) x0:(MOVWload [i0] {s} p mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y) s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_60(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem))) s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORL_70(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_80(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_90(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem)) x1:(MOVBload [i1] {s} p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y) s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_100(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem))) s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64ORL_110(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_120(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_130(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ORL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORLconst_0(v *Value) bool { // match: (ORLconst [c] x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSLconst [log2uint32(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (ORLconst [c] (ORLconst [d] x)) // result: (ORLconst [c | d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ORLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ORLconst) v.AuxInt = c | d v.AddArg(x) return true } // match: (ORLconst [c] (BTSLconst [d] x)) // result: (ORLconst [c | 1<= 128 // result: (BTSQconst [log2(c)] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (ORQ x (MOVQconst [c])) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSQconst [log2(c)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ORQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (ORQconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ORQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORQ (SHRQconst x [d]) (SHLQconst x [c])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRQ { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBQcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (SHLQ x y) (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHRQ x (NEGQ y)))) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBQcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 64 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGQ { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -64 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRQ { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_10(v *Value) bool { // match: (ORQ (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64]))) (SHLQ x y)) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRQ { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGQ { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBQcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 64 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGQ { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -64 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHRQ x (NEGQ y))) (SHLQ x y)) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBQcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 64 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGQ { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -64 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 63 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRQ { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRQ { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBQcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (SHLQ x y) (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHRQ x (NEGL y)))) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBQcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 64 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGL { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -64 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRQ { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64]))) (SHLQ x y)) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRQ { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGL { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBQcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 64 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGL { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -64 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHRQ x (NEGL y))) (SHLQ x y)) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBQcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 64 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGL { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -64 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 63 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRQ { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLQ { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBQcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (SHRQ x y) (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHLQ x (NEGQ y)))) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBQcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 64 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGQ { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -64 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLQ { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64]))) (SHRQ x y)) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLQ { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGQ { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBQcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 64 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGQ { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -64 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHLQ x (NEGQ y))) (SHRQ x y)) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBQcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 64 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGQ { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -64 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 63 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLQ { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLQ { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBQcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (SHRQ x y) (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHLQ x (NEGL y)))) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBQcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 64 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGL { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -64 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLQ { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64]))) (SHRQ x y)) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLQ { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGL { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBQcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 64 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGL { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -64 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHLQ x (NEGL y))) (SHRQ x y)) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBQcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 64 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGL { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -64 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 63 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLQ { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ORQ x0:(MOVBload [i0] {s} p mem) sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem)) x0:(MOVBload [i0] {s} p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem)) x0:(MOVWload [i0] {s} p mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVLload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem)) x0:(MOVLload [i0] {s} p mem)) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpAMD64MOVLload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y) s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem))) s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y) s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem))) s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_40(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_50(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVLloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVLloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVLloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVLloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem)) x0:(MOVLloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_60(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem)) x0:(MOVLloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem)) x0:(MOVLloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem)) x0:(MOVLloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_70(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_80(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_90(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem)) x1:(MOVBload [i1] {s} p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_100(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem))) r1:(BSWAPL x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] r1 := v.Args[1] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y) s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem))) s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_110(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_120(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_130(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_140(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_150(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_160(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ORQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ORQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ORQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORQconst_0(v *Value) bool { // match: (ORQconst [c] x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSQconst [log2(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (ORQconst [c] (ORQconst [d] x)) // result: (ORQconst [c | d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ORQconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ORQconst) v.AuxInt = c | d v.AddArg(x) return true } // match: (ORQconst [c] (BTSQconst [d] x)) // result: (ORQconst [c | 1<>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = int64(int8(d)) >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SARL_0(v *Value) bool { b := v.Block // match: (SARL x (MOVQconst [c])) // result: (SARLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SARLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SARL x (MOVLconst [c])) // result: (SARLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SARLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SARL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARLconst_0(v *Value) bool { // match: (SARLconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARLconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int32(d))>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = int64(int32(d)) >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SARQ_0(v *Value) bool { b := v.Block // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SARQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SARQ x (MOVLconst [c])) // result: (SARQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SARQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SARQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARQconst_0(v *Value) bool { // match: (SARQconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARQconst [c] (MOVQconst [d])) // result: (MOVQconst [d>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = d >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SARW_0(v *Value) bool { // match: (SARW x (MOVQconst [c])) // result: (SARWconst [min(c&31,15)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SARWconst) v.AuxInt = min(c&31, 15) v.AddArg(x) return true } // match: (SARW x (MOVLconst [c])) // result: (SARWconst [min(c&31,15)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SARWconst) v.AuxInt = min(c&31, 15) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SARWconst_0(v *Value) bool { // match: (SARWconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARWconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int16(d))>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = int64(int16(d)) >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SBBLcarrymask_0(v *Value) bool { // match: (SBBLcarrymask (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SBBLcarrymask (FlagLT_ULT)) // result: (MOVLconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = -1 return true } // match: (SBBLcarrymask (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SBBLcarrymask (FlagGT_ULT)) // result: (MOVLconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = -1 return true } // match: (SBBLcarrymask (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SBBQ_0(v *Value) bool { // match: (SBBQ x (MOVQconst [c]) borrow) // cond: is32Bit(c) // result: (SBBQconst x [c] borrow) for { borrow := v.Args[2] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64SBBQconst) v.AuxInt = c v.AddArg(x) v.AddArg(borrow) return true } // match: (SBBQ x y (FlagEQ)) // result: (SUBQborrow x y) for { _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQborrow) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64SBBQcarrymask_0(v *Value) bool { // match: (SBBQcarrymask (FlagEQ)) // result: (MOVQconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (SBBQcarrymask (FlagLT_ULT)) // result: (MOVQconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = -1 return true } // match: (SBBQcarrymask (FlagLT_UGT)) // result: (MOVQconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (SBBQcarrymask (FlagGT_ULT)) // result: (MOVQconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = -1 return true } // match: (SBBQcarrymask (FlagGT_UGT)) // result: (MOVQconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SBBQconst_0(v *Value) bool { // match: (SBBQconst x [c] (FlagEQ)) // result: (SUBQconstborrow x [c]) for { c := v.AuxInt _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SETA_0(v *Value) bool { // match: (SETA (InvertFlags x)) // result: (SETB x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETA (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETAE_0(v *Value) bool { // match: (SETAE (InvertFlags x)) // result: (SETBE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETAE (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETAE (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETAE (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETAE (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETAEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETBEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETAEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETAstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETAstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETB_0(v *Value) bool { // match: (SETB (InvertFlags x)) // result: (SETA x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETB (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETB (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETB (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETB (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETBE_0(v *Value) bool { // match: (SETBE (InvertFlags x)) // result: (SETAE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETBE (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETBEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETBEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETBstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETAstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETBstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ_0(v *Value) bool { b := v.Block // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETEQ (TESTL y (SHLL (MOVLconst [1]) x))) // result: (SETAE (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLL { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLQ { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETEQ (TESTQ y (SHLQ (MOVQconst [1]) x))) // result: (SETAE (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLQ { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (SETAE (BTLconst [log2uint32(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst { break } c := v_0_0.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ x (MOVQconst [c]))) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64MOVQconst { break } c := v_0_1.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPLconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETNE (CMPQconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPQconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ_10(v *Value) bool { b := v.Block // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z2 z1:(SHRQconst [63] x))) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ_20(v *Value) bool { b := v.Block // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTL z2 z1:(SHRLconst [31] x))) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETEQ (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore_0(v *Value) bool { b := v.Block // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLL { break } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTL y (SHLL (MOVLconst [1]) x)) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLL { break } x := v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64MOVLconst || v_1_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLQ { break } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ y (SHLQ (MOVQconst [1]) x)) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLQ { break } x := v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64MOVQconst || v_1_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTLconst [log2uint32(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTLconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64MOVQconst { break } c := v_1_0.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ x (MOVQconst [c])) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64MOVQconst { break } c := v_1_1.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPLconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPQconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore_10(v *Value) bool { b := v.Block // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x))) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTL z2 z1:(SHLLconst [31] (SHRLconst [31] x))) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x))) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x))) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] x)) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] x)) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETEQstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETG_0(v *Value) bool { // match: (SETG (InvertFlags x)) // result: (SETL x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETG (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETGE_0(v *Value) bool { // match: (SETGE (InvertFlags x)) // result: (SETLE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETGE (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETGE (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETGE (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETGE (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETGEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETLEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETGEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETGstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETGstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETL_0(v *Value) bool { // match: (SETL (InvertFlags x)) // result: (SETG x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETL (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETL (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETL (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETL (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETLE_0(v *Value) bool { // match: (SETLE (InvertFlags x)) // result: (SETGE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETLE (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETLEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETGEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETLEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETLstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETGstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETLstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNE_0(v *Value) bool { b := v.Block // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETNE (TESTL y (SHLL (MOVLconst [1]) x))) // result: (SETB (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLL { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLQ { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETNE (TESTQ y (SHLQ (MOVQconst [1]) x))) // result: (SETB (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLQ { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (SETB (BTLconst [log2uint32(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst { break } c := v_0_0.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ x (MOVQconst [c]))) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64MOVQconst { break } c := v_0_1.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPLconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETEQ (CMPQconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPQconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SETNE_10(v *Value) bool { b := v.Block // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ z2 z1:(SHRQconst [63] x))) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SETNE_20(v *Value) bool { b := v.Block // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTL z2 z1:(SHRLconst [31] x))) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (InvertFlags x)) // result: (SETNE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETNE (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore_0(v *Value) bool { b := v.Block // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLL { break } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTL y (SHLL (MOVLconst [1]) x)) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLL { break } x := v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64MOVLconst || v_1_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLQ { break } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ y (SHLQ (MOVQconst [1]) x)) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLQ { break } x := v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64MOVQconst || v_1_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTLconst [log2uint32(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTLconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64MOVQconst { break } c := v_1_0.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ x (MOVQconst [c])) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64MOVQconst { break } c := v_1_1.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPLconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPQconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore_10(v *Value) bool { b := v.Block // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x))) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTL z2 z1:(SHLLconst [31] (SHRLconst [31] x))) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x))) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x))) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] x)) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] x)) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETNEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLL_0(v *Value) bool { b := v.Block // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHLL x (MOVLconst [c])) // result: (SHLLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHLL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLLconst_0(v *Value) bool { // match: (SHLLconst [1] (SHRLconst [1] x)) // result: (BTRLconst [0] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = 0 v.AddArg(x) return true } // match: (SHLLconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHLQ_0(v *Value) bool { b := v.Block // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHLQ x (MOVLconst [c])) // result: (SHLQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHLQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLQconst_0(v *Value) bool { // match: (SHLQconst [1] (SHRQconst [1] x)) // result: (BTRQconst [0] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = 0 v.AddArg(x) return true } // match: (SHLQconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRB_0(v *Value) bool { // match: (SHRB x (MOVQconst [c])) // cond: c&31 < 8 // result: (SHRBconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRB _ (MOVQconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SHRBconst_0(v *Value) bool { // match: (SHRBconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRL_0(v *Value) bool { b := v.Block // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRL x (MOVLconst [c])) // result: (SHRLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRLconst_0(v *Value) bool { // match: (SHRLconst [1] (SHLLconst [1] x)) // result: (BTRLconst [31] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = 31 v.AddArg(x) return true } // match: (SHRLconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRQ_0(v *Value) bool { b := v.Block // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHRQ x (MOVLconst [c])) // result: (SHRQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHRQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRQconst_0(v *Value) bool { // match: (SHRQconst [1] (SHLQconst [1] x)) // result: (BTRQconst [63] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = 63 v.AddArg(x) return true } // match: (SHRQconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRW_0(v *Value) bool { // match: (SHRW x (MOVQconst [c])) // cond: c&31 < 16 // result: (SHRWconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRW _ (MOVQconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SHRWconst_0(v *Value) bool { // match: (SHRWconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBL_0(v *Value) bool { b := v.Block // match: (SUBL x (MOVLconst [c])) // result: (SUBLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SUBLconst) v.AuxInt = c v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // result: (NEGL (SUBLconst x [c])) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x x) // result: (MOVLconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBLconst_0(v *Value) bool { // match: (SUBLconst [c] x) // cond: int32(c) == 0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SUBLconst [c] x) // result: (ADDLconst [int64(int32(-c))] x) for { c := v.AuxInt x := v.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int64(int32(-c)) v.AddArg(x) return true } } func rewriteValueAMD64_OpAMD64SUBLload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (SUBL x (MOVLf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSSstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBL) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBLmodify_0(v *Value) bool { // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQ_0(v *Value) bool { b := v.Block // match: (SUBQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconst) v.AuxInt = c v.AddArg(x) return true } // match: (SUBQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (NEGQ (SUBQconst x [c])) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBQ x x) // result: (MOVQconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBQload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQborrow_0(v *Value) bool { // match: (SUBQborrow x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconstborrow x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQconst_0(v *Value) bool { // match: (SUBQconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SUBQconst [c] x) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { c := v.AuxInt x := v.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = -c v.AddArg(x) return true } // match: (SUBQconst (MOVQconst [d]) [c]) // result: (MOVQconst [d-c]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = d - c return true } // match: (SUBQconst (SUBQconst x [d]) [c]) // cond: is32Bit(-c-d) // result: (ADDQconst [-c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SUBQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(-c - d)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = -c - d v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBQload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (SUBQ x (MOVQf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSDstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBQ) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBQmodify_0(v *Value) bool { // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SUBQmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSD_0(v *Value) bool { // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSDload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (SUBSD x (MOVQi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVQstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBSD) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBSS_0(v *Value) bool { // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSSload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (SUBSS x (MOVLi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVLstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBSS) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64TESTB_0(v *Value) bool { b := v.Block // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64TESTBconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTB x (MOVLconst [c])) // result: (TESTBconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64TESTBconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0,off)] ptr mem) for { l2 := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVBload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (TESTB l2 l:(MOVBload {sym} [off] ptr mem)) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] l2 := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVBload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64TESTBconst_0(v *Value) bool { // match: (TESTBconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTB x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTB) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64TESTL_0(v *Value) bool { b := v.Block // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64TESTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTL x (MOVLconst [c])) // result: (TESTLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64TESTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0,off)] ptr mem) for { l2 := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (TESTL l2 l:(MOVLload {sym} [off] ptr mem)) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] l2 := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64TESTLconst_0(v *Value) bool { // match: (TESTLconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTL x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTL) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64TESTQ_0(v *Value) bool { b := v.Block // match: (TESTQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (TESTQconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64TESTQconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (TESTQconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64TESTQconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0,off)] ptr mem) for { l2 := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (TESTQ l2 l:(MOVQload {sym} [off] ptr mem)) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] l2 := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64TESTQconst_0(v *Value) bool { // match: (TESTQconst [-1] x) // cond: x.Op != OpAMD64MOVQconst // result: (TESTQ x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVQconst) { break } v.reset(OpAMD64TESTQ) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64TESTW_0(v *Value) bool { b := v.Block // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64TESTWconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTW x (MOVLconst [c])) // result: (TESTWconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64TESTWconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0,off)] ptr mem) for { l2 := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVWload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (TESTW l2 l:(MOVWload {sym} [off] ptr mem)) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] l2 := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVWload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64TESTWconst_0(v *Value) bool { // match: (TESTWconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTW x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTW) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64XADDLlock_0(v *Value) bool { // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XADDLlock [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XADDLlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XADDQlock_0(v *Value) bool { // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XADDQlock [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XADDQlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGL_0(v *Value) bool { // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XCHGL [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XCHGL) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux ptr := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGL) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGQ_0(v *Value) bool { // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XCHGQ [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux ptr := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XORL_0(v *Value) bool { // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { break } v.reset(OpAMD64BTCL) v.AddArg(x) v.AddArg(y) return true } // match: (XORL x (SHLL (MOVLconst [1]) y)) // result: (BTCL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64MOVLconst || v_1_0.AuxInt != 1 { break } v.reset(OpAMD64BTCL) v.AddArg(x) v.AddArg(y) return true } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCLconst [log2uint32(c)] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (XORL x (MOVLconst [c])) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCLconst [log2uint32(c)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64XORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (MOVLconst [c]) x) // result: (XORLconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64XORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHRLconst x [d]) (SHLLconst x [c])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { break } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHRWconst x [d]) (SHLLconst x [c])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { break } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64XORL_10(v *Value) bool { // match: (XORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRBconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { break } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHRBconst x [d]) (SHLLconst x [c])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRBconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { break } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL x x) // result: (MOVLconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64XORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (XORL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64XORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XORLconst_0(v *Value) bool { // match: (XORLconst [c] x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCLconst [log2uint32(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (XORLconst [1] (SETNE x)) // result: (SETEQ x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETNE { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (XORLconst [1] (SETEQ x)) // result: (SETNE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETEQ { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (XORLconst [1] (SETL x)) // result: (SETGE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETL { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (XORLconst [1] (SETGE x)) // result: (SETL x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETGE { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (XORLconst [1] (SETLE x)) // result: (SETG x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETLE { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (XORLconst [1] (SETG x)) // result: (SETLE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETG { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (XORLconst [1] (SETB x)) // result: (SETAE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETB { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (XORLconst [1] (SETAE x)) // result: (SETB x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETAE { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (XORLconst [1] (SETBE x)) // result: (SETA x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETBE { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64XORLconst_10(v *Value) bool { // match: (XORLconst [1] (SETA x)) // result: (SETBE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETA { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (XORLconst [c] (XORLconst [d] x)) // result: (XORLconst [c ^ d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64XORLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORLconst [c] (BTCLconst [d] x)) // result: (XORLconst [c ^ 1<= 128 // result: (BTCQconst [log2(c)] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (XORQ x (MOVQconst [c])) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCQconst [log2(c)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64XORQconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (XORQconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64XORQconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORQ (SHRQconst x [d]) (SHLQconst x [c])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORQ x x) // result: (MOVQconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64XORQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XORQ_10(v *Value) bool { // match: (XORQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64XORQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XORQconst_0(v *Value) bool { // match: (XORQconst [c] x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCQconst [log2(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (XORQconst [c] (XORQconst [d] x)) // result: (XORQconst [c ^ d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64XORQconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64XORQconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORQconst [c] (BTCQconst [d] x)) // result: (XORQconst [c ^ 1< val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore64 ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore8 ptr val mem) // result: (Select1 (XCHGB val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStorePtrNoWB_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (AtomicStorePtrNoWB ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAvg64u_0(v *Value) bool { // match: (Avg64u x y) // result: (AVGQU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64AVGQU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpBitLen16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen16 x) // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) for { x := v.Args[0] v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = 1 v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v2.AddArg(x) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) for { x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) v1.AuxInt = 1 v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v2.AddArg(x) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) for { t := v.Type x := v.Args[0] v.reset(OpAMD64ADDQconst) v.AuxInt = 1 v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) v1 := b.NewValue0(v.Pos, OpSelect0, t) v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v3.AuxInt = -1 v0.AddArg(v3) v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v5 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v5.AddArg(x) v4.AddArg(v5) v0.AddArg(v4) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen8 x) // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) for { x := v.Args[0] v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = 1 v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v2.AddArg(x) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBswap32_0(v *Value) bool { // match: (Bswap32 x) // result: (BSWAPL x) for { x := v.Args[0] v.reset(OpAMD64BSWAPL) v.AddArg(x) return true } } func rewriteValueAMD64_OpBswap64_0(v *Value) bool { // match: (Bswap64 x) // result: (BSWAPQ x) for { x := v.Args[0] v.reset(OpAMD64BSWAPQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCeil_0(v *Value) bool { // match: (Ceil x) // result: (ROUNDSD [2] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 2 v.AddArg(x) return true } } func rewriteValueAMD64_OpClosureCall_0(v *Value) bool { // match: (ClosureCall [argwid] entry closure mem) // result: (CALLclosure [argwid] entry closure mem) for { argwid := v.AuxInt mem := v.Args[2] entry := v.Args[0] closure := v.Args[1] v.reset(OpAMD64CALLclosure) v.AuxInt = argwid v.AddArg(entry) v.AddArg(closure) v.AddArg(mem) return true } } func rewriteValueAMD64_OpCom16_0(v *Value) bool { // match: (Com16 x) // result: (NOTL x) for { x := v.Args[0] v.reset(OpAMD64NOTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCom32_0(v *Value) bool { // match: (Com32 x) // result: (NOTL x) for { x := v.Args[0] v.reset(OpAMD64NOTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCom64_0(v *Value) bool { // match: (Com64 x) // result: (NOTQ x) for { x := v.Args[0] v.reset(OpAMD64NOTQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCom8_0(v *Value) bool { // match: (Com8 x) // result: (NOTL x) for { x := v.Args[0] v.reset(OpAMD64NOTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCondSelect_0(v *Value) bool { // match: (CondSelect x y (SETEQ cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQ y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQ) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETL cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETG cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETA cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQHI y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQHI) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETB cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCC y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCC) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_10(v *Value) bool { // match: (CondSelect x y (SETEQF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGTF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGTF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is32BitInt(t) // result: (CMOVLEQ y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQ) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is32BitInt(t) // result: (CMOVLNE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is32BitInt(t) // result: (CMOVLLT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is32BitInt(t) // result: (CMOVLGT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is32BitInt(t) // result: (CMOVLLE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is32BitInt(t) // result: (CMOVLGE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_20(v *Value) bool { // match: (CondSelect x y (SETA cond)) // cond: is32BitInt(t) // result: (CMOVLHI y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLHI) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is32BitInt(t) // result: (CMOVLCS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is32BitInt(t) // result: (CMOVLCC y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCC) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is32BitInt(t) // result: (CMOVLLS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is32BitInt(t) // result: (CMOVLEQF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is32BitInt(t) // result: (CMOVLNEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is32BitInt(t) // result: (CMOVLGTF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGTF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is32BitInt(t) // result: (CMOVLGEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is16BitInt(t) // result: (CMOVWEQ y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQ) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is16BitInt(t) // result: (CMOVWNE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_30(v *Value) bool { // match: (CondSelect x y (SETL cond)) // cond: is16BitInt(t) // result: (CMOVWLT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is16BitInt(t) // result: (CMOVWGT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is16BitInt(t) // result: (CMOVWLE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is16BitInt(t) // result: (CMOVWGE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is16BitInt(t) // result: (CMOVWHI y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWHI) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is16BitInt(t) // result: (CMOVWCS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is16BitInt(t) // result: (CMOVWCC y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCC) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is16BitInt(t) // result: (CMOVWLS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is16BitInt(t) // result: (CMOVWEQF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is16BitInt(t) // result: (CMOVWNEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_40(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (CondSelect x y (SETGF cond)) // cond: is16BitInt(t) // result: (CMOVWGTF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGTF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is16BitInt(t) // result: (CMOVWGEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 1 // result: (CondSelect x y (MOVBQZX check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 1) { break } v.reset(OpCondSelect) v.Type = t v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64) v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 2 // result: (CondSelect x y (MOVWQZX check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 2) { break } v.reset(OpCondSelect) v.Type = t v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64) v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 4 // result: (CondSelect x y (MOVLQZX check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 4) { break } v.reset(OpCondSelect) v.Type = t v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x (CMPQconst [0] check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { break } v.reset(OpAMD64CMOVQNE) v.AddArg(y) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) // result: (CMOVLNE y x (CMPQconst [0] check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg(y) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) // result: (CMOVWNE y x (CMPQconst [0] check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg(y) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(check) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpConst16_0(v *Value) bool { // match: (Const16 [val]) // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst32_0(v *Value) bool { // match: (Const32 [val]) // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst32F_0(v *Value) bool { // match: (Const32F [val]) // result: (MOVSSconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVSSconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst64_0(v *Value) bool { // match: (Const64 [val]) // result: (MOVQconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst64F_0(v *Value) bool { // match: (Const64F [val]) // result: (MOVSDconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVSDconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst8_0(v *Value) bool { // match: (Const8 [val]) // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConstBool_0(v *Value) bool { // match: (ConstBool [b]) // result: (MOVLconst [b]) for { b := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = b return true } } func rewriteValueAMD64_OpConstNil_0(v *Value) bool { // match: (ConstNil) // result: (MOVQconst [0]) for { v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } } func rewriteValueAMD64_OpCtz16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (BSFL (BTSLconst [16] x)) for { x := v.Args[0] v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = 16 v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz16NonZero_0(v *Value) bool { // match: (Ctz16NonZero x) // result: (BSFL x) for { x := v.Args[0] v.reset(OpAMD64BSFL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCtz32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // result: (Select0 (BSFQ (BTSQconst [32] x))) for { x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) v1.AuxInt = 32 v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz32NonZero_0(v *Value) bool { // match: (Ctz32NonZero x) // result: (BSFL x) for { x := v.Args[0] v.reset(OpAMD64BSFL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCtz64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) for { t := v.Type x := v.Args[0] v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v2.AuxInt = 64 v.AddArg(v2) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v4.AddArg(x) v3.AddArg(v4) v.AddArg(v3) return true } } func rewriteValueAMD64_OpCtz64NonZero_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz64NonZero x) // result: (Select0 (BSFQ x)) for { x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (BSFL (BTSLconst [ 8] x)) for { x := v.Args[0] v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = 8 v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8NonZero_0(v *Value) bool { // match: (Ctz8NonZero x) // result: (BSFL x) for { x := v.Args[0] v.reset(OpAMD64BSFL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32Fto32_0(v *Value) bool { // match: (Cvt32Fto32 x) // result: (CVTTSS2SL x) for { x := v.Args[0] v.reset(OpAMD64CVTTSS2SL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32Fto64_0(v *Value) bool { // match: (Cvt32Fto64 x) // result: (CVTTSS2SQ x) for { x := v.Args[0] v.reset(OpAMD64CVTTSS2SQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32Fto64F_0(v *Value) bool { // match: (Cvt32Fto64F x) // result: (CVTSS2SD x) for { x := v.Args[0] v.reset(OpAMD64CVTSS2SD) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32to32F_0(v *Value) bool { // match: (Cvt32to32F x) // result: (CVTSL2SS x) for { x := v.Args[0] v.reset(OpAMD64CVTSL2SS) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32to64F_0(v *Value) bool { // match: (Cvt32to64F x) // result: (CVTSL2SD x) for { x := v.Args[0] v.reset(OpAMD64CVTSL2SD) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64Fto32_0(v *Value) bool { // match: (Cvt64Fto32 x) // result: (CVTTSD2SL x) for { x := v.Args[0] v.reset(OpAMD64CVTTSD2SL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64Fto32F_0(v *Value) bool { // match: (Cvt64Fto32F x) // result: (CVTSD2SS x) for { x := v.Args[0] v.reset(OpAMD64CVTSD2SS) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64Fto64_0(v *Value) bool { // match: (Cvt64Fto64 x) // result: (CVTTSD2SQ x) for { x := v.Args[0] v.reset(OpAMD64CVTTSD2SQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64to32F_0(v *Value) bool { // match: (Cvt64to32F x) // result: (CVTSQ2SS x) for { x := v.Args[0] v.reset(OpAMD64CVTSQ2SS) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64to64F_0(v *Value) bool { // match: (Cvt64to64F x) // result: (CVTSQ2SD x) for { x := v.Args[0] v.reset(OpAMD64CVTSQ2SD) v.AddArg(x) return true } } func rewriteValueAMD64_OpDiv128u_0(v *Value) bool { // match: (Div128u xhi xlo y) // result: (DIVQU2 xhi xlo y) for { y := v.Args[2] xhi := v.Args[0] xlo := v.Args[1] v.reset(OpAMD64DIVQU2) v.AddArg(xhi) v.AddArg(xlo) v.AddArg(y) return true } } func rewriteValueAMD64_OpDiv16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16 [a] x y) // result: (Select0 (DIVW [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv16u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (Select0 (DIVWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div32 [a] x y) // result: (Select0 (DIVL [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32F_0(v *Value) bool { // match: (Div32F x y) // result: (DIVSS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64DIVSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpDiv32u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div32u x y) // result: (Select0 (DIVLU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div64 [a] x y) // result: (Select0 (DIVQ [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64F_0(v *Value) bool { // match: (Div64F x y) // result: (DIVSD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64DIVSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpDiv64u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div64u x y) // result: (Select0 (DIVQU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq16_0(v *Value) bool { b := v.Block // match: (Eq16 x y) // result: (SETEQ (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32_0(v *Value) bool { b := v.Block // match: (Eq32 x y) // result: (SETEQ (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32F_0(v *Value) bool { b := v.Block // match: (Eq32F x y) // result: (SETEQF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64_0(v *Value) bool { b := v.Block // match: (Eq64 x y) // result: (SETEQ (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64F_0(v *Value) bool { b := v.Block // match: (Eq64F x y) // result: (SETEQF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq8_0(v *Value) bool { b := v.Block // match: (Eq8 x y) // result: (SETEQ (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqB_0(v *Value) bool { b := v.Block // match: (EqB x y) // result: (SETEQ (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqPtr_0(v *Value) bool { b := v.Block // match: (EqPtr x y) // result: (SETEQ (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpFMA_0(v *Value) bool { // match: (FMA x y z) // result: (VFMADD231SD z x y) for { z := v.Args[2] x := v.Args[0] y := v.Args[1] v.reset(OpAMD64VFMADD231SD) v.AddArg(z) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpFloor_0(v *Value) bool { // match: (Floor x) // result: (ROUNDSD [1] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValueAMD64_OpGeq16_0(v *Value) bool { b := v.Block // match: (Geq16 x y) // result: (SETGE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq16U_0(v *Value) bool { b := v.Block // match: (Geq16U x y) // result: (SETAE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq32_0(v *Value) bool { b := v.Block // match: (Geq32 x y) // result: (SETGE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq32F_0(v *Value) bool { b := v.Block // match: (Geq32F x y) // result: (SETGEF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq32U_0(v *Value) bool { b := v.Block // match: (Geq32U x y) // result: (SETAE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq64_0(v *Value) bool { b := v.Block // match: (Geq64 x y) // result: (SETGE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq64F_0(v *Value) bool { b := v.Block // match: (Geq64F x y) // result: (SETGEF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq64U_0(v *Value) bool { b := v.Block // match: (Geq64U x y) // result: (SETAE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq8_0(v *Value) bool { b := v.Block // match: (Geq8 x y) // result: (SETGE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq8U_0(v *Value) bool { b := v.Block // match: (Geq8U x y) // result: (SETAE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGetCallerPC_0(v *Value) bool { // match: (GetCallerPC) // result: (LoweredGetCallerPC) for { v.reset(OpAMD64LoweredGetCallerPC) return true } } func rewriteValueAMD64_OpGetCallerSP_0(v *Value) bool { // match: (GetCallerSP) // result: (LoweredGetCallerSP) for { v.reset(OpAMD64LoweredGetCallerSP) return true } } func rewriteValueAMD64_OpGetClosurePtr_0(v *Value) bool { // match: (GetClosurePtr) // result: (LoweredGetClosurePtr) for { v.reset(OpAMD64LoweredGetClosurePtr) return true } } func rewriteValueAMD64_OpGetG_0(v *Value) bool { // match: (GetG mem) // result: (LoweredGetG mem) for { mem := v.Args[0] v.reset(OpAMD64LoweredGetG) v.AddArg(mem) return true } } func rewriteValueAMD64_OpGreater16_0(v *Value) bool { b := v.Block // match: (Greater16 x y) // result: (SETG (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater16U_0(v *Value) bool { b := v.Block // match: (Greater16U x y) // result: (SETA (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater32_0(v *Value) bool { b := v.Block // match: (Greater32 x y) // result: (SETG (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater32F_0(v *Value) bool { b := v.Block // match: (Greater32F x y) // result: (SETGF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater32U_0(v *Value) bool { b := v.Block // match: (Greater32U x y) // result: (SETA (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater64_0(v *Value) bool { b := v.Block // match: (Greater64 x y) // result: (SETG (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater64F_0(v *Value) bool { b := v.Block // match: (Greater64F x y) // result: (SETGF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater64U_0(v *Value) bool { b := v.Block // match: (Greater64U x y) // result: (SETA (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater8_0(v *Value) bool { b := v.Block // match: (Greater8 x y) // result: (SETG (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater8U_0(v *Value) bool { b := v.Block // match: (Greater8U x y) // result: (SETA (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpHmul32_0(v *Value) bool { // match: (Hmul32 x y) // result: (HMULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpHmul32u_0(v *Value) bool { // match: (Hmul32u x y) // result: (HMULLU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULLU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpHmul64_0(v *Value) bool { // match: (Hmul64 x y) // result: (HMULQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpHmul64u_0(v *Value) bool { // match: (Hmul64u x y) // result: (HMULQU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULQU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpInterCall_0(v *Value) bool { // match: (InterCall [argwid] entry mem) // result: (CALLinter [argwid] entry mem) for { argwid := v.AuxInt mem := v.Args[1] entry := v.Args[0] v.reset(OpAMD64CALLinter) v.AuxInt = argwid v.AddArg(entry) v.AddArg(mem) return true } } func rewriteValueAMD64_OpIsInBounds_0(v *Value) bool { b := v.Block // match: (IsInBounds idx len) // result: (SETB (CMPQ idx len)) for { len := v.Args[1] idx := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsNonNil_0(v *Value) bool { b := v.Block // match: (IsNonNil p) // result: (SETNE (TESTQ p p)) for { p := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) v0.AddArg(p) v0.AddArg(p) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsSliceInBounds_0(v *Value) bool { b := v.Block // match: (IsSliceInBounds idx len) // result: (SETBE (CMPQ idx len)) for { len := v.Args[1] idx := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16_0(v *Value) bool { b := v.Block // match: (Leq16 x y) // result: (SETLE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16U_0(v *Value) bool { b := v.Block // match: (Leq16U x y) // result: (SETBE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32_0(v *Value) bool { b := v.Block // match: (Leq32 x y) // result: (SETLE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32F_0(v *Value) bool { b := v.Block // match: (Leq32F x y) // result: (SETGEF (UCOMISS y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32U_0(v *Value) bool { b := v.Block // match: (Leq32U x y) // result: (SETBE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64_0(v *Value) bool { b := v.Block // match: (Leq64 x y) // result: (SETLE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64F_0(v *Value) bool { b := v.Block // match: (Leq64F x y) // result: (SETGEF (UCOMISD y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64U_0(v *Value) bool { b := v.Block // match: (Leq64U x y) // result: (SETBE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8_0(v *Value) bool { b := v.Block // match: (Leq8 x y) // result: (SETLE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8U_0(v *Value) bool { b := v.Block // match: (Leq8U x y) // result: (SETBE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16_0(v *Value) bool { b := v.Block // match: (Less16 x y) // result: (SETL (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16U_0(v *Value) bool { b := v.Block // match: (Less16U x y) // result: (SETB (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32_0(v *Value) bool { b := v.Block // match: (Less32 x y) // result: (SETL (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32F_0(v *Value) bool { b := v.Block // match: (Less32F x y) // result: (SETGF (UCOMISS y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32U_0(v *Value) bool { b := v.Block // match: (Less32U x y) // result: (SETB (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64_0(v *Value) bool { b := v.Block // match: (Less64 x y) // result: (SETL (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64F_0(v *Value) bool { b := v.Block // match: (Less64F x y) // result: (SETGF (UCOMISD y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64U_0(v *Value) bool { b := v.Block // match: (Less64U x y) // result: (SETB (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8_0(v *Value) bool { b := v.Block // match: (Less8 x y) // result: (SETL (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8U_0(v *Value) bool { b := v.Block // match: (Less8U x y) // result: (SETB (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLoad_0(v *Value) bool { // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVQload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64MOVQload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) // result: (MOVLload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64MOVLload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64MOVWload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(OpAMD64MOVBload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitFloat(t)) { break } v.reset(OpAMD64MOVSSload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is64BitFloat(t)) { break } v.reset(OpAMD64MOVSDload) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpLocalAddr_0(v *Value) bool { // match: (LocalAddr {sym} base _) // result: (LEAQ {sym} base) for { sym := v.Aux _ = v.Args[1] base := v.Args[0] v.reset(OpAMD64LEAQ) v.Aux = sym v.AddArg(base) return true } } func rewriteValueAMD64_OpLsh16x16_0(v *Value) bool { b := v.Block // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh16x32_0(v *Value) bool { b := v.Block // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh16x64_0(v *Value) bool { b := v.Block // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh16x8_0(v *Value) bool { b := v.Block // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x16_0(v *Value) bool { b := v.Block // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x32_0(v *Value) bool { b := v.Block // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x64_0(v *Value) bool { b := v.Block // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x8_0(v *Value) bool { b := v.Block // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x16_0(v *Value) bool { b := v.Block // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x32_0(v *Value) bool { b := v.Block // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x64_0(v *Value) bool { b := v.Block // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x8_0(v *Value) bool { b := v.Block // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x16_0(v *Value) bool { b := v.Block // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x32_0(v *Value) bool { b := v.Block // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x64_0(v *Value) bool { b := v.Block // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x8_0(v *Value) bool { b := v.Block // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpMod16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod16 [a] x y) // result: (Select1 (DIVW [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod16u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Select1 (DIVWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod32 [a] x y) // result: (Select1 (DIVL [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (Select1 (DIVLU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod64 [a] x y) // result: (Select1 (DIVQ [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (Select1 (DIVQU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMove_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if v.AuxInt != 0 { break } mem := v.Args[2] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBload src mem) mem) for { if v.AuxInt != 1 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [2] dst src mem) // result: (MOVWstore dst (MOVWload src mem) mem) for { if v.AuxInt != 2 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVWstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [4] dst src mem) // result: (MOVLstore dst (MOVLload src mem) mem) for { if v.AuxInt != 4 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVLstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [8] dst src mem) // result: (MOVQstore dst (MOVQload src mem) mem) for { if v.AuxInt != 8 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVQstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [16] dst src mem) // cond: config.useSSE // result: (MOVOstore dst (MOVOload src mem) mem) for { if v.AuxInt != 16 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [16] dst src mem) // cond: !config.useSSE // result: (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 16 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [32] dst src mem) // result: (Move [16] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if v.AuxInt != 32 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpMove) v.AuxInt = 16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = 16 v2.AddArg(dst) v2.AddArg(src) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Move [48] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if v.AuxInt != 48 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = 32 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = 16 v2.AddArg(dst) v2.AddArg(src) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Move [64] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [32]) (OffPtr src [32]) (Move [32] dst src mem)) for { if v.AuxInt != 64 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = 32 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = 32 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = 32 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = 32 v2.AddArg(dst) v2.AddArg(src) v2.AddArg(mem) v.AddArg(v2) return true } return false } func rewriteValueAMD64_OpMove_10(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if v.AuxInt != 3 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AuxInt = 2 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = 2 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 5 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [6] dst src mem) // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 6 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVWstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [7] dst src mem) // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 7 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVLstore) v.AuxInt = 3 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = 3 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 9 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [10] dst src mem) // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 10 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVWstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [12] dst src mem) // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 12 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVLstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [s] dst src mem) // cond: s == 11 || s >= 13 && s <= 15 // result: (MOVQstore [s-8] dst (MOVQload [s-8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s == 11 || s >= 13 && s <= 15) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = s - 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = s - 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 <= 8 // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore dst (MOVQload src mem) mem)) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 16 && s%16 != 0 && s%16 <= 8) { break } v.reset(OpMove) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = s % 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = s % 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVOstore dst (MOVOload src mem) mem)) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE) { break } v.reset(OpMove) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = s % 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = s % 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } return false } func rewriteValueAMD64_OpMove_20(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE) { break } v.reset(OpMove) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = s % 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = s % 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AuxInt = 8 v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AuxInt = 8 v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v5.AddArg(src) v5.AddArg(mem) v4.AddArg(v5) v4.AddArg(mem) v2.AddArg(v4) v.AddArg(v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice // result: (DUFFCOPY [14*(64-s/16)] dst src mem) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFCOPY) v.AuxInt = 14 * (64 - s/16) v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } // match: (Move [s] dst src mem) // cond: (s > 16*64 || config.noDuffDevice) && s%8 == 0 // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !((s > 16*64 || config.noDuffDevice) && s%8 == 0) { break } v.reset(OpAMD64REPMOVSQ) v.AddArg(dst) v.AddArg(src) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = s / 8 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpMul16_0(v *Value) bool { // match: (Mul16 x y) // result: (MULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul32_0(v *Value) bool { // match: (Mul32 x y) // result: (MULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul32F_0(v *Value) bool { // match: (Mul32F x y) // result: (MULSS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul64_0(v *Value) bool { // match: (Mul64 x y) // result: (MULQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul64F_0(v *Value) bool { // match: (Mul64F x y) // result: (MULSD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul64uhilo_0(v *Value) bool { // match: (Mul64uhilo x y) // result: (MULQU2 x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULQU2) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul8_0(v *Value) bool { // match: (Mul8 x y) // result: (MULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpNeg16_0(v *Value) bool { // match: (Neg16 x) // result: (NEGL x) for { x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeg32_0(v *Value) bool { // match: (Neg32 x) // result: (NEGL x) for { x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeg32F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Neg32F x) // result: (PXOR x (MOVSSconst [auxFrom32F(float32(math.Copysign(0, -1)))])) for { x := v.Args[0] v.reset(OpAMD64PXOR) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) v0.AuxInt = auxFrom32F(float32(math.Copysign(0, -1))) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeg64_0(v *Value) bool { // match: (Neg64 x) // result: (NEGQ x) for { x := v.Args[0] v.reset(OpAMD64NEGQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeg64F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Neg64F x) // result: (PXOR x (MOVSDconst [auxFrom64F(math.Copysign(0, -1))])) for { x := v.Args[0] v.reset(OpAMD64PXOR) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) v0.AuxInt = auxFrom64F(math.Copysign(0, -1)) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeg8_0(v *Value) bool { // match: (Neg8 x) // result: (NEGL x) for { x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeq16_0(v *Value) bool { b := v.Block // match: (Neq16 x y) // result: (SETNE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32_0(v *Value) bool { b := v.Block // match: (Neq32 x y) // result: (SETNE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32F_0(v *Value) bool { b := v.Block // match: (Neq32F x y) // result: (SETNEF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64_0(v *Value) bool { b := v.Block // match: (Neq64 x y) // result: (SETNE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64F_0(v *Value) bool { b := v.Block // match: (Neq64F x y) // result: (SETNEF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq8_0(v *Value) bool { b := v.Block // match: (Neq8 x y) // result: (SETNE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqB_0(v *Value) bool { b := v.Block // match: (NeqB x y) // result: (SETNE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqPtr_0(v *Value) bool { b := v.Block // match: (NeqPtr x y) // result: (SETNE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNilCheck_0(v *Value) bool { // match: (NilCheck ptr mem) // result: (LoweredNilCheck ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpAMD64LoweredNilCheck) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValueAMD64_OpNot_0(v *Value) bool { // match: (Not x) // result: (XORLconst [1] x) for { x := v.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValueAMD64_OpOffPtr_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // cond: is32Bit(off) // result: (ADDQconst [off] ptr) for { off := v.AuxInt ptr := v.Args[0] if !(is32Bit(off)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = off v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDQ (MOVQconst [off]) ptr) for { off := v.AuxInt ptr := v.Args[0] v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = off v.AddArg(v0) v.AddArg(ptr) return true } } func rewriteValueAMD64_OpOr16_0(v *Value) bool { // match: (Or16 x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOr32_0(v *Value) bool { // match: (Or32 x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOr64_0(v *Value) bool { // match: (Or64 x y) // result: (ORQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOr8_0(v *Value) bool { // match: (Or8 x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOrB_0(v *Value) bool { // match: (OrB x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpPanicBounds_0(v *Value) bool { // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 0) { break } v.reset(OpAMD64LoweredPanicBoundsA) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 1) { break } v.reset(OpAMD64LoweredPanicBoundsB) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 2) { break } v.reset(OpAMD64LoweredPanicBoundsC) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpPopCount16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTL (MOVWQZX x)) for { x := v.Args[0] v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpPopCount32_0(v *Value) bool { // match: (PopCount32 x) // result: (POPCNTL x) for { x := v.Args[0] v.reset(OpAMD64POPCNTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpPopCount64_0(v *Value) bool { // match: (PopCount64 x) // result: (POPCNTQ x) for { x := v.Args[0] v.reset(OpAMD64POPCNTQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpPopCount8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTL (MOVBQZX x)) for { x := v.Args[0] v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpRotateLeft16_0(v *Value) bool { // match: (RotateLeft16 a b) // result: (ROLW a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLW) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRotateLeft32_0(v *Value) bool { // match: (RotateLeft32 a b) // result: (ROLL a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLL) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRotateLeft64_0(v *Value) bool { // match: (RotateLeft64 a b) // result: (ROLQ a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLQ) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRotateLeft8_0(v *Value) bool { // match: (RotateLeft8 a b) // result: (ROLB a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLB) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRound32F_0(v *Value) bool { // match: (Round32F x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpRound64F_0(v *Value) bool { // match: (Round64F x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpRoundToEven_0(v *Value) bool { // match: (RoundToEven x) // result: (ROUNDSD [0] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 0 v.AddArg(x) return true } } func rewriteValueAMD64_OpRsh16Ux16_0(v *Value) bool { b := v.Block // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16Ux32_0(v *Value) bool { b := v.Block // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16Ux64_0(v *Value) bool { b := v.Block // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16Ux8_0(v *Value) bool { b := v.Block // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x16_0(v *Value) bool { b := v.Block // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x32_0(v *Value) bool { b := v.Block // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x64_0(v *Value) bool { b := v.Block // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x8_0(v *Value) bool { b := v.Block // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux16_0(v *Value) bool { b := v.Block // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux32_0(v *Value) bool { b := v.Block // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux64_0(v *Value) bool { b := v.Block // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux8_0(v *Value) bool { b := v.Block // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x16_0(v *Value) bool { b := v.Block // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x32_0(v *Value) bool { b := v.Block // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x64_0(v *Value) bool { b := v.Block // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x8_0(v *Value) bool { b := v.Block // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux16_0(v *Value) bool { b := v.Block // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux32_0(v *Value) bool { b := v.Block // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux64_0(v *Value) bool { b := v.Block // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux8_0(v *Value) bool { b := v.Block // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x16_0(v *Value) bool { b := v.Block // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x32_0(v *Value) bool { b := v.Block // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x64_0(v *Value) bool { b := v.Block // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x8_0(v *Value) bool { b := v.Block // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux16_0(v *Value) bool { b := v.Block // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux32_0(v *Value) bool { b := v.Block // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux64_0(v *Value) bool { b := v.Block // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux8_0(v *Value) bool { b := v.Block // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x16_0(v *Value) bool { b := v.Block // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x32_0(v *Value) bool { b := v.Block // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x64_0(v *Value) bool { b := v.Block // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x8_0(v *Value) bool { b := v.Block // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpSelect0_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uover x y)) // result: (Select0 (MULQU x y)) for { v_0 := v.Args[0] if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (Select0 (Mul32uover x y)) // result: (Select0 (MULLU x y)) for { v_0 := v.Args[0] if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) for { v_0 := v.Args[0] if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y c)) // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) for { v_0 := v.Args[0] if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst32 val tuple)) // result: (ADDL val (Select0 tuple)) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDL) v.AddArg(val) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst64 val tuple)) // result: (ADDQ val (Select0 tuple)) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDQ) v.AddArg(val) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpSelect1_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uover x y)) // result: (SETO (Select1 (MULQU x y))) for { v_0 := v.Args[0] if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul32uover x y)) // result: (SETO (Select1 (MULLU x y))) for { v_0 := v.Args[0] if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Add64carry x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) for { v_0 := v.Args[0] if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v2.AddArg(y) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) for { v_0 := v.Args[0] if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v2.AddArg(y) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (NEGLflags (MOVQconst [0]))) // result: (FlagEQ) for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst || v_0_0.AuxInt != 0 { break } v.reset(OpAMD64FlagEQ) return true } // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) // result: x for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64SBBQcarrymask { break } x := v_0_0_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Select1 (AddTupleFirst32 _ tuple)) // result: (Select1 tuple) for { v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } // match: (Select1 (AddTupleFirst64 _ tuple)) // result: (Select1 tuple) for { v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } return false } func rewriteValueAMD64_OpSignExt16to32_0(v *Value) bool { // match: (SignExt16to32 x) // result: (MOVWQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt16to64_0(v *Value) bool { // match: (SignExt16to64 x) // result: (MOVWQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt32to64_0(v *Value) bool { // match: (SignExt32to64 x) // result: (MOVLQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt8to16_0(v *Value) bool { // match: (SignExt8to16 x) // result: (MOVBQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt8to32_0(v *Value) bool { // match: (SignExt8to32 x) // result: (MOVBQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt8to64_0(v *Value) bool { // match: (SignExt8to64 x) // result: (MOVBQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSlicemask_0(v *Value) bool { b := v.Block // match: (Slicemask x) // result: (SARQconst (NEGQ x) [63]) for { t := v.Type x := v.Args[0] v.reset(OpAMD64SARQconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpSqrt_0(v *Value) bool { // match: (Sqrt x) // result: (SQRTSD x) for { x := v.Args[0] v.reset(OpAMD64SQRTSD) v.AddArg(x) return true } } func rewriteValueAMD64_OpStaticCall_0(v *Value) bool { // match: (StaticCall [argwid] {target} mem) // result: (CALLstatic [argwid] {target} mem) for { argwid := v.AuxInt target := v.Aux mem := v.Args[0] v.reset(OpAMD64CALLstatic) v.AuxInt = argwid v.Aux = target v.AddArg(mem) return true } } func rewriteValueAMD64_OpStore_0(v *Value) bool { // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) // result: (MOVSDstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) // result: (MOVSSstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSSstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 // result: (MOVQstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8) { break } v.reset(OpAMD64MOVQstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 // result: (MOVLstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 4) { break } v.reset(OpAMD64MOVLstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 2 // result: (MOVWstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 2) { break } v.reset(OpAMD64MOVWstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 1 // result: (MOVBstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 1) { break } v.reset(OpAMD64MOVBstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpSub16_0(v *Value) bool { // match: (Sub16 x y) // result: (SUBL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub32_0(v *Value) bool { // match: (Sub32 x y) // result: (SUBL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub32F_0(v *Value) bool { // match: (Sub32F x y) // result: (SUBSS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub64_0(v *Value) bool { // match: (Sub64 x y) // result: (SUBQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub64F_0(v *Value) bool { // match: (Sub64F x y) // result: (SUBSD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub8_0(v *Value) bool { // match: (Sub8 x y) // result: (SUBL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSubPtr_0(v *Value) bool { // match: (SubPtr x y) // result: (SUBQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpTrunc_0(v *Value) bool { // match: (Trunc x) // result: (ROUNDSD [3] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 3 v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc16to8_0(v *Value) bool { // match: (Trunc16to8 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc32to16_0(v *Value) bool { // match: (Trunc32to16 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc32to8_0(v *Value) bool { // match: (Trunc32to8 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc64to16_0(v *Value) bool { // match: (Trunc64to16 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc64to32_0(v *Value) bool { // match: (Trunc64to32 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc64to8_0(v *Value) bool { // match: (Trunc64to8 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpWB_0(v *Value) bool { // match: (WB {fn} destptr srcptr mem) // result: (LoweredWB {fn} destptr srcptr mem) for { fn := v.Aux mem := v.Args[2] destptr := v.Args[0] srcptr := v.Args[1] v.reset(OpAMD64LoweredWB) v.Aux = fn v.AddArg(destptr) v.AddArg(srcptr) v.AddArg(mem) return true } } func rewriteValueAMD64_OpXor16_0(v *Value) bool { // match: (Xor16 x y) // result: (XORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpXor32_0(v *Value) bool { // match: (Xor32 x y) // result: (XORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpXor64_0(v *Value) bool { // match: (Xor64 x y) // result: (XORQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpXor8_0(v *Value) bool { // match: (Xor8 x y) // result: (XORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpZero_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (Zero [0] _ mem) // result: mem for { if v.AuxInt != 0 { break } mem := v.Args[1] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstoreconst [0] destptr mem) for { if v.AuxInt != 1 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVBstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [2] destptr mem) // result: (MOVWstoreconst [0] destptr mem) for { if v.AuxInt != 2 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVWstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [4] destptr mem) // result: (MOVLstoreconst [0] destptr mem) for { if v.AuxInt != 4 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVLstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [8] destptr mem) // result: (MOVQstoreconst [0] destptr mem) for { if v.AuxInt != 8 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVQstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [0] destptr mem)) for { if v.AuxInt != 3 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(0, 2) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [5] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 5 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [6] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 6 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [7] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 7 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(0, 3) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s%8 != 0 && s > 8 && !config.useSSE // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVQstoreconst [0] destptr mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s%8 != 0 && s > 8 && !config.useSSE) { break } v.reset(OpZero) v.AuxInt = s - s%8 v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = s % 8 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v.AddArg(v1) return true } return false } func rewriteValueAMD64_OpZero_10(v *Value) bool { b := v.Block config := b.Func.Config // match: (Zero [16] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem)) for { if v.AuxInt != 16 { break } mem := v.Args[1] destptr := v.Args[0] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, 8) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [24] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem))) for { if v.AuxInt != 24 { break } mem := v.Args[1] destptr := v.Args[0] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, 16) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = makeValAndOff(0, 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [32] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem)))) for { if v.AuxInt != 32 { break } mem := v.Args[1] destptr := v.Args[0] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, 24) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = makeValAndOff(0, 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = makeValAndOff(0, 8) v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v2.AuxInt = 0 v2.AddArg(destptr) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s > 8 && s < 16 && config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,s-8)] destptr (MOVQstoreconst [0] destptr mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s > 8 && s < 16 && config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, s-8) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstore destptr (MOVOconst [0]) mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = s % 16 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v2.AuxInt = 0 v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVQstoreconst [0] destptr mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = s % 16 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Zero [16] destptr mem) // cond: config.useSSE // result: (MOVOstore destptr (MOVOconst [0]) mem) for { if v.AuxInt != 16 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (Zero [32] destptr mem) // cond: config.useSSE // result: (MOVOstore (OffPtr destptr [16]) (MOVOconst [0]) (MOVOstore destptr (MOVOconst [0]) mem)) for { if v.AuxInt != 32 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = 16 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v2.AddArg(destptr) v3 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v3.AuxInt = 0 v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Zero [48] destptr mem) // cond: config.useSSE // result: (MOVOstore (OffPtr destptr [32]) (MOVOconst [0]) (MOVOstore (OffPtr destptr [16]) (MOVOconst [0]) (MOVOstore destptr (MOVOconst [0]) mem))) for { if v.AuxInt != 48 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = 32 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v3.AuxInt = 16 v3.AddArg(destptr) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v4.AuxInt = 0 v2.AddArg(v4) v5 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v5.AddArg(destptr) v6 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v6.AuxInt = 0 v5.AddArg(v6) v5.AddArg(mem) v2.AddArg(v5) v.AddArg(v2) return true } // match: (Zero [64] destptr mem) // cond: config.useSSE // result: (MOVOstore (OffPtr destptr [48]) (MOVOconst [0]) (MOVOstore (OffPtr destptr [32]) (MOVOconst [0]) (MOVOstore (OffPtr destptr [16]) (MOVOconst [0]) (MOVOstore destptr (MOVOconst [0]) mem)))) for { if v.AuxInt != 64 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = 48 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v3.AuxInt = 32 v3.AddArg(destptr) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v4.AuxInt = 0 v2.AddArg(v4) v5 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v6 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v6.AuxInt = 16 v6.AddArg(destptr) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v7.AuxInt = 0 v5.AddArg(v7) v8 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v8.AddArg(destptr) v9 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v9.AuxInt = 0 v8.AddArg(v9) v8.AddArg(mem) v5.AddArg(v8) v2.AddArg(v5) v.AddArg(v2) return true } return false } func rewriteValueAMD64_OpZero_20(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [s] destptr mem) // cond: s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice // result: (DUFFZERO [s] destptr (MOVOconst [0]) mem) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFZERO) v.AuxInt = s v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0 // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !((s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0) { break } v.reset(OpAMD64REPSTOSQ) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = s / 8 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = 0 v.AddArg(v1) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpZeroExt16to32_0(v *Value) bool { // match: (ZeroExt16to32 x) // result: (MOVWQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt16to64_0(v *Value) bool { // match: (ZeroExt16to64 x) // result: (MOVWQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt32to64_0(v *Value) bool { // match: (ZeroExt32to64 x) // result: (MOVLQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt8to16_0(v *Value) bool { // match: (ZeroExt8to16 x) // result: (MOVBQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt8to32_0(v *Value) bool { // match: (ZeroExt8to32 x) // result: (MOVBQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt8to64_0(v *Value) bool { // match: (ZeroExt8to64 x) // result: (MOVBQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } } func rewriteBlockAMD64(b *Block) bool { switch b.Kind { case BlockAMD64EQ: // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (EQ (TESTL y (SHLL (MOVLconst [1]) x))) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLL { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLQ { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (EQ (TESTQ y (SHLQ (MOVQconst [1]) x))) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLQ { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (UGE (BTLconst [log2uint32(c)] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst { break } c := v_0_0.AuxInt if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ x (MOVQconst [c]))) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64MOVQconst { break } c := v_0_1.AuxInt if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ z2 z1:(SHRQconst [63] x))) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTL z2 z1:(SHRLconst [31] x))) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64EQ) b.AddControl(cmp) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64GE: // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LE) b.AddControl(cmp) return true } // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64GT: // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LT) b.AddControl(cmp) return true } // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockIf: // match: (If (SETL cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64SETL { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LT) b.AddControl(cmp) return true } // match: (If (SETLE cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64SETLE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LE) b.AddControl(cmp) return true } // match: (If (SETG cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64SETG { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GT) b.AddControl(cmp) return true } // match: (If (SETGE cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64SETGE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GE) b.AddControl(cmp) return true } // match: (If (SETEQ cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64SETEQ { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64EQ) b.AddControl(cmp) return true } // match: (If (SETNE cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64SETNE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64NE) b.AddControl(cmp) return true } // match: (If (SETB cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64SETB { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULT) b.AddControl(cmp) return true } // match: (If (SETBE cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64SETBE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULE) b.AddControl(cmp) return true } // match: (If (SETA cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETA { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (If (SETAE cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETAE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (If (SETO cmp) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64SETO { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64OS) b.AddControl(cmp) return true } // match: (If (SETGF cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETGF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (If (SETGEF cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETGEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (If (SETEQF cmp) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64SETEQF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64EQF) b.AddControl(cmp) return true } // match: (If (SETNEF cmp) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64SETNEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64NEF) b.AddControl(cmp) return true } // match: (If cond yes no) // result: (NE (TESTB cond cond) yes no) for { cond := b.Controls[0] b.Reset(BlockAMD64NE) v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) v0.AddArg(cond) v0.AddArg(cond) b.AddControl(v0) return true } case BlockAMD64LE: // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GE) b.AddControl(cmp) return true } // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64LT: // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GT) b.AddControl(cmp) return true } // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETL { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64LT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETLE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64LE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETG { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64GT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64GE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQ { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64EQ) b.AddControl(cmp) return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64NE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETB { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64ULT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETBE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64ULE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETA { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETAE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETO { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64OS) b.AddControl(cmp) return true } // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (NE (TESTL y (SHLL (MOVLconst [1]) x))) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLL { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLQ { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (NE (TESTQ y (SHLQ (MOVQconst [1]) x))) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLQ { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (ULT (BTLconst [log2uint32(c)] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst { break } c := v_0_0.AuxInt if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ x (MOVQconst [c]))) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64MOVQconst { break } c := v_0_1.AuxInt if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ z2 z1:(SHRQconst [63] x))) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTL z2 z1:(SHRLconst [31] x))) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64EQF) b.AddControl(cmp) return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64NEF) b.AddControl(cmp) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64NE) b.AddControl(cmp) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGE: // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULE) b.AddControl(cmp) return true } // match: (UGE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (UGE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGT: // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULT) b.AddControl(cmp) return true } // match: (UGT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64ULE: // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (ULE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64ULT: // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (ULT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- y -- // Code generated from gen/AMD64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/compile/internal/types" func rewriteValueAMD64(v *Value) bool { switch v.Op { case OpAMD64ADCQ: return rewriteValueAMD64_OpAMD64ADCQ_0(v) case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst_0(v) case OpAMD64ADDL: return rewriteValueAMD64_OpAMD64ADDL_0(v) || rewriteValueAMD64_OpAMD64ADDL_10(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst_0(v) || rewriteValueAMD64_OpAMD64ADDLconst_10(v) case OpAMD64ADDLconstmodify: return rewriteValueAMD64_OpAMD64ADDLconstmodify_0(v) case OpAMD64ADDLload: return rewriteValueAMD64_OpAMD64ADDLload_0(v) case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify_0(v) case OpAMD64ADDQ: return rewriteValueAMD64_OpAMD64ADDQ_0(v) || rewriteValueAMD64_OpAMD64ADDQ_10(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry_0(v) case OpAMD64ADDQconst: return rewriteValueAMD64_OpAMD64ADDQconst_0(v) || rewriteValueAMD64_OpAMD64ADDQconst_10(v) case OpAMD64ADDQconstmodify: return rewriteValueAMD64_OpAMD64ADDQconstmodify_0(v) case OpAMD64ADDQload: return rewriteValueAMD64_OpAMD64ADDQload_0(v) case OpAMD64ADDQmodify: return rewriteValueAMD64_OpAMD64ADDQmodify_0(v) case OpAMD64ADDSD: return rewriteValueAMD64_OpAMD64ADDSD_0(v) case OpAMD64ADDSDload: return rewriteValueAMD64_OpAMD64ADDSDload_0(v) case OpAMD64ADDSS: return rewriteValueAMD64_OpAMD64ADDSS_0(v) case OpAMD64ADDSSload: return rewriteValueAMD64_OpAMD64ADDSSload_0(v) case OpAMD64ANDL: return rewriteValueAMD64_OpAMD64ANDL_0(v) case OpAMD64ANDLconst: return rewriteValueAMD64_OpAMD64ANDLconst_0(v) case OpAMD64ANDLconstmodify: return rewriteValueAMD64_OpAMD64ANDLconstmodify_0(v) case OpAMD64ANDLload: return rewriteValueAMD64_OpAMD64ANDLload_0(v) case OpAMD64ANDLmodify: return rewriteValueAMD64_OpAMD64ANDLmodify_0(v) case OpAMD64ANDQ: return rewriteValueAMD64_OpAMD64ANDQ_0(v) case OpAMD64ANDQconst: return rewriteValueAMD64_OpAMD64ANDQconst_0(v) case OpAMD64ANDQconstmodify: return rewriteValueAMD64_OpAMD64ANDQconstmodify_0(v) case OpAMD64ANDQload: return rewriteValueAMD64_OpAMD64ANDQload_0(v) case OpAMD64ANDQmodify: return rewriteValueAMD64_OpAMD64ANDQmodify_0(v) case OpAMD64BSFQ: return rewriteValueAMD64_OpAMD64BSFQ_0(v) case OpAMD64BTCLconst: return rewriteValueAMD64_OpAMD64BTCLconst_0(v) case OpAMD64BTCLconstmodify: return rewriteValueAMD64_OpAMD64BTCLconstmodify_0(v) case OpAMD64BTCLmodify: return rewriteValueAMD64_OpAMD64BTCLmodify_0(v) case OpAMD64BTCQconst: return rewriteValueAMD64_OpAMD64BTCQconst_0(v) case OpAMD64BTCQconstmodify: return rewriteValueAMD64_OpAMD64BTCQconstmodify_0(v) case OpAMD64BTCQmodify: return rewriteValueAMD64_OpAMD64BTCQmodify_0(v) case OpAMD64BTLconst: return rewriteValueAMD64_OpAMD64BTLconst_0(v) case OpAMD64BTQconst: return rewriteValueAMD64_OpAMD64BTQconst_0(v) case OpAMD64BTRLconst: return rewriteValueAMD64_OpAMD64BTRLconst_0(v) case OpAMD64BTRLconstmodify: return rewriteValueAMD64_OpAMD64BTRLconstmodify_0(v) case OpAMD64BTRLmodify: return rewriteValueAMD64_OpAMD64BTRLmodify_0(v) case OpAMD64BTRQconst: return rewriteValueAMD64_OpAMD64BTRQconst_0(v) case OpAMD64BTRQconstmodify: return rewriteValueAMD64_OpAMD64BTRQconstmodify_0(v) case OpAMD64BTRQmodify: return rewriteValueAMD64_OpAMD64BTRQmodify_0(v) case OpAMD64BTSLconst: return rewriteValueAMD64_OpAMD64BTSLconst_0(v) case OpAMD64BTSLconstmodify: return rewriteValueAMD64_OpAMD64BTSLconstmodify_0(v) case OpAMD64BTSLmodify: return rewriteValueAMD64_OpAMD64BTSLmodify_0(v) case OpAMD64BTSQconst: return rewriteValueAMD64_OpAMD64BTSQconst_0(v) case OpAMD64BTSQconstmodify: return rewriteValueAMD64_OpAMD64BTSQconstmodify_0(v) case OpAMD64BTSQmodify: return rewriteValueAMD64_OpAMD64BTSQmodify_0(v) case OpAMD64CMOVLCC: return rewriteValueAMD64_OpAMD64CMOVLCC_0(v) case OpAMD64CMOVLCS: return rewriteValueAMD64_OpAMD64CMOVLCS_0(v) case OpAMD64CMOVLEQ: return rewriteValueAMD64_OpAMD64CMOVLEQ_0(v) case OpAMD64CMOVLGE: return rewriteValueAMD64_OpAMD64CMOVLGE_0(v) case OpAMD64CMOVLGT: return rewriteValueAMD64_OpAMD64CMOVLGT_0(v) case OpAMD64CMOVLHI: return rewriteValueAMD64_OpAMD64CMOVLHI_0(v) case OpAMD64CMOVLLE: return rewriteValueAMD64_OpAMD64CMOVLLE_0(v) case OpAMD64CMOVLLS: return rewriteValueAMD64_OpAMD64CMOVLLS_0(v) case OpAMD64CMOVLLT: return rewriteValueAMD64_OpAMD64CMOVLLT_0(v) case OpAMD64CMOVLNE: return rewriteValueAMD64_OpAMD64CMOVLNE_0(v) case OpAMD64CMOVQCC: return rewriteValueAMD64_OpAMD64CMOVQCC_0(v) case OpAMD64CMOVQCS: return rewriteValueAMD64_OpAMD64CMOVQCS_0(v) case OpAMD64CMOVQEQ: return rewriteValueAMD64_OpAMD64CMOVQEQ_0(v) case OpAMD64CMOVQGE: return rewriteValueAMD64_OpAMD64CMOVQGE_0(v) case OpAMD64CMOVQGT: return rewriteValueAMD64_OpAMD64CMOVQGT_0(v) case OpAMD64CMOVQHI: return rewriteValueAMD64_OpAMD64CMOVQHI_0(v) case OpAMD64CMOVQLE: return rewriteValueAMD64_OpAMD64CMOVQLE_0(v) case OpAMD64CMOVQLS: return rewriteValueAMD64_OpAMD64CMOVQLS_0(v) case OpAMD64CMOVQLT: return rewriteValueAMD64_OpAMD64CMOVQLT_0(v) case OpAMD64CMOVQNE: return rewriteValueAMD64_OpAMD64CMOVQNE_0(v) case OpAMD64CMOVWCC: return rewriteValueAMD64_OpAMD64CMOVWCC_0(v) case OpAMD64CMOVWCS: return rewriteValueAMD64_OpAMD64CMOVWCS_0(v) case OpAMD64CMOVWEQ: return rewriteValueAMD64_OpAMD64CMOVWEQ_0(v) case OpAMD64CMOVWGE: return rewriteValueAMD64_OpAMD64CMOVWGE_0(v) case OpAMD64CMOVWGT: return rewriteValueAMD64_OpAMD64CMOVWGT_0(v) case OpAMD64CMOVWHI: return rewriteValueAMD64_OpAMD64CMOVWHI_0(v) case OpAMD64CMOVWLE: return rewriteValueAMD64_OpAMD64CMOVWLE_0(v) case OpAMD64CMOVWLS: return rewriteValueAMD64_OpAMD64CMOVWLS_0(v) case OpAMD64CMOVWLT: return rewriteValueAMD64_OpAMD64CMOVWLT_0(v) case OpAMD64CMOVWNE: return rewriteValueAMD64_OpAMD64CMOVWNE_0(v) case OpAMD64CMPB: return rewriteValueAMD64_OpAMD64CMPB_0(v) case OpAMD64CMPBconst: return rewriteValueAMD64_OpAMD64CMPBconst_0(v) case OpAMD64CMPBconstload: return rewriteValueAMD64_OpAMD64CMPBconstload_0(v) case OpAMD64CMPBload: return rewriteValueAMD64_OpAMD64CMPBload_0(v) case OpAMD64CMPL: return rewriteValueAMD64_OpAMD64CMPL_0(v) case OpAMD64CMPLconst: return rewriteValueAMD64_OpAMD64CMPLconst_0(v) || rewriteValueAMD64_OpAMD64CMPLconst_10(v) case OpAMD64CMPLconstload: return rewriteValueAMD64_OpAMD64CMPLconstload_0(v) case OpAMD64CMPLload: return rewriteValueAMD64_OpAMD64CMPLload_0(v) case OpAMD64CMPQ: return rewriteValueAMD64_OpAMD64CMPQ_0(v) case OpAMD64CMPQconst: return rewriteValueAMD64_OpAMD64CMPQconst_0(v) || rewriteValueAMD64_OpAMD64CMPQconst_10(v) case OpAMD64CMPQconstload: return rewriteValueAMD64_OpAMD64CMPQconstload_0(v) case OpAMD64CMPQload: return rewriteValueAMD64_OpAMD64CMPQload_0(v) case OpAMD64CMPW: return rewriteValueAMD64_OpAMD64CMPW_0(v) case OpAMD64CMPWconst: return rewriteValueAMD64_OpAMD64CMPWconst_0(v) case OpAMD64CMPWconstload: return rewriteValueAMD64_OpAMD64CMPWconstload_0(v) case OpAMD64CMPWload: return rewriteValueAMD64_OpAMD64CMPWload_0(v) case OpAMD64CMPXCHGLlock: return rewriteValueAMD64_OpAMD64CMPXCHGLlock_0(v) case OpAMD64CMPXCHGQlock: return rewriteValueAMD64_OpAMD64CMPXCHGQlock_0(v) case OpAMD64DIVSD: return rewriteValueAMD64_OpAMD64DIVSD_0(v) case OpAMD64DIVSDload: return rewriteValueAMD64_OpAMD64DIVSDload_0(v) case OpAMD64DIVSS: return rewriteValueAMD64_OpAMD64DIVSS_0(v) case OpAMD64DIVSSload: return rewriteValueAMD64_OpAMD64DIVSSload_0(v) case OpAMD64HMULL: return rewriteValueAMD64_OpAMD64HMULL_0(v) case OpAMD64HMULLU: return rewriteValueAMD64_OpAMD64HMULLU_0(v) case OpAMD64HMULQ: return rewriteValueAMD64_OpAMD64HMULQ_0(v) case OpAMD64HMULQU: return rewriteValueAMD64_OpAMD64HMULQU_0(v) case OpAMD64LEAL: return rewriteValueAMD64_OpAMD64LEAL_0(v) case OpAMD64LEAL1: return rewriteValueAMD64_OpAMD64LEAL1_0(v) case OpAMD64LEAL2: return rewriteValueAMD64_OpAMD64LEAL2_0(v) case OpAMD64LEAL4: return rewriteValueAMD64_OpAMD64LEAL4_0(v) case OpAMD64LEAL8: return rewriteValueAMD64_OpAMD64LEAL8_0(v) case OpAMD64LEAQ: return rewriteValueAMD64_OpAMD64LEAQ_0(v) case OpAMD64LEAQ1: return rewriteValueAMD64_OpAMD64LEAQ1_0(v) case OpAMD64LEAQ2: return rewriteValueAMD64_OpAMD64LEAQ2_0(v) case OpAMD64LEAQ4: return rewriteValueAMD64_OpAMD64LEAQ4_0(v) case OpAMD64LEAQ8: return rewriteValueAMD64_OpAMD64LEAQ8_0(v) case OpAMD64MOVBQSX: return rewriteValueAMD64_OpAMD64MOVBQSX_0(v) case OpAMD64MOVBQSXload: return rewriteValueAMD64_OpAMD64MOVBQSXload_0(v) case OpAMD64MOVBQZX: return rewriteValueAMD64_OpAMD64MOVBQZX_0(v) case OpAMD64MOVBatomicload: return rewriteValueAMD64_OpAMD64MOVBatomicload_0(v) case OpAMD64MOVBload: return rewriteValueAMD64_OpAMD64MOVBload_0(v) case OpAMD64MOVBloadidx1: return rewriteValueAMD64_OpAMD64MOVBloadidx1_0(v) case OpAMD64MOVBstore: return rewriteValueAMD64_OpAMD64MOVBstore_0(v) || rewriteValueAMD64_OpAMD64MOVBstore_10(v) || rewriteValueAMD64_OpAMD64MOVBstore_20(v) || rewriteValueAMD64_OpAMD64MOVBstore_30(v) case OpAMD64MOVBstoreconst: return rewriteValueAMD64_OpAMD64MOVBstoreconst_0(v) case OpAMD64MOVBstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVBstoreconstidx1_0(v) case OpAMD64MOVBstoreidx1: return rewriteValueAMD64_OpAMD64MOVBstoreidx1_0(v) || rewriteValueAMD64_OpAMD64MOVBstoreidx1_10(v) case OpAMD64MOVLQSX: return rewriteValueAMD64_OpAMD64MOVLQSX_0(v) case OpAMD64MOVLQSXload: return rewriteValueAMD64_OpAMD64MOVLQSXload_0(v) case OpAMD64MOVLQZX: return rewriteValueAMD64_OpAMD64MOVLQZX_0(v) case OpAMD64MOVLatomicload: return rewriteValueAMD64_OpAMD64MOVLatomicload_0(v) case OpAMD64MOVLf2i: return rewriteValueAMD64_OpAMD64MOVLf2i_0(v) case OpAMD64MOVLi2f: return rewriteValueAMD64_OpAMD64MOVLi2f_0(v) case OpAMD64MOVLload: return rewriteValueAMD64_OpAMD64MOVLload_0(v) || rewriteValueAMD64_OpAMD64MOVLload_10(v) case OpAMD64MOVLloadidx1: return rewriteValueAMD64_OpAMD64MOVLloadidx1_0(v) case OpAMD64MOVLloadidx4: return rewriteValueAMD64_OpAMD64MOVLloadidx4_0(v) case OpAMD64MOVLloadidx8: return rewriteValueAMD64_OpAMD64MOVLloadidx8_0(v) case OpAMD64MOVLstore: return rewriteValueAMD64_OpAMD64MOVLstore_0(v) || rewriteValueAMD64_OpAMD64MOVLstore_10(v) || rewriteValueAMD64_OpAMD64MOVLstore_20(v) || rewriteValueAMD64_OpAMD64MOVLstore_30(v) case OpAMD64MOVLstoreconst: return rewriteValueAMD64_OpAMD64MOVLstoreconst_0(v) case OpAMD64MOVLstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVLstoreconstidx1_0(v) case OpAMD64MOVLstoreconstidx4: return rewriteValueAMD64_OpAMD64MOVLstoreconstidx4_0(v) case OpAMD64MOVLstoreidx1: return rewriteValueAMD64_OpAMD64MOVLstoreidx1_0(v) case OpAMD64MOVLstoreidx4: return rewriteValueAMD64_OpAMD64MOVLstoreidx4_0(v) case OpAMD64MOVLstoreidx8: return rewriteValueAMD64_OpAMD64MOVLstoreidx8_0(v) case OpAMD64MOVOload: return rewriteValueAMD64_OpAMD64MOVOload_0(v) case OpAMD64MOVOstore: return rewriteValueAMD64_OpAMD64MOVOstore_0(v) case OpAMD64MOVQatomicload: return rewriteValueAMD64_OpAMD64MOVQatomicload_0(v) case OpAMD64MOVQf2i: return rewriteValueAMD64_OpAMD64MOVQf2i_0(v) case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f_0(v) case OpAMD64MOVQload: return rewriteValueAMD64_OpAMD64MOVQload_0(v) case OpAMD64MOVQloadidx1: return rewriteValueAMD64_OpAMD64MOVQloadidx1_0(v) case OpAMD64MOVQloadidx8: return rewriteValueAMD64_OpAMD64MOVQloadidx8_0(v) case OpAMD64MOVQstore: return rewriteValueAMD64_OpAMD64MOVQstore_0(v) || rewriteValueAMD64_OpAMD64MOVQstore_10(v) || rewriteValueAMD64_OpAMD64MOVQstore_20(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst_0(v) case OpAMD64MOVQstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVQstoreconstidx1_0(v) case OpAMD64MOVQstoreconstidx8: return rewriteValueAMD64_OpAMD64MOVQstoreconstidx8_0(v) case OpAMD64MOVQstoreidx1: return rewriteValueAMD64_OpAMD64MOVQstoreidx1_0(v) case OpAMD64MOVQstoreidx8: return rewriteValueAMD64_OpAMD64MOVQstoreidx8_0(v) case OpAMD64MOVSDload: return rewriteValueAMD64_OpAMD64MOVSDload_0(v) case OpAMD64MOVSDloadidx1: return rewriteValueAMD64_OpAMD64MOVSDloadidx1_0(v) case OpAMD64MOVSDloadidx8: return rewriteValueAMD64_OpAMD64MOVSDloadidx8_0(v) case OpAMD64MOVSDstore: return rewriteValueAMD64_OpAMD64MOVSDstore_0(v) case OpAMD64MOVSDstoreidx1: return rewriteValueAMD64_OpAMD64MOVSDstoreidx1_0(v) case OpAMD64MOVSDstoreidx8: return rewriteValueAMD64_OpAMD64MOVSDstoreidx8_0(v) case OpAMD64MOVSSload: return rewriteValueAMD64_OpAMD64MOVSSload_0(v) case OpAMD64MOVSSloadidx1: return rewriteValueAMD64_OpAMD64MOVSSloadidx1_0(v) case OpAMD64MOVSSloadidx4: return rewriteValueAMD64_OpAMD64MOVSSloadidx4_0(v) case OpAMD64MOVSSstore: return rewriteValueAMD64_OpAMD64MOVSSstore_0(v) case OpAMD64MOVSSstoreidx1: return rewriteValueAMD64_OpAMD64MOVSSstoreidx1_0(v) case OpAMD64MOVSSstoreidx4: return rewriteValueAMD64_OpAMD64MOVSSstoreidx4_0(v) case OpAMD64MOVWQSX: return rewriteValueAMD64_OpAMD64MOVWQSX_0(v) case OpAMD64MOVWQSXload: return rewriteValueAMD64_OpAMD64MOVWQSXload_0(v) case OpAMD64MOVWQZX: return rewriteValueAMD64_OpAMD64MOVWQZX_0(v) case OpAMD64MOVWload: return rewriteValueAMD64_OpAMD64MOVWload_0(v) case OpAMD64MOVWloadidx1: return rewriteValueAMD64_OpAMD64MOVWloadidx1_0(v) case OpAMD64MOVWloadidx2: return rewriteValueAMD64_OpAMD64MOVWloadidx2_0(v) case OpAMD64MOVWstore: return rewriteValueAMD64_OpAMD64MOVWstore_0(v) || rewriteValueAMD64_OpAMD64MOVWstore_10(v) case OpAMD64MOVWstoreconst: return rewriteValueAMD64_OpAMD64MOVWstoreconst_0(v) case OpAMD64MOVWstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVWstoreconstidx1_0(v) case OpAMD64MOVWstoreconstidx2: return rewriteValueAMD64_OpAMD64MOVWstoreconstidx2_0(v) case OpAMD64MOVWstoreidx1: return rewriteValueAMD64_OpAMD64MOVWstoreidx1_0(v) case OpAMD64MOVWstoreidx2: return rewriteValueAMD64_OpAMD64MOVWstoreidx2_0(v) case OpAMD64MULL: return rewriteValueAMD64_OpAMD64MULL_0(v) case OpAMD64MULLconst: return rewriteValueAMD64_OpAMD64MULLconst_0(v) || rewriteValueAMD64_OpAMD64MULLconst_10(v) || rewriteValueAMD64_OpAMD64MULLconst_20(v) || rewriteValueAMD64_OpAMD64MULLconst_30(v) case OpAMD64MULQ: return rewriteValueAMD64_OpAMD64MULQ_0(v) case OpAMD64MULQconst: return rewriteValueAMD64_OpAMD64MULQconst_0(v) || rewriteValueAMD64_OpAMD64MULQconst_10(v) || rewriteValueAMD64_OpAMD64MULQconst_20(v) || rewriteValueAMD64_OpAMD64MULQconst_30(v) case OpAMD64MULSD: return rewriteValueAMD64_OpAMD64MULSD_0(v) case OpAMD64MULSDload: return rewriteValueAMD64_OpAMD64MULSDload_0(v) case OpAMD64MULSS: return rewriteValueAMD64_OpAMD64MULSS_0(v) case OpAMD64MULSSload: return rewriteValueAMD64_OpAMD64MULSSload_0(v) case OpAMD64NEGL: return rewriteValueAMD64_OpAMD64NEGL_0(v) case OpAMD64NEGQ: return rewriteValueAMD64_OpAMD64NEGQ_0(v) case OpAMD64NOTL: return rewriteValueAMD64_OpAMD64NOTL_0(v) case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ_0(v) case OpAMD64ORL: return rewriteValueAMD64_OpAMD64ORL_0(v) || rewriteValueAMD64_OpAMD64ORL_10(v) || rewriteValueAMD64_OpAMD64ORL_20(v) || rewriteValueAMD64_OpAMD64ORL_30(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst_0(v) case OpAMD64ORLconstmodify: return rewriteValueAMD64_OpAMD64ORLconstmodify_0(v) case OpAMD64ORLload: return rewriteValueAMD64_OpAMD64ORLload_0(v) case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify_0(v) case OpAMD64ORQ: return rewriteValueAMD64_OpAMD64ORQ_0(v) || rewriteValueAMD64_OpAMD64ORQ_10(v) || rewriteValueAMD64_OpAMD64ORQ_20(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst_0(v) case OpAMD64ORQconstmodify: return rewriteValueAMD64_OpAMD64ORQconstmodify_0(v) case OpAMD64ORQload: return rewriteValueAMD64_OpAMD64ORQload_0(v) case OpAMD64ORQmodify: return rewriteValueAMD64_OpAMD64ORQmodify_0(v) case OpAMD64ROLB: return rewriteValueAMD64_OpAMD64ROLB_0(v) case OpAMD64ROLBconst: return rewriteValueAMD64_OpAMD64ROLBconst_0(v) case OpAMD64ROLL: return rewriteValueAMD64_OpAMD64ROLL_0(v) case OpAMD64ROLLconst: return rewriteValueAMD64_OpAMD64ROLLconst_0(v) case OpAMD64ROLQ: return rewriteValueAMD64_OpAMD64ROLQ_0(v) case OpAMD64ROLQconst: return rewriteValueAMD64_OpAMD64ROLQconst_0(v) case OpAMD64ROLW: return rewriteValueAMD64_OpAMD64ROLW_0(v) case OpAMD64ROLWconst: return rewriteValueAMD64_OpAMD64ROLWconst_0(v) case OpAMD64RORB: return rewriteValueAMD64_OpAMD64RORB_0(v) case OpAMD64RORL: return rewriteValueAMD64_OpAMD64RORL_0(v) case OpAMD64RORQ: return rewriteValueAMD64_OpAMD64RORQ_0(v) case OpAMD64RORW: return rewriteValueAMD64_OpAMD64RORW_0(v) case OpAMD64SARB: return rewriteValueAMD64_OpAMD64SARB_0(v) case OpAMD64SARBconst: return rewriteValueAMD64_OpAMD64SARBconst_0(v) case OpAMD64SARL: return rewriteValueAMD64_OpAMD64SARL_0(v) case OpAMD64SARLconst: return rewriteValueAMD64_OpAMD64SARLconst_0(v) case OpAMD64SARQ: return rewriteValueAMD64_OpAMD64SARQ_0(v) case OpAMD64SARQconst: return rewriteValueAMD64_OpAMD64SARQconst_0(v) case OpAMD64SARW: return rewriteValueAMD64_OpAMD64SARW_0(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst_0(v) case OpAMD64SBBLcarrymask: return rewriteValueAMD64_OpAMD64SBBLcarrymask_0(v) case OpAMD64SBBQ: return rewriteValueAMD64_OpAMD64SBBQ_0(v) case OpAMD64SBBQcarrymask: return rewriteValueAMD64_OpAMD64SBBQcarrymask_0(v) case OpAMD64SBBQconst: return rewriteValueAMD64_OpAMD64SBBQconst_0(v) case OpAMD64SETA: return rewriteValueAMD64_OpAMD64SETA_0(v) case OpAMD64SETAE: return rewriteValueAMD64_OpAMD64SETAE_0(v) case OpAMD64SETAEstore: return rewriteValueAMD64_OpAMD64SETAEstore_0(v) case OpAMD64SETAstore: return rewriteValueAMD64_OpAMD64SETAstore_0(v) case OpAMD64SETB: return rewriteValueAMD64_OpAMD64SETB_0(v) case OpAMD64SETBE: return rewriteValueAMD64_OpAMD64SETBE_0(v) case OpAMD64SETBEstore: return rewriteValueAMD64_OpAMD64SETBEstore_0(v) case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore_0(v) case OpAMD64SETEQ: return rewriteValueAMD64_OpAMD64SETEQ_0(v) || rewriteValueAMD64_OpAMD64SETEQ_10(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore_0(v) || rewriteValueAMD64_OpAMD64SETEQstore_10(v) || rewriteValueAMD64_OpAMD64SETEQstore_20(v) case OpAMD64SETG: return rewriteValueAMD64_OpAMD64SETG_0(v) case OpAMD64SETGE: return rewriteValueAMD64_OpAMD64SETGE_0(v) case OpAMD64SETGEstore: return rewriteValueAMD64_OpAMD64SETGEstore_0(v) case OpAMD64SETGstore: return rewriteValueAMD64_OpAMD64SETGstore_0(v) case OpAMD64SETL: return rewriteValueAMD64_OpAMD64SETL_0(v) case OpAMD64SETLE: return rewriteValueAMD64_OpAMD64SETLE_0(v) case OpAMD64SETLEstore: return rewriteValueAMD64_OpAMD64SETLEstore_0(v) case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore_0(v) case OpAMD64SETNE: return rewriteValueAMD64_OpAMD64SETNE_0(v) || rewriteValueAMD64_OpAMD64SETNE_10(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore_0(v) || rewriteValueAMD64_OpAMD64SETNEstore_10(v) || rewriteValueAMD64_OpAMD64SETNEstore_20(v) case OpAMD64SHLL: return rewriteValueAMD64_OpAMD64SHLL_0(v) case OpAMD64SHLLconst: return rewriteValueAMD64_OpAMD64SHLLconst_0(v) case OpAMD64SHLQ: return rewriteValueAMD64_OpAMD64SHLQ_0(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst_0(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB_0(v) case OpAMD64SHRBconst: return rewriteValueAMD64_OpAMD64SHRBconst_0(v) case OpAMD64SHRL: return rewriteValueAMD64_OpAMD64SHRL_0(v) case OpAMD64SHRLconst: return rewriteValueAMD64_OpAMD64SHRLconst_0(v) case OpAMD64SHRQ: return rewriteValueAMD64_OpAMD64SHRQ_0(v) case OpAMD64SHRQconst: return rewriteValueAMD64_OpAMD64SHRQconst_0(v) case OpAMD64SHRW: return rewriteValueAMD64_OpAMD64SHRW_0(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst_0(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL_0(v) case OpAMD64SUBLconst: return rewriteValueAMD64_OpAMD64SUBLconst_0(v) case OpAMD64SUBLload: return rewriteValueAMD64_OpAMD64SUBLload_0(v) case OpAMD64SUBLmodify: return rewriteValueAMD64_OpAMD64SUBLmodify_0(v) case OpAMD64SUBQ: return rewriteValueAMD64_OpAMD64SUBQ_0(v) case OpAMD64SUBQborrow: return rewriteValueAMD64_OpAMD64SUBQborrow_0(v) case OpAMD64SUBQconst: return rewriteValueAMD64_OpAMD64SUBQconst_0(v) case OpAMD64SUBQload: return rewriteValueAMD64_OpAMD64SUBQload_0(v) case OpAMD64SUBQmodify: return rewriteValueAMD64_OpAMD64SUBQmodify_0(v) case OpAMD64SUBSD: return rewriteValueAMD64_OpAMD64SUBSD_0(v) case OpAMD64SUBSDload: return rewriteValueAMD64_OpAMD64SUBSDload_0(v) case OpAMD64SUBSS: return rewriteValueAMD64_OpAMD64SUBSS_0(v) case OpAMD64SUBSSload: return rewriteValueAMD64_OpAMD64SUBSSload_0(v) case OpAMD64TESTB: return rewriteValueAMD64_OpAMD64TESTB_0(v) case OpAMD64TESTBconst: return rewriteValueAMD64_OpAMD64TESTBconst_0(v) case OpAMD64TESTL: return rewriteValueAMD64_OpAMD64TESTL_0(v) case OpAMD64TESTLconst: return rewriteValueAMD64_OpAMD64TESTLconst_0(v) case OpAMD64TESTQ: return rewriteValueAMD64_OpAMD64TESTQ_0(v) case OpAMD64TESTQconst: return rewriteValueAMD64_OpAMD64TESTQconst_0(v) case OpAMD64TESTW: return rewriteValueAMD64_OpAMD64TESTW_0(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst_0(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock_0(v) case OpAMD64XADDQlock: return rewriteValueAMD64_OpAMD64XADDQlock_0(v) case OpAMD64XCHGL: return rewriteValueAMD64_OpAMD64XCHGL_0(v) case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ_0(v) case OpAMD64XORL: return rewriteValueAMD64_OpAMD64XORL_0(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst_0(v) || rewriteValueAMD64_OpAMD64XORLconst_10(v) case OpAMD64XORLconstmodify: return rewriteValueAMD64_OpAMD64XORLconstmodify_0(v) case OpAMD64XORLload: return rewriteValueAMD64_OpAMD64XORLload_0(v) case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify_0(v) case OpAMD64XORQ: return rewriteValueAMD64_OpAMD64XORQ_0(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst_0(v) case OpAMD64XORQconstmodify: return rewriteValueAMD64_OpAMD64XORQconstmodify_0(v) case OpAMD64XORQload: return rewriteValueAMD64_OpAMD64XORQload_0(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify_0(v) case OpAdd16: return rewriteValueAMD64_OpAdd16_0(v) case OpAdd32: return rewriteValueAMD64_OpAdd32_0(v) case OpAdd32F: return rewriteValueAMD64_OpAdd32F_0(v) case OpAdd64: return rewriteValueAMD64_OpAdd64_0(v) case OpAdd64F: return rewriteValueAMD64_OpAdd64F_0(v) case OpAdd8: return rewriteValueAMD64_OpAdd8_0(v) case OpAddPtr: return rewriteValueAMD64_OpAddPtr_0(v) case OpAddr: return rewriteValueAMD64_OpAddr_0(v) case OpAnd16: return rewriteValueAMD64_OpAnd16_0(v) case OpAnd32: return rewriteValueAMD64_OpAnd32_0(v) case OpAnd64: return rewriteValueAMD64_OpAnd64_0(v) case OpAnd8: return rewriteValueAMD64_OpAnd8_0(v) case OpAndB: return rewriteValueAMD64_OpAndB_0(v) case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32_0(v) case OpAtomicAdd64: return rewriteValueAMD64_OpAtomicAdd64_0(v) case OpAtomicAnd8: return rewriteValueAMD64_OpAtomicAnd8_0(v) case OpAtomicCompareAndSwap32: return rewriteValueAMD64_OpAtomicCompareAndSwap32_0(v) case OpAtomicCompareAndSwap64: return rewriteValueAMD64_OpAtomicCompareAndSwap64_0(v) case OpAtomicExchange32: return rewriteValueAMD64_OpAtomicExchange32_0(v) case OpAtomicExchange64: return rewriteValueAMD64_OpAtomicExchange64_0(v) case OpAtomicLoad32: return rewriteValueAMD64_OpAtomicLoad32_0(v) case OpAtomicLoad64: return rewriteValueAMD64_OpAtomicLoad64_0(v) case OpAtomicLoad8: return rewriteValueAMD64_OpAtomicLoad8_0(v) case OpAtomicLoadPtr: return rewriteValueAMD64_OpAtomicLoadPtr_0(v) case OpAtomicOr8: return rewriteValueAMD64_OpAtomicOr8_0(v) case OpAtomicStore32: return rewriteValueAMD64_OpAtomicStore32_0(v) case OpAtomicStore64: return rewriteValueAMD64_OpAtomicStore64_0(v) case OpAtomicStore8: return rewriteValueAMD64_OpAtomicStore8_0(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB_0(v) case OpAvg64u: return rewriteValueAMD64_OpAvg64u_0(v) case OpBitLen16: return rewriteValueAMD64_OpBitLen16_0(v) case OpBitLen32: return rewriteValueAMD64_OpBitLen32_0(v) case OpBitLen64: return rewriteValueAMD64_OpBitLen64_0(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8_0(v) case OpBswap32: return rewriteValueAMD64_OpBswap32_0(v) case OpBswap64: return rewriteValueAMD64_OpBswap64_0(v) case OpCeil: return rewriteValueAMD64_OpCeil_0(v) case OpClosureCall: return rewriteValueAMD64_OpClosureCall_0(v) case OpCom16: return rewriteValueAMD64_OpCom16_0(v) case OpCom32: return rewriteValueAMD64_OpCom32_0(v) case OpCom64: return rewriteValueAMD64_OpCom64_0(v) case OpCom8: return rewriteValueAMD64_OpCom8_0(v) case OpCondSelect: return rewriteValueAMD64_OpCondSelect_0(v) || rewriteValueAMD64_OpCondSelect_10(v) || rewriteValueAMD64_OpCondSelect_20(v) || rewriteValueAMD64_OpCondSelect_30(v) || rewriteValueAMD64_OpCondSelect_40(v) case OpConst16: return rewriteValueAMD64_OpConst16_0(v) case OpConst32: return rewriteValueAMD64_OpConst32_0(v) case OpConst32F: return rewriteValueAMD64_OpConst32F_0(v) case OpConst64: return rewriteValueAMD64_OpConst64_0(v) case OpConst64F: return rewriteValueAMD64_OpConst64F_0(v) case OpConst8: return rewriteValueAMD64_OpConst8_0(v) case OpConstBool: return rewriteValueAMD64_OpConstBool_0(v) case OpConstNil: return rewriteValueAMD64_OpConstNil_0(v) case OpCtz16: return rewriteValueAMD64_OpCtz16_0(v) case OpCtz16NonZero: return rewriteValueAMD64_OpCtz16NonZero_0(v) case OpCtz32: return rewriteValueAMD64_OpCtz32_0(v) case OpCtz32NonZero: return rewriteValueAMD64_OpCtz32NonZero_0(v) case OpCtz64: return rewriteValueAMD64_OpCtz64_0(v) case OpCtz64NonZero: return rewriteValueAMD64_OpCtz64NonZero_0(v) case OpCtz8: return rewriteValueAMD64_OpCtz8_0(v) case OpCtz8NonZero: return rewriteValueAMD64_OpCtz8NonZero_0(v) case OpCvt32Fto32: return rewriteValueAMD64_OpCvt32Fto32_0(v) case OpCvt32Fto64: return rewriteValueAMD64_OpCvt32Fto64_0(v) case OpCvt32Fto64F: return rewriteValueAMD64_OpCvt32Fto64F_0(v) case OpCvt32to32F: return rewriteValueAMD64_OpCvt32to32F_0(v) case OpCvt32to64F: return rewriteValueAMD64_OpCvt32to64F_0(v) case OpCvt64Fto32: return rewriteValueAMD64_OpCvt64Fto32_0(v) case OpCvt64Fto32F: return rewriteValueAMD64_OpCvt64Fto32F_0(v) case OpCvt64Fto64: return rewriteValueAMD64_OpCvt64Fto64_0(v) case OpCvt64to32F: return rewriteValueAMD64_OpCvt64to32F_0(v) case OpCvt64to64F: return rewriteValueAMD64_OpCvt64to64F_0(v) case OpDiv128u: return rewriteValueAMD64_OpDiv128u_0(v) case OpDiv16: return rewriteValueAMD64_OpDiv16_0(v) case OpDiv16u: return rewriteValueAMD64_OpDiv16u_0(v) case OpDiv32: return rewriteValueAMD64_OpDiv32_0(v) case OpDiv32F: return rewriteValueAMD64_OpDiv32F_0(v) case OpDiv32u: return rewriteValueAMD64_OpDiv32u_0(v) case OpDiv64: return rewriteValueAMD64_OpDiv64_0(v) case OpDiv64F: return rewriteValueAMD64_OpDiv64F_0(v) case OpDiv64u: return rewriteValueAMD64_OpDiv64u_0(v) case OpDiv8: return rewriteValueAMD64_OpDiv8_0(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u_0(v) case OpEq16: return rewriteValueAMD64_OpEq16_0(v) case OpEq32: return rewriteValueAMD64_OpEq32_0(v) case OpEq32F: return rewriteValueAMD64_OpEq32F_0(v) case OpEq64: return rewriteValueAMD64_OpEq64_0(v) case OpEq64F: return rewriteValueAMD64_OpEq64F_0(v) case OpEq8: return rewriteValueAMD64_OpEq8_0(v) case OpEqB: return rewriteValueAMD64_OpEqB_0(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr_0(v) case OpFMA: return rewriteValueAMD64_OpFMA_0(v) case OpFloor: return rewriteValueAMD64_OpFloor_0(v) case OpGeq16: return rewriteValueAMD64_OpGeq16_0(v) case OpGeq16U: return rewriteValueAMD64_OpGeq16U_0(v) case OpGeq32: return rewriteValueAMD64_OpGeq32_0(v) case OpGeq32F: return rewriteValueAMD64_OpGeq32F_0(v) case OpGeq32U: return rewriteValueAMD64_OpGeq32U_0(v) case OpGeq64: return rewriteValueAMD64_OpGeq64_0(v) case OpGeq64F: return rewriteValueAMD64_OpGeq64F_0(v) case OpGeq64U: return rewriteValueAMD64_OpGeq64U_0(v) case OpGeq8: return rewriteValueAMD64_OpGeq8_0(v) case OpGeq8U: return rewriteValueAMD64_OpGeq8U_0(v) case OpGetCallerPC: return rewriteValueAMD64_OpGetCallerPC_0(v) case OpGetCallerSP: return rewriteValueAMD64_OpGetCallerSP_0(v) case OpGetClosurePtr: return rewriteValueAMD64_OpGetClosurePtr_0(v) case OpGetG: return rewriteValueAMD64_OpGetG_0(v) case OpGreater16: return rewriteValueAMD64_OpGreater16_0(v) case OpGreater16U: return rewriteValueAMD64_OpGreater16U_0(v) case OpGreater32: return rewriteValueAMD64_OpGreater32_0(v) case OpGreater32F: return rewriteValueAMD64_OpGreater32F_0(v) case OpGreater32U: return rewriteValueAMD64_OpGreater32U_0(v) case OpGreater64: return rewriteValueAMD64_OpGreater64_0(v) case OpGreater64F: return rewriteValueAMD64_OpGreater64F_0(v) case OpGreater64U: return rewriteValueAMD64_OpGreater64U_0(v) case OpGreater8: return rewriteValueAMD64_OpGreater8_0(v) case OpGreater8U: return rewriteValueAMD64_OpGreater8U_0(v) case OpHmul32: return rewriteValueAMD64_OpHmul32_0(v) case OpHmul32u: return rewriteValueAMD64_OpHmul32u_0(v) case OpHmul64: return rewriteValueAMD64_OpHmul64_0(v) case OpHmul64u: return rewriteValueAMD64_OpHmul64u_0(v) case OpInterCall: return rewriteValueAMD64_OpInterCall_0(v) case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds_0(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil_0(v) case OpIsSliceInBounds: return rewriteValueAMD64_OpIsSliceInBounds_0(v) case OpLeq16: return rewriteValueAMD64_OpLeq16_0(v) case OpLeq16U: return rewriteValueAMD64_OpLeq16U_0(v) case OpLeq32: return rewriteValueAMD64_OpLeq32_0(v) case OpLeq32F: return rewriteValueAMD64_OpLeq32F_0(v) case OpLeq32U: return rewriteValueAMD64_OpLeq32U_0(v) case OpLeq64: return rewriteValueAMD64_OpLeq64_0(v) case OpLeq64F: return rewriteValueAMD64_OpLeq64F_0(v) case OpLeq64U: return rewriteValueAMD64_OpLeq64U_0(v) case OpLeq8: return rewriteValueAMD64_OpLeq8_0(v) case OpLeq8U: return rewriteValueAMD64_OpLeq8U_0(v) case OpLess16: return rewriteValueAMD64_OpLess16_0(v) case OpLess16U: return rewriteValueAMD64_OpLess16U_0(v) case OpLess32: return rewriteValueAMD64_OpLess32_0(v) case OpLess32F: return rewriteValueAMD64_OpLess32F_0(v) case OpLess32U: return rewriteValueAMD64_OpLess32U_0(v) case OpLess64: return rewriteValueAMD64_OpLess64_0(v) case OpLess64F: return rewriteValueAMD64_OpLess64F_0(v) case OpLess64U: return rewriteValueAMD64_OpLess64U_0(v) case OpLess8: return rewriteValueAMD64_OpLess8_0(v) case OpLess8U: return rewriteValueAMD64_OpLess8U_0(v) case OpLoad: return rewriteValueAMD64_OpLoad_0(v) case OpLocalAddr: return rewriteValueAMD64_OpLocalAddr_0(v) case OpLsh16x16: return rewriteValueAMD64_OpLsh16x16_0(v) case OpLsh16x32: return rewriteValueAMD64_OpLsh16x32_0(v) case OpLsh16x64: return rewriteValueAMD64_OpLsh16x64_0(v) case OpLsh16x8: return rewriteValueAMD64_OpLsh16x8_0(v) case OpLsh32x16: return rewriteValueAMD64_OpLsh32x16_0(v) case OpLsh32x32: return rewriteValueAMD64_OpLsh32x32_0(v) case OpLsh32x64: return rewriteValueAMD64_OpLsh32x64_0(v) case OpLsh32x8: return rewriteValueAMD64_OpLsh32x8_0(v) case OpLsh64x16: return rewriteValueAMD64_OpLsh64x16_0(v) case OpLsh64x32: return rewriteValueAMD64_OpLsh64x32_0(v) case OpLsh64x64: return rewriteValueAMD64_OpLsh64x64_0(v) case OpLsh64x8: return rewriteValueAMD64_OpLsh64x8_0(v) case OpLsh8x16: return rewriteValueAMD64_OpLsh8x16_0(v) case OpLsh8x32: return rewriteValueAMD64_OpLsh8x32_0(v) case OpLsh8x64: return rewriteValueAMD64_OpLsh8x64_0(v) case OpLsh8x8: return rewriteValueAMD64_OpLsh8x8_0(v) case OpMod16: return rewriteValueAMD64_OpMod16_0(v) case OpMod16u: return rewriteValueAMD64_OpMod16u_0(v) case OpMod32: return rewriteValueAMD64_OpMod32_0(v) case OpMod32u: return rewriteValueAMD64_OpMod32u_0(v) case OpMod64: return rewriteValueAMD64_OpMod64_0(v) case OpMod64u: return rewriteValueAMD64_OpMod64u_0(v) case OpMod8: return rewriteValueAMD64_OpMod8_0(v) case OpMod8u: return rewriteValueAMD64_OpMod8u_0(v) case OpMove: return rewriteValueAMD64_OpMove_0(v) || rewriteValueAMD64_OpMove_10(v) || rewriteValueAMD64_OpMove_20(v) case OpMul16: return rewriteValueAMD64_OpMul16_0(v) case OpMul32: return rewriteValueAMD64_OpMul32_0(v) case OpMul32F: return rewriteValueAMD64_OpMul32F_0(v) case OpMul64: return rewriteValueAMD64_OpMul64_0(v) case OpMul64F: return rewriteValueAMD64_OpMul64F_0(v) case OpMul64uhilo: return rewriteValueAMD64_OpMul64uhilo_0(v) case OpMul8: return rewriteValueAMD64_OpMul8_0(v) case OpNeg16: return rewriteValueAMD64_OpNeg16_0(v) case OpNeg32: return rewriteValueAMD64_OpNeg32_0(v) case OpNeg32F: return rewriteValueAMD64_OpNeg32F_0(v) case OpNeg64: return rewriteValueAMD64_OpNeg64_0(v) case OpNeg64F: return rewriteValueAMD64_OpNeg64F_0(v) case OpNeg8: return rewriteValueAMD64_OpNeg8_0(v) case OpNeq16: return rewriteValueAMD64_OpNeq16_0(v) case OpNeq32: return rewriteValueAMD64_OpNeq32_0(v) case OpNeq32F: return rewriteValueAMD64_OpNeq32F_0(v) case OpNeq64: return rewriteValueAMD64_OpNeq64_0(v) case OpNeq64F: return rewriteValueAMD64_OpNeq64F_0(v) case OpNeq8: return rewriteValueAMD64_OpNeq8_0(v) case OpNeqB: return rewriteValueAMD64_OpNeqB_0(v) case OpNeqPtr: return rewriteValueAMD64_OpNeqPtr_0(v) case OpNilCheck: return rewriteValueAMD64_OpNilCheck_0(v) case OpNot: return rewriteValueAMD64_OpNot_0(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr_0(v) case OpOr16: return rewriteValueAMD64_OpOr16_0(v) case OpOr32: return rewriteValueAMD64_OpOr32_0(v) case OpOr64: return rewriteValueAMD64_OpOr64_0(v) case OpOr8: return rewriteValueAMD64_OpOr8_0(v) case OpOrB: return rewriteValueAMD64_OpOrB_0(v) case OpPanicBounds: return rewriteValueAMD64_OpPanicBounds_0(v) case OpPopCount16: return rewriteValueAMD64_OpPopCount16_0(v) case OpPopCount32: return rewriteValueAMD64_OpPopCount32_0(v) case OpPopCount64: return rewriteValueAMD64_OpPopCount64_0(v) case OpPopCount8: return rewriteValueAMD64_OpPopCount8_0(v) case OpRotateLeft16: return rewriteValueAMD64_OpRotateLeft16_0(v) case OpRotateLeft32: return rewriteValueAMD64_OpRotateLeft32_0(v) case OpRotateLeft64: return rewriteValueAMD64_OpRotateLeft64_0(v) case OpRotateLeft8: return rewriteValueAMD64_OpRotateLeft8_0(v) case OpRound32F: return rewriteValueAMD64_OpRound32F_0(v) case OpRound64F: return rewriteValueAMD64_OpRound64F_0(v) case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven_0(v) case OpRsh16Ux16: return rewriteValueAMD64_OpRsh16Ux16_0(v) case OpRsh16Ux32: return rewriteValueAMD64_OpRsh16Ux32_0(v) case OpRsh16Ux64: return rewriteValueAMD64_OpRsh16Ux64_0(v) case OpRsh16Ux8: return rewriteValueAMD64_OpRsh16Ux8_0(v) case OpRsh16x16: return rewriteValueAMD64_OpRsh16x16_0(v) case OpRsh16x32: return rewriteValueAMD64_OpRsh16x32_0(v) case OpRsh16x64: return rewriteValueAMD64_OpRsh16x64_0(v) case OpRsh16x8: return rewriteValueAMD64_OpRsh16x8_0(v) case OpRsh32Ux16: return rewriteValueAMD64_OpRsh32Ux16_0(v) case OpRsh32Ux32: return rewriteValueAMD64_OpRsh32Ux32_0(v) case OpRsh32Ux64: return rewriteValueAMD64_OpRsh32Ux64_0(v) case OpRsh32Ux8: return rewriteValueAMD64_OpRsh32Ux8_0(v) case OpRsh32x16: return rewriteValueAMD64_OpRsh32x16_0(v) case OpRsh32x32: return rewriteValueAMD64_OpRsh32x32_0(v) case OpRsh32x64: return rewriteValueAMD64_OpRsh32x64_0(v) case OpRsh32x8: return rewriteValueAMD64_OpRsh32x8_0(v) case OpRsh64Ux16: return rewriteValueAMD64_OpRsh64Ux16_0(v) case OpRsh64Ux32: return rewriteValueAMD64_OpRsh64Ux32_0(v) case OpRsh64Ux64: return rewriteValueAMD64_OpRsh64Ux64_0(v) case OpRsh64Ux8: return rewriteValueAMD64_OpRsh64Ux8_0(v) case OpRsh64x16: return rewriteValueAMD64_OpRsh64x16_0(v) case OpRsh64x32: return rewriteValueAMD64_OpRsh64x32_0(v) case OpRsh64x64: return rewriteValueAMD64_OpRsh64x64_0(v) case OpRsh64x8: return rewriteValueAMD64_OpRsh64x8_0(v) case OpRsh8Ux16: return rewriteValueAMD64_OpRsh8Ux16_0(v) case OpRsh8Ux32: return rewriteValueAMD64_OpRsh8Ux32_0(v) case OpRsh8Ux64: return rewriteValueAMD64_OpRsh8Ux64_0(v) case OpRsh8Ux8: return rewriteValueAMD64_OpRsh8Ux8_0(v) case OpRsh8x16: return rewriteValueAMD64_OpRsh8x16_0(v) case OpRsh8x32: return rewriteValueAMD64_OpRsh8x32_0(v) case OpRsh8x64: return rewriteValueAMD64_OpRsh8x64_0(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8_0(v) case OpSelect0: return rewriteValueAMD64_OpSelect0_0(v) case OpSelect1: return rewriteValueAMD64_OpSelect1_0(v) case OpSignExt16to32: return rewriteValueAMD64_OpSignExt16to32_0(v) case OpSignExt16to64: return rewriteValueAMD64_OpSignExt16to64_0(v) case OpSignExt32to64: return rewriteValueAMD64_OpSignExt32to64_0(v) case OpSignExt8to16: return rewriteValueAMD64_OpSignExt8to16_0(v) case OpSignExt8to32: return rewriteValueAMD64_OpSignExt8to32_0(v) case OpSignExt8to64: return rewriteValueAMD64_OpSignExt8to64_0(v) case OpSlicemask: return rewriteValueAMD64_OpSlicemask_0(v) case OpSqrt: return rewriteValueAMD64_OpSqrt_0(v) case OpStaticCall: return rewriteValueAMD64_OpStaticCall_0(v) case OpStore: return rewriteValueAMD64_OpStore_0(v) case OpSub16: return rewriteValueAMD64_OpSub16_0(v) case OpSub32: return rewriteValueAMD64_OpSub32_0(v) case OpSub32F: return rewriteValueAMD64_OpSub32F_0(v) case OpSub64: return rewriteValueAMD64_OpSub64_0(v) case OpSub64F: return rewriteValueAMD64_OpSub64F_0(v) case OpSub8: return rewriteValueAMD64_OpSub8_0(v) case OpSubPtr: return rewriteValueAMD64_OpSubPtr_0(v) case OpTrunc: return rewriteValueAMD64_OpTrunc_0(v) case OpTrunc16to8: return rewriteValueAMD64_OpTrunc16to8_0(v) case OpTrunc32to16: return rewriteValueAMD64_OpTrunc32to16_0(v) case OpTrunc32to8: return rewriteValueAMD64_OpTrunc32to8_0(v) case OpTrunc64to16: return rewriteValueAMD64_OpTrunc64to16_0(v) case OpTrunc64to32: return rewriteValueAMD64_OpTrunc64to32_0(v) case OpTrunc64to8: return rewriteValueAMD64_OpTrunc64to8_0(v) case OpWB: return rewriteValueAMD64_OpWB_0(v) case OpXor16: return rewriteValueAMD64_OpXor16_0(v) case OpXor32: return rewriteValueAMD64_OpXor32_0(v) case OpXor64: return rewriteValueAMD64_OpXor64_0(v) case OpXor8: return rewriteValueAMD64_OpXor8_0(v) case OpZero: return rewriteValueAMD64_OpZero_0(v) || rewriteValueAMD64_OpZero_10(v) || rewriteValueAMD64_OpZero_20(v) case OpZeroExt16to32: return rewriteValueAMD64_OpZeroExt16to32_0(v) case OpZeroExt16to64: return rewriteValueAMD64_OpZeroExt16to64_0(v) case OpZeroExt32to64: return rewriteValueAMD64_OpZeroExt32to64_0(v) case OpZeroExt8to16: return rewriteValueAMD64_OpZeroExt8to16_0(v) case OpZeroExt8to32: return rewriteValueAMD64_OpZeroExt8to32_0(v) case OpZeroExt8to64: return rewriteValueAMD64_OpZeroExt8to64_0(v) } return false } func rewriteValueAMD64_OpAMD64ADCQ_0(v *Value) bool { // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) // result: (ADCQconst x [c] carry) for { carry := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64ADCQconst) v.AuxInt = c v.AddArg(x) v.AddArg(carry) return true } break } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) for { _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQcarry) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ADCQconst_0(v *Value) bool { // match: (ADCQconst x [c] (FlagEQ)) // result: (ADDQconstcarry x [c]) for { c := v.AuxInt _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL_0(v *Value) bool { // match: (ADDL x (MOVLconst [c])) // result: (ADDLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVLconst { continue } c := v_1.AuxInt v.reset(OpAMD64ADDLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRLconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRWconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRBconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDL { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { if x != v_1.Args[_i1] { continue } y := v_1.Args[1^_i1] v.reset(OpAMD64LEAL2) v.AddArg(y) v.AddArg(x) return true } } break } // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDLconst { continue } c := v_0.AuxInt x := v_0.Args[0] y := v.Args[1^_i0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDL_10(v *Value) bool { // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64LEAL { continue } c := v_1.AuxInt s := v_1.Aux y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64NEGL { continue } y := v_1.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVLload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDLconst_0(v *Value) bool { // match: (ADDLconst [c] (ADDL x y)) // result: (LEAL1 [c] x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (SHLLconst [1] x)) // result: (LEAL1 [c] x x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(c+d) // result: (LEAL [c+d] {s} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } d := v_0.AuxInt s := v_0.Aux x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL1 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL2 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL2 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL4 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL4 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL8 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL8 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] x) // cond: int32(c)==0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // result: (MOVLconst [int64(int32(c+d))]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = int64(int32(c + d)) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // result: (ADDLconst [int64(int32(c+d))] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int64(int32(c + d)) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconst_10(v *Value) bool { // match: (ADDLconst [off] x:(SP)) // result: (LEAL [off] x) for { off := v.AuxInt x := v.Args[0] if x.Op != OpSP { break } v.reset(OpAMD64LEAL) v.AuxInt = off v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconstmodify_0(v *Value) bool { // match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (ADDL x (MOVLf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSSstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDL) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDLmodify_0(v *Value) bool { // match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ_0(v *Value) bool { // match: (ADDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADDQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLQconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRQconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDQ { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDQ { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { if x != v_1.Args[_i1] { continue } y := v_1.Args[1^_i1] v.reset(OpAMD64LEAQ2) v.AddArg(y) v.AddArg(x) return true } } break } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDQconst { continue } c := v_0.AuxInt x := v_0.Args[0] y := v.Args[1^_i0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64LEAQ { continue } c := v_1.AuxInt s := v_1.Aux y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64NEGQ { continue } y := v_1.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQ_10(v *Value) bool { // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVQload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQcarry_0(v *Value) bool { // match: (ADDQcarry x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconstcarry x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = c v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQconst_0(v *Value) bool { // match: (ADDQconst [c] (ADDQ x y)) // result: (LEAQ1 [c] x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (SHLQconst [1] x)) // result: (LEAQ1 [c] x x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ [d] {s} x)) // cond: is32Bit(c+d) // result: (LEAQ [c+d] {s} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } d := v_0.AuxInt s := v_0.Aux x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ1 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ1 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (LEAQ2 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ2 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (LEAQ4 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ4 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (LEAQ8 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ8 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDQconst [c] (MOVQconst [d])) // result: (MOVQconst [c+d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = c + d return true } // match: (ADDQconst [c] (ADDQconst [d] x)) // cond: is32Bit(c+d) // result: (ADDQconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = c + d v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconst_10(v *Value) bool { // match: (ADDQconst [off] x:(SP)) // result: (LEAQ [off] x) for { off := v.AuxInt x := v.Args[0] if x.Op != OpSP { break } v.reset(OpAMD64LEAQ) v.AuxInt = off v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconstmodify_0(v *Value) bool { // match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ADDQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (ADDQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDQload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (ADDQ x (MOVQf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSDstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDQ) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDQmodify_0(v *Value) bool { // match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ADDQmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSD_0(v *Value) bool { // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVSDload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSDload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (ADDSD x (MOVQi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVQstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDSD) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDSS_0(v *Value) bool { // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVSSload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSSload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (ADDSS x (MOVLi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVLstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDSS) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ANDL_0(v *Value) bool { // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { continue } x := v.Args[1^_i0] v.reset(OpAMD64BTRL) v.AddArg(x) v.AddArg(y) return true } break } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRLconst [log2uint32(^c)] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVLconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRLconst) v.AuxInt = log2uint32(^c) v.AddArg(x) return true } break } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVLconst { continue } c := v_1.AuxInt v.reset(OpAMD64ANDLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ANDL x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVLload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDLconst_0(v *Value) bool { // match: (ANDLconst [c] x) // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRLconst [log2uint32(^c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = log2uint32(^c) v.AddArg(x) return true } // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDLconst [c] (BTRLconst [d] x)) // result: (ANDLconst [c &^ (1<= 128 // result: (BTRQconst [log2(^c)] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVQconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRQconst) v.AuxInt = log2(^c) v.AddArg(x) return true } break } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64ANDQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ANDQ x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVQload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDQconst_0(v *Value) bool { // match: (ANDQconst [c] x) // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRQconst [log2(^c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = log2(^c) v.AddArg(x) return true } // match: (ANDQconst [c] (ANDQconst [d] x)) // result: (ANDQconst [c & d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDQconst [c] (BTRQconst [d] x)) // result: (ANDQconst [c &^ (1< [1<<8] (MOVBQZX x))) // result: (BSFQ (ORQconst [1<<8] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if v_0.AuxInt != 1<<8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVBQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = 1 << 8 v0.AddArg(x) v.AddArg(v0) return true } // match: (BSFQ (ORQconst [1<<16] (MOVWQZX x))) // result: (BSFQ (ORQconst [1<<16] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if v_0.AuxInt != 1<<16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVWQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = 1 << 16 v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64BTCLconst_0(v *Value) bool { // match: (BTCLconst [c] (XORLconst [d] x)) // result: (XORLconst [d ^ 1<d // result: (BTLconst [c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = c - d v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if v.AuxInt != 0 { break } s := v.Args[0] if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg(y) v.AddArg(x) return true } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !((c + d) < 32) { break } v.reset(OpAMD64BTLconst) v.AuxInt = c + d v.AddArg(x) return true } // match: (BTLconst [c] (SHLLconst [d] x)) // cond: c>d // result: (BTLconst [c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = c - d v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRL x y)) // result: (BTL y x) for { if v.AuxInt != 0 { break } s := v.Args[0] if s.Op != OpAMD64SHRL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64BTQconst_0(v *Value) bool { // match: (BTQconst [c] (SHRQconst [d] x)) // cond: (c+d)<64 // result: (BTQconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !((c + d) < 64) { break } v.reset(OpAMD64BTQconst) v.AuxInt = c + d v.AddArg(x) return true } // match: (BTQconst [c] (SHLQconst [d] x)) // cond: c>d // result: (BTQconst [c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTQconst) v.AuxInt = c - d v.AddArg(x) return true } // match: (BTQconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if v.AuxInt != 0 { break } s := v.Args[0] if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64BTRLconst_0(v *Value) bool { // match: (BTRLconst [c] (BTSLconst [c] x)) // result: (BTRLconst [c] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64BTSLconst || v_0.AuxInt != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = c v.AddArg(x) return true } // match: (BTRLconst [c] (BTCLconst [c] x)) // result: (BTRLconst [c] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64BTCLconst || v_0.AuxInt != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = c v.AddArg(x) return true } // match: (BTRLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [d &^ (1<uint8(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int8(x) < int8(y) && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>int8(y) && uint8(x) int8(y) && uint8(x) < uint8(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>int8(y) && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int8(x) > int8(y) && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < int8(n) // result: (FlagLT_ULT) for { n := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } m := v_0.AuxInt if !(0 <= int8(m) && int8(m) < int8(n)) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPBconst (ANDL x y) [0]) // result: (TESTB x y) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64TESTB) v.AddArg(x) v.AddArg(y) return true } // match: (CMPBconst (ANDLconst [c] x) [0]) // result: (TESTBconst [int64(int8(c))] x) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64TESTBconst) v.AuxInt = int64(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // result: (TESTB x x) for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpAMD64TESTB) v.AddArg(x) v.AddArg(x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(c,off)] ptr mem) for { c := v.AuxInt l := v.Args[0] if l.Op != OpAMD64MOVBload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(c, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconstload_0(v *Value) bool { // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (CMPBconstload [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (CMPBconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBload_0(v *Value) bool { // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (CMPBload [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // cond: validValAndOff(int64(int8(c)),off) // result: (CMPBconstload {sym} [makeValAndOff(int64(int8(c)),off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validValAndOff(int64(int8(c)), off)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPL_0(v *Value) bool { b := v.Block // match: (CMPL x (MOVLconst [c])) // result: (CMPLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64CMPLconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // result: (InvertFlags (CMPLconst x [c])) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPLload) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(x) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPLconst_0(v *Value) bool { // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)uint32(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int32(x) < int32(y) && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)>int32(y) && uint32(x) int32(y) && uint32(x) < uint32(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)>int32(y) && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int32(x) > int32(y) && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } x := v_0.AuxInt if !(x < y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>y && uint64(x)>uint64(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } x := v_0.AuxInt if !(x > y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQconst (MOVBQZX _) [c]) // cond: 0xFF < c // result: (FlagLT_ULT) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVWQZX _) [c]) // cond: 0xFFFF < c // result: (FlagLT_ULT) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVLQZX _) [c]) // cond: 0xFFFFFFFF < c // result: (FlagLT_ULT) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLQZX || !(0xFFFFFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } return false } func rewriteValueAMD64_OpAMD64CMPQconst_10(v *Value) bool { b := v.Block // match: (CMPQconst (SHRQconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 64 && (1<uint16(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int16(x) < int16(y) && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>int16(y) && uint16(x) int16(y) && uint16(x) < uint16(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>int16(y) && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int16(x) > int16(y) && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < int16(n) // result: (FlagLT_ULT) for { n := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } m := v_0.AuxInt if !(0 <= int16(m) && int16(m) < int16(n)) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPWconst (ANDL x y) [0]) // result: (TESTW x y) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64TESTW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWconst (ANDLconst [c] x) [0]) // result: (TESTWconst [int64(int16(c))] x) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64TESTWconst) v.AuxInt = int64(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // result: (TESTW x x) for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpAMD64TESTW) v.AddArg(x) v.AddArg(x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(c,off)] ptr mem) for { c := v.AuxInt l := v.Args[0] if l.Op != OpAMD64MOVWload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(c, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWconstload_0(v *Value) bool { // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (CMPWconstload [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (CMPWconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWload_0(v *Value) bool { // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (CMPWload [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // cond: validValAndOff(int64(int16(c)),off) // result: (CMPWconstload {sym} [makeValAndOff(int64(int16(c)),off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validValAndOff(int64(int16(c)), off)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGLlock_0(v *Value) bool { // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(off1+off2) // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] old := v.Args[1] new_ := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPXCHGLlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGQlock_0(v *Value) bool { // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(off1+off2) // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] old := v.Args[1] new_ := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPXCHGQlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSD_0(v *Value) bool { // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSDload_0(v *Value) bool { // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSS_0(v *Value) bool { // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSSload_0(v *Value) bool { // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64HMULL_0(v *Value) bool { // match: (HMULL x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULL y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULL) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64HMULLU_0(v *Value) bool { // match: (HMULLU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULLU y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULLU) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQ_0(v *Value) bool { // match: (HMULQ x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQ y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQ) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQU_0(v *Value) bool { // match: (HMULQU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQU y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQU) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAL_0(v *Value) bool { // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(c+d) // result: (LEAL [c+d] {s} x) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v_0.Args[_i0] y := v_0.Args[1^_i0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL1_0(v *Value) bool { // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDLconst { continue } d := v_0.AuxInt x := v_0.Args[0] y := v.Args[1^_i0] if !(is32Bit(c+d) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL2_0(v *Value) bool { // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+2*d) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+2*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = c + 2*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL4_0(v *Value) bool { // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+4*d) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+4*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = c + 4*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL8_0(v *Value) bool { // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+8*d) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+8*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = c + 8*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ_0(v *Value) bool { // match: (LEAQ [c] {s} (ADDQconst [d] x)) // cond: is32Bit(c+d) // result: (LEAQ [c+d] {s} x) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (LEAQ [c] {s} (ADDQ x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v_0.Args[_i0] y := v_0.Args[1^_i0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) return true } // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ1_0(v *Value) bool { // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDQconst { continue } d := v_0.AuxInt x := v_0.Args[0] y := v.Args[1^_i0] if !(is32Bit(c+d) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64LEAQ { continue } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] y := v.Args[1^_i0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAQ2_0(v *Value) bool { // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ2 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(c+2*d) && y.Op != OpSB // result: (LEAQ2 [c+2*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+2*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = c + 2*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ4_0(v *Value) bool { // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ4 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(c+4*d) && y.Op != OpSB // result: (LEAQ4 [c+4*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+4*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = c + 4*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ4 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ8_0(v *Value) bool { // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ8 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(c+8*d) && y.Op != OpSB // result: (LEAQ8 [c+8*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+8*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = c + 8*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSX_0(v *Value) bool { b := v.Block // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVBload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0x7f v.AddArg(x) return true } // match: (MOVBQSX (MOVBQSX x)) // result: (MOVBQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSXload_0(v *Value) bool { // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBQSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQZX_0(v *Value) bool { b := v.Block // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVBload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x) // cond: zeroUpper56Bits(x,3) // result: x for { x := v.Args[0] if !(zeroUpper56Bits(x, 3)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVBQZX x:(MOVBloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVBloadidx1 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVBloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVBQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0xff v.AddArg(x) return true } // match: (MOVBQZX (MOVBQZX x)) // result: (MOVBQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBatomicload_0(v *Value) bool { // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBatomicload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBload_0(v *Value) bool { // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVBloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(read8(sym, off))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int64(read8(sym, off)) return true } return false } func rewriteValueAMD64_OpAMD64MOVBloadidx1_0(v *Value) bool { // match: (MOVBloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDQconst { continue } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1^_i0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVBloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDQconst { continue } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVBloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVBload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { p := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(i + c)) { continue } v.reset(OpAMD64MOVBload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MOVBstore_0(v *Value) bool { // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) // cond: y.Uses == 1 // result: (SETLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETL { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) // cond: y.Uses == 1 // result: (SETLEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETLE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) // cond: y.Uses == 1 // result: (SETGstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETG { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETGstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) // cond: y.Uses == 1 // result: (SETGEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETGE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) // cond: y.Uses == 1 // result: (SETEQstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETEQ { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) // cond: y.Uses == 1 // result: (SETNEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETNE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) // cond: y.Uses == 1 // result: (SETBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETB { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) // cond: y.Uses == 1 // result: (SETBEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETBE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) // cond: y.Uses == 1 // result: (SETAstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETA { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETAstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) // cond: y.Uses == 1 // result: (SETAEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETAE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_10(v *Value) bool { b := v.Block // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBQSX { break } x := v_1.Args[0] v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBQZX { break } x := v_1.Args[0] v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validOff(off) // result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVBstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] val := v.Args[1] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } break } // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstore [i-1] {s} p (ROLWconst [8] w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x0 := v.Args[2] if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-1 || x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || x0_1.AuxInt != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = 8 v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x2 := v.Args[2] if x2.Op != OpAMD64MOVBstore || x2.AuxInt != i-1 || x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || x2_1.AuxInt != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || x1.AuxInt != i-2 || x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || x1_1.AuxInt != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-3 || x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || x0_1.AuxInt != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 3 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x6 := v.Args[2] if x6.Op != OpAMD64MOVBstore || x6.AuxInt != i-1 || x6.Aux != s { break } _ = x6.Args[2] if p != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || x6_1.AuxInt != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || x5.AuxInt != i-2 || x5.Aux != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || x5_1.AuxInt != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || x4.AuxInt != i-3 || x4.Aux != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || x4_1.AuxInt != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || x3.AuxInt != i-4 || x3.Aux != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || x3_1.AuxInt != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || x2.AuxInt != i-5 || x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || x2_1.AuxInt != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || x1.AuxInt != i-6 || x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || x1_1.AuxInt != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-7 || x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || x0_1.AuxInt != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 7 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRWconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVBload { break } j := x1.AuxInt s2 := x1.Aux mem := x1.Args[1] p2 := x1.Args[0] mem2 := v.Args[2] if mem2.Op != OpAMD64MOVBstore || mem2.AuxInt != i-1 || mem2.Aux != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVBload || x2.AuxInt != j-1 || x2.Aux != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = j - 1 v0.Aux = s2 v0.AddArg(p2) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_30(v *Value) bool { // match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconst_0(v *Value) bool { // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVBstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVBstoreconst { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVBstoreconst [a] {s} p x:(MOVBstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem) for { a := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVBstoreconst { break } c := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconstidx1_0(v *Value) bool { // match: (MOVBstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconstidx1 [c] {s} p i x:(MOVBstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p i mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(i) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreidx1_0(v *Value) bool { b := v.Block // match: (MOVBstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x0:(MOVBstoreidx1 [i-1] {s} p idx (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstoreidx1 [i-1] {s} p idx (ROLWconst [8] w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x0 := v.Args[3] if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-1 || x0.Aux != s { break } mem := x0.Args[3] if p != x0.Args[0] || idx != x0.Args[1] { break } x0_2 := x0.Args[2] if x0_2.Op != OpAMD64SHRWconst || x0_2.AuxInt != 8 || w != x0_2.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = 8 v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x2:(MOVBstoreidx1 [i-1] {s} p idx (SHRLconst [8] w) x1:(MOVBstoreidx1 [i-2] {s} p idx (SHRLconst [16] w) x0:(MOVBstoreidx1 [i-3] {s} p idx (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) // result: (MOVLstoreidx1 [i-3] {s} p idx (BSWAPL w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x2 := v.Args[3] if x2.Op != OpAMD64MOVBstoreidx1 || x2.AuxInt != i-1 || x2.Aux != s { break } _ = x2.Args[3] if p != x2.Args[0] || idx != x2.Args[1] { break } x2_2 := x2.Args[2] if x2_2.Op != OpAMD64SHRLconst || x2_2.AuxInt != 8 || w != x2_2.Args[0] { break } x1 := x2.Args[3] if x1.Op != OpAMD64MOVBstoreidx1 || x1.AuxInt != i-2 || x1.Aux != s { break } _ = x1.Args[3] if p != x1.Args[0] || idx != x1.Args[1] { break } x1_2 := x1.Args[2] if x1_2.Op != OpAMD64SHRLconst || x1_2.AuxInt != 16 || w != x1_2.Args[0] { break } x0 := x1.Args[3] if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-3 || x0.Aux != s { break } mem := x0.Args[3] if p != x0.Args[0] || idx != x0.Args[1] { break } x0_2 := x0.Args[2] if x0_2.Op != OpAMD64SHRLconst || x0_2.AuxInt != 24 || w != x0_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 3 v.Aux = s v.AddArg(p) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x6:(MOVBstoreidx1 [i-1] {s} p idx (SHRQconst [8] w) x5:(MOVBstoreidx1 [i-2] {s} p idx (SHRQconst [16] w) x4:(MOVBstoreidx1 [i-3] {s} p idx (SHRQconst [24] w) x3:(MOVBstoreidx1 [i-4] {s} p idx (SHRQconst [32] w) x2:(MOVBstoreidx1 [i-5] {s} p idx (SHRQconst [40] w) x1:(MOVBstoreidx1 [i-6] {s} p idx (SHRQconst [48] w) x0:(MOVBstoreidx1 [i-7] {s} p idx (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) // result: (MOVQstoreidx1 [i-7] {s} p idx (BSWAPQ w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x6 := v.Args[3] if x6.Op != OpAMD64MOVBstoreidx1 || x6.AuxInt != i-1 || x6.Aux != s { break } _ = x6.Args[3] if p != x6.Args[0] || idx != x6.Args[1] { break } x6_2 := x6.Args[2] if x6_2.Op != OpAMD64SHRQconst || x6_2.AuxInt != 8 || w != x6_2.Args[0] { break } x5 := x6.Args[3] if x5.Op != OpAMD64MOVBstoreidx1 || x5.AuxInt != i-2 || x5.Aux != s { break } _ = x5.Args[3] if p != x5.Args[0] || idx != x5.Args[1] { break } x5_2 := x5.Args[2] if x5_2.Op != OpAMD64SHRQconst || x5_2.AuxInt != 16 || w != x5_2.Args[0] { break } x4 := x5.Args[3] if x4.Op != OpAMD64MOVBstoreidx1 || x4.AuxInt != i-3 || x4.Aux != s { break } _ = x4.Args[3] if p != x4.Args[0] || idx != x4.Args[1] { break } x4_2 := x4.Args[2] if x4_2.Op != OpAMD64SHRQconst || x4_2.AuxInt != 24 || w != x4_2.Args[0] { break } x3 := x4.Args[3] if x3.Op != OpAMD64MOVBstoreidx1 || x3.AuxInt != i-4 || x3.Aux != s { break } _ = x3.Args[3] if p != x3.Args[0] || idx != x3.Args[1] { break } x3_2 := x3.Args[2] if x3_2.Op != OpAMD64SHRQconst || x3_2.AuxInt != 32 || w != x3_2.Args[0] { break } x2 := x3.Args[3] if x2.Op != OpAMD64MOVBstoreidx1 || x2.AuxInt != i-5 || x2.Aux != s { break } _ = x2.Args[3] if p != x2.Args[0] || idx != x2.Args[1] { break } x2_2 := x2.Args[2] if x2_2.Op != OpAMD64SHRQconst || x2_2.AuxInt != 40 || w != x2_2.Args[0] { break } x1 := x2.Args[3] if x1.Op != OpAMD64MOVBstoreidx1 || x1.AuxInt != i-6 || x1.Aux != s { break } _ = x1.Args[3] if p != x1.Args[0] || idx != x1.Args[1] { break } x1_2 := x1.Args[2] if x1_2.Op != OpAMD64SHRQconst || x1_2.AuxInt != 48 || w != x1_2.Args[0] { break } x0 := x1.Args[3] if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-7 || x0.Aux != s { break } mem := x0.Args[3] if p != x0.Args[0] || idx != x0.Args[1] { break } x0_2 := x0.Args[2] if x0_2.Op != OpAMD64SHRQconst || x0_2.AuxInt != 56 || w != x0_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 7 v.Aux = s v.AddArg(p) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRWconst || v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst || v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRQconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreidx1_10(v *Value) bool { // match: (MOVBstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVBstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSX_0(v *Value) bool { b := v.Block // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQSX (ANDLconst [c] x)) // cond: c & 0x80000000 == 0 // result: (ANDLconst [c & 0x7fffffff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x80000000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0x7fffffff v.AddArg(x) return true } // match: (MOVLQSX (MOVLQSX x)) // result: (MOVLQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVWQSX x)) // result: (MOVWQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVBQSX x)) // result: (MOVBQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSXload_0(v *Value) bool { // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLQSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQZX_0(v *Value) bool { b := v.Block // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQZX x) // cond: zeroUpper32Bits(x,3) // result: x for { x := v.Args[0] if !(zeroUpper32Bits(x, 3)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVLQZX x:(MOVLloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLloadidx1 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVLQZX x:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLloadidx4 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLloadidx4 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx4, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVLQZX (ANDLconst [c] x)) // result: (ANDLconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVLQZX (MOVLQZX x)) // result: (MOVLQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVWQZX x)) // result: (MOVWQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVBQZX x)) // result: (MOVBQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLatomicload_0(v *Value) bool { // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLatomicload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLf2i_0(v *Value) bool { b := v.Block // match: (MOVLf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVLi2f_0(v *Value) bool { b := v.Block // match: (MOVLi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVLload_0(v *Value) bool { // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVLloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVSSstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVLf2i) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVLload_10(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64(read32(sym, off, config.BigEndian)) return true } return false } func rewriteValueAMD64_OpAMD64MOVLloadidx1_0(v *Value) bool { // match: (MOVLloadidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) // result: (MOVLloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { continue } idx := v_1.Args[0] v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVLloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVLloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { continue } idx := v_1.Args[0] v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVLloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDQconst { continue } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1^_i0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVLloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDQconst { continue } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVLloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVLload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { p := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(i + c)) { continue } v.reset(OpAMD64MOVLload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MOVLloadidx4_0(v *Value) bool { // match: (MOVLloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVLloadidx4 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+4*d) // result: (MOVLloadidx4 [c+4*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx4 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+4*c) // result: (MOVLload [i+4*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLloadidx8_0(v *Value) bool { // match: (MOVLloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVLloadidx8 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+8*d) // result: (MOVLloadidx8 [c+8*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx8 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+8*c) // result: (MOVLload [i+8*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore_0(v *Value) bool { // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLQSX { break } x := v_1.Args[0] v.reset(OpAMD64MOVLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLQZX { break } x := v_1.Args[0] v.reset(OpAMD64MOVLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(int64(int32(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validOff(off) // result: (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(int64(int32(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVLstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] val := v.Args[1] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MOVLstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst || v_1.AuxInt != 32 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVLstore || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVLstore || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVLload { break } j := x1.AuxInt s2 := x1.Aux mem := x1.Args[1] p2 := x1.Args[0] mem2 := v.Args[2] if mem2.Op != OpAMD64MOVLstore || mem2.AuxInt != i-4 || mem2.Aux != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVLload || x2.AuxInt != j-4 || x2.Aux != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x2.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = j - 4 v0.Aux = s2 v0.AddArg(p2) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDL { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MOVLstore_20(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SUBL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDL { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORL { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORL { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(BTCL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTCLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTCL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTCLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(BTRL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTRLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTRL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTRLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(BTSL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTSLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTSL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTSLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ADDLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ADDLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ANDLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ANDLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ANDLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ORLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ORLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ORLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore_30(v *Value) bool { // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (XORLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64XORLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64XORLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(BTCLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTCLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTCLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTCLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(BTRLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTRLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTRLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTRLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(BTSLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTSLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTSLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTSLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) // result: (MOVSSstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLf2i { break } val := v_1.Args[0] v.reset(OpAMD64MOVSSstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconst_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym1} (LEAQ4 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVLstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [c] {s} p x:(MOVLstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstore [ValAndOff(a).Off()] {s} p (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVLstoreconst { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVLstoreconst [a] {s} p x:(MOVLstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstore [ValAndOff(a).Off()] {s} p (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { a := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVLstoreconst { break } c := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconstidx1_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconstidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) // result: (MOVLstoreconstidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [c] {s} p i x:(MOVLstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstoreidx1 [ValAndOff(a).Off()] {s} p i (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVLstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconstidx4_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconstidx4 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx4 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(4*c) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(4*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(4 * c)) { break } v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(4 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx4 [c] {s} p i x:(MOVLstoreconstidx4 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstoreidx1 [ValAndOff(a).Off()] {s} p (SHLQconst [2] i) (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVLstoreconstidx4 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, i.Type) v0.AuxInt = 2 v0.AddArg(i) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v1) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreidx1_0(v *Value) bool { // match: (MOVLstoreidx1 [c] {sym} ptr (SHLQconst [2] idx) val mem) // result: (MOVLstoreidx4 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) // result: (MOVLstoreidx8 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [i] {s} p idx (SHRQconst [32] w) x:(MOVLstoreidx1 [i-4] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 32 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx1 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVLstoreidx1 [i-4] {s} p idx w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx1 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVLstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreidx4_0(v *Value) bool { b := v.Block // match: (MOVLstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx4 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+4*d) // result: (MOVLstoreidx4 [c+4*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [i] {s} p idx (SHRQconst [32] w) x:(MOVLstoreidx4 [i-4] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p (SHLQconst [2] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 32 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx4 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 2 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [i] {s} p idx (SHRQconst [j] w) x:(MOVLstoreidx4 [i-4] {s} p idx w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p (SHLQconst [2] idx) w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx4 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 2 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+4*c) // result: (MOVLstore [i+4*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreidx8_0(v *Value) bool { // match: (MOVLstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx8 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+8*d) // result: (MOVLstoreidx8 [c+8*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx8 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+8*c) // result: (MOVLstore [i+8*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOload_0(v *Value) bool { // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVOload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstore_0(v *Value) bool { // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVOstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQatomicload_0(v *Value) bool { // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVQatomicload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQf2i_0(v *Value) bool { b := v.Block // match: (MOVQf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVQi2f_0(v *Value) bool { b := v.Block // match: (MOVQi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVQload_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVQloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVQload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) // result: (MOVQf2i val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVSDstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVQf2i) v.AddArg(val) return true } // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64(read64(sym, off, config.BigEndian)) return true } return false } func rewriteValueAMD64_OpAMD64MOVQloadidx1_0(v *Value) bool { // match: (MOVQloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVQloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { continue } idx := v_1.Args[0] v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVQloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDQconst { continue } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1^_i0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVQloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDQconst { continue } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVQloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVQload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { p := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(i + c)) { continue } v.reset(OpAMD64MOVQload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MOVQloadidx8_0(v *Value) bool { // match: (MOVQloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVQloadidx8 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+8*d) // result: (MOVQloadidx8 [c+8*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx8 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+8*c) // result: (MOVQload [i+8*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_0(v *Value) bool { // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validValAndOff(c,off) // result: (MOVQstoreconst [makeValAndOff(c,off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validValAndOff(c, off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVQstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] val := v.Args[1] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } break } // match: (MOVQstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_10(v *Value) bool { // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDQ { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64ADDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SUBQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDQ { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64ANDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORQ { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64ORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORQ { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64XORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(BTCQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTCQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTCQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTCQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(BTRQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTRQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTRQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTRQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(BTSQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTSQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTSQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTSQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_20(v *Value) bool { // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ADDQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ADDQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ANDQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ANDQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ANDQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ORQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ORQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ORQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (XORQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64XORQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64XORQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(BTCQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTCQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTCQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTCQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(BTRQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTRQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTRQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTRQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(BTSQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTSQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTSQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTSQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) // result: (MOVSDstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQf2i { break } val := v_1.Args[0] v.reset(OpAMD64MOVSDstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconst_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVQstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconst [x] {sym1} (LEAQ8 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVQstoreconstidx8 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVQstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconst [c] {s} p x:(MOVQstoreconst [c2] {s} p mem)) // cond: config.useSSE && x.Uses == 1 && ValAndOff(c2).Off() + 8 == ValAndOff(c).Off() && ValAndOff(c).Val() == 0 && ValAndOff(c2).Val() == 0 && clobber(x) // result: (MOVOstore [ValAndOff(c2).Off()] {s} p (MOVOconst [0]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVQstoreconst { break } c2 := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(config.useSSE && x.Uses == 1 && ValAndOff(c2).Off()+8 == ValAndOff(c).Off() && ValAndOff(c).Val() == 0 && ValAndOff(c2).Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = ValAndOff(c2).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(x.Pos, OpAMD64MOVOconst, types.TypeInt128) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconstidx1_0(v *Value) bool { // match: (MOVQstoreconstidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVQstoreconstidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVQstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVQstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconstidx8_0(v *Value) bool { // match: (MOVQstoreconstidx8 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVQstoreconstidx8 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconstidx8 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(8*c) // result: (MOVQstoreconstidx8 [ValAndOff(x).add(8*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(8 * c)) { break } v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = ValAndOff(x).add(8 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreidx1_0(v *Value) bool { // match: (MOVQstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) // result: (MOVQstoreidx8 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVQstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVQstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVQstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreidx8_0(v *Value) bool { // match: (MOVQstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVQstoreidx8 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+8*d) // result: (MOVQstoreidx8 [c+8*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx8 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+8*c) // result: (MOVQstore [i+8*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDload_0(v *Value) bool { // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVSDloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVQi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDloadidx1_0(v *Value) bool { // match: (MOVSDloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVSDloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSDloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVSDloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVSDload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDloadidx8_0(v *Value) bool { // match: (MOVSDloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSDloadidx8 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+8*d) // result: (MOVSDloadidx8 [c+8*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx8 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+8*c) // result: (MOVSDload [i+8*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstore_0(v *Value) bool { // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVSDstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] val := v.Args[1] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } break } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQi2f { break } val := v_1.Args[0] v.reset(OpAMD64MOVQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstoreidx1_0(v *Value) bool { // match: (MOVSDstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) // result: (MOVSDstoreidx8 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSDstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVSDstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVSDstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstoreidx8_0(v *Value) bool { // match: (MOVSDstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSDstoreidx8 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+8*d) // result: (MOVSDstoreidx8 [c+8*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx8 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+8*c) // result: (MOVSDstore [i+8*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSload_0(v *Value) bool { // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVSSloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVLi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSloadidx1_0(v *Value) bool { // match: (MOVSSloadidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) // result: (MOVSSloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSSloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVSSloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVSSload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSloadidx4_0(v *Value) bool { // match: (MOVSSloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSSloadidx4 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+4*d) // result: (MOVSSloadidx4 [c+4*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx4 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+4*c) // result: (MOVSSload [i+4*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstore_0(v *Value) bool { // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVSSstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] val := v.Args[1] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } break } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLi2f { break } val := v_1.Args[0] v.reset(OpAMD64MOVLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstoreidx1_0(v *Value) bool { // match: (MOVSSstoreidx1 [c] {sym} ptr (SHLQconst [2] idx) val mem) // result: (MOVSSstoreidx4 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSSstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVSSstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVSSstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstoreidx4_0(v *Value) bool { // match: (MOVSSstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSSstoreidx4 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+4*d) // result: (MOVSSstoreidx4 [c+4*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx4 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+4*c) // result: (MOVSSstore [i+4*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSX_0(v *Value) bool { b := v.Block // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0x7fff v.AddArg(x) return true } // match: (MOVWQSX (MOVWQSX x)) // result: (MOVWQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSX (MOVBQSX x)) // result: (MOVBQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSXload_0(v *Value) bool { // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWQSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQZX_0(v *Value) bool { b := v.Block // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQZX x) // cond: zeroUpper48Bits(x,3) // result: x for { x := v.Args[0] if !(zeroUpper48Bits(x, 3)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWQZX x:(MOVWloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWloadidx1 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVWQZX x:(MOVWloadidx2 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWloadidx2 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWloadidx2 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx2, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVWQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xffff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0xffff v.AddArg(x) return true } // match: (MOVWQZX (MOVWQZX x)) // result: (MOVWQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWQZX (MOVBQZX x)) // result: (MOVBQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWload_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWloadidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWloadidx2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVWloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(read16(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int64(read16(sym, off, config.BigEndian)) return true } return false } func rewriteValueAMD64_OpAMD64MOVWloadidx1_0(v *Value) bool { // match: (MOVWloadidx1 [c] {sym} ptr (SHLQconst [1] idx) mem) // result: (MOVWloadidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { continue } idx := v_1.Args[0] v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVWloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDQconst { continue } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1^_i0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVWloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDQconst { continue } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVWloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVWload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { p := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(i + c)) { continue } v.reset(OpAMD64MOVWload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MOVWloadidx2_0(v *Value) bool { // match: (MOVWloadidx2 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVWloadidx2 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx2 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+2*d) // result: (MOVWloadidx2 [c+2*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 2*d)) { break } v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c + 2*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx2 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+2*c) // result: (MOVWload [i+2*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 2*c)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = i + 2*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore_0(v *Value) bool { // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWQSX { break } x := v_1.Args[0] v.reset(OpAMD64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWQZX { break } x := v_1.Args[0] v.reset(OpAMD64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validOff(off) // result: (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstoreidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVWstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] val := v.Args[1] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } break } // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst || v_1.AuxInt != 16 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst || v_1.AuxInt != 16 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVWload { break } j := x1.AuxInt s2 := x1.Aux mem := x1.Args[1] p2 := x1.Args[0] mem2 := v.Args[2] if mem2.Op != OpAMD64MOVWstore || mem2.AuxInt != i-2 || mem2.Aux != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVWload || x2.AuxInt != j-2 || x2.Aux != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x2.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = j - 2 v0.Aux = s2 v0.AddArg(p2) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconst_0(v *Value) bool { // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym1} (LEAQ2 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVWstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVWstoreconst { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVWstoreconst [a] {s} p x:(MOVWstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem) for { a := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVWstoreconst { break } c := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconstidx1_0(v *Value) bool { // match: (MOVWstoreconstidx1 [c] {sym} ptr (SHLQconst [1] idx) mem) // result: (MOVWstoreconstidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [c] {s} p i x:(MOVWstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p i mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVWstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(i) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconstidx2_0(v *Value) bool { b := v.Block // match: (MOVWstoreconstidx2 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx2 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(2*c) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(2*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(2 * c)) { break } v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(2 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx2 [c] {s} p i x:(MOVWstoreconstidx2 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p (SHLQconst [1] i) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVWstoreconstidx2 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, i.Type) v0.AuxInt = 1 v0.AddArg(i) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreidx1_0(v *Value) bool { // match: (MOVWstoreidx1 [c] {sym} ptr (SHLQconst [1] idx) val mem) // result: (MOVWstoreidx2 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVWstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVWstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRQconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVWstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreidx2_0(v *Value) bool { b := v.Block // match: (MOVWstoreidx2 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVWstoreidx2 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+2*d) // result: (MOVWstoreidx2 [c+2*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 2*d)) { break } v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = c + 2*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLQconst [1] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx2 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRQconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLQconst [1] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx2 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRQconst [j] w) x:(MOVWstoreidx2 [i-2] {s} p idx w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLQconst [1] idx) w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx2 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+2*c) // result: (MOVWstore [i+2*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 2*c)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i + 2*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MULL_0(v *Value) bool { // match: (MULL x (MOVLconst [c])) // result: (MULLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVLconst { continue } c := v_1.AuxInt v.reset(OpAMD64MULLconst) v.AuxInt = c v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULLconst_0(v *Value) bool { b := v.Block // match: (MULLconst [c] (MULLconst [d] x)) // result: (MULLconst [int64(int32(c * d))] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MULLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64MULLconst) v.AuxInt = int64(int32(c * d)) v.AddArg(x) return true } // match: (MULLconst [-9] x) // result: (NEGL (LEAL8 x x)) for { if v.AuxInt != -9 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // result: (NEGL (LEAL4 x x)) for { if v.AuxInt != -5 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // result: (NEGL (LEAL2 x x)) for { if v.AuxInt != -3 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // result: (NEGL x) for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } // match: (MULLconst [ 0] _) // result: (MOVLconst [0]) for { if v.AuxInt != 0 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (MULLconst [ 1] x) // result: x for { if v.AuxInt != 1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MULLconst [ 3] x) // result: (LEAL2 x x) for { if v.AuxInt != 3 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [ 5] x) // result: (LEAL4 x x) for { if v.AuxInt != 5 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [ 7] x) // result: (LEAL2 x (LEAL2 x x)) for { if v.AuxInt != 7 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_10(v *Value) bool { b := v.Block // match: (MULLconst [ 9] x) // result: (LEAL8 x x) for { if v.AuxInt != 9 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [11] x) // result: (LEAL2 x (LEAL4 x x)) for { if v.AuxInt != 11 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [13] x) // result: (LEAL4 x (LEAL2 x x)) for { if v.AuxInt != 13 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [19] x) // result: (LEAL2 x (LEAL8 x x)) for { if v.AuxInt != 19 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [21] x) // result: (LEAL4 x (LEAL4 x x)) for { if v.AuxInt != 21 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [25] x) // result: (LEAL8 x (LEAL2 x x)) for { if v.AuxInt != 25 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [27] x) // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if v.AuxInt != 27 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULLconst [37] x) // result: (LEAL4 x (LEAL8 x x)) for { if v.AuxInt != 37 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [41] x) // result: (LEAL8 x (LEAL4 x x)) for { if v.AuxInt != 41 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [45] x) // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if v.AuxInt != 45 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_20(v *Value) bool { b := v.Block // match: (MULLconst [73] x) // result: (LEAL8 x (LEAL8 x x)) for { if v.AuxInt != 73 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [81] x) // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if v.AuxInt != 81 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c+1) && c >= 15 // result: (SUBL (SHLLconst [log2(c+1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c+1) && c >= 15) { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c + 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [log2(c-1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-1) && c >= 17) { break } v.reset(OpAMD64LEAL1) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [log2(c-2)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-2) && c >= 34) { break } v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 2) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [log2(c-4)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-4) && c >= 68) { break } v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 4) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [log2(c-8)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-8) && c >= 136) { break } v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 8) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo(c/3) // result: (SHLLconst [log2(c/3)] (LEAL2 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%3 == 0 && isPowerOfTwo(c/3)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = log2(c / 3) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo(c/5) // result: (SHLLconst [log2(c/5)] (LEAL4 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%5 == 0 && isPowerOfTwo(c/5)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = log2(c / 5) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo(c/9) // result: (SHLLconst [log2(c/9)] (LEAL8 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%9 == 0 && isPowerOfTwo(c/9)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = log2(c / 9) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_30(v *Value) bool { // match: (MULLconst [c] (MOVLconst [d])) // result: (MOVLconst [int64(int32(c*d))]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = int64(int32(c * d)) return true } return false } func rewriteValueAMD64_OpAMD64MULQ_0(v *Value) bool { // match: (MULQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (MULQconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64MULQconst) v.AuxInt = c v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULQconst_0(v *Value) bool { b := v.Block // match: (MULQconst [c] (MULQconst [d] x)) // cond: is32Bit(c*d) // result: (MULQconst [c * d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MULQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c * d)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = c * d v.AddArg(x) return true } // match: (MULQconst [-9] x) // result: (NEGQ (LEAQ8 x x)) for { if v.AuxInt != -9 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [-5] x) // result: (NEGQ (LEAQ4 x x)) for { if v.AuxInt != -5 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [-3] x) // result: (NEGQ (LEAQ2 x x)) for { if v.AuxInt != -3 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [-1] x) // result: (NEGQ x) for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v.AddArg(x) return true } // match: (MULQconst [ 0] _) // result: (MOVQconst [0]) for { if v.AuxInt != 0 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (MULQconst [ 1] x) // result: x for { if v.AuxInt != 1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MULQconst [ 3] x) // result: (LEAQ2 x x) for { if v.AuxInt != 3 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(x) return true } // match: (MULQconst [ 5] x) // result: (LEAQ4 x x) for { if v.AuxInt != 5 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v.AddArg(x) return true } // match: (MULQconst [ 7] x) // result: (LEAQ2 x (LEAQ2 x x)) for { if v.AuxInt != 7 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_10(v *Value) bool { b := v.Block // match: (MULQconst [ 9] x) // result: (LEAQ8 x x) for { if v.AuxInt != 9 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v.AddArg(x) return true } // match: (MULQconst [11] x) // result: (LEAQ2 x (LEAQ4 x x)) for { if v.AuxInt != 11 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [13] x) // result: (LEAQ4 x (LEAQ2 x x)) for { if v.AuxInt != 13 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [19] x) // result: (LEAQ2 x (LEAQ8 x x)) for { if v.AuxInt != 19 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [21] x) // result: (LEAQ4 x (LEAQ4 x x)) for { if v.AuxInt != 21 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [25] x) // result: (LEAQ8 x (LEAQ2 x x)) for { if v.AuxInt != 25 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [27] x) // result: (LEAQ8 (LEAQ2 x x) (LEAQ2 x x)) for { if v.AuxInt != 27 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULQconst [37] x) // result: (LEAQ4 x (LEAQ8 x x)) for { if v.AuxInt != 37 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [41] x) // result: (LEAQ8 x (LEAQ4 x x)) for { if v.AuxInt != 41 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [45] x) // result: (LEAQ8 (LEAQ4 x x) (LEAQ4 x x)) for { if v.AuxInt != 45 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_20(v *Value) bool { b := v.Block // match: (MULQconst [73] x) // result: (LEAQ8 x (LEAQ8 x x)) for { if v.AuxInt != 73 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [81] x) // result: (LEAQ8 (LEAQ8 x x) (LEAQ8 x x)) for { if v.AuxInt != 81 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c+1) && c >= 15 // result: (SUBQ (SHLQconst [log2(c+1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c+1) && c >= 15) { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c + 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-1) && c >= 17 // result: (LEAQ1 (SHLQconst [log2(c-1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-1) && c >= 17) { break } v.reset(OpAMD64LEAQ1) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-2) && c >= 34 // result: (LEAQ2 (SHLQconst [log2(c-2)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-2) && c >= 34) { break } v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 2) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-4) && c >= 68 // result: (LEAQ4 (SHLQconst [log2(c-4)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-4) && c >= 68) { break } v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 4) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-8) && c >= 136 // result: (LEAQ8 (SHLQconst [log2(c-8)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-8) && c >= 136) { break } v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 8) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: c%3 == 0 && isPowerOfTwo(c/3) // result: (SHLQconst [log2(c/3)] (LEAQ2 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%3 == 0 && isPowerOfTwo(c/3)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = log2(c / 3) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%5 == 0 && isPowerOfTwo(c/5) // result: (SHLQconst [log2(c/5)] (LEAQ4 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%5 == 0 && isPowerOfTwo(c/5)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = log2(c / 5) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%9 == 0 && isPowerOfTwo(c/9) // result: (SHLQconst [log2(c/9)] (LEAQ8 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%9 == 0 && isPowerOfTwo(c/9)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = log2(c / 9) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_30(v *Value) bool { // match: (MULQconst [c] (MOVQconst [d])) // result: (MOVQconst [c*d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = c * d return true } // match: (MULQconst [c] (NEGQ x)) // cond: c != -(1<<31) // result: (MULQconst [-c] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = -c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULSD_0(v *Value) bool { // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVSDload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSDload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (MULSD x (MOVQi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVQstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64MULSD) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULSS_0(v *Value) bool { // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVSSload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSSload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (MULSS x (MOVLi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVLstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64MULSS) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64NEGL_0(v *Value) bool { // match: (NEGL (NEGL x)) // result: x for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGL { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (NEGL s:(SUBL x y)) // cond: s.Uses == 1 // result: (SUBL y x) for { s := v.Args[0] if s.Op != OpAMD64SUBL { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBL) v.AddArg(y) v.AddArg(x) return true } // match: (NEGL (MOVLconst [c])) // result: (MOVLconst [int64(int32(-c))]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = int64(int32(-c)) return true } return false } func rewriteValueAMD64_OpAMD64NEGQ_0(v *Value) bool { // match: (NEGQ (NEGQ x)) // result: x for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (NEGQ s:(SUBQ x y)) // cond: s.Uses == 1 // result: (SUBQ y x) for { s := v.Args[0] if s.Op != OpAMD64SUBQ { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBQ) v.AddArg(y) v.AddArg(x) return true } // match: (NEGQ (MOVQconst [c])) // result: (MOVQconst [-c]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = -c return true } // match: (NEGQ (ADDQconst [c] (NEGQ x))) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } x := v_0_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = -c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64NOTL_0(v *Value) bool { // match: (NOTL (MOVLconst [c])) // result: (MOVLconst [^c]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = ^c return true } return false } func rewriteValueAMD64_OpAMD64NOTQ_0(v *Value) bool { // match: (NOTQ (MOVQconst [c])) // result: (MOVQconst [^c]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = ^c return true } return false } func rewriteValueAMD64_OpAMD64ORL_0(v *Value) bool { // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { continue } x := v.Args[1^_i0] v.reset(OpAMD64BTSL) v.AddArg(x) v.AddArg(y) return true } break } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSLconst [log2uint32(c)] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVLconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } break } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVLconst { continue } c := v_1.AuxInt v.reset(OpAMD64ORLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRLconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRWconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRBconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (RORL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRL { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHLL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (RORL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRL { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHLL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } } break } return false } func rewriteValueAMD64_OpAMD64ORL_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHRW x (ANDQconst y [15])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg(x) v.AddArg(y) return true } break } // match: (ORL (SHRW x (ANDLconst y [15])) (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg(x) v.AddArg(y) return true } break } // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg(x) v.AddArg(y) return true } break } // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg(x) v.AddArg(y) return true } break } // match: (ORL x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ORL x0:(MOVBload [i0] {s} p mem) sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORL_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVWload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpAMD64SHLLconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1^_i0] if or.Op != OpAMD64ORL { continue } _ = or.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s0 := or.Args[_i1] if s0.Op != OpAMD64SHLLconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or.Args[1^_i1] if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } break } // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } } } break } // match: (ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVWloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } } } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpAMD64SHLLconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] or := v.Args[1^_i0] if or.Op != OpAMD64ORL { continue } _ = or.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s0 := or.Args[_i2] if s0.Op != OpAMD64SHLLconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i3 := 0; _i3 <= 1; _i3++ { if p != x0.Args[_i3] || idx != x0.Args[1^_i3] || mem != x0.Args[2] { continue } y := or.Args[1^_i2] if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } } } break } // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x1 := v.Args[_i0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { r1 := v.Args[_i0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpAMD64SHLLconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1^_i0] if or.Op != OpAMD64ORL { continue } _ = or.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s1 := or.Args[_i1] if s1.Op != OpAMD64SHLLconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or.Args[1^_i1] if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } break } // match: (ORL x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x1 := v.Args[_i0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } } } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { r1 := v.Args[_i0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } } } break } return false } func rewriteValueAMD64_OpAMD64ORL_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpAMD64SHLLconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] or := v.Args[1^_i0] if or.Op != OpAMD64ORL { continue } _ = or.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s1 := or.Args[_i2] if s1.Op != OpAMD64SHLLconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i3 := 0; _i3 <= 1; _i3++ { if p != x1.Args[_i3] || idx != x1.Args[1^_i3] || mem != x1.Args[2] { continue } y := or.Args[1^_i2] if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } } } break } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVLload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORLconst_0(v *Value) bool { // match: (ORLconst [c] x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSLconst [log2uint32(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (ORLconst [c] (ORLconst [d] x)) // result: (ORLconst [c | d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ORLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ORLconst) v.AuxInt = c | d v.AddArg(x) return true } // match: (ORLconst [c] (BTSLconst [d] x)) // result: (ORLconst [c | 1<= 128 // result: (BTSQconst [log2(c)] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVQconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSQconst) v.AuxInt = log2(c) v.AddArg(x) return true } break } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64ORQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLQconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRQconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLQ { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLQ { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRQ { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHLQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRQ { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHLQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORQ x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ORQ x0:(MOVBload [i0] {s} p mem) sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQ_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVWload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } break } // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVLload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s0 := or.Args[_i1] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or.Args[1^_i1] if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s0 := or.Args[_i1] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or.Args[1^_i1] if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } break } // match: (ORQ x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } } } break } // match: (ORQ x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVWloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } } } break } // match: (ORQ x0:(MOVLloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVLloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s0 := or.Args[_i2] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i3 := 0; _i3 <= 1; _i3++ { if p != x0.Args[_i3] || idx != x0.Args[1^_i3] || mem != x0.Args[2] { continue } y := or.Args[1^_i2] if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s0 := or.Args[_i2] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i3 := 0; _i3 <= 1; _i3++ { if p != x0.Args[_i3] || idx != x0.Args[1^_i3] || mem != x0.Args[2] { continue } y := or.Args[1^_i2] if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } } } break } // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x1 := v.Args[_i0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQ_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { r1 := v.Args[_i0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { r1 := v.Args[_i0] if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s1 := or.Args[_i1] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or.Args[1^_i1] if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s1 := or.Args[_i1] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or.Args[1^_i1] if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } break } // match: (ORQ x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x1 := v.Args[_i0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } } } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { r1 := v.Args[_i0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } } } break } // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { r1 := v.Args[_i0] if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } } } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s1 := or.Args[_i2] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i3 := 0; _i3 <= 1; _i3++ { if p != x1.Args[_i3] || idx != x1.Args[1^_i3] || mem != x1.Args[2] { continue } y := or.Args[1^_i2] if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s1 := or.Args[_i2] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i3 := 0; _i3 <= 1; _i3++ { if p != x1.Args[_i3] || idx != x1.Args[1^_i3] || mem != x1.Args[2] { continue } y := or.Args[1^_i2] if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } } } break } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVQload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQconst_0(v *Value) bool { // match: (ORQconst [c] x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSQconst [log2(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (ORQconst [c] (ORQconst [d] x)) // result: (ORQconst [c | d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ORQconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ORQconst) v.AuxInt = c | d v.AddArg(x) return true } // match: (ORQconst [c] (BTSQconst [d] x)) // result: (ORQconst [c | 1<>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = int64(int8(d)) >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SARL_0(v *Value) bool { b := v.Block // match: (SARL x (MOVQconst [c])) // result: (SARLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SARLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SARL x (MOVLconst [c])) // result: (SARLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SARLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SARL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARLconst_0(v *Value) bool { // match: (SARLconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARLconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int32(d))>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = int64(int32(d)) >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SARQ_0(v *Value) bool { b := v.Block // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SARQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SARQ x (MOVLconst [c])) // result: (SARQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SARQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SARQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARQconst_0(v *Value) bool { // match: (SARQconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARQconst [c] (MOVQconst [d])) // result: (MOVQconst [d>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = d >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SARW_0(v *Value) bool { // match: (SARW x (MOVQconst [c])) // result: (SARWconst [min(c&31,15)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SARWconst) v.AuxInt = min(c&31, 15) v.AddArg(x) return true } // match: (SARW x (MOVLconst [c])) // result: (SARWconst [min(c&31,15)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SARWconst) v.AuxInt = min(c&31, 15) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SARWconst_0(v *Value) bool { // match: (SARWconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARWconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int16(d))>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = int64(int16(d)) >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SBBLcarrymask_0(v *Value) bool { // match: (SBBLcarrymask (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SBBLcarrymask (FlagLT_ULT)) // result: (MOVLconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = -1 return true } // match: (SBBLcarrymask (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SBBLcarrymask (FlagGT_ULT)) // result: (MOVLconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = -1 return true } // match: (SBBLcarrymask (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SBBQ_0(v *Value) bool { // match: (SBBQ x (MOVQconst [c]) borrow) // cond: is32Bit(c) // result: (SBBQconst x [c] borrow) for { borrow := v.Args[2] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64SBBQconst) v.AuxInt = c v.AddArg(x) v.AddArg(borrow) return true } // match: (SBBQ x y (FlagEQ)) // result: (SUBQborrow x y) for { _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQborrow) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64SBBQcarrymask_0(v *Value) bool { // match: (SBBQcarrymask (FlagEQ)) // result: (MOVQconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (SBBQcarrymask (FlagLT_ULT)) // result: (MOVQconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = -1 return true } // match: (SBBQcarrymask (FlagLT_UGT)) // result: (MOVQconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (SBBQcarrymask (FlagGT_ULT)) // result: (MOVQconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = -1 return true } // match: (SBBQcarrymask (FlagGT_UGT)) // result: (MOVQconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SBBQconst_0(v *Value) bool { // match: (SBBQconst x [c] (FlagEQ)) // result: (SUBQconstborrow x [c]) for { c := v.AuxInt _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SETA_0(v *Value) bool { // match: (SETA (InvertFlags x)) // result: (SETB x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETA (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETAE_0(v *Value) bool { // match: (SETAE (InvertFlags x)) // result: (SETBE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETAE (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETAE (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETAE (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETAE (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETAEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETBEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETAEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETAstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETAstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETB_0(v *Value) bool { // match: (SETB (InvertFlags x)) // result: (SETA x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETB (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETB (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETB (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETB (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETBE_0(v *Value) bool { // match: (SETBE (InvertFlags x)) // result: (SETAE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETBE (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETBEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETBEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETBstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETAstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETBstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ_0(v *Value) bool { b := v.Block // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (SETAE (BTLconst [log2uint32(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64MOVQconst { continue } c := v_0_0.AuxInt x := v_0.Args[1^_i0] if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPLconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETNE (CMPQconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPQconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } break } return false } func rewriteValueAMD64_OpAMD64SETEQ_10(v *Value) bool { b := v.Block // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETEQ (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore_0(v *Value) bool { b := v.Block // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_1_0 := v_1.Args[_i0] if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { continue } y := v_1.Args[1^_i0] v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_1_0 := v_1.Args[_i0] if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { continue } y := v_1.Args[1^_i0] v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTLconst [log2uint32(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTLconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_1_0 := v_1.Args[_i0] if v_1_0.Op != OpAMD64MOVQconst { continue } c := v_1_0.AuxInt x := v_1.Args[1^_i0] if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPLconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPQconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64SETEQstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } x := z1.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } x := z1.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETEQstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETG_0(v *Value) bool { // match: (SETG (InvertFlags x)) // result: (SETL x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETG (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETGE_0(v *Value) bool { // match: (SETGE (InvertFlags x)) // result: (SETLE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETGE (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETGE (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETGE (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETGE (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETGEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETLEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETGEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETGstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETGstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETL_0(v *Value) bool { // match: (SETL (InvertFlags x)) // result: (SETG x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETL (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETL (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETL (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETL (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETLE_0(v *Value) bool { // match: (SETLE (InvertFlags x)) // result: (SETGE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETLE (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETLEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETGEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETLEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETLstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETGstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETLstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNE_0(v *Value) bool { b := v.Block // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } break } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (SETB (BTLconst [log2uint32(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64MOVQconst { continue } c := v_0_0.AuxInt x := v_0.Args[1^_i0] if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPLconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETEQ (CMPQconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPQconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } break } return false } func rewriteValueAMD64_OpAMD64SETNE_10(v *Value) bool { b := v.Block // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (InvertFlags x)) // result: (SETNE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETNE (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore_0(v *Value) bool { b := v.Block // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_1_0 := v_1.Args[_i0] if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { continue } y := v_1.Args[1^_i0] v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_1_0 := v_1.Args[_i0] if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { continue } y := v_1.Args[1^_i0] v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTLconst [log2uint32(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTLconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_1_0 := v_1.Args[_i0] if v_1_0.Op != OpAMD64MOVQconst { continue } c := v_1_0.AuxInt x := v_1.Args[1^_i0] if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPLconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPQconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64SETNEstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } x := z1.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } x := z1.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETNEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLL_0(v *Value) bool { b := v.Block // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHLL x (MOVLconst [c])) // result: (SHLLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHLL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLLconst_0(v *Value) bool { // match: (SHLLconst [1] (SHRLconst [1] x)) // result: (BTRLconst [0] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = 0 v.AddArg(x) return true } // match: (SHLLconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHLQ_0(v *Value) bool { b := v.Block // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHLQ x (MOVLconst [c])) // result: (SHLQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHLQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLQconst_0(v *Value) bool { // match: (SHLQconst [1] (SHRQconst [1] x)) // result: (BTRQconst [0] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = 0 v.AddArg(x) return true } // match: (SHLQconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRB_0(v *Value) bool { // match: (SHRB x (MOVQconst [c])) // cond: c&31 < 8 // result: (SHRBconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRB _ (MOVQconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SHRBconst_0(v *Value) bool { // match: (SHRBconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRL_0(v *Value) bool { b := v.Block // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRL x (MOVLconst [c])) // result: (SHRLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRLconst_0(v *Value) bool { // match: (SHRLconst [1] (SHLLconst [1] x)) // result: (BTRLconst [31] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = 31 v.AddArg(x) return true } // match: (SHRLconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRQ_0(v *Value) bool { b := v.Block // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHRQ x (MOVLconst [c])) // result: (SHRQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHRQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRQconst_0(v *Value) bool { // match: (SHRQconst [1] (SHLQconst [1] x)) // result: (BTRQconst [63] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = 63 v.AddArg(x) return true } // match: (SHRQconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRW_0(v *Value) bool { // match: (SHRW x (MOVQconst [c])) // cond: c&31 < 16 // result: (SHRWconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRW _ (MOVQconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SHRWconst_0(v *Value) bool { // match: (SHRWconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBL_0(v *Value) bool { b := v.Block // match: (SUBL x (MOVLconst [c])) // result: (SUBLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SUBLconst) v.AuxInt = c v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // result: (NEGL (SUBLconst x [c])) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x x) // result: (MOVLconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBLconst_0(v *Value) bool { // match: (SUBLconst [c] x) // cond: int32(c) == 0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SUBLconst [c] x) // result: (ADDLconst [int64(int32(-c))] x) for { c := v.AuxInt x := v.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int64(int32(-c)) v.AddArg(x) return true } } func rewriteValueAMD64_OpAMD64SUBLload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (SUBL x (MOVLf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSSstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBL) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBLmodify_0(v *Value) bool { // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQ_0(v *Value) bool { b := v.Block // match: (SUBQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconst) v.AuxInt = c v.AddArg(x) return true } // match: (SUBQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (NEGQ (SUBQconst x [c])) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBQ x x) // result: (MOVQconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBQload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQborrow_0(v *Value) bool { // match: (SUBQborrow x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconstborrow x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQconst_0(v *Value) bool { // match: (SUBQconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SUBQconst [c] x) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { c := v.AuxInt x := v.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = -c v.AddArg(x) return true } // match: (SUBQconst (MOVQconst [d]) [c]) // result: (MOVQconst [d-c]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = d - c return true } // match: (SUBQconst (SUBQconst x [d]) [c]) // cond: is32Bit(-c-d) // result: (ADDQconst [-c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SUBQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(-c - d)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = -c - d v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBQload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (SUBQ x (MOVQf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSDstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBQ) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBQmodify_0(v *Value) bool { // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SUBQmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSD_0(v *Value) bool { // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSDload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (SUBSD x (MOVQi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVQstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBSD) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBSS_0(v *Value) bool { // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSSload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (SUBSS x (MOVLi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVLstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBSS) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64TESTB_0(v *Value) bool { b := v.Block // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVLconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] v.reset(OpAMD64TESTBconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := v.Args[_i0] if l.Op != OpAMD64MOVBload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] l2 := v.Args[1^_i0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTBconst_0(v *Value) bool { // match: (TESTBconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTB x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTB) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64TESTL_0(v *Value) bool { b := v.Block // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVLconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] v.reset(OpAMD64TESTLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := v.Args[_i0] if l.Op != OpAMD64MOVLload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] l2 := v.Args[1^_i0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTLconst_0(v *Value) bool { // match: (TESTLconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTL x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTL) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64TESTQ_0(v *Value) bool { b := v.Block // match: (TESTQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (TESTQconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVQconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(is32Bit(c)) { continue } v.reset(OpAMD64TESTQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := v.Args[_i0] if l.Op != OpAMD64MOVQload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] l2 := v.Args[1^_i0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTQconst_0(v *Value) bool { // match: (TESTQconst [-1] x) // cond: x.Op != OpAMD64MOVQconst // result: (TESTQ x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVQconst) { break } v.reset(OpAMD64TESTQ) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64TESTW_0(v *Value) bool { b := v.Block // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVLconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] v.reset(OpAMD64TESTWconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := v.Args[_i0] if l.Op != OpAMD64MOVWload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] l2 := v.Args[1^_i0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTWconst_0(v *Value) bool { // match: (TESTWconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTW x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTW) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64XADDLlock_0(v *Value) bool { // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XADDLlock [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XADDLlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XADDQlock_0(v *Value) bool { // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XADDQlock [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XADDQlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGL_0(v *Value) bool { // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XCHGL [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XCHGL) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux ptr := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGL) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGQ_0(v *Value) bool { // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XCHGQ [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux ptr := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XORL_0(v *Value) bool { // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { continue } x := v.Args[1^_i0] v.reset(OpAMD64BTCL) v.AddArg(x) v.AddArg(y) return true } break } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCLconst [log2uint32(c)] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVLconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } break } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVLconst { continue } c := v_1.AuxInt v.reset(OpAMD64XORLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRLconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRWconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRBconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XORL x x) // result: (MOVLconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVLload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64XORLconst_0(v *Value) bool { // match: (XORLconst [c] x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCLconst [log2uint32(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (XORLconst [1] (SETNE x)) // result: (SETEQ x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETNE { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (XORLconst [1] (SETEQ x)) // result: (SETNE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETEQ { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (XORLconst [1] (SETL x)) // result: (SETGE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETL { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (XORLconst [1] (SETGE x)) // result: (SETL x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETGE { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (XORLconst [1] (SETLE x)) // result: (SETG x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETLE { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (XORLconst [1] (SETG x)) // result: (SETLE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETG { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (XORLconst [1] (SETB x)) // result: (SETAE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETB { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (XORLconst [1] (SETAE x)) // result: (SETB x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETAE { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (XORLconst [1] (SETBE x)) // result: (SETA x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETBE { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64XORLconst_10(v *Value) bool { // match: (XORLconst [1] (SETA x)) // result: (SETBE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETA { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (XORLconst [c] (XORLconst [d] x)) // result: (XORLconst [c ^ d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64XORLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORLconst [c] (BTCLconst [d] x)) // result: (XORLconst [c ^ 1<= 128 // result: (BTCQconst [log2(c)] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVQconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCQconst) v.AuxInt = log2(c) v.AddArg(x) return true } break } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64XORQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLQconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRQconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XORQ x x) // result: (MOVQconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVQload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64XORQconst_0(v *Value) bool { // match: (XORQconst [c] x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCQconst [log2(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (XORQconst [c] (XORQconst [d] x)) // result: (XORQconst [c ^ d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64XORQconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64XORQconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORQconst [c] (BTCQconst [d] x)) // result: (XORQconst [c ^ 1< val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore64 ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore8 ptr val mem) // result: (Select1 (XCHGB val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStorePtrNoWB_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (AtomicStorePtrNoWB ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAvg64u_0(v *Value) bool { // match: (Avg64u x y) // result: (AVGQU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64AVGQU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpBitLen16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen16 x) // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) for { x := v.Args[0] v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = 1 v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v2.AddArg(x) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) for { x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) v1.AuxInt = 1 v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v2.AddArg(x) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) for { t := v.Type x := v.Args[0] v.reset(OpAMD64ADDQconst) v.AuxInt = 1 v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) v1 := b.NewValue0(v.Pos, OpSelect0, t) v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v3.AuxInt = -1 v0.AddArg(v3) v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v5 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v5.AddArg(x) v4.AddArg(v5) v0.AddArg(v4) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen8 x) // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) for { x := v.Args[0] v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = 1 v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v2.AddArg(x) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBswap32_0(v *Value) bool { // match: (Bswap32 x) // result: (BSWAPL x) for { x := v.Args[0] v.reset(OpAMD64BSWAPL) v.AddArg(x) return true } } func rewriteValueAMD64_OpBswap64_0(v *Value) bool { // match: (Bswap64 x) // result: (BSWAPQ x) for { x := v.Args[0] v.reset(OpAMD64BSWAPQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCeil_0(v *Value) bool { // match: (Ceil x) // result: (ROUNDSD [2] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 2 v.AddArg(x) return true } } func rewriteValueAMD64_OpClosureCall_0(v *Value) bool { // match: (ClosureCall [argwid] entry closure mem) // result: (CALLclosure [argwid] entry closure mem) for { argwid := v.AuxInt mem := v.Args[2] entry := v.Args[0] closure := v.Args[1] v.reset(OpAMD64CALLclosure) v.AuxInt = argwid v.AddArg(entry) v.AddArg(closure) v.AddArg(mem) return true } } func rewriteValueAMD64_OpCom16_0(v *Value) bool { // match: (Com16 x) // result: (NOTL x) for { x := v.Args[0] v.reset(OpAMD64NOTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCom32_0(v *Value) bool { // match: (Com32 x) // result: (NOTL x) for { x := v.Args[0] v.reset(OpAMD64NOTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCom64_0(v *Value) bool { // match: (Com64 x) // result: (NOTQ x) for { x := v.Args[0] v.reset(OpAMD64NOTQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCom8_0(v *Value) bool { // match: (Com8 x) // result: (NOTL x) for { x := v.Args[0] v.reset(OpAMD64NOTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCondSelect_0(v *Value) bool { // match: (CondSelect x y (SETEQ cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQ y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQ) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETL cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETG cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETA cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQHI y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQHI) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETB cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCC y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCC) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_10(v *Value) bool { // match: (CondSelect x y (SETEQF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGTF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGTF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is32BitInt(t) // result: (CMOVLEQ y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQ) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is32BitInt(t) // result: (CMOVLNE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is32BitInt(t) // result: (CMOVLLT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is32BitInt(t) // result: (CMOVLGT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is32BitInt(t) // result: (CMOVLLE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is32BitInt(t) // result: (CMOVLGE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_20(v *Value) bool { // match: (CondSelect x y (SETA cond)) // cond: is32BitInt(t) // result: (CMOVLHI y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLHI) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is32BitInt(t) // result: (CMOVLCS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is32BitInt(t) // result: (CMOVLCC y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCC) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is32BitInt(t) // result: (CMOVLLS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is32BitInt(t) // result: (CMOVLEQF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is32BitInt(t) // result: (CMOVLNEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is32BitInt(t) // result: (CMOVLGTF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGTF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is32BitInt(t) // result: (CMOVLGEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is16BitInt(t) // result: (CMOVWEQ y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQ) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is16BitInt(t) // result: (CMOVWNE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_30(v *Value) bool { // match: (CondSelect x y (SETL cond)) // cond: is16BitInt(t) // result: (CMOVWLT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is16BitInt(t) // result: (CMOVWGT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is16BitInt(t) // result: (CMOVWLE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is16BitInt(t) // result: (CMOVWGE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is16BitInt(t) // result: (CMOVWHI y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWHI) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is16BitInt(t) // result: (CMOVWCS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is16BitInt(t) // result: (CMOVWCC y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCC) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is16BitInt(t) // result: (CMOVWLS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is16BitInt(t) // result: (CMOVWEQF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is16BitInt(t) // result: (CMOVWNEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_40(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (CondSelect x y (SETGF cond)) // cond: is16BitInt(t) // result: (CMOVWGTF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGTF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is16BitInt(t) // result: (CMOVWGEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 1 // result: (CondSelect x y (MOVBQZX check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 1) { break } v.reset(OpCondSelect) v.Type = t v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64) v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 2 // result: (CondSelect x y (MOVWQZX check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 2) { break } v.reset(OpCondSelect) v.Type = t v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64) v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 4 // result: (CondSelect x y (MOVLQZX check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 4) { break } v.reset(OpCondSelect) v.Type = t v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x (CMPQconst [0] check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { break } v.reset(OpAMD64CMOVQNE) v.AddArg(y) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) // result: (CMOVLNE y x (CMPQconst [0] check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg(y) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) // result: (CMOVWNE y x (CMPQconst [0] check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg(y) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(check) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpConst16_0(v *Value) bool { // match: (Const16 [val]) // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst32_0(v *Value) bool { // match: (Const32 [val]) // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst32F_0(v *Value) bool { // match: (Const32F [val]) // result: (MOVSSconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVSSconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst64_0(v *Value) bool { // match: (Const64 [val]) // result: (MOVQconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst64F_0(v *Value) bool { // match: (Const64F [val]) // result: (MOVSDconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVSDconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst8_0(v *Value) bool { // match: (Const8 [val]) // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConstBool_0(v *Value) bool { // match: (ConstBool [b]) // result: (MOVLconst [b]) for { b := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = b return true } } func rewriteValueAMD64_OpConstNil_0(v *Value) bool { // match: (ConstNil) // result: (MOVQconst [0]) for { v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } } func rewriteValueAMD64_OpCtz16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (BSFL (BTSLconst [16] x)) for { x := v.Args[0] v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = 16 v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz16NonZero_0(v *Value) bool { // match: (Ctz16NonZero x) // result: (BSFL x) for { x := v.Args[0] v.reset(OpAMD64BSFL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCtz32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // result: (Select0 (BSFQ (BTSQconst [32] x))) for { x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) v1.AuxInt = 32 v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz32NonZero_0(v *Value) bool { // match: (Ctz32NonZero x) // result: (BSFL x) for { x := v.Args[0] v.reset(OpAMD64BSFL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCtz64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) for { t := v.Type x := v.Args[0] v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v2.AuxInt = 64 v.AddArg(v2) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v4.AddArg(x) v3.AddArg(v4) v.AddArg(v3) return true } } func rewriteValueAMD64_OpCtz64NonZero_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz64NonZero x) // result: (Select0 (BSFQ x)) for { x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (BSFL (BTSLconst [ 8] x)) for { x := v.Args[0] v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = 8 v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8NonZero_0(v *Value) bool { // match: (Ctz8NonZero x) // result: (BSFL x) for { x := v.Args[0] v.reset(OpAMD64BSFL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32Fto32_0(v *Value) bool { // match: (Cvt32Fto32 x) // result: (CVTTSS2SL x) for { x := v.Args[0] v.reset(OpAMD64CVTTSS2SL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32Fto64_0(v *Value) bool { // match: (Cvt32Fto64 x) // result: (CVTTSS2SQ x) for { x := v.Args[0] v.reset(OpAMD64CVTTSS2SQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32Fto64F_0(v *Value) bool { // match: (Cvt32Fto64F x) // result: (CVTSS2SD x) for { x := v.Args[0] v.reset(OpAMD64CVTSS2SD) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32to32F_0(v *Value) bool { // match: (Cvt32to32F x) // result: (CVTSL2SS x) for { x := v.Args[0] v.reset(OpAMD64CVTSL2SS) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32to64F_0(v *Value) bool { // match: (Cvt32to64F x) // result: (CVTSL2SD x) for { x := v.Args[0] v.reset(OpAMD64CVTSL2SD) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64Fto32_0(v *Value) bool { // match: (Cvt64Fto32 x) // result: (CVTTSD2SL x) for { x := v.Args[0] v.reset(OpAMD64CVTTSD2SL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64Fto32F_0(v *Value) bool { // match: (Cvt64Fto32F x) // result: (CVTSD2SS x) for { x := v.Args[0] v.reset(OpAMD64CVTSD2SS) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64Fto64_0(v *Value) bool { // match: (Cvt64Fto64 x) // result: (CVTTSD2SQ x) for { x := v.Args[0] v.reset(OpAMD64CVTTSD2SQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64to32F_0(v *Value) bool { // match: (Cvt64to32F x) // result: (CVTSQ2SS x) for { x := v.Args[0] v.reset(OpAMD64CVTSQ2SS) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64to64F_0(v *Value) bool { // match: (Cvt64to64F x) // result: (CVTSQ2SD x) for { x := v.Args[0] v.reset(OpAMD64CVTSQ2SD) v.AddArg(x) return true } } func rewriteValueAMD64_OpDiv128u_0(v *Value) bool { // match: (Div128u xhi xlo y) // result: (DIVQU2 xhi xlo y) for { y := v.Args[2] xhi := v.Args[0] xlo := v.Args[1] v.reset(OpAMD64DIVQU2) v.AddArg(xhi) v.AddArg(xlo) v.AddArg(y) return true } } func rewriteValueAMD64_OpDiv16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16 [a] x y) // result: (Select0 (DIVW [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv16u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (Select0 (DIVWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div32 [a] x y) // result: (Select0 (DIVL [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32F_0(v *Value) bool { // match: (Div32F x y) // result: (DIVSS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64DIVSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpDiv32u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div32u x y) // result: (Select0 (DIVLU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div64 [a] x y) // result: (Select0 (DIVQ [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64F_0(v *Value) bool { // match: (Div64F x y) // result: (DIVSD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64DIVSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpDiv64u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div64u x y) // result: (Select0 (DIVQU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq16_0(v *Value) bool { b := v.Block // match: (Eq16 x y) // result: (SETEQ (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32_0(v *Value) bool { b := v.Block // match: (Eq32 x y) // result: (SETEQ (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32F_0(v *Value) bool { b := v.Block // match: (Eq32F x y) // result: (SETEQF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64_0(v *Value) bool { b := v.Block // match: (Eq64 x y) // result: (SETEQ (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64F_0(v *Value) bool { b := v.Block // match: (Eq64F x y) // result: (SETEQF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq8_0(v *Value) bool { b := v.Block // match: (Eq8 x y) // result: (SETEQ (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqB_0(v *Value) bool { b := v.Block // match: (EqB x y) // result: (SETEQ (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqPtr_0(v *Value) bool { b := v.Block // match: (EqPtr x y) // result: (SETEQ (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpFMA_0(v *Value) bool { // match: (FMA x y z) // result: (VFMADD231SD z x y) for { z := v.Args[2] x := v.Args[0] y := v.Args[1] v.reset(OpAMD64VFMADD231SD) v.AddArg(z) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpFloor_0(v *Value) bool { // match: (Floor x) // result: (ROUNDSD [1] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValueAMD64_OpGeq16_0(v *Value) bool { b := v.Block // match: (Geq16 x y) // result: (SETGE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq16U_0(v *Value) bool { b := v.Block // match: (Geq16U x y) // result: (SETAE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq32_0(v *Value) bool { b := v.Block // match: (Geq32 x y) // result: (SETGE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq32F_0(v *Value) bool { b := v.Block // match: (Geq32F x y) // result: (SETGEF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq32U_0(v *Value) bool { b := v.Block // match: (Geq32U x y) // result: (SETAE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq64_0(v *Value) bool { b := v.Block // match: (Geq64 x y) // result: (SETGE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq64F_0(v *Value) bool { b := v.Block // match: (Geq64F x y) // result: (SETGEF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq64U_0(v *Value) bool { b := v.Block // match: (Geq64U x y) // result: (SETAE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq8_0(v *Value) bool { b := v.Block // match: (Geq8 x y) // result: (SETGE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq8U_0(v *Value) bool { b := v.Block // match: (Geq8U x y) // result: (SETAE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGetCallerPC_0(v *Value) bool { // match: (GetCallerPC) // result: (LoweredGetCallerPC) for { v.reset(OpAMD64LoweredGetCallerPC) return true } } func rewriteValueAMD64_OpGetCallerSP_0(v *Value) bool { // match: (GetCallerSP) // result: (LoweredGetCallerSP) for { v.reset(OpAMD64LoweredGetCallerSP) return true } } func rewriteValueAMD64_OpGetClosurePtr_0(v *Value) bool { // match: (GetClosurePtr) // result: (LoweredGetClosurePtr) for { v.reset(OpAMD64LoweredGetClosurePtr) return true } } func rewriteValueAMD64_OpGetG_0(v *Value) bool { // match: (GetG mem) // result: (LoweredGetG mem) for { mem := v.Args[0] v.reset(OpAMD64LoweredGetG) v.AddArg(mem) return true } } func rewriteValueAMD64_OpGreater16_0(v *Value) bool { b := v.Block // match: (Greater16 x y) // result: (SETG (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater16U_0(v *Value) bool { b := v.Block // match: (Greater16U x y) // result: (SETA (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater32_0(v *Value) bool { b := v.Block // match: (Greater32 x y) // result: (SETG (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater32F_0(v *Value) bool { b := v.Block // match: (Greater32F x y) // result: (SETGF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater32U_0(v *Value) bool { b := v.Block // match: (Greater32U x y) // result: (SETA (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater64_0(v *Value) bool { b := v.Block // match: (Greater64 x y) // result: (SETG (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater64F_0(v *Value) bool { b := v.Block // match: (Greater64F x y) // result: (SETGF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater64U_0(v *Value) bool { b := v.Block // match: (Greater64U x y) // result: (SETA (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater8_0(v *Value) bool { b := v.Block // match: (Greater8 x y) // result: (SETG (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater8U_0(v *Value) bool { b := v.Block // match: (Greater8U x y) // result: (SETA (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpHmul32_0(v *Value) bool { // match: (Hmul32 x y) // result: (HMULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpHmul32u_0(v *Value) bool { // match: (Hmul32u x y) // result: (HMULLU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULLU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpHmul64_0(v *Value) bool { // match: (Hmul64 x y) // result: (HMULQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpHmul64u_0(v *Value) bool { // match: (Hmul64u x y) // result: (HMULQU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULQU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpInterCall_0(v *Value) bool { // match: (InterCall [argwid] entry mem) // result: (CALLinter [argwid] entry mem) for { argwid := v.AuxInt mem := v.Args[1] entry := v.Args[0] v.reset(OpAMD64CALLinter) v.AuxInt = argwid v.AddArg(entry) v.AddArg(mem) return true } } func rewriteValueAMD64_OpIsInBounds_0(v *Value) bool { b := v.Block // match: (IsInBounds idx len) // result: (SETB (CMPQ idx len)) for { len := v.Args[1] idx := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsNonNil_0(v *Value) bool { b := v.Block // match: (IsNonNil p) // result: (SETNE (TESTQ p p)) for { p := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) v0.AddArg(p) v0.AddArg(p) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsSliceInBounds_0(v *Value) bool { b := v.Block // match: (IsSliceInBounds idx len) // result: (SETBE (CMPQ idx len)) for { len := v.Args[1] idx := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16_0(v *Value) bool { b := v.Block // match: (Leq16 x y) // result: (SETLE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16U_0(v *Value) bool { b := v.Block // match: (Leq16U x y) // result: (SETBE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32_0(v *Value) bool { b := v.Block // match: (Leq32 x y) // result: (SETLE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32F_0(v *Value) bool { b := v.Block // match: (Leq32F x y) // result: (SETGEF (UCOMISS y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32U_0(v *Value) bool { b := v.Block // match: (Leq32U x y) // result: (SETBE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64_0(v *Value) bool { b := v.Block // match: (Leq64 x y) // result: (SETLE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64F_0(v *Value) bool { b := v.Block // match: (Leq64F x y) // result: (SETGEF (UCOMISD y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64U_0(v *Value) bool { b := v.Block // match: (Leq64U x y) // result: (SETBE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8_0(v *Value) bool { b := v.Block // match: (Leq8 x y) // result: (SETLE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8U_0(v *Value) bool { b := v.Block // match: (Leq8U x y) // result: (SETBE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16_0(v *Value) bool { b := v.Block // match: (Less16 x y) // result: (SETL (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16U_0(v *Value) bool { b := v.Block // match: (Less16U x y) // result: (SETB (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32_0(v *Value) bool { b := v.Block // match: (Less32 x y) // result: (SETL (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32F_0(v *Value) bool { b := v.Block // match: (Less32F x y) // result: (SETGF (UCOMISS y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32U_0(v *Value) bool { b := v.Block // match: (Less32U x y) // result: (SETB (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64_0(v *Value) bool { b := v.Block // match: (Less64 x y) // result: (SETL (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64F_0(v *Value) bool { b := v.Block // match: (Less64F x y) // result: (SETGF (UCOMISD y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64U_0(v *Value) bool { b := v.Block // match: (Less64U x y) // result: (SETB (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8_0(v *Value) bool { b := v.Block // match: (Less8 x y) // result: (SETL (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8U_0(v *Value) bool { b := v.Block // match: (Less8U x y) // result: (SETB (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLoad_0(v *Value) bool { // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVQload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64MOVQload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) // result: (MOVLload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64MOVLload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64MOVWload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(OpAMD64MOVBload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitFloat(t)) { break } v.reset(OpAMD64MOVSSload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is64BitFloat(t)) { break } v.reset(OpAMD64MOVSDload) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpLocalAddr_0(v *Value) bool { // match: (LocalAddr {sym} base _) // result: (LEAQ {sym} base) for { sym := v.Aux _ = v.Args[1] base := v.Args[0] v.reset(OpAMD64LEAQ) v.Aux = sym v.AddArg(base) return true } } func rewriteValueAMD64_OpLsh16x16_0(v *Value) bool { b := v.Block // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh16x32_0(v *Value) bool { b := v.Block // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh16x64_0(v *Value) bool { b := v.Block // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh16x8_0(v *Value) bool { b := v.Block // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x16_0(v *Value) bool { b := v.Block // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x32_0(v *Value) bool { b := v.Block // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x64_0(v *Value) bool { b := v.Block // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x8_0(v *Value) bool { b := v.Block // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x16_0(v *Value) bool { b := v.Block // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x32_0(v *Value) bool { b := v.Block // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x64_0(v *Value) bool { b := v.Block // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x8_0(v *Value) bool { b := v.Block // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x16_0(v *Value) bool { b := v.Block // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x32_0(v *Value) bool { b := v.Block // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x64_0(v *Value) bool { b := v.Block // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x8_0(v *Value) bool { b := v.Block // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpMod16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod16 [a] x y) // result: (Select1 (DIVW [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod16u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Select1 (DIVWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod32 [a] x y) // result: (Select1 (DIVL [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (Select1 (DIVLU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod64 [a] x y) // result: (Select1 (DIVQ [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (Select1 (DIVQU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMove_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if v.AuxInt != 0 { break } mem := v.Args[2] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBload src mem) mem) for { if v.AuxInt != 1 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [2] dst src mem) // result: (MOVWstore dst (MOVWload src mem) mem) for { if v.AuxInt != 2 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVWstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [4] dst src mem) // result: (MOVLstore dst (MOVLload src mem) mem) for { if v.AuxInt != 4 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVLstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [8] dst src mem) // result: (MOVQstore dst (MOVQload src mem) mem) for { if v.AuxInt != 8 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVQstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [16] dst src mem) // cond: config.useSSE // result: (MOVOstore dst (MOVOload src mem) mem) for { if v.AuxInt != 16 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [16] dst src mem) // cond: !config.useSSE // result: (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 16 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [32] dst src mem) // result: (Move [16] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if v.AuxInt != 32 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpMove) v.AuxInt = 16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = 16 v2.AddArg(dst) v2.AddArg(src) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Move [48] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if v.AuxInt != 48 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = 32 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = 16 v2.AddArg(dst) v2.AddArg(src) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Move [64] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [32]) (OffPtr src [32]) (Move [32] dst src mem)) for { if v.AuxInt != 64 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = 32 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = 32 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = 32 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = 32 v2.AddArg(dst) v2.AddArg(src) v2.AddArg(mem) v.AddArg(v2) return true } return false } func rewriteValueAMD64_OpMove_10(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if v.AuxInt != 3 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AuxInt = 2 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = 2 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 5 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [6] dst src mem) // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 6 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVWstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [7] dst src mem) // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 7 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVLstore) v.AuxInt = 3 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = 3 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 9 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [10] dst src mem) // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 10 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVWstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [12] dst src mem) // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 12 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVLstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [s] dst src mem) // cond: s == 11 || s >= 13 && s <= 15 // result: (MOVQstore [s-8] dst (MOVQload [s-8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s == 11 || s >= 13 && s <= 15) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = s - 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = s - 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 <= 8 // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore dst (MOVQload src mem) mem)) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 16 && s%16 != 0 && s%16 <= 8) { break } v.reset(OpMove) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = s % 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = s % 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVOstore dst (MOVOload src mem) mem)) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE) { break } v.reset(OpMove) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = s % 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = s % 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } return false } func rewriteValueAMD64_OpMove_20(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE) { break } v.reset(OpMove) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = s % 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = s % 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AuxInt = 8 v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AuxInt = 8 v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v5.AddArg(src) v5.AddArg(mem) v4.AddArg(v5) v4.AddArg(mem) v2.AddArg(v4) v.AddArg(v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice // result: (DUFFCOPY [14*(64-s/16)] dst src mem) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFCOPY) v.AuxInt = 14 * (64 - s/16) v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } // match: (Move [s] dst src mem) // cond: (s > 16*64 || config.noDuffDevice) && s%8 == 0 // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !((s > 16*64 || config.noDuffDevice) && s%8 == 0) { break } v.reset(OpAMD64REPMOVSQ) v.AddArg(dst) v.AddArg(src) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = s / 8 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpMul16_0(v *Value) bool { // match: (Mul16 x y) // result: (MULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul32_0(v *Value) bool { // match: (Mul32 x y) // result: (MULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul32F_0(v *Value) bool { // match: (Mul32F x y) // result: (MULSS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul64_0(v *Value) bool { // match: (Mul64 x y) // result: (MULQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul64F_0(v *Value) bool { // match: (Mul64F x y) // result: (MULSD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul64uhilo_0(v *Value) bool { // match: (Mul64uhilo x y) // result: (MULQU2 x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULQU2) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul8_0(v *Value) bool { // match: (Mul8 x y) // result: (MULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpNeg16_0(v *Value) bool { // match: (Neg16 x) // result: (NEGL x) for { x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeg32_0(v *Value) bool { // match: (Neg32 x) // result: (NEGL x) for { x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeg32F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Neg32F x) // result: (PXOR x (MOVSSconst [auxFrom32F(float32(math.Copysign(0, -1)))])) for { x := v.Args[0] v.reset(OpAMD64PXOR) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) v0.AuxInt = auxFrom32F(float32(math.Copysign(0, -1))) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeg64_0(v *Value) bool { // match: (Neg64 x) // result: (NEGQ x) for { x := v.Args[0] v.reset(OpAMD64NEGQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeg64F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Neg64F x) // result: (PXOR x (MOVSDconst [auxFrom64F(math.Copysign(0, -1))])) for { x := v.Args[0] v.reset(OpAMD64PXOR) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) v0.AuxInt = auxFrom64F(math.Copysign(0, -1)) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeg8_0(v *Value) bool { // match: (Neg8 x) // result: (NEGL x) for { x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeq16_0(v *Value) bool { b := v.Block // match: (Neq16 x y) // result: (SETNE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32_0(v *Value) bool { b := v.Block // match: (Neq32 x y) // result: (SETNE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32F_0(v *Value) bool { b := v.Block // match: (Neq32F x y) // result: (SETNEF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64_0(v *Value) bool { b := v.Block // match: (Neq64 x y) // result: (SETNE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64F_0(v *Value) bool { b := v.Block // match: (Neq64F x y) // result: (SETNEF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq8_0(v *Value) bool { b := v.Block // match: (Neq8 x y) // result: (SETNE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqB_0(v *Value) bool { b := v.Block // match: (NeqB x y) // result: (SETNE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqPtr_0(v *Value) bool { b := v.Block // match: (NeqPtr x y) // result: (SETNE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNilCheck_0(v *Value) bool { // match: (NilCheck ptr mem) // result: (LoweredNilCheck ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpAMD64LoweredNilCheck) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValueAMD64_OpNot_0(v *Value) bool { // match: (Not x) // result: (XORLconst [1] x) for { x := v.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValueAMD64_OpOffPtr_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // cond: is32Bit(off) // result: (ADDQconst [off] ptr) for { off := v.AuxInt ptr := v.Args[0] if !(is32Bit(off)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = off v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDQ (MOVQconst [off]) ptr) for { off := v.AuxInt ptr := v.Args[0] v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = off v.AddArg(v0) v.AddArg(ptr) return true } } func rewriteValueAMD64_OpOr16_0(v *Value) bool { // match: (Or16 x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOr32_0(v *Value) bool { // match: (Or32 x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOr64_0(v *Value) bool { // match: (Or64 x y) // result: (ORQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOr8_0(v *Value) bool { // match: (Or8 x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOrB_0(v *Value) bool { // match: (OrB x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpPanicBounds_0(v *Value) bool { // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 0) { break } v.reset(OpAMD64LoweredPanicBoundsA) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 1) { break } v.reset(OpAMD64LoweredPanicBoundsB) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 2) { break } v.reset(OpAMD64LoweredPanicBoundsC) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpPopCount16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTL (MOVWQZX x)) for { x := v.Args[0] v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpPopCount32_0(v *Value) bool { // match: (PopCount32 x) // result: (POPCNTL x) for { x := v.Args[0] v.reset(OpAMD64POPCNTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpPopCount64_0(v *Value) bool { // match: (PopCount64 x) // result: (POPCNTQ x) for { x := v.Args[0] v.reset(OpAMD64POPCNTQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpPopCount8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTL (MOVBQZX x)) for { x := v.Args[0] v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpRotateLeft16_0(v *Value) bool { // match: (RotateLeft16 a b) // result: (ROLW a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLW) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRotateLeft32_0(v *Value) bool { // match: (RotateLeft32 a b) // result: (ROLL a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLL) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRotateLeft64_0(v *Value) bool { // match: (RotateLeft64 a b) // result: (ROLQ a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLQ) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRotateLeft8_0(v *Value) bool { // match: (RotateLeft8 a b) // result: (ROLB a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLB) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRound32F_0(v *Value) bool { // match: (Round32F x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpRound64F_0(v *Value) bool { // match: (Round64F x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpRoundToEven_0(v *Value) bool { // match: (RoundToEven x) // result: (ROUNDSD [0] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 0 v.AddArg(x) return true } } func rewriteValueAMD64_OpRsh16Ux16_0(v *Value) bool { b := v.Block // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16Ux32_0(v *Value) bool { b := v.Block // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16Ux64_0(v *Value) bool { b := v.Block // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16Ux8_0(v *Value) bool { b := v.Block // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x16_0(v *Value) bool { b := v.Block // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x32_0(v *Value) bool { b := v.Block // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x64_0(v *Value) bool { b := v.Block // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x8_0(v *Value) bool { b := v.Block // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux16_0(v *Value) bool { b := v.Block // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux32_0(v *Value) bool { b := v.Block // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux64_0(v *Value) bool { b := v.Block // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux8_0(v *Value) bool { b := v.Block // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x16_0(v *Value) bool { b := v.Block // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x32_0(v *Value) bool { b := v.Block // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x64_0(v *Value) bool { b := v.Block // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x8_0(v *Value) bool { b := v.Block // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux16_0(v *Value) bool { b := v.Block // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux32_0(v *Value) bool { b := v.Block // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux64_0(v *Value) bool { b := v.Block // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux8_0(v *Value) bool { b := v.Block // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x16_0(v *Value) bool { b := v.Block // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x32_0(v *Value) bool { b := v.Block // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x64_0(v *Value) bool { b := v.Block // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x8_0(v *Value) bool { b := v.Block // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux16_0(v *Value) bool { b := v.Block // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux32_0(v *Value) bool { b := v.Block // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux64_0(v *Value) bool { b := v.Block // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux8_0(v *Value) bool { b := v.Block // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x16_0(v *Value) bool { b := v.Block // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x32_0(v *Value) bool { b := v.Block // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x64_0(v *Value) bool { b := v.Block // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x8_0(v *Value) bool { b := v.Block // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpSelect0_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uover x y)) // result: (Select0 (MULQU x y)) for { v_0 := v.Args[0] if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (Select0 (Mul32uover x y)) // result: (Select0 (MULLU x y)) for { v_0 := v.Args[0] if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) for { v_0 := v.Args[0] if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y c)) // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) for { v_0 := v.Args[0] if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst32 val tuple)) // result: (ADDL val (Select0 tuple)) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDL) v.AddArg(val) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst64 val tuple)) // result: (ADDQ val (Select0 tuple)) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDQ) v.AddArg(val) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpSelect1_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uover x y)) // result: (SETO (Select1 (MULQU x y))) for { v_0 := v.Args[0] if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul32uover x y)) // result: (SETO (Select1 (MULLU x y))) for { v_0 := v.Args[0] if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Add64carry x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) for { v_0 := v.Args[0] if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v2.AddArg(y) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) for { v_0 := v.Args[0] if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v2.AddArg(y) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (NEGLflags (MOVQconst [0]))) // result: (FlagEQ) for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst || v_0_0.AuxInt != 0 { break } v.reset(OpAMD64FlagEQ) return true } // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) // result: x for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64SBBQcarrymask { break } x := v_0_0_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Select1 (AddTupleFirst32 _ tuple)) // result: (Select1 tuple) for { v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } // match: (Select1 (AddTupleFirst64 _ tuple)) // result: (Select1 tuple) for { v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } return false } func rewriteValueAMD64_OpSignExt16to32_0(v *Value) bool { // match: (SignExt16to32 x) // result: (MOVWQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt16to64_0(v *Value) bool { // match: (SignExt16to64 x) // result: (MOVWQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt32to64_0(v *Value) bool { // match: (SignExt32to64 x) // result: (MOVLQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt8to16_0(v *Value) bool { // match: (SignExt8to16 x) // result: (MOVBQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt8to32_0(v *Value) bool { // match: (SignExt8to32 x) // result: (MOVBQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt8to64_0(v *Value) bool { // match: (SignExt8to64 x) // result: (MOVBQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSlicemask_0(v *Value) bool { b := v.Block // match: (Slicemask x) // result: (SARQconst (NEGQ x) [63]) for { t := v.Type x := v.Args[0] v.reset(OpAMD64SARQconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpSqrt_0(v *Value) bool { // match: (Sqrt x) // result: (SQRTSD x) for { x := v.Args[0] v.reset(OpAMD64SQRTSD) v.AddArg(x) return true } } func rewriteValueAMD64_OpStaticCall_0(v *Value) bool { // match: (StaticCall [argwid] {target} mem) // result: (CALLstatic [argwid] {target} mem) for { argwid := v.AuxInt target := v.Aux mem := v.Args[0] v.reset(OpAMD64CALLstatic) v.AuxInt = argwid v.Aux = target v.AddArg(mem) return true } } func rewriteValueAMD64_OpStore_0(v *Value) bool { // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) // result: (MOVSDstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) // result: (MOVSSstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSSstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 // result: (MOVQstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8) { break } v.reset(OpAMD64MOVQstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 // result: (MOVLstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 4) { break } v.reset(OpAMD64MOVLstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 2 // result: (MOVWstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 2) { break } v.reset(OpAMD64MOVWstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 1 // result: (MOVBstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 1) { break } v.reset(OpAMD64MOVBstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpSub16_0(v *Value) bool { // match: (Sub16 x y) // result: (SUBL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub32_0(v *Value) bool { // match: (Sub32 x y) // result: (SUBL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub32F_0(v *Value) bool { // match: (Sub32F x y) // result: (SUBSS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub64_0(v *Value) bool { // match: (Sub64 x y) // result: (SUBQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub64F_0(v *Value) bool { // match: (Sub64F x y) // result: (SUBSD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub8_0(v *Value) bool { // match: (Sub8 x y) // result: (SUBL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSubPtr_0(v *Value) bool { // match: (SubPtr x y) // result: (SUBQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpTrunc_0(v *Value) bool { // match: (Trunc x) // result: (ROUNDSD [3] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 3 v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc16to8_0(v *Value) bool { // match: (Trunc16to8 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc32to16_0(v *Value) bool { // match: (Trunc32to16 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc32to8_0(v *Value) bool { // match: (Trunc32to8 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc64to16_0(v *Value) bool { // match: (Trunc64to16 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc64to32_0(v *Value) bool { // match: (Trunc64to32 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc64to8_0(v *Value) bool { // match: (Trunc64to8 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpWB_0(v *Value) bool { // match: (WB {fn} destptr srcptr mem) // result: (LoweredWB {fn} destptr srcptr mem) for { fn := v.Aux mem := v.Args[2] destptr := v.Args[0] srcptr := v.Args[1] v.reset(OpAMD64LoweredWB) v.Aux = fn v.AddArg(destptr) v.AddArg(srcptr) v.AddArg(mem) return true } } func rewriteValueAMD64_OpXor16_0(v *Value) bool { // match: (Xor16 x y) // result: (XORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpXor32_0(v *Value) bool { // match: (Xor32 x y) // result: (XORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpXor64_0(v *Value) bool { // match: (Xor64 x y) // result: (XORQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpXor8_0(v *Value) bool { // match: (Xor8 x y) // result: (XORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpZero_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (Zero [0] _ mem) // result: mem for { if v.AuxInt != 0 { break } mem := v.Args[1] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstoreconst [0] destptr mem) for { if v.AuxInt != 1 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVBstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [2] destptr mem) // result: (MOVWstoreconst [0] destptr mem) for { if v.AuxInt != 2 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVWstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [4] destptr mem) // result: (MOVLstoreconst [0] destptr mem) for { if v.AuxInt != 4 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVLstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [8] destptr mem) // result: (MOVQstoreconst [0] destptr mem) for { if v.AuxInt != 8 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVQstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [0] destptr mem)) for { if v.AuxInt != 3 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(0, 2) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [5] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 5 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [6] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 6 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [7] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 7 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(0, 3) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s%8 != 0 && s > 8 && !config.useSSE // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVQstoreconst [0] destptr mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s%8 != 0 && s > 8 && !config.useSSE) { break } v.reset(OpZero) v.AuxInt = s - s%8 v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = s % 8 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v.AddArg(v1) return true } return false } func rewriteValueAMD64_OpZero_10(v *Value) bool { b := v.Block config := b.Func.Config // match: (Zero [16] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem)) for { if v.AuxInt != 16 { break } mem := v.Args[1] destptr := v.Args[0] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, 8) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [24] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem))) for { if v.AuxInt != 24 { break } mem := v.Args[1] destptr := v.Args[0] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, 16) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = makeValAndOff(0, 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [32] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem)))) for { if v.AuxInt != 32 { break } mem := v.Args[1] destptr := v.Args[0] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, 24) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = makeValAndOff(0, 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = makeValAndOff(0, 8) v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v2.AuxInt = 0 v2.AddArg(destptr) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s > 8 && s < 16 && config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,s-8)] destptr (MOVQstoreconst [0] destptr mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s > 8 && s < 16 && config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, s-8) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstore destptr (MOVOconst [0]) mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = s % 16 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v2.AuxInt = 0 v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVQstoreconst [0] destptr mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = s % 16 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Zero [16] destptr mem) // cond: config.useSSE // result: (MOVOstore destptr (MOVOconst [0]) mem) for { if v.AuxInt != 16 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (Zero [32] destptr mem) // cond: config.useSSE // result: (MOVOstore (OffPtr destptr [16]) (MOVOconst [0]) (MOVOstore destptr (MOVOconst [0]) mem)) for { if v.AuxInt != 32 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = 16 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v2.AddArg(destptr) v3 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v3.AuxInt = 0 v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Zero [48] destptr mem) // cond: config.useSSE // result: (MOVOstore (OffPtr destptr [32]) (MOVOconst [0]) (MOVOstore (OffPtr destptr [16]) (MOVOconst [0]) (MOVOstore destptr (MOVOconst [0]) mem))) for { if v.AuxInt != 48 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = 32 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v3.AuxInt = 16 v3.AddArg(destptr) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v4.AuxInt = 0 v2.AddArg(v4) v5 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v5.AddArg(destptr) v6 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v6.AuxInt = 0 v5.AddArg(v6) v5.AddArg(mem) v2.AddArg(v5) v.AddArg(v2) return true } // match: (Zero [64] destptr mem) // cond: config.useSSE // result: (MOVOstore (OffPtr destptr [48]) (MOVOconst [0]) (MOVOstore (OffPtr destptr [32]) (MOVOconst [0]) (MOVOstore (OffPtr destptr [16]) (MOVOconst [0]) (MOVOstore destptr (MOVOconst [0]) mem)))) for { if v.AuxInt != 64 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = 48 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v3.AuxInt = 32 v3.AddArg(destptr) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v4.AuxInt = 0 v2.AddArg(v4) v5 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v6 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v6.AuxInt = 16 v6.AddArg(destptr) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v7.AuxInt = 0 v5.AddArg(v7) v8 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v8.AddArg(destptr) v9 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v9.AuxInt = 0 v8.AddArg(v9) v8.AddArg(mem) v5.AddArg(v8) v2.AddArg(v5) v.AddArg(v2) return true } return false } func rewriteValueAMD64_OpZero_20(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [s] destptr mem) // cond: s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice // result: (DUFFZERO [s] destptr (MOVOconst [0]) mem) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFZERO) v.AuxInt = s v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0 // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !((s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0) { break } v.reset(OpAMD64REPSTOSQ) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = s / 8 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = 0 v.AddArg(v1) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpZeroExt16to32_0(v *Value) bool { // match: (ZeroExt16to32 x) // result: (MOVWQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt16to64_0(v *Value) bool { // match: (ZeroExt16to64 x) // result: (MOVWQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt32to64_0(v *Value) bool { // match: (ZeroExt32to64 x) // result: (MOVLQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt8to16_0(v *Value) bool { // match: (ZeroExt8to16 x) // result: (MOVBQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt8to32_0(v *Value) bool { // match: (ZeroExt8to32 x) // result: (MOVBQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt8to64_0(v *Value) bool { // match: (ZeroExt8to64 x) // result: (MOVBQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } } func rewriteBlockAMD64(b *Block) bool { switch b.Kind { case BlockAMD64EQ: // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (UGE (BTLconst [log2uint32(c)] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64MOVQconst { continue } c := v_0_0.AuxInt x := v_0.Args[1^_i0] if !(isUint64PowerOfTwo(c)) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64EQ) b.AddControl(cmp) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64GE: // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LE) b.AddControl(cmp) return true } // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64GT: // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LT) b.AddControl(cmp) return true } // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockIf: // match: (If (SETL cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64SETL { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LT) b.AddControl(cmp) return true } // match: (If (SETLE cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64SETLE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LE) b.AddControl(cmp) return true } // match: (If (SETG cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64SETG { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GT) b.AddControl(cmp) return true } // match: (If (SETGE cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64SETGE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GE) b.AddControl(cmp) return true } // match: (If (SETEQ cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64SETEQ { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64EQ) b.AddControl(cmp) return true } // match: (If (SETNE cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64SETNE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64NE) b.AddControl(cmp) return true } // match: (If (SETB cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64SETB { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULT) b.AddControl(cmp) return true } // match: (If (SETBE cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64SETBE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULE) b.AddControl(cmp) return true } // match: (If (SETA cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETA { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (If (SETAE cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETAE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (If (SETO cmp) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64SETO { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64OS) b.AddControl(cmp) return true } // match: (If (SETGF cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETGF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (If (SETGEF cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETGEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (If (SETEQF cmp) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64SETEQF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64EQF) b.AddControl(cmp) return true } // match: (If (SETNEF cmp) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64SETNEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64NEF) b.AddControl(cmp) return true } // match: (If cond yes no) // result: (NE (TESTB cond cond) yes no) for { cond := b.Controls[0] b.Reset(BlockAMD64NE) v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) v0.AddArg(cond) v0.AddArg(cond) b.AddControl(v0) return true } case BlockAMD64LE: // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GE) b.AddControl(cmp) return true } // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64LT: // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GT) b.AddControl(cmp) return true } // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETL { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64LT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETLE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64LE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETG { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64GT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64GE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQ { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64EQ) b.AddControl(cmp) return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64NE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETB { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64ULT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETBE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64ULE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETA { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETAE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETO { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64OS) b.AddControl(cmp) return true } // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (ULT (BTLconst [log2uint32(c)] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64MOVQconst { continue } c := v_0_0.AuxInt x := v_0.Args[1^_i0] if !(isUint64PowerOfTwo(c)) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64EQF) b.AddControl(cmp) return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64NEF) b.AddControl(cmp) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64NE) b.AddControl(cmp) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGE: // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULE) b.AddControl(cmp) return true } // match: (UGE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (UGE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGT: // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULT) b.AddControl(cmp) return true } // match: (UGT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64ULE: // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (ULE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64ULT: // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (ULT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } diff-1.0.1/internal/benchmarks/testdata/medium.test000066400000000000000000000672001516001707200223500ustar00rootroot00000000000000From https://github.com/AnubhabB/diff-match-patch-rs-bench/tree/main/testdata -- x -- This is a '''list of newspapers published by [[Journal Register Company]]'''. The company owns daily and weekly newspapers, other print media properties and newspaper-affiliated local Websites in the [[U.S.]] states of [[Connecticut]], [[Michigan]], [[New York]], [[Ohio]] and [[Pennsylvania]], organized in six geographic "clusters":[http://www.journalregister.com/newspapers.html Journal Register Company: Our Newspapers], accessed February 10, 2008. == Capital-Saratoga == Three dailies, associated weeklies and [[pennysaver]]s in greater [[Albany, New York]]; also [http://www.capitalcentral.com capitalcentral.com] and [http://www.jobsinnewyork.com JobsInNewYork.com]. * ''The Oneida Daily Dispatch'' {{WS|oneidadispatch.com}} of [[Oneida, New York]] * ''[[The Record (Troy)|The Record]]'' {{WS|troyrecord.com}} of [[Troy, New York]] * ''[[The Saratogian]]'' {{WS|saratogian.com}} of [[Saratoga Springs, New York]] * Weeklies: ** ''Community News'' {{WS|cnweekly.com}} weekly of [[Clifton Park, New York]] ** ''Rome Observer'' of [[Rome, New York]] ** ''Life & Times of Utica'' of [[Utica, New York]] == Connecticut == Five dailies, associated weeklies and [[pennysaver]]s in the state of [[Connecticut]]; also [http://www.ctcentral.com CTcentral.com], [http://www.ctcarsandtrucks.com CTCarsAndTrucks.com] and [http://www.jobsinct.com JobsInCT.com]. * ''The Middletown Press'' {{WS|middletownpress.com}} of [[Middletown, Connecticut|Middletown]] * ''[[New Haven Register]]'' {{WS|newhavenregister.com}} of [[New Haven, Connecticut|New Haven]] * ''The Register Citizen'' {{WS|registercitizen.com}} of [[Torrington, Connecticut|Torrington]] * [[New Haven Register#Competitors|Elm City Newspapers]] {{WS|ctcentral.com}} ** ''The Advertiser'' of [[East Haven, Connecticut|East Haven]] ** ''Hamden Chronicle'' of [[Hamden, Connecticut|Hamden]] ** ''Milford Weekly'' of [[Milford, Connecticut|Milford]] ** ''The Orange Bulletin'' of [[Orange, Connecticut|Orange]] ** ''The Post'' of [[North Haven, Connecticut|North Haven]] ** ''Shelton Weekly'' of [[Shelton, Connecticut|Shelton]] ** ''The Stratford Bard'' of [[Stratford, Connecticut|Stratford]] ** ''Wallingford Voice'' of [[Wallingford, Connecticut|Wallingford]] ** ''West Haven News'' of [[West Haven, Connecticut|West Haven]] * Housatonic Publications ** ''The New Milford Times'' {{WS|newmilfordtimes.com}} of [[New Milford, Connecticut|New Milford]] ** ''The Brookfield Journal'' of [[Brookfield, Connecticut|Brookfield]] ** ''The Kent Good Times Dispatch'' of [[Kent, Connecticut|Kent]] ** ''The Bethel Beacon'' of [[Bethel, Connecticut|Bethel]] ** ''The Litchfield Enquirer'' of [[Litchfield, Connecticut|Litchfield]] ** ''Litchfield County Times'' of [[Litchfield, Connecticut|Litchfield]] * Imprint Newspapers {{WS|imprintnewspapers.com}} ** ''West Hartford News'' of [[West Hartford, Connecticut|West Hartford]] ** ''Windsor Journal'' of [[Windsor, Connecticut|Windsor]] ** ''Windsor Locks Journal'' of [[Windsor Locks, Connecticut|Windsor Locks]] ** ''Avon Post'' of [[Avon, Connecticut|Avon]] ** ''Farmington Post'' of [[Farmington, Connecticut|Farmington]] ** ''Simsbury Post'' of [[Simsbury, Connecticut|Simsbury]] ** ''Tri-Town Post'' of [[Burlington, Connecticut|Burlington]], [[Canton, Connecticut|Canton]] and [[Harwinton, Connecticut|Harwinton]] * Minuteman Publications ** ''[[Fairfield Minuteman]]'' of [[Fairfield, Connecticut|Fairfield]] ** ''The Westport Minuteman'' {{WS|westportminuteman.com}} of [[Westport, Connecticut|Westport]] * Shoreline Newspapers weeklies: ** ''Branford Review'' of [[Branford, Connecticut|Branford]] ** ''Clinton Recorder'' of [[Clinton, Connecticut|Clinton]] ** ''The Dolphin'' of [[Naval Submarine Base New London]] in [[New London, Connecticut|New London]] ** ''Main Street News'' {{WS|ctmainstreetnews.com}} of [[Essex, Connecticut|Essex]] ** ''Pictorial Gazette'' of [[Old Saybrook, Connecticut|Old Saybrook]] ** ''Regional Express'' of [[Colchester, Connecticut|Colchester]] ** ''Regional Standard'' of [[Colchester, Connecticut|Colchester]] ** ''Shoreline Times'' {{WS|shorelinetimes.com}} of [[Guilford, Connecticut|Guilford]] ** ''Shore View East'' of [[Madison, Connecticut|Madison]] ** ''Shore View West'' of [[Guilford, Connecticut|Guilford]] * Other weeklies: ** ''Registro'' {{WS|registroct.com}} of [[New Haven, Connecticut|New Haven]] ** ''Thomaston Express'' {{WS|thomastownexpress.com}} of [[Thomaston, Connecticut|Thomaston]] ** ''Foothills Traders'' {{WS|foothillstrader.com}} of Torrington, Bristol, Canton == Michigan == Four dailies, associated weeklies and [[pennysaver]]s in the state of [[Michigan]]; also [http://www.micentralhomes.com MIcentralhomes.com] and [http://www.micentralautos.com MIcentralautos.com] * ''[[Oakland Press]]'' {{WS|theoaklandpress.com}} of [[Oakland, Michigan|Oakland]] * ''Daily Tribune'' {{WS|dailytribune.com}} of [[Royal Oak, Michigan|Royal Oak]] * ''Macomb Daily'' {{WS|macombdaily.com}} of [[Mt. Clemens, Michigan|Mt. Clemens]] * ''[[Morning Sun]]'' {{WS|themorningsun.com}} of [[Mount Pleasant, Michigan|Mount Pleasant]] * Heritage Newspapers {{WS|heritage.com}} ** ''Belleville View'' ** ''Ile Camera'' ** ''Monroe Guardian'' ** ''Ypsilanti Courier'' ** ''News-Herald'' ** ''Press & Guide'' ** ''Chelsea Standard & Dexter Leader'' ** ''Manchester Enterprise'' ** ''Milan News-Leader'' ** ''Saline Reporter'' * Independent Newspapers {{WS|sourcenewspapers.com}} ** ''Advisor'' ** ''Source'' * Morning Star {{WS|morningstarpublishing.com}} ** ''Alma Reminder'' ** ''Alpena Star'' ** ''Antrim County News'' ** ''Carson City Reminder'' ** ''The Leader & Kalkaskian'' ** ''Ogemaw/Oscoda County Star'' ** ''Petoskey/Charlevoix Star'' ** ''Presque Isle Star'' ** ''Preview Community Weekly'' ** ''Roscommon County Star'' ** ''St. Johns Reminder'' ** ''Straits Area Star'' ** ''The (Edmore) Advertiser'' * Voice Newspapers {{WS|voicenews.com}} ** ''Armada Times'' ** ''Bay Voice'' ** ''Blue Water Voice'' ** ''Downriver Voice'' ** ''Macomb Township Voice'' ** ''North Macomb Voice'' ** ''Weekend Voice'' ** ''Suburban Lifestyles'' {{WS|suburbanlifestyles.com}} == Mid-Hudson == One daily, associated magazines in the [[Hudson River Valley]] of [[New York]]; also [http://www.midhudsoncentral.com MidHudsonCentral.com] and [http://www.jobsinnewyork.com JobsInNewYork.com]. * ''[[Daily Freeman]]'' {{WS|dailyfreeman.com}} of [[Kingston, New York]] == Ohio == Two dailies, associated magazines and three shared Websites, all in the state of [[Ohio]]: [http://www.allaroundcleveland.com AllAroundCleveland.com], [http://www.allaroundclevelandcars.com AllAroundClevelandCars.com] and [http://www.allaroundclevelandjobs.com AllAroundClevelandJobs.com]. * ''[[The News-Herald (Ohio)|The News-Herald]]'' {{WS|news-herald.com}} of [[Willoughby, Ohio|Willoughby]] * ''[[The Morning Journal]]'' {{WS|morningjournal.com}} of [[Lorain, Ohio|Lorain]] == Philadelphia area == Seven dailies and associated weeklies and magazines in [[Pennsylvania]] and [[New Jersey]], and associated Websites: [http://www.allaroundphilly.com AllAroundPhilly.com], [http://www.jobsinnj.com JobsInNJ.com], [http://www.jobsinpa.com JobsInPA.com], and [http://www.phillycarsearch.com PhillyCarSearch.com]. * ''The Daily Local'' {{WS|dailylocal.com}} of [[West Chester, Pennsylvania|West Chester]] * ''[[Delaware County Daily and Sunday Times]] {{WS|delcotimes.com}} of Primos * ''[[The Mercury (Pennsylvania)|The Mercury]]'' {{WS|pottstownmercury.com}} of [[Pottstown, Pennsylvania|Pottstown]] * ''The Phoenix'' {{WS|phoenixvillenews.com}} of [[Phoenixville, Pennsylvania|Phoenixville]] * ''[[The Reporter (Lansdale)|The Reporter]]'' {{WS|thereporteronline.com}} of [[Lansdale, Pennsylvania|Lansdale]] * ''The Times Herald'' {{WS|timesherald.com}} of [[Norristown, Pennsylvania|Norristown]] * ''[[The Trentonian]]'' {{WS|trentonian.com}} of [[Trenton, New Jersey]] * Weeklies ** ''El Latino Expreso'' of [[Trenton, New Jersey]] ** ''La Voz'' of [[Norristown, Pennsylvania]] ** ''The Village News'' of [[Downingtown, Pennsylvania]] ** ''The Times Record'' of [[Kennett Square, Pennsylvania]] ** ''The Tri-County Record'' {{WS|tricountyrecord.com}} of [[Morgantown, Pennsylvania]] ** ''News of Delaware County'' {{WS|newsofdelawarecounty.com}}of [[Havertown, Pennsylvania]] ** ''Main Line Times'' {{WS|mainlinetimes.com}}of [[Ardmore, Pennsylvania]] ** ''Penny Pincher'' of [[Pottstown, Pennsylvania]] ** ''Town Talk'' {{WS|towntalknews.com}} of [[Ridley, Pennsylvania]] * Chesapeake Publishing {{WS|pa8newsgroup.com}} ** ''Solanco Sun Ledger'' of [[Quarryville, Pennsylvania]] ** ''Columbia Ledger'' of [[Columbia, Pennsylvania]] ** ''Coatesville Ledger'' of [[Downingtown, Pennsylvania]] ** ''Parkesburg Post Ledger'' of [[Quarryville, Pennsylvania]] ** ''Downingtown Ledger'' of [[Downingtown, Pennsylvania]] ** ''The Kennett Paper'' of [[Kennett Square, Pennsylvania]] ** ''Avon Grove Sun'' of [[West Grove, Pennsylvania]] ** ''Oxford Tribune'' of [[Oxford, Pennsylvania]] ** ''Elizabethtown Chronicle'' of [[Elizabethtown, Pennsylvania]] ** ''Donegal Ledger'' of [[Donegal, Pennsylvania]] ** ''Chadds Ford Post'' of [[Chadds Ford, Pennsylvania]] ** ''The Central Record'' of [[Medford, New Jersey]] ** ''Maple Shade Progress'' of [[Maple Shade, New Jersey]] * Intercounty Newspapers {{WS|buckslocalnews.com}} ** ''The Review'' of Roxborough, Pennsylvania ** ''The Recorder'' of [[Conshohocken, Pennsylvania]] ** ''The Leader'' of [[Mount Airy, Pennsylvania|Mount Airy]] and West Oak Lake, Pennsylvania ** ''The Pennington Post'' of [[Pennington, New Jersey]] ** ''The Bristol Pilot'' of [[Bristol, Pennsylvania]] ** ''Yardley News'' of [[Yardley, Pennsylvania]] ** ''New Hope Gazette'' of [[New Hope, Pennsylvania]] ** ''Doylestown Patriot'' of [[Doylestown, Pennsylvania]] ** ''Newtown Advance'' of [[Newtown, Pennsylvania]] ** ''The Plain Dealer'' of [[Williamstown, New Jersey]] ** ''News Report'' of [[Sewell, New Jersey]] ** ''Record Breeze'' of [[Berlin, New Jersey]] ** ''Newsweekly'' of [[Moorestown, New Jersey]] ** ''Haddon Herald'' of [[Haddonfield, New Jersey]] ** ''New Egypt Press'' of [[New Egypt, New Jersey]] ** ''Community News'' of [[Pemberton, New Jersey]] ** ''Plymouth Meeting Journal'' of [[Plymouth Meeting, Pennsylvania]] ** ''Lafayette Hill Journal'' of [[Lafayette Hill, Pennsylvania]] * Montgomery Newspapers {{WS|montgomerynews.com}} ** ''Ambler Gazette'' of [[Ambler, Pennsylvania]] ** ''Central Bucks Life'' of [[Bucks County, Pennsylvania]] ** ''The Colonial'' of [[Plymouth Meeting, Pennsylvania]] ** ''Glenside News'' of [[Glenside, Pennsylvania]] ** ''The Globe'' of [[Lower Moreland Township, Pennsylvania]] ** ''Main Line Life'' of [[Ardmore, Pennsylvania]] ** ''Montgomery Life'' of [[Fort Washington, Pennsylvania]] ** ''North Penn Life'' of [[Lansdale, Pennsylvania]] ** ''Perkasie News Herald'' of [[Perkasie, Pennsylvania]] ** ''Public Spirit'' of [[Hatboro, Pennsylvania]] ** ''Souderton Independent'' of [[Souderton, Pennsylvania]] ** ''Springfield Sun'' of [[Springfield, Pennsylvania]] ** ''Spring-Ford Reporter'' of [[Royersford, Pennsylvania]] ** ''Times Chronicle'' of [[Jenkintown, Pennsylvania]] ** ''Valley Item'' of [[Perkiomenville, Pennsylvania]] ** ''Willow Grove Guide'' of [[Willow Grove, Pennsylvania]] * News Gleaner Publications (closed December 2008) {{WS|newsgleaner.com}} ** ''Life Newspapers'' of [[Philadelphia, Pennsylvania]] * Suburban Publications ** ''The Suburban & Wayne Times'' {{WS|waynesuburban.com}} of [[Wayne, Pennsylvania]] ** ''The Suburban Advertiser'' of [[Exton, Pennsylvania]] ** ''The King of Prussia Courier'' of [[King of Prussia, Pennsylvania]] * Press Newspapers {{WS|countypressonline.com}} ** ''County Press'' of [[Newtown Square, Pennsylvania]] ** ''Garnet Valley Press'' of [[Glen Mills, Pennsylvania]] ** ''Haverford Press'' of [[Newtown Square, Pennsylvania]] (closed January 2009) ** ''Hometown Press'' of [[Glen Mills, Pennsylvania]] (closed January 2009) ** ''Media Press'' of [[Newtown Square, Pennsylvania]] (closed January 2009) ** ''Springfield Press'' of [[Springfield, Pennsylvania]] * Berks-Mont Newspapers {{WS|berksmontnews.com}} ** ''The Boyertown Area Times'' of [[Boyertown, Pennsylvania]] ** ''The Kutztown Area Patriot'' of [[Kutztown, Pennsylvania]] ** ''The Hamburg Area Item'' of [[Hamburg, Pennsylvania]] ** ''The Southern Berks News'' of [[Exeter Township, Berks County, Pennsylvania]] ** ''The Free Press'' of [[Quakertown, Pennsylvania]] ** ''The Saucon News'' of [[Quakertown, Pennsylvania]] ** ''Westside Weekly'' of [[Reading, Pennsylvania]] * Magazines ** ''Bucks Co. Town & Country Living'' ** ''Chester Co. Town & Country Living'' ** ''Montomgery Co. Town & Country Living'' ** ''Garden State Town & Country Living'' ** ''Montgomery Homes'' ** ''Philadelphia Golfer'' ** ''Parents Express'' ** ''Art Matters'' {{JRC}} * Let's checkout Unicodes Here's a long text with a variety of emoticons, broken into multiple paragraphs: ** Paragraph 1 Hey there! 🙂 I'm so excited to share this text with you! 🤩 It's going to be a wild ride 🎢 full of emotions 😂 and fun 🎉. We'll have some serious moments 🤔, some silly moments 🤪, and some moments that will make you go "huh?" 🤔. ** Paragraph 2 Let's start with some basics 😊. We've got your standard smiley face 🙂, your sad face ☹️, and your angry face 😠. But wait, there's more! 🤩 We've also got some more complex emotions like 😍, 🤤, and 🚀. And let's not forget about the classics: 😉, 👍, and 👏. ** Paragraph 3 Now, let's get a little crazy 🤪! 🎉🎉🎉🎉🎉🎉🎉🎉🎉🎉🎉👯‍♀️🕺 We've got emojis for every occasion 🎂, every emotion 🤣, and every interest 🎨. Want to talk about food? 🍔🍕🥤 We've got emojis for that! Want to talk about travel? 🗺️🛫️ We've got emojis for that too! ** Paragraph 4 But wait, there's more! 🤯 We've also got some more obscure emojis 🤔. Like, have you ever seen this one? 🚯 Or this one? 🛂️ What about this one? 🤷‍♂️ Yeah, we've got all those and more! ** Paragraph 5 So, there you have it! 🎉 A text full of emojis, fun, and excitement 🤩. We hope you enjoyed the ride 🎢 and will join us again soon 🤗. Until next time, stay emoji-tastic! 😄👋 Note: I've used a variety of emojis, including: - Smiley faces and emotions (e.g., 🙂, 😂, 🤔) - Objects (e.g., 🎉, 🎂, 🍔) - Animals (e.g., 🐶, 🐱) - Symbols (e.g., 👍, 👏) - Flags (e.g., 🇺🇸, 🇬🇧) - And more! 🤯 ==References== [[Category:Journal Register publications|*]] -- y -- This is a '''list of newspapers published by [[Journal Register Company]]'''. The company owns daily and weekly newspapers, other print media properties and newspaper-affiliated local Websites in the [[U.S.]] states of [[Connecticut]], [[Michigan]], [[New York]], [[Ohio]], [[Pennsylvania]] and [[New Jersey]], organized in six geographic "clusters":[http://www.journalregister.com/publications.html Journal Register Company: Our Publications], accessed April 21, 2010. == Capital-Saratoga == Three dailies, associated weeklies and [[pennysaver]]s in greater [[Albany, New York]]; also [http://www.capitalcentral.com capitalcentral.com] and [http://www.jobsinnewyork.com JobsInNewYork.com]. * ''The Oneida Daily Dispatch'' {{WS|oneidadispatch.com}} of [[Oneida, New York]] * ''[[The Record (Troy)|The Record]]'' {{WS|troyrecord.com}} of [[Troy, New York]] * ''[[The Saratogian]]'' {{WS|saratogian.com}} of [[Saratoga Springs, New York]] * Weeklies: ** ''Community News'' {{WS|cnweekly.com}} weekly of [[Clifton Park, New York]] ** ''Rome Observer'' {{WS|romeobserver.com}} of [[Rome, New York]] ** ''WG Life '' {{WS|saratogian.com/wglife/}} of [[Wilton, New York]] ** ''Ballston Spa Life '' {{WS|saratogian.com/bspalife}} of [[Ballston Spa, New York]] ** ''Greenbush Life'' {{WS|troyrecord.com/greenbush}} of [[Troy, New York]] ** ''Latham Life'' {{WS|troyrecord.com/latham}} of [[Latham, New York]] ** ''River Life'' {{WS|troyrecord.com/river}} of [[Troy, New York]] == Connecticut == Three dailies, associated weeklies and [[pennysaver]]s in the state of [[Connecticut]]; also [http://www.ctcentral.com CTcentral.com], [http://www.ctcarsandtrucks.com CTCarsAndTrucks.com] and [http://www.jobsinct.com JobsInCT.com]. * ''The Middletown Press'' {{WS|middletownpress.com}} of [[Middletown, Connecticut|Middletown]] * ''[[New Haven Register]]'' {{WS|newhavenregister.com}} of [[New Haven, Connecticut|New Haven]] * ''The Register Citizen'' {{WS|registercitizen.com}} of [[Torrington, Connecticut|Torrington]] * Housatonic Publications ** ''The Housatonic Times'' {{WS|housatonictimes.com}} of [[New Milford, Connecticut|New Milford]] ** ''Litchfield County Times'' {{WS|countytimes.com}} of [[Litchfield, Connecticut|Litchfield]] * Minuteman Publications ** ''[[Fairfield Minuteman]]'' {{WS|fairfieldminuteman.com}}of [[Fairfield, Connecticut|Fairfield]] ** ''The Westport Minuteman'' {{WS|westportminuteman.com}} of [[Westport, Connecticut|Westport]] * Shoreline Newspapers ** ''The Dolphin'' {{WS|dolphin-news.com}} of [[Naval Submarine Base New London]] in [[New London, Connecticut|New London]] ** ''Shoreline Times'' {{WS|shorelinetimes.com}} of [[Guilford, Connecticut|Guilford]] * Foothills Media Group {{WS|foothillsmediagroup.com}} ** ''Thomaston Express'' {{WS|thomastonexpress.com}} of [[Thomaston, Connecticut|Thomaston]] ** ''Good News About Torrington'' {{WS|goodnewsabouttorrington.com}} of [[Torrington, Connecticut|Torrington]] ** ''Granby News'' {{WS|foothillsmediagroup.com/granby}} of [[Granby, Connecticut|Granby]] ** ''Canton News'' {{WS|foothillsmediagroup.com/canton}} of [[Canton, Connecticut|Canton]] ** ''Avon News'' {{WS|foothillsmediagroup.com/avon}} of [[Avon, Connecticut|Avon]] ** ''Simsbury News'' {{WS|foothillsmediagroup.com/simsbury}} of [[Simsbury, Connecticut|Simsbury]] ** ''Litchfield News'' {{WS|foothillsmediagroup.com/litchfield}} of [[Litchfield, Connecticut|Litchfield]] ** ''Foothills Trader'' {{WS|foothillstrader.com}} of Torrington, Bristol, Canton * Other weeklies ** ''The Milford-Orange Bulletin'' {{WS|ctbulletin.com}} of [[Orange, Connecticut|Orange]] ** ''The Post-Chronicle'' {{WS|ctpostchronicle.com}} of [[North Haven, Connecticut|North Haven]] ** ''West Hartford News'' {{WS|westhartfordnews.com}} of [[West Hartford, Connecticut|West Hartford]] * Magazines ** ''The Connecticut Bride'' {{WS|connecticutmag.com}} ** ''Connecticut Magazine'' {{WS|theconnecticutbride.com}} ** ''Passport Magazine'' {{WS|passport-mag.com}} == Michigan == Four dailies, associated weeklies and [[pennysaver]]s in the state of [[Michigan]]; also [http://www.micentralhomes.com MIcentralhomes.com] and [http://www.micentralautos.com MIcentralautos.com] * ''[[Oakland Press]]'' {{WS|theoaklandpress.com}} of [[Oakland, Michigan|Oakland]] * ''Daily Tribune'' {{WS|dailytribune.com}} of [[Royal Oak, Michigan|Royal Oak]] * ''Macomb Daily'' {{WS|macombdaily.com}} of [[Mt. Clemens, Michigan|Mt. Clemens]] * ''[[Morning Sun]]'' {{WS|themorningsun.com}} of [[Mount Pleasant, Michigan|Mount Pleasant]] * Heritage Newspapers {{WS|heritage.com}} ** ''Belleville View'' {{WS|bellevilleview.com}} ** ''Ile Camera'' {{WS|thenewsherald.com/ile_camera}} ** ''Monroe Guardian'' {{WS|monreguardian.com}} ** ''Ypsilanti Courier'' {{WS|ypsilanticourier.com}} ** ''News-Herald'' {{WS|thenewsherald.com}} ** ''Press & Guide'' {{WS|pressandguide.com}} ** ''Chelsea Standard & Dexter Leader'' {{WS|chelseastandard.com}} ** ''Manchester Enterprise'' {{WS|manchesterguardian.com}} ** ''Milan News-Leader'' {{WS|milannews.com}} ** ''Saline Reporter'' {{WS|salinereporter.com}} * Independent Newspapers ** ''Advisor'' {{WS|sourcenewspapers.com}} ** ''Source'' {{WS|sourcenewspapers.com}} * Morning Star {{WS|morningstarpublishing.com}} ** ''The Leader & Kalkaskian'' {{WS|leaderandkalkaskian.com}} ** ''Grand Traverse Insider'' {{WS|grandtraverseinsider.com}} ** ''Alma Reminder'' ** ''Alpena Star'' ** ''Ogemaw/Oscoda County Star'' ** ''Presque Isle Star'' ** ''St. Johns Reminder'' * Voice Newspapers {{WS|voicenews.com}} ** ''Armada Times'' ** ''Bay Voice'' ** ''Blue Water Voice'' ** ''Downriver Voice'' ** ''Macomb Township Voice'' ** ''North Macomb Voice'' ** ''Weekend Voice'' == Mid-Hudson == One daily, associated magazines in the [[Hudson River Valley]] of [[New York]]; also [http://www.midhudsoncentral.com MidHudsonCentral.com] and [http://www.jobsinnewyork.com JobsInNewYork.com]. * ''[[Daily Freeman]]'' {{WS|dailyfreeman.com}} of [[Kingston, New York]] * ''Las Noticias'' {{WS|lasnoticiasny.com}} of [[Kingston, New York]] == Ohio == Two dailies, associated magazines and three shared Websites, all in the state of [[Ohio]]: [http://www.allaroundcleveland.com AllAroundCleveland.com], [http://www.allaroundclevelandcars.com AllAroundClevelandCars.com] and [http://www.allaroundclevelandjobs.com AllAroundClevelandJobs.com]. * ''[[The News-Herald (Ohio)|The News-Herald]]'' {{WS|news-herald.com}} of [[Willoughby, Ohio|Willoughby]] * ''[[The Morning Journal]]'' {{WS|morningjournal.com}} of [[Lorain, Ohio|Lorain]] * ''El Latino Expreso'' {{WS|lorainlatino.com}} of [[Lorain, Ohio|Lorain]] == Philadelphia area == Seven dailies and associated weeklies and magazines in [[Pennsylvania]] and [[New Jersey]], and associated Websites: [http://www.allaroundphilly.com AllAroundPhilly.com], [http://www.jobsinnj.com JobsInNJ.com], [http://www.jobsinpa.com JobsInPA.com], and [http://www.phillycarsearch.com PhillyCarSearch.com]. * ''[[The Daily Local News]]'' {{WS|dailylocal.com}} of [[West Chester, Pennsylvania|West Chester]] * ''[[Delaware County Daily and Sunday Times]] {{WS|delcotimes.com}} of Primos [[Upper Darby Township, Pennsylvania]] * ''[[The Mercury (Pennsylvania)|The Mercury]]'' {{WS|pottstownmercury.com}} of [[Pottstown, Pennsylvania|Pottstown]] * ''[[The Reporter (Lansdale)|The Reporter]]'' {{WS|thereporteronline.com}} of [[Lansdale, Pennsylvania|Lansdale]] * ''The Times Herald'' {{WS|timesherald.com}} of [[Norristown, Pennsylvania|Norristown]] * ''[[The Trentonian]]'' {{WS|trentonian.com}} of [[Trenton, New Jersey]] * Weeklies * ''The Phoenix'' {{WS|phoenixvillenews.com}} of [[Phoenixville, Pennsylvania]] ** ''El Latino Expreso'' {{WS|njexpreso.com}} of [[Trenton, New Jersey]] ** ''La Voz'' {{WS|lavozpa.com}} of [[Norristown, Pennsylvania]] ** ''The Tri County Record'' {{WS|tricountyrecord.com}} of [[Morgantown, Pennsylvania]] ** ''Penny Pincher'' {{WS|pennypincherpa.com}}of [[Pottstown, Pennsylvania]] * Chesapeake Publishing {{WS|southernchestercountyweeklies.com}} ** ''The Kennett Paper'' {{WS|kennettpaper.com}} of [[Kennett Square, Pennsylvania]] ** ''Avon Grove Sun'' {{WS|avongrovesun.com}} of [[West Grove, Pennsylvania]] ** ''The Central Record'' {{WS|medfordcentralrecord.com}} of [[Medford, New Jersey]] ** ''Maple Shade Progress'' {{WS|mapleshadeprogress.com}} of [[Maple Shade, New Jersey]] * Intercounty Newspapers {{WS|buckslocalnews.com}} {{WS|southjerseylocalnews.com}} ** ''The Pennington Post'' {{WS|penningtonpost.com}} of [[Pennington, New Jersey]] ** ''The Bristol Pilot'' {{WS|bristolpilot.com}} of [[Bristol, Pennsylvania]] ** ''Yardley News'' {{WS|yardleynews.com}} of [[Yardley, Pennsylvania]] ** ''Advance of Bucks County'' {{WS|advanceofbucks.com}} of [[Newtown, Pennsylvania]] ** ''Record Breeze'' {{WS|recordbreeze.com}} of [[Berlin, New Jersey]] ** ''Community News'' {{WS|sjcommunitynews.com}} of [[Pemberton, New Jersey]] * Montgomery Newspapers {{WS|montgomerynews.com}} ** ''Ambler Gazette'' {{WS|amblergazette.com}} of [[Ambler, Pennsylvania]] ** ''The Colonial'' {{WS|colonialnews.com}} of [[Plymouth Meeting, Pennsylvania]] ** ''Glenside News'' {{WS|glensidenews.com}} of [[Glenside, Pennsylvania]] ** ''The Globe'' {{WS|globenewspaper.com}} of [[Lower Moreland Township, Pennsylvania]] ** ''Montgomery Life'' {{WS|montgomerylife.com}} of [[Fort Washington, Pennsylvania]] ** ''North Penn Life'' {{WS|northpennlife.com}} of [[Lansdale, Pennsylvania]] ** ''Perkasie News Herald'' {{WS|perkasienewsherald.com}} of [[Perkasie, Pennsylvania]] ** ''Public Spirit'' {{WS|thepublicspirit.com}} of [[Hatboro, Pennsylvania]] ** ''Souderton Independent'' {{WS|soudertonindependent.com}} of [[Souderton, Pennsylvania]] ** ''Springfield Sun'' {{WS|springfieldsun.com}} of [[Springfield, Pennsylvania]] ** ''Spring-Ford Reporter'' {{WS|springfordreporter.com}} of [[Royersford, Pennsylvania]] ** ''Times Chronicle'' {{WS|thetimeschronicle.com}} of [[Jenkintown, Pennsylvania]] ** ''Valley Item'' {{WS|valleyitem.com}} of [[Perkiomenville, Pennsylvania]] ** ''Willow Grove Guide'' {{WS|willowgroveguide.com}} of [[Willow Grove, Pennsylvania]] ** ''The Review'' {{WS|roxreview.com}} of [[Roxborough, Philadelphia, Pennsylvania]] * Main Line Media News {{WS|mainlinemedianews.com}} ** ''Main Line Times'' {{WS|mainlinetimes.com}} of [[Ardmore, Pennsylvania]] ** ''Main Line Life'' {{WS|mainlinelife.com}} of [[Ardmore, Pennsylvania]] ** ''The King of Prussia Courier'' {{WS|kingofprussiacourier.com}} of [[King of Prussia, Pennsylvania]] * Delaware County News Network {{WS|delconewsnetwork.com}} ** ''News of Delaware County'' {{WS|newsofdelawarecounty.com}} of [[Havertown, Pennsylvania]] ** ''County Press'' {{WS|countypressonline.com}} of [[Newtown Square, Pennsylvania]] ** ''Garnet Valley Press'' {{WS|countypressonline.com}} of [[Glen Mills, Pennsylvania]] ** ''Springfield Press'' {{WS|countypressonline.com}} of [[Springfield, Pennsylvania]] ** ''Town Talk'' {{WS|towntalknews.com}} of [[Ridley, Pennsylvania]] * Berks-Mont Newspapers {{WS|berksmontnews.com}} ** ''The Boyertown Area Times'' {{WS|berksmontnews.com/boyertown_area_times}} of [[Boyertown, Pennsylvania]] ** ''The Kutztown Area Patriot'' {{WS|berksmontnews.com/kutztown_area_patriot}} of [[Kutztown, Pennsylvania]] ** ''The Hamburg Area Item'' {{WS|berksmontnews.com/hamburg_area_item}} of [[Hamburg, Pennsylvania]] ** ''The Southern Berks News'' {{WS|berksmontnews.com/southern_berks_news}} of [[Exeter Township, Berks County, Pennsylvania]] ** ''Community Connection'' {{WS|berksmontnews.com/community_connection}} of [[Boyertown, Pennsylvania]] * Magazines ** ''Bucks Co. Town & Country Living'' {{WS|buckscountymagazine.com}} ** ''Parents Express'' {{WS|parents-express.com}} ** ''Real Men, Rednecks'' {{WS|realmenredneck.com}} {{JRC}} * Let's checkout Unicodes Here's a long text with a variety of emoticons, broken into multiple paragraphs: ** Paragraph 1 Hey there! 🙂 I'm so excited to share this text with you! 🤩 It's going to be a wild ride 🎢 full of emotions 😂 and fun 🎉. We'll have some serious moments 🤔, some silly moments 🤪, and some moments that will make you go "huh?" 🤔. ** Paragraph 2 Now, let's explore some emotional extremes 🌊. We've got your ecstatic face 🤩, your devastated face 😭, and your utterly confused face 🤯. But that's not all! 🤔 We've also got some subtle emotions like 😐, 🙃, and 👀. ** Paragraph 3 Now, let's get a little crazy 🤪! 🎉👯‍♀️🕺 We've got emojis for every occasion 🎂, every emotion 🤣, and every interest 🎨. Want to talk about food? 🍔🍕🥤 We've got emojis for that! Want to talk about travel? 🗺️🛫️ We've got emojis for that too! ** Paragraph 4 But wait, there's more! 🤯 We've also got some more obscure emojis 🤔. Like, have you ever seen this one? 🚯 Or this one? 🛂️ What about this one? 🤷‍♂️ Yeah, we've got all those and more! ** Paragraph 5 So, there you have it! 🎉 A text full of emojis, fun, and excitement 🤩. We hope you enjoyed the ride 🎢 and will join us again soon 🤗. Until next time, stay emoji-tastic! 😄👋 Note: I've used a variety of emojis, including: - Smiley faces and emotions (e.g., 🙂😂🤔) - Objects (e.g., 🎉🎂🍔) - Animals (e.g., 🐶, 🐱) - Symbols (e.g., 👍, 👏) - Flags (e.g., 🇺🇸, 🇬🇧) - And more! 🤯🌊,🛂️ ==References== [[Category:Journal Register publications|*]] diff-1.0.1/internal/benchmarks/testdata/small.test000066400000000000000000000214741516001707200222030ustar00rootroot00000000000000From https://go.googlesource.com/go commit 78eadf5b3de568297456fe137b65ff16e8cc8bb6 file src/cmd/vendor/golang.org/x/sync/errgroup/errgroup.go -- x -- // Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // Package errgroup provides synchronization, error propagation, and Context // cancelation for groups of goroutines working on subtasks of a common task. // // [errgroup.Group] is related to [sync.WaitGroup] but adds handling of tasks // returning errors. package errgroup import ( "context" "fmt" "sync" ) type token struct{} // A Group is a collection of goroutines working on subtasks that are part of // the same overall task. A Group should not be reused for different tasks. // // A zero Group is valid, has no limit on the number of active goroutines, // and does not cancel on error. type Group struct { cancel func(error) wg sync.WaitGroup sem chan token errOnce sync.Once err error } func (g *Group) done() { if g.sem != nil { <-g.sem } g.wg.Done() } // WithContext returns a new Group and an associated Context derived from ctx. // // The derived Context is canceled the first time a function passed to Go // returns a non-nil error or the first time Wait returns, whichever occurs // first. func WithContext(ctx context.Context) (*Group, context.Context) { ctx, cancel := context.WithCancelCause(ctx) return &Group{cancel: cancel}, ctx } // Wait blocks until all function calls from the Go method have returned, then // returns the first non-nil error (if any) from them. func (g *Group) Wait() error { g.wg.Wait() if g.cancel != nil { g.cancel(g.err) } return g.err } // Go calls the given function in a new goroutine. // The first call to Go must happen before a Wait. // It blocks until the new goroutine can be added without the number of // active goroutines in the group exceeding the configured limit. // // The first call to return a non-nil error cancels the group's context, if the // group was created by calling WithContext. The error will be returned by Wait. func (g *Group) Go(f func() error) { if g.sem != nil { g.sem <- token{} } g.wg.Add(1) go func() { defer g.done() if err := f(); err != nil { g.errOnce.Do(func() { g.err = err if g.cancel != nil { g.cancel(g.err) } }) } }() } // TryGo calls the given function in a new goroutine only if the number of // active goroutines in the group is currently below the configured limit. // // The return value reports whether the goroutine was started. func (g *Group) TryGo(f func() error) bool { if g.sem != nil { select { case g.sem <- token{}: // Note: this allows barging iff channels in general allow barging. default: return false } } g.wg.Add(1) go func() { defer g.done() if err := f(); err != nil { g.errOnce.Do(func() { g.err = err if g.cancel != nil { g.cancel(g.err) } }) } }() return true } // SetLimit limits the number of active goroutines in this group to at most n. // A negative value indicates no limit. // A limit of zero will prevent any new goroutines from being added. // // Any subsequent call to the Go method will block until it can add an active // goroutine without exceeding the configured limit. // // The limit must not be modified while any goroutines in the group are active. func (g *Group) SetLimit(n int) { if n < 0 { g.sem = nil return } if len(g.sem) != 0 { panic(fmt.Errorf("errgroup: modify limit while %v goroutines in the group are still active", len(g.sem))) } g.sem = make(chan token, n) } -- y -- // Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // Package errgroup provides synchronization, error propagation, and Context // cancelation for groups of goroutines working on subtasks of a common task. // // [errgroup.Group] is related to [sync.WaitGroup] but adds handling of tasks // returning errors. package errgroup import ( "context" "fmt" "runtime" "runtime/debug" "sync" ) type token struct{} // A Group is a collection of goroutines working on subtasks that are part of // the same overall task. A Group should not be reused for different tasks. // // A zero Group is valid, has no limit on the number of active goroutines, // and does not cancel on error. type Group struct { cancel func(error) wg sync.WaitGroup sem chan token errOnce sync.Once err error mu sync.Mutex panicValue any // = PanicError | PanicValue; non-nil if some Group.Go goroutine panicked. abnormal bool // some Group.Go goroutine terminated abnormally (panic or goexit). } func (g *Group) done() { if g.sem != nil { <-g.sem } g.wg.Done() } // WithContext returns a new Group and an associated Context derived from ctx. // // The derived Context is canceled the first time a function passed to Go // returns a non-nil error or the first time Wait returns, whichever occurs // first. func WithContext(ctx context.Context) (*Group, context.Context) { ctx, cancel := context.WithCancelCause(ctx) return &Group{cancel: cancel}, ctx } // Wait blocks until all function calls from the Go method have returned // normally, then returns the first non-nil error (if any) from them. // // If any of the calls panics, Wait panics with a [PanicValue]; // and if any of them calls [runtime.Goexit], Wait calls runtime.Goexit. func (g *Group) Wait() error { g.wg.Wait() if g.cancel != nil { g.cancel(g.err) } if g.panicValue != nil { panic(g.panicValue) } if g.abnormal { runtime.Goexit() } return g.err } // Go calls the given function in a new goroutine. // // The first call to Go must happen before a Wait. // It blocks until the new goroutine can be added without the number of // goroutines in the group exceeding the configured limit. // // The first goroutine in the group that returns a non-nil error, panics, or // invokes [runtime.Goexit] will cancel the associated Context, if any. func (g *Group) Go(f func() error) { if g.sem != nil { g.sem <- token{} } g.add(f) } func (g *Group) add(f func() error) { g.wg.Add(1) go func() { defer g.done() normalReturn := false defer func() { if normalReturn { return } v := recover() g.mu.Lock() defer g.mu.Unlock() if !g.abnormal { if g.cancel != nil { g.cancel(g.err) } g.abnormal = true } if v != nil && g.panicValue == nil { switch v := v.(type) { case error: g.panicValue = PanicError{ Recovered: v, Stack: debug.Stack(), } default: g.panicValue = PanicValue{ Recovered: v, Stack: debug.Stack(), } } } }() err := f() normalReturn = true if err != nil { g.errOnce.Do(func() { g.err = err if g.cancel != nil { g.cancel(g.err) } }) } }() } // TryGo calls the given function in a new goroutine only if the number of // active goroutines in the group is currently below the configured limit. // // The return value reports whether the goroutine was started. func (g *Group) TryGo(f func() error) bool { if g.sem != nil { select { case g.sem <- token{}: // Note: this allows barging iff channels in general allow barging. default: return false } } g.add(f) return true } // SetLimit limits the number of active goroutines in this group to at most n. // A negative value indicates no limit. // A limit of zero will prevent any new goroutines from being added. // // Any subsequent call to the Go method will block until it can add an active // goroutine without exceeding the configured limit. // // The limit must not be modified while any goroutines in the group are active. func (g *Group) SetLimit(n int) { if n < 0 { g.sem = nil return } if len(g.sem) != 0 { panic(fmt.Errorf("errgroup: modify limit while %v goroutines in the group are still active", len(g.sem))) } g.sem = make(chan token, n) } // PanicError wraps an error recovered from an unhandled panic // when calling a function passed to Go or TryGo. type PanicError struct { Recovered error Stack []byte // result of call to [debug.Stack] } func (p PanicError) Error() string { if len(p.Stack) > 0 { return fmt.Sprintf("recovered from errgroup.Group: %v\n%s", p.Recovered, p.Stack) } return fmt.Sprintf("recovered from errgroup.Group: %v", p.Recovered) } func (p PanicError) Unwrap() error { return p.Recovered } // PanicValue wraps a value that does not implement the error interface, // recovered from an unhandled panic when calling a function passed to Go or // TryGo. type PanicValue struct { Recovered any Stack []byte // result of call to [debug.Stack] } func (p PanicValue) String() string { if len(p.Stack) > 0 { return fmt.Sprintf("recovered from errgroup.Group: %v\n%s", p.Recovered, p.Stack) } return fmt.Sprintf("recovered from errgroup.Group: %v", p.Recovered) } diff-1.0.1/internal/byteview/000077500000000000000000000000001516001707200160725ustar00rootroot00000000000000diff-1.0.1/internal/byteview/byteview.go000066400000000000000000000060351516001707200202630ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // Package byteview provides a mechanism to handle strings and []byte as immutable byte views. package byteview import ( "iter" "slices" "strings" "sync" "unsafe" ) type ByteView struct { data string } func From[T string | []byte](in T) ByteView { switch in := any(in).(type) { case string: return ByteView{in} case []byte: return ByteView{unsafe.String(unsafe.SliceData(in), len(in))} } panic("never reached") } func (v ByteView) Len() int { return len(v.data) } func (v ByteView) Bytes() iter.Seq[byte] { return func(yield func(byte) bool) { for i := range len(v.data) { if !yield(v.data[i]) { break } } } } // UnsafeAs converts a ByteView to type T independently of what it was originally. This is // only safe if the type is the same one used for From and either the result is not modified // or the ByteView is no longer used. func UnsafeAs[T string | []byte](v ByteView) T { switch any((*T)(nil)).(type) { case *string: return T(v.data) case *[]byte: return T(unsafe.Slice(unsafe.StringData(v.data), len(v.data))) } panic("never reached") } // SplitLines splits the input on '\n' and returns the lines including the newline character and // and either -1 if the last line ends in a newline character or len([]ByteView) if it's missing // a newline character. func SplitLines(v ByteView) (lines []ByteView, missingNewline int) { s := v.data n := strings.Count(v.data, "\n") if len(s) > 0 && s[len(s)-1] != '\n' { n++ } a := make([]ByteView, n) for i := range n { m := strings.Index(s, "\n") if m < 0 { break } a[i] = ByteView{s[:m+1]} s = s[m+1:] } missingNewline = -1 if len(s) > 0 { a[n-1] = ByteView{s} missingNewline = n - 1 } return a, missingNewline } type Builder[T string | []byte] struct { _ [0]sync.Mutex // don't copy buf []byte } func (b *Builder[T]) Grow(n int) { b.buf = slices.Grow(b.buf, n) } func (b *Builder[T]) Write(v []byte) (n int, err error) { b.buf = append(b.buf, v...) return len(v), nil } func (b *Builder[T]) WriteByteView(v ByteView) (n int, err error) { b.buf = append(b.buf, v.data...) return len(v.data), nil } func (b *Builder[T]) WriteString(v string) (n int, err error) { b.buf = append(b.buf, v...) return len(v), nil } func (b *Builder[T]) Build() T { defer func() { b.buf = nil }() switch any((*T)(nil)).(type) { case *string: return T(unsafe.String(unsafe.SliceData(b.buf), len(b.buf))) case *[]byte: return T(b.buf) } panic("never reached") } diff-1.0.1/internal/byteview/byteview_test.go000066400000000000000000000105031516001707200213150ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package byteview import ( "bytes" "slices" "testing" "unsafe" "github.com/google/go-cmp/cmp" ) func TestFromString(t *testing.T) { str := "my string" got := From(str) if unsafe.StringData(got.data) != unsafe.StringData(str) { t.Errorf("From(str) points to different memory") } if got.Len() != len(str) { t.Errorf("got.Len() = %v, want %v", got.Len(), len(str)) } t.Run("allocs", func(t *testing.T) { allocs := testing.AllocsPerRun(10, func() { _ = From(str) }) if allocs > 0 { t.Errorf("From[string](...) allocated %v times, want 0", allocs) } }) } func TestFromBytes(t *testing.T) { bytes := []byte("my byte slice") got := From(bytes) if unsafe.StringData(got.data) != unsafe.SliceData(bytes) { t.Errorf("From(bytes) points to different memory") } if got.Len() != len(bytes) { t.Errorf("got.Len() = %v, want %v", got.Len(), len(bytes)) } t.Run("allocs", func(t *testing.T) { allocs := testing.AllocsPerRun(10, func() { _ = From(bytes) }) if allocs > 0 { t.Errorf("From[[]byte](...) allocated %v times, want 0", allocs) } }) } func TestByteViewBytes(t *testing.T) { b := []byte("my byte slice") got := slices.Collect(From(b).Bytes()) if !bytes.Equal(got, b) { t.Errorf("From(b).Byte() = %q, want %q", got, b) } } func TestSplitLines(t *testing.T) { tests := []struct { name string input string wantLines []ByteView wantMissingNewline int }{ { name: "empty", input: "", wantLines: []ByteView{}, wantMissingNewline: -1, }, { name: "newline-only", input: "\n", wantLines: []ByteView{From("\n")}, wantMissingNewline: -1, }, { name: "missing-newline", input: "foo\nbar", wantLines: []ByteView{From("foo\n"), From("bar")}, wantMissingNewline: 1, }, { name: "missing-newline-in-fist-line", input: "foo", wantLines: []ByteView{From("foo")}, wantMissingNewline: 0, }, { name: "no-missing-newline", input: "foo\nbar\nbaz\n", wantLines: []ByteView{From("foo\n"), From("bar\n"), From("baz\n")}, wantMissingNewline: -1, }, } for _, tt := range tests { t.Run(tt.name, func(t *testing.T) { gotLines, gotMissingNewline := SplitLines(From(tt.input)) if diff := cmp.Diff(tt.wantLines, gotLines, cmp.Transformer("byteview", func(v ByteView) string { return v.data })); diff != "" { t.Errorf("SplitLines(...) result difference [-got, +want]:\n%s", diff) } if gotMissingNewline != tt.wantMissingNewline { t.Errorf("SplitLines(...) returned missing newline at %v, want %v", gotMissingNewline, tt.wantMissingNewline) } }) } } func TestBuilder(t *testing.T) { var b Builder[[]byte] b.WriteString("a") b.WriteByteView(From("b")) b.Write([]byte{'c'}) got, want := b.Build(), []byte("abc") if !cmp.Equal(got, want) { t.Errorf("got %q, want %q", got, want) } got, want = b.Build(), nil if !cmp.Equal(got, want) { t.Errorf("second call to Build: got %q, want %q", got, want) } } func TestBuilderBuildBytesAlloc(t *testing.T) { var b Builder[[]byte] allocs := testing.AllocsPerRun(10, func() { b.Grow(3) b.WriteString("a") b.WriteByteView(From("b")) b.Write([]byte{'c'}) _ = b.Build() }) if allocs > 1 { t.Errorf("Builder[...].Build() allocated %v times, want <= 1", allocs) } } func TestBuilderBuildStringAlloc(t *testing.T) { var b Builder[string] allocs := testing.AllocsPerRun(10, func() { b.Grow(3) b.WriteString("a") b.WriteByteView(From("b")) b.Write([]byte{'c'}) _ = b.Build() }) if allocs > 1 { t.Errorf("Builder[...].Build() allocated %v times, want <= 1", allocs) } } diff-1.0.1/internal/cmd/000077500000000000000000000000001516001707200147775ustar00rootroot00000000000000diff-1.0.1/internal/cmd/eval/000077500000000000000000000000001516001707200157265ustar00rootroot00000000000000diff-1.0.1/internal/cmd/eval/internal/000077500000000000000000000000001516001707200175425ustar00rootroot00000000000000diff-1.0.1/internal/cmd/eval/internal/git/000077500000000000000000000000001516001707200203255ustar00rootroot00000000000000diff-1.0.1/internal/cmd/eval/internal/git/git.go000066400000000000000000000111641516001707200214420ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // Package git provides a simplified git interface for reading a repository for evaluations package git import ( "bufio" "bytes" "fmt" "io" "os" "os/exec" "runtime" "strconv" "strings" ) type Repo struct { dir string gitcat chan<- gitcatterinstr done chan struct{} } func Open(dir string) (*Repo, error) { if _, err := os.Stat(dir); os.IsNotExist(err) { return nil, err } gitcat, done := gitcatter(dir) return &Repo{ dir: dir, gitcat: gitcat, done: done, }, nil } func (r *Repo) Close() { close(r.gitcat) <-r.done } func (r *Repo) RevList() ([]string, error) { out, err := git("-C", r.dir, "rev-list", "--no-merges", "HEAD") if err != nil { return nil, err } revs := strings.Split(out, "\n") if revs[len(revs)-1] == "" { revs = revs[:len(revs)-1] } return revs, nil } type FileDiff struct { Name string OldID string NewID string } func (r *Repo) DiffTree(commit string) ([]FileDiff, error) { out, err := git("-C", r.dir, "diff-tree", "-r", commit) if err != nil { return nil, err } lines := strings.Split(out, "\n")[1:] ret := make([]FileDiff, 0, len(lines)) for _, line := range lines { if len(line) == 0 { continue } if line[0] != ':' { return nil, fmt.Errorf("diff-tree file not starting with ':': %q", line) } fields := strings.Fields(line[1:]) ret = append(ret, FileDiff{ Name: fields[5], OldID: fields[2], NewID: fields[3], }) } return ret, nil } func (r *Repo) Read(blobIDs []string, cb func([]string)) { r.gitcat <- gitcatterinstr{blobIDs, cb} } func git(args ...string) (string, error) { var wout, werr strings.Builder cmd := exec.Command("git", args...) cmd.Stdout = &wout cmd.Stderr = &werr if err := cmd.Run(); err != nil { return "", fmt.Errorf("running git command %v: %v\n%s", cmd, err, werr.String()) } return wout.String(), nil } type gitcatterinstr struct { blobIds []string cb func([]string) } func gitcatter(repo string) (chan<- gitcatterinstr, chan struct{}) { wc := make(chan gitcatterinstr) rc := make(chan []gitcatterinstr, runtime.GOMAXPROCS(0)) done := make(chan struct{}) cmd := exec.Command("git", "-C", repo, "cat-file", "--batch-command", "--buffer") in, err := cmd.StdinPipe() if err != nil { panic(fmt.Sprintf("failed to connect stdin: %v", err)) } out, err := cmd.StdoutPipe() if err != nil { panic(fmt.Sprintf("failed to connect stdout: %v", err)) } var werr bytes.Buffer cmd.Stderr = &werr if err := cmd.Start(); err != nil { panic(err) } r, w := bufio.NewReader(out), in go func() { defer close(rc) const N = 32 for { bundle := make([]gitcatterinstr, 0, N) Write: for range N { select { case instr, ok := <-wc: if !ok { return } for _, id := range instr.blobIds { if id == "0000000000000000000000000000000000000000" { continue } if _, err := fmt.Fprintf(w, "contents %s\n", id); err != nil { panic(fmt.Sprintf("writing to stdin pipe: %v", err)) } } bundle = append(bundle, instr) default: break Write } } if _, err := fmt.Fprintf(w, "flush\n"); err != nil { panic(fmt.Sprintf("writing to stdin pipe: %v", err)) } rc <- bundle } }() go func() { defer close(done) for bundle := range rc { for _, instr := range bundle { out := make([]string, len(instr.blobIds)) for i, id := range instr.blobIds { if id == "0000000000000000000000000000000000000000" { continue } line, err := r.ReadString('\n') if err != nil { panic(err) } fields := strings.Fields(line) if len(fields) != 3 { panic(fmt.Sprintf("found %v fields, expected 3: %q", len(fields), line)) } if fields[0] != id { panic(fmt.Sprintf("ids don't match %s vs %s", fields[0], id)) } n, err := strconv.ParseInt(fields[2], 10, 64) if err != nil { panic(err) } buf := make([]byte, n+1) if _, err := io.ReadFull(r, buf); err != nil { panic(err) } out[i] = string(buf[:n]) } instr.cb(out) } } }() return wc, done } diff-1.0.1/internal/cmd/eval/main.go000066400000000000000000000177601516001707200172140ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // eval provides a way to validate the diffing algorithm by applying the resulting diffs using // the unix patch tool and checking that they produce the input again. package main import ( "bufio" "flag" "fmt" "math" "math/rand/v2" "os" "runtime" "slices" "strings" "sync" "sync/atomic" "time" "znkr.io/diff" "znkr.io/diff/internal/cmd/eval/internal/git" "znkr.io/diff/internal/unixpatch" "znkr.io/diff/textdiff" ) type config struct { repo string sample int parallel int stats string validate bool } func main() { var cfg config flag.StringVar(&cfg.repo, "repo", "", "repository to use for evaluation") flag.IntVar(&cfg.sample, "sample", 0, "if >0, sample commits to the value of the flag") flag.IntVar(&cfg.parallel, "parallel", runtime.GOMAXPROCS(0), "number of evaluations to run in parallel") flag.StringVar(&cfg.stats, "stats", "", "file to store stats in") flag.BoolVar(&cfg.validate, "validate", true, "if validation should be performed") flag.Parse() if len(flag.CommandLine.Args()) > 0 { fmt.Fprintf(os.Stderr, "error: unexpected command line arguments: %v\n", flag.CommandLine.Args()) os.Exit(1) } if err := run(&cfg); err != nil { fmt.Fprintf(os.Stderr, "error: %v\n", err) os.Exit(1) } } var bars = []string{ " ", "▏", "▎", "▍", "▌", "▋", "▊", "▉", "█", } type note struct { prefix string msg string } type result struct { commitID string file string variant string N, M int D int duration time.Duration } func run(cfg *config) error { start := time.Now() notes := make(chan note) done := make(chan struct{}) var commitsDone atomic.Int64 var processed atomic.Int64 var stats *os.File if cfg.stats != "" { var err error stats, err = os.Create(cfg.stats) if err != nil { return fmt.Errorf("creating stats file: %v", err) } } git, err := git.Open(cfg.repo) if err != nil { return fmt.Errorf("opening git repository: %v", err) } commitIDs, err := git.RevList() if err != nil { return fmt.Errorf("reading rev-list: %v", err) } // Sample commits if cfg.sample > 0 && cfg.sample < len(commitIDs) { picked := make(map[int]struct{}, cfg.sample) sample := make([]string, 0, cfg.sample) for len(sample) < cfg.sample { i := rand.IntN(len(commitIDs)) if _, ok := picked[i]; ok { continue } sample = append(sample, commitIDs[i]) picked[i] = struct{}{} } commitIDs = sample } // Process commits. type change struct { commitID string filename string old, new string } changes := make(chan change) var changesWG sync.WaitGroup chunkSize := len(commitIDs) / (4 * runtime.GOMAXPROCS(0)) for chunk := range slices.Chunk(commitIDs, chunkSize) { changesWG.Add(1) go func() { defer changesWG.Done() for _, commitID := range chunk { files, err := git.DiffTree(commitID) if err != nil { notes <- note{ prefix: commitID, msg: fmt.Sprintf("error proccesing commit: %v", err), } } for _, file := range files { if strings.HasSuffix(file.Name, ".zip") || strings.HasSuffix(file.Name, ".syso") { continue } git.Read([]string{file.OldID, file.NewID}, func(res []string) { changes <- change{ commitID: commitID, filename: file.Name, old: res[0], new: res[1], } }) } commitsDone.Add(1) } }() } // Process diffs. var processWG sync.WaitGroup var results chan result if cfg.stats != "" { results = make(chan result) } for range cfg.parallel { processWG.Add(1) go func() { defer processWG.Done() for change := range changes { variants := map[string][]diff.Option{ "default": nil, "minimal": {diff.Minimal()}, "fast": {diff.Fast()}, "indent-heuristic": {textdiff.IndentHeuristic()}, } lines := func(s string) int { n := strings.Count(s, "\n") if len(s) > 0 && s[len(s)-1] != '\n' { n++ } return n } old := change.old new := change.new for len(old) > 0 && len(new) > 0 && old[0] == new[0] { old = old[1:] new = new[1:] } for len(old) > 0 && len(new) > 0 && old[len(old)-1] == new[len(new)-1] { old = old[:len(old)-1] new = new[:len(new)-1] } N, M := lines(old), lines(new) for variant, opts := range variants { if results != nil { start := time.Now() hunks := textdiff.Hunks(change.old, change.new, opts...) duration := time.Since(start) nedits := 0 for _, hunk := range hunks { for _, edits := range hunk.Edits { if edits.Op == diff.Delete || edits.Op == diff.Insert { nedits++ } } } results <- result{ commitID: change.commitID, file: change.filename, variant: variant, N: N, M: M, D: nedits, duration: duration, } } if cfg.validate { unified := textdiff.Unified(change.old, change.new, opts...) patched, err := unixpatch.Patch(change.old, unified) if err != nil { notes <- note{ prefix: change.commitID + ":" + change.filename, msg: fmt.Sprintf("failed to run patch: %v", err), } } if change.new != patched { notes <- note{ prefix: change.commitID + ":" + change.filename, msg: fmt.Sprintf("file is different after applying patch. got:\n%s\nwant:\n%s", change.new, patched), } } } } processed.Add(1) } }() } // Render progress var ioWG sync.WaitGroup render := func() { const width = 60 commits := commitsDone.Load() processed := processed.Load() progress := float64(commits) / float64(len(commitIDs)) whole := int(progress * width) remainder := math.Mod(progress*width, 1) last := bars[max(0, min(len(bars), int(remainder*float64(len(bars)))))] if width-whole < 1 { last = "" } bar := strings.Repeat(bars[len(bars)-1], whole) + last var commitsPerSec, procPerSec int if commits > 0 { commitsPerSec = int((time.Duration(commits) * time.Second) / time.Since(start)) } if processed > 0 { procPerSec = int((time.Duration(processed) * time.Second) / time.Since(start)) } fmt.Printf("\r[%-*s] % 3.1f%% (%d commits/s, %d evals/s) ", width, bar, 100*progress, commitsPerSec, procPerSec) } ioWG.Add(1) go func() { defer ioWG.Done() ticker := time.NewTicker(200 * time.Millisecond) defer ticker.Stop() for { select { case note := <-notes: fmt.Printf("\r%s: %s\n", note.prefix, note.msg) render() case <-ticker.C: render() case <-done: render() fmt.Printf("\n") return } } }() if cfg.stats != "" { go func() { defer ioWG.Done() w := bufio.NewWriter(stats) w.WriteString("commit_id,file,variant,N,M,D,duration_ns\n") for result := range results { _, err := fmt.Fprintf(w, "%s,%s,%s,%d,%d,%d,%d\n", result.commitID, result.file, result.variant, result.N, result.M, result.D, result.duration.Nanoseconds()) if err != nil { notes <- note{ prefix: result.commitID + ":" + result.file, msg: fmt.Sprintf("failed to write stats: %v", err), } } } err := w.Flush() if err != nil { notes <- note{ prefix: "", msg: fmt.Sprintf("failed to flush stats: %v", err), } } }() } // Shutdown changesWG.Wait() git.Close() close(changes) processWG.Wait() close(done) if results != nil { close(results) } ioWG.Wait() return nil } diff-1.0.1/internal/cmd/gitdiff/000077500000000000000000000000001516001707200164135ustar00rootroot00000000000000diff-1.0.1/internal/cmd/gitdiff/gitdiff.go000066400000000000000000000047051516001707200203640ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // gitdiff is a tool that can be used with git using GIT_EXTERNAL_DIFF. // // This is not generally useful and it has some weird defaults. The use case for it is to work with // the slider evaluation in https://github.com/mhagger/diff-slider-tools. The evaluation can be used // with a small local modification of the repositories run-comparison script: // // Adding this snippet // // git_znkr() { // GIT_EXTERNAL_DIFF=${HOME}/Projects/diff/gitdiff git -C corpus/$1.git $GIT_OPTS diff "$2" "$3" -- // } // // allows us to compare against git's implementation of indent heuristics. The comparison is not // 100% because we sometimes return different diffs than git, but overall the quality of the // result is about the same. package main import ( "fmt" "os" "znkr.io/diff" "znkr.io/diff/textdiff" ) func main() { if err := run(os.Args); err != nil { fmt.Fprintf(os.Stderr, "error: %v\n", err) } } func run(args []string) error { if len(args) < 8 { return fmt.Errorf("expected at least 8 args, got %v: %v", len(args), args) } path, oldFile, oldHex, oldMode, newFile, newHex, newMode := args[1], args[2], args[3], args[4], args[5], args[6], args[7] _, _, _, _, _, _, _ = path, oldFile, oldHex, oldMode, newFile, newHex, newMode var old []byte if oldFile != "/dev/null" { var err error old, err = os.ReadFile(oldFile) if err != nil { return fmt.Errorf("reading old file: %v", err) } } var new []byte if newFile != "/dev/null" { var err error new, err = os.ReadFile(newFile) if err != nil { return fmt.Errorf("reading new file: %v", err) } } diff := textdiff.Unified(old, new, textdiff.IndentHeuristic(), diff.Context(20)) fmt.Printf("diff --git a/%s b/%s\n", path, path) fmt.Printf("index %s..%s %s\n", oldHex[:10], newHex[:10], newMode) fmt.Printf("--- a/%s\n", path) fmt.Printf("+++ b/%s\n", path) os.Stdout.Write(diff) return nil } diff-1.0.1/internal/cmd/specializemyers/000077500000000000000000000000001516001707200202075ustar00rootroot00000000000000diff-1.0.1/internal/cmd/specializemyers/main.go000066400000000000000000000022401516001707200214600ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // specializemyers is a bit of an abomination, it takes the myers implementation and generates a // specialization for int. That specialization is quit a bit faster and reduces run times by -10% to // -40%. The problem is that I haven't found a better way to do this optimization. package main import ( "fmt" "os" ) func main() { out, err := specialize("myers.go") if err != nil { fmt.Fprintf(os.Stderr, "error: %v", err) os.Exit(1) } if err := os.WriteFile("gen_myers_int.go", out, 0o644); err != nil { fmt.Fprintf(os.Stderr, "error: %v", err) os.Exit(1) } } diff-1.0.1/internal/cmd/specializemyers/specialize.go000066400000000000000000000120431516001707200226660ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package main import ( "bytes" "fmt" "go/ast" "go/format" "go/parser" "go/token" "slices" "golang.org/x/tools/go/ast/astutil" ) const header = `// generated by znkr.io/diff/internal/cmd/specializemyers // DO NOT EDIT ` func specialize(filename string) ([]byte, error) { fset := token.NewFileSet() file, err := parser.ParseFile(fset, filename, nil, 0) if err != nil { return nil, fmt.Errorf("parsing input: %v", err) } file = astutil.Apply(file, func(c *astutil.Cursor) bool { switch n := c.Node().(type) { case *ast.TypeSpec: if isMyersT(n) { n.Name.Name = "myersInt" n.TypeParams = nil for _, field := range n.Type.(*ast.StructType).Fields.List { field.Type = specializeT(field.Type) } } return false case *ast.FuncDecl: if isMyresTMethod(n) { if !methodsOfInterest[n.Name.Name] { return false } n.Recv.List[0].Type.(*ast.StarExpr).X = &ast.Ident{Name: "myersInt"} local := n.Recv.List[0].Names[0].Name n.Type.Params.List = slices.DeleteFunc(n.Type.Params.List, func(f *ast.Field) bool { if len(f.Names) != 1 { return false } return f.Names[0].Name == "eq" && isEqFunc(f.Type) }) for _, param := range n.Type.Params.List { param.Type = specializeT(param.Type) } n.Body = astutil.Apply(n.Body, func(c *astutil.Cursor) bool { call, ok := c.Node().(*ast.CallExpr) if !ok { return true } switch fun := call.Fun.(type) { case *ast.SelectorExpr: if x, ok := fun.X.(*ast.Ident); !ok || x.Name != local { return true } if !methodsOfInterest[n.Name.Name] { return true } call.Args = slices.DeleteFunc(call.Args, func(arg ast.Expr) bool { name, ok := arg.(*ast.Ident) return ok && name.Name == "eq" }) case *ast.Ident: if fun.Name != "eq" { return false } if len(call.Args) != 2 { return false } c.Replace(&ast.BinaryExpr{ X: call.Args[0], Op: token.EQL, Y: call.Args[1], }) } return true }, nil).(*ast.BlockStmt) } return false default: return true } }, nil).(*ast.File) var buf bytes.Buffer buf.WriteString(header) if err := format.Node(&buf, fset, file); err != nil { return nil, fmt.Errorf("formatting result: %v", err) } return buf.Bytes(), nil } var methodsOfInterest = map[string]bool{ "split": true, "compare": true, "init": true, } func isMyersT(ts *ast.TypeSpec) bool { if ts.Name.Name != "myers" { return false } if _, ok := ts.Type.(*ast.StructType); !ok { return false } return matchFields(ts.TypeParams, []fmatcher{ 0: func(name string, typ ast.Expr) bool { tname, ok := typ.(*ast.Ident) return ok && name == "T" && tname.Name == "any" }, }) } func isMyresTMethod(fd *ast.FuncDecl) bool { return matchFields(fd.Recv, []fmatcher{ 0: func(name string, typ ast.Expr) bool { star, ok := typ.(*ast.StarExpr) if !ok { return false } x, ok := star.X.(*ast.IndexExpr) if !ok { return false } tname, ok := x.X.(*ast.Ident) if !ok { return false } index, ok := x.Index.(*ast.Ident) if !ok { return false } return tname.Name == "myers" && index.Name == "T" }, }) } func isEqFunc(expr ast.Expr) bool { typ, ok := expr.(*ast.FuncType) if !ok { return false } isTypT := func(_ string, typ ast.Expr) bool { tname, ok := typ.(*ast.Ident) return ok && tname.Name == "T" } params := matchFields(typ.Params, []fmatcher{ 0: isTypT, 1: isTypT, }) ret := matchFields(typ.Results, []fmatcher{ 0: func(_ string, typ ast.Expr) bool { tname, ok := typ.(*ast.Ident) return ok && tname.Name == "bool" }, }) return params && ret } func specializeT[N ast.Node](n N) N { return astutil.Apply(n, func(c *astutil.Cursor) bool { if ident, ok := c.Node().(*ast.Ident); ok && ident.Name == "T" { ident.Name = "int" return false } return true }, nil).(N) } type fmatcher func(name string, typ ast.Expr) bool func matchFields(fl *ast.FieldList, matchers []fmatcher) bool { if len(fl.List) == 0 && len(matchers) != 0 { return false } i := 0 for _, f := range fl.List { if len(f.Names) == 0 { if i >= len(matchers) { return false } if !matchers[i]("", f.Type) { return false } i++ } for _, name := range f.Names { if i >= len(matchers) { return false } if !matchers[i](name.Name, f.Type) { return false } i++ } } return i == len(matchers) } diff-1.0.1/internal/cmd/specializemyers/specialize_test.go000066400000000000000000000020501516001707200237220ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package main import ( "os" "testing" "github.com/google/go-cmp/cmp" ) func TestSpecialize(t *testing.T) { got, err := specialize("../../impl/myers.go") if err != nil { t.Fatal(err) } want, err := os.ReadFile("../../impl/gen_myers_int.go") if err != nil { t.Fatal(err) } if diff := cmp.Diff(want, got); diff != "" { t.Errorf("differences between specialized file and checked in file detected:\n%s\nForgot to run go generate?", diff) } } diff-1.0.1/internal/config/000077500000000000000000000000001516001707200155015ustar00rootroot00000000000000diff-1.0.1/internal/config/config.go000066400000000000000000000061301516001707200172750ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // Package config provides shared configuration mechanisms for packages this module. // // This package is an implementation detail, the configuration surface for users is provided via // diff.Option. package config // Mode describes the mode of the diff algorithm. type Mode int const ( // Limit the cost for large inputs with many differences by applying heuristics that reduce the // time complexity at the cost of non-minimal diffs. ModeDefault Mode = iota // Find a minimal diff irrespective of the cost. ModeMinimal // Find a diff as fast as possible. ModeFast ) // Config collects all configurable parameters for comparison functions in this module. type Config struct { // Context is the number of matches to include as a prefix and postfix for hunks returned. Context int // Diff algorithm mode. Mode Mode // If set, textdiff will apply ident heuristics. IndentHeuristic bool // If not nil, textdiff.Unify will use this to color the output. Colors *ColorConfig // If set, internal/myers will always use the anchoring heuristic. This configuration is not // exposed via an option API, it's main use is for testing. ForceAnchoringHeuristic bool } type ColorConfig struct { Reset string HunkHeader string Match, Delete, Insert string } // Default is the default configuration. var Default = Config{ Context: 3, Mode: ModeDefault, IndentHeuristic: false, ForceAnchoringHeuristic: false, } // Flag describes a single config entry. This is used to detect if configurations are being set // that are not type Flag int const ( Context Flag = 1 << iota Minimal Fast IndentHeuristic TerminalColors ) // Option is the mechanism used to expose the configuration to users. type Option func(*Config) Flag // FromOptions creates a configuration from a set of options. func FromOptions(opts []Option, allowed Flag) Config { cfg := Default for _, opt := range opts { flag := opt(&cfg) if flag & ^allowed != 0 { panic("Option " + printFlag(flag) + " not allowed here") } } if cfg.Mode != ModeDefault && cfg.ForceAnchoringHeuristic { panic("ForceAnchoringHeuristic may only be set for ModeDefault") } return cfg } func printFlag(flag Flag) string { switch flag { case Context: return "diff.Context" case Minimal: return "diff.Minimal" case Fast: return "diff.Fast" case IndentHeuristic: return "textdiff.IndentHeuristic" case TerminalColors: return "textdiff.TerminalColors" default: panic("never reached") } } diff-1.0.1/internal/config/config_test.go000066400000000000000000000047401516001707200203410ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package config_test import ( "testing" "github.com/google/go-cmp/cmp" "znkr.io/diff" "znkr.io/diff/internal/config" "znkr.io/diff/textdiff" ) func TestFromOptions(t *testing.T) { tests := []struct { name string opts []config.Option want config.Config }{ { name: "default", opts: nil, want: config.Default, }, { name: "context", opts: []config.Option{ diff.Context(5), }, want: config.Config{ Context: 5, Mode: config.Default.Mode, IndentHeuristic: config.Default.IndentHeuristic, }, }, { name: "minimal", opts: []config.Option{ diff.Minimal(), }, want: config.Config{ Context: config.Default.Context, Mode: config.ModeMinimal, IndentHeuristic: config.Default.IndentHeuristic, }, }, { name: "minimal-context", opts: []config.Option{ diff.Minimal(), diff.Context(5), }, want: config.Config{ Context: 5, Mode: config.ModeMinimal, IndentHeuristic: config.Default.IndentHeuristic, }, }, { name: "context-override", opts: []config.Option{ diff.Context(5), diff.Minimal(), diff.Context(1), }, want: config.Config{ Context: 1, Mode: config.ModeMinimal, IndentHeuristic: config.Default.IndentHeuristic, }, }, { name: "everything", opts: []config.Option{ diff.Context(5), diff.Minimal(), textdiff.IndentHeuristic(), }, want: config.Config{ Context: 5, Mode: config.ModeMinimal, IndentHeuristic: true, }, }, } for _, tt := range tests { t.Run(tt.name, func(t *testing.T) { got := config.FromOptions(tt.opts, config.Context|config.Minimal|config.IndentHeuristic) if diff := cmp.Diff(tt.want, got); diff != "" { t.Errorf("FromOptions(...) result are different [-want,+got]:\n%s", diff) } }) } } diff-1.0.1/internal/impl/000077500000000000000000000000001516001707200151755ustar00rootroot00000000000000diff-1.0.1/internal/impl/api.go000066400000000000000000000321621516001707200163010ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // // The segments function is derived from Go's src/internal/diff/diff.go // which has the following copyright and license: // // Copyright 2022 The Go Authors. All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following disclaimer // in the documentation and/or other materials provided with the // distribution. // * Neither the name of Google LLC nor the names of its // contributors may be used to endorse or promote products derived from // this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. package impl import ( "fmt" "sort" "znkr.io/diff/internal/config" "znkr.io/diff/internal/rvecs" ) // Diff compares the contents of x and y and returns the changes necessary to convert from one to // the other. func Diff[T comparable](x, y []T, cfg config.Config) (rx, ry []bool) { rx, ry = rvecs.Make(x, y) smin, smax, tmin, tmax := findChangeBounds(x, y) if handleTrivialBounds(rx, ry, smin, smax, tmin, tmax) { return } // Preprocess x and y to reduce the problem size and to work with integer IDs instead of Ts. // This is (for now) only possible for comparable types, because mapping from T to a unique // ID requires a map. x0, y0, xidx, yidx, counts, nanchors := preprocess(rx, ry, smin, smax, tmin, tmax, x, y) switch cfg.Mode { case config.ModeMinimal: diffMinimal(rx, ry, x0, y0, xidx, yidx) case config.ModeDefault: diffDefault(rx, ry, x0, y0, xidx, yidx, counts, nanchors, cfg.ForceAnchoringHeuristic) case config.ModeFast: diffFast(rx, ry, x0, y0, xidx, yidx, counts, nanchors) default: panic(fmt.Sprintf("unknown mode: %v", cfg.Mode)) } return rx, ry } // DiffFunc compares the contents of x and y and returns the changes necessary to convert from one // to the other. // // Note that this function has generally worse performance than [Diff] for diffs with many changes. func DiffFunc[T any](x, y []T, eq func(a, b T) bool, cfg config.Config) (rx, ry []bool) { rx, ry = rvecs.Make(x, y) smin, smax, tmin, tmax := findChangeBoundsFunc(x, y, eq) if handleTrivialBounds(rx, ry, smin, smax, tmin, tmax) { return } var m myers[T] m.rx, m.ry = rx, ry smin, smax, tmin, tmax = m.init(x, y, eq) m.compare(smin, smax, tmin, tmax, cfg.Mode == config.ModeMinimal, eq) return m.rx, m.ry } // findChangeBounds returns the upper and lower bounds for the changed portion of the inputs. func findChangeBounds[T comparable](x, y []T) (smin, smax, tmin, tmax int) { smin, tmin = 0, 0 smax, tmax = len(x), len(y) // Strip common prefix. for smin < smax && tmin < tmax && x[smin] == y[tmin] { smin++ tmin++ } // Strip common suffix. for smax > smin && tmax > tmin && x[smax-1] == y[tmax-1] { smax-- tmax-- } return } // findChangeBoundsFunc returns the upper and lower bounds for the changed portion of the inputs. func findChangeBoundsFunc[T any](x, y []T, eq func(a, b T) bool) (smin, smax, tmin, tmax int) { smin, tmin = 0, 0 smax, tmax = len(x), len(y) // Strip common prefix. for smin < smax && tmin < tmax && eq(x[smin], y[tmin]) { smin++ tmin++ } // Strip common suffix. for smax > smin && tmax > tmin && eq(x[smax-1], y[tmax-1]) { smax-- tmax-- } return } // handleTrivialBounds handles trivial bounds. It returns true if the bounds are trivial. func handleTrivialBounds(rx, ry []bool, smin, smax, tmin, tmax int) bool { switch { case smin != smax && tmin == tmax: for s := smin; s < smax; s++ { rx[s] = true } return true case smin == smax && tmin != tmax: for t := tmin; t < tmax; t++ { ry[t] = true } return true case smin == smax && tmin == tmax: return true default: return false } } // preprocess performs an important optimization that significantly reduces the problem size and // time complexity. // // For performance reasons, it's doing a number of things at once. This makes it quite hard to // follow. To understand it, it's necessary to understand the individual tasks: // // Assign a unique ID to every unique input element in x and y that appears in both x and y. This // allows us to apply Myers' algorithm on integers instead of T (for faster comparison and // specialized implementation) and provides a dense ID space that makes it possible to use a slice // instead of a map to efficiently determine which elements exist in both x and y. // // Drop all elements that only appear in x or y. These are always deletions and insertions // respectively. This optimization dramatically reduces the time it takes to compute very large // diffs, because in practice those diffs will have many lines unique to x or y. // // Find all anchors, that is all elements that appear exactly once in interesting part of x and y // (x[smin:smax], y[tmin:tmax]). We do that by counting the number of occurrences as 0, 1, many for // both x and y. Using 0, 1, 2 for counts of elements in x and 0, 4, 8 for counts of elements in y. // For elements in y, we only count elements that were already found in x. With that, a count > 4 // means the element appears in both x and y and a count = 1+4 means the element is an anchor. // // The results are the following slices: // - x0: x[smin:smax] in as IDs except for elements that appear only in x // - y0: y[tmin:tmax] in as IDs except for elements that appear only in y // - xidx: A mapping from x0 to x: x0[s] corresponds to x[xidx[s]] // - yidx: A mapping from y0 to y: y0[t] corresponds to y[yidx[t]] // - counts: The number of times a ID appears in x and y. // // Note: The code below is trading some density of the ID space (and with that memory) for improved // runtime. The bottleneck here are map lookups, the code below is structured so that the number of // map lookups is minimal. func preprocess[T comparable](rx, ry []bool, smin, smax, tmin, tmax int, x, y []T) (x0, y0 []int, xidx, yidx []int, counts []int, nanchors int) { idx := make(map[T]int, smax-smin) // temporary map from element to ID buf := make([]int, 2*(smax-smin)+2*(tmax-tmin)) x0, buf = buf[:0:smax-smin], buf[smax-smin:] xidx, buf = buf[:0:smax-smin], buf[smax-smin:] y0, buf = buf[:0:tmax-tmin], buf[tmax-tmin:] yidx, buf = buf[:0:tmax-tmin], buf[tmax-tmin:] if len(buf) != 0 && cap(buf) != 0 { panic("something went wrong during buffer assignments") } counts = make([]int, smax-smin) // Step 1: Create an ID for every element in x[smin:smax] and count the number of occurrences. for _, e := range x[smin:smax] { id, ok := idx[e] if !ok { id = len(idx) idx[e] = id } if c := counts[id]; c < 2 { counts[id] = c + 1 } x0 = append(x0, id) } // Step 2: Do the same for y, but already ignore everything that's not in x, except for marking // these elements as insertions. for i, e := range y[tmin:tmax] { id, ok := idx[e] if !ok { // Not in x, this is always an insertion. ry[i+tmin] = true continue } if c := counts[id]; c < 8 { counts[id] = c + 4 } yidx = append(yidx, i+tmin) y0 = append(y0, id) } // Step 3: Filter out elements from x0 that are not in y. i := 0 for j, e := range x0 { if c := counts[e]; c > 4 { xidx = append(xidx, j+smin) x0[i] = e if c == 1+4 { // Element appears exactly once in x (1) and y (4). nanchors++ } i++ } else { rx[j+smin] = true // always an deletion } } x0 = x0[:i] return } func diffMinimal(rx, ry []bool, x0, y0 []int, xidx, yidx []int) { var m myersInt m.xidx, m.yidx = xidx, yidx m.rx, m.ry = rx, ry smin0, smax0, tmin0, tmax0 := m.init(x0, y0) m.compare(smin0, smax0, tmin0, tmax0, true) } func diffDefault(rx, ry []bool, x0, y0 []int, xidx, yidx []int, counts []int, nanchors int, forceAnchoring bool) { var m myersInt m.xidx, m.yidx = xidx, yidx m.rx, m.ry = rx, ry smin0, smax0, tmin0, tmax0 := m.init(x0, y0) // Heuristic (ANCHORING): If the input is too large and we have found anchors, use the // anchoring heuristic. This provides a significant performance boost and provides more // optimal results than the other heuristics. anchoring := nanchors > 0 && (smax0-smin0)+(tmax0-tmin0) > anchoringHeuristicMinInputLen if anchoring || forceAnchoring { segments := segments(smin0, smax0, tmin0, tmax0, nanchors, counts, x0, y0) done := segments[0] for _, anchor := range segments[1:] { if anchor.s < done.s { // Already handled scanning forward from earlier match. continue } start := anchor for start.s > done.s && start.t > done.t && x0[start.s-1] == y0[start.t-1] { start.s-- start.t-- } end := anchor for end.s < smax0 && end.t < tmax0 && x0[end.s] == y0[end.t] { end.s++ end.t++ } m.compare(done.s, start.s, done.t, start.t, false) if end.s >= smax0 && end.t >= tmax0 { break } done = end } } else { m.compare(smin0, smax0, tmin0, tmax0, false) } } func diffFast(rx, ry []bool, x0, y0 []int, xidx, yidx []int, counts []int, nanchors int) { // Fast mode uses patience diff. smin0, smax0, tmin0, tmax0 := findChangeBounds(x0, y0) segments := segments(smin0, smax0, tmin0, tmax0, nanchors, counts, x0, y0) done := segments[0] for _, anchor := range segments[1:] { if anchor.s < done.s { // Already handled scanning forward from earlier match. continue } start := anchor for start.s > done.s && start.t > done.t && x0[start.s-1] == y0[start.t-1] { start.s-- start.t-- } end := anchor for end.s < smax0 && end.t < tmax0 && x0[end.s] == y0[end.t] { end.s++ end.t++ } for s := done.s; s < start.s; s++ { rx[xidx[s]] = true } for t := done.t; t < start.t; t++ { ry[yidx[t]] = true } if end.s >= smax0 && end.t >= tmax0 { break } done = end } } type pair struct{ s, t int } // segments returns the pairs of indexes of the longest common subsequence of anchors in x and y. // // The longest common subsequence algorithm is as described in Thomas G. Szymanski, “A Special Case // of the Maximal Common Subsequence Problem,” Princeton TR #170 (January 1975), available at // https://research.swtch.com/tgs170.pdf. func segments(smin, smax, tmin, tmax int, nanchors int, counts []int, x, y []int) []pair { idx := make(map[int]int, nanchors) buf := make([]int, 3*nanchors) var xi, yi, inv []int xi, buf = buf[:0:nanchors], buf[nanchors:] yi, buf = buf[:0:nanchors], buf[nanchors:] inv, buf = buf[:0:nanchors], buf[nanchors:] if len(buf) != 0 && cap(buf) != 0 { panic("something went wrong during buffer assignments") } // Gather the indices of anchors in x and y: // xi[i] = increasing indexes of unique strings in x. // yi[i] = increasing indexes of unique strings in y. // inv[i] = index j such that x[xi[i]] = y[yi[j]]. for i, e := range y[tmin:tmax] { t := tmin + i if counts[e] == 1+4 { idx[e] = len(yi) yi = append(yi, t) } } for i, e := range x[smin:smax] { s := smin + i if counts[e] == 1+4 { xi = append(xi, s) inv = append(inv, idx[e]) } } // Apply Algorithm A from Szymanski's paper. // In those terms, A = J = inv and B = [0, n). // We add sentinel pairs {0,0}, and {len(x),len(y)} // to the returned sequence, to help the processing loop. J := inv n := len(xi) T := make([]int, n) L := make([]int, n) for i := range T { T[i] = n + 1 } for i := range n { k := sort.Search(n, func(k int) bool { return T[k] >= J[i] }) T[k] = J[i] L[i] = k + 1 } k := 0 for _, v := range L { if k < v { k = v } } anchors := make([]pair, 2+k) anchors[1+k] = pair{smax, tmax} // sentinel at end lastj := n for i := n - 1; i >= 0; i-- { if L[i] == k && J[i] < lastj { anchors[k] = pair{xi[i], yi[J[i]]} k-- } } anchors[0] = pair{smin, tmin} // sentinel at start return anchors } diff-1.0.1/internal/impl/api_test.go000066400000000000000000000077501516001707200173450ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package impl import ( "strings" "testing" "github.com/google/go-cmp/cmp" "znkr.io/diff/internal/config" ) func TestDiff(t *testing.T) { tests := []struct { name string skip func(cfg config.Config) bool x, y []string want string }{ { name: "identical", x: []string{"foo", "bar", "baz"}, y: []string{"foo", "bar", "baz"}, want: "MMM", }, { name: "empty", x: nil, y: nil, want: "", }, { name: "x-empty", x: nil, y: []string{"foo", "bar", "baz"}, want: "III", }, { name: "y-empty", x: []string{"foo", "bar", "baz"}, y: nil, want: "DDD", }, { name: "ABCABBA_to_CBABAC", skip: func(cfg config.Config) bool { return cfg.Mode == config.ModeFast }, x: strings.Split("ABCABBA", ""), y: strings.Split("CBABAC", ""), want: "DIMDMMDMI", }, { name: "ABCABBA_to_CBABAC", skip: func(cfg config.Config) bool { return cfg.Mode != config.ModeFast }, x: strings.Split("ABCABBA", ""), y: strings.Split("CBABAC", ""), want: "DDDDDDDIIIIII", }, { name: "same-prefix", x: []string{"foo", "bar"}, y: []string{"foo", "baz"}, want: "MDI", }, { name: "same-suffix", x: []string{"foo", "bar"}, y: []string{"loo", "bar"}, want: "DIM", }, { name: "largish", x: strings.Split("xaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaay", ""), y: strings.Split("waaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaait", ""), want: "DIMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMDII", }, } for _, tt := range tests { t.Run(tt.name, func(t *testing.T) { t.Run("diff", func(t *testing.T) { cfg := config.Default if tt.skip != nil && tt.skip(cfg) { return } rx, ry := Diff(tt.x, tt.y, cfg) got := render(rx, ry, len(tt.x), len(tt.y)) if diff := cmp.Diff(tt.want, got); diff != "" { t.Errorf("Diff(...) differs [-want,+got]:\n%s", diff) } }) t.Run("diff_with_anchoring", func(t *testing.T) { cfg := config.Default cfg.ForceAnchoringHeuristic = true if tt.skip != nil && tt.skip(cfg) { return } rx, ry := Diff(tt.x, tt.y, cfg) got := render(rx, ry, len(tt.x), len(tt.y)) if diff := cmp.Diff(tt.want, got); diff != "" { t.Errorf("Diff(...) differs [-want,+got]:\n%s", diff) } }) t.Run("diff_fast", func(t *testing.T) { cfg := config.Default cfg.Mode = config.ModeFast if tt.skip != nil && tt.skip(cfg) { return } rx, ry := Diff(tt.x, tt.y, cfg) got := render(rx, ry, len(tt.x), len(tt.y)) if diff := cmp.Diff(tt.want, got); diff != "" { t.Errorf("Diff(...) differs [-want,+got]:\n%s", diff) } }) t.Run("diff_func", func(t *testing.T) { cfg := config.Default if tt.skip != nil && tt.skip(cfg) { return } rx, ry := DiffFunc(tt.x, tt.y, func(a, b string) bool { return a == b }, cfg) got := render(rx, ry, len(tt.x), len(tt.y)) if diff := cmp.Diff(tt.want, got); diff != "" { t.Errorf("DiffFunc(...) differs [-want,+got]:\n%s", diff) } }) }) } } func render(rx, ry []bool, n, m int) string { var sb strings.Builder for s, t := 0, 0; s < n || t < m; { if rx[s] { sb.WriteRune('D') s++ } else if ry[t] { sb.WriteRune('I') t++ } else { sb.WriteRune('M') s++ t++ } } return sb.String() } diff-1.0.1/internal/impl/constants.go000066400000000000000000000023571516001707200175470ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package impl // minCostLimit is a lower bound for the TOO_EXPENSIVE heuristic. That is the heuristic is only // applied when the cost exceeds this number (large files with a lot of differences). const minCostLimit = 4096 // Constants for GOOD_DIAGONAL heuristic. const goodDiagMinLen = 20 // Minimal length of a diagonal for it to be considered. const goodDiagCostLimit = 256 // The Heuristic is only applied if the cost exceeds this number. const goodDiagMagic = 4 // Magic number for diagonal selection. // Constants for ANCHORING heuristic. const anchoringHeuristicMinInputLen = 5_000 // Minimum length for enabling the anchoring heuristic. diff-1.0.1/internal/impl/doc.go000066400000000000000000000174331516001707200163010ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // Package impl contains an implementation of diff algorithms. // // # Myers' Algorithm // // The implementation in this package uses the linear space variant described in section 4.2. In // addition, the TOO_EXPENSIVE heuristic by Paul Eggert is used to limit the amount of time spend // for large files with many differences. // // Without the heuristic, the runtime of Myers' algorithm is O(ND) where N is the sum of the length // of both inputs and D is the number of differences. The TOO_EXPENSIVE heuristic reduces the time // complexity to O(N^1.5 log N) but it produces suboptimal diffs. // // The algorithm is a graph search on the graph modelling all possible edits that transform x to y. // For simplicity, let's say that T is the []byte representation of string and the inputs are x = // "ABCABBA" and y = "CBABAC". Then we can represent all possible edits from x to y with the graph: // // (0,0) A B C A B B A // ┌───┬───┬───┬───┬───┬───┬───┐ 0 // │ │ │ ╲ │ │ │ │ │ // C ├───┼───┼───┼───┼───┼───┼───┤ 1 // │ │ ╲ │ │ │ ╲ │ ╲ │ │ // B ├───┼───┼───┼───┼───┼───┼───┤ 2 // │ ╲ │ │ │ ╲ │ │ │ ╲ │ // A ├───┼───┼───┼───┼───┼───┼───┤ 3 // │ │ ╲ │ │ │ ╲ │ ╲ │ │ // B ├───┼───┼───┼───┼───┼───┼───┤ 4 // │ ╲ │ │ │ ╲ │ │ │ ╲ │ // A ├───┼───┼───┼───┼───┼───┼───┤ 5 // │ │ │ ╲ │ │ │ │ │ // C └───┴───┴───┴───┴───┴───┴───┘ // 0 1 2 3 4 5 6 (7,6) // // Every vertex (intersections in the graph above) corresponds to a state. The top left (0,0) // corresponds to x and bottom right (7,6) to y. // // Every edge represents an edit. A step to the right represents a deletion of an element (e.g. // moving from (0,0) to (0,1) deletes the first "A") and a step down represents an insertion (e.g. // moving from (0,0) to (1,0) inserts a "C"). When both elements are identical, we also have // diagonal edges representing a match. // // The idea behind Myers' algorithm is to find an optimal diff (fewest insertions and deletions) by // finding a minimum-cost path from the top left (i.e. x) to the bottom right (i.e. y) where // horizontal and vertical edges have a cost of 1 and diagonal edges have a cost of 0. // // Myers found a greedy algorithm with O((N+M)D) time complexity and O(D) working memory (N = // len(x), M = len(y)). I am going to try to outline the relevant parts of the paper here without // proofs, because they are important to understand the code below. // // First some nomenclature: We're going to use s and t for the horizontal and vertical coordinates // and k for diagonals. The k=0 diagonal is the diagonal starting in (0, 0). // // Let a D-path be a path that has exactly D non-diagonal edges. A 0-path consists of only diagonal // edges. By induction, it follows that a D-path must consists of a (D-1)-path plus a non-diagonal // edge plus a possible empty sequence of diagonal edges (the paper calls a possible empty sequence // of diagonal edges a snake, but I found this confusing and will not use that terminology here). // // Lemma 1: A D-path must end on diagonal k in {-D, -D+2, ..., D-2, D}. // // Corollary 1: A D-path ends on odd diagonals when D is odd and on even diagonals when D is even. // // A D-path is furthest reaching in diagonal k if and only if it is one of the D-paths ending on // diagonal k whose end point has the greatest possible row (column) number of all such paths. // // Lemma 2: A furthest reaching 0-path ends at (s, s), where s is min(i-1 | x[i] != y[i] or i > M or // i > N). A furthest reaching D-path on diagonal k can without loss of generality be decomposed // into a furthest reaching (D-1)-path on diagonal k-1, followed by a horizontal edge, followed by // the longest possible sequence of diagonal edges or it may be decomposed into a furthest reaching // (D-1)-path on diagonal k+1, followed by a vertical edge, followed by the longest possible // sequence of diagonal edges. // // The lemma provides us with a greedy algorithm to compute an optimal path. Unfortunately, a naive // implementation of this algorithm as quadratic memory requirements. Fortunately, the algorithm can // be refined to use linear memory requirements. // // Lemma 3: There is a a D-path from (0,0) to (N,M) if and only if there is a ⌈D/2⌉-path from (0,0) // to some point (s,t) and a ⌊D/2⌋-path from some point (s',t') to (N,M) such that: // // - (feasibility) s'+t' >= ⌈D/2⌉ and s+t <= N+M-⌊D/2⌋, and // - (overlap) s-t = s'-t' and x >= s // // Moreover, both D/2-paths are contained within D-paths from (0,0) to (N,M). // // ## References: // // Myers, E.W. An O(ND) difference algorithm and its variations. Algorithmica 1, 251-266 (1986). // https://doi.org/10.1007/BF01840446 // // The algorithm was independently discovered by Ekko Ukkonen: // // Ukkonen, E. Algorithms for approximate string matching. Information and Control, Volume 64, // Issues 1-3, 100-118 (1985). https://doi.org/10.1016/S0019-9958(85)80046-2 // // ## Heuristics // // ANCHORING: A heuristic used anchor the diff around lines that are provably one 1:1 // correspondences in both files. This heuristic is similar to the patience diff algorithm, but the // idea is used as a heuristic to reduce the problem size. This heuristic speeds up diffs for large // files and produces better diffs than other heuristics we use to limit the time complexity of the // algorithm. However, this heuristic only works for comparable types. // // GOOD_DIAGONAL: A heuristic used by many diff implementations to eagerly use a good diagonal as a // split point instead of trying to find an optimal one. // // TOO_EXPENSIVE: A heuristic by Paul Eggert that reduces the time complexity significantly for // large files with many differences at the cost of suboptimal diffs. If the search for an optimal // d-path exceeds a cost limit (in terms of d), the search is aborted and the furthest reaching // d-path that optimizes x + y is used to determine a split. // // # Patience Diff (aka Anchored Diff) // // The patience diff algorithm is a heuristic to find a reasonably small diff. When the heuristics // fails, the resulting diff can be maximal (D = N+M). The upside is that this heuristic has much // better long-tail performance; O(N log N) vs O(ND) or O(N^1.5 log N). // // The algorithm works like this: // // 1. Find all anchors in x and y. That is elements that appear only once in both x and y. // 2. Find the longest common subsequence (LCS) of anchors. // 3. Expand the matching elements before and after each anchor. The regions that are not matched // this way are the diff. // // This diff algorithm is the basis for the ANCHORING heuristic. The difference is that for the // heuristic we apply Myers' algorithm on the unmatched regions. package impl diff-1.0.1/internal/impl/gen_myers_int.go000066400000000000000000000134571516001707200204000ustar00rootroot00000000000000// generated by znkr.io/diff/internal/cmd/specializemyers // DO NOT EDIT package impl import ( "math" ) type myersInt struct { x, y []int vf, vb []int v0 int costLimit int xidx, yidx []int rx, ry []bool } func (m *myersInt) init(x, y []int) (smin, smax, tmin, tmax int) { smin, tmin = 0, 0 smax, tmax = len(x), len(y) for smin < smax && tmin < tmax && x[smin] == y[tmin] { smin++ tmin++ } for smax > smin && tmax > tmin && x[smax-1] == y[tmax-1] { smax-- tmax-- } N, M := smax-smin, tmax-tmin diagonals := N + M vlen := 2*diagonals + 3 buf := make([]int, 2*vlen) m.x = x m.y = y m.vf = buf[:vlen] m.vb = buf[vlen:] m.v0 = diagonals + 1 costLimit := 1 for i := diagonals; i != 0; i >>= 2 { costLimit <<= 1 } m.costLimit = max(minCostLimit, costLimit) if m.xidx == nil || m.yidx == nil { idx := make([]int, max(len(x), len(y))) for i := range idx { idx[i] = i } m.xidx = idx[:len(x)] m.yidx = idx[:len(y)] } if m.rx == nil || m.ry == nil { r := make([]bool, (len(x) + len(y) + 2)) m.rx = r[: len(x)+1 : len(x)+1] m.ry = r[len(x)+1:] } return } func (m *myersInt) compare(smin, smax, tmin, tmax int, optimal bool) { if smin == smax { for t := tmin; t < tmax; t++ { m.ry[m.yidx[t]] = true } } else if tmin == tmax { for s := smin; s < smax; s++ { m.rx[m.xidx[s]] = true } } else { s0, s1, t0, t1, opt0, opt1 := m.split(smin, smax, tmin, tmax, optimal) m.compare(smin, s0, tmin, t0, opt0) m.compare(s1, smax, t1, tmax, opt1) } } func (m *myersInt) split(smin, smax, tmin, tmax int, optimal bool) (s0, s1, t0, t1 int, opt0, opt1 bool) { N, M := smax-smin, tmax-tmin x, y := m.x, m.y vf, vb := m.vf, m.vb v0 := m.v0 kmin, kmax := smin-tmax, smax-tmin fmid, bmid := smin-tmin, smax-tmax fmin, fmax := fmid, fmid bmin, bmax := bmid, bmid odd := (N-M)%2 != 0 vf[v0+fmid] = smin vb[v0+bmid] = smax for d := 1; ; d++ { longestDiag := 0 if fmin > kmin { fmin-- vf[v0+fmin-1] = math.MinInt } else { fmin++ } if fmax < kmax { fmax++ vf[v0+fmax+1] = math.MinInt } else { fmax-- } for k := fmin; k <= fmax; k += 2 { k0 := k + v0 var s int if vf[k0-1] < vf[k0+1] { s = vf[k0+1] } else { s = vf[k0-1] + 1 } t := s - k s0, t0 := s, t for s < smax && t < tmax && x[s] == y[t] { s++ t++ } longestDiag = max(longestDiag, s-s0) vf[k0] = s if odd && bmin <= k && k <= bmax && s >= vb[k0] { return s0, s, t0, t, true, true } } if bmin > kmin { bmin-- vb[v0+bmin-1] = math.MaxInt } else { bmin++ } if bmax < kmax { bmax++ vb[v0+bmax+1] = math.MaxInt } else { bmax-- } for k := bmin; k <= bmax; k += 2 { k0 := k + v0 var s int if vb[k0-1] < vb[k0+1] { s = vb[k0-1] } else { s = vb[k0+1] - 1 } t := s - k s0, t0 := s, t for s > smin && t > tmin && x[s-1] == y[t-1] { s-- t-- } longestDiag = max(longestDiag, s0-s) vb[k0] = s if !odd && fmin <= k && k <= fmax && s <= vf[v0+k] { return s, s0, t, t0, true, true } } if optimal { continue } if longestDiag >= goodDiagMinLen && d >= goodDiagCostLimit { best := struct { v int s0, s1, t0, t1 int opt0, opt1 bool }{} for k := fmin; k <= fmax; k += 2 { k0 := k + v0 s := vf[k0] t := s - k v := (s - smin) + (t - tmin) - max(fmid-d, d-fmid) if s < smin || smax <= s || t < tmin || tmax <= t { continue } if v <= goodDiagMagic*d || v < best.v { continue } var pk int if vf[k0-1] < vf[k0+1] { pk = k + 1 } else { pk = k - 1 } ps := vf[pk+v0] pt := ps - pk diag := min(s-ps, t-pt) if diag < goodDiagMinLen { best.v = v best.s0 = s - diag best.s1 = s best.t0 = t - diag best.t1 = t best.opt0 = true best.opt1 = false } } for k := bmin; k <= bmax; k += 2 { k0 := k + v0 s := vb[k0] t := s - k if s < smin || smax <= s || t < tmin || tmax <= t { continue } v := (smax - s) + (tmax - t) - max(bmid-d, d-bmid) if v <= goodDiagMagic*d || v < best.v { continue } var pk int if vb[k0-1] < vb[k0+1] { pk = k - 1 } else { pk = k + 1 } ps := vb[pk+v0] pt := ps - pk diag := min(ps-s, pt-t) if diag >= goodDiagMinLen { best.v = v best.s0 = s best.s1 = s + diag best.t0 = t best.t1 = t + diag best.opt0 = false best.opt1 = true } } if best.v > 0 { return best.s0, best.s1, best.t0, best.t1, best.opt0, best.opt1 } } if d >= m.costLimit { fbest, fbestk := math.MinInt, math.MinInt for k := fmin; k <= fmax; k += 2 { k0 := k + v0 s := vf[k0] t := s - k if smin <= s && s < smax && tmin <= t && t < tmax && fbest < s+t { fbest = s + t fbestk = k } } bbest, bbestk := math.MaxInt, math.MaxInt for k := bmin; k <= bmax; k += 2 { k0 := k + v0 s := vb[k0] t := s - k if smin <= s && s < smax && tmin <= t && t < tmax && s+t < bbest { bbest = s + t bbestk = k } } if fbest != math.MinInt && (smax+tmax)-bbest < fbest-(smin+tmin) { k := fbestk k0 := k + v0 s := vf[k0] t := s - k var pk int if vf[k0-1] < vf[k0+1] { pk = k + 1 } else { pk = k - 1 } ps := vf[pk+v0] pt := ps - pk diag := min(s-ps, t-pt) s0, t0 := s-diag, t-diag return s0, s, t0, t, true, false } else if bbest != math.MaxInt { k := bbestk k0 := k + v0 s := vb[k0] t := s - k var pk int if vb[k0-1] < vb[k0+1] { pk = k - 1 } else { pk = k + 1 } ps := vb[pk+v0] pt := ps - pk diag := min(ps-s, pt-t) s0, t0 := s+diag, t+diag return s, s0, t, t0, false, true } else { panic("no best path found") } } } } diff-1.0.1/internal/impl/generate.go000066400000000000000000000012541516001707200173200ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package impl //go:generate go tool znkr.io/diff/internal/cmd/specializemyers diff-1.0.1/internal/impl/myers.go000066400000000000000000000322711516001707200166700ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package impl import ( "math" ) type myers[T any] struct { // Inputs to compare. x, y []T // v-arrays for forwards and backwards iteration respectively. A v-array stores the furthest // reaching endpoint of a d-path in diagonal k in v[v0+k] where v0 is the offset that // translates k in [-d, d] to k0 = v0+k in [0, 2*d]. The endpoints only store the s-coordinate // since t = s - k. vf, vb []int v0 int // The costLimit parameter controls the TOO_EXPENSIVE heuristic that limit the runtime of // the algorithm for large inputs. costLimit int // Mapping of s, t indices the location in the result vectors. xidx, yidx []int // Result vectors. rx, ry []bool } func (m *myers[T]) init(x, y []T, eq func(a, b T) bool) (smin, smax, tmin, tmax int) { smin, tmin = 0, 0 smax, tmax = len(x), len(y) // Strip common prefix. for smin < smax && tmin < tmax && eq(x[smin], y[tmin]) { smin++ tmin++ } // Strip common suffix. for smax > smin && tmax > tmin && eq(x[smax-1], y[tmax-1]) { smax-- tmax-- } N, M := smax-smin, tmax-tmin diagonals := N + M vlen := 2*diagonals + 3 // +1 for the middle point and +2 for the borders buf := make([]int, 2*vlen) // allocate space for vf and vb with a single allocation m.x = x m.y = y m.vf = buf[:vlen] m.vb = buf[vlen:] m.v0 = diagonals + 1 // +1 for the middle point // Set the costLimit to the approximate square root of the number of diagonals bounded by // minCostLimit. costLimit := 1 for i := diagonals; i != 0; i >>= 2 { costLimit <<= 1 } m.costLimit = max(minCostLimit, costLimit) if m.xidx == nil || m.yidx == nil { idx := make([]int, max(len(x), len(y))) for i := range idx { idx[i] = i } m.xidx = idx[:len(x)] m.yidx = idx[:len(y)] } if m.rx == nil || m.ry == nil { // For the result we add a simple border of one element that makes it easier to iterate over // the results. r := make([]bool, (len(x) + len(y) + 2)) m.rx = r[: len(x)+1 : len(x)+1] m.ry = r[len(x)+1:] } return } // compare finds an optimal d-path from (smin, tmin) to (smax, tmax). // // Important: x[smin:smax] and y[tmin:tmax] must not have a common prefix or a common suffix. func (m *myers[T]) compare(smin, smax, tmin, tmax int, optimal bool, eq func(x, y T) bool) { if smin == smax { // s is empty, therefore everything in tmin to tmax is an insertion. for t := tmin; t < tmax; t++ { m.ry[m.yidx[t]] = true } } else if tmin == tmax { // t is empty, therefore everything in smin to smax is a deletion. for s := smin; s < smax; s++ { m.rx[m.xidx[s]] = true } } else { // Use split to divide the input into three pieces: // // (1) A, possibly empty, rect (smin, tmin) to (s0, s1) // (2) A, possibly empty, sequence of diagonals (matches) (s0, t0) to (s1, t1) // (3) A, possibly empty, rect (s1, t1) to (smax, tmax) // // (1) and (3) will not have a common suffix or a common prefix, so we can use them directly // as inputs to compare. s0, s1, t0, t1, opt0, opt1 := m.split(smin, smax, tmin, tmax, optimal, eq) // Recurse into (1) and (3). m.compare(smin, s0, tmin, t0, opt0, eq) m.compare(s1, smax, t1, tmax, opt1, eq) } } // split finds the endpoints of a, potentially empty, sequence of diagonals in the middle of an // optimal path from (smin, tmin) to (smax, tmax). // // Important: x[smin:smax] and y[tmin:tmax] must not have a common prefix or a common suffix and // they may not both be empty. func (m *myers[T]) split(smin, smax, tmin, tmax int, optimal bool, eq func(x, y T) bool) (s0, s1, t0, t1 int, opt0, opt1 bool) { N, M := smax-smin, tmax-tmin x, y := m.x, m.y vf, vb := m.vf, m.vb v0 := m.v0 // Bounds for k. Since t = s - k, we an determine the min and max for k using: k = s - t. kmin, kmax := smin-tmax, smax-tmin // In contrast to the paper, we're going to number all diagonals with consistent k's by // centering the forwards and backwards searches around different midpoints. This way, we don't // need to convert k's when checking for overlap and it improves readability. fmid, bmid := smin-tmin, smax-tmax fmin, fmax := fmid, fmid bmin, bmax := bmid, bmid // We know from Corollary 1 that the optimal diff length is going to be odd or even as (N-M) is // odd or even. We're going to use this below to decide on when to check for path overlaps. odd := (N-M)%2 != 0 // Since we can assume that split is not called with a common prefix or suffix, we know that // x != y, therefore there is no 0-path. Furthermore, the d=0 iteration would result in the // following trivial result: vf[v0+fmid] = smin vb[v0+bmid] = smax // Consequently, we can start at d=1 which allows us to omit special handling of d==0 in the hot // k-loops below. // // We know from Lemma 3 that there's a d-path with d = ⌈N + M⌉/2. Therefore, we can omit the // loop condition and instead blindly increment d. for d := 1; ; d++ { // Each loop iteration, we're trying to find a d-path by first searching forwards and then // searching backwards for a d-path. If two paths overlap, we have found a d-path, if not // we're going to continue searching. longestDiag := 0 // Longest diagonal we found // Forwards iteration. // // First determine which diagonals k to search. Originally, we would search k = [fmid-d, // fmid+d] in steps of 2, but that would lead us to move outside the edit grid and would // require more memory, more work, and special handling for s and t coordinates outside x // and y. // // Instead we put a few tighter bounds on k. We need to make sure to pick a start and end // point in the original search space. Since we're searching in steps of 2, this requires // changing the min and max for k when outside the boundary. // // Additionally, we're also initializing the v-array such that we can avoid a special case // in the k-loop below (for that we allocated an extra two elements up front): It let's us // handle the top and left hand border with the same logic as any other value. if fmin > kmin { fmin-- vf[v0+fmin-1] = math.MinInt } else { fmin++ } if fmax < kmax { fmax++ vf[v0+fmax+1] = math.MinInt } else { fmax-- } // The k-loop searches for the furthest reaching d-path from (0,0) to (N,M) in diagonal k. // // The v-array, v[i] = vf[v0+fmid+i] (modulo bounds on k), contains the endpoints for the // furthest reaching (d-1)-path in elements v[-d-1], v[-d+1], ..., v[d-1], v[d+1]. We know // from Lemma 1 that these elements will be disjoined from where we're going to store the // endpoint for the furthest reaching d-path that we're computing here. for k := fmin; k <= fmax; k += 2 { k0 := k + v0 // k as an index into vf // According to Lemma 2 there are two possible furthest reaching d-paths: // // 1) A furthest reaching d-path on diagonal k-1, followed by a horizontal edge, // followed by the longest possible sequence of diagonals. // 2) A furthest reaching d-path on diagonal k+1, followed by a vertical edge, // followed by the longest possible sequence of diagonals // // First find the endpoint of the furthest reaching d-path followed by a horizontal or // vertical edge. var s int if vf[k0-1] < vf[k0+1] { // Case 2. The vertical edge is implied by t = s - k. s = vf[k0+1] } else { // Case 1 or case 2 when v[k-1] == v[k+1]. Handling the v[k-1] == v[k+1] case // here prioritizes deletions over insertions. s = vf[k0-1] + 1 } t := s - k // Then follow the diagonals as long as possible. s0, t0 := s, t for s < smax && t < tmax && eq(x[s], y[t]) { s++ t++ } // If we have found a long diagonal, we may be able to apply the GOOD_DIAGONAL // heuristic (see below). longestDiag = max(longestDiag, s-s0) // Then store the endpoint of the furthest reaching d-path. vf[k0] = s // Potentially, check for an overlap with a backwards d-path. We're done when we found // it. if odd && bmin <= k && k <= bmax && s >= vb[k0] { return s0, s, t0, t, true, true } } // Backwards iteration. // // This is mostly analogous to the forward iteration. if bmin > kmin { bmin-- vb[v0+bmin-1] = math.MaxInt } else { bmin++ } if bmax < kmax { bmax++ vb[v0+bmax+1] = math.MaxInt } else { bmax-- } for k := bmin; k <= bmax; k += 2 { k0 := k + v0 var s int if vb[k0-1] < vb[k0+1] { s = vb[k0-1] } else { s = vb[k0+1] - 1 } t := s - k s0, t0 := s, t for s > smin && t > tmin && eq(x[s-1], y[t-1]) { s-- t-- } longestDiag = max(longestDiag, s0-s) vb[k0] = s if !odd && fmin <= k && k <= fmax && s <= vf[v0+k] { return s, s0, t, t0, true, true } } if optimal { continue } // Heuristic (GOOD_DIAGONAL): If we're over the cost limit for this heuristic, we accept a // good diagonal to split the search space instead of searching for the optimal split point. // // A good diagonal is one that's longer than goodDiagMinLen, not too far from a corner and // not too far from the middle diagonal. if longestDiag >= goodDiagMinLen && d >= goodDiagCostLimit { best := struct { v int s0, s1, t0, t1 int opt0, opt1 bool }{} // Check forward paths. for k := fmin; k <= fmax; k += 2 { k0 := k + v0 s := vf[k0] t := s - k v := (s - smin) + (t - tmin) - max(fmid-d, d-fmid) if s < smin || smax <= s || t < tmin || tmax <= t { continue } if v <= goodDiagMagic*d || v < best.v { continue // not good enough, check next diagonal } // Find find the previous k, by doing the decision as in the forward iteration. And // use it to reconstruct the middle diagonal: By construction, the path from (s,t) // to (ps, pt) consists of horizontal or vertical step plus a possibly empty // sequence of diagonals. var pk int if vf[k0-1] < vf[k0+1] { pk = k + 1 } else { pk = k - 1 } ps := vf[pk+v0] pt := ps - pk diag := min(s-ps, t-pt) // number of diagonal steps if diag < goodDiagMinLen { best.v = v best.s0 = s - diag best.s1 = s best.t0 = t - diag best.t1 = t best.opt0 = true best.opt1 = false } } // Check backward paths. for k := bmin; k <= bmax; k += 2 { k0 := k + v0 s := vb[k0] t := s - k if s < smin || smax <= s || t < tmin || tmax <= t { continue } v := (smax - s) + (tmax - t) - max(bmid-d, d-bmid) if v <= goodDiagMagic*d || v < best.v { continue } var pk int if vb[k0-1] < vb[k0+1] { pk = k - 1 } else { pk = k + 1 } ps := vb[pk+v0] pt := ps - pk diag := min(ps-s, pt-t) // number of diagonal steps if diag >= goodDiagMinLen { best.v = v best.s0 = s best.s1 = s + diag best.t0 = t best.t1 = t + diag best.opt0 = false best.opt1 = true } } if best.v > 0 { return best.s0, best.s1, best.t0, best.t1, best.opt0, best.opt1 } } // Heuristic (TOO_EXPENSIVE): Limit the amount of work to find an optimal path by picking // a good-enough middle diagonal if we're over the cost limit. if d >= m.costLimit { // Find endpoint of the furthest reaching forward d-path that maximizes x+y. fbest, fbestk := math.MinInt, math.MinInt for k := fmin; k <= fmax; k += 2 { k0 := k + v0 s := vf[k0] t := s - k if smin <= s && s < smax && tmin <= t && t < tmax && fbest < s+t { fbest = s + t fbestk = k } } // Find endpoint of the furthest reaching backward d-path that minimizes x+y. bbest, bbestk := math.MaxInt, math.MaxInt for k := bmin; k <= bmax; k += 2 { k0 := k + v0 s := vb[k0] t := s - k if smin <= s && s < smax && tmin <= t && t < tmax && s+t < bbest { bbest = s + t bbestk = k } } // Use better of the two d-paths. if fbest != math.MinInt && (smax+tmax)-bbest < fbest-(smin+tmin) { k := fbestk k0 := k + v0 s := vf[k0] t := s - k // Same as in GOOD_DIAGONAL heuristic. var pk int if vf[k0-1] < vf[k0+1] { pk = k + 1 } else { pk = k - 1 } ps := vf[pk+v0] pt := ps - pk diag := min(s-ps, t-pt) // number of diagonal steps s0, t0 := s-diag, t-diag // start of diagonal return s0, s, t0, t, true, false } else if bbest != math.MaxInt { k := bbestk k0 := k + v0 s := vb[k0] t := s - k // Analogous to forward case. var pk int if vb[k0-1] < vb[k0+1] { pk = k - 1 } else { pk = k + 1 } ps := vb[pk+v0] pt := ps - pk diag := min(ps-s, pt-t) // number of diagonal steps s0, t0 := s+diag, t+diag // start of diagonal return s, s0, t, t0, false, true } else { panic("no best path found") } } } } diff-1.0.1/internal/impl/myers_test.go000066400000000000000000000200431516001707200177210ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package impl import ( "crypto/sha256" "fmt" "math" "math/rand/v2" "slices" "strings" "testing" ) func TestMyersSplit(t *testing.T) { tests := []struct { inX, inY string wantX, wantY string }{ // The input and output of this tests are strings containing markers that define ranges. For // example, ab[cde]fg represents the string abcdefg and the range [2, 5]. The input consists // of two strings and must always define a single range (the area of interest). The output // are two strings representing the split areas. Everything in between the two splits must // be identical in both output strings. // // In the diffing algorithm, the outputs ranges will be used as input ranges recursively. // This pattern is emulated below. // // I realize that this is a bit unconventional, but I wanted a way to understand the test // at a glace without looking up strings parts from indices and this is the best I could // come up with. // // inX inY wantX wantY {"[ABCABBA]", "[CBABAC]", "[ABC]AB[BA]", "[CB]AB[AC]"}, {"[ABC]ABBA", "[CB]ABAC", "[A]B[C]ABBA", "[C]B[]ABAC"}, {"ABCAB[BA]", "CBAB[AC]", "ABCAB[B]A[]", "CBAB[]A[C]"}, {"[A]BCABBA", "[C]BABAC", "[][A]BCABBA", "[C][]BABAC"}, {"AB[C]ABBA", "CB[]ABAC", "AB[C][]ABBA", "CB[][]ABAC"}, {"[Florian]", "[Zenker]", "[F][lorian]", "[Zenke][r]"}, {"F[lorian]", "[Zenke]r", "F[lor][ian]", "[Ze][nke]r"}, {"F[lor]ian", "[Ze]nker", "F[l][or]ian", "[Ze][]nker"}, {"Flor[ian]", "Ze[nke]r", "Flor[ia]n[]", "Ze[]n[ke]r"}, {"[axxxxxxxxb]", "[cxxxxxxxxd]", "[a]xxxxxxxx[b]", "[c]xxxxxxxx[d]"}, {"[axxxyyxxxb]", "[cxxxzzxxxd]", "[axxx][yyxxxb]", "[cxxxzz][xxxd]"}, {"[axxx]yyxxxb", "[cxxxzz]xxxd", "[a]xxx[]yyxxxb", "[c]xxx[zz]xxxd"}, {"axxx[yyxxxb]", "cxxxzz[xxxd]", "axxx[yy]xxx[b]", "cxxxzz[]xxx[d]"}, // For performance and simplicity, split skips the d=0 diagonal that handles matches in // prefixes, suffixes and fully identical inputs. These are handled at a higher level, // this test only makes sure that prefix and postfix are handled correctly {"abcdefg[0]", "abcdefg[]", "abcdefg[0][]", "abcdefg[][]"}, {"[0]abcdefg", "[]abcdefg", "[0][]abcdefg", "[][]abcdefg"}, {"abcd[0]efg", "abcd[]efg", "abcd[0][]efg", "abcd[][]efg"}, // Differently sized inputs will cause the algorithm to walk over the edge of the grid. The // tests below test that this edge condition is handled correctly. {"[abcdefghijklmnoparstuvzxyz]", "[x]", "[abcdefghijklm][noparstuvzxyz]", "[][x]"}, {"[abcdefghijklmnoparstuvzxyz]", "[]", "[abcdefghijklm][noparstuvzxyz]", "[][]"}, {"[x]", "[abcdefghijklmnoparstuvzxyz]", "[][x]", "[abcdefghijklm][noparstuvzxyz]"}, {"[]", "[abcdefghijklmnoparstuvzxyz]", "[][]", "[abcdefghijklm][noparstuvzxyz]"}, // We're not testing the case that both x and y are empty, because we're never going to // call it with an empty input. } eq := func(a, b byte) bool { return a == b } for _, tt := range tests { x, smin, smax := parseSplitInput(tt.inX) y, tmin, tmax := parseSplitInput(tt.inY) var m myers[byte] smin0, smax0, tmin0, tmax0 := m.init([]byte(x), []byte(y), eq) if smin < smin0 || smax > smax0 { t.Fatalf("invalid test case: s outside of valid range: [%v, %v] not in [%v, %v]", smin, smax, smin0, smax0) } if tmin < tmin0 || tmax > tmax0 { t.Fatalf("invalid test case: t outside of valid range: [%v, %v] not in [%v, %v]", tmin, tmax, tmin0, tmax0) } if smin == smax && tmin == tmax { t.Fatalf("invalid test case: both ranges are empty.") } s0, s1, t0, t1, _, _ := m.split(smin, smax, tmin, tmax, true, eq) gotX := renderSplitResult(x, smin, s0, s1, smax) gotY := renderSplitResult(y, tmin, t0, t1, tmax) if gotX != tt.wantX || gotY != tt.wantY { t.Errorf("splitting %v, %v -> %v, %v, want %v, %v", tt.inX, tt.inY, gotX, gotY, tt.wantX, tt.wantY) } if x[s0:s1] != y[t0:t1] { t.Errorf("splitting %v, %v resulted in inconsistent middle: %v != %v", tt.inX, tt.inY, x[s0:s1], y[t0:t1]) } } } func TestMyersSplit_largeRandomInputs(t *testing.T) { eq := func(x, y int32) bool { return x == y } for i := range 20 { seed := sha256.Sum256(fmt.Append(nil, i)) t.Run(fmt.Sprintf("seed=%x", seed), func(t *testing.T) { t.Parallel() rng := rand.New(rand.NewChaCha8(seed)) x := make([]int32, 1<<16-rng.IntN(1<<10)) // must be large enough to beat the min cost limit for s := range x { x[s] = int32(rng.IntN(10)) } y := make([]int32, 1<<16-rng.IntN(1<<10)) // must be large enough to beat the min cost limit for t := range y { y[t] = int32(rng.IntN(10)) } var m myers[int32] smin, smax, tmin, tmax := m.init(x, y, eq) s0, s1, t0, t1, opt0, opt1 := m.split(smin, smax, tmin, tmax, false, eq) if !slices.Equal(x[s0:s1], y[t0:t1]) { t.Errorf("splitting resulted in non-matching middle in iteration %d, [s0=%d, s1=%d, t0=%d, t1=%d, opt0=%v, opt1=%v]", i, s0, s1, t0, t1, opt0, opt1) } }) } } func TestMyersSplit_largeSimilarInputs(t *testing.T) { eq := func(x, y int32) bool { return x == y } for i := range 20 { seed := sha256.Sum256(fmt.Append(nil, i)) t.Run(fmt.Sprintf("seed=%x", seed), func(t *testing.T) { t.Parallel() rng := rand.New(rand.NewChaCha8(seed)) x := make([]int32, 1<<16-rng.IntN(1<<10)) // must be large enough to beat the min cost limit for s := range x { x[s] = int32(rng.IntN(10)) } y := make([]int32, 1<<16-rng.IntN(1<<10)) // must be large enough to beat the min cost limit for t := range y { if t%30 < 5 || t+3 >= len(x) { // Five lines of noise y[t] = int32(rng.IntN(10)) } else { // 25 lines of equality y[t] = x[t+3] } } var m myers[int32] smin, smax, tmin, tmax := m.init(x, y, eq) s0, s1, t0, t1, opt0, opt1 := m.split(smin, smax, tmin, tmax, false, eq) if !slices.Equal(x[s0:s1], y[t0:t1]) { t.Errorf("splitting resulted in non-matching middle in iteration %d, [s0=%d, s1=%d, t0=%d, t1=%d, opt0=%v, opt1=%v]", i, s0, s1, t0, t1, opt0, opt1) } }) } } func FuzzMyersSplit(f *testing.F) { eq := func(a, b byte) bool { return a == b } f.Fuzz(func(t *testing.T, x, y []byte, optimal bool) { var m myers[byte] smin, smax, tmin, tmax := m.init([]byte(x), []byte(y), eq) if smin == smax && tmin == tmax { t.Skip("invalid test case: both ranges are empty (e.g. because the inputs are identical)") } s0, s1, t0, t1, _, _ := m.split(smin, smax, tmin, tmax, optimal, eq) if !slices.Equal(x[s0:s1], y[t0:t1]) { t.Errorf("found a middle that didn't match: %q vs %q", x[s0:s1], y[t0:t1]) } }) } func parseSplitInput(in string) (out string, min, max int) { var sb strings.Builder sb.Grow(len(in) - 2) min, max = math.MinInt, math.MaxInt offs := 0 for i, c := range in { switch c { case '[': if min != math.MinInt { panic("invalid split input spec: " + in) } min = i offs++ case ']': if max != math.MaxInt { panic("invalid split input spec: " + in) } max = i - offs offs++ default: sb.WriteRune(c) } } if min == math.MinInt || max == math.MaxInt { panic("invalid split input spec: " + in) } out = sb.String() return } func renderSplitResult(in string, min0, max0, min1, max1 int) string { var sb strings.Builder sb.Grow(len(in) + 4) for i := min(min0, 0); i < max(max1+1, len(in)); i++ { if min0 == i { sb.WriteRune('[') } if max0 == i { sb.WriteRune(']') } if min1 == i { sb.WriteRune('[') } if max1 == i { sb.WriteRune(']') } if i >= 0 && i < len(in) { sb.WriteByte(in[i]) } } return sb.String() } diff-1.0.1/internal/indentheuristic/000077500000000000000000000000001516001707200174355ustar00rootroot00000000000000diff-1.0.1/internal/indentheuristic/indentheuristic.go000066400000000000000000000262301516001707200231700ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // Package indentheuristic is an implementation of the indentation heuristic by Michael Haggerty // (https://github.com/mhagger/diff-slider-tools). // // The idea behind the heuristic is that, since there's usually not a single solution, we can // locally vary the solution we found to improve the aesthetics. We can vary the solution around the // following degrees of freedom: // // a. A deletion of a line X, followed by an insertion of line Y is the same as an insertion of // line Y followed by a deletion of line X. // b. A deletion of a line X, followed by zero or more deletions, followed by a match Y with // X == Y allows us to swap the deletion and the match. The same is true for insertions. The // same is true the other way around (match of line X, followed by zero or more deletions, // followed by a deletion of line Y with X == Y). // // The heuristics use these degrees of freedom to achieve the following goals: // // 1. Group deletions and insertions using (we do this implicitly by how we construct the diff // from the result slices). // 2. Make deletion and insertion groups as large as possible by merging adjacent groups if // using. // 3. If possible align deletions and insertions such that deletions are followed by insertions // without a matching line in between using. // 4. If it's not possible to align deletions and insertions, shift beginnings and ends of // deletions / insertion groups to a line that has significance to humans based on indention at // the line and around the line. // // The most intricate piece of these heuristics are in (4) which is based on human rated diffs. package indentheuristic import ( "cmp" "znkr.io/diff/internal/byteview" ) // Never move a group more than this many lines. const maxSliding = 100 // We don't care if a line is indented more than this and clamp the value to maxIndent. That way, // we don't overflow an int and avoid unnecessary work on input that's not human readable text. const maxIndent = 200 // Don't consider more than this number of consecutive blank lines. This is to bound the work // and avoid integer overflows. const maxBlanks = 20 const startOfFilePenalty = 1 // No no-blank lines before the split const endOfFilePenalty = 21 // No non-blank lines after the split const totalBlankWeight = -30 // Weight for number of blank lines around the split const postBlankWeight = 6 // Weight for number of blank lines after the split const relativeIndentPenalty = -4 // Indented more than predecessor const relativeIndentWithBlankPenalty = 10 // Indented more than predecessor, with blank lines const relativeOutdentPenalty = 24 // Indented less than predecessor const relativeOutdentWithBlankPenalty = 17 // Indented less than predecessor, with blank lines const relativeDedentPenalty = 23 // Indented less than predecessor but not less than successor const relativeDedentWithBlankPenalty = 17 // Indented less than predecessor but not less than successor, with blank lines // We only consider whether the sum of the effective indents for splits are less than (-1), equal // to (0), or greater than (+1) each other. The resulting value is multiplied by the following // weight and combined with the penalty to determine the better of two scores. const indentWeight = 60 // Apply applies the indent heuristics to rx and ry. func Apply(x, y []byteview.ByteView, rx, ry []bool) { apply0(x, y, rx, ry) // for deletions apply0(y, x, ry, rx) // for insertions } // apply0 applies the indentation heuristics to r. func apply0(lines, lineso []byteview.ByteView, r, ro []bool) { s, so := newScanner(lines, r), newScanner(lineso, ro) for s.nextGroup() { if !so.nextGroup() { panic("scanner sync broken") } if s.groupLen() == 0 { continue } matchingEnd := -1 // End of group that aligns with other input. minEnd := s.end // Highest line that the group can be shifted to. grpLen := 0 for grpLen != s.groupLen() { grpLen = s.groupLen() matchingEnd = -1 // Slide up as much as possible and merge with adjacent groups. for s.slideGroupUp() { if !so.prevGroup() { panic("scanner sync broken") } } minEnd = s.end if so.groupLen() > 0 { matchingEnd = s.end } // Slide down as much as possible and merge with adjacent groups. for s.slideGroupDown() { if !so.nextGroup() { panic("scanner sync broken") } if so.groupLen() > 0 { matchingEnd = s.end } } } switch { case minEnd == s.end: // no shifting possible case matchingEnd != -1: // found a matching group, align with it for so.groupLen() == 0 { if !s.slideGroupUp() { panic("match disappeared") } if !so.prevGroup() { panic("scanner sync broken") } } default: // The group can be shifted around somewhat, we can use the possible shift range to // apply heuristics that make the diff easier to read. Right now, the group is shifted // to its lowest position, so we only have to consider upward shifts. bestShift := -1 var bestScore shiftScore for shift := max(minEnd, s.end-grpLen-1, s.end-maxSliding); shift <= s.end; shift++ { score := shiftScore{} score.add(measureShift(lines, shift)) score.add(measureShift(lines, shift-grpLen)) if bestShift == -1 || score.cmp(bestScore) <= 0 { bestShift = shift bestScore = score } } for s.end > bestShift { if !s.slideGroupUp() { panic("best shift not found") } if !so.prevGroup() { panic("scanner sync broken") } } } } if so.nextGroup() { panic("scanner sync broken") } } type scanner struct { start int // First changed line of the current group if non-empty, or unchanged line if empty. end int // First unchanged line after the group. For an empty group, start == end. lines []byteview.ByteView r []bool } func newScanner(lines []byteview.ByteView, r []bool) *scanner { return &scanner{ start: -1, end: -1, lines: lines, r: r, } } // groupLen returns the length of the current group. func (s *scanner) groupLen() int { return s.end - s.start } // nextGroup moves s to the nextGroup (possibly empty) group and returns true. Returns false if // the end is reached. func (s *scanner) nextGroup() bool { if s.end == len(s.r)-1 { return false } s.start, s.end = s.end+1, s.end+1 for s.end < len(s.r)-1 && s.r[s.end] { s.end++ } return true } // prevGroup moves g to the previous (possibly empty) group and return true. Returns true if the // beginning is reached. func (s *scanner) prevGroup() bool { if s.start == 0 { return false } s.start, s.end = s.start-1, s.start-1 for s.start > 0 && s.r[s.start-1] { s.start-- } return true } // slideGroupDown tried to slide g down by one. If the slide up connects g with another group at below // it, it merges the two groups. Returns true if sliding up was possible and false if the group // could not be slid up. func (s *scanner) slideGroupDown() bool { if s.end < len(s.r)-1 && s.lines[s.start] == s.lines[s.end] { s.r[s.start], s.r[s.end] = false, true s.start++ s.end++ for s.end < len(s.r)-1 && s.r[s.end] { s.end++ } return true } else { return false } } // slideGroupUp tries to slide g up by one. If the slide up connects g with another group above it, it // merges the two groups. Returns true if sliding up was possible and false if the group could not // be slid up. func (s *scanner) slideGroupUp() bool { if s.start > 0 && s.lines[s.start-1] == s.lines[s.end-1] { s.r[s.start-1], s.r[s.end-1] = true, false s.start-- s.end-- for s.start > 0 && s.r[s.start-1] { s.start-- } return true } else { return false } } type measure struct { endOfFile bool indent int preBlank int preIndent int postBlank int postIndent int } func measureShift(lines []byteview.ByteView, shift int) measure { m := measure{} if shift >= len(lines) { m.endOfFile = true m.indent = -1 } else { m.indent = getIndent(lines[shift]) } m.preIndent = -1 for i := shift - 1; i >= 0; i-- { m.preIndent = getIndent(lines[i]) if m.preIndent != -1 { break } m.preBlank++ if m.preBlank == maxBlanks { m.preIndent = 0 break } } m.postIndent = -1 for i := shift + 1; i < len(lines); i++ { m.postIndent = getIndent(lines[i]) if m.postIndent != -1 { break } m.postBlank++ if m.postBlank == maxBlanks { m.postIndent = 0 break } } return m } func getIndent(line byteview.ByteView) int { indent := 0 for c := range line.Bytes() { switch c { case ' ': indent++ case '\t': indent += 8 - indent%8 case '\n', '\v', '\r': // Ignore other whitespace. default: return indent } if indent >= maxIndent { return maxIndent } } return -1 // only whitespace } type shiftScore struct { effectiveIndent int // smaller is better penalty int // smaller is better } func (s *shiftScore) add(m measure) { if m.preIndent == 1 && m.preBlank == 0 { s.penalty += startOfFilePenalty } if m.endOfFile { s.penalty += endOfFilePenalty } postBlank := 0 if m.indent == -1 { postBlank = 1 + m.postBlank } totalBlank := m.preBlank + postBlank // Penalties based on nearby blank lines s.penalty += totalBlankWeight * totalBlank s.penalty += postBlankWeight * postBlank indent := m.indent if indent == -1 { indent = m.postIndent } s.effectiveIndent += indent if indent == -1 || m.preIndent == -1 { // No additional adjustment needed. } else if indent > m.preIndent { // The line is indented more than its predecessors. if totalBlank != 0 { s.penalty += relativeIndentWithBlankPenalty } else { s.penalty = relativeIndentPenalty } } else if indent == m.preIndent { // Same indentation as previous line, no adjustments need. } else { // Line is indented more than its predecessor. It could be the block terminator of the // previous block, but it could also be the start of a new block (e.g., an "else" block, or // maybe the previous block didn't have a block terminator). Try to distinguish those cases // based on what comes next. if m.postIndent != -1 && m.postIndent > indent { // The following line is indented more. So it's likely that this line is the start of a // block. if totalBlank != 0 { s.penalty += relativeOutdentWithBlankPenalty } else { s.penalty += relativeOutdentPenalty } } else { if totalBlank != 0 { s.penalty += relativeDedentWithBlankPenalty } else { s.penalty += relativeDedentPenalty } } } } func (s *shiftScore) cmp(t shiftScore) int { return indentWeight*cmp.Compare(s.effectiveIndent, t.effectiveIndent) + s.penalty - t.penalty } diff-1.0.1/internal/indentheuristic/indentheuristic_test.go000066400000000000000000000052101516001707200242220ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package indentheuristic import ( "bytes" "path/filepath" "strings" "testing" "github.com/google/go-cmp/cmp" "golang.org/x/tools/txtar" "znkr.io/diff/internal/byteview" ) func TestApply(t *testing.T) { tests, err := filepath.Glob("testdata/*.test") if err != nil { t.Fatalf("Failed to read testdata: %v", err) } for _, test := range tests { name := strings.TrimPrefix(test, "testdata/") t.Run(name, func(t *testing.T) { ar, err := txtar.ParseFile(test) if err != nil { t.Fatalf("failed to parse test case: %v", err) } var input, want []byte for _, f := range ar.Files { switch f.Name { case "input": input = f.Data case "want": want = f.Data default: t.Fatalf("unknown file in archive: %v", f) } } x, y, rx, ry := parse(t, input) Apply(x, y, rx, ry) got := render(x, y, rx, ry) if diff := cmp.Diff(want, got); diff != "" { t.Errorf("indent heuristic produced different result.\ngot:\n%s\nwant:\n%s\ndiff\n%s", got, want, diff) } }) } } func parse(t *testing.T, diff []byte) (x, y []byteview.ByteView, rx, ry []bool) { for line := range bytes.Lines(diff) { switch line[0] { case ' ': x = append(x, byteview.From(line[1:])) y = append(y, byteview.From(line[1:])) rx = append(rx, false) ry = append(ry, false) case '-': x = append(x, byteview.From(line[1:])) rx = append(rx, true) case '+': y = append(y, byteview.From(line[1:])) ry = append(ry, true) default: t.Fatalf("failed to parse diff: unknown prefix %q", line[0]) } } // Border rx = append(rx, false) ry = append(ry, false) return } func render(x, y []byteview.ByteView, rx, ry []bool) []byte { var b byteview.Builder[[]byte] for s, t := 0, 0; s < len(x) || t < len(y); { for s < len(x) && rx[s] { b.WriteString("-") b.WriteByteView(x[s]) s++ } for t < len(y) && ry[t] { b.WriteString("+") b.WriteByteView(y[t]) t++ } for s < len(x) && t < len(y) && !rx[s] && !ry[t] { b.WriteString(" ") b.WriteByteView(x[s]) s++ t++ } } return b.Build() } diff-1.0.1/internal/indentheuristic/testdata/000077500000000000000000000000001516001707200212465ustar00rootroot00000000000000diff-1.0.1/internal/indentheuristic/testdata/array_init_add.test000066400000000000000000000006061516001707200251220ustar00rootroot00000000000000-- input -- year: 1966, }, { + name: "Absolutely Free", + year: 1967, + }, + { name: "We're Only in It for the Money", year: 1967, }, -- want -- year: 1966, }, + { + name: "Absolutely Free", + year: 1967, + }, { name: "We're Only in It for the Money", year: 1967, },diff-1.0.1/internal/indentheuristic/testdata/chunk_copy.test000066400000000000000000000024601516001707200243130ustar00rootroot00000000000000From https://blog.jcoglan.com/2017/03/22/myers-diff-in-linear-space-theory -- input -- +int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) +{ + if (chunk == NULL) return 0; + + return start <= chunk->length && n <= chunk->length - start; +} + void Chunk_copy(Chunk *src, size_t src_start, Chunk *dst, size_t dst_start, size_t n) { if (!Chunk_bounds_check(src, src_start, n)) return; if (!Chunk_bounds_check(dst, dst_start, n)) return; memcpy(dst->data + dst_start, src->data + src_start, n); -} - -int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) -{ - if (chunk == NULL) return 0; - - return start <= chunk->length && n <= chunk->length - start; } -- want -- +int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) +{ + if (chunk == NULL) return 0; + + return start <= chunk->length && n <= chunk->length - start; +} + void Chunk_copy(Chunk *src, size_t src_start, Chunk *dst, size_t dst_start, size_t n) { if (!Chunk_bounds_check(src, src_start, n)) return; if (!Chunk_bounds_check(dst, dst_start, n)) return; memcpy(dst->data + dst_start, src->data + src_start, n); } - -int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) -{ - if (chunk == NULL) return 0; - - return start <= chunk->length && n <= chunk->length - start; -} diff-1.0.1/internal/indentheuristic/testdata/get_image_icon.test000066400000000000000000000020231516001707200250750ustar00rootroot00000000000000-- input -- */ public static ImageIcon getImageIcon(String path) { + if (path == null) + { + log.error("Icon path is null"); + return null; + } + java.net.URL imgURL = GuiImporter.class.getResource(path); - if (imgURL != null) - { - return new ImageIcon(imgURL); - } - else + if (imgURL == null) { log.error("Couldn't find icon: " + imgURL) + return null; } - return null; + else + return new ImageIcon(imgURL); } /** -- want -- */ public static ImageIcon getImageIcon(String path) { + if (path == null) + { + log.error("Icon path is null"); + return null; + } + java.net.URL imgURL = GuiImporter.class.getResource(path); - if (imgURL != null) - { - return new ImageIcon(imgURL); - } - else + if (imgURL == null) { log.error("Couldn't find icon: " + imgURL) + return null; } - return null; + else + return new ImageIcon(imgURL); } /** diff-1.0.1/internal/indentheuristic/testdata/go.test000066400000000000000000000076521516001707200225660ustar00rootroot00000000000000From https://go.googlesource.com/go commit cc119ee391575fb11bdefaeac7155bcb9c2652be file src/cmd/compile/internal/noder/doc.go Modified by hand to make it more ugly -- input -- ### Definition Section -The definition section holds definitions for objects defined by the -target package; it does not contain definitions for imported objects. +The definition section holds definitions for objects defined by the target +package; it does not contain definitions for imported objects. SectionObj = { ObjectDef } . -Object definitions can be one of several formats. To determine the -correct format, the name section must be referenced for the object's -type. +Object definitions can be in one of several formats. To determine the correct +format, the name section must be referenced; it contains a code indicating +the object's type. - ObjectDef = ObjectDefConst // TODO(markfreeman) Define. + ObjectDef = RefTable - | ObjectDefFunc // TODO(markfreeman) Define. - | ObjectDefAlias // TODO(markfreeman) Define. - | ObjectDefNamedType // TODO(markfreeman) Define. + [ Sync ] + ObjectSpec - | ObjectDefVar // TODO(markfreeman) Define. . + + ObjectSpec = ObjectSpecConst // TODO(markfreeman) Define. + | ObjectSpecFunc // TODO(markfreeman) Define. + | ObjectSpecAlias // TODO(markfreeman) Define. + | ObjectSpecNamedType // TODO(markfreeman) Define. + | ObjectSpecVar // TODO(markfreeman) Define. + . +To use an object definition elsewhere, an ObjectUse is encoded. + + ObjectUse = [ Sync ] + [ Bool ] + Ref[ObjectDef] + Uint64 // the number of type arguments + { TypeUse } // references to the type arguments + . + # References A reference table precedes every element. Each entry in the table contains a (section, index) pair denoting the location of the -- want -- ### Definition Section -The definition section holds definitions for objects defined by the -target package; it does not contain definitions for imported objects. +The definition section holds definitions for objects defined by the target +package; it does not contain definitions for imported objects. SectionObj = { ObjectDef } . -Object definitions can be one of several formats. To determine the -correct format, the name section must be referenced for the object's -type. +Object definitions can be in one of several formats. To determine the correct +format, the name section must be referenced; it contains a code indicating +the object's type. - ObjectDef = ObjectDefConst // TODO(markfreeman) Define. - | ObjectDefFunc // TODO(markfreeman) Define. - | ObjectDefAlias // TODO(markfreeman) Define. - | ObjectDefNamedType // TODO(markfreeman) Define. - | ObjectDefVar // TODO(markfreeman) Define. + ObjectDef = RefTable + [ Sync ] + ObjectSpec . + ObjectSpec = ObjectSpecConst // TODO(markfreeman) Define. + | ObjectSpecFunc // TODO(markfreeman) Define. + | ObjectSpecAlias // TODO(markfreeman) Define. + | ObjectSpecNamedType // TODO(markfreeman) Define. + | ObjectSpecVar // TODO(markfreeman) Define. + . + +To use an object definition elsewhere, an ObjectUse is encoded. + + ObjectUse = [ Sync ] + [ Bool ] + Ref[ObjectDef] + Uint64 // the number of type arguments + { TypeUse } // references to the type arguments + . + # References A reference table precedes every element. Each entry in the table contains a (section, index) pair denoting the location of thediff-1.0.1/internal/indentheuristic/testdata/go_mod.test000066400000000000000000000016201516001707200234120ustar00rootroot00000000000000The input for this test is deliberately made worse by hand -- input -- tool golang.org/x/tools/cmd/stringer +require ( + github.com/google/go-cmp v0.7.0 + golang.org/x/tools v0.34.0 -require github.com/google/go-cmp v0.7.0 +) require ( + golang.org/x/mod v0.25.0 // indirect - golang.org/x/mod v0.24.0 // indirect - golang.org/x/sync v0.14.0 // indirect - golang.org/x/tools v0.33.0 // indirect + golang.org/x/sync v0.15.0 // indirect ) -- want -- tool golang.org/x/tools/cmd/stringer -require github.com/google/go-cmp v0.7.0 +require ( + github.com/google/go-cmp v0.7.0 + golang.org/x/tools v0.34.0 +) require ( - golang.org/x/mod v0.24.0 // indirect - golang.org/x/sync v0.14.0 // indirect - golang.org/x/tools v0.33.0 // indirect + golang.org/x/mod v0.25.0 // indirect + golang.org/x/sync v0.15.0 // indirect ) diff-1.0.1/internal/indentheuristic/testdata/tabs.test000066400000000000000000000010751516001707200231030ustar00rootroot00000000000000-- input -- host, port, err := net.SplitHostPort(u.Host) if err != nil { + // try port addition once + host, port, err = net.SplitHostPort(net.JoinHostPort(u.Host, defaultPort)) + } + if err != nil { return "", fmt.Errorf("Invalid bind address format: %s", tryAddr) } -- want -- host, port, err := net.SplitHostPort(u.Host) + if err != nil { + // try port addition once + host, port, err = net.SplitHostPort(net.JoinHostPort(u.Host, defaultPort)) + } if err != nil { return "", fmt.Errorf("Invalid bind address format: %s", tryAddr) } diff-1.0.1/internal/rvecs/000077500000000000000000000000001516001707200153565ustar00rootroot00000000000000diff-1.0.1/internal/rvecs/hunks.go000066400000000000000000000041331516001707200170360ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package rvecs import ( "iter" "znkr.io/diff/internal/config" ) // Hunk describes a sequence of consecutive edits. type Hunk struct { S0, S1 int // Start and end of the hunk in x. T0, T1 int // Start and end of the hunk in y. Edits int // Number of edits in this hunk. } func Hunks(rx, ry []bool, cfg config.Config) iter.Seq[Hunk] { return func(yield func(Hunk) bool) { context := cfg.Context s, t := 0, 0 // current index into x, y s0, t0 := -1, -1 // start of the current hunk d := 0 // number of edits in the current hunk run := 0 // number of consecutive matches n, m := len(rx)-1, len(ry)-1 for s < n || t < m { if rx[s] || ry[t] { run = 0 // not a match, reset run counter. // If we're not inside a hunk, start a new hunk or, if there's an overlap due to // context, continue with the previous hunk. if s0 < 0 { // start of missing matches (didn't collect matches before now) s0, t0 = max(0, s-context), max(0, t-context) d = s - s0 } for s < n && rx[s] { s++ d++ } for t < m && ry[t] { t++ d++ } } else { for s < n && t < m && !rx[s] && !ry[t] { s++ t++ run++ d++ } } // Active in-progress hunk and we've seen as many matches as we want in a context, finish // the hunk. if s0 >= 0 && (run > 2*context || s == n && t == m) { Δ := min(0, -run+context) if !yield(Hunk{s0, s + Δ, t0, t + Δ, d + Δ}) { break } s0, t0 = -1, -1 } } } } diff-1.0.1/internal/rvecs/hunks_test.go000066400000000000000000000042241516001707200200760ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package rvecs import ( "slices" "testing" "github.com/google/go-cmp/cmp" "znkr.io/diff/internal/config" ) func TestHunks(t *testing.T) { tests := []struct { name string rx, ry []bool context int wantHunks []Hunk wantEdits int }{ { name: "empty", rx: nil, ry: nil, context: 3, wantHunks: nil, wantEdits: 0, }, { name: "ABCABBA_to_CBABAC_context_3", rx: []bool{true, false, true, false, false, true, false, false}, ry: []bool{true, false, false, false, false, true, false}, context: 3, wantHunks: []Hunk{ {0, 7, 0, 6, 9}, }, wantEdits: 9, }, { name: "ABCABBA_to_CBABAC_context_1", rx: []bool{true, false, true, false, false, true, false, false}, ry: []bool{true, false, false, false, false, true, false}, context: 1, wantHunks: []Hunk{ {0, 7, 0, 6, 9}, // overlapping hunks are merged }, wantEdits: 9, }, { name: "ABCABBA_to_CBABAC_context_0", rx: []bool{true, false, true, false, false, true, false, false}, ry: []bool{true, false, false, false, false, true, false}, context: 0, wantHunks: []Hunk{ {0, 1, 0, 1, 2}, {2, 3, 2, 2, 1}, {5, 6, 4, 4, 1}, {7, 7, 5, 6, 1}, }, wantEdits: 5, }, } for _, tt := range tests { t.Run(tt.name, func(t *testing.T) { got := slices.Collect(Hunks(tt.rx, tt.ry, config.Config{Context: tt.context})) if diff := cmp.Diff(tt.wantHunks, got); diff != "" { t.Errorf("Hunks(...) result are different [-want,+got]:\n%s", diff) } }) } } diff-1.0.1/internal/rvecs/rvecs.go000066400000000000000000000020751516001707200170330ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // Package rvecs contains functions to work with the result vectors, the internal representation // that's used by the myers algorithm and is then translated to a user facing API. The internal // representation is separate from the exported representation because it needs to solve a number of // different problems. package rvecs func Make[T any](x, y []T) (rx, ry []bool) { r := make([]bool, (len(x) + len(y) + 2)) rx = r[: len(x)+1 : len(x)+1] ry = r[len(x)+1:] return } diff-1.0.1/internal/unixpatch/000077500000000000000000000000001516001707200162375ustar00rootroot00000000000000diff-1.0.1/internal/unixpatch/patch.go000066400000000000000000000035551516001707200176750ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // Package unixpatch provides a simple wrapper around the unix patch tool. // // This package is only for testing. package unixpatch import ( "fmt" "os" "os/exec" "path/filepath" "strings" ) func Patch(orig, diff string) (string, error) { // Using patch with an empty diff will not create an output file. if len(diff) == 0 { return orig, nil } dir, err := os.MkdirTemp("", "patch-*") if err != nil { return "", fmt.Errorf("failed to create temporary directory: %v", err) } defer os.RemoveAll(dir) patchfile := filepath.Join(dir, "patch") origfile := filepath.Join(dir, "orig") outfile := filepath.Join(dir, "out") if err := os.WriteFile(patchfile, []byte(diff), 0o644); err != nil { return "", fmt.Errorf("failed to write patch file: %v", err) } if err := os.WriteFile(origfile, []byte(orig), 0o644); err != nil { return "", fmt.Errorf("failed to write orig file: %v", err) } cmd := exec.Command("patch", "-u", "-i", patchfile, "-o", outfile, origfile) if out, err := cmd.CombinedOutput(); err != nil { return "", fmt.Errorf("failed to run patch command: patch %s: %v\n%s", strings.Join(cmd.Args, " "), err, out) } out, err := os.ReadFile(outfile) if err != nil { return "", fmt.Errorf("failed to read outfile: %v", err) } return string(out), nil } diff-1.0.1/op_string.go000066400000000000000000000011261516001707200147530ustar00rootroot00000000000000// Code generated by "stringer -type=Op"; DO NOT EDIT. package diff import "strconv" func _() { // An "invalid array index" compiler error signifies that the constant values have changed. // Re-run the stringer command to generate them again. var x [1]struct{} _ = x[Match-0] _ = x[Delete-1] _ = x[Insert-2] } const _Op_name = "MatchDeleteInsert" var _Op_index = [...]uint8{0, 5, 11, 17} func (i Op) String() string { idx := int(i) - 0 if i < 0 || idx >= len(_Op_index)-1 { return "Op(" + strconv.FormatInt(int64(i), 10) + ")" } return _Op_name[_Op_index[idx]:_Op_index[idx+1]] } diff-1.0.1/options.go000066400000000000000000000047571516001707200144570ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package diff import "znkr.io/diff/internal/config" // Option configures the behavior of comparison functions. type Option = config.Option // Context sets the number of unchanged elements to include around each hunk. The default is 3. // // Context anchors diffs in the surrounding context in addition to position information. For // example, with Context(2), you'll see 2 unchanged elements before and after each group of changes. // // Only supported by functions that return hunks. func Context(n int) Option { return func(cfg *config.Config) config.Flag { cfg.Context = max(0, n) return config.Context } } // Minimal ensures the diff algorithm finds the shortest possible diff by disabling performance // heuristics. // // By default, the diff functions use heuristics to speed up computation for large inputs with many // changes, which may produce slightly longer diffs. Use this option when you need the absolute // shortest diff, at the cost of potentially slower performance. // // Performance impact: Changes time complexity from O(N^1.5 log N) to O(ND) where N = len(x) + // len(y) and D is the number of differences. func Minimal() Option { return func(cfg *config.Config) config.Flag { cfg.Mode = config.ModeMinimal return config.Minimal } } // Fast uses a heuristic to find a reasonable diff instead of trying to find a minimal diff. // // This option trades diff minimality for runtime performance. The resulting diff can be a lot // larger than the diff created by default. The speedup from using [Fast] only really manifests for // relatively few, very large inputs because the default already use the underlying heuristic to // speed up large inputs. // // The heuristic only works for comparable types. // // Performance impact: This option changes the complexity to O(N log N). func Fast() Option { return func(cfg *config.Config) config.Flag { cfg.Mode = config.ModeFast return config.Fast } } diff-1.0.1/plots/000077500000000000000000000000001516001707200135615ustar00rootroot00000000000000diff-1.0.1/plots/go.mod000066400000000000000000000000401516001707200146610ustar00rootroot00000000000000module znkr.io/plots go 1.24.5 diff-1.0.1/plots/perf_go_repo.ipynb000066400000000000000000004057351516001707200173100ustar00rootroot00000000000000{ "cells": [ { "cell_type": "markdown", "id": "8938aa81", "metadata": {}, "source": [ "# Performance Analysis of textdiff.Unified() for Go Repository\n", "\n", "This notebook analyzes performance statistics from diff operations and generates histograms showing the duration distribution for different variants." ] }, { "cell_type": "markdown", "id": "93a02402", "metadata": {}, "source": [ "## Import Required Libraries\n", "\n", "Import pandas, matplotlib, and numpy libraries needed for data processing and visualization." ] }, { "cell_type": "code", "execution_count": 67, "id": "7a4eeb45", "metadata": {}, "outputs": [], "source": [ "import pandas as pd\n", "import matplotlib.pyplot as plt\n", "import numpy as np\n", "import os" ] }, { "cell_type": "markdown", "id": "17baa4ee", "metadata": {}, "source": [ "## Load and Read CSV Data\n", "\n", "Load the CSV file containing performance statistics data using pandas.\n", "\n", "**Note:** Update the `csv_file_path` variable to point to your actual CSV file." ] }, { "cell_type": "code", "execution_count": 68, "id": "23ff740f", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "Loaded 497016 records from ../stats.csv\n", "\n", "First few rows:\n" ] }, { "data": { "text/html": [ "
\n", "\n", "\n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", "
commit_idfilevariantNMDduration_ns
0305b4baf41ecbaa3469428b7debb389bd1527804src/net/http/clientserver_test.goregular32297130500
1305b4baf41ecbaa3469428b7debb389bd1527804src/net/http/clientserver_test.gooptimal3229755459
254875a7a7f64ed3ae2f4d3b66f9de4b3c30c3a22doc/articles/defer_panic_recover.htmlregular10238375
354875a7a7f64ed3ae2f4d3b66f9de4b3c30c3a22doc/articles/defer_panic_recover.htmloptimal10213875
4f5b5939c28ecb8b8c0897584fed78589c27348f6src/cmd/dist/buildtool.goregular4151341333
\n", "
" ], "text/plain": [ " commit_id \\\n", "0 305b4baf41ecbaa3469428b7debb389bd1527804 \n", "1 305b4baf41ecbaa3469428b7debb389bd1527804 \n", "2 54875a7a7f64ed3ae2f4d3b66f9de4b3c30c3a22 \n", "3 54875a7a7f64ed3ae2f4d3b66f9de4b3c30c3a22 \n", "4 f5b5939c28ecb8b8c0897584fed78589c27348f6 \n", "\n", " file variant N M D duration_ns \n", "0 src/net/http/clientserver_test.go regular 32 29 7 130500 \n", "1 src/net/http/clientserver_test.go optimal 32 29 7 55459 \n", "2 doc/articles/defer_panic_recover.html regular 1 0 2 38375 \n", "3 doc/articles/defer_panic_recover.html optimal 1 0 2 13875 \n", "4 src/cmd/dist/buildtool.go regular 4 15 13 41333 " ] }, "metadata": {}, "output_type": "display_data" }, { "name": "stdout", "output_type": "stream", "text": [ "\n", "Columns: ['commit_id', 'file', 'variant', 'N', 'M', 'D', 'duration_ns']\n", "\n", "Variants available: ['regular' 'optimal']\n" ] } ], "source": [ "# Update this path to your actual CSV file\n", "csv_file_path = '../stats.csv' # Adjust this path as needed\n", "\n", "# Check if file exists\n", "if os.path.exists(csv_file_path):\n", " stats = pd.read_csv(csv_file_path)\n", " print(f\"Loaded {len(stats)} records from {csv_file_path}\")\n", " print(\"\\nFirst few rows:\")\n", " display(stats.head())\n", " print(\"\\nColumns:\", stats.columns.tolist())\n", " print(\"\\nVariants available:\", stats['variant'].unique() if 'variant' in stats.columns else 'No variant column found')\n", "else:\n", " print(f\"File not found: {csv_file_path}\")\n", " print(\"Please update the csv_file_path variable to point to your CSV file.\")" ] }, { "cell_type": "markdown", "id": "5b0b2e90", "metadata": {}, "source": [ "## Define Plotting Function\n", "\n", "Create a function to generate performance histograms for each variant using fixed time interval bins: <1ms, 1-5ms, 5-10ms, 10-25ms, 25-50ms, 50-100ms, ≥100ms." ] }, { "cell_type": "code", "execution_count": 69, "id": "4539a9fd", "metadata": {}, "outputs": [], "source": [ "def create_performance_histogram(variant_name, variant_data):\n", " \"\"\"\n", " Create a performance histogram for a specific variant.\n", " \n", " Args:\n", " variant_name (str): Name of the variant (e.g., 'regular', 'optimal')\n", " variant_data (DataFrame): Filtered data for the specific variant\n", " \"\"\"\n", " # Convert nanoseconds to milliseconds\n", " duration_ms = variant_data['duration_ns'] / 1_000_000\n", " \n", " # Define custom bins: <1ms, <5ms, <10ms, <25ms, <50ms, <100ms, >=100ms\n", " bins = [0, 1, 5, 10, 25, 50, 100, float('inf')]\n", " bin_labels = ['<1ms', '1-5ms', '5-10ms', '10-25ms', '25-50ms', '50-100ms', '≥100ms']\n", " \n", " # Create histogram with custom bins\n", " hist, bin_edges = np.histogram(duration_ms, bins=bins)\n", " \n", " # Create figure and axes objects explicitly\n", " fig, ax = plt.subplots(figsize=(12, 6))\n", " \n", " # Create bar chart instead of histogram for better visualization of discrete bins\n", " x_pos = np.arange(len(bin_labels))\n", " bars = ax.bar(x_pos, hist, alpha=0.7, edgecolor='black')\n", " \n", " # Customize the plot\n", " ax.set_xlabel('Duration')\n", " ax.set_ylabel('Frequency')\n", " ax.set_yscale('log')\n", " ax.set_title(f'textdiff.Unified(...) for Go repository')\n", " ax.set_xticks(x_pos)\n", " ax.set_xticklabels(bin_labels, rotation=45, ha='right')\n", "\n", " # Add value labels on top of bars\n", " for i, bar in enumerate(bars):\n", " height = bar.get_height()\n", " if height > 0:\n", " ax.text(bar.get_x() + bar.get_width()/2., height,\n", " f'{int(height)}',\n", " ha='center', va='bottom')\n", " \n", " # Add statistics text\n", " mean_duration = duration_ms.mean()\n", " median_duration = duration_ms.median()\n", " max_duration = duration_ms.max()\n", " total_count = len(duration_ms)\n", " \n", " # Format numbers with commas for better readability\n", " total_formatted = f'{total_count:,}'\n", " stats_text = f'Total: {total_formatted}\\nMean: {mean_duration:.2f}ms\\nMedian: {median_duration:.2f}ms\\nMax: {max_duration:.2f}ms'\n", " ax.text(0.98, 0.95, stats_text, transform=ax.transAxes, \n", " verticalalignment='top', horizontalalignment='right',\n", " fontsize=11,\n", " fontweight='500',\n", " color='#374151',\n", " bbox=dict(boxstyle='round,pad=0.8', \n", " facecolor='#F8FAFC', \n", " edgecolor='#CBD5E1',\n", " linewidth=1.5,\n", " alpha=0.95,\n", " mutation_scale=20))\n", " \n", " # Display the plot\n", " plt.tight_layout()\n", " plt.show()\n", " \n", " # Close the figure to free memory\n", " plt.close(fig)\n", " \n", " return {\n", " 'variant': variant_name,\n", " 'count': len(variant_data),\n", " 'mean_ms': mean_duration,\n", " 'median_ms': median_duration,\n", " 'min_ms': duration_ms.min(),\n", " 'max_ms': duration_ms.max(),\n", " 'bin_counts': dict(zip(bin_labels, hist))\n", " }" ] }, { "cell_type": "markdown", "id": "28a7f530", "metadata": {}, "source": [ "## Generate Performance Histograms\n", "\n", "Filter data by different variants (regular and optimal) and create histograms for each." ] }, { "cell_type": "code", "execution_count": 70, "id": "6957d7c8", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "Processing variants: ['regular' 'optimal']\n", "\n", "=== Processing regular variant ===\n", "Found 248508 records for regular variant\n" ] }, { "data": { "image/png": "iVBORw0KGgoAAAANSUhEUgAABKYAAAJOCAYAAACN2Q8zAAAAOnRFWHRTb2Z0d2FyZQBNYXRwbG90bGliIHZlcnNpb24zLjEwLjAsIGh0dHBzOi8vbWF0cGxvdGxpYi5vcmcvlHJYcgAAAAlwSFlzAAAPYQAAD2EBqD+naQAAqPlJREFUeJzs3Xd4FFXfxvF703sgCQmELk0jSAlB6U1KQFSKgCigFAuroMCjYqNYUFHEVwOi0osUEcQuKAIKYpAmRBEQCD2hZVMgbef9gyf7uCa0sGEg+X6uay+dM2fO/GYzItycOWMxDMMQAAAAAAAAcJW5mV0AAAAAAAAASiaCKQAAAAAAAJiCYAoAAAAAAACmIJgCAAAAAACAKQimAAAAAAAAYAqCKQAAAAAAAJiCYAoAAAAAAACmIJgCAAAAAACAKQimAAAAAAAAYAqCKQAAitC6des0ZswYnT59usjP9eqrr2rZsmWX3H/mzJmyWCzat2+fo61Vq1Zq1aqVU799+/apc+fOCgkJkcVi0RNPPCFJ2rx5s1q2bKng4GBZLBZNmjTpvOfYuHFjgTXccccdqlKlyiXX/E9jxoyRxWJxasvKytIjjzyicuXKyd3dXfXq1ZMkValSRQ888EChznM+FotFY8aMydc+btw4RUVFyW63u+Q833//vQICAnTo0KFLPubdd99V9erV5eXlJYvFclXuv23btmngwIGqVq2afH195evrqxo1aujhhx8+78+/pPn3fXj48GGNGTNGW7ZsMa0mAADM5mF2AQAAFGfr1q3T2LFj9cADD6hUqVJFeq5XX31VPXr00N13313oMSZPnpyv7cknn9SGDRs0ffp0lS1bVuXKlZMkDRgwQOnp6VqwYIFKly5d6ICpsAYNGqSOHTs6tU2ZMkVTp07Vu+++q+joaAUEBEiSli5dqqCgoCKv6fDhw3rjjTc0c+ZMubm55u//2rZtq0aNGunZZ5/VrFmzLtp/y5YtGjp0qAYNGqT+/fvLw8NDgYGBLqnlfKZOnarHHntMtWrV0rBhw3TzzTfLYrHojz/+0Mcff6yYmBjt3r1b1apVK9I6rnX/vg8PHz6ssWPHqkqVKo4QFQCAkoZgCgAAOERFReVr2759uxo1apQv8Nq+fbsGDx6s2NjYq1SdswoVKqhChQr5avL19dVjjz3m1F6/fv2rUtM777yjUqVKqVu3bi4d12q1qlevXnr55ZdVsWLFC/bdsWOHJGnw4MFq1KiRS86fkZEhPz+/Avf9/PPPGjJkiDp37qxPPvlEXl5ejn1t2rSR1WrV4sWL5evr65JaCpKdnS2LxSIPj2v7t7ZX6z680M8LAIBrDY/yAQBQRMaMGaP//Oc/kqSqVavKYrHIYrHoxx9/dPRZuHChGjduLH9/fwUEBKhDhw7avHmzY/9PP/0kT09PjRw50mnsvEfkpk2bJuncY2Xp6emaNWuW4zz/fCTvl19+UdOmTeXj46PIyEiNGjVK2dnZ+Wr+56N8P/74oywWi3bv3q2vv/7aMW7euXNycjRlyhRHuyvs27dPFotFb775piZOnKiqVasqICBAjRs31i+//OLU99+P8lksFn300Uc6c+aMU61SwY/y2Ww2jRw5UlWrVpWXl5fKly+vJ554Qunp6fn6DR48WKGhoQoICFDHjh31119/5as9KytL06ZNU58+fVw2WypPly5dFBAQoA8//PCC/Vq1aqX7779fknTrrbfKYrE4Xff06dNVt25d+fj4KCQkRF27dtUff/zhNMYDDzyggIAA/f7772rfvr0CAwPVtm3b857z1Vdflbu7u6ZOneoUSv3TPffco8jISKe25cuXq3HjxvLz81NgYKDatWun9evXX/D6pP/dl3PmzNGIESNUvnx5eXt7a/fu3ZKklStXqm3btgoKCpKfn5+aNm2q77//3mmMvHtn8+bN6tatm4KCghQcHKz7779fycnJTn3tdrveeOMN3XjjjfL29lZ4eLj69eungwcPOvXbvHmz7rjjDoWHh8vb21uRkZHq3LmzU79/3oc//vijYmJiJEkPPvig45795+Ohl/Id5V3Lpk2b1KNHD5UuXVrVqlXTnDlzZLFYCvxOx40bJ09PTx0+fPii3zcAAEWNYAoAgCIyaNAgPf7445KkTz/9VOvXr9f69evVoEEDSef+QH/vvfcqKipKixYt0pw5c5SamqrmzZsrISFBktSsWTO9/PLLeuutt7R8+XJJ52bEWK1W3X///Ro4cKAkaf369fL19VWnTp0c58l7LC8hIUFt27bV6dOnNXPmTL3//vvavHmzXn755QvW36BBA61fv15ly5ZV06ZNHePGxsY6/rDbo0cPR7srxcXFacWKFZo0aZLmzZun9PR0derUSSkpKec9Zv369erUqZN8fX0dNXXu3LnAvhkZGWrZsqVmzZqloUOH6uuvv9bTTz+tmTNn6s4775RhGJIkwzB09913O0KQpUuX6rbbbitwltiGDRt04sQJtW7d2jVfwj94eXmpSZMm+vLLLy/Yb/LkyXr++eclSTNmzND69ev1wgsvSJLGjx+vgQMH6uabb9ann36qd955R9u2bVPjxo21a9cup3GysrJ05513qk2bNvrss880duzYAs+Xm5urVatWqWHDho5HPC/F/PnzdddddykoKEgff/yxpk2bplOnTqlVq1b66aefLmmMUaNGKTExUe+//74+//xzhYeHa+7cuWrfvr2CgoI0a9YsLVq0SCEhIerQoUO+cEqSunbtqurVq+uTTz7RmDFjtGzZMnXo0MEptH300Uf19NNPq127dlq+fLleeuklffPNN2rSpImOHz8uSUpPT1e7du107Ngxp3u3UqVKSk1NLbD+Bg0aaMaMGZKk559/3nHPDho0qFDfUbdu3VS9enUtXrxY77//vnr16qWyZcsqLi7OqV9OTo6mTp2qrl275gsLAQAwhQEAAIrMhAkTDEnG3r17ndoTExMNDw8P4/HHH3dqT01NNcqWLWv07NnT0Wa3241OnToZpUqVMrZv325ERUUZN954o5GWluZ0rL+/v9G/f/98NfTq1cvw9fU1jh496mjLyckxbrzxxny1tWzZ0mjZsqXT8ZUrVzY6d+6cb1xJhtVqveD1z5gxw5BkxMfHF7i/c+fORuXKlR3be/fuNSQZderUMXJychztv/76qyHJ+Pjjjx1to0ePNv79W5n+/fsb/v7++c5TuXJlp+9m/PjxhpubW766PvnkE0OS8dVXXxmGYRhff/21Icl45513nPq98sorhiRj9OjRjrbXX3/dkOT0PbvSc889Z7i5ueX7uf9bQd/5qVOnDF9fX6NTp05OfRMTEw1vb2+jT58+jrb+/fsbkozp06dftKajR48akozevXvn25eTk2NkZ2c7Pna73TAMw8jNzTUiIyONOnXqGLm5uY7+qampRnh4uNGkSZMLnnPVqlWGJKNFixZO7enp6UZISIjRpUsXp/bc3Fyjbt26RqNGjRxteffOk08+6dR33rx5hiRj7ty5hmEYxh9//GFIMoYMGeLUb8OGDYYk49lnnzUMwzA2btxoSDKWLVt2wdr/fR/Gx8cbkowZM2bkq/lSv6O8a3nxxRfznW/06NGGl5eXcezYMUfbwoULDUnG6tWrL1grAABXCzOmAAAwwbfffqucnBz169dPOTk5jo+Pj49atmzp9LifxWLR7NmzFRgYqIYNG2rv3r1atGiR/P39L+lcq1atUtu2bRUREeFoc3d3V69evVx9WS7TuXNnubu7O7ZvueUWSdL+/ftdMv4XX3yh2rVrq169ek7ff4cOHZwet1y1apUk6b777nM6vk+fPvnGPHz4sCwWi8LCwlxS47+Fh4fLbrfr6NGjl33s+vXrdebMmXyPM1asWFFt2rQpcDZR9+7dC1uqJCk6Olqenp6Oz1tvvSVJ2rlzpw4fPqy+ffs6PfIYEBCg7t2765dfflFGRsZFx/93fevWrdPJkyfVv39/p5+p3W5Xx44dFR8fn+8xzX//XHv27CkPDw/Hzz3vn//+3ho1aqSbbrrJ8b1Vr15dpUuX1tNPP63333/fMeOxsArzHRX083r00UclyekR0Pfee0916tRRixYtrqhGAABchWAKAAATHDt2TJIUExPj9Id3T09PLVy40PGIUJ7Q0FDdeeedOnv2rDp27Kg6depc8rlOnDihsmXL5msvqM3V8hajzs3NLXB/Tk6OPD0987WHhoY6bXt7e0uSzpw545K6jh07pm3btuX77gMDA2UYhuP7P3HihDw8PPLVU9B3d+bMGXl6ejoFaq7k4+PjOM/lOnHihCQV+LhdZGSkY38ePz+/S3qLYVhYmHx9fQsMDOfPn6/4+HjHI6iXWovdbtepU6cueu5/H5/331SPHj3y/Vxff/11GYahkydPOh3z759j3s86r8ZL/d6Cg4O1evVq1atXT88++6xuvvlmRUZGavTo0QWu5XYxhfmOCuobERGhXr16aerUqcrNzdW2bdu0du3afC8HAADATNf2q0sAACim8mbVfPLJJ6pcufJF+69YsUJTpkxRo0aNtHTpUi1ZsuSSZ7SEhoYWOMumMDNvLlfeLK1Dhw4VuP/QoUNOM7mulrxAZfr06efdL5377nJycnTixAmncKqg7y4sLExZWVlKT0+/5NlslyMvVCnMjKy82o8cOZJv3+HDh/ONeamL2bu7u6tNmzb67rvvdOTIEadwJO8Nj/v27busWtzc3FS6dOmLnvvfNeZdw7vvvqvbbrutwGP+fa8dPXpU5cuXd2z/+2f9z1r//QbIf39vderU0YIFC2QYhrZt26aZM2dq3Lhx8vX11TPPPHPR6/mnwnxH5/uZDRs2THPmzNFnn32mb775RqVKlco3UwwAADMxYwoAgCJ0vpk+HTp0kIeHh/bs2aOGDRsW+Mlz5MgR3X///WrZsqXWrVunO++8UwMHDtTevXvznaug2TStW7fW999/75hRIp2bwbRw4UJXXmqBbrvtNgUEBBR4roSEBO3YsUO33357kdfxb3fccYf27Nmj0NDQAr/7KlWqSJJjIfN58+Y5HT9//vx8Y954442SpD179hRJzX///bdCQ0MLFeQ1btxYvr6+mjt3rlP7wYMH9cMPP1zwrXsXM2rUKOXm5uqRRx65pNlBtWrVUvny5TV//nzHIvPSuQXElyxZ4ngL3eVq2rSpSpUqpYSEhPP+N/Xvtwb+++e6aNEi5eTkON5M2aZNG0nK973Fx8frjz/+KPB7s1gsqlu3rt5++22VKlVKmzZtOm/N5/v1wZXfUXR0tJo0aaLXX39d8+bN0wMPPFAkwSkAAIXFjCkAAIpQ3iN377zzjvr37y9PT0/VqlVLVapU0bhx4/Tcc8/p77//VseOHVW6dGkdO3ZMv/76q/z9/TV27Fjl5ubq3nvvlcVi0fz58+Xu7q6ZM2eqXr166tWrl3766SfHH7br1KmjH3/8UZ9//rnKlSunwMBA1apVS88//7yWL1+uNm3a6MUXX5Sfn5/i4uLyrbdzpWbPnq0BAwZo+vTp6tevnyQpMDBQY8eO1YgRI2S329WrVy+VLl1av//+u1599VVVrlxZQ4cOdWkdl+KJJ57QkiVL1KJFCz355JO65ZZbZLfblZiYqO+++04jRozQrbfeqvbt26tFixZ66qmnlJ6eroYNG+rnn3/WnDlz8o2ZF2b88ssvjjWx8lSvXl2StHv3bkfbwIEDNWvWLO3Zs8cxa66g7zDPL7/8opYtW17ybKZ/KlWqlF544QU9++yz6tevn+69916dOHFCY8eOlY+Pj0aPHn3ZY+Zp2rSp4uLi9Pjjj6tBgwZ66KGHdPPNN8vNzU1HjhzRkiVLJMnxaKCbm5veeOMN3Xfffbrjjjv08MMPKzMzUxMmTNDp06f12muvFaqOgIAAvfvuu+rfv79OnjypHj16KDw8XMnJydq6dauSk5M1ZcoUp2M+/fRTeXh4qF27dtqxY4deeOEF1a1bVz179pR0LiB66KGH9O6778rNzU2xsbHat2+fXnjhBVWsWFFPPvmkpHNrlk2ePFl33323brjhBhmGoU8//VSnT59Wu3btzltztWrV5Ovrq3nz5ummm25SQECAIiMjFRkZ6dLvaNiwYerVq5csFouGDBlymd8sAABFzMyV1wEAKAlGjRplREZGGm5uboYkY9WqVY59y5YtM1q3bm0EBQUZ3t7eRuXKlY0ePXoYK1euNAzjf29i+/77753GXLduneHh4WEMGzbM0bZlyxajadOmhp+fnyHJ6e16P//8s3HbbbcZ3t7eRtmyZY3//Oc/xgcffODSt/LlvQ3u328YMwzDWLRokdGsWTMjMDDQ8PDwMCpVqmQ8+uij+d5gl/dWvgkTJhR4vn++Be9K3spnGIaRlpZmPP/880atWrUMLy8vIzg42KhTp47x5JNPOtV1+vRpY8CAAUapUqUMPz8/o127dsaff/6Zrx7DMIzmzZvne/Nd3vn/+fbBvFr//f2f7zvcvXu3IclYsmRJvrH/7UJvQvzoo4+MW265xXG9d911l7Fjx458dRX0HV7Mli1bjAcffNCoWrWq4e3tbfj4+BjVq1c3+vXrl+/+NYxz9/6tt95q+Pj4GP7+/kbbtm2Nn3/++aLnyXsr3+LFiwvcv3r1aqNz585GSEiI4enpaZQvX97o3LmzU/+8e+e3334zunTpYgQEBBiBgYHGvffe6/QGO8M494a8119/3ahZs6bh6elphIWFGffff79x4MABR58///zTuPfee41q1aoZvr6+RnBwsNGoUSNj5syZTmMVdB9+/PHHxo033mh4enrmu6cu5TvKu5bk5OTzfmeZmZmGt7e30bFjx/P2AQDALBbD+Mf8YAAAABTakiVL1KtXL+3fv99p7aIr9cILL2j27Nnas2ePY0F5FN6YMWM0duxYJScnF9lbFK8ln3/+ue688059+eWX6tSpk9nlAADghDWmAAAAXKRbt26KiYnR+PHjXTbm6dOnFRcXp1dffZVQCpclISFBX3/9tUaMGKF69eopNjbW7JIAAMiHYAoAAMBFLBaLPvzwQ0VGRsput7tkzL1792rUqFHq06ePS8ZDyTFkyBDdeeedKl26tD7++ONCrU8GAEBR41E+AAAAAAAAmIIZUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAU5T4V7vY7XYdPnxYgYGBLAgJAAAAAABwhQzDUGpqqiIjI+XmduE5USU+mDp8+LAqVqxodhkAAAAAAADFyoEDB1ShQoUL9inxwVRgYKCkc19WUFCQydUAAAAAAABc32w2mypWrOjIXC6kxAdTeY/vBQUFEUwBAAAAAAC4yKUsmcTi5wAAAAAAADBFiQ2m4uLiFBUVpZiYGLNLAQAAAAAAKJEshmEYZhdhJpvNpuDgYKWkpPAoHwAAAAAAwBW6nKylxM6YAgAAAAAAgLkIpgAAAAAAAGAKgim43Pjx4xUTE6PAwECFh4fr7rvv1s6dO8/b/+GHH5bFYtGkSZOc2lu1aiWLxeL06d27d77jv/zyS916663y9fVVWFiYunXrVuB5Tpw4oQoVKshisej06dNO+wzD0JtvvqmaNWvK29tbFStW1KuvvnrZ1w4AAAAAAC6dh9kFoPhZvXq1rFarYmJilJOTo+eee07t27dXQkKC/P39nfouW7ZMGzZsUGRkZIFjDR48WOPGjXNs+/r6Ou1fsmSJBg8erFdffVVt2rSRYRj6/fffCxxr4MCBuuWWW3To0KF8+4YNG6bvvvtOb775purUqaOUlBQdP378ci8dAAAAAABcBoIpuNw333zjtD1jxgyFh4frt99+U4sWLRzthw4d0mOPPaZvv/1WnTt3LnAsPz8/lS1btsB9OTk5GjZsmCZMmKCBAwc62mvVqpWv75QpU3T69Gm9+OKL+vrrr532/fHHH5oyZYq2b99e4LEAAAAAUFzl5tqVmnFWtvSzysrKVY7drtxcu0r0W9JKGHeLRe7ubvJwd5Ofr5eC/H3k6+0pi8VyVc5PMIUil5KSIkkKCQlxtNntdvXt21f/+c9/dPPNN5/32Hnz5mnu3LmKiIhQbGysRo8ercDAQEnSpk2bdOjQIbm5ual+/fo6evSo6tWrpzfffNNpzISEBI0bN04bNmzQ33//ne8cn3/+uW644QZ98cUX6tixowzD0O2336433njDqWYAAAAAKA4Mw9Dp1DNKPpWm9DOZhFBwOJ12RoeTU+Tp4a7gAF+VCwuSp4d7kZ6TYApFyjAMDR8+XM2aNVPt2rUd7a+//ro8PDw0dOjQ8x573333qWrVqipbtqy2b9+uUaNGaevWrVqxYoUkOUKmMWPGaOLEiapSpYreeusttWzZUn/99ZdCQkKUmZmpe++9VxMmTFClSpUKDKb+/vtv7d+/X4sXL9bs2bOVm5urJ598Uj169NAPP/zg4m8EAAAAAMyTmZ2jxCOnlJpx1tHm5emhAD9v+Xp7yt3NTe5ubrpKk2VwDci1G8q125WTk6v0M1lKP5Op7JxcHT+dplO2dEWWCVZYqYAim0FFMIUi9dhjj2nbtm366aefHG2//fab3nnnHW3atOmCN/bgwYMd/167dm3VqFFDDRs21KZNm9SgQQPZ7XZJ0nPPPafu3btLOvfYYIUKFbR48WI9/PDDGjVqlG666Sbdf//95z2P3W5XZmamZs+erZo1a0qSpk2bpujoaO3cuZPH+wAAAAAUC5lZOdqVmKSsnFxZLBaFlQpQqUBfeXkSDeCc0FKS3W4o42ymkk6m6kxmtg4cO63sHLvKhQUVSThVYt/KFxcXp6ioKMXExJhdSrH1+OOPa/ny5Vq1apUqVKjgaF+7dq2SkpJUqVIleXh4yMPDQ/v379eIESNUpUqV847XoEEDeXp6ateuXZKkcuXKSZKioqIcfby9vXXDDTcoMTFRkvTDDz9o8eLFjvO0bdtWkhQWFqbRo0c7xvHw8HCEUpJ00003SZJjHAAAAAC4nuXm2rXrQLKycnLl5emh6hXLKDwkkFAK+bi5WRTg56Oq5cMUERIkSTp6wqbkU2lFcr4SewdarVZZrVbZbDYFBwebXU6xYhiGHn/8cS1dulQ//vijqlat6rS/b9++uv32253aOnTooL59++rBBx8877g7duxQdna2I5CKjo6Wt7e3du7cqWbNmkmSsrOztW/fPlWuXFnSubf2nTlzxjFGfHy8BgwYoLVr16patWqSpKZNmyonJ0d79uxxtP3111+S5BgHAAAAAK5nR46nKCs7R54e7qoSGVrk6wbh+mexWBRWOkCySMdO2HQ4OaVIZtiV2GAKRcdqtWr+/Pn67LPPFBgYqKNHj0qSgoOD5evrq9DQUIWGhjod4+npqbJlyzoem9uzZ4/mzZunTp06KSwsTAkJCRoxYoTq16+vpk2bSpKCgoL0yCOPaPTo0apYsaIqV66sCRMmSJLuueceSXIETXmOHz8u6dyMqFKlSkmSbr/9djVo0EADBgzQpEmTZLfbZbVa1a5dO6dZVAAAAABwPcrMynHMdoksU4pQCpclNNhfqelnlXE2S4eTU1QlMvTiB12GEvsoH4rOlClTlJKSolatWqlcuXKOz8KFCy95DC8vL33//ffq0KGDatWqpaFDh6p9+/ZauXKl3N3/94vohAkT1Lt3b/Xt21cxMTHav3+/fvjhB5UuXfqSz+Xm5qbPP/9cYWFhatGihTp37qybbrpJCxYsuKzrBgAAAIBr0em0MzIk+ft6K8DP2+xycJ2xWCyKCD33SF9K2lnZDde+x9FiGC4e8TqT9yhfSkqKgoKCzC4HAAAAAACX2p2YLFvGWZUNDVJoqQCzy8F1yDAM7dx3TLl2u2pWCr9owHk5WQszpgAAAAAAKKZy7XalnsmUJGZLodAsFovj/rGln3Xp2KwxVYwkJyfLZrOZXQaKSFBQkMqUKWN2GQAAAACuIxlns2QYhjzd3XkDH66Iv6+3UtLOKC0j06XjclcWE8nJybr/wUE6mZphdikoIiGBfpo74yPCKQAAAACXLCfHLkny9HSXxWIxuRpcz/IWzc/Jtbt0XIKpYsJms+lkaobKNO4u/5AIs8uBi6WfPKbk9Utks9kIpgAAAABcslz7uRDB3Y2VfHBl3N3P3UN595SrEEwVM/4hEQoKr2B2GSgCyWYXAAAAAOC6Y7efe9+Zm1vRz5Zq2eGei/Z5ZsQQxbZvfd79m7fu0PaEnep7b7dC1/DooL7qfc+dl3Xc8i9XaM3PG7Rn736dPZupihUi1bvHnWrTssl5j1nz8wa9MO5NVa1cUTM/mOi078jRJH0wY762bktQRkaGKlSIVK/uXdSuTfML1vH1d6v02luT87X36XmXHh54v1PbL79u0oczP1Zi4iGVCQvRPd27qGuXDk59TqfYNG3mAm3YuFmnU2wqG1FGd3Zqp+53d7rsGXTu/72HcpkxBQAAAAAArjWTJ73itD3kiefU7a5Y3d66maOtfLkLP+GzZdsOLfxkeaGDqcKaPX+JYqJv0Z2d28nP11c//7JRY199WykpNnW9s2O+/pmZmYqbOkshpYPz78vK0shnX5bFIj32cH8FBQXq+x9/0suv/5+8vbzUotmtF61nwivPyd/fz7FdJjTEaf/2hJ16dswb6nB7C1kf6q/tCTv1f5OnydPDQ3fEtnX0e2Hcmzp4+IgGP9BHZSPCtHHTNr37/kzl2u3q1b3L5XxFRYZgCgAAAAAAXLGbb6qZry2iTFiB7deaj+JeV6lS/wuZGja4RcnHT2jBJ8sLDKbmLliqiPAwlSsbrp1//e20b+dfe3Tw0BG9/fpoNahX2zFewh+79MPqny8pmKpZ4waVCg467/5Z8z5RzepV9fTwIZKkBvVq61hSsqbPXqhOHVrLzc1NSckntG37H3p6+BB16tD6v/3qaPff+7Vq9TqCKQAAAAAAUHLY7XbNW7hMX3y9UidOnlJ4mTB17dJR93TrLEmaMWeRZs5dLOl/jwXWuyVK70wYq/2JhzRz7iL9vmOnbKmpKhtRRp07tNU93TrLzQXrZ/0zlMpTo1pV/fLrpnzthw4f1aIlXyju7Ze1eOkX+fbn5ORKkgL+MeNJkvz9/WQYV1yqsrKytXnrdj004D6n9nZtmuuLr7/Xrj17VatGNeXm5hRYR4C/n1JSbFdeiIsQTAEAAAAAgCI35cM5+mTZl7q/dzfdUvsmbdy0Ve9NnamMM2fU/74e6tyxrZKPn9DKVT/p7ddHS5L8/XwlScdPnFTFCpG6vU1z+fn6aveefZoxZ6HOnD2rB+4//9pWeWs2TXpjjOrXvfmy6t22/Q9Vrlg+X/u7U2ao/e0tVL1alQKPu6X2japSqYI+nDFfTz4+WEFBAfph9Trt3LVHgx7ofUnnfuCh4Uqx2RQRXkZ3xN6ue++5U+7u596Kd/jIUWVn5+SrrUqlc+tN7088pFo1qqlc2Qg1bHCL5ny8RBUqlFPZ8DLauHmb1q77VSOGPnwZ30TRIpgCAAAAAABF6nSKTZ8u/1o9u3fRwP7nwpmY6LpKzzijjxct0z3dOiu8TKjKhIXKzWLJ9/hfdP06iq5fR5JkGIbq1L5RZzMztXT5NxcMpgrrp3Xx2rhpm5576nGn9p9/2ajtCTs1d/r/nfdYDw8PTZowRs+Ofl33PvCYJMnT00OjRj6mBvXqXPC8oSGl9WDfnoq6sYYsFot+Xh+vabM+1vHjJ/TEY4MkSalp6ZKkgAB/p2MDAgMkSbbUNEfby6P/o7GvvK0HHx4hSbJYLHpk4P3q2K7lpXwNV0WJDabi4uIUFxen3Nxcs0sBAAAAAKBY++PPXcrJyc33lru2rZrp869Watfufapb56bzHp+ZlaV5C5Zq5Q9rdSz5uONxOUnKOHNGfr6+BR4X2771Bd8CWJB9+w9o/FtxatW8sdq3beFUw3vvz9SD/XpdcP2nzMxMvfjSW8q12/XSiyMV4O+nn9dv1OtvTVZggL9ujal/3mMbNaynRg3rObZjouvK29tLiz/9Un3v7a7Q0NKOfed7q15eu2EYeu3NyTpw6Iief3qoyoSFaMu2BH0062MFBvqrc8e2BR5/tZXYYMpqtcpqtcpmsyk4OP+zpAAAAAAAwDXyZvmElC7l1J63nfqPWT4FmTptrr74+ns9cN89qlnjBgUE+Ovn9fGaPX+JsrKyzxtMXa6k5BP6z3Ov6IYqlfTsU4857ftk6ZeyWCxq26qp43qys3NkN+xKTUuXj7eXPD099eU3P+iPnbv0ydz3HWtXNahXR0eTkvX+tLkXDKYK0qpFEy345HPt+nufQkNLK/C/M6X+/Z2l/Xc7b//6DZv049r1mj7lTVW7obIkqd4tNystLV2TP5yj2PatXbI+15UqscEUAAAAAAC4OoL++5jZqVMpKhMW6mg/eeq0JCnwv/vP58c1v+jOTu3Up9fdjraCFia/Eim2VI189iX5+/np1TFPydvLy2l/4oFDOnT4qO7qOTDfsXd0f0DDHx+su+5or32JBxUWGpJvQfUa1apq42/bLr+wf62YHlmurDw9PbT/wCGnkGtf4kFJUuVK5R3b7m5uuqFqJafjq1erorSl6bLZUgtc9P1qI5gCAAAAAABF6sZa1eXh4a5Va9apZo0bHO0/rP5Zvj7eqlmjqqRz6zNlZefkOz4zK0seHv+LMHJzc/X9jz+7rL6MM2f01HOv6MyZs4p7+5UCg7I+PbuqYzvnxwLnL1yqxIOH9cwIqypWKCdJKhteRsdPnNSp0ykq/Y/g58+/9qhsRJnLru2H1evk7uamGv9dbN3Ly1P169bWqjXr1LPbHY5+36/6WaEhpVWjWtX/1hGmXLtdu/bsU83qVZ3q8PX1UfAFHke8mgimAAAAAABAkSoVHKTud3XSwk8+l6enp+rcfKN+2/y7Pv9qpR7s21O+Pj6Szs32yc3N1SdLv9TNUbXk7+erShXLq2H9W/TF1ytVpXIFlQoO0tLPv1F2dvZFz/vNitV6Y+JkTXz9RdW75fxv5Xvxpbe0a88+/eeJh5V8/ISSj59w7KtRraq8vDxVuVJ5x2yk/42/SsnHTzq98e/2Ns01b+FSPfXcK+rTq6sC/P20dt2vWr/hNw1/fLCj35GjSerd36oH7r9HD/btKUka+ezLalCvjm6oUlGS9PP6jfr865XqcXcnhYb8b32p/vf10NCRo/XG2++rXZvm2r7jT33xzUqNGPqw4/G8225toLIRZTTm5bfU//57FBYaok1bftfyL75Trx5dzrtG1dVGMAUAAAAAAIrcI4PuV2CAv7745nvNW7hUEWXCNOShfk6zfprc1lB3d+mgeQuX6tRpm+rWuUnvTBirYdYBeuv/PtA7k6fLx9tLHdu1UvMmt2rCpPcveE7DsCvXbv/303D5xP+2VZL02luT8+1bMCtO5cqGX/J1hpcJ1aQJYzRt5gL93+RpOnPmrMqXL6ennnxEnTq0cfQ7ezZTkvO6W5UqRurLb75X8vETMuyGKlQop8ceeUDd74p1OkftqFp6dcxT+nDGfH33/WqVCQvV0EcH6I7Y/y1o7ufrq7dfH60PZ36sD2fMly01TeUiwjV4QB/d07XzJV9PUbMYxsV+PMVb3uLnKSkpCgq6NqaxFcaePXvUe8AjqtJ5iILCK5hdDlzMlnRQ+76crAXT31e1atXMLgcAAADAdSLpZKoOJp1WcICvKkSUvvgBuGq+/OZ7TZ0+T4tmT5GPj7fZ5VxUVnaOdiUmyc1iUb1aF84dLidrMX/5dQAAAAAAgBLm9x07dU/XO66LUKoo8SgfAAAAAADAVfbMiCFml3BNYMYUAAAAAAAATEEwBQAAAAAAAFMQTAEAAAAAAMAUrDEFAAAAAABcZsacRZo5d7HCQktr8dz35ebmPCfmqedf1Yb4zWrcqIFee2mUSVVenl9+3aQPZ36sxMRDKhMWonu6d1HXLh0uetyseZ9o6+8J+nPnbqVnnNHUd1/TjTWd37R++nSKZn+8RAl/7NLuv/fJw91d33w2t6gu5ZrDjCkAAAAAAOBSHh7uSrGlasu2HU7tp1Ns2rhpm3x9fUyq7PJtT9ipZ8e8oZrVq+r1l59Vx/at9X+Tp+mLr7+/6LGff7VCOTk5atjglvP2ST5xUj/8uE6lSgWrVo1q5+1XXDFjCgAAAAAAuJSnh4ei69+ilat+UoN6dRztq9asV1hoaZWNKGNidZdn1rxPVLN6VT09/Nxb9BrUq61jScmaPnuhOnVonW9G2D8tmjNFbm5u2rx1h1b/tKHAPtWqVtayhR9JOjfbbM/f+1x+DdcygikAAAAAAOBybVs301v/94GefGyQPD09JUnfr1qrNi2b6o+du/L1T0o+oQ+mz9OvG7fozNmzurFmdT32SH+nWUTfrFitL75eoX37D8qQVP2Gynpk4P266cYajj4z5izSwk+WK+7tV/T2ex/qr917FVk2QkMe6qdGDetd1jVkZWVr89btemjAfU7t7do01xdff69de/ZecJbThUKry+kjScP+M1q+Pj5q06qpZs5ZpOMnT6lB3dp69j+PKePMWb35zlRt3/GnIsLLaJh1oBrUq+049uf18Zo17xMlHjgkd3d3lY8sqwH9eum2Rg0u6dxFiUf5AAAAAACAyzW9LVp2u10b4rdIko4eS9b2hL90e+tm+fqmpqbp8REvaPeefRo6ZIBeemGkfHy89eRTY3XqdIqj39FjSWp/e0uNfX6EXnhmmMqUCdXQkaN14OBhp/FycnP18hv/p47tWuvlF/+j4OBAvfjSm0qxpTr6zJizSC073KMjR5POew2HjxxVdnaOKlcs79RepVIFSdL+xEOX/b1ciV179mrZ59/K+nB/DX/8If2+40+9Mel9vfjyW2p8a7ReevE/KlUqWC++9KYyzpyRJB06fFQvvvyWqlSuqJde/I9GP/ukWrVootS09Kta+/kwYwoAAAAAALict7e3mjWO0cpVa9WsSYxWrvpJlSuWV/VqVfL1Xbz0S6Wlpev9/xuv0qWCJUkN6tVRnwcf14JPluvRQX0lSQ/cf4/jGLvdroYNbtHOnXv09Xc/6qEBfRz7srNz9PCA+xwzgiLLRei+AUO1IX6z2rdtccnXkBfeBAT4O7UHBAZIkmypaZc8liukp2do/LhnFBwUKEn6e+9+LVzyuYY/Plh33dFekhQaWloPPjxCmzZvV7MmMdq1Z69ycnL1hHWg/Px8JemyZ44VpWIRTHl4eKh27XNT1Bo2bKiPPvrI5IoAAAAAAEC7Ns31/LgJyjhzRitXrdXtbZoX2C9+01bVq3uzAgMDlJObK0lyc3fTLbVv1J879zj67Us8qA9nzNeOhL+cZlIdPOQ8Y8rNzaLo+v9b26pC+XLy9PRQ8vETjrYH+/bUg317XtJ1WCyWy2ovKtWrVXGEUpJUoUI5SXK61orlz7UlJR+XdG4NK3c3N4177R116XS76ta5SQH+zkGbmYpFMFWqVClt2bLF7DIAAAAAAMA/RNevIz9fX82et0R79x3Q7a2bFtgvJSVVCX/sUttOvfPtK18uQpKUkXFGI0e9rFKlgmR9uL8iwsPk5eWlCW9PUVZWttMx3l5ejnWt8ni4u+frdzGB/50plfqvmVFp/90ODLi6Ac+/AyVPj3Oxzj9ndOVdd961VqwQqfHjntHcBUv1wtgJsrhZ1KhhPT1hHaiIcPMXoS8WwRQAAAAAALj2uLu7q1WLxlq4ZLluvqmmypWNKLBfUGCAyjesp4H98wdTnp7noosdf/yl5OMn9Nq4Z5weB0xLz1CZsNAiqT+yXFl5enpo/4FDujWmvqN9X+JBSVLlSuXPd+g15daY+ro1pr7S0zO0YeMWxU2dqdfemqy3Xx9tdmnmL36+Zs0adenSRZGRkbJYLFq2bFm+PpMnT1bVqlXl4+Oj6OhorV271mm/zWZTdHS0mjVrptWrV1+lygEAAAAAwMV07thGTW5tqJ7d7zhvn+j6dbQ/8aAqVyqvG2tWc/pUq1pZkpSZmSVJ8vD83xyb7Tt26uix5CKr3cvLU/Xr1taqNeuc2r9f9bNCQ0qrRrWqRXbuouDv76c2LZuoTcumV33h9vMxfcZUenq66tatqwcffFDdu3fPt3/hwoV64oknNHnyZDVt2lRTp05VbGysEhISVKlSJUnSvn37FBkZqe3bt6tz5876/fffFRQUdLUvBQAAAAAA/EuNalX1ypinLtinZ/cuWrnqJw0bOVrd7+6kiPAwnU6x6Y8/dyk0NEQ9u92hqJtqyNfXR5Pe+0j39eqq5OMnNXPuIpUJCylUXTPnLtbseZ9o/sz3VDbi/I+09b+vh4aOHK033n5f7do01/Ydf+qLb1ZqxNCH5eb2v/k+fR54TBERZZxmIW3ZtkOnU2zat//cDKtNW7br6LEklY0I1401qzn6/bh2vSRp3/6DyrXbHds31qx+wdouxfIvV2h7wk7dGlNfoSGldORoklb8sFYNo2+5onFdxfRgKjY2VrGxsefdP3HiRA0cOFCDBg2SJE2aNEnffvutpkyZovHjx0uSIiMjJUm1a9dWVFSU/vrrLzVs2LDA8TIzM5WZmenYttlsrroUAAAAAABQCMFBgZo86RVNm7VAU6fNky01VaWCgxV1Uw01b3KrJCmkdCmNfW64pnw4R8+OeV0Vy0dq+NCH9PGiZYU6p2EYyrXbZRjGBfvVjqqlV8c8pQ9nzNd3369WmbBQDX10gO6IbevUL9dul91ud2qbMWeRtmxLcGxPnTZXktSxXUuNGvmYo330yxOdjsvbfmbEEMW2b335F/cPN1StpHW/bFTc1FmypaYqpHQptW3VtMDHJs1gMS72E7iKLBaLli5dqrvvvluSlJWVJT8/Py1evFhdu3Z19Bs2bJi2bNmi1atX69SpU/Lz85O3t7cOHjyopk2bavPmzQoJKTgxHTNmjMaOHZuvPSUl5bqeZbVnzx71HvCIqnQeoqDwCmaXAxezJR3Uvi8na8H091WtWrWLHwAAAAAAkpJOpupg0mkFB/iqQkRps8vBdSwrO0e7EpPkZrGoXq0L5w42m03BwcGXlLWYvsbUhRw/fly5ubmKiHBeHC0iIkJHjx6VJP3xxx9q2LCh6tatqzvuuEPvvPPOeUMpSRo1apRSUlIcnwMHDhTpNQAAAAAAAKBgpj/KdyksFovTtmEYjrYmTZro999/v+SxvL295e3t7dL6AAAAAAAAcPmu6RlTYWFhcnd3d8yOypOUlJRvFhUAAAAAAACuL9d0MOXl5aXo6GitWLHCqX3FihVq0qTJFY0dFxenqKgoxcTEXNE4AAAAAAAAKBzTH+VLS0vT7t27Hdt79+7Vli1bFBISokqVKmn48OHq27evGjZsqMaNG+uDDz5QYmKiHnnkkSs6r9VqldVqdSzIBQAAAAAA/mfGnEWaOXexwkJLa/Hc9+Xm5jy35annX9WG+M1q3KiBXntp1BWf78e16zX65YlaMCtO5cqGS5JadrhHjw7qq9733HnF41+JP/7cpfemztJfu/9WcFCg7oi9Xf36dM/3nRRkweLlWvr5Nzp58rSqVq2kRwf1Vf26Nzv2HzmapN79rfmOi7qxhqa886pLr+NaZHowtXHjRrVu/b9XHw4fPlyS1L9/f82cOVO9evXSiRMnNG7cOB05ckS1a9fWV199pcqVK5tVMgAAAAAAJYKHh7tSbKnasm2HGtSr42g/nWLTxk3b5OvrU6TnnzzpFZUNL1Ok57iYw0eOafiol1Tvlii9Nm6U9ice1PvT5ionJ0eDHrj3gscuWLxcH86cr8EP9FHNGlX1+dff66nnX9H7/zde1ao65xqDH+zjFFj5+foWyfVca0wPplq1aiXDMC7YZ8iQIRoyZMhVqggAAAAAAEiSp4eHouvfopWrfnIKplatWa+w0NIqG1G0odHNN9Us0vEvxceLP1OAv5/GPjdCXl6eiq5fR+kZZzR7/ifq1eNOBQb4F3hcVla25ny8RD26dnbM+KpbJ0oPPjJCcz/+VKOffdKpf4XyZa+J673aTA+mzBIXF6e4uDjl5uaaXQoAAAAAANestq2b6a3/+0BPPjZInp6ekqTvV61Vm5ZN9cfOXfn6JyWf0AfT5+nXjVt05uxZ3Vizuh57pL9q1ajm6JOTk6MpH87RtytXy263q2Xz21S3TlS+sf79KN/6Db9p8dIvtefv/crKzlbliuX1YN+eujWmvuOYr79bpdfemqwP33tdH878WNt+/0OhoaXVr08PdWzX8rKvf0P8ZjVv2kheXp6OtnZtmuujmR9r0+bf1bL5bQUetz1hp9LSM9S2VTNHm7u7u9q0bKqFSz6XYRiyWCyXXMf4N9/Tzr/+1pCH+mnyh7N16PBR1apRTc899Zj8/fw08d0PtWHjFpUKDtLgB+5Vm1ZNHcf+vuNPfTB9vvb8vU92w1DZiDLq3eNOdWzX6rK/D1e7phc/L0pWq1UJCQmKj483uxQAAAAAAK5ZTW+Llt1u14b4LZKko8eStT3hL93eulm+vqmpaXp8xAvavWefhg4ZoJdeGCkfH289+dRYnTqd4uj3wfT5WvbFt+p9z10a89xw5eba9dHMjy9ay5GjSWpyW0M999TjGvf8CNW+uZaefmG8Nm/dka/vy2/8n2Ki6+rl0f9R9Rsq67W34rRv/wHH/q+/W6WWHe4p8Ng8Z86e1bGk46pcsYJTe9mIMvLx9tb+A4fOe2zevsoVI53aK1eqoIyMM0o+ftKpfeK7H6p1bE/d1XOg3nj7fdlsqfnGPHHylKZOm6t+fXrohaeH6eixJL302v9p7PhJqlqlksY9P0I1q9+gl994V0ePJUuS0tMz9MwL4+Xv56sXRz2hV0Y/pS6d2iktLf28tV9NJXbGFAAAAAAAuDhvb281axyjlavWqlmTGK1c9ZMqVyyv6tWq5Ou7eOmXSktL1/v/N16lS5170ViDenXU58HHteCT5Xp0UF/ZbKla9sW36tPzbt3fu6skqVHDerI++Xy+sObfut0V6/h3u92u+vVqa9/+g/r8qxVO6zNJUtc7Y9W1SwdJ5x4JXP/rJq35+VdVqVzxkq89L7wJKOBxvcBAf9lS84dHjmNT0+Tl6Slvb2/n4/47VmpqmsLLhMrL01N33dFejaLrKSDATwl/7tbcj5do5649mvp/4+Xh8b/oJjUtXe9OfElVKp0Lyo6fOKl3Jk9Xn553qf99PSRJN9aqrrU/b9BP635Vj66ddeDQEaWlZ2jwgD6Oda2i69fRtYJgCgAAAAAAXFC7Ns31/LgJyjhzRitXrdXtbZoX2C9+01bVq3uzAgMDlPPfpXPc3N10S+0b9efOPZKkv/clKjMzS82b3up0bItmt2p7ws4L1pGUfEIfzfxYv23ephMnTzvWrK5V44Z8fWMa3OL4dz8/X4WXCVNy8glHW2z71opt3zrfcQUp6IE7wzBkKXDPhQ90rLP9332hoaU1/PHBjv31brlZVStX0DMvvqY1P/+qNi2bOPaFhZZ2hFKSVLHCudlY0fX/d62BAf4qVSpYSf+91vLlIuTv56u33/1Q3e7qpAZ1b1ap/4aG1wKCKQAAAAAAcEHR9evIz9dXs+ct0d59B3R766YF9ktJSVXCH7vUtlPvfPvKl4uQJJ04eVqSVLpUkNP+kNKlLliD3W7Xs2NeV3p6hgb066XykWXl4+Oj6bMXKinpeL7+/57l5OnhoazsrAue498CAwIknZup9G9paRkKDAw477EBgQHKyspWZlaWvL28/ndceobT2AW5rVED+fr66K9dfzsFUwH+zteUN5sq37V6eigr69y1BgYG6K3xL2j6nEV6dcK7ys3N1S21b9LQIQPyvRnQDCU2mGLxcwAAAAAALo27u7tatWishUuW6+abaqpc2YgC+wUFBqh8w3oa2D9/MOXpeS6CCA0pJUk6ddqmMmGhjv0nT52+YA2HDh/Vrt179crop9SsSYyjPTPz8sKmy+Hj462I8DDtP3DQqf3osWSdzcxU5Yrlz3ts3r79iYdUs3pVR/v+xIPy8/NVmbCQC588b2aVC9x0Yw1NeOU5ZWZmavPWHZr84Ww9P3aCPp75nsvOUVgsfs7i5wAAAAAAXFTnjm3U5NaG6tn9jvP2ia5fR/sTD6pypfK6sWY1p0/e7JwbqlSSt7eX1v68wenYNT9tKGhIh7wAysPzf3Nszi3E/mdhL+mS3BpTXz+ti1d2draj7fsff5KXl6caXGCtptpRtRTg76dVq392tOXm5mrV6nW6Lab+Bd/It27DbzpzNlM31qp23j6F4e3trdsaNdBdd3TQkaNJyswqulDvUpXYGVMAAAAAAODS1ahWVa+MeeqCfXp276KVq37SsJGj1f3uTooID9PpFJv++HOXQkND1LPbHQoKCtSdndtp/qJl8vb2Vs3qVbVy1U86lpR8wbErVSyvMmGh+mDaPNlz7Tp79qxmzFmksNCLzDw6j29WrNYbEydr4usvqt4tN5+337333KWVq37SmFfeVre7YpV48LBmz1uiXt27OBYyl6Qnnx6rY8eSNf+/s5C8vDzV997u+nDmfJUKDlaN6lX15Tff6/DRY3rx2Sccx03+YLYsbhZF1aqhgAB//bFzt+YtXKpaNaupWZNGhbq2f1q/4Td9+e0Pat6kkSLCw3Ty5Gl9+tnXqh1Vy+kRQ7MQTAEAAAAAAJcIDgrU5EmvaNqsBZo6bZ5sqakqFRysqJtqqHmT/y12/vCA+5Sba9fHiz+TYberedNGGti/t157a/J5x/by8tRLL47UpPc+0uhX3lJ4mTD1vbe7Nm/9XTv/+vuyazUMu3Lt9os+MRdZLkJvjX9B770/U8+8MF5BQQHqfc+d6tenu1M/u/3ceP/Uq0cXGTK05LOvdOpUiqpWraTXX3rWaW2nypXKa9nn3+rzL1fobGaWyoSFqHOHNnqwb095uLtf9nX9W/nIsnKzWPTRzI916nSKgoMC1bBBXT00oM8Vj+0KFsNw4UOL1yGbzabg4GClpKQoKCjo4gdco/bs2aPeAx5Rlc5DFBRe4eIH4LpiSzqofV9O1oLp76taNddO5QQAAABQfCWdTNXBpNMKDvBVhYjSZpeD61hWdo52JSbJzWJRvVoXzh0uJ2spsWtMAQAAAAAAwFwlNpiKi4tTVFSUYmJiLt4ZAAAAAAAALldigyneygcAAAAAAGCuEhtMAQAAAAAAwFwEUwAAAAAAADCFh9kFAAAAAACA4mPGnEWaOXexwkJLa/Hc9+Xm5jwn5qnnX9WG+M1q3KiBXntplElVStnZ2Zo2a6G++36NUtPSdEOVSnpowH2Krl/Hqd+seZ9o6+8J+nPnbqVnnNHUd1/TjTUv/W3pX37zvZYs+1oHDh6Wn5+vom6qofFjn3Hsj/9tq77+bpX+2Llbh48cU9cuHfTEY4Ncdp3XOmZMAQAAAAAAl/LwcFeKLVVbtu1waj+dYtPGTdvk6+tjUmX/8+77M7Xs82/Up+ddemX0U4osF6GnX3hVf+3626nf51+tUE5Ojho2uOWyzzFjziLFTZ2l29s014RXn9OIYQ8pNKS0U58NGzdr99/7VLdOlAIC/K/omq5HJXbGVFxcnOLi4pSbm2t2KQAAAAAAFCueHh6Krn+LVq76SQ3q/W8G0qo16xUWWlplI8qYWJ2UfPyEvvhqpayPPKDud8VKkmKi62rAoyM1c+5ivTr2aUffRXOmyM3NTZu37tDqnzZc8jn2JR7UnPlL9PrLzyomuq6jvUXTW536DRncT489/IAkafPW7VdwVdenEjtjirfyAQAAAABQdNq2bqbVP21Qdna2o+37VWvVpmVTWSwWp74nTpzSa29NVu/+VrXr0kd9HnxcH0yfr6ys/x27dt2vatnhHq375TdHW2paunrc94hefPmty6ptz95E5drtavSPwMhisSimQV3F/7bVqeZ/P4p4qb757keVKxfhFEoV5FLGP3I0SS073KNvVqzWG2+/r87d+uvOngO0YPFySdL3P/6s+wcOVWzXfnp+3ASlpqU7js3JydGUD2erZ99Hdfsd96rrvYP1zIuvKS09/Xynu6pKbDAFAAAAAACKTtPbomW327Uhfosk6eixZG1P+Eu3t26Wr+9pm01BgQGyPtxfE155Tvfec5e+XfmjJr77oaNP8yaN1LFdK02YNEWnU2ySpLff/VB2u10jhj7k6Df+zffUssM9F6wtKytLkuTh4fwgmaenh7Kys3XkaFKhrvmfEv78SzdUqaRZ8z7RXT0Hqm3n3ho68kXt2rO30GNOm/Wx/P18Nea54WrdoommfDRHU6fN1SfLvtQjA/vqCetAbd6yXe9/NMdxzNwFS/XZlyt0b8+79earz+uJIQMVFlpa2dk5V3yNrlBiH+UDAAAAAABFx9vbW80ax2jlqrVq1iRGK1f9pMoVy6t6tSr5+larWllDHurn2K59843y8fHW+Dfj9IR1oHx8vCVJQx99UAMe3aE335mqNi2a6Psff9brLz+r4KDAy6qtYvlISdIfO3erXNlwR3vCn7skSbbUtMu93HxOnjqtv3bv1b79BzRi6EPy8PDQzHmLNWLUS5o3/V0FFmI9qdpRtWR9uL8kqUG92lrz0y9auvwbLZwzxfEd7Pl7v7789gf954lHJEl/7tytmAZ11bVLB8c4LZvfdsXX5yoEUwAAAAAAoEi0a9Ncz4+boIwzZ7Ry1Vrd3qZ5gf0Mw9AnS7/S51+v0JGjSU6P8B0+ekw3VKkkSfL399OokVY9+fRYbfh1s+66o71ui6nvNNaokY9p1MjHLlhX1SoVVe+WmzV12lyFh4WqYsVIff3tKm3dliCp8I/v/ZPdbujMmbMa98JIVa1SUZJUq8YN6t3fqs+/Wqk+Pe+67DGj6/9vAXZ3d3eVKxshNzeLUzBXoUI5paWlK+PMGfn5+qpG9apa8MlyzZizSLc1aqBaNW5wyfW5CsEUAAAAAAAoEtH168jP11ez5y3R3n0HdHvrpgX2W7z0S035cLbuvecu1a9bWwEB/vrzrz2a9N5HTiGVdG7WUNmIcB0+ckzd7uxY6NpGjbRq9MtvyTr8eUlS2Ygy6ndfD82Ys0ghpUsVetw8QYEBOlM62BFKSVJoaGlVqhipffsPFGrMgAA/p21PTw/5+ji/4dDzv48nZmVly8/XV33v7S43Nzd9s+JHzZy7WKWCg9T1zo7qf1+PfGt9mYFgCgAAAAAAFAl3d3e1atFYC5cs18031VS5shEF9vtxzXo1ua2hHhpwn6Ntf+LBAvvOmLNIp06nqEL5cnr7vY806Y0xhQpYykaU0dR3X9ORo0nKzMxUxQqRWvTpFwoNcc1bAytXKq9jScn52g1DVzUQ8vLy1IN9e+rBvj118NARffXtKs2Ys0jlyoarw+0tr1od53PtzN0CAAAAAADFTueObdTk1obq2f2O8/bJzMpyzPTJs+KHtfn6bU/YqY8XfaYhD/XTi6OGaXvCTi369Isrqq9c2XBVqVxROTk5+uqbH9S5Y5srGi9P41ujdfJUiv7el+hoSz5+QokHD6n6DVVcco7LVaF8OT00oI+CAgO0P/GQKTX8W4mdMRUXF6e4uDjl5uaaXQoAAAAAAMVWjWpV9cqYpy7Yp2GDW7Rk2Vf69LOvVbFCpFb8sFaHDh916nPm7Fm9OuE9NYyuqzs7tZMk9evTQx/N+FiNous5Hpl7feJkfbtitX74euEFz/npZ1/L399P4WXCdPRYkhZ9+oW8vDzVp9fdTv22bNuh0yk27dt/bgbXpi3bdfRYkspGhOvGmtUcfYY/PU5PDR+iju3OzUJq3qSRalavqhfGvamB/XvL09NDs+Z9olLBQbqjU1vH+EePJevPv3ZLks6ezdShI8f049r1kqRWzRtf8BouxXNj3lDNGjeoRrWq8vHx1roNG2VLTVODerWveGxXKLHBlNVqldVqlc1mU3BwsNnlAAAAAABQYvW/r4dOn7Zp+uxzYVLL5rdp6KMDNGr0a44+k6fOVmpqmp5+8lFH2/29u+qXXzfp1Qnvaso7r8rDw0N2u125dvtFz5mdnaOZcxcr+fgJBQUGqkXTRhrYv3e+NZtmzFmkLf9dFF2Spk6bK0nq2K6lY5F1w5By7XYZxv/O6+7urjdeeU7vvT9Tb70zVTk5uap7S5RefGaY0zk2b92u196a7Nj+deMW/bpxiyRp9beLL3odF1P75lpatWa9Fi35XLm5uapYIVIvPDNMDRvccvGDrwKLYRiG2UWYKS+YSklJUVBQkNnlFNqePXvUe8AjqtJ5iILCK5hdDlzMlnRQ+76crAXT31e1atXMLgcAAADAdSLpZKoOJp1WcICvKkSUNrscXMeysnO0KzFJbhaL6tW6cO5wOVkLa0wBAAAAAADAFARTAAAAAAAAMAXBFAAAAAAAxZSbm0WSZLeX6FV84AK5/72H3N1dGyURTAEAAAAAUEzlhQi5uRdfDBy4kLx7yN2NYAoAAAAAAFwCD3d3SVJ2Tq5K+LvPcIWyc3IlSR7MmAIAAAAAAJfC38dTbhaLsnNzlZWdY3Y5uI6ln8mUJAX4ebt0XIIpAAAAAACKKTc3N0eQkJaRaXI1uF4ZhuG4f4L8fVw6NsEUAAAAAADFWF6QkJp+1uRKcL3KOJulXLtd7m5u8vf1cunYJTaYiouLU1RUlGJiYswuBQAAAACAIhMc4CuLLEo/m0U4hctmGIaSTqRKkkoF+spisbh0/BIbTFmtViUkJCg+Pt7sUgAAAAAAKDLeXh4qExIgSTpyPMWxiDVwKY6fTlNGZpbcLBaVCwty+fglNpgCAAAAAKCkKBcWJG9PD2Xn5GrfoePKzGIhdFyYYRhKPpmqpJPnZkuVDw+Wl6eHy89DMAUAAAAAQDHn7uamGpXKyNvTQ1k5udpzIEnHTtiUmZUjwzDMLg/XELvdUGr6Wf198LiSTp0LpcqFBalM6cAiOZ/roy4AAAAAAHDN8fL0UI1KZZR49JRs6Wd1/HSajp9Ok6eHuwL8vOXr7Sl3Nze5ubnJzcXrCOHaZMiQ3W4o125XTo5daWcylXE2yxFWuru5qXx4sMJKBRRZDQRTAAAAAACUEF6eHqpWIUwpaWeVfCpNaWcylZ2Tq1O2DJ0yuzhcM7w83BUc6KuyoUHy9HAv0nMRTAEAAAAAUIJYLBaVCvRVqUBf5drtSsvIlC39rLKyc5Wba1dOrl2GeLyvpHC3uMnd3U0e7m7y9/VSkL+PvL08XP72vfMhmAIAAAAAoIRyd3NTcICvggN8zS4FJRSLnwMAAAAAAMAUBFMAAAAAAAAwBcEUAAAAAAAATEEwBQAAAAAAAFMQTAEAAAAAAMAUBFMAAAAAAAAwRYkNpuLi4hQVFaWYmBizSwEAAAAAACiRSmwwZbValZCQoPj4eLNLAQAAAAAAKJFKbDAFAAAAAAAAcxFMAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAUxBMAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAUxBMAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAUxBMAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAUxSbYCojI0OVK1fWyJEjzS4FAAAAAAAAl6DYBFOvvPKKbr31VrPLAAAAAAAAwCUqFsHUrl279Oeff6pTp05mlwIAAAAAAIBLZHowtWbNGnXp0kWRkZGyWCxatmxZvj6TJ09W1apV5ePjo+joaK1du9Zp/8iRIzV+/PirVDEAAAAAAABcwfRgKj09XXXr1tV7771X4P6FCxfqiSee0HPPPafNmzerefPmio2NVWJioiTps88+U82aNVWzZs2rWTYAAAAAAACukIfZBcTGxio2Nva8+ydOnKiBAwdq0KBBkqRJkybp22+/1ZQpUzR+/Hj98ssvWrBggRYvXqy0tDRlZ2crKChIL774YoHjZWZmKjMz07Fts9lce0EAAAAAAAC4JKbPmLqQrKws/fbbb2rfvr1Te/v27bVu3TpJ0vjx43XgwAHt27dPb775pgYPHnzeUCqvf3BwsONTsWLFIr0GAAAAAAAAFOyaDqaOHz+u3NxcRUREOLVHRETo6NGjhRpz1KhRSklJcXwOHDjgilIBAAAAAABwmUx/lO9SWCwWp23DMPK1SdIDDzxw0bG8vb3l7e3tqtIAAAAAAABQSNf0jKmwsDC5u7vnmx2VlJSUbxYVAAAAAAAAri/XdDDl5eWl6OhorVixwql9xYoVatKkyRWNHRcXp6ioKMXExFzROAAAAAAAACgc0x/lS0tL0+7dux3be/fu1ZYtWxQSEqJKlSpp+PDh6tu3rxo2bKjGjRvrgw8+UGJioh555JErOq/VapXVapXNZlNwcPCVXgYAAAAAAAAuk+nB1MaNG9W6dWvH9vDhwyVJ/fv318yZM9WrVy+dOHFC48aN05EjR1S7dm199dVXqly5slklAwAAAAAAwAVMD6ZatWolwzAu2GfIkCEaMmTIVaoIAAAAAAAAV8M1vcZUUWKNKQAAAAAAAHOV2GDKarUqISFB8fHxZpcCAAAAAABQIpXYYAoAAAAAAADmIpgCAAAAAACAKQimAAAAAAAAYIoSG0yx+DkAAAAAAIC5SmwwxeLnAAAAAAAA5iqxwRQAAAAAAADMRTAFAAAAAAAAUxBMAQAAAAAAwBQlNphi8XMAAAAAAABzldhgisXPAQAAAAAAzFVigykAAAAAAACYi2AKAAAAAAAApiCYAgAAAAAAgCkIpgAAAAAAAGAKgikAAAAAAACYosQGU3FxcYqKilJMTIzZpQAAAAAAAJRIJTaYslqtSkhIUHx8vNmlAAAAAAAAlEglNpgCAAAAAACAuQimAAAAAAAAYAqCKQAAAAAAAJiCYAoAAAAAAACmIJgCAAAAAACAKQimAAAAAAAAYIoSG0zFxcUpKipKMTExZpcCwAXGjx+vmJgYBQYGKjw8XHfffbd27tzp1MdisRT4mTBhgiTp5MmTevzxx1WrVi35+fmpUqVKGjp0qFJSUpzGeeWVV9SkSRP5+fmpVKlSV+sSAQAAAKDYKbHBlNVqVUJCguLj480uBYALrF69WlarVb/88otWrFihnJwctW/fXunp6Y4+R44ccfpMnz5dFotF3bt3lyQdPnxYhw8f1ptvvqnff/9dM2fO1DfffKOBAwc6nSsrK0v33HOPHn300at6jQAAAABQ3HiYXQAAuMI333zjtD1jxgyFh4frt99+U4sWLSRJZcuWderz2WefqXXr1rrhhhskSbVr19aSJUsc+6tVq6ZXXnlF999/v3JycuThce6XzLFjx0qSZs6cWVSXAwAAAAAlAsEUgGIp7/G7kJCQAvcfO3ZMX375pWbNmnXRcYKCghyhFAAAAADAdUrso3wAii/DMDR8+HA1a9ZMtWvXLrDPrFmzFBgYqG7dup13nBMnTuill17Sww8/XFSlAgAAAECJxhQAAMXOY489pm3btumnn346b5/p06frvvvuk4+PT4H7bTabOnfurKioKI0ePbqoSgUAAACAEo1gCkCx8vjjj2v58uVas2aNKlSoUGCftWvXaufOnVq4cGGB+1NTU9WxY0cFBARo6dKl8vT0LMqSAQAAAKDE4lE+AMWCYRh67LHH9Omnn+qHH35Q1apVz9t32rRpio6OVt26dfPts9lsat++vby8vLR8+fLzzqgCAAAAAFw5ZkwBKBasVqvmz5+vzz77TIGBgTp69KgkKTg4WL6+vo5+NptNixcv1ltvvZVvjNTUVLVv314ZGRmaO3eubDabbDabJKlMmTJyd3eXJCUmJurkyZNKTExUbm6utmzZIkmqXr26AgICivhKAQAAAKD4IJgCUCxMmTJFktSqVSun9hkzZuiBBx5wbC9YsECGYejee+/NN8Zvv/2mDRs2SDoXMv3T3r17VaVKFUnSiy++6PQ2v/r160uSVq1ale/8AAAAAIDzK7HBVFxcnOLi4pSbm2t2KQBcwDCMS+r30EMP6aGHHipwX6tWrS5pnJkzZ2rmzJmXUx4AAAAAoAAldo0pq9WqhIQExcfHm10KAAAAAABAiVRiZ0wBuLjk5GTHGksofoKCglSmTBmzywAAAABQghFMAShQcnKy7n9wkE6mZphdCopISKCf5s74iHAKAAAAgGkIpgAUyGaz6WRqhso07i7/kAizy4GLpZ88puT1S2Sz2QimAAAAAJiGYArABfmHRCgovILZZaAIJJtdAAAAAIASr8Qufg4AAAAAAABzEUwBAAAAAADAFARTAAAAAAAAMAXBFAAAAAAAAExBMAUAAAAAAABTEEwBAAAAAADAFARTAAAAAAAAMAXBFAAAAAAAAExRYoOpuLg4RUVFKSYmxuxSAAAAAAAASqQSG0xZrVYlJCQoPj7e7FIAAAAAAABKpBIbTAEAAAAAAMBcBFMAAAAAAAAwBcEUAAAAAAAATFGoYGrv3r2urgMAAAAAAAAlTKGCqerVq6t169aaO3euzp496+qaAAAAAAAAUAIUKpjaunWr6tevrxEjRqhs2bJ6+OGH9euvv7q6NgAAAAAAABRjhQqmateurYkTJ+rQoUOaMWOGjh49qmbNmunmm2/WxIkTlZyc7Oo6AQAAAAAAUMxc0eLnHh4e6tq1qxYtWqTXX39de/bs0ciRI1WhQgX169dPR44ccVWdAAAAAAAAKGauKJjauHGjhgwZonLlymnixIkaOXKk9uzZox9++EGHDh3SXXfd5ao6AQAAAAAAUMx4FOagiRMnasaMGdq5c6c6deqk2bNnq1OnTnJzO5dzVa1aVVOnTtWNN97o0mIBAAAAAABQfBQqmJoyZYoGDBigBx98UGXLli2wT6VKlTRt2rQrKg4AAAAAAADFV6GCqV27dl20j5eXl/r371+Y4QEAAAAAAFACFGqNqRkzZmjx4sX52hcvXqxZs2ZdcVEAAAAAAAAo/goVTL322msKCwvL1x4eHq5XX331iosCAAAAAABA8VeoYGr//v2qWrVqvvbKlSsrMTHxiosCAAAAAABA8VeoYCo8PFzbtm3L175161aFhoZecVEAAAAAAAAo/goVTPXu3VtDhw7VqlWrlJubq9zcXP3www8aNmyYevfu7eoaAQAAAAAAUAwV6q18L7/8svbv36+2bdvKw+PcEHa7Xf369bvqa0ylpqaqTZs2ys7OVm5uroYOHarBgwdf1RoAAAAAAABw+QoVTHl5eWnhwoV66aWXtHXrVvn6+qpOnTqqXLmyq+u7KD8/P61evVp+fn7KyMhQ7dq11a1bNx4pBAAAAAAAuMYVKpjKU7NmTdWsWdNVtRSKu7u7/Pz8JElnz55Vbm6uDMMwtSYAAAAAAABcXKHWmMrNzdW0adPUp08f3X777WrTpo3T53KsWbNGXbp0UWRkpCwWi5YtW5avz+TJk1W1alX5+PgoOjpaa9euddp/+vRp1a1bVxUqVNBTTz2lsLCwwlwWAAAAAAAArqJCBVPDhg3TsGHDlJubq9q1a6tu3bpOn8uRnp6uunXr6r333itw/8KFC/XEE0/oueee0+bNm9W8eXPFxsYqMTHR0adUqVLaunWr9u7dq/nz5+vYsWOFuSwAAAAAAABcRYV6lG/BggVatGiROnXqdMUFxMbGKjY29rz7J06cqIEDB2rQoEGSpEmTJunbb7/VlClTNH78eKe+ERERuuWWW7RmzRrdc889BY6XmZmpzMxMx7bNZrviawAAAAAAAMDlK9SMKS8vL1WvXt3VteSTlZWl3377Te3bt3dqb9++vdatWydJOnbsmCNcstlsWrNmjWrVqnXeMcePH6/g4GDHp2LFikV3AQAAAAAAADivQgVTI0aM0DvvvFPki4wfP35cubm5ioiIcGqPiIjQ0aNHJUkHDx5UixYtVLduXTVr1kyPPfaYbrnllvOOOWrUKKWkpDg+Bw4cKNJrAAAAAAAAQMEK9SjfTz/9pFWrVunrr7/WzTffLE9PT6f9n376qUuKy2OxWJy2DcNwtEVHR2vLli2XPJa3t7e8vb1dWR4AAAAAAAAKoVDBVKlSpdS1a1dX15JPWFiY3N3dHbOj8iQlJeWbRQUAAAAAAIDrS6GCqRkzZri6jgJ5eXkpOjpaK1ascArCVqxYobvuuuuKxo6Li1NcXJxyc3OvtEwAAAAAAAAUQqGCKUnKycnRjz/+qD179qhPnz4KDAzU4cOHFRQUpICAgEseJy0tTbt373Zs7927V1u2bFFISIgqVaqk4cOHq2/fvmrYsKEaN26sDz74QImJiXrkkUcKW7okyWq1ymq1ymazKTg4+IrGAgAAAAAAwOUrVDC1f/9+dezYUYmJicrMzFS7du0UGBioN954Q2fPntX7779/yWNt3LhRrVu3dmwPHz5cktS/f3/NnDlTvXr10okTJzRu3DgdOXJEtWvX1ldffaXKlSsXpnQAAAAAAABcIwoVTA0bNkwNGzbU1q1bFRoa6mjv2rWrBg0adFljtWrV6qJv9xsyZIiGDBlSmFIBAAAAAABwjSr0W/l+/vlneXl5ObVXrlxZhw4dcklhRY01pgAAAAAAAMzlVpiD7HZ7gYHOwYMHFRgYeMVFXQ1Wq1UJCQmKj483uxQAAAAAAIASqVDBVLt27TRp0iTHtsViUVpamkaPHq1OnTq5qjYAAAAAAAAUY4V6lO/tt99W69atFRUVpbNnz6pPnz7atWuXwsLC9PHHH7u6RgAAAAAAABRDhQqmIiMjtWXLFn388cfatGmT7Ha7Bg4cqPvuu0++vr6urhEAAAAAAADFUKGCKUny9fXVgAEDNGDAAFfWc9Ww+DkAAAAAAIC5ChVMzZ49+4L7+/XrV6hiriar1Sqr1Sqbzabg4GCzywEAAAAAAChxChVMDRs2zGk7OztbGRkZ8vLykp+f33URTAEAAAAAAMBchXor36lTp5w+aWlp2rlzp5o1a8bi5wAAAAAAALgkhQqmClKjRg299tpr+WZTAQAAAAAAAAVxWTAlSe7u7jp8+LArhywycXFxioqKUkxMjNmlAAAAAAAAlEiFWmNq+fLlTtuGYejIkSN677331LRpU5cUVtRY/BwAAAAAAMBchQqm7r77bqdti8WiMmXKqE2bNnrrrbdcURcAAAAAAACKuUIFU3a73dV1AAAAAAAAoIRx6RpTAAAAAAAAwKUq1Iyp4cOHX3LfiRMnFuYUAAAAAAAAKOYKFUxt3rxZmzZtUk5OjmrVqiVJ+uuvv+Tu7q4GDRo4+lksFtdUCQAAAAAAgGKnUMFUly5dFBgYqFmzZql06dKSpFOnTunBBx9U8+bNNWLECJcWWRTi4uIUFxen3Nxcs0sBAAAAAAAokQq1xtRbb72l8ePHO0IpSSpdurRefvnl6+atfFarVQkJCYqPjze7FAAAAAAAgBKpUMGUzWbTsWPH8rUnJSUpNTX1iosCAAAAAABA8VeoYKpr16568MEH9cknn+jgwYM6ePCgPvnkEw0cOFDdunVzdY0AAAAAAAAohgq1xtT777+vkSNH6v7771d2dva5gTw8NHDgQE2YMMGlBQIAAAAAAKB4KlQw5efnp8mTJ2vChAnas2ePDMNQ9erV5e/v7+r6AAAAAAAAUEwV6lG+PEeOHNGRI0dUs2ZN+fv7yzAMV9UFAAAAAACAYq5QwdSJEyfUtm1b1axZU506ddKRI0ckSYMGDdKIESNcWiAAAAAAAACKp0IFU08++aQ8PT2VmJgoPz8/R3uvXr30zTffuKy4ohQXF6eoqCjFxMSYXQoAAAAAAECJVKg1pr777jt9++23qlChglN7jRo1tH//fpcUVtSsVqusVqtsNpuCg4PNLgcAAAAAAKDEKdSMqfT0dKeZUnmOHz8ub2/vKy4KAAAAAAAAxV+hgqkWLVpo9uzZjm2LxSK73a4JEyaodevWLisOAAAAAAAAxVehHuWbMGGCWrVqpY0bNyorK0tPPfWUduzYoZMnT+rnn392dY0AAAAAAAAohgo1YyoqKkrbtm1To0aN1K5dO6Wnp6tbt27avHmzqlWr5uoaAQAAAAAAUAxd9oyp7OxstW/fXlOnTtXYsWOLoiYAAAAAAACUAJc9Y8rT01Pbt2+XxWIpinoAAAAAAABQQhTqUb5+/fpp2rRprq4FAAAAAAAAJUihFj/PysrSRx99pBUrVqhhw4by9/d32j9x4kSXFAcAAAAAAIDi67KCqb///ltVqlTR9u3b1aBBA0nSX3/95dTnennELy4uTnFxccrNzTW7FAAAAAAAgBLpsoKpGjVq6MiRI1q1apUkqVevXvq///s/RUREFElxRclqtcpqtcpmsyk4ONjscgAAAAAAAEqcy1pjyjAMp+2vv/5a6enpLi0IAAAAAAAAJUOhFj/P8++gCgAAAAAAALhUlxVMWSyWfGtIXS9rSgEAAAAAAODacllrTBmGoQceeEDe3t6SpLNnz+qRRx7J91a+Tz/91HUVAgAAAAAAoFi6rGCqf//+Ttv333+/S4sBAAAAAABAyXFZwdSMGTOKqg4AAAAAAACUMFe0+DkAAAAAAABQWARTAAAAAAAAMAXBFAAAAAAAAExBMAUAAAAAAABTEEwBAAAAAADAFARTAAAAAAAAMAXBFAAAAAAAAExRYoOpuLg4RUVFKSYmxuxSAAAAAAAASqQSG0xZrVYlJCQoPj7e7FIAAAAAAABKpBIbTAEAAAAAAMBcBFMAAAAAAAAwBcEUAAAAAAAATEEwBQDAJVqzZo26dOmiyMhIWSwWLVu2zLEvOztbTz/9tOrUqSN/f39FRkaqX79+Onz4sNMYmZmZevzxxxUWFiZ/f3/deeedOnjw4FW+EgAAAODaQDAFAMAlSk9PV926dfXee+/l25eRkaFNmzbphRde0KZNm/Tpp5/qr7/+0p133unU74knntDSpUu1YMEC/fTTT0pLS9Mdd9yh3Nzcq3UZAAAAwDXDw+wCAAC4XsTGxio2NrbAfcHBwVqxYoVT27vvvqtGjRopMTFRlSpVUkpKiqZNm6Y5c+bo9ttvlyTNnTtXFStW1MqVK9WhQ4civwYAAADgWsKMKQAAikhKSoosFotKlSolSfrtt9+UnZ2t9u3bO/pERkaqdu3aWrdunUlVAgAAAOYhmAIAoAicPXtWzzzzjPr06aOgoCBJ0tGjR+Xl5aXSpUs79Y2IiNDRo0fNKBMAAAAwFcEUAAAulp2drd69e8tut2vy5MkX7W8YhiwWy1WoDAAAALi2EEwBAOBC2dnZ6tmzp/bu3asVK1Y4ZktJUtmyZZWVlaVTp045HZOUlKSIiIirXSoAAABgOoIpAABcJC+U2rVrl1auXKnQ0FCn/dHR0fL09HRaJP3IkSPavn27mjRpcrXLBQAAAEzHW/kAALhEaWlp2r17t2N779692rJli0JCQhQZGakePXpo06ZN+uKLL5Sbm+tYNyokJEReXl4KDg7WwIEDNWLECIWGhiokJEQjR45UnTp1HG/pAwAAAEoSgikAAC7Rxo0b1bp1a8f28OHDJUn9+/fXmDFjtHz5cklSvXr1nI5btWqVWrVqJUl6++235eHhoZ49e+rMmTNq27atZs6cKXd396tyDQAAAMC1hGAKAIBL1KpVKxmGcd79F9qXx8fHR++++67effddV5YGAAAAXJdYYwoAAAAAAACmYMYUAOCqSk5Ols1mM7sMFIGgoCCVKVPG7DIAAABwHbnug6kDBw6ob9++SkpKkoeHh1544QXdc889ZpcFAChAcnKy7n9wkE6mZphdCopASKCf5s74iHAKAAAAl+y6D6Y8PDw0adIk1atXT0lJSWrQoIE6deokf39/s0sDAPyLzWbTydQMlWncXf4hEWaXAxdKP3lMyeuXyGazEUwBAADgkl33wVS5cuVUrlw5SVJ4eLhCQkJ08uRJgikAuIb5h0QoKLyC2WXAxZLNLgAAAADXHdMXP1+zZo26dOmiyMhIWSwWLVu2LF+fyZMnq2rVqvLx8VF0dLTWrl1b4FgbN26U3W5XxYoVi7hqAAAAAAAAXCnTg6n09HTVrVtX7733XoH7Fy5cqCeeeELPPfecNm/erObNmys2NlaJiYlO/U6cOKF+/frpgw8+uBplAwAAAAAA4AqZ/ihfbGysYmNjz7t/4sSJGjhwoAYNGiRJmjRpkr799ltNmTJF48ePlyRlZmaqa9euGjVqlJo0aXJV6gYAAAAAAMCVMX3G1IVkZWXpt99+U/v27Z3a27dvr3Xr1kmSDMPQAw88oDZt2qhv374XHTMzM1M2m83pAwAAAAAAgKvvmg6mjh8/rtzcXEVEOL+5KSIiQkePHpUk/fzzz1q4cKGWLVumevXqqV69evr999/PO+b48eMVHBzs+LAeFQAAAAAAgDlMf5TvUlgsFqdtwzAcbc2aNZPdbr/ksUaNGqXhw4c7tm02G+EUAAAAAACACa7pYCosLEzu7u6O2VF5kpKS8s2iulTe3t7y9vZ2RXkAAAAAAAC4Atf0o3xeXl6Kjo7WihUrnNpXrFhxxYucx8XFKSoqSjExMVc0DgAAAAAAAArH9BlTaWlp2r17t2N779692rJli0JCQlSpUiUNHz5cffv2VcOGDdW4cWN98MEHSkxM1COPPHJF57VarbJarbLZbAoODr7SywAAAAAAAMBlMj2Y2rhxo1q3bu3Yzlv/qX///po5c6Z69eqlEydOaNy4cTpy5Ihq166tr776SpUrVzarZAAAAAAAALiA6cFUq1atZBjGBfsMGTJEQ4YMuUoVAQAAAAAA4Gq4pteYAgAAAAAAQPFVYoMpFj8HAAAAAAAwV4kNpqxWqxISEhQfH292KQAAAAAAACVSiQ2mAAAAAAAAYC6CKQAAAAAAAJiixAZTrDEFAAAAAABgrhIbTLHGFAAAAAAAgLlKbDAFAAAAAAAAcxFMAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMUWKDKd7KBwAAAAAAYK4SG0zxVj4AAAAAAABzldhgCgAAAAAAAOYimAIAAAAAAIApCKYAAAAAAABgCoIpAAAAAAAAmKLEBlO8lQ8AAAAAAMBcJTaY4q18AAAAAAAA5iqxwRQAAAAAAADMRTAFAAAAAAAAUxBMAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAU5TYYCouLk5RUVGKiYkxuxQAAAAAAIASqcQGU1arVQkJCYqPjze7FAAAAAAAgBKpxAZTAAAAAAAAMBfBFAAAAAAAAExBMAUAAAAAAABTEEwBAAAAAADAFARTAAAAAAAAMAXBFAAAAAAAAExBMAUAAAAAAABTEEwBAAAAAADAFARTAAAAAAAAMEWJDabi4uIUFRWlmJgYs0sBAAAAAAAokUpsMGW1WpWQkKD4+HizSwEAAAAAACiRSmwwBQAAAAAAAHMRTAEAAAAAAMAUBFMAAAAAAAAwBcEUAAAAAAAATEEwBQAAAAAAAFMQTAEAAFxD1qxZoy5duigyMlIWi0XLli1z2m+xWAr8TJgwwZyCAQAArgDBFAAAwDUkPT1ddevW1XvvvVfg/iNHjjh9pk+fLovFou7du1/lSgEAAK6ch9kFAAAA4H9iY2MVGxt73v1ly5Z12v7ss8/UunVr3XDDDUVdGgAAgMsRTAEAAFynjh07pi+//FKzZs0yuxQAAIBC4VE+AACA69SsWbMUGBiobt26mV0KAABAoRBMAQAAXKemT5+u++67Tz4+PmaXAgAAUCg8ygcAAHAdWrt2rXbu3KmFCxeaXQoAAEChldgZU3FxcYqKilJMTIzZpQAAAFy2adOmKTo6WnXr1jW7FAAAgEIrscGU1WpVQkKC4uPjzS4FAADAIS0tTVu2bNGWLVskSXv37tWWLVuUmJjo6GOz2bR48WINGjTIpCoBAABcg0f5AAAAriEbN25U69atHdvDhw+XJPXv318zZ86UJC1YsECGYejee+81o0QAAACXIZgCAAC4hrRq1UqGYVywz0MPPaSHHnroKlUEAABQdErso3wAAAAAAAAwFzOmAADAdS05OVk2m83sMlAEgoKCVKZMGbPLAAAARYhgCgAAXLeSk5N1/4ODdDI1w+xSUARCAv00d8ZHhFMAABRjBFMAAOC6ZbPZdDI1Q2Uad5d/SITZ5cCF0k8eU/L6JbLZbARTAAAUYwRTAADguucfEqGg8ApmlwEXSza7AAAAUORY/BwAAAAAAACmIJgCAAAAAACAKQimAAAAAAAAYAqCKQAAAAAAAJiCYAoAAAAAAACmIJgCAAAAAACAKQimAAAAAAAAYAqCKQAAAAAAAJiCYAoAAAAAAACmIJgCAAAAAACAKYpFMNW1a1eVLl1aPXr0MLsUAAAAAAAAXKJiEUwNHTpUs2fPNrsMAAAAAAAAXIZiEUy1bt1agYGBZpcBAAAAAACAy2B6MLVmzRp16dJFkZGRslgsWrZsWb4+kydPVtWqVeXj46Po6GitXbv26hcKAAAAAAAAlzI9mEpPT1fdunX13nvvFbh/4cKFeuKJJ/Tcc89p8+bNat68uWJjY5WYmHiVKwUAAAAAAIAreZhdQGxsrGJjY8+7f+LEiRo4cKAGDRokSZo0aZK+/fZbTZkyRePHj7/s82VmZiozM9OxbbPZLr9oAAAAAAAAXDHTZ0xdSFZWln777Te1b9/eqb19+/Zat25docYcP368goODHZ+KFSu6olQAAAAAAABcpms6mDp+/Lhyc3MVERHh1B4REaGjR486tjt06KB77rlHX331lSpUqKD4+Pjzjjlq1CilpKQ4PgcOHCiy+gEAAAAAAHB+pj/KdyksFovTtmEYTm3ffvvtJY/l7e0tb29vl9UGAAAAAACAwrmmZ0yFhYXJ3d3daXaUJCUlJeWbRQUAAAAAAIDryzUdTHl5eSk6OlorVqxwal+xYoWaNGlyRWPHxcUpKipKMTExVzQOAAAAAAAACsf0R/nS0tK0e/dux/bevXu1ZcsWhYSEqFKlSho+fLj69u2rhg0bqnHjxvrggw+UmJioRx555IrOa7VaZbVaZbPZFBwcfKWXAQAAAAAAgMtkejC1ceNGtW7d2rE9fPhwSVL//v01c+ZM9erVSydOnNC4ceN05MgR1a5dW1999ZUqV65sVskAAAAAAABwAdODqVatWskwjAv2GTJkiIYMGXKVKgIAAAAAAMDVcE2vMVWUWGMKAAAAAADAXCU2mLJarUpISFB8fLzZpQAAAAAAAJRIJTaYAgAAAAAAgLkIpgAAAAAAAGAKgikAAAAAAACYosQGUyx+DgAAAAAAYK4SG0yx+DkAAAAAAIC5SmwwBQAAAAAAAHMRTAEAAAAAAMAUBFMAAAAAAAAwRYkNplj8HAAAAAAAwFwlNphi8XMAAAAAAABzldhgCgAAAAAAAOYimAIAAAAAAIApCKYAAAAAAABgCoIpAAAAAAAAmIJgCgAAAAAAAKYoscFUXFycoqKiFBMTY3YpAAAAAAAAJVKJDaasVqsSEhIUHx9vdikAAAAAAAAlUokNpgAAAAAAAGAugikAAAAAAACYgmAKAAAAAAAApiCYAgAAAAAAgCkIpgAAAAAAAGAKgikAAAAAAACYosQGU3FxcYqKilJMTIzZpQAAAAAAAJRIJTaYslqtSkhIUHx8vNmlAAAAAAAAlEglNpgCAAAAAACAuQimAAAAAAAAYAqCKQAAAAAAAJiCYAoAAAAAAACmIJgCAAAAAACAKQimAAAAAAAAYAqCKQAAAAAAAJiCYAoAAAAAAACmKLHBVFxcnKKiohQTE2N2KQAAAAAAACVSiQ2mrFarEhISFB8fb3YpAAAAwFUzfvx4xcTEKDAwUOHh4br77ru1c+dOs8vCdYx7CsCVKLHBFAAAAFASrV69WlarVb/88otWrFihnJwctW/fXunp6WaXhusU9xSAK+FhdgEAAAAArp5vvvnGaXvGjBkKDw/Xb7/9phYtWphUFa5n3FMArgQzpgAAAIASLCUlRZIUEhJiciUoLrinAFwOgikAAACghDIMQ8OHD1ezZs1Uu3Zts8tBMcA9BeBy8SgfAAAAUEI99thj2rZtm3766SezS0ExwT0F4HIRTAEAAAAl0OOPP67ly5drzZo1qlChgtnloBjgngJQGARTAAAAQAliGIYef/xxLV26VD/++KOqVq1qdkm4znFPAbgSBFMAAABACWK1WjV//nx99tlnCgwM1NGjRyVJwcHB8vX1Nbk6XI+4pwBcCRY/BwAAAEqQKVOmKCUlRa1atVK5cuUcn4ULF5pdGq5T3FMArgQzpgAAAIASxDAMs0tAMcM9BeBKMGMKAAAAAAAApmDGFAAAAPAPycnJstlsZpeBIhAUFKQyZcpc9fNyTxVfZt1TQHFSYoOpuLg4xcXFKTc31+xSAAAAcI1ITk7W/Q8O0snUDLNLQREICfTT3BkfXdUggXuqeDPjngKKmxIbTFmtVlmtVtlsNgUHB5tdDgAAAK4BNptNJ1MzVKZxd/mHRJhdDlwo/eQxJa9fIpvNdlVDBO6p4susewoobkpsMAUAAACcj39IhILCK5hdBlws2cRzc08VT2beU0BxweLnAAAAAAAAMAXBFAAAAAAAAExBMAUAAAAAAABTEEwBAAAAAADAFARTAAAAAAAAMAXBFAAAAAAAAExBMAUAAAAAAABTEEwBAAAAAADAFARTAAAAAAAAMAXBFAAAAAAAAExBMAUAAAAAAABTEEwBAAAAAADAFARTAAAAAAAAMAXBFAAAAAAAAExBMAUAAAAAAABTEEwBAAAAAADAFARTAAAAAAAAMIWH2QWYzTAMSZLNZjO5kiuTmpqq3JwcZZ/NUNaZNLPLgYtln81Qbk6OUlNTr9q9yj1VvJlxT0ncV8UZ9xRcjXsKrsY9BVcz654Crgd5/03kZS4XYjEupVcxdvDgQVWsWNHsMgAAAAAAAIqVAwcOqEKFChfsU+KDKbvdrsOHDyswMFAWi8XscnCJbDabKlasqAMHDigoKMjsclAMcE/B1bin4GrcU3A17ikUBe4ruBr31PXJMAylpqYqMjJSbm4XXkWqxD/K5+bmdtH0DteuoKAgfnGCS3FPwdW4p+Bq3FNwNe4pFAXuK7ga99T1Jzg4+JL6sfg5AAAAAAAATEEwBQAAAAAAAFMQTOG65O3trdGjR8vb29vsUlBMcE/B1bin4GrcU3A17ikUBe4ruBr3VPFX4hc/BwAAAAAAgDmYMQUAAAAAAABTEEwBAAAAAADAFARTAAAAAAAAMAXBFAAAAAAAAExBMAUAAAAAAABTEEwBAAAAAADAFARTAAAAQDFiGIYkyW63O20DAHAtIpjCNSPvN02nT582txAUG3n31IYNG7R+/XplZ2ebXBGud3n3FH/Igyvl3U9JSUkmV4LiwDAMWSwWff/993r66aeVkZEhi8Vidlm4juX9GrVjxw7t3r3b5GpQXPF7q5KNYArXhLzfRH355Zfq2rWrfv31V7NLwnUu755aunSp7rjjDn3++ec6efKk2WXhOpZ3T3333Xd65plnlJaWZnZJKAb++f+/u+++W59//rnZJeE6Z7FYtGTJEvXs2VPZ2dn6888/Hfv4gx8u1z9/P9W9e3fNmjVLp06dMrssXOfyfi365ZdftHDhQkkiQC/hCKZwTbBYLPr000917733qmXLlvLw8DC7JFznLBaLVqxYob59++qNN97QqFGjFBERYXZZuI7l/WGvd+/eysjI0L59+8wuCcVA3v//evXqpW7duikyMtLsknCd27hxowYPHqzXXntNkyZNUoMGDSRJZ8+e5Q9+uGwWi0VffPGF+vTpoyeeeELDhg1T6dKlzS4L17G8sHPJkiXq2rWr4uPjtXPnTqf9KHksBj95XAP+/vtvtW3bViNHjpTVanW079ixQ1WqVJG/v7+J1eF6ZBiGhg0bpszMTE2dOlUZGRn6888/NXv2bEVGRqpp06Zq2rSp2WXiOrJx40a1b99eb775pgYMGOBoP3v2rHx8fEysDNezxMREdejQQY899pisVqvjN+Tr169X/fr15evra3KFuN58+OGHWrx4sb777judOnVK33//vebOnaudO3dq+PDhGjhwoNzc+LtpXBqbzabevXurRYsWeuaZZ5Senq6kpCR99tlnqlKliu644w7+QhmX7YcfftCdd96pt99+W4MHDza7HFwD+FUE14Tjx4/Lx8dH/fv31+nTpzVnzhx9+umn+vnnn3X33XfrpZdeUq1atcwuE9cRu92uxMREpaamauvWrXr77bd16NAhJSUlyc3NTVu2bFHdunXl7+/P3yDjkvz5559q2LChBgwYoFOnTmnFihWaO3eu9u/frwEDBmjgwIEKCAgwu0xcZ06dOqWMjAx17dpVmZmZeu+997Rs2TKtX79eMTExWrBggSpXrmx2mbiOhIWFaeXKlZo4caI+//xzBQQEKDw8XB07dtTDDz+sNm3aqFq1amaXietEYGCgUlNTdejQIaWmpur555/X5s2bdejQIe3fv1+vv/66RowYYXaZuE4YhiHDMLRs2TLdd999Gjx4sE6fPq3t27drwYIFysjI0LPPPqvq1as7ZlahZOCvS3BNqFatmg4dOqSuXbvq1ltv1Q8//KCWLVvqu+++02effaYNGzaYXSKucf+e/Onu7q4XX3xR27dv1+23366MjAw9+uij2rp1qx599FH99ddfcnNz4394uKB/3lc+Pj5a+f/t3WdYFOfaB/D/7lIEVKQJliC2iKBYsHexEQ0qigUNisbeAANoLEksRyxYQA1qFMEeExsaRQMKEjnGCjYsGEFURCyoVGH3eT/w7hxRYzQnceDk//u0zDyz3us11+zsPffz3FFRWL16Nfr06YPNmzfDysoK7dq1w5w5c3D37l0ZI6Wyqnbt2jA1NUX37t1hb2+PuLg4dO/eHampqbh48SJ++OEHuUOkUkx7jXp5zbuePXti9uzZCAkJga2tLWbNmoUNGzZgwYIFaNKkCZ49eyZXuFQGqdVq9OnTB4cPH4a5uTlu376NkSNH4ubNm5gyZQoOHz7M5jL0zhQKBZRKJcqVK4ejR4/ixIkTGDduHObNm4crV67g7NmzGDBggDSW/jlYMUUfnDb7nZaWBkNDQwCAmZkZjh49ipUrV6JTp0747LPPUL16dahUKnTq1IlzjemttOdUTEwMoqKiYGlpic6dO6Np06ZITExEeno6mjRpIp1HN27cgIWFhdRGm+hV2nMqJycH5cuXh0ajgZubG7788kusXr0anTp1wogRI9C8eXO8ePECv/zyCxeDpT+kPa9SUlKgVqthYWGBihUrYsuWLdi0aRPMzc0xdOhQVK5cGTo6OnBycuJaLvRW2vV/goODoaOjAzc3N/Tv3x9z5syBl5cXTE1NpbFz585FTk4OqlWrJmPEVJppr1Hnzp3DxYsXYWdnhyZNmmDSpElwdnbGb7/9ht69e0vjHz9+DBsbG04NpbfSnlcajUY6V1xcXHD58mV07doVrq6u8PLyQs+ePXH06FH4+voiMzMTFhYWMkdOHxLXmCJZ7N69G35+ftBoNGjRogVGjx6Nrl27lhgjhMDs2bOxYcMGxMfHo2bNmjJFS2XBwYMHMXDgQDg4OODp06coKirCd999hw4dOkhjfv31V+zduxfffvstjh8/jkaNGskYMZV2Bw4cwJIlS1CpUiW0a9cOkydPRrly5fDw4UOYm5tL42bMmIHdu3cjNjaWC+zTH9q1axd8fX3x7NkzdOjQAUOHDoWbm1uJMfn5+QgICMCaNWsQHx/PaVf0u06dOoWuXbti4sSJOHv2LJ4+fQoHBwfMmzcPVlZWAICoqCh8//332LNnD6KiotC4cWN5g6ZSbd++fRgyZAisra2RmpqKcePG4fPPP4e9vb005tatW1i7di3WrVuHuLi4EvuIXqZNSh09ehQHDhyAiYkJ3N3dpal6V65cKXH+eHt7IyEhAQcOHODyCP8wTG/TB5eSkgJfX1/4+fnB29sbQghMnToVe/fulcZERERg0KBB2LhxIw4ePMikFP2hU6dOISgoCPHx8QgLC0OLFi3Qr18//PLLLwCKq6SCg4Nx+PBhxMXFMSlFb3X69GkMHToUrVu3BlCcTPfw8EBubi7Mzc0hhMBPP/2E0aNHY926ddi+fTuTUvSH0tLS8PXXX2PGjBlYs2YNFAoFVqxYgTVr1khjDh48CE9PT2zYsAGRkZFMStFrXn6mnJGRgSlTpiAgIABHjhyBu7s7kpKSMHPmTDx48AB5eXm4dOkSMjMzERsby6QU/S6NRoOCggJs3boVQUFBuHTpElasWIGYmBgsW7YMFy5cAFCc6Jw3bx727NmDo0ePMilFb6VQKBAVFYVPPvkEKSkpCAwMxKhRo7B582YoFArp/Dl37hy8vLwQHh6OoKAgJqX+gZiYog/i5ZsoIQScnJwwbtw4eHl5Yfr06XB0dMTMmTMREREBAKhUqRKsra1x9OhRNGnSRK6wqRTTnlMpKSlITU3F5cuXpZLf5s2bY+bMmXB2dkbfvn0RHx+PunXr4quvvsJPP/0EBwcHOUOnUurl69SjR4/g4+ODhQsX4ocffsCYMWNw+/ZtDBs2DLm5uRBCIDU1FRkZGYiNjeV1it5Iu8irlq6uLho1aoRhw4ZhwIABWLRoET7++GNs2rQJa9euBQCYmprCzs6O33/0Rtrqg19//RU7d+7Ev//9b+jp6Un7vb294ebmhqtXr2L27NnIzc2Ft7c3Nm/ezAQCvZH2GvXkyRMolUpYWFigXbt2UKlUGDNmDHx8fJCQkICgoCDcuHEDbdq0gZubG6vv6J2dOHECixYtwu7du3H16lVUqlQJ69evR1hYGABIXbNPnTqF2NhYPjz+h+JUPvrbaW+ijhw5gv379wMoTiZoXwPFWfLg4GCcP38e33zzDVxdXVFYWAhdXV25wqYyYPfu3Rg9ejSqVauG1NRUrFixAiNGjJD2X716FQEBAdi8eTNOnDghVb8QvUp7nfr3v/+NtLQ0nDhxAgYGBli4cCEAoKCgANu2bcOaNWtQq1YthIaGwsDAAM+fP0eFChVkjp5KK+15dfjwYWzatAn6+vpIT0/HoUOHpDE3btzAggULkJycjCFDhmD8+PFQq9VQqVQyRk6l2a5duzB8+HCYmpri0aNHqFGjBuLj41GpUiVpzMqVKxESEoKuXbtixYoVXAOI3mr37t34+uuv8fz5c6jVamzdurXEUgibN2/GqlWrYG1tjQULFqBu3boyRkulnfa77/r161AoFNi4cSNat24NFxcXAMDdu3cxefJkPHr0CGPHjsWQIUPw22+/oUKFClxX6p9MEP1NNBqN9PrgwYNCX19fdO7cWTRo0EAoFAqxa9euEuPPnTsn+vXrJ1q2bCmeP39e4ngiLe15kZqaKmrXri1CQkLE1q1bxWeffSb09fVFdHR0ifGXLl0SY8aMEdeuXZMjXCpDdu3aJQwMDIS1tbWwsLAQDRo0KHEdKigoEOHh4aJOnTpi2LBhMkZKZUl0dLRQKpWif//+wt7eXujo6IgFCxaUGHPjxg3h5uYmunXrJp48eSJPoFSqaa9Fz58/FxMmTBAbN24Ujx8/Fhs2bBDNmzcXPXv2FA8fPixxTEhIiLh165YM0VJZoD2nbty4IUxNTcWCBQvEtGnThL29vejUqZP49ddfS4z/7rvvRMeOHcW9e/fkCJfKmJ07dwoLCwthYmIiVCqVmDJlSon9d+/eFQMGDBANGjQQO3bskClKKk1YMUV/u8zMTOzbtw9FRUUYN24ckpKSEBwcjG3btiEsLAyurq7S2MTERFhYWKBq1aoyRkylXVRUFJKSkqR1o4DiqVfTp0/Hli1b8NNPP8HJyUkaz+o7+j3i/5/q5efnY8KECejYsSN69uyJ2NhYzJw5E1ZWVjh69KhUvfLixQv8+OOPaN26Nde+oz908+ZNnD9/Hvfv38ekSZOQkpKCNWvWICIiAiNGjICfn1+JsYaGhqhSpYqMEVNpdvLkSXh6esLa2hpBQUGoX78+hBDYsWMHVq9eLXV4fLkTH9Hb/Prrr4iJicHTp0+xYMECAMWLn4eEhEClUuGbb75B8+bNpfHPnj1DxYoV5QqXSjntPVVmZib69u2LYcOGwdbWFhs2bEBiYiI8PDzg6+srjb9z5w6+/PJLzJs3DzY2NvIFTqUC63rpb3X9+nVYWlriX//6F4yNjQEA9evXh7+/Pzw8PODp6Yl9+/ZJ4xs1asSkFL0mNze3xN8HDhyAl5cX4uLikJWVBQAwMzPDwoULMXToUPTt2xeHDx+WxjMpRb9HoVAgLi4OzZo1Q2ZmJpo1awYLCwv07dsXwcHBePz4MZycnKDRaAAAenp6GDJkCJNS9IdSU1PRvHlzjB07FoaGhgAAGxsbjB8/Hn369MGGDRuwbNkyaXzt2rWZlKLfJYRATk4OKlWqhPj4eBgYGAAovoYNGjQIkyZNQm5uLlxcXPD48WOZo6XSTFuT8PDhQwQGBmLevHm4c+eOtL9Pnz4YN24cCgsLMX/+fMTHx0v7mJSit9EuieDj44PatWtj6NCh6NixIxYtWoT27dvjxx9/xJIlS6Tx1atXR1hYGJNSBICJKfobqNVq6bWVlRVmzJiBe/fuIS0tTdpes2ZN+Pr6YsSIEXB1dcWBAwfkCJXKgAsXLmDw4MElbppWrFiBb775BhcvXsTBgwel7WZmZli8eDF69uwJT0/P1xJaRK/SaDSoUKECVCoVjhw5IiWgdHR00KVLFwQGBuLZs2do0qSJtI/oTW7duoW4uDjpbyMjI0ybNg0qlQrnz5+XtteoUQPjx4+Hm5sbFi1ahJUrV8oRLpVyaWlp+P777/HDDz/g7NmzUCgU6Ny5M5YsWYKaNWuid+/eyM7OBgAolUoMHDgQnp6eqFixInJycmSOnkqjnJwcZGdn4/nz5wAAc3NzjBkzBl27dkVERAROnjwpje3bty8mTZqE+/fvIygoCPn5+XKFTWVIXl4eoqKiEBMTg7Nnz0qd9apUqYIZM2bA0dER+/btw9y5c6VjuJ4iSWScRkj/Y+7fvy+9LiwslF5nZWWJGTNmCKVSKbZv317imOTkZOHn5yeuXr36weKksiMhIUHo6OiImTNnStuKioqk1z4+PkJfX1/s3LmzxHGPHz/mGgj0RqmpqWLHjh0iNDRUXLhwQdqemJgo7O3tRdOmTUVOTo60vbCwUERERIg2bdqIlJQUOUKmMuD8+fNCoVCITZs2ldiemZkplixZIgwMDMScOXNK7Pvtt9/EnDlzRHJy8ocMlcqACxcuCEtLS+Hg4CBsbGyEvr6+mDVrlsjMzBRCCHH8+HHRtGlT0bRpU/H8+XPpOLVaLZ4+fSpX2FSKXbhwQXTt2lXY2tqKDh06iGnTpkn74uPjhYuLi2jSpImIj48vcdyBAwdEamrqhw6XyojMzEyRkJAgkpKSpGvR3bt3RUBAgKhQoYLw9fUtMf7u3bti2LBhomvXruLRo0dyhEylGBNT9JdISkoSurq6wsXFRdr24sUL6fXz58/FtGnThFKpfG2Bu5eTWERaFy5cEAYGBmLGjBkltr/6Rebl5SX09fXFjz/++CHDozIoMTFR+rFXu3ZtoaurK2bPni1u3LghhCg+5+rVqyeaN28ucnNzpeMKCwtFdna2XGFTKZeQkCCMjIzEF1988cb99+/fF4GBgaJSpUqvJaf4/UevevLkiWjcuLHw9fUVeXl54u7duyIsLEzo6+uLYcOGiTt37gghhIiJiRHNmjUTLVu2FM+ePZM5airNbt68KczMzISPj48ICQkRc+fOFaampqJbt27S+RQbGytcXV1FkyZNxMmTJ2WOmMqCxMREYWtrK2rWrCmsra2Fg4ODdO48evRIzJ8/X9SvX198+eWXJY5LT08X6enpcoRMpRwTU/Rfu3fvnmjTpo1o1aqVqFWrlujXr5+0703JKX19fREWFiZHqFRG3LlzR1hZWYlu3bpJ27y8vISTk5OoU6eOmDp1aolOQ1988YVQKBRi7969MkRLZcGTJ09Es2bNhL+/v8jOzhbZ2dli3bp1wtLSUowYMUJcunRJCPGfG63WrVuXqJwiepOLFy+WeCqsVqtFRESE+Pbbb0VoaKg07sGDByIwMFCYm5uXqFQgelVmZqaws7MThw8fLrE9OjpaGBgYiDFjxgghipOax44dE3Xq1BGdOnViJ2P6XWvWrBFt2rQR+fn50raLFy+KGjVqiA4dOkhVdtHR0WLAgAHCxsZGnDp1Sq5wqQy4e/eu+Oijj8S0adPE5cuXxU8//SQGDBggDAwMxNatW4UQQmRkZEjJqVmzZskcMZUFOnJPJaSyLyYmBlZWVpgyZQoePnwIX19f9O/fH7t27YKurq7UEa18+fKYNWsWsrOzMXXqVPTr1w8VKlSQO3wqhdRqNWrXrg1DQ0Ns374dq1evRvny5dGyZUv06tULc+fOxbVr1xAaGorKlSsjMDAQ+vr6qFevntyhUymlVqvx/PlztGnTBkZGRgCA0aNHw9zcHL6+vtDT00NAQAAcHBywY8cO9OjRAy4uLoiOjpY5cirN1qxZg+zsbLi7uyM/Px+9evVCTk4Obt++DV1dXSxatAjHjh1DlSpV4OHhgby8PKxfvx6+vr4wMzODQqGQ+yNQKaLRaJCbm4uUlBSpsUdRUREUCgWcnJywa9cu9OrVC23btsWwYcPQvn17hIWFoWrVqjyX6HfduXMHT548gb6+PoDi78MGDRogOjoaHTp0wKhRo7Bz5044OTlBrVajXLlyMDc3lzlqKs3S0tJgbGyMiRMn4qOPPoKdnR169uwJHx8fjBw5EuXLl0fv3r3h6ekJpVKJ4OBg6OnpYfbs2XKHTqWZ3JkxKvtycnLEvn37hBDFT/B27twpbGxsfrdyKjc3V2RkZHzwOKls0D71vXHjhnB2dhbm5ubCxcVFPHjwQBpz9epVYWBgIIKDg+UKk8oQjUYjfvvtN2FpaSlNJX75yfHOnTuFnp6e9JRPo9GIixcvcu0feid9+/YV5ubmomnTpqJ3794iKSlJZGZmiitXrogWLVqIZs2aCbVaLYQoXv+O62rQq16eOiyEEBMmTBAff/yxtA5eUVGRNO3T29tbdOzYUWRlZX3wOKls0d5PxcfHC2Nj4xLrvGrX6/z5559F5cqVxf79+6V9r56PRK/66aefhEKhkO7NX56WPm7cOGFsbCytTXbv3j0RGBjIeyr6Q+zKR/81Q0ND9O7dG0BxJysXFxcsWbIE586dQ//+/QEAurq6WLduHZKTk2FgYIDKlSvLGTKVYgqFAhqNBnXq1MHKlSvRr18/TJkyBRYWFgCKn/TVq1cPjRo1wtWrV2WOlsoChUKBmjVrol+/fvD29sadO3egr6+PwsJCCCEwYMAAjB8/HoGBgcjJyYFCoUCDBg1Qu3ZtuUOnMmDPnj3o0KEDsrKysHz5ctja2sLc3Bz169fHzJkzkZaWhsTERACAiYkJTE1NZY6YSpMLFy5gzJgxJTrPDh06FDVq1MCMGTOQlJQElUoFpbL4lt3CwgL5+fmoWLGiXCFTKaftIKutorO2tkavXr0QHh6OY8eOAfhPJ7SGDRvCyMgI9+7dk443MDD4wBFTWaE9tzp16oSmTZti2rRpyMnJgY6OjtSVfd68ebC3t8e6deugVqtRpUoV+Pj48J6K/hATU/RfCQ8Pf63Vdbly5dCrVy8EBgbi3LlzcHNzg7e3N8aNG8eWoPROlEol1Go16tSpg4ULF6Jdu3bSPpVKhZycHBgaGsLe3l7GKKksEMVrKQIAJk+eDFtbWwwaNAhpaWnQ1dWVbqRq1KgBfX19GBoayhkulXIZGRmIi4tDVFQU7t69K23ftWsXQkJCULVqVQCQzjmlUomKFStyWgy9UWJiIpo0aQJra2tUr15d2t6mTRt4eHggOzsbkydPxtmzZ6XEVGZmJkxMTJCXlydX2FSKXbt2Dd7e3hg1ahT8/Pzw5MkTVKtWDRMnTsSzZ8+wYsUKREZGSuMtLS1RvXp16ZpF9Ca5ubkAgJycHACAvr4+3N3dcfnyZaxcuRIFBQVQqVQQQsDc3ByVKlXC7du3pd992usX0dtwjSn609LT07Fs2TIMHjy4xHYhBAwMDNCrVy8UFRXB3d0dJiYmOHPmDGrWrClTtFSWFBUVQUdHB/n5+TAxMXltf0BAAG7duoWePXvKEB2VdpcvX8b27dsxf/58qQJPoVCgfv36mDp1KpYtW4ZPP/0UO3fulNYlS01NhZGREfLy8mBgYMD1Wug1Fy9ehLu7OwDg6dOnMDY2xg8//ID69esDALp37y6N1Z4/x44dg7W1NYyNjT98wFSqXbx4Ea1bt8b06dPxr3/9C0BxNUJWVhZMTU3h4eGB8uXLIywsDG3atEHHjh2hVqtx5swZHD9+nEl0ek1SUhJatmwJZ2dn5Ofn49SpUwgPD0dISAj69++PBQsWYP78+fjyyy9x+vRpODo64siRI7h48SK6desmd/hUSl26dAn+/v54+PAhypUrh+HDh+Pzzz/HpEmTkJycjB9//BH5+fmYNWsWdHSKUwsmJiYwMTGR7r94T0Xvgokpem9qtRoqlQpXr16Fnp4eOnfuXGK/9uJTrlw5REVFwdDQEHFxcbCzs5MjXCrFtOfSq9t0dHRw69YtuLi4YPfu3fj4448BAAcOHMD27dtx5MgRHDlyBDY2NjJETaXZzZs30aVLFzx48ADp6enYsGEDlEqllOx0cXGBoaEhli9fjkaNGqFVq1ZQqVT8sUdvdePGDXTr1g2enp6YMGECUlJSsHz5cgQFBWHVqlVQqVQlbryvXr2K0NBQhIaGIjY2ltOuqIQ7d+6gdevW6N69u5SU8vX1RUJCAp48eYK2bdsiMDAQrq6uaN26NX7++WecPn0aFhYW+Pbbb9nog16jVqsxb948fPrpp9i2bRs0Gg00Gg1GjBiBkSNHIi8vD5999hmMjY0RERGBVatWwcrKCnp6ejh27Bhq1aol90egUig5ORnt27eHh4cH2rVrh8ePH2P06NGIi4vD0qVLsWLFCsycORMRERGIiIiAi4sLkpOTERERgV9//ZWVUvRemJii96ZNJHz55ZewtbVFq1at3jju4MGDiI2NRWxsLJNS9Jrr169j//79GDJkCKpUqQKguNpOpVIhNTUV7dq1Q7du3VC3bl0AQGFhIfT09JCfn4+YmBhO46PXZGdnY8mSJWjXrh1cXFzg5eWFoqIihIeHQ0dHR0pOdenSBR06dMCWLVtw/fp1GBkZISQkREqAEr0sLy8PixcvRo8ePRAQEACFQgFra2scO3YMu3btkp4QayUkJGDDhg2IjIxETEwMHBwcZIqcSisDAwPUqFEDRUVFOHjwIObPnw8jIyM4OjqiYsWKWLp0Ka5fv47IyEhYWVnBw8MDHh4ecodNpZhKpUJWVpZ0vdFoNNDR0cHmzZul6pa6deuiZcuWaNy4Mb744gsUFRVBqVSyQzb9rl27dsHBwQHBwcHStk8++QR9+vRBfn4+1q9fjwULFiA6Ohrbt2/HiRMnYGFhgfj4eP72o/emEJxUTO9BCAGFQoHIyEjMmzcP69atkxIET58+xYMHD3Du3DkMGjQIeXl5ePr0KaysrGSOmkqb5ORktGzZEk+ePMH06dMxdepUaQ2W/Px8eHl5QalU4ttvv32t/Dc/Px/lypWTI2wq5Z4/f47Vq1ejbt266NevHyIjI+Hu7o4+ffogPDwcwJur9IjeJj8/H0uWLIG5uTnGjx8vfQ+eO3cOQ4YMwcmTJ1GhQgXpvMrOzsbly5dRvXp1VKtWTeboqbTRXoMyMjLQu3dvXLx4Ec7OzggJCYGlpSUA4MqVK2jRogXmz58Pb29veQOmMmPgwIFISUnBqVOnAAAFBQXQ19cHAPTs2RN3797F+fPnWcVC78zX1xenT59GbGwshBDSrIa4uDh0794dkydPxuLFi6XxGo1GeshM9L54ZaL3ok0S7NixAxYWFvj4448hhMDRo0fh6emJPn36ICQkBFlZWTAwMGBSil6Tk5ODgIAA9O7dGytXrsTChQuxePFiPHr0CEDxFFBfX1+EhIS8cU46k1L0eypUqIAJEyagf//+UCgU6NatG7Zu3Yp9+/Zh2LBhAIqfKr948QIpKSnyBktlRrly5fDZZ59h/PjxJbYrFAoUFhZCoVBIP/QyMjJQvnx5tGzZkkkpeiOVSgW1Wg1LS0tERESgf//+GDlypJSUAoC6deuiXr16JRbYJ/o92k5pPj4+ePbsGfz9/QEUL1Cdn58PAJg1axaePHkidQglehctWrRAfHw8Tp48KX3XqdVqtG/fHqGhoQgKCsLJkyel8Uqlkkkp+tOYmKL3FhsbiyNHjmDx4sXYs2cPPv/8c7i4uKBGjRpYuHAhYmJiUKlSJbnDpFJKqVTC0dERzs7OmDhxInbs2IHAwEAsWrQIDx48AABp+p4WCzvpXWnX8hFCQEdHB5988gm2bNmCiIgIDB8+HADg7e2Nr776il2t6J293LhDu6B+Tk4OCgoKoKenB4VCAT8/Pzg4OCA/P5/XLHorlUqFoqIiWFpaYu3atejSpUuJ/S9evICJiYk0vZjnE71K+/2lreAEgIYNG2LQoEE4evQovvnmGwD/eZinrepk0oD+iLZbMQA4OTmhb9++mD59Oi5cuFCi2q5Lly6wtrbGzZs35QiT/gdxjSl6b7GxsSgoKMDQoUORnp6OkSNH4vDhw2jXrp005uUvSqKXGRgYYPjw4TAyMgJQXHouhIC7uzuEEJg+fTrMzMyg0WiQmpqKmjVr8lyi96Y9Z5RKJXr16oWtW7di+PDhsLa2Rnp6Ok6ePAkDAwOZo6SyQqPRSDfk2rXKjIyMoKOjAz09PcyePRtr167Fzz//zKpOes3L5w/wn3MoLy8PhoaGryWeAgICcPPmTanTI78D6WVXrlyBs7MzgoKC4OrqKk2xKl++PCZOnIjs7GxERETgt99+w8qVK/H06VP88MMP0NXVLVGZR/SyjIwMWFpaSolzHR0dmJubY9iwYVixYgW+/PJLzJ8/H02aNAFQ3HmvYsWKUsUe0X+LiSl6L0VFRUhLS4OdnR3atWuHadOmwdjYGAqFokQyijdR9DbapJRarYZSqcSgQYMghMCQIUOgUCjg7e2NwMBApKamYvPmzeyURq/RrtPy8nVHeyP18roaQPH1yMnJCY6Ojjh79izOnz+PBg0ayBU6lTHac+3BgweoXLmytNi5vr4+TExMMH78eISHhyM+Ph6Ojo4yR0ulifaH3stJqZc7z3bs2BHR0dFSlXB0dDRCQ0OlzrM1atSQK3QqpW7fvo2BAweioKAAo0ePBgC4urpKU6wqV66MGTNmoF69eli6dCmqVasGa2trPHv2DBEREUxM0RtdvXoVDg4OcHZ2RkREBHR0dPDixQvo6enBxcUFeXl52LhxIwYOHIg5c+bA3Nwc0dHRuH37Ntq3by93+PQ/gokpei86OjoIDAyEEEKarqfRaKBQKJiMovemTSxoNBoMHjwYCoUCHh4eiIiIwM2bN3H69Gkmpeg1586dg7e3Nw4dOlQiyan9sefi4oLdu3dL02A0Gg0WL16Mn3/+mUkpei/aG/PU1FTUrVsXgYGBmDJlCgDg0aNHSExMRHJyMk6ePCk9RSYCgMTERDg7O2Pr1q1wcnKStqtUKunHXNeuXVGnTh0AxesvZmdnQ61Ws/MsvVFhYSE2bdoEW1tbLFu2DBEREfD09IRCoUDfvn2hVCpRVFQEMzMzjBo1Cp6enjh06BDMzc1Ro0YNVK9eXe6PQKVQeno6Pv/8czg6OuLy5cvo378/du3aBT09Pek7cODAgahRowa2b9+OMWPGwMbGBjo6Ojhy5AhsbGzk/gj0P4Jd+ei/wil79FfQXoYUCgW6dOmChIQExMTEoGHDhjJHRqVNYmIi2rZti7Fjx2Lp0qUA/nMdSk1NRatWrdCjRw9s3LhRujbl5uZi7dq16N69O3/s0Rtdu3YNa9euxb1799C4cWN0794dTZs2BVBcodCyZUu4urpi1apVJRY6nzZtGvz8/HheUQmJiYlo1aoVpkyZgkWLFpXYl5ubi1GjRsHExASrVq0qcQ9VWFiIoqIiTjOm33XixAncunULn332GdLS0rBw4UJs2bIFYWFh0rQ+7Xci78/pXWzfvh0//vgjpkyZgocPH8LX1xdNmzbFrl27AOC1KvS0tDQYGhpCqVTCxMRErrDpfxATU0RUKqjVavj5+WHFihVISEiAg4OD3CFRKXPhwgW0adMGEyZMKNGeOC8vDwYGBpgyZQqKioqwcuXK1xZ4fXWNFyKtK1euoE2bNmjfvj0qVaqEqKgo1K1bF71794avry/Cw8Nx/fp1zJ8//7Uferm5uazqpBKuXLkCR0dHTJ8+HV9//TWEEEhLS0NGRgYaN24MXV1d3LlzB1WrVuU1if5rKSkpCAwMxObNmxEeHo6+ffuioKAAp0+fRuPGjVG+fHm5Q6RSLjc3F1FRUejduzeKioqwZ88e+Pv7l0hOFRYWQldXlwUJ9LdiYoqISgW1Wo2wsDA4OjqicePGcodDpcz9+/fRpEkTNGrUCJGRkVCr1fDx8cGNGzdw7do1jB07FjVr1sTAgQPlDpXKkMLCQowaNQq6urpYv349gOIKqYCAAJw6dQpDhw7F1KlTZY6SyoqnT5+iZ8+eSEtLw+3btwEAgwYNwpUrV5CcnIxq1aphxowZ6N+/P4yNjWWOlsqylxMEt27dwtKlS7F582aEhoYiPj4e4eHhuHbtGszMzGSOlEqzNz20y8/Px4EDB+Dn51ciOfXdd9+hU6dOr3XOJvqrcI0pIioVVCoVRo4cyScx9Ltat26NtLQ07Nu3D2vWrEFRURFatGgBOzs7bNu2Dba2tmjUqBHq1asnd6hURujq6iI9PR0fffQRgOIfe9bW1vjqq6+wePFifP/997C0tMTQoUNljpTKAmNjY7i6uuLQoUMYPnw4Ll++jCpVqmDu3Lmwt7fHggULEBAQgIoVK8LNzY2VnPTetOeMQqGQqlhq1qwJX19fKBQKDBgwAMbGxjhy5AiTUvSH3nTPXa5cOfTq1QsKhQK+vr5wc3ND9erVERwcjJs3b8oQJf1TsGKKiIjKhPT0dEyfPh07d+5E+/btsWPHDpiamgIA9u7di3HjxiE4OJhVU/RO1Go1NBoNxo4di6ysLGzbtg36+voQQkCpVOL27dsYN24cdHV1sW/fPrnDpVLu5SRTcHAw1q5dC2tra4SGhqJKlSrSOGdnZ+Tk5CAuLk6uUKmMerVD6Kvc3d0RGRmJEydOwM7OToYIqax4dUre7du38dFHH5Xosp6fn499+/bB3d0dJiYm+Pnnn6W1F4n+DnxMQ0REZUKVKlUQEBCAqVOnYsaMGTA1NYVGowEA9O3bF2ZmZjh+/LjMUVJpp1arARRXaerq6mL48OGIiIjAunXroFAooFQqodFoYG1tjTlz5mD//v1ISEiQN2gqtXJycvD8+XNkZ2dL26ZMmYLp06dj0qRJsLKyAgAUFRUBALs30p/y4sULqFQqpKamStUrWhqNBuvWrUNkZCSio6OZlKK3UqvVUlLq6dOnWLVqFTp37oy9e/cC+E8VVbly5RAVFQVDQ0PExcUxKUV/O07lIyKiMqNq1arw9/eXulYplUoIIZCVlQUzMzM4OjrKHCGVZtevX8f+/fsxZMgQqYqlY8eOWLRoEXx8fGBoaIhRo0ZJlS/ly5eHnZ0dFzinN7py5Qp8fHyQmZmJjIwMLF68GIMHD4ZKpYKHhwcKCwulH3k6OsW33Hfv3oW9vT00Gg07p9Frfq9DqJ6eHm7fvo1WrVph1KhRmDRpknSMUqlE48aNcebMGdSuXVvG6Kks0DaHCQwMRHJyMtatW/fGcQcPHkRMTAxiY2OZ7KQPgokpIiIqU15dNFihUGD58uVIT09H586dZYqKSrvk5GS0bt0aT548waNHjzB16lSYm5sDAMaPH4+cnByMGTMGKSkpcHV1RY0aNbBp0ybk5eVxoWp6zZUrV9ChQwcMGzYMzZs3x5kzZzBixAjY29tLDTx0dXWl8fn5+Zg/fz4iIyMRFxfHtaXoNa92CA0KCsLBgwelDqHHjh3DyJEj39ghtEWLFjJFTWWBdnre48ePcf36dYwbNw5WVlaoVasWatWqBXd3d7i6upY4pnPnzoiLi5OqPon+blxjioiIyqwdO3YgJiYGO3fuRHR0NKfJ0Bvl5ORgypQp0Gg0aNasGSZPngxfX1/4+fnBwsICQPF0mK1bt8Lf3x9KpRIVK1bE8+fPsX//fp5XVMLjx4/h7u4OW1tbBAUFSdudnJzQsGFDBAUFlVjD5eDBg1i2bBmuXr3K84neiB1C6e92/PhxrFmzBsnJyahTpw6WLVuG6Oho7N+/HxMnTkT79u2h0Wjg6+sLa2treHt7yx0y/cOwYoqIiMosOzs7bNmyBXFxcbC3t5c7HCqllEolHB0dYWZmhkGDBsHCwgKDBw8GACk5pVQq4eHhgfbt2+P27dvIy8tDgwYNUK1aNZmjp9KmsLAQWVlZcHNzA/Cfhc9r1aqFR48eASjZ7apTp044f/48Vq9eza6h9EbsEEp/p7y8PGzbtg1Vq1aFm5sb+vXrBwDYuHEjqlatirZt2wIA/P39sWLFCpw5c0bOcOkfihVTRERUpr148QJ6enpyh0GlXE5ODoyMjKS/v//+e7i7u+OLL77AtGnTYG5ujqKiIty7dw/W1tYyRkplwY0bN1C3bl0AxYkqXV1dfP3117h16xY2bdokjXv27BkqVqwoV5hUymk77RUUFGD8+PHsEEp/m9zcXOjq6kpTjGfNmoXw8HBcuXIFFSpUgLe3N9auXYv4+HhWdZIsOMGdiIjKNCal6F1ok1JqtRpCCAwaNAjbtm3D0qVLsXjxYty7dw/+/v7w8fFBTk4O+NyO3kablNJoNNIPPbVajYyMDGlMQEAA1q9fL3XkI3rZuXPn0LlzZ+Tk5EBfX58dQulvZWhoKF2rEhMTcf78ecyZMwcVKlSAl5cX1q5dixMnTjApRbLhVD4iIiL6x1CpVBBCQKPRYPDgwVAoFPDw8EBERARu3ryJ06dPl6isInobbWdQbYc9bcerr776CvPnz8f58+eljnxEWomJiejQoQPGjh0LIyMjCCHQsWNHBAQEwMfHB+XKlcOYMWPYIZT+FikpKXj69ClatGiBWbNmYd26dThx4gSaNm0qd2j0D8ZvSiIiIvpH0a7/o62cWrduHRISEnDu3Dk0bNhQ5uiorNEmplQqFT766CMEBgZi8eLFOHPmDBo1aiR3eFTKXLhwAW3btsWECROwePFiAMXXpPz8fPj5+UGj0WD8+PFISUlB//792SGU/nLNmzdHcHAwIiMjsWDBApw5c4ZJKZIdE1NERET0j6NQKKBWq+Hn54djx44hISGBSSn6U7RVLbq6uvjuu+9QsWJF/PLLL/yhR6+5f/8+evTogXbt2mHx4sVQq9Xw8fHB9evXcePGDYwYMQKffPIJbG1tMX78eISFhcHY2FjqEGppaSn3R6D/AVWrVoWxsTFWr16N06dP81pFpQIXPyciIqJ/JLVajbCwMDg6OqJx48Zyh0Nl3JkzZ9CiRQtcunQJdnZ2codDpdD9+/cxYcIEpKWlYdasWVizZg2KiorQokULFBQU4MiRI6hXrx5CQ0Px5MkTpKSkoKCgAHZ2duwQSn85beMGotKAiSkiIiL6x9JOwyL6K7za/ZHoVenp6Zg+fTp27tyJ9u3bY8eOHTA1NQUA7N27F2PGjEFwcDAGDx4sc6RERB8OE1NEREREREQfyL1797B69Wp069YNnTp1gkajkaaE2tvbo3Pnzli1apXMURIRfThcY4qIiIiIiOgDqVq1Kvz9/WFgYADgP90ds7KyYGZmBkdHR5kjJCL6sJiYIiIiIiIi+oBe7bCnUCiwfPlypKeno3PnzjJFRUQkDyamiIiIiIiIZLJjxw7ExMRg586diI6Oho2NjdwhERF9UEq5AyAiIiIiIvqnsrOzw507dxAXF4cmTZrIHQ4R0QfHxc+JiIiIiIhk9OLFC+jp6ckdBhGRLJiYIiIiIiIiIiIiWXAqHxERERERERERyYKJKSIiIiIiIiIikgUTU0REREREREREJAsmpoiIiIiIiIiISBZMTBERERERERERkSyYmCIiIiIiIiIiIlkwMUVERET0PyQsLAyVKlWSOwwiIiKid8LEFBEREdGf4OnpCYVCAYVCAV1dXVhaWqJbt24IDQ2FRqP5IDHY2NhgxYoVJbYNGjQI169f/yD/PhEREdF/i4kpIiIioj/J2dkZ6enpSElJwaFDh9C5c2d4eXnh008/RVFR0Z96TyHEnz4WAAwMDFC5cuU/fTwRERHRh8TEFBEREdGfpK+vDysrK1SrVg1NmzbFjBkzsG/fPhw6dAhhYWFISUmBQqFAQkKCdExWVhYUCgViYmIAADExMVAoFDh8+DCaNWsGfX19xMXF4ebNm+jTpw8sLS1Rvnx5NG/eHFFRUdL7dOrUCampqfDx8ZEqt4A3T+ULCQlB7dq1oaenh3r16mHz5s0l9isUCqxfvx6urq4wNDRE3bp1ERER8bf8nxERERG9jIkpIiIior+Qk5MTGjVqhN27d7/Xcf7+/ggICEBSUhIcHByQnZ2Nnj17IioqCufPn0ePHj3g4uKC27dvAwB2796N6tWrY+7cuUhPT0d6evob33fPnj3w8vLCF198gUuXLmHs2LEYMWIEjh07VmLcnDlzMHDgQFy4cAE9e/bE0KFD8fjx4z/3n0BERET0jpiYIiIiIvqL2draIiUl5b2OmTt3Lrp164batWvDzMwMjRo1wtixY9GwYUPUrVsX8+fPR61ataRKJlNTU6hUKlSoUAFWVlawsrJ64/sGBgbC09MTEyZMwMcff4ypU6eiX79+CAwMLDHO09MT7u7uqFOnDhYsWICcnBycOnXqT31+IiIionfFxBQRERHRX0wIIU2te1fNmjUr8XdOTg78/f1hZ2eHSpUqoXz58rh69apUMfWukpKS0LZt2xLb2rZti6SkpBLbHBwcpNdGRkaoUKECHjx48F7/FhEREdH70pE7ACIiIqL/NUlJSahZsyaUyuJngEIIaV9hYeEbjzEyMirxt5+fHw4fPozAwEDUqVMHBgYGcHNzw4sXL947nleTZG9KnOnq6r52zIfqLkhERET/XKyYIiIiIvoLHT16FBcvXkT//v1hYWEBACXWf3p5IfS3iYuLg6enJ1xdXdGwYUNYWVm9Nj1QT08ParX6re9Tv359/PLLLyW2xcfHo379+u8UBxEREdHfiRVTRERERH9SQUEB7t+/D7VajYyMDERGRiIgIACffvophg0bBpVKhVatWmHhwoWwsbHBw4cPMWvWrHd67zp16mD37t1wcXGBQqHA7NmzX6tgsrGxwfHjxzF48GDo6+vD3Nz8tffx8/PDwIED0bRpU3Tp0gX79+/H7t27S3T4IyIiIpILK6aIiIiI/qTIyEhUqVIFNjY2cHZ2xrFjxxAcHIx9+/ZBpVIBAEJDQ1FYWIhmzZrBy8sL8+fPf6f3Xr58OUxMTNCmTRu4uLigR48eaNq0aYkxc+fORUpKCmrXri1VZ72qb9++CAoKwpIlS2Bvb4+1a9di48aN6NSp03/12YmIiIj+Cgrx8qIHREREREREREREHwgrpoiIiIiIiIiISBZMTBERERERERERkSyYmCIiIiIiIiIiIlkwMUVERERERERERLJgYoqIiIiIiIiIiGTBxBQREREREREREcmCiSkiIiIiIiIiIpIFE1NERERERERERCQLJqaIiIiIiIiIiEgWTEwREREREREREZEsmJgiIiIiIiIiIiJZMDFFRERERERERESy+D++SoLa0+sitwAAAABJRU5ErkJggg==", "text/plain": [ "
" ] }, "metadata": {}, "output_type": "display_data" }, { "name": "stdout", "output_type": "stream", "text": [ "\n", "=== Processing optimal variant ===\n", "Found 248508 records for optimal variant\n" ] }, { "data": { "image/png": "iVBORw0KGgoAAAANSUhEUgAABKYAAAJOCAYAAACN2Q8zAAAAOnRFWHRTb2Z0d2FyZQBNYXRwbG90bGliIHZlcnNpb24zLjEwLjAsIGh0dHBzOi8vbWF0cGxvdGxpYi5vcmcvlHJYcgAAAAlwSFlzAAAPYQAAD2EBqD+naQAAsC1JREFUeJzs3Xd4FNUexvF3U0kPKSSELtXQS1CaNOlNQEBROioSRAQbilIUAVHEK6GoCChdEcR+aSrd0ESIIiBFICGhpUJCsnP/4LK6JLSwYTD5fp5nn+ucOXPmN7Nr4b1nzlgMwzAEAAAAAAAA3GZOZhcAAAAAAACAgolgCgAAAAAAAKYgmAIAAAAAAIApCKYAAAAAAABgCoIpAAAAAAAAmIJgCgAAAAAAAKYgmAIAAAAAAIApCKYAAAAAAABgCoIpAAAAAAAAmIJgCgCAPLRp0yaNGTNG586dy/NzvfHGG1qxYsUN9587d64sFosOHz5sa2vSpImaNGli1+/w4cNq166dAgICZLFYNGzYMEnSzp071bhxY/n5+clisWjq1KlXPce2bdtyrKF9+/YqXbr0Ddf8T2PGjJHFYrFry8jI0KBBg1S0aFE5OzurRo0akqTSpUurb9++uTrP1VgsFo0ZMyZb+7hx4xQeHi6r1eqQ86xZs0be3t46fvz4DR/z3nvvqVy5cnJzc5PFYrktv7/du3drwIABKlu2rDw8POTh4aHy5cvriSeeuOr3X9Bc+Ts8ceKExowZo127dplWEwAAZnMxuwAAAPKzTZs2aezYserbt6/8/f3z9FxvvPGGHnzwQT3wwAO5HmP69OnZ2p555hlt3bpVH330kUJDQ1W0aFFJUv/+/ZWamqrFixercOHCuQ6YcmvgwIFq3bq1XduMGTM0a9Ysvffee6pdu7a8vb0lScuXL5evr2+e13TixAm9+eabmjt3rpycHPP//zVv3lx169bVSy+9pHnz5l23/65duzR06FANHDhQffr0kYuLi3x8fBxSy9XMmjVLQ4YMUcWKFfX000+rcuXKslgs+u2337Ro0SJFRETowIEDKlu2bJ7Wcae78nd44sQJjR07VqVLl7aFqAAAFDQEUwAAwCY8PDxb2549e1S3bt1sgdeePXv02GOPqU2bNrepOnvFixdX8eLFs9Xk4eGhIUOG2LXXrFnzttT07rvvyt/fX126dHHouJGRkerRo4def/11lShR4pp99+7dK0l67LHHVLduXYecPy0tTZ6enjnu27hxowYPHqx27drps88+k5ubm21fs2bNFBkZqU8//VQeHh4OqSUnFy9elMVikYvLnf2ftrfrd3it7wsAgDsNj/IBAJBHxowZo+eee06SVKZMGVksFlksFv3www+2PkuWLFG9evXk5eUlb29vtWrVSjt37rTt37Bhg1xdXfXss8/ajX35EbnZs2dLuvRYWWpqqubNm2c7zz8fyduyZYsaNGigQoUKKSwsTCNHjtTFixez1fzPR/l++OEHWSwWHThwQN9++61t3MvnzszM1IwZM2ztjnD48GFZLBa99dZbmjJlisqUKSNvb2/Vq1dPW7Zsset75aN8FotFH374oc6fP29Xq5Tzo3xJSUl69tlnVaZMGbm5ualYsWIaNmyYUlNTs/V77LHHFBgYKG9vb7Vu3Vp//PFHttozMjI0e/Zs9ezZ02GzpS7r0KGDvL299cEHH1yzX5MmTfToo49Kku655x5ZLBa76/7oo49UvXp1FSpUSAEBAercubN+++03uzH69u0rb29v/frrr2rZsqV8fHzUvHnzq57zjTfekLOzs2bNmmUXSv1Tt27dFBYWZte2cuVK1atXT56envLx8VGLFi20efPma16f9Pfv8pNPPtGIESNUrFgxubu768CBA5Kk1atXq3nz5vL19ZWnp6caNGigNWvW2I1x+bezc+dOdenSRb6+vvLz89Ojjz6qhIQEu75Wq1VvvvmmKlWqJHd3dxUpUkS9e/fWsWPH7Prt3LlT7du3V5EiReTu7q6wsDC1a9fOrt8/f4c//PCDIiIiJEn9+vWz/Wb/+Xjojdyjy9eyY8cOPfjggypcuLDKli2rTz75RBaLJcd7Om7cOLm6uurEiRPXvd8AAOQ1gikAAPLIwIED9dRTT0mSPv/8c23evFmbN29WrVq1JF36A/3DDz+s8PBwLV26VJ988omSk5PVqFEjxcTESJIaNmyo119/XW+//bZWrlwp6dKMmMjISD366KMaMGCAJGnz5s3y8PBQ27Ztbee5/FheTEyMmjdvrnPnzmnu3LmaOXOmdu7cqddff/2a9deqVUubN29WaGioGjRoYBu3TZs2tj/sPvjgg7Z2R4qKitKqVas0depULViwQKmpqWrbtq0SExOveszmzZvVtm1beXh42Gpq165djn3T0tLUuHFjzZs3T0OHDtW3336rF154QXPnzlXHjh1lGIYkyTAMPfDAA7YQZPny5br33ntznCW2detWnT59Wk2bNnXMTfgHNzc31a9fX19//fU1+02fPl2jRo2SJM2ZM0ebN2/WK6+8IkmaMGGCBgwYoMqVK+vzzz/Xu+++q927d6tevXrav3+/3TgZGRnq2LGjmjVrpi+++EJjx47N8XxZWVlat26d6tSpY3vE80YsXLhQnTp1kq+vrxYtWqTZs2fr7NmzatKkiTZs2HBDY4wcOVJHjx7VzJkz9eWXX6pIkSKaP3++WrZsKV9fX82bN09Lly5VQECAWrVqlS2ckqTOnTurXLly+uyzzzRmzBitWLFCrVq1sgttn3zySb3wwgtq0aKFVq5cqddee03fffed6tevr1OnTkmSUlNT1aJFC508edLut1uyZEklJyfnWH+tWrU0Z84cSdKoUaNsv9mBAwfm6h516dJF5cqV06effqqZM2eqR48eCg0NVVRUlF2/zMxMzZo1S507d84WFgIAYAoDAADkmcmTJxuSjEOHDtm1Hz161HBxcTGeeuopu/bk5GQjNDTU6N69u63NarUabdu2Nfz9/Y09e/YY4eHhRqVKlYyUlBS7Y728vIw+ffpkq6FHjx6Gh4eHERcXZ2vLzMw0KlWqlK22xo0bG40bN7Y7vlSpUka7du2yjSvJiIyMvOb1z5kzx5BkREdH57i/Xbt2RqlSpWzbhw4dMiQZVatWNTIzM23tP//8syHJWLRoka1t9OjRxpX/KdOnTx/Dy8sr23lKlSpld28mTJhgODk5Zavrs88+MyQZ33zzjWEYhvHtt98akox3333Xrt/48eMNScbo0aNtbZMmTTIk2d1nR3r55ZcNJyenbN/7lXK652fPnjU8PDyMtm3b2vU9evSo4e7ubvTs2dPW1qdPH0OS8dFHH123pri4OEOS8dBDD2Xbl5mZaVy8eNH2sVqthmEYRlZWlhEWFmZUrVrVyMrKsvVPTk42ihQpYtSvX/+a51y3bp0hybjvvvvs2lNTU42AgACjQ4cOdu1ZWVlG9erVjbp169raLv92nnnmGbu+CxYsMCQZ8+fPNwzDMH777TdDkjF48GC7flu3bjUkGS+99JJhGIaxbds2Q5KxYsWKa9Z+5e8wOjrakGTMmTMnW803eo8uX8urr76a7XyjR4823NzcjJMnT9ralixZYkgyfvzxx2vWCgDA7cKMKQAATPD9998rMzNTvXv3VmZmpu1TqFAhNW7c2O5xP4vFoo8//lg+Pj6qU6eODh06pKVLl8rLy+uGzrVu3To1b95cISEhtjZnZ2f16NHD0ZflMO3atZOzs7Ntu1q1apKkI0eOOGT8r776SlWqVFGNGjXs7n+rVq3sHrdct26dJOmRRx6xO75nz57Zxjxx4oQsFouCgoIcUuOVihQpIqvVqri4uJs+dvPmzTp//ny2xxlLlCihZs2a5TibqGvXrrktVZJUu3Ztubq62j5vv/22JGnfvn06ceKEevXqZffIo7e3t7p27aotW7YoLS3tuuNfWd+mTZt05swZ9enTx+47tVqtat26taKjo7M9pnnl99q9e3e5uLjYvvfL/3vlfatbt67uvvtu230rV66cChcurBdeeEEzZ860zXjMrdzco5y+ryeffFKS7B4BnTZtmqpWrar77rvvlmoEAMBRCKYAADDByZMnJUkRERF2f3h3dXXVkiVLbI8IXRYYGKiOHTvqwoULat26tapWrXrD5zp9+rRCQ0OztefU5miXF6POysrKcX9mZqZcXV2ztQcGBtptu7u7S5LOnz/vkLpOnjyp3bt3Z7v3Pj4+MgzDdv9Pnz4tFxeXbPXkdO/Onz8vV1dXu0DNkQoVKmQ7z806ffq0JOX4uF1YWJht/2Wenp439BbDoKAgeXh45BgYLly4UNHR0bZHUG+0FqvVqrNnz1733Fcef/nvqQcffDDb9zpp0iQZhqEzZ87YHXPl93j5u75c443eNz8/P/3444+qUaOGXnrpJVWuXFlhYWEaPXp0jmu5XU9u7lFOfUNCQtSjRw/NmjVLWVlZ2r17t9avX5/t5QAAAJjpzn51CQAA+dTlWTWfffaZSpUqdd3+q1at0owZM1S3bl0tX75cy5Ytu+EZLYGBgTnOssnNzJubdXmW1vHjx3Pcf/z4cbuZXLfL5UDlo48+uup+6dK9y8zM1OnTp+3CqZzuXVBQkDIyMpSamnrDs9luxuVQJTczsi7XHhsbm23fiRMnso15o4vZOzs7q1mzZvrvf/+r2NhYu3Dk8hseDx8+fFO1ODk5qXDhwtc995U1Xr6G9957T/fee2+Ox1z5W4uLi1OxYsVs21d+1/+s9co3QF5536pWrarFixfLMAzt3r1bc+fO1bhx4+Th4aEXX3zxutfzT7m5R1f7zp5++ml98skn+uKLL/Tdd9/J398/20wxAADMxIwpAADy0NVm+rRq1UouLi46ePCg6tSpk+PnstjYWD366KNq3LixNm3apI4dO2rAgAE6dOhQtnPlNJumadOmWrNmjW1GiXRpBtOSJUsceak5uvfee+Xt7Z3juWJiYrR3717df//9eV7Hldq3b6+DBw8qMDAwx3tfunRpSbItZL5gwQK74xcuXJhtzEqVKkmSDh48mCc1//nnnwoMDMxVkFevXj15eHho/vz5du3Hjh3T2rVrr/nWvesZOXKksrKyNGjQoBuaHVSxYkUVK1ZMCxcutC0yL11aQHzZsmW2t9DdrAYNGsjf318xMTFX/XvqyrcGXvm9Ll26VJmZmbY3UzZr1kySst236Oho/fbbbzneN4vFourVq+udd96Rv7+/duzYcdWar/bPB0feo9q1a6t+/fqaNGmSFixYoL59++ZJcAoAQG4xYwoAgDx0+ZG7d999V3369JGrq6sqVqyo0qVLa9y4cXr55Zf1559/qnXr1ipcuLBOnjypn3/+WV5eXho7dqyysrL08MMPy2KxaOHChXJ2dtbcuXNVo0YN9ejRQxs2bLD9Ybtq1ar64Ycf9OWXX6po0aLy8fFRxYoVNWrUKK1cuVLNmjXTq6++Kk9PT0VFRWVbb+dWffzxx+rfv78++ugj9e7dW5Lk4+OjsWPHasSIEbJarerRo4cKFy6sX3/9VW+88YZKlSqloUOHOrSOGzFs2DAtW7ZM9913n5555hlVq1ZNVqtVR48e1X//+1+NGDFC99xzj1q2bKn77rtPzz//vFJTU1WnTh1t3LhRn3zySbYxL4cZW7Zssa2JdVm5cuUkSQcOHLC1DRgwQPPmzdPBgwdts+ZyuoeXbdmyRY0bN77h2Uz/5O/vr1deeUUvvfSSevfurYcfflinT5/W2LFjVahQIY0ePfqmx7ysQYMGioqK0lNPPaVatWrp8ccfV+XKleXk5KTY2FgtW7ZMkmyPBjo5OenNN9/UI488ovbt2+uJJ55Qenq6Jk+erHPnzmnixIm5qsPb21vvvfee+vTpozNnzujBBx9UkSJFlJCQoF9++UUJCQmaMWOG3TGff/65XFxc1KJFC+3du1evvPKKqlevru7du0u6FBA9/vjjeu+99+Tk5KQ2bdro8OHDeuWVV1SiRAk988wzki6tWTZ9+nQ98MADuuuuu2QYhj7//HOdO3dOLVq0uGrNZcuWlYeHhxYsWKC7775b3t7eCgsLU1hYmEPv0dNPP60ePXrIYrFo8ODBN3lnAQDIY2auvA4AQEEwcuRIIywszHBycjIkGevWrbPtW7FihdG0aVPD19fXcHd3N0qVKmU8+OCDxurVqw3D+PtNbGvWrLEbc9OmTYaLi4vx9NNP29p27dplNGjQwPD09DQk2b1db+PGjca9995ruLu7G6GhocZzzz1nvP/++w59K9/lt8Fd+YYxwzCMpUuXGg0bNjR8fHwMFxcXo2TJksaTTz6Z7Q12l9/KN3ny5BzP98+34N3KW/kMwzBSUlKMUaNGGRUrVjTc3NwMPz8/o2rVqsYzzzxjV9e5c+eM/v37G/7+/oanp6fRokUL4/fff89Wj2EYRqNGjbK9+e7y+f/59sHLtV55/692Dw8cOGBIMpYtW5Zt7Ctd602IH374oVGtWjXb9Xbq1MnYu3dvtrpyuofXs2vXLqNfv35GmTJlDHd3d6NQoUJGuXLljN69e2f7/RrGpd/+PffcYxQqVMjw8vIymjdvbmzcuPG657n8Vr5PP/00x/0//vij0a5dOyMgIMBwdXU1ihUrZrRr186u/+Xfzvbt240OHToY3t7eho+Pj/Hwww/bvcHOMC69IW/SpElGhQoVDFdXVyMoKMh49NFHjb/++svW5/fffzcefvhho2zZsoaHh4fh5+dn1K1b15g7d67dWDn9DhctWmRUqlTJcHV1zfabupF7dPlaEhISrnrP0tPTDXd3d6N169ZX7QMAgFkshvGP+cEAAADItWXLlqlHjx46cuSI3dpFt+qVV17Rxx9/rIMHD9oWlEfujRkzRmPHjlVCQkKevUXxTvLll1+qY8eO+vrrr9W2bVuzywEAwA5rTAEAADhIly5dFBERoQkTJjhszHPnzikqKkpvvPEGoRRuSkxMjL799luNGDFCNWrUUJs2bcwuCQCAbAimAAAAHMRiseiDDz5QWFiYrFarQ8Y8dOiQRo4cqZ49ezpkPBQcgwcPVseOHVW4cGEtWrQoV+uTAQCQ13iUDwAAAAAAAKZgxhQAAAAAAABMQTAFAAAAAAAAUxBMAQAAAAAAwBQF/tUuVqtVJ06ckI+PDwtCAgAAAAAA3CLDMJScnKywsDA5OV17TlSBD6ZOnDihEiVKmF0GAAAAAABAvvLXX3+pePHi1+xT4IMpHx8fSZdulq+vr8nVAAAAAAAA/LslJSWpRIkStszlWgpsMBUVFaWoqChlZWVJknx9fQmmAAAAAAAAHORGlkyyGIZh3IZa7lhJSUny8/NTYmIiwRQAAAAAAMAtupmshbfyAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAUxBMweEmTJigiIgI+fj4qEiRInrggQe0b9++q/Z/4oknZLFYNHXqVLv2Jk2ayGKx2H0eeughuz5//PGHOnXqpKCgIPn6+qpBgwZat26dbf/p06fVunVrhYWFyd3dXSVKlNCQIUOUlJSUYy0HDhyQj4+P/P39c339AAAAAADgxhBMweF+/PFHRUZGasuWLVq1apUyMzPVsmVLpaamZuu7YsUKbd26VWFhYTmO9dhjjyk2Ntb2mTVrlt3+du3aKTMzU2vXrtX27dtVo0YNtW/fXnFxcZIkJycnderUSStXrtQff/yhuXPnavXq1Ro0aFC2c128eFEPP/ywGjVq5IC7AAAAAAAArsfF7AKQ/3z33Xd223PmzFGRIkW0fft23Xfffbb248ePa8iQIfr+++/Vrl27HMfy9PRUaGhojvtOnTqlAwcO6KOPPlK1atUkSRMnTtT06dO1d+9ehYaGqnDhwnryySdtx5QqVUqDBw/W5MmTs403atQoVapUSc2bN9emTZtu+roBAAAA4E6WlWVVctoFJaVeUEZGljKtVmVlWWWYXRhM5WyxyNnZSS7OTvL0cJOvVyF5uLvKYrHclvMTTCHPJSYmSpICAgJsbVarVb169dJzzz2nypUrX/XYBQsWaP78+QoJCVGbNm00evRo+fj4SJICAwN199136+OPP1atWrXk7u6uWbNmKSQkRLVr185xvBMnTujzzz9X48aN7drXrl2rTz/9VLt27dLnn39+q5cMAAAAAHcEwzB0Lvm8Es6mKPV8OiEUrulcynmdSEiUq4uz/Lw9VDTIV64uznl6ToIp5CnDMDR8+HA1bNhQVapUsbVPmjRJLi4uGjp06FWPfeSRR1SmTBmFhoZqz549GjlypH755RetWrVKkmSxWLRq1Sp16tRJPj4+cnJyUkhIiL777rtsa0Q9/PDD+uKLL3T+/Hl16NBBH374oW3f6dOn1bdvX82fP1++vr6OvQEAAAAAYJL0i5k6GntWyWkXbG1uri7y9nSXh7urnJ2c5OzkpNs0MQZ3qCyroSyrVZmZWUo9n6HU8+m6mJmlU+dSdDYpVWHBfgry986zGVQFNpiKiopSVFSUsrKyzC4lXxsyZIh2796tDRs22Nq2b9+ud999Vzt27LjmD/uxxx6z/XWVKlVUvnx51alTRzt27FCtWrVkGIYGDx6sIkWKaP369fLw8NCHH36o9u3bKzo6WkWLFrUd/84772j06NHat2+fXnrpJQ0fPlzTp0+3nadnz552jxkCAAAAwL9Zekam9h+NV0ZmliwWi4L8veXv4yE31wIbA+AGBPpLVquhtAvpij+TrPPpF/XXyXO6mGlV0SDfPAmnLIZhFOiZfElJSfLz81NiYiKzZRzsqaee0ooVK/TTTz+pTJkytvapU6dq+PDhcnL6e+39rKwsOTk5qUSJEjp8+HCO4xmGIXd3d33yySfq0aOH1qxZo5YtW+rs2bN231358uU1YMAAvfjiizmOs2HDBjVq1EgnTpxQ0aJF5e/vr5SUFLvzWK1WOTs76/3331f//v1v8U4AAAAAwO2TlWXVb4dPKuNiptxcXVSqaACBFG6aYRg6fS5VJ89ceqt98SL+KhLgc0PH3kzWwi8TDmcYhp566iktX75cP/zwg10oJUm9evXS/fffb9fWqlUr9erVS/369bvquHv37tXFixdtM6HS0tIkyS7gurxttVqvWZ8kpaenS5I2b95sN3Puiy++0KRJk7Rp0yYVK1bsepcLAAAAAHeU2FOJyriYKVcXZ5UOC8zzNYKQP1ksFgUV9pYs0snTSTqRkJgns+4IpuBwkZGRWrhwob744gv5+PgoLi5OkuTn5ycPDw8FBgYqMDDQ7hhXV1eFhoaqYsWKkqSDBw9qwYIFatu2rYKCghQTE6MRI0aoZs2aatCggSSpXr16Kly4sPr06aNXX31VHh4e+uCDD3To0CHbW/6++eYbnTx5UhEREfL29lZMTIyef/55NWjQQKVLl5Yk3X333Xa1bNu2TU5OTnZrYgEAAADAv0F6RqYSzl56IiQs2J9QCrcs0M9LyakXlHYhQycSElU6LPD6B90Ep+t3AW7OjBkzlJiYqCZNmqho0aK2z5IlS254DDc3N61Zs0atWrVSxYoVNXToULVs2VKrV6+Ws/Olf7AGBQXpu+++U0pKipo1a6Y6depow4YN+uKLL1S9enVJsoVVDRs21N13361hw4apffv2+uqrr/Lk2gEAAADATOdSzsuQ5OXhLm9Pd7PLQT5gsVgUEnjpcbzElAuyOnhFKNaYYo0pAAAAAEA+ceBogpLSLig00FeB/t5ml4N8wjAM7Tt8UllWqyqULHLd0PNmshZmTAEAAAAAkA9kWa1KPn9pLV1mS8GRLBaL7TeVlHrBoWOzxlQ+kpCQoKSkJLPLQB7x9fVVcHCw2WUAAAAAuEOlXciQYRhydXbmLXxwOC8PdyWmnFdKWrpDx+WXmk8kJCTo0X4DdSY5zexSkEcCfDw1f86HhFMAAAAAcpSZeent5K6uzrJYLCZXg/zm8kL6mVlWh45LMJVPJCUl6UxymoLrdZVXQIjZ5cDBUs+cVMLmZUpKSiKYAgAAAJCjLOulwMDZiVV74HjOzpd+V5d/Z45CMJXPeAWEyLdIcbPLQB5IMLsAAAAAAHc0q/XSu82cnMyZLdW4Vbfr9nlxxGC1adn0qvt3/rJXe2L2qdfDXXJdw5MDe+mhbh1v6riVX6/STxu36uChI7pwIV0liofpoQc7qlnj+lc95qeNW/XKuLdUplQJzX1/it2+2Lh4vT9noX7ZHaO0tDQVLx6mHl07qEWzRtes49v/rtPEt6dna+/ZvZOeGPCoXduWn3fog7mLdPTocQUHBahb1w7q3KGVXZ9ziUmaPXextm7bqXOJSQoNCVbHti3U9YG2Nz2rzvn/v6ssZkwBAAAAAIA7zfSp4+22Bw97WV06tdH9TRva2ooVvfYTPrt279WSz1bmOpjKrY8XLlNE7Wrq2K6FPD08tHHLNo194x0lJiapc8fW2fqnp6cratY8BRT2y74vI0PPvvS6LBZpyBN95OvrozU/bNDrk/4jdzc33dfwnuvWM3n8y/Ly8rRtBwcG2O3fE7NPL415U63uv0+Rj/fRnph9+s/02XJ1cVH7Ns1t/V4Z95aOnYjVY317KjQkSNt27NZ7M+cqy2pVj64dbuYW5RmCKQAAAAAAcMsq310hW1tIcFCO7XeaD6Mmyd//75CpTq1qSjh1Wos/W5ljMDV/8XKFFAlS0dAi2vfHn3b79v1xUMeOx+qdSaNVq0YV23gxv+3X2h833lAwVaH8XfL3873q/nkLPlOFcmX0wvDBkqRaNaroZHyCPvp4idq2aionJyfFJ5zW7j2/6YXhg9W2VdP/96uqA38e0bofNxFMAQAAAACAgsNqtWrBkhX66tvVOn3mrIoEB6lzh9bq1qWdJGnOJ0s1d/6nkv5+LLBGtXC9O3msjhw9rrnzl+rXvfuUlJys0JBgtWvVXN26tJOTA9bU+mcodVn5smW05ecd2dqPn4jT0mVfKeqd1/Xp8q+y7c/MzJIkef9jxpMkeXl5yjBuuVRlZFzUzl/26PH+j9i1t2jWSF99u0b7Dx5SxfJllZWVmWMd3l6eSkxMuvVCHIRgCgAAAAAA5LkZH3yiz1Z8rUcf6qJqVe7Wth2/aNqsuUo7f159HnlQ7Vo3V8Kp01q9boPemTRakuTl6SFJOnX6jEoUD9P9zRrJ08NDBw4e1pxPluj8hQvq++jV17a6vGbT1DfHqGb1yjdV7+49v6lUiWLZ2t+bMUct779P5cqWzvG4alUqqXTJ4vpgzkI989Rj8vX11tofN2nf/oMa2PehGzp338eHKzEpSSFFgtW+zf16uFtHOTtfeiveidg4XbyYma220iUvrTd95OhxVSxfVkVDQ1SnVjV9smiZihcvqtAiwdq2c7fWb/pZI4Y+cRN3Im8RTAEAAAAAgDx1LjFJn6/8Vt27dtCAPpfCmYja1ZWadl6Llq5Qty7tVCQ4UMFBgXKyWLI9/le7ZlXVrllVkmQYhqpWqaQL6elavvK7awZTubVhU7S27ditl59/yq5945Zt2hOzT/M/+s9Vj3VxcdHUyWP00uhJerjvEEmSq6uLRj47RLVqVL3meQMDCqtfr+4Kr1ReFotFGzdHa/a8RTp16rSGDRkoSUpOSZUkeXt72R3r7eMtSUpKTrG1vT76OY0d/476PTFCkmSxWDRowKNq3aLxjdyG24JgCgAAAAAA5Knfft+vzMysbG+5a96kob78ZrX2Hzis6lXvvurx6RkZWrB4uVavXa+TCadsj8tJUtr58/L08MjxuDYtm17zLYA5OXzkL014O0pNGtVTy+b32dUwbeZc9evd45rrP6Wnp+vV195WltWq1159Vt5entq4eZsmvT1dPt5euiei5lWPrVunhurWqWHbjqhdXe7ubvr086/V6+GuCgwsbNt3tbfqXW43DEMT35quv47HatQLQxUcFKBdu2P04bxF8vHxUrvWzXM8/nYrsMFUVFSUoqKilJWVdf3OAAAAAAAg1y7P8gko7G/Xfnk7+R+zfHIya/Z8ffXtGvV9pJsqlL9L3t5e2rg5Wh8vXKaMjItXDaZuVnzCaT338njdVbqkXnp+iN2+z5Z/LYvFouZNGtiu5+LFTFkNq5JTUlXI3U2urq76+ru1+m3ffn02f6Zt7apaNaoqLj5BM2fPv2YwlZMm99XX4s++1P4/DyswsLB8/j9T6sp7lvL/7cv7N2/doR/Wb9ZHM95S2btKSZJqVKuslJRUTf/gE7Vp2dQh63PdqgIbTEVGRioyMlJJSUny88u+yBkAAAAAAHAM3/8/Znb2bKKCgwJt7WfOnpMk+fx//9X88NMWdWzbQj17PGBry2lh8luRmJSsZ196TV6ennpjzPNyd3Oz23/0r+M6fiJOnboPyHZs+659Nfypx9SpfUsdPnpMQYEB2RZUL1+2jLZt333zhV2xYnpY0VC5urroyF/H7UKuw0ePSZJKlSxm23Z2ctJdZUraHV+ubGmlLE9VUlJyjou+324FNpgCAAAAAAC3R6WK5eTi4qx1P21ShfJ32drX/rhRHoXcVaF8GUmX1mfKuJiZ7fj0jAy5uPwdYWRlZWnNDxsdVl/a+fN6/uXxOn/+gqLeGZ9jUNaze2e1bmH/WODCJct19NgJvTgiUiWKF5UkhRYJ1qnTZ3T2XKIK/yP4+f2PgwoNCb7p2tb+uEnOTk4q///F1t3cXFWzehWt+2mTundpb+u3Zt1GBQYUVvmyZf5fR5CyrFbtP3hYFcqVsavDw6OQ/K7xOOLtRDAFAAAAAADylL+fr7p2aqsln30pV1dXVa1cSdt3/qovv1mtfr26y6NQIUmXZvtkZWXps+Vfq3J4RXl5eqhkiWKqU7Oavvp2tUqXKi5/P18t//I7Xbx48brn/W7Vj3pzynRNmfSqalS7+lv5Xn3tbe0/eFjPDXtCCadOK+HUadu+8mXLyM3NVaVKFrPNRvp7/HVKOHXG7o1/9zdrpAVLluv5l8erZ4/O8vby1PpNP2vz1u0a/tRjtn6xcfF6qE+k+j7aTf16dZckPfvS66pVo6ruKl1CkrRx8zZ9+e1qPfhAWwUG/L2+VJ9HHtTQZ0frzXdmqkWzRtqz93d99d1qjRj6hO3xvHvvqaXQkGCNef1t9Xm0m4ICA7Rj169a+dV/1ePBDlddo+p2I5gCAAAAAAB5btDAR+Xj7aWvvlujBUuWKyQ4SIMf720366f+vXX0QIdWWrBkuc6eS1L1qnfr3clj9XRkf739n/f17vSPVMjdTa1bNFGj+vdo8tSZ1zynYViVZbVe+TRcNtHbf5EkTXx7erZ9i+dFqWhokRu+ziLBgZo6eYxmz12s/0yfrfPnL6hYsaJ6/plBatuqma3fhQvpkuzX3SpZIkxff7dGCadOy7AaKl68qIYM6quundrYnaNKeEW9MeZ5fTBnof675kcFBwVq6JP91b7N3wuae3p46J1Jo/XB3EX6YM5CJSWnqGhIET3Wv6e6dW53w9eT1yyGcb2vJ3+7vMZUYmKifH3vjGlsuXHw4EE91H+QSrcbLN8ixc0uBw6WFH9Mh7+ersUfzVTZsmXNLgcAAADAHSj+TLKOxZ+Tn7eHiocUvv4BMNXX363RrI8WaOnHM1SokLvZ5VxXxsVM7T8aLyeLRTUqXjt3uJmsxfzl1wEAAAAAAAqYX/fuU7fO7f8VoVRe4lE+AAAAAACA2+zFEYPNLuGOwIwpAAAAAAAAmIJgCgAAAAAAAKYgmAIAAAAAAIApWGMKAAAAAAA4zJxPlmru/E8VFFhYn86fKScn+zkxz496Q1ujd6pe3Vqa+NpIk6q8OVt+3qEP5i7S0aPHFRwUoG5dO6hzh1bXPW7egs/0y68x+n3fAaWmndes9yaqUgX7N63v239Q73+0UH8eOqLklFQV9vdTnVrVNKDPQwoKDMirS7pjMGMKAAAAAAA4lIuLsxKTkrVr91679nOJSdq2Y7c8PAqZVNnN2xOzTy+NeVMVypXRpNdfUuuWTfWf6bP11bdrrnvsl9+sUmZmpurUqnbVPikpaSpVspiGDh6gt94Ypb69umvHrj167uXxysi46MhLuSMxYwoAAAAAADiUq4uLatesptXrNqhWjaq29nU/bVZQYGGFhgSbWN3NmbfgM1UoV0YvDL/0Fr1aNaroZHyCPvp4idq2apptRtg/Lf1khpycnLTzl736ccPWHPvUrllVtWv+fY9qVKusIkGBeval1/XH/j9VpXJFx17QHYZgCgAAAAAAOFzzpg319n/e1zNDBsrV1VWStGbdejVr3EC/7dufrX98wmm9/9EC/bxtl85fuKBKFcppyKA+qlj+70ffvlv1o776dpUOHzkmQ1K5u0pp0IBHdXel8rY+cz5ZqiWfrVTUO+P1zrQP9MeBQwoLDdHgx3urbp0aN3UNGRkXtfOXPXq8/yN27S2aNdJX367R/oOH7Oq70rVCq2vx8/WRJGVmZdrann5utDwKFVKzJg0095OlOnXmrGpVr6KXnhuitPMX9Na7s7Rn7+8KKRKspyMHqFaNKrZjN26O1rwFn+noX8fl7OysYmGh6t+7h+6tWytX9TkSj/IBAAAAAACHa3BvbVmtVm2N3iVJijuZoD0xf+j+pg2z9U1OTtFTI17RgYOHNXRwf732yrMqVMhdzzw/VmfPJdr6xZ2MV8v7G2vsqBF65cWnFRwcqKHPjtZfx07YjZeZlaXX3/yPWrdoqtdffU5+fj569bW3lJiUbOsz55Olatyqm2Lj4q96DSdi43TxYqZKlShm1166ZHFJ0pGjx2/6vlxNVlaWLl68qCNHj2vmh/NVoVwZValcya7P/oOHtOLL7xX5RB8Nf+px/br3d705daZeff1t1buntl579Tn5+/vp1dfeUtr585Kk4yfi9Orrb6t0qRJ67dXnNPqlZ9TkvvpKTkl1WO23ghlTAAAAAADA4dzd3dWwXoRWr1uvhvUjtHrdBpUqUUzlypbO1vfT5V8rJSVVM/8zQYX9/SRJtWpUVc9+T2nxZyv15MBekqS+j3azHWO1WlWnVjXt23dQ3/73Bz3ev6dt38WLmXqi/yO2GUFhRUP0SP+h2hq9Uy2b33fD13A5vPH29rJr9/bxliQlJafc8FjX8/Rzo/Xr3n2SpIoVymrS6y/JxdnZrk9qapomjHvRNqPqz0NHtGTZlxr+1GPq1L6lJCkwsLD6PTFCO3buUcP6Edp/8JAyM7M0LHKAPD09JOmmZ47lJYIpAAAAAACQJ1o0a6RR4yYr7fx5rV63Xvc3a5Rjv+gdv6hG9cry8fFWZlaWJMnJ2UnVqlTS7/sO2vodPnpMH8xZqL0xf9jNpDp23H7GlJOTxW7dpuLFisrV1UUJp07b2vr16q5+vbrf0HVYLJabas+N5595UimpaTp+Ik4LFi/XiJGvadrbr8nLy9PWp1zZ0rZQSpKKFy8qSXbXWqLYpbb4hFOSpLJlSsnZyUnjJr6rDm3vV/Wqd8vbyz5oMxPBFAAAAAAAyBO1a1aVp4eHPl6wTIcO/6X7mzbIsV9iYrJiftuv5m0fyravWNEQSVJa2nk9O/J1+fv7KvKJPgopEiQ3NzdNfmdGtrfXubu52da1uszF2fmm33Ln8/+ZUslXzIxK+f+2j7fjAp6S/39cMLxSedWqUUXdez2pL79ZrYe6dbT1uTJQcnW5FOv8c0bX5eu+fK0liodpwrgXNX/xcr0ydrIsThbVrVNDwyIHKKSI+YvQE0wBAAAAAIA84ezsrCb31dOSZStV+e4KKhoakmM/Xx9vFatTQwP6ZA+mXF0vRRd7f/tDCadOa+K4F+0eB0xJTVNwUGCe1B9WNFSuri468tdx3RNR09Z++OgxSVKpksWudugtCQworKDAAB0/EeeQ8e6JqKl7ImoqNTVNW7ftUtSsuZr49nS9M2m0Q8a/FQRTAAAAAAAgz7Rr3UwJCafVonnOj/FJl2ZWrVq7XqVKFpNHoUI59klPz5Akubj+HWXs2btPcScTVKZUCccW/X9ubq6qWb2K1v20Sd27tLe1r1m3UYEBhVW+bJk8OW/cyQQlJJxW0aI5B3m55eXlqWaN6+u33/drzQ8bHTp2bhFMAQAAAACAPFO+bBmNH/P8Nft079pBq9dt0NPPjlbXB9oqpEiQziUm6bff9yswMEDdu7RX+N3l5eFRSFOnfahHenRWwqkzmjt/qYKDAnJV19z5n+rjBZ9p4dxpCg25+iNtfR55UEOfHa0335mpFs0aac/e3/XVd6s1YugTcnJysvXr2XeIQkKC7WYh7dq9V+cSk3T4yKUZVjt27VHcyXiFhhRRpQplJUlvv/u+/Px8VLFCWXl5euqvYye05LOVCgjwV7vWzXJ1bf+08utV2hOzT/dE1FRggL9i4+K1au161ald7ZbHdoR8EUy5uLioSpUqkqQ6deroww8/NLkiAAAAAABwo/x8fTR96njNnrdYs2YvUFJysvz9/BR+d3k1qn+PJCmgsL/GvjxcMz74RC+NmaQSxcI0fOjjWrR0Ra7OaRiGsqxWGYZxzX5VwivqjTHP64M5C/XfNT8qOChQQ5/sr/Ztmtv1y7JaZbVa7drmfLJUu3bH2LZnzZ4vSWrdorFGPjtEklSpUjl99c1qLf/ye128eFEhwUG6955aevShLnYLnefWXWVKatOWbYqaNU9JyckKKOyv5k0a5PjYpBksxvW+gX+BoKAgnTp1KlfHJiUlyc/PT4mJifL19XVwZbfPwYMH9VD/QSrdbrB8ixQ3uxw4WFL8MR3+eroWfzRTZcuWNbscAAAAAHeg+DPJOhZ/Tn7eHioeUtjscpDPZFzM1P6j8XKyWFSj4rVzh5vJWpyuuRcAAAAAAADII6YHUz/99JM6dOigsLAwWSwWrVixIluf6dOnq0yZMipUqJBq166t9evX2+1PSkpS7dq11bBhQ/3444+3qXIAAAAAAADcCtODqdTUVFWvXl3Tpk3Lcf+SJUs0bNgwvfzyy9q5c6caNWqkNm3a6OjRo7Y+hw8f1vbt2zVz5kz17t1bSUlJt6t8AAAAAAAA5JLpwVSbNm30+uuvq0uXLjnunzJligYMGKCBAwfq7rvv1tSpU1WiRAnNmDHD1icsLEySVKVKFYWHh+uPP/646vnS09OVlJRk9wEAAAAAAMDtZ3owdS0ZGRnavn27WrZsadfesmVLbdq0SZJ09uxZpaenS5KOHTummJgY3XXXXVcdc8KECfLz87N9SpQokXcXAAAAAADAv9ScT5aqcatu6trz8Wxvm5Ok50e9ocatuunFVyY45Hw/rN+sxq26KTYu3tbWuFU3Lf50pUPGvxW//b5fkc+MUosOPfXgI09o7vxPc7wnOVn86Ur16D1YLdr31ONPvaidv+y12x93MkEvvjpRDz7yhFq076kuDz+uV19/W38dO5EXl3LHuaODqVOnTikrK0shISF27SEhIYqLi5Mk/fbbb6pTp46qV6+u9u3b691331VAQMBVxxw5cqQSExNtn7/++itPrwEAAAAAgH8rFxdnJSYla9du+zDlXGKStu3YLQ+PQnl6/ulTx6tFs0Z5eo7rORF7UsNHviZfX29NHDdSPbs/oIVLV+ijj5dc99jFn67UB3MXqnOH1pr0+kgVCwvV86PG6+ChI7Y+589fUGCAv54Y8Kgmv/GyBj/eW38dO6Fhz4/RucT8/5SXi9kF3AiLxWK3bRiGra1+/fr69ddfb3gsd3d3ubu7O7Q+AAAAAADyI1cXF9WuWU2r121QrRpVbe3rftqsoMDCCg0JztPzV767Qp6OfyMWffqFvL08NfblEXJzc1XtmlWVmnZeHy/8TD0e7Cgfb68cj8vIuKhPFi3Tg53b6aFuHSVJ1auGq9+gEZq/6HONfukZSVKZ0iX03LBBdsdWqlBWj/Qfqujtv5gezOW1OzqYCgoKkrOzs2121GXx8fHZZlEBAAAAAADHa960od7+z/t6ZshAubq6SpLWrFuvZo0b6Ld9+7P1j084rfc/WqCft+3S+QsXVKlCOQ0Z1EcVy5e19cnMzNSMDz7R96t/lNVqVeNG96p61fBsYzVu1U1PDuxlC3Y2b92uT5d/rYN/HlHGxYsqVaKY+vXqrnsiatqO+fa/6zTx7en6YNokfTB3kXb/+psCAwurd88H1bpF45u+/q3RO9WoQV25ubna2lo0a6QP5y7Sjp2/qnGje3M8bk/MPqWkpql5k4a2NmdnZzVr3EBLln1pN+nmSr4+3pKkrKwsW9uEt6Zp3x9/avDjvTX9g491/EScKpYvq5efHyIvT09Nee8Dbd22S/5+vnqs78Nq1qSB7dhf9/6u9z9aqIN/HpbVMBQaEqyHHuyo1i2a3PT9cLQ7+lE+Nzc31a5dW6tWrbJrX7VqlerXr39LY0dFRSk8PFwRERG3NA4AAAAAAPlZg3try2q1amv0LkmX1kTaE/OH7m/aMFvf5OQUPTXiFR04eFhDB/fXa688q0KF3PXM82N19lyird/7Hy3Uiq++10PdOmnMy8OVlWXVh3MXXbeW2Lh41b+3jl5+/imNGzVCVSpX1AuvTMi2bpMkvf7mfxRRu7peH/2cyt1VShPfjtLhI38v5/Ptf9epcatuOR572fkLF3Qy/pRKlShu1x4aEqxC7u468tfxqx57eV+pEmF27aVKFlda2nklnDpj1261WpWZmanYuHhNjZqtIsGBaljfPrM4feasZs2er949H9QrLzytuJPxem3ifzR2wlSVKV1S40aNUIVyd+n1N99T3MkESVJqappefGWCvDw99OrIYRo/+nl1aNtCKSmpV639djJ9xlRKSooOHDhg2z506JB27dqlgIAAlSxZUsOHD1evXr1Up04d1atXT++//76OHj2qQYMGXWPU64uMjFRkZKSSkpLk5+d3q5cBAAAAAEC+5O7urob1IrR63Xo1rB+h1es2qFSJYipXtnS2vp8u/1opKama+Z8JKux/6c/atWpUVc9+T2nxZyv15MBeSkpK1oqvvlfP7g/o0Yc6S5Lq1qmhyGdGZQtrrtSlUxvbX1utVtWsUUWHjxzTl9+sUs3qle36du7YRp07tJJ06ZHAzT/v0E8bf1bpUjf+ErTL4Y13Do/r+fh4KSk5+erHJqfIzdU123JClx/9S05OUZHgQFv7G5OnadXa9ZKkYkVDNGXiq/L2sj9vckqq3pvymkqXvBSUnTp9Ru9O/0g9u3dSn0celCRVqlhO6zdu1YZNP+vBzu301/FYpaSm6bH+PVW2TClJUu2aVXWnMD2Y2rZtm5o2bWrbHj58uCSpT58+mjt3rnr06KHTp09r3Lhxio2NVZUqVfTNN9+oVKlSZpUMAAAAAECB0qJZI40aN1lp589r9br1uv8q6x5F7/hFNapXlo+PtzL//xiak7OTqlWppN/3HZQk/Xn4qNLTM9SowT12x97X8B7tidl3zTriE07rw7mLtH3nbp0+c06GYUiSKpa/K1vfiFrVbH/t6emhIsFBSkg4bWtr07Kp2rRsmu24nOT0wJ1hGLLkuOfaB16u+cp9A/r0UNcH2io+/pQ+Xf6Vhr84TtOmvKaQIn+v4xUUWNgWSklSieKXZmPVrvn3tfp4e8nf30/x/7/WYkVD5OXpoXfe+0BdOrVVreqV5e9/50zQMT2YatKkyd9fylUMHjxYgwcPvk0VAQAAAACAf6pds6o8PTz08YJlOnT4L93ftEGO/RITkxXz2341b/tQtn3Fil5aK/r0mXOSpML+vnb7Awr7X7MGq9Wql8ZMUmpqmvr37qFiYaEqVKiQPvp4ieLjT2Xrf+UsJ1cXF2VczLjmOa7k431prafkHB57S0lJk8//14LKibePtzIyLio9I0Pubm5/H5eaZjf2ZUVDQ1Q0NER3VyynuhE11LPvEC1a+oWGDRn495hXzKBycbkU62S7VlcXZWRculYfH2+9PeEVffTJUr0x+T1lZWWpWpW7NXRwf9sMKjOZHkwBAAAAAIA7m7Ozs5rcV09Llq1U5bsrqGhozi8k8/XxVrE6NTSgT/ZgytX1UgQRGOAvSTp7LknBQX8/ynbm7Llr1nD8RJz2Hzik8aOft1t7KT395sKmm1GokLtCigTpyF/H7NrjTiboQnq6SpUodtVjL+87cvS4KpQrY2s/cvSYPD09FBwUcNVjPQoVUskSxXT8RNxV+9yMuyuV1+TxLys9PV07f9mr6R98rFFjJ2vR3GkOGf9W3NGLn+clFj8HAAAAAODGtWvdTPXvqaPuXdtftU/tmlV15OgxlSpZTJUqlLX7XJ6dc1fpknJ3d9P6jVvtjv1pw9achrS5HEC5uP49x+bSQuy/5/aSbsg9ETW1YVO0Ll68aGtb88MGubm5qtY11mqqEl5R3l6eWvfjRltbVlaW1v24SfdG1LzqG/mkSzO0Dh3+S0WL5hwA5pa7u7vurVtLndq3UmxcvNIz8i7Uu1EFdsYUi58DAAAAAHDjypcto/Fjnr9mn+5dO2j1ug16+tnR6vpAW4UUCdK5xCT99vt+BQYGqHuX9vL19VHHdi20cOkKubu7q0K5Mlq9boNOxidcc+ySJYopOChQ789eIGuWVRcuXNCcT5YqKPDqM4+u5btVP+rNKdM1ZdKrqlGt8lX7Pdytk1av26Ax499Rl05tdPTYCX28YJl6dO1gW8hckp55YaxOnkzQwv/PQnJzc1Wvh7vqg7kL5e/np/Llyujr79boRNxJvfrSMNtxcz5ZqtTUNFWpXFH+fr6KO5mgT5d/rczMTHXr3C5X1/ZPm7du19ffr1Wj+nUVUiRIZ86c0+dffKsq4RXtHjE0S4ENpgAAAAAAgGP5+fpo+tTxmj1vsWbNXqCk5GT5+/kp/O7yalT/78XOn+j/iLKyrFr06RcyrFY1alBXA/o8pIlvT7/q2G5urnrt1Wc1ddqHGj3+bRUJDlKvh7tq5y+/at8ff950rYZhVZbVqusse62woiF6e8IrmjZzrl58ZYJ8fb31ULeO6t2zq10/q/XSeP/U48EOMmRo2Rff6OzZRJUpU1KTXnvJbm2nCuXKaOnnX+m/a37S+fMXFBQUoGpV7tZrrzyrMAfMmCoWFioni0Ufzl2ks+cS5efrozq1quvx/j1veWxHsBjXW3k8n7s8YyoxMVG+vr7XP+AOdfDgQT3Uf5BKtxss3yLFr38A/lWS4o/p8NfTtfijmSpbtqzZ5QAAAAC4A8WfSdax+HPy8/ZQ8ZDCZpeDfCbjYqb2H42Xk8WiGhWvnTvcTNZSYNeYAgAAAAAAgLkKbDDF4ucAAAAAAADmKrDBVGRkpGJiYhQdHW12KQAAAAAAAAVSgQ2mAAAAAAAAYC6CKQAAAAAAAJjCxewCAAAAAACAueZ8slRz53+qoMDC+nT+TDk52c9jeX7UG9oavVP16tbSxNdGmlSlNPPD+dq8dbtOJpySxWJRieJh6tG1g5o3aWDrk5Z2XhPfjtK+/X/qzNlz8vAopIrly6p/7x66u2K5HMe1Wq16/KkXtf/AIY0dNVxNGtWz7bt8b640/KnH1Kl9y6vWuvOXvRr2/Jgc95UsHqZPZr8rSYqNi9dDfSKz9QmvVF4z3n3jquPnFwRTAAAAAABALi7OSkxK1q7de1WrRlVb+7nEJG3bsVseHoVMrO6SCxcuqGP7lipZPEyGYeiH9Vs0bsJUWa1WtWjWSJJ0MTNTbu5u6teru4oEByklNVWfLf9az7wwVh9Mm6QSxcOyjbvy61U6ffrMVc/r7u6mdyaNtmsLKxpyzVorlCuj6VPH27WlpZ3X86PG656Imtn6P9avp2pWr2zb9vTwuOb4+QXBFAAAAAAAkKuLi2rXrKbV6zbYBVPrftqsoMDCCg0JNrG6S4YNGWi3XbdODR05ekzfrfrBFkz5+fpo1PND7frVqVVNHbv11w/rt6jXw13s9p1LTNLseYs16LFeenPKjBzP62SxqPLdFW6qVi8vz2zHfPvfdbJaDTVv2jBb/+LFQm/6HPlBgV1jKioqSuHh4YqIiDC7FAAAAAAA7gjNmzbUjxu26uLFi7a2NevWq1njBrJYLHZ9T58+q4lvT9dDfSLVokNP9ez3lN7/aKEyMv4+dv2mn9W4VTdt2rLd1packqoHHxmkV19/2yE1+/p6KzMz65p9PAoVkpurq7Kysvd7/6OFqlm9smpVr+KQeq5l9boNKl6s6FUfKbyWCW9NU9/Hh+vnbbvU94nhatGhp4YMf0WxcSeVlJSsMeOnqE3n3nq47xCt/WGj3bG/7v1dT414VW0791brB3qp7xPD9d2qHxx0VbemwAZTkZGRiomJUXR0tNmlAAAAAABwR2hwb21ZrVZtjd4lSYo7maA9MX/o/hxm+JxLSpKvj7cin+ijyeNf1sPdOun71T9oynsf2Po0ql9XrVs00eSpM3QuMUmS9M57H8hqtWrE0Mdt/Sa8NU2NW3W7oRoNw1BmVpaSU1L1/eoftW37bnXu2CpbP6vVqsysLJ0+fVZR78+TxclJLZvfZ9fnt30HtGbdBj35WO9rnjM9I0Mdu/dXszY91PuxYfrym9U3VOs/nTl7Tjt37cnxXkrSlPc+UNM23dWp+wC9+c5MJSUlZ+tz+sxZzZo9X717PqhXXnhacSfj9drE/2jshKkqU7qkxo0aoQrl7tLrb76nuJMJkqTU1DS9+MoEeXl66NWRwzR+9PPq0LaFUlJSb/oa8gKP8gEAAAAAAEmSu7u7GtaL0Op169WwfoRWr9ugUiWKqVzZ0tn6li1TSoMf/zvQqVK5kgoVcteEt6I0LHKAChVylyQNfbKf+j+5V2+9O0vN7quvNT9s1KTXX5Kfr0+uaty+81eNGPmaJMnZ2VnDIgfYLVZ+2UcfL9Eniz6XJBX299Ok10barQtltVo1ddqH6t61vYqGFlFsXHyO5ysWFqon+j+q8uXKKCMjQ6vXbdBb785SamqaHurW8YbrXvvjJmVZrdmCKTdXV3Vq31J1a9eQt7enYn4/oPmLlmnf/oOa9Z8JcnH5O7pJTknVe1NeU+mSxSVJp06f0bvTP1LP7p3U55EHJUmVKpbT+o1btWHTz3qwczv9dTxWKalpeqx/T5UtU0qSVLtmVd0pCKYAAAAAAIBNi2aNNGrcZKWdP6/V69br/v+v3XQlwzD02fJv9OW3qxQbF2/3CN+JuJO6q3RJSZfWWhr5bKSeeWGstv68U53at9S9Vyz+PfLZIRr57JAbqi+8UnnNem+iUlPTtDV6p6ZGzZazs5PatW5u1++BDq3UsH5dnT5zVl9+s1ovvDJB70x8VRXK3yVJ+uq7NTp95pwe6dH5mue7cpZVvXtq62Jmpj5ZtEwPdm5rFxxdy+q161Wx/F3ZFl8PDCys4U89ZtuuUa2yypQqrhdfnaifNv6sZo3r2/YFBRa2hVKSbGPVrlnN1ubj7SV/fz/FJ5yWJBUrGiIvTw+9894H6tKprWpVryx/f78bqvl2KLCP8gEAAAAAgOxq16wqTw8PfbxgmQ4d/kv3N22QY79Pl3+t6R/MU8N6EXpjzAua+Z8JtsXJ/xlSSVKV8IoKDSmijIsX1aVj61uqz9PTQ5UqlFXtmlU1+PHe6tiuhaJmzcu2flRQYIAqVSirBvfW0RtjnldokSB99PESSVLa+fP6cM4i9e7ZVRczM5Wckqq0tPOSpAsXMpSamnbNGpreV18pqWk6diLuhmo+fiJOv+07cNWQ70r31q0lD49C+mP/n3bt3l5edtuXQzFvb/t2V1cXZWRkSJJ8fLz19oRX5OHhoTcmv6fODz+mp58brYOHjtxQLXmNYAoAAAAAANg4OzuryX31tGTZSlW+u4KKhobk2O+Hnzar/r119Hj/RxRRu7rurlhOHv9/fO9Kcz5ZqrPnElW8WFG9M+1DGYbhsHorlr9LqWnnbWtY5cTJyUnlypbW8f8HSYmJyUpMStbb/3lf7bv2VfuufdX/yWclXVrv6tEBQ686lqSbrn/1ug1ycrLYzX66Lgfeo7srldfk8S/r62VzNWHsizp7LlGjxk522Pi3gkf5AAAAAACAnXatmykh4bRaNL/6DJ/0jAy5XvEY26q167P12xOzT4uWfqFhTw1UxfJ3afCwl7X086/Uo2sHh9T6697f5eXpIT8/36v2yczM1G/7Dqjo/9eYCgjw19Q3x9j1OXP2nMZNmKp+vbqrzj8ejcvJuh83ydvbS8XDQm+oxjU/bFCNapUVFBhwQ/03bd2u8xfSVali2Rvqf6Pc3d11b91aOh57Uu/NmKP0jAy5u7k59Bw3q8AGU1FRUYqKisrxVZEAAAAAABRk5cuW0fgxz1+zT51a1bRsxTf6/ItvVaJ4mFatXW+bkXTZ+QsX9MbkaapTu7o6tm0hSerd80F9OGeR6tauoTKlS0iSJk2Zru9X/ai13y656vkO/nlEM2fPV5P76qloSLDOn7+gjVu26+vv1uqJ/o/IxdlZkrTym1X6fd8B1a5ZTYEB/jp95pxWfr1Kx0/EacTQJyRJ7m5uqlm9st34lxc/L12quKpUrmhrf3zIC2rVoolKFg9TenqGVq1dr582btVTg/rarS/1zAtjdfJkghbOnWY37h8HDunI0eNXDeKmv/+xLE4WhVcsL29vL/2274AWLFmuihXKqmH9ulf/Am7Q5q3b9fX3a9Wofl2FFAnSmTPn9PkX36pKeEXTQympAAdTkZGRioyMVFJSkvz87pxFvwAAAAAA+Dfo88iDOncuybZuU+NG92rok/01cvREW5/psz5WcnKKXnjmSVvbow911pafd+iNye9pxrtvyMXFRVarVVlW6zXPV7iwn7y9vfTxgs905sw5eXl5qmSJMI0f/bwa1o+w9StTqoTWb9iq92bMUUpqqgIK+6tShbKa9Z+JOb5d8HrCioZo6bIvdebsOVksFt1VuqRGvTBULa5YL+pq17Bm3Xq5ubrqvob35jh+qZLFtOLL7/Xl16t0IT1DwUEBateqmfr16m4L225FsbBQOVks+nDuIp09lyg/Xx/VqVVdj/fvectjO4LFcOSDnf9Cl4OpxMRE+fpefdrfne7gwYN6qP8glW43WL5Fil//APyrJMUf0+Gvp2vxRzNVtqxjp3ICAAAAyB/izyTrWPw5+Xl7qHhIYbPLQT6TcTFT+4/Gy8liUY2K184dbiZrYfFzAAAAAAAAmIJgCgAAAAAAAKYgmAIAAAAAIB9wcrJIkqzWAr1iD/JI1v9/V87Ojo2SCKYAAAAAAMgHLgcGWVnXXkQcyI3LvytnJ4IpAAAAAABwhctvcLuYmaUC/p4z5IGLmVmSJBdmTAEAAAAAgCt5FXKVk8Wii1lZyriYaXY5yGdSz6dLkrw93R06boENpqKiohQeHq6IiAizSwEAAAAA4JY5OTnZQoOUtHSTq0F+YhiG7Tfl61XIoWMX2GAqMjJSMTExio6ONrsUAAAAAAAc4nJokJx6weRKkJ+kXchQltUqZycneXm4OXTsAhtMAQAAAACQ3/h5e8gii1IvZBBOwSEMw1D86WRJkr+PhywWi0PHJ5gCAAAAACCfcHdzUXCAtyQp9lSibcFqILdOnUtRWnqGnCwWFQ3ydfj4BFMAAAAAAOQjRYN85e7qoouZWTp8/JTSM1gIHTfPMAwlnElW/JlLs6WKFfGTm6uLw89DMAUAAAAAQD7i7OSk8iWD5e7qoozMLB38K14nTycpPSNThmGYXR7ucFaroeTUC/rz2CnFn70UShUN8lVwYZ88OZ/joy4AAAAAAGAqN1cXlS8ZrKNxZ5WUekGnzqXo1LkUubo4y9vTXR7urnJ2cpKTk5OcHLxmEP49DBmyWg1lWa3KzLQq5Xy60i5k2AJMZycnFSvipyB/7zyrgWAKAAAAAIB8yM3VRWWLBykx5YISzqYo5Xy6LmZm6WxSms6aXRzuaG4uzvLz8VBooK9cXZzz9FwEUwAAAAAA5FMWi0X+Ph7y9/FQltWqlLR0JaVeUMbFLGVlWZWZZZUhHu8ryJwtTnJ2dpKLs5O8PNzk61VI7m4uDn/73tUQTAEAAAAAUAA4OznJz9tDft4eZpcC2LD4OQAAAAAAAExBMAUAAAAAAABTFNhgKioqSuHh4YqIiDC7FAAAAAAAgAKpwAZTkZGRiomJUXR0tNmlAAAAAAAAFEgFNpgCAAAAAACAuQimAAAAAAAAYAqCKQAAAAAAAJiCYAoAAAAAAACmIJgCAAAAAACAKQimAAAAAAAAYAqCKQAAAAAAAJiCYAoAAAAAAACmIJgCAAAAAACAKQimAAAAAAAAYAqCKQAAAAAAAJiCYAoAAAAAAACmIJgCAAAAAACAKQimAAAAAAAAYIoCG0xFRUUpPDxcERERZpcCAAAAAABQIBXYYCoyMlIxMTGKjo42uxQAAAAAAIACqcAGUwAAAAAAADAXwRQAAAAAAABMQTAFAAAAAAAAUxBMAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAUxBMAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAUxBMAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAUxBMAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAUxBMAQAAAAAAwBT5JphKS0tTqVKl9Oyzz5pdCgAAAAAAAG5Avgmmxo8fr3vuucfsMgAAAAAAAHCD8kUwtX//fv3+++9q27at2aUAAAAAAADgBpkeTP3000/q0KGDwsLCZLFYtGLFimx9pk+frjJlyqhQoUKqXbu21q9fb7f/2Wef1YQJE25TxQAAAAAAAHAE04Op1NRUVa9eXdOmTctx/5IlSzRs2DC9/PLL2rlzpxo1aqQ2bdro6NGjkqQvvvhCFSpUUIUKFW5n2QAAAAAAALhFLmYX0KZNG7Vp0+aq+6dMmaIBAwZo4MCBkqSpU6fq+++/14wZMzRhwgRt2bJFixcv1qeffqqUlBRdvHhRvr6+evXVV3McLz09Xenp6bbtpKQkx14QAAAAAAAAbojpM6auJSMjQ9u3b1fLli3t2lu2bKlNmzZJkiZMmKC//vpLhw8f1ltvvaXHHnvsqqHU5f5+fn62T4kSJfL0GgAAAAAAAJCzOzqYOnXqlLKyshQSEmLXHhISori4uFyNOXLkSCUmJto+f/31lyNKBQAAAAAAwE0y/VG+G2GxWOy2DcPI1iZJffv2ve5Y7u7ucnd3d1RpAAAAAAAAyKU7esZUUFCQnJ2ds82Oio+PzzaLCgAAAAAAAP8ud3Qw5ebmptq1a2vVqlV27atWrVL9+vVvaeyoqCiFh4crIiLilsYBAAAAAABA7pj+KF9KSooOHDhg2z506JB27dqlgIAAlSxZUsOHD1evXr1Up04d1atXT++//76OHj2qQYMG3dJ5IyMjFRkZqaSkJPn5+d3qZQAAAAAAAOAmmR5Mbdu2TU2bNrVtDx8+XJLUp08fzZ07Vz169NDp06c1btw4xcbGqkqVKvrmm29UqlQps0oGAAAAAACAA5geTDVp0kSGYVyzz+DBgzV48ODbVBEAAAAAAABuhzt6jSkAAAAAAADkXwU2mGLxcwAAAAAAAHMV2GAqMjJSMTExio6ONrsUAAAAAACAAqnABlMAAAAAAAAwF8EUAAAAAAAATEEwBQAAAAAAAFMQTAEAAAAAAMAUBTaY4q18AAAAAAAA5iqwwRRv5QMAAAAAADBXgQ2mAAAAAAAAYC6CKQAAAAAAAJiCYAoAAAAAAACmIJgCAAAAAACAKQpsMMVb+QAAAAAAAMxVYIMp3soHAAAAAABgrgIbTAEAAAAAAMBcBFMAAAAAAAAwBcEUAAAAAAAATEEwBQAAAAAAAFMQTAEAAAAAAMAUBTaYioqKUnh4uCIiIswuBQAAAAAAoEAqsMFUZGSkYmJiFB0dbXYpAAAAAAAABVKBDaYAAAAAAABgLoIpAAAAAAAAmIJgCgAAAAAAAKYgmAIAAAAAAIApCKYAAAAAAABgCoIpAAAAAAAAmIJgCgAAAAAAAKYosMFUVFSUwsPDFRERYXYpAAAAAAAABVKBDaYiIyMVExOj6Ohos0sBAAAAAAAokApsMAUAAAAAAABzEUwBAAAAAADAFARTAAAAAAAAMAXBFAAAAAAAAExBMAUAAAAAAABTEEwByBcmTJigiIgI+fj4qEiRInrggQe0b9++q/Z/4oknZLFYNHXqVLv2gwcPqnPnzgoODpavr6+6d++ukydP2vUpXbq0LBaL3efFF1/Mi8sCAAAAgHyNYApAvvDjjz8qMjJSW7Zs0apVq5SZmamWLVsqNTU1W98VK1Zo69atCgsLs2tPTU1Vy5YtZbFYtHbtWm3cuFEZGRnq0KGDrFarXd9x48YpNjbW9hk1alSeXh8AAAAA5EcuZhcAAI7w3Xff2W3PmTNHRYoU0fbt23XffffZ2o8fP64hQ4bo+++/V7t27eyO2bhxow4fPqydO3fK19fXNk5AQIDWrl2r+++/39bXx8dHoaGheXhFAAAAAJD/5WrG1KFDhxxdBwA4VGJioiQpICDA1ma1WtWrVy8999xzqly5crZj0tPTZbFY5O7ubmsrVKiQnJyctGHDBru+kyZNUmBgoGrUqKHx48crIyMjj64EAAAAAPKvXAVT5cqVU9OmTTV//nxduHDB0TUBwC0xDEPDhw9Xw4YNVaVKFVv7pEmT5OLioqFDh+Z43L333isvLy+98MILSktLU2pqqp577jlZrVbFxsba+j399NNavHix1q1bpyFDhmjq1KkaPHhwnl8XAAAAAOQ3uQqmfvnlF9WsWVMjRoxQaGionnjiCf3888+Ori1PRUVFKTw8XBEREWaXAsDBhgwZot27d2vRokW2tu3bt+vdd9/V3LlzZbFYcjwuODhYn376qb788kt5e3vLz89PiYmJqlWrlpydnW39nnnmGTVu3FjVqlXTwIEDNXPmTM2ePVunT5/O82sDAAAAgPwkV8FUlSpVNGXKFB0/flxz5sxRXFycGjZsqMqVK2vKlClKSEhwdJ0OFxkZqZiYGEVHR5tdCgAHeuqpp7Ry5UqtW7dOxYsXt7WvX79e8fHxKlmypFxcXOTi4qIjR45oxIgRKl26tK1fy5YtdfDgQcXHx+vUqVP65JNPdPz4cZUpU+aq57z33nslSQcOHMiz6wIAAACA/OiW3srn4uKizp07a+nSpZo0aZIOHjyoZ599VsWLF1fv3r3tHn0BgLxkGIaGDBmizz//XGvXrs0WJPXq1Uu7d+/Wrl27bJ+wsDA999xz+v7777ONFxQUJH9/f61du1bx8fHq2LHjVc+9c+dOSVLRokUde1EAAAAAkM/d0lv5tm3bpo8++kiLFy+Wl5eXnn32WQ0YMEAnTpzQq6++qk6dOv3rHvED8O8UGRmphQsX6osvvpCPj4/i4uIkSX5+fvLw8FBgYKACAwPtjnF1dVVoaKgqVqxoa5szZ47uvvtuBQcHa/PmzXr66af1zDPP2Pps3rxZW7ZsUdOmTeXn56fo6Gg988wz6tixo0qWLHn7LhgAAAAA8oFcBVNTpkzRnDlztG/fPrVt21Yff/yx2rZtKyenSxOwypQpo1mzZqlSpUoOLRYArmbGjBmSpCZNmti1z5kzR3379r3hcfbt26eRI0fqzJkzKl26tF5++WU988wztv3u7u5asmSJxo4dq/T0dJUqVUqPPfaYnn/+eUdcBgAAAAAUKLkKpmbMmKH+/furX79+Cg0NzbFPyZIlNXv27FsqDgBulGEYN33M4cOHs7VNnDhREydOvOoxtWrV0pYtW276XAAAAACA7HIVTO3fv/+6fdzc3NSnT5/cDA8AAAAAAIACIFfB1Jw5c+Tt7a1u3brZtX/66adKS0sjkALyiYSEBCUlJZldBvKIr6+vgoODzS4DAAAAQAGWq2Bq4sSJmjlzZrb2IkWK6PHHHyeYAvKBhIQEPdpvoM4kp5ldCvJIgI+n5s/5kHAKAAAAgGlyFUwdOXIk26vYJalUqVI6evToLRcFwHxJSUk6k5ym4Hpd5RUQYnY5cLDUMyeVsHmZkpKSCKYAAAAAmCZXwVSRIkW0e/dulS5d2q79l19+yfY6dgD/bl4BIfItUtzsMpAHEswuAAAAAECB55Sbgx566CENHTpU69atU1ZWlrKysrR27Vo9/fTTeuihhxxdIwAAAAAAAPKhXM2Yev3113XkyBE1b95cLi6XhrBarerdu7feeOMNhxYIAAAAAACA/ClXwZSbm5uWLFmi1157Tb/88os8PDxUtWpVlSpVytH1AQAAAAAAIJ/KVTB1WYUKFVShQgVH1QIAAAAAAIACJFfBVFZWlubOnas1a9YoPj5eVqvVbv/atWsdUhwAAAAAAADyr1wFU08//bTmzp2rdu3aqUqVKrJYLI6uK89FRUUpKipKWVlZZpcCAAAAAABQIOUqmFq8eLGWLl2qtm3bOrqe2yYyMlKRkZFKSkqSn5+f2eUAAAAAAAAUOE65OcjNzU3lypVzdC0AAAAAAAAoQHIVTI0YMULvvvuuDMNwdD0AAAAAAAAoIHL1KN+GDRu0bt06ffvtt6pcubJcXV3t9n/++ecOKQ4AAAAAAAD5V66CKX9/f3Xu3NnRtQAAAAAAAKAAyVUwNWfOHEfXAQAAAAAAgAImV2tMSVJmZqZWr16tWbNmKTk5WZJ04sQJpaSkOKw4AAAAAAAA5F+5mjF15MgRtW7dWkePHlV6erpatGghHx8fvfnmm7pw4YJmzpzp6DoBAAAAAACQz+RqxtTTTz+tOnXq6OzZs/Lw8LC1d+7cWWvWrHFYcQAAAAAAAMi/cv1Wvo0bN8rNzc2uvVSpUjp+/LhDCgMAAAAAAED+lqsZU1arVVlZWdnajx07Jh8fn1suCgAAAAAAAPlfroKpFi1aaOrUqbZti8WilJQUjR49Wm3btnVUbQAAAAAAAMjHcvUo3zvvvKOmTZsqPDxcFy5cUM+ePbV//34FBQVp0aJFjq4RAAAAAAAA+VCugqmwsDDt2rVLixYt0o4dO2S1WjVgwAA98sgjdouhAwAAAAAAAFeTq2BKkjw8PNS/f3/179/fkfUAAAAAAACggMhVMPXxxx9fc3/v3r1zVQwAAAAAAAAKjlwFU08//bTd9sWLF5WWliY3Nzd5enoSTAEAAAAAAOC6cvVWvrNnz9p9UlJStG/fPjVs2JDFzwEAAAAAAHBDchVM5aR8+fKaOHFittlUAAAAAAAAQE4cFkxJkrOzs06cOOHIIQEAAAAAAJBP5WqNqZUrV9ptG4ah2NhYTZs2TQ0aNHBIYQAAAAAAAMjfchVMPfDAA3bbFotFwcHBatasmd5++21H1HXDkpOT1axZM128eFFZWVkaOnSoHnvssdtaAwAAAAAAAG5eroIpq9Xq6DpyzdPTUz/++KM8PT2VlpamKlWqqEuXLgoMDDS7NAAAAAAAAFyDQ9eYMoOzs7M8PT0lSRcuXFBWVpYMwzC5KgAAAAAAAFxPrmZMDR8+/Ib7Tpky5Zr7f/rpJ02ePFnbt29XbGysli9fnu1RwenTp2vy5MmKjY1V5cqVNXXqVDVq1Mi2/9y5c2rcuLH279+vyZMnKygo6KauBwAAAAAAALdfroKpnTt3aseOHcrMzFTFihUlSX/88YecnZ1Vq1YtWz+LxXLdsVJTU1W9enX169dPXbt2zbZ/yZIlGjZsmKZPn64GDRpo1qxZatOmjWJiYlSyZElJkr+/v3755RedPHlSXbp00YMPPqiQkJDcXBoAAAAAAABuk1wFUx06dJCPj4/mzZunwoULS5LOnj2rfv36qVGjRhoxYsQNj9WmTRu1adPmqvunTJmiAQMGaODAgZKkqVOn6vvvv9eMGTM0YcIEu74hISGqVq2afvrpJ3Xr1i0XVwYAAAAAAIDbJVdrTL399tuaMGGCLZSSpMKFC+v111936Fv5MjIytH37drVs2dKuvWXLltq0aZMk6eTJk0pKSpIkJSUl6aeffrLN4spJenq6kpKS7D4AAAAAAAC4/XIVTCUlJenkyZPZ2uPj45WcnHzLRV126tQpZWVlZXssLyQkRHFxcZKkY8eO6b777lP16tXVsGFDDRkyRNWqVbvqmBMmTJCfn5/tU6JECYfVCwAAAAAAgBuXq0f5OnfurH79+untt9/WvffeK0nasmWLnnvuOXXp0sWhBUrZ16oyDMPWVrt2be3ateuGxxo5cqTd4u1JSUmEUwAAAAAAACbIVTA1c+ZMPfvss3r00Ud18eLFSwO5uGjAgAGaPHmyw4oLCgqSs7OzbXbUZfHx8ble3Nzd3V3u7u6OKA8AAAAAAAC3IFeP8nl6emr69Ok6ffq07Q19Z86c0fTp0+Xl5eWw4tzc3FS7dm2tWrXKrn3VqlWqX7++w84DAAAAAACA2y9XM6Yui42NVWxsrO677z55eHjYPWJ3o1JSUnTgwAHb9qFDh7Rr1y4FBASoZMmSGj58uHr16qU6deqoXr16ev/993X06FENGjToVkpXVFSUoqKilJWVdUvjAAAAAAAAIHdyFUydPn1a3bt317p162SxWLR//37dddddGjhwoPz9/W/qzXzbtm1T06ZNbduX13/q06eP5s6dqx49euj06dMaN26cYmNjVaVKFX3zzTcqVapUbkq3iYyMVGRkpJKSkuTn53dLYwEAAAAAAODm5epRvmeeeUaurq46evSoPD09be09evTQd999d1NjNWnSRIZhZPvMnTvX1mfw4ME6fPiw0tPTtX37dt133325KRsAAAAAAAB3kFzNmPrvf/+r77//XsWLF7drL1++vI4cOeKQwgAAAAAAAJC/5WrGVGpqqt1MqctOnTrFG+8AAAAAAABwQ3IVTN133336+OOPbdsWi0VWq1WTJ0+2Wy/qThYVFaXw8HBFRESYXQoAAAAAAECBlKtH+SZPnqwmTZpo27ZtysjI0PPPP6+9e/fqzJkz2rhxo6NrzBMsfg4AAAAAAGCuXM2YCg8P1+7du1W3bl21aNFCqamp6tKli3bu3KmyZcs6ukYAAAAAAADkQzc9Y+rixYtq2bKlZs2apbFjx+ZFTQAAAAAAACgAbnrGlKurq/bs2SOLxZIX9QAAAAAAAKCAyNWjfL1799bs2bMdXcttxeLnAAAAAAAA5srV4ucZGRn68MMPtWrVKtWpU0deXl52+6dMmeKQ4vISi58DAAAAAACY66aCqT///FOlS5fWnj17VKtWLUnSH3/8YdeHR/wAAAAAAABwI24qmCpfvrxiY2O1bt06SVKPHj30n//8RyEhIXlSHAAAAAAAAPKvm1pjyjAMu+1vv/1WqampDi0IAAAAAAAABUOuFj+/7MqgCgAAAAAAALhRNxVMWSyWbGtI/VvXlOKtfAAAAAAAAOa6qTWmDMNQ37595e7uLkm6cOGCBg0alO2tfJ9//rnjKswjvJUPAAAAAADAXDcVTPXp08du+9FHH3VoMQAAAAAAACg4biqYmjNnTl7VAQAAAAAAgALmlhY/BwAAAAAAAHKLYAoAAAAAAACmIJgCAAAAAACAKQimAAAAAAAAYIoCG0xFRUUpPDxcERERZpcCAAAAAABQIBXYYCoyMlIxMTGKjo42uxQAAAAAAIACqcAGUwAAAAAAADAXwRQAAAAAAABMQTAFAAAAAAAAUxBMAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAUxTYYCoqKkrh4eGKiIgwuxQAAAAAAIACqcAGU5GRkYqJiVF0dLTZpQAAAAAAABRIBTaYAgAAAAAAgLkIpgAAAAAAAGAKgikAAAAAAACYgmAKAAAAAAAApiCYAgAAAAAAgCkIpgAAAAAAAGAKgikAAAAAAACYgmAKAAAAAAAApiCYAgAAAAAAgCkKbDAVFRWl8PBwRUREmF0KAAAAAABAgVRgg6nIyEjFxMQoOjra7FIAAAAAAAAKpAIbTAEAAAAAAMBcBFMAAAAAAAAwBcEUAAAAAAAATEEwBQAAAAAAAFMQTAEAAAAAAMAUBFMAAAAAAAAwBcEUAAAAAAAATEEwBQAAAAAAAFMQTAEAAAAAAMAUBFMAAAAAAAAwBcEUAAAAAAAATEEwBQAAAAAAAFMQTAEAAAAAAMAUBFMAAAAAAAAwBcEUAAAAAAAATFFgg6moqCiFh4crIiLC7FIAAAAAAAAKpAIbTEVGRiomJkbR0dFmlwIAAAAAAFAgFdhgCgAAAAAAAOYimAIAAAAAAIApCKYAAAAAAABgCoIpAAAAAAAAmIJgCgAAAAAAAKYgmAIAAAAAAIApCKYAAAAAAABgCoIpAAAAAAAAmIJgCgAAAAAAAKYgmAIAAAAAAIApCKYAALhBP/30kzp06KCwsDBZLBatWLHCbr9hGBozZozCwsLk4eGhJk2aaO/evXZ94uLi1KtXL4WGhsrLy0u1atXSZ599dhuvAgAAALhzEEwBAHCDUlNTVb16dU2bNi3H/W+++aamTJmiadOmKTo6WqGhoWrRooWSk5NtfXr16qV9+/Zp5cqV+vXXX9WlSxf16NFDO3fuvF2XAQAAANwxCKYAALhBbdq00euvv64uXbpk22cYhqZOnaqXX35ZXbp0UZUqVTRv3jylpaVp4cKFtn6bN2/WU089pbp16+quu+7SqFGj5O/vrx07dtzOSwEAAADuCARTAAA4wKFDhxQXF6eWLVva2tzd3dW4cWNt2rTJ1tawYUMtWbJEZ86ckdVq1eLFi5Wenq4mTZqYUDUAAABgLhezCwAAID+Ii4uTJIWEhNi1h4SE6MiRI7btJUuWqEePHgoMDJSLi4s8PT21fPlylS1b9rbWCwAAANwJCKYAAHAgi8Vit20Yhl3bqFGjdPbsWa1evVpBQUFasWKFunXrpvXr16tq1aq3u1wAAADAVARTAAA4QGhoqKRLM6eKFi1qa4+Pj7fNojp48KCmTZumPXv2qHLlypKk6tWra/369YqKitLMmTNvf+EAAACAiVhjCgAAByhTpoxCQ0O1atUqW1tGRoZ+/PFH1a9fX5KUlpYmSXJysv/Xr7Ozs6xW6+0rFgAAALhDMGMKAIAblJKSogMHDti2Dx06pF27dikgIEAlS5bUsGHD9MYbb6h8+fIqX7683njjDXl6eqpnz56SpEqVKqlcuXJ64okn9NZbbykwMFArVqzQqlWr9NVXX5l1WQAAAIBpCKYAALhB27ZtU9OmTW3bw4cPlyT16dNHc+fO1fPPP6/z589r8ODBOnv2rO655x7997//lY+PjyTJ1dVV33zzjV588UV16NBBKSkpKleunObNm6e2bduack0AAACAmf71wdRff/2lXr16KT4+Xi4uLnrllVfUrVs3s8sCAORDTZo0kWEYV91vsVg0ZswYjRkz5qp9ypcvr2XLluVBdQAAAMC/z78+mHJxcdHUqVNVo0YNxcfHq1atWmrbtq28vLzMLg0AAAAAAADX8K8PpooWLWp7+1GRIkUUEBCgM2fOEEwBwB0qISFBSUlJZpeBPODr66vg4GCzywAAAMC/iOnB1E8//aTJkydr+/btio2N1fLly/XAAw/Y9Zk+fbomT56s2NhYVa5cWVOnTlWjRo2yjbVt2zZZrVaVKFHiNlUPALgZCQkJerTfQJ1JTjO7FOSBAB9PzZ/zIeEUAAAAbpjpwVRqaqqqV6+ufv36qWvXrtn2L1myRMOGDdP06dPVoEEDzZo1S23atFFMTIxKlixp63f69Gn17t1bH3744e0sHwBwE5KSknQmOU3B9brKKyDE7HLgQKlnTiph8zIlJSURTAEAAOCGmR5MtWnTRm3atLnq/ilTpmjAgAEaOHCgJGnq1Kn6/vvvNWPGDE2YMEGSlJ6ers6dO2vkyJGqX7/+Nc+Xnp6u9PR02zaPkwDA7ecVECLfIsXNLgMOlmB2AQAAAPjXcTK7gGvJyMjQ9u3b1bJlS7v2li1batOmTZIkwzDUt29fNWvWTL169brumBMmTJCfn5/tw2N/AAAAAAAA5rijg6lTp04pKytLISH2j3uEhIQoLi5OkrRx40YtWbJEK1asUI0aNVSjRg39+uuvVx1z5MiRSkxMtH3++uuvPL0GAAAAAAAA5Mz0R/luhMVisds2DMPW1rBhQ1mt1hsey93dXe7u7g6tDwAAAAAAADfvjp4xFRQUJGdnZ9vsqMvi4+OzzaICAAAAAADAv8sdHUy5ubmpdu3aWrVqlV37qlWrrrvI+fVERUUpPDxcERERtzQOAAAAAAAAcsf0R/lSUlJ04MAB2/ahQ4e0a9cuBQQEqGTJkho+fLh69eqlOnXqqF69enr//fd19OhRDRo06JbOGxkZqcjISCUlJcnPz+9WLwMAAAAAAAA3yfRgatu2bWratKlte/jw4ZKkPn36aO7cuerRo4dOnz6tcePGKTY2VlWqVNE333yjUqVKmVUyAAAAAAAAHMD0YKpJkyYyDOOafQYPHqzBgwffpooAAAAAAABwO9zRa0wBAAAAAAAg/yqwwRSLnwMAAAAAAJirwAZTkZGRiomJUXR0tNmlAAAAAAAAFEgFNpgCAAAAAACAuQimAAAAAAAAYAqCKQAAAAAAAJiiwAZTLH4OAAAAAABgrgIbTLH4OQAAAAAAgLkKbDAFAAAAAAAAcxFMAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAUxTYYCoqKkrh4eGKiIgwuxQAAAAAAIACqcAGU5GRkYqJiVF0dLTZpQAAAAAAABRIBTaYAgAAAAAAgLkIpgAAAAAAAGAKgikAAIA7yIwZM1StWjX5+vrK19dX9erV07fffmvbf/LkSfXt21dhYWHy9PRU69attX//fhMrBgAAyD2CKQAAgDtI8eLFNXHiRG3btk3btm1Ts2bN1KlTJ+3du1eGYeiBBx7Qn3/+qS+++EI7d+5UqVKldP/99ys1NdXs0gEAAG6ai9kFAAAA4G8dOnSw2x4/frxmzJihLVu2yNXVVVu2bNGePXtUuXJlSdL06dNVpEgRLVq0SAMHDjSjZAAAgFwrsDOmoqKiFB4eroiICLNLAQAAyFFWVpYWL16s1NRU1atXT+np6ZKkQoUK2fo4OzvLzc1NGzZsMKtMAACAXCuwwVRkZKRiYmIUHR1tdikAAAB2fv31V3l7e8vd3V2DBg3S8uXLFR4erkqVKqlUqVIaOXKkzp49q4yMDE2cOFFxcXGKjY01u2wAAICbVmCDKQAAgDtVxYoVtWvXLm3ZskVPPvmk+vTpo5iYGLm6umrZsmX6448/FBAQIE9PT/3www9q06aNnJ2dzS4bAADgprHGFAAAwB3Gzc1N5cqVkyTVqVNH0dHRevfddzVr1izVrl1bu3btUmJiojIyMhQcHKx77rlHderUMblqAACAm8eMKQAAgDucYRi29aUu8/PzU3BwsPbv369t27apU6dOJlUHAACQe8yYAgAAuIO89NJLatOmjUqUKKHk5GQtXrxYP/zwg7777jtJ0qeffqrg4GCVLFlSv/76q55++mk98MADatmypcmVAwAA3DyCKQAAgDvIyZMn1atXL8XGxsrPz0/VqlXTd999pxYtWkiSYmNjNXz4cJ08eVJFixZV79699corr5hcNQAAQO4QTAEAANxBZs+efc39Q4cO1dChQ29TNQAAAHmLNaYAAAAAAABgigI7YyoqKkpRUVHKysoyuxQAAHALEhISlJSUZHYZyAO+vr4KDg42uwwAAJCHCmwwFRkZqcjISCUlJcnPz8/scgAAQC4kJCTo0X4DdSY5zexSkAcCfDw1f86HhFMAAORjBTaYAgAA/35JSUk6k5ym4Hpd5RUQYnY5cKDUMyeVsHmZkpKSCKYAAMjHCKYAAMC/nldAiHyLFDe7DDhYgtkFAACAPMfi5wAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAUxBMAQAAAAAAwBQEUwAAAAAAADAFwRQAAAAAAABMQTAFAAAAAAAAUxBMAQAAAAAAwBQFNpiKiopSeHi4IiIizC4FAAAAAACgQCqwwVRkZKRiYmIUHR1tdikAAAAAAAAFUoENpgAAAAAAAGAugikAAAAAAACYgmAKAAAAAAAApiCYAgAAAAAAgCkIpgAAAAAAAGAKgikAAAAAAACYgmAKAAAAAAAApiCYAgAAAAAAgCkIpgAAAAAAAGAKgikAAAAAAACYgmAKAAAAAAAApiCYAgAAAAAAgCkIpgAAAAAAAGAKgikAAAAAAACYosAGU1FRUQoPD1dERITZpQAAAAAAABRIBTaYioyMVExMjKKjo80uBQAAAAAAoEAqsMEUAAAAAAAAzEUwBQAAAAAAAFMQTAEAAAAAAMAUBFMAAAAAAMA0P/30kzp06KCwsDBZLBatWLHCbv+YMWNUqVIleXl5qXDhwrr//vu1detWc4qFwxFMAQAAAAAA06Smpqp69eqaNm1ajvsrVKigadOm6ddff9WGDRtUunRptWzZUgkJCbe5UuQFF7MLAAAAAAAABVebNm3Upk2bq+7v2bOn3faUKVM0e/Zs7d69W82bN8/r8pDHmDEFAAAAAAD+FTIyMvT+++/Lz89P1atXN7scOAAzpgAAAAAAwB3tq6++0kMPPaS0tDQVLVpUq1atUlBQkNllwQGYMQUAAAAAAO5oTZs21a5du7Rp0ya1bt1a3bt3V3x8vNllwQEIpgAAAAAAwB3Ny8tL5cqV07333qvZs2fLxcVFs2fPNrssOADBFAAAAJCPXe817J9//rlatWqloKAgWSwW7dq1y5Q6AeBmGIah9PR0s8uAAxBMAQAAAPnY9V7DnpqaqgYNGmjixIm3uTIAuCQlJUW7du2yBeOHDh3Srl27dPToUaWmpuqll17Sli1bdOTIEe3YsUMDBw7UsWPH1K1bN3MLh0Ow+DkAAACQj13vNey9evWSJB0+fPg2VQQA9rZt26amTZvatocPHy5J6tOnj2bOnKnff/9d8+bN06lTpxQYGKiIiAitX79elStXNqtkOBDBFAAAAAAAME2TJk1kGMZV93/++ee3sRrcbjzKBwAAAAAAAFMwYwoAAAAAgH+RhIQEJSUlmV0G8oCvr6+Cg4PNLuO2IpgCAAAAAOBfIiEhQY/2G6gzyWlml4I8EODjqflzPixQ4RTBFAAAAAAA/xJJSUk6k5ym4Hpd5RUQYnY5cKDUMyeVsHmZkpKSCKYAAAAA5A8pKSk6cOCAbfvya9gDAgJUsmRJnTlzRkePHtWJEyckSfv27ZMkhYaGKjQ01JSaAVyfV0CIfIsUN7sMOFiC2QWYgMXPAQAAgHxs27ZtqlmzpmrWrCnp0mvYa9asqVdffVWStHLlStWsWVPt2rWTJD300EOqWbOmZs6caVrNAICCI1/MmOrcubN++OEHNW/eXJ999pnZ5QAAAAB3jOu9hr1v377q27fv7SsIAIB/yBczpoYOHaqPP/7Y7DIAAAAAAABwE/LFjKmmTZvqhx9+MLsMAAAA5AO8hj3/KoivYb8dMjMzNWbMGC1YsEBxcXEqWrSo+vbtq1GjRsnJKV/MhQCQh0wPpn766SdNnjxZ27dvV2xsrJYvX64HHnjArs/06dM1efJkxcbGqnLlypo6daoaNWpkTsEAAADIt3gNe/5WEF/DfjtMmjRJM2fO1Lx581S5cmVt27ZN/fr1k5+fn55++mmzywNwhzM9mEpNTVX16tXVr18/de3aNdv+JUuWaNiwYZo+fboaNGigWbNmqU2bNoqJiVHJkiVNqBgAAAD5Fa9hz78K6mvYb4fNmzerU6dOtgX0S5curUWLFmnbtm0mVwbg38D0YKpNmzZq06bNVfdPmTJFAwYM0MCBAyVJU6dO1ffff68ZM2ZowoQJN32+9PR0paen27aZpg0AAIAr8Rr2/Kkgvob9dmjYsKFmzpypP/74QxUqVNAvv/yiDRs2aOrUqWaXBuBfwPRg6loyMjK0fft2vfjii3btLVu21KZNm3I15oQJEzR27FhHlAcAAAAABd4LL7ygxMREVapUSc7OzsrKytL48eP18MMPm10agH+BO3olulOnTikrK0shIfbTqENCQhQXF2fbbtWqlbp166ZvvvlGxYsXV3R09FXHHDlypBITE22fv/76K8/qBwAAAID8bsmSJZo/f74WLlyoHTt2aN68eXrrrbc0b948s0sD8C9wR8+YusxisdhtG4Zh1/b999/f8Fju7u5yd3d3WG0AAAAAUJA999xzevHFF/XQQw9JkqpWraojR45owoQJ6tOnj8nVAbjT3dEzpoKCguTs7Gw3O0qS4uPjs82iAgAAAADcfmlpaXJysv+jpbOzs6xWq0kVAfg3uaODKTc3N9WuXVurVq2ya1+1apXq169vUlUAAAAAgMs6dOig8ePH6+uvv9bhw4e1fPlyTZkyRZ07dza7NAD/AqY/ypeSkqIDBw7Ytg8dOqRdu3YpICBAJUuW1PDhw9WrVy/VqVNH9erV0/vvv6+jR49q0KBBt3TeqKgoRUVFKSsr61YvAQAAAAAKrPfee0+vvPKKBg8erPj4eIWFhemJJ57Qq6++anZpAP4FTA+mtm3bpqZNm9q2hw8fLknq06eP5s6dqx49euj06dMaN26cYmNjVaVKFX3zzTcqVarULZ03MjJSkZGRSkpKkp+f3y2NBQAAAAAFlY+Pj6ZOnaqpU6eaXQqAfyHTg6kmTZrIMIxr9hk8eLAGDx58myoCAAAAAADA7WB6MAUAAAAA+VlCQoKSkpLMLgN5wNfXV8HBwWaXAfyrFdhgijWmAAAAAOS1hIQEPdpvoM4kp5ldCvJAgI+n5s/5kHAKuAUFNphijSkAAAAAeS0pKUlnktMUXK+rvAJCzC4HDpR65qQSNi9TUlISwRRwCwpsMAUAAAAAt4tXQIh8ixQ3uww4WILZBQD5gNP/2rvzuBrT/3/gr/uc9pBUypZsg+yy77uGibLHRIydUZmymxnLV5bGEibMILsxYynGhCLTaGxDWUNGi2Qv2tU51+8Pv3N/hDHMGPeJ1/Ovuu/rHK9mrsd97vO+r0XpAERERERERERE9GFiYYqIiIiIiIiIiBTBwhQRERERERERESnigy1MrVy5Eo6OjmjcuLHSUYiIiIiIiIiIPkgfbGFq3LhxuHTpEk6dOqV0FCIiIiIiIiKiD9IHW5giIiIiIiIiIiJlsTBFRERERERERESKYGGKiIiIiIiIiIgUwcIUEREREREREREp4oMtTHFXPiIiIiIiIiIiZX2whSnuykdEREREREREpKwPtjBFRERERERERETKYmGKiIiIiIiIiIgUwcIUEREREREREREpgoUpIiIiIiIiIiJSBAtTRERERERERESkCBamiIiIiIiIiIhIEQZKB1DKypUrsXLlShQUFAAAHj9+rHCifycjIwOaggLk52bjSU6m0nHoLcvPzYamoAAZGRnvrK+yT73flOhTAPvV+4x9it429il629in6G1jn6K3Tak+9V/Q5RdC/G1bSbxOq/fYzZs3UaFCBaVjEBERERERERG9V5KTk1G+fPlXtvngC1NarRa3bt1C8eLFIUmS0nHoNT1+/BgVKlRAcnIySpQooXQceg+wT9Hbxj5Fbxv7FL1t7FP0X2C/oreNfapoEkIgIyMDZcuWhUr16lWkPtipfDoqlepvq3ekv0qUKMGLE71V7FP0trFP0dvGPkVvG/sU/RfYr+htY58qeiwsLF6rHRc/JyIiIiIiIiIiRbAwRUREREREREREimBhiookY2NjfPXVVzA2NlY6Cr0n2KfobWOforeNfYreNvYp+i+wX9Hbxj71/vvgFz8nIiIiIiIiIiJlcMQUEREREREREREpgoUpIiIiIiIiIiJSBAtTRERERERERESkCBamiIiIiIiIiIhIESxMERERERERERGRIliYIiIiIiIiIiIiRbAwRURERET0HhFCAAC0Wm2h34mIiPQRC1OkN3Q3Tenp6coGofeGrk+dOHECv//+O/Lz8xVOREWdrk/xSx69Tbr+dPfuXYWT0PtACAFJkhAREYHJkycjOzsbkiQpHYuKMN016uLFi4iPj1c4Db2veG/1YWNhivSC7ibq559/hpubG06ePKl0JCridH1q9+7d+OSTT7B37148fPhQ6VhUhOn61MGDBzFlyhRkZmYqHYneA89+/rm6umLv3r1KR6IiTpIk7Ny5E/369UN+fj7i4uLkc/ziR2/q2fup3r17Y8OGDUhLS1M6FhVxumvR8ePH8cMPPwAAC+gfOBamSC9IkoRdu3bB3d0dbdu2hYGBgdKRqIiTJAmHDh2Ch4cHFi5ciKlTp8LW1lbpWFSE6b7sDRgwANnZ2UhISFA6Er0HdJ9//fv3R69evVC2bFmlI1ERd/r0aYwYMQLz58/H0qVL0bBhQwBAbm4uv/jRG5MkCfv27cPAgQPh7e0NLy8vWFpaKh2LijBdsXPnzp1wc3PDqVOncOXKlULn6cMjCf6fJz3w559/omPHjvD19cW4cePk4xcvXoSDgwPMzc0VTEdFkRACXl5eyMvLw+rVq5GdnY24uDhs3LgRZcuWRcuWLdGyZUulY1IRcvr0aXTp0gUBAQEYNmyYfDw3NxcmJiYKJqOiLCkpCV27dsX48eMxbtw4+Yb8999/R4MGDWBqaqpwQipqvvvuO/z44484ePAg0tLSEBERgc2bN+PKlSuYOHEiPvvsM6hUfDZNr+fx48cYMGAA2rRpgylTpiArKwt3795FSEgIHBwc8Mknn/CBMr2xw4cPo0ePHliyZAlGjBihdBzSA7yKkF64f/8+TExMMGTIEKSnp2PTpk3YtWsXjh07BldXV8yZMwfVq1dXOiYVIVqtFklJScjIyEBsbCyWLFmClJQU3L17FyqVCjExMahXrx7Mzc35BJleS1xcHBo1aoRhw4YhLS0Nhw4dwubNm5GYmIhhw4bhs88+Q7FixZSOSUVMWloasrOz4ebmhry8PKxYsQJ79uzB77//jsaNG2P79u2oWLGi0jGpCLG2tkZ4eDgWL16MvXv3olixYihdujScnZ0xatQodOjQAVWqVFE6JhURxYsXR0ZGBlJSUpCRkYEZM2bg7NmzSElJQWJiIhYsWIAvvvhC6ZhURAghIITAnj17MGjQIIwYMQLp6em4cOECtm/fjuzsbEybNg1Vq1aVR1bRh4GPS0gvVKlSBSkpKXBzc0PTpk1x+PBhtG3bFgcPHkRISAhOnDihdETSc88P/lSr1fjyyy9x4cIFdOrUCdnZ2RgzZgxiY2MxZswYXL16FSqVih949ErP9isTExOEh4dj5cqV6NmzJzZt2gQ7Ozu0atUKs2bNQkpKioJJqaiqUqUKSpUqhS5duqBWrVqIiopCly5dkJiYiPPnz+PHH39UOiLpMd016tk177p164aZM2ciKCgINWrUwIwZM7B27VrMmzcPDRo0wOPHj5WKS0WQRqNBz549ceDAAVhbWyMpKQnDhg3D9evXMWHCBBw4cICby9BrkyQJKpUKJiYmOHz4MI4dO4bRo0djzpw5uHTpEv744w/07dtXbksfDo6YondOV/1OTk6GmZkZAMDKygqHDx/G8uXL0a5dO3z66acoX7481Go12rVrx7nG9Eq6PhUZGYnw8HDY2tqiffv2aNiwIWJjY5GamooGDRrI/ejatWuwsbGRt9Emep6uT2VlZaFYsWLQarXo06cPpk6dipUrV6Jdu3YYOnQoGjdujCdPnuC3337jYrD0t3T9KiEhARqNBjY2NihRogQ2b96MjRs3wtraGoMGDULp0qVhYGCADh06cC0XeiXd+j+BgYEwMDBAnz590Lt3b8yaNQteXl4oVaqU3Hb27NnIyspCuXLlFExM+kx3jTpz5gzOnz8PR0dHNGjQAOPHj4ezszP+/PNP9OjRQ27/8OFDODg4cGoovZKuX2m1WrmvuLi44OLFi+jUqRPc3Nzg5eWFbt264fDhw/D19cW9e/dgY2OjcHJ6l7jGFCli165d8PPzg1arRZMmTTBixAh06tSpUBshBGbOnIm1a9ciOjoalSpVUigtFQX79+9Hv379ULduXTx69AgFBQX47rvv0KZNG7nNiRMnsGfPHnz77bf49ddfUa9ePQUTk77bt28fFi1ahJIlS6JVq1b4/PPPYWJigvv378Pa2lpuN23aNOzatQtHjx7lAvv0t3bu3AlfX188fvwYbdq0waBBg9CnT59CbXJzc+Hv749Vq1YhOjqa067oL508eRKdOnXCuHHj8Mcff+DRo0eoW7cu5syZAzs7OwBAeHg4fvjhB+zevRvh4eGoX7++sqFJr4WEhGDgwIGwt7dHYmIiRo8ejc8++wy1atWS29y4cQOrV6/GmjVrEBUVVegc0bN0RanDhw9j3759sLS0hLu7uzxV79KlS4X6j7e3N2JiYrBv3z4uj/CBYXmb3rmEhAT4+vrCz88P3t7eEEJg4sSJ2LNnj9wmNDQU/fv3x/r167F//34WpehvnTx5EsuWLUN0dDSCg4PRpEkT9OrVC7/99huAp6OkAgMDceDAAURFRbEoRa906tQpDBo0CM2bNwfwtJju4eGB7OxsWFtbQwiBn3/+GSNGjMCaNWuwbds2FqXobyUnJ+Orr77CtGnTsGrVKkiShKVLl2LVqlVym/3798PT0xNr165FWFgYi1L0gmefKd+5cwcTJkyAv78/Dh48CHd3d1y+fBnTp0/H3bt3kZOTgwsXLuDevXs4evQoi1L0l7RaLfLy8rBlyxYsW7YMFy5cwNKlSxEZGYnFixfj3LlzAJ4WOufMmYPdu3fj8OHDLErRK0mShPDwcHz88cdISEhAQEAAhg8fjk2bNkGSJLn/nDlzBl5eXtiwYQOWLVvGotQHiIUpeieevYkSQqBDhw4YPXo0vLy8MGXKFDg5OWH69OkIDQ0FAJQsWRL29vY4fPgwGjRooFRs0mO6PpWQkIDExERcvHhRHvLbuHFjTJ8+Hc7OznB1dUV0dDSqVauGL7/8Ej///DPq1q2rZHTSU89epx48eAAfHx/Mnz8fP/74I0aOHImkpCQMHjwY2dnZEEIgMTERd+7cwdGjR3mdopfSLfKqY2hoiHr16mHw4MHo27cvFixYgI8++ggbN27E6tWrAQClSpWCo6MjP//opXSjD06cOIEdO3bg999/h5GRkXze29sbffr0QVxcHGbOnIns7Gx4e3tj06ZNLCDQS+muUWlpaVCpVLCxsUGrVq2gVqsxcuRI+Pj4ICYmBsuWLcO1a9fQokUL9OnTh6Pv6LUdO3YMCxYswK5duxAXF4eSJUvi+++/R3BwMADIu2afPHkSR48e5cPjDxSn8tF/TncTdfDgQezduxfA02KC7mfgaZU8MDAQZ8+exddffw03Nzfk5+fD0NBQqdhUBOzatQsjRoxAuXLlkJiYiKVLl2Lo0KHy+bi4OPj7+2PTpk04duyYPPqF6Hm669Tvv/+O5ORkHDt2DKamppg/fz4AIC8vD1u3bsWqVatQuXJlrFu3DqampsjIyEDx4sUVTk/6StevDhw4gI0bN8LY2Bipqan45Zdf5DbXrl3DvHnzEB8fj4EDB2LMmDHQaDRQq9UKJid9tnPnTgwZMgSlSpXCgwcPULFiRURHR6NkyZJym+XLlyMoKAidOnXC0qVLuQYQvdKuXbvw1VdfISMjAxqNBlu2bCm0FMKmTZuwYsUK2NvbY968eahWrZqCaUnf6T77rl69CkmSsH79ejRv3hwuLi4AgJSUFHz++ed48OABRo0ahYEDB+LPP/9E8eLFua7Uh0wQ/Ue0Wq388/79+4WxsbFo3769qF27tpAkSezcubNQ+zNnzohevXqJpk2bioyMjEKvJ9LR9YvExERRpUoVERQUJLZs2SI+/fRTYWxsLCIiIgq1v3Dhghg5cqS4cuWKEnGpCNm5c6cwNTUV9vb2wsbGRtSuXbvQdSgvL09s2LBBVK1aVQwePFjBpFSURERECJVKJXr37i1q1aolDAwMxLx58wq1uXbtmujTp4/o3LmzSEtLUyYo6TXdtSgjI0OMHTtWrF+/Xjx8+FCsXbtWNG7cWHTr1k3cv3+/0GuCgoLEjRs3FEhLRYGuT127dk2UKlVKzJs3T0yePFnUqlVLtGvXTpw4caJQ+++++060bdtW3Lp1S4m4VMTs2LFD2NjYCEtLS6FWq8WECRMKnU9JSRF9+/YVtWvXFtu3b1coJekTjpii/9y9e/cQEhKCgoICjB49GpcvX0ZgYCC2bt2K4OBguLm5yW1jY2NhY2ODsmXLKpiY9F14eDguX74srxsFPJ16NWXKFGzevBk///wzOnToILfn6Dv6K+L/P9XLzc3F2LFj0bZtW3Tr1g1Hjx7F9OnTYWdnh8OHD8ujV548eYKffvoJzZs359p39LeuX7+Os2fP4vbt2xg/fjwSEhKwatUqhIaGYujQofDz8yvU1szMDGXKlFEwMemz48ePw9PTE/b29li2bBlq1qwJIQS2b9+OlStXyjs8PrsTH9GrnDhxApGRkXj06BHmzZsH4Oni50FBQVCr1fj666/RuHFjuf3jx49RokQJpeKSntPdU927dw+urq4YPHgwatSogbVr1yI2NhYeHh7w9fWV29+8eRNTp07FnDlz4ODgoFxw0gsc10v/qatXr8LW1hb/93//BwsLCwBAzZo1MWnSJHh4eMDT0xMhISFy+3r16rEoRS/Izs4u9Pu+ffvg5eWFqKgopKenAwCsrKwwf/58DBo0CK6urjhw4IDcnkUp+iuSJCEqKgqNGjXCvXv30KhRI9jY2MDV1RWBgYF4+PAhOnToAK1WCwAwMjLCwIEDWZSiv5WYmIjGjRtj1KhRMDMzAwA4ODhgzJgx6NmzJ9auXYvFixfL7atUqcKiFP0lIQSysrJQsmRJREdHw9TUFMDTa1j//v0xfvx4ZGdnw8XFBQ8fPlQ4Lekz3ZiE+/fvIyAgAHPmzMHNmzfl8z179sTo0aORn5+PuXPnIjo6Wj7HohS9im5JBB8fH1SpUgWDBg1C27ZtsWDBArRu3Ro//fQTFi1aJLcvX748goODWZQiACxM0X9Ao9HIP9vZ2WHatGm4desWkpOT5eOVKlWCr68vhg4dCjc3N+zbt0+JqFQEnDt3DgMGDCh007R06VJ8/fXXOH/+PPbv3y8ft7KywsKFC9GtWzd4enq+UNAiep5Wq0Xx4sWhVqtx8OBBuQBlYGCAjh07IiAgAI8fP0aDBg3kc0Qvc+PGDURFRcm/m5ubY/LkyVCr1Th79qx8vGLFihgzZgz69OmDBQsWYPny5UrEJT2XnJyMH374AT/++CP++OMPSJKE9u3bY9GiRahUqRJ69OiBzMxMAIBKpUK/fv3g6emJEiVKICsrS+H0pI+ysrKQmZmJjIwMAIC1tTVGjhyJTp06ITQ0FMePH5fburq6Yvz48bh9+zaWLVuG3NxcpWJTEZKTk4Pw8HBERkbijz/+kHfWK1OmDKZNmwYnJyeEhIRg9uzZ8mu4niLJFJxGSO+Z27dvyz/n5+fLP6enp4tp06YJlUoltm3bVug18fHxws/PT8TFxb2znFR0xMTECAMDAzF9+nT5WEFBgfyzj4+PMDY2Fjt27Cj0uocPH3INBHqpxMREsX37drFu3Tpx7tw5+XhsbKyoVauWaNiwocjKypKP5+fni9DQUNGiRQuRkJCgRGQqAs6ePSskSRIbN24sdPzevXti0aJFwtTUVMyaNavQuT///FPMmjVLxMfHv8uoVAScO3dO2Nrairp16woHBwdhbGwsZsyYIe7duyeEEOLXX38VDRs2FA0bNhQZGRny6zQajXj06JFSsUmPnTt3TnTq1EnUqFFDtGnTRkyePFk+Fx0dLVxcXESDBg1EdHR0odft27dPJCYmvuu4VETcu3dPxMTEiMuXL8vXopSUFOHv7y+KFy8ufH19C7VPSUkRgwcPFp06dRIPHjxQIjLpMRam6K24fPmyMDQ0FC4uLvKxJ0+eyD9nZGSIyZMnC5VK9cICd88WsYh0zp07J0xNTcW0adMKHX/+g8zLy0sYGxuLn3766V3GoyIoNjZW/rJXpUoVYWhoKGbOnCmuXbsmhHja56pXry4aN24ssrOz5dfl5+eLzMxMpWKTnouJiRHm5ubiiy++eOn527dvi4CAAFGyZMkXilP8/KPnpaWlifr16wtfX1+Rk5MjUlJSRHBwsDA2NhaDBw8WN2/eFEIIERkZKRo1aiSaNm0qHj9+rHBq0mfXr18XVlZWwsfHRwQFBYnZs2eLUqVKic6dO8v96ejRo8LNzU00aNBAHD9+XOHEVBTExsaKGjVqiEqVKgl7e3tRt25due88ePBAzJ07V9SsWVNMnTq10OtSU1NFamqqEpFJz7EwRf/arVu3RIsWLUSzZs1E5cqVRa9eveRzLytOGRsbi+DgYCWiUhFx8+ZNYWdnJzp37iwf8/LyEh06dBBVq1YVEydOLLTT0BdffCEkSRJ79uxRIC0VBWlpaaJRo0Zi0qRJIjMzU2RmZoo1a9YIW1tbMXToUHHhwgUhxP9utJo3b15o5BTRy5w/f77QU2GNRiNCQ0PFt99+K9atWye3u3v3rggICBDW1taFRioQPe/evXvC0dFRHDhwoNDxiIgIYWpqKkaOHCmEeFrUPHLkiKhatapo164ddzKmv7Rq1SrRokULkZubKx87f/68qFixomjTpo08yi4iIkL07dtXODg4iJMnTyoVl4qAlJQUUaFCBTF58mRx8eJF8fPPP4u+ffsKU1NTsWXLFiGEEHfu3JGLUzNmzFA4MRUFBkpPJaSiLzIyEnZ2dpgwYQLu378PX19f9O7dGzt37oShoaG8I1qxYsUwY8YMZGZmYuLEiejVqxeKFy+udHzSQxqNBlWqVIGZmRm2bduGlStXolixYmjatCm6d++O2bNn48qVK1i3bh1Kly6NgIAAGBsbo3r16kpHJz2l0WiQkZGBFi1awNzcHAAwYsQIWFtbw9fXF0ZGRvD390fdunWxfft2dO3aFS4uLoiIiFA4OemzVatWITMzE+7u7sjNzUX37t2RlZWFpKQkGBoaYsGCBThy5AjKlCkDDw8P5OTk4Pvvv4evry+srKwgSZLSfwLpEa1Wi+zsbCQkJMgbexQUFECSJHTo0AE7d+5E9+7d0bJlSwwePBitW7dGcHAwypYty75Ef+nmzZtIS0uDsbExgKefh7Vr10ZERATatGmD4cOHY8eOHejQoQM0Gg1MTExgbW2tcGrSZ8nJybCwsMC4ceNQoUIFODo6olu3bvDx8cGwYcNQrFgx9OjRA56enlCpVAgMDISRkRFmzpypdHTSZ0pXxqjoy8rKEiEhIUKIp0/wduzYIRwcHP5y5FR2dra4c+fOO89JRYPuqe+1a9eEs7OzsLa2Fi4uLuLu3btym7i4OGFqaioCAwOViklFiFarFX/++aewtbWVpxI/++R4x44dwsjISH7Kp9Vqxfnz57n2D70WV1dXYW1tLRo2bCh69OghLl++LO7duycuXbokmjRpIho1aiQ0Go0Q4un6d1xXg5737NRhIYQYO3as+Oijj+R18AoKCuRpn97e3qJt27YiPT39neekokV3PxUdHS0sLCwKrfOqW6/z0KFDonTp0mLv3r3yuef7I9Hzfv75ZyFJknxv/uy09NGjRwsLCwt5bbJbt26JgIAA3lPR3+KufPSvmZmZoUePHgCe7mTl4uKCRYsW4cyZM+jduzcAwNDQEGvWrEF8fDxMTU1RunRpJSOTHpMkCVqtFlWrVsXy5cvRq1cvTJgwATY2NgCePumrXr066tWrh7i4OIXTUlEgSRIqVaqEXr16wdvbGzdv3oSxsTHy8/MhhEDfvn0xZswYBAQEICsrC5IkoXbt2qhSpYrS0akI2L17N9q0aYP09HQsWbIENWrUgLW1NWrWrInp06cjOTkZsbGxAABLS0uUKlVK4cSkT86dO4eRI0cW2nl20KBBqFixIqZNm4bLly9DrVZDpXp6y25jY4Pc3FyUKFFCqcik53Q7yOpG0dnb26N79+7YsGEDjhw5AuB/O6HVqVMH5ubmuHXrlvx6U1PTd5yYigpd32rXrh0aNmyIyZMnIysrCwYGBvKu7HPmzEGtWrWwZs0aaDQalClTBj4+Prynor/FwhT9Kxs2bHhhq2sTExN0794dAQEBOHPmDPr06QNvb2+MHj2aW4LSa1GpVNBoNKhatSrmz5+PVq1ayefUajWysrJgZmaGWrVqKZiSigLxdC1FAMDnn3+OGjVqoH///khOToahoaF8I1WxYkUYGxvDzMxMybik5+7cuYOoqCiEh4cjJSVFPr5z504EBQWhbNmyACD3OZVKhRIlSnBaDL1UbGwsGjRoAHt7e5QvX14+3qJFC3h4eCAzMxOff/45/vjjD7kwde/ePVhaWiInJ0ep2KTHrly5Am9vbwwfPhx+fn5IS0tDuXLlMG7cODx+/BhLly5FWFiY3N7W1hbly5eXr1lEL5OdnQ0AyMrKAgAYGxvD3d0dFy9exPLly5GXlwe1Wg0hBKytrVGyZEkkJSXJ3/t01y+iV+EaU/SPpaamYvHixRgwYECh40IImJqaonv37igoKIC7uzssLS1x+vRpVKpUSaG0VJQUFBTAwMAAubm5sLS0fOG8v78/bty4gW7duimQjvTdxYsXsW3bNsydO1cegSdJEmrWrImJEydi8eLF+OSTT7Bjxw55XbLExESYm5sjJycHpqamXK+FXnD+/Hm4u7sDAB49egQLCwv8+OOPqFmzJgCgS5cucltd/zly5Ajs7e1hYWHx7gOTXjt//jyaN2+OKVOm4P/+7/8APB2NkJ6ejlKlSsHDwwPFihVDcHAwWrRogbZt20Kj0eD06dP49ddfWUSnF1y+fBlNmzaFs7MzcnNzcfLkSWzYsAFBQUHo3bs35s2bh7lz52Lq1Kk4deoUnJyccPDgQZw/fx6dO3dWOj7pqQsXLmDSpEm4f/8+TExMMGTIEHz22WcYP3484uPj8dNPPyE3NxczZsyAgcHT0oKlpSUsLS3l+y/eU9HrYGGK3phGo4FarUZcXByMjIzQvn37Qud1Fx8TExOEh4fDzMwMUVFRcHR0VCIu6TFdX3r+mIGBAW7cuAEXFxfs2rULH330EQBg37592LZtGw4ePIiDBw/CwcFBgdSkz65fv46OHTvi7t27SE1Nxdq1a6FSqeRip4uLC8zMzLBkyRLUq1cPzZo1g1qt5pc9eqVr166hc+fO8PT0xNixY5GQkIAlS5Zg2bJlWLFiBdRqdaEb77i4OKxbtw7r1q3D0aNHOe2KCrl58yaaN2+OLl26yEUpX19fxMTEIC0tDS1btkRAQADc3NzQvHlzHDp0CKdOnYKNjQ2+/fZbbvRBL9BoNJgzZw4++eQTbN26FVqtFlqtFkOHDsWwYcOQk5ODTz/9FBYWFggNDcWKFStgZ2cHIyMjHDlyBJUrV1b6TyA9FB8fj9atW8PDwwOtWrXCw4cPMWLECERFReGbb77B0qVLMX36dISGhiI0NBQuLi6Ij49HaGgoTpw4wZFS9EZYmKI3piskTJ06FTVq1ECzZs1e2m7//v04evQojh49yqIUveDq1avYu3cvBg4ciDJlygB4OtpOrVYjMTERrVq1QufOnVGtWjUAQH5+PoyMjJCbm4vIyEhO46MXZGZmYtGiRWjVqhVcXFzg5eWFgoICbNiwAQYGBnJxqmPHjmjTpg02b96Mq1evwtzcHEFBQXIBlOhZOTk5WLhwIbp27Qp/f39IkgR7e3scOXIEO3fulJ8Q68TExGDt2rUICwtDZGQk6tatq1By0lempqaoWLEiCgoKsH//fsydOxfm5uZwcnJCiRIl8M033+Dq1asICwuDnZ0dPDw84OHhoXRs0mNqtRrp6eny9Uar1cLAwACbNm2SR7dUq1YNTZs2Rf369fHFF1+goKAAKpWKO2TTX9q5cyfq1q2LwMBA+djHH3+Mnj17Ijc3F99//z3mzZuHiIgIbNu2DceOHYONjQ2io6P53Y/emCQ4qZjegBACkiQhLCwMc+bMwZo1a+QCwaNHj3D37l2cOXMG/fv3R05ODh49egQ7OzuFU5O+iY+PR9OmTZGWloYpU6Zg4sSJ8hosubm58PLygkqlwrfffvvC8N/c3FyYmJgoEZv0XEZGBlauXIlq1aqhV69eCAsLg7u7O3r27IkNGzYAePkoPaJXyc3NxaJFi2BtbY0xY8bIn4NnzpzBwIEDcfz4cRQvXlzuV5mZmbh48SLKly+PcuXKKZye9I3uGnTnzh306NED58+fh7OzM4KCgmBrawsAuHTpEpo0aYK5c+fC29tb2cBUZPTr1w8JCQk4efIkACAvLw/GxsYAgG7duiElJQVnz57lKBZ6bb6+vjh16hSOHj0KIYQ8qyEqKgpdunTB559/joULF8rttVqt/JCZ6E3xykRvRFck2L59O2xsbPDRRx9BCIHDhw/D09MTPXv2RFBQENLT02FqasqiFL0gKysL/v7+6NGjB5YvX4758+dj4cKFePDgAYCnU0B9fX0RFBT00jnpLErRXylevDjGjh2L3r17Q5IkdO7cGVu2bEFISAgGDx4M4OlT5SdPniAhIUHZsFRkmJiY4NNPP8WYMWMKHZckCfn5+ZAkSf6id+fOHRQrVgxNmzZlUYpeSq1WQ6PRwNbWFqGhoejduzeGDRsmF6UAoFq1aqhevXqhBfaJ/opupzQfHx88fvwYkyZNAvB0gerc3FwAwIwZM5CWlibvEEr0Opo0aYLo6GgcP35c/qzTaDRo3bo11q1bh2XLluH48eNye5VKxaIU/WMsTNEbO3r0KA4ePIiFCxdi9+7d+Oyzz+Di4oKKFSti/vz5iIyMRMmSJZWOSXpKpVLByckJzs7OGDduHLZv346AgAAsWLAAd+/eBQB5+p4OB3bS69Kt5SOEgIGBAT7++GNs3rwZoaGhGDJkCADA29sbX375JXe1otf27MYdugX1s7KykJeXByMjI0iSBD8/P9StWxe5ubm8ZtErqdVqFBQUwNbWFqtXr0bHjh0LnX/y5AksLS3l6cXsT/Q83eeXbgQnANSpUwf9+/fH4cOH8fXXXwP438M83ahOFg3o7+h2KwaADh06wNXVFVOmTMG5c+cKjbbr2LEj7O3tcf36dSVi0nuIa0zRGzt69Cjy8vIwaNAgpKamYtiwYThw4ABatWolt3n2g5LoWaamphgyZAjMzc0BPB16LoSAu7s7hBCYMmUKrKysoNVqkZiYiEqVKrEv0RvT9RmVSoXu3btjy5YtGDJkCOzt7ZGamorjx4/D1NRU4ZRUVGi1WvmGXLdWmbm5OQwMDGBkZISZM2di9erVOHToEEd10gue7T/A//pQTk4OzMzMXig8+fv74/r16/JOj/wMpGddunQJzs7OWLZsGdzc3OQpVsWKFcO4ceOQmZmJ0NBQ/Pnnn1i+fDkePXqEH3/8EYaGhoVG5hE9686dO7C1tZUL5wYGBrC2tsbgwYOxdOlSTJ06FXPnzkWDBg0APN15r0SJEvKIPaJ/i4UpeiMFBQVITk6Go6MjWrVqhcmTJ8PCwgKSJBUqRvEmil5FV5TSaDRQqVTo378/hBAYOHAgJEmCt7c3AgICkJiYiE2bNnGnNHqBbp2WZ687uhupZ9fVAJ5ejzp06AAnJyf88ccfOHv2LGrXrq1UdCpidH3t7t27KF26tLzYubGxMSwtLTFmzBhs2LAB0dHRcHJyUjgt6RPdF71ni1LP7jzbtm1bREREyKOEIyIisG7dOnnn2YoVKyoVnfRUUlIS+vXrh7y8PIwYMQIA4ObmJk+xKl26NKZNm4bq1avjm2++Qbly5WBvb4/Hjx8jNDSUhSl6qbi4ONStWxfOzs4IDQ2FgYEBnjx5AiMjI7i4uCAnJwfr169Hv379MGvWLFhbWyMiIgJJSUlo3bq10vHpPcHCFL0RAwMDBAQEQAghT9fTarWQJInFKHpjusKCVqvFgAEDIEkSPDw8EBoaiuvXr+PUqVMsStELzpw5A29vb/zyyy+Fipy6L3suLi7YtWuXPA1Gq9Vi4cKFOHToEItS9EZ0N+aJiYmoVq0aAgICMGHCBADAgwcPEBsbi/j4eBw/flx+ikwEALGxsXB2dsaWLVvQoUMH+bharZa/zHXq1AlVq1YF8HT9xczMTGg0Gu48Sy+Vn5+PjRs3okaNGli8eDFCQ0Ph6ekJSZLg6uoKlUqFgoICWFlZYfjw4fD09MQvv/wCa2trVKxYEeXLl1f6TyA9lJqais8++wxOTk64ePEievfujZ07d8LIyEj+DOzXrx8qVqyIbdu2YeTIkXBwcICBgQEOHjwIBwcHpf8Eek9wVz76Vzhlj94G3WVIkiR07NgRMTExiIyMRJ06dRRORvomNjYWLVu2xKhRo/DNN98A+N91KDExEc2aNUPXrl2xfv16+dqUnZ2N1atXo0uXLvyyRy915coVrF69Grdu3UL9+vXRpUsXNGzYEMDTEQpNmzaFm5sbVqxYUWih88mTJ8PPz4/9igqJjY1Fs2bNMGHCBCxYsKDQuezsbAwfPhyWlpZYsWJFoXuo/Px8FBQUcJox/aVjx47hxo0b+PTTT5GcnIz58+dj8+bNCA4Olqf16T4TeX9Or2Pbtm346aefMGHCBNy/fx++vr5o2LAhdu7cCQAvjEJPTk6GmZkZVCoVLC0tlYpN7yEWpohIL2g0Gvj5+WHp0qWIiYlB3bp1lY5EeubcuXNo0aIFxo4dW2h74pycHJiammLChAkoKCjA8uXLX1jg9fk1Xoh0Ll26hBYtWqB169YoWbIkwsPDUa1aNfTo0QO+vr7YsGEDrl69irlz577wRS87O5ujOqmQS5cuwcnJCVOmTMFXX30FIQSSk5Nx584d1K9fH4aGhrh58ybKli3LaxL9awkJCQgICMCmTZuwYcMGuLq6Ii8vD6dOnUL9+vVRrFgxpSOSnsvOzkZ4eDh69OiBgoIC7N69G5MmTSpUnMrPz4ehoSEHJNB/ioUpItILGo0GwcHBcHJyQv369ZWOQ3rm9u3baNCgAerVq4ewsDBoNBr4+Pjg2rVruHLlCkaNGoVKlSqhX79+SkelIiQ/Px/Dhw+HoaEhvv/+ewBPR0j5+/vj5MmTGDRoECZOnKhwSioqHj16hG7duiE5ORlJSUkAgP79++PSpUuIj49HuXLlMG3aNPTu3RsWFhYKp6Wi7NkCwY0bN/DNN99g06ZNWLduHaKjo7FhwwZcuXIFVlZWCiclffayh3a5ubnYt28f/Pz8ChWnvvvuO7Rr1+6FnbOJ3hauMUVEekGtVmPYsGF8EkN/qXnz5khOTkZISAhWrVqFgoICNGnSBI6Ojti6dStq1KiBevXqoXr16kpHpSLC0NAQqampqFChAoCnX/bs7e3x5ZdfYuHChfjhhx9ga2uLQYMGKZyUigILCwu4ubnhl19+wZAhQ3Dx4kWUKVMGs2fPRq1atTBv3jz4+/ujRIkS6NOnD0dy0hvT9RlJkuRRLJUqVYKvry8kSULfvn1hYWGBgwcPsihFf+tl99wmJibo3r07JEmCr68v+vTpg/LlyyMwMBDXr19XICV9KDhiioiIioTU1FRMmTIFO3bsQOvWrbF9+3aUKlUKALBnzx6MHj0agYGBHDVFr0Wj0UCr1WLUqFFIT0/H1q1bYWxsDCEEVCoVkpKSMHr0aBgaGiIkJETpuKTnni0yBQYGYvXq1bC3t8e6detQpkwZuZ2zszOysrIQFRWlVFQqop7fIfR57u7uCAsLw7Fjx+Do6KhAQioqnp+Sl5SUhAoVKhTaZT03NxchISFwd3eHpaUlDh06JK+9SPRf4GMaIiIqEsqUKQN/f39MnDgR06ZNQ6lSpaDVagEArq6usLKywq+//qpwStJ3Go0GwNNRmoaGhhgyZAhCQ0OxZs0aSJIElUoFrVYLe3t7zJo1C3v37kVMTIyyoUlvZWVlISMjA5mZmfKxCRMmYMqUKRg/fjzs7OwAAAUFBQDA3RvpH3ny5AnUajUSExPl0Ss6Wq0Wa9asQVhYGCIiIliUolfSaDRyUerRo0dYsWIF2rdvjz179gD43ygqExMThIeHw8zMDFFRUSxK0X+OU/mIiKjIKFu2LCZNmiTvWqVSqSCEQHp6OqysrODk5KRwQtJnV69exd69ezFw4EB5FEvbtm2xYMEC+Pj4wMzMDMOHD5dHvhQrVgyOjo5c4Jxe6tKlS/Dx8cG9e/dw584dLFy4EAMGDIBarYaHhwfy8/PlL3kGBk9vuVNSUlCrVi1otVrunEYv+KsdQo2MjJCUlIRmzZph+PDhGD9+vPwalUqF+vXr4/Tp06hSpYqC6ako0G0OExAQgPj4eKxZs+al7fbv34/IyEgcPXqUxU56J1iYIiKiIuX5RYMlScKSJUuQmpqK9u3bK5SK9F18fDyaN2+OtLQ0PHjwABMnToS1tTUAYMyYMcjKysLIkSORkJAANzc3VKxYERs3bkROTg4XqqYXXLp0CW3atMHgwYPRuHFjnD59GkOHDkWtWrXkDTwMDQ3l9rm5uZg7dy7CwsIQFRXFtaXoBc/vELps2TLs379f3iH0yJEjGDZs2Et3CG3SpIlCqako0E3Pe/jwIa5evYrRo0fDzs4OlStXRuXKleHu7g43N7dCr2nfvj2ioqLkUZ9E/zWuMUVEREXW9u3bERkZiR07diAiIoLTZOilsrKyMGHCBGi1WjRq1Aiff/45fH194efnBxsbGwBPp8Ns2bIFkyZNgkqlQokSJZCRkYG9e/eyX1EhDx8+hLu7O2rUqIFly5bJxzt06IA6depg2bJlhdZw2b9/PxYvXoy4uDj2J3op7hBK/7Vff/0Vq1atQnx8PKpWrYrFixcjIiICe/fuxbhx49C6dWtotVr4+vrC3t4e3t7eSkemDwxHTBERUZHl6OiIzZs3IyoqCrVq1VI6DukplUoFJycnWFlZoX///rCxscGAAQMAQC5OqVQqeHh4oHXr1khKSkJOTg5q166NcuXKKZye9E1+fj7S09PRp08fAP9b+Lxy5cp48OABgMK7XbVr1w5nz57FypUruWsovRR3CKX/Uk5ODrZu3YqyZcuiT58+6NWrFwBg/fr1KFu2LFq2bAkAmDRpEpYuXYrTp08rGZc+UBwxRURERdqTJ09gZGSkdAzSc1lZWTA3N5d//+GHH+Du7o4vvvgCkydPhrW1NQoKCnDr1i3Y29srmJSKgmvXrqFatWoAnhaqDA0N8dVXX+HGjRvYuHGj3O7x48coUaKEUjFJz+l22svLy8OYMWO4Qyj9Z7Kzs2FoaChPMZ4xYwY2bNiAS5cuoXjx4vD29sbq1asRHR3NUZ2kCE5wJyKiIo1FKXoduqKURqOBEAL9+/fH1q1b8c0332DhwoW4desWJk2aBB8fH2RlZYHP7ehVdEUprVYrf9HTaDS4c+eO3Mbf3x/ff/+9vCMf0bPOnDmD9u3bIysrC8bGxtwhlP5TZmZm8rUqNjYWZ8+exaxZs1C8eHF4eXlh9erVOHbsGItSpBhO5SMiIqIPhlqthhACWq0WAwYMgCRJ8PDwQGhoKK5fv45Tp04VGllF9Cq6nUF1O+zpdrz68ssvMXfuXJw9e1bekY9IJzY2Fm3atMGoUaNgbm4OIQTatm0Lf39/+Pj4wMTEBCNHjuQOofSfSEhIwKNHj9CkSRPMmDEDa9aswbFjx9CwYUOlo9EHjJ+URERE9EHRrf+jGzm1Zs0axMTE4MyZM6hTp47C6aio0RWm1Go1KlSogICAACxcuBCnT59GvXr1lI5HeubcuXNo2bIlxo4di4ULFwJ4ek3Kzc2Fn58ftFotxowZg4SEBPTu3Zs7hNJb17hxYwQGBiIsLAzz5s3D6dOnWZQixbEwRURERB8cSZKg0Wjg5+eHI0eOICYmhkUp+kd0o1oMDQ3x3XffoUSJEvjtt9/4RY9ecPv2bXTt2hWtWrXCwoULodFo4OPjg6tXr+LatWsYOnQoPv74Y9SoUQNjxoxBcHAwLCws5B1CbW1tlf4T6D1QtmxZWFhYYOXKlTh16hSvVaQXuPg5ERERfZA0Gg2Cg4Ph5OSE+vXrKx2HirjTp0+jSZMmuHDhAhwdHZWOQ3ro9u3bGDt2LJKTkzFjxgysWrUKBQUFaNKkCfLy8nDw4EFUr14d69atQ1paGhISEpCXlwdHR0fuEEpvnW7jBiJ9wMIUERERfbB007CI3obnd38kel5qaiqmTJmCHTt2oHXr1ti+fTtKlSoFANizZw9GjhyJwMBADBgwQOGkRETvDgtTRERERERE78itW7ewcuVKdO7cGe3atYNWq5WnhNaqVQvt27fHihUrFE5JRPTucI0pIiIiIiKid6Rs2bKYNGkSTE1NAfxvd8f09HRYWVnByclJ4YRERO8WC1NERERERETv0PM77EmShCVLliA1NRXt27dXKBURkTJYmCIiIiIiIlLI9u3bERkZiR07diAiIgIODg5KRyIieqdUSgcgIiIiIiL6UDk6OuLmzZuIiopCgwYNlI5DRPTOcfFzIiIiIiIiBT158gRGRkZKxyAiUgQLU0REREREREREpAhO5SMiIiIiIiIiIkWwMEVERERERERERIpgYYqIiIiIiIiIiBTBwhQRERERERERESmChSkiIiIiIiIiIlIEC1NERERERERERKQIFqaIiIiI3iPBwcEoWbKk0jGIiIiIXgsLU0RERET/gKenJyRJgiRJMDQ0hK2tLTp37ox169ZBq9W+kwwODg5YunRpoWP9+/fH1atX38m/T0RERPRvsTBFRERE9A85OzsjNTUVCQkJ+OWXX9C+fXt4eXnhk08+QUFBwT96TyHEP34tAJiamqJ06dL/+PVERERE7xILU0RERET/kLGxMezs7FCuXDk0bNgQ06ZNQ0hICH755RcEBwcjISEBkiQhJiZGfk16ejokSUJkZCQAIDIyEpIk4cCBA2jUqBGMjY0RFRWF69evo2fPnrC1tUWxYsXQuHFjhIeHy+/Trl07JCYmwsfHRx65Bbx8Kl9QUBCqVKkCIyMjVK9eHZs2bSp0XpIkfP/993Bzc4OZmRmqVauG0NDQ/+S/GREREdGzWJgiIiIieos6dOiAevXqYdeuXW/0ukmTJsHf3x+XL19G3bp1kZmZiW7duiE8PBxnz55F165d4eLigqSkJADArl27UL58ecyePRupqalITU196fvu3r0bXl5e+OKLL3DhwgWMGjUKQ4cOxZEjRwq1mzVrFvr164dz586hW7duGDRoEB4+fPjP/iMQERERvSYWpoiIiIjesho1aiAhIeGNXjN79mx07twZVapUgZWVFerVq4dRo0ahTp06qFatGubOnYvKlSvLI5lKlSoFtVqN4sWLw87ODnZ2di9934CAAHh6emLs2LH46KOPMHHiRPTq1QsBAQGF2nl6esLd3R1Vq1bFvHnzkJWVhZMnT/6jv5+IiIjodbEwRURERPSWCSHkqXWvq1GjRoV+z8rKwqRJk+Do6IiSJUuiWLFiiIuLk0dMva7Lly+jZcuWhY61bNkSly9fLnSsbt268s/m5uYoXrw47t69+0b/FhEREdGbMlA6ABEREdH75vLly6hUqRJUqqfPAIUQ8rn8/PyXvsbc3LzQ735+fjhw4AACAgJQtWpVmJqaok+fPnjy5Mkb53m+SPaywpmhoeELr3lXuwsSERHRh4sjpoiIiIjeosOHD+P8+fPo3bs3bGxsAKDQ+k/PLoT+KlFRUfD09ISbmxvq1KkDOzu7F6YHGhkZQaPRvPJ9atasid9++63QsejoaNSsWfO1chARERH9lzhiioiIiOgfysvLw+3bt6HRaHDnzh2EhYXB398fn3zyCQYPHgy1Wo1mzZph/vz5cHBwwP379zFjxozXeu+qVati165dcHFxgSRJmDlz5gsjmBwcHPDrr79iwIABMDY2hrW19Qvv4+fnh379+qFhw4bo2LEj9u7di127dhXa4Y+IiIhIKRwxRURERPQPhYWFoUyZMnBwcICzszOOHDmCwMBAhISEQK1WAwDWrVuH/Px8NGrUCF5eXpg7d+5rvfeSJUtgaWmJFi1awMXFBV27dkXDhg0LtZk9ezYSEhJQpUoVeXTW81xdXbFs2TIsWrQItWrVwurVq7F+/Xq0a9fuX/3tRERERG+DJJ5d9ICIiIiIiIiIiOgd4YgpIiIiIiIiIiJSBAtTRERERERERESkCBamiIiIiIiIiIhIESxMERERERERERGRIliYIiIiIiIiIiIiRbAwRUREREREREREimBhioiIiIiIiIiIFMHCFBERERERERERKYKFKSIiIiIiIiIiUgQLU0REREREREREpAgWpoiIiIiIiIiISBEsTBERERERERERkSL+H5vIJwu97PcDAAAAAElFTkSuQmCC", "text/plain": [ "
" ] }, "metadata": {}, "output_type": "display_data" }, { "name": "stdout", "output_type": "stream", "text": [ "\n", "=== Summary Statistics ===\n" ] }, { "data": { "text/html": [ "
\n", "\n", "\n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", " \n", "
variantcountmean_msmedian_msmin_msmax_msbin_counts
0regular2485080.1133280.0518330.00020891.613584{'<1ms': 245646, '1-5ms': 2721, '5-10ms': 120,...
1optimal2485080.1297410.0282080.0001663345.752291{'<1ms': 245834, '1-5ms': 2495, '5-10ms': 108,...
\n", "
" ], "text/plain": [ " variant count mean_ms median_ms min_ms max_ms \\\n", "0 regular 248508 0.113328 0.051833 0.000208 91.613584 \n", "1 optimal 248508 0.129741 0.028208 0.000166 3345.752291 \n", "\n", " bin_counts \n", "0 {'<1ms': 245646, '1-5ms': 2721, '5-10ms': 120,... \n", "1 {'<1ms': 245834, '1-5ms': 2495, '5-10ms': 108,... " ] }, "metadata": {}, "output_type": "display_data" } ], "source": [ "# Check if data is loaded and has the required columns\n", "if 'stats' in locals() and 'variant' in stats.columns and 'duration_ns' in stats.columns:\n", " # Get available variants\n", " available_variants = stats['variant'].unique()\n", " print(f\"Processing variants: {available_variants}\")\n", " \n", " # Store statistics for summary\n", " variant_stats = []\n", " \n", " # Process each variant\n", " for variant in available_variants:\n", " print(f\"\\n=== Processing {variant} variant ===\")\n", " \n", " # Filter data for current variant\n", " variant_data = stats[stats[\"variant\"] == variant]\n", " print(f\"Found {len(variant_data)} records for {variant} variant\")\n", " \n", " if len(variant_data) > 0:\n", " # Create histogram for this variant\n", " stats_summary = create_performance_histogram(variant, variant_data)\n", " variant_stats.append(stats_summary)\n", " else:\n", " print(f\"No data found for variant: {variant}\")\n", " \n", " # Display summary statistics\n", " if variant_stats:\n", " print(\"\\n=== Summary Statistics ===\")\n", " summary_df = pd.DataFrame(variant_stats)\n", " display(summary_df)\n", " \n", "else:\n", " print(\"Data not loaded or missing required columns ('variant', 'duration_ns')\")\n", " print(\"Please ensure the CSV file is loaded and contains the correct columns.\")" ] } ], "metadata": { "kernelspec": { "display_name": "base", "language": "python", "name": "python3" }, "language_info": { "codemirror_mode": { "name": "ipython", "version": 3 }, "file_extension": ".py", "mimetype": "text/x-python", "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", "version": "3.13.5" } }, "nbformat": 4, "nbformat_minor": 5 } diff-1.0.1/plots/perf_go_repo.png000066400000000000000000001246151516001707200167460ustar00rootroot00000000000000PNG  IHDRN3:tEXtSoftwareMatplotlib version3.10.0, https://matplotlib.org/rXr pHYsaa?iIDATxwxU{{ .M#H AMJ@T( bXPQWҋ.( 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For example the code below, // presents the header in bold yellow: // // HunkHeader(1, 33) // // This is equivalent to the following raw ANSI sequence: \033[1;33m. // // It's the responsibility of the caller to ensure that the parameters are correct and supported // by the underlying terminal. // // [Select Graphic Rendition parameters]: https://en.wikipedia.org/wiki/ANSI_escape_code#SGR package color import ( "fmt" "strings" "znkr.io/diff/internal/config" ) // A Option makes it possible to configure custom colors in [textdiff.TerminalColors]. // // [textdiff.TerminalColors]: https://pkg.go.dev/znkr.io/diff/textdiff#TerminalColors type Option func(*config.ColorConfig) // HunkHeaders colors hunk headers, the "@@ ... @@" part of the unified diff. func HunkHeaders(params ...int) Option { code := format(params) return func(cc *config.ColorConfig) { cc.HunkHeader = code } } // Matches colors matching lines. func Matches(params ...int) Option { code := format(params) return func(cc *config.ColorConfig) { cc.Match = code } } // Deletes colors deleted lines. func Deletes(params ...int) Option { code := format(params) return func(cc *config.ColorConfig) { cc.Delete = code } } // Inserts colors deleted lines. func Inserts(params ...int) Option { code := format(params) return func(cc *config.ColorConfig) { cc.Insert = code } } func format(params []int) string { var sb strings.Builder sb.WriteString("\033[") for i, v := range params { if i > 0 { sb.WriteRune(';') } fmt.Fprint(&sb, v) } sb.WriteRune('m') return sb.String() } diff-1.0.1/textdiff/example_test.go000066400000000000000000000027071516001707200172640ustar00rootroot00000000000000package textdiff_test import ( "fmt" "znkr.io/diff/textdiff" ) func ExampleUnified() { x := `this paragraph is not changed and barely long enough to create a new hunk this paragraph is going to be removed ` y := `this is a new paragraph that is inserted at the top this paragraph is not changed and barely long enough to create a new hunk ` fmt.Print(textdiff.Unified(x, y)) // Output: // @@ -1,3 +1,6 @@ // +this is a new paragraph // +that is inserted at the top // + // this paragraph // is not // changed and // @@ -5,7 +8,3 @@ // enough to // create a // new hunk // - // -this paragraph // -is going to be // -removed } func ExampleIndentHeuristic() { x := `// ... ["foo", "bar", "baz"].map do |i| i.upcase end ` y := `// ... ["foo", "bar", "baz"].map do |i| i end ["foo", "bar", "baz"].map do |i| i.upcase end ` fmt.Println("With textdiff.IndentHeuristic:") fmt.Print(textdiff.Unified(x, y, textdiff.IndentHeuristic())) fmt.Println() fmt.Println("Without textdiff.IndentHeuristic:") fmt.Print(textdiff.Unified(x, y)) // Output: // With textdiff.IndentHeuristic: // @@ -1,4 +1,8 @@ // // ... // +["foo", "bar", "baz"].map do |i| // + i // +end // + // ["foo", "bar", "baz"].map do |i| // i.upcase // end // // Without textdiff.IndentHeuristic: // @@ -1,4 +1,8 @@ // // ... // ["foo", "bar", "baz"].map do |i| // + i // +end // + // +["foo", "bar", "baz"].map do |i| // i.upcase // end } diff-1.0.1/textdiff/options.go000066400000000000000000000047041516001707200162640ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package textdiff import ( "znkr.io/diff/internal/config" "znkr.io/diff/textdiff/color" ) // Option configures the behavior of comparison functions. // // Note: The [options defined in the diff package] work for most functions in this package too. See // the description of the individual functions for a list of supported options. // // [options defined in the diff package]: https://pkg.go.dev/znkr.io/diff#Option type Option = config.Option // IndentHeuristic applies a heuristic to make diffs easier to read by improving the placement of // edit boundaries. // // This implements a heuristic that shifts edit boundaries to align with indentation patterns, // making the resulting diff more readable for humans. The heuristic is particularly effective with // code and structured text. func IndentHeuristic() Option { return func(cfg *config.Config) config.Flag { cfg.IndentHeuristic = true return config.IndentHeuristic } } // TerminalColors uses ANSI escape codes to color the output of [Unified]. // // By default, the colors try to emulate git's color scheme, but the colors can be overridden using // [color.Option]. // // Note: Using TerminalColors will output ANSI escape quotes unconditionally. It's the callers // responsibility to make sure it's only used in contexts that support ANSI escape sequences (e.g. // by guarding the use of this option with [github.com/mattn/go-isatty]). // // [github.com/mattn/go-isatty]: https://pkg.go.dev/github.com/mattn/go-isatty func TerminalColors(opts ...color.Option) Option { return func(c *config.Config) config.Flag { colors := config.ColorConfig{ Reset: "\033[m", HunkHeader: "\033[36m", // Cyan Match: "", // Normal Delete: "\033[31m", // Red Insert: "\033[32m", // Green } for _, opt := range opts { opt(&colors) } c.Colors = &colors return config.TerminalColors } } diff-1.0.1/textdiff/testdata/000077500000000000000000000000001516001707200160465ustar00rootroot00000000000000diff-1.0.1/textdiff/testdata/array_init_add.test000066400000000000000000000030751516001707200217250ustar00rootroot00000000000000-- x -- package array var m = []struct{ name string year int }{ { name: "Freak Out!", year: 1966, }, { name: "We're Only in It for the Money", year: 1967, }, } -- y -- package array var m = []struct{ name string year int }{ { name: "Freak Out!", year: 1966, }, { name: "Absolutely Free", year: 1967, }, { name: "We're Only in It for the Money", year: 1967, }, } -- diff -- @@ -9,6 +9,10 @@ year: 1966, }, { + name: "Absolutely Free", + year: 1967, + }, + { name: "We're Only in It for the Money", year: 1967, }, -- diff -- # indent-heuristic: true @@ -8,6 +8,10 @@ name: "Freak Out!", year: 1966, }, + { + name: "Absolutely Free", + year: 1967, + }, { name: "We're Only in It for the Money", year: 1967, -- diff -- # force-anchoring-heuristic: true @@ -9,6 +9,10 @@ year: 1966, }, { + name: "Absolutely Free", + year: 1967, + }, + { name: "We're Only in It for the Money", year: 1967, }, -- diff -- # fast: true @@ -9,6 +9,10 @@ year: 1966, }, { + name: "Absolutely Free", + year: 1967, + }, + { name: "We're Only in It for the Money", year: 1967, }, -- diff -- # context: 1 # indent-heuristic: true @@ -10,2 +10,6 @@ }, + { + name: "Absolutely Free", + year: 1967, + }, { diff-1.0.1/textdiff/testdata/array_init_delete.test000066400000000000000000000030751516001707200224370ustar00rootroot00000000000000-- x -- package array var m = []struct{ name string year int }{ { name: "Freak Out!", year: 1966, }, { name: "We're Only in It for the Money", year: 1967, }, { name: "Absolutely Free", year: 1967, }, } -- y -- package array var m = []struct{ name string year int }{ { name: "Freak Out!", year: 1966, }, { name: "Absolutely Free", year: 1967, }, } -- diff -- @@ -9,10 +9,6 @@ year: 1966, }, { - name: "We're Only in It for the Money", - year: 1967, - }, - { name: "Absolutely Free", year: 1967, }, -- diff -- # force-anchoring-heuristic: true @@ -9,10 +9,6 @@ year: 1966, }, { - name: "We're Only in It for the Money", - year: 1967, - }, - { name: "Absolutely Free", year: 1967, }, -- diff -- # fast: true @@ -9,10 +9,6 @@ year: 1966, }, { - name: "We're Only in It for the Money", - year: 1967, - }, - { name: "Absolutely Free", year: 1967, }, -- diff -- # indent-heuristic: true @@ -8,10 +8,6 @@ name: "Freak Out!", year: 1966, }, - { - name: "We're Only in It for the Money", - year: 1967, - }, { name: "Absolutely Free", year: 1967, -- diff -- # context: 1 # indent-heuristic: true @@ -10,6 +10,2 @@ }, - { - name: "We're Only in It for the Money", - year: 1967, - }, { diff-1.0.1/textdiff/testdata/array_init_reorder.test000066400000000000000000000041411516001707200226320ustar00rootroot00000000000000-- x -- package array var m = []struct{ name string year int }{ { name: "Freak Out!", year: 1966, }, { name: "We're Only in It for the Money", year: 1967, }, { name: "Absolutely Free", year: 1967, }, } -- y -- package array var m = []struct{ name string year int }{ { name: "Freak Out!", year: 1966, }, { name: "Absolutely Free", year: 1967, }, { name: "We're Only in It for the Money", year: 1967, }, } -- diff -- @@ -9,11 +9,11 @@ year: 1966, }, { - name: "We're Only in It for the Money", + name: "Absolutely Free", year: 1967, }, { - name: "Absolutely Free", + name: "We're Only in It for the Money", year: 1967, }, } -- diff -- # force-anchoring-heuristic: true @@ -9,11 +9,11 @@ year: 1966, }, { - name: "We're Only in It for the Money", + name: "Absolutely Free", year: 1967, }, { - name: "Absolutely Free", + name: "We're Only in It for the Money", year: 1967, }, } -- diff -- # fast: true @@ -9,11 +9,11 @@ year: 1966, }, { - name: "We're Only in It for the Money", + name: "Absolutely Free", year: 1967, }, { - name: "Absolutely Free", + name: "We're Only in It for the Money", year: 1967, }, } -- diff -- # indent-heuristic: true @@ -9,11 +9,11 @@ year: 1966, }, { - name: "We're Only in It for the Money", + name: "Absolutely Free", year: 1967, }, { - name: "Absolutely Free", + name: "We're Only in It for the Money", year: 1967, }, } -- diff -- # context: 1 # indent-heuristic: true @@ -11,3 +11,3 @@ { - name: "We're Only in It for the Money", + name: "Absolutely Free", year: 1967, @@ -15,3 +15,3 @@ { - name: "Absolutely Free", + name: "We're Only in It for the Money", year: 1967, diff-1.0.1/textdiff/testdata/chunk_copy.test000066400000000000000000000067461516001707200211260ustar00rootroot00000000000000From https://blog.jcoglan.com/2017/03/22/myers-diff-in-linear-space-theory/ -- x -- void Chunk_copy(Chunk *src, size_t src_start, Chunk *dst, size_t dst_start, size_t n) { if (!Chunk_bounds_check(src, src_start, n)) return; if (!Chunk_bounds_check(dst, dst_start, n)) return; memcpy(dst->data + dst_start, src->data + src_start, n); } int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) { if (chunk == NULL) return 0; return start <= chunk->length && n <= chunk->length - start; } -- y -- int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) { if (chunk == NULL) return 0; return start <= chunk->length && n <= chunk->length - start; } void Chunk_copy(Chunk *src, size_t src_start, Chunk *dst, size_t dst_start, size_t n) { if (!Chunk_bounds_check(src, src_start, n)) return; if (!Chunk_bounds_check(dst, dst_start, n)) return; memcpy(dst->data + dst_start, src->data + src_start, n); } -- diff -- @@ -1,14 +1,14 @@ +int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) +{ + if (chunk == NULL) return 0; + + return start <= chunk->length && n <= chunk->length - start; +} + void Chunk_copy(Chunk *src, size_t src_start, Chunk *dst, size_t dst_start, size_t n) { if (!Chunk_bounds_check(src, src_start, n)) return; if (!Chunk_bounds_check(dst, dst_start, n)) return; memcpy(dst->data + dst_start, src->data + src_start, n); -} - -int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) -{ - if (chunk == NULL) return 0; - - return start <= chunk->length && n <= chunk->length - start; } -- diff -- # indent-heuristic: true @@ -1,3 +1,10 @@ +int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) +{ + if (chunk == NULL) return 0; + + return start <= chunk->length && n <= chunk->length - start; +} + void Chunk_copy(Chunk *src, size_t src_start, Chunk *dst, size_t dst_start, size_t n) { if (!Chunk_bounds_check(src, src_start, n)) return; @@ -5,10 +12,3 @@ memcpy(dst->data + dst_start, src->data + src_start, n); } - -int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) -{ - if (chunk == NULL) return 0; - - return start <= chunk->length && n <= chunk->length - start; -} -- diff -- # force-anchoring-heuristic: true @@ -1,14 +1,14 @@ +int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) +{ + if (chunk == NULL) return 0; + + return start <= chunk->length && n <= chunk->length - start; +} + void Chunk_copy(Chunk *src, size_t src_start, Chunk *dst, size_t dst_start, size_t n) { if (!Chunk_bounds_check(src, src_start, n)) return; if (!Chunk_bounds_check(dst, dst_start, n)) return; memcpy(dst->data + dst_start, src->data + src_start, n); -} - -int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) -{ - if (chunk == NULL) return 0; - - return start <= chunk->length && n <= chunk->length - start; } -- diff -- # fast: true @@ -1,14 +1,14 @@ +int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) +{ + if (chunk == NULL) return 0; + + return start <= chunk->length && n <= chunk->length - start; +} + void Chunk_copy(Chunk *src, size_t src_start, Chunk *dst, size_t dst_start, size_t n) { if (!Chunk_bounds_check(src, src_start, n)) return; if (!Chunk_bounds_check(dst, dst_start, n)) return; memcpy(dst->data + dst_start, src->data + src_start, n); -} - -int Chunk_bounds_check(Chunk *chunk, size_t start, size_t n) -{ - if (chunk == NULL) return 0; - - return start <= chunk->length && n <= chunk->length - start; } diff-1.0.1/textdiff/testdata/frobnitz.test000066400000000000000000000066051516001707200206130ustar00rootroot00000000000000From https://vimways.org/2018/the-power-of-diff/ -- x -- #include // Frobs foo heartily int frobnitz(int foo) { int i; for(i = 0; i < 10; i++) { printf("Your answer is: "); printf("%d\n", foo); } } int fact(int n) { if(n > 1) { return fact(n-1) * n; } return 1; } int main(int argc, char **argv) { frobnitz(fact(10)); } -- y -- #include int fib(int n) { if(n > 2) { return fib(n-1) + fib(n-2); } return 1; } // Frobs foo heartily int frobnitz(int foo) { int i; for(i = 0; i < 10; i++) { printf("%d\n", foo); } } int main(int argc, char **argv) { frobnitz(fib(10)); } -- diff -- @@ -1,26 +1,25 @@ #include +int fib(int n) +{ + if(n > 2) + { + return fib(n-1) + fib(n-2); + } + return 1; +} + // Frobs foo heartily int frobnitz(int foo) { int i; for(i = 0; i < 10; i++) { - printf("Your answer is: "); printf("%d\n", foo); - } -} - -int fact(int n) -{ - if(n > 1) - { - return fact(n-1) * n; } - return 1; } int main(int argc, char **argv) { - frobnitz(fact(10)); + frobnitz(fib(10)); } -- diff -- # indent-heuristic: true @@ -1,26 +1,25 @@ #include +int fib(int n) +{ + if(n > 2) + { + return fib(n-1) + fib(n-2); + } + return 1; +} + // Frobs foo heartily int frobnitz(int foo) { int i; for(i = 0; i < 10; i++) { - printf("Your answer is: "); printf("%d\n", foo); } } -int fact(int n) -{ - if(n > 1) - { - return fact(n-1) * n; - } - return 1; -} - int main(int argc, char **argv) { - frobnitz(fact(10)); + frobnitz(fib(10)); } -- diff -- # force-anchoring-heuristic: true @@ -1,26 +1,25 @@ #include +int fib(int n) +{ + if(n > 2) + { + return fib(n-1) + fib(n-2); + } + return 1; +} + // Frobs foo heartily int frobnitz(int foo) { int i; for(i = 0; i < 10; i++) { - printf("Your answer is: "); printf("%d\n", foo); } -} - -int fact(int n) -{ - if(n > 1) - { - return fact(n-1) * n; - } - return 1; } int main(int argc, char **argv) { - frobnitz(fact(10)); + frobnitz(fib(10)); } -- diff -- # force-anchoring-heuristic: true # indent-heuristic: true @@ -1,26 +1,25 @@ #include +int fib(int n) +{ + if(n > 2) + { + return fib(n-1) + fib(n-2); + } + return 1; +} + // Frobs foo heartily int frobnitz(int foo) { int i; for(i = 0; i < 10; i++) { - printf("Your answer is: "); printf("%d\n", foo); } } -int fact(int n) -{ - if(n > 1) - { - return fact(n-1) * n; - } - return 1; -} - int main(int argc, char **argv) { - frobnitz(fact(10)); + frobnitz(fib(10)); } -- diff -- # fast: true # indent-heuristic: true @@ -1,26 +1,25 @@ #include +int fib(int n) +{ + if(n > 2) + { + return fib(n-1) + fib(n-2); + } + return 1; +} + // Frobs foo heartily int frobnitz(int foo) { int i; for(i = 0; i < 10; i++) { - printf("Your answer is: "); printf("%d\n", foo); } } -int fact(int n) -{ - if(n > 1) - { - return fact(n-1) * n; - } - return 1; -} - int main(int argc, char **argv) { - frobnitz(fact(10)); + frobnitz(fib(10)); } diff-1.0.1/textdiff/testdata/get_image_icon.test000066400000000000000000000074601516001707200217070ustar00rootroot00000000000000From: Nugroho, Y.S., Hata, H. & Matsumoto, K. How different are different diff algorithms in Git?. Empir Software Eng 25, 790-823 (2020). https://doi.org/10.1007/s10664-019-09772-z -- x -- ... other code here ... */ public static ImageIcon getImageIcon(String path) { java.net.URL imgURL = GuiImporter.class.getResource(path); if (imgURL != null) { return new ImageIcon(imgURL); } else { log.error("Couldn't find icon: " + imgURL) } return null; } /** ... other code here ... -- y -- ... other code here ... */ public static ImageIcon getImageIcon(String path) { if (path == null) { log.error("Icon path is null"); return null; } java.net.URL imgURL = GuiImporter.class.getResource(path); if (imgURL == null) { log.error("Couldn't find icon: " + imgURL) return null; } else return new ImageIcon(imgURL); } /** ... other code here ... -- diff -- @@ -2,17 +2,21 @@ */ public static ImageIcon getImageIcon(String path) { + if (path == null) + { + log.error("Icon path is null"); + return null; + } + java.net.URL imgURL = GuiImporter.class.getResource(path); - if (imgURL != null) + if (imgURL == null) { - return new ImageIcon(imgURL); + log.error("Couldn't find icon: " + imgURL) + return null; } else - { - log.error("Couldn't find icon: " + imgURL) - } - return null; + return new ImageIcon(imgURL); } /** -- diff -- # indent-heuristic: true @@ -2,17 +2,21 @@ */ public static ImageIcon getImageIcon(String path) { + if (path == null) + { + log.error("Icon path is null"); + return null; + } + java.net.URL imgURL = GuiImporter.class.getResource(path); - if (imgURL != null) + if (imgURL == null) { - return new ImageIcon(imgURL); + log.error("Couldn't find icon: " + imgURL) + return null; } else - { - log.error("Couldn't find icon: " + imgURL) - } - return null; + return new ImageIcon(imgURL); } /** -- diff -- # force-anchoring-heuristic: true @@ -2,17 +2,21 @@ */ public static ImageIcon getImageIcon(String path) { + if (path == null) + { + log.error("Icon path is null"); + return null; + } + java.net.URL imgURL = GuiImporter.class.getResource(path); - if (imgURL != null) + if (imgURL == null) { - return new ImageIcon(imgURL); - } - else - { log.error("Couldn't find icon: " + imgURL) + return null; } - return null; + else + return new ImageIcon(imgURL); } /** -- diff -- # fast: true @@ -2,17 +2,21 @@ */ public static ImageIcon getImageIcon(String path) { + if (path == null) + { + log.error("Icon path is null"); + return null; + } + java.net.URL imgURL = GuiImporter.class.getResource(path); - if (imgURL != null) + if (imgURL == null) { - return new ImageIcon(imgURL); - } - else - { log.error("Couldn't find icon: " + imgURL) - } - return null; + return null; + } + else + return new ImageIcon(imgURL); } /** -- diff -- # force-anchoring-heuristic: true # indent-heuristic: true @@ -2,17 +2,21 @@ */ public static ImageIcon getImageIcon(String path) { + if (path == null) + { + log.error("Icon path is null"); + return null; + } + java.net.URL imgURL = GuiImporter.class.getResource(path); - if (imgURL != null) - { - return new ImageIcon(imgURL); - } - else + if (imgURL == null) { log.error("Couldn't find icon: " + imgURL) + return null; } - return null; + else + return new ImageIcon(imgURL); } /** diff-1.0.1/textdiff/testdata/go.mod000066400000000000000000000000611516001707200171510ustar00rootroot00000000000000module znkr.io/diff/textdiff/testdata go 1.24.5 go_44563340cc6b6e3b8b1bf8f510dad9ee3f075633_src_cmd_compile_internal_ssa_rewriteAMD64.go.test000066400000000000000000066233331516001707200356400ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit 44563340cc6b6e3b8b1bf8f510dad9ee3f075633 file src/cmd/compile/internal/ssa/rewriteAMD64.go -- x -- // Code generated from gen/AMD64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "internal/buildcfg" import "math" import "cmd/internal/obj" import "cmd/compile/internal/types" func rewriteValueAMD64(v *Value) bool { switch v.Op { case OpAMD64ADCQ: return rewriteValueAMD64_OpAMD64ADCQ(v) case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst(v) case OpAMD64ADDL: return rewriteValueAMD64_OpAMD64ADDL(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst(v) case OpAMD64ADDLconstmodify: return rewriteValueAMD64_OpAMD64ADDLconstmodify(v) case OpAMD64ADDLload: return rewriteValueAMD64_OpAMD64ADDLload(v) case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify(v) case OpAMD64ADDQ: return rewriteValueAMD64_OpAMD64ADDQ(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry(v) case OpAMD64ADDQconst: return rewriteValueAMD64_OpAMD64ADDQconst(v) case OpAMD64ADDQconstmodify: return rewriteValueAMD64_OpAMD64ADDQconstmodify(v) case OpAMD64ADDQload: return rewriteValueAMD64_OpAMD64ADDQload(v) case OpAMD64ADDQmodify: return rewriteValueAMD64_OpAMD64ADDQmodify(v) case OpAMD64ADDSD: return rewriteValueAMD64_OpAMD64ADDSD(v) case OpAMD64ADDSDload: return rewriteValueAMD64_OpAMD64ADDSDload(v) case OpAMD64ADDSS: return rewriteValueAMD64_OpAMD64ADDSS(v) case OpAMD64ADDSSload: return rewriteValueAMD64_OpAMD64ADDSSload(v) case OpAMD64ANDL: return rewriteValueAMD64_OpAMD64ANDL(v) case OpAMD64ANDLconst: return rewriteValueAMD64_OpAMD64ANDLconst(v) case OpAMD64ANDLconstmodify: return rewriteValueAMD64_OpAMD64ANDLconstmodify(v) case OpAMD64ANDLload: return rewriteValueAMD64_OpAMD64ANDLload(v) case OpAMD64ANDLmodify: return rewriteValueAMD64_OpAMD64ANDLmodify(v) case OpAMD64ANDNL: return rewriteValueAMD64_OpAMD64ANDNL(v) case OpAMD64ANDNQ: return rewriteValueAMD64_OpAMD64ANDNQ(v) case OpAMD64ANDQ: return rewriteValueAMD64_OpAMD64ANDQ(v) case OpAMD64ANDQconst: return rewriteValueAMD64_OpAMD64ANDQconst(v) case OpAMD64ANDQconstmodify: return rewriteValueAMD64_OpAMD64ANDQconstmodify(v) case OpAMD64ANDQload: return rewriteValueAMD64_OpAMD64ANDQload(v) case OpAMD64ANDQmodify: return rewriteValueAMD64_OpAMD64ANDQmodify(v) case OpAMD64BSFQ: return rewriteValueAMD64_OpAMD64BSFQ(v) case OpAMD64BSWAPL: return rewriteValueAMD64_OpAMD64BSWAPL(v) case OpAMD64BSWAPQ: return rewriteValueAMD64_OpAMD64BSWAPQ(v) case OpAMD64BTCLconst: return rewriteValueAMD64_OpAMD64BTCLconst(v) case OpAMD64BTCQconst: return rewriteValueAMD64_OpAMD64BTCQconst(v) case OpAMD64BTLconst: return rewriteValueAMD64_OpAMD64BTLconst(v) case OpAMD64BTQconst: return rewriteValueAMD64_OpAMD64BTQconst(v) case OpAMD64BTRLconst: return rewriteValueAMD64_OpAMD64BTRLconst(v) case OpAMD64BTRQconst: return rewriteValueAMD64_OpAMD64BTRQconst(v) case OpAMD64BTSLconst: return rewriteValueAMD64_OpAMD64BTSLconst(v) case OpAMD64BTSQconst: return rewriteValueAMD64_OpAMD64BTSQconst(v) case OpAMD64CMOVLCC: return rewriteValueAMD64_OpAMD64CMOVLCC(v) case OpAMD64CMOVLCS: return rewriteValueAMD64_OpAMD64CMOVLCS(v) case OpAMD64CMOVLEQ: return rewriteValueAMD64_OpAMD64CMOVLEQ(v) case OpAMD64CMOVLGE: return rewriteValueAMD64_OpAMD64CMOVLGE(v) case OpAMD64CMOVLGT: return rewriteValueAMD64_OpAMD64CMOVLGT(v) case OpAMD64CMOVLHI: return rewriteValueAMD64_OpAMD64CMOVLHI(v) case OpAMD64CMOVLLE: return rewriteValueAMD64_OpAMD64CMOVLLE(v) case OpAMD64CMOVLLS: return rewriteValueAMD64_OpAMD64CMOVLLS(v) case OpAMD64CMOVLLT: return rewriteValueAMD64_OpAMD64CMOVLLT(v) case OpAMD64CMOVLNE: return rewriteValueAMD64_OpAMD64CMOVLNE(v) case OpAMD64CMOVQCC: return rewriteValueAMD64_OpAMD64CMOVQCC(v) case OpAMD64CMOVQCS: return rewriteValueAMD64_OpAMD64CMOVQCS(v) case OpAMD64CMOVQEQ: return rewriteValueAMD64_OpAMD64CMOVQEQ(v) case OpAMD64CMOVQGE: return rewriteValueAMD64_OpAMD64CMOVQGE(v) case OpAMD64CMOVQGT: return rewriteValueAMD64_OpAMD64CMOVQGT(v) case OpAMD64CMOVQHI: return rewriteValueAMD64_OpAMD64CMOVQHI(v) case OpAMD64CMOVQLE: return rewriteValueAMD64_OpAMD64CMOVQLE(v) case OpAMD64CMOVQLS: return rewriteValueAMD64_OpAMD64CMOVQLS(v) case OpAMD64CMOVQLT: return rewriteValueAMD64_OpAMD64CMOVQLT(v) case OpAMD64CMOVQNE: return rewriteValueAMD64_OpAMD64CMOVQNE(v) case OpAMD64CMOVWCC: return rewriteValueAMD64_OpAMD64CMOVWCC(v) case OpAMD64CMOVWCS: return rewriteValueAMD64_OpAMD64CMOVWCS(v) case OpAMD64CMOVWEQ: return rewriteValueAMD64_OpAMD64CMOVWEQ(v) case OpAMD64CMOVWGE: return rewriteValueAMD64_OpAMD64CMOVWGE(v) case OpAMD64CMOVWGT: return rewriteValueAMD64_OpAMD64CMOVWGT(v) case OpAMD64CMOVWHI: return rewriteValueAMD64_OpAMD64CMOVWHI(v) case OpAMD64CMOVWLE: return rewriteValueAMD64_OpAMD64CMOVWLE(v) case OpAMD64CMOVWLS: return rewriteValueAMD64_OpAMD64CMOVWLS(v) case OpAMD64CMOVWLT: return rewriteValueAMD64_OpAMD64CMOVWLT(v) case OpAMD64CMOVWNE: return rewriteValueAMD64_OpAMD64CMOVWNE(v) case OpAMD64CMPB: return rewriteValueAMD64_OpAMD64CMPB(v) case OpAMD64CMPBconst: return rewriteValueAMD64_OpAMD64CMPBconst(v) case OpAMD64CMPBconstload: return rewriteValueAMD64_OpAMD64CMPBconstload(v) case OpAMD64CMPBload: return rewriteValueAMD64_OpAMD64CMPBload(v) case OpAMD64CMPL: return rewriteValueAMD64_OpAMD64CMPL(v) case OpAMD64CMPLconst: return rewriteValueAMD64_OpAMD64CMPLconst(v) case OpAMD64CMPLconstload: return rewriteValueAMD64_OpAMD64CMPLconstload(v) case OpAMD64CMPLload: return rewriteValueAMD64_OpAMD64CMPLload(v) case OpAMD64CMPQ: return rewriteValueAMD64_OpAMD64CMPQ(v) case OpAMD64CMPQconst: return rewriteValueAMD64_OpAMD64CMPQconst(v) case OpAMD64CMPQconstload: return rewriteValueAMD64_OpAMD64CMPQconstload(v) case OpAMD64CMPQload: return rewriteValueAMD64_OpAMD64CMPQload(v) case OpAMD64CMPW: return rewriteValueAMD64_OpAMD64CMPW(v) case OpAMD64CMPWconst: return rewriteValueAMD64_OpAMD64CMPWconst(v) case OpAMD64CMPWconstload: return rewriteValueAMD64_OpAMD64CMPWconstload(v) case OpAMD64CMPWload: return rewriteValueAMD64_OpAMD64CMPWload(v) case OpAMD64CMPXCHGLlock: return rewriteValueAMD64_OpAMD64CMPXCHGLlock(v) case OpAMD64CMPXCHGQlock: return rewriteValueAMD64_OpAMD64CMPXCHGQlock(v) case OpAMD64DIVSD: return rewriteValueAMD64_OpAMD64DIVSD(v) case OpAMD64DIVSDload: return rewriteValueAMD64_OpAMD64DIVSDload(v) case OpAMD64DIVSS: return rewriteValueAMD64_OpAMD64DIVSS(v) case OpAMD64DIVSSload: return rewriteValueAMD64_OpAMD64DIVSSload(v) case OpAMD64HMULL: return rewriteValueAMD64_OpAMD64HMULL(v) case OpAMD64HMULLU: return rewriteValueAMD64_OpAMD64HMULLU(v) case OpAMD64HMULQ: return rewriteValueAMD64_OpAMD64HMULQ(v) case OpAMD64HMULQU: return rewriteValueAMD64_OpAMD64HMULQU(v) case OpAMD64LEAL: return rewriteValueAMD64_OpAMD64LEAL(v) case OpAMD64LEAL1: return rewriteValueAMD64_OpAMD64LEAL1(v) case OpAMD64LEAL2: return rewriteValueAMD64_OpAMD64LEAL2(v) case OpAMD64LEAL4: return rewriteValueAMD64_OpAMD64LEAL4(v) case OpAMD64LEAL8: return rewriteValueAMD64_OpAMD64LEAL8(v) case OpAMD64LEAQ: return rewriteValueAMD64_OpAMD64LEAQ(v) case OpAMD64LEAQ1: return rewriteValueAMD64_OpAMD64LEAQ1(v) case OpAMD64LEAQ2: return rewriteValueAMD64_OpAMD64LEAQ2(v) case OpAMD64LEAQ4: return rewriteValueAMD64_OpAMD64LEAQ4(v) case OpAMD64LEAQ8: return rewriteValueAMD64_OpAMD64LEAQ8(v) case OpAMD64MOVBELstore: return rewriteValueAMD64_OpAMD64MOVBELstore(v) case OpAMD64MOVBEQstore: return rewriteValueAMD64_OpAMD64MOVBEQstore(v) case OpAMD64MOVBEWstore: return rewriteValueAMD64_OpAMD64MOVBEWstore(v) case OpAMD64MOVBQSX: return rewriteValueAMD64_OpAMD64MOVBQSX(v) case OpAMD64MOVBQSXload: return rewriteValueAMD64_OpAMD64MOVBQSXload(v) case OpAMD64MOVBQZX: return rewriteValueAMD64_OpAMD64MOVBQZX(v) case OpAMD64MOVBatomicload: return rewriteValueAMD64_OpAMD64MOVBatomicload(v) case OpAMD64MOVBload: return rewriteValueAMD64_OpAMD64MOVBload(v) case OpAMD64MOVBstore: return rewriteValueAMD64_OpAMD64MOVBstore(v) case OpAMD64MOVBstoreconst: return rewriteValueAMD64_OpAMD64MOVBstoreconst(v) case OpAMD64MOVLQSX: return rewriteValueAMD64_OpAMD64MOVLQSX(v) case OpAMD64MOVLQSXload: return rewriteValueAMD64_OpAMD64MOVLQSXload(v) case OpAMD64MOVLQZX: return rewriteValueAMD64_OpAMD64MOVLQZX(v) case OpAMD64MOVLatomicload: return rewriteValueAMD64_OpAMD64MOVLatomicload(v) case OpAMD64MOVLf2i: return rewriteValueAMD64_OpAMD64MOVLf2i(v) case OpAMD64MOVLi2f: return rewriteValueAMD64_OpAMD64MOVLi2f(v) case OpAMD64MOVLload: return rewriteValueAMD64_OpAMD64MOVLload(v) case OpAMD64MOVLstore: return rewriteValueAMD64_OpAMD64MOVLstore(v) case OpAMD64MOVLstoreconst: return rewriteValueAMD64_OpAMD64MOVLstoreconst(v) case OpAMD64MOVOload: return rewriteValueAMD64_OpAMD64MOVOload(v) case OpAMD64MOVOstore: return rewriteValueAMD64_OpAMD64MOVOstore(v) case OpAMD64MOVOstoreconst: return rewriteValueAMD64_OpAMD64MOVOstoreconst(v) case OpAMD64MOVQatomicload: return rewriteValueAMD64_OpAMD64MOVQatomicload(v) case OpAMD64MOVQf2i: return rewriteValueAMD64_OpAMD64MOVQf2i(v) case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f(v) case OpAMD64MOVQload: return rewriteValueAMD64_OpAMD64MOVQload(v) case OpAMD64MOVQstore: return rewriteValueAMD64_OpAMD64MOVQstore(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst(v) case OpAMD64MOVSDload: return rewriteValueAMD64_OpAMD64MOVSDload(v) case OpAMD64MOVSDstore: return rewriteValueAMD64_OpAMD64MOVSDstore(v) case OpAMD64MOVSSload: return rewriteValueAMD64_OpAMD64MOVSSload(v) case OpAMD64MOVSSstore: return rewriteValueAMD64_OpAMD64MOVSSstore(v) case OpAMD64MOVWQSX: return rewriteValueAMD64_OpAMD64MOVWQSX(v) case OpAMD64MOVWQSXload: return rewriteValueAMD64_OpAMD64MOVWQSXload(v) case OpAMD64MOVWQZX: return rewriteValueAMD64_OpAMD64MOVWQZX(v) case OpAMD64MOVWload: return rewriteValueAMD64_OpAMD64MOVWload(v) case OpAMD64MOVWstore: return rewriteValueAMD64_OpAMD64MOVWstore(v) case OpAMD64MOVWstoreconst: return rewriteValueAMD64_OpAMD64MOVWstoreconst(v) case OpAMD64MULL: return rewriteValueAMD64_OpAMD64MULL(v) case OpAMD64MULLconst: return rewriteValueAMD64_OpAMD64MULLconst(v) case OpAMD64MULQ: return rewriteValueAMD64_OpAMD64MULQ(v) case OpAMD64MULQconst: return rewriteValueAMD64_OpAMD64MULQconst(v) case OpAMD64MULSD: return rewriteValueAMD64_OpAMD64MULSD(v) case OpAMD64MULSDload: return rewriteValueAMD64_OpAMD64MULSDload(v) case OpAMD64MULSS: return rewriteValueAMD64_OpAMD64MULSS(v) case OpAMD64MULSSload: return rewriteValueAMD64_OpAMD64MULSSload(v) case OpAMD64NEGL: return rewriteValueAMD64_OpAMD64NEGL(v) case OpAMD64NEGQ: return rewriteValueAMD64_OpAMD64NEGQ(v) case OpAMD64NOTL: return rewriteValueAMD64_OpAMD64NOTL(v) case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ(v) case OpAMD64ORL: return rewriteValueAMD64_OpAMD64ORL(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst(v) case OpAMD64ORLconstmodify: return rewriteValueAMD64_OpAMD64ORLconstmodify(v) case OpAMD64ORLload: return rewriteValueAMD64_OpAMD64ORLload(v) case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify(v) case OpAMD64ORQ: return rewriteValueAMD64_OpAMD64ORQ(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst(v) case OpAMD64ORQconstmodify: return rewriteValueAMD64_OpAMD64ORQconstmodify(v) case OpAMD64ORQload: return rewriteValueAMD64_OpAMD64ORQload(v) case OpAMD64ORQmodify: return rewriteValueAMD64_OpAMD64ORQmodify(v) case OpAMD64ROLB: return rewriteValueAMD64_OpAMD64ROLB(v) case OpAMD64ROLBconst: return rewriteValueAMD64_OpAMD64ROLBconst(v) case OpAMD64ROLL: return rewriteValueAMD64_OpAMD64ROLL(v) case OpAMD64ROLLconst: return rewriteValueAMD64_OpAMD64ROLLconst(v) case OpAMD64ROLQ: return rewriteValueAMD64_OpAMD64ROLQ(v) case OpAMD64ROLQconst: return rewriteValueAMD64_OpAMD64ROLQconst(v) case OpAMD64ROLW: return rewriteValueAMD64_OpAMD64ROLW(v) case OpAMD64ROLWconst: return rewriteValueAMD64_OpAMD64ROLWconst(v) case OpAMD64RORB: return rewriteValueAMD64_OpAMD64RORB(v) case OpAMD64RORL: return rewriteValueAMD64_OpAMD64RORL(v) case OpAMD64RORQ: return rewriteValueAMD64_OpAMD64RORQ(v) case OpAMD64RORW: return rewriteValueAMD64_OpAMD64RORW(v) case OpAMD64SARB: return rewriteValueAMD64_OpAMD64SARB(v) case OpAMD64SARBconst: return rewriteValueAMD64_OpAMD64SARBconst(v) case OpAMD64SARL: return rewriteValueAMD64_OpAMD64SARL(v) case OpAMD64SARLconst: return rewriteValueAMD64_OpAMD64SARLconst(v) case OpAMD64SARQ: return rewriteValueAMD64_OpAMD64SARQ(v) case OpAMD64SARQconst: return rewriteValueAMD64_OpAMD64SARQconst(v) case OpAMD64SARW: return rewriteValueAMD64_OpAMD64SARW(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst(v) case OpAMD64SARXL: return rewriteValueAMD64_OpAMD64SARXL(v) case OpAMD64SARXLload: return rewriteValueAMD64_OpAMD64SARXLload(v) case OpAMD64SARXQ: return rewriteValueAMD64_OpAMD64SARXQ(v) case OpAMD64SARXQload: return rewriteValueAMD64_OpAMD64SARXQload(v) case OpAMD64SBBLcarrymask: return rewriteValueAMD64_OpAMD64SBBLcarrymask(v) case OpAMD64SBBQ: return rewriteValueAMD64_OpAMD64SBBQ(v) case OpAMD64SBBQcarrymask: return rewriteValueAMD64_OpAMD64SBBQcarrymask(v) case OpAMD64SBBQconst: return rewriteValueAMD64_OpAMD64SBBQconst(v) case OpAMD64SETA: return rewriteValueAMD64_OpAMD64SETA(v) case OpAMD64SETAE: return rewriteValueAMD64_OpAMD64SETAE(v) case OpAMD64SETAEstore: return rewriteValueAMD64_OpAMD64SETAEstore(v) case OpAMD64SETAstore: return rewriteValueAMD64_OpAMD64SETAstore(v) case OpAMD64SETB: return rewriteValueAMD64_OpAMD64SETB(v) case OpAMD64SETBE: return rewriteValueAMD64_OpAMD64SETBE(v) case OpAMD64SETBEstore: return rewriteValueAMD64_OpAMD64SETBEstore(v) case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore(v) case OpAMD64SETEQ: return rewriteValueAMD64_OpAMD64SETEQ(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore(v) case OpAMD64SETG: return rewriteValueAMD64_OpAMD64SETG(v) case OpAMD64SETGE: return rewriteValueAMD64_OpAMD64SETGE(v) case OpAMD64SETGEstore: return rewriteValueAMD64_OpAMD64SETGEstore(v) case OpAMD64SETGstore: return rewriteValueAMD64_OpAMD64SETGstore(v) case OpAMD64SETL: return rewriteValueAMD64_OpAMD64SETL(v) case OpAMD64SETLE: return rewriteValueAMD64_OpAMD64SETLE(v) case OpAMD64SETLEstore: return rewriteValueAMD64_OpAMD64SETLEstore(v) case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore(v) case OpAMD64SETNE: return rewriteValueAMD64_OpAMD64SETNE(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore(v) case OpAMD64SHLL: return rewriteValueAMD64_OpAMD64SHLL(v) case OpAMD64SHLLconst: return rewriteValueAMD64_OpAMD64SHLLconst(v) case OpAMD64SHLQ: return rewriteValueAMD64_OpAMD64SHLQ(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst(v) case OpAMD64SHLXL: return rewriteValueAMD64_OpAMD64SHLXL(v) case OpAMD64SHLXLload: return rewriteValueAMD64_OpAMD64SHLXLload(v) case OpAMD64SHLXQ: return rewriteValueAMD64_OpAMD64SHLXQ(v) case OpAMD64SHLXQload: return rewriteValueAMD64_OpAMD64SHLXQload(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB(v) case OpAMD64SHRBconst: return rewriteValueAMD64_OpAMD64SHRBconst(v) case OpAMD64SHRL: return rewriteValueAMD64_OpAMD64SHRL(v) case OpAMD64SHRLconst: return rewriteValueAMD64_OpAMD64SHRLconst(v) case OpAMD64SHRQ: return rewriteValueAMD64_OpAMD64SHRQ(v) case OpAMD64SHRQconst: return rewriteValueAMD64_OpAMD64SHRQconst(v) case OpAMD64SHRW: return rewriteValueAMD64_OpAMD64SHRW(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst(v) case OpAMD64SHRXL: return rewriteValueAMD64_OpAMD64SHRXL(v) case OpAMD64SHRXLload: return rewriteValueAMD64_OpAMD64SHRXLload(v) case OpAMD64SHRXQ: return rewriteValueAMD64_OpAMD64SHRXQ(v) case OpAMD64SHRXQload: return rewriteValueAMD64_OpAMD64SHRXQload(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL(v) case OpAMD64SUBLconst: return rewriteValueAMD64_OpAMD64SUBLconst(v) case OpAMD64SUBLload: return rewriteValueAMD64_OpAMD64SUBLload(v) case OpAMD64SUBLmodify: return rewriteValueAMD64_OpAMD64SUBLmodify(v) case OpAMD64SUBQ: return rewriteValueAMD64_OpAMD64SUBQ(v) case OpAMD64SUBQborrow: return rewriteValueAMD64_OpAMD64SUBQborrow(v) case OpAMD64SUBQconst: return rewriteValueAMD64_OpAMD64SUBQconst(v) case OpAMD64SUBQload: return rewriteValueAMD64_OpAMD64SUBQload(v) case OpAMD64SUBQmodify: return rewriteValueAMD64_OpAMD64SUBQmodify(v) case OpAMD64SUBSD: return rewriteValueAMD64_OpAMD64SUBSD(v) case OpAMD64SUBSDload: return rewriteValueAMD64_OpAMD64SUBSDload(v) case OpAMD64SUBSS: return rewriteValueAMD64_OpAMD64SUBSS(v) case OpAMD64SUBSSload: return rewriteValueAMD64_OpAMD64SUBSSload(v) case OpAMD64TESTB: return rewriteValueAMD64_OpAMD64TESTB(v) case OpAMD64TESTBconst: return rewriteValueAMD64_OpAMD64TESTBconst(v) case OpAMD64TESTL: return rewriteValueAMD64_OpAMD64TESTL(v) case OpAMD64TESTLconst: return rewriteValueAMD64_OpAMD64TESTLconst(v) case OpAMD64TESTQ: return rewriteValueAMD64_OpAMD64TESTQ(v) case OpAMD64TESTQconst: return rewriteValueAMD64_OpAMD64TESTQconst(v) case OpAMD64TESTW: return rewriteValueAMD64_OpAMD64TESTW(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock(v) case OpAMD64XADDQlock: return rewriteValueAMD64_OpAMD64XADDQlock(v) case OpAMD64XCHGL: return rewriteValueAMD64_OpAMD64XCHGL(v) case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ(v) case OpAMD64XORL: return rewriteValueAMD64_OpAMD64XORL(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst(v) case OpAMD64XORLconstmodify: return rewriteValueAMD64_OpAMD64XORLconstmodify(v) case OpAMD64XORLload: return rewriteValueAMD64_OpAMD64XORLload(v) case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify(v) case OpAMD64XORQ: return rewriteValueAMD64_OpAMD64XORQ(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst(v) case OpAMD64XORQconstmodify: return rewriteValueAMD64_OpAMD64XORQconstmodify(v) case OpAMD64XORQload: return rewriteValueAMD64_OpAMD64XORQload(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify(v) case OpAdd16: v.Op = OpAMD64ADDL return true case OpAdd32: v.Op = OpAMD64ADDL return true case OpAdd32F: v.Op = OpAMD64ADDSS return true case OpAdd64: v.Op = OpAMD64ADDQ return true case OpAdd64F: v.Op = OpAMD64ADDSD return true case OpAdd8: v.Op = OpAMD64ADDL return true case OpAddPtr: v.Op = OpAMD64ADDQ return true case OpAddr: return rewriteValueAMD64_OpAddr(v) case OpAnd16: v.Op = OpAMD64ANDL return true case OpAnd32: v.Op = OpAMD64ANDL return true case OpAnd64: v.Op = OpAMD64ANDQ return true case OpAnd8: v.Op = OpAMD64ANDL return true case OpAndB: v.Op = OpAMD64ANDL return true case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32(v) case OpAtomicAdd64: return rewriteValueAMD64_OpAtomicAdd64(v) case OpAtomicAnd32: return rewriteValueAMD64_OpAtomicAnd32(v) case OpAtomicAnd8: return rewriteValueAMD64_OpAtomicAnd8(v) case OpAtomicCompareAndSwap32: return rewriteValueAMD64_OpAtomicCompareAndSwap32(v) case OpAtomicCompareAndSwap64: return rewriteValueAMD64_OpAtomicCompareAndSwap64(v) case OpAtomicExchange32: return rewriteValueAMD64_OpAtomicExchange32(v) case OpAtomicExchange64: return rewriteValueAMD64_OpAtomicExchange64(v) case OpAtomicLoad32: return rewriteValueAMD64_OpAtomicLoad32(v) case OpAtomicLoad64: return rewriteValueAMD64_OpAtomicLoad64(v) case OpAtomicLoad8: return rewriteValueAMD64_OpAtomicLoad8(v) case OpAtomicLoadPtr: return rewriteValueAMD64_OpAtomicLoadPtr(v) case OpAtomicOr32: return rewriteValueAMD64_OpAtomicOr32(v) case OpAtomicOr8: return rewriteValueAMD64_OpAtomicOr8(v) case OpAtomicStore32: return rewriteValueAMD64_OpAtomicStore32(v) case OpAtomicStore64: return rewriteValueAMD64_OpAtomicStore64(v) case OpAtomicStore8: return rewriteValueAMD64_OpAtomicStore8(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB(v) case OpAvg64u: v.Op = OpAMD64AVGQU return true case OpBitLen16: return rewriteValueAMD64_OpBitLen16(v) case OpBitLen32: return rewriteValueAMD64_OpBitLen32(v) case OpBitLen64: return rewriteValueAMD64_OpBitLen64(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8(v) case OpBswap32: v.Op = OpAMD64BSWAPL return true case OpBswap64: v.Op = OpAMD64BSWAPQ return true case OpCeil: return rewriteValueAMD64_OpCeil(v) case OpClosureCall: v.Op = OpAMD64CALLclosure return true case OpCom16: v.Op = OpAMD64NOTL return true case OpCom32: v.Op = OpAMD64NOTL return true case OpCom64: v.Op = OpAMD64NOTQ return true case OpCom8: v.Op = OpAMD64NOTL return true case OpCondSelect: return rewriteValueAMD64_OpCondSelect(v) case OpConst16: return rewriteValueAMD64_OpConst16(v) case OpConst32: v.Op = OpAMD64MOVLconst return true case OpConst32F: v.Op = OpAMD64MOVSSconst return true case OpConst64: v.Op = OpAMD64MOVQconst return true case OpConst64F: v.Op = OpAMD64MOVSDconst return true case OpConst8: return rewriteValueAMD64_OpConst8(v) case OpConstBool: return rewriteValueAMD64_OpConstBool(v) case OpConstNil: return rewriteValueAMD64_OpConstNil(v) case OpCtz16: return rewriteValueAMD64_OpCtz16(v) case OpCtz16NonZero: return rewriteValueAMD64_OpCtz16NonZero(v) case OpCtz32: return rewriteValueAMD64_OpCtz32(v) case OpCtz32NonZero: return rewriteValueAMD64_OpCtz32NonZero(v) case OpCtz64: return rewriteValueAMD64_OpCtz64(v) case OpCtz64NonZero: return rewriteValueAMD64_OpCtz64NonZero(v) case OpCtz8: return rewriteValueAMD64_OpCtz8(v) case OpCtz8NonZero: return rewriteValueAMD64_OpCtz8NonZero(v) case OpCvt32Fto32: v.Op = OpAMD64CVTTSS2SL return true case OpCvt32Fto64: v.Op = OpAMD64CVTTSS2SQ return true case OpCvt32Fto64F: v.Op = OpAMD64CVTSS2SD return true case OpCvt32to32F: v.Op = OpAMD64CVTSL2SS return true case OpCvt32to64F: v.Op = OpAMD64CVTSL2SD return true case OpCvt64Fto32: v.Op = OpAMD64CVTTSD2SL return true case OpCvt64Fto32F: v.Op = OpAMD64CVTSD2SS return true case OpCvt64Fto64: v.Op = OpAMD64CVTTSD2SQ return true case OpCvt64to32F: v.Op = OpAMD64CVTSQ2SS return true case OpCvt64to64F: v.Op = OpAMD64CVTSQ2SD return true case OpCvtBoolToUint8: v.Op = OpCopy return true case OpDiv128u: v.Op = OpAMD64DIVQU2 return true case OpDiv16: return rewriteValueAMD64_OpDiv16(v) case OpDiv16u: return rewriteValueAMD64_OpDiv16u(v) case OpDiv32: return rewriteValueAMD64_OpDiv32(v) case OpDiv32F: v.Op = OpAMD64DIVSS return true case OpDiv32u: return rewriteValueAMD64_OpDiv32u(v) case OpDiv64: return rewriteValueAMD64_OpDiv64(v) case OpDiv64F: v.Op = OpAMD64DIVSD return true case OpDiv64u: return rewriteValueAMD64_OpDiv64u(v) case OpDiv8: return rewriteValueAMD64_OpDiv8(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u(v) case OpEq16: return rewriteValueAMD64_OpEq16(v) case OpEq32: return rewriteValueAMD64_OpEq32(v) case OpEq32F: return rewriteValueAMD64_OpEq32F(v) case OpEq64: return rewriteValueAMD64_OpEq64(v) case OpEq64F: return rewriteValueAMD64_OpEq64F(v) case OpEq8: return rewriteValueAMD64_OpEq8(v) case OpEqB: return rewriteValueAMD64_OpEqB(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr(v) case OpFMA: return rewriteValueAMD64_OpFMA(v) case OpFloor: return rewriteValueAMD64_OpFloor(v) case OpGetCallerPC: v.Op = OpAMD64LoweredGetCallerPC return true case OpGetCallerSP: v.Op = OpAMD64LoweredGetCallerSP return true case OpGetClosurePtr: v.Op = OpAMD64LoweredGetClosurePtr return true case OpGetG: return rewriteValueAMD64_OpGetG(v) case OpHasCPUFeature: return rewriteValueAMD64_OpHasCPUFeature(v) case OpHmul32: v.Op = OpAMD64HMULL return true case OpHmul32u: v.Op = OpAMD64HMULLU return true case OpHmul64: v.Op = OpAMD64HMULQ return true case OpHmul64u: v.Op = OpAMD64HMULQU return true case OpInterCall: v.Op = OpAMD64CALLinter return true case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueAMD64_OpIsSliceInBounds(v) case OpLeq16: return rewriteValueAMD64_OpLeq16(v) case OpLeq16U: return rewriteValueAMD64_OpLeq16U(v) case OpLeq32: return rewriteValueAMD64_OpLeq32(v) case OpLeq32F: return rewriteValueAMD64_OpLeq32F(v) case OpLeq32U: return rewriteValueAMD64_OpLeq32U(v) case OpLeq64: return rewriteValueAMD64_OpLeq64(v) case OpLeq64F: return rewriteValueAMD64_OpLeq64F(v) case OpLeq64U: return rewriteValueAMD64_OpLeq64U(v) case OpLeq8: return rewriteValueAMD64_OpLeq8(v) case OpLeq8U: return rewriteValueAMD64_OpLeq8U(v) case OpLess16: return rewriteValueAMD64_OpLess16(v) case OpLess16U: return rewriteValueAMD64_OpLess16U(v) case OpLess32: return rewriteValueAMD64_OpLess32(v) case OpLess32F: return rewriteValueAMD64_OpLess32F(v) case OpLess32U: return rewriteValueAMD64_OpLess32U(v) case OpLess64: return rewriteValueAMD64_OpLess64(v) case OpLess64F: return rewriteValueAMD64_OpLess64F(v) case OpLess64U: return rewriteValueAMD64_OpLess64U(v) case OpLess8: return rewriteValueAMD64_OpLess8(v) case OpLess8U: return rewriteValueAMD64_OpLess8U(v) case OpLoad: return rewriteValueAMD64_OpLoad(v) case OpLocalAddr: return rewriteValueAMD64_OpLocalAddr(v) case OpLsh16x16: return rewriteValueAMD64_OpLsh16x16(v) case OpLsh16x32: return rewriteValueAMD64_OpLsh16x32(v) case OpLsh16x64: return rewriteValueAMD64_OpLsh16x64(v) case OpLsh16x8: return rewriteValueAMD64_OpLsh16x8(v) case OpLsh32x16: return rewriteValueAMD64_OpLsh32x16(v) case OpLsh32x32: return rewriteValueAMD64_OpLsh32x32(v) case OpLsh32x64: return rewriteValueAMD64_OpLsh32x64(v) case OpLsh32x8: return rewriteValueAMD64_OpLsh32x8(v) case OpLsh64x16: return rewriteValueAMD64_OpLsh64x16(v) case OpLsh64x32: return rewriteValueAMD64_OpLsh64x32(v) case OpLsh64x64: return rewriteValueAMD64_OpLsh64x64(v) case OpLsh64x8: return rewriteValueAMD64_OpLsh64x8(v) case OpLsh8x16: return rewriteValueAMD64_OpLsh8x16(v) case OpLsh8x32: return rewriteValueAMD64_OpLsh8x32(v) case OpLsh8x64: return rewriteValueAMD64_OpLsh8x64(v) case OpLsh8x8: return rewriteValueAMD64_OpLsh8x8(v) case OpMod16: return rewriteValueAMD64_OpMod16(v) case OpMod16u: return rewriteValueAMD64_OpMod16u(v) case OpMod32: return rewriteValueAMD64_OpMod32(v) case OpMod32u: return rewriteValueAMD64_OpMod32u(v) case OpMod64: return rewriteValueAMD64_OpMod64(v) case OpMod64u: return rewriteValueAMD64_OpMod64u(v) case OpMod8: return rewriteValueAMD64_OpMod8(v) case OpMod8u: return rewriteValueAMD64_OpMod8u(v) case OpMove: return rewriteValueAMD64_OpMove(v) case OpMul16: v.Op = OpAMD64MULL return true case OpMul32: v.Op = OpAMD64MULL return true case OpMul32F: v.Op = OpAMD64MULSS return true case OpMul64: v.Op = OpAMD64MULQ return true case OpMul64F: v.Op = OpAMD64MULSD return true case OpMul64uhilo: v.Op = OpAMD64MULQU2 return true case OpMul8: v.Op = OpAMD64MULL return true case OpNeg16: v.Op = OpAMD64NEGL return true case OpNeg32: v.Op = OpAMD64NEGL return true case OpNeg32F: return rewriteValueAMD64_OpNeg32F(v) case OpNeg64: v.Op = OpAMD64NEGQ return true case OpNeg64F: return rewriteValueAMD64_OpNeg64F(v) case OpNeg8: v.Op = OpAMD64NEGL return true case OpNeq16: return rewriteValueAMD64_OpNeq16(v) case OpNeq32: return rewriteValueAMD64_OpNeq32(v) case OpNeq32F: return rewriteValueAMD64_OpNeq32F(v) case OpNeq64: return rewriteValueAMD64_OpNeq64(v) case OpNeq64F: return rewriteValueAMD64_OpNeq64F(v) case OpNeq8: return rewriteValueAMD64_OpNeq8(v) case OpNeqB: return rewriteValueAMD64_OpNeqB(v) case OpNeqPtr: return rewriteValueAMD64_OpNeqPtr(v) case OpNilCheck: v.Op = OpAMD64LoweredNilCheck return true case OpNot: return rewriteValueAMD64_OpNot(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr(v) case OpOr16: v.Op = OpAMD64ORL return true case OpOr32: v.Op = OpAMD64ORL return true case OpOr64: v.Op = OpAMD64ORQ return true case OpOr8: v.Op = OpAMD64ORL return true case OpOrB: v.Op = OpAMD64ORL return true case OpPanicBounds: return rewriteValueAMD64_OpPanicBounds(v) case OpPopCount16: return rewriteValueAMD64_OpPopCount16(v) case OpPopCount32: v.Op = OpAMD64POPCNTL return true case OpPopCount64: v.Op = OpAMD64POPCNTQ return true case OpPopCount8: return rewriteValueAMD64_OpPopCount8(v) case OpPrefetchCache: v.Op = OpAMD64PrefetchT0 return true case OpPrefetchCacheStreamed: v.Op = OpAMD64PrefetchNTA return true case OpRotateLeft16: v.Op = OpAMD64ROLW return true case OpRotateLeft32: v.Op = OpAMD64ROLL return true case OpRotateLeft64: v.Op = OpAMD64ROLQ return true case OpRotateLeft8: v.Op = OpAMD64ROLB return true case OpRound32F: v.Op = OpCopy return true case OpRound64F: v.Op = OpCopy return true case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven(v) case OpRsh16Ux16: return rewriteValueAMD64_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValueAMD64_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValueAMD64_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValueAMD64_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValueAMD64_OpRsh16x16(v) case OpRsh16x32: return rewriteValueAMD64_OpRsh16x32(v) case OpRsh16x64: return rewriteValueAMD64_OpRsh16x64(v) case OpRsh16x8: return rewriteValueAMD64_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValueAMD64_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValueAMD64_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValueAMD64_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValueAMD64_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValueAMD64_OpRsh32x16(v) case OpRsh32x32: return rewriteValueAMD64_OpRsh32x32(v) case OpRsh32x64: return rewriteValueAMD64_OpRsh32x64(v) case OpRsh32x8: return rewriteValueAMD64_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValueAMD64_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValueAMD64_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValueAMD64_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValueAMD64_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValueAMD64_OpRsh64x16(v) case OpRsh64x32: return rewriteValueAMD64_OpRsh64x32(v) case OpRsh64x64: return rewriteValueAMD64_OpRsh64x64(v) case OpRsh64x8: return rewriteValueAMD64_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValueAMD64_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValueAMD64_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValueAMD64_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValueAMD64_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValueAMD64_OpRsh8x16(v) case OpRsh8x32: return rewriteValueAMD64_OpRsh8x32(v) case OpRsh8x64: return rewriteValueAMD64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8(v) case OpSelect0: return rewriteValueAMD64_OpSelect0(v) case OpSelect1: return rewriteValueAMD64_OpSelect1(v) case OpSelectN: return rewriteValueAMD64_OpSelectN(v) case OpSignExt16to32: v.Op = OpAMD64MOVWQSX return true case OpSignExt16to64: v.Op = OpAMD64MOVWQSX return true case OpSignExt32to64: v.Op = OpAMD64MOVLQSX return true case OpSignExt8to16: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to32: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to64: v.Op = OpAMD64MOVBQSX return true case OpSlicemask: return rewriteValueAMD64_OpSlicemask(v) case OpSpectreIndex: return rewriteValueAMD64_OpSpectreIndex(v) case OpSpectreSliceIndex: return rewriteValueAMD64_OpSpectreSliceIndex(v) case OpSqrt: v.Op = OpAMD64SQRTSD return true case OpSqrt32: v.Op = OpAMD64SQRTSS return true case OpStaticCall: v.Op = OpAMD64CALLstatic return true case OpStore: return rewriteValueAMD64_OpStore(v) case OpSub16: v.Op = OpAMD64SUBL return true case OpSub32: v.Op = OpAMD64SUBL return true case OpSub32F: v.Op = OpAMD64SUBSS return true case OpSub64: v.Op = OpAMD64SUBQ return true case OpSub64F: v.Op = OpAMD64SUBSD return true case OpSub8: v.Op = OpAMD64SUBL return true case OpSubPtr: v.Op = OpAMD64SUBQ return true case OpTailCall: v.Op = OpAMD64CALLtail return true case OpTrunc: return rewriteValueAMD64_OpTrunc(v) case OpTrunc16to8: v.Op = OpCopy return true case OpTrunc32to16: v.Op = OpCopy return true case OpTrunc32to8: v.Op = OpCopy return true case OpTrunc64to16: v.Op = OpCopy return true case OpTrunc64to32: v.Op = OpCopy return true case OpTrunc64to8: v.Op = OpCopy return true case OpWB: v.Op = OpAMD64LoweredWB return true case OpXor16: v.Op = OpAMD64XORL return true case OpXor32: v.Op = OpAMD64XORL return true case OpXor64: v.Op = OpAMD64XORQ return true case OpXor8: v.Op = OpAMD64XORL return true case OpZero: return rewriteValueAMD64_OpZero(v) case OpZeroExt16to32: v.Op = OpAMD64MOVWQZX return true case OpZeroExt16to64: v.Op = OpAMD64MOVWQZX return true case OpZeroExt32to64: v.Op = OpAMD64MOVLQZX return true case OpZeroExt8to16: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to32: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to64: v.Op = OpAMD64MOVBQZX return true } return false } func rewriteValueAMD64_OpAMD64ADCQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) // result: (ADCQconst x [int32(c)] carry) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) carry := v_2 if !(is32Bit(c)) { continue } v.reset(OpAMD64ADCQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, carry) return true } break } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQcarry) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64ADCQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQconst x [c] (FlagEQ)) // result: (ADDQconstcarry x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDL x (MOVLconst [c])) // result: (ADDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAL2) v.AddArg2(y, x) return true } } break } // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAL { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL { continue } y := v_1.Args[0] v.reset(OpAMD64SUBL) v.AddArg2(x, y) return true } break } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDLconst [c] (ADDL x y)) // result: (LEAL1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (SHLLconst [1] x)) // result: (LEAL1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // result: (MOVLconst [c+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c + d) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // result: (ADDLconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDLconst [off] x:(SP)) // result: (LEAL [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (ADDL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ADDQ x (MOVLconst [c])) // result: (ADDQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAQ2) v.AddArg2(y, x) return true } } break } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ { continue } y := v_1.Args[0] v.reset(OpAMD64SUBQ) v.AddArg2(x, y) return true } break } // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQcarry(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQcarry x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconstcarry x [int32(c)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDQconst [c] (ADDQ x y)) // result: (LEAQ1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (SHLQconst [1] x)) // result: (LEAQ1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDQconst [c] (LEAQ [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ADDQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) + d) return true } // match: (ADDQconst [c] (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (ADDQconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDQconst [off] x:(SP)) // result: (LEAQ [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (ADDQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (ADDSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (ADDSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ANDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTRL) v.AddArg2(x, y) return true } break } // match: (ANDL (NOTL (SHLXL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLXL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTRL) v.AddArg2(x, y) return true } break } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } break } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ANDL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDL x (NOTL y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTL { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNL) v.AddArg2(x, y) return true } break } // match: (ANDL x (NEGL x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIL) v.AddArg(x) return true } break } // match: (ANDL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSRL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSRL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDLconst [c] x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDLconst [c] (BTRLconst [d] x)) // result: (ANDLconst [c &^ (1<= 128 // result: (BTRQconst [int8(log64(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log64(^c))) v.AddArg(x) return true } break } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ANDQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDQ x (NOTQ y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTQ { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNQ) v.AddArg2(x, y) return true } break } // match: (ANDQ x (NEGQ x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIQ) v.AddArg(x) return true } break } // match: (ANDQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSRQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSRQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDQconst [c] x) // cond: isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRQconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDQconst [c] (ANDQconst [d] x)) // result: (ANDQconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDQconst [c] (BTRQconst [d] x)) // cond: is32Bit(int64(c) &^ (1< [1<<8] (MOVBQZX x))) // result: (BSFQ (ORQconst [1<<8] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVBQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 8) v0.AddArg(x) v.AddArg(v0) return true } // match: (BSFQ (ORQconst [1<<16] (MOVWQZX x))) // result: (BSFQ (ORQconst [1<<16] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVWQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPL(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPL (BSWAPL p)) // result: p for { if v_0.Op != OpAMD64BSWAPL { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPL x:(MOVLload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPL (MOVBELload [i] {s} p m)) // result: (MOVLload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBELload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPQ(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPQ (BSWAPQ p)) // result: p for { if v_0.Op != OpAMD64BSWAPQ { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPQ x:(MOVQload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPQ (MOVBEQload [i] {s} p m)) // result: (MOVQload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBEQload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BTCLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTCLconst [c] (XORLconst [d] x)) // result: (XORLconst [d ^ 1<d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTLconst [0] s:(SHRXQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 32) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTLconst [c] (SHLLconst [d] x)) // cond: c>d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } // match: (BTLconst [0] s:(SHRXL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTQconst(v *Value) bool { v_0 := v.Args[0] // match: (BTQconst [c] (SHRQconst [d] x)) // cond: (c+d)<64 // result: (BTQconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 64) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTQconst [c] (SHLQconst [d] x)) // cond: c>d // result: (BTQconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTQconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTQconst [0] s:(SHRXQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTRLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTRLconst [c] (BTSLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTSLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (BTCLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTCLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [d &^ (1<uint8(y) // result: (FlagLT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) < y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x) y && uint8(x) < uint8(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) > y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int8(m) && int8(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPBconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTB x y) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, y) return true } // match: (CMPBconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTBconst [int8(c)] x) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt8(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVBload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPBload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPL x (MOVLconst [c])) // result: (CMPLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64CMPLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // result: (InvertFlags (CMPLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPL y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x==y // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x == y) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: xuint32(y) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x < y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x) y && uint32(x) < uint32(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x > y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) // result: (FlagLT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x < y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x)>uint64(y) // result: (FlagGT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x > y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQ l:(MOVQload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPQload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPQ x l:(MOVQload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPQload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPQload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x==int64(y) // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x == int64(y)) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: xuint64(int64(y)) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x < int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x) int64(y) && uint64(x) < uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x)>uint64(int64(y)) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x > int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQconst (MOVBQZX _) [c]) // cond: 0xFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVWQZX _) [c]) // cond: 0xFFFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (SHRQconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 64 && (1<uint16(y) // result: (FlagLT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) < y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x) y && uint16(x) < uint16(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) > y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int16(m) && int16(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPWconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTW x y) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, y) return true } // match: (CMPWconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTWconst [int16(c)] x) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt16(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVWload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPWload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGLlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGQlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64HMULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULL x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULL y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULLU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULLU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULLU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULLU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQ x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQ y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64LEAL(v *Value) bool { v_0 := v.Args[0] // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { v_0 := v.Args[0] // match: (LEAQ [c] {s} (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAQ [c] {s} (ADDQ x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg(x) return true } // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ2 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ4 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ8 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64LEAQ { continue } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(y, x) return true } } break } // match: (LEAQ1 [0] x y) // cond: v.Aux == nil // result: (ADDQ x y) for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 y := v_1 if !(v.Aux == nil) { break } v.reset(OpAMD64ADDQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAQ2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil // result: (LEAQ4 [off1+2*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + 2*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ2 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ2 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAQ4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil // result: (LEAQ8 [off1+4*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + 4*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ4 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ4 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAQ8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ8 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ8 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBELstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBELstore [i] {s} p (BSWAPL x) m) // result: (MOVLstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPL { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEQstore [i] {s} p (BSWAPQ x) m) // result: (MOVQstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPQ { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7f) v.AddArg(x) return true } // match: (MOVBQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x) // cond: zeroUpper56Bits(x,3) // result: x for { x := v_0 if !(zeroUpper56Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVBQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xff) v.AddArg(x) return true } // match: (MOVBQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read8(sym, int64(off)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read8(sym, int64(off)))) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) // cond: y.Uses == 1 // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETL { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) // cond: y.Uses == 1 // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETLE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) // cond: y.Uses == 1 // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETG { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) // cond: y.Uses == 1 // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETGE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) // cond: y.Uses == 1 // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETEQ { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) // cond: y.Uses == 1 // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETNE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) // cond: y.Uses == 1 // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETB { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) // cond: y.Uses == 1 // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETBE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) // cond: y.Uses == 1 // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETA { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) // cond: y.Uses == 1 // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETAE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstore [i-1] {s} p (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p1 w x0:(MOVBstore [i] {s} p0 (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0) // result: (MOVWstore [i] {s} p0 (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-1 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-3 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 3) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p3 w x2:(MOVBstore [i] {s} p2 (SHRLconst [8] w) x1:(MOVBstore [i] {s} p1 (SHRLconst [16] w) x0:(MOVBstore [i] {s} p0 (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2) // result: (MOVLstore [i] {s} p0 (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p3 := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i-1 || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] if p != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i-2 || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i-3 || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i-4 || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-5 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-6 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-7 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 7) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p7 w x6:(MOVBstore [i] {s} p6 (SHRQconst [8] w) x5:(MOVBstore [i] {s} p5 (SHRQconst [16] w) x4:(MOVBstore [i] {s} p4 (SHRQconst [24] w) x3:(MOVBstore [i] {s} p3 (SHRQconst [32] w) x2:(MOVBstore [i] {s} p2 (SHRQconst [40] w) x1:(MOVBstore [i] {s} p1 (SHRQconst [48] w) x0:(MOVBstore [i] {s} p0 (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i] {s} p0 (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p7 := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] p6 := x6.Args[0] x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] p5 := x5.Args[0] x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] p4 := x4.Args[0] x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] p3 := x3.Args[0] x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRWconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [c3] {s} p3 (SHRQconst [56] w) x1:(MOVWstore [c2] {s} p2 (SHRQconst [40] w) x2:(MOVLstore [c1] {s} p1 (SHRQconst [8] w) x3:(MOVBstore [c0] {s} p0 w mem)))) // cond: x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1 + c0 - c1)) && sequentialAddresses(p0, p2, int64(5 + c0 - c2)) && sequentialAddresses(p0, p3, int64(7 + c0 - c3)) && clobber(x1, x2, x3) // result: (MOVQstore [c0] {s} p0 w mem) for { c3 := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p3 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 56 { break } w := v_1.Args[0] x1 := v_2 if x1.Op != OpAMD64MOVWstore { break } c2 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p2 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 40 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpAMD64MOVLstore { break } c1 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p1 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpAMD64MOVBstore { break } c0 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { break } mem := x3.Args[2] p0 := x3.Args[0] if w != x3.Args[1] || !(x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1+c0-c1)) && sequentialAddresses(p0, p2, int64(5+c0-c2)) && sequentialAddresses(p0, p3, int64(7+c0-c3)) && clobber(x1, x2, x3)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(c0) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVBload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVBstore || auxIntToInt32(mem2.AuxInt) != i-1 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVBload || auxIntToInt32(x2.AuxInt) != j-1 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(j - 1) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [c] {s} p1 x:(MOVBstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVBstoreconst [a] {s} p0 x:(MOVBstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX (ANDLconst [c] x)) // cond: uint32(c) & 0x80000000 == 0 // result: (ANDLconst [c & 0x7fffffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(uint32(c)&0x80000000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fffffff) v.AddArg(x) return true } // match: (MOVLQSX (MOVLQSX x)) // result: (MOVLQSX x) for { if v_0.Op != OpAMD64MOVLQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x) // cond: zeroUpper32Bits(x,3) // result: x for { x := v_0 if !(zeroUpper32Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVLQZX (ANDLconst [c] x)) // result: (ANDLconst [c] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (MOVLQZX (MOVLQZX x)) // result: (MOVLQZX x) for { if v_0.Op != OpAMD64MOVLQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLf2i) v.AddArg(val) return true } // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [32] w) x:(MOVLstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [j] w) x:(MOVLstore [i] {s} p0 w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVLload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVLstore || auxIntToInt32(mem2.AuxInt) != i-4 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVLload || auxIntToInt32(x2.AuxInt) != j-4 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(j - 4) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) // result: (MOVSSstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [i] {s} p x:(BSWAPL w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPL { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [c] {s} p1 x:(MOVLstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p0, v0, mem) return true } // match: (MOVLstoreconst [a] {s} p0 x:(MOVLstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p0, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) // cond: symIsRO(srcSym) // result: (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))]) (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))]) mem)) for { dstOff := auxIntToInt32(v.AuxInt) dstSym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVOload { break } srcOff := auxIntToInt32(v_1.AuxInt) srcSym := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } mem := v_2 if !(symIsRO(srcSym)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(dstOff + 8) v.Aux = symToAux(dstSym) v0 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))) v1 := b.NewValue0(v_1.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AuxInt = int32ToAuxInt(dstOff) v1.Aux = symToAux(dstSym) v2 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))) v1.AddArg3(ptr, v2, mem) v.AddArg3(ptr, v0, v1) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVOstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.copyOf(x) return true } // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) // result: (MOVQf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQf2i) v.AddArg(val) return true } // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validVal(c) // result: (MOVQstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(validVal(c)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) // result: (MOVSDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [i] {s} p x:(BSWAPQ w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPQ { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [c] {s} p1 x:(MOVQstoreconst [a] {s} p0 mem)) // cond: config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVQstoreconst [a] {s} p0 x:(MOVQstoreconst [c] {s} p1 mem)) // cond: config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fff) v.AddArg(x) return true } // match: (MOVWQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x) // cond: zeroUpper48Bits(x,3) // result: x for { x := v_0 if !(zeroUpper48Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVWQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xffff) v.AddArg(x) return true } // match: (MOVWQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVWload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVWstore || auxIntToInt32(mem2.AuxInt) != i-2 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVWload || auxIntToInt32(x2.AuxInt) != j-2 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(j - 2) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [c] {s} p1 x:(MOVWstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVWstoreconst [a] {s} p0 x:(MOVWstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULL x (MOVLconst [c])) // result: (MULLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULLconst [c] (MULLconst [d] x)) // result: (MULLconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULLconst [-9] x) // result: (NEGL (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // result: (NEGL (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // result: (NEGL (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // result: (NEGL x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGL) v.AddArg(x) return true } // match: (MULLconst [ 0] _) // result: (MOVLconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (MULLconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULLconst [ 3] x) // result: (LEAL2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAL2) v.AddArg2(x, x) return true } // match: (MULLconst [ 5] x) // result: (LEAL4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAL4) v.AddArg2(x, x) return true } // match: (MULLconst [ 7] x) // result: (LEAL2 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [ 9] x) // result: (LEAL8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAL8) v.AddArg2(x, x) return true } // match: (MULLconst [11] x) // result: (LEAL2 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [13] x) // result: (LEAL4 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [19] x) // result: (LEAL2 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [21] x) // result: (LEAL4 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [25] x) // result: (LEAL8 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [27] x) // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [37] x) // result: (LEAL4 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [41] x) // result: (LEAL8 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [45] x) // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [73] x) // result: (LEAL8 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [81] x) // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBL (SHLLconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAL1) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLLconst [int8(log32(c/3))] (LEAL2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLLconst [int8(log32(c/5))] (LEAL4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLLconst [int8(log32(c/9))] (LEAL8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] (MOVLconst [d])) // result: (MOVLconst [c*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c * d) return true } return false } func rewriteValueAMD64_OpAMD64MULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (MULQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULQconst [c] (MULQconst [d] x)) // cond: is32Bit(int64(c)*int64(d)) // result: (MULQconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) * int64(d))) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULQconst [-9] x) // result: (NEGQ (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-5] x) // result: (NEGQ (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-3] x) // result: (NEGQ (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-1] x) // result: (NEGQ x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGQ) v.AddArg(x) return true } // match: (MULQconst [ 0] _) // result: (MOVQconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MULQconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULQconst [ 3] x) // result: (LEAQ2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAQ2) v.AddArg2(x, x) return true } // match: (MULQconst [ 5] x) // result: (LEAQ4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAQ4) v.AddArg2(x, x) return true } // match: (MULQconst [ 7] x) // result: (LEAQ2 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [ 9] x) // result: (LEAQ8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAQ8) v.AddArg2(x, x) return true } // match: (MULQconst [11] x) // result: (LEAQ2 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [13] x) // result: (LEAQ4 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [19] x) // result: (LEAQ2 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [21] x) // result: (LEAQ4 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [25] x) // result: (LEAQ8 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [27] x) // result: (LEAQ8 (LEAQ2 x x) (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [37] x) // result: (LEAQ4 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [41] x) // result: (LEAQ8 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [45] x) // result: (LEAQ8 (LEAQ4 x x) (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [73] x) // result: (LEAQ8 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [81] x) // result: (LEAQ8 (LEAQ8 x x) (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBQ (SHLQconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAQ1 (SHLQconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAQ1) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAQ2 (SHLQconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAQ4 (SHLQconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAQ8 (SHLQconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLQconst [int8(log32(c/3))] (LEAQ2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLQconst [int8(log32(c/5))] (LEAQ4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLQconst [int8(log32(c/9))] (LEAQ8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) * d) return true } // match: (MULQconst [c] (NEGQ x)) // cond: c != -(1<<31) // result: (MULQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (MULSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64MULSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (MULSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64NEGL(v *Value) bool { v_0 := v.Args[0] // match: (NEGL (NEGL x)) // result: x for { if v_0.Op != OpAMD64NEGL { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGL s:(SUBL x y)) // cond: s.Uses == 1 // result: (SUBL y x) for { s := v_0 if s.Op != OpAMD64SUBL { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBL) v.AddArg2(y, x) return true } // match: (NEGL (MOVLconst [c])) // result: (MOVLconst [-c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-c) return true } return false } func rewriteValueAMD64_OpAMD64NEGQ(v *Value) bool { v_0 := v.Args[0] // match: (NEGQ (NEGQ x)) // result: x for { if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGQ s:(SUBQ x y)) // cond: s.Uses == 1 // result: (SUBQ y x) for { s := v_0 if s.Op != OpAMD64SUBQ { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBQ) v.AddArg2(y, x) return true } // match: (NEGQ (MOVQconst [c])) // result: (MOVQconst [-c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-c) return true } // match: (NEGQ (ADDQconst [c] (NEGQ x))) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { if v_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } x := v_0_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64NOTL(v *Value) bool { v_0 := v.Args[0] // match: (NOTL (MOVLconst [c])) // result: (MOVLconst [^c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64NOTQ(v *Value) bool { v_0 := v.Args[0] // match: (NOTQ (MOVQconst [c])) // result: (MOVQconst [^c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64ORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTSL) v.AddArg2(x, y) return true } break } // match: (ORL (SHLXL (MOVLconst [1]) y) x) // result: (BTSL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTSL) v.AddArg2(x, y) return true } break } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORL x0:(MOVBload [i0] {s} p mem) sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVBload [i] {s} p0 mem) sh:(SHLLconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVWload [i] {s} p0 mem) sh:(SHLLconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL x1:(MOVBload [i] {s} p1 mem) sh:(SHLLconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORLconst(v *Value) bool { v_0 := v.Args[0] // match: (ORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORLconst [c] (ORLconst [d] x)) // result: (ORLconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORLconst [c] (BTSLconst [d] x)) // result: (ORLconst [c | 1<= 128 // result: (BTSQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ORQ x (MOVLconst [c])) // result: (ORQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORQ (SHRQ lo bits) (SHLQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLQ lo bits) (SHRQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHRXQ lo bits) (SHLXQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLXQ lo bits) (SHRXQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (MOVQconst [c]) (MOVQconst [d])) // result: (MOVQconst [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c | d) return true } break } // match: (ORQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORQ x0:(MOVBload [i0] {s} p mem) sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBload [i] {s} p0 mem) sh:(SHLQconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVWload [i] {s} p0 mem) sh:(SHLQconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVLload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVLload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i] {s} p0 mem)) y)) // cond: j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ x1:(MOVBload [i] {s} p1 mem) sh:(SHLQconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i] {s} p1 mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem))) y)) // cond: j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ORQ x0:(MOVBELload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVBELload [i1] {s} p mem))) // cond: i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i1] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i1) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBELload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVBELload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i] {s} p1 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p1, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQconst(v *Value) bool { v_0 := v.Args[0] // match: (ORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORQconst [c] (ORQconst [d] x)) // result: (ORQconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORQconst [c] (BTSQconst [d] x)) // cond: is32Bit(int64(c) | 1<>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int8(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARL x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SARXL x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (MOVLconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SARLconst(v *Value) bool { v_0 := v.Args[0] // match: (SARLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARLconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int32(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int32(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SARXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (MOVLconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SARQconst(v *Value) bool { v_0 := v.Args[0] // match: (SARQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARQconst [c] (MOVQconst [d])) // result: (MOVQconst [d>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SARW x (MOVQconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } // match: (SARW x (MOVLconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SARWconst(v *Value) bool { v_0 := v.Args[0] // match: (SARWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARWconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int16(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int16(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARXL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARXL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARXL x (MOVLconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARXL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SARXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SARXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SARLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARXQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARXQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARXQ x (MOVLconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARXQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SARXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SARXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SARXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SBBLcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBLcarrymask (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagLT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagGT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQ x (MOVQconst [c]) borrow) // cond: is32Bit(c) // result: (SBBQconst x [int32(c)] borrow) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) borrow := v_2 if !(is32Bit(c)) { break } v.reset(OpAMD64SBBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, borrow) return true } // match: (SBBQ x y (FlagEQ)) // result: (SUBQborrow x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQborrow) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64SBBQcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBQcarrymask (FlagEQ)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagLT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagLT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagGT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagGT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQconst x [c] (FlagEQ)) // result: (SUBQconstborrow x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SETA(v *Value) bool { v_0 := v.Args[0] // match: (SETA (InvertFlags x)) // result: (SETB x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETA (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAE(v *Value) bool { v_0 := v.Args[0] // match: (SETAE (TESTQ x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTL x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTW x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTB x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (InvertFlags x)) // result: (SETBE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETAstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETB(v *Value) bool { v_0 := v.Args[0] // match: (SETB (TESTQ x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTL x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTW x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTB x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (BTLconst [0] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64BTLconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (BTQconst [0] x)) // result: (ANDQconst [1] x) for { if v_0.Op != OpAMD64BTQconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (InvertFlags x)) // result: (SETA x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBE(v *Value) bool { v_0 := v.Args[0] // match: (SETBE (InvertFlags x)) // result: (SETAE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETBE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAE (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAE (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETNE (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETEQ (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETEQstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETG(v *Value) bool { v_0 := v.Args[0] // match: (SETG (InvertFlags x)) // result: (SETL x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETG (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGE(v *Value) bool { v_0 := v.Args[0] // match: (SETGE (InvertFlags x)) // result: (SETLE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETL(v *Value) bool { v_0 := v.Args[0] // match: (SETL (InvertFlags x)) // result: (SETG x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLE(v *Value) bool { v_0 := v.Args[0] // match: (SETLE (InvertFlags x)) // result: (SETGE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETLE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNE(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETNE (TESTBconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTBconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTWconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTWconst || auxIntToInt16(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETB (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETB (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETEQ (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (InvertFlags x)) // result: (SETNE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETNE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETNEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLL x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHLXL x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (MOVLconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLLconst [1] (SHRLconst [1] x)) // result: (BTRLconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLLconst [d] (MOVLconst [c])) // result: (MOVLconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHLXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (MOVLconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLQconst [1] (SHRQconst [1] x)) // result: (BTRQconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLQconst [d] (MOVQconst [c])) // result: (MOVQconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c << uint64(d)) return true } // match: (SHLQconst [d] (MOVLconst [c])) // result: (MOVQconst [int64(c) << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLXL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLXL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLXL x (MOVLconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLXL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHLXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHLXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHLLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLXQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLXQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLXQ x (MOVLconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLXQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHLXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHLXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SHLXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRB x (MOVQconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB _ (MOVQconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRBconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRBconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRL x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHRXL x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (MOVLconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRLconst [1] (SHLLconst [1] x)) // result: (BTRLconst [31] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(31) v.AddArg(x) return true } // match: (SHRLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHRXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (MOVLconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRQconst [1] (SHLQconst [1] x)) // result: (BTRQconst [63] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(63) v.AddArg(x) return true } // match: (SHRQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRW x (MOVQconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW _ (MOVQconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRWconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRXL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRXL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRXL x (MOVLconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRXL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHRXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHRXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHRLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRXQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRXQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRXQ x (MOVLconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRXQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHRXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHRXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SHRXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBL x (MOVLconst [c])) // result: (SUBLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SUBLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // result: (NEGL (SUBLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBLconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (SUBLconst [c] x) // result: (ADDLconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } } func rewriteValueAMD64_OpAMD64SUBLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (SUBL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconst x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } // match: (SUBQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (NEGQ (SUBQconst x [int32(c)])) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBQload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQborrow(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQborrow x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconstborrow x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SUBQconst [c] x) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } // match: (SUBQconst (MOVQconst [d]) [c]) // result: (MOVQconst [d-int64(c)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d - int64(c)) return true } // match: (SUBQconst (SUBQconst x [d]) [c]) // cond: is32Bit(int64(-c)-int64(d)) // result: (ADDQconst [-c-d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SUBQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(-c) - int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c - d) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (SUBQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (SUBSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (SUBSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64TESTB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [int8(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } break } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVBload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTBconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTBconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTL a:(ANDLload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTL (MOVLload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDLload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTL) v0 := b.NewValue0(a.Pos, OpAMD64MOVLload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTLconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTLconst [c] (MOVLconst [c])) // cond: c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTLconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTL x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTL) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (TESTQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { continue } v.reset(OpAMD64TESTQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTQ a:(ANDQload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTQ (MOVQload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDQload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTQ) v0 := b.NewValue0(a.Pos, OpAMD64MOVQload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTQconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTQconst [-1] x) // cond: x.Op != OpAMD64MOVQconst // result: (TESTQ x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVQconst) { break } v.reset(OpAMD64TESTQ) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [int16(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } break } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVWload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTWconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTWconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64XADDLlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDLlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XADDQlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDQlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGL(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGL [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGQ [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTCL) v.AddArg2(x, y) return true } break } // match: (XORL (SHLXL (MOVLconst [1]) y) x) // result: (BTCL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTCL) v.AddArg2(x, y) return true } break } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORLconst(v *Value) bool { v_0 := v.Args[0] // match: (XORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORLconst [1] (SETNE x)) // result: (SETEQ x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETNE { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (XORLconst [1] (SETEQ x)) // result: (SETNE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETEQ { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (XORLconst [1] (SETL x)) // result: (SETGE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETL { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (XORLconst [1] (SETGE x)) // result: (SETL x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETGE { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (XORLconst [1] (SETLE x)) // result: (SETG x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETLE { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (XORLconst [1] (SETG x)) // result: (SETLE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETG { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (XORLconst [1] (SETB x)) // result: (SETAE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETB { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (XORLconst [1] (SETAE x)) // result: (SETB x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETAE { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (XORLconst [1] (SETBE x)) // result: (SETA x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETBE { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (XORLconst [1] (SETA x)) // result: (SETBE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETA { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (XORLconst [c] (XORLconst [d] x)) // result: (XORLconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORLconst [c] (BTCLconst [d] x)) // result: (XORLconst [c ^ 1<= 128 // result: (BTCQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (XORQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORQconst(v *Value) bool { v_0 := v.Args[0] // match: (XORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORQconst [c] (XORQconst [d] x)) // result: (XORQconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORQconst [c] (BTCQconst [d] x)) // cond: is32Bit(int64(c) ^ 1< val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore64(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore64 ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore8 ptr val mem) // result: (Select1 (XCHGB val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStorePtrNoWB(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStorePtrNoWB ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen16 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen16 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVWQZX x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, x.Type) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) v1.AuxInt = int32ToAuxInt(1) v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v2.AddArg(x) v1.AddArg2(v2, v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (BitLen32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // cond: buildcfg.GOAMD64 < 3 // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(1) v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) v1 := b.NewValue0(v.Pos, OpSelect0, t) v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v3.AuxInt = int64ToAuxInt(-1) v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4.AddArg(v2) v0.AddArg3(v1, v3, v4) v.AddArg(v0) return true } // match: (BitLen64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-64] (LZCNTQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-64) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTQ, typ.UInt64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen8 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen8 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVBQZX x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, x.Type) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCeil(v *Value) bool { v_0 := v.Args[0] // match: (Ceil x) // result: (ROUNDSD [2] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(2) v.AddArg(x) return true } } func rewriteValueAMD64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (CondSelect x y (SETEQ cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is32BitInt(t) // result: (CMOVLEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is32BitInt(t) // result: (CMOVLNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is32BitInt(t) // result: (CMOVLLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is32BitInt(t) // result: (CMOVLGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is32BitInt(t) // result: (CMOVLLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is32BitInt(t) // result: (CMOVLGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is32BitInt(t) // result: (CMOVLHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is32BitInt(t) // result: (CMOVLCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is32BitInt(t) // result: (CMOVLCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is32BitInt(t) // result: (CMOVLLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is32BitInt(t) // result: (CMOVLEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is32BitInt(t) // result: (CMOVLNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is32BitInt(t) // result: (CMOVLGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is32BitInt(t) // result: (CMOVLGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is16BitInt(t) // result: (CMOVWEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is16BitInt(t) // result: (CMOVWNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is16BitInt(t) // result: (CMOVWLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is16BitInt(t) // result: (CMOVWGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is16BitInt(t) // result: (CMOVWLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is16BitInt(t) // result: (CMOVWGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is16BitInt(t) // result: (CMOVWHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is16BitInt(t) // result: (CMOVWCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is16BitInt(t) // result: (CMOVWCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is16BitInt(t) // result: (CMOVWLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is16BitInt(t) // result: (CMOVWEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is16BitInt(t) // result: (CMOVWNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is16BitInt(t) // result: (CMOVWGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is16BitInt(t) // result: (CMOVWGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 1 // result: (CondSelect x y (MOVBQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 1) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 2 // result: (CondSelect x y (MOVWQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 2) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 4 // result: (CondSelect x y (MOVLQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 4) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { break } v.reset(OpAMD64CMOVQNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) // result: (CMOVLNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) // result: (CMOVWNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } return false } func rewriteValueAMD64_OpConst16(v *Value) bool { // match: (Const16 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt16(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConst8(v *Value) bool { // match: (Const8 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt8(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConstBool(v *Value) bool { // match: (ConstBool [c]) // result: (MOVLconst [b2i32(c)]) for { c := auxIntToBool(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(b2i32(c)) return true } } func rewriteValueAMD64_OpConstNil(v *Value) bool { // match: (ConstNil ) // result: (MOVQconst [0]) for { v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } } func rewriteValueAMD64_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (BSFL (BTSLconst [16] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(16) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz16NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ (BTSQconst [32] x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) v1.AuxInt = int8ToAuxInt(32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz32NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64 x) // cond: buildcfg.GOAMD64 < 3 // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v3.AddArg(v1) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueAMD64_OpCtz64NonZero(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ x)) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (BSFL (BTSLconst [ 8] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 [a] x y) // result: (Select0 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (Select0 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32 [a] x y) // result: (Select0 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32u x y) // result: (Select0 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64 [a] x y) // result: (Select0 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64u x y) // result: (Select0 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq16 x y) // result: (SETEQ (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32 x y) // result: (SETEQ (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32F x y) // result: (SETEQF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64 x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64F x y) // result: (SETEQF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq8 x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqB x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqPtr x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpFMA(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMA x y z) // result: (VFMADD231SD z x y) for { x := v_0 y := v_1 z := v_2 v.reset(OpAMD64VFMADD231SD) v.AddArg3(z, x, y) return true } } func rewriteValueAMD64_OpFloor(v *Value) bool { v_0 := v.Args[0] // match: (Floor x) // result: (ROUNDSD [1] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpGetG(v *Value) bool { v_0 := v.Args[0] // match: (GetG mem) // cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal // result: (LoweredGetG mem) for { mem := v_0 if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) { break } v.reset(OpAMD64LoweredGetG) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (HasCPUFeature {s}) // result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s}))) for { s := auxToSym(v.Aux) v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64) v1.Aux = symToAux(s) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsInBounds idx len) // result: (SETB (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsNonNil(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (IsNonNil p) // result: (SETNE (TESTQ p p)) for { p := v_0 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) v0.AddArg2(p, p) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsSliceInBounds idx len) // result: (SETBE (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16 x y) // result: (SETLE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16U x y) // result: (SETBE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32 x y) // result: (SETLE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32F x y) // result: (SETGEF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32U x y) // result: (SETBE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64 x y) // result: (SETLE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64F x y) // result: (SETGEF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64U x y) // result: (SETBE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8 x y) // result: (SETLE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8U x y) // result: (SETBE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16 x y) // result: (SETL (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16U x y) // result: (SETB (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 x y) // result: (SETL (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32F x y) // result: (SETGF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32U x y) // result: (SETB (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 x y) // result: (SETL (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64F x y) // result: (SETGF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64U x y) // result: (SETB (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8 x y) // result: (SETL (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8U x y) // result: (SETB (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVQload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64MOVQload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) // result: (MOVLload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t)) { break } v.reset(OpAMD64MOVLload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t)) { break } v.reset(OpAMD64MOVWload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(OpAMD64MOVBload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitFloat(t)) { break } v.reset(OpAMD64MOVSSload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitFloat(t)) { break } v.reset(OpAMD64MOVSDload) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpLocalAddr(v *Value) bool { v_0 := v.Args[0] // match: (LocalAddr {sym} base _) // result: (LEAQ {sym} base) for { sym := auxToSym(v.Aux) base := v_0 v.reset(OpAMD64LEAQ) v.Aux = symToAux(sym) v.AddArg(base) return true } } func rewriteValueAMD64_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16 [a] x y) // result: (Select1 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Select1 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32 [a] x y) // result: (Select1 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (Select1 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64 [a] x y) // result: (Select1 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (Select1 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [2] dst src mem) // result: (MOVWstore dst (MOVWload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [4] dst src mem) // result: (MOVLstore dst (MOVLload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [8] dst src mem) // result: (MOVQstore dst (MOVQload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVQstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: config.useSSE // result: (MOVOstore dst (MOVOload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: !config.useSSE // result: (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [32] dst src mem) // result: (Move [16] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpMove) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [48] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 48 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [64] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [32]) (OffPtr src [32]) (Move [32] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 64 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(32) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(32) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(32) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(2) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [6] dst src mem) // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [7] dst src mem) // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [10] dst src mem) // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [12] dst src mem) // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s == 11 || s >= 13 && s <= 15 // result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s == 11 || s >= 13 && s <= 15) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(int32(s - 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(int32(s - 8)) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 <= 8 // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 <= 8) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVOstore dst (MOVOload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AuxInt = int32ToAuxInt(8) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AuxInt = int32ToAuxInt(8) v3.AddArg2(src, mem) v4 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v5 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v5.AddArg2(src, mem) v4.AddArg3(dst, v5, mem) v2.AddArg3(dst, v3, v4) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s) // result: (DUFFCOPY [s] dst src mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s)) { break } v.reset(OpAMD64DUFFCOPY) v.AuxInt = int64ToAuxInt(s) v.AddArg3(dst, src, mem) return true } // match: (Move [s] dst src mem) // cond: (s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s) // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !((s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s)) { break } v.reset(OpAMD64REPMOVSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v.AddArg4(dst, src, v0, mem) return true } return false } func rewriteValueAMD64_OpNeg32F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg32F x) // result: (PXOR x (MOVSSconst [float32(math.Copysign(0, -1))])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1))) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeg64F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg64F x) // result: (PXOR x (MOVSDconst [math.Copysign(0, -1)])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) v0.AuxInt = float64ToAuxInt(math.Copysign(0, -1)) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq16 x y) // result: (SETNE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32 x y) // result: (SETNE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32F x y) // result: (SETNEF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64 x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64F x y) // result: (SETNEF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq8 x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqB x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqPtr x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNot(v *Value) bool { v_0 := v.Args[0] // match: (Not x) // result: (XORLconst [1] x) for { x := v_0 v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // cond: is32Bit(off) // result: (ADDQconst [int32(off)] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 if !(is32Bit(off)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(off)) v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDQ (MOVQconst [off]) ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(off) v.AddArg2(v0, ptr) return true } } func rewriteValueAMD64_OpPanicBounds(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 0) { break } v.reset(OpAMD64LoweredPanicBoundsA) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 1) { break } v.reset(OpAMD64LoweredPanicBoundsB) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 2) { break } v.reset(OpAMD64LoweredPanicBoundsC) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } return false } func rewriteValueAMD64_OpPopCount16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTL (MOVWQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpPopCount8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTL (MOVBQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpRoundToEven(v *Value) bool { v_0 := v.Args[0] // match: (RoundToEven x) // result: (ROUNDSD [0] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } } func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpSelect0(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uover x y)) // result: (Select0 (MULQU x y)) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Mul32uover x y)) // result: (Select0 (MULLU x y)) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y c)) // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst32 val tuple)) // result: (ADDL val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDL) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } // match: (Select0 (AddTupleFirst64 val tuple)) // result: (ADDQ val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } return false } func rewriteValueAMD64_OpSelect1(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uover x y)) // result: (SETO (Select1 (MULQU x y))) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul32uover x y)) // result: (SETO (Select1 (MULLU x y))) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Add64carry x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (NEGLflags (MOVQconst [0]))) // result: (FlagEQ) for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 0 { break } v.reset(OpAMD64FlagEQ) return true } // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) // result: x for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64SBBQcarrymask { break } x := v_0_0_0.Args[0] v.copyOf(x) return true } // match: (Select1 (AddTupleFirst32 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } // match: (Select1 (AddTupleFirst64 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } return false } func rewriteValueAMD64_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem))))) // cond: sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call) // result: (Move [sc.Val64()] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpAMD64MOVQstoreconst { break } sc := auxIntToValAndOff(s1.AuxInt) _ = s1.Args[1] s2 := s1.Args[1] if s2.Op != OpAMD64MOVQstore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpAMD64MOVQstore { break } mem := s3.Args[2] dst := s3.Args[1] if !(sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sc.Val64()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem)) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpAMD64MOVQconst { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } return false } func rewriteValueAMD64_OpSlicemask(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Slicemask x) // result: (SARQconst (NEGQ x) [63]) for { t := v.Type x := v_0 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(63) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpSpectreIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreIndex x y) // result: (CMOVQCC x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQCC) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpSpectreSliceIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreSliceIndex x y) // result: (CMOVQHI x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQHI) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && is64BitFloat(val.Type) // result: (MOVSDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSDstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && is32BitFloat(val.Type) // result: (MOVSSstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSSstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 // result: (MOVQstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8) { break } v.reset(OpAMD64MOVQstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 // result: (MOVLstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4) { break } v.reset(OpAMD64MOVLstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 2 // result: (MOVWstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 2) { break } v.reset(OpAMD64MOVWstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 1 // result: (MOVBstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 1) { break } v.reset(OpAMD64MOVBstore) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpTrunc(v *Value) bool { v_0 := v.Args[0] // match: (Trunc x) // result: (ROUNDSD [3] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(3) v.AddArg(x) return true } } func rewriteValueAMD64_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [0] _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_1 v.copyOf(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [2] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [4] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [8] destptr mem) // result: (MOVQstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 2)) v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [5] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [6] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [7] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 3)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%8 != 0 && s > 8 && !config.useSSE // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%8 != 0 && s > 8 && !config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%8) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [24] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 24 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [32] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 24)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 8 && s < 16 && config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,int32(s-8))] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 8 && s < 16 && config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, int32(s-8))) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [32] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [48] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [64] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,48)] destptr (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 48)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice // result: (DUFFZERO [s] destptr mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFZERO) v.AuxInt = int64ToAuxInt(s) v.AddArg2(destptr, mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0 // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !((s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0) { break } v.reset(OpAMD64REPSTOSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(0) v.AddArg4(destptr, v0, v1, mem) return true } return false } func rewriteBlockAMD64(b *Block) bool { typ := &b.Func.Config.Types switch b.Kind { case BlockAMD64EQ: // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (UGE (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (UGE (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64GE: // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64GT: // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockIf: // match: (If (SETL cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64SETL { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (If (SETLE cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64SETLE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (If (SETG cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64SETG { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (If (SETGE cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64SETGE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (If (SETEQ cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64SETEQ { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (If (SETNE cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64SETNE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (If (SETB cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64SETB { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (If (SETBE cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64SETBE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (If (SETA cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETA { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETAE cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETAE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETO cmp) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64SETO { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (If (SETGF cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETGF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETGEF cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETGEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETEQF cmp) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64SETEQF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (If (SETNEF cmp) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64SETNEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (If cond yes no) // result: (NE (TESTB cond cond) yes no) for { cond := b.Controls[0] v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) v0.AddArg2(cond, cond) b.resetWithControl(BlockAMD64NE, v0) return true } case BlockJumpTable: // match: (JumpTable idx) // result: (JUMPTABLE {makeJumpTableSym(b)} idx (LEAQ {makeJumpTableSym(b)} (SB))) for { idx := b.Controls[0] v0 := b.NewValue0(b.Pos, OpAMD64LEAQ, typ.Uintptr) v0.Aux = symToAux(makeJumpTableSym(b)) v1 := b.NewValue0(b.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) b.resetWithControl2(BlockAMD64JUMPTABLE, idx, v0) b.Aux = symToAux(makeJumpTableSym(b)) return true } case BlockAMD64LE: // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64LT: // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETL { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETLE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETG { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQ { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETB { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETBE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETA { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETAE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETO { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (ULT (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (ULT (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGE: // match: (UGE (TESTQ x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTL x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTW x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTB x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (UGE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (UGE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGT: // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (UGT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64ULE: // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (ULE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64ULT: // match: (ULT (TESTQ x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTL x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTW x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTB x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (ULT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- y -- // Code generated from gen/AMD64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "internal/buildcfg" import "math" import "cmd/internal/obj" import "cmd/compile/internal/types" func rewriteValueAMD64(v *Value) bool { switch v.Op { case OpAMD64ADCQ: return rewriteValueAMD64_OpAMD64ADCQ(v) case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst(v) case OpAMD64ADDL: return rewriteValueAMD64_OpAMD64ADDL(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst(v) case OpAMD64ADDLconstmodify: return rewriteValueAMD64_OpAMD64ADDLconstmodify(v) case OpAMD64ADDLload: return rewriteValueAMD64_OpAMD64ADDLload(v) case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify(v) case OpAMD64ADDQ: return rewriteValueAMD64_OpAMD64ADDQ(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry(v) case OpAMD64ADDQconst: return rewriteValueAMD64_OpAMD64ADDQconst(v) case OpAMD64ADDQconstmodify: return rewriteValueAMD64_OpAMD64ADDQconstmodify(v) case OpAMD64ADDQload: return rewriteValueAMD64_OpAMD64ADDQload(v) case OpAMD64ADDQmodify: return rewriteValueAMD64_OpAMD64ADDQmodify(v) case OpAMD64ADDSD: return rewriteValueAMD64_OpAMD64ADDSD(v) case OpAMD64ADDSDload: return rewriteValueAMD64_OpAMD64ADDSDload(v) case OpAMD64ADDSS: return rewriteValueAMD64_OpAMD64ADDSS(v) case OpAMD64ADDSSload: return rewriteValueAMD64_OpAMD64ADDSSload(v) case OpAMD64ANDL: return rewriteValueAMD64_OpAMD64ANDL(v) case OpAMD64ANDLconst: return rewriteValueAMD64_OpAMD64ANDLconst(v) case OpAMD64ANDLconstmodify: return rewriteValueAMD64_OpAMD64ANDLconstmodify(v) case OpAMD64ANDLload: return rewriteValueAMD64_OpAMD64ANDLload(v) case OpAMD64ANDLmodify: return rewriteValueAMD64_OpAMD64ANDLmodify(v) case OpAMD64ANDNL: return rewriteValueAMD64_OpAMD64ANDNL(v) case OpAMD64ANDNQ: return rewriteValueAMD64_OpAMD64ANDNQ(v) case OpAMD64ANDQ: return rewriteValueAMD64_OpAMD64ANDQ(v) case OpAMD64ANDQconst: return rewriteValueAMD64_OpAMD64ANDQconst(v) case OpAMD64ANDQconstmodify: return rewriteValueAMD64_OpAMD64ANDQconstmodify(v) case OpAMD64ANDQload: return rewriteValueAMD64_OpAMD64ANDQload(v) case OpAMD64ANDQmodify: return rewriteValueAMD64_OpAMD64ANDQmodify(v) case OpAMD64BSFQ: return rewriteValueAMD64_OpAMD64BSFQ(v) case OpAMD64BSWAPL: return rewriteValueAMD64_OpAMD64BSWAPL(v) case OpAMD64BSWAPQ: return rewriteValueAMD64_OpAMD64BSWAPQ(v) case OpAMD64BTCLconst: return rewriteValueAMD64_OpAMD64BTCLconst(v) case OpAMD64BTCQconst: return rewriteValueAMD64_OpAMD64BTCQconst(v) case OpAMD64BTLconst: return rewriteValueAMD64_OpAMD64BTLconst(v) case OpAMD64BTQconst: return rewriteValueAMD64_OpAMD64BTQconst(v) case OpAMD64BTRLconst: return rewriteValueAMD64_OpAMD64BTRLconst(v) case OpAMD64BTRQconst: return rewriteValueAMD64_OpAMD64BTRQconst(v) case OpAMD64BTSLconst: return rewriteValueAMD64_OpAMD64BTSLconst(v) case OpAMD64BTSQconst: return rewriteValueAMD64_OpAMD64BTSQconst(v) case OpAMD64CMOVLCC: return rewriteValueAMD64_OpAMD64CMOVLCC(v) case OpAMD64CMOVLCS: return rewriteValueAMD64_OpAMD64CMOVLCS(v) case OpAMD64CMOVLEQ: return rewriteValueAMD64_OpAMD64CMOVLEQ(v) case OpAMD64CMOVLGE: return rewriteValueAMD64_OpAMD64CMOVLGE(v) case OpAMD64CMOVLGT: return rewriteValueAMD64_OpAMD64CMOVLGT(v) case OpAMD64CMOVLHI: return rewriteValueAMD64_OpAMD64CMOVLHI(v) case OpAMD64CMOVLLE: return rewriteValueAMD64_OpAMD64CMOVLLE(v) case OpAMD64CMOVLLS: return rewriteValueAMD64_OpAMD64CMOVLLS(v) case OpAMD64CMOVLLT: return rewriteValueAMD64_OpAMD64CMOVLLT(v) case OpAMD64CMOVLNE: return rewriteValueAMD64_OpAMD64CMOVLNE(v) case OpAMD64CMOVQCC: return rewriteValueAMD64_OpAMD64CMOVQCC(v) case OpAMD64CMOVQCS: return rewriteValueAMD64_OpAMD64CMOVQCS(v) case OpAMD64CMOVQEQ: return rewriteValueAMD64_OpAMD64CMOVQEQ(v) case OpAMD64CMOVQGE: return rewriteValueAMD64_OpAMD64CMOVQGE(v) case OpAMD64CMOVQGT: return rewriteValueAMD64_OpAMD64CMOVQGT(v) case OpAMD64CMOVQHI: return rewriteValueAMD64_OpAMD64CMOVQHI(v) case OpAMD64CMOVQLE: return rewriteValueAMD64_OpAMD64CMOVQLE(v) case OpAMD64CMOVQLS: return rewriteValueAMD64_OpAMD64CMOVQLS(v) case OpAMD64CMOVQLT: return rewriteValueAMD64_OpAMD64CMOVQLT(v) case OpAMD64CMOVQNE: return rewriteValueAMD64_OpAMD64CMOVQNE(v) case OpAMD64CMOVWCC: return rewriteValueAMD64_OpAMD64CMOVWCC(v) case OpAMD64CMOVWCS: return rewriteValueAMD64_OpAMD64CMOVWCS(v) case OpAMD64CMOVWEQ: return rewriteValueAMD64_OpAMD64CMOVWEQ(v) case OpAMD64CMOVWGE: return rewriteValueAMD64_OpAMD64CMOVWGE(v) case OpAMD64CMOVWGT: return rewriteValueAMD64_OpAMD64CMOVWGT(v) case OpAMD64CMOVWHI: return rewriteValueAMD64_OpAMD64CMOVWHI(v) case OpAMD64CMOVWLE: return rewriteValueAMD64_OpAMD64CMOVWLE(v) case OpAMD64CMOVWLS: return rewriteValueAMD64_OpAMD64CMOVWLS(v) case OpAMD64CMOVWLT: return rewriteValueAMD64_OpAMD64CMOVWLT(v) case OpAMD64CMOVWNE: return rewriteValueAMD64_OpAMD64CMOVWNE(v) case OpAMD64CMPB: return rewriteValueAMD64_OpAMD64CMPB(v) case OpAMD64CMPBconst: return rewriteValueAMD64_OpAMD64CMPBconst(v) case OpAMD64CMPBconstload: return rewriteValueAMD64_OpAMD64CMPBconstload(v) case OpAMD64CMPBload: return rewriteValueAMD64_OpAMD64CMPBload(v) case OpAMD64CMPL: return rewriteValueAMD64_OpAMD64CMPL(v) case OpAMD64CMPLconst: return rewriteValueAMD64_OpAMD64CMPLconst(v) case OpAMD64CMPLconstload: return rewriteValueAMD64_OpAMD64CMPLconstload(v) case OpAMD64CMPLload: return rewriteValueAMD64_OpAMD64CMPLload(v) case OpAMD64CMPQ: return rewriteValueAMD64_OpAMD64CMPQ(v) case OpAMD64CMPQconst: return rewriteValueAMD64_OpAMD64CMPQconst(v) case OpAMD64CMPQconstload: return rewriteValueAMD64_OpAMD64CMPQconstload(v) case OpAMD64CMPQload: return rewriteValueAMD64_OpAMD64CMPQload(v) case OpAMD64CMPW: return rewriteValueAMD64_OpAMD64CMPW(v) case OpAMD64CMPWconst: return rewriteValueAMD64_OpAMD64CMPWconst(v) case OpAMD64CMPWconstload: return rewriteValueAMD64_OpAMD64CMPWconstload(v) case OpAMD64CMPWload: return rewriteValueAMD64_OpAMD64CMPWload(v) case OpAMD64CMPXCHGLlock: return rewriteValueAMD64_OpAMD64CMPXCHGLlock(v) case OpAMD64CMPXCHGQlock: return rewriteValueAMD64_OpAMD64CMPXCHGQlock(v) case OpAMD64DIVSD: return rewriteValueAMD64_OpAMD64DIVSD(v) case OpAMD64DIVSDload: return rewriteValueAMD64_OpAMD64DIVSDload(v) case OpAMD64DIVSS: return rewriteValueAMD64_OpAMD64DIVSS(v) case OpAMD64DIVSSload: return rewriteValueAMD64_OpAMD64DIVSSload(v) case OpAMD64HMULL: return rewriteValueAMD64_OpAMD64HMULL(v) case OpAMD64HMULLU: return rewriteValueAMD64_OpAMD64HMULLU(v) case OpAMD64HMULQ: return rewriteValueAMD64_OpAMD64HMULQ(v) case OpAMD64HMULQU: return rewriteValueAMD64_OpAMD64HMULQU(v) case OpAMD64LEAL: return rewriteValueAMD64_OpAMD64LEAL(v) case OpAMD64LEAL1: return rewriteValueAMD64_OpAMD64LEAL1(v) case OpAMD64LEAL2: return rewriteValueAMD64_OpAMD64LEAL2(v) case OpAMD64LEAL4: return rewriteValueAMD64_OpAMD64LEAL4(v) case OpAMD64LEAL8: return rewriteValueAMD64_OpAMD64LEAL8(v) case OpAMD64LEAQ: return rewriteValueAMD64_OpAMD64LEAQ(v) case OpAMD64LEAQ1: return rewriteValueAMD64_OpAMD64LEAQ1(v) case OpAMD64LEAQ2: return rewriteValueAMD64_OpAMD64LEAQ2(v) case OpAMD64LEAQ4: return rewriteValueAMD64_OpAMD64LEAQ4(v) case OpAMD64LEAQ8: return rewriteValueAMD64_OpAMD64LEAQ8(v) case OpAMD64MOVBELstore: return rewriteValueAMD64_OpAMD64MOVBELstore(v) case OpAMD64MOVBEQstore: return rewriteValueAMD64_OpAMD64MOVBEQstore(v) case OpAMD64MOVBEWstore: return rewriteValueAMD64_OpAMD64MOVBEWstore(v) case OpAMD64MOVBQSX: return rewriteValueAMD64_OpAMD64MOVBQSX(v) case OpAMD64MOVBQSXload: return rewriteValueAMD64_OpAMD64MOVBQSXload(v) case OpAMD64MOVBQZX: return rewriteValueAMD64_OpAMD64MOVBQZX(v) case OpAMD64MOVBatomicload: return rewriteValueAMD64_OpAMD64MOVBatomicload(v) case OpAMD64MOVBload: return rewriteValueAMD64_OpAMD64MOVBload(v) case OpAMD64MOVBstore: return rewriteValueAMD64_OpAMD64MOVBstore(v) case OpAMD64MOVBstoreconst: return rewriteValueAMD64_OpAMD64MOVBstoreconst(v) case OpAMD64MOVLQSX: return rewriteValueAMD64_OpAMD64MOVLQSX(v) case OpAMD64MOVLQSXload: return rewriteValueAMD64_OpAMD64MOVLQSXload(v) case OpAMD64MOVLQZX: return rewriteValueAMD64_OpAMD64MOVLQZX(v) case OpAMD64MOVLatomicload: return rewriteValueAMD64_OpAMD64MOVLatomicload(v) case OpAMD64MOVLf2i: return rewriteValueAMD64_OpAMD64MOVLf2i(v) case OpAMD64MOVLi2f: return rewriteValueAMD64_OpAMD64MOVLi2f(v) case OpAMD64MOVLload: return rewriteValueAMD64_OpAMD64MOVLload(v) case OpAMD64MOVLstore: return rewriteValueAMD64_OpAMD64MOVLstore(v) case OpAMD64MOVLstoreconst: return rewriteValueAMD64_OpAMD64MOVLstoreconst(v) case OpAMD64MOVOload: return rewriteValueAMD64_OpAMD64MOVOload(v) case OpAMD64MOVOstore: return rewriteValueAMD64_OpAMD64MOVOstore(v) case OpAMD64MOVOstoreconst: return rewriteValueAMD64_OpAMD64MOVOstoreconst(v) case OpAMD64MOVQatomicload: return rewriteValueAMD64_OpAMD64MOVQatomicload(v) case OpAMD64MOVQf2i: return rewriteValueAMD64_OpAMD64MOVQf2i(v) case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f(v) case OpAMD64MOVQload: return rewriteValueAMD64_OpAMD64MOVQload(v) case OpAMD64MOVQstore: return rewriteValueAMD64_OpAMD64MOVQstore(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst(v) case OpAMD64MOVSDload: return rewriteValueAMD64_OpAMD64MOVSDload(v) case OpAMD64MOVSDstore: return rewriteValueAMD64_OpAMD64MOVSDstore(v) case OpAMD64MOVSSload: return rewriteValueAMD64_OpAMD64MOVSSload(v) case OpAMD64MOVSSstore: return rewriteValueAMD64_OpAMD64MOVSSstore(v) case OpAMD64MOVWQSX: return rewriteValueAMD64_OpAMD64MOVWQSX(v) case OpAMD64MOVWQSXload: return rewriteValueAMD64_OpAMD64MOVWQSXload(v) case OpAMD64MOVWQZX: return rewriteValueAMD64_OpAMD64MOVWQZX(v) case OpAMD64MOVWload: return rewriteValueAMD64_OpAMD64MOVWload(v) case OpAMD64MOVWstore: return rewriteValueAMD64_OpAMD64MOVWstore(v) case OpAMD64MOVWstoreconst: return rewriteValueAMD64_OpAMD64MOVWstoreconst(v) case OpAMD64MULL: return rewriteValueAMD64_OpAMD64MULL(v) case OpAMD64MULLconst: return rewriteValueAMD64_OpAMD64MULLconst(v) case OpAMD64MULQ: return rewriteValueAMD64_OpAMD64MULQ(v) case OpAMD64MULQconst: return rewriteValueAMD64_OpAMD64MULQconst(v) case OpAMD64MULSD: return rewriteValueAMD64_OpAMD64MULSD(v) case OpAMD64MULSDload: return rewriteValueAMD64_OpAMD64MULSDload(v) case OpAMD64MULSS: return rewriteValueAMD64_OpAMD64MULSS(v) case OpAMD64MULSSload: return rewriteValueAMD64_OpAMD64MULSSload(v) case OpAMD64NEGL: return rewriteValueAMD64_OpAMD64NEGL(v) case OpAMD64NEGQ: return rewriteValueAMD64_OpAMD64NEGQ(v) case OpAMD64NOTL: return rewriteValueAMD64_OpAMD64NOTL(v) case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ(v) case OpAMD64ORL: return rewriteValueAMD64_OpAMD64ORL(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst(v) case OpAMD64ORLconstmodify: return rewriteValueAMD64_OpAMD64ORLconstmodify(v) case OpAMD64ORLload: return rewriteValueAMD64_OpAMD64ORLload(v) case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify(v) case OpAMD64ORQ: return rewriteValueAMD64_OpAMD64ORQ(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst(v) case OpAMD64ORQconstmodify: return rewriteValueAMD64_OpAMD64ORQconstmodify(v) case OpAMD64ORQload: return rewriteValueAMD64_OpAMD64ORQload(v) case OpAMD64ORQmodify: return rewriteValueAMD64_OpAMD64ORQmodify(v) case OpAMD64ROLB: return rewriteValueAMD64_OpAMD64ROLB(v) case OpAMD64ROLBconst: return rewriteValueAMD64_OpAMD64ROLBconst(v) case OpAMD64ROLL: return rewriteValueAMD64_OpAMD64ROLL(v) case OpAMD64ROLLconst: return rewriteValueAMD64_OpAMD64ROLLconst(v) case OpAMD64ROLQ: return rewriteValueAMD64_OpAMD64ROLQ(v) case OpAMD64ROLQconst: return rewriteValueAMD64_OpAMD64ROLQconst(v) case OpAMD64ROLW: return rewriteValueAMD64_OpAMD64ROLW(v) case OpAMD64ROLWconst: return rewriteValueAMD64_OpAMD64ROLWconst(v) case OpAMD64RORB: return rewriteValueAMD64_OpAMD64RORB(v) case OpAMD64RORL: return rewriteValueAMD64_OpAMD64RORL(v) case OpAMD64RORQ: return rewriteValueAMD64_OpAMD64RORQ(v) case OpAMD64RORW: return rewriteValueAMD64_OpAMD64RORW(v) case OpAMD64SARB: return rewriteValueAMD64_OpAMD64SARB(v) case OpAMD64SARBconst: return rewriteValueAMD64_OpAMD64SARBconst(v) case OpAMD64SARL: return rewriteValueAMD64_OpAMD64SARL(v) case OpAMD64SARLconst: return rewriteValueAMD64_OpAMD64SARLconst(v) case OpAMD64SARQ: return rewriteValueAMD64_OpAMD64SARQ(v) case OpAMD64SARQconst: return rewriteValueAMD64_OpAMD64SARQconst(v) case OpAMD64SARW: return rewriteValueAMD64_OpAMD64SARW(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst(v) case OpAMD64SARXLload: return rewriteValueAMD64_OpAMD64SARXLload(v) case OpAMD64SARXQload: return rewriteValueAMD64_OpAMD64SARXQload(v) case OpAMD64SBBLcarrymask: return rewriteValueAMD64_OpAMD64SBBLcarrymask(v) case OpAMD64SBBQ: return rewriteValueAMD64_OpAMD64SBBQ(v) case OpAMD64SBBQcarrymask: return rewriteValueAMD64_OpAMD64SBBQcarrymask(v) case OpAMD64SBBQconst: return rewriteValueAMD64_OpAMD64SBBQconst(v) case OpAMD64SETA: return rewriteValueAMD64_OpAMD64SETA(v) case OpAMD64SETAE: return rewriteValueAMD64_OpAMD64SETAE(v) case OpAMD64SETAEstore: return rewriteValueAMD64_OpAMD64SETAEstore(v) case OpAMD64SETAstore: return rewriteValueAMD64_OpAMD64SETAstore(v) case OpAMD64SETB: return rewriteValueAMD64_OpAMD64SETB(v) case OpAMD64SETBE: return rewriteValueAMD64_OpAMD64SETBE(v) case OpAMD64SETBEstore: return rewriteValueAMD64_OpAMD64SETBEstore(v) case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore(v) case OpAMD64SETEQ: return rewriteValueAMD64_OpAMD64SETEQ(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore(v) case OpAMD64SETG: return rewriteValueAMD64_OpAMD64SETG(v) case OpAMD64SETGE: return rewriteValueAMD64_OpAMD64SETGE(v) case OpAMD64SETGEstore: return rewriteValueAMD64_OpAMD64SETGEstore(v) case OpAMD64SETGstore: return rewriteValueAMD64_OpAMD64SETGstore(v) case OpAMD64SETL: return rewriteValueAMD64_OpAMD64SETL(v) case OpAMD64SETLE: return rewriteValueAMD64_OpAMD64SETLE(v) case OpAMD64SETLEstore: return rewriteValueAMD64_OpAMD64SETLEstore(v) case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore(v) case OpAMD64SETNE: return rewriteValueAMD64_OpAMD64SETNE(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore(v) case OpAMD64SHLL: return rewriteValueAMD64_OpAMD64SHLL(v) case OpAMD64SHLLconst: return rewriteValueAMD64_OpAMD64SHLLconst(v) case OpAMD64SHLQ: return rewriteValueAMD64_OpAMD64SHLQ(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst(v) case OpAMD64SHLXLload: return rewriteValueAMD64_OpAMD64SHLXLload(v) case OpAMD64SHLXQload: return rewriteValueAMD64_OpAMD64SHLXQload(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB(v) case OpAMD64SHRBconst: return rewriteValueAMD64_OpAMD64SHRBconst(v) case OpAMD64SHRL: return rewriteValueAMD64_OpAMD64SHRL(v) case OpAMD64SHRLconst: return rewriteValueAMD64_OpAMD64SHRLconst(v) case OpAMD64SHRQ: return rewriteValueAMD64_OpAMD64SHRQ(v) case OpAMD64SHRQconst: return rewriteValueAMD64_OpAMD64SHRQconst(v) case OpAMD64SHRW: return rewriteValueAMD64_OpAMD64SHRW(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst(v) case OpAMD64SHRXLload: return rewriteValueAMD64_OpAMD64SHRXLload(v) case OpAMD64SHRXQload: return rewriteValueAMD64_OpAMD64SHRXQload(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL(v) case OpAMD64SUBLconst: return rewriteValueAMD64_OpAMD64SUBLconst(v) case OpAMD64SUBLload: return rewriteValueAMD64_OpAMD64SUBLload(v) case OpAMD64SUBLmodify: return rewriteValueAMD64_OpAMD64SUBLmodify(v) case OpAMD64SUBQ: return rewriteValueAMD64_OpAMD64SUBQ(v) case OpAMD64SUBQborrow: return rewriteValueAMD64_OpAMD64SUBQborrow(v) case OpAMD64SUBQconst: return rewriteValueAMD64_OpAMD64SUBQconst(v) case OpAMD64SUBQload: return rewriteValueAMD64_OpAMD64SUBQload(v) case OpAMD64SUBQmodify: return rewriteValueAMD64_OpAMD64SUBQmodify(v) case OpAMD64SUBSD: return rewriteValueAMD64_OpAMD64SUBSD(v) case OpAMD64SUBSDload: return rewriteValueAMD64_OpAMD64SUBSDload(v) case OpAMD64SUBSS: return rewriteValueAMD64_OpAMD64SUBSS(v) case OpAMD64SUBSSload: return rewriteValueAMD64_OpAMD64SUBSSload(v) case OpAMD64TESTB: return rewriteValueAMD64_OpAMD64TESTB(v) case OpAMD64TESTBconst: return rewriteValueAMD64_OpAMD64TESTBconst(v) case OpAMD64TESTL: return rewriteValueAMD64_OpAMD64TESTL(v) case OpAMD64TESTLconst: return rewriteValueAMD64_OpAMD64TESTLconst(v) case OpAMD64TESTQ: return rewriteValueAMD64_OpAMD64TESTQ(v) case OpAMD64TESTQconst: return rewriteValueAMD64_OpAMD64TESTQconst(v) case OpAMD64TESTW: return rewriteValueAMD64_OpAMD64TESTW(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock(v) case OpAMD64XADDQlock: return rewriteValueAMD64_OpAMD64XADDQlock(v) case OpAMD64XCHGL: return rewriteValueAMD64_OpAMD64XCHGL(v) case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ(v) case OpAMD64XORL: return rewriteValueAMD64_OpAMD64XORL(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst(v) case OpAMD64XORLconstmodify: return rewriteValueAMD64_OpAMD64XORLconstmodify(v) case OpAMD64XORLload: return rewriteValueAMD64_OpAMD64XORLload(v) case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify(v) case OpAMD64XORQ: return rewriteValueAMD64_OpAMD64XORQ(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst(v) case OpAMD64XORQconstmodify: return rewriteValueAMD64_OpAMD64XORQconstmodify(v) case OpAMD64XORQload: return rewriteValueAMD64_OpAMD64XORQload(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify(v) case OpAdd16: v.Op = OpAMD64ADDL return true case OpAdd32: v.Op = OpAMD64ADDL return true case OpAdd32F: v.Op = OpAMD64ADDSS return true case OpAdd64: v.Op = OpAMD64ADDQ return true case OpAdd64F: v.Op = OpAMD64ADDSD return true case OpAdd8: v.Op = OpAMD64ADDL return true case OpAddPtr: v.Op = OpAMD64ADDQ return true case OpAddr: return rewriteValueAMD64_OpAddr(v) case OpAnd16: v.Op = OpAMD64ANDL return true case OpAnd32: v.Op = OpAMD64ANDL return true case OpAnd64: v.Op = OpAMD64ANDQ return true case OpAnd8: v.Op = OpAMD64ANDL return true case OpAndB: v.Op = OpAMD64ANDL return true case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32(v) case OpAtomicAdd64: return rewriteValueAMD64_OpAtomicAdd64(v) case OpAtomicAnd32: return rewriteValueAMD64_OpAtomicAnd32(v) case OpAtomicAnd8: return rewriteValueAMD64_OpAtomicAnd8(v) case OpAtomicCompareAndSwap32: return rewriteValueAMD64_OpAtomicCompareAndSwap32(v) case OpAtomicCompareAndSwap64: return rewriteValueAMD64_OpAtomicCompareAndSwap64(v) case OpAtomicExchange32: return rewriteValueAMD64_OpAtomicExchange32(v) case OpAtomicExchange64: return rewriteValueAMD64_OpAtomicExchange64(v) case OpAtomicLoad32: return rewriteValueAMD64_OpAtomicLoad32(v) case OpAtomicLoad64: return rewriteValueAMD64_OpAtomicLoad64(v) case OpAtomicLoad8: return rewriteValueAMD64_OpAtomicLoad8(v) case OpAtomicLoadPtr: return rewriteValueAMD64_OpAtomicLoadPtr(v) case OpAtomicOr32: return rewriteValueAMD64_OpAtomicOr32(v) case OpAtomicOr8: return rewriteValueAMD64_OpAtomicOr8(v) case OpAtomicStore32: return rewriteValueAMD64_OpAtomicStore32(v) case OpAtomicStore64: return rewriteValueAMD64_OpAtomicStore64(v) case OpAtomicStore8: return rewriteValueAMD64_OpAtomicStore8(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB(v) case OpAvg64u: v.Op = OpAMD64AVGQU return true case OpBitLen16: return rewriteValueAMD64_OpBitLen16(v) case OpBitLen32: return rewriteValueAMD64_OpBitLen32(v) case OpBitLen64: return rewriteValueAMD64_OpBitLen64(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8(v) case OpBswap32: v.Op = OpAMD64BSWAPL return true case OpBswap64: v.Op = OpAMD64BSWAPQ return true case OpCeil: return rewriteValueAMD64_OpCeil(v) case OpClosureCall: v.Op = OpAMD64CALLclosure return true case OpCom16: v.Op = OpAMD64NOTL return true case OpCom32: v.Op = OpAMD64NOTL return true case OpCom64: v.Op = OpAMD64NOTQ return true case OpCom8: v.Op = OpAMD64NOTL return true case OpCondSelect: return rewriteValueAMD64_OpCondSelect(v) case OpConst16: return rewriteValueAMD64_OpConst16(v) case OpConst32: v.Op = OpAMD64MOVLconst return true case OpConst32F: v.Op = OpAMD64MOVSSconst return true case OpConst64: v.Op = OpAMD64MOVQconst return true case OpConst64F: v.Op = OpAMD64MOVSDconst return true case OpConst8: return rewriteValueAMD64_OpConst8(v) case OpConstBool: return rewriteValueAMD64_OpConstBool(v) case OpConstNil: return rewriteValueAMD64_OpConstNil(v) case OpCtz16: return rewriteValueAMD64_OpCtz16(v) case OpCtz16NonZero: return rewriteValueAMD64_OpCtz16NonZero(v) case OpCtz32: return rewriteValueAMD64_OpCtz32(v) case OpCtz32NonZero: return rewriteValueAMD64_OpCtz32NonZero(v) case OpCtz64: return rewriteValueAMD64_OpCtz64(v) case OpCtz64NonZero: return rewriteValueAMD64_OpCtz64NonZero(v) case OpCtz8: return rewriteValueAMD64_OpCtz8(v) case OpCtz8NonZero: return rewriteValueAMD64_OpCtz8NonZero(v) case OpCvt32Fto32: v.Op = OpAMD64CVTTSS2SL return true case OpCvt32Fto64: v.Op = OpAMD64CVTTSS2SQ return true case OpCvt32Fto64F: v.Op = OpAMD64CVTSS2SD return true case OpCvt32to32F: v.Op = OpAMD64CVTSL2SS return true case OpCvt32to64F: v.Op = OpAMD64CVTSL2SD return true case OpCvt64Fto32: v.Op = OpAMD64CVTTSD2SL return true case OpCvt64Fto32F: v.Op = OpAMD64CVTSD2SS return true case OpCvt64Fto64: v.Op = OpAMD64CVTTSD2SQ return true case OpCvt64to32F: v.Op = OpAMD64CVTSQ2SS return true case OpCvt64to64F: v.Op = OpAMD64CVTSQ2SD return true case OpCvtBoolToUint8: v.Op = OpCopy return true case OpDiv128u: v.Op = OpAMD64DIVQU2 return true case OpDiv16: return rewriteValueAMD64_OpDiv16(v) case OpDiv16u: return rewriteValueAMD64_OpDiv16u(v) case OpDiv32: return rewriteValueAMD64_OpDiv32(v) case OpDiv32F: v.Op = OpAMD64DIVSS return true case OpDiv32u: return rewriteValueAMD64_OpDiv32u(v) case OpDiv64: return rewriteValueAMD64_OpDiv64(v) case OpDiv64F: v.Op = OpAMD64DIVSD return true case OpDiv64u: return rewriteValueAMD64_OpDiv64u(v) case OpDiv8: return rewriteValueAMD64_OpDiv8(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u(v) case OpEq16: return rewriteValueAMD64_OpEq16(v) case OpEq32: return rewriteValueAMD64_OpEq32(v) case OpEq32F: return rewriteValueAMD64_OpEq32F(v) case OpEq64: return rewriteValueAMD64_OpEq64(v) case OpEq64F: return rewriteValueAMD64_OpEq64F(v) case OpEq8: return rewriteValueAMD64_OpEq8(v) case OpEqB: return rewriteValueAMD64_OpEqB(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr(v) case OpFMA: return rewriteValueAMD64_OpFMA(v) case OpFloor: return rewriteValueAMD64_OpFloor(v) case OpGetCallerPC: v.Op = OpAMD64LoweredGetCallerPC return true case OpGetCallerSP: v.Op = OpAMD64LoweredGetCallerSP return true case OpGetClosurePtr: v.Op = OpAMD64LoweredGetClosurePtr return true case OpGetG: return rewriteValueAMD64_OpGetG(v) case OpHasCPUFeature: return rewriteValueAMD64_OpHasCPUFeature(v) case OpHmul32: v.Op = OpAMD64HMULL return true case OpHmul32u: v.Op = OpAMD64HMULLU return true case OpHmul64: v.Op = OpAMD64HMULQ return true case OpHmul64u: v.Op = OpAMD64HMULQU return true case OpInterCall: v.Op = OpAMD64CALLinter return true case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueAMD64_OpIsSliceInBounds(v) case OpLeq16: return rewriteValueAMD64_OpLeq16(v) case OpLeq16U: return rewriteValueAMD64_OpLeq16U(v) case OpLeq32: return rewriteValueAMD64_OpLeq32(v) case OpLeq32F: return rewriteValueAMD64_OpLeq32F(v) case OpLeq32U: return rewriteValueAMD64_OpLeq32U(v) case OpLeq64: return rewriteValueAMD64_OpLeq64(v) case OpLeq64F: return rewriteValueAMD64_OpLeq64F(v) case OpLeq64U: return rewriteValueAMD64_OpLeq64U(v) case OpLeq8: return rewriteValueAMD64_OpLeq8(v) case OpLeq8U: return rewriteValueAMD64_OpLeq8U(v) case OpLess16: return rewriteValueAMD64_OpLess16(v) case OpLess16U: return rewriteValueAMD64_OpLess16U(v) case OpLess32: return rewriteValueAMD64_OpLess32(v) case OpLess32F: return rewriteValueAMD64_OpLess32F(v) case OpLess32U: return rewriteValueAMD64_OpLess32U(v) case OpLess64: return rewriteValueAMD64_OpLess64(v) case OpLess64F: return rewriteValueAMD64_OpLess64F(v) case OpLess64U: return rewriteValueAMD64_OpLess64U(v) case OpLess8: return rewriteValueAMD64_OpLess8(v) case OpLess8U: return rewriteValueAMD64_OpLess8U(v) case OpLoad: return rewriteValueAMD64_OpLoad(v) case OpLocalAddr: return rewriteValueAMD64_OpLocalAddr(v) case OpLsh16x16: return rewriteValueAMD64_OpLsh16x16(v) case OpLsh16x32: return rewriteValueAMD64_OpLsh16x32(v) case OpLsh16x64: return rewriteValueAMD64_OpLsh16x64(v) case OpLsh16x8: return rewriteValueAMD64_OpLsh16x8(v) case OpLsh32x16: return rewriteValueAMD64_OpLsh32x16(v) case OpLsh32x32: return rewriteValueAMD64_OpLsh32x32(v) case OpLsh32x64: return rewriteValueAMD64_OpLsh32x64(v) case OpLsh32x8: return rewriteValueAMD64_OpLsh32x8(v) case OpLsh64x16: return rewriteValueAMD64_OpLsh64x16(v) case OpLsh64x32: return rewriteValueAMD64_OpLsh64x32(v) case OpLsh64x64: return rewriteValueAMD64_OpLsh64x64(v) case OpLsh64x8: return rewriteValueAMD64_OpLsh64x8(v) case OpLsh8x16: return rewriteValueAMD64_OpLsh8x16(v) case OpLsh8x32: return rewriteValueAMD64_OpLsh8x32(v) case OpLsh8x64: return rewriteValueAMD64_OpLsh8x64(v) case OpLsh8x8: return rewriteValueAMD64_OpLsh8x8(v) case OpMod16: return rewriteValueAMD64_OpMod16(v) case OpMod16u: return rewriteValueAMD64_OpMod16u(v) case OpMod32: return rewriteValueAMD64_OpMod32(v) case OpMod32u: return rewriteValueAMD64_OpMod32u(v) case OpMod64: return rewriteValueAMD64_OpMod64(v) case OpMod64u: return rewriteValueAMD64_OpMod64u(v) case OpMod8: return rewriteValueAMD64_OpMod8(v) case OpMod8u: return rewriteValueAMD64_OpMod8u(v) case OpMove: return rewriteValueAMD64_OpMove(v) case OpMul16: v.Op = OpAMD64MULL return true case OpMul32: v.Op = OpAMD64MULL return true case OpMul32F: v.Op = OpAMD64MULSS return true case OpMul64: v.Op = OpAMD64MULQ return true case OpMul64F: v.Op = OpAMD64MULSD return true case OpMul64uhilo: v.Op = OpAMD64MULQU2 return true case OpMul8: v.Op = OpAMD64MULL return true case OpNeg16: v.Op = OpAMD64NEGL return true case OpNeg32: v.Op = OpAMD64NEGL return true case OpNeg32F: return rewriteValueAMD64_OpNeg32F(v) case OpNeg64: v.Op = OpAMD64NEGQ return true case OpNeg64F: return rewriteValueAMD64_OpNeg64F(v) case OpNeg8: v.Op = OpAMD64NEGL return true case OpNeq16: return rewriteValueAMD64_OpNeq16(v) case OpNeq32: return rewriteValueAMD64_OpNeq32(v) case OpNeq32F: return rewriteValueAMD64_OpNeq32F(v) case OpNeq64: return rewriteValueAMD64_OpNeq64(v) case OpNeq64F: return rewriteValueAMD64_OpNeq64F(v) case OpNeq8: return rewriteValueAMD64_OpNeq8(v) case OpNeqB: return rewriteValueAMD64_OpNeqB(v) case OpNeqPtr: return rewriteValueAMD64_OpNeqPtr(v) case OpNilCheck: v.Op = OpAMD64LoweredNilCheck return true case OpNot: return rewriteValueAMD64_OpNot(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr(v) case OpOr16: v.Op = OpAMD64ORL return true case OpOr32: v.Op = OpAMD64ORL return true case OpOr64: v.Op = OpAMD64ORQ return true case OpOr8: v.Op = OpAMD64ORL return true case OpOrB: v.Op = OpAMD64ORL return true case OpPanicBounds: return rewriteValueAMD64_OpPanicBounds(v) case OpPopCount16: return rewriteValueAMD64_OpPopCount16(v) case OpPopCount32: v.Op = OpAMD64POPCNTL return true case OpPopCount64: v.Op = OpAMD64POPCNTQ return true case OpPopCount8: return rewriteValueAMD64_OpPopCount8(v) case OpPrefetchCache: v.Op = OpAMD64PrefetchT0 return true case OpPrefetchCacheStreamed: v.Op = OpAMD64PrefetchNTA return true case OpRotateLeft16: v.Op = OpAMD64ROLW return true case OpRotateLeft32: v.Op = OpAMD64ROLL return true case OpRotateLeft64: v.Op = OpAMD64ROLQ return true case OpRotateLeft8: v.Op = OpAMD64ROLB return true case OpRound32F: v.Op = OpCopy return true case OpRound64F: v.Op = OpCopy return true case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven(v) case OpRsh16Ux16: return rewriteValueAMD64_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValueAMD64_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValueAMD64_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValueAMD64_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValueAMD64_OpRsh16x16(v) case OpRsh16x32: return rewriteValueAMD64_OpRsh16x32(v) case OpRsh16x64: return rewriteValueAMD64_OpRsh16x64(v) case OpRsh16x8: return rewriteValueAMD64_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValueAMD64_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValueAMD64_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValueAMD64_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValueAMD64_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValueAMD64_OpRsh32x16(v) case OpRsh32x32: return rewriteValueAMD64_OpRsh32x32(v) case OpRsh32x64: return rewriteValueAMD64_OpRsh32x64(v) case OpRsh32x8: return rewriteValueAMD64_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValueAMD64_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValueAMD64_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValueAMD64_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValueAMD64_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValueAMD64_OpRsh64x16(v) case OpRsh64x32: return rewriteValueAMD64_OpRsh64x32(v) case OpRsh64x64: return rewriteValueAMD64_OpRsh64x64(v) case OpRsh64x8: return rewriteValueAMD64_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValueAMD64_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValueAMD64_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValueAMD64_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValueAMD64_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValueAMD64_OpRsh8x16(v) case OpRsh8x32: return rewriteValueAMD64_OpRsh8x32(v) case OpRsh8x64: return rewriteValueAMD64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8(v) case OpSelect0: return rewriteValueAMD64_OpSelect0(v) case OpSelect1: return rewriteValueAMD64_OpSelect1(v) case OpSelectN: return rewriteValueAMD64_OpSelectN(v) case OpSignExt16to32: v.Op = OpAMD64MOVWQSX return true case OpSignExt16to64: v.Op = OpAMD64MOVWQSX return true case OpSignExt32to64: v.Op = OpAMD64MOVLQSX return true case OpSignExt8to16: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to32: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to64: v.Op = OpAMD64MOVBQSX return true case OpSlicemask: return rewriteValueAMD64_OpSlicemask(v) case OpSpectreIndex: return rewriteValueAMD64_OpSpectreIndex(v) case OpSpectreSliceIndex: return rewriteValueAMD64_OpSpectreSliceIndex(v) case OpSqrt: v.Op = OpAMD64SQRTSD return true case OpSqrt32: v.Op = OpAMD64SQRTSS return true case OpStaticCall: v.Op = OpAMD64CALLstatic return true case OpStore: return rewriteValueAMD64_OpStore(v) case OpSub16: v.Op = OpAMD64SUBL return true case OpSub32: v.Op = OpAMD64SUBL return true case OpSub32F: v.Op = OpAMD64SUBSS return true case OpSub64: v.Op = OpAMD64SUBQ return true case OpSub64F: v.Op = OpAMD64SUBSD return true case OpSub8: v.Op = OpAMD64SUBL return true case OpSubPtr: v.Op = OpAMD64SUBQ return true case OpTailCall: v.Op = OpAMD64CALLtail return true case OpTrunc: return rewriteValueAMD64_OpTrunc(v) case OpTrunc16to8: v.Op = OpCopy return true case OpTrunc32to16: v.Op = OpCopy return true case OpTrunc32to8: v.Op = OpCopy return true case OpTrunc64to16: v.Op = OpCopy return true case OpTrunc64to32: v.Op = OpCopy return true case OpTrunc64to8: v.Op = OpCopy return true case OpWB: v.Op = OpAMD64LoweredWB return true case OpXor16: v.Op = OpAMD64XORL return true case OpXor32: v.Op = OpAMD64XORL return true case OpXor64: v.Op = OpAMD64XORQ return true case OpXor8: v.Op = OpAMD64XORL return true case OpZero: return rewriteValueAMD64_OpZero(v) case OpZeroExt16to32: v.Op = OpAMD64MOVWQZX return true case OpZeroExt16to64: v.Op = OpAMD64MOVWQZX return true case OpZeroExt32to64: v.Op = OpAMD64MOVLQZX return true case OpZeroExt8to16: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to32: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to64: v.Op = OpAMD64MOVBQZX return true } return false } func rewriteValueAMD64_OpAMD64ADCQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) // result: (ADCQconst x [int32(c)] carry) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) carry := v_2 if !(is32Bit(c)) { continue } v.reset(OpAMD64ADCQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, carry) return true } break } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQcarry) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64ADCQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQconst x [c] (FlagEQ)) // result: (ADDQconstcarry x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDL x (MOVLconst [c])) // result: (ADDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAL2) v.AddArg2(y, x) return true } } break } // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAL { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL { continue } y := v_1.Args[0] v.reset(OpAMD64SUBL) v.AddArg2(x, y) return true } break } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDLconst [c] (ADDL x y)) // result: (LEAL1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (SHLLconst [1] x)) // result: (LEAL1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // result: (MOVLconst [c+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c + d) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // result: (ADDLconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDLconst [off] x:(SP)) // result: (LEAL [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (ADDL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ADDQ x (MOVLconst [c])) // result: (ADDQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAQ2) v.AddArg2(y, x) return true } } break } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ { continue } y := v_1.Args[0] v.reset(OpAMD64SUBQ) v.AddArg2(x, y) return true } break } // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQcarry(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQcarry x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconstcarry x [int32(c)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDQconst [c] (ADDQ x y)) // result: (LEAQ1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (SHLQconst [1] x)) // result: (LEAQ1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDQconst [c] (LEAQ [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ADDQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) + d) return true } // match: (ADDQconst [c] (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (ADDQconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDQconst [off] x:(SP)) // result: (LEAQ [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (ADDQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (ADDSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (ADDSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ANDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTRL) v.AddArg2(x, y) return true } break } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } break } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ANDL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDL x (NOTL y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTL { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNL) v.AddArg2(x, y) return true } break } // match: (ANDL x (NEGL x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIL) v.AddArg(x) return true } break } // match: (ANDL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSRL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSRL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDLconst [c] x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDLconst [c] (BTRLconst [d] x)) // result: (ANDLconst [c &^ (1<= 128 // result: (BTRQconst [int8(log64(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log64(^c))) v.AddArg(x) return true } break } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ANDQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDQ x (NOTQ y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTQ { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNQ) v.AddArg2(x, y) return true } break } // match: (ANDQ x (NEGQ x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIQ) v.AddArg(x) return true } break } // match: (ANDQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSRQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSRQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDQconst [c] x) // cond: isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRQconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDQconst [c] (ANDQconst [d] x)) // result: (ANDQconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDQconst [c] (BTRQconst [d] x)) // cond: is32Bit(int64(c) &^ (1< [1<<8] (MOVBQZX x))) // result: (BSFQ (ORQconst [1<<8] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVBQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 8) v0.AddArg(x) v.AddArg(v0) return true } // match: (BSFQ (ORQconst [1<<16] (MOVWQZX x))) // result: (BSFQ (ORQconst [1<<16] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVWQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPL(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPL (BSWAPL p)) // result: p for { if v_0.Op != OpAMD64BSWAPL { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPL x:(MOVLload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPL (MOVBELload [i] {s} p m)) // result: (MOVLload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBELload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPQ(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPQ (BSWAPQ p)) // result: p for { if v_0.Op != OpAMD64BSWAPQ { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPQ x:(MOVQload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPQ (MOVBEQload [i] {s} p m)) // result: (MOVQload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBEQload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BTCLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTCLconst [c] (XORLconst [d] x)) // result: (XORLconst [d ^ 1<d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 32) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTLconst [c] (SHLLconst [d] x)) // cond: c>d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } // match: (BTLconst [0] s:(SHRXL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTQconst(v *Value) bool { v_0 := v.Args[0] // match: (BTQconst [c] (SHRQconst [d] x)) // cond: (c+d)<64 // result: (BTQconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 64) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTQconst [c] (SHLQconst [d] x)) // cond: c>d // result: (BTQconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTQconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTRLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTRLconst [c] (BTSLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTSLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (BTCLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTCLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [d &^ (1<uint8(y) // result: (FlagLT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) < y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x) y && uint8(x) < uint8(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) > y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int8(m) && int8(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPBconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTB x y) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, y) return true } // match: (CMPBconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTBconst [int8(c)] x) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt8(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVBload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPBload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPL x (MOVLconst [c])) // result: (CMPLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64CMPLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // result: (InvertFlags (CMPLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPL y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x==y // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x == y) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: xuint32(y) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x < y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x) y && uint32(x) < uint32(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x > y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) // result: (FlagLT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x < y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x)>uint64(y) // result: (FlagGT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x > y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQ l:(MOVQload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPQload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPQ x l:(MOVQload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPQload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPQload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x==int64(y) // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x == int64(y)) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: xuint64(int64(y)) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x < int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x) int64(y) && uint64(x) < uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x)>uint64(int64(y)) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x > int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQconst (MOVBQZX _) [c]) // cond: 0xFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVWQZX _) [c]) // cond: 0xFFFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (SHRQconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 64 && (1<uint16(y) // result: (FlagLT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) < y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x) y && uint16(x) < uint16(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) > y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int16(m) && int16(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPWconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTW x y) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, y) return true } // match: (CMPWconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTWconst [int16(c)] x) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt16(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVWload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPWload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGLlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGQlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64HMULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULL x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULL y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULLU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULLU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULLU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULLU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQ x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQ y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64LEAL(v *Value) bool { v_0 := v.Args[0] // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { v_0 := v.Args[0] // match: (LEAQ [c] {s} (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAQ [c] {s} (ADDQ x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg(x) return true } // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ2 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ4 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ8 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64LEAQ { continue } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(y, x) return true } } break } // match: (LEAQ1 [0] x y) // cond: v.Aux == nil // result: (ADDQ x y) for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 y := v_1 if !(v.Aux == nil) { break } v.reset(OpAMD64ADDQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAQ2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil // result: (LEAQ4 [off1+2*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + 2*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ2 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ2 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAQ4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil // result: (LEAQ8 [off1+4*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + 4*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ4 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ4 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAQ8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ8 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ8 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBELstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBELstore [i] {s} p (BSWAPL x) m) // result: (MOVLstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPL { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEQstore [i] {s} p (BSWAPQ x) m) // result: (MOVQstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPQ { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7f) v.AddArg(x) return true } // match: (MOVBQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x) // cond: zeroUpper56Bits(x,3) // result: x for { x := v_0 if !(zeroUpper56Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVBQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xff) v.AddArg(x) return true } // match: (MOVBQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read8(sym, int64(off)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read8(sym, int64(off)))) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) // cond: y.Uses == 1 // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETL { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) // cond: y.Uses == 1 // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETLE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) // cond: y.Uses == 1 // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETG { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) // cond: y.Uses == 1 // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETGE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) // cond: y.Uses == 1 // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETEQ { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) // cond: y.Uses == 1 // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETNE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) // cond: y.Uses == 1 // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETB { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) // cond: y.Uses == 1 // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETBE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) // cond: y.Uses == 1 // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETA { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) // cond: y.Uses == 1 // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETAE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstore [i-1] {s} p (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p1 w x0:(MOVBstore [i] {s} p0 (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0) // result: (MOVWstore [i] {s} p0 (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-1 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-3 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 3) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p3 w x2:(MOVBstore [i] {s} p2 (SHRLconst [8] w) x1:(MOVBstore [i] {s} p1 (SHRLconst [16] w) x0:(MOVBstore [i] {s} p0 (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2) // result: (MOVLstore [i] {s} p0 (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p3 := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i-1 || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] if p != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i-2 || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i-3 || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i-4 || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-5 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-6 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-7 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 7) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p7 w x6:(MOVBstore [i] {s} p6 (SHRQconst [8] w) x5:(MOVBstore [i] {s} p5 (SHRQconst [16] w) x4:(MOVBstore [i] {s} p4 (SHRQconst [24] w) x3:(MOVBstore [i] {s} p3 (SHRQconst [32] w) x2:(MOVBstore [i] {s} p2 (SHRQconst [40] w) x1:(MOVBstore [i] {s} p1 (SHRQconst [48] w) x0:(MOVBstore [i] {s} p0 (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i] {s} p0 (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p7 := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] p6 := x6.Args[0] x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] p5 := x5.Args[0] x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] p4 := x4.Args[0] x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] p3 := x3.Args[0] x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRWconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [c3] {s} p3 (SHRQconst [56] w) x1:(MOVWstore [c2] {s} p2 (SHRQconst [40] w) x2:(MOVLstore [c1] {s} p1 (SHRQconst [8] w) x3:(MOVBstore [c0] {s} p0 w mem)))) // cond: x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1 + c0 - c1)) && sequentialAddresses(p0, p2, int64(5 + c0 - c2)) && sequentialAddresses(p0, p3, int64(7 + c0 - c3)) && clobber(x1, x2, x3) // result: (MOVQstore [c0] {s} p0 w mem) for { c3 := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p3 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 56 { break } w := v_1.Args[0] x1 := v_2 if x1.Op != OpAMD64MOVWstore { break } c2 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p2 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 40 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpAMD64MOVLstore { break } c1 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p1 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpAMD64MOVBstore { break } c0 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { break } mem := x3.Args[2] p0 := x3.Args[0] if w != x3.Args[1] || !(x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1+c0-c1)) && sequentialAddresses(p0, p2, int64(5+c0-c2)) && sequentialAddresses(p0, p3, int64(7+c0-c3)) && clobber(x1, x2, x3)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(c0) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVBload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVBstore || auxIntToInt32(mem2.AuxInt) != i-1 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVBload || auxIntToInt32(x2.AuxInt) != j-1 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(j - 1) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [c] {s} p1 x:(MOVBstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVBstoreconst [a] {s} p0 x:(MOVBstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX (ANDLconst [c] x)) // cond: uint32(c) & 0x80000000 == 0 // result: (ANDLconst [c & 0x7fffffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(uint32(c)&0x80000000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fffffff) v.AddArg(x) return true } // match: (MOVLQSX (MOVLQSX x)) // result: (MOVLQSX x) for { if v_0.Op != OpAMD64MOVLQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x) // cond: zeroUpper32Bits(x,3) // result: x for { x := v_0 if !(zeroUpper32Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVLQZX (ANDLconst [c] x)) // result: (ANDLconst [c] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (MOVLQZX (MOVLQZX x)) // result: (MOVLQZX x) for { if v_0.Op != OpAMD64MOVLQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLf2i) v.AddArg(val) return true } // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [32] w) x:(MOVLstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [j] w) x:(MOVLstore [i] {s} p0 w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVLload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVLstore || auxIntToInt32(mem2.AuxInt) != i-4 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVLload || auxIntToInt32(x2.AuxInt) != j-4 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(j - 4) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) // result: (MOVSSstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [i] {s} p x:(BSWAPL w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPL { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [c] {s} p1 x:(MOVLstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p0, v0, mem) return true } // match: (MOVLstoreconst [a] {s} p0 x:(MOVLstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p0, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) // cond: symIsRO(srcSym) // result: (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))]) (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))]) mem)) for { dstOff := auxIntToInt32(v.AuxInt) dstSym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVOload { break } srcOff := auxIntToInt32(v_1.AuxInt) srcSym := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } mem := v_2 if !(symIsRO(srcSym)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(dstOff + 8) v.Aux = symToAux(dstSym) v0 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))) v1 := b.NewValue0(v_1.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AuxInt = int32ToAuxInt(dstOff) v1.Aux = symToAux(dstSym) v2 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))) v1.AddArg3(ptr, v2, mem) v.AddArg3(ptr, v0, v1) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVOstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.copyOf(x) return true } // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) // result: (MOVQf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQf2i) v.AddArg(val) return true } // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validVal(c) // result: (MOVQstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(validVal(c)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) // result: (MOVSDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [i] {s} p x:(BSWAPQ w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPQ { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [c] {s} p1 x:(MOVQstoreconst [a] {s} p0 mem)) // cond: config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVQstoreconst [a] {s} p0 x:(MOVQstoreconst [c] {s} p1 mem)) // cond: config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fff) v.AddArg(x) return true } // match: (MOVWQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x) // cond: zeroUpper48Bits(x,3) // result: x for { x := v_0 if !(zeroUpper48Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVWQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xffff) v.AddArg(x) return true } // match: (MOVWQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVWload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVWstore || auxIntToInt32(mem2.AuxInt) != i-2 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVWload || auxIntToInt32(x2.AuxInt) != j-2 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(j - 2) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [c] {s} p1 x:(MOVWstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVWstoreconst [a] {s} p0 x:(MOVWstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULL x (MOVLconst [c])) // result: (MULLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULLconst [c] (MULLconst [d] x)) // result: (MULLconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULLconst [-9] x) // result: (NEGL (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // result: (NEGL (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // result: (NEGL (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // result: (NEGL x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGL) v.AddArg(x) return true } // match: (MULLconst [ 0] _) // result: (MOVLconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (MULLconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULLconst [ 3] x) // result: (LEAL2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAL2) v.AddArg2(x, x) return true } // match: (MULLconst [ 5] x) // result: (LEAL4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAL4) v.AddArg2(x, x) return true } // match: (MULLconst [ 7] x) // result: (LEAL2 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [ 9] x) // result: (LEAL8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAL8) v.AddArg2(x, x) return true } // match: (MULLconst [11] x) // result: (LEAL2 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [13] x) // result: (LEAL4 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [19] x) // result: (LEAL2 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [21] x) // result: (LEAL4 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [25] x) // result: (LEAL8 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [27] x) // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [37] x) // result: (LEAL4 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [41] x) // result: (LEAL8 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [45] x) // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [73] x) // result: (LEAL8 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [81] x) // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBL (SHLLconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAL1) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLLconst [int8(log32(c/3))] (LEAL2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLLconst [int8(log32(c/5))] (LEAL4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLLconst [int8(log32(c/9))] (LEAL8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] (MOVLconst [d])) // result: (MOVLconst [c*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c * d) return true } return false } func rewriteValueAMD64_OpAMD64MULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (MULQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULQconst [c] (MULQconst [d] x)) // cond: is32Bit(int64(c)*int64(d)) // result: (MULQconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) * int64(d))) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULQconst [-9] x) // result: (NEGQ (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-5] x) // result: (NEGQ (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-3] x) // result: (NEGQ (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-1] x) // result: (NEGQ x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGQ) v.AddArg(x) return true } // match: (MULQconst [ 0] _) // result: (MOVQconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MULQconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULQconst [ 3] x) // result: (LEAQ2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAQ2) v.AddArg2(x, x) return true } // match: (MULQconst [ 5] x) // result: (LEAQ4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAQ4) v.AddArg2(x, x) return true } // match: (MULQconst [ 7] x) // result: (LEAQ2 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [ 9] x) // result: (LEAQ8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAQ8) v.AddArg2(x, x) return true } // match: (MULQconst [11] x) // result: (LEAQ2 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [13] x) // result: (LEAQ4 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [19] x) // result: (LEAQ2 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [21] x) // result: (LEAQ4 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [25] x) // result: (LEAQ8 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [27] x) // result: (LEAQ8 (LEAQ2 x x) (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [37] x) // result: (LEAQ4 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [41] x) // result: (LEAQ8 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [45] x) // result: (LEAQ8 (LEAQ4 x x) (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [73] x) // result: (LEAQ8 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [81] x) // result: (LEAQ8 (LEAQ8 x x) (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBQ (SHLQconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAQ1 (SHLQconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAQ1) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAQ2 (SHLQconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAQ4 (SHLQconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAQ8 (SHLQconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLQconst [int8(log32(c/3))] (LEAQ2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLQconst [int8(log32(c/5))] (LEAQ4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLQconst [int8(log32(c/9))] (LEAQ8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) * d) return true } // match: (MULQconst [c] (NEGQ x)) // cond: c != -(1<<31) // result: (MULQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (MULSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64MULSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (MULSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64NEGL(v *Value) bool { v_0 := v.Args[0] // match: (NEGL (NEGL x)) // result: x for { if v_0.Op != OpAMD64NEGL { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGL s:(SUBL x y)) // cond: s.Uses == 1 // result: (SUBL y x) for { s := v_0 if s.Op != OpAMD64SUBL { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBL) v.AddArg2(y, x) return true } // match: (NEGL (MOVLconst [c])) // result: (MOVLconst [-c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-c) return true } return false } func rewriteValueAMD64_OpAMD64NEGQ(v *Value) bool { v_0 := v.Args[0] // match: (NEGQ (NEGQ x)) // result: x for { if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGQ s:(SUBQ x y)) // cond: s.Uses == 1 // result: (SUBQ y x) for { s := v_0 if s.Op != OpAMD64SUBQ { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBQ) v.AddArg2(y, x) return true } // match: (NEGQ (MOVQconst [c])) // result: (MOVQconst [-c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-c) return true } // match: (NEGQ (ADDQconst [c] (NEGQ x))) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { if v_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } x := v_0_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64NOTL(v *Value) bool { v_0 := v.Args[0] // match: (NOTL (MOVLconst [c])) // result: (MOVLconst [^c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64NOTQ(v *Value) bool { v_0 := v.Args[0] // match: (NOTQ (MOVQconst [c])) // result: (MOVQconst [^c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64ORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTSL) v.AddArg2(x, y) return true } break } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORL x0:(MOVBload [i0] {s} p mem) sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVBload [i] {s} p0 mem) sh:(SHLLconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVWload [i] {s} p0 mem) sh:(SHLLconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL x1:(MOVBload [i] {s} p1 mem) sh:(SHLLconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORLconst(v *Value) bool { v_0 := v.Args[0] // match: (ORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORLconst [c] (ORLconst [d] x)) // result: (ORLconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORLconst [c] (BTSLconst [d] x)) // result: (ORLconst [c | 1<= 128 // result: (BTSQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ORQ x (MOVLconst [c])) // result: (ORQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORQ (SHRQ lo bits) (SHLQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLQ lo bits) (SHRQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHRXQ lo bits) (SHLXQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLXQ lo bits) (SHRXQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (MOVQconst [c]) (MOVQconst [d])) // result: (MOVQconst [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c | d) return true } break } // match: (ORQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORQ x0:(MOVBload [i0] {s} p mem) sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBload [i] {s} p0 mem) sh:(SHLQconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVWload [i] {s} p0 mem) sh:(SHLQconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVLload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVLload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i] {s} p0 mem)) y)) // cond: j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ x1:(MOVBload [i] {s} p1 mem) sh:(SHLQconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i] {s} p1 mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem))) y)) // cond: j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ORQ x0:(MOVBELload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVBELload [i1] {s} p mem))) // cond: i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i1] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i1) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBELload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVBELload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i] {s} p1 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p1, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQconst(v *Value) bool { v_0 := v.Args[0] // match: (ORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORQconst [c] (ORQconst [d] x)) // result: (ORQconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORQconst [c] (BTSQconst [d] x)) // cond: is32Bit(int64(c) | 1<>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int8(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (MOVLconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL l:(MOVLload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SARXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARLconst(v *Value) bool { v_0 := v.Args[0] // match: (SARLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARLconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int32(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int32(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (MOVLconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ l:(MOVQload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SARXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARQconst(v *Value) bool { v_0 := v.Args[0] // match: (SARQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARQconst [c] (MOVQconst [d])) // result: (MOVQconst [d>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SARW x (MOVQconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } // match: (SARW x (MOVLconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SARWconst(v *Value) bool { v_0 := v.Args[0] // match: (SARWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARWconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int16(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int16(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SARXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SARLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SARXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SARXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SBBLcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBLcarrymask (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagLT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagGT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQ x (MOVQconst [c]) borrow) // cond: is32Bit(c) // result: (SBBQconst x [int32(c)] borrow) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) borrow := v_2 if !(is32Bit(c)) { break } v.reset(OpAMD64SBBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, borrow) return true } // match: (SBBQ x y (FlagEQ)) // result: (SUBQborrow x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQborrow) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64SBBQcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBQcarrymask (FlagEQ)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagLT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagLT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagGT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagGT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQconst x [c] (FlagEQ)) // result: (SUBQconstborrow x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SETA(v *Value) bool { v_0 := v.Args[0] // match: (SETA (InvertFlags x)) // result: (SETB x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETA (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAE(v *Value) bool { v_0 := v.Args[0] // match: (SETAE (TESTQ x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTL x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTW x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTB x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (InvertFlags x)) // result: (SETBE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETAstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETB(v *Value) bool { v_0 := v.Args[0] // match: (SETB (TESTQ x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTL x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTW x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTB x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (BTLconst [0] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64BTLconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (BTQconst [0] x)) // result: (ANDQconst [1] x) for { if v_0.Op != OpAMD64BTQconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (InvertFlags x)) // result: (SETA x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBE(v *Value) bool { v_0 := v.Args[0] // match: (SETBE (InvertFlags x)) // result: (SETAE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETBE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAE (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAE (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETNE (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETEQ (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETEQstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETG(v *Value) bool { v_0 := v.Args[0] // match: (SETG (InvertFlags x)) // result: (SETL x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETG (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGE(v *Value) bool { v_0 := v.Args[0] // match: (SETGE (InvertFlags x)) // result: (SETLE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETL(v *Value) bool { v_0 := v.Args[0] // match: (SETL (InvertFlags x)) // result: (SETG x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLE(v *Value) bool { v_0 := v.Args[0] // match: (SETLE (InvertFlags x)) // result: (SETGE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETLE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNE(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETNE (TESTBconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTBconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTWconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTWconst || auxIntToInt16(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETB (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETB (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETEQ (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (InvertFlags x)) // result: (SETNE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETNE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETNEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (MOVLconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL l:(MOVLload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHLXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLLconst [1] (SHRLconst [1] x)) // result: (BTRLconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLLconst [d] (MOVLconst [c])) // result: (MOVLconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (MOVLconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ l:(MOVQload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHLXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLQconst [1] (SHRQconst [1] x)) // result: (BTRQconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLQconst [d] (MOVQconst [c])) // result: (MOVQconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c << uint64(d)) return true } // match: (SHLQconst [d] (MOVLconst [c])) // result: (MOVQconst [int64(c) << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHLXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHLLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHLXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SHLXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRB x (MOVQconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB _ (MOVQconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRBconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRBconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (MOVLconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL l:(MOVLload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHRXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRLconst [1] (SHLLconst [1] x)) // result: (BTRLconst [31] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(31) v.AddArg(x) return true } // match: (SHRLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (MOVLconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ l:(MOVQload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHRXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRQconst [1] (SHLQconst [1] x)) // result: (BTRQconst [63] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(63) v.AddArg(x) return true } // match: (SHRQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRW x (MOVQconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW _ (MOVQconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRWconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHRXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHRLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHRXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SHRXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBL x (MOVLconst [c])) // result: (SUBLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SUBLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // result: (NEGL (SUBLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBLconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (SUBLconst [c] x) // result: (ADDLconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } } func rewriteValueAMD64_OpAMD64SUBLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (SUBL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconst x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } // match: (SUBQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (NEGQ (SUBQconst x [int32(c)])) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBQload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQborrow(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQborrow x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconstborrow x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SUBQconst [c] x) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } // match: (SUBQconst (MOVQconst [d]) [c]) // result: (MOVQconst [d-int64(c)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d - int64(c)) return true } // match: (SUBQconst (SUBQconst x [d]) [c]) // cond: is32Bit(int64(-c)-int64(d)) // result: (ADDQconst [-c-d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SUBQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(-c) - int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c - d) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (SUBQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (SUBSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (SUBSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64TESTB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [int8(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } break } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVBload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTBconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTBconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTL a:(ANDLload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTL (MOVLload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDLload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTL) v0 := b.NewValue0(a.Pos, OpAMD64MOVLload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTLconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTLconst [c] (MOVLconst [c])) // cond: c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTLconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTL x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTL) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (TESTQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { continue } v.reset(OpAMD64TESTQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTQ a:(ANDQload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTQ (MOVQload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDQload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTQ) v0 := b.NewValue0(a.Pos, OpAMD64MOVQload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTQconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTQconst [-1] x) // cond: x.Op != OpAMD64MOVQconst // result: (TESTQ x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVQconst) { break } v.reset(OpAMD64TESTQ) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [int16(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } break } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVWload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTWconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTWconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64XADDLlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDLlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XADDQlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDQlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGL(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGL [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGQ [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTCL) v.AddArg2(x, y) return true } break } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORLconst(v *Value) bool { v_0 := v.Args[0] // match: (XORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORLconst [1] (SETNE x)) // result: (SETEQ x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETNE { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (XORLconst [1] (SETEQ x)) // result: (SETNE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETEQ { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (XORLconst [1] (SETL x)) // result: (SETGE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETL { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (XORLconst [1] (SETGE x)) // result: (SETL x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETGE { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (XORLconst [1] (SETLE x)) // result: (SETG x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETLE { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (XORLconst [1] (SETG x)) // result: (SETLE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETG { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (XORLconst [1] (SETB x)) // result: (SETAE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETB { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (XORLconst [1] (SETAE x)) // result: (SETB x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETAE { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (XORLconst [1] (SETBE x)) // result: (SETA x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETBE { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (XORLconst [1] (SETA x)) // result: (SETBE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETA { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (XORLconst [c] (XORLconst [d] x)) // result: (XORLconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORLconst [c] (BTCLconst [d] x)) // result: (XORLconst [c ^ 1<= 128 // result: (BTCQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (XORQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORQconst(v *Value) bool { v_0 := v.Args[0] // match: (XORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORQconst [c] (XORQconst [d] x)) // result: (XORQconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORQconst [c] (BTCQconst [d] x)) // cond: is32Bit(int64(c) ^ 1< val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore64(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore64 ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore8 ptr val mem) // result: (Select1 (XCHGB val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStorePtrNoWB(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStorePtrNoWB ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen16 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen16 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVWQZX x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, x.Type) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) v1.AuxInt = int32ToAuxInt(1) v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v2.AddArg(x) v1.AddArg2(v2, v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (BitLen32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // cond: buildcfg.GOAMD64 < 3 // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(1) v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) v1 := b.NewValue0(v.Pos, OpSelect0, t) v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v3.AuxInt = int64ToAuxInt(-1) v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4.AddArg(v2) v0.AddArg3(v1, v3, v4) v.AddArg(v0) return true } // match: (BitLen64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-64] (LZCNTQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-64) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTQ, typ.UInt64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen8 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen8 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVBQZX x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, x.Type) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCeil(v *Value) bool { v_0 := v.Args[0] // match: (Ceil x) // result: (ROUNDSD [2] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(2) v.AddArg(x) return true } } func rewriteValueAMD64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (CondSelect x y (SETEQ cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is32BitInt(t) // result: (CMOVLEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is32BitInt(t) // result: (CMOVLNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is32BitInt(t) // result: (CMOVLLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is32BitInt(t) // result: (CMOVLGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is32BitInt(t) // result: (CMOVLLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is32BitInt(t) // result: (CMOVLGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is32BitInt(t) // result: (CMOVLHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is32BitInt(t) // result: (CMOVLCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is32BitInt(t) // result: (CMOVLCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is32BitInt(t) // result: (CMOVLLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is32BitInt(t) // result: (CMOVLEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is32BitInt(t) // result: (CMOVLNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is32BitInt(t) // result: (CMOVLGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is32BitInt(t) // result: (CMOVLGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is16BitInt(t) // result: (CMOVWEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is16BitInt(t) // result: (CMOVWNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is16BitInt(t) // result: (CMOVWLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is16BitInt(t) // result: (CMOVWGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is16BitInt(t) // result: (CMOVWLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is16BitInt(t) // result: (CMOVWGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is16BitInt(t) // result: (CMOVWHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is16BitInt(t) // result: (CMOVWCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is16BitInt(t) // result: (CMOVWCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is16BitInt(t) // result: (CMOVWLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is16BitInt(t) // result: (CMOVWEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is16BitInt(t) // result: (CMOVWNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is16BitInt(t) // result: (CMOVWGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is16BitInt(t) // result: (CMOVWGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 1 // result: (CondSelect x y (MOVBQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 1) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 2 // result: (CondSelect x y (MOVWQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 2) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 4 // result: (CondSelect x y (MOVLQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 4) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { break } v.reset(OpAMD64CMOVQNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) // result: (CMOVLNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) // result: (CMOVWNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } return false } func rewriteValueAMD64_OpConst16(v *Value) bool { // match: (Const16 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt16(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConst8(v *Value) bool { // match: (Const8 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt8(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConstBool(v *Value) bool { // match: (ConstBool [c]) // result: (MOVLconst [b2i32(c)]) for { c := auxIntToBool(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(b2i32(c)) return true } } func rewriteValueAMD64_OpConstNil(v *Value) bool { // match: (ConstNil ) // result: (MOVQconst [0]) for { v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } } func rewriteValueAMD64_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (BSFL (BTSLconst [16] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(16) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz16NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ (BTSQconst [32] x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) v1.AuxInt = int8ToAuxInt(32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz32NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64 x) // cond: buildcfg.GOAMD64 < 3 // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v3.AddArg(v1) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueAMD64_OpCtz64NonZero(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ x)) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (BSFL (BTSLconst [ 8] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 [a] x y) // result: (Select0 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (Select0 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32 [a] x y) // result: (Select0 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32u x y) // result: (Select0 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64 [a] x y) // result: (Select0 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64u x y) // result: (Select0 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq16 x y) // result: (SETEQ (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32 x y) // result: (SETEQ (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32F x y) // result: (SETEQF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64 x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64F x y) // result: (SETEQF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq8 x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqB x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqPtr x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpFMA(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMA x y z) // result: (VFMADD231SD z x y) for { x := v_0 y := v_1 z := v_2 v.reset(OpAMD64VFMADD231SD) v.AddArg3(z, x, y) return true } } func rewriteValueAMD64_OpFloor(v *Value) bool { v_0 := v.Args[0] // match: (Floor x) // result: (ROUNDSD [1] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpGetG(v *Value) bool { v_0 := v.Args[0] // match: (GetG mem) // cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal // result: (LoweredGetG mem) for { mem := v_0 if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) { break } v.reset(OpAMD64LoweredGetG) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (HasCPUFeature {s}) // result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s}))) for { s := auxToSym(v.Aux) v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64) v1.Aux = symToAux(s) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsInBounds idx len) // result: (SETB (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsNonNil(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (IsNonNil p) // result: (SETNE (TESTQ p p)) for { p := v_0 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) v0.AddArg2(p, p) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsSliceInBounds idx len) // result: (SETBE (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16 x y) // result: (SETLE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16U x y) // result: (SETBE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32 x y) // result: (SETLE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32F x y) // result: (SETGEF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32U x y) // result: (SETBE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64 x y) // result: (SETLE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64F x y) // result: (SETGEF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64U x y) // result: (SETBE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8 x y) // result: (SETLE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8U x y) // result: (SETBE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16 x y) // result: (SETL (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16U x y) // result: (SETB (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 x y) // result: (SETL (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32F x y) // result: (SETGF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32U x y) // result: (SETB (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 x y) // result: (SETL (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64F x y) // result: (SETGF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64U x y) // result: (SETB (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8 x y) // result: (SETL (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8U x y) // result: (SETB (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVQload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64MOVQload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) // result: (MOVLload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t)) { break } v.reset(OpAMD64MOVLload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t)) { break } v.reset(OpAMD64MOVWload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(OpAMD64MOVBload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitFloat(t)) { break } v.reset(OpAMD64MOVSSload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitFloat(t)) { break } v.reset(OpAMD64MOVSDload) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpLocalAddr(v *Value) bool { v_0 := v.Args[0] // match: (LocalAddr {sym} base _) // result: (LEAQ {sym} base) for { sym := auxToSym(v.Aux) base := v_0 v.reset(OpAMD64LEAQ) v.Aux = symToAux(sym) v.AddArg(base) return true } } func rewriteValueAMD64_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16 [a] x y) // result: (Select1 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Select1 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32 [a] x y) // result: (Select1 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (Select1 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64 [a] x y) // result: (Select1 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (Select1 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [2] dst src mem) // result: (MOVWstore dst (MOVWload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [4] dst src mem) // result: (MOVLstore dst (MOVLload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [8] dst src mem) // result: (MOVQstore dst (MOVQload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVQstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: config.useSSE // result: (MOVOstore dst (MOVOload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: !config.useSSE // result: (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [32] dst src mem) // result: (Move [16] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpMove) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [48] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 48 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [64] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [32]) (OffPtr src [32]) (Move [32] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 64 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(32) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(32) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(32) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(2) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [6] dst src mem) // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [7] dst src mem) // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [10] dst src mem) // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [12] dst src mem) // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s == 11 || s >= 13 && s <= 15 // result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s == 11 || s >= 13 && s <= 15) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(int32(s - 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(int32(s - 8)) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 <= 8 // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 <= 8) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVOstore dst (MOVOload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AuxInt = int32ToAuxInt(8) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AuxInt = int32ToAuxInt(8) v3.AddArg2(src, mem) v4 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v5 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v5.AddArg2(src, mem) v4.AddArg3(dst, v5, mem) v2.AddArg3(dst, v3, v4) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s) // result: (DUFFCOPY [s] dst src mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s)) { break } v.reset(OpAMD64DUFFCOPY) v.AuxInt = int64ToAuxInt(s) v.AddArg3(dst, src, mem) return true } // match: (Move [s] dst src mem) // cond: (s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s) // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !((s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s)) { break } v.reset(OpAMD64REPMOVSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v.AddArg4(dst, src, v0, mem) return true } return false } func rewriteValueAMD64_OpNeg32F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg32F x) // result: (PXOR x (MOVSSconst [float32(math.Copysign(0, -1))])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1))) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeg64F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg64F x) // result: (PXOR x (MOVSDconst [math.Copysign(0, -1)])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) v0.AuxInt = float64ToAuxInt(math.Copysign(0, -1)) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq16 x y) // result: (SETNE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32 x y) // result: (SETNE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32F x y) // result: (SETNEF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64 x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64F x y) // result: (SETNEF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq8 x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqB x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqPtr x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNot(v *Value) bool { v_0 := v.Args[0] // match: (Not x) // result: (XORLconst [1] x) for { x := v_0 v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // cond: is32Bit(off) // result: (ADDQconst [int32(off)] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 if !(is32Bit(off)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(off)) v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDQ (MOVQconst [off]) ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(off) v.AddArg2(v0, ptr) return true } } func rewriteValueAMD64_OpPanicBounds(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 0) { break } v.reset(OpAMD64LoweredPanicBoundsA) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 1) { break } v.reset(OpAMD64LoweredPanicBoundsB) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 2) { break } v.reset(OpAMD64LoweredPanicBoundsC) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } return false } func rewriteValueAMD64_OpPopCount16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTL (MOVWQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpPopCount8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTL (MOVBQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpRoundToEven(v *Value) bool { v_0 := v.Args[0] // match: (RoundToEven x) // result: (ROUNDSD [0] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } } func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpSelect0(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uover x y)) // result: (Select0 (MULQU x y)) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Mul32uover x y)) // result: (Select0 (MULLU x y)) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y c)) // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst32 val tuple)) // result: (ADDL val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDL) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } // match: (Select0 (AddTupleFirst64 val tuple)) // result: (ADDQ val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } return false } func rewriteValueAMD64_OpSelect1(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uover x y)) // result: (SETO (Select1 (MULQU x y))) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul32uover x y)) // result: (SETO (Select1 (MULLU x y))) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Add64carry x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (NEGLflags (MOVQconst [0]))) // result: (FlagEQ) for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 0 { break } v.reset(OpAMD64FlagEQ) return true } // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) // result: x for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64SBBQcarrymask { break } x := v_0_0_0.Args[0] v.copyOf(x) return true } // match: (Select1 (AddTupleFirst32 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } // match: (Select1 (AddTupleFirst64 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } return false } func rewriteValueAMD64_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem))))) // cond: sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call) // result: (Move [sc.Val64()] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpAMD64MOVQstoreconst { break } sc := auxIntToValAndOff(s1.AuxInt) _ = s1.Args[1] s2 := s1.Args[1] if s2.Op != OpAMD64MOVQstore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpAMD64MOVQstore { break } mem := s3.Args[2] dst := s3.Args[1] if !(sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sc.Val64()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem)) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpAMD64MOVQconst { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } return false } func rewriteValueAMD64_OpSlicemask(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Slicemask x) // result: (SARQconst (NEGQ x) [63]) for { t := v.Type x := v_0 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(63) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpSpectreIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreIndex x y) // result: (CMOVQCC x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQCC) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpSpectreSliceIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreSliceIndex x y) // result: (CMOVQHI x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQHI) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && is64BitFloat(val.Type) // result: (MOVSDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSDstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && is32BitFloat(val.Type) // result: (MOVSSstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSSstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 // result: (MOVQstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8) { break } v.reset(OpAMD64MOVQstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 // result: (MOVLstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4) { break } v.reset(OpAMD64MOVLstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 2 // result: (MOVWstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 2) { break } v.reset(OpAMD64MOVWstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 1 // result: (MOVBstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 1) { break } v.reset(OpAMD64MOVBstore) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpTrunc(v *Value) bool { v_0 := v.Args[0] // match: (Trunc x) // result: (ROUNDSD [3] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(3) v.AddArg(x) return true } } func rewriteValueAMD64_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [0] _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_1 v.copyOf(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [2] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [4] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [8] destptr mem) // result: (MOVQstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 2)) v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [5] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [6] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [7] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 3)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%8 != 0 && s > 8 && !config.useSSE // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%8 != 0 && s > 8 && !config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%8) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [24] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 24 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [32] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 24)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 8 && s < 16 && config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,int32(s-8))] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 8 && s < 16 && config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, int32(s-8))) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [32] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [48] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [64] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,48)] destptr (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 48)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice // result: (DUFFZERO [s] destptr mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFZERO) v.AuxInt = int64ToAuxInt(s) v.AddArg2(destptr, mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0 // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !((s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0) { break } v.reset(OpAMD64REPSTOSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(0) v.AddArg4(destptr, v0, v1, mem) return true } return false } func rewriteBlockAMD64(b *Block) bool { typ := &b.Func.Config.Types switch b.Kind { case BlockAMD64EQ: // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (UGE (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (UGE (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64GE: // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64GT: // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockIf: // match: (If (SETL cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64SETL { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (If (SETLE cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64SETLE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (If (SETG cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64SETG { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (If (SETGE cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64SETGE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (If (SETEQ cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64SETEQ { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (If (SETNE cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64SETNE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (If (SETB cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64SETB { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (If (SETBE cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64SETBE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (If (SETA cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETA { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETAE cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETAE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETO cmp) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64SETO { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (If (SETGF cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETGF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETGEF cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETGEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETEQF cmp) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64SETEQF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (If (SETNEF cmp) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64SETNEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (If cond yes no) // result: (NE (TESTB cond cond) yes no) for { cond := b.Controls[0] v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) v0.AddArg2(cond, cond) b.resetWithControl(BlockAMD64NE, v0) return true } case BlockJumpTable: // match: (JumpTable idx) // result: (JUMPTABLE {makeJumpTableSym(b)} idx (LEAQ {makeJumpTableSym(b)} (SB))) for { idx := b.Controls[0] v0 := b.NewValue0(b.Pos, OpAMD64LEAQ, typ.Uintptr) v0.Aux = symToAux(makeJumpTableSym(b)) v1 := b.NewValue0(b.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) b.resetWithControl2(BlockAMD64JUMPTABLE, idx, v0) b.Aux = symToAux(makeJumpTableSym(b)) return true } case BlockAMD64LE: // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64LT: // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETL { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETLE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETG { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQ { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETB { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETBE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETA { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETAE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETO { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (ULT (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (ULT (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGE: // match: (UGE (TESTQ x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTL x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTW x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTB x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (UGE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (UGE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGT: // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (UGT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64ULE: // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (ULE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64ULT: // match: (ULT (TESTQ x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTL x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTW x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTB x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (ULT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- diff -- @@ -382,12 +382,8 @@ return rewriteValueAMD64_OpAMD64SARW(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst(v) - case OpAMD64SARXL: - return rewriteValueAMD64_OpAMD64SARXL(v) case OpAMD64SARXLload: return rewriteValueAMD64_OpAMD64SARXLload(v) - case OpAMD64SARXQ: - return rewriteValueAMD64_OpAMD64SARXQ(v) case OpAMD64SARXQload: return rewriteValueAMD64_OpAMD64SARXQload(v) case OpAMD64SBBLcarrymask: @@ -446,12 +442,8 @@ return rewriteValueAMD64_OpAMD64SHLQ(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst(v) - case OpAMD64SHLXL: - return rewriteValueAMD64_OpAMD64SHLXL(v) case OpAMD64SHLXLload: return rewriteValueAMD64_OpAMD64SHLXLload(v) - case OpAMD64SHLXQ: - return rewriteValueAMD64_OpAMD64SHLXQ(v) case OpAMD64SHLXQload: return rewriteValueAMD64_OpAMD64SHLXQload(v) case OpAMD64SHRB: @@ -470,12 +462,8 @@ return rewriteValueAMD64_OpAMD64SHRW(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst(v) - case OpAMD64SHRXL: - return rewriteValueAMD64_OpAMD64SHRXL(v) case OpAMD64SHRXLload: return rewriteValueAMD64_OpAMD64SHRXLload(v) - case OpAMD64SHRXQ: - return rewriteValueAMD64_OpAMD64SHRXQ(v) case OpAMD64SHRXQload: return rewriteValueAMD64_OpAMD64SHRXQload(v) case OpAMD64SUBL: @@ -2626,29 +2614,6 @@ } break } - // match: (ANDL (NOTL (SHLXL (MOVLconst [1]) y)) x) - // result: (BTRL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64NOTL { - continue - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLXL { - continue - } - y := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { - continue - } - x := v_1 - v.reset(OpAMD64BTRL) - v.AddArg2(x, y) - return true - } - break - } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) @@ -3066,22 +3031,6 @@ v.AddArg2(x, y) return true } - // match: (ANDNL x (SHLXL (MOVLconst [1]) y)) - // result: (BTRL x y) - for { - x := v_0 - if v_1.Op != OpAMD64SHLXL { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0.AuxInt) != 1 { - break - } - v.reset(OpAMD64BTRL) - v.AddArg2(x, y) - return true - } return false } func rewriteValueAMD64_OpAMD64ANDNQ(v *Value) bool { @@ -3103,22 +3052,6 @@ v.AddArg2(x, y) return true } - // match: (ANDNQ x (SHLXQ (MOVQconst [1]) y)) - // result: (BTRQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64SHLXQ { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0.AuxInt) != 1 { - break - } - v.reset(OpAMD64BTRQ) - v.AddArg2(x, y) - return true - } return false } func rewriteValueAMD64_OpAMD64ANDQ(v *Value) bool { @@ -3147,29 +3080,6 @@ } break } - // match: (ANDQ (NOTQ (SHLXQ (MOVQconst [1]) y)) x) - // result: (BTRQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64NOTQ { - continue - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLXQ { - continue - } - y := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { - continue - } - x := v_1 - v.reset(OpAMD64BTRQ) - v.AddArg2(x, y) - return true - } - break - } // match: (ANDQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRQconst [int8(log64(^c))] x) @@ -3873,22 +3783,6 @@ v.AddArg2(y, x) return true } - // match: (BTLconst [0] s:(SHRXQ x y)) - // result: (BTQ y x) - for { - if auxIntToInt8(v.AuxInt) != 0 { - break - } - s := v_0 - if s.Op != OpAMD64SHRXQ { - break - } - y := s.Args[1] - x := s.Args[0] - v.reset(OpAMD64BTQ) - v.AddArg2(y, x) - return true - } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) @@ -4013,22 +3907,6 @@ v.AddArg2(y, x) return true } - // match: (BTQconst [0] s:(SHRXQ x y)) - // result: (BTQ y x) - for { - if auxIntToInt8(v.AuxInt) != 0 { - break - } - s := v_0 - if s.Op != OpAMD64SHRXQ { - break - } - y := s.Args[1] - x := s.Args[0] - v.reset(OpAMD64BTQ) - v.AddArg2(y, x) - return true - } return false } func rewriteValueAMD64_OpAMD64BTRLconst(v *Value) bool { @@ -15920,25 +15798,6 @@ } break } - // match: (ORL (SHLXL (MOVLconst [1]) y) x) - // result: (BTSL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { - continue - } - x := v_1 - v.reset(OpAMD64BTSL) - v.AddArg2(x, y) - return true - } - break - } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) @@ -16868,25 +16727,6 @@ } break } - // match: (ORQ (SHLXQ (MOVQconst [1]) y) x) - // result: (BTSQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXQ { - continue - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 1 { - continue - } - x := v_1 - v.reset(OpAMD64BTSQ) - v.AddArg2(x, y) - return true - } - break - } // match: (ORQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSQconst [int8(log64(c))] x) @@ -18994,19 +18834,6 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SARL x y) - // cond: buildcfg.GOAMD64 >= 3 - // result: (SARXL x y) - for { - x := v_0 - y := v_1 - if !(buildcfg.GOAMD64 >= 3) { - break - } - v.reset(OpAMD64SARXL) - v.AddArg2(x, y) - return true - } // match: (SARL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { @@ -19197,6 +19024,28 @@ v.AddArg2(x, v0) return true } + // match: (SARL l:(MOVLload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SARXLload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVLload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SARXLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } return false } func rewriteValueAMD64_OpAMD64SARLconst(v *Value) bool { @@ -19229,19 +19078,6 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SARQ x y) - // cond: buildcfg.GOAMD64 >= 3 - // result: (SARXQ x y) - for { - x := v_0 - y := v_1 - if !(buildcfg.GOAMD64 >= 3) { - break - } - v.reset(OpAMD64SARXQ) - v.AddArg2(x, y) - return true - } // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { @@ -19432,6 +19268,28 @@ v.AddArg2(x, v0) return true } + // match: (SARQ l:(MOVQload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SARXQload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVQload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SARXQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } return false } func rewriteValueAMD64_OpAMD64SARQconst(v *Value) bool { @@ -19517,224 +19375,6 @@ } return false } -func rewriteValueAMD64_OpAMD64SARXL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SARXL x (MOVQconst [c])) - // result: (SARLconst [int8(c&31)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SARLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) - return true - } - // match: (SARXL x (MOVLconst [c])) - // result: (SARLconst [int8(c&31)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SARLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) - return true - } - // match: (SARXL x (ADDQconst [c] y)) - // cond: c & 31 == 0 - // result: (SARXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SARXL) - v.AddArg2(x, y) - return true - } - // match: (SARXL x (NEGQ (ADDQconst [c] y))) - // cond: c & 31 == 0 - // result: (SARXL x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SARXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXL x (ANDQconst [c] y)) - // cond: c & 31 == 31 - // result: (SARXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SARXL) - v.AddArg2(x, y) - return true - } - // match: (SARXL x (NEGQ (ANDQconst [c] y))) - // cond: c & 31 == 31 - // result: (SARXL x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SARXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXL x (ADDLconst [c] y)) - // cond: c & 31 == 0 - // result: (SARXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SARXL) - v.AddArg2(x, y) - return true - } - // match: (SARXL x (NEGL (ADDLconst [c] y))) - // cond: c & 31 == 0 - // result: (SARXL x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SARXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXL x (ANDLconst [c] y)) - // cond: c & 31 == 31 - // result: (SARXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SARXL) - v.AddArg2(x, y) - return true - } - // match: (SARXL x (NEGL (ANDLconst [c] y))) - // cond: c & 31 == 31 - // result: (SARXL x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SARXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (SARXLload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVLload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SARXLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64SARXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -19763,224 +19403,6 @@ } return false } -func rewriteValueAMD64_OpAMD64SARXQ(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SARXQ x (MOVQconst [c])) - // result: (SARQconst [int8(c&63)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SARQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) - return true - } - // match: (SARXQ x (MOVLconst [c])) - // result: (SARQconst [int8(c&63)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SARQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) - return true - } - // match: (SARXQ x (ADDQconst [c] y)) - // cond: c & 63 == 0 - // result: (SARXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SARXQ) - v.AddArg2(x, y) - return true - } - // match: (SARXQ x (NEGQ (ADDQconst [c] y))) - // cond: c & 63 == 0 - // result: (SARXQ x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SARXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXQ x (ANDQconst [c] y)) - // cond: c & 63 == 63 - // result: (SARXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SARXQ) - v.AddArg2(x, y) - return true - } - // match: (SARXQ x (NEGQ (ANDQconst [c] y))) - // cond: c & 63 == 63 - // result: (SARXQ x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SARXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXQ x (ADDLconst [c] y)) - // cond: c & 63 == 0 - // result: (SARXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SARXQ) - v.AddArg2(x, y) - return true - } - // match: (SARXQ x (NEGL (ADDLconst [c] y))) - // cond: c & 63 == 0 - // result: (SARXQ x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SARXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXQ x (ANDLconst [c] y)) - // cond: c & 63 == 63 - // result: (SARXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SARXQ) - v.AddArg2(x, y) - return true - } - // match: (SARXQ x (NEGL (ANDLconst [c] y))) - // cond: c & 63 == 63 - // result: (SARXQ x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SARXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (SARXQload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SARXQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64SARXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -21284,60 +20706,6 @@ } break } - // match: (SETEQ (TESTL (SHLXL (MOVLconst [1]) x) y)) - // result: (SETAE (BTL x y)) - for { - if v_0.Op != OpAMD64TESTL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXL { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } - break - } - // match: (SETEQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) - // result: (SETAE (BTQ x y)) - for { - if v_0.Op != OpAMD64TESTQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXQ { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } - break - } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAE (BTLconst [int8(log32(c))] x)) @@ -21763,72 +21131,6 @@ } break } - // match: (SETEQstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) - // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXL { - continue - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { - continue - } - y := v_1_1 - mem := v_2 - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg3(ptr, v0, mem) - return true - } - break - } - // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) - // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXQ { - continue - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { - continue - } - y := v_1_1 - mem := v_2 - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg3(ptr, v0, mem) - return true - } - break - } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) @@ -23320,60 +22622,6 @@ } break } - // match: (SETNE (TESTL (SHLXL (MOVLconst [1]) x) y)) - // result: (SETB (BTL x y)) - for { - if v_0.Op != OpAMD64TESTL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXL { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } - break - } - // match: (SETNE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) - // result: (SETB (BTQ x y)) - for { - if v_0.Op != OpAMD64TESTQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXQ { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } - break - } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETB (BTLconst [int8(log32(c))] x)) @@ -23799,72 +23047,6 @@ } break } - // match: (SETNEstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) - // result: (SETBstore [off] {sym} ptr (BTL x y) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXL { - continue - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { - continue - } - y := v_1_1 - mem := v_2 - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg3(ptr, v0, mem) - return true - } - break - } - // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) - // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXQ { - continue - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { - continue - } - y := v_1_1 - mem := v_2 - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg3(ptr, v0, mem) - return true - } - break - } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) @@ -24379,19 +23561,6 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SHLL x y) - // cond: buildcfg.GOAMD64 >= 3 - // result: (SHLXL x y) - for { - x := v_0 - y := v_1 - if !(buildcfg.GOAMD64 >= 3) { - break - } - v.reset(OpAMD64SHLXL) - v.AddArg2(x, y) - return true - } // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { @@ -24582,6 +23751,28 @@ v.AddArg2(x, v0) return true } + // match: (SHLL l:(MOVLload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SHLXLload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVLload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHLXLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } return false } func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { @@ -24626,19 +23817,6 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SHLQ x y) - // cond: buildcfg.GOAMD64 >= 3 - // result: (SHLXQ x y) - for { - x := v_0 - y := v_1 - if !(buildcfg.GOAMD64 >= 3) { - break - } - v.reset(OpAMD64SHLXQ) - v.AddArg2(x, y) - return true - } // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { @@ -24829,6 +24007,28 @@ v.AddArg2(x, v0) return true } + // match: (SHLQ l:(MOVQload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SHLXQload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVQload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHLXQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } return false } func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { @@ -24881,224 +24081,6 @@ } return false } -func rewriteValueAMD64_OpAMD64SHLXL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SHLXL x (MOVQconst [c])) - // result: (SHLLconst [int8(c&31)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SHLLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) - return true - } - // match: (SHLXL x (MOVLconst [c])) - // result: (SHLLconst [int8(c&31)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SHLLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) - return true - } - // match: (SHLXL x (ADDQconst [c] y)) - // cond: c & 31 == 0 - // result: (SHLXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHLXL) - v.AddArg2(x, y) - return true - } - // match: (SHLXL x (NEGQ (ADDQconst [c] y))) - // cond: c & 31 == 0 - // result: (SHLXL x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHLXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXL x (ANDQconst [c] y)) - // cond: c & 31 == 31 - // result: (SHLXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHLXL) - v.AddArg2(x, y) - return true - } - // match: (SHLXL x (NEGQ (ANDQconst [c] y))) - // cond: c & 31 == 31 - // result: (SHLXL x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHLXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXL x (ADDLconst [c] y)) - // cond: c & 31 == 0 - // result: (SHLXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHLXL) - v.AddArg2(x, y) - return true - } - // match: (SHLXL x (NEGL (ADDLconst [c] y))) - // cond: c & 31 == 0 - // result: (SHLXL x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHLXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXL x (ANDLconst [c] y)) - // cond: c & 31 == 31 - // result: (SHLXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHLXL) - v.AddArg2(x, y) - return true - } - // match: (SHLXL x (NEGL (ANDLconst [c] y))) - // cond: c & 31 == 31 - // result: (SHLXL x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHLXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (SHLXLload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVLload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHLXLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64SHLXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -25127,224 +24109,6 @@ } return false } -func rewriteValueAMD64_OpAMD64SHLXQ(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SHLXQ x (MOVQconst [c])) - // result: (SHLQconst [int8(c&63)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SHLQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) - return true - } - // match: (SHLXQ x (MOVLconst [c])) - // result: (SHLQconst [int8(c&63)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SHLQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) - return true - } - // match: (SHLXQ x (ADDQconst [c] y)) - // cond: c & 63 == 0 - // result: (SHLXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHLXQ) - v.AddArg2(x, y) - return true - } - // match: (SHLXQ x (NEGQ (ADDQconst [c] y))) - // cond: c & 63 == 0 - // result: (SHLXQ x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHLXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXQ x (ANDQconst [c] y)) - // cond: c & 63 == 63 - // result: (SHLXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHLXQ) - v.AddArg2(x, y) - return true - } - // match: (SHLXQ x (NEGQ (ANDQconst [c] y))) - // cond: c & 63 == 63 - // result: (SHLXQ x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHLXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXQ x (ADDLconst [c] y)) - // cond: c & 63 == 0 - // result: (SHLXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHLXQ) - v.AddArg2(x, y) - return true - } - // match: (SHLXQ x (NEGL (ADDLconst [c] y))) - // cond: c & 63 == 0 - // result: (SHLXQ x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHLXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXQ x (ANDLconst [c] y)) - // cond: c & 63 == 63 - // result: (SHLXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHLXQ) - v.AddArg2(x, y) - return true - } - // match: (SHLXQ x (NEGL (ANDLconst [c] y))) - // cond: c & 63 == 63 - // result: (SHLXQ x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHLXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (SHLXQload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHLXQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64SHLXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -25480,19 +24244,6 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SHRL x y) - // cond: buildcfg.GOAMD64 >= 3 - // result: (SHRXL x y) - for { - x := v_0 - y := v_1 - if !(buildcfg.GOAMD64 >= 3) { - break - } - v.reset(OpAMD64SHRXL) - v.AddArg2(x, y) - return true - } // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { @@ -25683,6 +24434,28 @@ v.AddArg2(x, v0) return true } + // match: (SHRL l:(MOVLload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SHRXLload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVLload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHRXLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } return false } func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { @@ -25715,19 +24488,6 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SHRQ x y) - // cond: buildcfg.GOAMD64 >= 3 - // result: (SHRXQ x y) - for { - x := v_0 - y := v_1 - if !(buildcfg.GOAMD64 >= 3) { - break - } - v.reset(OpAMD64SHRXQ) - v.AddArg2(x, y) - return true - } // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { @@ -25918,6 +24678,28 @@ v.AddArg2(x, v0) return true } + // match: (SHRQ l:(MOVQload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SHRXQload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVQload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHRXQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } return false } func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { @@ -26029,224 +24811,6 @@ } return false } -func rewriteValueAMD64_OpAMD64SHRXL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SHRXL x (MOVQconst [c])) - // result: (SHRLconst [int8(c&31)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SHRLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) - return true - } - // match: (SHRXL x (MOVLconst [c])) - // result: (SHRLconst [int8(c&31)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SHRLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) - return true - } - // match: (SHRXL x (ADDQconst [c] y)) - // cond: c & 31 == 0 - // result: (SHRXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHRXL) - v.AddArg2(x, y) - return true - } - // match: (SHRXL x (NEGQ (ADDQconst [c] y))) - // cond: c & 31 == 0 - // result: (SHRXL x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHRXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXL x (ANDQconst [c] y)) - // cond: c & 31 == 31 - // result: (SHRXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHRXL) - v.AddArg2(x, y) - return true - } - // match: (SHRXL x (NEGQ (ANDQconst [c] y))) - // cond: c & 31 == 31 - // result: (SHRXL x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHRXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXL x (ADDLconst [c] y)) - // cond: c & 31 == 0 - // result: (SHRXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHRXL) - v.AddArg2(x, y) - return true - } - // match: (SHRXL x (NEGL (ADDLconst [c] y))) - // cond: c & 31 == 0 - // result: (SHRXL x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHRXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXL x (ANDLconst [c] y)) - // cond: c & 31 == 31 - // result: (SHRXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHRXL) - v.AddArg2(x, y) - return true - } - // match: (SHRXL x (NEGL (ANDLconst [c] y))) - // cond: c & 31 == 31 - // result: (SHRXL x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHRXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (SHRXLload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVLload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHRXLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64SHRXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -26275,224 +24839,6 @@ } return false } -func rewriteValueAMD64_OpAMD64SHRXQ(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SHRXQ x (MOVQconst [c])) - // result: (SHRQconst [int8(c&63)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SHRQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) - return true - } - // match: (SHRXQ x (MOVLconst [c])) - // result: (SHRQconst [int8(c&63)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SHRQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) - return true - } - // match: (SHRXQ x (ADDQconst [c] y)) - // cond: c & 63 == 0 - // result: (SHRXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHRXQ) - v.AddArg2(x, y) - return true - } - // match: (SHRXQ x (NEGQ (ADDQconst [c] y))) - // cond: c & 63 == 0 - // result: (SHRXQ x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHRXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXQ x (ANDQconst [c] y)) - // cond: c & 63 == 63 - // result: (SHRXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHRXQ) - v.AddArg2(x, y) - return true - } - // match: (SHRXQ x (NEGQ (ANDQconst [c] y))) - // cond: c & 63 == 63 - // result: (SHRXQ x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHRXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXQ x (ADDLconst [c] y)) - // cond: c & 63 == 0 - // result: (SHRXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHRXQ) - v.AddArg2(x, y) - return true - } - // match: (SHRXQ x (NEGL (ADDLconst [c] y))) - // cond: c & 63 == 0 - // result: (SHRXQ x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHRXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXQ x (ANDLconst [c] y)) - // cond: c & 63 == 63 - // result: (SHRXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHRXQ) - v.AddArg2(x, y) - return true - } - // match: (SHRXQ x (NEGL (ANDLconst [c] y))) - // cond: c & 63 == 63 - // result: (SHRXQ x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHRXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (SHRXQload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHRXQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -27824,25 +26170,6 @@ } break } - // match: (XORL (SHLXL (MOVLconst [1]) y) x) - // result: (BTCL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { - continue - } - x := v_1 - v.reset(OpAMD64BTCL) - v.AddArg2(x, y) - return true - } - break - } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) @@ -28306,25 +26633,6 @@ } break } - // match: (XORQ (SHLXQ (MOVQconst [1]) y) x) - // result: (BTCQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXQ { - continue - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 1 { - continue - } - x := v_1 - v.reset(OpAMD64BTCQ) - v.AddArg2(x, y) - return true - } - break - } // match: (XORQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCQconst [int8(log64(c))] x) @@ -34928,54 +33236,6 @@ } break } - // match: (EQ (TESTL (SHLXL (MOVLconst [1]) x) y)) - // result: (UGE (BTL x y)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXL { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - b.resetWithControl(BlockAMD64UGE, v0) - return true - } - break - } - // match: (EQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) - // result: (UGE (BTQ x y)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXQ { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - b.resetWithControl(BlockAMD64UGE, v0) - return true - } - break - } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (UGE (BTLconst [int8(log32(c))] x)) @@ -35777,54 +34037,6 @@ v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - b.resetWithControl(BlockAMD64ULT, v0) - return true - } - break - } - // match: (NE (TESTL (SHLXL (MOVLconst [1]) x) y)) - // result: (ULT (BTL x y)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXL { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - b.resetWithControl(BlockAMD64ULT, v0) - return true - } - break - } - // match: (NE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) - // result: (ULT (BTQ x y)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] -- diff -- # indent-heuristic: true @@ -382,12 +382,8 @@ return rewriteValueAMD64_OpAMD64SARW(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst(v) - case OpAMD64SARXL: - return rewriteValueAMD64_OpAMD64SARXL(v) case OpAMD64SARXLload: return rewriteValueAMD64_OpAMD64SARXLload(v) - case OpAMD64SARXQ: - return rewriteValueAMD64_OpAMD64SARXQ(v) case OpAMD64SARXQload: return rewriteValueAMD64_OpAMD64SARXQload(v) case OpAMD64SBBLcarrymask: @@ -446,12 +442,8 @@ return rewriteValueAMD64_OpAMD64SHLQ(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst(v) - case OpAMD64SHLXL: - return rewriteValueAMD64_OpAMD64SHLXL(v) case OpAMD64SHLXLload: return rewriteValueAMD64_OpAMD64SHLXLload(v) - case OpAMD64SHLXQ: - return rewriteValueAMD64_OpAMD64SHLXQ(v) case OpAMD64SHLXQload: return rewriteValueAMD64_OpAMD64SHLXQload(v) case OpAMD64SHRB: @@ -470,12 +462,8 @@ return rewriteValueAMD64_OpAMD64SHRW(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst(v) - case OpAMD64SHRXL: - return rewriteValueAMD64_OpAMD64SHRXL(v) case OpAMD64SHRXLload: return rewriteValueAMD64_OpAMD64SHRXLload(v) - case OpAMD64SHRXQ: - return rewriteValueAMD64_OpAMD64SHRXQ(v) case OpAMD64SHRXQload: return rewriteValueAMD64_OpAMD64SHRXQload(v) case OpAMD64SUBL: @@ -2626,29 +2614,6 @@ } break } - // match: (ANDL (NOTL (SHLXL (MOVLconst [1]) y)) x) - // result: (BTRL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64NOTL { - continue - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLXL { - continue - } - y := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { - continue - } - x := v_1 - v.reset(OpAMD64BTRL) - v.AddArg2(x, y) - return true - } - break - } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) @@ -3066,22 +3031,6 @@ v.AddArg2(x, y) return true } - // match: (ANDNL x (SHLXL (MOVLconst [1]) y)) - // result: (BTRL x y) - for { - x := v_0 - if v_1.Op != OpAMD64SHLXL { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0.AuxInt) != 1 { - break - } - v.reset(OpAMD64BTRL) - v.AddArg2(x, y) - return true - } return false } func rewriteValueAMD64_OpAMD64ANDNQ(v *Value) bool { @@ -3103,22 +3052,6 @@ v.AddArg2(x, y) return true } - // match: (ANDNQ x (SHLXQ (MOVQconst [1]) y)) - // result: (BTRQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64SHLXQ { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0.AuxInt) != 1 { - break - } - v.reset(OpAMD64BTRQ) - v.AddArg2(x, y) - return true - } return false } func rewriteValueAMD64_OpAMD64ANDQ(v *Value) bool { @@ -3147,29 +3080,6 @@ } break } - // match: (ANDQ (NOTQ (SHLXQ (MOVQconst [1]) y)) x) - // result: (BTRQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64NOTQ { - continue - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLXQ { - continue - } - y := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { - continue - } - x := v_1 - v.reset(OpAMD64BTRQ) - v.AddArg2(x, y) - return true - } - break - } // match: (ANDQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRQconst [int8(log64(^c))] x) @@ -3873,22 +3783,6 @@ v.AddArg2(y, x) return true } - // match: (BTLconst [0] s:(SHRXQ x y)) - // result: (BTQ y x) - for { - if auxIntToInt8(v.AuxInt) != 0 { - break - } - s := v_0 - if s.Op != OpAMD64SHRXQ { - break - } - y := s.Args[1] - x := s.Args[0] - v.reset(OpAMD64BTQ) - v.AddArg2(y, x) - return true - } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) @@ -4013,22 +3907,6 @@ v.AddArg2(y, x) return true } - // match: (BTQconst [0] s:(SHRXQ x y)) - // result: (BTQ y x) - for { - if auxIntToInt8(v.AuxInt) != 0 { - break - } - s := v_0 - if s.Op != OpAMD64SHRXQ { - break - } - y := s.Args[1] - x := s.Args[0] - v.reset(OpAMD64BTQ) - v.AddArg2(y, x) - return true - } return false } func rewriteValueAMD64_OpAMD64BTRLconst(v *Value) bool { @@ -15920,25 +15798,6 @@ } break } - // match: (ORL (SHLXL (MOVLconst [1]) y) x) - // result: (BTSL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { - continue - } - x := v_1 - v.reset(OpAMD64BTSL) - v.AddArg2(x, y) - return true - } - break - } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) @@ -16868,25 +16727,6 @@ } break } - // match: (ORQ (SHLXQ (MOVQconst [1]) y) x) - // result: (BTSQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXQ { - continue - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 1 { - continue - } - x := v_1 - v.reset(OpAMD64BTSQ) - v.AddArg2(x, y) - return true - } - break - } // match: (ORQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSQconst [int8(log64(c))] x) @@ -18994,19 +18834,6 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SARL x y) - // cond: buildcfg.GOAMD64 >= 3 - // result: (SARXL x y) - for { - x := v_0 - y := v_1 - if !(buildcfg.GOAMD64 >= 3) { - break - } - v.reset(OpAMD64SARXL) - v.AddArg2(x, y) - return true - } // match: (SARL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { @@ -19197,6 +19024,28 @@ v.AddArg2(x, v0) return true } + // match: (SARL l:(MOVLload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SARXLload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVLload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SARXLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } return false } func rewriteValueAMD64_OpAMD64SARLconst(v *Value) bool { @@ -19229,19 +19078,6 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SARQ x y) - // cond: buildcfg.GOAMD64 >= 3 - // result: (SARXQ x y) - for { - x := v_0 - y := v_1 - if !(buildcfg.GOAMD64 >= 3) { - break - } - v.reset(OpAMD64SARXQ) - v.AddArg2(x, y) - return true - } // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { @@ -19432,6 +19268,28 @@ v.AddArg2(x, v0) return true } + // match: (SARQ l:(MOVQload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SARXQload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVQload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SARXQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } return false } func rewriteValueAMD64_OpAMD64SARQconst(v *Value) bool { @@ -19517,224 +19375,6 @@ } return false } -func rewriteValueAMD64_OpAMD64SARXL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SARXL x (MOVQconst [c])) - // result: (SARLconst [int8(c&31)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SARLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) - return true - } - // match: (SARXL x (MOVLconst [c])) - // result: (SARLconst [int8(c&31)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SARLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) - return true - } - // match: (SARXL x (ADDQconst [c] y)) - // cond: c & 31 == 0 - // result: (SARXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SARXL) - v.AddArg2(x, y) - return true - } - // match: (SARXL x (NEGQ (ADDQconst [c] y))) - // cond: c & 31 == 0 - // result: (SARXL x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SARXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXL x (ANDQconst [c] y)) - // cond: c & 31 == 31 - // result: (SARXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SARXL) - v.AddArg2(x, y) - return true - } - // match: (SARXL x (NEGQ (ANDQconst [c] y))) - // cond: c & 31 == 31 - // result: (SARXL x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SARXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXL x (ADDLconst [c] y)) - // cond: c & 31 == 0 - // result: (SARXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SARXL) - v.AddArg2(x, y) - return true - } - // match: (SARXL x (NEGL (ADDLconst [c] y))) - // cond: c & 31 == 0 - // result: (SARXL x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SARXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXL x (ANDLconst [c] y)) - // cond: c & 31 == 31 - // result: (SARXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SARXL) - v.AddArg2(x, y) - return true - } - // match: (SARXL x (NEGL (ANDLconst [c] y))) - // cond: c & 31 == 31 - // result: (SARXL x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SARXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (SARXLload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVLload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SARXLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64SARXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -19763,224 +19403,6 @@ } return false } -func rewriteValueAMD64_OpAMD64SARXQ(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SARXQ x (MOVQconst [c])) - // result: (SARQconst [int8(c&63)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SARQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) - return true - } - // match: (SARXQ x (MOVLconst [c])) - // result: (SARQconst [int8(c&63)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SARQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) - return true - } - // match: (SARXQ x (ADDQconst [c] y)) - // cond: c & 63 == 0 - // result: (SARXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SARXQ) - v.AddArg2(x, y) - return true - } - // match: (SARXQ x (NEGQ (ADDQconst [c] y))) - // cond: c & 63 == 0 - // result: (SARXQ x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SARXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXQ x (ANDQconst [c] y)) - // cond: c & 63 == 63 - // result: (SARXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SARXQ) - v.AddArg2(x, y) - return true - } - // match: (SARXQ x (NEGQ (ANDQconst [c] y))) - // cond: c & 63 == 63 - // result: (SARXQ x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SARXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXQ x (ADDLconst [c] y)) - // cond: c & 63 == 0 - // result: (SARXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SARXQ) - v.AddArg2(x, y) - return true - } - // match: (SARXQ x (NEGL (ADDLconst [c] y))) - // cond: c & 63 == 0 - // result: (SARXQ x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SARXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXQ x (ANDLconst [c] y)) - // cond: c & 63 == 63 - // result: (SARXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SARXQ) - v.AddArg2(x, y) - return true - } - // match: (SARXQ x (NEGL (ANDLconst [c] y))) - // cond: c & 63 == 63 - // result: (SARXQ x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SARXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SARXQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (SARXQload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SARXQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64SARXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -21284,60 +20706,6 @@ } break } - // match: (SETEQ (TESTL (SHLXL (MOVLconst [1]) x) y)) - // result: (SETAE (BTL x y)) - for { - if v_0.Op != OpAMD64TESTL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXL { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } - break - } - // match: (SETEQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) - // result: (SETAE (BTQ x y)) - for { - if v_0.Op != OpAMD64TESTQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXQ { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } - break - } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAE (BTLconst [int8(log32(c))] x)) @@ -21763,72 +21131,6 @@ } break } - // match: (SETEQstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) - // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXL { - continue - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { - continue - } - y := v_1_1 - mem := v_2 - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg3(ptr, v0, mem) - return true - } - break - } - // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) - // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXQ { - continue - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { - continue - } - y := v_1_1 - mem := v_2 - v.reset(OpAMD64SETAEstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg3(ptr, v0, mem) - return true - } - break - } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) @@ -23320,60 +22622,6 @@ } break } - // match: (SETNE (TESTL (SHLXL (MOVLconst [1]) x) y)) - // result: (SETB (BTL x y)) - for { - if v_0.Op != OpAMD64TESTL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXL { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } - break - } - // match: (SETNE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) - // result: (SETB (BTQ x y)) - for { - if v_0.Op != OpAMD64TESTQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXQ { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) - return true - } - break - } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETB (BTLconst [int8(log32(c))] x)) @@ -23799,72 +23047,6 @@ } break } - // match: (SETNEstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) - // result: (SETBstore [off] {sym} ptr (BTL x y) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXL { - continue - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { - continue - } - y := v_1_1 - mem := v_2 - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg3(ptr, v0, mem) - return true - } - break - } - // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) - // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) - for { - off := auxIntToInt32(v.AuxInt) - sym := auxToSym(v.Aux) - ptr := v_0 - if v_1.Op != OpAMD64TESTQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXQ { - continue - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { - continue - } - y := v_1_1 - mem := v_2 - v.reset(OpAMD64SETBstore) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg3(ptr, v0, mem) - return true - } - break - } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) @@ -24379,19 +23561,6 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SHLL x y) - // cond: buildcfg.GOAMD64 >= 3 - // result: (SHLXL x y) - for { - x := v_0 - y := v_1 - if !(buildcfg.GOAMD64 >= 3) { - break - } - v.reset(OpAMD64SHLXL) - v.AddArg2(x, y) - return true - } // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { @@ -24582,6 +23751,28 @@ v.AddArg2(x, v0) return true } + // match: (SHLL l:(MOVLload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SHLXLload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVLload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHLXLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } return false } func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { @@ -24626,19 +23817,6 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SHLQ x y) - // cond: buildcfg.GOAMD64 >= 3 - // result: (SHLXQ x y) - for { - x := v_0 - y := v_1 - if !(buildcfg.GOAMD64 >= 3) { - break - } - v.reset(OpAMD64SHLXQ) - v.AddArg2(x, y) - return true - } // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { @@ -24829,6 +24007,28 @@ v.AddArg2(x, v0) return true } + // match: (SHLQ l:(MOVQload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SHLXQload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVQload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHLXQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } return false } func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { @@ -24881,224 +24081,6 @@ } return false } -func rewriteValueAMD64_OpAMD64SHLXL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SHLXL x (MOVQconst [c])) - // result: (SHLLconst [int8(c&31)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SHLLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) - return true - } - // match: (SHLXL x (MOVLconst [c])) - // result: (SHLLconst [int8(c&31)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SHLLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) - return true - } - // match: (SHLXL x (ADDQconst [c] y)) - // cond: c & 31 == 0 - // result: (SHLXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHLXL) - v.AddArg2(x, y) - return true - } - // match: (SHLXL x (NEGQ (ADDQconst [c] y))) - // cond: c & 31 == 0 - // result: (SHLXL x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHLXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXL x (ANDQconst [c] y)) - // cond: c & 31 == 31 - // result: (SHLXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHLXL) - v.AddArg2(x, y) - return true - } - // match: (SHLXL x (NEGQ (ANDQconst [c] y))) - // cond: c & 31 == 31 - // result: (SHLXL x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHLXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXL x (ADDLconst [c] y)) - // cond: c & 31 == 0 - // result: (SHLXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHLXL) - v.AddArg2(x, y) - return true - } - // match: (SHLXL x (NEGL (ADDLconst [c] y))) - // cond: c & 31 == 0 - // result: (SHLXL x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHLXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXL x (ANDLconst [c] y)) - // cond: c & 31 == 31 - // result: (SHLXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHLXL) - v.AddArg2(x, y) - return true - } - // match: (SHLXL x (NEGL (ANDLconst [c] y))) - // cond: c & 31 == 31 - // result: (SHLXL x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHLXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (SHLXLload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVLload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHLXLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64SHLXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -25127,224 +24109,6 @@ } return false } -func rewriteValueAMD64_OpAMD64SHLXQ(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SHLXQ x (MOVQconst [c])) - // result: (SHLQconst [int8(c&63)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SHLQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) - return true - } - // match: (SHLXQ x (MOVLconst [c])) - // result: (SHLQconst [int8(c&63)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SHLQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) - return true - } - // match: (SHLXQ x (ADDQconst [c] y)) - // cond: c & 63 == 0 - // result: (SHLXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHLXQ) - v.AddArg2(x, y) - return true - } - // match: (SHLXQ x (NEGQ (ADDQconst [c] y))) - // cond: c & 63 == 0 - // result: (SHLXQ x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHLXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXQ x (ANDQconst [c] y)) - // cond: c & 63 == 63 - // result: (SHLXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHLXQ) - v.AddArg2(x, y) - return true - } - // match: (SHLXQ x (NEGQ (ANDQconst [c] y))) - // cond: c & 63 == 63 - // result: (SHLXQ x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHLXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXQ x (ADDLconst [c] y)) - // cond: c & 63 == 0 - // result: (SHLXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHLXQ) - v.AddArg2(x, y) - return true - } - // match: (SHLXQ x (NEGL (ADDLconst [c] y))) - // cond: c & 63 == 0 - // result: (SHLXQ x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHLXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXQ x (ANDLconst [c] y)) - // cond: c & 63 == 63 - // result: (SHLXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHLXQ) - v.AddArg2(x, y) - return true - } - // match: (SHLXQ x (NEGL (ANDLconst [c] y))) - // cond: c & 63 == 63 - // result: (SHLXQ x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHLXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHLXQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (SHLXQload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHLXQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64SHLXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -25480,19 +24244,6 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SHRL x y) - // cond: buildcfg.GOAMD64 >= 3 - // result: (SHRXL x y) - for { - x := v_0 - y := v_1 - if !(buildcfg.GOAMD64 >= 3) { - break - } - v.reset(OpAMD64SHRXL) - v.AddArg2(x, y) - return true - } // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { @@ -25683,6 +24434,28 @@ v.AddArg2(x, v0) return true } + // match: (SHRL l:(MOVLload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SHRXLload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVLload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHRXLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } return false } func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { @@ -25715,19 +24488,6 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (SHRQ x y) - // cond: buildcfg.GOAMD64 >= 3 - // result: (SHRXQ x y) - for { - x := v_0 - y := v_1 - if !(buildcfg.GOAMD64 >= 3) { - break - } - v.reset(OpAMD64SHRXQ) - v.AddArg2(x, y) - return true - } // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { @@ -25918,6 +24678,28 @@ v.AddArg2(x, v0) return true } + // match: (SHRQ l:(MOVQload [off] {sym} ptr mem) x) + // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) + // result: (SHRXQload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVQload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHRXQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } return false } func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { @@ -26029,224 +24811,6 @@ } return false } -func rewriteValueAMD64_OpAMD64SHRXL(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SHRXL x (MOVQconst [c])) - // result: (SHRLconst [int8(c&31)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SHRLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) - return true - } - // match: (SHRXL x (MOVLconst [c])) - // result: (SHRLconst [int8(c&31)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SHRLconst) - v.AuxInt = int8ToAuxInt(int8(c & 31)) - v.AddArg(x) - return true - } - // match: (SHRXL x (ADDQconst [c] y)) - // cond: c & 31 == 0 - // result: (SHRXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHRXL) - v.AddArg2(x, y) - return true - } - // match: (SHRXL x (NEGQ (ADDQconst [c] y))) - // cond: c & 31 == 0 - // result: (SHRXL x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHRXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXL x (ANDQconst [c] y)) - // cond: c & 31 == 31 - // result: (SHRXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHRXL) - v.AddArg2(x, y) - return true - } - // match: (SHRXL x (NEGQ (ANDQconst [c] y))) - // cond: c & 31 == 31 - // result: (SHRXL x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHRXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXL x (ADDLconst [c] y)) - // cond: c & 31 == 0 - // result: (SHRXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHRXL) - v.AddArg2(x, y) - return true - } - // match: (SHRXL x (NEGL (ADDLconst [c] y))) - // cond: c & 31 == 0 - // result: (SHRXL x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 0) { - break - } - v.reset(OpAMD64SHRXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXL x (ANDLconst [c] y)) - // cond: c & 31 == 31 - // result: (SHRXL x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHRXL) - v.AddArg2(x, y) - return true - } - // match: (SHRXL x (NEGL (ANDLconst [c] y))) - // cond: c & 31 == 31 - // result: (SHRXL x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&31 == 31) { - break - } - v.reset(OpAMD64SHRXL) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (SHRXLload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVLload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHRXLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64SHRXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -26275,224 +24839,6 @@ } return false } -func rewriteValueAMD64_OpAMD64SHRXQ(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - b := v.Block - // match: (SHRXQ x (MOVQconst [c])) - // result: (SHRQconst [int8(c&63)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVQconst { - break - } - c := auxIntToInt64(v_1.AuxInt) - v.reset(OpAMD64SHRQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) - return true - } - // match: (SHRXQ x (MOVLconst [c])) - // result: (SHRQconst [int8(c&63)] x) - for { - x := v_0 - if v_1.Op != OpAMD64MOVLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - v.reset(OpAMD64SHRQconst) - v.AuxInt = int8ToAuxInt(int8(c & 63)) - v.AddArg(x) - return true - } - // match: (SHRXQ x (ADDQconst [c] y)) - // cond: c & 63 == 0 - // result: (SHRXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHRXQ) - v.AddArg2(x, y) - return true - } - // match: (SHRXQ x (NEGQ (ADDQconst [c] y))) - // cond: c & 63 == 0 - // result: (SHRXQ x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHRXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXQ x (ANDQconst [c] y)) - // cond: c & 63 == 63 - // result: (SHRXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHRXQ) - v.AddArg2(x, y) - return true - } - // match: (SHRXQ x (NEGQ (ANDQconst [c] y))) - // cond: c & 63 == 63 - // result: (SHRXQ x (NEGQ y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGQ { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDQconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHRXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXQ x (ADDLconst [c] y)) - // cond: c & 63 == 0 - // result: (SHRXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHRXQ) - v.AddArg2(x, y) - return true - } - // match: (SHRXQ x (NEGL (ADDLconst [c] y))) - // cond: c & 63 == 0 - // result: (SHRXQ x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ADDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 0) { - break - } - v.reset(OpAMD64SHRXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXQ x (ANDLconst [c] y)) - // cond: c & 63 == 63 - // result: (SHRXQ x y) - for { - x := v_0 - if v_1.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1.AuxInt) - y := v_1.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHRXQ) - v.AddArg2(x, y) - return true - } - // match: (SHRXQ x (NEGL (ANDLconst [c] y))) - // cond: c & 63 == 63 - // result: (SHRXQ x (NEGL y)) - for { - x := v_0 - if v_1.Op != OpAMD64NEGL { - break - } - t := v_1.Type - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64ANDLconst { - break - } - c := auxIntToInt32(v_1_0.AuxInt) - y := v_1_0.Args[0] - if !(c&63 == 63) { - break - } - v.reset(OpAMD64SHRXQ) - v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) - v0.AddArg(y) - v.AddArg2(x, v0) - return true - } - // match: (SHRXQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (SHRXQload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHRXQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -27824,25 +26170,6 @@ } break } - // match: (XORL (SHLXL (MOVLconst [1]) y) x) - // result: (BTCL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { - continue - } - x := v_1 - v.reset(OpAMD64BTCL) - v.AddArg2(x, y) - return true - } - break - } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) @@ -28306,25 +26633,6 @@ } break } - // match: (XORQ (SHLXQ (MOVQconst [1]) y) x) - // result: (BTCQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXQ { - continue - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 1 { - continue - } - x := v_1 - v.reset(OpAMD64BTCQ) - v.AddArg2(x, y) - return true - } - break - } // match: (XORQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCQconst [int8(log64(c))] x) @@ -34928,54 +33236,6 @@ } break } - // match: (EQ (TESTL (SHLXL (MOVLconst [1]) x) y)) - // result: (UGE (BTL x y)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXL { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - b.resetWithControl(BlockAMD64UGE, v0) - return true - } - break - } - // match: (EQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) - // result: (UGE (BTQ x y)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXQ { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - b.resetWithControl(BlockAMD64UGE, v0) - return true - } - break - } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (UGE (BTLconst [int8(log32(c))] x)) @@ -35792,54 +34052,6 @@ } break } - // match: (NE (TESTL (SHLXL (MOVLconst [1]) x) y)) - // result: (ULT (BTL x y)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXL { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg2(x, y) - b.resetWithControl(BlockAMD64ULT, v0) - return true - } - break - } - // match: (NE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) - // result: (ULT (BTQ x y)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - if v_0_0.Op != OpAMD64SHLXQ { - continue - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { - continue - } - y := v_0_1 - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg2(x, y) - b.resetWithControl(BlockAMD64ULT, v0) - return true - } - break - } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (ULT (BTLconst [int8(log32(c))] x)) go_4b78fe57a81fe4fd9a1c370c65e3a694066ac1ab_src_cmd_compile_internal_ssa_rewrite386.go.test000066400000000000000000042505441516001707200355510ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit 4b78fe57a81fe4fd9a1c370c65e3a694066ac1ab file testdata/go_4b78fe57a81fe4fd9a1c370c65e3a694066ac1ab_src_cmd_compile_internal_ssa_rewrite386.go.test -- x -- // Code generated from gen/386.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/internal/obj" import "cmd/internal/objabi" import "cmd/compile/internal/types" var _ = math.MinInt8 // in case not otherwise used var _ = obj.ANOP // in case not otherwise used var _ = objabi.GOROOT // in case not otherwise used var _ = types.TypeMem // in case not otherwise used func rewriteValue386(v *Value) bool { switch v.Op { case Op386ADCL: return rewriteValue386_Op386ADCL_0(v) case Op386ADDL: return rewriteValue386_Op386ADDL_0(v) || rewriteValue386_Op386ADDL_10(v) || rewriteValue386_Op386ADDL_20(v) case Op386ADDLcarry: return rewriteValue386_Op386ADDLcarry_0(v) case Op386ADDLconst: return rewriteValue386_Op386ADDLconst_0(v) case Op386ADDLconstmodify: return rewriteValue386_Op386ADDLconstmodify_0(v) case Op386ADDLconstmodifyidx4: return rewriteValue386_Op386ADDLconstmodifyidx4_0(v) case Op386ADDLload: return rewriteValue386_Op386ADDLload_0(v) case Op386ADDLloadidx4: return rewriteValue386_Op386ADDLloadidx4_0(v) case Op386ADDLmodify: return rewriteValue386_Op386ADDLmodify_0(v) case Op386ADDLmodifyidx4: return rewriteValue386_Op386ADDLmodifyidx4_0(v) case Op386ADDSD: return rewriteValue386_Op386ADDSD_0(v) case Op386ADDSDload: return rewriteValue386_Op386ADDSDload_0(v) case Op386ADDSS: return rewriteValue386_Op386ADDSS_0(v) case Op386ADDSSload: return rewriteValue386_Op386ADDSSload_0(v) case Op386ANDL: return rewriteValue386_Op386ANDL_0(v) case Op386ANDLconst: return rewriteValue386_Op386ANDLconst_0(v) case Op386ANDLconstmodify: return rewriteValue386_Op386ANDLconstmodify_0(v) case Op386ANDLconstmodifyidx4: return rewriteValue386_Op386ANDLconstmodifyidx4_0(v) case Op386ANDLload: return rewriteValue386_Op386ANDLload_0(v) case Op386ANDLloadidx4: return rewriteValue386_Op386ANDLloadidx4_0(v) case Op386ANDLmodify: return rewriteValue386_Op386ANDLmodify_0(v) case Op386ANDLmodifyidx4: return rewriteValue386_Op386ANDLmodifyidx4_0(v) case Op386CMPB: return rewriteValue386_Op386CMPB_0(v) case Op386CMPBconst: return rewriteValue386_Op386CMPBconst_0(v) case Op386CMPBload: return rewriteValue386_Op386CMPBload_0(v) case Op386CMPL: return rewriteValue386_Op386CMPL_0(v) case Op386CMPLconst: return rewriteValue386_Op386CMPLconst_0(v) || rewriteValue386_Op386CMPLconst_10(v) case Op386CMPLload: return rewriteValue386_Op386CMPLload_0(v) case Op386CMPW: return rewriteValue386_Op386CMPW_0(v) case Op386CMPWconst: return rewriteValue386_Op386CMPWconst_0(v) case Op386CMPWload: return rewriteValue386_Op386CMPWload_0(v) case Op386DIVSD: return rewriteValue386_Op386DIVSD_0(v) case Op386DIVSDload: return rewriteValue386_Op386DIVSDload_0(v) case Op386DIVSS: return rewriteValue386_Op386DIVSS_0(v) case Op386DIVSSload: return rewriteValue386_Op386DIVSSload_0(v) case Op386LEAL: return rewriteValue386_Op386LEAL_0(v) case Op386LEAL1: return rewriteValue386_Op386LEAL1_0(v) case Op386LEAL2: return rewriteValue386_Op386LEAL2_0(v) case Op386LEAL4: return rewriteValue386_Op386LEAL4_0(v) case Op386LEAL8: return rewriteValue386_Op386LEAL8_0(v) case Op386MOVBLSX: return rewriteValue386_Op386MOVBLSX_0(v) case Op386MOVBLSXload: return rewriteValue386_Op386MOVBLSXload_0(v) case Op386MOVBLZX: return rewriteValue386_Op386MOVBLZX_0(v) case Op386MOVBload: return rewriteValue386_Op386MOVBload_0(v) case Op386MOVBloadidx1: return rewriteValue386_Op386MOVBloadidx1_0(v) case Op386MOVBstore: return rewriteValue386_Op386MOVBstore_0(v) case Op386MOVBstoreconst: return rewriteValue386_Op386MOVBstoreconst_0(v) case Op386MOVBstoreconstidx1: return rewriteValue386_Op386MOVBstoreconstidx1_0(v) case Op386MOVBstoreidx1: return rewriteValue386_Op386MOVBstoreidx1_0(v) || rewriteValue386_Op386MOVBstoreidx1_10(v) case Op386MOVLload: return rewriteValue386_Op386MOVLload_0(v) case Op386MOVLloadidx1: return rewriteValue386_Op386MOVLloadidx1_0(v) case Op386MOVLloadidx4: return rewriteValue386_Op386MOVLloadidx4_0(v) case Op386MOVLstore: return rewriteValue386_Op386MOVLstore_0(v) || rewriteValue386_Op386MOVLstore_10(v) || rewriteValue386_Op386MOVLstore_20(v) case Op386MOVLstoreconst: return rewriteValue386_Op386MOVLstoreconst_0(v) case Op386MOVLstoreconstidx1: return rewriteValue386_Op386MOVLstoreconstidx1_0(v) case Op386MOVLstoreconstidx4: return rewriteValue386_Op386MOVLstoreconstidx4_0(v) case Op386MOVLstoreidx1: return rewriteValue386_Op386MOVLstoreidx1_0(v) case Op386MOVLstoreidx4: return rewriteValue386_Op386MOVLstoreidx4_0(v) || rewriteValue386_Op386MOVLstoreidx4_10(v) case Op386MOVSDconst: return rewriteValue386_Op386MOVSDconst_0(v) case Op386MOVSDload: return rewriteValue386_Op386MOVSDload_0(v) case Op386MOVSDloadidx1: return rewriteValue386_Op386MOVSDloadidx1_0(v) case Op386MOVSDloadidx8: return rewriteValue386_Op386MOVSDloadidx8_0(v) case Op386MOVSDstore: return rewriteValue386_Op386MOVSDstore_0(v) case Op386MOVSDstoreidx1: return rewriteValue386_Op386MOVSDstoreidx1_0(v) case Op386MOVSDstoreidx8: return rewriteValue386_Op386MOVSDstoreidx8_0(v) case Op386MOVSSconst: return rewriteValue386_Op386MOVSSconst_0(v) case Op386MOVSSload: return rewriteValue386_Op386MOVSSload_0(v) case Op386MOVSSloadidx1: return rewriteValue386_Op386MOVSSloadidx1_0(v) case Op386MOVSSloadidx4: return rewriteValue386_Op386MOVSSloadidx4_0(v) case Op386MOVSSstore: return rewriteValue386_Op386MOVSSstore_0(v) case Op386MOVSSstoreidx1: return rewriteValue386_Op386MOVSSstoreidx1_0(v) case Op386MOVSSstoreidx4: return rewriteValue386_Op386MOVSSstoreidx4_0(v) case Op386MOVWLSX: return rewriteValue386_Op386MOVWLSX_0(v) case Op386MOVWLSXload: return rewriteValue386_Op386MOVWLSXload_0(v) case Op386MOVWLZX: return rewriteValue386_Op386MOVWLZX_0(v) case Op386MOVWload: return rewriteValue386_Op386MOVWload_0(v) case Op386MOVWloadidx1: return rewriteValue386_Op386MOVWloadidx1_0(v) case Op386MOVWloadidx2: return rewriteValue386_Op386MOVWloadidx2_0(v) case Op386MOVWstore: return rewriteValue386_Op386MOVWstore_0(v) case Op386MOVWstoreconst: return rewriteValue386_Op386MOVWstoreconst_0(v) case Op386MOVWstoreconstidx1: return rewriteValue386_Op386MOVWstoreconstidx1_0(v) case Op386MOVWstoreconstidx2: return rewriteValue386_Op386MOVWstoreconstidx2_0(v) case Op386MOVWstoreidx1: return rewriteValue386_Op386MOVWstoreidx1_0(v) || rewriteValue386_Op386MOVWstoreidx1_10(v) case Op386MOVWstoreidx2: return rewriteValue386_Op386MOVWstoreidx2_0(v) case Op386MULL: return rewriteValue386_Op386MULL_0(v) case Op386MULLconst: return rewriteValue386_Op386MULLconst_0(v) || rewriteValue386_Op386MULLconst_10(v) || rewriteValue386_Op386MULLconst_20(v) || rewriteValue386_Op386MULLconst_30(v) case Op386MULLload: return rewriteValue386_Op386MULLload_0(v) case Op386MULLloadidx4: return rewriteValue386_Op386MULLloadidx4_0(v) case Op386MULSD: return rewriteValue386_Op386MULSD_0(v) case Op386MULSDload: return rewriteValue386_Op386MULSDload_0(v) case Op386MULSS: return rewriteValue386_Op386MULSS_0(v) case Op386MULSSload: return rewriteValue386_Op386MULSSload_0(v) case Op386NEGL: return rewriteValue386_Op386NEGL_0(v) case Op386NOTL: return rewriteValue386_Op386NOTL_0(v) case Op386ORL: return rewriteValue386_Op386ORL_0(v) || rewriteValue386_Op386ORL_10(v) || rewriteValue386_Op386ORL_20(v) || rewriteValue386_Op386ORL_30(v) || rewriteValue386_Op386ORL_40(v) || rewriteValue386_Op386ORL_50(v) case Op386ORLconst: return rewriteValue386_Op386ORLconst_0(v) case Op386ORLconstmodify: return rewriteValue386_Op386ORLconstmodify_0(v) case Op386ORLconstmodifyidx4: return rewriteValue386_Op386ORLconstmodifyidx4_0(v) case Op386ORLload: return rewriteValue386_Op386ORLload_0(v) case Op386ORLloadidx4: return rewriteValue386_Op386ORLloadidx4_0(v) case Op386ORLmodify: return rewriteValue386_Op386ORLmodify_0(v) case Op386ORLmodifyidx4: return rewriteValue386_Op386ORLmodifyidx4_0(v) case Op386ROLBconst: return rewriteValue386_Op386ROLBconst_0(v) case Op386ROLLconst: return rewriteValue386_Op386ROLLconst_0(v) case Op386ROLWconst: return rewriteValue386_Op386ROLWconst_0(v) case Op386SARB: return rewriteValue386_Op386SARB_0(v) case Op386SARBconst: return rewriteValue386_Op386SARBconst_0(v) case Op386SARL: return rewriteValue386_Op386SARL_0(v) case Op386SARLconst: return rewriteValue386_Op386SARLconst_0(v) case Op386SARW: return rewriteValue386_Op386SARW_0(v) case Op386SARWconst: return rewriteValue386_Op386SARWconst_0(v) case Op386SBBL: return rewriteValue386_Op386SBBL_0(v) case Op386SBBLcarrymask: return rewriteValue386_Op386SBBLcarrymask_0(v) case Op386SETA: return rewriteValue386_Op386SETA_0(v) case Op386SETAE: return rewriteValue386_Op386SETAE_0(v) case Op386SETB: return rewriteValue386_Op386SETB_0(v) case Op386SETBE: return rewriteValue386_Op386SETBE_0(v) case Op386SETEQ: return rewriteValue386_Op386SETEQ_0(v) case Op386SETG: return rewriteValue386_Op386SETG_0(v) case Op386SETGE: return rewriteValue386_Op386SETGE_0(v) case Op386SETL: return rewriteValue386_Op386SETL_0(v) case Op386SETLE: return rewriteValue386_Op386SETLE_0(v) case Op386SETNE: return rewriteValue386_Op386SETNE_0(v) case Op386SHLL: return rewriteValue386_Op386SHLL_0(v) case Op386SHLLconst: return rewriteValue386_Op386SHLLconst_0(v) case Op386SHRB: return rewriteValue386_Op386SHRB_0(v) case Op386SHRBconst: return rewriteValue386_Op386SHRBconst_0(v) case Op386SHRL: return rewriteValue386_Op386SHRL_0(v) case Op386SHRLconst: return rewriteValue386_Op386SHRLconst_0(v) case Op386SHRW: return rewriteValue386_Op386SHRW_0(v) case Op386SHRWconst: return rewriteValue386_Op386SHRWconst_0(v) case Op386SUBL: return rewriteValue386_Op386SUBL_0(v) case Op386SUBLcarry: return rewriteValue386_Op386SUBLcarry_0(v) case Op386SUBLconst: return rewriteValue386_Op386SUBLconst_0(v) case Op386SUBLload: return rewriteValue386_Op386SUBLload_0(v) case Op386SUBLloadidx4: return rewriteValue386_Op386SUBLloadidx4_0(v) case Op386SUBLmodify: return rewriteValue386_Op386SUBLmodify_0(v) case Op386SUBLmodifyidx4: return rewriteValue386_Op386SUBLmodifyidx4_0(v) case Op386SUBSD: return rewriteValue386_Op386SUBSD_0(v) case Op386SUBSDload: return rewriteValue386_Op386SUBSDload_0(v) case Op386SUBSS: return rewriteValue386_Op386SUBSS_0(v) case Op386SUBSSload: return rewriteValue386_Op386SUBSSload_0(v) case Op386XORL: return rewriteValue386_Op386XORL_0(v) || rewriteValue386_Op386XORL_10(v) case Op386XORLconst: return rewriteValue386_Op386XORLconst_0(v) case Op386XORLconstmodify: return rewriteValue386_Op386XORLconstmodify_0(v) case Op386XORLconstmodifyidx4: return rewriteValue386_Op386XORLconstmodifyidx4_0(v) case Op386XORLload: return rewriteValue386_Op386XORLload_0(v) case Op386XORLloadidx4: return rewriteValue386_Op386XORLloadidx4_0(v) case Op386XORLmodify: return rewriteValue386_Op386XORLmodify_0(v) case Op386XORLmodifyidx4: return rewriteValue386_Op386XORLmodifyidx4_0(v) case OpAdd16: return rewriteValue386_OpAdd16_0(v) case OpAdd32: return rewriteValue386_OpAdd32_0(v) case OpAdd32F: return rewriteValue386_OpAdd32F_0(v) case OpAdd32carry: return rewriteValue386_OpAdd32carry_0(v) case OpAdd32withcarry: return rewriteValue386_OpAdd32withcarry_0(v) case OpAdd64F: return rewriteValue386_OpAdd64F_0(v) case OpAdd8: return rewriteValue386_OpAdd8_0(v) case OpAddPtr: return rewriteValue386_OpAddPtr_0(v) case OpAddr: return rewriteValue386_OpAddr_0(v) case OpAnd16: return rewriteValue386_OpAnd16_0(v) case OpAnd32: return rewriteValue386_OpAnd32_0(v) case OpAnd8: return rewriteValue386_OpAnd8_0(v) case OpAndB: return rewriteValue386_OpAndB_0(v) case OpAvg32u: return rewriteValue386_OpAvg32u_0(v) case OpBswap32: return rewriteValue386_OpBswap32_0(v) case OpClosureCall: return rewriteValue386_OpClosureCall_0(v) case OpCom16: return rewriteValue386_OpCom16_0(v) case OpCom32: return rewriteValue386_OpCom32_0(v) case OpCom8: return rewriteValue386_OpCom8_0(v) case OpConst16: return rewriteValue386_OpConst16_0(v) case OpConst32: return rewriteValue386_OpConst32_0(v) case OpConst32F: return rewriteValue386_OpConst32F_0(v) case OpConst64F: return rewriteValue386_OpConst64F_0(v) case OpConst8: return rewriteValue386_OpConst8_0(v) case OpConstBool: return rewriteValue386_OpConstBool_0(v) case OpConstNil: return rewriteValue386_OpConstNil_0(v) case OpCvt32Fto32: return rewriteValue386_OpCvt32Fto32_0(v) case OpCvt32Fto64F: return rewriteValue386_OpCvt32Fto64F_0(v) case OpCvt32to32F: return rewriteValue386_OpCvt32to32F_0(v) case OpCvt32to64F: return rewriteValue386_OpCvt32to64F_0(v) case OpCvt64Fto32: return rewriteValue386_OpCvt64Fto32_0(v) case OpCvt64Fto32F: return rewriteValue386_OpCvt64Fto32F_0(v) case OpDiv16: return rewriteValue386_OpDiv16_0(v) case OpDiv16u: return rewriteValue386_OpDiv16u_0(v) case OpDiv32: return rewriteValue386_OpDiv32_0(v) case OpDiv32F: return rewriteValue386_OpDiv32F_0(v) case OpDiv32u: return rewriteValue386_OpDiv32u_0(v) case OpDiv64F: return rewriteValue386_OpDiv64F_0(v) case OpDiv8: return rewriteValue386_OpDiv8_0(v) case OpDiv8u: return rewriteValue386_OpDiv8u_0(v) case OpEq16: return rewriteValue386_OpEq16_0(v) case OpEq32: return rewriteValue386_OpEq32_0(v) case OpEq32F: return rewriteValue386_OpEq32F_0(v) case OpEq64F: return rewriteValue386_OpEq64F_0(v) case OpEq8: return rewriteValue386_OpEq8_0(v) case OpEqB: return rewriteValue386_OpEqB_0(v) case OpEqPtr: return rewriteValue386_OpEqPtr_0(v) case OpGeq16: return rewriteValue386_OpGeq16_0(v) case OpGeq16U: return rewriteValue386_OpGeq16U_0(v) case OpGeq32: return rewriteValue386_OpGeq32_0(v) case OpGeq32F: return rewriteValue386_OpGeq32F_0(v) case OpGeq32U: return rewriteValue386_OpGeq32U_0(v) case OpGeq64F: return rewriteValue386_OpGeq64F_0(v) case OpGeq8: return rewriteValue386_OpGeq8_0(v) case OpGeq8U: return rewriteValue386_OpGeq8U_0(v) case OpGetCallerPC: return rewriteValue386_OpGetCallerPC_0(v) case OpGetCallerSP: return rewriteValue386_OpGetCallerSP_0(v) case OpGetClosurePtr: return rewriteValue386_OpGetClosurePtr_0(v) case OpGetG: return rewriteValue386_OpGetG_0(v) case OpGreater16: return rewriteValue386_OpGreater16_0(v) case OpGreater16U: return rewriteValue386_OpGreater16U_0(v) case OpGreater32: return rewriteValue386_OpGreater32_0(v) case OpGreater32F: return rewriteValue386_OpGreater32F_0(v) case OpGreater32U: return rewriteValue386_OpGreater32U_0(v) case OpGreater64F: return rewriteValue386_OpGreater64F_0(v) case OpGreater8: return rewriteValue386_OpGreater8_0(v) case OpGreater8U: return rewriteValue386_OpGreater8U_0(v) case OpHmul32: return rewriteValue386_OpHmul32_0(v) case OpHmul32u: return rewriteValue386_OpHmul32u_0(v) case OpInterCall: return rewriteValue386_OpInterCall_0(v) case OpIsInBounds: return rewriteValue386_OpIsInBounds_0(v) case OpIsNonNil: return rewriteValue386_OpIsNonNil_0(v) case OpIsSliceInBounds: return rewriteValue386_OpIsSliceInBounds_0(v) case OpLeq16: return rewriteValue386_OpLeq16_0(v) case OpLeq16U: return rewriteValue386_OpLeq16U_0(v) case OpLeq32: return rewriteValue386_OpLeq32_0(v) case OpLeq32F: return rewriteValue386_OpLeq32F_0(v) case OpLeq32U: return rewriteValue386_OpLeq32U_0(v) case OpLeq64F: return rewriteValue386_OpLeq64F_0(v) case OpLeq8: return rewriteValue386_OpLeq8_0(v) case OpLeq8U: return rewriteValue386_OpLeq8U_0(v) case OpLess16: return rewriteValue386_OpLess16_0(v) case OpLess16U: return rewriteValue386_OpLess16U_0(v) case OpLess32: return rewriteValue386_OpLess32_0(v) case OpLess32F: return rewriteValue386_OpLess32F_0(v) case OpLess32U: return rewriteValue386_OpLess32U_0(v) case OpLess64F: return rewriteValue386_OpLess64F_0(v) case OpLess8: return rewriteValue386_OpLess8_0(v) case OpLess8U: return rewriteValue386_OpLess8U_0(v) case OpLoad: return rewriteValue386_OpLoad_0(v) case OpLocalAddr: return rewriteValue386_OpLocalAddr_0(v) case OpLsh16x16: return rewriteValue386_OpLsh16x16_0(v) case OpLsh16x32: return rewriteValue386_OpLsh16x32_0(v) case OpLsh16x64: return rewriteValue386_OpLsh16x64_0(v) case OpLsh16x8: return rewriteValue386_OpLsh16x8_0(v) case OpLsh32x16: return rewriteValue386_OpLsh32x16_0(v) case OpLsh32x32: return rewriteValue386_OpLsh32x32_0(v) case OpLsh32x64: return rewriteValue386_OpLsh32x64_0(v) case OpLsh32x8: return rewriteValue386_OpLsh32x8_0(v) case OpLsh8x16: return rewriteValue386_OpLsh8x16_0(v) case OpLsh8x32: return rewriteValue386_OpLsh8x32_0(v) case OpLsh8x64: return rewriteValue386_OpLsh8x64_0(v) case OpLsh8x8: return rewriteValue386_OpLsh8x8_0(v) case OpMod16: return rewriteValue386_OpMod16_0(v) case OpMod16u: return rewriteValue386_OpMod16u_0(v) case OpMod32: return rewriteValue386_OpMod32_0(v) case OpMod32u: return rewriteValue386_OpMod32u_0(v) case OpMod8: return rewriteValue386_OpMod8_0(v) case OpMod8u: return rewriteValue386_OpMod8u_0(v) case OpMove: return rewriteValue386_OpMove_0(v) || rewriteValue386_OpMove_10(v) case OpMul16: return rewriteValue386_OpMul16_0(v) case OpMul32: return rewriteValue386_OpMul32_0(v) case OpMul32F: return rewriteValue386_OpMul32F_0(v) case OpMul32uhilo: return rewriteValue386_OpMul32uhilo_0(v) case OpMul64F: return rewriteValue386_OpMul64F_0(v) case OpMul8: return rewriteValue386_OpMul8_0(v) case OpNeg16: return rewriteValue386_OpNeg16_0(v) case OpNeg32: return rewriteValue386_OpNeg32_0(v) case OpNeg32F: return rewriteValue386_OpNeg32F_0(v) case OpNeg64F: return rewriteValue386_OpNeg64F_0(v) case OpNeg8: return rewriteValue386_OpNeg8_0(v) case OpNeq16: return rewriteValue386_OpNeq16_0(v) case OpNeq32: return rewriteValue386_OpNeq32_0(v) case OpNeq32F: return rewriteValue386_OpNeq32F_0(v) case OpNeq64F: return rewriteValue386_OpNeq64F_0(v) case OpNeq8: return rewriteValue386_OpNeq8_0(v) case OpNeqB: return rewriteValue386_OpNeqB_0(v) case OpNeqPtr: return rewriteValue386_OpNeqPtr_0(v) case OpNilCheck: return rewriteValue386_OpNilCheck_0(v) case OpNot: return rewriteValue386_OpNot_0(v) case OpOffPtr: return rewriteValue386_OpOffPtr_0(v) case OpOr16: return rewriteValue386_OpOr16_0(v) case OpOr32: return rewriteValue386_OpOr32_0(v) case OpOr8: return rewriteValue386_OpOr8_0(v) case OpOrB: return rewriteValue386_OpOrB_0(v) case OpRound32F: return rewriteValue386_OpRound32F_0(v) case OpRound64F: return rewriteValue386_OpRound64F_0(v) case OpRsh16Ux16: return rewriteValue386_OpRsh16Ux16_0(v) case OpRsh16Ux32: return rewriteValue386_OpRsh16Ux32_0(v) case OpRsh16Ux64: return rewriteValue386_OpRsh16Ux64_0(v) case OpRsh16Ux8: return rewriteValue386_OpRsh16Ux8_0(v) case OpRsh16x16: return rewriteValue386_OpRsh16x16_0(v) case OpRsh16x32: return rewriteValue386_OpRsh16x32_0(v) case OpRsh16x64: return rewriteValue386_OpRsh16x64_0(v) case OpRsh16x8: return rewriteValue386_OpRsh16x8_0(v) case OpRsh32Ux16: return rewriteValue386_OpRsh32Ux16_0(v) case OpRsh32Ux32: return rewriteValue386_OpRsh32Ux32_0(v) case OpRsh32Ux64: return rewriteValue386_OpRsh32Ux64_0(v) case OpRsh32Ux8: return rewriteValue386_OpRsh32Ux8_0(v) case OpRsh32x16: return rewriteValue386_OpRsh32x16_0(v) case OpRsh32x32: return rewriteValue386_OpRsh32x32_0(v) case OpRsh32x64: return rewriteValue386_OpRsh32x64_0(v) case OpRsh32x8: return rewriteValue386_OpRsh32x8_0(v) case OpRsh8Ux16: return rewriteValue386_OpRsh8Ux16_0(v) case OpRsh8Ux32: return rewriteValue386_OpRsh8Ux32_0(v) case OpRsh8Ux64: return rewriteValue386_OpRsh8Ux64_0(v) case OpRsh8Ux8: return rewriteValue386_OpRsh8Ux8_0(v) case OpRsh8x16: return rewriteValue386_OpRsh8x16_0(v) case OpRsh8x32: return rewriteValue386_OpRsh8x32_0(v) case OpRsh8x64: return rewriteValue386_OpRsh8x64_0(v) case OpRsh8x8: return rewriteValue386_OpRsh8x8_0(v) case OpSelect0: return rewriteValue386_OpSelect0_0(v) case OpSelect1: return rewriteValue386_OpSelect1_0(v) case OpSignExt16to32: return rewriteValue386_OpSignExt16to32_0(v) case OpSignExt8to16: return rewriteValue386_OpSignExt8to16_0(v) case OpSignExt8to32: return rewriteValue386_OpSignExt8to32_0(v) case OpSignmask: return rewriteValue386_OpSignmask_0(v) case OpSlicemask: return rewriteValue386_OpSlicemask_0(v) case OpSqrt: return rewriteValue386_OpSqrt_0(v) case OpStaticCall: return rewriteValue386_OpStaticCall_0(v) case OpStore: return rewriteValue386_OpStore_0(v) case OpSub16: return rewriteValue386_OpSub16_0(v) case OpSub32: return rewriteValue386_OpSub32_0(v) case OpSub32F: return rewriteValue386_OpSub32F_0(v) case OpSub32carry: return rewriteValue386_OpSub32carry_0(v) case OpSub32withcarry: return rewriteValue386_OpSub32withcarry_0(v) case OpSub64F: return rewriteValue386_OpSub64F_0(v) case OpSub8: return rewriteValue386_OpSub8_0(v) case OpSubPtr: return rewriteValue386_OpSubPtr_0(v) case OpTrunc16to8: return rewriteValue386_OpTrunc16to8_0(v) case OpTrunc32to16: return rewriteValue386_OpTrunc32to16_0(v) case OpTrunc32to8: return rewriteValue386_OpTrunc32to8_0(v) case OpWB: return rewriteValue386_OpWB_0(v) case OpXor16: return rewriteValue386_OpXor16_0(v) case OpXor32: return rewriteValue386_OpXor32_0(v) case OpXor8: return rewriteValue386_OpXor8_0(v) case OpZero: return rewriteValue386_OpZero_0(v) || rewriteValue386_OpZero_10(v) case OpZeroExt16to32: return rewriteValue386_OpZeroExt16to32_0(v) case OpZeroExt8to16: return rewriteValue386_OpZeroExt8to16_0(v) case OpZeroExt8to32: return rewriteValue386_OpZeroExt8to32_0(v) case OpZeromask: return rewriteValue386_OpZeromask_0(v) } return false } func rewriteValue386_Op386ADCL_0(v *Value) bool { // match: (ADCL x (MOVLconst [c]) f) // cond: // result: (ADCLconst [c] x f) for { _ = v.Args[2] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt f := v.Args[2] v.reset(Op386ADCLconst) v.AuxInt = c v.AddArg(x) v.AddArg(f) return true } // match: (ADCL (MOVLconst [c]) x f) // cond: // result: (ADCLconst [c] x f) for { _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] f := v.Args[2] v.reset(Op386ADCLconst) v.AuxInt = c v.AddArg(x) v.AddArg(f) return true } // match: (ADCL (MOVLconst [c]) x f) // cond: // result: (ADCLconst [c] x f) for { _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] f := v.Args[2] v.reset(Op386ADCLconst) v.AuxInt = c v.AddArg(x) v.AddArg(f) return true } // match: (ADCL x (MOVLconst [c]) f) // cond: // result: (ADCLconst [c] x f) for { _ = v.Args[2] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt f := v.Args[2] v.reset(Op386ADCLconst) v.AuxInt = c v.AddArg(x) v.AddArg(f) return true } return false } func rewriteValue386_Op386ADDL_0(v *Value) bool { // match: (ADDL x (MOVLconst [c])) // cond: // result: (ADDLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386ADDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (MOVLconst [c]) x) // cond: // result: (ADDLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386ADDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHLLconst [c] x) (SHRLconst [d] x)) // cond: d == 32-c // result: (ROLLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(Op386ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHRLconst [d] x) (SHLLconst [c] x)) // cond: d == 32-c // result: (ROLLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(Op386ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHLLconst x [c]) (SHRWconst x [d])) // cond: c < 16 && d == 16-c && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 16 && d == 16-c && t.Size() == 2) { break } v.reset(Op386ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHRWconst x [d]) (SHLLconst x [c])) // cond: c < 16 && d == 16-c && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 16 && d == 16-c && t.Size() == 2) { break } v.reset(Op386ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHLLconst x [c]) (SHRBconst x [d])) // cond: c < 8 && d == 8-c && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRBconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 8 && d == 8-c && t.Size() == 1) { break } v.reset(Op386ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHRBconst x [d]) (SHLLconst x [c])) // cond: c < 8 && d == 8-c && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRBconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 8 && d == 8-c && t.Size() == 1) { break } v.reset(Op386ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL x (SHLLconst [3] y)) // cond: // result: (LEAL8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 3 { break } y := v_1.Args[0] v.reset(Op386LEAL8) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (SHLLconst [3] y) x) // cond: // result: (LEAL8 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 3 { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386LEAL8) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386ADDL_10(v *Value) bool { // match: (ADDL x (SHLLconst [2] y)) // cond: // result: (LEAL4 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(Op386LEAL4) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (SHLLconst [2] y) x) // cond: // result: (LEAL4 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 2 { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386LEAL4) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (SHLLconst [1] y)) // cond: // result: (LEAL2 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(Op386LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (SHLLconst [1] y) x) // cond: // result: (LEAL2 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 1 { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (ADDL y y)) // cond: // result: (LEAL2 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDL { break } _ = v_1.Args[1] y := v_1.Args[0] if y != v_1.Args[1] { break } v.reset(Op386LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (ADDL y y) x) // cond: // result: (LEAL2 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] y := v_0.Args[0] if y != v_0.Args[1] { break } x := v.Args[1] v.reset(Op386LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (ADDL x y)) // cond: // result: (LEAL2 y x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } y := v_1.Args[1] v.reset(Op386LEAL2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDL x (ADDL y x)) // cond: // result: (LEAL2 y x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDL { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(Op386LEAL2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDL (ADDL x y) x) // cond: // result: (LEAL2 y x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if x != v.Args[1] { break } v.reset(Op386LEAL2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDL (ADDL y x) x) // cond: // result: (LEAL2 y x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] y := v_0.Args[0] x := v_0.Args[1] if x != v.Args[1] { break } v.reset(Op386LEAL2) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValue386_Op386ADDL_20(v *Value) bool { // match: (ADDL (ADDLconst [c] x) y) // cond: // result: (LEAL1 [c] x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } c := v_0.AuxInt x := v_0.Args[0] y := v.Args[1] v.reset(Op386LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDL y (ADDLconst [c] x)) // cond: // result: (LEAL1 [c] x y) for { _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } c := v_1.AuxInt x := v_1.Args[0] v.reset(Op386LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } c := v_1.AuxInt s := v_1.Aux y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (LEAL [c] {s} y) x) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } c := v_0.AuxInt s := v_0.Aux y := v_0.Args[0] x := v.Args[1] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ADDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ADDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ADDLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ADDLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (ADDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ADDLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ADDLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (ADDL x (NEGL y)) // cond: // result: (SUBL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386NEGL { break } y := v_1.Args[0] v.reset(Op386SUBL) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (NEGL y) x) // cond: // result: (SUBL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386NEGL { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386SUBL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386ADDLcarry_0(v *Value) bool { // match: (ADDLcarry x (MOVLconst [c])) // cond: // result: (ADDLconstcarry [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386ADDLconstcarry) v.AuxInt = c v.AddArg(x) return true } // match: (ADDLcarry (MOVLconst [c]) x) // cond: // result: (ADDLconstcarry [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386ADDLconstcarry) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValue386_Op386ADDLconst_0(v *Value) bool { // match: (ADDLconst [c] (ADDL x y)) // cond: // result: (LEAL1 [c] x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] v.reset(Op386LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(c+d) // result: (LEAL [c+d] {s} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } d := v_0.AuxInt s := v_0.Aux x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(Op386LEAL) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } d := v_0.AuxInt s := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(c + d)) { break } v.reset(Op386LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL2 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386LEAL2 { break } d := v_0.AuxInt s := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(c + d)) { break } v.reset(Op386LEAL2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL4 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } d := v_0.AuxInt s := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(c + d)) { break } v.reset(Op386LEAL4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL8 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386LEAL8 { break } d := v_0.AuxInt s := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(c + d)) { break } v.reset(Op386LEAL8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] x) // cond: int32(c)==0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [int64(int32(c+d))]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = int64(int32(c + d)) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // cond: // result: (ADDLconst [int64(int32(c+d))] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ADDLconst) v.AuxInt = int64(int32(c + d)) v.AddArg(x) return true } return false } func rewriteValue386_Op386ADDLconstmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386ADDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDLconstmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386ADDLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ADDLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem) // cond: ValAndOff(valoff1).canAdd(off2*4) // result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2 * 4)) { break } v.reset(Op386ADDLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2 * 4) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ADDLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDLload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ADDLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL4 { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[1] ptr := v_1.Args[0] idx := v_1.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386ADDLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDLloadidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem) // cond: is32Bit(off1+off2) // result: (ADDLloadidx4 [off1+off2] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ADDLloadidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ADDLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem) // cond: is32Bit(off1+off2*4) // result: (ADDLloadidx4 [off1+off2*4] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] base := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386ADDLconst { break } off2 := v_2.AuxInt idx := v_2.Args[0] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386ADDLloadidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ADDLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDLmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDLmodify [off1] {sym} (ADDLconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ADDLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDLmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem) // cond: is32Bit(off1+off2) // result: (ADDLmodifyidx4 [off1+off2] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ADDLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem) // cond: is32Bit(off1+off2*4) // result: (ADDLmodifyidx4 [off1+off2*4] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386ADDLmodifyidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem) // cond: validValAndOff(c,off) // result: (ADDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386MOVLconst { break } c := v_2.AuxInt mem := v.Args[3] if !(validValAndOff(c, off)) { break } v.reset(Op386ADDLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDSD_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSDload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386ADDSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDSD l:(MOVSDload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVSDload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386ADDSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDSDload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDSDload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ADDSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDSS_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSSload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386ADDSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDSS l:(MOVSSload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVSSload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386ADDSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDSSload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDSSload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ADDSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ANDL_0(v *Value) bool { // match: (ANDL x (MOVLconst [c])) // cond: // result: (ANDLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386ANDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ANDL (MOVLconst [c]) x) // cond: // result: (ANDLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386ANDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ANDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ANDL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ANDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ANDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ANDLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ANDLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (ANDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ANDLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ANDLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (ANDL x x) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] if x != v.Args[1] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386ANDLconst_0(v *Value) bool { // match: (ANDLconst [c] (ANDLconst [d] x)) // cond: // result: (ANDLconst [c & d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ANDLconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDLconst [c] _) // cond: int32(c)==0 // result: (MOVLconst [0]) for { c := v.AuxInt if !(int32(c) == 0) { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (ANDLconst [c] x) // cond: int32(c)==-1 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == -1) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDLconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [c&d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = c & d return true } return false } func rewriteValue386_Op386ANDLconstmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ANDLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386ANDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ANDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ANDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ANDLconstmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ANDLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386ANDLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ANDLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem) // cond: ValAndOff(valoff1).canAdd(off2*4) // result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2 * 4)) { break } v.reset(Op386ANDLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2 * 4) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ANDLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ANDLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ANDLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ANDLload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ANDLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ANDLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ANDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ANDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ANDLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ANDLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ANDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL4 { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[1] ptr := v_1.Args[0] idx := v_1.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386ANDLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ANDLloadidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ANDLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem) // cond: is32Bit(off1+off2) // result: (ANDLloadidx4 [off1+off2] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ANDLloadidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ANDLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem) // cond: is32Bit(off1+off2*4) // result: (ANDLloadidx4 [off1+off2*4] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] base := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386ADDLconst { break } off2 := v_2.AuxInt idx := v_2.Args[0] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386ANDLloadidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ANDLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ANDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ANDLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ANDLmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ANDLmodify [off1] {sym} (ADDLconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ANDLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ANDLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ANDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ANDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ANDLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ANDLmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ANDLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem) // cond: is32Bit(off1+off2) // result: (ANDLmodifyidx4 [off1+off2] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ANDLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ANDLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem) // cond: is32Bit(off1+off2*4) // result: (ANDLmodifyidx4 [off1+off2*4] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386ANDLmodifyidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ANDLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ANDLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ANDLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ANDLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem) // cond: validValAndOff(c,off) // result: (ANDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386MOVLconst { break } c := v_2.AuxInt mem := v.Args[3] if !(validValAndOff(c, off)) { break } v.reset(Op386ANDLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386CMPB_0(v *Value) bool { b := v.Block _ = b // match: (CMPB x (MOVLconst [c])) // cond: // result: (CMPBconst x [int64(int8(c))]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386CMPBconst) v.AuxInt = int64(int8(c)) v.AddArg(x) return true } // match: (CMPB (MOVLconst [c]) x) // cond: // result: (InvertFlags (CMPBconst x [int64(int8(c))])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386InvertFlags) v0 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v0.AuxInt = int64(int8(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPB l:(MOVBload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (CMPBload {sym} [off] ptr x mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVBload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386CMPBload) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (CMPB x l:(MOVBload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (InvertFlags (CMPBload {sym} [off] ptr x mem)) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVBload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386InvertFlags) v0 := b.NewValue0(v.Pos, Op386CMPBload, types.TypeFlags) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(x) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValue386_Op386CMPBconst_0(v *Value) bool { b := v.Block _ = b // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)==int8(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int8(x) == int8(y)) { break } v.reset(Op386FlagEQ) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)uint8(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int8(x) < int8(y) && uint8(x) > uint8(y)) { break } v.reset(Op386FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>int8(y) && uint8(x) int8(y) && uint8(x) < uint8(y)) { break } v.reset(Op386FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>int8(y) && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int8(x) > int8(y) && uint8(x) > uint8(y)) { break } v.reset(Op386FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < int8(n) // result: (FlagLT_ULT) for { n := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } m := v_0.AuxInt if !(0 <= int8(m) && int8(m) < int8(n)) { break } v.reset(Op386FlagLT_ULT) return true } // match: (CMPBconst l:(ANDL x y) [0]) // cond: l.Uses==1 // result: (TESTB x y) for { if v.AuxInt != 0 { break } l := v.Args[0] if l.Op != Op386ANDL { break } _ = l.Args[1] x := l.Args[0] y := l.Args[1] if !(l.Uses == 1) { break } v.reset(Op386TESTB) v.AddArg(x) v.AddArg(y) return true } // match: (CMPBconst l:(ANDLconst [c] x) [0]) // cond: l.Uses==1 // result: (TESTBconst [int64(int8(c))] x) for { if v.AuxInt != 0 { break } l := v.Args[0] if l.Op != Op386ANDLconst { break } c := l.AuxInt x := l.Args[0] if !(l.Uses == 1) { break } v.reset(Op386TESTBconst) v.AuxInt = int64(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // cond: // result: (TESTB x x) for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(Op386TESTB) v.AddArg(x) v.AddArg(x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(c,off)] ptr mem) for { c := v.AuxInt l := v.Args[0] if l.Op != Op386MOVBload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(v.Pos, Op386CMPBconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(c, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386CMPBload_0(v *Value) bool { // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // cond: validValAndOff(int64(int8(c)),off) // result: (CMPBconstload {sym} [makeValAndOff(int64(int8(c)),off)] ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt mem := v.Args[2] if !(validValAndOff(int64(int8(c)), off)) { break } v.reset(Op386CMPBconstload) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386CMPL_0(v *Value) bool { b := v.Block _ = b // match: (CMPL x (MOVLconst [c])) // cond: // result: (CMPLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386CMPLconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // cond: // result: (InvertFlags (CMPLconst x [c])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386InvertFlags) v0 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386CMPLload) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386InvertFlags) v0 := b.NewValue0(v.Pos, Op386CMPLload, types.TypeFlags) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(x) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValue386_Op386CMPLconst_0(v *Value) bool { // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(Op386FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)uint32(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int32(x) < int32(y) && uint32(x) > uint32(y)) { break } v.reset(Op386FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)>int32(y) && uint32(x) int32(y) && uint32(x) < uint32(y)) { break } v.reset(Op386FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)>int32(y) && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int32(x) > int32(y) && uint32(x) > uint32(y)) { break } v.reset(Op386FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint16(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int16(x) < int16(y) && uint16(x) > uint16(y)) { break } v.reset(Op386FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>int16(y) && uint16(x) int16(y) && uint16(x) < uint16(y)) { break } v.reset(Op386FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>int16(y) && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int16(x) > int16(y) && uint16(x) > uint16(y)) { break } v.reset(Op386FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < int16(n) // result: (FlagLT_ULT) for { n := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } m := v_0.AuxInt if !(0 <= int16(m) && int16(m) < int16(n)) { break } v.reset(Op386FlagLT_ULT) return true } // match: (CMPWconst l:(ANDL x y) [0]) // cond: l.Uses==1 // result: (TESTW x y) for { if v.AuxInt != 0 { break } l := v.Args[0] if l.Op != Op386ANDL { break } _ = l.Args[1] x := l.Args[0] y := l.Args[1] if !(l.Uses == 1) { break } v.reset(Op386TESTW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWconst l:(ANDLconst [c] x) [0]) // cond: l.Uses==1 // result: (TESTWconst [int64(int16(c))] x) for { if v.AuxInt != 0 { break } l := v.Args[0] if l.Op != Op386ANDLconst { break } c := l.AuxInt x := l.Args[0] if !(l.Uses == 1) { break } v.reset(Op386TESTWconst) v.AuxInt = int64(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // cond: // result: (TESTW x x) for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(Op386TESTW) v.AddArg(x) v.AddArg(x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(c,off)] ptr mem) for { c := v.AuxInt l := v.Args[0] if l.Op != Op386MOVWload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(v.Pos, Op386CMPWconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(c, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386CMPWload_0(v *Value) bool { // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // cond: validValAndOff(int64(int16(c)),off) // result: (CMPWconstload {sym} [makeValAndOff(int64(int16(c)),off)] ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt mem := v.Args[2] if !(validValAndOff(int64(int16(c)), off)) { break } v.reset(Op386CMPWconstload) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386DIVSD_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSDload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386DIVSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386DIVSDload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (DIVSDload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386DIVSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386DIVSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386DIVSS_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSSload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386DIVSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386DIVSSload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (DIVSSload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386DIVSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386DIVSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386LEAL_0(v *Value) bool { // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(c+d) // result: (LEAL [c+d] {s} x) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(Op386LEAL) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL [off1] {sym1} (LEAL [off2] {sym2} x)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAL [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386LEAL) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) return true } // match: (LEAL [off1] {sym1} (LEAL1 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386LEAL1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAL [off1] {sym1} (LEAL2 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != Op386LEAL2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386LEAL2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAL [off1] {sym1} (LEAL4 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386LEAL4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAL [off1] {sym1} (LEAL8 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != Op386LEAL8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386LEAL8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386LEAL1_0(v *Value) bool { // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] y := v.Args[1] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} y (ADDLconst [d] x)) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt x := v_1.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // cond: // result: (LEAL2 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(Op386LEAL2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} (SHLLconst [1] y) x) // cond: // result: (LEAL2 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 1 { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386LEAL2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // cond: // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(Op386LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} (SHLLconst [2] y) x) // cond: // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 2 { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // cond: // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 3 { break } y := v_1.Args[0] v.reset(Op386LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} (SHLLconst [3] y) x) // cond: // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 3 { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [off1] {sym1} (LEAL [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] y := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [off1] {sym1} y (LEAL [off2] {sym2} x)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux x := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386LEAL2_0(v *Value) bool { // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] y := v.Args[1] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(Op386LEAL2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+2*d) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+2*d) && y.Op != OpSB) { break } v.reset(Op386LEAL2) v.AuxInt = c + 2*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // cond: // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(Op386LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // cond: // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(Op386LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [off1] {sym1} (LEAL [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] y := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(Op386LEAL2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386LEAL4_0(v *Value) bool { // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] y := v.Args[1] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(Op386LEAL4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+4*d) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+4*d) && y.Op != OpSB) { break } v.reset(Op386LEAL4) v.AuxInt = c + 4*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // cond: // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(Op386LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [off1] {sym1} (LEAL [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] y := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(Op386LEAL4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386LEAL8_0(v *Value) bool { // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] y := v.Args[1] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(Op386LEAL8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+8*d) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+8*d) && y.Op != OpSB) { break } v.reset(Op386LEAL8) v.AuxInt = c + 8*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL8 [off1] {sym1} (LEAL [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] y := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(Op386LEAL8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386MOVBLSX_0(v *Value) bool { b := v.Block _ = b // match: (MOVBLSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBLSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != Op386MOVBload { break } off := x.AuxInt sym := x.Aux _ = x.Args[1] ptr := x.Args[0] mem := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVBLSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBLSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(Op386ANDLconst) v.AuxInt = c & 0x7f v.AddArg(x) return true } return false } func rewriteValue386_Op386MOVBLSXload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVBLSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBLSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVBstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(Op386MOVBLSX) v.AddArg(x) return true } // match: (MOVBLSXload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVBLSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVBLSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBLZX_0(v *Value) bool { b := v.Block _ = b // match: (MOVBLZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != Op386MOVBload { break } off := x.AuxInt sym := x.Aux _ = x.Args[1] ptr := x.Args[0] mem := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBLZX x:(MOVBloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != Op386MOVBloadidx1 { break } off := x.AuxInt sym := x.Aux _ = x.Args[2] ptr := x.Args[0] idx := x.Args[1] mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVBloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVBLZX (ANDLconst [c] x)) // cond: // result: (ANDLconst [c & 0xff] x) for { v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ANDLconst) v.AuxInt = c & 0xff v.AddArg(x) return true } return false } func rewriteValue386_Op386MOVBload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBLZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVBstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(Op386MOVBLZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVBloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (ADDL ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVBloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVBloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(read8(sym, off))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB { break } if !(symIsRO(sym)) { break } v.reset(Op386MOVLconst) v.AuxInt = int64(read8(sym, off)) return true } return false } func rewriteValue386_Op386MOVBloadidx1_0(v *Value) bool { // match: (MOVBloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVBloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [c] {sym} idx (ADDLconst [d] ptr) mem) // cond: // result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt ptr := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVBloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVBloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [c] {sym} (ADDLconst [d] idx) ptr mem) // cond: // result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] mem := v.Args[2] v.reset(Op386MOVBloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBstore_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVBstore [off] {sym} ptr (MOVBLSX x) mem) // cond: // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVBLSX { break } x := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBLZX x) mem) // cond: // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVBLZX { break } x := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt mem := v.Args[2] if !(validOff(off)) { break } v.reset(Op386MOVBstoreconst) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVBstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} (ADDL ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVBstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVBstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } if v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != Op386MOVBstore { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } if w != x.Args[1] { break } mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != Op386MOVBstore { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-8 { break } if w != w0.Args[0] { break } mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBstoreconst_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVBstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(Op386MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconst [x] {sym} (ADDL ptr idx) mem) // cond: // result: (MOVBstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] v.reset(Op386MOVBstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != Op386MOVBstoreconst { break } a := x.AuxInt if x.Aux != s { break } _ = x.Args[1] if p != x.Args[0] { break } mem := x.Args[1] if !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(Op386MOVWstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBstoreconstidx1_0(v *Value) bool { // match: (MOVBstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem) // cond: // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem) // cond: // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } c := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconstidx1 [c] {s} p i x:(MOVBstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p i mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != Op386MOVBstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } if i != x.Args[1] { break } mem := x.Args[2] if !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(Op386MOVWstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(i) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBstoreidx1_0(v *Value) bool { // match: (MOVBstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVBstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [c] {sym} idx (ADDLconst [d] ptr) val mem) // cond: // result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt ptr := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVBstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVBstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [c] {sym} (ADDLconst [d] idx) ptr val mem) // cond: // result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVBstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-8 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} idx p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-8 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBstoreidx1_10(v *Value) bool { // match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-8 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} idx p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-8 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVLloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off] {sym} (ADDL ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVLloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVLloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(int32(read32(sym, off, config.BigEndian)))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB { break } if !(symIsRO(sym)) { break } v.reset(Op386MOVLconst) v.AuxInt = int64(int32(read32(sym, off, config.BigEndian))) return true } return false } func rewriteValue386_Op386MOVLloadidx1_0(v *Value) bool { // match: (MOVLloadidx1 [c] {sym} ptr (SHLLconst [2] idx) mem) // cond: // result: (MOVLloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 2 { break } idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (SHLLconst [2] idx) ptr mem) // cond: // result: (MOVLloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 2 { break } idx := v_0.Args[0] ptr := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} idx (ADDLconst [d] ptr) mem) // cond: // result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt ptr := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (ADDLconst [d] idx) ptr mem) // cond: // result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLloadidx4_0(v *Value) bool { // match: (MOVLloadidx4 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVLloadidx4 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLloadidx4) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx4 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVLloadidx4 [int64(int32(c+4*d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLloadidx4) v.AuxInt = int64(int32(c + 4*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstore_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVLstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt mem := v.Args[2] if !(validOff(off)) { break } v.reset(Op386MOVLstoreconst) v.AuxInt = makeValAndOff(int64(int32(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVLstoreidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} (ADDL ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVLstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ADDLload { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] { break } mem := y.Args[2] if mem != v.Args[2] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ANDLload { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] { break } mem := y.Args[2] if mem != v.Args[2] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ORLload { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] { break } mem := y.Args[2] if mem != v.Args[2] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386XORLload { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] { break } mem := y.Args[2] if mem != v.Args[2] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstore_10(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ADDL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] x := y.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ADDL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386SUBL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] x := y.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386SUBLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ANDL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] x := y.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ANDL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ORL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] x := y.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ORL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386XORL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] x := y.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386XORL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (ADDLconstmodify [makeValAndOff(c,off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ADDLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386ADDLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstore_20(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(ANDLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (ANDLconstmodify [makeValAndOff(c,off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ANDLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386ANDLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (ORLconstmodify [makeValAndOff(c,off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ORLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386ORLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (XORLconstmodify [makeValAndOff(c,off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386XORLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386XORLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstoreconst_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVLstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(Op386MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym1} (LEAL4 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } off := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym} (ADDL ptr idx) mem) // cond: // result: (MOVLstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] v.reset(Op386MOVLstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstoreconstidx1_0(v *Value) bool { // match: (MOVLstoreconstidx1 [c] {sym} ptr (SHLLconst [2] idx) mem) // cond: // result: (MOVLstoreconstidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 2 { break } idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLstoreconstidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem) // cond: // result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem) // cond: // result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } c := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstoreconstidx4_0(v *Value) bool { // match: (MOVLstoreconstidx4 [x] {sym} (ADDLconst [c] ptr) idx mem) // cond: // result: (MOVLstoreconstidx4 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx4 [x] {sym} ptr (ADDLconst [c] idx) mem) // cond: // result: (MOVLstoreconstidx4 [ValAndOff(x).add(4*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } c := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(4 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstoreidx1_0(v *Value) bool { // match: (MOVLstoreidx1 [c] {sym} ptr (SHLLconst [2] idx) val mem) // cond: // result: (MOVLstoreidx4 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 2 { break } idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} (SHLLconst [2] idx) ptr val mem) // cond: // result: (MOVLstoreidx4 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 2 { break } idx := v_0.Args[0] ptr := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} idx (ADDLconst [d] ptr) val mem) // cond: // result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt ptr := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} (ADDLconst [d] idx) ptr val mem) // cond: // result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstoreidx4_0(v *Value) bool { // match: (MOVLstoreidx4 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVLstoreidx4 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx4) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVLstoreidx4 [int64(int32(c+4*d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx4) v.AuxInt = int64(int32(c + 4*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDLloadidx4 x [off] {sym} ptr idx mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ADDLloadidx4 { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[3] x := y.Args[0] if ptr != y.Args[1] { break } if idx != y.Args[2] { break } mem := y.Args[3] if mem != v.Args[3] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386ADDLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDLloadidx4 x [off] {sym} ptr idx mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ANDLloadidx4 { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[3] x := y.Args[0] if ptr != y.Args[1] { break } if idx != y.Args[2] { break } mem := y.Args[3] if mem != v.Args[3] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386ANDLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORLloadidx4 x [off] {sym} ptr idx mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ORLloadidx4 { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[3] x := y.Args[0] if ptr != y.Args[1] { break } if idx != y.Args[2] { break } mem := y.Args[3] if mem != v.Args[3] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386ORLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORLloadidx4 x [off] {sym} ptr idx mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386XORLloadidx4 { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[3] x := y.Args[0] if ptr != y.Args[1] { break } if idx != y.Args[2] { break } mem := y.Args[3] if mem != v.Args[3] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386XORLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ADDL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] x := y.Args[1] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ADDLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ADDL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ADDLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(SUBL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386SUBL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] x := y.Args[1] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386SUBLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ANDL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] x := y.Args[1] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ANDLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstoreidx4_10(v *Value) bool { // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ANDL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ANDLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ORL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] x := y.Args[1] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ORLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ORL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ORLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386XORL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] x := y.Args[1] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386XORLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386XORL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386XORLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (ADDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ADDLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386ADDLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (ANDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ANDLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386ANDLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (ORLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ORLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386ORLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (XORLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386XORLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386XORLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSDconst_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config typ := &b.Func.Config.Types _ = typ // match: (MOVSDconst [c]) // cond: config.ctxt.Flag_shared // result: (MOVSDconst2 (MOVSDconst1 [c])) for { c := v.AuxInt if !(config.ctxt.Flag_shared) { break } v.reset(Op386MOVSDconst2) v0 := b.NewValue0(v.Pos, Op386MOVSDconst1, typ.UInt32) v0.AuxInt = c v.AddArg(v0) return true } return false } func rewriteValue386_Op386MOVSDload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVSDload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSDloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAL8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSDloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off] {sym} (ADDL ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVSDloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVSDloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSDloadidx1_0(v *Value) bool { // match: (MOVSDloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVSDloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVSDloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVSDloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVSDloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSDloadidx8_0(v *Value) bool { // match: (MOVSDloadidx8 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVSDloadidx8 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVSDloadidx8) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx8 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVSDloadidx8 [int64(int32(c+8*d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVSDloadidx8) v.AuxInt = int64(int32(c + 8*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSDstore_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVSDstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVSDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVSDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSDstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAL8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSDstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off] {sym} (ADDL ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVSDstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVSDstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSDstoreidx1_0(v *Value) bool { // match: (MOVSDstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVSDstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSDstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVSDstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSDstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSDstoreidx8_0(v *Value) bool { // match: (MOVSDstoreidx8 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVSDstoreidx8 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSDstoreidx8) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx8 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVSDstoreidx8 [int64(int32(c+8*d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSDstoreidx8) v.AuxInt = int64(int32(c + 8*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSSconst_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config typ := &b.Func.Config.Types _ = typ // match: (MOVSSconst [c]) // cond: config.ctxt.Flag_shared // result: (MOVSSconst2 (MOVSSconst1 [c])) for { c := v.AuxInt if !(config.ctxt.Flag_shared) { break } v.reset(Op386MOVSSconst2) v0 := b.NewValue0(v.Pos, Op386MOVSSconst1, typ.UInt32) v0.AuxInt = c v.AddArg(v0) return true } return false } func rewriteValue386_Op386MOVSSload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVSSload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSSloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSSloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off] {sym} (ADDL ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVSSloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVSSloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSSloadidx1_0(v *Value) bool { // match: (MOVSSloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVSSloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVSSloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVSSloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVSSloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSSloadidx4_0(v *Value) bool { // match: (MOVSSloadidx4 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVSSloadidx4 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVSSloadidx4) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx4 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVSSloadidx4 [int64(int32(c+4*d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVSSloadidx4) v.AuxInt = int64(int32(c + 4*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSSstore_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVSSstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVSSstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVSSstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSSstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSSstoreidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off] {sym} (ADDL ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVSSstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVSSstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSSstoreidx1_0(v *Value) bool { // match: (MOVSSstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVSSstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSSstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVSSstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSSstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSSstoreidx4_0(v *Value) bool { // match: (MOVSSstoreidx4 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVSSstoreidx4 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSSstoreidx4) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx4 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVSSstoreidx4 [int64(int32(c+4*d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSSstoreidx4) v.AuxInt = int64(int32(c + 4*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWLSX_0(v *Value) bool { b := v.Block _ = b // match: (MOVWLSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWLSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != Op386MOVWload { break } off := x.AuxInt sym := x.Aux _ = x.Args[1] ptr := x.Args[0] mem := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVWLSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWLSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(Op386ANDLconst) v.AuxInt = c & 0x7fff v.AddArg(x) return true } return false } func rewriteValue386_Op386MOVWLSXload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVWLSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWLSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVWstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(Op386MOVWLSX) v.AddArg(x) return true } // match: (MOVWLSXload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVWLSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVWLSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWLZX_0(v *Value) bool { b := v.Block _ = b // match: (MOVWLZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != Op386MOVWload { break } off := x.AuxInt sym := x.Aux _ = x.Args[1] ptr := x.Args[0] mem := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWLZX x:(MOVWloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != Op386MOVWloadidx1 { break } off := x.AuxInt sym := x.Aux _ = x.Args[2] ptr := x.Args[0] idx := x.Args[1] mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVWLZX x:(MOVWloadidx2 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWloadidx2 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != Op386MOVWloadidx2 { break } off := x.AuxInt sym := x.Aux _ = x.Args[2] ptr := x.Args[0] idx := x.Args[1] mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVWloadidx2, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVWLZX (ANDLconst [c] x)) // cond: // result: (ANDLconst [c & 0xffff] x) for { v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ANDLconst) v.AuxInt = c & 0xffff v.AddArg(x) return true } return false } func rewriteValue386_Op386MOVWload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWLZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVWstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(Op386MOVWLZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVWloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAL2 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWloadidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVWloadidx2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (ADDL ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVWloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVWloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(read16(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB { break } if !(symIsRO(sym)) { break } v.reset(Op386MOVLconst) v.AuxInt = int64(read16(sym, off, config.BigEndian)) return true } return false } func rewriteValue386_Op386MOVWloadidx1_0(v *Value) bool { // match: (MOVWloadidx1 [c] {sym} ptr (SHLLconst [1] idx) mem) // cond: // result: (MOVWloadidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWloadidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} (SHLLconst [1] idx) ptr mem) // cond: // result: (MOVWloadidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 1 { break } idx := v_0.Args[0] ptr := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWloadidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} idx (ADDLconst [d] ptr) mem) // cond: // result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt ptr := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} (ADDLconst [d] idx) ptr mem) // cond: // result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWloadidx2_0(v *Value) bool { // match: (MOVWloadidx2 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVWloadidx2 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWloadidx2) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx2 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVWloadidx2 [int64(int32(c+2*d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWloadidx2) v.AuxInt = int64(int32(c + 2*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstore_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVWstore [off] {sym} ptr (MOVWLSX x) mem) // cond: // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVWLSX { break } x := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWLZX x) mem) // cond: // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVWLZX { break } x := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt mem := v.Args[2] if !(validOff(off)) { break } v.reset(Op386MOVWstoreconst) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAL2 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstoreidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVWstoreidx2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} (ADDL ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVWstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } if v_1.AuxInt != 16 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != Op386MOVWstore { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } if w != x.Args[1] { break } mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != Op386MOVWstore { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-16 { break } if w != w0.Args[0] { break } mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstoreconst_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVWstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(Op386MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym1} (LEAL2 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL2 { break } off := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym} (ADDL ptr idx) mem) // cond: // result: (MOVWstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] v.reset(Op386MOVWstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != Op386MOVWstoreconst { break } a := x.AuxInt if x.Aux != s { break } _ = x.Args[1] if p != x.Args[0] { break } mem := x.Args[1] if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(Op386MOVLstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstoreconstidx1_0(v *Value) bool { // match: (MOVWstoreconstidx1 [c] {sym} ptr (SHLLconst [1] idx) mem) // cond: // result: (MOVWstoreconstidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWstoreconstidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem) // cond: // result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem) // cond: // result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } c := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [c] {s} p i x:(MOVWstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p i mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != Op386MOVWstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } if i != x.Args[1] { break } mem := x.Args[2] if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(Op386MOVLstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(i) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstoreconstidx2_0(v *Value) bool { b := v.Block _ = b // match: (MOVWstoreconstidx2 [x] {sym} (ADDLconst [c] ptr) idx mem) // cond: // result: (MOVWstoreconstidx2 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx2 [x] {sym} ptr (ADDLconst [c] idx) mem) // cond: // result: (MOVWstoreconstidx2 [ValAndOff(x).add(2*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } c := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(2 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx2 [c] {s} p i x:(MOVWstoreconstidx2 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p (SHLLconst [1] i) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != Op386MOVWstoreconstidx2 { break } a := x.AuxInt if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } if i != x.Args[1] { break } mem := x.Args[2] if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(Op386MOVLstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, Op386SHLLconst, i.Type) v0.AuxInt = 1 v0.AddArg(i) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstoreidx1_0(v *Value) bool { // match: (MOVWstoreidx1 [c] {sym} ptr (SHLLconst [1] idx) val mem) // cond: // result: (MOVWstoreidx2 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} (SHLLconst [1] idx) ptr val mem) // cond: // result: (MOVWstoreidx2 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 1 { break } idx := v_0.Args[0] ptr := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} idx (ADDLconst [d] ptr) val mem) // cond: // result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt ptr := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} (ADDLconst [d] idx) ptr val mem) // cond: // result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} idx p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} idx p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstoreidx1_10(v *Value) bool { // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-16 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} idx p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-16 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-16 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} idx p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-16 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstoreidx2_0(v *Value) bool { b := v.Block _ = b // match: (MOVWstoreidx2 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVWstoreidx2 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx2) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVWstoreidx2 [int64(int32(c+2*d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx2) v.AuxInt = int64(int32(c + 2*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLLconst [1] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx2 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, Op386SHLLconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx2 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLLconst [1] idx) w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx2 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-16 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, Op386SHLLconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULL_0(v *Value) bool { // match: (MULL x (MOVLconst [c])) // cond: // result: (MULLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386MULLconst) v.AuxInt = c v.AddArg(x) return true } // match: (MULL (MOVLconst [c]) x) // cond: // result: (MULLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386MULLconst) v.AuxInt = c v.AddArg(x) return true } // match: (MULL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (MULLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386MULLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MULL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (MULLload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386MULLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MULL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (MULLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386MULLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MULL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (MULLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386MULLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULLconst_0(v *Value) bool { b := v.Block _ = b // match: (MULLconst [c] (MULLconst [d] x)) // cond: // result: (MULLconst [int64(int32(c * d))] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MULLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386MULLconst) v.AuxInt = int64(int32(c * d)) v.AddArg(x) return true } // match: (MULLconst [-9] x) // cond: // result: (NEGL (LEAL8 x x)) for { if v.AuxInt != -9 { break } x := v.Args[0] v.reset(Op386NEGL) v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // cond: // result: (NEGL (LEAL4 x x)) for { if v.AuxInt != -5 { break } x := v.Args[0] v.reset(Op386NEGL) v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // cond: // result: (NEGL (LEAL2 x x)) for { if v.AuxInt != -3 { break } x := v.Args[0] v.reset(Op386NEGL) v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // cond: // result: (NEGL x) for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(Op386NEGL) v.AddArg(x) return true } // match: (MULLconst [0] _) // cond: // result: (MOVLconst [0]) for { if v.AuxInt != 0 { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (MULLconst [1] x) // cond: // result: x for { if v.AuxInt != 1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MULLconst [3] x) // cond: // result: (LEAL2 x x) for { if v.AuxInt != 3 { break } x := v.Args[0] v.reset(Op386LEAL2) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [5] x) // cond: // result: (LEAL4 x x) for { if v.AuxInt != 5 { break } x := v.Args[0] v.reset(Op386LEAL4) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [7] x) // cond: // result: (LEAL2 x (LEAL2 x x)) for { if v.AuxInt != 7 { break } x := v.Args[0] v.reset(Op386LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValue386_Op386MULLconst_10(v *Value) bool { b := v.Block _ = b // match: (MULLconst [9] x) // cond: // result: (LEAL8 x x) for { if v.AuxInt != 9 { break } x := v.Args[0] v.reset(Op386LEAL8) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [11] x) // cond: // result: (LEAL2 x (LEAL4 x x)) for { if v.AuxInt != 11 { break } x := v.Args[0] v.reset(Op386LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [13] x) // cond: // result: (LEAL4 x (LEAL2 x x)) for { if v.AuxInt != 13 { break } x := v.Args[0] v.reset(Op386LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [19] x) // cond: // result: (LEAL2 x (LEAL8 x x)) for { if v.AuxInt != 19 { break } x := v.Args[0] v.reset(Op386LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [21] x) // cond: // result: (LEAL4 x (LEAL4 x x)) for { if v.AuxInt != 21 { break } x := v.Args[0] v.reset(Op386LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [25] x) // cond: // result: (LEAL8 x (LEAL2 x x)) for { if v.AuxInt != 25 { break } x := v.Args[0] v.reset(Op386LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [27] x) // cond: // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if v.AuxInt != 27 { break } x := v.Args[0] v.reset(Op386LEAL8) v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULLconst [37] x) // cond: // result: (LEAL4 x (LEAL8 x x)) for { if v.AuxInt != 37 { break } x := v.Args[0] v.reset(Op386LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [41] x) // cond: // result: (LEAL8 x (LEAL4 x x)) for { if v.AuxInt != 41 { break } x := v.Args[0] v.reset(Op386LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [45] x) // cond: // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if v.AuxInt != 45 { break } x := v.Args[0] v.reset(Op386LEAL8) v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } return false } func rewriteValue386_Op386MULLconst_20(v *Value) bool { b := v.Block _ = b // match: (MULLconst [73] x) // cond: // result: (LEAL8 x (LEAL8 x x)) for { if v.AuxInt != 73 { break } x := v.Args[0] v.reset(Op386LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [81] x) // cond: // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if v.AuxInt != 81 { break } x := v.Args[0] v.reset(Op386LEAL8) v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c+1) && c >= 15 // result: (SUBL (SHLLconst [log2(c+1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c+1) && c >= 15) { break } v.reset(Op386SUBL) v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type) v0.AuxInt = log2(c + 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [log2(c-1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-1) && c >= 17) { break } v.reset(Op386LEAL1) v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type) v0.AuxInt = log2(c - 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [log2(c-2)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-2) && c >= 34) { break } v.reset(Op386LEAL2) v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type) v0.AuxInt = log2(c - 2) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [log2(c-4)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-4) && c >= 68) { break } v.reset(Op386LEAL4) v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type) v0.AuxInt = log2(c - 4) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [log2(c-8)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-8) && c >= 136) { break } v.reset(Op386LEAL8) v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type) v0.AuxInt = log2(c - 8) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo(c/3) // result: (SHLLconst [log2(c/3)] (LEAL2 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%3 == 0 && isPowerOfTwo(c/3)) { break } v.reset(Op386SHLLconst) v.AuxInt = log2(c / 3) v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo(c/5) // result: (SHLLconst [log2(c/5)] (LEAL4 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%5 == 0 && isPowerOfTwo(c/5)) { break } v.reset(Op386SHLLconst) v.AuxInt = log2(c / 5) v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo(c/9) // result: (SHLLconst [log2(c/9)] (LEAL8 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%9 == 0 && isPowerOfTwo(c/9)) { break } v.reset(Op386SHLLconst) v.AuxInt = log2(c / 9) v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValue386_Op386MULLconst_30(v *Value) bool { // match: (MULLconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [int64(int32(c*d))]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = int64(int32(c * d)) return true } return false } func rewriteValue386_Op386MULLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MULLload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MULLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MULLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MULLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MULLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL4 { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[1] ptr := v_1.Args[0] idx := v_1.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MULLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULLloadidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MULLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem) // cond: is32Bit(off1+off2) // result: (MULLloadidx4 [off1+off2] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MULLloadidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (MULLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem) // cond: is32Bit(off1+off2*4) // result: (MULLloadidx4 [off1+off2*4] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] base := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386ADDLconst { break } off2 := v_2.AuxInt idx := v_2.Args[0] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386MULLloadidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (MULLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MULLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MULLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULSD_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSDload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386MULSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MULSD l:(MOVSDload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVSDload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386MULSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULSDload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MULSDload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MULSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MULSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULSS_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSSload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386MULSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MULSS l:(MOVSSload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVSSload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386MULSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULSSload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MULSSload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MULSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MULSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386NEGL_0(v *Value) bool { // match: (NEGL (MOVLconst [c])) // cond: // result: (MOVLconst [int64(int32(-c))]) for { v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = int64(int32(-c)) return true } return false } func rewriteValue386_Op386NOTL_0(v *Value) bool { // match: (NOTL (MOVLconst [c])) // cond: // result: (MOVLconst [^c]) for { v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = ^c return true } return false } func rewriteValue386_Op386ORL_0(v *Value) bool { // match: (ORL x (MOVLconst [c])) // cond: // result: (ORLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386ORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (MOVLconst [c]) x) // cond: // result: (ORLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386ORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHLLconst [c] x) (SHRLconst [d] x)) // cond: d == 32-c // result: (ROLLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(Op386ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHRLconst [d] x) (SHLLconst [c] x)) // cond: d == 32-c // result: (ROLLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(Op386ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: c < 16 && d == 16-c && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 16 && d == 16-c && t.Size() == 2) { break } v.reset(Op386ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHRWconst x [d]) (SHLLconst x [c])) // cond: c < 16 && d == 16-c && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 16 && d == 16-c && t.Size() == 2) { break } v.reset(Op386ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: c < 8 && d == 8-c && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRBconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 8 && d == 8-c && t.Size() == 1) { break } v.reset(Op386ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHRBconst x [d]) (SHLLconst x [c])) // cond: c < 8 && d == 8-c && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRBconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 8 && d == 8-c && t.Size() == 1) { break } v.reset(Op386ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ORL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ORL_10(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (ORL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ORLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ORLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (ORL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ORLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ORLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (ORL x x) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] if x != v.Args[1] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ORL x0:(MOVBload [i0] {s} p mem) s0:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != Op386MOVBload { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[1] p := x0.Args[0] mem := x0.Args[1] s0 := v.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL s0:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem)) x0:(MOVBload [i0] {s} p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBload { break } i1 := x1.AuxInt s := x1.Aux _ = x1.Args[1] p := x1.Args[0] mem := x1.Args[1] x0 := v.Args[1] if x0.Op != Op386MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWload [i0] {s} p mem) s0:(SHLLconst [16] x1:(MOVBload [i2] {s} p mem))) s1:(SHLLconst [24] x2:(MOVBload [i3] {s} p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWload { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[1] p := x0.Args[0] mem := x0.Args[1] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBload { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBload [i2] {s} p mem)) x0:(MOVWload [i0] {s} p mem)) s1:(SHLLconst [24] x2:(MOVBload [i3] {s} p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBload { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[1] p := x1.Args[0] mem := x1.Args[1] x0 := o0.Args[1] if x0.Op != Op386MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBload { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBload [i3] {s} p mem)) o0:(ORL x0:(MOVWload [i0] {s} p mem) s0:(SHLLconst [16] x1:(MOVBload [i2] {s} p mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBload { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[1] p := x2.Args[0] mem := x2.Args[1] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBload [i3] {s} p mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBload [i2] {s} p mem)) x0:(MOVWload [i0] {s} p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBload { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[1] p := x2.Args[0] mem := x2.Args[1] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] p := x0.Args[0] idx := x0.Args[1] mem := x0.Args[2] s0 := v.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386ORL_20(v *Value) bool { b := v.Block _ = b // match: (ORL x0:(MOVBloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] idx := x0.Args[0] p := x0.Args[1] mem := x0.Args[2] s0 := v.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] p := x0.Args[0] idx := x0.Args[1] mem := x0.Args[2] s0 := v.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] idx := x0.Args[0] p := x0.Args[1] mem := x0.Args[2] s0 := v.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux _ = x1.Args[2] p := x1.Args[0] idx := x1.Args[1] mem := x1.Args[2] x0 := v.Args[1] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux _ = x1.Args[2] idx := x1.Args[0] p := x1.Args[1] mem := x1.Args[2] x0 := v.Args[1] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux _ = x1.Args[2] p := x1.Args[0] idx := x1.Args[1] mem := x1.Args[2] x0 := v.Args[1] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux _ = x1.Args[2] idx := x1.Args[0] p := x1.Args[1] mem := x1.Args[2] x0 := v.Args[1] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] p := x0.Args[0] idx := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] idx := x0.Args[0] p := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] p := x0.Args[0] idx := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386ORL_30(v *Value) bool { b := v.Block _ = b // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] idx := x0.Args[0] p := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] p := x1.Args[0] idx := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] idx := x1.Args[0] p := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] p := x1.Args[0] idx := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] idx := x1.Args[0] p := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] p := x0.Args[0] idx := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] idx := x0.Args[0] p := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] p := x0.Args[0] idx := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] idx := x0.Args[0] p := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] p := x1.Args[0] idx := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386ORL_40(v *Value) bool { b := v.Block _ = b // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] idx := x1.Args[0] p := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] p := x1.Args[0] idx := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] idx := x1.Args[0] p := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386ORL_50(v *Value) bool { b := v.Block _ = b // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386ORLconst_0(v *Value) bool { // match: (ORLconst [c] x) // cond: int32(c)==0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ORLconst [c] _) // cond: int32(c)==-1 // result: (MOVLconst [-1]) for { c := v.AuxInt if !(int32(c) == -1) { break } v.reset(Op386MOVLconst) v.AuxInt = -1 return true } // match: (ORLconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [c|d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = c | d return true } return false } func rewriteValue386_Op386ORLconstmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ORLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ORLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386ORLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ORLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ORLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ORLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ORLconstmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ORLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ORLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386ORLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ORLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem) // cond: ValAndOff(valoff1).canAdd(off2*4) // result: (ORLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2 * 4)) { break } v.reset(Op386ORLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2 * 4) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ORLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ORLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ORLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ORLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ORLload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ORLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ORLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ORLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ORLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ORLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ORLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL4 { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[1] ptr := v_1.Args[0] idx := v_1.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386ORLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ORLloadidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ORLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem) // cond: is32Bit(off1+off2) // result: (ORLloadidx4 [off1+off2] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ORLloadidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ORLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem) // cond: is32Bit(off1+off2*4) // result: (ORLloadidx4 [off1+off2*4] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] base := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386ADDLconst { break } off2 := v_2.AuxInt idx := v_2.Args[0] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386ORLloadidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ORLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ORLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ORLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ORLmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ORLmodify [off1] {sym} (ADDLconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ORLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ORLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ORLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ORLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ORLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ORLmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ORLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem) // cond: is32Bit(off1+off2) // result: (ORLmodifyidx4 [off1+off2] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ORLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ORLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem) // cond: is32Bit(off1+off2*4) // result: (ORLmodifyidx4 [off1+off2*4] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386ORLmodifyidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ORLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ORLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ORLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ORLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem) // cond: validValAndOff(c,off) // result: (ORLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386MOVLconst { break } c := v_2.AuxInt mem := v.Args[3] if !(validValAndOff(c, off)) { break } v.reset(Op386ORLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ROLBconst_0(v *Value) bool { // match: (ROLBconst [c] (ROLBconst [d] x)) // cond: // result: (ROLBconst [(c+d)& 7] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ROLBconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ROLBconst) v.AuxInt = (c + d) & 7 v.AddArg(x) return true } // match: (ROLBconst [0] x) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386ROLLconst_0(v *Value) bool { // match: (ROLLconst [c] (ROLLconst [d] x)) // cond: // result: (ROLLconst [(c+d)&31] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ROLLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ROLLconst) v.AuxInt = (c + d) & 31 v.AddArg(x) return true } // match: (ROLLconst [0] x) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386ROLWconst_0(v *Value) bool { // match: (ROLWconst [c] (ROLWconst [d] x)) // cond: // result: (ROLWconst [(c+d)&15] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ROLWconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ROLWconst) v.AuxInt = (c + d) & 15 v.AddArg(x) return true } // match: (ROLWconst [0] x) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386SARB_0(v *Value) bool { // match: (SARB x (MOVLconst [c])) // cond: // result: (SARBconst [min(c&31,7)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SARBconst) v.AuxInt = min(c&31, 7) v.AddArg(x) return true } return false } func rewriteValue386_Op386SARBconst_0(v *Value) bool { // match: (SARBconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARBconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [d>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = d >> uint64(c) return true } return false } func rewriteValue386_Op386SARL_0(v *Value) bool { // match: (SARL x (MOVLconst [c])) // cond: // result: (SARLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SARLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SARL x (ANDLconst [31] y)) // cond: // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ANDLconst { break } if v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(Op386SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386SARLconst_0(v *Value) bool { // match: (SARLconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARLconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [d>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = d >> uint64(c) return true } return false } func rewriteValue386_Op386SARW_0(v *Value) bool { // match: (SARW x (MOVLconst [c])) // cond: // result: (SARWconst [min(c&31,15)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SARWconst) v.AuxInt = min(c&31, 15) v.AddArg(x) return true } return false } func rewriteValue386_Op386SARWconst_0(v *Value) bool { // match: (SARWconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARWconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [d>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = d >> uint64(c) return true } return false } func rewriteValue386_Op386SBBL_0(v *Value) bool { // match: (SBBL x (MOVLconst [c]) f) // cond: // result: (SBBLconst [c] x f) for { _ = v.Args[2] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt f := v.Args[2] v.reset(Op386SBBLconst) v.AuxInt = c v.AddArg(x) v.AddArg(f) return true } return false } func rewriteValue386_Op386SBBLcarrymask_0(v *Value) bool { // match: (SBBLcarrymask (FlagEQ)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SBBLcarrymask (FlagLT_ULT)) // cond: // result: (MOVLconst [-1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = -1 return true } // match: (SBBLcarrymask (FlagLT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SBBLcarrymask (FlagGT_ULT)) // cond: // result: (MOVLconst [-1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = -1 return true } // match: (SBBLcarrymask (FlagGT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SETA_0(v *Value) bool { // match: (SETA (InvertFlags x)) // cond: // result: (SETB x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagLT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagLT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETA (FlagGT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagGT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValue386_Op386SETAE_0(v *Value) bool { // match: (SETAE (InvertFlags x)) // cond: // result: (SETBE x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETAE (FlagLT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETAE (FlagLT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETAE (FlagGT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETAE (FlagGT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValue386_Op386SETB_0(v *Value) bool { // match: (SETB (InvertFlags x)) // cond: // result: (SETA x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETB (FlagLT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETB (FlagLT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETB (FlagGT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETB (FlagGT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SETBE_0(v *Value) bool { // match: (SETBE (InvertFlags x)) // cond: // result: (SETAE x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagLT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagLT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETBE (FlagGT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagGT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SETEQ_0(v *Value) bool { // match: (SETEQ (InvertFlags x)) // cond: // result: (SETEQ x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETEQ (FlagLT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagLT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagGT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagGT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SETG_0(v *Value) bool { // match: (SETG (InvertFlags x)) // cond: // result: (SETL x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagLT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagLT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagGT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETG (FlagGT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValue386_Op386SETGE_0(v *Value) bool { // match: (SETGE (InvertFlags x)) // cond: // result: (SETLE x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETGE (FlagLT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETGE (FlagLT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETGE (FlagGT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETGE (FlagGT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValue386_Op386SETL_0(v *Value) bool { // match: (SETL (InvertFlags x)) // cond: // result: (SETG x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETL (FlagLT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETL (FlagLT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETL (FlagGT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETL (FlagGT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SETLE_0(v *Value) bool { // match: (SETLE (InvertFlags x)) // cond: // result: (SETGE x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagLT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagLT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagGT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETLE (FlagGT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SETNE_0(v *Value) bool { // match: (SETNE (InvertFlags x)) // cond: // result: (SETNE x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETNE (FlagLT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagLT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagGT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagGT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValue386_Op386SHLL_0(v *Value) bool { // match: (SHLL x (MOVLconst [c])) // cond: // result: (SHLLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SHLLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHLL x (ANDLconst [31] y)) // cond: // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ANDLconst { break } if v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(Op386SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386SHLLconst_0(v *Value) bool { // match: (SHLLconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386SHRB_0(v *Value) bool { // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt if !(c&31 < 8) { break } v.reset(Op386SHRBconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt if !(c&31 >= 8) { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SHRBconst_0(v *Value) bool { // match: (SHRBconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386SHRL_0(v *Value) bool { // match: (SHRL x (MOVLconst [c])) // cond: // result: (SHRLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SHRLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRL x (ANDLconst [31] y)) // cond: // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ANDLconst { break } if v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(Op386SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386SHRLconst_0(v *Value) bool { // match: (SHRLconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386SHRW_0(v *Value) bool { // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt if !(c&31 < 16) { break } v.reset(Op386SHRWconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt if !(c&31 >= 16) { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SHRWconst_0(v *Value) bool { // match: (SHRWconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386SUBL_0(v *Value) bool { b := v.Block _ = b // match: (SUBL x (MOVLconst [c])) // cond: // result: (SUBLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SUBLconst) v.AuxInt = c v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // cond: // result: (NEGL (SUBLconst x [c])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386NEGL) v0 := b.NewValue0(v.Pos, Op386SUBLconst, v.Type) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386SUBLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (SUBL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (SUBLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386SUBLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (SUBL x x) // cond: // result: (MOVLconst [0]) for { _ = v.Args[1] x := v.Args[0] if x != v.Args[1] { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SUBLcarry_0(v *Value) bool { // match: (SUBLcarry x (MOVLconst [c])) // cond: // result: (SUBLconstcarry [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SUBLconstcarry) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValue386_Op386SUBLconst_0(v *Value) bool { // match: (SUBLconst [c] x) // cond: int32(c) == 0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SUBLconst [c] x) // cond: // result: (ADDLconst [int64(int32(-c))] x) for { c := v.AuxInt x := v.Args[0] v.reset(Op386ADDLconst) v.AuxInt = int64(int32(-c)) v.AddArg(x) return true } } func rewriteValue386_Op386SUBLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBLload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386SUBLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386SUBLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL4 { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[1] ptr := v_1.Args[0] idx := v_1.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386SUBLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBLloadidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem) // cond: is32Bit(off1+off2) // result: (SUBLloadidx4 [off1+off2] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386SUBLloadidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (SUBLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem) // cond: is32Bit(off1+off2*4) // result: (SUBLloadidx4 [off1+off2*4] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] base := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386ADDLconst { break } off2 := v_2.AuxInt idx := v_2.Args[0] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386SUBLloadidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (SUBLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (SUBLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386SUBLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBLmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBLmodify [off1] {sym} (ADDLconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386SUBLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386SUBLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBLmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem) // cond: is32Bit(off1+off2) // result: (SUBLmodifyidx4 [off1+off2] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386SUBLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem) // cond: is32Bit(off1+off2*4) // result: (SUBLmodifyidx4 [off1+off2*4] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386SUBLmodifyidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (SUBLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386SUBLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem) // cond: validValAndOff(-c,off) // result: (ADDLconstmodifyidx4 [makeValAndOff(-c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386MOVLconst { break } c := v_2.AuxInt mem := v.Args[3] if !(validValAndOff(-c, off)) { break } v.reset(Op386ADDLconstmodifyidx4) v.AuxInt = makeValAndOff(-c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBSD_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSDload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386SUBSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBSDload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBSDload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386SUBSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386SUBSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBSS_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSSload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386SUBSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBSSload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBSSload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386SUBSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386SUBSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORL_0(v *Value) bool { // match: (XORL x (MOVLconst [c])) // cond: // result: (XORLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386XORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (MOVLconst [c]) x) // cond: // result: (XORLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386XORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHLLconst [c] x) (SHRLconst [d] x)) // cond: d == 32-c // result: (ROLLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(Op386ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHRLconst [d] x) (SHLLconst [c] x)) // cond: d == 32-c // result: (ROLLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(Op386ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: c < 16 && d == 16-c && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 16 && d == 16-c && t.Size() == 2) { break } v.reset(Op386ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHRWconst x [d]) (SHLLconst x [c])) // cond: c < 16 && d == 16-c && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 16 && d == 16-c && t.Size() == 2) { break } v.reset(Op386ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: c < 8 && d == 8-c && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRBconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 8 && d == 8-c && t.Size() == 1) { break } v.reset(Op386ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHRBconst x [d]) (SHLLconst x [c])) // cond: c < 8 && d == 8-c && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRBconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 8 && d == 8-c && t.Size() == 1) { break } v.reset(Op386ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386XORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (XORL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386XORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORL_10(v *Value) bool { // match: (XORL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (XORLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386XORLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (XORL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (XORLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386XORLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (XORL x x) // cond: // result: (MOVLconst [0]) for { _ = v.Args[1] x := v.Args[0] if x != v.Args[1] { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386XORLconst_0(v *Value) bool { // match: (XORLconst [c] (XORLconst [d] x)) // cond: // result: (XORLconst [c ^ d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386XORLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386XORLconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORLconst [c] x) // cond: int32(c)==0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (XORLconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [c^d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = c ^ d return true } return false } func rewriteValue386_Op386XORLconstmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (XORLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (XORLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386XORLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (XORLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (XORLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386XORLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORLconstmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (XORLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (XORLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386XORLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (XORLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem) // cond: ValAndOff(valoff1).canAdd(off2*4) // result: (XORLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2 * 4)) { break } v.reset(Op386XORLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2 * 4) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (XORLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (XORLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386XORLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (XORLload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (XORLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386XORLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (XORLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (XORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386XORLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (XORLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (XORLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL4 { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[1] ptr := v_1.Args[0] idx := v_1.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386XORLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORLloadidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (XORLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem) // cond: is32Bit(off1+off2) // result: (XORLloadidx4 [off1+off2] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386XORLloadidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (XORLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem) // cond: is32Bit(off1+off2*4) // result: (XORLloadidx4 [off1+off2*4] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] base := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386ADDLconst { break } off2 := v_2.AuxInt idx := v_2.Args[0] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386XORLloadidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (XORLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (XORLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386XORLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORLmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (XORLmodify [off1] {sym} (ADDLconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (XORLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386XORLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (XORLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (XORLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386XORLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORLmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (XORLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem) // cond: is32Bit(off1+off2) // result: (XORLmodifyidx4 [off1+off2] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386XORLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (XORLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem) // cond: is32Bit(off1+off2*4) // result: (XORLmodifyidx4 [off1+off2*4] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386XORLmodifyidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (XORLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (XORLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386XORLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (XORLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem) // cond: validValAndOff(c,off) // result: (XORLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386MOVLconst { break } c := v_2.AuxInt mem := v.Args[3] if !(validValAndOff(c, off)) { break } v.reset(Op386XORLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_OpAdd16_0(v *Value) bool { // match: (Add16 x y) // cond: // result: (ADDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAdd32_0(v *Value) bool { // match: (Add32 x y) // cond: // result: (ADDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAdd32F_0(v *Value) bool { // match: (Add32F x y) // cond: // result: (ADDSS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAdd32carry_0(v *Value) bool { // match: (Add32carry x y) // cond: // result: (ADDLcarry x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDLcarry) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAdd32withcarry_0(v *Value) bool { // match: (Add32withcarry x y c) // cond: // result: (ADCL x y c) for { _ = v.Args[2] x := v.Args[0] y := v.Args[1] c := v.Args[2] v.reset(Op386ADCL) v.AddArg(x) v.AddArg(y) v.AddArg(c) return true } } func rewriteValue386_OpAdd64F_0(v *Value) bool { // match: (Add64F x y) // cond: // result: (ADDSD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAdd8_0(v *Value) bool { // match: (Add8 x y) // cond: // result: (ADDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAddPtr_0(v *Value) bool { // match: (AddPtr x y) // cond: // result: (ADDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAddr_0(v *Value) bool { // match: (Addr {sym} base) // cond: // result: (LEAL {sym} base) for { sym := v.Aux base := v.Args[0] v.reset(Op386LEAL) v.Aux = sym v.AddArg(base) return true } } func rewriteValue386_OpAnd16_0(v *Value) bool { // match: (And16 x y) // cond: // result: (ANDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAnd32_0(v *Value) bool { // match: (And32 x y) // cond: // result: (ANDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAnd8_0(v *Value) bool { // match: (And8 x y) // cond: // result: (ANDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAndB_0(v *Value) bool { // match: (AndB x y) // cond: // result: (ANDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAvg32u_0(v *Value) bool { // match: (Avg32u x y) // cond: // result: (AVGLU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386AVGLU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpBswap32_0(v *Value) bool { // match: (Bswap32 x) // cond: // result: (BSWAPL x) for { x := v.Args[0] v.reset(Op386BSWAPL) v.AddArg(x) return true } } func rewriteValue386_OpClosureCall_0(v *Value) bool { // match: (ClosureCall [argwid] entry closure mem) // cond: // result: (CALLclosure [argwid] entry closure mem) for { argwid := v.AuxInt _ = v.Args[2] entry := v.Args[0] closure := v.Args[1] mem := v.Args[2] v.reset(Op386CALLclosure) v.AuxInt = argwid v.AddArg(entry) v.AddArg(closure) v.AddArg(mem) return true } } func rewriteValue386_OpCom16_0(v *Value) bool { // match: (Com16 x) // cond: // result: (NOTL x) for { x := v.Args[0] v.reset(Op386NOTL) v.AddArg(x) return true } } func rewriteValue386_OpCom32_0(v *Value) bool { // match: (Com32 x) // cond: // result: (NOTL x) for { x := v.Args[0] v.reset(Op386NOTL) v.AddArg(x) return true } } func rewriteValue386_OpCom8_0(v *Value) bool { // match: (Com8 x) // cond: // result: (NOTL x) for { x := v.Args[0] v.reset(Op386NOTL) v.AddArg(x) return true } } func rewriteValue386_OpConst16_0(v *Value) bool { // match: (Const16 [val]) // cond: // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(Op386MOVLconst) v.AuxInt = val return true } } func rewriteValue386_OpConst32_0(v *Value) bool { // match: (Const32 [val]) // cond: // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(Op386MOVLconst) v.AuxInt = val return true } } func rewriteValue386_OpConst32F_0(v *Value) bool { // match: (Const32F [val]) // cond: // result: (MOVSSconst [val]) for { val := v.AuxInt v.reset(Op386MOVSSconst) v.AuxInt = val return true } } func rewriteValue386_OpConst64F_0(v *Value) bool { // match: (Const64F [val]) // cond: // result: (MOVSDconst [val]) for { val := v.AuxInt v.reset(Op386MOVSDconst) v.AuxInt = val return true } } func rewriteValue386_OpConst8_0(v *Value) bool { // match: (Const8 [val]) // cond: // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(Op386MOVLconst) v.AuxInt = val return true } } func rewriteValue386_OpConstBool_0(v *Value) bool { // match: (ConstBool [b]) // cond: // result: (MOVLconst [b]) for { b := v.AuxInt v.reset(Op386MOVLconst) v.AuxInt = b return true } } func rewriteValue386_OpConstNil_0(v *Value) bool { // match: (ConstNil) // cond: // result: (MOVLconst [0]) for { v.reset(Op386MOVLconst) v.AuxInt = 0 return true } } func rewriteValue386_OpCvt32Fto32_0(v *Value) bool { // match: (Cvt32Fto32 x) // cond: // result: (CVTTSS2SL x) for { x := v.Args[0] v.reset(Op386CVTTSS2SL) v.AddArg(x) return true } } func rewriteValue386_OpCvt32Fto64F_0(v *Value) bool { // match: (Cvt32Fto64F x) // cond: // result: (CVTSS2SD x) for { x := v.Args[0] v.reset(Op386CVTSS2SD) v.AddArg(x) return true } } func rewriteValue386_OpCvt32to32F_0(v *Value) bool { // match: (Cvt32to32F x) // cond: // result: (CVTSL2SS x) for { x := v.Args[0] v.reset(Op386CVTSL2SS) v.AddArg(x) return true } } func rewriteValue386_OpCvt32to64F_0(v *Value) bool { // match: (Cvt32to64F x) // cond: // result: (CVTSL2SD x) for { x := v.Args[0] v.reset(Op386CVTSL2SD) v.AddArg(x) return true } } func rewriteValue386_OpCvt64Fto32_0(v *Value) bool { // match: (Cvt64Fto32 x) // cond: // result: (CVTTSD2SL x) for { x := v.Args[0] v.reset(Op386CVTTSD2SL) v.AddArg(x) return true } } func rewriteValue386_OpCvt64Fto32F_0(v *Value) bool { // match: (Cvt64Fto32F x) // cond: // result: (CVTSD2SS x) for { x := v.Args[0] v.reset(Op386CVTSD2SS) v.AddArg(x) return true } } func rewriteValue386_OpDiv16_0(v *Value) bool { // match: (Div16 x y) // cond: // result: (DIVW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpDiv16u_0(v *Value) bool { // match: (Div16u x y) // cond: // result: (DIVWU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVWU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpDiv32_0(v *Value) bool { // match: (Div32 x y) // cond: // result: (DIVL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpDiv32F_0(v *Value) bool { // match: (Div32F x y) // cond: // result: (DIVSS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpDiv32u_0(v *Value) bool { // match: (Div32u x y) // cond: // result: (DIVLU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVLU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpDiv64F_0(v *Value) bool { // match: (Div64F x y) // cond: // result: (DIVSD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpDiv8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Div8 x y) // cond: // result: (DIVW (SignExt8to16 x) (SignExt8to16 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVW) v0 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValue386_OpDiv8u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Div8u x y) // cond: // result: (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVWU) v0 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValue386_OpEq16_0(v *Value) bool { b := v.Block _ = b // match: (Eq16 x y) // cond: // result: (SETEQ (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQ) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpEq32_0(v *Value) bool { b := v.Block _ = b // match: (Eq32 x y) // cond: // result: (SETEQ (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQ) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpEq32F_0(v *Value) bool { b := v.Block _ = b // match: (Eq32F x y) // cond: // result: (SETEQF (UCOMISS x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQF) v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpEq64F_0(v *Value) bool { b := v.Block _ = b // match: (Eq64F x y) // cond: // result: (SETEQF (UCOMISD x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQF) v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpEq8_0(v *Value) bool { b := v.Block _ = b // match: (Eq8 x y) // cond: // result: (SETEQ (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQ) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpEqB_0(v *Value) bool { b := v.Block _ = b // match: (EqB x y) // cond: // result: (SETEQ (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQ) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpEqPtr_0(v *Value) bool { b := v.Block _ = b // match: (EqPtr x y) // cond: // result: (SETEQ (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQ) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq16_0(v *Value) bool { b := v.Block _ = b // match: (Geq16 x y) // cond: // result: (SETGE (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGE) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq16U_0(v *Value) bool { b := v.Block _ = b // match: (Geq16U x y) // cond: // result: (SETAE (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETAE) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq32_0(v *Value) bool { b := v.Block _ = b // match: (Geq32 x y) // cond: // result: (SETGE (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq32F_0(v *Value) bool { b := v.Block _ = b // match: (Geq32F x y) // cond: // result: (SETGEF (UCOMISS x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGEF) v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq32U_0(v *Value) bool { b := v.Block _ = b // match: (Geq32U x y) // cond: // result: (SETAE (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETAE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq64F_0(v *Value) bool { b := v.Block _ = b // match: (Geq64F x y) // cond: // result: (SETGEF (UCOMISD x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGEF) v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq8_0(v *Value) bool { b := v.Block _ = b // match: (Geq8 x y) // cond: // result: (SETGE (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGE) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq8U_0(v *Value) bool { b := v.Block _ = b // match: (Geq8U x y) // cond: // result: (SETAE (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETAE) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGetCallerPC_0(v *Value) bool { // match: (GetCallerPC) // cond: // result: (LoweredGetCallerPC) for { v.reset(Op386LoweredGetCallerPC) return true } } func rewriteValue386_OpGetCallerSP_0(v *Value) bool { // match: (GetCallerSP) // cond: // result: (LoweredGetCallerSP) for { v.reset(Op386LoweredGetCallerSP) return true } } func rewriteValue386_OpGetClosurePtr_0(v *Value) bool { // match: (GetClosurePtr) // cond: // result: (LoweredGetClosurePtr) for { v.reset(Op386LoweredGetClosurePtr) return true } } func rewriteValue386_OpGetG_0(v *Value) bool { // match: (GetG mem) // cond: // result: (LoweredGetG mem) for { mem := v.Args[0] v.reset(Op386LoweredGetG) v.AddArg(mem) return true } } func rewriteValue386_OpGreater16_0(v *Value) bool { b := v.Block _ = b // match: (Greater16 x y) // cond: // result: (SETG (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETG) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater16U_0(v *Value) bool { b := v.Block _ = b // match: (Greater16U x y) // cond: // result: (SETA (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETA) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater32_0(v *Value) bool { b := v.Block _ = b // match: (Greater32 x y) // cond: // result: (SETG (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETG) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater32F_0(v *Value) bool { b := v.Block _ = b // match: (Greater32F x y) // cond: // result: (SETGF (UCOMISS x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGF) v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater32U_0(v *Value) bool { b := v.Block _ = b // match: (Greater32U x y) // cond: // result: (SETA (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETA) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater64F_0(v *Value) bool { b := v.Block _ = b // match: (Greater64F x y) // cond: // result: (SETGF (UCOMISD x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGF) v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater8_0(v *Value) bool { b := v.Block _ = b // match: (Greater8 x y) // cond: // result: (SETG (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETG) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater8U_0(v *Value) bool { b := v.Block _ = b // match: (Greater8U x y) // cond: // result: (SETA (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETA) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpHmul32_0(v *Value) bool { // match: (Hmul32 x y) // cond: // result: (HMULL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386HMULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpHmul32u_0(v *Value) bool { // match: (Hmul32u x y) // cond: // result: (HMULLU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386HMULLU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpInterCall_0(v *Value) bool { // match: (InterCall [argwid] entry mem) // cond: // result: (CALLinter [argwid] entry mem) for { argwid := v.AuxInt _ = v.Args[1] entry := v.Args[0] mem := v.Args[1] v.reset(Op386CALLinter) v.AuxInt = argwid v.AddArg(entry) v.AddArg(mem) return true } } func rewriteValue386_OpIsInBounds_0(v *Value) bool { b := v.Block _ = b // match: (IsInBounds idx len) // cond: // result: (SETB (CMPL idx len)) for { _ = v.Args[1] idx := v.Args[0] len := v.Args[1] v.reset(Op386SETB) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValue386_OpIsNonNil_0(v *Value) bool { b := v.Block _ = b // match: (IsNonNil p) // cond: // result: (SETNE (TESTL p p)) for { p := v.Args[0] v.reset(Op386SETNE) v0 := b.NewValue0(v.Pos, Op386TESTL, types.TypeFlags) v0.AddArg(p) v0.AddArg(p) v.AddArg(v0) return true } } func rewriteValue386_OpIsSliceInBounds_0(v *Value) bool { b := v.Block _ = b // match: (IsSliceInBounds idx len) // cond: // result: (SETBE (CMPL idx len)) for { _ = v.Args[1] idx := v.Args[0] len := v.Args[1] v.reset(Op386SETBE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValue386_OpLeq16_0(v *Value) bool { b := v.Block _ = b // match: (Leq16 x y) // cond: // result: (SETLE (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETLE) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLeq16U_0(v *Value) bool { b := v.Block _ = b // match: (Leq16U x y) // cond: // result: (SETBE (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETBE) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLeq32_0(v *Value) bool { b := v.Block _ = b // match: (Leq32 x y) // cond: // result: (SETLE (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETLE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLeq32F_0(v *Value) bool { b := v.Block _ = b // match: (Leq32F x y) // cond: // result: (SETGEF (UCOMISS y x)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGEF) v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValue386_OpLeq32U_0(v *Value) bool { b := v.Block _ = b // match: (Leq32U x y) // cond: // result: (SETBE (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETBE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLeq64F_0(v *Value) bool { b := v.Block _ = b // match: (Leq64F x y) // cond: // result: (SETGEF (UCOMISD y x)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGEF) v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValue386_OpLeq8_0(v *Value) bool { b := v.Block _ = b // match: (Leq8 x y) // cond: // result: (SETLE (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETLE) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLeq8U_0(v *Value) bool { b := v.Block _ = b // match: (Leq8U x y) // cond: // result: (SETBE (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETBE) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLess16_0(v *Value) bool { b := v.Block _ = b // match: (Less16 x y) // cond: // result: (SETL (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETL) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLess16U_0(v *Value) bool { b := v.Block _ = b // match: (Less16U x y) // cond: // result: (SETB (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETB) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLess32_0(v *Value) bool { b := v.Block _ = b // match: (Less32 x y) // cond: // result: (SETL (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETL) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLess32F_0(v *Value) bool { b := v.Block _ = b // match: (Less32F x y) // cond: // result: (SETGF (UCOMISS y x)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGF) v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValue386_OpLess32U_0(v *Value) bool { b := v.Block _ = b // match: (Less32U x y) // cond: // result: (SETB (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETB) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLess64F_0(v *Value) bool { b := v.Block _ = b // match: (Less64F x y) // cond: // result: (SETGF (UCOMISD y x)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGF) v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValue386_OpLess8_0(v *Value) bool { b := v.Block _ = b // match: (Less8 x y) // cond: // result: (SETL (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETL) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLess8U_0(v *Value) bool { b := v.Block _ = b // match: (Less8U x y) // cond: // result: (SETB (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETB) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLoad_0(v *Value) bool { // match: (Load ptr mem) // cond: (is32BitInt(t) || isPtr(t)) // result: (MOVLload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is32BitInt(t) || isPtr(t)) { break } v.reset(Op386MOVLload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is16BitInt(t)) { break } v.reset(Op386MOVWload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(Op386MOVBload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is32BitFloat(t)) { break } v.reset(Op386MOVSSload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is64BitFloat(t)) { break } v.reset(Op386MOVSDload) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_OpLocalAddr_0(v *Value) bool { // match: (LocalAddr {sym} base _) // cond: // result: (LEAL {sym} base) for { sym := v.Aux _ = v.Args[1] base := v.Args[0] v.reset(Op386LEAL) v.Aux = sym v.AddArg(base) return true } } func rewriteValue386_OpLsh16x16_0(v *Value) bool { b := v.Block _ = b // match: (Lsh16x16 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh16x32_0(v *Value) bool { b := v.Block _ = b // match: (Lsh16x32 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh16x64_0(v *Value) bool { // match: (Lsh16x64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SHLLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(Op386SHLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValue386_OpLsh16x8_0(v *Value) bool { b := v.Block _ = b // match: (Lsh16x8 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh32x16_0(v *Value) bool { b := v.Block _ = b // match: (Lsh32x16 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh32x32_0(v *Value) bool { b := v.Block _ = b // match: (Lsh32x32 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh32x64_0(v *Value) bool { // match: (Lsh32x64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SHLLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(Op386SHLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValue386_OpLsh32x8_0(v *Value) bool { b := v.Block _ = b // match: (Lsh32x8 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh8x16_0(v *Value) bool { b := v.Block _ = b // match: (Lsh8x16 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh8x32_0(v *Value) bool { b := v.Block _ = b // match: (Lsh8x32 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh8x64_0(v *Value) bool { // match: (Lsh8x64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SHLLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(Op386SHLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValue386_OpLsh8x8_0(v *Value) bool { b := v.Block _ = b // match: (Lsh8x8 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpMod16_0(v *Value) bool { // match: (Mod16 x y) // cond: // result: (MODW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MODW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMod16u_0(v *Value) bool { // match: (Mod16u x y) // cond: // result: (MODWU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MODWU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMod32_0(v *Value) bool { // match: (Mod32 x y) // cond: // result: (MODL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MODL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMod32u_0(v *Value) bool { // match: (Mod32u x y) // cond: // result: (MODLU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MODLU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMod8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod8 x y) // cond: // result: (MODW (SignExt8to16 x) (SignExt8to16 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MODW) v0 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValue386_OpMod8u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod8u x y) // cond: // result: (MODWU (ZeroExt8to16 x) (ZeroExt8to16 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MODWU) v0 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValue386_OpMove_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Move [0] _ _ mem) // cond: // result: mem for { if v.AuxInt != 0 { break } _ = v.Args[2] mem := v.Args[2] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Move [1] dst src mem) // cond: // result: (MOVBstore dst (MOVBload src mem) mem) for { if v.AuxInt != 1 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVBstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVBload, typ.UInt8) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [2] dst src mem) // cond: // result: (MOVWstore dst (MOVWload src mem) mem) for { if v.AuxInt != 2 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [4] dst src mem) // cond: // result: (MOVLstore dst (MOVLload src mem) mem) for { if v.AuxInt != 4 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [3] dst src mem) // cond: // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if v.AuxInt != 3 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVBstore) v.AuxInt = 2 v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVBload, typ.UInt8) v0.AuxInt = 2 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [5] dst src mem) // cond: // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 5 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVBstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVBload, typ.UInt8) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [6] dst src mem) // cond: // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 6 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [7] dst src mem) // cond: // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 7 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLstore) v.AuxInt = 3 v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v0.AuxInt = 3 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [8] dst src mem) // cond: // result: (MOVLstore [4] dst (MOVLload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 8 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [s] dst src mem) // cond: s > 8 && s%4 != 0 // result: (Move [s-s%4] (ADDLconst dst [s%4]) (ADDLconst src [s%4]) (MOVLstore dst (MOVLload src mem) mem)) for { s := v.AuxInt _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] if !(s > 8 && s%4 != 0) { break } v.reset(OpMove) v.AuxInt = s - s%4 v0 := b.NewValue0(v.Pos, Op386ADDLconst, dst.Type) v0.AuxInt = s % 4 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386ADDLconst, src.Type) v1.AuxInt = s % 4 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } return false } func rewriteValue386_OpMove_10(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config typ := &b.Func.Config.Types _ = typ // match: (Move [s] dst src mem) // cond: s > 8 && s <= 4*128 && s%4 == 0 && !config.noDuffDevice // result: (DUFFCOPY [10*(128-s/4)] dst src mem) for { s := v.AuxInt _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] if !(s > 8 && s <= 4*128 && s%4 == 0 && !config.noDuffDevice) { break } v.reset(Op386DUFFCOPY) v.AuxInt = 10 * (128 - s/4) v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } // match: (Move [s] dst src mem) // cond: (s > 4*128 || config.noDuffDevice) && s%4 == 0 // result: (REPMOVSL dst src (MOVLconst [s/4]) mem) for { s := v.AuxInt _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] if !((s > 4*128 || config.noDuffDevice) && s%4 == 0) { break } v.reset(Op386REPMOVSL) v.AddArg(dst) v.AddArg(src) v0 := b.NewValue0(v.Pos, Op386MOVLconst, typ.UInt32) v0.AuxInt = s / 4 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValue386_OpMul16_0(v *Value) bool { // match: (Mul16 x y) // cond: // result: (MULL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMul32_0(v *Value) bool { // match: (Mul32 x y) // cond: // result: (MULL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMul32F_0(v *Value) bool { // match: (Mul32F x y) // cond: // result: (MULSS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MULSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMul32uhilo_0(v *Value) bool { // match: (Mul32uhilo x y) // cond: // result: (MULLQU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MULLQU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMul64F_0(v *Value) bool { // match: (Mul64F x y) // cond: // result: (MULSD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MULSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMul8_0(v *Value) bool { // match: (Mul8 x y) // cond: // result: (MULL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpNeg16_0(v *Value) bool { // match: (Neg16 x) // cond: // result: (NEGL x) for { x := v.Args[0] v.reset(Op386NEGL) v.AddArg(x) return true } } func rewriteValue386_OpNeg32_0(v *Value) bool { // match: (Neg32 x) // cond: // result: (NEGL x) for { x := v.Args[0] v.reset(Op386NEGL) v.AddArg(x) return true } } func rewriteValue386_OpNeg32F_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config typ := &b.Func.Config.Types _ = typ // match: (Neg32F x) // cond: !config.use387 // result: (PXOR x (MOVSSconst [auxFrom32F(float32(math.Copysign(0, -1)))])) for { x := v.Args[0] if !(!config.use387) { break } v.reset(Op386PXOR) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386MOVSSconst, typ.Float32) v0.AuxInt = auxFrom32F(float32(math.Copysign(0, -1))) v.AddArg(v0) return true } // match: (Neg32F x) // cond: config.use387 // result: (FCHS x) for { x := v.Args[0] if !(config.use387) { break } v.reset(Op386FCHS) v.AddArg(x) return true } return false } func rewriteValue386_OpNeg64F_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config typ := &b.Func.Config.Types _ = typ // match: (Neg64F x) // cond: !config.use387 // result: (PXOR x (MOVSDconst [auxFrom64F(math.Copysign(0, -1))])) for { x := v.Args[0] if !(!config.use387) { break } v.reset(Op386PXOR) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386MOVSDconst, typ.Float64) v0.AuxInt = auxFrom64F(math.Copysign(0, -1)) v.AddArg(v0) return true } // match: (Neg64F x) // cond: config.use387 // result: (FCHS x) for { x := v.Args[0] if !(config.use387) { break } v.reset(Op386FCHS) v.AddArg(x) return true } return false } func rewriteValue386_OpNeg8_0(v *Value) bool { // match: (Neg8 x) // cond: // result: (NEGL x) for { x := v.Args[0] v.reset(Op386NEGL) v.AddArg(x) return true } } func rewriteValue386_OpNeq16_0(v *Value) bool { b := v.Block _ = b // match: (Neq16 x y) // cond: // result: (SETNE (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNE) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNeq32_0(v *Value) bool { b := v.Block _ = b // match: (Neq32 x y) // cond: // result: (SETNE (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNeq32F_0(v *Value) bool { b := v.Block _ = b // match: (Neq32F x y) // cond: // result: (SETNEF (UCOMISS x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNEF) v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNeq64F_0(v *Value) bool { b := v.Block _ = b // match: (Neq64F x y) // cond: // result: (SETNEF (UCOMISD x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNEF) v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNeq8_0(v *Value) bool { b := v.Block _ = b // match: (Neq8 x y) // cond: // result: (SETNE (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNE) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNeqB_0(v *Value) bool { b := v.Block _ = b // match: (NeqB x y) // cond: // result: (SETNE (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNE) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNeqPtr_0(v *Value) bool { b := v.Block _ = b // match: (NeqPtr x y) // cond: // result: (SETNE (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNilCheck_0(v *Value) bool { // match: (NilCheck ptr mem) // cond: // result: (LoweredNilCheck ptr mem) for { _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] v.reset(Op386LoweredNilCheck) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValue386_OpNot_0(v *Value) bool { // match: (Not x) // cond: // result: (XORLconst [1] x) for { x := v.Args[0] v.reset(Op386XORLconst) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValue386_OpOffPtr_0(v *Value) bool { // match: (OffPtr [off] ptr) // cond: // result: (ADDLconst [off] ptr) for { off := v.AuxInt ptr := v.Args[0] v.reset(Op386ADDLconst) v.AuxInt = off v.AddArg(ptr) return true } } func rewriteValue386_OpOr16_0(v *Value) bool { // match: (Or16 x y) // cond: // result: (ORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpOr32_0(v *Value) bool { // match: (Or32 x y) // cond: // result: (ORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpOr8_0(v *Value) bool { // match: (Or8 x y) // cond: // result: (ORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpOrB_0(v *Value) bool { // match: (OrB x y) // cond: // result: (ORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpRound32F_0(v *Value) bool { // match: (Round32F x) // cond: // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValue386_OpRound64F_0(v *Value) bool { // match: (Round64F x) // cond: // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValue386_OpRsh16Ux16_0(v *Value) bool { b := v.Block _ = b // match: (Rsh16Ux16 x y) // cond: // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh16Ux32_0(v *Value) bool { b := v.Block _ = b // match: (Rsh16Ux32 x y) // cond: // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh16Ux64_0(v *Value) bool { // match: (Rsh16Ux64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SHRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(Op386SHRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh16Ux64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValue386_OpRsh16Ux8_0(v *Value) bool { b := v.Block _ = b // match: (Rsh16Ux8 x y) // cond: // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh16x16_0(v *Value) bool { b := v.Block _ = b // match: (Rsh16x16 x y) // cond: // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh16x32_0(v *Value) bool { b := v.Block _ = b // match: (Rsh16x32 x y) // cond: // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh16x64_0(v *Value) bool { // match: (Rsh16x64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SARWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(Op386SARWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh16x64 x (Const64 [c])) // cond: uint64(c) >= 16 // result: (SARWconst x [15]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(Op386SARWconst) v.AuxInt = 15 v.AddArg(x) return true } return false } func rewriteValue386_OpRsh16x8_0(v *Value) bool { b := v.Block _ = b // match: (Rsh16x8 x y) // cond: // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh32Ux16_0(v *Value) bool { b := v.Block _ = b // match: (Rsh32Ux16 x y) // cond: // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh32Ux32_0(v *Value) bool { b := v.Block _ = b // match: (Rsh32Ux32 x y) // cond: // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh32Ux64_0(v *Value) bool { // match: (Rsh32Ux64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SHRLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(Op386SHRLconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValue386_OpRsh32Ux8_0(v *Value) bool { b := v.Block _ = b // match: (Rsh32Ux8 x y) // cond: // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh32x16_0(v *Value) bool { b := v.Block _ = b // match: (Rsh32x16 x y) // cond: // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh32x32_0(v *Value) bool { b := v.Block _ = b // match: (Rsh32x32 x y) // cond: // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh32x64_0(v *Value) bool { // match: (Rsh32x64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SARLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(Op386SARLconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x64 x (Const64 [c])) // cond: uint64(c) >= 32 // result: (SARLconst x [31]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(Op386SARLconst) v.AuxInt = 31 v.AddArg(x) return true } return false } func rewriteValue386_OpRsh32x8_0(v *Value) bool { b := v.Block _ = b // match: (Rsh32x8 x y) // cond: // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh8Ux16_0(v *Value) bool { b := v.Block _ = b // match: (Rsh8Ux16 x y) // cond: // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh8Ux32_0(v *Value) bool { b := v.Block _ = b // match: (Rsh8Ux32 x y) // cond: // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh8Ux64_0(v *Value) bool { // match: (Rsh8Ux64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SHRBconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(Op386SHRBconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh8Ux64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValue386_OpRsh8Ux8_0(v *Value) bool { b := v.Block _ = b // match: (Rsh8Ux8 x y) // cond: // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh8x16_0(v *Value) bool { b := v.Block _ = b // match: (Rsh8x16 x y) // cond: // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh8x32_0(v *Value) bool { b := v.Block _ = b // match: (Rsh8x32 x y) // cond: // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh8x64_0(v *Value) bool { // match: (Rsh8x64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SARBconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(Op386SARBconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh8x64 x (Const64 [c])) // cond: uint64(c) >= 8 // result: (SARBconst x [7]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(Op386SARBconst) v.AuxInt = 7 v.AddArg(x) return true } return false } func rewriteValue386_OpRsh8x8_0(v *Value) bool { b := v.Block _ = b // match: (Rsh8x8 x y) // cond: // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpSelect0_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Select0 (Mul32uover x y)) // cond: // result: (Select0 (MULLU x y)) for { v_0 := v.Args[0] if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, Op386MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValue386_OpSelect1_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Select1 (Mul32uover x y)) // cond: // result: (SETO (Select1 (MULLU x y))) for { v_0 := v.Args[0] if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] v.reset(Op386SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, Op386MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValue386_OpSignExt16to32_0(v *Value) bool { // match: (SignExt16to32 x) // cond: // result: (MOVWLSX x) for { x := v.Args[0] v.reset(Op386MOVWLSX) v.AddArg(x) return true } } func rewriteValue386_OpSignExt8to16_0(v *Value) bool { // match: (SignExt8to16 x) // cond: // result: (MOVBLSX x) for { x := v.Args[0] v.reset(Op386MOVBLSX) v.AddArg(x) return true } } func rewriteValue386_OpSignExt8to32_0(v *Value) bool { // match: (SignExt8to32 x) // cond: // result: (MOVBLSX x) for { x := v.Args[0] v.reset(Op386MOVBLSX) v.AddArg(x) return true } } func rewriteValue386_OpSignmask_0(v *Value) bool { // match: (Signmask x) // cond: // result: (SARLconst x [31]) for { x := v.Args[0] v.reset(Op386SARLconst) v.AuxInt = 31 v.AddArg(x) return true } } func rewriteValue386_OpSlicemask_0(v *Value) bool { b := v.Block _ = b // match: (Slicemask x) // cond: // result: (SARLconst (NEGL x) [31]) for { t := v.Type x := v.Args[0] v.reset(Op386SARLconst) v.AuxInt = 31 v0 := b.NewValue0(v.Pos, Op386NEGL, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValue386_OpSqrt_0(v *Value) bool { // match: (Sqrt x) // cond: // result: (SQRTSD x) for { x := v.Args[0] v.reset(Op386SQRTSD) v.AddArg(x) return true } } func rewriteValue386_OpStaticCall_0(v *Value) bool { // match: (StaticCall [argwid] {target} mem) // cond: // result: (CALLstatic [argwid] {target} mem) for { argwid := v.AuxInt target := v.Aux mem := v.Args[0] v.reset(Op386CALLstatic) v.AuxInt = argwid v.Aux = target v.AddArg(mem) return true } } func rewriteValue386_OpStore_0(v *Value) bool { // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) // result: (MOVSDstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(Op386MOVSDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) // result: (MOVSSstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(Op386MOVSSstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 // result: (MOVLstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 4) { break } v.reset(Op386MOVLstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 2 // result: (MOVWstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 2) { break } v.reset(Op386MOVWstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 1 // result: (MOVBstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 1) { break } v.reset(Op386MOVBstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_OpSub16_0(v *Value) bool { // match: (Sub16 x y) // cond: // result: (SUBL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpSub32_0(v *Value) bool { // match: (Sub32 x y) // cond: // result: (SUBL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpSub32F_0(v *Value) bool { // match: (Sub32F x y) // cond: // result: (SUBSS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpSub32carry_0(v *Value) bool { // match: (Sub32carry x y) // cond: // result: (SUBLcarry x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBLcarry) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpSub32withcarry_0(v *Value) bool { // match: (Sub32withcarry x y c) // cond: // result: (SBBL x y c) for { _ = v.Args[2] x := v.Args[0] y := v.Args[1] c := v.Args[2] v.reset(Op386SBBL) v.AddArg(x) v.AddArg(y) v.AddArg(c) return true } } func rewriteValue386_OpSub64F_0(v *Value) bool { // match: (Sub64F x y) // cond: // result: (SUBSD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpSub8_0(v *Value) bool { // match: (Sub8 x y) // cond: // result: (SUBL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpSubPtr_0(v *Value) bool { // match: (SubPtr x y) // cond: // result: (SUBL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpTrunc16to8_0(v *Value) bool { // match: (Trunc16to8 x) // cond: // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValue386_OpTrunc32to16_0(v *Value) bool { // match: (Trunc32to16 x) // cond: // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValue386_OpTrunc32to8_0(v *Value) bool { // match: (Trunc32to8 x) // cond: // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValue386_OpWB_0(v *Value) bool { // match: (WB {fn} destptr srcptr mem) // cond: // result: (LoweredWB {fn} destptr srcptr mem) for { fn := v.Aux _ = v.Args[2] destptr := v.Args[0] srcptr := v.Args[1] mem := v.Args[2] v.reset(Op386LoweredWB) v.Aux = fn v.AddArg(destptr) v.AddArg(srcptr) v.AddArg(mem) return true } } func rewriteValue386_OpXor16_0(v *Value) bool { // match: (Xor16 x y) // cond: // result: (XORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpXor32_0(v *Value) bool { // match: (Xor32 x y) // cond: // result: (XORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpXor8_0(v *Value) bool { // match: (Xor8 x y) // cond: // result: (XORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpZero_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Zero [0] _ mem) // cond: // result: mem for { if v.AuxInt != 0 { break } _ = v.Args[1] mem := v.Args[1] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Zero [1] destptr mem) // cond: // result: (MOVBstoreconst [0] destptr mem) for { if v.AuxInt != 1 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVBstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [2] destptr mem) // cond: // result: (MOVWstoreconst [0] destptr mem) for { if v.AuxInt != 2 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVWstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [4] destptr mem) // cond: // result: (MOVLstoreconst [0] destptr mem) for { if v.AuxInt != 4 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVLstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [3] destptr mem) // cond: // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [0] destptr mem)) for { if v.AuxInt != 3 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVBstoreconst) v.AuxInt = makeValAndOff(0, 2) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVWstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [5] destptr mem) // cond: // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 5 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVBstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [6] destptr mem) // cond: // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 6 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVWstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [7] destptr mem) // cond: // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 7 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVLstoreconst) v.AuxInt = makeValAndOff(0, 3) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s%4 != 0 && s > 4 // result: (Zero [s-s%4] (ADDLconst destptr [s%4]) (MOVLstoreconst [0] destptr mem)) for { s := v.AuxInt _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(s%4 != 0 && s > 4) { break } v.reset(OpZero) v.AuxInt = s - s%4 v0 := b.NewValue0(v.Pos, Op386ADDLconst, typ.UInt32) v0.AuxInt = s % 4 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Zero [8] destptr mem) // cond: // result: (MOVLstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 8 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVLstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValue386_OpZero_10(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config typ := &b.Func.Config.Types _ = typ // match: (Zero [12] destptr mem) // cond: // result: (MOVLstoreconst [makeValAndOff(0,8)] destptr (MOVLstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem))) for { if v.AuxInt != 12 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVLstoreconst) v.AuxInt = makeValAndOff(0, 8) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v0.AuxInt = makeValAndOff(0, 4) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [16] destptr mem) // cond: // result: (MOVLstoreconst [makeValAndOff(0,12)] destptr (MOVLstoreconst [makeValAndOff(0,8)] destptr (MOVLstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)))) for { if v.AuxInt != 16 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVLstoreconst) v.AuxInt = makeValAndOff(0, 12) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v0.AuxInt = makeValAndOff(0, 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v1.AuxInt = makeValAndOff(0, 4) v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v2.AuxInt = 0 v2.AddArg(destptr) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s > 16 && s <= 4*128 && s%4 == 0 && !config.noDuffDevice // result: (DUFFZERO [1*(128-s/4)] destptr (MOVLconst [0]) mem) for { s := v.AuxInt _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(s > 16 && s <= 4*128 && s%4 == 0 && !config.noDuffDevice) { break } v.reset(Op386DUFFZERO) v.AuxInt = 1 * (128 - s/4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLconst, typ.UInt32) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 4*128 || (config.noDuffDevice && s > 16)) && s%4 == 0 // result: (REPSTOSL destptr (MOVLconst [s/4]) (MOVLconst [0]) mem) for { s := v.AuxInt _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !((s > 4*128 || (config.noDuffDevice && s > 16)) && s%4 == 0) { break } v.reset(Op386REPSTOSL) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLconst, typ.UInt32) v0.AuxInt = s / 4 v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVLconst, typ.UInt32) v1.AuxInt = 0 v.AddArg(v1) v.AddArg(mem) return true } return false } func rewriteValue386_OpZeroExt16to32_0(v *Value) bool { // match: (ZeroExt16to32 x) // cond: // result: (MOVWLZX x) for { x := v.Args[0] v.reset(Op386MOVWLZX) v.AddArg(x) return true } } func rewriteValue386_OpZeroExt8to16_0(v *Value) bool { // match: (ZeroExt8to16 x) // cond: // result: (MOVBLZX x) for { x := v.Args[0] v.reset(Op386MOVBLZX) v.AddArg(x) return true } } func rewriteValue386_OpZeroExt8to32_0(v *Value) bool { // match: (ZeroExt8to32 x) // cond: // result: (MOVBLZX x) for { x := v.Args[0] v.reset(Op386MOVBLZX) v.AddArg(x) return true } } func rewriteValue386_OpZeromask_0(v *Value) bool { b := v.Block _ = b // match: (Zeromask x) // cond: // result: (XORLconst [-1] (SBBLcarrymask (CMPLconst x [1]))) for { t := v.Type x := v.Args[0] v.reset(Op386XORLconst) v.AuxInt = -1 v0 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v1 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v1.AuxInt = 1 v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteBlock386(b *Block) bool { config := b.Func.Config _ = config fe := b.Func.fe _ = fe typ := &config.Types _ = typ switch b.Kind { case Block386EQ: // match: (EQ (InvertFlags cmp) yes no) // cond: // result: (EQ cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386EQ b.SetControl(cmp) b.Aux = nil return true } // match: (EQ (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (EQ (FlagLT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } case Block386GE: // match: (GE (InvertFlags cmp) yes no) // cond: // result: (LE cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386LE b.SetControl(cmp) b.Aux = nil return true } // match: (GE (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (GE (FlagLT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (GE (FlagGT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } case Block386GT: // match: (GT (InvertFlags cmp) yes no) // cond: // result: (LT cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386LT b.SetControl(cmp) b.Aux = nil return true } // match: (GT (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (GT (FlagGT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } case BlockIf: // match: (If (SETL cmp) yes no) // cond: // result: (LT cmp yes no) for { v := b.Control if v.Op != Op386SETL { break } cmp := v.Args[0] b.Kind = Block386LT b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETLE cmp) yes no) // cond: // result: (LE cmp yes no) for { v := b.Control if v.Op != Op386SETLE { break } cmp := v.Args[0] b.Kind = Block386LE b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETG cmp) yes no) // cond: // result: (GT cmp yes no) for { v := b.Control if v.Op != Op386SETG { break } cmp := v.Args[0] b.Kind = Block386GT b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETGE cmp) yes no) // cond: // result: (GE cmp yes no) for { v := b.Control if v.Op != Op386SETGE { break } cmp := v.Args[0] b.Kind = Block386GE b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETEQ cmp) yes no) // cond: // result: (EQ cmp yes no) for { v := b.Control if v.Op != Op386SETEQ { break } cmp := v.Args[0] b.Kind = Block386EQ b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETNE cmp) yes no) // cond: // result: (NE cmp yes no) for { v := b.Control if v.Op != Op386SETNE { break } cmp := v.Args[0] b.Kind = Block386NE b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETB cmp) yes no) // cond: // result: (ULT cmp yes no) for { v := b.Control if v.Op != Op386SETB { break } cmp := v.Args[0] b.Kind = Block386ULT b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETBE cmp) yes no) // cond: // result: (ULE cmp yes no) for { v := b.Control if v.Op != Op386SETBE { break } cmp := v.Args[0] b.Kind = Block386ULE b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETA cmp) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386SETA { break } cmp := v.Args[0] b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETAE cmp) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386SETAE { break } cmp := v.Args[0] b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETO cmp) yes no) // cond: // result: (OS cmp yes no) for { v := b.Control if v.Op != Op386SETO { break } cmp := v.Args[0] b.Kind = Block386OS b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETGF cmp) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386SETGF { break } cmp := v.Args[0] b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETGEF cmp) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386SETGEF { break } cmp := v.Args[0] b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETEQF cmp) yes no) // cond: // result: (EQF cmp yes no) for { v := b.Control if v.Op != Op386SETEQF { break } cmp := v.Args[0] b.Kind = Block386EQF b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETNEF cmp) yes no) // cond: // result: (NEF cmp yes no) for { v := b.Control if v.Op != Op386SETNEF { break } cmp := v.Args[0] b.Kind = Block386NEF b.SetControl(cmp) b.Aux = nil return true } // match: (If cond yes no) // cond: // result: (NE (TESTB cond cond) yes no) for { v := b.Control _ = v cond := b.Control b.Kind = Block386NE v0 := b.NewValue0(v.Pos, Op386TESTB, types.TypeFlags) v0.AddArg(cond) v0.AddArg(cond) b.SetControl(v0) b.Aux = nil return true } case Block386LE: // match: (LE (InvertFlags cmp) yes no) // cond: // result: (GE cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386GE b.SetControl(cmp) b.Aux = nil return true } // match: (LE (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LE (FlagLT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LE (FlagLT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LE (FlagGT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } case Block386LT: // match: (LT (InvertFlags cmp) yes no) // cond: // result: (GT cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386GT b.SetControl(cmp) b.Aux = nil return true } // match: (LT (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LT (FlagLT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LT (FlagGT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } case Block386NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // cond: // result: (LT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETL { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETL { break } if cmp != v_1.Args[0] { break } b.Kind = Block386LT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // cond: // result: (LT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETL { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETL { break } if cmp != v_1.Args[0] { break } b.Kind = Block386LT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // cond: // result: (LE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETLE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETLE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386LE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // cond: // result: (LE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETLE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETLE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386LE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // cond: // result: (GT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETG { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETG { break } if cmp != v_1.Args[0] { break } b.Kind = Block386GT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // cond: // result: (GT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETG { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETG { break } if cmp != v_1.Args[0] { break } b.Kind = Block386GT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // cond: // result: (GE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETGE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETGE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386GE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // cond: // result: (GE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETGE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETGE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386GE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // cond: // result: (EQ cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETEQ { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETEQ { break } if cmp != v_1.Args[0] { break } b.Kind = Block386EQ b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // cond: // result: (EQ cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETEQ { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETEQ { break } if cmp != v_1.Args[0] { break } b.Kind = Block386EQ b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // cond: // result: (NE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETNE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETNE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386NE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // cond: // result: (NE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETNE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETNE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386NE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // cond: // result: (ULT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETB { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETB { break } if cmp != v_1.Args[0] { break } b.Kind = Block386ULT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // cond: // result: (ULT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETB { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETB { break } if cmp != v_1.Args[0] { break } b.Kind = Block386ULT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // cond: // result: (ULE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETBE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETBE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386ULE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // cond: // result: (ULE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETBE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETBE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386ULE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETA { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETA { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETA { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETA { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETAE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETAE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETAE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETAE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // cond: // result: (OS cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETO { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETO { break } if cmp != v_1.Args[0] { break } b.Kind = Block386OS b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // cond: // result: (OS cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETO { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETO { break } if cmp != v_1.Args[0] { break } b.Kind = Block386OS b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETGF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETGF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETGF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETGF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETGEF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETGEF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETGEF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETGEF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // cond: // result: (EQF cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETEQF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETEQF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386EQF b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // cond: // result: (EQF cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETEQF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETEQF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386EQF b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // cond: // result: (NEF cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETNEF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETNEF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386NEF b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // cond: // result: (NEF cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETNEF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETNEF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386NEF b.SetControl(cmp) b.Aux = nil return true } // match: (NE (InvertFlags cmp) yes no) // cond: // result: (NE cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386NE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (NE (FlagLT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (NE (FlagGT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (NE (FlagGT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } case Block386UGE: // match: (UGE (InvertFlags cmp) yes no) // cond: // result: (ULE cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386ULE b.SetControl(cmp) b.Aux = nil return true } // match: (UGE (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (UGE (FlagLT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (UGE (FlagGT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } case Block386UGT: // match: (UGT (InvertFlags cmp) yes no) // cond: // result: (ULT cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386ULT b.SetControl(cmp) b.Aux = nil return true } // match: (UGT (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (UGT (FlagGT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } case Block386ULE: // match: (ULE (InvertFlags cmp) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (ULE (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (ULE (FlagLT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (ULE (FlagLT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (ULE (FlagGT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } case Block386ULT: // match: (ULT (InvertFlags cmp) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (ULT (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (ULT (FlagLT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (ULT (FlagGT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } } return false } -- y -- // Code generated from gen/386.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/internal/obj" import "cmd/internal/objabi" import "cmd/compile/internal/types" var _ = math.MinInt8 // in case not otherwise used var _ = obj.ANOP // in case not otherwise used var _ = objabi.GOROOT // in case not otherwise used var _ = types.TypeMem // in case not otherwise used func rewriteValue386(v *Value) bool { switch v.Op { case Op386ADCL: return rewriteValue386_Op386ADCL_0(v) case Op386ADDL: return rewriteValue386_Op386ADDL_0(v) || rewriteValue386_Op386ADDL_10(v) || rewriteValue386_Op386ADDL_20(v) case Op386ADDLcarry: return rewriteValue386_Op386ADDLcarry_0(v) case Op386ADDLconst: return rewriteValue386_Op386ADDLconst_0(v) case Op386ADDLconstmodify: return rewriteValue386_Op386ADDLconstmodify_0(v) case Op386ADDLconstmodifyidx4: return rewriteValue386_Op386ADDLconstmodifyidx4_0(v) case Op386ADDLload: return rewriteValue386_Op386ADDLload_0(v) case Op386ADDLloadidx4: return rewriteValue386_Op386ADDLloadidx4_0(v) case Op386ADDLmodify: return rewriteValue386_Op386ADDLmodify_0(v) case Op386ADDLmodifyidx4: return rewriteValue386_Op386ADDLmodifyidx4_0(v) case Op386ADDSD: return rewriteValue386_Op386ADDSD_0(v) case Op386ADDSDload: return rewriteValue386_Op386ADDSDload_0(v) case Op386ADDSS: return rewriteValue386_Op386ADDSS_0(v) case Op386ADDSSload: return rewriteValue386_Op386ADDSSload_0(v) case Op386ANDL: return rewriteValue386_Op386ANDL_0(v) case Op386ANDLconst: return rewriteValue386_Op386ANDLconst_0(v) case Op386ANDLconstmodify: return rewriteValue386_Op386ANDLconstmodify_0(v) case Op386ANDLconstmodifyidx4: return rewriteValue386_Op386ANDLconstmodifyidx4_0(v) case Op386ANDLload: return rewriteValue386_Op386ANDLload_0(v) case Op386ANDLloadidx4: return rewriteValue386_Op386ANDLloadidx4_0(v) case Op386ANDLmodify: return rewriteValue386_Op386ANDLmodify_0(v) case Op386ANDLmodifyidx4: return rewriteValue386_Op386ANDLmodifyidx4_0(v) case Op386CMPB: return rewriteValue386_Op386CMPB_0(v) case Op386CMPBconst: return rewriteValue386_Op386CMPBconst_0(v) case Op386CMPBload: return rewriteValue386_Op386CMPBload_0(v) case Op386CMPL: return rewriteValue386_Op386CMPL_0(v) case Op386CMPLconst: return rewriteValue386_Op386CMPLconst_0(v) || rewriteValue386_Op386CMPLconst_10(v) case Op386CMPLload: return rewriteValue386_Op386CMPLload_0(v) case Op386CMPW: return rewriteValue386_Op386CMPW_0(v) case Op386CMPWconst: return rewriteValue386_Op386CMPWconst_0(v) case Op386CMPWload: return rewriteValue386_Op386CMPWload_0(v) case Op386DIVSD: return rewriteValue386_Op386DIVSD_0(v) case Op386DIVSDload: return rewriteValue386_Op386DIVSDload_0(v) case Op386DIVSS: return rewriteValue386_Op386DIVSS_0(v) case Op386DIVSSload: return rewriteValue386_Op386DIVSSload_0(v) case Op386LEAL: return rewriteValue386_Op386LEAL_0(v) case Op386LEAL1: return rewriteValue386_Op386LEAL1_0(v) case Op386LEAL2: return rewriteValue386_Op386LEAL2_0(v) case Op386LEAL4: return rewriteValue386_Op386LEAL4_0(v) case Op386LEAL8: return rewriteValue386_Op386LEAL8_0(v) case Op386MOVBLSX: return rewriteValue386_Op386MOVBLSX_0(v) case Op386MOVBLSXload: return rewriteValue386_Op386MOVBLSXload_0(v) case Op386MOVBLZX: return rewriteValue386_Op386MOVBLZX_0(v) case Op386MOVBload: return rewriteValue386_Op386MOVBload_0(v) case Op386MOVBloadidx1: return rewriteValue386_Op386MOVBloadidx1_0(v) case Op386MOVBstore: return rewriteValue386_Op386MOVBstore_0(v) || rewriteValue386_Op386MOVBstore_10(v) case Op386MOVBstoreconst: return rewriteValue386_Op386MOVBstoreconst_0(v) case Op386MOVBstoreconstidx1: return rewriteValue386_Op386MOVBstoreconstidx1_0(v) case Op386MOVBstoreidx1: return rewriteValue386_Op386MOVBstoreidx1_0(v) || rewriteValue386_Op386MOVBstoreidx1_10(v) || rewriteValue386_Op386MOVBstoreidx1_20(v) case Op386MOVLload: return rewriteValue386_Op386MOVLload_0(v) case Op386MOVLloadidx1: return rewriteValue386_Op386MOVLloadidx1_0(v) case Op386MOVLloadidx4: return rewriteValue386_Op386MOVLloadidx4_0(v) case Op386MOVLstore: return rewriteValue386_Op386MOVLstore_0(v) || rewriteValue386_Op386MOVLstore_10(v) || rewriteValue386_Op386MOVLstore_20(v) case Op386MOVLstoreconst: return rewriteValue386_Op386MOVLstoreconst_0(v) case Op386MOVLstoreconstidx1: return rewriteValue386_Op386MOVLstoreconstidx1_0(v) case Op386MOVLstoreconstidx4: return rewriteValue386_Op386MOVLstoreconstidx4_0(v) case Op386MOVLstoreidx1: return rewriteValue386_Op386MOVLstoreidx1_0(v) case Op386MOVLstoreidx4: return rewriteValue386_Op386MOVLstoreidx4_0(v) || rewriteValue386_Op386MOVLstoreidx4_10(v) case Op386MOVSDconst: return rewriteValue386_Op386MOVSDconst_0(v) case Op386MOVSDload: return rewriteValue386_Op386MOVSDload_0(v) case Op386MOVSDloadidx1: return rewriteValue386_Op386MOVSDloadidx1_0(v) case Op386MOVSDloadidx8: return rewriteValue386_Op386MOVSDloadidx8_0(v) case Op386MOVSDstore: return rewriteValue386_Op386MOVSDstore_0(v) case Op386MOVSDstoreidx1: return rewriteValue386_Op386MOVSDstoreidx1_0(v) case Op386MOVSDstoreidx8: return rewriteValue386_Op386MOVSDstoreidx8_0(v) case Op386MOVSSconst: return rewriteValue386_Op386MOVSSconst_0(v) case Op386MOVSSload: return rewriteValue386_Op386MOVSSload_0(v) case Op386MOVSSloadidx1: return rewriteValue386_Op386MOVSSloadidx1_0(v) case Op386MOVSSloadidx4: return rewriteValue386_Op386MOVSSloadidx4_0(v) case Op386MOVSSstore: return rewriteValue386_Op386MOVSSstore_0(v) case Op386MOVSSstoreidx1: return rewriteValue386_Op386MOVSSstoreidx1_0(v) case Op386MOVSSstoreidx4: return rewriteValue386_Op386MOVSSstoreidx4_0(v) case Op386MOVWLSX: return rewriteValue386_Op386MOVWLSX_0(v) case Op386MOVWLSXload: return rewriteValue386_Op386MOVWLSXload_0(v) case Op386MOVWLZX: return rewriteValue386_Op386MOVWLZX_0(v) case Op386MOVWload: return rewriteValue386_Op386MOVWload_0(v) case Op386MOVWloadidx1: return rewriteValue386_Op386MOVWloadidx1_0(v) case Op386MOVWloadidx2: return rewriteValue386_Op386MOVWloadidx2_0(v) case Op386MOVWstore: return rewriteValue386_Op386MOVWstore_0(v) case Op386MOVWstoreconst: return rewriteValue386_Op386MOVWstoreconst_0(v) case Op386MOVWstoreconstidx1: return rewriteValue386_Op386MOVWstoreconstidx1_0(v) case Op386MOVWstoreconstidx2: return rewriteValue386_Op386MOVWstoreconstidx2_0(v) case Op386MOVWstoreidx1: return rewriteValue386_Op386MOVWstoreidx1_0(v) || rewriteValue386_Op386MOVWstoreidx1_10(v) case Op386MOVWstoreidx2: return rewriteValue386_Op386MOVWstoreidx2_0(v) case Op386MULL: return rewriteValue386_Op386MULL_0(v) case Op386MULLconst: return rewriteValue386_Op386MULLconst_0(v) || rewriteValue386_Op386MULLconst_10(v) || rewriteValue386_Op386MULLconst_20(v) || rewriteValue386_Op386MULLconst_30(v) case Op386MULLload: return rewriteValue386_Op386MULLload_0(v) case Op386MULLloadidx4: return rewriteValue386_Op386MULLloadidx4_0(v) case Op386MULSD: return rewriteValue386_Op386MULSD_0(v) case Op386MULSDload: return rewriteValue386_Op386MULSDload_0(v) case Op386MULSS: return rewriteValue386_Op386MULSS_0(v) case Op386MULSSload: return rewriteValue386_Op386MULSSload_0(v) case Op386NEGL: return rewriteValue386_Op386NEGL_0(v) case Op386NOTL: return rewriteValue386_Op386NOTL_0(v) case Op386ORL: return rewriteValue386_Op386ORL_0(v) || rewriteValue386_Op386ORL_10(v) || rewriteValue386_Op386ORL_20(v) || rewriteValue386_Op386ORL_30(v) || rewriteValue386_Op386ORL_40(v) || rewriteValue386_Op386ORL_50(v) case Op386ORLconst: return rewriteValue386_Op386ORLconst_0(v) case Op386ORLconstmodify: return rewriteValue386_Op386ORLconstmodify_0(v) case Op386ORLconstmodifyidx4: return rewriteValue386_Op386ORLconstmodifyidx4_0(v) case Op386ORLload: return rewriteValue386_Op386ORLload_0(v) case Op386ORLloadidx4: return rewriteValue386_Op386ORLloadidx4_0(v) case Op386ORLmodify: return rewriteValue386_Op386ORLmodify_0(v) case Op386ORLmodifyidx4: return rewriteValue386_Op386ORLmodifyidx4_0(v) case Op386ROLBconst: return rewriteValue386_Op386ROLBconst_0(v) case Op386ROLLconst: return rewriteValue386_Op386ROLLconst_0(v) case Op386ROLWconst: return rewriteValue386_Op386ROLWconst_0(v) case Op386SARB: return rewriteValue386_Op386SARB_0(v) case Op386SARBconst: return rewriteValue386_Op386SARBconst_0(v) case Op386SARL: return rewriteValue386_Op386SARL_0(v) case Op386SARLconst: return rewriteValue386_Op386SARLconst_0(v) case Op386SARW: return rewriteValue386_Op386SARW_0(v) case Op386SARWconst: return rewriteValue386_Op386SARWconst_0(v) case Op386SBBL: return rewriteValue386_Op386SBBL_0(v) case Op386SBBLcarrymask: return rewriteValue386_Op386SBBLcarrymask_0(v) case Op386SETA: return rewriteValue386_Op386SETA_0(v) case Op386SETAE: return rewriteValue386_Op386SETAE_0(v) case Op386SETB: return rewriteValue386_Op386SETB_0(v) case Op386SETBE: return rewriteValue386_Op386SETBE_0(v) case Op386SETEQ: return rewriteValue386_Op386SETEQ_0(v) case Op386SETG: return rewriteValue386_Op386SETG_0(v) case Op386SETGE: return rewriteValue386_Op386SETGE_0(v) case Op386SETL: return rewriteValue386_Op386SETL_0(v) case Op386SETLE: return rewriteValue386_Op386SETLE_0(v) case Op386SETNE: return rewriteValue386_Op386SETNE_0(v) case Op386SHLL: return rewriteValue386_Op386SHLL_0(v) case Op386SHLLconst: return rewriteValue386_Op386SHLLconst_0(v) case Op386SHRB: return rewriteValue386_Op386SHRB_0(v) case Op386SHRBconst: return rewriteValue386_Op386SHRBconst_0(v) case Op386SHRL: return rewriteValue386_Op386SHRL_0(v) case Op386SHRLconst: return rewriteValue386_Op386SHRLconst_0(v) case Op386SHRW: return rewriteValue386_Op386SHRW_0(v) case Op386SHRWconst: return rewriteValue386_Op386SHRWconst_0(v) case Op386SUBL: return rewriteValue386_Op386SUBL_0(v) case Op386SUBLcarry: return rewriteValue386_Op386SUBLcarry_0(v) case Op386SUBLconst: return rewriteValue386_Op386SUBLconst_0(v) case Op386SUBLload: return rewriteValue386_Op386SUBLload_0(v) case Op386SUBLloadidx4: return rewriteValue386_Op386SUBLloadidx4_0(v) case Op386SUBLmodify: return rewriteValue386_Op386SUBLmodify_0(v) case Op386SUBLmodifyidx4: return rewriteValue386_Op386SUBLmodifyidx4_0(v) case Op386SUBSD: return rewriteValue386_Op386SUBSD_0(v) case Op386SUBSDload: return rewriteValue386_Op386SUBSDload_0(v) case Op386SUBSS: return rewriteValue386_Op386SUBSS_0(v) case Op386SUBSSload: return rewriteValue386_Op386SUBSSload_0(v) case Op386XORL: return rewriteValue386_Op386XORL_0(v) || rewriteValue386_Op386XORL_10(v) case Op386XORLconst: return rewriteValue386_Op386XORLconst_0(v) case Op386XORLconstmodify: return rewriteValue386_Op386XORLconstmodify_0(v) case Op386XORLconstmodifyidx4: return rewriteValue386_Op386XORLconstmodifyidx4_0(v) case Op386XORLload: return rewriteValue386_Op386XORLload_0(v) case Op386XORLloadidx4: return rewriteValue386_Op386XORLloadidx4_0(v) case Op386XORLmodify: return rewriteValue386_Op386XORLmodify_0(v) case Op386XORLmodifyidx4: return rewriteValue386_Op386XORLmodifyidx4_0(v) case OpAdd16: return rewriteValue386_OpAdd16_0(v) case OpAdd32: return rewriteValue386_OpAdd32_0(v) case OpAdd32F: return rewriteValue386_OpAdd32F_0(v) case OpAdd32carry: return rewriteValue386_OpAdd32carry_0(v) case OpAdd32withcarry: return rewriteValue386_OpAdd32withcarry_0(v) case OpAdd64F: return rewriteValue386_OpAdd64F_0(v) case OpAdd8: return rewriteValue386_OpAdd8_0(v) case OpAddPtr: return rewriteValue386_OpAddPtr_0(v) case OpAddr: return rewriteValue386_OpAddr_0(v) case OpAnd16: return rewriteValue386_OpAnd16_0(v) case OpAnd32: return rewriteValue386_OpAnd32_0(v) case OpAnd8: return rewriteValue386_OpAnd8_0(v) case OpAndB: return rewriteValue386_OpAndB_0(v) case OpAvg32u: return rewriteValue386_OpAvg32u_0(v) case OpBswap32: return rewriteValue386_OpBswap32_0(v) case OpClosureCall: return rewriteValue386_OpClosureCall_0(v) case OpCom16: return rewriteValue386_OpCom16_0(v) case OpCom32: return rewriteValue386_OpCom32_0(v) case OpCom8: return rewriteValue386_OpCom8_0(v) case OpConst16: return rewriteValue386_OpConst16_0(v) case OpConst32: return rewriteValue386_OpConst32_0(v) case OpConst32F: return rewriteValue386_OpConst32F_0(v) case OpConst64F: return rewriteValue386_OpConst64F_0(v) case OpConst8: return rewriteValue386_OpConst8_0(v) case OpConstBool: return rewriteValue386_OpConstBool_0(v) case OpConstNil: return rewriteValue386_OpConstNil_0(v) case OpCvt32Fto32: return rewriteValue386_OpCvt32Fto32_0(v) case OpCvt32Fto64F: return rewriteValue386_OpCvt32Fto64F_0(v) case OpCvt32to32F: return rewriteValue386_OpCvt32to32F_0(v) case OpCvt32to64F: return rewriteValue386_OpCvt32to64F_0(v) case OpCvt64Fto32: return rewriteValue386_OpCvt64Fto32_0(v) case OpCvt64Fto32F: return rewriteValue386_OpCvt64Fto32F_0(v) case OpDiv16: return rewriteValue386_OpDiv16_0(v) case OpDiv16u: return rewriteValue386_OpDiv16u_0(v) case OpDiv32: return rewriteValue386_OpDiv32_0(v) case OpDiv32F: return rewriteValue386_OpDiv32F_0(v) case OpDiv32u: return rewriteValue386_OpDiv32u_0(v) case OpDiv64F: return rewriteValue386_OpDiv64F_0(v) case OpDiv8: return rewriteValue386_OpDiv8_0(v) case OpDiv8u: return rewriteValue386_OpDiv8u_0(v) case OpEq16: return rewriteValue386_OpEq16_0(v) case OpEq32: return rewriteValue386_OpEq32_0(v) case OpEq32F: return rewriteValue386_OpEq32F_0(v) case OpEq64F: return rewriteValue386_OpEq64F_0(v) case OpEq8: return rewriteValue386_OpEq8_0(v) case OpEqB: return rewriteValue386_OpEqB_0(v) case OpEqPtr: return rewriteValue386_OpEqPtr_0(v) case OpGeq16: return rewriteValue386_OpGeq16_0(v) case OpGeq16U: return rewriteValue386_OpGeq16U_0(v) case OpGeq32: return rewriteValue386_OpGeq32_0(v) case OpGeq32F: return rewriteValue386_OpGeq32F_0(v) case OpGeq32U: return rewriteValue386_OpGeq32U_0(v) case OpGeq64F: return rewriteValue386_OpGeq64F_0(v) case OpGeq8: return rewriteValue386_OpGeq8_0(v) case OpGeq8U: return rewriteValue386_OpGeq8U_0(v) case OpGetCallerPC: return rewriteValue386_OpGetCallerPC_0(v) case OpGetCallerSP: return rewriteValue386_OpGetCallerSP_0(v) case OpGetClosurePtr: return rewriteValue386_OpGetClosurePtr_0(v) case OpGetG: return rewriteValue386_OpGetG_0(v) case OpGreater16: return rewriteValue386_OpGreater16_0(v) case OpGreater16U: return rewriteValue386_OpGreater16U_0(v) case OpGreater32: return rewriteValue386_OpGreater32_0(v) case OpGreater32F: return rewriteValue386_OpGreater32F_0(v) case OpGreater32U: return rewriteValue386_OpGreater32U_0(v) case OpGreater64F: return rewriteValue386_OpGreater64F_0(v) case OpGreater8: return rewriteValue386_OpGreater8_0(v) case OpGreater8U: return rewriteValue386_OpGreater8U_0(v) case OpHmul32: return rewriteValue386_OpHmul32_0(v) case OpHmul32u: return rewriteValue386_OpHmul32u_0(v) case OpInterCall: return rewriteValue386_OpInterCall_0(v) case OpIsInBounds: return rewriteValue386_OpIsInBounds_0(v) case OpIsNonNil: return rewriteValue386_OpIsNonNil_0(v) case OpIsSliceInBounds: return rewriteValue386_OpIsSliceInBounds_0(v) case OpLeq16: return rewriteValue386_OpLeq16_0(v) case OpLeq16U: return rewriteValue386_OpLeq16U_0(v) case OpLeq32: return rewriteValue386_OpLeq32_0(v) case OpLeq32F: return rewriteValue386_OpLeq32F_0(v) case OpLeq32U: return rewriteValue386_OpLeq32U_0(v) case OpLeq64F: return rewriteValue386_OpLeq64F_0(v) case OpLeq8: return rewriteValue386_OpLeq8_0(v) case OpLeq8U: return rewriteValue386_OpLeq8U_0(v) case OpLess16: return rewriteValue386_OpLess16_0(v) case OpLess16U: return rewriteValue386_OpLess16U_0(v) case OpLess32: return rewriteValue386_OpLess32_0(v) case OpLess32F: return rewriteValue386_OpLess32F_0(v) case OpLess32U: return rewriteValue386_OpLess32U_0(v) case OpLess64F: return rewriteValue386_OpLess64F_0(v) case OpLess8: return rewriteValue386_OpLess8_0(v) case OpLess8U: return rewriteValue386_OpLess8U_0(v) case OpLoad: return rewriteValue386_OpLoad_0(v) case OpLocalAddr: return rewriteValue386_OpLocalAddr_0(v) case OpLsh16x16: return rewriteValue386_OpLsh16x16_0(v) case OpLsh16x32: return rewriteValue386_OpLsh16x32_0(v) case OpLsh16x64: return rewriteValue386_OpLsh16x64_0(v) case OpLsh16x8: return rewriteValue386_OpLsh16x8_0(v) case OpLsh32x16: return rewriteValue386_OpLsh32x16_0(v) case OpLsh32x32: return rewriteValue386_OpLsh32x32_0(v) case OpLsh32x64: return rewriteValue386_OpLsh32x64_0(v) case OpLsh32x8: return rewriteValue386_OpLsh32x8_0(v) case OpLsh8x16: return rewriteValue386_OpLsh8x16_0(v) case OpLsh8x32: return rewriteValue386_OpLsh8x32_0(v) case OpLsh8x64: return rewriteValue386_OpLsh8x64_0(v) case OpLsh8x8: return rewriteValue386_OpLsh8x8_0(v) case OpMod16: return rewriteValue386_OpMod16_0(v) case OpMod16u: return rewriteValue386_OpMod16u_0(v) case OpMod32: return rewriteValue386_OpMod32_0(v) case OpMod32u: return rewriteValue386_OpMod32u_0(v) case OpMod8: return rewriteValue386_OpMod8_0(v) case OpMod8u: return rewriteValue386_OpMod8u_0(v) case OpMove: return rewriteValue386_OpMove_0(v) || rewriteValue386_OpMove_10(v) case OpMul16: return rewriteValue386_OpMul16_0(v) case OpMul32: return rewriteValue386_OpMul32_0(v) case OpMul32F: return rewriteValue386_OpMul32F_0(v) case OpMul32uhilo: return rewriteValue386_OpMul32uhilo_0(v) case OpMul64F: return rewriteValue386_OpMul64F_0(v) case OpMul8: return rewriteValue386_OpMul8_0(v) case OpNeg16: return rewriteValue386_OpNeg16_0(v) case OpNeg32: return rewriteValue386_OpNeg32_0(v) case OpNeg32F: return rewriteValue386_OpNeg32F_0(v) case OpNeg64F: return rewriteValue386_OpNeg64F_0(v) case OpNeg8: return rewriteValue386_OpNeg8_0(v) case OpNeq16: return rewriteValue386_OpNeq16_0(v) case OpNeq32: return rewriteValue386_OpNeq32_0(v) case OpNeq32F: return rewriteValue386_OpNeq32F_0(v) case OpNeq64F: return rewriteValue386_OpNeq64F_0(v) case OpNeq8: return rewriteValue386_OpNeq8_0(v) case OpNeqB: return rewriteValue386_OpNeqB_0(v) case OpNeqPtr: return rewriteValue386_OpNeqPtr_0(v) case OpNilCheck: return rewriteValue386_OpNilCheck_0(v) case OpNot: return rewriteValue386_OpNot_0(v) case OpOffPtr: return rewriteValue386_OpOffPtr_0(v) case OpOr16: return rewriteValue386_OpOr16_0(v) case OpOr32: return rewriteValue386_OpOr32_0(v) case OpOr8: return rewriteValue386_OpOr8_0(v) case OpOrB: return rewriteValue386_OpOrB_0(v) case OpRound32F: return rewriteValue386_OpRound32F_0(v) case OpRound64F: return rewriteValue386_OpRound64F_0(v) case OpRsh16Ux16: return rewriteValue386_OpRsh16Ux16_0(v) case OpRsh16Ux32: return rewriteValue386_OpRsh16Ux32_0(v) case OpRsh16Ux64: return rewriteValue386_OpRsh16Ux64_0(v) case OpRsh16Ux8: return rewriteValue386_OpRsh16Ux8_0(v) case OpRsh16x16: return rewriteValue386_OpRsh16x16_0(v) case OpRsh16x32: return rewriteValue386_OpRsh16x32_0(v) case OpRsh16x64: return rewriteValue386_OpRsh16x64_0(v) case OpRsh16x8: return rewriteValue386_OpRsh16x8_0(v) case OpRsh32Ux16: return rewriteValue386_OpRsh32Ux16_0(v) case OpRsh32Ux32: return rewriteValue386_OpRsh32Ux32_0(v) case OpRsh32Ux64: return rewriteValue386_OpRsh32Ux64_0(v) case OpRsh32Ux8: return rewriteValue386_OpRsh32Ux8_0(v) case OpRsh32x16: return rewriteValue386_OpRsh32x16_0(v) case OpRsh32x32: return rewriteValue386_OpRsh32x32_0(v) case OpRsh32x64: return rewriteValue386_OpRsh32x64_0(v) case OpRsh32x8: return rewriteValue386_OpRsh32x8_0(v) case OpRsh8Ux16: return rewriteValue386_OpRsh8Ux16_0(v) case OpRsh8Ux32: return rewriteValue386_OpRsh8Ux32_0(v) case OpRsh8Ux64: return rewriteValue386_OpRsh8Ux64_0(v) case OpRsh8Ux8: return rewriteValue386_OpRsh8Ux8_0(v) case OpRsh8x16: return rewriteValue386_OpRsh8x16_0(v) case OpRsh8x32: return rewriteValue386_OpRsh8x32_0(v) case OpRsh8x64: return rewriteValue386_OpRsh8x64_0(v) case OpRsh8x8: return rewriteValue386_OpRsh8x8_0(v) case OpSelect0: return rewriteValue386_OpSelect0_0(v) case OpSelect1: return rewriteValue386_OpSelect1_0(v) case OpSignExt16to32: return rewriteValue386_OpSignExt16to32_0(v) case OpSignExt8to16: return rewriteValue386_OpSignExt8to16_0(v) case OpSignExt8to32: return rewriteValue386_OpSignExt8to32_0(v) case OpSignmask: return rewriteValue386_OpSignmask_0(v) case OpSlicemask: return rewriteValue386_OpSlicemask_0(v) case OpSqrt: return rewriteValue386_OpSqrt_0(v) case OpStaticCall: return rewriteValue386_OpStaticCall_0(v) case OpStore: return rewriteValue386_OpStore_0(v) case OpSub16: return rewriteValue386_OpSub16_0(v) case OpSub32: return rewriteValue386_OpSub32_0(v) case OpSub32F: return rewriteValue386_OpSub32F_0(v) case OpSub32carry: return rewriteValue386_OpSub32carry_0(v) case OpSub32withcarry: return rewriteValue386_OpSub32withcarry_0(v) case OpSub64F: return rewriteValue386_OpSub64F_0(v) case OpSub8: return rewriteValue386_OpSub8_0(v) case OpSubPtr: return rewriteValue386_OpSubPtr_0(v) case OpTrunc16to8: return rewriteValue386_OpTrunc16to8_0(v) case OpTrunc32to16: return rewriteValue386_OpTrunc32to16_0(v) case OpTrunc32to8: return rewriteValue386_OpTrunc32to8_0(v) case OpWB: return rewriteValue386_OpWB_0(v) case OpXor16: return rewriteValue386_OpXor16_0(v) case OpXor32: return rewriteValue386_OpXor32_0(v) case OpXor8: return rewriteValue386_OpXor8_0(v) case OpZero: return rewriteValue386_OpZero_0(v) || rewriteValue386_OpZero_10(v) case OpZeroExt16to32: return rewriteValue386_OpZeroExt16to32_0(v) case OpZeroExt8to16: return rewriteValue386_OpZeroExt8to16_0(v) case OpZeroExt8to32: return rewriteValue386_OpZeroExt8to32_0(v) case OpZeromask: return rewriteValue386_OpZeromask_0(v) } return false } func rewriteValue386_Op386ADCL_0(v *Value) bool { // match: (ADCL x (MOVLconst [c]) f) // cond: // result: (ADCLconst [c] x f) for { _ = v.Args[2] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt f := v.Args[2] v.reset(Op386ADCLconst) v.AuxInt = c v.AddArg(x) v.AddArg(f) return true } // match: (ADCL (MOVLconst [c]) x f) // cond: // result: (ADCLconst [c] x f) for { _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] f := v.Args[2] v.reset(Op386ADCLconst) v.AuxInt = c v.AddArg(x) v.AddArg(f) return true } // match: (ADCL (MOVLconst [c]) x f) // cond: // result: (ADCLconst [c] x f) for { _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] f := v.Args[2] v.reset(Op386ADCLconst) v.AuxInt = c v.AddArg(x) v.AddArg(f) return true } // match: (ADCL x (MOVLconst [c]) f) // cond: // result: (ADCLconst [c] x f) for { _ = v.Args[2] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt f := v.Args[2] v.reset(Op386ADCLconst) v.AuxInt = c v.AddArg(x) v.AddArg(f) return true } return false } func rewriteValue386_Op386ADDL_0(v *Value) bool { // match: (ADDL x (MOVLconst [c])) // cond: // result: (ADDLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386ADDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (MOVLconst [c]) x) // cond: // result: (ADDLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386ADDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHLLconst [c] x) (SHRLconst [d] x)) // cond: d == 32-c // result: (ROLLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(Op386ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHRLconst [d] x) (SHLLconst [c] x)) // cond: d == 32-c // result: (ROLLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(Op386ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHLLconst x [c]) (SHRWconst x [d])) // cond: c < 16 && d == 16-c && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 16 && d == 16-c && t.Size() == 2) { break } v.reset(Op386ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHRWconst x [d]) (SHLLconst x [c])) // cond: c < 16 && d == 16-c && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 16 && d == 16-c && t.Size() == 2) { break } v.reset(Op386ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHLLconst x [c]) (SHRBconst x [d])) // cond: c < 8 && d == 8-c && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRBconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 8 && d == 8-c && t.Size() == 1) { break } v.reset(Op386ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHRBconst x [d]) (SHLLconst x [c])) // cond: c < 8 && d == 8-c && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRBconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 8 && d == 8-c && t.Size() == 1) { break } v.reset(Op386ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL x (SHLLconst [3] y)) // cond: // result: (LEAL8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 3 { break } y := v_1.Args[0] v.reset(Op386LEAL8) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (SHLLconst [3] y) x) // cond: // result: (LEAL8 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 3 { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386LEAL8) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386ADDL_10(v *Value) bool { // match: (ADDL x (SHLLconst [2] y)) // cond: // result: (LEAL4 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(Op386LEAL4) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (SHLLconst [2] y) x) // cond: // result: (LEAL4 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 2 { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386LEAL4) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (SHLLconst [1] y)) // cond: // result: (LEAL2 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(Op386LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (SHLLconst [1] y) x) // cond: // result: (LEAL2 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 1 { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (ADDL y y)) // cond: // result: (LEAL2 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDL { break } _ = v_1.Args[1] y := v_1.Args[0] if y != v_1.Args[1] { break } v.reset(Op386LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (ADDL y y) x) // cond: // result: (LEAL2 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] y := v_0.Args[0] if y != v_0.Args[1] { break } x := v.Args[1] v.reset(Op386LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (ADDL x y)) // cond: // result: (LEAL2 y x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } y := v_1.Args[1] v.reset(Op386LEAL2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDL x (ADDL y x)) // cond: // result: (LEAL2 y x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDL { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(Op386LEAL2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDL (ADDL x y) x) // cond: // result: (LEAL2 y x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if x != v.Args[1] { break } v.reset(Op386LEAL2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDL (ADDL y x) x) // cond: // result: (LEAL2 y x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] y := v_0.Args[0] x := v_0.Args[1] if x != v.Args[1] { break } v.reset(Op386LEAL2) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValue386_Op386ADDL_20(v *Value) bool { // match: (ADDL (ADDLconst [c] x) y) // cond: // result: (LEAL1 [c] x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } c := v_0.AuxInt x := v_0.Args[0] y := v.Args[1] v.reset(Op386LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDL y (ADDLconst [c] x)) // cond: // result: (LEAL1 [c] x y) for { _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } c := v_1.AuxInt x := v_1.Args[0] v.reset(Op386LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } c := v_1.AuxInt s := v_1.Aux y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (LEAL [c] {s} y) x) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } c := v_0.AuxInt s := v_0.Aux y := v_0.Args[0] x := v.Args[1] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ADDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ADDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ADDLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ADDLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (ADDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ADDLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ADDLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (ADDL x (NEGL y)) // cond: // result: (SUBL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386NEGL { break } y := v_1.Args[0] v.reset(Op386SUBL) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (NEGL y) x) // cond: // result: (SUBL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386NEGL { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386SUBL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386ADDLcarry_0(v *Value) bool { // match: (ADDLcarry x (MOVLconst [c])) // cond: // result: (ADDLconstcarry [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386ADDLconstcarry) v.AuxInt = c v.AddArg(x) return true } // match: (ADDLcarry (MOVLconst [c]) x) // cond: // result: (ADDLconstcarry [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386ADDLconstcarry) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValue386_Op386ADDLconst_0(v *Value) bool { // match: (ADDLconst [c] (ADDL x y)) // cond: // result: (LEAL1 [c] x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] v.reset(Op386LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(c+d) // result: (LEAL [c+d] {s} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } d := v_0.AuxInt s := v_0.Aux x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(Op386LEAL) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } d := v_0.AuxInt s := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(c + d)) { break } v.reset(Op386LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL2 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386LEAL2 { break } d := v_0.AuxInt s := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(c + d)) { break } v.reset(Op386LEAL2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL4 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } d := v_0.AuxInt s := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(c + d)) { break } v.reset(Op386LEAL4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL8 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386LEAL8 { break } d := v_0.AuxInt s := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(c + d)) { break } v.reset(Op386LEAL8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] x) // cond: int32(c)==0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [int64(int32(c+d))]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = int64(int32(c + d)) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // cond: // result: (ADDLconst [int64(int32(c+d))] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ADDLconst) v.AuxInt = int64(int32(c + d)) v.AddArg(x) return true } return false } func rewriteValue386_Op386ADDLconstmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386ADDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDLconstmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386ADDLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ADDLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem) // cond: ValAndOff(valoff1).canAdd(off2*4) // result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2 * 4)) { break } v.reset(Op386ADDLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2 * 4) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ADDLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDLload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ADDLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL4 { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[1] ptr := v_1.Args[0] idx := v_1.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386ADDLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDLloadidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem) // cond: is32Bit(off1+off2) // result: (ADDLloadidx4 [off1+off2] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ADDLloadidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ADDLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem) // cond: is32Bit(off1+off2*4) // result: (ADDLloadidx4 [off1+off2*4] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] base := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386ADDLconst { break } off2 := v_2.AuxInt idx := v_2.Args[0] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386ADDLloadidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ADDLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDLmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDLmodify [off1] {sym} (ADDLconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ADDLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDLmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem) // cond: is32Bit(off1+off2) // result: (ADDLmodifyidx4 [off1+off2] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ADDLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem) // cond: is32Bit(off1+off2*4) // result: (ADDLmodifyidx4 [off1+off2*4] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386ADDLmodifyidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem) // cond: validValAndOff(c,off) // result: (ADDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386MOVLconst { break } c := v_2.AuxInt mem := v.Args[3] if !(validValAndOff(c, off)) { break } v.reset(Op386ADDLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDSD_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSDload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386ADDSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDSD l:(MOVSDload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVSDload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386ADDSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDSDload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDSDload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ADDSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDSS_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSSload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386ADDSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDSS l:(MOVSSload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVSSload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386ADDSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ADDSSload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ADDSSload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ADDSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ADDSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ANDL_0(v *Value) bool { // match: (ANDL x (MOVLconst [c])) // cond: // result: (ANDLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386ANDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ANDL (MOVLconst [c]) x) // cond: // result: (ANDLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386ANDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ANDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ANDL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ANDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ANDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ANDLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ANDLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (ANDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ANDLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ANDLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (ANDL x x) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] if x != v.Args[1] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386ANDLconst_0(v *Value) bool { // match: (ANDLconst [c] (ANDLconst [d] x)) // cond: // result: (ANDLconst [c & d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ANDLconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDLconst [c] _) // cond: int32(c)==0 // result: (MOVLconst [0]) for { c := v.AuxInt if !(int32(c) == 0) { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (ANDLconst [c] x) // cond: int32(c)==-1 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == -1) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDLconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [c&d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = c & d return true } return false } func rewriteValue386_Op386ANDLconstmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ANDLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386ANDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ANDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ANDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ANDLconstmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ANDLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386ANDLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ANDLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem) // cond: ValAndOff(valoff1).canAdd(off2*4) // result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2 * 4)) { break } v.reset(Op386ANDLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2 * 4) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ANDLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ANDLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ANDLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ANDLload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ANDLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ANDLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ANDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ANDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ANDLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ANDLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ANDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL4 { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[1] ptr := v_1.Args[0] idx := v_1.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386ANDLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ANDLloadidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ANDLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem) // cond: is32Bit(off1+off2) // result: (ANDLloadidx4 [off1+off2] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ANDLloadidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ANDLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem) // cond: is32Bit(off1+off2*4) // result: (ANDLloadidx4 [off1+off2*4] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] base := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386ADDLconst { break } off2 := v_2.AuxInt idx := v_2.Args[0] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386ANDLloadidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ANDLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ANDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ANDLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ANDLmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ANDLmodify [off1] {sym} (ADDLconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ANDLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ANDLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ANDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ANDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ANDLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ANDLmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ANDLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem) // cond: is32Bit(off1+off2) // result: (ANDLmodifyidx4 [off1+off2] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ANDLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ANDLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem) // cond: is32Bit(off1+off2*4) // result: (ANDLmodifyidx4 [off1+off2*4] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386ANDLmodifyidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ANDLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ANDLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ANDLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ANDLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem) // cond: validValAndOff(c,off) // result: (ANDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386MOVLconst { break } c := v_2.AuxInt mem := v.Args[3] if !(validValAndOff(c, off)) { break } v.reset(Op386ANDLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386CMPB_0(v *Value) bool { b := v.Block _ = b // match: (CMPB x (MOVLconst [c])) // cond: // result: (CMPBconst x [int64(int8(c))]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386CMPBconst) v.AuxInt = int64(int8(c)) v.AddArg(x) return true } // match: (CMPB (MOVLconst [c]) x) // cond: // result: (InvertFlags (CMPBconst x [int64(int8(c))])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386InvertFlags) v0 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v0.AuxInt = int64(int8(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPB l:(MOVBload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (CMPBload {sym} [off] ptr x mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVBload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386CMPBload) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (CMPB x l:(MOVBload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (InvertFlags (CMPBload {sym} [off] ptr x mem)) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVBload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386InvertFlags) v0 := b.NewValue0(v.Pos, Op386CMPBload, types.TypeFlags) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(x) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValue386_Op386CMPBconst_0(v *Value) bool { b := v.Block _ = b // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)==int8(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int8(x) == int8(y)) { break } v.reset(Op386FlagEQ) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)uint8(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int8(x) < int8(y) && uint8(x) > uint8(y)) { break } v.reset(Op386FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>int8(y) && uint8(x) int8(y) && uint8(x) < uint8(y)) { break } v.reset(Op386FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>int8(y) && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int8(x) > int8(y) && uint8(x) > uint8(y)) { break } v.reset(Op386FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < int8(n) // result: (FlagLT_ULT) for { n := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } m := v_0.AuxInt if !(0 <= int8(m) && int8(m) < int8(n)) { break } v.reset(Op386FlagLT_ULT) return true } // match: (CMPBconst l:(ANDL x y) [0]) // cond: l.Uses==1 // result: (TESTB x y) for { if v.AuxInt != 0 { break } l := v.Args[0] if l.Op != Op386ANDL { break } _ = l.Args[1] x := l.Args[0] y := l.Args[1] if !(l.Uses == 1) { break } v.reset(Op386TESTB) v.AddArg(x) v.AddArg(y) return true } // match: (CMPBconst l:(ANDLconst [c] x) [0]) // cond: l.Uses==1 // result: (TESTBconst [int64(int8(c))] x) for { if v.AuxInt != 0 { break } l := v.Args[0] if l.Op != Op386ANDLconst { break } c := l.AuxInt x := l.Args[0] if !(l.Uses == 1) { break } v.reset(Op386TESTBconst) v.AuxInt = int64(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // cond: // result: (TESTB x x) for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(Op386TESTB) v.AddArg(x) v.AddArg(x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(c,off)] ptr mem) for { c := v.AuxInt l := v.Args[0] if l.Op != Op386MOVBload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(v.Pos, Op386CMPBconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(c, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386CMPBload_0(v *Value) bool { // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // cond: validValAndOff(int64(int8(c)),off) // result: (CMPBconstload {sym} [makeValAndOff(int64(int8(c)),off)] ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt mem := v.Args[2] if !(validValAndOff(int64(int8(c)), off)) { break } v.reset(Op386CMPBconstload) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386CMPL_0(v *Value) bool { b := v.Block _ = b // match: (CMPL x (MOVLconst [c])) // cond: // result: (CMPLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386CMPLconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // cond: // result: (InvertFlags (CMPLconst x [c])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386InvertFlags) v0 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386CMPLload) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386InvertFlags) v0 := b.NewValue0(v.Pos, Op386CMPLload, types.TypeFlags) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(x) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValue386_Op386CMPLconst_0(v *Value) bool { // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(Op386FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)uint32(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int32(x) < int32(y) && uint32(x) > uint32(y)) { break } v.reset(Op386FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)>int32(y) && uint32(x) int32(y) && uint32(x) < uint32(y)) { break } v.reset(Op386FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)>int32(y) && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int32(x) > int32(y) && uint32(x) > uint32(y)) { break } v.reset(Op386FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint16(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int16(x) < int16(y) && uint16(x) > uint16(y)) { break } v.reset(Op386FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>int16(y) && uint16(x) int16(y) && uint16(x) < uint16(y)) { break } v.reset(Op386FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>int16(y) && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } x := v_0.AuxInt if !(int16(x) > int16(y) && uint16(x) > uint16(y)) { break } v.reset(Op386FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < int16(n) // result: (FlagLT_ULT) for { n := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } m := v_0.AuxInt if !(0 <= int16(m) && int16(m) < int16(n)) { break } v.reset(Op386FlagLT_ULT) return true } // match: (CMPWconst l:(ANDL x y) [0]) // cond: l.Uses==1 // result: (TESTW x y) for { if v.AuxInt != 0 { break } l := v.Args[0] if l.Op != Op386ANDL { break } _ = l.Args[1] x := l.Args[0] y := l.Args[1] if !(l.Uses == 1) { break } v.reset(Op386TESTW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWconst l:(ANDLconst [c] x) [0]) // cond: l.Uses==1 // result: (TESTWconst [int64(int16(c))] x) for { if v.AuxInt != 0 { break } l := v.Args[0] if l.Op != Op386ANDLconst { break } c := l.AuxInt x := l.Args[0] if !(l.Uses == 1) { break } v.reset(Op386TESTWconst) v.AuxInt = int64(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // cond: // result: (TESTW x x) for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(Op386TESTW) v.AddArg(x) v.AddArg(x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(c,off)] ptr mem) for { c := v.AuxInt l := v.Args[0] if l.Op != Op386MOVWload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(v.Pos, Op386CMPWconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(c, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386CMPWload_0(v *Value) bool { // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // cond: validValAndOff(int64(int16(c)),off) // result: (CMPWconstload {sym} [makeValAndOff(int64(int16(c)),off)] ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt mem := v.Args[2] if !(validValAndOff(int64(int16(c)), off)) { break } v.reset(Op386CMPWconstload) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386DIVSD_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSDload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386DIVSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386DIVSDload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (DIVSDload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386DIVSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386DIVSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386DIVSS_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSSload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386DIVSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386DIVSSload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (DIVSSload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386DIVSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386DIVSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386LEAL_0(v *Value) bool { // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(c+d) // result: (LEAL [c+d] {s} x) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(Op386LEAL) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL [off1] {sym1} (LEAL [off2] {sym2} x)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAL [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386LEAL) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) return true } // match: (LEAL [off1] {sym1} (LEAL1 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386LEAL1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAL [off1] {sym1} (LEAL2 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != Op386LEAL2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386LEAL2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAL [off1] {sym1} (LEAL4 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386LEAL4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAL [off1] {sym1} (LEAL8 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != Op386LEAL8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386LEAL8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386LEAL1_0(v *Value) bool { // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] y := v.Args[1] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} y (ADDLconst [d] x)) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt x := v_1.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // cond: // result: (LEAL2 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(Op386LEAL2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} (SHLLconst [1] y) x) // cond: // result: (LEAL2 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 1 { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386LEAL2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // cond: // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(Op386LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} (SHLLconst [2] y) x) // cond: // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 2 { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // cond: // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 3 { break } y := v_1.Args[0] v.reset(Op386LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} (SHLLconst [3] y) x) // cond: // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 3 { break } y := v_0.Args[0] x := v.Args[1] v.reset(Op386LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [off1] {sym1} (LEAL [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] y := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [off1] {sym1} y (LEAL [off2] {sym2} x)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux x := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(Op386LEAL1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386LEAL2_0(v *Value) bool { // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] y := v.Args[1] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(Op386LEAL2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+2*d) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+2*d) && y.Op != OpSB) { break } v.reset(Op386LEAL2) v.AuxInt = c + 2*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // cond: // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(Op386LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // cond: // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(Op386LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [off1] {sym1} (LEAL [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] y := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(Op386LEAL2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386LEAL4_0(v *Value) bool { // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] y := v.Args[1] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(Op386LEAL4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+4*d) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+4*d) && y.Op != OpSB) { break } v.reset(Op386LEAL4) v.AuxInt = c + 4*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // cond: // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(Op386LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [off1] {sym1} (LEAL [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] y := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(Op386LEAL4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386LEAL8_0(v *Value) bool { // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] y := v.Args[1] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(Op386LEAL8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+8*d) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+8*d) && y.Op != OpSB) { break } v.reset(Op386LEAL8) v.AuxInt = c + 8*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL8 [off1] {sym1} (LEAL [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] y := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(Op386LEAL8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386MOVBLSX_0(v *Value) bool { b := v.Block _ = b // match: (MOVBLSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBLSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != Op386MOVBload { break } off := x.AuxInt sym := x.Aux _ = x.Args[1] ptr := x.Args[0] mem := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVBLSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBLSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(Op386ANDLconst) v.AuxInt = c & 0x7f v.AddArg(x) return true } return false } func rewriteValue386_Op386MOVBLSXload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVBLSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBLSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVBstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(Op386MOVBLSX) v.AddArg(x) return true } // match: (MOVBLSXload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVBLSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVBLSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBLZX_0(v *Value) bool { b := v.Block _ = b // match: (MOVBLZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != Op386MOVBload { break } off := x.AuxInt sym := x.Aux _ = x.Args[1] ptr := x.Args[0] mem := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBLZX x:(MOVBloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != Op386MOVBloadidx1 { break } off := x.AuxInt sym := x.Aux _ = x.Args[2] ptr := x.Args[0] idx := x.Args[1] mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVBloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVBLZX (ANDLconst [c] x)) // cond: // result: (ANDLconst [c & 0xff] x) for { v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ANDLconst) v.AuxInt = c & 0xff v.AddArg(x) return true } return false } func rewriteValue386_Op386MOVBload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBLZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVBstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(Op386MOVBLZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVBloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (ADDL ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVBloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVBloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(read8(sym, off))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB { break } if !(symIsRO(sym)) { break } v.reset(Op386MOVLconst) v.AuxInt = int64(read8(sym, off)) return true } return false } func rewriteValue386_Op386MOVBloadidx1_0(v *Value) bool { // match: (MOVBloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVBloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [c] {sym} idx (ADDLconst [d] ptr) mem) // cond: // result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt ptr := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVBloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVBloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [c] {sym} (ADDLconst [d] idx) ptr mem) // cond: // result: (MOVBloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] mem := v.Args[2] v.reset(Op386MOVBloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBstore_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVBstore [off] {sym} ptr (MOVBLSX x) mem) // cond: // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVBLSX { break } x := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBLZX x) mem) // cond: // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVBLZX { break } x := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt mem := v.Args[2] if !(validOff(off)) { break } v.reset(Op386MOVBstoreconst) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVBstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} (ADDL ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVBstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVBstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRWconst { break } if v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != Op386MOVBstore { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } if w != x.Args[1] { break } mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } if v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != Op386MOVBstore { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } if w != x.Args[1] { break } mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore {s} [i+1] p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != Op386MOVBstore { break } if x.AuxInt != i+1 { break } if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != Op386SHRWconst { break } if x_1.AuxInt != 8 { break } if w != x_1.Args[0] { break } mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBstore_10(v *Value) bool { // match: (MOVBstore [i] {s} p w x:(MOVBstore {s} [i+1] p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != Op386MOVBstore { break } if x.AuxInt != i+1 { break } if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != Op386SHRLconst { break } if x_1.AuxInt != 8 { break } if w != x_1.Args[0] { break } mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != Op386MOVBstore { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-8 { break } if w != w0.Args[0] { break } mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBstoreconst_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVBstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(Op386MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconst [x] {sym} (ADDL ptr idx) mem) // cond: // result: (MOVBstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] v.reset(Op386MOVBstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != Op386MOVBstoreconst { break } a := x.AuxInt if x.Aux != s { break } _ = x.Args[1] if p != x.Args[0] { break } mem := x.Args[1] if !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(Op386MOVWstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBstoreconstidx1_0(v *Value) bool { // match: (MOVBstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem) // cond: // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem) // cond: // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } c := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconstidx1 [c] {s} p i x:(MOVBstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p i mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != Op386MOVBstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } if i != x.Args[1] { break } mem := x.Args[2] if !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(Op386MOVWstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(i) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBstoreidx1_0(v *Value) bool { // match: (MOVBstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVBstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [c] {sym} idx (ADDLconst [d] ptr) val mem) // cond: // result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt ptr := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVBstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVBstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [c] {sym} (ADDLconst [d] idx) ptr val mem) // cond: // result: (MOVBstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVBstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRWconst { break } if v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRWconst { break } if v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBstoreidx1_10(v *Value) bool { // match: (MOVBstoreidx1 [i] {s} idx p (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRWconst { break } if v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} idx p (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRWconst { break } if v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i+1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } x_2 := x.Args[2] if x_2.Op != Op386SHRLconst { break } if x_2.AuxInt != 8 { break } if w != x_2.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i+1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } x_2 := x.Args[2] if x_2.Op != Op386SHRLconst { break } if x_2.AuxInt != 8 { break } if w != x_2.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] w := v.Args[2] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i+1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } x_2 := x.Args[2] if x_2.Op != Op386SHRLconst { break } if x_2.AuxInt != 8 { break } if w != x_2.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] w := v.Args[2] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i+1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } x_2 := x.Args[2] if x_2.Op != Op386SHRLconst { break } if x_2.AuxInt != 8 { break } if w != x_2.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i+1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } x_2 := x.Args[2] if x_2.Op != Op386SHRWconst { break } if x_2.AuxInt != 8 { break } if w != x_2.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i+1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } x_2 := x.Args[2] if x_2.Op != Op386SHRWconst { break } if x_2.AuxInt != 8 { break } if w != x_2.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] w := v.Args[2] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i+1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } x_2 := x.Args[2] if x_2.Op != Op386SHRWconst { break } if x_2.AuxInt != 8 { break } if w != x_2.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] w := v.Args[2] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i+1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } x_2 := x.Args[2] if x_2.Op != Op386SHRWconst { break } if x_2.AuxInt != 8 { break } if w != x_2.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVBstoreidx1_20(v *Value) bool { // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-8 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} idx p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-8 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-8 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} idx p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { break } if x.AuxInt != i-1 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-8 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVLloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off] {sym} (ADDL ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVLloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVLloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(int32(read32(sym, off, config.BigEndian)))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB { break } if !(symIsRO(sym)) { break } v.reset(Op386MOVLconst) v.AuxInt = int64(int32(read32(sym, off, config.BigEndian))) return true } return false } func rewriteValue386_Op386MOVLloadidx1_0(v *Value) bool { // match: (MOVLloadidx1 [c] {sym} ptr (SHLLconst [2] idx) mem) // cond: // result: (MOVLloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 2 { break } idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (SHLLconst [2] idx) ptr mem) // cond: // result: (MOVLloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 2 { break } idx := v_0.Args[0] ptr := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} idx (ADDLconst [d] ptr) mem) // cond: // result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt ptr := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (ADDLconst [d] idx) ptr mem) // cond: // result: (MOVLloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLloadidx4_0(v *Value) bool { // match: (MOVLloadidx4 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVLloadidx4 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLloadidx4) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx4 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVLloadidx4 [int64(int32(c+4*d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLloadidx4) v.AuxInt = int64(int32(c + 4*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstore_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVLstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt mem := v.Args[2] if !(validOff(off)) { break } v.reset(Op386MOVLstoreconst) v.AuxInt = makeValAndOff(int64(int32(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVLstoreidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} (ADDL ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVLstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ADDLload { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] { break } mem := y.Args[2] if mem != v.Args[2] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ANDLload { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] { break } mem := y.Args[2] if mem != v.Args[2] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ORLload { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] { break } mem := y.Args[2] if mem != v.Args[2] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386XORLload { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] { break } mem := y.Args[2] if mem != v.Args[2] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstore_10(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ADDL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] x := y.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ADDL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386SUBL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] x := y.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386SUBLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ANDL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] x := y.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ANDL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ORL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] x := y.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ORL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386XORL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] x := y.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386XORL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (ADDLconstmodify [makeValAndOff(c,off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ADDLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386ADDLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstore_20(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(ANDLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (ANDLconstmodify [makeValAndOff(c,off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ANDLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386ANDLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (ORLconstmodify [makeValAndOff(c,off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386ORLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386ORLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLconst [c] l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (XORLconstmodify [makeValAndOff(c,off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != Op386XORLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLload { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] { break } mem := l.Args[1] if mem != v.Args[2] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386XORLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstoreconst_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVLstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(Op386MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym1} (LEAL4 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } off := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym} (ADDL ptr idx) mem) // cond: // result: (MOVLstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] v.reset(Op386MOVLstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstoreconstidx1_0(v *Value) bool { // match: (MOVLstoreconstidx1 [c] {sym} ptr (SHLLconst [2] idx) mem) // cond: // result: (MOVLstoreconstidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 2 { break } idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLstoreconstidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem) // cond: // result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem) // cond: // result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } c := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstoreconstidx4_0(v *Value) bool { // match: (MOVLstoreconstidx4 [x] {sym} (ADDLconst [c] ptr) idx mem) // cond: // result: (MOVLstoreconstidx4 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx4 [x] {sym} ptr (ADDLconst [c] idx) mem) // cond: // result: (MOVLstoreconstidx4 [ValAndOff(x).add(4*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } c := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(4 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstoreidx1_0(v *Value) bool { // match: (MOVLstoreidx1 [c] {sym} ptr (SHLLconst [2] idx) val mem) // cond: // result: (MOVLstoreidx4 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 2 { break } idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} (SHLLconst [2] idx) ptr val mem) // cond: // result: (MOVLstoreidx4 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 2 { break } idx := v_0.Args[0] ptr := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} idx (ADDLconst [d] ptr) val mem) // cond: // result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt ptr := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} (ADDLconst [d] idx) ptr val mem) // cond: // result: (MOVLstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstoreidx4_0(v *Value) bool { // match: (MOVLstoreidx4 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVLstoreidx4 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx4) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVLstoreidx4 [int64(int32(c+4*d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVLstoreidx4) v.AuxInt = int64(int32(c + 4*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDLloadidx4 x [off] {sym} ptr idx mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ADDLloadidx4 { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[3] x := y.Args[0] if ptr != y.Args[1] { break } if idx != y.Args[2] { break } mem := y.Args[3] if mem != v.Args[3] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386ADDLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDLloadidx4 x [off] {sym} ptr idx mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ANDLloadidx4 { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[3] x := y.Args[0] if ptr != y.Args[1] { break } if idx != y.Args[2] { break } mem := y.Args[3] if mem != v.Args[3] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386ANDLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORLloadidx4 x [off] {sym} ptr idx mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ORLloadidx4 { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[3] x := y.Args[0] if ptr != y.Args[1] { break } if idx != y.Args[2] { break } mem := y.Args[3] if mem != v.Args[3] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386ORLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORLloadidx4 x [off] {sym} ptr idx mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386XORLloadidx4 { break } if y.AuxInt != off { break } if y.Aux != sym { break } _ = y.Args[3] x := y.Args[0] if ptr != y.Args[1] { break } if idx != y.Args[2] { break } mem := y.Args[3] if mem != v.Args[3] { break } if !(y.Uses == 1 && clobber(y)) { break } v.reset(Op386XORLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ADDL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] x := y.Args[1] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ADDLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ADDL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ADDLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(SUBL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386SUBL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] x := y.Args[1] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386SUBLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ANDL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] x := y.Args[1] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ANDLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVLstoreidx4_10(v *Value) bool { // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ANDL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ANDLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ORL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] x := y.Args[1] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ORLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ORL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386ORLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386XORL { break } _ = y.Args[1] l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] x := y.Args[1] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386XORLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodifyidx4 [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386XORL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(Op386XORLmodifyidx4) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ADDLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (ADDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ADDLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386ADDLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ANDLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (ANDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ANDLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386ANDLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(ORLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (ORLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386ORLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386ORLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreidx4 {sym} [off] ptr idx y:(XORLconst [c] l:(MOVLloadidx4 [off] {sym} ptr idx mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) && validValAndOff(c,off) // result: (XORLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] y := v.Args[2] if y.Op != Op386XORLconst { break } c := y.AuxInt l := y.Args[0] if l.Op != Op386MOVLloadidx4 { break } if l.AuxInt != off { break } if l.Aux != sym { break } _ = l.Args[2] if ptr != l.Args[0] { break } if idx != l.Args[1] { break } mem := l.Args[2] if mem != v.Args[3] { break } if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l) && validValAndOff(c, off)) { break } v.reset(Op386XORLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSDconst_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config typ := &b.Func.Config.Types _ = typ // match: (MOVSDconst [c]) // cond: config.ctxt.Flag_shared // result: (MOVSDconst2 (MOVSDconst1 [c])) for { c := v.AuxInt if !(config.ctxt.Flag_shared) { break } v.reset(Op386MOVSDconst2) v0 := b.NewValue0(v.Pos, Op386MOVSDconst1, typ.UInt32) v0.AuxInt = c v.AddArg(v0) return true } return false } func rewriteValue386_Op386MOVSDload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVSDload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSDloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAL8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSDloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off] {sym} (ADDL ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVSDloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVSDloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSDloadidx1_0(v *Value) bool { // match: (MOVSDloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVSDloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVSDloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVSDloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVSDloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSDloadidx8_0(v *Value) bool { // match: (MOVSDloadidx8 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVSDloadidx8 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVSDloadidx8) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx8 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVSDloadidx8 [int64(int32(c+8*d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVSDloadidx8) v.AuxInt = int64(int32(c + 8*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSDstore_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVSDstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVSDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVSDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSDstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAL8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSDstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off] {sym} (ADDL ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVSDstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVSDstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSDstoreidx1_0(v *Value) bool { // match: (MOVSDstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVSDstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSDstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVSDstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSDstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSDstoreidx8_0(v *Value) bool { // match: (MOVSDstoreidx8 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVSDstoreidx8 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSDstoreidx8) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx8 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVSDstoreidx8 [int64(int32(c+8*d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSDstoreidx8) v.AuxInt = int64(int32(c + 8*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSSconst_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config typ := &b.Func.Config.Types _ = typ // match: (MOVSSconst [c]) // cond: config.ctxt.Flag_shared // result: (MOVSSconst2 (MOVSSconst1 [c])) for { c := v.AuxInt if !(config.ctxt.Flag_shared) { break } v.reset(Op386MOVSSconst2) v0 := b.NewValue0(v.Pos, Op386MOVSSconst1, typ.UInt32) v0.AuxInt = c v.AddArg(v0) return true } return false } func rewriteValue386_Op386MOVSSload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVSSload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSSloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSSloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off] {sym} (ADDL ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVSSloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVSSloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSSloadidx1_0(v *Value) bool { // match: (MOVSSloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVSSloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVSSloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVSSloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVSSloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSSloadidx4_0(v *Value) bool { // match: (MOVSSloadidx4 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVSSloadidx4 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVSSloadidx4) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx4 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVSSloadidx4 [int64(int32(c+4*d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVSSloadidx4) v.AuxInt = int64(int32(c + 4*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSSstore_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVSSstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVSSstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVSSstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSSstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAL4 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVSSstoreidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off] {sym} (ADDL ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVSSstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVSSstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSSstoreidx1_0(v *Value) bool { // match: (MOVSSstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVSSstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSSstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVSSstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSSstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVSSstoreidx4_0(v *Value) bool { // match: (MOVSSstoreidx4 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVSSstoreidx4 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSSstoreidx4) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx4 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVSSstoreidx4 [int64(int32(c+4*d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVSSstoreidx4) v.AuxInt = int64(int32(c + 4*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWLSX_0(v *Value) bool { b := v.Block _ = b // match: (MOVWLSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWLSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != Op386MOVWload { break } off := x.AuxInt sym := x.Aux _ = x.Args[1] ptr := x.Args[0] mem := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVWLSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWLSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(Op386ANDLconst) v.AuxInt = c & 0x7fff v.AddArg(x) return true } return false } func rewriteValue386_Op386MOVWLSXload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVWLSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWLSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVWstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(Op386MOVWLSX) v.AddArg(x) return true } // match: (MOVWLSXload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVWLSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVWLSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWLZX_0(v *Value) bool { b := v.Block _ = b // match: (MOVWLZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != Op386MOVWload { break } off := x.AuxInt sym := x.Aux _ = x.Args[1] ptr := x.Args[0] mem := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWLZX x:(MOVWloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != Op386MOVWloadidx1 { break } off := x.AuxInt sym := x.Aux _ = x.Args[2] ptr := x.Args[0] idx := x.Args[1] mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVWLZX x:(MOVWloadidx2 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWloadidx2 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != Op386MOVWloadidx2 { break } off := x.AuxInt sym := x.Aux _ = x.Args[2] ptr := x.Args[0] idx := x.Args[1] mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, Op386MOVWloadidx2, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVWLZX (ANDLconst [c] x)) // cond: // result: (ANDLconst [c & 0xffff] x) for { v_0 := v.Args[0] if v_0.Op != Op386ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ANDLconst) v.AuxInt = c & 0xffff v.AddArg(x) return true } return false } func rewriteValue386_Op386MOVWload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWLZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVWstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(Op386MOVWLZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVWloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAL2 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWloadidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVWloadidx2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (ADDL ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVWloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVWloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(read16(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB { break } if !(symIsRO(sym)) { break } v.reset(Op386MOVLconst) v.AuxInt = int64(read16(sym, off, config.BigEndian)) return true } return false } func rewriteValue386_Op386MOVWloadidx1_0(v *Value) bool { // match: (MOVWloadidx1 [c] {sym} ptr (SHLLconst [1] idx) mem) // cond: // result: (MOVWloadidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWloadidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} (SHLLconst [1] idx) ptr mem) // cond: // result: (MOVWloadidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 1 { break } idx := v_0.Args[0] ptr := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWloadidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} idx (ADDLconst [d] ptr) mem) // cond: // result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt ptr := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} (ADDLconst [d] idx) ptr mem) // cond: // result: (MOVWloadidx1 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWloadidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWloadidx2_0(v *Value) bool { // match: (MOVWloadidx2 [c] {sym} (ADDLconst [d] ptr) idx mem) // cond: // result: (MOVWloadidx2 [int64(int32(c+d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWloadidx2) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx2 [c] {sym} ptr (ADDLconst [d] idx) mem) // cond: // result: (MOVWloadidx2 [int64(int32(c+2*d))] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWloadidx2) v.AuxInt = int64(int32(c + 2*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstore_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVWstore [off] {sym} ptr (MOVWLSX x) mem) // cond: // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVWLSX { break } x := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWLZX x) mem) // cond: // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVWLZX { break } x := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt mem := v.Args[2] if !(validOff(off)) { break } v.reset(Op386MOVWstoreconst) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAL1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAL2 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstoreidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVWstoreidx2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} (ADDL ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVWstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] val := v.Args[1] mem := v.Args[2] if !(ptr.Op != OpSB) { break } v.reset(Op386MOVWstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } if v_1.AuxInt != 16 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != Op386MOVWstore { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } if w != x.Args[1] { break } mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != Op386MOVWstore { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-16 { break } if w != w0.Args[0] { break } mem := x.Args[2] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstoreconst_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVWstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(Op386MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym1} (LEAL1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL1 { break } off := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym1} (LEAL2 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL2 { break } off := v_0.AuxInt sym2 := v_0.Aux _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] if !(canMergeSym(sym1, sym2)) { break } v.reset(Op386MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym} (ADDL ptr idx) mem) // cond: // result: (MOVWstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDL { break } _ = v_0.Args[1] ptr := v_0.Args[0] idx := v_0.Args[1] mem := v.Args[1] v.reset(Op386MOVWstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != Op386MOVWstoreconst { break } a := x.AuxInt if x.Aux != s { break } _ = x.Args[1] if p != x.Args[0] { break } mem := x.Args[1] if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(Op386MOVLstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstoreconstidx1_0(v *Value) bool { // match: (MOVWstoreconstidx1 [c] {sym} ptr (SHLLconst [1] idx) mem) // cond: // result: (MOVWstoreconstidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWstoreconstidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [x] {sym} (ADDLconst [c] ptr) idx mem) // cond: // result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [x] {sym} ptr (ADDLconst [c] idx) mem) // cond: // result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } c := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [c] {s} p i x:(MOVWstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p i mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != Op386MOVWstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } if i != x.Args[1] { break } mem := x.Args[2] if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(Op386MOVLstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(i) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstoreconstidx2_0(v *Value) bool { b := v.Block _ = b // match: (MOVWstoreconstidx2 [x] {sym} (ADDLconst [c] ptr) idx mem) // cond: // result: (MOVWstoreconstidx2 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx2 [x] {sym} ptr (ADDLconst [c] idx) mem) // cond: // result: (MOVWstoreconstidx2 [ValAndOff(x).add(2*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } c := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] v.reset(Op386MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(2 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx2 [c] {s} p i x:(MOVWstoreconstidx2 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p (SHLLconst [1] i) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != Op386MOVWstoreconstidx2 { break } a := x.AuxInt if x.Aux != s { break } _ = x.Args[2] if p != x.Args[0] { break } if i != x.Args[1] { break } mem := x.Args[2] if !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(Op386MOVLstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, Op386SHLLconst, i.Type) v0.AuxInt = 1 v0.AddArg(i) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstoreidx1_0(v *Value) bool { // match: (MOVWstoreidx1 [c] {sym} ptr (SHLLconst [1] idx) val mem) // cond: // result: (MOVWstoreidx2 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } if v_1.AuxInt != 1 { break } idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} (SHLLconst [1] idx) ptr val mem) // cond: // result: (MOVWstoreidx2 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } if v_0.AuxInt != 1 { break } idx := v_0.Args[0] ptr := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} idx (ADDLconst [d] ptr) val mem) // cond: // result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt ptr := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} (ADDLconst [d] idx) ptr val mem) // cond: // result: (MOVWstoreidx1 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx1) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} idx p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} idx p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstoreidx1_10(v *Value) bool { // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-16 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} idx p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-16 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-16 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} idx p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] idx := v.Args[0] p := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx1 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if idx != x.Args[0] { break } if p != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-16 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MOVWstoreidx2_0(v *Value) bool { b := v.Block _ = b // match: (MOVWstoreidx2 [c] {sym} (ADDLconst [d] ptr) idx val mem) // cond: // result: (MOVWstoreidx2 [int64(int32(c+d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx2) v.AuxInt = int64(int32(c + d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [c] {sym} ptr (ADDLconst [d] idx) val mem) // cond: // result: (MOVWstoreidx2 [int64(int32(c+2*d))] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] v.reset(Op386MOVWstoreidx2) v.AuxInt = int64(int32(c + 2*d)) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLLconst [1] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } if v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx2 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } if w != x.Args[2] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, Op386SHLLconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx2 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLLconst [1] idx) w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVWstoreidx2 { break } if x.AuxInt != i-2 { break } if x.Aux != s { break } _ = x.Args[3] if p != x.Args[0] { break } if idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != Op386SHRLconst { break } if w0.AuxInt != j-16 { break } if w != w0.Args[0] { break } mem := x.Args[3] if !(x.Uses == 1 && clobber(x)) { break } v.reset(Op386MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, Op386SHLLconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULL_0(v *Value) bool { // match: (MULL x (MOVLconst [c])) // cond: // result: (MULLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386MULLconst) v.AuxInt = c v.AddArg(x) return true } // match: (MULL (MOVLconst [c]) x) // cond: // result: (MULLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386MULLconst) v.AuxInt = c v.AddArg(x) return true } // match: (MULL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (MULLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386MULLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MULL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (MULLload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386MULLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MULL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (MULLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386MULLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MULL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (MULLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386MULLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULLconst_0(v *Value) bool { b := v.Block _ = b // match: (MULLconst [c] (MULLconst [d] x)) // cond: // result: (MULLconst [int64(int32(c * d))] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MULLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386MULLconst) v.AuxInt = int64(int32(c * d)) v.AddArg(x) return true } // match: (MULLconst [-9] x) // cond: // result: (NEGL (LEAL8 x x)) for { if v.AuxInt != -9 { break } x := v.Args[0] v.reset(Op386NEGL) v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // cond: // result: (NEGL (LEAL4 x x)) for { if v.AuxInt != -5 { break } x := v.Args[0] v.reset(Op386NEGL) v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // cond: // result: (NEGL (LEAL2 x x)) for { if v.AuxInt != -3 { break } x := v.Args[0] v.reset(Op386NEGL) v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // cond: // result: (NEGL x) for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(Op386NEGL) v.AddArg(x) return true } // match: (MULLconst [0] _) // cond: // result: (MOVLconst [0]) for { if v.AuxInt != 0 { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (MULLconst [1] x) // cond: // result: x for { if v.AuxInt != 1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MULLconst [3] x) // cond: // result: (LEAL2 x x) for { if v.AuxInt != 3 { break } x := v.Args[0] v.reset(Op386LEAL2) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [5] x) // cond: // result: (LEAL4 x x) for { if v.AuxInt != 5 { break } x := v.Args[0] v.reset(Op386LEAL4) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [7] x) // cond: // result: (LEAL2 x (LEAL2 x x)) for { if v.AuxInt != 7 { break } x := v.Args[0] v.reset(Op386LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValue386_Op386MULLconst_10(v *Value) bool { b := v.Block _ = b // match: (MULLconst [9] x) // cond: // result: (LEAL8 x x) for { if v.AuxInt != 9 { break } x := v.Args[0] v.reset(Op386LEAL8) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [11] x) // cond: // result: (LEAL2 x (LEAL4 x x)) for { if v.AuxInt != 11 { break } x := v.Args[0] v.reset(Op386LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [13] x) // cond: // result: (LEAL4 x (LEAL2 x x)) for { if v.AuxInt != 13 { break } x := v.Args[0] v.reset(Op386LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [19] x) // cond: // result: (LEAL2 x (LEAL8 x x)) for { if v.AuxInt != 19 { break } x := v.Args[0] v.reset(Op386LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [21] x) // cond: // result: (LEAL4 x (LEAL4 x x)) for { if v.AuxInt != 21 { break } x := v.Args[0] v.reset(Op386LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [25] x) // cond: // result: (LEAL8 x (LEAL2 x x)) for { if v.AuxInt != 25 { break } x := v.Args[0] v.reset(Op386LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [27] x) // cond: // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if v.AuxInt != 27 { break } x := v.Args[0] v.reset(Op386LEAL8) v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULLconst [37] x) // cond: // result: (LEAL4 x (LEAL8 x x)) for { if v.AuxInt != 37 { break } x := v.Args[0] v.reset(Op386LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [41] x) // cond: // result: (LEAL8 x (LEAL4 x x)) for { if v.AuxInt != 41 { break } x := v.Args[0] v.reset(Op386LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [45] x) // cond: // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if v.AuxInt != 45 { break } x := v.Args[0] v.reset(Op386LEAL8) v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } return false } func rewriteValue386_Op386MULLconst_20(v *Value) bool { b := v.Block _ = b // match: (MULLconst [73] x) // cond: // result: (LEAL8 x (LEAL8 x x)) for { if v.AuxInt != 73 { break } x := v.Args[0] v.reset(Op386LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [81] x) // cond: // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if v.AuxInt != 81 { break } x := v.Args[0] v.reset(Op386LEAL8) v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c+1) && c >= 15 // result: (SUBL (SHLLconst [log2(c+1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c+1) && c >= 15) { break } v.reset(Op386SUBL) v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type) v0.AuxInt = log2(c + 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [log2(c-1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-1) && c >= 17) { break } v.reset(Op386LEAL1) v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type) v0.AuxInt = log2(c - 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [log2(c-2)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-2) && c >= 34) { break } v.reset(Op386LEAL2) v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type) v0.AuxInt = log2(c - 2) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [log2(c-4)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-4) && c >= 68) { break } v.reset(Op386LEAL4) v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type) v0.AuxInt = log2(c - 4) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [log2(c-8)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-8) && c >= 136) { break } v.reset(Op386LEAL8) v0 := b.NewValue0(v.Pos, Op386SHLLconst, v.Type) v0.AuxInt = log2(c - 8) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo(c/3) // result: (SHLLconst [log2(c/3)] (LEAL2 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%3 == 0 && isPowerOfTwo(c/3)) { break } v.reset(Op386SHLLconst) v.AuxInt = log2(c / 3) v0 := b.NewValue0(v.Pos, Op386LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo(c/5) // result: (SHLLconst [log2(c/5)] (LEAL4 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%5 == 0 && isPowerOfTwo(c/5)) { break } v.reset(Op386SHLLconst) v.AuxInt = log2(c / 5) v0 := b.NewValue0(v.Pos, Op386LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo(c/9) // result: (SHLLconst [log2(c/9)] (LEAL8 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%9 == 0 && isPowerOfTwo(c/9)) { break } v.reset(Op386SHLLconst) v.AuxInt = log2(c / 9) v0 := b.NewValue0(v.Pos, Op386LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValue386_Op386MULLconst_30(v *Value) bool { // match: (MULLconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [int64(int32(c*d))]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = int64(int32(c * d)) return true } return false } func rewriteValue386_Op386MULLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MULLload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MULLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MULLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MULLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MULLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL4 { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[1] ptr := v_1.Args[0] idx := v_1.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386MULLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULLloadidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MULLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem) // cond: is32Bit(off1+off2) // result: (MULLloadidx4 [off1+off2] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MULLloadidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (MULLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem) // cond: is32Bit(off1+off2*4) // result: (MULLloadidx4 [off1+off2*4] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] base := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386ADDLconst { break } off2 := v_2.AuxInt idx := v_2.Args[0] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386MULLloadidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (MULLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MULLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MULLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULSD_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSDload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386MULSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MULSD l:(MOVSDload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVSDload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386MULSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULSDload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MULSDload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MULSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MULSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULSS_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSSload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386MULSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MULSS l:(MOVSSload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVSSload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386MULSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386MULSSload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MULSSload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386MULSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386MULSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386NEGL_0(v *Value) bool { // match: (NEGL (MOVLconst [c])) // cond: // result: (MOVLconst [int64(int32(-c))]) for { v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = int64(int32(-c)) return true } return false } func rewriteValue386_Op386NOTL_0(v *Value) bool { // match: (NOTL (MOVLconst [c])) // cond: // result: (MOVLconst [^c]) for { v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = ^c return true } return false } func rewriteValue386_Op386ORL_0(v *Value) bool { // match: (ORL x (MOVLconst [c])) // cond: // result: (ORLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386ORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (MOVLconst [c]) x) // cond: // result: (ORLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386ORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHLLconst [c] x) (SHRLconst [d] x)) // cond: d == 32-c // result: (ROLLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(Op386ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHRLconst [d] x) (SHLLconst [c] x)) // cond: d == 32-c // result: (ROLLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(Op386ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: c < 16 && d == 16-c && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 16 && d == 16-c && t.Size() == 2) { break } v.reset(Op386ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHRWconst x [d]) (SHLLconst x [c])) // cond: c < 16 && d == 16-c && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 16 && d == 16-c && t.Size() == 2) { break } v.reset(Op386ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: c < 8 && d == 8-c && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRBconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 8 && d == 8-c && t.Size() == 1) { break } v.reset(Op386ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHRBconst x [d]) (SHLLconst x [c])) // cond: c < 8 && d == 8-c && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRBconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 8 && d == 8-c && t.Size() == 1) { break } v.reset(Op386ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ORL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ORL_10(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (ORL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ORLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ORLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (ORL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (ORLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386ORLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (ORL x x) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] if x != v.Args[1] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ORL x0:(MOVBload [i0] {s} p mem) s0:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != Op386MOVBload { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[1] p := x0.Args[0] mem := x0.Args[1] s0 := v.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL s0:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem)) x0:(MOVBload [i0] {s} p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBload { break } i1 := x1.AuxInt s := x1.Aux _ = x1.Args[1] p := x1.Args[0] mem := x1.Args[1] x0 := v.Args[1] if x0.Op != Op386MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWload [i0] {s} p mem) s0:(SHLLconst [16] x1:(MOVBload [i2] {s} p mem))) s1:(SHLLconst [24] x2:(MOVBload [i3] {s} p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWload { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[1] p := x0.Args[0] mem := x0.Args[1] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBload { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBload [i2] {s} p mem)) x0:(MOVWload [i0] {s} p mem)) s1:(SHLLconst [24] x2:(MOVBload [i3] {s} p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBload { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[1] p := x1.Args[0] mem := x1.Args[1] x0 := o0.Args[1] if x0.Op != Op386MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBload { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBload [i3] {s} p mem)) o0:(ORL x0:(MOVWload [i0] {s} p mem) s0:(SHLLconst [16] x1:(MOVBload [i2] {s} p mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBload { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[1] p := x2.Args[0] mem := x2.Args[1] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBload [i3] {s} p mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBload [i2] {s} p mem)) x0:(MOVWload [i0] {s} p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBload { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[1] p := x2.Args[0] mem := x2.Args[1] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] p := x0.Args[0] idx := x0.Args[1] mem := x0.Args[2] s0 := v.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386ORL_20(v *Value) bool { b := v.Block _ = b // match: (ORL x0:(MOVBloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] idx := x0.Args[0] p := x0.Args[1] mem := x0.Args[2] s0 := v.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] p := x0.Args[0] idx := x0.Args[1] mem := x0.Args[2] s0 := v.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] idx := x0.Args[0] p := x0.Args[1] mem := x0.Args[2] s0 := v.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux _ = x1.Args[2] p := x1.Args[0] idx := x1.Args[1] mem := x1.Args[2] x0 := v.Args[1] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux _ = x1.Args[2] idx := x1.Args[0] p := x1.Args[1] mem := x1.Args[2] x0 := v.Args[1] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux _ = x1.Args[2] p := x1.Args[0] idx := x1.Args[1] mem := x1.Args[2] x0 := v.Args[1] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s0:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) // cond: i1==i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux _ = x1.Args[2] idx := x1.Args[0] p := x1.Args[1] mem := x1.Args[2] x0 := v.Args[1] if x0.Op != Op386MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, Op386MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] p := x0.Args[0] idx := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] idx := x0.Args[0] p := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] p := x0.Args[0] idx := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386ORL_30(v *Value) bool { b := v.Block _ = b // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] idx := x0.Args[0] p := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] p := x1.Args[0] idx := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] idx := x1.Args[0] p := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] p := x1.Args[0] idx := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] idx := x1.Args[0] p := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if idx != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] p := x0.Args[0] idx := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] idx := x0.Args[0] p := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] p := x0.Args[0] idx := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem))) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[2] idx := x0.Args[0] p := x0.Args[1] mem := x0.Args[2] s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] p := x1.Args[0] idx := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386ORL_40(v *Value) bool { b := v.Block _ = b // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] idx := x1.Args[0] p := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] p := x1.Args[0] idx := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] o0 := v.Args[0] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[2] idx := x1.Args[0] p := x1.Args[1] mem := x1.Args[2] x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s1 := v.Args[1] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if idx != x2.Args[0] { break } if p != x2.Args[1] { break } if mem != x2.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386ORL_50(v *Value) bool { b := v.Block _ = b // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } s0 := o0.Args[1] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if idx != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } if idx != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} p idx mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] p := x2.Args[0] idx := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [24] x2:(MOVBloadidx1 [i3] {s} idx p mem)) o0:(ORL s0:(SHLLconst [16] x1:(MOVBloadidx1 [i2] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != Op386SHLLconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != Op386MOVBloadidx1 { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[2] idx := x2.Args[0] p := x2.Args[1] mem := x2.Args[2] o0 := v.Args[1] if o0.Op != Op386ORL { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != Op386SHLLconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != Op386MOVBloadidx1 { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] { break } if p != x1.Args[1] { break } if mem != x1.Args[2] { break } x0 := o0.Args[1] if x0.Op != Op386MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] { break } if p != x0.Args[1] { break } if mem != x0.Args[2] { break } if !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, Op386MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValue386_Op386ORLconst_0(v *Value) bool { // match: (ORLconst [c] x) // cond: int32(c)==0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ORLconst [c] _) // cond: int32(c)==-1 // result: (MOVLconst [-1]) for { c := v.AuxInt if !(int32(c) == -1) { break } v.reset(Op386MOVLconst) v.AuxInt = -1 return true } // match: (ORLconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [c|d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = c | d return true } return false } func rewriteValue386_Op386ORLconstmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ORLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ORLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386ORLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ORLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ORLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ORLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ORLconstmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ORLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ORLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386ORLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ORLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem) // cond: ValAndOff(valoff1).canAdd(off2*4) // result: (ORLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2 * 4)) { break } v.reset(Op386ORLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2 * 4) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ORLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ORLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ORLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ORLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ORLload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ORLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ORLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ORLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ORLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ORLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ORLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL4 { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[1] ptr := v_1.Args[0] idx := v_1.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386ORLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ORLloadidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ORLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem) // cond: is32Bit(off1+off2) // result: (ORLloadidx4 [off1+off2] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ORLloadidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ORLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem) // cond: is32Bit(off1+off2*4) // result: (ORLloadidx4 [off1+off2*4] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] base := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386ADDLconst { break } off2 := v_2.AuxInt idx := v_2.Args[0] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386ORLloadidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (ORLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ORLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ORLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ORLmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ORLmodify [off1] {sym} (ADDLconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ORLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ORLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ORLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ORLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ORLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ORLmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (ORLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem) // cond: is32Bit(off1+off2) // result: (ORLmodifyidx4 [off1+off2] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386ORLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ORLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem) // cond: is32Bit(off1+off2*4) // result: (ORLmodifyidx4 [off1+off2*4] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386ORLmodifyidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ORLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (ORLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386ORLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (ORLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem) // cond: validValAndOff(c,off) // result: (ORLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386MOVLconst { break } c := v_2.AuxInt mem := v.Args[3] if !(validValAndOff(c, off)) { break } v.reset(Op386ORLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386ROLBconst_0(v *Value) bool { // match: (ROLBconst [c] (ROLBconst [d] x)) // cond: // result: (ROLBconst [(c+d)& 7] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ROLBconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ROLBconst) v.AuxInt = (c + d) & 7 v.AddArg(x) return true } // match: (ROLBconst [0] x) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386ROLLconst_0(v *Value) bool { // match: (ROLLconst [c] (ROLLconst [d] x)) // cond: // result: (ROLLconst [(c+d)&31] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ROLLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ROLLconst) v.AuxInt = (c + d) & 31 v.AddArg(x) return true } // match: (ROLLconst [0] x) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386ROLWconst_0(v *Value) bool { // match: (ROLWconst [c] (ROLWconst [d] x)) // cond: // result: (ROLWconst [(c+d)&15] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386ROLWconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386ROLWconst) v.AuxInt = (c + d) & 15 v.AddArg(x) return true } // match: (ROLWconst [0] x) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386SARB_0(v *Value) bool { // match: (SARB x (MOVLconst [c])) // cond: // result: (SARBconst [min(c&31,7)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SARBconst) v.AuxInt = min(c&31, 7) v.AddArg(x) return true } return false } func rewriteValue386_Op386SARBconst_0(v *Value) bool { // match: (SARBconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARBconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [d>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = d >> uint64(c) return true } return false } func rewriteValue386_Op386SARL_0(v *Value) bool { // match: (SARL x (MOVLconst [c])) // cond: // result: (SARLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SARLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SARL x (ANDLconst [31] y)) // cond: // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ANDLconst { break } if v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(Op386SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386SARLconst_0(v *Value) bool { // match: (SARLconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARLconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [d>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = d >> uint64(c) return true } return false } func rewriteValue386_Op386SARW_0(v *Value) bool { // match: (SARW x (MOVLconst [c])) // cond: // result: (SARWconst [min(c&31,15)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SARWconst) v.AuxInt = min(c&31, 15) v.AddArg(x) return true } return false } func rewriteValue386_Op386SARWconst_0(v *Value) bool { // match: (SARWconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARWconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [d>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = d >> uint64(c) return true } return false } func rewriteValue386_Op386SBBL_0(v *Value) bool { // match: (SBBL x (MOVLconst [c]) f) // cond: // result: (SBBLconst [c] x f) for { _ = v.Args[2] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt f := v.Args[2] v.reset(Op386SBBLconst) v.AuxInt = c v.AddArg(x) v.AddArg(f) return true } return false } func rewriteValue386_Op386SBBLcarrymask_0(v *Value) bool { // match: (SBBLcarrymask (FlagEQ)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SBBLcarrymask (FlagLT_ULT)) // cond: // result: (MOVLconst [-1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = -1 return true } // match: (SBBLcarrymask (FlagLT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SBBLcarrymask (FlagGT_ULT)) // cond: // result: (MOVLconst [-1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = -1 return true } // match: (SBBLcarrymask (FlagGT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SETA_0(v *Value) bool { // match: (SETA (InvertFlags x)) // cond: // result: (SETB x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagLT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagLT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETA (FlagGT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagGT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValue386_Op386SETAE_0(v *Value) bool { // match: (SETAE (InvertFlags x)) // cond: // result: (SETBE x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETAE (FlagLT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETAE (FlagLT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETAE (FlagGT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETAE (FlagGT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValue386_Op386SETB_0(v *Value) bool { // match: (SETB (InvertFlags x)) // cond: // result: (SETA x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETB (FlagLT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETB (FlagLT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETB (FlagGT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETB (FlagGT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SETBE_0(v *Value) bool { // match: (SETBE (InvertFlags x)) // cond: // result: (SETAE x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagLT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagLT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETBE (FlagGT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagGT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SETEQ_0(v *Value) bool { // match: (SETEQ (InvertFlags x)) // cond: // result: (SETEQ x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETEQ (FlagLT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagLT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagGT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagGT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SETG_0(v *Value) bool { // match: (SETG (InvertFlags x)) // cond: // result: (SETL x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagLT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagLT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagGT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETG (FlagGT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValue386_Op386SETGE_0(v *Value) bool { // match: (SETGE (InvertFlags x)) // cond: // result: (SETLE x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETGE (FlagLT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETGE (FlagLT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETGE (FlagGT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETGE (FlagGT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValue386_Op386SETL_0(v *Value) bool { // match: (SETL (InvertFlags x)) // cond: // result: (SETG x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETL (FlagLT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETL (FlagLT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETL (FlagGT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETL (FlagGT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SETLE_0(v *Value) bool { // match: (SETLE (InvertFlags x)) // cond: // result: (SETGE x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagLT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagLT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagGT_ULT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETLE (FlagGT_UGT)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SETNE_0(v *Value) bool { // match: (SETNE (InvertFlags x)) // cond: // result: (SETNE x) for { v_0 := v.Args[0] if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // cond: // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagEQ { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } // match: (SETNE (FlagLT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagLT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagLT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagGT_ULT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_ULT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagGT_UGT)) // cond: // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != Op386FlagGT_UGT { break } v.reset(Op386MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValue386_Op386SHLL_0(v *Value) bool { // match: (SHLL x (MOVLconst [c])) // cond: // result: (SHLLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SHLLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHLL x (ANDLconst [31] y)) // cond: // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ANDLconst { break } if v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(Op386SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386SHLLconst_0(v *Value) bool { // match: (SHLLconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386SHRB_0(v *Value) bool { // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt if !(c&31 < 8) { break } v.reset(Op386SHRBconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt if !(c&31 >= 8) { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SHRBconst_0(v *Value) bool { // match: (SHRBconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386SHRL_0(v *Value) bool { // match: (SHRL x (MOVLconst [c])) // cond: // result: (SHRLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SHRLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRL x (ANDLconst [31] y)) // cond: // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ANDLconst { break } if v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(Op386SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValue386_Op386SHRLconst_0(v *Value) bool { // match: (SHRLconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386SHRW_0(v *Value) bool { // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt if !(c&31 < 16) { break } v.reset(Op386SHRWconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt if !(c&31 >= 16) { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SHRWconst_0(v *Value) bool { // match: (SHRWconst x [0]) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValue386_Op386SUBL_0(v *Value) bool { b := v.Block _ = b // match: (SUBL x (MOVLconst [c])) // cond: // result: (SUBLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SUBLconst) v.AuxInt = c v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // cond: // result: (NEGL (SUBLconst x [c])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386NEGL) v0 := b.NewValue0(v.Pos, Op386SUBLconst, v.Type) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386SUBLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (SUBL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (SUBLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386SUBLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (SUBL x x) // cond: // result: (MOVLconst [0]) for { _ = v.Args[1] x := v.Args[0] if x != v.Args[1] { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386SUBLcarry_0(v *Value) bool { // match: (SUBLcarry x (MOVLconst [c])) // cond: // result: (SUBLconstcarry [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386SUBLconstcarry) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValue386_Op386SUBLconst_0(v *Value) bool { // match: (SUBLconst [c] x) // cond: int32(c) == 0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SUBLconst [c] x) // cond: // result: (ADDLconst [int64(int32(-c))] x) for { c := v.AuxInt x := v.Args[0] v.reset(Op386ADDLconst) v.AuxInt = int64(int32(-c)) v.AddArg(x) return true } } func rewriteValue386_Op386SUBLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBLload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386SUBLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386SUBLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL4 { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[1] ptr := v_1.Args[0] idx := v_1.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386SUBLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBLloadidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem) // cond: is32Bit(off1+off2) // result: (SUBLloadidx4 [off1+off2] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386SUBLloadidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (SUBLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem) // cond: is32Bit(off1+off2*4) // result: (SUBLloadidx4 [off1+off2*4] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] base := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386ADDLconst { break } off2 := v_2.AuxInt idx := v_2.Args[0] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386SUBLloadidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (SUBLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (SUBLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386SUBLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBLmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBLmodify [off1] {sym} (ADDLconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386SUBLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386SUBLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBLmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem) // cond: is32Bit(off1+off2) // result: (SUBLmodifyidx4 [off1+off2] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386SUBLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem) // cond: is32Bit(off1+off2*4) // result: (SUBLmodifyidx4 [off1+off2*4] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386SUBLmodifyidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (SUBLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386SUBLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem) // cond: validValAndOff(-c,off) // result: (ADDLconstmodifyidx4 [makeValAndOff(-c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386MOVLconst { break } c := v_2.AuxInt mem := v.Args[3] if !(validValAndOff(-c, off)) { break } v.reset(Op386ADDLconstmodifyidx4) v.AuxInt = makeValAndOff(-c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBSD_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSDload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386SUBSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBSDload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBSDload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386SUBSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386SUBSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBSS_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVSSload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) { break } v.reset(Op386SUBSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386SUBSSload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (SUBSSload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386SUBSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386SUBSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORL_0(v *Value) bool { // match: (XORL x (MOVLconst [c])) // cond: // result: (XORLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386MOVLconst { break } c := v_1.AuxInt v.reset(Op386XORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (MOVLconst [c]) x) // cond: // result: (XORLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } c := v_0.AuxInt x := v.Args[1] v.reset(Op386XORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHLLconst [c] x) (SHRLconst [d] x)) // cond: d == 32-c // result: (ROLLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRLconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(Op386ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHRLconst [d] x) (SHLLconst [c] x)) // cond: d == 32-c // result: (ROLLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(Op386ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: c < 16 && d == 16-c && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 16 && d == 16-c && t.Size() == 2) { break } v.reset(Op386ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHRWconst x [d]) (SHLLconst x [c])) // cond: c < 16 && d == 16-c && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 16 && d == 16-c && t.Size() == 2) { break } v.reset(Op386ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: c < 8 && d == 8-c && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHRBconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 8 && d == 8-c && t.Size() == 1) { break } v.reset(Op386ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHRBconst x [d]) (SHLLconst x [c])) // cond: c < 8 && d == 8-c && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SHRBconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(c < 8 && d == 8-c && t.Size() == 1) { break } v.reset(Op386ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386XORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (XORL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLload { break } off := l.AuxInt sym := l.Aux _ = l.Args[1] ptr := l.Args[0] mem := l.Args[1] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386XORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORL_10(v *Value) bool { // match: (XORL x l:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (XORLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386XORLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (XORL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x) // cond: canMergeLoad(v, l, x) && clobber(l) // result: (XORLloadidx4 x [off] {sym} ptr idx mem) for { _ = v.Args[1] l := v.Args[0] if l.Op != Op386MOVLloadidx4 { break } off := l.AuxInt sym := l.Aux _ = l.Args[2] ptr := l.Args[0] idx := l.Args[1] mem := l.Args[2] x := v.Args[1] if !(canMergeLoad(v, l, x) && clobber(l)) { break } v.reset(Op386XORLloadidx4) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (XORL x x) // cond: // result: (MOVLconst [0]) for { _ = v.Args[1] x := v.Args[0] if x != v.Args[1] { break } v.reset(Op386MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValue386_Op386XORLconst_0(v *Value) bool { // match: (XORLconst [c] (XORLconst [d] x)) // cond: // result: (XORLconst [c ^ d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386XORLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(Op386XORLconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORLconst [c] x) // cond: int32(c)==0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (XORLconst [c] (MOVLconst [d])) // cond: // result: (MOVLconst [c^d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != Op386MOVLconst { break } d := v_0.AuxInt v.reset(Op386MOVLconst) v.AuxInt = c ^ d return true } return false } func rewriteValue386_Op386XORLconstmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (XORLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (XORLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386XORLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (XORLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (XORLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] mem := v.Args[1] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386XORLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORLconstmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (XORLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (XORLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(Op386XORLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (XORLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem) // cond: ValAndOff(valoff1).canAdd(off2*4) // result: (XORLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem) for { valoff1 := v.AuxInt sym := v.Aux _ = v.Args[2] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2 * 4)) { break } v.reset(Op386XORLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2 * 4) v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (XORLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (XORLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem) for { valoff1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] mem := v.Args[2] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386XORLconstmodifyidx4) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORLload_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (XORLload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (XORLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386XORLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (XORLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (XORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386XORLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (XORLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (XORLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL4 { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[1] ptr := v_1.Args[0] idx := v_1.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(Op386XORLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORLloadidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (XORLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem) // cond: is32Bit(off1+off2) // result: (XORLloadidx4 [off1+off2] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386XORLloadidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (XORLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem) // cond: is32Bit(off1+off2*4) // result: (XORLloadidx4 [off1+off2*4] {sym} val base idx mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] val := v.Args[0] base := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386ADDLconst { break } off2 := v_2.AuxInt idx := v_2.Args[0] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386XORLloadidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } // match: (XORLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (XORLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386LEAL { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] idx := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386XORLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORLmodify_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (XORLmodify [off1] {sym} (ADDLconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (XORLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(Op386XORLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (XORLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (XORLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386XORLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_Op386XORLmodifyidx4_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (XORLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem) // cond: is32Bit(off1+off2) // result: (XORLmodifyidx4 [off1+off2] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386ADDLconst { break } off2 := v_0.AuxInt base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2)) { break } v.reset(Op386XORLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (XORLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem) // cond: is32Bit(off1+off2*4) // result: (XORLmodifyidx4 [off1+off2*4] {sym} base idx val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[3] base := v.Args[0] v_1 := v.Args[1] if v_1.Op != Op386ADDLconst { break } off2 := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1 + off2*4)) { break } v.reset(Op386XORLmodifyidx4) v.AuxInt = off1 + off2*4 v.Aux = sym v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (XORLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) // result: (XORLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[3] v_0 := v.Args[0] if v_0.Op != Op386LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] idx := v.Args[1] val := v.Args[2] mem := v.Args[3] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) { break } v.reset(Op386XORLmodifyidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (XORLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem) // cond: validValAndOff(c,off) // result: (XORLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != Op386MOVLconst { break } c := v_2.AuxInt mem := v.Args[3] if !(validValAndOff(c, off)) { break } v.reset(Op386XORLconstmodifyidx4) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValue386_OpAdd16_0(v *Value) bool { // match: (Add16 x y) // cond: // result: (ADDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAdd32_0(v *Value) bool { // match: (Add32 x y) // cond: // result: (ADDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAdd32F_0(v *Value) bool { // match: (Add32F x y) // cond: // result: (ADDSS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAdd32carry_0(v *Value) bool { // match: (Add32carry x y) // cond: // result: (ADDLcarry x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDLcarry) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAdd32withcarry_0(v *Value) bool { // match: (Add32withcarry x y c) // cond: // result: (ADCL x y c) for { _ = v.Args[2] x := v.Args[0] y := v.Args[1] c := v.Args[2] v.reset(Op386ADCL) v.AddArg(x) v.AddArg(y) v.AddArg(c) return true } } func rewriteValue386_OpAdd64F_0(v *Value) bool { // match: (Add64F x y) // cond: // result: (ADDSD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAdd8_0(v *Value) bool { // match: (Add8 x y) // cond: // result: (ADDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAddPtr_0(v *Value) bool { // match: (AddPtr x y) // cond: // result: (ADDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ADDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAddr_0(v *Value) bool { // match: (Addr {sym} base) // cond: // result: (LEAL {sym} base) for { sym := v.Aux base := v.Args[0] v.reset(Op386LEAL) v.Aux = sym v.AddArg(base) return true } } func rewriteValue386_OpAnd16_0(v *Value) bool { // match: (And16 x y) // cond: // result: (ANDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAnd32_0(v *Value) bool { // match: (And32 x y) // cond: // result: (ANDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAnd8_0(v *Value) bool { // match: (And8 x y) // cond: // result: (ANDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAndB_0(v *Value) bool { // match: (AndB x y) // cond: // result: (ANDL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpAvg32u_0(v *Value) bool { // match: (Avg32u x y) // cond: // result: (AVGLU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386AVGLU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpBswap32_0(v *Value) bool { // match: (Bswap32 x) // cond: // result: (BSWAPL x) for { x := v.Args[0] v.reset(Op386BSWAPL) v.AddArg(x) return true } } func rewriteValue386_OpClosureCall_0(v *Value) bool { // match: (ClosureCall [argwid] entry closure mem) // cond: // result: (CALLclosure [argwid] entry closure mem) for { argwid := v.AuxInt _ = v.Args[2] entry := v.Args[0] closure := v.Args[1] mem := v.Args[2] v.reset(Op386CALLclosure) v.AuxInt = argwid v.AddArg(entry) v.AddArg(closure) v.AddArg(mem) return true } } func rewriteValue386_OpCom16_0(v *Value) bool { // match: (Com16 x) // cond: // result: (NOTL x) for { x := v.Args[0] v.reset(Op386NOTL) v.AddArg(x) return true } } func rewriteValue386_OpCom32_0(v *Value) bool { // match: (Com32 x) // cond: // result: (NOTL x) for { x := v.Args[0] v.reset(Op386NOTL) v.AddArg(x) return true } } func rewriteValue386_OpCom8_0(v *Value) bool { // match: (Com8 x) // cond: // result: (NOTL x) for { x := v.Args[0] v.reset(Op386NOTL) v.AddArg(x) return true } } func rewriteValue386_OpConst16_0(v *Value) bool { // match: (Const16 [val]) // cond: // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(Op386MOVLconst) v.AuxInt = val return true } } func rewriteValue386_OpConst32_0(v *Value) bool { // match: (Const32 [val]) // cond: // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(Op386MOVLconst) v.AuxInt = val return true } } func rewriteValue386_OpConst32F_0(v *Value) bool { // match: (Const32F [val]) // cond: // result: (MOVSSconst [val]) for { val := v.AuxInt v.reset(Op386MOVSSconst) v.AuxInt = val return true } } func rewriteValue386_OpConst64F_0(v *Value) bool { // match: (Const64F [val]) // cond: // result: (MOVSDconst [val]) for { val := v.AuxInt v.reset(Op386MOVSDconst) v.AuxInt = val return true } } func rewriteValue386_OpConst8_0(v *Value) bool { // match: (Const8 [val]) // cond: // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(Op386MOVLconst) v.AuxInt = val return true } } func rewriteValue386_OpConstBool_0(v *Value) bool { // match: (ConstBool [b]) // cond: // result: (MOVLconst [b]) for { b := v.AuxInt v.reset(Op386MOVLconst) v.AuxInt = b return true } } func rewriteValue386_OpConstNil_0(v *Value) bool { // match: (ConstNil) // cond: // result: (MOVLconst [0]) for { v.reset(Op386MOVLconst) v.AuxInt = 0 return true } } func rewriteValue386_OpCvt32Fto32_0(v *Value) bool { // match: (Cvt32Fto32 x) // cond: // result: (CVTTSS2SL x) for { x := v.Args[0] v.reset(Op386CVTTSS2SL) v.AddArg(x) return true } } func rewriteValue386_OpCvt32Fto64F_0(v *Value) bool { // match: (Cvt32Fto64F x) // cond: // result: (CVTSS2SD x) for { x := v.Args[0] v.reset(Op386CVTSS2SD) v.AddArg(x) return true } } func rewriteValue386_OpCvt32to32F_0(v *Value) bool { // match: (Cvt32to32F x) // cond: // result: (CVTSL2SS x) for { x := v.Args[0] v.reset(Op386CVTSL2SS) v.AddArg(x) return true } } func rewriteValue386_OpCvt32to64F_0(v *Value) bool { // match: (Cvt32to64F x) // cond: // result: (CVTSL2SD x) for { x := v.Args[0] v.reset(Op386CVTSL2SD) v.AddArg(x) return true } } func rewriteValue386_OpCvt64Fto32_0(v *Value) bool { // match: (Cvt64Fto32 x) // cond: // result: (CVTTSD2SL x) for { x := v.Args[0] v.reset(Op386CVTTSD2SL) v.AddArg(x) return true } } func rewriteValue386_OpCvt64Fto32F_0(v *Value) bool { // match: (Cvt64Fto32F x) // cond: // result: (CVTSD2SS x) for { x := v.Args[0] v.reset(Op386CVTSD2SS) v.AddArg(x) return true } } func rewriteValue386_OpDiv16_0(v *Value) bool { // match: (Div16 x y) // cond: // result: (DIVW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpDiv16u_0(v *Value) bool { // match: (Div16u x y) // cond: // result: (DIVWU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVWU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpDiv32_0(v *Value) bool { // match: (Div32 x y) // cond: // result: (DIVL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpDiv32F_0(v *Value) bool { // match: (Div32F x y) // cond: // result: (DIVSS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpDiv32u_0(v *Value) bool { // match: (Div32u x y) // cond: // result: (DIVLU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVLU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpDiv64F_0(v *Value) bool { // match: (Div64F x y) // cond: // result: (DIVSD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpDiv8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Div8 x y) // cond: // result: (DIVW (SignExt8to16 x) (SignExt8to16 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVW) v0 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValue386_OpDiv8u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Div8u x y) // cond: // result: (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386DIVWU) v0 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValue386_OpEq16_0(v *Value) bool { b := v.Block _ = b // match: (Eq16 x y) // cond: // result: (SETEQ (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQ) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpEq32_0(v *Value) bool { b := v.Block _ = b // match: (Eq32 x y) // cond: // result: (SETEQ (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQ) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpEq32F_0(v *Value) bool { b := v.Block _ = b // match: (Eq32F x y) // cond: // result: (SETEQF (UCOMISS x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQF) v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpEq64F_0(v *Value) bool { b := v.Block _ = b // match: (Eq64F x y) // cond: // result: (SETEQF (UCOMISD x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQF) v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpEq8_0(v *Value) bool { b := v.Block _ = b // match: (Eq8 x y) // cond: // result: (SETEQ (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQ) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpEqB_0(v *Value) bool { b := v.Block _ = b // match: (EqB x y) // cond: // result: (SETEQ (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQ) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpEqPtr_0(v *Value) bool { b := v.Block _ = b // match: (EqPtr x y) // cond: // result: (SETEQ (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETEQ) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq16_0(v *Value) bool { b := v.Block _ = b // match: (Geq16 x y) // cond: // result: (SETGE (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGE) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq16U_0(v *Value) bool { b := v.Block _ = b // match: (Geq16U x y) // cond: // result: (SETAE (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETAE) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq32_0(v *Value) bool { b := v.Block _ = b // match: (Geq32 x y) // cond: // result: (SETGE (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq32F_0(v *Value) bool { b := v.Block _ = b // match: (Geq32F x y) // cond: // result: (SETGEF (UCOMISS x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGEF) v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq32U_0(v *Value) bool { b := v.Block _ = b // match: (Geq32U x y) // cond: // result: (SETAE (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETAE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq64F_0(v *Value) bool { b := v.Block _ = b // match: (Geq64F x y) // cond: // result: (SETGEF (UCOMISD x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGEF) v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq8_0(v *Value) bool { b := v.Block _ = b // match: (Geq8 x y) // cond: // result: (SETGE (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGE) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGeq8U_0(v *Value) bool { b := v.Block _ = b // match: (Geq8U x y) // cond: // result: (SETAE (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETAE) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGetCallerPC_0(v *Value) bool { // match: (GetCallerPC) // cond: // result: (LoweredGetCallerPC) for { v.reset(Op386LoweredGetCallerPC) return true } } func rewriteValue386_OpGetCallerSP_0(v *Value) bool { // match: (GetCallerSP) // cond: // result: (LoweredGetCallerSP) for { v.reset(Op386LoweredGetCallerSP) return true } } func rewriteValue386_OpGetClosurePtr_0(v *Value) bool { // match: (GetClosurePtr) // cond: // result: (LoweredGetClosurePtr) for { v.reset(Op386LoweredGetClosurePtr) return true } } func rewriteValue386_OpGetG_0(v *Value) bool { // match: (GetG mem) // cond: // result: (LoweredGetG mem) for { mem := v.Args[0] v.reset(Op386LoweredGetG) v.AddArg(mem) return true } } func rewriteValue386_OpGreater16_0(v *Value) bool { b := v.Block _ = b // match: (Greater16 x y) // cond: // result: (SETG (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETG) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater16U_0(v *Value) bool { b := v.Block _ = b // match: (Greater16U x y) // cond: // result: (SETA (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETA) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater32_0(v *Value) bool { b := v.Block _ = b // match: (Greater32 x y) // cond: // result: (SETG (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETG) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater32F_0(v *Value) bool { b := v.Block _ = b // match: (Greater32F x y) // cond: // result: (SETGF (UCOMISS x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGF) v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater32U_0(v *Value) bool { b := v.Block _ = b // match: (Greater32U x y) // cond: // result: (SETA (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETA) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater64F_0(v *Value) bool { b := v.Block _ = b // match: (Greater64F x y) // cond: // result: (SETGF (UCOMISD x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGF) v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater8_0(v *Value) bool { b := v.Block _ = b // match: (Greater8 x y) // cond: // result: (SETG (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETG) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpGreater8U_0(v *Value) bool { b := v.Block _ = b // match: (Greater8U x y) // cond: // result: (SETA (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETA) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpHmul32_0(v *Value) bool { // match: (Hmul32 x y) // cond: // result: (HMULL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386HMULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpHmul32u_0(v *Value) bool { // match: (Hmul32u x y) // cond: // result: (HMULLU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386HMULLU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpInterCall_0(v *Value) bool { // match: (InterCall [argwid] entry mem) // cond: // result: (CALLinter [argwid] entry mem) for { argwid := v.AuxInt _ = v.Args[1] entry := v.Args[0] mem := v.Args[1] v.reset(Op386CALLinter) v.AuxInt = argwid v.AddArg(entry) v.AddArg(mem) return true } } func rewriteValue386_OpIsInBounds_0(v *Value) bool { b := v.Block _ = b // match: (IsInBounds idx len) // cond: // result: (SETB (CMPL idx len)) for { _ = v.Args[1] idx := v.Args[0] len := v.Args[1] v.reset(Op386SETB) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValue386_OpIsNonNil_0(v *Value) bool { b := v.Block _ = b // match: (IsNonNil p) // cond: // result: (SETNE (TESTL p p)) for { p := v.Args[0] v.reset(Op386SETNE) v0 := b.NewValue0(v.Pos, Op386TESTL, types.TypeFlags) v0.AddArg(p) v0.AddArg(p) v.AddArg(v0) return true } } func rewriteValue386_OpIsSliceInBounds_0(v *Value) bool { b := v.Block _ = b // match: (IsSliceInBounds idx len) // cond: // result: (SETBE (CMPL idx len)) for { _ = v.Args[1] idx := v.Args[0] len := v.Args[1] v.reset(Op386SETBE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValue386_OpLeq16_0(v *Value) bool { b := v.Block _ = b // match: (Leq16 x y) // cond: // result: (SETLE (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETLE) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLeq16U_0(v *Value) bool { b := v.Block _ = b // match: (Leq16U x y) // cond: // result: (SETBE (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETBE) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLeq32_0(v *Value) bool { b := v.Block _ = b // match: (Leq32 x y) // cond: // result: (SETLE (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETLE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLeq32F_0(v *Value) bool { b := v.Block _ = b // match: (Leq32F x y) // cond: // result: (SETGEF (UCOMISS y x)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGEF) v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValue386_OpLeq32U_0(v *Value) bool { b := v.Block _ = b // match: (Leq32U x y) // cond: // result: (SETBE (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETBE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLeq64F_0(v *Value) bool { b := v.Block _ = b // match: (Leq64F x y) // cond: // result: (SETGEF (UCOMISD y x)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGEF) v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValue386_OpLeq8_0(v *Value) bool { b := v.Block _ = b // match: (Leq8 x y) // cond: // result: (SETLE (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETLE) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLeq8U_0(v *Value) bool { b := v.Block _ = b // match: (Leq8U x y) // cond: // result: (SETBE (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETBE) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLess16_0(v *Value) bool { b := v.Block _ = b // match: (Less16 x y) // cond: // result: (SETL (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETL) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLess16U_0(v *Value) bool { b := v.Block _ = b // match: (Less16U x y) // cond: // result: (SETB (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETB) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLess32_0(v *Value) bool { b := v.Block _ = b // match: (Less32 x y) // cond: // result: (SETL (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETL) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLess32F_0(v *Value) bool { b := v.Block _ = b // match: (Less32F x y) // cond: // result: (SETGF (UCOMISS y x)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGF) v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValue386_OpLess32U_0(v *Value) bool { b := v.Block _ = b // match: (Less32U x y) // cond: // result: (SETB (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETB) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLess64F_0(v *Value) bool { b := v.Block _ = b // match: (Less64F x y) // cond: // result: (SETGF (UCOMISD y x)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETGF) v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValue386_OpLess8_0(v *Value) bool { b := v.Block _ = b // match: (Less8 x y) // cond: // result: (SETL (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETL) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLess8U_0(v *Value) bool { b := v.Block _ = b // match: (Less8U x y) // cond: // result: (SETB (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETB) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpLoad_0(v *Value) bool { // match: (Load ptr mem) // cond: (is32BitInt(t) || isPtr(t)) // result: (MOVLload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is32BitInt(t) || isPtr(t)) { break } v.reset(Op386MOVLload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is16BitInt(t)) { break } v.reset(Op386MOVWload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(Op386MOVBload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is32BitFloat(t)) { break } v.reset(Op386MOVSSload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is64BitFloat(t)) { break } v.reset(Op386MOVSDload) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValue386_OpLocalAddr_0(v *Value) bool { // match: (LocalAddr {sym} base _) // cond: // result: (LEAL {sym} base) for { sym := v.Aux _ = v.Args[1] base := v.Args[0] v.reset(Op386LEAL) v.Aux = sym v.AddArg(base) return true } } func rewriteValue386_OpLsh16x16_0(v *Value) bool { b := v.Block _ = b // match: (Lsh16x16 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh16x32_0(v *Value) bool { b := v.Block _ = b // match: (Lsh16x32 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh16x64_0(v *Value) bool { // match: (Lsh16x64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SHLLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(Op386SHLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValue386_OpLsh16x8_0(v *Value) bool { b := v.Block _ = b // match: (Lsh16x8 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh32x16_0(v *Value) bool { b := v.Block _ = b // match: (Lsh32x16 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh32x32_0(v *Value) bool { b := v.Block _ = b // match: (Lsh32x32 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh32x64_0(v *Value) bool { // match: (Lsh32x64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SHLLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(Op386SHLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValue386_OpLsh32x8_0(v *Value) bool { b := v.Block _ = b // match: (Lsh32x8 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh8x16_0(v *Value) bool { b := v.Block _ = b // match: (Lsh8x16 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh8x32_0(v *Value) bool { b := v.Block _ = b // match: (Lsh8x32 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpLsh8x64_0(v *Value) bool { // match: (Lsh8x64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SHLLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(Op386SHLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValue386_OpLsh8x8_0(v *Value) bool { b := v.Block _ = b // match: (Lsh8x8 x y) // cond: // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpMod16_0(v *Value) bool { // match: (Mod16 x y) // cond: // result: (MODW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MODW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMod16u_0(v *Value) bool { // match: (Mod16u x y) // cond: // result: (MODWU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MODWU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMod32_0(v *Value) bool { // match: (Mod32 x y) // cond: // result: (MODL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MODL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMod32u_0(v *Value) bool { // match: (Mod32u x y) // cond: // result: (MODLU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MODLU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMod8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod8 x y) // cond: // result: (MODW (SignExt8to16 x) (SignExt8to16 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MODW) v0 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValue386_OpMod8u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod8u x y) // cond: // result: (MODWU (ZeroExt8to16 x) (ZeroExt8to16 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MODWU) v0 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValue386_OpMove_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Move [0] _ _ mem) // cond: // result: mem for { if v.AuxInt != 0 { break } _ = v.Args[2] mem := v.Args[2] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Move [1] dst src mem) // cond: // result: (MOVBstore dst (MOVBload src mem) mem) for { if v.AuxInt != 1 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVBstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVBload, typ.UInt8) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [2] dst src mem) // cond: // result: (MOVWstore dst (MOVWload src mem) mem) for { if v.AuxInt != 2 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [4] dst src mem) // cond: // result: (MOVLstore dst (MOVLload src mem) mem) for { if v.AuxInt != 4 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [3] dst src mem) // cond: // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if v.AuxInt != 3 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVBstore) v.AuxInt = 2 v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVBload, typ.UInt8) v0.AuxInt = 2 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [5] dst src mem) // cond: // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 5 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVBstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVBload, typ.UInt8) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [6] dst src mem) // cond: // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 6 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVWstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVWload, typ.UInt16) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [7] dst src mem) // cond: // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 7 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLstore) v.AuxInt = 3 v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v0.AuxInt = 3 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [8] dst src mem) // cond: // result: (MOVLstore [4] dst (MOVLload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 8 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(Op386MOVLstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [s] dst src mem) // cond: s > 8 && s%4 != 0 // result: (Move [s-s%4] (ADDLconst dst [s%4]) (ADDLconst src [s%4]) (MOVLstore dst (MOVLload src mem) mem)) for { s := v.AuxInt _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] if !(s > 8 && s%4 != 0) { break } v.reset(OpMove) v.AuxInt = s - s%4 v0 := b.NewValue0(v.Pos, Op386ADDLconst, dst.Type) v0.AuxInt = s % 4 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386ADDLconst, src.Type) v1.AuxInt = s % 4 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, Op386MOVLstore, types.TypeMem) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, Op386MOVLload, typ.UInt32) v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } return false } func rewriteValue386_OpMove_10(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config typ := &b.Func.Config.Types _ = typ // match: (Move [s] dst src mem) // cond: s > 8 && s <= 4*128 && s%4 == 0 && !config.noDuffDevice // result: (DUFFCOPY [10*(128-s/4)] dst src mem) for { s := v.AuxInt _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] if !(s > 8 && s <= 4*128 && s%4 == 0 && !config.noDuffDevice) { break } v.reset(Op386DUFFCOPY) v.AuxInt = 10 * (128 - s/4) v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } // match: (Move [s] dst src mem) // cond: (s > 4*128 || config.noDuffDevice) && s%4 == 0 // result: (REPMOVSL dst src (MOVLconst [s/4]) mem) for { s := v.AuxInt _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] if !((s > 4*128 || config.noDuffDevice) && s%4 == 0) { break } v.reset(Op386REPMOVSL) v.AddArg(dst) v.AddArg(src) v0 := b.NewValue0(v.Pos, Op386MOVLconst, typ.UInt32) v0.AuxInt = s / 4 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValue386_OpMul16_0(v *Value) bool { // match: (Mul16 x y) // cond: // result: (MULL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMul32_0(v *Value) bool { // match: (Mul32 x y) // cond: // result: (MULL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMul32F_0(v *Value) bool { // match: (Mul32F x y) // cond: // result: (MULSS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MULSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMul32uhilo_0(v *Value) bool { // match: (Mul32uhilo x y) // cond: // result: (MULLQU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MULLQU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMul64F_0(v *Value) bool { // match: (Mul64F x y) // cond: // result: (MULSD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MULSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpMul8_0(v *Value) bool { // match: (Mul8 x y) // cond: // result: (MULL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpNeg16_0(v *Value) bool { // match: (Neg16 x) // cond: // result: (NEGL x) for { x := v.Args[0] v.reset(Op386NEGL) v.AddArg(x) return true } } func rewriteValue386_OpNeg32_0(v *Value) bool { // match: (Neg32 x) // cond: // result: (NEGL x) for { x := v.Args[0] v.reset(Op386NEGL) v.AddArg(x) return true } } func rewriteValue386_OpNeg32F_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config typ := &b.Func.Config.Types _ = typ // match: (Neg32F x) // cond: !config.use387 // result: (PXOR x (MOVSSconst [auxFrom32F(float32(math.Copysign(0, -1)))])) for { x := v.Args[0] if !(!config.use387) { break } v.reset(Op386PXOR) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386MOVSSconst, typ.Float32) v0.AuxInt = auxFrom32F(float32(math.Copysign(0, -1))) v.AddArg(v0) return true } // match: (Neg32F x) // cond: config.use387 // result: (FCHS x) for { x := v.Args[0] if !(config.use387) { break } v.reset(Op386FCHS) v.AddArg(x) return true } return false } func rewriteValue386_OpNeg64F_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config typ := &b.Func.Config.Types _ = typ // match: (Neg64F x) // cond: !config.use387 // result: (PXOR x (MOVSDconst [auxFrom64F(math.Copysign(0, -1))])) for { x := v.Args[0] if !(!config.use387) { break } v.reset(Op386PXOR) v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386MOVSDconst, typ.Float64) v0.AuxInt = auxFrom64F(math.Copysign(0, -1)) v.AddArg(v0) return true } // match: (Neg64F x) // cond: config.use387 // result: (FCHS x) for { x := v.Args[0] if !(config.use387) { break } v.reset(Op386FCHS) v.AddArg(x) return true } return false } func rewriteValue386_OpNeg8_0(v *Value) bool { // match: (Neg8 x) // cond: // result: (NEGL x) for { x := v.Args[0] v.reset(Op386NEGL) v.AddArg(x) return true } } func rewriteValue386_OpNeq16_0(v *Value) bool { b := v.Block _ = b // match: (Neq16 x y) // cond: // result: (SETNE (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNE) v0 := b.NewValue0(v.Pos, Op386CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNeq32_0(v *Value) bool { b := v.Block _ = b // match: (Neq32 x y) // cond: // result: (SETNE (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNeq32F_0(v *Value) bool { b := v.Block _ = b // match: (Neq32F x y) // cond: // result: (SETNEF (UCOMISS x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNEF) v0 := b.NewValue0(v.Pos, Op386UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNeq64F_0(v *Value) bool { b := v.Block _ = b // match: (Neq64F x y) // cond: // result: (SETNEF (UCOMISD x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNEF) v0 := b.NewValue0(v.Pos, Op386UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNeq8_0(v *Value) bool { b := v.Block _ = b // match: (Neq8 x y) // cond: // result: (SETNE (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNE) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNeqB_0(v *Value) bool { b := v.Block _ = b // match: (NeqB x y) // cond: // result: (SETNE (CMPB x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNE) v0 := b.NewValue0(v.Pos, Op386CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNeqPtr_0(v *Value) bool { b := v.Block _ = b // match: (NeqPtr x y) // cond: // result: (SETNE (CMPL x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SETNE) v0 := b.NewValue0(v.Pos, Op386CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValue386_OpNilCheck_0(v *Value) bool { // match: (NilCheck ptr mem) // cond: // result: (LoweredNilCheck ptr mem) for { _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] v.reset(Op386LoweredNilCheck) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValue386_OpNot_0(v *Value) bool { // match: (Not x) // cond: // result: (XORLconst [1] x) for { x := v.Args[0] v.reset(Op386XORLconst) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValue386_OpOffPtr_0(v *Value) bool { // match: (OffPtr [off] ptr) // cond: // result: (ADDLconst [off] ptr) for { off := v.AuxInt ptr := v.Args[0] v.reset(Op386ADDLconst) v.AuxInt = off v.AddArg(ptr) return true } } func rewriteValue386_OpOr16_0(v *Value) bool { // match: (Or16 x y) // cond: // result: (ORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpOr32_0(v *Value) bool { // match: (Or32 x y) // cond: // result: (ORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpOr8_0(v *Value) bool { // match: (Or8 x y) // cond: // result: (ORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpOrB_0(v *Value) bool { // match: (OrB x y) // cond: // result: (ORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpRound32F_0(v *Value) bool { // match: (Round32F x) // cond: // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValue386_OpRound64F_0(v *Value) bool { // match: (Round64F x) // cond: // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValue386_OpRsh16Ux16_0(v *Value) bool { b := v.Block _ = b // match: (Rsh16Ux16 x y) // cond: // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh16Ux32_0(v *Value) bool { b := v.Block _ = b // match: (Rsh16Ux32 x y) // cond: // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh16Ux64_0(v *Value) bool { // match: (Rsh16Ux64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SHRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(Op386SHRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh16Ux64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValue386_OpRsh16Ux8_0(v *Value) bool { b := v.Block _ = b // match: (Rsh16Ux8 x y) // cond: // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh16x16_0(v *Value) bool { b := v.Block _ = b // match: (Rsh16x16 x y) // cond: // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh16x32_0(v *Value) bool { b := v.Block _ = b // match: (Rsh16x32 x y) // cond: // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh16x64_0(v *Value) bool { // match: (Rsh16x64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SARWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(Op386SARWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh16x64 x (Const64 [c])) // cond: uint64(c) >= 16 // result: (SARWconst x [15]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(Op386SARWconst) v.AuxInt = 15 v.AddArg(x) return true } return false } func rewriteValue386_OpRsh16x8_0(v *Value) bool { b := v.Block _ = b // match: (Rsh16x8 x y) // cond: // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh32Ux16_0(v *Value) bool { b := v.Block _ = b // match: (Rsh32Ux16 x y) // cond: // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh32Ux32_0(v *Value) bool { b := v.Block _ = b // match: (Rsh32Ux32 x y) // cond: // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh32Ux64_0(v *Value) bool { // match: (Rsh32Ux64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SHRLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(Op386SHRLconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValue386_OpRsh32Ux8_0(v *Value) bool { b := v.Block _ = b // match: (Rsh32Ux8 x y) // cond: // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh32x16_0(v *Value) bool { b := v.Block _ = b // match: (Rsh32x16 x y) // cond: // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh32x32_0(v *Value) bool { b := v.Block _ = b // match: (Rsh32x32 x y) // cond: // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh32x64_0(v *Value) bool { // match: (Rsh32x64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SARLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(Op386SARLconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x64 x (Const64 [c])) // cond: uint64(c) >= 32 // result: (SARLconst x [31]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(Op386SARLconst) v.AuxInt = 31 v.AddArg(x) return true } return false } func rewriteValue386_OpRsh32x8_0(v *Value) bool { b := v.Block _ = b // match: (Rsh32x8 x y) // cond: // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh8Ux16_0(v *Value) bool { b := v.Block _ = b // match: (Rsh8Ux16 x y) // cond: // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh8Ux32_0(v *Value) bool { b := v.Block _ = b // match: (Rsh8Ux32 x y) // cond: // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh8Ux64_0(v *Value) bool { // match: (Rsh8Ux64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SHRBconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(Op386SHRBconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh8Ux64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValue386_OpRsh8Ux8_0(v *Value) bool { b := v.Block _ = b // match: (Rsh8Ux8 x y) // cond: // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386ANDL) v0 := b.NewValue0(v.Pos, Op386SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValue386_OpRsh8x16_0(v *Value) bool { b := v.Block _ = b // match: (Rsh8x16 x y) // cond: // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh8x32_0(v *Value) bool { b := v.Block _ = b // match: (Rsh8x32 x y) // cond: // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpRsh8x64_0(v *Value) bool { // match: (Rsh8x64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SARBconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(Op386SARBconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh8x64 x (Const64 [c])) // cond: uint64(c) >= 8 // result: (SARBconst x [7]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(Op386SARBconst) v.AuxInt = 7 v.AddArg(x) return true } return false } func rewriteValue386_OpRsh8x8_0(v *Value) bool { b := v.Block _ = b // match: (Rsh8x8 x y) // cond: // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, Op386ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, Op386NOTL, y.Type) v2 := b.NewValue0(v.Pos, Op386SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValue386_OpSelect0_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Select0 (Mul32uover x y)) // cond: // result: (Select0 (MULLU x y)) for { v_0 := v.Args[0] if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, Op386MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValue386_OpSelect1_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Select1 (Mul32uover x y)) // cond: // result: (SETO (Select1 (MULLU x y))) for { v_0 := v.Args[0] if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] v.reset(Op386SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, Op386MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValue386_OpSignExt16to32_0(v *Value) bool { // match: (SignExt16to32 x) // cond: // result: (MOVWLSX x) for { x := v.Args[0] v.reset(Op386MOVWLSX) v.AddArg(x) return true } } func rewriteValue386_OpSignExt8to16_0(v *Value) bool { // match: (SignExt8to16 x) // cond: // result: (MOVBLSX x) for { x := v.Args[0] v.reset(Op386MOVBLSX) v.AddArg(x) return true } } func rewriteValue386_OpSignExt8to32_0(v *Value) bool { // match: (SignExt8to32 x) // cond: // result: (MOVBLSX x) for { x := v.Args[0] v.reset(Op386MOVBLSX) v.AddArg(x) return true } } func rewriteValue386_OpSignmask_0(v *Value) bool { // match: (Signmask x) // cond: // result: (SARLconst x [31]) for { x := v.Args[0] v.reset(Op386SARLconst) v.AuxInt = 31 v.AddArg(x) return true } } func rewriteValue386_OpSlicemask_0(v *Value) bool { b := v.Block _ = b // match: (Slicemask x) // cond: // result: (SARLconst (NEGL x) [31]) for { t := v.Type x := v.Args[0] v.reset(Op386SARLconst) v.AuxInt = 31 v0 := b.NewValue0(v.Pos, Op386NEGL, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValue386_OpSqrt_0(v *Value) bool { // match: (Sqrt x) // cond: // result: (SQRTSD x) for { x := v.Args[0] v.reset(Op386SQRTSD) v.AddArg(x) return true } } func rewriteValue386_OpStaticCall_0(v *Value) bool { // match: (StaticCall [argwid] {target} mem) // cond: // result: (CALLstatic [argwid] {target} mem) for { argwid := v.AuxInt target := v.Aux mem := v.Args[0] v.reset(Op386CALLstatic) v.AuxInt = argwid v.Aux = target v.AddArg(mem) return true } } func rewriteValue386_OpStore_0(v *Value) bool { // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) // result: (MOVSDstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(Op386MOVSDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) // result: (MOVSSstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(Op386MOVSSstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 // result: (MOVLstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 4) { break } v.reset(Op386MOVLstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 2 // result: (MOVWstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 2) { break } v.reset(Op386MOVWstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 1 // result: (MOVBstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 1) { break } v.reset(Op386MOVBstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValue386_OpSub16_0(v *Value) bool { // match: (Sub16 x y) // cond: // result: (SUBL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpSub32_0(v *Value) bool { // match: (Sub32 x y) // cond: // result: (SUBL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpSub32F_0(v *Value) bool { // match: (Sub32F x y) // cond: // result: (SUBSS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpSub32carry_0(v *Value) bool { // match: (Sub32carry x y) // cond: // result: (SUBLcarry x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBLcarry) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpSub32withcarry_0(v *Value) bool { // match: (Sub32withcarry x y c) // cond: // result: (SBBL x y c) for { _ = v.Args[2] x := v.Args[0] y := v.Args[1] c := v.Args[2] v.reset(Op386SBBL) v.AddArg(x) v.AddArg(y) v.AddArg(c) return true } } func rewriteValue386_OpSub64F_0(v *Value) bool { // match: (Sub64F x y) // cond: // result: (SUBSD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpSub8_0(v *Value) bool { // match: (Sub8 x y) // cond: // result: (SUBL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpSubPtr_0(v *Value) bool { // match: (SubPtr x y) // cond: // result: (SUBL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpTrunc16to8_0(v *Value) bool { // match: (Trunc16to8 x) // cond: // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValue386_OpTrunc32to16_0(v *Value) bool { // match: (Trunc32to16 x) // cond: // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValue386_OpTrunc32to8_0(v *Value) bool { // match: (Trunc32to8 x) // cond: // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValue386_OpWB_0(v *Value) bool { // match: (WB {fn} destptr srcptr mem) // cond: // result: (LoweredWB {fn} destptr srcptr mem) for { fn := v.Aux _ = v.Args[2] destptr := v.Args[0] srcptr := v.Args[1] mem := v.Args[2] v.reset(Op386LoweredWB) v.Aux = fn v.AddArg(destptr) v.AddArg(srcptr) v.AddArg(mem) return true } } func rewriteValue386_OpXor16_0(v *Value) bool { // match: (Xor16 x y) // cond: // result: (XORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpXor32_0(v *Value) bool { // match: (Xor32 x y) // cond: // result: (XORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpXor8_0(v *Value) bool { // match: (Xor8 x y) // cond: // result: (XORL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(Op386XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValue386_OpZero_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Zero [0] _ mem) // cond: // result: mem for { if v.AuxInt != 0 { break } _ = v.Args[1] mem := v.Args[1] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Zero [1] destptr mem) // cond: // result: (MOVBstoreconst [0] destptr mem) for { if v.AuxInt != 1 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVBstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [2] destptr mem) // cond: // result: (MOVWstoreconst [0] destptr mem) for { if v.AuxInt != 2 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVWstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [4] destptr mem) // cond: // result: (MOVLstoreconst [0] destptr mem) for { if v.AuxInt != 4 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVLstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [3] destptr mem) // cond: // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [0] destptr mem)) for { if v.AuxInt != 3 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVBstoreconst) v.AuxInt = makeValAndOff(0, 2) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVWstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [5] destptr mem) // cond: // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 5 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVBstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [6] destptr mem) // cond: // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 6 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVWstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [7] destptr mem) // cond: // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 7 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVLstoreconst) v.AuxInt = makeValAndOff(0, 3) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s%4 != 0 && s > 4 // result: (Zero [s-s%4] (ADDLconst destptr [s%4]) (MOVLstoreconst [0] destptr mem)) for { s := v.AuxInt _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(s%4 != 0 && s > 4) { break } v.reset(OpZero) v.AuxInt = s - s%4 v0 := b.NewValue0(v.Pos, Op386ADDLconst, typ.UInt32) v0.AuxInt = s % 4 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Zero [8] destptr mem) // cond: // result: (MOVLstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 8 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVLstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValue386_OpZero_10(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config typ := &b.Func.Config.Types _ = typ // match: (Zero [12] destptr mem) // cond: // result: (MOVLstoreconst [makeValAndOff(0,8)] destptr (MOVLstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem))) for { if v.AuxInt != 12 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVLstoreconst) v.AuxInt = makeValAndOff(0, 8) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v0.AuxInt = makeValAndOff(0, 4) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [16] destptr mem) // cond: // result: (MOVLstoreconst [makeValAndOff(0,12)] destptr (MOVLstoreconst [makeValAndOff(0,8)] destptr (MOVLstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)))) for { if v.AuxInt != 16 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(Op386MOVLstoreconst) v.AuxInt = makeValAndOff(0, 12) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v0.AuxInt = makeValAndOff(0, 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v1.AuxInt = makeValAndOff(0, 4) v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, Op386MOVLstoreconst, types.TypeMem) v2.AuxInt = 0 v2.AddArg(destptr) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s > 16 && s <= 4*128 && s%4 == 0 && !config.noDuffDevice // result: (DUFFZERO [1*(128-s/4)] destptr (MOVLconst [0]) mem) for { s := v.AuxInt _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(s > 16 && s <= 4*128 && s%4 == 0 && !config.noDuffDevice) { break } v.reset(Op386DUFFZERO) v.AuxInt = 1 * (128 - s/4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLconst, typ.UInt32) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 4*128 || (config.noDuffDevice && s > 16)) && s%4 == 0 // result: (REPSTOSL destptr (MOVLconst [s/4]) (MOVLconst [0]) mem) for { s := v.AuxInt _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !((s > 4*128 || (config.noDuffDevice && s > 16)) && s%4 == 0) { break } v.reset(Op386REPSTOSL) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, Op386MOVLconst, typ.UInt32) v0.AuxInt = s / 4 v.AddArg(v0) v1 := b.NewValue0(v.Pos, Op386MOVLconst, typ.UInt32) v1.AuxInt = 0 v.AddArg(v1) v.AddArg(mem) return true } return false } func rewriteValue386_OpZeroExt16to32_0(v *Value) bool { // match: (ZeroExt16to32 x) // cond: // result: (MOVWLZX x) for { x := v.Args[0] v.reset(Op386MOVWLZX) v.AddArg(x) return true } } func rewriteValue386_OpZeroExt8to16_0(v *Value) bool { // match: (ZeroExt8to16 x) // cond: // result: (MOVBLZX x) for { x := v.Args[0] v.reset(Op386MOVBLZX) v.AddArg(x) return true } } func rewriteValue386_OpZeroExt8to32_0(v *Value) bool { // match: (ZeroExt8to32 x) // cond: // result: (MOVBLZX x) for { x := v.Args[0] v.reset(Op386MOVBLZX) v.AddArg(x) return true } } func rewriteValue386_OpZeromask_0(v *Value) bool { b := v.Block _ = b // match: (Zeromask x) // cond: // result: (XORLconst [-1] (SBBLcarrymask (CMPLconst x [1]))) for { t := v.Type x := v.Args[0] v.reset(Op386XORLconst) v.AuxInt = -1 v0 := b.NewValue0(v.Pos, Op386SBBLcarrymask, t) v1 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags) v1.AuxInt = 1 v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteBlock386(b *Block) bool { config := b.Func.Config _ = config fe := b.Func.fe _ = fe typ := &config.Types _ = typ switch b.Kind { case Block386EQ: // match: (EQ (InvertFlags cmp) yes no) // cond: // result: (EQ cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386EQ b.SetControl(cmp) b.Aux = nil return true } // match: (EQ (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (EQ (FlagLT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } case Block386GE: // match: (GE (InvertFlags cmp) yes no) // cond: // result: (LE cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386LE b.SetControl(cmp) b.Aux = nil return true } // match: (GE (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (GE (FlagLT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (GE (FlagGT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } case Block386GT: // match: (GT (InvertFlags cmp) yes no) // cond: // result: (LT cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386LT b.SetControl(cmp) b.Aux = nil return true } // match: (GT (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (GT (FlagGT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } case BlockIf: // match: (If (SETL cmp) yes no) // cond: // result: (LT cmp yes no) for { v := b.Control if v.Op != Op386SETL { break } cmp := v.Args[0] b.Kind = Block386LT b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETLE cmp) yes no) // cond: // result: (LE cmp yes no) for { v := b.Control if v.Op != Op386SETLE { break } cmp := v.Args[0] b.Kind = Block386LE b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETG cmp) yes no) // cond: // result: (GT cmp yes no) for { v := b.Control if v.Op != Op386SETG { break } cmp := v.Args[0] b.Kind = Block386GT b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETGE cmp) yes no) // cond: // result: (GE cmp yes no) for { v := b.Control if v.Op != Op386SETGE { break } cmp := v.Args[0] b.Kind = Block386GE b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETEQ cmp) yes no) // cond: // result: (EQ cmp yes no) for { v := b.Control if v.Op != Op386SETEQ { break } cmp := v.Args[0] b.Kind = Block386EQ b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETNE cmp) yes no) // cond: // result: (NE cmp yes no) for { v := b.Control if v.Op != Op386SETNE { break } cmp := v.Args[0] b.Kind = Block386NE b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETB cmp) yes no) // cond: // result: (ULT cmp yes no) for { v := b.Control if v.Op != Op386SETB { break } cmp := v.Args[0] b.Kind = Block386ULT b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETBE cmp) yes no) // cond: // result: (ULE cmp yes no) for { v := b.Control if v.Op != Op386SETBE { break } cmp := v.Args[0] b.Kind = Block386ULE b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETA cmp) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386SETA { break } cmp := v.Args[0] b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETAE cmp) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386SETAE { break } cmp := v.Args[0] b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETO cmp) yes no) // cond: // result: (OS cmp yes no) for { v := b.Control if v.Op != Op386SETO { break } cmp := v.Args[0] b.Kind = Block386OS b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETGF cmp) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386SETGF { break } cmp := v.Args[0] b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETGEF cmp) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386SETGEF { break } cmp := v.Args[0] b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETEQF cmp) yes no) // cond: // result: (EQF cmp yes no) for { v := b.Control if v.Op != Op386SETEQF { break } cmp := v.Args[0] b.Kind = Block386EQF b.SetControl(cmp) b.Aux = nil return true } // match: (If (SETNEF cmp) yes no) // cond: // result: (NEF cmp yes no) for { v := b.Control if v.Op != Op386SETNEF { break } cmp := v.Args[0] b.Kind = Block386NEF b.SetControl(cmp) b.Aux = nil return true } // match: (If cond yes no) // cond: // result: (NE (TESTB cond cond) yes no) for { v := b.Control _ = v cond := b.Control b.Kind = Block386NE v0 := b.NewValue0(v.Pos, Op386TESTB, types.TypeFlags) v0.AddArg(cond) v0.AddArg(cond) b.SetControl(v0) b.Aux = nil return true } case Block386LE: // match: (LE (InvertFlags cmp) yes no) // cond: // result: (GE cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386GE b.SetControl(cmp) b.Aux = nil return true } // match: (LE (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LE (FlagLT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LE (FlagLT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LE (FlagGT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } case Block386LT: // match: (LT (InvertFlags cmp) yes no) // cond: // result: (GT cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386GT b.SetControl(cmp) b.Aux = nil return true } // match: (LT (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LT (FlagLT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LT (FlagGT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } case Block386NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // cond: // result: (LT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETL { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETL { break } if cmp != v_1.Args[0] { break } b.Kind = Block386LT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // cond: // result: (LT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETL { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETL { break } if cmp != v_1.Args[0] { break } b.Kind = Block386LT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // cond: // result: (LE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETLE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETLE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386LE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // cond: // result: (LE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETLE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETLE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386LE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // cond: // result: (GT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETG { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETG { break } if cmp != v_1.Args[0] { break } b.Kind = Block386GT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // cond: // result: (GT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETG { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETG { break } if cmp != v_1.Args[0] { break } b.Kind = Block386GT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // cond: // result: (GE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETGE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETGE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386GE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // cond: // result: (GE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETGE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETGE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386GE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // cond: // result: (EQ cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETEQ { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETEQ { break } if cmp != v_1.Args[0] { break } b.Kind = Block386EQ b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // cond: // result: (EQ cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETEQ { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETEQ { break } if cmp != v_1.Args[0] { break } b.Kind = Block386EQ b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // cond: // result: (NE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETNE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETNE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386NE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // cond: // result: (NE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETNE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETNE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386NE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // cond: // result: (ULT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETB { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETB { break } if cmp != v_1.Args[0] { break } b.Kind = Block386ULT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // cond: // result: (ULT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETB { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETB { break } if cmp != v_1.Args[0] { break } b.Kind = Block386ULT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // cond: // result: (ULE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETBE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETBE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386ULE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // cond: // result: (ULE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETBE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETBE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386ULE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETA { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETA { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETA { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETA { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETAE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETAE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETAE { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETAE { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // cond: // result: (OS cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETO { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETO { break } if cmp != v_1.Args[0] { break } b.Kind = Block386OS b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // cond: // result: (OS cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETO { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETO { break } if cmp != v_1.Args[0] { break } b.Kind = Block386OS b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETGF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETGF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETGF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETGF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETGEF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETGEF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETGEF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETGEF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // cond: // result: (EQF cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETEQF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETEQF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386EQF b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // cond: // result: (EQF cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETEQF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETEQF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386EQF b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // cond: // result: (NEF cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETNEF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETNEF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386NEF b.SetControl(cmp) b.Aux = nil return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // cond: // result: (NEF cmp yes no) for { v := b.Control if v.Op != Op386TESTB { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != Op386SETNEF { break } cmp := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != Op386SETNEF { break } if cmp != v_1.Args[0] { break } b.Kind = Block386NEF b.SetControl(cmp) b.Aux = nil return true } // match: (NE (InvertFlags cmp) yes no) // cond: // result: (NE cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386NE b.SetControl(cmp) b.Aux = nil return true } // match: (NE (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (NE (FlagLT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (NE (FlagGT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (NE (FlagGT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } case Block386UGE: // match: (UGE (InvertFlags cmp) yes no) // cond: // result: (ULE cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386ULE b.SetControl(cmp) b.Aux = nil return true } // match: (UGE (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (UGE (FlagLT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (UGE (FlagGT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } case Block386UGT: // match: (UGT (InvertFlags cmp) yes no) // cond: // result: (ULT cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386ULT b.SetControl(cmp) b.Aux = nil return true } // match: (UGT (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (UGT (FlagGT_ULT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } case Block386ULE: // match: (ULE (InvertFlags cmp) yes no) // cond: // result: (UGE cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386UGE b.SetControl(cmp) b.Aux = nil return true } // match: (ULE (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (ULE (FlagLT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (ULE (FlagLT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (ULE (FlagGT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } case Block386ULT: // match: (ULT (InvertFlags cmp) yes no) // cond: // result: (UGT cmp yes no) for { v := b.Control if v.Op != Op386InvertFlags { break } cmp := v.Args[0] b.Kind = Block386UGT b.SetControl(cmp) b.Aux = nil return true } // match: (ULT (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagLT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (ULT (FlagLT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagLT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != Op386FlagGT_ULT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (ULT (FlagGT_UGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != Op386FlagGT_UGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } } return false } -- diff -- @@ -106,13 +106,13 @@ case Op386MOVBloadidx1: return rewriteValue386_Op386MOVBloadidx1_0(v) case Op386MOVBstore: - return rewriteValue386_Op386MOVBstore_0(v) + return rewriteValue386_Op386MOVBstore_0(v) || rewriteValue386_Op386MOVBstore_10(v) case Op386MOVBstoreconst: return rewriteValue386_Op386MOVBstoreconst_0(v) case Op386MOVBstoreconstidx1: return rewriteValue386_Op386MOVBstoreconstidx1_0(v) case Op386MOVBstoreidx1: - return rewriteValue386_Op386MOVBstoreidx1_0(v) || rewriteValue386_Op386MOVBstoreidx1_10(v) + return rewriteValue386_Op386MOVBstoreidx1_0(v) || rewriteValue386_Op386MOVBstoreidx1_10(v) || rewriteValue386_Op386MOVBstoreidx1_20(v) case Op386MOVLload: return rewriteValue386_Op386MOVLload_0(v) case Op386MOVLloadidx1: @@ -5545,6 +5545,51 @@ v.AddArg(mem) return true } + // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstore [i-1] {s} p w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[2] + p := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != Op386SHRWconst { + break + } + if v_1.AuxInt != 8 { + break + } + w := v_1.Args[0] + x := v.Args[2] + if x.Op != Op386MOVBstore { + break + } + if x.AuxInt != i-1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[2] + if p != x.Args[0] { + break + } + if w != x.Args[1] { + break + } + mem := x.Args[2] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstore) + v.AuxInt = i - 1 + v.Aux = s + v.AddArg(p) + v.AddArg(w) + v.AddArg(mem) + return true + } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) @@ -5590,6 +5635,99 @@ v.AddArg(mem) return true } + // match: (MOVBstore [i] {s} p w x:(MOVBstore {s} [i+1] p (SHRWconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstore [i] {s} p w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[2] + p := v.Args[0] + w := v.Args[1] + x := v.Args[2] + if x.Op != Op386MOVBstore { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[2] + if p != x.Args[0] { + break + } + x_1 := x.Args[1] + if x_1.Op != Op386SHRWconst { + break + } + if x_1.AuxInt != 8 { + break + } + if w != x_1.Args[0] { + break + } + mem := x.Args[2] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstore) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(w) + v.AddArg(mem) + return true + } + return false +} +func rewriteValue386_Op386MOVBstore_10(v *Value) bool { + // match: (MOVBstore [i] {s} p w x:(MOVBstore {s} [i+1] p (SHRLconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstore [i] {s} p w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[2] + p := v.Args[0] + w := v.Args[1] + x := v.Args[2] + if x.Op != Op386MOVBstore { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[2] + if p != x.Args[0] { + break + } + x_1 := x.Args[1] + if x_1.Op != Op386SHRLconst { + break + } + if x_1.AuxInt != 8 { + break + } + if w != x_1.Args[0] { + break + } + mem := x.Args[2] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstore) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(w) + v.AddArg(mem) + return true + } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) @@ -6166,9 +6304,9 @@ v.AddArg(mem) return true } - // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) + // match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) + // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux @@ -6176,10 +6314,12 @@ p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] - if v_2.Op != Op386SHRLconst { + if v_2.Op != Op386SHRWconst { + break + } + if v_2.AuxInt != 8 { break } - j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { @@ -6196,16 +6336,59 @@ break } if idx != x.Args[1] { + break + } + if w != x.Args[2] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { break } - w0 := x.Args[2] - if w0.Op != Op386SHRLconst { + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i - 1 + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + v_2 := v.Args[2] + if v_2.Op != Op386SHRWconst { + break + } + if v_2.AuxInt != 8 { + break + } + w := v_2.Args[0] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i-1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if idx != x.Args[0] { break } - if w0.AuxInt != j-8 { + if p != x.Args[1] { break } - if w != w0.Args[0] { + if w != x.Args[2] { break } mem := x.Args[3] @@ -6217,24 +6400,29 @@ v.Aux = s v.AddArg(p) v.AddArg(idx) - v.AddArg(w0) + v.AddArg(w) v.AddArg(mem) return true } - // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} idx p w0:(SHRLconst [j-8] w) mem)) + return false +} +func rewriteValue386_Op386MOVBstoreidx1_10(v *Value) bool { + // match: (MOVBstoreidx1 [i] {s} idx p (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) + // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] - p := v.Args[0] - idx := v.Args[1] + idx := v.Args[0] + p := v.Args[1] v_2 := v.Args[2] - if v_2.Op != Op386SHRLconst { + if v_2.Op != Op386SHRWconst { + break + } + if v_2.AuxInt != 8 { break } - j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { @@ -6247,20 +6435,63 @@ break } _ = x.Args[3] - if idx != x.Args[0] { + if p != x.Args[0] { + break + } + if idx != x.Args[1] { + break + } + if w != x.Args[2] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i - 1 + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} idx p (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + idx := v.Args[0] + p := v.Args[1] + v_2 := v.Args[2] + if v_2.Op != Op386SHRWconst { + break + } + if v_2.AuxInt != 8 { + break + } + w := v_2.Args[0] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i-1 { break } - if p != x.Args[1] { + if x.Aux != s { break } - w0 := x.Args[2] - if w0.Op != Op386SHRLconst { + _ = x.Args[3] + if idx != x.Args[0] { break } - if w0.AuxInt != j-8 { + if p != x.Args[1] { break } - if w != w0.Args[0] { + if w != x.Args[2] { break } mem := x.Args[3] @@ -6272,13 +6503,523 @@ v.Aux = s v.AddArg(p) v.AddArg(idx) - v.AddArg(w0) + v.AddArg(w) v.AddArg(mem) return true } - return false -} -func rewriteValue386_Op386MOVBstoreidx1_10(v *Value) bool { + // match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRLconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if p != x.Args[0] { + break + } + if idx != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRLconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRLconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if idx != x.Args[0] { + break + } + if p != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRLconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRLconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + idx := v.Args[0] + p := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if p != x.Args[0] { + break + } + if idx != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRLconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRLconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + idx := v.Args[0] + p := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if idx != x.Args[0] { + break + } + if p != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRLconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRWconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if p != x.Args[0] { + break + } + if idx != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRWconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRWconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if idx != x.Args[0] { + break + } + if p != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRWconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRWconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + idx := v.Args[0] + p := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if p != x.Args[0] { + break + } + if idx != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRWconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRWconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + idx := v.Args[0] + p := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if idx != x.Args[0] { + break + } + if p != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRWconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + return false +} +func rewriteValue386_Op386MOVBstoreidx1_20(v *Value) bool { + // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + v_2 := v.Args[2] + if v_2.Op != Op386SHRLconst { + break + } + j := v_2.AuxInt + w := v_2.Args[0] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i-1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if p != x.Args[0] { + break + } + if idx != x.Args[1] { + break + } + w0 := x.Args[2] + if w0.Op != Op386SHRLconst { + break + } + if w0.AuxInt != j-8 { + break + } + if w != w0.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i - 1 + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w0) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} idx p w0:(SHRLconst [j-8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + v_2 := v.Args[2] + if v_2.Op != Op386SHRLconst { + break + } + j := v_2.AuxInt + w := v_2.Args[0] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i-1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if idx != x.Args[0] { + break + } + if p != x.Args[1] { + break + } + w0 := x.Args[2] + if w0.Op != Op386SHRLconst { + break + } + if w0.AuxInt != j-8 { + break + } + if w != w0.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i - 1 + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w0) + v.AddArg(mem) + return true + } // match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) -- diff -- # indent-heuristic: true @@ -106,13 +106,13 @@ case Op386MOVBloadidx1: return rewriteValue386_Op386MOVBloadidx1_0(v) case Op386MOVBstore: - return rewriteValue386_Op386MOVBstore_0(v) + return rewriteValue386_Op386MOVBstore_0(v) || rewriteValue386_Op386MOVBstore_10(v) case Op386MOVBstoreconst: return rewriteValue386_Op386MOVBstoreconst_0(v) case Op386MOVBstoreconstidx1: return rewriteValue386_Op386MOVBstoreconstidx1_0(v) case Op386MOVBstoreidx1: - return rewriteValue386_Op386MOVBstoreidx1_0(v) || rewriteValue386_Op386MOVBstoreidx1_10(v) + return rewriteValue386_Op386MOVBstoreidx1_0(v) || rewriteValue386_Op386MOVBstoreidx1_10(v) || rewriteValue386_Op386MOVBstoreidx1_20(v) case Op386MOVLload: return rewriteValue386_Op386MOVLload_0(v) case Op386MOVLloadidx1: @@ -5545,6 +5545,51 @@ v.AddArg(mem) return true } + // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstore [i-1] {s} p w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[2] + p := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != Op386SHRWconst { + break + } + if v_1.AuxInt != 8 { + break + } + w := v_1.Args[0] + x := v.Args[2] + if x.Op != Op386MOVBstore { + break + } + if x.AuxInt != i-1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[2] + if p != x.Args[0] { + break + } + if w != x.Args[1] { + break + } + mem := x.Args[2] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstore) + v.AuxInt = i - 1 + v.Aux = s + v.AddArg(p) + v.AddArg(w) + v.AddArg(mem) + return true + } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) @@ -5590,6 +5635,99 @@ v.AddArg(mem) return true } + // match: (MOVBstore [i] {s} p w x:(MOVBstore {s} [i+1] p (SHRWconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstore [i] {s} p w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[2] + p := v.Args[0] + w := v.Args[1] + x := v.Args[2] + if x.Op != Op386MOVBstore { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[2] + if p != x.Args[0] { + break + } + x_1 := x.Args[1] + if x_1.Op != Op386SHRWconst { + break + } + if x_1.AuxInt != 8 { + break + } + if w != x_1.Args[0] { + break + } + mem := x.Args[2] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstore) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(w) + v.AddArg(mem) + return true + } + return false +} +func rewriteValue386_Op386MOVBstore_10(v *Value) bool { + // match: (MOVBstore [i] {s} p w x:(MOVBstore {s} [i+1] p (SHRLconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstore [i] {s} p w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[2] + p := v.Args[0] + w := v.Args[1] + x := v.Args[2] + if x.Op != Op386MOVBstore { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[2] + if p != x.Args[0] { + break + } + x_1 := x.Args[1] + if x_1.Op != Op386SHRLconst { + break + } + if x_1.AuxInt != 8 { + break + } + if w != x_1.Args[0] { + break + } + mem := x.Args[2] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstore) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(w) + v.AddArg(mem) + return true + } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) @@ -6166,9 +6304,9 @@ v.AddArg(mem) return true } - // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) + // match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) + // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux @@ -6176,10 +6314,12 @@ p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] - if v_2.Op != Op386SHRLconst { + if v_2.Op != Op386SHRWconst { + break + } + if v_2.AuxInt != 8 { break } - j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { @@ -6198,14 +6338,57 @@ if idx != x.Args[1] { break } - w0 := x.Args[2] - if w0.Op != Op386SHRLconst { + if w != x.Args[2] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i - 1 + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + v_2 := v.Args[2] + if v_2.Op != Op386SHRWconst { + break + } + if v_2.AuxInt != 8 { + break + } + w := v_2.Args[0] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i-1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if idx != x.Args[0] { break } - if w0.AuxInt != j-8 { + if p != x.Args[1] { break } - if w != w0.Args[0] { + if w != x.Args[2] { break } mem := x.Args[3] @@ -6217,24 +6400,29 @@ v.Aux = s v.AddArg(p) v.AddArg(idx) - v.AddArg(w0) + v.AddArg(w) v.AddArg(mem) return true } - // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} idx p w0:(SHRLconst [j-8] w) mem)) + return false +} +func rewriteValue386_Op386MOVBstoreidx1_10(v *Value) bool { + // match: (MOVBstoreidx1 [i] {s} idx p (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) + // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] - p := v.Args[0] - idx := v.Args[1] + idx := v.Args[0] + p := v.Args[1] v_2 := v.Args[2] - if v_2.Op != Op386SHRLconst { + if v_2.Op != Op386SHRWconst { + break + } + if v_2.AuxInt != 8 { break } - j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != Op386MOVBstoreidx1 { @@ -6247,20 +6435,63 @@ break } _ = x.Args[3] - if idx != x.Args[0] { + if p != x.Args[0] { + break + } + if idx != x.Args[1] { + break + } + if w != x.Args[2] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i - 1 + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} idx p (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} idx p w mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + idx := v.Args[0] + p := v.Args[1] + v_2 := v.Args[2] + if v_2.Op != Op386SHRWconst { + break + } + if v_2.AuxInt != 8 { + break + } + w := v_2.Args[0] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i-1 { break } - if p != x.Args[1] { + if x.Aux != s { break } - w0 := x.Args[2] - if w0.Op != Op386SHRLconst { + _ = x.Args[3] + if idx != x.Args[0] { break } - if w0.AuxInt != j-8 { + if p != x.Args[1] { break } - if w != w0.Args[0] { + if w != x.Args[2] { break } mem := x.Args[3] @@ -6272,13 +6503,523 @@ v.Aux = s v.AddArg(p) v.AddArg(idx) - v.AddArg(w0) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRLconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if p != x.Args[0] { + break + } + if idx != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRLconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRLconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if idx != x.Args[0] { + break + } + if p != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRLconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRLconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + idx := v.Args[0] + p := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if p != x.Args[0] { + break + } + if idx != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRLconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRLconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + idx := v.Args[0] + p := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if idx != x.Args[0] { + break + } + if p != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRLconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRWconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if p != x.Args[0] { + break + } + if idx != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRWconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} p idx w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRWconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if idx != x.Args[0] { + break + } + if p != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRWconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} p idx (SHRWconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + idx := v.Args[0] + p := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if p != x.Args[0] { + break + } + if idx != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRWconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} idx p w x:(MOVBstoreidx1 [i+1] {s} idx p (SHRWconst [8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i] {s} p idx w mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + idx := v.Args[0] + p := v.Args[1] + w := v.Args[2] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i+1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if idx != x.Args[0] { + break + } + if p != x.Args[1] { + break + } + x_2 := x.Args[2] + if x_2.Op != Op386SHRWconst { + break + } + if x_2.AuxInt != 8 { + break + } + if w != x_2.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w) + v.AddArg(mem) + return true + } + return false +} +func rewriteValue386_Op386MOVBstoreidx1_20(v *Value) bool { + // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + v_2 := v.Args[2] + if v_2.Op != Op386SHRLconst { + break + } + j := v_2.AuxInt + w := v_2.Args[0] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i-1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if p != x.Args[0] { + break + } + if idx != x.Args[1] { + break + } + w0 := x.Args[2] + if w0.Op != Op386SHRLconst { + break + } + if w0.AuxInt != j-8 { + break + } + if w != w0.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i - 1 + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w0) + v.AddArg(mem) + return true + } + // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} idx p w0:(SHRLconst [j-8] w) mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) + for { + i := v.AuxInt + s := v.Aux + _ = v.Args[3] + p := v.Args[0] + idx := v.Args[1] + v_2 := v.Args[2] + if v_2.Op != Op386SHRLconst { + break + } + j := v_2.AuxInt + w := v_2.Args[0] + x := v.Args[3] + if x.Op != Op386MOVBstoreidx1 { + break + } + if x.AuxInt != i-1 { + break + } + if x.Aux != s { + break + } + _ = x.Args[3] + if idx != x.Args[0] { + break + } + if p != x.Args[1] { + break + } + w0 := x.Args[2] + if w0.Op != Op386SHRLconst { + break + } + if w0.AuxInt != j-8 { + break + } + if w != w0.Args[0] { + break + } + mem := x.Args[3] + if !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(Op386MOVWstoreidx1) + v.AuxInt = i - 1 + v.Aux = s + v.AddArg(p) + v.AddArg(idx) + v.AddArg(w0) v.AddArg(mem) return true } - return false -} -func rewriteValue386_Op386MOVBstoreidx1_10(v *Value) bool { // match: (MOVBstoreidx1 [i] {s} idx p (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) go_4d10d4ad849467f12a1a16a5ade26cc03d8f1a1f_src_cmd_compile_internal_ssa_opGen.go.test000066400000000000000000106406541516001707200346470ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit 4d10d4ad849467f12a1a16a5ade26cc03d8f1a1f file src/cmd/compile/internal/ssa/opGen.go -- x -- // Code generated from _gen/*Ops.go using 'go generate'; DO NOT EDIT. package ssa import ( "cmd/internal/obj" "cmd/internal/obj/arm" "cmd/internal/obj/arm64" "cmd/internal/obj/loong64" "cmd/internal/obj/mips" "cmd/internal/obj/ppc64" "cmd/internal/obj/riscv" "cmd/internal/obj/s390x" "cmd/internal/obj/wasm" "cmd/internal/obj/x86" ) const ( BlockInvalid BlockKind = iota Block386EQ Block386NE Block386LT Block386LE Block386GT Block386GE Block386OS Block386OC Block386ULT Block386ULE Block386UGT Block386UGE Block386EQF Block386NEF Block386ORD Block386NAN BlockAMD64EQ BlockAMD64NE BlockAMD64LT BlockAMD64LE BlockAMD64GT BlockAMD64GE BlockAMD64OS BlockAMD64OC BlockAMD64ULT BlockAMD64ULE BlockAMD64UGT BlockAMD64UGE BlockAMD64EQF BlockAMD64NEF BlockAMD64ORD BlockAMD64NAN BlockAMD64JUMPTABLE BlockARMEQ BlockARMNE BlockARMLT BlockARMLE BlockARMGT BlockARMGE BlockARMULT BlockARMULE BlockARMUGT BlockARMUGE BlockARMLTnoov BlockARMLEnoov BlockARMGTnoov BlockARMGEnoov BlockARM64EQ BlockARM64NE BlockARM64LT BlockARM64LE BlockARM64GT BlockARM64GE BlockARM64ULT BlockARM64ULE BlockARM64UGT BlockARM64UGE BlockARM64Z BlockARM64NZ BlockARM64ZW BlockARM64NZW BlockARM64TBZ BlockARM64TBNZ BlockARM64FLT BlockARM64FLE BlockARM64FGT BlockARM64FGE BlockARM64LTnoov BlockARM64LEnoov BlockARM64GTnoov BlockARM64GEnoov BlockARM64JUMPTABLE BlockLOONG64EQ BlockLOONG64NE BlockLOONG64LTZ BlockLOONG64LEZ BlockLOONG64GTZ BlockLOONG64GEZ BlockLOONG64FPT BlockLOONG64FPF BlockLOONG64BEQ BlockLOONG64BNE BlockLOONG64BGE BlockLOONG64BLT BlockLOONG64BGEU BlockLOONG64BLTU BlockMIPSEQ BlockMIPSNE BlockMIPSLTZ BlockMIPSLEZ BlockMIPSGTZ BlockMIPSGEZ BlockMIPSFPT BlockMIPSFPF BlockMIPS64EQ BlockMIPS64NE BlockMIPS64LTZ BlockMIPS64LEZ BlockMIPS64GTZ BlockMIPS64GEZ BlockMIPS64FPT BlockMIPS64FPF BlockPPC64EQ BlockPPC64NE BlockPPC64LT BlockPPC64LE BlockPPC64GT BlockPPC64GE BlockPPC64FLT BlockPPC64FLE BlockPPC64FGT BlockPPC64FGE BlockRISCV64BEQ BlockRISCV64BNE BlockRISCV64BLT BlockRISCV64BGE BlockRISCV64BLTU BlockRISCV64BGEU BlockRISCV64BEQZ BlockRISCV64BNEZ BlockRISCV64BLEZ BlockRISCV64BGEZ BlockRISCV64BLTZ BlockRISCV64BGTZ BlockS390XBRC BlockS390XCRJ BlockS390XCGRJ BlockS390XCLRJ BlockS390XCLGRJ BlockS390XCIJ BlockS390XCGIJ BlockS390XCLIJ BlockS390XCLGIJ BlockPlain BlockIf BlockDefer BlockRet BlockRetJmp BlockExit BlockJumpTable BlockFirst ) var blockString = [...]string{ BlockInvalid: "BlockInvalid", Block386EQ: "EQ", Block386NE: "NE", Block386LT: "LT", Block386LE: "LE", Block386GT: "GT", Block386GE: "GE", Block386OS: "OS", Block386OC: "OC", Block386ULT: "ULT", Block386ULE: "ULE", Block386UGT: "UGT", Block386UGE: "UGE", Block386EQF: "EQF", Block386NEF: "NEF", Block386ORD: "ORD", Block386NAN: "NAN", BlockAMD64EQ: "EQ", BlockAMD64NE: "NE", BlockAMD64LT: "LT", BlockAMD64LE: "LE", BlockAMD64GT: "GT", BlockAMD64GE: "GE", BlockAMD64OS: "OS", BlockAMD64OC: "OC", BlockAMD64ULT: "ULT", BlockAMD64ULE: "ULE", BlockAMD64UGT: "UGT", BlockAMD64UGE: "UGE", BlockAMD64EQF: "EQF", BlockAMD64NEF: "NEF", BlockAMD64ORD: "ORD", BlockAMD64NAN: "NAN", BlockAMD64JUMPTABLE: "JUMPTABLE", BlockARMEQ: "EQ", BlockARMNE: "NE", BlockARMLT: "LT", BlockARMLE: "LE", BlockARMGT: "GT", BlockARMGE: "GE", BlockARMULT: "ULT", BlockARMULE: "ULE", BlockARMUGT: "UGT", BlockARMUGE: "UGE", BlockARMLTnoov: "LTnoov", BlockARMLEnoov: "LEnoov", BlockARMGTnoov: "GTnoov", BlockARMGEnoov: "GEnoov", BlockARM64EQ: "EQ", BlockARM64NE: "NE", BlockARM64LT: "LT", BlockARM64LE: "LE", BlockARM64GT: "GT", BlockARM64GE: "GE", BlockARM64ULT: "ULT", BlockARM64ULE: "ULE", BlockARM64UGT: "UGT", BlockARM64UGE: "UGE", BlockARM64Z: "Z", BlockARM64NZ: "NZ", BlockARM64ZW: "ZW", BlockARM64NZW: "NZW", BlockARM64TBZ: "TBZ", BlockARM64TBNZ: "TBNZ", BlockARM64FLT: "FLT", BlockARM64FLE: "FLE", BlockARM64FGT: "FGT", BlockARM64FGE: "FGE", BlockARM64LTnoov: "LTnoov", BlockARM64LEnoov: "LEnoov", BlockARM64GTnoov: "GTnoov", BlockARM64GEnoov: "GEnoov", BlockARM64JUMPTABLE: "JUMPTABLE", BlockLOONG64EQ: "EQ", BlockLOONG64NE: "NE", BlockLOONG64LTZ: "LTZ", BlockLOONG64LEZ: "LEZ", BlockLOONG64GTZ: "GTZ", BlockLOONG64GEZ: "GEZ", BlockLOONG64FPT: "FPT", BlockLOONG64FPF: "FPF", BlockLOONG64BEQ: "BEQ", BlockLOONG64BNE: "BNE", BlockLOONG64BGE: "BGE", BlockLOONG64BLT: "BLT", BlockLOONG64BGEU: "BGEU", BlockLOONG64BLTU: "BLTU", BlockMIPSEQ: "EQ", BlockMIPSNE: "NE", BlockMIPSLTZ: "LTZ", BlockMIPSLEZ: "LEZ", BlockMIPSGTZ: "GTZ", BlockMIPSGEZ: "GEZ", BlockMIPSFPT: "FPT", BlockMIPSFPF: "FPF", BlockMIPS64EQ: "EQ", BlockMIPS64NE: "NE", BlockMIPS64LTZ: "LTZ", BlockMIPS64LEZ: "LEZ", BlockMIPS64GTZ: "GTZ", BlockMIPS64GEZ: "GEZ", BlockMIPS64FPT: "FPT", BlockMIPS64FPF: "FPF", BlockPPC64EQ: "EQ", BlockPPC64NE: "NE", BlockPPC64LT: "LT", BlockPPC64LE: "LE", BlockPPC64GT: "GT", BlockPPC64GE: "GE", BlockPPC64FLT: "FLT", BlockPPC64FLE: "FLE", BlockPPC64FGT: "FGT", BlockPPC64FGE: "FGE", BlockRISCV64BEQ: "BEQ", BlockRISCV64BNE: "BNE", BlockRISCV64BLT: "BLT", BlockRISCV64BGE: "BGE", BlockRISCV64BLTU: "BLTU", BlockRISCV64BGEU: "BGEU", BlockRISCV64BEQZ: "BEQZ", BlockRISCV64BNEZ: "BNEZ", BlockRISCV64BLEZ: "BLEZ", BlockRISCV64BGEZ: "BGEZ", BlockRISCV64BLTZ: "BLTZ", BlockRISCV64BGTZ: "BGTZ", BlockS390XBRC: "BRC", BlockS390XCRJ: "CRJ", BlockS390XCGRJ: "CGRJ", BlockS390XCLRJ: "CLRJ", BlockS390XCLGRJ: "CLGRJ", BlockS390XCIJ: "CIJ", BlockS390XCGIJ: "CGIJ", BlockS390XCLIJ: "CLIJ", BlockS390XCLGIJ: "CLGIJ", BlockPlain: "Plain", BlockIf: "If", BlockDefer: "Defer", BlockRet: "Ret", BlockRetJmp: "RetJmp", BlockExit: "Exit", BlockJumpTable: "JumpTable", BlockFirst: "First", } func (k BlockKind) String() string { return blockString[k] } func (k BlockKind) AuxIntType() string { switch k { case BlockARM64TBZ: return "int64" case BlockARM64TBNZ: return "int64" case BlockS390XCIJ: return "int8" case BlockS390XCGIJ: return "int8" case BlockS390XCLIJ: return "uint8" case BlockS390XCLGIJ: return "uint8" } return "" } const ( OpInvalid Op = iota Op386ADDSS Op386ADDSD Op386SUBSS Op386SUBSD Op386MULSS Op386MULSD Op386DIVSS Op386DIVSD Op386MOVSSload Op386MOVSDload Op386MOVSSconst Op386MOVSDconst Op386MOVSSloadidx1 Op386MOVSSloadidx4 Op386MOVSDloadidx1 Op386MOVSDloadidx8 Op386MOVSSstore Op386MOVSDstore Op386MOVSSstoreidx1 Op386MOVSSstoreidx4 Op386MOVSDstoreidx1 Op386MOVSDstoreidx8 Op386ADDSSload Op386ADDSDload Op386SUBSSload Op386SUBSDload Op386MULSSload Op386MULSDload Op386DIVSSload Op386DIVSDload Op386ADDL Op386ADDLconst Op386ADDLcarry Op386ADDLconstcarry Op386ADCL Op386ADCLconst Op386SUBL Op386SUBLconst Op386SUBLcarry Op386SUBLconstcarry Op386SBBL Op386SBBLconst Op386MULL Op386MULLconst Op386MULLU Op386HMULL Op386HMULLU Op386MULLQU Op386AVGLU Op386DIVL Op386DIVW Op386DIVLU Op386DIVWU Op386MODL Op386MODW Op386MODLU Op386MODWU Op386ANDL Op386ANDLconst Op386ORL Op386ORLconst Op386XORL Op386XORLconst Op386CMPL Op386CMPW Op386CMPB Op386CMPLconst Op386CMPWconst Op386CMPBconst Op386CMPLload Op386CMPWload Op386CMPBload Op386CMPLconstload Op386CMPWconstload Op386CMPBconstload Op386UCOMISS Op386UCOMISD Op386TESTL Op386TESTW Op386TESTB Op386TESTLconst Op386TESTWconst Op386TESTBconst Op386SHLL Op386SHLLconst Op386SHRL Op386SHRW Op386SHRB Op386SHRLconst Op386SHRWconst Op386SHRBconst Op386SARL Op386SARW Op386SARB Op386SARLconst Op386SARWconst Op386SARBconst Op386ROLL Op386ROLW Op386ROLB Op386ROLLconst Op386ROLWconst Op386ROLBconst Op386ADDLload Op386SUBLload Op386MULLload Op386ANDLload Op386ORLload Op386XORLload Op386ADDLloadidx4 Op386SUBLloadidx4 Op386MULLloadidx4 Op386ANDLloadidx4 Op386ORLloadidx4 Op386XORLloadidx4 Op386NEGL Op386NOTL Op386BSFL Op386BSFW Op386LoweredCtz32 Op386LoweredCtz64 Op386BSRL Op386BSRW Op386BSWAPL Op386SQRTSD Op386SQRTSS Op386SBBLcarrymask Op386SETEQ Op386SETNE Op386SETL Op386SETLE Op386SETG Op386SETGE Op386SETB Op386SETBE Op386SETA Op386SETAE Op386SETO Op386SETEQF Op386SETNEF Op386SETORD Op386SETNAN Op386SETGF Op386SETGEF Op386MOVBLSX Op386MOVBLZX Op386MOVWLSX Op386MOVWLZX Op386MOVLconst Op386CVTTSD2SL Op386CVTTSS2SL Op386CVTSL2SS Op386CVTSL2SD Op386CVTSD2SS Op386CVTSS2SD Op386PXOR Op386LEAL Op386LEAL1 Op386LEAL2 Op386LEAL4 Op386LEAL8 Op386MOVBload Op386MOVBLSXload Op386MOVWload Op386MOVWLSXload Op386MOVLload Op386MOVBstore Op386MOVWstore Op386MOVLstore Op386ADDLmodify Op386SUBLmodify Op386ANDLmodify Op386ORLmodify Op386XORLmodify Op386ADDLmodifyidx4 Op386SUBLmodifyidx4 Op386ANDLmodifyidx4 Op386ORLmodifyidx4 Op386XORLmodifyidx4 Op386ADDLconstmodify Op386ANDLconstmodify Op386ORLconstmodify Op386XORLconstmodify Op386ADDLconstmodifyidx4 Op386ANDLconstmodifyidx4 Op386ORLconstmodifyidx4 Op386XORLconstmodifyidx4 Op386MOVBloadidx1 Op386MOVWloadidx1 Op386MOVWloadidx2 Op386MOVLloadidx1 Op386MOVLloadidx4 Op386MOVBstoreidx1 Op386MOVWstoreidx1 Op386MOVWstoreidx2 Op386MOVLstoreidx1 Op386MOVLstoreidx4 Op386MOVBstoreconst Op386MOVWstoreconst Op386MOVLstoreconst Op386MOVBstoreconstidx1 Op386MOVWstoreconstidx1 Op386MOVWstoreconstidx2 Op386MOVLstoreconstidx1 Op386MOVLstoreconstidx4 Op386DUFFZERO Op386REPSTOSL Op386CALLstatic Op386CALLtail Op386CALLclosure Op386CALLinter Op386DUFFCOPY Op386REPMOVSL Op386InvertFlags Op386LoweredGetG Op386LoweredGetClosurePtr Op386LoweredGetCallerPC Op386LoweredGetCallerSP Op386LoweredNilCheck Op386LoweredWB Op386LoweredPanicBoundsA Op386LoweredPanicBoundsB Op386LoweredPanicBoundsC Op386LoweredPanicExtendA Op386LoweredPanicExtendB Op386LoweredPanicExtendC Op386FlagEQ Op386FlagLT_ULT Op386FlagLT_UGT Op386FlagGT_UGT Op386FlagGT_ULT Op386MOVSSconst1 Op386MOVSDconst1 Op386MOVSSconst2 Op386MOVSDconst2 OpAMD64ADDSS OpAMD64ADDSD OpAMD64SUBSS OpAMD64SUBSD OpAMD64MULSS OpAMD64MULSD OpAMD64DIVSS OpAMD64DIVSD OpAMD64MOVSSload OpAMD64MOVSDload OpAMD64MOVSSconst OpAMD64MOVSDconst OpAMD64MOVSSloadidx1 OpAMD64MOVSSloadidx4 OpAMD64MOVSDloadidx1 OpAMD64MOVSDloadidx8 OpAMD64MOVSSstore OpAMD64MOVSDstore OpAMD64MOVSSstoreidx1 OpAMD64MOVSSstoreidx4 OpAMD64MOVSDstoreidx1 OpAMD64MOVSDstoreidx8 OpAMD64ADDSSload OpAMD64ADDSDload OpAMD64SUBSSload OpAMD64SUBSDload OpAMD64MULSSload OpAMD64MULSDload OpAMD64DIVSSload OpAMD64DIVSDload OpAMD64ADDSSloadidx1 OpAMD64ADDSSloadidx4 OpAMD64ADDSDloadidx1 OpAMD64ADDSDloadidx8 OpAMD64SUBSSloadidx1 OpAMD64SUBSSloadidx4 OpAMD64SUBSDloadidx1 OpAMD64SUBSDloadidx8 OpAMD64MULSSloadidx1 OpAMD64MULSSloadidx4 OpAMD64MULSDloadidx1 OpAMD64MULSDloadidx8 OpAMD64DIVSSloadidx1 OpAMD64DIVSSloadidx4 OpAMD64DIVSDloadidx1 OpAMD64DIVSDloadidx8 OpAMD64ADDQ OpAMD64ADDL OpAMD64ADDQconst OpAMD64ADDLconst OpAMD64ADDQconstmodify OpAMD64ADDLconstmodify OpAMD64SUBQ OpAMD64SUBL OpAMD64SUBQconst OpAMD64SUBLconst OpAMD64MULQ OpAMD64MULL OpAMD64MULQconst OpAMD64MULLconst OpAMD64MULLU OpAMD64MULQU OpAMD64HMULQ OpAMD64HMULL OpAMD64HMULQU OpAMD64HMULLU OpAMD64AVGQU OpAMD64DIVQ OpAMD64DIVL OpAMD64DIVW OpAMD64DIVQU OpAMD64DIVLU OpAMD64DIVWU OpAMD64NEGLflags OpAMD64ADDQcarry OpAMD64ADCQ OpAMD64ADDQconstcarry OpAMD64ADCQconst OpAMD64SUBQborrow OpAMD64SBBQ OpAMD64SUBQconstborrow OpAMD64SBBQconst OpAMD64MULQU2 OpAMD64DIVQU2 OpAMD64ANDQ OpAMD64ANDL OpAMD64ANDQconst OpAMD64ANDLconst OpAMD64ANDQconstmodify OpAMD64ANDLconstmodify OpAMD64ORQ OpAMD64ORL OpAMD64ORQconst OpAMD64ORLconst OpAMD64ORQconstmodify OpAMD64ORLconstmodify OpAMD64XORQ OpAMD64XORL OpAMD64XORQconst OpAMD64XORLconst OpAMD64XORQconstmodify OpAMD64XORLconstmodify OpAMD64CMPQ OpAMD64CMPL OpAMD64CMPW OpAMD64CMPB OpAMD64CMPQconst OpAMD64CMPLconst OpAMD64CMPWconst OpAMD64CMPBconst OpAMD64CMPQload OpAMD64CMPLload OpAMD64CMPWload OpAMD64CMPBload OpAMD64CMPQconstload OpAMD64CMPLconstload OpAMD64CMPWconstload OpAMD64CMPBconstload OpAMD64CMPQloadidx8 OpAMD64CMPQloadidx1 OpAMD64CMPLloadidx4 OpAMD64CMPLloadidx1 OpAMD64CMPWloadidx2 OpAMD64CMPWloadidx1 OpAMD64CMPBloadidx1 OpAMD64CMPQconstloadidx8 OpAMD64CMPQconstloadidx1 OpAMD64CMPLconstloadidx4 OpAMD64CMPLconstloadidx1 OpAMD64CMPWconstloadidx2 OpAMD64CMPWconstloadidx1 OpAMD64CMPBconstloadidx1 OpAMD64UCOMISS OpAMD64UCOMISD OpAMD64BTL OpAMD64BTQ OpAMD64BTCL OpAMD64BTCQ OpAMD64BTRL OpAMD64BTRQ OpAMD64BTSL OpAMD64BTSQ OpAMD64BTLconst OpAMD64BTQconst OpAMD64BTCQconst OpAMD64BTRQconst OpAMD64BTSQconst OpAMD64BTSQconstmodify OpAMD64BTRQconstmodify OpAMD64BTCQconstmodify OpAMD64TESTQ OpAMD64TESTL OpAMD64TESTW OpAMD64TESTB OpAMD64TESTQconst OpAMD64TESTLconst OpAMD64TESTWconst OpAMD64TESTBconst OpAMD64SHLQ OpAMD64SHLL OpAMD64SHLQconst OpAMD64SHLLconst OpAMD64SHRQ OpAMD64SHRL OpAMD64SHRW OpAMD64SHRB OpAMD64SHRQconst OpAMD64SHRLconst OpAMD64SHRWconst OpAMD64SHRBconst OpAMD64SARQ OpAMD64SARL OpAMD64SARW OpAMD64SARB OpAMD64SARQconst OpAMD64SARLconst OpAMD64SARWconst OpAMD64SARBconst OpAMD64SHRDQ OpAMD64SHLDQ OpAMD64ROLQ OpAMD64ROLL OpAMD64ROLW OpAMD64ROLB OpAMD64RORQ OpAMD64RORL OpAMD64RORW OpAMD64RORB OpAMD64ROLQconst OpAMD64ROLLconst OpAMD64ROLWconst OpAMD64ROLBconst OpAMD64ADDLload OpAMD64ADDQload OpAMD64SUBQload OpAMD64SUBLload OpAMD64ANDLload OpAMD64ANDQload OpAMD64ORQload OpAMD64ORLload OpAMD64XORQload OpAMD64XORLload OpAMD64ADDLloadidx1 OpAMD64ADDLloadidx4 OpAMD64ADDLloadidx8 OpAMD64ADDQloadidx1 OpAMD64ADDQloadidx8 OpAMD64SUBLloadidx1 OpAMD64SUBLloadidx4 OpAMD64SUBLloadidx8 OpAMD64SUBQloadidx1 OpAMD64SUBQloadidx8 OpAMD64ANDLloadidx1 OpAMD64ANDLloadidx4 OpAMD64ANDLloadidx8 OpAMD64ANDQloadidx1 OpAMD64ANDQloadidx8 OpAMD64ORLloadidx1 OpAMD64ORLloadidx4 OpAMD64ORLloadidx8 OpAMD64ORQloadidx1 OpAMD64ORQloadidx8 OpAMD64XORLloadidx1 OpAMD64XORLloadidx4 OpAMD64XORLloadidx8 OpAMD64XORQloadidx1 OpAMD64XORQloadidx8 OpAMD64ADDQmodify OpAMD64SUBQmodify OpAMD64ANDQmodify OpAMD64ORQmodify OpAMD64XORQmodify OpAMD64ADDLmodify OpAMD64SUBLmodify OpAMD64ANDLmodify OpAMD64ORLmodify OpAMD64XORLmodify OpAMD64ADDQmodifyidx1 OpAMD64ADDQmodifyidx8 OpAMD64SUBQmodifyidx1 OpAMD64SUBQmodifyidx8 OpAMD64ANDQmodifyidx1 OpAMD64ANDQmodifyidx8 OpAMD64ORQmodifyidx1 OpAMD64ORQmodifyidx8 OpAMD64XORQmodifyidx1 OpAMD64XORQmodifyidx8 OpAMD64ADDLmodifyidx1 OpAMD64ADDLmodifyidx4 OpAMD64ADDLmodifyidx8 OpAMD64SUBLmodifyidx1 OpAMD64SUBLmodifyidx4 OpAMD64SUBLmodifyidx8 OpAMD64ANDLmodifyidx1 OpAMD64ANDLmodifyidx4 OpAMD64ANDLmodifyidx8 OpAMD64ORLmodifyidx1 OpAMD64ORLmodifyidx4 OpAMD64ORLmodifyidx8 OpAMD64XORLmodifyidx1 OpAMD64XORLmodifyidx4 OpAMD64XORLmodifyidx8 OpAMD64ADDQconstmodifyidx1 OpAMD64ADDQconstmodifyidx8 OpAMD64ANDQconstmodifyidx1 OpAMD64ANDQconstmodifyidx8 OpAMD64ORQconstmodifyidx1 OpAMD64ORQconstmodifyidx8 OpAMD64XORQconstmodifyidx1 OpAMD64XORQconstmodifyidx8 OpAMD64ADDLconstmodifyidx1 OpAMD64ADDLconstmodifyidx4 OpAMD64ADDLconstmodifyidx8 OpAMD64ANDLconstmodifyidx1 OpAMD64ANDLconstmodifyidx4 OpAMD64ANDLconstmodifyidx8 OpAMD64ORLconstmodifyidx1 OpAMD64ORLconstmodifyidx4 OpAMD64ORLconstmodifyidx8 OpAMD64XORLconstmodifyidx1 OpAMD64XORLconstmodifyidx4 OpAMD64XORLconstmodifyidx8 OpAMD64NEGQ OpAMD64NEGL OpAMD64NOTQ OpAMD64NOTL OpAMD64BSFQ OpAMD64BSFL OpAMD64BSRQ OpAMD64BSRL OpAMD64CMOVQEQ OpAMD64CMOVQNE OpAMD64CMOVQLT OpAMD64CMOVQGT OpAMD64CMOVQLE OpAMD64CMOVQGE OpAMD64CMOVQLS OpAMD64CMOVQHI OpAMD64CMOVQCC OpAMD64CMOVQCS OpAMD64CMOVLEQ OpAMD64CMOVLNE OpAMD64CMOVLLT OpAMD64CMOVLGT OpAMD64CMOVLLE OpAMD64CMOVLGE OpAMD64CMOVLLS OpAMD64CMOVLHI OpAMD64CMOVLCC OpAMD64CMOVLCS OpAMD64CMOVWEQ OpAMD64CMOVWNE OpAMD64CMOVWLT OpAMD64CMOVWGT OpAMD64CMOVWLE OpAMD64CMOVWGE OpAMD64CMOVWLS OpAMD64CMOVWHI OpAMD64CMOVWCC OpAMD64CMOVWCS OpAMD64CMOVQEQF OpAMD64CMOVQNEF OpAMD64CMOVQGTF OpAMD64CMOVQGEF OpAMD64CMOVLEQF OpAMD64CMOVLNEF OpAMD64CMOVLGTF OpAMD64CMOVLGEF OpAMD64CMOVWEQF OpAMD64CMOVWNEF OpAMD64CMOVWGTF OpAMD64CMOVWGEF OpAMD64BSWAPQ OpAMD64BSWAPL OpAMD64POPCNTQ OpAMD64POPCNTL OpAMD64SQRTSD OpAMD64SQRTSS OpAMD64ROUNDSD OpAMD64LoweredRound32F OpAMD64LoweredRound64F OpAMD64VFMADD231SS OpAMD64VFMADD231SD OpAMD64MINSD OpAMD64MINSS OpAMD64SBBQcarrymask OpAMD64SBBLcarrymask OpAMD64SETEQ OpAMD64SETNE OpAMD64SETL OpAMD64SETLE OpAMD64SETG OpAMD64SETGE OpAMD64SETB OpAMD64SETBE OpAMD64SETA OpAMD64SETAE OpAMD64SETO OpAMD64SETEQstore OpAMD64SETNEstore OpAMD64SETLstore OpAMD64SETLEstore OpAMD64SETGstore OpAMD64SETGEstore OpAMD64SETBstore OpAMD64SETBEstore OpAMD64SETAstore OpAMD64SETAEstore OpAMD64SETEQstoreidx1 OpAMD64SETNEstoreidx1 OpAMD64SETLstoreidx1 OpAMD64SETLEstoreidx1 OpAMD64SETGstoreidx1 OpAMD64SETGEstoreidx1 OpAMD64SETBstoreidx1 OpAMD64SETBEstoreidx1 OpAMD64SETAstoreidx1 OpAMD64SETAEstoreidx1 OpAMD64SETEQF OpAMD64SETNEF OpAMD64SETORD OpAMD64SETNAN OpAMD64SETGF OpAMD64SETGEF OpAMD64MOVBQSX OpAMD64MOVBQZX OpAMD64MOVWQSX OpAMD64MOVWQZX OpAMD64MOVLQSX OpAMD64MOVLQZX OpAMD64MOVLconst OpAMD64MOVQconst OpAMD64CVTTSD2SL OpAMD64CVTTSD2SQ OpAMD64CVTTSS2SL OpAMD64CVTTSS2SQ OpAMD64CVTSL2SS OpAMD64CVTSL2SD OpAMD64CVTSQ2SS OpAMD64CVTSQ2SD OpAMD64CVTSD2SS OpAMD64CVTSS2SD OpAMD64MOVQi2f OpAMD64MOVQf2i OpAMD64MOVLi2f OpAMD64MOVLf2i OpAMD64PXOR OpAMD64POR OpAMD64LEAQ OpAMD64LEAL OpAMD64LEAW OpAMD64LEAQ1 OpAMD64LEAL1 OpAMD64LEAW1 OpAMD64LEAQ2 OpAMD64LEAL2 OpAMD64LEAW2 OpAMD64LEAQ4 OpAMD64LEAL4 OpAMD64LEAW4 OpAMD64LEAQ8 OpAMD64LEAL8 OpAMD64LEAW8 OpAMD64MOVBload OpAMD64MOVBQSXload OpAMD64MOVWload OpAMD64MOVWQSXload OpAMD64MOVLload OpAMD64MOVLQSXload OpAMD64MOVQload OpAMD64MOVBstore OpAMD64MOVWstore OpAMD64MOVLstore OpAMD64MOVQstore OpAMD64MOVOload OpAMD64MOVOstore OpAMD64MOVBloadidx1 OpAMD64MOVWloadidx1 OpAMD64MOVWloadidx2 OpAMD64MOVLloadidx1 OpAMD64MOVLloadidx4 OpAMD64MOVLloadidx8 OpAMD64MOVQloadidx1 OpAMD64MOVQloadidx8 OpAMD64MOVBstoreidx1 OpAMD64MOVWstoreidx1 OpAMD64MOVWstoreidx2 OpAMD64MOVLstoreidx1 OpAMD64MOVLstoreidx4 OpAMD64MOVLstoreidx8 OpAMD64MOVQstoreidx1 OpAMD64MOVQstoreidx8 OpAMD64MOVBstoreconst OpAMD64MOVWstoreconst OpAMD64MOVLstoreconst OpAMD64MOVQstoreconst OpAMD64MOVOstoreconst OpAMD64MOVBstoreconstidx1 OpAMD64MOVWstoreconstidx1 OpAMD64MOVWstoreconstidx2 OpAMD64MOVLstoreconstidx1 OpAMD64MOVLstoreconstidx4 OpAMD64MOVQstoreconstidx1 OpAMD64MOVQstoreconstidx8 OpAMD64DUFFZERO OpAMD64REPSTOSQ OpAMD64CALLstatic OpAMD64CALLtail OpAMD64CALLclosure OpAMD64CALLinter OpAMD64DUFFCOPY OpAMD64REPMOVSQ OpAMD64InvertFlags OpAMD64LoweredGetG OpAMD64LoweredGetClosurePtr OpAMD64LoweredGetCallerPC OpAMD64LoweredGetCallerSP OpAMD64LoweredNilCheck OpAMD64LoweredWB OpAMD64LoweredHasCPUFeature OpAMD64LoweredPanicBoundsA OpAMD64LoweredPanicBoundsB OpAMD64LoweredPanicBoundsC OpAMD64FlagEQ OpAMD64FlagLT_ULT OpAMD64FlagLT_UGT OpAMD64FlagGT_UGT OpAMD64FlagGT_ULT OpAMD64MOVBatomicload OpAMD64MOVLatomicload OpAMD64MOVQatomicload OpAMD64XCHGB OpAMD64XCHGL OpAMD64XCHGQ OpAMD64XADDLlock OpAMD64XADDQlock OpAMD64AddTupleFirst32 OpAMD64AddTupleFirst64 OpAMD64CMPXCHGLlock OpAMD64CMPXCHGQlock OpAMD64ANDBlock OpAMD64ANDLlock OpAMD64ANDQlock OpAMD64ORBlock OpAMD64ORLlock OpAMD64ORQlock OpAMD64LoweredAtomicAnd64 OpAMD64LoweredAtomicAnd32 OpAMD64LoweredAtomicOr64 OpAMD64LoweredAtomicOr32 OpAMD64PrefetchT0 OpAMD64PrefetchNTA OpAMD64ANDNQ OpAMD64ANDNL OpAMD64BLSIQ OpAMD64BLSIL OpAMD64BLSMSKQ OpAMD64BLSMSKL OpAMD64BLSRQ OpAMD64BLSRL OpAMD64TZCNTQ OpAMD64TZCNTL OpAMD64LZCNTQ OpAMD64LZCNTL OpAMD64MOVBEWstore OpAMD64MOVBELload OpAMD64MOVBELstore OpAMD64MOVBEQload OpAMD64MOVBEQstore OpAMD64MOVBELloadidx1 OpAMD64MOVBELloadidx4 OpAMD64MOVBELloadidx8 OpAMD64MOVBEQloadidx1 OpAMD64MOVBEQloadidx8 OpAMD64MOVBEWstoreidx1 OpAMD64MOVBEWstoreidx2 OpAMD64MOVBELstoreidx1 OpAMD64MOVBELstoreidx4 OpAMD64MOVBELstoreidx8 OpAMD64MOVBEQstoreidx1 OpAMD64MOVBEQstoreidx8 OpAMD64SARXQ OpAMD64SARXL OpAMD64SHLXQ OpAMD64SHLXL OpAMD64SHRXQ OpAMD64SHRXL OpAMD64SARXLload OpAMD64SARXQload OpAMD64SHLXLload OpAMD64SHLXQload OpAMD64SHRXLload OpAMD64SHRXQload OpAMD64SARXLloadidx1 OpAMD64SARXLloadidx4 OpAMD64SARXLloadidx8 OpAMD64SARXQloadidx1 OpAMD64SARXQloadidx8 OpAMD64SHLXLloadidx1 OpAMD64SHLXLloadidx4 OpAMD64SHLXLloadidx8 OpAMD64SHLXQloadidx1 OpAMD64SHLXQloadidx8 OpAMD64SHRXLloadidx1 OpAMD64SHRXLloadidx4 OpAMD64SHRXLloadidx8 OpAMD64SHRXQloadidx1 OpAMD64SHRXQloadidx8 OpAMD64PUNPCKLBW OpAMD64PSHUFLW OpAMD64PSHUFBbroadcast OpAMD64VPBROADCASTB OpAMD64PSIGNB OpAMD64PCMPEQB OpAMD64PMOVMSKB OpARMADD OpARMADDconst OpARMSUB OpARMSUBconst OpARMRSB OpARMRSBconst OpARMMUL OpARMHMUL OpARMHMULU OpARMCALLudiv OpARMADDS OpARMADDSconst OpARMADC OpARMADCconst OpARMSUBS OpARMSUBSconst OpARMRSBSconst OpARMSBC OpARMSBCconst OpARMRSCconst OpARMMULLU OpARMMULA OpARMMULS OpARMADDF OpARMADDD OpARMSUBF OpARMSUBD OpARMMULF OpARMMULD OpARMNMULF OpARMNMULD OpARMDIVF OpARMDIVD OpARMMULAF OpARMMULAD OpARMMULSF OpARMMULSD OpARMFMULAD OpARMAND OpARMANDconst OpARMOR OpARMORconst OpARMXOR OpARMXORconst OpARMBIC OpARMBICconst OpARMBFX OpARMBFXU OpARMMVN OpARMNEGF OpARMNEGD OpARMSQRTD OpARMSQRTF OpARMABSD OpARMCLZ OpARMREV OpARMREV16 OpARMRBIT OpARMSLL OpARMSLLconst OpARMSRL OpARMSRLconst OpARMSRA OpARMSRAconst OpARMSRR OpARMSRRconst OpARMADDshiftLL OpARMADDshiftRL OpARMADDshiftRA OpARMSUBshiftLL OpARMSUBshiftRL OpARMSUBshiftRA OpARMRSBshiftLL OpARMRSBshiftRL OpARMRSBshiftRA OpARMANDshiftLL OpARMANDshiftRL OpARMANDshiftRA OpARMORshiftLL OpARMORshiftRL OpARMORshiftRA OpARMXORshiftLL OpARMXORshiftRL OpARMXORshiftRA OpARMXORshiftRR OpARMBICshiftLL OpARMBICshiftRL OpARMBICshiftRA OpARMMVNshiftLL OpARMMVNshiftRL OpARMMVNshiftRA OpARMADCshiftLL OpARMADCshiftRL OpARMADCshiftRA OpARMSBCshiftLL OpARMSBCshiftRL OpARMSBCshiftRA OpARMRSCshiftLL OpARMRSCshiftRL OpARMRSCshiftRA OpARMADDSshiftLL OpARMADDSshiftRL OpARMADDSshiftRA OpARMSUBSshiftLL OpARMSUBSshiftRL OpARMSUBSshiftRA OpARMRSBSshiftLL OpARMRSBSshiftRL OpARMRSBSshiftRA OpARMADDshiftLLreg OpARMADDshiftRLreg OpARMADDshiftRAreg OpARMSUBshiftLLreg OpARMSUBshiftRLreg OpARMSUBshiftRAreg OpARMRSBshiftLLreg OpARMRSBshiftRLreg OpARMRSBshiftRAreg OpARMANDshiftLLreg OpARMANDshiftRLreg OpARMANDshiftRAreg OpARMORshiftLLreg OpARMORshiftRLreg OpARMORshiftRAreg OpARMXORshiftLLreg OpARMXORshiftRLreg OpARMXORshiftRAreg OpARMBICshiftLLreg OpARMBICshiftRLreg OpARMBICshiftRAreg OpARMMVNshiftLLreg OpARMMVNshiftRLreg OpARMMVNshiftRAreg OpARMADCshiftLLreg OpARMADCshiftRLreg OpARMADCshiftRAreg OpARMSBCshiftLLreg OpARMSBCshiftRLreg OpARMSBCshiftRAreg OpARMRSCshiftLLreg OpARMRSCshiftRLreg OpARMRSCshiftRAreg OpARMADDSshiftLLreg OpARMADDSshiftRLreg OpARMADDSshiftRAreg OpARMSUBSshiftLLreg OpARMSUBSshiftRLreg OpARMSUBSshiftRAreg OpARMRSBSshiftLLreg OpARMRSBSshiftRLreg OpARMRSBSshiftRAreg OpARMCMP OpARMCMPconst OpARMCMN OpARMCMNconst OpARMTST OpARMTSTconst OpARMTEQ OpARMTEQconst OpARMCMPF OpARMCMPD OpARMCMPshiftLL OpARMCMPshiftRL OpARMCMPshiftRA OpARMCMNshiftLL OpARMCMNshiftRL OpARMCMNshiftRA OpARMTSTshiftLL OpARMTSTshiftRL OpARMTSTshiftRA OpARMTEQshiftLL OpARMTEQshiftRL OpARMTEQshiftRA OpARMCMPshiftLLreg OpARMCMPshiftRLreg OpARMCMPshiftRAreg OpARMCMNshiftLLreg OpARMCMNshiftRLreg OpARMCMNshiftRAreg OpARMTSTshiftLLreg OpARMTSTshiftRLreg OpARMTSTshiftRAreg OpARMTEQshiftLLreg OpARMTEQshiftRLreg OpARMTEQshiftRAreg OpARMCMPF0 OpARMCMPD0 OpARMMOVWconst OpARMMOVFconst OpARMMOVDconst OpARMMOVWaddr OpARMMOVBload OpARMMOVBUload OpARMMOVHload OpARMMOVHUload OpARMMOVWload OpARMMOVFload OpARMMOVDload OpARMMOVBstore OpARMMOVHstore OpARMMOVWstore OpARMMOVFstore OpARMMOVDstore OpARMMOVWloadidx OpARMMOVWloadshiftLL OpARMMOVWloadshiftRL OpARMMOVWloadshiftRA OpARMMOVBUloadidx OpARMMOVBloadidx OpARMMOVHUloadidx OpARMMOVHloadidx OpARMMOVWstoreidx OpARMMOVWstoreshiftLL OpARMMOVWstoreshiftRL OpARMMOVWstoreshiftRA OpARMMOVBstoreidx OpARMMOVHstoreidx OpARMMOVBreg OpARMMOVBUreg OpARMMOVHreg OpARMMOVHUreg OpARMMOVWreg OpARMMOVWnop OpARMMOVWF OpARMMOVWD OpARMMOVWUF OpARMMOVWUD OpARMMOVFW OpARMMOVDW OpARMMOVFWU OpARMMOVDWU OpARMMOVFD OpARMMOVDF OpARMCMOVWHSconst OpARMCMOVWLSconst OpARMSRAcond OpARMCALLstatic OpARMCALLtail OpARMCALLclosure OpARMCALLinter OpARMLoweredNilCheck OpARMEqual OpARMNotEqual OpARMLessThan OpARMLessEqual OpARMGreaterThan OpARMGreaterEqual OpARMLessThanU OpARMLessEqualU OpARMGreaterThanU OpARMGreaterEqualU OpARMDUFFZERO OpARMDUFFCOPY OpARMLoweredZero OpARMLoweredMove OpARMLoweredGetClosurePtr OpARMLoweredGetCallerSP OpARMLoweredGetCallerPC OpARMLoweredPanicBoundsA OpARMLoweredPanicBoundsB OpARMLoweredPanicBoundsC OpARMLoweredPanicExtendA OpARMLoweredPanicExtendB OpARMLoweredPanicExtendC OpARMFlagConstant OpARMInvertFlags OpARMLoweredWB OpARM64ADCSflags OpARM64ADCzerocarry OpARM64ADD OpARM64ADDconst OpARM64ADDSconstflags OpARM64ADDSflags OpARM64SUB OpARM64SUBconst OpARM64SBCSflags OpARM64SUBSflags OpARM64MUL OpARM64MULW OpARM64MNEG OpARM64MNEGW OpARM64MULH OpARM64UMULH OpARM64MULL OpARM64UMULL OpARM64DIV OpARM64UDIV OpARM64DIVW OpARM64UDIVW OpARM64MOD OpARM64UMOD OpARM64MODW OpARM64UMODW OpARM64FADDS OpARM64FADDD OpARM64FSUBS OpARM64FSUBD OpARM64FMULS OpARM64FMULD OpARM64FNMULS OpARM64FNMULD OpARM64FDIVS OpARM64FDIVD OpARM64AND OpARM64ANDconst OpARM64OR OpARM64ORconst OpARM64XOR OpARM64XORconst OpARM64BIC OpARM64EON OpARM64ORN OpARM64MVN OpARM64NEG OpARM64NEGSflags OpARM64NGCzerocarry OpARM64FABSD OpARM64FNEGS OpARM64FNEGD OpARM64FSQRTD OpARM64FSQRTS OpARM64FMIND OpARM64FMINS OpARM64FMAXD OpARM64FMAXS OpARM64REV OpARM64REVW OpARM64REV16 OpARM64REV16W OpARM64RBIT OpARM64RBITW OpARM64CLZ OpARM64CLZW OpARM64VCNT OpARM64VUADDLV OpARM64LoweredRound32F OpARM64LoweredRound64F OpARM64FMADDS OpARM64FMADDD OpARM64FNMADDS OpARM64FNMADDD OpARM64FMSUBS OpARM64FMSUBD OpARM64FNMSUBS OpARM64FNMSUBD OpARM64MADD OpARM64MADDW OpARM64MSUB OpARM64MSUBW OpARM64SLL OpARM64SLLconst OpARM64SRL OpARM64SRLconst OpARM64SRA OpARM64SRAconst OpARM64ROR OpARM64RORW OpARM64RORconst OpARM64RORWconst OpARM64EXTRconst OpARM64EXTRWconst OpARM64CMP OpARM64CMPconst OpARM64CMPW OpARM64CMPWconst OpARM64CMN OpARM64CMNconst OpARM64CMNW OpARM64CMNWconst OpARM64TST OpARM64TSTconst OpARM64TSTW OpARM64TSTWconst OpARM64FCMPS OpARM64FCMPD OpARM64FCMPS0 OpARM64FCMPD0 OpARM64MVNshiftLL OpARM64MVNshiftRL OpARM64MVNshiftRA OpARM64MVNshiftRO OpARM64NEGshiftLL OpARM64NEGshiftRL OpARM64NEGshiftRA OpARM64ADDshiftLL OpARM64ADDshiftRL OpARM64ADDshiftRA OpARM64SUBshiftLL OpARM64SUBshiftRL OpARM64SUBshiftRA OpARM64ANDshiftLL OpARM64ANDshiftRL OpARM64ANDshiftRA OpARM64ANDshiftRO OpARM64ORshiftLL OpARM64ORshiftRL OpARM64ORshiftRA OpARM64ORshiftRO OpARM64XORshiftLL OpARM64XORshiftRL OpARM64XORshiftRA OpARM64XORshiftRO OpARM64BICshiftLL OpARM64BICshiftRL OpARM64BICshiftRA OpARM64BICshiftRO OpARM64EONshiftLL OpARM64EONshiftRL OpARM64EONshiftRA OpARM64EONshiftRO OpARM64ORNshiftLL OpARM64ORNshiftRL OpARM64ORNshiftRA OpARM64ORNshiftRO OpARM64CMPshiftLL OpARM64CMPshiftRL OpARM64CMPshiftRA OpARM64CMNshiftLL OpARM64CMNshiftRL OpARM64CMNshiftRA OpARM64TSTshiftLL OpARM64TSTshiftRL OpARM64TSTshiftRA OpARM64TSTshiftRO OpARM64BFI OpARM64BFXIL OpARM64SBFIZ OpARM64SBFX OpARM64UBFIZ OpARM64UBFX OpARM64MOVDconst OpARM64FMOVSconst OpARM64FMOVDconst OpARM64MOVDaddr OpARM64MOVBload OpARM64MOVBUload OpARM64MOVHload OpARM64MOVHUload OpARM64MOVWload OpARM64MOVWUload OpARM64MOVDload OpARM64FMOVSload OpARM64FMOVDload OpARM64LDP OpARM64LDPW OpARM64LDPSW OpARM64FLDPD OpARM64FLDPS OpARM64MOVDloadidx OpARM64MOVWloadidx OpARM64MOVWUloadidx OpARM64MOVHloadidx OpARM64MOVHUloadidx OpARM64MOVBloadidx OpARM64MOVBUloadidx OpARM64FMOVSloadidx OpARM64FMOVDloadidx OpARM64MOVHloadidx2 OpARM64MOVHUloadidx2 OpARM64MOVWloadidx4 OpARM64MOVWUloadidx4 OpARM64MOVDloadidx8 OpARM64FMOVSloadidx4 OpARM64FMOVDloadidx8 OpARM64MOVBstore OpARM64MOVHstore OpARM64MOVWstore OpARM64MOVDstore OpARM64FMOVSstore OpARM64FMOVDstore OpARM64STP OpARM64STPW OpARM64FSTPD OpARM64FSTPS OpARM64MOVBstoreidx OpARM64MOVHstoreidx OpARM64MOVWstoreidx OpARM64MOVDstoreidx OpARM64FMOVSstoreidx OpARM64FMOVDstoreidx OpARM64MOVHstoreidx2 OpARM64MOVWstoreidx4 OpARM64MOVDstoreidx8 OpARM64FMOVSstoreidx4 OpARM64FMOVDstoreidx8 OpARM64FMOVDgpfp OpARM64FMOVDfpgp OpARM64FMOVSgpfp OpARM64FMOVSfpgp OpARM64MOVBreg OpARM64MOVBUreg OpARM64MOVHreg OpARM64MOVHUreg OpARM64MOVWreg OpARM64MOVWUreg OpARM64MOVDreg OpARM64MOVDnop OpARM64SCVTFWS OpARM64SCVTFWD OpARM64UCVTFWS OpARM64UCVTFWD OpARM64SCVTFS OpARM64SCVTFD OpARM64UCVTFS OpARM64UCVTFD OpARM64FCVTZSSW OpARM64FCVTZSDW OpARM64FCVTZUSW OpARM64FCVTZUDW OpARM64FCVTZSS OpARM64FCVTZSD OpARM64FCVTZUS OpARM64FCVTZUD OpARM64FCVTSD OpARM64FCVTDS OpARM64FRINTAD OpARM64FRINTMD OpARM64FRINTND OpARM64FRINTPD OpARM64FRINTZD OpARM64CSEL OpARM64CSEL0 OpARM64CSINC OpARM64CSINV OpARM64CSNEG OpARM64CSETM OpARM64CALLstatic OpARM64CALLtail OpARM64CALLclosure OpARM64CALLinter OpARM64LoweredNilCheck OpARM64Equal OpARM64NotEqual OpARM64LessThan OpARM64LessEqual OpARM64GreaterThan OpARM64GreaterEqual OpARM64LessThanU OpARM64LessEqualU OpARM64GreaterThanU OpARM64GreaterEqualU OpARM64LessThanF OpARM64LessEqualF OpARM64GreaterThanF OpARM64GreaterEqualF OpARM64NotLessThanF OpARM64NotLessEqualF OpARM64NotGreaterThanF OpARM64NotGreaterEqualF OpARM64LessThanNoov OpARM64GreaterEqualNoov OpARM64DUFFZERO OpARM64LoweredZero OpARM64DUFFCOPY OpARM64LoweredMove OpARM64LoweredGetClosurePtr OpARM64LoweredGetCallerSP OpARM64LoweredGetCallerPC OpARM64FlagConstant OpARM64InvertFlags OpARM64LDAR OpARM64LDARB OpARM64LDARW OpARM64STLRB OpARM64STLR OpARM64STLRW OpARM64LoweredAtomicExchange64 OpARM64LoweredAtomicExchange32 OpARM64LoweredAtomicExchange8 OpARM64LoweredAtomicExchange64Variant OpARM64LoweredAtomicExchange32Variant OpARM64LoweredAtomicExchange8Variant OpARM64LoweredAtomicAdd64 OpARM64LoweredAtomicAdd32 OpARM64LoweredAtomicAdd64Variant OpARM64LoweredAtomicAdd32Variant OpARM64LoweredAtomicCas64 OpARM64LoweredAtomicCas32 OpARM64LoweredAtomicCas64Variant OpARM64LoweredAtomicCas32Variant OpARM64LoweredAtomicAnd8 OpARM64LoweredAtomicOr8 OpARM64LoweredAtomicAnd64 OpARM64LoweredAtomicOr64 OpARM64LoweredAtomicAnd32 OpARM64LoweredAtomicOr32 OpARM64LoweredAtomicAnd8Variant OpARM64LoweredAtomicOr8Variant OpARM64LoweredAtomicAnd64Variant OpARM64LoweredAtomicOr64Variant OpARM64LoweredAtomicAnd32Variant OpARM64LoweredAtomicOr32Variant OpARM64LoweredWB OpARM64LoweredPanicBoundsA OpARM64LoweredPanicBoundsB OpARM64LoweredPanicBoundsC OpARM64PRFM OpARM64DMB OpARM64ZERO OpLOONG64NEGV OpLOONG64NEGF OpLOONG64NEGD OpLOONG64SQRTD OpLOONG64SQRTF OpLOONG64ABSD OpLOONG64CLZW OpLOONG64CLZV OpLOONG64CTZW OpLOONG64CTZV OpLOONG64REVB2H OpLOONG64REVB2W OpLOONG64REVBV OpLOONG64BITREV4B OpLOONG64BITREVW OpLOONG64BITREVV OpLOONG64VPCNT64 OpLOONG64VPCNT32 OpLOONG64VPCNT16 OpLOONG64ADDV OpLOONG64ADDVconst OpLOONG64SUBV OpLOONG64SUBVconst OpLOONG64MULV OpLOONG64MULHV OpLOONG64MULHVU OpLOONG64DIVV OpLOONG64DIVVU OpLOONG64REMV OpLOONG64REMVU OpLOONG64ADDF OpLOONG64ADDD OpLOONG64SUBF OpLOONG64SUBD OpLOONG64MULF OpLOONG64MULD OpLOONG64DIVF OpLOONG64DIVD OpLOONG64AND OpLOONG64ANDconst OpLOONG64OR OpLOONG64ORconst OpLOONG64XOR OpLOONG64XORconst OpLOONG64NOR OpLOONG64NORconst OpLOONG64FMADDF OpLOONG64FMADDD OpLOONG64FMSUBF OpLOONG64FMSUBD OpLOONG64FNMADDF OpLOONG64FNMADDD OpLOONG64FNMSUBF OpLOONG64FNMSUBD OpLOONG64FMINF OpLOONG64FMIND OpLOONG64FMAXF OpLOONG64FMAXD OpLOONG64MASKEQZ OpLOONG64MASKNEZ OpLOONG64FCOPYSGD OpLOONG64SLL OpLOONG64SLLV OpLOONG64SLLconst OpLOONG64SLLVconst OpLOONG64SRL OpLOONG64SRLV OpLOONG64SRLconst OpLOONG64SRLVconst OpLOONG64SRA OpLOONG64SRAV OpLOONG64SRAconst OpLOONG64SRAVconst OpLOONG64ROTR OpLOONG64ROTRV OpLOONG64ROTRconst OpLOONG64ROTRVconst OpLOONG64SGT OpLOONG64SGTconst OpLOONG64SGTU OpLOONG64SGTUconst OpLOONG64CMPEQF OpLOONG64CMPEQD OpLOONG64CMPGEF OpLOONG64CMPGED OpLOONG64CMPGTF OpLOONG64CMPGTD OpLOONG64BSTRPICKW OpLOONG64BSTRPICKV OpLOONG64MOVVconst OpLOONG64MOVFconst OpLOONG64MOVDconst OpLOONG64MOVVaddr OpLOONG64MOVBload OpLOONG64MOVBUload OpLOONG64MOVHload OpLOONG64MOVHUload OpLOONG64MOVWload OpLOONG64MOVWUload OpLOONG64MOVVload OpLOONG64MOVFload OpLOONG64MOVDload OpLOONG64MOVVloadidx OpLOONG64MOVWloadidx OpLOONG64MOVWUloadidx OpLOONG64MOVHloadidx OpLOONG64MOVHUloadidx OpLOONG64MOVBloadidx OpLOONG64MOVBUloadidx OpLOONG64MOVFloadidx OpLOONG64MOVDloadidx OpLOONG64MOVBstore OpLOONG64MOVHstore OpLOONG64MOVWstore OpLOONG64MOVVstore OpLOONG64MOVFstore OpLOONG64MOVDstore OpLOONG64MOVBstoreidx OpLOONG64MOVHstoreidx OpLOONG64MOVWstoreidx OpLOONG64MOVVstoreidx OpLOONG64MOVFstoreidx OpLOONG64MOVDstoreidx OpLOONG64MOVBstorezero OpLOONG64MOVHstorezero OpLOONG64MOVWstorezero OpLOONG64MOVVstorezero OpLOONG64MOVBstorezeroidx OpLOONG64MOVHstorezeroidx OpLOONG64MOVWstorezeroidx OpLOONG64MOVVstorezeroidx OpLOONG64MOVWfpgp OpLOONG64MOVWgpfp OpLOONG64MOVVfpgp OpLOONG64MOVVgpfp OpLOONG64MOVBreg OpLOONG64MOVBUreg OpLOONG64MOVHreg OpLOONG64MOVHUreg OpLOONG64MOVWreg OpLOONG64MOVWUreg OpLOONG64MOVVreg OpLOONG64MOVVnop OpLOONG64MOVWF OpLOONG64MOVWD OpLOONG64MOVVF OpLOONG64MOVVD OpLOONG64TRUNCFW OpLOONG64TRUNCDW OpLOONG64TRUNCFV OpLOONG64TRUNCDV OpLOONG64MOVFD OpLOONG64MOVDF OpLOONG64LoweredRound32F OpLOONG64LoweredRound64F OpLOONG64CALLstatic OpLOONG64CALLtail OpLOONG64CALLclosure OpLOONG64CALLinter OpLOONG64DUFFZERO OpLOONG64DUFFCOPY OpLOONG64LoweredZero OpLOONG64LoweredMove OpLOONG64LoweredAtomicLoad8 OpLOONG64LoweredAtomicLoad32 OpLOONG64LoweredAtomicLoad64 OpLOONG64LoweredAtomicStore8 OpLOONG64LoweredAtomicStore32 OpLOONG64LoweredAtomicStore64 OpLOONG64LoweredAtomicStore8Variant OpLOONG64LoweredAtomicStore32Variant OpLOONG64LoweredAtomicStore64Variant OpLOONG64LoweredAtomicExchange32 OpLOONG64LoweredAtomicExchange64 OpLOONG64LoweredAtomicExchange8Variant OpLOONG64LoweredAtomicAdd32 OpLOONG64LoweredAtomicAdd64 OpLOONG64LoweredAtomicCas32 OpLOONG64LoweredAtomicCas64 OpLOONG64LoweredAtomicCas64Variant OpLOONG64LoweredAtomicCas32Variant OpLOONG64LoweredAtomicAnd32 OpLOONG64LoweredAtomicOr32 OpLOONG64LoweredAtomicAnd32value OpLOONG64LoweredAtomicAnd64value OpLOONG64LoweredAtomicOr32value OpLOONG64LoweredAtomicOr64value OpLOONG64LoweredNilCheck OpLOONG64FPFlagTrue OpLOONG64FPFlagFalse OpLOONG64LoweredGetClosurePtr OpLOONG64LoweredGetCallerSP OpLOONG64LoweredGetCallerPC OpLOONG64LoweredWB OpLOONG64LoweredPubBarrier OpLOONG64LoweredPanicBoundsA OpLOONG64LoweredPanicBoundsB OpLOONG64LoweredPanicBoundsC OpMIPSADD OpMIPSADDconst OpMIPSSUB OpMIPSSUBconst OpMIPSMUL OpMIPSMULT OpMIPSMULTU OpMIPSDIV OpMIPSDIVU OpMIPSADDF OpMIPSADDD OpMIPSSUBF OpMIPSSUBD OpMIPSMULF OpMIPSMULD OpMIPSDIVF OpMIPSDIVD OpMIPSAND OpMIPSANDconst OpMIPSOR OpMIPSORconst OpMIPSXOR OpMIPSXORconst OpMIPSNOR OpMIPSNORconst OpMIPSNEG OpMIPSNEGF OpMIPSNEGD OpMIPSABSD OpMIPSSQRTD OpMIPSSQRTF OpMIPSSLL OpMIPSSLLconst OpMIPSSRL OpMIPSSRLconst OpMIPSSRA OpMIPSSRAconst OpMIPSCLZ OpMIPSSGT OpMIPSSGTconst OpMIPSSGTzero OpMIPSSGTU OpMIPSSGTUconst OpMIPSSGTUzero OpMIPSCMPEQF OpMIPSCMPEQD OpMIPSCMPGEF OpMIPSCMPGED OpMIPSCMPGTF OpMIPSCMPGTD OpMIPSMOVWconst OpMIPSMOVFconst OpMIPSMOVDconst OpMIPSMOVWaddr OpMIPSMOVBload OpMIPSMOVBUload OpMIPSMOVHload OpMIPSMOVHUload OpMIPSMOVWload OpMIPSMOVFload OpMIPSMOVDload OpMIPSMOVBstore OpMIPSMOVHstore OpMIPSMOVWstore OpMIPSMOVFstore OpMIPSMOVDstore OpMIPSMOVBstorezero OpMIPSMOVHstorezero OpMIPSMOVWstorezero OpMIPSMOVWfpgp OpMIPSMOVWgpfp OpMIPSMOVBreg OpMIPSMOVBUreg OpMIPSMOVHreg OpMIPSMOVHUreg OpMIPSMOVWreg OpMIPSMOVWnop OpMIPSCMOVZ OpMIPSCMOVZzero OpMIPSMOVWF OpMIPSMOVWD OpMIPSTRUNCFW OpMIPSTRUNCDW OpMIPSMOVFD OpMIPSMOVDF OpMIPSCALLstatic OpMIPSCALLtail OpMIPSCALLclosure OpMIPSCALLinter OpMIPSLoweredAtomicLoad8 OpMIPSLoweredAtomicLoad32 OpMIPSLoweredAtomicStore8 OpMIPSLoweredAtomicStore32 OpMIPSLoweredAtomicStorezero OpMIPSLoweredAtomicExchange OpMIPSLoweredAtomicAdd OpMIPSLoweredAtomicAddconst OpMIPSLoweredAtomicCas OpMIPSLoweredAtomicAnd OpMIPSLoweredAtomicOr OpMIPSLoweredZero OpMIPSLoweredMove OpMIPSLoweredNilCheck OpMIPSFPFlagTrue OpMIPSFPFlagFalse OpMIPSLoweredGetClosurePtr OpMIPSLoweredGetCallerSP OpMIPSLoweredGetCallerPC OpMIPSLoweredWB OpMIPSLoweredPanicBoundsA OpMIPSLoweredPanicBoundsB OpMIPSLoweredPanicBoundsC OpMIPSLoweredPanicExtendA OpMIPSLoweredPanicExtendB OpMIPSLoweredPanicExtendC OpMIPS64ADDV OpMIPS64ADDVconst OpMIPS64SUBV OpMIPS64SUBVconst OpMIPS64MULV OpMIPS64MULVU OpMIPS64DIVV OpMIPS64DIVVU OpMIPS64ADDF OpMIPS64ADDD OpMIPS64SUBF OpMIPS64SUBD OpMIPS64MULF OpMIPS64MULD OpMIPS64DIVF OpMIPS64DIVD OpMIPS64AND OpMIPS64ANDconst OpMIPS64OR OpMIPS64ORconst OpMIPS64XOR OpMIPS64XORconst OpMIPS64NOR OpMIPS64NORconst OpMIPS64NEGV OpMIPS64NEGF OpMIPS64NEGD OpMIPS64ABSD OpMIPS64SQRTD OpMIPS64SQRTF OpMIPS64SLLV OpMIPS64SLLVconst OpMIPS64SRLV OpMIPS64SRLVconst OpMIPS64SRAV OpMIPS64SRAVconst OpMIPS64SGT OpMIPS64SGTconst OpMIPS64SGTU OpMIPS64SGTUconst OpMIPS64CMPEQF OpMIPS64CMPEQD OpMIPS64CMPGEF OpMIPS64CMPGED OpMIPS64CMPGTF OpMIPS64CMPGTD OpMIPS64MOVVconst OpMIPS64MOVFconst OpMIPS64MOVDconst OpMIPS64MOVVaddr OpMIPS64MOVBload OpMIPS64MOVBUload OpMIPS64MOVHload OpMIPS64MOVHUload OpMIPS64MOVWload OpMIPS64MOVWUload OpMIPS64MOVVload OpMIPS64MOVFload OpMIPS64MOVDload OpMIPS64MOVBstore OpMIPS64MOVHstore OpMIPS64MOVWstore OpMIPS64MOVVstore OpMIPS64MOVFstore OpMIPS64MOVDstore OpMIPS64MOVBstorezero OpMIPS64MOVHstorezero OpMIPS64MOVWstorezero OpMIPS64MOVVstorezero OpMIPS64MOVWfpgp OpMIPS64MOVWgpfp OpMIPS64MOVVfpgp OpMIPS64MOVVgpfp OpMIPS64MOVBreg OpMIPS64MOVBUreg OpMIPS64MOVHreg OpMIPS64MOVHUreg OpMIPS64MOVWreg OpMIPS64MOVWUreg OpMIPS64MOVVreg OpMIPS64MOVVnop OpMIPS64MOVWF OpMIPS64MOVWD OpMIPS64MOVVF OpMIPS64MOVVD OpMIPS64TRUNCFW OpMIPS64TRUNCDW OpMIPS64TRUNCFV OpMIPS64TRUNCDV OpMIPS64MOVFD OpMIPS64MOVDF OpMIPS64CALLstatic OpMIPS64CALLtail OpMIPS64CALLclosure OpMIPS64CALLinter OpMIPS64DUFFZERO OpMIPS64DUFFCOPY OpMIPS64LoweredZero OpMIPS64LoweredMove OpMIPS64LoweredAtomicAnd32 OpMIPS64LoweredAtomicOr32 OpMIPS64LoweredAtomicLoad8 OpMIPS64LoweredAtomicLoad32 OpMIPS64LoweredAtomicLoad64 OpMIPS64LoweredAtomicStore8 OpMIPS64LoweredAtomicStore32 OpMIPS64LoweredAtomicStore64 OpMIPS64LoweredAtomicStorezero32 OpMIPS64LoweredAtomicStorezero64 OpMIPS64LoweredAtomicExchange32 OpMIPS64LoweredAtomicExchange64 OpMIPS64LoweredAtomicAdd32 OpMIPS64LoweredAtomicAdd64 OpMIPS64LoweredAtomicAddconst32 OpMIPS64LoweredAtomicAddconst64 OpMIPS64LoweredAtomicCas32 OpMIPS64LoweredAtomicCas64 OpMIPS64LoweredNilCheck OpMIPS64FPFlagTrue OpMIPS64FPFlagFalse OpMIPS64LoweredGetClosurePtr OpMIPS64LoweredGetCallerSP OpMIPS64LoweredGetCallerPC OpMIPS64LoweredWB OpMIPS64LoweredPanicBoundsA OpMIPS64LoweredPanicBoundsB OpMIPS64LoweredPanicBoundsC OpPPC64ADD OpPPC64ADDCC OpPPC64ADDconst OpPPC64ADDCCconst OpPPC64FADD OpPPC64FADDS OpPPC64SUB OpPPC64SUBCC OpPPC64SUBFCconst OpPPC64FSUB OpPPC64FSUBS OpPPC64XSMINJDP OpPPC64XSMAXJDP OpPPC64MULLD OpPPC64MULLW OpPPC64MULLDconst OpPPC64MULLWconst OpPPC64MADDLD OpPPC64MULHD OpPPC64MULHW OpPPC64MULHDU OpPPC64MULHDUCC OpPPC64MULHWU OpPPC64FMUL OpPPC64FMULS OpPPC64FMADD OpPPC64FMADDS OpPPC64FMSUB OpPPC64FMSUBS OpPPC64SRAD OpPPC64SRAW OpPPC64SRD OpPPC64SRW OpPPC64SLD OpPPC64SLW OpPPC64ROTL OpPPC64ROTLW OpPPC64CLRLSLWI OpPPC64CLRLSLDI OpPPC64ADDC OpPPC64SUBC OpPPC64ADDCconst OpPPC64SUBCconst OpPPC64ADDE OpPPC64ADDZE OpPPC64SUBE OpPPC64ADDZEzero OpPPC64SUBZEzero OpPPC64SRADconst OpPPC64SRAWconst OpPPC64SRDconst OpPPC64SRWconst OpPPC64SLDconst OpPPC64SLWconst OpPPC64ROTLconst OpPPC64ROTLWconst OpPPC64EXTSWSLconst OpPPC64RLWINM OpPPC64RLWNM OpPPC64RLWMI OpPPC64RLDICL OpPPC64RLDICLCC OpPPC64RLDICR OpPPC64CNTLZD OpPPC64CNTLZDCC OpPPC64CNTLZW OpPPC64CNTTZD OpPPC64CNTTZW OpPPC64POPCNTD OpPPC64POPCNTW OpPPC64POPCNTB OpPPC64FDIV OpPPC64FDIVS OpPPC64DIVD OpPPC64DIVW OpPPC64DIVDU OpPPC64DIVWU OpPPC64MODUD OpPPC64MODSD OpPPC64MODUW OpPPC64MODSW OpPPC64FCTIDZ OpPPC64FCTIWZ OpPPC64FCFID OpPPC64FCFIDS OpPPC64FRSP OpPPC64MFVSRD OpPPC64MTVSRD OpPPC64AND OpPPC64ANDN OpPPC64ANDNCC OpPPC64ANDCC OpPPC64OR OpPPC64ORN OpPPC64ORCC OpPPC64NOR OpPPC64NORCC OpPPC64XOR OpPPC64XORCC OpPPC64EQV OpPPC64NEG OpPPC64NEGCC OpPPC64BRD OpPPC64BRW OpPPC64BRH OpPPC64FNEG OpPPC64FSQRT OpPPC64FSQRTS OpPPC64FFLOOR OpPPC64FCEIL OpPPC64FTRUNC OpPPC64FROUND OpPPC64FABS OpPPC64FNABS OpPPC64FCPSGN OpPPC64ORconst OpPPC64XORconst OpPPC64ANDCCconst OpPPC64ANDconst OpPPC64MOVBreg OpPPC64MOVBZreg OpPPC64MOVHreg OpPPC64MOVHZreg OpPPC64MOVWreg OpPPC64MOVWZreg OpPPC64MOVBZload OpPPC64MOVHload OpPPC64MOVHZload OpPPC64MOVWload OpPPC64MOVWZload OpPPC64MOVDload OpPPC64MOVDBRload OpPPC64MOVWBRload OpPPC64MOVHBRload OpPPC64MOVBZloadidx OpPPC64MOVHloadidx OpPPC64MOVHZloadidx OpPPC64MOVWloadidx OpPPC64MOVWZloadidx OpPPC64MOVDloadidx OpPPC64MOVHBRloadidx OpPPC64MOVWBRloadidx OpPPC64MOVDBRloadidx OpPPC64FMOVDloadidx OpPPC64FMOVSloadidx OpPPC64DCBT OpPPC64MOVDBRstore OpPPC64MOVWBRstore OpPPC64MOVHBRstore OpPPC64FMOVDload OpPPC64FMOVSload OpPPC64MOVBstore OpPPC64MOVHstore OpPPC64MOVWstore OpPPC64MOVDstore OpPPC64FMOVDstore OpPPC64FMOVSstore OpPPC64MOVBstoreidx OpPPC64MOVHstoreidx OpPPC64MOVWstoreidx OpPPC64MOVDstoreidx OpPPC64FMOVDstoreidx OpPPC64FMOVSstoreidx OpPPC64MOVHBRstoreidx OpPPC64MOVWBRstoreidx OpPPC64MOVDBRstoreidx OpPPC64MOVBstorezero OpPPC64MOVHstorezero OpPPC64MOVWstorezero OpPPC64MOVDstorezero OpPPC64MOVDaddr OpPPC64MOVDconst OpPPC64FMOVDconst OpPPC64FMOVSconst OpPPC64FCMPU OpPPC64CMP OpPPC64CMPU OpPPC64CMPW OpPPC64CMPWU OpPPC64CMPconst OpPPC64CMPUconst OpPPC64CMPWconst OpPPC64CMPWUconst OpPPC64ISEL OpPPC64ISELZ OpPPC64SETBC OpPPC64SETBCR OpPPC64Equal OpPPC64NotEqual OpPPC64LessThan OpPPC64FLessThan OpPPC64LessEqual OpPPC64FLessEqual OpPPC64GreaterThan OpPPC64FGreaterThan OpPPC64GreaterEqual OpPPC64FGreaterEqual OpPPC64LoweredGetClosurePtr OpPPC64LoweredGetCallerSP OpPPC64LoweredGetCallerPC OpPPC64LoweredNilCheck OpPPC64LoweredRound32F OpPPC64LoweredRound64F OpPPC64CALLstatic OpPPC64CALLtail OpPPC64CALLclosure OpPPC64CALLinter OpPPC64LoweredZero OpPPC64LoweredZeroShort OpPPC64LoweredQuadZeroShort OpPPC64LoweredQuadZero OpPPC64LoweredMove OpPPC64LoweredMoveShort OpPPC64LoweredQuadMove OpPPC64LoweredQuadMoveShort OpPPC64LoweredAtomicStore8 OpPPC64LoweredAtomicStore32 OpPPC64LoweredAtomicStore64 OpPPC64LoweredAtomicLoad8 OpPPC64LoweredAtomicLoad32 OpPPC64LoweredAtomicLoad64 OpPPC64LoweredAtomicLoadPtr OpPPC64LoweredAtomicAdd32 OpPPC64LoweredAtomicAdd64 OpPPC64LoweredAtomicExchange8 OpPPC64LoweredAtomicExchange32 OpPPC64LoweredAtomicExchange64 OpPPC64LoweredAtomicCas64 OpPPC64LoweredAtomicCas32 OpPPC64LoweredAtomicAnd8 OpPPC64LoweredAtomicAnd32 OpPPC64LoweredAtomicOr8 OpPPC64LoweredAtomicOr32 OpPPC64LoweredWB OpPPC64LoweredPubBarrier OpPPC64LoweredPanicBoundsA OpPPC64LoweredPanicBoundsB OpPPC64LoweredPanicBoundsC OpPPC64InvertFlags OpPPC64FlagEQ OpPPC64FlagLT OpPPC64FlagGT OpRISCV64ADD OpRISCV64ADDI OpRISCV64ADDIW OpRISCV64NEG OpRISCV64NEGW OpRISCV64SUB OpRISCV64SUBW OpRISCV64MUL OpRISCV64MULW OpRISCV64MULH OpRISCV64MULHU OpRISCV64LoweredMuluhilo OpRISCV64LoweredMuluover OpRISCV64DIV OpRISCV64DIVU OpRISCV64DIVW OpRISCV64DIVUW OpRISCV64REM OpRISCV64REMU OpRISCV64REMW OpRISCV64REMUW OpRISCV64MOVaddr OpRISCV64MOVDconst OpRISCV64MOVBload OpRISCV64MOVHload OpRISCV64MOVWload OpRISCV64MOVDload OpRISCV64MOVBUload OpRISCV64MOVHUload OpRISCV64MOVWUload OpRISCV64MOVBstore OpRISCV64MOVHstore OpRISCV64MOVWstore OpRISCV64MOVDstore OpRISCV64MOVBstorezero OpRISCV64MOVHstorezero OpRISCV64MOVWstorezero OpRISCV64MOVDstorezero OpRISCV64MOVBreg OpRISCV64MOVHreg OpRISCV64MOVWreg OpRISCV64MOVDreg OpRISCV64MOVBUreg OpRISCV64MOVHUreg OpRISCV64MOVWUreg OpRISCV64MOVDnop OpRISCV64SLL OpRISCV64SLLW OpRISCV64SRA OpRISCV64SRAW OpRISCV64SRL OpRISCV64SRLW OpRISCV64SLLI OpRISCV64SLLIW OpRISCV64SRAI OpRISCV64SRAIW OpRISCV64SRLI OpRISCV64SRLIW OpRISCV64SH1ADD OpRISCV64SH2ADD OpRISCV64SH3ADD OpRISCV64AND OpRISCV64ANDN OpRISCV64ANDI OpRISCV64CLZ OpRISCV64CLZW OpRISCV64CTZ OpRISCV64CTZW OpRISCV64NOT OpRISCV64OR OpRISCV64ORN OpRISCV64ORI OpRISCV64REV8 OpRISCV64ROL OpRISCV64ROLW OpRISCV64ROR OpRISCV64RORI OpRISCV64RORIW OpRISCV64RORW OpRISCV64XNOR OpRISCV64XOR OpRISCV64XORI OpRISCV64MIN OpRISCV64MAX OpRISCV64MINU OpRISCV64MAXU OpRISCV64SEQZ OpRISCV64SNEZ OpRISCV64SLT OpRISCV64SLTI OpRISCV64SLTU OpRISCV64SLTIU OpRISCV64LoweredRound32F OpRISCV64LoweredRound64F OpRISCV64CALLstatic OpRISCV64CALLtail OpRISCV64CALLclosure OpRISCV64CALLinter OpRISCV64DUFFZERO OpRISCV64DUFFCOPY OpRISCV64LoweredZero OpRISCV64LoweredMove OpRISCV64LoweredAtomicLoad8 OpRISCV64LoweredAtomicLoad32 OpRISCV64LoweredAtomicLoad64 OpRISCV64LoweredAtomicStore8 OpRISCV64LoweredAtomicStore32 OpRISCV64LoweredAtomicStore64 OpRISCV64LoweredAtomicExchange32 OpRISCV64LoweredAtomicExchange64 OpRISCV64LoweredAtomicAdd32 OpRISCV64LoweredAtomicAdd64 OpRISCV64LoweredAtomicCas32 OpRISCV64LoweredAtomicCas64 OpRISCV64LoweredAtomicAnd32 OpRISCV64LoweredAtomicOr32 OpRISCV64LoweredNilCheck OpRISCV64LoweredGetClosurePtr OpRISCV64LoweredGetCallerSP OpRISCV64LoweredGetCallerPC OpRISCV64LoweredWB OpRISCV64LoweredPubBarrier OpRISCV64LoweredPanicBoundsA OpRISCV64LoweredPanicBoundsB OpRISCV64LoweredPanicBoundsC OpRISCV64FADDS OpRISCV64FSUBS OpRISCV64FMULS OpRISCV64FDIVS OpRISCV64FMADDS OpRISCV64FMSUBS OpRISCV64FNMADDS OpRISCV64FNMSUBS OpRISCV64FSQRTS OpRISCV64FNEGS OpRISCV64FMVSX OpRISCV64FCVTSW OpRISCV64FCVTSL OpRISCV64FCVTWS OpRISCV64FCVTLS OpRISCV64FMOVWload OpRISCV64FMOVWstore OpRISCV64FEQS OpRISCV64FNES OpRISCV64FLTS OpRISCV64FLES OpRISCV64LoweredFMAXS OpRISCV64LoweredFMINS OpRISCV64FADDD OpRISCV64FSUBD OpRISCV64FMULD OpRISCV64FDIVD OpRISCV64FMADDD OpRISCV64FMSUBD OpRISCV64FNMADDD OpRISCV64FNMSUBD OpRISCV64FSQRTD OpRISCV64FNEGD OpRISCV64FABSD OpRISCV64FSGNJD OpRISCV64FMVDX OpRISCV64FCVTDW OpRISCV64FCVTDL OpRISCV64FCVTWD OpRISCV64FCVTLD OpRISCV64FCVTDS OpRISCV64FCVTSD OpRISCV64FMOVDload OpRISCV64FMOVDstore OpRISCV64FEQD OpRISCV64FNED OpRISCV64FLTD OpRISCV64FLED OpRISCV64LoweredFMIND OpRISCV64LoweredFMAXD OpS390XFADDS OpS390XFADD OpS390XFSUBS OpS390XFSUB OpS390XFMULS OpS390XFMUL OpS390XFDIVS OpS390XFDIV OpS390XFNEGS OpS390XFNEG OpS390XFMADDS OpS390XFMADD OpS390XFMSUBS OpS390XFMSUB OpS390XLPDFR OpS390XLNDFR OpS390XCPSDR OpS390XFIDBR OpS390XFMOVSload OpS390XFMOVDload OpS390XFMOVSconst OpS390XFMOVDconst OpS390XFMOVSloadidx OpS390XFMOVDloadidx OpS390XFMOVSstore OpS390XFMOVDstore OpS390XFMOVSstoreidx OpS390XFMOVDstoreidx OpS390XADD OpS390XADDW OpS390XADDconst OpS390XADDWconst OpS390XADDload OpS390XADDWload OpS390XSUB OpS390XSUBW OpS390XSUBconst OpS390XSUBWconst OpS390XSUBload OpS390XSUBWload OpS390XMULLD OpS390XMULLW OpS390XMULLDconst OpS390XMULLWconst OpS390XMULLDload OpS390XMULLWload OpS390XMULHD OpS390XMULHDU OpS390XDIVD OpS390XDIVW OpS390XDIVDU OpS390XDIVWU OpS390XMODD OpS390XMODW OpS390XMODDU OpS390XMODWU OpS390XAND OpS390XANDW OpS390XANDconst OpS390XANDWconst OpS390XANDload OpS390XANDWload OpS390XOR OpS390XORW OpS390XORconst OpS390XORWconst OpS390XORload OpS390XORWload OpS390XXOR OpS390XXORW OpS390XXORconst OpS390XXORWconst OpS390XXORload OpS390XXORWload OpS390XADDC OpS390XADDCconst OpS390XADDE OpS390XSUBC OpS390XSUBE OpS390XCMP OpS390XCMPW OpS390XCMPU OpS390XCMPWU OpS390XCMPconst OpS390XCMPWconst OpS390XCMPUconst OpS390XCMPWUconst OpS390XFCMPS OpS390XFCMP OpS390XLTDBR OpS390XLTEBR OpS390XSLD OpS390XSLW OpS390XSLDconst OpS390XSLWconst OpS390XSRD OpS390XSRW OpS390XSRDconst OpS390XSRWconst OpS390XSRAD OpS390XSRAW OpS390XSRADconst OpS390XSRAWconst OpS390XRLLG OpS390XRLL OpS390XRLLconst OpS390XRXSBG OpS390XRISBGZ OpS390XNEG OpS390XNEGW OpS390XNOT OpS390XNOTW OpS390XFSQRT OpS390XFSQRTS OpS390XLOCGR OpS390XMOVBreg OpS390XMOVBZreg OpS390XMOVHreg OpS390XMOVHZreg OpS390XMOVWreg OpS390XMOVWZreg OpS390XMOVDconst OpS390XLDGR OpS390XLGDR OpS390XCFDBRA OpS390XCGDBRA OpS390XCFEBRA OpS390XCGEBRA OpS390XCEFBRA OpS390XCDFBRA OpS390XCEGBRA OpS390XCDGBRA OpS390XCLFEBR OpS390XCLFDBR OpS390XCLGEBR OpS390XCLGDBR OpS390XCELFBR OpS390XCDLFBR OpS390XCELGBR OpS390XCDLGBR OpS390XLEDBR OpS390XLDEBR OpS390XMOVDaddr OpS390XMOVDaddridx OpS390XMOVBZload OpS390XMOVBload OpS390XMOVHZload OpS390XMOVHload OpS390XMOVWZload OpS390XMOVWload OpS390XMOVDload OpS390XMOVWBR OpS390XMOVDBR OpS390XMOVHBRload OpS390XMOVWBRload OpS390XMOVDBRload OpS390XMOVBstore OpS390XMOVHstore OpS390XMOVWstore OpS390XMOVDstore OpS390XMOVHBRstore OpS390XMOVWBRstore OpS390XMOVDBRstore OpS390XMVC OpS390XMOVBZloadidx OpS390XMOVBloadidx OpS390XMOVHZloadidx OpS390XMOVHloadidx OpS390XMOVWZloadidx OpS390XMOVWloadidx OpS390XMOVDloadidx OpS390XMOVHBRloadidx OpS390XMOVWBRloadidx OpS390XMOVDBRloadidx OpS390XMOVBstoreidx OpS390XMOVHstoreidx OpS390XMOVWstoreidx OpS390XMOVDstoreidx OpS390XMOVHBRstoreidx OpS390XMOVWBRstoreidx OpS390XMOVDBRstoreidx OpS390XMOVBstoreconst OpS390XMOVHstoreconst OpS390XMOVWstoreconst OpS390XMOVDstoreconst OpS390XCLEAR OpS390XCALLstatic OpS390XCALLtail OpS390XCALLclosure OpS390XCALLinter OpS390XInvertFlags OpS390XLoweredGetG OpS390XLoweredGetClosurePtr OpS390XLoweredGetCallerSP OpS390XLoweredGetCallerPC OpS390XLoweredNilCheck OpS390XLoweredRound32F OpS390XLoweredRound64F OpS390XLoweredWB OpS390XLoweredPanicBoundsA OpS390XLoweredPanicBoundsB OpS390XLoweredPanicBoundsC OpS390XFlagEQ OpS390XFlagLT OpS390XFlagGT OpS390XFlagOV OpS390XSYNC OpS390XMOVBZatomicload OpS390XMOVWZatomicload OpS390XMOVDatomicload OpS390XMOVBatomicstore OpS390XMOVWatomicstore OpS390XMOVDatomicstore OpS390XLAA OpS390XLAAG OpS390XAddTupleFirst32 OpS390XAddTupleFirst64 OpS390XLAN OpS390XLANfloor OpS390XLAO OpS390XLAOfloor OpS390XLoweredAtomicCas32 OpS390XLoweredAtomicCas64 OpS390XLoweredAtomicExchange32 OpS390XLoweredAtomicExchange64 OpS390XFLOGR OpS390XPOPCNT OpS390XMLGR OpS390XSumBytes2 OpS390XSumBytes4 OpS390XSumBytes8 OpS390XSTMG2 OpS390XSTMG3 OpS390XSTMG4 OpS390XSTM2 OpS390XSTM3 OpS390XSTM4 OpS390XLoweredMove OpS390XLoweredZero OpWasmLoweredStaticCall OpWasmLoweredTailCall OpWasmLoweredClosureCall OpWasmLoweredInterCall OpWasmLoweredAddr OpWasmLoweredMove OpWasmLoweredZero OpWasmLoweredGetClosurePtr OpWasmLoweredGetCallerPC OpWasmLoweredGetCallerSP OpWasmLoweredNilCheck OpWasmLoweredWB OpWasmLoweredConvert OpWasmSelect OpWasmI64Load8U OpWasmI64Load8S OpWasmI64Load16U OpWasmI64Load16S OpWasmI64Load32U OpWasmI64Load32S OpWasmI64Load OpWasmI64Store8 OpWasmI64Store16 OpWasmI64Store32 OpWasmI64Store OpWasmF32Load OpWasmF64Load OpWasmF32Store OpWasmF64Store OpWasmI64Const OpWasmF32Const OpWasmF64Const OpWasmI64Eqz OpWasmI64Eq OpWasmI64Ne OpWasmI64LtS OpWasmI64LtU OpWasmI64GtS OpWasmI64GtU OpWasmI64LeS OpWasmI64LeU OpWasmI64GeS OpWasmI64GeU OpWasmF32Eq OpWasmF32Ne OpWasmF32Lt OpWasmF32Gt OpWasmF32Le OpWasmF32Ge OpWasmF64Eq OpWasmF64Ne OpWasmF64Lt OpWasmF64Gt OpWasmF64Le OpWasmF64Ge OpWasmI64Add OpWasmI64AddConst OpWasmI64Sub OpWasmI64Mul OpWasmI64DivS OpWasmI64DivU OpWasmI64RemS OpWasmI64RemU OpWasmI64And OpWasmI64Or OpWasmI64Xor OpWasmI64Shl OpWasmI64ShrS OpWasmI64ShrU OpWasmF32Neg OpWasmF32Add OpWasmF32Sub OpWasmF32Mul OpWasmF32Div OpWasmF64Neg OpWasmF64Add OpWasmF64Sub OpWasmF64Mul OpWasmF64Div OpWasmI64TruncSatF64S OpWasmI64TruncSatF64U OpWasmI64TruncSatF32S OpWasmI64TruncSatF32U OpWasmF32ConvertI64S OpWasmF32ConvertI64U OpWasmF64ConvertI64S OpWasmF64ConvertI64U OpWasmF32DemoteF64 OpWasmF64PromoteF32 OpWasmI64Extend8S OpWasmI64Extend16S OpWasmI64Extend32S OpWasmF32Sqrt OpWasmF32Trunc OpWasmF32Ceil OpWasmF32Floor OpWasmF32Nearest OpWasmF32Abs OpWasmF32Copysign OpWasmF64Sqrt OpWasmF64Trunc OpWasmF64Ceil OpWasmF64Floor OpWasmF64Nearest OpWasmF64Abs OpWasmF64Copysign OpWasmI64Ctz OpWasmI64Clz OpWasmI32Rotl OpWasmI64Rotl OpWasmI64Popcnt OpAdd8 OpAdd16 OpAdd32 OpAdd64 OpAddPtr OpAdd32F OpAdd64F OpSub8 OpSub16 OpSub32 OpSub64 OpSubPtr OpSub32F OpSub64F OpMul8 OpMul16 OpMul32 OpMul64 OpMul32F OpMul64F OpDiv32F OpDiv64F OpHmul32 OpHmul32u OpHmul64 OpHmul64u OpMul32uhilo OpMul64uhilo OpMul32uover OpMul64uover OpAvg32u OpAvg64u OpDiv8 OpDiv8u OpDiv16 OpDiv16u OpDiv32 OpDiv32u OpDiv64 OpDiv64u OpDiv128u OpMod8 OpMod8u OpMod16 OpMod16u OpMod32 OpMod32u OpMod64 OpMod64u OpAnd8 OpAnd16 OpAnd32 OpAnd64 OpOr8 OpOr16 OpOr32 OpOr64 OpXor8 OpXor16 OpXor32 OpXor64 OpLsh8x8 OpLsh8x16 OpLsh8x32 OpLsh8x64 OpLsh16x8 OpLsh16x16 OpLsh16x32 OpLsh16x64 OpLsh32x8 OpLsh32x16 OpLsh32x32 OpLsh32x64 OpLsh64x8 OpLsh64x16 OpLsh64x32 OpLsh64x64 OpRsh8x8 OpRsh8x16 OpRsh8x32 OpRsh8x64 OpRsh16x8 OpRsh16x16 OpRsh16x32 OpRsh16x64 OpRsh32x8 OpRsh32x16 OpRsh32x32 OpRsh32x64 OpRsh64x8 OpRsh64x16 OpRsh64x32 OpRsh64x64 OpRsh8Ux8 OpRsh8Ux16 OpRsh8Ux32 OpRsh8Ux64 OpRsh16Ux8 OpRsh16Ux16 OpRsh16Ux32 OpRsh16Ux64 OpRsh32Ux8 OpRsh32Ux16 OpRsh32Ux32 OpRsh32Ux64 OpRsh64Ux8 OpRsh64Ux16 OpRsh64Ux32 OpRsh64Ux64 OpEq8 OpEq16 OpEq32 OpEq64 OpEqPtr OpEqInter OpEqSlice OpEq32F OpEq64F OpNeq8 OpNeq16 OpNeq32 OpNeq64 OpNeqPtr OpNeqInter OpNeqSlice OpNeq32F OpNeq64F OpLess8 OpLess8U OpLess16 OpLess16U OpLess32 OpLess32U OpLess64 OpLess64U OpLess32F OpLess64F OpLeq8 OpLeq8U OpLeq16 OpLeq16U OpLeq32 OpLeq32U OpLeq64 OpLeq64U OpLeq32F OpLeq64F OpCondSelect OpAndB OpOrB OpEqB OpNeqB OpNot OpNeg8 OpNeg16 OpNeg32 OpNeg64 OpNeg32F OpNeg64F OpCom8 OpCom16 OpCom32 OpCom64 OpCtz8 OpCtz16 OpCtz32 OpCtz64 OpCtz64On32 OpCtz8NonZero OpCtz16NonZero OpCtz32NonZero OpCtz64NonZero OpBitLen8 OpBitLen16 OpBitLen32 OpBitLen64 OpBswap16 OpBswap32 OpBswap64 OpBitRev8 OpBitRev16 OpBitRev32 OpBitRev64 OpPopCount8 OpPopCount16 OpPopCount32 OpPopCount64 OpRotateLeft64 OpRotateLeft32 OpRotateLeft16 OpRotateLeft8 OpSqrt OpSqrt32 OpFloor OpCeil OpTrunc OpRound OpRoundToEven OpAbs OpCopysign OpMin64 OpMax64 OpMin64u OpMax64u OpMin64F OpMin32F OpMax64F OpMax32F OpFMA OpPhi OpCopy OpConvert OpConstBool OpConstString OpConstNil OpConst8 OpConst16 OpConst32 OpConst64 OpConst32F OpConst64F OpConstInterface OpConstSlice OpInitMem OpArg OpArgIntReg OpArgFloatReg OpAddr OpLocalAddr OpSP OpSB OpSPanchored OpLoad OpDereference OpStore OpMove OpZero OpStoreWB OpMoveWB OpZeroWB OpWBend OpWB OpHasCPUFeature OpPanicBounds OpPanicExtend OpClosureCall OpStaticCall OpInterCall OpTailCall OpClosureLECall OpStaticLECall OpInterLECall OpTailLECall OpSignExt8to16 OpSignExt8to32 OpSignExt8to64 OpSignExt16to32 OpSignExt16to64 OpSignExt32to64 OpZeroExt8to16 OpZeroExt8to32 OpZeroExt8to64 OpZeroExt16to32 OpZeroExt16to64 OpZeroExt32to64 OpTrunc16to8 OpTrunc32to8 OpTrunc32to16 OpTrunc64to8 OpTrunc64to16 OpTrunc64to32 OpCvt32to32F OpCvt32to64F OpCvt64to32F OpCvt64to64F OpCvt32Fto32 OpCvt32Fto64 OpCvt64Fto32 OpCvt64Fto64 OpCvt32Fto64F OpCvt64Fto32F OpCvtBoolToUint8 OpRound32F OpRound64F OpIsNonNil OpIsInBounds OpIsSliceInBounds OpNilCheck OpGetG OpGetClosurePtr OpGetCallerPC OpGetCallerSP OpPtrIndex OpOffPtr OpSliceMake OpSlicePtr OpSliceLen OpSliceCap OpSlicePtrUnchecked OpComplexMake OpComplexReal OpComplexImag OpStringMake OpStringPtr OpStringLen OpIMake OpITab OpIData OpStructMake OpStructSelect OpArrayMake0 OpArrayMake1 OpArraySelect OpStoreReg OpLoadReg OpFwdRef OpUnknown OpVarDef OpVarLive OpKeepAlive OpInlMark OpInt64Make OpInt64Hi OpInt64Lo OpAdd32carry OpAdd32withcarry OpSub32carry OpSub32withcarry OpAdd64carry OpSub64borrow OpSignmask OpZeromask OpSlicemask OpSpectreIndex OpSpectreSliceIndex OpCvt32Uto32F OpCvt32Uto64F OpCvt32Fto32U OpCvt64Fto32U OpCvt64Uto32F OpCvt64Uto64F OpCvt32Fto64U OpCvt64Fto64U OpSelect0 OpSelect1 OpMakeTuple OpSelectN OpSelectNAddr OpMakeResult OpAtomicLoad8 OpAtomicLoad32 OpAtomicLoad64 OpAtomicLoadPtr OpAtomicLoadAcq32 OpAtomicLoadAcq64 OpAtomicStore8 OpAtomicStore32 OpAtomicStore64 OpAtomicStorePtrNoWB OpAtomicStoreRel32 OpAtomicStoreRel64 OpAtomicExchange8 OpAtomicExchange32 OpAtomicExchange64 OpAtomicAdd32 OpAtomicAdd64 OpAtomicCompareAndSwap32 OpAtomicCompareAndSwap64 OpAtomicCompareAndSwapRel32 OpAtomicAnd8 OpAtomicOr8 OpAtomicAnd32 OpAtomicOr32 OpAtomicAnd64value OpAtomicAnd32value OpAtomicAnd8value OpAtomicOr64value OpAtomicOr32value OpAtomicOr8value OpAtomicStore8Variant OpAtomicStore32Variant OpAtomicStore64Variant OpAtomicAdd32Variant OpAtomicAdd64Variant OpAtomicExchange8Variant OpAtomicExchange32Variant OpAtomicExchange64Variant OpAtomicCompareAndSwap32Variant OpAtomicCompareAndSwap64Variant OpAtomicAnd64valueVariant OpAtomicOr64valueVariant OpAtomicAnd32valueVariant OpAtomicOr32valueVariant OpAtomicAnd8valueVariant OpAtomicOr8valueVariant OpPubBarrier OpClobber OpClobberReg OpPrefetchCache OpPrefetchCacheStreamed ) var opcodeTable = [...]opInfo{ {name: "OpInvalid"}, { name: "ADDSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSS", argLen: 2, resultInArg0: true, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSD", argLen: 2, resultInArg0: true, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSS", argLen: 2, resultInArg0: true, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSD", argLen: 2, resultInArg0: true, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: x86.AMOVSS, reg: regInfo{ outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: x86.AMOVSD, reg: regInfo{ outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSSstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSSstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 239}, // AX CX DX BX BP SI DI {0, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLcarry", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADCL", argLen: 3, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AADCL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADCLconst", auxType: auxInt32, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AADCL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLcarry", argLen: 2, resultInArg0: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SBBL", argLen: 3, resultInArg0: true, clobberFlags: true, asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SBBLconst", auxType: auxInt32, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AIMUL3L, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "HMULL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULLU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MULLQU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 4}, // DX {1, 1}, // AX }, }, }, { name: "AVGLU", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "DIVL", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVW", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "MODL", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODW", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "ANDL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CMPL", argLen: 2, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPW", argLen: 2, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPB", argLen: 2, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPLconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPWconst", auxType: auxInt16, argLen: 1, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPBconst", auxType: auxInt8, argLen: 1, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPWload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPBload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPLconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPWconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPBconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "UCOMISS", argLen: 2, asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "UCOMISD", argLen: 2, asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "TESTL", argLen: 2, commutative: true, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTW", argLen: 2, commutative: true, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTB", argLen: 2, commutative: true, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTLconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTWconst", auxType: auxInt16, argLen: 1, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTBconst", auxType: auxInt8, argLen: 1, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "SHLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "NEGL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "NOTL", argLen: 1, resultInArg0: true, asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSFL", argLen: 1, clobberFlags: true, asm: x86.ABSFL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSFW", argLen: 1, clobberFlags: true, asm: x86.ABSFW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredCtz32", argLen: 1, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredCtz64", argLen: 2, resultNotInArgs: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSRL", argLen: 1, clobberFlags: true, asm: x86.ABSRL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSRW", argLen: 1, clobberFlags: true, asm: x86.ABSRW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSWAPL", argLen: 1, resultInArg0: true, asm: x86.ABSWAPL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SQRTSD", argLen: 1, asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SQRTSS", argLen: 1, asm: x86.ASQRTSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SBBLcarrymask", argLen: 1, asm: x86.ASBBL, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETEQ", argLen: 1, asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETNE", argLen: 1, asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETL", argLen: 1, asm: x86.ASETLT, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETLE", argLen: 1, asm: x86.ASETLE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETG", argLen: 1, asm: x86.ASETGT, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGE", argLen: 1, asm: x86.ASETGE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETB", argLen: 1, asm: x86.ASETCS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETBE", argLen: 1, asm: x86.ASETLS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETA", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETAE", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETO", argLen: 1, asm: x86.ASETOS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETEQF", argLen: 1, clobberFlags: true, asm: x86.ASETEQ, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 238}, // CX DX BX BP SI DI }, }, }, { name: "SETNEF", argLen: 1, clobberFlags: true, asm: x86.ASETNE, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 238}, // CX DX BX BP SI DI }, }, }, { name: "SETORD", argLen: 1, asm: x86.ASETPC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETNAN", argLen: 1, asm: x86.ASETPS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGF", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGEF", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLSX", argLen: 1, asm: x86.AMOVBLSX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLZX", argLen: 1, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLSX", argLen: 1, asm: x86.AMOVWLSX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLZX", argLen: 1, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: x86.AMOVL, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTTSD2SL", argLen: 1, asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTTSS2SL", argLen: 1, asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTSL2SS", argLen: 1, asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSL2SD", argLen: 1, asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSD2SS", argLen: 1, asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSS2SD", argLen: 1, asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "PXOR", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "LEAL", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBLSX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWLSX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "SUBLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "SUBLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWloadidx2", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreidx2", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconstidx2", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconstidx4", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "REPSTOSL", argLen: 4, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 2}, // CX {2, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4}, // DX {0, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI }, clobbers: 194, // CX SI DI }, }, { name: "REPMOVSL", argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI {2, 2}, // CX }, clobbers: 194, // CX SI DI }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 65280, // X0 X1 X2 X3 X4 X5 X6 X7 outputs: []outputInfo{ {0, 128}, // DI }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // DX {1, 8}, // BX }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // CX {1, 4}, // DX }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 2}, // CX }, }, }, { name: "LoweredPanicExtendA", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // SI {1, 4}, // DX {2, 8}, // BX }, }, }, { name: "LoweredPanicExtendB", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // SI {1, 2}, // CX {2, 4}, // DX }, }, }, { name: "LoweredPanicExtendC", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // SI {1, 1}, // AX {2, 2}, // CX }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_ULT", argLen: 0, reg: regInfo{}, }, { name: "MOVSSconst1", auxType: auxFloat32, argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVSDconst1", auxType: auxFloat64, argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVSSconst2", argLen: 1, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDconst2", argLen: 1, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSS", argLen: 2, resultInArg0: true, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSD", argLen: 2, resultInArg0: true, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSS", argLen: 2, resultInArg0: true, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSD", argLen: 2, resultInArg0: true, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: x86.AMOVSS, reg: regInfo{ outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: x86.AMOVSD, reg: regInfo{ outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSSstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSSstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSDstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSDstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "ADDSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDQ", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULQconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AIMUL3Q, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AIMUL3L, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULLU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 4, // DX outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "MULQU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 4, // DX outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "HMULQ", argLen: 2, clobberFlags: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULL", argLen: 2, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULQU", argLen: 2, clobberFlags: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULLU", argLen: 2, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "AVGQU", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "DIVQ", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVL", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVW", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVQU", argLen: 2, clobberFlags: true, asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "NEGLflags", argLen: 1, resultInArg0: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQcarry", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADCQ", argLen: 3, commutative: true, resultInArg0: true, asm: x86.AADCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADCQconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: x86.AADCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQborrow", argLen: 2, resultInArg0: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SBBQ", argLen: 3, resultInArg0: true, asm: x86.ASBBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQconstborrow", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SBBQconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: x86.ASBBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULQU2", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 4}, // DX {1, 1}, // AX }, }, }, { name: "DIVQU2", argLen: 3, clobberFlags: true, asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // DX {1, 1}, // AX {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "ANDQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQ", argLen: 2, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPL", argLen: 2, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPW", argLen: 2, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPB", argLen: 2, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPQconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPLconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPWconst", auxType: auxInt16, argLen: 1, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPBconst", auxType: auxInt8, argLen: 1, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQloadidx8", auxType: auxSymOff, argLen: 4, symEffect: SymRead, asm: x86.ACMPQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLloadidx4", auxType: auxSymOff, argLen: 4, symEffect: SymRead, asm: x86.ACMPL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWloadidx2", auxType: auxSymOff, argLen: 4, symEffect: SymRead, asm: x86.ACMPW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQconstloadidx8", auxType: auxSymValAndOff, argLen: 3, symEffect: SymRead, asm: x86.ACMPQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLconstloadidx4", auxType: auxSymValAndOff, argLen: 3, symEffect: SymRead, asm: x86.ACMPL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWconstloadidx2", auxType: auxSymValAndOff, argLen: 3, symEffect: SymRead, asm: x86.ACMPW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "UCOMISS", argLen: 2, asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "UCOMISD", argLen: 2, asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "BTL", argLen: 2, asm: x86.ABTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTQ", argLen: 2, asm: x86.ABTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTCL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTSL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTLconst", auxType: auxInt8, argLen: 1, asm: x86.ABTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTQconst", auxType: auxInt8, argLen: 1, asm: x86.ABTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "BTRQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "BTCQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "TESTQ", argLen: 2, commutative: true, asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTL", argLen: 2, commutative: true, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTW", argLen: 2, commutative: true, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTB", argLen: 2, commutative: true, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTQconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTLconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTWconst", auxType: auxInt16, argLen: 1, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTBconst", auxType: auxInt8, argLen: 1, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRWconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARWconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRDQ", argLen: 3, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {2, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLDQ", argLen: 3, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {2, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLWconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "NEGQ", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "NEGL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "NOTQ", argLen: 1, resultInArg0: true, asm: x86.ANOTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "NOTL", argLen: 1, resultInArg0: true, asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSFQ", argLen: 1, asm: x86.ABSFQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSFL", argLen: 1, clobberFlags: true, asm: x86.ABSFL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSRQ", argLen: 1, asm: x86.ABSRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSRL", argLen: 1, clobberFlags: true, asm: x86.ABSRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQEQ", argLen: 3, resultInArg0: true, asm: x86.ACMOVQEQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQNE", argLen: 3, resultInArg0: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQLT", argLen: 3, resultInArg0: true, asm: x86.ACMOVQLT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGT", argLen: 3, resultInArg0: true, asm: x86.ACMOVQGT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQLE", argLen: 3, resultInArg0: true, asm: x86.ACMOVQLE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGE", argLen: 3, resultInArg0: true, asm: x86.ACMOVQGE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQLS", argLen: 3, resultInArg0: true, asm: x86.ACMOVQLS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQHI", argLen: 3, resultInArg0: true, asm: x86.ACMOVQHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQCC", argLen: 3, resultInArg0: true, asm: x86.ACMOVQCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQCS", argLen: 3, resultInArg0: true, asm: x86.ACMOVQCS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLEQ", argLen: 3, resultInArg0: true, asm: x86.ACMOVLEQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLNE", argLen: 3, resultInArg0: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLLT", argLen: 3, resultInArg0: true, asm: x86.ACMOVLLT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGT", argLen: 3, resultInArg0: true, asm: x86.ACMOVLGT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLLE", argLen: 3, resultInArg0: true, asm: x86.ACMOVLLE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGE", argLen: 3, resultInArg0: true, asm: x86.ACMOVLGE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLLS", argLen: 3, resultInArg0: true, asm: x86.ACMOVLLS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLHI", argLen: 3, resultInArg0: true, asm: x86.ACMOVLHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLCC", argLen: 3, resultInArg0: true, asm: x86.ACMOVLCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLCS", argLen: 3, resultInArg0: true, asm: x86.ACMOVLCS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWEQ", argLen: 3, resultInArg0: true, asm: x86.ACMOVWEQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWNE", argLen: 3, resultInArg0: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWLT", argLen: 3, resultInArg0: true, asm: x86.ACMOVWLT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGT", argLen: 3, resultInArg0: true, asm: x86.ACMOVWGT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWLE", argLen: 3, resultInArg0: true, asm: x86.ACMOVWLE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGE", argLen: 3, resultInArg0: true, asm: x86.ACMOVWGE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWLS", argLen: 3, resultInArg0: true, asm: x86.ACMOVWLS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWHI", argLen: 3, resultInArg0: true, asm: x86.ACMOVWHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWCC", argLen: 3, resultInArg0: true, asm: x86.ACMOVWCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWCS", argLen: 3, resultInArg0: true, asm: x86.ACMOVWCS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQEQF", argLen: 3, resultInArg0: true, needIntTemp: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQNEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGTF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLEQF", argLen: 3, resultInArg0: true, needIntTemp: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLNEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGTF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWEQF", argLen: 3, resultInArg0: true, needIntTemp: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWNEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGTF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSWAPQ", argLen: 1, resultInArg0: true, asm: x86.ABSWAPQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSWAPL", argLen: 1, resultInArg0: true, asm: x86.ABSWAPL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "POPCNTQ", argLen: 1, clobberFlags: true, asm: x86.APOPCNTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "POPCNTL", argLen: 1, clobberFlags: true, asm: x86.APOPCNTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SQRTSD", argLen: 1, asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SQRTSS", argLen: 1, asm: x86.ASQRTSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ROUNDSD", auxType: auxInt8, argLen: 1, asm: x86.AROUNDSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "VFMADD231SS", argLen: 3, resultInArg0: true, asm: x86.AVFMADD231SS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "VFMADD231SD", argLen: 3, resultInArg0: true, asm: x86.AVFMADD231SD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MINSD", argLen: 2, resultInArg0: true, asm: x86.AMINSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MINSS", argLen: 2, resultInArg0: true, asm: x86.AMINSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SBBQcarrymask", argLen: 1, asm: x86.ASBBQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SBBLcarrymask", argLen: 1, asm: x86.ASBBL, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETEQ", argLen: 1, asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETNE", argLen: 1, asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETL", argLen: 1, asm: x86.ASETLT, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETLE", argLen: 1, asm: x86.ASETLE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETG", argLen: 1, asm: x86.ASETGT, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETGE", argLen: 1, asm: x86.ASETGE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETB", argLen: 1, asm: x86.ASETCS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETBE", argLen: 1, asm: x86.ASETLS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETA", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETAE", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETO", argLen: 1, asm: x86.ASETOS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETEQstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETEQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETNEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETNE, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETLstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETLT, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETLEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETLE, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETGstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETGT, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETGEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETGE, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETCS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETBEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETLS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETAstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETHI, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETAEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETCC, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETEQstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETEQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETNEstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETNE, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETLstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETLT, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETLEstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETLE, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETGstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETGT, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETGEstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETGE, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETBstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETCS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETBEstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETLS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETAstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETHI, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETAEstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETCC, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETEQF", argLen: 1, clobberFlags: true, needIntTemp: true, asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETNEF", argLen: 1, clobberFlags: true, needIntTemp: true, asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETORD", argLen: 1, asm: x86.ASETPC, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETNAN", argLen: 1, asm: x86.ASETPS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETGF", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETGEF", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBQSX", argLen: 1, asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBQZX", argLen: 1, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWQSX", argLen: 1, asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWQZX", argLen: 1, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLQSX", argLen: 1, asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLQZX", argLen: 1, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: x86.AMOVL, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: x86.AMOVQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSD2SL", argLen: 1, asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSD2SQ", argLen: 1, asm: x86.ACVTTSD2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSS2SL", argLen: 1, asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSS2SQ", argLen: 1, asm: x86.ACVTTSS2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTSL2SS", argLen: 1, asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSL2SD", argLen: 1, asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSQ2SS", argLen: 1, asm: x86.ACVTSQ2SS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSQ2SD", argLen: 1, asm: x86.ACVTSQ2SD, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSD2SS", argLen: 1, asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSS2SD", argLen: 1, asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVQi2f", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVQf2i", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLi2f", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVLf2i", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "PXOR", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "POR", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APOR, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "LEAQ", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: x86.ALEAQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: x86.ALEAL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: x86.ALEAW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, asm: x86.ALEAQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, asm: x86.ALEAL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, asm: x86.ALEAW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAQ, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAL, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAQ, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAW, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAW, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBQSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWQSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLQSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVOload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVOstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVBloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBLZX, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVWLZX, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWloadidx2", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVWLZX, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreidx2", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVOstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreconstidx2", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreconstidx4", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreconstidx8", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI }, clobbers: 128, // DI }, }, { name: "REPSTOSQ", argLen: 4, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 2}, // CX {2, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4}, // DX {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI }, clobbers: 65728, // SI DI X0 }, }, { name: "REPMOVSQ", argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI {2, 2}, // CX }, clobbers: 194, // CX SI DI }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 outputs: []outputInfo{ {0, 2048}, // R11 }, }, }, { name: "LoweredHasCPUFeature", auxType: auxSym, argLen: 0, rematerializeable: true, symEffect: SymNone, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // DX {1, 8}, // BX }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // CX {1, 4}, // DX }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 2}, // CX }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_ULT", argLen: 0, reg: regInfo{}, }, { name: "MOVBatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XCHGB", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXCHGB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XCHGL", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXCHGL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XCHGQ", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXCHGQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XADDLlock", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXADDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XADDQlock", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "AddTupleFirst32", argLen: 2, reg: regInfo{}, }, { name: "AddTupleFirst64", argLen: 2, reg: regInfo{}, }, { name: "CMPXCHGLlock", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.ACMPXCHGL, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // AX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPXCHGQlock", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.ACMPXCHGQ, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // AX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDBlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AANDB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORBlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AORB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "LoweredAtomicAnd64", auxType: auxSymOff, argLen: 3, resultNotInArgs: true, clobberFlags: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, symEffect: SymRdWr, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "LoweredAtomicAnd32", auxType: auxSymOff, argLen: 3, resultNotInArgs: true, clobberFlags: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, symEffect: SymRdWr, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "LoweredAtomicOr64", auxType: auxSymOff, argLen: 3, resultNotInArgs: true, clobberFlags: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, symEffect: SymRdWr, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "LoweredAtomicOr32", auxType: auxSymOff, argLen: 3, resultNotInArgs: true, clobberFlags: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, symEffect: SymRdWr, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "PrefetchT0", argLen: 2, hasSideEffects: true, asm: x86.APREFETCHT0, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "PrefetchNTA", argLen: 2, hasSideEffects: true, asm: x86.APREFETCHNTA, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDNQ", argLen: 2, clobberFlags: true, asm: x86.AANDNQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDNL", argLen: 2, clobberFlags: true, asm: x86.AANDNL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSIQ", argLen: 1, clobberFlags: true, asm: x86.ABLSIQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSIL", argLen: 1, clobberFlags: true, asm: x86.ABLSIL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSMSKQ", argLen: 1, clobberFlags: true, asm: x86.ABLSMSKQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSMSKL", argLen: 1, clobberFlags: true, asm: x86.ABLSMSKL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSRQ", argLen: 1, asm: x86.ABLSRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSRL", argLen: 1, asm: x86.ABLSRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TZCNTQ", argLen: 1, clobberFlags: true, asm: x86.ATZCNTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TZCNTL", argLen: 1, clobberFlags: true, asm: x86.ATZCNTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LZCNTQ", argLen: 1, clobberFlags: true, asm: x86.ALZCNTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LZCNTL", argLen: 1, clobberFlags: true, asm: x86.ALZCNTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVBEW, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBEL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBELstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVBEL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEQload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBEQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEQstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVBEQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBEL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBELloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVBEL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBELloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVBEL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEQloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBEQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEQloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVBEQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEWstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVBEW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEWstoreidx2", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVBEL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEQstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVBEQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEQstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SARXQ", argLen: 2, asm: x86.ASARXQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXL", argLen: 2, asm: x86.ASARXL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQ", argLen: 2, asm: x86.ASHLXQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXL", argLen: 2, asm: x86.ASHLXL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQ", argLen: 2, asm: x86.ASHRXQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXL", argLen: 2, asm: x86.ASHRXL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLloadidx4", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXQloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXQloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLloadidx4", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLloadidx4", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "PUNPCKLBW", argLen: 2, resultInArg0: true, asm: x86.APUNPCKLBW, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "PSHUFLW", auxType: auxInt8, argLen: 1, asm: x86.APSHUFLW, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "PSHUFBbroadcast", argLen: 1, resultInArg0: true, asm: x86.APSHUFB, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "VPBROADCASTB", argLen: 1, asm: x86.AVPBROADCASTB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "PSIGNB", argLen: 2, resultInArg0: true, asm: x86.APSIGNB, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "PCMPEQB", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APCMPEQB, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "PMOVMSKB", argLen: 1, asm: x86.APMOVMSKB, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUB", argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSB", argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBconst", auxType: auxInt32, argLen: 1, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: arm.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "HMUL", argLen: 2, commutative: true, asm: arm.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "HMULU", argLen: 2, commutative: true, asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CALLudiv", argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 1}, // R0 }, clobbers: 20492, // R2 R3 R12 R14 outputs: []outputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "ADDS", argLen: 2, commutative: true, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSconst", auxType: auxInt32, argLen: 1, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADC", argLen: 3, commutative: true, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCconst", auxType: auxInt32, argLen: 2, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBS", argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSconst", auxType: auxInt32, argLen: 1, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSconst", auxType: auxInt32, argLen: 1, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBC", argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCconst", auxType: auxInt32, argLen: 2, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCconst", auxType: auxInt32, argLen: 2, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULLU", argLen: 2, commutative: true, asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULA", argLen: 3, asm: arm.AMULA, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULS", argLen: 3, asm: arm.AMULS, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: arm.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: arm.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SUBF", argLen: 2, asm: arm.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SUBD", argLen: 2, asm: arm.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: arm.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: arm.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "NMULF", argLen: 2, commutative: true, asm: arm.ANMULF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "NMULD", argLen: 2, commutative: true, asm: arm.ANMULD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "DIVF", argLen: 2, asm: arm.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "DIVD", argLen: 2, asm: arm.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULAF", argLen: 3, resultInArg0: true, asm: arm.AMULAF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULAD", argLen: 3, resultInArg0: true, asm: arm.AMULAD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULSF", argLen: 3, resultInArg0: true, asm: arm.AMULSF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULSD", argLen: 3, resultInArg0: true, asm: arm.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMULAD", argLen: 3, resultInArg0: true, asm: arm.AFMULAD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDconst", auxType: auxInt32, argLen: 1, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORconst", auxType: auxInt32, argLen: 1, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORconst", auxType: auxInt32, argLen: 1, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BIC", argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICconst", auxType: auxInt32, argLen: 1, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BFX", auxType: auxInt32, argLen: 1, asm: arm.ABFX, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BFXU", auxType: auxInt32, argLen: 1, asm: arm.ABFXU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVN", argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "NEGF", argLen: 1, asm: arm.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "NEGD", argLen: 1, asm: arm.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SQRTD", argLen: 1, asm: arm.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SQRTF", argLen: 1, asm: arm.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ABSD", argLen: 1, asm: arm.AABSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CLZ", argLen: 1, asm: arm.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "REV", argLen: 1, asm: arm.AREV, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "REV16", argLen: 1, asm: arm.AREV16, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RBIT", argLen: 1, asm: arm.ARBIT, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SLL", argLen: 2, asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SLLconst", auxType: auxInt32, argLen: 1, asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRL", argLen: 2, asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRLconst", auxType: auxInt32, argLen: 1, asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRA", argLen: 2, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRAconst", auxType: auxInt32, argLen: 1, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRR", argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRRconst", auxType: auxInt32, argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRR", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftLL", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRL", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRA", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftLLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRAreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftLLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRAreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftLLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRAreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftLLreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRLreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRAreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftLLreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRLreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRAreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftLLreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRLreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRAreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftLLreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRLreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRAreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftLLreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRLreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRAreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftLLreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRLreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRAreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftLLreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRLreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRAreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftLLreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRLreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRAreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftLLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRAreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftLLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRAreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftLLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRAreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMP", argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPconst", auxType: auxInt32, argLen: 1, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMN", argLen: 2, commutative: true, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNconst", auxType: auxInt32, argLen: 1, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TST", argLen: 2, commutative: true, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTconst", auxType: auxInt32, argLen: 1, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQ", argLen: 2, commutative: true, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQconst", auxType: auxInt32, argLen: 1, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPF", argLen: 2, asm: arm.ACMPF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPD", argLen: 2, asm: arm.ACMPD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPshiftLLreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMPshiftRLreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMPshiftRAreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMNshiftLLreg", argLen: 3, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMNshiftRLreg", argLen: 3, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMNshiftRAreg", argLen: 3, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TSTshiftLLreg", argLen: 3, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TSTshiftRLreg", argLen: 3, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TSTshiftRAreg", argLen: 3, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TEQshiftLLreg", argLen: 3, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TEQshiftRLreg", argLen: 3, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TEQshiftRAreg", argLen: 3, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMPF0", argLen: 1, asm: arm.ACMPF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPD0", argLen: 1, asm: arm.ACMPD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: arm.AMOVW, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4294975488}, // SP SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWloadshiftLL", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWloadshiftRL", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWloadshiftRA", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBUloadidx", argLen: 3, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBloadidx", argLen: 3, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHUloadidx", argLen: 3, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstoreshiftLL", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstoreshiftRL", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstoreshiftRA", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVBreg", argLen: 1, asm: arm.AMOVBS, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBUreg", argLen: 1, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHreg", argLen: 1, asm: arm.AMOVHS, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHUreg", argLen: 1, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWreg", argLen: 1, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWF", argLen: 1, asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWD", argLen: 1, asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWUF", argLen: 1, asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWUD", argLen: 1, asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVFW", argLen: 1, asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVDW", argLen: 1, asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFWU", argLen: 1, asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVDWU", argLen: 1, asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFD", argLen: 1, asm: arm.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDF", argLen: 1, asm: arm.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMOVWHSconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMOVWLSconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRAcond", argLen: 3, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 128}, // R7 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 }, clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 1}, // R0 }, clobbers: 20482, // R1 R12 R14 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 }, clobbers: 20487, // R0 R1 R2 R12 R14 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2, // R1 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 6, // R1 R2 }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 128}, // R7 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "LoweredPanicExtendA", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 4}, // R2 {2, 8}, // R3 }, }, }, { name: "LoweredPanicExtendB", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 2}, // R1 {2, 4}, // R2 }, }, }, { name: "LoweredPanicExtendC", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 1}, // R0 {2, 2}, // R1 }, }, }, { name: "FlagConstant", auxType: auxFlagConstant, argLen: 0, reg: regInfo{}, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 outputs: []outputInfo{ {0, 256}, // R8 }, }, }, { name: "ADCSflags", argLen: 3, commutative: true, asm: arm64.AADCS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADCzerocarry", argLen: 1, asm: arm64.AADC, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDconst", auxType: auxInt64, argLen: 1, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1476395007}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDSconstflags", auxType: auxInt64, argLen: 1, asm: arm64.AADDS, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {1, 0}, {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDSflags", argLen: 2, commutative: true, asm: arm64.AADDS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUB", argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBconst", auxType: auxInt64, argLen: 1, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SBCSflags", argLen: 3, asm: arm64.ASBCS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBSflags", argLen: 2, asm: arm64.ASUBS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: arm64.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MULW", argLen: 2, commutative: true, asm: arm64.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MNEG", argLen: 2, commutative: true, asm: arm64.AMNEG, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MNEGW", argLen: 2, commutative: true, asm: arm64.AMNEGW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MULH", argLen: 2, commutative: true, asm: arm64.ASMULH, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMULH", argLen: 2, commutative: true, asm: arm64.AUMULH, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MULL", argLen: 2, commutative: true, asm: arm64.ASMULL, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMULL", argLen: 2, commutative: true, asm: arm64.AUMULL, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "DIV", argLen: 2, asm: arm64.ASDIV, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UDIV", argLen: 2, asm: arm64.AUDIV, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "DIVW", argLen: 2, asm: arm64.ASDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UDIVW", argLen: 2, asm: arm64.AUDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOD", argLen: 2, asm: arm64.AREM, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMOD", argLen: 2, asm: arm64.AUREM, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MODW", argLen: 2, asm: arm64.AREMW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMODW", argLen: 2, asm: arm64.AUREMW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: arm64.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FADDD", argLen: 2, commutative: true, asm: arm64.AFADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBS", argLen: 2, asm: arm64.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBD", argLen: 2, asm: arm64.AFSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: arm64.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULD", argLen: 2, commutative: true, asm: arm64.AFMULD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMULS", argLen: 2, commutative: true, asm: arm64.AFNMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMULD", argLen: 2, commutative: true, asm: arm64.AFNMULD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVS", argLen: 2, asm: arm64.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVD", argLen: 2, asm: arm64.AFDIVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BIC", argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EON", argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORN", argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVN", argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEG", argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGSflags", argLen: 1, asm: arm64.ANEGS, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {1, 0}, {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NGCzerocarry", argLen: 1, asm: arm64.ANGC, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FABSD", argLen: 1, asm: arm64.AFABSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGS", argLen: 1, asm: arm64.AFNEGS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGD", argLen: 1, asm: arm64.AFNEGD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTD", argLen: 1, asm: arm64.AFSQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTS", argLen: 1, asm: arm64.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMIND", argLen: 2, asm: arm64.AFMIND, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMINS", argLen: 2, asm: arm64.AFMINS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMAXD", argLen: 2, asm: arm64.AFMAXD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMAXS", argLen: 2, asm: arm64.AFMAXS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "REV", argLen: 1, asm: arm64.AREV, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "REVW", argLen: 1, asm: arm64.AREVW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "REV16", argLen: 1, asm: arm64.AREV16, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "REV16W", argLen: 1, asm: arm64.AREV16W, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RBIT", argLen: 1, asm: arm64.ARBIT, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RBITW", argLen: 1, asm: arm64.ARBITW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CLZ", argLen: 1, asm: arm64.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CLZW", argLen: 1, asm: arm64.ACLZW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "VCNT", argLen: 1, asm: arm64.AVCNT, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "VUADDLV", argLen: 1, asm: arm64.AVUADDLV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDS", argLen: 3, asm: arm64.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDD", argLen: 3, asm: arm64.AFMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDS", argLen: 3, asm: arm64.AFNMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDD", argLen: 3, asm: arm64.AFNMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBS", argLen: 3, asm: arm64.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBD", argLen: 3, asm: arm64.AFMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBS", argLen: 3, asm: arm64.AFNMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBD", argLen: 3, asm: arm64.AFNMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MADD", argLen: 3, asm: arm64.AMADD, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MADDW", argLen: 3, asm: arm64.AMADDW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MSUB", argLen: 3, asm: arm64.AMSUB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MSUBW", argLen: 3, asm: arm64.AMSUBW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SLL", argLen: 2, asm: arm64.ALSL, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SLLconst", auxType: auxInt64, argLen: 1, asm: arm64.ALSL, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRL", argLen: 2, asm: arm64.ALSR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRLconst", auxType: auxInt64, argLen: 1, asm: arm64.ALSR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRA", argLen: 2, asm: arm64.AASR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRAconst", auxType: auxInt64, argLen: 1, asm: arm64.AASR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ROR", argLen: 2, asm: arm64.AROR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RORW", argLen: 2, asm: arm64.ARORW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RORconst", auxType: auxInt64, argLen: 1, asm: arm64.AROR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RORWconst", auxType: auxInt64, argLen: 1, asm: arm64.ARORW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EXTRconst", auxType: auxInt64, argLen: 2, asm: arm64.AEXTR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EXTRWconst", auxType: auxInt64, argLen: 2, asm: arm64.AEXTRW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CMP", argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPconst", auxType: auxInt64, argLen: 1, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPW", argLen: 2, asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMN", argLen: 2, commutative: true, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNconst", auxType: auxInt64, argLen: 1, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNW", argLen: 2, commutative: true, asm: arm64.ACMNW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNWconst", auxType: auxInt32, argLen: 1, asm: arm64.ACMNW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TST", argLen: 2, commutative: true, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTconst", auxType: auxInt64, argLen: 1, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTW", argLen: 2, commutative: true, asm: arm64.ATSTW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTWconst", auxType: auxInt32, argLen: 1, asm: arm64.ATSTW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "FCMPS", argLen: 2, asm: arm64.AFCMPS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCMPD", argLen: 2, asm: arm64.AFCMPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCMPS0", argLen: 1, asm: arm64.AFCMPS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCMPD0", argLen: 1, asm: arm64.AFCMPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MVNshiftLL", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVNshiftRL", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVNshiftRA", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVNshiftRO", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGshiftLL", auxType: auxInt64, argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGshiftRL", auxType: auxInt64, argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGshiftRA", auxType: auxInt64, argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CMPshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "BFI", auxType: auxARM64BitField, argLen: 2, resultInArg0: true, asm: arm64.ABFI, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BFXIL", auxType: auxARM64BitField, argLen: 2, resultInArg0: true, asm: arm64.ABFXIL, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SBFIZ", auxType: auxARM64BitField, argLen: 1, asm: arm64.ASBFIZ, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SBFX", auxType: auxARM64BitField, argLen: 1, asm: arm64.ASBFX, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UBFIZ", auxType: auxARM64BitField, argLen: 1, asm: arm64.AUBFIZ, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UBFX", auxType: auxARM64BitField, argLen: 1, asm: arm64.AUBFX, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: arm64.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm64.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm64.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037928517632}, // SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LDP", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.ALDP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "LDPW", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.ALDPW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "LDPSW", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.ALDPSW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "FLDPD", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AFLDPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FLDPS", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AFLDPS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDloadidx", argLen: 3, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUloadidx", argLen: 3, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUloadidx", argLen: 3, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBloadidx", argLen: 3, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBUloadidx", argLen: 3, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSloadidx", argLen: 3, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDloadidx", argLen: 3, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVHloadidx2", argLen: 3, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUloadidx2", argLen: 3, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWloadidx4", argLen: 3, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUloadidx4", argLen: 3, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDloadidx8", argLen: 3, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSloadidx4", argLen: 3, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDloadidx8", argLen: 3, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "STP", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.ASTP, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "STPW", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.ASTPW, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FSTPD", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AFSTPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSTPS", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AFSTPS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstoreidx", argLen: 4, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVSstoreidx", argLen: 4, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstoreidx", argLen: 4, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVHstoreidx2", argLen: 4, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstoreidx4", argLen: 4, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstoreidx8", argLen: 4, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVSstoreidx4", argLen: 4, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstoreidx8", argLen: 4, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDgpfp", argLen: 1, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDfpgp", argLen: 1, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSgpfp", argLen: 1, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVSfpgp", argLen: 1, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBreg", argLen: 1, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBUreg", argLen: 1, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHreg", argLen: 1, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUreg", argLen: 1, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWreg", argLen: 1, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUreg", argLen: 1, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDreg", argLen: 1, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SCVTFWS", argLen: 1, asm: arm64.ASCVTFWS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SCVTFWD", argLen: 1, asm: arm64.ASCVTFWD, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFWS", argLen: 1, asm: arm64.AUCVTFWS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFWD", argLen: 1, asm: arm64.AUCVTFWD, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SCVTFS", argLen: 1, asm: arm64.ASCVTFS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SCVTFD", argLen: 1, asm: arm64.ASCVTFD, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFS", argLen: 1, asm: arm64.AUCVTFS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFD", argLen: 1, asm: arm64.AUCVTFD, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTZSSW", argLen: 1, asm: arm64.AFCVTZSSW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZSDW", argLen: 1, asm: arm64.AFCVTZSDW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUSW", argLen: 1, asm: arm64.AFCVTZUSW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUDW", argLen: 1, asm: arm64.AFCVTZUDW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZSS", argLen: 1, asm: arm64.AFCVTZSS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZSD", argLen: 1, asm: arm64.AFCVTZSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUS", argLen: 1, asm: arm64.AFCVTZUS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUD", argLen: 1, asm: arm64.AFCVTZUD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTSD", argLen: 1, asm: arm64.AFCVTSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTDS", argLen: 1, asm: arm64.AFCVTDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTAD", argLen: 1, asm: arm64.AFRINTAD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTMD", argLen: 1, asm: arm64.AFRINTMD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTND", argLen: 1, asm: arm64.AFRINTND, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTPD", argLen: 1, asm: arm64.AFRINTPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTZD", argLen: 1, asm: arm64.AFRINTZD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CSEL", auxType: auxCCop, argLen: 3, asm: arm64.ACSEL, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSEL0", auxType: auxCCop, argLen: 2, asm: arm64.ACSEL, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSINC", auxType: auxCCop, argLen: 3, asm: arm64.ACSINC, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSINV", auxType: auxCCop, argLen: 3, asm: arm64.ACSINV, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSNEG", auxType: auxCCop, argLen: 3, asm: arm64.ACSNEG, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSETM", auxType: auxCCop, argLen: 1, asm: arm64.ACSETM, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 33554432}, // R26 {0, 1409286143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP }, clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotLessThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotLessEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotGreaterThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotGreaterEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThanNoov", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqualNoov", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 524288}, // R20 }, clobbers: 269156352, // R16 R17 R20 R30 }, }, { name: "LoweredZero", argLen: 3, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 65536}, // R16 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, clobbers: 65536, // R16 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R21 {1, 524288}, // R20 }, clobbers: 303759360, // R16 R17 R20 R21 R26 R30 }, }, { name: "LoweredMove", argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 131072}, // R17 {1, 65536}, // R16 {2, 318767103}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30 }, clobbers: 16973824, // R16 R17 R25 }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 33554432}, // R26 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FlagConstant", auxType: auxFlagConstant, argLen: 0, reg: regInfo{}, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LDAR", argLen: 2, faultOnNilArg0: true, asm: arm64.ALDAR, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LDARB", argLen: 2, faultOnNilArg0: true, asm: arm64.ALDARB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LDARW", argLen: 2, faultOnNilArg0: true, asm: arm64.ALDARW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "STLRB", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: arm64.ASTLRB, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "STLR", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: arm64.ASTLR, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "STLRW", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: arm64.ASTLRW, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange8", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange64Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange8Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd64Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas64Variant", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas32Variant", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd8", argLen: 3, resultNotInArgs: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr8", argLen: 3, resultNotInArgs: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd64", argLen: 3, resultNotInArgs: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr64", argLen: 3, resultNotInArgs: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, resultNotInArgs: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr32", argLen: 3, resultNotInArgs: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd8Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr8Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd64Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr64Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 9223372034975924224, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 outputs: []outputInfo{ {0, 16777216}, // R25 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "PRFM", auxType: auxInt64, argLen: 2, hasSideEffects: true, asm: arm64.APRFM, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "DMB", auxType: auxInt64, argLen: 1, hasSideEffects: true, asm: arm64.ADMB, reg: regInfo{}, }, { name: "ZERO", argLen: 0, zeroWidth: true, fixedReg: true, reg: regInfo{}, }, { name: "NEGV", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "NEGF", argLen: 1, asm: loong64.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "NEGD", argLen: 1, asm: loong64.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTD", argLen: 1, asm: loong64.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTF", argLen: 1, asm: loong64.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "ABSD", argLen: 1, asm: loong64.AABSD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CLZW", argLen: 1, asm: loong64.ACLZW, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "CLZV", argLen: 1, asm: loong64.ACLZV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "CTZW", argLen: 1, asm: loong64.ACTZW, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "CTZV", argLen: 1, asm: loong64.ACTZV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "REVB2H", argLen: 1, asm: loong64.AREVB2H, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "REVB2W", argLen: 1, asm: loong64.AREVB2W, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "REVBV", argLen: 1, asm: loong64.AREVBV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "BITREV4B", argLen: 1, asm: loong64.ABITREV4B, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "BITREVW", argLen: 1, asm: loong64.ABITREVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "BITREVV", argLen: 1, asm: loong64.ABITREVV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "VPCNT64", argLen: 1, asm: loong64.AVPCNTV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "VPCNT32", argLen: 1, asm: loong64.AVPCNTW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "VPCNT16", argLen: 1, asm: loong64.AVPCNTH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "ADDV", argLen: 2, commutative: true, asm: loong64.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ADDVconst", auxType: auxInt64, argLen: 1, asm: loong64.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SUBV", argLen: 2, asm: loong64.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SUBVconst", auxType: auxInt64, argLen: 1, asm: loong64.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MULV", argLen: 2, commutative: true, asm: loong64.AMULV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MULHV", argLen: 2, commutative: true, asm: loong64.AMULHV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MULHVU", argLen: 2, commutative: true, asm: loong64.AMULHVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "DIVV", argLen: 2, asm: loong64.ADIVV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "DIVVU", argLen: 2, asm: loong64.ADIVVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "REMV", argLen: 2, asm: loong64.AREMV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "REMVU", argLen: 2, asm: loong64.AREMVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: loong64.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: loong64.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBF", argLen: 2, asm: loong64.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBD", argLen: 2, asm: loong64.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: loong64.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: loong64.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVF", argLen: 2, asm: loong64.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVD", argLen: 2, asm: loong64.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: loong64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, asm: loong64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: loong64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: loong64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: loong64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: loong64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: loong64.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "NORconst", auxType: auxInt64, argLen: 1, asm: loong64.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "FMADDF", argLen: 3, commutative: true, asm: loong64.AFMADDF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDD", argLen: 3, commutative: true, asm: loong64.AFMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBF", argLen: 3, commutative: true, asm: loong64.AFMSUBF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBD", argLen: 3, commutative: true, asm: loong64.AFMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDF", argLen: 3, commutative: true, asm: loong64.AFNMADDF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDD", argLen: 3, commutative: true, asm: loong64.AFNMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBF", argLen: 3, commutative: true, asm: loong64.AFNMSUBF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBD", argLen: 3, commutative: true, asm: loong64.AFNMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMINF", argLen: 2, commutative: true, resultNotInArgs: true, asm: loong64.AFMINF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMIND", argLen: 2, commutative: true, resultNotInArgs: true, asm: loong64.AFMIND, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMAXF", argLen: 2, commutative: true, resultNotInArgs: true, asm: loong64.AFMAXF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMAXD", argLen: 2, commutative: true, resultNotInArgs: true, asm: loong64.AFMAXD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MASKEQZ", argLen: 2, asm: loong64.AMASKEQZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MASKNEZ", argLen: 2, asm: loong64.AMASKNEZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "FCOPYSGD", argLen: 2, asm: loong64.AFCOPYSGD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SLL", argLen: 2, asm: loong64.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SLLV", argLen: 2, asm: loong64.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SLLconst", auxType: auxInt64, argLen: 1, asm: loong64.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SLLVconst", auxType: auxInt64, argLen: 1, asm: loong64.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRL", argLen: 2, asm: loong64.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRLV", argLen: 2, asm: loong64.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRLconst", auxType: auxInt64, argLen: 1, asm: loong64.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRLVconst", auxType: auxInt64, argLen: 1, asm: loong64.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRA", argLen: 2, asm: loong64.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRAV", argLen: 2, asm: loong64.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRAconst", auxType: auxInt64, argLen: 1, asm: loong64.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRAVconst", auxType: auxInt64, argLen: 1, asm: loong64.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ROTR", argLen: 2, asm: loong64.AROTR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ROTRV", argLen: 2, asm: loong64.AROTRV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ROTRconst", auxType: auxInt64, argLen: 1, asm: loong64.AROTR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ROTRVconst", auxType: auxInt64, argLen: 1, asm: loong64.AROTRV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SGT", argLen: 2, asm: loong64.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SGTconst", auxType: auxInt64, argLen: 1, asm: loong64.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SGTU", argLen: 2, asm: loong64.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SGTUconst", auxType: auxInt64, argLen: 1, asm: loong64.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "CMPEQF", argLen: 2, asm: loong64.ACMPEQF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPEQD", argLen: 2, asm: loong64.ACMPEQD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGEF", argLen: 2, asm: loong64.ACMPGEF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGED", argLen: 2, asm: loong64.ACMPGED, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTF", argLen: 2, asm: loong64.ACMPGTF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTD", argLen: 2, asm: loong64.ACMPGTD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "BSTRPICKW", auxType: auxInt64, argLen: 1, asm: loong64.ABSTRPICKW, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "BSTRPICKV", auxType: auxInt64, argLen: 1, asm: loong64.ABSTRPICKV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVVconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: loong64.AMOVV, reg: regInfo{ outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVFconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: loong64.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: loong64.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018427387908}, // SP SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVVload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVloadidx", argLen: 3, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWUloadidx", argLen: 3, asm: loong64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHUloadidx", argLen: 3, asm: loong64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVBloadidx", argLen: 3, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVBUloadidx", argLen: 3, asm: loong64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVFloadidx", argLen: 3, asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDloadidx", argLen: 3, asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVVstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVVstoreidx", argLen: 4, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVFstoreidx", argLen: 4, asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDstoreidx", argLen: 4, asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVVstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVBstorezeroidx", argLen: 3, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVHstorezeroidx", argLen: 3, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVWstorezeroidx", argLen: 3, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVVstorezeroidx", argLen: 3, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVWfpgp", argLen: 1, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWgpfp", argLen: 1, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVfpgp", argLen: 1, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVVgpfp", argLen: 1, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBreg", argLen: 1, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVBUreg", argLen: 1, asm: loong64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHreg", argLen: 1, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHUreg", argLen: 1, asm: loong64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWreg", argLen: 1, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWUreg", argLen: 1, asm: loong64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVVreg", argLen: 1, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVVnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWF", argLen: 1, asm: loong64.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVWD", argLen: 1, asm: loong64.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVF", argLen: 1, asm: loong64.AMOVVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVD", argLen: 1, asm: loong64.AMOVVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFW", argLen: 1, asm: loong64.ATRUNCFW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDW", argLen: 1, asm: loong64.ATRUNCDW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFV", argLen: 1, asm: loong64.ATRUNCFV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDV", argLen: 1, asm: loong64.ATRUNCDV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVFD", argLen: 1, asm: loong64.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDF", argLen: 1, asm: loong64.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 268435456}, // R29 {0, 1071644668}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 524288}, // R20 }, clobbers: 524290, // R1 R20 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R21 {1, 524288}, // R20 }, clobbers: 1572866, // R1 R20 R21 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 524288}, // R20 {1, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 524288, // R20 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R21 {1, 524288}, // R20 {2, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 1572864, // R20 R21 }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicLoad64", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStore64", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStore8Variant", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStore32Variant", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStore64Variant", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicExchange8Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicCas64Variant", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicCas32Variant", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, asm: loong64.AAMANDDBW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicOr32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, asm: loong64.AAMORDBW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAnd32value", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, asm: loong64.AAMANDDBW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAnd64value", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, asm: loong64.AAMANDDBV, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicOr32value", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, asm: loong64.AAMORDBW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicOr64value", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, asm: loong64.AAMORDBV, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "FPFlagTrue", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "FPFlagFalse", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 268435456}, // R29 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 outputs: []outputInfo{ {0, 268435456}, // R29 }, }, }, { name: "LoweredPubBarrier", argLen: 1, hasSideEffects: true, asm: loong64.ADBAR, reg: regInfo{}, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4194304}, // R23 {1, 8388608}, // R24 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R21 {1, 4194304}, // R23 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 524288}, // R20 {1, 1048576}, // R21 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: mips.AADDU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, asm: mips.AADDU, reg: regInfo{ inputs: []inputInfo{ {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SUB", argLen: 2, asm: mips.ASUBU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, asm: mips.ASUBU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: mips.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, clobbers: 105553116266496, // HI LO outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MULT", argLen: 2, commutative: true, asm: mips.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "MULTU", argLen: 2, commutative: true, asm: mips.AMULU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "DIV", argLen: 2, asm: mips.ADIV, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "DIVU", argLen: 2, asm: mips.ADIVU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: mips.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: mips.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SUBF", argLen: 2, asm: mips.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SUBD", argLen: 2, asm: mips.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: mips.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: mips.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "DIVF", argLen: 2, asm: mips.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "DIVD", argLen: 2, asm: mips.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "ANDconst", auxType: auxInt32, argLen: 1, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "ORconst", auxType: auxInt32, argLen: 1, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "XORconst", auxType: auxInt32, argLen: 1, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NORconst", auxType: auxInt32, argLen: 1, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NEG", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NEGF", argLen: 1, asm: mips.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "NEGD", argLen: 1, asm: mips.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "ABSD", argLen: 1, asm: mips.AABSD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SQRTD", argLen: 1, asm: mips.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SQRTF", argLen: 1, asm: mips.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SLL", argLen: 2, asm: mips.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SLLconst", auxType: auxInt32, argLen: 1, asm: mips.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRL", argLen: 2, asm: mips.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRLconst", auxType: auxInt32, argLen: 1, asm: mips.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRA", argLen: 2, asm: mips.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRAconst", auxType: auxInt32, argLen: 1, asm: mips.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CLZ", argLen: 1, asm: mips.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGT", argLen: 2, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTconst", auxType: auxInt32, argLen: 1, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTzero", argLen: 1, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTU", argLen: 2, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTUconst", auxType: auxInt32, argLen: 1, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTUzero", argLen: 1, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CMPEQF", argLen: 2, asm: mips.ACMPEQF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPEQD", argLen: 2, asm: mips.ACMPEQD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGEF", argLen: 2, asm: mips.ACMPGEF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGED", argLen: 2, asm: mips.ACMPGED, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGTF", argLen: 2, asm: mips.ACMPGTF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGTD", argLen: 2, asm: mips.ACMPGTD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVWconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: mips.AMOVW, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVFconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: mips.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: mips.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVWaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 140737555464192}, // SP SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVWfpgp", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWgpfp", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVBreg", argLen: 1, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVBUreg", argLen: 1, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHreg", argLen: 1, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHUreg", argLen: 1, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWreg", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CMOVZ", argLen: 3, resultInArg0: true, asm: mips.ACMOVZ, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CMOVZzero", argLen: 2, resultInArg0: true, asm: mips.ACMOVZ, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWF", argLen: 1, asm: mips.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVWD", argLen: 1, asm: mips.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "TRUNCFW", argLen: 1, asm: mips.ATRUNCFW, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "TRUNCDW", argLen: 1, asm: mips.ATRUNCDW, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVFD", argLen: 1, asm: mips.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVDF", argLen: 1, asm: mips.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4194304}, // R22 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 }, clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicStorezero", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicExchange", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicAdd", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicAddconst", auxType: auxInt32, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicCas", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicAnd", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicOr", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredZero", auxType: auxInt32, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, clobbers: 2, // R1 }, }, { name: "LoweredMove", auxType: auxInt32, argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, clobbers: 6, // R1 R2 }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, }, }, { name: "FPFlagTrue", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "FPFlagFalse", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4194304}, // R22 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO outputs: []outputInfo{ {0, 16777216}, // R25 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 8}, // R3 {1, 16}, // R4 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicExtendA", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 8}, // R3 {2, 16}, // R4 }, }, }, { name: "LoweredPanicExtendB", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 4}, // R2 {2, 8}, // R3 }, }, }, { name: "LoweredPanicExtendC", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 2}, // R1 {2, 4}, // R2 }, }, }, { name: "ADDV", argLen: 2, commutative: true, asm: mips.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "ADDVconst", auxType: auxInt64, argLen: 1, asm: mips.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SUBV", argLen: 2, asm: mips.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SUBVconst", auxType: auxInt64, argLen: 1, asm: mips.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MULV", argLen: 2, commutative: true, asm: mips.AMULV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "MULVU", argLen: 2, commutative: true, asm: mips.AMULVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "DIVV", argLen: 2, asm: mips.ADIVV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "DIVVU", argLen: 2, asm: mips.ADIVVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: mips.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: mips.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBF", argLen: 2, asm: mips.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBD", argLen: 2, asm: mips.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: mips.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: mips.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVF", argLen: 2, asm: mips.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVD", argLen: 2, asm: mips.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NORconst", auxType: auxInt64, argLen: 1, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NEGV", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NEGF", argLen: 1, asm: mips.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "NEGD", argLen: 1, asm: mips.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "ABSD", argLen: 1, asm: mips.AABSD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTD", argLen: 1, asm: mips.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTF", argLen: 1, asm: mips.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SLLV", argLen: 2, asm: mips.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SLLVconst", auxType: auxInt64, argLen: 1, asm: mips.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRLV", argLen: 2, asm: mips.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRLVconst", auxType: auxInt64, argLen: 1, asm: mips.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRAV", argLen: 2, asm: mips.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRAVconst", auxType: auxInt64, argLen: 1, asm: mips.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGT", argLen: 2, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGTconst", auxType: auxInt64, argLen: 1, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGTU", argLen: 2, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGTUconst", auxType: auxInt64, argLen: 1, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "CMPEQF", argLen: 2, asm: mips.ACMPEQF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPEQD", argLen: 2, asm: mips.ACMPEQD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGEF", argLen: 2, asm: mips.ACMPGEF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGED", argLen: 2, asm: mips.ACMPGED, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTF", argLen: 2, asm: mips.ACMPGTF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTD", argLen: 2, asm: mips.ACMPGTD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: mips.AMOVV, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVFconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: mips.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: mips.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018460942336}, // SP SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVVstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVVstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVWfpgp", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWgpfp", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVfpgp", argLen: 1, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVgpfp", argLen: 1, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBreg", argLen: 1, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVBUreg", argLen: 1, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHreg", argLen: 1, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHUreg", argLen: 1, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWreg", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWUreg", argLen: 1, asm: mips.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVreg", argLen: 1, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWF", argLen: 1, asm: mips.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVWD", argLen: 1, asm: mips.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVF", argLen: 1, asm: mips.AMOVVF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVD", argLen: 1, asm: mips.AMOVVD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFW", argLen: 1, asm: mips.ATRUNCFW, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDW", argLen: 1, asm: mips.ATRUNCDW, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFV", argLen: 1, asm: mips.ATRUNCFV, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDV", argLen: 1, asm: mips.ATRUNCDV, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVFD", argLen: 1, asm: mips.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDF", argLen: 1, asm: mips.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4194304}, // R22 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 }, clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 134217730, // R1 R31 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 }, clobbers: 134217734, // R1 R2 R31 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 2, // R1 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 6, // R1 R2 }, }, { name: "LoweredAtomicAnd32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicOr32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicLoad64", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStore64", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStorezero32", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStorezero64", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAddconst32", auxType: auxInt32, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAddconst64", auxType: auxInt64, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, }, }, { name: "FPFlagTrue", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "FPFlagFalse", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4194304}, // R22 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO outputs: []outputInfo{ {0, 16777216}, // R25 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 8}, // R3 {1, 16}, // R4 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: ppc64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDCC", argLen: 2, commutative: true, asm: ppc64.AADDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDconst", auxType: auxInt64, argLen: 1, asm: ppc64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDCCconst", auxType: auxInt64, argLen: 1, asm: ppc64.AADDCCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FADD", argLen: 2, commutative: true, asm: ppc64.AFADD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: ppc64.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "SUB", argLen: 2, asm: ppc64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBCC", argLen: 2, asm: ppc64.ASUBCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBFCconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FSUB", argLen: 2, asm: ppc64.AFSUB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FSUBS", argLen: 2, asm: ppc64.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "XSMINJDP", argLen: 2, asm: ppc64.AXSMINJDP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "XSMAXJDP", argLen: 2, asm: ppc64.AXSMAXJDP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MULLD", argLen: 2, commutative: true, asm: ppc64.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLW", argLen: 2, commutative: true, asm: ppc64.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLDconst", auxType: auxInt32, argLen: 1, asm: ppc64.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLWconst", auxType: auxInt32, argLen: 1, asm: ppc64.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MADDLD", argLen: 3, asm: ppc64.AMADDLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHD", argLen: 2, commutative: true, asm: ppc64.AMULHD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHW", argLen: 2, commutative: true, asm: ppc64.AMULHW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHDU", argLen: 2, commutative: true, asm: ppc64.AMULHDU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHDUCC", argLen: 2, commutative: true, asm: ppc64.AMULHDUCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHWU", argLen: 2, commutative: true, asm: ppc64.AMULHWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMUL", argLen: 2, commutative: true, asm: ppc64.AFMUL, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: ppc64.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMADD", argLen: 3, asm: ppc64.AFMADD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMADDS", argLen: 3, asm: ppc64.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMSUB", argLen: 3, asm: ppc64.AFMSUB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMSUBS", argLen: 3, asm: ppc64.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "SRAD", argLen: 2, asm: ppc64.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRAW", argLen: 2, asm: ppc64.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRD", argLen: 2, asm: ppc64.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRW", argLen: 2, asm: ppc64.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLD", argLen: 2, asm: ppc64.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLW", argLen: 2, asm: ppc64.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTL", argLen: 2, asm: ppc64.AROTL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTLW", argLen: 2, asm: ppc64.AROTLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CLRLSLWI", auxType: auxInt32, argLen: 1, asm: ppc64.ACLRLSLWI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CLRLSLDI", auxType: auxInt32, argLen: 1, asm: ppc64.ACLRLSLDI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDC", argLen: 2, commutative: true, asm: ppc64.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBC", argLen: 2, asm: ppc64.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDCconst", auxType: auxInt64, argLen: 1, asm: ppc64.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBCconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDE", argLen: 3, commutative: true, asm: ppc64.AADDE, reg: regInfo{ inputs: []inputInfo{ {2, 9223372036854775808}, // XER {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDZE", argLen: 2, asm: ppc64.AADDZE, reg: regInfo{ inputs: []inputInfo{ {1, 9223372036854775808}, // XER {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBE", argLen: 3, asm: ppc64.ASUBE, reg: regInfo{ inputs: []inputInfo{ {2, 9223372036854775808}, // XER {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDZEzero", argLen: 1, asm: ppc64.AADDZE, reg: regInfo{ inputs: []inputInfo{ {0, 9223372036854775808}, // XER }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBZEzero", argLen: 1, asm: ppc64.ASUBZE, reg: regInfo{ inputs: []inputInfo{ {0, 9223372036854775808}, // XER }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRADconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRAWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRDconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLDconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTLconst", auxType: auxInt64, argLen: 1, asm: ppc64.AROTL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTLWconst", auxType: auxInt64, argLen: 1, asm: ppc64.AROTLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "EXTSWSLconst", auxType: auxInt64, argLen: 1, asm: ppc64.AEXTSWSLI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLWINM", auxType: auxInt64, argLen: 1, asm: ppc64.ARLWNM, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLWNM", auxType: auxInt64, argLen: 2, asm: ppc64.ARLWNM, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLWMI", auxType: auxInt64, argLen: 2, resultInArg0: true, asm: ppc64.ARLWMI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLDICL", auxType: auxInt64, argLen: 1, asm: ppc64.ARLDICL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLDICLCC", auxType: auxInt64, argLen: 1, asm: ppc64.ARLDICLCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLDICR", auxType: auxInt64, argLen: 1, asm: ppc64.ARLDICR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTLZD", argLen: 1, asm: ppc64.ACNTLZD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTLZDCC", argLen: 1, asm: ppc64.ACNTLZDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTLZW", argLen: 1, asm: ppc64.ACNTLZW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTTZD", argLen: 1, asm: ppc64.ACNTTZD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTTZW", argLen: 1, asm: ppc64.ACNTTZW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "POPCNTD", argLen: 1, asm: ppc64.APOPCNTD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "POPCNTW", argLen: 1, asm: ppc64.APOPCNTW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "POPCNTB", argLen: 1, asm: ppc64.APOPCNTB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FDIV", argLen: 2, asm: ppc64.AFDIV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FDIVS", argLen: 2, asm: ppc64.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "DIVD", argLen: 2, asm: ppc64.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVW", argLen: 2, asm: ppc64.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVDU", argLen: 2, asm: ppc64.ADIVDU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVWU", argLen: 2, asm: ppc64.ADIVWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODUD", argLen: 2, asm: ppc64.AMODUD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODSD", argLen: 2, asm: ppc64.AMODSD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODUW", argLen: 2, asm: ppc64.AMODUW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODSW", argLen: 2, asm: ppc64.AMODSW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FCTIDZ", argLen: 1, asm: ppc64.AFCTIDZ, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCTIWZ", argLen: 1, asm: ppc64.AFCTIWZ, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCFID", argLen: 1, asm: ppc64.AFCFID, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCFIDS", argLen: 1, asm: ppc64.AFCFIDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FRSP", argLen: 1, asm: ppc64.AFRSP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MFVSRD", argLen: 1, asm: ppc64.AMFVSRD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MTVSRD", argLen: 1, asm: ppc64.AMTVSRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDN", argLen: 2, asm: ppc64.AANDN, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDNCC", argLen: 2, asm: ppc64.AANDNCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDCC", argLen: 2, commutative: true, asm: ppc64.AANDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ORN", argLen: 2, asm: ppc64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ORCC", argLen: 2, commutative: true, asm: ppc64.AORCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: ppc64.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NORCC", argLen: 2, commutative: true, asm: ppc64.ANORCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: ppc64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XORCC", argLen: 2, commutative: true, asm: ppc64.AXORCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "EQV", argLen: 2, commutative: true, asm: ppc64.AEQV, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NEG", argLen: 1, asm: ppc64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NEGCC", argLen: 1, asm: ppc64.ANEGCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "BRD", argLen: 1, asm: ppc64.ABRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "BRW", argLen: 1, asm: ppc64.ABRW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "BRH", argLen: 1, asm: ppc64.ABRH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FNEG", argLen: 1, asm: ppc64.AFNEG, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FSQRT", argLen: 1, asm: ppc64.AFSQRT, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FSQRTS", argLen: 1, asm: ppc64.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FFLOOR", argLen: 1, asm: ppc64.AFRIM, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCEIL", argLen: 1, asm: ppc64.AFRIP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FTRUNC", argLen: 1, asm: ppc64.AFRIZ, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FROUND", argLen: 1, asm: ppc64.AFRIN, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FABS", argLen: 1, asm: ppc64.AFABS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FNABS", argLen: 1, asm: ppc64.AFNABS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCPSGN", argLen: 2, asm: ppc64.AFCPSGN, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: ppc64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDCCconst", auxType: auxInt64, argLen: 1, asm: ppc64.AANDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, clobberFlags: true, asm: ppc64.AANDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBreg", argLen: 1, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZreg", argLen: 1, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHreg", argLen: 1, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZreg", argLen: 1, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWreg", argLen: 1, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZreg", argLen: 1, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRload", argLen: 2, faultOnNilArg0: true, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRload", argLen: 2, faultOnNilArg0: true, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHBRload", argLen: 2, faultOnNilArg0: true, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZloadidx", argLen: 3, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZloadidx", argLen: 3, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZloadidx", argLen: 3, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDloadidx", argLen: 3, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHBRloadidx", argLen: 3, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRloadidx", argLen: 3, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRloadidx", argLen: 3, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDloadidx", argLen: 3, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSloadidx", argLen: 3, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "DCBT", auxType: auxInt64, argLen: 2, hasSideEffects: true, asm: ppc64.ADCBT, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRstore", argLen: 3, faultOnNilArg0: true, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRstore", argLen: 3, faultOnNilArg0: true, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHBRstore", argLen: 3, faultOnNilArg0: true, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstoreidx", argLen: 4, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDstoreidx", argLen: 4, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSstoreidx", argLen: 4, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MOVHBRstoreidx", argLen: 4, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRstoreidx", argLen: 4, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRstoreidx", argLen: 4, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: ppc64.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: ppc64.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: ppc64.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCMPU", argLen: 2, asm: ppc64.AFCMPU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "CMP", argLen: 2, asm: ppc64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPU", argLen: 2, asm: ppc64.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPW", argLen: 2, asm: ppc64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWU", argLen: 2, asm: ppc64.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPconst", auxType: auxInt64, argLen: 1, asm: ppc64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPUconst", auxType: auxInt64, argLen: 1, asm: ppc64.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: ppc64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWUconst", auxType: auxInt32, argLen: 1, asm: ppc64.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ISEL", auxType: auxInt32, argLen: 3, asm: ppc64.AISEL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ISELZ", auxType: auxInt32, argLen: 2, asm: ppc64.AISEL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SETBC", auxType: auxInt32, argLen: 1, asm: ppc64.ASETBC, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SETBCR", auxType: auxInt32, argLen: 1, asm: ppc64.ASETBCR, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FLessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FLessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FGreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FGreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 2048}, // R11 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 2147483648, // R31 }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4096}, // R12 {1, 2048}, // R11 }, clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4096}, // R12 }, clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 }, clobbers: 1048576, // R20 }, }, { name: "LoweredZeroShort", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredQuadZeroShort", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredQuadZero", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 }, clobbers: 1048576, // R20 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 3145728, // R20 R21 }, }, { name: "LoweredMoveShort", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredQuadMove", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 3145728, // R20 R21 }, }, { name: "LoweredQuadMoveShort", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicStore8", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicStore32", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicStore64", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoad8", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoad32", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoad64", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoadPtr", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicExchange8", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicCas64", auxType: auxInt64, argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicCas32", auxType: auxInt64, argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAnd8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicOr8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicOr32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER outputs: []outputInfo{ {0, 536870912}, // R29 }, }, }, { name: "LoweredPubBarrier", argLen: 1, hasSideEffects: true, asm: ppc64.ALWSYNC, reg: regInfo{}, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 64}, // R6 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 32}, // R5 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 8}, // R3 {1, 16}, // R4 }, }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT", argLen: 0, reg: regInfo{}, }, { name: "ADD", argLen: 2, commutative: true, asm: riscv.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ADDI", auxType: auxInt64, argLen: 1, asm: riscv.AADDI, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ADDIW", auxType: auxInt64, argLen: 1, asm: riscv.AADDIW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "NEG", argLen: 1, asm: riscv.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "NEGW", argLen: 1, asm: riscv.ANEGW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SUB", argLen: 2, asm: riscv.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SUBW", argLen: 2, asm: riscv.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: riscv.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MULW", argLen: 2, commutative: true, asm: riscv.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MULH", argLen: 2, commutative: true, asm: riscv.AMULH, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MULHU", argLen: 2, commutative: true, asm: riscv.AMULHU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredMuluhilo", argLen: 2, resultNotInArgs: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredMuluover", argLen: 2, resultNotInArgs: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIV", argLen: 2, asm: riscv.ADIV, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIVU", argLen: 2, asm: riscv.ADIVU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIVW", argLen: 2, asm: riscv.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIVUW", argLen: 2, asm: riscv.ADIVUW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REM", argLen: 2, asm: riscv.AREM, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REMU", argLen: 2, asm: riscv.AREMU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REMW", argLen: 2, asm: riscv.AREMW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REMUW", argLen: 2, asm: riscv.AREMUW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: riscv.AMOV, reg: regInfo{ outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVDstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVBreg", argLen: 1, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHreg", argLen: 1, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWreg", argLen: 1, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDreg", argLen: 1, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBUreg", argLen: 1, asm: riscv.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHUreg", argLen: 1, asm: riscv.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWUreg", argLen: 1, asm: riscv.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLL", argLen: 2, asm: riscv.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLLW", argLen: 2, asm: riscv.ASLLW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRA", argLen: 2, asm: riscv.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRAW", argLen: 2, asm: riscv.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRL", argLen: 2, asm: riscv.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRLW", argLen: 2, asm: riscv.ASRLW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLLI", auxType: auxInt64, argLen: 1, asm: riscv.ASLLI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLLIW", auxType: auxInt64, argLen: 1, asm: riscv.ASLLIW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRAI", auxType: auxInt64, argLen: 1, asm: riscv.ASRAI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRAIW", auxType: auxInt64, argLen: 1, asm: riscv.ASRAIW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRLI", auxType: auxInt64, argLen: 1, asm: riscv.ASRLI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRLIW", auxType: auxInt64, argLen: 1, asm: riscv.ASRLIW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SH1ADD", argLen: 2, asm: riscv.ASH1ADD, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SH2ADD", argLen: 2, asm: riscv.ASH2ADD, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SH3ADD", argLen: 2, asm: riscv.ASH3ADD, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: riscv.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ANDN", argLen: 2, asm: riscv.AANDN, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ANDI", auxType: auxInt64, argLen: 1, asm: riscv.AANDI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "CLZ", argLen: 1, asm: riscv.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "CLZW", argLen: 1, asm: riscv.ACLZW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "CTZ", argLen: 1, asm: riscv.ACTZ, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "CTZW", argLen: 1, asm: riscv.ACTZW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "NOT", argLen: 1, asm: riscv.ANOT, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: riscv.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ORN", argLen: 2, asm: riscv.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ORI", auxType: auxInt64, argLen: 1, asm: riscv.AORI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REV8", argLen: 1, asm: riscv.AREV8, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ROL", argLen: 2, asm: riscv.AROL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ROLW", argLen: 2, asm: riscv.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ROR", argLen: 2, asm: riscv.AROR, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "RORI", auxType: auxInt64, argLen: 1, asm: riscv.ARORI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "RORIW", auxType: auxInt64, argLen: 1, asm: riscv.ARORIW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "RORW", argLen: 2, asm: riscv.ARORW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "XNOR", argLen: 2, commutative: true, asm: riscv.AXNOR, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: riscv.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "XORI", auxType: auxInt64, argLen: 1, asm: riscv.AXORI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MIN", argLen: 2, commutative: true, asm: riscv.AMIN, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MAX", argLen: 2, commutative: true, asm: riscv.AMAX, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MINU", argLen: 2, commutative: true, asm: riscv.AMINU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MAXU", argLen: 2, commutative: true, asm: riscv.AMAXU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SEQZ", argLen: 1, asm: riscv.ASEQZ, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SNEZ", argLen: 1, asm: riscv.ASNEZ, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLT", argLen: 2, asm: riscv.ASLT, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLTI", auxType: auxInt64, argLen: 1, asm: riscv.ASLTI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLTU", argLen: 2, asm: riscv.ASLTU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLTIU", auxType: auxInt64, argLen: 1, asm: riscv.ASLTIU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, call: true, reg: regInfo{ clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, call: true, tailCall: true, reg: regInfo{ clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 33554432}, // X26 {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 16777216}, // X25 }, clobbers: 16777216, // X25 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 16777216}, // X25 {1, 8388608}, // X24 }, clobbers: 25165824, // X24 X25 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 16, // X5 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 32}, // X6 {2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 112, // X5 X6 X7 }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicLoad64", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "LoweredAtomicStore64", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: riscv.AAMOANDW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, }, }, { name: "LoweredAtomicOr32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: riscv.AAMOORW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 33554432}, // X26 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 outputs: []outputInfo{ {0, 8388608}, // X24 }, }, }, { name: "LoweredPubBarrier", argLen: 1, hasSideEffects: true, asm: riscv.AFENCE, reg: regInfo{}, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // X7 {1, 134217728}, // X28 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // X6 {1, 64}, // X7 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 32}, // X6 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: riscv.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBS", argLen: 2, asm: riscv.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: riscv.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVS", argLen: 2, asm: riscv.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDS", argLen: 3, commutative: true, asm: riscv.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBS", argLen: 3, commutative: true, asm: riscv.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDS", argLen: 3, commutative: true, asm: riscv.AFNMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBS", argLen: 3, commutative: true, asm: riscv.AFNMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTS", argLen: 1, asm: riscv.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGS", argLen: 1, asm: riscv.AFNEGS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMVSX", argLen: 1, asm: riscv.AFMVSX, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTSW", argLen: 1, asm: riscv.AFCVTSW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTSL", argLen: 1, asm: riscv.AFCVTSL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTWS", argLen: 1, asm: riscv.AFCVTWS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FCVTLS", argLen: 1, asm: riscv.AFCVTLS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FMOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FEQS", argLen: 2, commutative: true, asm: riscv.AFEQS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FNES", argLen: 2, commutative: true, asm: riscv.AFNES, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLTS", argLen: 2, asm: riscv.AFLTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLES", argLen: 2, asm: riscv.AFLES, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredFMAXS", argLen: 2, commutative: true, resultNotInArgs: true, asm: riscv.AFMAXS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredFMINS", argLen: 2, commutative: true, resultNotInArgs: true, asm: riscv.AFMINS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FADDD", argLen: 2, commutative: true, asm: riscv.AFADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBD", argLen: 2, asm: riscv.AFSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULD", argLen: 2, commutative: true, asm: riscv.AFMULD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVD", argLen: 2, asm: riscv.AFDIVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDD", argLen: 3, commutative: true, asm: riscv.AFMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBD", argLen: 3, commutative: true, asm: riscv.AFMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDD", argLen: 3, commutative: true, asm: riscv.AFNMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBD", argLen: 3, commutative: true, asm: riscv.AFNMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTD", argLen: 1, asm: riscv.AFSQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGD", argLen: 1, asm: riscv.AFNEGD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FABSD", argLen: 1, asm: riscv.AFABSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSGNJD", argLen: 2, asm: riscv.AFSGNJD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMVDX", argLen: 1, asm: riscv.AFMVDX, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTDW", argLen: 1, asm: riscv.AFCVTDW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTDL", argLen: 1, asm: riscv.AFCVTDL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTWD", argLen: 1, asm: riscv.AFCVTWD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FCVTLD", argLen: 1, asm: riscv.AFCVTLD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FCVTDS", argLen: 1, asm: riscv.AFCVTDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTSD", argLen: 1, asm: riscv.AFCVTSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FEQD", argLen: 2, commutative: true, asm: riscv.AFEQD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FNED", argLen: 2, commutative: true, asm: riscv.AFNED, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLTD", argLen: 2, asm: riscv.AFLTD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLED", argLen: 2, asm: riscv.AFLED, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredFMIND", argLen: 2, commutative: true, resultNotInArgs: true, asm: riscv.AFMIND, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredFMAXD", argLen: 2, commutative: true, resultNotInArgs: true, asm: riscv.AFMAXD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FADDS", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FADD", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFADD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FSUBS", argLen: 2, resultInArg0: true, asm: s390x.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FSUB", argLen: 2, resultInArg0: true, asm: s390x.AFSUB, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMULS", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMUL", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFMUL, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FDIVS", argLen: 2, resultInArg0: true, asm: s390x.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FDIV", argLen: 2, resultInArg0: true, asm: s390x.AFDIV, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FNEGS", argLen: 1, clobberFlags: true, asm: s390x.AFNEGS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FNEG", argLen: 1, clobberFlags: true, asm: s390x.AFNEG, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMADDS", argLen: 3, resultInArg0: true, asm: s390x.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMADD", argLen: 3, resultInArg0: true, asm: s390x.AFMADD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMSUBS", argLen: 3, resultInArg0: true, asm: s390x.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMSUB", argLen: 3, resultInArg0: true, asm: s390x.AFMSUB, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LPDFR", argLen: 1, asm: s390x.ALPDFR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LNDFR", argLen: 1, asm: s390x.ALNDFR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CPSDR", argLen: 2, asm: s390x.ACPSDR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FIDBR", auxType: auxInt8, argLen: 1, asm: s390x.AFIDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: s390x.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: s390x.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSloadidx", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDloadidx", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSstoreidx", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDstoreidx", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ADD", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AADD, reg: regInfo{ inputs: []inputInfo{ {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AADDW, reg: regInfo{ inputs: []inputInfo{ {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: s390x.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDWconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: s390x.AADDW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AADDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUB", argLen: 2, clobberFlags: true, asm: s390x.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBW", argLen: 2, clobberFlags: true, asm: s390x.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLD", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLW", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLDconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULHD", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULHD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULHDU", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULHDU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVD", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVDU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVDU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVWU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVWU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODD", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODDU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODDU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODWU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODWU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "AND", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "OR", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XOR", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDC", argLen: 2, commutative: true, asm: s390x.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDCconst", auxType: auxInt16, argLen: 1, asm: s390x.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDE", argLen: 3, commutative: true, resultInArg0: true, asm: s390x.AADDE, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBC", argLen: 2, asm: s390x.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBE", argLen: 3, resultInArg0: true, asm: s390x.ASUBE, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CMP", argLen: 2, asm: s390x.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPW", argLen: 2, asm: s390x.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPU", argLen: 2, asm: s390x.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPWU", argLen: 2, asm: s390x.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPUconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPWUconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "FCMPS", argLen: 2, asm: s390x.ACEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FCMP", argLen: 2, asm: s390x.AFCMPU, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LTDBR", argLen: 1, asm: s390x.ALTDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LTEBR", argLen: 1, asm: s390x.ALTEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SLD", argLen: 2, asm: s390x.ASLD, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SLW", argLen: 2, asm: s390x.ASLW, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SLDconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SLWconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRD", argLen: 2, asm: s390x.ASRD, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRW", argLen: 2, asm: s390x.ASRW, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRDconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRWconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRAD", argLen: 2, clobberFlags: true, asm: s390x.ASRAD, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRAW", argLen: 2, clobberFlags: true, asm: s390x.ASRAW, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRADconst", auxType: auxUInt8, argLen: 1, clobberFlags: true, asm: s390x.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRAWconst", auxType: auxUInt8, argLen: 1, clobberFlags: true, asm: s390x.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RLLG", argLen: 2, asm: s390x.ARLLG, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RLL", argLen: 2, asm: s390x.ARLL, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RLLconst", auxType: auxUInt8, argLen: 1, asm: s390x.ARLL, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RXSBG", auxType: auxS390XRotateParams, argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ARXSBG, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RISBGZ", auxType: auxS390XRotateParams, argLen: 1, clobberFlags: true, asm: s390x.ARISBGZ, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NEG", argLen: 1, clobberFlags: true, asm: s390x.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NEGW", argLen: 1, clobberFlags: true, asm: s390x.ANEGW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NOT", argLen: 1, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NOTW", argLen: 1, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "FSQRT", argLen: 1, asm: s390x.AFSQRT, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FSQRTS", argLen: 1, asm: s390x.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LOCGR", auxType: auxS390XCCMask, argLen: 3, resultInArg0: true, asm: s390x.ALOCGR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBreg", argLen: 1, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBZreg", argLen: 1, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHreg", argLen: 1, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHZreg", argLen: 1, asm: s390x.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWreg", argLen: 1, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZreg", argLen: 1, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: s390x.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LDGR", argLen: 1, asm: s390x.ALDGR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LGDR", argLen: 1, asm: s390x.ALGDR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CFDBRA", argLen: 1, clobberFlags: true, asm: s390x.ACFDBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CGDBRA", argLen: 1, clobberFlags: true, asm: s390x.ACGDBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CFEBRA", argLen: 1, clobberFlags: true, asm: s390x.ACFEBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CGEBRA", argLen: 1, clobberFlags: true, asm: s390x.ACGEBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CEFBRA", argLen: 1, clobberFlags: true, asm: s390x.ACEFBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDFBRA", argLen: 1, clobberFlags: true, asm: s390x.ACDFBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CEGBRA", argLen: 1, clobberFlags: true, asm: s390x.ACEGBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDGBRA", argLen: 1, clobberFlags: true, asm: s390x.ACDGBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CLFEBR", argLen: 1, clobberFlags: true, asm: s390x.ACLFEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CLFDBR", argLen: 1, clobberFlags: true, asm: s390x.ACLFDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CLGEBR", argLen: 1, clobberFlags: true, asm: s390x.ACLGEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CLGDBR", argLen: 1, clobberFlags: true, asm: s390x.ACLGDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CELFBR", argLen: 1, clobberFlags: true, asm: s390x.ACELFBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDLFBR", argLen: 1, clobberFlags: true, asm: s390x.ACDLFBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CELGBR", argLen: 1, clobberFlags: true, asm: s390x.ACELGBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDLGBR", argLen: 1, clobberFlags: true, asm: s390x.ACDLGBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LEDBR", argLen: 1, asm: s390x.ALEDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LDEBR", argLen: 1, asm: s390x.ALDEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {0, 4295000064}, // SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDaddridx", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {0, 4295000064}, // SP SB {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWBR", argLen: 1, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDBR", argLen: 1, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHBRstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWBRstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDBRstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MVC", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, symEffect: SymNone, asm: s390x.AMVC, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVBZloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHZloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHBRloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWBRloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDBRloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHBRstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWBRstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDBRstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "MOVHstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "MOVDstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "CLEAR", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ACLEAR, reg: regInfo{ inputs: []inputInfo{ {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4096}, // R12 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4096}, // R12 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 outputs: []outputInfo{ {0, 512}, // R9 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT", argLen: 0, reg: regInfo{}, }, { name: "FlagOV", argLen: 0, reg: regInfo{}, }, { name: "SYNC", argLen: 1, asm: s390x.ASYNC, reg: regInfo{}, }, { name: "MOVBZatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBatomicstore", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWatomicstore", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDatomicstore", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LAA", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ALAA, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LAAG", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ALAAG, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "AddTupleFirst32", argLen: 2, reg: regInfo{}, }, { name: "AddTupleFirst64", argLen: 2, reg: regInfo{}, }, { name: "LAN", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAN, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LANfloor", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAN, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 2, // R1 }, }, { name: "LAO", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAO, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LAOfloor", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAO, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 2, // R1 }, }, { name: "LoweredAtomicCas32", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACS, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // R0 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 1, // R0 outputs: []outputInfo{ {1, 0}, {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredAtomicCas64", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACSG, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // R0 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 1, // R0 outputs: []outputInfo{ {1, 0}, {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredAtomicExchange32", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACS, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {1, 0}, {0, 1}, // R0 }, }, }, { name: "LoweredAtomicExchange64", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACSG, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {1, 0}, {0, 1}, // R0 }, }, }, { name: "FLOGR", argLen: 1, clobberFlags: true, asm: s390x.AFLOGR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, clobbers: 2, // R1 outputs: []outputInfo{ {0, 1}, // R0 }, }, }, { name: "POPCNT", argLen: 1, clobberFlags: true, asm: s390x.APOPCNT, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MLGR", argLen: 2, asm: s390x.AMLGR, reg: regInfo{ inputs: []inputInfo{ {1, 8}, // R3 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "SumBytes2", argLen: 1, reg: regInfo{}, }, { name: "SumBytes4", argLen: 1, reg: regInfo{}, }, { name: "SumBytes8", argLen: 1, reg: regInfo{}, }, { name: "STMG2", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMG, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STMG3", auxType: auxSymOff, argLen: 5, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMG, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STMG4", auxType: auxSymOff, argLen: 6, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMG, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {4, 16}, // R4 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STM2", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMY, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STM3", auxType: auxSymOff, argLen: 5, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMY, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STM4", auxType: auxSymOff, argLen: 6, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMY, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {4, 16}, // R4 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 6, // R1 R2 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 2, // R1 }, }, { name: "LoweredStaticCall", auxType: auxCallOff, argLen: 1, call: true, reg: regInfo{ clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredTailCall", auxType: auxCallOff, argLen: 1, call: true, tailCall: true, reg: regInfo{ clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredClosureCall", auxType: auxCallOff, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredInterCall", auxType: auxCallOff, argLen: 2, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredAddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 3, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, reg: regInfo{ clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredConvert", argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "Select", argLen: 3, asm: wasm.ASelect, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load8U", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load8U, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load8S", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load8S, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load16U", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load16U, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load16S", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load16S, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load32U", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load32U, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load32S", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load32S, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Store8", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store8, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Store16", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store16, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Store32", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store32, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Store", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "F32Load", auxType: auxInt64, argLen: 2, asm: wasm.AF32Load, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Load", auxType: auxInt64, argLen: 2, asm: wasm.AF64Load, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F32Store", auxType: auxInt64, argLen: 3, asm: wasm.AF32Store, reg: regInfo{ inputs: []inputInfo{ {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "F64Store", auxType: auxInt64, argLen: 3, asm: wasm.AF64Store, reg: regInfo{ inputs: []inputInfo{ {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Const", auxType: auxInt64, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Const", auxType: auxFloat32, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Const", auxType: auxFloat64, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64Eqz", argLen: 1, asm: wasm.AI64Eqz, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Eq", argLen: 2, asm: wasm.AI64Eq, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Ne", argLen: 2, asm: wasm.AI64Ne, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LtS", argLen: 2, asm: wasm.AI64LtS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LtU", argLen: 2, asm: wasm.AI64LtU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GtS", argLen: 2, asm: wasm.AI64GtS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GtU", argLen: 2, asm: wasm.AI64GtU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LeS", argLen: 2, asm: wasm.AI64LeS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LeU", argLen: 2, asm: wasm.AI64LeU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GeS", argLen: 2, asm: wasm.AI64GeS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GeU", argLen: 2, asm: wasm.AI64GeU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Eq", argLen: 2, asm: wasm.AF32Eq, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Ne", argLen: 2, asm: wasm.AF32Ne, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Lt", argLen: 2, asm: wasm.AF32Lt, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Gt", argLen: 2, asm: wasm.AF32Gt, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Le", argLen: 2, asm: wasm.AF32Le, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Ge", argLen: 2, asm: wasm.AF32Ge, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Eq", argLen: 2, asm: wasm.AF64Eq, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Ne", argLen: 2, asm: wasm.AF64Ne, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Lt", argLen: 2, asm: wasm.AF64Lt, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Gt", argLen: 2, asm: wasm.AF64Gt, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Le", argLen: 2, asm: wasm.AF64Le, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Ge", argLen: 2, asm: wasm.AF64Ge, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Add", argLen: 2, asm: wasm.AI64Add, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64AddConst", auxType: auxInt64, argLen: 1, asm: wasm.AI64Add, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Sub", argLen: 2, asm: wasm.AI64Sub, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Mul", argLen: 2, asm: wasm.AI64Mul, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64DivS", argLen: 2, asm: wasm.AI64DivS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64DivU", argLen: 2, asm: wasm.AI64DivU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64RemS", argLen: 2, asm: wasm.AI64RemS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64RemU", argLen: 2, asm: wasm.AI64RemU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64And", argLen: 2, asm: wasm.AI64And, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Or", argLen: 2, asm: wasm.AI64Or, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Xor", argLen: 2, asm: wasm.AI64Xor, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Shl", argLen: 2, asm: wasm.AI64Shl, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64ShrS", argLen: 2, asm: wasm.AI64ShrS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64ShrU", argLen: 2, asm: wasm.AI64ShrU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Neg", argLen: 1, asm: wasm.AF32Neg, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Add", argLen: 2, asm: wasm.AF32Add, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Sub", argLen: 2, asm: wasm.AF32Sub, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Mul", argLen: 2, asm: wasm.AF32Mul, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Div", argLen: 2, asm: wasm.AF32Div, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Neg", argLen: 1, asm: wasm.AF64Neg, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Add", argLen: 2, asm: wasm.AF64Add, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Sub", argLen: 2, asm: wasm.AF64Sub, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Mul", argLen: 2, asm: wasm.AF64Mul, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Div", argLen: 2, asm: wasm.AF64Div, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64TruncSatF64S", argLen: 1, asm: wasm.AI64TruncSatF64S, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64TruncSatF64U", argLen: 1, asm: wasm.AI64TruncSatF64U, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64TruncSatF32S", argLen: 1, asm: wasm.AI64TruncSatF32S, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64TruncSatF32U", argLen: 1, asm: wasm.AI64TruncSatF32U, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32ConvertI64S", argLen: 1, asm: wasm.AF32ConvertI64S, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32ConvertI64U", argLen: 1, asm: wasm.AF32ConvertI64U, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64ConvertI64S", argLen: 1, asm: wasm.AF64ConvertI64S, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64ConvertI64U", argLen: 1, asm: wasm.AF64ConvertI64U, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F32DemoteF64", argLen: 1, asm: wasm.AF32DemoteF64, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64PromoteF32", argLen: 1, asm: wasm.AF64PromoteF32, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64Extend8S", argLen: 1, asm: wasm.AI64Extend8S, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Extend16S", argLen: 1, asm: wasm.AI64Extend16S, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Extend32S", argLen: 1, asm: wasm.AI64Extend32S, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Sqrt", argLen: 1, asm: wasm.AF32Sqrt, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Trunc", argLen: 1, asm: wasm.AF32Trunc, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Ceil", argLen: 1, asm: wasm.AF32Ceil, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Floor", argLen: 1, asm: wasm.AF32Floor, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Nearest", argLen: 1, asm: wasm.AF32Nearest, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Abs", argLen: 1, asm: wasm.AF32Abs, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Copysign", argLen: 2, asm: wasm.AF32Copysign, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Sqrt", argLen: 1, asm: wasm.AF64Sqrt, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Trunc", argLen: 1, asm: wasm.AF64Trunc, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Ceil", argLen: 1, asm: wasm.AF64Ceil, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Floor", argLen: 1, asm: wasm.AF64Floor, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Nearest", argLen: 1, asm: wasm.AF64Nearest, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Abs", argLen: 1, asm: wasm.AF64Abs, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Copysign", argLen: 2, asm: wasm.AF64Copysign, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64Ctz", argLen: 1, asm: wasm.AI64Ctz, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Clz", argLen: 1, asm: wasm.AI64Clz, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I32Rotl", argLen: 2, asm: wasm.AI32Rotl, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Rotl", argLen: 2, asm: wasm.AI64Rotl, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Popcnt", argLen: 1, asm: wasm.AI64Popcnt, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "Add8", argLen: 2, commutative: true, generic: true, }, { name: "Add16", argLen: 2, commutative: true, generic: true, }, { name: "Add32", argLen: 2, commutative: true, generic: true, }, { name: "Add64", argLen: 2, commutative: true, generic: true, }, { name: "AddPtr", argLen: 2, generic: true, }, { name: "Add32F", argLen: 2, commutative: true, generic: true, }, { name: "Add64F", argLen: 2, commutative: true, generic: true, }, { name: "Sub8", argLen: 2, generic: true, }, { name: "Sub16", argLen: 2, generic: true, }, { name: "Sub32", argLen: 2, generic: true, }, { name: "Sub64", argLen: 2, generic: true, }, { name: "SubPtr", argLen: 2, generic: true, }, { name: "Sub32F", argLen: 2, generic: true, }, { name: "Sub64F", argLen: 2, generic: true, }, { name: "Mul8", argLen: 2, commutative: true, generic: true, }, { name: "Mul16", argLen: 2, commutative: true, generic: true, }, { name: "Mul32", argLen: 2, commutative: true, generic: true, }, { name: "Mul64", argLen: 2, commutative: true, generic: true, }, { name: "Mul32F", argLen: 2, commutative: true, generic: true, }, { name: "Mul64F", argLen: 2, commutative: true, generic: true, }, { name: "Div32F", argLen: 2, generic: true, }, { name: "Div64F", argLen: 2, generic: true, }, { name: "Hmul32", argLen: 2, commutative: true, generic: true, }, { name: "Hmul32u", argLen: 2, commutative: true, generic: true, }, { name: "Hmul64", argLen: 2, commutative: true, generic: true, }, { name: "Hmul64u", argLen: 2, commutative: true, generic: true, }, { name: "Mul32uhilo", argLen: 2, commutative: true, generic: true, }, { name: "Mul64uhilo", argLen: 2, commutative: true, generic: true, }, { name: "Mul32uover", argLen: 2, commutative: true, generic: true, }, { name: "Mul64uover", argLen: 2, commutative: true, generic: true, }, { name: "Avg32u", argLen: 2, generic: true, }, { name: "Avg64u", argLen: 2, generic: true, }, { name: "Div8", argLen: 2, generic: true, }, { name: "Div8u", argLen: 2, generic: true, }, { name: "Div16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Div16u", argLen: 2, generic: true, }, { name: "Div32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Div32u", argLen: 2, generic: true, }, { name: "Div64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Div64u", argLen: 2, generic: true, }, { name: "Div128u", argLen: 3, generic: true, }, { name: "Mod8", argLen: 2, generic: true, }, { name: "Mod8u", argLen: 2, generic: true, }, { name: "Mod16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Mod16u", argLen: 2, generic: true, }, { name: "Mod32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Mod32u", argLen: 2, generic: true, }, { name: "Mod64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Mod64u", argLen: 2, generic: true, }, { name: "And8", argLen: 2, commutative: true, generic: true, }, { name: "And16", argLen: 2, commutative: true, generic: true, }, { name: "And32", argLen: 2, commutative: true, generic: true, }, { name: "And64", argLen: 2, commutative: true, generic: true, }, { name: "Or8", argLen: 2, commutative: true, generic: true, }, { name: "Or16", argLen: 2, commutative: true, generic: true, }, { name: "Or32", argLen: 2, commutative: true, generic: true, }, { name: "Or64", argLen: 2, commutative: true, generic: true, }, { name: "Xor8", argLen: 2, commutative: true, generic: true, }, { name: "Xor16", argLen: 2, commutative: true, generic: true, }, { name: "Xor32", argLen: 2, commutative: true, generic: true, }, { name: "Xor64", argLen: 2, commutative: true, generic: true, }, { name: "Lsh8x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh8x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh8x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh8x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Eq8", argLen: 2, commutative: true, generic: true, }, { name: "Eq16", argLen: 2, commutative: true, generic: true, }, { name: "Eq32", argLen: 2, commutative: true, generic: true, }, { name: "Eq64", argLen: 2, commutative: true, generic: true, }, { name: "EqPtr", argLen: 2, commutative: true, generic: true, }, { name: "EqInter", argLen: 2, generic: true, }, { name: "EqSlice", argLen: 2, generic: true, }, { name: "Eq32F", argLen: 2, commutative: true, generic: true, }, { name: "Eq64F", argLen: 2, commutative: true, generic: true, }, { name: "Neq8", argLen: 2, commutative: true, generic: true, }, { name: "Neq16", argLen: 2, commutative: true, generic: true, }, { name: "Neq32", argLen: 2, commutative: true, generic: true, }, { name: "Neq64", argLen: 2, commutative: true, generic: true, }, { name: "NeqPtr", argLen: 2, commutative: true, generic: true, }, { name: "NeqInter", argLen: 2, generic: true, }, { name: "NeqSlice", argLen: 2, generic: true, }, { name: "Neq32F", argLen: 2, commutative: true, generic: true, }, { name: "Neq64F", argLen: 2, commutative: true, generic: true, }, { name: "Less8", argLen: 2, generic: true, }, { name: "Less8U", argLen: 2, generic: true, }, { name: "Less16", argLen: 2, generic: true, }, { name: "Less16U", argLen: 2, generic: true, }, { name: "Less32", argLen: 2, generic: true, }, { name: "Less32U", argLen: 2, generic: true, }, { name: "Less64", argLen: 2, generic: true, }, { name: "Less64U", argLen: 2, generic: true, }, { name: "Less32F", argLen: 2, generic: true, }, { name: "Less64F", argLen: 2, generic: true, }, { name: "Leq8", argLen: 2, generic: true, }, { name: "Leq8U", argLen: 2, generic: true, }, { name: "Leq16", argLen: 2, generic: true, }, { name: "Leq16U", argLen: 2, generic: true, }, { name: "Leq32", argLen: 2, generic: true, }, { name: "Leq32U", argLen: 2, generic: true, }, { name: "Leq64", argLen: 2, generic: true, }, { name: "Leq64U", argLen: 2, generic: true, }, { name: "Leq32F", argLen: 2, generic: true, }, { name: "Leq64F", argLen: 2, generic: true, }, { name: "CondSelect", argLen: 3, generic: true, }, { name: "AndB", argLen: 2, commutative: true, generic: true, }, { name: "OrB", argLen: 2, commutative: true, generic: true, }, { name: "EqB", argLen: 2, commutative: true, generic: true, }, { name: "NeqB", argLen: 2, commutative: true, generic: true, }, { name: "Not", argLen: 1, generic: true, }, { name: "Neg8", argLen: 1, generic: true, }, { name: "Neg16", argLen: 1, generic: true, }, { name: "Neg32", argLen: 1, generic: true, }, { name: "Neg64", argLen: 1, generic: true, }, { name: "Neg32F", argLen: 1, generic: true, }, { name: "Neg64F", argLen: 1, generic: true, }, { name: "Com8", argLen: 1, generic: true, }, { name: "Com16", argLen: 1, generic: true, }, { name: "Com32", argLen: 1, generic: true, }, { name: "Com64", argLen: 1, generic: true, }, { name: "Ctz8", argLen: 1, generic: true, }, { name: "Ctz16", argLen: 1, generic: true, }, { name: "Ctz32", argLen: 1, generic: true, }, { name: "Ctz64", argLen: 1, generic: true, }, { name: "Ctz64On32", argLen: 2, generic: true, }, { name: "Ctz8NonZero", argLen: 1, generic: true, }, { name: "Ctz16NonZero", argLen: 1, generic: true, }, { name: "Ctz32NonZero", argLen: 1, generic: true, }, { name: "Ctz64NonZero", argLen: 1, generic: true, }, { name: "BitLen8", argLen: 1, generic: true, }, { name: "BitLen16", argLen: 1, generic: true, }, { name: "BitLen32", argLen: 1, generic: true, }, { name: "BitLen64", argLen: 1, generic: true, }, { name: "Bswap16", argLen: 1, generic: true, }, { name: "Bswap32", argLen: 1, generic: true, }, { name: "Bswap64", argLen: 1, generic: true, }, { name: "BitRev8", argLen: 1, generic: true, }, { name: "BitRev16", argLen: 1, generic: true, }, { name: "BitRev32", argLen: 1, generic: true, }, { name: "BitRev64", argLen: 1, generic: true, }, { name: "PopCount8", argLen: 1, generic: true, }, { name: "PopCount16", argLen: 1, generic: true, }, { name: "PopCount32", argLen: 1, generic: true, }, { name: "PopCount64", argLen: 1, generic: true, }, { name: "RotateLeft64", argLen: 2, generic: true, }, { name: "RotateLeft32", argLen: 2, generic: true, }, { name: "RotateLeft16", argLen: 2, generic: true, }, { name: "RotateLeft8", argLen: 2, generic: true, }, { name: "Sqrt", argLen: 1, generic: true, }, { name: "Sqrt32", argLen: 1, generic: true, }, { name: "Floor", argLen: 1, generic: true, }, { name: "Ceil", argLen: 1, generic: true, }, { name: "Trunc", argLen: 1, generic: true, }, { name: "Round", argLen: 1, generic: true, }, { name: "RoundToEven", argLen: 1, generic: true, }, { name: "Abs", argLen: 1, generic: true, }, { name: "Copysign", argLen: 2, generic: true, }, { name: "Min64", argLen: 2, generic: true, }, { name: "Max64", argLen: 2, generic: true, }, { name: "Min64u", argLen: 2, generic: true, }, { name: "Max64u", argLen: 2, generic: true, }, { name: "Min64F", argLen: 2, generic: true, }, { name: "Min32F", argLen: 2, generic: true, }, { name: "Max64F", argLen: 2, generic: true, }, { name: "Max32F", argLen: 2, generic: true, }, { name: "FMA", argLen: 3, generic: true, }, { name: "Phi", argLen: -1, zeroWidth: true, generic: true, }, { name: "Copy", argLen: 1, generic: true, }, { name: "Convert", argLen: 2, resultInArg0: true, zeroWidth: true, generic: true, }, { name: "ConstBool", auxType: auxBool, argLen: 0, generic: true, }, { name: "ConstString", auxType: auxString, argLen: 0, generic: true, }, { name: "ConstNil", argLen: 0, generic: true, }, { name: "Const8", auxType: auxInt8, argLen: 0, generic: true, }, { name: "Const16", auxType: auxInt16, argLen: 0, generic: true, }, { name: "Const32", auxType: auxInt32, argLen: 0, generic: true, }, { name: "Const64", auxType: auxInt64, argLen: 0, generic: true, }, { name: "Const32F", auxType: auxFloat32, argLen: 0, generic: true, }, { name: "Const64F", auxType: auxFloat64, argLen: 0, generic: true, }, { name: "ConstInterface", argLen: 0, generic: true, }, { name: "ConstSlice", argLen: 0, generic: true, }, { name: "InitMem", argLen: 0, zeroWidth: true, generic: true, }, { name: "Arg", auxType: auxSymOff, argLen: 0, zeroWidth: true, symEffect: SymRead, generic: true, }, { name: "ArgIntReg", auxType: auxNameOffsetInt8, argLen: 0, zeroWidth: true, generic: true, }, { name: "ArgFloatReg", auxType: auxNameOffsetInt8, argLen: 0, zeroWidth: true, generic: true, }, { name: "Addr", auxType: auxSym, argLen: 1, symEffect: SymAddr, generic: true, }, { name: "LocalAddr", auxType: auxSym, argLen: 2, symEffect: SymAddr, generic: true, }, { name: "SP", argLen: 0, zeroWidth: true, fixedReg: true, generic: true, }, { name: "SB", argLen: 0, zeroWidth: true, fixedReg: true, generic: true, }, { name: "SPanchored", argLen: 2, zeroWidth: true, generic: true, }, { name: "Load", argLen: 2, generic: true, }, { name: "Dereference", argLen: 2, generic: true, }, { name: "Store", auxType: auxTyp, argLen: 3, generic: true, }, { name: "Move", auxType: auxTypSize, argLen: 3, generic: true, }, { name: "Zero", auxType: auxTypSize, argLen: 2, generic: true, }, { name: "StoreWB", auxType: auxTyp, argLen: 3, generic: true, }, { name: "MoveWB", auxType: auxTypSize, argLen: 3, generic: true, }, { name: "ZeroWB", auxType: auxTypSize, argLen: 2, generic: true, }, { name: "WBend", argLen: 1, generic: true, }, { name: "WB", auxType: auxInt64, argLen: 1, generic: true, }, { name: "HasCPUFeature", auxType: auxSym, argLen: 0, symEffect: SymNone, generic: true, }, { name: "PanicBounds", auxType: auxInt64, argLen: 3, call: true, generic: true, }, { name: "PanicExtend", auxType: auxInt64, argLen: 4, call: true, generic: true, }, { name: "ClosureCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "StaticCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "InterCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "TailCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "ClosureLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "StaticLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "InterLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "TailLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "SignExt8to16", argLen: 1, generic: true, }, { name: "SignExt8to32", argLen: 1, generic: true, }, { name: "SignExt8to64", argLen: 1, generic: true, }, { name: "SignExt16to32", argLen: 1, generic: true, }, { name: "SignExt16to64", argLen: 1, generic: true, }, { name: "SignExt32to64", argLen: 1, generic: true, }, { name: "ZeroExt8to16", argLen: 1, generic: true, }, { name: "ZeroExt8to32", argLen: 1, generic: true, }, { name: "ZeroExt8to64", argLen: 1, generic: true, }, { name: "ZeroExt16to32", argLen: 1, generic: true, }, { name: "ZeroExt16to64", argLen: 1, generic: true, }, { name: "ZeroExt32to64", argLen: 1, generic: true, }, { name: "Trunc16to8", argLen: 1, generic: true, }, { name: "Trunc32to8", argLen: 1, generic: true, }, { name: "Trunc32to16", argLen: 1, generic: true, }, { name: "Trunc64to8", argLen: 1, generic: true, }, { name: "Trunc64to16", argLen: 1, generic: true, }, { name: "Trunc64to32", argLen: 1, generic: true, }, { name: "Cvt32to32F", argLen: 1, generic: true, }, { name: "Cvt32to64F", argLen: 1, generic: true, }, { name: "Cvt64to32F", argLen: 1, generic: true, }, { name: "Cvt64to64F", argLen: 1, generic: true, }, { name: "Cvt32Fto32", argLen: 1, generic: true, }, { name: "Cvt32Fto64", argLen: 1, generic: true, }, { name: "Cvt64Fto32", argLen: 1, generic: true, }, { name: "Cvt64Fto64", argLen: 1, generic: true, }, { name: "Cvt32Fto64F", argLen: 1, generic: true, }, { name: "Cvt64Fto32F", argLen: 1, generic: true, }, { name: "CvtBoolToUint8", argLen: 1, generic: true, }, { name: "Round32F", argLen: 1, generic: true, }, { name: "Round64F", argLen: 1, generic: true, }, { name: "IsNonNil", argLen: 1, generic: true, }, { name: "IsInBounds", argLen: 2, generic: true, }, { name: "IsSliceInBounds", argLen: 2, generic: true, }, { name: "NilCheck", argLen: 2, nilCheck: true, generic: true, }, { name: "GetG", argLen: 1, zeroWidth: true, generic: true, }, { name: "GetClosurePtr", argLen: 0, generic: true, }, { name: "GetCallerPC", argLen: 0, generic: true, }, { name: "GetCallerSP", argLen: 1, generic: true, }, { name: "PtrIndex", argLen: 2, generic: true, }, { name: "OffPtr", auxType: auxInt64, argLen: 1, generic: true, }, { name: "SliceMake", argLen: 3, generic: true, }, { name: "SlicePtr", argLen: 1, generic: true, }, { name: "SliceLen", argLen: 1, generic: true, }, { name: "SliceCap", argLen: 1, generic: true, }, { name: "SlicePtrUnchecked", argLen: 1, generic: true, }, { name: "ComplexMake", argLen: 2, generic: true, }, { name: "ComplexReal", argLen: 1, generic: true, }, { name: "ComplexImag", argLen: 1, generic: true, }, { name: "StringMake", argLen: 2, generic: true, }, { name: "StringPtr", argLen: 1, generic: true, }, { name: "StringLen", argLen: 1, generic: true, }, { name: "IMake", argLen: 2, generic: true, }, { name: "ITab", argLen: 1, generic: true, }, { name: "IData", argLen: 1, generic: true, }, { name: "StructMake", argLen: -1, generic: true, }, { name: "StructSelect", auxType: auxInt64, argLen: 1, generic: true, }, { name: "ArrayMake0", argLen: 0, generic: true, }, { name: "ArrayMake1", argLen: 1, generic: true, }, { name: "ArraySelect", auxType: auxInt64, argLen: 1, generic: true, }, { name: "StoreReg", argLen: 1, generic: true, }, { name: "LoadReg", argLen: 1, generic: true, }, { name: "FwdRef", auxType: auxSym, argLen: 0, symEffect: SymNone, generic: true, }, { name: "Unknown", argLen: 0, generic: true, }, { name: "VarDef", auxType: auxSym, argLen: 1, zeroWidth: true, symEffect: SymNone, generic: true, }, { name: "VarLive", auxType: auxSym, argLen: 1, zeroWidth: true, symEffect: SymRead, generic: true, }, { name: "KeepAlive", argLen: 2, zeroWidth: true, generic: true, }, { name: "InlMark", auxType: auxInt32, argLen: 1, generic: true, }, { name: "Int64Make", argLen: 2, generic: true, }, { name: "Int64Hi", argLen: 1, generic: true, }, { name: "Int64Lo", argLen: 1, generic: true, }, { name: "Add32carry", argLen: 2, commutative: true, generic: true, }, { name: "Add32withcarry", argLen: 3, commutative: true, generic: true, }, { name: "Sub32carry", argLen: 2, generic: true, }, { name: "Sub32withcarry", argLen: 3, generic: true, }, { name: "Add64carry", argLen: 3, commutative: true, generic: true, }, { name: "Sub64borrow", argLen: 3, generic: true, }, { name: "Signmask", argLen: 1, generic: true, }, { name: "Zeromask", argLen: 1, generic: true, }, { name: "Slicemask", argLen: 1, generic: true, }, { name: "SpectreIndex", argLen: 2, generic: true, }, { name: "SpectreSliceIndex", argLen: 2, generic: true, }, { name: "Cvt32Uto32F", argLen: 1, generic: true, }, { name: "Cvt32Uto64F", argLen: 1, generic: true, }, { name: "Cvt32Fto32U", argLen: 1, generic: true, }, { name: "Cvt64Fto32U", argLen: 1, generic: true, }, { name: "Cvt64Uto32F", argLen: 1, generic: true, }, { name: "Cvt64Uto64F", argLen: 1, generic: true, }, { name: "Cvt32Fto64U", argLen: 1, generic: true, }, { name: "Cvt64Fto64U", argLen: 1, generic: true, }, { name: "Select0", argLen: 1, zeroWidth: true, generic: true, }, { name: "Select1", argLen: 1, zeroWidth: true, generic: true, }, { name: "MakeTuple", argLen: 2, generic: true, }, { name: "SelectN", auxType: auxInt64, argLen: 1, generic: true, }, { name: "SelectNAddr", auxType: auxInt64, argLen: 1, generic: true, }, { name: "MakeResult", argLen: -1, generic: true, }, { name: "AtomicLoad8", argLen: 2, generic: true, }, { name: "AtomicLoad32", argLen: 2, generic: true, }, { name: "AtomicLoad64", argLen: 2, generic: true, }, { name: "AtomicLoadPtr", argLen: 2, generic: true, }, { name: "AtomicLoadAcq32", argLen: 2, generic: true, }, { name: "AtomicLoadAcq64", argLen: 2, generic: true, }, { name: "AtomicStore8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStorePtrNoWB", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStoreRel32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStoreRel64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap32", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap64", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwapRel32", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicAnd8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd64value", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd32value", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd8value", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr64value", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr32value", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr8value", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore8Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore64Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd64Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange8Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange64Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap32Variant", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap64Variant", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicAnd64valueVariant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr64valueVariant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd32valueVariant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr32valueVariant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd8valueVariant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr8valueVariant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "PubBarrier", argLen: 1, hasSideEffects: true, generic: true, }, { name: "Clobber", auxType: auxSymOff, argLen: 0, symEffect: SymNone, generic: true, }, { name: "ClobberReg", argLen: 0, generic: true, }, { name: "PrefetchCache", argLen: 2, hasSideEffects: true, generic: true, }, { name: "PrefetchCacheStreamed", argLen: 2, hasSideEffects: true, generic: true, }, } func (o Op) Asm() obj.As { return opcodeTable[o].asm } func (o Op) Scale() int16 { return int16(opcodeTable[o].scale) } func (o Op) String() string { return opcodeTable[o].name } func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } func (o Op) IsCall() bool { return opcodeTable[o].call } func (o Op) IsTailCall() bool { return opcodeTable[o].tailCall } func (o Op) HasSideEffects() bool { return opcodeTable[o].hasSideEffects } func (o Op) UnsafePoint() bool { return opcodeTable[o].unsafePoint } func (o Op) ResultInArg0() bool { return opcodeTable[o].resultInArg0 } var registers386 = [...]Register{ {0, x86.REG_AX, "AX"}, {1, x86.REG_CX, "CX"}, {2, x86.REG_DX, "DX"}, {3, x86.REG_BX, "BX"}, {4, x86.REGSP, "SP"}, {5, x86.REG_BP, "BP"}, {6, x86.REG_SI, "SI"}, {7, x86.REG_DI, "DI"}, {8, x86.REG_X0, "X0"}, {9, x86.REG_X1, "X1"}, {10, x86.REG_X2, "X2"}, {11, x86.REG_X3, "X3"}, {12, x86.REG_X4, "X4"}, {13, x86.REG_X5, "X5"}, {14, x86.REG_X6, "X6"}, {15, x86.REG_X7, "X7"}, {16, 0, "SB"}, } var paramIntReg386 = []int8(nil) var paramFloatReg386 = []int8(nil) var gpRegMask386 = regMask(239) var fpRegMask386 = regMask(65280) var specialRegMask386 = regMask(0) var framepointerReg386 = int8(5) var linkReg386 = int8(-1) var registersAMD64 = [...]Register{ {0, x86.REG_AX, "AX"}, {1, x86.REG_CX, "CX"}, {2, x86.REG_DX, "DX"}, {3, x86.REG_BX, "BX"}, {4, x86.REGSP, "SP"}, {5, x86.REG_BP, "BP"}, {6, x86.REG_SI, "SI"}, {7, x86.REG_DI, "DI"}, {8, x86.REG_R8, "R8"}, {9, x86.REG_R9, "R9"}, {10, x86.REG_R10, "R10"}, {11, x86.REG_R11, "R11"}, {12, x86.REG_R12, "R12"}, {13, x86.REG_R13, "R13"}, {14, x86.REGG, "g"}, {15, x86.REG_R15, "R15"}, {16, x86.REG_X0, "X0"}, {17, x86.REG_X1, "X1"}, {18, x86.REG_X2, "X2"}, {19, x86.REG_X3, "X3"}, {20, x86.REG_X4, "X4"}, {21, x86.REG_X5, "X5"}, {22, x86.REG_X6, "X6"}, {23, x86.REG_X7, "X7"}, {24, x86.REG_X8, "X8"}, {25, x86.REG_X9, "X9"}, {26, x86.REG_X10, "X10"}, {27, x86.REG_X11, "X11"}, {28, x86.REG_X12, "X12"}, {29, x86.REG_X13, "X13"}, {30, x86.REG_X14, "X14"}, {31, x86.REG_X15, "X15"}, {32, 0, "SB"}, } var paramIntRegAMD64 = []int8{0, 3, 1, 7, 6, 8, 9, 10, 11} var paramFloatRegAMD64 = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30} var gpRegMaskAMD64 = regMask(49135) var fpRegMaskAMD64 = regMask(2147418112) var specialRegMaskAMD64 = regMask(2147483648) var framepointerRegAMD64 = int8(5) var linkRegAMD64 = int8(-1) var registersARM = [...]Register{ {0, arm.REG_R0, "R0"}, {1, arm.REG_R1, "R1"}, {2, arm.REG_R2, "R2"}, {3, arm.REG_R3, "R3"}, {4, arm.REG_R4, "R4"}, {5, arm.REG_R5, "R5"}, {6, arm.REG_R6, "R6"}, {7, arm.REG_R7, "R7"}, {8, arm.REG_R8, "R8"}, {9, arm.REG_R9, "R9"}, {10, arm.REGG, "g"}, {11, arm.REG_R11, "R11"}, {12, arm.REG_R12, "R12"}, {13, arm.REGSP, "SP"}, {14, arm.REG_R14, "R14"}, {15, arm.REG_R15, "R15"}, {16, arm.REG_F0, "F0"}, {17, arm.REG_F1, "F1"}, {18, arm.REG_F2, "F2"}, {19, arm.REG_F3, "F3"}, {20, arm.REG_F4, "F4"}, {21, arm.REG_F5, "F5"}, {22, arm.REG_F6, "F6"}, {23, arm.REG_F7, "F7"}, {24, arm.REG_F8, "F8"}, {25, arm.REG_F9, "F9"}, {26, arm.REG_F10, "F10"}, {27, arm.REG_F11, "F11"}, {28, arm.REG_F12, "F12"}, {29, arm.REG_F13, "F13"}, {30, arm.REG_F14, "F14"}, {31, arm.REG_F15, "F15"}, {32, 0, "SB"}, } var paramIntRegARM = []int8(nil) var paramFloatRegARM = []int8(nil) var gpRegMaskARM = regMask(21503) var fpRegMaskARM = regMask(4294901760) var specialRegMaskARM = regMask(0) var framepointerRegARM = int8(-1) var linkRegARM = int8(14) var registersARM64 = [...]Register{ {0, arm64.REG_R0, "R0"}, {1, arm64.REG_R1, "R1"}, {2, arm64.REG_R2, "R2"}, {3, arm64.REG_R3, "R3"}, {4, arm64.REG_R4, "R4"}, {5, arm64.REG_R5, "R5"}, {6, arm64.REG_R6, "R6"}, {7, arm64.REG_R7, "R7"}, {8, arm64.REG_R8, "R8"}, {9, arm64.REG_R9, "R9"}, {10, arm64.REG_R10, "R10"}, {11, arm64.REG_R11, "R11"}, {12, arm64.REG_R12, "R12"}, {13, arm64.REG_R13, "R13"}, {14, arm64.REG_R14, "R14"}, {15, arm64.REG_R15, "R15"}, {16, arm64.REG_R16, "R16"}, {17, arm64.REG_R17, "R17"}, {18, arm64.REG_R19, "R19"}, {19, arm64.REG_R20, "R20"}, {20, arm64.REG_R21, "R21"}, {21, arm64.REG_R22, "R22"}, {22, arm64.REG_R23, "R23"}, {23, arm64.REG_R24, "R24"}, {24, arm64.REG_R25, "R25"}, {25, arm64.REG_R26, "R26"}, {26, arm64.REGG, "g"}, {27, arm64.REG_R29, "R29"}, {28, arm64.REG_R30, "R30"}, {29, arm64.REGZERO, "ZERO"}, {30, arm64.REGSP, "SP"}, {31, arm64.REG_F0, "F0"}, {32, arm64.REG_F1, "F1"}, {33, arm64.REG_F2, "F2"}, {34, arm64.REG_F3, "F3"}, {35, arm64.REG_F4, "F4"}, {36, arm64.REG_F5, "F5"}, {37, arm64.REG_F6, "F6"}, {38, arm64.REG_F7, "F7"}, {39, arm64.REG_F8, "F8"}, {40, arm64.REG_F9, "F9"}, {41, arm64.REG_F10, "F10"}, {42, arm64.REG_F11, "F11"}, {43, arm64.REG_F12, "F12"}, {44, arm64.REG_F13, "F13"}, {45, arm64.REG_F14, "F14"}, {46, arm64.REG_F15, "F15"}, {47, arm64.REG_F16, "F16"}, {48, arm64.REG_F17, "F17"}, {49, arm64.REG_F18, "F18"}, {50, arm64.REG_F19, "F19"}, {51, arm64.REG_F20, "F20"}, {52, arm64.REG_F21, "F21"}, {53, arm64.REG_F22, "F22"}, {54, arm64.REG_F23, "F23"}, {55, arm64.REG_F24, "F24"}, {56, arm64.REG_F25, "F25"}, {57, arm64.REG_F26, "F26"}, {58, arm64.REG_F27, "F27"}, {59, arm64.REG_F28, "F28"}, {60, arm64.REG_F29, "F29"}, {61, arm64.REG_F30, "F30"}, {62, arm64.REG_F31, "F31"}, {63, 0, "SB"}, } var paramIntRegARM64 = []int8{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} var paramFloatRegARM64 = []int8{31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46} var gpRegMaskARM64 = regMask(335544319) var fpRegMaskARM64 = regMask(9223372034707292160) var specialRegMaskARM64 = regMask(0) var framepointerRegARM64 = int8(-1) var linkRegARM64 = int8(28) var registersLOONG64 = [...]Register{ {0, loong64.REG_R0, "R0"}, {1, loong64.REG_R1, "R1"}, {2, loong64.REGSP, "SP"}, {3, loong64.REG_R4, "R4"}, {4, loong64.REG_R5, "R5"}, {5, loong64.REG_R6, "R6"}, {6, loong64.REG_R7, "R7"}, {7, loong64.REG_R8, "R8"}, {8, loong64.REG_R9, "R9"}, {9, loong64.REG_R10, "R10"}, {10, loong64.REG_R11, "R11"}, {11, loong64.REG_R12, "R12"}, {12, loong64.REG_R13, "R13"}, {13, loong64.REG_R14, "R14"}, {14, loong64.REG_R15, "R15"}, {15, loong64.REG_R16, "R16"}, {16, loong64.REG_R17, "R17"}, {17, loong64.REG_R18, "R18"}, {18, loong64.REG_R19, "R19"}, {19, loong64.REG_R20, "R20"}, {20, loong64.REG_R21, "R21"}, {21, loong64.REGG, "g"}, {22, loong64.REG_R23, "R23"}, {23, loong64.REG_R24, "R24"}, {24, loong64.REG_R25, "R25"}, {25, loong64.REG_R26, "R26"}, {26, loong64.REG_R27, "R27"}, {27, loong64.REG_R28, "R28"}, {28, loong64.REG_R29, "R29"}, {29, loong64.REG_R31, "R31"}, {30, loong64.REG_F0, "F0"}, {31, loong64.REG_F1, "F1"}, {32, loong64.REG_F2, "F2"}, {33, loong64.REG_F3, "F3"}, {34, loong64.REG_F4, "F4"}, {35, loong64.REG_F5, "F5"}, {36, loong64.REG_F6, "F6"}, {37, loong64.REG_F7, "F7"}, {38, loong64.REG_F8, "F8"}, {39, loong64.REG_F9, "F9"}, {40, loong64.REG_F10, "F10"}, {41, loong64.REG_F11, "F11"}, {42, loong64.REG_F12, "F12"}, {43, loong64.REG_F13, "F13"}, {44, loong64.REG_F14, "F14"}, {45, loong64.REG_F15, "F15"}, {46, loong64.REG_F16, "F16"}, {47, loong64.REG_F17, "F17"}, {48, loong64.REG_F18, "F18"}, {49, loong64.REG_F19, "F19"}, {50, loong64.REG_F20, "F20"}, {51, loong64.REG_F21, "F21"}, {52, loong64.REG_F22, "F22"}, {53, loong64.REG_F23, "F23"}, {54, loong64.REG_F24, "F24"}, {55, loong64.REG_F25, "F25"}, {56, loong64.REG_F26, "F26"}, {57, loong64.REG_F27, "F27"}, {58, loong64.REG_F28, "F28"}, {59, loong64.REG_F29, "F29"}, {60, loong64.REG_F30, "F30"}, {61, loong64.REG_F31, "F31"}, {62, 0, "SB"}, } var paramIntRegLOONG64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18} var paramFloatRegLOONG64 = []int8{30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45} var gpRegMaskLOONG64 = regMask(1071644664) var fpRegMaskLOONG64 = regMask(4611686017353646080) var specialRegMaskLOONG64 = regMask(0) var framepointerRegLOONG64 = int8(-1) var linkRegLOONG64 = int8(1) var registersMIPS = [...]Register{ {0, mips.REG_R0, "R0"}, {1, mips.REG_R1, "R1"}, {2, mips.REG_R2, "R2"}, {3, mips.REG_R3, "R3"}, {4, mips.REG_R4, "R4"}, {5, mips.REG_R5, "R5"}, {6, mips.REG_R6, "R6"}, {7, mips.REG_R7, "R7"}, {8, mips.REG_R8, "R8"}, {9, mips.REG_R9, "R9"}, {10, mips.REG_R10, "R10"}, {11, mips.REG_R11, "R11"}, {12, mips.REG_R12, "R12"}, {13, mips.REG_R13, "R13"}, {14, mips.REG_R14, "R14"}, {15, mips.REG_R15, "R15"}, {16, mips.REG_R16, "R16"}, {17, mips.REG_R17, "R17"}, {18, mips.REG_R18, "R18"}, {19, mips.REG_R19, "R19"}, {20, mips.REG_R20, "R20"}, {21, mips.REG_R21, "R21"}, {22, mips.REG_R22, "R22"}, {23, mips.REG_R24, "R24"}, {24, mips.REG_R25, "R25"}, {25, mips.REG_R28, "R28"}, {26, mips.REGSP, "SP"}, {27, mips.REGG, "g"}, {28, mips.REG_R31, "R31"}, {29, mips.REG_F0, "F0"}, {30, mips.REG_F2, "F2"}, {31, mips.REG_F4, "F4"}, {32, mips.REG_F6, "F6"}, {33, mips.REG_F8, "F8"}, {34, mips.REG_F10, "F10"}, {35, mips.REG_F12, "F12"}, {36, mips.REG_F14, "F14"}, {37, mips.REG_F16, "F16"}, {38, mips.REG_F18, "F18"}, {39, mips.REG_F20, "F20"}, {40, mips.REG_F22, "F22"}, {41, mips.REG_F24, "F24"}, {42, mips.REG_F26, "F26"}, {43, mips.REG_F28, "F28"}, {44, mips.REG_F30, "F30"}, {45, mips.REG_HI, "HI"}, {46, mips.REG_LO, "LO"}, {47, 0, "SB"}, } var paramIntRegMIPS = []int8(nil) var paramFloatRegMIPS = []int8(nil) var gpRegMaskMIPS = regMask(335544318) var fpRegMaskMIPS = regMask(35183835217920) var specialRegMaskMIPS = regMask(105553116266496) var framepointerRegMIPS = int8(-1) var linkRegMIPS = int8(28) var registersMIPS64 = [...]Register{ {0, mips.REG_R0, "R0"}, {1, mips.REG_R1, "R1"}, {2, mips.REG_R2, "R2"}, {3, mips.REG_R3, "R3"}, {4, mips.REG_R4, "R4"}, {5, mips.REG_R5, "R5"}, {6, mips.REG_R6, "R6"}, {7, mips.REG_R7, "R7"}, {8, mips.REG_R8, "R8"}, {9, mips.REG_R9, "R9"}, {10, mips.REG_R10, "R10"}, {11, mips.REG_R11, "R11"}, {12, mips.REG_R12, "R12"}, {13, mips.REG_R13, "R13"}, {14, mips.REG_R14, "R14"}, {15, mips.REG_R15, "R15"}, {16, mips.REG_R16, "R16"}, {17, mips.REG_R17, "R17"}, {18, mips.REG_R18, "R18"}, {19, mips.REG_R19, "R19"}, {20, mips.REG_R20, "R20"}, {21, mips.REG_R21, "R21"}, {22, mips.REG_R22, "R22"}, {23, mips.REG_R24, "R24"}, {24, mips.REG_R25, "R25"}, {25, mips.REGSP, "SP"}, {26, mips.REGG, "g"}, {27, mips.REG_R31, "R31"}, {28, mips.REG_F0, "F0"}, {29, mips.REG_F1, "F1"}, {30, mips.REG_F2, "F2"}, {31, mips.REG_F3, "F3"}, {32, mips.REG_F4, "F4"}, {33, mips.REG_F5, "F5"}, {34, mips.REG_F6, "F6"}, {35, mips.REG_F7, "F7"}, {36, mips.REG_F8, "F8"}, {37, mips.REG_F9, "F9"}, {38, mips.REG_F10, "F10"}, {39, mips.REG_F11, "F11"}, {40, mips.REG_F12, "F12"}, {41, mips.REG_F13, "F13"}, {42, mips.REG_F14, "F14"}, {43, mips.REG_F15, "F15"}, {44, mips.REG_F16, "F16"}, {45, mips.REG_F17, "F17"}, {46, mips.REG_F18, "F18"}, {47, mips.REG_F19, "F19"}, {48, mips.REG_F20, "F20"}, {49, mips.REG_F21, "F21"}, {50, mips.REG_F22, "F22"}, {51, mips.REG_F23, "F23"}, {52, mips.REG_F24, "F24"}, {53, mips.REG_F25, "F25"}, {54, mips.REG_F26, "F26"}, {55, mips.REG_F27, "F27"}, {56, mips.REG_F28, "F28"}, {57, mips.REG_F29, "F29"}, {58, mips.REG_F30, "F30"}, {59, mips.REG_F31, "F31"}, {60, mips.REG_HI, "HI"}, {61, mips.REG_LO, "LO"}, {62, 0, "SB"}, } var paramIntRegMIPS64 = []int8(nil) var paramFloatRegMIPS64 = []int8(nil) var gpRegMaskMIPS64 = regMask(167772158) var fpRegMaskMIPS64 = regMask(1152921504338411520) var specialRegMaskMIPS64 = regMask(3458764513820540928) var framepointerRegMIPS64 = int8(-1) var linkRegMIPS64 = int8(27) var registersPPC64 = [...]Register{ {0, ppc64.REG_R0, "R0"}, {1, ppc64.REGSP, "SP"}, {2, 0, "SB"}, {3, ppc64.REG_R3, "R3"}, {4, ppc64.REG_R4, "R4"}, {5, ppc64.REG_R5, "R5"}, {6, ppc64.REG_R6, "R6"}, {7, ppc64.REG_R7, "R7"}, {8, ppc64.REG_R8, "R8"}, {9, ppc64.REG_R9, "R9"}, {10, ppc64.REG_R10, "R10"}, {11, ppc64.REG_R11, "R11"}, {12, ppc64.REG_R12, "R12"}, {13, ppc64.REG_R13, "R13"}, {14, ppc64.REG_R14, "R14"}, {15, ppc64.REG_R15, "R15"}, {16, ppc64.REG_R16, "R16"}, {17, ppc64.REG_R17, "R17"}, {18, ppc64.REG_R18, "R18"}, {19, ppc64.REG_R19, "R19"}, {20, ppc64.REG_R20, "R20"}, {21, ppc64.REG_R21, "R21"}, {22, ppc64.REG_R22, "R22"}, {23, ppc64.REG_R23, "R23"}, {24, ppc64.REG_R24, "R24"}, {25, ppc64.REG_R25, "R25"}, {26, ppc64.REG_R26, "R26"}, {27, ppc64.REG_R27, "R27"}, {28, ppc64.REG_R28, "R28"}, {29, ppc64.REG_R29, "R29"}, {30, ppc64.REGG, "g"}, {31, ppc64.REG_R31, "R31"}, {32, ppc64.REG_F0, "F0"}, {33, ppc64.REG_F1, "F1"}, {34, ppc64.REG_F2, "F2"}, {35, ppc64.REG_F3, "F3"}, {36, ppc64.REG_F4, "F4"}, {37, ppc64.REG_F5, "F5"}, {38, ppc64.REG_F6, "F6"}, {39, ppc64.REG_F7, "F7"}, {40, ppc64.REG_F8, "F8"}, {41, ppc64.REG_F9, "F9"}, {42, ppc64.REG_F10, "F10"}, {43, ppc64.REG_F11, "F11"}, {44, ppc64.REG_F12, "F12"}, {45, ppc64.REG_F13, "F13"}, {46, ppc64.REG_F14, "F14"}, {47, ppc64.REG_F15, "F15"}, {48, ppc64.REG_F16, "F16"}, {49, ppc64.REG_F17, "F17"}, {50, ppc64.REG_F18, "F18"}, {51, ppc64.REG_F19, "F19"}, {52, ppc64.REG_F20, "F20"}, {53, ppc64.REG_F21, "F21"}, {54, ppc64.REG_F22, "F22"}, {55, ppc64.REG_F23, "F23"}, {56, ppc64.REG_F24, "F24"}, {57, ppc64.REG_F25, "F25"}, {58, ppc64.REG_F26, "F26"}, {59, ppc64.REG_F27, "F27"}, {60, ppc64.REG_F28, "F28"}, {61, ppc64.REG_F29, "F29"}, {62, ppc64.REG_F30, "F30"}, {63, ppc64.REG_XER, "XER"}, } var paramIntRegPPC64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 16, 17} var paramFloatRegPPC64 = []int8{33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44} var gpRegMaskPPC64 = regMask(1073733624) var fpRegMaskPPC64 = regMask(9223372032559808512) var specialRegMaskPPC64 = regMask(9223372036854775808) var framepointerRegPPC64 = int8(-1) var linkRegPPC64 = int8(-1) var registersRISCV64 = [...]Register{ {0, riscv.REG_X0, "X0"}, {1, riscv.REGSP, "SP"}, {2, riscv.REG_X3, "X3"}, {3, riscv.REG_X4, "X4"}, {4, riscv.REG_X5, "X5"}, {5, riscv.REG_X6, "X6"}, {6, riscv.REG_X7, "X7"}, {7, riscv.REG_X8, "X8"}, {8, riscv.REG_X9, "X9"}, {9, riscv.REG_X10, "X10"}, {10, riscv.REG_X11, "X11"}, {11, riscv.REG_X12, "X12"}, {12, riscv.REG_X13, "X13"}, {13, riscv.REG_X14, "X14"}, {14, riscv.REG_X15, "X15"}, {15, riscv.REG_X16, "X16"}, {16, riscv.REG_X17, "X17"}, {17, riscv.REG_X18, "X18"}, {18, riscv.REG_X19, "X19"}, {19, riscv.REG_X20, "X20"}, {20, riscv.REG_X21, "X21"}, {21, riscv.REG_X22, "X22"}, {22, riscv.REG_X23, "X23"}, {23, riscv.REG_X24, "X24"}, {24, riscv.REG_X25, "X25"}, {25, riscv.REG_X26, "X26"}, {26, riscv.REGG, "g"}, {27, riscv.REG_X28, "X28"}, {28, riscv.REG_X29, "X29"}, {29, riscv.REG_X30, "X30"}, {30, riscv.REG_X31, "X31"}, {31, riscv.REG_F0, "F0"}, {32, riscv.REG_F1, "F1"}, {33, riscv.REG_F2, "F2"}, {34, riscv.REG_F3, "F3"}, {35, riscv.REG_F4, "F4"}, {36, riscv.REG_F5, "F5"}, {37, riscv.REG_F6, "F6"}, {38, riscv.REG_F7, "F7"}, {39, riscv.REG_F8, "F8"}, {40, riscv.REG_F9, "F9"}, {41, riscv.REG_F10, "F10"}, {42, riscv.REG_F11, "F11"}, {43, riscv.REG_F12, "F12"}, {44, riscv.REG_F13, "F13"}, {45, riscv.REG_F14, "F14"}, {46, riscv.REG_F15, "F15"}, {47, riscv.REG_F16, "F16"}, {48, riscv.REG_F17, "F17"}, {49, riscv.REG_F18, "F18"}, {50, riscv.REG_F19, "F19"}, {51, riscv.REG_F20, "F20"}, {52, riscv.REG_F21, "F21"}, {53, riscv.REG_F22, "F22"}, {54, riscv.REG_F23, "F23"}, {55, riscv.REG_F24, "F24"}, {56, riscv.REG_F25, "F25"}, {57, riscv.REG_F26, "F26"}, {58, riscv.REG_F27, "F27"}, {59, riscv.REG_F28, "F28"}, {60, riscv.REG_F29, "F29"}, {61, riscv.REG_F30, "F30"}, {62, riscv.REG_F31, "F31"}, {63, 0, "SB"}, } var paramIntRegRISCV64 = []int8{9, 10, 11, 12, 13, 14, 15, 16, 7, 8, 17, 18, 19, 20, 21, 22} var paramFloatRegRISCV64 = []int8{41, 42, 43, 44, 45, 46, 47, 48, 39, 40, 49, 50, 51, 52, 53, 54} var gpRegMaskRISCV64 = regMask(1006632944) var fpRegMaskRISCV64 = regMask(9223372034707292160) var specialRegMaskRISCV64 = regMask(0) var framepointerRegRISCV64 = int8(-1) var linkRegRISCV64 = int8(0) var registersS390X = [...]Register{ {0, s390x.REG_R0, "R0"}, {1, s390x.REG_R1, "R1"}, {2, s390x.REG_R2, "R2"}, {3, s390x.REG_R3, "R3"}, {4, s390x.REG_R4, "R4"}, {5, s390x.REG_R5, "R5"}, {6, s390x.REG_R6, "R6"}, {7, s390x.REG_R7, "R7"}, {8, s390x.REG_R8, "R8"}, {9, s390x.REG_R9, "R9"}, {10, s390x.REG_R10, "R10"}, {11, s390x.REG_R11, "R11"}, {12, s390x.REG_R12, "R12"}, {13, s390x.REGG, "g"}, {14, s390x.REG_R14, "R14"}, {15, s390x.REGSP, "SP"}, {16, s390x.REG_F0, "F0"}, {17, s390x.REG_F1, "F1"}, {18, s390x.REG_F2, "F2"}, {19, s390x.REG_F3, "F3"}, {20, s390x.REG_F4, "F4"}, {21, s390x.REG_F5, "F5"}, {22, s390x.REG_F6, "F6"}, {23, s390x.REG_F7, "F7"}, {24, s390x.REG_F8, "F8"}, {25, s390x.REG_F9, "F9"}, {26, s390x.REG_F10, "F10"}, {27, s390x.REG_F11, "F11"}, {28, s390x.REG_F12, "F12"}, {29, s390x.REG_F13, "F13"}, {30, s390x.REG_F14, "F14"}, {31, s390x.REG_F15, "F15"}, {32, 0, "SB"}, } var paramIntRegS390X = []int8(nil) var paramFloatRegS390X = []int8(nil) var gpRegMaskS390X = regMask(23551) var fpRegMaskS390X = regMask(4294901760) var specialRegMaskS390X = regMask(0) var framepointerRegS390X = int8(-1) var linkRegS390X = int8(14) var registersWasm = [...]Register{ {0, wasm.REG_R0, "R0"}, {1, wasm.REG_R1, "R1"}, {2, wasm.REG_R2, "R2"}, {3, wasm.REG_R3, "R3"}, {4, wasm.REG_R4, "R4"}, {5, wasm.REG_R5, "R5"}, {6, wasm.REG_R6, "R6"}, {7, wasm.REG_R7, "R7"}, {8, wasm.REG_R8, "R8"}, {9, wasm.REG_R9, "R9"}, {10, wasm.REG_R10, "R10"}, {11, wasm.REG_R11, "R11"}, {12, wasm.REG_R12, "R12"}, {13, wasm.REG_R13, "R13"}, {14, wasm.REG_R14, "R14"}, {15, wasm.REG_R15, "R15"}, {16, wasm.REG_F0, "F0"}, {17, wasm.REG_F1, "F1"}, {18, wasm.REG_F2, "F2"}, {19, wasm.REG_F3, "F3"}, {20, wasm.REG_F4, "F4"}, {21, wasm.REG_F5, "F5"}, {22, wasm.REG_F6, "F6"}, {23, wasm.REG_F7, "F7"}, {24, wasm.REG_F8, "F8"}, {25, wasm.REG_F9, "F9"}, {26, wasm.REG_F10, "F10"}, {27, wasm.REG_F11, "F11"}, {28, wasm.REG_F12, "F12"}, {29, wasm.REG_F13, "F13"}, {30, wasm.REG_F14, "F14"}, {31, wasm.REG_F15, "F15"}, {32, wasm.REG_F16, "F16"}, {33, wasm.REG_F17, "F17"}, {34, wasm.REG_F18, "F18"}, {35, wasm.REG_F19, "F19"}, {36, wasm.REG_F20, "F20"}, {37, wasm.REG_F21, "F21"}, {38, wasm.REG_F22, "F22"}, {39, wasm.REG_F23, "F23"}, {40, wasm.REG_F24, "F24"}, {41, wasm.REG_F25, "F25"}, {42, wasm.REG_F26, "F26"}, {43, wasm.REG_F27, "F27"}, {44, wasm.REG_F28, "F28"}, {45, wasm.REG_F29, "F29"}, {46, wasm.REG_F30, "F30"}, {47, wasm.REG_F31, "F31"}, {48, wasm.REGSP, "SP"}, {49, wasm.REGG, "g"}, {50, 0, "SB"}, } var paramIntRegWasm = []int8(nil) var paramFloatRegWasm = []int8(nil) var gpRegMaskWasm = regMask(65535) var fpRegMaskWasm = regMask(281474976645120) var fp32RegMaskWasm = regMask(4294901760) var fp64RegMaskWasm = regMask(281470681743360) var specialRegMaskWasm = regMask(0) var framepointerRegWasm = int8(-1) var linkRegWasm = int8(-1) -- y -- // Code generated from _gen/*Ops.go using 'go generate'; DO NOT EDIT. package ssa import ( "cmd/internal/obj" "cmd/internal/obj/arm" "cmd/internal/obj/arm64" "cmd/internal/obj/loong64" "cmd/internal/obj/mips" "cmd/internal/obj/ppc64" "cmd/internal/obj/riscv" "cmd/internal/obj/s390x" "cmd/internal/obj/wasm" "cmd/internal/obj/x86" ) const ( BlockInvalid BlockKind = iota Block386EQ Block386NE Block386LT Block386LE Block386GT Block386GE Block386OS Block386OC Block386ULT Block386ULE Block386UGT Block386UGE Block386EQF Block386NEF Block386ORD Block386NAN BlockAMD64EQ BlockAMD64NE BlockAMD64LT BlockAMD64LE BlockAMD64GT BlockAMD64GE BlockAMD64OS BlockAMD64OC BlockAMD64ULT BlockAMD64ULE BlockAMD64UGT BlockAMD64UGE BlockAMD64EQF BlockAMD64NEF BlockAMD64ORD BlockAMD64NAN BlockAMD64JUMPTABLE BlockARMEQ BlockARMNE BlockARMLT BlockARMLE BlockARMGT BlockARMGE BlockARMULT BlockARMULE BlockARMUGT BlockARMUGE BlockARMLTnoov BlockARMLEnoov BlockARMGTnoov BlockARMGEnoov BlockARM64EQ BlockARM64NE BlockARM64LT BlockARM64LE BlockARM64GT BlockARM64GE BlockARM64ULT BlockARM64ULE BlockARM64UGT BlockARM64UGE BlockARM64Z BlockARM64NZ BlockARM64ZW BlockARM64NZW BlockARM64TBZ BlockARM64TBNZ BlockARM64FLT BlockARM64FLE BlockARM64FGT BlockARM64FGE BlockARM64LTnoov BlockARM64LEnoov BlockARM64GTnoov BlockARM64GEnoov BlockARM64JUMPTABLE BlockLOONG64EQ BlockLOONG64NE BlockLOONG64LTZ BlockLOONG64LEZ BlockLOONG64GTZ BlockLOONG64GEZ BlockLOONG64FPT BlockLOONG64FPF BlockLOONG64BEQ BlockLOONG64BNE BlockLOONG64BGE BlockLOONG64BLT BlockLOONG64BGEU BlockLOONG64BLTU BlockMIPSEQ BlockMIPSNE BlockMIPSLTZ BlockMIPSLEZ BlockMIPSGTZ BlockMIPSGEZ BlockMIPSFPT BlockMIPSFPF BlockMIPS64EQ BlockMIPS64NE BlockMIPS64LTZ BlockMIPS64LEZ BlockMIPS64GTZ BlockMIPS64GEZ BlockMIPS64FPT BlockMIPS64FPF BlockPPC64EQ BlockPPC64NE BlockPPC64LT BlockPPC64LE BlockPPC64GT BlockPPC64GE BlockPPC64FLT BlockPPC64FLE BlockPPC64FGT BlockPPC64FGE BlockRISCV64BEQ BlockRISCV64BNE BlockRISCV64BLT BlockRISCV64BGE BlockRISCV64BLTU BlockRISCV64BGEU BlockRISCV64BEQZ BlockRISCV64BNEZ BlockRISCV64BLEZ BlockRISCV64BGEZ BlockRISCV64BLTZ BlockRISCV64BGTZ BlockS390XBRC BlockS390XCRJ BlockS390XCGRJ BlockS390XCLRJ BlockS390XCLGRJ BlockS390XCIJ BlockS390XCGIJ BlockS390XCLIJ BlockS390XCLGIJ BlockPlain BlockIf BlockDefer BlockRet BlockRetJmp BlockExit BlockJumpTable BlockFirst ) var blockString = [...]string{ BlockInvalid: "BlockInvalid", Block386EQ: "EQ", Block386NE: "NE", Block386LT: "LT", Block386LE: "LE", Block386GT: "GT", Block386GE: "GE", Block386OS: "OS", Block386OC: "OC", Block386ULT: "ULT", Block386ULE: "ULE", Block386UGT: "UGT", Block386UGE: "UGE", Block386EQF: "EQF", Block386NEF: "NEF", Block386ORD: "ORD", Block386NAN: "NAN", BlockAMD64EQ: "EQ", BlockAMD64NE: "NE", BlockAMD64LT: "LT", BlockAMD64LE: "LE", BlockAMD64GT: "GT", BlockAMD64GE: "GE", BlockAMD64OS: "OS", BlockAMD64OC: "OC", BlockAMD64ULT: "ULT", BlockAMD64ULE: "ULE", BlockAMD64UGT: "UGT", BlockAMD64UGE: "UGE", BlockAMD64EQF: "EQF", BlockAMD64NEF: "NEF", BlockAMD64ORD: "ORD", BlockAMD64NAN: "NAN", BlockAMD64JUMPTABLE: "JUMPTABLE", BlockARMEQ: "EQ", BlockARMNE: "NE", BlockARMLT: "LT", BlockARMLE: "LE", BlockARMGT: "GT", BlockARMGE: "GE", BlockARMULT: "ULT", BlockARMULE: "ULE", BlockARMUGT: "UGT", BlockARMUGE: "UGE", BlockARMLTnoov: "LTnoov", BlockARMLEnoov: "LEnoov", BlockARMGTnoov: "GTnoov", BlockARMGEnoov: "GEnoov", BlockARM64EQ: "EQ", BlockARM64NE: "NE", BlockARM64LT: "LT", BlockARM64LE: "LE", BlockARM64GT: "GT", BlockARM64GE: "GE", BlockARM64ULT: "ULT", BlockARM64ULE: "ULE", BlockARM64UGT: "UGT", BlockARM64UGE: "UGE", BlockARM64Z: "Z", BlockARM64NZ: "NZ", BlockARM64ZW: "ZW", BlockARM64NZW: "NZW", BlockARM64TBZ: "TBZ", BlockARM64TBNZ: "TBNZ", BlockARM64FLT: "FLT", BlockARM64FLE: "FLE", BlockARM64FGT: "FGT", BlockARM64FGE: "FGE", BlockARM64LTnoov: "LTnoov", BlockARM64LEnoov: "LEnoov", BlockARM64GTnoov: "GTnoov", BlockARM64GEnoov: "GEnoov", BlockARM64JUMPTABLE: "JUMPTABLE", BlockLOONG64EQ: "EQ", BlockLOONG64NE: "NE", BlockLOONG64LTZ: "LTZ", BlockLOONG64LEZ: "LEZ", BlockLOONG64GTZ: "GTZ", BlockLOONG64GEZ: "GEZ", BlockLOONG64FPT: "FPT", BlockLOONG64FPF: "FPF", BlockLOONG64BEQ: "BEQ", BlockLOONG64BNE: "BNE", BlockLOONG64BGE: "BGE", BlockLOONG64BLT: "BLT", BlockLOONG64BGEU: "BGEU", BlockLOONG64BLTU: "BLTU", BlockMIPSEQ: "EQ", BlockMIPSNE: "NE", BlockMIPSLTZ: "LTZ", BlockMIPSLEZ: "LEZ", BlockMIPSGTZ: "GTZ", BlockMIPSGEZ: "GEZ", BlockMIPSFPT: "FPT", BlockMIPSFPF: "FPF", BlockMIPS64EQ: "EQ", BlockMIPS64NE: "NE", BlockMIPS64LTZ: "LTZ", BlockMIPS64LEZ: "LEZ", BlockMIPS64GTZ: "GTZ", BlockMIPS64GEZ: "GEZ", BlockMIPS64FPT: "FPT", BlockMIPS64FPF: "FPF", BlockPPC64EQ: "EQ", BlockPPC64NE: "NE", BlockPPC64LT: "LT", BlockPPC64LE: "LE", BlockPPC64GT: "GT", BlockPPC64GE: "GE", BlockPPC64FLT: "FLT", BlockPPC64FLE: "FLE", BlockPPC64FGT: "FGT", BlockPPC64FGE: "FGE", BlockRISCV64BEQ: "BEQ", BlockRISCV64BNE: "BNE", BlockRISCV64BLT: "BLT", BlockRISCV64BGE: "BGE", BlockRISCV64BLTU: "BLTU", BlockRISCV64BGEU: "BGEU", BlockRISCV64BEQZ: "BEQZ", BlockRISCV64BNEZ: "BNEZ", BlockRISCV64BLEZ: "BLEZ", BlockRISCV64BGEZ: "BGEZ", BlockRISCV64BLTZ: "BLTZ", BlockRISCV64BGTZ: "BGTZ", BlockS390XBRC: "BRC", BlockS390XCRJ: "CRJ", BlockS390XCGRJ: "CGRJ", BlockS390XCLRJ: "CLRJ", BlockS390XCLGRJ: "CLGRJ", BlockS390XCIJ: "CIJ", BlockS390XCGIJ: "CGIJ", BlockS390XCLIJ: "CLIJ", BlockS390XCLGIJ: "CLGIJ", BlockPlain: "Plain", BlockIf: "If", BlockDefer: "Defer", BlockRet: "Ret", BlockRetJmp: "RetJmp", BlockExit: "Exit", BlockJumpTable: "JumpTable", BlockFirst: "First", } func (k BlockKind) String() string { return blockString[k] } func (k BlockKind) AuxIntType() string { switch k { case BlockARM64TBZ: return "int64" case BlockARM64TBNZ: return "int64" case BlockS390XCIJ: return "int8" case BlockS390XCGIJ: return "int8" case BlockS390XCLIJ: return "uint8" case BlockS390XCLGIJ: return "uint8" } return "" } const ( OpInvalid Op = iota Op386ADDSS Op386ADDSD Op386SUBSS Op386SUBSD Op386MULSS Op386MULSD Op386DIVSS Op386DIVSD Op386MOVSSload Op386MOVSDload Op386MOVSSconst Op386MOVSDconst Op386MOVSSloadidx1 Op386MOVSSloadidx4 Op386MOVSDloadidx1 Op386MOVSDloadidx8 Op386MOVSSstore Op386MOVSDstore Op386MOVSSstoreidx1 Op386MOVSSstoreidx4 Op386MOVSDstoreidx1 Op386MOVSDstoreidx8 Op386ADDSSload Op386ADDSDload Op386SUBSSload Op386SUBSDload Op386MULSSload Op386MULSDload Op386DIVSSload Op386DIVSDload Op386ADDL Op386ADDLconst Op386ADDLcarry Op386ADDLconstcarry Op386ADCL Op386ADCLconst Op386SUBL Op386SUBLconst Op386SUBLcarry Op386SUBLconstcarry Op386SBBL Op386SBBLconst Op386MULL Op386MULLconst Op386MULLU Op386HMULL Op386HMULLU Op386MULLQU Op386AVGLU Op386DIVL Op386DIVW Op386DIVLU Op386DIVWU Op386MODL Op386MODW Op386MODLU Op386MODWU Op386ANDL Op386ANDLconst Op386ORL Op386ORLconst Op386XORL Op386XORLconst Op386CMPL Op386CMPW Op386CMPB Op386CMPLconst Op386CMPWconst Op386CMPBconst Op386CMPLload Op386CMPWload Op386CMPBload Op386CMPLconstload Op386CMPWconstload Op386CMPBconstload Op386UCOMISS Op386UCOMISD Op386TESTL Op386TESTW Op386TESTB Op386TESTLconst Op386TESTWconst Op386TESTBconst Op386SHLL Op386SHLLconst Op386SHRL Op386SHRW Op386SHRB Op386SHRLconst Op386SHRWconst Op386SHRBconst Op386SARL Op386SARW Op386SARB Op386SARLconst Op386SARWconst Op386SARBconst Op386ROLL Op386ROLW Op386ROLB Op386ROLLconst Op386ROLWconst Op386ROLBconst Op386ADDLload Op386SUBLload Op386MULLload Op386ANDLload Op386ORLload Op386XORLload Op386ADDLloadidx4 Op386SUBLloadidx4 Op386MULLloadidx4 Op386ANDLloadidx4 Op386ORLloadidx4 Op386XORLloadidx4 Op386NEGL Op386NOTL Op386BSFL Op386BSFW Op386LoweredCtz32 Op386LoweredCtz64 Op386BSRL Op386BSRW Op386BSWAPL Op386SQRTSD Op386SQRTSS Op386SBBLcarrymask Op386SETEQ Op386SETNE Op386SETL Op386SETLE Op386SETG Op386SETGE Op386SETB Op386SETBE Op386SETA Op386SETAE Op386SETO Op386SETEQF Op386SETNEF Op386SETORD Op386SETNAN Op386SETGF Op386SETGEF Op386MOVBLSX Op386MOVBLZX Op386MOVWLSX Op386MOVWLZX Op386MOVLconst Op386CVTTSD2SL Op386CVTTSS2SL Op386CVTSL2SS Op386CVTSL2SD Op386CVTSD2SS Op386CVTSS2SD Op386PXOR Op386LEAL Op386LEAL1 Op386LEAL2 Op386LEAL4 Op386LEAL8 Op386MOVBload Op386MOVBLSXload Op386MOVWload Op386MOVWLSXload Op386MOVLload Op386MOVBstore Op386MOVWstore Op386MOVLstore Op386ADDLmodify Op386SUBLmodify Op386ANDLmodify Op386ORLmodify Op386XORLmodify Op386ADDLmodifyidx4 Op386SUBLmodifyidx4 Op386ANDLmodifyidx4 Op386ORLmodifyidx4 Op386XORLmodifyidx4 Op386ADDLconstmodify Op386ANDLconstmodify Op386ORLconstmodify Op386XORLconstmodify Op386ADDLconstmodifyidx4 Op386ANDLconstmodifyidx4 Op386ORLconstmodifyidx4 Op386XORLconstmodifyidx4 Op386MOVBloadidx1 Op386MOVWloadidx1 Op386MOVWloadidx2 Op386MOVLloadidx1 Op386MOVLloadidx4 Op386MOVBstoreidx1 Op386MOVWstoreidx1 Op386MOVWstoreidx2 Op386MOVLstoreidx1 Op386MOVLstoreidx4 Op386MOVBstoreconst Op386MOVWstoreconst Op386MOVLstoreconst Op386MOVBstoreconstidx1 Op386MOVWstoreconstidx1 Op386MOVWstoreconstidx2 Op386MOVLstoreconstidx1 Op386MOVLstoreconstidx4 Op386DUFFZERO Op386REPSTOSL Op386CALLstatic Op386CALLtail Op386CALLclosure Op386CALLinter Op386DUFFCOPY Op386REPMOVSL Op386InvertFlags Op386LoweredGetG Op386LoweredGetClosurePtr Op386LoweredGetCallerPC Op386LoweredGetCallerSP Op386LoweredNilCheck Op386LoweredWB Op386LoweredPanicBoundsA Op386LoweredPanicBoundsB Op386LoweredPanicBoundsC Op386LoweredPanicExtendA Op386LoweredPanicExtendB Op386LoweredPanicExtendC Op386FlagEQ Op386FlagLT_ULT Op386FlagLT_UGT Op386FlagGT_UGT Op386FlagGT_ULT Op386MOVSSconst1 Op386MOVSDconst1 Op386MOVSSconst2 Op386MOVSDconst2 OpAMD64ADDSS OpAMD64ADDSD OpAMD64SUBSS OpAMD64SUBSD OpAMD64MULSS OpAMD64MULSD OpAMD64DIVSS OpAMD64DIVSD OpAMD64MOVSSload OpAMD64MOVSDload OpAMD64MOVSSconst OpAMD64MOVSDconst OpAMD64MOVSSloadidx1 OpAMD64MOVSSloadidx4 OpAMD64MOVSDloadidx1 OpAMD64MOVSDloadidx8 OpAMD64MOVSSstore OpAMD64MOVSDstore OpAMD64MOVSSstoreidx1 OpAMD64MOVSSstoreidx4 OpAMD64MOVSDstoreidx1 OpAMD64MOVSDstoreidx8 OpAMD64ADDSSload OpAMD64ADDSDload OpAMD64SUBSSload OpAMD64SUBSDload OpAMD64MULSSload OpAMD64MULSDload OpAMD64DIVSSload OpAMD64DIVSDload OpAMD64ADDSSloadidx1 OpAMD64ADDSSloadidx4 OpAMD64ADDSDloadidx1 OpAMD64ADDSDloadidx8 OpAMD64SUBSSloadidx1 OpAMD64SUBSSloadidx4 OpAMD64SUBSDloadidx1 OpAMD64SUBSDloadidx8 OpAMD64MULSSloadidx1 OpAMD64MULSSloadidx4 OpAMD64MULSDloadidx1 OpAMD64MULSDloadidx8 OpAMD64DIVSSloadidx1 OpAMD64DIVSSloadidx4 OpAMD64DIVSDloadidx1 OpAMD64DIVSDloadidx8 OpAMD64ADDQ OpAMD64ADDL OpAMD64ADDQconst OpAMD64ADDLconst OpAMD64ADDQconstmodify OpAMD64ADDLconstmodify OpAMD64SUBQ OpAMD64SUBL OpAMD64SUBQconst OpAMD64SUBLconst OpAMD64MULQ OpAMD64MULL OpAMD64MULQconst OpAMD64MULLconst OpAMD64MULLU OpAMD64MULQU OpAMD64HMULQ OpAMD64HMULL OpAMD64HMULQU OpAMD64HMULLU OpAMD64AVGQU OpAMD64DIVQ OpAMD64DIVL OpAMD64DIVW OpAMD64DIVQU OpAMD64DIVLU OpAMD64DIVWU OpAMD64NEGLflags OpAMD64ADDQcarry OpAMD64ADCQ OpAMD64ADDQconstcarry OpAMD64ADCQconst OpAMD64SUBQborrow OpAMD64SBBQ OpAMD64SUBQconstborrow OpAMD64SBBQconst OpAMD64MULQU2 OpAMD64DIVQU2 OpAMD64ANDQ OpAMD64ANDL OpAMD64ANDQconst OpAMD64ANDLconst OpAMD64ANDQconstmodify OpAMD64ANDLconstmodify OpAMD64ORQ OpAMD64ORL OpAMD64ORQconst OpAMD64ORLconst OpAMD64ORQconstmodify OpAMD64ORLconstmodify OpAMD64XORQ OpAMD64XORL OpAMD64XORQconst OpAMD64XORLconst OpAMD64XORQconstmodify OpAMD64XORLconstmodify OpAMD64CMPQ OpAMD64CMPL OpAMD64CMPW OpAMD64CMPB OpAMD64CMPQconst OpAMD64CMPLconst OpAMD64CMPWconst OpAMD64CMPBconst OpAMD64CMPQload OpAMD64CMPLload OpAMD64CMPWload OpAMD64CMPBload OpAMD64CMPQconstload OpAMD64CMPLconstload OpAMD64CMPWconstload OpAMD64CMPBconstload OpAMD64CMPQloadidx8 OpAMD64CMPQloadidx1 OpAMD64CMPLloadidx4 OpAMD64CMPLloadidx1 OpAMD64CMPWloadidx2 OpAMD64CMPWloadidx1 OpAMD64CMPBloadidx1 OpAMD64CMPQconstloadidx8 OpAMD64CMPQconstloadidx1 OpAMD64CMPLconstloadidx4 OpAMD64CMPLconstloadidx1 OpAMD64CMPWconstloadidx2 OpAMD64CMPWconstloadidx1 OpAMD64CMPBconstloadidx1 OpAMD64UCOMISS OpAMD64UCOMISD OpAMD64BTL OpAMD64BTQ OpAMD64BTCL OpAMD64BTCQ OpAMD64BTRL OpAMD64BTRQ OpAMD64BTSL OpAMD64BTSQ OpAMD64BTLconst OpAMD64BTQconst OpAMD64BTCQconst OpAMD64BTRQconst OpAMD64BTSQconst OpAMD64BTSQconstmodify OpAMD64BTRQconstmodify OpAMD64BTCQconstmodify OpAMD64TESTQ OpAMD64TESTL OpAMD64TESTW OpAMD64TESTB OpAMD64TESTQconst OpAMD64TESTLconst OpAMD64TESTWconst OpAMD64TESTBconst OpAMD64SHLQ OpAMD64SHLL OpAMD64SHLQconst OpAMD64SHLLconst OpAMD64SHRQ OpAMD64SHRL OpAMD64SHRW OpAMD64SHRB OpAMD64SHRQconst OpAMD64SHRLconst OpAMD64SHRWconst OpAMD64SHRBconst OpAMD64SARQ OpAMD64SARL OpAMD64SARW OpAMD64SARB OpAMD64SARQconst OpAMD64SARLconst OpAMD64SARWconst OpAMD64SARBconst OpAMD64SHRDQ OpAMD64SHLDQ OpAMD64ROLQ OpAMD64ROLL OpAMD64ROLW OpAMD64ROLB OpAMD64RORQ OpAMD64RORL OpAMD64RORW OpAMD64RORB OpAMD64ROLQconst OpAMD64ROLLconst OpAMD64ROLWconst OpAMD64ROLBconst OpAMD64ADDLload OpAMD64ADDQload OpAMD64SUBQload OpAMD64SUBLload OpAMD64ANDLload OpAMD64ANDQload OpAMD64ORQload OpAMD64ORLload OpAMD64XORQload OpAMD64XORLload OpAMD64ADDLloadidx1 OpAMD64ADDLloadidx4 OpAMD64ADDLloadidx8 OpAMD64ADDQloadidx1 OpAMD64ADDQloadidx8 OpAMD64SUBLloadidx1 OpAMD64SUBLloadidx4 OpAMD64SUBLloadidx8 OpAMD64SUBQloadidx1 OpAMD64SUBQloadidx8 OpAMD64ANDLloadidx1 OpAMD64ANDLloadidx4 OpAMD64ANDLloadidx8 OpAMD64ANDQloadidx1 OpAMD64ANDQloadidx8 OpAMD64ORLloadidx1 OpAMD64ORLloadidx4 OpAMD64ORLloadidx8 OpAMD64ORQloadidx1 OpAMD64ORQloadidx8 OpAMD64XORLloadidx1 OpAMD64XORLloadidx4 OpAMD64XORLloadidx8 OpAMD64XORQloadidx1 OpAMD64XORQloadidx8 OpAMD64ADDQmodify OpAMD64SUBQmodify OpAMD64ANDQmodify OpAMD64ORQmodify OpAMD64XORQmodify OpAMD64ADDLmodify OpAMD64SUBLmodify OpAMD64ANDLmodify OpAMD64ORLmodify OpAMD64XORLmodify OpAMD64ADDQmodifyidx1 OpAMD64ADDQmodifyidx8 OpAMD64SUBQmodifyidx1 OpAMD64SUBQmodifyidx8 OpAMD64ANDQmodifyidx1 OpAMD64ANDQmodifyidx8 OpAMD64ORQmodifyidx1 OpAMD64ORQmodifyidx8 OpAMD64XORQmodifyidx1 OpAMD64XORQmodifyidx8 OpAMD64ADDLmodifyidx1 OpAMD64ADDLmodifyidx4 OpAMD64ADDLmodifyidx8 OpAMD64SUBLmodifyidx1 OpAMD64SUBLmodifyidx4 OpAMD64SUBLmodifyidx8 OpAMD64ANDLmodifyidx1 OpAMD64ANDLmodifyidx4 OpAMD64ANDLmodifyidx8 OpAMD64ORLmodifyidx1 OpAMD64ORLmodifyidx4 OpAMD64ORLmodifyidx8 OpAMD64XORLmodifyidx1 OpAMD64XORLmodifyidx4 OpAMD64XORLmodifyidx8 OpAMD64ADDQconstmodifyidx1 OpAMD64ADDQconstmodifyidx8 OpAMD64ANDQconstmodifyidx1 OpAMD64ANDQconstmodifyidx8 OpAMD64ORQconstmodifyidx1 OpAMD64ORQconstmodifyidx8 OpAMD64XORQconstmodifyidx1 OpAMD64XORQconstmodifyidx8 OpAMD64ADDLconstmodifyidx1 OpAMD64ADDLconstmodifyidx4 OpAMD64ADDLconstmodifyidx8 OpAMD64ANDLconstmodifyidx1 OpAMD64ANDLconstmodifyidx4 OpAMD64ANDLconstmodifyidx8 OpAMD64ORLconstmodifyidx1 OpAMD64ORLconstmodifyidx4 OpAMD64ORLconstmodifyidx8 OpAMD64XORLconstmodifyidx1 OpAMD64XORLconstmodifyidx4 OpAMD64XORLconstmodifyidx8 OpAMD64NEGQ OpAMD64NEGL OpAMD64NOTQ OpAMD64NOTL OpAMD64BSFQ OpAMD64BSFL OpAMD64BSRQ OpAMD64BSRL OpAMD64CMOVQEQ OpAMD64CMOVQNE OpAMD64CMOVQLT OpAMD64CMOVQGT OpAMD64CMOVQLE OpAMD64CMOVQGE OpAMD64CMOVQLS OpAMD64CMOVQHI OpAMD64CMOVQCC OpAMD64CMOVQCS OpAMD64CMOVLEQ OpAMD64CMOVLNE OpAMD64CMOVLLT OpAMD64CMOVLGT OpAMD64CMOVLLE OpAMD64CMOVLGE OpAMD64CMOVLLS OpAMD64CMOVLHI OpAMD64CMOVLCC OpAMD64CMOVLCS OpAMD64CMOVWEQ OpAMD64CMOVWNE OpAMD64CMOVWLT OpAMD64CMOVWGT OpAMD64CMOVWLE OpAMD64CMOVWGE OpAMD64CMOVWLS OpAMD64CMOVWHI OpAMD64CMOVWCC OpAMD64CMOVWCS OpAMD64CMOVQEQF OpAMD64CMOVQNEF OpAMD64CMOVQGTF OpAMD64CMOVQGEF OpAMD64CMOVLEQF OpAMD64CMOVLNEF OpAMD64CMOVLGTF OpAMD64CMOVLGEF OpAMD64CMOVWEQF OpAMD64CMOVWNEF OpAMD64CMOVWGTF OpAMD64CMOVWGEF OpAMD64BSWAPQ OpAMD64BSWAPL OpAMD64POPCNTQ OpAMD64POPCNTL OpAMD64SQRTSD OpAMD64SQRTSS OpAMD64ROUNDSD OpAMD64LoweredRound32F OpAMD64LoweredRound64F OpAMD64VFMADD231SS OpAMD64VFMADD231SD OpAMD64MINSD OpAMD64MINSS OpAMD64SBBQcarrymask OpAMD64SBBLcarrymask OpAMD64SETEQ OpAMD64SETNE OpAMD64SETL OpAMD64SETLE OpAMD64SETG OpAMD64SETGE OpAMD64SETB OpAMD64SETBE OpAMD64SETA OpAMD64SETAE OpAMD64SETO OpAMD64SETEQstore OpAMD64SETNEstore OpAMD64SETLstore OpAMD64SETLEstore OpAMD64SETGstore OpAMD64SETGEstore OpAMD64SETBstore OpAMD64SETBEstore OpAMD64SETAstore OpAMD64SETAEstore OpAMD64SETEQstoreidx1 OpAMD64SETNEstoreidx1 OpAMD64SETLstoreidx1 OpAMD64SETLEstoreidx1 OpAMD64SETGstoreidx1 OpAMD64SETGEstoreidx1 OpAMD64SETBstoreidx1 OpAMD64SETBEstoreidx1 OpAMD64SETAstoreidx1 OpAMD64SETAEstoreidx1 OpAMD64SETEQF OpAMD64SETNEF OpAMD64SETORD OpAMD64SETNAN OpAMD64SETGF OpAMD64SETGEF OpAMD64MOVBQSX OpAMD64MOVBQZX OpAMD64MOVWQSX OpAMD64MOVWQZX OpAMD64MOVLQSX OpAMD64MOVLQZX OpAMD64MOVLconst OpAMD64MOVQconst OpAMD64CVTTSD2SL OpAMD64CVTTSD2SQ OpAMD64CVTTSS2SL OpAMD64CVTTSS2SQ OpAMD64CVTSL2SS OpAMD64CVTSL2SD OpAMD64CVTSQ2SS OpAMD64CVTSQ2SD OpAMD64CVTSD2SS OpAMD64CVTSS2SD OpAMD64MOVQi2f OpAMD64MOVQf2i OpAMD64MOVLi2f OpAMD64MOVLf2i OpAMD64PXOR OpAMD64POR OpAMD64LEAQ OpAMD64LEAL OpAMD64LEAW OpAMD64LEAQ1 OpAMD64LEAL1 OpAMD64LEAW1 OpAMD64LEAQ2 OpAMD64LEAL2 OpAMD64LEAW2 OpAMD64LEAQ4 OpAMD64LEAL4 OpAMD64LEAW4 OpAMD64LEAQ8 OpAMD64LEAL8 OpAMD64LEAW8 OpAMD64MOVBload OpAMD64MOVBQSXload OpAMD64MOVWload OpAMD64MOVWQSXload OpAMD64MOVLload OpAMD64MOVLQSXload OpAMD64MOVQload OpAMD64MOVBstore OpAMD64MOVWstore OpAMD64MOVLstore OpAMD64MOVQstore OpAMD64MOVOload OpAMD64MOVOstore OpAMD64MOVBloadidx1 OpAMD64MOVWloadidx1 OpAMD64MOVWloadidx2 OpAMD64MOVLloadidx1 OpAMD64MOVLloadidx4 OpAMD64MOVLloadidx8 OpAMD64MOVQloadidx1 OpAMD64MOVQloadidx8 OpAMD64MOVBstoreidx1 OpAMD64MOVWstoreidx1 OpAMD64MOVWstoreidx2 OpAMD64MOVLstoreidx1 OpAMD64MOVLstoreidx4 OpAMD64MOVLstoreidx8 OpAMD64MOVQstoreidx1 OpAMD64MOVQstoreidx8 OpAMD64MOVBstoreconst OpAMD64MOVWstoreconst OpAMD64MOVLstoreconst OpAMD64MOVQstoreconst OpAMD64MOVOstoreconst OpAMD64MOVBstoreconstidx1 OpAMD64MOVWstoreconstidx1 OpAMD64MOVWstoreconstidx2 OpAMD64MOVLstoreconstidx1 OpAMD64MOVLstoreconstidx4 OpAMD64MOVQstoreconstidx1 OpAMD64MOVQstoreconstidx8 OpAMD64DUFFZERO OpAMD64REPSTOSQ OpAMD64CALLstatic OpAMD64CALLtail OpAMD64CALLclosure OpAMD64CALLinter OpAMD64DUFFCOPY OpAMD64REPMOVSQ OpAMD64InvertFlags OpAMD64LoweredGetG OpAMD64LoweredGetClosurePtr OpAMD64LoweredGetCallerPC OpAMD64LoweredGetCallerSP OpAMD64LoweredNilCheck OpAMD64LoweredWB OpAMD64LoweredHasCPUFeature OpAMD64LoweredPanicBoundsA OpAMD64LoweredPanicBoundsB OpAMD64LoweredPanicBoundsC OpAMD64FlagEQ OpAMD64FlagLT_ULT OpAMD64FlagLT_UGT OpAMD64FlagGT_UGT OpAMD64FlagGT_ULT OpAMD64MOVBatomicload OpAMD64MOVLatomicload OpAMD64MOVQatomicload OpAMD64XCHGB OpAMD64XCHGL OpAMD64XCHGQ OpAMD64XADDLlock OpAMD64XADDQlock OpAMD64AddTupleFirst32 OpAMD64AddTupleFirst64 OpAMD64CMPXCHGLlock OpAMD64CMPXCHGQlock OpAMD64ANDBlock OpAMD64ANDLlock OpAMD64ANDQlock OpAMD64ORBlock OpAMD64ORLlock OpAMD64ORQlock OpAMD64LoweredAtomicAnd64 OpAMD64LoweredAtomicAnd32 OpAMD64LoweredAtomicOr64 OpAMD64LoweredAtomicOr32 OpAMD64PrefetchT0 OpAMD64PrefetchNTA OpAMD64ANDNQ OpAMD64ANDNL OpAMD64BLSIQ OpAMD64BLSIL OpAMD64BLSMSKQ OpAMD64BLSMSKL OpAMD64BLSRQ OpAMD64BLSRL OpAMD64TZCNTQ OpAMD64TZCNTL OpAMD64LZCNTQ OpAMD64LZCNTL OpAMD64MOVBEWstore OpAMD64MOVBELload OpAMD64MOVBELstore OpAMD64MOVBEQload OpAMD64MOVBEQstore OpAMD64MOVBELloadidx1 OpAMD64MOVBELloadidx4 OpAMD64MOVBELloadidx8 OpAMD64MOVBEQloadidx1 OpAMD64MOVBEQloadidx8 OpAMD64MOVBEWstoreidx1 OpAMD64MOVBEWstoreidx2 OpAMD64MOVBELstoreidx1 OpAMD64MOVBELstoreidx4 OpAMD64MOVBELstoreidx8 OpAMD64MOVBEQstoreidx1 OpAMD64MOVBEQstoreidx8 OpAMD64SARXQ OpAMD64SARXL OpAMD64SHLXQ OpAMD64SHLXL OpAMD64SHRXQ OpAMD64SHRXL OpAMD64SARXLload OpAMD64SARXQload OpAMD64SHLXLload OpAMD64SHLXQload OpAMD64SHRXLload OpAMD64SHRXQload OpAMD64SARXLloadidx1 OpAMD64SARXLloadidx4 OpAMD64SARXLloadidx8 OpAMD64SARXQloadidx1 OpAMD64SARXQloadidx8 OpAMD64SHLXLloadidx1 OpAMD64SHLXLloadidx4 OpAMD64SHLXLloadidx8 OpAMD64SHLXQloadidx1 OpAMD64SHLXQloadidx8 OpAMD64SHRXLloadidx1 OpAMD64SHRXLloadidx4 OpAMD64SHRXLloadidx8 OpAMD64SHRXQloadidx1 OpAMD64SHRXQloadidx8 OpAMD64PUNPCKLBW OpAMD64PSHUFLW OpAMD64PSHUFBbroadcast OpAMD64VPBROADCASTB OpAMD64PSIGNB OpAMD64PCMPEQB OpAMD64PMOVMSKB OpARMADD OpARMADDconst OpARMSUB OpARMSUBconst OpARMRSB OpARMRSBconst OpARMMUL OpARMHMUL OpARMHMULU OpARMCALLudiv OpARMADDS OpARMADDSconst OpARMADC OpARMADCconst OpARMSUBS OpARMSUBSconst OpARMRSBSconst OpARMSBC OpARMSBCconst OpARMRSCconst OpARMMULLU OpARMMULA OpARMMULS OpARMADDF OpARMADDD OpARMSUBF OpARMSUBD OpARMMULF OpARMMULD OpARMNMULF OpARMNMULD OpARMDIVF OpARMDIVD OpARMMULAF OpARMMULAD OpARMMULSF OpARMMULSD OpARMFMULAD OpARMAND OpARMANDconst OpARMOR OpARMORconst OpARMXOR OpARMXORconst OpARMBIC OpARMBICconst OpARMBFX OpARMBFXU OpARMMVN OpARMNEGF OpARMNEGD OpARMSQRTD OpARMSQRTF OpARMABSD OpARMCLZ OpARMREV OpARMREV16 OpARMRBIT OpARMSLL OpARMSLLconst OpARMSRL OpARMSRLconst OpARMSRA OpARMSRAconst OpARMSRR OpARMSRRconst OpARMADDshiftLL OpARMADDshiftRL OpARMADDshiftRA OpARMSUBshiftLL OpARMSUBshiftRL OpARMSUBshiftRA OpARMRSBshiftLL OpARMRSBshiftRL OpARMRSBshiftRA OpARMANDshiftLL OpARMANDshiftRL OpARMANDshiftRA OpARMORshiftLL OpARMORshiftRL OpARMORshiftRA OpARMXORshiftLL OpARMXORshiftRL OpARMXORshiftRA OpARMXORshiftRR OpARMBICshiftLL OpARMBICshiftRL OpARMBICshiftRA OpARMMVNshiftLL OpARMMVNshiftRL OpARMMVNshiftRA OpARMADCshiftLL OpARMADCshiftRL OpARMADCshiftRA OpARMSBCshiftLL OpARMSBCshiftRL OpARMSBCshiftRA OpARMRSCshiftLL OpARMRSCshiftRL OpARMRSCshiftRA OpARMADDSshiftLL OpARMADDSshiftRL OpARMADDSshiftRA OpARMSUBSshiftLL OpARMSUBSshiftRL OpARMSUBSshiftRA OpARMRSBSshiftLL OpARMRSBSshiftRL OpARMRSBSshiftRA OpARMADDshiftLLreg OpARMADDshiftRLreg OpARMADDshiftRAreg OpARMSUBshiftLLreg OpARMSUBshiftRLreg OpARMSUBshiftRAreg OpARMRSBshiftLLreg OpARMRSBshiftRLreg OpARMRSBshiftRAreg OpARMANDshiftLLreg OpARMANDshiftRLreg OpARMANDshiftRAreg OpARMORshiftLLreg OpARMORshiftRLreg OpARMORshiftRAreg OpARMXORshiftLLreg OpARMXORshiftRLreg OpARMXORshiftRAreg OpARMBICshiftLLreg OpARMBICshiftRLreg OpARMBICshiftRAreg OpARMMVNshiftLLreg OpARMMVNshiftRLreg OpARMMVNshiftRAreg OpARMADCshiftLLreg OpARMADCshiftRLreg OpARMADCshiftRAreg OpARMSBCshiftLLreg OpARMSBCshiftRLreg OpARMSBCshiftRAreg OpARMRSCshiftLLreg OpARMRSCshiftRLreg OpARMRSCshiftRAreg OpARMADDSshiftLLreg OpARMADDSshiftRLreg OpARMADDSshiftRAreg OpARMSUBSshiftLLreg OpARMSUBSshiftRLreg OpARMSUBSshiftRAreg OpARMRSBSshiftLLreg OpARMRSBSshiftRLreg OpARMRSBSshiftRAreg OpARMCMP OpARMCMPconst OpARMCMN OpARMCMNconst OpARMTST OpARMTSTconst OpARMTEQ OpARMTEQconst OpARMCMPF OpARMCMPD OpARMCMPshiftLL OpARMCMPshiftRL OpARMCMPshiftRA OpARMCMNshiftLL OpARMCMNshiftRL OpARMCMNshiftRA OpARMTSTshiftLL OpARMTSTshiftRL OpARMTSTshiftRA OpARMTEQshiftLL OpARMTEQshiftRL OpARMTEQshiftRA OpARMCMPshiftLLreg OpARMCMPshiftRLreg OpARMCMPshiftRAreg OpARMCMNshiftLLreg OpARMCMNshiftRLreg OpARMCMNshiftRAreg OpARMTSTshiftLLreg OpARMTSTshiftRLreg OpARMTSTshiftRAreg OpARMTEQshiftLLreg OpARMTEQshiftRLreg OpARMTEQshiftRAreg OpARMCMPF0 OpARMCMPD0 OpARMMOVWconst OpARMMOVFconst OpARMMOVDconst OpARMMOVWaddr OpARMMOVBload OpARMMOVBUload OpARMMOVHload OpARMMOVHUload OpARMMOVWload OpARMMOVFload OpARMMOVDload OpARMMOVBstore OpARMMOVHstore OpARMMOVWstore OpARMMOVFstore OpARMMOVDstore OpARMMOVWloadidx OpARMMOVWloadshiftLL OpARMMOVWloadshiftRL OpARMMOVWloadshiftRA OpARMMOVBUloadidx OpARMMOVBloadidx OpARMMOVHUloadidx OpARMMOVHloadidx OpARMMOVWstoreidx OpARMMOVWstoreshiftLL OpARMMOVWstoreshiftRL OpARMMOVWstoreshiftRA OpARMMOVBstoreidx OpARMMOVHstoreidx OpARMMOVBreg OpARMMOVBUreg OpARMMOVHreg OpARMMOVHUreg OpARMMOVWreg OpARMMOVWnop OpARMMOVWF OpARMMOVWD OpARMMOVWUF OpARMMOVWUD OpARMMOVFW OpARMMOVDW OpARMMOVFWU OpARMMOVDWU OpARMMOVFD OpARMMOVDF OpARMCMOVWHSconst OpARMCMOVWLSconst OpARMSRAcond OpARMCALLstatic OpARMCALLtail OpARMCALLclosure OpARMCALLinter OpARMLoweredNilCheck OpARMEqual OpARMNotEqual OpARMLessThan OpARMLessEqual OpARMGreaterThan OpARMGreaterEqual OpARMLessThanU OpARMLessEqualU OpARMGreaterThanU OpARMGreaterEqualU OpARMDUFFZERO OpARMDUFFCOPY OpARMLoweredZero OpARMLoweredMove OpARMLoweredGetClosurePtr OpARMLoweredGetCallerSP OpARMLoweredGetCallerPC OpARMLoweredPanicBoundsA OpARMLoweredPanicBoundsB OpARMLoweredPanicBoundsC OpARMLoweredPanicExtendA OpARMLoweredPanicExtendB OpARMLoweredPanicExtendC OpARMFlagConstant OpARMInvertFlags OpARMLoweredWB OpARM64ADCSflags OpARM64ADCzerocarry OpARM64ADD OpARM64ADDconst OpARM64ADDSconstflags OpARM64ADDSflags OpARM64SUB OpARM64SUBconst OpARM64SBCSflags OpARM64SUBSflags OpARM64MUL OpARM64MULW OpARM64MNEG OpARM64MNEGW OpARM64MULH OpARM64UMULH OpARM64MULL OpARM64UMULL OpARM64DIV OpARM64UDIV OpARM64DIVW OpARM64UDIVW OpARM64MOD OpARM64UMOD OpARM64MODW OpARM64UMODW OpARM64FADDS OpARM64FADDD OpARM64FSUBS OpARM64FSUBD OpARM64FMULS OpARM64FMULD OpARM64FNMULS OpARM64FNMULD OpARM64FDIVS OpARM64FDIVD OpARM64AND OpARM64ANDconst OpARM64OR OpARM64ORconst OpARM64XOR OpARM64XORconst OpARM64BIC OpARM64EON OpARM64ORN OpARM64MVN OpARM64NEG OpARM64NEGSflags OpARM64NGCzerocarry OpARM64FABSD OpARM64FNEGS OpARM64FNEGD OpARM64FSQRTD OpARM64FSQRTS OpARM64FMIND OpARM64FMINS OpARM64FMAXD OpARM64FMAXS OpARM64REV OpARM64REVW OpARM64REV16 OpARM64REV16W OpARM64RBIT OpARM64RBITW OpARM64CLZ OpARM64CLZW OpARM64VCNT OpARM64VUADDLV OpARM64LoweredRound32F OpARM64LoweredRound64F OpARM64FMADDS OpARM64FMADDD OpARM64FNMADDS OpARM64FNMADDD OpARM64FMSUBS OpARM64FMSUBD OpARM64FNMSUBS OpARM64FNMSUBD OpARM64MADD OpARM64MADDW OpARM64MSUB OpARM64MSUBW OpARM64SLL OpARM64SLLconst OpARM64SRL OpARM64SRLconst OpARM64SRA OpARM64SRAconst OpARM64ROR OpARM64RORW OpARM64RORconst OpARM64RORWconst OpARM64EXTRconst OpARM64EXTRWconst OpARM64CMP OpARM64CMPconst OpARM64CMPW OpARM64CMPWconst OpARM64CMN OpARM64CMNconst OpARM64CMNW OpARM64CMNWconst OpARM64TST OpARM64TSTconst OpARM64TSTW OpARM64TSTWconst OpARM64FCMPS OpARM64FCMPD OpARM64FCMPS0 OpARM64FCMPD0 OpARM64MVNshiftLL OpARM64MVNshiftRL OpARM64MVNshiftRA OpARM64MVNshiftRO OpARM64NEGshiftLL OpARM64NEGshiftRL OpARM64NEGshiftRA OpARM64ADDshiftLL OpARM64ADDshiftRL OpARM64ADDshiftRA OpARM64SUBshiftLL OpARM64SUBshiftRL OpARM64SUBshiftRA OpARM64ANDshiftLL OpARM64ANDshiftRL OpARM64ANDshiftRA OpARM64ANDshiftRO OpARM64ORshiftLL OpARM64ORshiftRL OpARM64ORshiftRA OpARM64ORshiftRO OpARM64XORshiftLL OpARM64XORshiftRL OpARM64XORshiftRA OpARM64XORshiftRO OpARM64BICshiftLL OpARM64BICshiftRL OpARM64BICshiftRA OpARM64BICshiftRO OpARM64EONshiftLL OpARM64EONshiftRL OpARM64EONshiftRA OpARM64EONshiftRO OpARM64ORNshiftLL OpARM64ORNshiftRL OpARM64ORNshiftRA OpARM64ORNshiftRO OpARM64CMPshiftLL OpARM64CMPshiftRL OpARM64CMPshiftRA OpARM64CMNshiftLL OpARM64CMNshiftRL OpARM64CMNshiftRA OpARM64TSTshiftLL OpARM64TSTshiftRL OpARM64TSTshiftRA OpARM64TSTshiftRO OpARM64BFI OpARM64BFXIL OpARM64SBFIZ OpARM64SBFX OpARM64UBFIZ OpARM64UBFX OpARM64MOVDconst OpARM64FMOVSconst OpARM64FMOVDconst OpARM64MOVDaddr OpARM64MOVBload OpARM64MOVBUload OpARM64MOVHload OpARM64MOVHUload OpARM64MOVWload OpARM64MOVWUload OpARM64MOVDload OpARM64FMOVSload OpARM64FMOVDload OpARM64LDP OpARM64LDPW OpARM64LDPSW OpARM64FLDPD OpARM64FLDPS OpARM64MOVDloadidx OpARM64MOVWloadidx OpARM64MOVWUloadidx OpARM64MOVHloadidx OpARM64MOVHUloadidx OpARM64MOVBloadidx OpARM64MOVBUloadidx OpARM64FMOVSloadidx OpARM64FMOVDloadidx OpARM64MOVHloadidx2 OpARM64MOVHUloadidx2 OpARM64MOVWloadidx4 OpARM64MOVWUloadidx4 OpARM64MOVDloadidx8 OpARM64FMOVSloadidx4 OpARM64FMOVDloadidx8 OpARM64MOVBstore OpARM64MOVHstore OpARM64MOVWstore OpARM64MOVDstore OpARM64FMOVSstore OpARM64FMOVDstore OpARM64STP OpARM64STPW OpARM64FSTPD OpARM64FSTPS OpARM64MOVBstoreidx OpARM64MOVHstoreidx OpARM64MOVWstoreidx OpARM64MOVDstoreidx OpARM64FMOVSstoreidx OpARM64FMOVDstoreidx OpARM64MOVHstoreidx2 OpARM64MOVWstoreidx4 OpARM64MOVDstoreidx8 OpARM64FMOVSstoreidx4 OpARM64FMOVDstoreidx8 OpARM64FMOVDgpfp OpARM64FMOVDfpgp OpARM64FMOVSgpfp OpARM64FMOVSfpgp OpARM64MOVBreg OpARM64MOVBUreg OpARM64MOVHreg OpARM64MOVHUreg OpARM64MOVWreg OpARM64MOVWUreg OpARM64MOVDreg OpARM64MOVDnop OpARM64SCVTFWS OpARM64SCVTFWD OpARM64UCVTFWS OpARM64UCVTFWD OpARM64SCVTFS OpARM64SCVTFD OpARM64UCVTFS OpARM64UCVTFD OpARM64FCVTZSSW OpARM64FCVTZSDW OpARM64FCVTZUSW OpARM64FCVTZUDW OpARM64FCVTZSS OpARM64FCVTZSD OpARM64FCVTZUS OpARM64FCVTZUD OpARM64FCVTSD OpARM64FCVTDS OpARM64FRINTAD OpARM64FRINTMD OpARM64FRINTND OpARM64FRINTPD OpARM64FRINTZD OpARM64CSEL OpARM64CSEL0 OpARM64CSINC OpARM64CSINV OpARM64CSNEG OpARM64CSETM OpARM64CALLstatic OpARM64CALLtail OpARM64CALLclosure OpARM64CALLinter OpARM64LoweredNilCheck OpARM64Equal OpARM64NotEqual OpARM64LessThan OpARM64LessEqual OpARM64GreaterThan OpARM64GreaterEqual OpARM64LessThanU OpARM64LessEqualU OpARM64GreaterThanU OpARM64GreaterEqualU OpARM64LessThanF OpARM64LessEqualF OpARM64GreaterThanF OpARM64GreaterEqualF OpARM64NotLessThanF OpARM64NotLessEqualF OpARM64NotGreaterThanF OpARM64NotGreaterEqualF OpARM64LessThanNoov OpARM64GreaterEqualNoov OpARM64DUFFZERO OpARM64LoweredZero OpARM64DUFFCOPY OpARM64LoweredMove OpARM64LoweredGetClosurePtr OpARM64LoweredGetCallerSP OpARM64LoweredGetCallerPC OpARM64FlagConstant OpARM64InvertFlags OpARM64LDAR OpARM64LDARB OpARM64LDARW OpARM64STLRB OpARM64STLR OpARM64STLRW OpARM64LoweredAtomicExchange64 OpARM64LoweredAtomicExchange32 OpARM64LoweredAtomicExchange8 OpARM64LoweredAtomicExchange64Variant OpARM64LoweredAtomicExchange32Variant OpARM64LoweredAtomicExchange8Variant OpARM64LoweredAtomicAdd64 OpARM64LoweredAtomicAdd32 OpARM64LoweredAtomicAdd64Variant OpARM64LoweredAtomicAdd32Variant OpARM64LoweredAtomicCas64 OpARM64LoweredAtomicCas32 OpARM64LoweredAtomicCas64Variant OpARM64LoweredAtomicCas32Variant OpARM64LoweredAtomicAnd8 OpARM64LoweredAtomicOr8 OpARM64LoweredAtomicAnd64 OpARM64LoweredAtomicOr64 OpARM64LoweredAtomicAnd32 OpARM64LoweredAtomicOr32 OpARM64LoweredAtomicAnd8Variant OpARM64LoweredAtomicOr8Variant OpARM64LoweredAtomicAnd64Variant OpARM64LoweredAtomicOr64Variant OpARM64LoweredAtomicAnd32Variant OpARM64LoweredAtomicOr32Variant OpARM64LoweredWB OpARM64LoweredPanicBoundsA OpARM64LoweredPanicBoundsB OpARM64LoweredPanicBoundsC OpARM64PRFM OpARM64DMB OpARM64ZERO OpLOONG64NEGV OpLOONG64NEGF OpLOONG64NEGD OpLOONG64SQRTD OpLOONG64SQRTF OpLOONG64ABSD OpLOONG64CLZW OpLOONG64CLZV OpLOONG64CTZW OpLOONG64CTZV OpLOONG64REVB2H OpLOONG64REVB2W OpLOONG64REVBV OpLOONG64BITREV4B OpLOONG64BITREVW OpLOONG64BITREVV OpLOONG64VPCNT64 OpLOONG64VPCNT32 OpLOONG64VPCNT16 OpLOONG64ADDV OpLOONG64ADDVconst OpLOONG64SUBV OpLOONG64SUBVconst OpLOONG64MULV OpLOONG64MULHV OpLOONG64MULHVU OpLOONG64DIVV OpLOONG64DIVVU OpLOONG64REMV OpLOONG64REMVU OpLOONG64ADDF OpLOONG64ADDD OpLOONG64SUBF OpLOONG64SUBD OpLOONG64MULF OpLOONG64MULD OpLOONG64DIVF OpLOONG64DIVD OpLOONG64AND OpLOONG64ANDconst OpLOONG64OR OpLOONG64ORconst OpLOONG64XOR OpLOONG64XORconst OpLOONG64NOR OpLOONG64NORconst OpLOONG64FMADDF OpLOONG64FMADDD OpLOONG64FMSUBF OpLOONG64FMSUBD OpLOONG64FNMADDF OpLOONG64FNMADDD OpLOONG64FNMSUBF OpLOONG64FNMSUBD OpLOONG64FMINF OpLOONG64FMIND OpLOONG64FMAXF OpLOONG64FMAXD OpLOONG64MASKEQZ OpLOONG64MASKNEZ OpLOONG64FCOPYSGD OpLOONG64SLL OpLOONG64SLLV OpLOONG64SLLconst OpLOONG64SLLVconst OpLOONG64SRL OpLOONG64SRLV OpLOONG64SRLconst OpLOONG64SRLVconst OpLOONG64SRA OpLOONG64SRAV OpLOONG64SRAconst OpLOONG64SRAVconst OpLOONG64ROTR OpLOONG64ROTRV OpLOONG64ROTRconst OpLOONG64ROTRVconst OpLOONG64SGT OpLOONG64SGTconst OpLOONG64SGTU OpLOONG64SGTUconst OpLOONG64CMPEQF OpLOONG64CMPEQD OpLOONG64CMPGEF OpLOONG64CMPGED OpLOONG64CMPGTF OpLOONG64CMPGTD OpLOONG64BSTRPICKW OpLOONG64BSTRPICKV OpLOONG64MOVVconst OpLOONG64MOVFconst OpLOONG64MOVDconst OpLOONG64MOVVaddr OpLOONG64MOVBload OpLOONG64MOVBUload OpLOONG64MOVHload OpLOONG64MOVHUload OpLOONG64MOVWload OpLOONG64MOVWUload OpLOONG64MOVVload OpLOONG64MOVFload OpLOONG64MOVDload OpLOONG64MOVVloadidx OpLOONG64MOVWloadidx OpLOONG64MOVWUloadidx OpLOONG64MOVHloadidx OpLOONG64MOVHUloadidx OpLOONG64MOVBloadidx OpLOONG64MOVBUloadidx OpLOONG64MOVFloadidx OpLOONG64MOVDloadidx OpLOONG64MOVBstore OpLOONG64MOVHstore OpLOONG64MOVWstore OpLOONG64MOVVstore OpLOONG64MOVFstore OpLOONG64MOVDstore OpLOONG64MOVBstoreidx OpLOONG64MOVHstoreidx OpLOONG64MOVWstoreidx OpLOONG64MOVVstoreidx OpLOONG64MOVFstoreidx OpLOONG64MOVDstoreidx OpLOONG64MOVBstorezero OpLOONG64MOVHstorezero OpLOONG64MOVWstorezero OpLOONG64MOVVstorezero OpLOONG64MOVBstorezeroidx OpLOONG64MOVHstorezeroidx OpLOONG64MOVWstorezeroidx OpLOONG64MOVVstorezeroidx OpLOONG64MOVWfpgp OpLOONG64MOVWgpfp OpLOONG64MOVVfpgp OpLOONG64MOVVgpfp OpLOONG64MOVBreg OpLOONG64MOVBUreg OpLOONG64MOVHreg OpLOONG64MOVHUreg OpLOONG64MOVWreg OpLOONG64MOVWUreg OpLOONG64MOVVreg OpLOONG64MOVVnop OpLOONG64MOVWF OpLOONG64MOVWD OpLOONG64MOVVF OpLOONG64MOVVD OpLOONG64TRUNCFW OpLOONG64TRUNCDW OpLOONG64TRUNCFV OpLOONG64TRUNCDV OpLOONG64MOVFD OpLOONG64MOVDF OpLOONG64LoweredRound32F OpLOONG64LoweredRound64F OpLOONG64CALLstatic OpLOONG64CALLtail OpLOONG64CALLclosure OpLOONG64CALLinter OpLOONG64DUFFZERO OpLOONG64DUFFCOPY OpLOONG64LoweredZero OpLOONG64LoweredMove OpLOONG64LoweredAtomicLoad8 OpLOONG64LoweredAtomicLoad32 OpLOONG64LoweredAtomicLoad64 OpLOONG64LoweredAtomicStore8 OpLOONG64LoweredAtomicStore32 OpLOONG64LoweredAtomicStore64 OpLOONG64LoweredAtomicStore8Variant OpLOONG64LoweredAtomicStore32Variant OpLOONG64LoweredAtomicStore64Variant OpLOONG64LoweredAtomicExchange32 OpLOONG64LoweredAtomicExchange64 OpLOONG64LoweredAtomicExchange8Variant OpLOONG64LoweredAtomicAdd32 OpLOONG64LoweredAtomicAdd64 OpLOONG64LoweredAtomicCas32 OpLOONG64LoweredAtomicCas64 OpLOONG64LoweredAtomicCas64Variant OpLOONG64LoweredAtomicCas32Variant OpLOONG64LoweredAtomicAnd32 OpLOONG64LoweredAtomicOr32 OpLOONG64LoweredAtomicAnd32value OpLOONG64LoweredAtomicAnd64value OpLOONG64LoweredAtomicOr32value OpLOONG64LoweredAtomicOr64value OpLOONG64LoweredNilCheck OpLOONG64FPFlagTrue OpLOONG64FPFlagFalse OpLOONG64LoweredGetClosurePtr OpLOONG64LoweredGetCallerSP OpLOONG64LoweredGetCallerPC OpLOONG64LoweredWB OpLOONG64LoweredPubBarrier OpLOONG64LoweredPanicBoundsA OpLOONG64LoweredPanicBoundsB OpLOONG64LoweredPanicBoundsC OpMIPSADD OpMIPSADDconst OpMIPSSUB OpMIPSSUBconst OpMIPSMUL OpMIPSMULT OpMIPSMULTU OpMIPSDIV OpMIPSDIVU OpMIPSADDF OpMIPSADDD OpMIPSSUBF OpMIPSSUBD OpMIPSMULF OpMIPSMULD OpMIPSDIVF OpMIPSDIVD OpMIPSAND OpMIPSANDconst OpMIPSOR OpMIPSORconst OpMIPSXOR OpMIPSXORconst OpMIPSNOR OpMIPSNORconst OpMIPSNEG OpMIPSNEGF OpMIPSNEGD OpMIPSABSD OpMIPSSQRTD OpMIPSSQRTF OpMIPSSLL OpMIPSSLLconst OpMIPSSRL OpMIPSSRLconst OpMIPSSRA OpMIPSSRAconst OpMIPSCLZ OpMIPSSGT OpMIPSSGTconst OpMIPSSGTzero OpMIPSSGTU OpMIPSSGTUconst OpMIPSSGTUzero OpMIPSCMPEQF OpMIPSCMPEQD OpMIPSCMPGEF OpMIPSCMPGED OpMIPSCMPGTF OpMIPSCMPGTD OpMIPSMOVWconst OpMIPSMOVFconst OpMIPSMOVDconst OpMIPSMOVWaddr OpMIPSMOVBload OpMIPSMOVBUload OpMIPSMOVHload OpMIPSMOVHUload OpMIPSMOVWload OpMIPSMOVFload OpMIPSMOVDload OpMIPSMOVBstore OpMIPSMOVHstore OpMIPSMOVWstore OpMIPSMOVFstore OpMIPSMOVDstore OpMIPSMOVBstorezero OpMIPSMOVHstorezero OpMIPSMOVWstorezero OpMIPSMOVWfpgp OpMIPSMOVWgpfp OpMIPSMOVBreg OpMIPSMOVBUreg OpMIPSMOVHreg OpMIPSMOVHUreg OpMIPSMOVWreg OpMIPSMOVWnop OpMIPSCMOVZ OpMIPSCMOVZzero OpMIPSMOVWF OpMIPSMOVWD OpMIPSTRUNCFW OpMIPSTRUNCDW OpMIPSMOVFD OpMIPSMOVDF OpMIPSCALLstatic OpMIPSCALLtail OpMIPSCALLclosure OpMIPSCALLinter OpMIPSLoweredAtomicLoad8 OpMIPSLoweredAtomicLoad32 OpMIPSLoweredAtomicStore8 OpMIPSLoweredAtomicStore32 OpMIPSLoweredAtomicStorezero OpMIPSLoweredAtomicExchange OpMIPSLoweredAtomicAdd OpMIPSLoweredAtomicAddconst OpMIPSLoweredAtomicCas OpMIPSLoweredAtomicAnd OpMIPSLoweredAtomicOr OpMIPSLoweredZero OpMIPSLoweredMove OpMIPSLoweredNilCheck OpMIPSFPFlagTrue OpMIPSFPFlagFalse OpMIPSLoweredGetClosurePtr OpMIPSLoweredGetCallerSP OpMIPSLoweredGetCallerPC OpMIPSLoweredWB OpMIPSLoweredPanicBoundsA OpMIPSLoweredPanicBoundsB OpMIPSLoweredPanicBoundsC OpMIPSLoweredPanicExtendA OpMIPSLoweredPanicExtendB OpMIPSLoweredPanicExtendC OpMIPS64ADDV OpMIPS64ADDVconst OpMIPS64SUBV OpMIPS64SUBVconst OpMIPS64MULV OpMIPS64MULVU OpMIPS64DIVV OpMIPS64DIVVU OpMIPS64ADDF OpMIPS64ADDD OpMIPS64SUBF OpMIPS64SUBD OpMIPS64MULF OpMIPS64MULD OpMIPS64DIVF OpMIPS64DIVD OpMIPS64AND OpMIPS64ANDconst OpMIPS64OR OpMIPS64ORconst OpMIPS64XOR OpMIPS64XORconst OpMIPS64NOR OpMIPS64NORconst OpMIPS64NEGV OpMIPS64NEGF OpMIPS64NEGD OpMIPS64ABSD OpMIPS64SQRTD OpMIPS64SQRTF OpMIPS64SLLV OpMIPS64SLLVconst OpMIPS64SRLV OpMIPS64SRLVconst OpMIPS64SRAV OpMIPS64SRAVconst OpMIPS64SGT OpMIPS64SGTconst OpMIPS64SGTU OpMIPS64SGTUconst OpMIPS64CMPEQF OpMIPS64CMPEQD OpMIPS64CMPGEF OpMIPS64CMPGED OpMIPS64CMPGTF OpMIPS64CMPGTD OpMIPS64MOVVconst OpMIPS64MOVFconst OpMIPS64MOVDconst OpMIPS64MOVVaddr OpMIPS64MOVBload OpMIPS64MOVBUload OpMIPS64MOVHload OpMIPS64MOVHUload OpMIPS64MOVWload OpMIPS64MOVWUload OpMIPS64MOVVload OpMIPS64MOVFload OpMIPS64MOVDload OpMIPS64MOVBstore OpMIPS64MOVHstore OpMIPS64MOVWstore OpMIPS64MOVVstore OpMIPS64MOVFstore OpMIPS64MOVDstore OpMIPS64MOVBstorezero OpMIPS64MOVHstorezero OpMIPS64MOVWstorezero OpMIPS64MOVVstorezero OpMIPS64MOVWfpgp OpMIPS64MOVWgpfp OpMIPS64MOVVfpgp OpMIPS64MOVVgpfp OpMIPS64MOVBreg OpMIPS64MOVBUreg OpMIPS64MOVHreg OpMIPS64MOVHUreg OpMIPS64MOVWreg OpMIPS64MOVWUreg OpMIPS64MOVVreg OpMIPS64MOVVnop OpMIPS64MOVWF OpMIPS64MOVWD OpMIPS64MOVVF OpMIPS64MOVVD OpMIPS64TRUNCFW OpMIPS64TRUNCDW OpMIPS64TRUNCFV OpMIPS64TRUNCDV OpMIPS64MOVFD OpMIPS64MOVDF OpMIPS64CALLstatic OpMIPS64CALLtail OpMIPS64CALLclosure OpMIPS64CALLinter OpMIPS64DUFFZERO OpMIPS64DUFFCOPY OpMIPS64LoweredZero OpMIPS64LoweredMove OpMIPS64LoweredAtomicAnd32 OpMIPS64LoweredAtomicOr32 OpMIPS64LoweredAtomicLoad8 OpMIPS64LoweredAtomicLoad32 OpMIPS64LoweredAtomicLoad64 OpMIPS64LoweredAtomicStore8 OpMIPS64LoweredAtomicStore32 OpMIPS64LoweredAtomicStore64 OpMIPS64LoweredAtomicStorezero32 OpMIPS64LoweredAtomicStorezero64 OpMIPS64LoweredAtomicExchange32 OpMIPS64LoweredAtomicExchange64 OpMIPS64LoweredAtomicAdd32 OpMIPS64LoweredAtomicAdd64 OpMIPS64LoweredAtomicAddconst32 OpMIPS64LoweredAtomicAddconst64 OpMIPS64LoweredAtomicCas32 OpMIPS64LoweredAtomicCas64 OpMIPS64LoweredNilCheck OpMIPS64FPFlagTrue OpMIPS64FPFlagFalse OpMIPS64LoweredGetClosurePtr OpMIPS64LoweredGetCallerSP OpMIPS64LoweredGetCallerPC OpMIPS64LoweredWB OpMIPS64LoweredPanicBoundsA OpMIPS64LoweredPanicBoundsB OpMIPS64LoweredPanicBoundsC OpPPC64ADD OpPPC64ADDCC OpPPC64ADDconst OpPPC64ADDCCconst OpPPC64FADD OpPPC64FADDS OpPPC64SUB OpPPC64SUBCC OpPPC64SUBFCconst OpPPC64FSUB OpPPC64FSUBS OpPPC64XSMINJDP OpPPC64XSMAXJDP OpPPC64MULLD OpPPC64MULLW OpPPC64MULLDconst OpPPC64MULLWconst OpPPC64MADDLD OpPPC64MULHD OpPPC64MULHW OpPPC64MULHDU OpPPC64MULHDUCC OpPPC64MULHWU OpPPC64FMUL OpPPC64FMULS OpPPC64FMADD OpPPC64FMADDS OpPPC64FMSUB OpPPC64FMSUBS OpPPC64SRAD OpPPC64SRAW OpPPC64SRD OpPPC64SRW OpPPC64SLD OpPPC64SLW OpPPC64ROTL OpPPC64ROTLW OpPPC64CLRLSLWI OpPPC64CLRLSLDI OpPPC64ADDC OpPPC64SUBC OpPPC64ADDCconst OpPPC64SUBCconst OpPPC64ADDE OpPPC64ADDZE OpPPC64SUBE OpPPC64ADDZEzero OpPPC64SUBZEzero OpPPC64SRADconst OpPPC64SRAWconst OpPPC64SRDconst OpPPC64SRWconst OpPPC64SLDconst OpPPC64SLWconst OpPPC64ROTLconst OpPPC64ROTLWconst OpPPC64EXTSWSLconst OpPPC64RLWINM OpPPC64RLWNM OpPPC64RLWMI OpPPC64RLDICL OpPPC64RLDICLCC OpPPC64RLDICR OpPPC64CNTLZD OpPPC64CNTLZDCC OpPPC64CNTLZW OpPPC64CNTTZD OpPPC64CNTTZW OpPPC64POPCNTD OpPPC64POPCNTW OpPPC64POPCNTB OpPPC64FDIV OpPPC64FDIVS OpPPC64DIVD OpPPC64DIVW OpPPC64DIVDU OpPPC64DIVWU OpPPC64MODUD OpPPC64MODSD OpPPC64MODUW OpPPC64MODSW OpPPC64FCTIDZ OpPPC64FCTIWZ OpPPC64FCFID OpPPC64FCFIDS OpPPC64FRSP OpPPC64MFVSRD OpPPC64MTVSRD OpPPC64AND OpPPC64ANDN OpPPC64ANDNCC OpPPC64ANDCC OpPPC64OR OpPPC64ORN OpPPC64ORCC OpPPC64NOR OpPPC64NORCC OpPPC64XOR OpPPC64XORCC OpPPC64EQV OpPPC64NEG OpPPC64NEGCC OpPPC64BRD OpPPC64BRW OpPPC64BRH OpPPC64FNEG OpPPC64FSQRT OpPPC64FSQRTS OpPPC64FFLOOR OpPPC64FCEIL OpPPC64FTRUNC OpPPC64FROUND OpPPC64FABS OpPPC64FNABS OpPPC64FCPSGN OpPPC64ORconst OpPPC64XORconst OpPPC64ANDCCconst OpPPC64ANDconst OpPPC64MOVBreg OpPPC64MOVBZreg OpPPC64MOVHreg OpPPC64MOVHZreg OpPPC64MOVWreg OpPPC64MOVWZreg OpPPC64MOVBZload OpPPC64MOVHload OpPPC64MOVHZload OpPPC64MOVWload OpPPC64MOVWZload OpPPC64MOVDload OpPPC64MOVDBRload OpPPC64MOVWBRload OpPPC64MOVHBRload OpPPC64MOVBZloadidx OpPPC64MOVHloadidx OpPPC64MOVHZloadidx OpPPC64MOVWloadidx OpPPC64MOVWZloadidx OpPPC64MOVDloadidx OpPPC64MOVHBRloadidx OpPPC64MOVWBRloadidx OpPPC64MOVDBRloadidx OpPPC64FMOVDloadidx OpPPC64FMOVSloadidx OpPPC64DCBT OpPPC64MOVDBRstore OpPPC64MOVWBRstore OpPPC64MOVHBRstore OpPPC64FMOVDload OpPPC64FMOVSload OpPPC64MOVBstore OpPPC64MOVHstore OpPPC64MOVWstore OpPPC64MOVDstore OpPPC64FMOVDstore OpPPC64FMOVSstore OpPPC64MOVBstoreidx OpPPC64MOVHstoreidx OpPPC64MOVWstoreidx OpPPC64MOVDstoreidx OpPPC64FMOVDstoreidx OpPPC64FMOVSstoreidx OpPPC64MOVHBRstoreidx OpPPC64MOVWBRstoreidx OpPPC64MOVDBRstoreidx OpPPC64MOVBstorezero OpPPC64MOVHstorezero OpPPC64MOVWstorezero OpPPC64MOVDstorezero OpPPC64MOVDaddr OpPPC64MOVDconst OpPPC64FMOVDconst OpPPC64FMOVSconst OpPPC64FCMPU OpPPC64CMP OpPPC64CMPU OpPPC64CMPW OpPPC64CMPWU OpPPC64CMPconst OpPPC64CMPUconst OpPPC64CMPWconst OpPPC64CMPWUconst OpPPC64ISEL OpPPC64ISELZ OpPPC64SETBC OpPPC64SETBCR OpPPC64Equal OpPPC64NotEqual OpPPC64LessThan OpPPC64FLessThan OpPPC64LessEqual OpPPC64FLessEqual OpPPC64GreaterThan OpPPC64FGreaterThan OpPPC64GreaterEqual OpPPC64FGreaterEqual OpPPC64LoweredGetClosurePtr OpPPC64LoweredGetCallerSP OpPPC64LoweredGetCallerPC OpPPC64LoweredNilCheck OpPPC64LoweredRound32F OpPPC64LoweredRound64F OpPPC64CALLstatic OpPPC64CALLtail OpPPC64CALLclosure OpPPC64CALLinter OpPPC64LoweredZero OpPPC64LoweredZeroShort OpPPC64LoweredQuadZeroShort OpPPC64LoweredQuadZero OpPPC64LoweredMove OpPPC64LoweredMoveShort OpPPC64LoweredQuadMove OpPPC64LoweredQuadMoveShort OpPPC64LoweredAtomicStore8 OpPPC64LoweredAtomicStore32 OpPPC64LoweredAtomicStore64 OpPPC64LoweredAtomicLoad8 OpPPC64LoweredAtomicLoad32 OpPPC64LoweredAtomicLoad64 OpPPC64LoweredAtomicLoadPtr OpPPC64LoweredAtomicAdd32 OpPPC64LoweredAtomicAdd64 OpPPC64LoweredAtomicExchange8 OpPPC64LoweredAtomicExchange32 OpPPC64LoweredAtomicExchange64 OpPPC64LoweredAtomicCas64 OpPPC64LoweredAtomicCas32 OpPPC64LoweredAtomicAnd8 OpPPC64LoweredAtomicAnd32 OpPPC64LoweredAtomicOr8 OpPPC64LoweredAtomicOr32 OpPPC64LoweredWB OpPPC64LoweredPubBarrier OpPPC64LoweredPanicBoundsA OpPPC64LoweredPanicBoundsB OpPPC64LoweredPanicBoundsC OpPPC64InvertFlags OpPPC64FlagEQ OpPPC64FlagLT OpPPC64FlagGT OpRISCV64ADD OpRISCV64ADDI OpRISCV64ADDIW OpRISCV64NEG OpRISCV64NEGW OpRISCV64SUB OpRISCV64SUBW OpRISCV64MUL OpRISCV64MULW OpRISCV64MULH OpRISCV64MULHU OpRISCV64LoweredMuluhilo OpRISCV64LoweredMuluover OpRISCV64DIV OpRISCV64DIVU OpRISCV64DIVW OpRISCV64DIVUW OpRISCV64REM OpRISCV64REMU OpRISCV64REMW OpRISCV64REMUW OpRISCV64MOVaddr OpRISCV64MOVDconst OpRISCV64MOVBload OpRISCV64MOVHload OpRISCV64MOVWload OpRISCV64MOVDload OpRISCV64MOVBUload OpRISCV64MOVHUload OpRISCV64MOVWUload OpRISCV64MOVBstore OpRISCV64MOVHstore OpRISCV64MOVWstore OpRISCV64MOVDstore OpRISCV64MOVBstorezero OpRISCV64MOVHstorezero OpRISCV64MOVWstorezero OpRISCV64MOVDstorezero OpRISCV64MOVBreg OpRISCV64MOVHreg OpRISCV64MOVWreg OpRISCV64MOVDreg OpRISCV64MOVBUreg OpRISCV64MOVHUreg OpRISCV64MOVWUreg OpRISCV64MOVDnop OpRISCV64SLL OpRISCV64SLLW OpRISCV64SRA OpRISCV64SRAW OpRISCV64SRL OpRISCV64SRLW OpRISCV64SLLI OpRISCV64SLLIW OpRISCV64SRAI OpRISCV64SRAIW OpRISCV64SRLI OpRISCV64SRLIW OpRISCV64SH1ADD OpRISCV64SH2ADD OpRISCV64SH3ADD OpRISCV64AND OpRISCV64ANDN OpRISCV64ANDI OpRISCV64CLZ OpRISCV64CLZW OpRISCV64CPOP OpRISCV64CPOPW OpRISCV64CTZ OpRISCV64CTZW OpRISCV64NOT OpRISCV64OR OpRISCV64ORN OpRISCV64ORI OpRISCV64REV8 OpRISCV64ROL OpRISCV64ROLW OpRISCV64ROR OpRISCV64RORI OpRISCV64RORIW OpRISCV64RORW OpRISCV64XNOR OpRISCV64XOR OpRISCV64XORI OpRISCV64MIN OpRISCV64MAX OpRISCV64MINU OpRISCV64MAXU OpRISCV64SEQZ OpRISCV64SNEZ OpRISCV64SLT OpRISCV64SLTI OpRISCV64SLTU OpRISCV64SLTIU OpRISCV64LoweredRound32F OpRISCV64LoweredRound64F OpRISCV64CALLstatic OpRISCV64CALLtail OpRISCV64CALLclosure OpRISCV64CALLinter OpRISCV64DUFFZERO OpRISCV64DUFFCOPY OpRISCV64LoweredZero OpRISCV64LoweredMove OpRISCV64LoweredAtomicLoad8 OpRISCV64LoweredAtomicLoad32 OpRISCV64LoweredAtomicLoad64 OpRISCV64LoweredAtomicStore8 OpRISCV64LoweredAtomicStore32 OpRISCV64LoweredAtomicStore64 OpRISCV64LoweredAtomicExchange32 OpRISCV64LoweredAtomicExchange64 OpRISCV64LoweredAtomicAdd32 OpRISCV64LoweredAtomicAdd64 OpRISCV64LoweredAtomicCas32 OpRISCV64LoweredAtomicCas64 OpRISCV64LoweredAtomicAnd32 OpRISCV64LoweredAtomicOr32 OpRISCV64LoweredNilCheck OpRISCV64LoweredGetClosurePtr OpRISCV64LoweredGetCallerSP OpRISCV64LoweredGetCallerPC OpRISCV64LoweredWB OpRISCV64LoweredPubBarrier OpRISCV64LoweredPanicBoundsA OpRISCV64LoweredPanicBoundsB OpRISCV64LoweredPanicBoundsC OpRISCV64FADDS OpRISCV64FSUBS OpRISCV64FMULS OpRISCV64FDIVS OpRISCV64FMADDS OpRISCV64FMSUBS OpRISCV64FNMADDS OpRISCV64FNMSUBS OpRISCV64FSQRTS OpRISCV64FNEGS OpRISCV64FMVSX OpRISCV64FCVTSW OpRISCV64FCVTSL OpRISCV64FCVTWS OpRISCV64FCVTLS OpRISCV64FMOVWload OpRISCV64FMOVWstore OpRISCV64FEQS OpRISCV64FNES OpRISCV64FLTS OpRISCV64FLES OpRISCV64LoweredFMAXS OpRISCV64LoweredFMINS OpRISCV64FADDD OpRISCV64FSUBD OpRISCV64FMULD OpRISCV64FDIVD OpRISCV64FMADDD OpRISCV64FMSUBD OpRISCV64FNMADDD OpRISCV64FNMSUBD OpRISCV64FSQRTD OpRISCV64FNEGD OpRISCV64FABSD OpRISCV64FSGNJD OpRISCV64FMVDX OpRISCV64FCVTDW OpRISCV64FCVTDL OpRISCV64FCVTWD OpRISCV64FCVTLD OpRISCV64FCVTDS OpRISCV64FCVTSD OpRISCV64FMOVDload OpRISCV64FMOVDstore OpRISCV64FEQD OpRISCV64FNED OpRISCV64FLTD OpRISCV64FLED OpRISCV64LoweredFMIND OpRISCV64LoweredFMAXD OpS390XFADDS OpS390XFADD OpS390XFSUBS OpS390XFSUB OpS390XFMULS OpS390XFMUL OpS390XFDIVS OpS390XFDIV OpS390XFNEGS OpS390XFNEG OpS390XFMADDS OpS390XFMADD OpS390XFMSUBS OpS390XFMSUB OpS390XLPDFR OpS390XLNDFR OpS390XCPSDR OpS390XFIDBR OpS390XFMOVSload OpS390XFMOVDload OpS390XFMOVSconst OpS390XFMOVDconst OpS390XFMOVSloadidx OpS390XFMOVDloadidx OpS390XFMOVSstore OpS390XFMOVDstore OpS390XFMOVSstoreidx OpS390XFMOVDstoreidx OpS390XADD OpS390XADDW OpS390XADDconst OpS390XADDWconst OpS390XADDload OpS390XADDWload OpS390XSUB OpS390XSUBW OpS390XSUBconst OpS390XSUBWconst OpS390XSUBload OpS390XSUBWload OpS390XMULLD OpS390XMULLW OpS390XMULLDconst OpS390XMULLWconst OpS390XMULLDload OpS390XMULLWload OpS390XMULHD OpS390XMULHDU OpS390XDIVD OpS390XDIVW OpS390XDIVDU OpS390XDIVWU OpS390XMODD OpS390XMODW OpS390XMODDU OpS390XMODWU OpS390XAND OpS390XANDW OpS390XANDconst OpS390XANDWconst OpS390XANDload OpS390XANDWload OpS390XOR OpS390XORW OpS390XORconst OpS390XORWconst OpS390XORload OpS390XORWload OpS390XXOR OpS390XXORW OpS390XXORconst OpS390XXORWconst OpS390XXORload OpS390XXORWload OpS390XADDC OpS390XADDCconst OpS390XADDE OpS390XSUBC OpS390XSUBE OpS390XCMP OpS390XCMPW OpS390XCMPU OpS390XCMPWU OpS390XCMPconst OpS390XCMPWconst OpS390XCMPUconst OpS390XCMPWUconst OpS390XFCMPS OpS390XFCMP OpS390XLTDBR OpS390XLTEBR OpS390XSLD OpS390XSLW OpS390XSLDconst OpS390XSLWconst OpS390XSRD OpS390XSRW OpS390XSRDconst OpS390XSRWconst OpS390XSRAD OpS390XSRAW OpS390XSRADconst OpS390XSRAWconst OpS390XRLLG OpS390XRLL OpS390XRLLconst OpS390XRXSBG OpS390XRISBGZ OpS390XNEG OpS390XNEGW OpS390XNOT OpS390XNOTW OpS390XFSQRT OpS390XFSQRTS OpS390XLOCGR OpS390XMOVBreg OpS390XMOVBZreg OpS390XMOVHreg OpS390XMOVHZreg OpS390XMOVWreg OpS390XMOVWZreg OpS390XMOVDconst OpS390XLDGR OpS390XLGDR OpS390XCFDBRA OpS390XCGDBRA OpS390XCFEBRA OpS390XCGEBRA OpS390XCEFBRA OpS390XCDFBRA OpS390XCEGBRA OpS390XCDGBRA OpS390XCLFEBR OpS390XCLFDBR OpS390XCLGEBR OpS390XCLGDBR OpS390XCELFBR OpS390XCDLFBR OpS390XCELGBR OpS390XCDLGBR OpS390XLEDBR OpS390XLDEBR OpS390XMOVDaddr OpS390XMOVDaddridx OpS390XMOVBZload OpS390XMOVBload OpS390XMOVHZload OpS390XMOVHload OpS390XMOVWZload OpS390XMOVWload OpS390XMOVDload OpS390XMOVWBR OpS390XMOVDBR OpS390XMOVHBRload OpS390XMOVWBRload OpS390XMOVDBRload OpS390XMOVBstore OpS390XMOVHstore OpS390XMOVWstore OpS390XMOVDstore OpS390XMOVHBRstore OpS390XMOVWBRstore OpS390XMOVDBRstore OpS390XMVC OpS390XMOVBZloadidx OpS390XMOVBloadidx OpS390XMOVHZloadidx OpS390XMOVHloadidx OpS390XMOVWZloadidx OpS390XMOVWloadidx OpS390XMOVDloadidx OpS390XMOVHBRloadidx OpS390XMOVWBRloadidx OpS390XMOVDBRloadidx OpS390XMOVBstoreidx OpS390XMOVHstoreidx OpS390XMOVWstoreidx OpS390XMOVDstoreidx OpS390XMOVHBRstoreidx OpS390XMOVWBRstoreidx OpS390XMOVDBRstoreidx OpS390XMOVBstoreconst OpS390XMOVHstoreconst OpS390XMOVWstoreconst OpS390XMOVDstoreconst OpS390XCLEAR OpS390XCALLstatic OpS390XCALLtail OpS390XCALLclosure OpS390XCALLinter OpS390XInvertFlags OpS390XLoweredGetG OpS390XLoweredGetClosurePtr OpS390XLoweredGetCallerSP OpS390XLoweredGetCallerPC OpS390XLoweredNilCheck OpS390XLoweredRound32F OpS390XLoweredRound64F OpS390XLoweredWB OpS390XLoweredPanicBoundsA OpS390XLoweredPanicBoundsB OpS390XLoweredPanicBoundsC OpS390XFlagEQ OpS390XFlagLT OpS390XFlagGT OpS390XFlagOV OpS390XSYNC OpS390XMOVBZatomicload OpS390XMOVWZatomicload OpS390XMOVDatomicload OpS390XMOVBatomicstore OpS390XMOVWatomicstore OpS390XMOVDatomicstore OpS390XLAA OpS390XLAAG OpS390XAddTupleFirst32 OpS390XAddTupleFirst64 OpS390XLAN OpS390XLANfloor OpS390XLAO OpS390XLAOfloor OpS390XLoweredAtomicCas32 OpS390XLoweredAtomicCas64 OpS390XLoweredAtomicExchange32 OpS390XLoweredAtomicExchange64 OpS390XFLOGR OpS390XPOPCNT OpS390XMLGR OpS390XSumBytes2 OpS390XSumBytes4 OpS390XSumBytes8 OpS390XSTMG2 OpS390XSTMG3 OpS390XSTMG4 OpS390XSTM2 OpS390XSTM3 OpS390XSTM4 OpS390XLoweredMove OpS390XLoweredZero OpWasmLoweredStaticCall OpWasmLoweredTailCall OpWasmLoweredClosureCall OpWasmLoweredInterCall OpWasmLoweredAddr OpWasmLoweredMove OpWasmLoweredZero OpWasmLoweredGetClosurePtr OpWasmLoweredGetCallerPC OpWasmLoweredGetCallerSP OpWasmLoweredNilCheck OpWasmLoweredWB OpWasmLoweredConvert OpWasmSelect OpWasmI64Load8U OpWasmI64Load8S OpWasmI64Load16U OpWasmI64Load16S OpWasmI64Load32U OpWasmI64Load32S OpWasmI64Load OpWasmI64Store8 OpWasmI64Store16 OpWasmI64Store32 OpWasmI64Store OpWasmF32Load OpWasmF64Load OpWasmF32Store OpWasmF64Store OpWasmI64Const OpWasmF32Const OpWasmF64Const OpWasmI64Eqz OpWasmI64Eq OpWasmI64Ne OpWasmI64LtS OpWasmI64LtU OpWasmI64GtS OpWasmI64GtU OpWasmI64LeS OpWasmI64LeU OpWasmI64GeS OpWasmI64GeU OpWasmF32Eq OpWasmF32Ne OpWasmF32Lt OpWasmF32Gt OpWasmF32Le OpWasmF32Ge OpWasmF64Eq OpWasmF64Ne OpWasmF64Lt OpWasmF64Gt OpWasmF64Le OpWasmF64Ge OpWasmI64Add OpWasmI64AddConst OpWasmI64Sub OpWasmI64Mul OpWasmI64DivS OpWasmI64DivU OpWasmI64RemS OpWasmI64RemU OpWasmI64And OpWasmI64Or OpWasmI64Xor OpWasmI64Shl OpWasmI64ShrS OpWasmI64ShrU OpWasmF32Neg OpWasmF32Add OpWasmF32Sub OpWasmF32Mul OpWasmF32Div OpWasmF64Neg OpWasmF64Add OpWasmF64Sub OpWasmF64Mul OpWasmF64Div OpWasmI64TruncSatF64S OpWasmI64TruncSatF64U OpWasmI64TruncSatF32S OpWasmI64TruncSatF32U OpWasmF32ConvertI64S OpWasmF32ConvertI64U OpWasmF64ConvertI64S OpWasmF64ConvertI64U OpWasmF32DemoteF64 OpWasmF64PromoteF32 OpWasmI64Extend8S OpWasmI64Extend16S OpWasmI64Extend32S OpWasmF32Sqrt OpWasmF32Trunc OpWasmF32Ceil OpWasmF32Floor OpWasmF32Nearest OpWasmF32Abs OpWasmF32Copysign OpWasmF64Sqrt OpWasmF64Trunc OpWasmF64Ceil OpWasmF64Floor OpWasmF64Nearest OpWasmF64Abs OpWasmF64Copysign OpWasmI64Ctz OpWasmI64Clz OpWasmI32Rotl OpWasmI64Rotl OpWasmI64Popcnt OpAdd8 OpAdd16 OpAdd32 OpAdd64 OpAddPtr OpAdd32F OpAdd64F OpSub8 OpSub16 OpSub32 OpSub64 OpSubPtr OpSub32F OpSub64F OpMul8 OpMul16 OpMul32 OpMul64 OpMul32F OpMul64F OpDiv32F OpDiv64F OpHmul32 OpHmul32u OpHmul64 OpHmul64u OpMul32uhilo OpMul64uhilo OpMul32uover OpMul64uover OpAvg32u OpAvg64u OpDiv8 OpDiv8u OpDiv16 OpDiv16u OpDiv32 OpDiv32u OpDiv64 OpDiv64u OpDiv128u OpMod8 OpMod8u OpMod16 OpMod16u OpMod32 OpMod32u OpMod64 OpMod64u OpAnd8 OpAnd16 OpAnd32 OpAnd64 OpOr8 OpOr16 OpOr32 OpOr64 OpXor8 OpXor16 OpXor32 OpXor64 OpLsh8x8 OpLsh8x16 OpLsh8x32 OpLsh8x64 OpLsh16x8 OpLsh16x16 OpLsh16x32 OpLsh16x64 OpLsh32x8 OpLsh32x16 OpLsh32x32 OpLsh32x64 OpLsh64x8 OpLsh64x16 OpLsh64x32 OpLsh64x64 OpRsh8x8 OpRsh8x16 OpRsh8x32 OpRsh8x64 OpRsh16x8 OpRsh16x16 OpRsh16x32 OpRsh16x64 OpRsh32x8 OpRsh32x16 OpRsh32x32 OpRsh32x64 OpRsh64x8 OpRsh64x16 OpRsh64x32 OpRsh64x64 OpRsh8Ux8 OpRsh8Ux16 OpRsh8Ux32 OpRsh8Ux64 OpRsh16Ux8 OpRsh16Ux16 OpRsh16Ux32 OpRsh16Ux64 OpRsh32Ux8 OpRsh32Ux16 OpRsh32Ux32 OpRsh32Ux64 OpRsh64Ux8 OpRsh64Ux16 OpRsh64Ux32 OpRsh64Ux64 OpEq8 OpEq16 OpEq32 OpEq64 OpEqPtr OpEqInter OpEqSlice OpEq32F OpEq64F OpNeq8 OpNeq16 OpNeq32 OpNeq64 OpNeqPtr OpNeqInter OpNeqSlice OpNeq32F OpNeq64F OpLess8 OpLess8U OpLess16 OpLess16U OpLess32 OpLess32U OpLess64 OpLess64U OpLess32F OpLess64F OpLeq8 OpLeq8U OpLeq16 OpLeq16U OpLeq32 OpLeq32U OpLeq64 OpLeq64U OpLeq32F OpLeq64F OpCondSelect OpAndB OpOrB OpEqB OpNeqB OpNot OpNeg8 OpNeg16 OpNeg32 OpNeg64 OpNeg32F OpNeg64F OpCom8 OpCom16 OpCom32 OpCom64 OpCtz8 OpCtz16 OpCtz32 OpCtz64 OpCtz64On32 OpCtz8NonZero OpCtz16NonZero OpCtz32NonZero OpCtz64NonZero OpBitLen8 OpBitLen16 OpBitLen32 OpBitLen64 OpBswap16 OpBswap32 OpBswap64 OpBitRev8 OpBitRev16 OpBitRev32 OpBitRev64 OpPopCount8 OpPopCount16 OpPopCount32 OpPopCount64 OpRotateLeft64 OpRotateLeft32 OpRotateLeft16 OpRotateLeft8 OpSqrt OpSqrt32 OpFloor OpCeil OpTrunc OpRound OpRoundToEven OpAbs OpCopysign OpMin64 OpMax64 OpMin64u OpMax64u OpMin64F OpMin32F OpMax64F OpMax32F OpFMA OpPhi OpCopy OpConvert OpConstBool OpConstString OpConstNil OpConst8 OpConst16 OpConst32 OpConst64 OpConst32F OpConst64F OpConstInterface OpConstSlice OpInitMem OpArg OpArgIntReg OpArgFloatReg OpAddr OpLocalAddr OpSP OpSB OpSPanchored OpLoad OpDereference OpStore OpMove OpZero OpStoreWB OpMoveWB OpZeroWB OpWBend OpWB OpHasCPUFeature OpPanicBounds OpPanicExtend OpClosureCall OpStaticCall OpInterCall OpTailCall OpClosureLECall OpStaticLECall OpInterLECall OpTailLECall OpSignExt8to16 OpSignExt8to32 OpSignExt8to64 OpSignExt16to32 OpSignExt16to64 OpSignExt32to64 OpZeroExt8to16 OpZeroExt8to32 OpZeroExt8to64 OpZeroExt16to32 OpZeroExt16to64 OpZeroExt32to64 OpTrunc16to8 OpTrunc32to8 OpTrunc32to16 OpTrunc64to8 OpTrunc64to16 OpTrunc64to32 OpCvt32to32F OpCvt32to64F OpCvt64to32F OpCvt64to64F OpCvt32Fto32 OpCvt32Fto64 OpCvt64Fto32 OpCvt64Fto64 OpCvt32Fto64F OpCvt64Fto32F OpCvtBoolToUint8 OpRound32F OpRound64F OpIsNonNil OpIsInBounds OpIsSliceInBounds OpNilCheck OpGetG OpGetClosurePtr OpGetCallerPC OpGetCallerSP OpPtrIndex OpOffPtr OpSliceMake OpSlicePtr OpSliceLen OpSliceCap OpSlicePtrUnchecked OpComplexMake OpComplexReal OpComplexImag OpStringMake OpStringPtr OpStringLen OpIMake OpITab OpIData OpStructMake OpStructSelect OpArrayMake0 OpArrayMake1 OpArraySelect OpStoreReg OpLoadReg OpFwdRef OpUnknown OpVarDef OpVarLive OpKeepAlive OpInlMark OpInt64Make OpInt64Hi OpInt64Lo OpAdd32carry OpAdd32withcarry OpSub32carry OpSub32withcarry OpAdd64carry OpSub64borrow OpSignmask OpZeromask OpSlicemask OpSpectreIndex OpSpectreSliceIndex OpCvt32Uto32F OpCvt32Uto64F OpCvt32Fto32U OpCvt64Fto32U OpCvt64Uto32F OpCvt64Uto64F OpCvt32Fto64U OpCvt64Fto64U OpSelect0 OpSelect1 OpMakeTuple OpSelectN OpSelectNAddr OpMakeResult OpAtomicLoad8 OpAtomicLoad32 OpAtomicLoad64 OpAtomicLoadPtr OpAtomicLoadAcq32 OpAtomicLoadAcq64 OpAtomicStore8 OpAtomicStore32 OpAtomicStore64 OpAtomicStorePtrNoWB OpAtomicStoreRel32 OpAtomicStoreRel64 OpAtomicExchange8 OpAtomicExchange32 OpAtomicExchange64 OpAtomicAdd32 OpAtomicAdd64 OpAtomicCompareAndSwap32 OpAtomicCompareAndSwap64 OpAtomicCompareAndSwapRel32 OpAtomicAnd8 OpAtomicOr8 OpAtomicAnd32 OpAtomicOr32 OpAtomicAnd64value OpAtomicAnd32value OpAtomicAnd8value OpAtomicOr64value OpAtomicOr32value OpAtomicOr8value OpAtomicStore8Variant OpAtomicStore32Variant OpAtomicStore64Variant OpAtomicAdd32Variant OpAtomicAdd64Variant OpAtomicExchange8Variant OpAtomicExchange32Variant OpAtomicExchange64Variant OpAtomicCompareAndSwap32Variant OpAtomicCompareAndSwap64Variant OpAtomicAnd64valueVariant OpAtomicOr64valueVariant OpAtomicAnd32valueVariant OpAtomicOr32valueVariant OpAtomicAnd8valueVariant OpAtomicOr8valueVariant OpPubBarrier OpClobber OpClobberReg OpPrefetchCache OpPrefetchCacheStreamed ) var opcodeTable = [...]opInfo{ {name: "OpInvalid"}, { name: "ADDSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSS", argLen: 2, resultInArg0: true, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSD", argLen: 2, resultInArg0: true, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSS", argLen: 2, resultInArg0: true, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSD", argLen: 2, resultInArg0: true, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: x86.AMOVSS, reg: regInfo{ outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: x86.AMOVSD, reg: regInfo{ outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSSstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSSstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 239}, // AX CX DX BX BP SI DI {0, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLcarry", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADCL", argLen: 3, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AADCL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADCLconst", auxType: auxInt32, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AADCL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLcarry", argLen: 2, resultInArg0: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SBBL", argLen: 3, resultInArg0: true, clobberFlags: true, asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SBBLconst", auxType: auxInt32, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AIMUL3L, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "HMULL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULLU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MULLQU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 4}, // DX {1, 1}, // AX }, }, }, { name: "AVGLU", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "DIVL", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVW", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "MODL", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODW", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "ANDL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CMPL", argLen: 2, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPW", argLen: 2, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPB", argLen: 2, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPLconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPWconst", auxType: auxInt16, argLen: 1, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPBconst", auxType: auxInt8, argLen: 1, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPWload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPBload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPLconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPWconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPBconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "UCOMISS", argLen: 2, asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "UCOMISD", argLen: 2, asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "TESTL", argLen: 2, commutative: true, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTW", argLen: 2, commutative: true, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTB", argLen: 2, commutative: true, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTLconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTWconst", auxType: auxInt16, argLen: 1, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTBconst", auxType: auxInt8, argLen: 1, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "SHLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "NEGL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "NOTL", argLen: 1, resultInArg0: true, asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSFL", argLen: 1, clobberFlags: true, asm: x86.ABSFL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSFW", argLen: 1, clobberFlags: true, asm: x86.ABSFW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredCtz32", argLen: 1, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredCtz64", argLen: 2, resultNotInArgs: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSRL", argLen: 1, clobberFlags: true, asm: x86.ABSRL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSRW", argLen: 1, clobberFlags: true, asm: x86.ABSRW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSWAPL", argLen: 1, resultInArg0: true, asm: x86.ABSWAPL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SQRTSD", argLen: 1, asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SQRTSS", argLen: 1, asm: x86.ASQRTSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SBBLcarrymask", argLen: 1, asm: x86.ASBBL, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETEQ", argLen: 1, asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETNE", argLen: 1, asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETL", argLen: 1, asm: x86.ASETLT, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETLE", argLen: 1, asm: x86.ASETLE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETG", argLen: 1, asm: x86.ASETGT, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGE", argLen: 1, asm: x86.ASETGE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETB", argLen: 1, asm: x86.ASETCS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETBE", argLen: 1, asm: x86.ASETLS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETA", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETAE", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETO", argLen: 1, asm: x86.ASETOS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETEQF", argLen: 1, clobberFlags: true, asm: x86.ASETEQ, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 238}, // CX DX BX BP SI DI }, }, }, { name: "SETNEF", argLen: 1, clobberFlags: true, asm: x86.ASETNE, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 238}, // CX DX BX BP SI DI }, }, }, { name: "SETORD", argLen: 1, asm: x86.ASETPC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETNAN", argLen: 1, asm: x86.ASETPS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGF", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGEF", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLSX", argLen: 1, asm: x86.AMOVBLSX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLZX", argLen: 1, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLSX", argLen: 1, asm: x86.AMOVWLSX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLZX", argLen: 1, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: x86.AMOVL, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTTSD2SL", argLen: 1, asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTTSS2SL", argLen: 1, asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTSL2SS", argLen: 1, asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSL2SD", argLen: 1, asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSD2SS", argLen: 1, asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSS2SD", argLen: 1, asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "PXOR", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "LEAL", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBLSX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWLSX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "SUBLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "SUBLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWloadidx2", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreidx2", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconstidx2", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconstidx4", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "REPSTOSL", argLen: 4, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 2}, // CX {2, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4}, // DX {0, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI }, clobbers: 194, // CX SI DI }, }, { name: "REPMOVSL", argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI {2, 2}, // CX }, clobbers: 194, // CX SI DI }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 65280, // X0 X1 X2 X3 X4 X5 X6 X7 outputs: []outputInfo{ {0, 128}, // DI }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // DX {1, 8}, // BX }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // CX {1, 4}, // DX }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 2}, // CX }, }, }, { name: "LoweredPanicExtendA", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // SI {1, 4}, // DX {2, 8}, // BX }, }, }, { name: "LoweredPanicExtendB", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // SI {1, 2}, // CX {2, 4}, // DX }, }, }, { name: "LoweredPanicExtendC", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // SI {1, 1}, // AX {2, 2}, // CX }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_ULT", argLen: 0, reg: regInfo{}, }, { name: "MOVSSconst1", auxType: auxFloat32, argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVSDconst1", auxType: auxFloat64, argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVSSconst2", argLen: 1, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDconst2", argLen: 1, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSS", argLen: 2, resultInArg0: true, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSD", argLen: 2, resultInArg0: true, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSS", argLen: 2, resultInArg0: true, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSD", argLen: 2, resultInArg0: true, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: x86.AMOVSS, reg: regInfo{ outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: x86.AMOVSD, reg: regInfo{ outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSSstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSSstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSDstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSDstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "ADDSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDQ", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULQconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AIMUL3Q, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AIMUL3L, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULLU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 4, // DX outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "MULQU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 4, // DX outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "HMULQ", argLen: 2, clobberFlags: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULL", argLen: 2, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULQU", argLen: 2, clobberFlags: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULLU", argLen: 2, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "AVGQU", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "DIVQ", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVL", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVW", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVQU", argLen: 2, clobberFlags: true, asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "NEGLflags", argLen: 1, resultInArg0: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQcarry", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADCQ", argLen: 3, commutative: true, resultInArg0: true, asm: x86.AADCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADCQconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: x86.AADCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQborrow", argLen: 2, resultInArg0: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SBBQ", argLen: 3, resultInArg0: true, asm: x86.ASBBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQconstborrow", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SBBQconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: x86.ASBBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULQU2", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 4}, // DX {1, 1}, // AX }, }, }, { name: "DIVQU2", argLen: 3, clobberFlags: true, asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // DX {1, 1}, // AX {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "ANDQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQ", argLen: 2, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPL", argLen: 2, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPW", argLen: 2, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPB", argLen: 2, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPQconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPLconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPWconst", auxType: auxInt16, argLen: 1, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPBconst", auxType: auxInt8, argLen: 1, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQloadidx8", auxType: auxSymOff, argLen: 4, symEffect: SymRead, asm: x86.ACMPQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLloadidx4", auxType: auxSymOff, argLen: 4, symEffect: SymRead, asm: x86.ACMPL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWloadidx2", auxType: auxSymOff, argLen: 4, symEffect: SymRead, asm: x86.ACMPW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQconstloadidx8", auxType: auxSymValAndOff, argLen: 3, symEffect: SymRead, asm: x86.ACMPQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLconstloadidx4", auxType: auxSymValAndOff, argLen: 3, symEffect: SymRead, asm: x86.ACMPL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWconstloadidx2", auxType: auxSymValAndOff, argLen: 3, symEffect: SymRead, asm: x86.ACMPW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "UCOMISS", argLen: 2, asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "UCOMISD", argLen: 2, asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "BTL", argLen: 2, asm: x86.ABTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTQ", argLen: 2, asm: x86.ABTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTCL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTSL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTLconst", auxType: auxInt8, argLen: 1, asm: x86.ABTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTQconst", auxType: auxInt8, argLen: 1, asm: x86.ABTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "BTRQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "BTCQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "TESTQ", argLen: 2, commutative: true, asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTL", argLen: 2, commutative: true, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTW", argLen: 2, commutative: true, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTB", argLen: 2, commutative: true, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTQconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTLconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTWconst", auxType: auxInt16, argLen: 1, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTBconst", auxType: auxInt8, argLen: 1, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRWconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARWconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRDQ", argLen: 3, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {2, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLDQ", argLen: 3, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {2, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLWconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "NEGQ", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "NEGL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "NOTQ", argLen: 1, resultInArg0: true, asm: x86.ANOTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "NOTL", argLen: 1, resultInArg0: true, asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSFQ", argLen: 1, asm: x86.ABSFQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSFL", argLen: 1, clobberFlags: true, asm: x86.ABSFL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSRQ", argLen: 1, asm: x86.ABSRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSRL", argLen: 1, clobberFlags: true, asm: x86.ABSRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQEQ", argLen: 3, resultInArg0: true, asm: x86.ACMOVQEQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQNE", argLen: 3, resultInArg0: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQLT", argLen: 3, resultInArg0: true, asm: x86.ACMOVQLT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGT", argLen: 3, resultInArg0: true, asm: x86.ACMOVQGT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQLE", argLen: 3, resultInArg0: true, asm: x86.ACMOVQLE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGE", argLen: 3, resultInArg0: true, asm: x86.ACMOVQGE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQLS", argLen: 3, resultInArg0: true, asm: x86.ACMOVQLS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQHI", argLen: 3, resultInArg0: true, asm: x86.ACMOVQHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQCC", argLen: 3, resultInArg0: true, asm: x86.ACMOVQCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQCS", argLen: 3, resultInArg0: true, asm: x86.ACMOVQCS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLEQ", argLen: 3, resultInArg0: true, asm: x86.ACMOVLEQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLNE", argLen: 3, resultInArg0: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLLT", argLen: 3, resultInArg0: true, asm: x86.ACMOVLLT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGT", argLen: 3, resultInArg0: true, asm: x86.ACMOVLGT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLLE", argLen: 3, resultInArg0: true, asm: x86.ACMOVLLE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGE", argLen: 3, resultInArg0: true, asm: x86.ACMOVLGE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLLS", argLen: 3, resultInArg0: true, asm: x86.ACMOVLLS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLHI", argLen: 3, resultInArg0: true, asm: x86.ACMOVLHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLCC", argLen: 3, resultInArg0: true, asm: x86.ACMOVLCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLCS", argLen: 3, resultInArg0: true, asm: x86.ACMOVLCS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWEQ", argLen: 3, resultInArg0: true, asm: x86.ACMOVWEQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWNE", argLen: 3, resultInArg0: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWLT", argLen: 3, resultInArg0: true, asm: x86.ACMOVWLT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGT", argLen: 3, resultInArg0: true, asm: x86.ACMOVWGT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWLE", argLen: 3, resultInArg0: true, asm: x86.ACMOVWLE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGE", argLen: 3, resultInArg0: true, asm: x86.ACMOVWGE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWLS", argLen: 3, resultInArg0: true, asm: x86.ACMOVWLS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWHI", argLen: 3, resultInArg0: true, asm: x86.ACMOVWHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWCC", argLen: 3, resultInArg0: true, asm: x86.ACMOVWCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWCS", argLen: 3, resultInArg0: true, asm: x86.ACMOVWCS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQEQF", argLen: 3, resultInArg0: true, needIntTemp: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQNEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGTF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLEQF", argLen: 3, resultInArg0: true, needIntTemp: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLNEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGTF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWEQF", argLen: 3, resultInArg0: true, needIntTemp: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWNEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGTF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSWAPQ", argLen: 1, resultInArg0: true, asm: x86.ABSWAPQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSWAPL", argLen: 1, resultInArg0: true, asm: x86.ABSWAPL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "POPCNTQ", argLen: 1, clobberFlags: true, asm: x86.APOPCNTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "POPCNTL", argLen: 1, clobberFlags: true, asm: x86.APOPCNTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SQRTSD", argLen: 1, asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SQRTSS", argLen: 1, asm: x86.ASQRTSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ROUNDSD", auxType: auxInt8, argLen: 1, asm: x86.AROUNDSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "VFMADD231SS", argLen: 3, resultInArg0: true, asm: x86.AVFMADD231SS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "VFMADD231SD", argLen: 3, resultInArg0: true, asm: x86.AVFMADD231SD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MINSD", argLen: 2, resultInArg0: true, asm: x86.AMINSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MINSS", argLen: 2, resultInArg0: true, asm: x86.AMINSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SBBQcarrymask", argLen: 1, asm: x86.ASBBQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SBBLcarrymask", argLen: 1, asm: x86.ASBBL, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETEQ", argLen: 1, asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETNE", argLen: 1, asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETL", argLen: 1, asm: x86.ASETLT, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETLE", argLen: 1, asm: x86.ASETLE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETG", argLen: 1, asm: x86.ASETGT, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETGE", argLen: 1, asm: x86.ASETGE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETB", argLen: 1, asm: x86.ASETCS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETBE", argLen: 1, asm: x86.ASETLS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETA", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETAE", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETO", argLen: 1, asm: x86.ASETOS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETEQstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETEQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETNEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETNE, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETLstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETLT, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETLEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETLE, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETGstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETGT, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETGEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETGE, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETCS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETBEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETLS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETAstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETHI, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETAEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETCC, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETEQstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETEQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETNEstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETNE, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETLstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETLT, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETLEstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETLE, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETGstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETGT, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETGEstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETGE, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETBstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETCS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETBEstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETLS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETAstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETHI, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETAEstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.ASETCC, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETEQF", argLen: 1, clobberFlags: true, needIntTemp: true, asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETNEF", argLen: 1, clobberFlags: true, needIntTemp: true, asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETORD", argLen: 1, asm: x86.ASETPC, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETNAN", argLen: 1, asm: x86.ASETPS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETGF", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETGEF", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBQSX", argLen: 1, asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBQZX", argLen: 1, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWQSX", argLen: 1, asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWQZX", argLen: 1, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLQSX", argLen: 1, asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLQZX", argLen: 1, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: x86.AMOVL, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: x86.AMOVQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSD2SL", argLen: 1, asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSD2SQ", argLen: 1, asm: x86.ACVTTSD2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSS2SL", argLen: 1, asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSS2SQ", argLen: 1, asm: x86.ACVTTSS2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTSL2SS", argLen: 1, asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSL2SD", argLen: 1, asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSQ2SS", argLen: 1, asm: x86.ACVTSQ2SS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSQ2SD", argLen: 1, asm: x86.ACVTSQ2SD, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSD2SS", argLen: 1, asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSS2SD", argLen: 1, asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVQi2f", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVQf2i", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLi2f", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVLf2i", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "PXOR", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "POR", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APOR, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "LEAQ", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: x86.ALEAQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: x86.ALEAL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: x86.ALEAW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, asm: x86.ALEAQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, asm: x86.ALEAL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, asm: x86.ALEAW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAQ, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAL, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAQ, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAW, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAW, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBQSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWQSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLQSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVOload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVOstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVBloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBLZX, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVWLZX, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWloadidx2", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVWLZX, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreidx2", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVOstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreconstidx2", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreconstidx4", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreconstidx8", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI }, clobbers: 128, // DI }, }, { name: "REPSTOSQ", argLen: 4, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 2}, // CX {2, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4}, // DX {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI }, clobbers: 65728, // SI DI X0 }, }, { name: "REPMOVSQ", argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI {2, 2}, // CX }, clobbers: 194, // CX SI DI }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 outputs: []outputInfo{ {0, 2048}, // R11 }, }, }, { name: "LoweredHasCPUFeature", auxType: auxSym, argLen: 0, rematerializeable: true, symEffect: SymNone, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // DX {1, 8}, // BX }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // CX {1, 4}, // DX }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 2}, // CX }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_ULT", argLen: 0, reg: regInfo{}, }, { name: "MOVBatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XCHGB", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXCHGB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XCHGL", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXCHGL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XCHGQ", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXCHGQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XADDLlock", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXADDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XADDQlock", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "AddTupleFirst32", argLen: 2, reg: regInfo{}, }, { name: "AddTupleFirst64", argLen: 2, reg: regInfo{}, }, { name: "CMPXCHGLlock", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.ACMPXCHGL, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // AX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPXCHGQlock", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.ACMPXCHGQ, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // AX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDBlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AANDB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORBlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AORB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "LoweredAtomicAnd64", auxType: auxSymOff, argLen: 3, resultNotInArgs: true, clobberFlags: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, symEffect: SymRdWr, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "LoweredAtomicAnd32", auxType: auxSymOff, argLen: 3, resultNotInArgs: true, clobberFlags: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, symEffect: SymRdWr, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "LoweredAtomicOr64", auxType: auxSymOff, argLen: 3, resultNotInArgs: true, clobberFlags: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, symEffect: SymRdWr, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "LoweredAtomicOr32", auxType: auxSymOff, argLen: 3, resultNotInArgs: true, clobberFlags: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, symEffect: SymRdWr, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "PrefetchT0", argLen: 2, hasSideEffects: true, asm: x86.APREFETCHT0, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "PrefetchNTA", argLen: 2, hasSideEffects: true, asm: x86.APREFETCHNTA, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDNQ", argLen: 2, clobberFlags: true, asm: x86.AANDNQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDNL", argLen: 2, clobberFlags: true, asm: x86.AANDNL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSIQ", argLen: 1, clobberFlags: true, asm: x86.ABLSIQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSIL", argLen: 1, clobberFlags: true, asm: x86.ABLSIL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSMSKQ", argLen: 1, clobberFlags: true, asm: x86.ABLSMSKQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSMSKL", argLen: 1, clobberFlags: true, asm: x86.ABLSMSKL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSRQ", argLen: 1, asm: x86.ABLSRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSRL", argLen: 1, asm: x86.ABLSRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TZCNTQ", argLen: 1, clobberFlags: true, asm: x86.ATZCNTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TZCNTL", argLen: 1, clobberFlags: true, asm: x86.ATZCNTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LZCNTQ", argLen: 1, clobberFlags: true, asm: x86.ALZCNTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LZCNTL", argLen: 1, clobberFlags: true, asm: x86.ALZCNTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVBEW, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBEL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBELstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVBEL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEQload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBEQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEQstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVBEQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBEL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBELloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVBEL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBELloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVBEL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEQloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBEQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEQloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVBEQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEWstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVBEW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEWstoreidx2", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVBEL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEQstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVBEQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEQstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SARXQ", argLen: 2, asm: x86.ASARXQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXL", argLen: 2, asm: x86.ASARXL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQ", argLen: 2, asm: x86.ASHLXQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXL", argLen: 2, asm: x86.ASHLXL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQ", argLen: 2, asm: x86.ASHRXQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXL", argLen: 2, asm: x86.ASHRXL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLloadidx4", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXQloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXQloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLloadidx4", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLloadidx4", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "PUNPCKLBW", argLen: 2, resultInArg0: true, asm: x86.APUNPCKLBW, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "PSHUFLW", auxType: auxInt8, argLen: 1, asm: x86.APSHUFLW, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "PSHUFBbroadcast", argLen: 1, resultInArg0: true, asm: x86.APSHUFB, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "VPBROADCASTB", argLen: 1, asm: x86.AVPBROADCASTB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "PSIGNB", argLen: 2, resultInArg0: true, asm: x86.APSIGNB, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "PCMPEQB", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APCMPEQB, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "PMOVMSKB", argLen: 1, asm: x86.APMOVMSKB, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUB", argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSB", argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBconst", auxType: auxInt32, argLen: 1, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: arm.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "HMUL", argLen: 2, commutative: true, asm: arm.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "HMULU", argLen: 2, commutative: true, asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CALLudiv", argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 1}, // R0 }, clobbers: 20492, // R2 R3 R12 R14 outputs: []outputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "ADDS", argLen: 2, commutative: true, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSconst", auxType: auxInt32, argLen: 1, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADC", argLen: 3, commutative: true, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCconst", auxType: auxInt32, argLen: 2, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBS", argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSconst", auxType: auxInt32, argLen: 1, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSconst", auxType: auxInt32, argLen: 1, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBC", argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCconst", auxType: auxInt32, argLen: 2, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCconst", auxType: auxInt32, argLen: 2, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULLU", argLen: 2, commutative: true, asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULA", argLen: 3, asm: arm.AMULA, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULS", argLen: 3, asm: arm.AMULS, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: arm.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: arm.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SUBF", argLen: 2, asm: arm.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SUBD", argLen: 2, asm: arm.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: arm.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: arm.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "NMULF", argLen: 2, commutative: true, asm: arm.ANMULF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "NMULD", argLen: 2, commutative: true, asm: arm.ANMULD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "DIVF", argLen: 2, asm: arm.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "DIVD", argLen: 2, asm: arm.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULAF", argLen: 3, resultInArg0: true, asm: arm.AMULAF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULAD", argLen: 3, resultInArg0: true, asm: arm.AMULAD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULSF", argLen: 3, resultInArg0: true, asm: arm.AMULSF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULSD", argLen: 3, resultInArg0: true, asm: arm.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMULAD", argLen: 3, resultInArg0: true, asm: arm.AFMULAD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDconst", auxType: auxInt32, argLen: 1, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORconst", auxType: auxInt32, argLen: 1, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORconst", auxType: auxInt32, argLen: 1, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BIC", argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICconst", auxType: auxInt32, argLen: 1, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BFX", auxType: auxInt32, argLen: 1, asm: arm.ABFX, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BFXU", auxType: auxInt32, argLen: 1, asm: arm.ABFXU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVN", argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "NEGF", argLen: 1, asm: arm.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "NEGD", argLen: 1, asm: arm.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SQRTD", argLen: 1, asm: arm.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SQRTF", argLen: 1, asm: arm.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ABSD", argLen: 1, asm: arm.AABSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CLZ", argLen: 1, asm: arm.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "REV", argLen: 1, asm: arm.AREV, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "REV16", argLen: 1, asm: arm.AREV16, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RBIT", argLen: 1, asm: arm.ARBIT, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SLL", argLen: 2, asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SLLconst", auxType: auxInt32, argLen: 1, asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRL", argLen: 2, asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRLconst", auxType: auxInt32, argLen: 1, asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRA", argLen: 2, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRAconst", auxType: auxInt32, argLen: 1, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRR", argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRRconst", auxType: auxInt32, argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRR", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftLL", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRL", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRA", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftLLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRAreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftLLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRAreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftLLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRAreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftLLreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRLreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRAreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftLLreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRLreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRAreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftLLreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRLreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRAreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftLLreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRLreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRAreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftLLreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRLreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRAreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftLLreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRLreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRAreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftLLreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRLreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRAreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftLLreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRLreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRAreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftLLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRAreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftLLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRAreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftLLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRAreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMP", argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPconst", auxType: auxInt32, argLen: 1, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMN", argLen: 2, commutative: true, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNconst", auxType: auxInt32, argLen: 1, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TST", argLen: 2, commutative: true, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTconst", auxType: auxInt32, argLen: 1, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQ", argLen: 2, commutative: true, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQconst", auxType: auxInt32, argLen: 1, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPF", argLen: 2, asm: arm.ACMPF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPD", argLen: 2, asm: arm.ACMPD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPshiftLLreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMPshiftRLreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMPshiftRAreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMNshiftLLreg", argLen: 3, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMNshiftRLreg", argLen: 3, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMNshiftRAreg", argLen: 3, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TSTshiftLLreg", argLen: 3, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TSTshiftRLreg", argLen: 3, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TSTshiftRAreg", argLen: 3, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TEQshiftLLreg", argLen: 3, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TEQshiftRLreg", argLen: 3, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TEQshiftRAreg", argLen: 3, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMPF0", argLen: 1, asm: arm.ACMPF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPD0", argLen: 1, asm: arm.ACMPD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: arm.AMOVW, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4294975488}, // SP SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWloadshiftLL", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWloadshiftRL", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWloadshiftRA", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBUloadidx", argLen: 3, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBloadidx", argLen: 3, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHUloadidx", argLen: 3, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstoreshiftLL", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstoreshiftRL", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstoreshiftRA", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVBreg", argLen: 1, asm: arm.AMOVBS, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBUreg", argLen: 1, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHreg", argLen: 1, asm: arm.AMOVHS, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHUreg", argLen: 1, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWreg", argLen: 1, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWF", argLen: 1, asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWD", argLen: 1, asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWUF", argLen: 1, asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWUD", argLen: 1, asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVFW", argLen: 1, asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVDW", argLen: 1, asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFWU", argLen: 1, asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVDWU", argLen: 1, asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFD", argLen: 1, asm: arm.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDF", argLen: 1, asm: arm.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMOVWHSconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMOVWLSconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRAcond", argLen: 3, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 128}, // R7 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 }, clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 1}, // R0 }, clobbers: 20482, // R1 R12 R14 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 }, clobbers: 20487, // R0 R1 R2 R12 R14 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2, // R1 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 6, // R1 R2 }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 128}, // R7 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "LoweredPanicExtendA", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 4}, // R2 {2, 8}, // R3 }, }, }, { name: "LoweredPanicExtendB", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 2}, // R1 {2, 4}, // R2 }, }, }, { name: "LoweredPanicExtendC", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 1}, // R0 {2, 2}, // R1 }, }, }, { name: "FlagConstant", auxType: auxFlagConstant, argLen: 0, reg: regInfo{}, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 outputs: []outputInfo{ {0, 256}, // R8 }, }, }, { name: "ADCSflags", argLen: 3, commutative: true, asm: arm64.AADCS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADCzerocarry", argLen: 1, asm: arm64.AADC, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDconst", auxType: auxInt64, argLen: 1, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1476395007}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDSconstflags", auxType: auxInt64, argLen: 1, asm: arm64.AADDS, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {1, 0}, {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDSflags", argLen: 2, commutative: true, asm: arm64.AADDS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUB", argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBconst", auxType: auxInt64, argLen: 1, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SBCSflags", argLen: 3, asm: arm64.ASBCS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBSflags", argLen: 2, asm: arm64.ASUBS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: arm64.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MULW", argLen: 2, commutative: true, asm: arm64.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MNEG", argLen: 2, commutative: true, asm: arm64.AMNEG, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MNEGW", argLen: 2, commutative: true, asm: arm64.AMNEGW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MULH", argLen: 2, commutative: true, asm: arm64.ASMULH, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMULH", argLen: 2, commutative: true, asm: arm64.AUMULH, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MULL", argLen: 2, commutative: true, asm: arm64.ASMULL, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMULL", argLen: 2, commutative: true, asm: arm64.AUMULL, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "DIV", argLen: 2, asm: arm64.ASDIV, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UDIV", argLen: 2, asm: arm64.AUDIV, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "DIVW", argLen: 2, asm: arm64.ASDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UDIVW", argLen: 2, asm: arm64.AUDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOD", argLen: 2, asm: arm64.AREM, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMOD", argLen: 2, asm: arm64.AUREM, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MODW", argLen: 2, asm: arm64.AREMW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMODW", argLen: 2, asm: arm64.AUREMW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: arm64.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FADDD", argLen: 2, commutative: true, asm: arm64.AFADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBS", argLen: 2, asm: arm64.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBD", argLen: 2, asm: arm64.AFSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: arm64.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULD", argLen: 2, commutative: true, asm: arm64.AFMULD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMULS", argLen: 2, commutative: true, asm: arm64.AFNMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMULD", argLen: 2, commutative: true, asm: arm64.AFNMULD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVS", argLen: 2, asm: arm64.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVD", argLen: 2, asm: arm64.AFDIVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BIC", argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EON", argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORN", argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVN", argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEG", argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGSflags", argLen: 1, asm: arm64.ANEGS, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {1, 0}, {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NGCzerocarry", argLen: 1, asm: arm64.ANGC, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FABSD", argLen: 1, asm: arm64.AFABSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGS", argLen: 1, asm: arm64.AFNEGS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGD", argLen: 1, asm: arm64.AFNEGD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTD", argLen: 1, asm: arm64.AFSQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTS", argLen: 1, asm: arm64.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMIND", argLen: 2, asm: arm64.AFMIND, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMINS", argLen: 2, asm: arm64.AFMINS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMAXD", argLen: 2, asm: arm64.AFMAXD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMAXS", argLen: 2, asm: arm64.AFMAXS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "REV", argLen: 1, asm: arm64.AREV, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "REVW", argLen: 1, asm: arm64.AREVW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "REV16", argLen: 1, asm: arm64.AREV16, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "REV16W", argLen: 1, asm: arm64.AREV16W, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RBIT", argLen: 1, asm: arm64.ARBIT, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RBITW", argLen: 1, asm: arm64.ARBITW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CLZ", argLen: 1, asm: arm64.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CLZW", argLen: 1, asm: arm64.ACLZW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "VCNT", argLen: 1, asm: arm64.AVCNT, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "VUADDLV", argLen: 1, asm: arm64.AVUADDLV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDS", argLen: 3, asm: arm64.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDD", argLen: 3, asm: arm64.AFMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDS", argLen: 3, asm: arm64.AFNMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDD", argLen: 3, asm: arm64.AFNMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBS", argLen: 3, asm: arm64.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBD", argLen: 3, asm: arm64.AFMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBS", argLen: 3, asm: arm64.AFNMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBD", argLen: 3, asm: arm64.AFNMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MADD", argLen: 3, asm: arm64.AMADD, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MADDW", argLen: 3, asm: arm64.AMADDW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MSUB", argLen: 3, asm: arm64.AMSUB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MSUBW", argLen: 3, asm: arm64.AMSUBW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SLL", argLen: 2, asm: arm64.ALSL, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SLLconst", auxType: auxInt64, argLen: 1, asm: arm64.ALSL, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRL", argLen: 2, asm: arm64.ALSR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRLconst", auxType: auxInt64, argLen: 1, asm: arm64.ALSR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRA", argLen: 2, asm: arm64.AASR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRAconst", auxType: auxInt64, argLen: 1, asm: arm64.AASR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ROR", argLen: 2, asm: arm64.AROR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RORW", argLen: 2, asm: arm64.ARORW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RORconst", auxType: auxInt64, argLen: 1, asm: arm64.AROR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RORWconst", auxType: auxInt64, argLen: 1, asm: arm64.ARORW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EXTRconst", auxType: auxInt64, argLen: 2, asm: arm64.AEXTR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EXTRWconst", auxType: auxInt64, argLen: 2, asm: arm64.AEXTRW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CMP", argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPconst", auxType: auxInt64, argLen: 1, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPW", argLen: 2, asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMN", argLen: 2, commutative: true, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNconst", auxType: auxInt64, argLen: 1, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNW", argLen: 2, commutative: true, asm: arm64.ACMNW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNWconst", auxType: auxInt32, argLen: 1, asm: arm64.ACMNW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TST", argLen: 2, commutative: true, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTconst", auxType: auxInt64, argLen: 1, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTW", argLen: 2, commutative: true, asm: arm64.ATSTW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTWconst", auxType: auxInt32, argLen: 1, asm: arm64.ATSTW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "FCMPS", argLen: 2, asm: arm64.AFCMPS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCMPD", argLen: 2, asm: arm64.AFCMPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCMPS0", argLen: 1, asm: arm64.AFCMPS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCMPD0", argLen: 1, asm: arm64.AFCMPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MVNshiftLL", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVNshiftRL", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVNshiftRA", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVNshiftRO", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGshiftLL", auxType: auxInt64, argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGshiftRL", auxType: auxInt64, argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGshiftRA", auxType: auxInt64, argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CMPshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "BFI", auxType: auxARM64BitField, argLen: 2, resultInArg0: true, asm: arm64.ABFI, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BFXIL", auxType: auxARM64BitField, argLen: 2, resultInArg0: true, asm: arm64.ABFXIL, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SBFIZ", auxType: auxARM64BitField, argLen: 1, asm: arm64.ASBFIZ, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SBFX", auxType: auxARM64BitField, argLen: 1, asm: arm64.ASBFX, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UBFIZ", auxType: auxARM64BitField, argLen: 1, asm: arm64.AUBFIZ, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UBFX", auxType: auxARM64BitField, argLen: 1, asm: arm64.AUBFX, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: arm64.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm64.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm64.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037928517632}, // SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LDP", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.ALDP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "LDPW", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.ALDPW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "LDPSW", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.ALDPSW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "FLDPD", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AFLDPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FLDPS", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AFLDPS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDloadidx", argLen: 3, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUloadidx", argLen: 3, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUloadidx", argLen: 3, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBloadidx", argLen: 3, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBUloadidx", argLen: 3, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSloadidx", argLen: 3, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDloadidx", argLen: 3, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVHloadidx2", argLen: 3, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUloadidx2", argLen: 3, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWloadidx4", argLen: 3, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUloadidx4", argLen: 3, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDloadidx8", argLen: 3, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSloadidx4", argLen: 3, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDloadidx8", argLen: 3, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "STP", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.ASTP, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "STPW", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.ASTPW, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FSTPD", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AFSTPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSTPS", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AFSTPS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstoreidx", argLen: 4, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVSstoreidx", argLen: 4, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstoreidx", argLen: 4, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVHstoreidx2", argLen: 4, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstoreidx4", argLen: 4, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstoreidx8", argLen: 4, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVSstoreidx4", argLen: 4, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstoreidx8", argLen: 4, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDgpfp", argLen: 1, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDfpgp", argLen: 1, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSgpfp", argLen: 1, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVSfpgp", argLen: 1, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBreg", argLen: 1, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBUreg", argLen: 1, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHreg", argLen: 1, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUreg", argLen: 1, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWreg", argLen: 1, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUreg", argLen: 1, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDreg", argLen: 1, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SCVTFWS", argLen: 1, asm: arm64.ASCVTFWS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SCVTFWD", argLen: 1, asm: arm64.ASCVTFWD, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFWS", argLen: 1, asm: arm64.AUCVTFWS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFWD", argLen: 1, asm: arm64.AUCVTFWD, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SCVTFS", argLen: 1, asm: arm64.ASCVTFS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SCVTFD", argLen: 1, asm: arm64.ASCVTFD, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFS", argLen: 1, asm: arm64.AUCVTFS, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFD", argLen: 1, asm: arm64.AUCVTFD, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTZSSW", argLen: 1, asm: arm64.AFCVTZSSW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZSDW", argLen: 1, asm: arm64.AFCVTZSDW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUSW", argLen: 1, asm: arm64.AFCVTZUSW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUDW", argLen: 1, asm: arm64.AFCVTZUDW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZSS", argLen: 1, asm: arm64.AFCVTZSS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZSD", argLen: 1, asm: arm64.AFCVTZSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUS", argLen: 1, asm: arm64.AFCVTZUS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUD", argLen: 1, asm: arm64.AFCVTZUD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTSD", argLen: 1, asm: arm64.AFCVTSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTDS", argLen: 1, asm: arm64.AFCVTDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTAD", argLen: 1, asm: arm64.AFRINTAD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTMD", argLen: 1, asm: arm64.AFRINTMD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTND", argLen: 1, asm: arm64.AFRINTND, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTPD", argLen: 1, asm: arm64.AFRINTPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTZD", argLen: 1, asm: arm64.AFRINTZD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CSEL", auxType: auxCCop, argLen: 3, asm: arm64.ACSEL, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSEL0", auxType: auxCCop, argLen: 2, asm: arm64.ACSEL, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSINC", auxType: auxCCop, argLen: 3, asm: arm64.ACSINC, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSINV", auxType: auxCCop, argLen: 3, asm: arm64.ACSINV, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSNEG", auxType: auxCCop, argLen: 3, asm: arm64.ACSNEG, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSETM", auxType: auxCCop, argLen: 1, asm: arm64.ACSETM, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 33554432}, // R26 {0, 1409286143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP }, clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotLessThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotLessEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotGreaterThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotGreaterEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThanNoov", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqualNoov", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 524288}, // R20 }, clobbers: 269156352, // R16 R17 R20 R30 }, }, { name: "LoweredZero", argLen: 3, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 65536}, // R16 {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, clobbers: 65536, // R16 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R21 {1, 524288}, // R20 }, clobbers: 303759360, // R16 R17 R20 R21 R26 R30 }, }, { name: "LoweredMove", argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 131072}, // R17 {1, 65536}, // R16 {2, 318767103}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30 }, clobbers: 16973824, // R16 R17 R25 }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 33554432}, // R26 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FlagConstant", auxType: auxFlagConstant, argLen: 0, reg: regInfo{}, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LDAR", argLen: 2, faultOnNilArg0: true, asm: arm64.ALDAR, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LDARB", argLen: 2, faultOnNilArg0: true, asm: arm64.ALDARB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LDARW", argLen: 2, faultOnNilArg0: true, asm: arm64.ALDARW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "STLRB", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: arm64.ASTLRB, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "STLR", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: arm64.ASTLR, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "STLRW", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: arm64.ASTLRW, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange8", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange64Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange8Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd64Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas64Variant", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas32Variant", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd8", argLen: 3, resultNotInArgs: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr8", argLen: 3, resultNotInArgs: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd64", argLen: 3, resultNotInArgs: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr64", argLen: 3, resultNotInArgs: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, resultNotInArgs: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr32", argLen: 3, resultNotInArgs: true, needIntTemp: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd8Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr8Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd64Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr64Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 9223372034975924224, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 outputs: []outputInfo{ {0, 16777216}, // R25 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "PRFM", auxType: auxInt64, argLen: 2, hasSideEffects: true, asm: arm64.APRFM, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "DMB", auxType: auxInt64, argLen: 1, hasSideEffects: true, asm: arm64.ADMB, reg: regInfo{}, }, { name: "ZERO", argLen: 0, zeroWidth: true, fixedReg: true, reg: regInfo{}, }, { name: "NEGV", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "NEGF", argLen: 1, asm: loong64.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "NEGD", argLen: 1, asm: loong64.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTD", argLen: 1, asm: loong64.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTF", argLen: 1, asm: loong64.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "ABSD", argLen: 1, asm: loong64.AABSD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CLZW", argLen: 1, asm: loong64.ACLZW, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "CLZV", argLen: 1, asm: loong64.ACLZV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "CTZW", argLen: 1, asm: loong64.ACTZW, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "CTZV", argLen: 1, asm: loong64.ACTZV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "REVB2H", argLen: 1, asm: loong64.AREVB2H, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "REVB2W", argLen: 1, asm: loong64.AREVB2W, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "REVBV", argLen: 1, asm: loong64.AREVBV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "BITREV4B", argLen: 1, asm: loong64.ABITREV4B, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "BITREVW", argLen: 1, asm: loong64.ABITREVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "BITREVV", argLen: 1, asm: loong64.ABITREVV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "VPCNT64", argLen: 1, asm: loong64.AVPCNTV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "VPCNT32", argLen: 1, asm: loong64.AVPCNTW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "VPCNT16", argLen: 1, asm: loong64.AVPCNTH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "ADDV", argLen: 2, commutative: true, asm: loong64.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ADDVconst", auxType: auxInt64, argLen: 1, asm: loong64.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SUBV", argLen: 2, asm: loong64.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SUBVconst", auxType: auxInt64, argLen: 1, asm: loong64.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MULV", argLen: 2, commutative: true, asm: loong64.AMULV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MULHV", argLen: 2, commutative: true, asm: loong64.AMULHV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MULHVU", argLen: 2, commutative: true, asm: loong64.AMULHVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "DIVV", argLen: 2, asm: loong64.ADIVV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "DIVVU", argLen: 2, asm: loong64.ADIVVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "REMV", argLen: 2, asm: loong64.AREMV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "REMVU", argLen: 2, asm: loong64.AREMVU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: loong64.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: loong64.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBF", argLen: 2, asm: loong64.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBD", argLen: 2, asm: loong64.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: loong64.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: loong64.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVF", argLen: 2, asm: loong64.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVD", argLen: 2, asm: loong64.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: loong64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, asm: loong64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: loong64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: loong64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: loong64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: loong64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: loong64.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "NORconst", auxType: auxInt64, argLen: 1, asm: loong64.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "FMADDF", argLen: 3, commutative: true, asm: loong64.AFMADDF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDD", argLen: 3, commutative: true, asm: loong64.AFMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBF", argLen: 3, commutative: true, asm: loong64.AFMSUBF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBD", argLen: 3, commutative: true, asm: loong64.AFMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDF", argLen: 3, commutative: true, asm: loong64.AFNMADDF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDD", argLen: 3, commutative: true, asm: loong64.AFNMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBF", argLen: 3, commutative: true, asm: loong64.AFNMSUBF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBD", argLen: 3, commutative: true, asm: loong64.AFNMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMINF", argLen: 2, commutative: true, resultNotInArgs: true, asm: loong64.AFMINF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMIND", argLen: 2, commutative: true, resultNotInArgs: true, asm: loong64.AFMIND, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMAXF", argLen: 2, commutative: true, resultNotInArgs: true, asm: loong64.AFMAXF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMAXD", argLen: 2, commutative: true, resultNotInArgs: true, asm: loong64.AFMAXD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MASKEQZ", argLen: 2, asm: loong64.AMASKEQZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MASKNEZ", argLen: 2, asm: loong64.AMASKNEZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "FCOPYSGD", argLen: 2, asm: loong64.AFCOPYSGD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SLL", argLen: 2, asm: loong64.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SLLV", argLen: 2, asm: loong64.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SLLconst", auxType: auxInt64, argLen: 1, asm: loong64.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SLLVconst", auxType: auxInt64, argLen: 1, asm: loong64.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRL", argLen: 2, asm: loong64.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRLV", argLen: 2, asm: loong64.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRLconst", auxType: auxInt64, argLen: 1, asm: loong64.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRLVconst", auxType: auxInt64, argLen: 1, asm: loong64.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRA", argLen: 2, asm: loong64.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRAV", argLen: 2, asm: loong64.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRAconst", auxType: auxInt64, argLen: 1, asm: loong64.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRAVconst", auxType: auxInt64, argLen: 1, asm: loong64.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ROTR", argLen: 2, asm: loong64.AROTR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ROTRV", argLen: 2, asm: loong64.AROTRV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ROTRconst", auxType: auxInt64, argLen: 1, asm: loong64.AROTR, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ROTRVconst", auxType: auxInt64, argLen: 1, asm: loong64.AROTRV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SGT", argLen: 2, asm: loong64.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SGTconst", auxType: auxInt64, argLen: 1, asm: loong64.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SGTU", argLen: 2, asm: loong64.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SGTUconst", auxType: auxInt64, argLen: 1, asm: loong64.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "CMPEQF", argLen: 2, asm: loong64.ACMPEQF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPEQD", argLen: 2, asm: loong64.ACMPEQD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGEF", argLen: 2, asm: loong64.ACMPGEF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGED", argLen: 2, asm: loong64.ACMPGED, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTF", argLen: 2, asm: loong64.ACMPGTF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTD", argLen: 2, asm: loong64.ACMPGTD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "BSTRPICKW", auxType: auxInt64, argLen: 1, asm: loong64.ABSTRPICKW, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "BSTRPICKV", auxType: auxInt64, argLen: 1, asm: loong64.ABSTRPICKV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVVconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: loong64.AMOVV, reg: regInfo{ outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVFconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: loong64.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: loong64.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018427387908}, // SP SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVVload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVloadidx", argLen: 3, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWUloadidx", argLen: 3, asm: loong64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHUloadidx", argLen: 3, asm: loong64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVBloadidx", argLen: 3, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVBUloadidx", argLen: 3, asm: loong64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVFloadidx", argLen: 3, asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDloadidx", argLen: 3, asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVVstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVVstoreidx", argLen: 4, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVFstoreidx", argLen: 4, asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDstoreidx", argLen: 4, asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVVstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVBstorezeroidx", argLen: 3, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVHstorezeroidx", argLen: 3, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVWstorezeroidx", argLen: 3, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVVstorezeroidx", argLen: 3, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVWfpgp", argLen: 1, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWgpfp", argLen: 1, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVfpgp", argLen: 1, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVVgpfp", argLen: 1, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBreg", argLen: 1, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVBUreg", argLen: 1, asm: loong64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHreg", argLen: 1, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHUreg", argLen: 1, asm: loong64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWreg", argLen: 1, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWUreg", argLen: 1, asm: loong64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVVreg", argLen: 1, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVVnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWF", argLen: 1, asm: loong64.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVWD", argLen: 1, asm: loong64.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVF", argLen: 1, asm: loong64.AMOVVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVD", argLen: 1, asm: loong64.AMOVVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFW", argLen: 1, asm: loong64.ATRUNCFW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDW", argLen: 1, asm: loong64.ATRUNCDW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFV", argLen: 1, asm: loong64.ATRUNCFV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDV", argLen: 1, asm: loong64.ATRUNCDV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVFD", argLen: 1, asm: loong64.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDF", argLen: 1, asm: loong64.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 268435456}, // R29 {0, 1071644668}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 524288}, // R20 }, clobbers: 524290, // R1 R20 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R21 {1, 524288}, // R20 }, clobbers: 1572866, // R1 R20 R21 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 524288}, // R20 {1, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 524288, // R20 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R21 {1, 524288}, // R20 {2, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 1572864, // R20 R21 }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicLoad64", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStore64", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStore8Variant", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStore32Variant", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStore64Variant", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicExchange8Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicCas64Variant", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicCas32Variant", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, asm: loong64.AAMANDDBW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicOr32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, asm: loong64.AAMORDBW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAnd32value", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, asm: loong64.AAMANDDBW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAnd64value", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, asm: loong64.AAMANDDBV, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicOr32value", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, asm: loong64.AAMORDBW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicOr64value", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, asm: loong64.AAMORDBV, reg: regInfo{ inputs: []inputInfo{ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "FPFlagTrue", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "FPFlagFalse", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 268435456}, // R29 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 outputs: []outputInfo{ {0, 268435456}, // R29 }, }, }, { name: "LoweredPubBarrier", argLen: 1, hasSideEffects: true, asm: loong64.ADBAR, reg: regInfo{}, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4194304}, // R23 {1, 8388608}, // R24 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R21 {1, 4194304}, // R23 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 524288}, // R20 {1, 1048576}, // R21 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: mips.AADDU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, asm: mips.AADDU, reg: regInfo{ inputs: []inputInfo{ {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SUB", argLen: 2, asm: mips.ASUBU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, asm: mips.ASUBU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: mips.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, clobbers: 105553116266496, // HI LO outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MULT", argLen: 2, commutative: true, asm: mips.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "MULTU", argLen: 2, commutative: true, asm: mips.AMULU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "DIV", argLen: 2, asm: mips.ADIV, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "DIVU", argLen: 2, asm: mips.ADIVU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: mips.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: mips.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SUBF", argLen: 2, asm: mips.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SUBD", argLen: 2, asm: mips.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: mips.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: mips.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "DIVF", argLen: 2, asm: mips.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "DIVD", argLen: 2, asm: mips.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "ANDconst", auxType: auxInt32, argLen: 1, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "ORconst", auxType: auxInt32, argLen: 1, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "XORconst", auxType: auxInt32, argLen: 1, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NORconst", auxType: auxInt32, argLen: 1, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NEG", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NEGF", argLen: 1, asm: mips.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "NEGD", argLen: 1, asm: mips.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "ABSD", argLen: 1, asm: mips.AABSD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SQRTD", argLen: 1, asm: mips.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SQRTF", argLen: 1, asm: mips.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SLL", argLen: 2, asm: mips.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SLLconst", auxType: auxInt32, argLen: 1, asm: mips.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRL", argLen: 2, asm: mips.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRLconst", auxType: auxInt32, argLen: 1, asm: mips.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRA", argLen: 2, asm: mips.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRAconst", auxType: auxInt32, argLen: 1, asm: mips.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CLZ", argLen: 1, asm: mips.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGT", argLen: 2, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTconst", auxType: auxInt32, argLen: 1, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTzero", argLen: 1, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTU", argLen: 2, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTUconst", auxType: auxInt32, argLen: 1, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTUzero", argLen: 1, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CMPEQF", argLen: 2, asm: mips.ACMPEQF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPEQD", argLen: 2, asm: mips.ACMPEQD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGEF", argLen: 2, asm: mips.ACMPGEF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGED", argLen: 2, asm: mips.ACMPGED, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGTF", argLen: 2, asm: mips.ACMPGTF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGTD", argLen: 2, asm: mips.ACMPGTD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVWconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: mips.AMOVW, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVFconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: mips.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: mips.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVWaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 140737555464192}, // SP SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVWfpgp", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWgpfp", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVBreg", argLen: 1, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVBUreg", argLen: 1, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHreg", argLen: 1, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHUreg", argLen: 1, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWreg", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CMOVZ", argLen: 3, resultInArg0: true, asm: mips.ACMOVZ, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CMOVZzero", argLen: 2, resultInArg0: true, asm: mips.ACMOVZ, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWF", argLen: 1, asm: mips.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVWD", argLen: 1, asm: mips.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "TRUNCFW", argLen: 1, asm: mips.ATRUNCFW, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "TRUNCDW", argLen: 1, asm: mips.ATRUNCDW, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVFD", argLen: 1, asm: mips.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVDF", argLen: 1, asm: mips.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4194304}, // R22 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 }, clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicStorezero", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicExchange", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicAdd", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicAddconst", auxType: auxInt32, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicCas", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicAnd", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicOr", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredZero", auxType: auxInt32, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, clobbers: 2, // R1 }, }, { name: "LoweredMove", auxType: auxInt32, argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, clobbers: 6, // R1 R2 }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, }, }, { name: "FPFlagTrue", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "FPFlagFalse", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4194304}, // R22 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO outputs: []outputInfo{ {0, 16777216}, // R25 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 8}, // R3 {1, 16}, // R4 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicExtendA", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 8}, // R3 {2, 16}, // R4 }, }, }, { name: "LoweredPanicExtendB", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 4}, // R2 {2, 8}, // R3 }, }, }, { name: "LoweredPanicExtendC", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 2}, // R1 {2, 4}, // R2 }, }, }, { name: "ADDV", argLen: 2, commutative: true, asm: mips.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "ADDVconst", auxType: auxInt64, argLen: 1, asm: mips.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SUBV", argLen: 2, asm: mips.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SUBVconst", auxType: auxInt64, argLen: 1, asm: mips.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MULV", argLen: 2, commutative: true, asm: mips.AMULV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "MULVU", argLen: 2, commutative: true, asm: mips.AMULVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "DIVV", argLen: 2, asm: mips.ADIVV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "DIVVU", argLen: 2, asm: mips.ADIVVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: mips.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: mips.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBF", argLen: 2, asm: mips.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBD", argLen: 2, asm: mips.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: mips.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: mips.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVF", argLen: 2, asm: mips.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVD", argLen: 2, asm: mips.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NORconst", auxType: auxInt64, argLen: 1, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NEGV", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NEGF", argLen: 1, asm: mips.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "NEGD", argLen: 1, asm: mips.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "ABSD", argLen: 1, asm: mips.AABSD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTD", argLen: 1, asm: mips.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTF", argLen: 1, asm: mips.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SLLV", argLen: 2, asm: mips.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SLLVconst", auxType: auxInt64, argLen: 1, asm: mips.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRLV", argLen: 2, asm: mips.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRLVconst", auxType: auxInt64, argLen: 1, asm: mips.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRAV", argLen: 2, asm: mips.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRAVconst", auxType: auxInt64, argLen: 1, asm: mips.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGT", argLen: 2, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGTconst", auxType: auxInt64, argLen: 1, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGTU", argLen: 2, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGTUconst", auxType: auxInt64, argLen: 1, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "CMPEQF", argLen: 2, asm: mips.ACMPEQF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPEQD", argLen: 2, asm: mips.ACMPEQD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGEF", argLen: 2, asm: mips.ACMPGEF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGED", argLen: 2, asm: mips.ACMPGED, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTF", argLen: 2, asm: mips.ACMPGTF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTD", argLen: 2, asm: mips.ACMPGTD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: mips.AMOVV, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVFconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: mips.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: mips.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018460942336}, // SP SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVVstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVVstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVWfpgp", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWgpfp", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVfpgp", argLen: 1, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVgpfp", argLen: 1, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBreg", argLen: 1, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVBUreg", argLen: 1, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHreg", argLen: 1, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHUreg", argLen: 1, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWreg", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWUreg", argLen: 1, asm: mips.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVreg", argLen: 1, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWF", argLen: 1, asm: mips.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVWD", argLen: 1, asm: mips.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVF", argLen: 1, asm: mips.AMOVVF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVD", argLen: 1, asm: mips.AMOVVD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFW", argLen: 1, asm: mips.ATRUNCFW, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDW", argLen: 1, asm: mips.ATRUNCDW, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFV", argLen: 1, asm: mips.ATRUNCFV, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDV", argLen: 1, asm: mips.ATRUNCDV, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVFD", argLen: 1, asm: mips.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDF", argLen: 1, asm: mips.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4194304}, // R22 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 }, clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 134217730, // R1 R31 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 }, clobbers: 134217734, // R1 R2 R31 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 2, // R1 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 6, // R1 R2 }, }, { name: "LoweredAtomicAnd32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicOr32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicLoad64", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStore64", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStorezero32", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStorezero64", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAddconst32", auxType: auxInt32, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAddconst64", auxType: auxInt64, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, }, }, { name: "FPFlagTrue", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "FPFlagFalse", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4194304}, // R22 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO outputs: []outputInfo{ {0, 16777216}, // R25 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 8}, // R3 {1, 16}, // R4 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: ppc64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDCC", argLen: 2, commutative: true, asm: ppc64.AADDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDconst", auxType: auxInt64, argLen: 1, asm: ppc64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDCCconst", auxType: auxInt64, argLen: 1, asm: ppc64.AADDCCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FADD", argLen: 2, commutative: true, asm: ppc64.AFADD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: ppc64.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "SUB", argLen: 2, asm: ppc64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBCC", argLen: 2, asm: ppc64.ASUBCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBFCconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FSUB", argLen: 2, asm: ppc64.AFSUB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FSUBS", argLen: 2, asm: ppc64.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "XSMINJDP", argLen: 2, asm: ppc64.AXSMINJDP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "XSMAXJDP", argLen: 2, asm: ppc64.AXSMAXJDP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MULLD", argLen: 2, commutative: true, asm: ppc64.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLW", argLen: 2, commutative: true, asm: ppc64.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLDconst", auxType: auxInt32, argLen: 1, asm: ppc64.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLWconst", auxType: auxInt32, argLen: 1, asm: ppc64.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MADDLD", argLen: 3, asm: ppc64.AMADDLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHD", argLen: 2, commutative: true, asm: ppc64.AMULHD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHW", argLen: 2, commutative: true, asm: ppc64.AMULHW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHDU", argLen: 2, commutative: true, asm: ppc64.AMULHDU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHDUCC", argLen: 2, commutative: true, asm: ppc64.AMULHDUCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHWU", argLen: 2, commutative: true, asm: ppc64.AMULHWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMUL", argLen: 2, commutative: true, asm: ppc64.AFMUL, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: ppc64.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMADD", argLen: 3, asm: ppc64.AFMADD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMADDS", argLen: 3, asm: ppc64.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMSUB", argLen: 3, asm: ppc64.AFMSUB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMSUBS", argLen: 3, asm: ppc64.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "SRAD", argLen: 2, asm: ppc64.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRAW", argLen: 2, asm: ppc64.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRD", argLen: 2, asm: ppc64.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRW", argLen: 2, asm: ppc64.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLD", argLen: 2, asm: ppc64.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLW", argLen: 2, asm: ppc64.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTL", argLen: 2, asm: ppc64.AROTL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTLW", argLen: 2, asm: ppc64.AROTLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CLRLSLWI", auxType: auxInt32, argLen: 1, asm: ppc64.ACLRLSLWI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CLRLSLDI", auxType: auxInt32, argLen: 1, asm: ppc64.ACLRLSLDI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDC", argLen: 2, commutative: true, asm: ppc64.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBC", argLen: 2, asm: ppc64.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDCconst", auxType: auxInt64, argLen: 1, asm: ppc64.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBCconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDE", argLen: 3, commutative: true, asm: ppc64.AADDE, reg: regInfo{ inputs: []inputInfo{ {2, 9223372036854775808}, // XER {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDZE", argLen: 2, asm: ppc64.AADDZE, reg: regInfo{ inputs: []inputInfo{ {1, 9223372036854775808}, // XER {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBE", argLen: 3, asm: ppc64.ASUBE, reg: regInfo{ inputs: []inputInfo{ {2, 9223372036854775808}, // XER {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDZEzero", argLen: 1, asm: ppc64.AADDZE, reg: regInfo{ inputs: []inputInfo{ {0, 9223372036854775808}, // XER }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBZEzero", argLen: 1, asm: ppc64.ASUBZE, reg: regInfo{ inputs: []inputInfo{ {0, 9223372036854775808}, // XER }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRADconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRAWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRDconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLDconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTLconst", auxType: auxInt64, argLen: 1, asm: ppc64.AROTL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTLWconst", auxType: auxInt64, argLen: 1, asm: ppc64.AROTLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "EXTSWSLconst", auxType: auxInt64, argLen: 1, asm: ppc64.AEXTSWSLI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLWINM", auxType: auxInt64, argLen: 1, asm: ppc64.ARLWNM, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLWNM", auxType: auxInt64, argLen: 2, asm: ppc64.ARLWNM, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLWMI", auxType: auxInt64, argLen: 2, resultInArg0: true, asm: ppc64.ARLWMI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLDICL", auxType: auxInt64, argLen: 1, asm: ppc64.ARLDICL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLDICLCC", auxType: auxInt64, argLen: 1, asm: ppc64.ARLDICLCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLDICR", auxType: auxInt64, argLen: 1, asm: ppc64.ARLDICR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTLZD", argLen: 1, asm: ppc64.ACNTLZD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTLZDCC", argLen: 1, asm: ppc64.ACNTLZDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTLZW", argLen: 1, asm: ppc64.ACNTLZW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTTZD", argLen: 1, asm: ppc64.ACNTTZD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTTZW", argLen: 1, asm: ppc64.ACNTTZW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "POPCNTD", argLen: 1, asm: ppc64.APOPCNTD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "POPCNTW", argLen: 1, asm: ppc64.APOPCNTW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "POPCNTB", argLen: 1, asm: ppc64.APOPCNTB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FDIV", argLen: 2, asm: ppc64.AFDIV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FDIVS", argLen: 2, asm: ppc64.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "DIVD", argLen: 2, asm: ppc64.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVW", argLen: 2, asm: ppc64.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVDU", argLen: 2, asm: ppc64.ADIVDU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVWU", argLen: 2, asm: ppc64.ADIVWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODUD", argLen: 2, asm: ppc64.AMODUD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODSD", argLen: 2, asm: ppc64.AMODSD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODUW", argLen: 2, asm: ppc64.AMODUW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODSW", argLen: 2, asm: ppc64.AMODSW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FCTIDZ", argLen: 1, asm: ppc64.AFCTIDZ, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCTIWZ", argLen: 1, asm: ppc64.AFCTIWZ, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCFID", argLen: 1, asm: ppc64.AFCFID, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCFIDS", argLen: 1, asm: ppc64.AFCFIDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FRSP", argLen: 1, asm: ppc64.AFRSP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MFVSRD", argLen: 1, asm: ppc64.AMFVSRD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MTVSRD", argLen: 1, asm: ppc64.AMTVSRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDN", argLen: 2, asm: ppc64.AANDN, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDNCC", argLen: 2, asm: ppc64.AANDNCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDCC", argLen: 2, commutative: true, asm: ppc64.AANDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ORN", argLen: 2, asm: ppc64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ORCC", argLen: 2, commutative: true, asm: ppc64.AORCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: ppc64.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NORCC", argLen: 2, commutative: true, asm: ppc64.ANORCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: ppc64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XORCC", argLen: 2, commutative: true, asm: ppc64.AXORCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "EQV", argLen: 2, commutative: true, asm: ppc64.AEQV, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NEG", argLen: 1, asm: ppc64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NEGCC", argLen: 1, asm: ppc64.ANEGCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "BRD", argLen: 1, asm: ppc64.ABRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "BRW", argLen: 1, asm: ppc64.ABRW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "BRH", argLen: 1, asm: ppc64.ABRH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FNEG", argLen: 1, asm: ppc64.AFNEG, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FSQRT", argLen: 1, asm: ppc64.AFSQRT, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FSQRTS", argLen: 1, asm: ppc64.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FFLOOR", argLen: 1, asm: ppc64.AFRIM, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCEIL", argLen: 1, asm: ppc64.AFRIP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FTRUNC", argLen: 1, asm: ppc64.AFRIZ, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FROUND", argLen: 1, asm: ppc64.AFRIN, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FABS", argLen: 1, asm: ppc64.AFABS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FNABS", argLen: 1, asm: ppc64.AFNABS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCPSGN", argLen: 2, asm: ppc64.AFCPSGN, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: ppc64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDCCconst", auxType: auxInt64, argLen: 1, asm: ppc64.AANDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, clobberFlags: true, asm: ppc64.AANDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBreg", argLen: 1, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZreg", argLen: 1, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHreg", argLen: 1, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZreg", argLen: 1, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWreg", argLen: 1, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZreg", argLen: 1, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRload", argLen: 2, faultOnNilArg0: true, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRload", argLen: 2, faultOnNilArg0: true, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHBRload", argLen: 2, faultOnNilArg0: true, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZloadidx", argLen: 3, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZloadidx", argLen: 3, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZloadidx", argLen: 3, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDloadidx", argLen: 3, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHBRloadidx", argLen: 3, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRloadidx", argLen: 3, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRloadidx", argLen: 3, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDloadidx", argLen: 3, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSloadidx", argLen: 3, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "DCBT", auxType: auxInt64, argLen: 2, hasSideEffects: true, asm: ppc64.ADCBT, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRstore", argLen: 3, faultOnNilArg0: true, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRstore", argLen: 3, faultOnNilArg0: true, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHBRstore", argLen: 3, faultOnNilArg0: true, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstoreidx", argLen: 4, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDstoreidx", argLen: 4, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSstoreidx", argLen: 4, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MOVHBRstoreidx", argLen: 4, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRstoreidx", argLen: 4, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRstoreidx", argLen: 4, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: ppc64.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: ppc64.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: ppc64.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCMPU", argLen: 2, asm: ppc64.AFCMPU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "CMP", argLen: 2, asm: ppc64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPU", argLen: 2, asm: ppc64.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPW", argLen: 2, asm: ppc64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWU", argLen: 2, asm: ppc64.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPconst", auxType: auxInt64, argLen: 1, asm: ppc64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPUconst", auxType: auxInt64, argLen: 1, asm: ppc64.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: ppc64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWUconst", auxType: auxInt32, argLen: 1, asm: ppc64.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ISEL", auxType: auxInt32, argLen: 3, asm: ppc64.AISEL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ISELZ", auxType: auxInt32, argLen: 2, asm: ppc64.AISEL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SETBC", auxType: auxInt32, argLen: 1, asm: ppc64.ASETBC, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SETBCR", auxType: auxInt32, argLen: 1, asm: ppc64.ASETBCR, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FLessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FLessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FGreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FGreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 2048}, // R11 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 2147483648, // R31 }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4096}, // R12 {1, 2048}, // R11 }, clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4096}, // R12 }, clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 }, clobbers: 1048576, // R20 }, }, { name: "LoweredZeroShort", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredQuadZeroShort", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredQuadZero", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 }, clobbers: 1048576, // R20 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 3145728, // R20 R21 }, }, { name: "LoweredMoveShort", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredQuadMove", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 3145728, // R20 R21 }, }, { name: "LoweredQuadMoveShort", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicStore8", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicStore32", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicStore64", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoad8", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoad32", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoad64", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoadPtr", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicExchange8", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicCas64", auxType: auxInt64, argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicCas32", auxType: auxInt64, argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAnd8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicOr8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicOr32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER outputs: []outputInfo{ {0, 536870912}, // R29 }, }, }, { name: "LoweredPubBarrier", argLen: 1, hasSideEffects: true, asm: ppc64.ALWSYNC, reg: regInfo{}, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 64}, // R6 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 32}, // R5 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 8}, // R3 {1, 16}, // R4 }, }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT", argLen: 0, reg: regInfo{}, }, { name: "ADD", argLen: 2, commutative: true, asm: riscv.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ADDI", auxType: auxInt64, argLen: 1, asm: riscv.AADDI, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ADDIW", auxType: auxInt64, argLen: 1, asm: riscv.AADDIW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "NEG", argLen: 1, asm: riscv.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "NEGW", argLen: 1, asm: riscv.ANEGW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SUB", argLen: 2, asm: riscv.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SUBW", argLen: 2, asm: riscv.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: riscv.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MULW", argLen: 2, commutative: true, asm: riscv.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MULH", argLen: 2, commutative: true, asm: riscv.AMULH, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MULHU", argLen: 2, commutative: true, asm: riscv.AMULHU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredMuluhilo", argLen: 2, resultNotInArgs: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredMuluover", argLen: 2, resultNotInArgs: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIV", argLen: 2, asm: riscv.ADIV, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIVU", argLen: 2, asm: riscv.ADIVU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIVW", argLen: 2, asm: riscv.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIVUW", argLen: 2, asm: riscv.ADIVUW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REM", argLen: 2, asm: riscv.AREM, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REMU", argLen: 2, asm: riscv.AREMU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REMW", argLen: 2, asm: riscv.AREMW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REMUW", argLen: 2, asm: riscv.AREMUW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: riscv.AMOV, reg: regInfo{ outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVDstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVBreg", argLen: 1, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHreg", argLen: 1, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWreg", argLen: 1, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDreg", argLen: 1, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBUreg", argLen: 1, asm: riscv.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHUreg", argLen: 1, asm: riscv.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWUreg", argLen: 1, asm: riscv.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLL", argLen: 2, asm: riscv.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLLW", argLen: 2, asm: riscv.ASLLW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRA", argLen: 2, asm: riscv.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRAW", argLen: 2, asm: riscv.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRL", argLen: 2, asm: riscv.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRLW", argLen: 2, asm: riscv.ASRLW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLLI", auxType: auxInt64, argLen: 1, asm: riscv.ASLLI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLLIW", auxType: auxInt64, argLen: 1, asm: riscv.ASLLIW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRAI", auxType: auxInt64, argLen: 1, asm: riscv.ASRAI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRAIW", auxType: auxInt64, argLen: 1, asm: riscv.ASRAIW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRLI", auxType: auxInt64, argLen: 1, asm: riscv.ASRLI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRLIW", auxType: auxInt64, argLen: 1, asm: riscv.ASRLIW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SH1ADD", argLen: 2, asm: riscv.ASH1ADD, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SH2ADD", argLen: 2, asm: riscv.ASH2ADD, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SH3ADD", argLen: 2, asm: riscv.ASH3ADD, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: riscv.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ANDN", argLen: 2, asm: riscv.AANDN, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ANDI", auxType: auxInt64, argLen: 1, asm: riscv.AANDI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "CLZ", argLen: 1, asm: riscv.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "CLZW", argLen: 1, asm: riscv.ACLZW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "CPOP", argLen: 1, asm: riscv.ACPOP, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "CPOPW", argLen: 1, asm: riscv.ACPOPW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "CTZ", argLen: 1, asm: riscv.ACTZ, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "CTZW", argLen: 1, asm: riscv.ACTZW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "NOT", argLen: 1, asm: riscv.ANOT, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: riscv.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ORN", argLen: 2, asm: riscv.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ORI", auxType: auxInt64, argLen: 1, asm: riscv.AORI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REV8", argLen: 1, asm: riscv.AREV8, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ROL", argLen: 2, asm: riscv.AROL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ROLW", argLen: 2, asm: riscv.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ROR", argLen: 2, asm: riscv.AROR, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "RORI", auxType: auxInt64, argLen: 1, asm: riscv.ARORI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "RORIW", auxType: auxInt64, argLen: 1, asm: riscv.ARORIW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "RORW", argLen: 2, asm: riscv.ARORW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "XNOR", argLen: 2, commutative: true, asm: riscv.AXNOR, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: riscv.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "XORI", auxType: auxInt64, argLen: 1, asm: riscv.AXORI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MIN", argLen: 2, commutative: true, asm: riscv.AMIN, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MAX", argLen: 2, commutative: true, asm: riscv.AMAX, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MINU", argLen: 2, commutative: true, asm: riscv.AMINU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MAXU", argLen: 2, commutative: true, asm: riscv.AMAXU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SEQZ", argLen: 1, asm: riscv.ASEQZ, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SNEZ", argLen: 1, asm: riscv.ASNEZ, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLT", argLen: 2, asm: riscv.ASLT, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLTI", auxType: auxInt64, argLen: 1, asm: riscv.ASLTI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLTU", argLen: 2, asm: riscv.ASLTU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLTIU", auxType: auxInt64, argLen: 1, asm: riscv.ASLTIU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, call: true, reg: regInfo{ clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, call: true, tailCall: true, reg: regInfo{ clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 33554432}, // X26 {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 16777216}, // X25 }, clobbers: 16777216, // X25 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 16777216}, // X25 {1, 8388608}, // X24 }, clobbers: 25165824, // X24 X25 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 16, // X5 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 32}, // X6 {2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 112, // X5 X6 X7 }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicLoad64", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "LoweredAtomicStore64", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: riscv.AAMOANDW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, }, }, { name: "LoweredAtomicOr32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: riscv.AAMOORW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 33554432}, // X26 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 outputs: []outputInfo{ {0, 8388608}, // X24 }, }, }, { name: "LoweredPubBarrier", argLen: 1, hasSideEffects: true, asm: riscv.AFENCE, reg: regInfo{}, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // X7 {1, 134217728}, // X28 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // X6 {1, 64}, // X7 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 32}, // X6 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: riscv.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBS", argLen: 2, asm: riscv.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: riscv.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVS", argLen: 2, asm: riscv.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDS", argLen: 3, commutative: true, asm: riscv.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBS", argLen: 3, commutative: true, asm: riscv.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDS", argLen: 3, commutative: true, asm: riscv.AFNMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBS", argLen: 3, commutative: true, asm: riscv.AFNMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTS", argLen: 1, asm: riscv.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGS", argLen: 1, asm: riscv.AFNEGS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMVSX", argLen: 1, asm: riscv.AFMVSX, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTSW", argLen: 1, asm: riscv.AFCVTSW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTSL", argLen: 1, asm: riscv.AFCVTSL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTWS", argLen: 1, asm: riscv.AFCVTWS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FCVTLS", argLen: 1, asm: riscv.AFCVTLS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FMOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FEQS", argLen: 2, commutative: true, asm: riscv.AFEQS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FNES", argLen: 2, commutative: true, asm: riscv.AFNES, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLTS", argLen: 2, asm: riscv.AFLTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLES", argLen: 2, asm: riscv.AFLES, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredFMAXS", argLen: 2, commutative: true, resultNotInArgs: true, asm: riscv.AFMAXS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredFMINS", argLen: 2, commutative: true, resultNotInArgs: true, asm: riscv.AFMINS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FADDD", argLen: 2, commutative: true, asm: riscv.AFADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBD", argLen: 2, asm: riscv.AFSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULD", argLen: 2, commutative: true, asm: riscv.AFMULD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVD", argLen: 2, asm: riscv.AFDIVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDD", argLen: 3, commutative: true, asm: riscv.AFMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBD", argLen: 3, commutative: true, asm: riscv.AFMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDD", argLen: 3, commutative: true, asm: riscv.AFNMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBD", argLen: 3, commutative: true, asm: riscv.AFNMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTD", argLen: 1, asm: riscv.AFSQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGD", argLen: 1, asm: riscv.AFNEGD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FABSD", argLen: 1, asm: riscv.AFABSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSGNJD", argLen: 2, asm: riscv.AFSGNJD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMVDX", argLen: 1, asm: riscv.AFMVDX, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTDW", argLen: 1, asm: riscv.AFCVTDW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTDL", argLen: 1, asm: riscv.AFCVTDL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTWD", argLen: 1, asm: riscv.AFCVTWD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FCVTLD", argLen: 1, asm: riscv.AFCVTLD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FCVTDS", argLen: 1, asm: riscv.AFCVTDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTSD", argLen: 1, asm: riscv.AFCVTSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FEQD", argLen: 2, commutative: true, asm: riscv.AFEQD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FNED", argLen: 2, commutative: true, asm: riscv.AFNED, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLTD", argLen: 2, asm: riscv.AFLTD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLED", argLen: 2, asm: riscv.AFLED, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredFMIND", argLen: 2, commutative: true, resultNotInArgs: true, asm: riscv.AFMIND, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredFMAXD", argLen: 2, commutative: true, resultNotInArgs: true, asm: riscv.AFMAXD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FADDS", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FADD", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFADD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FSUBS", argLen: 2, resultInArg0: true, asm: s390x.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FSUB", argLen: 2, resultInArg0: true, asm: s390x.AFSUB, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMULS", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMUL", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFMUL, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FDIVS", argLen: 2, resultInArg0: true, asm: s390x.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FDIV", argLen: 2, resultInArg0: true, asm: s390x.AFDIV, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FNEGS", argLen: 1, clobberFlags: true, asm: s390x.AFNEGS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FNEG", argLen: 1, clobberFlags: true, asm: s390x.AFNEG, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMADDS", argLen: 3, resultInArg0: true, asm: s390x.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMADD", argLen: 3, resultInArg0: true, asm: s390x.AFMADD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMSUBS", argLen: 3, resultInArg0: true, asm: s390x.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMSUB", argLen: 3, resultInArg0: true, asm: s390x.AFMSUB, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LPDFR", argLen: 1, asm: s390x.ALPDFR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LNDFR", argLen: 1, asm: s390x.ALNDFR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CPSDR", argLen: 2, asm: s390x.ACPSDR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FIDBR", auxType: auxInt8, argLen: 1, asm: s390x.AFIDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: s390x.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: s390x.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSloadidx", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDloadidx", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSstoreidx", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDstoreidx", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ADD", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AADD, reg: regInfo{ inputs: []inputInfo{ {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AADDW, reg: regInfo{ inputs: []inputInfo{ {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: s390x.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDWconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: s390x.AADDW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AADDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUB", argLen: 2, clobberFlags: true, asm: s390x.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBW", argLen: 2, clobberFlags: true, asm: s390x.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLD", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLW", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLDconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULHD", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULHD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULHDU", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULHDU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVD", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVDU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVDU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVWU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVWU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODD", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODDU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODDU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODWU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODWU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "AND", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "OR", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XOR", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDC", argLen: 2, commutative: true, asm: s390x.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDCconst", auxType: auxInt16, argLen: 1, asm: s390x.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDE", argLen: 3, commutative: true, resultInArg0: true, asm: s390x.AADDE, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBC", argLen: 2, asm: s390x.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBE", argLen: 3, resultInArg0: true, asm: s390x.ASUBE, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CMP", argLen: 2, asm: s390x.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPW", argLen: 2, asm: s390x.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPU", argLen: 2, asm: s390x.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPWU", argLen: 2, asm: s390x.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPUconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPWUconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "FCMPS", argLen: 2, asm: s390x.ACEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FCMP", argLen: 2, asm: s390x.AFCMPU, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LTDBR", argLen: 1, asm: s390x.ALTDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LTEBR", argLen: 1, asm: s390x.ALTEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SLD", argLen: 2, asm: s390x.ASLD, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SLW", argLen: 2, asm: s390x.ASLW, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SLDconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SLWconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRD", argLen: 2, asm: s390x.ASRD, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRW", argLen: 2, asm: s390x.ASRW, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRDconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRWconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRAD", argLen: 2, clobberFlags: true, asm: s390x.ASRAD, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRAW", argLen: 2, clobberFlags: true, asm: s390x.ASRAW, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRADconst", auxType: auxUInt8, argLen: 1, clobberFlags: true, asm: s390x.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRAWconst", auxType: auxUInt8, argLen: 1, clobberFlags: true, asm: s390x.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RLLG", argLen: 2, asm: s390x.ARLLG, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RLL", argLen: 2, asm: s390x.ARLL, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RLLconst", auxType: auxUInt8, argLen: 1, asm: s390x.ARLL, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RXSBG", auxType: auxS390XRotateParams, argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ARXSBG, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RISBGZ", auxType: auxS390XRotateParams, argLen: 1, clobberFlags: true, asm: s390x.ARISBGZ, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NEG", argLen: 1, clobberFlags: true, asm: s390x.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NEGW", argLen: 1, clobberFlags: true, asm: s390x.ANEGW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NOT", argLen: 1, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NOTW", argLen: 1, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "FSQRT", argLen: 1, asm: s390x.AFSQRT, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FSQRTS", argLen: 1, asm: s390x.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LOCGR", auxType: auxS390XCCMask, argLen: 3, resultInArg0: true, asm: s390x.ALOCGR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBreg", argLen: 1, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBZreg", argLen: 1, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHreg", argLen: 1, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHZreg", argLen: 1, asm: s390x.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWreg", argLen: 1, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZreg", argLen: 1, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: s390x.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LDGR", argLen: 1, asm: s390x.ALDGR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LGDR", argLen: 1, asm: s390x.ALGDR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CFDBRA", argLen: 1, clobberFlags: true, asm: s390x.ACFDBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CGDBRA", argLen: 1, clobberFlags: true, asm: s390x.ACGDBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CFEBRA", argLen: 1, clobberFlags: true, asm: s390x.ACFEBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CGEBRA", argLen: 1, clobberFlags: true, asm: s390x.ACGEBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CEFBRA", argLen: 1, clobberFlags: true, asm: s390x.ACEFBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDFBRA", argLen: 1, clobberFlags: true, asm: s390x.ACDFBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CEGBRA", argLen: 1, clobberFlags: true, asm: s390x.ACEGBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDGBRA", argLen: 1, clobberFlags: true, asm: s390x.ACDGBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CLFEBR", argLen: 1, clobberFlags: true, asm: s390x.ACLFEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CLFDBR", argLen: 1, clobberFlags: true, asm: s390x.ACLFDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CLGEBR", argLen: 1, clobberFlags: true, asm: s390x.ACLGEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CLGDBR", argLen: 1, clobberFlags: true, asm: s390x.ACLGDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CELFBR", argLen: 1, clobberFlags: true, asm: s390x.ACELFBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDLFBR", argLen: 1, clobberFlags: true, asm: s390x.ACDLFBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CELGBR", argLen: 1, clobberFlags: true, asm: s390x.ACELGBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDLGBR", argLen: 1, clobberFlags: true, asm: s390x.ACDLGBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LEDBR", argLen: 1, asm: s390x.ALEDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LDEBR", argLen: 1, asm: s390x.ALDEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {0, 4295000064}, // SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDaddridx", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {0, 4295000064}, // SP SB {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWBR", argLen: 1, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDBR", argLen: 1, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHBRstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWBRstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDBRstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MVC", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, symEffect: SymNone, asm: s390x.AMVC, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVBZloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHZloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHBRloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWBRloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDBRloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHBRstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWBRstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDBRstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "MOVHstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "MOVDstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "CLEAR", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ACLEAR, reg: regInfo{ inputs: []inputInfo{ {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4096}, // R12 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4096}, // R12 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, clobberFlags: true, reg: regInfo{ clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 outputs: []outputInfo{ {0, 512}, // R9 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT", argLen: 0, reg: regInfo{}, }, { name: "FlagOV", argLen: 0, reg: regInfo{}, }, { name: "SYNC", argLen: 1, asm: s390x.ASYNC, reg: regInfo{}, }, { name: "MOVBZatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBatomicstore", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWatomicstore", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDatomicstore", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LAA", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ALAA, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LAAG", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ALAAG, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "AddTupleFirst32", argLen: 2, reg: regInfo{}, }, { name: "AddTupleFirst64", argLen: 2, reg: regInfo{}, }, { name: "LAN", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAN, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LANfloor", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAN, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 2, // R1 }, }, { name: "LAO", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAO, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LAOfloor", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAO, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 2, // R1 }, }, { name: "LoweredAtomicCas32", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACS, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // R0 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 1, // R0 outputs: []outputInfo{ {1, 0}, {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredAtomicCas64", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACSG, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // R0 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 1, // R0 outputs: []outputInfo{ {1, 0}, {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredAtomicExchange32", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACS, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {1, 0}, {0, 1}, // R0 }, }, }, { name: "LoweredAtomicExchange64", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACSG, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {1, 0}, {0, 1}, // R0 }, }, }, { name: "FLOGR", argLen: 1, clobberFlags: true, asm: s390x.AFLOGR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, clobbers: 2, // R1 outputs: []outputInfo{ {0, 1}, // R0 }, }, }, { name: "POPCNT", argLen: 1, clobberFlags: true, asm: s390x.APOPCNT, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MLGR", argLen: 2, asm: s390x.AMLGR, reg: regInfo{ inputs: []inputInfo{ {1, 8}, // R3 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "SumBytes2", argLen: 1, reg: regInfo{}, }, { name: "SumBytes4", argLen: 1, reg: regInfo{}, }, { name: "SumBytes8", argLen: 1, reg: regInfo{}, }, { name: "STMG2", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMG, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STMG3", auxType: auxSymOff, argLen: 5, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMG, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STMG4", auxType: auxSymOff, argLen: 6, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMG, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {4, 16}, // R4 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STM2", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMY, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STM3", auxType: auxSymOff, argLen: 5, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMY, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STM4", auxType: auxSymOff, argLen: 6, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMY, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {4, 16}, // R4 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 6, // R1 R2 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 2, // R1 }, }, { name: "LoweredStaticCall", auxType: auxCallOff, argLen: 1, call: true, reg: regInfo{ clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredTailCall", auxType: auxCallOff, argLen: 1, call: true, tailCall: true, reg: regInfo{ clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredClosureCall", auxType: auxCallOff, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredInterCall", auxType: auxCallOff, argLen: 2, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredAddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 3, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetCallerSP", argLen: 1, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredWB", auxType: auxInt64, argLen: 1, reg: regInfo{ clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredConvert", argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "Select", argLen: 3, asm: wasm.ASelect, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load8U", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load8U, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load8S", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load8S, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load16U", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load16U, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load16S", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load16S, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load32U", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load32U, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load32S", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load32S, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Store8", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store8, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Store16", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store16, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Store32", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store32, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Store", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "F32Load", auxType: auxInt64, argLen: 2, asm: wasm.AF32Load, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Load", auxType: auxInt64, argLen: 2, asm: wasm.AF64Load, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F32Store", auxType: auxInt64, argLen: 3, asm: wasm.AF32Store, reg: regInfo{ inputs: []inputInfo{ {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "F64Store", auxType: auxInt64, argLen: 3, asm: wasm.AF64Store, reg: regInfo{ inputs: []inputInfo{ {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Const", auxType: auxInt64, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Const", auxType: auxFloat32, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Const", auxType: auxFloat64, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64Eqz", argLen: 1, asm: wasm.AI64Eqz, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Eq", argLen: 2, asm: wasm.AI64Eq, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Ne", argLen: 2, asm: wasm.AI64Ne, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LtS", argLen: 2, asm: wasm.AI64LtS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LtU", argLen: 2, asm: wasm.AI64LtU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GtS", argLen: 2, asm: wasm.AI64GtS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GtU", argLen: 2, asm: wasm.AI64GtU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LeS", argLen: 2, asm: wasm.AI64LeS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LeU", argLen: 2, asm: wasm.AI64LeU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GeS", argLen: 2, asm: wasm.AI64GeS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GeU", argLen: 2, asm: wasm.AI64GeU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Eq", argLen: 2, asm: wasm.AF32Eq, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Ne", argLen: 2, asm: wasm.AF32Ne, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Lt", argLen: 2, asm: wasm.AF32Lt, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Gt", argLen: 2, asm: wasm.AF32Gt, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Le", argLen: 2, asm: wasm.AF32Le, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Ge", argLen: 2, asm: wasm.AF32Ge, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Eq", argLen: 2, asm: wasm.AF64Eq, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Ne", argLen: 2, asm: wasm.AF64Ne, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Lt", argLen: 2, asm: wasm.AF64Lt, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Gt", argLen: 2, asm: wasm.AF64Gt, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Le", argLen: 2, asm: wasm.AF64Le, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Ge", argLen: 2, asm: wasm.AF64Ge, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Add", argLen: 2, asm: wasm.AI64Add, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64AddConst", auxType: auxInt64, argLen: 1, asm: wasm.AI64Add, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Sub", argLen: 2, asm: wasm.AI64Sub, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Mul", argLen: 2, asm: wasm.AI64Mul, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64DivS", argLen: 2, asm: wasm.AI64DivS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64DivU", argLen: 2, asm: wasm.AI64DivU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64RemS", argLen: 2, asm: wasm.AI64RemS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64RemU", argLen: 2, asm: wasm.AI64RemU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64And", argLen: 2, asm: wasm.AI64And, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Or", argLen: 2, asm: wasm.AI64Or, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Xor", argLen: 2, asm: wasm.AI64Xor, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Shl", argLen: 2, asm: wasm.AI64Shl, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64ShrS", argLen: 2, asm: wasm.AI64ShrS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64ShrU", argLen: 2, asm: wasm.AI64ShrU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Neg", argLen: 1, asm: wasm.AF32Neg, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Add", argLen: 2, asm: wasm.AF32Add, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Sub", argLen: 2, asm: wasm.AF32Sub, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Mul", argLen: 2, asm: wasm.AF32Mul, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Div", argLen: 2, asm: wasm.AF32Div, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Neg", argLen: 1, asm: wasm.AF64Neg, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Add", argLen: 2, asm: wasm.AF64Add, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Sub", argLen: 2, asm: wasm.AF64Sub, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Mul", argLen: 2, asm: wasm.AF64Mul, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Div", argLen: 2, asm: wasm.AF64Div, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64TruncSatF64S", argLen: 1, asm: wasm.AI64TruncSatF64S, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64TruncSatF64U", argLen: 1, asm: wasm.AI64TruncSatF64U, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64TruncSatF32S", argLen: 1, asm: wasm.AI64TruncSatF32S, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64TruncSatF32U", argLen: 1, asm: wasm.AI64TruncSatF32U, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32ConvertI64S", argLen: 1, asm: wasm.AF32ConvertI64S, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32ConvertI64U", argLen: 1, asm: wasm.AF32ConvertI64U, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64ConvertI64S", argLen: 1, asm: wasm.AF64ConvertI64S, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64ConvertI64U", argLen: 1, asm: wasm.AF64ConvertI64U, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F32DemoteF64", argLen: 1, asm: wasm.AF32DemoteF64, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64PromoteF32", argLen: 1, asm: wasm.AF64PromoteF32, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64Extend8S", argLen: 1, asm: wasm.AI64Extend8S, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Extend16S", argLen: 1, asm: wasm.AI64Extend16S, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Extend32S", argLen: 1, asm: wasm.AI64Extend32S, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Sqrt", argLen: 1, asm: wasm.AF32Sqrt, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Trunc", argLen: 1, asm: wasm.AF32Trunc, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Ceil", argLen: 1, asm: wasm.AF32Ceil, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Floor", argLen: 1, asm: wasm.AF32Floor, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Nearest", argLen: 1, asm: wasm.AF32Nearest, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Abs", argLen: 1, asm: wasm.AF32Abs, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Copysign", argLen: 2, asm: wasm.AF32Copysign, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Sqrt", argLen: 1, asm: wasm.AF64Sqrt, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Trunc", argLen: 1, asm: wasm.AF64Trunc, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Ceil", argLen: 1, asm: wasm.AF64Ceil, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Floor", argLen: 1, asm: wasm.AF64Floor, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Nearest", argLen: 1, asm: wasm.AF64Nearest, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Abs", argLen: 1, asm: wasm.AF64Abs, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Copysign", argLen: 2, asm: wasm.AF64Copysign, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64Ctz", argLen: 1, asm: wasm.AI64Ctz, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Clz", argLen: 1, asm: wasm.AI64Clz, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I32Rotl", argLen: 2, asm: wasm.AI32Rotl, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Rotl", argLen: 2, asm: wasm.AI64Rotl, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Popcnt", argLen: 1, asm: wasm.AI64Popcnt, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "Add8", argLen: 2, commutative: true, generic: true, }, { name: "Add16", argLen: 2, commutative: true, generic: true, }, { name: "Add32", argLen: 2, commutative: true, generic: true, }, { name: "Add64", argLen: 2, commutative: true, generic: true, }, { name: "AddPtr", argLen: 2, generic: true, }, { name: "Add32F", argLen: 2, commutative: true, generic: true, }, { name: "Add64F", argLen: 2, commutative: true, generic: true, }, { name: "Sub8", argLen: 2, generic: true, }, { name: "Sub16", argLen: 2, generic: true, }, { name: "Sub32", argLen: 2, generic: true, }, { name: "Sub64", argLen: 2, generic: true, }, { name: "SubPtr", argLen: 2, generic: true, }, { name: "Sub32F", argLen: 2, generic: true, }, { name: "Sub64F", argLen: 2, generic: true, }, { name: "Mul8", argLen: 2, commutative: true, generic: true, }, { name: "Mul16", argLen: 2, commutative: true, generic: true, }, { name: "Mul32", argLen: 2, commutative: true, generic: true, }, { name: "Mul64", argLen: 2, commutative: true, generic: true, }, { name: "Mul32F", argLen: 2, commutative: true, generic: true, }, { name: "Mul64F", argLen: 2, commutative: true, generic: true, }, { name: "Div32F", argLen: 2, generic: true, }, { name: "Div64F", argLen: 2, generic: true, }, { name: "Hmul32", argLen: 2, commutative: true, generic: true, }, { name: "Hmul32u", argLen: 2, commutative: true, generic: true, }, { name: "Hmul64", argLen: 2, commutative: true, generic: true, }, { name: "Hmul64u", argLen: 2, commutative: true, generic: true, }, { name: "Mul32uhilo", argLen: 2, commutative: true, generic: true, }, { name: "Mul64uhilo", argLen: 2, commutative: true, generic: true, }, { name: "Mul32uover", argLen: 2, commutative: true, generic: true, }, { name: "Mul64uover", argLen: 2, commutative: true, generic: true, }, { name: "Avg32u", argLen: 2, generic: true, }, { name: "Avg64u", argLen: 2, generic: true, }, { name: "Div8", argLen: 2, generic: true, }, { name: "Div8u", argLen: 2, generic: true, }, { name: "Div16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Div16u", argLen: 2, generic: true, }, { name: "Div32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Div32u", argLen: 2, generic: true, }, { name: "Div64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Div64u", argLen: 2, generic: true, }, { name: "Div128u", argLen: 3, generic: true, }, { name: "Mod8", argLen: 2, generic: true, }, { name: "Mod8u", argLen: 2, generic: true, }, { name: "Mod16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Mod16u", argLen: 2, generic: true, }, { name: "Mod32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Mod32u", argLen: 2, generic: true, }, { name: "Mod64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Mod64u", argLen: 2, generic: true, }, { name: "And8", argLen: 2, commutative: true, generic: true, }, { name: "And16", argLen: 2, commutative: true, generic: true, }, { name: "And32", argLen: 2, commutative: true, generic: true, }, { name: "And64", argLen: 2, commutative: true, generic: true, }, { name: "Or8", argLen: 2, commutative: true, generic: true, }, { name: "Or16", argLen: 2, commutative: true, generic: true, }, { name: "Or32", argLen: 2, commutative: true, generic: true, }, { name: "Or64", argLen: 2, commutative: true, generic: true, }, { name: "Xor8", argLen: 2, commutative: true, generic: true, }, { name: "Xor16", argLen: 2, commutative: true, generic: true, }, { name: "Xor32", argLen: 2, commutative: true, generic: true, }, { name: "Xor64", argLen: 2, commutative: true, generic: true, }, { name: "Lsh8x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh8x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh8x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh8x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Eq8", argLen: 2, commutative: true, generic: true, }, { name: "Eq16", argLen: 2, commutative: true, generic: true, }, { name: "Eq32", argLen: 2, commutative: true, generic: true, }, { name: "Eq64", argLen: 2, commutative: true, generic: true, }, { name: "EqPtr", argLen: 2, commutative: true, generic: true, }, { name: "EqInter", argLen: 2, generic: true, }, { name: "EqSlice", argLen: 2, generic: true, }, { name: "Eq32F", argLen: 2, commutative: true, generic: true, }, { name: "Eq64F", argLen: 2, commutative: true, generic: true, }, { name: "Neq8", argLen: 2, commutative: true, generic: true, }, { name: "Neq16", argLen: 2, commutative: true, generic: true, }, { name: "Neq32", argLen: 2, commutative: true, generic: true, }, { name: "Neq64", argLen: 2, commutative: true, generic: true, }, { name: "NeqPtr", argLen: 2, commutative: true, generic: true, }, { name: "NeqInter", argLen: 2, generic: true, }, { name: "NeqSlice", argLen: 2, generic: true, }, { name: "Neq32F", argLen: 2, commutative: true, generic: true, }, { name: "Neq64F", argLen: 2, commutative: true, generic: true, }, { name: "Less8", argLen: 2, generic: true, }, { name: "Less8U", argLen: 2, generic: true, }, { name: "Less16", argLen: 2, generic: true, }, { name: "Less16U", argLen: 2, generic: true, }, { name: "Less32", argLen: 2, generic: true, }, { name: "Less32U", argLen: 2, generic: true, }, { name: "Less64", argLen: 2, generic: true, }, { name: "Less64U", argLen: 2, generic: true, }, { name: "Less32F", argLen: 2, generic: true, }, { name: "Less64F", argLen: 2, generic: true, }, { name: "Leq8", argLen: 2, generic: true, }, { name: "Leq8U", argLen: 2, generic: true, }, { name: "Leq16", argLen: 2, generic: true, }, { name: "Leq16U", argLen: 2, generic: true, }, { name: "Leq32", argLen: 2, generic: true, }, { name: "Leq32U", argLen: 2, generic: true, }, { name: "Leq64", argLen: 2, generic: true, }, { name: "Leq64U", argLen: 2, generic: true, }, { name: "Leq32F", argLen: 2, generic: true, }, { name: "Leq64F", argLen: 2, generic: true, }, { name: "CondSelect", argLen: 3, generic: true, }, { name: "AndB", argLen: 2, commutative: true, generic: true, }, { name: "OrB", argLen: 2, commutative: true, generic: true, }, { name: "EqB", argLen: 2, commutative: true, generic: true, }, { name: "NeqB", argLen: 2, commutative: true, generic: true, }, { name: "Not", argLen: 1, generic: true, }, { name: "Neg8", argLen: 1, generic: true, }, { name: "Neg16", argLen: 1, generic: true, }, { name: "Neg32", argLen: 1, generic: true, }, { name: "Neg64", argLen: 1, generic: true, }, { name: "Neg32F", argLen: 1, generic: true, }, { name: "Neg64F", argLen: 1, generic: true, }, { name: "Com8", argLen: 1, generic: true, }, { name: "Com16", argLen: 1, generic: true, }, { name: "Com32", argLen: 1, generic: true, }, { name: "Com64", argLen: 1, generic: true, }, { name: "Ctz8", argLen: 1, generic: true, }, { name: "Ctz16", argLen: 1, generic: true, }, { name: "Ctz32", argLen: 1, generic: true, }, { name: "Ctz64", argLen: 1, generic: true, }, { name: "Ctz64On32", argLen: 2, generic: true, }, { name: "Ctz8NonZero", argLen: 1, generic: true, }, { name: "Ctz16NonZero", argLen: 1, generic: true, }, { name: "Ctz32NonZero", argLen: 1, generic: true, }, { name: "Ctz64NonZero", argLen: 1, generic: true, }, { name: "BitLen8", argLen: 1, generic: true, }, { name: "BitLen16", argLen: 1, generic: true, }, { name: "BitLen32", argLen: 1, generic: true, }, { name: "BitLen64", argLen: 1, generic: true, }, { name: "Bswap16", argLen: 1, generic: true, }, { name: "Bswap32", argLen: 1, generic: true, }, { name: "Bswap64", argLen: 1, generic: true, }, { name: "BitRev8", argLen: 1, generic: true, }, { name: "BitRev16", argLen: 1, generic: true, }, { name: "BitRev32", argLen: 1, generic: true, }, { name: "BitRev64", argLen: 1, generic: true, }, { name: "PopCount8", argLen: 1, generic: true, }, { name: "PopCount16", argLen: 1, generic: true, }, { name: "PopCount32", argLen: 1, generic: true, }, { name: "PopCount64", argLen: 1, generic: true, }, { name: "RotateLeft64", argLen: 2, generic: true, }, { name: "RotateLeft32", argLen: 2, generic: true, }, { name: "RotateLeft16", argLen: 2, generic: true, }, { name: "RotateLeft8", argLen: 2, generic: true, }, { name: "Sqrt", argLen: 1, generic: true, }, { name: "Sqrt32", argLen: 1, generic: true, }, { name: "Floor", argLen: 1, generic: true, }, { name: "Ceil", argLen: 1, generic: true, }, { name: "Trunc", argLen: 1, generic: true, }, { name: "Round", argLen: 1, generic: true, }, { name: "RoundToEven", argLen: 1, generic: true, }, { name: "Abs", argLen: 1, generic: true, }, { name: "Copysign", argLen: 2, generic: true, }, { name: "Min64", argLen: 2, generic: true, }, { name: "Max64", argLen: 2, generic: true, }, { name: "Min64u", argLen: 2, generic: true, }, { name: "Max64u", argLen: 2, generic: true, }, { name: "Min64F", argLen: 2, generic: true, }, { name: "Min32F", argLen: 2, generic: true, }, { name: "Max64F", argLen: 2, generic: true, }, { name: "Max32F", argLen: 2, generic: true, }, { name: "FMA", argLen: 3, generic: true, }, { name: "Phi", argLen: -1, zeroWidth: true, generic: true, }, { name: "Copy", argLen: 1, generic: true, }, { name: "Convert", argLen: 2, resultInArg0: true, zeroWidth: true, generic: true, }, { name: "ConstBool", auxType: auxBool, argLen: 0, generic: true, }, { name: "ConstString", auxType: auxString, argLen: 0, generic: true, }, { name: "ConstNil", argLen: 0, generic: true, }, { name: "Const8", auxType: auxInt8, argLen: 0, generic: true, }, { name: "Const16", auxType: auxInt16, argLen: 0, generic: true, }, { name: "Const32", auxType: auxInt32, argLen: 0, generic: true, }, { name: "Const64", auxType: auxInt64, argLen: 0, generic: true, }, { name: "Const32F", auxType: auxFloat32, argLen: 0, generic: true, }, { name: "Const64F", auxType: auxFloat64, argLen: 0, generic: true, }, { name: "ConstInterface", argLen: 0, generic: true, }, { name: "ConstSlice", argLen: 0, generic: true, }, { name: "InitMem", argLen: 0, zeroWidth: true, generic: true, }, { name: "Arg", auxType: auxSymOff, argLen: 0, zeroWidth: true, symEffect: SymRead, generic: true, }, { name: "ArgIntReg", auxType: auxNameOffsetInt8, argLen: 0, zeroWidth: true, generic: true, }, { name: "ArgFloatReg", auxType: auxNameOffsetInt8, argLen: 0, zeroWidth: true, generic: true, }, { name: "Addr", auxType: auxSym, argLen: 1, symEffect: SymAddr, generic: true, }, { name: "LocalAddr", auxType: auxSym, argLen: 2, symEffect: SymAddr, generic: true, }, { name: "SP", argLen: 0, zeroWidth: true, fixedReg: true, generic: true, }, { name: "SB", argLen: 0, zeroWidth: true, fixedReg: true, generic: true, }, { name: "SPanchored", argLen: 2, zeroWidth: true, generic: true, }, { name: "Load", argLen: 2, generic: true, }, { name: "Dereference", argLen: 2, generic: true, }, { name: "Store", auxType: auxTyp, argLen: 3, generic: true, }, { name: "Move", auxType: auxTypSize, argLen: 3, generic: true, }, { name: "Zero", auxType: auxTypSize, argLen: 2, generic: true, }, { name: "StoreWB", auxType: auxTyp, argLen: 3, generic: true, }, { name: "MoveWB", auxType: auxTypSize, argLen: 3, generic: true, }, { name: "ZeroWB", auxType: auxTypSize, argLen: 2, generic: true, }, { name: "WBend", argLen: 1, generic: true, }, { name: "WB", auxType: auxInt64, argLen: 1, generic: true, }, { name: "HasCPUFeature", auxType: auxSym, argLen: 0, symEffect: SymNone, generic: true, }, { name: "PanicBounds", auxType: auxInt64, argLen: 3, call: true, generic: true, }, { name: "PanicExtend", auxType: auxInt64, argLen: 4, call: true, generic: true, }, { name: "ClosureCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "StaticCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "InterCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "TailCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "ClosureLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "StaticLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "InterLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "TailLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "SignExt8to16", argLen: 1, generic: true, }, { name: "SignExt8to32", argLen: 1, generic: true, }, { name: "SignExt8to64", argLen: 1, generic: true, }, { name: "SignExt16to32", argLen: 1, generic: true, }, { name: "SignExt16to64", argLen: 1, generic: true, }, { name: "SignExt32to64", argLen: 1, generic: true, }, { name: "ZeroExt8to16", argLen: 1, generic: true, }, { name: "ZeroExt8to32", argLen: 1, generic: true, }, { name: "ZeroExt8to64", argLen: 1, generic: true, }, { name: "ZeroExt16to32", argLen: 1, generic: true, }, { name: "ZeroExt16to64", argLen: 1, generic: true, }, { name: "ZeroExt32to64", argLen: 1, generic: true, }, { name: "Trunc16to8", argLen: 1, generic: true, }, { name: "Trunc32to8", argLen: 1, generic: true, }, { name: "Trunc32to16", argLen: 1, generic: true, }, { name: "Trunc64to8", argLen: 1, generic: true, }, { name: "Trunc64to16", argLen: 1, generic: true, }, { name: "Trunc64to32", argLen: 1, generic: true, }, { name: "Cvt32to32F", argLen: 1, generic: true, }, { name: "Cvt32to64F", argLen: 1, generic: true, }, { name: "Cvt64to32F", argLen: 1, generic: true, }, { name: "Cvt64to64F", argLen: 1, generic: true, }, { name: "Cvt32Fto32", argLen: 1, generic: true, }, { name: "Cvt32Fto64", argLen: 1, generic: true, }, { name: "Cvt64Fto32", argLen: 1, generic: true, }, { name: "Cvt64Fto64", argLen: 1, generic: true, }, { name: "Cvt32Fto64F", argLen: 1, generic: true, }, { name: "Cvt64Fto32F", argLen: 1, generic: true, }, { name: "CvtBoolToUint8", argLen: 1, generic: true, }, { name: "Round32F", argLen: 1, generic: true, }, { name: "Round64F", argLen: 1, generic: true, }, { name: "IsNonNil", argLen: 1, generic: true, }, { name: "IsInBounds", argLen: 2, generic: true, }, { name: "IsSliceInBounds", argLen: 2, generic: true, }, { name: "NilCheck", argLen: 2, nilCheck: true, generic: true, }, { name: "GetG", argLen: 1, zeroWidth: true, generic: true, }, { name: "GetClosurePtr", argLen: 0, generic: true, }, { name: "GetCallerPC", argLen: 0, generic: true, }, { name: "GetCallerSP", argLen: 1, generic: true, }, { name: "PtrIndex", argLen: 2, generic: true, }, { name: "OffPtr", auxType: auxInt64, argLen: 1, generic: true, }, { name: "SliceMake", argLen: 3, generic: true, }, { name: "SlicePtr", argLen: 1, generic: true, }, { name: "SliceLen", argLen: 1, generic: true, }, { name: "SliceCap", argLen: 1, generic: true, }, { name: "SlicePtrUnchecked", argLen: 1, generic: true, }, { name: "ComplexMake", argLen: 2, generic: true, }, { name: "ComplexReal", argLen: 1, generic: true, }, { name: "ComplexImag", argLen: 1, generic: true, }, { name: "StringMake", argLen: 2, generic: true, }, { name: "StringPtr", argLen: 1, generic: true, }, { name: "StringLen", argLen: 1, generic: true, }, { name: "IMake", argLen: 2, generic: true, }, { name: "ITab", argLen: 1, generic: true, }, { name: "IData", argLen: 1, generic: true, }, { name: "StructMake", argLen: -1, generic: true, }, { name: "StructSelect", auxType: auxInt64, argLen: 1, generic: true, }, { name: "ArrayMake0", argLen: 0, generic: true, }, { name: "ArrayMake1", argLen: 1, generic: true, }, { name: "ArraySelect", auxType: auxInt64, argLen: 1, generic: true, }, { name: "StoreReg", argLen: 1, generic: true, }, { name: "LoadReg", argLen: 1, generic: true, }, { name: "FwdRef", auxType: auxSym, argLen: 0, symEffect: SymNone, generic: true, }, { name: "Unknown", argLen: 0, generic: true, }, { name: "VarDef", auxType: auxSym, argLen: 1, zeroWidth: true, symEffect: SymNone, generic: true, }, { name: "VarLive", auxType: auxSym, argLen: 1, zeroWidth: true, symEffect: SymRead, generic: true, }, { name: "KeepAlive", argLen: 2, zeroWidth: true, generic: true, }, { name: "InlMark", auxType: auxInt32, argLen: 1, generic: true, }, { name: "Int64Make", argLen: 2, generic: true, }, { name: "Int64Hi", argLen: 1, generic: true, }, { name: "Int64Lo", argLen: 1, generic: true, }, { name: "Add32carry", argLen: 2, commutative: true, generic: true, }, { name: "Add32withcarry", argLen: 3, commutative: true, generic: true, }, { name: "Sub32carry", argLen: 2, generic: true, }, { name: "Sub32withcarry", argLen: 3, generic: true, }, { name: "Add64carry", argLen: 3, commutative: true, generic: true, }, { name: "Sub64borrow", argLen: 3, generic: true, }, { name: "Signmask", argLen: 1, generic: true, }, { name: "Zeromask", argLen: 1, generic: true, }, { name: "Slicemask", argLen: 1, generic: true, }, { name: "SpectreIndex", argLen: 2, generic: true, }, { name: "SpectreSliceIndex", argLen: 2, generic: true, }, { name: "Cvt32Uto32F", argLen: 1, generic: true, }, { name: "Cvt32Uto64F", argLen: 1, generic: true, }, { name: "Cvt32Fto32U", argLen: 1, generic: true, }, { name: "Cvt64Fto32U", argLen: 1, generic: true, }, { name: "Cvt64Uto32F", argLen: 1, generic: true, }, { name: "Cvt64Uto64F", argLen: 1, generic: true, }, { name: "Cvt32Fto64U", argLen: 1, generic: true, }, { name: "Cvt64Fto64U", argLen: 1, generic: true, }, { name: "Select0", argLen: 1, zeroWidth: true, generic: true, }, { name: "Select1", argLen: 1, zeroWidth: true, generic: true, }, { name: "MakeTuple", argLen: 2, generic: true, }, { name: "SelectN", auxType: auxInt64, argLen: 1, generic: true, }, { name: "SelectNAddr", auxType: auxInt64, argLen: 1, generic: true, }, { name: "MakeResult", argLen: -1, generic: true, }, { name: "AtomicLoad8", argLen: 2, generic: true, }, { name: "AtomicLoad32", argLen: 2, generic: true, }, { name: "AtomicLoad64", argLen: 2, generic: true, }, { name: "AtomicLoadPtr", argLen: 2, generic: true, }, { name: "AtomicLoadAcq32", argLen: 2, generic: true, }, { name: "AtomicLoadAcq64", argLen: 2, generic: true, }, { name: "AtomicStore8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStorePtrNoWB", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStoreRel32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStoreRel64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap32", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap64", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwapRel32", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicAnd8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd64value", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd32value", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd8value", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr64value", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr32value", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr8value", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore8Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore64Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd64Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange8Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange64Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap32Variant", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap64Variant", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicAnd64valueVariant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr64valueVariant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd32valueVariant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr32valueVariant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd8valueVariant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr8valueVariant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "PubBarrier", argLen: 1, hasSideEffects: true, generic: true, }, { name: "Clobber", auxType: auxSymOff, argLen: 0, symEffect: SymNone, generic: true, }, { name: "ClobberReg", argLen: 0, generic: true, }, { name: "PrefetchCache", argLen: 2, hasSideEffects: true, generic: true, }, { name: "PrefetchCacheStreamed", argLen: 2, hasSideEffects: true, generic: true, }, } func (o Op) Asm() obj.As { return opcodeTable[o].asm } func (o Op) Scale() int16 { return int16(opcodeTable[o].scale) } func (o Op) String() string { return opcodeTable[o].name } func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } func (o Op) IsCall() bool { return opcodeTable[o].call } func (o Op) IsTailCall() bool { return opcodeTable[o].tailCall } func (o Op) HasSideEffects() bool { return opcodeTable[o].hasSideEffects } func (o Op) UnsafePoint() bool { return opcodeTable[o].unsafePoint } func (o Op) ResultInArg0() bool { return opcodeTable[o].resultInArg0 } var registers386 = [...]Register{ {0, x86.REG_AX, "AX"}, {1, x86.REG_CX, "CX"}, {2, x86.REG_DX, "DX"}, {3, x86.REG_BX, "BX"}, {4, x86.REGSP, "SP"}, {5, x86.REG_BP, "BP"}, {6, x86.REG_SI, "SI"}, {7, x86.REG_DI, "DI"}, {8, x86.REG_X0, "X0"}, {9, x86.REG_X1, "X1"}, {10, x86.REG_X2, "X2"}, {11, x86.REG_X3, "X3"}, {12, x86.REG_X4, "X4"}, {13, x86.REG_X5, "X5"}, {14, x86.REG_X6, "X6"}, {15, x86.REG_X7, "X7"}, {16, 0, "SB"}, } var paramIntReg386 = []int8(nil) var paramFloatReg386 = []int8(nil) var gpRegMask386 = regMask(239) var fpRegMask386 = regMask(65280) var specialRegMask386 = regMask(0) var framepointerReg386 = int8(5) var linkReg386 = int8(-1) var registersAMD64 = [...]Register{ {0, x86.REG_AX, "AX"}, {1, x86.REG_CX, "CX"}, {2, x86.REG_DX, "DX"}, {3, x86.REG_BX, "BX"}, {4, x86.REGSP, "SP"}, {5, x86.REG_BP, "BP"}, {6, x86.REG_SI, "SI"}, {7, x86.REG_DI, "DI"}, {8, x86.REG_R8, "R8"}, {9, x86.REG_R9, "R9"}, {10, x86.REG_R10, "R10"}, {11, x86.REG_R11, "R11"}, {12, x86.REG_R12, "R12"}, {13, x86.REG_R13, "R13"}, {14, x86.REGG, "g"}, {15, x86.REG_R15, "R15"}, {16, x86.REG_X0, "X0"}, {17, x86.REG_X1, "X1"}, {18, x86.REG_X2, "X2"}, {19, x86.REG_X3, "X3"}, {20, x86.REG_X4, "X4"}, {21, x86.REG_X5, "X5"}, {22, x86.REG_X6, "X6"}, {23, x86.REG_X7, "X7"}, {24, x86.REG_X8, "X8"}, {25, x86.REG_X9, "X9"}, {26, x86.REG_X10, "X10"}, {27, x86.REG_X11, "X11"}, {28, x86.REG_X12, "X12"}, {29, x86.REG_X13, "X13"}, {30, x86.REG_X14, "X14"}, {31, x86.REG_X15, "X15"}, {32, 0, "SB"}, } var paramIntRegAMD64 = []int8{0, 3, 1, 7, 6, 8, 9, 10, 11} var paramFloatRegAMD64 = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30} var gpRegMaskAMD64 = regMask(49135) var fpRegMaskAMD64 = regMask(2147418112) var specialRegMaskAMD64 = regMask(2147483648) var framepointerRegAMD64 = int8(5) var linkRegAMD64 = int8(-1) var registersARM = [...]Register{ {0, arm.REG_R0, "R0"}, {1, arm.REG_R1, "R1"}, {2, arm.REG_R2, "R2"}, {3, arm.REG_R3, "R3"}, {4, arm.REG_R4, "R4"}, {5, arm.REG_R5, "R5"}, {6, arm.REG_R6, "R6"}, {7, arm.REG_R7, "R7"}, {8, arm.REG_R8, "R8"}, {9, arm.REG_R9, "R9"}, {10, arm.REGG, "g"}, {11, arm.REG_R11, "R11"}, {12, arm.REG_R12, "R12"}, {13, arm.REGSP, "SP"}, {14, arm.REG_R14, "R14"}, {15, arm.REG_R15, "R15"}, {16, arm.REG_F0, "F0"}, {17, arm.REG_F1, "F1"}, {18, arm.REG_F2, "F2"}, {19, arm.REG_F3, "F3"}, {20, arm.REG_F4, "F4"}, {21, arm.REG_F5, "F5"}, {22, arm.REG_F6, "F6"}, {23, arm.REG_F7, "F7"}, {24, arm.REG_F8, "F8"}, {25, arm.REG_F9, "F9"}, {26, arm.REG_F10, "F10"}, {27, arm.REG_F11, "F11"}, {28, arm.REG_F12, "F12"}, {29, arm.REG_F13, "F13"}, {30, arm.REG_F14, "F14"}, {31, arm.REG_F15, "F15"}, {32, 0, "SB"}, } var paramIntRegARM = []int8(nil) var paramFloatRegARM = []int8(nil) var gpRegMaskARM = regMask(21503) var fpRegMaskARM = regMask(4294901760) var specialRegMaskARM = regMask(0) var framepointerRegARM = int8(-1) var linkRegARM = int8(14) var registersARM64 = [...]Register{ {0, arm64.REG_R0, "R0"}, {1, arm64.REG_R1, "R1"}, {2, arm64.REG_R2, "R2"}, {3, arm64.REG_R3, "R3"}, {4, arm64.REG_R4, "R4"}, {5, arm64.REG_R5, "R5"}, {6, arm64.REG_R6, "R6"}, {7, arm64.REG_R7, "R7"}, {8, arm64.REG_R8, "R8"}, {9, arm64.REG_R9, "R9"}, {10, arm64.REG_R10, "R10"}, {11, arm64.REG_R11, "R11"}, {12, arm64.REG_R12, "R12"}, {13, arm64.REG_R13, "R13"}, {14, arm64.REG_R14, "R14"}, {15, arm64.REG_R15, "R15"}, {16, arm64.REG_R16, "R16"}, {17, arm64.REG_R17, "R17"}, {18, arm64.REG_R19, "R19"}, {19, arm64.REG_R20, "R20"}, {20, arm64.REG_R21, "R21"}, {21, arm64.REG_R22, "R22"}, {22, arm64.REG_R23, "R23"}, {23, arm64.REG_R24, "R24"}, {24, arm64.REG_R25, "R25"}, {25, arm64.REG_R26, "R26"}, {26, arm64.REGG, "g"}, {27, arm64.REG_R29, "R29"}, {28, arm64.REG_R30, "R30"}, {29, arm64.REGZERO, "ZERO"}, {30, arm64.REGSP, "SP"}, {31, arm64.REG_F0, "F0"}, {32, arm64.REG_F1, "F1"}, {33, arm64.REG_F2, "F2"}, {34, arm64.REG_F3, "F3"}, {35, arm64.REG_F4, "F4"}, {36, arm64.REG_F5, "F5"}, {37, arm64.REG_F6, "F6"}, {38, arm64.REG_F7, "F7"}, {39, arm64.REG_F8, "F8"}, {40, arm64.REG_F9, "F9"}, {41, arm64.REG_F10, "F10"}, {42, arm64.REG_F11, "F11"}, {43, arm64.REG_F12, "F12"}, {44, arm64.REG_F13, "F13"}, {45, arm64.REG_F14, "F14"}, {46, arm64.REG_F15, "F15"}, {47, arm64.REG_F16, "F16"}, {48, arm64.REG_F17, "F17"}, {49, arm64.REG_F18, "F18"}, {50, arm64.REG_F19, "F19"}, {51, arm64.REG_F20, "F20"}, {52, arm64.REG_F21, "F21"}, {53, arm64.REG_F22, "F22"}, {54, arm64.REG_F23, "F23"}, {55, arm64.REG_F24, "F24"}, {56, arm64.REG_F25, "F25"}, {57, arm64.REG_F26, "F26"}, {58, arm64.REG_F27, "F27"}, {59, arm64.REG_F28, "F28"}, {60, arm64.REG_F29, "F29"}, {61, arm64.REG_F30, "F30"}, {62, arm64.REG_F31, "F31"}, {63, 0, "SB"}, } var paramIntRegARM64 = []int8{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} var paramFloatRegARM64 = []int8{31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46} var gpRegMaskARM64 = regMask(335544319) var fpRegMaskARM64 = regMask(9223372034707292160) var specialRegMaskARM64 = regMask(0) var framepointerRegARM64 = int8(-1) var linkRegARM64 = int8(28) var registersLOONG64 = [...]Register{ {0, loong64.REG_R0, "R0"}, {1, loong64.REG_R1, "R1"}, {2, loong64.REGSP, "SP"}, {3, loong64.REG_R4, "R4"}, {4, loong64.REG_R5, "R5"}, {5, loong64.REG_R6, "R6"}, {6, loong64.REG_R7, "R7"}, {7, loong64.REG_R8, "R8"}, {8, loong64.REG_R9, "R9"}, {9, loong64.REG_R10, "R10"}, {10, loong64.REG_R11, "R11"}, {11, loong64.REG_R12, "R12"}, {12, loong64.REG_R13, "R13"}, {13, loong64.REG_R14, "R14"}, {14, loong64.REG_R15, "R15"}, {15, loong64.REG_R16, "R16"}, {16, loong64.REG_R17, "R17"}, {17, loong64.REG_R18, "R18"}, {18, loong64.REG_R19, "R19"}, {19, loong64.REG_R20, "R20"}, {20, loong64.REG_R21, "R21"}, {21, loong64.REGG, "g"}, {22, loong64.REG_R23, "R23"}, {23, loong64.REG_R24, "R24"}, {24, loong64.REG_R25, "R25"}, {25, loong64.REG_R26, "R26"}, {26, loong64.REG_R27, "R27"}, {27, loong64.REG_R28, "R28"}, {28, loong64.REG_R29, "R29"}, {29, loong64.REG_R31, "R31"}, {30, loong64.REG_F0, "F0"}, {31, loong64.REG_F1, "F1"}, {32, loong64.REG_F2, "F2"}, {33, loong64.REG_F3, "F3"}, {34, loong64.REG_F4, "F4"}, {35, loong64.REG_F5, "F5"}, {36, loong64.REG_F6, "F6"}, {37, loong64.REG_F7, "F7"}, {38, loong64.REG_F8, "F8"}, {39, loong64.REG_F9, "F9"}, {40, loong64.REG_F10, "F10"}, {41, loong64.REG_F11, "F11"}, {42, loong64.REG_F12, "F12"}, {43, loong64.REG_F13, "F13"}, {44, loong64.REG_F14, "F14"}, {45, loong64.REG_F15, "F15"}, {46, loong64.REG_F16, "F16"}, {47, loong64.REG_F17, "F17"}, {48, loong64.REG_F18, "F18"}, {49, loong64.REG_F19, "F19"}, {50, loong64.REG_F20, "F20"}, {51, loong64.REG_F21, "F21"}, {52, loong64.REG_F22, "F22"}, {53, loong64.REG_F23, "F23"}, {54, loong64.REG_F24, "F24"}, {55, loong64.REG_F25, "F25"}, {56, loong64.REG_F26, "F26"}, {57, loong64.REG_F27, "F27"}, {58, loong64.REG_F28, "F28"}, {59, loong64.REG_F29, "F29"}, {60, loong64.REG_F30, "F30"}, {61, loong64.REG_F31, "F31"}, {62, 0, "SB"}, } var paramIntRegLOONG64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18} var paramFloatRegLOONG64 = []int8{30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45} var gpRegMaskLOONG64 = regMask(1071644664) var fpRegMaskLOONG64 = regMask(4611686017353646080) var specialRegMaskLOONG64 = regMask(0) var framepointerRegLOONG64 = int8(-1) var linkRegLOONG64 = int8(1) var registersMIPS = [...]Register{ {0, mips.REG_R0, "R0"}, {1, mips.REG_R1, "R1"}, {2, mips.REG_R2, "R2"}, {3, mips.REG_R3, "R3"}, {4, mips.REG_R4, "R4"}, {5, mips.REG_R5, "R5"}, {6, mips.REG_R6, "R6"}, {7, mips.REG_R7, "R7"}, {8, mips.REG_R8, "R8"}, {9, mips.REG_R9, "R9"}, {10, mips.REG_R10, "R10"}, {11, mips.REG_R11, "R11"}, {12, mips.REG_R12, "R12"}, {13, mips.REG_R13, "R13"}, {14, mips.REG_R14, "R14"}, {15, mips.REG_R15, "R15"}, {16, mips.REG_R16, "R16"}, {17, mips.REG_R17, "R17"}, {18, mips.REG_R18, "R18"}, {19, mips.REG_R19, "R19"}, {20, mips.REG_R20, "R20"}, {21, mips.REG_R21, "R21"}, {22, mips.REG_R22, "R22"}, {23, mips.REG_R24, "R24"}, {24, mips.REG_R25, "R25"}, {25, mips.REG_R28, "R28"}, {26, mips.REGSP, "SP"}, {27, mips.REGG, "g"}, {28, mips.REG_R31, "R31"}, {29, mips.REG_F0, "F0"}, {30, mips.REG_F2, "F2"}, {31, mips.REG_F4, "F4"}, {32, mips.REG_F6, "F6"}, {33, mips.REG_F8, "F8"}, {34, mips.REG_F10, "F10"}, {35, mips.REG_F12, "F12"}, {36, mips.REG_F14, "F14"}, {37, mips.REG_F16, "F16"}, {38, mips.REG_F18, "F18"}, {39, mips.REG_F20, "F20"}, {40, mips.REG_F22, "F22"}, {41, mips.REG_F24, "F24"}, {42, mips.REG_F26, "F26"}, {43, mips.REG_F28, "F28"}, {44, mips.REG_F30, "F30"}, {45, mips.REG_HI, "HI"}, {46, mips.REG_LO, "LO"}, {47, 0, "SB"}, } var paramIntRegMIPS = []int8(nil) var paramFloatRegMIPS = []int8(nil) var gpRegMaskMIPS = regMask(335544318) var fpRegMaskMIPS = regMask(35183835217920) var specialRegMaskMIPS = regMask(105553116266496) var framepointerRegMIPS = int8(-1) var linkRegMIPS = int8(28) var registersMIPS64 = [...]Register{ {0, mips.REG_R0, "R0"}, {1, mips.REG_R1, "R1"}, {2, mips.REG_R2, "R2"}, {3, mips.REG_R3, "R3"}, {4, mips.REG_R4, "R4"}, {5, mips.REG_R5, "R5"}, {6, mips.REG_R6, "R6"}, {7, mips.REG_R7, "R7"}, {8, mips.REG_R8, "R8"}, {9, mips.REG_R9, "R9"}, {10, mips.REG_R10, "R10"}, {11, mips.REG_R11, "R11"}, {12, mips.REG_R12, "R12"}, {13, mips.REG_R13, "R13"}, {14, mips.REG_R14, "R14"}, {15, mips.REG_R15, "R15"}, {16, mips.REG_R16, "R16"}, {17, mips.REG_R17, "R17"}, {18, mips.REG_R18, "R18"}, {19, mips.REG_R19, "R19"}, {20, mips.REG_R20, "R20"}, {21, mips.REG_R21, "R21"}, {22, mips.REG_R22, "R22"}, {23, mips.REG_R24, "R24"}, {24, mips.REG_R25, "R25"}, {25, mips.REGSP, "SP"}, {26, mips.REGG, "g"}, {27, mips.REG_R31, "R31"}, {28, mips.REG_F0, "F0"}, {29, mips.REG_F1, "F1"}, {30, mips.REG_F2, "F2"}, {31, mips.REG_F3, "F3"}, {32, mips.REG_F4, "F4"}, {33, mips.REG_F5, "F5"}, {34, mips.REG_F6, "F6"}, {35, mips.REG_F7, "F7"}, {36, mips.REG_F8, "F8"}, {37, mips.REG_F9, "F9"}, {38, mips.REG_F10, "F10"}, {39, mips.REG_F11, "F11"}, {40, mips.REG_F12, "F12"}, {41, mips.REG_F13, "F13"}, {42, mips.REG_F14, "F14"}, {43, mips.REG_F15, "F15"}, {44, mips.REG_F16, "F16"}, {45, mips.REG_F17, "F17"}, {46, mips.REG_F18, "F18"}, {47, mips.REG_F19, "F19"}, {48, mips.REG_F20, "F20"}, {49, mips.REG_F21, "F21"}, {50, mips.REG_F22, "F22"}, {51, mips.REG_F23, "F23"}, {52, mips.REG_F24, "F24"}, {53, mips.REG_F25, "F25"}, {54, mips.REG_F26, "F26"}, {55, mips.REG_F27, "F27"}, {56, mips.REG_F28, "F28"}, {57, mips.REG_F29, "F29"}, {58, mips.REG_F30, "F30"}, {59, mips.REG_F31, "F31"}, {60, mips.REG_HI, "HI"}, {61, mips.REG_LO, "LO"}, {62, 0, "SB"}, } var paramIntRegMIPS64 = []int8(nil) var paramFloatRegMIPS64 = []int8(nil) var gpRegMaskMIPS64 = regMask(167772158) var fpRegMaskMIPS64 = regMask(1152921504338411520) var specialRegMaskMIPS64 = regMask(3458764513820540928) var framepointerRegMIPS64 = int8(-1) var linkRegMIPS64 = int8(27) var registersPPC64 = [...]Register{ {0, ppc64.REG_R0, "R0"}, {1, ppc64.REGSP, "SP"}, {2, 0, "SB"}, {3, ppc64.REG_R3, "R3"}, {4, ppc64.REG_R4, "R4"}, {5, ppc64.REG_R5, "R5"}, {6, ppc64.REG_R6, "R6"}, {7, ppc64.REG_R7, "R7"}, {8, ppc64.REG_R8, "R8"}, {9, ppc64.REG_R9, "R9"}, {10, ppc64.REG_R10, "R10"}, {11, ppc64.REG_R11, "R11"}, {12, ppc64.REG_R12, "R12"}, {13, ppc64.REG_R13, "R13"}, {14, ppc64.REG_R14, "R14"}, {15, ppc64.REG_R15, "R15"}, {16, ppc64.REG_R16, "R16"}, {17, ppc64.REG_R17, "R17"}, {18, ppc64.REG_R18, "R18"}, {19, ppc64.REG_R19, "R19"}, {20, ppc64.REG_R20, "R20"}, {21, ppc64.REG_R21, "R21"}, {22, ppc64.REG_R22, "R22"}, {23, ppc64.REG_R23, "R23"}, {24, ppc64.REG_R24, "R24"}, {25, ppc64.REG_R25, "R25"}, {26, ppc64.REG_R26, "R26"}, {27, ppc64.REG_R27, "R27"}, {28, ppc64.REG_R28, "R28"}, {29, ppc64.REG_R29, "R29"}, {30, ppc64.REGG, "g"}, {31, ppc64.REG_R31, "R31"}, {32, ppc64.REG_F0, "F0"}, {33, ppc64.REG_F1, "F1"}, {34, ppc64.REG_F2, "F2"}, {35, ppc64.REG_F3, "F3"}, {36, ppc64.REG_F4, "F4"}, {37, ppc64.REG_F5, "F5"}, {38, ppc64.REG_F6, "F6"}, {39, ppc64.REG_F7, "F7"}, {40, ppc64.REG_F8, "F8"}, {41, ppc64.REG_F9, "F9"}, {42, ppc64.REG_F10, "F10"}, {43, ppc64.REG_F11, "F11"}, {44, ppc64.REG_F12, "F12"}, {45, ppc64.REG_F13, "F13"}, {46, ppc64.REG_F14, "F14"}, {47, ppc64.REG_F15, "F15"}, {48, ppc64.REG_F16, "F16"}, {49, ppc64.REG_F17, "F17"}, {50, ppc64.REG_F18, "F18"}, {51, ppc64.REG_F19, "F19"}, {52, ppc64.REG_F20, "F20"}, {53, ppc64.REG_F21, "F21"}, {54, ppc64.REG_F22, "F22"}, {55, ppc64.REG_F23, "F23"}, {56, ppc64.REG_F24, "F24"}, {57, ppc64.REG_F25, "F25"}, {58, ppc64.REG_F26, "F26"}, {59, ppc64.REG_F27, "F27"}, {60, ppc64.REG_F28, "F28"}, {61, ppc64.REG_F29, "F29"}, {62, ppc64.REG_F30, "F30"}, {63, ppc64.REG_XER, "XER"}, } var paramIntRegPPC64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 16, 17} var paramFloatRegPPC64 = []int8{33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44} var gpRegMaskPPC64 = regMask(1073733624) var fpRegMaskPPC64 = regMask(9223372032559808512) var specialRegMaskPPC64 = regMask(9223372036854775808) var framepointerRegPPC64 = int8(-1) var linkRegPPC64 = int8(-1) var registersRISCV64 = [...]Register{ {0, riscv.REG_X0, "X0"}, {1, riscv.REGSP, "SP"}, {2, riscv.REG_X3, "X3"}, {3, riscv.REG_X4, "X4"}, {4, riscv.REG_X5, "X5"}, {5, riscv.REG_X6, "X6"}, {6, riscv.REG_X7, "X7"}, {7, riscv.REG_X8, "X8"}, {8, riscv.REG_X9, "X9"}, {9, riscv.REG_X10, "X10"}, {10, riscv.REG_X11, "X11"}, {11, riscv.REG_X12, "X12"}, {12, riscv.REG_X13, "X13"}, {13, riscv.REG_X14, "X14"}, {14, riscv.REG_X15, "X15"}, {15, riscv.REG_X16, "X16"}, {16, riscv.REG_X17, "X17"}, {17, riscv.REG_X18, "X18"}, {18, riscv.REG_X19, "X19"}, {19, riscv.REG_X20, "X20"}, {20, riscv.REG_X21, "X21"}, {21, riscv.REG_X22, "X22"}, {22, riscv.REG_X23, "X23"}, {23, riscv.REG_X24, "X24"}, {24, riscv.REG_X25, "X25"}, {25, riscv.REG_X26, "X26"}, {26, riscv.REGG, "g"}, {27, riscv.REG_X28, "X28"}, {28, riscv.REG_X29, "X29"}, {29, riscv.REG_X30, "X30"}, {30, riscv.REG_X31, "X31"}, {31, riscv.REG_F0, "F0"}, {32, riscv.REG_F1, "F1"}, {33, riscv.REG_F2, "F2"}, {34, riscv.REG_F3, "F3"}, {35, riscv.REG_F4, "F4"}, {36, riscv.REG_F5, "F5"}, {37, riscv.REG_F6, "F6"}, {38, riscv.REG_F7, "F7"}, {39, riscv.REG_F8, "F8"}, {40, riscv.REG_F9, "F9"}, {41, riscv.REG_F10, "F10"}, {42, riscv.REG_F11, "F11"}, {43, riscv.REG_F12, "F12"}, {44, riscv.REG_F13, "F13"}, {45, riscv.REG_F14, "F14"}, {46, riscv.REG_F15, "F15"}, {47, riscv.REG_F16, "F16"}, {48, riscv.REG_F17, "F17"}, {49, riscv.REG_F18, "F18"}, {50, riscv.REG_F19, "F19"}, {51, riscv.REG_F20, "F20"}, {52, riscv.REG_F21, "F21"}, {53, riscv.REG_F22, "F22"}, {54, riscv.REG_F23, "F23"}, {55, riscv.REG_F24, "F24"}, {56, riscv.REG_F25, "F25"}, {57, riscv.REG_F26, "F26"}, {58, riscv.REG_F27, "F27"}, {59, riscv.REG_F28, "F28"}, {60, riscv.REG_F29, "F29"}, {61, riscv.REG_F30, "F30"}, {62, riscv.REG_F31, "F31"}, {63, 0, "SB"}, } var paramIntRegRISCV64 = []int8{9, 10, 11, 12, 13, 14, 15, 16, 7, 8, 17, 18, 19, 20, 21, 22} var paramFloatRegRISCV64 = []int8{41, 42, 43, 44, 45, 46, 47, 48, 39, 40, 49, 50, 51, 52, 53, 54} var gpRegMaskRISCV64 = regMask(1006632944) var fpRegMaskRISCV64 = regMask(9223372034707292160) var specialRegMaskRISCV64 = regMask(0) var framepointerRegRISCV64 = int8(-1) var linkRegRISCV64 = int8(0) var registersS390X = [...]Register{ {0, s390x.REG_R0, "R0"}, {1, s390x.REG_R1, "R1"}, {2, s390x.REG_R2, "R2"}, {3, s390x.REG_R3, "R3"}, {4, s390x.REG_R4, "R4"}, {5, s390x.REG_R5, "R5"}, {6, s390x.REG_R6, "R6"}, {7, s390x.REG_R7, "R7"}, {8, s390x.REG_R8, "R8"}, {9, s390x.REG_R9, "R9"}, {10, s390x.REG_R10, "R10"}, {11, s390x.REG_R11, "R11"}, {12, s390x.REG_R12, "R12"}, {13, s390x.REGG, "g"}, {14, s390x.REG_R14, "R14"}, {15, s390x.REGSP, "SP"}, {16, s390x.REG_F0, "F0"}, {17, s390x.REG_F1, "F1"}, {18, s390x.REG_F2, "F2"}, {19, s390x.REG_F3, "F3"}, {20, s390x.REG_F4, "F4"}, {21, s390x.REG_F5, "F5"}, {22, s390x.REG_F6, "F6"}, {23, s390x.REG_F7, "F7"}, {24, s390x.REG_F8, "F8"}, {25, s390x.REG_F9, "F9"}, {26, s390x.REG_F10, "F10"}, {27, s390x.REG_F11, "F11"}, {28, s390x.REG_F12, "F12"}, {29, s390x.REG_F13, "F13"}, {30, s390x.REG_F14, "F14"}, {31, s390x.REG_F15, "F15"}, {32, 0, "SB"}, } var paramIntRegS390X = []int8(nil) var paramFloatRegS390X = []int8(nil) var gpRegMaskS390X = regMask(23551) var fpRegMaskS390X = regMask(4294901760) var specialRegMaskS390X = regMask(0) var framepointerRegS390X = int8(-1) var linkRegS390X = int8(14) var registersWasm = [...]Register{ {0, wasm.REG_R0, "R0"}, {1, wasm.REG_R1, "R1"}, {2, wasm.REG_R2, "R2"}, {3, wasm.REG_R3, "R3"}, {4, wasm.REG_R4, "R4"}, {5, wasm.REG_R5, "R5"}, {6, wasm.REG_R6, "R6"}, {7, wasm.REG_R7, "R7"}, {8, wasm.REG_R8, "R8"}, {9, wasm.REG_R9, "R9"}, {10, wasm.REG_R10, "R10"}, {11, wasm.REG_R11, "R11"}, {12, wasm.REG_R12, "R12"}, {13, wasm.REG_R13, "R13"}, {14, wasm.REG_R14, "R14"}, {15, wasm.REG_R15, "R15"}, {16, wasm.REG_F0, "F0"}, {17, wasm.REG_F1, "F1"}, {18, wasm.REG_F2, "F2"}, {19, wasm.REG_F3, "F3"}, {20, wasm.REG_F4, "F4"}, {21, wasm.REG_F5, "F5"}, {22, wasm.REG_F6, "F6"}, {23, wasm.REG_F7, "F7"}, {24, wasm.REG_F8, "F8"}, {25, wasm.REG_F9, "F9"}, {26, wasm.REG_F10, "F10"}, {27, wasm.REG_F11, "F11"}, {28, wasm.REG_F12, "F12"}, {29, wasm.REG_F13, "F13"}, {30, wasm.REG_F14, "F14"}, {31, wasm.REG_F15, "F15"}, {32, wasm.REG_F16, "F16"}, {33, wasm.REG_F17, "F17"}, {34, wasm.REG_F18, "F18"}, {35, wasm.REG_F19, "F19"}, {36, wasm.REG_F20, "F20"}, {37, wasm.REG_F21, "F21"}, {38, wasm.REG_F22, "F22"}, {39, wasm.REG_F23, "F23"}, {40, wasm.REG_F24, "F24"}, {41, wasm.REG_F25, "F25"}, {42, wasm.REG_F26, "F26"}, {43, wasm.REG_F27, "F27"}, {44, wasm.REG_F28, "F28"}, {45, wasm.REG_F29, "F29"}, {46, wasm.REG_F30, "F30"}, {47, wasm.REG_F31, "F31"}, {48, wasm.REGSP, "SP"}, {49, wasm.REGG, "g"}, {50, 0, "SB"}, } var paramIntRegWasm = []int8(nil) var paramFloatRegWasm = []int8(nil) var gpRegMaskWasm = regMask(65535) var fpRegMaskWasm = regMask(281474976645120) var fp32RegMaskWasm = regMask(4294901760) var fp64RegMaskWasm = regMask(281470681743360) var specialRegMaskWasm = regMask(0) var framepointerRegWasm = int8(-1) var linkRegWasm = int8(-1) -- diff -- @@ -2514,6 +2514,8 @@ OpRISCV64ANDI OpRISCV64CLZ OpRISCV64CLZW + OpRISCV64CPOP + OpRISCV64CPOPW OpRISCV64CTZ OpRISCV64CTZW OpRISCV64NOT @@ -33878,6 +33880,32 @@ name: "CLZW", argLen: 1, asm: riscv.ACLZW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CPOP", + argLen: 1, + asm: riscv.ACPOP, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CPOPW", + argLen: 1, + asm: riscv.ACPOPW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 -- diff -- # indent-heuristic: true @@ -2514,6 +2514,8 @@ OpRISCV64ANDI OpRISCV64CLZ OpRISCV64CLZW + OpRISCV64CPOP + OpRISCV64CPOPW OpRISCV64CTZ OpRISCV64CTZW OpRISCV64NOT @@ -33887,6 +33889,32 @@ }, }, }, + { + name: "CPOP", + argLen: 1, + asm: riscv.ACPOP, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CPOPW", + argLen: 1, + asm: riscv.ACPOPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, { name: "CTZ", argLen: 1, go_4d9dd3580624df413d65d83e467fcd6ad4a0168b_src_cmd_compile_internal_ssa_rewritegeneric.go.test000066400000000000000000112022461516001707200365030ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit 4d9dd3580624df413d65d83e467fcd6ad4a0168b file testdata/go_4d9dd3580624df413d65d83e467fcd6ad4a0168b_src_cmd_compile_internal_ssa_rewritegeneric.go.test -- x -- // Code generated from gen/generic.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "fmt" import "math" import "cmd/internal/obj" import "cmd/internal/objabi" import "cmd/compile/internal/types" var _ = fmt.Println // in case not otherwise used var _ = math.MinInt8 // in case not otherwise used var _ = obj.ANOP // in case not otherwise used var _ = objabi.GOROOT // in case not otherwise used var _ = types.TypeMem // in case not otherwise used func rewriteValuegeneric(v *Value) bool { switch v.Op { case OpAdd16: return rewriteValuegeneric_OpAdd16_0(v) || rewriteValuegeneric_OpAdd16_10(v) || rewriteValuegeneric_OpAdd16_20(v) || rewriteValuegeneric_OpAdd16_30(v) case OpAdd32: return rewriteValuegeneric_OpAdd32_0(v) || rewriteValuegeneric_OpAdd32_10(v) || rewriteValuegeneric_OpAdd32_20(v) || rewriteValuegeneric_OpAdd32_30(v) case OpAdd32F: return rewriteValuegeneric_OpAdd32F_0(v) case OpAdd64: return rewriteValuegeneric_OpAdd64_0(v) || rewriteValuegeneric_OpAdd64_10(v) || rewriteValuegeneric_OpAdd64_20(v) || rewriteValuegeneric_OpAdd64_30(v) case OpAdd64F: return rewriteValuegeneric_OpAdd64F_0(v) case OpAdd8: return rewriteValuegeneric_OpAdd8_0(v) || rewriteValuegeneric_OpAdd8_10(v) || rewriteValuegeneric_OpAdd8_20(v) || rewriteValuegeneric_OpAdd8_30(v) case OpAddPtr: return rewriteValuegeneric_OpAddPtr_0(v) case OpAnd16: return rewriteValuegeneric_OpAnd16_0(v) || rewriteValuegeneric_OpAnd16_10(v) || rewriteValuegeneric_OpAnd16_20(v) case OpAnd32: return rewriteValuegeneric_OpAnd32_0(v) || rewriteValuegeneric_OpAnd32_10(v) || rewriteValuegeneric_OpAnd32_20(v) case OpAnd64: return rewriteValuegeneric_OpAnd64_0(v) || rewriteValuegeneric_OpAnd64_10(v) || rewriteValuegeneric_OpAnd64_20(v) case OpAnd8: return rewriteValuegeneric_OpAnd8_0(v) || rewriteValuegeneric_OpAnd8_10(v) || rewriteValuegeneric_OpAnd8_20(v) case OpArraySelect: return rewriteValuegeneric_OpArraySelect_0(v) case OpCom16: return rewriteValuegeneric_OpCom16_0(v) case OpCom32: return rewriteValuegeneric_OpCom32_0(v) case OpCom64: return rewriteValuegeneric_OpCom64_0(v) case OpCom8: return rewriteValuegeneric_OpCom8_0(v) case OpConstInterface: return rewriteValuegeneric_OpConstInterface_0(v) case OpConstSlice: return rewriteValuegeneric_OpConstSlice_0(v) case OpConstString: return rewriteValuegeneric_OpConstString_0(v) case OpConvert: return rewriteValuegeneric_OpConvert_0(v) case OpCvt32Fto32: return rewriteValuegeneric_OpCvt32Fto32_0(v) case OpCvt32Fto64: return rewriteValuegeneric_OpCvt32Fto64_0(v) case OpCvt32Fto64F: return rewriteValuegeneric_OpCvt32Fto64F_0(v) case OpCvt32to32F: return rewriteValuegeneric_OpCvt32to32F_0(v) case OpCvt32to64F: return rewriteValuegeneric_OpCvt32to64F_0(v) case OpCvt64Fto32: return rewriteValuegeneric_OpCvt64Fto32_0(v) case OpCvt64Fto32F: return rewriteValuegeneric_OpCvt64Fto32F_0(v) case OpCvt64Fto64: return rewriteValuegeneric_OpCvt64Fto64_0(v) case OpCvt64to32F: return rewriteValuegeneric_OpCvt64to32F_0(v) case OpCvt64to64F: return rewriteValuegeneric_OpCvt64to64F_0(v) case OpDiv16: return rewriteValuegeneric_OpDiv16_0(v) case OpDiv16u: return rewriteValuegeneric_OpDiv16u_0(v) case OpDiv32: return rewriteValuegeneric_OpDiv32_0(v) case OpDiv32F: return rewriteValuegeneric_OpDiv32F_0(v) case OpDiv32u: return rewriteValuegeneric_OpDiv32u_0(v) case OpDiv64: return rewriteValuegeneric_OpDiv64_0(v) case OpDiv64F: return rewriteValuegeneric_OpDiv64F_0(v) case OpDiv64u: return rewriteValuegeneric_OpDiv64u_0(v) case OpDiv8: return rewriteValuegeneric_OpDiv8_0(v) case OpDiv8u: return rewriteValuegeneric_OpDiv8u_0(v) case OpEq16: return rewriteValuegeneric_OpEq16_0(v) || rewriteValuegeneric_OpEq16_10(v) || rewriteValuegeneric_OpEq16_20(v) || rewriteValuegeneric_OpEq16_30(v) || rewriteValuegeneric_OpEq16_40(v) case OpEq32: return rewriteValuegeneric_OpEq32_0(v) || rewriteValuegeneric_OpEq32_10(v) || rewriteValuegeneric_OpEq32_20(v) || rewriteValuegeneric_OpEq32_30(v) || rewriteValuegeneric_OpEq32_40(v) || rewriteValuegeneric_OpEq32_50(v) || rewriteValuegeneric_OpEq32_60(v) case OpEq32F: return rewriteValuegeneric_OpEq32F_0(v) case OpEq64: return rewriteValuegeneric_OpEq64_0(v) || rewriteValuegeneric_OpEq64_10(v) || rewriteValuegeneric_OpEq64_20(v) || rewriteValuegeneric_OpEq64_30(v) case OpEq64F: return rewriteValuegeneric_OpEq64F_0(v) case OpEq8: return rewriteValuegeneric_OpEq8_0(v) || rewriteValuegeneric_OpEq8_10(v) || rewriteValuegeneric_OpEq8_20(v) case OpEqB: return rewriteValuegeneric_OpEqB_0(v) case OpEqInter: return rewriteValuegeneric_OpEqInter_0(v) case OpEqPtr: return rewriteValuegeneric_OpEqPtr_0(v) || rewriteValuegeneric_OpEqPtr_10(v) || rewriteValuegeneric_OpEqPtr_20(v) case OpEqSlice: return rewriteValuegeneric_OpEqSlice_0(v) case OpGeq16: return rewriteValuegeneric_OpGeq16_0(v) case OpGeq16U: return rewriteValuegeneric_OpGeq16U_0(v) case OpGeq32: return rewriteValuegeneric_OpGeq32_0(v) case OpGeq32F: return rewriteValuegeneric_OpGeq32F_0(v) case OpGeq32U: return rewriteValuegeneric_OpGeq32U_0(v) case OpGeq64: return rewriteValuegeneric_OpGeq64_0(v) case OpGeq64F: return rewriteValuegeneric_OpGeq64F_0(v) case OpGeq64U: return rewriteValuegeneric_OpGeq64U_0(v) case OpGeq8: return rewriteValuegeneric_OpGeq8_0(v) case OpGeq8U: return rewriteValuegeneric_OpGeq8U_0(v) case OpGreater16: return rewriteValuegeneric_OpGreater16_0(v) case OpGreater16U: return rewriteValuegeneric_OpGreater16U_0(v) case OpGreater32: return rewriteValuegeneric_OpGreater32_0(v) case OpGreater32F: return rewriteValuegeneric_OpGreater32F_0(v) case OpGreater32U: return rewriteValuegeneric_OpGreater32U_0(v) case OpGreater64: return rewriteValuegeneric_OpGreater64_0(v) case OpGreater64F: return rewriteValuegeneric_OpGreater64F_0(v) case OpGreater64U: return rewriteValuegeneric_OpGreater64U_0(v) case OpGreater8: return rewriteValuegeneric_OpGreater8_0(v) case OpGreater8U: return rewriteValuegeneric_OpGreater8U_0(v) case OpIMake: return rewriteValuegeneric_OpIMake_0(v) case OpInterCall: return rewriteValuegeneric_OpInterCall_0(v) case OpIsInBounds: return rewriteValuegeneric_OpIsInBounds_0(v) || rewriteValuegeneric_OpIsInBounds_10(v) || rewriteValuegeneric_OpIsInBounds_20(v) || rewriteValuegeneric_OpIsInBounds_30(v) case OpIsNonNil: return rewriteValuegeneric_OpIsNonNil_0(v) case OpIsSliceInBounds: return rewriteValuegeneric_OpIsSliceInBounds_0(v) case OpLeq16: return rewriteValuegeneric_OpLeq16_0(v) case OpLeq16U: return rewriteValuegeneric_OpLeq16U_0(v) case OpLeq32: return rewriteValuegeneric_OpLeq32_0(v) case OpLeq32F: return rewriteValuegeneric_OpLeq32F_0(v) case OpLeq32U: return rewriteValuegeneric_OpLeq32U_0(v) case OpLeq64: return rewriteValuegeneric_OpLeq64_0(v) case OpLeq64F: return rewriteValuegeneric_OpLeq64F_0(v) case OpLeq64U: return rewriteValuegeneric_OpLeq64U_0(v) case OpLeq8: return rewriteValuegeneric_OpLeq8_0(v) case OpLeq8U: return rewriteValuegeneric_OpLeq8U_0(v) case OpLess16: return rewriteValuegeneric_OpLess16_0(v) case OpLess16U: return rewriteValuegeneric_OpLess16U_0(v) case OpLess32: return rewriteValuegeneric_OpLess32_0(v) case OpLess32F: return rewriteValuegeneric_OpLess32F_0(v) case OpLess32U: return rewriteValuegeneric_OpLess32U_0(v) case OpLess64: return rewriteValuegeneric_OpLess64_0(v) case OpLess64F: return rewriteValuegeneric_OpLess64F_0(v) case OpLess64U: return rewriteValuegeneric_OpLess64U_0(v) case OpLess8: return rewriteValuegeneric_OpLess8_0(v) case OpLess8U: return rewriteValuegeneric_OpLess8U_0(v) case OpLoad: return rewriteValuegeneric_OpLoad_0(v) || rewriteValuegeneric_OpLoad_10(v) || rewriteValuegeneric_OpLoad_20(v) case OpLsh16x16: return rewriteValuegeneric_OpLsh16x16_0(v) case OpLsh16x32: return rewriteValuegeneric_OpLsh16x32_0(v) case OpLsh16x64: return rewriteValuegeneric_OpLsh16x64_0(v) case OpLsh16x8: return rewriteValuegeneric_OpLsh16x8_0(v) case OpLsh32x16: return rewriteValuegeneric_OpLsh32x16_0(v) case OpLsh32x32: return rewriteValuegeneric_OpLsh32x32_0(v) case OpLsh32x64: return rewriteValuegeneric_OpLsh32x64_0(v) case OpLsh32x8: return rewriteValuegeneric_OpLsh32x8_0(v) case OpLsh64x16: return rewriteValuegeneric_OpLsh64x16_0(v) case OpLsh64x32: return rewriteValuegeneric_OpLsh64x32_0(v) case OpLsh64x64: return rewriteValuegeneric_OpLsh64x64_0(v) case OpLsh64x8: return rewriteValuegeneric_OpLsh64x8_0(v) case OpLsh8x16: return rewriteValuegeneric_OpLsh8x16_0(v) case OpLsh8x32: return rewriteValuegeneric_OpLsh8x32_0(v) case OpLsh8x64: return rewriteValuegeneric_OpLsh8x64_0(v) case OpLsh8x8: return rewriteValuegeneric_OpLsh8x8_0(v) case OpMod16: return rewriteValuegeneric_OpMod16_0(v) case OpMod16u: return rewriteValuegeneric_OpMod16u_0(v) case OpMod32: return rewriteValuegeneric_OpMod32_0(v) case OpMod32u: return rewriteValuegeneric_OpMod32u_0(v) case OpMod64: return rewriteValuegeneric_OpMod64_0(v) case OpMod64u: return rewriteValuegeneric_OpMod64u_0(v) case OpMod8: return rewriteValuegeneric_OpMod8_0(v) case OpMod8u: return rewriteValuegeneric_OpMod8u_0(v) case OpMove: return rewriteValuegeneric_OpMove_0(v) || rewriteValuegeneric_OpMove_10(v) || rewriteValuegeneric_OpMove_20(v) case OpMul16: return rewriteValuegeneric_OpMul16_0(v) || rewriteValuegeneric_OpMul16_10(v) case OpMul32: return rewriteValuegeneric_OpMul32_0(v) || rewriteValuegeneric_OpMul32_10(v) case OpMul32F: return rewriteValuegeneric_OpMul32F_0(v) case OpMul64: return rewriteValuegeneric_OpMul64_0(v) || rewriteValuegeneric_OpMul64_10(v) case OpMul64F: return rewriteValuegeneric_OpMul64F_0(v) case OpMul8: return rewriteValuegeneric_OpMul8_0(v) || rewriteValuegeneric_OpMul8_10(v) case OpNeg16: return rewriteValuegeneric_OpNeg16_0(v) case OpNeg32: return rewriteValuegeneric_OpNeg32_0(v) case OpNeg32F: return rewriteValuegeneric_OpNeg32F_0(v) case OpNeg64: return rewriteValuegeneric_OpNeg64_0(v) case OpNeg64F: return rewriteValuegeneric_OpNeg64F_0(v) case OpNeg8: return rewriteValuegeneric_OpNeg8_0(v) case OpNeq16: return rewriteValuegeneric_OpNeq16_0(v) case OpNeq32: return rewriteValuegeneric_OpNeq32_0(v) case OpNeq32F: return rewriteValuegeneric_OpNeq32F_0(v) case OpNeq64: return rewriteValuegeneric_OpNeq64_0(v) case OpNeq64F: return rewriteValuegeneric_OpNeq64F_0(v) case OpNeq8: return rewriteValuegeneric_OpNeq8_0(v) case OpNeqB: return rewriteValuegeneric_OpNeqB_0(v) case OpNeqInter: return rewriteValuegeneric_OpNeqInter_0(v) case OpNeqPtr: return rewriteValuegeneric_OpNeqPtr_0(v) || rewriteValuegeneric_OpNeqPtr_10(v) || rewriteValuegeneric_OpNeqPtr_20(v) case OpNeqSlice: return rewriteValuegeneric_OpNeqSlice_0(v) case OpNilCheck: return rewriteValuegeneric_OpNilCheck_0(v) case OpNot: return rewriteValuegeneric_OpNot_0(v) || rewriteValuegeneric_OpNot_10(v) || rewriteValuegeneric_OpNot_20(v) || rewriteValuegeneric_OpNot_30(v) || rewriteValuegeneric_OpNot_40(v) case OpOffPtr: return rewriteValuegeneric_OpOffPtr_0(v) case OpOr16: return rewriteValuegeneric_OpOr16_0(v) || rewriteValuegeneric_OpOr16_10(v) || rewriteValuegeneric_OpOr16_20(v) case OpOr32: return rewriteValuegeneric_OpOr32_0(v) || rewriteValuegeneric_OpOr32_10(v) || rewriteValuegeneric_OpOr32_20(v) case OpOr64: return rewriteValuegeneric_OpOr64_0(v) || rewriteValuegeneric_OpOr64_10(v) || rewriteValuegeneric_OpOr64_20(v) case OpOr8: return rewriteValuegeneric_OpOr8_0(v) || rewriteValuegeneric_OpOr8_10(v) || rewriteValuegeneric_OpOr8_20(v) case OpPhi: return rewriteValuegeneric_OpPhi_0(v) case OpPtrIndex: return rewriteValuegeneric_OpPtrIndex_0(v) case OpRotateLeft16: return rewriteValuegeneric_OpRotateLeft16_0(v) case OpRotateLeft32: return rewriteValuegeneric_OpRotateLeft32_0(v) case OpRotateLeft64: return rewriteValuegeneric_OpRotateLeft64_0(v) case OpRotateLeft8: return rewriteValuegeneric_OpRotateLeft8_0(v) case OpRound32F: return rewriteValuegeneric_OpRound32F_0(v) case OpRound64F: return rewriteValuegeneric_OpRound64F_0(v) case OpRsh16Ux16: return rewriteValuegeneric_OpRsh16Ux16_0(v) case OpRsh16Ux32: return rewriteValuegeneric_OpRsh16Ux32_0(v) case OpRsh16Ux64: return rewriteValuegeneric_OpRsh16Ux64_0(v) case OpRsh16Ux8: return rewriteValuegeneric_OpRsh16Ux8_0(v) case OpRsh16x16: return rewriteValuegeneric_OpRsh16x16_0(v) case OpRsh16x32: return rewriteValuegeneric_OpRsh16x32_0(v) case OpRsh16x64: return rewriteValuegeneric_OpRsh16x64_0(v) case OpRsh16x8: return rewriteValuegeneric_OpRsh16x8_0(v) case OpRsh32Ux16: return rewriteValuegeneric_OpRsh32Ux16_0(v) case OpRsh32Ux32: return rewriteValuegeneric_OpRsh32Ux32_0(v) case OpRsh32Ux64: return rewriteValuegeneric_OpRsh32Ux64_0(v) case OpRsh32Ux8: return rewriteValuegeneric_OpRsh32Ux8_0(v) case OpRsh32x16: return rewriteValuegeneric_OpRsh32x16_0(v) case OpRsh32x32: return rewriteValuegeneric_OpRsh32x32_0(v) case OpRsh32x64: return rewriteValuegeneric_OpRsh32x64_0(v) case OpRsh32x8: return rewriteValuegeneric_OpRsh32x8_0(v) case OpRsh64Ux16: return rewriteValuegeneric_OpRsh64Ux16_0(v) case OpRsh64Ux32: return rewriteValuegeneric_OpRsh64Ux32_0(v) case OpRsh64Ux64: return rewriteValuegeneric_OpRsh64Ux64_0(v) case OpRsh64Ux8: return rewriteValuegeneric_OpRsh64Ux8_0(v) case OpRsh64x16: return rewriteValuegeneric_OpRsh64x16_0(v) case OpRsh64x32: return rewriteValuegeneric_OpRsh64x32_0(v) case OpRsh64x64: return rewriteValuegeneric_OpRsh64x64_0(v) case OpRsh64x8: return rewriteValuegeneric_OpRsh64x8_0(v) case OpRsh8Ux16: return rewriteValuegeneric_OpRsh8Ux16_0(v) case OpRsh8Ux32: return rewriteValuegeneric_OpRsh8Ux32_0(v) case OpRsh8Ux64: return rewriteValuegeneric_OpRsh8Ux64_0(v) case OpRsh8Ux8: return rewriteValuegeneric_OpRsh8Ux8_0(v) case OpRsh8x16: return rewriteValuegeneric_OpRsh8x16_0(v) case OpRsh8x32: return rewriteValuegeneric_OpRsh8x32_0(v) case OpRsh8x64: return rewriteValuegeneric_OpRsh8x64_0(v) case OpRsh8x8: return rewriteValuegeneric_OpRsh8x8_0(v) case OpSelect0: return rewriteValuegeneric_OpSelect0_0(v) case OpSelect1: return rewriteValuegeneric_OpSelect1_0(v) case OpSignExt16to32: return rewriteValuegeneric_OpSignExt16to32_0(v) case OpSignExt16to64: return rewriteValuegeneric_OpSignExt16to64_0(v) case OpSignExt32to64: return rewriteValuegeneric_OpSignExt32to64_0(v) case OpSignExt8to16: return rewriteValuegeneric_OpSignExt8to16_0(v) case OpSignExt8to32: return rewriteValuegeneric_OpSignExt8to32_0(v) case OpSignExt8to64: return rewriteValuegeneric_OpSignExt8to64_0(v) case OpSliceCap: return rewriteValuegeneric_OpSliceCap_0(v) case OpSliceLen: return rewriteValuegeneric_OpSliceLen_0(v) case OpSlicePtr: return rewriteValuegeneric_OpSlicePtr_0(v) case OpSlicemask: return rewriteValuegeneric_OpSlicemask_0(v) case OpSqrt: return rewriteValuegeneric_OpSqrt_0(v) case OpStaticCall: return rewriteValuegeneric_OpStaticCall_0(v) case OpStore: return rewriteValuegeneric_OpStore_0(v) || rewriteValuegeneric_OpStore_10(v) || rewriteValuegeneric_OpStore_20(v) case OpStringLen: return rewriteValuegeneric_OpStringLen_0(v) case OpStringPtr: return rewriteValuegeneric_OpStringPtr_0(v) case OpStructSelect: return rewriteValuegeneric_OpStructSelect_0(v) || rewriteValuegeneric_OpStructSelect_10(v) case OpSub16: return rewriteValuegeneric_OpSub16_0(v) || rewriteValuegeneric_OpSub16_10(v) case OpSub32: return rewriteValuegeneric_OpSub32_0(v) || rewriteValuegeneric_OpSub32_10(v) case OpSub32F: return rewriteValuegeneric_OpSub32F_0(v) case OpSub64: return rewriteValuegeneric_OpSub64_0(v) || rewriteValuegeneric_OpSub64_10(v) case OpSub64F: return rewriteValuegeneric_OpSub64F_0(v) case OpSub8: return rewriteValuegeneric_OpSub8_0(v) || rewriteValuegeneric_OpSub8_10(v) case OpTrunc16to8: return rewriteValuegeneric_OpTrunc16to8_0(v) case OpTrunc32to16: return rewriteValuegeneric_OpTrunc32to16_0(v) case OpTrunc32to8: return rewriteValuegeneric_OpTrunc32to8_0(v) case OpTrunc64to16: return rewriteValuegeneric_OpTrunc64to16_0(v) case OpTrunc64to32: return rewriteValuegeneric_OpTrunc64to32_0(v) case OpTrunc64to8: return rewriteValuegeneric_OpTrunc64to8_0(v) case OpXor16: return rewriteValuegeneric_OpXor16_0(v) || rewriteValuegeneric_OpXor16_10(v) case OpXor32: return rewriteValuegeneric_OpXor32_0(v) || rewriteValuegeneric_OpXor32_10(v) case OpXor64: return rewriteValuegeneric_OpXor64_0(v) || rewriteValuegeneric_OpXor64_10(v) case OpXor8: return rewriteValuegeneric_OpXor8_0(v) || rewriteValuegeneric_OpXor8_10(v) case OpZero: return rewriteValuegeneric_OpZero_0(v) case OpZeroExt16to32: return rewriteValuegeneric_OpZeroExt16to32_0(v) case OpZeroExt16to64: return rewriteValuegeneric_OpZeroExt16to64_0(v) case OpZeroExt32to64: return rewriteValuegeneric_OpZeroExt32to64_0(v) case OpZeroExt8to16: return rewriteValuegeneric_OpZeroExt8to16_0(v) case OpZeroExt8to32: return rewriteValuegeneric_OpZeroExt8to32_0(v) case OpZeroExt8to64: return rewriteValuegeneric_OpZeroExt8to64_0(v) } return false } func rewriteValuegeneric_OpAdd16_0(v *Value) bool { b := v.Block // match: (Add16 (Const16 [c]) (Const16 [d])) // cond: // result: (Const16 [int64(int16(c+d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c + d)) return true } // match: (Add16 (Const16 [d]) (Const16 [c])) // cond: // result: (Const16 [int64(int16(c+d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c + d)) return true } // match: (Add16 (Mul16 x y) (Mul16 x z)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 y x) (Mul16 x z)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 x y) (Mul16 z x)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 y x) (Mul16 z x)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 x z) (Mul16 x y)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 z x) (Mul16 x y)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 x z) (Mul16 y x)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 z x) (Mul16 y x)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd16_10(v *Value) bool { b := v.Block // match: (Add16 (Const16 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add16 x (Const16 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add16 (Const16 [1]) (Com16 x)) // cond: // result: (Neg16 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpCom16 { break } x := v_1.Args[0] v.reset(OpNeg16) v.AddArg(x) return true } // match: (Add16 (Com16 x) (Const16 [1])) // cond: // result: (Neg16 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpCom16 { break } x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 1 { break } v.reset(OpNeg16) v.AddArg(x) return true } // match: (Add16 (Add16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Add16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add16 (Add16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Add16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add16 x (Add16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Add16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add16 x (Add16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Add16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add16 (Sub16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 x (Sub16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd16_20(v *Value) bool { b := v.Block // match: (Add16 x (Sub16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Sub16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Sub16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub16 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add16 x (Sub16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add16 x (Sub16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add16 (Sub16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub16 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add16 (Const16 [c]) (Add16 (Const16 [d]) x)) // cond: // result: (Add16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add16 (Const16 [c]) (Add16 x (Const16 [d]))) // cond: // result: (Add16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add16 (Add16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Add16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add16 (Add16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Add16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd16_30(v *Value) bool { b := v.Block // match: (Add16 (Const16 [c]) (Sub16 (Const16 [d]) x)) // cond: // result: (Sub16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add16 (Sub16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Sub16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add16 (Const16 [c]) (Sub16 x (Const16 [d]))) // cond: // result: (Add16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add16 (Sub16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Add16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd32_0(v *Value) bool { b := v.Block // match: (Add32 (Const32 [c]) (Const32 [d])) // cond: // result: (Const32 [int64(int32(c+d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c + d)) return true } // match: (Add32 (Const32 [d]) (Const32 [c])) // cond: // result: (Const32 [int64(int32(c+d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c + d)) return true } // match: (Add32 (Mul32 x y) (Mul32 x z)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 y x) (Mul32 x z)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 x y) (Mul32 z x)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 y x) (Mul32 z x)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 x z) (Mul32 x y)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 z x) (Mul32 x y)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 x z) (Mul32 y x)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 z x) (Mul32 y x)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd32_10(v *Value) bool { b := v.Block // match: (Add32 (Const32 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add32 x (Const32 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add32 (Const32 [1]) (Com32 x)) // cond: // result: (Neg32 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpCom32 { break } x := v_1.Args[0] v.reset(OpNeg32) v.AddArg(x) return true } // match: (Add32 (Com32 x) (Const32 [1])) // cond: // result: (Neg32 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpCom32 { break } x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 1 { break } v.reset(OpNeg32) v.AddArg(x) return true } // match: (Add32 (Add32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Add32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add32 (Add32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Add32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add32 x (Add32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Add32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add32 x (Add32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Add32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add32 (Sub32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 x (Sub32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd32_20(v *Value) bool { b := v.Block // match: (Add32 x (Sub32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Sub32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Sub32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub32 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add32 x (Sub32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add32 x (Sub32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add32 (Sub32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub32 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add32 (Const32 [c]) (Add32 (Const32 [d]) x)) // cond: // result: (Add32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add32 (Const32 [c]) (Add32 x (Const32 [d]))) // cond: // result: (Add32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add32 (Add32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Add32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add32 (Add32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Add32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd32_30(v *Value) bool { b := v.Block // match: (Add32 (Const32 [c]) (Sub32 (Const32 [d]) x)) // cond: // result: (Sub32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add32 (Sub32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Sub32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add32 (Const32 [c]) (Sub32 x (Const32 [d]))) // cond: // result: (Add32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add32 (Sub32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Add32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd32F_0(v *Value) bool { // match: (Add32F (Const32F [c]) (Const32F [d])) // cond: // result: (Const32F [auxFrom32F(auxTo32F(c) + auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(auxTo32F(c) + auxTo32F(d)) return true } // match: (Add32F (Const32F [d]) (Const32F [c])) // cond: // result: (Const32F [auxFrom32F(auxTo32F(c) + auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } c := v_1.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(auxTo32F(c) + auxTo32F(d)) return true } return false } func rewriteValuegeneric_OpAdd64_0(v *Value) bool { b := v.Block // match: (Add64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c+d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c + d return true } // match: (Add64 (Const64 [d]) (Const64 [c])) // cond: // result: (Const64 [c+d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c + d return true } // match: (Add64 (Mul64 x y) (Mul64 x z)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 y x) (Mul64 x z)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 x y) (Mul64 z x)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 y x) (Mul64 z x)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 x z) (Mul64 x y)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 z x) (Mul64 x y)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 x z) (Mul64 y x)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 z x) (Mul64 y x)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd64_10(v *Value) bool { b := v.Block // match: (Add64 (Const64 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add64 (Const64 [1]) (Com64 x)) // cond: // result: (Neg64 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpCom64 { break } x := v_1.Args[0] v.reset(OpNeg64) v.AddArg(x) return true } // match: (Add64 (Com64 x) (Const64 [1])) // cond: // result: (Neg64 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpCom64 { break } x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 1 { break } v.reset(OpNeg64) v.AddArg(x) return true } // match: (Add64 (Add64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Add64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add64 (Add64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Add64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add64 x (Add64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Add64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add64 x (Add64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Add64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add64 (Sub64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 x (Sub64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd64_20(v *Value) bool { b := v.Block // match: (Add64 x (Sub64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Sub64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Sub64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub64 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add64 x (Sub64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add64 x (Sub64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add64 (Sub64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub64 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add64 (Const64 [c]) (Add64 (Const64 [d]) x)) // cond: // result: (Add64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } // match: (Add64 (Const64 [c]) (Add64 x (Const64 [d]))) // cond: // result: (Add64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } // match: (Add64 (Add64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Add64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } // match: (Add64 (Add64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Add64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd64_30(v *Value) bool { b := v.Block // match: (Add64 (Const64 [c]) (Sub64 (Const64 [d]) x)) // cond: // result: (Sub64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } // match: (Add64 (Sub64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Sub64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } // match: (Add64 (Const64 [c]) (Sub64 x (Const64 [d]))) // cond: // result: (Add64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Add64 (Sub64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Add64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd64F_0(v *Value) bool { // match: (Add64F (Const64F [c]) (Const64F [d])) // cond: // result: (Const64F [auxFrom64F(auxTo64F(c) + auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(auxTo64F(c) + auxTo64F(d)) return true } // match: (Add64F (Const64F [d]) (Const64F [c])) // cond: // result: (Const64F [auxFrom64F(auxTo64F(c) + auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } c := v_1.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(auxTo64F(c) + auxTo64F(d)) return true } return false } func rewriteValuegeneric_OpAdd8_0(v *Value) bool { b := v.Block // match: (Add8 (Const8 [c]) (Const8 [d])) // cond: // result: (Const8 [int64(int8(c+d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c + d)) return true } // match: (Add8 (Const8 [d]) (Const8 [c])) // cond: // result: (Const8 [int64(int8(c+d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c + d)) return true } // match: (Add8 (Mul8 x y) (Mul8 x z)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 y x) (Mul8 x z)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 x y) (Mul8 z x)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 y x) (Mul8 z x)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 x z) (Mul8 x y)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 z x) (Mul8 x y)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 x z) (Mul8 y x)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 z x) (Mul8 y x)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd8_10(v *Value) bool { b := v.Block // match: (Add8 (Const8 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add8 x (Const8 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add8 (Const8 [1]) (Com8 x)) // cond: // result: (Neg8 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpCom8 { break } x := v_1.Args[0] v.reset(OpNeg8) v.AddArg(x) return true } // match: (Add8 (Com8 x) (Const8 [1])) // cond: // result: (Neg8 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpCom8 { break } x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 1 { break } v.reset(OpNeg8) v.AddArg(x) return true } // match: (Add8 (Add8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Add8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add8 (Add8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Add8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add8 x (Add8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Add8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add8 x (Add8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Add8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add8 (Sub8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 x (Sub8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd8_20(v *Value) bool { b := v.Block // match: (Add8 x (Sub8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Sub8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Sub8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub8 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add8 x (Sub8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add8 x (Sub8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add8 (Sub8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub8 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add8 (Const8 [c]) (Add8 (Const8 [d]) x)) // cond: // result: (Add8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add8 (Const8 [c]) (Add8 x (Const8 [d]))) // cond: // result: (Add8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add8 (Add8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Add8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add8 (Add8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Add8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd8_30(v *Value) bool { b := v.Block // match: (Add8 (Const8 [c]) (Sub8 (Const8 [d]) x)) // cond: // result: (Sub8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add8 (Sub8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Sub8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add8 (Const8 [c]) (Sub8 x (Const8 [d]))) // cond: // result: (Add8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add8 (Sub8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Add8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAddPtr_0(v *Value) bool { // match: (AddPtr x (Const64 [c])) // cond: // result: (OffPtr x [c]) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpOffPtr) v.Type = t v.AuxInt = c v.AddArg(x) return true } // match: (AddPtr x (Const32 [c])) // cond: // result: (OffPtr x [c]) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpOffPtr) v.Type = t v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd16_0(v *Value) bool { // match: (And16 (Const16 [c]) (Const16 [d])) // cond: // result: (Const16 [int64(int16(c&d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c & d)) return true } // match: (And16 (Const16 [d]) (Const16 [c])) // cond: // result: (Const16 [int64(int16(c&d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c & d)) return true } // match: (And16 (Const16 [m]) (Rsh16Ux64 _ (Const64 [c]))) // cond: c >= 64-ntz(m) // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpRsh16Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (And16 (Rsh16Ux64 _ (Const64 [c])) (Const16 [m])) // cond: c >= 64-ntz(m) // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } m := v_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (And16 (Const16 [m]) (Lsh16x64 _ (Const64 [c]))) // cond: c >= 64-nlz(m) // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpLsh16x64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (And16 (Lsh16x64 _ (Const64 [c])) (Const16 [m])) // cond: c >= 64-nlz(m) // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } m := v_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (And16 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And16 (Const16 [-1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And16 x (Const16 [-1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And16 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpAnd16_10(v *Value) bool { b := v.Block // match: (And16 _ (Const16 [0])) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (And16 x (And16 x y)) // cond: // result: (And16 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpAnd16) v.AddArg(x) v.AddArg(y) return true } // match: (And16 x (And16 y x)) // cond: // result: (And16 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpAnd16) v.AddArg(x) v.AddArg(y) return true } // match: (And16 (And16 x y) x) // cond: // result: (And16 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpAnd16) v.AddArg(x) v.AddArg(y) return true } // match: (And16 (And16 y x) x) // cond: // result: (And16 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpAnd16) v.AddArg(x) v.AddArg(y) return true } // match: (And16 (And16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (And16 i (And16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAnd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And16 (And16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (And16 i (And16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAnd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And16 x (And16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (And16 i (And16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAnd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And16 x (And16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (And16 i (And16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAnd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And16 (Const16 [c]) (And16 (Const16 [d]) x)) // cond: // result: (And16 (Const16 [int64(int16(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c & d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd16_20(v *Value) bool { b := v.Block // match: (And16 (Const16 [c]) (And16 x (Const16 [d]))) // cond: // result: (And16 (Const16 [int64(int16(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c & d)) v.AddArg(v0) v.AddArg(x) return true } // match: (And16 (And16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (And16 (Const16 [int64(int16(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c & d)) v.AddArg(v0) v.AddArg(x) return true } // match: (And16 (And16 x (Const16 [d])) (Const16 [c])) // cond: // result: (And16 (Const16 [int64(int16(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c & d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd32_0(v *Value) bool { // match: (And32 (Const32 [c]) (Const32 [d])) // cond: // result: (Const32 [int64(int32(c&d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c & d)) return true } // match: (And32 (Const32 [d]) (Const32 [c])) // cond: // result: (Const32 [int64(int32(c&d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c & d)) return true } // match: (And32 (Const32 [m]) (Rsh32Ux64 _ (Const64 [c]))) // cond: c >= 64-ntz(m) // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpRsh32Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (And32 (Rsh32Ux64 _ (Const64 [c])) (Const32 [m])) // cond: c >= 64-ntz(m) // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } m := v_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (And32 (Const32 [m]) (Lsh32x64 _ (Const64 [c]))) // cond: c >= 64-nlz(m) // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpLsh32x64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (And32 (Lsh32x64 _ (Const64 [c])) (Const32 [m])) // cond: c >= 64-nlz(m) // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } m := v_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (And32 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And32 (Const32 [-1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And32 x (Const32 [-1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And32 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpAnd32_10(v *Value) bool { b := v.Block // match: (And32 _ (Const32 [0])) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (And32 x (And32 x y)) // cond: // result: (And32 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpAnd32) v.AddArg(x) v.AddArg(y) return true } // match: (And32 x (And32 y x)) // cond: // result: (And32 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpAnd32) v.AddArg(x) v.AddArg(y) return true } // match: (And32 (And32 x y) x) // cond: // result: (And32 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpAnd32) v.AddArg(x) v.AddArg(y) return true } // match: (And32 (And32 y x) x) // cond: // result: (And32 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpAnd32) v.AddArg(x) v.AddArg(y) return true } // match: (And32 (And32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (And32 i (And32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAnd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And32 (And32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (And32 i (And32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAnd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And32 x (And32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (And32 i (And32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAnd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And32 x (And32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (And32 i (And32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAnd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And32 (Const32 [c]) (And32 (Const32 [d]) x)) // cond: // result: (And32 (Const32 [int64(int32(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c & d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd32_20(v *Value) bool { b := v.Block // match: (And32 (Const32 [c]) (And32 x (Const32 [d]))) // cond: // result: (And32 (Const32 [int64(int32(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c & d)) v.AddArg(v0) v.AddArg(x) return true } // match: (And32 (And32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (And32 (Const32 [int64(int32(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c & d)) v.AddArg(v0) v.AddArg(x) return true } // match: (And32 (And32 x (Const32 [d])) (Const32 [c])) // cond: // result: (And32 (Const32 [int64(int32(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c & d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd64_0(v *Value) bool { // match: (And64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c&d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c & d return true } // match: (And64 (Const64 [d]) (Const64 [c])) // cond: // result: (Const64 [c&d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c & d return true } // match: (And64 (Const64 [m]) (Rsh64Ux64 _ (Const64 [c]))) // cond: c >= 64-ntz(m) // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpRsh64Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (And64 (Rsh64Ux64 _ (Const64 [c])) (Const64 [m])) // cond: c >= 64-ntz(m) // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } m := v_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (And64 (Const64 [m]) (Lsh64x64 _ (Const64 [c]))) // cond: c >= 64-nlz(m) // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpLsh64x64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (And64 (Lsh64x64 _ (Const64 [c])) (Const64 [m])) // cond: c >= 64-nlz(m) // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } m := v_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (And64 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And64 (Const64 [-1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And64 x (Const64 [-1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And64 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpAnd64_10(v *Value) bool { b := v.Block // match: (And64 _ (Const64 [0])) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (And64 x (And64 x y)) // cond: // result: (And64 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpAnd64) v.AddArg(x) v.AddArg(y) return true } // match: (And64 x (And64 y x)) // cond: // result: (And64 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpAnd64) v.AddArg(x) v.AddArg(y) return true } // match: (And64 (And64 x y) x) // cond: // result: (And64 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpAnd64) v.AddArg(x) v.AddArg(y) return true } // match: (And64 (And64 y x) x) // cond: // result: (And64 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpAnd64) v.AddArg(x) v.AddArg(y) return true } // match: (And64 (Const64 [y]) x) // cond: nlz(y) + nto(y) == 64 && nto(y) >= 32 // result: (Rsh64Ux64 (Lsh64x64 x (Const64 [nlz(y)])) (Const64 [nlz(y)])) for { t := v.Type x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } y := v_0.AuxInt if !(nlz(y)+nto(y) == 64 && nto(y) >= 32) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpLsh64x64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = nlz(y) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = nlz(y) v.AddArg(v2) return true } // match: (And64 x (Const64 [y])) // cond: nlz(y) + nto(y) == 64 && nto(y) >= 32 // result: (Rsh64Ux64 (Lsh64x64 x (Const64 [nlz(y)])) (Const64 [nlz(y)])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } y := v_1.AuxInt if !(nlz(y)+nto(y) == 64 && nto(y) >= 32) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpLsh64x64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = nlz(y) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = nlz(y) v.AddArg(v2) return true } // match: (And64 (Const64 [y]) x) // cond: nlo(y) + ntz(y) == 64 && ntz(y) >= 32 // result: (Lsh64x64 (Rsh64Ux64 x (Const64 [ntz(y)])) (Const64 [ntz(y)])) for { t := v.Type x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } y := v_0.AuxInt if !(nlo(y)+ntz(y) == 64 && ntz(y) >= 32) { break } v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = ntz(y) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = ntz(y) v.AddArg(v2) return true } // match: (And64 x (Const64 [y])) // cond: nlo(y) + ntz(y) == 64 && ntz(y) >= 32 // result: (Lsh64x64 (Rsh64Ux64 x (Const64 [ntz(y)])) (Const64 [ntz(y)])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } y := v_1.AuxInt if !(nlo(y)+ntz(y) == 64 && ntz(y) >= 32) { break } v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = ntz(y) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = ntz(y) v.AddArg(v2) return true } // match: (And64 (And64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (And64 i (And64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAnd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAnd64_20(v *Value) bool { b := v.Block // match: (And64 (And64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (And64 i (And64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAnd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And64 x (And64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (And64 i (And64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAnd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And64 x (And64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (And64 i (And64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAnd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And64 (Const64 [c]) (And64 (Const64 [d]) x)) // cond: // result: (And64 (Const64 [c&d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c & d v.AddArg(v0) v.AddArg(x) return true } // match: (And64 (Const64 [c]) (And64 x (Const64 [d]))) // cond: // result: (And64 (Const64 [c&d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c & d v.AddArg(v0) v.AddArg(x) return true } // match: (And64 (And64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (And64 (Const64 [c&d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c & d v.AddArg(v0) v.AddArg(x) return true } // match: (And64 (And64 x (Const64 [d])) (Const64 [c])) // cond: // result: (And64 (Const64 [c&d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c & d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd8_0(v *Value) bool { // match: (And8 (Const8 [c]) (Const8 [d])) // cond: // result: (Const8 [int64(int8(c&d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c & d)) return true } // match: (And8 (Const8 [d]) (Const8 [c])) // cond: // result: (Const8 [int64(int8(c&d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c & d)) return true } // match: (And8 (Const8 [m]) (Rsh8Ux64 _ (Const64 [c]))) // cond: c >= 64-ntz(m) // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpRsh8Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (And8 (Rsh8Ux64 _ (Const64 [c])) (Const8 [m])) // cond: c >= 64-ntz(m) // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } m := v_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (And8 (Const8 [m]) (Lsh8x64 _ (Const64 [c]))) // cond: c >= 64-nlz(m) // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpLsh8x64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (And8 (Lsh8x64 _ (Const64 [c])) (Const8 [m])) // cond: c >= 64-nlz(m) // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } m := v_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (And8 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And8 (Const8 [-1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And8 x (Const8 [-1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And8 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpAnd8_10(v *Value) bool { b := v.Block // match: (And8 _ (Const8 [0])) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (And8 x (And8 x y)) // cond: // result: (And8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpAnd8) v.AddArg(x) v.AddArg(y) return true } // match: (And8 x (And8 y x)) // cond: // result: (And8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpAnd8) v.AddArg(x) v.AddArg(y) return true } // match: (And8 (And8 x y) x) // cond: // result: (And8 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpAnd8) v.AddArg(x) v.AddArg(y) return true } // match: (And8 (And8 y x) x) // cond: // result: (And8 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpAnd8) v.AddArg(x) v.AddArg(y) return true } // match: (And8 (And8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (And8 i (And8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAnd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And8 (And8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (And8 i (And8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAnd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And8 x (And8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (And8 i (And8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAnd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And8 x (And8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (And8 i (And8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAnd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And8 (Const8 [c]) (And8 (Const8 [d]) x)) // cond: // result: (And8 (Const8 [int64(int8(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c & d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd8_20(v *Value) bool { b := v.Block // match: (And8 (Const8 [c]) (And8 x (Const8 [d]))) // cond: // result: (And8 (Const8 [int64(int8(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c & d)) v.AddArg(v0) v.AddArg(x) return true } // match: (And8 (And8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (And8 (Const8 [int64(int8(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c & d)) v.AddArg(v0) v.AddArg(x) return true } // match: (And8 (And8 x (Const8 [d])) (Const8 [c])) // cond: // result: (And8 (Const8 [int64(int8(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c & d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpArraySelect_0(v *Value) bool { // match: (ArraySelect (ArrayMake1 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpArrayMake1 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ArraySelect [0] x:(IData _)) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] if x.Op != OpIData { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpCom16_0(v *Value) bool { // match: (Com16 (Com16 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpCom16 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Com16 (Const16 [c])) // cond: // result: (Const16 [^c]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst16) v.AuxInt = ^c return true } return false } func rewriteValuegeneric_OpCom32_0(v *Value) bool { // match: (Com32 (Com32 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpCom32 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Com32 (Const32 [c])) // cond: // result: (Const32 [^c]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = ^c return true } return false } func rewriteValuegeneric_OpCom64_0(v *Value) bool { // match: (Com64 (Com64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpCom64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Com64 (Const64 [c])) // cond: // result: (Const64 [^c]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = ^c return true } return false } func rewriteValuegeneric_OpCom8_0(v *Value) bool { // match: (Com8 (Com8 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpCom8 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Com8 (Const8 [c])) // cond: // result: (Const8 [^c]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst8) v.AuxInt = ^c return true } return false } func rewriteValuegeneric_OpConstInterface_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ConstInterface) // cond: // result: (IMake (ConstNil ) (ConstNil )) for { v.reset(OpIMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.Uintptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v.AddArg(v1) return true } } func rewriteValuegeneric_OpConstSlice_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (ConstSlice) // cond: config.PtrSize == 4 // result: (SliceMake (ConstNil ) (Const32 [0]) (Const32 [0])) for { if !(config.PtrSize == 4) { break } v.reset(OpSliceMake) v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int) v2.AuxInt = 0 v.AddArg(v2) return true } // match: (ConstSlice) // cond: config.PtrSize == 8 // result: (SliceMake (ConstNil ) (Const64 [0]) (Const64 [0])) for { if !(config.PtrSize == 8) { break } v.reset(OpSliceMake) v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.Int) v2.AuxInt = 0 v.AddArg(v2) return true } return false } func rewriteValuegeneric_OpConstString_0(v *Value) bool { b := v.Block config := b.Func.Config fe := b.Func.fe typ := &b.Func.Config.Types // match: (ConstString {s}) // cond: config.PtrSize == 4 && s.(string) == "" // result: (StringMake (ConstNil) (Const32 [0])) for { s := v.Aux if !(config.PtrSize == 4 && s.(string) == "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = 0 v.AddArg(v1) return true } // match: (ConstString {s}) // cond: config.PtrSize == 8 && s.(string) == "" // result: (StringMake (ConstNil) (Const64 [0])) for { s := v.Aux if !(config.PtrSize == 8 && s.(string) == "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = 0 v.AddArg(v1) return true } // match: (ConstString {s}) // cond: config.PtrSize == 4 && s.(string) != "" // result: (StringMake (Addr {fe.StringData(s.(string))} (SB)) (Const32 [int64(len(s.(string)))])) for { s := v.Aux if !(config.PtrSize == 4 && s.(string) != "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) v0.Aux = fe.StringData(s.(string)) v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int) v2.AuxInt = int64(len(s.(string))) v.AddArg(v2) return true } // match: (ConstString {s}) // cond: config.PtrSize == 8 && s.(string) != "" // result: (StringMake (Addr {fe.StringData(s.(string))} (SB)) (Const64 [int64(len(s.(string)))])) for { s := v.Aux if !(config.PtrSize == 8 && s.(string) != "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) v0.Aux = fe.StringData(s.(string)) v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.Int) v2.AuxInt = int64(len(s.(string))) v.AddArg(v2) return true } return false } func rewriteValuegeneric_OpConvert_0(v *Value) bool { // match: (Convert (Add64 (Convert ptr mem) off) mem) // cond: // result: (Add64 ptr off) for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } off := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConvert { break } _ = v_0_0.Args[1] ptr := v_0_0.Args[0] if mem != v_0_0.Args[1] { break } v.reset(OpAdd64) v.AddArg(ptr) v.AddArg(off) return true } // match: (Convert (Add64 off (Convert ptr mem)) mem) // cond: // result: (Add64 ptr off) for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] off := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConvert { break } _ = v_0_1.Args[1] ptr := v_0_1.Args[0] if mem != v_0_1.Args[1] { break } v.reset(OpAdd64) v.AddArg(ptr) v.AddArg(off) return true } // match: (Convert (Add32 (Convert ptr mem) off) mem) // cond: // result: (Add32 ptr off) for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } off := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConvert { break } _ = v_0_0.Args[1] ptr := v_0_0.Args[0] if mem != v_0_0.Args[1] { break } v.reset(OpAdd32) v.AddArg(ptr) v.AddArg(off) return true } // match: (Convert (Add32 off (Convert ptr mem)) mem) // cond: // result: (Add32 ptr off) for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] off := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConvert { break } _ = v_0_1.Args[1] ptr := v_0_1.Args[0] if mem != v_0_1.Args[1] { break } v.reset(OpAdd32) v.AddArg(ptr) v.AddArg(off) return true } // match: (Convert (Convert ptr mem) mem) // cond: // result: ptr for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConvert { break } _ = v_0.Args[1] ptr := v_0.Args[0] if mem != v_0.Args[1] { break } v.reset(OpCopy) v.Type = ptr.Type v.AddArg(ptr) return true } return false } func rewriteValuegeneric_OpCvt32Fto32_0(v *Value) bool { // match: (Cvt32Fto32 (Const32F [c])) // cond: // result: (Const32 [int64(int32(auxTo32F(c)))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(auxTo32F(c))) return true } return false } func rewriteValuegeneric_OpCvt32Fto64_0(v *Value) bool { // match: (Cvt32Fto64 (Const32F [c])) // cond: // result: (Const64 [int64(auxTo32F(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(auxTo32F(c)) return true } return false } func rewriteValuegeneric_OpCvt32Fto64F_0(v *Value) bool { // match: (Cvt32Fto64F (Const32F [c])) // cond: // result: (Const64F [c]) for { v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v.reset(OpConst64F) v.AuxInt = c return true } return false } func rewriteValuegeneric_OpCvt32to32F_0(v *Value) bool { // match: (Cvt32to32F (Const32 [c])) // cond: // result: (Const32F [auxFrom32F(float32(int32(c)))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(float32(int32(c))) return true } return false } func rewriteValuegeneric_OpCvt32to64F_0(v *Value) bool { // match: (Cvt32to64F (Const32 [c])) // cond: // result: (Const64F [auxFrom64F(float64(int32(c)))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(float64(int32(c))) return true } return false } func rewriteValuegeneric_OpCvt64Fto32_0(v *Value) bool { // match: (Cvt64Fto32 (Const64F [c])) // cond: // result: (Const32 [int64(int32(auxTo64F(c)))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(auxTo64F(c))) return true } return false } func rewriteValuegeneric_OpCvt64Fto32F_0(v *Value) bool { // match: (Cvt64Fto32F (Const64F [c])) // cond: // result: (Const32F [auxFrom32F(float32(auxTo64F(c)))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(float32(auxTo64F(c))) return true } return false } func rewriteValuegeneric_OpCvt64Fto64_0(v *Value) bool { // match: (Cvt64Fto64 (Const64F [c])) // cond: // result: (Const64 [int64(auxTo64F(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(auxTo64F(c)) return true } return false } func rewriteValuegeneric_OpCvt64to32F_0(v *Value) bool { // match: (Cvt64to32F (Const64 [c])) // cond: // result: (Const32F [auxFrom32F(float32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(float32(c)) return true } return false } func rewriteValuegeneric_OpCvt64to64F_0(v *Value) bool { // match: (Cvt64to64F (Const64 [c])) // cond: // result: (Const64F [auxFrom64F(float64(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(float64(c)) return true } return false } func rewriteValuegeneric_OpDiv16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16 (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int64(int16(c)/int16(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int64(int16(c) / int16(d)) return true } // match: (Div16 n (Const16 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c&0xffff) // result: (Rsh16Ux64 n (Const64 [log2(c&0xffff)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c&0xffff)) { break } v.reset(OpRsh16Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c & 0xffff) v.AddArg(v0) return true } // match: (Div16 n (Const16 [c])) // cond: c < 0 && c != -1<<15 // result: (Neg16 (Div16 n (Const16 [-c]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<15) { break } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpDiv16, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = -c v0.AddArg(v1) v.AddArg(v0) return true } // match: (Div16 x (Const16 [-1<<15])) // cond: // result: (Rsh16Ux64 (And16 x (Neg16 x)) (Const64 [15])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != -1<<15 { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpNeg16, t) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = 15 v.AddArg(v2) return true } // match: (Div16 n (Const16 [c])) // cond: isPowerOfTwo(c) // result: (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [16-log2(c)]))) (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpRsh16Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh16x64, t) v2.AddArg(n) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = 15 v2.AddArg(v3) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 16 - log2(c) v1.AddArg(v4) v0.AddArg(v1) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = log2(c) v.AddArg(v5) return true } // match: (Div16 x (Const16 [c])) // cond: smagicOK(16,c) // result: (Sub16 (Rsh32x64 (Mul32 (Const32 [int64(smagic(16,c).m)]) (SignExt16to32 x)) (Const64 [16+smagic(16,c).s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(smagicOK(16, c)) { break } v.reset(OpSub16) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(smagic(16, c).m) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 16 + smagic(16, c).s v0.AddArg(v4) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v6.AddArg(x) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = 31 v5.AddArg(v7) v.AddArg(v5) return true } return false } func rewriteValuegeneric_OpDiv16u_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div16u (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int64(int16(uint16(c)/uint16(d)))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int64(int16(uint16(c) / uint16(d))) return true } // match: (Div16u n (Const16 [c])) // cond: isPowerOfTwo(c&0xffff) // result: (Rsh16Ux64 n (Const64 [log2(c&0xffff)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(isPowerOfTwo(c & 0xffff)) { break } v.reset(OpRsh16Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c & 0xffff) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK(16, c) && config.RegSize == 8 // result: (Trunc64to16 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<16+umagic(16,c).m)]) (ZeroExt16to64 x)) (Const64 [16+umagic(16,c).s]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(umagicOK(16, c) && config.RegSize == 8) { break } v.reset(OpTrunc64to16) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(1<<16 + umagic(16, c).m) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 16 + umagic(16, c).s v0.AddArg(v4) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK(16, c) && config.RegSize == 4 && umagic(16,c).m&1 == 0 // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int64(1<<15+umagic(16,c).m/2)]) (ZeroExt16to32 x)) (Const64 [16+umagic(16,c).s-1]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(umagicOK(16, c) && config.RegSize == 4 && umagic(16, c).m&1 == 0) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(1<<15 + umagic(16, c).m/2) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 16 + umagic(16, c).s - 1 v0.AddArg(v4) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK(16, c) && config.RegSize == 4 && c&1 == 0 // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int64(1<<15+(umagic(16,c).m+1)/2)]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [16+umagic(16,c).s-2]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(umagicOK(16, c) && config.RegSize == 4 && c&1 == 0) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(1<<15 + (umagic(16, c).m+1)/2) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v4.AddArg(x) v3.AddArg(v4) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = 1 v3.AddArg(v5) v1.AddArg(v3) v0.AddArg(v1) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = 16 + umagic(16, c).s - 2 v0.AddArg(v6) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK(16, c) && config.RegSize == 4 && config.useAvg // result: (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) (Mul32 (Const32 [int64(umagic(16,c).m)]) (ZeroExt16to32 x))) (Const64 [16+umagic(16,c).s-1]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(umagicOK(16, c) && config.RegSize == 4 && config.useAvg) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) v2 := b.NewValue0(v.Pos, OpLsh32x64, typ.UInt32) v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v3.AddArg(x) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 16 v2.AddArg(v4) v1.AddArg(v2) v5 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(umagic(16, c).m) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v7.AddArg(x) v5.AddArg(v7) v1.AddArg(v5) v0.AddArg(v1) v8 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v8.AuxInt = 16 + umagic(16, c).s - 1 v0.AddArg(v8) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv32_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32 (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int64(int32(c)/int32(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int64(int32(c) / int32(d)) return true } // match: (Div32 n (Const32 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c&0xffffffff) // result: (Rsh32Ux64 n (Const64 [log2(c&0xffffffff)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c&0xffffffff)) { break } v.reset(OpRsh32Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c & 0xffffffff) v.AddArg(v0) return true } // match: (Div32 n (Const32 [c])) // cond: c < 0 && c != -1<<31 // result: (Neg32 (Div32 n (Const32 [-c]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<31) { break } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpDiv32, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = -c v0.AddArg(v1) v.AddArg(v0) return true } // match: (Div32 x (Const32 [-1<<31])) // cond: // result: (Rsh32Ux64 (And32 x (Neg32 x)) (Const64 [31])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != -1<<31 { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpNeg32, t) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = 31 v.AddArg(v2) return true } // match: (Div32 n (Const32 [c])) // cond: isPowerOfTwo(c) // result: (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [32-log2(c)]))) (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpRsh32Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh32x64, t) v2.AddArg(n) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = 31 v2.AddArg(v3) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 32 - log2(c) v1.AddArg(v4) v0.AddArg(v1) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = log2(c) v.AddArg(v5) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK(32,c) && config.RegSize == 8 // result: (Sub32 (Rsh64x64 (Mul64 (Const64 [int64(smagic(32,c).m)]) (SignExt32to64 x)) (Const64 [32+smagic(32,c).s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(smagicOK(32, c) && config.RegSize == 8) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(smagic(32, c).m) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 32 + smagic(32, c).s v0.AddArg(v4) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpRsh64x64, t) v6 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v6.AddArg(x) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = 63 v5.AddArg(v7) v.AddArg(v5) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK(32,c) && config.RegSize == 4 && smagic(32,c).m&1 == 0 && config.useHmul // result: (Sub32 (Rsh32x64 (Hmul32 (Const32 [int64(int32(smagic(32,c).m/2))]) x) (Const64 [smagic(32,c).s-1])) (Rsh32x64 x (Const64 [31]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(smagicOK(32, c) && config.RegSize == 4 && smagic(32, c).m&1 == 0 && config.useHmul) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpHmul32, t) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(smagic(32, c).m / 2)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = smagic(32, c).s - 1 v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpRsh32x64, t) v4.AddArg(x) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = 31 v4.AddArg(v5) v.AddArg(v4) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK(32,c) && config.RegSize == 4 && smagic(32,c).m&1 != 0 && config.useHmul // result: (Sub32 (Rsh32x64 (Add32 (Hmul32 (Const32 [int64(int32(smagic(32,c).m))]) x) x) (Const64 [smagic(32,c).s])) (Rsh32x64 x (Const64 [31]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(smagicOK(32, c) && config.RegSize == 4 && smagic(32, c).m&1 != 0 && config.useHmul) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpAdd32, t) v2 := b.NewValue0(v.Pos, OpHmul32, t) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(smagic(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = smagic(32, c).s v0.AddArg(v4) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v5.AddArg(x) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = 31 v5.AddArg(v6) v.AddArg(v5) return true } return false } func rewriteValuegeneric_OpDiv32F_0(v *Value) bool { b := v.Block // match: (Div32F (Const32F [c]) (Const32F [d])) // cond: // result: (Const32F [auxFrom32F(auxTo32F(c) / auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(auxTo32F(c) / auxTo32F(d)) return true } // match: (Div32F x (Const32F [c])) // cond: reciprocalExact32(auxTo32F(c)) // result: (Mul32F x (Const32F [auxFrom32F(1/auxTo32F(c))])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32F { break } t := v_1.Type c := v_1.AuxInt if !(reciprocalExact32(auxTo32F(c))) { break } v.reset(OpMul32F) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst32F, t) v0.AuxInt = auxFrom32F(1 / auxTo32F(c)) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv32u_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32u (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int64(int32(uint32(c)/uint32(d)))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int64(int32(uint32(c) / uint32(d))) return true } // match: (Div32u n (Const32 [c])) // cond: isPowerOfTwo(c&0xffffffff) // result: (Rsh32Ux64 n (Const64 [log2(c&0xffffffff)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(isPowerOfTwo(c & 0xffffffff)) { break } v.reset(OpRsh32Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c & 0xffffffff) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK(32, c) && config.RegSize == 4 && umagic(32,c).m&1 == 0 && config.useHmul // result: (Rsh32Ux64 (Hmul32u (Const32 [int64(int32(1<<31+umagic(32,c).m/2))]) x) (Const64 [umagic(32,c).s-1])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(umagicOK(32, c) && config.RegSize == 4 && umagic(32, c).m&1 == 0 && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v1.AuxInt = int64(int32(1<<31 + umagic(32, c).m/2)) v0.AddArg(v1) v0.AddArg(x) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = umagic(32, c).s - 1 v.AddArg(v2) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK(32, c) && config.RegSize == 4 && c&1 == 0 && config.useHmul // result: (Rsh32Ux64 (Hmul32u (Const32 [int64(int32(1<<31+(umagic(32,c).m+1)/2))]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [umagic(32,c).s-2])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(umagicOK(32, c) && config.RegSize == 4 && c&1 == 0 && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v1.AuxInt = int64(int32(1<<31 + (umagic(32, c).m+1)/2)) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v2.AddArg(x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = 1 v2.AddArg(v3) v0.AddArg(v2) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = umagic(32, c).s - 2 v.AddArg(v4) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK(32, c) && config.RegSize == 4 && config.useAvg && config.useHmul // result: (Rsh32Ux64 (Avg32u x (Hmul32u (Const32 [int64(int32(umagic(32,c).m))]) x)) (Const64 [umagic(32,c).s-1])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(umagicOK(32, c) && config.RegSize == 4 && config.useAvg && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(umagic(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = umagic(32, c).s - 1 v.AddArg(v3) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK(32, c) && config.RegSize == 8 && umagic(32,c).m&1 == 0 // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+umagic(32,c).m/2)]) (ZeroExt32to64 x)) (Const64 [32+umagic(32,c).s-1]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(umagicOK(32, c) && config.RegSize == 8 && umagic(32, c).m&1 == 0) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(1<<31 + umagic(32, c).m/2) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 32 + umagic(32, c).s - 1 v0.AddArg(v4) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK(32, c) && config.RegSize == 8 && c&1 == 0 // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+(umagic(32,c).m+1)/2)]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [32+umagic(32,c).s-2]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(umagicOK(32, c) && config.RegSize == 8 && c&1 == 0) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(1<<31 + (umagic(32, c).m+1)/2) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(x) v3.AddArg(v4) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = 1 v3.AddArg(v5) v1.AddArg(v3) v0.AddArg(v1) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = 32 + umagic(32, c).s - 2 v0.AddArg(v6) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK(32, c) && config.RegSize == 8 && config.useAvg // result: (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) (Mul64 (Const64 [int64(umagic(32,c).m)]) (ZeroExt32to64 x))) (Const64 [32+umagic(32,c).s-1]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(umagicOK(32, c) && config.RegSize == 8 && config.useAvg) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 32 v2.AddArg(v4) v1.AddArg(v2) v5 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt32) v6.AuxInt = int64(umagic(32, c).m) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v7.AddArg(x) v5.AddArg(v7) v1.AddArg(v5) v0.AddArg(v1) v8 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v8.AuxInt = 32 + umagic(32, c).s - 1 v0.AddArg(v8) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv64_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64 (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [c/d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = c / d return true } // match: (Div64 n (Const64 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c) // result: (Rsh64Ux64 n (Const64 [log2(c)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c)) { break } v.reset(OpRsh64Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Div64 n (Const64 [-1<<63])) // cond: isNonNegative(n) // result: (Const64 [0]) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1<<63 { break } if !(isNonNegative(n)) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Div64 n (Const64 [c])) // cond: c < 0 && c != -1<<63 // result: (Neg64 (Div64 n (Const64 [-c]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<63) { break } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpDiv64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = -c v0.AddArg(v1) v.AddArg(v0) return true } // match: (Div64 x (Const64 [-1<<63])) // cond: // result: (Rsh64Ux64 (And64 x (Neg64 x)) (Const64 [63])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1<<63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpNeg64, t) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = 63 v.AddArg(v2) return true } // match: (Div64 n (Const64 [c])) // cond: isPowerOfTwo(c) // result: (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [64-log2(c)]))) (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpRsh64Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh64x64, t) v2.AddArg(n) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = 63 v2.AddArg(v3) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 64 - log2(c) v1.AddArg(v4) v0.AddArg(v1) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = log2(c) v.AddArg(v5) return true } // match: (Div64 x (Const64 [c])) // cond: smagicOK(64,c) && smagic(64,c).m&1 == 0 && config.useHmul // result: (Sub64 (Rsh64x64 (Hmul64 (Const64 [int64(smagic(64,c).m/2)]) x) (Const64 [smagic(64,c).s-1])) (Rsh64x64 x (Const64 [63]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(smagicOK(64, c) && smagic(64, c).m&1 == 0 && config.useHmul) { break } v.reset(OpSub64) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpHmul64, t) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(smagic(64, c).m / 2) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = smagic(64, c).s - 1 v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpRsh64x64, t) v4.AddArg(x) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = 63 v4.AddArg(v5) v.AddArg(v4) return true } // match: (Div64 x (Const64 [c])) // cond: smagicOK(64,c) && smagic(64,c).m&1 != 0 && config.useHmul // result: (Sub64 (Rsh64x64 (Add64 (Hmul64 (Const64 [int64(smagic(64,c).m)]) x) x) (Const64 [smagic(64,c).s])) (Rsh64x64 x (Const64 [63]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(smagicOK(64, c) && smagic(64, c).m&1 != 0 && config.useHmul) { break } v.reset(OpSub64) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpAdd64, t) v2 := b.NewValue0(v.Pos, OpHmul64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(smagic(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = smagic(64, c).s v0.AddArg(v4) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpRsh64x64, t) v5.AddArg(x) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = 63 v5.AddArg(v6) v.AddArg(v5) return true } return false } func rewriteValuegeneric_OpDiv64F_0(v *Value) bool { b := v.Block // match: (Div64F (Const64F [c]) (Const64F [d])) // cond: // result: (Const64F [auxFrom64F(auxTo64F(c) / auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(auxTo64F(c) / auxTo64F(d)) return true } // match: (Div64F x (Const64F [c])) // cond: reciprocalExact64(auxTo64F(c)) // result: (Mul64F x (Const64F [auxFrom64F(1/auxTo64F(c))])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64F { break } t := v_1.Type c := v_1.AuxInt if !(reciprocalExact64(auxTo64F(c))) { break } v.reset(OpMul64F) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64F, t) v0.AuxInt = auxFrom64F(1 / auxTo64F(c)) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv64u_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64u (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [int64(uint64(c)/uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64(uint64(c) / uint64(d)) return true } // match: (Div64u n (Const64 [c])) // cond: isPowerOfTwo(c) // result: (Rsh64Ux64 n (Const64 [log2(c)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpRsh64Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Div64u n (Const64 [-1<<63])) // cond: // result: (Rsh64Ux64 n (Const64 [63])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1<<63 { break } v.reset(OpRsh64Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = 63 v.AddArg(v0) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK(64, c) && config.RegSize == 8 && umagic(64,c).m&1 == 0 && config.useHmul // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+umagic(64,c).m/2)]) x) (Const64 [umagic(64,c).s-1])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(umagicOK(64, c) && config.RegSize == 8 && umagic(64, c).m&1 == 0 && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64(1<<63 + umagic(64, c).m/2) v0.AddArg(v1) v0.AddArg(x) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = umagic(64, c).s - 1 v.AddArg(v2) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK(64, c) && config.RegSize == 8 && c&1 == 0 && config.useHmul // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+(umagic(64,c).m+1)/2)]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [umagic(64,c).s-2])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(umagicOK(64, c) && config.RegSize == 8 && c&1 == 0 && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64(1<<63 + (umagic(64, c).m+1)/2) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v2.AddArg(x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = 1 v2.AddArg(v3) v0.AddArg(v2) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = umagic(64, c).s - 2 v.AddArg(v4) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK(64, c) && config.RegSize == 8 && config.useAvg && config.useHmul // result: (Rsh64Ux64 (Avg64u x (Hmul64u (Const64 [int64(umagic(64,c).m)]) x)) (Const64 [umagic(64,c).s-1])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(umagicOK(64, c) && config.RegSize == 8 && config.useAvg && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(umagic(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = umagic(64, c).s - 1 v.AddArg(v3) return true } return false } func rewriteValuegeneric_OpDiv8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8 (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int64(int8(c)/int8(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int64(int8(c) / int8(d)) return true } // match: (Div8 n (Const8 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c&0xff) // result: (Rsh8Ux64 n (Const64 [log2(c&0xff)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c&0xff)) { break } v.reset(OpRsh8Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c & 0xff) v.AddArg(v0) return true } // match: (Div8 n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Neg8 (Div8 n (Const8 [-c]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<7) { break } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpDiv8, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = -c v0.AddArg(v1) v.AddArg(v0) return true } // match: (Div8 x (Const8 [-1<<7 ])) // cond: // result: (Rsh8Ux64 (And8 x (Neg8 x)) (Const64 [7 ])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != -1<<7 { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpNeg8, t) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = 7 v.AddArg(v2) return true } // match: (Div8 n (Const8 [c])) // cond: isPowerOfTwo(c) // result: (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [ 8-log2(c)]))) (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpRsh8Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh8x64, t) v2.AddArg(n) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = 7 v2.AddArg(v3) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 8 - log2(c) v1.AddArg(v4) v0.AddArg(v1) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = log2(c) v.AddArg(v5) return true } // match: (Div8 x (Const8 [c])) // cond: smagicOK(8,c) // result: (Sub8 (Rsh32x64 (Mul32 (Const32 [int64(smagic(8,c).m)]) (SignExt8to32 x)) (Const64 [8+smagic(8,c).s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(smagicOK(8, c)) { break } v.reset(OpSub8) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(smagic(8, c).m) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 8 + smagic(8, c).s v0.AddArg(v4) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v6.AddArg(x) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = 31 v5.AddArg(v7) v.AddArg(v5) return true } return false } func rewriteValuegeneric_OpDiv8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8u (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int64(int8(uint8(c)/uint8(d)))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int64(int8(uint8(c) / uint8(d))) return true } // match: (Div8u n (Const8 [c])) // cond: isPowerOfTwo(c&0xff) // result: (Rsh8Ux64 n (Const64 [log2(c&0xff)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(isPowerOfTwo(c & 0xff)) { break } v.reset(OpRsh8Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c & 0xff) v.AddArg(v0) return true } // match: (Div8u x (Const8 [c])) // cond: umagicOK(8, c) // result: (Trunc32to8 (Rsh32Ux64 (Mul32 (Const32 [int64(1<<8+umagic(8,c).m)]) (ZeroExt8to32 x)) (Const64 [8+umagic(8,c).s]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(umagicOK(8, c)) { break } v.reset(OpTrunc32to8) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(1<<8 + umagic(8, c).m) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 8 + umagic(8, c).s v0.AddArg(v4) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpEq16_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Eq16 x x) // cond: // result: (ConstBool [1]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (Eq16 (Const16 [c]) (Add16 (Const16 [d]) x)) // cond: // result: (Eq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq16 (Const16 [c]) (Add16 x (Const16 [d]))) // cond: // result: (Eq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq16 (Add16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Eq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq16 (Add16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Eq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq16 (Const16 [c]) (Const16 [d])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq16 (Const16 [d]) (Const16 [c])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq16 (Mod16u x (Const16 [c])) (Const16 [0])) // cond: x.Op != OpConst16 && udivisibleOK(16,c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt16to32 x) (Const32 [c&0xffff])) (Const32 [0])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMod16u { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } if !(x.Op != OpConst16 && udivisibleOK(16, c) && !hasSmallRotate(config)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = c & 0xffff v0.AddArg(v2) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = 0 v.AddArg(v3) return true } // match: (Eq16 (Const16 [0]) (Mod16u x (Const16 [c]))) // cond: x.Op != OpConst16 && udivisibleOK(16,c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt16to32 x) (Const32 [c&0xffff])) (Const32 [0])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v_1 := v.Args[1] if v_1.Op != OpMod16u { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(x.Op != OpConst16 && udivisibleOK(16, c) && !hasSmallRotate(config)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = c & 0xffff v0.AddArg(v2) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = 0 v.AddArg(v3) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to64 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq16_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (ZeroExt16to64 x) (Const64 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to64 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (ZeroExt16to64 x) (Const64 [m])) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to64 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (ZeroExt16to64 x) (Const64 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to64 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (ZeroExt16to64 x) (Const64 [m])) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x)) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (ZeroExt16to32 x) (Const32 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x)) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq16_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (ZeroExt16to32 x) (Const32 [m])) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x)) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (ZeroExt16to32 x) (Const32 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x)) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (ZeroExt16to32 x) (Const32 [m])) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt16to32 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) (Const32 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt16to32 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt16to32 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) (Const32 [m])) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt16to32 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt16to32 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq16_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) (Const32 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt16to32 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt16to32 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) (Const32 [m])) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt16to32 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x))) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg32u { break } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh32x64 { break } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_1_1_0_0_0_0.Args[0] { break } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 { break } if v_1_1_0_0_0_1.AuxInt != 16 { break } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (ZeroExt16to32 x) (Const32 [m]))) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg32u { break } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh32x64 { break } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_1_1_0_0_0_0.Args[0] { break } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 { break } if v_1_1_0_0_0_1.AuxInt != 16 { break } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x))) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAvg32u { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpLsh32x64 { break } _ = v_1_0_0_0_0.Args[1] v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_1_0_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.AuxInt != 16 { break } mul := v_1_0_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (ZeroExt16to32 x) (Const32 [m]))) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAvg32u { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpLsh32x64 { break } _ = v_1_0_0_0_0.Args[1] v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_1_0_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.AuxInt != 16 { break } mul := v_1_0_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAvg32u { break } _ = v_0_1_0_0.Args[1] v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpLsh32x64 { break } _ = v_0_1_0_0_0.Args[1] v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_0_1_0_0_0_0.Args[0] { break } v_0_1_0_0_0_1 := v_0_1_0_0_0.Args[1] if v_0_1_0_0_0_1.Op != OpConst64 { break } if v_0_1_0_0_0_1.AuxInt != 16 { break } mul := v_0_1_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (ZeroExt16to32 x) (Const32 [m]))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAvg32u { break } _ = v_0_1_0_0.Args[1] v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpLsh32x64 { break } _ = v_0_1_0_0_0.Args[1] v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_0_1_0_0_0_0.Args[0] { break } v_0_1_0_0_0_1 := v_0_1_0_0_0.Args[1] if v_0_1_0_0_0_1.Op != OpConst64 { break } if v_0_1_0_0_0_1.AuxInt != 16 { break } mul := v_0_1_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x))) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAvg32u { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpLsh32x64 { break } _ = v_0_0_0_0_0.Args[1] v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_0_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.AuxInt != 16 { break } mul := v_0_0_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq16_40(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (ZeroExt16to32 x) (Const32 [m]))) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAvg32u { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpLsh32x64 { break } _ = v_0_0_0_0_0.Args[1] v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_0_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.AuxInt != 16 { break } mul := v_0_0_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh16x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh16x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd16 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] if n != v_1_0_0.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpRsh16Ux64 { break } if v_1_0_0_1.Type != t { break } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh16x64 { break } if v_1_0_0_1_0.Type != t { break } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { break } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 { break } if v_1_0_0_1_0_1.Type != typ.UInt64 { break } if v_1_0_0_1_0_1.AuxInt != 15 { break } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 { break } if v_1_0_0_1_1.Type != typ.UInt64 { break } kbar := v_1_0_0_1_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 15 && kbar == 16-k) { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int64(1< (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh16x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh16x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd16 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpRsh16Ux64 { break } if v_1_0_0_0.Type != t { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpRsh16x64 { break } if v_1_0_0_0_0.Type != t { break } _ = v_1_0_0_0_0.Args[1] if n != v_1_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.Type != typ.UInt64 { break } if v_1_0_0_0_0_1.AuxInt != 15 { break } v_1_0_0_0_1 := v_1_0_0_0.Args[1] if v_1_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_1.Type != typ.UInt64 { break } kbar := v_1_0_0_0_1.AuxInt if n != v_1_0_0.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 15 && kbar == 16-k) { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int64(1< n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh16x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd16 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] if n != v_0_0_0.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpRsh16Ux64 { break } if v_0_0_0_1.Type != t { break } _ = v_0_0_0_1.Args[1] v_0_0_0_1_0 := v_0_0_0_1.Args[0] if v_0_0_0_1_0.Op != OpRsh16x64 { break } if v_0_0_0_1_0.Type != t { break } _ = v_0_0_0_1_0.Args[1] if n != v_0_0_0_1_0.Args[0] { break } v_0_0_0_1_0_1 := v_0_0_0_1_0.Args[1] if v_0_0_0_1_0_1.Op != OpConst64 { break } if v_0_0_0_1_0_1.Type != typ.UInt64 { break } if v_0_0_0_1_0_1.AuxInt != 15 { break } v_0_0_0_1_1 := v_0_0_0_1.Args[1] if v_0_0_0_1_1.Op != OpConst64 { break } if v_0_0_0_1_1.Type != typ.UInt64 { break } kbar := v_0_0_0_1_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 15 && kbar == 16-k) { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int64(1< (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh16x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd16 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpRsh16Ux64 { break } if v_0_0_0_0.Type != t { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpRsh16x64 { break } if v_0_0_0_0_0.Type != t { break } _ = v_0_0_0_0_0.Args[1] if n != v_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.Type != typ.UInt64 { break } if v_0_0_0_0_0_1.AuxInt != 15 { break } v_0_0_0_0_1 := v_0_0_0_0.Args[1] if v_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_1.Type != typ.UInt64 { break } kbar := v_0_0_0_0_1.AuxInt if n != v_0_0_0.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 15 && kbar == 16-k) { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int64(1< [c]) (Add32 (Const32 [d]) x)) // cond: // result: (Eq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq32 (Const32 [c]) (Add32 x (Const32 [d]))) // cond: // result: (Eq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq32 (Add32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Eq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq32 (Add32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Eq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq32 (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq32 (Const32 [d]) (Const32 [c])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) x) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh32Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u x (Const32 [m])) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh32Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) x) (Const64 [s])) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq32_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq32 x (Mul32 (Rsh32Ux64 mul:(Hmul32u x (Const32 [m])) (Const64 [s])) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) x) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh32Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u x (Const32 [m])) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh32Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) x) (Const64 [s])) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Rsh32Ux64 mul:(Hmul32u x (Const32 [m])) (Const64 [s])) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh32Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } if mul_0.Type != typ.UInt32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Rsh32Ux64 x (Const64 [1])) (Const32 [m])) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh32Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } if mul_1.Type != typ.UInt32 { break } m := mul_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [s])) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } if mul_0.Type != typ.UInt32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Rsh32Ux64 mul:(Hmul32u (Rsh32Ux64 x (Const64 [1])) (Const32 [m])) (Const64 [s])) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } if mul_1.Type != typ.UInt32 { break } m := mul_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh32Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } if mul_0.Type != typ.UInt32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq32_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq32 (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Rsh32Ux64 x (Const64 [1])) (Const32 [m])) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh32Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } if mul_1.Type != typ.UInt32 { break } m := mul_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [s])) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } if mul_0.Type != typ.UInt32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Rsh32Ux64 mul:(Hmul32u (Rsh32Ux64 x (Const64 [1])) (Const32 [m])) (Const64 [s])) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } if mul_1.Type != typ.UInt32 { break } m := mul_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 (Avg32u x mul:(Hmul32u (Const32 [m]) x)) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh32Ux64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg32u { break } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { break } mul := v_1_1_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 (Avg32u x mul:(Hmul32u x (Const32 [m]))) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh32Ux64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg32u { break } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { break } mul := v_1_1_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Rsh32Ux64 (Avg32u x mul:(Hmul32u (Const32 [m]) x)) (Const64 [s])) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32Ux64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAvg32u { break } _ = v_1_0_0.Args[1] if x != v_1_0_0.Args[0] { break } mul := v_1_0_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Rsh32Ux64 (Avg32u x mul:(Hmul32u x (Const32 [m]))) (Const64 [s])) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32Ux64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAvg32u { break } _ = v_1_0_0.Args[1] if x != v_1_0_0.Args[0] { break } mul := v_1_0_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Rsh32Ux64 (Avg32u x mul:(Hmul32u (Const32 [m]) x)) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh32Ux64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAvg32u { break } _ = v_0_1_0.Args[1] if x != v_0_1_0.Args[0] { break } mul := v_0_1_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Rsh32Ux64 (Avg32u x mul:(Hmul32u x (Const32 [m]))) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh32Ux64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAvg32u { break } _ = v_0_1_0.Args[1] if x != v_0_1_0.Args[0] { break } mul := v_0_1_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Rsh32Ux64 (Avg32u x mul:(Hmul32u (Const32 [m]) x)) (Const64 [s])) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAvg32u { break } _ = v_0_0_0.Args[1] if x != v_0_0_0.Args[0] { break } mul := v_0_0_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq32_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq32 (Mul32 (Rsh32Ux64 (Avg32u x mul:(Hmul32u x (Const32 [m]))) (Const64 [s])) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAvg32u { break } _ = v_0_0_0.Args[1] if x != v_0_0_0.Args[0] { break } mul := v_0_0_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x)) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to32 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (ZeroExt32to64 x) (Const64 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to32 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x)) (Const64 [s]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to32 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (ZeroExt32to64 x) (Const64 [m])) (Const64 [s]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to32 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x)) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to32 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (ZeroExt32to64 x) (Const64 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to32 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x)) (Const64 [s]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to32 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (ZeroExt32to64 x) (Const64 [m])) (Const64 [s]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to32 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to32 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt32to64 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq32_40(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1])) (Const64 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to32 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt32to64 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [s]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to32 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt32to64 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1])) (Const64 [m])) (Const64 [s]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to32 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt32to64 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to32 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt32to64 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1])) (Const64 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to32 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt32to64 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [s]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to32 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt32to64 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1])) (Const64 [m])) (Const64 [s]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to32 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt32to64 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x))) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to32 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg64u { break } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh64x64 { break } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_1_1_0_0_0_0.Args[0] { break } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 { break } if v_1_1_0_0_0_1.AuxInt != 32 { break } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (ZeroExt32to64 x) (Const64 [m]))) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to32 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg64u { break } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh64x64 { break } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_1_1_0_0_0_0.Args[0] { break } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 { break } if v_1_1_0_0_0_1.AuxInt != 32 { break } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x))) (Const64 [s]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to32 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAvg64u { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpLsh64x64 { break } _ = v_1_0_0_0_0.Args[1] v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_1_0_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.AuxInt != 32 { break } mul := v_1_0_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq32_50(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq32 x (Mul32 (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (ZeroExt32to64 x) (Const64 [m]))) (Const64 [s]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to32 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAvg64u { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpLsh64x64 { break } _ = v_1_0_0_0_0.Args[1] v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_1_0_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.AuxInt != 32 { break } mul := v_1_0_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to32 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAvg64u { break } _ = v_0_1_0_0.Args[1] v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpLsh64x64 { break } _ = v_0_1_0_0_0.Args[1] v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_0_1_0_0_0_0.Args[0] { break } v_0_1_0_0_0_1 := v_0_1_0_0_0.Args[1] if v_0_1_0_0_0_1.Op != OpConst64 { break } if v_0_1_0_0_0_1.AuxInt != 32 { break } mul := v_0_1_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (ZeroExt32to64 x) (Const64 [m]))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to32 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAvg64u { break } _ = v_0_1_0_0.Args[1] v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpLsh64x64 { break } _ = v_0_1_0_0_0.Args[1] v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_0_1_0_0_0_0.Args[0] { break } v_0_1_0_0_0_1 := v_0_1_0_0_0.Args[1] if v_0_1_0_0_0_1.Op != OpConst64 { break } if v_0_1_0_0_0_1.AuxInt != 32 { break } mul := v_0_1_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x))) (Const64 [s]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to32 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAvg64u { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpLsh64x64 { break } _ = v_0_0_0_0_0.Args[1] v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_0_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.AuxInt != 32 { break } mul := v_0_0_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (ZeroExt32to64 x) (Const64 [m]))) (Const64 [s]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to32 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAvg64u { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpLsh64x64 { break } _ = v_0_0_0_0_0.Args[1] v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_0_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.AuxInt != 32 { break } mul := v_0_0_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh32x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd32 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] if n != v_1_0_0.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpRsh32Ux64 { break } if v_1_0_0_1.Type != t { break } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh32x64 { break } if v_1_0_0_1_0.Type != t { break } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { break } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 { break } if v_1_0_0_1_0_1.Type != typ.UInt64 { break } if v_1_0_0_1_0_1.AuxInt != 31 { break } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 { break } if v_1_0_0_1_1.Type != typ.UInt64 { break } kbar := v_1_0_0_1_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 31 && kbar == 32-k) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int64(1< (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh32x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd32 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpRsh32Ux64 { break } if v_1_0_0_0.Type != t { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpRsh32x64 { break } if v_1_0_0_0_0.Type != t { break } _ = v_1_0_0_0_0.Args[1] if n != v_1_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.Type != typ.UInt64 { break } if v_1_0_0_0_0_1.AuxInt != 31 { break } v_1_0_0_0_1 := v_1_0_0_0.Args[1] if v_1_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_1.Type != typ.UInt64 { break } kbar := v_1_0_0_0_1.AuxInt if n != v_1_0_0.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 31 && kbar == 32-k) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int64(1< n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd32 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] if n != v_0_0_0.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpRsh32Ux64 { break } if v_0_0_0_1.Type != t { break } _ = v_0_0_0_1.Args[1] v_0_0_0_1_0 := v_0_0_0_1.Args[0] if v_0_0_0_1_0.Op != OpRsh32x64 { break } if v_0_0_0_1_0.Type != t { break } _ = v_0_0_0_1_0.Args[1] if n != v_0_0_0_1_0.Args[0] { break } v_0_0_0_1_0_1 := v_0_0_0_1_0.Args[1] if v_0_0_0_1_0_1.Op != OpConst64 { break } if v_0_0_0_1_0_1.Type != typ.UInt64 { break } if v_0_0_0_1_0_1.AuxInt != 31 { break } v_0_0_0_1_1 := v_0_0_0_1.Args[1] if v_0_0_0_1_1.Op != OpConst64 { break } if v_0_0_0_1_1.Type != typ.UInt64 { break } kbar := v_0_0_0_1_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 31 && kbar == 32-k) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int64(1< (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd32 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpRsh32Ux64 { break } if v_0_0_0_0.Type != t { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpRsh32x64 { break } if v_0_0_0_0_0.Type != t { break } _ = v_0_0_0_0_0.Args[1] if n != v_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.Type != typ.UInt64 { break } if v_0_0_0_0_0_1.AuxInt != 31 { break } v_0_0_0_0_1 := v_0_0_0_0.Args[1] if v_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_1.Type != typ.UInt64 { break } kbar := v_0_0_0_0_1.AuxInt if n != v_0_0_0.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 31 && kbar == 32-k) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int64(1< [c]) (Add64 (Const64 [d]) x)) // cond: // result: (Eq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Eq64 (Const64 [c]) (Add64 x (Const64 [d]))) // cond: // result: (Eq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Eq64 (Add64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Eq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Eq64 (Add64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Eq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Eq64 (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq64 (Const64 [d]) (Const64 [c])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) x) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh64Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u x (Const64 [m])) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh64Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) x) (Const64 [s])) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq64_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq64 x (Mul64 (Rsh64Ux64 mul:(Hmul64u x (Const64 [m])) (Const64 [s])) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) x) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh64Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u x (Const64 [m])) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh64Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) x) (Const64 [s])) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Rsh64Ux64 mul:(Hmul64u x (Const64 [m])) (Const64 [s])) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh64Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Rsh64Ux64 x (Const64 [1])) (Const64 [m])) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh64Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [s])) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Rsh64Ux64 mul:(Hmul64u (Rsh64Ux64 x (Const64 [1])) (Const64 [m])) (Const64 [s])) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh64Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq64_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq64 (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Rsh64Ux64 x (Const64 [1])) (Const64 [m])) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh64Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [s])) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Rsh64Ux64 mul:(Hmul64u (Rsh64Ux64 x (Const64 [1])) (Const64 [m])) (Const64 [s])) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 (Avg64u x mul:(Hmul64u (Const64 [m]) x)) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh64Ux64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg64u { break } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { break } mul := v_1_1_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 (Avg64u x mul:(Hmul64u x (Const64 [m]))) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh64Ux64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg64u { break } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { break } mul := v_1_1_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Rsh64Ux64 (Avg64u x mul:(Hmul64u (Const64 [m]) x)) (Const64 [s])) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64Ux64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAvg64u { break } _ = v_1_0_0.Args[1] if x != v_1_0_0.Args[0] { break } mul := v_1_0_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Rsh64Ux64 (Avg64u x mul:(Hmul64u x (Const64 [m]))) (Const64 [s])) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64Ux64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAvg64u { break } _ = v_1_0_0.Args[1] if x != v_1_0_0.Args[0] { break } mul := v_1_0_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Rsh64Ux64 (Avg64u x mul:(Hmul64u (Const64 [m]) x)) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh64Ux64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAvg64u { break } _ = v_0_1_0.Args[1] if x != v_0_1_0.Args[0] { break } mul := v_0_1_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Rsh64Ux64 (Avg64u x mul:(Hmul64u x (Const64 [m]))) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh64Ux64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAvg64u { break } _ = v_0_1_0.Args[1] if x != v_0_1_0.Args[0] { break } mul := v_0_1_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Rsh64Ux64 (Avg64u x mul:(Hmul64u (Const64 [m]) x)) (Const64 [s])) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAvg64u { break } _ = v_0_0_0.Args[1] if x != v_0_0_0.Args[0] { break } mul := v_0_0_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq64_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq64 (Mul64 (Rsh64Ux64 (Avg64u x mul:(Hmul64u x (Const64 [m]))) (Const64 [s])) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAvg64u { break } _ = v_0_0_0.Args[1] if x != v_0_0_0.Args[0] { break } mul := v_0_0_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh64x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd64 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] if n != v_1_0_0.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpRsh64Ux64 { break } if v_1_0_0_1.Type != t { break } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh64x64 { break } if v_1_0_0_1_0.Type != t { break } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { break } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 { break } if v_1_0_0_1_0_1.Type != typ.UInt64 { break } if v_1_0_0_1_0_1.AuxInt != 63 { break } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 { break } if v_1_0_0_1_1.Type != typ.UInt64 { break } kbar := v_1_0_0_1_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 63 && kbar == 64-k) { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64(1< (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh64x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd64 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpRsh64Ux64 { break } if v_1_0_0_0.Type != t { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpRsh64x64 { break } if v_1_0_0_0_0.Type != t { break } _ = v_1_0_0_0_0.Args[1] if n != v_1_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.Type != typ.UInt64 { break } if v_1_0_0_0_0_1.AuxInt != 63 { break } v_1_0_0_0_1 := v_1_0_0_0.Args[1] if v_1_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_1.Type != typ.UInt64 { break } kbar := v_1_0_0_0_1.AuxInt if n != v_1_0_0.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 63 && kbar == 64-k) { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64(1< n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd64 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] if n != v_0_0_0.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpRsh64Ux64 { break } if v_0_0_0_1.Type != t { break } _ = v_0_0_0_1.Args[1] v_0_0_0_1_0 := v_0_0_0_1.Args[0] if v_0_0_0_1_0.Op != OpRsh64x64 { break } if v_0_0_0_1_0.Type != t { break } _ = v_0_0_0_1_0.Args[1] if n != v_0_0_0_1_0.Args[0] { break } v_0_0_0_1_0_1 := v_0_0_0_1_0.Args[1] if v_0_0_0_1_0_1.Op != OpConst64 { break } if v_0_0_0_1_0_1.Type != typ.UInt64 { break } if v_0_0_0_1_0_1.AuxInt != 63 { break } v_0_0_0_1_1 := v_0_0_0_1.Args[1] if v_0_0_0_1_1.Op != OpConst64 { break } if v_0_0_0_1_1.Type != typ.UInt64 { break } kbar := v_0_0_0_1_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 63 && kbar == 64-k) { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64(1< (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd64 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpRsh64Ux64 { break } if v_0_0_0_0.Type != t { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpRsh64x64 { break } if v_0_0_0_0_0.Type != t { break } _ = v_0_0_0_0_0.Args[1] if n != v_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.Type != typ.UInt64 { break } if v_0_0_0_0_0_1.AuxInt != 63 { break } v_0_0_0_0_1 := v_0_0_0_0.Args[1] if v_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_1.Type != typ.UInt64 { break } kbar := v_0_0_0_0_1.AuxInt if n != v_0_0_0.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 63 && kbar == 64-k) { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64(1< [c]) (Add8 (Const8 [d]) x)) // cond: // result: (Eq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq8 (Const8 [c]) (Add8 x (Const8 [d]))) // cond: // result: (Eq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq8 (Add8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Eq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq8 (Add8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Eq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq8 (Const8 [c]) (Const8 [d])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq8 (Const8 [d]) (Const8 [c])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq8 (Mod8u x (Const8 [c])) (Const8 [0])) // cond: x.Op != OpConst8 && udivisibleOK(8,c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt8to32 x) (Const32 [c&0xff])) (Const32 [0])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMod8u { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } if !(x.Op != OpConst8 && udivisibleOK(8, c) && !hasSmallRotate(config)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = c & 0xff v0.AddArg(v2) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = 0 v.AddArg(v3) return true } // match: (Eq8 (Const8 [0]) (Mod8u x (Const8 [c]))) // cond: x.Op != OpConst8 && udivisibleOK(8,c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt8to32 x) (Const32 [c&0xff])) (Const32 [0])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v_1 := v.Args[1] if v_1.Op != OpMod8u { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } c := v_1_1.AuxInt if !(x.Op != OpConst8 && udivisibleOK(8, c) && !hasSmallRotate(config)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = c & 0xff v0.AddArg(v2) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = 0 v.AddArg(v3) return true } // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to8 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt8to32 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq8_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (ZeroExt8to32 x) (Const32 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to8 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt8to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 x (Mul8 (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))) (Const8 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to8 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt8to32 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 x (Mul8 (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (ZeroExt8to32 x) (Const32 [m])) (Const64 [s]))) (Const8 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to8 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt8to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to8 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt8to32 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (ZeroExt8to32 x) (Const32 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to8 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt8to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 (Mul8 (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))) (Const8 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to8 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt8to32 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 (Mul8 (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (ZeroExt8to32 x) (Const32 [m])) (Const64 [s]))) (Const8 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to8 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt8to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh8x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh8x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd8 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] if n != v_1_0_0.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpRsh8Ux64 { break } if v_1_0_0_1.Type != t { break } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh8x64 { break } if v_1_0_0_1_0.Type != t { break } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { break } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 { break } if v_1_0_0_1_0_1.Type != typ.UInt64 { break } if v_1_0_0_1_0_1.AuxInt != 7 { break } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 { break } if v_1_0_0_1_1.Type != typ.UInt64 { break } kbar := v_1_0_0_1_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 7 && kbar == 8-k) { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int64(1< (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh8x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh8x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd8 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpRsh8Ux64 { break } if v_1_0_0_0.Type != t { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpRsh8x64 { break } if v_1_0_0_0_0.Type != t { break } _ = v_1_0_0_0_0.Args[1] if n != v_1_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.Type != typ.UInt64 { break } if v_1_0_0_0_0_1.AuxInt != 7 { break } v_1_0_0_0_1 := v_1_0_0_0.Args[1] if v_1_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_1.Type != typ.UInt64 { break } kbar := v_1_0_0_0_1.AuxInt if n != v_1_0_0.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 7 && kbar == 8-k) { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int64(1< n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh8x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd8 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] if n != v_0_0_0.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpRsh8Ux64 { break } if v_0_0_0_1.Type != t { break } _ = v_0_0_0_1.Args[1] v_0_0_0_1_0 := v_0_0_0_1.Args[0] if v_0_0_0_1_0.Op != OpRsh8x64 { break } if v_0_0_0_1_0.Type != t { break } _ = v_0_0_0_1_0.Args[1] if n != v_0_0_0_1_0.Args[0] { break } v_0_0_0_1_0_1 := v_0_0_0_1_0.Args[1] if v_0_0_0_1_0_1.Op != OpConst64 { break } if v_0_0_0_1_0_1.Type != typ.UInt64 { break } if v_0_0_0_1_0_1.AuxInt != 7 { break } v_0_0_0_1_1 := v_0_0_0_1.Args[1] if v_0_0_0_1_1.Op != OpConst64 { break } if v_0_0_0_1_1.Type != typ.UInt64 { break } kbar := v_0_0_0_1_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 7 && kbar == 8-k) { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int64(1< (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh8x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd8 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpRsh8Ux64 { break } if v_0_0_0_0.Type != t { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpRsh8x64 { break } if v_0_0_0_0_0.Type != t { break } _ = v_0_0_0_0_0.Args[1] if n != v_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.Type != typ.UInt64 { break } if v_0_0_0_0_0_1.AuxInt != 7 { break } v_0_0_0_0_1 := v_0_0_0_0.Args[1] if v_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_1.Type != typ.UInt64 { break } kbar := v_0_0_0_0_1.AuxInt if n != v_0_0_0.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 7 && kbar == 8-k) { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int64(1<= d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c >= d) return true } // match: (Geq16 (And16 _ (Const16 [c])) (Const16 [0])) // cond: int16(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } if !(int16(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (Geq16 (And16 (Const16 [c]) _) (Const16 [0])) // cond: int16(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } if !(int16(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } return false } func rewriteValuegeneric_OpGeq16U_0(v *Value) bool { // match: (Geq16U (Const16 [c]) (Const16 [d])) // cond: // result: (ConstBool [b2i(uint16(c) >= uint16(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint16(c) >= uint16(d)) return true } return false } func rewriteValuegeneric_OpGeq32_0(v *Value) bool { // match: (Geq32 (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(c >= d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c >= d) return true } // match: (Geq32 (And32 _ (Const32 [c])) (Const32 [0])) // cond: int32(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } if !(int32(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (Geq32 (And32 (Const32 [c]) _) (Const32 [0])) // cond: int32(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } if !(int32(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } return false } func rewriteValuegeneric_OpGeq32F_0(v *Value) bool { // match: (Geq32F (Const32F [c]) (Const32F [d])) // cond: // result: (ConstBool [b2i(auxTo32F(c) >= auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo32F(c) >= auxTo32F(d)) return true } return false } func rewriteValuegeneric_OpGeq32U_0(v *Value) bool { // match: (Geq32U (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(uint32(c) >= uint32(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint32(c) >= uint32(d)) return true } return false } func rewriteValuegeneric_OpGeq64_0(v *Value) bool { // match: (Geq64 (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(c >= d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c >= d) return true } // match: (Geq64 (And64 _ (Const64 [c])) (Const64 [0])) // cond: int64(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } if !(int64(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (Geq64 (And64 (Const64 [c]) _) (Const64 [0])) // cond: int64(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } if !(int64(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (Geq64 (Rsh64Ux64 _ (Const64 [c])) (Const64 [0])) // cond: c > 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } return false } func rewriteValuegeneric_OpGeq64F_0(v *Value) bool { // match: (Geq64F (Const64F [c]) (Const64F [d])) // cond: // result: (ConstBool [b2i(auxTo64F(c) >= auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo64F(c) >= auxTo64F(d)) return true } return false } func rewriteValuegeneric_OpGeq64U_0(v *Value) bool { // match: (Geq64U (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(uint64(c) >= uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint64(c) >= uint64(d)) return true } return false } func rewriteValuegeneric_OpGeq8_0(v *Value) bool { // match: (Geq8 (Const8 [c]) (Const8 [d])) // cond: // result: (ConstBool [b2i(c >= d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c >= d) return true } // match: (Geq8 (And8 _ (Const8 [c])) (Const8 [0])) // cond: int8(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } if !(int8(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (Geq8 (And8 (Const8 [c]) _) (Const8 [0])) // cond: int8(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } if !(int8(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } return false } func rewriteValuegeneric_OpGeq8U_0(v *Value) bool { // match: (Geq8U (Const8 [c]) (Const8 [d])) // cond: // result: (ConstBool [b2i(uint8(c) >= uint8(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint8(c) >= uint8(d)) return true } return false } func rewriteValuegeneric_OpGreater16_0(v *Value) bool { // match: (Greater16 (Const16 [c]) (Const16 [d])) // cond: // result: (ConstBool [b2i(c > d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c > d) return true } return false } func rewriteValuegeneric_OpGreater16U_0(v *Value) bool { // match: (Greater16U (Const16 [c]) (Const16 [d])) // cond: // result: (ConstBool [b2i(uint16(c) > uint16(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint16(c) > uint16(d)) return true } return false } func rewriteValuegeneric_OpGreater32_0(v *Value) bool { // match: (Greater32 (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(c > d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c > d) return true } return false } func rewriteValuegeneric_OpGreater32F_0(v *Value) bool { // match: (Greater32F (Const32F [c]) (Const32F [d])) // cond: // result: (ConstBool [b2i(auxTo32F(c) > auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo32F(c) > auxTo32F(d)) return true } return false } func rewriteValuegeneric_OpGreater32U_0(v *Value) bool { // match: (Greater32U (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(uint32(c) > uint32(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint32(c) > uint32(d)) return true } return false } func rewriteValuegeneric_OpGreater64_0(v *Value) bool { // match: (Greater64 (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(c > d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c > d) return true } return false } func rewriteValuegeneric_OpGreater64F_0(v *Value) bool { // match: (Greater64F (Const64F [c]) (Const64F [d])) // cond: // result: (ConstBool [b2i(auxTo64F(c) > auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo64F(c) > auxTo64F(d)) return true } return false } func rewriteValuegeneric_OpGreater64U_0(v *Value) bool { // match: (Greater64U (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(uint64(c) > uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint64(c) > uint64(d)) return true } return false } func rewriteValuegeneric_OpGreater8_0(v *Value) bool { // match: (Greater8 (Const8 [c]) (Const8 [d])) // cond: // result: (ConstBool [b2i(c > d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c > d) return true } return false } func rewriteValuegeneric_OpGreater8U_0(v *Value) bool { // match: (Greater8U (Const8 [c]) (Const8 [d])) // cond: // result: (ConstBool [b2i(uint8(c) > uint8(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint8(c) > uint8(d)) return true } return false } func rewriteValuegeneric_OpIMake_0(v *Value) bool { // match: (IMake typ (StructMake1 val)) // cond: // result: (IMake typ val) for { _ = v.Args[1] typ := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStructMake1 { break } val := v_1.Args[0] v.reset(OpIMake) v.AddArg(typ) v.AddArg(val) return true } // match: (IMake typ (ArrayMake1 val)) // cond: // result: (IMake typ val) for { _ = v.Args[1] typ := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpArrayMake1 { break } val := v_1.Args[0] v.reset(OpIMake) v.AddArg(typ) v.AddArg(val) return true } return false } func rewriteValuegeneric_OpInterCall_0(v *Value) bool { // match: (InterCall [argsize] (Load (OffPtr [off] (ITab (IMake (Addr {itab} (SB)) _))) _) mem) // cond: devirt(v, itab, off) != nil // result: (StaticCall [argsize] {devirt(v, itab, off)} mem) for { argsize := v.AuxInt mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLoad { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpOffPtr { break } off := v_0_0.AuxInt v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpITab { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpIMake { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAddr { break } itab := v_0_0_0_0_0.Aux v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpSB { break } if !(devirt(v, itab, off) != nil) { break } v.reset(OpStaticCall) v.AuxInt = argsize v.Aux = devirt(v, itab, off) v.AddArg(mem) return true } return false } func rewriteValuegeneric_OpIsInBounds_0(v *Value) bool { // match: (IsInBounds (ZeroExt8to32 _) (Const32 [c])) // cond: (1 << 8) <= c // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to32 { break } v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !((1 << 8) <= c) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to64 _) (Const64 [c])) // cond: (1 << 8) <= c // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to64 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !((1 << 8) <= c) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt16to32 _) (Const32 [c])) // cond: (1 << 16) <= c // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt16to32 { break } v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !((1 << 16) <= c) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt16to64 _) (Const64 [c])) // cond: (1 << 16) <= c // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt16to64 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !((1 << 16) <= c) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds x x) // cond: // result: (ConstBool [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (IsInBounds (And8 (Const8 [c]) _) (Const8 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (And8 _ (Const8 [c])) (Const8 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to16 (And8 (Const8 [c]) _)) (Const16 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpConst8 { break } c := v_0_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to16 (And8 _ (Const8 [c]))) (Const16 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } _ = v_0_0.Args[1] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst8 { break } c := v_0_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to32 (And8 (Const8 [c]) _)) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpConst8 { break } c := v_0_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } return false } func rewriteValuegeneric_OpIsInBounds_10(v *Value) bool { // match: (IsInBounds (ZeroExt8to32 (And8 _ (Const8 [c]))) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } _ = v_0_0.Args[1] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst8 { break } c := v_0_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to64 (And8 (Const8 [c]) _)) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpConst8 { break } c := v_0_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to64 (And8 _ (Const8 [c]))) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } _ = v_0_0.Args[1] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst8 { break } c := v_0_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (And16 (Const16 [c]) _) (Const16 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (And16 _ (Const16 [c])) (Const16 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt16to32 (And16 (Const16 [c]) _)) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt16to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpConst16 { break } c := v_0_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt16to32 (And16 _ (Const16 [c]))) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt16to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } _ = v_0_0.Args[1] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst16 { break } c := v_0_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt16to64 (And16 (Const16 [c]) _)) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt16to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpConst16 { break } c := v_0_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt16to64 (And16 _ (Const16 [c]))) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt16to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } _ = v_0_0.Args[1] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst16 { break } c := v_0_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (And32 (Const32 [c]) _) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } return false } func rewriteValuegeneric_OpIsInBounds_20(v *Value) bool { // match: (IsInBounds (And32 _ (Const32 [c])) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt32to64 (And32 (Const32 [c]) _)) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt32to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd32 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpConst32 { break } c := v_0_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt32to64 (And32 _ (Const32 [c]))) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt32to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd32 { break } _ = v_0_0.Args[1] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst32 { break } c := v_0_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (And64 (Const64 [c]) _) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (And64 _ (Const64 [c])) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(0 <= c && c < d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(0 <= c && c < d) return true } // match: (IsInBounds (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(0 <= c && c < d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(0 <= c && c < d) return true } // match: (IsInBounds (Mod32u _ y) y) // cond: // result: (ConstBool [1]) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMod32u { break } _ = v_0.Args[1] if y != v_0.Args[1] { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (Mod64u _ y) y) // cond: // result: (ConstBool [1]) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMod64u { break } _ = v_0.Args[1] if y != v_0.Args[1] { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to64 (Rsh8Ux64 _ (Const64 [c]))) (Const64 [d])) // cond: 0 < c && c < 8 && 1< p1 (Store {t2} p2 x _)) // cond: isSamePtr(p1, p2) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) // result: x for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] x := v_1.Args[1] if !(isSamePtr(p1, p2) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 x _))) // cond: isSamePtr(p1, p3) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) && disjoint(p3, sizeof(t3), p2, sizeof(t2)) // result: x for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := v_1_2.Aux _ = v_1_2.Args[2] p3 := v_1_2.Args[0] x := v_1_2.Args[1] if !(isSamePtr(p1, p3) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) && disjoint(p3, sizeof(t3), p2, sizeof(t2))) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 x _)))) // cond: isSamePtr(p1, p4) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) && disjoint(p4, sizeof(t4), p2, sizeof(t2)) && disjoint(p4, sizeof(t4), p3, sizeof(t3)) // result: x for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := v_1_2.Aux _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := v_1_2_2.Aux _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] x := v_1_2_2.Args[1] if !(isSamePtr(p1, p4) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) && disjoint(p4, sizeof(t4), p2, sizeof(t2)) && disjoint(p4, sizeof(t4), p3, sizeof(t3))) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 x _))))) // cond: isSamePtr(p1, p5) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) && disjoint(p5, sizeof(t5), p2, sizeof(t2)) && disjoint(p5, sizeof(t5), p3, sizeof(t3)) && disjoint(p5, sizeof(t5), p4, sizeof(t4)) // result: x for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := v_1_2.Aux _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := v_1_2_2.Aux _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] v_1_2_2_2 := v_1_2_2.Args[2] if v_1_2_2_2.Op != OpStore { break } t5 := v_1_2_2_2.Aux _ = v_1_2_2_2.Args[2] p5 := v_1_2_2_2.Args[0] x := v_1_2_2_2.Args[1] if !(isSamePtr(p1, p5) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) && disjoint(p5, sizeof(t5), p2, sizeof(t2)) && disjoint(p5, sizeof(t5), p3, sizeof(t3)) && disjoint(p5, sizeof(t5), p4, sizeof(t4))) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Load p1 (Store {t2} p2 (Const64 [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitFloat(t1) // result: (Const64F [x]) for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } x := v_1_1.AuxInt if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitFloat(t1)) { break } v.reset(OpConst64F) v.AuxInt = x return true } // match: (Load p1 (Store {t2} p2 (Const32 [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitFloat(t1) // result: (Const32F [auxFrom32F(math.Float32frombits(uint32(x)))]) for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } x := v_1_1.AuxInt if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitFloat(t1)) { break } v.reset(OpConst32F) v.AuxInt = auxFrom32F(math.Float32frombits(uint32(x))) return true } // match: (Load p1 (Store {t2} p2 (Const64F [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitInt(t1) // result: (Const64 [x]) for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64F { break } x := v_1_1.AuxInt if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitInt(t1)) { break } v.reset(OpConst64) v.AuxInt = x return true } // match: (Load p1 (Store {t2} p2 (Const32F [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitInt(t1) // result: (Const32 [int64(int32(math.Float32bits(auxTo32F(x))))]) for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32F { break } x := v_1_1.AuxInt if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitInt(t1)) { break } v.reset(OpConst32) v.AuxInt = int64(int32(math.Float32bits(auxTo32F(x)))) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ mem:(Zero [n] p3 _))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p3) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) // result: @mem.Block (Load (OffPtr [o1] p3) mem) for { t1 := v.Type _ = v.Args[1] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] mem := v_1.Args[2] if mem.Op != OpZero { break } n := mem.AuxInt _ = mem.Args[1] p3 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p3) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2))) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = o1 v1.AddArg(p3) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ mem:(Zero [n] p4 _)))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p4) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) && disjoint(op, t1.Size(), p3, sizeof(t3)) // result: @mem.Block (Load (OffPtr [o1] p4) mem) for { t1 := v.Type _ = v.Args[1] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := v_1_2.Aux _ = v_1_2.Args[2] p3 := v_1_2.Args[0] mem := v_1_2.Args[2] if mem.Op != OpZero { break } n := mem.AuxInt _ = mem.Args[1] p4 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p4) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) && disjoint(op, t1.Size(), p3, sizeof(t3))) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = o1 v1.AddArg(p4) v0.AddArg(v1) v0.AddArg(mem) return true } return false } func rewriteValuegeneric_OpLoad_10(v *Value) bool { b := v.Block fe := b.Func.fe // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ mem:(Zero [n] p5 _))))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p5) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) && disjoint(op, t1.Size(), p3, sizeof(t3)) && disjoint(op, t1.Size(), p4, sizeof(t4)) // result: @mem.Block (Load (OffPtr [o1] p5) mem) for { t1 := v.Type _ = v.Args[1] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := v_1_2.Aux _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := v_1_2_2.Aux _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] mem := v_1_2_2.Args[2] if mem.Op != OpZero { break } n := mem.AuxInt _ = mem.Args[1] p5 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p5) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) && disjoint(op, t1.Size(), p3, sizeof(t3)) && disjoint(op, t1.Size(), p4, sizeof(t4))) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = o1 v1.AddArg(p5) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 _ mem:(Zero [n] p6 _)))))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p6) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) && disjoint(op, t1.Size(), p3, sizeof(t3)) && disjoint(op, t1.Size(), p4, sizeof(t4)) && disjoint(op, t1.Size(), p5, sizeof(t5)) // result: @mem.Block (Load (OffPtr [o1] p6) mem) for { t1 := v.Type _ = v.Args[1] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := v_1_2.Aux _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := v_1_2_2.Aux _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] v_1_2_2_2 := v_1_2_2.Args[2] if v_1_2_2_2.Op != OpStore { break } t5 := v_1_2_2_2.Aux _ = v_1_2_2_2.Args[2] p5 := v_1_2_2_2.Args[0] mem := v_1_2_2_2.Args[2] if mem.Op != OpZero { break } n := mem.AuxInt _ = mem.Args[1] p6 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p6) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) && disjoint(op, t1.Size(), p3, sizeof(t3)) && disjoint(op, t1.Size(), p4, sizeof(t4)) && disjoint(op, t1.Size(), p5, sizeof(t5))) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = o1 v1.AddArg(p6) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: t1.IsBoolean() && isSamePtr(p1, p2) && n >= o + 1 // result: (ConstBool [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(t1.IsBoolean() && isSamePtr(p1, p2) && n >= o+1) { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is8BitInt(t1) && isSamePtr(p1, p2) && n >= o + 1 // result: (Const8 [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(is8BitInt(t1) && isSamePtr(p1, p2) && n >= o+1) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is16BitInt(t1) && isSamePtr(p1, p2) && n >= o + 2 // result: (Const16 [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(is16BitInt(t1) && isSamePtr(p1, p2) && n >= o+2) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is32BitInt(t1) && isSamePtr(p1, p2) && n >= o + 4 // result: (Const32 [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(is32BitInt(t1) && isSamePtr(p1, p2) && n >= o+4) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is64BitInt(t1) && isSamePtr(p1, p2) && n >= o + 8 // result: (Const64 [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(is64BitInt(t1) && isSamePtr(p1, p2) && n >= o+8) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is32BitFloat(t1) && isSamePtr(p1, p2) && n >= o + 4 // result: (Const32F [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(is32BitFloat(t1) && isSamePtr(p1, p2) && n >= o+4) { break } v.reset(OpConst32F) v.AuxInt = 0 return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is64BitFloat(t1) && isSamePtr(p1, p2) && n >= o + 8 // result: (Const64F [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(is64BitFloat(t1) && isSamePtr(p1, p2) && n >= o+8) { break } v.reset(OpConst64F) v.AuxInt = 0 return true } // match: (Load _ _) // cond: t.IsStruct() && t.NumFields() == 0 && fe.CanSSA(t) // result: (StructMake0) for { t := v.Type _ = v.Args[1] if !(t.IsStruct() && t.NumFields() == 0 && fe.CanSSA(t)) { break } v.reset(OpStructMake0) return true } return false } func rewriteValuegeneric_OpLoad_20(v *Value) bool { b := v.Block fe := b.Func.fe // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 1 && fe.CanSSA(t) // result: (StructMake1 (Load (OffPtr [0] ptr) mem)) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsStruct() && t.NumFields() == 1 && fe.CanSSA(t)) { break } v.reset(OpStructMake1) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = 0 v1.AddArg(ptr) v0.AddArg(v1) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 2 && fe.CanSSA(t) // result: (StructMake2 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem)) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsStruct() && t.NumFields() == 2 && fe.CanSSA(t)) { break } v.reset(OpStructMake2) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = 0 v1.AddArg(ptr) v0.AddArg(v1) v0.AddArg(mem) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = t.FieldOff(1) v3.AddArg(ptr) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 3 && fe.CanSSA(t) // result: (StructMake3 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem) (Load (OffPtr [t.FieldOff(2)] ptr) mem)) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsStruct() && t.NumFields() == 3 && fe.CanSSA(t)) { break } v.reset(OpStructMake3) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = 0 v1.AddArg(ptr) v0.AddArg(v1) v0.AddArg(mem) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = t.FieldOff(1) v3.AddArg(ptr) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2)) v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v5.AuxInt = t.FieldOff(2) v5.AddArg(ptr) v4.AddArg(v5) v4.AddArg(mem) v.AddArg(v4) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 4 && fe.CanSSA(t) // result: (StructMake4 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem) (Load (OffPtr [t.FieldOff(2)] ptr) mem) (Load (OffPtr [t.FieldOff(3)] ptr) mem)) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsStruct() && t.NumFields() == 4 && fe.CanSSA(t)) { break } v.reset(OpStructMake4) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = 0 v1.AddArg(ptr) v0.AddArg(v1) v0.AddArg(mem) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = t.FieldOff(1) v3.AddArg(ptr) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2)) v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v5.AuxInt = t.FieldOff(2) v5.AddArg(ptr) v4.AddArg(v5) v4.AddArg(mem) v.AddArg(v4) v6 := b.NewValue0(v.Pos, OpLoad, t.FieldType(3)) v7 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo()) v7.AuxInt = t.FieldOff(3) v7.AddArg(ptr) v6.AddArg(v7) v6.AddArg(mem) v.AddArg(v6) return true } // match: (Load _ _) // cond: t.IsArray() && t.NumElem() == 0 // result: (ArrayMake0) for { t := v.Type _ = v.Args[1] if !(t.IsArray() && t.NumElem() == 0) { break } v.reset(OpArrayMake0) return true } // match: (Load ptr mem) // cond: t.IsArray() && t.NumElem() == 1 && fe.CanSSA(t) // result: (ArrayMake1 (Load ptr mem)) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsArray() && t.NumElem() == 1 && fe.CanSSA(t)) { break } v.reset(OpArrayMake1) v0 := b.NewValue0(v.Pos, OpLoad, t.Elem()) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh16x16_0(v *Value) bool { b := v.Block // match: (Lsh16x16 x (Const16 [c])) // cond: // result: (Lsh16x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpLsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Lsh16x16 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh16x32_0(v *Value) bool { b := v.Block // match: (Lsh16x32 x (Const32 [c])) // cond: // result: (Lsh16x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpLsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Lsh16x32 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh16x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x64 (Const16 [c]) (Const64 [d])) // cond: // result: (Const16 [int64(int16(c) << uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c) << uint64(d)) return true } // match: (Lsh16x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Lsh16x64 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Lsh16x64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Lsh16x64 (Lsh16x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh16x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpLsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Lsh16x64 (Rsh16Ux64 (Lsh16x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh16x64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh16x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh16x8_0(v *Value) bool { b := v.Block // match: (Lsh16x8 x (Const8 [c])) // cond: // result: (Lsh16x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpLsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Lsh16x8 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh32x16_0(v *Value) bool { b := v.Block // match: (Lsh32x16 x (Const16 [c])) // cond: // result: (Lsh32x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpLsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Lsh32x16 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh32x32_0(v *Value) bool { b := v.Block // match: (Lsh32x32 x (Const32 [c])) // cond: // result: (Lsh32x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpLsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Lsh32x32 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh32x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x64 (Const32 [c]) (Const64 [d])) // cond: // result: (Const32 [int64(int32(c) << uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c) << uint64(d)) return true } // match: (Lsh32x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Lsh32x64 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Lsh32x64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Lsh32x64 (Lsh32x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh32x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpLsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Lsh32x64 (Rsh32Ux64 (Lsh32x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh32x64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh32x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh32x8_0(v *Value) bool { b := v.Block // match: (Lsh32x8 x (Const8 [c])) // cond: // result: (Lsh32x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpLsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Lsh32x8 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh64x16_0(v *Value) bool { b := v.Block // match: (Lsh64x16 x (Const16 [c])) // cond: // result: (Lsh64x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpLsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Lsh64x16 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh64x32_0(v *Value) bool { b := v.Block // match: (Lsh64x32 x (Const32 [c])) // cond: // result: (Lsh64x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpLsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Lsh64x32 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh64x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c << uint64(d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c << uint64(d) return true } // match: (Lsh64x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Lsh64x64 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Lsh64x64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (Const64 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Lsh64x64 (Lsh64x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh64x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpLsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Lsh64x64 (Rsh64Ux64 (Lsh64x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh64x64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh64x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh64x8_0(v *Value) bool { b := v.Block // match: (Lsh64x8 x (Const8 [c])) // cond: // result: (Lsh64x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpLsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Lsh64x8 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh8x16_0(v *Value) bool { b := v.Block // match: (Lsh8x16 x (Const16 [c])) // cond: // result: (Lsh8x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpLsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Lsh8x16 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh8x32_0(v *Value) bool { b := v.Block // match: (Lsh8x32 x (Const32 [c])) // cond: // result: (Lsh8x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpLsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Lsh8x32 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh8x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x64 (Const8 [c]) (Const64 [d])) // cond: // result: (Const8 [int64(int8(c) << uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c) << uint64(d)) return true } // match: (Lsh8x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Lsh8x64 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Lsh8x64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Lsh8x64 (Lsh8x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh8x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpLsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Lsh8x64 (Rsh8Ux64 (Lsh8x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh8x64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh8x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh8x8_0(v *Value) bool { b := v.Block // match: (Lsh8x8 x (Const8 [c])) // cond: // result: (Lsh8x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpLsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Lsh8x8 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpMod16_0(v *Value) bool { b := v.Block // match: (Mod16 (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int64(int16(c % d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int64(int16(c % d)) return true } // match: (Mod16 n (Const16 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c&0xffff) // result: (And16 n (Const16 [(c&0xffff)-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c&0xffff)) { break } v.reset(OpAnd16) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = (c & 0xffff) - 1 v.AddArg(v0) return true } // match: (Mod16 n (Const16 [c])) // cond: c < 0 && c != -1<<15 // result: (Mod16 n (Const16 [-c])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<15) { break } v.reset(OpMod16) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = -c v.AddArg(v0) return true } // match: (Mod16 x (Const16 [c])) // cond: x.Op != OpConst16 && (c > 0 || c == -1<<15) // result: (Sub16 x (Mul16 (Div16 x (Const16 [c])) (Const16 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(x.Op != OpConst16 && (c > 0 || c == -1<<15)) { break } v.reset(OpSub16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul16, t) v1 := b.NewValue0(v.Pos, OpDiv16, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod16u_0(v *Value) bool { b := v.Block // match: (Mod16u (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int64(uint16(c) % uint16(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int64(uint16(c) % uint16(d)) return true } // match: (Mod16u n (Const16 [c])) // cond: isPowerOfTwo(c&0xffff) // result: (And16 n (Const16 [(c&0xffff)-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(isPowerOfTwo(c & 0xffff)) { break } v.reset(OpAnd16) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = (c & 0xffff) - 1 v.AddArg(v0) return true } // match: (Mod16u x (Const16 [c])) // cond: x.Op != OpConst16 && c > 0 && umagicOK(16,c) // result: (Sub16 x (Mul16 (Div16u x (Const16 [c])) (Const16 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(x.Op != OpConst16 && c > 0 && umagicOK(16, c)) { break } v.reset(OpSub16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul16, t) v1 := b.NewValue0(v.Pos, OpDiv16u, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod32_0(v *Value) bool { b := v.Block // match: (Mod32 (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int64(int32(c % d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int64(int32(c % d)) return true } // match: (Mod32 n (Const32 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c&0xffffffff) // result: (And32 n (Const32 [(c&0xffffffff)-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c&0xffffffff)) { break } v.reset(OpAnd32) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = (c & 0xffffffff) - 1 v.AddArg(v0) return true } // match: (Mod32 n (Const32 [c])) // cond: c < 0 && c != -1<<31 // result: (Mod32 n (Const32 [-c])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<31) { break } v.reset(OpMod32) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = -c v.AddArg(v0) return true } // match: (Mod32 x (Const32 [c])) // cond: x.Op != OpConst32 && (c > 0 || c == -1<<31) // result: (Sub32 x (Mul32 (Div32 x (Const32 [c])) (Const32 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(x.Op != OpConst32 && (c > 0 || c == -1<<31)) { break } v.reset(OpSub32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul32, t) v1 := b.NewValue0(v.Pos, OpDiv32, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod32u_0(v *Value) bool { b := v.Block // match: (Mod32u (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int64(uint32(c) % uint32(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int64(uint32(c) % uint32(d)) return true } // match: (Mod32u n (Const32 [c])) // cond: isPowerOfTwo(c&0xffffffff) // result: (And32 n (Const32 [(c&0xffffffff)-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(isPowerOfTwo(c & 0xffffffff)) { break } v.reset(OpAnd32) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = (c & 0xffffffff) - 1 v.AddArg(v0) return true } // match: (Mod32u x (Const32 [c])) // cond: x.Op != OpConst32 && c > 0 && umagicOK(32,c) // result: (Sub32 x (Mul32 (Div32u x (Const32 [c])) (Const32 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(x.Op != OpConst32 && c > 0 && umagicOK(32, c)) { break } v.reset(OpSub32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul32, t) v1 := b.NewValue0(v.Pos, OpDiv32u, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod64_0(v *Value) bool { b := v.Block // match: (Mod64 (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [c % d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = c % d return true } // match: (Mod64 n (Const64 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c) // result: (And64 n (Const64 [c-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c)) { break } v.reset(OpAnd64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - 1 v.AddArg(v0) return true } // match: (Mod64 n (Const64 [-1<<63])) // cond: isNonNegative(n) // result: n for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1<<63 { break } if !(isNonNegative(n)) { break } v.reset(OpCopy) v.Type = n.Type v.AddArg(n) return true } // match: (Mod64 n (Const64 [c])) // cond: c < 0 && c != -1<<63 // result: (Mod64 n (Const64 [-c])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<63) { break } v.reset(OpMod64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = -c v.AddArg(v0) return true } // match: (Mod64 x (Const64 [c])) // cond: x.Op != OpConst64 && (c > 0 || c == -1<<63) // result: (Sub64 x (Mul64 (Div64 x (Const64 [c])) (Const64 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(x.Op != OpConst64 && (c > 0 || c == -1<<63)) { break } v.reset(OpSub64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul64, t) v1 := b.NewValue0(v.Pos, OpDiv64, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod64u_0(v *Value) bool { b := v.Block // match: (Mod64u (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [int64(uint64(c) % uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64(uint64(c) % uint64(d)) return true } // match: (Mod64u n (Const64 [c])) // cond: isPowerOfTwo(c) // result: (And64 n (Const64 [c-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpAnd64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - 1 v.AddArg(v0) return true } // match: (Mod64u n (Const64 [-1<<63])) // cond: // result: (And64 n (Const64 [1<<63-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1<<63 { break } v.reset(OpAnd64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = 1<<63 - 1 v.AddArg(v0) return true } // match: (Mod64u x (Const64 [c])) // cond: x.Op != OpConst64 && c > 0 && umagicOK(64,c) // result: (Sub64 x (Mul64 (Div64u x (Const64 [c])) (Const64 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(x.Op != OpConst64 && c > 0 && umagicOK(64, c)) { break } v.reset(OpSub64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul64, t) v1 := b.NewValue0(v.Pos, OpDiv64u, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod8_0(v *Value) bool { b := v.Block // match: (Mod8 (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int64(int8(c % d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int64(int8(c % d)) return true } // match: (Mod8 n (Const8 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c&0xff) // result: (And8 n (Const8 [(c&0xff)-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c&0xff)) { break } v.reset(OpAnd8) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = (c & 0xff) - 1 v.AddArg(v0) return true } // match: (Mod8 n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Mod8 n (Const8 [-c])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<7) { break } v.reset(OpMod8) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = -c v.AddArg(v0) return true } // match: (Mod8 x (Const8 [c])) // cond: x.Op != OpConst8 && (c > 0 || c == -1<<7) // result: (Sub8 x (Mul8 (Div8 x (Const8 [c])) (Const8 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(x.Op != OpConst8 && (c > 0 || c == -1<<7)) { break } v.reset(OpSub8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul8, t) v1 := b.NewValue0(v.Pos, OpDiv8, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod8u_0(v *Value) bool { b := v.Block // match: (Mod8u (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int64(uint8(c) % uint8(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int64(uint8(c) % uint8(d)) return true } // match: (Mod8u n (Const8 [c])) // cond: isPowerOfTwo(c&0xff) // result: (And8 n (Const8 [(c&0xff)-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(isPowerOfTwo(c & 0xff)) { break } v.reset(OpAnd8) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = (c & 0xff) - 1 v.AddArg(v0) return true } // match: (Mod8u x (Const8 [c])) // cond: x.Op != OpConst8 && c > 0 && umagicOK(8,c) // result: (Sub8 x (Mul8 (Div8u x (Const8 [c])) (Const8 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(x.Op != OpConst8 && c > 0 && umagicOK(8, c)) { break } v.reset(OpSub8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul8, t) v1 := b.NewValue0(v.Pos, OpDiv8u, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMove_0(v *Value) bool { b := v.Block // match: (Move {t} [n] dst1 src mem:(Zero {t} [n] dst2 _)) // cond: isSamePtr(src, dst2) // result: (Zero {t} [n] dst1 mem) for { n := v.AuxInt t := v.Aux _ = v.Args[2] dst1 := v.Args[0] src := v.Args[1] mem := v.Args[2] if mem.Op != OpZero { break } if mem.AuxInt != n { break } if mem.Aux != t { break } _ = mem.Args[1] dst2 := mem.Args[0] if !(isSamePtr(src, dst2)) { break } v.reset(OpZero) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(mem) return true } // match: (Move {t} [n] dst1 src mem:(VarDef (Zero {t} [n] dst0 _))) // cond: isSamePtr(src, dst0) // result: (Zero {t} [n] dst1 mem) for { n := v.AuxInt t := v.Aux _ = v.Args[2] dst1 := v.Args[0] src := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpZero { break } if mem_0.AuxInt != n { break } if mem_0.Aux != t { break } _ = mem_0.Args[1] dst0 := mem_0.Args[0] if !(isSamePtr(src, dst0)) { break } v.reset(OpZero) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(mem) return true } // match: (Move {t1} [n] dst1 src1 store:(Store {t2} op:(OffPtr [o2] dst2) _ mem)) // cond: isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2 + sizeof(t2) && disjoint(src1, n, op, sizeof(t2)) && clobber(store) // result: (Move {t1} [n] dst1 src1 mem) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst1 := v.Args[0] src1 := v.Args[1] store := v.Args[2] if store.Op != OpStore { break } t2 := store.Aux mem := store.Args[2] op := store.Args[0] if op.Op != OpOffPtr { break } o2 := op.AuxInt dst2 := op.Args[0] if !(isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2+sizeof(t2) && disjoint(src1, n, op, sizeof(t2)) && clobber(store)) { break } v.reset(OpMove) v.AuxInt = n v.Aux = t1 v.AddArg(dst1) v.AddArg(src1) v.AddArg(mem) return true } // match: (Move {t} [n] dst1 src1 move:(Move {t} [n] dst2 _ mem)) // cond: move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move) // result: (Move {t} [n] dst1 src1 mem) for { n := v.AuxInt t := v.Aux _ = v.Args[2] dst1 := v.Args[0] src1 := v.Args[1] move := v.Args[2] if move.Op != OpMove { break } if move.AuxInt != n { break } if move.Aux != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move)) { break } v.reset(OpMove) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(src1) v.AddArg(mem) return true } // match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem))) // cond: move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move) && clobber(vardef) // result: (Move {t} [n] dst1 src1 (VarDef {x} mem)) for { n := v.AuxInt t := v.Aux _ = v.Args[2] dst1 := v.Args[0] src1 := v.Args[1] vardef := v.Args[2] if vardef.Op != OpVarDef { break } x := vardef.Aux move := vardef.Args[0] if move.Op != OpMove { break } if move.AuxInt != n { break } if move.Aux != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move) && clobber(vardef)) { break } v.reset(OpMove) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(src1) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = x v0.AddArg(mem) v.AddArg(v0) return true } // match: (Move {t} [n] dst1 src1 zero:(Zero {t} [n] dst2 mem)) // cond: zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero) // result: (Move {t} [n] dst1 src1 mem) for { n := v.AuxInt t := v.Aux _ = v.Args[2] dst1 := v.Args[0] src1 := v.Args[1] zero := v.Args[2] if zero.Op != OpZero { break } if zero.AuxInt != n { break } if zero.Aux != t { break } mem := zero.Args[1] dst2 := zero.Args[0] if !(zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero)) { break } v.reset(OpMove) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(src1) v.AddArg(mem) return true } // match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} zero:(Zero {t} [n] dst2 mem))) // cond: zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero) && clobber(vardef) // result: (Move {t} [n] dst1 src1 (VarDef {x} mem)) for { n := v.AuxInt t := v.Aux _ = v.Args[2] dst1 := v.Args[0] src1 := v.Args[1] vardef := v.Args[2] if vardef.Op != OpVarDef { break } x := vardef.Aux zero := vardef.Args[0] if zero.Op != OpZero { break } if zero.AuxInt != n { break } if zero.Aux != t { break } mem := zero.Args[1] dst2 := zero.Args[0] if !(zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero) && clobber(vardef)) { break } v.reset(OpMove) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(src1) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = x v0.AddArg(mem) v.AddArg(v0) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [0] p3) d2 _))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && o2 == sizeof(t3) && n == sizeof(t2) + sizeof(t3) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [0] dst) d2 mem)) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type if op3.AuxInt != 0 { break } p3 := op3.Args[0] d2 := mem_2.Args[1] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && o2 == sizeof(t3) && n == sizeof(t2)+sizeof(t3)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = 0 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [0] p4) d3 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2) + sizeof(t3) + sizeof(t4) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [0] dst) d3 mem))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := op3.AuxInt p3 := op3.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := mem_2_2.Aux _ = mem_2_2.Args[2] op4 := mem_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type if op4.AuxInt != 0 { break } p4 := op4.Args[0] d3 := mem_2_2.Args[1] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2)+sizeof(t3)+sizeof(t4)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = 0 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [o4] p4) d3 (Store {t5} op5:(OffPtr [0] p5) d4 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == sizeof(t5) && o3-o4 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2) + sizeof(t3) + sizeof(t4) + sizeof(t5) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [0] dst) d4 mem)))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := op3.AuxInt p3 := op3.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := mem_2_2.Aux _ = mem_2_2.Args[2] op4 := mem_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type o4 := op4.AuxInt p4 := op4.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpStore { break } t5 := mem_2_2_2.Aux _ = mem_2_2_2.Args[2] op5 := mem_2_2_2.Args[0] if op5.Op != OpOffPtr { break } tt5 := op5.Type if op5.AuxInt != 0 { break } p5 := op5.Args[0] d4 := mem_2_2_2.Args[1] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == sizeof(t5) && o3-o4 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2)+sizeof(t3)+sizeof(t4)+sizeof(t5)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = o4 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = t5 v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = 0 v6.AddArg(dst) v5.AddArg(v6) v5.AddArg(d4) v5.AddArg(mem) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } return false } func rewriteValuegeneric_OpMove_10(v *Value) bool { b := v.Block // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [0] p3) d2 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && o2 == sizeof(t3) && n == sizeof(t2) + sizeof(t3) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [0] dst) d2 mem)) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type if op3.AuxInt != 0 { break } p3 := op3.Args[0] d2 := mem_0_2.Args[1] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && o2 == sizeof(t3) && n == sizeof(t2)+sizeof(t3)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = 0 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [0] p4) d3 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2) + sizeof(t3) + sizeof(t4) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [0] dst) d3 mem))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := op3.AuxInt p3 := op3.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := mem_0_2_2.Aux _ = mem_0_2_2.Args[2] op4 := mem_0_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type if op4.AuxInt != 0 { break } p4 := op4.Args[0] d3 := mem_0_2_2.Args[1] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2)+sizeof(t3)+sizeof(t4)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = 0 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [o4] p4) d3 (Store {t5} op5:(OffPtr [0] p5) d4 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == sizeof(t5) && o3-o4 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2) + sizeof(t3) + sizeof(t4) + sizeof(t5) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [0] dst) d4 mem)))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := op3.AuxInt p3 := op3.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := mem_0_2_2.Aux _ = mem_0_2_2.Args[2] op4 := mem_0_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type o4 := op4.AuxInt p4 := op4.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpStore { break } t5 := mem_0_2_2_2.Aux _ = mem_0_2_2_2.Args[2] op5 := mem_0_2_2_2.Args[0] if op5.Op != OpOffPtr { break } tt5 := op5.Type if op5.AuxInt != 0 { break } p5 := op5.Args[0] d4 := mem_0_2_2_2.Args[1] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == sizeof(t5) && o3-o4 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2)+sizeof(t3)+sizeof(t4)+sizeof(t5)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = o4 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = t5 v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = 0 v6.AddArg(dst) v5.AddArg(v6) v5.AddArg(d4) v5.AddArg(mem) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Zero {t3} [n] p3 _))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && n >= o2 + sizeof(t2) // result: (Store {t2} (OffPtr [o2] dst) d1 (Zero {t1} [n] dst mem)) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpZero { break } if mem_2.AuxInt != n { break } t3 := mem_2.Aux _ = mem_2.Args[1] p3 := mem_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && n >= o2+sizeof(t2)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = n v1.Aux = t1 v1.AddArg(dst) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Zero {t4} [n] p4 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + sizeof(t2) && n >= o3 + sizeof(t3) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Zero {t1} [n] dst mem))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := mem_0.AuxInt p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := mem_2_0.AuxInt p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpZero { break } if mem_2_2.AuxInt != n { break } t4 := mem_2_2.Aux _ = mem_2_2.Args[1] p4 := mem_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && n >= o2+sizeof(t2) && n >= o3+sizeof(t3)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v3.AuxInt = n v3.Aux = t1 v3.AddArg(dst) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Zero {t5} [n] p5 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + sizeof(t2) && n >= o3 + sizeof(t3) && n >= o4 + sizeof(t4) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Zero {t1} [n] dst mem)))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := mem_0.AuxInt p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := mem_2_0.AuxInt p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := mem_2_2.Aux _ = mem_2_2.Args[2] mem_2_2_0 := mem_2_2.Args[0] if mem_2_2_0.Op != OpOffPtr { break } tt4 := mem_2_2_0.Type o4 := mem_2_2_0.AuxInt p4 := mem_2_2_0.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpZero { break } if mem_2_2_2.AuxInt != n { break } t5 := mem_2_2_2.Aux _ = mem_2_2_2.Args[1] p5 := mem_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+sizeof(t2) && n >= o3+sizeof(t3) && n >= o4+sizeof(t4)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = o4 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v5.AuxInt = n v5.Aux = t1 v5.AddArg(dst) v5.AddArg(mem) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Store {t5} (OffPtr [o5] p5) d4 (Zero {t6} [n] p6 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && alignof(t6) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + sizeof(t2) && n >= o3 + sizeof(t3) && n >= o4 + sizeof(t4) && n >= o5 + sizeof(t5) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [o5] dst) d4 (Zero {t1} [n] dst mem))))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := mem_0.AuxInt p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := mem_2_0.AuxInt p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := mem_2_2.Aux _ = mem_2_2.Args[2] mem_2_2_0 := mem_2_2.Args[0] if mem_2_2_0.Op != OpOffPtr { break } tt4 := mem_2_2_0.Type o4 := mem_2_2_0.AuxInt p4 := mem_2_2_0.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpStore { break } t5 := mem_2_2_2.Aux _ = mem_2_2_2.Args[2] mem_2_2_2_0 := mem_2_2_2.Args[0] if mem_2_2_2_0.Op != OpOffPtr { break } tt5 := mem_2_2_2_0.Type o5 := mem_2_2_2_0.AuxInt p5 := mem_2_2_2_0.Args[0] d4 := mem_2_2_2.Args[1] mem_2_2_2_2 := mem_2_2_2.Args[2] if mem_2_2_2_2.Op != OpZero { break } if mem_2_2_2_2.AuxInt != n { break } t6 := mem_2_2_2_2.Aux _ = mem_2_2_2_2.Args[1] p6 := mem_2_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && alignof(t6) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+sizeof(t2) && n >= o3+sizeof(t3) && n >= o4+sizeof(t4) && n >= o5+sizeof(t5)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = o4 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = t5 v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = o5 v6.AddArg(dst) v5.AddArg(v6) v5.AddArg(d4) v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v7.AuxInt = n v7.Aux = t1 v7.AddArg(dst) v7.AddArg(mem) v5.AddArg(v7) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Zero {t3} [n] p3 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && n >= o2 + sizeof(t2) // result: (Store {t2} (OffPtr [o2] dst) d1 (Zero {t1} [n] dst mem)) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpZero { break } if mem_0_2.AuxInt != n { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[1] p3 := mem_0_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && n >= o2+sizeof(t2)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = n v1.Aux = t1 v1.AddArg(dst) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Zero {t4} [n] p4 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + sizeof(t2) && n >= o3 + sizeof(t3) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Zero {t1} [n] dst mem))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := mem_0_0.AuxInt p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := mem_0_2_0.AuxInt p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpZero { break } if mem_0_2_2.AuxInt != n { break } t4 := mem_0_2_2.Aux _ = mem_0_2_2.Args[1] p4 := mem_0_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && n >= o2+sizeof(t2) && n >= o3+sizeof(t3)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v3.AuxInt = n v3.Aux = t1 v3.AddArg(dst) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Zero {t5} [n] p5 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + sizeof(t2) && n >= o3 + sizeof(t3) && n >= o4 + sizeof(t4) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Zero {t1} [n] dst mem)))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := mem_0_0.AuxInt p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := mem_0_2_0.AuxInt p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := mem_0_2_2.Aux _ = mem_0_2_2.Args[2] mem_0_2_2_0 := mem_0_2_2.Args[0] if mem_0_2_2_0.Op != OpOffPtr { break } tt4 := mem_0_2_2_0.Type o4 := mem_0_2_2_0.AuxInt p4 := mem_0_2_2_0.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpZero { break } if mem_0_2_2_2.AuxInt != n { break } t5 := mem_0_2_2_2.Aux _ = mem_0_2_2_2.Args[1] p5 := mem_0_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+sizeof(t2) && n >= o3+sizeof(t3) && n >= o4+sizeof(t4)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = o4 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v5.AuxInt = n v5.Aux = t1 v5.AddArg(dst) v5.AddArg(mem) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } return false } func rewriteValuegeneric_OpMove_20(v *Value) bool { b := v.Block config := b.Func.Config // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Store {t5} (OffPtr [o5] p5) d4 (Zero {t6} [n] p6 _))))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && alignof(t6) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + sizeof(t2) && n >= o3 + sizeof(t3) && n >= o4 + sizeof(t4) && n >= o5 + sizeof(t5) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [o5] dst) d4 (Zero {t1} [n] dst mem))))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := mem_0_0.AuxInt p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := mem_0_2_0.AuxInt p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := mem_0_2_2.Aux _ = mem_0_2_2.Args[2] mem_0_2_2_0 := mem_0_2_2.Args[0] if mem_0_2_2_0.Op != OpOffPtr { break } tt4 := mem_0_2_2_0.Type o4 := mem_0_2_2_0.AuxInt p4 := mem_0_2_2_0.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpStore { break } t5 := mem_0_2_2_2.Aux _ = mem_0_2_2_2.Args[2] mem_0_2_2_2_0 := mem_0_2_2_2.Args[0] if mem_0_2_2_2_0.Op != OpOffPtr { break } tt5 := mem_0_2_2_2_0.Type o5 := mem_0_2_2_2_0.AuxInt p5 := mem_0_2_2_2_0.Args[0] d4 := mem_0_2_2_2.Args[1] mem_0_2_2_2_2 := mem_0_2_2_2.Args[2] if mem_0_2_2_2_2.Op != OpZero { break } if mem_0_2_2_2_2.AuxInt != n { break } t6 := mem_0_2_2_2_2.Aux _ = mem_0_2_2_2_2.Args[1] p6 := mem_0_2_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && alignof(t6) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+sizeof(t2) && n >= o3+sizeof(t3) && n >= o4+sizeof(t4) && n >= o5+sizeof(t5)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = o4 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = t5 v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = o5 v6.AddArg(dst) v5.AddArg(v6) v5.AddArg(d4) v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v7.AuxInt = n v7.Aux = t1 v7.AddArg(dst) v7.AddArg(mem) v5.AddArg(v7) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [s] dst tmp1 midmem:(Move {t2} [s] tmp2 src _)) // cond: t1.(*types.Type).Compare(t2.(*types.Type)) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config)) // result: (Move {t1} [s] dst src midmem) for { s := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] tmp1 := v.Args[1] midmem := v.Args[2] if midmem.Op != OpMove { break } if midmem.AuxInt != s { break } t2 := midmem.Aux _ = midmem.Args[2] tmp2 := midmem.Args[0] src := midmem.Args[1] if !(t1.(*types.Type).Compare(t2.(*types.Type)) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) { break } v.reset(OpMove) v.AuxInt = s v.Aux = t1 v.AddArg(dst) v.AddArg(src) v.AddArg(midmem) return true } // match: (Move {t1} [s] dst tmp1 midmem:(VarDef (Move {t2} [s] tmp2 src _))) // cond: t1.(*types.Type).Compare(t2.(*types.Type)) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config)) // result: (Move {t1} [s] dst src midmem) for { s := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] tmp1 := v.Args[1] midmem := v.Args[2] if midmem.Op != OpVarDef { break } midmem_0 := midmem.Args[0] if midmem_0.Op != OpMove { break } if midmem_0.AuxInt != s { break } t2 := midmem_0.Aux _ = midmem_0.Args[2] tmp2 := midmem_0.Args[0] src := midmem_0.Args[1] if !(t1.(*types.Type).Compare(t2.(*types.Type)) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) { break } v.reset(OpMove) v.AuxInt = s v.Aux = t1 v.AddArg(dst) v.AddArg(src) v.AddArg(midmem) return true } // match: (Move dst src mem) // cond: isSamePtr(dst, src) // result: mem for { mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(isSamePtr(dst, src)) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } return false } func rewriteValuegeneric_OpMul16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mul16 (Const16 [c]) (Const16 [d])) // cond: // result: (Const16 [int64(int16(c*d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c * d)) return true } // match: (Mul16 (Const16 [d]) (Const16 [c])) // cond: // result: (Const16 [int64(int16(c*d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c * d)) return true } // match: (Mul16 (Const16 [1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul16 x (Const16 [1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul16 (Const16 [-1]) x) // cond: // result: (Neg16 x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != -1 { break } v.reset(OpNeg16) v.AddArg(x) return true } // match: (Mul16 x (Const16 [-1])) // cond: // result: (Neg16 x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != -1 { break } v.reset(OpNeg16) v.AddArg(x) return true } // match: (Mul16 n (Const16 [c])) // cond: isPowerOfTwo(c) // result: (Lsh16x64 n (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh16x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul16 (Const16 [c]) n) // cond: isPowerOfTwo(c) // result: (Lsh16x64 n (Const64 [log2(c)])) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh16x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul16 n (Const16 [c])) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg16 (Lsh16x64 n (Const64 [log2(-c)]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Mul16 (Const16 [c]) n) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg16 (Lsh16x64 n (Const64 [log2(-c)]))) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMul16_10(v *Value) bool { b := v.Block // match: (Mul16 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Mul16 _ (Const16 [0])) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Mul16 (Const16 [c]) (Mul16 (Const16 [d]) x)) // cond: // result: (Mul16 (Const16 [int64(int16(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul16 (Const16 [c]) (Mul16 x (Const16 [d]))) // cond: // result: (Mul16 (Const16 [int64(int16(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul16 (Mul16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Mul16 (Const16 [int64(int16(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul16 (Mul16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Mul16 (Const16 [int64(int16(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c * d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpMul32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mul32 (Const32 [c]) (Const32 [d])) // cond: // result: (Const32 [int64(int32(c*d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c * d)) return true } // match: (Mul32 (Const32 [d]) (Const32 [c])) // cond: // result: (Const32 [int64(int32(c*d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c * d)) return true } // match: (Mul32 (Const32 [1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul32 x (Const32 [1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul32 (Const32 [-1]) x) // cond: // result: (Neg32 x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != -1 { break } v.reset(OpNeg32) v.AddArg(x) return true } // match: (Mul32 x (Const32 [-1])) // cond: // result: (Neg32 x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != -1 { break } v.reset(OpNeg32) v.AddArg(x) return true } // match: (Mul32 n (Const32 [c])) // cond: isPowerOfTwo(c) // result: (Lsh32x64 n (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh32x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul32 (Const32 [c]) n) // cond: isPowerOfTwo(c) // result: (Lsh32x64 n (Const64 [log2(c)])) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh32x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul32 n (Const32 [c])) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg32 (Lsh32x64 n (Const64 [log2(-c)]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpLsh32x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Mul32 (Const32 [c]) n) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg32 (Lsh32x64 n (Const64 [log2(-c)]))) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpLsh32x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMul32_10(v *Value) bool { b := v.Block // match: (Mul32 (Const32 [c]) (Add32 (Const32 [d]) x)) // cond: // result: (Add32 (Const32 [int64(int32(c*d))]) (Mul32 (Const32 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } if v_1.Type != t { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul32 (Const32 [c]) (Add32 x (Const32 [d]))) // cond: // result: (Add32 (Const32 [int64(int32(c*d))]) (Mul32 (Const32 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } if v_1.Type != t { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul32 (Add32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Add32 (Const32 [int64(int32(c*d))]) (Mul32 (Const32 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } t := v_0.Type x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } if v_0_0.Type != t { break } d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul32 (Add32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Add32 (Const32 [int64(int32(c*d))]) (Mul32 (Const32 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } t := v_0.Type _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } if v_0_1.Type != t { break } d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul32 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Mul32 _ (Const32 [0])) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Mul32 (Const32 [c]) (Mul32 (Const32 [d]) x)) // cond: // result: (Mul32 (Const32 [int64(int32(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul32 (Const32 [c]) (Mul32 x (Const32 [d]))) // cond: // result: (Mul32 (Const32 [int64(int32(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul32 (Mul32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Mul32 (Const32 [int64(int32(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul32 (Mul32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Mul32 (Const32 [int64(int32(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpMul32F_0(v *Value) bool { // match: (Mul32F (Const32F [c]) (Const32F [d])) // cond: // result: (Const32F [auxFrom32F(auxTo32F(c) * auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(auxTo32F(c) * auxTo32F(d)) return true } // match: (Mul32F (Const32F [d]) (Const32F [c])) // cond: // result: (Const32F [auxFrom32F(auxTo32F(c) * auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } c := v_1.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(auxTo32F(c) * auxTo32F(d)) return true } // match: (Mul32F x (Const32F [auxFrom64F(1)])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32F { break } if v_1.AuxInt != auxFrom64F(1) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul32F (Const32F [auxFrom64F(1)]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } if v_0.AuxInt != auxFrom64F(1) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul32F x (Const32F [auxFrom32F(-1)])) // cond: // result: (Neg32F x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32F { break } if v_1.AuxInt != auxFrom32F(-1) { break } v.reset(OpNeg32F) v.AddArg(x) return true } // match: (Mul32F (Const32F [auxFrom32F(-1)]) x) // cond: // result: (Neg32F x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } if v_0.AuxInt != auxFrom32F(-1) { break } v.reset(OpNeg32F) v.AddArg(x) return true } // match: (Mul32F x (Const32F [auxFrom32F(2)])) // cond: // result: (Add32F x x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32F { break } if v_1.AuxInt != auxFrom32F(2) { break } v.reset(OpAdd32F) v.AddArg(x) v.AddArg(x) return true } // match: (Mul32F (Const32F [auxFrom32F(2)]) x) // cond: // result: (Add32F x x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } if v_0.AuxInt != auxFrom32F(2) { break } v.reset(OpAdd32F) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpMul64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mul64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c*d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c * d return true } // match: (Mul64 (Const64 [d]) (Const64 [c])) // cond: // result: (Const64 [c*d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c * d return true } // match: (Mul64 (Const64 [1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul64 x (Const64 [1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul64 (Const64 [-1]) x) // cond: // result: (Neg64 x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != -1 { break } v.reset(OpNeg64) v.AddArg(x) return true } // match: (Mul64 x (Const64 [-1])) // cond: // result: (Neg64 x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1 { break } v.reset(OpNeg64) v.AddArg(x) return true } // match: (Mul64 n (Const64 [c])) // cond: isPowerOfTwo(c) // result: (Lsh64x64 n (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh64x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul64 (Const64 [c]) n) // cond: isPowerOfTwo(c) // result: (Lsh64x64 n (Const64 [log2(c)])) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh64x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul64 n (Const64 [c])) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg64 (Lsh64x64 n (Const64 [log2(-c)]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpLsh64x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Mul64 (Const64 [c]) n) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg64 (Lsh64x64 n (Const64 [log2(-c)]))) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpLsh64x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMul64_10(v *Value) bool { b := v.Block // match: (Mul64 (Const64 [c]) (Add64 (Const64 [d]) x)) // cond: // result: (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } if v_1.Type != t { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul64 (Const64 [c]) (Add64 x (Const64 [d]))) // cond: // result: (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } if v_1.Type != t { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul64 (Add64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } t := v_0.Type x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } if v_0_0.Type != t { break } d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul64 (Add64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } t := v_0.Type _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != t { break } d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul64 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Mul64 _ (Const64 [0])) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Mul64 (Const64 [c]) (Mul64 (Const64 [d]) x)) // cond: // result: (Mul64 (Const64 [c*d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v.AddArg(x) return true } // match: (Mul64 (Const64 [c]) (Mul64 x (Const64 [d]))) // cond: // result: (Mul64 (Const64 [c*d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v.AddArg(x) return true } // match: (Mul64 (Mul64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Mul64 (Const64 [c*d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v.AddArg(x) return true } // match: (Mul64 (Mul64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Mul64 (Const64 [c*d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpMul64F_0(v *Value) bool { // match: (Mul64F (Const64F [c]) (Const64F [d])) // cond: // result: (Const64F [auxFrom64F(auxTo64F(c) * auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(auxTo64F(c) * auxTo64F(d)) return true } // match: (Mul64F (Const64F [d]) (Const64F [c])) // cond: // result: (Const64F [auxFrom64F(auxTo64F(c) * auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } c := v_1.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(auxTo64F(c) * auxTo64F(d)) return true } // match: (Mul64F x (Const64F [auxFrom64F(1)])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64F { break } if v_1.AuxInt != auxFrom64F(1) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul64F (Const64F [auxFrom64F(1)]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } if v_0.AuxInt != auxFrom64F(1) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul64F x (Const64F [auxFrom64F(-1)])) // cond: // result: (Neg64F x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64F { break } if v_1.AuxInt != auxFrom64F(-1) { break } v.reset(OpNeg64F) v.AddArg(x) return true } // match: (Mul64F (Const64F [auxFrom64F(-1)]) x) // cond: // result: (Neg64F x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } if v_0.AuxInt != auxFrom64F(-1) { break } v.reset(OpNeg64F) v.AddArg(x) return true } // match: (Mul64F x (Const64F [auxFrom64F(2)])) // cond: // result: (Add64F x x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64F { break } if v_1.AuxInt != auxFrom64F(2) { break } v.reset(OpAdd64F) v.AddArg(x) v.AddArg(x) return true } // match: (Mul64F (Const64F [auxFrom64F(2)]) x) // cond: // result: (Add64F x x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } if v_0.AuxInt != auxFrom64F(2) { break } v.reset(OpAdd64F) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpMul8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mul8 (Const8 [c]) (Const8 [d])) // cond: // result: (Const8 [int64(int8(c*d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c * d)) return true } // match: (Mul8 (Const8 [d]) (Const8 [c])) // cond: // result: (Const8 [int64(int8(c*d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c * d)) return true } // match: (Mul8 (Const8 [1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul8 x (Const8 [1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul8 (Const8 [-1]) x) // cond: // result: (Neg8 x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != -1 { break } v.reset(OpNeg8) v.AddArg(x) return true } // match: (Mul8 x (Const8 [-1])) // cond: // result: (Neg8 x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != -1 { break } v.reset(OpNeg8) v.AddArg(x) return true } // match: (Mul8 n (Const8 [c])) // cond: isPowerOfTwo(c) // result: (Lsh8x64 n (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh8x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul8 (Const8 [c]) n) // cond: isPowerOfTwo(c) // result: (Lsh8x64 n (Const64 [log2(c)])) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh8x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul8 n (Const8 [c])) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg8 (Lsh8x64 n (Const64 [log2(-c)]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Mul8 (Const8 [c]) n) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg8 (Lsh8x64 n (Const64 [log2(-c)]))) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMul8_10(v *Value) bool { b := v.Block // match: (Mul8 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Mul8 _ (Const8 [0])) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Mul8 (Const8 [c]) (Mul8 (Const8 [d]) x)) // cond: // result: (Mul8 (Const8 [int64(int8(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul8 (Const8 [c]) (Mul8 x (Const8 [d]))) // cond: // result: (Mul8 (Const8 [int64(int8(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul8 (Mul8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Mul8 (Const8 [int64(int8(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul8 (Mul8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Mul8 (Const8 [int64(int8(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c * d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpNeg16_0(v *Value) bool { // match: (Neg16 (Const16 [c])) // cond: // result: (Const16 [int64(-int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst16) v.AuxInt = int64(-int16(c)) return true } // match: (Neg16 (Sub16 x y)) // cond: // result: (Sub16 y x) for { v_0 := v.Args[0] if v_0.Op != OpSub16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub16) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpNeg32_0(v *Value) bool { // match: (Neg32 (Const32 [c])) // cond: // result: (Const32 [int64(-int32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(-int32(c)) return true } // match: (Neg32 (Sub32 x y)) // cond: // result: (Sub32 y x) for { v_0 := v.Args[0] if v_0.Op != OpSub32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub32) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpNeg32F_0(v *Value) bool { // match: (Neg32F (Const32F [c])) // cond: auxTo32F(c) != 0 // result: (Const32F [auxFrom32F(-auxTo32F(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt if !(auxTo32F(c) != 0) { break } v.reset(OpConst32F) v.AuxInt = auxFrom32F(-auxTo32F(c)) return true } return false } func rewriteValuegeneric_OpNeg64_0(v *Value) bool { // match: (Neg64 (Const64 [c])) // cond: // result: (Const64 [-c]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = -c return true } // match: (Neg64 (Sub64 x y)) // cond: // result: (Sub64 y x) for { v_0 := v.Args[0] if v_0.Op != OpSub64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub64) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpNeg64F_0(v *Value) bool { // match: (Neg64F (Const64F [c])) // cond: auxTo64F(c) != 0 // result: (Const64F [auxFrom64F(-auxTo64F(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt if !(auxTo64F(c) != 0) { break } v.reset(OpConst64F) v.AuxInt = auxFrom64F(-auxTo64F(c)) return true } return false } func rewriteValuegeneric_OpNeg8_0(v *Value) bool { // match: (Neg8 (Const8 [c])) // cond: // result: (Const8 [int64( -int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst8) v.AuxInt = int64(-int8(c)) return true } // match: (Neg8 (Sub8 x y)) // cond: // result: (Sub8 y x) for { v_0 := v.Args[0] if v_0.Op != OpSub8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub8) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpNeq16_0(v *Value) bool { b := v.Block // match: (Neq16 x x) // cond: // result: (ConstBool [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (Neq16 (Const16 [c]) (Add16 (Const16 [d]) x)) // cond: // result: (Neq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq16 (Const16 [c]) (Add16 x (Const16 [d]))) // cond: // result: (Neq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq16 (Add16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Neq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq16 (Add16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Neq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq16 (Const16 [c]) (Const16 [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq16 (Const16 [d]) (Const16 [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq16 s:(Sub16 x y) (Const16 [0])) // cond: s.Uses == 1 // result: (Neq16 x y) for { _ = v.Args[1] s := v.Args[0] if s.Op != OpSub16 { break } y := s.Args[1] x := s.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } if !(s.Uses == 1) { break } v.reset(OpNeq16) v.AddArg(x) v.AddArg(y) return true } // match: (Neq16 (Const16 [0]) s:(Sub16 x y)) // cond: s.Uses == 1 // result: (Neq16 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } s := v.Args[1] if s.Op != OpSub16 { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpNeq16) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNeq32_0(v *Value) bool { b := v.Block // match: (Neq32 x x) // cond: // result: (ConstBool [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (Neq32 (Const32 [c]) (Add32 (Const32 [d]) x)) // cond: // result: (Neq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq32 (Const32 [c]) (Add32 x (Const32 [d]))) // cond: // result: (Neq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq32 (Add32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Neq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq32 (Add32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Neq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq32 (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq32 (Const32 [d]) (Const32 [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq32 s:(Sub32 x y) (Const32 [0])) // cond: s.Uses == 1 // result: (Neq32 x y) for { _ = v.Args[1] s := v.Args[0] if s.Op != OpSub32 { break } y := s.Args[1] x := s.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } if !(s.Uses == 1) { break } v.reset(OpNeq32) v.AddArg(x) v.AddArg(y) return true } // match: (Neq32 (Const32 [0]) s:(Sub32 x y)) // cond: s.Uses == 1 // result: (Neq32 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } s := v.Args[1] if s.Op != OpSub32 { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpNeq32) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNeq32F_0(v *Value) bool { // match: (Neq32F (Const32F [c]) (Const32F [d])) // cond: // result: (ConstBool [b2i(auxTo32F(c) != auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo32F(c) != auxTo32F(d)) return true } // match: (Neq32F (Const32F [d]) (Const32F [c])) // cond: // result: (ConstBool [b2i(auxTo32F(c) != auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo32F(c) != auxTo32F(d)) return true } return false } func rewriteValuegeneric_OpNeq64_0(v *Value) bool { b := v.Block // match: (Neq64 x x) // cond: // result: (ConstBool [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (Neq64 (Const64 [c]) (Add64 (Const64 [d]) x)) // cond: // result: (Neq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Neq64 (Const64 [c]) (Add64 x (Const64 [d]))) // cond: // result: (Neq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Neq64 (Add64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Neq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Neq64 (Add64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Neq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Neq64 (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq64 (Const64 [d]) (Const64 [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq64 s:(Sub64 x y) (Const64 [0])) // cond: s.Uses == 1 // result: (Neq64 x y) for { _ = v.Args[1] s := v.Args[0] if s.Op != OpSub64 { break } y := s.Args[1] x := s.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } if !(s.Uses == 1) { break } v.reset(OpNeq64) v.AddArg(x) v.AddArg(y) return true } // match: (Neq64 (Const64 [0]) s:(Sub64 x y)) // cond: s.Uses == 1 // result: (Neq64 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } s := v.Args[1] if s.Op != OpSub64 { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpNeq64) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNeq64F_0(v *Value) bool { // match: (Neq64F (Const64F [c]) (Const64F [d])) // cond: // result: (ConstBool [b2i(auxTo64F(c) != auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo64F(c) != auxTo64F(d)) return true } // match: (Neq64F (Const64F [d]) (Const64F [c])) // cond: // result: (ConstBool [b2i(auxTo64F(c) != auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo64F(c) != auxTo64F(d)) return true } return false } func rewriteValuegeneric_OpNeq8_0(v *Value) bool { b := v.Block // match: (Neq8 x x) // cond: // result: (ConstBool [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (Neq8 (Const8 [c]) (Add8 (Const8 [d]) x)) // cond: // result: (Neq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq8 (Const8 [c]) (Add8 x (Const8 [d]))) // cond: // result: (Neq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq8 (Add8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Neq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq8 (Add8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Neq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq8 (Const8 [c]) (Const8 [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq8 (Const8 [d]) (Const8 [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq8 s:(Sub8 x y) (Const8 [0])) // cond: s.Uses == 1 // result: (Neq8 x y) for { _ = v.Args[1] s := v.Args[0] if s.Op != OpSub8 { break } y := s.Args[1] x := s.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } if !(s.Uses == 1) { break } v.reset(OpNeq8) v.AddArg(x) v.AddArg(y) return true } // match: (Neq8 (Const8 [0]) s:(Sub8 x y)) // cond: s.Uses == 1 // result: (Neq8 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } s := v.Args[1] if s.Op != OpSub8 { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpNeq8) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNeqB_0(v *Value) bool { // match: (NeqB (ConstBool [c]) (ConstBool [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConstBool { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConstBool { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (NeqB (ConstBool [d]) (ConstBool [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConstBool { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConstBool { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (NeqB (ConstBool [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConstBool { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (NeqB x (ConstBool [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConstBool { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (NeqB (ConstBool [1]) x) // cond: // result: (Not x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConstBool { break } if v_0.AuxInt != 1 { break } v.reset(OpNot) v.AddArg(x) return true } // match: (NeqB x (ConstBool [1])) // cond: // result: (Not x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConstBool { break } if v_1.AuxInt != 1 { break } v.reset(OpNot) v.AddArg(x) return true } // match: (NeqB (Not x) (Not y)) // cond: // result: (NeqB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpNot { break } x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpNot { break } y := v_1.Args[0] v.reset(OpNeqB) v.AddArg(x) v.AddArg(y) return true } // match: (NeqB (Not y) (Not x)) // cond: // result: (NeqB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpNot { break } y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpNot { break } x := v_1.Args[0] v.reset(OpNeqB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNeqInter_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (NeqInter x y) // cond: // result: (NeqPtr (ITab x) (ITab y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpNeqPtr) v0 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuegeneric_OpNeqPtr_0(v *Value) bool { // match: (NeqPtr x x) // cond: // result: (ConstBool [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (NeqPtr (Addr {a} _) (Addr {b} _)) // cond: // result: (ConstBool [b2i(a != b)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAddr { break } a := v_0.Aux v_1 := v.Args[1] if v_1.Op != OpAddr { break } b := v_1.Aux v.reset(OpConstBool) v.AuxInt = b2i(a != b) return true } // match: (NeqPtr (Addr {b} _) (Addr {a} _)) // cond: // result: (ConstBool [b2i(a != b)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAddr { break } b := v_0.Aux v_1 := v.Args[1] if v_1.Op != OpAddr { break } a := v_1.Aux v.reset(OpConstBool) v.AuxInt = b2i(a != b) return true } // match: (NeqPtr (LocalAddr {a} _ _) (LocalAddr {b} _ _)) // cond: // result: (ConstBool [b2i(a != b)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLocalAddr { break } a := v_0.Aux _ = v_0.Args[1] v_1 := v.Args[1] if v_1.Op != OpLocalAddr { break } b := v_1.Aux _ = v_1.Args[1] v.reset(OpConstBool) v.AuxInt = b2i(a != b) return true } // match: (NeqPtr (LocalAddr {b} _ _) (LocalAddr {a} _ _)) // cond: // result: (ConstBool [b2i(a != b)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLocalAddr { break } b := v_0.Aux _ = v_0.Args[1] v_1 := v.Args[1] if v_1.Op != OpLocalAddr { break } a := v_1.Aux _ = v_1.Args[1] v.reset(OpConstBool) v.AuxInt = b2i(a != b) return true } // match: (NeqPtr (OffPtr [o1] p1) p2) // cond: isSamePtr(p1, p2) // result: (ConstBool [b2i(o1 != 0)]) for { p2 := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o1 := v_0.AuxInt p1 := v_0.Args[0] if !(isSamePtr(p1, p2)) { break } v.reset(OpConstBool) v.AuxInt = b2i(o1 != 0) return true } // match: (NeqPtr p2 (OffPtr [o1] p1)) // cond: isSamePtr(p1, p2) // result: (ConstBool [b2i(o1 != 0)]) for { _ = v.Args[1] p2 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOffPtr { break } o1 := v_1.AuxInt p1 := v_1.Args[0] if !(isSamePtr(p1, p2)) { break } v.reset(OpConstBool) v.AuxInt = b2i(o1 != 0) return true } // match: (NeqPtr (OffPtr [o1] p1) (OffPtr [o2] p2)) // cond: isSamePtr(p1, p2) // result: (ConstBool [b2i(o1 != o2)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o1 := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpOffPtr { break } o2 := v_1.AuxInt p2 := v_1.Args[0] if !(isSamePtr(p1, p2)) { break } v.reset(OpConstBool) v.AuxInt = b2i(o1 != o2) return true } // match: (NeqPtr (OffPtr [o2] p2) (OffPtr [o1] p1)) // cond: isSamePtr(p1, p2) // result: (ConstBool [b2i(o1 != o2)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o2 := v_0.AuxInt p2 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpOffPtr { break } o1 := v_1.AuxInt p1 := v_1.Args[0] if !(isSamePtr(p1, p2)) { break } v.reset(OpConstBool) v.AuxInt = b2i(o1 != o2) return true } // match: (NeqPtr (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } return false } func rewriteValuegeneric_OpNeqPtr_10(v *Value) bool { // match: (NeqPtr (Const32 [d]) (Const32 [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (NeqPtr (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (NeqPtr (Const64 [d]) (Const64 [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (NeqPtr (LocalAddr _ _) (Addr _)) // cond: // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLocalAddr { break } _ = v_0.Args[1] v_1 := v.Args[1] if v_1.Op != OpAddr { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (NeqPtr (Addr _) (LocalAddr _ _)) // cond: // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAddr { break } v_1 := v.Args[1] if v_1.Op != OpLocalAddr { break } _ = v_1.Args[1] v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (NeqPtr (Addr _) (LocalAddr _ _)) // cond: // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAddr { break } v_1 := v.Args[1] if v_1.Op != OpLocalAddr { break } _ = v_1.Args[1] v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (NeqPtr (LocalAddr _ _) (Addr _)) // cond: // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLocalAddr { break } _ = v_0.Args[1] v_1 := v.Args[1] if v_1.Op != OpAddr { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (NeqPtr (AddPtr p1 o1) p2) // cond: isSamePtr(p1, p2) // result: (IsNonNil o1) for { p2 := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAddPtr { break } o1 := v_0.Args[1] p1 := v_0.Args[0] if !(isSamePtr(p1, p2)) { break } v.reset(OpIsNonNil) v.AddArg(o1) return true } // match: (NeqPtr p2 (AddPtr p1 o1)) // cond: isSamePtr(p1, p2) // result: (IsNonNil o1) for { _ = v.Args[1] p2 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddPtr { break } o1 := v_1.Args[1] p1 := v_1.Args[0] if !(isSamePtr(p1, p2)) { break } v.reset(OpIsNonNil) v.AddArg(o1) return true } // match: (NeqPtr (Const32 [0]) p) // cond: // result: (IsNonNil p) for { p := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpIsNonNil) v.AddArg(p) return true } return false } func rewriteValuegeneric_OpNeqPtr_20(v *Value) bool { // match: (NeqPtr p (Const32 [0])) // cond: // result: (IsNonNil p) for { _ = v.Args[1] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } v.reset(OpIsNonNil) v.AddArg(p) return true } // match: (NeqPtr (Const64 [0]) p) // cond: // result: (IsNonNil p) for { p := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpIsNonNil) v.AddArg(p) return true } // match: (NeqPtr p (Const64 [0])) // cond: // result: (IsNonNil p) for { _ = v.Args[1] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpIsNonNil) v.AddArg(p) return true } // match: (NeqPtr (ConstNil) p) // cond: // result: (IsNonNil p) for { p := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConstNil { break } v.reset(OpIsNonNil) v.AddArg(p) return true } // match: (NeqPtr p (ConstNil)) // cond: // result: (IsNonNil p) for { _ = v.Args[1] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConstNil { break } v.reset(OpIsNonNil) v.AddArg(p) return true } return false } func rewriteValuegeneric_OpNeqSlice_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (NeqSlice x y) // cond: // result: (NeqPtr (SlicePtr x) (SlicePtr y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpNeqPtr) v0 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuegeneric_OpNilCheck_0(v *Value) bool { b := v.Block config := b.Func.Config fe := b.Func.fe // match: (NilCheck (GetG mem) mem) // cond: // result: mem for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpGetG { break } if mem != v_0.Args[0] { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (NilCheck (Load (OffPtr [c] (SP)) (StaticCall {sym} _)) _) // cond: isSameSym(sym, "runtime.newobject") && c == config.ctxt.FixedFrameSize() + config.RegSize && warnRule(fe.Debug_checknil(), v, "removed nil check") // result: (Invalid) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLoad { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpOffPtr { break } c := v_0_0.AuxInt v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpSP { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpStaticCall { break } sym := v_0_1.Aux if !(isSameSym(sym, "runtime.newobject") && c == config.ctxt.FixedFrameSize()+config.RegSize && warnRule(fe.Debug_checknil(), v, "removed nil check")) { break } v.reset(OpInvalid) return true } // match: (NilCheck (OffPtr (Load (OffPtr [c] (SP)) (StaticCall {sym} _))) _) // cond: isSameSym(sym, "runtime.newobject") && c == config.ctxt.FixedFrameSize() + config.RegSize && warnRule(fe.Debug_checknil(), v, "removed nil check") // result: (Invalid) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLoad { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpOffPtr { break } c := v_0_0_0.AuxInt v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpSP { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpStaticCall { break } sym := v_0_0_1.Aux if !(isSameSym(sym, "runtime.newobject") && c == config.ctxt.FixedFrameSize()+config.RegSize && warnRule(fe.Debug_checknil(), v, "removed nil check")) { break } v.reset(OpInvalid) return true } return false } func rewriteValuegeneric_OpNot_0(v *Value) bool { // match: (Not (ConstBool [c])) // cond: // result: (ConstBool [1-c]) for { v_0 := v.Args[0] if v_0.Op != OpConstBool { break } c := v_0.AuxInt v.reset(OpConstBool) v.AuxInt = 1 - c return true } // match: (Not (Eq64 x y)) // cond: // result: (Neq64 x y) for { v_0 := v.Args[0] if v_0.Op != OpEq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq64) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Eq32 x y)) // cond: // result: (Neq32 x y) for { v_0 := v.Args[0] if v_0.Op != OpEq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq32) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Eq16 x y)) // cond: // result: (Neq16 x y) for { v_0 := v.Args[0] if v_0.Op != OpEq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq16) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Eq8 x y)) // cond: // result: (Neq8 x y) for { v_0 := v.Args[0] if v_0.Op != OpEq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq8) v.AddArg(x) v.AddArg(y) return true } // match: (Not (EqB x y)) // cond: // result: (NeqB x y) for { v_0 := v.Args[0] if v_0.Op != OpEqB { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeqB) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Neq64 x y)) // cond: // result: (Eq64 x y) for { v_0 := v.Args[0] if v_0.Op != OpNeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq64) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Neq32 x y)) // cond: // result: (Eq32 x y) for { v_0 := v.Args[0] if v_0.Op != OpNeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq32) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Neq16 x y)) // cond: // result: (Eq16 x y) for { v_0 := v.Args[0] if v_0.Op != OpNeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq16) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Neq8 x y)) // cond: // result: (Eq8 x y) for { v_0 := v.Args[0] if v_0.Op != OpNeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq8) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNot_10(v *Value) bool { // match: (Not (NeqB x y)) // cond: // result: (EqB x y) for { v_0 := v.Args[0] if v_0.Op != OpNeqB { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEqB) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater64 x y)) // cond: // result: (Leq64 x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq64) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater32 x y)) // cond: // result: (Leq32 x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq32) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater16 x y)) // cond: // result: (Leq16 x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq16) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater8 x y)) // cond: // result: (Leq8 x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq8) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater64U x y)) // cond: // result: (Leq64U x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq64U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater32U x y)) // cond: // result: (Leq32U x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq32U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater16U x y)) // cond: // result: (Leq16U x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq16U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater8U x y)) // cond: // result: (Leq8U x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq8U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq64 x y)) // cond: // result: (Less64 x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess64) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNot_20(v *Value) bool { // match: (Not (Geq32 x y)) // cond: // result: (Less32 x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess32) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq16 x y)) // cond: // result: (Less16 x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess16) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq8 x y)) // cond: // result: (Less8 x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess8) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq64U x y)) // cond: // result: (Less64U x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess64U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq32U x y)) // cond: // result: (Less32U x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess32U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq16U x y)) // cond: // result: (Less16U x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess16U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq8U x y)) // cond: // result: (Less8U x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess8U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less64 x y)) // cond: // result: (Geq64 x y) for { v_0 := v.Args[0] if v_0.Op != OpLess64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq64) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less32 x y)) // cond: // result: (Geq32 x y) for { v_0 := v.Args[0] if v_0.Op != OpLess32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq32) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less16 x y)) // cond: // result: (Geq16 x y) for { v_0 := v.Args[0] if v_0.Op != OpLess16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq16) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNot_30(v *Value) bool { // match: (Not (Less8 x y)) // cond: // result: (Geq8 x y) for { v_0 := v.Args[0] if v_0.Op != OpLess8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq8) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less64U x y)) // cond: // result: (Geq64U x y) for { v_0 := v.Args[0] if v_0.Op != OpLess64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq64U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less32U x y)) // cond: // result: (Geq32U x y) for { v_0 := v.Args[0] if v_0.Op != OpLess32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq32U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less16U x y)) // cond: // result: (Geq16U x y) for { v_0 := v.Args[0] if v_0.Op != OpLess16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq16U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less8U x y)) // cond: // result: (Geq8U x y) for { v_0 := v.Args[0] if v_0.Op != OpLess8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq8U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq64 x y)) // cond: // result: (Greater64 x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater64) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq32 x y)) // cond: // result: (Greater32 x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater32) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq16 x y)) // cond: // result: (Greater16 x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater16) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq8 x y)) // cond: // result: (Greater8 x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater8) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq64U x y)) // cond: // result: (Greater64U x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater64U) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNot_40(v *Value) bool { // match: (Not (Leq32U x y)) // cond: // result: (Greater32U x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater32U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq16U x y)) // cond: // result: (Greater16U x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater16U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq8U x y)) // cond: // result: (Greater8U x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater8U) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpOffPtr_0(v *Value) bool { // match: (OffPtr (OffPtr p [b]) [a]) // cond: // result: (OffPtr p [a+b]) for { a := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } b := v_0.AuxInt p := v_0.Args[0] v.reset(OpOffPtr) v.AuxInt = a + b v.AddArg(p) return true } // match: (OffPtr p [0]) // cond: v.Type.Compare(p.Type) == types.CMPeq // result: p for { if v.AuxInt != 0 { break } p := v.Args[0] if !(v.Type.Compare(p.Type) == types.CMPeq) { break } v.reset(OpCopy) v.Type = p.Type v.AddArg(p) return true } return false } func rewriteValuegeneric_OpOr16_0(v *Value) bool { // match: (Or16 (Const16 [c]) (Const16 [d])) // cond: // result: (Const16 [int64(int16(c|d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c | d)) return true } // match: (Or16 (Const16 [d]) (Const16 [c])) // cond: // result: (Const16 [int64(int16(c|d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c | d)) return true } // match: (Or16 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or16 (Const16 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or16 x (Const16 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or16 (Const16 [-1]) _) // cond: // result: (Const16 [-1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != -1 { break } v.reset(OpConst16) v.AuxInt = -1 return true } // match: (Or16 _ (Const16 [-1])) // cond: // result: (Const16 [-1]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != -1 { break } v.reset(OpConst16) v.AuxInt = -1 return true } // match: (Or16 x (Or16 x y)) // cond: // result: (Or16 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr16 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpOr16) v.AddArg(x) v.AddArg(y) return true } // match: (Or16 x (Or16 y x)) // cond: // result: (Or16 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr16 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpOr16) v.AddArg(x) v.AddArg(y) return true } // match: (Or16 (Or16 x y) x) // cond: // result: (Or16 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr16 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpOr16) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpOr16_10(v *Value) bool { b := v.Block // match: (Or16 (Or16 y x) x) // cond: // result: (Or16 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr16 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpOr16) v.AddArg(x) v.AddArg(y) return true } // match: (Or16 (And16 x (Const16 [c2])) (Const16 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or16 (Const16 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or16 (And16 (Const16 [c2]) x) (Const16 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or16 (Const16 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c2 := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or16 (Const16 [c1]) (And16 x (Const16 [c2]))) // cond: ^(c1 | c2) == 0 // result: (Or16 (Const16 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c2 := v_1_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or16 (Const16 [c1]) (And16 (Const16 [c2]) x)) // cond: ^(c1 | c2) == 0 // result: (Or16 (Const16 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c2 := v_1_0.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or16 (Or16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Or16 i (Or16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpOr16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or16 (Or16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Or16 i (Or16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr16 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpOr16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or16 x (Or16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Or16 i (Or16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpOr16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or16 x (Or16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Or16 i (Or16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpOr16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or16 (Const16 [c]) (Or16 (Const16 [d]) x)) // cond: // result: (Or16 (Const16 [int64(int16(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c | d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr16_20(v *Value) bool { b := v.Block // match: (Or16 (Const16 [c]) (Or16 x (Const16 [d]))) // cond: // result: (Or16 (Const16 [int64(int16(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c | d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Or16 (Or16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Or16 (Const16 [int64(int16(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c | d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Or16 (Or16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Or16 (Const16 [int64(int16(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c | d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr32_0(v *Value) bool { // match: (Or32 (Const32 [c]) (Const32 [d])) // cond: // result: (Const32 [int64(int32(c|d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c | d)) return true } // match: (Or32 (Const32 [d]) (Const32 [c])) // cond: // result: (Const32 [int64(int32(c|d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c | d)) return true } // match: (Or32 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or32 (Const32 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or32 x (Const32 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or32 (Const32 [-1]) _) // cond: // result: (Const32 [-1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != -1 { break } v.reset(OpConst32) v.AuxInt = -1 return true } // match: (Or32 _ (Const32 [-1])) // cond: // result: (Const32 [-1]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != -1 { break } v.reset(OpConst32) v.AuxInt = -1 return true } // match: (Or32 x (Or32 x y)) // cond: // result: (Or32 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr32 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpOr32) v.AddArg(x) v.AddArg(y) return true } // match: (Or32 x (Or32 y x)) // cond: // result: (Or32 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr32 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpOr32) v.AddArg(x) v.AddArg(y) return true } // match: (Or32 (Or32 x y) x) // cond: // result: (Or32 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr32 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpOr32) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpOr32_10(v *Value) bool { b := v.Block // match: (Or32 (Or32 y x) x) // cond: // result: (Or32 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr32 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpOr32) v.AddArg(x) v.AddArg(y) return true } // match: (Or32 (And32 x (Const32 [c2])) (Const32 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or32 (Const32 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or32 (And32 (Const32 [c2]) x) (Const32 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or32 (Const32 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c2 := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or32 (Const32 [c1]) (And32 x (Const32 [c2]))) // cond: ^(c1 | c2) == 0 // result: (Or32 (Const32 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c2 := v_1_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or32 (Const32 [c1]) (And32 (Const32 [c2]) x)) // cond: ^(c1 | c2) == 0 // result: (Or32 (Const32 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c2 := v_1_0.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or32 (Or32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Or32 i (Or32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpOr32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or32 (Or32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Or32 i (Or32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr32 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpOr32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or32 x (Or32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Or32 i (Or32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpOr32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or32 x (Or32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Or32 i (Or32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpOr32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or32 (Const32 [c]) (Or32 (Const32 [d]) x)) // cond: // result: (Or32 (Const32 [int64(int32(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c | d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr32_20(v *Value) bool { b := v.Block // match: (Or32 (Const32 [c]) (Or32 x (Const32 [d]))) // cond: // result: (Or32 (Const32 [int64(int32(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c | d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Or32 (Or32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Or32 (Const32 [int64(int32(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c | d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Or32 (Or32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Or32 (Const32 [int64(int32(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c | d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr64_0(v *Value) bool { // match: (Or64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c|d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c | d return true } // match: (Or64 (Const64 [d]) (Const64 [c])) // cond: // result: (Const64 [c|d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c | d return true } // match: (Or64 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or64 (Const64 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or64 (Const64 [-1]) _) // cond: // result: (Const64 [-1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != -1 { break } v.reset(OpConst64) v.AuxInt = -1 return true } // match: (Or64 _ (Const64 [-1])) // cond: // result: (Const64 [-1]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1 { break } v.reset(OpConst64) v.AuxInt = -1 return true } // match: (Or64 x (Or64 x y)) // cond: // result: (Or64 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr64 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpOr64) v.AddArg(x) v.AddArg(y) return true } // match: (Or64 x (Or64 y x)) // cond: // result: (Or64 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr64 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpOr64) v.AddArg(x) v.AddArg(y) return true } // match: (Or64 (Or64 x y) x) // cond: // result: (Or64 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr64 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpOr64) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpOr64_10(v *Value) bool { b := v.Block // match: (Or64 (Or64 y x) x) // cond: // result: (Or64 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr64 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpOr64) v.AddArg(x) v.AddArg(y) return true } // match: (Or64 (And64 x (Const64 [c2])) (Const64 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or64 (Const64 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or64 (And64 (Const64 [c2]) x) (Const64 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or64 (Const64 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c2 := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or64 (Const64 [c1]) (And64 x (Const64 [c2]))) // cond: ^(c1 | c2) == 0 // result: (Or64 (Const64 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c2 := v_1_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or64 (Const64 [c1]) (And64 (Const64 [c2]) x)) // cond: ^(c1 | c2) == 0 // result: (Or64 (Const64 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c2 := v_1_0.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or64 (Or64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Or64 i (Or64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpOr64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or64 (Or64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Or64 i (Or64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr64 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpOr64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or64 x (Or64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Or64 i (Or64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpOr64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or64 x (Or64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Or64 i (Or64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpOr64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or64 (Const64 [c]) (Or64 (Const64 [d]) x)) // cond: // result: (Or64 (Const64 [c|d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c | d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr64_20(v *Value) bool { b := v.Block // match: (Or64 (Const64 [c]) (Or64 x (Const64 [d]))) // cond: // result: (Or64 (Const64 [c|d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c | d v.AddArg(v0) v.AddArg(x) return true } // match: (Or64 (Or64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Or64 (Const64 [c|d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c | d v.AddArg(v0) v.AddArg(x) return true } // match: (Or64 (Or64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Or64 (Const64 [c|d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c | d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr8_0(v *Value) bool { // match: (Or8 (Const8 [c]) (Const8 [d])) // cond: // result: (Const8 [int64(int8(c|d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c | d)) return true } // match: (Or8 (Const8 [d]) (Const8 [c])) // cond: // result: (Const8 [int64(int8(c|d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c | d)) return true } // match: (Or8 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or8 (Const8 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or8 x (Const8 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or8 (Const8 [-1]) _) // cond: // result: (Const8 [-1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != -1 { break } v.reset(OpConst8) v.AuxInt = -1 return true } // match: (Or8 _ (Const8 [-1])) // cond: // result: (Const8 [-1]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != -1 { break } v.reset(OpConst8) v.AuxInt = -1 return true } // match: (Or8 x (Or8 x y)) // cond: // result: (Or8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr8 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpOr8) v.AddArg(x) v.AddArg(y) return true } // match: (Or8 x (Or8 y x)) // cond: // result: (Or8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr8 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpOr8) v.AddArg(x) v.AddArg(y) return true } // match: (Or8 (Or8 x y) x) // cond: // result: (Or8 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr8 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpOr8) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpOr8_10(v *Value) bool { b := v.Block // match: (Or8 (Or8 y x) x) // cond: // result: (Or8 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr8 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpOr8) v.AddArg(x) v.AddArg(y) return true } // match: (Or8 (And8 x (Const8 [c2])) (Const8 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or8 (Const8 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or8 (And8 (Const8 [c2]) x) (Const8 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or8 (Const8 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } c2 := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or8 (Const8 [c1]) (And8 x (Const8 [c2]))) // cond: ^(c1 | c2) == 0 // result: (Or8 (Const8 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } c2 := v_1_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or8 (Const8 [c1]) (And8 (Const8 [c2]) x)) // cond: ^(c1 | c2) == 0 // result: (Or8 (Const8 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c2 := v_1_0.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or8 (Or8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Or8 i (Or8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpOr8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or8 (Or8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Or8 i (Or8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr8 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpOr8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or8 x (Or8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Or8 i (Or8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpOr8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or8 x (Or8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Or8 i (Or8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpOr8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or8 (Const8 [c]) (Or8 (Const8 [d]) x)) // cond: // result: (Or8 (Const8 [int64(int8(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c | d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr8_20(v *Value) bool { b := v.Block // match: (Or8 (Const8 [c]) (Or8 x (Const8 [d]))) // cond: // result: (Or8 (Const8 [int64(int8(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c | d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Or8 (Or8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Or8 (Const8 [int64(int8(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c | d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Or8 (Or8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Or8 (Const8 [int64(int8(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c | d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpPhi_0(v *Value) bool { // match: (Phi (Const8 [c]) (Const8 [c])) // cond: // result: (Const8 [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != c { break } if len(v.Args) != 2 { break } v.reset(OpConst8) v.AuxInt = c return true } // match: (Phi (Const16 [c]) (Const16 [c])) // cond: // result: (Const16 [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != c { break } if len(v.Args) != 2 { break } v.reset(OpConst16) v.AuxInt = c return true } // match: (Phi (Const32 [c]) (Const32 [c])) // cond: // result: (Const32 [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != c { break } if len(v.Args) != 2 { break } v.reset(OpConst32) v.AuxInt = c return true } // match: (Phi (Const64 [c]) (Const64 [c])) // cond: // result: (Const64 [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != c { break } if len(v.Args) != 2 { break } v.reset(OpConst64) v.AuxInt = c return true } return false } func rewriteValuegeneric_OpPtrIndex_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (PtrIndex ptr idx) // cond: config.PtrSize == 4 // result: (AddPtr ptr (Mul32 idx (Const32 [t.Elem().Size()]))) for { t := v.Type idx := v.Args[1] ptr := v.Args[0] if !(config.PtrSize == 4) { break } v.reset(OpAddPtr) v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpMul32, typ.Int) v0.AddArg(idx) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = t.Elem().Size() v0.AddArg(v1) v.AddArg(v0) return true } // match: (PtrIndex ptr idx) // cond: config.PtrSize == 8 // result: (AddPtr ptr (Mul64 idx (Const64 [t.Elem().Size()]))) for { t := v.Type idx := v.Args[1] ptr := v.Args[0] if !(config.PtrSize == 8) { break } v.reset(OpAddPtr) v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpMul64, typ.Int) v0.AddArg(idx) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = t.Elem().Size() v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRotateLeft16_0(v *Value) bool { // match: (RotateLeft16 x (Const16 [c])) // cond: c%16 == 0 // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(c%16 == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpRotateLeft32_0(v *Value) bool { // match: (RotateLeft32 x (Const32 [c])) // cond: c%32 == 0 // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(c%32 == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpRotateLeft64_0(v *Value) bool { // match: (RotateLeft64 x (Const64 [c])) // cond: c%64 == 0 // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(c%64 == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpRotateLeft8_0(v *Value) bool { // match: (RotateLeft8 x (Const8 [c])) // cond: c%8 == 0 // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(c%8 == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpRound32F_0(v *Value) bool { // match: (Round32F x:(Const32F)) // cond: // result: x for { x := v.Args[0] if x.Op != OpConst32F { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpRound64F_0(v *Value) bool { // match: (Round64F x:(Const64F)) // cond: // result: x for { x := v.Args[0] if x.Op != OpConst64F { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpRsh16Ux16_0(v *Value) bool { b := v.Block // match: (Rsh16Ux16 x (Const16 [c])) // cond: // result: (Rsh16Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh16Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh16Ux16 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh16Ux32_0(v *Value) bool { b := v.Block // match: (Rsh16Ux32 x (Const32 [c])) // cond: // result: (Rsh16Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh16Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh16Ux32 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh16Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux64 (Const16 [c]) (Const64 [d])) // cond: // result: (Const16 [int64(int16(uint16(c) >> uint64(d)))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(uint16(c) >> uint64(d))) return true } // match: (Rsh16Ux64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh16Ux64 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Rsh16Ux64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Rsh16Ux64 (Rsh16Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh16Ux64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh16Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh16Ux64 (Rsh16x64 x _) (Const64 [15])) // cond: // result: (Rsh16Ux64 x (Const64 [15])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type if v_1.AuxInt != 15 { break } v.reset(OpRsh16Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = 15 v.AddArg(v0) return true } // match: (Rsh16Ux64 (Lsh16x64 (Rsh16Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh16Ux64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh16Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh16Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } // match: (Rsh16Ux64 (Lsh16x64 x (Const64 [8])) (Const64 [8])) // cond: // result: (ZeroExt8to16 (Trunc16to8 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 8 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 8 { break } v.reset(OpZeroExt8to16) v0 := b.NewValue0(v.Pos, OpTrunc16to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh16Ux8_0(v *Value) bool { b := v.Block // match: (Rsh16Ux8 x (Const8 [c])) // cond: // result: (Rsh16Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh16Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh16Ux8 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh16x16_0(v *Value) bool { b := v.Block // match: (Rsh16x16 x (Const16 [c])) // cond: // result: (Rsh16x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh16x16 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh16x32_0(v *Value) bool { b := v.Block // match: (Rsh16x32 x (Const32 [c])) // cond: // result: (Rsh16x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh16x32 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh16x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x64 (Const16 [c]) (Const64 [d])) // cond: // result: (Const16 [int64(int16(c) >> uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c) >> uint64(d)) return true } // match: (Rsh16x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh16x64 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Rsh16x64 (Rsh16x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh16x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh16x64 (Lsh16x64 x (Const64 [8])) (Const64 [8])) // cond: // result: (SignExt8to16 (Trunc16to8 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 8 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 8 { break } v.reset(OpSignExt8to16) v0 := b.NewValue0(v.Pos, OpTrunc16to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh16x8_0(v *Value) bool { b := v.Block // match: (Rsh16x8 x (Const8 [c])) // cond: // result: (Rsh16x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh16x8 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh32Ux16_0(v *Value) bool { b := v.Block // match: (Rsh32Ux16 x (Const16 [c])) // cond: // result: (Rsh32Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh32Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh32Ux16 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh32Ux32_0(v *Value) bool { b := v.Block // match: (Rsh32Ux32 x (Const32 [c])) // cond: // result: (Rsh32Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh32Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh32Ux32 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh32Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux64 (Const32 [c]) (Const64 [d])) // cond: // result: (Const32 [int64(int32(uint32(c) >> uint64(d)))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(uint32(c) >> uint64(d))) return true } // match: (Rsh32Ux64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh32Ux64 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Rsh32Ux64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Rsh32Ux64 (Rsh32Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh32Ux64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh32Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh32Ux64 (Rsh32x64 x _) (Const64 [31])) // cond: // result: (Rsh32Ux64 x (Const64 [31])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type if v_1.AuxInt != 31 { break } v.reset(OpRsh32Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = 31 v.AddArg(v0) return true } // match: (Rsh32Ux64 (Lsh32x64 (Rsh32Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh32Ux64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh32Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } // match: (Rsh32Ux64 (Lsh32x64 x (Const64 [24])) (Const64 [24])) // cond: // result: (ZeroExt8to32 (Trunc32to8 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 24 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 24 { break } v.reset(OpZeroExt8to32) v0 := b.NewValue0(v.Pos, OpTrunc32to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh32Ux64 (Lsh32x64 x (Const64 [16])) (Const64 [16])) // cond: // result: (ZeroExt16to32 (Trunc32to16 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 16 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 16 { break } v.reset(OpZeroExt16to32) v0 := b.NewValue0(v.Pos, OpTrunc32to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh32Ux8_0(v *Value) bool { b := v.Block // match: (Rsh32Ux8 x (Const8 [c])) // cond: // result: (Rsh32Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh32Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh32Ux8 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh32x16_0(v *Value) bool { b := v.Block // match: (Rsh32x16 x (Const16 [c])) // cond: // result: (Rsh32x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh32x16 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh32x32_0(v *Value) bool { b := v.Block // match: (Rsh32x32 x (Const32 [c])) // cond: // result: (Rsh32x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh32x32 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh32x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x64 (Const32 [c]) (Const64 [d])) // cond: // result: (Const32 [int64(int32(c) >> uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c) >> uint64(d)) return true } // match: (Rsh32x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh32x64 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Rsh32x64 (Rsh32x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh32x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh32x64 (Lsh32x64 x (Const64 [24])) (Const64 [24])) // cond: // result: (SignExt8to32 (Trunc32to8 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 24 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 24 { break } v.reset(OpSignExt8to32) v0 := b.NewValue0(v.Pos, OpTrunc32to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh32x64 (Lsh32x64 x (Const64 [16])) (Const64 [16])) // cond: // result: (SignExt16to32 (Trunc32to16 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 16 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 16 { break } v.reset(OpSignExt16to32) v0 := b.NewValue0(v.Pos, OpTrunc32to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh32x8_0(v *Value) bool { b := v.Block // match: (Rsh32x8 x (Const8 [c])) // cond: // result: (Rsh32x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh32x8 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh64Ux16_0(v *Value) bool { b := v.Block // match: (Rsh64Ux16 x (Const16 [c])) // cond: // result: (Rsh64Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh64Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh64Ux16 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh64Ux32_0(v *Value) bool { b := v.Block // match: (Rsh64Ux32 x (Const32 [c])) // cond: // result: (Rsh64Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh64Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh64Ux32 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh64Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [int64(uint64(c) >> uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = int64(uint64(c) >> uint64(d)) return true } // match: (Rsh64Ux64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh64Ux64 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Rsh64Ux64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (Const64 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Rsh64Ux64 (Rsh64Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh64Ux64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh64Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh64Ux64 (Rsh64x64 x _) (Const64 [63])) // cond: // result: (Rsh64Ux64 x (Const64 [63])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type if v_1.AuxInt != 63 { break } v.reset(OpRsh64Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = 63 v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 (Rsh64Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh64Ux64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh64Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [56])) (Const64 [56])) // cond: // result: (ZeroExt8to64 (Trunc64to8 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 56 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 56 { break } v.reset(OpZeroExt8to64) v0 := b.NewValue0(v.Pos, OpTrunc64to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [48])) (Const64 [48])) // cond: // result: (ZeroExt16to64 (Trunc64to16 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 48 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 48 { break } v.reset(OpZeroExt16to64) v0 := b.NewValue0(v.Pos, OpTrunc64to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [32])) (Const64 [32])) // cond: // result: (ZeroExt32to64 (Trunc64to32 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 32 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 32 { break } v.reset(OpZeroExt32to64) v0 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh64Ux8_0(v *Value) bool { b := v.Block // match: (Rsh64Ux8 x (Const8 [c])) // cond: // result: (Rsh64Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh64Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh64Ux8 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh64x16_0(v *Value) bool { b := v.Block // match: (Rsh64x16 x (Const16 [c])) // cond: // result: (Rsh64x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh64x16 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh64x32_0(v *Value) bool { b := v.Block // match: (Rsh64x32 x (Const32 [c])) // cond: // result: (Rsh64x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh64x32 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh64x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c >> uint64(d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c >> uint64(d) return true } // match: (Rsh64x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh64x64 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Rsh64x64 (Rsh64x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh64x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [56])) (Const64 [56])) // cond: // result: (SignExt8to64 (Trunc64to8 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 56 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 56 { break } v.reset(OpSignExt8to64) v0 := b.NewValue0(v.Pos, OpTrunc64to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [48])) (Const64 [48])) // cond: // result: (SignExt16to64 (Trunc64to16 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 48 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 48 { break } v.reset(OpSignExt16to64) v0 := b.NewValue0(v.Pos, OpTrunc64to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [32])) (Const64 [32])) // cond: // result: (SignExt32to64 (Trunc64to32 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 32 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 32 { break } v.reset(OpSignExt32to64) v0 := b.NewValue0(v.Pos, OpTrunc64to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh64x8_0(v *Value) bool { b := v.Block // match: (Rsh64x8 x (Const8 [c])) // cond: // result: (Rsh64x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh64x8 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh8Ux16_0(v *Value) bool { b := v.Block // match: (Rsh8Ux16 x (Const16 [c])) // cond: // result: (Rsh8Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh8Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh8Ux16 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh8Ux32_0(v *Value) bool { b := v.Block // match: (Rsh8Ux32 x (Const32 [c])) // cond: // result: (Rsh8Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh8Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh8Ux32 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh8Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux64 (Const8 [c]) (Const64 [d])) // cond: // result: (Const8 [int64(int8(uint8(c) >> uint64(d)))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(uint8(c) >> uint64(d))) return true } // match: (Rsh8Ux64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh8Ux64 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Rsh8Ux64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Rsh8Ux64 (Rsh8Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh8Ux64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh8Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh8Ux64 (Rsh8x64 x _) (Const64 [7])) // cond: // result: (Rsh8Ux64 x (Const64 [7] )) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type if v_1.AuxInt != 7 { break } v.reset(OpRsh8Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = 7 v.AddArg(v0) return true } // match: (Rsh8Ux64 (Lsh8x64 (Rsh8Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh8Ux64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh8Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh8Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh8Ux8_0(v *Value) bool { b := v.Block // match: (Rsh8Ux8 x (Const8 [c])) // cond: // result: (Rsh8Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh8Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh8Ux8 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh8x16_0(v *Value) bool { b := v.Block // match: (Rsh8x16 x (Const16 [c])) // cond: // result: (Rsh8x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh8x16 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh8x32_0(v *Value) bool { b := v.Block // match: (Rsh8x32 x (Const32 [c])) // cond: // result: (Rsh8x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh8x32 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh8x64_0(v *Value) bool { b := v.Block // match: (Rsh8x64 (Const8 [c]) (Const64 [d])) // cond: // result: (Const8 [int64(int8(c) >> uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c) >> uint64(d)) return true } // match: (Rsh8x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh8x64 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Rsh8x64 (Rsh8x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh8x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh8x8_0(v *Value) bool { b := v.Block // match: (Rsh8x8 x (Const8 [c])) // cond: // result: (Rsh8x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh8x8 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpSelect0_0(v *Value) bool { // match: (Select0 (Div128u (Const64 [0]) lo y)) // cond: // result: (Div64u lo y) for { v_0 := v.Args[0] if v_0.Op != OpDiv128u { break } y := v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } if v_0_0.AuxInt != 0 { break } lo := v_0.Args[1] v.reset(OpDiv64u) v.AddArg(lo) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpSelect1_0(v *Value) bool { // match: (Select1 (Div128u (Const64 [0]) lo y)) // cond: // result: (Mod64u lo y) for { v_0 := v.Args[0] if v_0.Op != OpDiv128u { break } y := v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } if v_0_0.AuxInt != 0 { break } lo := v_0.Args[1] v.reset(OpMod64u) v.AddArg(lo) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpSignExt16to32_0(v *Value) bool { // match: (SignExt16to32 (Const16 [c])) // cond: // result: (Const32 [int64( int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(int16(c)) return true } // match: (SignExt16to32 (Trunc32to16 x:(Rsh32x64 _ (Const64 [s])))) // cond: s >= 16 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc32to16 { break } x := v_0.Args[0] if x.Op != OpRsh32x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 16) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSignExt16to64_0(v *Value) bool { // match: (SignExt16to64 (Const16 [c])) // cond: // result: (Const64 [int64( int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(int16(c)) return true } // match: (SignExt16to64 (Trunc64to16 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 48 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc64to16 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 48) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSignExt32to64_0(v *Value) bool { // match: (SignExt32to64 (Const32 [c])) // cond: // result: (Const64 [int64( int32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(int32(c)) return true } // match: (SignExt32to64 (Trunc64to32 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 32 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc64to32 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 32) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSignExt8to16_0(v *Value) bool { // match: (SignExt8to16 (Const8 [c])) // cond: // result: (Const16 [int64( int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst16) v.AuxInt = int64(int8(c)) return true } // match: (SignExt8to16 (Trunc16to8 x:(Rsh16x64 _ (Const64 [s])))) // cond: s >= 8 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc16to8 { break } x := v_0.Args[0] if x.Op != OpRsh16x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 8) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSignExt8to32_0(v *Value) bool { // match: (SignExt8to32 (Const8 [c])) // cond: // result: (Const32 [int64( int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(int8(c)) return true } // match: (SignExt8to32 (Trunc32to8 x:(Rsh32x64 _ (Const64 [s])))) // cond: s >= 24 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc32to8 { break } x := v_0.Args[0] if x.Op != OpRsh32x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 24) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSignExt8to64_0(v *Value) bool { // match: (SignExt8to64 (Const8 [c])) // cond: // result: (Const64 [int64( int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(int8(c)) return true } // match: (SignExt8to64 (Trunc64to8 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 56 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc64to8 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 56) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSliceCap_0(v *Value) bool { // match: (SliceCap (SliceMake _ _ (Const64 [c]))) // cond: // result: (Const64 [c]) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpConst64 { break } t := v_0_2.Type c := v_0_2.AuxInt v.reset(OpConst64) v.Type = t v.AuxInt = c return true } // match: (SliceCap (SliceMake _ _ (Const32 [c]))) // cond: // result: (Const32 [c]) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpConst32 { break } t := v_0_2.Type c := v_0_2.AuxInt v.reset(OpConst32) v.Type = t v.AuxInt = c return true } // match: (SliceCap (SliceMake _ _ (SliceCap x))) // cond: // result: (SliceCap x) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpSliceCap { break } x := v_0_2.Args[0] v.reset(OpSliceCap) v.AddArg(x) return true } // match: (SliceCap (SliceMake _ _ (SliceLen x))) // cond: // result: (SliceLen x) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpSliceLen { break } x := v_0_2.Args[0] v.reset(OpSliceLen) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSliceLen_0(v *Value) bool { // match: (SliceLen (SliceMake _ (Const64 [c]) _)) // cond: // result: (Const64 [c]) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type c := v_0_1.AuxInt v.reset(OpConst64) v.Type = t v.AuxInt = c return true } // match: (SliceLen (SliceMake _ (Const32 [c]) _)) // cond: // result: (Const32 [c]) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type c := v_0_1.AuxInt v.reset(OpConst32) v.Type = t v.AuxInt = c return true } // match: (SliceLen (SliceMake _ (SliceLen x) _)) // cond: // result: (SliceLen x) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_1 := v_0.Args[1] if v_0_1.Op != OpSliceLen { break } x := v_0_1.Args[0] v.reset(OpSliceLen) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSlicePtr_0(v *Value) bool { // match: (SlicePtr (SliceMake (SlicePtr x) _ _)) // cond: // result: (SlicePtr x) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSlicePtr { break } x := v_0_0.Args[0] v.reset(OpSlicePtr) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSlicemask_0(v *Value) bool { // match: (Slicemask (Const32 [x])) // cond: x > 0 // result: (Const32 [-1]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } x := v_0.AuxInt if !(x > 0) { break } v.reset(OpConst32) v.AuxInt = -1 return true } // match: (Slicemask (Const32 [0])) // cond: // result: (Const32 [0]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Slicemask (Const64 [x])) // cond: x > 0 // result: (Const64 [-1]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } x := v_0.AuxInt if !(x > 0) { break } v.reset(OpConst64) v.AuxInt = -1 return true } // match: (Slicemask (Const64 [0])) // cond: // result: (Const64 [0]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpSqrt_0(v *Value) bool { // match: (Sqrt (Const64F [c])) // cond: // result: (Const64F [auxFrom64F(math.Sqrt(auxTo64F(c)))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(math.Sqrt(auxTo64F(c))) return true } return false } func rewriteValuegeneric_OpStaticCall_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (StaticCall {sym} s1:(Store _ (Const64 [sz]) s2:(Store _ src s3:(Store {t} _ dst mem)))) // cond: isSameSym(sym,"runtime.memmove") && t.(*types.Type).IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst,src,sz,config) && clobber(s1) && clobber(s2) && clobber(s3) // result: (Move {t.(*types.Type).Elem()} [sz] dst src mem) for { sym := v.Aux s1 := v.Args[0] if s1.Op != OpStore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpConst64 { break } sz := s1_1.AuxInt s2 := s1.Args[2] if s2.Op != OpStore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpStore { break } t := s3.Aux mem := s3.Args[2] dst := s3.Args[1] if !(isSameSym(sym, "runtime.memmove") && t.(*types.Type).IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(s1) && clobber(s2) && clobber(s3)) { break } v.reset(OpMove) v.AuxInt = sz v.Aux = t.(*types.Type).Elem() v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } // match: (StaticCall {sym} s1:(Store _ (Const32 [sz]) s2:(Store _ src s3:(Store {t} _ dst mem)))) // cond: isSameSym(sym,"runtime.memmove") && t.(*types.Type).IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst,src,sz,config) && clobber(s1) && clobber(s2) && clobber(s3) // result: (Move {t.(*types.Type).Elem()} [sz] dst src mem) for { sym := v.Aux s1 := v.Args[0] if s1.Op != OpStore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpConst32 { break } sz := s1_1.AuxInt s2 := s1.Args[2] if s2.Op != OpStore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpStore { break } t := s3.Aux mem := s3.Args[2] dst := s3.Args[1] if !(isSameSym(sym, "runtime.memmove") && t.(*types.Type).IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(s1) && clobber(s2) && clobber(s3)) { break } v.reset(OpMove) v.AuxInt = sz v.Aux = t.(*types.Type).Elem() v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } // match: (StaticCall {sym} x) // cond: needRaceCleanup(sym,v) // result: x for { sym := v.Aux x := v.Args[0] if !(needRaceCleanup(sym, v)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpStore_0(v *Value) bool { b := v.Block // match: (Store {t1} p1 (Load p2 mem) mem) // cond: isSamePtr(p1, p2) && t2.Size() == sizeof(t1) // result: mem for { t1 := v.Aux mem := v.Args[2] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLoad { break } t2 := v_1.Type _ = v_1.Args[1] p2 := v_1.Args[0] if mem != v_1.Args[1] { break } if !(isSamePtr(p1, p2) && t2.Size() == sizeof(t1)) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ oldmem)) // cond: isSamePtr(p1, p2) && t2.Size() == sizeof(t1) && disjoint(p1, sizeof(t1), p3, sizeof(t3)) // result: mem for { t1 := v.Aux _ = v.Args[2] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v.Args[2] if mem.Op != OpStore { break } t3 := mem.Aux _ = mem.Args[2] p3 := mem.Args[0] if oldmem != mem.Args[2] { break } if !(isSamePtr(p1, p2) && t2.Size() == sizeof(t1) && disjoint(p1, sizeof(t1), p3, sizeof(t3))) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ (Store {t4} p4 _ oldmem))) // cond: isSamePtr(p1, p2) && t2.Size() == sizeof(t1) && disjoint(p1, sizeof(t1), p3, sizeof(t3)) && disjoint(p1, sizeof(t1), p4, sizeof(t4)) // result: mem for { t1 := v.Aux _ = v.Args[2] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v.Args[2] if mem.Op != OpStore { break } t3 := mem.Aux _ = mem.Args[2] p3 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t4 := mem_2.Aux _ = mem_2.Args[2] p4 := mem_2.Args[0] if oldmem != mem_2.Args[2] { break } if !(isSamePtr(p1, p2) && t2.Size() == sizeof(t1) && disjoint(p1, sizeof(t1), p3, sizeof(t3)) && disjoint(p1, sizeof(t1), p4, sizeof(t4))) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 _ oldmem)))) // cond: isSamePtr(p1, p2) && t2.Size() == sizeof(t1) && disjoint(p1, sizeof(t1), p3, sizeof(t3)) && disjoint(p1, sizeof(t1), p4, sizeof(t4)) && disjoint(p1, sizeof(t1), p5, sizeof(t5)) // result: mem for { t1 := v.Aux _ = v.Args[2] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v.Args[2] if mem.Op != OpStore { break } t3 := mem.Aux _ = mem.Args[2] p3 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t4 := mem_2.Aux _ = mem_2.Args[2] p4 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t5 := mem_2_2.Aux _ = mem_2_2.Args[2] p5 := mem_2_2.Args[0] if oldmem != mem_2_2.Args[2] { break } if !(isSamePtr(p1, p2) && t2.Size() == sizeof(t1) && disjoint(p1, sizeof(t1), p3, sizeof(t3)) && disjoint(p1, sizeof(t1), p4, sizeof(t4)) && disjoint(p1, sizeof(t1), p5, sizeof(t5))) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t} (OffPtr [o] p1) x mem:(Zero [n] p2 _)) // cond: isConstZero(x) && o >= 0 && sizeof(t) + o <= n && isSamePtr(p1, p2) // result: mem for { t := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] x := v.Args[1] mem := v.Args[2] if mem.Op != OpZero { break } n := mem.AuxInt _ = mem.Args[1] p2 := mem.Args[0] if !(isConstZero(x) && o >= 0 && sizeof(t)+o <= n && isSamePtr(p1, p2)) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Zero [n] p3 _))) // cond: isConstZero(x) && o1 >= 0 && sizeof(t1) + o1 <= n && isSamePtr(p1, p3) && disjoint(op, sizeof(t1), p2, sizeof(t2)) // result: mem for { t1 := v.Aux _ = v.Args[2] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] x := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpZero { break } n := mem_2.AuxInt _ = mem_2.Args[1] p3 := mem_2.Args[0] if !(isConstZero(x) && o1 >= 0 && sizeof(t1)+o1 <= n && isSamePtr(p1, p3) && disjoint(op, sizeof(t1), p2, sizeof(t2))) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Store {t3} p3 _ (Zero [n] p4 _)))) // cond: isConstZero(x) && o1 >= 0 && sizeof(t1) + o1 <= n && isSamePtr(p1, p4) && disjoint(op, sizeof(t1), p2, sizeof(t2)) && disjoint(op, sizeof(t1), p3, sizeof(t3)) // result: mem for { t1 := v.Aux _ = v.Args[2] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] x := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] p3 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpZero { break } n := mem_2_2.AuxInt _ = mem_2_2.Args[1] p4 := mem_2_2.Args[0] if !(isConstZero(x) && o1 >= 0 && sizeof(t1)+o1 <= n && isSamePtr(p1, p4) && disjoint(op, sizeof(t1), p2, sizeof(t2)) && disjoint(op, sizeof(t1), p3, sizeof(t3))) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Zero [n] p5 _))))) // cond: isConstZero(x) && o1 >= 0 && sizeof(t1) + o1 <= n && isSamePtr(p1, p5) && disjoint(op, sizeof(t1), p2, sizeof(t2)) && disjoint(op, sizeof(t1), p3, sizeof(t3)) && disjoint(op, sizeof(t1), p4, sizeof(t4)) // result: mem for { t1 := v.Aux _ = v.Args[2] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] x := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] p3 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := mem_2_2.Aux _ = mem_2_2.Args[2] p4 := mem_2_2.Args[0] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpZero { break } n := mem_2_2_2.AuxInt _ = mem_2_2_2.Args[1] p5 := mem_2_2_2.Args[0] if !(isConstZero(x) && o1 >= 0 && sizeof(t1)+o1 <= n && isSamePtr(p1, p5) && disjoint(op, sizeof(t1), p2, sizeof(t2)) && disjoint(op, sizeof(t1), p3, sizeof(t3)) && disjoint(op, sizeof(t1), p4, sizeof(t4))) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store _ (StructMake0) mem) // cond: // result: mem for { mem := v.Args[2] v_1 := v.Args[1] if v_1.Op != OpStructMake0 { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store dst (StructMake1 f0) mem) // cond: // result: (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem) for { mem := v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStructMake1 { break } t := v_1.Type f0 := v_1.Args[0] v.reset(OpStore) v.Aux = t.FieldType(0) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v0.AuxInt = 0 v0.AddArg(dst) v.AddArg(v0) v.AddArg(f0) v.AddArg(mem) return true } return false } func rewriteValuegeneric_OpStore_10(v *Value) bool { b := v.Block config := b.Func.Config fe := b.Func.fe // match: (Store dst (StructMake2 f0 f1) mem) // cond: // result: (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem)) for { mem := v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStructMake2 { break } t := v_1.Type f1 := v_1.Args[1] f0 := v_1.Args[0] v.reset(OpStore) v.Aux = t.FieldType(1) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v0.AuxInt = t.FieldOff(1) v0.AddArg(dst) v.AddArg(v0) v.AddArg(f1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t.FieldType(0) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v2.AuxInt = 0 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(f0) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Store dst (StructMake3 f0 f1 f2) mem) // cond: // result: (Store {t.FieldType(2)} (OffPtr [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem))) for { mem := v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStructMake3 { break } t := v_1.Type f2 := v_1.Args[2] f0 := v_1.Args[0] f1 := v_1.Args[1] v.reset(OpStore) v.Aux = t.FieldType(2) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v0.AuxInt = t.FieldOff(2) v0.AddArg(dst) v.AddArg(v0) v.AddArg(f2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t.FieldType(1) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v2.AuxInt = t.FieldOff(1) v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(f1) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t.FieldType(0) v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v4.AuxInt = 0 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(f0) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Store dst (StructMake4 f0 f1 f2 f3) mem) // cond: // result: (Store {t.FieldType(3)} (OffPtr [t.FieldOff(3)] dst) f3 (Store {t.FieldType(2)} (OffPtr [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem)))) for { mem := v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStructMake4 { break } t := v_1.Type f3 := v_1.Args[3] f0 := v_1.Args[0] f1 := v_1.Args[1] f2 := v_1.Args[2] v.reset(OpStore) v.Aux = t.FieldType(3) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo()) v0.AuxInt = t.FieldOff(3) v0.AddArg(dst) v.AddArg(v0) v.AddArg(f3) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t.FieldType(2) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v2.AuxInt = t.FieldOff(2) v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(f2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t.FieldType(1) v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v4.AuxInt = t.FieldOff(1) v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(f1) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = t.FieldType(0) v6 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v6.AuxInt = 0 v6.AddArg(dst) v5.AddArg(v6) v5.AddArg(f0) v5.AddArg(mem) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Store {t} dst (Load src mem) mem) // cond: !fe.CanSSA(t.(*types.Type)) // result: (Move {t} [sizeof(t)] dst src mem) for { t := v.Aux mem := v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLoad { break } _ = v_1.Args[1] src := v_1.Args[0] if mem != v_1.Args[1] { break } if !(!fe.CanSSA(t.(*types.Type))) { break } v.reset(OpMove) v.AuxInt = sizeof(t) v.Aux = t v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } // match: (Store {t} dst (Load src mem) (VarDef {x} mem)) // cond: !fe.CanSSA(t.(*types.Type)) // result: (Move {t} [sizeof(t)] dst src (VarDef {x} mem)) for { t := v.Aux _ = v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLoad { break } mem := v_1.Args[1] src := v_1.Args[0] v_2 := v.Args[2] if v_2.Op != OpVarDef { break } x := v_2.Aux if mem != v_2.Args[0] { break } if !(!fe.CanSSA(t.(*types.Type))) { break } v.reset(OpMove) v.AuxInt = sizeof(t) v.Aux = t v.AddArg(dst) v.AddArg(src) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = x v0.AddArg(mem) v.AddArg(v0) return true } // match: (Store _ (ArrayMake0) mem) // cond: // result: mem for { mem := v.Args[2] v_1 := v.Args[1] if v_1.Op != OpArrayMake0 { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store dst (ArrayMake1 e) mem) // cond: // result: (Store {e.Type} dst e mem) for { mem := v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpArrayMake1 { break } e := v_1.Args[0] v.reset(OpStore) v.Aux = e.Type v.AddArg(dst) v.AddArg(e) v.AddArg(mem) return true } // match: (Store (Load (OffPtr [c] (SP)) mem) x mem) // cond: isConstZero(x) && mem.Op == OpStaticCall && isSameSym(mem.Aux, "runtime.newobject") && c == config.ctxt.FixedFrameSize() + config.RegSize // result: mem for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpLoad { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpOffPtr { break } c := v_0_0.AuxInt v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpSP { break } if mem != v_0.Args[1] { break } x := v.Args[1] if !(isConstZero(x) && mem.Op == OpStaticCall && isSameSym(mem.Aux, "runtime.newobject") && c == config.ctxt.FixedFrameSize()+config.RegSize) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store (OffPtr (Load (OffPtr [c] (SP)) mem)) x mem) // cond: isConstZero(x) && mem.Op == OpStaticCall && isSameSym(mem.Aux, "runtime.newobject") && c == config.ctxt.FixedFrameSize() + config.RegSize // result: mem for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLoad { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpOffPtr { break } c := v_0_0_0.AuxInt v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpSP { break } if mem != v_0_0.Args[1] { break } x := v.Args[1] if !(isConstZero(x) && mem.Op == OpStaticCall && isSameSym(mem.Aux, "runtime.newobject") && c == config.ctxt.FixedFrameSize()+config.RegSize) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [0] p2) d2 m3:(Move [n] p3 _ mem))) // cond: m2.Uses == 1 && m3.Uses == 1 && o1 == sizeof(t2) && n == sizeof(t2) + sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2) && clobber(m3) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 mem)) for { t1 := v.Aux _ = v.Args[2] op1 := v.Args[0] if op1.Op != OpOffPtr { break } o1 := op1.AuxInt p1 := op1.Args[0] d1 := v.Args[1] m2 := v.Args[2] if m2.Op != OpStore { break } t2 := m2.Aux _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } if op2.AuxInt != 0 { break } p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpMove { break } n := m3.AuxInt mem := m3.Args[2] p3 := m3.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && o1 == sizeof(t2) && n == sizeof(t2)+sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2) && clobber(m3)) { break } v.reset(OpStore) v.Aux = t1 v.AddArg(op1) v.AddArg(d1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = t2 v0.AddArg(op2) v0.AddArg(d2) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpStore_20(v *Value) bool { b := v.Block // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Move [n] p4 _ mem)))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t3) + sizeof(t2) + sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2) && clobber(m3) && clobber(m4) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 mem))) for { t1 := v.Aux _ = v.Args[2] op1 := v.Args[0] if op1.Op != OpOffPtr { break } o1 := op1.AuxInt p1 := op1.Args[0] d1 := v.Args[1] m2 := v.Args[2] if m2.Op != OpStore { break } t2 := m2.Aux _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := op2.AuxInt p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := m3.Aux _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } if op3.AuxInt != 0 { break } p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpMove { break } n := m4.AuxInt mem := m4.Args[2] p4 := m4.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t3)+sizeof(t2)+sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2) && clobber(m3) && clobber(m4)) { break } v.reset(OpStore) v.Aux = t1 v.AddArg(op1) v.AddArg(d1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = t2 v0.AddArg(op2) v0.AddArg(d2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v1.AddArg(op3) v1.AddArg(d3) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Move [n] p5 _ mem))))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t4) + sizeof(t3) + sizeof(t2) + sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2) && clobber(m3) && clobber(m4) && clobber(m5) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 (Store {t4} op4 d4 mem)))) for { t1 := v.Aux _ = v.Args[2] op1 := v.Args[0] if op1.Op != OpOffPtr { break } o1 := op1.AuxInt p1 := op1.Args[0] d1 := v.Args[1] m2 := v.Args[2] if m2.Op != OpStore { break } t2 := m2.Aux _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := op2.AuxInt p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := m3.Aux _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } o3 := op3.AuxInt p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpStore { break } t4 := m4.Aux _ = m4.Args[2] op4 := m4.Args[0] if op4.Op != OpOffPtr { break } if op4.AuxInt != 0 { break } p4 := op4.Args[0] d4 := m4.Args[1] m5 := m4.Args[2] if m5.Op != OpMove { break } n := m5.AuxInt mem := m5.Args[2] p5 := m5.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t4)+sizeof(t3)+sizeof(t2)+sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2) && clobber(m3) && clobber(m4) && clobber(m5)) { break } v.reset(OpStore) v.Aux = t1 v.AddArg(op1) v.AddArg(d1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = t2 v0.AddArg(op2) v0.AddArg(d2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v1.AddArg(op3) v1.AddArg(d3) v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v2.Aux = t4 v2.AddArg(op4) v2.AddArg(d4) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [0] p2) d2 m3:(Zero [n] p3 mem))) // cond: m2.Uses == 1 && m3.Uses == 1 && o1 == sizeof(t2) && n == sizeof(t2) + sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2) && clobber(m3) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 mem)) for { t1 := v.Aux _ = v.Args[2] op1 := v.Args[0] if op1.Op != OpOffPtr { break } o1 := op1.AuxInt p1 := op1.Args[0] d1 := v.Args[1] m2 := v.Args[2] if m2.Op != OpStore { break } t2 := m2.Aux _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } if op2.AuxInt != 0 { break } p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpZero { break } n := m3.AuxInt mem := m3.Args[1] p3 := m3.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && o1 == sizeof(t2) && n == sizeof(t2)+sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2) && clobber(m3)) { break } v.reset(OpStore) v.Aux = t1 v.AddArg(op1) v.AddArg(d1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = t2 v0.AddArg(op2) v0.AddArg(d2) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Zero [n] p4 mem)))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t3) + sizeof(t2) + sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2) && clobber(m3) && clobber(m4) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 mem))) for { t1 := v.Aux _ = v.Args[2] op1 := v.Args[0] if op1.Op != OpOffPtr { break } o1 := op1.AuxInt p1 := op1.Args[0] d1 := v.Args[1] m2 := v.Args[2] if m2.Op != OpStore { break } t2 := m2.Aux _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := op2.AuxInt p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := m3.Aux _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } if op3.AuxInt != 0 { break } p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpZero { break } n := m4.AuxInt mem := m4.Args[1] p4 := m4.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t3)+sizeof(t2)+sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2) && clobber(m3) && clobber(m4)) { break } v.reset(OpStore) v.Aux = t1 v.AddArg(op1) v.AddArg(d1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = t2 v0.AddArg(op2) v0.AddArg(d2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v1.AddArg(op3) v1.AddArg(d3) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Zero [n] p5 mem))))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t4) + sizeof(t3) + sizeof(t2) + sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2) && clobber(m3) && clobber(m4) && clobber(m5) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 (Store {t4} op4 d4 mem)))) for { t1 := v.Aux _ = v.Args[2] op1 := v.Args[0] if op1.Op != OpOffPtr { break } o1 := op1.AuxInt p1 := op1.Args[0] d1 := v.Args[1] m2 := v.Args[2] if m2.Op != OpStore { break } t2 := m2.Aux _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := op2.AuxInt p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := m3.Aux _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } o3 := op3.AuxInt p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpStore { break } t4 := m4.Aux _ = m4.Args[2] op4 := m4.Args[0] if op4.Op != OpOffPtr { break } if op4.AuxInt != 0 { break } p4 := op4.Args[0] d4 := m4.Args[1] m5 := m4.Args[2] if m5.Op != OpZero { break } n := m5.AuxInt mem := m5.Args[1] p5 := m5.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t4)+sizeof(t3)+sizeof(t2)+sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2) && clobber(m3) && clobber(m4) && clobber(m5)) { break } v.reset(OpStore) v.Aux = t1 v.AddArg(op1) v.AddArg(d1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = t2 v0.AddArg(op2) v0.AddArg(d2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v1.AddArg(op3) v1.AddArg(d3) v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v2.Aux = t4 v2.AddArg(op4) v2.AddArg(d4) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpStringLen_0(v *Value) bool { // match: (StringLen (StringMake _ (Const64 [c]))) // cond: // result: (Const64 [c]) for { v_0 := v.Args[0] if v_0.Op != OpStringMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type c := v_0_1.AuxInt v.reset(OpConst64) v.Type = t v.AuxInt = c return true } return false } func rewriteValuegeneric_OpStringPtr_0(v *Value) bool { // match: (StringPtr (StringMake (Addr {s} base) _)) // cond: // result: (Addr {s} base) for { v_0 := v.Args[0] if v_0.Op != OpStringMake { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { break } t := v_0_0.Type s := v_0_0.Aux base := v_0_0.Args[0] v.reset(OpAddr) v.Type = t v.Aux = s v.AddArg(base) return true } return false } func rewriteValuegeneric_OpStructSelect_0(v *Value) bool { // match: (StructSelect (StructMake1 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpStructMake1 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [0] (StructMake2 x _)) // cond: // result: x for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake2 { break } _ = v_0.Args[1] x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [1] (StructMake2 _ x)) // cond: // result: x for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake2 { break } x := v_0.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [0] (StructMake3 x _ _)) // cond: // result: x for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake3 { break } _ = v_0.Args[2] x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [1] (StructMake3 _ x _)) // cond: // result: x for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake3 { break } _ = v_0.Args[2] x := v_0.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [2] (StructMake3 _ _ x)) // cond: // result: x for { if v.AuxInt != 2 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake3 { break } x := v_0.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [0] (StructMake4 x _ _ _)) // cond: // result: x for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake4 { break } _ = v_0.Args[3] x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [1] (StructMake4 _ x _ _)) // cond: // result: x for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake4 { break } _ = v_0.Args[3] x := v_0.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [2] (StructMake4 _ _ x _)) // cond: // result: x for { if v.AuxInt != 2 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake4 { break } _ = v_0.Args[3] x := v_0.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [3] (StructMake4 _ _ _ x)) // cond: // result: x for { if v.AuxInt != 3 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake4 { break } x := v_0.Args[3] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpStructSelect_10(v *Value) bool { b := v.Block fe := b.Func.fe // match: (StructSelect [i] x:(Load ptr mem)) // cond: !fe.CanSSA(t) // result: @x.Block (Load (OffPtr [t.FieldOff(int(i))] ptr) mem) for { i := v.AuxInt x := v.Args[0] if x.Op != OpLoad { break } t := x.Type mem := x.Args[1] ptr := x.Args[0] if !(!fe.CanSSA(t)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpLoad, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, v.Type.PtrTo()) v1.AuxInt = t.FieldOff(int(i)) v1.AddArg(ptr) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (StructSelect [0] x:(IData _)) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] if x.Op != OpIData { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub16_0(v *Value) bool { b := v.Block // match: (Sub16 (Const16 [c]) (Const16 [d])) // cond: // result: (Const16 [int64(int16(c-d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c - d)) return true } // match: (Sub16 x (Const16 [c])) // cond: x.Op != OpConst16 // result: (Add16 (Const16 [int64(int16(-c))]) x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } t := v_1.Type c := v_1.AuxInt if !(x.Op != OpConst16) { break } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(-c)) v.AddArg(v0) v.AddArg(x) return true } // match: (Sub16 (Mul16 x y) (Mul16 x z)) // cond: // result: (Mul16 x (Sub16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub16 (Mul16 y x) (Mul16 x z)) // cond: // result: (Mul16 x (Sub16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub16 (Mul16 x y) (Mul16 z x)) // cond: // result: (Mul16 x (Sub16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub16 (Mul16 y x) (Mul16 z x)) // cond: // result: (Mul16 x (Sub16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub16 x x) // cond: // result: (Const16 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Sub16 (Add16 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub16 (Add16 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub16 (Add16 x y) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] x := v_0.Args[0] if y != v_0.Args[1] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub16_10(v *Value) bool { b := v.Block // match: (Sub16 (Add16 y x) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } x := v_0.Args[1] if y != v_0.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Sub16 x (Sub16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Sub16 x (Sub16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub16 (Const16 [c]) (Sub16 x (Const16 [d]))) // cond: // result: (Sub16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Sub16 (Const16 [c]) (Sub16 (Const16 [d]) x)) // cond: // result: (Add16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub32_0(v *Value) bool { b := v.Block // match: (Sub32 (Const32 [c]) (Const32 [d])) // cond: // result: (Const32 [int64(int32(c-d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c - d)) return true } // match: (Sub32 x (Const32 [c])) // cond: x.Op != OpConst32 // result: (Add32 (Const32 [int64(int32(-c))]) x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } t := v_1.Type c := v_1.AuxInt if !(x.Op != OpConst32) { break } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(-c)) v.AddArg(v0) v.AddArg(x) return true } // match: (Sub32 (Mul32 x y) (Mul32 x z)) // cond: // result: (Mul32 x (Sub32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub32 (Mul32 y x) (Mul32 x z)) // cond: // result: (Mul32 x (Sub32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub32 (Mul32 x y) (Mul32 z x)) // cond: // result: (Mul32 x (Sub32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub32 (Mul32 y x) (Mul32 z x)) // cond: // result: (Mul32 x (Sub32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub32 x x) // cond: // result: (Const32 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Sub32 (Add32 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub32 (Add32 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub32 (Add32 x y) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] x := v_0.Args[0] if y != v_0.Args[1] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub32_10(v *Value) bool { b := v.Block // match: (Sub32 (Add32 y x) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } x := v_0.Args[1] if y != v_0.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Sub32 x (Sub32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Sub32 x (Sub32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub32 (Const32 [c]) (Sub32 x (Const32 [d]))) // cond: // result: (Sub32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Sub32 (Const32 [c]) (Sub32 (Const32 [d]) x)) // cond: // result: (Add32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub32F_0(v *Value) bool { // match: (Sub32F (Const32F [c]) (Const32F [d])) // cond: // result: (Const32F [auxFrom32F(auxTo32F(c) - auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(auxTo32F(c) - auxTo32F(d)) return true } return false } func rewriteValuegeneric_OpSub64_0(v *Value) bool { b := v.Block // match: (Sub64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c-d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c - d return true } // match: (Sub64 x (Const64 [c])) // cond: x.Op != OpConst64 // result: (Add64 (Const64 [-c]) x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type c := v_1.AuxInt if !(x.Op != OpConst64) { break } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = -c v.AddArg(v0) v.AddArg(x) return true } // match: (Sub64 (Mul64 x y) (Mul64 x z)) // cond: // result: (Mul64 x (Sub64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub64 (Mul64 y x) (Mul64 x z)) // cond: // result: (Mul64 x (Sub64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub64 (Mul64 x y) (Mul64 z x)) // cond: // result: (Mul64 x (Sub64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub64 (Mul64 y x) (Mul64 z x)) // cond: // result: (Mul64 x (Sub64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub64 x x) // cond: // result: (Const64 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Sub64 (Add64 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub64 (Add64 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub64 (Add64 x y) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] x := v_0.Args[0] if y != v_0.Args[1] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub64_10(v *Value) bool { b := v.Block // match: (Sub64 (Add64 y x) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } x := v_0.Args[1] if y != v_0.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Sub64 x (Sub64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Sub64 x (Sub64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub64 (Const64 [c]) (Sub64 x (Const64 [d]))) // cond: // result: (Sub64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } // match: (Sub64 (Const64 [c]) (Sub64 (Const64 [d]) x)) // cond: // result: (Add64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub64F_0(v *Value) bool { // match: (Sub64F (Const64F [c]) (Const64F [d])) // cond: // result: (Const64F [auxFrom64F(auxTo64F(c) - auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(auxTo64F(c) - auxTo64F(d)) return true } return false } func rewriteValuegeneric_OpSub8_0(v *Value) bool { b := v.Block // match: (Sub8 (Const8 [c]) (Const8 [d])) // cond: // result: (Const8 [int64(int8(c-d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c - d)) return true } // match: (Sub8 x (Const8 [c])) // cond: x.Op != OpConst8 // result: (Add8 (Const8 [int64(int8(-c))]) x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } t := v_1.Type c := v_1.AuxInt if !(x.Op != OpConst8) { break } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(-c)) v.AddArg(v0) v.AddArg(x) return true } // match: (Sub8 (Mul8 x y) (Mul8 x z)) // cond: // result: (Mul8 x (Sub8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub8 (Mul8 y x) (Mul8 x z)) // cond: // result: (Mul8 x (Sub8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub8 (Mul8 x y) (Mul8 z x)) // cond: // result: (Mul8 x (Sub8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub8 (Mul8 y x) (Mul8 z x)) // cond: // result: (Mul8 x (Sub8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub8 x x) // cond: // result: (Const8 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Sub8 (Add8 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub8 (Add8 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub8 (Add8 x y) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] x := v_0.Args[0] if y != v_0.Args[1] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub8_10(v *Value) bool { b := v.Block // match: (Sub8 (Add8 y x) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } x := v_0.Args[1] if y != v_0.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Sub8 x (Sub8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Sub8 x (Sub8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub8 (Const8 [c]) (Sub8 x (Const8 [d]))) // cond: // result: (Sub8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Sub8 (Const8 [c]) (Sub8 (Const8 [d]) x)) // cond: // result: (Add8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpTrunc16to8_0(v *Value) bool { // match: (Trunc16to8 (Const16 [c])) // cond: // result: (Const8 [int64(int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c)) return true } // match: (Trunc16to8 (ZeroExt8to16 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpZeroExt8to16 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc16to8 (SignExt8to16 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpSignExt8to16 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc16to8 (And16 (Const16 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc16to8 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } y := v_0_0.AuxInt if !(y&0xFF == 0xFF) { break } v.reset(OpTrunc16to8) v.AddArg(x) return true } // match: (Trunc16to8 (And16 x (Const16 [y]))) // cond: y&0xFF == 0xFF // result: (Trunc16to8 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } y := v_0_1.AuxInt if !(y&0xFF == 0xFF) { break } v.reset(OpTrunc16to8) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpTrunc32to16_0(v *Value) bool { // match: (Trunc32to16 (Const32 [c])) // cond: // result: (Const16 [int64(int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c)) return true } // match: (Trunc32to16 (ZeroExt8to32 x)) // cond: // result: (ZeroExt8to16 x) for { v_0 := v.Args[0] if v_0.Op != OpZeroExt8to32 { break } x := v_0.Args[0] v.reset(OpZeroExt8to16) v.AddArg(x) return true } // match: (Trunc32to16 (ZeroExt16to32 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpZeroExt16to32 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc32to16 (SignExt8to32 x)) // cond: // result: (SignExt8to16 x) for { v_0 := v.Args[0] if v_0.Op != OpSignExt8to32 { break } x := v_0.Args[0] v.reset(OpSignExt8to16) v.AddArg(x) return true } // match: (Trunc32to16 (SignExt16to32 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpSignExt16to32 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc32to16 (And32 (Const32 [y]) x)) // cond: y&0xFFFF == 0xFFFF // result: (Trunc32to16 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } y := v_0_0.AuxInt if !(y&0xFFFF == 0xFFFF) { break } v.reset(OpTrunc32to16) v.AddArg(x) return true } // match: (Trunc32to16 (And32 x (Const32 [y]))) // cond: y&0xFFFF == 0xFFFF // result: (Trunc32to16 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } y := v_0_1.AuxInt if !(y&0xFFFF == 0xFFFF) { break } v.reset(OpTrunc32to16) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpTrunc32to8_0(v *Value) bool { // match: (Trunc32to8 (Const32 [c])) // cond: // result: (Const8 [int64(int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c)) return true } // match: (Trunc32to8 (ZeroExt8to32 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpZeroExt8to32 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc32to8 (SignExt8to32 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpSignExt8to32 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc32to8 (And32 (Const32 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc32to8 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } y := v_0_0.AuxInt if !(y&0xFF == 0xFF) { break } v.reset(OpTrunc32to8) v.AddArg(x) return true } // match: (Trunc32to8 (And32 x (Const32 [y]))) // cond: y&0xFF == 0xFF // result: (Trunc32to8 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } y := v_0_1.AuxInt if !(y&0xFF == 0xFF) { break } v.reset(OpTrunc32to8) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpTrunc64to16_0(v *Value) bool { // match: (Trunc64to16 (Const64 [c])) // cond: // result: (Const16 [int64(int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c)) return true } // match: (Trunc64to16 (ZeroExt8to64 x)) // cond: // result: (ZeroExt8to16 x) for { v_0 := v.Args[0] if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpZeroExt8to16) v.AddArg(x) return true } // match: (Trunc64to16 (ZeroExt16to64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpZeroExt16to64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc64to16 (SignExt8to64 x)) // cond: // result: (SignExt8to16 x) for { v_0 := v.Args[0] if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpSignExt8to16) v.AddArg(x) return true } // match: (Trunc64to16 (SignExt16to64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpSignExt16to64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc64to16 (And64 (Const64 [y]) x)) // cond: y&0xFFFF == 0xFFFF // result: (Trunc64to16 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } y := v_0_0.AuxInt if !(y&0xFFFF == 0xFFFF) { break } v.reset(OpTrunc64to16) v.AddArg(x) return true } // match: (Trunc64to16 (And64 x (Const64 [y]))) // cond: y&0xFFFF == 0xFFFF // result: (Trunc64to16 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } y := v_0_1.AuxInt if !(y&0xFFFF == 0xFFFF) { break } v.reset(OpTrunc64to16) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpTrunc64to32_0(v *Value) bool { // match: (Trunc64to32 (Const64 [c])) // cond: // result: (Const32 [int64(int32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c)) return true } // match: (Trunc64to32 (ZeroExt8to64 x)) // cond: // result: (ZeroExt8to32 x) for { v_0 := v.Args[0] if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpZeroExt8to32) v.AddArg(x) return true } // match: (Trunc64to32 (ZeroExt16to64 x)) // cond: // result: (ZeroExt16to32 x) for { v_0 := v.Args[0] if v_0.Op != OpZeroExt16to64 { break } x := v_0.Args[0] v.reset(OpZeroExt16to32) v.AddArg(x) return true } // match: (Trunc64to32 (ZeroExt32to64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpZeroExt32to64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc64to32 (SignExt8to64 x)) // cond: // result: (SignExt8to32 x) for { v_0 := v.Args[0] if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpSignExt8to32) v.AddArg(x) return true } // match: (Trunc64to32 (SignExt16to64 x)) // cond: // result: (SignExt16to32 x) for { v_0 := v.Args[0] if v_0.Op != OpSignExt16to64 { break } x := v_0.Args[0] v.reset(OpSignExt16to32) v.AddArg(x) return true } // match: (Trunc64to32 (SignExt32to64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpSignExt32to64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc64to32 (And64 (Const64 [y]) x)) // cond: y&0xFFFFFFFF == 0xFFFFFFFF // result: (Trunc64to32 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } y := v_0_0.AuxInt if !(y&0xFFFFFFFF == 0xFFFFFFFF) { break } v.reset(OpTrunc64to32) v.AddArg(x) return true } // match: (Trunc64to32 (And64 x (Const64 [y]))) // cond: y&0xFFFFFFFF == 0xFFFFFFFF // result: (Trunc64to32 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } y := v_0_1.AuxInt if !(y&0xFFFFFFFF == 0xFFFFFFFF) { break } v.reset(OpTrunc64to32) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpTrunc64to8_0(v *Value) bool { // match: (Trunc64to8 (Const64 [c])) // cond: // result: (Const8 [int64(int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c)) return true } // match: (Trunc64to8 (ZeroExt8to64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc64to8 (SignExt8to64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc64to8 (And64 (Const64 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc64to8 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } y := v_0_0.AuxInt if !(y&0xFF == 0xFF) { break } v.reset(OpTrunc64to8) v.AddArg(x) return true } // match: (Trunc64to8 (And64 x (Const64 [y]))) // cond: y&0xFF == 0xFF // result: (Trunc64to8 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } y := v_0_1.AuxInt if !(y&0xFF == 0xFF) { break } v.reset(OpTrunc64to8) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpXor16_0(v *Value) bool { b := v.Block // match: (Xor16 (Const16 [c]) (Const16 [d])) // cond: // result: (Const16 [int64(int16(c^d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c ^ d)) return true } // match: (Xor16 (Const16 [d]) (Const16 [c])) // cond: // result: (Const16 [int64(int16(c^d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c ^ d)) return true } // match: (Xor16 x x) // cond: // result: (Const16 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Xor16 (Const16 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor16 x (Const16 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor16 x (Xor16 x y)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor16 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor16 x (Xor16 y x)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor16 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor16 (Xor16 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor16 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor16 (Xor16 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor16 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor16 (Xor16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Xor16 i (Xor16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpXor16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpXor16_10(v *Value) bool { b := v.Block // match: (Xor16 (Xor16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Xor16 i (Xor16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor16 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpXor16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor16 x (Xor16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Xor16 i (Xor16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpXor16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor16 x (Xor16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Xor16 i (Xor16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpXor16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor16 (Const16 [c]) (Xor16 (Const16 [d]) x)) // cond: // result: (Xor16 (Const16 [int64(int16(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor16 (Const16 [c]) (Xor16 x (Const16 [d]))) // cond: // result: (Xor16 (Const16 [int64(int16(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor16 (Xor16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Xor16 (Const16 [int64(int16(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor16 (Xor16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Xor16 (Const16 [int64(int16(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpXor32_0(v *Value) bool { b := v.Block // match: (Xor32 (Const32 [c]) (Const32 [d])) // cond: // result: (Const32 [int64(int32(c^d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c ^ d)) return true } // match: (Xor32 (Const32 [d]) (Const32 [c])) // cond: // result: (Const32 [int64(int32(c^d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c ^ d)) return true } // match: (Xor32 x x) // cond: // result: (Const32 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Xor32 (Const32 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor32 x (Const32 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor32 x (Xor32 x y)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor32 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor32 x (Xor32 y x)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor32 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor32 (Xor32 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor32 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor32 (Xor32 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor32 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor32 (Xor32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Xor32 i (Xor32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpXor32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpXor32_10(v *Value) bool { b := v.Block // match: (Xor32 (Xor32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Xor32 i (Xor32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor32 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpXor32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor32 x (Xor32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Xor32 i (Xor32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpXor32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor32 x (Xor32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Xor32 i (Xor32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpXor32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor32 (Const32 [c]) (Xor32 (Const32 [d]) x)) // cond: // result: (Xor32 (Const32 [int64(int32(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor32 (Const32 [c]) (Xor32 x (Const32 [d]))) // cond: // result: (Xor32 (Const32 [int64(int32(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor32 (Xor32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Xor32 (Const32 [int64(int32(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor32 (Xor32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Xor32 (Const32 [int64(int32(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpXor64_0(v *Value) bool { b := v.Block // match: (Xor64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c^d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c ^ d return true } // match: (Xor64 (Const64 [d]) (Const64 [c])) // cond: // result: (Const64 [c^d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c ^ d return true } // match: (Xor64 x x) // cond: // result: (Const64 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Xor64 (Const64 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor64 x (Xor64 x y)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor64 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor64 x (Xor64 y x)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor64 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor64 (Xor64 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor64 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor64 (Xor64 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor64 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor64 (Xor64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Xor64 i (Xor64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpXor64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpXor64_10(v *Value) bool { b := v.Block // match: (Xor64 (Xor64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Xor64 i (Xor64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor64 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpXor64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor64 x (Xor64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Xor64 i (Xor64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpXor64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor64 x (Xor64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Xor64 i (Xor64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpXor64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor64 (Const64 [c]) (Xor64 (Const64 [d]) x)) // cond: // result: (Xor64 (Const64 [c^d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c ^ d v.AddArg(v0) v.AddArg(x) return true } // match: (Xor64 (Const64 [c]) (Xor64 x (Const64 [d]))) // cond: // result: (Xor64 (Const64 [c^d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c ^ d v.AddArg(v0) v.AddArg(x) return true } // match: (Xor64 (Xor64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Xor64 (Const64 [c^d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c ^ d v.AddArg(v0) v.AddArg(x) return true } // match: (Xor64 (Xor64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Xor64 (Const64 [c^d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c ^ d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpXor8_0(v *Value) bool { b := v.Block // match: (Xor8 (Const8 [c]) (Const8 [d])) // cond: // result: (Const8 [int64(int8(c^d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c ^ d)) return true } // match: (Xor8 (Const8 [d]) (Const8 [c])) // cond: // result: (Const8 [int64(int8(c^d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c ^ d)) return true } // match: (Xor8 x x) // cond: // result: (Const8 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Xor8 (Const8 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor8 x (Const8 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor8 x (Xor8 x y)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor8 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor8 x (Xor8 y x)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor8 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor8 (Xor8 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor8 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor8 (Xor8 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor8 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor8 (Xor8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Xor8 i (Xor8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpXor8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpXor8_10(v *Value) bool { b := v.Block // match: (Xor8 (Xor8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Xor8 i (Xor8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor8 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpXor8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor8 x (Xor8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Xor8 i (Xor8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpXor8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor8 x (Xor8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Xor8 i (Xor8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpXor8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor8 (Const8 [c]) (Xor8 (Const8 [d]) x)) // cond: // result: (Xor8 (Const8 [int64(int8(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor8 (Const8 [c]) (Xor8 x (Const8 [d]))) // cond: // result: (Xor8 (Const8 [int64(int8(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor8 (Xor8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Xor8 (Const8 [int64(int8(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor8 (Xor8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Xor8 (Const8 [int64(int8(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpZero_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (Zero (Load (OffPtr [c] (SP)) mem) mem) // cond: mem.Op == OpStaticCall && isSameSym(mem.Aux, "runtime.newobject") && c == config.ctxt.FixedFrameSize() + config.RegSize // result: mem for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLoad { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpOffPtr { break } c := v_0_0.AuxInt v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpSP { break } if mem != v_0.Args[1] { break } if !(mem.Op == OpStaticCall && isSameSym(mem.Aux, "runtime.newobject") && c == config.ctxt.FixedFrameSize()+config.RegSize) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Zero {t1} [n] p1 store:(Store {t2} (OffPtr [o2] p2) _ mem)) // cond: isSamePtr(p1, p2) && store.Uses == 1 && n >= o2 + sizeof(t2) && clobber(store) // result: (Zero {t1} [n] p1 mem) for { n := v.AuxInt t1 := v.Aux _ = v.Args[1] p1 := v.Args[0] store := v.Args[1] if store.Op != OpStore { break } t2 := store.Aux mem := store.Args[2] store_0 := store.Args[0] if store_0.Op != OpOffPtr { break } o2 := store_0.AuxInt p2 := store_0.Args[0] if !(isSamePtr(p1, p2) && store.Uses == 1 && n >= o2+sizeof(t2) && clobber(store)) { break } v.reset(OpZero) v.AuxInt = n v.Aux = t1 v.AddArg(p1) v.AddArg(mem) return true } // match: (Zero {t} [n] dst1 move:(Move {t} [n] dst2 _ mem)) // cond: move.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move) // result: (Zero {t} [n] dst1 mem) for { n := v.AuxInt t := v.Aux _ = v.Args[1] dst1 := v.Args[0] move := v.Args[1] if move.Op != OpMove { break } if move.AuxInt != n { break } if move.Aux != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move)) { break } v.reset(OpZero) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(mem) return true } // match: (Zero {t} [n] dst1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem))) // cond: move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move) && clobber(vardef) // result: (Zero {t} [n] dst1 (VarDef {x} mem)) for { n := v.AuxInt t := v.Aux _ = v.Args[1] dst1 := v.Args[0] vardef := v.Args[1] if vardef.Op != OpVarDef { break } x := vardef.Aux move := vardef.Args[0] if move.Op != OpMove { break } if move.AuxInt != n { break } if move.Aux != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move) && clobber(vardef)) { break } v.reset(OpZero) v.AuxInt = n v.Aux = t v.AddArg(dst1) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = x v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpZeroExt16to32_0(v *Value) bool { // match: (ZeroExt16to32 (Const16 [c])) // cond: // result: (Const32 [int64(uint16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(uint16(c)) return true } // match: (ZeroExt16to32 (Trunc32to16 x:(Rsh32Ux64 _ (Const64 [s])))) // cond: s >= 16 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc32to16 { break } x := v_0.Args[0] if x.Op != OpRsh32Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 16) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpZeroExt16to64_0(v *Value) bool { // match: (ZeroExt16to64 (Const16 [c])) // cond: // result: (Const64 [int64(uint16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(uint16(c)) return true } // match: (ZeroExt16to64 (Trunc64to16 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 48 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc64to16 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 48) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpZeroExt32to64_0(v *Value) bool { // match: (ZeroExt32to64 (Const32 [c])) // cond: // result: (Const64 [int64(uint32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(uint32(c)) return true } // match: (ZeroExt32to64 (Trunc64to32 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 32 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc64to32 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 32) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to16_0(v *Value) bool { // match: (ZeroExt8to16 (Const8 [c])) // cond: // result: (Const16 [int64( uint8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst16) v.AuxInt = int64(uint8(c)) return true } // match: (ZeroExt8to16 (Trunc16to8 x:(Rsh16Ux64 _ (Const64 [s])))) // cond: s >= 8 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc16to8 { break } x := v_0.Args[0] if x.Op != OpRsh16Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 8) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to32_0(v *Value) bool { // match: (ZeroExt8to32 (Const8 [c])) // cond: // result: (Const32 [int64( uint8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(uint8(c)) return true } // match: (ZeroExt8to32 (Trunc32to8 x:(Rsh32Ux64 _ (Const64 [s])))) // cond: s >= 24 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc32to8 { break } x := v_0.Args[0] if x.Op != OpRsh32Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 24) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to64_0(v *Value) bool { // match: (ZeroExt8to64 (Const8 [c])) // cond: // result: (Const64 [int64( uint8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(uint8(c)) return true } // match: (ZeroExt8to64 (Trunc64to8 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 56 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc64to8 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 56) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteBlockgeneric(b *Block) bool { config := b.Func.Config typ := &config.Types _ = typ v := b.Control _ = v switch b.Kind { case BlockIf: // match: (If (Not cond) yes no) // cond: // result: (If cond no yes) for v.Op == OpNot { cond := v.Args[0] b.Kind = BlockIf b.SetControl(cond) b.Aux = nil b.swapSuccessors() return true } // match: (If (ConstBool [c]) yes no) // cond: c == 1 // result: (First nil yes no) for v.Op == OpConstBool { c := v.AuxInt if !(c == 1) { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (If (ConstBool [c]) yes no) // cond: c == 0 // result: (First nil no yes) for v.Op == OpConstBool { c := v.AuxInt if !(c == 0) { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } } return false } -- y -- // Code generated from gen/generic.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "fmt" import "math" import "cmd/internal/obj" import "cmd/internal/objabi" import "cmd/compile/internal/types" var _ = fmt.Println // in case not otherwise used var _ = math.MinInt8 // in case not otherwise used var _ = obj.ANOP // in case not otherwise used var _ = objabi.GOROOT // in case not otherwise used var _ = types.TypeMem // in case not otherwise used func rewriteValuegeneric(v *Value) bool { switch v.Op { case OpAdd16: return rewriteValuegeneric_OpAdd16_0(v) || rewriteValuegeneric_OpAdd16_10(v) || rewriteValuegeneric_OpAdd16_20(v) || rewriteValuegeneric_OpAdd16_30(v) case OpAdd32: return rewriteValuegeneric_OpAdd32_0(v) || rewriteValuegeneric_OpAdd32_10(v) || rewriteValuegeneric_OpAdd32_20(v) || rewriteValuegeneric_OpAdd32_30(v) case OpAdd32F: return rewriteValuegeneric_OpAdd32F_0(v) case OpAdd64: return rewriteValuegeneric_OpAdd64_0(v) || rewriteValuegeneric_OpAdd64_10(v) || rewriteValuegeneric_OpAdd64_20(v) || rewriteValuegeneric_OpAdd64_30(v) case OpAdd64F: return rewriteValuegeneric_OpAdd64F_0(v) case OpAdd8: return rewriteValuegeneric_OpAdd8_0(v) || rewriteValuegeneric_OpAdd8_10(v) || rewriteValuegeneric_OpAdd8_20(v) || rewriteValuegeneric_OpAdd8_30(v) case OpAddPtr: return rewriteValuegeneric_OpAddPtr_0(v) case OpAnd16: return rewriteValuegeneric_OpAnd16_0(v) || rewriteValuegeneric_OpAnd16_10(v) || rewriteValuegeneric_OpAnd16_20(v) case OpAnd32: return rewriteValuegeneric_OpAnd32_0(v) || rewriteValuegeneric_OpAnd32_10(v) || rewriteValuegeneric_OpAnd32_20(v) case OpAnd64: return rewriteValuegeneric_OpAnd64_0(v) || rewriteValuegeneric_OpAnd64_10(v) || rewriteValuegeneric_OpAnd64_20(v) case OpAnd8: return rewriteValuegeneric_OpAnd8_0(v) || rewriteValuegeneric_OpAnd8_10(v) || rewriteValuegeneric_OpAnd8_20(v) case OpArraySelect: return rewriteValuegeneric_OpArraySelect_0(v) case OpCom16: return rewriteValuegeneric_OpCom16_0(v) case OpCom32: return rewriteValuegeneric_OpCom32_0(v) case OpCom64: return rewriteValuegeneric_OpCom64_0(v) case OpCom8: return rewriteValuegeneric_OpCom8_0(v) case OpConstInterface: return rewriteValuegeneric_OpConstInterface_0(v) case OpConstSlice: return rewriteValuegeneric_OpConstSlice_0(v) case OpConstString: return rewriteValuegeneric_OpConstString_0(v) case OpConvert: return rewriteValuegeneric_OpConvert_0(v) case OpCvt32Fto32: return rewriteValuegeneric_OpCvt32Fto32_0(v) case OpCvt32Fto64: return rewriteValuegeneric_OpCvt32Fto64_0(v) case OpCvt32Fto64F: return rewriteValuegeneric_OpCvt32Fto64F_0(v) case OpCvt32to32F: return rewriteValuegeneric_OpCvt32to32F_0(v) case OpCvt32to64F: return rewriteValuegeneric_OpCvt32to64F_0(v) case OpCvt64Fto32: return rewriteValuegeneric_OpCvt64Fto32_0(v) case OpCvt64Fto32F: return rewriteValuegeneric_OpCvt64Fto32F_0(v) case OpCvt64Fto64: return rewriteValuegeneric_OpCvt64Fto64_0(v) case OpCvt64to32F: return rewriteValuegeneric_OpCvt64to32F_0(v) case OpCvt64to64F: return rewriteValuegeneric_OpCvt64to64F_0(v) case OpDiv16: return rewriteValuegeneric_OpDiv16_0(v) case OpDiv16u: return rewriteValuegeneric_OpDiv16u_0(v) case OpDiv32: return rewriteValuegeneric_OpDiv32_0(v) case OpDiv32F: return rewriteValuegeneric_OpDiv32F_0(v) case OpDiv32u: return rewriteValuegeneric_OpDiv32u_0(v) case OpDiv64: return rewriteValuegeneric_OpDiv64_0(v) case OpDiv64F: return rewriteValuegeneric_OpDiv64F_0(v) case OpDiv64u: return rewriteValuegeneric_OpDiv64u_0(v) case OpDiv8: return rewriteValuegeneric_OpDiv8_0(v) case OpDiv8u: return rewriteValuegeneric_OpDiv8u_0(v) case OpEq16: return rewriteValuegeneric_OpEq16_0(v) || rewriteValuegeneric_OpEq16_10(v) || rewriteValuegeneric_OpEq16_20(v) || rewriteValuegeneric_OpEq16_30(v) || rewriteValuegeneric_OpEq16_40(v) || rewriteValuegeneric_OpEq16_50(v) case OpEq32: return rewriteValuegeneric_OpEq32_0(v) || rewriteValuegeneric_OpEq32_10(v) || rewriteValuegeneric_OpEq32_20(v) || rewriteValuegeneric_OpEq32_30(v) || rewriteValuegeneric_OpEq32_40(v) || rewriteValuegeneric_OpEq32_50(v) || rewriteValuegeneric_OpEq32_60(v) || rewriteValuegeneric_OpEq32_70(v) || rewriteValuegeneric_OpEq32_80(v) || rewriteValuegeneric_OpEq32_90(v) case OpEq32F: return rewriteValuegeneric_OpEq32F_0(v) case OpEq64: return rewriteValuegeneric_OpEq64_0(v) || rewriteValuegeneric_OpEq64_10(v) || rewriteValuegeneric_OpEq64_20(v) || rewriteValuegeneric_OpEq64_30(v) || rewriteValuegeneric_OpEq64_40(v) || rewriteValuegeneric_OpEq64_50(v) || rewriteValuegeneric_OpEq64_60(v) case OpEq64F: return rewriteValuegeneric_OpEq64F_0(v) case OpEq8: return rewriteValuegeneric_OpEq8_0(v) || rewriteValuegeneric_OpEq8_10(v) || rewriteValuegeneric_OpEq8_20(v) || rewriteValuegeneric_OpEq8_30(v) case OpEqB: return rewriteValuegeneric_OpEqB_0(v) case OpEqInter: return rewriteValuegeneric_OpEqInter_0(v) case OpEqPtr: return rewriteValuegeneric_OpEqPtr_0(v) || rewriteValuegeneric_OpEqPtr_10(v) || rewriteValuegeneric_OpEqPtr_20(v) case OpEqSlice: return rewriteValuegeneric_OpEqSlice_0(v) case OpGeq16: return rewriteValuegeneric_OpGeq16_0(v) case OpGeq16U: return rewriteValuegeneric_OpGeq16U_0(v) case OpGeq32: return rewriteValuegeneric_OpGeq32_0(v) case OpGeq32F: return rewriteValuegeneric_OpGeq32F_0(v) case OpGeq32U: return rewriteValuegeneric_OpGeq32U_0(v) case OpGeq64: return rewriteValuegeneric_OpGeq64_0(v) case OpGeq64F: return rewriteValuegeneric_OpGeq64F_0(v) case OpGeq64U: return rewriteValuegeneric_OpGeq64U_0(v) case OpGeq8: return rewriteValuegeneric_OpGeq8_0(v) case OpGeq8U: return rewriteValuegeneric_OpGeq8U_0(v) case OpGreater16: return rewriteValuegeneric_OpGreater16_0(v) case OpGreater16U: return rewriteValuegeneric_OpGreater16U_0(v) case OpGreater32: return rewriteValuegeneric_OpGreater32_0(v) case OpGreater32F: return rewriteValuegeneric_OpGreater32F_0(v) case OpGreater32U: return rewriteValuegeneric_OpGreater32U_0(v) case OpGreater64: return rewriteValuegeneric_OpGreater64_0(v) case OpGreater64F: return rewriteValuegeneric_OpGreater64F_0(v) case OpGreater64U: return rewriteValuegeneric_OpGreater64U_0(v) case OpGreater8: return rewriteValuegeneric_OpGreater8_0(v) case OpGreater8U: return rewriteValuegeneric_OpGreater8U_0(v) case OpIMake: return rewriteValuegeneric_OpIMake_0(v) case OpInterCall: return rewriteValuegeneric_OpInterCall_0(v) case OpIsInBounds: return rewriteValuegeneric_OpIsInBounds_0(v) || rewriteValuegeneric_OpIsInBounds_10(v) || rewriteValuegeneric_OpIsInBounds_20(v) || rewriteValuegeneric_OpIsInBounds_30(v) case OpIsNonNil: return rewriteValuegeneric_OpIsNonNil_0(v) case OpIsSliceInBounds: return rewriteValuegeneric_OpIsSliceInBounds_0(v) case OpLeq16: return rewriteValuegeneric_OpLeq16_0(v) case OpLeq16U: return rewriteValuegeneric_OpLeq16U_0(v) case OpLeq32: return rewriteValuegeneric_OpLeq32_0(v) case OpLeq32F: return rewriteValuegeneric_OpLeq32F_0(v) case OpLeq32U: return rewriteValuegeneric_OpLeq32U_0(v) case OpLeq64: return rewriteValuegeneric_OpLeq64_0(v) case OpLeq64F: return rewriteValuegeneric_OpLeq64F_0(v) case OpLeq64U: return rewriteValuegeneric_OpLeq64U_0(v) case OpLeq8: return rewriteValuegeneric_OpLeq8_0(v) case OpLeq8U: return rewriteValuegeneric_OpLeq8U_0(v) case OpLess16: return rewriteValuegeneric_OpLess16_0(v) case OpLess16U: return rewriteValuegeneric_OpLess16U_0(v) case OpLess32: return rewriteValuegeneric_OpLess32_0(v) case OpLess32F: return rewriteValuegeneric_OpLess32F_0(v) case OpLess32U: return rewriteValuegeneric_OpLess32U_0(v) case OpLess64: return rewriteValuegeneric_OpLess64_0(v) case OpLess64F: return rewriteValuegeneric_OpLess64F_0(v) case OpLess64U: return rewriteValuegeneric_OpLess64U_0(v) case OpLess8: return rewriteValuegeneric_OpLess8_0(v) case OpLess8U: return rewriteValuegeneric_OpLess8U_0(v) case OpLoad: return rewriteValuegeneric_OpLoad_0(v) || rewriteValuegeneric_OpLoad_10(v) || rewriteValuegeneric_OpLoad_20(v) case OpLsh16x16: return rewriteValuegeneric_OpLsh16x16_0(v) case OpLsh16x32: return rewriteValuegeneric_OpLsh16x32_0(v) case OpLsh16x64: return rewriteValuegeneric_OpLsh16x64_0(v) case OpLsh16x8: return rewriteValuegeneric_OpLsh16x8_0(v) case OpLsh32x16: return rewriteValuegeneric_OpLsh32x16_0(v) case OpLsh32x32: return rewriteValuegeneric_OpLsh32x32_0(v) case OpLsh32x64: return rewriteValuegeneric_OpLsh32x64_0(v) case OpLsh32x8: return rewriteValuegeneric_OpLsh32x8_0(v) case OpLsh64x16: return rewriteValuegeneric_OpLsh64x16_0(v) case OpLsh64x32: return rewriteValuegeneric_OpLsh64x32_0(v) case OpLsh64x64: return rewriteValuegeneric_OpLsh64x64_0(v) case OpLsh64x8: return rewriteValuegeneric_OpLsh64x8_0(v) case OpLsh8x16: return rewriteValuegeneric_OpLsh8x16_0(v) case OpLsh8x32: return rewriteValuegeneric_OpLsh8x32_0(v) case OpLsh8x64: return rewriteValuegeneric_OpLsh8x64_0(v) case OpLsh8x8: return rewriteValuegeneric_OpLsh8x8_0(v) case OpMod16: return rewriteValuegeneric_OpMod16_0(v) case OpMod16u: return rewriteValuegeneric_OpMod16u_0(v) case OpMod32: return rewriteValuegeneric_OpMod32_0(v) case OpMod32u: return rewriteValuegeneric_OpMod32u_0(v) case OpMod64: return rewriteValuegeneric_OpMod64_0(v) case OpMod64u: return rewriteValuegeneric_OpMod64u_0(v) case OpMod8: return rewriteValuegeneric_OpMod8_0(v) case OpMod8u: return rewriteValuegeneric_OpMod8u_0(v) case OpMove: return rewriteValuegeneric_OpMove_0(v) || rewriteValuegeneric_OpMove_10(v) || rewriteValuegeneric_OpMove_20(v) case OpMul16: return rewriteValuegeneric_OpMul16_0(v) || rewriteValuegeneric_OpMul16_10(v) case OpMul32: return rewriteValuegeneric_OpMul32_0(v) || rewriteValuegeneric_OpMul32_10(v) case OpMul32F: return rewriteValuegeneric_OpMul32F_0(v) case OpMul64: return rewriteValuegeneric_OpMul64_0(v) || rewriteValuegeneric_OpMul64_10(v) case OpMul64F: return rewriteValuegeneric_OpMul64F_0(v) case OpMul8: return rewriteValuegeneric_OpMul8_0(v) || rewriteValuegeneric_OpMul8_10(v) case OpNeg16: return rewriteValuegeneric_OpNeg16_0(v) case OpNeg32: return rewriteValuegeneric_OpNeg32_0(v) case OpNeg32F: return rewriteValuegeneric_OpNeg32F_0(v) case OpNeg64: return rewriteValuegeneric_OpNeg64_0(v) case OpNeg64F: return rewriteValuegeneric_OpNeg64F_0(v) case OpNeg8: return rewriteValuegeneric_OpNeg8_0(v) case OpNeq16: return rewriteValuegeneric_OpNeq16_0(v) case OpNeq32: return rewriteValuegeneric_OpNeq32_0(v) case OpNeq32F: return rewriteValuegeneric_OpNeq32F_0(v) case OpNeq64: return rewriteValuegeneric_OpNeq64_0(v) case OpNeq64F: return rewriteValuegeneric_OpNeq64F_0(v) case OpNeq8: return rewriteValuegeneric_OpNeq8_0(v) case OpNeqB: return rewriteValuegeneric_OpNeqB_0(v) case OpNeqInter: return rewriteValuegeneric_OpNeqInter_0(v) case OpNeqPtr: return rewriteValuegeneric_OpNeqPtr_0(v) || rewriteValuegeneric_OpNeqPtr_10(v) || rewriteValuegeneric_OpNeqPtr_20(v) case OpNeqSlice: return rewriteValuegeneric_OpNeqSlice_0(v) case OpNilCheck: return rewriteValuegeneric_OpNilCheck_0(v) case OpNot: return rewriteValuegeneric_OpNot_0(v) || rewriteValuegeneric_OpNot_10(v) || rewriteValuegeneric_OpNot_20(v) || rewriteValuegeneric_OpNot_30(v) || rewriteValuegeneric_OpNot_40(v) case OpOffPtr: return rewriteValuegeneric_OpOffPtr_0(v) case OpOr16: return rewriteValuegeneric_OpOr16_0(v) || rewriteValuegeneric_OpOr16_10(v) || rewriteValuegeneric_OpOr16_20(v) case OpOr32: return rewriteValuegeneric_OpOr32_0(v) || rewriteValuegeneric_OpOr32_10(v) || rewriteValuegeneric_OpOr32_20(v) case OpOr64: return rewriteValuegeneric_OpOr64_0(v) || rewriteValuegeneric_OpOr64_10(v) || rewriteValuegeneric_OpOr64_20(v) case OpOr8: return rewriteValuegeneric_OpOr8_0(v) || rewriteValuegeneric_OpOr8_10(v) || rewriteValuegeneric_OpOr8_20(v) case OpPhi: return rewriteValuegeneric_OpPhi_0(v) case OpPtrIndex: return rewriteValuegeneric_OpPtrIndex_0(v) case OpRotateLeft16: return rewriteValuegeneric_OpRotateLeft16_0(v) case OpRotateLeft32: return rewriteValuegeneric_OpRotateLeft32_0(v) case OpRotateLeft64: return rewriteValuegeneric_OpRotateLeft64_0(v) case OpRotateLeft8: return rewriteValuegeneric_OpRotateLeft8_0(v) case OpRound32F: return rewriteValuegeneric_OpRound32F_0(v) case OpRound64F: return rewriteValuegeneric_OpRound64F_0(v) case OpRsh16Ux16: return rewriteValuegeneric_OpRsh16Ux16_0(v) case OpRsh16Ux32: return rewriteValuegeneric_OpRsh16Ux32_0(v) case OpRsh16Ux64: return rewriteValuegeneric_OpRsh16Ux64_0(v) case OpRsh16Ux8: return rewriteValuegeneric_OpRsh16Ux8_0(v) case OpRsh16x16: return rewriteValuegeneric_OpRsh16x16_0(v) case OpRsh16x32: return rewriteValuegeneric_OpRsh16x32_0(v) case OpRsh16x64: return rewriteValuegeneric_OpRsh16x64_0(v) case OpRsh16x8: return rewriteValuegeneric_OpRsh16x8_0(v) case OpRsh32Ux16: return rewriteValuegeneric_OpRsh32Ux16_0(v) case OpRsh32Ux32: return rewriteValuegeneric_OpRsh32Ux32_0(v) case OpRsh32Ux64: return rewriteValuegeneric_OpRsh32Ux64_0(v) case OpRsh32Ux8: return rewriteValuegeneric_OpRsh32Ux8_0(v) case OpRsh32x16: return rewriteValuegeneric_OpRsh32x16_0(v) case OpRsh32x32: return rewriteValuegeneric_OpRsh32x32_0(v) case OpRsh32x64: return rewriteValuegeneric_OpRsh32x64_0(v) case OpRsh32x8: return rewriteValuegeneric_OpRsh32x8_0(v) case OpRsh64Ux16: return rewriteValuegeneric_OpRsh64Ux16_0(v) case OpRsh64Ux32: return rewriteValuegeneric_OpRsh64Ux32_0(v) case OpRsh64Ux64: return rewriteValuegeneric_OpRsh64Ux64_0(v) case OpRsh64Ux8: return rewriteValuegeneric_OpRsh64Ux8_0(v) case OpRsh64x16: return rewriteValuegeneric_OpRsh64x16_0(v) case OpRsh64x32: return rewriteValuegeneric_OpRsh64x32_0(v) case OpRsh64x64: return rewriteValuegeneric_OpRsh64x64_0(v) case OpRsh64x8: return rewriteValuegeneric_OpRsh64x8_0(v) case OpRsh8Ux16: return rewriteValuegeneric_OpRsh8Ux16_0(v) case OpRsh8Ux32: return rewriteValuegeneric_OpRsh8Ux32_0(v) case OpRsh8Ux64: return rewriteValuegeneric_OpRsh8Ux64_0(v) case OpRsh8Ux8: return rewriteValuegeneric_OpRsh8Ux8_0(v) case OpRsh8x16: return rewriteValuegeneric_OpRsh8x16_0(v) case OpRsh8x32: return rewriteValuegeneric_OpRsh8x32_0(v) case OpRsh8x64: return rewriteValuegeneric_OpRsh8x64_0(v) case OpRsh8x8: return rewriteValuegeneric_OpRsh8x8_0(v) case OpSelect0: return rewriteValuegeneric_OpSelect0_0(v) case OpSelect1: return rewriteValuegeneric_OpSelect1_0(v) case OpSignExt16to32: return rewriteValuegeneric_OpSignExt16to32_0(v) case OpSignExt16to64: return rewriteValuegeneric_OpSignExt16to64_0(v) case OpSignExt32to64: return rewriteValuegeneric_OpSignExt32to64_0(v) case OpSignExt8to16: return rewriteValuegeneric_OpSignExt8to16_0(v) case OpSignExt8to32: return rewriteValuegeneric_OpSignExt8to32_0(v) case OpSignExt8to64: return rewriteValuegeneric_OpSignExt8to64_0(v) case OpSliceCap: return rewriteValuegeneric_OpSliceCap_0(v) case OpSliceLen: return rewriteValuegeneric_OpSliceLen_0(v) case OpSlicePtr: return rewriteValuegeneric_OpSlicePtr_0(v) case OpSlicemask: return rewriteValuegeneric_OpSlicemask_0(v) case OpSqrt: return rewriteValuegeneric_OpSqrt_0(v) case OpStaticCall: return rewriteValuegeneric_OpStaticCall_0(v) case OpStore: return rewriteValuegeneric_OpStore_0(v) || rewriteValuegeneric_OpStore_10(v) || rewriteValuegeneric_OpStore_20(v) case OpStringLen: return rewriteValuegeneric_OpStringLen_0(v) case OpStringPtr: return rewriteValuegeneric_OpStringPtr_0(v) case OpStructSelect: return rewriteValuegeneric_OpStructSelect_0(v) || rewriteValuegeneric_OpStructSelect_10(v) case OpSub16: return rewriteValuegeneric_OpSub16_0(v) || rewriteValuegeneric_OpSub16_10(v) case OpSub32: return rewriteValuegeneric_OpSub32_0(v) || rewriteValuegeneric_OpSub32_10(v) case OpSub32F: return rewriteValuegeneric_OpSub32F_0(v) case OpSub64: return rewriteValuegeneric_OpSub64_0(v) || rewriteValuegeneric_OpSub64_10(v) case OpSub64F: return rewriteValuegeneric_OpSub64F_0(v) case OpSub8: return rewriteValuegeneric_OpSub8_0(v) || rewriteValuegeneric_OpSub8_10(v) case OpTrunc16to8: return rewriteValuegeneric_OpTrunc16to8_0(v) case OpTrunc32to16: return rewriteValuegeneric_OpTrunc32to16_0(v) case OpTrunc32to8: return rewriteValuegeneric_OpTrunc32to8_0(v) case OpTrunc64to16: return rewriteValuegeneric_OpTrunc64to16_0(v) case OpTrunc64to32: return rewriteValuegeneric_OpTrunc64to32_0(v) case OpTrunc64to8: return rewriteValuegeneric_OpTrunc64to8_0(v) case OpXor16: return rewriteValuegeneric_OpXor16_0(v) || rewriteValuegeneric_OpXor16_10(v) case OpXor32: return rewriteValuegeneric_OpXor32_0(v) || rewriteValuegeneric_OpXor32_10(v) case OpXor64: return rewriteValuegeneric_OpXor64_0(v) || rewriteValuegeneric_OpXor64_10(v) case OpXor8: return rewriteValuegeneric_OpXor8_0(v) || rewriteValuegeneric_OpXor8_10(v) case OpZero: return rewriteValuegeneric_OpZero_0(v) case OpZeroExt16to32: return rewriteValuegeneric_OpZeroExt16to32_0(v) case OpZeroExt16to64: return rewriteValuegeneric_OpZeroExt16to64_0(v) case OpZeroExt32to64: return rewriteValuegeneric_OpZeroExt32to64_0(v) case OpZeroExt8to16: return rewriteValuegeneric_OpZeroExt8to16_0(v) case OpZeroExt8to32: return rewriteValuegeneric_OpZeroExt8to32_0(v) case OpZeroExt8to64: return rewriteValuegeneric_OpZeroExt8to64_0(v) } return false } func rewriteValuegeneric_OpAdd16_0(v *Value) bool { b := v.Block // match: (Add16 (Const16 [c]) (Const16 [d])) // cond: // result: (Const16 [int64(int16(c+d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c + d)) return true } // match: (Add16 (Const16 [d]) (Const16 [c])) // cond: // result: (Const16 [int64(int16(c+d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c + d)) return true } // match: (Add16 (Mul16 x y) (Mul16 x z)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 y x) (Mul16 x z)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 x y) (Mul16 z x)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 y x) (Mul16 z x)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 x z) (Mul16 x y)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 z x) (Mul16 x y)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 x z) (Mul16 y x)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Mul16 z x) (Mul16 y x)) // cond: // result: (Mul16 x (Add16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd16_10(v *Value) bool { b := v.Block // match: (Add16 (Const16 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add16 x (Const16 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add16 (Const16 [1]) (Com16 x)) // cond: // result: (Neg16 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpCom16 { break } x := v_1.Args[0] v.reset(OpNeg16) v.AddArg(x) return true } // match: (Add16 (Com16 x) (Const16 [1])) // cond: // result: (Neg16 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpCom16 { break } x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 1 { break } v.reset(OpNeg16) v.AddArg(x) return true } // match: (Add16 (Add16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Add16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add16 (Add16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Add16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add16 x (Add16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Add16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add16 x (Add16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Add16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add16 (Sub16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 x (Sub16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd16_20(v *Value) bool { b := v.Block // match: (Add16 x (Sub16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Sub16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add16 (Sub16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub16 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add16 x (Sub16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add16 x (Sub16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add16 (Sub16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub16 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add16 (Const16 [c]) (Add16 (Const16 [d]) x)) // cond: // result: (Add16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add16 (Const16 [c]) (Add16 x (Const16 [d]))) // cond: // result: (Add16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add16 (Add16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Add16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add16 (Add16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Add16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd16_30(v *Value) bool { b := v.Block // match: (Add16 (Const16 [c]) (Sub16 (Const16 [d]) x)) // cond: // result: (Sub16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add16 (Sub16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Sub16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add16 (Const16 [c]) (Sub16 x (Const16 [d]))) // cond: // result: (Add16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add16 (Sub16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Add16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd32_0(v *Value) bool { b := v.Block // match: (Add32 (Const32 [c]) (Const32 [d])) // cond: // result: (Const32 [int64(int32(c+d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c + d)) return true } // match: (Add32 (Const32 [d]) (Const32 [c])) // cond: // result: (Const32 [int64(int32(c+d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c + d)) return true } // match: (Add32 (Mul32 x y) (Mul32 x z)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 y x) (Mul32 x z)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 x y) (Mul32 z x)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 y x) (Mul32 z x)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 x z) (Mul32 x y)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 z x) (Mul32 x y)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 x z) (Mul32 y x)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Mul32 z x) (Mul32 y x)) // cond: // result: (Mul32 x (Add32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd32_10(v *Value) bool { b := v.Block // match: (Add32 (Const32 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add32 x (Const32 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add32 (Const32 [1]) (Com32 x)) // cond: // result: (Neg32 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpCom32 { break } x := v_1.Args[0] v.reset(OpNeg32) v.AddArg(x) return true } // match: (Add32 (Com32 x) (Const32 [1])) // cond: // result: (Neg32 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpCom32 { break } x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 1 { break } v.reset(OpNeg32) v.AddArg(x) return true } // match: (Add32 (Add32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Add32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add32 (Add32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Add32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add32 x (Add32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Add32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add32 x (Add32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Add32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add32 (Sub32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 x (Sub32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd32_20(v *Value) bool { b := v.Block // match: (Add32 x (Sub32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Sub32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add32 (Sub32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub32 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add32 x (Sub32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add32 x (Sub32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add32 (Sub32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub32 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add32 (Const32 [c]) (Add32 (Const32 [d]) x)) // cond: // result: (Add32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add32 (Const32 [c]) (Add32 x (Const32 [d]))) // cond: // result: (Add32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add32 (Add32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Add32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add32 (Add32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Add32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd32_30(v *Value) bool { b := v.Block // match: (Add32 (Const32 [c]) (Sub32 (Const32 [d]) x)) // cond: // result: (Sub32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add32 (Sub32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Sub32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add32 (Const32 [c]) (Sub32 x (Const32 [d]))) // cond: // result: (Add32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add32 (Sub32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Add32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd32F_0(v *Value) bool { // match: (Add32F (Const32F [c]) (Const32F [d])) // cond: // result: (Const32F [auxFrom32F(auxTo32F(c) + auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(auxTo32F(c) + auxTo32F(d)) return true } // match: (Add32F (Const32F [d]) (Const32F [c])) // cond: // result: (Const32F [auxFrom32F(auxTo32F(c) + auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } c := v_1.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(auxTo32F(c) + auxTo32F(d)) return true } return false } func rewriteValuegeneric_OpAdd64_0(v *Value) bool { b := v.Block // match: (Add64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c+d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c + d return true } // match: (Add64 (Const64 [d]) (Const64 [c])) // cond: // result: (Const64 [c+d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c + d return true } // match: (Add64 (Mul64 x y) (Mul64 x z)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 y x) (Mul64 x z)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 x y) (Mul64 z x)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 y x) (Mul64 z x)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 x z) (Mul64 x y)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 z x) (Mul64 x y)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 x z) (Mul64 y x)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Mul64 z x) (Mul64 y x)) // cond: // result: (Mul64 x (Add64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd64_10(v *Value) bool { b := v.Block // match: (Add64 (Const64 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add64 (Const64 [1]) (Com64 x)) // cond: // result: (Neg64 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpCom64 { break } x := v_1.Args[0] v.reset(OpNeg64) v.AddArg(x) return true } // match: (Add64 (Com64 x) (Const64 [1])) // cond: // result: (Neg64 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpCom64 { break } x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 1 { break } v.reset(OpNeg64) v.AddArg(x) return true } // match: (Add64 (Add64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Add64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add64 (Add64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Add64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add64 x (Add64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Add64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add64 x (Add64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Add64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add64 (Sub64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 x (Sub64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd64_20(v *Value) bool { b := v.Block // match: (Add64 x (Sub64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Sub64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add64 (Sub64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub64 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add64 x (Sub64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add64 x (Sub64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add64 (Sub64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub64 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add64 (Const64 [c]) (Add64 (Const64 [d]) x)) // cond: // result: (Add64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } // match: (Add64 (Const64 [c]) (Add64 x (Const64 [d]))) // cond: // result: (Add64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } // match: (Add64 (Add64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Add64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } // match: (Add64 (Add64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Add64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd64_30(v *Value) bool { b := v.Block // match: (Add64 (Const64 [c]) (Sub64 (Const64 [d]) x)) // cond: // result: (Sub64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } // match: (Add64 (Sub64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Sub64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } // match: (Add64 (Const64 [c]) (Sub64 x (Const64 [d]))) // cond: // result: (Add64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Add64 (Sub64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Add64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd64F_0(v *Value) bool { // match: (Add64F (Const64F [c]) (Const64F [d])) // cond: // result: (Const64F [auxFrom64F(auxTo64F(c) + auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(auxTo64F(c) + auxTo64F(d)) return true } // match: (Add64F (Const64F [d]) (Const64F [c])) // cond: // result: (Const64F [auxFrom64F(auxTo64F(c) + auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } c := v_1.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(auxTo64F(c) + auxTo64F(d)) return true } return false } func rewriteValuegeneric_OpAdd8_0(v *Value) bool { b := v.Block // match: (Add8 (Const8 [c]) (Const8 [d])) // cond: // result: (Const8 [int64(int8(c+d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c + d)) return true } // match: (Add8 (Const8 [d]) (Const8 [c])) // cond: // result: (Const8 [int64(int8(c+d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c + d)) return true } // match: (Add8 (Mul8 x y) (Mul8 x z)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 y x) (Mul8 x z)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 x y) (Mul8 z x)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 y x) (Mul8 z x)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 x z) (Mul8 x y)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 z x) (Mul8 x y)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 x z) (Mul8 y x)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } z := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Mul8 z x) (Mul8 y x)) // cond: // result: (Mul8 x (Add8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] z := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd8_10(v *Value) bool { b := v.Block // match: (Add8 (Const8 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add8 x (Const8 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Add8 (Const8 [1]) (Com8 x)) // cond: // result: (Neg8 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpCom8 { break } x := v_1.Args[0] v.reset(OpNeg8) v.AddArg(x) return true } // match: (Add8 (Com8 x) (Const8 [1])) // cond: // result: (Neg8 x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpCom8 { break } x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 1 { break } v.reset(OpNeg8) v.AddArg(x) return true } // match: (Add8 (Add8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Add8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add8 (Add8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Add8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add8 x (Add8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Add8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add8 x (Add8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Add8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Add8 (Sub8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 x (Sub8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAdd8_20(v *Value) bool { b := v.Block // match: (Add8 x (Sub8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Sub8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Add8 (Sub8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub8 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add8 x (Sub8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add8 x (Sub8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add8 (Sub8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub8 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Add8 (Const8 [c]) (Add8 (Const8 [d]) x)) // cond: // result: (Add8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add8 (Const8 [c]) (Add8 x (Const8 [d]))) // cond: // result: (Add8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add8 (Add8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Add8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add8 (Add8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Add8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAdd8_30(v *Value) bool { b := v.Block // match: (Add8 (Const8 [c]) (Sub8 (Const8 [d]) x)) // cond: // result: (Sub8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add8 (Sub8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Sub8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add8 (Const8 [c]) (Sub8 x (Const8 [d]))) // cond: // result: (Add8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Add8 (Sub8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Add8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSub8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAddPtr_0(v *Value) bool { // match: (AddPtr x (Const64 [c])) // cond: // result: (OffPtr x [c]) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpOffPtr) v.Type = t v.AuxInt = c v.AddArg(x) return true } // match: (AddPtr x (Const32 [c])) // cond: // result: (OffPtr x [c]) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpOffPtr) v.Type = t v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd16_0(v *Value) bool { // match: (And16 (Const16 [c]) (Const16 [d])) // cond: // result: (Const16 [int64(int16(c&d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c & d)) return true } // match: (And16 (Const16 [d]) (Const16 [c])) // cond: // result: (Const16 [int64(int16(c&d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c & d)) return true } // match: (And16 (Const16 [m]) (Rsh16Ux64 _ (Const64 [c]))) // cond: c >= 64-ntz(m) // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpRsh16Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (And16 (Rsh16Ux64 _ (Const64 [c])) (Const16 [m])) // cond: c >= 64-ntz(m) // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } m := v_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (And16 (Const16 [m]) (Lsh16x64 _ (Const64 [c]))) // cond: c >= 64-nlz(m) // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpLsh16x64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (And16 (Lsh16x64 _ (Const64 [c])) (Const16 [m])) // cond: c >= 64-nlz(m) // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } m := v_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (And16 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And16 (Const16 [-1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And16 x (Const16 [-1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And16 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpAnd16_10(v *Value) bool { b := v.Block // match: (And16 _ (Const16 [0])) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (And16 x (And16 x y)) // cond: // result: (And16 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpAnd16) v.AddArg(x) v.AddArg(y) return true } // match: (And16 x (And16 y x)) // cond: // result: (And16 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpAnd16) v.AddArg(x) v.AddArg(y) return true } // match: (And16 (And16 x y) x) // cond: // result: (And16 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpAnd16) v.AddArg(x) v.AddArg(y) return true } // match: (And16 (And16 y x) x) // cond: // result: (And16 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpAnd16) v.AddArg(x) v.AddArg(y) return true } // match: (And16 (And16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (And16 i (And16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAnd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And16 (And16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (And16 i (And16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAnd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And16 x (And16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (And16 i (And16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAnd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And16 x (And16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (And16 i (And16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAnd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And16 (Const16 [c]) (And16 (Const16 [d]) x)) // cond: // result: (And16 (Const16 [int64(int16(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c & d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd16_20(v *Value) bool { b := v.Block // match: (And16 (Const16 [c]) (And16 x (Const16 [d]))) // cond: // result: (And16 (Const16 [int64(int16(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c & d)) v.AddArg(v0) v.AddArg(x) return true } // match: (And16 (And16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (And16 (Const16 [int64(int16(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c & d)) v.AddArg(v0) v.AddArg(x) return true } // match: (And16 (And16 x (Const16 [d])) (Const16 [c])) // cond: // result: (And16 (Const16 [int64(int16(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c & d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd32_0(v *Value) bool { // match: (And32 (Const32 [c]) (Const32 [d])) // cond: // result: (Const32 [int64(int32(c&d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c & d)) return true } // match: (And32 (Const32 [d]) (Const32 [c])) // cond: // result: (Const32 [int64(int32(c&d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c & d)) return true } // match: (And32 (Const32 [m]) (Rsh32Ux64 _ (Const64 [c]))) // cond: c >= 64-ntz(m) // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpRsh32Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (And32 (Rsh32Ux64 _ (Const64 [c])) (Const32 [m])) // cond: c >= 64-ntz(m) // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } m := v_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (And32 (Const32 [m]) (Lsh32x64 _ (Const64 [c]))) // cond: c >= 64-nlz(m) // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpLsh32x64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (And32 (Lsh32x64 _ (Const64 [c])) (Const32 [m])) // cond: c >= 64-nlz(m) // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } m := v_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (And32 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And32 (Const32 [-1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And32 x (Const32 [-1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And32 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpAnd32_10(v *Value) bool { b := v.Block // match: (And32 _ (Const32 [0])) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (And32 x (And32 x y)) // cond: // result: (And32 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpAnd32) v.AddArg(x) v.AddArg(y) return true } // match: (And32 x (And32 y x)) // cond: // result: (And32 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpAnd32) v.AddArg(x) v.AddArg(y) return true } // match: (And32 (And32 x y) x) // cond: // result: (And32 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpAnd32) v.AddArg(x) v.AddArg(y) return true } // match: (And32 (And32 y x) x) // cond: // result: (And32 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpAnd32) v.AddArg(x) v.AddArg(y) return true } // match: (And32 (And32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (And32 i (And32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAnd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And32 (And32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (And32 i (And32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAnd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And32 x (And32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (And32 i (And32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAnd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And32 x (And32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (And32 i (And32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAnd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And32 (Const32 [c]) (And32 (Const32 [d]) x)) // cond: // result: (And32 (Const32 [int64(int32(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c & d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd32_20(v *Value) bool { b := v.Block // match: (And32 (Const32 [c]) (And32 x (Const32 [d]))) // cond: // result: (And32 (Const32 [int64(int32(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c & d)) v.AddArg(v0) v.AddArg(x) return true } // match: (And32 (And32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (And32 (Const32 [int64(int32(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c & d)) v.AddArg(v0) v.AddArg(x) return true } // match: (And32 (And32 x (Const32 [d])) (Const32 [c])) // cond: // result: (And32 (Const32 [int64(int32(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c & d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd64_0(v *Value) bool { // match: (And64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c&d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c & d return true } // match: (And64 (Const64 [d]) (Const64 [c])) // cond: // result: (Const64 [c&d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c & d return true } // match: (And64 (Const64 [m]) (Rsh64Ux64 _ (Const64 [c]))) // cond: c >= 64-ntz(m) // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpRsh64Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (And64 (Rsh64Ux64 _ (Const64 [c])) (Const64 [m])) // cond: c >= 64-ntz(m) // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } m := v_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (And64 (Const64 [m]) (Lsh64x64 _ (Const64 [c]))) // cond: c >= 64-nlz(m) // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpLsh64x64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (And64 (Lsh64x64 _ (Const64 [c])) (Const64 [m])) // cond: c >= 64-nlz(m) // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } m := v_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (And64 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And64 (Const64 [-1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And64 x (Const64 [-1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And64 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpAnd64_10(v *Value) bool { b := v.Block // match: (And64 _ (Const64 [0])) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (And64 x (And64 x y)) // cond: // result: (And64 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpAnd64) v.AddArg(x) v.AddArg(y) return true } // match: (And64 x (And64 y x)) // cond: // result: (And64 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpAnd64) v.AddArg(x) v.AddArg(y) return true } // match: (And64 (And64 x y) x) // cond: // result: (And64 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpAnd64) v.AddArg(x) v.AddArg(y) return true } // match: (And64 (And64 y x) x) // cond: // result: (And64 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpAnd64) v.AddArg(x) v.AddArg(y) return true } // match: (And64 (Const64 [y]) x) // cond: nlz(y) + nto(y) == 64 && nto(y) >= 32 // result: (Rsh64Ux64 (Lsh64x64 x (Const64 [nlz(y)])) (Const64 [nlz(y)])) for { t := v.Type x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } y := v_0.AuxInt if !(nlz(y)+nto(y) == 64 && nto(y) >= 32) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpLsh64x64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = nlz(y) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = nlz(y) v.AddArg(v2) return true } // match: (And64 x (Const64 [y])) // cond: nlz(y) + nto(y) == 64 && nto(y) >= 32 // result: (Rsh64Ux64 (Lsh64x64 x (Const64 [nlz(y)])) (Const64 [nlz(y)])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } y := v_1.AuxInt if !(nlz(y)+nto(y) == 64 && nto(y) >= 32) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpLsh64x64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = nlz(y) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = nlz(y) v.AddArg(v2) return true } // match: (And64 (Const64 [y]) x) // cond: nlo(y) + ntz(y) == 64 && ntz(y) >= 32 // result: (Lsh64x64 (Rsh64Ux64 x (Const64 [ntz(y)])) (Const64 [ntz(y)])) for { t := v.Type x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } y := v_0.AuxInt if !(nlo(y)+ntz(y) == 64 && ntz(y) >= 32) { break } v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = ntz(y) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = ntz(y) v.AddArg(v2) return true } // match: (And64 x (Const64 [y])) // cond: nlo(y) + ntz(y) == 64 && ntz(y) >= 32 // result: (Lsh64x64 (Rsh64Ux64 x (Const64 [ntz(y)])) (Const64 [ntz(y)])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } y := v_1.AuxInt if !(nlo(y)+ntz(y) == 64 && ntz(y) >= 32) { break } v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = ntz(y) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = ntz(y) v.AddArg(v2) return true } // match: (And64 (And64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (And64 i (And64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAnd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpAnd64_20(v *Value) bool { b := v.Block // match: (And64 (And64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (And64 i (And64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAnd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And64 x (And64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (And64 i (And64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAnd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And64 x (And64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (And64 i (And64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAnd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And64 (Const64 [c]) (And64 (Const64 [d]) x)) // cond: // result: (And64 (Const64 [c&d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c & d v.AddArg(v0) v.AddArg(x) return true } // match: (And64 (Const64 [c]) (And64 x (Const64 [d]))) // cond: // result: (And64 (Const64 [c&d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c & d v.AddArg(v0) v.AddArg(x) return true } // match: (And64 (And64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (And64 (Const64 [c&d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c & d v.AddArg(v0) v.AddArg(x) return true } // match: (And64 (And64 x (Const64 [d])) (Const64 [c])) // cond: // result: (And64 (Const64 [c&d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c & d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd8_0(v *Value) bool { // match: (And8 (Const8 [c]) (Const8 [d])) // cond: // result: (Const8 [int64(int8(c&d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c & d)) return true } // match: (And8 (Const8 [d]) (Const8 [c])) // cond: // result: (Const8 [int64(int8(c&d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c & d)) return true } // match: (And8 (Const8 [m]) (Rsh8Ux64 _ (Const64 [c]))) // cond: c >= 64-ntz(m) // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpRsh8Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (And8 (Rsh8Ux64 _ (Const64 [c])) (Const8 [m])) // cond: c >= 64-ntz(m) // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } m := v_1.AuxInt if !(c >= 64-ntz(m)) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (And8 (Const8 [m]) (Lsh8x64 _ (Const64 [c]))) // cond: c >= 64-nlz(m) // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } m := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpLsh8x64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (And8 (Lsh8x64 _ (Const64 [c])) (Const8 [m])) // cond: c >= 64-nlz(m) // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } m := v_1.AuxInt if !(c >= 64-nlz(m)) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (And8 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And8 (Const8 [-1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And8 x (Const8 [-1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (And8 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpAnd8_10(v *Value) bool { b := v.Block // match: (And8 _ (Const8 [0])) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (And8 x (And8 x y)) // cond: // result: (And8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpAnd8) v.AddArg(x) v.AddArg(y) return true } // match: (And8 x (And8 y x)) // cond: // result: (And8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpAnd8) v.AddArg(x) v.AddArg(y) return true } // match: (And8 (And8 x y) x) // cond: // result: (And8 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpAnd8) v.AddArg(x) v.AddArg(y) return true } // match: (And8 (And8 y x) x) // cond: // result: (And8 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpAnd8) v.AddArg(x) v.AddArg(y) return true } // match: (And8 (And8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (And8 i (And8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAnd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And8 (And8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (And8 i (And8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAnd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And8 x (And8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (And8 i (And8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAnd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And8 x (And8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (And8 i (And8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAnd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (And8 (Const8 [c]) (And8 (Const8 [d]) x)) // cond: // result: (And8 (Const8 [int64(int8(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c & d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd8_20(v *Value) bool { b := v.Block // match: (And8 (Const8 [c]) (And8 x (Const8 [d]))) // cond: // result: (And8 (Const8 [int64(int8(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c & d)) v.AddArg(v0) v.AddArg(x) return true } // match: (And8 (And8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (And8 (Const8 [int64(int8(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c & d)) v.AddArg(v0) v.AddArg(x) return true } // match: (And8 (And8 x (Const8 [d])) (Const8 [c])) // cond: // result: (And8 (Const8 [int64(int8(c&d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c & d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpArraySelect_0(v *Value) bool { // match: (ArraySelect (ArrayMake1 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpArrayMake1 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ArraySelect [0] x:(IData _)) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] if x.Op != OpIData { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpCom16_0(v *Value) bool { // match: (Com16 (Com16 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpCom16 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Com16 (Const16 [c])) // cond: // result: (Const16 [^c]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst16) v.AuxInt = ^c return true } return false } func rewriteValuegeneric_OpCom32_0(v *Value) bool { // match: (Com32 (Com32 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpCom32 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Com32 (Const32 [c])) // cond: // result: (Const32 [^c]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = ^c return true } return false } func rewriteValuegeneric_OpCom64_0(v *Value) bool { // match: (Com64 (Com64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpCom64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Com64 (Const64 [c])) // cond: // result: (Const64 [^c]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = ^c return true } return false } func rewriteValuegeneric_OpCom8_0(v *Value) bool { // match: (Com8 (Com8 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpCom8 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Com8 (Const8 [c])) // cond: // result: (Const8 [^c]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst8) v.AuxInt = ^c return true } return false } func rewriteValuegeneric_OpConstInterface_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ConstInterface) // cond: // result: (IMake (ConstNil ) (ConstNil )) for { v.reset(OpIMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.Uintptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v.AddArg(v1) return true } } func rewriteValuegeneric_OpConstSlice_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (ConstSlice) // cond: config.PtrSize == 4 // result: (SliceMake (ConstNil ) (Const32 [0]) (Const32 [0])) for { if !(config.PtrSize == 4) { break } v.reset(OpSliceMake) v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int) v2.AuxInt = 0 v.AddArg(v2) return true } // match: (ConstSlice) // cond: config.PtrSize == 8 // result: (SliceMake (ConstNil ) (Const64 [0]) (Const64 [0])) for { if !(config.PtrSize == 8) { break } v.reset(OpSliceMake) v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.Int) v2.AuxInt = 0 v.AddArg(v2) return true } return false } func rewriteValuegeneric_OpConstString_0(v *Value) bool { b := v.Block config := b.Func.Config fe := b.Func.fe typ := &b.Func.Config.Types // match: (ConstString {s}) // cond: config.PtrSize == 4 && s.(string) == "" // result: (StringMake (ConstNil) (Const32 [0])) for { s := v.Aux if !(config.PtrSize == 4 && s.(string) == "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = 0 v.AddArg(v1) return true } // match: (ConstString {s}) // cond: config.PtrSize == 8 && s.(string) == "" // result: (StringMake (ConstNil) (Const64 [0])) for { s := v.Aux if !(config.PtrSize == 8 && s.(string) == "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = 0 v.AddArg(v1) return true } // match: (ConstString {s}) // cond: config.PtrSize == 4 && s.(string) != "" // result: (StringMake (Addr {fe.StringData(s.(string))} (SB)) (Const32 [int64(len(s.(string)))])) for { s := v.Aux if !(config.PtrSize == 4 && s.(string) != "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) v0.Aux = fe.StringData(s.(string)) v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int) v2.AuxInt = int64(len(s.(string))) v.AddArg(v2) return true } // match: (ConstString {s}) // cond: config.PtrSize == 8 && s.(string) != "" // result: (StringMake (Addr {fe.StringData(s.(string))} (SB)) (Const64 [int64(len(s.(string)))])) for { s := v.Aux if !(config.PtrSize == 8 && s.(string) != "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) v0.Aux = fe.StringData(s.(string)) v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.Int) v2.AuxInt = int64(len(s.(string))) v.AddArg(v2) return true } return false } func rewriteValuegeneric_OpConvert_0(v *Value) bool { // match: (Convert (Add64 (Convert ptr mem) off) mem) // cond: // result: (Add64 ptr off) for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } off := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConvert { break } _ = v_0_0.Args[1] ptr := v_0_0.Args[0] if mem != v_0_0.Args[1] { break } v.reset(OpAdd64) v.AddArg(ptr) v.AddArg(off) return true } // match: (Convert (Add64 off (Convert ptr mem)) mem) // cond: // result: (Add64 ptr off) for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] off := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConvert { break } _ = v_0_1.Args[1] ptr := v_0_1.Args[0] if mem != v_0_1.Args[1] { break } v.reset(OpAdd64) v.AddArg(ptr) v.AddArg(off) return true } // match: (Convert (Add32 (Convert ptr mem) off) mem) // cond: // result: (Add32 ptr off) for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } off := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConvert { break } _ = v_0_0.Args[1] ptr := v_0_0.Args[0] if mem != v_0_0.Args[1] { break } v.reset(OpAdd32) v.AddArg(ptr) v.AddArg(off) return true } // match: (Convert (Add32 off (Convert ptr mem)) mem) // cond: // result: (Add32 ptr off) for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] off := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConvert { break } _ = v_0_1.Args[1] ptr := v_0_1.Args[0] if mem != v_0_1.Args[1] { break } v.reset(OpAdd32) v.AddArg(ptr) v.AddArg(off) return true } // match: (Convert (Convert ptr mem) mem) // cond: // result: ptr for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConvert { break } _ = v_0.Args[1] ptr := v_0.Args[0] if mem != v_0.Args[1] { break } v.reset(OpCopy) v.Type = ptr.Type v.AddArg(ptr) return true } return false } func rewriteValuegeneric_OpCvt32Fto32_0(v *Value) bool { // match: (Cvt32Fto32 (Const32F [c])) // cond: // result: (Const32 [int64(int32(auxTo32F(c)))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(auxTo32F(c))) return true } return false } func rewriteValuegeneric_OpCvt32Fto64_0(v *Value) bool { // match: (Cvt32Fto64 (Const32F [c])) // cond: // result: (Const64 [int64(auxTo32F(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(auxTo32F(c)) return true } return false } func rewriteValuegeneric_OpCvt32Fto64F_0(v *Value) bool { // match: (Cvt32Fto64F (Const32F [c])) // cond: // result: (Const64F [c]) for { v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v.reset(OpConst64F) v.AuxInt = c return true } return false } func rewriteValuegeneric_OpCvt32to32F_0(v *Value) bool { // match: (Cvt32to32F (Const32 [c])) // cond: // result: (Const32F [auxFrom32F(float32(int32(c)))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(float32(int32(c))) return true } return false } func rewriteValuegeneric_OpCvt32to64F_0(v *Value) bool { // match: (Cvt32to64F (Const32 [c])) // cond: // result: (Const64F [auxFrom64F(float64(int32(c)))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(float64(int32(c))) return true } return false } func rewriteValuegeneric_OpCvt64Fto32_0(v *Value) bool { // match: (Cvt64Fto32 (Const64F [c])) // cond: // result: (Const32 [int64(int32(auxTo64F(c)))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(auxTo64F(c))) return true } return false } func rewriteValuegeneric_OpCvt64Fto32F_0(v *Value) bool { // match: (Cvt64Fto32F (Const64F [c])) // cond: // result: (Const32F [auxFrom32F(float32(auxTo64F(c)))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(float32(auxTo64F(c))) return true } return false } func rewriteValuegeneric_OpCvt64Fto64_0(v *Value) bool { // match: (Cvt64Fto64 (Const64F [c])) // cond: // result: (Const64 [int64(auxTo64F(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(auxTo64F(c)) return true } return false } func rewriteValuegeneric_OpCvt64to32F_0(v *Value) bool { // match: (Cvt64to32F (Const64 [c])) // cond: // result: (Const32F [auxFrom32F(float32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(float32(c)) return true } return false } func rewriteValuegeneric_OpCvt64to64F_0(v *Value) bool { // match: (Cvt64to64F (Const64 [c])) // cond: // result: (Const64F [auxFrom64F(float64(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(float64(c)) return true } return false } func rewriteValuegeneric_OpDiv16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16 (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int64(int16(c)/int16(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int64(int16(c) / int16(d)) return true } // match: (Div16 n (Const16 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c&0xffff) // result: (Rsh16Ux64 n (Const64 [log2(c&0xffff)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c&0xffff)) { break } v.reset(OpRsh16Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c & 0xffff) v.AddArg(v0) return true } // match: (Div16 n (Const16 [c])) // cond: c < 0 && c != -1<<15 // result: (Neg16 (Div16 n (Const16 [-c]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<15) { break } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpDiv16, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = -c v0.AddArg(v1) v.AddArg(v0) return true } // match: (Div16 x (Const16 [-1<<15])) // cond: // result: (Rsh16Ux64 (And16 x (Neg16 x)) (Const64 [15])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != -1<<15 { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpNeg16, t) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = 15 v.AddArg(v2) return true } // match: (Div16 n (Const16 [c])) // cond: isPowerOfTwo(c) // result: (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [16-log2(c)]))) (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpRsh16Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh16x64, t) v2.AddArg(n) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = 15 v2.AddArg(v3) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 16 - log2(c) v1.AddArg(v4) v0.AddArg(v1) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = log2(c) v.AddArg(v5) return true } // match: (Div16 x (Const16 [c])) // cond: smagicOK(16,c) // result: (Sub16 (Rsh32x64 (Mul32 (Const32 [int64(smagic(16,c).m)]) (SignExt16to32 x)) (Const64 [16+smagic(16,c).s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(smagicOK(16, c)) { break } v.reset(OpSub16) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(smagic(16, c).m) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 16 + smagic(16, c).s v0.AddArg(v4) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v6.AddArg(x) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = 31 v5.AddArg(v7) v.AddArg(v5) return true } return false } func rewriteValuegeneric_OpDiv16u_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div16u (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int64(int16(uint16(c)/uint16(d)))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int64(int16(uint16(c) / uint16(d))) return true } // match: (Div16u n (Const16 [c])) // cond: isPowerOfTwo(c&0xffff) // result: (Rsh16Ux64 n (Const64 [log2(c&0xffff)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(isPowerOfTwo(c & 0xffff)) { break } v.reset(OpRsh16Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c & 0xffff) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK(16, c) && config.RegSize == 8 // result: (Trunc64to16 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<16+umagic(16,c).m)]) (ZeroExt16to64 x)) (Const64 [16+umagic(16,c).s]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(umagicOK(16, c) && config.RegSize == 8) { break } v.reset(OpTrunc64to16) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(1<<16 + umagic(16, c).m) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 16 + umagic(16, c).s v0.AddArg(v4) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK(16, c) && config.RegSize == 4 && umagic(16,c).m&1 == 0 // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int64(1<<15+umagic(16,c).m/2)]) (ZeroExt16to32 x)) (Const64 [16+umagic(16,c).s-1]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(umagicOK(16, c) && config.RegSize == 4 && umagic(16, c).m&1 == 0) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(1<<15 + umagic(16, c).m/2) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 16 + umagic(16, c).s - 1 v0.AddArg(v4) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK(16, c) && config.RegSize == 4 && c&1 == 0 // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int64(1<<15+(umagic(16,c).m+1)/2)]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [16+umagic(16,c).s-2]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(umagicOK(16, c) && config.RegSize == 4 && c&1 == 0) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(1<<15 + (umagic(16, c).m+1)/2) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v4.AddArg(x) v3.AddArg(v4) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = 1 v3.AddArg(v5) v1.AddArg(v3) v0.AddArg(v1) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = 16 + umagic(16, c).s - 2 v0.AddArg(v6) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK(16, c) && config.RegSize == 4 && config.useAvg // result: (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) (Mul32 (Const32 [int64(umagic(16,c).m)]) (ZeroExt16to32 x))) (Const64 [16+umagic(16,c).s-1]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(umagicOK(16, c) && config.RegSize == 4 && config.useAvg) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) v2 := b.NewValue0(v.Pos, OpLsh32x64, typ.UInt32) v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v3.AddArg(x) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 16 v2.AddArg(v4) v1.AddArg(v2) v5 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(umagic(16, c).m) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v7.AddArg(x) v5.AddArg(v7) v1.AddArg(v5) v0.AddArg(v1) v8 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v8.AuxInt = 16 + umagic(16, c).s - 1 v0.AddArg(v8) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv32_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32 (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int64(int32(c)/int32(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int64(int32(c) / int32(d)) return true } // match: (Div32 n (Const32 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c&0xffffffff) // result: (Rsh32Ux64 n (Const64 [log2(c&0xffffffff)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c&0xffffffff)) { break } v.reset(OpRsh32Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c & 0xffffffff) v.AddArg(v0) return true } // match: (Div32 n (Const32 [c])) // cond: c < 0 && c != -1<<31 // result: (Neg32 (Div32 n (Const32 [-c]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<31) { break } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpDiv32, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = -c v0.AddArg(v1) v.AddArg(v0) return true } // match: (Div32 x (Const32 [-1<<31])) // cond: // result: (Rsh32Ux64 (And32 x (Neg32 x)) (Const64 [31])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != -1<<31 { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpNeg32, t) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = 31 v.AddArg(v2) return true } // match: (Div32 n (Const32 [c])) // cond: isPowerOfTwo(c) // result: (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [32-log2(c)]))) (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpRsh32Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh32x64, t) v2.AddArg(n) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = 31 v2.AddArg(v3) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 32 - log2(c) v1.AddArg(v4) v0.AddArg(v1) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = log2(c) v.AddArg(v5) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK(32,c) && config.RegSize == 8 // result: (Sub32 (Rsh64x64 (Mul64 (Const64 [int64(smagic(32,c).m)]) (SignExt32to64 x)) (Const64 [32+smagic(32,c).s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(smagicOK(32, c) && config.RegSize == 8) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(smagic(32, c).m) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 32 + smagic(32, c).s v0.AddArg(v4) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpRsh64x64, t) v6 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v6.AddArg(x) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = 63 v5.AddArg(v7) v.AddArg(v5) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK(32,c) && config.RegSize == 4 && smagic(32,c).m&1 == 0 && config.useHmul // result: (Sub32 (Rsh32x64 (Hmul32 (Const32 [int64(int32(smagic(32,c).m/2))]) x) (Const64 [smagic(32,c).s-1])) (Rsh32x64 x (Const64 [31]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(smagicOK(32, c) && config.RegSize == 4 && smagic(32, c).m&1 == 0 && config.useHmul) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpHmul32, t) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(smagic(32, c).m / 2)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = smagic(32, c).s - 1 v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpRsh32x64, t) v4.AddArg(x) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = 31 v4.AddArg(v5) v.AddArg(v4) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK(32,c) && config.RegSize == 4 && smagic(32,c).m&1 != 0 && config.useHmul // result: (Sub32 (Rsh32x64 (Add32 (Hmul32 (Const32 [int64(int32(smagic(32,c).m))]) x) x) (Const64 [smagic(32,c).s])) (Rsh32x64 x (Const64 [31]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(smagicOK(32, c) && config.RegSize == 4 && smagic(32, c).m&1 != 0 && config.useHmul) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpAdd32, t) v2 := b.NewValue0(v.Pos, OpHmul32, t) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(smagic(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = smagic(32, c).s v0.AddArg(v4) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v5.AddArg(x) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = 31 v5.AddArg(v6) v.AddArg(v5) return true } return false } func rewriteValuegeneric_OpDiv32F_0(v *Value) bool { b := v.Block // match: (Div32F (Const32F [c]) (Const32F [d])) // cond: // result: (Const32F [auxFrom32F(auxTo32F(c) / auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(auxTo32F(c) / auxTo32F(d)) return true } // match: (Div32F x (Const32F [c])) // cond: reciprocalExact32(auxTo32F(c)) // result: (Mul32F x (Const32F [auxFrom32F(1/auxTo32F(c))])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32F { break } t := v_1.Type c := v_1.AuxInt if !(reciprocalExact32(auxTo32F(c))) { break } v.reset(OpMul32F) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst32F, t) v0.AuxInt = auxFrom32F(1 / auxTo32F(c)) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv32u_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32u (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int64(int32(uint32(c)/uint32(d)))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int64(int32(uint32(c) / uint32(d))) return true } // match: (Div32u n (Const32 [c])) // cond: isPowerOfTwo(c&0xffffffff) // result: (Rsh32Ux64 n (Const64 [log2(c&0xffffffff)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(isPowerOfTwo(c & 0xffffffff)) { break } v.reset(OpRsh32Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c & 0xffffffff) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK(32, c) && config.RegSize == 4 && umagic(32,c).m&1 == 0 && config.useHmul // result: (Rsh32Ux64 (Hmul32u (Const32 [int64(int32(1<<31+umagic(32,c).m/2))]) x) (Const64 [umagic(32,c).s-1])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(umagicOK(32, c) && config.RegSize == 4 && umagic(32, c).m&1 == 0 && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v1.AuxInt = int64(int32(1<<31 + umagic(32, c).m/2)) v0.AddArg(v1) v0.AddArg(x) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = umagic(32, c).s - 1 v.AddArg(v2) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK(32, c) && config.RegSize == 4 && c&1 == 0 && config.useHmul // result: (Rsh32Ux64 (Hmul32u (Const32 [int64(int32(1<<31+(umagic(32,c).m+1)/2))]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [umagic(32,c).s-2])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(umagicOK(32, c) && config.RegSize == 4 && c&1 == 0 && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v1.AuxInt = int64(int32(1<<31 + (umagic(32, c).m+1)/2)) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v2.AddArg(x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = 1 v2.AddArg(v3) v0.AddArg(v2) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = umagic(32, c).s - 2 v.AddArg(v4) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK(32, c) && config.RegSize == 4 && config.useAvg && config.useHmul // result: (Rsh32Ux64 (Avg32u x (Hmul32u (Const32 [int64(int32(umagic(32,c).m))]) x)) (Const64 [umagic(32,c).s-1])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(umagicOK(32, c) && config.RegSize == 4 && config.useAvg && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(umagic(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = umagic(32, c).s - 1 v.AddArg(v3) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK(32, c) && config.RegSize == 8 && umagic(32,c).m&1 == 0 // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+umagic(32,c).m/2)]) (ZeroExt32to64 x)) (Const64 [32+umagic(32,c).s-1]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(umagicOK(32, c) && config.RegSize == 8 && umagic(32, c).m&1 == 0) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(1<<31 + umagic(32, c).m/2) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 32 + umagic(32, c).s - 1 v0.AddArg(v4) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK(32, c) && config.RegSize == 8 && c&1 == 0 // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+(umagic(32,c).m+1)/2)]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [32+umagic(32,c).s-2]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(umagicOK(32, c) && config.RegSize == 8 && c&1 == 0) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(1<<31 + (umagic(32, c).m+1)/2) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(x) v3.AddArg(v4) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = 1 v3.AddArg(v5) v1.AddArg(v3) v0.AddArg(v1) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = 32 + umagic(32, c).s - 2 v0.AddArg(v6) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK(32, c) && config.RegSize == 8 && config.useAvg // result: (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) (Mul64 (Const64 [int64(umagic(32,c).m)]) (ZeroExt32to64 x))) (Const64 [32+umagic(32,c).s-1]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(umagicOK(32, c) && config.RegSize == 8 && config.useAvg) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 32 v2.AddArg(v4) v1.AddArg(v2) v5 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt32) v6.AuxInt = int64(umagic(32, c).m) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v7.AddArg(x) v5.AddArg(v7) v1.AddArg(v5) v0.AddArg(v1) v8 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v8.AuxInt = 32 + umagic(32, c).s - 1 v0.AddArg(v8) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv64_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64 (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [c/d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = c / d return true } // match: (Div64 n (Const64 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c) // result: (Rsh64Ux64 n (Const64 [log2(c)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c)) { break } v.reset(OpRsh64Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Div64 n (Const64 [-1<<63])) // cond: isNonNegative(n) // result: (Const64 [0]) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1<<63 { break } if !(isNonNegative(n)) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Div64 n (Const64 [c])) // cond: c < 0 && c != -1<<63 // result: (Neg64 (Div64 n (Const64 [-c]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<63) { break } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpDiv64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = -c v0.AddArg(v1) v.AddArg(v0) return true } // match: (Div64 x (Const64 [-1<<63])) // cond: // result: (Rsh64Ux64 (And64 x (Neg64 x)) (Const64 [63])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1<<63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpNeg64, t) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = 63 v.AddArg(v2) return true } // match: (Div64 n (Const64 [c])) // cond: isPowerOfTwo(c) // result: (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [64-log2(c)]))) (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpRsh64Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh64x64, t) v2.AddArg(n) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = 63 v2.AddArg(v3) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 64 - log2(c) v1.AddArg(v4) v0.AddArg(v1) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = log2(c) v.AddArg(v5) return true } // match: (Div64 x (Const64 [c])) // cond: smagicOK(64,c) && smagic(64,c).m&1 == 0 && config.useHmul // result: (Sub64 (Rsh64x64 (Hmul64 (Const64 [int64(smagic(64,c).m/2)]) x) (Const64 [smagic(64,c).s-1])) (Rsh64x64 x (Const64 [63]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(smagicOK(64, c) && smagic(64, c).m&1 == 0 && config.useHmul) { break } v.reset(OpSub64) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpHmul64, t) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(smagic(64, c).m / 2) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = smagic(64, c).s - 1 v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpRsh64x64, t) v4.AddArg(x) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = 63 v4.AddArg(v5) v.AddArg(v4) return true } // match: (Div64 x (Const64 [c])) // cond: smagicOK(64,c) && smagic(64,c).m&1 != 0 && config.useHmul // result: (Sub64 (Rsh64x64 (Add64 (Hmul64 (Const64 [int64(smagic(64,c).m)]) x) x) (Const64 [smagic(64,c).s])) (Rsh64x64 x (Const64 [63]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(smagicOK(64, c) && smagic(64, c).m&1 != 0 && config.useHmul) { break } v.reset(OpSub64) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpAdd64, t) v2 := b.NewValue0(v.Pos, OpHmul64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(smagic(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = smagic(64, c).s v0.AddArg(v4) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpRsh64x64, t) v5.AddArg(x) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = 63 v5.AddArg(v6) v.AddArg(v5) return true } return false } func rewriteValuegeneric_OpDiv64F_0(v *Value) bool { b := v.Block // match: (Div64F (Const64F [c]) (Const64F [d])) // cond: // result: (Const64F [auxFrom64F(auxTo64F(c) / auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(auxTo64F(c) / auxTo64F(d)) return true } // match: (Div64F x (Const64F [c])) // cond: reciprocalExact64(auxTo64F(c)) // result: (Mul64F x (Const64F [auxFrom64F(1/auxTo64F(c))])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64F { break } t := v_1.Type c := v_1.AuxInt if !(reciprocalExact64(auxTo64F(c))) { break } v.reset(OpMul64F) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64F, t) v0.AuxInt = auxFrom64F(1 / auxTo64F(c)) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv64u_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64u (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [int64(uint64(c)/uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64(uint64(c) / uint64(d)) return true } // match: (Div64u n (Const64 [c])) // cond: isPowerOfTwo(c) // result: (Rsh64Ux64 n (Const64 [log2(c)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpRsh64Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Div64u n (Const64 [-1<<63])) // cond: // result: (Rsh64Ux64 n (Const64 [63])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1<<63 { break } v.reset(OpRsh64Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = 63 v.AddArg(v0) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK(64, c) && config.RegSize == 8 && umagic(64,c).m&1 == 0 && config.useHmul // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+umagic(64,c).m/2)]) x) (Const64 [umagic(64,c).s-1])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(umagicOK(64, c) && config.RegSize == 8 && umagic(64, c).m&1 == 0 && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64(1<<63 + umagic(64, c).m/2) v0.AddArg(v1) v0.AddArg(x) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = umagic(64, c).s - 1 v.AddArg(v2) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK(64, c) && config.RegSize == 8 && c&1 == 0 && config.useHmul // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+(umagic(64,c).m+1)/2)]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [umagic(64,c).s-2])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(umagicOK(64, c) && config.RegSize == 8 && c&1 == 0 && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64(1<<63 + (umagic(64, c).m+1)/2) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v2.AddArg(x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = 1 v2.AddArg(v3) v0.AddArg(v2) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = umagic(64, c).s - 2 v.AddArg(v4) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK(64, c) && config.RegSize == 8 && config.useAvg && config.useHmul // result: (Rsh64Ux64 (Avg64u x (Hmul64u (Const64 [int64(umagic(64,c).m)]) x)) (Const64 [umagic(64,c).s-1])) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(umagicOK(64, c) && config.RegSize == 8 && config.useAvg && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(umagic(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = umagic(64, c).s - 1 v.AddArg(v3) return true } return false } func rewriteValuegeneric_OpDiv8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8 (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int64(int8(c)/int8(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int64(int8(c) / int8(d)) return true } // match: (Div8 n (Const8 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c&0xff) // result: (Rsh8Ux64 n (Const64 [log2(c&0xff)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c&0xff)) { break } v.reset(OpRsh8Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c & 0xff) v.AddArg(v0) return true } // match: (Div8 n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Neg8 (Div8 n (Const8 [-c]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<7) { break } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpDiv8, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = -c v0.AddArg(v1) v.AddArg(v0) return true } // match: (Div8 x (Const8 [-1<<7 ])) // cond: // result: (Rsh8Ux64 (And8 x (Neg8 x)) (Const64 [7 ])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != -1<<7 { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpNeg8, t) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = 7 v.AddArg(v2) return true } // match: (Div8 n (Const8 [c])) // cond: isPowerOfTwo(c) // result: (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [ 8-log2(c)]))) (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpRsh8Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh8x64, t) v2.AddArg(n) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = 7 v2.AddArg(v3) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 8 - log2(c) v1.AddArg(v4) v0.AddArg(v1) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = log2(c) v.AddArg(v5) return true } // match: (Div8 x (Const8 [c])) // cond: smagicOK(8,c) // result: (Sub8 (Rsh32x64 (Mul32 (Const32 [int64(smagic(8,c).m)]) (SignExt8to32 x)) (Const64 [8+smagic(8,c).s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(smagicOK(8, c)) { break } v.reset(OpSub8) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(smagic(8, c).m) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 8 + smagic(8, c).s v0.AddArg(v4) v.AddArg(v0) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v6.AddArg(x) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = 31 v5.AddArg(v7) v.AddArg(v5) return true } return false } func rewriteValuegeneric_OpDiv8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8u (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int64(int8(uint8(c)/uint8(d)))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int64(int8(uint8(c) / uint8(d))) return true } // match: (Div8u n (Const8 [c])) // cond: isPowerOfTwo(c&0xff) // result: (Rsh8Ux64 n (Const64 [log2(c&0xff)])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(isPowerOfTwo(c & 0xff)) { break } v.reset(OpRsh8Ux64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c & 0xff) v.AddArg(v0) return true } // match: (Div8u x (Const8 [c])) // cond: umagicOK(8, c) // result: (Trunc32to8 (Rsh32Ux64 (Mul32 (Const32 [int64(1<<8+umagic(8,c).m)]) (ZeroExt8to32 x)) (Const64 [8+umagic(8,c).s]))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(umagicOK(8, c)) { break } v.reset(OpTrunc32to8) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(1<<8 + umagic(8, c).m) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = 8 + umagic(8, c).s v0.AddArg(v4) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpEq16_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Eq16 x x) // cond: // result: (ConstBool [1]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (Eq16 (Const16 [c]) (Add16 (Const16 [d]) x)) // cond: // result: (Eq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq16 (Const16 [c]) (Add16 x (Const16 [d]))) // cond: // result: (Eq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq16 (Add16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Eq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq16 (Add16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Eq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq16 (Const16 [c]) (Const16 [d])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq16 (Const16 [d]) (Const16 [c])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq16 (Mod16u x (Const16 [c])) (Const16 [0])) // cond: x.Op != OpConst16 && udivisibleOK(16,c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt16to32 x) (Const32 [c&0xffff])) (Const32 [0])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMod16u { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } if !(x.Op != OpConst16 && udivisibleOK(16, c) && !hasSmallRotate(config)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = c & 0xffff v0.AddArg(v2) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = 0 v.AddArg(v3) return true } // match: (Eq16 (Const16 [0]) (Mod16u x (Const16 [c]))) // cond: x.Op != OpConst16 && udivisibleOK(16,c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt16to32 x) (Const32 [c&0xffff])) (Const32 [0])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v_1 := v.Args[1] if v_1.Op != OpMod16u { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(x.Op != OpConst16 && udivisibleOK(16, c) && !hasSmallRotate(config)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = c & 0xffff v0.AddArg(v2) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = 0 v.AddArg(v3) return true } // match: (Eq16 (Mod16 x (Const16 [c])) (Const16 [0])) // cond: x.Op != OpConst16 && sdivisibleOK(16,c) && !hasSmallRotate(config) // result: (Eq32 (Mod32 (SignExt16to32 x) (Const32 [c])) (Const32 [0])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMod16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } if !(x.Op != OpConst16 && sdivisibleOK(16, c) && !hasSmallRotate(config)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = c v0.AddArg(v2) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v3.AuxInt = 0 v.AddArg(v3) return true } return false } func rewriteValuegeneric_OpEq16_10(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Eq16 (Const16 [0]) (Mod16 x (Const16 [c]))) // cond: x.Op != OpConst16 && sdivisibleOK(16,c) && !hasSmallRotate(config) // result: (Eq32 (Mod32 (SignExt16to32 x) (Const32 [c])) (Const32 [0])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v_1 := v.Args[1] if v_1.Op != OpMod16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(x.Op != OpConst16 && sdivisibleOK(16, c) && !hasSmallRotate(config)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = c v0.AddArg(v2) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v3.AuxInt = 0 v.AddArg(v3) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to64 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (ZeroExt16to64 x) (Const64 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to64 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (ZeroExt16to64 x) (Const64 [m])) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to64 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (ZeroExt16to64 x) (Const64 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to64 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (ZeroExt16to64 x) (Const64 [m])) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x)) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq16_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (ZeroExt16to32 x) (Const32 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x)) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (ZeroExt16to32 x) (Const32 [m])) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x)) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (ZeroExt16to32 x) (Const32 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x)) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (ZeroExt16to32 x) (Const32 [m])) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16, c).m/2) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt16to32 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) (Const32 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt16to32 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt16to32 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq16_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) (Const32 [m])) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt16to32 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt16to32 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) (Const32 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt16to32 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt16to32 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) (Const32 [m])) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt16to32 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16, c).m+1)/2) && s == 16+umagic(16, c).s-2 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x))) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg32u { break } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh32x64 { break } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_1_1_0_0_0_0.Args[0] { break } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 { break } if v_1_1_0_0_0_1.AuxInt != 16 { break } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (ZeroExt16to32 x) (Const32 [m]))) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to16 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg32u { break } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh32x64 { break } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_1_1_0_0_0_0.Args[0] { break } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 { break } if v_1_1_0_0_0_1.AuxInt != 16 { break } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x))) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAvg32u { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpLsh32x64 { break } _ = v_1_0_0_0_0.Args[1] v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_1_0_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.AuxInt != 16 { break } mul := v_1_0_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (ZeroExt16to32 x) (Const32 [m]))) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to16 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAvg32u { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpLsh32x64 { break } _ = v_1_0_0_0_0.Args[1] v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_1_0_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.AuxInt != 16 { break } mul := v_1_0_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAvg32u { break } _ = v_0_1_0_0.Args[1] v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpLsh32x64 { break } _ = v_0_1_0_0_0.Args[1] v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_0_1_0_0_0_0.Args[0] { break } v_0_1_0_0_0_1 := v_0_1_0_0_0.Args[1] if v_0_1_0_0_0_1.Op != OpConst64 { break } if v_0_1_0_0_0_1.AuxInt != 16 { break } mul := v_0_1_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq16_40(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (ZeroExt16to32 x) (Const32 [m]))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to16 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAvg32u { break } _ = v_0_1_0_0.Args[1] v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpLsh32x64 { break } _ = v_0_1_0_0_0.Args[1] v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_0_1_0_0_0_0.Args[0] { break } v_0_1_0_0_0_1 := v_0_1_0_0_0.Args[1] if v_0_1_0_0_0_1.Op != OpConst64 { break } if v_0_1_0_0_0_1.AuxInt != 16 { break } mul := v_0_1_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x))) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAvg32u { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpLsh32x64 { break } _ = v_0_0_0_0_0.Args[1] v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_0_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.AuxInt != 16 { break } mul := v_0_0_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt16to32 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (ZeroExt16to32 x) (Const32 [m]))) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAvg32u { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpLsh32x64 { break } _ = v_0_0_0_0_0.Args[1] v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpZeroExt16to32 { break } if x != v_0_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.AuxInt != 16 { break } mul := v_0_0_0_0.Args[1] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16, c).m) && s == 16+umagic(16, c).s-1 && x.Op != OpConst16 && udivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int64(int16(udivisible(16, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(16 - udivisible(16, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(udivisible(16, c).max)) v.AddArg(v4) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub16 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpSignExt16to32 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { break } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt16to32 { break } if x != v_1_1_1_0.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(int16(sdivisible(16, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(sdivisible(16, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v5.AuxInt = int64(16 - sdivisible(16, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v6.AuxInt = int64(int16(sdivisible(16, c).max)) v.AddArg(v6) return true } // match: (Eq16 x (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (SignExt16to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub16 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpSignExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { break } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt16to32 { break } if x != v_1_1_1_0.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(int16(sdivisible(16, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(sdivisible(16, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v5.AuxInt = int64(16 - sdivisible(16, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v6.AuxInt = int64(int16(sdivisible(16, c).max)) v.AddArg(v6) return true } // match: (Eq16 x (Mul16 (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub16 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32x64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpSignExt16to32 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh32x64 { break } _ = v_1_0_1.Args[1] v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpSignExt16to32 { break } if x != v_1_0_1_0.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 31 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(int16(sdivisible(16, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(sdivisible(16, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v5.AuxInt = int64(16 - sdivisible(16, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v6.AuxInt = int64(int16(sdivisible(16, c).max)) v.AddArg(v6) return true } // match: (Eq16 x (Mul16 (Sub16 (Rsh32x64 mul:(Mul32 (SignExt16to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub16 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32x64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpSignExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh32x64 { break } _ = v_1_0_1.Args[1] v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpSignExt16to32 { break } if x != v_1_0_1_0.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 31 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(int16(sdivisible(16, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(sdivisible(16, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v5.AuxInt = int64(16 - sdivisible(16, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v6.AuxInt = int64(int16(sdivisible(16, c).max)) v.AddArg(v6) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub16 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32x64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpSignExt16to32 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh32x64 { break } _ = v_0_1_1.Args[1] v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpSignExt16to32 { break } if x != v_0_1_1_0.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(int16(sdivisible(16, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(sdivisible(16, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v5.AuxInt = int64(16 - sdivisible(16, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v6.AuxInt = int64(int16(sdivisible(16, c).max)) v.AddArg(v6) return true } // match: (Eq16 (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (SignExt16to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub16 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32x64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpSignExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh32x64 { break } _ = v_0_1_1.Args[1] v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpSignExt16to32 { break } if x != v_0_1_1_0.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(int16(sdivisible(16, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(sdivisible(16, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v5.AuxInt = int64(16 - sdivisible(16, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v6.AuxInt = int64(int16(sdivisible(16, c).max)) v.AddArg(v6) return true } // match: (Eq16 (Mul16 (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub16 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32x64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpSignExt16to32 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh32x64 { break } _ = v_0_0_1.Args[1] v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpSignExt16to32 { break } if x != v_0_0_1_0.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 31 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(int16(sdivisible(16, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(sdivisible(16, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v5.AuxInt = int64(16 - sdivisible(16, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v6.AuxInt = int64(int16(sdivisible(16, c).max)) v.AddArg(v6) return true } return false } func rewriteValuegeneric_OpEq16_50(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq16 (Mul16 (Sub16 (Rsh32x64 mul:(Mul32 (SignExt16to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub16 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32x64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpSignExt16to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh32x64 { break } _ = v_0_0_1.Args[1] v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpSignExt16to32 { break } if x != v_0_0_1_0.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 31 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { break } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int64(int16(sdivisible(16, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int64(int16(sdivisible(16, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v5.AuxInt = int64(16 - sdivisible(16, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v6.AuxInt = int64(int16(sdivisible(16, c).max)) v.AddArg(v6) return true } // match: (Eq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh16x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh16x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd16 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] if n != v_1_0_0.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpRsh16Ux64 { break } if v_1_0_0_1.Type != t { break } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh16x64 { break } if v_1_0_0_1_0.Type != t { break } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { break } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 { break } if v_1_0_0_1_0_1.Type != typ.UInt64 { break } if v_1_0_0_1_0_1.AuxInt != 15 { break } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 { break } if v_1_0_0_1_1.Type != typ.UInt64 { break } kbar := v_1_0_0_1_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 15 && kbar == 16-k) { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int64(1< (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh16x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh16x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd16 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpRsh16Ux64 { break } if v_1_0_0_0.Type != t { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpRsh16x64 { break } if v_1_0_0_0_0.Type != t { break } _ = v_1_0_0_0_0.Args[1] if n != v_1_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.Type != typ.UInt64 { break } if v_1_0_0_0_0_1.AuxInt != 15 { break } v_1_0_0_0_1 := v_1_0_0_0.Args[1] if v_1_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_1.Type != typ.UInt64 { break } kbar := v_1_0_0_0_1.AuxInt if n != v_1_0_0.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 15 && kbar == 16-k) { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int64(1< n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh16x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd16 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] if n != v_0_0_0.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpRsh16Ux64 { break } if v_0_0_0_1.Type != t { break } _ = v_0_0_0_1.Args[1] v_0_0_0_1_0 := v_0_0_0_1.Args[0] if v_0_0_0_1_0.Op != OpRsh16x64 { break } if v_0_0_0_1_0.Type != t { break } _ = v_0_0_0_1_0.Args[1] if n != v_0_0_0_1_0.Args[0] { break } v_0_0_0_1_0_1 := v_0_0_0_1_0.Args[1] if v_0_0_0_1_0_1.Op != OpConst64 { break } if v_0_0_0_1_0_1.Type != typ.UInt64 { break } if v_0_0_0_1_0_1.AuxInt != 15 { break } v_0_0_0_1_1 := v_0_0_0_1.Args[1] if v_0_0_0_1_1.Op != OpConst64 { break } if v_0_0_0_1_1.Type != typ.UInt64 { break } kbar := v_0_0_0_1_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 15 && kbar == 16-k) { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int64(1< (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh16x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd16 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpRsh16Ux64 { break } if v_0_0_0_0.Type != t { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpRsh16x64 { break } if v_0_0_0_0_0.Type != t { break } _ = v_0_0_0_0_0.Args[1] if n != v_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.Type != typ.UInt64 { break } if v_0_0_0_0_0_1.AuxInt != 15 { break } v_0_0_0_0_1 := v_0_0_0_0.Args[1] if v_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_1.Type != typ.UInt64 { break } kbar := v_0_0_0_0_1.AuxInt if n != v_0_0_0.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 15 && kbar == 16-k) { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int64(1< [c]) (Add32 (Const32 [d]) x)) // cond: // result: (Eq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq32 (Const32 [c]) (Add32 x (Const32 [d]))) // cond: // result: (Eq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq32 (Add32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Eq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq32 (Add32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Eq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq32 (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq32 (Const32 [d]) (Const32 [c])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) x) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh32Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u x (Const32 [m])) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh32Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) x) (Const64 [s])) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq32_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq32 x (Mul32 (Rsh32Ux64 mul:(Hmul32u x (Const32 [m])) (Const64 [s])) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) x) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh32Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u x (Const32 [m])) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh32Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) x) (Const64 [s])) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Rsh32Ux64 mul:(Hmul32u x (Const32 [m])) (Const64 [s])) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32,c).m/2)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+umagic(32, c).m/2)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh32Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } if mul_0.Type != typ.UInt32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Rsh32Ux64 x (Const64 [1])) (Const32 [m])) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh32Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } if mul_1.Type != typ.UInt32 { break } m := mul_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [s])) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } if mul_0.Type != typ.UInt32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Rsh32Ux64 mul:(Hmul32u (Rsh32Ux64 x (Const64 [1])) (Const32 [m])) (Const64 [s])) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } if mul_1.Type != typ.UInt32 { break } m := mul_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh32Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } if mul_0.Type != typ.UInt32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq32_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq32 (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Rsh32Ux64 x (Const64 [1])) (Const32 [m])) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh32Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } if mul_1.Type != typ.UInt32 { break } m := mul_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [s])) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } if mul_0.Type != typ.UInt32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh32Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Rsh32Ux64 mul:(Hmul32u (Rsh32Ux64 x (Const64 [1])) (Const32 [m])) (Const64 [s])) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32,c).m+1)/2)) && s == umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh32Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } if mul_1.Type != typ.UInt32 { break } m := mul_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(1<<31+(umagic(32, c).m+1)/2)) && s == umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 (Avg32u x mul:(Hmul32u (Const32 [m]) x)) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh32Ux64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg32u { break } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { break } mul := v_1_1_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 (Avg32u x mul:(Hmul32u x (Const32 [m]))) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh32Ux64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg32u { break } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { break } mul := v_1_1_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Rsh32Ux64 (Avg32u x mul:(Hmul32u (Const32 [m]) x)) (Const64 [s])) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32Ux64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAvg32u { break } _ = v_1_0_0.Args[1] if x != v_1_0_0.Args[0] { break } mul := v_1_0_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Rsh32Ux64 (Avg32u x mul:(Hmul32u x (Const32 [m]))) (Const64 [s])) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32Ux64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAvg32u { break } _ = v_1_0_0.Args[1] if x != v_1_0_0.Args[0] { break } mul := v_1_0_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Rsh32Ux64 (Avg32u x mul:(Hmul32u (Const32 [m]) x)) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh32Ux64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAvg32u { break } _ = v_0_1_0.Args[1] if x != v_0_1_0.Args[0] { break } mul := v_0_1_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Rsh32Ux64 (Avg32u x mul:(Hmul32u x (Const32 [m]))) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh32Ux64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAvg32u { break } _ = v_0_1_0.Args[1] if x != v_0_1_0.Args[0] { break } mul := v_0_1_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Rsh32Ux64 (Avg32u x mul:(Hmul32u (Const32 [m]) x)) (Const64 [s])) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAvg32u { break } _ = v_0_0_0.Args[1] if x != v_0_0_0.Args[0] { break } mul := v_0_0_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq32_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq32 (Mul32 (Rsh32Ux64 (Avg32u x mul:(Hmul32u x (Const32 [m]))) (Const64 [s])) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32,c).m)) && s == umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAvg32u { break } _ = v_0_0_0.Args[1] if x != v_0_0_0.Args[0] { break } mul := v_0_0_0.Args[1] if mul.Op != OpHmul32u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(umagic(32, c).m)) && s == umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x)) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to32 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (ZeroExt32to64 x) (Const64 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to32 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x)) (Const64 [s]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to32 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (ZeroExt32to64 x) (Const64 [m])) (Const64 [s]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to32 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x)) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to32 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (ZeroExt32to64 x) (Const64 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to32 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x)) (Const64 [s]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to32 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (ZeroExt32to64 x) (Const64 [m])) (Const64 [s]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32,c).m/2) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to32 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic(32, c).m/2) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to32 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt32to64 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq32_40(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1])) (Const64 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to32 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt32to64 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [s]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to32 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt32to64 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1])) (Const64 [m])) (Const64 [s]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to32 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt32to64 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to32 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt32to64 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1])) (Const64 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to32 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt32to64 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [s]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to32 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt32to64 { break } if x != mul_1_0.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1])) (Const64 [m])) (Const64 [s]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32,c).m+1)/2) && s == 32+umagic(32,c).s-2 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to32 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] mul_0_0 := mul_0.Args[0] if mul_0_0.Op != OpZeroExt32to64 { break } if x != mul_0_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic(32, c).m+1)/2) && s == 32+umagic(32, c).s-2 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x))) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to32 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg64u { break } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh64x64 { break } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_1_1_0_0_0_0.Args[0] { break } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 { break } if v_1_1_0_0_0_1.AuxInt != 32 { break } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (ZeroExt32to64 x) (Const64 [m]))) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc64to32 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg64u { break } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh64x64 { break } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_1_1_0_0_0_0.Args[0] { break } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 { break } if v_1_1_0_0_0_1.AuxInt != 32 { break } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x))) (Const64 [s]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to32 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAvg64u { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpLsh64x64 { break } _ = v_1_0_0_0_0.Args[1] v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_1_0_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.AuxInt != 32 { break } mul := v_1_0_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq32_50(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq32 x (Mul32 (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (ZeroExt32to64 x) (Const64 [m]))) (Const64 [s]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc64to32 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64Ux64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAvg64u { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpLsh64x64 { break } _ = v_1_0_0_0_0.Args[1] v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_1_0_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.AuxInt != 32 { break } mul := v_1_0_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to32 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAvg64u { break } _ = v_0_1_0_0.Args[1] v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpLsh64x64 { break } _ = v_0_1_0_0_0.Args[1] v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_0_1_0_0_0_0.Args[0] { break } v_0_1_0_0_0_1 := v_0_1_0_0_0.Args[1] if v_0_1_0_0_0_1.Op != OpConst64 { break } if v_0_1_0_0_0_1.AuxInt != 32 { break } mul := v_0_1_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (ZeroExt32to64 x) (Const64 [m]))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc64to32 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64Ux64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAvg64u { break } _ = v_0_1_0_0.Args[1] v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpLsh64x64 { break } _ = v_0_1_0_0_0.Args[1] v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_0_1_0_0_0_0.Args[0] { break } v_0_1_0_0_0_1 := v_0_1_0_0_0.Args[1] if v_0_1_0_0_0_1.Op != OpConst64 { break } if v_0_1_0_0_0_1.AuxInt != 32 { break } mul := v_0_1_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x))) (Const64 [s]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to32 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAvg64u { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpLsh64x64 { break } _ = v_0_0_0_0_0.Args[1] v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_0_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.AuxInt != 32 { break } mul := v_0_0_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt32to64 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 (Mul32 (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (ZeroExt32to64 x) (Const64 [m]))) (Const64 [s]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32,c).m) && s == 32+umagic(32,c).s-1 && x.Op != OpConst32 && udivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int64(int32(udivisible(32,c).m))]) x) (Const32 [int64(32-udivisible(32,c).k)]) ) (Const32 [int64(int32(udivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc64to32 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAvg64u { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpLsh64x64 { break } _ = v_0_0_0_0_0.Args[1] v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpZeroExt32to64 { break } if x != v_0_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.AuxInt != 32 { break } mul := v_0_0_0_0.Args[1] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(32, c).m) && s == 32+umagic(32, c).s-1 && x.Op != OpConst32 && udivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int64(int32(udivisible(32, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(32 - udivisible(32, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(udivisible(32, c).max)) v.AddArg(v4) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub32 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpSignExt32to64 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { break } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt32to64 { break } if x != v_1_1_1_0.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (SignExt32to64 x) (Const64 [m])) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub32 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpSignExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { break } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt32to64 { break } if x != v_1_1_1_0.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64x64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpSignExt32to64 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh64x64 { break } _ = v_1_0_1.Args[1] v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpSignExt32to64 { break } if x != v_1_0_1_0.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 63 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Sub32 (Rsh64x64 mul:(Mul64 (SignExt32to64 x) (Const64 [m])) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64x64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpSignExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh64x64 { break } _ = v_1_0_1.Args[1] v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpSignExt32to64 { break } if x != v_1_0_1_0.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 63 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub32 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64x64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpSignExt32to64 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh64x64 { break } _ = v_0_1_1.Args[1] v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpSignExt32to64 { break } if x != v_0_1_1_0.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } return false } func rewriteValuegeneric_OpEq32_60(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (SignExt32to64 x) (Const64 [m])) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub32 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64x64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpSignExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh64x64 { break } _ = v_0_1_1.Args[1] v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpSignExt32to64 { break } if x != v_0_1_1_0.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 (Mul32 (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub32 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64x64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpSignExt32to64 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh64x64 { break } _ = v_0_0_1.Args[1] v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpSignExt32to64 { break } if x != v_0_0_1_0.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 63 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 (Mul32 (Sub32 (Rsh64x64 mul:(Mul64 (SignExt32to64 x) (Const64 [m])) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub32 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64x64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpSignExt32to64 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh64x64 { break } _ = v_0_0_1.Args[1] v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpSignExt32to64 { break } if x != v_0_0_1_0.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 63 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub32 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { break } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 x (Const32 [m])) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub32 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { break } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32x64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh32x64 { break } _ = v_1_0_1.Args[1] if x != v_1_0_1.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 31 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 mul:(Hmul32 x (Const32 [m])) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32x64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh32x64 { break } _ = v_1_0_1.Args[1] if x != v_1_0_1.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 31 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub32 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32x64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh32x64 { break } _ = v_0_1_1.Args[1] if x != v_0_1_1.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 x (Const32 [m])) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub32 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32x64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh32x64 { break } _ = v_0_1_1.Args[1] if x != v_0_1_1.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub32 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32x64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh32x64 { break } _ = v_0_0_1.Args[1] if x != v_0_0_1.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 31 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } return false } func rewriteValuegeneric_OpEq32_70(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 mul:(Hmul32 x (Const32 [m])) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub32 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32x64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh32x64 { break } _ = v_0_0_1.Args[1] if x != v_0_0_1.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 31 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub32 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd32 { break } _ = v_1_1_0_0.Args[1] mul := v_1_1_0_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } if x != v_1_1_0_0.Args[1] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { break } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 x (Const32 [m])) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub32 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd32 { break } _ = v_1_1_0_0.Args[1] mul := v_1_1_0_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt if x != v_1_1_0_0.Args[1] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { break } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 (Const32 [m]) x)) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub32 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd32 { break } _ = v_1_1_0_0.Args[1] if x != v_1_1_0_0.Args[0] { break } mul := v_1_1_0_0.Args[1] if mul.Op != OpHmul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { break } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 x (Const32 [m]))) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub32 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd32 { break } _ = v_1_1_0_0.Args[1] if x != v_1_1_0_0.Args[0] { break } mul := v_1_1_0_0.Args[1] if mul.Op != OpHmul32 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { break } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32x64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAdd32 { break } _ = v_1_0_0_0.Args[1] mul := v_1_0_0_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } if x != v_1_0_0_0.Args[1] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh32x64 { break } _ = v_1_0_1.Args[1] if x != v_1_0_1.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 31 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 x (Const32 [m])) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32x64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAdd32 { break } _ = v_1_0_0_0.Args[1] mul := v_1_0_0_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt if x != v_1_0_0_0.Args[1] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh32x64 { break } _ = v_1_0_1.Args[1] if x != v_1_0_1.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 31 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 (Const32 [m]) x)) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32x64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAdd32 { break } _ = v_1_0_0_0.Args[1] if x != v_1_0_0_0.Args[0] { break } mul := v_1_0_0_0.Args[1] if mul.Op != OpHmul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh32x64 { break } _ = v_1_0_1.Args[1] if x != v_1_0_1.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 31 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 x (Const32 [m]))) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32x64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAdd32 { break } _ = v_1_0_0_0.Args[1] if x != v_1_0_0_0.Args[0] { break } mul := v_1_0_0_0.Args[1] if mul.Op != OpHmul32 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh32x64 { break } _ = v_1_0_1.Args[1] if x != v_1_0_1.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 31 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub32 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32x64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAdd32 { break } _ = v_0_1_0_0.Args[1] mul := v_0_1_0_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } if x != v_0_1_0_0.Args[1] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh32x64 { break } _ = v_0_1_1.Args[1] if x != v_0_1_1.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } return false } func rewriteValuegeneric_OpEq32_80(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 x (Const32 [m])) x) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub32 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32x64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAdd32 { break } _ = v_0_1_0_0.Args[1] mul := v_0_1_0_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt if x != v_0_1_0_0.Args[1] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh32x64 { break } _ = v_0_1_1.Args[1] if x != v_0_1_1.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 (Const32 [m]) x)) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub32 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32x64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAdd32 { break } _ = v_0_1_0_0.Args[1] if x != v_0_1_0_0.Args[0] { break } mul := v_0_1_0_0.Args[1] if mul.Op != OpHmul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh32x64 { break } _ = v_0_1_1.Args[1] if x != v_0_1_1.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 x (Const32 [m]))) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub32 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32x64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAdd32 { break } _ = v_0_1_0_0.Args[1] if x != v_0_1_0_0.Args[0] { break } mul := v_0_1_0_0.Args[1] if mul.Op != OpHmul32 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh32x64 { break } _ = v_0_1_1.Args[1] if x != v_0_1_1.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub32 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32x64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAdd32 { break } _ = v_0_0_0_0.Args[1] mul := v_0_0_0_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } if x != v_0_0_0_0.Args[1] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh32x64 { break } _ = v_0_0_1.Args[1] if x != v_0_0_1.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 31 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 x (Const32 [m])) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub32 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32x64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAdd32 { break } _ = v_0_0_0_0.Args[1] mul := v_0_0_0_0.Args[0] if mul.Op != OpHmul32 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt if x != v_0_0_0_0.Args[1] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh32x64 { break } _ = v_0_0_1.Args[1] if x != v_0_0_1.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 31 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 (Const32 [m]) x)) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub32 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32x64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAdd32 { break } _ = v_0_0_0_0.Args[1] if x != v_0_0_0_0.Args[0] { break } mul := v_0_0_0_0.Args[1] if mul.Op != OpHmul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh32x64 { break } _ = v_0_0_1.Args[1] if x != v_0_0_1.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 31 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 x (Const32 [m]))) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub32 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32x64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAdd32 { break } _ = v_0_0_0_0.Args[1] if x != v_0_0_0_0.Args[0] { break } mul := v_0_0_0_0.Args[1] if mul.Op != OpHmul32 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh32x64 { break } _ = v_0_0_1.Args[1] if x != v_0_0_1.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 31 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { break } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int64(int32(sdivisible(32, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int64(int32(sdivisible(32, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int64(32 - sdivisible(32, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int64(int32(sdivisible(32, c).max)) v.AddArg(v6) return true } // match: (Eq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh32x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd32 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] if n != v_1_0_0.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpRsh32Ux64 { break } if v_1_0_0_1.Type != t { break } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh32x64 { break } if v_1_0_0_1_0.Type != t { break } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { break } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 { break } if v_1_0_0_1_0_1.Type != typ.UInt64 { break } if v_1_0_0_1_0_1.AuxInt != 31 { break } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 { break } if v_1_0_0_1_1.Type != typ.UInt64 { break } kbar := v_1_0_0_1_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 31 && kbar == 32-k) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int64(1< (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh32x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd32 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpRsh32Ux64 { break } if v_1_0_0_0.Type != t { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpRsh32x64 { break } if v_1_0_0_0_0.Type != t { break } _ = v_1_0_0_0_0.Args[1] if n != v_1_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.Type != typ.UInt64 { break } if v_1_0_0_0_0_1.AuxInt != 31 { break } v_1_0_0_0_1 := v_1_0_0_0.Args[1] if v_1_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_1.Type != typ.UInt64 { break } kbar := v_1_0_0_0_1.AuxInt if n != v_1_0_0.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 31 && kbar == 32-k) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int64(1< n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd32 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] if n != v_0_0_0.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpRsh32Ux64 { break } if v_0_0_0_1.Type != t { break } _ = v_0_0_0_1.Args[1] v_0_0_0_1_0 := v_0_0_0_1.Args[0] if v_0_0_0_1_0.Op != OpRsh32x64 { break } if v_0_0_0_1_0.Type != t { break } _ = v_0_0_0_1_0.Args[1] if n != v_0_0_0_1_0.Args[0] { break } v_0_0_0_1_0_1 := v_0_0_0_1_0.Args[1] if v_0_0_0_1_0_1.Op != OpConst64 { break } if v_0_0_0_1_0_1.Type != typ.UInt64 { break } if v_0_0_0_1_0_1.AuxInt != 31 { break } v_0_0_0_1_1 := v_0_0_0_1.Args[1] if v_0_0_0_1_1.Op != OpConst64 { break } if v_0_0_0_1_1.Type != typ.UInt64 { break } kbar := v_0_0_0_1_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 31 && kbar == 32-k) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int64(1< (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd32 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpRsh32Ux64 { break } if v_0_0_0_0.Type != t { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpRsh32x64 { break } if v_0_0_0_0_0.Type != t { break } _ = v_0_0_0_0_0.Args[1] if n != v_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.Type != typ.UInt64 { break } if v_0_0_0_0_0_1.AuxInt != 31 { break } v_0_0_0_0_1 := v_0_0_0_0.Args[1] if v_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_1.Type != typ.UInt64 { break } kbar := v_0_0_0_0_1.AuxInt if n != v_0_0_0.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 31 && kbar == 32-k) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int64(1< [c]) (Add64 (Const64 [d]) x)) // cond: // result: (Eq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Eq64 (Const64 [c]) (Add64 x (Const64 [d]))) // cond: // result: (Eq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Eq64 (Add64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Eq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Eq64 (Add64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Eq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Eq64 (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq64 (Const64 [d]) (Const64 [c])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) x) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh64Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u x (Const64 [m])) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh64Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) x) (Const64 [s])) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq64_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq64 x (Mul64 (Rsh64Ux64 mul:(Hmul64u x (Const64 [m])) (Const64 [s])) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) x) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh64Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u x (Const64 [m])) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh64Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) x) (Const64 [s])) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Rsh64Ux64 mul:(Hmul64u x (Const64 [m])) (Const64 [s])) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64,c).m/2) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic(64, c).m/2) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh64Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Rsh64Ux64 x (Const64 [1])) (Const64 [m])) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh64Ux64 { break } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [s])) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Rsh64Ux64 mul:(Hmul64u (Rsh64Ux64 x (Const64 [1])) (Const64 [m])) (Const64 [s])) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64Ux64 { break } _ = v_1_0.Args[1] mul := v_1_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh64Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq64_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq64 (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Rsh64Ux64 x (Const64 [1])) (Const64 [m])) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh64Ux64 { break } _ = v_0_1.Args[1] mul := v_0_1.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [s])) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpRsh64Ux64 { break } _ = mul_1.Args[1] if x != mul_1.Args[0] { break } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 { break } if mul_1_1.AuxInt != 1 { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Rsh64Ux64 mul:(Hmul64u (Rsh64Ux64 x (Const64 [1])) (Const64 [m])) (Const64 [s])) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64,c).m+1)/2) && s == umagic(64,c).s-2 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] mul := v_0_0.Args[0] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpRsh64Ux64 { break } _ = mul_0.Args[1] if x != mul_0.Args[0] { break } mul_0_1 := mul_0.Args[1] if mul_0_1.Op != OpConst64 { break } if mul_0_1.AuxInt != 1 { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic(64, c).m+1)/2) && s == umagic(64, c).s-2 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 (Avg64u x mul:(Hmul64u (Const64 [m]) x)) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh64Ux64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg64u { break } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { break } mul := v_1_1_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 (Avg64u x mul:(Hmul64u x (Const64 [m]))) (Const64 [s])))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpRsh64Ux64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg64u { break } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { break } mul := v_1_1_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { break } s := v_1_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Rsh64Ux64 (Avg64u x mul:(Hmul64u (Const64 [m]) x)) (Const64 [s])) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64Ux64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAvg64u { break } _ = v_1_0_0.Args[1] if x != v_1_0_0.Args[0] { break } mul := v_1_0_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Rsh64Ux64 (Avg64u x mul:(Hmul64u x (Const64 [m]))) (Const64 [s])) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64Ux64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAvg64u { break } _ = v_1_0_0.Args[1] if x != v_1_0_0.Args[0] { break } mul := v_1_0_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } s := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Rsh64Ux64 (Avg64u x mul:(Hmul64u (Const64 [m]) x)) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh64Ux64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAvg64u { break } _ = v_0_1_0.Args[1] if x != v_0_1_0.Args[0] { break } mul := v_0_1_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Rsh64Ux64 (Avg64u x mul:(Hmul64u x (Const64 [m]))) (Const64 [s]))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpRsh64Ux64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAvg64u { break } _ = v_0_1_0.Args[1] if x != v_0_1_0.Args[0] { break } mul := v_0_1_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpConst64 { break } s := v_0_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 (Mul64 (Rsh64Ux64 (Avg64u x mul:(Hmul64u (Const64 [m]) x)) (Const64 [s])) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAvg64u { break } _ = v_0_0_0.Args[1] if x != v_0_0_0.Args[0] { break } mul := v_0_0_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } return false } func rewriteValuegeneric_OpEq64_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq64 (Mul64 (Rsh64Ux64 (Avg64u x mul:(Hmul64u x (Const64 [m]))) (Const64 [s])) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64,c).m) && s == umagic(64,c).s-1 && x.Op != OpConst64 && udivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible(64,c).m)]) x) (Const64 [int64(64-udivisible(64,c).k)]) ) (Const64 [int64(udivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAvg64u { break } _ = v_0_0_0.Args[1] if x != v_0_0_0.Args[0] { break } mul := v_0_0_0.Args[1] if mul.Op != OpHmul64u { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } s := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(64, c).m) && s == umagic(64, c).s-1 && x.Op != OpConst64 && udivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64(udivisible(64, c).m) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(64 - udivisible(64, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(udivisible(64, c).max) v.AddArg(v4) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { break } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 x (Const64 [m])) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { break } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64x64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh64x64 { break } _ = v_1_0_1.Args[1] if x != v_1_0_1.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 63 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 mul:(Hmul64 x (Const64 [m])) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64x64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh64x64 { break } _ = v_1_0_1.Args[1] if x != v_1_0_1.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 63 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64x64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh64x64 { break } _ = v_0_1_1.Args[1] if x != v_0_1_1.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 x (Const64 [m])) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64x64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh64x64 { break } _ = v_0_1_1.Args[1] if x != v_0_1_1.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64x64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh64x64 { break } _ = v_0_0_1.Args[1] if x != v_0_0_1.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 63 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 mul:(Hmul64 x (Const64 [m])) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64x64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh64x64 { break } _ = v_0_0_1.Args[1] if x != v_0_0_1.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 63 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd64 { break } _ = v_1_1_0_0.Args[1] mul := v_1_1_0_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } if x != v_1_1_0_0.Args[1] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { break } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } return false } func rewriteValuegeneric_OpEq64_40(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 x (Const64 [m])) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd64 { break } _ = v_1_1_0_0.Args[1] mul := v_1_1_0_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt if x != v_1_1_0_0.Args[1] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { break } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 (Const64 [m]) x)) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd64 { break } _ = v_1_1_0_0.Args[1] if x != v_1_1_0_0.Args[0] { break } mul := v_1_1_0_0.Args[1] if mul.Op != OpHmul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { break } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 x (Const64 [m]))) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub64 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { break } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd64 { break } _ = v_1_1_0_0.Args[1] if x != v_1_1_0_0.Args[0] { break } mul := v_1_1_0_0.Args[1] if mul.Op != OpHmul64 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { break } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64x64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAdd64 { break } _ = v_1_0_0_0.Args[1] mul := v_1_0_0_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } if x != v_1_0_0_0.Args[1] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh64x64 { break } _ = v_1_0_1.Args[1] if x != v_1_0_1.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 63 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 x (Const64 [m])) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64x64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAdd64 { break } _ = v_1_0_0_0.Args[1] mul := v_1_0_0_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt if x != v_1_0_0_0.Args[1] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh64x64 { break } _ = v_1_0_1.Args[1] if x != v_1_0_1.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 63 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 (Const64 [m]) x)) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64x64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAdd64 { break } _ = v_1_0_0_0.Args[1] if x != v_1_0_0_0.Args[0] { break } mul := v_1_0_0_0.Args[1] if mul.Op != OpHmul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh64x64 { break } _ = v_1_0_1.Args[1] if x != v_1_0_1.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 63 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 x (Const64 [m]))) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh64x64 { break } _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAdd64 { break } _ = v_1_0_0_0.Args[1] if x != v_1_0_0_0.Args[0] { break } mul := v_1_0_0_0.Args[1] if mul.Op != OpHmul64 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh64x64 { break } _ = v_1_0_1.Args[1] if x != v_1_0_1.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 63 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64x64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAdd64 { break } _ = v_0_1_0_0.Args[1] mul := v_0_1_0_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } if x != v_0_1_0_0.Args[1] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh64x64 { break } _ = v_0_1_1.Args[1] if x != v_0_1_1.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 x (Const64 [m])) x) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64x64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAdd64 { break } _ = v_0_1_0_0.Args[1] mul := v_0_1_0_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt if x != v_0_1_0_0.Args[1] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh64x64 { break } _ = v_0_1_1.Args[1] if x != v_0_1_1.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 (Const64 [m]) x)) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64x64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAdd64 { break } _ = v_0_1_0_0.Args[1] if x != v_0_1_0_0.Args[0] { break } mul := v_0_1_0_0.Args[1] if mul.Op != OpHmul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh64x64 { break } _ = v_0_1_1.Args[1] if x != v_0_1_1.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } return false } func rewriteValuegeneric_OpEq64_50(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 x (Const64 [m]))) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub64 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh64x64 { break } _ = v_0_1_0.Args[1] v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAdd64 { break } _ = v_0_1_0_0.Args[1] if x != v_0_1_0_0.Args[0] { break } mul := v_0_1_0_0.Args[1] if mul.Op != OpHmul64 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh64x64 { break } _ = v_0_1_1.Args[1] if x != v_0_1_1.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 63 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64x64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAdd64 { break } _ = v_0_0_0_0.Args[1] mul := v_0_0_0_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } if x != v_0_0_0_0.Args[1] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh64x64 { break } _ = v_0_0_1.Args[1] if x != v_0_0_1.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 63 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 x (Const64 [m])) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64x64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAdd64 { break } _ = v_0_0_0_0.Args[1] mul := v_0_0_0_0.Args[0] if mul.Op != OpHmul64 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt if x != v_0_0_0_0.Args[1] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh64x64 { break } _ = v_0_0_1.Args[1] if x != v_0_0_1.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 63 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 (Const64 [m]) x)) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64x64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAdd64 { break } _ = v_0_0_0_0.Args[1] if x != v_0_0_0_0.Args[0] { break } mul := v_0_0_0_0.Args[1] if mul.Op != OpHmul64 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst64 { break } m := mul_0.AuxInt if x != mul.Args[1] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh64x64 { break } _ = v_0_0_1.Args[1] if x != v_0_0_1.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 63 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 x (Const64 [m]))) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh64x64 { break } _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAdd64 { break } _ = v_0_0_0_0.Args[1] if x != v_0_0_0_0.Args[0] { break } mul := v_0_0_0_0.Args[1] if mul.Op != OpHmul64 { break } _ = mul.Args[1] if x != mul.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst64 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh64x64 { break } _ = v_0_0_1.Args[1] if x != v_0_0_1.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 63 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { break } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64(sdivisible(64, c).m) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64(sdivisible(64, c).a) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64(64 - sdivisible(64, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64(sdivisible(64, c).max) v.AddArg(v6) return true } // match: (Eq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh64x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd64 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] if n != v_1_0_0.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpRsh64Ux64 { break } if v_1_0_0_1.Type != t { break } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh64x64 { break } if v_1_0_0_1_0.Type != t { break } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { break } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 { break } if v_1_0_0_1_0_1.Type != typ.UInt64 { break } if v_1_0_0_1_0_1.AuxInt != 63 { break } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 { break } if v_1_0_0_1_1.Type != typ.UInt64 { break } kbar := v_1_0_0_1_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 63 && kbar == 64-k) { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64(1< (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh64x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd64 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpRsh64Ux64 { break } if v_1_0_0_0.Type != t { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpRsh64x64 { break } if v_1_0_0_0_0.Type != t { break } _ = v_1_0_0_0_0.Args[1] if n != v_1_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.Type != typ.UInt64 { break } if v_1_0_0_0_0_1.AuxInt != 63 { break } v_1_0_0_0_1 := v_1_0_0_0.Args[1] if v_1_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_1.Type != typ.UInt64 { break } kbar := v_1_0_0_0_1.AuxInt if n != v_1_0_0.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 63 && kbar == 64-k) { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64(1< n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd64 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] if n != v_0_0_0.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpRsh64Ux64 { break } if v_0_0_0_1.Type != t { break } _ = v_0_0_0_1.Args[1] v_0_0_0_1_0 := v_0_0_0_1.Args[0] if v_0_0_0_1_0.Op != OpRsh64x64 { break } if v_0_0_0_1_0.Type != t { break } _ = v_0_0_0_1_0.Args[1] if n != v_0_0_0_1_0.Args[0] { break } v_0_0_0_1_0_1 := v_0_0_0_1_0.Args[1] if v_0_0_0_1_0_1.Op != OpConst64 { break } if v_0_0_0_1_0_1.Type != typ.UInt64 { break } if v_0_0_0_1_0_1.AuxInt != 63 { break } v_0_0_0_1_1 := v_0_0_0_1.Args[1] if v_0_0_0_1_1.Op != OpConst64 { break } if v_0_0_0_1_1.Type != typ.UInt64 { break } kbar := v_0_0_0_1_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 63 && kbar == 64-k) { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64(1< (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd64 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpRsh64Ux64 { break } if v_0_0_0_0.Type != t { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpRsh64x64 { break } if v_0_0_0_0_0.Type != t { break } _ = v_0_0_0_0_0.Args[1] if n != v_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.Type != typ.UInt64 { break } if v_0_0_0_0_0_1.AuxInt != 63 { break } v_0_0_0_0_1 := v_0_0_0_0.Args[1] if v_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_1.Type != typ.UInt64 { break } kbar := v_0_0_0_0_1.AuxInt if n != v_0_0_0.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 63 && kbar == 64-k) { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64(1< [c]) (Add8 (Const8 [d]) x)) // cond: // result: (Eq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq8 (Const8 [c]) (Add8 x (Const8 [d]))) // cond: // result: (Eq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq8 (Add8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Eq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq8 (Add8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Eq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Eq8 (Const8 [c]) (Const8 [d])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq8 (Const8 [d]) (Const8 [c])) // cond: // result: (ConstBool [b2i(c == d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c == d) return true } // match: (Eq8 (Mod8u x (Const8 [c])) (Const8 [0])) // cond: x.Op != OpConst8 && udivisibleOK(8,c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt8to32 x) (Const32 [c&0xff])) (Const32 [0])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMod8u { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } if !(x.Op != OpConst8 && udivisibleOK(8, c) && !hasSmallRotate(config)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = c & 0xff v0.AddArg(v2) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = 0 v.AddArg(v3) return true } // match: (Eq8 (Const8 [0]) (Mod8u x (Const8 [c]))) // cond: x.Op != OpConst8 && udivisibleOK(8,c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt8to32 x) (Const32 [c&0xff])) (Const32 [0])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v_1 := v.Args[1] if v_1.Op != OpMod8u { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } c := v_1_1.AuxInt if !(x.Op != OpConst8 && udivisibleOK(8, c) && !hasSmallRotate(config)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = c & 0xff v0.AddArg(v2) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = 0 v.AddArg(v3) return true } // match: (Eq8 (Mod8 x (Const8 [c])) (Const8 [0])) // cond: x.Op != OpConst8 && sdivisibleOK(8,c) && !hasSmallRotate(config) // result: (Eq32 (Mod32 (SignExt8to32 x) (Const32 [c])) (Const32 [0])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMod8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } if !(x.Op != OpConst8 && sdivisibleOK(8, c) && !hasSmallRotate(config)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = c v0.AddArg(v2) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v3.AuxInt = 0 v.AddArg(v3) return true } return false } func rewriteValuegeneric_OpEq8_10(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Eq8 (Const8 [0]) (Mod8 x (Const8 [c]))) // cond: x.Op != OpConst8 && sdivisibleOK(8,c) && !hasSmallRotate(config) // result: (Eq32 (Mod32 (SignExt8to32 x) (Const32 [c])) (Const32 [0])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v_1 := v.Args[1] if v_1.Op != OpMod8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } c := v_1_1.AuxInt if !(x.Op != OpConst8 && sdivisibleOK(8, c) && !hasSmallRotate(config)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = c v0.AddArg(v2) v.AddArg(v0) v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v3.AuxInt = 0 v.AddArg(v3) return true } // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to8 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt8to32 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (ZeroExt8to32 x) (Const32 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpTrunc32to8 { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt8to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 x (Mul8 (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))) (Const8 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to8 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt8to32 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 x (Mul8 (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (ZeroExt8to32 x) (Const32 [m])) (Const64 [s]))) (Const8 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpTrunc32to8 { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32Ux64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt8to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to8 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt8to32 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (ZeroExt8to32 x) (Const32 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpTrunc32to8 { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32Ux64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt8to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 (Mul8 (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))) (Const8 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to8 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpZeroExt8to32 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 (Mul8 (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (ZeroExt8to32 x) (Const32 [m])) (Const64 [s]))) (Const8 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpTrunc32to8 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpZeroExt8to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int64(int8(udivisible(8, c).m)) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(8 - udivisible(8, c).k) v0.AddArg(v3) v.AddArg(v0) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(udivisible(8, c).max)) v.AddArg(v4) return true } // match: (Eq8 x (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub8 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpSignExt8to32 { break } if x != mul_1.Args[0] { break } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { break } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt8to32 { break } if x != v_1_1_1_0.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(int8(sdivisible(8, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(sdivisible(8, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v5.AuxInt = int64(8 - sdivisible(8, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v6.AuxInt = int64(int8(sdivisible(8, c).max)) v.AddArg(v6) return true } return false } func rewriteValuegeneric_OpEq8_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq8 x (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (SignExt8to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := v_1_0.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpSub8 { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { break } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpSignExt8to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { break } s := v_1_1_0_1.AuxInt v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { break } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt8to32 { break } if x != v_1_1_1_0.Args[0] { break } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 { break } if v_1_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(int8(sdivisible(8, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(sdivisible(8, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v5.AuxInt = int64(8 - sdivisible(8, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v6.AuxInt = int64(int8(sdivisible(8, c).max)) v.AddArg(v6) return true } // match: (Eq8 x (Mul8 (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) (Const8 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub8 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32x64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpSignExt8to32 { break } if x != mul_1.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh32x64 { break } _ = v_1_0_1.Args[1] v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpSignExt8to32 { break } if x != v_1_0_1_0.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 31 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(int8(sdivisible(8, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(sdivisible(8, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v5.AuxInt = int64(8 - sdivisible(8, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v6.AuxInt = int64(int8(sdivisible(8, c).max)) v.AddArg(v6) return true } // match: (Eq8 x (Mul8 (Sub8 (Rsh32x64 mul:(Mul32 (SignExt8to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) (Const8 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpSub8 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpRsh32x64 { break } _ = v_1_0_0.Args[1] mul := v_1_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpSignExt8to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpConst64 { break } s := v_1_0_0_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpRsh32x64 { break } _ = v_1_0_1.Args[1] v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpSignExt8to32 { break } if x != v_1_0_1_0.Args[0] { break } v_1_0_1_1 := v_1_0_1.Args[1] if v_1_0_1_1.Op != OpConst64 { break } if v_1_0_1_1.AuxInt != 31 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } c := v_1_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(int8(sdivisible(8, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(sdivisible(8, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v5.AuxInt = int64(8 - sdivisible(8, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v6.AuxInt = int64(int8(sdivisible(8, c).max)) v.AddArg(v6) return true } // match: (Eq8 (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub8 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32x64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpSignExt8to32 { break } if x != mul_1.Args[0] { break } v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh32x64 { break } _ = v_0_1_1.Args[1] v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpSignExt8to32 { break } if x != v_0_1_1_0.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(int8(sdivisible(8, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(sdivisible(8, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v5.AuxInt = int64(8 - sdivisible(8, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v6.AuxInt = int64(int8(sdivisible(8, c).max)) v.AddArg(v6) return true } // match: (Eq8 (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (SignExt8to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } c := v_0_0.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpSub8 { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpRsh32x64 { break } _ = v_0_1_0.Args[1] mul := v_0_1_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpSignExt8to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_1_0_1 := v_0_1_0.Args[1] if v_0_1_0_1.Op != OpConst64 { break } s := v_0_1_0_1.AuxInt v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpRsh32x64 { break } _ = v_0_1_1.Args[1] v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpSignExt8to32 { break } if x != v_0_1_1_0.Args[0] { break } v_0_1_1_1 := v_0_1_1.Args[1] if v_0_1_1_1.Op != OpConst64 { break } if v_0_1_1_1.AuxInt != 31 { break } if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(int8(sdivisible(8, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(sdivisible(8, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v5.AuxInt = int64(8 - sdivisible(8, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v6.AuxInt = int64(int8(sdivisible(8, c).max)) v.AddArg(v6) return true } // match: (Eq8 (Mul8 (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) (Const8 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub8 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32x64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpConst32 { break } m := mul_0.AuxInt mul_1 := mul.Args[1] if mul_1.Op != OpSignExt8to32 { break } if x != mul_1.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh32x64 { break } _ = v_0_0_1.Args[1] v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpSignExt8to32 { break } if x != v_0_0_1_0.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 31 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(int8(sdivisible(8, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(sdivisible(8, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v5.AuxInt = int64(8 - sdivisible(8, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v6.AuxInt = int64(int8(sdivisible(8, c).max)) v.AddArg(v6) return true } // match: (Eq8 (Mul8 (Sub8 (Rsh32x64 mul:(Mul32 (SignExt8to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) (Const8 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSub8 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpRsh32x64 { break } _ = v_0_0_0.Args[1] mul := v_0_0_0.Args[0] if mul.Op != OpMul32 { break } _ = mul.Args[1] mul_0 := mul.Args[0] if mul_0.Op != OpSignExt8to32 { break } if x != mul_0.Args[0] { break } mul_1 := mul.Args[1] if mul_1.Op != OpConst32 { break } m := mul_1.AuxInt v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpConst64 { break } s := v_0_0_0_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpRsh32x64 { break } _ = v_0_0_1.Args[1] v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpSignExt8to32 { break } if x != v_0_0_1_0.Args[0] { break } v_0_0_1_1 := v_0_0_1.Args[1] if v_0_0_1_1.Op != OpConst64 { break } if v_0_0_1_1.AuxInt != 31 { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c := v_0_1.AuxInt if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { break } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int64(int8(sdivisible(8, c).m)) v2.AddArg(v3) v2.AddArg(x) v1.AddArg(v2) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int64(int8(sdivisible(8, c).a)) v1.AddArg(v4) v0.AddArg(v1) v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v5.AuxInt = int64(8 - sdivisible(8, c).k) v0.AddArg(v5) v.AddArg(v0) v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v6.AuxInt = int64(int8(sdivisible(8, c).max)) v.AddArg(v6) return true } // match: (Eq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh8x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh8x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd8 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] if n != v_1_0_0.Args[0] { break } v_1_0_0_1 := v_1_0_0.Args[1] if v_1_0_0_1.Op != OpRsh8Ux64 { break } if v_1_0_0_1.Type != t { break } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh8x64 { break } if v_1_0_0_1_0.Type != t { break } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { break } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 { break } if v_1_0_0_1_0_1.Type != typ.UInt64 { break } if v_1_0_0_1_0_1.AuxInt != 7 { break } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 { break } if v_1_0_0_1_1.Type != typ.UInt64 { break } kbar := v_1_0_0_1_1.AuxInt v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 7 && kbar == 8-k) { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int64(1< (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [int64(1< [0])) for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLsh8x64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh8x64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd8 { break } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpRsh8Ux64 { break } if v_1_0_0_0.Type != t { break } _ = v_1_0_0_0.Args[1] v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpRsh8x64 { break } if v_1_0_0_0_0.Type != t { break } _ = v_1_0_0_0_0.Args[1] if n != v_1_0_0_0_0.Args[0] { break } v_1_0_0_0_0_1 := v_1_0_0_0_0.Args[1] if v_1_0_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_0_1.Type != typ.UInt64 { break } if v_1_0_0_0_0_1.AuxInt != 7 { break } v_1_0_0_0_1 := v_1_0_0_0.Args[1] if v_1_0_0_0_1.Op != OpConst64 { break } if v_1_0_0_0_1.Type != typ.UInt64 { break } kbar := v_1_0_0_0_1.AuxInt if n != v_1_0_0.Args[1] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 { break } if v_1_0_1.Type != typ.UInt64 { break } k := v_1_0_1.AuxInt v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != typ.UInt64 { break } if v_1_1.AuxInt != k { break } if !(k > 0 && k < 7 && kbar == 8-k) { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int64(1< n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh8x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd8 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] if n != v_0_0_0.Args[0] { break } v_0_0_0_1 := v_0_0_0.Args[1] if v_0_0_0_1.Op != OpRsh8Ux64 { break } if v_0_0_0_1.Type != t { break } _ = v_0_0_0_1.Args[1] v_0_0_0_1_0 := v_0_0_0_1.Args[0] if v_0_0_0_1_0.Op != OpRsh8x64 { break } if v_0_0_0_1_0.Type != t { break } _ = v_0_0_0_1_0.Args[1] if n != v_0_0_0_1_0.Args[0] { break } v_0_0_0_1_0_1 := v_0_0_0_1_0.Args[1] if v_0_0_0_1_0_1.Op != OpConst64 { break } if v_0_0_0_1_0_1.Type != typ.UInt64 { break } if v_0_0_0_1_0_1.AuxInt != 7 { break } v_0_0_0_1_1 := v_0_0_0_1.Args[1] if v_0_0_0_1_1.Op != OpConst64 { break } if v_0_0_0_1_1.Type != typ.UInt64 { break } kbar := v_0_0_0_1_1.AuxInt v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 7 && kbar == 8-k) { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int64(1< (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [int64(1< [0])) for { n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh8x64 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAdd8 { break } t := v_0_0_0.Type _ = v_0_0_0.Args[1] v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpRsh8Ux64 { break } if v_0_0_0_0.Type != t { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpRsh8x64 { break } if v_0_0_0_0_0.Type != t { break } _ = v_0_0_0_0_0.Args[1] if n != v_0_0_0_0_0.Args[0] { break } v_0_0_0_0_0_1 := v_0_0_0_0_0.Args[1] if v_0_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_0_1.Type != typ.UInt64 { break } if v_0_0_0_0_0_1.AuxInt != 7 { break } v_0_0_0_0_1 := v_0_0_0_0.Args[1] if v_0_0_0_0_1.Op != OpConst64 { break } if v_0_0_0_0_1.Type != typ.UInt64 { break } kbar := v_0_0_0_0_1.AuxInt if n != v_0_0_0.Args[1] { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } if v_0_0_1.Type != typ.UInt64 { break } k := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != typ.UInt64 { break } if v_0_1.AuxInt != k { break } if !(k > 0 && k < 7 && kbar == 8-k) { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int64(1<= d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c >= d) return true } // match: (Geq16 (And16 _ (Const16 [c])) (Const16 [0])) // cond: int16(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } if !(int16(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (Geq16 (And16 (Const16 [c]) _) (Const16 [0])) // cond: int16(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } if !(int16(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } return false } func rewriteValuegeneric_OpGeq16U_0(v *Value) bool { // match: (Geq16U (Const16 [c]) (Const16 [d])) // cond: // result: (ConstBool [b2i(uint16(c) >= uint16(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint16(c) >= uint16(d)) return true } return false } func rewriteValuegeneric_OpGeq32_0(v *Value) bool { // match: (Geq32 (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(c >= d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c >= d) return true } // match: (Geq32 (And32 _ (Const32 [c])) (Const32 [0])) // cond: int32(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } if !(int32(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (Geq32 (And32 (Const32 [c]) _) (Const32 [0])) // cond: int32(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } if !(int32(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } return false } func rewriteValuegeneric_OpGeq32F_0(v *Value) bool { // match: (Geq32F (Const32F [c]) (Const32F [d])) // cond: // result: (ConstBool [b2i(auxTo32F(c) >= auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo32F(c) >= auxTo32F(d)) return true } return false } func rewriteValuegeneric_OpGeq32U_0(v *Value) bool { // match: (Geq32U (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(uint32(c) >= uint32(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint32(c) >= uint32(d)) return true } return false } func rewriteValuegeneric_OpGeq64_0(v *Value) bool { // match: (Geq64 (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(c >= d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c >= d) return true } // match: (Geq64 (And64 _ (Const64 [c])) (Const64 [0])) // cond: int64(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } if !(int64(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (Geq64 (And64 (Const64 [c]) _) (Const64 [0])) // cond: int64(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } if !(int64(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (Geq64 (Rsh64Ux64 _ (Const64 [c])) (Const64 [0])) // cond: c > 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } return false } func rewriteValuegeneric_OpGeq64F_0(v *Value) bool { // match: (Geq64F (Const64F [c]) (Const64F [d])) // cond: // result: (ConstBool [b2i(auxTo64F(c) >= auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo64F(c) >= auxTo64F(d)) return true } return false } func rewriteValuegeneric_OpGeq64U_0(v *Value) bool { // match: (Geq64U (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(uint64(c) >= uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint64(c) >= uint64(d)) return true } return false } func rewriteValuegeneric_OpGeq8_0(v *Value) bool { // match: (Geq8 (Const8 [c]) (Const8 [d])) // cond: // result: (ConstBool [b2i(c >= d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c >= d) return true } // match: (Geq8 (And8 _ (Const8 [c])) (Const8 [0])) // cond: int8(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } if !(int8(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (Geq8 (And8 (Const8 [c]) _) (Const8 [0])) // cond: int8(c) >= 0 // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } if !(int8(c) >= 0) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } return false } func rewriteValuegeneric_OpGeq8U_0(v *Value) bool { // match: (Geq8U (Const8 [c]) (Const8 [d])) // cond: // result: (ConstBool [b2i(uint8(c) >= uint8(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint8(c) >= uint8(d)) return true } return false } func rewriteValuegeneric_OpGreater16_0(v *Value) bool { // match: (Greater16 (Const16 [c]) (Const16 [d])) // cond: // result: (ConstBool [b2i(c > d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c > d) return true } return false } func rewriteValuegeneric_OpGreater16U_0(v *Value) bool { // match: (Greater16U (Const16 [c]) (Const16 [d])) // cond: // result: (ConstBool [b2i(uint16(c) > uint16(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint16(c) > uint16(d)) return true } return false } func rewriteValuegeneric_OpGreater32_0(v *Value) bool { // match: (Greater32 (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(c > d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c > d) return true } return false } func rewriteValuegeneric_OpGreater32F_0(v *Value) bool { // match: (Greater32F (Const32F [c]) (Const32F [d])) // cond: // result: (ConstBool [b2i(auxTo32F(c) > auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo32F(c) > auxTo32F(d)) return true } return false } func rewriteValuegeneric_OpGreater32U_0(v *Value) bool { // match: (Greater32U (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(uint32(c) > uint32(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint32(c) > uint32(d)) return true } return false } func rewriteValuegeneric_OpGreater64_0(v *Value) bool { // match: (Greater64 (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(c > d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c > d) return true } return false } func rewriteValuegeneric_OpGreater64F_0(v *Value) bool { // match: (Greater64F (Const64F [c]) (Const64F [d])) // cond: // result: (ConstBool [b2i(auxTo64F(c) > auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo64F(c) > auxTo64F(d)) return true } return false } func rewriteValuegeneric_OpGreater64U_0(v *Value) bool { // match: (Greater64U (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(uint64(c) > uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint64(c) > uint64(d)) return true } return false } func rewriteValuegeneric_OpGreater8_0(v *Value) bool { // match: (Greater8 (Const8 [c]) (Const8 [d])) // cond: // result: (ConstBool [b2i(c > d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c > d) return true } return false } func rewriteValuegeneric_OpGreater8U_0(v *Value) bool { // match: (Greater8U (Const8 [c]) (Const8 [d])) // cond: // result: (ConstBool [b2i(uint8(c) > uint8(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(uint8(c) > uint8(d)) return true } return false } func rewriteValuegeneric_OpIMake_0(v *Value) bool { // match: (IMake typ (StructMake1 val)) // cond: // result: (IMake typ val) for { _ = v.Args[1] typ := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStructMake1 { break } val := v_1.Args[0] v.reset(OpIMake) v.AddArg(typ) v.AddArg(val) return true } // match: (IMake typ (ArrayMake1 val)) // cond: // result: (IMake typ val) for { _ = v.Args[1] typ := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpArrayMake1 { break } val := v_1.Args[0] v.reset(OpIMake) v.AddArg(typ) v.AddArg(val) return true } return false } func rewriteValuegeneric_OpInterCall_0(v *Value) bool { // match: (InterCall [argsize] (Load (OffPtr [off] (ITab (IMake (Addr {itab} (SB)) _))) _) mem) // cond: devirt(v, itab, off) != nil // result: (StaticCall [argsize] {devirt(v, itab, off)} mem) for { argsize := v.AuxInt mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLoad { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpOffPtr { break } off := v_0_0.AuxInt v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpITab { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpIMake { break } _ = v_0_0_0_0.Args[1] v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAddr { break } itab := v_0_0_0_0_0.Aux v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpSB { break } if !(devirt(v, itab, off) != nil) { break } v.reset(OpStaticCall) v.AuxInt = argsize v.Aux = devirt(v, itab, off) v.AddArg(mem) return true } return false } func rewriteValuegeneric_OpIsInBounds_0(v *Value) bool { // match: (IsInBounds (ZeroExt8to32 _) (Const32 [c])) // cond: (1 << 8) <= c // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to32 { break } v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !((1 << 8) <= c) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to64 _) (Const64 [c])) // cond: (1 << 8) <= c // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to64 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !((1 << 8) <= c) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt16to32 _) (Const32 [c])) // cond: (1 << 16) <= c // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt16to32 { break } v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !((1 << 16) <= c) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt16to64 _) (Const64 [c])) // cond: (1 << 16) <= c // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt16to64 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !((1 << 16) <= c) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds x x) // cond: // result: (ConstBool [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (IsInBounds (And8 (Const8 [c]) _) (Const8 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (And8 _ (Const8 [c])) (Const8 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to16 (And8 (Const8 [c]) _)) (Const16 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpConst8 { break } c := v_0_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to16 (And8 _ (Const8 [c]))) (Const16 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } _ = v_0_0.Args[1] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst8 { break } c := v_0_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to32 (And8 (Const8 [c]) _)) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpConst8 { break } c := v_0_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } return false } func rewriteValuegeneric_OpIsInBounds_10(v *Value) bool { // match: (IsInBounds (ZeroExt8to32 (And8 _ (Const8 [c]))) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } _ = v_0_0.Args[1] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst8 { break } c := v_0_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to64 (And8 (Const8 [c]) _)) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpConst8 { break } c := v_0_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to64 (And8 _ (Const8 [c]))) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt8to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } _ = v_0_0.Args[1] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst8 { break } c := v_0_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (And16 (Const16 [c]) _) (Const16 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (And16 _ (Const16 [c])) (Const16 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt16to32 (And16 (Const16 [c]) _)) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt16to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpConst16 { break } c := v_0_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt16to32 (And16 _ (Const16 [c]))) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt16to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } _ = v_0_0.Args[1] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst16 { break } c := v_0_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt16to64 (And16 (Const16 [c]) _)) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt16to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpConst16 { break } c := v_0_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt16to64 (And16 _ (Const16 [c]))) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt16to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } _ = v_0_0.Args[1] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst16 { break } c := v_0_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (And32 (Const32 [c]) _) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } return false } func rewriteValuegeneric_OpIsInBounds_20(v *Value) bool { // match: (IsInBounds (And32 _ (Const32 [c])) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt32to64 (And32 (Const32 [c]) _)) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt32to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd32 { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpConst32 { break } c := v_0_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt32to64 (And32 _ (Const32 [c]))) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpZeroExt32to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd32 { break } _ = v_0_0.Args[1] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst32 { break } c := v_0_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (And64 (Const64 [c]) _) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (And64 _ (Const64 [c])) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(0 <= c && c < d) { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(0 <= c && c < d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(0 <= c && c < d) return true } // match: (IsInBounds (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(0 <= c && c < d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(0 <= c && c < d) return true } // match: (IsInBounds (Mod32u _ y) y) // cond: // result: (ConstBool [1]) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMod32u { break } _ = v_0.Args[1] if y != v_0.Args[1] { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (Mod64u _ y) y) // cond: // result: (ConstBool [1]) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMod64u { break } _ = v_0.Args[1] if y != v_0.Args[1] { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (IsInBounds (ZeroExt8to64 (Rsh8Ux64 _ (Const64 [c]))) (Const64 [d])) // cond: 0 < c && c < 8 && 1< p1 (Store {t2} p2 x _)) // cond: isSamePtr(p1, p2) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) // result: x for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] x := v_1.Args[1] if !(isSamePtr(p1, p2) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 x _))) // cond: isSamePtr(p1, p3) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) && disjoint(p3, sizeof(t3), p2, sizeof(t2)) // result: x for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := v_1_2.Aux _ = v_1_2.Args[2] p3 := v_1_2.Args[0] x := v_1_2.Args[1] if !(isSamePtr(p1, p3) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) && disjoint(p3, sizeof(t3), p2, sizeof(t2))) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 x _)))) // cond: isSamePtr(p1, p4) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) && disjoint(p4, sizeof(t4), p2, sizeof(t2)) && disjoint(p4, sizeof(t4), p3, sizeof(t3)) // result: x for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := v_1_2.Aux _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := v_1_2_2.Aux _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] x := v_1_2_2.Args[1] if !(isSamePtr(p1, p4) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) && disjoint(p4, sizeof(t4), p2, sizeof(t2)) && disjoint(p4, sizeof(t4), p3, sizeof(t3))) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 x _))))) // cond: isSamePtr(p1, p5) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) && disjoint(p5, sizeof(t5), p2, sizeof(t2)) && disjoint(p5, sizeof(t5), p3, sizeof(t3)) && disjoint(p5, sizeof(t5), p4, sizeof(t4)) // result: x for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := v_1_2.Aux _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := v_1_2_2.Aux _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] v_1_2_2_2 := v_1_2_2.Args[2] if v_1_2_2_2.Op != OpStore { break } t5 := v_1_2_2_2.Aux _ = v_1_2_2_2.Args[2] p5 := v_1_2_2_2.Args[0] x := v_1_2_2_2.Args[1] if !(isSamePtr(p1, p5) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == sizeof(t2) && disjoint(p5, sizeof(t5), p2, sizeof(t2)) && disjoint(p5, sizeof(t5), p3, sizeof(t3)) && disjoint(p5, sizeof(t5), p4, sizeof(t4))) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Load p1 (Store {t2} p2 (Const64 [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitFloat(t1) // result: (Const64F [x]) for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } x := v_1_1.AuxInt if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitFloat(t1)) { break } v.reset(OpConst64F) v.AuxInt = x return true } // match: (Load p1 (Store {t2} p2 (Const32 [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitFloat(t1) // result: (Const32F [auxFrom32F(math.Float32frombits(uint32(x)))]) for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } x := v_1_1.AuxInt if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitFloat(t1)) { break } v.reset(OpConst32F) v.AuxInt = auxFrom32F(math.Float32frombits(uint32(x))) return true } // match: (Load p1 (Store {t2} p2 (Const64F [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitInt(t1) // result: (Const64 [x]) for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64F { break } x := v_1_1.AuxInt if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitInt(t1)) { break } v.reset(OpConst64) v.AuxInt = x return true } // match: (Load p1 (Store {t2} p2 (Const32F [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitInt(t1) // result: (Const32 [int64(int32(math.Float32bits(auxTo32F(x))))]) for { t1 := v.Type _ = v.Args[1] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32F { break } x := v_1_1.AuxInt if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitInt(t1)) { break } v.reset(OpConst32) v.AuxInt = int64(int32(math.Float32bits(auxTo32F(x)))) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ mem:(Zero [n] p3 _))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p3) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) // result: @mem.Block (Load (OffPtr [o1] p3) mem) for { t1 := v.Type _ = v.Args[1] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] mem := v_1.Args[2] if mem.Op != OpZero { break } n := mem.AuxInt _ = mem.Args[1] p3 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p3) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2))) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = o1 v1.AddArg(p3) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ mem:(Zero [n] p4 _)))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p4) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) && disjoint(op, t1.Size(), p3, sizeof(t3)) // result: @mem.Block (Load (OffPtr [o1] p4) mem) for { t1 := v.Type _ = v.Args[1] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := v_1_2.Aux _ = v_1_2.Args[2] p3 := v_1_2.Args[0] mem := v_1_2.Args[2] if mem.Op != OpZero { break } n := mem.AuxInt _ = mem.Args[1] p4 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p4) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) && disjoint(op, t1.Size(), p3, sizeof(t3))) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = o1 v1.AddArg(p4) v0.AddArg(v1) v0.AddArg(mem) return true } return false } func rewriteValuegeneric_OpLoad_10(v *Value) bool { b := v.Block fe := b.Func.fe // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ mem:(Zero [n] p5 _))))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p5) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) && disjoint(op, t1.Size(), p3, sizeof(t3)) && disjoint(op, t1.Size(), p4, sizeof(t4)) // result: @mem.Block (Load (OffPtr [o1] p5) mem) for { t1 := v.Type _ = v.Args[1] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := v_1_2.Aux _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := v_1_2_2.Aux _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] mem := v_1_2_2.Args[2] if mem.Op != OpZero { break } n := mem.AuxInt _ = mem.Args[1] p5 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p5) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) && disjoint(op, t1.Size(), p3, sizeof(t3)) && disjoint(op, t1.Size(), p4, sizeof(t4))) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = o1 v1.AddArg(p5) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 _ mem:(Zero [n] p6 _)))))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p6) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) && disjoint(op, t1.Size(), p3, sizeof(t3)) && disjoint(op, t1.Size(), p4, sizeof(t4)) && disjoint(op, t1.Size(), p5, sizeof(t5)) // result: @mem.Block (Load (OffPtr [o1] p6) mem) for { t1 := v.Type _ = v.Args[1] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] v_1 := v.Args[1] if v_1.Op != OpStore { break } t2 := v_1.Aux _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := v_1_2.Aux _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := v_1_2_2.Aux _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] v_1_2_2_2 := v_1_2_2.Args[2] if v_1_2_2_2.Op != OpStore { break } t5 := v_1_2_2_2.Aux _ = v_1_2_2_2.Args[2] p5 := v_1_2_2_2.Args[0] mem := v_1_2_2_2.Args[2] if mem.Op != OpZero { break } n := mem.AuxInt _ = mem.Args[1] p6 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p6) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, sizeof(t2)) && disjoint(op, t1.Size(), p3, sizeof(t3)) && disjoint(op, t1.Size(), p4, sizeof(t4)) && disjoint(op, t1.Size(), p5, sizeof(t5))) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = o1 v1.AddArg(p6) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: t1.IsBoolean() && isSamePtr(p1, p2) && n >= o + 1 // result: (ConstBool [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(t1.IsBoolean() && isSamePtr(p1, p2) && n >= o+1) { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is8BitInt(t1) && isSamePtr(p1, p2) && n >= o + 1 // result: (Const8 [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(is8BitInt(t1) && isSamePtr(p1, p2) && n >= o+1) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is16BitInt(t1) && isSamePtr(p1, p2) && n >= o + 2 // result: (Const16 [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(is16BitInt(t1) && isSamePtr(p1, p2) && n >= o+2) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is32BitInt(t1) && isSamePtr(p1, p2) && n >= o + 4 // result: (Const32 [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(is32BitInt(t1) && isSamePtr(p1, p2) && n >= o+4) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is64BitInt(t1) && isSamePtr(p1, p2) && n >= o + 8 // result: (Const64 [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(is64BitInt(t1) && isSamePtr(p1, p2) && n >= o+8) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is32BitFloat(t1) && isSamePtr(p1, p2) && n >= o + 4 // result: (Const32F [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(is32BitFloat(t1) && isSamePtr(p1, p2) && n >= o+4) { break } v.reset(OpConst32F) v.AuxInt = 0 return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is64BitFloat(t1) && isSamePtr(p1, p2) && n >= o + 8 // result: (Const64F [0]) for { t1 := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpZero { break } n := v_1.AuxInt _ = v_1.Args[1] p2 := v_1.Args[0] if !(is64BitFloat(t1) && isSamePtr(p1, p2) && n >= o+8) { break } v.reset(OpConst64F) v.AuxInt = 0 return true } // match: (Load _ _) // cond: t.IsStruct() && t.NumFields() == 0 && fe.CanSSA(t) // result: (StructMake0) for { t := v.Type _ = v.Args[1] if !(t.IsStruct() && t.NumFields() == 0 && fe.CanSSA(t)) { break } v.reset(OpStructMake0) return true } return false } func rewriteValuegeneric_OpLoad_20(v *Value) bool { b := v.Block fe := b.Func.fe // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 1 && fe.CanSSA(t) // result: (StructMake1 (Load (OffPtr [0] ptr) mem)) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsStruct() && t.NumFields() == 1 && fe.CanSSA(t)) { break } v.reset(OpStructMake1) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = 0 v1.AddArg(ptr) v0.AddArg(v1) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 2 && fe.CanSSA(t) // result: (StructMake2 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem)) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsStruct() && t.NumFields() == 2 && fe.CanSSA(t)) { break } v.reset(OpStructMake2) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = 0 v1.AddArg(ptr) v0.AddArg(v1) v0.AddArg(mem) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = t.FieldOff(1) v3.AddArg(ptr) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 3 && fe.CanSSA(t) // result: (StructMake3 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem) (Load (OffPtr [t.FieldOff(2)] ptr) mem)) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsStruct() && t.NumFields() == 3 && fe.CanSSA(t)) { break } v.reset(OpStructMake3) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = 0 v1.AddArg(ptr) v0.AddArg(v1) v0.AddArg(mem) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = t.FieldOff(1) v3.AddArg(ptr) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2)) v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v5.AuxInt = t.FieldOff(2) v5.AddArg(ptr) v4.AddArg(v5) v4.AddArg(mem) v.AddArg(v4) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 4 && fe.CanSSA(t) // result: (StructMake4 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem) (Load (OffPtr [t.FieldOff(2)] ptr) mem) (Load (OffPtr [t.FieldOff(3)] ptr) mem)) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsStruct() && t.NumFields() == 4 && fe.CanSSA(t)) { break } v.reset(OpStructMake4) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = 0 v1.AddArg(ptr) v0.AddArg(v1) v0.AddArg(mem) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = t.FieldOff(1) v3.AddArg(ptr) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2)) v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v5.AuxInt = t.FieldOff(2) v5.AddArg(ptr) v4.AddArg(v5) v4.AddArg(mem) v.AddArg(v4) v6 := b.NewValue0(v.Pos, OpLoad, t.FieldType(3)) v7 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo()) v7.AuxInt = t.FieldOff(3) v7.AddArg(ptr) v6.AddArg(v7) v6.AddArg(mem) v.AddArg(v6) return true } // match: (Load _ _) // cond: t.IsArray() && t.NumElem() == 0 // result: (ArrayMake0) for { t := v.Type _ = v.Args[1] if !(t.IsArray() && t.NumElem() == 0) { break } v.reset(OpArrayMake0) return true } // match: (Load ptr mem) // cond: t.IsArray() && t.NumElem() == 1 && fe.CanSSA(t) // result: (ArrayMake1 (Load ptr mem)) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsArray() && t.NumElem() == 1 && fe.CanSSA(t)) { break } v.reset(OpArrayMake1) v0 := b.NewValue0(v.Pos, OpLoad, t.Elem()) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh16x16_0(v *Value) bool { b := v.Block // match: (Lsh16x16 x (Const16 [c])) // cond: // result: (Lsh16x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpLsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Lsh16x16 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh16x32_0(v *Value) bool { b := v.Block // match: (Lsh16x32 x (Const32 [c])) // cond: // result: (Lsh16x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpLsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Lsh16x32 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh16x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x64 (Const16 [c]) (Const64 [d])) // cond: // result: (Const16 [int64(int16(c) << uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c) << uint64(d)) return true } // match: (Lsh16x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Lsh16x64 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Lsh16x64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Lsh16x64 (Lsh16x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh16x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpLsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Lsh16x64 (Rsh16Ux64 (Lsh16x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh16x64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh16x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh16x8_0(v *Value) bool { b := v.Block // match: (Lsh16x8 x (Const8 [c])) // cond: // result: (Lsh16x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpLsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Lsh16x8 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh32x16_0(v *Value) bool { b := v.Block // match: (Lsh32x16 x (Const16 [c])) // cond: // result: (Lsh32x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpLsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Lsh32x16 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh32x32_0(v *Value) bool { b := v.Block // match: (Lsh32x32 x (Const32 [c])) // cond: // result: (Lsh32x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpLsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Lsh32x32 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh32x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x64 (Const32 [c]) (Const64 [d])) // cond: // result: (Const32 [int64(int32(c) << uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c) << uint64(d)) return true } // match: (Lsh32x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Lsh32x64 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Lsh32x64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Lsh32x64 (Lsh32x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh32x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpLsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Lsh32x64 (Rsh32Ux64 (Lsh32x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh32x64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh32x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh32x8_0(v *Value) bool { b := v.Block // match: (Lsh32x8 x (Const8 [c])) // cond: // result: (Lsh32x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpLsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Lsh32x8 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh64x16_0(v *Value) bool { b := v.Block // match: (Lsh64x16 x (Const16 [c])) // cond: // result: (Lsh64x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpLsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Lsh64x16 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh64x32_0(v *Value) bool { b := v.Block // match: (Lsh64x32 x (Const32 [c])) // cond: // result: (Lsh64x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpLsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Lsh64x32 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh64x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c << uint64(d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c << uint64(d) return true } // match: (Lsh64x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Lsh64x64 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Lsh64x64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (Const64 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Lsh64x64 (Lsh64x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh64x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpLsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Lsh64x64 (Rsh64Ux64 (Lsh64x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh64x64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh64x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh64x8_0(v *Value) bool { b := v.Block // match: (Lsh64x8 x (Const8 [c])) // cond: // result: (Lsh64x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpLsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Lsh64x8 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh8x16_0(v *Value) bool { b := v.Block // match: (Lsh8x16 x (Const16 [c])) // cond: // result: (Lsh8x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpLsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Lsh8x16 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh8x32_0(v *Value) bool { b := v.Block // match: (Lsh8x32 x (Const32 [c])) // cond: // result: (Lsh8x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpLsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Lsh8x32 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpLsh8x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x64 (Const8 [c]) (Const64 [d])) // cond: // result: (Const8 [int64(int8(c) << uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c) << uint64(d)) return true } // match: (Lsh8x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Lsh8x64 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Lsh8x64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Lsh8x64 (Lsh8x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh8x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpLsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Lsh8x64 (Rsh8Ux64 (Lsh8x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh8x64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh8x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh8x8_0(v *Value) bool { b := v.Block // match: (Lsh8x8 x (Const8 [c])) // cond: // result: (Lsh8x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpLsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Lsh8x8 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpMod16_0(v *Value) bool { b := v.Block // match: (Mod16 (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int64(int16(c % d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int64(int16(c % d)) return true } // match: (Mod16 n (Const16 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c&0xffff) // result: (And16 n (Const16 [(c&0xffff)-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c&0xffff)) { break } v.reset(OpAnd16) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = (c & 0xffff) - 1 v.AddArg(v0) return true } // match: (Mod16 n (Const16 [c])) // cond: c < 0 && c != -1<<15 // result: (Mod16 n (Const16 [-c])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<15) { break } v.reset(OpMod16) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = -c v.AddArg(v0) return true } // match: (Mod16 x (Const16 [c])) // cond: x.Op != OpConst16 && (c > 0 || c == -1<<15) // result: (Sub16 x (Mul16 (Div16 x (Const16 [c])) (Const16 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(x.Op != OpConst16 && (c > 0 || c == -1<<15)) { break } v.reset(OpSub16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul16, t) v1 := b.NewValue0(v.Pos, OpDiv16, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod16u_0(v *Value) bool { b := v.Block // match: (Mod16u (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int64(uint16(c) % uint16(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int64(uint16(c) % uint16(d)) return true } // match: (Mod16u n (Const16 [c])) // cond: isPowerOfTwo(c&0xffff) // result: (And16 n (Const16 [(c&0xffff)-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(isPowerOfTwo(c & 0xffff)) { break } v.reset(OpAnd16) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = (c & 0xffff) - 1 v.AddArg(v0) return true } // match: (Mod16u x (Const16 [c])) // cond: x.Op != OpConst16 && c > 0 && umagicOK(16,c) // result: (Sub16 x (Mul16 (Div16u x (Const16 [c])) (Const16 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(x.Op != OpConst16 && c > 0 && umagicOK(16, c)) { break } v.reset(OpSub16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul16, t) v1 := b.NewValue0(v.Pos, OpDiv16u, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst16, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod32_0(v *Value) bool { b := v.Block // match: (Mod32 (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int64(int32(c % d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int64(int32(c % d)) return true } // match: (Mod32 n (Const32 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c&0xffffffff) // result: (And32 n (Const32 [(c&0xffffffff)-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c&0xffffffff)) { break } v.reset(OpAnd32) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = (c & 0xffffffff) - 1 v.AddArg(v0) return true } // match: (Mod32 n (Const32 [c])) // cond: c < 0 && c != -1<<31 // result: (Mod32 n (Const32 [-c])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<31) { break } v.reset(OpMod32) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = -c v.AddArg(v0) return true } // match: (Mod32 x (Const32 [c])) // cond: x.Op != OpConst32 && (c > 0 || c == -1<<31) // result: (Sub32 x (Mul32 (Div32 x (Const32 [c])) (Const32 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(x.Op != OpConst32 && (c > 0 || c == -1<<31)) { break } v.reset(OpSub32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul32, t) v1 := b.NewValue0(v.Pos, OpDiv32, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod32u_0(v *Value) bool { b := v.Block // match: (Mod32u (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int64(uint32(c) % uint32(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int64(uint32(c) % uint32(d)) return true } // match: (Mod32u n (Const32 [c])) // cond: isPowerOfTwo(c&0xffffffff) // result: (And32 n (Const32 [(c&0xffffffff)-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(isPowerOfTwo(c & 0xffffffff)) { break } v.reset(OpAnd32) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = (c & 0xffffffff) - 1 v.AddArg(v0) return true } // match: (Mod32u x (Const32 [c])) // cond: x.Op != OpConst32 && c > 0 && umagicOK(32,c) // result: (Sub32 x (Mul32 (Div32u x (Const32 [c])) (Const32 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(x.Op != OpConst32 && c > 0 && umagicOK(32, c)) { break } v.reset(OpSub32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul32, t) v1 := b.NewValue0(v.Pos, OpDiv32u, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst32, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod64_0(v *Value) bool { b := v.Block // match: (Mod64 (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [c % d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = c % d return true } // match: (Mod64 n (Const64 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c) // result: (And64 n (Const64 [c-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c)) { break } v.reset(OpAnd64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - 1 v.AddArg(v0) return true } // match: (Mod64 n (Const64 [-1<<63])) // cond: isNonNegative(n) // result: n for { _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1<<63 { break } if !(isNonNegative(n)) { break } v.reset(OpCopy) v.Type = n.Type v.AddArg(n) return true } // match: (Mod64 n (Const64 [c])) // cond: c < 0 && c != -1<<63 // result: (Mod64 n (Const64 [-c])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<63) { break } v.reset(OpMod64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = -c v.AddArg(v0) return true } // match: (Mod64 x (Const64 [c])) // cond: x.Op != OpConst64 && (c > 0 || c == -1<<63) // result: (Sub64 x (Mul64 (Div64 x (Const64 [c])) (Const64 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(x.Op != OpConst64 && (c > 0 || c == -1<<63)) { break } v.reset(OpSub64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul64, t) v1 := b.NewValue0(v.Pos, OpDiv64, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod64u_0(v *Value) bool { b := v.Block // match: (Mod64u (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [int64(uint64(c) % uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64(uint64(c) % uint64(d)) return true } // match: (Mod64u n (Const64 [c])) // cond: isPowerOfTwo(c) // result: (And64 n (Const64 [c-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpAnd64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - 1 v.AddArg(v0) return true } // match: (Mod64u n (Const64 [-1<<63])) // cond: // result: (And64 n (Const64 [1<<63-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1<<63 { break } v.reset(OpAnd64) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = 1<<63 - 1 v.AddArg(v0) return true } // match: (Mod64u x (Const64 [c])) // cond: x.Op != OpConst64 && c > 0 && umagicOK(64,c) // result: (Sub64 x (Mul64 (Div64u x (Const64 [c])) (Const64 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(x.Op != OpConst64 && c > 0 && umagicOK(64, c)) { break } v.reset(OpSub64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul64, t) v1 := b.NewValue0(v.Pos, OpDiv64u, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst64, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod8_0(v *Value) bool { b := v.Block // match: (Mod8 (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int64(int8(c % d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int64(int8(c % d)) return true } // match: (Mod8 n (Const8 [c])) // cond: isNonNegative(n) && isPowerOfTwo(c&0xff) // result: (And8 n (Const8 [(c&0xff)-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(isNonNegative(n) && isPowerOfTwo(c&0xff)) { break } v.reset(OpAnd8) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = (c & 0xff) - 1 v.AddArg(v0) return true } // match: (Mod8 n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Mod8 n (Const8 [-c])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(c < 0 && c != -1<<7) { break } v.reset(OpMod8) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = -c v.AddArg(v0) return true } // match: (Mod8 x (Const8 [c])) // cond: x.Op != OpConst8 && (c > 0 || c == -1<<7) // result: (Sub8 x (Mul8 (Div8 x (Const8 [c])) (Const8 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(x.Op != OpConst8 && (c > 0 || c == -1<<7)) { break } v.reset(OpSub8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul8, t) v1 := b.NewValue0(v.Pos, OpDiv8, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMod8u_0(v *Value) bool { b := v.Block // match: (Mod8u (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int64(uint8(c) % uint8(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int64(uint8(c) % uint8(d)) return true } // match: (Mod8u n (Const8 [c])) // cond: isPowerOfTwo(c&0xff) // result: (And8 n (Const8 [(c&0xff)-1])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(isPowerOfTwo(c & 0xff)) { break } v.reset(OpAnd8) v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = (c & 0xff) - 1 v.AddArg(v0) return true } // match: (Mod8u x (Const8 [c])) // cond: x.Op != OpConst8 && c > 0 && umagicOK(8, c) // result: (Sub8 x (Mul8 (Div8u x (Const8 [c])) (Const8 [c]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(x.Op != OpConst8 && c > 0 && umagicOK(8, c)) { break } v.reset(OpSub8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpMul8, t) v1 := b.NewValue0(v.Pos, OpDiv8u, t) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = c v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpConst8, t) v3.AuxInt = c v0.AddArg(v3) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMove_0(v *Value) bool { b := v.Block // match: (Move {t} [n] dst1 src mem:(Zero {t} [n] dst2 _)) // cond: isSamePtr(src, dst2) // result: (Zero {t} [n] dst1 mem) for { n := v.AuxInt t := v.Aux _ = v.Args[2] dst1 := v.Args[0] src := v.Args[1] mem := v.Args[2] if mem.Op != OpZero { break } if mem.AuxInt != n { break } if mem.Aux != t { break } _ = mem.Args[1] dst2 := mem.Args[0] if !(isSamePtr(src, dst2)) { break } v.reset(OpZero) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(mem) return true } // match: (Move {t} [n] dst1 src mem:(VarDef (Zero {t} [n] dst0 _))) // cond: isSamePtr(src, dst0) // result: (Zero {t} [n] dst1 mem) for { n := v.AuxInt t := v.Aux _ = v.Args[2] dst1 := v.Args[0] src := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpZero { break } if mem_0.AuxInt != n { break } if mem_0.Aux != t { break } _ = mem_0.Args[1] dst0 := mem_0.Args[0] if !(isSamePtr(src, dst0)) { break } v.reset(OpZero) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(mem) return true } // match: (Move {t1} [n] dst1 src1 store:(Store {t2} op:(OffPtr [o2] dst2) _ mem)) // cond: isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2 + sizeof(t2) && disjoint(src1, n, op, sizeof(t2)) && clobber(store) // result: (Move {t1} [n] dst1 src1 mem) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst1 := v.Args[0] src1 := v.Args[1] store := v.Args[2] if store.Op != OpStore { break } t2 := store.Aux mem := store.Args[2] op := store.Args[0] if op.Op != OpOffPtr { break } o2 := op.AuxInt dst2 := op.Args[0] if !(isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2+sizeof(t2) && disjoint(src1, n, op, sizeof(t2)) && clobber(store)) { break } v.reset(OpMove) v.AuxInt = n v.Aux = t1 v.AddArg(dst1) v.AddArg(src1) v.AddArg(mem) return true } // match: (Move {t} [n] dst1 src1 move:(Move {t} [n] dst2 _ mem)) // cond: move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move) // result: (Move {t} [n] dst1 src1 mem) for { n := v.AuxInt t := v.Aux _ = v.Args[2] dst1 := v.Args[0] src1 := v.Args[1] move := v.Args[2] if move.Op != OpMove { break } if move.AuxInt != n { break } if move.Aux != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move)) { break } v.reset(OpMove) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(src1) v.AddArg(mem) return true } // match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem))) // cond: move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move) && clobber(vardef) // result: (Move {t} [n] dst1 src1 (VarDef {x} mem)) for { n := v.AuxInt t := v.Aux _ = v.Args[2] dst1 := v.Args[0] src1 := v.Args[1] vardef := v.Args[2] if vardef.Op != OpVarDef { break } x := vardef.Aux move := vardef.Args[0] if move.Op != OpMove { break } if move.AuxInt != n { break } if move.Aux != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move) && clobber(vardef)) { break } v.reset(OpMove) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(src1) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = x v0.AddArg(mem) v.AddArg(v0) return true } // match: (Move {t} [n] dst1 src1 zero:(Zero {t} [n] dst2 mem)) // cond: zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero) // result: (Move {t} [n] dst1 src1 mem) for { n := v.AuxInt t := v.Aux _ = v.Args[2] dst1 := v.Args[0] src1 := v.Args[1] zero := v.Args[2] if zero.Op != OpZero { break } if zero.AuxInt != n { break } if zero.Aux != t { break } mem := zero.Args[1] dst2 := zero.Args[0] if !(zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero)) { break } v.reset(OpMove) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(src1) v.AddArg(mem) return true } // match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} zero:(Zero {t} [n] dst2 mem))) // cond: zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero) && clobber(vardef) // result: (Move {t} [n] dst1 src1 (VarDef {x} mem)) for { n := v.AuxInt t := v.Aux _ = v.Args[2] dst1 := v.Args[0] src1 := v.Args[1] vardef := v.Args[2] if vardef.Op != OpVarDef { break } x := vardef.Aux zero := vardef.Args[0] if zero.Op != OpZero { break } if zero.AuxInt != n { break } if zero.Aux != t { break } mem := zero.Args[1] dst2 := zero.Args[0] if !(zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero) && clobber(vardef)) { break } v.reset(OpMove) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(src1) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = x v0.AddArg(mem) v.AddArg(v0) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [0] p3) d2 _))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && o2 == sizeof(t3) && n == sizeof(t2) + sizeof(t3) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [0] dst) d2 mem)) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type if op3.AuxInt != 0 { break } p3 := op3.Args[0] d2 := mem_2.Args[1] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && o2 == sizeof(t3) && n == sizeof(t2)+sizeof(t3)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = 0 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [0] p4) d3 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2) + sizeof(t3) + sizeof(t4) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [0] dst) d3 mem))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := op3.AuxInt p3 := op3.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := mem_2_2.Aux _ = mem_2_2.Args[2] op4 := mem_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type if op4.AuxInt != 0 { break } p4 := op4.Args[0] d3 := mem_2_2.Args[1] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2)+sizeof(t3)+sizeof(t4)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = 0 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [o4] p4) d3 (Store {t5} op5:(OffPtr [0] p5) d4 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == sizeof(t5) && o3-o4 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2) + sizeof(t3) + sizeof(t4) + sizeof(t5) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [0] dst) d4 mem)))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := op3.AuxInt p3 := op3.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := mem_2_2.Aux _ = mem_2_2.Args[2] op4 := mem_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type o4 := op4.AuxInt p4 := op4.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpStore { break } t5 := mem_2_2_2.Aux _ = mem_2_2_2.Args[2] op5 := mem_2_2_2.Args[0] if op5.Op != OpOffPtr { break } tt5 := op5.Type if op5.AuxInt != 0 { break } p5 := op5.Args[0] d4 := mem_2_2_2.Args[1] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == sizeof(t5) && o3-o4 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2)+sizeof(t3)+sizeof(t4)+sizeof(t5)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = o4 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = t5 v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = 0 v6.AddArg(dst) v5.AddArg(v6) v5.AddArg(d4) v5.AddArg(mem) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } return false } func rewriteValuegeneric_OpMove_10(v *Value) bool { b := v.Block // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [0] p3) d2 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && o2 == sizeof(t3) && n == sizeof(t2) + sizeof(t3) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [0] dst) d2 mem)) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type if op3.AuxInt != 0 { break } p3 := op3.Args[0] d2 := mem_0_2.Args[1] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && o2 == sizeof(t3) && n == sizeof(t2)+sizeof(t3)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = 0 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [0] p4) d3 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2) + sizeof(t3) + sizeof(t4) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [0] dst) d3 mem))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := op3.AuxInt p3 := op3.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := mem_0_2_2.Aux _ = mem_0_2_2.Args[2] op4 := mem_0_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type if op4.AuxInt != 0 { break } p4 := op4.Args[0] d3 := mem_0_2_2.Args[1] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2)+sizeof(t3)+sizeof(t4)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = 0 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [o4] p4) d3 (Store {t5} op5:(OffPtr [0] p5) d4 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == sizeof(t5) && o3-o4 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2) + sizeof(t3) + sizeof(t4) + sizeof(t5) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [0] dst) d4 mem)))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := op3.AuxInt p3 := op3.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := mem_0_2_2.Aux _ = mem_0_2_2.Args[2] op4 := mem_0_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type o4 := op4.AuxInt p4 := op4.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpStore { break } t5 := mem_0_2_2_2.Aux _ = mem_0_2_2_2.Args[2] op5 := mem_0_2_2_2.Args[0] if op5.Op != OpOffPtr { break } tt5 := op5.Type if op5.AuxInt != 0 { break } p5 := op5.Args[0] d4 := mem_0_2_2_2.Args[1] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == sizeof(t5) && o3-o4 == sizeof(t4) && o2-o3 == sizeof(t3) && n == sizeof(t2)+sizeof(t3)+sizeof(t4)+sizeof(t5)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = o4 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = t5 v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = 0 v6.AddArg(dst) v5.AddArg(v6) v5.AddArg(d4) v5.AddArg(mem) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Zero {t3} [n] p3 _))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && n >= o2 + sizeof(t2) // result: (Store {t2} (OffPtr [o2] dst) d1 (Zero {t1} [n] dst mem)) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpZero { break } if mem_2.AuxInt != n { break } t3 := mem_2.Aux _ = mem_2.Args[1] p3 := mem_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && n >= o2+sizeof(t2)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = n v1.Aux = t1 v1.AddArg(dst) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Zero {t4} [n] p4 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + sizeof(t2) && n >= o3 + sizeof(t3) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Zero {t1} [n] dst mem))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := mem_0.AuxInt p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := mem_2_0.AuxInt p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpZero { break } if mem_2_2.AuxInt != n { break } t4 := mem_2_2.Aux _ = mem_2_2.Args[1] p4 := mem_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && n >= o2+sizeof(t2) && n >= o3+sizeof(t3)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v3.AuxInt = n v3.Aux = t1 v3.AddArg(dst) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Zero {t5} [n] p5 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + sizeof(t2) && n >= o3 + sizeof(t3) && n >= o4 + sizeof(t4) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Zero {t1} [n] dst mem)))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := mem_0.AuxInt p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := mem_2_0.AuxInt p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := mem_2_2.Aux _ = mem_2_2.Args[2] mem_2_2_0 := mem_2_2.Args[0] if mem_2_2_0.Op != OpOffPtr { break } tt4 := mem_2_2_0.Type o4 := mem_2_2_0.AuxInt p4 := mem_2_2_0.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpZero { break } if mem_2_2_2.AuxInt != n { break } t5 := mem_2_2_2.Aux _ = mem_2_2_2.Args[1] p5 := mem_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+sizeof(t2) && n >= o3+sizeof(t3) && n >= o4+sizeof(t4)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = o4 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v5.AuxInt = n v5.Aux = t1 v5.AddArg(dst) v5.AddArg(mem) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Store {t5} (OffPtr [o5] p5) d4 (Zero {t6} [n] p6 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && alignof(t6) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + sizeof(t2) && n >= o3 + sizeof(t3) && n >= o4 + sizeof(t4) && n >= o5 + sizeof(t5) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [o5] dst) d4 (Zero {t1} [n] dst mem))))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := mem_0.AuxInt p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := mem_2_0.AuxInt p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := mem_2_2.Aux _ = mem_2_2.Args[2] mem_2_2_0 := mem_2_2.Args[0] if mem_2_2_0.Op != OpOffPtr { break } tt4 := mem_2_2_0.Type o4 := mem_2_2_0.AuxInt p4 := mem_2_2_0.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpStore { break } t5 := mem_2_2_2.Aux _ = mem_2_2_2.Args[2] mem_2_2_2_0 := mem_2_2_2.Args[0] if mem_2_2_2_0.Op != OpOffPtr { break } tt5 := mem_2_2_2_0.Type o5 := mem_2_2_2_0.AuxInt p5 := mem_2_2_2_0.Args[0] d4 := mem_2_2_2.Args[1] mem_2_2_2_2 := mem_2_2_2.Args[2] if mem_2_2_2_2.Op != OpZero { break } if mem_2_2_2_2.AuxInt != n { break } t6 := mem_2_2_2_2.Aux _ = mem_2_2_2_2.Args[1] p6 := mem_2_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && alignof(t6) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+sizeof(t2) && n >= o3+sizeof(t3) && n >= o4+sizeof(t4) && n >= o5+sizeof(t5)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = o4 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = t5 v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = o5 v6.AddArg(dst) v5.AddArg(v6) v5.AddArg(d4) v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v7.AuxInt = n v7.Aux = t1 v7.AddArg(dst) v7.AddArg(mem) v5.AddArg(v7) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Zero {t3} [n] p3 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && n >= o2 + sizeof(t2) // result: (Store {t2} (OffPtr [o2] dst) d1 (Zero {t1} [n] dst mem)) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := op2.AuxInt p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpZero { break } if mem_0_2.AuxInt != n { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[1] p3 := mem_0_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && registerizable(b, t2) && n >= o2+sizeof(t2)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = n v1.Aux = t1 v1.AddArg(dst) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Zero {t4} [n] p4 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + sizeof(t2) && n >= o3 + sizeof(t3) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Zero {t1} [n] dst mem))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := mem_0_0.AuxInt p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := mem_0_2_0.AuxInt p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpZero { break } if mem_0_2_2.AuxInt != n { break } t4 := mem_0_2_2.Aux _ = mem_0_2_2.Args[1] p4 := mem_0_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && n >= o2+sizeof(t2) && n >= o3+sizeof(t3)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v3.AuxInt = n v3.Aux = t1 v3.AddArg(dst) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Zero {t5} [n] p5 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + sizeof(t2) && n >= o3 + sizeof(t3) && n >= o4 + sizeof(t4) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Zero {t1} [n] dst mem)))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := mem_0_0.AuxInt p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := mem_0_2_0.AuxInt p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := mem_0_2_2.Aux _ = mem_0_2_2.Args[2] mem_0_2_2_0 := mem_0_2_2.Args[0] if mem_0_2_2_0.Op != OpOffPtr { break } tt4 := mem_0_2_2_0.Type o4 := mem_0_2_2_0.AuxInt p4 := mem_0_2_2_0.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpZero { break } if mem_0_2_2_2.AuxInt != n { break } t5 := mem_0_2_2_2.Aux _ = mem_0_2_2_2.Args[1] p5 := mem_0_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+sizeof(t2) && n >= o3+sizeof(t3) && n >= o4+sizeof(t4)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = o4 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v5.AuxInt = n v5.Aux = t1 v5.AddArg(dst) v5.AddArg(mem) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } return false } func rewriteValuegeneric_OpMove_20(v *Value) bool { b := v.Block config := b.Func.Config // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Store {t5} (OffPtr [o5] p5) d4 (Zero {t6} [n] p6 _))))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && alignof(t6) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + sizeof(t2) && n >= o3 + sizeof(t3) && n >= o4 + sizeof(t4) && n >= o5 + sizeof(t5) // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [o5] dst) d4 (Zero {t1} [n] dst mem))))) for { n := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] p1 := v.Args[1] mem := v.Args[2] if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := mem_0.Aux _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := mem_0_0.AuxInt p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := mem_0_2.Aux _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := mem_0_2_0.AuxInt p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := mem_0_2_2.Aux _ = mem_0_2_2.Args[2] mem_0_2_2_0 := mem_0_2_2.Args[0] if mem_0_2_2_0.Op != OpOffPtr { break } tt4 := mem_0_2_2_0.Type o4 := mem_0_2_2_0.AuxInt p4 := mem_0_2_2_0.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpStore { break } t5 := mem_0_2_2_2.Aux _ = mem_0_2_2_2.Args[2] mem_0_2_2_2_0 := mem_0_2_2_2.Args[0] if mem_0_2_2_2_0.Op != OpOffPtr { break } tt5 := mem_0_2_2_2_0.Type o5 := mem_0_2_2_2_0.AuxInt p5 := mem_0_2_2_2_0.Args[0] d4 := mem_0_2_2_2.Args[1] mem_0_2_2_2_2 := mem_0_2_2_2.Args[2] if mem_0_2_2_2_2.Op != OpZero { break } if mem_0_2_2_2_2.AuxInt != n { break } t6 := mem_0_2_2_2_2.Aux _ = mem_0_2_2_2_2.Args[1] p6 := mem_0_2_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && alignof(t2) <= alignof(t1) && alignof(t3) <= alignof(t1) && alignof(t4) <= alignof(t1) && alignof(t5) <= alignof(t1) && alignof(t6) <= alignof(t1) && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+sizeof(t2) && n >= o3+sizeof(t3) && n >= o4+sizeof(t4) && n >= o5+sizeof(t5)) { break } v.reset(OpStore) v.Aux = t2 v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = o2 v0.AddArg(dst) v.AddArg(v0) v.AddArg(d1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = o3 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(d2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t4 v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = o4 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(d3) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = t5 v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = o5 v6.AddArg(dst) v5.AddArg(v6) v5.AddArg(d4) v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v7.AuxInt = n v7.Aux = t1 v7.AddArg(dst) v7.AddArg(mem) v5.AddArg(v7) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Move {t1} [s] dst tmp1 midmem:(Move {t2} [s] tmp2 src _)) // cond: t1.(*types.Type).Compare(t2.(*types.Type)) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config)) // result: (Move {t1} [s] dst src midmem) for { s := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] tmp1 := v.Args[1] midmem := v.Args[2] if midmem.Op != OpMove { break } if midmem.AuxInt != s { break } t2 := midmem.Aux _ = midmem.Args[2] tmp2 := midmem.Args[0] src := midmem.Args[1] if !(t1.(*types.Type).Compare(t2.(*types.Type)) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) { break } v.reset(OpMove) v.AuxInt = s v.Aux = t1 v.AddArg(dst) v.AddArg(src) v.AddArg(midmem) return true } // match: (Move {t1} [s] dst tmp1 midmem:(VarDef (Move {t2} [s] tmp2 src _))) // cond: t1.(*types.Type).Compare(t2.(*types.Type)) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config)) // result: (Move {t1} [s] dst src midmem) for { s := v.AuxInt t1 := v.Aux _ = v.Args[2] dst := v.Args[0] tmp1 := v.Args[1] midmem := v.Args[2] if midmem.Op != OpVarDef { break } midmem_0 := midmem.Args[0] if midmem_0.Op != OpMove { break } if midmem_0.AuxInt != s { break } t2 := midmem_0.Aux _ = midmem_0.Args[2] tmp2 := midmem_0.Args[0] src := midmem_0.Args[1] if !(t1.(*types.Type).Compare(t2.(*types.Type)) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) { break } v.reset(OpMove) v.AuxInt = s v.Aux = t1 v.AddArg(dst) v.AddArg(src) v.AddArg(midmem) return true } // match: (Move dst src mem) // cond: isSamePtr(dst, src) // result: mem for { mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(isSamePtr(dst, src)) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } return false } func rewriteValuegeneric_OpMul16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mul16 (Const16 [c]) (Const16 [d])) // cond: // result: (Const16 [int64(int16(c*d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c * d)) return true } // match: (Mul16 (Const16 [d]) (Const16 [c])) // cond: // result: (Const16 [int64(int16(c*d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c * d)) return true } // match: (Mul16 (Const16 [1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul16 x (Const16 [1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul16 (Const16 [-1]) x) // cond: // result: (Neg16 x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != -1 { break } v.reset(OpNeg16) v.AddArg(x) return true } // match: (Mul16 x (Const16 [-1])) // cond: // result: (Neg16 x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != -1 { break } v.reset(OpNeg16) v.AddArg(x) return true } // match: (Mul16 n (Const16 [c])) // cond: isPowerOfTwo(c) // result: (Lsh16x64 n (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh16x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul16 (Const16 [c]) n) // cond: isPowerOfTwo(c) // result: (Lsh16x64 n (Const64 [log2(c)])) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh16x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul16 n (Const16 [c])) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg16 (Lsh16x64 n (Const64 [log2(-c)]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Mul16 (Const16 [c]) n) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg16 (Lsh16x64 n (Const64 [log2(-c)]))) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMul16_10(v *Value) bool { b := v.Block // match: (Mul16 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Mul16 _ (Const16 [0])) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Mul16 (Const16 [c]) (Mul16 (Const16 [d]) x)) // cond: // result: (Mul16 (Const16 [int64(int16(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul16 (Const16 [c]) (Mul16 x (Const16 [d]))) // cond: // result: (Mul16 (Const16 [int64(int16(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul16 (Mul16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Mul16 (Const16 [int64(int16(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul16 (Mul16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Mul16 (Const16 [int64(int16(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c * d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpMul32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mul32 (Const32 [c]) (Const32 [d])) // cond: // result: (Const32 [int64(int32(c*d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c * d)) return true } // match: (Mul32 (Const32 [d]) (Const32 [c])) // cond: // result: (Const32 [int64(int32(c*d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c * d)) return true } // match: (Mul32 (Const32 [1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul32 x (Const32 [1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul32 (Const32 [-1]) x) // cond: // result: (Neg32 x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != -1 { break } v.reset(OpNeg32) v.AddArg(x) return true } // match: (Mul32 x (Const32 [-1])) // cond: // result: (Neg32 x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != -1 { break } v.reset(OpNeg32) v.AddArg(x) return true } // match: (Mul32 n (Const32 [c])) // cond: isPowerOfTwo(c) // result: (Lsh32x64 n (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh32x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul32 (Const32 [c]) n) // cond: isPowerOfTwo(c) // result: (Lsh32x64 n (Const64 [log2(c)])) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh32x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul32 n (Const32 [c])) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg32 (Lsh32x64 n (Const64 [log2(-c)]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpLsh32x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Mul32 (Const32 [c]) n) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg32 (Lsh32x64 n (Const64 [log2(-c)]))) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpLsh32x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMul32_10(v *Value) bool { b := v.Block // match: (Mul32 (Const32 [c]) (Add32 (Const32 [d]) x)) // cond: // result: (Add32 (Const32 [int64(int32(c*d))]) (Mul32 (Const32 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } if v_1.Type != t { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul32 (Const32 [c]) (Add32 x (Const32 [d]))) // cond: // result: (Add32 (Const32 [int64(int32(c*d))]) (Mul32 (Const32 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } if v_1.Type != t { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul32 (Add32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Add32 (Const32 [int64(int32(c*d))]) (Mul32 (Const32 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } t := v_0.Type x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } if v_0_0.Type != t { break } d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul32 (Add32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Add32 (Const32 [int64(int32(c*d))]) (Mul32 (Const32 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } t := v_0.Type _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } if v_0_1.Type != t { break } d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul32 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Mul32 _ (Const32 [0])) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Mul32 (Const32 [c]) (Mul32 (Const32 [d]) x)) // cond: // result: (Mul32 (Const32 [int64(int32(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul32 (Const32 [c]) (Mul32 x (Const32 [d]))) // cond: // result: (Mul32 (Const32 [int64(int32(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul32 (Mul32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Mul32 (Const32 [int64(int32(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul32 (Mul32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Mul32 (Const32 [int64(int32(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c * d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpMul32F_0(v *Value) bool { // match: (Mul32F (Const32F [c]) (Const32F [d])) // cond: // result: (Const32F [auxFrom32F(auxTo32F(c) * auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(auxTo32F(c) * auxTo32F(d)) return true } // match: (Mul32F (Const32F [d]) (Const32F [c])) // cond: // result: (Const32F [auxFrom32F(auxTo32F(c) * auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } c := v_1.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(auxTo32F(c) * auxTo32F(d)) return true } // match: (Mul32F x (Const32F [auxFrom64F(1)])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32F { break } if v_1.AuxInt != auxFrom64F(1) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul32F (Const32F [auxFrom64F(1)]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } if v_0.AuxInt != auxFrom64F(1) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul32F x (Const32F [auxFrom32F(-1)])) // cond: // result: (Neg32F x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32F { break } if v_1.AuxInt != auxFrom32F(-1) { break } v.reset(OpNeg32F) v.AddArg(x) return true } // match: (Mul32F (Const32F [auxFrom32F(-1)]) x) // cond: // result: (Neg32F x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } if v_0.AuxInt != auxFrom32F(-1) { break } v.reset(OpNeg32F) v.AddArg(x) return true } // match: (Mul32F x (Const32F [auxFrom32F(2)])) // cond: // result: (Add32F x x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32F { break } if v_1.AuxInt != auxFrom32F(2) { break } v.reset(OpAdd32F) v.AddArg(x) v.AddArg(x) return true } // match: (Mul32F (Const32F [auxFrom32F(2)]) x) // cond: // result: (Add32F x x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } if v_0.AuxInt != auxFrom32F(2) { break } v.reset(OpAdd32F) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpMul64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mul64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c*d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c * d return true } // match: (Mul64 (Const64 [d]) (Const64 [c])) // cond: // result: (Const64 [c*d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c * d return true } // match: (Mul64 (Const64 [1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul64 x (Const64 [1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul64 (Const64 [-1]) x) // cond: // result: (Neg64 x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != -1 { break } v.reset(OpNeg64) v.AddArg(x) return true } // match: (Mul64 x (Const64 [-1])) // cond: // result: (Neg64 x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1 { break } v.reset(OpNeg64) v.AddArg(x) return true } // match: (Mul64 n (Const64 [c])) // cond: isPowerOfTwo(c) // result: (Lsh64x64 n (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh64x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul64 (Const64 [c]) n) // cond: isPowerOfTwo(c) // result: (Lsh64x64 n (Const64 [log2(c)])) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh64x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul64 n (Const64 [c])) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg64 (Lsh64x64 n (Const64 [log2(-c)]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpLsh64x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Mul64 (Const64 [c]) n) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg64 (Lsh64x64 n (Const64 [log2(-c)]))) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpLsh64x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMul64_10(v *Value) bool { b := v.Block // match: (Mul64 (Const64 [c]) (Add64 (Const64 [d]) x)) // cond: // result: (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } if v_1.Type != t { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul64 (Const64 [c]) (Add64 x (Const64 [d]))) // cond: // result: (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } if v_1.Type != t { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul64 (Add64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } t := v_0.Type x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } if v_0_0.Type != t { break } d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul64 (Add64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } t := v_0.Type _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.Type != t { break } d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpMul64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = c v1.AddArg(v2) v1.AddArg(x) v.AddArg(v1) return true } // match: (Mul64 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Mul64 _ (Const64 [0])) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Mul64 (Const64 [c]) (Mul64 (Const64 [d]) x)) // cond: // result: (Mul64 (Const64 [c*d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v.AddArg(x) return true } // match: (Mul64 (Const64 [c]) (Mul64 x (Const64 [d]))) // cond: // result: (Mul64 (Const64 [c*d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v.AddArg(x) return true } // match: (Mul64 (Mul64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Mul64 (Const64 [c*d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v.AddArg(x) return true } // match: (Mul64 (Mul64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Mul64 (Const64 [c*d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c * d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpMul64F_0(v *Value) bool { // match: (Mul64F (Const64F [c]) (Const64F [d])) // cond: // result: (Const64F [auxFrom64F(auxTo64F(c) * auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(auxTo64F(c) * auxTo64F(d)) return true } // match: (Mul64F (Const64F [d]) (Const64F [c])) // cond: // result: (Const64F [auxFrom64F(auxTo64F(c) * auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } c := v_1.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(auxTo64F(c) * auxTo64F(d)) return true } // match: (Mul64F x (Const64F [auxFrom64F(1)])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64F { break } if v_1.AuxInt != auxFrom64F(1) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul64F (Const64F [auxFrom64F(1)]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } if v_0.AuxInt != auxFrom64F(1) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul64F x (Const64F [auxFrom64F(-1)])) // cond: // result: (Neg64F x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64F { break } if v_1.AuxInt != auxFrom64F(-1) { break } v.reset(OpNeg64F) v.AddArg(x) return true } // match: (Mul64F (Const64F [auxFrom64F(-1)]) x) // cond: // result: (Neg64F x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } if v_0.AuxInt != auxFrom64F(-1) { break } v.reset(OpNeg64F) v.AddArg(x) return true } // match: (Mul64F x (Const64F [auxFrom64F(2)])) // cond: // result: (Add64F x x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64F { break } if v_1.AuxInt != auxFrom64F(2) { break } v.reset(OpAdd64F) v.AddArg(x) v.AddArg(x) return true } // match: (Mul64F (Const64F [auxFrom64F(2)]) x) // cond: // result: (Add64F x x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } if v_0.AuxInt != auxFrom64F(2) { break } v.reset(OpAdd64F) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpMul8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mul8 (Const8 [c]) (Const8 [d])) // cond: // result: (Const8 [int64(int8(c*d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c * d)) return true } // match: (Mul8 (Const8 [d]) (Const8 [c])) // cond: // result: (Const8 [int64(int8(c*d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c * d)) return true } // match: (Mul8 (Const8 [1]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul8 x (Const8 [1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Mul8 (Const8 [-1]) x) // cond: // result: (Neg8 x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != -1 { break } v.reset(OpNeg8) v.AddArg(x) return true } // match: (Mul8 x (Const8 [-1])) // cond: // result: (Neg8 x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != -1 { break } v.reset(OpNeg8) v.AddArg(x) return true } // match: (Mul8 n (Const8 [c])) // cond: isPowerOfTwo(c) // result: (Lsh8x64 n (Const64 [log2(c)])) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh8x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul8 (Const8 [c]) n) // cond: isPowerOfTwo(c) // result: (Lsh8x64 n (Const64 [log2(c)])) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt if !(isPowerOfTwo(c)) { break } v.reset(OpLsh8x64) v.Type = t v.AddArg(n) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = log2(c) v.AddArg(v0) return true } // match: (Mul8 n (Const8 [c])) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg8 (Lsh8x64 n (Const64 [log2(-c)]))) for { t := v.Type _ = v.Args[1] n := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Mul8 (Const8 [c]) n) // cond: t.IsSigned() && isPowerOfTwo(-c) // result: (Neg8 (Lsh8x64 n (Const64 [log2(-c)]))) for { t := v.Type n := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt if !(t.IsSigned() && isPowerOfTwo(-c)) { break } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v0.AddArg(n) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = log2(-c) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpMul8_10(v *Value) bool { b := v.Block // match: (Mul8 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Mul8 _ (Const8 [0])) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Mul8 (Const8 [c]) (Mul8 (Const8 [d]) x)) // cond: // result: (Mul8 (Const8 [int64(int8(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul8 (Const8 [c]) (Mul8 x (Const8 [d]))) // cond: // result: (Mul8 (Const8 [int64(int8(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul8 (Mul8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Mul8 (Const8 [int64(int8(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c * d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Mul8 (Mul8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Mul8 (Const8 [int64(int8(c*d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c * d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpNeg16_0(v *Value) bool { // match: (Neg16 (Const16 [c])) // cond: // result: (Const16 [int64(-int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst16) v.AuxInt = int64(-int16(c)) return true } // match: (Neg16 (Sub16 x y)) // cond: // result: (Sub16 y x) for { v_0 := v.Args[0] if v_0.Op != OpSub16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub16) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpNeg32_0(v *Value) bool { // match: (Neg32 (Const32 [c])) // cond: // result: (Const32 [int64(-int32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(-int32(c)) return true } // match: (Neg32 (Sub32 x y)) // cond: // result: (Sub32 y x) for { v_0 := v.Args[0] if v_0.Op != OpSub32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub32) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpNeg32F_0(v *Value) bool { // match: (Neg32F (Const32F [c])) // cond: auxTo32F(c) != 0 // result: (Const32F [auxFrom32F(-auxTo32F(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt if !(auxTo32F(c) != 0) { break } v.reset(OpConst32F) v.AuxInt = auxFrom32F(-auxTo32F(c)) return true } return false } func rewriteValuegeneric_OpNeg64_0(v *Value) bool { // match: (Neg64 (Const64 [c])) // cond: // result: (Const64 [-c]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = -c return true } // match: (Neg64 (Sub64 x y)) // cond: // result: (Sub64 y x) for { v_0 := v.Args[0] if v_0.Op != OpSub64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub64) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpNeg64F_0(v *Value) bool { // match: (Neg64F (Const64F [c])) // cond: auxTo64F(c) != 0 // result: (Const64F [auxFrom64F(-auxTo64F(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt if !(auxTo64F(c) != 0) { break } v.reset(OpConst64F) v.AuxInt = auxFrom64F(-auxTo64F(c)) return true } return false } func rewriteValuegeneric_OpNeg8_0(v *Value) bool { // match: (Neg8 (Const8 [c])) // cond: // result: (Const8 [int64( -int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst8) v.AuxInt = int64(-int8(c)) return true } // match: (Neg8 (Sub8 x y)) // cond: // result: (Sub8 y x) for { v_0 := v.Args[0] if v_0.Op != OpSub8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub8) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpNeq16_0(v *Value) bool { b := v.Block // match: (Neq16 x x) // cond: // result: (ConstBool [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (Neq16 (Const16 [c]) (Add16 (Const16 [d]) x)) // cond: // result: (Neq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq16 (Const16 [c]) (Add16 x (Const16 [d]))) // cond: // result: (Neq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq16 (Add16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Neq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq16 (Add16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Neq16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq16 (Const16 [c]) (Const16 [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq16 (Const16 [d]) (Const16 [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq16 s:(Sub16 x y) (Const16 [0])) // cond: s.Uses == 1 // result: (Neq16 x y) for { _ = v.Args[1] s := v.Args[0] if s.Op != OpSub16 { break } y := s.Args[1] x := s.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } if !(s.Uses == 1) { break } v.reset(OpNeq16) v.AddArg(x) v.AddArg(y) return true } // match: (Neq16 (Const16 [0]) s:(Sub16 x y)) // cond: s.Uses == 1 // result: (Neq16 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } s := v.Args[1] if s.Op != OpSub16 { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpNeq16) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNeq32_0(v *Value) bool { b := v.Block // match: (Neq32 x x) // cond: // result: (ConstBool [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (Neq32 (Const32 [c]) (Add32 (Const32 [d]) x)) // cond: // result: (Neq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq32 (Const32 [c]) (Add32 x (Const32 [d]))) // cond: // result: (Neq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq32 (Add32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Neq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq32 (Add32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Neq32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq32 (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq32 (Const32 [d]) (Const32 [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq32 s:(Sub32 x y) (Const32 [0])) // cond: s.Uses == 1 // result: (Neq32 x y) for { _ = v.Args[1] s := v.Args[0] if s.Op != OpSub32 { break } y := s.Args[1] x := s.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } if !(s.Uses == 1) { break } v.reset(OpNeq32) v.AddArg(x) v.AddArg(y) return true } // match: (Neq32 (Const32 [0]) s:(Sub32 x y)) // cond: s.Uses == 1 // result: (Neq32 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } s := v.Args[1] if s.Op != OpSub32 { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpNeq32) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNeq32F_0(v *Value) bool { // match: (Neq32F (Const32F [c]) (Const32F [d])) // cond: // result: (ConstBool [b2i(auxTo32F(c) != auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo32F(c) != auxTo32F(d)) return true } // match: (Neq32F (Const32F [d]) (Const32F [c])) // cond: // result: (ConstBool [b2i(auxTo32F(c) != auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo32F(c) != auxTo32F(d)) return true } return false } func rewriteValuegeneric_OpNeq64_0(v *Value) bool { b := v.Block // match: (Neq64 x x) // cond: // result: (ConstBool [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (Neq64 (Const64 [c]) (Add64 (Const64 [d]) x)) // cond: // result: (Neq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Neq64 (Const64 [c]) (Add64 x (Const64 [d]))) // cond: // result: (Neq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Neq64 (Add64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Neq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Neq64 (Add64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Neq64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } // match: (Neq64 (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq64 (Const64 [d]) (Const64 [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq64 s:(Sub64 x y) (Const64 [0])) // cond: s.Uses == 1 // result: (Neq64 x y) for { _ = v.Args[1] s := v.Args[0] if s.Op != OpSub64 { break } y := s.Args[1] x := s.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } if !(s.Uses == 1) { break } v.reset(OpNeq64) v.AddArg(x) v.AddArg(y) return true } // match: (Neq64 (Const64 [0]) s:(Sub64 x y)) // cond: s.Uses == 1 // result: (Neq64 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } s := v.Args[1] if s.Op != OpSub64 { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpNeq64) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNeq64F_0(v *Value) bool { // match: (Neq64F (Const64F [c]) (Const64F [d])) // cond: // result: (ConstBool [b2i(auxTo64F(c) != auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo64F(c) != auxTo64F(d)) return true } // match: (Neq64F (Const64F [d]) (Const64F [c])) // cond: // result: (ConstBool [b2i(auxTo64F(c) != auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(auxTo64F(c) != auxTo64F(d)) return true } return false } func rewriteValuegeneric_OpNeq8_0(v *Value) bool { b := v.Block // match: (Neq8 x x) // cond: // result: (ConstBool [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (Neq8 (Const8 [c]) (Add8 (Const8 [d]) x)) // cond: // result: (Neq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq8 (Const8 [c]) (Add8 x (Const8 [d]))) // cond: // result: (Neq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq8 (Add8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Neq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq8 (Add8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Neq8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Neq8 (Const8 [c]) (Const8 [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq8 (Const8 [d]) (Const8 [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (Neq8 s:(Sub8 x y) (Const8 [0])) // cond: s.Uses == 1 // result: (Neq8 x y) for { _ = v.Args[1] s := v.Args[0] if s.Op != OpSub8 { break } y := s.Args[1] x := s.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } if !(s.Uses == 1) { break } v.reset(OpNeq8) v.AddArg(x) v.AddArg(y) return true } // match: (Neq8 (Const8 [0]) s:(Sub8 x y)) // cond: s.Uses == 1 // result: (Neq8 x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } s := v.Args[1] if s.Op != OpSub8 { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpNeq8) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNeqB_0(v *Value) bool { // match: (NeqB (ConstBool [c]) (ConstBool [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConstBool { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConstBool { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (NeqB (ConstBool [d]) (ConstBool [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConstBool { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConstBool { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (NeqB (ConstBool [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConstBool { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (NeqB x (ConstBool [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConstBool { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (NeqB (ConstBool [1]) x) // cond: // result: (Not x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConstBool { break } if v_0.AuxInt != 1 { break } v.reset(OpNot) v.AddArg(x) return true } // match: (NeqB x (ConstBool [1])) // cond: // result: (Not x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConstBool { break } if v_1.AuxInt != 1 { break } v.reset(OpNot) v.AddArg(x) return true } // match: (NeqB (Not x) (Not y)) // cond: // result: (NeqB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpNot { break } x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpNot { break } y := v_1.Args[0] v.reset(OpNeqB) v.AddArg(x) v.AddArg(y) return true } // match: (NeqB (Not y) (Not x)) // cond: // result: (NeqB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpNot { break } y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpNot { break } x := v_1.Args[0] v.reset(OpNeqB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNeqInter_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (NeqInter x y) // cond: // result: (NeqPtr (ITab x) (ITab y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpNeqPtr) v0 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuegeneric_OpNeqPtr_0(v *Value) bool { // match: (NeqPtr x x) // cond: // result: (ConstBool [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConstBool) v.AuxInt = 0 return true } // match: (NeqPtr (Addr {a} _) (Addr {b} _)) // cond: // result: (ConstBool [b2i(a != b)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAddr { break } a := v_0.Aux v_1 := v.Args[1] if v_1.Op != OpAddr { break } b := v_1.Aux v.reset(OpConstBool) v.AuxInt = b2i(a != b) return true } // match: (NeqPtr (Addr {b} _) (Addr {a} _)) // cond: // result: (ConstBool [b2i(a != b)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAddr { break } b := v_0.Aux v_1 := v.Args[1] if v_1.Op != OpAddr { break } a := v_1.Aux v.reset(OpConstBool) v.AuxInt = b2i(a != b) return true } // match: (NeqPtr (LocalAddr {a} _ _) (LocalAddr {b} _ _)) // cond: // result: (ConstBool [b2i(a != b)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLocalAddr { break } a := v_0.Aux _ = v_0.Args[1] v_1 := v.Args[1] if v_1.Op != OpLocalAddr { break } b := v_1.Aux _ = v_1.Args[1] v.reset(OpConstBool) v.AuxInt = b2i(a != b) return true } // match: (NeqPtr (LocalAddr {b} _ _) (LocalAddr {a} _ _)) // cond: // result: (ConstBool [b2i(a != b)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLocalAddr { break } b := v_0.Aux _ = v_0.Args[1] v_1 := v.Args[1] if v_1.Op != OpLocalAddr { break } a := v_1.Aux _ = v_1.Args[1] v.reset(OpConstBool) v.AuxInt = b2i(a != b) return true } // match: (NeqPtr (OffPtr [o1] p1) p2) // cond: isSamePtr(p1, p2) // result: (ConstBool [b2i(o1 != 0)]) for { p2 := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o1 := v_0.AuxInt p1 := v_0.Args[0] if !(isSamePtr(p1, p2)) { break } v.reset(OpConstBool) v.AuxInt = b2i(o1 != 0) return true } // match: (NeqPtr p2 (OffPtr [o1] p1)) // cond: isSamePtr(p1, p2) // result: (ConstBool [b2i(o1 != 0)]) for { _ = v.Args[1] p2 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOffPtr { break } o1 := v_1.AuxInt p1 := v_1.Args[0] if !(isSamePtr(p1, p2)) { break } v.reset(OpConstBool) v.AuxInt = b2i(o1 != 0) return true } // match: (NeqPtr (OffPtr [o1] p1) (OffPtr [o2] p2)) // cond: isSamePtr(p1, p2) // result: (ConstBool [b2i(o1 != o2)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o1 := v_0.AuxInt p1 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpOffPtr { break } o2 := v_1.AuxInt p2 := v_1.Args[0] if !(isSamePtr(p1, p2)) { break } v.reset(OpConstBool) v.AuxInt = b2i(o1 != o2) return true } // match: (NeqPtr (OffPtr [o2] p2) (OffPtr [o1] p1)) // cond: isSamePtr(p1, p2) // result: (ConstBool [b2i(o1 != o2)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o2 := v_0.AuxInt p2 := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpOffPtr { break } o1 := v_1.AuxInt p1 := v_1.Args[0] if !(isSamePtr(p1, p2)) { break } v.reset(OpConstBool) v.AuxInt = b2i(o1 != o2) return true } // match: (NeqPtr (Const32 [c]) (Const32 [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } return false } func rewriteValuegeneric_OpNeqPtr_10(v *Value) bool { // match: (NeqPtr (Const32 [d]) (Const32 [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (NeqPtr (Const64 [c]) (Const64 [d])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (NeqPtr (Const64 [d]) (Const64 [c])) // cond: // result: (ConstBool [b2i(c != d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConstBool) v.AuxInt = b2i(c != d) return true } // match: (NeqPtr (LocalAddr _ _) (Addr _)) // cond: // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLocalAddr { break } _ = v_0.Args[1] v_1 := v.Args[1] if v_1.Op != OpAddr { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (NeqPtr (Addr _) (LocalAddr _ _)) // cond: // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAddr { break } v_1 := v.Args[1] if v_1.Op != OpLocalAddr { break } _ = v_1.Args[1] v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (NeqPtr (Addr _) (LocalAddr _ _)) // cond: // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAddr { break } v_1 := v.Args[1] if v_1.Op != OpLocalAddr { break } _ = v_1.Args[1] v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (NeqPtr (LocalAddr _ _) (Addr _)) // cond: // result: (ConstBool [1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLocalAddr { break } _ = v_0.Args[1] v_1 := v.Args[1] if v_1.Op != OpAddr { break } v.reset(OpConstBool) v.AuxInt = 1 return true } // match: (NeqPtr (AddPtr p1 o1) p2) // cond: isSamePtr(p1, p2) // result: (IsNonNil o1) for { p2 := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAddPtr { break } o1 := v_0.Args[1] p1 := v_0.Args[0] if !(isSamePtr(p1, p2)) { break } v.reset(OpIsNonNil) v.AddArg(o1) return true } // match: (NeqPtr p2 (AddPtr p1 o1)) // cond: isSamePtr(p1, p2) // result: (IsNonNil o1) for { _ = v.Args[1] p2 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddPtr { break } o1 := v_1.Args[1] p1 := v_1.Args[0] if !(isSamePtr(p1, p2)) { break } v.reset(OpIsNonNil) v.AddArg(o1) return true } // match: (NeqPtr (Const32 [0]) p) // cond: // result: (IsNonNil p) for { p := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpIsNonNil) v.AddArg(p) return true } return false } func rewriteValuegeneric_OpNeqPtr_20(v *Value) bool { // match: (NeqPtr p (Const32 [0])) // cond: // result: (IsNonNil p) for { _ = v.Args[1] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } v.reset(OpIsNonNil) v.AddArg(p) return true } // match: (NeqPtr (Const64 [0]) p) // cond: // result: (IsNonNil p) for { p := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpIsNonNil) v.AddArg(p) return true } // match: (NeqPtr p (Const64 [0])) // cond: // result: (IsNonNil p) for { _ = v.Args[1] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpIsNonNil) v.AddArg(p) return true } // match: (NeqPtr (ConstNil) p) // cond: // result: (IsNonNil p) for { p := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConstNil { break } v.reset(OpIsNonNil) v.AddArg(p) return true } // match: (NeqPtr p (ConstNil)) // cond: // result: (IsNonNil p) for { _ = v.Args[1] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConstNil { break } v.reset(OpIsNonNil) v.AddArg(p) return true } return false } func rewriteValuegeneric_OpNeqSlice_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (NeqSlice x y) // cond: // result: (NeqPtr (SlicePtr x) (SlicePtr y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpNeqPtr) v0 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuegeneric_OpNilCheck_0(v *Value) bool { b := v.Block config := b.Func.Config fe := b.Func.fe // match: (NilCheck (GetG mem) mem) // cond: // result: mem for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpGetG { break } if mem != v_0.Args[0] { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (NilCheck (Load (OffPtr [c] (SP)) (StaticCall {sym} _)) _) // cond: isSameSym(sym, "runtime.newobject") && c == config.ctxt.FixedFrameSize() + config.RegSize && warnRule(fe.Debug_checknil(), v, "removed nil check") // result: (Invalid) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLoad { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpOffPtr { break } c := v_0_0.AuxInt v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpSP { break } v_0_1 := v_0.Args[1] if v_0_1.Op != OpStaticCall { break } sym := v_0_1.Aux if !(isSameSym(sym, "runtime.newobject") && c == config.ctxt.FixedFrameSize()+config.RegSize && warnRule(fe.Debug_checknil(), v, "removed nil check")) { break } v.reset(OpInvalid) return true } // match: (NilCheck (OffPtr (Load (OffPtr [c] (SP)) (StaticCall {sym} _))) _) // cond: isSameSym(sym, "runtime.newobject") && c == config.ctxt.FixedFrameSize() + config.RegSize && warnRule(fe.Debug_checknil(), v, "removed nil check") // result: (Invalid) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLoad { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpOffPtr { break } c := v_0_0_0.AuxInt v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpSP { break } v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpStaticCall { break } sym := v_0_0_1.Aux if !(isSameSym(sym, "runtime.newobject") && c == config.ctxt.FixedFrameSize()+config.RegSize && warnRule(fe.Debug_checknil(), v, "removed nil check")) { break } v.reset(OpInvalid) return true } return false } func rewriteValuegeneric_OpNot_0(v *Value) bool { // match: (Not (ConstBool [c])) // cond: // result: (ConstBool [1-c]) for { v_0 := v.Args[0] if v_0.Op != OpConstBool { break } c := v_0.AuxInt v.reset(OpConstBool) v.AuxInt = 1 - c return true } // match: (Not (Eq64 x y)) // cond: // result: (Neq64 x y) for { v_0 := v.Args[0] if v_0.Op != OpEq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq64) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Eq32 x y)) // cond: // result: (Neq32 x y) for { v_0 := v.Args[0] if v_0.Op != OpEq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq32) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Eq16 x y)) // cond: // result: (Neq16 x y) for { v_0 := v.Args[0] if v_0.Op != OpEq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq16) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Eq8 x y)) // cond: // result: (Neq8 x y) for { v_0 := v.Args[0] if v_0.Op != OpEq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq8) v.AddArg(x) v.AddArg(y) return true } // match: (Not (EqB x y)) // cond: // result: (NeqB x y) for { v_0 := v.Args[0] if v_0.Op != OpEqB { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeqB) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Neq64 x y)) // cond: // result: (Eq64 x y) for { v_0 := v.Args[0] if v_0.Op != OpNeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq64) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Neq32 x y)) // cond: // result: (Eq32 x y) for { v_0 := v.Args[0] if v_0.Op != OpNeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq32) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Neq16 x y)) // cond: // result: (Eq16 x y) for { v_0 := v.Args[0] if v_0.Op != OpNeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq16) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Neq8 x y)) // cond: // result: (Eq8 x y) for { v_0 := v.Args[0] if v_0.Op != OpNeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq8) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNot_10(v *Value) bool { // match: (Not (NeqB x y)) // cond: // result: (EqB x y) for { v_0 := v.Args[0] if v_0.Op != OpNeqB { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEqB) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater64 x y)) // cond: // result: (Leq64 x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq64) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater32 x y)) // cond: // result: (Leq32 x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq32) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater16 x y)) // cond: // result: (Leq16 x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq16) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater8 x y)) // cond: // result: (Leq8 x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq8) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater64U x y)) // cond: // result: (Leq64U x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq64U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater32U x y)) // cond: // result: (Leq32U x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq32U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater16U x y)) // cond: // result: (Leq16U x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq16U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Greater8U x y)) // cond: // result: (Leq8U x y) for { v_0 := v.Args[0] if v_0.Op != OpGreater8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq8U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq64 x y)) // cond: // result: (Less64 x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess64) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNot_20(v *Value) bool { // match: (Not (Geq32 x y)) // cond: // result: (Less32 x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess32) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq16 x y)) // cond: // result: (Less16 x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess16) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq8 x y)) // cond: // result: (Less8 x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess8) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq64U x y)) // cond: // result: (Less64U x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess64U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq32U x y)) // cond: // result: (Less32U x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess32U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq16U x y)) // cond: // result: (Less16U x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess16U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Geq8U x y)) // cond: // result: (Less8U x y) for { v_0 := v.Args[0] if v_0.Op != OpGeq8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess8U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less64 x y)) // cond: // result: (Geq64 x y) for { v_0 := v.Args[0] if v_0.Op != OpLess64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq64) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less32 x y)) // cond: // result: (Geq32 x y) for { v_0 := v.Args[0] if v_0.Op != OpLess32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq32) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less16 x y)) // cond: // result: (Geq16 x y) for { v_0 := v.Args[0] if v_0.Op != OpLess16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq16) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNot_30(v *Value) bool { // match: (Not (Less8 x y)) // cond: // result: (Geq8 x y) for { v_0 := v.Args[0] if v_0.Op != OpLess8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq8) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less64U x y)) // cond: // result: (Geq64U x y) for { v_0 := v.Args[0] if v_0.Op != OpLess64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq64U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less32U x y)) // cond: // result: (Geq32U x y) for { v_0 := v.Args[0] if v_0.Op != OpLess32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq32U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less16U x y)) // cond: // result: (Geq16U x y) for { v_0 := v.Args[0] if v_0.Op != OpLess16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq16U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Less8U x y)) // cond: // result: (Geq8U x y) for { v_0 := v.Args[0] if v_0.Op != OpLess8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGeq8U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq64 x y)) // cond: // result: (Greater64 x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater64) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq32 x y)) // cond: // result: (Greater32 x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater32) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq16 x y)) // cond: // result: (Greater16 x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater16) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq8 x y)) // cond: // result: (Greater8 x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater8) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq64U x y)) // cond: // result: (Greater64U x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater64U) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpNot_40(v *Value) bool { // match: (Not (Leq32U x y)) // cond: // result: (Greater32U x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater32U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq16U x y)) // cond: // result: (Greater16U x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater16U) v.AddArg(x) v.AddArg(y) return true } // match: (Not (Leq8U x y)) // cond: // result: (Greater8U x y) for { v_0 := v.Args[0] if v_0.Op != OpLeq8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpGreater8U) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpOffPtr_0(v *Value) bool { // match: (OffPtr (OffPtr p [b]) [a]) // cond: // result: (OffPtr p [a+b]) for { a := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } b := v_0.AuxInt p := v_0.Args[0] v.reset(OpOffPtr) v.AuxInt = a + b v.AddArg(p) return true } // match: (OffPtr p [0]) // cond: v.Type.Compare(p.Type) == types.CMPeq // result: p for { if v.AuxInt != 0 { break } p := v.Args[0] if !(v.Type.Compare(p.Type) == types.CMPeq) { break } v.reset(OpCopy) v.Type = p.Type v.AddArg(p) return true } return false } func rewriteValuegeneric_OpOr16_0(v *Value) bool { // match: (Or16 (Const16 [c]) (Const16 [d])) // cond: // result: (Const16 [int64(int16(c|d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c | d)) return true } // match: (Or16 (Const16 [d]) (Const16 [c])) // cond: // result: (Const16 [int64(int16(c|d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c | d)) return true } // match: (Or16 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or16 (Const16 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or16 x (Const16 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or16 (Const16 [-1]) _) // cond: // result: (Const16 [-1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != -1 { break } v.reset(OpConst16) v.AuxInt = -1 return true } // match: (Or16 _ (Const16 [-1])) // cond: // result: (Const16 [-1]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != -1 { break } v.reset(OpConst16) v.AuxInt = -1 return true } // match: (Or16 x (Or16 x y)) // cond: // result: (Or16 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr16 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpOr16) v.AddArg(x) v.AddArg(y) return true } // match: (Or16 x (Or16 y x)) // cond: // result: (Or16 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr16 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpOr16) v.AddArg(x) v.AddArg(y) return true } // match: (Or16 (Or16 x y) x) // cond: // result: (Or16 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr16 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpOr16) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpOr16_10(v *Value) bool { b := v.Block // match: (Or16 (Or16 y x) x) // cond: // result: (Or16 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr16 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpOr16) v.AddArg(x) v.AddArg(y) return true } // match: (Or16 (And16 x (Const16 [c2])) (Const16 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or16 (Const16 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or16 (And16 (Const16 [c2]) x) (Const16 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or16 (Const16 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } c2 := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or16 (Const16 [c1]) (And16 x (Const16 [c2]))) // cond: ^(c1 | c2) == 0 // result: (Or16 (Const16 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } c2 := v_1_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or16 (Const16 [c1]) (And16 (Const16 [c2]) x)) // cond: ^(c1 | c2) == 0 // result: (Or16 (Const16 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c2 := v_1_0.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or16 (Or16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Or16 i (Or16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpOr16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or16 (Or16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Or16 i (Or16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr16 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpOr16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or16 x (Or16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Or16 i (Or16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpOr16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or16 x (Or16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Or16 i (Or16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpOr16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or16 (Const16 [c]) (Or16 (Const16 [d]) x)) // cond: // result: (Or16 (Const16 [int64(int16(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c | d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr16_20(v *Value) bool { b := v.Block // match: (Or16 (Const16 [c]) (Or16 x (Const16 [d]))) // cond: // result: (Or16 (Const16 [int64(int16(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c | d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Or16 (Or16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Or16 (Const16 [int64(int16(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c | d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Or16 (Or16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Or16 (Const16 [int64(int16(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c | d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr32_0(v *Value) bool { // match: (Or32 (Const32 [c]) (Const32 [d])) // cond: // result: (Const32 [int64(int32(c|d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c | d)) return true } // match: (Or32 (Const32 [d]) (Const32 [c])) // cond: // result: (Const32 [int64(int32(c|d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c | d)) return true } // match: (Or32 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or32 (Const32 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or32 x (Const32 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or32 (Const32 [-1]) _) // cond: // result: (Const32 [-1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != -1 { break } v.reset(OpConst32) v.AuxInt = -1 return true } // match: (Or32 _ (Const32 [-1])) // cond: // result: (Const32 [-1]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != -1 { break } v.reset(OpConst32) v.AuxInt = -1 return true } // match: (Or32 x (Or32 x y)) // cond: // result: (Or32 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr32 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpOr32) v.AddArg(x) v.AddArg(y) return true } // match: (Or32 x (Or32 y x)) // cond: // result: (Or32 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr32 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpOr32) v.AddArg(x) v.AddArg(y) return true } // match: (Or32 (Or32 x y) x) // cond: // result: (Or32 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr32 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpOr32) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpOr32_10(v *Value) bool { b := v.Block // match: (Or32 (Or32 y x) x) // cond: // result: (Or32 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr32 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpOr32) v.AddArg(x) v.AddArg(y) return true } // match: (Or32 (And32 x (Const32 [c2])) (Const32 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or32 (Const32 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or32 (And32 (Const32 [c2]) x) (Const32 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or32 (Const32 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } c2 := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or32 (Const32 [c1]) (And32 x (Const32 [c2]))) // cond: ^(c1 | c2) == 0 // result: (Or32 (Const32 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } c2 := v_1_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or32 (Const32 [c1]) (And32 (Const32 [c2]) x)) // cond: ^(c1 | c2) == 0 // result: (Or32 (Const32 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c2 := v_1_0.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or32 (Or32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Or32 i (Or32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpOr32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or32 (Or32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Or32 i (Or32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr32 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpOr32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or32 x (Or32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Or32 i (Or32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpOr32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or32 x (Or32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Or32 i (Or32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpOr32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or32 (Const32 [c]) (Or32 (Const32 [d]) x)) // cond: // result: (Or32 (Const32 [int64(int32(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c | d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr32_20(v *Value) bool { b := v.Block // match: (Or32 (Const32 [c]) (Or32 x (Const32 [d]))) // cond: // result: (Or32 (Const32 [int64(int32(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c | d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Or32 (Or32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Or32 (Const32 [int64(int32(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c | d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Or32 (Or32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Or32 (Const32 [int64(int32(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c | d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr64_0(v *Value) bool { // match: (Or64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c|d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c | d return true } // match: (Or64 (Const64 [d]) (Const64 [c])) // cond: // result: (Const64 [c|d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c | d return true } // match: (Or64 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or64 (Const64 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or64 (Const64 [-1]) _) // cond: // result: (Const64 [-1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != -1 { break } v.reset(OpConst64) v.AuxInt = -1 return true } // match: (Or64 _ (Const64 [-1])) // cond: // result: (Const64 [-1]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != -1 { break } v.reset(OpConst64) v.AuxInt = -1 return true } // match: (Or64 x (Or64 x y)) // cond: // result: (Or64 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr64 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpOr64) v.AddArg(x) v.AddArg(y) return true } // match: (Or64 x (Or64 y x)) // cond: // result: (Or64 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr64 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpOr64) v.AddArg(x) v.AddArg(y) return true } // match: (Or64 (Or64 x y) x) // cond: // result: (Or64 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr64 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpOr64) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpOr64_10(v *Value) bool { b := v.Block // match: (Or64 (Or64 y x) x) // cond: // result: (Or64 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr64 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpOr64) v.AddArg(x) v.AddArg(y) return true } // match: (Or64 (And64 x (Const64 [c2])) (Const64 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or64 (Const64 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or64 (And64 (Const64 [c2]) x) (Const64 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or64 (Const64 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } c2 := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or64 (Const64 [c1]) (And64 x (Const64 [c2]))) // cond: ^(c1 | c2) == 0 // result: (Or64 (Const64 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c2 := v_1_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or64 (Const64 [c1]) (And64 (Const64 [c2]) x)) // cond: ^(c1 | c2) == 0 // result: (Or64 (Const64 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c2 := v_1_0.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or64 (Or64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Or64 i (Or64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpOr64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or64 (Or64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Or64 i (Or64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr64 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpOr64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or64 x (Or64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Or64 i (Or64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpOr64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or64 x (Or64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Or64 i (Or64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpOr64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or64 (Const64 [c]) (Or64 (Const64 [d]) x)) // cond: // result: (Or64 (Const64 [c|d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c | d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr64_20(v *Value) bool { b := v.Block // match: (Or64 (Const64 [c]) (Or64 x (Const64 [d]))) // cond: // result: (Or64 (Const64 [c|d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c | d v.AddArg(v0) v.AddArg(x) return true } // match: (Or64 (Or64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Or64 (Const64 [c|d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c | d v.AddArg(v0) v.AddArg(x) return true } // match: (Or64 (Or64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Or64 (Const64 [c|d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c | d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr8_0(v *Value) bool { // match: (Or8 (Const8 [c]) (Const8 [d])) // cond: // result: (Const8 [int64(int8(c|d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c | d)) return true } // match: (Or8 (Const8 [d]) (Const8 [c])) // cond: // result: (Const8 [int64(int8(c|d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c | d)) return true } // match: (Or8 x x) // cond: // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or8 (Const8 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or8 x (Const8 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Or8 (Const8 [-1]) _) // cond: // result: (Const8 [-1]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != -1 { break } v.reset(OpConst8) v.AuxInt = -1 return true } // match: (Or8 _ (Const8 [-1])) // cond: // result: (Const8 [-1]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != -1 { break } v.reset(OpConst8) v.AuxInt = -1 return true } // match: (Or8 x (Or8 x y)) // cond: // result: (Or8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr8 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpOr8) v.AddArg(x) v.AddArg(y) return true } // match: (Or8 x (Or8 y x)) // cond: // result: (Or8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr8 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpOr8) v.AddArg(x) v.AddArg(y) return true } // match: (Or8 (Or8 x y) x) // cond: // result: (Or8 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr8 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpOr8) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpOr8_10(v *Value) bool { b := v.Block // match: (Or8 (Or8 y x) x) // cond: // result: (Or8 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr8 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpOr8) v.AddArg(x) v.AddArg(y) return true } // match: (Or8 (And8 x (Const8 [c2])) (Const8 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or8 (Const8 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or8 (And8 (Const8 [c2]) x) (Const8 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or8 (Const8 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAnd8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } c2 := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } t := v_1.Type c1 := v_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or8 (Const8 [c1]) (And8 x (Const8 [c2]))) // cond: ^(c1 | c2) == 0 // result: (Or8 (Const8 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } c2 := v_1_1.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or8 (Const8 [c1]) (And8 (Const8 [c2]) x)) // cond: ^(c1 | c2) == 0 // result: (Or8 (Const8 [c1]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c1 := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpAnd8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c2 := v_1_0.AuxInt if !(^(c1 | c2) == 0) { break } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = c1 v.AddArg(v0) v.AddArg(x) return true } // match: (Or8 (Or8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Or8 i (Or8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpOr8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or8 (Or8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Or8 i (Or8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr8 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpOr8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or8 x (Or8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Or8 i (Or8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpOr8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or8 x (Or8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Or8 i (Or8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpOr8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpOr8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpOr8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Or8 (Const8 [c]) (Or8 (Const8 [d]) x)) // cond: // result: (Or8 (Const8 [int64(int8(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c | d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpOr8_20(v *Value) bool { b := v.Block // match: (Or8 (Const8 [c]) (Or8 x (Const8 [d]))) // cond: // result: (Or8 (Const8 [int64(int8(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpOr8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c | d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Or8 (Or8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Or8 (Const8 [int64(int8(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c | d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Or8 (Or8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Or8 (Const8 [int64(int8(c|d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpOr8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c | d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpPhi_0(v *Value) bool { // match: (Phi (Const8 [c]) (Const8 [c])) // cond: // result: (Const8 [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != c { break } if len(v.Args) != 2 { break } v.reset(OpConst8) v.AuxInt = c return true } // match: (Phi (Const16 [c]) (Const16 [c])) // cond: // result: (Const16 [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != c { break } if len(v.Args) != 2 { break } v.reset(OpConst16) v.AuxInt = c return true } // match: (Phi (Const32 [c]) (Const32 [c])) // cond: // result: (Const32 [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != c { break } if len(v.Args) != 2 { break } v.reset(OpConst32) v.AuxInt = c return true } // match: (Phi (Const64 [c]) (Const64 [c])) // cond: // result: (Const64 [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != c { break } if len(v.Args) != 2 { break } v.reset(OpConst64) v.AuxInt = c return true } return false } func rewriteValuegeneric_OpPtrIndex_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (PtrIndex ptr idx) // cond: config.PtrSize == 4 // result: (AddPtr ptr (Mul32 idx (Const32 [t.Elem().Size()]))) for { t := v.Type idx := v.Args[1] ptr := v.Args[0] if !(config.PtrSize == 4) { break } v.reset(OpAddPtr) v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpMul32, typ.Int) v0.AddArg(idx) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = t.Elem().Size() v0.AddArg(v1) v.AddArg(v0) return true } // match: (PtrIndex ptr idx) // cond: config.PtrSize == 8 // result: (AddPtr ptr (Mul64 idx (Const64 [t.Elem().Size()]))) for { t := v.Type idx := v.Args[1] ptr := v.Args[0] if !(config.PtrSize == 8) { break } v.reset(OpAddPtr) v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpMul64, typ.Int) v0.AddArg(idx) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = t.Elem().Size() v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRotateLeft16_0(v *Value) bool { // match: (RotateLeft16 x (Const16 [c])) // cond: c%16 == 0 // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt if !(c%16 == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpRotateLeft32_0(v *Value) bool { // match: (RotateLeft32 x (Const32 [c])) // cond: c%32 == 0 // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt if !(c%32 == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpRotateLeft64_0(v *Value) bool { // match: (RotateLeft64 x (Const64 [c])) // cond: c%64 == 0 // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(c%64 == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpRotateLeft8_0(v *Value) bool { // match: (RotateLeft8 x (Const8 [c])) // cond: c%8 == 0 // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt if !(c%8 == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpRound32F_0(v *Value) bool { // match: (Round32F x:(Const32F)) // cond: // result: x for { x := v.Args[0] if x.Op != OpConst32F { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpRound64F_0(v *Value) bool { // match: (Round64F x:(Const64F)) // cond: // result: x for { x := v.Args[0] if x.Op != OpConst64F { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpRsh16Ux16_0(v *Value) bool { b := v.Block // match: (Rsh16Ux16 x (Const16 [c])) // cond: // result: (Rsh16Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh16Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh16Ux16 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh16Ux32_0(v *Value) bool { b := v.Block // match: (Rsh16Ux32 x (Const32 [c])) // cond: // result: (Rsh16Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh16Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh16Ux32 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh16Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux64 (Const16 [c]) (Const64 [d])) // cond: // result: (Const16 [int64(int16(uint16(c) >> uint64(d)))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(uint16(c) >> uint64(d))) return true } // match: (Rsh16Ux64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh16Ux64 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Rsh16Ux64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Rsh16Ux64 (Rsh16Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh16Ux64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh16Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh16Ux64 (Rsh16x64 x _) (Const64 [15])) // cond: // result: (Rsh16Ux64 x (Const64 [15])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type if v_1.AuxInt != 15 { break } v.reset(OpRsh16Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = 15 v.AddArg(v0) return true } // match: (Rsh16Ux64 (Lsh16x64 (Rsh16Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh16Ux64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh16Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh16Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } // match: (Rsh16Ux64 (Lsh16x64 x (Const64 [8])) (Const64 [8])) // cond: // result: (ZeroExt8to16 (Trunc16to8 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 8 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 8 { break } v.reset(OpZeroExt8to16) v0 := b.NewValue0(v.Pos, OpTrunc16to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh16Ux8_0(v *Value) bool { b := v.Block // match: (Rsh16Ux8 x (Const8 [c])) // cond: // result: (Rsh16Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh16Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh16Ux8 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh16x16_0(v *Value) bool { b := v.Block // match: (Rsh16x16 x (Const16 [c])) // cond: // result: (Rsh16x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh16x16 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh16x32_0(v *Value) bool { b := v.Block // match: (Rsh16x32 x (Const32 [c])) // cond: // result: (Rsh16x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh16x32 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh16x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x64 (Const16 [c]) (Const64 [d])) // cond: // result: (Const16 [int64(int16(c) >> uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c) >> uint64(d)) return true } // match: (Rsh16x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh16x64 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Rsh16x64 (Rsh16x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh16x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh16x64 (Lsh16x64 x (Const64 [8])) (Const64 [8])) // cond: // result: (SignExt8to16 (Trunc16to8 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 8 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 8 { break } v.reset(OpSignExt8to16) v0 := b.NewValue0(v.Pos, OpTrunc16to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh16x8_0(v *Value) bool { b := v.Block // match: (Rsh16x8 x (Const8 [c])) // cond: // result: (Rsh16x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh16x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh16x8 (Const16 [0]) _) // cond: // result: (Const16 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst16) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh32Ux16_0(v *Value) bool { b := v.Block // match: (Rsh32Ux16 x (Const16 [c])) // cond: // result: (Rsh32Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh32Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh32Ux16 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh32Ux32_0(v *Value) bool { b := v.Block // match: (Rsh32Ux32 x (Const32 [c])) // cond: // result: (Rsh32Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh32Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh32Ux32 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh32Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux64 (Const32 [c]) (Const64 [d])) // cond: // result: (Const32 [int64(int32(uint32(c) >> uint64(d)))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(uint32(c) >> uint64(d))) return true } // match: (Rsh32Ux64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh32Ux64 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Rsh32Ux64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Rsh32Ux64 (Rsh32Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh32Ux64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh32Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh32Ux64 (Rsh32x64 x _) (Const64 [31])) // cond: // result: (Rsh32Ux64 x (Const64 [31])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type if v_1.AuxInt != 31 { break } v.reset(OpRsh32Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = 31 v.AddArg(v0) return true } // match: (Rsh32Ux64 (Lsh32x64 (Rsh32Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh32Ux64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh32Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } // match: (Rsh32Ux64 (Lsh32x64 x (Const64 [24])) (Const64 [24])) // cond: // result: (ZeroExt8to32 (Trunc32to8 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 24 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 24 { break } v.reset(OpZeroExt8to32) v0 := b.NewValue0(v.Pos, OpTrunc32to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh32Ux64 (Lsh32x64 x (Const64 [16])) (Const64 [16])) // cond: // result: (ZeroExt16to32 (Trunc32to16 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 16 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 16 { break } v.reset(OpZeroExt16to32) v0 := b.NewValue0(v.Pos, OpTrunc32to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh32Ux8_0(v *Value) bool { b := v.Block // match: (Rsh32Ux8 x (Const8 [c])) // cond: // result: (Rsh32Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh32Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh32Ux8 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh32x16_0(v *Value) bool { b := v.Block // match: (Rsh32x16 x (Const16 [c])) // cond: // result: (Rsh32x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh32x16 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh32x32_0(v *Value) bool { b := v.Block // match: (Rsh32x32 x (Const32 [c])) // cond: // result: (Rsh32x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh32x32 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh32x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x64 (Const32 [c]) (Const64 [d])) // cond: // result: (Const32 [int64(int32(c) >> uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c) >> uint64(d)) return true } // match: (Rsh32x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh32x64 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Rsh32x64 (Rsh32x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh32x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh32x64 (Lsh32x64 x (Const64 [24])) (Const64 [24])) // cond: // result: (SignExt8to32 (Trunc32to8 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 24 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 24 { break } v.reset(OpSignExt8to32) v0 := b.NewValue0(v.Pos, OpTrunc32to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh32x64 (Lsh32x64 x (Const64 [16])) (Const64 [16])) // cond: // result: (SignExt16to32 (Trunc32to16 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 16 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 16 { break } v.reset(OpSignExt16to32) v0 := b.NewValue0(v.Pos, OpTrunc32to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh32x8_0(v *Value) bool { b := v.Block // match: (Rsh32x8 x (Const8 [c])) // cond: // result: (Rsh32x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh32x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh32x8 (Const32 [0]) _) // cond: // result: (Const32 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh64Ux16_0(v *Value) bool { b := v.Block // match: (Rsh64Ux16 x (Const16 [c])) // cond: // result: (Rsh64Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh64Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh64Ux16 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh64Ux32_0(v *Value) bool { b := v.Block // match: (Rsh64Ux32 x (Const32 [c])) // cond: // result: (Rsh64Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh64Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh64Ux32 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh64Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [int64(uint64(c) >> uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = int64(uint64(c) >> uint64(d)) return true } // match: (Rsh64Ux64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh64Ux64 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Rsh64Ux64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (Const64 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Rsh64Ux64 (Rsh64Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh64Ux64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh64Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh64Ux64 (Rsh64x64 x _) (Const64 [63])) // cond: // result: (Rsh64Ux64 x (Const64 [63])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type if v_1.AuxInt != 63 { break } v.reset(OpRsh64Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = 63 v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 (Rsh64Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh64Ux64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh64Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [56])) (Const64 [56])) // cond: // result: (ZeroExt8to64 (Trunc64to8 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 56 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 56 { break } v.reset(OpZeroExt8to64) v0 := b.NewValue0(v.Pos, OpTrunc64to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [48])) (Const64 [48])) // cond: // result: (ZeroExt16to64 (Trunc64to16 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 48 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 48 { break } v.reset(OpZeroExt16to64) v0 := b.NewValue0(v.Pos, OpTrunc64to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [32])) (Const64 [32])) // cond: // result: (ZeroExt32to64 (Trunc64to32 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 32 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 32 { break } v.reset(OpZeroExt32to64) v0 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh64Ux8_0(v *Value) bool { b := v.Block // match: (Rsh64Ux8 x (Const8 [c])) // cond: // result: (Rsh64Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh64Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh64Ux8 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh64x16_0(v *Value) bool { b := v.Block // match: (Rsh64x16 x (Const16 [c])) // cond: // result: (Rsh64x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh64x16 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh64x32_0(v *Value) bool { b := v.Block // match: (Rsh64x32 x (Const32 [c])) // cond: // result: (Rsh64x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh64x32 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh64x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c >> uint64(d)]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c >> uint64(d) return true } // match: (Rsh64x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh64x64 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Rsh64x64 (Rsh64x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh64x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [56])) (Const64 [56])) // cond: // result: (SignExt8to64 (Trunc64to8 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 56 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 56 { break } v.reset(OpSignExt8to64) v0 := b.NewValue0(v.Pos, OpTrunc64to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [48])) (Const64 [48])) // cond: // result: (SignExt16to64 (Trunc64to16 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 48 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 48 { break } v.reset(OpSignExt16to64) v0 := b.NewValue0(v.Pos, OpTrunc64to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [32])) (Const64 [32])) // cond: // result: (SignExt32to64 (Trunc64to32 x)) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } if v_0_1.AuxInt != 32 { break } v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 32 { break } v.reset(OpSignExt32to64) v0 := b.NewValue0(v.Pos, OpTrunc64to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh64x8_0(v *Value) bool { b := v.Block // match: (Rsh64x8 x (Const8 [c])) // cond: // result: (Rsh64x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh64x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh64x8 (Const64 [0]) _) // cond: // result: (Const64 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh8Ux16_0(v *Value) bool { b := v.Block // match: (Rsh8Ux16 x (Const16 [c])) // cond: // result: (Rsh8Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh8Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh8Ux16 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh8Ux32_0(v *Value) bool { b := v.Block // match: (Rsh8Ux32 x (Const32 [c])) // cond: // result: (Rsh8Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh8Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh8Ux32 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh8Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux64 (Const8 [c]) (Const64 [d])) // cond: // result: (Const8 [int64(int8(uint8(c) >> uint64(d)))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(uint8(c) >> uint64(d))) return true } // match: (Rsh8Ux64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh8Ux64 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Rsh8Ux64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Rsh8Ux64 (Rsh8Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh8Ux64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh8Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } // match: (Rsh8Ux64 (Rsh8x64 x _) (Const64 [7])) // cond: // result: (Rsh8Ux64 x (Const64 [7] )) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type if v_1.AuxInt != 7 { break } v.reset(OpRsh8Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = 7 v.AddArg(v0) return true } // match: (Rsh8Ux64 (Lsh8x64 (Rsh8Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh8Ux64 x (Const64 [c1-c2+c3])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh8Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := v_0_0_1.AuxInt v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c3 := v_1.AuxInt if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh8Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = c1 - c2 + c3 v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh8Ux8_0(v *Value) bool { b := v.Block // match: (Rsh8Ux8 x (Const8 [c])) // cond: // result: (Rsh8Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh8Ux64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh8Ux8 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh8x16_0(v *Value) bool { b := v.Block // match: (Rsh8x16 x (Const16 [c])) // cond: // result: (Rsh8x64 x (Const64 [int64(uint16(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpRsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint16(c)) v.AddArg(v0) return true } // match: (Rsh8x16 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh8x32_0(v *Value) bool { b := v.Block // match: (Rsh8x32 x (Const32 [c])) // cond: // result: (Rsh8x64 x (Const64 [int64(uint32(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpRsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint32(c)) v.AddArg(v0) return true } // match: (Rsh8x32 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpRsh8x64_0(v *Value) bool { b := v.Block // match: (Rsh8x64 (Const8 [c]) (Const64 [d])) // cond: // result: (Const8 [int64(int8(c) >> uint64(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c) >> uint64(d)) return true } // match: (Rsh8x64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Rsh8x64 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Rsh8x64 (Rsh8x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh8x64 x (Const64 [c+d])) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpRsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt if !(!uaddOvf(c, d)) { break } v.reset(OpRsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh8x8_0(v *Value) bool { b := v.Block // match: (Rsh8x8 x (Const8 [c])) // cond: // result: (Rsh8x64 x (Const64 [int64(uint8(c))])) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpRsh8x64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64(uint8(c)) v.AddArg(v0) return true } // match: (Rsh8x8 (Const8 [0]) _) // cond: // result: (Const8 [0]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst8) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpSelect0_0(v *Value) bool { // match: (Select0 (Div128u (Const64 [0]) lo y)) // cond: // result: (Div64u lo y) for { v_0 := v.Args[0] if v_0.Op != OpDiv128u { break } y := v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } if v_0_0.AuxInt != 0 { break } lo := v_0.Args[1] v.reset(OpDiv64u) v.AddArg(lo) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpSelect1_0(v *Value) bool { // match: (Select1 (Div128u (Const64 [0]) lo y)) // cond: // result: (Mod64u lo y) for { v_0 := v.Args[0] if v_0.Op != OpDiv128u { break } y := v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } if v_0_0.AuxInt != 0 { break } lo := v_0.Args[1] v.reset(OpMod64u) v.AddArg(lo) v.AddArg(y) return true } return false } func rewriteValuegeneric_OpSignExt16to32_0(v *Value) bool { // match: (SignExt16to32 (Const16 [c])) // cond: // result: (Const32 [int64( int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(int16(c)) return true } // match: (SignExt16to32 (Trunc32to16 x:(Rsh32x64 _ (Const64 [s])))) // cond: s >= 16 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc32to16 { break } x := v_0.Args[0] if x.Op != OpRsh32x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 16) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSignExt16to64_0(v *Value) bool { // match: (SignExt16to64 (Const16 [c])) // cond: // result: (Const64 [int64( int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(int16(c)) return true } // match: (SignExt16to64 (Trunc64to16 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 48 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc64to16 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 48) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSignExt32to64_0(v *Value) bool { // match: (SignExt32to64 (Const32 [c])) // cond: // result: (Const64 [int64( int32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(int32(c)) return true } // match: (SignExt32to64 (Trunc64to32 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 32 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc64to32 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 32) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSignExt8to16_0(v *Value) bool { // match: (SignExt8to16 (Const8 [c])) // cond: // result: (Const16 [int64( int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst16) v.AuxInt = int64(int8(c)) return true } // match: (SignExt8to16 (Trunc16to8 x:(Rsh16x64 _ (Const64 [s])))) // cond: s >= 8 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc16to8 { break } x := v_0.Args[0] if x.Op != OpRsh16x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 8) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSignExt8to32_0(v *Value) bool { // match: (SignExt8to32 (Const8 [c])) // cond: // result: (Const32 [int64( int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(int8(c)) return true } // match: (SignExt8to32 (Trunc32to8 x:(Rsh32x64 _ (Const64 [s])))) // cond: s >= 24 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc32to8 { break } x := v_0.Args[0] if x.Op != OpRsh32x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 24) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSignExt8to64_0(v *Value) bool { // match: (SignExt8to64 (Const8 [c])) // cond: // result: (Const64 [int64( int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(int8(c)) return true } // match: (SignExt8to64 (Trunc64to8 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 56 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc64to8 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 56) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSliceCap_0(v *Value) bool { // match: (SliceCap (SliceMake _ _ (Const64 [c]))) // cond: // result: (Const64 [c]) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpConst64 { break } t := v_0_2.Type c := v_0_2.AuxInt v.reset(OpConst64) v.Type = t v.AuxInt = c return true } // match: (SliceCap (SliceMake _ _ (Const32 [c]))) // cond: // result: (Const32 [c]) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpConst32 { break } t := v_0_2.Type c := v_0_2.AuxInt v.reset(OpConst32) v.Type = t v.AuxInt = c return true } // match: (SliceCap (SliceMake _ _ (SliceCap x))) // cond: // result: (SliceCap x) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpSliceCap { break } x := v_0_2.Args[0] v.reset(OpSliceCap) v.AddArg(x) return true } // match: (SliceCap (SliceMake _ _ (SliceLen x))) // cond: // result: (SliceLen x) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpSliceLen { break } x := v_0_2.Args[0] v.reset(OpSliceLen) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSliceLen_0(v *Value) bool { // match: (SliceLen (SliceMake _ (Const64 [c]) _)) // cond: // result: (Const64 [c]) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type c := v_0_1.AuxInt v.reset(OpConst64) v.Type = t v.AuxInt = c return true } // match: (SliceLen (SliceMake _ (Const32 [c]) _)) // cond: // result: (Const32 [c]) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type c := v_0_1.AuxInt v.reset(OpConst32) v.Type = t v.AuxInt = c return true } // match: (SliceLen (SliceMake _ (SliceLen x) _)) // cond: // result: (SliceLen x) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_1 := v_0.Args[1] if v_0_1.Op != OpSliceLen { break } x := v_0_1.Args[0] v.reset(OpSliceLen) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSlicePtr_0(v *Value) bool { // match: (SlicePtr (SliceMake (SlicePtr x) _ _)) // cond: // result: (SlicePtr x) for { v_0 := v.Args[0] if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpSlicePtr { break } x := v_0_0.Args[0] v.reset(OpSlicePtr) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSlicemask_0(v *Value) bool { // match: (Slicemask (Const32 [x])) // cond: x > 0 // result: (Const32 [-1]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } x := v_0.AuxInt if !(x > 0) { break } v.reset(OpConst32) v.AuxInt = -1 return true } // match: (Slicemask (Const32 [0])) // cond: // result: (Const32 [0]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Slicemask (Const64 [x])) // cond: x > 0 // result: (Const64 [-1]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } x := v_0.AuxInt if !(x > 0) { break } v.reset(OpConst64) v.AuxInt = -1 return true } // match: (Slicemask (Const64 [0])) // cond: // result: (Const64 [0]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpConst64) v.AuxInt = 0 return true } return false } func rewriteValuegeneric_OpSqrt_0(v *Value) bool { // match: (Sqrt (Const64F [c])) // cond: // result: (Const64F [auxFrom64F(math.Sqrt(auxTo64F(c)))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(math.Sqrt(auxTo64F(c))) return true } return false } func rewriteValuegeneric_OpStaticCall_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (StaticCall {sym} s1:(Store _ (Const64 [sz]) s2:(Store _ src s3:(Store {t} _ dst mem)))) // cond: isSameSym(sym,"runtime.memmove") && t.(*types.Type).IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst,src,sz,config) && clobber(s1) && clobber(s2) && clobber(s3) // result: (Move {t.(*types.Type).Elem()} [sz] dst src mem) for { sym := v.Aux s1 := v.Args[0] if s1.Op != OpStore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpConst64 { break } sz := s1_1.AuxInt s2 := s1.Args[2] if s2.Op != OpStore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpStore { break } t := s3.Aux mem := s3.Args[2] dst := s3.Args[1] if !(isSameSym(sym, "runtime.memmove") && t.(*types.Type).IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(s1) && clobber(s2) && clobber(s3)) { break } v.reset(OpMove) v.AuxInt = sz v.Aux = t.(*types.Type).Elem() v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } // match: (StaticCall {sym} s1:(Store _ (Const32 [sz]) s2:(Store _ src s3:(Store {t} _ dst mem)))) // cond: isSameSym(sym,"runtime.memmove") && t.(*types.Type).IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst,src,sz,config) && clobber(s1) && clobber(s2) && clobber(s3) // result: (Move {t.(*types.Type).Elem()} [sz] dst src mem) for { sym := v.Aux s1 := v.Args[0] if s1.Op != OpStore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpConst32 { break } sz := s1_1.AuxInt s2 := s1.Args[2] if s2.Op != OpStore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpStore { break } t := s3.Aux mem := s3.Args[2] dst := s3.Args[1] if !(isSameSym(sym, "runtime.memmove") && t.(*types.Type).IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(s1) && clobber(s2) && clobber(s3)) { break } v.reset(OpMove) v.AuxInt = sz v.Aux = t.(*types.Type).Elem() v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } // match: (StaticCall {sym} x) // cond: needRaceCleanup(sym,v) // result: x for { sym := v.Aux x := v.Args[0] if !(needRaceCleanup(sym, v)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpStore_0(v *Value) bool { b := v.Block // match: (Store {t1} p1 (Load p2 mem) mem) // cond: isSamePtr(p1, p2) && t2.Size() == sizeof(t1) // result: mem for { t1 := v.Aux mem := v.Args[2] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLoad { break } t2 := v_1.Type _ = v_1.Args[1] p2 := v_1.Args[0] if mem != v_1.Args[1] { break } if !(isSamePtr(p1, p2) && t2.Size() == sizeof(t1)) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ oldmem)) // cond: isSamePtr(p1, p2) && t2.Size() == sizeof(t1) && disjoint(p1, sizeof(t1), p3, sizeof(t3)) // result: mem for { t1 := v.Aux _ = v.Args[2] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v.Args[2] if mem.Op != OpStore { break } t3 := mem.Aux _ = mem.Args[2] p3 := mem.Args[0] if oldmem != mem.Args[2] { break } if !(isSamePtr(p1, p2) && t2.Size() == sizeof(t1) && disjoint(p1, sizeof(t1), p3, sizeof(t3))) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ (Store {t4} p4 _ oldmem))) // cond: isSamePtr(p1, p2) && t2.Size() == sizeof(t1) && disjoint(p1, sizeof(t1), p3, sizeof(t3)) && disjoint(p1, sizeof(t1), p4, sizeof(t4)) // result: mem for { t1 := v.Aux _ = v.Args[2] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v.Args[2] if mem.Op != OpStore { break } t3 := mem.Aux _ = mem.Args[2] p3 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t4 := mem_2.Aux _ = mem_2.Args[2] p4 := mem_2.Args[0] if oldmem != mem_2.Args[2] { break } if !(isSamePtr(p1, p2) && t2.Size() == sizeof(t1) && disjoint(p1, sizeof(t1), p3, sizeof(t3)) && disjoint(p1, sizeof(t1), p4, sizeof(t4))) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 _ oldmem)))) // cond: isSamePtr(p1, p2) && t2.Size() == sizeof(t1) && disjoint(p1, sizeof(t1), p3, sizeof(t3)) && disjoint(p1, sizeof(t1), p4, sizeof(t4)) && disjoint(p1, sizeof(t1), p5, sizeof(t5)) // result: mem for { t1 := v.Aux _ = v.Args[2] p1 := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v.Args[2] if mem.Op != OpStore { break } t3 := mem.Aux _ = mem.Args[2] p3 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t4 := mem_2.Aux _ = mem_2.Args[2] p4 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t5 := mem_2_2.Aux _ = mem_2_2.Args[2] p5 := mem_2_2.Args[0] if oldmem != mem_2_2.Args[2] { break } if !(isSamePtr(p1, p2) && t2.Size() == sizeof(t1) && disjoint(p1, sizeof(t1), p3, sizeof(t3)) && disjoint(p1, sizeof(t1), p4, sizeof(t4)) && disjoint(p1, sizeof(t1), p5, sizeof(t5))) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t} (OffPtr [o] p1) x mem:(Zero [n] p2 _)) // cond: isConstZero(x) && o >= 0 && sizeof(t) + o <= n && isSamePtr(p1, p2) // result: mem for { t := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } o := v_0.AuxInt p1 := v_0.Args[0] x := v.Args[1] mem := v.Args[2] if mem.Op != OpZero { break } n := mem.AuxInt _ = mem.Args[1] p2 := mem.Args[0] if !(isConstZero(x) && o >= 0 && sizeof(t)+o <= n && isSamePtr(p1, p2)) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Zero [n] p3 _))) // cond: isConstZero(x) && o1 >= 0 && sizeof(t1) + o1 <= n && isSamePtr(p1, p3) && disjoint(op, sizeof(t1), p2, sizeof(t2)) // result: mem for { t1 := v.Aux _ = v.Args[2] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] x := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpZero { break } n := mem_2.AuxInt _ = mem_2.Args[1] p3 := mem_2.Args[0] if !(isConstZero(x) && o1 >= 0 && sizeof(t1)+o1 <= n && isSamePtr(p1, p3) && disjoint(op, sizeof(t1), p2, sizeof(t2))) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Store {t3} p3 _ (Zero [n] p4 _)))) // cond: isConstZero(x) && o1 >= 0 && sizeof(t1) + o1 <= n && isSamePtr(p1, p4) && disjoint(op, sizeof(t1), p2, sizeof(t2)) && disjoint(op, sizeof(t1), p3, sizeof(t3)) // result: mem for { t1 := v.Aux _ = v.Args[2] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] x := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] p3 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpZero { break } n := mem_2_2.AuxInt _ = mem_2_2.Args[1] p4 := mem_2_2.Args[0] if !(isConstZero(x) && o1 >= 0 && sizeof(t1)+o1 <= n && isSamePtr(p1, p4) && disjoint(op, sizeof(t1), p2, sizeof(t2)) && disjoint(op, sizeof(t1), p3, sizeof(t3))) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Zero [n] p5 _))))) // cond: isConstZero(x) && o1 >= 0 && sizeof(t1) + o1 <= n && isSamePtr(p1, p5) && disjoint(op, sizeof(t1), p2, sizeof(t2)) && disjoint(op, sizeof(t1), p3, sizeof(t3)) && disjoint(op, sizeof(t1), p4, sizeof(t4)) // result: mem for { t1 := v.Aux _ = v.Args[2] op := v.Args[0] if op.Op != OpOffPtr { break } o1 := op.AuxInt p1 := op.Args[0] x := v.Args[1] mem := v.Args[2] if mem.Op != OpStore { break } t2 := mem.Aux _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := mem_2.Aux _ = mem_2.Args[2] p3 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := mem_2_2.Aux _ = mem_2_2.Args[2] p4 := mem_2_2.Args[0] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpZero { break } n := mem_2_2_2.AuxInt _ = mem_2_2_2.Args[1] p5 := mem_2_2_2.Args[0] if !(isConstZero(x) && o1 >= 0 && sizeof(t1)+o1 <= n && isSamePtr(p1, p5) && disjoint(op, sizeof(t1), p2, sizeof(t2)) && disjoint(op, sizeof(t1), p3, sizeof(t3)) && disjoint(op, sizeof(t1), p4, sizeof(t4))) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store _ (StructMake0) mem) // cond: // result: mem for { mem := v.Args[2] v_1 := v.Args[1] if v_1.Op != OpStructMake0 { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store dst (StructMake1 f0) mem) // cond: // result: (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem) for { mem := v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStructMake1 { break } t := v_1.Type f0 := v_1.Args[0] v.reset(OpStore) v.Aux = t.FieldType(0) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v0.AuxInt = 0 v0.AddArg(dst) v.AddArg(v0) v.AddArg(f0) v.AddArg(mem) return true } return false } func rewriteValuegeneric_OpStore_10(v *Value) bool { b := v.Block config := b.Func.Config fe := b.Func.fe // match: (Store dst (StructMake2 f0 f1) mem) // cond: // result: (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem)) for { mem := v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStructMake2 { break } t := v_1.Type f1 := v_1.Args[1] f0 := v_1.Args[0] v.reset(OpStore) v.Aux = t.FieldType(1) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v0.AuxInt = t.FieldOff(1) v0.AddArg(dst) v.AddArg(v0) v.AddArg(f1) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t.FieldType(0) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v2.AuxInt = 0 v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(f0) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Store dst (StructMake3 f0 f1 f2) mem) // cond: // result: (Store {t.FieldType(2)} (OffPtr [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem))) for { mem := v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStructMake3 { break } t := v_1.Type f2 := v_1.Args[2] f0 := v_1.Args[0] f1 := v_1.Args[1] v.reset(OpStore) v.Aux = t.FieldType(2) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v0.AuxInt = t.FieldOff(2) v0.AddArg(dst) v.AddArg(v0) v.AddArg(f2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t.FieldType(1) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v2.AuxInt = t.FieldOff(1) v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(f1) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t.FieldType(0) v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v4.AuxInt = 0 v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(f0) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Store dst (StructMake4 f0 f1 f2 f3) mem) // cond: // result: (Store {t.FieldType(3)} (OffPtr [t.FieldOff(3)] dst) f3 (Store {t.FieldType(2)} (OffPtr [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem)))) for { mem := v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpStructMake4 { break } t := v_1.Type f3 := v_1.Args[3] f0 := v_1.Args[0] f1 := v_1.Args[1] f2 := v_1.Args[2] v.reset(OpStore) v.Aux = t.FieldType(3) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo()) v0.AuxInt = t.FieldOff(3) v0.AddArg(dst) v.AddArg(v0) v.AddArg(f3) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t.FieldType(2) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v2.AuxInt = t.FieldOff(2) v2.AddArg(dst) v1.AddArg(v2) v1.AddArg(f2) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = t.FieldType(1) v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v4.AuxInt = t.FieldOff(1) v4.AddArg(dst) v3.AddArg(v4) v3.AddArg(f1) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = t.FieldType(0) v6 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v6.AuxInt = 0 v6.AddArg(dst) v5.AddArg(v6) v5.AddArg(f0) v5.AddArg(mem) v3.AddArg(v5) v1.AddArg(v3) v.AddArg(v1) return true } // match: (Store {t} dst (Load src mem) mem) // cond: !fe.CanSSA(t.(*types.Type)) // result: (Move {t} [sizeof(t)] dst src mem) for { t := v.Aux mem := v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLoad { break } _ = v_1.Args[1] src := v_1.Args[0] if mem != v_1.Args[1] { break } if !(!fe.CanSSA(t.(*types.Type))) { break } v.reset(OpMove) v.AuxInt = sizeof(t) v.Aux = t v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } // match: (Store {t} dst (Load src mem) (VarDef {x} mem)) // cond: !fe.CanSSA(t.(*types.Type)) // result: (Move {t} [sizeof(t)] dst src (VarDef {x} mem)) for { t := v.Aux _ = v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpLoad { break } mem := v_1.Args[1] src := v_1.Args[0] v_2 := v.Args[2] if v_2.Op != OpVarDef { break } x := v_2.Aux if mem != v_2.Args[0] { break } if !(!fe.CanSSA(t.(*types.Type))) { break } v.reset(OpMove) v.AuxInt = sizeof(t) v.Aux = t v.AddArg(dst) v.AddArg(src) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = x v0.AddArg(mem) v.AddArg(v0) return true } // match: (Store _ (ArrayMake0) mem) // cond: // result: mem for { mem := v.Args[2] v_1 := v.Args[1] if v_1.Op != OpArrayMake0 { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store dst (ArrayMake1 e) mem) // cond: // result: (Store {e.Type} dst e mem) for { mem := v.Args[2] dst := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpArrayMake1 { break } e := v_1.Args[0] v.reset(OpStore) v.Aux = e.Type v.AddArg(dst) v.AddArg(e) v.AddArg(mem) return true } // match: (Store (Load (OffPtr [c] (SP)) mem) x mem) // cond: isConstZero(x) && mem.Op == OpStaticCall && isSameSym(mem.Aux, "runtime.newobject") && c == config.ctxt.FixedFrameSize() + config.RegSize // result: mem for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpLoad { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpOffPtr { break } c := v_0_0.AuxInt v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpSP { break } if mem != v_0.Args[1] { break } x := v.Args[1] if !(isConstZero(x) && mem.Op == OpStaticCall && isSameSym(mem.Aux, "runtime.newobject") && c == config.ctxt.FixedFrameSize()+config.RegSize) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store (OffPtr (Load (OffPtr [c] (SP)) mem)) x mem) // cond: isConstZero(x) && mem.Op == OpStaticCall && isSameSym(mem.Aux, "runtime.newobject") && c == config.ctxt.FixedFrameSize() + config.RegSize // result: mem for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpOffPtr { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLoad { break } _ = v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpOffPtr { break } c := v_0_0_0.AuxInt v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpSP { break } if mem != v_0_0.Args[1] { break } x := v.Args[1] if !(isConstZero(x) && mem.Op == OpStaticCall && isSameSym(mem.Aux, "runtime.newobject") && c == config.ctxt.FixedFrameSize()+config.RegSize) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [0] p2) d2 m3:(Move [n] p3 _ mem))) // cond: m2.Uses == 1 && m3.Uses == 1 && o1 == sizeof(t2) && n == sizeof(t2) + sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2) && clobber(m3) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 mem)) for { t1 := v.Aux _ = v.Args[2] op1 := v.Args[0] if op1.Op != OpOffPtr { break } o1 := op1.AuxInt p1 := op1.Args[0] d1 := v.Args[1] m2 := v.Args[2] if m2.Op != OpStore { break } t2 := m2.Aux _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } if op2.AuxInt != 0 { break } p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpMove { break } n := m3.AuxInt mem := m3.Args[2] p3 := m3.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && o1 == sizeof(t2) && n == sizeof(t2)+sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2) && clobber(m3)) { break } v.reset(OpStore) v.Aux = t1 v.AddArg(op1) v.AddArg(d1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = t2 v0.AddArg(op2) v0.AddArg(d2) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpStore_20(v *Value) bool { b := v.Block // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Move [n] p4 _ mem)))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t3) + sizeof(t2) + sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2) && clobber(m3) && clobber(m4) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 mem))) for { t1 := v.Aux _ = v.Args[2] op1 := v.Args[0] if op1.Op != OpOffPtr { break } o1 := op1.AuxInt p1 := op1.Args[0] d1 := v.Args[1] m2 := v.Args[2] if m2.Op != OpStore { break } t2 := m2.Aux _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := op2.AuxInt p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := m3.Aux _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } if op3.AuxInt != 0 { break } p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpMove { break } n := m4.AuxInt mem := m4.Args[2] p4 := m4.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t3)+sizeof(t2)+sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2) && clobber(m3) && clobber(m4)) { break } v.reset(OpStore) v.Aux = t1 v.AddArg(op1) v.AddArg(d1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = t2 v0.AddArg(op2) v0.AddArg(d2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v1.AddArg(op3) v1.AddArg(d3) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Move [n] p5 _ mem))))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t4) + sizeof(t3) + sizeof(t2) + sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2) && clobber(m3) && clobber(m4) && clobber(m5) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 (Store {t4} op4 d4 mem)))) for { t1 := v.Aux _ = v.Args[2] op1 := v.Args[0] if op1.Op != OpOffPtr { break } o1 := op1.AuxInt p1 := op1.Args[0] d1 := v.Args[1] m2 := v.Args[2] if m2.Op != OpStore { break } t2 := m2.Aux _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := op2.AuxInt p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := m3.Aux _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } o3 := op3.AuxInt p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpStore { break } t4 := m4.Aux _ = m4.Args[2] op4 := m4.Args[0] if op4.Op != OpOffPtr { break } if op4.AuxInt != 0 { break } p4 := op4.Args[0] d4 := m4.Args[1] m5 := m4.Args[2] if m5.Op != OpMove { break } n := m5.AuxInt mem := m5.Args[2] p5 := m5.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t4)+sizeof(t3)+sizeof(t2)+sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2) && clobber(m3) && clobber(m4) && clobber(m5)) { break } v.reset(OpStore) v.Aux = t1 v.AddArg(op1) v.AddArg(d1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = t2 v0.AddArg(op2) v0.AddArg(d2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v1.AddArg(op3) v1.AddArg(d3) v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v2.Aux = t4 v2.AddArg(op4) v2.AddArg(d4) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [0] p2) d2 m3:(Zero [n] p3 mem))) // cond: m2.Uses == 1 && m3.Uses == 1 && o1 == sizeof(t2) && n == sizeof(t2) + sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2) && clobber(m3) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 mem)) for { t1 := v.Aux _ = v.Args[2] op1 := v.Args[0] if op1.Op != OpOffPtr { break } o1 := op1.AuxInt p1 := op1.Args[0] d1 := v.Args[1] m2 := v.Args[2] if m2.Op != OpStore { break } t2 := m2.Aux _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } if op2.AuxInt != 0 { break } p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpZero { break } n := m3.AuxInt mem := m3.Args[1] p3 := m3.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && o1 == sizeof(t2) && n == sizeof(t2)+sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2) && clobber(m3)) { break } v.reset(OpStore) v.Aux = t1 v.AddArg(op1) v.AddArg(d1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = t2 v0.AddArg(op2) v0.AddArg(d2) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Zero [n] p4 mem)))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t3) + sizeof(t2) + sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2) && clobber(m3) && clobber(m4) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 mem))) for { t1 := v.Aux _ = v.Args[2] op1 := v.Args[0] if op1.Op != OpOffPtr { break } o1 := op1.AuxInt p1 := op1.Args[0] d1 := v.Args[1] m2 := v.Args[2] if m2.Op != OpStore { break } t2 := m2.Aux _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := op2.AuxInt p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := m3.Aux _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } if op3.AuxInt != 0 { break } p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpZero { break } n := m4.AuxInt mem := m4.Args[1] p4 := m4.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t3)+sizeof(t2)+sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2) && clobber(m3) && clobber(m4)) { break } v.reset(OpStore) v.Aux = t1 v.AddArg(op1) v.AddArg(d1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = t2 v0.AddArg(op2) v0.AddArg(d2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v1.AddArg(op3) v1.AddArg(d3) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Zero [n] p5 mem))))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t4) + sizeof(t3) + sizeof(t2) + sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2) && clobber(m3) && clobber(m4) && clobber(m5) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 (Store {t4} op4 d4 mem)))) for { t1 := v.Aux _ = v.Args[2] op1 := v.Args[0] if op1.Op != OpOffPtr { break } o1 := op1.AuxInt p1 := op1.Args[0] d1 := v.Args[1] m2 := v.Args[2] if m2.Op != OpStore { break } t2 := m2.Aux _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := op2.AuxInt p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := m3.Aux _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } o3 := op3.AuxInt p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpStore { break } t4 := m4.Aux _ = m4.Args[2] op4 := m4.Args[0] if op4.Op != OpOffPtr { break } if op4.AuxInt != 0 { break } p4 := op4.Args[0] d4 := m4.Args[1] m5 := m4.Args[2] if m5.Op != OpZero { break } n := m5.AuxInt mem := m5.Args[1] p5 := m5.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == sizeof(t4) && o2-o3 == sizeof(t3) && o1-o2 == sizeof(t2) && n == sizeof(t4)+sizeof(t3)+sizeof(t2)+sizeof(t1) && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2) && clobber(m3) && clobber(m4) && clobber(m5)) { break } v.reset(OpStore) v.Aux = t1 v.AddArg(op1) v.AddArg(d1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = t2 v0.AddArg(op2) v0.AddArg(d2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = t3 v1.AddArg(op3) v1.AddArg(d3) v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v2.Aux = t4 v2.AddArg(op4) v2.AddArg(d4) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpStringLen_0(v *Value) bool { // match: (StringLen (StringMake _ (Const64 [c]))) // cond: // result: (Const64 [c]) for { v_0 := v.Args[0] if v_0.Op != OpStringMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type c := v_0_1.AuxInt v.reset(OpConst64) v.Type = t v.AuxInt = c return true } return false } func rewriteValuegeneric_OpStringPtr_0(v *Value) bool { // match: (StringPtr (StringMake (Addr {s} base) _)) // cond: // result: (Addr {s} base) for { v_0 := v.Args[0] if v_0.Op != OpStringMake { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { break } t := v_0_0.Type s := v_0_0.Aux base := v_0_0.Args[0] v.reset(OpAddr) v.Type = t v.Aux = s v.AddArg(base) return true } return false } func rewriteValuegeneric_OpStructSelect_0(v *Value) bool { // match: (StructSelect (StructMake1 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpStructMake1 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [0] (StructMake2 x _)) // cond: // result: x for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake2 { break } _ = v_0.Args[1] x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [1] (StructMake2 _ x)) // cond: // result: x for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake2 { break } x := v_0.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [0] (StructMake3 x _ _)) // cond: // result: x for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake3 { break } _ = v_0.Args[2] x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [1] (StructMake3 _ x _)) // cond: // result: x for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake3 { break } _ = v_0.Args[2] x := v_0.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [2] (StructMake3 _ _ x)) // cond: // result: x for { if v.AuxInt != 2 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake3 { break } x := v_0.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [0] (StructMake4 x _ _ _)) // cond: // result: x for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake4 { break } _ = v_0.Args[3] x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [1] (StructMake4 _ x _ _)) // cond: // result: x for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake4 { break } _ = v_0.Args[3] x := v_0.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [2] (StructMake4 _ _ x _)) // cond: // result: x for { if v.AuxInt != 2 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake4 { break } _ = v_0.Args[3] x := v_0.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (StructSelect [3] (StructMake4 _ _ _ x)) // cond: // result: x for { if v.AuxInt != 3 { break } v_0 := v.Args[0] if v_0.Op != OpStructMake4 { break } x := v_0.Args[3] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpStructSelect_10(v *Value) bool { b := v.Block fe := b.Func.fe // match: (StructSelect [i] x:(Load ptr mem)) // cond: !fe.CanSSA(t) // result: @x.Block (Load (OffPtr [t.FieldOff(int(i))] ptr) mem) for { i := v.AuxInt x := v.Args[0] if x.Op != OpLoad { break } t := x.Type mem := x.Args[1] ptr := x.Args[0] if !(!fe.CanSSA(t)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpLoad, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, v.Type.PtrTo()) v1.AuxInt = t.FieldOff(int(i)) v1.AddArg(ptr) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (StructSelect [0] x:(IData _)) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] if x.Op != OpIData { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub16_0(v *Value) bool { b := v.Block // match: (Sub16 (Const16 [c]) (Const16 [d])) // cond: // result: (Const16 [int64(int16(c-d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c - d)) return true } // match: (Sub16 x (Const16 [c])) // cond: x.Op != OpConst16 // result: (Add16 (Const16 [int64(int16(-c))]) x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } t := v_1.Type c := v_1.AuxInt if !(x.Op != OpConst16) { break } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(-c)) v.AddArg(v0) v.AddArg(x) return true } // match: (Sub16 (Mul16 x y) (Mul16 x z)) // cond: // result: (Mul16 x (Sub16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub16 (Mul16 y x) (Mul16 x z)) // cond: // result: (Mul16 x (Sub16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub16 (Mul16 x y) (Mul16 z x)) // cond: // result: (Mul16 x (Sub16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub16 (Mul16 y x) (Mul16 z x)) // cond: // result: (Mul16 x (Sub16 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul16 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul16 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul16) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub16 x x) // cond: // result: (Const16 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Sub16 (Add16 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub16 (Add16 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub16 (Add16 x y) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] x := v_0.Args[0] if y != v_0.Args[1] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub16_10(v *Value) bool { b := v.Block // match: (Sub16 (Add16 y x) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd16 { break } x := v_0.Args[1] if y != v_0.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Sub16 x (Sub16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Sub16 x (Sub16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpAdd16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub16 (Const16 [c]) (Sub16 x (Const16 [d]))) // cond: // result: (Sub16 (Const16 [int64(int16(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Sub16 (Const16 [c]) (Sub16 (Const16 [d]) x)) // cond: // result: (Add16 (Const16 [int64(int16(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c - d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub32_0(v *Value) bool { b := v.Block // match: (Sub32 (Const32 [c]) (Const32 [d])) // cond: // result: (Const32 [int64(int32(c-d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c - d)) return true } // match: (Sub32 x (Const32 [c])) // cond: x.Op != OpConst32 // result: (Add32 (Const32 [int64(int32(-c))]) x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } t := v_1.Type c := v_1.AuxInt if !(x.Op != OpConst32) { break } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(-c)) v.AddArg(v0) v.AddArg(x) return true } // match: (Sub32 (Mul32 x y) (Mul32 x z)) // cond: // result: (Mul32 x (Sub32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub32 (Mul32 y x) (Mul32 x z)) // cond: // result: (Mul32 x (Sub32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub32 (Mul32 x y) (Mul32 z x)) // cond: // result: (Mul32 x (Sub32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub32 (Mul32 y x) (Mul32 z x)) // cond: // result: (Mul32 x (Sub32 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul32 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul32 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul32) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub32 x x) // cond: // result: (Const32 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Sub32 (Add32 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub32 (Add32 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub32 (Add32 x y) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] x := v_0.Args[0] if y != v_0.Args[1] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub32_10(v *Value) bool { b := v.Block // match: (Sub32 (Add32 y x) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd32 { break } x := v_0.Args[1] if y != v_0.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Sub32 x (Sub32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Sub32 x (Sub32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpAdd32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub32 (Const32 [c]) (Sub32 x (Const32 [d]))) // cond: // result: (Sub32 (Const32 [int64(int32(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Sub32 (Const32 [c]) (Sub32 (Const32 [d]) x)) // cond: // result: (Add32 (Const32 [int64(int32(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c - d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub32F_0(v *Value) bool { // match: (Sub32F (Const32F [c]) (Const32F [d])) // cond: // result: (Const32F [auxFrom32F(auxTo32F(c) - auxTo32F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32F { break } d := v_1.AuxInt v.reset(OpConst32F) v.AuxInt = auxFrom32F(auxTo32F(c) - auxTo32F(d)) return true } return false } func rewriteValuegeneric_OpSub64_0(v *Value) bool { b := v.Block // match: (Sub64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c-d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c - d return true } // match: (Sub64 x (Const64 [c])) // cond: x.Op != OpConst64 // result: (Add64 (Const64 [-c]) x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } t := v_1.Type c := v_1.AuxInt if !(x.Op != OpConst64) { break } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = -c v.AddArg(v0) v.AddArg(x) return true } // match: (Sub64 (Mul64 x y) (Mul64 x z)) // cond: // result: (Mul64 x (Sub64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub64 (Mul64 y x) (Mul64 x z)) // cond: // result: (Mul64 x (Sub64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub64 (Mul64 x y) (Mul64 z x)) // cond: // result: (Mul64 x (Sub64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub64 (Mul64 y x) (Mul64 z x)) // cond: // result: (Mul64 x (Sub64 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul64 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul64 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul64) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub64 x x) // cond: // result: (Const64 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Sub64 (Add64 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub64 (Add64 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub64 (Add64 x y) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] x := v_0.Args[0] if y != v_0.Args[1] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub64_10(v *Value) bool { b := v.Block // match: (Sub64 (Add64 y x) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd64 { break } x := v_0.Args[1] if y != v_0.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Sub64 x (Sub64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Sub64 x (Sub64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpAdd64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub64 (Const64 [c]) (Sub64 x (Const64 [d]))) // cond: // result: (Sub64 (Const64 [c+d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c + d v.AddArg(v0) v.AddArg(x) return true } // match: (Sub64 (Const64 [c]) (Sub64 (Const64 [d]) x)) // cond: // result: (Add64 (Const64 [c-d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c - d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub64F_0(v *Value) bool { // match: (Sub64F (Const64F [c]) (Const64F [d])) // cond: // result: (Const64F [auxFrom64F(auxTo64F(c) - auxTo64F(d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64F { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64F { break } d := v_1.AuxInt v.reset(OpConst64F) v.AuxInt = auxFrom64F(auxTo64F(c) - auxTo64F(d)) return true } return false } func rewriteValuegeneric_OpSub8_0(v *Value) bool { b := v.Block // match: (Sub8 (Const8 [c]) (Const8 [d])) // cond: // result: (Const8 [int64(int8(c-d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c - d)) return true } // match: (Sub8 x (Const8 [c])) // cond: x.Op != OpConst8 // result: (Add8 (Const8 [int64(int8(-c))]) x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } t := v_1.Type c := v_1.AuxInt if !(x.Op != OpConst8) { break } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(-c)) v.AddArg(v0) v.AddArg(x) return true } // match: (Sub8 (Mul8 x y) (Mul8 x z)) // cond: // result: (Mul8 x (Sub8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub8 (Mul8 y x) (Mul8 x z)) // cond: // result: (Mul8 x (Sub8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } z := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub8 (Mul8 x y) (Mul8 z x)) // cond: // result: (Mul8 x (Sub8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub8 (Mul8 y x) (Mul8 z x)) // cond: // result: (Mul8 x (Sub8 y z)) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpMul8 { break } x := v_0.Args[1] y := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpMul8 { break } _ = v_1.Args[1] z := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpMul8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(y) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub8 x x) // cond: // result: (Const8 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Sub8 (Add8 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub8 (Add8 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Sub8 (Add8 x y) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] x := v_0.Args[0] if y != v_0.Args[1] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub8_10(v *Value) bool { b := v.Block // match: (Sub8 (Add8 y x) y) // cond: // result: x for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAdd8 { break } x := v_0.Args[1] if y != v_0.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Sub8 x (Sub8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) v.AddArg(i) return true } // match: (Sub8 x (Sub8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpSub8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpAdd8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg(x) v0.AddArg(z) v.AddArg(v0) return true } // match: (Sub8 (Const8 [c]) (Sub8 x (Const8 [d]))) // cond: // result: (Sub8 (Const8 [int64(int8(c+d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c + d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Sub8 (Const8 [c]) (Sub8 (Const8 [d]) x)) // cond: // result: (Add8 (Const8 [int64(int8(c-d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpSub8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c - d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpTrunc16to8_0(v *Value) bool { // match: (Trunc16to8 (Const16 [c])) // cond: // result: (Const8 [int64(int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c)) return true } // match: (Trunc16to8 (ZeroExt8to16 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpZeroExt8to16 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc16to8 (SignExt8to16 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpSignExt8to16 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc16to8 (And16 (Const16 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc16to8 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } y := v_0_0.AuxInt if !(y&0xFF == 0xFF) { break } v.reset(OpTrunc16to8) v.AddArg(x) return true } // match: (Trunc16to8 (And16 x (Const16 [y]))) // cond: y&0xFF == 0xFF // result: (Trunc16to8 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } y := v_0_1.AuxInt if !(y&0xFF == 0xFF) { break } v.reset(OpTrunc16to8) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpTrunc32to16_0(v *Value) bool { // match: (Trunc32to16 (Const32 [c])) // cond: // result: (Const16 [int64(int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c)) return true } // match: (Trunc32to16 (ZeroExt8to32 x)) // cond: // result: (ZeroExt8to16 x) for { v_0 := v.Args[0] if v_0.Op != OpZeroExt8to32 { break } x := v_0.Args[0] v.reset(OpZeroExt8to16) v.AddArg(x) return true } // match: (Trunc32to16 (ZeroExt16to32 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpZeroExt16to32 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc32to16 (SignExt8to32 x)) // cond: // result: (SignExt8to16 x) for { v_0 := v.Args[0] if v_0.Op != OpSignExt8to32 { break } x := v_0.Args[0] v.reset(OpSignExt8to16) v.AddArg(x) return true } // match: (Trunc32to16 (SignExt16to32 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpSignExt16to32 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc32to16 (And32 (Const32 [y]) x)) // cond: y&0xFFFF == 0xFFFF // result: (Trunc32to16 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } y := v_0_0.AuxInt if !(y&0xFFFF == 0xFFFF) { break } v.reset(OpTrunc32to16) v.AddArg(x) return true } // match: (Trunc32to16 (And32 x (Const32 [y]))) // cond: y&0xFFFF == 0xFFFF // result: (Trunc32to16 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } y := v_0_1.AuxInt if !(y&0xFFFF == 0xFFFF) { break } v.reset(OpTrunc32to16) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpTrunc32to8_0(v *Value) bool { // match: (Trunc32to8 (Const32 [c])) // cond: // result: (Const8 [int64(int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c)) return true } // match: (Trunc32to8 (ZeroExt8to32 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpZeroExt8to32 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc32to8 (SignExt8to32 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpSignExt8to32 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc32to8 (And32 (Const32 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc32to8 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } y := v_0_0.AuxInt if !(y&0xFF == 0xFF) { break } v.reset(OpTrunc32to8) v.AddArg(x) return true } // match: (Trunc32to8 (And32 x (Const32 [y]))) // cond: y&0xFF == 0xFF // result: (Trunc32to8 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } y := v_0_1.AuxInt if !(y&0xFF == 0xFF) { break } v.reset(OpTrunc32to8) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpTrunc64to16_0(v *Value) bool { // match: (Trunc64to16 (Const64 [c])) // cond: // result: (Const16 [int64(int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c)) return true } // match: (Trunc64to16 (ZeroExt8to64 x)) // cond: // result: (ZeroExt8to16 x) for { v_0 := v.Args[0] if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpZeroExt8to16) v.AddArg(x) return true } // match: (Trunc64to16 (ZeroExt16to64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpZeroExt16to64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc64to16 (SignExt8to64 x)) // cond: // result: (SignExt8to16 x) for { v_0 := v.Args[0] if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpSignExt8to16) v.AddArg(x) return true } // match: (Trunc64to16 (SignExt16to64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpSignExt16to64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc64to16 (And64 (Const64 [y]) x)) // cond: y&0xFFFF == 0xFFFF // result: (Trunc64to16 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } y := v_0_0.AuxInt if !(y&0xFFFF == 0xFFFF) { break } v.reset(OpTrunc64to16) v.AddArg(x) return true } // match: (Trunc64to16 (And64 x (Const64 [y]))) // cond: y&0xFFFF == 0xFFFF // result: (Trunc64to16 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } y := v_0_1.AuxInt if !(y&0xFFFF == 0xFFFF) { break } v.reset(OpTrunc64to16) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpTrunc64to32_0(v *Value) bool { // match: (Trunc64to32 (Const64 [c])) // cond: // result: (Const32 [int64(int32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c)) return true } // match: (Trunc64to32 (ZeroExt8to64 x)) // cond: // result: (ZeroExt8to32 x) for { v_0 := v.Args[0] if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpZeroExt8to32) v.AddArg(x) return true } // match: (Trunc64to32 (ZeroExt16to64 x)) // cond: // result: (ZeroExt16to32 x) for { v_0 := v.Args[0] if v_0.Op != OpZeroExt16to64 { break } x := v_0.Args[0] v.reset(OpZeroExt16to32) v.AddArg(x) return true } // match: (Trunc64to32 (ZeroExt32to64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpZeroExt32to64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc64to32 (SignExt8to64 x)) // cond: // result: (SignExt8to32 x) for { v_0 := v.Args[0] if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpSignExt8to32) v.AddArg(x) return true } // match: (Trunc64to32 (SignExt16to64 x)) // cond: // result: (SignExt16to32 x) for { v_0 := v.Args[0] if v_0.Op != OpSignExt16to64 { break } x := v_0.Args[0] v.reset(OpSignExt16to32) v.AddArg(x) return true } // match: (Trunc64to32 (SignExt32to64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpSignExt32to64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc64to32 (And64 (Const64 [y]) x)) // cond: y&0xFFFFFFFF == 0xFFFFFFFF // result: (Trunc64to32 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } y := v_0_0.AuxInt if !(y&0xFFFFFFFF == 0xFFFFFFFF) { break } v.reset(OpTrunc64to32) v.AddArg(x) return true } // match: (Trunc64to32 (And64 x (Const64 [y]))) // cond: y&0xFFFFFFFF == 0xFFFFFFFF // result: (Trunc64to32 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } y := v_0_1.AuxInt if !(y&0xFFFFFFFF == 0xFFFFFFFF) { break } v.reset(OpTrunc64to32) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpTrunc64to8_0(v *Value) bool { // match: (Trunc64to8 (Const64 [c])) // cond: // result: (Const8 [int64(int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c)) return true } // match: (Trunc64to8 (ZeroExt8to64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc64to8 (SignExt8to64 x)) // cond: // result: x for { v_0 := v.Args[0] if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Trunc64to8 (And64 (Const64 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc64to8 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } y := v_0_0.AuxInt if !(y&0xFF == 0xFF) { break } v.reset(OpTrunc64to8) v.AddArg(x) return true } // match: (Trunc64to8 (And64 x (Const64 [y]))) // cond: y&0xFF == 0xFF // result: (Trunc64to8 x) for { v_0 := v.Args[0] if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } y := v_0_1.AuxInt if !(y&0xFF == 0xFF) { break } v.reset(OpTrunc64to8) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpXor16_0(v *Value) bool { b := v.Block // match: (Xor16 (Const16 [c]) (Const16 [d])) // cond: // result: (Const16 [int64(int16(c^d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } d := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c ^ d)) return true } // match: (Xor16 (Const16 [d]) (Const16 [c])) // cond: // result: (Const16 [int64(int16(c^d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } c := v_1.AuxInt v.reset(OpConst16) v.AuxInt = int64(int16(c ^ d)) return true } // match: (Xor16 x x) // cond: // result: (Const16 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst16) v.AuxInt = 0 return true } // match: (Xor16 (Const16 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor16 x (Const16 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor16 x (Xor16 x y)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor16 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor16 x (Xor16 y x)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor16 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor16 (Xor16 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor16 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor16 (Xor16 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor16 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor16 (Xor16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Xor16 i (Xor16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpXor16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpXor16_10(v *Value) bool { b := v.Block // match: (Xor16 (Xor16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Xor16 i (Xor16 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor16 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpXor16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor16 x (Xor16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Xor16 i (Xor16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpXor16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor16 x (Xor16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Xor16 i (Xor16 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor16 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpXor16) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor16, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor16 (Const16 [c]) (Xor16 (Const16 [d]) x)) // cond: // result: (Xor16 (Const16 [int64(int16(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor16 (Const16 [c]) (Xor16 x (Const16 [d]))) // cond: // result: (Xor16 (Const16 [int64(int16(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor16 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor16 (Xor16 (Const16 [d]) x) (Const16 [c])) // cond: // result: (Xor16 (Const16 [int64(int16(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor16 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor16 (Xor16 x (Const16 [d])) (Const16 [c])) // cond: // result: (Xor16 (Const16 [int64(int16(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor16 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst16 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int64(int16(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpXor32_0(v *Value) bool { b := v.Block // match: (Xor32 (Const32 [c]) (Const32 [d])) // cond: // result: (Const32 [int64(int32(c^d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } d := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c ^ d)) return true } // match: (Xor32 (Const32 [d]) (Const32 [c])) // cond: // result: (Const32 [int64(int32(c^d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } c := v_1.AuxInt v.reset(OpConst32) v.AuxInt = int64(int32(c ^ d)) return true } // match: (Xor32 x x) // cond: // result: (Const32 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst32) v.AuxInt = 0 return true } // match: (Xor32 (Const32 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor32 x (Const32 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor32 x (Xor32 x y)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor32 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor32 x (Xor32 y x)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor32 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor32 (Xor32 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor32 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor32 (Xor32 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor32 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor32 (Xor32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Xor32 i (Xor32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpXor32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpXor32_10(v *Value) bool { b := v.Block // match: (Xor32 (Xor32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Xor32 i (Xor32 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor32 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpXor32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor32 x (Xor32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Xor32 i (Xor32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpXor32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor32 x (Xor32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Xor32 i (Xor32 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor32 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpXor32) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor32, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor32 (Const32 [c]) (Xor32 (Const32 [d]) x)) // cond: // result: (Xor32 (Const32 [int64(int32(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor32 (Const32 [c]) (Xor32 x (Const32 [d]))) // cond: // result: (Xor32 (Const32 [int64(int32(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor32 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor32 (Xor32 (Const32 [d]) x) (Const32 [c])) // cond: // result: (Xor32 (Const32 [int64(int32(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor32 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor32 (Xor32 x (Const32 [d])) (Const32 [c])) // cond: // result: (Xor32 (Const32 [int64(int32(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor32 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst32 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int64(int32(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpXor64_0(v *Value) bool { b := v.Block // match: (Xor64 (Const64 [c]) (Const64 [d])) // cond: // result: (Const64 [c^d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } d := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c ^ d return true } // match: (Xor64 (Const64 [d]) (Const64 [c])) // cond: // result: (Const64 [c^d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt v.reset(OpConst64) v.AuxInt = c ^ d return true } // match: (Xor64 x x) // cond: // result: (Const64 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst64) v.AuxInt = 0 return true } // match: (Xor64 (Const64 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor64 x (Const64 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor64 x (Xor64 x y)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor64 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor64 x (Xor64 y x)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor64 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor64 (Xor64 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor64 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor64 (Xor64 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor64 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor64 (Xor64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Xor64 i (Xor64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpXor64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpXor64_10(v *Value) bool { b := v.Block // match: (Xor64 (Xor64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Xor64 i (Xor64 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor64 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpXor64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor64 x (Xor64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Xor64 i (Xor64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpXor64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor64 x (Xor64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Xor64 i (Xor64 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor64 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpXor64) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor64, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor64 (Const64 [c]) (Xor64 (Const64 [d]) x)) // cond: // result: (Xor64 (Const64 [c^d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c ^ d v.AddArg(v0) v.AddArg(x) return true } // match: (Xor64 (Const64 [c]) (Xor64 x (Const64 [d]))) // cond: // result: (Xor64 (Const64 [c^d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor64 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c ^ d v.AddArg(v0) v.AddArg(x) return true } // match: (Xor64 (Xor64 (Const64 [d]) x) (Const64 [c])) // cond: // result: (Xor64 (Const64 [c^d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor64 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c ^ d v.AddArg(v0) v.AddArg(x) return true } // match: (Xor64 (Xor64 x (Const64 [d])) (Const64 [c])) // cond: // result: (Xor64 (Const64 [c^d]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst64 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = c ^ d v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpXor8_0(v *Value) bool { b := v.Block // match: (Xor8 (Const8 [c]) (Const8 [d])) // cond: // result: (Const8 [int64(int8(c^d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } d := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c ^ d)) return true } // match: (Xor8 (Const8 [d]) (Const8 [c])) // cond: // result: (Const8 [int64(int8(c^d))]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } c := v_1.AuxInt v.reset(OpConst8) v.AuxInt = int64(int8(c ^ d)) return true } // match: (Xor8 x x) // cond: // result: (Const8 [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpConst8) v.AuxInt = 0 return true } // match: (Xor8 (Const8 [0]) x) // cond: // result: x for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } if v_0.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor8 x (Const8 [0])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.AuxInt != 0 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Xor8 x (Xor8 x y)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor8 { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor8 x (Xor8 y x)) // cond: // result: y for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor8 { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor8 (Xor8 x y) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor8 { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor8 (Xor8 y x) x) // cond: // result: y for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor8 { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (Xor8 (Xor8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Xor8 i (Xor8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpXor8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpXor8_10(v *Value) bool { b := v.Block // match: (Xor8 (Xor8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Xor8 i (Xor8 z x)) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor8 { break } _ = v_0.Args[1] z := v_0.Args[0] i := v_0.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpXor8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor8 x (Xor8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Xor8 i (Xor8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpXor8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor8 x (Xor8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Xor8 i (Xor8 z x)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpXor8 { break } _ = v_1.Args[1] z := v_1.Args[0] i := v_1.Args[1] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpXor8) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpXor8, t) v0.AddArg(z) v0.AddArg(x) v.AddArg(v0) return true } // match: (Xor8 (Const8 [c]) (Xor8 (Const8 [d]) x)) // cond: // result: (Xor8 (Const8 [int64(int8(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } if v_1_0.Type != t { break } d := v_1_0.AuxInt v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor8 (Const8 [c]) (Xor8 x (Const8 [d]))) // cond: // result: (Xor8 (Const8 [int64(int8(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } t := v_0.Type c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpXor8 { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { break } if v_1_1.Type != t { break } d := v_1_1.AuxInt v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor8 (Xor8 (Const8 [d]) x) (Const8 [c])) // cond: // result: (Xor8 (Const8 [int64(int8(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor8 { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { break } t := v_0_0.Type d := v_0_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } // match: (Xor8 (Xor8 x (Const8 [d])) (Const8 [c])) // cond: // result: (Xor8 (Const8 [int64(int8(c^d))]) x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpXor8 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { break } t := v_0_1.Type d := v_0_1.AuxInt v_1 := v.Args[1] if v_1.Op != OpConst8 { break } if v_1.Type != t { break } c := v_1.AuxInt v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int64(int8(c ^ d)) v.AddArg(v0) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpZero_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (Zero (Load (OffPtr [c] (SP)) mem) mem) // cond: mem.Op == OpStaticCall && isSameSym(mem.Aux, "runtime.newobject") && c == config.ctxt.FixedFrameSize() + config.RegSize // result: mem for { mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpLoad { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpOffPtr { break } c := v_0_0.AuxInt v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpSP { break } if mem != v_0.Args[1] { break } if !(mem.Op == OpStaticCall && isSameSym(mem.Aux, "runtime.newobject") && c == config.ctxt.FixedFrameSize()+config.RegSize) { break } v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Zero {t1} [n] p1 store:(Store {t2} (OffPtr [o2] p2) _ mem)) // cond: isSamePtr(p1, p2) && store.Uses == 1 && n >= o2 + sizeof(t2) && clobber(store) // result: (Zero {t1} [n] p1 mem) for { n := v.AuxInt t1 := v.Aux _ = v.Args[1] p1 := v.Args[0] store := v.Args[1] if store.Op != OpStore { break } t2 := store.Aux mem := store.Args[2] store_0 := store.Args[0] if store_0.Op != OpOffPtr { break } o2 := store_0.AuxInt p2 := store_0.Args[0] if !(isSamePtr(p1, p2) && store.Uses == 1 && n >= o2+sizeof(t2) && clobber(store)) { break } v.reset(OpZero) v.AuxInt = n v.Aux = t1 v.AddArg(p1) v.AddArg(mem) return true } // match: (Zero {t} [n] dst1 move:(Move {t} [n] dst2 _ mem)) // cond: move.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move) // result: (Zero {t} [n] dst1 mem) for { n := v.AuxInt t := v.Aux _ = v.Args[1] dst1 := v.Args[0] move := v.Args[1] if move.Op != OpMove { break } if move.AuxInt != n { break } if move.Aux != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move)) { break } v.reset(OpZero) v.AuxInt = n v.Aux = t v.AddArg(dst1) v.AddArg(mem) return true } // match: (Zero {t} [n] dst1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem))) // cond: move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move) && clobber(vardef) // result: (Zero {t} [n] dst1 (VarDef {x} mem)) for { n := v.AuxInt t := v.Aux _ = v.Args[1] dst1 := v.Args[0] vardef := v.Args[1] if vardef.Op != OpVarDef { break } x := vardef.Aux move := vardef.Args[0] if move.Op != OpMove { break } if move.AuxInt != n { break } if move.Aux != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move) && clobber(vardef)) { break } v.reset(OpZero) v.AuxInt = n v.Aux = t v.AddArg(dst1) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = x v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpZeroExt16to32_0(v *Value) bool { // match: (ZeroExt16to32 (Const16 [c])) // cond: // result: (Const32 [int64(uint16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(uint16(c)) return true } // match: (ZeroExt16to32 (Trunc32to16 x:(Rsh32Ux64 _ (Const64 [s])))) // cond: s >= 16 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc32to16 { break } x := v_0.Args[0] if x.Op != OpRsh32Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 16) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpZeroExt16to64_0(v *Value) bool { // match: (ZeroExt16to64 (Const16 [c])) // cond: // result: (Const64 [int64(uint16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(uint16(c)) return true } // match: (ZeroExt16to64 (Trunc64to16 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 48 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc64to16 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 48) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpZeroExt32to64_0(v *Value) bool { // match: (ZeroExt32to64 (Const32 [c])) // cond: // result: (Const64 [int64(uint32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(uint32(c)) return true } // match: (ZeroExt32to64 (Trunc64to32 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 32 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc64to32 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 32) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to16_0(v *Value) bool { // match: (ZeroExt8to16 (Const8 [c])) // cond: // result: (Const16 [int64( uint8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst16) v.AuxInt = int64(uint8(c)) return true } // match: (ZeroExt8to16 (Trunc16to8 x:(Rsh16Ux64 _ (Const64 [s])))) // cond: s >= 8 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc16to8 { break } x := v_0.Args[0] if x.Op != OpRsh16Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 8) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to32_0(v *Value) bool { // match: (ZeroExt8to32 (Const8 [c])) // cond: // result: (Const32 [int64( uint8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst32) v.AuxInt = int64(uint8(c)) return true } // match: (ZeroExt8to32 (Trunc32to8 x:(Rsh32Ux64 _ (Const64 [s])))) // cond: s >= 24 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc32to8 { break } x := v_0.Args[0] if x.Op != OpRsh32Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 24) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to64_0(v *Value) bool { // match: (ZeroExt8to64 (Const8 [c])) // cond: // result: (Const64 [int64( uint8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := v_0.AuxInt v.reset(OpConst64) v.AuxInt = int64(uint8(c)) return true } // match: (ZeroExt8to64 (Trunc64to8 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 56 // result: x for { v_0 := v.Args[0] if v_0.Op != OpTrunc64to8 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := x_1.AuxInt if !(s >= 56) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteBlockgeneric(b *Block) bool { config := b.Func.Config typ := &config.Types _ = typ v := b.Control _ = v switch b.Kind { case BlockIf: // match: (If (Not cond) yes no) // cond: // result: (If cond no yes) for v.Op == OpNot { cond := v.Args[0] b.Kind = BlockIf b.SetControl(cond) b.Aux = nil b.swapSuccessors() return true } // match: (If (ConstBool [c]) yes no) // cond: c == 1 // result: (First nil yes no) for v.Op == OpConstBool { c := v.AuxInt if !(c == 1) { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (If (ConstBool [c]) yes no) // cond: c == 0 // result: (First nil no yes) for v.Op == OpConstBool { c := v.AuxInt if !(c == 0) { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } } return false } -- diff -- @@ -98,17 +98,17 @@ case OpDiv8u: return rewriteValuegeneric_OpDiv8u_0(v) case OpEq16: - return rewriteValuegeneric_OpEq16_0(v) || rewriteValuegeneric_OpEq16_10(v) || rewriteValuegeneric_OpEq16_20(v) || rewriteValuegeneric_OpEq16_30(v) || rewriteValuegeneric_OpEq16_40(v) + return rewriteValuegeneric_OpEq16_0(v) || rewriteValuegeneric_OpEq16_10(v) || rewriteValuegeneric_OpEq16_20(v) || rewriteValuegeneric_OpEq16_30(v) || rewriteValuegeneric_OpEq16_40(v) || rewriteValuegeneric_OpEq16_50(v) case OpEq32: - return rewriteValuegeneric_OpEq32_0(v) || rewriteValuegeneric_OpEq32_10(v) || rewriteValuegeneric_OpEq32_20(v) || rewriteValuegeneric_OpEq32_30(v) || rewriteValuegeneric_OpEq32_40(v) || rewriteValuegeneric_OpEq32_50(v) || rewriteValuegeneric_OpEq32_60(v) + return rewriteValuegeneric_OpEq32_0(v) || rewriteValuegeneric_OpEq32_10(v) || rewriteValuegeneric_OpEq32_20(v) || rewriteValuegeneric_OpEq32_30(v) || rewriteValuegeneric_OpEq32_40(v) || rewriteValuegeneric_OpEq32_50(v) || rewriteValuegeneric_OpEq32_60(v) || rewriteValuegeneric_OpEq32_70(v) || rewriteValuegeneric_OpEq32_80(v) || rewriteValuegeneric_OpEq32_90(v) case OpEq32F: return rewriteValuegeneric_OpEq32F_0(v) case OpEq64: - return rewriteValuegeneric_OpEq64_0(v) || rewriteValuegeneric_OpEq64_10(v) || rewriteValuegeneric_OpEq64_20(v) || rewriteValuegeneric_OpEq64_30(v) + return rewriteValuegeneric_OpEq64_0(v) || rewriteValuegeneric_OpEq64_10(v) || rewriteValuegeneric_OpEq64_20(v) || rewriteValuegeneric_OpEq64_30(v) || rewriteValuegeneric_OpEq64_40(v) || rewriteValuegeneric_OpEq64_50(v) || rewriteValuegeneric_OpEq64_60(v) case OpEq64F: return rewriteValuegeneric_OpEq64F_0(v) case OpEq8: - return rewriteValuegeneric_OpEq8_0(v) || rewriteValuegeneric_OpEq8_10(v) || rewriteValuegeneric_OpEq8_20(v) + return rewriteValuegeneric_OpEq8_0(v) || rewriteValuegeneric_OpEq8_10(v) || rewriteValuegeneric_OpEq8_20(v) || rewriteValuegeneric_OpEq8_30(v) case OpEqB: return rewriteValuegeneric_OpEqB_0(v) case OpEqInter: @@ -9041,78 +9041,159 @@ v.AddArg(v3) return true } - // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))))) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) - // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) + // match: (Eq16 (Mod16 x (Const16 [c])) (Const16 [0])) + // cond: x.Op != OpConst16 && sdivisibleOK(16,c) && !hasSmallRotate(config) + // result: (Eq32 (Mod32 (SignExt16to32 x) (Const32 [c])) (Const32 [0])) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpMul16 { + v_0 := v.Args[0] + if v_0.Op != OpMod16 { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpConst16 { + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst16 { break } - c := v_1_0.AuxInt - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpTrunc64to16 { + c := v_0_1.AuxInt + v_1 := v.Args[1] + if v_1.Op != OpConst16 { break } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh64Ux64 { - break - } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpMul64 { + if v_1.AuxInt != 0 { break } - _ = mul.Args[1] - mul_0 := mul.Args[0] - if mul_0.Op != OpConst64 { + if !(x.Op != OpConst16 && sdivisibleOK(16, c) && !hasSmallRotate(config)) { break } - m := mul_0.AuxInt - mul_1 := mul.Args[1] - if mul_1.Op != OpZeroExt16to64 { - break - } - if x != mul_1.Args[0] { - break - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - break - } - s := v_1_1_0_1.AuxInt - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { - break - } - v.reset(OpLeq16U) - v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) - v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) - v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v2.AuxInt = int64(int16(udivisible(16, c).m)) - v1.AddArg(v2) + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) + v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) - v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v3.AuxInt = int64(16 - udivisible(16, c).k) - v0.AddArg(v3) + v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v2.AuxInt = c + v0.AddArg(v2) v.AddArg(v0) - v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v4.AuxInt = int64(int16(udivisible(16, c).max)) - v.AddArg(v4) + v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v3.AuxInt = 0 + v.AddArg(v3) return true } return false } func rewriteValuegeneric_OpEq16_10(v *Value) bool { b := v.Block + config := b.Func.Config typ := &b.Func.Config.Types + // match: (Eq16 (Const16 [0]) (Mod16 x (Const16 [c]))) + // cond: x.Op != OpConst16 && sdivisibleOK(16,c) && !hasSmallRotate(config) + // result: (Eq32 (Mod32 (SignExt16to32 x) (Const32 [c])) (Const32 [0])) + for { + _ = v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpConst16 { + break + } + if v_0.AuxInt != 0 { + break + } + v_1 := v.Args[1] + if v_1.Op != OpMod16 { + break + } + _ = v_1.Args[1] + x := v_1.Args[0] + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst16 { + break + } + c := v_1_1.AuxInt + if !(x.Op != OpConst16 && sdivisibleOK(16, c) && !hasSmallRotate(config)) { + break + } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) + v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v2.AuxInt = c + v0.AddArg(v2) + v.AddArg(v0) + v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v3.AuxInt = 0 + v.AddArg(v3) + return true + } + // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpTrunc64to16 { + break + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64Ux64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpZeroExt16to64 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v2.AuxInt = int64(int16(udivisible(16, c).m)) + v1.AddArg(v2) + v1.AddArg(x) + v0.AddArg(v1) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(16 - udivisible(16, c).k) + v0.AddArg(v3) + v.AddArg(v0) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(udivisible(16, c).max)) + v.AddArg(v4) + return true + } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (ZeroExt16to64 x) (Const64 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -9645,6 +9726,11 @@ v.AddArg(v4) return true } + return false +} +func rewriteValuegeneric_OpEq16_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (ZeroExt16to32 x) (Const32 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -9779,11 +9865,6 @@ v.AddArg(v4) return true } - return false -} -func rewriteValuegeneric_OpEq16_20(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (ZeroExt16to32 x) (Const32 [m])) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -10352,6 +10433,11 @@ v.AddArg(v4) return true } + return false +} +func rewriteValuegeneric_OpEq16_30(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) (Const32 [m])) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -10509,11 +10595,6 @@ v.AddArg(v4) return true } - return false -} -func rewriteValuegeneric_OpEq16_30(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) (Const32 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -11202,6 +11283,11 @@ v.AddArg(v4) return true } + return false +} +func rewriteValuegeneric_OpEq16_40(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (ZeroExt16to32 x) (Const32 [m]))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -11382,11 +11468,6 @@ v.AddArg(v4) return true } - return false -} -func rewriteValuegeneric_OpEq16_40(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (ZeroExt16to32 x) (Const32 [m]))) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -11477,6 +11558,743 @@ v.AddArg(v4) return true } + // match: (Eq16 x (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub16 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt16to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + v_1_1_1_0 := v_1_1_1.Args[0] + if v_1_1_1_0.Op != OpSignExt16to32 { + break + } + if x != v_1_1_1_0.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq16 x (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (SignExt16to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub16 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt16to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + v_1_1_1_0 := v_1_1_1.Args[0] + if v_1_1_1_0.Op != OpSignExt16to32 { + break + } + if x != v_1_1_1_0.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq16 x (Mul16 (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) (Const16 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub16 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt16to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpSignExt16to32 { + break + } + if x != v_1_0_1_0.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst16 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq16 x (Mul16 (Sub16 (Rsh32x64 mul:(Mul32 (SignExt16to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) (Const16 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub16 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt16to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpSignExt16to32 { + break + } + if x != v_1_0_1_0.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst16 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq16 (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul16 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst16 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub16 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt16to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + v_0_1_1_0 := v_0_1_1.Args[0] + if v_0_1_1_0.Op != OpSignExt16to32 { + break + } + if x != v_0_1_1_0.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq16 (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (SignExt16to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul16 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst16 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub16 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt16to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + v_0_1_1_0 := v_0_1_1.Args[0] + if v_0_1_1_0.Op != OpSignExt16to32 { + break + } + if x != v_0_1_1_0.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq16 (Mul16 (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) (Const16 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul16 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub16 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt16to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + v_0_0_1_0 := v_0_0_1.Args[0] + if v_0_0_1_0.Op != OpSignExt16to32 { + break + } + if x != v_0_0_1_0.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst16 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq16_50(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq16 (Mul16 (Sub16 (Rsh32x64 mul:(Mul32 (SignExt16to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) (Const16 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul16 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub16 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt16to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + v_0_0_1_0 := v_0_0_1.Args[0] + if v_0_0_1_0.Op != OpSignExt16to32 { + break + } + if x != v_0_0_1_0.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst16 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } // match: (Eq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [int64(1< [0])) @@ -15585,6 +16403,2885 @@ v.AddArg(v4) return true } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt32to64 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + v_1_1_1_0 := v_1_1_1.Args[0] + if v_1_1_1_0.Op != OpSignExt32to64 { + break + } + if x != v_1_1_1_0.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (SignExt32to64 x) (Const64 [m])) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt32to64 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + v_1_1_1_0 := v_1_1_1.Args[0] + if v_1_1_1_0.Op != OpSignExt32to64 { + break + } + if x != v_1_1_1_0.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt32to64 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpSignExt32to64 { + break + } + if x != v_1_0_1_0.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh64x64 mul:(Mul64 (SignExt32to64 x) (Const64 [m])) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt32to64 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpSignExt32to64 { + break + } + if x != v_1_0_1_0.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt32to64 { + break + } + if x != mul_1.Args[0] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + v_0_1_1_0 := v_0_1_1.Args[0] + if v_0_1_1_0.Op != OpSignExt32to64 { + break + } + if x != v_0_1_1_0.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq32_60(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (SignExt32to64 x) (Const64 [m])) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt32to64 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + v_0_1_1_0 := v_0_1_1.Args[0] + if v_0_1_1_0.Op != OpSignExt32to64 { + break + } + if x != v_0_1_1_0.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt32to64 { + break + } + if x != mul_1.Args[0] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + v_0_0_1_0 := v_0_0_1.Args[0] + if v_0_0_1_0.Op != OpSignExt32to64 { + break + } + if x != v_0_0_1_0.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh64x64 mul:(Mul64 (SignExt32to64 x) (Const64 [m])) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt32to64 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + v_0_0_1_0 := v_0_0_1.Args[0] + if v_0_0_1_0.Op != OpSignExt32to64 { + break + } + if x != v_0_0_1_0.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 x (Const32 [m])) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 mul:(Hmul32 x (Const32 [m])) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 x (Const32 [m])) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq32_70(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 mul:(Hmul32 x (Const32 [m])) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd32 { + break + } + _ = v_1_1_0_0.Args[1] + mul := v_1_1_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_1_1_0_0.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 x (Const32 [m])) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd32 { + break + } + _ = v_1_1_0_0.Args[1] + mul := v_1_1_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + if x != v_1_1_0_0.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 (Const32 [m]) x)) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd32 { + break + } + _ = v_1_1_0_0.Args[1] + if x != v_1_1_0_0.Args[0] { + break + } + mul := v_1_1_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 x (Const32 [m]))) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd32 { + break + } + _ = v_1_1_0_0.Args[1] + if x != v_1_1_0_0.Args[0] { + break + } + mul := v_1_1_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd32 { + break + } + _ = v_1_0_0_0.Args[1] + mul := v_1_0_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_1_0_0_0.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 x (Const32 [m])) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd32 { + break + } + _ = v_1_0_0_0.Args[1] + mul := v_1_0_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + if x != v_1_0_0_0.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 (Const32 [m]) x)) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd32 { + break + } + _ = v_1_0_0_0.Args[1] + if x != v_1_0_0_0.Args[0] { + break + } + mul := v_1_0_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 x (Const32 [m]))) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd32 { + break + } + _ = v_1_0_0_0.Args[1] + if x != v_1_0_0_0.Args[0] { + break + } + mul := v_1_0_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd32 { + break + } + _ = v_0_1_0_0.Args[1] + mul := v_0_1_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_0_1_0_0.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq32_80(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 x (Const32 [m])) x) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd32 { + break + } + _ = v_0_1_0_0.Args[1] + mul := v_0_1_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + if x != v_0_1_0_0.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 (Const32 [m]) x)) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd32 { + break + } + _ = v_0_1_0_0.Args[1] + if x != v_0_1_0_0.Args[0] { + break + } + mul := v_0_1_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 x (Const32 [m]))) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd32 { + break + } + _ = v_0_1_0_0.Args[1] + if x != v_0_1_0_0.Args[0] { + break + } + mul := v_0_1_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd32 { + break + } + _ = v_0_0_0_0.Args[1] + mul := v_0_0_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_0_0_0_0.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 x (Const32 [m])) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd32 { + break + } + _ = v_0_0_0_0.Args[1] + mul := v_0_0_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + if x != v_0_0_0_0.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 (Const32 [m]) x)) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd32 { + break + } + _ = v_0_0_0_0.Args[1] + if x != v_0_0_0_0.Args[0] { + break + } + mul := v_0_0_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 x (Const32 [m]))) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd32 { + break + } + _ = v_0_0_0_0.Args[1] + if x != v_0_0_0_0.Args[0] { + break + } + mul := v_0_0_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } // match: (Eq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [int64(1< [0])) @@ -15869,6 +19566,11 @@ v.AddArg(v2) return true } + return false +} +func rewriteValuegeneric_OpEq32_90(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (Eq32 (Lsh32x64 (Rsh32x64 (Add32 (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [int64(1< [0])) @@ -15989,9 +19691,6 @@ v.AddArg(y) return true } - return false -} -func rewriteValuegeneric_OpEq32_60(v *Value) bool { // match: (Eq32 (Const32 [0]) s:(Sub32 x y)) // cond: s.Uses == 1 // result: (Eq32 x y) @@ -17819,6 +21518,2148 @@ v.AddArg(v4) return true } + // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub64 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 x (Const64 [m])) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub64 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 mul:(Hmul64 x (Const64 [m])) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst64 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub64 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 x (Const64 [m])) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst64 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub64 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub64 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 mul:(Hmul64 x (Const64 [m])) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub64 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub64 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd64 { + break + } + _ = v_1_1_0_0.Args[1] + mul := v_1_1_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_1_1_0_0.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq64_40(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 x (Const64 [m])) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub64 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd64 { + break + } + _ = v_1_1_0_0.Args[1] + mul := v_1_1_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + if x != v_1_1_0_0.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 (Const64 [m]) x)) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub64 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd64 { + break + } + _ = v_1_1_0_0.Args[1] + if x != v_1_1_0_0.Args[0] { + break + } + mul := v_1_1_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 x (Const64 [m]))) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub64 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd64 { + break + } + _ = v_1_1_0_0.Args[1] + if x != v_1_1_0_0.Args[0] { + break + } + mul := v_1_1_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd64 { + break + } + _ = v_1_0_0_0.Args[1] + mul := v_1_0_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_1_0_0_0.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 x (Const64 [m])) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd64 { + break + } + _ = v_1_0_0_0.Args[1] + mul := v_1_0_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + if x != v_1_0_0_0.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 (Const64 [m]) x)) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd64 { + break + } + _ = v_1_0_0_0.Args[1] + if x != v_1_0_0_0.Args[0] { + break + } + mul := v_1_0_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 x (Const64 [m]))) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd64 { + break + } + _ = v_1_0_0_0.Args[1] + if x != v_1_0_0_0.Args[0] { + break + } + mul := v_1_0_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst64 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub64 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd64 { + break + } + _ = v_0_1_0_0.Args[1] + mul := v_0_1_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_0_1_0_0.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 x (Const64 [m])) x) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst64 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub64 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd64 { + break + } + _ = v_0_1_0_0.Args[1] + mul := v_0_1_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + if x != v_0_1_0_0.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 (Const64 [m]) x)) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst64 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub64 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd64 { + break + } + _ = v_0_1_0_0.Args[1] + if x != v_0_1_0_0.Args[0] { + break + } + mul := v_0_1_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq64_50(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 x (Const64 [m]))) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst64 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub64 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd64 { + break + } + _ = v_0_1_0_0.Args[1] + if x != v_0_1_0_0.Args[0] { + break + } + mul := v_0_1_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub64 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd64 { + break + } + _ = v_0_0_0_0.Args[1] + mul := v_0_0_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_0_0_0_0.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 x (Const64 [m])) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub64 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd64 { + break + } + _ = v_0_0_0_0.Args[1] + mul := v_0_0_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + if x != v_0_0_0_0.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 (Const64 [m]) x)) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub64 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd64 { + break + } + _ = v_0_0_0_0.Args[1] + if x != v_0_0_0_0.Args[0] { + break + } + mul := v_0_0_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 x (Const64 [m]))) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub64 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd64 { + break + } + _ = v_0_0_0_0.Args[1] + if x != v_0_0_0_0.Args[0] { + break + } + mul := v_0_0_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } // match: (Eq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [int64(1< [0])) @@ -18223,6 +24064,9 @@ v.AddArg(y) return true } + return false +} +func rewriteValuegeneric_OpEq64_60(v *Value) bool { // match: (Eq64 (Const64 [0]) s:(Sub64 x y)) // cond: s.Uses == 1 // result: (Eq64 x y) @@ -18552,78 +24396,159 @@ v.AddArg(v3) return true } - // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))))) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) - // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) + // match: (Eq8 (Mod8 x (Const8 [c])) (Const8 [0])) + // cond: x.Op != OpConst8 && sdivisibleOK(8,c) && !hasSmallRotate(config) + // result: (Eq32 (Mod32 (SignExt8to32 x) (Const32 [c])) (Const32 [0])) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpMul8 { + v_0 := v.Args[0] + if v_0.Op != OpMod8 { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpConst8 { + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst8 { break } - c := v_1_0.AuxInt - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpTrunc32to8 { + c := v_0_1.AuxInt + v_1 := v.Args[1] + if v_1.Op != OpConst8 { break } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh32Ux64 { - break - } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpMul32 { + if v_1.AuxInt != 0 { break } - _ = mul.Args[1] - mul_0 := mul.Args[0] - if mul_0.Op != OpConst32 { + if !(x.Op != OpConst8 && sdivisibleOK(8, c) && !hasSmallRotate(config)) { break } - m := mul_0.AuxInt - mul_1 := mul.Args[1] - if mul_1.Op != OpZeroExt8to32 { - break - } - if x != mul_1.Args[0] { - break - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - break - } - s := v_1_1_0_1.AuxInt - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { - break - } - v.reset(OpLeq8U) - v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) - v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) - v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) - v2.AuxInt = int64(int8(udivisible(8, c).m)) - v1.AddArg(v2) + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) + v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) - v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) - v3.AuxInt = int64(8 - udivisible(8, c).k) - v0.AddArg(v3) + v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v2.AuxInt = c + v0.AddArg(v2) v.AddArg(v0) - v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) - v4.AuxInt = int64(int8(udivisible(8, c).max)) - v.AddArg(v4) + v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v3.AuxInt = 0 + v.AddArg(v3) return true } return false } func rewriteValuegeneric_OpEq8_10(v *Value) bool { b := v.Block + config := b.Func.Config typ := &b.Func.Config.Types + // match: (Eq8 (Const8 [0]) (Mod8 x (Const8 [c]))) + // cond: x.Op != OpConst8 && sdivisibleOK(8,c) && !hasSmallRotate(config) + // result: (Eq32 (Mod32 (SignExt8to32 x) (Const32 [c])) (Const32 [0])) + for { + _ = v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpConst8 { + break + } + if v_0.AuxInt != 0 { + break + } + v_1 := v.Args[1] + if v_1.Op != OpMod8 { + break + } + _ = v_1.Args[1] + x := v_1.Args[0] + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst8 { + break + } + c := v_1_1.AuxInt + if !(x.Op != OpConst8 && sdivisibleOK(8, c) && !hasSmallRotate(config)) { + break + } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) + v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v2.AuxInt = c + v0.AddArg(v2) + v.AddArg(v0) + v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v3.AuxInt = 0 + v.AddArg(v3) + return true + } + // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpTrunc32to8 { + break + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32Ux64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpZeroExt8to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v2.AuxInt = int64(int8(udivisible(8, c).m)) + v1.AddArg(v2) + v1.AddArg(x) + v0.AddArg(v1) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(8 - udivisible(8, c).k) + v0.AddArg(v3) + v.AddArg(v0) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(udivisible(8, c).max)) + v.AddArg(v4) + return true + } // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (ZeroExt8to32 x) (Const32 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) @@ -19089,6 +25014,743 @@ v.AddArg(v4) return true } + // match: (Eq8 x (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub8 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt8to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + v_1_1_1_0 := v_1_1_1.Args[0] + if v_1_1_1_0.Op != OpSignExt8to32 { + break + } + if x != v_1_1_1_0.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq8_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq8 x (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (SignExt8to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub8 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt8to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + v_1_1_1_0 := v_1_1_1.Args[0] + if v_1_1_1_0.Op != OpSignExt8to32 { + break + } + if x != v_1_1_1_0.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq8 x (Mul8 (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) (Const8 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub8 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt8to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpSignExt8to32 { + break + } + if x != v_1_0_1_0.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst8 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq8 x (Mul8 (Sub8 (Rsh32x64 mul:(Mul32 (SignExt8to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) (Const8 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub8 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt8to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpSignExt8to32 { + break + } + if x != v_1_0_1_0.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst8 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq8 (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul8 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst8 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub8 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt8to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + v_0_1_1_0 := v_0_1_1.Args[0] + if v_0_1_1_0.Op != OpSignExt8to32 { + break + } + if x != v_0_1_1_0.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq8 (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (SignExt8to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul8 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst8 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub8 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt8to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + v_0_1_1_0 := v_0_1_1.Args[0] + if v_0_1_1_0.Op != OpSignExt8to32 { + break + } + if x != v_0_1_1_0.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq8 (Mul8 (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) (Const8 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul8 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub8 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt8to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + v_0_0_1_0 := v_0_0_1.Args[0] + if v_0_0_1_0.Op != OpSignExt8to32 { + break + } + if x != v_0_0_1_0.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst8 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq8 (Mul8 (Sub8 (Rsh32x64 mul:(Mul32 (SignExt8to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) (Const8 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul8 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub8 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt8to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + v_0_0_1_0 := v_0_0_1.Args[0] + if v_0_0_1_0.Op != OpSignExt8to32 { + break + } + if x != v_0_0_1_0.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst8 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } // match: (Eq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [int64(1< [0])) @@ -19375,7 +26037,7 @@ } return false } -func rewriteValuegeneric_OpEq8_20(v *Value) bool { +func rewriteValuegeneric_OpEq8_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq8 (Lsh8x64 (Rsh8x64 (Add8 (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k])) n) @@ -25308,7 +31970,7 @@ return true } // match: (Mod8u x (Const8 [c])) - // cond: x.Op != OpConst8 && c > 0 && umagicOK(8,c) + // cond: x.Op != OpConst8 && c > 0 && umagicOK(8, c) // result: (Sub8 x (Mul8 (Div8u x (Const8 [c])) (Const8 [c]))) for { t := v.Type -- diff -- # indent-heuristic: true @@ -98,17 +98,17 @@ case OpDiv8u: return rewriteValuegeneric_OpDiv8u_0(v) case OpEq16: - return rewriteValuegeneric_OpEq16_0(v) || rewriteValuegeneric_OpEq16_10(v) || rewriteValuegeneric_OpEq16_20(v) || rewriteValuegeneric_OpEq16_30(v) || rewriteValuegeneric_OpEq16_40(v) + return rewriteValuegeneric_OpEq16_0(v) || rewriteValuegeneric_OpEq16_10(v) || rewriteValuegeneric_OpEq16_20(v) || rewriteValuegeneric_OpEq16_30(v) || rewriteValuegeneric_OpEq16_40(v) || rewriteValuegeneric_OpEq16_50(v) case OpEq32: - return rewriteValuegeneric_OpEq32_0(v) || rewriteValuegeneric_OpEq32_10(v) || rewriteValuegeneric_OpEq32_20(v) || rewriteValuegeneric_OpEq32_30(v) || rewriteValuegeneric_OpEq32_40(v) || rewriteValuegeneric_OpEq32_50(v) || rewriteValuegeneric_OpEq32_60(v) + return rewriteValuegeneric_OpEq32_0(v) || rewriteValuegeneric_OpEq32_10(v) || rewriteValuegeneric_OpEq32_20(v) || rewriteValuegeneric_OpEq32_30(v) || rewriteValuegeneric_OpEq32_40(v) || rewriteValuegeneric_OpEq32_50(v) || rewriteValuegeneric_OpEq32_60(v) || rewriteValuegeneric_OpEq32_70(v) || rewriteValuegeneric_OpEq32_80(v) || rewriteValuegeneric_OpEq32_90(v) case OpEq32F: return rewriteValuegeneric_OpEq32F_0(v) case OpEq64: - return rewriteValuegeneric_OpEq64_0(v) || rewriteValuegeneric_OpEq64_10(v) || rewriteValuegeneric_OpEq64_20(v) || rewriteValuegeneric_OpEq64_30(v) + return rewriteValuegeneric_OpEq64_0(v) || rewriteValuegeneric_OpEq64_10(v) || rewriteValuegeneric_OpEq64_20(v) || rewriteValuegeneric_OpEq64_30(v) || rewriteValuegeneric_OpEq64_40(v) || rewriteValuegeneric_OpEq64_50(v) || rewriteValuegeneric_OpEq64_60(v) case OpEq64F: return rewriteValuegeneric_OpEq64F_0(v) case OpEq8: - return rewriteValuegeneric_OpEq8_0(v) || rewriteValuegeneric_OpEq8_10(v) || rewriteValuegeneric_OpEq8_20(v) + return rewriteValuegeneric_OpEq8_0(v) || rewriteValuegeneric_OpEq8_10(v) || rewriteValuegeneric_OpEq8_20(v) || rewriteValuegeneric_OpEq8_30(v) case OpEqB: return rewriteValuegeneric_OpEqB_0(v) case OpEqInter: @@ -9041,78 +9041,159 @@ v.AddArg(v3) return true } - // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))))) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) - // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) + // match: (Eq16 (Mod16 x (Const16 [c])) (Const16 [0])) + // cond: x.Op != OpConst16 && sdivisibleOK(16,c) && !hasSmallRotate(config) + // result: (Eq32 (Mod32 (SignExt16to32 x) (Const32 [c])) (Const32 [0])) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpMul16 { + v_0 := v.Args[0] + if v_0.Op != OpMod16 { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpConst16 { + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst16 { break } - c := v_1_0.AuxInt - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpTrunc64to16 { + c := v_0_1.AuxInt + v_1 := v.Args[1] + if v_1.Op != OpConst16 { break } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh64Ux64 { - break - } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpMul64 { + if v_1.AuxInt != 0 { break } - _ = mul.Args[1] - mul_0 := mul.Args[0] - if mul_0.Op != OpConst64 { + if !(x.Op != OpConst16 && sdivisibleOK(16, c) && !hasSmallRotate(config)) { break } - m := mul_0.AuxInt - mul_1 := mul.Args[1] - if mul_1.Op != OpZeroExt16to64 { - break - } - if x != mul_1.Args[0] { - break - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - break - } - s := v_1_1_0_1.AuxInt - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { - break - } - v.reset(OpLeq16U) - v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) - v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) - v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v2.AuxInt = int64(int16(udivisible(16, c).m)) - v1.AddArg(v2) + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) + v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) - v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v3.AuxInt = int64(16 - udivisible(16, c).k) - v0.AddArg(v3) + v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v2.AuxInt = c + v0.AddArg(v2) v.AddArg(v0) - v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) - v4.AuxInt = int64(int16(udivisible(16, c).max)) - v.AddArg(v4) + v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v3.AuxInt = 0 + v.AddArg(v3) return true } return false } func rewriteValuegeneric_OpEq16_10(v *Value) bool { b := v.Block + config := b.Func.Config typ := &b.Func.Config.Types + // match: (Eq16 (Const16 [0]) (Mod16 x (Const16 [c]))) + // cond: x.Op != OpConst16 && sdivisibleOK(16,c) && !hasSmallRotate(config) + // result: (Eq32 (Mod32 (SignExt16to32 x) (Const32 [c])) (Const32 [0])) + for { + _ = v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpConst16 { + break + } + if v_0.AuxInt != 0 { + break + } + v_1 := v.Args[1] + if v_1.Op != OpMod16 { + break + } + _ = v_1.Args[1] + x := v_1.Args[0] + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst16 { + break + } + c := v_1_1.AuxInt + if !(x.Op != OpConst16 && sdivisibleOK(16, c) && !hasSmallRotate(config)) { + break + } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) + v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v2.AuxInt = c + v0.AddArg(v2) + v.AddArg(v0) + v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v3.AuxInt = 0 + v.AddArg(v3) + return true + } + // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpTrunc64to16 { + break + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64Ux64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpZeroExt16to64 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16, c).m) && s == 16+umagic(16, c).s && x.Op != OpConst16 && udivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v2.AuxInt = int64(int16(udivisible(16, c).m)) + v1.AddArg(v2) + v1.AddArg(x) + v0.AddArg(v1) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(16 - udivisible(16, c).k) + v0.AddArg(v3) + v.AddArg(v0) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(udivisible(16, c).max)) + v.AddArg(v4) + return true + } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (ZeroExt16to64 x) (Const64 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic(16,c).m) && s == 16+umagic(16,c).s && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -9645,6 +9726,11 @@ v.AddArg(v4) return true } + return false +} +func rewriteValuegeneric_OpEq16_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (ZeroExt16to32 x) (Const32 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -9779,11 +9865,6 @@ v.AddArg(v4) return true } - return false -} -func rewriteValuegeneric_OpEq16_20(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (ZeroExt16to32 x) (Const32 [m])) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+umagic(16,c).m/2) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -10352,6 +10433,11 @@ v.AddArg(v4) return true } + return false +} +func rewriteValuegeneric_OpEq16_30(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (Eq16 x (Mul16 (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) (Const32 [m])) (Const64 [s]))) (Const16 [c]))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -10509,11 +10595,6 @@ v.AddArg(v4) return true } - return false -} -func rewriteValuegeneric_OpEq16_30(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1])) (Const32 [m])) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<15+(umagic(16,c).m+1)/2) && s == 16+umagic(16,c).s-2 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -11202,6 +11283,11 @@ v.AddArg(v4) return true } + return false +} +func rewriteValuegeneric_OpEq16_40(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (Eq16 (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (ZeroExt16to32 x) (Const32 [m]))) (Const64 [s])))) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -11382,11 +11468,6 @@ v.AddArg(v4) return true } - return false -} -func rewriteValuegeneric_OpEq16_40(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Eq16 (Mul16 (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (ZeroExt16to32 x) (Const32 [m]))) (Const64 [s]))) (Const16 [c])) x) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic(16,c).m) && s == 16+umagic(16,c).s-1 && x.Op != OpConst16 && udivisibleOK(16,c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int64(int16(udivisible(16,c).m))]) x) (Const16 [int64(16-udivisible(16,c).k)]) ) (Const16 [int64(int16(udivisible(16,c).max))]) ) @@ -11477,6 +11558,743 @@ v.AddArg(v4) return true } + // match: (Eq16 x (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub16 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt16to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + v_1_1_1_0 := v_1_1_1.Args[0] + if v_1_1_1_0.Op != OpSignExt16to32 { + break + } + if x != v_1_1_1_0.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq16 x (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (SignExt16to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub16 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt16to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + v_1_1_1_0 := v_1_1_1.Args[0] + if v_1_1_1_0.Op != OpSignExt16to32 { + break + } + if x != v_1_1_1_0.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq16 x (Mul16 (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) (Const16 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub16 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt16to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpSignExt16to32 { + break + } + if x != v_1_0_1_0.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst16 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq16 x (Mul16 (Sub16 (Rsh32x64 mul:(Mul32 (SignExt16to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) (Const16 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub16 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt16to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpSignExt16to32 { + break + } + if x != v_1_0_1_0.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst16 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq16 (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul16 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst16 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub16 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt16to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + v_0_1_1_0 := v_0_1_1.Args[0] + if v_0_1_1_0.Op != OpSignExt16to32 { + break + } + if x != v_0_1_1_0.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq16 (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (SignExt16to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul16 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst16 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub16 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt16to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + v_0_1_1_0 := v_0_1_1.Args[0] + if v_0_1_1_0.Op != OpSignExt16to32 { + break + } + if x != v_0_1_1_0.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq16 (Mul16 (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) (Const16 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul16 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub16 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt16to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + v_0_0_1_0 := v_0_0_1.Args[0] + if v_0_0_1_0.Op != OpSignExt16to32 { + break + } + if x != v_0_0_1_0.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst16 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq16_50(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq16 (Mul16 (Sub16 (Rsh32x64 mul:(Mul32 (SignExt16to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) (Const16 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16,c).m) && s == 16+smagic(16,c).s && x.Op != OpConst16 && sdivisibleOK(16,c) + // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int64(int16(sdivisible(16,c).m))]) x) (Const16 [int64(int16(sdivisible(16,c).a))]) ) (Const16 [int64(16-sdivisible(16,c).k)]) ) (Const16 [int64(int16(sdivisible(16,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul16 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub16 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt16to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + v_0_0_1_0 := v_0_0_1.Args[0] + if v_0_0_1_0.Op != OpSignExt16to32 { + break + } + if x != v_0_0_1_0.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst16 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(16, c).m) && s == 16+smagic(16, c).s && x.Op != OpConst16 && sdivisibleOK(16, c)) { + break + } + v.reset(OpLeq16U) + v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) + v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) + v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) + v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v3.AuxInt = int64(int16(sdivisible(16, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v4.AuxInt = int64(int16(sdivisible(16, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v5.AuxInt = int64(16 - sdivisible(16, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) + v6.AuxInt = int64(int16(sdivisible(16, c).max)) + v.AddArg(v6) + return true + } // match: (Eq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [int64(1< [0])) @@ -15585,6 +16403,2885 @@ v.AddArg(v4) return true } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt32to64 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + v_1_1_1_0 := v_1_1_1.Args[0] + if v_1_1_1_0.Op != OpSignExt32to64 { + break + } + if x != v_1_1_1_0.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (SignExt32to64 x) (Const64 [m])) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt32to64 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + v_1_1_1_0 := v_1_1_1.Args[0] + if v_1_1_1_0.Op != OpSignExt32to64 { + break + } + if x != v_1_1_1_0.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt32to64 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpSignExt32to64 { + break + } + if x != v_1_0_1_0.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh64x64 mul:(Mul64 (SignExt32to64 x) (Const64 [m])) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt32to64 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpSignExt32to64 { + break + } + if x != v_1_0_1_0.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt32to64 { + break + } + if x != mul_1.Args[0] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + v_0_1_1_0 := v_0_1_1.Args[0] + if v_0_1_1_0.Op != OpSignExt32to64 { + break + } + if x != v_0_1_1_0.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq32_60(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (SignExt32to64 x) (Const64 [m])) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt32to64 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + v_0_1_1_0 := v_0_1_1.Args[0] + if v_0_1_1_0.Op != OpSignExt32to64 { + break + } + if x != v_0_1_1_0.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt32to64 { + break + } + if x != mul_1.Args[0] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + v_0_0_1_0 := v_0_0_1.Args[0] + if v_0_0_1_0.Op != OpSignExt32to64 { + break + } + if x != v_0_0_1_0.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh64x64 mul:(Mul64 (SignExt32to64 x) (Const64 [m])) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32,c).m) && s == 32+smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpMul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt32to64 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + v_0_0_1_0 := v_0_0_1.Args[0] + if v_0_0_1_0.Op != OpSignExt32to64 { + break + } + if x != v_0_0_1_0.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(32, c).m) && s == 32+smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 x (Const32 [m])) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 mul:(Hmul32 x (Const32 [m])) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 x (Const32 [m])) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq32_70(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 mul:(Hmul32 x (Const32 [m])) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m/2)) && s == smagic(32,c).s-1 && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m/2)) && s == smagic(32, c).s-1 && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd32 { + break + } + _ = v_1_1_0_0.Args[1] + mul := v_1_1_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_1_1_0_0.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 x (Const32 [m])) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd32 { + break + } + _ = v_1_1_0_0.Args[1] + mul := v_1_1_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + if x != v_1_1_0_0.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 (Const32 [m]) x)) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd32 { + break + } + _ = v_1_1_0_0.Args[1] + if x != v_1_1_0_0.Args[0] { + break + } + mul := v_1_1_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 x (Const32 [m]))) (Const64 [s])) (Rsh32x64 x (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub32 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd32 { + break + } + _ = v_1_1_0_0.Args[1] + if x != v_1_1_0_0.Args[0] { + break + } + mul := v_1_1_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd32 { + break + } + _ = v_1_0_0_0.Args[1] + mul := v_1_0_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_1_0_0_0.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 x (Const32 [m])) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd32 { + break + } + _ = v_1_0_0_0.Args[1] + mul := v_1_0_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + if x != v_1_0_0_0.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 (Const32 [m]) x)) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd32 { + break + } + _ = v_1_0_0_0.Args[1] + if x != v_1_0_0_0.Args[0] { + break + } + mul := v_1_0_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 x (Mul32 (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 x (Const32 [m]))) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd32 { + break + } + _ = v_1_0_0_0.Args[1] + if x != v_1_0_0_0.Args[0] { + break + } + mul := v_1_0_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst32 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd32 { + break + } + _ = v_0_1_0_0.Args[1] + mul := v_0_1_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_0_1_0_0.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq32_80(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 x (Const32 [m])) x) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd32 { + break + } + _ = v_0_1_0_0.Args[1] + mul := v_0_1_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + if x != v_0_1_0_0.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 (Const32 [m]) x)) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd32 { + break + } + _ = v_0_1_0_0.Args[1] + if x != v_0_1_0_0.Args[0] { + break + } + mul := v_0_1_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 x (Const32 [m]))) (Const64 [s])) (Rsh32x64 x (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst32 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub32 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd32 { + break + } + _ = v_0_1_0_0.Args[1] + if x != v_0_1_0_0.Args[0] { + break + } + mul := v_0_1_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd32 { + break + } + _ = v_0_0_0_0.Args[1] + mul := v_0_0_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_0_0_0_0.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 x (Const32 [m])) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd32 { + break + } + _ = v_0_0_0_0.Args[1] + mul := v_0_0_0_0.Args[0] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + if x != v_0_0_0_0.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 (Const32 [m]) x)) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd32 { + break + } + _ = v_0_0_0_0.Args[1] + if x != v_0_0_0_0.Args[0] { + break + } + mul := v_0_0_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq32 (Mul32 (Sub32 (Rsh32x64 (Add32 x mul:(Hmul32 x (Const32 [m]))) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) (Const32 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32,c).m)) && s == smagic(32,c).s && x.Op != OpConst32 && sdivisibleOK(32,c) + // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int64(int32(sdivisible(32,c).m))]) x) (Const32 [int64(int32(sdivisible(32,c).a))]) ) (Const32 [int64(32-sdivisible(32,c).k)]) ) (Const32 [int64(int32(sdivisible(32,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul32 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub32 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd32 { + break + } + _ = v_0_0_0_0.Args[1] + if x != v_0_0_0_0.Args[0] { + break + } + mul := v_0_0_0_0.Args[1] + if mul.Op != OpHmul32 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst32 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(int32(smagic(32, c).m)) && s == smagic(32, c).s && x.Op != OpConst32 && sdivisibleOK(32, c)) { + break + } + v.reset(OpLeq32U) + v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) + v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) + v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v3.AuxInt = int64(int32(sdivisible(32, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v4.AuxInt = int64(int32(sdivisible(32, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v5.AuxInt = int64(32 - sdivisible(32, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) + v6.AuxInt = int64(int32(sdivisible(32, c).max)) + v.AddArg(v6) + return true + } // match: (Eq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [int64(1< [0])) @@ -15869,6 +19566,11 @@ v.AddArg(v2) return true } + return false +} +func rewriteValuegeneric_OpEq32_90(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (Eq32 (Lsh32x64 (Rsh32x64 (Add32 (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k])) n) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [int64(1< [0])) @@ -15989,9 +19691,6 @@ v.AddArg(y) return true } - return false -} -func rewriteValuegeneric_OpEq32_60(v *Value) bool { // match: (Eq32 (Const32 [0]) s:(Sub32 x y)) // cond: s.Uses == 1 // result: (Eq32 x y) @@ -17819,6 +21518,2148 @@ v.AddArg(v4) return true } + // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub64 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 x (Const64 [m])) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub64 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 mul:(Hmul64 x (Const64 [m])) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst64 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub64 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 x (Const64 [m])) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst64 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub64 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub64 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 mul:(Hmul64 x (Const64 [m])) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m/2) && s == smagic(64,c).s-1 && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub64 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m/2) && s == smagic(64, c).s-1 && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub64 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd64 { + break + } + _ = v_1_1_0_0.Args[1] + mul := v_1_1_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_1_1_0_0.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq64_40(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 x (Const64 [m])) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub64 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd64 { + break + } + _ = v_1_1_0_0.Args[1] + mul := v_1_1_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + if x != v_1_1_0_0.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 (Const64 [m]) x)) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub64 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd64 { + break + } + _ = v_1_1_0_0.Args[1] + if x != v_1_1_0_0.Args[0] { + break + } + mul := v_1_1_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 x (Const64 [m]))) (Const64 [s])) (Rsh64x64 x (Const64 [63]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub64 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh64x64 { + break + } + _ = v_1_1_0.Args[1] + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAdd64 { + break + } + _ = v_1_1_0_0.Args[1] + if x != v_1_1_0_0.Args[0] { + break + } + mul := v_1_1_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh64x64 { + break + } + _ = v_1_1_1.Args[1] + if x != v_1_1_1.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd64 { + break + } + _ = v_1_0_0_0.Args[1] + mul := v_1_0_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_1_0_0_0.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 x (Const64 [m])) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd64 { + break + } + _ = v_1_0_0_0.Args[1] + mul := v_1_0_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + if x != v_1_0_0_0.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 (Const64 [m]) x)) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd64 { + break + } + _ = v_1_0_0_0.Args[1] + if x != v_1_0_0_0.Args[0] { + break + } + mul := v_1_0_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 x (Mul64 (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 x (Const64 [m]))) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh64x64 { + break + } + _ = v_1_0_0.Args[1] + v_1_0_0_0 := v_1_0_0.Args[0] + if v_1_0_0_0.Op != OpAdd64 { + break + } + _ = v_1_0_0_0.Args[1] + if x != v_1_0_0_0.Args[0] { + break + } + mul := v_1_0_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh64x64 { + break + } + _ = v_1_0_1.Args[1] + if x != v_1_0_1.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 63 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst64 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub64 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd64 { + break + } + _ = v_0_1_0_0.Args[1] + mul := v_0_1_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_0_1_0_0.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 x (Const64 [m])) x) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst64 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub64 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd64 { + break + } + _ = v_0_1_0_0.Args[1] + mul := v_0_1_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + if x != v_0_1_0_0.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 (Const64 [m]) x)) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst64 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub64 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd64 { + break + } + _ = v_0_1_0_0.Args[1] + if x != v_0_1_0_0.Args[0] { + break + } + mul := v_0_1_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq64_50(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq64 (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 x (Const64 [m]))) (Const64 [s])) (Rsh64x64 x (Const64 [63])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst64 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub64 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh64x64 { + break + } + _ = v_0_1_0.Args[1] + v_0_1_0_0 := v_0_1_0.Args[0] + if v_0_1_0_0.Op != OpAdd64 { + break + } + _ = v_0_1_0_0.Args[1] + if x != v_0_1_0_0.Args[0] { + break + } + mul := v_0_1_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh64x64 { + break + } + _ = v_0_1_1.Args[1] + if x != v_0_1_1.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 63 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub64 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd64 { + break + } + _ = v_0_0_0_0.Args[1] + mul := v_0_0_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + if x != v_0_0_0_0.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 x (Const64 [m])) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub64 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd64 { + break + } + _ = v_0_0_0_0.Args[1] + mul := v_0_0_0_0.Args[0] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + if x != v_0_0_0_0.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 (Const64 [m]) x)) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub64 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd64 { + break + } + _ = v_0_0_0_0.Args[1] + if x != v_0_0_0_0.Args[0] { + break + } + mul := v_0_0_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst64 { + break + } + m := mul_0.AuxInt + if x != mul.Args[1] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } + // match: (Eq64 (Mul64 (Sub64 (Rsh64x64 (Add64 x mul:(Hmul64 x (Const64 [m]))) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) (Const64 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64,c).m) && s == smagic(64,c).s && x.Op != OpConst64 && sdivisibleOK(64,c) + // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible(64,c).m)]) x) (Const64 [int64(sdivisible(64,c).a)]) ) (Const64 [int64(64-sdivisible(64,c).k)]) ) (Const64 [int64(sdivisible(64,c).max)]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul64 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub64 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh64x64 { + break + } + _ = v_0_0_0.Args[1] + v_0_0_0_0 := v_0_0_0.Args[0] + if v_0_0_0_0.Op != OpAdd64 { + break + } + _ = v_0_0_0_0.Args[1] + if x != v_0_0_0_0.Args[0] { + break + } + mul := v_0_0_0_0.Args[1] + if mul.Op != OpHmul64 { + break + } + _ = mul.Args[1] + if x != mul.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst64 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh64x64 { + break + } + _ = v_0_0_1.Args[1] + if x != v_0_0_1.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 63 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst64 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(64, c).m) && s == smagic(64, c).s && x.Op != OpConst64 && sdivisibleOK(64, c)) { + break + } + v.reset(OpLeq64U) + v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) + v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) + v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) + v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v3.AuxInt = int64(sdivisible(64, c).m) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v4.AuxInt = int64(sdivisible(64, c).a) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v5.AuxInt = int64(64 - sdivisible(64, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) + v6.AuxInt = int64(sdivisible(64, c).max) + v.AddArg(v6) + return true + } // match: (Eq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [int64(1< [0])) @@ -18223,6 +24064,9 @@ v.AddArg(y) return true } + return false +} +func rewriteValuegeneric_OpEq64_60(v *Value) bool { // match: (Eq64 (Const64 [0]) s:(Sub64 x y)) // cond: s.Uses == 1 // result: (Eq64 x y) @@ -18552,78 +24396,159 @@ v.AddArg(v3) return true } - // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))))) - // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) - // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) + // match: (Eq8 (Mod8 x (Const8 [c])) (Const8 [0])) + // cond: x.Op != OpConst8 && sdivisibleOK(8,c) && !hasSmallRotate(config) + // result: (Eq32 (Mod32 (SignExt8to32 x) (Const32 [c])) (Const32 [0])) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpMul8 { + v_0 := v.Args[0] + if v_0.Op != OpMod8 { break } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpConst8 { + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst8 { break } - c := v_1_0.AuxInt - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpTrunc32to8 { + c := v_0_1.AuxInt + v_1 := v.Args[1] + if v_1.Op != OpConst8 { break } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpRsh32Ux64 { - break - } - _ = v_1_1_0.Args[1] - mul := v_1_1_0.Args[0] - if mul.Op != OpMul32 { + if v_1.AuxInt != 0 { break } - _ = mul.Args[1] - mul_0 := mul.Args[0] - if mul_0.Op != OpConst32 { + if !(x.Op != OpConst8 && sdivisibleOK(8, c) && !hasSmallRotate(config)) { break } - m := mul_0.AuxInt - mul_1 := mul.Args[1] - if mul_1.Op != OpZeroExt8to32 { - break - } - if x != mul_1.Args[0] { - break - } - v_1_1_0_1 := v_1_1_0.Args[1] - if v_1_1_0_1.Op != OpConst64 { - break - } - s := v_1_1_0_1.AuxInt - if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { - break - } - v.reset(OpLeq8U) - v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) - v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) - v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) - v2.AuxInt = int64(int8(udivisible(8, c).m)) - v1.AddArg(v2) + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) + v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) - v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) - v3.AuxInt = int64(8 - udivisible(8, c).k) - v0.AddArg(v3) + v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v2.AuxInt = c + v0.AddArg(v2) v.AddArg(v0) - v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) - v4.AuxInt = int64(int8(udivisible(8, c).max)) - v.AddArg(v4) + v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v3.AuxInt = 0 + v.AddArg(v3) return true } return false } func rewriteValuegeneric_OpEq8_10(v *Value) bool { b := v.Block + config := b.Func.Config typ := &b.Func.Config.Types + // match: (Eq8 (Const8 [0]) (Mod8 x (Const8 [c]))) + // cond: x.Op != OpConst8 && sdivisibleOK(8,c) && !hasSmallRotate(config) + // result: (Eq32 (Mod32 (SignExt8to32 x) (Const32 [c])) (Const32 [0])) + for { + _ = v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpConst8 { + break + } + if v_0.AuxInt != 0 { + break + } + v_1 := v.Args[1] + if v_1.Op != OpMod8 { + break + } + _ = v_1.Args[1] + x := v_1.Args[0] + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst8 { + break + } + c := v_1_1.AuxInt + if !(x.Op != OpConst8 && sdivisibleOK(8, c) && !hasSmallRotate(config)) { + break + } + v.reset(OpEq32) + v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) + v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v2.AuxInt = c + v0.AddArg(v2) + v.AddArg(v0) + v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) + v3.AuxInt = 0 + v.AddArg(v3) + return true + } + // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpTrunc32to8 { + break + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32Ux64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpZeroExt8to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8, c).m) && s == 8+umagic(8, c).s && x.Op != OpConst8 && udivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v2.AuxInt = int64(int8(udivisible(8, c).m)) + v1.AddArg(v2) + v1.AddArg(x) + v0.AddArg(v1) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(8 - udivisible(8, c).k) + v0.AddArg(v3) + v.AddArg(v0) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(udivisible(8, c).max)) + v.AddArg(v4) + return true + } // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (ZeroExt8to32 x) (Const32 [m])) (Const64 [s]))))) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<8+umagic(8,c).m) && s == 8+umagic(8,c).s && x.Op != OpConst8 && udivisibleOK(8,c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int64(int8(udivisible(8,c).m))]) x) (Const8 [int64(8-udivisible(8,c).k)]) ) (Const8 [int64(int8(udivisible(8,c).max))]) ) @@ -19089,6 +25014,743 @@ v.AddArg(v4) return true } + // match: (Eq8 x (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub8 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt8to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + v_1_1_1_0 := v_1_1_1.Args[0] + if v_1_1_1_0.Op != OpSignExt8to32 { + break + } + if x != v_1_1_1_0.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + return false +} +func rewriteValuegeneric_OpEq8_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (Eq8 x (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (SignExt8to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := v_1_0.AuxInt + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpSub8 { + break + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpRsh32x64 { + break + } + _ = v_1_1_0.Args[1] + mul := v_1_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt8to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_1_0_1 := v_1_1_0.Args[1] + if v_1_1_0_1.Op != OpConst64 { + break + } + s := v_1_1_0_1.AuxInt + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpRsh32x64 { + break + } + _ = v_1_1_1.Args[1] + v_1_1_1_0 := v_1_1_1.Args[0] + if v_1_1_1_0.Op != OpSignExt8to32 { + break + } + if x != v_1_1_1_0.Args[0] { + break + } + v_1_1_1_1 := v_1_1_1.Args[1] + if v_1_1_1_1.Op != OpConst64 { + break + } + if v_1_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq8 x (Mul8 (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) (Const8 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub8 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt8to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpSignExt8to32 { + break + } + if x != v_1_0_1_0.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst8 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq8 x (Mul8 (Sub8 (Rsh32x64 mul:(Mul32 (SignExt8to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) (Const8 [c]))) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + _ = v.Args[1] + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpMul8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpSub8 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpRsh32x64 { + break + } + _ = v_1_0_0.Args[1] + mul := v_1_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt8to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_1_0_0_1 := v_1_0_0.Args[1] + if v_1_0_0_1.Op != OpConst64 { + break + } + s := v_1_0_0_1.AuxInt + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpRsh32x64 { + break + } + _ = v_1_0_1.Args[1] + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpSignExt8to32 { + break + } + if x != v_1_0_1_0.Args[0] { + break + } + v_1_0_1_1 := v_1_0_1.Args[1] + if v_1_0_1_1.Op != OpConst64 { + break + } + if v_1_0_1_1.AuxInt != 31 { + break + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst8 { + break + } + c := v_1_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq8 (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul8 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst8 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub8 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt8to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + v_0_1_1_0 := v_0_1_1.Args[0] + if v_0_1_1_0.Op != OpSignExt8to32 { + break + } + if x != v_0_1_1_0.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq8 (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (SignExt8to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31])))) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul8 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpConst8 { + break + } + c := v_0_0.AuxInt + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpSub8 { + break + } + _ = v_0_1.Args[1] + v_0_1_0 := v_0_1.Args[0] + if v_0_1_0.Op != OpRsh32x64 { + break + } + _ = v_0_1_0.Args[1] + mul := v_0_1_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt8to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_1_0_1 := v_0_1_0.Args[1] + if v_0_1_0_1.Op != OpConst64 { + break + } + s := v_0_1_0_1.AuxInt + v_0_1_1 := v_0_1.Args[1] + if v_0_1_1.Op != OpRsh32x64 { + break + } + _ = v_0_1_1.Args[1] + v_0_1_1_0 := v_0_1_1.Args[0] + if v_0_1_1_0.Op != OpSignExt8to32 { + break + } + if x != v_0_1_1_0.Args[0] { + break + } + v_0_1_1_1 := v_0_1_1.Args[1] + if v_0_1_1_1.Op != OpConst64 { + break + } + if v_0_1_1_1.AuxInt != 31 { + break + } + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq8 (Mul8 (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) (Const8 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul8 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub8 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpConst32 { + break + } + m := mul_0.AuxInt + mul_1 := mul.Args[1] + if mul_1.Op != OpSignExt8to32 { + break + } + if x != mul_1.Args[0] { + break + } + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + v_0_0_1_0 := v_0_0_1.Args[0] + if v_0_0_1_0.Op != OpSignExt8to32 { + break + } + if x != v_0_0_1_0.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst8 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } + // match: (Eq8 (Mul8 (Sub8 (Rsh32x64 mul:(Mul32 (SignExt8to32 x) (Const32 [m])) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) (Const8 [c])) x) + // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8,c).m) && s == 8+smagic(8,c).s && x.Op != OpConst8 && sdivisibleOK(8,c) + // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int64(int8(sdivisible(8,c).m))]) x) (Const8 [int64(int8(sdivisible(8,c).a))]) ) (Const8 [int64(8-sdivisible(8,c).k)]) ) (Const8 [int64(int8(sdivisible(8,c).max))]) ) + for { + x := v.Args[1] + v_0 := v.Args[0] + if v_0.Op != OpMul8 { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpSub8 { + break + } + _ = v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpRsh32x64 { + break + } + _ = v_0_0_0.Args[1] + mul := v_0_0_0.Args[0] + if mul.Op != OpMul32 { + break + } + _ = mul.Args[1] + mul_0 := mul.Args[0] + if mul_0.Op != OpSignExt8to32 { + break + } + if x != mul_0.Args[0] { + break + } + mul_1 := mul.Args[1] + if mul_1.Op != OpConst32 { + break + } + m := mul_1.AuxInt + v_0_0_0_1 := v_0_0_0.Args[1] + if v_0_0_0_1.Op != OpConst64 { + break + } + s := v_0_0_0_1.AuxInt + v_0_0_1 := v_0_0.Args[1] + if v_0_0_1.Op != OpRsh32x64 { + break + } + _ = v_0_0_1.Args[1] + v_0_0_1_0 := v_0_0_1.Args[0] + if v_0_0_1_0.Op != OpSignExt8to32 { + break + } + if x != v_0_0_1_0.Args[0] { + break + } + v_0_0_1_1 := v_0_0_1.Args[1] + if v_0_0_1_1.Op != OpConst64 { + break + } + if v_0_0_1_1.AuxInt != 31 { + break + } + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpConst8 { + break + } + c := v_0_1.AuxInt + if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic(8, c).m) && s == 8+smagic(8, c).s && x.Op != OpConst8 && sdivisibleOK(8, c)) { + break + } + v.reset(OpLeq8U) + v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) + v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) + v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) + v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v3.AuxInt = int64(int8(sdivisible(8, c).m)) + v2.AddArg(v3) + v2.AddArg(x) + v1.AddArg(v2) + v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v4.AuxInt = int64(int8(sdivisible(8, c).a)) + v1.AddArg(v4) + v0.AddArg(v1) + v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v5.AuxInt = int64(8 - sdivisible(8, c).k) + v0.AddArg(v5) + v.AddArg(v0) + v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) + v6.AuxInt = int64(int8(sdivisible(8, c).max)) + v.AddArg(v6) + return true + } // match: (Eq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k]))) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [int64(1< [0])) @@ -19375,7 +26037,7 @@ } return false } -func rewriteValuegeneric_OpEq8_20(v *Value) bool { +func rewriteValuegeneric_OpEq8_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq8 (Lsh8x64 (Rsh8x64 (Add8 (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar])) n) (Const64 [k])) (Const64 [k])) n) @@ -25308,7 +31970,7 @@ return true } // match: (Mod8u x (Const8 [c])) - // cond: x.Op != OpConst8 && c > 0 && umagicOK(8,c) + // cond: x.Op != OpConst8 && c > 0 && umagicOK(8, c) // result: (Sub8 x (Mul8 (Div8u x (Const8 [c])) (Const8 [c]))) for { t := v.Type go_60ad3c48f59c35981dd872ed5dfe74e4d6becab2_src_cmd_compile_internal_ssa_rewriteAMD64.go.test000066400000000000000000071375351516001707200361670ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit 60ad3c48f59c35981dd872ed5dfe74e4d6becab2 file src/cmd/compile/internal/ssa/rewriteAMD64.go -- x -- // Code generated from gen/AMD64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "internal/buildcfg" import "math" import "cmd/internal/obj" import "cmd/compile/internal/types" func rewriteValueAMD64(v *Value) bool { switch v.Op { case OpAMD64ADCQ: return rewriteValueAMD64_OpAMD64ADCQ(v) case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst(v) case OpAMD64ADDL: return rewriteValueAMD64_OpAMD64ADDL(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst(v) case OpAMD64ADDLconstmodify: return rewriteValueAMD64_OpAMD64ADDLconstmodify(v) case OpAMD64ADDLload: return rewriteValueAMD64_OpAMD64ADDLload(v) case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify(v) case OpAMD64ADDQ: return rewriteValueAMD64_OpAMD64ADDQ(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry(v) case OpAMD64ADDQconst: return rewriteValueAMD64_OpAMD64ADDQconst(v) case OpAMD64ADDQconstmodify: return rewriteValueAMD64_OpAMD64ADDQconstmodify(v) case OpAMD64ADDQload: return rewriteValueAMD64_OpAMD64ADDQload(v) case OpAMD64ADDQmodify: return rewriteValueAMD64_OpAMD64ADDQmodify(v) case OpAMD64ADDSD: return rewriteValueAMD64_OpAMD64ADDSD(v) case OpAMD64ADDSDload: return rewriteValueAMD64_OpAMD64ADDSDload(v) case OpAMD64ADDSS: return rewriteValueAMD64_OpAMD64ADDSS(v) case OpAMD64ADDSSload: return rewriteValueAMD64_OpAMD64ADDSSload(v) case OpAMD64ANDL: return rewriteValueAMD64_OpAMD64ANDL(v) case OpAMD64ANDLconst: return rewriteValueAMD64_OpAMD64ANDLconst(v) case OpAMD64ANDLconstmodify: return rewriteValueAMD64_OpAMD64ANDLconstmodify(v) case OpAMD64ANDLload: return rewriteValueAMD64_OpAMD64ANDLload(v) case OpAMD64ANDLmodify: return rewriteValueAMD64_OpAMD64ANDLmodify(v) case OpAMD64ANDNL: return rewriteValueAMD64_OpAMD64ANDNL(v) case OpAMD64ANDNQ: return rewriteValueAMD64_OpAMD64ANDNQ(v) case OpAMD64ANDQ: return rewriteValueAMD64_OpAMD64ANDQ(v) case OpAMD64ANDQconst: return rewriteValueAMD64_OpAMD64ANDQconst(v) case OpAMD64ANDQconstmodify: return rewriteValueAMD64_OpAMD64ANDQconstmodify(v) case OpAMD64ANDQload: return rewriteValueAMD64_OpAMD64ANDQload(v) case OpAMD64ANDQmodify: return rewriteValueAMD64_OpAMD64ANDQmodify(v) case OpAMD64BSFQ: return rewriteValueAMD64_OpAMD64BSFQ(v) case OpAMD64BSWAPL: return rewriteValueAMD64_OpAMD64BSWAPL(v) case OpAMD64BSWAPQ: return rewriteValueAMD64_OpAMD64BSWAPQ(v) case OpAMD64BTCLconst: return rewriteValueAMD64_OpAMD64BTCLconst(v) case OpAMD64BTCQconst: return rewriteValueAMD64_OpAMD64BTCQconst(v) case OpAMD64BTLconst: return rewriteValueAMD64_OpAMD64BTLconst(v) case OpAMD64BTQconst: return rewriteValueAMD64_OpAMD64BTQconst(v) case OpAMD64BTRLconst: return rewriteValueAMD64_OpAMD64BTRLconst(v) case OpAMD64BTRQconst: return rewriteValueAMD64_OpAMD64BTRQconst(v) case OpAMD64BTSLconst: return rewriteValueAMD64_OpAMD64BTSLconst(v) case OpAMD64BTSQconst: return rewriteValueAMD64_OpAMD64BTSQconst(v) case OpAMD64CMOVLCC: return rewriteValueAMD64_OpAMD64CMOVLCC(v) case OpAMD64CMOVLCS: return rewriteValueAMD64_OpAMD64CMOVLCS(v) case OpAMD64CMOVLEQ: return rewriteValueAMD64_OpAMD64CMOVLEQ(v) case OpAMD64CMOVLGE: return rewriteValueAMD64_OpAMD64CMOVLGE(v) case OpAMD64CMOVLGT: return rewriteValueAMD64_OpAMD64CMOVLGT(v) case OpAMD64CMOVLHI: return rewriteValueAMD64_OpAMD64CMOVLHI(v) case OpAMD64CMOVLLE: return rewriteValueAMD64_OpAMD64CMOVLLE(v) case OpAMD64CMOVLLS: return rewriteValueAMD64_OpAMD64CMOVLLS(v) case OpAMD64CMOVLLT: return rewriteValueAMD64_OpAMD64CMOVLLT(v) case OpAMD64CMOVLNE: return rewriteValueAMD64_OpAMD64CMOVLNE(v) case OpAMD64CMOVQCC: return rewriteValueAMD64_OpAMD64CMOVQCC(v) case OpAMD64CMOVQCS: return rewriteValueAMD64_OpAMD64CMOVQCS(v) case OpAMD64CMOVQEQ: return rewriteValueAMD64_OpAMD64CMOVQEQ(v) case OpAMD64CMOVQGE: return rewriteValueAMD64_OpAMD64CMOVQGE(v) case OpAMD64CMOVQGT: return rewriteValueAMD64_OpAMD64CMOVQGT(v) case OpAMD64CMOVQHI: return rewriteValueAMD64_OpAMD64CMOVQHI(v) case OpAMD64CMOVQLE: return rewriteValueAMD64_OpAMD64CMOVQLE(v) case OpAMD64CMOVQLS: return rewriteValueAMD64_OpAMD64CMOVQLS(v) case OpAMD64CMOVQLT: return rewriteValueAMD64_OpAMD64CMOVQLT(v) case OpAMD64CMOVQNE: return rewriteValueAMD64_OpAMD64CMOVQNE(v) case OpAMD64CMOVWCC: return rewriteValueAMD64_OpAMD64CMOVWCC(v) case OpAMD64CMOVWCS: return rewriteValueAMD64_OpAMD64CMOVWCS(v) case OpAMD64CMOVWEQ: return rewriteValueAMD64_OpAMD64CMOVWEQ(v) case OpAMD64CMOVWGE: return rewriteValueAMD64_OpAMD64CMOVWGE(v) case OpAMD64CMOVWGT: return rewriteValueAMD64_OpAMD64CMOVWGT(v) case OpAMD64CMOVWHI: return rewriteValueAMD64_OpAMD64CMOVWHI(v) case OpAMD64CMOVWLE: return rewriteValueAMD64_OpAMD64CMOVWLE(v) case OpAMD64CMOVWLS: return rewriteValueAMD64_OpAMD64CMOVWLS(v) case OpAMD64CMOVWLT: return rewriteValueAMD64_OpAMD64CMOVWLT(v) case OpAMD64CMOVWNE: return rewriteValueAMD64_OpAMD64CMOVWNE(v) case OpAMD64CMPB: return rewriteValueAMD64_OpAMD64CMPB(v) case OpAMD64CMPBconst: return rewriteValueAMD64_OpAMD64CMPBconst(v) case OpAMD64CMPBconstload: return rewriteValueAMD64_OpAMD64CMPBconstload(v) case OpAMD64CMPBload: return rewriteValueAMD64_OpAMD64CMPBload(v) case OpAMD64CMPL: return rewriteValueAMD64_OpAMD64CMPL(v) case OpAMD64CMPLconst: return rewriteValueAMD64_OpAMD64CMPLconst(v) case OpAMD64CMPLconstload: return rewriteValueAMD64_OpAMD64CMPLconstload(v) case OpAMD64CMPLload: return rewriteValueAMD64_OpAMD64CMPLload(v) case OpAMD64CMPQ: return rewriteValueAMD64_OpAMD64CMPQ(v) case OpAMD64CMPQconst: return rewriteValueAMD64_OpAMD64CMPQconst(v) case OpAMD64CMPQconstload: return rewriteValueAMD64_OpAMD64CMPQconstload(v) case OpAMD64CMPQload: return rewriteValueAMD64_OpAMD64CMPQload(v) case OpAMD64CMPW: return rewriteValueAMD64_OpAMD64CMPW(v) case OpAMD64CMPWconst: return rewriteValueAMD64_OpAMD64CMPWconst(v) case OpAMD64CMPWconstload: return rewriteValueAMD64_OpAMD64CMPWconstload(v) case OpAMD64CMPWload: return rewriteValueAMD64_OpAMD64CMPWload(v) case OpAMD64CMPXCHGLlock: return rewriteValueAMD64_OpAMD64CMPXCHGLlock(v) case OpAMD64CMPXCHGQlock: return rewriteValueAMD64_OpAMD64CMPXCHGQlock(v) case OpAMD64DIVSD: return rewriteValueAMD64_OpAMD64DIVSD(v) case OpAMD64DIVSDload: return rewriteValueAMD64_OpAMD64DIVSDload(v) case OpAMD64DIVSS: return rewriteValueAMD64_OpAMD64DIVSS(v) case OpAMD64DIVSSload: return rewriteValueAMD64_OpAMD64DIVSSload(v) case OpAMD64HMULL: return rewriteValueAMD64_OpAMD64HMULL(v) case OpAMD64HMULLU: return rewriteValueAMD64_OpAMD64HMULLU(v) case OpAMD64HMULQ: return rewriteValueAMD64_OpAMD64HMULQ(v) case OpAMD64HMULQU: return rewriteValueAMD64_OpAMD64HMULQU(v) case OpAMD64LEAL: return rewriteValueAMD64_OpAMD64LEAL(v) case OpAMD64LEAL1: return rewriteValueAMD64_OpAMD64LEAL1(v) case OpAMD64LEAL2: return rewriteValueAMD64_OpAMD64LEAL2(v) case OpAMD64LEAL4: return rewriteValueAMD64_OpAMD64LEAL4(v) case OpAMD64LEAL8: return rewriteValueAMD64_OpAMD64LEAL8(v) case OpAMD64LEAQ: return rewriteValueAMD64_OpAMD64LEAQ(v) case OpAMD64LEAQ1: return rewriteValueAMD64_OpAMD64LEAQ1(v) case OpAMD64LEAQ2: return rewriteValueAMD64_OpAMD64LEAQ2(v) case OpAMD64LEAQ4: return rewriteValueAMD64_OpAMD64LEAQ4(v) case OpAMD64LEAQ8: return rewriteValueAMD64_OpAMD64LEAQ8(v) case OpAMD64MOVBELstore: return rewriteValueAMD64_OpAMD64MOVBELstore(v) case OpAMD64MOVBEQstore: return rewriteValueAMD64_OpAMD64MOVBEQstore(v) case OpAMD64MOVBEWstore: return rewriteValueAMD64_OpAMD64MOVBEWstore(v) case OpAMD64MOVBQSX: return rewriteValueAMD64_OpAMD64MOVBQSX(v) case OpAMD64MOVBQSXload: return rewriteValueAMD64_OpAMD64MOVBQSXload(v) case OpAMD64MOVBQZX: return rewriteValueAMD64_OpAMD64MOVBQZX(v) case OpAMD64MOVBatomicload: return rewriteValueAMD64_OpAMD64MOVBatomicload(v) case OpAMD64MOVBload: return rewriteValueAMD64_OpAMD64MOVBload(v) case OpAMD64MOVBstore: return rewriteValueAMD64_OpAMD64MOVBstore(v) case OpAMD64MOVBstoreconst: return rewriteValueAMD64_OpAMD64MOVBstoreconst(v) case OpAMD64MOVLQSX: return rewriteValueAMD64_OpAMD64MOVLQSX(v) case OpAMD64MOVLQSXload: return rewriteValueAMD64_OpAMD64MOVLQSXload(v) case OpAMD64MOVLQZX: return rewriteValueAMD64_OpAMD64MOVLQZX(v) case OpAMD64MOVLatomicload: return rewriteValueAMD64_OpAMD64MOVLatomicload(v) case OpAMD64MOVLf2i: return rewriteValueAMD64_OpAMD64MOVLf2i(v) case OpAMD64MOVLi2f: return rewriteValueAMD64_OpAMD64MOVLi2f(v) case OpAMD64MOVLload: return rewriteValueAMD64_OpAMD64MOVLload(v) case OpAMD64MOVLstore: return rewriteValueAMD64_OpAMD64MOVLstore(v) case OpAMD64MOVLstoreconst: return rewriteValueAMD64_OpAMD64MOVLstoreconst(v) case OpAMD64MOVOload: return rewriteValueAMD64_OpAMD64MOVOload(v) case OpAMD64MOVOstore: return rewriteValueAMD64_OpAMD64MOVOstore(v) case OpAMD64MOVOstoreconst: return rewriteValueAMD64_OpAMD64MOVOstoreconst(v) case OpAMD64MOVQatomicload: return rewriteValueAMD64_OpAMD64MOVQatomicload(v) case OpAMD64MOVQf2i: return rewriteValueAMD64_OpAMD64MOVQf2i(v) case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f(v) case OpAMD64MOVQload: return rewriteValueAMD64_OpAMD64MOVQload(v) case OpAMD64MOVQstore: return rewriteValueAMD64_OpAMD64MOVQstore(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst(v) case OpAMD64MOVSDload: return rewriteValueAMD64_OpAMD64MOVSDload(v) case OpAMD64MOVSDstore: return rewriteValueAMD64_OpAMD64MOVSDstore(v) case OpAMD64MOVSSload: return rewriteValueAMD64_OpAMD64MOVSSload(v) case OpAMD64MOVSSstore: return rewriteValueAMD64_OpAMD64MOVSSstore(v) case OpAMD64MOVWQSX: return rewriteValueAMD64_OpAMD64MOVWQSX(v) case OpAMD64MOVWQSXload: return rewriteValueAMD64_OpAMD64MOVWQSXload(v) case OpAMD64MOVWQZX: return rewriteValueAMD64_OpAMD64MOVWQZX(v) case OpAMD64MOVWload: return rewriteValueAMD64_OpAMD64MOVWload(v) case OpAMD64MOVWstore: return rewriteValueAMD64_OpAMD64MOVWstore(v) case OpAMD64MOVWstoreconst: return rewriteValueAMD64_OpAMD64MOVWstoreconst(v) case OpAMD64MULL: return rewriteValueAMD64_OpAMD64MULL(v) case OpAMD64MULLconst: return rewriteValueAMD64_OpAMD64MULLconst(v) case OpAMD64MULQ: return rewriteValueAMD64_OpAMD64MULQ(v) case OpAMD64MULQconst: return rewriteValueAMD64_OpAMD64MULQconst(v) case OpAMD64MULSD: return rewriteValueAMD64_OpAMD64MULSD(v) case OpAMD64MULSDload: return rewriteValueAMD64_OpAMD64MULSDload(v) case OpAMD64MULSS: return rewriteValueAMD64_OpAMD64MULSS(v) case OpAMD64MULSSload: return rewriteValueAMD64_OpAMD64MULSSload(v) case OpAMD64NEGL: return rewriteValueAMD64_OpAMD64NEGL(v) case OpAMD64NEGQ: return rewriteValueAMD64_OpAMD64NEGQ(v) case OpAMD64NOTL: return rewriteValueAMD64_OpAMD64NOTL(v) case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ(v) case OpAMD64ORL: return rewriteValueAMD64_OpAMD64ORL(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst(v) case OpAMD64ORLconstmodify: return rewriteValueAMD64_OpAMD64ORLconstmodify(v) case OpAMD64ORLload: return rewriteValueAMD64_OpAMD64ORLload(v) case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify(v) case OpAMD64ORQ: return rewriteValueAMD64_OpAMD64ORQ(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst(v) case OpAMD64ORQconstmodify: return rewriteValueAMD64_OpAMD64ORQconstmodify(v) case OpAMD64ORQload: return rewriteValueAMD64_OpAMD64ORQload(v) case OpAMD64ORQmodify: return rewriteValueAMD64_OpAMD64ORQmodify(v) case OpAMD64ROLB: return rewriteValueAMD64_OpAMD64ROLB(v) case OpAMD64ROLBconst: return rewriteValueAMD64_OpAMD64ROLBconst(v) case OpAMD64ROLL: return rewriteValueAMD64_OpAMD64ROLL(v) case OpAMD64ROLLconst: return rewriteValueAMD64_OpAMD64ROLLconst(v) case OpAMD64ROLQ: return rewriteValueAMD64_OpAMD64ROLQ(v) case OpAMD64ROLQconst: return rewriteValueAMD64_OpAMD64ROLQconst(v) case OpAMD64ROLW: return rewriteValueAMD64_OpAMD64ROLW(v) case OpAMD64ROLWconst: return rewriteValueAMD64_OpAMD64ROLWconst(v) case OpAMD64RORB: return rewriteValueAMD64_OpAMD64RORB(v) case OpAMD64RORL: return rewriteValueAMD64_OpAMD64RORL(v) case OpAMD64RORQ: return rewriteValueAMD64_OpAMD64RORQ(v) case OpAMD64RORW: return rewriteValueAMD64_OpAMD64RORW(v) case OpAMD64SARB: return rewriteValueAMD64_OpAMD64SARB(v) case OpAMD64SARBconst: return rewriteValueAMD64_OpAMD64SARBconst(v) case OpAMD64SARL: return rewriteValueAMD64_OpAMD64SARL(v) case OpAMD64SARLconst: return rewriteValueAMD64_OpAMD64SARLconst(v) case OpAMD64SARQ: return rewriteValueAMD64_OpAMD64SARQ(v) case OpAMD64SARQconst: return rewriteValueAMD64_OpAMD64SARQconst(v) case OpAMD64SARW: return rewriteValueAMD64_OpAMD64SARW(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst(v) case OpAMD64SARXL: return rewriteValueAMD64_OpAMD64SARXL(v) case OpAMD64SARXLload: return rewriteValueAMD64_OpAMD64SARXLload(v) case OpAMD64SARXQ: return rewriteValueAMD64_OpAMD64SARXQ(v) case OpAMD64SARXQload: return rewriteValueAMD64_OpAMD64SARXQload(v) case OpAMD64SBBLcarrymask: return rewriteValueAMD64_OpAMD64SBBLcarrymask(v) case OpAMD64SBBQ: return rewriteValueAMD64_OpAMD64SBBQ(v) case OpAMD64SBBQcarrymask: return rewriteValueAMD64_OpAMD64SBBQcarrymask(v) case OpAMD64SBBQconst: return rewriteValueAMD64_OpAMD64SBBQconst(v) case OpAMD64SETA: return rewriteValueAMD64_OpAMD64SETA(v) case OpAMD64SETAE: return rewriteValueAMD64_OpAMD64SETAE(v) case OpAMD64SETAEstore: return rewriteValueAMD64_OpAMD64SETAEstore(v) case OpAMD64SETAstore: return rewriteValueAMD64_OpAMD64SETAstore(v) case OpAMD64SETB: return rewriteValueAMD64_OpAMD64SETB(v) case OpAMD64SETBE: return rewriteValueAMD64_OpAMD64SETBE(v) case OpAMD64SETBEstore: return rewriteValueAMD64_OpAMD64SETBEstore(v) case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore(v) case OpAMD64SETEQ: return rewriteValueAMD64_OpAMD64SETEQ(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore(v) case OpAMD64SETG: return rewriteValueAMD64_OpAMD64SETG(v) case OpAMD64SETGE: return rewriteValueAMD64_OpAMD64SETGE(v) case OpAMD64SETGEstore: return rewriteValueAMD64_OpAMD64SETGEstore(v) case OpAMD64SETGstore: return rewriteValueAMD64_OpAMD64SETGstore(v) case OpAMD64SETL: return rewriteValueAMD64_OpAMD64SETL(v) case OpAMD64SETLE: return rewriteValueAMD64_OpAMD64SETLE(v) case OpAMD64SETLEstore: return rewriteValueAMD64_OpAMD64SETLEstore(v) case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore(v) case OpAMD64SETNE: return rewriteValueAMD64_OpAMD64SETNE(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore(v) case OpAMD64SHLL: return rewriteValueAMD64_OpAMD64SHLL(v) case OpAMD64SHLLconst: return rewriteValueAMD64_OpAMD64SHLLconst(v) case OpAMD64SHLQ: return rewriteValueAMD64_OpAMD64SHLQ(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst(v) case OpAMD64SHLXL: return rewriteValueAMD64_OpAMD64SHLXL(v) case OpAMD64SHLXLload: return rewriteValueAMD64_OpAMD64SHLXLload(v) case OpAMD64SHLXQ: return rewriteValueAMD64_OpAMD64SHLXQ(v) case OpAMD64SHLXQload: return rewriteValueAMD64_OpAMD64SHLXQload(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB(v) case OpAMD64SHRBconst: return rewriteValueAMD64_OpAMD64SHRBconst(v) case OpAMD64SHRL: return rewriteValueAMD64_OpAMD64SHRL(v) case OpAMD64SHRLconst: return rewriteValueAMD64_OpAMD64SHRLconst(v) case OpAMD64SHRQ: return rewriteValueAMD64_OpAMD64SHRQ(v) case OpAMD64SHRQconst: return rewriteValueAMD64_OpAMD64SHRQconst(v) case OpAMD64SHRW: return rewriteValueAMD64_OpAMD64SHRW(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst(v) case OpAMD64SHRXL: return rewriteValueAMD64_OpAMD64SHRXL(v) case OpAMD64SHRXLload: return rewriteValueAMD64_OpAMD64SHRXLload(v) case OpAMD64SHRXQ: return rewriteValueAMD64_OpAMD64SHRXQ(v) case OpAMD64SHRXQload: return rewriteValueAMD64_OpAMD64SHRXQload(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL(v) case OpAMD64SUBLconst: return rewriteValueAMD64_OpAMD64SUBLconst(v) case OpAMD64SUBLload: return rewriteValueAMD64_OpAMD64SUBLload(v) case OpAMD64SUBLmodify: return rewriteValueAMD64_OpAMD64SUBLmodify(v) case OpAMD64SUBQ: return rewriteValueAMD64_OpAMD64SUBQ(v) case OpAMD64SUBQborrow: return rewriteValueAMD64_OpAMD64SUBQborrow(v) case OpAMD64SUBQconst: return rewriteValueAMD64_OpAMD64SUBQconst(v) case OpAMD64SUBQload: return rewriteValueAMD64_OpAMD64SUBQload(v) case OpAMD64SUBQmodify: return rewriteValueAMD64_OpAMD64SUBQmodify(v) case OpAMD64SUBSD: return rewriteValueAMD64_OpAMD64SUBSD(v) case OpAMD64SUBSDload: return rewriteValueAMD64_OpAMD64SUBSDload(v) case OpAMD64SUBSS: return rewriteValueAMD64_OpAMD64SUBSS(v) case OpAMD64SUBSSload: return rewriteValueAMD64_OpAMD64SUBSSload(v) case OpAMD64TESTB: return rewriteValueAMD64_OpAMD64TESTB(v) case OpAMD64TESTBconst: return rewriteValueAMD64_OpAMD64TESTBconst(v) case OpAMD64TESTL: return rewriteValueAMD64_OpAMD64TESTL(v) case OpAMD64TESTLconst: return rewriteValueAMD64_OpAMD64TESTLconst(v) case OpAMD64TESTQ: return rewriteValueAMD64_OpAMD64TESTQ(v) case OpAMD64TESTQconst: return rewriteValueAMD64_OpAMD64TESTQconst(v) case OpAMD64TESTW: return rewriteValueAMD64_OpAMD64TESTW(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock(v) case OpAMD64XADDQlock: return rewriteValueAMD64_OpAMD64XADDQlock(v) case OpAMD64XCHGL: return rewriteValueAMD64_OpAMD64XCHGL(v) case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ(v) case OpAMD64XORL: return rewriteValueAMD64_OpAMD64XORL(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst(v) case OpAMD64XORLconstmodify: return rewriteValueAMD64_OpAMD64XORLconstmodify(v) case OpAMD64XORLload: return rewriteValueAMD64_OpAMD64XORLload(v) case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify(v) case OpAMD64XORQ: return rewriteValueAMD64_OpAMD64XORQ(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst(v) case OpAMD64XORQconstmodify: return rewriteValueAMD64_OpAMD64XORQconstmodify(v) case OpAMD64XORQload: return rewriteValueAMD64_OpAMD64XORQload(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify(v) case OpAdd16: v.Op = OpAMD64ADDL return true case OpAdd32: v.Op = OpAMD64ADDL return true case OpAdd32F: v.Op = OpAMD64ADDSS return true case OpAdd64: v.Op = OpAMD64ADDQ return true case OpAdd64F: v.Op = OpAMD64ADDSD return true case OpAdd8: v.Op = OpAMD64ADDL return true case OpAddPtr: v.Op = OpAMD64ADDQ return true case OpAddr: return rewriteValueAMD64_OpAddr(v) case OpAnd16: v.Op = OpAMD64ANDL return true case OpAnd32: v.Op = OpAMD64ANDL return true case OpAnd64: v.Op = OpAMD64ANDQ return true case OpAnd8: v.Op = OpAMD64ANDL return true case OpAndB: v.Op = OpAMD64ANDL return true case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32(v) case OpAtomicAdd64: return rewriteValueAMD64_OpAtomicAdd64(v) case OpAtomicAnd32: return rewriteValueAMD64_OpAtomicAnd32(v) case OpAtomicAnd8: return rewriteValueAMD64_OpAtomicAnd8(v) case OpAtomicCompareAndSwap32: return rewriteValueAMD64_OpAtomicCompareAndSwap32(v) case OpAtomicCompareAndSwap64: return rewriteValueAMD64_OpAtomicCompareAndSwap64(v) case OpAtomicExchange32: return rewriteValueAMD64_OpAtomicExchange32(v) case OpAtomicExchange64: return rewriteValueAMD64_OpAtomicExchange64(v) case OpAtomicLoad32: return rewriteValueAMD64_OpAtomicLoad32(v) case OpAtomicLoad64: return rewriteValueAMD64_OpAtomicLoad64(v) case OpAtomicLoad8: return rewriteValueAMD64_OpAtomicLoad8(v) case OpAtomicLoadPtr: return rewriteValueAMD64_OpAtomicLoadPtr(v) case OpAtomicOr32: return rewriteValueAMD64_OpAtomicOr32(v) case OpAtomicOr8: return rewriteValueAMD64_OpAtomicOr8(v) case OpAtomicStore32: return rewriteValueAMD64_OpAtomicStore32(v) case OpAtomicStore64: return rewriteValueAMD64_OpAtomicStore64(v) case OpAtomicStore8: return rewriteValueAMD64_OpAtomicStore8(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB(v) case OpAvg64u: v.Op = OpAMD64AVGQU return true case OpBitLen16: return rewriteValueAMD64_OpBitLen16(v) case OpBitLen32: return rewriteValueAMD64_OpBitLen32(v) case OpBitLen64: return rewriteValueAMD64_OpBitLen64(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8(v) case OpBswap32: v.Op = OpAMD64BSWAPL return true case OpBswap64: v.Op = OpAMD64BSWAPQ return true case OpCeil: return rewriteValueAMD64_OpCeil(v) case OpClosureCall: v.Op = OpAMD64CALLclosure return true case OpCom16: v.Op = OpAMD64NOTL return true case OpCom32: v.Op = OpAMD64NOTL return true case OpCom64: v.Op = OpAMD64NOTQ return true case OpCom8: v.Op = OpAMD64NOTL return true case OpCondSelect: return rewriteValueAMD64_OpCondSelect(v) case OpConst16: return rewriteValueAMD64_OpConst16(v) case OpConst32: v.Op = OpAMD64MOVLconst return true case OpConst32F: v.Op = OpAMD64MOVSSconst return true case OpConst64: v.Op = OpAMD64MOVQconst return true case OpConst64F: v.Op = OpAMD64MOVSDconst return true case OpConst8: return rewriteValueAMD64_OpConst8(v) case OpConstBool: return rewriteValueAMD64_OpConstBool(v) case OpConstNil: return rewriteValueAMD64_OpConstNil(v) case OpCtz16: return rewriteValueAMD64_OpCtz16(v) case OpCtz16NonZero: return rewriteValueAMD64_OpCtz16NonZero(v) case OpCtz32: return rewriteValueAMD64_OpCtz32(v) case OpCtz32NonZero: return rewriteValueAMD64_OpCtz32NonZero(v) case OpCtz64: return rewriteValueAMD64_OpCtz64(v) case OpCtz64NonZero: return rewriteValueAMD64_OpCtz64NonZero(v) case OpCtz8: return rewriteValueAMD64_OpCtz8(v) case OpCtz8NonZero: return rewriteValueAMD64_OpCtz8NonZero(v) case OpCvt32Fto32: v.Op = OpAMD64CVTTSS2SL return true case OpCvt32Fto64: v.Op = OpAMD64CVTTSS2SQ return true case OpCvt32Fto64F: v.Op = OpAMD64CVTSS2SD return true case OpCvt32to32F: v.Op = OpAMD64CVTSL2SS return true case OpCvt32to64F: v.Op = OpAMD64CVTSL2SD return true case OpCvt64Fto32: v.Op = OpAMD64CVTTSD2SL return true case OpCvt64Fto32F: v.Op = OpAMD64CVTSD2SS return true case OpCvt64Fto64: v.Op = OpAMD64CVTTSD2SQ return true case OpCvt64to32F: v.Op = OpAMD64CVTSQ2SS return true case OpCvt64to64F: v.Op = OpAMD64CVTSQ2SD return true case OpCvtBoolToUint8: v.Op = OpCopy return true case OpDiv128u: v.Op = OpAMD64DIVQU2 return true case OpDiv16: return rewriteValueAMD64_OpDiv16(v) case OpDiv16u: return rewriteValueAMD64_OpDiv16u(v) case OpDiv32: return rewriteValueAMD64_OpDiv32(v) case OpDiv32F: v.Op = OpAMD64DIVSS return true case OpDiv32u: return rewriteValueAMD64_OpDiv32u(v) case OpDiv64: return rewriteValueAMD64_OpDiv64(v) case OpDiv64F: v.Op = OpAMD64DIVSD return true case OpDiv64u: return rewriteValueAMD64_OpDiv64u(v) case OpDiv8: return rewriteValueAMD64_OpDiv8(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u(v) case OpEq16: return rewriteValueAMD64_OpEq16(v) case OpEq32: return rewriteValueAMD64_OpEq32(v) case OpEq32F: return rewriteValueAMD64_OpEq32F(v) case OpEq64: return rewriteValueAMD64_OpEq64(v) case OpEq64F: return rewriteValueAMD64_OpEq64F(v) case OpEq8: return rewriteValueAMD64_OpEq8(v) case OpEqB: return rewriteValueAMD64_OpEqB(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr(v) case OpFMA: return rewriteValueAMD64_OpFMA(v) case OpFloor: return rewriteValueAMD64_OpFloor(v) case OpGetCallerPC: v.Op = OpAMD64LoweredGetCallerPC return true case OpGetCallerSP: v.Op = OpAMD64LoweredGetCallerSP return true case OpGetClosurePtr: v.Op = OpAMD64LoweredGetClosurePtr return true case OpGetG: return rewriteValueAMD64_OpGetG(v) case OpHasCPUFeature: return rewriteValueAMD64_OpHasCPUFeature(v) case OpHmul32: v.Op = OpAMD64HMULL return true case OpHmul32u: v.Op = OpAMD64HMULLU return true case OpHmul64: v.Op = OpAMD64HMULQ return true case OpHmul64u: v.Op = OpAMD64HMULQU return true case OpInterCall: v.Op = OpAMD64CALLinter return true case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueAMD64_OpIsSliceInBounds(v) case OpLeq16: return rewriteValueAMD64_OpLeq16(v) case OpLeq16U: return rewriteValueAMD64_OpLeq16U(v) case OpLeq32: return rewriteValueAMD64_OpLeq32(v) case OpLeq32F: return rewriteValueAMD64_OpLeq32F(v) case OpLeq32U: return rewriteValueAMD64_OpLeq32U(v) case OpLeq64: return rewriteValueAMD64_OpLeq64(v) case OpLeq64F: return rewriteValueAMD64_OpLeq64F(v) case OpLeq64U: return rewriteValueAMD64_OpLeq64U(v) case OpLeq8: return rewriteValueAMD64_OpLeq8(v) case OpLeq8U: return rewriteValueAMD64_OpLeq8U(v) case OpLess16: return rewriteValueAMD64_OpLess16(v) case OpLess16U: return rewriteValueAMD64_OpLess16U(v) case OpLess32: return rewriteValueAMD64_OpLess32(v) case OpLess32F: return rewriteValueAMD64_OpLess32F(v) case OpLess32U: return rewriteValueAMD64_OpLess32U(v) case OpLess64: return rewriteValueAMD64_OpLess64(v) case OpLess64F: return rewriteValueAMD64_OpLess64F(v) case OpLess64U: return rewriteValueAMD64_OpLess64U(v) case OpLess8: return rewriteValueAMD64_OpLess8(v) case OpLess8U: return rewriteValueAMD64_OpLess8U(v) case OpLoad: return rewriteValueAMD64_OpLoad(v) case OpLocalAddr: return rewriteValueAMD64_OpLocalAddr(v) case OpLsh16x16: return rewriteValueAMD64_OpLsh16x16(v) case OpLsh16x32: return rewriteValueAMD64_OpLsh16x32(v) case OpLsh16x64: return rewriteValueAMD64_OpLsh16x64(v) case OpLsh16x8: return rewriteValueAMD64_OpLsh16x8(v) case OpLsh32x16: return rewriteValueAMD64_OpLsh32x16(v) case OpLsh32x32: return rewriteValueAMD64_OpLsh32x32(v) case OpLsh32x64: return rewriteValueAMD64_OpLsh32x64(v) case OpLsh32x8: return rewriteValueAMD64_OpLsh32x8(v) case OpLsh64x16: return rewriteValueAMD64_OpLsh64x16(v) case OpLsh64x32: return rewriteValueAMD64_OpLsh64x32(v) case OpLsh64x64: return rewriteValueAMD64_OpLsh64x64(v) case OpLsh64x8: return rewriteValueAMD64_OpLsh64x8(v) case OpLsh8x16: return rewriteValueAMD64_OpLsh8x16(v) case OpLsh8x32: return rewriteValueAMD64_OpLsh8x32(v) case OpLsh8x64: return rewriteValueAMD64_OpLsh8x64(v) case OpLsh8x8: return rewriteValueAMD64_OpLsh8x8(v) case OpMod16: return rewriteValueAMD64_OpMod16(v) case OpMod16u: return rewriteValueAMD64_OpMod16u(v) case OpMod32: return rewriteValueAMD64_OpMod32(v) case OpMod32u: return rewriteValueAMD64_OpMod32u(v) case OpMod64: return rewriteValueAMD64_OpMod64(v) case OpMod64u: return rewriteValueAMD64_OpMod64u(v) case OpMod8: return rewriteValueAMD64_OpMod8(v) case OpMod8u: return rewriteValueAMD64_OpMod8u(v) case OpMove: return rewriteValueAMD64_OpMove(v) case OpMul16: v.Op = OpAMD64MULL return true case OpMul32: v.Op = OpAMD64MULL return true case OpMul32F: v.Op = OpAMD64MULSS return true case OpMul64: v.Op = OpAMD64MULQ return true case OpMul64F: v.Op = OpAMD64MULSD return true case OpMul64uhilo: v.Op = OpAMD64MULQU2 return true case OpMul8: v.Op = OpAMD64MULL return true case OpNeg16: v.Op = OpAMD64NEGL return true case OpNeg32: v.Op = OpAMD64NEGL return true case OpNeg32F: return rewriteValueAMD64_OpNeg32F(v) case OpNeg64: v.Op = OpAMD64NEGQ return true case OpNeg64F: return rewriteValueAMD64_OpNeg64F(v) case OpNeg8: v.Op = OpAMD64NEGL return true case OpNeq16: return rewriteValueAMD64_OpNeq16(v) case OpNeq32: return rewriteValueAMD64_OpNeq32(v) case OpNeq32F: return rewriteValueAMD64_OpNeq32F(v) case OpNeq64: return rewriteValueAMD64_OpNeq64(v) case OpNeq64F: return rewriteValueAMD64_OpNeq64F(v) case OpNeq8: return rewriteValueAMD64_OpNeq8(v) case OpNeqB: return rewriteValueAMD64_OpNeqB(v) case OpNeqPtr: return rewriteValueAMD64_OpNeqPtr(v) case OpNilCheck: v.Op = OpAMD64LoweredNilCheck return true case OpNot: return rewriteValueAMD64_OpNot(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr(v) case OpOr16: v.Op = OpAMD64ORL return true case OpOr32: v.Op = OpAMD64ORL return true case OpOr64: v.Op = OpAMD64ORQ return true case OpOr8: v.Op = OpAMD64ORL return true case OpOrB: v.Op = OpAMD64ORL return true case OpPanicBounds: return rewriteValueAMD64_OpPanicBounds(v) case OpPopCount16: return rewriteValueAMD64_OpPopCount16(v) case OpPopCount32: v.Op = OpAMD64POPCNTL return true case OpPopCount64: v.Op = OpAMD64POPCNTQ return true case OpPopCount8: return rewriteValueAMD64_OpPopCount8(v) case OpPrefetchCache: v.Op = OpAMD64PrefetchT0 return true case OpPrefetchCacheStreamed: v.Op = OpAMD64PrefetchNTA return true case OpRotateLeft16: v.Op = OpAMD64ROLW return true case OpRotateLeft32: v.Op = OpAMD64ROLL return true case OpRotateLeft64: v.Op = OpAMD64ROLQ return true case OpRotateLeft8: v.Op = OpAMD64ROLB return true case OpRound32F: v.Op = OpCopy return true case OpRound64F: v.Op = OpCopy return true case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven(v) case OpRsh16Ux16: return rewriteValueAMD64_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValueAMD64_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValueAMD64_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValueAMD64_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValueAMD64_OpRsh16x16(v) case OpRsh16x32: return rewriteValueAMD64_OpRsh16x32(v) case OpRsh16x64: return rewriteValueAMD64_OpRsh16x64(v) case OpRsh16x8: return rewriteValueAMD64_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValueAMD64_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValueAMD64_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValueAMD64_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValueAMD64_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValueAMD64_OpRsh32x16(v) case OpRsh32x32: return rewriteValueAMD64_OpRsh32x32(v) case OpRsh32x64: return rewriteValueAMD64_OpRsh32x64(v) case OpRsh32x8: return rewriteValueAMD64_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValueAMD64_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValueAMD64_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValueAMD64_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValueAMD64_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValueAMD64_OpRsh64x16(v) case OpRsh64x32: return rewriteValueAMD64_OpRsh64x32(v) case OpRsh64x64: return rewriteValueAMD64_OpRsh64x64(v) case OpRsh64x8: return rewriteValueAMD64_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValueAMD64_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValueAMD64_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValueAMD64_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValueAMD64_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValueAMD64_OpRsh8x16(v) case OpRsh8x32: return rewriteValueAMD64_OpRsh8x32(v) case OpRsh8x64: return rewriteValueAMD64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8(v) case OpSelect0: return rewriteValueAMD64_OpSelect0(v) case OpSelect1: return rewriteValueAMD64_OpSelect1(v) case OpSelectN: return rewriteValueAMD64_OpSelectN(v) case OpSignExt16to32: v.Op = OpAMD64MOVWQSX return true case OpSignExt16to64: v.Op = OpAMD64MOVWQSX return true case OpSignExt32to64: v.Op = OpAMD64MOVLQSX return true case OpSignExt8to16: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to32: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to64: v.Op = OpAMD64MOVBQSX return true case OpSlicemask: return rewriteValueAMD64_OpSlicemask(v) case OpSpectreIndex: return rewriteValueAMD64_OpSpectreIndex(v) case OpSpectreSliceIndex: return rewriteValueAMD64_OpSpectreSliceIndex(v) case OpSqrt: v.Op = OpAMD64SQRTSD return true case OpSqrt32: v.Op = OpAMD64SQRTSS return true case OpStaticCall: v.Op = OpAMD64CALLstatic return true case OpStore: return rewriteValueAMD64_OpStore(v) case OpSub16: v.Op = OpAMD64SUBL return true case OpSub32: v.Op = OpAMD64SUBL return true case OpSub32F: v.Op = OpAMD64SUBSS return true case OpSub64: v.Op = OpAMD64SUBQ return true case OpSub64F: v.Op = OpAMD64SUBSD return true case OpSub8: v.Op = OpAMD64SUBL return true case OpSubPtr: v.Op = OpAMD64SUBQ return true case OpTailCall: v.Op = OpAMD64CALLtail return true case OpTrunc: return rewriteValueAMD64_OpTrunc(v) case OpTrunc16to8: v.Op = OpCopy return true case OpTrunc32to16: v.Op = OpCopy return true case OpTrunc32to8: v.Op = OpCopy return true case OpTrunc64to16: v.Op = OpCopy return true case OpTrunc64to32: v.Op = OpCopy return true case OpTrunc64to8: v.Op = OpCopy return true case OpWB: v.Op = OpAMD64LoweredWB return true case OpXor16: v.Op = OpAMD64XORL return true case OpXor32: v.Op = OpAMD64XORL return true case OpXor64: v.Op = OpAMD64XORQ return true case OpXor8: v.Op = OpAMD64XORL return true case OpZero: return rewriteValueAMD64_OpZero(v) case OpZeroExt16to32: v.Op = OpAMD64MOVWQZX return true case OpZeroExt16to64: v.Op = OpAMD64MOVWQZX return true case OpZeroExt32to64: v.Op = OpAMD64MOVLQZX return true case OpZeroExt8to16: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to32: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to64: v.Op = OpAMD64MOVBQZX return true } return false } func rewriteValueAMD64_OpAMD64ADCQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) // result: (ADCQconst x [int32(c)] carry) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) carry := v_2 if !(is32Bit(c)) { continue } v.reset(OpAMD64ADCQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, carry) return true } break } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQcarry) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64ADCQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQconst x [c] (FlagEQ)) // result: (ADDQconstcarry x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDL x (MOVLconst [c])) // result: (ADDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRLconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRWconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRBconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAL2) v.AddArg2(y, x) return true } } break } // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAL { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL { continue } y := v_1.Args[0] v.reset(OpAMD64SUBL) v.AddArg2(x, y) return true } break } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDLconst [c] (ADDL x y)) // result: (LEAL1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (SHLLconst [1] x)) // result: (LEAL1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // result: (MOVLconst [c+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c + d) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // result: (ADDLconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDLconst [off] x:(SP)) // result: (LEAL [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (ADDL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ADDQ x (MOVLconst [c])) // result: (ADDQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRQconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAQ2) v.AddArg2(y, x) return true } } break } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ { continue } y := v_1.Args[0] v.reset(OpAMD64SUBQ) v.AddArg2(x, y) return true } break } // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQcarry(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQcarry x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconstcarry x [int32(c)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDQconst [c] (ADDQ x y)) // result: (LEAQ1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (SHLQconst [1] x)) // result: (LEAQ1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDQconst [c] (LEAQ [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ADDQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) + d) return true } // match: (ADDQconst [c] (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (ADDQconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDQconst [off] x:(SP)) // result: (LEAQ [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (ADDQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (ADDSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (ADDSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ANDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTRL) v.AddArg2(x, y) return true } break } // match: (ANDL (NOTL (SHLXL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLXL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTRL) v.AddArg2(x, y) return true } break } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } break } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ANDL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDL x (NOTL y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTL { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNL) v.AddArg2(x, y) return true } break } // match: (ANDL x (NEGL x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIL) v.AddArg(x) return true } break } // match: (ANDL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSRL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSRL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDLconst [c] x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDLconst [c] (BTRLconst [d] x)) // result: (ANDLconst [c &^ (1<= 128 // result: (BTRQconst [int8(log64(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log64(^c))) v.AddArg(x) return true } break } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ANDQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDQ x (NOTQ y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTQ { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNQ) v.AddArg2(x, y) return true } break } // match: (ANDQ x (NEGQ x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIQ) v.AddArg(x) return true } break } // match: (ANDQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSRQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSRQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDQconst [c] x) // cond: isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRQconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDQconst [c] (ANDQconst [d] x)) // result: (ANDQconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDQconst [c] (BTRQconst [d] x)) // cond: is32Bit(int64(c) &^ (1< [1<<8] (MOVBQZX x))) // result: (BSFQ (ORQconst [1<<8] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVBQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 8) v0.AddArg(x) v.AddArg(v0) return true } // match: (BSFQ (ORQconst [1<<16] (MOVWQZX x))) // result: (BSFQ (ORQconst [1<<16] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVWQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPL(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPL (BSWAPL p)) // result: p for { if v_0.Op != OpAMD64BSWAPL { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPL x:(MOVLload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPL (MOVBELload [i] {s} p m)) // result: (MOVLload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBELload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPQ(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPQ (BSWAPQ p)) // result: p for { if v_0.Op != OpAMD64BSWAPQ { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPQ x:(MOVQload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPQ (MOVBEQload [i] {s} p m)) // result: (MOVQload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBEQload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BTCLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTCLconst [c] (XORLconst [d] x)) // result: (XORLconst [d ^ 1<d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTLconst [0] s:(SHRXQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 32) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTLconst [c] (SHLLconst [d] x)) // cond: c>d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } // match: (BTLconst [0] s:(SHRXL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTQconst(v *Value) bool { v_0 := v.Args[0] // match: (BTQconst [c] (SHRQconst [d] x)) // cond: (c+d)<64 // result: (BTQconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 64) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTQconst [c] (SHLQconst [d] x)) // cond: c>d // result: (BTQconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTQconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTQconst [0] s:(SHRXQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTRLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTRLconst [c] (BTSLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTSLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (BTCLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTCLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [d &^ (1<uint8(y) // result: (FlagLT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) < y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x) y && uint8(x) < uint8(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) > y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int8(m) && int8(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPBconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTB x y) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, y) return true } // match: (CMPBconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTBconst [int8(c)] x) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt8(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVBload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPBload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPL x (MOVLconst [c])) // result: (CMPLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64CMPLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // result: (InvertFlags (CMPLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPL y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x==y // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x == y) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: xuint32(y) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x < y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x) y && uint32(x) < uint32(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x > y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) // result: (FlagLT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x < y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x)>uint64(y) // result: (FlagGT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x > y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQ l:(MOVQload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPQload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPQ x l:(MOVQload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPQload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPQload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPQconst (NEGQ (ADDQconst [-16] (ANDQconst [15] _))) [32]) // result: (FlagLT_ULT) for { if auxIntToInt32(v.AuxInt) != 32 || v_0.Op != OpAMD64NEGQ { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_0_0.AuxInt) != -16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_0_0.AuxInt) != 15 { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (NEGQ (ADDQconst [ -8] (ANDQconst [7] _))) [32]) // result: (FlagLT_ULT) for { if auxIntToInt32(v.AuxInt) != 32 || v_0.Op != OpAMD64NEGQ { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_0_0.AuxInt) != -8 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_0_0.AuxInt) != 7 { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x==int64(y) // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x == int64(y)) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: xuint64(int64(y)) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x < int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x) int64(y) && uint64(x) < uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x)>uint64(int64(y)) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x > int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQconst (MOVBQZX _) [c]) // cond: 0xFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVWQZX _) [c]) // cond: 0xFFFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (SHRQconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 64 && (1<uint16(y) // result: (FlagLT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) < y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x) y && uint16(x) < uint16(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) > y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int16(m) && int16(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPWconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTW x y) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, y) return true } // match: (CMPWconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTWconst [int16(c)] x) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt16(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVWload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPWload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGLlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGQlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64HMULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULL x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULL y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULLU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULLU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULLU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULLU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQ x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQ y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64LEAL(v *Value) bool { v_0 := v.Args[0] // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { v_0 := v.Args[0] // match: (LEAQ [c] {s} (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAQ [c] {s} (ADDQ x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg(x) return true } // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ2 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ4 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ8 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64LEAQ { continue } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(y, x) return true } } break } // match: (LEAQ1 [0] x y) // cond: v.Aux == nil // result: (ADDQ x y) for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 y := v_1 if !(v.Aux == nil) { break } v.reset(OpAMD64ADDQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAQ2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil // result: (LEAQ4 [off1+2*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + 2*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ2 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ2 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAQ4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil // result: (LEAQ8 [off1+4*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + 4*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ4 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ4 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAQ8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ8 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ8 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBELstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBELstore [i] {s} p (BSWAPL x) m) // result: (MOVLstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPL { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEQstore [i] {s} p (BSWAPQ x) m) // result: (MOVQstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPQ { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7f) v.AddArg(x) return true } // match: (MOVBQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x) // cond: zeroUpper56Bits(x,3) // result: x for { x := v_0 if !(zeroUpper56Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVBQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xff) v.AddArg(x) return true } // match: (MOVBQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read8(sym, int64(off)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read8(sym, int64(off)))) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) // cond: y.Uses == 1 // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETL { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) // cond: y.Uses == 1 // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETLE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) // cond: y.Uses == 1 // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETG { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) // cond: y.Uses == 1 // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETGE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) // cond: y.Uses == 1 // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETEQ { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) // cond: y.Uses == 1 // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETNE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) // cond: y.Uses == 1 // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETB { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) // cond: y.Uses == 1 // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETBE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) // cond: y.Uses == 1 // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETA { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) // cond: y.Uses == 1 // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETAE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstore [i-1] {s} p (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p1 w x0:(MOVBstore [i] {s} p0 (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0) // result: (MOVWstore [i] {s} p0 (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-1 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-3 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 3) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p3 w x2:(MOVBstore [i] {s} p2 (SHRLconst [8] w) x1:(MOVBstore [i] {s} p1 (SHRLconst [16] w) x0:(MOVBstore [i] {s} p0 (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2) // result: (MOVLstore [i] {s} p0 (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p3 := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i-1 || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] if p != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i-2 || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i-3 || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i-4 || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-5 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-6 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-7 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 7) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p7 w x6:(MOVBstore [i] {s} p6 (SHRQconst [8] w) x5:(MOVBstore [i] {s} p5 (SHRQconst [16] w) x4:(MOVBstore [i] {s} p4 (SHRQconst [24] w) x3:(MOVBstore [i] {s} p3 (SHRQconst [32] w) x2:(MOVBstore [i] {s} p2 (SHRQconst [40] w) x1:(MOVBstore [i] {s} p1 (SHRQconst [48] w) x0:(MOVBstore [i] {s} p0 (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i] {s} p0 (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p7 := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] p6 := x6.Args[0] x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] p5 := x5.Args[0] x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] p4 := x4.Args[0] x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] p3 := x3.Args[0] x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRWconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [c3] {s} p3 (SHRQconst [56] w) x1:(MOVWstore [c2] {s} p2 (SHRQconst [40] w) x2:(MOVLstore [c1] {s} p1 (SHRQconst [8] w) x3:(MOVBstore [c0] {s} p0 w mem)))) // cond: x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1 + c0 - c1)) && sequentialAddresses(p0, p2, int64(5 + c0 - c2)) && sequentialAddresses(p0, p3, int64(7 + c0 - c3)) && clobber(x1, x2, x3) // result: (MOVQstore [c0] {s} p0 w mem) for { c3 := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p3 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 56 { break } w := v_1.Args[0] x1 := v_2 if x1.Op != OpAMD64MOVWstore { break } c2 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p2 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 40 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpAMD64MOVLstore { break } c1 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p1 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpAMD64MOVBstore { break } c0 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { break } mem := x3.Args[2] p0 := x3.Args[0] if w != x3.Args[1] || !(x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1+c0-c1)) && sequentialAddresses(p0, p2, int64(5+c0-c2)) && sequentialAddresses(p0, p3, int64(7+c0-c3)) && clobber(x1, x2, x3)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(c0) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVBload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVBstore || auxIntToInt32(mem2.AuxInt) != i-1 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVBload || auxIntToInt32(x2.AuxInt) != j-1 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(j - 1) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [c] {s} p1 x:(MOVBstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVBstoreconst [a] {s} p0 x:(MOVBstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX (ANDLconst [c] x)) // cond: uint32(c) & 0x80000000 == 0 // result: (ANDLconst [c & 0x7fffffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(uint32(c)&0x80000000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fffffff) v.AddArg(x) return true } // match: (MOVLQSX (MOVLQSX x)) // result: (MOVLQSX x) for { if v_0.Op != OpAMD64MOVLQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x) // cond: zeroUpper32Bits(x,3) // result: x for { x := v_0 if !(zeroUpper32Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVLQZX (ANDLconst [c] x)) // result: (ANDLconst [c] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (MOVLQZX (MOVLQZX x)) // result: (MOVLQZX x) for { if v_0.Op != OpAMD64MOVLQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLf2i) v.AddArg(val) return true } // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [32] w) x:(MOVLstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [j] w) x:(MOVLstore [i] {s} p0 w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVLload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVLstore || auxIntToInt32(mem2.AuxInt) != i-4 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVLload || auxIntToInt32(x2.AuxInt) != j-4 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(j - 4) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) // result: (MOVSSstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [i] {s} p x:(BSWAPL w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPL { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [c] {s} p1 x:(MOVLstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p0, v0, mem) return true } // match: (MOVLstoreconst [a] {s} p0 x:(MOVLstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p0, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) // cond: symIsRO(srcSym) // result: (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))]) (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))]) mem)) for { dstOff := auxIntToInt32(v.AuxInt) dstSym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVOload { break } srcOff := auxIntToInt32(v_1.AuxInt) srcSym := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } mem := v_2 if !(symIsRO(srcSym)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(dstOff + 8) v.Aux = symToAux(dstSym) v0 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))) v1 := b.NewValue0(v_1.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AuxInt = int32ToAuxInt(dstOff) v1.Aux = symToAux(dstSym) v2 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))) v1.AddArg3(ptr, v2, mem) v.AddArg3(ptr, v0, v1) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVOstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.copyOf(x) return true } // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) // result: (MOVQf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQf2i) v.AddArg(val) return true } // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validVal(c) // result: (MOVQstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(validVal(c)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) // result: (MOVSDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [i] {s} p x:(BSWAPQ w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPQ { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [c] {s} p1 x:(MOVQstoreconst [a] {s} p0 mem)) // cond: config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVQstoreconst [a] {s} p0 x:(MOVQstoreconst [c] {s} p1 mem)) // cond: config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fff) v.AddArg(x) return true } // match: (MOVWQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x) // cond: zeroUpper48Bits(x,3) // result: x for { x := v_0 if !(zeroUpper48Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVWQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xffff) v.AddArg(x) return true } // match: (MOVWQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVWload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVWstore || auxIntToInt32(mem2.AuxInt) != i-2 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVWload || auxIntToInt32(x2.AuxInt) != j-2 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(j - 2) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [c] {s} p1 x:(MOVWstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVWstoreconst [a] {s} p0 x:(MOVWstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULL x (MOVLconst [c])) // result: (MULLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULLconst [c] (MULLconst [d] x)) // result: (MULLconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULLconst [-9] x) // result: (NEGL (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // result: (NEGL (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // result: (NEGL (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // result: (NEGL x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGL) v.AddArg(x) return true } // match: (MULLconst [ 0] _) // result: (MOVLconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (MULLconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULLconst [ 3] x) // result: (LEAL2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAL2) v.AddArg2(x, x) return true } // match: (MULLconst [ 5] x) // result: (LEAL4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAL4) v.AddArg2(x, x) return true } // match: (MULLconst [ 7] x) // result: (LEAL2 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [ 9] x) // result: (LEAL8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAL8) v.AddArg2(x, x) return true } // match: (MULLconst [11] x) // result: (LEAL2 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [13] x) // result: (LEAL4 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [19] x) // result: (LEAL2 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [21] x) // result: (LEAL4 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [25] x) // result: (LEAL8 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [27] x) // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [37] x) // result: (LEAL4 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [41] x) // result: (LEAL8 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [45] x) // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [73] x) // result: (LEAL8 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [81] x) // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBL (SHLLconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAL1) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLLconst [int8(log32(c/3))] (LEAL2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLLconst [int8(log32(c/5))] (LEAL4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLLconst [int8(log32(c/9))] (LEAL8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] (MOVLconst [d])) // result: (MOVLconst [c*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c * d) return true } return false } func rewriteValueAMD64_OpAMD64MULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (MULQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULQconst [c] (MULQconst [d] x)) // cond: is32Bit(int64(c)*int64(d)) // result: (MULQconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) * int64(d))) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULQconst [-9] x) // result: (NEGQ (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-5] x) // result: (NEGQ (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-3] x) // result: (NEGQ (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-1] x) // result: (NEGQ x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGQ) v.AddArg(x) return true } // match: (MULQconst [ 0] _) // result: (MOVQconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MULQconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULQconst [ 3] x) // result: (LEAQ2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAQ2) v.AddArg2(x, x) return true } // match: (MULQconst [ 5] x) // result: (LEAQ4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAQ4) v.AddArg2(x, x) return true } // match: (MULQconst [ 7] x) // result: (LEAQ2 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [ 9] x) // result: (LEAQ8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAQ8) v.AddArg2(x, x) return true } // match: (MULQconst [11] x) // result: (LEAQ2 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [13] x) // result: (LEAQ4 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [19] x) // result: (LEAQ2 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [21] x) // result: (LEAQ4 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [25] x) // result: (LEAQ8 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [27] x) // result: (LEAQ8 (LEAQ2 x x) (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [37] x) // result: (LEAQ4 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [41] x) // result: (LEAQ8 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [45] x) // result: (LEAQ8 (LEAQ4 x x) (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [73] x) // result: (LEAQ8 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [81] x) // result: (LEAQ8 (LEAQ8 x x) (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBQ (SHLQconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAQ1 (SHLQconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAQ1) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAQ2 (SHLQconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAQ4 (SHLQconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAQ8 (SHLQconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLQconst [int8(log32(c/3))] (LEAQ2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLQconst [int8(log32(c/5))] (LEAQ4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLQconst [int8(log32(c/9))] (LEAQ8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) * d) return true } // match: (MULQconst [c] (NEGQ x)) // cond: c != -(1<<31) // result: (MULQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (MULSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64MULSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (MULSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64NEGL(v *Value) bool { v_0 := v.Args[0] // match: (NEGL (NEGL x)) // result: x for { if v_0.Op != OpAMD64NEGL { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGL s:(SUBL x y)) // cond: s.Uses == 1 // result: (SUBL y x) for { s := v_0 if s.Op != OpAMD64SUBL { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBL) v.AddArg2(y, x) return true } // match: (NEGL (MOVLconst [c])) // result: (MOVLconst [-c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-c) return true } return false } func rewriteValueAMD64_OpAMD64NEGQ(v *Value) bool { v_0 := v.Args[0] // match: (NEGQ (NEGQ x)) // result: x for { if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGQ s:(SUBQ x y)) // cond: s.Uses == 1 // result: (SUBQ y x) for { s := v_0 if s.Op != OpAMD64SUBQ { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBQ) v.AddArg2(y, x) return true } // match: (NEGQ (MOVQconst [c])) // result: (MOVQconst [-c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-c) return true } // match: (NEGQ (ADDQconst [c] (NEGQ x))) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { if v_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } x := v_0_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64NOTL(v *Value) bool { v_0 := v.Args[0] // match: (NOTL (MOVLconst [c])) // result: (MOVLconst [^c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64NOTQ(v *Value) bool { v_0 := v.Args[0] // match: (NOTQ (MOVQconst [c])) // result: (MOVQconst [^c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64ORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTSL) v.AddArg2(x, y) return true } break } // match: (ORL (SHLXL (MOVLconst [1]) y) x) // result: (BTSL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTSL) v.AddArg2(x, y) return true } break } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRLconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRWconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRBconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (RORL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (RORL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLXL x y) (ANDL (SHRXL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRXL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLXL x y) (ANDL (SHRXL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRXL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRXL x y) (ANDL (SHLXL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (RORL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRXL x y) (ANDL (SHLXL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (RORL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRW x (ANDQconst y [15])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg2(x, y) return true } break } // match: (ORL (SHRW x (ANDLconst y [15])) (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg2(x, y) return true } break } // match: (ORL (SHLXL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLXL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRW x (ANDQconst y [15])) (SHLXL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLXL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg2(x, y) return true } break } // match: (ORL (SHRW x (ANDLconst y [15])) (SHLXL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLXL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg2(x, y) return true } break } // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg2(x, y) return true } break } // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg2(x, y) return true } break } // match: (ORL (SHLXL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLXL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLXL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLXL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg2(x, y) return true } break } // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLXL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLXL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg2(x, y) return true } break } // match: (ORL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORL x0:(MOVBload [i0] {s} p mem) sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVBload [i] {s} p0 mem) sh:(SHLLconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVWload [i] {s} p0 mem) sh:(SHLLconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL x1:(MOVBload [i] {s} p1 mem) sh:(SHLLconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORLconst(v *Value) bool { v_0 := v.Args[0] // match: (ORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORLconst [c] (ORLconst [d] x)) // result: (ORLconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORLconst [c] (BTSLconst [d] x)) // result: (ORLconst [c | 1<= 128 // result: (BTSQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ORQ x (MOVLconst [c])) // result: (ORQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRQconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHLXQ x y) (ANDQ (SHRXQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRXQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHLXQ x y) (ANDQ (SHRXQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRXQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHRXQ x y) (ANDQ (SHLXQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHRXQ x y) (ANDQ (SHLXQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHRQ lo bits) (SHLQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLQ lo bits) (SHRQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHRXQ lo bits) (SHLXQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLXQ lo bits) (SHRXQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (MOVQconst [c]) (MOVQconst [d])) // result: (MOVQconst [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c | d) return true } break } // match: (ORQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORQ x0:(MOVBload [i0] {s} p mem) sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBload [i] {s} p0 mem) sh:(SHLQconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVWload [i] {s} p0 mem) sh:(SHLQconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVLload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVLload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i] {s} p0 mem)) y)) // cond: j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ x1:(MOVBload [i] {s} p1 mem) sh:(SHLQconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i] {s} p1 mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem))) y)) // cond: j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ORQ x0:(MOVBELload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVBELload [i1] {s} p mem))) // cond: i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i1] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i1) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBELload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVBELload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i] {s} p1 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p1, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQconst(v *Value) bool { v_0 := v.Args[0] // match: (ORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORQconst [c] (ORQconst [d] x)) // result: (ORQconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORQconst [c] (BTSQconst [d] x)) // cond: is32Bit(int64(c) | 1<>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int8(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARL x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SARXL x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (MOVLconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SARLconst(v *Value) bool { v_0 := v.Args[0] // match: (SARLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARLconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int32(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int32(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SARXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (MOVLconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SARQconst(v *Value) bool { v_0 := v.Args[0] // match: (SARQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARQconst [c] (MOVQconst [d])) // result: (MOVQconst [d>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SARW x (MOVQconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } // match: (SARW x (MOVLconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SARWconst(v *Value) bool { v_0 := v.Args[0] // match: (SARWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARWconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int16(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int16(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARXL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARXL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARXL x (MOVLconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARXL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SARXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SARXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SARLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARXQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARXQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARXQ x (MOVLconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARXQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SARXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SARXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SARXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SBBLcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBLcarrymask (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagLT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagGT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQ x (MOVQconst [c]) borrow) // cond: is32Bit(c) // result: (SBBQconst x [int32(c)] borrow) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) borrow := v_2 if !(is32Bit(c)) { break } v.reset(OpAMD64SBBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, borrow) return true } // match: (SBBQ x y (FlagEQ)) // result: (SUBQborrow x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQborrow) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64SBBQcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBQcarrymask (FlagEQ)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagLT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagLT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagGT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagGT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQconst x [c] (FlagEQ)) // result: (SUBQconstborrow x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SETA(v *Value) bool { v_0 := v.Args[0] // match: (SETA (InvertFlags x)) // result: (SETB x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETA (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAE(v *Value) bool { v_0 := v.Args[0] // match: (SETAE (TESTQ x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTL x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTW x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTB x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (InvertFlags x)) // result: (SETBE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETAstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETB(v *Value) bool { v_0 := v.Args[0] // match: (SETB (TESTQ x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTL x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTW x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTB x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (BTLconst [0] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64BTLconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (BTQconst [0] x)) // result: (ANDQconst [1] x) for { if v_0.Op != OpAMD64BTQconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (InvertFlags x)) // result: (SETA x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBE(v *Value) bool { v_0 := v.Args[0] // match: (SETBE (InvertFlags x)) // result: (SETAE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETBE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAE (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAE (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETNE (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETEQ (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETEQstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETG(v *Value) bool { v_0 := v.Args[0] // match: (SETG (InvertFlags x)) // result: (SETL x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETG (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGE(v *Value) bool { v_0 := v.Args[0] // match: (SETGE (InvertFlags x)) // result: (SETLE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETL(v *Value) bool { v_0 := v.Args[0] // match: (SETL (InvertFlags x)) // result: (SETG x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLE(v *Value) bool { v_0 := v.Args[0] // match: (SETLE (InvertFlags x)) // result: (SETGE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETLE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNE(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETNE (TESTBconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTBconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTWconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTWconst || auxIntToInt16(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETB (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETB (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETEQ (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (InvertFlags x)) // result: (SETNE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETNE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETNEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLL x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHLXL x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (MOVLconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLLconst [1] (SHRLconst [1] x)) // result: (BTRLconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLLconst [d] (MOVLconst [c])) // result: (MOVLconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHLXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (MOVLconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLQconst [1] (SHRQconst [1] x)) // result: (BTRQconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLQconst [d] (MOVQconst [c])) // result: (MOVQconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c << uint64(d)) return true } // match: (SHLQconst [d] (MOVLconst [c])) // result: (MOVQconst [int64(c) << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLXL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLXL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLXL x (MOVLconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLXL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHLXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHLXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHLLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLXQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLXQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLXQ x (MOVLconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLXQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHLXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHLXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SHLXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRB x (MOVQconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB _ (MOVQconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRBconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRBconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRL x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHRXL x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (MOVLconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRLconst [1] (SHLLconst [1] x)) // result: (BTRLconst [31] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(31) v.AddArg(x) return true } // match: (SHRLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHRXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (MOVLconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRQconst [1] (SHLQconst [1] x)) // result: (BTRQconst [63] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(63) v.AddArg(x) return true } // match: (SHRQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRW x (MOVQconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW _ (MOVQconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRWconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRXL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRXL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRXL x (MOVLconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRXL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHRXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHRXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHRLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRXQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRXQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRXQ x (MOVLconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRXQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHRXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHRXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SHRXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBL x (MOVLconst [c])) // result: (SUBLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SUBLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // result: (NEGL (SUBLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBLconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (SUBLconst [c] x) // result: (ADDLconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } } func rewriteValueAMD64_OpAMD64SUBLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (SUBL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconst x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } // match: (SUBQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (NEGQ (SUBQconst x [int32(c)])) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBQload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQborrow(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQborrow x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconstborrow x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SUBQconst [c] x) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } // match: (SUBQconst (MOVQconst [d]) [c]) // result: (MOVQconst [d-int64(c)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d - int64(c)) return true } // match: (SUBQconst (SUBQconst x [d]) [c]) // cond: is32Bit(int64(-c)-int64(d)) // result: (ADDQconst [-c-d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SUBQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(-c) - int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c - d) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (SUBQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (SUBSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (SUBSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64TESTB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [int8(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } break } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVBload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTBconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTBconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTL a:(ANDLload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTL (MOVLload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDLload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTL) v0 := b.NewValue0(a.Pos, OpAMD64MOVLload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTLconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTLconst [c] (MOVLconst [c])) // cond: c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTLconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTL x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTL) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (TESTQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { continue } v.reset(OpAMD64TESTQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTQ a:(ANDQload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTQ (MOVQload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDQload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTQ) v0 := b.NewValue0(a.Pos, OpAMD64MOVQload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTQconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTQconst [-1] x) // cond: x.Op != OpAMD64MOVQconst // result: (TESTQ x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVQconst) { break } v.reset(OpAMD64TESTQ) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [int16(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } break } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVWload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTWconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTWconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64XADDLlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDLlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XADDQlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDQlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGL(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGL [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGQ [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTCL) v.AddArg2(x, y) return true } break } // match: (XORL (SHLXL (MOVLconst [1]) y) x) // result: (BTCL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTCL) v.AddArg2(x, y) return true } break } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRLconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRWconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRBconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORLconst(v *Value) bool { v_0 := v.Args[0] // match: (XORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORLconst [1] (SETNE x)) // result: (SETEQ x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETNE { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (XORLconst [1] (SETEQ x)) // result: (SETNE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETEQ { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (XORLconst [1] (SETL x)) // result: (SETGE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETL { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (XORLconst [1] (SETGE x)) // result: (SETL x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETGE { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (XORLconst [1] (SETLE x)) // result: (SETG x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETLE { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (XORLconst [1] (SETG x)) // result: (SETLE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETG { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (XORLconst [1] (SETB x)) // result: (SETAE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETB { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (XORLconst [1] (SETAE x)) // result: (SETB x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETAE { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (XORLconst [1] (SETBE x)) // result: (SETA x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETBE { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (XORLconst [1] (SETA x)) // result: (SETBE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETA { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (XORLconst [c] (XORLconst [d] x)) // result: (XORLconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORLconst [c] (BTCLconst [d] x)) // result: (XORLconst [c ^ 1<= 128 // result: (BTCQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (XORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRQconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORQconst(v *Value) bool { v_0 := v.Args[0] // match: (XORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORQconst [c] (XORQconst [d] x)) // result: (XORQconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORQconst [c] (BTCQconst [d] x)) // cond: is32Bit(int64(c) ^ 1< val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore64(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore64 ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore8 ptr val mem) // result: (Select1 (XCHGB val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStorePtrNoWB(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStorePtrNoWB ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen16 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen16 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVWQZX x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, x.Type) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) v1.AuxInt = int32ToAuxInt(1) v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v2.AddArg(x) v1.AddArg2(v2, v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (BitLen32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // cond: buildcfg.GOAMD64 < 3 // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(1) v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) v1 := b.NewValue0(v.Pos, OpSelect0, t) v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v3.AuxInt = int64ToAuxInt(-1) v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4.AddArg(v2) v0.AddArg3(v1, v3, v4) v.AddArg(v0) return true } // match: (BitLen64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-64] (LZCNTQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-64) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTQ, typ.UInt64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen8 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen8 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVBQZX x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, x.Type) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCeil(v *Value) bool { v_0 := v.Args[0] // match: (Ceil x) // result: (ROUNDSD [2] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(2) v.AddArg(x) return true } } func rewriteValueAMD64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (CondSelect x y (SETEQ cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is32BitInt(t) // result: (CMOVLEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is32BitInt(t) // result: (CMOVLNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is32BitInt(t) // result: (CMOVLLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is32BitInt(t) // result: (CMOVLGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is32BitInt(t) // result: (CMOVLLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is32BitInt(t) // result: (CMOVLGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is32BitInt(t) // result: (CMOVLHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is32BitInt(t) // result: (CMOVLCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is32BitInt(t) // result: (CMOVLCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is32BitInt(t) // result: (CMOVLLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is32BitInt(t) // result: (CMOVLEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is32BitInt(t) // result: (CMOVLNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is32BitInt(t) // result: (CMOVLGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is32BitInt(t) // result: (CMOVLGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is16BitInt(t) // result: (CMOVWEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is16BitInt(t) // result: (CMOVWNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is16BitInt(t) // result: (CMOVWLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is16BitInt(t) // result: (CMOVWGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is16BitInt(t) // result: (CMOVWLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is16BitInt(t) // result: (CMOVWGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is16BitInt(t) // result: (CMOVWHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is16BitInt(t) // result: (CMOVWCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is16BitInt(t) // result: (CMOVWCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is16BitInt(t) // result: (CMOVWLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is16BitInt(t) // result: (CMOVWEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is16BitInt(t) // result: (CMOVWNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is16BitInt(t) // result: (CMOVWGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is16BitInt(t) // result: (CMOVWGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 1 // result: (CondSelect x y (MOVBQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 1) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 2 // result: (CondSelect x y (MOVWQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 2) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 4 // result: (CondSelect x y (MOVLQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 4) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { break } v.reset(OpAMD64CMOVQNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) // result: (CMOVLNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) // result: (CMOVWNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } return false } func rewriteValueAMD64_OpConst16(v *Value) bool { // match: (Const16 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt16(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConst8(v *Value) bool { // match: (Const8 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt8(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConstBool(v *Value) bool { // match: (ConstBool [c]) // result: (MOVLconst [b2i32(c)]) for { c := auxIntToBool(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(b2i32(c)) return true } } func rewriteValueAMD64_OpConstNil(v *Value) bool { // match: (ConstNil ) // result: (MOVQconst [0]) for { v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } } func rewriteValueAMD64_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (BSFL (BTSLconst [16] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(16) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz16NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ (BTSQconst [32] x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) v1.AuxInt = int8ToAuxInt(32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz32NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64 x) // cond: buildcfg.GOAMD64 < 3 // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v3.AddArg(v1) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueAMD64_OpCtz64NonZero(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ x)) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (BSFL (BTSLconst [ 8] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 [a] x y) // result: (Select0 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (Select0 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32 [a] x y) // result: (Select0 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32u x y) // result: (Select0 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64 [a] x y) // result: (Select0 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64u x y) // result: (Select0 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq16 x y) // result: (SETEQ (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32 x y) // result: (SETEQ (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32F x y) // result: (SETEQF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64 x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64F x y) // result: (SETEQF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq8 x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqB x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqPtr x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpFMA(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMA x y z) // result: (VFMADD231SD z x y) for { x := v_0 y := v_1 z := v_2 v.reset(OpAMD64VFMADD231SD) v.AddArg3(z, x, y) return true } } func rewriteValueAMD64_OpFloor(v *Value) bool { v_0 := v.Args[0] // match: (Floor x) // result: (ROUNDSD [1] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpGetG(v *Value) bool { v_0 := v.Args[0] // match: (GetG mem) // cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal // result: (LoweredGetG mem) for { mem := v_0 if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) { break } v.reset(OpAMD64LoweredGetG) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (HasCPUFeature {s}) // result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s}))) for { s := auxToSym(v.Aux) v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64) v1.Aux = symToAux(s) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsInBounds idx len) // result: (SETB (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsNonNil(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (IsNonNil p) // result: (SETNE (TESTQ p p)) for { p := v_0 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) v0.AddArg2(p, p) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsSliceInBounds idx len) // result: (SETBE (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16 x y) // result: (SETLE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16U x y) // result: (SETBE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32 x y) // result: (SETLE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32F x y) // result: (SETGEF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32U x y) // result: (SETBE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64 x y) // result: (SETLE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64F x y) // result: (SETGEF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64U x y) // result: (SETBE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8 x y) // result: (SETLE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8U x y) // result: (SETBE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16 x y) // result: (SETL (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16U x y) // result: (SETB (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 x y) // result: (SETL (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32F x y) // result: (SETGF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32U x y) // result: (SETB (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 x y) // result: (SETL (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64F x y) // result: (SETGF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64U x y) // result: (SETB (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8 x y) // result: (SETL (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8U x y) // result: (SETB (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVQload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64MOVQload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) // result: (MOVLload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t)) { break } v.reset(OpAMD64MOVLload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t)) { break } v.reset(OpAMD64MOVWload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(OpAMD64MOVBload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitFloat(t)) { break } v.reset(OpAMD64MOVSSload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitFloat(t)) { break } v.reset(OpAMD64MOVSDload) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpLocalAddr(v *Value) bool { v_0 := v.Args[0] // match: (LocalAddr {sym} base _) // result: (LEAQ {sym} base) for { sym := auxToSym(v.Aux) base := v_0 v.reset(OpAMD64LEAQ) v.Aux = symToAux(sym) v.AddArg(base) return true } } func rewriteValueAMD64_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16 [a] x y) // result: (Select1 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Select1 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32 [a] x y) // result: (Select1 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (Select1 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64 [a] x y) // result: (Select1 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (Select1 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [2] dst src mem) // result: (MOVWstore dst (MOVWload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [4] dst src mem) // result: (MOVLstore dst (MOVLload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [8] dst src mem) // result: (MOVQstore dst (MOVQload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVQstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: config.useSSE // result: (MOVOstore dst (MOVOload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: !config.useSSE // result: (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [32] dst src mem) // result: (Move [16] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpMove) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [48] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 48 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [64] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [32]) (OffPtr src [32]) (Move [32] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 64 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(32) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(32) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(32) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(2) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [6] dst src mem) // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [7] dst src mem) // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [10] dst src mem) // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [12] dst src mem) // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s == 11 || s >= 13 && s <= 15 // result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s == 11 || s >= 13 && s <= 15) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(int32(s - 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(int32(s - 8)) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 <= 8 // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 <= 8) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVOstore dst (MOVOload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AuxInt = int32ToAuxInt(8) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AuxInt = int32ToAuxInt(8) v3.AddArg2(src, mem) v4 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v5 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v5.AddArg2(src, mem) v4.AddArg3(dst, v5, mem) v2.AddArg3(dst, v3, v4) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s) // result: (DUFFCOPY [s] dst src mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s)) { break } v.reset(OpAMD64DUFFCOPY) v.AuxInt = int64ToAuxInt(s) v.AddArg3(dst, src, mem) return true } // match: (Move [s] dst src mem) // cond: (s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s) // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !((s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s)) { break } v.reset(OpAMD64REPMOVSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v.AddArg4(dst, src, v0, mem) return true } return false } func rewriteValueAMD64_OpNeg32F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg32F x) // result: (PXOR x (MOVSSconst [float32(math.Copysign(0, -1))])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1))) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeg64F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg64F x) // result: (PXOR x (MOVSDconst [math.Copysign(0, -1)])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) v0.AuxInt = float64ToAuxInt(math.Copysign(0, -1)) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq16 x y) // result: (SETNE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32 x y) // result: (SETNE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32F x y) // result: (SETNEF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64 x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64F x y) // result: (SETNEF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq8 x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqB x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqPtr x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNot(v *Value) bool { v_0 := v.Args[0] // match: (Not x) // result: (XORLconst [1] x) for { x := v_0 v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // cond: is32Bit(off) // result: (ADDQconst [int32(off)] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 if !(is32Bit(off)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(off)) v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDQ (MOVQconst [off]) ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(off) v.AddArg2(v0, ptr) return true } } func rewriteValueAMD64_OpPanicBounds(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 0) { break } v.reset(OpAMD64LoweredPanicBoundsA) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 1) { break } v.reset(OpAMD64LoweredPanicBoundsB) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 2) { break } v.reset(OpAMD64LoweredPanicBoundsC) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } return false } func rewriteValueAMD64_OpPopCount16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTL (MOVWQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpPopCount8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTL (MOVBQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpRoundToEven(v *Value) bool { v_0 := v.Args[0] // match: (RoundToEven x) // result: (ROUNDSD [0] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } } func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpSelect0(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uover x y)) // result: (Select0 (MULQU x y)) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Mul32uover x y)) // result: (Select0 (MULLU x y)) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y c)) // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst32 val tuple)) // result: (ADDL val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDL) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } // match: (Select0 (AddTupleFirst64 val tuple)) // result: (ADDQ val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } return false } func rewriteValueAMD64_OpSelect1(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uover x y)) // result: (SETO (Select1 (MULQU x y))) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul32uover x y)) // result: (SETO (Select1 (MULLU x y))) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Add64carry x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (NEGLflags (MOVQconst [0]))) // result: (FlagEQ) for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 0 { break } v.reset(OpAMD64FlagEQ) return true } // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) // result: x for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64SBBQcarrymask { break } x := v_0_0_0.Args[0] v.copyOf(x) return true } // match: (Select1 (AddTupleFirst32 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } // match: (Select1 (AddTupleFirst64 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } return false } func rewriteValueAMD64_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem))))) // cond: sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call) // result: (Move [sc.Val64()] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpAMD64MOVQstoreconst { break } sc := auxIntToValAndOff(s1.AuxInt) _ = s1.Args[1] s2 := s1.Args[1] if s2.Op != OpAMD64MOVQstore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpAMD64MOVQstore { break } mem := s3.Args[2] dst := s3.Args[1] if !(sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sc.Val64()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem)) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpAMD64MOVQconst { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } return false } func rewriteValueAMD64_OpSlicemask(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Slicemask x) // result: (SARQconst (NEGQ x) [63]) for { t := v.Type x := v_0 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(63) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpSpectreIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreIndex x y) // result: (CMOVQCC x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQCC) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpSpectreSliceIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreSliceIndex x y) // result: (CMOVQHI x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQHI) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && is64BitFloat(val.Type) // result: (MOVSDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSDstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && is32BitFloat(val.Type) // result: (MOVSSstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSSstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 // result: (MOVQstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8) { break } v.reset(OpAMD64MOVQstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 // result: (MOVLstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4) { break } v.reset(OpAMD64MOVLstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 2 // result: (MOVWstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 2) { break } v.reset(OpAMD64MOVWstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 1 // result: (MOVBstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 1) { break } v.reset(OpAMD64MOVBstore) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpTrunc(v *Value) bool { v_0 := v.Args[0] // match: (Trunc x) // result: (ROUNDSD [3] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(3) v.AddArg(x) return true } } func rewriteValueAMD64_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [0] _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_1 v.copyOf(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [2] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [4] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [8] destptr mem) // result: (MOVQstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 2)) v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [5] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [6] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [7] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 3)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%8 != 0 && s > 8 && !config.useSSE // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%8 != 0 && s > 8 && !config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%8) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [24] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 24 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [32] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 24)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 8 && s < 16 && config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,int32(s-8))] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 8 && s < 16 && config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, int32(s-8))) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [32] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [48] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [64] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,48)] destptr (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 48)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice // result: (DUFFZERO [s] destptr mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFZERO) v.AuxInt = int64ToAuxInt(s) v.AddArg2(destptr, mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0 // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !((s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0) { break } v.reset(OpAMD64REPSTOSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(0) v.AddArg4(destptr, v0, v1, mem) return true } return false } func rewriteBlockAMD64(b *Block) bool { typ := &b.Func.Config.Types switch b.Kind { case BlockAMD64EQ: // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (UGE (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (UGE (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64GE: // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64GT: // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockIf: // match: (If (SETL cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64SETL { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (If (SETLE cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64SETLE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (If (SETG cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64SETG { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (If (SETGE cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64SETGE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (If (SETEQ cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64SETEQ { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (If (SETNE cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64SETNE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (If (SETB cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64SETB { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (If (SETBE cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64SETBE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (If (SETA cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETA { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETAE cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETAE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETO cmp) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64SETO { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (If (SETGF cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETGF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETGEF cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETGEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETEQF cmp) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64SETEQF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (If (SETNEF cmp) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64SETNEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (If cond yes no) // result: (NE (TESTB cond cond) yes no) for { cond := b.Controls[0] v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) v0.AddArg2(cond, cond) b.resetWithControl(BlockAMD64NE, v0) return true } case BlockJumpTable: // match: (JumpTable idx) // result: (JUMPTABLE {makeJumpTableSym(b)} idx (LEAQ {makeJumpTableSym(b)} (SB))) for { idx := b.Controls[0] v0 := b.NewValue0(b.Pos, OpAMD64LEAQ, typ.Uintptr) v0.Aux = symToAux(makeJumpTableSym(b)) v1 := b.NewValue0(b.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) b.resetWithControl2(BlockAMD64JUMPTABLE, idx, v0) b.Aux = symToAux(makeJumpTableSym(b)) return true } case BlockAMD64LE: // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64LT: // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETL { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETLE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETG { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQ { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETB { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETBE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETA { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETAE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETO { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (ULT (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (ULT (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGE: // match: (UGE (TESTQ x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTL x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTW x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTB x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (UGE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (UGE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGT: // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (UGT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64ULE: // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (ULE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64ULT: // match: (ULT (TESTQ x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTL x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTW x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTB x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (ULT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- y -- // Code generated from gen/AMD64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "internal/buildcfg" import "math" import "cmd/internal/obj" import "cmd/compile/internal/types" func rewriteValueAMD64(v *Value) bool { switch v.Op { case OpAMD64ADCQ: return rewriteValueAMD64_OpAMD64ADCQ(v) case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst(v) case OpAMD64ADDL: return rewriteValueAMD64_OpAMD64ADDL(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst(v) case OpAMD64ADDLconstmodify: return rewriteValueAMD64_OpAMD64ADDLconstmodify(v) case OpAMD64ADDLload: return rewriteValueAMD64_OpAMD64ADDLload(v) case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify(v) case OpAMD64ADDQ: return rewriteValueAMD64_OpAMD64ADDQ(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry(v) case OpAMD64ADDQconst: return rewriteValueAMD64_OpAMD64ADDQconst(v) case OpAMD64ADDQconstmodify: return rewriteValueAMD64_OpAMD64ADDQconstmodify(v) case OpAMD64ADDQload: return rewriteValueAMD64_OpAMD64ADDQload(v) case OpAMD64ADDQmodify: return rewriteValueAMD64_OpAMD64ADDQmodify(v) case OpAMD64ADDSD: return rewriteValueAMD64_OpAMD64ADDSD(v) case OpAMD64ADDSDload: return rewriteValueAMD64_OpAMD64ADDSDload(v) case OpAMD64ADDSS: return rewriteValueAMD64_OpAMD64ADDSS(v) case OpAMD64ADDSSload: return rewriteValueAMD64_OpAMD64ADDSSload(v) case OpAMD64ANDL: return rewriteValueAMD64_OpAMD64ANDL(v) case OpAMD64ANDLconst: return rewriteValueAMD64_OpAMD64ANDLconst(v) case OpAMD64ANDLconstmodify: return rewriteValueAMD64_OpAMD64ANDLconstmodify(v) case OpAMD64ANDLload: return rewriteValueAMD64_OpAMD64ANDLload(v) case OpAMD64ANDLmodify: return rewriteValueAMD64_OpAMD64ANDLmodify(v) case OpAMD64ANDNL: return rewriteValueAMD64_OpAMD64ANDNL(v) case OpAMD64ANDNQ: return rewriteValueAMD64_OpAMD64ANDNQ(v) case OpAMD64ANDQ: return rewriteValueAMD64_OpAMD64ANDQ(v) case OpAMD64ANDQconst: return rewriteValueAMD64_OpAMD64ANDQconst(v) case OpAMD64ANDQconstmodify: return rewriteValueAMD64_OpAMD64ANDQconstmodify(v) case OpAMD64ANDQload: return rewriteValueAMD64_OpAMD64ANDQload(v) case OpAMD64ANDQmodify: return rewriteValueAMD64_OpAMD64ANDQmodify(v) case OpAMD64BSFQ: return rewriteValueAMD64_OpAMD64BSFQ(v) case OpAMD64BSWAPL: return rewriteValueAMD64_OpAMD64BSWAPL(v) case OpAMD64BSWAPQ: return rewriteValueAMD64_OpAMD64BSWAPQ(v) case OpAMD64BTCLconst: return rewriteValueAMD64_OpAMD64BTCLconst(v) case OpAMD64BTCQconst: return rewriteValueAMD64_OpAMD64BTCQconst(v) case OpAMD64BTLconst: return rewriteValueAMD64_OpAMD64BTLconst(v) case OpAMD64BTQconst: return rewriteValueAMD64_OpAMD64BTQconst(v) case OpAMD64BTRLconst: return rewriteValueAMD64_OpAMD64BTRLconst(v) case OpAMD64BTRQconst: return rewriteValueAMD64_OpAMD64BTRQconst(v) case OpAMD64BTSLconst: return rewriteValueAMD64_OpAMD64BTSLconst(v) case OpAMD64BTSQconst: return rewriteValueAMD64_OpAMD64BTSQconst(v) case OpAMD64CMOVLCC: return rewriteValueAMD64_OpAMD64CMOVLCC(v) case OpAMD64CMOVLCS: return rewriteValueAMD64_OpAMD64CMOVLCS(v) case OpAMD64CMOVLEQ: return rewriteValueAMD64_OpAMD64CMOVLEQ(v) case OpAMD64CMOVLGE: return rewriteValueAMD64_OpAMD64CMOVLGE(v) case OpAMD64CMOVLGT: return rewriteValueAMD64_OpAMD64CMOVLGT(v) case OpAMD64CMOVLHI: return rewriteValueAMD64_OpAMD64CMOVLHI(v) case OpAMD64CMOVLLE: return rewriteValueAMD64_OpAMD64CMOVLLE(v) case OpAMD64CMOVLLS: return rewriteValueAMD64_OpAMD64CMOVLLS(v) case OpAMD64CMOVLLT: return rewriteValueAMD64_OpAMD64CMOVLLT(v) case OpAMD64CMOVLNE: return rewriteValueAMD64_OpAMD64CMOVLNE(v) case OpAMD64CMOVQCC: return rewriteValueAMD64_OpAMD64CMOVQCC(v) case OpAMD64CMOVQCS: return rewriteValueAMD64_OpAMD64CMOVQCS(v) case OpAMD64CMOVQEQ: return rewriteValueAMD64_OpAMD64CMOVQEQ(v) case OpAMD64CMOVQGE: return rewriteValueAMD64_OpAMD64CMOVQGE(v) case OpAMD64CMOVQGT: return rewriteValueAMD64_OpAMD64CMOVQGT(v) case OpAMD64CMOVQHI: return rewriteValueAMD64_OpAMD64CMOVQHI(v) case OpAMD64CMOVQLE: return rewriteValueAMD64_OpAMD64CMOVQLE(v) case OpAMD64CMOVQLS: return rewriteValueAMD64_OpAMD64CMOVQLS(v) case OpAMD64CMOVQLT: return rewriteValueAMD64_OpAMD64CMOVQLT(v) case OpAMD64CMOVQNE: return rewriteValueAMD64_OpAMD64CMOVQNE(v) case OpAMD64CMOVWCC: return rewriteValueAMD64_OpAMD64CMOVWCC(v) case OpAMD64CMOVWCS: return rewriteValueAMD64_OpAMD64CMOVWCS(v) case OpAMD64CMOVWEQ: return rewriteValueAMD64_OpAMD64CMOVWEQ(v) case OpAMD64CMOVWGE: return rewriteValueAMD64_OpAMD64CMOVWGE(v) case OpAMD64CMOVWGT: return rewriteValueAMD64_OpAMD64CMOVWGT(v) case OpAMD64CMOVWHI: return rewriteValueAMD64_OpAMD64CMOVWHI(v) case OpAMD64CMOVWLE: return rewriteValueAMD64_OpAMD64CMOVWLE(v) case OpAMD64CMOVWLS: return rewriteValueAMD64_OpAMD64CMOVWLS(v) case OpAMD64CMOVWLT: return rewriteValueAMD64_OpAMD64CMOVWLT(v) case OpAMD64CMOVWNE: return rewriteValueAMD64_OpAMD64CMOVWNE(v) case OpAMD64CMPB: return rewriteValueAMD64_OpAMD64CMPB(v) case OpAMD64CMPBconst: return rewriteValueAMD64_OpAMD64CMPBconst(v) case OpAMD64CMPBconstload: return rewriteValueAMD64_OpAMD64CMPBconstload(v) case OpAMD64CMPBload: return rewriteValueAMD64_OpAMD64CMPBload(v) case OpAMD64CMPL: return rewriteValueAMD64_OpAMD64CMPL(v) case OpAMD64CMPLconst: return rewriteValueAMD64_OpAMD64CMPLconst(v) case OpAMD64CMPLconstload: return rewriteValueAMD64_OpAMD64CMPLconstload(v) case OpAMD64CMPLload: return rewriteValueAMD64_OpAMD64CMPLload(v) case OpAMD64CMPQ: return rewriteValueAMD64_OpAMD64CMPQ(v) case OpAMD64CMPQconst: return rewriteValueAMD64_OpAMD64CMPQconst(v) case OpAMD64CMPQconstload: return rewriteValueAMD64_OpAMD64CMPQconstload(v) case OpAMD64CMPQload: return rewriteValueAMD64_OpAMD64CMPQload(v) case OpAMD64CMPW: return rewriteValueAMD64_OpAMD64CMPW(v) case OpAMD64CMPWconst: return rewriteValueAMD64_OpAMD64CMPWconst(v) case OpAMD64CMPWconstload: return rewriteValueAMD64_OpAMD64CMPWconstload(v) case OpAMD64CMPWload: return rewriteValueAMD64_OpAMD64CMPWload(v) case OpAMD64CMPXCHGLlock: return rewriteValueAMD64_OpAMD64CMPXCHGLlock(v) case OpAMD64CMPXCHGQlock: return rewriteValueAMD64_OpAMD64CMPXCHGQlock(v) case OpAMD64DIVSD: return rewriteValueAMD64_OpAMD64DIVSD(v) case OpAMD64DIVSDload: return rewriteValueAMD64_OpAMD64DIVSDload(v) case OpAMD64DIVSS: return rewriteValueAMD64_OpAMD64DIVSS(v) case OpAMD64DIVSSload: return rewriteValueAMD64_OpAMD64DIVSSload(v) case OpAMD64HMULL: return rewriteValueAMD64_OpAMD64HMULL(v) case OpAMD64HMULLU: return rewriteValueAMD64_OpAMD64HMULLU(v) case OpAMD64HMULQ: return rewriteValueAMD64_OpAMD64HMULQ(v) case OpAMD64HMULQU: return rewriteValueAMD64_OpAMD64HMULQU(v) case OpAMD64LEAL: return rewriteValueAMD64_OpAMD64LEAL(v) case OpAMD64LEAL1: return rewriteValueAMD64_OpAMD64LEAL1(v) case OpAMD64LEAL2: return rewriteValueAMD64_OpAMD64LEAL2(v) case OpAMD64LEAL4: return rewriteValueAMD64_OpAMD64LEAL4(v) case OpAMD64LEAL8: return rewriteValueAMD64_OpAMD64LEAL8(v) case OpAMD64LEAQ: return rewriteValueAMD64_OpAMD64LEAQ(v) case OpAMD64LEAQ1: return rewriteValueAMD64_OpAMD64LEAQ1(v) case OpAMD64LEAQ2: return rewriteValueAMD64_OpAMD64LEAQ2(v) case OpAMD64LEAQ4: return rewriteValueAMD64_OpAMD64LEAQ4(v) case OpAMD64LEAQ8: return rewriteValueAMD64_OpAMD64LEAQ8(v) case OpAMD64MOVBELstore: return rewriteValueAMD64_OpAMD64MOVBELstore(v) case OpAMD64MOVBEQstore: return rewriteValueAMD64_OpAMD64MOVBEQstore(v) case OpAMD64MOVBEWstore: return rewriteValueAMD64_OpAMD64MOVBEWstore(v) case OpAMD64MOVBQSX: return rewriteValueAMD64_OpAMD64MOVBQSX(v) case OpAMD64MOVBQSXload: return rewriteValueAMD64_OpAMD64MOVBQSXload(v) case OpAMD64MOVBQZX: return rewriteValueAMD64_OpAMD64MOVBQZX(v) case OpAMD64MOVBatomicload: return rewriteValueAMD64_OpAMD64MOVBatomicload(v) case OpAMD64MOVBload: return rewriteValueAMD64_OpAMD64MOVBload(v) case OpAMD64MOVBstore: return rewriteValueAMD64_OpAMD64MOVBstore(v) case OpAMD64MOVBstoreconst: return rewriteValueAMD64_OpAMD64MOVBstoreconst(v) case OpAMD64MOVLQSX: return rewriteValueAMD64_OpAMD64MOVLQSX(v) case OpAMD64MOVLQSXload: return rewriteValueAMD64_OpAMD64MOVLQSXload(v) case OpAMD64MOVLQZX: return rewriteValueAMD64_OpAMD64MOVLQZX(v) case OpAMD64MOVLatomicload: return rewriteValueAMD64_OpAMD64MOVLatomicload(v) case OpAMD64MOVLf2i: return rewriteValueAMD64_OpAMD64MOVLf2i(v) case OpAMD64MOVLi2f: return rewriteValueAMD64_OpAMD64MOVLi2f(v) case OpAMD64MOVLload: return rewriteValueAMD64_OpAMD64MOVLload(v) case OpAMD64MOVLstore: return rewriteValueAMD64_OpAMD64MOVLstore(v) case OpAMD64MOVLstoreconst: return rewriteValueAMD64_OpAMD64MOVLstoreconst(v) case OpAMD64MOVOload: return rewriteValueAMD64_OpAMD64MOVOload(v) case OpAMD64MOVOstore: return rewriteValueAMD64_OpAMD64MOVOstore(v) case OpAMD64MOVOstoreconst: return rewriteValueAMD64_OpAMD64MOVOstoreconst(v) case OpAMD64MOVQatomicload: return rewriteValueAMD64_OpAMD64MOVQatomicload(v) case OpAMD64MOVQf2i: return rewriteValueAMD64_OpAMD64MOVQf2i(v) case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f(v) case OpAMD64MOVQload: return rewriteValueAMD64_OpAMD64MOVQload(v) case OpAMD64MOVQstore: return rewriteValueAMD64_OpAMD64MOVQstore(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst(v) case OpAMD64MOVSDload: return rewriteValueAMD64_OpAMD64MOVSDload(v) case OpAMD64MOVSDstore: return rewriteValueAMD64_OpAMD64MOVSDstore(v) case OpAMD64MOVSSload: return rewriteValueAMD64_OpAMD64MOVSSload(v) case OpAMD64MOVSSstore: return rewriteValueAMD64_OpAMD64MOVSSstore(v) case OpAMD64MOVWQSX: return rewriteValueAMD64_OpAMD64MOVWQSX(v) case OpAMD64MOVWQSXload: return rewriteValueAMD64_OpAMD64MOVWQSXload(v) case OpAMD64MOVWQZX: return rewriteValueAMD64_OpAMD64MOVWQZX(v) case OpAMD64MOVWload: return rewriteValueAMD64_OpAMD64MOVWload(v) case OpAMD64MOVWstore: return rewriteValueAMD64_OpAMD64MOVWstore(v) case OpAMD64MOVWstoreconst: return rewriteValueAMD64_OpAMD64MOVWstoreconst(v) case OpAMD64MULL: return rewriteValueAMD64_OpAMD64MULL(v) case OpAMD64MULLconst: return rewriteValueAMD64_OpAMD64MULLconst(v) case OpAMD64MULQ: return rewriteValueAMD64_OpAMD64MULQ(v) case OpAMD64MULQconst: return rewriteValueAMD64_OpAMD64MULQconst(v) case OpAMD64MULSD: return rewriteValueAMD64_OpAMD64MULSD(v) case OpAMD64MULSDload: return rewriteValueAMD64_OpAMD64MULSDload(v) case OpAMD64MULSS: return rewriteValueAMD64_OpAMD64MULSS(v) case OpAMD64MULSSload: return rewriteValueAMD64_OpAMD64MULSSload(v) case OpAMD64NEGL: return rewriteValueAMD64_OpAMD64NEGL(v) case OpAMD64NEGQ: return rewriteValueAMD64_OpAMD64NEGQ(v) case OpAMD64NOTL: return rewriteValueAMD64_OpAMD64NOTL(v) case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ(v) case OpAMD64ORL: return rewriteValueAMD64_OpAMD64ORL(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst(v) case OpAMD64ORLconstmodify: return rewriteValueAMD64_OpAMD64ORLconstmodify(v) case OpAMD64ORLload: return rewriteValueAMD64_OpAMD64ORLload(v) case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify(v) case OpAMD64ORQ: return rewriteValueAMD64_OpAMD64ORQ(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst(v) case OpAMD64ORQconstmodify: return rewriteValueAMD64_OpAMD64ORQconstmodify(v) case OpAMD64ORQload: return rewriteValueAMD64_OpAMD64ORQload(v) case OpAMD64ORQmodify: return rewriteValueAMD64_OpAMD64ORQmodify(v) case OpAMD64ROLB: return rewriteValueAMD64_OpAMD64ROLB(v) case OpAMD64ROLBconst: return rewriteValueAMD64_OpAMD64ROLBconst(v) case OpAMD64ROLL: return rewriteValueAMD64_OpAMD64ROLL(v) case OpAMD64ROLLconst: return rewriteValueAMD64_OpAMD64ROLLconst(v) case OpAMD64ROLQ: return rewriteValueAMD64_OpAMD64ROLQ(v) case OpAMD64ROLQconst: return rewriteValueAMD64_OpAMD64ROLQconst(v) case OpAMD64ROLW: return rewriteValueAMD64_OpAMD64ROLW(v) case OpAMD64ROLWconst: return rewriteValueAMD64_OpAMD64ROLWconst(v) case OpAMD64RORB: return rewriteValueAMD64_OpAMD64RORB(v) case OpAMD64RORL: return rewriteValueAMD64_OpAMD64RORL(v) case OpAMD64RORQ: return rewriteValueAMD64_OpAMD64RORQ(v) case OpAMD64RORW: return rewriteValueAMD64_OpAMD64RORW(v) case OpAMD64SARB: return rewriteValueAMD64_OpAMD64SARB(v) case OpAMD64SARBconst: return rewriteValueAMD64_OpAMD64SARBconst(v) case OpAMD64SARL: return rewriteValueAMD64_OpAMD64SARL(v) case OpAMD64SARLconst: return rewriteValueAMD64_OpAMD64SARLconst(v) case OpAMD64SARQ: return rewriteValueAMD64_OpAMD64SARQ(v) case OpAMD64SARQconst: return rewriteValueAMD64_OpAMD64SARQconst(v) case OpAMD64SARW: return rewriteValueAMD64_OpAMD64SARW(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst(v) case OpAMD64SARXL: return rewriteValueAMD64_OpAMD64SARXL(v) case OpAMD64SARXLload: return rewriteValueAMD64_OpAMD64SARXLload(v) case OpAMD64SARXQ: return rewriteValueAMD64_OpAMD64SARXQ(v) case OpAMD64SARXQload: return rewriteValueAMD64_OpAMD64SARXQload(v) case OpAMD64SBBLcarrymask: return rewriteValueAMD64_OpAMD64SBBLcarrymask(v) case OpAMD64SBBQ: return rewriteValueAMD64_OpAMD64SBBQ(v) case OpAMD64SBBQcarrymask: return rewriteValueAMD64_OpAMD64SBBQcarrymask(v) case OpAMD64SBBQconst: return rewriteValueAMD64_OpAMD64SBBQconst(v) case OpAMD64SETA: return rewriteValueAMD64_OpAMD64SETA(v) case OpAMD64SETAE: return rewriteValueAMD64_OpAMD64SETAE(v) case OpAMD64SETAEstore: return rewriteValueAMD64_OpAMD64SETAEstore(v) case OpAMD64SETAstore: return rewriteValueAMD64_OpAMD64SETAstore(v) case OpAMD64SETB: return rewriteValueAMD64_OpAMD64SETB(v) case OpAMD64SETBE: return rewriteValueAMD64_OpAMD64SETBE(v) case OpAMD64SETBEstore: return rewriteValueAMD64_OpAMD64SETBEstore(v) case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore(v) case OpAMD64SETEQ: return rewriteValueAMD64_OpAMD64SETEQ(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore(v) case OpAMD64SETG: return rewriteValueAMD64_OpAMD64SETG(v) case OpAMD64SETGE: return rewriteValueAMD64_OpAMD64SETGE(v) case OpAMD64SETGEstore: return rewriteValueAMD64_OpAMD64SETGEstore(v) case OpAMD64SETGstore: return rewriteValueAMD64_OpAMD64SETGstore(v) case OpAMD64SETL: return rewriteValueAMD64_OpAMD64SETL(v) case OpAMD64SETLE: return rewriteValueAMD64_OpAMD64SETLE(v) case OpAMD64SETLEstore: return rewriteValueAMD64_OpAMD64SETLEstore(v) case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore(v) case OpAMD64SETNE: return rewriteValueAMD64_OpAMD64SETNE(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore(v) case OpAMD64SHLL: return rewriteValueAMD64_OpAMD64SHLL(v) case OpAMD64SHLLconst: return rewriteValueAMD64_OpAMD64SHLLconst(v) case OpAMD64SHLQ: return rewriteValueAMD64_OpAMD64SHLQ(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst(v) case OpAMD64SHLXL: return rewriteValueAMD64_OpAMD64SHLXL(v) case OpAMD64SHLXLload: return rewriteValueAMD64_OpAMD64SHLXLload(v) case OpAMD64SHLXQ: return rewriteValueAMD64_OpAMD64SHLXQ(v) case OpAMD64SHLXQload: return rewriteValueAMD64_OpAMD64SHLXQload(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB(v) case OpAMD64SHRBconst: return rewriteValueAMD64_OpAMD64SHRBconst(v) case OpAMD64SHRL: return rewriteValueAMD64_OpAMD64SHRL(v) case OpAMD64SHRLconst: return rewriteValueAMD64_OpAMD64SHRLconst(v) case OpAMD64SHRQ: return rewriteValueAMD64_OpAMD64SHRQ(v) case OpAMD64SHRQconst: return rewriteValueAMD64_OpAMD64SHRQconst(v) case OpAMD64SHRW: return rewriteValueAMD64_OpAMD64SHRW(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst(v) case OpAMD64SHRXL: return rewriteValueAMD64_OpAMD64SHRXL(v) case OpAMD64SHRXLload: return rewriteValueAMD64_OpAMD64SHRXLload(v) case OpAMD64SHRXQ: return rewriteValueAMD64_OpAMD64SHRXQ(v) case OpAMD64SHRXQload: return rewriteValueAMD64_OpAMD64SHRXQload(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL(v) case OpAMD64SUBLconst: return rewriteValueAMD64_OpAMD64SUBLconst(v) case OpAMD64SUBLload: return rewriteValueAMD64_OpAMD64SUBLload(v) case OpAMD64SUBLmodify: return rewriteValueAMD64_OpAMD64SUBLmodify(v) case OpAMD64SUBQ: return rewriteValueAMD64_OpAMD64SUBQ(v) case OpAMD64SUBQborrow: return rewriteValueAMD64_OpAMD64SUBQborrow(v) case OpAMD64SUBQconst: return rewriteValueAMD64_OpAMD64SUBQconst(v) case OpAMD64SUBQload: return rewriteValueAMD64_OpAMD64SUBQload(v) case OpAMD64SUBQmodify: return rewriteValueAMD64_OpAMD64SUBQmodify(v) case OpAMD64SUBSD: return rewriteValueAMD64_OpAMD64SUBSD(v) case OpAMD64SUBSDload: return rewriteValueAMD64_OpAMD64SUBSDload(v) case OpAMD64SUBSS: return rewriteValueAMD64_OpAMD64SUBSS(v) case OpAMD64SUBSSload: return rewriteValueAMD64_OpAMD64SUBSSload(v) case OpAMD64TESTB: return rewriteValueAMD64_OpAMD64TESTB(v) case OpAMD64TESTBconst: return rewriteValueAMD64_OpAMD64TESTBconst(v) case OpAMD64TESTL: return rewriteValueAMD64_OpAMD64TESTL(v) case OpAMD64TESTLconst: return rewriteValueAMD64_OpAMD64TESTLconst(v) case OpAMD64TESTQ: return rewriteValueAMD64_OpAMD64TESTQ(v) case OpAMD64TESTQconst: return rewriteValueAMD64_OpAMD64TESTQconst(v) case OpAMD64TESTW: return rewriteValueAMD64_OpAMD64TESTW(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock(v) case OpAMD64XADDQlock: return rewriteValueAMD64_OpAMD64XADDQlock(v) case OpAMD64XCHGL: return rewriteValueAMD64_OpAMD64XCHGL(v) case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ(v) case OpAMD64XORL: return rewriteValueAMD64_OpAMD64XORL(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst(v) case OpAMD64XORLconstmodify: return rewriteValueAMD64_OpAMD64XORLconstmodify(v) case OpAMD64XORLload: return rewriteValueAMD64_OpAMD64XORLload(v) case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify(v) case OpAMD64XORQ: return rewriteValueAMD64_OpAMD64XORQ(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst(v) case OpAMD64XORQconstmodify: return rewriteValueAMD64_OpAMD64XORQconstmodify(v) case OpAMD64XORQload: return rewriteValueAMD64_OpAMD64XORQload(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify(v) case OpAdd16: v.Op = OpAMD64ADDL return true case OpAdd32: v.Op = OpAMD64ADDL return true case OpAdd32F: v.Op = OpAMD64ADDSS return true case OpAdd64: v.Op = OpAMD64ADDQ return true case OpAdd64F: v.Op = OpAMD64ADDSD return true case OpAdd8: v.Op = OpAMD64ADDL return true case OpAddPtr: v.Op = OpAMD64ADDQ return true case OpAddr: return rewriteValueAMD64_OpAddr(v) case OpAnd16: v.Op = OpAMD64ANDL return true case OpAnd32: v.Op = OpAMD64ANDL return true case OpAnd64: v.Op = OpAMD64ANDQ return true case OpAnd8: v.Op = OpAMD64ANDL return true case OpAndB: v.Op = OpAMD64ANDL return true case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32(v) case OpAtomicAdd64: return rewriteValueAMD64_OpAtomicAdd64(v) case OpAtomicAnd32: return rewriteValueAMD64_OpAtomicAnd32(v) case OpAtomicAnd8: return rewriteValueAMD64_OpAtomicAnd8(v) case OpAtomicCompareAndSwap32: return rewriteValueAMD64_OpAtomicCompareAndSwap32(v) case OpAtomicCompareAndSwap64: return rewriteValueAMD64_OpAtomicCompareAndSwap64(v) case OpAtomicExchange32: return rewriteValueAMD64_OpAtomicExchange32(v) case OpAtomicExchange64: return rewriteValueAMD64_OpAtomicExchange64(v) case OpAtomicLoad32: return rewriteValueAMD64_OpAtomicLoad32(v) case OpAtomicLoad64: return rewriteValueAMD64_OpAtomicLoad64(v) case OpAtomicLoad8: return rewriteValueAMD64_OpAtomicLoad8(v) case OpAtomicLoadPtr: return rewriteValueAMD64_OpAtomicLoadPtr(v) case OpAtomicOr32: return rewriteValueAMD64_OpAtomicOr32(v) case OpAtomicOr8: return rewriteValueAMD64_OpAtomicOr8(v) case OpAtomicStore32: return rewriteValueAMD64_OpAtomicStore32(v) case OpAtomicStore64: return rewriteValueAMD64_OpAtomicStore64(v) case OpAtomicStore8: return rewriteValueAMD64_OpAtomicStore8(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB(v) case OpAvg64u: v.Op = OpAMD64AVGQU return true case OpBitLen16: return rewriteValueAMD64_OpBitLen16(v) case OpBitLen32: return rewriteValueAMD64_OpBitLen32(v) case OpBitLen64: return rewriteValueAMD64_OpBitLen64(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8(v) case OpBswap32: v.Op = OpAMD64BSWAPL return true case OpBswap64: v.Op = OpAMD64BSWAPQ return true case OpCeil: return rewriteValueAMD64_OpCeil(v) case OpClosureCall: v.Op = OpAMD64CALLclosure return true case OpCom16: v.Op = OpAMD64NOTL return true case OpCom32: v.Op = OpAMD64NOTL return true case OpCom64: v.Op = OpAMD64NOTQ return true case OpCom8: v.Op = OpAMD64NOTL return true case OpCondSelect: return rewriteValueAMD64_OpCondSelect(v) case OpConst16: return rewriteValueAMD64_OpConst16(v) case OpConst32: v.Op = OpAMD64MOVLconst return true case OpConst32F: v.Op = OpAMD64MOVSSconst return true case OpConst64: v.Op = OpAMD64MOVQconst return true case OpConst64F: v.Op = OpAMD64MOVSDconst return true case OpConst8: return rewriteValueAMD64_OpConst8(v) case OpConstBool: return rewriteValueAMD64_OpConstBool(v) case OpConstNil: return rewriteValueAMD64_OpConstNil(v) case OpCtz16: return rewriteValueAMD64_OpCtz16(v) case OpCtz16NonZero: return rewriteValueAMD64_OpCtz16NonZero(v) case OpCtz32: return rewriteValueAMD64_OpCtz32(v) case OpCtz32NonZero: return rewriteValueAMD64_OpCtz32NonZero(v) case OpCtz64: return rewriteValueAMD64_OpCtz64(v) case OpCtz64NonZero: return rewriteValueAMD64_OpCtz64NonZero(v) case OpCtz8: return rewriteValueAMD64_OpCtz8(v) case OpCtz8NonZero: return rewriteValueAMD64_OpCtz8NonZero(v) case OpCvt32Fto32: v.Op = OpAMD64CVTTSS2SL return true case OpCvt32Fto64: v.Op = OpAMD64CVTTSS2SQ return true case OpCvt32Fto64F: v.Op = OpAMD64CVTSS2SD return true case OpCvt32to32F: v.Op = OpAMD64CVTSL2SS return true case OpCvt32to64F: v.Op = OpAMD64CVTSL2SD return true case OpCvt64Fto32: v.Op = OpAMD64CVTTSD2SL return true case OpCvt64Fto32F: v.Op = OpAMD64CVTSD2SS return true case OpCvt64Fto64: v.Op = OpAMD64CVTTSD2SQ return true case OpCvt64to32F: v.Op = OpAMD64CVTSQ2SS return true case OpCvt64to64F: v.Op = OpAMD64CVTSQ2SD return true case OpCvtBoolToUint8: v.Op = OpCopy return true case OpDiv128u: v.Op = OpAMD64DIVQU2 return true case OpDiv16: return rewriteValueAMD64_OpDiv16(v) case OpDiv16u: return rewriteValueAMD64_OpDiv16u(v) case OpDiv32: return rewriteValueAMD64_OpDiv32(v) case OpDiv32F: v.Op = OpAMD64DIVSS return true case OpDiv32u: return rewriteValueAMD64_OpDiv32u(v) case OpDiv64: return rewriteValueAMD64_OpDiv64(v) case OpDiv64F: v.Op = OpAMD64DIVSD return true case OpDiv64u: return rewriteValueAMD64_OpDiv64u(v) case OpDiv8: return rewriteValueAMD64_OpDiv8(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u(v) case OpEq16: return rewriteValueAMD64_OpEq16(v) case OpEq32: return rewriteValueAMD64_OpEq32(v) case OpEq32F: return rewriteValueAMD64_OpEq32F(v) case OpEq64: return rewriteValueAMD64_OpEq64(v) case OpEq64F: return rewriteValueAMD64_OpEq64F(v) case OpEq8: return rewriteValueAMD64_OpEq8(v) case OpEqB: return rewriteValueAMD64_OpEqB(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr(v) case OpFMA: return rewriteValueAMD64_OpFMA(v) case OpFloor: return rewriteValueAMD64_OpFloor(v) case OpGetCallerPC: v.Op = OpAMD64LoweredGetCallerPC return true case OpGetCallerSP: v.Op = OpAMD64LoweredGetCallerSP return true case OpGetClosurePtr: v.Op = OpAMD64LoweredGetClosurePtr return true case OpGetG: return rewriteValueAMD64_OpGetG(v) case OpHasCPUFeature: return rewriteValueAMD64_OpHasCPUFeature(v) case OpHmul32: v.Op = OpAMD64HMULL return true case OpHmul32u: v.Op = OpAMD64HMULLU return true case OpHmul64: v.Op = OpAMD64HMULQ return true case OpHmul64u: v.Op = OpAMD64HMULQU return true case OpInterCall: v.Op = OpAMD64CALLinter return true case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueAMD64_OpIsSliceInBounds(v) case OpLeq16: return rewriteValueAMD64_OpLeq16(v) case OpLeq16U: return rewriteValueAMD64_OpLeq16U(v) case OpLeq32: return rewriteValueAMD64_OpLeq32(v) case OpLeq32F: return rewriteValueAMD64_OpLeq32F(v) case OpLeq32U: return rewriteValueAMD64_OpLeq32U(v) case OpLeq64: return rewriteValueAMD64_OpLeq64(v) case OpLeq64F: return rewriteValueAMD64_OpLeq64F(v) case OpLeq64U: return rewriteValueAMD64_OpLeq64U(v) case OpLeq8: return rewriteValueAMD64_OpLeq8(v) case OpLeq8U: return rewriteValueAMD64_OpLeq8U(v) case OpLess16: return rewriteValueAMD64_OpLess16(v) case OpLess16U: return rewriteValueAMD64_OpLess16U(v) case OpLess32: return rewriteValueAMD64_OpLess32(v) case OpLess32F: return rewriteValueAMD64_OpLess32F(v) case OpLess32U: return rewriteValueAMD64_OpLess32U(v) case OpLess64: return rewriteValueAMD64_OpLess64(v) case OpLess64F: return rewriteValueAMD64_OpLess64F(v) case OpLess64U: return rewriteValueAMD64_OpLess64U(v) case OpLess8: return rewriteValueAMD64_OpLess8(v) case OpLess8U: return rewriteValueAMD64_OpLess8U(v) case OpLoad: return rewriteValueAMD64_OpLoad(v) case OpLocalAddr: return rewriteValueAMD64_OpLocalAddr(v) case OpLsh16x16: return rewriteValueAMD64_OpLsh16x16(v) case OpLsh16x32: return rewriteValueAMD64_OpLsh16x32(v) case OpLsh16x64: return rewriteValueAMD64_OpLsh16x64(v) case OpLsh16x8: return rewriteValueAMD64_OpLsh16x8(v) case OpLsh32x16: return rewriteValueAMD64_OpLsh32x16(v) case OpLsh32x32: return rewriteValueAMD64_OpLsh32x32(v) case OpLsh32x64: return rewriteValueAMD64_OpLsh32x64(v) case OpLsh32x8: return rewriteValueAMD64_OpLsh32x8(v) case OpLsh64x16: return rewriteValueAMD64_OpLsh64x16(v) case OpLsh64x32: return rewriteValueAMD64_OpLsh64x32(v) case OpLsh64x64: return rewriteValueAMD64_OpLsh64x64(v) case OpLsh64x8: return rewriteValueAMD64_OpLsh64x8(v) case OpLsh8x16: return rewriteValueAMD64_OpLsh8x16(v) case OpLsh8x32: return rewriteValueAMD64_OpLsh8x32(v) case OpLsh8x64: return rewriteValueAMD64_OpLsh8x64(v) case OpLsh8x8: return rewriteValueAMD64_OpLsh8x8(v) case OpMod16: return rewriteValueAMD64_OpMod16(v) case OpMod16u: return rewriteValueAMD64_OpMod16u(v) case OpMod32: return rewriteValueAMD64_OpMod32(v) case OpMod32u: return rewriteValueAMD64_OpMod32u(v) case OpMod64: return rewriteValueAMD64_OpMod64(v) case OpMod64u: return rewriteValueAMD64_OpMod64u(v) case OpMod8: return rewriteValueAMD64_OpMod8(v) case OpMod8u: return rewriteValueAMD64_OpMod8u(v) case OpMove: return rewriteValueAMD64_OpMove(v) case OpMul16: v.Op = OpAMD64MULL return true case OpMul32: v.Op = OpAMD64MULL return true case OpMul32F: v.Op = OpAMD64MULSS return true case OpMul64: v.Op = OpAMD64MULQ return true case OpMul64F: v.Op = OpAMD64MULSD return true case OpMul64uhilo: v.Op = OpAMD64MULQU2 return true case OpMul8: v.Op = OpAMD64MULL return true case OpNeg16: v.Op = OpAMD64NEGL return true case OpNeg32: v.Op = OpAMD64NEGL return true case OpNeg32F: return rewriteValueAMD64_OpNeg32F(v) case OpNeg64: v.Op = OpAMD64NEGQ return true case OpNeg64F: return rewriteValueAMD64_OpNeg64F(v) case OpNeg8: v.Op = OpAMD64NEGL return true case OpNeq16: return rewriteValueAMD64_OpNeq16(v) case OpNeq32: return rewriteValueAMD64_OpNeq32(v) case OpNeq32F: return rewriteValueAMD64_OpNeq32F(v) case OpNeq64: return rewriteValueAMD64_OpNeq64(v) case OpNeq64F: return rewriteValueAMD64_OpNeq64F(v) case OpNeq8: return rewriteValueAMD64_OpNeq8(v) case OpNeqB: return rewriteValueAMD64_OpNeqB(v) case OpNeqPtr: return rewriteValueAMD64_OpNeqPtr(v) case OpNilCheck: v.Op = OpAMD64LoweredNilCheck return true case OpNot: return rewriteValueAMD64_OpNot(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr(v) case OpOr16: v.Op = OpAMD64ORL return true case OpOr32: v.Op = OpAMD64ORL return true case OpOr64: v.Op = OpAMD64ORQ return true case OpOr8: v.Op = OpAMD64ORL return true case OpOrB: v.Op = OpAMD64ORL return true case OpPanicBounds: return rewriteValueAMD64_OpPanicBounds(v) case OpPopCount16: return rewriteValueAMD64_OpPopCount16(v) case OpPopCount32: v.Op = OpAMD64POPCNTL return true case OpPopCount64: v.Op = OpAMD64POPCNTQ return true case OpPopCount8: return rewriteValueAMD64_OpPopCount8(v) case OpPrefetchCache: v.Op = OpAMD64PrefetchT0 return true case OpPrefetchCacheStreamed: v.Op = OpAMD64PrefetchNTA return true case OpRotateLeft16: v.Op = OpAMD64ROLW return true case OpRotateLeft32: v.Op = OpAMD64ROLL return true case OpRotateLeft64: v.Op = OpAMD64ROLQ return true case OpRotateLeft8: v.Op = OpAMD64ROLB return true case OpRound32F: v.Op = OpCopy return true case OpRound64F: v.Op = OpCopy return true case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven(v) case OpRsh16Ux16: return rewriteValueAMD64_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValueAMD64_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValueAMD64_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValueAMD64_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValueAMD64_OpRsh16x16(v) case OpRsh16x32: return rewriteValueAMD64_OpRsh16x32(v) case OpRsh16x64: return rewriteValueAMD64_OpRsh16x64(v) case OpRsh16x8: return rewriteValueAMD64_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValueAMD64_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValueAMD64_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValueAMD64_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValueAMD64_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValueAMD64_OpRsh32x16(v) case OpRsh32x32: return rewriteValueAMD64_OpRsh32x32(v) case OpRsh32x64: return rewriteValueAMD64_OpRsh32x64(v) case OpRsh32x8: return rewriteValueAMD64_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValueAMD64_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValueAMD64_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValueAMD64_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValueAMD64_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValueAMD64_OpRsh64x16(v) case OpRsh64x32: return rewriteValueAMD64_OpRsh64x32(v) case OpRsh64x64: return rewriteValueAMD64_OpRsh64x64(v) case OpRsh64x8: return rewriteValueAMD64_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValueAMD64_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValueAMD64_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValueAMD64_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValueAMD64_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValueAMD64_OpRsh8x16(v) case OpRsh8x32: return rewriteValueAMD64_OpRsh8x32(v) case OpRsh8x64: return rewriteValueAMD64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8(v) case OpSelect0: return rewriteValueAMD64_OpSelect0(v) case OpSelect1: return rewriteValueAMD64_OpSelect1(v) case OpSelectN: return rewriteValueAMD64_OpSelectN(v) case OpSignExt16to32: v.Op = OpAMD64MOVWQSX return true case OpSignExt16to64: v.Op = OpAMD64MOVWQSX return true case OpSignExt32to64: v.Op = OpAMD64MOVLQSX return true case OpSignExt8to16: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to32: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to64: v.Op = OpAMD64MOVBQSX return true case OpSlicemask: return rewriteValueAMD64_OpSlicemask(v) case OpSpectreIndex: return rewriteValueAMD64_OpSpectreIndex(v) case OpSpectreSliceIndex: return rewriteValueAMD64_OpSpectreSliceIndex(v) case OpSqrt: v.Op = OpAMD64SQRTSD return true case OpSqrt32: v.Op = OpAMD64SQRTSS return true case OpStaticCall: v.Op = OpAMD64CALLstatic return true case OpStore: return rewriteValueAMD64_OpStore(v) case OpSub16: v.Op = OpAMD64SUBL return true case OpSub32: v.Op = OpAMD64SUBL return true case OpSub32F: v.Op = OpAMD64SUBSS return true case OpSub64: v.Op = OpAMD64SUBQ return true case OpSub64F: v.Op = OpAMD64SUBSD return true case OpSub8: v.Op = OpAMD64SUBL return true case OpSubPtr: v.Op = OpAMD64SUBQ return true case OpTailCall: v.Op = OpAMD64CALLtail return true case OpTrunc: return rewriteValueAMD64_OpTrunc(v) case OpTrunc16to8: v.Op = OpCopy return true case OpTrunc32to16: v.Op = OpCopy return true case OpTrunc32to8: v.Op = OpCopy return true case OpTrunc64to16: v.Op = OpCopy return true case OpTrunc64to32: v.Op = OpCopy return true case OpTrunc64to8: v.Op = OpCopy return true case OpWB: v.Op = OpAMD64LoweredWB return true case OpXor16: v.Op = OpAMD64XORL return true case OpXor32: v.Op = OpAMD64XORL return true case OpXor64: v.Op = OpAMD64XORQ return true case OpXor8: v.Op = OpAMD64XORL return true case OpZero: return rewriteValueAMD64_OpZero(v) case OpZeroExt16to32: v.Op = OpAMD64MOVWQZX return true case OpZeroExt16to64: v.Op = OpAMD64MOVWQZX return true case OpZeroExt32to64: v.Op = OpAMD64MOVLQZX return true case OpZeroExt8to16: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to32: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to64: v.Op = OpAMD64MOVBQZX return true } return false } func rewriteValueAMD64_OpAMD64ADCQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) // result: (ADCQconst x [int32(c)] carry) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) carry := v_2 if !(is32Bit(c)) { continue } v.reset(OpAMD64ADCQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, carry) return true } break } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQcarry) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64ADCQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQconst x [c] (FlagEQ)) // result: (ADDQconstcarry x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDL x (MOVLconst [c])) // result: (ADDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAL2) v.AddArg2(y, x) return true } } break } // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAL { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL { continue } y := v_1.Args[0] v.reset(OpAMD64SUBL) v.AddArg2(x, y) return true } break } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDLconst [c] (ADDL x y)) // result: (LEAL1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (SHLLconst [1] x)) // result: (LEAL1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // result: (MOVLconst [c+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c + d) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // result: (ADDLconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDLconst [off] x:(SP)) // result: (LEAL [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (ADDL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ADDQ x (MOVLconst [c])) // result: (ADDQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAQ2) v.AddArg2(y, x) return true } } break } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ { continue } y := v_1.Args[0] v.reset(OpAMD64SUBQ) v.AddArg2(x, y) return true } break } // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQcarry(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQcarry x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconstcarry x [int32(c)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDQconst [c] (ADDQ x y)) // result: (LEAQ1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (SHLQconst [1] x)) // result: (LEAQ1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDQconst [c] (LEAQ [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ADDQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) + d) return true } // match: (ADDQconst [c] (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (ADDQconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDQconst [off] x:(SP)) // result: (LEAQ [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (ADDQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (ADDSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (ADDSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ANDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTRL) v.AddArg2(x, y) return true } break } // match: (ANDL (NOTL (SHLXL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLXL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTRL) v.AddArg2(x, y) return true } break } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } break } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ANDL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDL x (NOTL y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTL { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNL) v.AddArg2(x, y) return true } break } // match: (ANDL x (NEGL x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIL) v.AddArg(x) return true } break } // match: (ANDL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSRL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSRL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDLconst [c] x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDLconst [c] (BTRLconst [d] x)) // result: (ANDLconst [c &^ (1<= 128 // result: (BTRQconst [int8(log64(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log64(^c))) v.AddArg(x) return true } break } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ANDQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDQ x (NOTQ y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTQ { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNQ) v.AddArg2(x, y) return true } break } // match: (ANDQ x (NEGQ x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIQ) v.AddArg(x) return true } break } // match: (ANDQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSRQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSRQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDQconst [c] x) // cond: isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRQconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDQconst [c] (ANDQconst [d] x)) // result: (ANDQconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDQconst [c] (BTRQconst [d] x)) // cond: is32Bit(int64(c) &^ (1< [1<<8] (MOVBQZX x))) // result: (BSFQ (ORQconst [1<<8] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVBQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 8) v0.AddArg(x) v.AddArg(v0) return true } // match: (BSFQ (ORQconst [1<<16] (MOVWQZX x))) // result: (BSFQ (ORQconst [1<<16] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVWQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPL(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPL (BSWAPL p)) // result: p for { if v_0.Op != OpAMD64BSWAPL { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPL x:(MOVLload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPL (MOVBELload [i] {s} p m)) // result: (MOVLload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBELload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPQ(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPQ (BSWAPQ p)) // result: p for { if v_0.Op != OpAMD64BSWAPQ { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPQ x:(MOVQload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPQ (MOVBEQload [i] {s} p m)) // result: (MOVQload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBEQload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BTCLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTCLconst [c] (XORLconst [d] x)) // result: (XORLconst [d ^ 1<d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTLconst [0] s:(SHRXQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 32) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTLconst [c] (SHLLconst [d] x)) // cond: c>d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } // match: (BTLconst [0] s:(SHRXL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTQconst(v *Value) bool { v_0 := v.Args[0] // match: (BTQconst [c] (SHRQconst [d] x)) // cond: (c+d)<64 // result: (BTQconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 64) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTQconst [c] (SHLQconst [d] x)) // cond: c>d // result: (BTQconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTQconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTQconst [0] s:(SHRXQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTRLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTRLconst [c] (BTSLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTSLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (BTCLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTCLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [d &^ (1<uint8(y) // result: (FlagLT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) < y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x) y && uint8(x) < uint8(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) > y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int8(m) && int8(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPBconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTB x y) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, y) return true } // match: (CMPBconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTBconst [int8(c)] x) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt8(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVBload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPBload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPL x (MOVLconst [c])) // result: (CMPLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64CMPLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // result: (InvertFlags (CMPLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPL y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x==y // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x == y) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: xuint32(y) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x < y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x) y && uint32(x) < uint32(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x > y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) // result: (FlagLT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x < y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x)>uint64(y) // result: (FlagGT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x > y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQ l:(MOVQload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPQload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPQ x l:(MOVQload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPQload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPQload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x==int64(y) // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x == int64(y)) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: xuint64(int64(y)) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x < int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x) int64(y) && uint64(x) < uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x)>uint64(int64(y)) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x > int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQconst (MOVBQZX _) [c]) // cond: 0xFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVWQZX _) [c]) // cond: 0xFFFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (SHRQconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 64 && (1<uint16(y) // result: (FlagLT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) < y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x) y && uint16(x) < uint16(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) > y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int16(m) && int16(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPWconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTW x y) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, y) return true } // match: (CMPWconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTWconst [int16(c)] x) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt16(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVWload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPWload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGLlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGQlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64HMULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULL x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULL y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULLU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULLU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULLU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULLU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQ x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQ y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64LEAL(v *Value) bool { v_0 := v.Args[0] // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { v_0 := v.Args[0] // match: (LEAQ [c] {s} (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAQ [c] {s} (ADDQ x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg(x) return true } // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ2 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ4 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ8 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64LEAQ { continue } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(y, x) return true } } break } // match: (LEAQ1 [0] x y) // cond: v.Aux == nil // result: (ADDQ x y) for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 y := v_1 if !(v.Aux == nil) { break } v.reset(OpAMD64ADDQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAQ2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil // result: (LEAQ4 [off1+2*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + 2*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ2 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ2 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAQ4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil // result: (LEAQ8 [off1+4*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + 4*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ4 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ4 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAQ8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ8 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ8 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBELstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBELstore [i] {s} p (BSWAPL x) m) // result: (MOVLstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPL { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEQstore [i] {s} p (BSWAPQ x) m) // result: (MOVQstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPQ { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7f) v.AddArg(x) return true } // match: (MOVBQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x) // cond: zeroUpper56Bits(x,3) // result: x for { x := v_0 if !(zeroUpper56Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVBQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xff) v.AddArg(x) return true } // match: (MOVBQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read8(sym, int64(off)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read8(sym, int64(off)))) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) // cond: y.Uses == 1 // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETL { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) // cond: y.Uses == 1 // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETLE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) // cond: y.Uses == 1 // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETG { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) // cond: y.Uses == 1 // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETGE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) // cond: y.Uses == 1 // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETEQ { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) // cond: y.Uses == 1 // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETNE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) // cond: y.Uses == 1 // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETB { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) // cond: y.Uses == 1 // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETBE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) // cond: y.Uses == 1 // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETA { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) // cond: y.Uses == 1 // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETAE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstore [i-1] {s} p (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p1 w x0:(MOVBstore [i] {s} p0 (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0) // result: (MOVWstore [i] {s} p0 (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-1 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-3 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 3) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p3 w x2:(MOVBstore [i] {s} p2 (SHRLconst [8] w) x1:(MOVBstore [i] {s} p1 (SHRLconst [16] w) x0:(MOVBstore [i] {s} p0 (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2) // result: (MOVLstore [i] {s} p0 (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p3 := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i-1 || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] if p != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i-2 || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i-3 || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i-4 || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-5 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-6 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-7 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 7) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p7 w x6:(MOVBstore [i] {s} p6 (SHRQconst [8] w) x5:(MOVBstore [i] {s} p5 (SHRQconst [16] w) x4:(MOVBstore [i] {s} p4 (SHRQconst [24] w) x3:(MOVBstore [i] {s} p3 (SHRQconst [32] w) x2:(MOVBstore [i] {s} p2 (SHRQconst [40] w) x1:(MOVBstore [i] {s} p1 (SHRQconst [48] w) x0:(MOVBstore [i] {s} p0 (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i] {s} p0 (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p7 := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] p6 := x6.Args[0] x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] p5 := x5.Args[0] x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] p4 := x4.Args[0] x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] p3 := x3.Args[0] x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRWconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [c3] {s} p3 (SHRQconst [56] w) x1:(MOVWstore [c2] {s} p2 (SHRQconst [40] w) x2:(MOVLstore [c1] {s} p1 (SHRQconst [8] w) x3:(MOVBstore [c0] {s} p0 w mem)))) // cond: x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1 + c0 - c1)) && sequentialAddresses(p0, p2, int64(5 + c0 - c2)) && sequentialAddresses(p0, p3, int64(7 + c0 - c3)) && clobber(x1, x2, x3) // result: (MOVQstore [c0] {s} p0 w mem) for { c3 := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p3 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 56 { break } w := v_1.Args[0] x1 := v_2 if x1.Op != OpAMD64MOVWstore { break } c2 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p2 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 40 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpAMD64MOVLstore { break } c1 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p1 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpAMD64MOVBstore { break } c0 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { break } mem := x3.Args[2] p0 := x3.Args[0] if w != x3.Args[1] || !(x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1+c0-c1)) && sequentialAddresses(p0, p2, int64(5+c0-c2)) && sequentialAddresses(p0, p3, int64(7+c0-c3)) && clobber(x1, x2, x3)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(c0) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVBload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVBstore || auxIntToInt32(mem2.AuxInt) != i-1 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVBload || auxIntToInt32(x2.AuxInt) != j-1 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(j - 1) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [c] {s} p1 x:(MOVBstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVBstoreconst [a] {s} p0 x:(MOVBstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX (ANDLconst [c] x)) // cond: uint32(c) & 0x80000000 == 0 // result: (ANDLconst [c & 0x7fffffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(uint32(c)&0x80000000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fffffff) v.AddArg(x) return true } // match: (MOVLQSX (MOVLQSX x)) // result: (MOVLQSX x) for { if v_0.Op != OpAMD64MOVLQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x) // cond: zeroUpper32Bits(x,3) // result: x for { x := v_0 if !(zeroUpper32Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVLQZX (ANDLconst [c] x)) // result: (ANDLconst [c] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (MOVLQZX (MOVLQZX x)) // result: (MOVLQZX x) for { if v_0.Op != OpAMD64MOVLQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLf2i) v.AddArg(val) return true } // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [32] w) x:(MOVLstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [j] w) x:(MOVLstore [i] {s} p0 w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVLload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVLstore || auxIntToInt32(mem2.AuxInt) != i-4 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVLload || auxIntToInt32(x2.AuxInt) != j-4 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(j - 4) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) // result: (MOVSSstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [i] {s} p x:(BSWAPL w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPL { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [c] {s} p1 x:(MOVLstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p0, v0, mem) return true } // match: (MOVLstoreconst [a] {s} p0 x:(MOVLstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p0, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) // cond: symIsRO(srcSym) // result: (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))]) (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))]) mem)) for { dstOff := auxIntToInt32(v.AuxInt) dstSym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVOload { break } srcOff := auxIntToInt32(v_1.AuxInt) srcSym := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } mem := v_2 if !(symIsRO(srcSym)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(dstOff + 8) v.Aux = symToAux(dstSym) v0 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))) v1 := b.NewValue0(v_1.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AuxInt = int32ToAuxInt(dstOff) v1.Aux = symToAux(dstSym) v2 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))) v1.AddArg3(ptr, v2, mem) v.AddArg3(ptr, v0, v1) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVOstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.copyOf(x) return true } // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) // result: (MOVQf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQf2i) v.AddArg(val) return true } // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validVal(c) // result: (MOVQstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(validVal(c)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) // result: (MOVSDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [i] {s} p x:(BSWAPQ w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPQ { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [c] {s} p1 x:(MOVQstoreconst [a] {s} p0 mem)) // cond: config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVQstoreconst [a] {s} p0 x:(MOVQstoreconst [c] {s} p1 mem)) // cond: config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fff) v.AddArg(x) return true } // match: (MOVWQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x) // cond: zeroUpper48Bits(x,3) // result: x for { x := v_0 if !(zeroUpper48Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVWQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xffff) v.AddArg(x) return true } // match: (MOVWQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVWload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVWstore || auxIntToInt32(mem2.AuxInt) != i-2 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVWload || auxIntToInt32(x2.AuxInt) != j-2 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(j - 2) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [c] {s} p1 x:(MOVWstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVWstoreconst [a] {s} p0 x:(MOVWstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULL x (MOVLconst [c])) // result: (MULLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULLconst [c] (MULLconst [d] x)) // result: (MULLconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULLconst [-9] x) // result: (NEGL (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // result: (NEGL (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // result: (NEGL (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // result: (NEGL x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGL) v.AddArg(x) return true } // match: (MULLconst [ 0] _) // result: (MOVLconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (MULLconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULLconst [ 3] x) // result: (LEAL2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAL2) v.AddArg2(x, x) return true } // match: (MULLconst [ 5] x) // result: (LEAL4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAL4) v.AddArg2(x, x) return true } // match: (MULLconst [ 7] x) // result: (LEAL2 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [ 9] x) // result: (LEAL8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAL8) v.AddArg2(x, x) return true } // match: (MULLconst [11] x) // result: (LEAL2 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [13] x) // result: (LEAL4 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [19] x) // result: (LEAL2 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [21] x) // result: (LEAL4 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [25] x) // result: (LEAL8 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [27] x) // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [37] x) // result: (LEAL4 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [41] x) // result: (LEAL8 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [45] x) // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [73] x) // result: (LEAL8 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [81] x) // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBL (SHLLconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAL1) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLLconst [int8(log32(c/3))] (LEAL2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLLconst [int8(log32(c/5))] (LEAL4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLLconst [int8(log32(c/9))] (LEAL8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] (MOVLconst [d])) // result: (MOVLconst [c*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c * d) return true } return false } func rewriteValueAMD64_OpAMD64MULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (MULQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULQconst [c] (MULQconst [d] x)) // cond: is32Bit(int64(c)*int64(d)) // result: (MULQconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) * int64(d))) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULQconst [-9] x) // result: (NEGQ (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-5] x) // result: (NEGQ (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-3] x) // result: (NEGQ (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-1] x) // result: (NEGQ x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGQ) v.AddArg(x) return true } // match: (MULQconst [ 0] _) // result: (MOVQconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MULQconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULQconst [ 3] x) // result: (LEAQ2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAQ2) v.AddArg2(x, x) return true } // match: (MULQconst [ 5] x) // result: (LEAQ4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAQ4) v.AddArg2(x, x) return true } // match: (MULQconst [ 7] x) // result: (LEAQ2 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [ 9] x) // result: (LEAQ8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAQ8) v.AddArg2(x, x) return true } // match: (MULQconst [11] x) // result: (LEAQ2 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [13] x) // result: (LEAQ4 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [19] x) // result: (LEAQ2 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [21] x) // result: (LEAQ4 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [25] x) // result: (LEAQ8 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [27] x) // result: (LEAQ8 (LEAQ2 x x) (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [37] x) // result: (LEAQ4 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [41] x) // result: (LEAQ8 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [45] x) // result: (LEAQ8 (LEAQ4 x x) (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [73] x) // result: (LEAQ8 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [81] x) // result: (LEAQ8 (LEAQ8 x x) (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBQ (SHLQconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAQ1 (SHLQconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAQ1) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAQ2 (SHLQconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAQ4 (SHLQconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAQ8 (SHLQconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLQconst [int8(log32(c/3))] (LEAQ2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLQconst [int8(log32(c/5))] (LEAQ4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLQconst [int8(log32(c/9))] (LEAQ8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) * d) return true } // match: (MULQconst [c] (NEGQ x)) // cond: c != -(1<<31) // result: (MULQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (MULSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64MULSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (MULSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64NEGL(v *Value) bool { v_0 := v.Args[0] // match: (NEGL (NEGL x)) // result: x for { if v_0.Op != OpAMD64NEGL { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGL s:(SUBL x y)) // cond: s.Uses == 1 // result: (SUBL y x) for { s := v_0 if s.Op != OpAMD64SUBL { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBL) v.AddArg2(y, x) return true } // match: (NEGL (MOVLconst [c])) // result: (MOVLconst [-c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-c) return true } return false } func rewriteValueAMD64_OpAMD64NEGQ(v *Value) bool { v_0 := v.Args[0] // match: (NEGQ (NEGQ x)) // result: x for { if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGQ s:(SUBQ x y)) // cond: s.Uses == 1 // result: (SUBQ y x) for { s := v_0 if s.Op != OpAMD64SUBQ { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBQ) v.AddArg2(y, x) return true } // match: (NEGQ (MOVQconst [c])) // result: (MOVQconst [-c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-c) return true } // match: (NEGQ (ADDQconst [c] (NEGQ x))) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { if v_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } x := v_0_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64NOTL(v *Value) bool { v_0 := v.Args[0] // match: (NOTL (MOVLconst [c])) // result: (MOVLconst [^c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64NOTQ(v *Value) bool { v_0 := v.Args[0] // match: (NOTQ (MOVQconst [c])) // result: (MOVQconst [^c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64ORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTSL) v.AddArg2(x, y) return true } break } // match: (ORL (SHLXL (MOVLconst [1]) y) x) // result: (BTSL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTSL) v.AddArg2(x, y) return true } break } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORL x0:(MOVBload [i0] {s} p mem) sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVBload [i] {s} p0 mem) sh:(SHLLconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVWload [i] {s} p0 mem) sh:(SHLLconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL x1:(MOVBload [i] {s} p1 mem) sh:(SHLLconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORLconst(v *Value) bool { v_0 := v.Args[0] // match: (ORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORLconst [c] (ORLconst [d] x)) // result: (ORLconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORLconst [c] (BTSLconst [d] x)) // result: (ORLconst [c | 1<= 128 // result: (BTSQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ORQ x (MOVLconst [c])) // result: (ORQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORQ (SHRQ lo bits) (SHLQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLQ lo bits) (SHRQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHRXQ lo bits) (SHLXQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLXQ lo bits) (SHRXQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (MOVQconst [c]) (MOVQconst [d])) // result: (MOVQconst [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c | d) return true } break } // match: (ORQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORQ x0:(MOVBload [i0] {s} p mem) sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBload [i] {s} p0 mem) sh:(SHLQconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVWload [i] {s} p0 mem) sh:(SHLQconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVLload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVLload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i] {s} p0 mem)) y)) // cond: j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ x1:(MOVBload [i] {s} p1 mem) sh:(SHLQconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i] {s} p1 mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem))) y)) // cond: j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ORQ x0:(MOVBELload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVBELload [i1] {s} p mem))) // cond: i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i1] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i1) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBELload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVBELload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i] {s} p1 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p1, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQconst(v *Value) bool { v_0 := v.Args[0] // match: (ORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORQconst [c] (ORQconst [d] x)) // result: (ORQconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORQconst [c] (BTSQconst [d] x)) // cond: is32Bit(int64(c) | 1<>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int8(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARL x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SARXL x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (MOVLconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SARLconst(v *Value) bool { v_0 := v.Args[0] // match: (SARLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARLconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int32(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int32(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SARXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (MOVLconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SARQconst(v *Value) bool { v_0 := v.Args[0] // match: (SARQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARQconst [c] (MOVQconst [d])) // result: (MOVQconst [d>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SARW x (MOVQconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } // match: (SARW x (MOVLconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SARWconst(v *Value) bool { v_0 := v.Args[0] // match: (SARWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARWconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int16(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int16(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARXL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARXL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARXL x (MOVLconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARXL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SARXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SARXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SARLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARXQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARXQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARXQ x (MOVLconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARXQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SARXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SARXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SARXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SBBLcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBLcarrymask (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagLT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagGT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQ x (MOVQconst [c]) borrow) // cond: is32Bit(c) // result: (SBBQconst x [int32(c)] borrow) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) borrow := v_2 if !(is32Bit(c)) { break } v.reset(OpAMD64SBBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, borrow) return true } // match: (SBBQ x y (FlagEQ)) // result: (SUBQborrow x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQborrow) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64SBBQcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBQcarrymask (FlagEQ)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagLT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagLT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagGT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagGT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQconst x [c] (FlagEQ)) // result: (SUBQconstborrow x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SETA(v *Value) bool { v_0 := v.Args[0] // match: (SETA (InvertFlags x)) // result: (SETB x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETA (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAE(v *Value) bool { v_0 := v.Args[0] // match: (SETAE (TESTQ x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTL x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTW x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTB x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (InvertFlags x)) // result: (SETBE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETAstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETB(v *Value) bool { v_0 := v.Args[0] // match: (SETB (TESTQ x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTL x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTW x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTB x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (BTLconst [0] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64BTLconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (BTQconst [0] x)) // result: (ANDQconst [1] x) for { if v_0.Op != OpAMD64BTQconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (InvertFlags x)) // result: (SETA x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBE(v *Value) bool { v_0 := v.Args[0] // match: (SETBE (InvertFlags x)) // result: (SETAE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETBE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAE (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAE (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETNE (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETEQ (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETEQstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETG(v *Value) bool { v_0 := v.Args[0] // match: (SETG (InvertFlags x)) // result: (SETL x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETG (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGE(v *Value) bool { v_0 := v.Args[0] // match: (SETGE (InvertFlags x)) // result: (SETLE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETL(v *Value) bool { v_0 := v.Args[0] // match: (SETL (InvertFlags x)) // result: (SETG x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLE(v *Value) bool { v_0 := v.Args[0] // match: (SETLE (InvertFlags x)) // result: (SETGE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETLE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNE(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETNE (TESTBconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTBconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTWconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTWconst || auxIntToInt16(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETB (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETB (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETEQ (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (InvertFlags x)) // result: (SETNE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETNE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETNEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLL x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHLXL x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (MOVLconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLLconst [1] (SHRLconst [1] x)) // result: (BTRLconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLLconst [d] (MOVLconst [c])) // result: (MOVLconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHLXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (MOVLconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLQconst [1] (SHRQconst [1] x)) // result: (BTRQconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLQconst [d] (MOVQconst [c])) // result: (MOVQconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c << uint64(d)) return true } // match: (SHLQconst [d] (MOVLconst [c])) // result: (MOVQconst [int64(c) << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLXL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLXL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLXL x (MOVLconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLXL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHLXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHLXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHLLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLXQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLXQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLXQ x (MOVLconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLXQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHLXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHLXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SHLXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRB x (MOVQconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB _ (MOVQconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRBconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRBconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRL x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHRXL x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (MOVLconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRLconst [1] (SHLLconst [1] x)) // result: (BTRLconst [31] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(31) v.AddArg(x) return true } // match: (SHRLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHRXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (MOVLconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRQconst [1] (SHLQconst [1] x)) // result: (BTRQconst [63] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(63) v.AddArg(x) return true } // match: (SHRQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRW x (MOVQconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW _ (MOVQconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRWconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRXL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRXL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRXL x (MOVLconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRXL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHRXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHRXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHRLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRXQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRXQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRXQ x (MOVLconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRXQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHRXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHRXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SHRXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBL x (MOVLconst [c])) // result: (SUBLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SUBLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // result: (NEGL (SUBLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBLconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (SUBLconst [c] x) // result: (ADDLconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } } func rewriteValueAMD64_OpAMD64SUBLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (SUBL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconst x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } // match: (SUBQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (NEGQ (SUBQconst x [int32(c)])) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBQload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQborrow(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQborrow x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconstborrow x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SUBQconst [c] x) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } // match: (SUBQconst (MOVQconst [d]) [c]) // result: (MOVQconst [d-int64(c)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d - int64(c)) return true } // match: (SUBQconst (SUBQconst x [d]) [c]) // cond: is32Bit(int64(-c)-int64(d)) // result: (ADDQconst [-c-d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SUBQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(-c) - int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c - d) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (SUBQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (SUBSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (SUBSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64TESTB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [int8(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } break } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVBload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTBconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTBconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTL a:(ANDLload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTL (MOVLload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDLload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTL) v0 := b.NewValue0(a.Pos, OpAMD64MOVLload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTLconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTLconst [c] (MOVLconst [c])) // cond: c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTLconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTL x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTL) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (TESTQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { continue } v.reset(OpAMD64TESTQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTQ a:(ANDQload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTQ (MOVQload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDQload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTQ) v0 := b.NewValue0(a.Pos, OpAMD64MOVQload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTQconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTQconst [-1] x) // cond: x.Op != OpAMD64MOVQconst // result: (TESTQ x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVQconst) { break } v.reset(OpAMD64TESTQ) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [int16(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } break } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVWload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTWconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTWconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64XADDLlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDLlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XADDQlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDQlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGL(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGL [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGQ [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTCL) v.AddArg2(x, y) return true } break } // match: (XORL (SHLXL (MOVLconst [1]) y) x) // result: (BTCL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTCL) v.AddArg2(x, y) return true } break } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORLconst(v *Value) bool { v_0 := v.Args[0] // match: (XORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORLconst [1] (SETNE x)) // result: (SETEQ x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETNE { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (XORLconst [1] (SETEQ x)) // result: (SETNE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETEQ { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (XORLconst [1] (SETL x)) // result: (SETGE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETL { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (XORLconst [1] (SETGE x)) // result: (SETL x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETGE { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (XORLconst [1] (SETLE x)) // result: (SETG x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETLE { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (XORLconst [1] (SETG x)) // result: (SETLE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETG { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (XORLconst [1] (SETB x)) // result: (SETAE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETB { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (XORLconst [1] (SETAE x)) // result: (SETB x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETAE { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (XORLconst [1] (SETBE x)) // result: (SETA x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETBE { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (XORLconst [1] (SETA x)) // result: (SETBE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETA { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (XORLconst [c] (XORLconst [d] x)) // result: (XORLconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORLconst [c] (BTCLconst [d] x)) // result: (XORLconst [c ^ 1<= 128 // result: (BTCQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (XORQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORQconst(v *Value) bool { v_0 := v.Args[0] // match: (XORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORQconst [c] (XORQconst [d] x)) // result: (XORQconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORQconst [c] (BTCQconst [d] x)) // cond: is32Bit(int64(c) ^ 1< val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore64(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore64 ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore8 ptr val mem) // result: (Select1 (XCHGB val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStorePtrNoWB(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStorePtrNoWB ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen16 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen16 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVWQZX x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, x.Type) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) v1.AuxInt = int32ToAuxInt(1) v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v2.AddArg(x) v1.AddArg2(v2, v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (BitLen32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // cond: buildcfg.GOAMD64 < 3 // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(1) v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) v1 := b.NewValue0(v.Pos, OpSelect0, t) v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v3.AuxInt = int64ToAuxInt(-1) v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4.AddArg(v2) v0.AddArg3(v1, v3, v4) v.AddArg(v0) return true } // match: (BitLen64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-64] (LZCNTQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-64) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTQ, typ.UInt64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen8 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen8 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVBQZX x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, x.Type) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCeil(v *Value) bool { v_0 := v.Args[0] // match: (Ceil x) // result: (ROUNDSD [2] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(2) v.AddArg(x) return true } } func rewriteValueAMD64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (CondSelect x y (SETEQ cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is32BitInt(t) // result: (CMOVLEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is32BitInt(t) // result: (CMOVLNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is32BitInt(t) // result: (CMOVLLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is32BitInt(t) // result: (CMOVLGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is32BitInt(t) // result: (CMOVLLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is32BitInt(t) // result: (CMOVLGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is32BitInt(t) // result: (CMOVLHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is32BitInt(t) // result: (CMOVLCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is32BitInt(t) // result: (CMOVLCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is32BitInt(t) // result: (CMOVLLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is32BitInt(t) // result: (CMOVLEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is32BitInt(t) // result: (CMOVLNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is32BitInt(t) // result: (CMOVLGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is32BitInt(t) // result: (CMOVLGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is16BitInt(t) // result: (CMOVWEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is16BitInt(t) // result: (CMOVWNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is16BitInt(t) // result: (CMOVWLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is16BitInt(t) // result: (CMOVWGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is16BitInt(t) // result: (CMOVWLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is16BitInt(t) // result: (CMOVWGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is16BitInt(t) // result: (CMOVWHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is16BitInt(t) // result: (CMOVWCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is16BitInt(t) // result: (CMOVWCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is16BitInt(t) // result: (CMOVWLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is16BitInt(t) // result: (CMOVWEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is16BitInt(t) // result: (CMOVWNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is16BitInt(t) // result: (CMOVWGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is16BitInt(t) // result: (CMOVWGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 1 // result: (CondSelect x y (MOVBQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 1) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 2 // result: (CondSelect x y (MOVWQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 2) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 4 // result: (CondSelect x y (MOVLQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 4) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { break } v.reset(OpAMD64CMOVQNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) // result: (CMOVLNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) // result: (CMOVWNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } return false } func rewriteValueAMD64_OpConst16(v *Value) bool { // match: (Const16 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt16(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConst8(v *Value) bool { // match: (Const8 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt8(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConstBool(v *Value) bool { // match: (ConstBool [c]) // result: (MOVLconst [b2i32(c)]) for { c := auxIntToBool(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(b2i32(c)) return true } } func rewriteValueAMD64_OpConstNil(v *Value) bool { // match: (ConstNil ) // result: (MOVQconst [0]) for { v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } } func rewriteValueAMD64_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (BSFL (BTSLconst [16] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(16) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz16NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ (BTSQconst [32] x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) v1.AuxInt = int8ToAuxInt(32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz32NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64 x) // cond: buildcfg.GOAMD64 < 3 // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v3.AddArg(v1) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueAMD64_OpCtz64NonZero(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ x)) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (BSFL (BTSLconst [ 8] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 [a] x y) // result: (Select0 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (Select0 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32 [a] x y) // result: (Select0 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32u x y) // result: (Select0 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64 [a] x y) // result: (Select0 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64u x y) // result: (Select0 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq16 x y) // result: (SETEQ (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32 x y) // result: (SETEQ (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32F x y) // result: (SETEQF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64 x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64F x y) // result: (SETEQF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq8 x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqB x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqPtr x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpFMA(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMA x y z) // result: (VFMADD231SD z x y) for { x := v_0 y := v_1 z := v_2 v.reset(OpAMD64VFMADD231SD) v.AddArg3(z, x, y) return true } } func rewriteValueAMD64_OpFloor(v *Value) bool { v_0 := v.Args[0] // match: (Floor x) // result: (ROUNDSD [1] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpGetG(v *Value) bool { v_0 := v.Args[0] // match: (GetG mem) // cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal // result: (LoweredGetG mem) for { mem := v_0 if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) { break } v.reset(OpAMD64LoweredGetG) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (HasCPUFeature {s}) // result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s}))) for { s := auxToSym(v.Aux) v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64) v1.Aux = symToAux(s) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsInBounds idx len) // result: (SETB (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsNonNil(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (IsNonNil p) // result: (SETNE (TESTQ p p)) for { p := v_0 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) v0.AddArg2(p, p) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsSliceInBounds idx len) // result: (SETBE (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16 x y) // result: (SETLE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16U x y) // result: (SETBE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32 x y) // result: (SETLE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32F x y) // result: (SETGEF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32U x y) // result: (SETBE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64 x y) // result: (SETLE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64F x y) // result: (SETGEF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64U x y) // result: (SETBE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8 x y) // result: (SETLE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8U x y) // result: (SETBE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16 x y) // result: (SETL (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16U x y) // result: (SETB (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 x y) // result: (SETL (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32F x y) // result: (SETGF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32U x y) // result: (SETB (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 x y) // result: (SETL (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64F x y) // result: (SETGF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64U x y) // result: (SETB (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8 x y) // result: (SETL (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8U x y) // result: (SETB (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVQload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64MOVQload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) // result: (MOVLload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t)) { break } v.reset(OpAMD64MOVLload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t)) { break } v.reset(OpAMD64MOVWload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(OpAMD64MOVBload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitFloat(t)) { break } v.reset(OpAMD64MOVSSload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitFloat(t)) { break } v.reset(OpAMD64MOVSDload) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpLocalAddr(v *Value) bool { v_0 := v.Args[0] // match: (LocalAddr {sym} base _) // result: (LEAQ {sym} base) for { sym := auxToSym(v.Aux) base := v_0 v.reset(OpAMD64LEAQ) v.Aux = symToAux(sym) v.AddArg(base) return true } } func rewriteValueAMD64_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16 [a] x y) // result: (Select1 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Select1 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32 [a] x y) // result: (Select1 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (Select1 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64 [a] x y) // result: (Select1 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (Select1 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [2] dst src mem) // result: (MOVWstore dst (MOVWload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [4] dst src mem) // result: (MOVLstore dst (MOVLload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [8] dst src mem) // result: (MOVQstore dst (MOVQload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVQstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: config.useSSE // result: (MOVOstore dst (MOVOload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: !config.useSSE // result: (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [32] dst src mem) // result: (Move [16] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpMove) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [48] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 48 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [64] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [32]) (OffPtr src [32]) (Move [32] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 64 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(32) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(32) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(32) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(2) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [6] dst src mem) // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [7] dst src mem) // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [10] dst src mem) // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [12] dst src mem) // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s == 11 || s >= 13 && s <= 15 // result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s == 11 || s >= 13 && s <= 15) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(int32(s - 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(int32(s - 8)) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 <= 8 // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 <= 8) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVOstore dst (MOVOload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AuxInt = int32ToAuxInt(8) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AuxInt = int32ToAuxInt(8) v3.AddArg2(src, mem) v4 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v5 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v5.AddArg2(src, mem) v4.AddArg3(dst, v5, mem) v2.AddArg3(dst, v3, v4) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s) // result: (DUFFCOPY [s] dst src mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s)) { break } v.reset(OpAMD64DUFFCOPY) v.AuxInt = int64ToAuxInt(s) v.AddArg3(dst, src, mem) return true } // match: (Move [s] dst src mem) // cond: (s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s) // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !((s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s)) { break } v.reset(OpAMD64REPMOVSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v.AddArg4(dst, src, v0, mem) return true } return false } func rewriteValueAMD64_OpNeg32F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg32F x) // result: (PXOR x (MOVSSconst [float32(math.Copysign(0, -1))])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1))) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeg64F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg64F x) // result: (PXOR x (MOVSDconst [math.Copysign(0, -1)])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) v0.AuxInt = float64ToAuxInt(math.Copysign(0, -1)) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq16 x y) // result: (SETNE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32 x y) // result: (SETNE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32F x y) // result: (SETNEF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64 x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64F x y) // result: (SETNEF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq8 x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqB x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqPtr x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNot(v *Value) bool { v_0 := v.Args[0] // match: (Not x) // result: (XORLconst [1] x) for { x := v_0 v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // cond: is32Bit(off) // result: (ADDQconst [int32(off)] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 if !(is32Bit(off)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(off)) v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDQ (MOVQconst [off]) ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(off) v.AddArg2(v0, ptr) return true } } func rewriteValueAMD64_OpPanicBounds(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 0) { break } v.reset(OpAMD64LoweredPanicBoundsA) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 1) { break } v.reset(OpAMD64LoweredPanicBoundsB) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 2) { break } v.reset(OpAMD64LoweredPanicBoundsC) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } return false } func rewriteValueAMD64_OpPopCount16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTL (MOVWQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpPopCount8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTL (MOVBQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpRoundToEven(v *Value) bool { v_0 := v.Args[0] // match: (RoundToEven x) // result: (ROUNDSD [0] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } } func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpSelect0(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uover x y)) // result: (Select0 (MULQU x y)) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Mul32uover x y)) // result: (Select0 (MULLU x y)) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y c)) // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst32 val tuple)) // result: (ADDL val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDL) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } // match: (Select0 (AddTupleFirst64 val tuple)) // result: (ADDQ val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } return false } func rewriteValueAMD64_OpSelect1(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uover x y)) // result: (SETO (Select1 (MULQU x y))) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul32uover x y)) // result: (SETO (Select1 (MULLU x y))) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Add64carry x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (NEGLflags (MOVQconst [0]))) // result: (FlagEQ) for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 0 { break } v.reset(OpAMD64FlagEQ) return true } // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) // result: x for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64SBBQcarrymask { break } x := v_0_0_0.Args[0] v.copyOf(x) return true } // match: (Select1 (AddTupleFirst32 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } // match: (Select1 (AddTupleFirst64 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } return false } func rewriteValueAMD64_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem))))) // cond: sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call) // result: (Move [sc.Val64()] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpAMD64MOVQstoreconst { break } sc := auxIntToValAndOff(s1.AuxInt) _ = s1.Args[1] s2 := s1.Args[1] if s2.Op != OpAMD64MOVQstore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpAMD64MOVQstore { break } mem := s3.Args[2] dst := s3.Args[1] if !(sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sc.Val64()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem)) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpAMD64MOVQconst { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } return false } func rewriteValueAMD64_OpSlicemask(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Slicemask x) // result: (SARQconst (NEGQ x) [63]) for { t := v.Type x := v_0 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(63) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpSpectreIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreIndex x y) // result: (CMOVQCC x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQCC) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpSpectreSliceIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreSliceIndex x y) // result: (CMOVQHI x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQHI) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && is64BitFloat(val.Type) // result: (MOVSDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSDstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && is32BitFloat(val.Type) // result: (MOVSSstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSSstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 // result: (MOVQstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8) { break } v.reset(OpAMD64MOVQstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 // result: (MOVLstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4) { break } v.reset(OpAMD64MOVLstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 2 // result: (MOVWstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 2) { break } v.reset(OpAMD64MOVWstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 1 // result: (MOVBstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 1) { break } v.reset(OpAMD64MOVBstore) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpTrunc(v *Value) bool { v_0 := v.Args[0] // match: (Trunc x) // result: (ROUNDSD [3] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(3) v.AddArg(x) return true } } func rewriteValueAMD64_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [0] _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_1 v.copyOf(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [2] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [4] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [8] destptr mem) // result: (MOVQstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 2)) v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [5] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [6] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [7] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 3)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%8 != 0 && s > 8 && !config.useSSE // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%8 != 0 && s > 8 && !config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%8) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [24] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 24 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [32] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 24)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 8 && s < 16 && config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,int32(s-8))] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 8 && s < 16 && config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, int32(s-8))) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [32] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [48] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [64] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,48)] destptr (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 48)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice // result: (DUFFZERO [s] destptr mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFZERO) v.AuxInt = int64ToAuxInt(s) v.AddArg2(destptr, mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0 // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !((s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0) { break } v.reset(OpAMD64REPSTOSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(0) v.AddArg4(destptr, v0, v1, mem) return true } return false } func rewriteBlockAMD64(b *Block) bool { typ := &b.Func.Config.Types switch b.Kind { case BlockAMD64EQ: // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (UGE (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (UGE (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64GE: // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64GT: // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockIf: // match: (If (SETL cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64SETL { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (If (SETLE cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64SETLE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (If (SETG cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64SETG { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (If (SETGE cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64SETGE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (If (SETEQ cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64SETEQ { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (If (SETNE cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64SETNE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (If (SETB cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64SETB { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (If (SETBE cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64SETBE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (If (SETA cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETA { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETAE cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETAE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETO cmp) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64SETO { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (If (SETGF cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETGF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETGEF cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETGEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETEQF cmp) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64SETEQF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (If (SETNEF cmp) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64SETNEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (If cond yes no) // result: (NE (TESTB cond cond) yes no) for { cond := b.Controls[0] v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) v0.AddArg2(cond, cond) b.resetWithControl(BlockAMD64NE, v0) return true } case BlockJumpTable: // match: (JumpTable idx) // result: (JUMPTABLE {makeJumpTableSym(b)} idx (LEAQ {makeJumpTableSym(b)} (SB))) for { idx := b.Controls[0] v0 := b.NewValue0(b.Pos, OpAMD64LEAQ, typ.Uintptr) v0.Aux = symToAux(makeJumpTableSym(b)) v1 := b.NewValue0(b.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) b.resetWithControl2(BlockAMD64JUMPTABLE, idx, v0) b.Aux = symToAux(makeJumpTableSym(b)) return true } case BlockAMD64LE: // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64LT: // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETL { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETLE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETG { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQ { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETB { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETBE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETA { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETAE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETO { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (ULT (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (ULT (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGE: // match: (UGE (TESTQ x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTL x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTW x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTB x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (UGE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (UGE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGT: // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (UGT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64ULE: // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (ULE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64ULT: // match: (ULT (TESTQ x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTL x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTW x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTB x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (ULT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- diff -- @@ -1276,80 +1276,6 @@ } break } - // match: (ADDL (SHLLconst x [c]) (SHRLconst x [d])) - // cond: d==32-c - // result: (ROLLconst x [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRLconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 32-c) { - continue - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (ADDL (SHLLconst x [c]) (SHRWconst x [d])) - // cond: d==16-c && c < 16 && t.Size() == 2 - // result: (ROLWconst x [c]) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRWconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - continue - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (ADDL (SHLLconst x [c]) (SHRBconst x [d])) - // cond: d==8-c && c < 8 && t.Size() == 1 - // result: (ROLBconst x [c]) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRBconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - continue - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { @@ -1915,30 +1841,6 @@ } break } - // match: (ADDQ (SHLQconst x [c]) (SHRQconst x [d])) - // cond: d==64-c - // result: (ROLQconst x [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLQconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRQconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 64-c) { - continue - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { @@ -7516,40 +7418,6 @@ func rewriteValueAMD64_OpAMD64CMPQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block - // match: (CMPQconst (NEGQ (ADDQconst [-16] (ANDQconst [15] _))) [32]) - // result: (FlagLT_ULT) - for { - if auxIntToInt32(v.AuxInt) != 32 || v_0.Op != OpAMD64NEGQ { - break - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_0_0.AuxInt) != -16 { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_0_0.AuxInt) != 15 { - break - } - v.reset(OpAMD64FlagLT_ULT) - return true - } - // match: (CMPQconst (NEGQ (ADDQconst [ -8] (ANDQconst [7] _))) [32]) - // result: (FlagLT_ULT) - for { - if auxIntToInt32(v.AuxInt) != 32 || v_0.Op != OpAMD64NEGQ { - break - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_0_0.AuxInt) != -8 { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_0_0.AuxInt) != 7 { - break - } - v.reset(OpAMD64FlagLT_ULT) - return true - } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x==int64(y) // result: (FlagEQ) @@ -16107,1312 +15975,6 @@ } break } - // match: (ORL (SHLLconst x [c]) (SHRLconst x [d])) - // cond: d==32-c - // result: (ROLLconst x [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRLconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 32-c) { - continue - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (ORL (SHLLconst x [c]) (SHRWconst x [d])) - // cond: d==16-c && c < 16 && t.Size() == 2 - // result: (ROLWconst x [c]) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRWconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - continue - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (ORL (SHLLconst x [c]) (SHRBconst x [d])) - // cond: d==8-c && c < 8 && t.Size() == 1 - // result: (ROLBconst x [c]) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRBconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - continue - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) - // result: (ROLL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) - // result: (ROLL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) - // result: (RORL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) - // result: (RORL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLXL x y) (ANDL (SHRXL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) - // result: (ROLL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRXL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLXL x y) (ANDL (SHRXL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) - // result: (ROLL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRXL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRXL x y) (ANDL (SHLXL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) - // result: (RORL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRXL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRXL x y) (ANDL (SHLXL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) - // result: (RORL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRXL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRW { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64ROLW) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRW { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64ROLW) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRW x (ANDQconst y [15])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) - // cond: v.Type.Size() == 2 - // result: (RORW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRW { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64RORW) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHRW x (ANDLconst y [15])) (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) - // cond: v.Type.Size() == 2 - // result: (RORW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRW { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGL { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64RORW) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHLXL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRW { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64ROLW) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLXL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRW { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64ROLW) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRW x (ANDQconst y [15])) (SHLXL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) - // cond: v.Type.Size() == 2 - // result: (RORW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRW { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLXL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64RORW) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHRW x (ANDLconst y [15])) (SHLXL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) - // cond: v.Type.Size() == 2 - // result: (RORW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRW { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLXL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGL { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64RORW) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRB { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64ROLB) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRB { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64ROLB) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) - // cond: v.Type.Size() == 1 - // result: (RORB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRB { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64RORB) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) - // cond: v.Type.Size() == 1 - // result: (RORB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRB { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGL { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64RORB) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHLXL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRB { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64ROLB) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLXL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRB { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64ROLB) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLXL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) - // cond: v.Type.Size() == 1 - // result: (RORB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRB { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLXL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64RORB) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLXL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) - // cond: v.Type.Size() == 1 - // result: (RORB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRB { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLXL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGL { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64RORB) - v.AddArg2(x, y) - return true - } - break - } // match: (ORL x x) // result: x for { @@ -18381,430 +16943,6 @@ } break } - // match: (ORQ (SHLQconst x [c]) (SHRQconst x [d])) - // cond: d==64-c - // result: (ROLQconst x [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLQconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRQconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 64-c) { - continue - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) - // result: (ROLQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) - // result: (ROLQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) - // result: (RORQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) - // result: (RORQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHLXQ x y) (ANDQ (SHRXQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) - // result: (ROLQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRXQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHLXQ x y) (ANDQ (SHRXQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) - // result: (ROLQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRXQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHRXQ x y) (ANDQ (SHLXQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) - // result: (RORQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRXQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHRXQ x y) (ANDQ (SHLXQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) - // result: (RORQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRXQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORQ) - v.AddArg2(x, y) - return true - } - } - break - } // match: (ORQ (SHRQ lo bits) (SHLQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { @@ -20356,20 +18494,6 @@ } func rewriteValueAMD64_OpAMD64ROLBconst(v *Value) bool { v_0 := v.Args[0] - // match: (ROLBconst [c] (ROLBconst [d] x)) - // result: (ROLBconst [(c+d)& 7] x) - for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64ROLBconst { - break - } - d := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpAMD64ROLBconst) - v.AuxInt = int8ToAuxInt((c + d) & 7) - v.AddArg(x) - return true - } // match: (ROLBconst x [0]) // result: x for { @@ -20439,20 +18563,6 @@ } func rewriteValueAMD64_OpAMD64ROLLconst(v *Value) bool { v_0 := v.Args[0] - // match: (ROLLconst [c] (ROLLconst [d] x)) - // result: (ROLLconst [(c+d)&31] x) - for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64ROLLconst { - break - } - d := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpAMD64ROLLconst) - v.AuxInt = int8ToAuxInt((c + d) & 31) - v.AddArg(x) - return true - } // match: (ROLLconst x [0]) // result: x for { @@ -20522,20 +18632,6 @@ } func rewriteValueAMD64_OpAMD64ROLQconst(v *Value) bool { v_0 := v.Args[0] - // match: (ROLQconst [c] (ROLQconst [d] x)) - // result: (ROLQconst [(c+d)&63] x) - for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64ROLQconst { - break - } - d := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpAMD64ROLQconst) - v.AuxInt = int8ToAuxInt((c + d) & 63) - v.AddArg(x) - return true - } // match: (ROLQconst x [0]) // result: x for { @@ -20605,20 +18701,6 @@ } func rewriteValueAMD64_OpAMD64ROLWconst(v *Value) bool { v_0 := v.Args[0] - // match: (ROLWconst [c] (ROLWconst [d] x)) - // result: (ROLWconst [(c+d)&15] x) - for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64ROLWconst { - break - } - d := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpAMD64ROLWconst) - v.AuxInt = int8ToAuxInt((c + d) & 15) - v.AddArg(x) - return true - } // match: (ROLWconst x [0]) // result: x for { @@ -29797,80 +27879,6 @@ } break } - // match: (XORL (SHLLconst x [c]) (SHRLconst x [d])) - // cond: d==32-c - // result: (ROLLconst x [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRLconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 32-c) { - continue - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (XORL (SHLLconst x [c]) (SHRWconst x [d])) - // cond: d==16-c && c < 16 && t.Size() == 2 - // result: (ROLWconst x [c]) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRWconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - continue - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (XORL (SHLLconst x [c]) (SHRBconst x [d])) - // cond: d==8-c && c < 8 && t.Size() == 1 - // result: (ROLBconst x [c]) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRBconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - continue - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } // match: (XORL x x) // result: (MOVLconst [0]) for { @@ -30352,30 +28360,6 @@ } v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(int32(c)) - v.AddArg(x) - return true - } - break - } - // match: (XORQ (SHLQconst x [c]) (SHRQconst x [d])) - // cond: d==64-c - // result: (ROLQconst x [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLQconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRQconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 64-c) { - continue - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } -- diff -- # indent-heuristic: true @@ -1276,80 +1276,6 @@ } break } - // match: (ADDL (SHLLconst x [c]) (SHRLconst x [d])) - // cond: d==32-c - // result: (ROLLconst x [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRLconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 32-c) { - continue - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (ADDL (SHLLconst x [c]) (SHRWconst x [d])) - // cond: d==16-c && c < 16 && t.Size() == 2 - // result: (ROLWconst x [c]) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRWconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - continue - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (ADDL (SHLLconst x [c]) (SHRBconst x [d])) - // cond: d==8-c && c < 8 && t.Size() == 1 - // result: (ROLBconst x [c]) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRBconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - continue - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { @@ -1915,30 +1841,6 @@ } break } - // match: (ADDQ (SHLQconst x [c]) (SHRQconst x [d])) - // cond: d==64-c - // result: (ROLQconst x [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLQconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRQconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 64-c) { - continue - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { @@ -7516,40 +7418,6 @@ func rewriteValueAMD64_OpAMD64CMPQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block - // match: (CMPQconst (NEGQ (ADDQconst [-16] (ANDQconst [15] _))) [32]) - // result: (FlagLT_ULT) - for { - if auxIntToInt32(v.AuxInt) != 32 || v_0.Op != OpAMD64NEGQ { - break - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_0_0.AuxInt) != -16 { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_0_0.AuxInt) != 15 { - break - } - v.reset(OpAMD64FlagLT_ULT) - return true - } - // match: (CMPQconst (NEGQ (ADDQconst [ -8] (ANDQconst [7] _))) [32]) - // result: (FlagLT_ULT) - for { - if auxIntToInt32(v.AuxInt) != 32 || v_0.Op != OpAMD64NEGQ { - break - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_0_0.AuxInt) != -8 { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_0_0.AuxInt) != 7 { - break - } - v.reset(OpAMD64FlagLT_ULT) - return true - } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x==int64(y) // result: (FlagEQ) @@ -16107,1312 +15975,6 @@ } break } - // match: (ORL (SHLLconst x [c]) (SHRLconst x [d])) - // cond: d==32-c - // result: (ROLLconst x [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRLconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 32-c) { - continue - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (ORL (SHLLconst x [c]) (SHRWconst x [d])) - // cond: d==16-c && c < 16 && t.Size() == 2 - // result: (ROLWconst x [c]) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRWconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - continue - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (ORL (SHLLconst x [c]) (SHRBconst x [d])) - // cond: d==8-c && c < 8 && t.Size() == 1 - // result: (ROLBconst x [c]) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRBconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - continue - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) - // result: (ROLL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) - // result: (ROLL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) - // result: (RORL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) - // result: (RORL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLXL x y) (ANDL (SHRXL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) - // result: (ROLL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRXL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLXL x y) (ANDL (SHRXL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) - // result: (ROLL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRXL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRXL x y) (ANDL (SHLXL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) - // result: (RORL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRXL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRXL x y) (ANDL (SHLXL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) - // result: (RORL x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRXL { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXL { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORL) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRW { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64ROLW) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRW { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64ROLW) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRW x (ANDQconst y [15])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) - // cond: v.Type.Size() == 2 - // result: (RORW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRW { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64RORW) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHRW x (ANDLconst y [15])) (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) - // cond: v.Type.Size() == 2 - // result: (RORW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRW { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGL { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64RORW) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHLXL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRW { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64ROLW) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLXL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRW { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64ROLW) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRW x (ANDQconst y [15])) (SHLXL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) - // cond: v.Type.Size() == 2 - // result: (RORW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRW { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLXL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64RORW) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHRW x (ANDLconst y [15])) (SHLXL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) - // cond: v.Type.Size() == 2 - // result: (RORW x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRW { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLXL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGL { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - continue - } - v.reset(OpAMD64RORW) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRB { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64ROLB) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRB { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64ROLB) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) - // cond: v.Type.Size() == 1 - // result: (RORB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRB { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64RORB) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) - // cond: v.Type.Size() == 1 - // result: (RORB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRB { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGL { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64RORB) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHLXL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRB { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64ROLB) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHLXL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXL { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64ANDL { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRB { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL { - continue - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { - continue - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64ROLB) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLXL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) - // cond: v.Type.Size() == 1 - // result: (RORB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRB { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLXL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64RORB) - v.AddArg2(x, y) - return true - } - break - } - // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLXL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) - // cond: v.Type.Size() == 1 - // result: (RORB x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRB { - continue - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { - continue - } - y := v_0_1.Args[0] - if v_1.Op != OpAMD64SHLXL { - continue - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - continue - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGL { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - continue - } - v.reset(OpAMD64RORB) - v.AddArg2(x, y) - return true - } - break - } // match: (ORL x x) // result: x for { @@ -18381,430 +16943,6 @@ } break } - // match: (ORQ (SHLQconst x [c]) (SHRQconst x [d])) - // cond: d==64-c - // result: (ROLQconst x [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLQconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRQconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 64-c) { - continue - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) - // result: (ROLQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) - // result: (ROLQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) - // result: (RORQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) - // result: (RORQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHLXQ x y) (ANDQ (SHRXQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) - // result: (ROLQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRXQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHLXQ x y) (ANDQ (SHRXQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) - // result: (ROLQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLXQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHRXQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64ROLQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHRXQ x y) (ANDQ (SHLXQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) - // result: (RORQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRXQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORQ) - v.AddArg2(x, y) - return true - } - } - break - } - // match: (ORQ (SHRXQ x y) (ANDQ (SHLXQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) - // result: (RORQ x y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHRXQ { - continue - } - y := v_0.Args[1] - x := v_0.Args[0] - if v_1.Op != OpAMD64ANDQ { - continue - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - v_1_1 := v_1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { - if v_1_0.Op != OpAMD64SHLXQ { - continue - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - continue - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { - continue - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { - continue - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - continue - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { - continue - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { - continue - } - v.reset(OpAMD64RORQ) - v.AddArg2(x, y) - return true - } - } - break - } // match: (ORQ (SHRQ lo bits) (SHLQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { @@ -20356,20 +18494,6 @@ } func rewriteValueAMD64_OpAMD64ROLBconst(v *Value) bool { v_0 := v.Args[0] - // match: (ROLBconst [c] (ROLBconst [d] x)) - // result: (ROLBconst [(c+d)& 7] x) - for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64ROLBconst { - break - } - d := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpAMD64ROLBconst) - v.AuxInt = int8ToAuxInt((c + d) & 7) - v.AddArg(x) - return true - } // match: (ROLBconst x [0]) // result: x for { @@ -20439,20 +18563,6 @@ } func rewriteValueAMD64_OpAMD64ROLLconst(v *Value) bool { v_0 := v.Args[0] - // match: (ROLLconst [c] (ROLLconst [d] x)) - // result: (ROLLconst [(c+d)&31] x) - for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64ROLLconst { - break - } - d := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpAMD64ROLLconst) - v.AuxInt = int8ToAuxInt((c + d) & 31) - v.AddArg(x) - return true - } // match: (ROLLconst x [0]) // result: x for { @@ -20522,20 +18632,6 @@ } func rewriteValueAMD64_OpAMD64ROLQconst(v *Value) bool { v_0 := v.Args[0] - // match: (ROLQconst [c] (ROLQconst [d] x)) - // result: (ROLQconst [(c+d)&63] x) - for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64ROLQconst { - break - } - d := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpAMD64ROLQconst) - v.AuxInt = int8ToAuxInt((c + d) & 63) - v.AddArg(x) - return true - } // match: (ROLQconst x [0]) // result: x for { @@ -20605,20 +18701,6 @@ } func rewriteValueAMD64_OpAMD64ROLWconst(v *Value) bool { v_0 := v.Args[0] - // match: (ROLWconst [c] (ROLWconst [d] x)) - // result: (ROLWconst [(c+d)&15] x) - for { - c := auxIntToInt8(v.AuxInt) - if v_0.Op != OpAMD64ROLWconst { - break - } - d := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - v.reset(OpAMD64ROLWconst) - v.AuxInt = int8ToAuxInt((c + d) & 15) - v.AddArg(x) - return true - } // match: (ROLWconst x [0]) // result: x for { @@ -29797,80 +27879,6 @@ } break } - // match: (XORL (SHLLconst x [c]) (SHRLconst x [d])) - // cond: d==32-c - // result: (ROLLconst x [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRLconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 32-c) { - continue - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (XORL (SHLLconst x [c]) (SHRWconst x [d])) - // cond: d==16-c && c < 16 && t.Size() == 2 - // result: (ROLWconst x [c]) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRWconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - continue - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } - // match: (XORL (SHLLconst x [c]) (SHRBconst x [d])) - // cond: d==8-c && c < 8 && t.Size() == 1 - // result: (ROLBconst x [c]) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLLconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRBconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - continue - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } // match: (XORL x x) // result: (MOVLconst [0]) for { @@ -30357,30 +28365,6 @@ } break } - // match: (XORQ (SHLQconst x [c]) (SHRQconst x [d])) - // cond: d==64-c - // result: (ROLQconst x [c]) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - if v_0.Op != OpAMD64SHLQconst { - continue - } - c := auxIntToInt8(v_0.AuxInt) - x := v_0.Args[0] - if v_1.Op != OpAMD64SHRQconst { - continue - } - d := auxIntToInt8(v_1.AuxInt) - if x != v_1.Args[0] || !(d == 64-c) { - continue - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = int8ToAuxInt(c) - v.AddArg(x) - return true - } - break - } // match: (XORQ x x) // result: (MOVQconst [0]) for { go_60ad3c48f59c35981dd872ed5dfe74e4d6becab2_src_cmd_compile_internal_ssa_rewritegeneric.go.test000066400000000000000000063231361516001707200370210ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit 60ad3c48f59c35981dd872ed5dfe74e4d6becab2 file src/cmd/compile/internal/ssa/rewritegeneric.go -- x -- // Code generated from gen/generic.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/compile/internal/types" func rewriteValuegeneric(v *Value) bool { switch v.Op { case OpAdd16: return rewriteValuegeneric_OpAdd16(v) case OpAdd32: return rewriteValuegeneric_OpAdd32(v) case OpAdd32F: return rewriteValuegeneric_OpAdd32F(v) case OpAdd64: return rewriteValuegeneric_OpAdd64(v) case OpAdd64F: return rewriteValuegeneric_OpAdd64F(v) case OpAdd8: return rewriteValuegeneric_OpAdd8(v) case OpAddPtr: return rewriteValuegeneric_OpAddPtr(v) case OpAnd16: return rewriteValuegeneric_OpAnd16(v) case OpAnd32: return rewriteValuegeneric_OpAnd32(v) case OpAnd64: return rewriteValuegeneric_OpAnd64(v) case OpAnd8: return rewriteValuegeneric_OpAnd8(v) case OpAndB: return rewriteValuegeneric_OpAndB(v) case OpArraySelect: return rewriteValuegeneric_OpArraySelect(v) case OpCom16: return rewriteValuegeneric_OpCom16(v) case OpCom32: return rewriteValuegeneric_OpCom32(v) case OpCom64: return rewriteValuegeneric_OpCom64(v) case OpCom8: return rewriteValuegeneric_OpCom8(v) case OpConstInterface: return rewriteValuegeneric_OpConstInterface(v) case OpConstSlice: return rewriteValuegeneric_OpConstSlice(v) case OpConstString: return rewriteValuegeneric_OpConstString(v) case OpConvert: return rewriteValuegeneric_OpConvert(v) case OpCtz16: return rewriteValuegeneric_OpCtz16(v) case OpCtz32: return rewriteValuegeneric_OpCtz32(v) case OpCtz64: return rewriteValuegeneric_OpCtz64(v) case OpCtz8: return rewriteValuegeneric_OpCtz8(v) case OpCvt32Fto32: return rewriteValuegeneric_OpCvt32Fto32(v) case OpCvt32Fto64: return rewriteValuegeneric_OpCvt32Fto64(v) case OpCvt32Fto64F: return rewriteValuegeneric_OpCvt32Fto64F(v) case OpCvt32to32F: return rewriteValuegeneric_OpCvt32to32F(v) case OpCvt32to64F: return rewriteValuegeneric_OpCvt32to64F(v) case OpCvt64Fto32: return rewriteValuegeneric_OpCvt64Fto32(v) case OpCvt64Fto32F: return rewriteValuegeneric_OpCvt64Fto32F(v) case OpCvt64Fto64: return rewriteValuegeneric_OpCvt64Fto64(v) case OpCvt64to32F: return rewriteValuegeneric_OpCvt64to32F(v) case OpCvt64to64F: return rewriteValuegeneric_OpCvt64to64F(v) case OpCvtBoolToUint8: return rewriteValuegeneric_OpCvtBoolToUint8(v) case OpDiv16: return rewriteValuegeneric_OpDiv16(v) case OpDiv16u: return rewriteValuegeneric_OpDiv16u(v) case OpDiv32: return rewriteValuegeneric_OpDiv32(v) case OpDiv32F: return rewriteValuegeneric_OpDiv32F(v) case OpDiv32u: return rewriteValuegeneric_OpDiv32u(v) case OpDiv64: return rewriteValuegeneric_OpDiv64(v) case OpDiv64F: return rewriteValuegeneric_OpDiv64F(v) case OpDiv64u: return rewriteValuegeneric_OpDiv64u(v) case OpDiv8: return rewriteValuegeneric_OpDiv8(v) case OpDiv8u: return rewriteValuegeneric_OpDiv8u(v) case OpEq16: return rewriteValuegeneric_OpEq16(v) case OpEq32: return rewriteValuegeneric_OpEq32(v) case OpEq32F: return rewriteValuegeneric_OpEq32F(v) case OpEq64: return rewriteValuegeneric_OpEq64(v) case OpEq64F: return rewriteValuegeneric_OpEq64F(v) case OpEq8: return rewriteValuegeneric_OpEq8(v) case OpEqB: return rewriteValuegeneric_OpEqB(v) case OpEqInter: return rewriteValuegeneric_OpEqInter(v) case OpEqPtr: return rewriteValuegeneric_OpEqPtr(v) case OpEqSlice: return rewriteValuegeneric_OpEqSlice(v) case OpIMake: return rewriteValuegeneric_OpIMake(v) case OpInterLECall: return rewriteValuegeneric_OpInterLECall(v) case OpIsInBounds: return rewriteValuegeneric_OpIsInBounds(v) case OpIsNonNil: return rewriteValuegeneric_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValuegeneric_OpIsSliceInBounds(v) case OpLeq16: return rewriteValuegeneric_OpLeq16(v) case OpLeq16U: return rewriteValuegeneric_OpLeq16U(v) case OpLeq32: return rewriteValuegeneric_OpLeq32(v) case OpLeq32F: return rewriteValuegeneric_OpLeq32F(v) case OpLeq32U: return rewriteValuegeneric_OpLeq32U(v) case OpLeq64: return rewriteValuegeneric_OpLeq64(v) case OpLeq64F: return rewriteValuegeneric_OpLeq64F(v) case OpLeq64U: return rewriteValuegeneric_OpLeq64U(v) case OpLeq8: return rewriteValuegeneric_OpLeq8(v) case OpLeq8U: return rewriteValuegeneric_OpLeq8U(v) case OpLess16: return rewriteValuegeneric_OpLess16(v) case OpLess16U: return rewriteValuegeneric_OpLess16U(v) case OpLess32: return rewriteValuegeneric_OpLess32(v) case OpLess32F: return rewriteValuegeneric_OpLess32F(v) case OpLess32U: return rewriteValuegeneric_OpLess32U(v) case OpLess64: return rewriteValuegeneric_OpLess64(v) case OpLess64F: return rewriteValuegeneric_OpLess64F(v) case OpLess64U: return rewriteValuegeneric_OpLess64U(v) case OpLess8: return rewriteValuegeneric_OpLess8(v) case OpLess8U: return rewriteValuegeneric_OpLess8U(v) case OpLoad: return rewriteValuegeneric_OpLoad(v) case OpLsh16x16: return rewriteValuegeneric_OpLsh16x16(v) case OpLsh16x32: return rewriteValuegeneric_OpLsh16x32(v) case OpLsh16x64: return rewriteValuegeneric_OpLsh16x64(v) case OpLsh16x8: return rewriteValuegeneric_OpLsh16x8(v) case OpLsh32x16: return rewriteValuegeneric_OpLsh32x16(v) case OpLsh32x32: return rewriteValuegeneric_OpLsh32x32(v) case OpLsh32x64: return rewriteValuegeneric_OpLsh32x64(v) case OpLsh32x8: return rewriteValuegeneric_OpLsh32x8(v) case OpLsh64x16: return rewriteValuegeneric_OpLsh64x16(v) case OpLsh64x32: return rewriteValuegeneric_OpLsh64x32(v) case OpLsh64x64: return rewriteValuegeneric_OpLsh64x64(v) case OpLsh64x8: return rewriteValuegeneric_OpLsh64x8(v) case OpLsh8x16: return rewriteValuegeneric_OpLsh8x16(v) case OpLsh8x32: return rewriteValuegeneric_OpLsh8x32(v) case OpLsh8x64: return rewriteValuegeneric_OpLsh8x64(v) case OpLsh8x8: return rewriteValuegeneric_OpLsh8x8(v) case OpMod16: return rewriteValuegeneric_OpMod16(v) case OpMod16u: return rewriteValuegeneric_OpMod16u(v) case OpMod32: return rewriteValuegeneric_OpMod32(v) case OpMod32u: return rewriteValuegeneric_OpMod32u(v) case OpMod64: return rewriteValuegeneric_OpMod64(v) case OpMod64u: return rewriteValuegeneric_OpMod64u(v) case OpMod8: return rewriteValuegeneric_OpMod8(v) case OpMod8u: return rewriteValuegeneric_OpMod8u(v) case OpMove: return rewriteValuegeneric_OpMove(v) case OpMul16: return rewriteValuegeneric_OpMul16(v) case OpMul32: return rewriteValuegeneric_OpMul32(v) case OpMul32F: return rewriteValuegeneric_OpMul32F(v) case OpMul64: return rewriteValuegeneric_OpMul64(v) case OpMul64F: return rewriteValuegeneric_OpMul64F(v) case OpMul8: return rewriteValuegeneric_OpMul8(v) case OpNeg16: return rewriteValuegeneric_OpNeg16(v) case OpNeg32: return rewriteValuegeneric_OpNeg32(v) case OpNeg32F: return rewriteValuegeneric_OpNeg32F(v) case OpNeg64: return rewriteValuegeneric_OpNeg64(v) case OpNeg64F: return rewriteValuegeneric_OpNeg64F(v) case OpNeg8: return rewriteValuegeneric_OpNeg8(v) case OpNeq16: return rewriteValuegeneric_OpNeq16(v) case OpNeq32: return rewriteValuegeneric_OpNeq32(v) case OpNeq32F: return rewriteValuegeneric_OpNeq32F(v) case OpNeq64: return rewriteValuegeneric_OpNeq64(v) case OpNeq64F: return rewriteValuegeneric_OpNeq64F(v) case OpNeq8: return rewriteValuegeneric_OpNeq8(v) case OpNeqB: return rewriteValuegeneric_OpNeqB(v) case OpNeqInter: return rewriteValuegeneric_OpNeqInter(v) case OpNeqPtr: return rewriteValuegeneric_OpNeqPtr(v) case OpNeqSlice: return rewriteValuegeneric_OpNeqSlice(v) case OpNilCheck: return rewriteValuegeneric_OpNilCheck(v) case OpNot: return rewriteValuegeneric_OpNot(v) case OpOffPtr: return rewriteValuegeneric_OpOffPtr(v) case OpOr16: return rewriteValuegeneric_OpOr16(v) case OpOr32: return rewriteValuegeneric_OpOr32(v) case OpOr64: return rewriteValuegeneric_OpOr64(v) case OpOr8: return rewriteValuegeneric_OpOr8(v) case OpOrB: return rewriteValuegeneric_OpOrB(v) case OpPhi: return rewriteValuegeneric_OpPhi(v) case OpPtrIndex: return rewriteValuegeneric_OpPtrIndex(v) case OpRotateLeft16: return rewriteValuegeneric_OpRotateLeft16(v) case OpRotateLeft32: return rewriteValuegeneric_OpRotateLeft32(v) case OpRotateLeft64: return rewriteValuegeneric_OpRotateLeft64(v) case OpRotateLeft8: return rewriteValuegeneric_OpRotateLeft8(v) case OpRound32F: return rewriteValuegeneric_OpRound32F(v) case OpRound64F: return rewriteValuegeneric_OpRound64F(v) case OpRsh16Ux16: return rewriteValuegeneric_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValuegeneric_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValuegeneric_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValuegeneric_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValuegeneric_OpRsh16x16(v) case OpRsh16x32: return rewriteValuegeneric_OpRsh16x32(v) case OpRsh16x64: return rewriteValuegeneric_OpRsh16x64(v) case OpRsh16x8: return rewriteValuegeneric_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValuegeneric_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValuegeneric_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValuegeneric_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValuegeneric_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValuegeneric_OpRsh32x16(v) case OpRsh32x32: return rewriteValuegeneric_OpRsh32x32(v) case OpRsh32x64: return rewriteValuegeneric_OpRsh32x64(v) case OpRsh32x8: return rewriteValuegeneric_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValuegeneric_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValuegeneric_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValuegeneric_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValuegeneric_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValuegeneric_OpRsh64x16(v) case OpRsh64x32: return rewriteValuegeneric_OpRsh64x32(v) case OpRsh64x64: return rewriteValuegeneric_OpRsh64x64(v) case OpRsh64x8: return rewriteValuegeneric_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValuegeneric_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValuegeneric_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValuegeneric_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValuegeneric_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValuegeneric_OpRsh8x16(v) case OpRsh8x32: return rewriteValuegeneric_OpRsh8x32(v) case OpRsh8x64: return rewriteValuegeneric_OpRsh8x64(v) case OpRsh8x8: return rewriteValuegeneric_OpRsh8x8(v) case OpSelect0: return rewriteValuegeneric_OpSelect0(v) case OpSelect1: return rewriteValuegeneric_OpSelect1(v) case OpSelectN: return rewriteValuegeneric_OpSelectN(v) case OpSignExt16to32: return rewriteValuegeneric_OpSignExt16to32(v) case OpSignExt16to64: return rewriteValuegeneric_OpSignExt16to64(v) case OpSignExt32to64: return rewriteValuegeneric_OpSignExt32to64(v) case OpSignExt8to16: return rewriteValuegeneric_OpSignExt8to16(v) case OpSignExt8to32: return rewriteValuegeneric_OpSignExt8to32(v) case OpSignExt8to64: return rewriteValuegeneric_OpSignExt8to64(v) case OpSliceCap: return rewriteValuegeneric_OpSliceCap(v) case OpSliceLen: return rewriteValuegeneric_OpSliceLen(v) case OpSlicePtr: return rewriteValuegeneric_OpSlicePtr(v) case OpSlicemask: return rewriteValuegeneric_OpSlicemask(v) case OpSqrt: return rewriteValuegeneric_OpSqrt(v) case OpStaticLECall: return rewriteValuegeneric_OpStaticLECall(v) case OpStore: return rewriteValuegeneric_OpStore(v) case OpStringLen: return rewriteValuegeneric_OpStringLen(v) case OpStringPtr: return rewriteValuegeneric_OpStringPtr(v) case OpStructSelect: return rewriteValuegeneric_OpStructSelect(v) case OpSub16: return rewriteValuegeneric_OpSub16(v) case OpSub32: return rewriteValuegeneric_OpSub32(v) case OpSub32F: return rewriteValuegeneric_OpSub32F(v) case OpSub64: return rewriteValuegeneric_OpSub64(v) case OpSub64F: return rewriteValuegeneric_OpSub64F(v) case OpSub8: return rewriteValuegeneric_OpSub8(v) case OpTrunc16to8: return rewriteValuegeneric_OpTrunc16to8(v) case OpTrunc32to16: return rewriteValuegeneric_OpTrunc32to16(v) case OpTrunc32to8: return rewriteValuegeneric_OpTrunc32to8(v) case OpTrunc64to16: return rewriteValuegeneric_OpTrunc64to16(v) case OpTrunc64to32: return rewriteValuegeneric_OpTrunc64to32(v) case OpTrunc64to8: return rewriteValuegeneric_OpTrunc64to8(v) case OpXor16: return rewriteValuegeneric_OpXor16(v) case OpXor32: return rewriteValuegeneric_OpXor32(v) case OpXor64: return rewriteValuegeneric_OpXor64(v) case OpXor8: return rewriteValuegeneric_OpXor8(v) case OpZero: return rewriteValuegeneric_OpZero(v) case OpZeroExt16to32: return rewriteValuegeneric_OpZeroExt16to32(v) case OpZeroExt16to64: return rewriteValuegeneric_OpZeroExt16to64(v) case OpZeroExt32to64: return rewriteValuegeneric_OpZeroExt32to64(v) case OpZeroExt8to16: return rewriteValuegeneric_OpZeroExt8to16(v) case OpZeroExt8to32: return rewriteValuegeneric_OpZeroExt8to32(v) case OpZeroExt8to64: return rewriteValuegeneric_OpZeroExt8to64(v) } return false } func rewriteValuegeneric_OpAdd16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Add16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c + d) return true } break } // match: (Add16 (Mul16 x y) (Mul16 x z)) // result: (Mul16 x (Add16 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add16 (Const16 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add16 x (Neg16 y)) // result: (Sub16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg16 { continue } y := v_1.Args[0] v.reset(OpSub16) v.AddArg2(x, y) return true } break } // match: (Add16 (Com16 x) x) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Add16 (Const16 [1]) (Com16 x)) // result: (Neg16 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 1 || v_1.Op != OpCom16 { continue } x := v_1.Args[0] v.reset(OpNeg16) v.AddArg(x) return true } break } // match: (Add16 x (Sub16 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub16 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add16 x (Add16 y (Sub16 z x))) // result: (Add16 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub16 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd16) v.AddArg2(y, z) return true } } break } // match: (Add16 (Add16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Add16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add16 (Sub16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub16 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { continue } t := i.Type x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Add16 (Const16 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add16 (Const16 [c]) (Sub16 (Const16 [d]) x)) // result: (Sub16 (Const16 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpSub16 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpAdd32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Add32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c + d) return true } break } // match: (Add32 (Mul32 x y) (Mul32 x z)) // result: (Mul32 x (Add32 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add32 (Const32 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add32 x (Neg32 y)) // result: (Sub32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg32 { continue } y := v_1.Args[0] v.reset(OpSub32) v.AddArg2(x, y) return true } break } // match: (Add32 (Com32 x) x) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Add32 (Const32 [1]) (Com32 x)) // result: (Neg32 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 1 || v_1.Op != OpCom32 { continue } x := v_1.Args[0] v.reset(OpNeg32) v.AddArg(x) return true } break } // match: (Add32 x (Sub32 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub32 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add32 x (Add32 y (Sub32 z x))) // result: (Add32 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd32) v.AddArg2(y, z) return true } } break } // match: (Add32 (Add32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Add32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add32 (Sub32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub32 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { continue } t := i.Type x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Add32 (Const32 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add32 (Const32 [c]) (Sub32 (Const32 [d]) x)) // result: (Sub32 (Const32 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpSub32 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpAdd32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Add32F (Const32F [c]) (Const32F [d])) // cond: c+d == c+d // result: (Const32F [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) if !(c+d == c+d) { continue } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c + d) return true } break } return false } func rewriteValuegeneric_OpAdd64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Add64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c + d) return true } break } // match: (Add64 (Mul64 x y) (Mul64 x z)) // result: (Mul64 x (Add64 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add64 (Const64 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add64 x (Neg64 y)) // result: (Sub64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg64 { continue } y := v_1.Args[0] v.reset(OpSub64) v.AddArg2(x, y) return true } break } // match: (Add64 (Com64 x) x) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Add64 (Const64 [1]) (Com64 x)) // result: (Neg64 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 1 || v_1.Op != OpCom64 { continue } x := v_1.Args[0] v.reset(OpNeg64) v.AddArg(x) return true } break } // match: (Add64 x (Sub64 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub64 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add64 x (Add64 y (Sub64 z x))) // result: (Add64 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub64 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd64) v.AddArg2(y, z) return true } } break } // match: (Add64 (Add64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Add64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add64 (Sub64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub64 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { continue } t := i.Type x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Add64 (Const64 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add64 (Const64 [c]) (Sub64 (Const64 [d]) x)) // result: (Sub64 (Const64 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpSub64 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpAdd64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Add64F (Const64F [c]) (Const64F [d])) // cond: c+d == c+d // result: (Const64F [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) if !(c+d == c+d) { continue } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c + d) return true } break } return false } func rewriteValuegeneric_OpAdd8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Add8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c + d) return true } break } // match: (Add8 (Mul8 x y) (Mul8 x z)) // result: (Mul8 x (Add8 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add8 (Const8 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add8 x (Neg8 y)) // result: (Sub8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg8 { continue } y := v_1.Args[0] v.reset(OpSub8) v.AddArg2(x, y) return true } break } // match: (Add8 (Com8 x) x) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Add8 (Const8 [1]) (Com8 x)) // result: (Neg8 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 1 || v_1.Op != OpCom8 { continue } x := v_1.Args[0] v.reset(OpNeg8) v.AddArg(x) return true } break } // match: (Add8 x (Sub8 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub8 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add8 x (Add8 y (Sub8 z x))) // result: (Add8 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub8 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd8) v.AddArg2(y, z) return true } } break } // match: (Add8 (Add8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Add8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add8 (Sub8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub8 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { continue } t := i.Type x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Add8 (Const8 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add8 (Const8 [c]) (Sub8 (Const8 [d]) x)) // result: (Sub8 (Const8 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpSub8 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpAddPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (AddPtr x (Const64 [c])) // result: (OffPtr x [c]) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpOffPtr) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (AddPtr x (Const32 [c])) // result: (OffPtr x [int64(c)]) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpOffPtr) v.Type = t v.AuxInt = int64ToAuxInt(int64(c)) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c & d) return true } break } // match: (And16 (Const16 [m]) (Rsh16Ux64 _ (Const64 [c]))) // cond: c >= int64(16-ntz16(m)) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } m := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpRsh16Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(16-ntz16(m))) { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 (Const16 [m]) (Lsh16x64 _ (Const64 [c]))) // cond: c >= int64(16-nlz16(m)) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } m := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpLsh16x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(16-nlz16(m))) { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And16 (Const16 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And16 (Const16 [0]) _) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 (Com16 x) x) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 x (And16 x y)) // result: (And16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd16) v.AddArg2(x, y) return true } } break } // match: (And16 (And16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (And16 i (And16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And16 (Const16 [c]) (And16 (Const16 [d]) x)) // result: (And16 (Const16 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAnd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAnd32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c & d) return true } break } // match: (And32 (Const32 [m]) (Rsh32Ux64 _ (Const64 [c]))) // cond: c >= int64(32-ntz32(m)) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } m := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpRsh32Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(32-ntz32(m))) { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 (Const32 [m]) (Lsh32x64 _ (Const64 [c]))) // cond: c >= int64(32-nlz32(m)) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } m := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpLsh32x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(32-nlz32(m))) { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And32 (Const32 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And32 (Const32 [0]) _) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 (Com32 x) x) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 x (And32 x y)) // result: (And32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd32) v.AddArg2(x, y) return true } } break } // match: (And32 (And32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (And32 i (And32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And32 (Const32 [c]) (And32 (Const32 [d]) x)) // result: (And32 (Const32 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAnd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAnd64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c & d) return true } break } // match: (And64 (Const64 [m]) (Rsh64Ux64 _ (Const64 [c]))) // cond: c >= int64(64-ntz64(m)) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } m := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpRsh64Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(64-ntz64(m))) { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 (Const64 [m]) (Lsh64x64 _ (Const64 [c]))) // cond: c >= int64(64-nlz64(m)) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } m := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpLsh64x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(64-nlz64(m))) { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And64 (Const64 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And64 (Const64 [0]) _) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 (Com64 x) x) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 x (And64 x y)) // result: (And64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd64) v.AddArg2(x, y) return true } } break } // match: (And64 (And64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (And64 i (And64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And64 (Const64 [c]) (And64 (Const64 [d]) x)) // result: (And64 (Const64 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAnd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAnd8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c & d) return true } break } // match: (And8 (Const8 [m]) (Rsh8Ux64 _ (Const64 [c]))) // cond: c >= int64(8-ntz8(m)) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } m := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpRsh8Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(8-ntz8(m))) { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 (Const8 [m]) (Lsh8x64 _ (Const64 [c]))) // cond: c >= int64(8-nlz8(m)) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } m := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpLsh8x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(8-nlz8(m))) { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And8 (Const8 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And8 (Const8 [0]) _) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 (Com8 x) x) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 x (And8 x y)) // result: (And8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd8) v.AddArg2(x, y) return true } } break } // match: (And8 (And8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (And8 i (And8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And8 (Const8 [c]) (And8 (Const8 [d]) x)) // result: (And8 (Const8 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAnd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAndB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (AndB (Leq64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: d >= c // result: (Less64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: d >= c // result: (Leq64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: d >= c // result: (Less32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: d >= c // result: (Leq32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: d >= c // result: (Less16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: d >= c // result: (Leq16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: d >= c // result: (Less8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: d >= c // result: (Leq8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c) // result: (Less64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c) // result: (Leq64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c) // result: (Less32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c) // result: (Leq32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c) // result: (Less16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c) // result: (Leq16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c) // result: (Less8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c) // result: (Leq8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c) // result: (Less64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c) // result: (Leq64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c) // result: (Less32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c) // result: (Leq32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c) // result: (Less16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c) // result: (Leq16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c) // result: (Less8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c) // result: (Leq8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } return false } func rewriteValuegeneric_OpArraySelect(v *Value) bool { v_0 := v.Args[0] // match: (ArraySelect (ArrayMake1 x)) // result: x for { if v_0.Op != OpArrayMake1 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (ArraySelect [0] (IData x)) // result: (IData x) for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpIData { break } x := v_0.Args[0] v.reset(OpIData) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpCom16(v *Value) bool { v_0 := v.Args[0] // match: (Com16 (Com16 x)) // result: x for { if v_0.Op != OpCom16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com16 (Const16 [c])) // result: (Const16 [^c]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(^c) return true } // match: (Com16 (Add16 (Const16 [-1]) x)) // result: (Neg16 x) for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst16 || auxIntToInt16(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg16) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpCom32(v *Value) bool { v_0 := v.Args[0] // match: (Com32 (Com32 x)) // result: x for { if v_0.Op != OpCom32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com32 (Const32 [c])) // result: (Const32 [^c]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(^c) return true } // match: (Com32 (Add32 (Const32 [-1]) x)) // result: (Neg32 x) for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg32) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpCom64(v *Value) bool { v_0 := v.Args[0] // match: (Com64 (Com64 x)) // result: x for { if v_0.Op != OpCom64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com64 (Const64 [c])) // result: (Const64 [^c]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(^c) return true } // match: (Com64 (Add64 (Const64 [-1]) x)) // result: (Neg64 x) for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg64) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpCom8(v *Value) bool { v_0 := v.Args[0] // match: (Com8 (Com8 x)) // result: x for { if v_0.Op != OpCom8 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com8 (Const8 [c])) // result: (Const8 [^c]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(^c) return true } // match: (Com8 (Add8 (Const8 [-1]) x)) // result: (Neg8 x) for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst8 || auxIntToInt8(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpConstInterface(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ConstInterface) // result: (IMake (ConstNil ) (ConstNil )) for { v.reset(OpIMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.Uintptr) v1 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpConstSlice(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (ConstSlice) // cond: config.PtrSize == 4 // result: (SliceMake (ConstNil ) (Const32 [0]) (Const32 [0])) for { if !(config.PtrSize == 4) { break } v.reset(OpSliceMake) v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = int32ToAuxInt(0) v.AddArg3(v0, v1, v1) return true } // match: (ConstSlice) // cond: config.PtrSize == 8 // result: (SliceMake (ConstNil ) (Const64 [0]) (Const64 [0])) for { if !(config.PtrSize == 8) { break } v.reset(OpSliceMake) v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = int64ToAuxInt(0) v.AddArg3(v0, v1, v1) return true } return false } func rewriteValuegeneric_OpConstString(v *Value) bool { b := v.Block config := b.Func.Config fe := b.Func.fe typ := &b.Func.Config.Types // match: (ConstString {str}) // cond: config.PtrSize == 4 && str == "" // result: (StringMake (ConstNil) (Const32 [0])) for { str := auxToString(v.Aux) if !(config.PtrSize == 4 && str == "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v1) return true } // match: (ConstString {str}) // cond: config.PtrSize == 8 && str == "" // result: (StringMake (ConstNil) (Const64 [0])) for { str := auxToString(v.Aux) if !(config.PtrSize == 8 && str == "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, v1) return true } // match: (ConstString {str}) // cond: config.PtrSize == 4 && str != "" // result: (StringMake (Addr {fe.StringData(str)} (SB)) (Const32 [int32(len(str))])) for { str := auxToString(v.Aux) if !(config.PtrSize == 4 && str != "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) v0.Aux = symToAux(fe.StringData(str)) v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int) v2.AuxInt = int32ToAuxInt(int32(len(str))) v.AddArg2(v0, v2) return true } // match: (ConstString {str}) // cond: config.PtrSize == 8 && str != "" // result: (StringMake (Addr {fe.StringData(str)} (SB)) (Const64 [int64(len(str))])) for { str := auxToString(v.Aux) if !(config.PtrSize == 8 && str != "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) v0.Aux = symToAux(fe.StringData(str)) v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.Int) v2.AuxInt = int64ToAuxInt(int64(len(str))) v.AddArg2(v0, v2) return true } return false } func rewriteValuegeneric_OpConvert(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Convert (Add64 (Convert ptr mem) off) mem) // result: (AddPtr ptr off) for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConvert { continue } mem := v_0_0.Args[1] ptr := v_0_0.Args[0] off := v_0_1 if mem != v_1 { continue } v.reset(OpAddPtr) v.AddArg2(ptr, off) return true } break } // match: (Convert (Add32 (Convert ptr mem) off) mem) // result: (AddPtr ptr off) for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConvert { continue } mem := v_0_0.Args[1] ptr := v_0_0.Args[0] off := v_0_1 if mem != v_1 { continue } v.reset(OpAddPtr) v.AddArg2(ptr, off) return true } break } // match: (Convert (Convert ptr mem) mem) // result: ptr for { if v_0.Op != OpConvert { break } mem := v_0.Args[1] ptr := v_0.Args[0] if mem != v_1 { break } v.copyOf(ptr) return true } return false } func rewriteValuegeneric_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz16 (Const16 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz16(c))) return true } // match: (Ctz16 (Const16 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz16(c))) return true } return false } func rewriteValuegeneric_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz32 (Const32 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz32(c))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz32(c))) return true } // match: (Ctz32 (Const32 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz32(c))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz32(c))) return true } return false } func rewriteValuegeneric_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz64 (Const64 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz64(c))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz64(c))) return true } // match: (Ctz64 (Const64 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz64(c))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } return false } func rewriteValuegeneric_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz8 (Const8 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz8(c))) return true } // match: (Ctz8 (Const8 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz8(c))) return true } return false } func rewriteValuegeneric_OpCvt32Fto32(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32Fto32 (Const32F [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } return false } func rewriteValuegeneric_OpCvt32Fto64(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32Fto64 (Const32F [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } return false } func rewriteValuegeneric_OpCvt32Fto64F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32Fto64F (Const32F [c])) // result: (Const64F [float64(c)]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(float64(c)) return true } return false } func rewriteValuegeneric_OpCvt32to32F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32to32F (Const32 [c])) // result: (Const32F [float32(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(float32(c)) return true } return false } func rewriteValuegeneric_OpCvt32to64F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32to64F (Const32 [c])) // result: (Const64F [float64(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(float64(c)) return true } return false } func rewriteValuegeneric_OpCvt64Fto32(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64Fto32 (Const64F [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } return false } func rewriteValuegeneric_OpCvt64Fto32F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64Fto32F (Const64F [c])) // result: (Const32F [float32(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(float32(c)) return true } // match: (Cvt64Fto32F sqrt0:(Sqrt (Cvt32Fto64F x))) // cond: sqrt0.Uses==1 // result: (Sqrt32 x) for { sqrt0 := v_0 if sqrt0.Op != OpSqrt { break } sqrt0_0 := sqrt0.Args[0] if sqrt0_0.Op != OpCvt32Fto64F { break } x := sqrt0_0.Args[0] if !(sqrt0.Uses == 1) { break } v.reset(OpSqrt32) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpCvt64Fto64(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64Fto64 (Const64F [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } return false } func rewriteValuegeneric_OpCvt64to32F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64to32F (Const64 [c])) // result: (Const32F [float32(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(float32(c)) return true } return false } func rewriteValuegeneric_OpCvt64to64F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64to64F (Const64 [c])) // result: (Const64F [float64(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(float64(c)) return true } return false } func rewriteValuegeneric_OpCvtBoolToUint8(v *Value) bool { v_0 := v.Args[0] // match: (CvtBoolToUint8 (ConstBool [false])) // result: (Const8 [0]) for { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != false { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (CvtBoolToUint8 (ConstBool [true])) // result: (Const8 [1]) for { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != true { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(1) return true } return false } func rewriteValuegeneric_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [c/d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c / d) return true } // match: (Div16 n (Const16 [c])) // cond: isNonNegative(n) && isPowerOfTwo16(c) // result: (Rsh16Ux64 n (Const64 [log16(c)])) for { n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo16(c)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log16(c)) v.AddArg2(n, v0) return true } // match: (Div16 n (Const16 [c])) // cond: c < 0 && c != -1<<15 // result: (Neg16 (Div16 n (Const16 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(c < 0 && c != -1<<15) { break } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpDiv16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div16 x (Const16 [-1<<15])) // result: (Rsh16Ux64 (And16 x (Neg16 x)) (Const64 [15])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != -1<<15 { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpNeg16, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(15) v.AddArg2(v0, v2) return true } // match: (Div16 n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [int64(16-log16(c))]))) (Const64 [int64(log16(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { break } v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpAdd16, t) v1 := b.NewValue0(v.Pos, OpRsh16Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh16x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(15) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(16 - log16(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log16(c))) v.AddArg2(v0, v5) return true } // match: (Div16 x (Const16 [c])) // cond: smagicOK16(c) // result: (Sub16 (Rsh32x64 (Mul32 (Const32 [int32(smagic16(c).m)]) (SignExt16to32 x)) (Const64 [16+smagic16(c).s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(smagicOK16(c)) { break } v.reset(OpSub16) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(smagic16(c).m)) v3 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16 + smagic16(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(31) v5.AddArg2(v3, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div16u (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int16(uint16(c)/uint16(d))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint16(c) / uint16(d))) return true } // match: (Div16u n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (Rsh16Ux64 n (Const64 [log16(c)])) for { n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log16(c)) v.AddArg2(n, v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 8 // result: (Trunc64to16 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<16+umagic16(c).m)]) (ZeroExt16to64 x)) (Const64 [16+umagic16(c).s]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 8) { break } v.reset(OpTrunc64to16) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(1<<16 + umagic16(c).m)) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16 + umagic16(c).s) v0.AddArg2(v1, v4) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 4 && umagic16(c).m&1 == 0 // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<15+umagic16(c).m/2)]) (ZeroExt16to32 x)) (Const64 [16+umagic16(c).s-1]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 4 && umagic16(c).m&1 == 0) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(1<<15 + umagic16(c).m/2)) v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 1) v0.AddArg2(v1, v4) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 4 && c&1 == 0 // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<15+(umagic16(c).m+1)/2)]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [16+umagic16(c).s-2]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 4 && c&1 == 0) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(1<<15 + (umagic16(c).m+1)/2)) v3 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v4.AddArg(x) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(1) v3.AddArg2(v4, v5) v1.AddArg2(v2, v3) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 2) v0.AddArg2(v1, v6) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 4 && config.useAvg // result: (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) (Mul32 (Const32 [int32(umagic16(c).m)]) (ZeroExt16to32 x))) (Const64 [16+umagic16(c).s-1]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 4 && config.useAvg) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) v2 := b.NewValue0(v.Pos, OpLsh32x64, typ.UInt32) v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v3.AddArg(x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16) v2.AddArg2(v3, v4) v5 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(umagic16(c).m)) v5.AddArg2(v6, v3) v1.AddArg2(v2, v5) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 1) v0.AddArg2(v1, v7) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32 (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [c/d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c / d) return true } // match: (Div32 n (Const32 [c])) // cond: isNonNegative(n) && isPowerOfTwo32(c) // result: (Rsh32Ux64 n (Const64 [log32(c)])) for { n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo32(c)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log32(c)) v.AddArg2(n, v0) return true } // match: (Div32 n (Const32 [c])) // cond: c < 0 && c != -1<<31 // result: (Neg32 (Div32 n (Const32 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(c < 0 && c != -1<<31) { break } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpDiv32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div32 x (Const32 [-1<<31])) // result: (Rsh32Ux64 (And32 x (Neg32 x)) (Const64 [31])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != -1<<31 { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpNeg32, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(31) v.AddArg2(v0, v2) return true } // match: (Div32 n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [int64(32-log32(c))]))) (Const64 [int64(log32(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { break } v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpAdd32, t) v1 := b.NewValue0(v.Pos, OpRsh32Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh32x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(31) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(32 - log32(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log32(c))) v.AddArg2(v0, v5) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK32(c) && config.RegSize == 8 // result: (Sub32 (Rsh64x64 (Mul64 (Const64 [int64(smagic32(c).m)]) (SignExt32to64 x)) (Const64 [32+smagic32(c).s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(smagicOK32(c) && config.RegSize == 8) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(smagic32(c).m)) v3 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(32 + smagic32(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh64x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(63) v5.AddArg2(v3, v6) v.AddArg2(v0, v5) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0 && config.useHmul // result: (Sub32 (Rsh32x64 (Hmul32 (Const32 [int32(smagic32(c).m/2)]) x) (Const64 [smagic32(c).s-1])) (Rsh32x64 x (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0 && config.useHmul) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpHmul32, t) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(smagic32(c).m / 2)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(smagic32(c).s - 1) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpRsh32x64, t) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(31) v4.AddArg2(x, v5) v.AddArg2(v0, v4) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0 && config.useHmul // result: (Sub32 (Rsh32x64 (Add32 (Hmul32 (Const32 [int32(smagic32(c).m)]) x) x) (Const64 [smagic32(c).s])) (Rsh32x64 x (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0 && config.useHmul) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpAdd32, t) v2 := b.NewValue0(v.Pos, OpHmul32, t) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(smagic32(c).m)) v2.AddArg2(v3, x) v1.AddArg2(v2, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(smagic32(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(31) v5.AddArg2(x, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Div32F (Const32F [c]) (Const32F [d])) // cond: c/d == c/d // result: (Const32F [c/d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) if !(c/d == c/d) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c / d) return true } // match: (Div32F x (Const32F [c])) // cond: reciprocalExact32(c) // result: (Mul32F x (Const32F [1/c])) for { x := v_0 if v_1.Op != OpConst32F { break } t := v_1.Type c := auxIntToFloat32(v_1.AuxInt) if !(reciprocalExact32(c)) { break } v.reset(OpMul32F) v0 := b.NewValue0(v.Pos, OpConst32F, t) v0.AuxInt = float32ToAuxInt(1 / c) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpDiv32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32u (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int32(uint32(c)/uint32(d))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint32(c) / uint32(d))) return true } // match: (Div32u n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (Rsh32Ux64 n (Const64 [log32(c)])) for { n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log32(c)) v.AddArg2(n, v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 4 && umagic32(c).m&1 == 0 && config.useHmul // result: (Rsh32Ux64 (Hmul32u (Const32 [int32(1<<31+umagic32(c).m/2)]) x) (Const64 [umagic32(c).s-1])) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 4 && umagic32(c).m&1 == 0 && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v1.AuxInt = int32ToAuxInt(int32(1<<31 + umagic32(c).m/2)) v0.AddArg2(v1, x) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(umagic32(c).s - 1) v.AddArg2(v0, v2) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 4 && c&1 == 0 && config.useHmul // result: (Rsh32Ux64 (Hmul32u (Const32 [int32(1<<31+(umagic32(c).m+1)/2)]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [umagic32(c).s-2])) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 4 && c&1 == 0 && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v1.AuxInt = int32ToAuxInt(int32(1<<31 + (umagic32(c).m+1)/2)) v2 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(1) v2.AddArg2(x, v3) v0.AddArg2(v1, v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(umagic32(c).s - 2) v.AddArg2(v0, v4) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 4 && config.useAvg && config.useHmul // result: (Rsh32Ux64 (Avg32u x (Hmul32u (Const32 [int32(umagic32(c).m)]) x)) (Const64 [umagic32(c).s-1])) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 4 && config.useAvg && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(umagic32(c).m)) v1.AddArg2(v2, x) v0.AddArg2(x, v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(umagic32(c).s - 1) v.AddArg2(v0, v3) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 8 && umagic32(c).m&1 == 0 // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+umagic32(c).m/2)]) (ZeroExt32to64 x)) (Const64 [32+umagic32(c).s-1]))) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 8 && umagic32(c).m&1 == 0) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(1<<31 + umagic32(c).m/2)) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 1) v0.AddArg2(v1, v4) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 8 && c&1 == 0 // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+(umagic32(c).m+1)/2)]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [32+umagic32(c).s-2]))) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 8 && c&1 == 0) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(1<<31 + (umagic32(c).m+1)/2)) v3 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(x) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(1) v3.AddArg2(v4, v5) v1.AddArg2(v2, v3) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 2) v0.AddArg2(v1, v6) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 8 && config.useAvg // result: (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) (Mul64 (Const64 [int64(umagic32(c).m)]) (ZeroExt32to64 x))) (Const64 [32+umagic32(c).s-1]))) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 8 && config.useAvg) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(32) v2.AddArg2(v3, v4) v5 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt32) v6.AuxInt = int64ToAuxInt(int64(umagic32(c).m)) v5.AddArg2(v6, v3) v1.AddArg2(v2, v5) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 1) v0.AddArg2(v1, v7) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64 (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [c/d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c / d) return true } // match: (Div64 n (Const64 [c])) // cond: isNonNegative(n) && isPowerOfTwo64(c) // result: (Rsh64Ux64 n (Const64 [log64(c)])) for { n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo64(c)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(n, v0) return true } // match: (Div64 n (Const64 [-1<<63])) // cond: isNonNegative(n) // result: (Const64 [0]) for { n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 || !(isNonNegative(n)) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Div64 n (Const64 [c])) // cond: c < 0 && c != -1<<63 // result: (Neg64 (Div64 n (Const64 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c < 0 && c != -1<<63) { break } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpDiv64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div64 x (Const64 [-1<<63])) // result: (Rsh64Ux64 (And64 x (Neg64 x)) (Const64 [63])) for { t := v.Type x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpNeg64, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(63) v.AddArg2(v0, v2) return true } // match: (Div64 n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [int64(64-log64(c))]))) (Const64 [int64(log64(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v1 := b.NewValue0(v.Pos, OpRsh64Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh64x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(63) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(64 - log64(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log64(c))) v.AddArg2(v0, v5) return true } // match: (Div64 x (Const64 [c])) // cond: smagicOK64(c) && smagic64(c).m&1 == 0 && config.useHmul // result: (Sub64 (Rsh64x64 (Hmul64 (Const64 [int64(smagic64(c).m/2)]) x) (Const64 [smagic64(c).s-1])) (Rsh64x64 x (Const64 [63]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(smagicOK64(c) && smagic64(c).m&1 == 0 && config.useHmul) { break } v.reset(OpSub64) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpHmul64, t) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(smagic64(c).m / 2)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(smagic64(c).s - 1) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpRsh64x64, t) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(63) v4.AddArg2(x, v5) v.AddArg2(v0, v4) return true } // match: (Div64 x (Const64 [c])) // cond: smagicOK64(c) && smagic64(c).m&1 != 0 && config.useHmul // result: (Sub64 (Rsh64x64 (Add64 (Hmul64 (Const64 [int64(smagic64(c).m)]) x) x) (Const64 [smagic64(c).s])) (Rsh64x64 x (Const64 [63]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(smagicOK64(c) && smagic64(c).m&1 != 0 && config.useHmul) { break } v.reset(OpSub64) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpAdd64, t) v2 := b.NewValue0(v.Pos, OpHmul64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(int64(smagic64(c).m)) v2.AddArg2(v3, x) v1.AddArg2(v2, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(smagic64(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh64x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(63) v5.AddArg2(x, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Div64F (Const64F [c]) (Const64F [d])) // cond: c/d == c/d // result: (Const64F [c/d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) if !(c/d == c/d) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c / d) return true } // match: (Div64F x (Const64F [c])) // cond: reciprocalExact64(c) // result: (Mul64F x (Const64F [1/c])) for { x := v_0 if v_1.Op != OpConst64F { break } t := v_1.Type c := auxIntToFloat64(v_1.AuxInt) if !(reciprocalExact64(c)) { break } v.reset(OpMul64F) v0 := b.NewValue0(v.Pos, OpConst64F, t) v0.AuxInt = float64ToAuxInt(1 / c) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpDiv64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64u (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [int64(uint64(c)/uint64(d))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint64(c) / uint64(d))) return true } // match: (Div64u n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (Rsh64Ux64 n (Const64 [log64(c)])) for { n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(n, v0) return true } // match: (Div64u n (Const64 [-1<<63])) // result: (Rsh64Ux64 n (Const64 [63])) for { n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(63) v.AddArg2(n, v0) return true } // match: (Div64u x (Const64 [c])) // cond: c > 0 && c <= 0xFFFF && umagicOK32(int32(c)) && config.RegSize == 4 && config.useHmul // result: (Add64 (Add64 (Add64 (Lsh64x64 (ZeroExt32to64 (Div32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)]))) (Const64 [32])) (ZeroExt32to64 (Div32u (Trunc64to32 x) (Const32 [int32(c)])))) (Mul64 (ZeroExt32to64 (Mod32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)]))) (Const64 [int64((1<<32)/c)]))) (ZeroExt32to64 (Div32u (Add32 (Mod32u (Trunc64to32 x) (Const32 [int32(c)])) (Mul32 (Mod32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)])) (Const32 [int32((1<<32)%c)]))) (Const32 [int32(c)])))) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c > 0 && c <= 0xFFFF && umagicOK32(int32(c)) && config.RegSize == 4 && config.useHmul) { break } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) v5 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v6 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = int64ToAuxInt(32) v6.AddArg2(x, v7) v5.AddArg(v6) v8 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v8.AuxInt = int32ToAuxInt(int32(c)) v4.AddArg2(v5, v8) v3.AddArg(v4) v2.AddArg2(v3, v7) v9 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v10 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) v11 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v11.AddArg(x) v10.AddArg2(v11, v8) v9.AddArg(v10) v1.AddArg2(v2, v9) v12 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v13 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v14 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v14.AddArg2(v5, v8) v13.AddArg(v14) v15 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v15.AuxInt = int64ToAuxInt(int64((1 << 32) / c)) v12.AddArg2(v13, v15) v0.AddArg2(v1, v12) v16 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v17 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) v18 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v19 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v19.AddArg2(v11, v8) v20 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v21 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v21.AuxInt = int32ToAuxInt(int32((1 << 32) % c)) v20.AddArg2(v14, v21) v18.AddArg2(v19, v20) v17.AddArg2(v18, v8) v16.AddArg(v17) v.AddArg2(v0, v16) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK64(c) && config.RegSize == 8 && umagic64(c).m&1 == 0 && config.useHmul // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+umagic64(c).m/2)]) x) (Const64 [umagic64(c).s-1])) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(umagicOK64(c) && config.RegSize == 8 && umagic64(c).m&1 == 0 && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(int64(1<<63 + umagic64(c).m/2)) v0.AddArg2(v1, x) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(umagic64(c).s - 1) v.AddArg2(v0, v2) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK64(c) && config.RegSize == 8 && c&1 == 0 && config.useHmul // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+(umagic64(c).m+1)/2)]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [umagic64(c).s-2])) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(umagicOK64(c) && config.RegSize == 8 && c&1 == 0 && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(int64(1<<63 + (umagic64(c).m+1)/2)) v2 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(1) v2.AddArg2(x, v3) v0.AddArg2(v1, v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(umagic64(c).s - 2) v.AddArg2(v0, v4) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK64(c) && config.RegSize == 8 && config.useAvg && config.useHmul // result: (Rsh64Ux64 (Avg64u x (Hmul64u (Const64 [int64(umagic64(c).m)]) x)) (Const64 [umagic64(c).s-1])) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(umagicOK64(c) && config.RegSize == 8 && config.useAvg && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(umagic64(c).m)) v1.AddArg2(v2, x) v0.AddArg2(x, v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(umagic64(c).s - 1) v.AddArg2(v0, v3) return true } return false } func rewriteValuegeneric_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [c/d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c / d) return true } // match: (Div8 n (Const8 [c])) // cond: isNonNegative(n) && isPowerOfTwo8(c) // result: (Rsh8Ux64 n (Const64 [log8(c)])) for { n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo8(c)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log8(c)) v.AddArg2(n, v0) return true } // match: (Div8 n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Neg8 (Div8 n (Const8 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(c < 0 && c != -1<<7) { break } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpDiv8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div8 x (Const8 [-1<<7 ])) // result: (Rsh8Ux64 (And8 x (Neg8 x)) (Const64 [7 ])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != -1<<7 { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpNeg8, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(7) v.AddArg2(v0, v2) return true } // match: (Div8 n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [int64( 8-log8(c))]))) (Const64 [int64(log8(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { break } v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpAdd8, t) v1 := b.NewValue0(v.Pos, OpRsh8Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh8x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(7) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(8 - log8(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log8(c))) v.AddArg2(v0, v5) return true } // match: (Div8 x (Const8 [c])) // cond: smagicOK8(c) // result: (Sub8 (Rsh32x64 (Mul32 (Const32 [int32(smagic8(c).m)]) (SignExt8to32 x)) (Const64 [8+smagic8(c).s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(smagicOK8(c)) { break } v.reset(OpSub8) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(smagic8(c).m)) v3 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(8 + smagic8(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(31) v5.AddArg2(v3, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int8(uint8(c)/uint8(d))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(uint8(c) / uint8(d))) return true } // match: (Div8u n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (Rsh8Ux64 n (Const64 [log8(c)])) for { n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log8(c)) v.AddArg2(n, v0) return true } // match: (Div8u x (Const8 [c])) // cond: umagicOK8(c) // result: (Trunc32to8 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<8+umagic8(c).m)]) (ZeroExt8to32 x)) (Const64 [8+umagic8(c).s]))) for { x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(umagicOK8(c)) { break } v.reset(OpTrunc32to8) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(1<<8 + umagic8(c).m)) v3 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(8 + umagic8(c).s) v0.AddArg2(v1, v4) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Eq16 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Eq16 (Const16 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq16 (Const16 [c]) (Const16 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq16 (Mod16u x (Const16 [c])) (Const16 [0])) // cond: x.Op != OpConst16 && udivisibleOK16(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt16to32 x) (Const32 [int32(uint16(c))])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod16u { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 || !(x.Op != OpConst16 && udivisibleOK16(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(uint16(c))) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq16 (Mod16 x (Const16 [c])) (Const16 [0])) // cond: x.Op != OpConst16 && sdivisibleOK16(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32 (SignExt16to32 x) (Const32 [int32(c)])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod16 { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 || !(x.Op != OpConst16 && sdivisibleOK16(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic16(c).m) && s == 16+umagic16(c).s && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpZeroExt16to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic16(c).m) && s == 16+umagic16(c).s && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+umagic16(c).m/2) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpZeroExt16to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+umagic16(c).m/2) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+(umagic16(c).m+1)/2) && s == 16+umagic16(c).s-2 && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpRsh32Ux64 { continue } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt16to32 || x != mul_1_0.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+(umagic16(c).m+1)/2) && s == 16+umagic16(c).s-2 && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic16(c).m) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg32u { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh32x64 { continue } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt16to32 || x != v_1_1_0_0_0_0.Args[0] { continue } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 || auxIntToInt64(v_1_1_0_0_0_1.AuxInt) != 16 { continue } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpZeroExt16to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic16(c).m) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic16(c).m) && s == 16+smagic16(c).s && x.Op != OpConst16 && sdivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int16(sdivisible16(c).m)]) x) (Const16 [int16(sdivisible16(c).a)]) ) (Const16 [int16(16-sdivisible16(c).k)]) ) (Const16 [int16(sdivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpSub16 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpSignExt16to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt16to32 || x != v_1_1_1_0.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic16(c).m) && s == 16+smagic16(c).s && x.Op != OpConst16 && sdivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(sdivisible16(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(sdivisible16(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v5.AuxInt = int16ToAuxInt(int16(16 - sdivisible16(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v6.AuxInt = int16ToAuxInt(int16(sdivisible16(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh16x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh16x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd16 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh16Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh16x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 15 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 15 && kbar == 16-k) { continue } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(1< x (Const16 [y])) (Const16 [y])) // cond: oneBit16(y) // result: (Neq16 (And16 x (Const16 [y])) (Const16 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst16 || v_0_1.Type != t { continue } y := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || v_1.Type != t || auxIntToInt16(v_1.AuxInt) != y || !(oneBit16(y)) { continue } v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq32 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Eq32 (Const32 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) x) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+umagic32(c).m/2) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpRsh32Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+umagic32(c).m/2) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+(umagic32(c).m+1)/2) && s == umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpRsh32Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 || mul_0.Type != typ.UInt32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpRsh32Ux64 { continue } _ = mul_1.Args[1] if x != mul_1.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+(umagic32(c).m+1)/2) && s == umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 (Avg32u x mul:(Hmul32u (Const32 [m]) x)) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic32(c).m) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpRsh32Ux64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg32u { continue } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { continue } mul := v_1_1_0.Args[1] if mul.Op != OpHmul32u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic32(c).m) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic32(c).m/2) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to32 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpZeroExt32to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic32(c).m/2) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic32(c).m+1)/2) && s == 32+umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to32 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpRsh64Ux64 { continue } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt32to64 || x != mul_1_0.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic32(c).m+1)/2) && s == 32+umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic32(c).m) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to32 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg64u { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh64x64 { continue } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt32to64 || x != v_1_1_0_0_0_0.Args[0] { continue } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 || auxIntToInt64(v_1_1_0_0_0_1.AuxInt) != 32 { continue } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpZeroExt32to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic32(c).m) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic32(c).m) && s == 32+smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpSignExt32to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { continue } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt32to64 || x != v_1_1_1_0.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic32(c).m) && s == 32+smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m/2) && s == smagic32(c).s-1 && x.Op != OpConst32 && sdivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpHmul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m/2) && s == smagic32(c).s-1 && x.Op != OpConst32 && sdivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m) && s == smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd32 { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] v_1_1_0_0_1 := v_1_1_0_0.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_1_0_0_0, v_1_1_0_0_1 = _i2+1, v_1_1_0_0_1, v_1_1_0_0_0 { mul := v_1_1_0_0_0 if mul.Op != OpHmul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i3 := 0; _i3 <= 1; _i3, mul_0, mul_1 = _i3+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 || x != v_1_1_0_0_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m) && s == smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) v.AddArg2(v0, v6) return true } } } } break } // match: (Eq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh32x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd32 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh32Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh32x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 31 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 31 && kbar == 32-k) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(1< x (Const32 [y])) (Const32 [y])) // cond: oneBit32(y) // result: (Neq32 (And32 x (Const32 [y])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst32 || v_0_1.Type != t { continue } y := auxIntToInt32(v_0_1.AuxInt) if v_1.Op != OpConst32 || v_1.Type != t || auxIntToInt32(v_1.AuxInt) != y || !(oneBit32(y)) { continue } v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Eq32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } return false } func rewriteValuegeneric_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq64 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Eq64 (Const64 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) x) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic64(c).m/2) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpRsh64Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic64(c).m/2) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic64(c).m+1)/2) && s == umagic64(c).s-2 && x.Op != OpConst64 && udivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpRsh64Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpRsh64Ux64 { continue } _ = mul_1.Args[1] if x != mul_1.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic64(c).m+1)/2) && s == umagic64(c).s-2 && x.Op != OpConst64 && udivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 (Avg64u x mul:(Hmul64u (Const64 [m]) x)) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic64(c).m) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpRsh64Ux64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg64u { continue } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { continue } mul := v_1_1_0.Args[1] if mul.Op != OpHmul64u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic64(c).m) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m/2) && s == smagic64(c).s-1 && x.Op != OpConst64 && sdivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible64(c).m)]) x) (Const64 [int64(sdivisible64(c).a)]) ) (Const64 [64-sdivisible64(c).k]) ) (Const64 [int64(sdivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpSub64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpHmul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m/2) && s == smagic64(c).s-1 && x.Op != OpConst64 && sdivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(int64(sdivisible64(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(sdivisible64(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(64 - sdivisible64(c).k) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(int64(sdivisible64(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m) && s == smagic64(c).s && x.Op != OpConst64 && sdivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible64(c).m)]) x) (Const64 [int64(sdivisible64(c).a)]) ) (Const64 [64-sdivisible64(c).k]) ) (Const64 [int64(sdivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpSub64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd64 { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] v_1_1_0_0_1 := v_1_1_0_0.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_1_0_0_0, v_1_1_0_0_1 = _i2+1, v_1_1_0_0_1, v_1_1_0_0_0 { mul := v_1_1_0_0_0 if mul.Op != OpHmul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i3 := 0; _i3 <= 1; _i3, mul_0, mul_1 = _i3+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 || x != v_1_1_0_0_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m) && s == smagic64(c).s && x.Op != OpConst64 && sdivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(int64(sdivisible64(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(sdivisible64(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(64 - sdivisible64(c).k) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(int64(sdivisible64(c).max)) v.AddArg2(v0, v6) return true } } } } break } // match: (Eq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh64x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd64 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh64Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh64x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 63 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 63 && kbar == 64-k) { continue } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(1< x (Const64 [y])) (Const64 [y])) // cond: oneBit64(y) // result: (Neq64 (And64 x (Const64 [y])) (Const64 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst64 || v_0_1.Type != t { continue } y := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 || v_1.Type != t || auxIntToInt64(v_1.AuxInt) != y || !(oneBit64(y)) { continue } v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Eq64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } return false } func rewriteValuegeneric_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Eq8 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Eq8 (Const8 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq8 (Mod8u x (Const8 [c])) (Const8 [0])) // cond: x.Op != OpConst8 && udivisibleOK8(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt8to32 x) (Const32 [int32(uint8(c))])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod8u { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 || !(x.Op != OpConst8 && udivisibleOK8(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(uint8(c))) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq8 (Mod8 x (Const8 [c])) (Const8 [0])) // cond: x.Op != OpConst8 && sdivisibleOK8(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32 (SignExt8to32 x) (Const32 [int32(c)])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod8 { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 || !(x.Op != OpConst8 && sdivisibleOK8(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<8+umagic8(c).m) && s == 8+umagic8(c).s && x.Op != OpConst8 && udivisibleOK8(c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int8(udivisible8(c).m)]) x) (Const8 [int8(8-udivisible8(c).k)]) ) (Const8 [int8(udivisible8(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to8 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpZeroExt8to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<8+umagic8(c).m) && s == 8+umagic8(c).s && x.Op != OpConst8 && udivisibleOK8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int8ToAuxInt(int8(udivisible8(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int8ToAuxInt(int8(8 - udivisible8(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int8ToAuxInt(int8(udivisible8(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq8 x (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic8(c).m) && s == 8+smagic8(c).s && x.Op != OpConst8 && sdivisibleOK8(c) // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int8(sdivisible8(c).m)]) x) (Const8 [int8(sdivisible8(c).a)]) ) (Const8 [int8(8-sdivisible8(c).k)]) ) (Const8 [int8(sdivisible8(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0.AuxInt) if v_1_1.Op != OpSub8 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpSignExt8to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt8to32 || x != v_1_1_1_0.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic8(c).m) && s == 8+smagic8(c).s && x.Op != OpConst8 && sdivisibleOK8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int8ToAuxInt(int8(sdivisible8(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int8ToAuxInt(int8(sdivisible8(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v5.AuxInt = int8ToAuxInt(int8(8 - sdivisible8(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v6.AuxInt = int8ToAuxInt(int8(sdivisible8(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh8x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh8x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd8 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh8Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh8x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 7 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 7 && kbar == 8-k) { continue } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(1< x (Const8 [y])) (Const8 [y])) // cond: oneBit8(y) // result: (Neq8 (And8 x (Const8 [y])) (Const8 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst8 || v_0_1.Type != t { continue } y := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || v_1.Type != t || auxIntToInt8(v_1.AuxInt) != y || !(oneBit8(y)) { continue } v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EqB (ConstBool [c]) (ConstBool [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool { continue } c := auxIntToBool(v_0.AuxInt) if v_1.Op != OpConstBool { continue } d := auxIntToBool(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (EqB (ConstBool [false]) x) // result: (Not x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != false { continue } x := v_1 v.reset(OpNot) v.AddArg(x) return true } break } // match: (EqB (ConstBool [true]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != true { continue } x := v_1 v.copyOf(x) return true } break } return false } func rewriteValuegeneric_OpEqInter(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqInter x y) // result: (EqPtr (ITab x) (ITab y)) for { x := v_0 y := v_1 v.reset(OpEqPtr) v0 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqPtr x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (EqPtr (Addr {x} _) (Addr {y} _)) // result: (ConstBool [x == y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y) return true } break } // match: (EqPtr (Addr {x} _) (OffPtr [o] (Addr {y} _))) // result: (ConstBool [x == y && o == 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o == 0) return true } break } // match: (EqPtr (OffPtr [o1] (Addr {x} _)) (OffPtr [o2] (Addr {y} _))) // result: (ConstBool [x == y && o1 == o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o1 == o2) return true } break } // match: (EqPtr (LocalAddr {x} _ _) (LocalAddr {y} _ _)) // result: (ConstBool [x == y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpLocalAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y) return true } break } // match: (EqPtr (LocalAddr {x} _ _) (OffPtr [o] (LocalAddr {y} _ _))) // result: (ConstBool [x == y && o == 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o == 0) return true } break } // match: (EqPtr (OffPtr [o1] (LocalAddr {x} _ _)) (OffPtr [o2] (LocalAddr {y} _ _))) // result: (ConstBool [x == y && o1 == o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o1 == o2) return true } break } // match: (EqPtr (OffPtr [o1] p1) p2) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 == 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 == 0) return true } break } // match: (EqPtr (OffPtr [o1] p1) (OffPtr [o2] p2)) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 == o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 == o2) return true } break } // match: (EqPtr (Const32 [c]) (Const32 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (EqPtr (Const64 [c]) (Const64 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (EqPtr (LocalAddr _ _) (Addr _)) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (OffPtr (LocalAddr _ _)) (Addr _)) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (LocalAddr _ _) (OffPtr (Addr _))) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (OffPtr (LocalAddr _ _)) (OffPtr (Addr _))) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (AddPtr p1 o1) p2) // cond: isSamePtr(p1, p2) // result: (Not (IsNonNil o1)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddPtr { continue } o1 := v_0.Args[1] p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(o1) v.AddArg(v0) return true } break } // match: (EqPtr (Const32 [0]) p) // result: (Not (IsNonNil p)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(p) v.AddArg(v0) return true } break } // match: (EqPtr (Const64 [0]) p) // result: (Not (IsNonNil p)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(p) v.AddArg(v0) return true } break } // match: (EqPtr (ConstNil) p) // result: (Not (IsNonNil p)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstNil { continue } p := v_1 v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(p) v.AddArg(v0) return true } break } return false } func rewriteValuegeneric_OpEqSlice(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqSlice x y) // result: (EqPtr (SlicePtr x) (SlicePtr y)) for { x := v_0 y := v_1 v.reset(OpEqPtr) v0 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpIMake(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (IMake _typ (StructMake1 val)) // result: (IMake _typ val) for { _typ := v_0 if v_1.Op != OpStructMake1 { break } val := v_1.Args[0] v.reset(OpIMake) v.AddArg2(_typ, val) return true } // match: (IMake _typ (ArrayMake1 val)) // result: (IMake _typ val) for { _typ := v_0 if v_1.Op != OpArrayMake1 { break } val := v_1.Args[0] v.reset(OpIMake) v.AddArg2(_typ, val) return true } return false } func rewriteValuegeneric_OpInterLECall(v *Value) bool { // match: (InterLECall [argsize] {auxCall} (Load (OffPtr [off] (ITab (IMake (Addr {itab} (SB)) _))) _) ___) // cond: devirtLESym(v, auxCall, itab, off) != nil // result: devirtLECall(v, devirtLESym(v, auxCall, itab, off)) for { if len(v.Args) < 1 { break } auxCall := auxToCall(v.Aux) v_0 := v.Args[0] if v_0.Op != OpLoad { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpOffPtr { break } off := auxIntToInt64(v_0_0.AuxInt) v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpITab { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpIMake { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAddr { break } itab := auxToSym(v_0_0_0_0_0.Aux) v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpSB || !(devirtLESym(v, auxCall, itab, off) != nil) { break } v.copyOf(devirtLECall(v, devirtLESym(v, auxCall, itab, off))) return true } return false } func rewriteValuegeneric_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (IsInBounds (ZeroExt8to32 _) (Const32 [c])) // cond: (1 << 8) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to32 || v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !((1 << 8) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt8to64 _) (Const64 [c])) // cond: (1 << 8) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to64 || v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !((1 << 8) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt16to32 _) (Const32 [c])) // cond: (1 << 16) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to32 || v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !((1 << 16) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt16to64 _) (Const64 [c])) // cond: (1 << 16) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to64 || v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !((1 << 16) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (IsInBounds (And8 (Const8 [c]) _) (Const8 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd8 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt8to16 (And8 (Const8 [c]) _)) (Const16 [d])) // cond: 0 <= c && int16(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) if !(0 <= c && int16(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt8to32 (And8 (Const8 [c]) _)) (Const32 [d])) // cond: 0 <= c && int32(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) if !(0 <= c && int32(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt8to64 (And8 (Const8 [c]) _)) (Const64 [d])) // cond: 0 <= c && int64(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && int64(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (And16 (Const16 [c]) _) (Const16 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd16 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt16to32 (And16 (Const16 [c]) _)) (Const32 [d])) // cond: 0 <= c && int32(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) if !(0 <= c && int32(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt16to64 (And16 (Const16 [c]) _)) (Const64 [d])) // cond: 0 <= c && int64(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && int64(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (And32 (Const32 [c]) _) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd32 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt32to64 (And32 (Const32 [c]) _)) (Const64 [d])) // cond: 0 <= c && int64(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt32to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd32 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && int64(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (And64 (Const64 [c]) _) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd64 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (Const32 [c]) (Const32 [d])) // result: (ConstBool [0 <= c && c < d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(0 <= c && c < d) return true } // match: (IsInBounds (Const64 [c]) (Const64 [d])) // result: (ConstBool [0 <= c && c < d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(0 <= c && c < d) return true } // match: (IsInBounds (Mod32u _ y) y) // result: (ConstBool [true]) for { if v_0.Op != OpMod32u { break } y := v_0.Args[1] if y != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (Mod64u _ y) y) // result: (ConstBool [true]) for { if v_0.Op != OpMod64u { break } y := v_0.Args[1] if y != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt8to64 (Rsh8Ux64 _ (Const64 [c]))) (Const64 [d])) // cond: 0 < c && c < 8 && 1<= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 || v_1.Op != OpAnd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq16 (Const16 [0]) (Rsh16Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 || v_1.Op != OpRsh16Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq16U (Const16 [c]) (Const16 [d])) // result: (ConstBool [uint16(c) <= uint16(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint16(c) <= uint16(d)) return true } // match: (Leq16U (Const16 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } // match: (Leq32 (Const32 [0]) (And32 _ (Const32 [c]))) // cond: c >= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 || v_1.Op != OpAnd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq32 (Const32 [0]) (Rsh32Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 || v_1.Op != OpRsh32Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } return false } func rewriteValuegeneric_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq32U (Const32 [c]) (Const32 [d])) // result: (ConstBool [uint32(c) <= uint32(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint32(c) <= uint32(d)) return true } // match: (Leq32U (Const32 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } // match: (Leq64 (Const64 [0]) (And64 _ (Const64 [c]))) // cond: c >= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 || v_1.Op != OpAnd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq64 (Const64 [0]) (Rsh64Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 || v_1.Op != OpRsh64Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } return false } func rewriteValuegeneric_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq64U (Const64 [c]) (Const64 [d])) // result: (ConstBool [uint64(c) <= uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint64(c) <= uint64(d)) return true } // match: (Leq64U (Const64 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } // match: (Leq8 (Const8 [0]) (And8 _ (Const8 [c]))) // cond: c >= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 || v_1.Op != OpAnd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq8 (Const8 [0]) (Rsh8Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 || v_1.Op != OpRsh8Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq8U (Const8 [c]) (Const8 [d])) // result: (ConstBool [ uint8(c) <= uint8(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint8(c) <= uint8(d)) return true } // match: (Leq8U (Const8 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16 (Const16 [c]) (Const16 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less16 (Const16 [0]) x) // cond: isNonNegative(x) // result: (Neq16 (Const16 [0]) x) for { if v_0.Op != OpConst16 { break } t := v_0.Type if auxIntToInt16(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less16 x (Const16 [1])) // cond: isNonNegative(x) // result: (Eq16 (Const16 [0]) x) for { x := v_0 if v_1.Op != OpConst16 { break } t := v_1.Type if auxIntToInt16(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less16U (Const16 [c]) (Const16 [d])) // result: (ConstBool [uint16(c) < uint16(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint16(c) < uint16(d)) return true } // match: (Less16U _ (Const16 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less32 (Const32 [0]) x) // cond: isNonNegative(x) // result: (Neq32 (Const32 [0]) x) for { if v_0.Op != OpConst32 { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less32 x (Const32 [1])) // cond: isNonNegative(x) // result: (Eq32 (Const32 [0]) x) for { x := v_0 if v_1.Op != OpConst32 { break } t := v_1.Type if auxIntToInt32(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } return false } func rewriteValuegeneric_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less32U (Const32 [c]) (Const32 [d])) // result: (ConstBool [uint32(c) < uint32(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint32(c) < uint32(d)) return true } // match: (Less32U _ (Const32 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less64 (Const64 [0]) x) // cond: isNonNegative(x) // result: (Neq64 (Const64 [0]) x) for { if v_0.Op != OpConst64 { break } t := v_0.Type if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less64 x (Const64 [1])) // cond: isNonNegative(x) // result: (Eq64 (Const64 [0]) x) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } return false } func rewriteValuegeneric_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less64U (Const64 [c]) (Const64 [d])) // result: (ConstBool [uint64(c) < uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint64(c) < uint64(d)) return true } // match: (Less64U _ (Const64 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less8 (Const8 [0]) x) // cond: isNonNegative(x) // result: (Neq8 (Const8 [0]) x) for { if v_0.Op != OpConst8 { break } t := v_0.Type if auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less8 x (Const8 [1])) // cond: isNonNegative(x) // result: (Eq8 (Const8 [0]) x) for { x := v_0 if v_1.Op != OpConst8 { break } t := v_1.Type if auxIntToInt8(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less8U (Const8 [c]) (Const8 [d])) // result: (ConstBool [ uint8(c) < uint8(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint8(c) < uint8(d)) return true } // match: (Less8U _ (Const8 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (Load p1 (Store {t2} p2 x _)) // cond: isSamePtr(p1, p2) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) x := v_1.Args[1] p2 := v_1.Args[0] if !(isSamePtr(p1, p2) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size()) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 x _))) // cond: isSamePtr(p1, p3) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p3, t3.Size(), p2, t2.Size()) // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) x := v_1_2.Args[1] p3 := v_1_2.Args[0] if !(isSamePtr(p1, p3) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p3, t3.Size(), p2, t2.Size())) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 x _)))) // cond: isSamePtr(p1, p4) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p4, t4.Size(), p2, t2.Size()) && disjoint(p4, t4.Size(), p3, t3.Size()) // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) x := v_1_2_2.Args[1] p4 := v_1_2_2.Args[0] if !(isSamePtr(p1, p4) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p4, t4.Size(), p2, t2.Size()) && disjoint(p4, t4.Size(), p3, t3.Size())) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 x _))))) // cond: isSamePtr(p1, p5) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p5, t5.Size(), p2, t2.Size()) && disjoint(p5, t5.Size(), p3, t3.Size()) && disjoint(p5, t5.Size(), p4, t4.Size()) // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] v_1_2_2_2 := v_1_2_2.Args[2] if v_1_2_2_2.Op != OpStore { break } t5 := auxToType(v_1_2_2_2.Aux) x := v_1_2_2_2.Args[1] p5 := v_1_2_2_2.Args[0] if !(isSamePtr(p1, p5) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p5, t5.Size(), p2, t2.Size()) && disjoint(p5, t5.Size(), p3, t3.Size()) && disjoint(p5, t5.Size(), p4, t4.Size())) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 (Const64 [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x))) // result: (Const64F [math.Float64frombits(uint64(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } x := auxIntToInt64(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x)))) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(math.Float64frombits(uint64(x))) return true } // match: (Load p1 (Store {t2} p2 (Const32 [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x)))) // result: (Const32F [math.Float32frombits(uint32(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } x := auxIntToInt32(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x))))) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(math.Float32frombits(uint32(x))) return true } // match: (Load p1 (Store {t2} p2 (Const64F [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitInt(t1) // result: (Const64 [int64(math.Float64bits(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64F { break } x := auxIntToFloat64(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitInt(t1)) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(math.Float64bits(x))) return true } // match: (Load p1 (Store {t2} p2 (Const32F [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitInt(t1) // result: (Const32 [int32(math.Float32bits(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32F { break } x := auxIntToFloat32(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitInt(t1)) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(math.Float32bits(x))) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ mem:(Zero [n] p3 _))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p3) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) // result: @mem.Block (Load (OffPtr [o1] p3) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] mem := v_1.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p3 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p3) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p3) v0.AddArg2(v1, mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ mem:(Zero [n] p4 _)))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p4) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) // result: @mem.Block (Load (OffPtr [o1] p4) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] mem := v_1_2.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p4 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p4) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p4) v0.AddArg2(v1, mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ mem:(Zero [n] p5 _))))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p5) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) // result: @mem.Block (Load (OffPtr [o1] p5) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] mem := v_1_2_2.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p5 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p5) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p5) v0.AddArg2(v1, mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 _ mem:(Zero [n] p6 _)))))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p6) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) && disjoint(op, t1.Size(), p5, t5.Size()) // result: @mem.Block (Load (OffPtr [o1] p6) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] v_1_2_2_2 := v_1_2_2.Args[2] if v_1_2_2_2.Op != OpStore { break } t5 := auxToType(v_1_2_2_2.Aux) _ = v_1_2_2_2.Args[2] p5 := v_1_2_2_2.Args[0] mem := v_1_2_2_2.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p6 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p6) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) && disjoint(op, t1.Size(), p5, t5.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p6) v0.AddArg2(v1, mem) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: t1.IsBoolean() && isSamePtr(p1, p2) && n >= o + 1 // result: (ConstBool [false]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(t1.IsBoolean() && isSamePtr(p1, p2) && n >= o+1) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is8BitInt(t1) && isSamePtr(p1, p2) && n >= o + 1 // result: (Const8 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is8BitInt(t1) && isSamePtr(p1, p2) && n >= o+1) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is16BitInt(t1) && isSamePtr(p1, p2) && n >= o + 2 // result: (Const16 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is16BitInt(t1) && isSamePtr(p1, p2) && n >= o+2) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is32BitInt(t1) && isSamePtr(p1, p2) && n >= o + 4 // result: (Const32 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is32BitInt(t1) && isSamePtr(p1, p2) && n >= o+4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is64BitInt(t1) && isSamePtr(p1, p2) && n >= o + 8 // result: (Const64 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is64BitInt(t1) && isSamePtr(p1, p2) && n >= o+8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is32BitFloat(t1) && isSamePtr(p1, p2) && n >= o + 4 // result: (Const32F [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is32BitFloat(t1) && isSamePtr(p1, p2) && n >= o+4) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is64BitFloat(t1) && isSamePtr(p1, p2) && n >= o + 8 // result: (Const64F [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is64BitFloat(t1) && isSamePtr(p1, p2) && n >= o+8) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(0) return true } // match: (Load _ _) // cond: t.IsStruct() && t.NumFields() == 0 && fe.CanSSA(t) // result: (StructMake0) for { t := v.Type if !(t.IsStruct() && t.NumFields() == 0 && fe.CanSSA(t)) { break } v.reset(OpStructMake0) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 1 && fe.CanSSA(t) // result: (StructMake1 (Load (OffPtr [0] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 1 && fe.CanSSA(t)) { break } v.reset(OpStructMake1) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v.AddArg(v0) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 2 && fe.CanSSA(t) // result: (StructMake2 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 2 && fe.CanSSA(t)) { break } v.reset(OpStructMake2) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = int64ToAuxInt(t.FieldOff(1)) v3.AddArg(ptr) v2.AddArg2(v3, mem) v.AddArg2(v0, v2) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 3 && fe.CanSSA(t) // result: (StructMake3 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem) (Load (OffPtr [t.FieldOff(2)] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 3 && fe.CanSSA(t)) { break } v.reset(OpStructMake3) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = int64ToAuxInt(t.FieldOff(1)) v3.AddArg(ptr) v2.AddArg2(v3, mem) v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2)) v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v5.AuxInt = int64ToAuxInt(t.FieldOff(2)) v5.AddArg(ptr) v4.AddArg2(v5, mem) v.AddArg3(v0, v2, v4) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 4 && fe.CanSSA(t) // result: (StructMake4 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem) (Load (OffPtr [t.FieldOff(2)] ptr) mem) (Load (OffPtr [t.FieldOff(3)] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 4 && fe.CanSSA(t)) { break } v.reset(OpStructMake4) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = int64ToAuxInt(t.FieldOff(1)) v3.AddArg(ptr) v2.AddArg2(v3, mem) v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2)) v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v5.AuxInt = int64ToAuxInt(t.FieldOff(2)) v5.AddArg(ptr) v4.AddArg2(v5, mem) v6 := b.NewValue0(v.Pos, OpLoad, t.FieldType(3)) v7 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo()) v7.AuxInt = int64ToAuxInt(t.FieldOff(3)) v7.AddArg(ptr) v6.AddArg2(v7, mem) v.AddArg4(v0, v2, v4, v6) return true } // match: (Load _ _) // cond: t.IsArray() && t.NumElem() == 0 // result: (ArrayMake0) for { t := v.Type if !(t.IsArray() && t.NumElem() == 0) { break } v.reset(OpArrayMake0) return true } // match: (Load ptr mem) // cond: t.IsArray() && t.NumElem() == 1 && fe.CanSSA(t) // result: (ArrayMake1 (Load ptr mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsArray() && t.NumElem() == 1 && fe.CanSSA(t)) { break } v.reset(OpArrayMake1) v0 := b.NewValue0(v.Pos, OpLoad, t.Elem()) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x16 x (Const16 [c])) // result: (Lsh16x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh16x16 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x32 x (Const32 [c])) // result: (Lsh16x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh16x32 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x64 (Const16 [c]) (Const64 [d])) // result: (Const16 [c << uint64(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c << uint64(d)) return true } // match: (Lsh16x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh16x64 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Lsh16x64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Lsh16x64 (Lsh16x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh16x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh16x64 (Rsh16Ux64 (Lsh16x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh16x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh16x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x8 x (Const8 [c])) // result: (Lsh16x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh16x8 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x16 x (Const16 [c])) // result: (Lsh32x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh32x16 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x32 x (Const32 [c])) // result: (Lsh32x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh32x32 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x64 (Const32 [c]) (Const64 [d])) // result: (Const32 [c << uint64(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c << uint64(d)) return true } // match: (Lsh32x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh32x64 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Lsh32x64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Lsh32x64 (Lsh32x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh32x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh32x64 (Rsh32Ux64 (Lsh32x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh32x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh32x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x8 x (Const8 [c])) // result: (Lsh32x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh32x8 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x16 x (Const16 [c])) // result: (Lsh64x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh64x16 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x32 x (Const32 [c])) // result: (Lsh64x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh64x32 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c << uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c << uint64(d)) return true } // match: (Lsh64x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh64x64 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Lsh64x64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (Const64 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 64) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Lsh64x64 (Lsh64x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh64x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh64x64 (Rsh64Ux64 (Lsh64x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh64x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh64x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x8 x (Const8 [c])) // result: (Lsh64x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh64x8 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x16 x (Const16 [c])) // result: (Lsh8x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh8x16 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x32 x (Const32 [c])) // result: (Lsh8x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh8x32 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x64 (Const8 [c]) (Const64 [d])) // result: (Const8 [c << uint64(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c << uint64(d)) return true } // match: (Lsh8x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh8x64 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Lsh8x64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Lsh8x64 (Lsh8x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh8x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh8x64 (Rsh8Ux64 (Lsh8x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh8x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh8x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x8 x (Const8 [c])) // result: (Lsh8x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh8x8 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod16 (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [c % d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c % d) return true } // match: (Mod16 n (Const16 [c])) // cond: isNonNegative(n) && isPowerOfTwo16(c) // result: (And16 n (Const16 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo16(c)) { break } v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod16 n (Const16 [c])) // cond: c < 0 && c != -1<<15 // result: (Mod16 n (Const16 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(c < 0 && c != -1<<15) { break } v.reset(OpMod16) v.Type = t v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod16 x (Const16 [c])) // cond: x.Op != OpConst16 && (c > 0 || c == -1<<15) // result: (Sub16 x (Mul16 (Div16 x (Const16 [c])) (Const16 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(x.Op != OpConst16 && (c > 0 || c == -1<<15)) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpMul16, t) v1 := b.NewValue0(v.Pos, OpDiv16, t) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod16u (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int16(uint16(c) % uint16(d))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint16(c) % uint16(d))) return true } // match: (Mod16u n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (And16 n (Const16 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { break } v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod16u x (Const16 [c])) // cond: x.Op != OpConst16 && c > 0 && umagicOK16(c) // result: (Sub16 x (Mul16 (Div16u x (Const16 [c])) (Const16 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(x.Op != OpConst16 && c > 0 && umagicOK16(c)) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpMul16, t) v1 := b.NewValue0(v.Pos, OpDiv16u, t) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod32 (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [c % d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c % d) return true } // match: (Mod32 n (Const32 [c])) // cond: isNonNegative(n) && isPowerOfTwo32(c) // result: (And32 n (Const32 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo32(c)) { break } v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod32 n (Const32 [c])) // cond: c < 0 && c != -1<<31 // result: (Mod32 n (Const32 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(c < 0 && c != -1<<31) { break } v.reset(OpMod32) v.Type = t v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod32 x (Const32 [c])) // cond: x.Op != OpConst32 && (c > 0 || c == -1<<31) // result: (Sub32 x (Mul32 (Div32 x (Const32 [c])) (Const32 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(x.Op != OpConst32 && (c > 0 || c == -1<<31)) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpMul32, t) v1 := b.NewValue0(v.Pos, OpDiv32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod32u (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int32(uint32(c) % uint32(d))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint32(c) % uint32(d))) return true } // match: (Mod32u n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (And32 n (Const32 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { break } v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod32u x (Const32 [c])) // cond: x.Op != OpConst32 && c > 0 && umagicOK32(c) // result: (Sub32 x (Mul32 (Div32u x (Const32 [c])) (Const32 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(x.Op != OpConst32 && c > 0 && umagicOK32(c)) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpMul32, t) v1 := b.NewValue0(v.Pos, OpDiv32u, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod64 (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [c % d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c % d) return true } // match: (Mod64 n (Const64 [c])) // cond: isNonNegative(n) && isPowerOfTwo64(c) // result: (And64 n (Const64 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo64(c)) { break } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod64 n (Const64 [-1<<63])) // cond: isNonNegative(n) // result: n for { n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 || !(isNonNegative(n)) { break } v.copyOf(n) return true } // match: (Mod64 n (Const64 [c])) // cond: c < 0 && c != -1<<63 // result: (Mod64 n (Const64 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c < 0 && c != -1<<63) { break } v.reset(OpMod64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod64 x (Const64 [c])) // cond: x.Op != OpConst64 && (c > 0 || c == -1<<63) // result: (Sub64 x (Mul64 (Div64 x (Const64 [c])) (Const64 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(x.Op != OpConst64 && (c > 0 || c == -1<<63)) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpMul64, t) v1 := b.NewValue0(v.Pos, OpDiv64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod64u (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [int64(uint64(c) % uint64(d))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint64(c) % uint64(d))) return true } // match: (Mod64u n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (And64 n (Const64 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod64u n (Const64 [-1<<63])) // result: (And64 n (Const64 [1<<63-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 { break } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(1<<63 - 1) v.AddArg2(n, v0) return true } // match: (Mod64u x (Const64 [c])) // cond: x.Op != OpConst64 && c > 0 && umagicOK64(c) // result: (Sub64 x (Mul64 (Div64u x (Const64 [c])) (Const64 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(x.Op != OpConst64 && c > 0 && umagicOK64(c)) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpMul64, t) v1 := b.NewValue0(v.Pos, OpDiv64u, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod8 (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [c % d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c % d) return true } // match: (Mod8 n (Const8 [c])) // cond: isNonNegative(n) && isPowerOfTwo8(c) // result: (And8 n (Const8 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo8(c)) { break } v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod8 n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Mod8 n (Const8 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(c < 0 && c != -1<<7) { break } v.reset(OpMod8) v.Type = t v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod8 x (Const8 [c])) // cond: x.Op != OpConst8 && (c > 0 || c == -1<<7) // result: (Sub8 x (Mul8 (Div8 x (Const8 [c])) (Const8 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(x.Op != OpConst8 && (c > 0 || c == -1<<7)) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpMul8, t) v1 := b.NewValue0(v.Pos, OpDiv8, t) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod8u (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int8(uint8(c) % uint8(d))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(uint8(c) % uint8(d))) return true } // match: (Mod8u n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (And8 n (Const8 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { break } v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod8u x (Const8 [c])) // cond: x.Op != OpConst8 && c > 0 && umagicOK8( c) // result: (Sub8 x (Mul8 (Div8u x (Const8 [c])) (Const8 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(x.Op != OpConst8 && c > 0 && umagicOK8(c)) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpMul8, t) v1 := b.NewValue0(v.Pos, OpDiv8u, t) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Move {t} [n] dst1 src mem:(Zero {t} [n] dst2 _)) // cond: isSamePtr(src, dst2) // result: (Zero {t} [n] dst1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src := v_1 mem := v_2 if mem.Op != OpZero || auxIntToInt64(mem.AuxInt) != n || auxToType(mem.Aux) != t { break } dst2 := mem.Args[0] if !(isSamePtr(src, dst2)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst1, mem) return true } // match: (Move {t} [n] dst1 src mem:(VarDef (Zero {t} [n] dst0 _))) // cond: isSamePtr(src, dst0) // result: (Zero {t} [n] dst1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpZero || auxIntToInt64(mem_0.AuxInt) != n || auxToType(mem_0.Aux) != t { break } dst0 := mem_0.Args[0] if !(isSamePtr(src, dst0)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst1, mem) return true } // match: (Move {t} [n] dst (Addr {sym} (SB)) mem) // cond: symIsROZero(sym) // result: (Zero {t} [n] dst mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst := v_0 if v_1.Op != OpAddr { break } sym := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } mem := v_2 if !(symIsROZero(sym)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst, mem) return true } // match: (Move {t1} [n] dst1 src1 store:(Store {t2} op:(OffPtr [o2] dst2) _ mem)) // cond: isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2 + t2.Size() && disjoint(src1, n, op, t2.Size()) && clobber(store) // result: (Move {t1} [n] dst1 src1 mem) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst1 := v_0 src1 := v_1 store := v_2 if store.Op != OpStore { break } t2 := auxToType(store.Aux) mem := store.Args[2] op := store.Args[0] if op.Op != OpOffPtr { break } o2 := auxIntToInt64(op.AuxInt) dst2 := op.Args[0] if !(isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2+t2.Size() && disjoint(src1, n, op, t2.Size()) && clobber(store)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t1) v.AddArg3(dst1, src1, mem) return true } // match: (Move {t} [n] dst1 src1 move:(Move {t} [n] dst2 _ mem)) // cond: move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move) // result: (Move {t} [n] dst1 src1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 move := v_2 if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg3(dst1, src1, mem) return true } // match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem))) // cond: move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move, vardef) // result: (Move {t} [n] dst1 src1 (VarDef {x} mem)) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 vardef := v_2 if vardef.Op != OpVarDef { break } x := auxToSym(vardef.Aux) move := vardef.Args[0] if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move, vardef)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg3(dst1, src1, v0) return true } // match: (Move {t} [n] dst1 src1 zero:(Zero {t} [n] dst2 mem)) // cond: zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero) // result: (Move {t} [n] dst1 src1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 zero := v_2 if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != n || auxToType(zero.Aux) != t { break } mem := zero.Args[1] dst2 := zero.Args[0] if !(zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg3(dst1, src1, mem) return true } // match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} zero:(Zero {t} [n] dst2 mem))) // cond: zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero, vardef) // result: (Move {t} [n] dst1 src1 (VarDef {x} mem)) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 vardef := v_2 if vardef.Op != OpVarDef { break } x := auxToSym(vardef.Aux) zero := vardef.Args[0] if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != n || auxToType(zero.Aux) != t { break } mem := zero.Args[1] dst2 := zero.Args[0] if !(zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero, vardef)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg3(dst1, src1, v0) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [0] p3) d2 _))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size() + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [0] dst) d2 mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) d2 := mem_2.Args[1] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type if auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size()+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(0) v2.AddArg(dst) v1.AddArg3(v2, d2, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [0] p4) d3 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [0] dst) d3 mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) d3 := mem_2_2.Args[1] op4 := mem_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type if auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(0) v4.AddArg(dst) v3.AddArg3(v4, d3, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [o4] p4) d3 (Store {t5} op5:(OffPtr [0] p5) d4 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [0] dst) d4 mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] op4 := mem_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type o4 := auxIntToInt64(op4.AuxInt) p4 := op4.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpStore { break } t5 := auxToType(mem_2_2_2.Aux) d4 := mem_2_2_2.Args[1] op5 := mem_2_2_2.Args[0] if op5.Op != OpOffPtr { break } tt5 := op5.Type if auxIntToInt64(op5.AuxInt) != 0 { break } p5 := op5.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(0) v6.AddArg(dst) v5.AddArg3(v6, d4, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [0] p3) d2 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size() + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [0] dst) d2 mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) d2 := mem_0_2.Args[1] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type if auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size()+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(0) v2.AddArg(dst) v1.AddArg3(v2, d2, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [0] p4) d3 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [0] dst) d3 mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) d3 := mem_0_2_2.Args[1] op4 := mem_0_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type if auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(0) v4.AddArg(dst) v3.AddArg3(v4, d3, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [o4] p4) d3 (Store {t5} op5:(OffPtr [0] p5) d4 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [0] dst) d4 mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) _ = mem_0_2_2.Args[2] op4 := mem_0_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type o4 := auxIntToInt64(op4.AuxInt) p4 := op4.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpStore { break } t5 := auxToType(mem_0_2_2_2.Aux) d4 := mem_0_2_2_2.Args[1] op5 := mem_0_2_2_2.Args[0] if op5.Op != OpOffPtr { break } tt5 := op5.Type if auxIntToInt64(op5.AuxInt) != 0 { break } p5 := op5.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(0) v6.AddArg(dst) v5.AddArg3(v6, d4, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Zero {t3} [n] p3 _))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2 + t2.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Zero {t1} [n] dst mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpZero || auxIntToInt64(mem_2.AuxInt) != n { break } t3 := auxToType(mem_2.Aux) p3 := mem_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2+t2.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(n) v1.Aux = typeToAux(t1) v1.AddArg2(dst, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Zero {t4} [n] p4 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + t2.Size() && n >= o3 + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Zero {t1} [n] dst mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := auxIntToInt64(mem_0.AuxInt) p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := auxIntToInt64(mem_2_0.AuxInt) p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpZero || auxIntToInt64(mem_2_2.AuxInt) != n { break } t4 := auxToType(mem_2_2.Aux) p4 := mem_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2+t2.Size() && n >= o3+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v3.AuxInt = int64ToAuxInt(n) v3.Aux = typeToAux(t1) v3.AddArg2(dst, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Zero {t5} [n] p5 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Zero {t1} [n] dst mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := auxIntToInt64(mem_0.AuxInt) p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := auxIntToInt64(mem_2_0.AuxInt) p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] mem_2_2_0 := mem_2_2.Args[0] if mem_2_2_0.Op != OpOffPtr { break } tt4 := mem_2_2_0.Type o4 := auxIntToInt64(mem_2_2_0.AuxInt) p4 := mem_2_2_0.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpZero || auxIntToInt64(mem_2_2_2.AuxInt) != n { break } t5 := auxToType(mem_2_2_2.Aux) p5 := mem_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v5.AuxInt = int64ToAuxInt(n) v5.Aux = typeToAux(t1) v5.AddArg2(dst, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Store {t5} (OffPtr [o5] p5) d4 (Zero {t6} [n] p6 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() && n >= o5 + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [o5] dst) d4 (Zero {t1} [n] dst mem))))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := auxIntToInt64(mem_0.AuxInt) p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := auxIntToInt64(mem_2_0.AuxInt) p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] mem_2_2_0 := mem_2_2.Args[0] if mem_2_2_0.Op != OpOffPtr { break } tt4 := mem_2_2_0.Type o4 := auxIntToInt64(mem_2_2_0.AuxInt) p4 := mem_2_2_0.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpStore { break } t5 := auxToType(mem_2_2_2.Aux) _ = mem_2_2_2.Args[2] mem_2_2_2_0 := mem_2_2_2.Args[0] if mem_2_2_2_0.Op != OpOffPtr { break } tt5 := mem_2_2_2_0.Type o5 := auxIntToInt64(mem_2_2_2_0.AuxInt) p5 := mem_2_2_2_0.Args[0] d4 := mem_2_2_2.Args[1] mem_2_2_2_2 := mem_2_2_2.Args[2] if mem_2_2_2_2.Op != OpZero || auxIntToInt64(mem_2_2_2_2.AuxInt) != n { break } t6 := auxToType(mem_2_2_2_2.Aux) p6 := mem_2_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size() && n >= o5+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(o5) v6.AddArg(dst) v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v7.AuxInt = int64ToAuxInt(n) v7.Aux = typeToAux(t1) v7.AddArg2(dst, mem) v5.AddArg3(v6, d4, v7) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Zero {t3} [n] p3 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2 + t2.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Zero {t1} [n] dst mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpZero || auxIntToInt64(mem_0_2.AuxInt) != n { break } t3 := auxToType(mem_0_2.Aux) p3 := mem_0_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2+t2.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(n) v1.Aux = typeToAux(t1) v1.AddArg2(dst, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Zero {t4} [n] p4 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + t2.Size() && n >= o3 + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Zero {t1} [n] dst mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := auxIntToInt64(mem_0_0.AuxInt) p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := auxIntToInt64(mem_0_2_0.AuxInt) p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2.AuxInt) != n { break } t4 := auxToType(mem_0_2_2.Aux) p4 := mem_0_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2+t2.Size() && n >= o3+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v3.AuxInt = int64ToAuxInt(n) v3.Aux = typeToAux(t1) v3.AddArg2(dst, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Zero {t5} [n] p5 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Zero {t1} [n] dst mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := auxIntToInt64(mem_0_0.AuxInt) p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := auxIntToInt64(mem_0_2_0.AuxInt) p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) _ = mem_0_2_2.Args[2] mem_0_2_2_0 := mem_0_2_2.Args[0] if mem_0_2_2_0.Op != OpOffPtr { break } tt4 := mem_0_2_2_0.Type o4 := auxIntToInt64(mem_0_2_2_0.AuxInt) p4 := mem_0_2_2_0.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2_2.AuxInt) != n { break } t5 := auxToType(mem_0_2_2_2.Aux) p5 := mem_0_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v5.AuxInt = int64ToAuxInt(n) v5.Aux = typeToAux(t1) v5.AddArg2(dst, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Store {t5} (OffPtr [o5] p5) d4 (Zero {t6} [n] p6 _))))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() && n >= o5 + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [o5] dst) d4 (Zero {t1} [n] dst mem))))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := auxIntToInt64(mem_0_0.AuxInt) p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := auxIntToInt64(mem_0_2_0.AuxInt) p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) _ = mem_0_2_2.Args[2] mem_0_2_2_0 := mem_0_2_2.Args[0] if mem_0_2_2_0.Op != OpOffPtr { break } tt4 := mem_0_2_2_0.Type o4 := auxIntToInt64(mem_0_2_2_0.AuxInt) p4 := mem_0_2_2_0.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpStore { break } t5 := auxToType(mem_0_2_2_2.Aux) _ = mem_0_2_2_2.Args[2] mem_0_2_2_2_0 := mem_0_2_2_2.Args[0] if mem_0_2_2_2_0.Op != OpOffPtr { break } tt5 := mem_0_2_2_2_0.Type o5 := auxIntToInt64(mem_0_2_2_2_0.AuxInt) p5 := mem_0_2_2_2_0.Args[0] d4 := mem_0_2_2_2.Args[1] mem_0_2_2_2_2 := mem_0_2_2_2.Args[2] if mem_0_2_2_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2_2_2.AuxInt) != n { break } t6 := auxToType(mem_0_2_2_2_2.Aux) p6 := mem_0_2_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size() && n >= o5+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(o5) v6.AddArg(dst) v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v7.AuxInt = int64ToAuxInt(n) v7.Aux = typeToAux(t1) v7.AddArg2(dst, mem) v5.AddArg3(v6, d4, v7) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [s] dst tmp1 midmem:(Move {t2} [s] tmp2 src _)) // cond: t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config)) // result: (Move {t1} [s] dst src midmem) for { s := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 tmp1 := v_1 midmem := v_2 if midmem.Op != OpMove || auxIntToInt64(midmem.AuxInt) != s { break } t2 := auxToType(midmem.Aux) src := midmem.Args[1] tmp2 := midmem.Args[0] if !(t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s) v.Aux = typeToAux(t1) v.AddArg3(dst, src, midmem) return true } // match: (Move {t1} [s] dst tmp1 midmem:(VarDef (Move {t2} [s] tmp2 src _))) // cond: t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config)) // result: (Move {t1} [s] dst src midmem) for { s := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 tmp1 := v_1 midmem := v_2 if midmem.Op != OpVarDef { break } midmem_0 := midmem.Args[0] if midmem_0.Op != OpMove || auxIntToInt64(midmem_0.AuxInt) != s { break } t2 := auxToType(midmem_0.Aux) src := midmem_0.Args[1] tmp2 := midmem_0.Args[0] if !(t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s) v.Aux = typeToAux(t1) v.AddArg3(dst, src, midmem) return true } // match: (Move dst src mem) // cond: isSamePtr(dst, src) // result: mem for { dst := v_0 src := v_1 mem := v_2 if !(isSamePtr(dst, src)) { break } v.copyOf(mem) return true } return false } func rewriteValuegeneric_OpMul16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c * d) return true } break } // match: (Mul16 (Const16 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul16 (Const16 [-1]) x) // result: (Neg16 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg16) v.AddArg(x) return true } break } // match: (Mul16 n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (Lsh16x64 n (Const64 [log16(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { continue } v.reset(OpLsh16x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log16(c)) v.AddArg2(n, v0) return true } break } // match: (Mul16 n (Const16 [c])) // cond: t.IsSigned() && isPowerOfTwo16(-c) // result: (Neg16 (Lsh16x64 n (Const64 [log16(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo16(-c)) { continue } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log16(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul16 (Const16 [0]) _) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (Mul16 (Mul16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Mul16 i (Mul16 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpMul16, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul16 (Const16 [c]) (Mul16 (Const16 [d]) x)) // result: (Mul16 (Const16 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpMul32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c * d) return true } break } // match: (Mul32 (Const32 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul32 (Const32 [-1]) x) // result: (Neg32 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg32) v.AddArg(x) return true } break } // match: (Mul32 n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (Lsh32x64 n (Const64 [log32(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { continue } v.reset(OpLsh32x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log32(c)) v.AddArg2(n, v0) return true } break } // match: (Mul32 n (Const32 [c])) // cond: t.IsSigned() && isPowerOfTwo32(-c) // result: (Neg32 (Lsh32x64 n (Const64 [log32(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo32(-c)) { continue } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpLsh32x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log32(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Add32 (Const32 [c*d]) (Mul32 (Const32 [c]) x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 || v_1.Type != t { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c * d) v1 := b.NewValue0(v.Pos, OpMul32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(c) v1.AddArg2(v2, x) v.AddArg2(v0, v1) return true } } break } // match: (Mul32 (Const32 [0]) _) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (Mul32 (Mul32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Mul32 i (Mul32 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpMul32, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul32 (Const32 [c]) (Mul32 (Const32 [d]) x)) // result: (Mul32 (Const32 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpMul32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mul32F (Const32F [c]) (Const32F [d])) // cond: c*d == c*d // result: (Const32F [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) if !(c*d == c*d) { continue } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c * d) return true } break } // match: (Mul32F x (Const32F [1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst32F || auxIntToFloat32(v_1.AuxInt) != 1 { continue } v.copyOf(x) return true } break } // match: (Mul32F x (Const32F [-1])) // result: (Neg32F x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst32F || auxIntToFloat32(v_1.AuxInt) != -1 { continue } v.reset(OpNeg32F) v.AddArg(x) return true } break } // match: (Mul32F x (Const32F [2])) // result: (Add32F x x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst32F || auxIntToFloat32(v_1.AuxInt) != 2 { continue } v.reset(OpAdd32F) v.AddArg2(x, x) return true } break } return false } func rewriteValuegeneric_OpMul64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c * d) return true } break } // match: (Mul64 (Const64 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul64 (Const64 [-1]) x) // result: (Neg64 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg64) v.AddArg(x) return true } break } // match: (Mul64 n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (Lsh64x64 n (Const64 [log64(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpLsh64x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(n, v0) return true } break } // match: (Mul64 n (Const64 [c])) // cond: t.IsSigned() && isPowerOfTwo64(-c) // result: (Neg64 (Lsh64x64 n (Const64 [log64(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo64(-c)) { continue } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpLsh64x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log64(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 || v_1.Type != t { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c * d) v1 := b.NewValue0(v.Pos, OpMul64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(c) v1.AddArg2(v2, x) v.AddArg2(v0, v1) return true } } break } // match: (Mul64 (Const64 [0]) _) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (Mul64 (Mul64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Mul64 i (Mul64 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpMul64, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul64 (Const64 [c]) (Mul64 (Const64 [d]) x)) // result: (Mul64 (Const64 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpMul64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mul64F (Const64F [c]) (Const64F [d])) // cond: c*d == c*d // result: (Const64F [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) if !(c*d == c*d) { continue } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c * d) return true } break } // match: (Mul64F x (Const64F [1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst64F || auxIntToFloat64(v_1.AuxInt) != 1 { continue } v.copyOf(x) return true } break } // match: (Mul64F x (Const64F [-1])) // result: (Neg64F x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst64F || auxIntToFloat64(v_1.AuxInt) != -1 { continue } v.reset(OpNeg64F) v.AddArg(x) return true } break } // match: (Mul64F x (Const64F [2])) // result: (Add64F x x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst64F || auxIntToFloat64(v_1.AuxInt) != 2 { continue } v.reset(OpAdd64F) v.AddArg2(x, x) return true } break } return false } func rewriteValuegeneric_OpMul8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c * d) return true } break } // match: (Mul8 (Const8 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul8 (Const8 [-1]) x) // result: (Neg8 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg8) v.AddArg(x) return true } break } // match: (Mul8 n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (Lsh8x64 n (Const64 [log8(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { continue } v.reset(OpLsh8x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log8(c)) v.AddArg2(n, v0) return true } break } // match: (Mul8 n (Const8 [c])) // cond: t.IsSigned() && isPowerOfTwo8(-c) // result: (Neg8 (Lsh8x64 n (Const64 [log8(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo8(-c)) { continue } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log8(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul8 (Const8 [0]) _) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (Mul8 (Mul8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Mul8 i (Mul8 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpMul8, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul8 (Const8 [c]) (Mul8 (Const8 [d]) x)) // result: (Mul8 (Const8 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpNeg16(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg16 (Const16 [c])) // result: (Const16 [-c]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-c) return true } // match: (Neg16 (Sub16 x y)) // result: (Sub16 y x) for { if v_0.Op != OpSub16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub16) v.AddArg2(y, x) return true } // match: (Neg16 (Neg16 x)) // result: x for { if v_0.Op != OpNeg16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg16 (Com16 x)) // result: (Add16 (Const16 [1]) x) for { t := v.Type if v_0.Op != OpCom16 { break } x := v_0.Args[0] v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeg32(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg32 (Const32 [c])) // result: (Const32 [-c]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-c) return true } // match: (Neg32 (Sub32 x y)) // result: (Sub32 y x) for { if v_0.Op != OpSub32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub32) v.AddArg2(y, x) return true } // match: (Neg32 (Neg32 x)) // result: x for { if v_0.Op != OpNeg32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg32 (Com32 x)) // result: (Add32 (Const32 [1]) x) for { t := v.Type if v_0.Op != OpCom32 { break } x := v_0.Args[0] v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeg32F(v *Value) bool { v_0 := v.Args[0] // match: (Neg32F (Const32F [c])) // cond: c != 0 // result: (Const32F [-c]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if !(c != 0) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(-c) return true } return false } func rewriteValuegeneric_OpNeg64(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg64 (Const64 [c])) // result: (Const64 [-c]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-c) return true } // match: (Neg64 (Sub64 x y)) // result: (Sub64 y x) for { if v_0.Op != OpSub64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub64) v.AddArg2(y, x) return true } // match: (Neg64 (Neg64 x)) // result: x for { if v_0.Op != OpNeg64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg64 (Com64 x)) // result: (Add64 (Const64 [1]) x) for { t := v.Type if v_0.Op != OpCom64 { break } x := v_0.Args[0] v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeg64F(v *Value) bool { v_0 := v.Args[0] // match: (Neg64F (Const64F [c])) // cond: c != 0 // result: (Const64F [-c]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if !(c != 0) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(-c) return true } return false } func rewriteValuegeneric_OpNeg8(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg8 (Const8 [c])) // result: (Const8 [-c]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-c) return true } // match: (Neg8 (Sub8 x y)) // result: (Sub8 y x) for { if v_0.Op != OpSub8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub8) v.AddArg2(y, x) return true } // match: (Neg8 (Neg8 x)) // result: x for { if v_0.Op != OpNeg8 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg8 (Com8 x)) // result: (Add8 (Const8 [1]) x) for { t := v.Type if v_0.Op != OpCom8 { break } x := v_0.Args[0] v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq16 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Neq16 (Const16 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq16 (Const16 [c]) (Const16 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Neq16 (And16 n (Const16 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh16x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh16x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd16 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh16Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh16x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 15 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 15 && kbar == 16-k) { continue } v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(1< x (Const16 [y])) (Const16 [y])) // cond: oneBit16(y) // result: (Eq16 (And16 x (Const16 [y])) (Const16 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst16 || v_0_1.Type != t { continue } y := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || v_1.Type != t || auxIntToInt16(v_1.AuxInt) != y || !(oneBit16(y)) { continue } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq32 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Neq32 (Const32 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Neq32 (And32 n (Const32 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh32x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd32 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh32Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh32x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 31 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 31 && kbar == 32-k) { continue } v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(1< x (Const32 [y])) (Const32 [y])) // cond: oneBit32(y) // result: (Eq32 (And32 x (Const32 [y])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst32 || v_0_1.Type != t { continue } y := auxIntToInt32(v_0_1.AuxInt) if v_1.Op != OpConst32 || v_1.Type != t || auxIntToInt32(v_1.AuxInt) != y || !(oneBit32(y)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Neq32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } return false } func rewriteValuegeneric_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq64 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Neq64 (Const64 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Neq64 (And64 n (Const64 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh64x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd64 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh64Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh64x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 63 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 63 && kbar == 64-k) { continue } v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(1< x (Const64 [y])) (Const64 [y])) // cond: oneBit64(y) // result: (Eq64 (And64 x (Const64 [y])) (Const64 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst64 || v_0_1.Type != t { continue } y := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 || v_1.Type != t || auxIntToInt64(v_1.AuxInt) != y || !(oneBit64(y)) { continue } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Neq64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } return false } func rewriteValuegeneric_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq8 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Neq8 (Const8 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Neq8 (And8 n (Const8 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh8x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh8x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd8 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh8Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh8x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 7 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 7 && kbar == 8-k) { continue } v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(1< x (Const8 [y])) (Const8 [y])) // cond: oneBit8(y) // result: (Eq8 (And8 x (Const8 [y])) (Const8 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst8 || v_0_1.Type != t { continue } y := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || v_1.Type != t || auxIntToInt8(v_1.AuxInt) != y || !(oneBit8(y)) { continue } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (NeqB (ConstBool [c]) (ConstBool [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool { continue } c := auxIntToBool(v_0.AuxInt) if v_1.Op != OpConstBool { continue } d := auxIntToBool(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (NeqB (ConstBool [false]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != false { continue } x := v_1 v.copyOf(x) return true } break } // match: (NeqB (ConstBool [true]) x) // result: (Not x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != true { continue } x := v_1 v.reset(OpNot) v.AddArg(x) return true } break } // match: (NeqB (Not x) (Not y)) // result: (NeqB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpNot { continue } x := v_0.Args[0] if v_1.Op != OpNot { continue } y := v_1.Args[0] v.reset(OpNeqB) v.AddArg2(x, y) return true } break } return false } func rewriteValuegeneric_OpNeqInter(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (NeqInter x y) // result: (NeqPtr (ITab x) (ITab y)) for { x := v_0 y := v_1 v.reset(OpNeqPtr) v0 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (NeqPtr x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (NeqPtr (Addr {x} _) (Addr {y} _)) // result: (ConstBool [x != y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y) return true } break } // match: (NeqPtr (Addr {x} _) (OffPtr [o] (Addr {y} _))) // result: (ConstBool [x != y || o != 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o != 0) return true } break } // match: (NeqPtr (OffPtr [o1] (Addr {x} _)) (OffPtr [o2] (Addr {y} _))) // result: (ConstBool [x != y || o1 != o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o1 != o2) return true } break } // match: (NeqPtr (LocalAddr {x} _ _) (LocalAddr {y} _ _)) // result: (ConstBool [x != y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpLocalAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y) return true } break } // match: (NeqPtr (LocalAddr {x} _ _) (OffPtr [o] (LocalAddr {y} _ _))) // result: (ConstBool [x != y || o != 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o != 0) return true } break } // match: (NeqPtr (OffPtr [o1] (LocalAddr {x} _ _)) (OffPtr [o2] (LocalAddr {y} _ _))) // result: (ConstBool [x != y || o1 != o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o1 != o2) return true } break } // match: (NeqPtr (OffPtr [o1] p1) p2) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 != 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 != 0) return true } break } // match: (NeqPtr (OffPtr [o1] p1) (OffPtr [o2] p2)) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 != o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 != o2) return true } break } // match: (NeqPtr (Const32 [c]) (Const32 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (NeqPtr (Const64 [c]) (Const64 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (NeqPtr (LocalAddr _ _) (Addr _)) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (OffPtr (LocalAddr _ _)) (Addr _)) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (LocalAddr _ _) (OffPtr (Addr _))) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (OffPtr (LocalAddr _ _)) (OffPtr (Addr _))) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (AddPtr p1 o1) p2) // cond: isSamePtr(p1, p2) // result: (IsNonNil o1) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddPtr { continue } o1 := v_0.Args[1] p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpIsNonNil) v.AddArg(o1) return true } break } // match: (NeqPtr (Const32 [0]) p) // result: (IsNonNil p) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpIsNonNil) v.AddArg(p) return true } break } // match: (NeqPtr (Const64 [0]) p) // result: (IsNonNil p) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpIsNonNil) v.AddArg(p) return true } break } // match: (NeqPtr (ConstNil) p) // result: (IsNonNil p) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstNil { continue } p := v_1 v.reset(OpIsNonNil) v.AddArg(p) return true } break } return false } func rewriteValuegeneric_OpNeqSlice(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (NeqSlice x y) // result: (NeqPtr (SlicePtr x) (SlicePtr y)) for { x := v_0 y := v_1 v.reset(OpNeqPtr) v0 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpNilCheck(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (NilCheck (GetG mem) mem) // result: mem for { if v_0.Op != OpGetG { break } mem := v_0.Args[0] if mem != v_1 { break } v.copyOf(mem) return true } // match: (NilCheck (SelectN [0] call:(StaticLECall _ _)) _) // cond: isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check") // result: (Invalid) for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { break } call := v_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 || !(isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check")) { break } v.reset(OpInvalid) return true } // match: (NilCheck (OffPtr (SelectN [0] call:(StaticLECall _ _))) _) // cond: isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check") // result: (Invalid) for { if v_0.Op != OpOffPtr { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpSelectN || auxIntToInt64(v_0_0.AuxInt) != 0 { break } call := v_0_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 || !(isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check")) { break } v.reset(OpInvalid) return true } return false } func rewriteValuegeneric_OpNot(v *Value) bool { v_0 := v.Args[0] // match: (Not (ConstBool [c])) // result: (ConstBool [!c]) for { if v_0.Op != OpConstBool { break } c := auxIntToBool(v_0.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(!c) return true } // match: (Not (Eq64 x y)) // result: (Neq64 x y) for { if v_0.Op != OpEq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq64) v.AddArg2(x, y) return true } // match: (Not (Eq32 x y)) // result: (Neq32 x y) for { if v_0.Op != OpEq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq32) v.AddArg2(x, y) return true } // match: (Not (Eq16 x y)) // result: (Neq16 x y) for { if v_0.Op != OpEq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq16) v.AddArg2(x, y) return true } // match: (Not (Eq8 x y)) // result: (Neq8 x y) for { if v_0.Op != OpEq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq8) v.AddArg2(x, y) return true } // match: (Not (EqB x y)) // result: (NeqB x y) for { if v_0.Op != OpEqB { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeqB) v.AddArg2(x, y) return true } // match: (Not (EqPtr x y)) // result: (NeqPtr x y) for { if v_0.Op != OpEqPtr { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeqPtr) v.AddArg2(x, y) return true } // match: (Not (Eq64F x y)) // result: (Neq64F x y) for { if v_0.Op != OpEq64F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq64F) v.AddArg2(x, y) return true } // match: (Not (Eq32F x y)) // result: (Neq32F x y) for { if v_0.Op != OpEq32F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq32F) v.AddArg2(x, y) return true } // match: (Not (Neq64 x y)) // result: (Eq64 x y) for { if v_0.Op != OpNeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq64) v.AddArg2(x, y) return true } // match: (Not (Neq32 x y)) // result: (Eq32 x y) for { if v_0.Op != OpNeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq32) v.AddArg2(x, y) return true } // match: (Not (Neq16 x y)) // result: (Eq16 x y) for { if v_0.Op != OpNeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq16) v.AddArg2(x, y) return true } // match: (Not (Neq8 x y)) // result: (Eq8 x y) for { if v_0.Op != OpNeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq8) v.AddArg2(x, y) return true } // match: (Not (NeqB x y)) // result: (EqB x y) for { if v_0.Op != OpNeqB { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEqB) v.AddArg2(x, y) return true } // match: (Not (NeqPtr x y)) // result: (EqPtr x y) for { if v_0.Op != OpNeqPtr { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEqPtr) v.AddArg2(x, y) return true } // match: (Not (Neq64F x y)) // result: (Eq64F x y) for { if v_0.Op != OpNeq64F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq64F) v.AddArg2(x, y) return true } // match: (Not (Neq32F x y)) // result: (Eq32F x y) for { if v_0.Op != OpNeq32F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq32F) v.AddArg2(x, y) return true } // match: (Not (Less64 x y)) // result: (Leq64 y x) for { if v_0.Op != OpLess64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq64) v.AddArg2(y, x) return true } // match: (Not (Less32 x y)) // result: (Leq32 y x) for { if v_0.Op != OpLess32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq32) v.AddArg2(y, x) return true } // match: (Not (Less16 x y)) // result: (Leq16 y x) for { if v_0.Op != OpLess16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq16) v.AddArg2(y, x) return true } // match: (Not (Less8 x y)) // result: (Leq8 y x) for { if v_0.Op != OpLess8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq8) v.AddArg2(y, x) return true } // match: (Not (Less64U x y)) // result: (Leq64U y x) for { if v_0.Op != OpLess64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq64U) v.AddArg2(y, x) return true } // match: (Not (Less32U x y)) // result: (Leq32U y x) for { if v_0.Op != OpLess32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq32U) v.AddArg2(y, x) return true } // match: (Not (Less16U x y)) // result: (Leq16U y x) for { if v_0.Op != OpLess16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq16U) v.AddArg2(y, x) return true } // match: (Not (Less8U x y)) // result: (Leq8U y x) for { if v_0.Op != OpLess8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq8U) v.AddArg2(y, x) return true } // match: (Not (Leq64 x y)) // result: (Less64 y x) for { if v_0.Op != OpLeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess64) v.AddArg2(y, x) return true } // match: (Not (Leq32 x y)) // result: (Less32 y x) for { if v_0.Op != OpLeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess32) v.AddArg2(y, x) return true } // match: (Not (Leq16 x y)) // result: (Less16 y x) for { if v_0.Op != OpLeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess16) v.AddArg2(y, x) return true } // match: (Not (Leq8 x y)) // result: (Less8 y x) for { if v_0.Op != OpLeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess8) v.AddArg2(y, x) return true } // match: (Not (Leq64U x y)) // result: (Less64U y x) for { if v_0.Op != OpLeq64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess64U) v.AddArg2(y, x) return true } // match: (Not (Leq32U x y)) // result: (Less32U y x) for { if v_0.Op != OpLeq32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess32U) v.AddArg2(y, x) return true } // match: (Not (Leq16U x y)) // result: (Less16U y x) for { if v_0.Op != OpLeq16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess16U) v.AddArg2(y, x) return true } // match: (Not (Leq8U x y)) // result: (Less8U y x) for { if v_0.Op != OpLeq8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess8U) v.AddArg2(y, x) return true } return false } func rewriteValuegeneric_OpOffPtr(v *Value) bool { v_0 := v.Args[0] // match: (OffPtr (OffPtr p [y]) [x]) // result: (OffPtr p [x+y]) for { x := auxIntToInt64(v.AuxInt) if v_0.Op != OpOffPtr { break } y := auxIntToInt64(v_0.AuxInt) p := v_0.Args[0] v.reset(OpOffPtr) v.AuxInt = int64ToAuxInt(x + y) v.AddArg(p) return true } // match: (OffPtr p [0]) // cond: v.Type.Compare(p.Type) == types.CMPeq // result: p for { if auxIntToInt64(v.AuxInt) != 0 { break } p := v_0 if !(v.Type.Compare(p.Type) == types.CMPeq) { break } v.copyOf(p) return true } return false } func rewriteValuegeneric_OpOr16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Or16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c | d) return true } break } // match: (Or16 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or16 (Const16 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or16 (Const16 [-1]) _) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Or16 (Com16 x) x) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Or16 x (Or16 x y)) // result: (Or16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr16) v.AddArg2(x, y) return true } } break } // match: (Or16 (And16 x (Const16 [c2])) (Const16 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or16 (Const16 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst16 { continue } c2 := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 { continue } t := v_1.Type c1 := auxIntToInt16(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or16 (Or16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Or16 i (Or16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpOr16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or16 (Const16 [c]) (Or16 (Const16 [d]) x)) // result: (Or16 (Const16 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpOr16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpOr32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Or32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c | d) return true } break } // match: (Or32 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or32 (Const32 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or32 (Const32 [-1]) _) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Or32 (Com32 x) x) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Or32 x (Or32 x y)) // result: (Or32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr32) v.AddArg2(x, y) return true } } break } // match: (Or32 (And32 x (Const32 [c2])) (Const32 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or32 (Const32 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst32 { continue } c2 := auxIntToInt32(v_0_1.AuxInt) if v_1.Op != OpConst32 { continue } t := v_1.Type c1 := auxIntToInt32(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or32 (Or32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Or32 i (Or32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpOr32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or32 (Const32 [c]) (Or32 (Const32 [d]) x)) // result: (Or32 (Const32 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpOr32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpOr64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Or64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c | d) return true } break } // match: (Or64 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or64 (Const64 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or64 (Const64 [-1]) _) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Or64 (Com64 x) x) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Or64 x (Or64 x y)) // result: (Or64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr64) v.AddArg2(x, y) return true } } break } // match: (Or64 (And64 x (Const64 [c2])) (Const64 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or64 (Const64 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst64 { continue } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { continue } t := v_1.Type c1 := auxIntToInt64(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or64 (Or64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Or64 i (Or64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpOr64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or64 (Const64 [c]) (Or64 (Const64 [d]) x)) // result: (Or64 (Const64 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpOr64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpOr8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Or8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c | d) return true } break } // match: (Or8 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or8 (Const8 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or8 (Const8 [-1]) _) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Or8 (Com8 x) x) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Or8 x (Or8 x y)) // result: (Or8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr8) v.AddArg2(x, y) return true } } break } // match: (Or8 (And8 x (Const8 [c2])) (Const8 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or8 (Const8 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst8 { continue } c2 := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 { continue } t := v_1.Type c1 := auxIntToInt8(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or8 (Or8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Or8 i (Or8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpOr8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or8 (Const8 [c]) (Or8 (Const8 [d]) x)) // result: (Or8 (Const8 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpOr8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpOrB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (OrB (Less64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: c >= d // result: (Less64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: c >= d // result: (Leq64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: c >= d // result: (Less32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: c >= d // result: (Leq32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: c >= d // result: (Less16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: c >= d // result: (Leq16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: c >= d // result: (Less8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: c >= d // result: (Leq8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d) // result: (Less64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d) // result: (Leq64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d) // result: (Less32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d) // result: (Leq32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d) // result: (Less16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d) // result: (Leq16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d) // result: (Less8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d) // result: (Leq8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d) // result: (Less64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d) // result: (Leq64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d) // result: (Less32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d) // result: (Leq32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d) // result: (Less16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d) // result: (Leq16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d) // result: (Less8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d) // result: (Leq8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } return false } func rewriteValuegeneric_OpPhi(v *Value) bool { // match: (Phi (Const8 [c]) (Const8 [c])) // result: (Const8 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != c { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c) return true } // match: (Phi (Const16 [c]) (Const16 [c])) // result: (Const16 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != c { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c) return true } // match: (Phi (Const32 [c]) (Const32 [c])) // result: (Const32 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != c { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c) return true } // match: (Phi (Const64 [c]) (Const64 [c])) // result: (Const64 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != c { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValuegeneric_OpPtrIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (PtrIndex ptr idx) // cond: config.PtrSize == 4 && is32Bit(t.Elem().Size()) // result: (AddPtr ptr (Mul32 idx (Const32 [int32(t.Elem().Size())]))) for { t := v.Type ptr := v_0 idx := v_1 if !(config.PtrSize == 4 && is32Bit(t.Elem().Size())) { break } v.reset(OpAddPtr) v0 := b.NewValue0(v.Pos, OpMul32, typ.Int) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = int32ToAuxInt(int32(t.Elem().Size())) v0.AddArg2(idx, v1) v.AddArg2(ptr, v0) return true } // match: (PtrIndex ptr idx) // cond: config.PtrSize == 8 // result: (AddPtr ptr (Mul64 idx (Const64 [t.Elem().Size()]))) for { t := v.Type ptr := v_0 idx := v_1 if !(config.PtrSize == 8) { break } v.reset(OpAddPtr) v0 := b.NewValue0(v.Pos, OpMul64, typ.Int) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = int64ToAuxInt(t.Elem().Size()) v0.AddArg2(idx, v1) v.AddArg2(ptr, v0) return true } return false } func rewriteValuegeneric_OpRotateLeft16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (RotateLeft16 x (Const16 [c])) // cond: c%16 == 0 // result: x for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(c%16 == 0) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRotateLeft32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (RotateLeft32 x (Const32 [c])) // cond: c%32 == 0 // result: x for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(c%32 == 0) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRotateLeft64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (RotateLeft64 x (Const64 [c])) // cond: c%64 == 0 // result: x for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c%64 == 0) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRotateLeft8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (RotateLeft8 x (Const8 [c])) // cond: c%8 == 0 // result: x for { x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(c%8 == 0) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRound32F(v *Value) bool { v_0 := v.Args[0] // match: (Round32F x:(Const32F)) // result: x for { x := v_0 if x.Op != OpConst32F { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRound64F(v *Value) bool { v_0 := v.Args[0] // match: (Round64F x:(Const64F)) // result: x for { x := v_0 if x.Op != OpConst64F { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux16 x (Const16 [c])) // result: (Rsh16Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh16Ux16 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux32 x (Const32 [c])) // result: (Rsh16Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh16Ux32 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux64 (Const16 [c]) (Const64 [d])) // result: (Const16 [int16(uint16(c) >> uint64(d))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint16(c) >> uint64(d))) return true } // match: (Rsh16Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh16Ux64 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Rsh16Ux64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Rsh16Ux64 (Rsh16Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh16Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh16Ux64 (Rsh16x64 x _) (Const64 [15])) // result: (Rsh16Ux64 x (Const64 [15])) for { if v_0.Op != OpRsh16x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 15 { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(15) v.AddArg2(x, v0) return true } // match: (Rsh16Ux64 (Lsh16x64 (Rsh16Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh16Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh16Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } // match: (Rsh16Ux64 (Lsh16x64 x (Const64 [8])) (Const64 [8])) // result: (ZeroExt8to16 (Trunc16to8 x)) for { if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 8 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 8 { break } v.reset(OpZeroExt8to16) v0 := b.NewValue0(v.Pos, OpTrunc16to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux8 x (Const8 [c])) // result: (Rsh16Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh16Ux8 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x16 x (Const16 [c])) // result: (Rsh16x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh16x16 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x32 x (Const32 [c])) // result: (Rsh16x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh16x32 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x64 (Const16 [c]) (Const64 [d])) // result: (Const16 [c >> uint64(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c >> uint64(d)) return true } // match: (Rsh16x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh16x64 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Rsh16x64 (Rsh16x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh16x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh16x64 (Lsh16x64 x (Const64 [8])) (Const64 [8])) // result: (SignExt8to16 (Trunc16to8 x)) for { if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 8 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 8 { break } v.reset(OpSignExt8to16) v0 := b.NewValue0(v.Pos, OpTrunc16to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x8 x (Const8 [c])) // result: (Rsh16x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh16x8 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux16 x (Const16 [c])) // result: (Rsh32Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh32Ux16 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux32 x (Const32 [c])) // result: (Rsh32Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh32Ux32 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux64 (Const32 [c]) (Const64 [d])) // result: (Const32 [int32(uint32(c) >> uint64(d))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint32(c) >> uint64(d))) return true } // match: (Rsh32Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh32Ux64 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Rsh32Ux64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Rsh32Ux64 (Rsh32Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh32Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh32Ux64 (Rsh32x64 x _) (Const64 [31])) // result: (Rsh32Ux64 x (Const64 [31])) for { if v_0.Op != OpRsh32x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 31 { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(31) v.AddArg2(x, v0) return true } // match: (Rsh32Ux64 (Lsh32x64 (Rsh32Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh32Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } // match: (Rsh32Ux64 (Lsh32x64 x (Const64 [24])) (Const64 [24])) // result: (ZeroExt8to32 (Trunc32to8 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 24 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 24 { break } v.reset(OpZeroExt8to32) v0 := b.NewValue0(v.Pos, OpTrunc32to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh32Ux64 (Lsh32x64 x (Const64 [16])) (Const64 [16])) // result: (ZeroExt16to32 (Trunc32to16 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 16 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 16 { break } v.reset(OpZeroExt16to32) v0 := b.NewValue0(v.Pos, OpTrunc32to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux8 x (Const8 [c])) // result: (Rsh32Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh32Ux8 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x16 x (Const16 [c])) // result: (Rsh32x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh32x16 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x32 x (Const32 [c])) // result: (Rsh32x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh32x32 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x64 (Const32 [c]) (Const64 [d])) // result: (Const32 [c >> uint64(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c >> uint64(d)) return true } // match: (Rsh32x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh32x64 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Rsh32x64 (Rsh32x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh32x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh32x64 (Lsh32x64 x (Const64 [24])) (Const64 [24])) // result: (SignExt8to32 (Trunc32to8 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 24 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 24 { break } v.reset(OpSignExt8to32) v0 := b.NewValue0(v.Pos, OpTrunc32to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh32x64 (Lsh32x64 x (Const64 [16])) (Const64 [16])) // result: (SignExt16to32 (Trunc32to16 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 16 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 16 { break } v.reset(OpSignExt16to32) v0 := b.NewValue0(v.Pos, OpTrunc32to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x8 x (Const8 [c])) // result: (Rsh32x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh32x8 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux16 x (Const16 [c])) // result: (Rsh64Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh64Ux16 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux32 x (Const32 [c])) // result: (Rsh64Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh64Ux32 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux64 (Const64 [c]) (Const64 [d])) // result: (Const64 [int64(uint64(c) >> uint64(d))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) return true } // match: (Rsh64Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh64Ux64 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Rsh64Ux64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (Const64 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 64) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Rsh64Ux64 (Rsh64Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh64Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh64Ux64 (Rsh64x64 x _) (Const64 [63])) // result: (Rsh64Ux64 x (Const64 [63])) for { if v_0.Op != OpRsh64x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(63) v.AddArg2(x, v0) return true } // match: (Rsh64Ux64 (Lsh64x64 (Rsh64Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh64Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [56])) (Const64 [56])) // result: (ZeroExt8to64 (Trunc64to8 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 56 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 56 { break } v.reset(OpZeroExt8to64) v0 := b.NewValue0(v.Pos, OpTrunc64to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [48])) (Const64 [48])) // result: (ZeroExt16to64 (Trunc64to16 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 48 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 48 { break } v.reset(OpZeroExt16to64) v0 := b.NewValue0(v.Pos, OpTrunc64to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [32])) (Const64 [32])) // result: (ZeroExt32to64 (Trunc64to32 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 32 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 32 { break } v.reset(OpZeroExt32to64) v0 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux8 x (Const8 [c])) // result: (Rsh64Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh64Ux8 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x16 x (Const16 [c])) // result: (Rsh64x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh64x16 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x32 x (Const32 [c])) // result: (Rsh64x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh64x32 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c >> uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c >> uint64(d)) return true } // match: (Rsh64x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh64x64 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Rsh64x64 (Rsh64x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh64x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [56])) (Const64 [56])) // result: (SignExt8to64 (Trunc64to8 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 56 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 56 { break } v.reset(OpSignExt8to64) v0 := b.NewValue0(v.Pos, OpTrunc64to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [48])) (Const64 [48])) // result: (SignExt16to64 (Trunc64to16 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 48 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 48 { break } v.reset(OpSignExt16to64) v0 := b.NewValue0(v.Pos, OpTrunc64to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [32])) (Const64 [32])) // result: (SignExt32to64 (Trunc64to32 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 32 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 32 { break } v.reset(OpSignExt32to64) v0 := b.NewValue0(v.Pos, OpTrunc64to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x8 x (Const8 [c])) // result: (Rsh64x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh64x8 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux16 x (Const16 [c])) // result: (Rsh8Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh8Ux16 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux32 x (Const32 [c])) // result: (Rsh8Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh8Ux32 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux64 (Const8 [c]) (Const64 [d])) // result: (Const8 [int8(uint8(c) >> uint64(d))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(uint8(c) >> uint64(d))) return true } // match: (Rsh8Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh8Ux64 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Rsh8Ux64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Rsh8Ux64 (Rsh8Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh8Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh8Ux64 (Rsh8x64 x _) (Const64 [7] )) // result: (Rsh8Ux64 x (Const64 [7] )) for { if v_0.Op != OpRsh8x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 7 { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(7) v.AddArg2(x, v0) return true } // match: (Rsh8Ux64 (Lsh8x64 (Rsh8Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh8Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh8Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux8 x (Const8 [c])) // result: (Rsh8Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh8Ux8 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x16 x (Const16 [c])) // result: (Rsh8x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh8x16 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x32 x (Const32 [c])) // result: (Rsh8x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh8x32 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x64 (Const8 [c]) (Const64 [d])) // result: (Const8 [c >> uint64(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c >> uint64(d)) return true } // match: (Rsh8x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh8x64 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Rsh8x64 (Rsh8x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh8x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x8 x (Const8 [c])) // result: (Rsh8x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh8x8 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpSelect0(v *Value) bool { v_0 := v.Args[0] // match: (Select0 (Div128u (Const64 [0]) lo y)) // result: (Div64u lo y) for { if v_0.Op != OpDiv128u { break } y := v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { break } lo := v_0.Args[1] v.reset(OpDiv64u) v.AddArg2(lo, y) return true } // match: (Select0 (Mul32uover (Const32 [1]) x)) // result: x for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_0_1 v.copyOf(x) return true } break } // match: (Select0 (Mul64uover (Const64 [1]) x)) // result: x for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 1 { continue } x := v_0_1 v.copyOf(x) return true } break } // match: (Select0 (Mul64uover (Const64 [0]) x)) // result: (Const64 [0]) for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (Select0 (Mul32uover (Const32 [0]) x)) // result: (Const32 [0]) for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 0 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } return false } func rewriteValuegeneric_OpSelect1(v *Value) bool { v_0 := v.Args[0] // match: (Select1 (Div128u (Const64 [0]) lo y)) // result: (Mod64u lo y) for { if v_0.Op != OpDiv128u { break } y := v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { break } lo := v_0.Args[1] v.reset(OpMod64u) v.AddArg2(lo, y) return true } // match: (Select1 (Mul32uover (Const32 [1]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (Select1 (Mul64uover (Const64 [1]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 1 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (Select1 (Mul64uover (Const64 [0]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (Select1 (Mul32uover (Const32 [0]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 0 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } return false } func rewriteValuegeneric_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] (MakeResult x ___)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpMakeResult || len(v_0.Args) < 1 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (SelectN [1] (MakeResult x y ___)) // result: y for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpMakeResult || len(v_0.Args) < 2 { break } y := v_0.Args[1] v.copyOf(y) return true } // match: (SelectN [2] (MakeResult x y z ___)) // result: z for { if auxIntToInt64(v.AuxInt) != 2 || v_0.Op != OpMakeResult || len(v_0.Args) < 3 { break } z := v_0.Args[2] v.copyOf(z) return true } // match: (SelectN [0] call:(StaticCall {sym} s1:(Store _ (Const64 [sz]) s2:(Store _ src s3:(Store {t} _ dst mem))))) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call) // result: (Move {t.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpStore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpConst64 { break } sz := auxIntToInt64(s1_1.AuxInt) s2 := s1.Args[2] if s2.Op != OpStore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpStore { break } t := auxToType(s3.Aux) mem := s3.Args[2] dst := s3.Args[1] if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(t.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticCall {sym} s1:(Store _ (Const32 [sz]) s2:(Store _ src s3:(Store {t} _ dst mem))))) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call) // result: (Move {t.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpStore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpConst32 { break } sz := auxIntToInt32(s1_1.AuxInt) s2 := s1.Args[2] if s2.Op != OpStore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpStore { break } t := auxToType(s3.Aux) mem := s3.Args[2] dst := s3.Args[1] if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(t.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticCall {sym} dst src (Const64 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst64 { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticCall {sym} dst src (Const32 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst32 { break } sz := auxIntToInt32(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticLECall {sym} dst src (Const64 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst64 { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticLECall {sym} dst src (Const32 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst32 { break } sz := auxIntToInt32(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticLECall {sym} a x)) // cond: needRaceCleanup(sym, call) && clobber(call) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 2 { break } sym := auxToCall(call.Aux) x := call.Args[1] if !(needRaceCleanup(sym, call) && clobber(call)) { break } v.copyOf(x) return true } // match: (SelectN [0] call:(StaticLECall {sym} x)) // cond: needRaceCleanup(sym, call) && clobber(call) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) x := call.Args[0] if !(needRaceCleanup(sym, call) && clobber(call)) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt16to32(v *Value) bool { v_0 := v.Args[0] // match: (SignExt16to32 (Const16 [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } // match: (SignExt16to32 (Trunc32to16 x:(Rsh32x64 _ (Const64 [s])))) // cond: s >= 16 // result: x for { if v_0.Op != OpTrunc32to16 { break } x := v_0.Args[0] if x.Op != OpRsh32x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 16) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt16to64(v *Value) bool { v_0 := v.Args[0] // match: (SignExt16to64 (Const16 [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } // match: (SignExt16to64 (Trunc64to16 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 48 // result: x for { if v_0.Op != OpTrunc64to16 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 48) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt32to64(v *Value) bool { v_0 := v.Args[0] // match: (SignExt32to64 (Const32 [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } // match: (SignExt32to64 (Trunc64to32 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 32 // result: x for { if v_0.Op != OpTrunc64to32 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 32) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt8to16(v *Value) bool { v_0 := v.Args[0] // match: (SignExt8to16 (Const8 [c])) // result: (Const16 [int16(c)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(c)) return true } // match: (SignExt8to16 (Trunc16to8 x:(Rsh16x64 _ (Const64 [s])))) // cond: s >= 8 // result: x for { if v_0.Op != OpTrunc16to8 { break } x := v_0.Args[0] if x.Op != OpRsh16x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 8) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt8to32(v *Value) bool { v_0 := v.Args[0] // match: (SignExt8to32 (Const8 [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } // match: (SignExt8to32 (Trunc32to8 x:(Rsh32x64 _ (Const64 [s])))) // cond: s >= 24 // result: x for { if v_0.Op != OpTrunc32to8 { break } x := v_0.Args[0] if x.Op != OpRsh32x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 24) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt8to64(v *Value) bool { v_0 := v.Args[0] // match: (SignExt8to64 (Const8 [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } // match: (SignExt8to64 (Trunc64to8 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 56 // result: x for { if v_0.Op != OpTrunc64to8 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 56) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSliceCap(v *Value) bool { v_0 := v.Args[0] // match: (SliceCap (SliceMake _ _ (Const64 [c]))) // result: (Const64 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpConst64 { break } t := v_0_2.Type c := auxIntToInt64(v_0_2.AuxInt) v.reset(OpConst64) v.Type = t v.AuxInt = int64ToAuxInt(c) return true } // match: (SliceCap (SliceMake _ _ (Const32 [c]))) // result: (Const32 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpConst32 { break } t := v_0_2.Type c := auxIntToInt32(v_0_2.AuxInt) v.reset(OpConst32) v.Type = t v.AuxInt = int32ToAuxInt(c) return true } // match: (SliceCap (SliceMake _ _ (SliceCap x))) // result: (SliceCap x) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpSliceCap { break } x := v_0_2.Args[0] v.reset(OpSliceCap) v.AddArg(x) return true } // match: (SliceCap (SliceMake _ _ (SliceLen x))) // result: (SliceLen x) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpSliceLen { break } x := v_0_2.Args[0] v.reset(OpSliceLen) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSliceLen(v *Value) bool { v_0 := v.Args[0] // match: (SliceLen (SliceMake _ (Const64 [c]) _)) // result: (Const64 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type c := auxIntToInt64(v_0_1.AuxInt) v.reset(OpConst64) v.Type = t v.AuxInt = int64ToAuxInt(c) return true } // match: (SliceLen (SliceMake _ (Const32 [c]) _)) // result: (Const32 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type c := auxIntToInt32(v_0_1.AuxInt) v.reset(OpConst32) v.Type = t v.AuxInt = int32ToAuxInt(c) return true } // match: (SliceLen (SliceMake _ (SliceLen x) _)) // result: (SliceLen x) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpSliceLen { break } x := v_0_1.Args[0] v.reset(OpSliceLen) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSlicePtr(v *Value) bool { v_0 := v.Args[0] // match: (SlicePtr (SliceMake (SlicePtr x) _ _)) // result: (SlicePtr x) for { if v_0.Op != OpSliceMake { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpSlicePtr { break } x := v_0_0.Args[0] v.reset(OpSlicePtr) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSlicemask(v *Value) bool { v_0 := v.Args[0] // match: (Slicemask (Const32 [x])) // cond: x > 0 // result: (Const32 [-1]) for { if v_0.Op != OpConst32 { break } x := auxIntToInt32(v_0.AuxInt) if !(x > 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } // match: (Slicemask (Const32 [0])) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Slicemask (Const64 [x])) // cond: x > 0 // result: (Const64 [-1]) for { if v_0.Op != OpConst64 { break } x := auxIntToInt64(v_0.AuxInt) if !(x > 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } // match: (Slicemask (Const64 [0])) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpSqrt(v *Value) bool { v_0 := v.Args[0] // match: (Sqrt (Const64F [c])) // cond: !math.IsNaN(math.Sqrt(c)) // result: (Const64F [math.Sqrt(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if !(!math.IsNaN(math.Sqrt(c))) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(math.Sqrt(c)) return true } return false } func rewriteValuegeneric_OpStaticLECall(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [1]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) // result: (MakeResult (Eq8 (Load sptr mem) (Const8 [int8(read8(scon,0))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 1 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon)) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq8, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int8) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst8, typ.Int8) v2.AuxInt = int8ToAuxInt(int8(read8(scon, 0))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [2]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) // result: (MakeResult (Eq16 (Load sptr mem) (Const16 [int16(read16(scon,0,config.ctxt.Arch.ByteOrder))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 2 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config)) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq16, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int16) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst16, typ.Int16) v2.AuxInt = int16ToAuxInt(int16(read16(scon, 0, config.ctxt.Arch.ByteOrder))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [4]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) // result: (MakeResult (Eq32 (Load sptr mem) (Const32 [int32(read32(scon,0,config.ctxt.Arch.ByteOrder))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 4 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config)) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq32, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int32) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = int32ToAuxInt(int32(read32(scon, 0, config.ctxt.Arch.ByteOrder))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [8]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) && config.PtrSize == 8 // result: (MakeResult (Eq64 (Load sptr mem) (Const64 [int64(read64(scon,0,config.ctxt.Arch.ByteOrder))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 8 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) && config.PtrSize == 8) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq64, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int64) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst64, typ.Int64) v2.AuxInt = int64ToAuxInt(int64(read64(scon, 0, config.ctxt.Arch.ByteOrder))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } return false } func rewriteValuegeneric_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (Store {t1} p1 (Load p2 mem) mem) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type mem := v_1.Args[1] p2 := v_1.Args[0] if mem != v_2 || !(isSamePtr(p1, p2) && t2.Size() == t1.Size()) { break } v.copyOf(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ oldmem)) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v_2 if mem.Op != OpStore { break } t3 := auxToType(mem.Aux) _ = mem.Args[2] p3 := mem.Args[0] if oldmem != mem.Args[2] || !(isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ (Store {t4} p4 _ oldmem))) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size()) // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v_2 if mem.Op != OpStore { break } t3 := auxToType(mem.Aux) _ = mem.Args[2] p3 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t4 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p4 := mem_2.Args[0] if oldmem != mem_2.Args[2] || !(isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 _ oldmem)))) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size()) && disjoint(p1, t1.Size(), p5, t5.Size()) // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v_2 if mem.Op != OpStore { break } t3 := auxToType(mem.Aux) _ = mem.Args[2] p3 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t4 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p4 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t5 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] p5 := mem_2_2.Args[0] if oldmem != mem_2_2.Args[2] || !(isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size()) && disjoint(p1, t1.Size(), p5, t5.Size())) { break } v.copyOf(mem) return true } // match: (Store {t} (OffPtr [o] p1) x mem:(Zero [n] p2 _)) // cond: isConstZero(x) && o >= 0 && t.Size() + o <= n && isSamePtr(p1, p2) // result: mem for { t := auxToType(v.Aux) if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] x := v_1 mem := v_2 if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p2 := mem.Args[0] if !(isConstZero(x) && o >= 0 && t.Size()+o <= n && isSamePtr(p1, p2)) { break } v.copyOf(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Zero [n] p3 _))) // cond: isConstZero(x) && o1 >= 0 && t1.Size() + o1 <= n && isSamePtr(p1, p3) && disjoint(op, t1.Size(), p2, t2.Size()) // result: mem for { t1 := auxToType(v.Aux) op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] x := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpZero { break } n := auxIntToInt64(mem_2.AuxInt) p3 := mem_2.Args[0] if !(isConstZero(x) && o1 >= 0 && t1.Size()+o1 <= n && isSamePtr(p1, p3) && disjoint(op, t1.Size(), p2, t2.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Store {t3} p3 _ (Zero [n] p4 _)))) // cond: isConstZero(x) && o1 >= 0 && t1.Size() + o1 <= n && isSamePtr(p1, p4) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) // result: mem for { t1 := auxToType(v.Aux) op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] x := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p3 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpZero { break } n := auxIntToInt64(mem_2_2.AuxInt) p4 := mem_2_2.Args[0] if !(isConstZero(x) && o1 >= 0 && t1.Size()+o1 <= n && isSamePtr(p1, p4) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Zero [n] p5 _))))) // cond: isConstZero(x) && o1 >= 0 && t1.Size() + o1 <= n && isSamePtr(p1, p5) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) // result: mem for { t1 := auxToType(v.Aux) op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] x := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p3 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] p4 := mem_2_2.Args[0] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpZero { break } n := auxIntToInt64(mem_2_2_2.AuxInt) p5 := mem_2_2_2.Args[0] if !(isConstZero(x) && o1 >= 0 && t1.Size()+o1 <= n && isSamePtr(p1, p5) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size())) { break } v.copyOf(mem) return true } // match: (Store _ (StructMake0) mem) // result: mem for { if v_1.Op != OpStructMake0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Store dst (StructMake1 f0) mem) // result: (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem) for { dst := v_0 if v_1.Op != OpStructMake1 { break } t := v_1.Type f0 := v_1.Args[0] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(0)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v0.AuxInt = int64ToAuxInt(0) v0.AddArg(dst) v.AddArg3(v0, f0, mem) return true } // match: (Store dst (StructMake2 f0 f1) mem) // result: (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem)) for { dst := v_0 if v_1.Op != OpStructMake2 { break } t := v_1.Type f1 := v_1.Args[1] f0 := v_1.Args[0] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(1)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v0.AuxInt = int64ToAuxInt(t.FieldOff(1)) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t.FieldType(0)) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v2.AuxInt = int64ToAuxInt(0) v2.AddArg(dst) v1.AddArg3(v2, f0, mem) v.AddArg3(v0, f1, v1) return true } // match: (Store dst (StructMake3 f0 f1 f2) mem) // result: (Store {t.FieldType(2)} (OffPtr [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem))) for { dst := v_0 if v_1.Op != OpStructMake3 { break } t := v_1.Type f2 := v_1.Args[2] f0 := v_1.Args[0] f1 := v_1.Args[1] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(2)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v0.AuxInt = int64ToAuxInt(t.FieldOff(2)) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t.FieldType(1)) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v2.AuxInt = int64ToAuxInt(t.FieldOff(1)) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t.FieldType(0)) v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v4.AuxInt = int64ToAuxInt(0) v4.AddArg(dst) v3.AddArg3(v4, f0, mem) v1.AddArg3(v2, f1, v3) v.AddArg3(v0, f2, v1) return true } // match: (Store dst (StructMake4 f0 f1 f2 f3) mem) // result: (Store {t.FieldType(3)} (OffPtr [t.FieldOff(3)] dst) f3 (Store {t.FieldType(2)} (OffPtr [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem)))) for { dst := v_0 if v_1.Op != OpStructMake4 { break } t := v_1.Type f3 := v_1.Args[3] f0 := v_1.Args[0] f1 := v_1.Args[1] f2 := v_1.Args[2] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(3)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo()) v0.AuxInt = int64ToAuxInt(t.FieldOff(3)) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t.FieldType(2)) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v2.AuxInt = int64ToAuxInt(t.FieldOff(2)) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t.FieldType(1)) v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v4.AuxInt = int64ToAuxInt(t.FieldOff(1)) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t.FieldType(0)) v6 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v6.AuxInt = int64ToAuxInt(0) v6.AddArg(dst) v5.AddArg3(v6, f0, mem) v3.AddArg3(v4, f1, v5) v1.AddArg3(v2, f2, v3) v.AddArg3(v0, f3, v1) return true } // match: (Store {t} dst (Load src mem) mem) // cond: !fe.CanSSA(t) // result: (Move {t} [t.Size()] dst src mem) for { t := auxToType(v.Aux) dst := v_0 if v_1.Op != OpLoad { break } mem := v_1.Args[1] src := v_1.Args[0] if mem != v_2 || !(!fe.CanSSA(t)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(t.Size()) v.Aux = typeToAux(t) v.AddArg3(dst, src, mem) return true } // match: (Store {t} dst (Load src mem) (VarDef {x} mem)) // cond: !fe.CanSSA(t) // result: (Move {t} [t.Size()] dst src (VarDef {x} mem)) for { t := auxToType(v.Aux) dst := v_0 if v_1.Op != OpLoad { break } mem := v_1.Args[1] src := v_1.Args[0] if v_2.Op != OpVarDef { break } x := auxToSym(v_2.Aux) if mem != v_2.Args[0] || !(!fe.CanSSA(t)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(t.Size()) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg3(dst, src, v0) return true } // match: (Store _ (ArrayMake0) mem) // result: mem for { if v_1.Op != OpArrayMake0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Store dst (ArrayMake1 e) mem) // result: (Store {e.Type} dst e mem) for { dst := v_0 if v_1.Op != OpArrayMake1 { break } e := v_1.Args[0] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(e.Type) v.AddArg3(dst, e, mem) return true } // match: (Store (SelectN [0] call:(StaticLECall _ _)) x mem:(SelectN [1] call)) // cond: isConstZero(x) && isSameCall(call.Aux, "runtime.newobject") // result: mem for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { break } call := v_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 { break } x := v_1 mem := v_2 if mem.Op != OpSelectN || auxIntToInt64(mem.AuxInt) != 1 || call != mem.Args[0] || !(isConstZero(x) && isSameCall(call.Aux, "runtime.newobject")) { break } v.copyOf(mem) return true } // match: (Store (OffPtr (SelectN [0] call:(StaticLECall _ _))) x mem:(SelectN [1] call)) // cond: isConstZero(x) && isSameCall(call.Aux, "runtime.newobject") // result: mem for { if v_0.Op != OpOffPtr { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpSelectN || auxIntToInt64(v_0_0.AuxInt) != 0 { break } call := v_0_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 { break } x := v_1 mem := v_2 if mem.Op != OpSelectN || auxIntToInt64(mem.AuxInt) != 1 || call != mem.Args[0] || !(isConstZero(x) && isSameCall(call.Aux, "runtime.newobject")) { break } v.copyOf(mem) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [0] p2) d2 m3:(Move [n] p3 _ mem))) // cond: m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 mem)) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr || auxIntToInt64(op2.AuxInt) != 0 { break } p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpMove { break } n := auxIntToInt64(m3.AuxInt) mem := m3.Args[2] p3 := m3.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v0.AddArg3(op2, d2, mem) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Move [n] p4 _ mem)))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 mem))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr || auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpMove { break } n := auxIntToInt64(m4.AuxInt) mem := m4.Args[2] p4 := m4.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v1.AddArg3(op3, d3, mem) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Move [n] p5 _ mem))))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size() + t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 (Store {t4} op4 d4 mem)))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpStore { break } t4 := auxToType(m4.Aux) _ = m4.Args[2] op4 := m4.Args[0] if op4.Op != OpOffPtr || auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] d4 := m4.Args[1] m5 := m4.Args[2] if m5.Op != OpMove { break } n := auxIntToInt64(m5.AuxInt) mem := m5.Args[2] p5 := m5.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size()+t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v2.Aux = typeToAux(t4) v2.AddArg3(op4, d4, mem) v1.AddArg3(op3, d3, v2) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [0] p2) d2 m3:(Zero [n] p3 mem))) // cond: m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 mem)) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr || auxIntToInt64(op2.AuxInt) != 0 { break } p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpZero { break } n := auxIntToInt64(m3.AuxInt) mem := m3.Args[1] p3 := m3.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v0.AddArg3(op2, d2, mem) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Zero [n] p4 mem)))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 mem))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr || auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpZero { break } n := auxIntToInt64(m4.AuxInt) mem := m4.Args[1] p4 := m4.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v1.AddArg3(op3, d3, mem) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Zero [n] p5 mem))))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size() + t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 (Store {t4} op4 d4 mem)))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpStore { break } t4 := auxToType(m4.Aux) _ = m4.Args[2] op4 := m4.Args[0] if op4.Op != OpOffPtr || auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] d4 := m4.Args[1] m5 := m4.Args[2] if m5.Op != OpZero { break } n := auxIntToInt64(m5.AuxInt) mem := m5.Args[1] p5 := m5.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size()+t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v2.Aux = typeToAux(t4) v2.AddArg3(op4, d4, mem) v1.AddArg3(op3, d3, v2) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } return false } func rewriteValuegeneric_OpStringLen(v *Value) bool { v_0 := v.Args[0] // match: (StringLen (StringMake _ (Const64 [c]))) // result: (Const64 [c]) for { if v_0.Op != OpStringMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type c := auxIntToInt64(v_0_1.AuxInt) v.reset(OpConst64) v.Type = t v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValuegeneric_OpStringPtr(v *Value) bool { v_0 := v.Args[0] // match: (StringPtr (StringMake (Addr {s} base) _)) // result: (Addr {s} base) for { if v_0.Op != OpStringMake { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { break } t := v_0_0.Type s := auxToSym(v_0_0.Aux) base := v_0_0.Args[0] v.reset(OpAddr) v.Type = t v.Aux = symToAux(s) v.AddArg(base) return true } return false } func rewriteValuegeneric_OpStructSelect(v *Value) bool { v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (StructSelect (StructMake1 x)) // result: x for { if v_0.Op != OpStructMake1 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [0] (StructMake2 x _)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpStructMake2 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [1] (StructMake2 _ x)) // result: x for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStructMake2 { break } x := v_0.Args[1] v.copyOf(x) return true } // match: (StructSelect [0] (StructMake3 x _ _)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpStructMake3 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [1] (StructMake3 _ x _)) // result: x for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStructMake3 { break } x := v_0.Args[1] v.copyOf(x) return true } // match: (StructSelect [2] (StructMake3 _ _ x)) // result: x for { if auxIntToInt64(v.AuxInt) != 2 || v_0.Op != OpStructMake3 { break } x := v_0.Args[2] v.copyOf(x) return true } // match: (StructSelect [0] (StructMake4 x _ _ _)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpStructMake4 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [1] (StructMake4 _ x _ _)) // result: x for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStructMake4 { break } x := v_0.Args[1] v.copyOf(x) return true } // match: (StructSelect [2] (StructMake4 _ _ x _)) // result: x for { if auxIntToInt64(v.AuxInt) != 2 || v_0.Op != OpStructMake4 { break } x := v_0.Args[2] v.copyOf(x) return true } // match: (StructSelect [3] (StructMake4 _ _ _ x)) // result: x for { if auxIntToInt64(v.AuxInt) != 3 || v_0.Op != OpStructMake4 { break } x := v_0.Args[3] v.copyOf(x) return true } // match: (StructSelect [i] x:(Load ptr mem)) // cond: !fe.CanSSA(t) // result: @x.Block (Load (OffPtr [t.FieldOff(int(i))] ptr) mem) for { i := auxIntToInt64(v.AuxInt) x := v_0 if x.Op != OpLoad { break } t := x.Type mem := x.Args[1] ptr := x.Args[0] if !(!fe.CanSSA(t)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpLoad, v.Type) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, v.Type.PtrTo()) v1.AuxInt = int64ToAuxInt(t.FieldOff(int(i))) v1.AddArg(ptr) v0.AddArg2(v1, mem) return true } // match: (StructSelect [0] (IData x)) // result: (IData x) for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpIData { break } x := v_0.Args[0] v.reset(OpIData) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c-d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c - d) return true } // match: (Sub16 x (Const16 [c])) // cond: x.Op != OpConst16 // result: (Add16 (Const16 [-c]) x) for { x := v_0 if v_1.Op != OpConst16 { break } t := v_1.Type c := auxIntToInt16(v_1.AuxInt) if !(x.Op != OpConst16) { break } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub16 (Mul16 x y) (Mul16 x z)) // result: (Mul16 x (Sub16 y z)) for { t := v.Type if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub16 x x) // result: (Const16 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Sub16 (Neg16 x) (Com16 x)) // result: (Const16 [1]) for { if v_0.Op != OpNeg16 { break } x := v_0.Args[0] if v_1.Op != OpCom16 || x != v_1.Args[0] { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(1) return true } // match: (Sub16 (Com16 x) (Neg16 x)) // result: (Const16 [-1]) for { if v_0.Op != OpCom16 { break } x := v_0.Args[0] if v_1.Op != OpNeg16 || x != v_1.Args[0] { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } // match: (Sub16 (Add16 x y) x) // result: y for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub16 (Add16 x y) y) // result: x for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub16 (Sub16 x y) x) // result: (Neg16 y) for { if v_0.Op != OpSub16 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg16) v.AddArg(y) return true } // match: (Sub16 x (Add16 x y)) // result: (Neg16 y) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg16) v.AddArg(y) return true } break } // match: (Sub16 x (Sub16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { x := v_0 if v_1.Op != OpSub16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub16 x (Add16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Sub16 x z) i) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst16 { continue } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub16 (Sub16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 i (Add16 z x)) for { if v_0.Op != OpSub16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub16 (Add16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 z x)) for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst16 { continue } t := i.Type x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub16 (Const16 [c]) (Sub16 (Const16 [d]) x)) // result: (Add16 (Const16 [c-d]) x) for { if v_0.Op != OpConst16 { break } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpSub16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 || v_1_0.Type != t { break } d := auxIntToInt16(v_1_0.AuxInt) v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Sub16 (Const16 [c-d]) x) for { if v_0.Op != OpConst16 { break } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpSub32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c-d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c - d) return true } // match: (Sub32 x (Const32 [c])) // cond: x.Op != OpConst32 // result: (Add32 (Const32 [-c]) x) for { x := v_0 if v_1.Op != OpConst32 { break } t := v_1.Type c := auxIntToInt32(v_1.AuxInt) if !(x.Op != OpConst32) { break } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub32 (Mul32 x y) (Mul32 x z)) // result: (Mul32 x (Sub32 y z)) for { t := v.Type if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub32 x x) // result: (Const32 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Sub32 (Neg32 x) (Com32 x)) // result: (Const32 [1]) for { if v_0.Op != OpNeg32 { break } x := v_0.Args[0] if v_1.Op != OpCom32 || x != v_1.Args[0] { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(1) return true } // match: (Sub32 (Com32 x) (Neg32 x)) // result: (Const32 [-1]) for { if v_0.Op != OpCom32 { break } x := v_0.Args[0] if v_1.Op != OpNeg32 || x != v_1.Args[0] { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } // match: (Sub32 (Add32 x y) x) // result: y for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub32 (Add32 x y) y) // result: x for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub32 (Sub32 x y) x) // result: (Neg32 y) for { if v_0.Op != OpSub32 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg32) v.AddArg(y) return true } // match: (Sub32 x (Add32 x y)) // result: (Neg32 y) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg32) v.AddArg(y) return true } break } // match: (Sub32 x (Sub32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { x := v_0 if v_1.Op != OpSub32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub32 x (Add32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Sub32 x z) i) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst32 { continue } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub32 (Sub32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 i (Add32 z x)) for { if v_0.Op != OpSub32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub32 (Add32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 z x)) for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst32 { continue } t := i.Type x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub32 (Const32 [c]) (Sub32 (Const32 [d]) x)) // result: (Add32 (Const32 [c-d]) x) for { if v_0.Op != OpConst32 { break } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpSub32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 || v_1_0.Type != t { break } d := auxIntToInt32(v_1_0.AuxInt) v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Sub32 (Const32 [c-d]) x) for { if v_0.Op != OpConst32 { break } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpSub32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Sub32F (Const32F [c]) (Const32F [d])) // cond: c-d == c-d // result: (Const32F [c-d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) if !(c-d == c-d) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c - d) return true } return false } func rewriteValuegeneric_OpSub64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c-d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c - d) return true } // match: (Sub64 x (Const64 [c])) // cond: x.Op != OpConst64 // result: (Add64 (Const64 [-c]) x) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(x.Op != OpConst64) { break } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub64 (Mul64 x y) (Mul64 x z)) // result: (Mul64 x (Sub64 y z)) for { t := v.Type if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub64 x x) // result: (Const64 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Sub64 (Neg64 x) (Com64 x)) // result: (Const64 [1]) for { if v_0.Op != OpNeg64 { break } x := v_0.Args[0] if v_1.Op != OpCom64 || x != v_1.Args[0] { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(1) return true } // match: (Sub64 (Com64 x) (Neg64 x)) // result: (Const64 [-1]) for { if v_0.Op != OpCom64 { break } x := v_0.Args[0] if v_1.Op != OpNeg64 || x != v_1.Args[0] { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } // match: (Sub64 (Add64 x y) x) // result: y for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub64 (Add64 x y) y) // result: x for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub64 (Sub64 x y) x) // result: (Neg64 y) for { if v_0.Op != OpSub64 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg64) v.AddArg(y) return true } // match: (Sub64 x (Add64 x y)) // result: (Neg64 y) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg64) v.AddArg(y) return true } break } // match: (Sub64 x (Sub64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { x := v_0 if v_1.Op != OpSub64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub64 x (Add64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Sub64 x z) i) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst64 { continue } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub64 (Sub64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 i (Add64 z x)) for { if v_0.Op != OpSub64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub64 (Add64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 z x)) for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst64 { continue } t := i.Type x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub64 (Const64 [c]) (Sub64 (Const64 [d]) x)) // result: (Add64 (Const64 [c-d]) x) for { if v_0.Op != OpConst64 { break } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpSub64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 || v_1_0.Type != t { break } d := auxIntToInt64(v_1_0.AuxInt) v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Sub64 (Const64 [c-d]) x) for { if v_0.Op != OpConst64 { break } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpSub64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Sub64F (Const64F [c]) (Const64F [d])) // cond: c-d == c-d // result: (Const64F [c-d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) if !(c-d == c-d) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c - d) return true } return false } func rewriteValuegeneric_OpSub8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c-d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c - d) return true } // match: (Sub8 x (Const8 [c])) // cond: x.Op != OpConst8 // result: (Add8 (Const8 [-c]) x) for { x := v_0 if v_1.Op != OpConst8 { break } t := v_1.Type c := auxIntToInt8(v_1.AuxInt) if !(x.Op != OpConst8) { break } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub8 (Mul8 x y) (Mul8 x z)) // result: (Mul8 x (Sub8 y z)) for { t := v.Type if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub8 x x) // result: (Const8 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Sub8 (Neg8 x) (Com8 x)) // result: (Const8 [1]) for { if v_0.Op != OpNeg8 { break } x := v_0.Args[0] if v_1.Op != OpCom8 || x != v_1.Args[0] { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(1) return true } // match: (Sub8 (Com8 x) (Neg8 x)) // result: (Const8 [-1]) for { if v_0.Op != OpCom8 { break } x := v_0.Args[0] if v_1.Op != OpNeg8 || x != v_1.Args[0] { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } // match: (Sub8 (Add8 x y) x) // result: y for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub8 (Add8 x y) y) // result: x for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub8 (Sub8 x y) x) // result: (Neg8 y) for { if v_0.Op != OpSub8 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg8) v.AddArg(y) return true } // match: (Sub8 x (Add8 x y)) // result: (Neg8 y) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg8) v.AddArg(y) return true } break } // match: (Sub8 x (Sub8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { x := v_0 if v_1.Op != OpSub8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub8 x (Add8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Sub8 x z) i) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst8 { continue } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub8 (Sub8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 i (Add8 z x)) for { if v_0.Op != OpSub8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub8 (Add8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 z x)) for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst8 { continue } t := i.Type x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub8 (Const8 [c]) (Sub8 (Const8 [d]) x)) // result: (Add8 (Const8 [c-d]) x) for { if v_0.Op != OpConst8 { break } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpSub8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 || v_1_0.Type != t { break } d := auxIntToInt8(v_1_0.AuxInt) v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Sub8 (Const8 [c-d]) x) for { if v_0.Op != OpConst8 { break } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpTrunc16to8(v *Value) bool { v_0 := v.Args[0] // match: (Trunc16to8 (Const16 [c])) // result: (Const8 [int8(c)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(c)) return true } // match: (Trunc16to8 (ZeroExt8to16 x)) // result: x for { if v_0.Op != OpZeroExt8to16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc16to8 (SignExt8to16 x)) // result: x for { if v_0.Op != OpSignExt8to16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc16to8 (And16 (Const16 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc16to8 x) for { if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst16 { continue } y := auxIntToInt16(v_0_0.AuxInt) x := v_0_1 if !(y&0xFF == 0xFF) { continue } v.reset(OpTrunc16to8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc32to16(v *Value) bool { v_0 := v.Args[0] // match: (Trunc32to16 (Const32 [c])) // result: (Const16 [int16(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(c)) return true } // match: (Trunc32to16 (ZeroExt8to32 x)) // result: (ZeroExt8to16 x) for { if v_0.Op != OpZeroExt8to32 { break } x := v_0.Args[0] v.reset(OpZeroExt8to16) v.AddArg(x) return true } // match: (Trunc32to16 (ZeroExt16to32 x)) // result: x for { if v_0.Op != OpZeroExt16to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to16 (SignExt8to32 x)) // result: (SignExt8to16 x) for { if v_0.Op != OpSignExt8to32 { break } x := v_0.Args[0] v.reset(OpSignExt8to16) v.AddArg(x) return true } // match: (Trunc32to16 (SignExt16to32 x)) // result: x for { if v_0.Op != OpSignExt16to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to16 (And32 (Const32 [y]) x)) // cond: y&0xFFFF == 0xFFFF // result: (Trunc32to16 x) for { if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 { continue } y := auxIntToInt32(v_0_0.AuxInt) x := v_0_1 if !(y&0xFFFF == 0xFFFF) { continue } v.reset(OpTrunc32to16) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc32to8(v *Value) bool { v_0 := v.Args[0] // match: (Trunc32to8 (Const32 [c])) // result: (Const8 [int8(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(c)) return true } // match: (Trunc32to8 (ZeroExt8to32 x)) // result: x for { if v_0.Op != OpZeroExt8to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to8 (SignExt8to32 x)) // result: x for { if v_0.Op != OpSignExt8to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to8 (And32 (Const32 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc32to8 x) for { if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 { continue } y := auxIntToInt32(v_0_0.AuxInt) x := v_0_1 if !(y&0xFF == 0xFF) { continue } v.reset(OpTrunc32to8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc64to16(v *Value) bool { v_0 := v.Args[0] // match: (Trunc64to16 (Const64 [c])) // result: (Const16 [int16(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(c)) return true } // match: (Trunc64to16 (ZeroExt8to64 x)) // result: (ZeroExt8to16 x) for { if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpZeroExt8to16) v.AddArg(x) return true } // match: (Trunc64to16 (ZeroExt16to64 x)) // result: x for { if v_0.Op != OpZeroExt16to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to16 (SignExt8to64 x)) // result: (SignExt8to16 x) for { if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpSignExt8to16) v.AddArg(x) return true } // match: (Trunc64to16 (SignExt16to64 x)) // result: x for { if v_0.Op != OpSignExt16to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to16 (And64 (Const64 [y]) x)) // cond: y&0xFFFF == 0xFFFF // result: (Trunc64to16 x) for { if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } y := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(y&0xFFFF == 0xFFFF) { continue } v.reset(OpTrunc64to16) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc64to32(v *Value) bool { v_0 := v.Args[0] // match: (Trunc64to32 (Const64 [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } // match: (Trunc64to32 (ZeroExt8to64 x)) // result: (ZeroExt8to32 x) for { if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpZeroExt8to32) v.AddArg(x) return true } // match: (Trunc64to32 (ZeroExt16to64 x)) // result: (ZeroExt16to32 x) for { if v_0.Op != OpZeroExt16to64 { break } x := v_0.Args[0] v.reset(OpZeroExt16to32) v.AddArg(x) return true } // match: (Trunc64to32 (ZeroExt32to64 x)) // result: x for { if v_0.Op != OpZeroExt32to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to32 (SignExt8to64 x)) // result: (SignExt8to32 x) for { if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpSignExt8to32) v.AddArg(x) return true } // match: (Trunc64to32 (SignExt16to64 x)) // result: (SignExt16to32 x) for { if v_0.Op != OpSignExt16to64 { break } x := v_0.Args[0] v.reset(OpSignExt16to32) v.AddArg(x) return true } // match: (Trunc64to32 (SignExt32to64 x)) // result: x for { if v_0.Op != OpSignExt32to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to32 (And64 (Const64 [y]) x)) // cond: y&0xFFFFFFFF == 0xFFFFFFFF // result: (Trunc64to32 x) for { if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } y := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(y&0xFFFFFFFF == 0xFFFFFFFF) { continue } v.reset(OpTrunc64to32) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc64to8(v *Value) bool { v_0 := v.Args[0] // match: (Trunc64to8 (Const64 [c])) // result: (Const8 [int8(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(c)) return true } // match: (Trunc64to8 (ZeroExt8to64 x)) // result: x for { if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to8 (SignExt8to64 x)) // result: x for { if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to8 (And64 (Const64 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc64to8 x) for { if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } y := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(y&0xFF == 0xFF) { continue } v.reset(OpTrunc64to8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpXor16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Xor16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c ^ d) return true } break } // match: (Xor16 x x) // result: (Const16 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Xor16 (Const16 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor16 (Com16 x) x) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Xor16 (Const16 [-1]) x) // result: (Com16 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom16) v.AddArg(x) return true } break } // match: (Xor16 x (Xor16 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor16 (Xor16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Xor16 i (Xor16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpXor16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor16 (Const16 [c]) (Xor16 (Const16 [d]) x)) // result: (Xor16 (Const16 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpXor16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpXor32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Xor32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c ^ d) return true } break } // match: (Xor32 x x) // result: (Const32 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Xor32 (Const32 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor32 (Com32 x) x) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Xor32 (Const32 [-1]) x) // result: (Com32 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom32) v.AddArg(x) return true } break } // match: (Xor32 x (Xor32 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor32 (Xor32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Xor32 i (Xor32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpXor32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor32 (Const32 [c]) (Xor32 (Const32 [d]) x)) // result: (Xor32 (Const32 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpXor32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpXor64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Xor64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c ^ d) return true } break } // match: (Xor64 x x) // result: (Const64 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Xor64 (Const64 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor64 (Com64 x) x) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Xor64 (Const64 [-1]) x) // result: (Com64 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom64) v.AddArg(x) return true } break } // match: (Xor64 x (Xor64 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor64 (Xor64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Xor64 i (Xor64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpXor64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor64 (Const64 [c]) (Xor64 (Const64 [d]) x)) // result: (Xor64 (Const64 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpXor64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpXor8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Xor8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c ^ d) return true } break } // match: (Xor8 x x) // result: (Const8 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Xor8 (Const8 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor8 (Com8 x) x) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Xor8 (Const8 [-1]) x) // result: (Com8 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom8) v.AddArg(x) return true } break } // match: (Xor8 x (Xor8 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor8 (Xor8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Xor8 i (Xor8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpXor8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor8 (Const8 [c]) (Xor8 (Const8 [d]) x)) // result: (Xor8 (Const8 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpXor8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Zero (SelectN [0] call:(StaticLECall _ _)) mem:(SelectN [1] call)) // cond: isSameCall(call.Aux, "runtime.newobject") // result: mem for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { break } call := v_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 { break } mem := v_1 if mem.Op != OpSelectN || auxIntToInt64(mem.AuxInt) != 1 || call != mem.Args[0] || !(isSameCall(call.Aux, "runtime.newobject")) { break } v.copyOf(mem) return true } // match: (Zero {t1} [n] p1 store:(Store {t2} (OffPtr [o2] p2) _ mem)) // cond: isSamePtr(p1, p2) && store.Uses == 1 && n >= o2 + t2.Size() && clobber(store) // result: (Zero {t1} [n] p1 mem) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) p1 := v_0 store := v_1 if store.Op != OpStore { break } t2 := auxToType(store.Aux) mem := store.Args[2] store_0 := store.Args[0] if store_0.Op != OpOffPtr { break } o2 := auxIntToInt64(store_0.AuxInt) p2 := store_0.Args[0] if !(isSamePtr(p1, p2) && store.Uses == 1 && n >= o2+t2.Size() && clobber(store)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t1) v.AddArg2(p1, mem) return true } // match: (Zero {t} [n] dst1 move:(Move {t} [n] dst2 _ mem)) // cond: move.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move) // result: (Zero {t} [n] dst1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 move := v_1 if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst1, mem) return true } // match: (Zero {t} [n] dst1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem))) // cond: move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move, vardef) // result: (Zero {t} [n] dst1 (VarDef {x} mem)) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 vardef := v_1 if vardef.Op != OpVarDef { break } x := auxToSym(vardef.Aux) move := vardef.Args[0] if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move, vardef)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg2(dst1, v0) return true } // match: (Zero {t} [s] dst1 zero:(Zero {t} [s] dst2 _)) // cond: isSamePtr(dst1, dst2) // result: zero for { s := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 zero := v_1 if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != s || auxToType(zero.Aux) != t { break } dst2 := zero.Args[0] if !(isSamePtr(dst1, dst2)) { break } v.copyOf(zero) return true } // match: (Zero {t} [s] dst1 vardef:(VarDef (Zero {t} [s] dst2 _))) // cond: isSamePtr(dst1, dst2) // result: vardef for { s := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 vardef := v_1 if vardef.Op != OpVarDef { break } vardef_0 := vardef.Args[0] if vardef_0.Op != OpZero || auxIntToInt64(vardef_0.AuxInt) != s || auxToType(vardef_0.Aux) != t { break } dst2 := vardef_0.Args[0] if !(isSamePtr(dst1, dst2)) { break } v.copyOf(vardef) return true } return false } func rewriteValuegeneric_OpZeroExt16to32(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt16to32 (Const16 [c])) // result: (Const32 [int32(uint16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint16(c))) return true } // match: (ZeroExt16to32 (Trunc32to16 x:(Rsh32Ux64 _ (Const64 [s])))) // cond: s >= 16 // result: x for { if v_0.Op != OpTrunc32to16 { break } x := v_0.Args[0] if x.Op != OpRsh32Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 16) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt16to64(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt16to64 (Const16 [c])) // result: (Const64 [int64(uint16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint16(c))) return true } // match: (ZeroExt16to64 (Trunc64to16 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 48 // result: x for { if v_0.Op != OpTrunc64to16 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 48) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt32to64(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt32to64 (Const32 [c])) // result: (Const64 [int64(uint32(c))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint32(c))) return true } // match: (ZeroExt32to64 (Trunc64to32 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 32 // result: x for { if v_0.Op != OpTrunc64to32 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 32) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to16(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt8to16 (Const8 [c])) // result: (Const16 [int16( uint8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint8(c))) return true } // match: (ZeroExt8to16 (Trunc16to8 x:(Rsh16Ux64 _ (Const64 [s])))) // cond: s >= 8 // result: x for { if v_0.Op != OpTrunc16to8 { break } x := v_0.Args[0] if x.Op != OpRsh16Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 8) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to32(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt8to32 (Const8 [c])) // result: (Const32 [int32( uint8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint8(c))) return true } // match: (ZeroExt8to32 (Trunc32to8 x:(Rsh32Ux64 _ (Const64 [s])))) // cond: s >= 24 // result: x for { if v_0.Op != OpTrunc32to8 { break } x := v_0.Args[0] if x.Op != OpRsh32Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 24) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to64(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt8to64 (Const8 [c])) // result: (Const64 [int64( uint8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint8(c))) return true } // match: (ZeroExt8to64 (Trunc64to8 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 56 // result: x for { if v_0.Op != OpTrunc64to8 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 56) { break } v.copyOf(x) return true } return false } func rewriteBlockgeneric(b *Block) bool { switch b.Kind { case BlockIf: // match: (If (Not cond) yes no) // result: (If cond no yes) for b.Controls[0].Op == OpNot { v_0 := b.Controls[0] cond := v_0.Args[0] b.resetWithControl(BlockIf, cond) b.swapSuccessors() return true } // match: (If (ConstBool [c]) yes no) // cond: c // result: (First yes no) for b.Controls[0].Op == OpConstBool { v_0 := b.Controls[0] c := auxIntToBool(v_0.AuxInt) if !(c) { break } b.Reset(BlockFirst) return true } // match: (If (ConstBool [c]) yes no) // cond: !c // result: (First no yes) for b.Controls[0].Op == OpConstBool { v_0 := b.Controls[0] c := auxIntToBool(v_0.AuxInt) if !(!c) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- y -- // Code generated from gen/generic.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/compile/internal/types" func rewriteValuegeneric(v *Value) bool { switch v.Op { case OpAdd16: return rewriteValuegeneric_OpAdd16(v) case OpAdd32: return rewriteValuegeneric_OpAdd32(v) case OpAdd32F: return rewriteValuegeneric_OpAdd32F(v) case OpAdd64: return rewriteValuegeneric_OpAdd64(v) case OpAdd64F: return rewriteValuegeneric_OpAdd64F(v) case OpAdd8: return rewriteValuegeneric_OpAdd8(v) case OpAddPtr: return rewriteValuegeneric_OpAddPtr(v) case OpAnd16: return rewriteValuegeneric_OpAnd16(v) case OpAnd32: return rewriteValuegeneric_OpAnd32(v) case OpAnd64: return rewriteValuegeneric_OpAnd64(v) case OpAnd8: return rewriteValuegeneric_OpAnd8(v) case OpAndB: return rewriteValuegeneric_OpAndB(v) case OpArraySelect: return rewriteValuegeneric_OpArraySelect(v) case OpCom16: return rewriteValuegeneric_OpCom16(v) case OpCom32: return rewriteValuegeneric_OpCom32(v) case OpCom64: return rewriteValuegeneric_OpCom64(v) case OpCom8: return rewriteValuegeneric_OpCom8(v) case OpConstInterface: return rewriteValuegeneric_OpConstInterface(v) case OpConstSlice: return rewriteValuegeneric_OpConstSlice(v) case OpConstString: return rewriteValuegeneric_OpConstString(v) case OpConvert: return rewriteValuegeneric_OpConvert(v) case OpCtz16: return rewriteValuegeneric_OpCtz16(v) case OpCtz32: return rewriteValuegeneric_OpCtz32(v) case OpCtz64: return rewriteValuegeneric_OpCtz64(v) case OpCtz8: return rewriteValuegeneric_OpCtz8(v) case OpCvt32Fto32: return rewriteValuegeneric_OpCvt32Fto32(v) case OpCvt32Fto64: return rewriteValuegeneric_OpCvt32Fto64(v) case OpCvt32Fto64F: return rewriteValuegeneric_OpCvt32Fto64F(v) case OpCvt32to32F: return rewriteValuegeneric_OpCvt32to32F(v) case OpCvt32to64F: return rewriteValuegeneric_OpCvt32to64F(v) case OpCvt64Fto32: return rewriteValuegeneric_OpCvt64Fto32(v) case OpCvt64Fto32F: return rewriteValuegeneric_OpCvt64Fto32F(v) case OpCvt64Fto64: return rewriteValuegeneric_OpCvt64Fto64(v) case OpCvt64to32F: return rewriteValuegeneric_OpCvt64to32F(v) case OpCvt64to64F: return rewriteValuegeneric_OpCvt64to64F(v) case OpCvtBoolToUint8: return rewriteValuegeneric_OpCvtBoolToUint8(v) case OpDiv16: return rewriteValuegeneric_OpDiv16(v) case OpDiv16u: return rewriteValuegeneric_OpDiv16u(v) case OpDiv32: return rewriteValuegeneric_OpDiv32(v) case OpDiv32F: return rewriteValuegeneric_OpDiv32F(v) case OpDiv32u: return rewriteValuegeneric_OpDiv32u(v) case OpDiv64: return rewriteValuegeneric_OpDiv64(v) case OpDiv64F: return rewriteValuegeneric_OpDiv64F(v) case OpDiv64u: return rewriteValuegeneric_OpDiv64u(v) case OpDiv8: return rewriteValuegeneric_OpDiv8(v) case OpDiv8u: return rewriteValuegeneric_OpDiv8u(v) case OpEq16: return rewriteValuegeneric_OpEq16(v) case OpEq32: return rewriteValuegeneric_OpEq32(v) case OpEq32F: return rewriteValuegeneric_OpEq32F(v) case OpEq64: return rewriteValuegeneric_OpEq64(v) case OpEq64F: return rewriteValuegeneric_OpEq64F(v) case OpEq8: return rewriteValuegeneric_OpEq8(v) case OpEqB: return rewriteValuegeneric_OpEqB(v) case OpEqInter: return rewriteValuegeneric_OpEqInter(v) case OpEqPtr: return rewriteValuegeneric_OpEqPtr(v) case OpEqSlice: return rewriteValuegeneric_OpEqSlice(v) case OpIMake: return rewriteValuegeneric_OpIMake(v) case OpInterLECall: return rewriteValuegeneric_OpInterLECall(v) case OpIsInBounds: return rewriteValuegeneric_OpIsInBounds(v) case OpIsNonNil: return rewriteValuegeneric_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValuegeneric_OpIsSliceInBounds(v) case OpLeq16: return rewriteValuegeneric_OpLeq16(v) case OpLeq16U: return rewriteValuegeneric_OpLeq16U(v) case OpLeq32: return rewriteValuegeneric_OpLeq32(v) case OpLeq32F: return rewriteValuegeneric_OpLeq32F(v) case OpLeq32U: return rewriteValuegeneric_OpLeq32U(v) case OpLeq64: return rewriteValuegeneric_OpLeq64(v) case OpLeq64F: return rewriteValuegeneric_OpLeq64F(v) case OpLeq64U: return rewriteValuegeneric_OpLeq64U(v) case OpLeq8: return rewriteValuegeneric_OpLeq8(v) case OpLeq8U: return rewriteValuegeneric_OpLeq8U(v) case OpLess16: return rewriteValuegeneric_OpLess16(v) case OpLess16U: return rewriteValuegeneric_OpLess16U(v) case OpLess32: return rewriteValuegeneric_OpLess32(v) case OpLess32F: return rewriteValuegeneric_OpLess32F(v) case OpLess32U: return rewriteValuegeneric_OpLess32U(v) case OpLess64: return rewriteValuegeneric_OpLess64(v) case OpLess64F: return rewriteValuegeneric_OpLess64F(v) case OpLess64U: return rewriteValuegeneric_OpLess64U(v) case OpLess8: return rewriteValuegeneric_OpLess8(v) case OpLess8U: return rewriteValuegeneric_OpLess8U(v) case OpLoad: return rewriteValuegeneric_OpLoad(v) case OpLsh16x16: return rewriteValuegeneric_OpLsh16x16(v) case OpLsh16x32: return rewriteValuegeneric_OpLsh16x32(v) case OpLsh16x64: return rewriteValuegeneric_OpLsh16x64(v) case OpLsh16x8: return rewriteValuegeneric_OpLsh16x8(v) case OpLsh32x16: return rewriteValuegeneric_OpLsh32x16(v) case OpLsh32x32: return rewriteValuegeneric_OpLsh32x32(v) case OpLsh32x64: return rewriteValuegeneric_OpLsh32x64(v) case OpLsh32x8: return rewriteValuegeneric_OpLsh32x8(v) case OpLsh64x16: return rewriteValuegeneric_OpLsh64x16(v) case OpLsh64x32: return rewriteValuegeneric_OpLsh64x32(v) case OpLsh64x64: return rewriteValuegeneric_OpLsh64x64(v) case OpLsh64x8: return rewriteValuegeneric_OpLsh64x8(v) case OpLsh8x16: return rewriteValuegeneric_OpLsh8x16(v) case OpLsh8x32: return rewriteValuegeneric_OpLsh8x32(v) case OpLsh8x64: return rewriteValuegeneric_OpLsh8x64(v) case OpLsh8x8: return rewriteValuegeneric_OpLsh8x8(v) case OpMod16: return rewriteValuegeneric_OpMod16(v) case OpMod16u: return rewriteValuegeneric_OpMod16u(v) case OpMod32: return rewriteValuegeneric_OpMod32(v) case OpMod32u: return rewriteValuegeneric_OpMod32u(v) case OpMod64: return rewriteValuegeneric_OpMod64(v) case OpMod64u: return rewriteValuegeneric_OpMod64u(v) case OpMod8: return rewriteValuegeneric_OpMod8(v) case OpMod8u: return rewriteValuegeneric_OpMod8u(v) case OpMove: return rewriteValuegeneric_OpMove(v) case OpMul16: return rewriteValuegeneric_OpMul16(v) case OpMul32: return rewriteValuegeneric_OpMul32(v) case OpMul32F: return rewriteValuegeneric_OpMul32F(v) case OpMul64: return rewriteValuegeneric_OpMul64(v) case OpMul64F: return rewriteValuegeneric_OpMul64F(v) case OpMul8: return rewriteValuegeneric_OpMul8(v) case OpNeg16: return rewriteValuegeneric_OpNeg16(v) case OpNeg32: return rewriteValuegeneric_OpNeg32(v) case OpNeg32F: return rewriteValuegeneric_OpNeg32F(v) case OpNeg64: return rewriteValuegeneric_OpNeg64(v) case OpNeg64F: return rewriteValuegeneric_OpNeg64F(v) case OpNeg8: return rewriteValuegeneric_OpNeg8(v) case OpNeq16: return rewriteValuegeneric_OpNeq16(v) case OpNeq32: return rewriteValuegeneric_OpNeq32(v) case OpNeq32F: return rewriteValuegeneric_OpNeq32F(v) case OpNeq64: return rewriteValuegeneric_OpNeq64(v) case OpNeq64F: return rewriteValuegeneric_OpNeq64F(v) case OpNeq8: return rewriteValuegeneric_OpNeq8(v) case OpNeqB: return rewriteValuegeneric_OpNeqB(v) case OpNeqInter: return rewriteValuegeneric_OpNeqInter(v) case OpNeqPtr: return rewriteValuegeneric_OpNeqPtr(v) case OpNeqSlice: return rewriteValuegeneric_OpNeqSlice(v) case OpNilCheck: return rewriteValuegeneric_OpNilCheck(v) case OpNot: return rewriteValuegeneric_OpNot(v) case OpOffPtr: return rewriteValuegeneric_OpOffPtr(v) case OpOr16: return rewriteValuegeneric_OpOr16(v) case OpOr32: return rewriteValuegeneric_OpOr32(v) case OpOr64: return rewriteValuegeneric_OpOr64(v) case OpOr8: return rewriteValuegeneric_OpOr8(v) case OpOrB: return rewriteValuegeneric_OpOrB(v) case OpPhi: return rewriteValuegeneric_OpPhi(v) case OpPtrIndex: return rewriteValuegeneric_OpPtrIndex(v) case OpRotateLeft16: return rewriteValuegeneric_OpRotateLeft16(v) case OpRotateLeft32: return rewriteValuegeneric_OpRotateLeft32(v) case OpRotateLeft64: return rewriteValuegeneric_OpRotateLeft64(v) case OpRotateLeft8: return rewriteValuegeneric_OpRotateLeft8(v) case OpRound32F: return rewriteValuegeneric_OpRound32F(v) case OpRound64F: return rewriteValuegeneric_OpRound64F(v) case OpRsh16Ux16: return rewriteValuegeneric_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValuegeneric_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValuegeneric_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValuegeneric_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValuegeneric_OpRsh16x16(v) case OpRsh16x32: return rewriteValuegeneric_OpRsh16x32(v) case OpRsh16x64: return rewriteValuegeneric_OpRsh16x64(v) case OpRsh16x8: return rewriteValuegeneric_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValuegeneric_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValuegeneric_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValuegeneric_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValuegeneric_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValuegeneric_OpRsh32x16(v) case OpRsh32x32: return rewriteValuegeneric_OpRsh32x32(v) case OpRsh32x64: return rewriteValuegeneric_OpRsh32x64(v) case OpRsh32x8: return rewriteValuegeneric_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValuegeneric_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValuegeneric_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValuegeneric_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValuegeneric_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValuegeneric_OpRsh64x16(v) case OpRsh64x32: return rewriteValuegeneric_OpRsh64x32(v) case OpRsh64x64: return rewriteValuegeneric_OpRsh64x64(v) case OpRsh64x8: return rewriteValuegeneric_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValuegeneric_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValuegeneric_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValuegeneric_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValuegeneric_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValuegeneric_OpRsh8x16(v) case OpRsh8x32: return rewriteValuegeneric_OpRsh8x32(v) case OpRsh8x64: return rewriteValuegeneric_OpRsh8x64(v) case OpRsh8x8: return rewriteValuegeneric_OpRsh8x8(v) case OpSelect0: return rewriteValuegeneric_OpSelect0(v) case OpSelect1: return rewriteValuegeneric_OpSelect1(v) case OpSelectN: return rewriteValuegeneric_OpSelectN(v) case OpSignExt16to32: return rewriteValuegeneric_OpSignExt16to32(v) case OpSignExt16to64: return rewriteValuegeneric_OpSignExt16to64(v) case OpSignExt32to64: return rewriteValuegeneric_OpSignExt32to64(v) case OpSignExt8to16: return rewriteValuegeneric_OpSignExt8to16(v) case OpSignExt8to32: return rewriteValuegeneric_OpSignExt8to32(v) case OpSignExt8to64: return rewriteValuegeneric_OpSignExt8to64(v) case OpSliceCap: return rewriteValuegeneric_OpSliceCap(v) case OpSliceLen: return rewriteValuegeneric_OpSliceLen(v) case OpSlicePtr: return rewriteValuegeneric_OpSlicePtr(v) case OpSlicemask: return rewriteValuegeneric_OpSlicemask(v) case OpSqrt: return rewriteValuegeneric_OpSqrt(v) case OpStaticLECall: return rewriteValuegeneric_OpStaticLECall(v) case OpStore: return rewriteValuegeneric_OpStore(v) case OpStringLen: return rewriteValuegeneric_OpStringLen(v) case OpStringPtr: return rewriteValuegeneric_OpStringPtr(v) case OpStructSelect: return rewriteValuegeneric_OpStructSelect(v) case OpSub16: return rewriteValuegeneric_OpSub16(v) case OpSub32: return rewriteValuegeneric_OpSub32(v) case OpSub32F: return rewriteValuegeneric_OpSub32F(v) case OpSub64: return rewriteValuegeneric_OpSub64(v) case OpSub64F: return rewriteValuegeneric_OpSub64F(v) case OpSub8: return rewriteValuegeneric_OpSub8(v) case OpTrunc16to8: return rewriteValuegeneric_OpTrunc16to8(v) case OpTrunc32to16: return rewriteValuegeneric_OpTrunc32to16(v) case OpTrunc32to8: return rewriteValuegeneric_OpTrunc32to8(v) case OpTrunc64to16: return rewriteValuegeneric_OpTrunc64to16(v) case OpTrunc64to32: return rewriteValuegeneric_OpTrunc64to32(v) case OpTrunc64to8: return rewriteValuegeneric_OpTrunc64to8(v) case OpXor16: return rewriteValuegeneric_OpXor16(v) case OpXor32: return rewriteValuegeneric_OpXor32(v) case OpXor64: return rewriteValuegeneric_OpXor64(v) case OpXor8: return rewriteValuegeneric_OpXor8(v) case OpZero: return rewriteValuegeneric_OpZero(v) case OpZeroExt16to32: return rewriteValuegeneric_OpZeroExt16to32(v) case OpZeroExt16to64: return rewriteValuegeneric_OpZeroExt16to64(v) case OpZeroExt32to64: return rewriteValuegeneric_OpZeroExt32to64(v) case OpZeroExt8to16: return rewriteValuegeneric_OpZeroExt8to16(v) case OpZeroExt8to32: return rewriteValuegeneric_OpZeroExt8to32(v) case OpZeroExt8to64: return rewriteValuegeneric_OpZeroExt8to64(v) } return false } func rewriteValuegeneric_OpAdd16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Add16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c + d) return true } break } // match: (Add16 (Mul16 x y) (Mul16 x z)) // result: (Mul16 x (Add16 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add16 (Const16 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add16 x (Neg16 y)) // result: (Sub16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg16 { continue } y := v_1.Args[0] v.reset(OpSub16) v.AddArg2(x, y) return true } break } // match: (Add16 (Com16 x) x) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Add16 (Const16 [1]) (Com16 x)) // result: (Neg16 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 1 || v_1.Op != OpCom16 { continue } x := v_1.Args[0] v.reset(OpNeg16) v.AddArg(x) return true } break } // match: (Add16 x (Sub16 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub16 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add16 x (Add16 y (Sub16 z x))) // result: (Add16 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub16 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd16) v.AddArg2(y, z) return true } } break } // match: (Add16 (Add16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Add16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add16 (Sub16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub16 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { continue } t := i.Type x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Add16 (Const16 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add16 (Const16 [c]) (Sub16 (Const16 [d]) x)) // result: (Sub16 (Const16 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpSub16 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } // match: (Add16 (Lsh16x64 x z:(Const64 [c])) (Rsh16Ux64 x (Const64 [d]))) // cond: c < 16 && d == 16-c && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh16x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh16Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 16 && d == 16-c && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Add16 left:(Lsh16x64 x y) right:(Rsh16Ux64 x (Sub64 (Const64 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Add16 left:(Lsh16x32 x y) right:(Rsh16Ux32 x (Sub32 (Const32 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Add16 left:(Lsh16x16 x y) right:(Rsh16Ux16 x (Sub16 (Const16 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Add16 left:(Lsh16x8 x y) right:(Rsh16Ux8 x (Sub8 (Const8 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Add16 right:(Rsh16Ux64 x y) left:(Lsh16x64 x z:(Sub64 (Const64 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Add16 right:(Rsh16Ux32 x y) left:(Lsh16x32 x z:(Sub32 (Const32 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Add16 right:(Rsh16Ux16 x y) left:(Lsh16x16 x z:(Sub16 (Const16 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Add16 right:(Rsh16Ux8 x y) left:(Lsh16x8 x z:(Sub8 (Const8 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpAdd32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Add32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c + d) return true } break } // match: (Add32 (Mul32 x y) (Mul32 x z)) // result: (Mul32 x (Add32 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add32 (Const32 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add32 x (Neg32 y)) // result: (Sub32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg32 { continue } y := v_1.Args[0] v.reset(OpSub32) v.AddArg2(x, y) return true } break } // match: (Add32 (Com32 x) x) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Add32 (Const32 [1]) (Com32 x)) // result: (Neg32 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 1 || v_1.Op != OpCom32 { continue } x := v_1.Args[0] v.reset(OpNeg32) v.AddArg(x) return true } break } // match: (Add32 x (Sub32 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub32 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add32 x (Add32 y (Sub32 z x))) // result: (Add32 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd32) v.AddArg2(y, z) return true } } break } // match: (Add32 (Add32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Add32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add32 (Sub32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub32 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { continue } t := i.Type x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Add32 (Const32 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add32 (Const32 [c]) (Sub32 (Const32 [d]) x)) // result: (Sub32 (Const32 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpSub32 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } // match: (Add32 (Lsh32x64 x z:(Const64 [c])) (Rsh32Ux64 x (Const64 [d]))) // cond: c < 32 && d == 32-c && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh32x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh32Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 32 && d == 32-c && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Add32 left:(Lsh32x64 x y) right:(Rsh32Ux64 x (Sub64 (Const64 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Add32 left:(Lsh32x32 x y) right:(Rsh32Ux32 x (Sub32 (Const32 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Add32 left:(Lsh32x16 x y) right:(Rsh32Ux16 x (Sub16 (Const16 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Add32 left:(Lsh32x8 x y) right:(Rsh32Ux8 x (Sub8 (Const8 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Add32 right:(Rsh32Ux64 x y) left:(Lsh32x64 x z:(Sub64 (Const64 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Add32 right:(Rsh32Ux32 x y) left:(Lsh32x32 x z:(Sub32 (Const32 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Add32 right:(Rsh32Ux16 x y) left:(Lsh32x16 x z:(Sub16 (Const16 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Add32 right:(Rsh32Ux8 x y) left:(Lsh32x8 x z:(Sub8 (Const8 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpAdd32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Add32F (Const32F [c]) (Const32F [d])) // cond: c+d == c+d // result: (Const32F [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) if !(c+d == c+d) { continue } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c + d) return true } break } return false } func rewriteValuegeneric_OpAdd64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Add64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c + d) return true } break } // match: (Add64 (Mul64 x y) (Mul64 x z)) // result: (Mul64 x (Add64 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add64 (Const64 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add64 x (Neg64 y)) // result: (Sub64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg64 { continue } y := v_1.Args[0] v.reset(OpSub64) v.AddArg2(x, y) return true } break } // match: (Add64 (Com64 x) x) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Add64 (Const64 [1]) (Com64 x)) // result: (Neg64 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 1 || v_1.Op != OpCom64 { continue } x := v_1.Args[0] v.reset(OpNeg64) v.AddArg(x) return true } break } // match: (Add64 x (Sub64 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub64 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add64 x (Add64 y (Sub64 z x))) // result: (Add64 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub64 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd64) v.AddArg2(y, z) return true } } break } // match: (Add64 (Add64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Add64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add64 (Sub64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub64 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { continue } t := i.Type x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Add64 (Const64 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add64 (Const64 [c]) (Sub64 (Const64 [d]) x)) // result: (Sub64 (Const64 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpSub64 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } // match: (Add64 (Lsh64x64 x z:(Const64 [c])) (Rsh64Ux64 x (Const64 [d]))) // cond: c < 64 && d == 64-c && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh64x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh64Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 64 && d == 64-c && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Add64 left:(Lsh64x64 x y) right:(Rsh64Ux64 x (Sub64 (Const64 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Add64 left:(Lsh64x32 x y) right:(Rsh64Ux32 x (Sub32 (Const32 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Add64 left:(Lsh64x16 x y) right:(Rsh64Ux16 x (Sub16 (Const16 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Add64 left:(Lsh64x8 x y) right:(Rsh64Ux8 x (Sub8 (Const8 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Add64 right:(Rsh64Ux64 x y) left:(Lsh64x64 x z:(Sub64 (Const64 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Add64 right:(Rsh64Ux32 x y) left:(Lsh64x32 x z:(Sub32 (Const32 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Add64 right:(Rsh64Ux16 x y) left:(Lsh64x16 x z:(Sub16 (Const16 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Add64 right:(Rsh64Ux8 x y) left:(Lsh64x8 x z:(Sub8 (Const8 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpAdd64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Add64F (Const64F [c]) (Const64F [d])) // cond: c+d == c+d // result: (Const64F [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) if !(c+d == c+d) { continue } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c + d) return true } break } return false } func rewriteValuegeneric_OpAdd8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Add8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c+d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c + d) return true } break } // match: (Add8 (Mul8 x y) (Mul8 x z)) // result: (Mul8 x (Add8 y z)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_0, v_1_1 = _i2+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } } break } // match: (Add8 (Const8 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Add8 x (Neg8 y)) // result: (Sub8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpNeg8 { continue } y := v_1.Args[0] v.reset(OpSub8) v.AddArg2(x, y) return true } break } // match: (Add8 (Com8 x) x) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Add8 (Const8 [1]) (Com8 x)) // result: (Neg8 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 1 || v_1.Op != OpCom8 { continue } x := v_1.Args[0] v.reset(OpNeg8) v.AddArg(x) return true } break } // match: (Add8 x (Sub8 y x)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpSub8 { continue } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { continue } v.copyOf(y) return true } break } // match: (Add8 x (Add8 y (Sub8 z x))) // result: (Add8 y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpSub8 { continue } _ = v_1_1.Args[1] z := v_1_1.Args[0] if x != v_1_1.Args[1] { continue } v.reset(OpAdd8) v.AddArg2(y, z) return true } } break } // match: (Add8 (Add8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Add8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAdd8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Add8 (Sub8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpSub8 { continue } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { continue } t := i.Type x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } break } // match: (Add8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Add8 (Const8 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c + d) v.AddArg2(v0, x) return true } } break } // match: (Add8 (Const8 [c]) (Sub8 (Const8 [d]) x)) // result: (Sub8 (Const8 [c+d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpSub8 { continue } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c + d) v.AddArg2(v0, x) return true } break } // match: (Add8 (Lsh8x64 x z:(Const64 [c])) (Rsh8Ux64 x (Const64 [d]))) // cond: c < 8 && d == 8-c && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh8x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh8Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 8 && d == 8-c && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Add8 left:(Lsh8x64 x y) right:(Rsh8Ux64 x (Sub64 (Const64 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Add8 left:(Lsh8x32 x y) right:(Rsh8Ux32 x (Sub32 (Const32 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Add8 left:(Lsh8x16 x y) right:(Rsh8Ux16 x (Sub16 (Const16 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Add8 left:(Lsh8x8 x y) right:(Rsh8Ux8 x (Sub8 (Const8 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Add8 right:(Rsh8Ux64 x y) left:(Lsh8x64 x z:(Sub64 (Const64 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Add8 right:(Rsh8Ux32 x y) left:(Lsh8x32 x z:(Sub32 (Const32 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Add8 right:(Rsh8Ux16 x y) left:(Lsh8x16 x z:(Sub16 (Const16 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Add8 right:(Rsh8Ux8 x y) left:(Lsh8x8 x z:(Sub8 (Const8 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpAddPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (AddPtr x (Const64 [c])) // result: (OffPtr x [c]) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpOffPtr) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (AddPtr x (Const32 [c])) // result: (OffPtr x [int64(c)]) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpOffPtr) v.Type = t v.AuxInt = int64ToAuxInt(int64(c)) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpAnd16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c & d) return true } break } // match: (And16 (Const16 [m]) (Rsh16Ux64 _ (Const64 [c]))) // cond: c >= int64(16-ntz16(m)) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } m := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpRsh16Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(16-ntz16(m))) { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 (Const16 [m]) (Lsh16x64 _ (Const64 [c]))) // cond: c >= int64(16-nlz16(m)) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } m := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpLsh16x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(16-nlz16(m))) { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And16 (Const16 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And16 (Const16 [0]) _) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 (Com16 x) x) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (And16 x (And16 x y)) // result: (And16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd16) v.AddArg2(x, y) return true } } break } // match: (And16 (And16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (And16 i (And16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And16 (Const16 [c]) (And16 (Const16 [d]) x)) // result: (And16 (Const16 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAnd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAnd32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c & d) return true } break } // match: (And32 (Const32 [m]) (Rsh32Ux64 _ (Const64 [c]))) // cond: c >= int64(32-ntz32(m)) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } m := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpRsh32Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(32-ntz32(m))) { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 (Const32 [m]) (Lsh32x64 _ (Const64 [c]))) // cond: c >= int64(32-nlz32(m)) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } m := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpLsh32x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(32-nlz32(m))) { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And32 (Const32 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And32 (Const32 [0]) _) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 (Com32 x) x) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (And32 x (And32 x y)) // result: (And32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd32) v.AddArg2(x, y) return true } } break } // match: (And32 (And32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (And32 i (And32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And32 (Const32 [c]) (And32 (Const32 [d]) x)) // result: (And32 (Const32 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAnd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAnd64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c & d) return true } break } // match: (And64 (Const64 [m]) (Rsh64Ux64 _ (Const64 [c]))) // cond: c >= int64(64-ntz64(m)) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } m := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpRsh64Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(64-ntz64(m))) { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 (Const64 [m]) (Lsh64x64 _ (Const64 [c]))) // cond: c >= int64(64-nlz64(m)) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } m := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpLsh64x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(64-nlz64(m))) { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And64 (Const64 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And64 (Const64 [0]) _) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 (Com64 x) x) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (And64 x (And64 x y)) // result: (And64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd64) v.AddArg2(x, y) return true } } break } // match: (And64 (And64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (And64 i (And64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And64 (Const64 [c]) (And64 (Const64 [d]) x)) // result: (And64 (Const64 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAnd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAnd8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (And8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c&d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c & d) return true } break } // match: (And8 (Const8 [m]) (Rsh8Ux64 _ (Const64 [c]))) // cond: c >= int64(8-ntz8(m)) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } m := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpRsh8Ux64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(8-ntz8(m))) { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 (Const8 [m]) (Lsh8x64 _ (Const64 [c]))) // cond: c >= int64(8-nlz8(m)) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } m := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpLsh8x64 { continue } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= int64(8-nlz8(m))) { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (And8 (Const8 [-1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (And8 (Const8 [0]) _) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 (Com8 x) x) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (And8 x (And8 x y)) // result: (And8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAnd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAnd8) v.AddArg2(x, y) return true } } break } // match: (And8 (And8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (And8 i (And8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (And8 (Const8 [c]) (And8 (Const8 [d]) x)) // result: (And8 (Const8 [c&d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAnd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c & d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpAndB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (AndB (Leq64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: d >= c // result: (Less64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: d >= c // result: (Leq64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: d >= c // result: (Less32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: d >= c // result: (Leq32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: d >= c // result: (Less16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: d >= c // result: (Leq16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: d >= c // result: (Less8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: d >= c // result: (Leq8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: d >= c+1 && c+1 > c // result: (Less8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: d >= c+1 && c+1 > c // result: (Leq8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(d >= c+1 && c+1 > c) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c) // result: (Less64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c) // result: (Leq64U (Sub64 x (Const64 [c])) (Const64 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c) // result: (Less32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c) // result: (Leq32U (Sub32 x (Const32 [c])) (Const32 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c) // result: (Less16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c) // result: (Leq16U (Sub16 x (Const16 [c])) (Const16 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c) // result: (Less8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Leq8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c) // result: (Leq8U (Sub8 x (Const8 [c])) (Const8 [d-c])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c) // result: (Less64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c) // result: (Leq64U (Sub64 x (Const64 [c+1])) (Const64 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(d) >= uint64(c+1) && uint64(c+1) > uint64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpSub64, x.Type) v1 := b.NewValue0(v.Pos, OpConst64, x.Type) v1.AuxInt = int64ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c) // result: (Less32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c) // result: (Leq32U (Sub32 x (Const32 [c+1])) (Const32 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(d) >= uint32(c+1) && uint32(c+1) > uint32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpSub32, x.Type) v1 := b.NewValue0(v.Pos, OpConst32, x.Type) v1.AuxInt = int32ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c) // result: (Less16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c) // result: (Leq16U (Sub16 x (Const16 [c+1])) (Const16 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(d) >= uint16(c+1) && uint16(c+1) > uint16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpSub16, x.Type) v1 := b.NewValue0(v.Pos, OpConst16, x.Type) v1.AuxInt = int16ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c) // result: (Less8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } // match: (AndB (Less8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c) // result: (Leq8U (Sub8 x (Const8 [c+1])) (Const8 [d-c-1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(d) >= uint8(c+1) && uint8(c+1) > uint8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpSub8, x.Type) v1 := b.NewValue0(v.Pos, OpConst8, x.Type) v1.AuxInt = int8ToAuxInt(c + 1) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d - c - 1) v.AddArg2(v0, v2) return true } break } return false } func rewriteValuegeneric_OpArraySelect(v *Value) bool { v_0 := v.Args[0] // match: (ArraySelect (ArrayMake1 x)) // result: x for { if v_0.Op != OpArrayMake1 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (ArraySelect [0] (IData x)) // result: (IData x) for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpIData { break } x := v_0.Args[0] v.reset(OpIData) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpCom16(v *Value) bool { v_0 := v.Args[0] // match: (Com16 (Com16 x)) // result: x for { if v_0.Op != OpCom16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com16 (Const16 [c])) // result: (Const16 [^c]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(^c) return true } // match: (Com16 (Add16 (Const16 [-1]) x)) // result: (Neg16 x) for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst16 || auxIntToInt16(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg16) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpCom32(v *Value) bool { v_0 := v.Args[0] // match: (Com32 (Com32 x)) // result: x for { if v_0.Op != OpCom32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com32 (Const32 [c])) // result: (Const32 [^c]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(^c) return true } // match: (Com32 (Add32 (Const32 [-1]) x)) // result: (Neg32 x) for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg32) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpCom64(v *Value) bool { v_0 := v.Args[0] // match: (Com64 (Com64 x)) // result: x for { if v_0.Op != OpCom64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com64 (Const64 [c])) // result: (Const64 [^c]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(^c) return true } // match: (Com64 (Add64 (Const64 [-1]) x)) // result: (Neg64 x) for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg64) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpCom8(v *Value) bool { v_0 := v.Args[0] // match: (Com8 (Com8 x)) // result: x for { if v_0.Op != OpCom8 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Com8 (Const8 [c])) // result: (Const8 [^c]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(^c) return true } // match: (Com8 (Add8 (Const8 [-1]) x)) // result: (Neg8 x) for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst8 || auxIntToInt8(v_0_0.AuxInt) != -1 { continue } x := v_0_1 v.reset(OpNeg8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpConstInterface(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ConstInterface) // result: (IMake (ConstNil ) (ConstNil )) for { v.reset(OpIMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.Uintptr) v1 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpConstSlice(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (ConstSlice) // cond: config.PtrSize == 4 // result: (SliceMake (ConstNil ) (Const32 [0]) (Const32 [0])) for { if !(config.PtrSize == 4) { break } v.reset(OpSliceMake) v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = int32ToAuxInt(0) v.AddArg3(v0, v1, v1) return true } // match: (ConstSlice) // cond: config.PtrSize == 8 // result: (SliceMake (ConstNil ) (Const64 [0]) (Const64 [0])) for { if !(config.PtrSize == 8) { break } v.reset(OpSliceMake) v0 := b.NewValue0(v.Pos, OpConstNil, v.Type.Elem().PtrTo()) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = int64ToAuxInt(0) v.AddArg3(v0, v1, v1) return true } return false } func rewriteValuegeneric_OpConstString(v *Value) bool { b := v.Block config := b.Func.Config fe := b.Func.fe typ := &b.Func.Config.Types // match: (ConstString {str}) // cond: config.PtrSize == 4 && str == "" // result: (StringMake (ConstNil) (Const32 [0])) for { str := auxToString(v.Aux) if !(config.PtrSize == 4 && str == "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v1) return true } // match: (ConstString {str}) // cond: config.PtrSize == 8 && str == "" // result: (StringMake (ConstNil) (Const64 [0])) for { str := auxToString(v.Aux) if !(config.PtrSize == 8 && str == "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpConstNil, typ.BytePtr) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, v1) return true } // match: (ConstString {str}) // cond: config.PtrSize == 4 && str != "" // result: (StringMake (Addr {fe.StringData(str)} (SB)) (Const32 [int32(len(str))])) for { str := auxToString(v.Aux) if !(config.PtrSize == 4 && str != "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) v0.Aux = symToAux(fe.StringData(str)) v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int) v2.AuxInt = int32ToAuxInt(int32(len(str))) v.AddArg2(v0, v2) return true } // match: (ConstString {str}) // cond: config.PtrSize == 8 && str != "" // result: (StringMake (Addr {fe.StringData(str)} (SB)) (Const64 [int64(len(str))])) for { str := auxToString(v.Aux) if !(config.PtrSize == 8 && str != "") { break } v.reset(OpStringMake) v0 := b.NewValue0(v.Pos, OpAddr, typ.BytePtr) v0.Aux = symToAux(fe.StringData(str)) v1 := b.NewValue0(v.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.Int) v2.AuxInt = int64ToAuxInt(int64(len(str))) v.AddArg2(v0, v2) return true } return false } func rewriteValuegeneric_OpConvert(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Convert (Add64 (Convert ptr mem) off) mem) // result: (AddPtr ptr off) for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConvert { continue } mem := v_0_0.Args[1] ptr := v_0_0.Args[0] off := v_0_1 if mem != v_1 { continue } v.reset(OpAddPtr) v.AddArg2(ptr, off) return true } break } // match: (Convert (Add32 (Convert ptr mem) off) mem) // result: (AddPtr ptr off) for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConvert { continue } mem := v_0_0.Args[1] ptr := v_0_0.Args[0] off := v_0_1 if mem != v_1 { continue } v.reset(OpAddPtr) v.AddArg2(ptr, off) return true } break } // match: (Convert (Convert ptr mem) mem) // result: ptr for { if v_0.Op != OpConvert { break } mem := v_0.Args[1] ptr := v_0.Args[0] if mem != v_1 { break } v.copyOf(ptr) return true } return false } func rewriteValuegeneric_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz16 (Const16 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz16(c))) return true } // match: (Ctz16 (Const16 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz16(c))) return true } return false } func rewriteValuegeneric_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz32 (Const32 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz32(c))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz32(c))) return true } // match: (Ctz32 (Const32 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz32(c))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz32(c))) return true } return false } func rewriteValuegeneric_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz64 (Const64 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz64(c))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz64(c))) return true } // match: (Ctz64 (Const64 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz64(c))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } return false } func rewriteValuegeneric_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Ctz8 (Const8 [c])) // cond: config.PtrSize == 4 // result: (Const32 [int32(ntz8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(ntz8(c))) return true } // match: (Ctz8 (Const8 [c])) // cond: config.PtrSize == 8 // result: (Const64 [int64(ntz8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if !(config.PtrSize == 8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(ntz8(c))) return true } return false } func rewriteValuegeneric_OpCvt32Fto32(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32Fto32 (Const32F [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } return false } func rewriteValuegeneric_OpCvt32Fto64(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32Fto64 (Const32F [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } return false } func rewriteValuegeneric_OpCvt32Fto64F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32Fto64F (Const32F [c])) // result: (Const64F [float64(c)]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(float64(c)) return true } return false } func rewriteValuegeneric_OpCvt32to32F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32to32F (Const32 [c])) // result: (Const32F [float32(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(float32(c)) return true } return false } func rewriteValuegeneric_OpCvt32to64F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt32to64F (Const32 [c])) // result: (Const64F [float64(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(float64(c)) return true } return false } func rewriteValuegeneric_OpCvt64Fto32(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64Fto32 (Const64F [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } return false } func rewriteValuegeneric_OpCvt64Fto32F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64Fto32F (Const64F [c])) // result: (Const32F [float32(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(float32(c)) return true } // match: (Cvt64Fto32F sqrt0:(Sqrt (Cvt32Fto64F x))) // cond: sqrt0.Uses==1 // result: (Sqrt32 x) for { sqrt0 := v_0 if sqrt0.Op != OpSqrt { break } sqrt0_0 := sqrt0.Args[0] if sqrt0_0.Op != OpCvt32Fto64F { break } x := sqrt0_0.Args[0] if !(sqrt0.Uses == 1) { break } v.reset(OpSqrt32) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpCvt64Fto64(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64Fto64 (Const64F [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } return false } func rewriteValuegeneric_OpCvt64to32F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64to32F (Const64 [c])) // result: (Const32F [float32(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(float32(c)) return true } return false } func rewriteValuegeneric_OpCvt64to64F(v *Value) bool { v_0 := v.Args[0] // match: (Cvt64to64F (Const64 [c])) // result: (Const64F [float64(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(float64(c)) return true } return false } func rewriteValuegeneric_OpCvtBoolToUint8(v *Value) bool { v_0 := v.Args[0] // match: (CvtBoolToUint8 (ConstBool [false])) // result: (Const8 [0]) for { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != false { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (CvtBoolToUint8 (ConstBool [true])) // result: (Const8 [1]) for { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != true { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(1) return true } return false } func rewriteValuegeneric_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [c/d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c / d) return true } // match: (Div16 n (Const16 [c])) // cond: isNonNegative(n) && isPowerOfTwo16(c) // result: (Rsh16Ux64 n (Const64 [log16(c)])) for { n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo16(c)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log16(c)) v.AddArg2(n, v0) return true } // match: (Div16 n (Const16 [c])) // cond: c < 0 && c != -1<<15 // result: (Neg16 (Div16 n (Const16 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(c < 0 && c != -1<<15) { break } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpDiv16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div16 x (Const16 [-1<<15])) // result: (Rsh16Ux64 (And16 x (Neg16 x)) (Const64 [15])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != -1<<15 { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpNeg16, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(15) v.AddArg2(v0, v2) return true } // match: (Div16 n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [int64(16-log16(c))]))) (Const64 [int64(log16(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { break } v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpAdd16, t) v1 := b.NewValue0(v.Pos, OpRsh16Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh16x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(15) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(16 - log16(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log16(c))) v.AddArg2(v0, v5) return true } // match: (Div16 x (Const16 [c])) // cond: smagicOK16(c) // result: (Sub16 (Rsh32x64 (Mul32 (Const32 [int32(smagic16(c).m)]) (SignExt16to32 x)) (Const64 [16+smagic16(c).s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(smagicOK16(c)) { break } v.reset(OpSub16) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(smagic16(c).m)) v3 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16 + smagic16(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(31) v5.AddArg2(v3, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div16u (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int16(uint16(c)/uint16(d))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint16(c) / uint16(d))) return true } // match: (Div16u n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (Rsh16Ux64 n (Const64 [log16(c)])) for { n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log16(c)) v.AddArg2(n, v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 8 // result: (Trunc64to16 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<16+umagic16(c).m)]) (ZeroExt16to64 x)) (Const64 [16+umagic16(c).s]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 8) { break } v.reset(OpTrunc64to16) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(1<<16 + umagic16(c).m)) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16 + umagic16(c).s) v0.AddArg2(v1, v4) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 4 && umagic16(c).m&1 == 0 // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<15+umagic16(c).m/2)]) (ZeroExt16to32 x)) (Const64 [16+umagic16(c).s-1]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 4 && umagic16(c).m&1 == 0) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(1<<15 + umagic16(c).m/2)) v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 1) v0.AddArg2(v1, v4) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 4 && c&1 == 0 // result: (Trunc32to16 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<15+(umagic16(c).m+1)/2)]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [16+umagic16(c).s-2]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 4 && c&1 == 0) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(1<<15 + (umagic16(c).m+1)/2)) v3 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v4 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v4.AddArg(x) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(1) v3.AddArg2(v4, v5) v1.AddArg2(v2, v3) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 2) v0.AddArg2(v1, v6) v.AddArg(v0) return true } // match: (Div16u x (Const16 [c])) // cond: umagicOK16(c) && config.RegSize == 4 && config.useAvg // result: (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) (Mul32 (Const32 [int32(umagic16(c).m)]) (ZeroExt16to32 x))) (Const64 [16+umagic16(c).s-1]))) for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(umagicOK16(c) && config.RegSize == 4 && config.useAvg) { break } v.reset(OpTrunc32to16) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) v2 := b.NewValue0(v.Pos, OpLsh32x64, typ.UInt32) v3 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v3.AddArg(x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(16) v2.AddArg2(v3, v4) v5 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(umagic16(c).m)) v5.AddArg2(v6, v3) v1.AddArg2(v2, v5) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = int64ToAuxInt(16 + umagic16(c).s - 1) v0.AddArg2(v1, v7) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32 (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [c/d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c / d) return true } // match: (Div32 n (Const32 [c])) // cond: isNonNegative(n) && isPowerOfTwo32(c) // result: (Rsh32Ux64 n (Const64 [log32(c)])) for { n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo32(c)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log32(c)) v.AddArg2(n, v0) return true } // match: (Div32 n (Const32 [c])) // cond: c < 0 && c != -1<<31 // result: (Neg32 (Div32 n (Const32 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(c < 0 && c != -1<<31) { break } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpDiv32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div32 x (Const32 [-1<<31])) // result: (Rsh32Ux64 (And32 x (Neg32 x)) (Const64 [31])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != -1<<31 { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpNeg32, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(31) v.AddArg2(v0, v2) return true } // match: (Div32 n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [int64(32-log32(c))]))) (Const64 [int64(log32(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { break } v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpAdd32, t) v1 := b.NewValue0(v.Pos, OpRsh32Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh32x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(31) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(32 - log32(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log32(c))) v.AddArg2(v0, v5) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK32(c) && config.RegSize == 8 // result: (Sub32 (Rsh64x64 (Mul64 (Const64 [int64(smagic32(c).m)]) (SignExt32to64 x)) (Const64 [32+smagic32(c).s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(smagicOK32(c) && config.RegSize == 8) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(smagic32(c).m)) v3 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(32 + smagic32(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh64x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(63) v5.AddArg2(v3, v6) v.AddArg2(v0, v5) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0 && config.useHmul // result: (Sub32 (Rsh32x64 (Hmul32 (Const32 [int32(smagic32(c).m/2)]) x) (Const64 [smagic32(c).s-1])) (Rsh32x64 x (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 == 0 && config.useHmul) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpHmul32, t) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(smagic32(c).m / 2)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(smagic32(c).s - 1) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpRsh32x64, t) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(31) v4.AddArg2(x, v5) v.AddArg2(v0, v4) return true } // match: (Div32 x (Const32 [c])) // cond: smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0 && config.useHmul // result: (Sub32 (Rsh32x64 (Add32 (Hmul32 (Const32 [int32(smagic32(c).m)]) x) x) (Const64 [smagic32(c).s])) (Rsh32x64 x (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(smagicOK32(c) && config.RegSize == 4 && smagic32(c).m&1 != 0 && config.useHmul) { break } v.reset(OpSub32) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpAdd32, t) v2 := b.NewValue0(v.Pos, OpHmul32, t) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(smagic32(c).m)) v2.AddArg2(v3, x) v1.AddArg2(v2, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(smagic32(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(31) v5.AddArg2(x, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Div32F (Const32F [c]) (Const32F [d])) // cond: c/d == c/d // result: (Const32F [c/d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) if !(c/d == c/d) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c / d) return true } // match: (Div32F x (Const32F [c])) // cond: reciprocalExact32(c) // result: (Mul32F x (Const32F [1/c])) for { x := v_0 if v_1.Op != OpConst32F { break } t := v_1.Type c := auxIntToFloat32(v_1.AuxInt) if !(reciprocalExact32(c)) { break } v.reset(OpMul32F) v0 := b.NewValue0(v.Pos, OpConst32F, t) v0.AuxInt = float32ToAuxInt(1 / c) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpDiv32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div32u (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int32(uint32(c)/uint32(d))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint32(c) / uint32(d))) return true } // match: (Div32u n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (Rsh32Ux64 n (Const64 [log32(c)])) for { n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log32(c)) v.AddArg2(n, v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 4 && umagic32(c).m&1 == 0 && config.useHmul // result: (Rsh32Ux64 (Hmul32u (Const32 [int32(1<<31+umagic32(c).m/2)]) x) (Const64 [umagic32(c).s-1])) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 4 && umagic32(c).m&1 == 0 && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v1.AuxInt = int32ToAuxInt(int32(1<<31 + umagic32(c).m/2)) v0.AddArg2(v1, x) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(umagic32(c).s - 1) v.AddArg2(v0, v2) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 4 && c&1 == 0 && config.useHmul // result: (Rsh32Ux64 (Hmul32u (Const32 [int32(1<<31+(umagic32(c).m+1)/2)]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [umagic32(c).s-2])) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 4 && c&1 == 0 && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v1.AuxInt = int32ToAuxInt(int32(1<<31 + (umagic32(c).m+1)/2)) v2 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(1) v2.AddArg2(x, v3) v0.AddArg2(v1, v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(umagic32(c).s - 2) v.AddArg2(v0, v4) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 4 && config.useAvg && config.useHmul // result: (Rsh32Ux64 (Avg32u x (Hmul32u (Const32 [int32(umagic32(c).m)]) x)) (Const64 [umagic32(c).s-1])) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 4 && config.useAvg && config.useHmul) { break } v.reset(OpRsh32Ux64) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAvg32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpHmul32u, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(umagic32(c).m)) v1.AddArg2(v2, x) v0.AddArg2(x, v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(umagic32(c).s - 1) v.AddArg2(v0, v3) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 8 && umagic32(c).m&1 == 0 // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+umagic32(c).m/2)]) (ZeroExt32to64 x)) (Const64 [32+umagic32(c).s-1]))) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 8 && umagic32(c).m&1 == 0) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(1<<31 + umagic32(c).m/2)) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 1) v0.AddArg2(v1, v4) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 8 && c&1 == 0 // result: (Trunc64to32 (Rsh64Ux64 (Mul64 (Const64 [int64(1<<31+(umagic32(c).m+1)/2)]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [32+umagic32(c).s-2]))) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 8 && c&1 == 0) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(1<<31 + (umagic32(c).m+1)/2)) v3 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(x) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(1) v3.AddArg2(v4, v5) v1.AddArg2(v2, v3) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 2) v0.AddArg2(v1, v6) v.AddArg(v0) return true } // match: (Div32u x (Const32 [c])) // cond: umagicOK32(c) && config.RegSize == 8 && config.useAvg // result: (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) (Mul64 (Const64 [int64(umagic32(c).m)]) (ZeroExt32to64 x))) (Const64 [32+umagic32(c).s-1]))) for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(umagicOK32(c) && config.RegSize == 8 && config.useAvg) { break } v.reset(OpTrunc64to32) v0 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(32) v2.AddArg2(v3, v4) v5 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt32) v6.AuxInt = int64ToAuxInt(int64(umagic32(c).m)) v5.AddArg2(v6, v3) v1.AddArg2(v2, v5) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = int64ToAuxInt(32 + umagic32(c).s - 1) v0.AddArg2(v1, v7) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64 (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [c/d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c / d) return true } // match: (Div64 n (Const64 [c])) // cond: isNonNegative(n) && isPowerOfTwo64(c) // result: (Rsh64Ux64 n (Const64 [log64(c)])) for { n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo64(c)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(n, v0) return true } // match: (Div64 n (Const64 [-1<<63])) // cond: isNonNegative(n) // result: (Const64 [0]) for { n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 || !(isNonNegative(n)) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Div64 n (Const64 [c])) // cond: c < 0 && c != -1<<63 // result: (Neg64 (Div64 n (Const64 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c < 0 && c != -1<<63) { break } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpDiv64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div64 x (Const64 [-1<<63])) // result: (Rsh64Ux64 (And64 x (Neg64 x)) (Const64 [63])) for { t := v.Type x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpNeg64, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(63) v.AddArg2(v0, v2) return true } // match: (Div64 n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [int64(64-log64(c))]))) (Const64 [int64(log64(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v1 := b.NewValue0(v.Pos, OpRsh64Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh64x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(63) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(64 - log64(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log64(c))) v.AddArg2(v0, v5) return true } // match: (Div64 x (Const64 [c])) // cond: smagicOK64(c) && smagic64(c).m&1 == 0 && config.useHmul // result: (Sub64 (Rsh64x64 (Hmul64 (Const64 [int64(smagic64(c).m/2)]) x) (Const64 [smagic64(c).s-1])) (Rsh64x64 x (Const64 [63]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(smagicOK64(c) && smagic64(c).m&1 == 0 && config.useHmul) { break } v.reset(OpSub64) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpHmul64, t) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(smagic64(c).m / 2)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(smagic64(c).s - 1) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpRsh64x64, t) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(63) v4.AddArg2(x, v5) v.AddArg2(v0, v4) return true } // match: (Div64 x (Const64 [c])) // cond: smagicOK64(c) && smagic64(c).m&1 != 0 && config.useHmul // result: (Sub64 (Rsh64x64 (Add64 (Hmul64 (Const64 [int64(smagic64(c).m)]) x) x) (Const64 [smagic64(c).s])) (Rsh64x64 x (Const64 [63]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(smagicOK64(c) && smagic64(c).m&1 != 0 && config.useHmul) { break } v.reset(OpSub64) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh64x64, t) v1 := b.NewValue0(v.Pos, OpAdd64, t) v2 := b.NewValue0(v.Pos, OpHmul64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(int64(smagic64(c).m)) v2.AddArg2(v3, x) v1.AddArg2(v2, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(smagic64(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh64x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(63) v5.AddArg2(x, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Div64F (Const64F [c]) (Const64F [d])) // cond: c/d == c/d // result: (Const64F [c/d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) if !(c/d == c/d) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c / d) return true } // match: (Div64F x (Const64F [c])) // cond: reciprocalExact64(c) // result: (Mul64F x (Const64F [1/c])) for { x := v_0 if v_1.Op != OpConst64F { break } t := v_1.Type c := auxIntToFloat64(v_1.AuxInt) if !(reciprocalExact64(c)) { break } v.reset(OpMul64F) v0 := b.NewValue0(v.Pos, OpConst64F, t) v0.AuxInt = float64ToAuxInt(1 / c) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpDiv64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Div64u (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [int64(uint64(c)/uint64(d))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint64(c) / uint64(d))) return true } // match: (Div64u n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (Rsh64Ux64 n (Const64 [log64(c)])) for { n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(n, v0) return true } // match: (Div64u n (Const64 [-1<<63])) // result: (Rsh64Ux64 n (Const64 [63])) for { n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(63) v.AddArg2(n, v0) return true } // match: (Div64u x (Const64 [c])) // cond: c > 0 && c <= 0xFFFF && umagicOK32(int32(c)) && config.RegSize == 4 && config.useHmul // result: (Add64 (Add64 (Add64 (Lsh64x64 (ZeroExt32to64 (Div32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)]))) (Const64 [32])) (ZeroExt32to64 (Div32u (Trunc64to32 x) (Const32 [int32(c)])))) (Mul64 (ZeroExt32to64 (Mod32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)]))) (Const64 [int64((1<<32)/c)]))) (ZeroExt32to64 (Div32u (Add32 (Mod32u (Trunc64to32 x) (Const32 [int32(c)])) (Mul32 (Mod32u (Trunc64to32 (Rsh64Ux64 x (Const64 [32]))) (Const32 [int32(c)])) (Const32 [int32((1<<32)%c)]))) (Const32 [int32(c)])))) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c > 0 && c <= 0xFFFF && umagicOK32(int32(c)) && config.RegSize == 4 && config.useHmul) { break } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpLsh64x64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) v5 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v6 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v7 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v7.AuxInt = int64ToAuxInt(32) v6.AddArg2(x, v7) v5.AddArg(v6) v8 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v8.AuxInt = int32ToAuxInt(int32(c)) v4.AddArg2(v5, v8) v3.AddArg(v4) v2.AddArg2(v3, v7) v9 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v10 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) v11 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v11.AddArg(x) v10.AddArg2(v11, v8) v9.AddArg(v10) v1.AddArg2(v2, v9) v12 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v13 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v14 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v14.AddArg2(v5, v8) v13.AddArg(v14) v15 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v15.AuxInt = int64ToAuxInt(int64((1 << 32) / c)) v12.AddArg2(v13, v15) v0.AddArg2(v1, v12) v16 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v17 := b.NewValue0(v.Pos, OpDiv32u, typ.UInt32) v18 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v19 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v19.AddArg2(v11, v8) v20 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v21 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v21.AuxInt = int32ToAuxInt(int32((1 << 32) % c)) v20.AddArg2(v14, v21) v18.AddArg2(v19, v20) v17.AddArg2(v18, v8) v16.AddArg(v17) v.AddArg2(v0, v16) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK64(c) && config.RegSize == 8 && umagic64(c).m&1 == 0 && config.useHmul // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+umagic64(c).m/2)]) x) (Const64 [umagic64(c).s-1])) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(umagicOK64(c) && config.RegSize == 8 && umagic64(c).m&1 == 0 && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(int64(1<<63 + umagic64(c).m/2)) v0.AddArg2(v1, x) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(umagic64(c).s - 1) v.AddArg2(v0, v2) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK64(c) && config.RegSize == 8 && c&1 == 0 && config.useHmul // result: (Rsh64Ux64 (Hmul64u (Const64 [int64(1<<63+(umagic64(c).m+1)/2)]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [umagic64(c).s-2])) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(umagicOK64(c) && config.RegSize == 8 && c&1 == 0 && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(int64(1<<63 + (umagic64(c).m+1)/2)) v2 := b.NewValue0(v.Pos, OpRsh64Ux64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(1) v2.AddArg2(x, v3) v0.AddArg2(v1, v2) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(umagic64(c).s - 2) v.AddArg2(v0, v4) return true } // match: (Div64u x (Const64 [c])) // cond: umagicOK64(c) && config.RegSize == 8 && config.useAvg && config.useHmul // result: (Rsh64Ux64 (Avg64u x (Hmul64u (Const64 [int64(umagic64(c).m)]) x)) (Const64 [umagic64(c).s-1])) for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(umagicOK64(c) && config.RegSize == 8 && config.useAvg && config.useHmul) { break } v.reset(OpRsh64Ux64) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAvg64u, typ.UInt64) v1 := b.NewValue0(v.Pos, OpHmul64u, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(umagic64(c).m)) v1.AddArg2(v2, x) v0.AddArg2(x, v1) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(umagic64(c).s - 1) v.AddArg2(v0, v3) return true } return false } func rewriteValuegeneric_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [c/d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c / d) return true } // match: (Div8 n (Const8 [c])) // cond: isNonNegative(n) && isPowerOfTwo8(c) // result: (Rsh8Ux64 n (Const64 [log8(c)])) for { n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo8(c)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log8(c)) v.AddArg2(n, v0) return true } // match: (Div8 n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Neg8 (Div8 n (Const8 [-c]))) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(c < 0 && c != -1<<7) { break } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpDiv8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(-c) v0.AddArg2(n, v1) v.AddArg(v0) return true } // match: (Div8 x (Const8 [-1<<7 ])) // result: (Rsh8Ux64 (And8 x (Neg8 x)) (Const64 [7 ])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != -1<<7 { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpNeg8, t) v1.AddArg(x) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(7) v.AddArg2(v0, v2) return true } // match: (Div8 n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [int64( 8-log8(c))]))) (Const64 [int64(log8(c))])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { break } v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpAdd8, t) v1 := b.NewValue0(v.Pos, OpRsh8Ux64, t) v2 := b.NewValue0(v.Pos, OpRsh8x64, t) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(7) v2.AddArg2(n, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(8 - log8(c))) v1.AddArg2(v2, v4) v0.AddArg2(n, v1) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(int64(log8(c))) v.AddArg2(v0, v5) return true } // match: (Div8 x (Const8 [c])) // cond: smagicOK8(c) // result: (Sub8 (Rsh32x64 (Mul32 (Const32 [int32(smagic8(c).m)]) (SignExt8to32 x)) (Const64 [8+smagic8(c).s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(smagicOK8(c)) { break } v.reset(OpSub8) v.Type = t v0 := b.NewValue0(v.Pos, OpRsh32x64, t) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(smagic8(c).m)) v3 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(8 + smagic8(c).s) v0.AddArg2(v1, v4) v5 := b.NewValue0(v.Pos, OpRsh32x64, t) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(31) v5.AddArg2(v3, v6) v.AddArg2(v0, v5) return true } return false } func rewriteValuegeneric_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int8(uint8(c)/uint8(d))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(uint8(c) / uint8(d))) return true } // match: (Div8u n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (Rsh8Ux64 n (Const64 [log8(c)])) for { n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log8(c)) v.AddArg2(n, v0) return true } // match: (Div8u x (Const8 [c])) // cond: umagicOK8(c) // result: (Trunc32to8 (Rsh32Ux64 (Mul32 (Const32 [int32(1<<8+umagic8(c).m)]) (ZeroExt8to32 x)) (Const64 [8+umagic8(c).s]))) for { x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(umagicOK8(c)) { break } v.reset(OpTrunc32to8) v0 := b.NewValue0(v.Pos, OpRsh32Ux64, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(1<<8 + umagic8(c).m)) v3 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v3.AddArg(x) v1.AddArg2(v2, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(8 + umagic8(c).s) v0.AddArg2(v1, v4) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Eq16 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Eq16 (Const16 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq16 (Const16 [c]) (Const16 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq16 (Mod16u x (Const16 [c])) (Const16 [0])) // cond: x.Op != OpConst16 && udivisibleOK16(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt16to32 x) (Const32 [int32(uint16(c))])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod16u { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 || !(x.Op != OpConst16 && udivisibleOK16(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(uint16(c))) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq16 (Mod16 x (Const16 [c])) (Const16 [0])) // cond: x.Op != OpConst16 && sdivisibleOK16(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32 (SignExt16to32 x) (Const32 [int32(c)])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod16 { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 || !(x.Op != OpConst16 && sdivisibleOK16(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc64to16 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt16to64 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic16(c).m) && s == 16+umagic16(c).s && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpZeroExt16to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<16+umagic16(c).m) && s == 16+umagic16(c).s && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+umagic16(c).m/2) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpZeroExt16to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+umagic16(c).m/2) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (Rsh32Ux64 (ZeroExt16to32 x) (Const64 [1]))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+(umagic16(c).m+1)/2) && s == 16+umagic16(c).s-2 && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpRsh32Ux64 { continue } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt16to32 || x != mul_1_0.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<15+(umagic16(c).m+1)/2) && s == 16+umagic16(c).s-2 && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Trunc32to16 (Rsh32Ux64 (Avg32u (Lsh32x64 (ZeroExt16to32 x) (Const64 [16])) mul:(Mul32 (Const32 [m]) (ZeroExt16to32 x))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic16(c).m) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Mul16 (Const16 [int16(udivisible16(c).m)]) x) (Const16 [int16(16-udivisible16(c).k)]) ) (Const16 [int16(udivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to16 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg32u { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh32x64 { continue } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt16to32 || x != v_1_1_0_0_0_0.Args[0] { continue } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 || auxIntToInt64(v_1_1_0_0_0_1.AuxInt) != 16 { continue } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpZeroExt16to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic16(c).m) && s == 16+umagic16(c).s-1 && x.Op != OpConst16 && udivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v2.AuxInt = int16ToAuxInt(int16(udivisible16(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(16 - udivisible16(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(udivisible16(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq16 x (Mul16 (Const16 [c]) (Sub16 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt16to32 x)) (Const64 [s])) (Rsh32x64 (SignExt16to32 x) (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic16(c).m) && s == 16+smagic16(c).s && x.Op != OpConst16 && sdivisibleOK16(c) // result: (Leq16U (RotateLeft16 (Add16 (Mul16 (Const16 [int16(sdivisible16(c).m)]) x) (Const16 [int16(sdivisible16(c).a)]) ) (Const16 [int16(16-sdivisible16(c).k)]) ) (Const16 [int16(sdivisible16(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0.AuxInt) if v_1_1.Op != OpSub16 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpSignExt16to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt16to32 || x != v_1_1_1_0.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic16(c).m) && s == 16+smagic16(c).s && x.Op != OpConst16 && sdivisibleOK16(c)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpRotateLeft16, typ.UInt16) v1 := b.NewValue0(v.Pos, OpAdd16, typ.UInt16) v2 := b.NewValue0(v.Pos, OpMul16, typ.UInt16) v3 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v3.AuxInt = int16ToAuxInt(int16(sdivisible16(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v4.AuxInt = int16ToAuxInt(int16(sdivisible16(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v5.AuxInt = int16ToAuxInt(int16(16 - sdivisible16(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst16, typ.UInt16) v6.AuxInt = int16ToAuxInt(int16(sdivisible16(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Eq16 (And16 n (Const16 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh16x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh16x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd16 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh16Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh16x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 15 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 15 && kbar == 16-k) { continue } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(1< x (Const16 [y])) (Const16 [y])) // cond: oneBit16(y) // result: (Neq16 (And16 x (Const16 [y])) (Const16 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst16 || v_0_1.Type != t { continue } y := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || v_1.Type != t || auxIntToInt16(v_1.AuxInt) != y || !(oneBit16(y)) { continue } v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq32 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Eq32 (Const32 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) x) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+umagic32(c).m/2) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpRsh32Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+umagic32(c).m/2) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 mul:(Hmul32u (Const32 [m]) (Rsh32Ux64 x (Const64 [1]))) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+(umagic32(c).m+1)/2) && s == umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpRsh32Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul32u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 || mul_0.Type != typ.UInt32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpRsh32Ux64 { continue } _ = mul_1.Args[1] if x != mul_1.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<31+(umagic32(c).m+1)/2) && s == umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Rsh32Ux64 (Avg32u x mul:(Hmul32u (Const32 [m]) x)) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic32(c).m) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpRsh32Ux64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg32u { continue } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { continue } mul := v_1_1_0.Args[1] if mul.Op != OpHmul32u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(umagic32(c).m) && s == umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic32(c).m/2) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to32 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpZeroExt32to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+umagic32(c).m/2) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 mul:(Mul64 (Const64 [m]) (Rsh64Ux64 (ZeroExt32to64 x) (Const64 [1]))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic32(c).m+1)/2) && s == 32+umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to32 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpRsh64Ux64 { continue } _ = mul_1.Args[1] mul_1_0 := mul_1.Args[0] if mul_1_0.Op != OpZeroExt32to64 || x != mul_1_0.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<31+(umagic32(c).m+1)/2) && s == 32+umagic32(c).s-2 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Trunc64to32 (Rsh64Ux64 (Avg64u (Lsh64x64 (ZeroExt32to64 x) (Const64 [32])) mul:(Mul64 (Const64 [m]) (ZeroExt32to64 x))) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic32(c).m) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Mul32 (Const32 [int32(udivisible32(c).m)]) x) (Const32 [int32(32-udivisible32(c).k)]) ) (Const32 [int32(udivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpTrunc64to32 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64Ux64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAvg64u { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpLsh64x64 { continue } _ = v_1_1_0_0_0.Args[1] v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpZeroExt32to64 || x != v_1_1_0_0_0_0.Args[0] { continue } v_1_1_0_0_0_1 := v_1_1_0_0_0.Args[1] if v_1_1_0_0_0_1.Op != OpConst64 || auxIntToInt64(v_1_1_0_0_0_1.AuxInt) != 32 { continue } mul := v_1_1_0_0.Args[1] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpZeroExt32to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic32(c).m) && s == 32+umagic32(c).s-1 && x.Op != OpConst32 && udivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(udivisible32(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(32 - udivisible32(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(udivisible32(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh64x64 mul:(Mul64 (Const64 [m]) (SignExt32to64 x)) (Const64 [s])) (Rsh64x64 (SignExt32to64 x) (Const64 [63]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic32(c).m) && s == 32+smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpSignExt32to64 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { continue } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt32to64 || x != v_1_1_1_0.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic32(c).m) && s == 32+smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 mul:(Hmul32 (Const32 [m]) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m/2) && s == smagic32(c).s-1 && x.Op != OpConst32 && sdivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpHmul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m/2) && s == smagic32(c).s-1 && x.Op != OpConst32 && sdivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq32 x (Mul32 (Const32 [c]) (Sub32 (Rsh32x64 (Add32 mul:(Hmul32 (Const32 [m]) x) x) (Const64 [s])) (Rsh32x64 x (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m) && s == smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c) // result: (Leq32U (RotateLeft32 (Add32 (Mul32 (Const32 [int32(sdivisible32(c).m)]) x) (Const32 [int32(sdivisible32(c).a)]) ) (Const32 [int32(32-sdivisible32(c).k)]) ) (Const32 [int32(sdivisible32(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0.AuxInt) if v_1_1.Op != OpSub32 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd32 { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] v_1_1_0_0_1 := v_1_1_0_0.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_1_0_0_0, v_1_1_0_0_1 = _i2+1, v_1_1_0_0_1, v_1_1_0_0_0 { mul := v_1_1_0_0_0 if mul.Op != OpHmul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i3 := 0; _i3 <= 1; _i3, mul_0, mul_1 = _i3+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if x != mul_1 || x != v_1_1_0_0_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic32(c).m) && s == smagic32(c).s && x.Op != OpConst32 && sdivisibleOK32(c)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpRotateLeft32, typ.UInt32) v1 := b.NewValue0(v.Pos, OpAdd32, typ.UInt32) v2 := b.NewValue0(v.Pos, OpMul32, typ.UInt32) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(int32(sdivisible32(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v4.AuxInt = int32ToAuxInt(int32(sdivisible32(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v5.AuxInt = int32ToAuxInt(int32(32 - sdivisible32(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v6.AuxInt = int32ToAuxInt(int32(sdivisible32(c).max)) v.AddArg2(v0, v6) return true } } } } break } // match: (Eq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Eq32 (And32 n (Const32 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh32x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd32 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh32Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh32x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 31 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 31 && kbar == 32-k) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(1< x (Const32 [y])) (Const32 [y])) // cond: oneBit32(y) // result: (Neq32 (And32 x (Const32 [y])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst32 || v_0_1.Type != t { continue } y := auxIntToInt32(v_0_1.AuxInt) if v_1.Op != OpConst32 || v_1.Type != t || auxIntToInt32(v_1.AuxInt) != y || !(oneBit32(y)) { continue } v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Eq32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } return false } func rewriteValuegeneric_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq64 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Eq64 (Const64 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) x) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic64(c).m/2) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpRsh64Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+umagic64(c).m/2) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 mul:(Hmul64u (Const64 [m]) (Rsh64Ux64 x (Const64 [1]))) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic64(c).m+1)/2) && s == umagic64(c).s-2 && x.Op != OpConst64 && udivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpRsh64Ux64 { continue } _ = v_1_1.Args[1] mul := v_1_1.Args[0] if mul.Op != OpHmul64u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if mul_1.Op != OpRsh64Ux64 { continue } _ = mul_1.Args[1] if x != mul_1.Args[0] { continue } mul_1_1 := mul_1.Args[1] if mul_1_1.Op != OpConst64 || auxIntToInt64(mul_1_1.AuxInt) != 1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(1<<63+(umagic64(c).m+1)/2) && s == umagic64(c).s-2 && x.Op != OpConst64 && udivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Rsh64Ux64 (Avg64u x mul:(Hmul64u (Const64 [m]) x)) (Const64 [s])) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic64(c).m) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Mul64 (Const64 [int64(udivisible64(c).m)]) x) (Const64 [64-udivisible64(c).k]) ) (Const64 [int64(udivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpRsh64Ux64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAvg64u { continue } _ = v_1_1_0.Args[1] if x != v_1_1_0.Args[0] { continue } mul := v_1_1_0.Args[1] if mul.Op != OpHmul64u { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(umagic64(c).m) && s == umagic64(c).s-1 && x.Op != OpConst64 && udivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(udivisible64(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(64 - udivisible64(c).k) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(udivisible64(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 mul:(Hmul64 (Const64 [m]) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m/2) && s == smagic64(c).s-1 && x.Op != OpConst64 && sdivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible64(c).m)]) x) (Const64 [int64(sdivisible64(c).a)]) ) (Const64 [64-sdivisible64(c).k]) ) (Const64 [int64(sdivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpSub64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpHmul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m/2) && s == smagic64(c).s-1 && x.Op != OpConst64 && sdivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(int64(sdivisible64(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(sdivisible64(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(64 - sdivisible64(c).k) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(int64(sdivisible64(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq64 x (Mul64 (Const64 [c]) (Sub64 (Rsh64x64 (Add64 mul:(Hmul64 (Const64 [m]) x) x) (Const64 [s])) (Rsh64x64 x (Const64 [63]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m) && s == smagic64(c).s && x.Op != OpConst64 && sdivisibleOK64(c) // result: (Leq64U (RotateLeft64 (Add64 (Mul64 (Const64 [int64(sdivisible64(c).m)]) x) (Const64 [int64(sdivisible64(c).a)]) ) (Const64 [64-sdivisible64(c).k]) ) (Const64 [int64(sdivisible64(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0.AuxInt) if v_1_1.Op != OpSub64 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh64x64 { continue } _ = v_1_1_0.Args[1] v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAdd64 { continue } _ = v_1_1_0_0.Args[1] v_1_1_0_0_0 := v_1_1_0_0.Args[0] v_1_1_0_0_1 := v_1_1_0_0.Args[1] for _i2 := 0; _i2 <= 1; _i2, v_1_1_0_0_0, v_1_1_0_0_1 = _i2+1, v_1_1_0_0_1, v_1_1_0_0_0 { mul := v_1_1_0_0_0 if mul.Op != OpHmul64 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i3 := 0; _i3 <= 1; _i3, mul_0, mul_1 = _i3+1, mul_1, mul_0 { if mul_0.Op != OpConst64 { continue } m := auxIntToInt64(mul_0.AuxInt) if x != mul_1 || x != v_1_1_0_0_1 { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh64x64 { continue } _ = v_1_1_1.Args[1] if x != v_1_1_1.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 63 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int64(smagic64(c).m) && s == smagic64(c).s && x.Op != OpConst64 && sdivisibleOK64(c)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpRotateLeft64, typ.UInt64) v1 := b.NewValue0(v.Pos, OpAdd64, typ.UInt64) v2 := b.NewValue0(v.Pos, OpMul64, typ.UInt64) v3 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v3.AuxInt = int64ToAuxInt(int64(sdivisible64(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v4.AuxInt = int64ToAuxInt(int64(sdivisible64(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v5.AuxInt = int64ToAuxInt(64 - sdivisible64(c).k) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v6.AuxInt = int64ToAuxInt(int64(sdivisible64(c).max)) v.AddArg2(v0, v6) return true } } } } break } // match: (Eq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Eq64 (And64 n (Const64 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh64x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd64 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh64Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh64x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 63 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 63 && kbar == 64-k) { continue } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(1< x (Const64 [y])) (Const64 [y])) // cond: oneBit64(y) // result: (Neq64 (And64 x (Const64 [y])) (Const64 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst64 || v_0_1.Type != t { continue } y := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 || v_1.Type != t || auxIntToInt64(v_1.AuxInt) != y || !(oneBit64(y)) { continue } v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Eq64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } return false } func rewriteValuegeneric_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Eq8 x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (Eq8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Eq8 (Const8 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Eq8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (Eq8 (Mod8u x (Const8 [c])) (Const8 [0])) // cond: x.Op != OpConst8 && udivisibleOK8(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32u (ZeroExt8to32 x) (Const32 [int32(uint8(c))])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod8u { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 || !(x.Op != OpConst8 && udivisibleOK8(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32u, typ.UInt32) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v2.AuxInt = int32ToAuxInt(int32(uint8(c))) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.UInt32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq8 (Mod8 x (Const8 [c])) (Const8 [0])) // cond: x.Op != OpConst8 && sdivisibleOK8(c) && !hasSmallRotate(config) // result: (Eq32 (Mod32 (SignExt8to32 x) (Const32 [int32(c)])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMod8 { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 || !(x.Op != OpConst8 && sdivisibleOK8(c) && !hasSmallRotate(config)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpMod32, typ.Int32) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg2(v1, v2) v3 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v3.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v3) return true } break } // match: (Eq8 x (Mul8 (Const8 [c]) (Trunc32to8 (Rsh32Ux64 mul:(Mul32 (Const32 [m]) (ZeroExt8to32 x)) (Const64 [s]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<8+umagic8(c).m) && s == 8+umagic8(c).s && x.Op != OpConst8 && udivisibleOK8(c) // result: (Leq8U (RotateLeft8 (Mul8 (Const8 [int8(udivisible8(c).m)]) x) (Const8 [int8(8-udivisible8(c).k)]) ) (Const8 [int8(udivisible8(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0.AuxInt) if v_1_1.Op != OpTrunc32to8 { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32Ux64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpZeroExt8to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) if !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(1<<8+umagic8(c).m) && s == 8+umagic8(c).s && x.Op != OpConst8 && udivisibleOK8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v2.AuxInt = int8ToAuxInt(int8(udivisible8(c).m)) v1.AddArg2(v2, x) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int8ToAuxInt(int8(8 - udivisible8(c).k)) v0.AddArg2(v1, v3) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int8ToAuxInt(int8(udivisible8(c).max)) v.AddArg2(v0, v4) return true } } } break } // match: (Eq8 x (Mul8 (Const8 [c]) (Sub8 (Rsh32x64 mul:(Mul32 (Const32 [m]) (SignExt8to32 x)) (Const64 [s])) (Rsh32x64 (SignExt8to32 x) (Const64 [31]))) ) ) // cond: v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic8(c).m) && s == 8+smagic8(c).s && x.Op != OpConst8 && sdivisibleOK8(c) // result: (Leq8U (RotateLeft8 (Add8 (Mul8 (Const8 [int8(sdivisible8(c).m)]) x) (Const8 [int8(sdivisible8(c).a)]) ) (Const8 [int8(8-sdivisible8(c).k)]) ) (Const8 [int8(sdivisible8(c).max)]) ) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0.AuxInt) if v_1_1.Op != OpSub8 { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpRsh32x64 { continue } _ = v_1_1_0.Args[1] mul := v_1_1_0.Args[0] if mul.Op != OpMul32 { continue } _ = mul.Args[1] mul_0 := mul.Args[0] mul_1 := mul.Args[1] for _i2 := 0; _i2 <= 1; _i2, mul_0, mul_1 = _i2+1, mul_1, mul_0 { if mul_0.Op != OpConst32 { continue } m := auxIntToInt32(mul_0.AuxInt) if mul_1.Op != OpSignExt8to32 || x != mul_1.Args[0] { continue } v_1_1_0_1 := v_1_1_0.Args[1] if v_1_1_0_1.Op != OpConst64 { continue } s := auxIntToInt64(v_1_1_0_1.AuxInt) v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpRsh32x64 { continue } _ = v_1_1_1.Args[1] v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpSignExt8to32 || x != v_1_1_1_0.Args[0] { continue } v_1_1_1_1 := v_1_1_1.Args[1] if v_1_1_1_1.Op != OpConst64 || auxIntToInt64(v_1_1_1_1.AuxInt) != 31 || !(v.Block.Func.pass.name != "opt" && mul.Uses == 1 && m == int32(smagic8(c).m) && s == 8+smagic8(c).s && x.Op != OpConst8 && sdivisibleOK8(c)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpRotateLeft8, typ.UInt8) v1 := b.NewValue0(v.Pos, OpAdd8, typ.UInt8) v2 := b.NewValue0(v.Pos, OpMul8, typ.UInt8) v3 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v3.AuxInt = int8ToAuxInt(int8(sdivisible8(c).m)) v2.AddArg2(v3, x) v4 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v4.AuxInt = int8ToAuxInt(int8(sdivisible8(c).a)) v1.AddArg2(v2, v4) v5 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v5.AuxInt = int8ToAuxInt(int8(8 - sdivisible8(c).k)) v0.AddArg2(v1, v5) v6 := b.NewValue0(v.Pos, OpConst8, typ.UInt8) v6.AuxInt = int8ToAuxInt(int8(sdivisible8(c).max)) v.AddArg2(v0, v6) return true } } } break } // match: (Eq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Eq8 (And8 n (Const8 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh8x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh8x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd8 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh8Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh8x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 7 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 7 && kbar == 8-k) { continue } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(1< x (Const8 [y])) (Const8 [y])) // cond: oneBit8(y) // result: (Neq8 (And8 x (Const8 [y])) (Const8 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst8 || v_0_1.Type != t { continue } y := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || v_1.Type != t || auxIntToInt8(v_1.AuxInt) != y || !(oneBit8(y)) { continue } v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EqB (ConstBool [c]) (ConstBool [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool { continue } c := auxIntToBool(v_0.AuxInt) if v_1.Op != OpConstBool { continue } d := auxIntToBool(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (EqB (ConstBool [false]) x) // result: (Not x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != false { continue } x := v_1 v.reset(OpNot) v.AddArg(x) return true } break } // match: (EqB (ConstBool [true]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != true { continue } x := v_1 v.copyOf(x) return true } break } return false } func rewriteValuegeneric_OpEqInter(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqInter x y) // result: (EqPtr (ITab x) (ITab y)) for { x := v_0 y := v_1 v.reset(OpEqPtr) v0 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqPtr x x) // result: (ConstBool [true]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (EqPtr (Addr {x} _) (Addr {y} _)) // result: (ConstBool [x == y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y) return true } break } // match: (EqPtr (Addr {x} _) (OffPtr [o] (Addr {y} _))) // result: (ConstBool [x == y && o == 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o == 0) return true } break } // match: (EqPtr (OffPtr [o1] (Addr {x} _)) (OffPtr [o2] (Addr {y} _))) // result: (ConstBool [x == y && o1 == o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o1 == o2) return true } break } // match: (EqPtr (LocalAddr {x} _ _) (LocalAddr {y} _ _)) // result: (ConstBool [x == y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpLocalAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y) return true } break } // match: (EqPtr (LocalAddr {x} _ _) (OffPtr [o] (LocalAddr {y} _ _))) // result: (ConstBool [x == y && o == 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o == 0) return true } break } // match: (EqPtr (OffPtr [o1] (LocalAddr {x} _ _)) (OffPtr [o2] (LocalAddr {y} _ _))) // result: (ConstBool [x == y && o1 == o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x == y && o1 == o2) return true } break } // match: (EqPtr (OffPtr [o1] p1) p2) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 == 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 == 0) return true } break } // match: (EqPtr (OffPtr [o1] p1) (OffPtr [o2] p2)) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 == o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 == o2) return true } break } // match: (EqPtr (Const32 [c]) (Const32 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (EqPtr (Const64 [c]) (Const64 [d])) // result: (ConstBool [c == d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c == d) return true } break } // match: (EqPtr (LocalAddr _ _) (Addr _)) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (OffPtr (LocalAddr _ _)) (Addr _)) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (LocalAddr _ _) (OffPtr (Addr _))) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (OffPtr (LocalAddr _ _)) (OffPtr (Addr _))) // result: (ConstBool [false]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (EqPtr (AddPtr p1 o1) p2) // cond: isSamePtr(p1, p2) // result: (Not (IsNonNil o1)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddPtr { continue } o1 := v_0.Args[1] p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(o1) v.AddArg(v0) return true } break } // match: (EqPtr (Const32 [0]) p) // result: (Not (IsNonNil p)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(p) v.AddArg(v0) return true } break } // match: (EqPtr (Const64 [0]) p) // result: (Not (IsNonNil p)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(p) v.AddArg(v0) return true } break } // match: (EqPtr (ConstNil) p) // result: (Not (IsNonNil p)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstNil { continue } p := v_1 v.reset(OpNot) v0 := b.NewValue0(v.Pos, OpIsNonNil, typ.Bool) v0.AddArg(p) v.AddArg(v0) return true } break } return false } func rewriteValuegeneric_OpEqSlice(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqSlice x y) // result: (EqPtr (SlicePtr x) (SlicePtr y)) for { x := v_0 y := v_1 v.reset(OpEqPtr) v0 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpIMake(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (IMake _typ (StructMake1 val)) // result: (IMake _typ val) for { _typ := v_0 if v_1.Op != OpStructMake1 { break } val := v_1.Args[0] v.reset(OpIMake) v.AddArg2(_typ, val) return true } // match: (IMake _typ (ArrayMake1 val)) // result: (IMake _typ val) for { _typ := v_0 if v_1.Op != OpArrayMake1 { break } val := v_1.Args[0] v.reset(OpIMake) v.AddArg2(_typ, val) return true } return false } func rewriteValuegeneric_OpInterLECall(v *Value) bool { // match: (InterLECall [argsize] {auxCall} (Load (OffPtr [off] (ITab (IMake (Addr {itab} (SB)) _))) _) ___) // cond: devirtLESym(v, auxCall, itab, off) != nil // result: devirtLECall(v, devirtLESym(v, auxCall, itab, off)) for { if len(v.Args) < 1 { break } auxCall := auxToCall(v.Aux) v_0 := v.Args[0] if v_0.Op != OpLoad { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpOffPtr { break } off := auxIntToInt64(v_0_0.AuxInt) v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpITab { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpIMake { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAddr { break } itab := auxToSym(v_0_0_0_0_0.Aux) v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpSB || !(devirtLESym(v, auxCall, itab, off) != nil) { break } v.copyOf(devirtLECall(v, devirtLESym(v, auxCall, itab, off))) return true } return false } func rewriteValuegeneric_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (IsInBounds (ZeroExt8to32 _) (Const32 [c])) // cond: (1 << 8) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to32 || v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !((1 << 8) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt8to64 _) (Const64 [c])) // cond: (1 << 8) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to64 || v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !((1 << 8) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt16to32 _) (Const32 [c])) // cond: (1 << 16) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to32 || v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !((1 << 16) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt16to64 _) (Const64 [c])) // cond: (1 << 16) <= c // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to64 || v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !((1 << 16) <= c) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (IsInBounds (And8 (Const8 [c]) _) (Const8 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd8 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt8to16 (And8 (Const8 [c]) _)) (Const16 [d])) // cond: 0 <= c && int16(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) if !(0 <= c && int16(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt8to32 (And8 (Const8 [c]) _)) (Const32 [d])) // cond: 0 <= c && int32(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) if !(0 <= c && int32(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt8to64 (And8 (Const8 [c]) _)) (Const64 [d])) // cond: 0 <= c && int64(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt8to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd8 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && int64(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (And16 (Const16 [c]) _) (Const16 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd16 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt16to32 (And16 (Const16 [c]) _)) (Const32 [d])) // cond: 0 <= c && int32(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to32 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) if !(0 <= c && int32(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt16to64 (And16 (Const16 [c]) _)) (Const64 [d])) // cond: 0 <= c && int64(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt16to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd16 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && int64(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (And32 (Const32 [c]) _) (Const32 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd32 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (ZeroExt32to64 (And32 (Const32 [c]) _)) (Const64 [d])) // cond: 0 <= c && int64(c) < d // result: (ConstBool [true]) for { if v_0.Op != OpZeroExt32to64 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAnd32 { break } v_0_0_0 := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0_0, v_0_0_1 = _i0+1, v_0_0_1, v_0_0_0 { if v_0_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && int64(c) < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (And64 (Const64 [c]) _) (Const64 [d])) // cond: 0 <= c && c < d // result: (ConstBool [true]) for { if v_0.Op != OpAnd64 { break } v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) if !(0 <= c && c < d) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (IsInBounds (Const32 [c]) (Const32 [d])) // result: (ConstBool [0 <= c && c < d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(0 <= c && c < d) return true } // match: (IsInBounds (Const64 [c]) (Const64 [d])) // result: (ConstBool [0 <= c && c < d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(0 <= c && c < d) return true } // match: (IsInBounds (Mod32u _ y) y) // result: (ConstBool [true]) for { if v_0.Op != OpMod32u { break } y := v_0.Args[1] if y != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (Mod64u _ y) y) // result: (ConstBool [true]) for { if v_0.Op != OpMod64u { break } y := v_0.Args[1] if y != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (IsInBounds (ZeroExt8to64 (Rsh8Ux64 _ (Const64 [c]))) (Const64 [d])) // cond: 0 < c && c < 8 && 1<= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 || v_1.Op != OpAnd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq16 (Const16 [0]) (Rsh16Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 || v_1.Op != OpRsh16Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq16U (Const16 [c]) (Const16 [d])) // result: (ConstBool [uint16(c) <= uint16(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint16(c) <= uint16(d)) return true } // match: (Leq16U (Const16 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } // match: (Leq32 (Const32 [0]) (And32 _ (Const32 [c]))) // cond: c >= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 || v_1.Op != OpAnd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq32 (Const32 [0]) (Rsh32Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 || v_1.Op != OpRsh32Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } return false } func rewriteValuegeneric_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq32U (Const32 [c]) (Const32 [d])) // result: (ConstBool [uint32(c) <= uint32(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint32(c) <= uint32(d)) return true } // match: (Leq32U (Const32 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } // match: (Leq64 (Const64 [0]) (And64 _ (Const64 [c]))) // cond: c >= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 || v_1.Op != OpAnd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq64 (Const64 [0]) (Rsh64Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 || v_1.Op != OpRsh64Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } return false } func rewriteValuegeneric_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq64U (Const64 [c]) (Const64 [d])) // result: (ConstBool [uint64(c) <= uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint64(c) <= uint64(d)) return true } // match: (Leq64U (Const64 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c <= d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c <= d) return true } // match: (Leq8 (Const8 [0]) (And8 _ (Const8 [c]))) // cond: c >= 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 || v_1.Op != OpAnd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c >= 0) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (Leq8 (Const8 [0]) (Rsh8Ux64 _ (Const64 [c]))) // cond: c > 0 // result: (ConstBool [true]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 || v_1.Op != OpRsh8Ux64 { break } _ = v_1.Args[1] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } c := auxIntToInt64(v_1_1.AuxInt) if !(c > 0) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Leq8U (Const8 [c]) (Const8 [d])) // result: (ConstBool [ uint8(c) <= uint8(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint8(c) <= uint8(d)) return true } // match: (Leq8U (Const8 [0]) _) // result: (ConstBool [true]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } return false } func rewriteValuegeneric_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16 (Const16 [c]) (Const16 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less16 (Const16 [0]) x) // cond: isNonNegative(x) // result: (Neq16 (Const16 [0]) x) for { if v_0.Op != OpConst16 { break } t := v_0.Type if auxIntToInt16(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less16 x (Const16 [1])) // cond: isNonNegative(x) // result: (Eq16 (Const16 [0]) x) for { x := v_0 if v_1.Op != OpConst16 { break } t := v_1.Type if auxIntToInt16(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less16U (Const16 [c]) (Const16 [d])) // result: (ConstBool [uint16(c) < uint16(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint16(c) < uint16(d)) return true } // match: (Less16U _ (Const16 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less32 (Const32 [0]) x) // cond: isNonNegative(x) // result: (Neq32 (Const32 [0]) x) for { if v_0.Op != OpConst32 { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less32 x (Const32 [1])) // cond: isNonNegative(x) // result: (Eq32 (Const32 [0]) x) for { x := v_0 if v_1.Op != OpConst32 { break } t := v_1.Type if auxIntToInt32(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } return false } func rewriteValuegeneric_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less32U (Const32 [c]) (Const32 [d])) // result: (ConstBool [uint32(c) < uint32(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint32(c) < uint32(d)) return true } // match: (Less32U _ (Const32 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less64 (Const64 [0]) x) // cond: isNonNegative(x) // result: (Neq64 (Const64 [0]) x) for { if v_0.Op != OpConst64 { break } t := v_0.Type if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less64 x (Const64 [1])) // cond: isNonNegative(x) // result: (Eq64 (Const64 [0]) x) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } return false } func rewriteValuegeneric_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less64U (Const64 [c]) (Const64 [d])) // result: (ConstBool [uint64(c) < uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint64(c) < uint64(d)) return true } // match: (Less64U _ (Const64 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c < d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c < d) return true } // match: (Less8 (Const8 [0]) x) // cond: isNonNegative(x) // result: (Neq8 (Const8 [0]) x) for { if v_0.Op != OpConst8 { break } t := v_0.Type if auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_1 if !(isNonNegative(x)) { break } v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Less8 x (Const8 [1])) // cond: isNonNegative(x) // result: (Eq8 (Const8 [0]) x) for { x := v_0 if v_1.Op != OpConst8 { break } t := v_1.Type if auxIntToInt8(v_1.AuxInt) != 1 || !(isNonNegative(x)) { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Less8U (Const8 [c]) (Const8 [d])) // result: (ConstBool [ uint8(c) < uint8(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(uint8(c) < uint8(d)) return true } // match: (Less8U _ (Const8 [0])) // result: (ConstBool [false]) for { if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != 0 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } return false } func rewriteValuegeneric_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (Load p1 (Store {t2} p2 x _)) // cond: isSamePtr(p1, p2) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) x := v_1.Args[1] p2 := v_1.Args[0] if !(isSamePtr(p1, p2) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size()) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 x _))) // cond: isSamePtr(p1, p3) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p3, t3.Size(), p2, t2.Size()) // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) x := v_1_2.Args[1] p3 := v_1_2.Args[0] if !(isSamePtr(p1, p3) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p3, t3.Size(), p2, t2.Size())) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 x _)))) // cond: isSamePtr(p1, p4) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p4, t4.Size(), p2, t2.Size()) && disjoint(p4, t4.Size(), p3, t3.Size()) // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) x := v_1_2_2.Args[1] p4 := v_1_2_2.Args[0] if !(isSamePtr(p1, p4) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p4, t4.Size(), p2, t2.Size()) && disjoint(p4, t4.Size(), p3, t3.Size())) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 x _))))) // cond: isSamePtr(p1, p5) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p5, t5.Size(), p2, t2.Size()) && disjoint(p5, t5.Size(), p3, t3.Size()) && disjoint(p5, t5.Size(), p4, t4.Size()) // result: x for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] v_1_2_2_2 := v_1_2_2.Args[2] if v_1_2_2_2.Op != OpStore { break } t5 := auxToType(v_1_2_2_2.Aux) x := v_1_2_2_2.Args[1] p5 := v_1_2_2_2.Args[0] if !(isSamePtr(p1, p5) && t1.Compare(x.Type) == types.CMPeq && t1.Size() == t2.Size() && disjoint(p5, t5.Size(), p2, t2.Size()) && disjoint(p5, t5.Size(), p3, t3.Size()) && disjoint(p5, t5.Size(), p4, t4.Size())) { break } v.copyOf(x) return true } // match: (Load p1 (Store {t2} p2 (Const64 [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x))) // result: (Const64F [math.Float64frombits(uint64(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { break } x := auxIntToInt64(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitFloat(t1) && !math.IsNaN(math.Float64frombits(uint64(x)))) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(math.Float64frombits(uint64(x))) return true } // match: (Load p1 (Store {t2} p2 (Const32 [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x)))) // result: (Const32F [math.Float32frombits(uint32(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { break } x := auxIntToInt32(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitFloat(t1) && !math.IsNaN(float64(math.Float32frombits(uint32(x))))) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(math.Float32frombits(uint32(x))) return true } // match: (Load p1 (Store {t2} p2 (Const64F [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 8 && is64BitInt(t1) // result: (Const64 [int64(math.Float64bits(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64F { break } x := auxIntToFloat64(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 8 && is64BitInt(t1)) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(math.Float64bits(x))) return true } // match: (Load p1 (Store {t2} p2 (Const32F [x]) _)) // cond: isSamePtr(p1,p2) && sizeof(t2) == 4 && is32BitInt(t1) // result: (Const32 [int32(math.Float32bits(x))]) for { t1 := v.Type p1 := v_0 if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[1] p2 := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32F { break } x := auxIntToFloat32(v_1_1.AuxInt) if !(isSamePtr(p1, p2) && sizeof(t2) == 4 && is32BitInt(t1)) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(math.Float32bits(x))) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ mem:(Zero [n] p3 _))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p3) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) // result: @mem.Block (Load (OffPtr [o1] p3) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] mem := v_1.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p3 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p3) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p3) v0.AddArg2(v1, mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ mem:(Zero [n] p4 _)))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p4) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) // result: @mem.Block (Load (OffPtr [o1] p4) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] mem := v_1_2.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p4 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p4) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p4) v0.AddArg2(v1, mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ mem:(Zero [n] p5 _))))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p5) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) // result: @mem.Block (Load (OffPtr [o1] p5) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] mem := v_1_2_2.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p5 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p5) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p5) v0.AddArg2(v1, mem) return true } // match: (Load op:(OffPtr [o1] p1) (Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 _ mem:(Zero [n] p6 _)))))) // cond: o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p6) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) && disjoint(op, t1.Size(), p5, t5.Size()) // result: @mem.Block (Load (OffPtr [o1] p6) mem) for { t1 := v.Type op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] if v_1.Op != OpStore { break } t2 := auxToType(v_1.Aux) _ = v_1.Args[2] p2 := v_1.Args[0] v_1_2 := v_1.Args[2] if v_1_2.Op != OpStore { break } t3 := auxToType(v_1_2.Aux) _ = v_1_2.Args[2] p3 := v_1_2.Args[0] v_1_2_2 := v_1_2.Args[2] if v_1_2_2.Op != OpStore { break } t4 := auxToType(v_1_2_2.Aux) _ = v_1_2_2.Args[2] p4 := v_1_2_2.Args[0] v_1_2_2_2 := v_1_2_2.Args[2] if v_1_2_2_2.Op != OpStore { break } t5 := auxToType(v_1_2_2_2.Aux) _ = v_1_2_2_2.Args[2] p5 := v_1_2_2_2.Args[0] mem := v_1_2_2_2.Args[2] if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p6 := mem.Args[0] if !(o1 >= 0 && o1+t1.Size() <= n && isSamePtr(p1, p6) && fe.CanSSA(t1) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) && disjoint(op, t1.Size(), p5, t5.Size())) { break } b = mem.Block v0 := b.NewValue0(v.Pos, OpLoad, t1) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, op.Type) v1.AuxInt = int64ToAuxInt(o1) v1.AddArg(p6) v0.AddArg2(v1, mem) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: t1.IsBoolean() && isSamePtr(p1, p2) && n >= o + 1 // result: (ConstBool [false]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(t1.IsBoolean() && isSamePtr(p1, p2) && n >= o+1) { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is8BitInt(t1) && isSamePtr(p1, p2) && n >= o + 1 // result: (Const8 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is8BitInt(t1) && isSamePtr(p1, p2) && n >= o+1) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is16BitInt(t1) && isSamePtr(p1, p2) && n >= o + 2 // result: (Const16 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is16BitInt(t1) && isSamePtr(p1, p2) && n >= o+2) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is32BitInt(t1) && isSamePtr(p1, p2) && n >= o + 4 // result: (Const32 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is32BitInt(t1) && isSamePtr(p1, p2) && n >= o+4) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is64BitInt(t1) && isSamePtr(p1, p2) && n >= o + 8 // result: (Const64 [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is64BitInt(t1) && isSamePtr(p1, p2) && n >= o+8) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is32BitFloat(t1) && isSamePtr(p1, p2) && n >= o + 4 // result: (Const32F [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is32BitFloat(t1) && isSamePtr(p1, p2) && n >= o+4) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(0) return true } // match: (Load (OffPtr [o] p1) (Zero [n] p2 _)) // cond: is64BitFloat(t1) && isSamePtr(p1, p2) && n >= o + 8 // result: (Const64F [0]) for { t1 := v.Type if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpZero { break } n := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(is64BitFloat(t1) && isSamePtr(p1, p2) && n >= o+8) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(0) return true } // match: (Load _ _) // cond: t.IsStruct() && t.NumFields() == 0 && fe.CanSSA(t) // result: (StructMake0) for { t := v.Type if !(t.IsStruct() && t.NumFields() == 0 && fe.CanSSA(t)) { break } v.reset(OpStructMake0) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 1 && fe.CanSSA(t) // result: (StructMake1 (Load (OffPtr [0] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 1 && fe.CanSSA(t)) { break } v.reset(OpStructMake1) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v.AddArg(v0) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 2 && fe.CanSSA(t) // result: (StructMake2 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 2 && fe.CanSSA(t)) { break } v.reset(OpStructMake2) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = int64ToAuxInt(t.FieldOff(1)) v3.AddArg(ptr) v2.AddArg2(v3, mem) v.AddArg2(v0, v2) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 3 && fe.CanSSA(t) // result: (StructMake3 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem) (Load (OffPtr [t.FieldOff(2)] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 3 && fe.CanSSA(t)) { break } v.reset(OpStructMake3) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = int64ToAuxInt(t.FieldOff(1)) v3.AddArg(ptr) v2.AddArg2(v3, mem) v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2)) v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v5.AuxInt = int64ToAuxInt(t.FieldOff(2)) v5.AddArg(ptr) v4.AddArg2(v5, mem) v.AddArg3(v0, v2, v4) return true } // match: (Load ptr mem) // cond: t.IsStruct() && t.NumFields() == 4 && fe.CanSSA(t) // result: (StructMake4 (Load (OffPtr [0] ptr) mem) (Load (OffPtr [t.FieldOff(1)] ptr) mem) (Load (OffPtr [t.FieldOff(2)] ptr) mem) (Load (OffPtr [t.FieldOff(3)] ptr) mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsStruct() && t.NumFields() == 4 && fe.CanSSA(t)) { break } v.reset(OpStructMake4) v0 := b.NewValue0(v.Pos, OpLoad, t.FieldType(0)) v1 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v1.AuxInt = int64ToAuxInt(0) v1.AddArg(ptr) v0.AddArg2(v1, mem) v2 := b.NewValue0(v.Pos, OpLoad, t.FieldType(1)) v3 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v3.AuxInt = int64ToAuxInt(t.FieldOff(1)) v3.AddArg(ptr) v2.AddArg2(v3, mem) v4 := b.NewValue0(v.Pos, OpLoad, t.FieldType(2)) v5 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v5.AuxInt = int64ToAuxInt(t.FieldOff(2)) v5.AddArg(ptr) v4.AddArg2(v5, mem) v6 := b.NewValue0(v.Pos, OpLoad, t.FieldType(3)) v7 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo()) v7.AuxInt = int64ToAuxInt(t.FieldOff(3)) v7.AddArg(ptr) v6.AddArg2(v7, mem) v.AddArg4(v0, v2, v4, v6) return true } // match: (Load _ _) // cond: t.IsArray() && t.NumElem() == 0 // result: (ArrayMake0) for { t := v.Type if !(t.IsArray() && t.NumElem() == 0) { break } v.reset(OpArrayMake0) return true } // match: (Load ptr mem) // cond: t.IsArray() && t.NumElem() == 1 && fe.CanSSA(t) // result: (ArrayMake1 (Load ptr mem)) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsArray() && t.NumElem() == 1 && fe.CanSSA(t)) { break } v.reset(OpArrayMake1) v0 := b.NewValue0(v.Pos, OpLoad, t.Elem()) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x16 x (Const16 [c])) // result: (Lsh16x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh16x16 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x32 x (Const32 [c])) // result: (Lsh16x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh16x32 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x64 (Const16 [c]) (Const64 [d])) // result: (Const16 [c << uint64(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c << uint64(d)) return true } // match: (Lsh16x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh16x64 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Lsh16x64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Lsh16x64 (Lsh16x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh16x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh16x64 (Rsh16Ux64 (Lsh16x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh16x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh16x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x8 x (Const8 [c])) // result: (Lsh16x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh16x8 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x16 x (Const16 [c])) // result: (Lsh32x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh32x16 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x32 x (Const32 [c])) // result: (Lsh32x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh32x32 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x64 (Const32 [c]) (Const64 [d])) // result: (Const32 [c << uint64(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c << uint64(d)) return true } // match: (Lsh32x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh32x64 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Lsh32x64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Lsh32x64 (Lsh32x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh32x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh32x64 (Rsh32Ux64 (Lsh32x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh32x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh32x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x8 x (Const8 [c])) // result: (Lsh32x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh32x8 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x16 x (Const16 [c])) // result: (Lsh64x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh64x16 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x32 x (Const32 [c])) // result: (Lsh64x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh64x32 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c << uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c << uint64(d)) return true } // match: (Lsh64x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh64x64 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Lsh64x64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (Const64 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 64) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Lsh64x64 (Lsh64x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh64x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh64x64 (Rsh64Ux64 (Lsh64x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh64x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh64x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x8 x (Const8 [c])) // result: (Lsh64x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh64x8 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x16 x (Const16 [c])) // result: (Lsh8x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Lsh8x16 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x32 x (Const32 [c])) // result: (Lsh8x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Lsh8x32 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x64 (Const8 [c]) (Const64 [d])) // result: (Const8 [c << uint64(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c << uint64(d)) return true } // match: (Lsh8x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Lsh8x64 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Lsh8x64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Lsh8x64 (Lsh8x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Lsh8x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Lsh8x64 (Rsh8Ux64 (Lsh8x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Lsh8x64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpLsh8x64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x8 x (Const8 [c])) // result: (Lsh8x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpLsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Lsh8x8 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod16 (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [c % d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c % d) return true } // match: (Mod16 n (Const16 [c])) // cond: isNonNegative(n) && isPowerOfTwo16(c) // result: (And16 n (Const16 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo16(c)) { break } v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod16 n (Const16 [c])) // cond: c < 0 && c != -1<<15 // result: (Mod16 n (Const16 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(c < 0 && c != -1<<15) { break } v.reset(OpMod16) v.Type = t v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod16 x (Const16 [c])) // cond: x.Op != OpConst16 && (c > 0 || c == -1<<15) // result: (Sub16 x (Mul16 (Div16 x (Const16 [c])) (Const16 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(x.Op != OpConst16 && (c > 0 || c == -1<<15)) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpMul16, t) v1 := b.NewValue0(v.Pos, OpDiv16, t) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod16u (Const16 [c]) (Const16 [d])) // cond: d != 0 // result: (Const16 [int16(uint16(c) % uint16(d))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint16(c) % uint16(d))) return true } // match: (Mod16u n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (And16 n (Const16 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { break } v.reset(OpAnd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod16u x (Const16 [c])) // cond: x.Op != OpConst16 && c > 0 && umagicOK16(c) // result: (Sub16 x (Mul16 (Div16u x (Const16 [c])) (Const16 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(x.Op != OpConst16 && c > 0 && umagicOK16(c)) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpMul16, t) v1 := b.NewValue0(v.Pos, OpDiv16u, t) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod32 (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [c % d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c % d) return true } // match: (Mod32 n (Const32 [c])) // cond: isNonNegative(n) && isPowerOfTwo32(c) // result: (And32 n (Const32 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo32(c)) { break } v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod32 n (Const32 [c])) // cond: c < 0 && c != -1<<31 // result: (Mod32 n (Const32 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(c < 0 && c != -1<<31) { break } v.reset(OpMod32) v.Type = t v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod32 x (Const32 [c])) // cond: x.Op != OpConst32 && (c > 0 || c == -1<<31) // result: (Sub32 x (Mul32 (Div32 x (Const32 [c])) (Const32 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(x.Op != OpConst32 && (c > 0 || c == -1<<31)) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpMul32, t) v1 := b.NewValue0(v.Pos, OpDiv32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod32u (Const32 [c]) (Const32 [d])) // cond: d != 0 // result: (Const32 [int32(uint32(c) % uint32(d))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint32(c) % uint32(d))) return true } // match: (Mod32u n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (And32 n (Const32 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { break } v.reset(OpAnd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod32u x (Const32 [c])) // cond: x.Op != OpConst32 && c > 0 && umagicOK32(c) // result: (Sub32 x (Mul32 (Div32u x (Const32 [c])) (Const32 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(x.Op != OpConst32 && c > 0 && umagicOK32(c)) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpMul32, t) v1 := b.NewValue0(v.Pos, OpDiv32u, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod64 (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [c % d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c % d) return true } // match: (Mod64 n (Const64 [c])) // cond: isNonNegative(n) && isPowerOfTwo64(c) // result: (And64 n (Const64 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo64(c)) { break } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod64 n (Const64 [-1<<63])) // cond: isNonNegative(n) // result: n for { n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 || !(isNonNegative(n)) { break } v.copyOf(n) return true } // match: (Mod64 n (Const64 [c])) // cond: c < 0 && c != -1<<63 // result: (Mod64 n (Const64 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c < 0 && c != -1<<63) { break } v.reset(OpMod64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod64 x (Const64 [c])) // cond: x.Op != OpConst64 && (c > 0 || c == -1<<63) // result: (Sub64 x (Mul64 (Div64 x (Const64 [c])) (Const64 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(x.Op != OpConst64 && (c > 0 || c == -1<<63)) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpMul64, t) v1 := b.NewValue0(v.Pos, OpDiv64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod64u (Const64 [c]) (Const64 [d])) // cond: d != 0 // result: (Const64 [int64(uint64(c) % uint64(d))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint64(c) % uint64(d))) return true } // match: (Mod64u n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (And64 n (Const64 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod64u n (Const64 [-1<<63])) // result: (And64 n (Const64 [1<<63-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != -1<<63 { break } v.reset(OpAnd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(1<<63 - 1) v.AddArg2(n, v0) return true } // match: (Mod64u x (Const64 [c])) // cond: x.Op != OpConst64 && c > 0 && umagicOK64(c) // result: (Sub64 x (Mul64 (Div64u x (Const64 [c])) (Const64 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(x.Op != OpConst64 && c > 0 && umagicOK64(c)) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpMul64, t) v1 := b.NewValue0(v.Pos, OpDiv64u, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod8 (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [c % d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c % d) return true } // match: (Mod8 n (Const8 [c])) // cond: isNonNegative(n) && isPowerOfTwo8(c) // result: (And8 n (Const8 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isNonNegative(n) && isPowerOfTwo8(c)) { break } v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod8 n (Const8 [c])) // cond: c < 0 && c != -1<<7 // result: (Mod8 n (Const8 [-c])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(c < 0 && c != -1<<7) { break } v.reset(OpMod8) v.Type = t v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(-c) v.AddArg2(n, v0) return true } // match: (Mod8 x (Const8 [c])) // cond: x.Op != OpConst8 && (c > 0 || c == -1<<7) // result: (Sub8 x (Mul8 (Div8 x (Const8 [c])) (Const8 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(x.Op != OpConst8 && (c > 0 || c == -1<<7)) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpMul8, t) v1 := b.NewValue0(v.Pos, OpDiv8, t) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Mod8u (Const8 [c]) (Const8 [d])) // cond: d != 0 // result: (Const8 [int8(uint8(c) % uint8(d))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) if !(d != 0) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(uint8(c) % uint8(d))) return true } // match: (Mod8u n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (And8 n (Const8 [c-1])) for { t := v.Type n := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { break } v.reset(OpAnd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - 1) v.AddArg2(n, v0) return true } // match: (Mod8u x (Const8 [c])) // cond: x.Op != OpConst8 && c > 0 && umagicOK8( c) // result: (Sub8 x (Mul8 (Div8u x (Const8 [c])) (Const8 [c]))) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(x.Op != OpConst8 && c > 0 && umagicOK8(c)) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpMul8, t) v1 := b.NewValue0(v.Pos, OpDiv8u, t) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(c) v1.AddArg2(x, v2) v0.AddArg2(v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Move {t} [n] dst1 src mem:(Zero {t} [n] dst2 _)) // cond: isSamePtr(src, dst2) // result: (Zero {t} [n] dst1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src := v_1 mem := v_2 if mem.Op != OpZero || auxIntToInt64(mem.AuxInt) != n || auxToType(mem.Aux) != t { break } dst2 := mem.Args[0] if !(isSamePtr(src, dst2)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst1, mem) return true } // match: (Move {t} [n] dst1 src mem:(VarDef (Zero {t} [n] dst0 _))) // cond: isSamePtr(src, dst0) // result: (Zero {t} [n] dst1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpZero || auxIntToInt64(mem_0.AuxInt) != n || auxToType(mem_0.Aux) != t { break } dst0 := mem_0.Args[0] if !(isSamePtr(src, dst0)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst1, mem) return true } // match: (Move {t} [n] dst (Addr {sym} (SB)) mem) // cond: symIsROZero(sym) // result: (Zero {t} [n] dst mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst := v_0 if v_1.Op != OpAddr { break } sym := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } mem := v_2 if !(symIsROZero(sym)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst, mem) return true } // match: (Move {t1} [n] dst1 src1 store:(Store {t2} op:(OffPtr [o2] dst2) _ mem)) // cond: isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2 + t2.Size() && disjoint(src1, n, op, t2.Size()) && clobber(store) // result: (Move {t1} [n] dst1 src1 mem) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst1 := v_0 src1 := v_1 store := v_2 if store.Op != OpStore { break } t2 := auxToType(store.Aux) mem := store.Args[2] op := store.Args[0] if op.Op != OpOffPtr { break } o2 := auxIntToInt64(op.AuxInt) dst2 := op.Args[0] if !(isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2+t2.Size() && disjoint(src1, n, op, t2.Size()) && clobber(store)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t1) v.AddArg3(dst1, src1, mem) return true } // match: (Move {t} [n] dst1 src1 move:(Move {t} [n] dst2 _ mem)) // cond: move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move) // result: (Move {t} [n] dst1 src1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 move := v_2 if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg3(dst1, src1, mem) return true } // match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem))) // cond: move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move, vardef) // result: (Move {t} [n] dst1 src1 (VarDef {x} mem)) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 vardef := v_2 if vardef.Op != OpVarDef { break } x := auxToSym(vardef.Aux) move := vardef.Args[0] if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move, vardef)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg3(dst1, src1, v0) return true } // match: (Move {t} [n] dst1 src1 zero:(Zero {t} [n] dst2 mem)) // cond: zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero) // result: (Move {t} [n] dst1 src1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 zero := v_2 if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != n || auxToType(zero.Aux) != t { break } mem := zero.Args[1] dst2 := zero.Args[0] if !(zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg3(dst1, src1, mem) return true } // match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} zero:(Zero {t} [n] dst2 mem))) // cond: zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero, vardef) // result: (Move {t} [n] dst1 src1 (VarDef {x} mem)) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 src1 := v_1 vardef := v_2 if vardef.Op != OpVarDef { break } x := auxToSym(vardef.Aux) zero := vardef.Args[0] if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != n || auxToType(zero.Aux) != t { break } mem := zero.Args[1] dst2 := zero.Args[0] if !(zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero, vardef)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg3(dst1, src1, v0) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [0] p3) d2 _))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size() + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [0] dst) d2 mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) d2 := mem_2.Args[1] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type if auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size()+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(0) v2.AddArg(dst) v1.AddArg3(v2, d2, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [0] p4) d3 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [0] dst) d3 mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) d3 := mem_2_2.Args[1] op4 := mem_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type if auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(0) v4.AddArg(dst) v3.AddArg3(v4, d3, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [o4] p4) d3 (Store {t5} op5:(OffPtr [0] p5) d4 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [0] dst) d4 mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] op3 := mem_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] op4 := mem_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type o4 := auxIntToInt64(op4.AuxInt) p4 := op4.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpStore { break } t5 := auxToType(mem_2_2_2.Aux) d4 := mem_2_2_2.Args[1] op5 := mem_2_2_2.Args[0] if op5.Op != OpOffPtr { break } tt5 := op5.Type if auxIntToInt64(op5.AuxInt) != 0 { break } p5 := op5.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(0) v6.AddArg(dst) v5.AddArg3(v6, d4, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [0] p3) d2 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size() + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [0] dst) d2 mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) d2 := mem_0_2.Args[1] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type if auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size()+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(0) v2.AddArg(dst) v1.AddArg3(v2, d2, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [0] p4) d3 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [0] dst) d3 mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) d3 := mem_0_2_2.Args[1] op4 := mem_0_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type if auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(0) v4.AddArg(dst) v3.AddArg3(v4, d3, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Store {t3} op3:(OffPtr [o3] p3) d2 (Store {t4} op4:(OffPtr [o4] p4) d3 (Store {t5} op5:(OffPtr [0] p5) d4 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [0] dst) d4 mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] op3 := mem_0_2.Args[0] if op3.Op != OpOffPtr { break } tt3 := op3.Type o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) _ = mem_0_2_2.Args[2] op4 := mem_0_2_2.Args[0] if op4.Op != OpOffPtr { break } tt4 := op4.Type o4 := auxIntToInt64(op4.AuxInt) p4 := op4.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpStore { break } t5 := auxToType(mem_0_2_2_2.Aux) d4 := mem_0_2_2_2.Args[1] op5 := mem_0_2_2_2.Args[0] if op5.Op != OpOffPtr { break } tt5 := op5.Type if auxIntToInt64(op5.AuxInt) != 0 { break } p5 := op5.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(0) v6.AddArg(dst) v5.AddArg3(v6, d4, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr [o2] p2) d1 (Zero {t3} [n] p3 _))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2 + t2.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Zero {t1} [n] dst mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] op2 := mem.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpZero || auxIntToInt64(mem_2.AuxInt) != n { break } t3 := auxToType(mem_2.Aux) p3 := mem_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2+t2.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(n) v1.Aux = typeToAux(t1) v1.AddArg2(dst, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Zero {t4} [n] p4 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + t2.Size() && n >= o3 + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Zero {t1} [n] dst mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := auxIntToInt64(mem_0.AuxInt) p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := auxIntToInt64(mem_2_0.AuxInt) p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpZero || auxIntToInt64(mem_2_2.AuxInt) != n { break } t4 := auxToType(mem_2_2.Aux) p4 := mem_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2+t2.Size() && n >= o3+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v3.AuxInt = int64ToAuxInt(n) v3.Aux = typeToAux(t1) v3.AddArg2(dst, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Zero {t5} [n] p5 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Zero {t1} [n] dst mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := auxIntToInt64(mem_0.AuxInt) p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := auxIntToInt64(mem_2_0.AuxInt) p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] mem_2_2_0 := mem_2_2.Args[0] if mem_2_2_0.Op != OpOffPtr { break } tt4 := mem_2_2_0.Type o4 := auxIntToInt64(mem_2_2_0.AuxInt) p4 := mem_2_2_0.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpZero || auxIntToInt64(mem_2_2_2.AuxInt) != n { break } t5 := auxToType(mem_2_2_2.Aux) p5 := mem_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v5.AuxInt = int64ToAuxInt(n) v5.Aux = typeToAux(t1) v5.AddArg2(dst, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Store {t5} (OffPtr [o5] p5) d4 (Zero {t6} [n] p6 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() && n >= o5 + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [o5] dst) d4 (Zero {t1} [n] dst mem))))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] mem_0 := mem.Args[0] if mem_0.Op != OpOffPtr { break } tt2 := mem_0.Type o2 := auxIntToInt64(mem_0.AuxInt) p2 := mem_0.Args[0] d1 := mem.Args[1] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] mem_2_0 := mem_2.Args[0] if mem_2_0.Op != OpOffPtr { break } tt3 := mem_2_0.Type o3 := auxIntToInt64(mem_2_0.AuxInt) p3 := mem_2_0.Args[0] d2 := mem_2.Args[1] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] mem_2_2_0 := mem_2_2.Args[0] if mem_2_2_0.Op != OpOffPtr { break } tt4 := mem_2_2_0.Type o4 := auxIntToInt64(mem_2_2_0.AuxInt) p4 := mem_2_2_0.Args[0] d3 := mem_2_2.Args[1] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpStore { break } t5 := auxToType(mem_2_2_2.Aux) _ = mem_2_2_2.Args[2] mem_2_2_2_0 := mem_2_2_2.Args[0] if mem_2_2_2_0.Op != OpOffPtr { break } tt5 := mem_2_2_2_0.Type o5 := auxIntToInt64(mem_2_2_2_0.AuxInt) p5 := mem_2_2_2_0.Args[0] d4 := mem_2_2_2.Args[1] mem_2_2_2_2 := mem_2_2_2.Args[2] if mem_2_2_2_2.Op != OpZero || auxIntToInt64(mem_2_2_2_2.AuxInt) != n { break } t6 := auxToType(mem_2_2_2_2.Aux) p6 := mem_2_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size() && n >= o5+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(o5) v6.AddArg(dst) v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v7.AuxInt = int64ToAuxInt(n) v7.Aux = typeToAux(t1) v7.AddArg2(dst, mem) v5.AddArg3(v6, d4, v7) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr [o2] p2) d1 (Zero {t3} [n] p3 _)))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2 + t2.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Zero {t1} [n] dst mem)) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] op2 := mem_0.Args[0] if op2.Op != OpOffPtr { break } tt2 := op2.Type o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpZero || auxIntToInt64(mem_0_2.AuxInt) != n { break } t3 := auxToType(mem_0_2.Aux) p3 := mem_0_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2+t2.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(n) v1.Aux = typeToAux(t1) v1.AddArg2(dst, mem) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Zero {t4} [n] p4 _))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + t2.Size() && n >= o3 + t3.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Zero {t1} [n] dst mem))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := auxIntToInt64(mem_0_0.AuxInt) p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := auxIntToInt64(mem_0_2_0.AuxInt) p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2.AuxInt) != n { break } t4 := auxToType(mem_0_2_2.Aux) p4 := mem_0_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2+t2.Size() && n >= o3+t3.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v3.AuxInt = int64ToAuxInt(n) v3.Aux = typeToAux(t1) v3.AddArg2(dst, mem) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Zero {t5} [n] p5 _)))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Zero {t1} [n] dst mem)))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := auxIntToInt64(mem_0_0.AuxInt) p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := auxIntToInt64(mem_0_2_0.AuxInt) p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) _ = mem_0_2_2.Args[2] mem_0_2_2_0 := mem_0_2_2.Args[0] if mem_0_2_2_0.Op != OpOffPtr { break } tt4 := mem_0_2_2_0.Type o4 := auxIntToInt64(mem_0_2_2_0.AuxInt) p4 := mem_0_2_2_0.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2_2.AuxInt) != n { break } t5 := auxToType(mem_0_2_2_2.Aux) p5 := mem_0_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v5.AuxInt = int64ToAuxInt(n) v5.Aux = typeToAux(t1) v5.AddArg2(dst, mem) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr [o2] p2) d1 (Store {t3} (OffPtr [o3] p3) d2 (Store {t4} (OffPtr [o4] p4) d3 (Store {t5} (OffPtr [o5] p5) d4 (Zero {t6} [n] p6 _))))))) // cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() && n >= o5 + t5.Size() // result: (Store {t2} (OffPtr [o2] dst) d1 (Store {t3} (OffPtr [o3] dst) d2 (Store {t4} (OffPtr [o4] dst) d3 (Store {t5} (OffPtr [o5] dst) d4 (Zero {t1} [n] dst mem))))) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 p1 := v_1 mem := v_2 if mem.Op != OpVarDef { break } mem_0 := mem.Args[0] if mem_0.Op != OpStore { break } t2 := auxToType(mem_0.Aux) _ = mem_0.Args[2] mem_0_0 := mem_0.Args[0] if mem_0_0.Op != OpOffPtr { break } tt2 := mem_0_0.Type o2 := auxIntToInt64(mem_0_0.AuxInt) p2 := mem_0_0.Args[0] d1 := mem_0.Args[1] mem_0_2 := mem_0.Args[2] if mem_0_2.Op != OpStore { break } t3 := auxToType(mem_0_2.Aux) _ = mem_0_2.Args[2] mem_0_2_0 := mem_0_2.Args[0] if mem_0_2_0.Op != OpOffPtr { break } tt3 := mem_0_2_0.Type o3 := auxIntToInt64(mem_0_2_0.AuxInt) p3 := mem_0_2_0.Args[0] d2 := mem_0_2.Args[1] mem_0_2_2 := mem_0_2.Args[2] if mem_0_2_2.Op != OpStore { break } t4 := auxToType(mem_0_2_2.Aux) _ = mem_0_2_2.Args[2] mem_0_2_2_0 := mem_0_2_2.Args[0] if mem_0_2_2_0.Op != OpOffPtr { break } tt4 := mem_0_2_2_0.Type o4 := auxIntToInt64(mem_0_2_2_0.AuxInt) p4 := mem_0_2_2_0.Args[0] d3 := mem_0_2_2.Args[1] mem_0_2_2_2 := mem_0_2_2.Args[2] if mem_0_2_2_2.Op != OpStore { break } t5 := auxToType(mem_0_2_2_2.Aux) _ = mem_0_2_2_2.Args[2] mem_0_2_2_2_0 := mem_0_2_2_2.Args[0] if mem_0_2_2_2_0.Op != OpOffPtr { break } tt5 := mem_0_2_2_2_0.Type o5 := auxIntToInt64(mem_0_2_2_2_0.AuxInt) p5 := mem_0_2_2_2_0.Args[0] d4 := mem_0_2_2_2.Args[1] mem_0_2_2_2_2 := mem_0_2_2_2.Args[2] if mem_0_2_2_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2_2_2.AuxInt) != n { break } t6 := auxToType(mem_0_2_2_2_2.Aux) p6 := mem_0_2_2_2_2.Args[0] if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size() && n >= o5+t5.Size()) { break } v.reset(OpStore) v.Aux = typeToAux(t2) v0 := b.NewValue0(v.Pos, OpOffPtr, tt2) v0.AuxInt = int64ToAuxInt(o2) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpOffPtr, tt3) v2.AuxInt = int64ToAuxInt(o3) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t4) v4 := b.NewValue0(v.Pos, OpOffPtr, tt4) v4.AuxInt = int64ToAuxInt(o4) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t5) v6 := b.NewValue0(v.Pos, OpOffPtr, tt5) v6.AuxInt = int64ToAuxInt(o5) v6.AddArg(dst) v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v7.AuxInt = int64ToAuxInt(n) v7.Aux = typeToAux(t1) v7.AddArg2(dst, mem) v5.AddArg3(v6, d4, v7) v3.AddArg3(v4, d3, v5) v1.AddArg3(v2, d2, v3) v.AddArg3(v0, d1, v1) return true } // match: (Move {t1} [s] dst tmp1 midmem:(Move {t2} [s] tmp2 src _)) // cond: t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config)) // result: (Move {t1} [s] dst src midmem) for { s := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 tmp1 := v_1 midmem := v_2 if midmem.Op != OpMove || auxIntToInt64(midmem.AuxInt) != s { break } t2 := auxToType(midmem.Aux) src := midmem.Args[1] tmp2 := midmem.Args[0] if !(t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s) v.Aux = typeToAux(t1) v.AddArg3(dst, src, midmem) return true } // match: (Move {t1} [s] dst tmp1 midmem:(VarDef (Move {t2} [s] tmp2 src _))) // cond: t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config)) // result: (Move {t1} [s] dst src midmem) for { s := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) dst := v_0 tmp1 := v_1 midmem := v_2 if midmem.Op != OpVarDef { break } midmem_0 := midmem.Args[0] if midmem_0.Op != OpMove || auxIntToInt64(midmem_0.AuxInt) != s { break } t2 := auxToType(midmem_0.Aux) src := midmem_0.Args[1] tmp2 := midmem_0.Args[0] if !(t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s) v.Aux = typeToAux(t1) v.AddArg3(dst, src, midmem) return true } // match: (Move dst src mem) // cond: isSamePtr(dst, src) // result: mem for { dst := v_0 src := v_1 mem := v_2 if !(isSamePtr(dst, src)) { break } v.copyOf(mem) return true } return false } func rewriteValuegeneric_OpMul16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c * d) return true } break } // match: (Mul16 (Const16 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul16 (Const16 [-1]) x) // result: (Neg16 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg16) v.AddArg(x) return true } break } // match: (Mul16 n (Const16 [c])) // cond: isPowerOfTwo16(c) // result: (Lsh16x64 n (Const64 [log16(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1.AuxInt) if !(isPowerOfTwo16(c)) { continue } v.reset(OpLsh16x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log16(c)) v.AddArg2(n, v0) return true } break } // match: (Mul16 n (Const16 [c])) // cond: t.IsSigned() && isPowerOfTwo16(-c) // result: (Neg16 (Lsh16x64 n (Const64 [log16(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo16(-c)) { continue } v.reset(OpNeg16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log16(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul16 (Const16 [0]) _) // result: (Const16 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } break } // match: (Mul16 (Mul16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Mul16 i (Mul16 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpMul16, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul16 (Const16 [c]) (Mul16 (Const16 [d]) x)) // result: (Mul16 (Const16 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpMul32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c * d) return true } break } // match: (Mul32 (Const32 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul32 (Const32 [-1]) x) // result: (Neg32 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg32) v.AddArg(x) return true } break } // match: (Mul32 n (Const32 [c])) // cond: isPowerOfTwo32(c) // result: (Lsh32x64 n (Const64 [log32(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1.AuxInt) if !(isPowerOfTwo32(c)) { continue } v.reset(OpLsh32x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log32(c)) v.AddArg2(n, v0) return true } break } // match: (Mul32 n (Const32 [c])) // cond: t.IsSigned() && isPowerOfTwo32(-c) // result: (Neg32 (Lsh32x64 n (Const64 [log32(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo32(-c)) { continue } v.reset(OpNeg32) v0 := b.NewValue0(v.Pos, OpLsh32x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log32(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Add32 (Const32 [c*d]) (Mul32 (Const32 [c]) x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 || v_1.Type != t { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c * d) v1 := b.NewValue0(v.Pos, OpMul32, t) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(c) v1.AddArg2(v2, x) v.AddArg2(v0, v1) return true } } break } // match: (Mul32 (Const32 [0]) _) // result: (Const32 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } // match: (Mul32 (Mul32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Mul32 i (Mul32 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpMul32, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul32 (Const32 [c]) (Mul32 (Const32 [d]) x)) // result: (Mul32 (Const32 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpMul32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mul32F (Const32F [c]) (Const32F [d])) // cond: c*d == c*d // result: (Const32F [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) if !(c*d == c*d) { continue } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c * d) return true } break } // match: (Mul32F x (Const32F [1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst32F || auxIntToFloat32(v_1.AuxInt) != 1 { continue } v.copyOf(x) return true } break } // match: (Mul32F x (Const32F [-1])) // result: (Neg32F x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst32F || auxIntToFloat32(v_1.AuxInt) != -1 { continue } v.reset(OpNeg32F) v.AddArg(x) return true } break } // match: (Mul32F x (Const32F [2])) // result: (Add32F x x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst32F || auxIntToFloat32(v_1.AuxInt) != 2 { continue } v.reset(OpAdd32F) v.AddArg2(x, x) return true } break } return false } func rewriteValuegeneric_OpMul64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c * d) return true } break } // match: (Mul64 (Const64 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul64 (Const64 [-1]) x) // result: (Neg64 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg64) v.AddArg(x) return true } break } // match: (Mul64 n (Const64 [c])) // cond: isPowerOfTwo64(c) // result: (Lsh64x64 n (Const64 [log64(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpLsh64x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(n, v0) return true } break } // match: (Mul64 n (Const64 [c])) // cond: t.IsSigned() && isPowerOfTwo64(-c) // result: (Neg64 (Lsh64x64 n (Const64 [log64(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo64(-c)) { continue } v.reset(OpNeg64) v0 := b.NewValue0(v.Pos, OpLsh64x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log64(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Add64 (Const64 [c*d]) (Mul64 (Const64 [c]) x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 || v_1.Type != t { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c * d) v1 := b.NewValue0(v.Pos, OpMul64, t) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(c) v1.AddArg2(v2, x) v.AddArg2(v0, v1) return true } } break } // match: (Mul64 (Const64 [0]) _) // result: (Const64 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (Mul64 (Mul64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Mul64 i (Mul64 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpMul64, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul64 (Const64 [c]) (Mul64 (Const64 [d]) x)) // result: (Mul64 (Const64 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpMul64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mul64F (Const64F [c]) (Const64F [d])) // cond: c*d == c*d // result: (Const64F [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) if !(c*d == c*d) { continue } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c * d) return true } break } // match: (Mul64F x (Const64F [1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst64F || auxIntToFloat64(v_1.AuxInt) != 1 { continue } v.copyOf(x) return true } break } // match: (Mul64F x (Const64F [-1])) // result: (Neg64F x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst64F || auxIntToFloat64(v_1.AuxInt) != -1 { continue } v.reset(OpNeg64F) v.AddArg(x) return true } break } // match: (Mul64F x (Const64F [2])) // result: (Add64F x x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpConst64F || auxIntToFloat64(v_1.AuxInt) != 2 { continue } v.reset(OpAdd64F) v.AddArg2(x, x) return true } break } return false } func rewriteValuegeneric_OpMul8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mul8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c * d) return true } break } // match: (Mul8 (Const8 [1]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 1 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Mul8 (Const8 [-1]) x) // result: (Neg8 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpNeg8) v.AddArg(x) return true } break } // match: (Mul8 n (Const8 [c])) // cond: isPowerOfTwo8(c) // result: (Lsh8x64 n (Const64 [log8(c)])) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1.AuxInt) if !(isPowerOfTwo8(c)) { continue } v.reset(OpLsh8x64) v.Type = t v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(log8(c)) v.AddArg2(n, v0) return true } break } // match: (Mul8 n (Const8 [c])) // cond: t.IsSigned() && isPowerOfTwo8(-c) // result: (Neg8 (Lsh8x64 n (Const64 [log8(-c)]))) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1.AuxInt) if !(t.IsSigned() && isPowerOfTwo8(-c)) { continue } v.reset(OpNeg8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v1 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v1.AuxInt = int64ToAuxInt(log8(-c)) v0.AddArg2(n, v1) v.AddArg(v0) return true } break } // match: (Mul8 (Const8 [0]) _) // result: (Const8 [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } break } // match: (Mul8 (Mul8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Mul8 i (Mul8 x z)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpMul8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpMul8, t) v0.AddArg2(x, z) v.AddArg2(i, v0) return true } } break } // match: (Mul8 (Const8 [c]) (Mul8 (Const8 [d]) x)) // result: (Mul8 (Const8 [c*d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c * d) v.AddArg2(v0, x) return true } } break } return false } func rewriteValuegeneric_OpNeg16(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg16 (Const16 [c])) // result: (Const16 [-c]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-c) return true } // match: (Neg16 (Sub16 x y)) // result: (Sub16 y x) for { if v_0.Op != OpSub16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub16) v.AddArg2(y, x) return true } // match: (Neg16 (Neg16 x)) // result: x for { if v_0.Op != OpNeg16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg16 (Com16 x)) // result: (Add16 (Const16 [1]) x) for { t := v.Type if v_0.Op != OpCom16 { break } x := v_0.Args[0] v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeg32(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg32 (Const32 [c])) // result: (Const32 [-c]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-c) return true } // match: (Neg32 (Sub32 x y)) // result: (Sub32 y x) for { if v_0.Op != OpSub32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub32) v.AddArg2(y, x) return true } // match: (Neg32 (Neg32 x)) // result: x for { if v_0.Op != OpNeg32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg32 (Com32 x)) // result: (Add32 (Const32 [1]) x) for { t := v.Type if v_0.Op != OpCom32 { break } x := v_0.Args[0] v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeg32F(v *Value) bool { v_0 := v.Args[0] // match: (Neg32F (Const32F [c])) // cond: c != 0 // result: (Const32F [-c]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if !(c != 0) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(-c) return true } return false } func rewriteValuegeneric_OpNeg64(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg64 (Const64 [c])) // result: (Const64 [-c]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-c) return true } // match: (Neg64 (Sub64 x y)) // result: (Sub64 y x) for { if v_0.Op != OpSub64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub64) v.AddArg2(y, x) return true } // match: (Neg64 (Neg64 x)) // result: x for { if v_0.Op != OpNeg64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg64 (Com64 x)) // result: (Add64 (Const64 [1]) x) for { t := v.Type if v_0.Op != OpCom64 { break } x := v_0.Args[0] v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeg64F(v *Value) bool { v_0 := v.Args[0] // match: (Neg64F (Const64F [c])) // cond: c != 0 // result: (Const64F [-c]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if !(c != 0) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(-c) return true } return false } func rewriteValuegeneric_OpNeg8(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Neg8 (Const8 [c])) // result: (Const8 [-c]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-c) return true } // match: (Neg8 (Sub8 x y)) // result: (Sub8 y x) for { if v_0.Op != OpSub8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSub8) v.AddArg2(y, x) return true } // match: (Neg8 (Neg8 x)) // result: x for { if v_0.Op != OpNeg8 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Neg8 (Com8 x)) // result: (Add8 (Const8 [1]) x) for { t := v.Type if v_0.Op != OpCom8 { break } x := v_0.Args[0] v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(1) v.AddArg2(v0, x) return true } return false } func rewriteValuegeneric_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq16 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Neq16 (Const16 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq16 (Const16 [c]) (Const16 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq16 n (Lsh16x64 (Rsh16x64 (Add16 n (Rsh16Ux64 (Rsh16x64 n (Const64 [15])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 15 && kbar == 16 - k // result: (Neq16 (And16 n (Const16 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh16x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh16x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd16 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh16Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh16x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 15 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 15 && kbar == 16-k) { continue } v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(1< x (Const16 [y])) (Const16 [y])) // cond: oneBit16(y) // result: (Eq16 (And16 x (Const16 [y])) (Const16 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst16 || v_0_1.Type != t { continue } y := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 || v_1.Type != t || auxIntToInt16(v_1.AuxInt) != y || !(oneBit16(y)) { continue } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpAnd16, t) v1 := b.NewValue0(v.Pos, OpConst16, t) v1.AuxInt = int16ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst16, t) v2.AuxInt = int16ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq32 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Neq32 (Const32 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq32 (Const32 [c]) (Const32 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq32 n (Lsh32x64 (Rsh32x64 (Add32 n (Rsh32Ux64 (Rsh32x64 n (Const64 [31])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 31 && kbar == 32 - k // result: (Neq32 (And32 n (Const32 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh32x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh32x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd32 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh32Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh32x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 31 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 31 && kbar == 32-k) { continue } v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(1< x (Const32 [y])) (Const32 [y])) // cond: oneBit32(y) // result: (Eq32 (And32 x (Const32 [y])) (Const32 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst32 || v_0_1.Type != t { continue } y := auxIntToInt32(v_0_1.AuxInt) if v_1.Op != OpConst32 || v_1.Type != t || auxIntToInt32(v_1.AuxInt) != y || !(oneBit32(y)) { continue } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpAnd32, t) v1 := b.NewValue0(v.Pos, OpConst32, t) v1.AuxInt = int32ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst32, t) v2.AuxInt = int32ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Neq32F (Const32F [c]) (Const32F [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32F { continue } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { continue } d := auxIntToFloat32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } return false } func rewriteValuegeneric_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq64 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Neq64 (Const64 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq64 (Const64 [c]) (Const64 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq64 n (Lsh64x64 (Rsh64x64 (Add64 n (Rsh64Ux64 (Rsh64x64 n (Const64 [63])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 63 && kbar == 64 - k // result: (Neq64 (And64 n (Const64 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh64x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh64x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd64 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh64Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh64x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 63 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 63 && kbar == 64-k) { continue } v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(1< x (Const64 [y])) (Const64 [y])) // cond: oneBit64(y) // result: (Eq64 (And64 x (Const64 [y])) (Const64 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst64 || v_0_1.Type != t { continue } y := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 || v_1.Type != t || auxIntToInt64(v_1.AuxInt) != y || !(oneBit64(y)) { continue } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpAnd64, t) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Neq64F (Const64F [c]) (Const64F [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64F { continue } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { continue } d := auxIntToFloat64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } return false } func rewriteValuegeneric_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq8 x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (Neq8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Neq8 (Const8 [c-d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } } break } // match: (Neq8 (Const8 [c]) (Const8 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (Neq8 n (Lsh8x64 (Rsh8x64 (Add8 n (Rsh8Ux64 (Rsh8x64 n (Const64 [ 7])) (Const64 [kbar]))) (Const64 [k])) (Const64 [k])) ) // cond: k > 0 && k < 7 && kbar == 8 - k // result: (Neq8 (And8 n (Const8 [1< [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { n := v_0 if v_1.Op != OpLsh8x64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpRsh8x64 { continue } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAdd8 { continue } t := v_1_0_0.Type _ = v_1_0_0.Args[1] v_1_0_0_0 := v_1_0_0.Args[0] v_1_0_0_1 := v_1_0_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0_0_0, v_1_0_0_1 = _i1+1, v_1_0_0_1, v_1_0_0_0 { if n != v_1_0_0_0 || v_1_0_0_1.Op != OpRsh8Ux64 || v_1_0_0_1.Type != t { continue } _ = v_1_0_0_1.Args[1] v_1_0_0_1_0 := v_1_0_0_1.Args[0] if v_1_0_0_1_0.Op != OpRsh8x64 || v_1_0_0_1_0.Type != t { continue } _ = v_1_0_0_1_0.Args[1] if n != v_1_0_0_1_0.Args[0] { continue } v_1_0_0_1_0_1 := v_1_0_0_1_0.Args[1] if v_1_0_0_1_0_1.Op != OpConst64 || v_1_0_0_1_0_1.Type != typ.UInt64 || auxIntToInt64(v_1_0_0_1_0_1.AuxInt) != 7 { continue } v_1_0_0_1_1 := v_1_0_0_1.Args[1] if v_1_0_0_1_1.Op != OpConst64 || v_1_0_0_1_1.Type != typ.UInt64 { continue } kbar := auxIntToInt64(v_1_0_0_1_1.AuxInt) v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpConst64 || v_1_0_1.Type != typ.UInt64 { continue } k := auxIntToInt64(v_1_0_1.AuxInt) v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 || v_1_1.Type != typ.UInt64 || auxIntToInt64(v_1_1.AuxInt) != k || !(k > 0 && k < 7 && kbar == 8-k) { continue } v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(1< x (Const8 [y])) (Const8 [y])) // cond: oneBit8(y) // result: (Eq8 (And8 x (Const8 [y])) (Const8 [0])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } t := v_0.Type _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst8 || v_0_1.Type != t { continue } y := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 || v_1.Type != t || auxIntToInt8(v_1.AuxInt) != y || !(oneBit8(y)) { continue } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpAnd8, t) v1 := b.NewValue0(v.Pos, OpConst8, t) v1.AuxInt = int8ToAuxInt(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpConst8, t) v2.AuxInt = int8ToAuxInt(0) v.AddArg2(v0, v2) return true } } break } return false } func rewriteValuegeneric_OpNeqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (NeqB (ConstBool [c]) (ConstBool [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool { continue } c := auxIntToBool(v_0.AuxInt) if v_1.Op != OpConstBool { continue } d := auxIntToBool(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (NeqB (ConstBool [false]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != false { continue } x := v_1 v.copyOf(x) return true } break } // match: (NeqB (ConstBool [true]) x) // result: (Not x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstBool || auxIntToBool(v_0.AuxInt) != true { continue } x := v_1 v.reset(OpNot) v.AddArg(x) return true } break } // match: (NeqB (Not x) (Not y)) // result: (NeqB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpNot { continue } x := v_0.Args[0] if v_1.Op != OpNot { continue } y := v_1.Args[0] v.reset(OpNeqB) v.AddArg2(x, y) return true } break } return false } func rewriteValuegeneric_OpNeqInter(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (NeqInter x y) // result: (NeqPtr (ITab x) (ITab y)) for { x := v_0 y := v_1 v.reset(OpNeqPtr) v0 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpITab, typ.Uintptr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (NeqPtr x x) // result: (ConstBool [false]) for { x := v_0 if x != v_1 { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (NeqPtr (Addr {x} _) (Addr {y} _)) // result: (ConstBool [x != y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y) return true } break } // match: (NeqPtr (Addr {x} _) (OffPtr [o] (Addr {y} _))) // result: (ConstBool [x != y || o != 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o != 0) return true } break } // match: (NeqPtr (OffPtr [o1] (Addr {x} _)) (OffPtr [o2] (Addr {y} _))) // result: (ConstBool [x != y || o1 != o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o1 != o2) return true } break } // match: (NeqPtr (LocalAddr {x} _ _) (LocalAddr {y} _ _)) // result: (ConstBool [x != y]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpLocalAddr { continue } y := auxToSym(v_1.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y) return true } break } // match: (NeqPtr (LocalAddr {x} _ _) (OffPtr [o] (LocalAddr {y} _ _))) // result: (ConstBool [x != y || o != 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr { continue } x := auxToSym(v_0.Aux) if v_1.Op != OpOffPtr { continue } o := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o != 0) return true } break } // match: (NeqPtr (OffPtr [o1] (LocalAddr {x} _ _)) (OffPtr [o2] (LocalAddr {y} _ _))) // result: (ConstBool [x != y || o1 != o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr { continue } x := auxToSym(v_0_0.Aux) if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpLocalAddr { continue } y := auxToSym(v_1_0.Aux) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(x != y || o1 != o2) return true } break } // match: (NeqPtr (OffPtr [o1] p1) p2) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 != 0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 != 0) return true } break } // match: (NeqPtr (OffPtr [o1] p1) (OffPtr [o2] p2)) // cond: isSamePtr(p1, p2) // result: (ConstBool [o1 != o2]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } o1 := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] if v_1.Op != OpOffPtr { continue } o2 := auxIntToInt64(v_1.AuxInt) p2 := v_1.Args[0] if !(isSamePtr(p1, p2)) { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(o1 != o2) return true } break } // match: (NeqPtr (Const32 [c]) (Const32 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (NeqPtr (Const64 [c]) (Const64 [d])) // result: (ConstBool [c != d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(c != d) return true } break } // match: (NeqPtr (LocalAddr _ _) (Addr _)) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (OffPtr (LocalAddr _ _)) (Addr _)) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (LocalAddr _ _) (OffPtr (Addr _))) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (OffPtr (LocalAddr _ _)) (OffPtr (Addr _))) // result: (ConstBool [true]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOffPtr { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpLocalAddr || v_1.Op != OpOffPtr { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAddr { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } break } // match: (NeqPtr (AddPtr p1 o1) p2) // cond: isSamePtr(p1, p2) // result: (IsNonNil o1) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAddPtr { continue } o1 := v_0.Args[1] p1 := v_0.Args[0] p2 := v_1 if !(isSamePtr(p1, p2)) { continue } v.reset(OpIsNonNil) v.AddArg(o1) return true } break } // match: (NeqPtr (Const32 [0]) p) // result: (IsNonNil p) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpIsNonNil) v.AddArg(p) return true } break } // match: (NeqPtr (Const64 [0]) p) // result: (IsNonNil p) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } p := v_1 v.reset(OpIsNonNil) v.AddArg(p) return true } break } // match: (NeqPtr (ConstNil) p) // result: (IsNonNil p) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConstNil { continue } p := v_1 v.reset(OpIsNonNil) v.AddArg(p) return true } break } return false } func rewriteValuegeneric_OpNeqSlice(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (NeqSlice x y) // result: (NeqPtr (SlicePtr x) (SlicePtr y)) for { x := v_0 y := v_1 v.reset(OpNeqPtr) v0 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSlicePtr, typ.BytePtr) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValuegeneric_OpNilCheck(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (NilCheck (GetG mem) mem) // result: mem for { if v_0.Op != OpGetG { break } mem := v_0.Args[0] if mem != v_1 { break } v.copyOf(mem) return true } // match: (NilCheck (SelectN [0] call:(StaticLECall _ _)) _) // cond: isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check") // result: (Invalid) for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { break } call := v_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 || !(isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check")) { break } v.reset(OpInvalid) return true } // match: (NilCheck (OffPtr (SelectN [0] call:(StaticLECall _ _))) _) // cond: isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check") // result: (Invalid) for { if v_0.Op != OpOffPtr { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpSelectN || auxIntToInt64(v_0_0.AuxInt) != 0 { break } call := v_0_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 || !(isSameCall(call.Aux, "runtime.newobject") && warnRule(fe.Debug_checknil(), v, "removed nil check")) { break } v.reset(OpInvalid) return true } return false } func rewriteValuegeneric_OpNot(v *Value) bool { v_0 := v.Args[0] // match: (Not (ConstBool [c])) // result: (ConstBool [!c]) for { if v_0.Op != OpConstBool { break } c := auxIntToBool(v_0.AuxInt) v.reset(OpConstBool) v.AuxInt = boolToAuxInt(!c) return true } // match: (Not (Eq64 x y)) // result: (Neq64 x y) for { if v_0.Op != OpEq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq64) v.AddArg2(x, y) return true } // match: (Not (Eq32 x y)) // result: (Neq32 x y) for { if v_0.Op != OpEq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq32) v.AddArg2(x, y) return true } // match: (Not (Eq16 x y)) // result: (Neq16 x y) for { if v_0.Op != OpEq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq16) v.AddArg2(x, y) return true } // match: (Not (Eq8 x y)) // result: (Neq8 x y) for { if v_0.Op != OpEq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq8) v.AddArg2(x, y) return true } // match: (Not (EqB x y)) // result: (NeqB x y) for { if v_0.Op != OpEqB { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeqB) v.AddArg2(x, y) return true } // match: (Not (EqPtr x y)) // result: (NeqPtr x y) for { if v_0.Op != OpEqPtr { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeqPtr) v.AddArg2(x, y) return true } // match: (Not (Eq64F x y)) // result: (Neq64F x y) for { if v_0.Op != OpEq64F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq64F) v.AddArg2(x, y) return true } // match: (Not (Eq32F x y)) // result: (Neq32F x y) for { if v_0.Op != OpEq32F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpNeq32F) v.AddArg2(x, y) return true } // match: (Not (Neq64 x y)) // result: (Eq64 x y) for { if v_0.Op != OpNeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq64) v.AddArg2(x, y) return true } // match: (Not (Neq32 x y)) // result: (Eq32 x y) for { if v_0.Op != OpNeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq32) v.AddArg2(x, y) return true } // match: (Not (Neq16 x y)) // result: (Eq16 x y) for { if v_0.Op != OpNeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq16) v.AddArg2(x, y) return true } // match: (Not (Neq8 x y)) // result: (Eq8 x y) for { if v_0.Op != OpNeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq8) v.AddArg2(x, y) return true } // match: (Not (NeqB x y)) // result: (EqB x y) for { if v_0.Op != OpNeqB { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEqB) v.AddArg2(x, y) return true } // match: (Not (NeqPtr x y)) // result: (EqPtr x y) for { if v_0.Op != OpNeqPtr { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEqPtr) v.AddArg2(x, y) return true } // match: (Not (Neq64F x y)) // result: (Eq64F x y) for { if v_0.Op != OpNeq64F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq64F) v.AddArg2(x, y) return true } // match: (Not (Neq32F x y)) // result: (Eq32F x y) for { if v_0.Op != OpNeq32F { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpEq32F) v.AddArg2(x, y) return true } // match: (Not (Less64 x y)) // result: (Leq64 y x) for { if v_0.Op != OpLess64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq64) v.AddArg2(y, x) return true } // match: (Not (Less32 x y)) // result: (Leq32 y x) for { if v_0.Op != OpLess32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq32) v.AddArg2(y, x) return true } // match: (Not (Less16 x y)) // result: (Leq16 y x) for { if v_0.Op != OpLess16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq16) v.AddArg2(y, x) return true } // match: (Not (Less8 x y)) // result: (Leq8 y x) for { if v_0.Op != OpLess8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq8) v.AddArg2(y, x) return true } // match: (Not (Less64U x y)) // result: (Leq64U y x) for { if v_0.Op != OpLess64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq64U) v.AddArg2(y, x) return true } // match: (Not (Less32U x y)) // result: (Leq32U y x) for { if v_0.Op != OpLess32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq32U) v.AddArg2(y, x) return true } // match: (Not (Less16U x y)) // result: (Leq16U y x) for { if v_0.Op != OpLess16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq16U) v.AddArg2(y, x) return true } // match: (Not (Less8U x y)) // result: (Leq8U y x) for { if v_0.Op != OpLess8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLeq8U) v.AddArg2(y, x) return true } // match: (Not (Leq64 x y)) // result: (Less64 y x) for { if v_0.Op != OpLeq64 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess64) v.AddArg2(y, x) return true } // match: (Not (Leq32 x y)) // result: (Less32 y x) for { if v_0.Op != OpLeq32 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess32) v.AddArg2(y, x) return true } // match: (Not (Leq16 x y)) // result: (Less16 y x) for { if v_0.Op != OpLeq16 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess16) v.AddArg2(y, x) return true } // match: (Not (Leq8 x y)) // result: (Less8 y x) for { if v_0.Op != OpLeq8 { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess8) v.AddArg2(y, x) return true } // match: (Not (Leq64U x y)) // result: (Less64U y x) for { if v_0.Op != OpLeq64U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess64U) v.AddArg2(y, x) return true } // match: (Not (Leq32U x y)) // result: (Less32U y x) for { if v_0.Op != OpLeq32U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess32U) v.AddArg2(y, x) return true } // match: (Not (Leq16U x y)) // result: (Less16U y x) for { if v_0.Op != OpLeq16U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess16U) v.AddArg2(y, x) return true } // match: (Not (Leq8U x y)) // result: (Less8U y x) for { if v_0.Op != OpLeq8U { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpLess8U) v.AddArg2(y, x) return true } return false } func rewriteValuegeneric_OpOffPtr(v *Value) bool { v_0 := v.Args[0] // match: (OffPtr (OffPtr p [y]) [x]) // result: (OffPtr p [x+y]) for { x := auxIntToInt64(v.AuxInt) if v_0.Op != OpOffPtr { break } y := auxIntToInt64(v_0.AuxInt) p := v_0.Args[0] v.reset(OpOffPtr) v.AuxInt = int64ToAuxInt(x + y) v.AddArg(p) return true } // match: (OffPtr p [0]) // cond: v.Type.Compare(p.Type) == types.CMPeq // result: p for { if auxIntToInt64(v.AuxInt) != 0 { break } p := v_0 if !(v.Type.Compare(p.Type) == types.CMPeq) { break } v.copyOf(p) return true } return false } func rewriteValuegeneric_OpOr16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Or16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c | d) return true } break } // match: (Or16 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or16 (Const16 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or16 (Const16 [-1]) _) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Or16 (Com16 x) x) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Or16 x (Or16 x y)) // result: (Or16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr16) v.AddArg2(x, y) return true } } break } // match: (Or16 (And16 x (Const16 [c2])) (Const16 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or16 (Const16 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst16 { continue } c2 := auxIntToInt16(v_0_1.AuxInt) if v_1.Op != OpConst16 { continue } t := v_1.Type c1 := auxIntToInt16(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or16 (Or16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Or16 i (Or16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpOr16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or16 (Const16 [c]) (Or16 (Const16 [d]) x)) // result: (Or16 (Const16 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpOr16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } // match: (Or16 (Lsh16x64 x z:(Const64 [c])) (Rsh16Ux64 x (Const64 [d]))) // cond: c < 16 && d == 16-c && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh16x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh16Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 16 && d == 16-c && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Or16 left:(Lsh16x64 x y) right:(Rsh16Ux64 x (Sub64 (Const64 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Or16 left:(Lsh16x32 x y) right:(Rsh16Ux32 x (Sub32 (Const32 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Or16 left:(Lsh16x16 x y) right:(Rsh16Ux16 x (Sub16 (Const16 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Or16 left:(Lsh16x8 x y) right:(Rsh16Ux8 x (Sub8 (Const8 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Or16 right:(Rsh16Ux64 x y) left:(Lsh16x64 x z:(Sub64 (Const64 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Or16 right:(Rsh16Ux32 x y) left:(Lsh16x32 x z:(Sub32 (Const32 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Or16 right:(Rsh16Ux16 x y) left:(Lsh16x16 x z:(Sub16 (Const16 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Or16 right:(Rsh16Ux8 x y) left:(Lsh16x8 x z:(Sub8 (Const8 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpOr32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Or32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c | d) return true } break } // match: (Or32 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or32 (Const32 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or32 (Const32 [-1]) _) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Or32 (Com32 x) x) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Or32 x (Or32 x y)) // result: (Or32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr32) v.AddArg2(x, y) return true } } break } // match: (Or32 (And32 x (Const32 [c2])) (Const32 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or32 (Const32 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst32 { continue } c2 := auxIntToInt32(v_0_1.AuxInt) if v_1.Op != OpConst32 { continue } t := v_1.Type c1 := auxIntToInt32(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or32 (Or32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Or32 i (Or32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpOr32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or32 (Const32 [c]) (Or32 (Const32 [d]) x)) // result: (Or32 (Const32 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpOr32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } // match: (Or32 (Lsh32x64 x z:(Const64 [c])) (Rsh32Ux64 x (Const64 [d]))) // cond: c < 32 && d == 32-c && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh32x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh32Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 32 && d == 32-c && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Or32 left:(Lsh32x64 x y) right:(Rsh32Ux64 x (Sub64 (Const64 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Or32 left:(Lsh32x32 x y) right:(Rsh32Ux32 x (Sub32 (Const32 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Or32 left:(Lsh32x16 x y) right:(Rsh32Ux16 x (Sub16 (Const16 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Or32 left:(Lsh32x8 x y) right:(Rsh32Ux8 x (Sub8 (Const8 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Or32 right:(Rsh32Ux64 x y) left:(Lsh32x64 x z:(Sub64 (Const64 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Or32 right:(Rsh32Ux32 x y) left:(Lsh32x32 x z:(Sub32 (Const32 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Or32 right:(Rsh32Ux16 x y) left:(Lsh32x16 x z:(Sub16 (Const16 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Or32 right:(Rsh32Ux8 x y) left:(Lsh32x8 x z:(Sub8 (Const8 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpOr64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Or64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c | d) return true } break } // match: (Or64 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or64 (Const64 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or64 (Const64 [-1]) _) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Or64 (Com64 x) x) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Or64 x (Or64 x y)) // result: (Or64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr64) v.AddArg2(x, y) return true } } break } // match: (Or64 (And64 x (Const64 [c2])) (Const64 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or64 (Const64 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst64 { continue } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { continue } t := v_1.Type c1 := auxIntToInt64(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or64 (Or64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Or64 i (Or64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpOr64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or64 (Const64 [c]) (Or64 (Const64 [d]) x)) // result: (Or64 (Const64 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpOr64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } // match: (Or64 (Lsh64x64 x z:(Const64 [c])) (Rsh64Ux64 x (Const64 [d]))) // cond: c < 64 && d == 64-c && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh64x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh64Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 64 && d == 64-c && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Or64 left:(Lsh64x64 x y) right:(Rsh64Ux64 x (Sub64 (Const64 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Or64 left:(Lsh64x32 x y) right:(Rsh64Ux32 x (Sub32 (Const32 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Or64 left:(Lsh64x16 x y) right:(Rsh64Ux16 x (Sub16 (Const16 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Or64 left:(Lsh64x8 x y) right:(Rsh64Ux8 x (Sub8 (Const8 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Or64 right:(Rsh64Ux64 x y) left:(Lsh64x64 x z:(Sub64 (Const64 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Or64 right:(Rsh64Ux32 x y) left:(Lsh64x32 x z:(Sub32 (Const32 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Or64 right:(Rsh64Ux16 x y) left:(Lsh64x16 x z:(Sub16 (Const16 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Or64 right:(Rsh64Ux8 x y) left:(Lsh64x8 x z:(Sub8 (Const8 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpOr8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Or8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c | d) return true } break } // match: (Or8 x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (Or8 (Const8 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Or8 (Const8 [-1]) _) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Or8 (Com8 x) x) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Or8 x (Or8 x y)) // result: (Or8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpOr8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpOr8) v.AddArg2(x, y) return true } } break } // match: (Or8 (And8 x (Const8 [c2])) (Const8 [c1])) // cond: ^(c1 | c2) == 0 // result: (Or8 (Const8 [c1]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAnd8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { x := v_0_0 if v_0_1.Op != OpConst8 { continue } c2 := auxIntToInt8(v_0_1.AuxInt) if v_1.Op != OpConst8 { continue } t := v_1.Type c1 := auxIntToInt8(v_1.AuxInt) if !(^(c1 | c2) == 0) { continue } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c1) v.AddArg2(v0, x) return true } } break } // match: (Or8 (Or8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Or8 i (Or8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpOr8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpOr8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Or8 (Const8 [c]) (Or8 (Const8 [d]) x)) // result: (Or8 (Const8 [c|d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpOr8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c | d) v.AddArg2(v0, x) return true } } break } // match: (Or8 (Lsh8x64 x z:(Const64 [c])) (Rsh8Ux64 x (Const64 [d]))) // cond: c < 8 && d == 8-c && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh8x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh8Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 8 && d == 8-c && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Or8 left:(Lsh8x64 x y) right:(Rsh8Ux64 x (Sub64 (Const64 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Or8 left:(Lsh8x32 x y) right:(Rsh8Ux32 x (Sub32 (Const32 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Or8 left:(Lsh8x16 x y) right:(Rsh8Ux16 x (Sub16 (Const16 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Or8 left:(Lsh8x8 x y) right:(Rsh8Ux8 x (Sub8 (Const8 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Or8 right:(Rsh8Ux64 x y) left:(Lsh8x64 x z:(Sub64 (Const64 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Or8 right:(Rsh8Ux32 x y) left:(Lsh8x32 x z:(Sub32 (Const32 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Or8 right:(Rsh8Ux16 x y) left:(Lsh8x16 x z:(Sub16 (Const16 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Or8 right:(Rsh8Ux8 x y) left:(Lsh8x8 x z:(Sub8 (Const8 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpOrB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (OrB (Less64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: c >= d // result: (Less64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64 (Const64 [c]) x) (Less64 x (Const64 [d]))) // cond: c >= d // result: (Leq64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: c >= d // result: (Less32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32 (Const32 [c]) x) (Less32 x (Const32 [d]))) // cond: c >= d // result: (Leq32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: c >= d // result: (Less16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16 (Const16 [c]) x) (Less16 x (Const16 [d]))) // cond: c >= d // result: (Leq16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: c >= d // result: (Less8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8 (Const8 [c]) x) (Less8 x (Const8 [d]))) // cond: c >= d // result: (Leq8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64 (Const64 [c]) x) (Leq64 x (Const64 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32 (Const32 [c]) x) (Leq32 x (Const32 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16 (Const16 [c]) x) (Leq16 x (Const16 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: c >= d+1 && d+1 > d // result: (Less8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8 (Const8 [c]) x) (Leq8 x (Const8 [d]))) // cond: c >= d+1 && d+1 > d // result: (Leq8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8 { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(c >= d+1 && d+1 > d) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d) // result: (Less64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64U (Const64 [c]) x) (Less64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d) // result: (Leq64U (Const64 [c-d]) (Sub64 x (Const64 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLess64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d) // result: (Less32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32U (Const32 [c]) x) (Less32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d) // result: (Leq32U (Const32 [c-d]) (Sub32 x (Const32 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLess32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d) // result: (Less16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16U (Const16 [c]) x) (Less16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d) // result: (Leq16U (Const16 [c-d]) (Sub16 x (Const16 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLess16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d) // result: (Less8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8U (Const8 [c]) x) (Less8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d) // result: (Leq8U (Const8 [c-d]) (Sub8 x (Const8 [d]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLess8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d) // result: (Less64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d)) { continue } v.reset(OpLess64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq64U (Const64 [c]) x) (Leq64U x (Const64 [d]))) // cond: uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d) // result: (Leq64U (Const64 [c-d-1]) (Sub64 x (Const64 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq64U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0_0.AuxInt) if v_1.Op != OpLeq64U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(uint64(c) >= uint64(d+1) && uint64(d+1) > uint64(d)) { continue } v.reset(OpLeq64U) v0 := b.NewValue0(v.Pos, OpConst64, x.Type) v0.AuxInt = int64ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub64, x.Type) v2 := b.NewValue0(v.Pos, OpConst64, x.Type) v2.AuxInt = int64ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d) // result: (Less32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d)) { continue } v.reset(OpLess32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq32U (Const32 [c]) x) (Leq32U x (Const32 [d]))) // cond: uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d) // result: (Leq32U (Const32 [c-d-1]) (Sub32 x (Const32 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq32U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0_0.AuxInt) if v_1.Op != OpLeq32U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1_1.AuxInt) if !(uint32(c) >= uint32(d+1) && uint32(d+1) > uint32(d)) { continue } v.reset(OpLeq32U) v0 := b.NewValue0(v.Pos, OpConst32, x.Type) v0.AuxInt = int32ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub32, x.Type) v2 := b.NewValue0(v.Pos, OpConst32, x.Type) v2.AuxInt = int32ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d) // result: (Less16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d)) { continue } v.reset(OpLess16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq16U (Const16 [c]) x) (Leq16U x (Const16 [d]))) // cond: uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d) // result: (Leq16U (Const16 [c-d-1]) (Sub16 x (Const16 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq16U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0_0.AuxInt) if v_1.Op != OpLeq16U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1_1.AuxInt) if !(uint16(c) >= uint16(d+1) && uint16(d+1) > uint16(d)) { continue } v.reset(OpLeq16U) v0 := b.NewValue0(v.Pos, OpConst16, x.Type) v0.AuxInt = int16ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub16, x.Type) v2 := b.NewValue0(v.Pos, OpConst16, x.Type) v2.AuxInt = int16ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Less8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d) // result: (Less8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLess8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d)) { continue } v.reset(OpLess8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } // match: (OrB (Leq8U (Const8 [c]) x) (Leq8U x (Const8 [d]))) // cond: uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d) // result: (Leq8U (Const8 [c-d-1]) (Sub8 x (Const8 [d+1]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLeq8U { continue } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0_0.AuxInt) if v_1.Op != OpLeq8U { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1_1.AuxInt) if !(uint8(c) >= uint8(d+1) && uint8(d+1) > uint8(d)) { continue } v.reset(OpLeq8U) v0 := b.NewValue0(v.Pos, OpConst8, x.Type) v0.AuxInt = int8ToAuxInt(c - d - 1) v1 := b.NewValue0(v.Pos, OpSub8, x.Type) v2 := b.NewValue0(v.Pos, OpConst8, x.Type) v2.AuxInt = int8ToAuxInt(d + 1) v1.AddArg2(x, v2) v.AddArg2(v0, v1) return true } break } return false } func rewriteValuegeneric_OpPhi(v *Value) bool { // match: (Phi (Const8 [c]) (Const8 [c])) // result: (Const8 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst8 || auxIntToInt8(v_1.AuxInt) != c { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c) return true } // match: (Phi (Const16 [c]) (Const16 [c])) // result: (Const16 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst16 || auxIntToInt16(v_1.AuxInt) != c { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c) return true } // match: (Phi (Const32 [c]) (Const32 [c])) // result: (Const32 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst32 || auxIntToInt32(v_1.AuxInt) != c { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c) return true } // match: (Phi (Const64 [c]) (Const64 [c])) // result: (Const64 [c]) for { if len(v.Args) != 2 { break } _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v_1 := v.Args[1] if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != c { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValuegeneric_OpPtrIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (PtrIndex ptr idx) // cond: config.PtrSize == 4 && is32Bit(t.Elem().Size()) // result: (AddPtr ptr (Mul32 idx (Const32 [int32(t.Elem().Size())]))) for { t := v.Type ptr := v_0 idx := v_1 if !(config.PtrSize == 4 && is32Bit(t.Elem().Size())) { break } v.reset(OpAddPtr) v0 := b.NewValue0(v.Pos, OpMul32, typ.Int) v1 := b.NewValue0(v.Pos, OpConst32, typ.Int) v1.AuxInt = int32ToAuxInt(int32(t.Elem().Size())) v0.AddArg2(idx, v1) v.AddArg2(ptr, v0) return true } // match: (PtrIndex ptr idx) // cond: config.PtrSize == 8 // result: (AddPtr ptr (Mul64 idx (Const64 [t.Elem().Size()]))) for { t := v.Type ptr := v_0 idx := v_1 if !(config.PtrSize == 8) { break } v.reset(OpAddPtr) v0 := b.NewValue0(v.Pos, OpMul64, typ.Int) v1 := b.NewValue0(v.Pos, OpConst64, typ.Int) v1.AuxInt = int64ToAuxInt(t.Elem().Size()) v0.AddArg2(idx, v1) v.AddArg2(ptr, v0) return true } return false } func rewriteValuegeneric_OpRotateLeft16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (RotateLeft16 x (Const16 [c])) // cond: c%16 == 0 // result: x for { x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) if !(c%16 == 0) { break } v.copyOf(x) return true } // match: (RotateLeft16 x (And64 y (Const64 [c]))) // cond: c&15 == 15 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (And32 y (Const32 [c]))) // cond: c&15 == 15 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (And16 y (Const16 [c]))) // cond: c&15 == 15 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (And8 y (Const8 [c]))) // cond: c&15 == 15 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (Neg64 (And64 y (Const64 [c])))) // cond: c&15 == 15 // result: (RotateLeft16 x (Neg64 y)) for { x := v_0 if v_1.Op != OpNeg64 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft16 x (Neg32 (And32 y (Const32 [c])))) // cond: c&15 == 15 // result: (RotateLeft16 x (Neg32 y)) for { x := v_0 if v_1.Op != OpNeg32 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft16 x (Neg16 (And16 y (Const16 [c])))) // cond: c&15 == 15 // result: (RotateLeft16 x (Neg16 y)) for { x := v_0 if v_1.Op != OpNeg16 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd16 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft16 x (Neg8 (And8 y (Const8 [c])))) // cond: c&15 == 15 // result: (RotateLeft16 x (Neg8 y)) for { x := v_0 if v_1.Op != OpNeg8 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd8 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0_1.AuxInt) if !(c&15 == 15) { continue } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft16 x (Add64 y (Const64 [c]))) // cond: c&15 == 0 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&15 == 0) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (Add32 y (Const32 [c]))) // cond: c&15 == 0 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&15 == 0) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (Add16 y (Const16 [c]))) // cond: c&15 == 0 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&15 == 0) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (Add8 y (Const8 [c]))) // cond: c&15 == 0 // result: (RotateLeft16 x y) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&15 == 0) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (RotateLeft16 x (Sub64 (Const64 [c]) y)) // cond: c&15 == 0 // result: (RotateLeft16 x (Neg64 y)) for { x := v_0 if v_1.Op != OpSub64 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := auxIntToInt64(v_1_0.AuxInt) if !(c&15 == 0) { break } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft16 x (Sub32 (Const32 [c]) y)) // cond: c&15 == 0 // result: (RotateLeft16 x (Neg32 y)) for { x := v_0 if v_1.Op != OpSub32 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := auxIntToInt32(v_1_0.AuxInt) if !(c&15 == 0) { break } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft16 x (Sub16 (Const16 [c]) y)) // cond: c&15 == 0 // result: (RotateLeft16 x (Neg16 y)) for { x := v_0 if v_1.Op != OpSub16 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := auxIntToInt16(v_1_0.AuxInt) if !(c&15 == 0) { break } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft16 x (Sub8 (Const8 [c]) y)) // cond: c&15 == 0 // result: (RotateLeft16 x (Neg8 y)) for { x := v_0 if v_1.Op != OpSub8 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := auxIntToInt8(v_1_0.AuxInt) if !(c&15 == 0) { break } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft16 x (Const64 [c])) // cond: config.PtrSize == 4 // result: (RotateLeft16 x (Const32 [int32(c)])) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpRotateLeft16) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRotateLeft32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (RotateLeft32 x (Const32 [c])) // cond: c%32 == 0 // result: x for { x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) if !(c%32 == 0) { break } v.copyOf(x) return true } // match: (RotateLeft32 x (And64 y (Const64 [c]))) // cond: c&31 == 31 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (And32 y (Const32 [c]))) // cond: c&31 == 31 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (And16 y (Const16 [c]))) // cond: c&31 == 31 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (And8 y (Const8 [c]))) // cond: c&31 == 31 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (Neg64 (And64 y (Const64 [c])))) // cond: c&31 == 31 // result: (RotateLeft32 x (Neg64 y)) for { x := v_0 if v_1.Op != OpNeg64 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft32 x (Neg32 (And32 y (Const32 [c])))) // cond: c&31 == 31 // result: (RotateLeft32 x (Neg32 y)) for { x := v_0 if v_1.Op != OpNeg32 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft32 x (Neg16 (And16 y (Const16 [c])))) // cond: c&31 == 31 // result: (RotateLeft32 x (Neg16 y)) for { x := v_0 if v_1.Op != OpNeg16 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd16 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft32 x (Neg8 (And8 y (Const8 [c])))) // cond: c&31 == 31 // result: (RotateLeft32 x (Neg8 y)) for { x := v_0 if v_1.Op != OpNeg8 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd8 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0_1.AuxInt) if !(c&31 == 31) { continue } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft32 x (Add64 y (Const64 [c]))) // cond: c&31 == 0 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&31 == 0) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (Add32 y (Const32 [c]))) // cond: c&31 == 0 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&31 == 0) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (Add16 y (Const16 [c]))) // cond: c&31 == 0 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&31 == 0) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (Add8 y (Const8 [c]))) // cond: c&31 == 0 // result: (RotateLeft32 x y) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&31 == 0) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (RotateLeft32 x (Sub64 (Const64 [c]) y)) // cond: c&31 == 0 // result: (RotateLeft32 x (Neg64 y)) for { x := v_0 if v_1.Op != OpSub64 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := auxIntToInt64(v_1_0.AuxInt) if !(c&31 == 0) { break } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft32 x (Sub32 (Const32 [c]) y)) // cond: c&31 == 0 // result: (RotateLeft32 x (Neg32 y)) for { x := v_0 if v_1.Op != OpSub32 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := auxIntToInt32(v_1_0.AuxInt) if !(c&31 == 0) { break } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft32 x (Sub16 (Const16 [c]) y)) // cond: c&31 == 0 // result: (RotateLeft32 x (Neg16 y)) for { x := v_0 if v_1.Op != OpSub16 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := auxIntToInt16(v_1_0.AuxInt) if !(c&31 == 0) { break } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft32 x (Sub8 (Const8 [c]) y)) // cond: c&31 == 0 // result: (RotateLeft32 x (Neg8 y)) for { x := v_0 if v_1.Op != OpSub8 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := auxIntToInt8(v_1_0.AuxInt) if !(c&31 == 0) { break } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft32 x (Const64 [c])) // cond: config.PtrSize == 4 // result: (RotateLeft32 x (Const32 [int32(c)])) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpRotateLeft32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRotateLeft64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (RotateLeft64 x (Const64 [c])) // cond: c%64 == 0 // result: x for { x := v_0 if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(c%64 == 0) { break } v.copyOf(x) return true } // match: (RotateLeft64 x (And64 y (Const64 [c]))) // cond: c&63 == 63 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (And32 y (Const32 [c]))) // cond: c&63 == 63 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (And16 y (Const16 [c]))) // cond: c&63 == 63 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (And8 y (Const8 [c]))) // cond: c&63 == 63 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (Neg64 (And64 y (Const64 [c])))) // cond: c&63 == 63 // result: (RotateLeft64 x (Neg64 y)) for { x := v_0 if v_1.Op != OpNeg64 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft64 x (Neg32 (And32 y (Const32 [c])))) // cond: c&63 == 63 // result: (RotateLeft64 x (Neg32 y)) for { x := v_0 if v_1.Op != OpNeg32 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft64 x (Neg16 (And16 y (Const16 [c])))) // cond: c&63 == 63 // result: (RotateLeft64 x (Neg16 y)) for { x := v_0 if v_1.Op != OpNeg16 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd16 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft64 x (Neg8 (And8 y (Const8 [c])))) // cond: c&63 == 63 // result: (RotateLeft64 x (Neg8 y)) for { x := v_0 if v_1.Op != OpNeg8 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd8 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0_1.AuxInt) if !(c&63 == 63) { continue } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft64 x (Add64 y (Const64 [c]))) // cond: c&63 == 0 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&63 == 0) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (Add32 y (Const32 [c]))) // cond: c&63 == 0 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&63 == 0) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (Add16 y (Const16 [c]))) // cond: c&63 == 0 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&63 == 0) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (Add8 y (Const8 [c]))) // cond: c&63 == 0 // result: (RotateLeft64 x y) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&63 == 0) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (RotateLeft64 x (Sub64 (Const64 [c]) y)) // cond: c&63 == 0 // result: (RotateLeft64 x (Neg64 y)) for { x := v_0 if v_1.Op != OpSub64 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := auxIntToInt64(v_1_0.AuxInt) if !(c&63 == 0) { break } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft64 x (Sub32 (Const32 [c]) y)) // cond: c&63 == 0 // result: (RotateLeft64 x (Neg32 y)) for { x := v_0 if v_1.Op != OpSub32 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := auxIntToInt32(v_1_0.AuxInt) if !(c&63 == 0) { break } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft64 x (Sub16 (Const16 [c]) y)) // cond: c&63 == 0 // result: (RotateLeft64 x (Neg16 y)) for { x := v_0 if v_1.Op != OpSub16 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := auxIntToInt16(v_1_0.AuxInt) if !(c&63 == 0) { break } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft64 x (Sub8 (Const8 [c]) y)) // cond: c&63 == 0 // result: (RotateLeft64 x (Neg8 y)) for { x := v_0 if v_1.Op != OpSub8 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := auxIntToInt8(v_1_0.AuxInt) if !(c&63 == 0) { break } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft64 x (Const64 [c])) // cond: config.PtrSize == 4 // result: (RotateLeft64 x (Const32 [int32(c)])) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpRotateLeft64) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRotateLeft8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (RotateLeft8 x (Const8 [c])) // cond: c%8 == 0 // result: x for { x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) if !(c%8 == 0) { break } v.copyOf(x) return true } // match: (RotateLeft8 x (And64 y (Const64 [c]))) // cond: c&7 == 7 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAnd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (And32 y (Const32 [c]))) // cond: c&7 == 7 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAnd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (And16 y (Const16 [c]))) // cond: c&7 == 7 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAnd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (And8 y (Const8 [c]))) // cond: c&7 == 7 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAnd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (Neg64 (And64 y (Const64 [c])))) // cond: c&7 == 7 // result: (RotateLeft8 x (Neg64 y)) for { x := v_0 if v_1.Op != OpNeg64 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd64 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_0_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft8 x (Neg32 (And32 y (Const32 [c])))) // cond: c&7 == 7 // result: (RotateLeft8 x (Neg32 y)) for { x := v_0 if v_1.Op != OpNeg32 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd32 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_0_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft8 x (Neg16 (And16 y (Const16 [c])))) // cond: c&7 == 7 // result: (RotateLeft8 x (Neg16 y)) for { x := v_0 if v_1.Op != OpNeg16 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd16 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_0_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft8 x (Neg8 (And8 y (Const8 [c])))) // cond: c&7 == 7 // result: (RotateLeft8 x (Neg8 y)) for { x := v_0 if v_1.Op != OpNeg8 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAnd8 { break } _ = v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] v_1_0_1 := v_1_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { y := v_1_0_0 if v_1_0_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_0_1.AuxInt) if !(c&7 == 7) { continue } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } break } // match: (RotateLeft8 x (Add64 y (Const64 [c]))) // cond: c&7 == 0 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst64 { continue } c := auxIntToInt64(v_1_1.AuxInt) if !(c&7 == 0) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (Add32 y (Const32 [c]))) // cond: c&7 == 0 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst32 { continue } c := auxIntToInt32(v_1_1.AuxInt) if !(c&7 == 0) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (Add16 y (Const16 [c]))) // cond: c&7 == 0 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst16 { continue } c := auxIntToInt16(v_1_1.AuxInt) if !(c&7 == 0) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (Add8 y (Const8 [c]))) // cond: c&7 == 0 // result: (RotateLeft8 x y) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { y := v_1_0 if v_1_1.Op != OpConst8 { continue } c := auxIntToInt8(v_1_1.AuxInt) if !(c&7 == 0) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (RotateLeft8 x (Sub64 (Const64 [c]) y)) // cond: c&7 == 0 // result: (RotateLeft8 x (Neg64 y)) for { x := v_0 if v_1.Op != OpSub64 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 { break } c := auxIntToInt64(v_1_0.AuxInt) if !(c&7 == 0) { break } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft8 x (Sub32 (Const32 [c]) y)) // cond: c&7 == 0 // result: (RotateLeft8 x (Neg32 y)) for { x := v_0 if v_1.Op != OpSub32 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 { break } c := auxIntToInt32(v_1_0.AuxInt) if !(c&7 == 0) { break } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft8 x (Sub16 (Const16 [c]) y)) // cond: c&7 == 0 // result: (RotateLeft8 x (Neg16 y)) for { x := v_0 if v_1.Op != OpSub16 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 { break } c := auxIntToInt16(v_1_0.AuxInt) if !(c&7 == 0) { break } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft8 x (Sub8 (Const8 [c]) y)) // cond: c&7 == 0 // result: (RotateLeft8 x (Neg8 y)) for { x := v_0 if v_1.Op != OpSub8 { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 { break } c := auxIntToInt8(v_1_0.AuxInt) if !(c&7 == 0) { break } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (RotateLeft8 x (Const64 [c])) // cond: config.PtrSize == 4 // result: (RotateLeft8 x (Const32 [int32(c)])) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(config.PtrSize == 4) { break } v.reset(OpRotateLeft8) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRound32F(v *Value) bool { v_0 := v.Args[0] // match: (Round32F x:(Const32F)) // result: x for { x := v_0 if x.Op != OpConst32F { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRound64F(v *Value) bool { v_0 := v.Args[0] // match: (Round64F x:(Const64F)) // result: x for { x := v_0 if x.Op != OpConst64F { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux16 x (Const16 [c])) // result: (Rsh16Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh16Ux16 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux32 x (Const32 [c])) // result: (Rsh16Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh16Ux32 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux64 (Const16 [c]) (Const64 [d])) // result: (Const16 [int16(uint16(c) >> uint64(d))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint16(c) >> uint64(d))) return true } // match: (Rsh16Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh16Ux64 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Rsh16Ux64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (Const16 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 16) { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Rsh16Ux64 (Rsh16Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh16Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh16Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh16Ux64 (Rsh16x64 x _) (Const64 [15])) // result: (Rsh16Ux64 x (Const64 [15])) for { if v_0.Op != OpRsh16x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 15 { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(15) v.AddArg2(x, v0) return true } // match: (Rsh16Ux64 (Lsh16x64 (Rsh16Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh16Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh16Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } // match: (Rsh16Ux64 (Lsh16x64 x (Const64 [8])) (Const64 [8])) // result: (ZeroExt8to16 (Trunc16to8 x)) for { if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 8 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 8 { break } v.reset(OpZeroExt8to16) v0 := b.NewValue0(v.Pos, OpTrunc16to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux8 x (Const8 [c])) // result: (Rsh16Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh16Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh16Ux8 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x16 x (Const16 [c])) // result: (Rsh16x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh16x16 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x32 x (Const32 [c])) // result: (Rsh16x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh16x32 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x64 (Const16 [c]) (Const64 [d])) // result: (Const16 [c >> uint64(d)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c >> uint64(d)) return true } // match: (Rsh16x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh16x64 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Rsh16x64 (Rsh16x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh16x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh16x64 (Lsh16x64 x (Const64 [8])) (Const64 [8])) // result: (SignExt8to16 (Trunc16to8 x)) for { if v_0.Op != OpLsh16x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 8 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 8 { break } v.reset(OpSignExt8to16) v0 := b.NewValue0(v.Pos, OpTrunc16to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x8 x (Const8 [c])) // result: (Rsh16x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh16x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh16x8 (Const16 [0]) _) // result: (Const16 [0]) for { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux16 x (Const16 [c])) // result: (Rsh32Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh32Ux16 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux32 x (Const32 [c])) // result: (Rsh32Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh32Ux32 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux64 (Const32 [c]) (Const64 [d])) // result: (Const32 [int32(uint32(c) >> uint64(d))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint32(c) >> uint64(d))) return true } // match: (Rsh32Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh32Ux64 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Rsh32Ux64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (Const32 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 32) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Rsh32Ux64 (Rsh32Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh32Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh32Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh32Ux64 (Rsh32x64 x _) (Const64 [31])) // result: (Rsh32Ux64 x (Const64 [31])) for { if v_0.Op != OpRsh32x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 31 { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(31) v.AddArg2(x, v0) return true } // match: (Rsh32Ux64 (Lsh32x64 (Rsh32Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh32Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh32Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } // match: (Rsh32Ux64 (Lsh32x64 x (Const64 [24])) (Const64 [24])) // result: (ZeroExt8to32 (Trunc32to8 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 24 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 24 { break } v.reset(OpZeroExt8to32) v0 := b.NewValue0(v.Pos, OpTrunc32to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh32Ux64 (Lsh32x64 x (Const64 [16])) (Const64 [16])) // result: (ZeroExt16to32 (Trunc32to16 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 16 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 16 { break } v.reset(OpZeroExt16to32) v0 := b.NewValue0(v.Pos, OpTrunc32to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux8 x (Const8 [c])) // result: (Rsh32Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh32Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh32Ux8 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x16 x (Const16 [c])) // result: (Rsh32x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh32x16 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x32 x (Const32 [c])) // result: (Rsh32x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh32x32 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x64 (Const32 [c]) (Const64 [d])) // result: (Const32 [c >> uint64(d)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c >> uint64(d)) return true } // match: (Rsh32x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh32x64 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Rsh32x64 (Rsh32x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh32x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh32x64 (Lsh32x64 x (Const64 [24])) (Const64 [24])) // result: (SignExt8to32 (Trunc32to8 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 24 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 24 { break } v.reset(OpSignExt8to32) v0 := b.NewValue0(v.Pos, OpTrunc32to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh32x64 (Lsh32x64 x (Const64 [16])) (Const64 [16])) // result: (SignExt16to32 (Trunc32to16 x)) for { if v_0.Op != OpLsh32x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 16 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 16 { break } v.reset(OpSignExt16to32) v0 := b.NewValue0(v.Pos, OpTrunc32to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x8 x (Const8 [c])) // result: (Rsh32x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh32x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh32x8 (Const32 [0]) _) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux16 x (Const16 [c])) // result: (Rsh64Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh64Ux16 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux32 x (Const32 [c])) // result: (Rsh64Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh64Ux32 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux64 (Const64 [c]) (Const64 [d])) // result: (Const64 [int64(uint64(c) >> uint64(d))]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) return true } // match: (Rsh64Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh64Ux64 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Rsh64Ux64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (Const64 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 64) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Rsh64Ux64 (Rsh64Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh64Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh64Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh64Ux64 (Rsh64x64 x _) (Const64 [63])) // result: (Rsh64Ux64 x (Const64 [63])) for { if v_0.Op != OpRsh64x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 63 { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(63) v.AddArg2(x, v0) return true } // match: (Rsh64Ux64 (Lsh64x64 (Rsh64Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh64Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh64Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [56])) (Const64 [56])) // result: (ZeroExt8to64 (Trunc64to8 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 56 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 56 { break } v.reset(OpZeroExt8to64) v0 := b.NewValue0(v.Pos, OpTrunc64to8, typ.UInt8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [48])) (Const64 [48])) // result: (ZeroExt16to64 (Trunc64to16 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 48 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 48 { break } v.reset(OpZeroExt16to64) v0 := b.NewValue0(v.Pos, OpTrunc64to16, typ.UInt16) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64Ux64 (Lsh64x64 x (Const64 [32])) (Const64 [32])) // result: (ZeroExt32to64 (Trunc64to32 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 32 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 32 { break } v.reset(OpZeroExt32to64) v0 := b.NewValue0(v.Pos, OpTrunc64to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux8 x (Const8 [c])) // result: (Rsh64Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh64Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh64Ux8 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x16 x (Const16 [c])) // result: (Rsh64x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh64x16 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x32 x (Const32 [c])) // result: (Rsh64x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh64x32 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c >> uint64(d)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c >> uint64(d)) return true } // match: (Rsh64x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh64x64 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Rsh64x64 (Rsh64x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh64x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [56])) (Const64 [56])) // result: (SignExt8to64 (Trunc64to8 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 56 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 56 { break } v.reset(OpSignExt8to64) v0 := b.NewValue0(v.Pos, OpTrunc64to8, typ.Int8) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [48])) (Const64 [48])) // result: (SignExt16to64 (Trunc64to16 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 48 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 48 { break } v.reset(OpSignExt16to64) v0 := b.NewValue0(v.Pos, OpTrunc64to16, typ.Int16) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh64x64 (Lsh64x64 x (Const64 [32])) (Const64 [32])) // result: (SignExt32to64 (Trunc64to32 x)) for { if v_0.Op != OpLsh64x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 || auxIntToInt64(v_0_1.AuxInt) != 32 || v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 32 { break } v.reset(OpSignExt32to64) v0 := b.NewValue0(v.Pos, OpTrunc64to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValuegeneric_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x8 x (Const8 [c])) // result: (Rsh64x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh64x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh64x8 (Const64 [0]) _) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux16 x (Const16 [c])) // result: (Rsh8Ux64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh8Ux16 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux32 x (Const32 [c])) // result: (Rsh8Ux64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh8Ux32 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux64 (Const8 [c]) (Const64 [d])) // result: (Const8 [int8(uint8(c) >> uint64(d))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(uint8(c) >> uint64(d))) return true } // match: (Rsh8Ux64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh8Ux64 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Rsh8Ux64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (Const8 [0]) for { if v_1.Op != OpConst64 { break } c := auxIntToInt64(v_1.AuxInt) if !(uint64(c) >= 8) { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Rsh8Ux64 (Rsh8Ux64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh8Ux64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh8Ux64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } // match: (Rsh8Ux64 (Rsh8x64 x _) (Const64 [7] )) // result: (Rsh8Ux64 x (Const64 [7] )) for { if v_0.Op != OpRsh8x64 { break } x := v_0.Args[0] if v_1.Op != OpConst64 { break } t := v_1.Type if auxIntToInt64(v_1.AuxInt) != 7 { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(7) v.AddArg2(x, v0) return true } // match: (Rsh8Ux64 (Lsh8x64 (Rsh8Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) // cond: uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) // result: (Rsh8Ux64 x (Const64 [c1-c2+c3])) for { if v_0.Op != OpLsh8x64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpRsh8Ux64 { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpConst64 { break } c1 := auxIntToInt64(v_0_0_1.AuxInt) v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c2 := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } c3 := auxIntToInt64(v_1.AuxInt) if !(uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3)) { break } v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, typ.UInt64) v0.AuxInt = int64ToAuxInt(c1 - c2 + c3) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux8 x (Const8 [c])) // result: (Rsh8Ux64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh8Ux64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh8Ux8 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x16 x (Const16 [c])) // result: (Rsh8x64 x (Const64 [int64(uint16(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst16 { break } c := auxIntToInt16(v_1.AuxInt) v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint16(c))) v.AddArg2(x, v0) return true } // match: (Rsh8x16 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x32 x (Const32 [c])) // result: (Rsh8x64 x (Const64 [int64(uint32(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst32 { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint32(c))) v.AddArg2(x, v0) return true } // match: (Rsh8x32 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x64 (Const8 [c]) (Const64 [d])) // result: (Const8 [c >> uint64(d)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c >> uint64(d)) return true } // match: (Rsh8x64 x (Const64 [0])) // result: x for { x := v_0 if v_1.Op != OpConst64 || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(x) return true } // match: (Rsh8x64 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Rsh8x64 (Rsh8x64 x (Const64 [c])) (Const64 [d])) // cond: !uaddOvf(c,d) // result: (Rsh8x64 x (Const64 [c+d])) for { t := v.Type if v_0.Op != OpRsh8x64 { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } c := auxIntToInt64(v_0_1.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) if !(!uaddOvf(c, d)) { break } v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c + d) v.AddArg2(x, v0) return true } return false } func rewriteValuegeneric_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x8 x (Const8 [c])) // result: (Rsh8x64 x (Const64 [int64(uint8(c))])) for { t := v.Type x := v_0 if v_1.Op != OpConst8 { break } c := auxIntToInt8(v_1.AuxInt) v.reset(OpRsh8x64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(int64(uint8(c))) v.AddArg2(x, v0) return true } // match: (Rsh8x8 (Const8 [0]) _) // result: (Const8 [0]) for { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpSelect0(v *Value) bool { v_0 := v.Args[0] // match: (Select0 (Div128u (Const64 [0]) lo y)) // result: (Div64u lo y) for { if v_0.Op != OpDiv128u { break } y := v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { break } lo := v_0.Args[1] v.reset(OpDiv64u) v.AddArg2(lo, y) return true } // match: (Select0 (Mul32uover (Const32 [1]) x)) // result: x for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_0_1 v.copyOf(x) return true } break } // match: (Select0 (Mul64uover (Const64 [1]) x)) // result: x for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 1 { continue } x := v_0_1 v.copyOf(x) return true } break } // match: (Select0 (Mul64uover (Const64 [0]) x)) // result: (Const64 [0]) for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (Select0 (Mul32uover (Const32 [0]) x)) // result: (Const32 [0]) for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 0 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } break } return false } func rewriteValuegeneric_OpSelect1(v *Value) bool { v_0 := v.Args[0] // match: (Select1 (Div128u (Const64 [0]) lo y)) // result: (Mod64u lo y) for { if v_0.Op != OpDiv128u { break } y := v_0.Args[2] v_0_0 := v_0.Args[0] if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { break } lo := v_0.Args[1] v.reset(OpMod64u) v.AddArg2(lo, y) return true } // match: (Select1 (Mul32uover (Const32 [1]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (Select1 (Mul64uover (Const64 [1]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 1 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (Select1 (Mul64uover (Const64 [0]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul64uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 || auxIntToInt64(v_0_0.AuxInt) != 0 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } // match: (Select1 (Mul32uover (Const32 [0]) x)) // result: (ConstBool [false]) for { if v_0.Op != OpMul32uover { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 || auxIntToInt32(v_0_0.AuxInt) != 0 { continue } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } break } return false } func rewriteValuegeneric_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] (MakeResult x ___)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpMakeResult || len(v_0.Args) < 1 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (SelectN [1] (MakeResult x y ___)) // result: y for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpMakeResult || len(v_0.Args) < 2 { break } y := v_0.Args[1] v.copyOf(y) return true } // match: (SelectN [2] (MakeResult x y z ___)) // result: z for { if auxIntToInt64(v.AuxInt) != 2 || v_0.Op != OpMakeResult || len(v_0.Args) < 3 { break } z := v_0.Args[2] v.copyOf(z) return true } // match: (SelectN [0] call:(StaticCall {sym} s1:(Store _ (Const64 [sz]) s2:(Store _ src s3:(Store {t} _ dst mem))))) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call) // result: (Move {t.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpStore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpConst64 { break } sz := auxIntToInt64(s1_1.AuxInt) s2 := s1.Args[2] if s2.Op != OpStore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpStore { break } t := auxToType(s3.Aux) mem := s3.Args[2] dst := s3.Args[1] if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(t.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticCall {sym} s1:(Store _ (Const32 [sz]) s2:(Store _ src s3:(Store {t} _ dst mem))))) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call) // result: (Move {t.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpStore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpConst32 { break } sz := auxIntToInt32(s1_1.AuxInt) s2 := s1.Args[2] if s2.Op != OpStore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpStore { break } t := auxToType(s3.Aux) mem := s3.Args[2] dst := s3.Args[1] if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && t.IsPtr() && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, int64(sz), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(t.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticCall {sym} dst src (Const64 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst64 { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticCall {sym} dst src (Const32 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticCall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst32 { break } sz := auxIntToInt32(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticLECall {sym} dst src (Const64 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst64 { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticLECall {sym} dst src (Const32 [sz]) mem)) // cond: sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call) // result: (Move {dst.Type.Elem()} [int64(sz)] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpConst32 { break } sz := auxIntToInt32(call_2.AuxInt) if !(sz >= 0 && call.Uses == 1 && isSameCall(sym, "runtime.memmove") && dst.Type.IsPtr() && isInlinableMemmove(dst, src, int64(sz), config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(int64(sz)) v.Aux = typeToAux(dst.Type.Elem()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(StaticLECall {sym} a x)) // cond: needRaceCleanup(sym, call) && clobber(call) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 2 { break } sym := auxToCall(call.Aux) x := call.Args[1] if !(needRaceCleanup(sym, call) && clobber(call)) { break } v.copyOf(x) return true } // match: (SelectN [0] call:(StaticLECall {sym} x)) // cond: needRaceCleanup(sym, call) && clobber(call) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpStaticLECall || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) x := call.Args[0] if !(needRaceCleanup(sym, call) && clobber(call)) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt16to32(v *Value) bool { v_0 := v.Args[0] // match: (SignExt16to32 (Const16 [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } // match: (SignExt16to32 (Trunc32to16 x:(Rsh32x64 _ (Const64 [s])))) // cond: s >= 16 // result: x for { if v_0.Op != OpTrunc32to16 { break } x := v_0.Args[0] if x.Op != OpRsh32x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 16) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt16to64(v *Value) bool { v_0 := v.Args[0] // match: (SignExt16to64 (Const16 [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } // match: (SignExt16to64 (Trunc64to16 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 48 // result: x for { if v_0.Op != OpTrunc64to16 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 48) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt32to64(v *Value) bool { v_0 := v.Args[0] // match: (SignExt32to64 (Const32 [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } // match: (SignExt32to64 (Trunc64to32 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 32 // result: x for { if v_0.Op != OpTrunc64to32 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 32) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt8to16(v *Value) bool { v_0 := v.Args[0] // match: (SignExt8to16 (Const8 [c])) // result: (Const16 [int16(c)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(c)) return true } // match: (SignExt8to16 (Trunc16to8 x:(Rsh16x64 _ (Const64 [s])))) // cond: s >= 8 // result: x for { if v_0.Op != OpTrunc16to8 { break } x := v_0.Args[0] if x.Op != OpRsh16x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 8) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt8to32(v *Value) bool { v_0 := v.Args[0] // match: (SignExt8to32 (Const8 [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } // match: (SignExt8to32 (Trunc32to8 x:(Rsh32x64 _ (Const64 [s])))) // cond: s >= 24 // result: x for { if v_0.Op != OpTrunc32to8 { break } x := v_0.Args[0] if x.Op != OpRsh32x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 24) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSignExt8to64(v *Value) bool { v_0 := v.Args[0] // match: (SignExt8to64 (Const8 [c])) // result: (Const64 [int64(c)]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(c)) return true } // match: (SignExt8to64 (Trunc64to8 x:(Rsh64x64 _ (Const64 [s])))) // cond: s >= 56 // result: x for { if v_0.Op != OpTrunc64to8 { break } x := v_0.Args[0] if x.Op != OpRsh64x64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 56) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpSliceCap(v *Value) bool { v_0 := v.Args[0] // match: (SliceCap (SliceMake _ _ (Const64 [c]))) // result: (Const64 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpConst64 { break } t := v_0_2.Type c := auxIntToInt64(v_0_2.AuxInt) v.reset(OpConst64) v.Type = t v.AuxInt = int64ToAuxInt(c) return true } // match: (SliceCap (SliceMake _ _ (Const32 [c]))) // result: (Const32 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpConst32 { break } t := v_0_2.Type c := auxIntToInt32(v_0_2.AuxInt) v.reset(OpConst32) v.Type = t v.AuxInt = int32ToAuxInt(c) return true } // match: (SliceCap (SliceMake _ _ (SliceCap x))) // result: (SliceCap x) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpSliceCap { break } x := v_0_2.Args[0] v.reset(OpSliceCap) v.AddArg(x) return true } // match: (SliceCap (SliceMake _ _ (SliceLen x))) // result: (SliceLen x) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[2] v_0_2 := v_0.Args[2] if v_0_2.Op != OpSliceLen { break } x := v_0_2.Args[0] v.reset(OpSliceLen) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSliceLen(v *Value) bool { v_0 := v.Args[0] // match: (SliceLen (SliceMake _ (Const64 [c]) _)) // result: (Const64 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type c := auxIntToInt64(v_0_1.AuxInt) v.reset(OpConst64) v.Type = t v.AuxInt = int64ToAuxInt(c) return true } // match: (SliceLen (SliceMake _ (Const32 [c]) _)) // result: (Const32 [c]) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst32 { break } t := v_0_1.Type c := auxIntToInt32(v_0_1.AuxInt) v.reset(OpConst32) v.Type = t v.AuxInt = int32ToAuxInt(c) return true } // match: (SliceLen (SliceMake _ (SliceLen x) _)) // result: (SliceLen x) for { if v_0.Op != OpSliceMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpSliceLen { break } x := v_0_1.Args[0] v.reset(OpSliceLen) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSlicePtr(v *Value) bool { v_0 := v.Args[0] // match: (SlicePtr (SliceMake (SlicePtr x) _ _)) // result: (SlicePtr x) for { if v_0.Op != OpSliceMake { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpSlicePtr { break } x := v_0_0.Args[0] v.reset(OpSlicePtr) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSlicemask(v *Value) bool { v_0 := v.Args[0] // match: (Slicemask (Const32 [x])) // cond: x > 0 // result: (Const32 [-1]) for { if v_0.Op != OpConst32 { break } x := auxIntToInt32(v_0.AuxInt) if !(x > 0) { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } // match: (Slicemask (Const32 [0])) // result: (Const32 [0]) for { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Slicemask (Const64 [x])) // cond: x > 0 // result: (Const64 [-1]) for { if v_0.Op != OpConst64 { break } x := auxIntToInt64(v_0.AuxInt) if !(x > 0) { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } // match: (Slicemask (Const64 [0])) // result: (Const64 [0]) for { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValuegeneric_OpSqrt(v *Value) bool { v_0 := v.Args[0] // match: (Sqrt (Const64F [c])) // cond: !math.IsNaN(math.Sqrt(c)) // result: (Const64F [math.Sqrt(c)]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if !(!math.IsNaN(math.Sqrt(c))) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(math.Sqrt(c)) return true } return false } func rewriteValuegeneric_OpStaticLECall(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [1]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) // result: (MakeResult (Eq8 (Load sptr mem) (Const8 [int8(read8(scon,0))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 1 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon)) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq8, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int8) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst8, typ.Int8) v2.AuxInt = int8ToAuxInt(int8(read8(scon, 0))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [2]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) // result: (MakeResult (Eq16 (Load sptr mem) (Const16 [int16(read16(scon,0,config.ctxt.Arch.ByteOrder))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 2 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config)) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq16, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int16) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst16, typ.Int16) v2.AuxInt = int16ToAuxInt(int16(read16(scon, 0, config.ctxt.Arch.ByteOrder))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [4]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) // result: (MakeResult (Eq32 (Load sptr mem) (Const32 [int32(read32(scon,0,config.ctxt.Arch.ByteOrder))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 4 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config)) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq32, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int32) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst32, typ.Int32) v2.AuxInt = int32ToAuxInt(int32(read32(scon, 0, config.ctxt.Arch.ByteOrder))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } // match: (StaticLECall {callAux} sptr (Addr {scon} (SB)) (Const64 [8]) mem) // cond: isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) && config.PtrSize == 8 // result: (MakeResult (Eq64 (Load sptr mem) (Const64 [int64(read64(scon,0,config.ctxt.Arch.ByteOrder))])) mem) for { if len(v.Args) != 4 { break } callAux := auxToCall(v.Aux) mem := v.Args[3] sptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAddr { break } scon := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } v_2 := v.Args[2] if v_2.Op != OpConst64 || auxIntToInt64(v_2.AuxInt) != 8 || !(isSameCall(callAux, "runtime.memequal") && symIsRO(scon) && canLoadUnaligned(config) && config.PtrSize == 8) { break } v.reset(OpMakeResult) v0 := b.NewValue0(v.Pos, OpEq64, typ.Bool) v1 := b.NewValue0(v.Pos, OpLoad, typ.Int64) v1.AddArg2(sptr, mem) v2 := b.NewValue0(v.Pos, OpConst64, typ.Int64) v2.AuxInt = int64ToAuxInt(int64(read64(scon, 0, config.ctxt.Arch.ByteOrder))) v0.AddArg2(v1, v2) v.AddArg2(v0, mem) return true } return false } func rewriteValuegeneric_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (Store {t1} p1 (Load p2 mem) mem) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type mem := v_1.Args[1] p2 := v_1.Args[0] if mem != v_2 || !(isSamePtr(p1, p2) && t2.Size() == t1.Size()) { break } v.copyOf(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ oldmem)) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v_2 if mem.Op != OpStore { break } t3 := auxToType(mem.Aux) _ = mem.Args[2] p3 := mem.Args[0] if oldmem != mem.Args[2] || !(isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ (Store {t4} p4 _ oldmem))) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size()) // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v_2 if mem.Op != OpStore { break } t3 := auxToType(mem.Aux) _ = mem.Args[2] p3 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t4 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p4 := mem_2.Args[0] if oldmem != mem_2.Args[2] || !(isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} p1 (Load p2 oldmem) mem:(Store {t3} p3 _ (Store {t4} p4 _ (Store {t5} p5 _ oldmem)))) // cond: isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size()) && disjoint(p1, t1.Size(), p5, t5.Size()) // result: mem for { t1 := auxToType(v.Aux) p1 := v_0 if v_1.Op != OpLoad { break } t2 := v_1.Type oldmem := v_1.Args[1] p2 := v_1.Args[0] mem := v_2 if mem.Op != OpStore { break } t3 := auxToType(mem.Aux) _ = mem.Args[2] p3 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t4 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p4 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t5 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] p5 := mem_2_2.Args[0] if oldmem != mem_2_2.Args[2] || !(isSamePtr(p1, p2) && t2.Size() == t1.Size() && disjoint(p1, t1.Size(), p3, t3.Size()) && disjoint(p1, t1.Size(), p4, t4.Size()) && disjoint(p1, t1.Size(), p5, t5.Size())) { break } v.copyOf(mem) return true } // match: (Store {t} (OffPtr [o] p1) x mem:(Zero [n] p2 _)) // cond: isConstZero(x) && o >= 0 && t.Size() + o <= n && isSamePtr(p1, p2) // result: mem for { t := auxToType(v.Aux) if v_0.Op != OpOffPtr { break } o := auxIntToInt64(v_0.AuxInt) p1 := v_0.Args[0] x := v_1 mem := v_2 if mem.Op != OpZero { break } n := auxIntToInt64(mem.AuxInt) p2 := mem.Args[0] if !(isConstZero(x) && o >= 0 && t.Size()+o <= n && isSamePtr(p1, p2)) { break } v.copyOf(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Zero [n] p3 _))) // cond: isConstZero(x) && o1 >= 0 && t1.Size() + o1 <= n && isSamePtr(p1, p3) && disjoint(op, t1.Size(), p2, t2.Size()) // result: mem for { t1 := auxToType(v.Aux) op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] x := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpZero { break } n := auxIntToInt64(mem_2.AuxInt) p3 := mem_2.Args[0] if !(isConstZero(x) && o1 >= 0 && t1.Size()+o1 <= n && isSamePtr(p1, p3) && disjoint(op, t1.Size(), p2, t2.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Store {t3} p3 _ (Zero [n] p4 _)))) // cond: isConstZero(x) && o1 >= 0 && t1.Size() + o1 <= n && isSamePtr(p1, p4) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) // result: mem for { t1 := auxToType(v.Aux) op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] x := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p3 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpZero { break } n := auxIntToInt64(mem_2_2.AuxInt) p4 := mem_2_2.Args[0] if !(isConstZero(x) && o1 >= 0 && t1.Size()+o1 <= n && isSamePtr(p1, p4) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size())) { break } v.copyOf(mem) return true } // match: (Store {t1} op:(OffPtr [o1] p1) x mem:(Store {t2} p2 _ (Store {t3} p3 _ (Store {t4} p4 _ (Zero [n] p5 _))))) // cond: isConstZero(x) && o1 >= 0 && t1.Size() + o1 <= n && isSamePtr(p1, p5) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size()) // result: mem for { t1 := auxToType(v.Aux) op := v_0 if op.Op != OpOffPtr { break } o1 := auxIntToInt64(op.AuxInt) p1 := op.Args[0] x := v_1 mem := v_2 if mem.Op != OpStore { break } t2 := auxToType(mem.Aux) _ = mem.Args[2] p2 := mem.Args[0] mem_2 := mem.Args[2] if mem_2.Op != OpStore { break } t3 := auxToType(mem_2.Aux) _ = mem_2.Args[2] p3 := mem_2.Args[0] mem_2_2 := mem_2.Args[2] if mem_2_2.Op != OpStore { break } t4 := auxToType(mem_2_2.Aux) _ = mem_2_2.Args[2] p4 := mem_2_2.Args[0] mem_2_2_2 := mem_2_2.Args[2] if mem_2_2_2.Op != OpZero { break } n := auxIntToInt64(mem_2_2_2.AuxInt) p5 := mem_2_2_2.Args[0] if !(isConstZero(x) && o1 >= 0 && t1.Size()+o1 <= n && isSamePtr(p1, p5) && disjoint(op, t1.Size(), p2, t2.Size()) && disjoint(op, t1.Size(), p3, t3.Size()) && disjoint(op, t1.Size(), p4, t4.Size())) { break } v.copyOf(mem) return true } // match: (Store _ (StructMake0) mem) // result: mem for { if v_1.Op != OpStructMake0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Store dst (StructMake1 f0) mem) // result: (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem) for { dst := v_0 if v_1.Op != OpStructMake1 { break } t := v_1.Type f0 := v_1.Args[0] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(0)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v0.AuxInt = int64ToAuxInt(0) v0.AddArg(dst) v.AddArg3(v0, f0, mem) return true } // match: (Store dst (StructMake2 f0 f1) mem) // result: (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem)) for { dst := v_0 if v_1.Op != OpStructMake2 { break } t := v_1.Type f1 := v_1.Args[1] f0 := v_1.Args[0] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(1)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v0.AuxInt = int64ToAuxInt(t.FieldOff(1)) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t.FieldType(0)) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v2.AuxInt = int64ToAuxInt(0) v2.AddArg(dst) v1.AddArg3(v2, f0, mem) v.AddArg3(v0, f1, v1) return true } // match: (Store dst (StructMake3 f0 f1 f2) mem) // result: (Store {t.FieldType(2)} (OffPtr [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem))) for { dst := v_0 if v_1.Op != OpStructMake3 { break } t := v_1.Type f2 := v_1.Args[2] f0 := v_1.Args[0] f1 := v_1.Args[1] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(2)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v0.AuxInt = int64ToAuxInt(t.FieldOff(2)) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t.FieldType(1)) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v2.AuxInt = int64ToAuxInt(t.FieldOff(1)) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t.FieldType(0)) v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v4.AuxInt = int64ToAuxInt(0) v4.AddArg(dst) v3.AddArg3(v4, f0, mem) v1.AddArg3(v2, f1, v3) v.AddArg3(v0, f2, v1) return true } // match: (Store dst (StructMake4 f0 f1 f2 f3) mem) // result: (Store {t.FieldType(3)} (OffPtr [t.FieldOff(3)] dst) f3 (Store {t.FieldType(2)} (OffPtr [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr [0] dst) f0 mem)))) for { dst := v_0 if v_1.Op != OpStructMake4 { break } t := v_1.Type f3 := v_1.Args[3] f0 := v_1.Args[0] f1 := v_1.Args[1] f2 := v_1.Args[2] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(t.FieldType(3)) v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo()) v0.AuxInt = int64ToAuxInt(t.FieldOff(3)) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t.FieldType(2)) v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo()) v2.AuxInt = int64ToAuxInt(t.FieldOff(2)) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v3.Aux = typeToAux(t.FieldType(1)) v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo()) v4.AuxInt = int64ToAuxInt(t.FieldOff(1)) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v5.Aux = typeToAux(t.FieldType(0)) v6 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo()) v6.AuxInt = int64ToAuxInt(0) v6.AddArg(dst) v5.AddArg3(v6, f0, mem) v3.AddArg3(v4, f1, v5) v1.AddArg3(v2, f2, v3) v.AddArg3(v0, f3, v1) return true } // match: (Store {t} dst (Load src mem) mem) // cond: !fe.CanSSA(t) // result: (Move {t} [t.Size()] dst src mem) for { t := auxToType(v.Aux) dst := v_0 if v_1.Op != OpLoad { break } mem := v_1.Args[1] src := v_1.Args[0] if mem != v_2 || !(!fe.CanSSA(t)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(t.Size()) v.Aux = typeToAux(t) v.AddArg3(dst, src, mem) return true } // match: (Store {t} dst (Load src mem) (VarDef {x} mem)) // cond: !fe.CanSSA(t) // result: (Move {t} [t.Size()] dst src (VarDef {x} mem)) for { t := auxToType(v.Aux) dst := v_0 if v_1.Op != OpLoad { break } mem := v_1.Args[1] src := v_1.Args[0] if v_2.Op != OpVarDef { break } x := auxToSym(v_2.Aux) if mem != v_2.Args[0] || !(!fe.CanSSA(t)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(t.Size()) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg3(dst, src, v0) return true } // match: (Store _ (ArrayMake0) mem) // result: mem for { if v_1.Op != OpArrayMake0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Store dst (ArrayMake1 e) mem) // result: (Store {e.Type} dst e mem) for { dst := v_0 if v_1.Op != OpArrayMake1 { break } e := v_1.Args[0] mem := v_2 v.reset(OpStore) v.Aux = typeToAux(e.Type) v.AddArg3(dst, e, mem) return true } // match: (Store (SelectN [0] call:(StaticLECall _ _)) x mem:(SelectN [1] call)) // cond: isConstZero(x) && isSameCall(call.Aux, "runtime.newobject") // result: mem for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { break } call := v_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 { break } x := v_1 mem := v_2 if mem.Op != OpSelectN || auxIntToInt64(mem.AuxInt) != 1 || call != mem.Args[0] || !(isConstZero(x) && isSameCall(call.Aux, "runtime.newobject")) { break } v.copyOf(mem) return true } // match: (Store (OffPtr (SelectN [0] call:(StaticLECall _ _))) x mem:(SelectN [1] call)) // cond: isConstZero(x) && isSameCall(call.Aux, "runtime.newobject") // result: mem for { if v_0.Op != OpOffPtr { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpSelectN || auxIntToInt64(v_0_0.AuxInt) != 0 { break } call := v_0_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 { break } x := v_1 mem := v_2 if mem.Op != OpSelectN || auxIntToInt64(mem.AuxInt) != 1 || call != mem.Args[0] || !(isConstZero(x) && isSameCall(call.Aux, "runtime.newobject")) { break } v.copyOf(mem) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [0] p2) d2 m3:(Move [n] p3 _ mem))) // cond: m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 mem)) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr || auxIntToInt64(op2.AuxInt) != 0 { break } p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpMove { break } n := auxIntToInt64(m3.AuxInt) mem := m3.Args[2] p3 := m3.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v0.AddArg3(op2, d2, mem) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Move [n] p4 _ mem)))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 mem))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr || auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpMove { break } n := auxIntToInt64(m4.AuxInt) mem := m4.Args[2] p4 := m4.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v1.AddArg3(op3, d3, mem) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Move [n] p5 _ mem))))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size() + t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 (Store {t4} op4 d4 mem)))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpStore { break } t4 := auxToType(m4.Aux) _ = m4.Args[2] op4 := m4.Args[0] if op4.Op != OpOffPtr || auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] d4 := m4.Args[1] m5 := m4.Args[2] if m5.Op != OpMove { break } n := auxIntToInt64(m5.AuxInt) mem := m5.Args[2] p5 := m5.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size()+t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v2.Aux = typeToAux(t4) v2.AddArg3(op4, d4, mem) v1.AddArg3(op3, d3, v2) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [0] p2) d2 m3:(Zero [n] p3 mem))) // cond: m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 mem)) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr || auxIntToInt64(op2.AuxInt) != 0 { break } p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpZero { break } n := auxIntToInt64(m3.AuxInt) mem := m3.Args[1] p3 := m3.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && o1 == t2.Size() && n == t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && clobber(m2, m3)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v0.AddArg3(op2, d2, mem) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [0] p3) d3 m4:(Zero [n] p4 mem)))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 mem))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr || auxIntToInt64(op3.AuxInt) != 0 { break } p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpZero { break } n := auxIntToInt64(m4.AuxInt) mem := m4.Args[1] p4 := m4.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && o2 == t3.Size() && o1-o2 == t2.Size() && n == t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && clobber(m2, m3, m4)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v1.AddArg3(op3, d3, mem) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } // match: (Store {t1} op1:(OffPtr [o1] p1) d1 m2:(Store {t2} op2:(OffPtr [o2] p2) d2 m3:(Store {t3} op3:(OffPtr [o3] p3) d3 m4:(Store {t4} op4:(OffPtr [0] p4) d4 m5:(Zero [n] p5 mem))))) // cond: m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size() + t3.Size() + t2.Size() + t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5) // result: (Store {t1} op1 d1 (Store {t2} op2 d2 (Store {t3} op3 d3 (Store {t4} op4 d4 mem)))) for { t1 := auxToType(v.Aux) op1 := v_0 if op1.Op != OpOffPtr { break } o1 := auxIntToInt64(op1.AuxInt) p1 := op1.Args[0] d1 := v_1 m2 := v_2 if m2.Op != OpStore { break } t2 := auxToType(m2.Aux) _ = m2.Args[2] op2 := m2.Args[0] if op2.Op != OpOffPtr { break } o2 := auxIntToInt64(op2.AuxInt) p2 := op2.Args[0] d2 := m2.Args[1] m3 := m2.Args[2] if m3.Op != OpStore { break } t3 := auxToType(m3.Aux) _ = m3.Args[2] op3 := m3.Args[0] if op3.Op != OpOffPtr { break } o3 := auxIntToInt64(op3.AuxInt) p3 := op3.Args[0] d3 := m3.Args[1] m4 := m3.Args[2] if m4.Op != OpStore { break } t4 := auxToType(m4.Aux) _ = m4.Args[2] op4 := m4.Args[0] if op4.Op != OpOffPtr || auxIntToInt64(op4.AuxInt) != 0 { break } p4 := op4.Args[0] d4 := m4.Args[1] m5 := m4.Args[2] if m5.Op != OpZero { break } n := auxIntToInt64(m5.AuxInt) mem := m5.Args[1] p5 := m5.Args[0] if !(m2.Uses == 1 && m3.Uses == 1 && m4.Uses == 1 && m5.Uses == 1 && o3 == t4.Size() && o2-o3 == t3.Size() && o1-o2 == t2.Size() && n == t4.Size()+t3.Size()+t2.Size()+t1.Size() && isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && clobber(m2, m3, m4, m5)) { break } v.reset(OpStore) v.Aux = typeToAux(t1) v0 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v0.Aux = typeToAux(t2) v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v1.Aux = typeToAux(t3) v2 := b.NewValue0(v.Pos, OpStore, types.TypeMem) v2.Aux = typeToAux(t4) v2.AddArg3(op4, d4, mem) v1.AddArg3(op3, d3, v2) v0.AddArg3(op2, d2, v1) v.AddArg3(op1, d1, v0) return true } return false } func rewriteValuegeneric_OpStringLen(v *Value) bool { v_0 := v.Args[0] // match: (StringLen (StringMake _ (Const64 [c]))) // result: (Const64 [c]) for { if v_0.Op != OpStringMake { break } _ = v_0.Args[1] v_0_1 := v_0.Args[1] if v_0_1.Op != OpConst64 { break } t := v_0_1.Type c := auxIntToInt64(v_0_1.AuxInt) v.reset(OpConst64) v.Type = t v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValuegeneric_OpStringPtr(v *Value) bool { v_0 := v.Args[0] // match: (StringPtr (StringMake (Addr {s} base) _)) // result: (Addr {s} base) for { if v_0.Op != OpStringMake { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAddr { break } t := v_0_0.Type s := auxToSym(v_0_0.Aux) base := v_0_0.Args[0] v.reset(OpAddr) v.Type = t v.Aux = symToAux(s) v.AddArg(base) return true } return false } func rewriteValuegeneric_OpStructSelect(v *Value) bool { v_0 := v.Args[0] b := v.Block fe := b.Func.fe // match: (StructSelect (StructMake1 x)) // result: x for { if v_0.Op != OpStructMake1 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [0] (StructMake2 x _)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpStructMake2 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [1] (StructMake2 _ x)) // result: x for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStructMake2 { break } x := v_0.Args[1] v.copyOf(x) return true } // match: (StructSelect [0] (StructMake3 x _ _)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpStructMake3 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [1] (StructMake3 _ x _)) // result: x for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStructMake3 { break } x := v_0.Args[1] v.copyOf(x) return true } // match: (StructSelect [2] (StructMake3 _ _ x)) // result: x for { if auxIntToInt64(v.AuxInt) != 2 || v_0.Op != OpStructMake3 { break } x := v_0.Args[2] v.copyOf(x) return true } // match: (StructSelect [0] (StructMake4 x _ _ _)) // result: x for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpStructMake4 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (StructSelect [1] (StructMake4 _ x _ _)) // result: x for { if auxIntToInt64(v.AuxInt) != 1 || v_0.Op != OpStructMake4 { break } x := v_0.Args[1] v.copyOf(x) return true } // match: (StructSelect [2] (StructMake4 _ _ x _)) // result: x for { if auxIntToInt64(v.AuxInt) != 2 || v_0.Op != OpStructMake4 { break } x := v_0.Args[2] v.copyOf(x) return true } // match: (StructSelect [3] (StructMake4 _ _ _ x)) // result: x for { if auxIntToInt64(v.AuxInt) != 3 || v_0.Op != OpStructMake4 { break } x := v_0.Args[3] v.copyOf(x) return true } // match: (StructSelect [i] x:(Load ptr mem)) // cond: !fe.CanSSA(t) // result: @x.Block (Load (OffPtr [t.FieldOff(int(i))] ptr) mem) for { i := auxIntToInt64(v.AuxInt) x := v_0 if x.Op != OpLoad { break } t := x.Type mem := x.Args[1] ptr := x.Args[0] if !(!fe.CanSSA(t)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpLoad, v.Type) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, v.Type.PtrTo()) v1.AuxInt = int64ToAuxInt(t.FieldOff(int(i))) v1.AddArg(ptr) v0.AddArg2(v1, mem) return true } // match: (StructSelect [0] (IData x)) // result: (IData x) for { if auxIntToInt64(v.AuxInt) != 0 || v_0.Op != OpIData { break } x := v_0.Args[0] v.reset(OpIData) v.AddArg(x) return true } return false } func rewriteValuegeneric_OpSub16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c-d]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { break } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c - d) return true } // match: (Sub16 x (Const16 [c])) // cond: x.Op != OpConst16 // result: (Add16 (Const16 [-c]) x) for { x := v_0 if v_1.Op != OpConst16 { break } t := v_1.Type c := auxIntToInt16(v_1.AuxInt) if !(x.Op != OpConst16) { break } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub16 (Mul16 x y) (Mul16 x z)) // result: (Mul16 x (Sub16 y z)) for { t := v.Type if v_0.Op != OpMul16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub16 x x) // result: (Const16 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Sub16 (Neg16 x) (Com16 x)) // result: (Const16 [1]) for { if v_0.Op != OpNeg16 { break } x := v_0.Args[0] if v_1.Op != OpCom16 || x != v_1.Args[0] { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(1) return true } // match: (Sub16 (Com16 x) (Neg16 x)) // result: (Const16 [-1]) for { if v_0.Op != OpCom16 { break } x := v_0.Args[0] if v_1.Op != OpNeg16 || x != v_1.Args[0] { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } // match: (Sub16 (Add16 x y) x) // result: y for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub16 (Add16 x y) y) // result: x for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub16 (Sub16 x y) x) // result: (Neg16 y) for { if v_0.Op != OpSub16 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg16) v.AddArg(y) return true } // match: (Sub16 x (Add16 x y)) // result: (Neg16 y) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg16) v.AddArg(y) return true } break } // match: (Sub16 x (Sub16 i:(Const16 ) z)) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Add16 x z) i) for { x := v_0 if v_1.Op != OpSub16 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst16 { break } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub16 x (Add16 z i:(Const16 ))) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 (Sub16 x z) i) for { x := v_0 if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst16 { continue } t := i.Type if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub16 (Sub16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Sub16 i (Add16 z x)) for { if v_0.Op != OpSub16 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst16 { break } t := i.Type x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { break } v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpAdd16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub16 (Add16 z i:(Const16 )) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Add16 i (Sub16 z x)) for { if v_0.Op != OpAdd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst16 { continue } t := i.Type x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpSub16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub16 (Const16 [c]) (Sub16 (Const16 [d]) x)) // result: (Add16 (Const16 [c-d]) x) for { if v_0.Op != OpConst16 { break } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpSub16 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst16 || v_1_0.Type != t { break } d := auxIntToInt16(v_1_0.AuxInt) v.reset(OpAdd16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub16 (Const16 [c]) (Add16 (Const16 [d]) x)) // result: (Sub16 (Const16 [c-d]) x) for { if v_0.Op != OpConst16 { break } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpAdd16 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpSub32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c-d]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { break } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c - d) return true } // match: (Sub32 x (Const32 [c])) // cond: x.Op != OpConst32 // result: (Add32 (Const32 [-c]) x) for { x := v_0 if v_1.Op != OpConst32 { break } t := v_1.Type c := auxIntToInt32(v_1.AuxInt) if !(x.Op != OpConst32) { break } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub32 (Mul32 x y) (Mul32 x z)) // result: (Mul32 x (Sub32 y z)) for { t := v.Type if v_0.Op != OpMul32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub32 x x) // result: (Const32 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Sub32 (Neg32 x) (Com32 x)) // result: (Const32 [1]) for { if v_0.Op != OpNeg32 { break } x := v_0.Args[0] if v_1.Op != OpCom32 || x != v_1.Args[0] { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(1) return true } // match: (Sub32 (Com32 x) (Neg32 x)) // result: (Const32 [-1]) for { if v_0.Op != OpCom32 { break } x := v_0.Args[0] if v_1.Op != OpNeg32 || x != v_1.Args[0] { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } // match: (Sub32 (Add32 x y) x) // result: y for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub32 (Add32 x y) y) // result: x for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub32 (Sub32 x y) x) // result: (Neg32 y) for { if v_0.Op != OpSub32 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg32) v.AddArg(y) return true } // match: (Sub32 x (Add32 x y)) // result: (Neg32 y) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg32) v.AddArg(y) return true } break } // match: (Sub32 x (Sub32 i:(Const32 ) z)) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Add32 x z) i) for { x := v_0 if v_1.Op != OpSub32 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst32 { break } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub32 x (Add32 z i:(Const32 ))) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 (Sub32 x z) i) for { x := v_0 if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst32 { continue } t := i.Type if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub32 (Sub32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Sub32 i (Add32 z x)) for { if v_0.Op != OpSub32 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst32 { break } t := i.Type x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { break } v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpAdd32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub32 (Add32 z i:(Const32 )) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Add32 i (Sub32 z x)) for { if v_0.Op != OpAdd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst32 { continue } t := i.Type x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpSub32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub32 (Const32 [c]) (Sub32 (Const32 [d]) x)) // result: (Add32 (Const32 [c-d]) x) for { if v_0.Op != OpConst32 { break } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpSub32 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst32 || v_1_0.Type != t { break } d := auxIntToInt32(v_1_0.AuxInt) v.reset(OpAdd32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub32 (Const32 [c]) (Add32 (Const32 [d]) x)) // result: (Sub32 (Const32 [c-d]) x) for { if v_0.Op != OpConst32 { break } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpAdd32 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpSub32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Sub32F (Const32F [c]) (Const32F [d])) // cond: c-d == c-d // result: (Const32F [c-d]) for { if v_0.Op != OpConst32F { break } c := auxIntToFloat32(v_0.AuxInt) if v_1.Op != OpConst32F { break } d := auxIntToFloat32(v_1.AuxInt) if !(c-d == c-d) { break } v.reset(OpConst32F) v.AuxInt = float32ToAuxInt(c - d) return true } return false } func rewriteValuegeneric_OpSub64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c-d]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { break } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c - d) return true } // match: (Sub64 x (Const64 [c])) // cond: x.Op != OpConst64 // result: (Add64 (Const64 [-c]) x) for { x := v_0 if v_1.Op != OpConst64 { break } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(x.Op != OpConst64) { break } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub64 (Mul64 x y) (Mul64 x z)) // result: (Mul64 x (Sub64 y z)) for { t := v.Type if v_0.Op != OpMul64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub64 x x) // result: (Const64 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Sub64 (Neg64 x) (Com64 x)) // result: (Const64 [1]) for { if v_0.Op != OpNeg64 { break } x := v_0.Args[0] if v_1.Op != OpCom64 || x != v_1.Args[0] { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(1) return true } // match: (Sub64 (Com64 x) (Neg64 x)) // result: (Const64 [-1]) for { if v_0.Op != OpCom64 { break } x := v_0.Args[0] if v_1.Op != OpNeg64 || x != v_1.Args[0] { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } // match: (Sub64 (Add64 x y) x) // result: y for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub64 (Add64 x y) y) // result: x for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub64 (Sub64 x y) x) // result: (Neg64 y) for { if v_0.Op != OpSub64 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg64) v.AddArg(y) return true } // match: (Sub64 x (Add64 x y)) // result: (Neg64 y) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg64) v.AddArg(y) return true } break } // match: (Sub64 x (Sub64 i:(Const64 ) z)) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Add64 x z) i) for { x := v_0 if v_1.Op != OpSub64 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst64 { break } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub64 x (Add64 z i:(Const64 ))) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 (Sub64 x z) i) for { x := v_0 if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst64 { continue } t := i.Type if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub64 (Sub64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Sub64 i (Add64 z x)) for { if v_0.Op != OpSub64 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst64 { break } t := i.Type x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { break } v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpAdd64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub64 (Add64 z i:(Const64 )) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Add64 i (Sub64 z x)) for { if v_0.Op != OpAdd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst64 { continue } t := i.Type x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpSub64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub64 (Const64 [c]) (Sub64 (Const64 [d]) x)) // result: (Add64 (Const64 [c-d]) x) for { if v_0.Op != OpConst64 { break } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpSub64 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst64 || v_1_0.Type != t { break } d := auxIntToInt64(v_1_0.AuxInt) v.reset(OpAdd64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub64 (Const64 [c]) (Add64 (Const64 [d]) x)) // result: (Sub64 (Const64 [c-d]) x) for { if v_0.Op != OpConst64 { break } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAdd64 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpSub64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Sub64F (Const64F [c]) (Const64F [d])) // cond: c-d == c-d // result: (Const64F [c-d]) for { if v_0.Op != OpConst64F { break } c := auxIntToFloat64(v_0.AuxInt) if v_1.Op != OpConst64F { break } d := auxIntToFloat64(v_1.AuxInt) if !(c-d == c-d) { break } v.reset(OpConst64F) v.AuxInt = float64ToAuxInt(c - d) return true } return false } func rewriteValuegeneric_OpSub8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Sub8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c-d]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { break } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c - d) return true } // match: (Sub8 x (Const8 [c])) // cond: x.Op != OpConst8 // result: (Add8 (Const8 [-c]) x) for { x := v_0 if v_1.Op != OpConst8 { break } t := v_1.Type c := auxIntToInt8(v_1.AuxInt) if !(x.Op != OpConst8) { break } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(-c) v.AddArg2(v0, x) return true } // match: (Sub8 (Mul8 x y) (Mul8 x z)) // result: (Mul8 x (Sub8 y z)) for { t := v.Type if v_0.Op != OpMul8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if v_1.Op != OpMul8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } z := v_1_1 v.reset(OpMul8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } } break } // match: (Sub8 x x) // result: (Const8 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Sub8 (Neg8 x) (Com8 x)) // result: (Const8 [1]) for { if v_0.Op != OpNeg8 { break } x := v_0.Args[0] if v_1.Op != OpCom8 || x != v_1.Args[0] { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(1) return true } // match: (Sub8 (Com8 x) (Neg8 x)) // result: (Const8 [-1]) for { if v_0.Op != OpCom8 { break } x := v_0.Args[0] if v_1.Op != OpNeg8 || x != v_1.Args[0] { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } // match: (Sub8 (Add8 x y) x) // result: y for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if x != v_1 { continue } v.copyOf(y) return true } break } // match: (Sub8 (Add8 x y) y) // result: x for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if y != v_1 { continue } v.copyOf(x) return true } break } // match: (Sub8 (Sub8 x y) x) // result: (Neg8 y) for { if v_0.Op != OpSub8 { break } y := v_0.Args[1] x := v_0.Args[0] if x != v_1 { break } v.reset(OpNeg8) v.AddArg(y) return true } // match: (Sub8 x (Add8 x y)) // result: (Neg8 y) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpNeg8) v.AddArg(y) return true } break } // match: (Sub8 x (Sub8 i:(Const8 ) z)) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Add8 x z) i) for { x := v_0 if v_1.Op != OpSub8 { break } z := v_1.Args[1] i := v_1.Args[0] if i.Op != OpConst8 { break } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } // match: (Sub8 x (Add8 z i:(Const8 ))) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 (Sub8 x z) i) for { x := v_0 if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z := v_1_0 i := v_1_1 if i.Op != OpConst8 { continue } t := i.Type if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(x, z) v.AddArg2(v0, i) return true } break } // match: (Sub8 (Sub8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Sub8 i (Add8 z x)) for { if v_0.Op != OpSub8 { break } z := v_0.Args[1] i := v_0.Args[0] if i.Op != OpConst8 { break } t := i.Type x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { break } v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpAdd8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } // match: (Sub8 (Add8 z i:(Const8 )) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Add8 i (Sub8 z x)) for { if v_0.Op != OpAdd8 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z := v_0_0 i := v_0_1 if i.Op != OpConst8 { continue } t := i.Type x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpSub8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } break } // match: (Sub8 (Const8 [c]) (Sub8 (Const8 [d]) x)) // result: (Add8 (Const8 [c-d]) x) for { if v_0.Op != OpConst8 { break } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpSub8 { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpConst8 || v_1_0.Type != t { break } d := auxIntToInt8(v_1_0.AuxInt) v.reset(OpAdd8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } // match: (Sub8 (Const8 [c]) (Add8 (Const8 [d]) x)) // result: (Sub8 (Const8 [c-d]) x) for { if v_0.Op != OpConst8 { break } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpAdd8 { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpSub8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c - d) v.AddArg2(v0, x) return true } break } return false } func rewriteValuegeneric_OpTrunc16to8(v *Value) bool { v_0 := v.Args[0] // match: (Trunc16to8 (Const16 [c])) // result: (Const8 [int8(c)]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(c)) return true } // match: (Trunc16to8 (ZeroExt8to16 x)) // result: x for { if v_0.Op != OpZeroExt8to16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc16to8 (SignExt8to16 x)) // result: x for { if v_0.Op != OpSignExt8to16 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc16to8 (And16 (Const16 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc16to8 x) for { if v_0.Op != OpAnd16 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst16 { continue } y := auxIntToInt16(v_0_0.AuxInt) x := v_0_1 if !(y&0xFF == 0xFF) { continue } v.reset(OpTrunc16to8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc32to16(v *Value) bool { v_0 := v.Args[0] // match: (Trunc32to16 (Const32 [c])) // result: (Const16 [int16(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(c)) return true } // match: (Trunc32to16 (ZeroExt8to32 x)) // result: (ZeroExt8to16 x) for { if v_0.Op != OpZeroExt8to32 { break } x := v_0.Args[0] v.reset(OpZeroExt8to16) v.AddArg(x) return true } // match: (Trunc32to16 (ZeroExt16to32 x)) // result: x for { if v_0.Op != OpZeroExt16to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to16 (SignExt8to32 x)) // result: (SignExt8to16 x) for { if v_0.Op != OpSignExt8to32 { break } x := v_0.Args[0] v.reset(OpSignExt8to16) v.AddArg(x) return true } // match: (Trunc32to16 (SignExt16to32 x)) // result: x for { if v_0.Op != OpSignExt16to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to16 (And32 (Const32 [y]) x)) // cond: y&0xFFFF == 0xFFFF // result: (Trunc32to16 x) for { if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 { continue } y := auxIntToInt32(v_0_0.AuxInt) x := v_0_1 if !(y&0xFFFF == 0xFFFF) { continue } v.reset(OpTrunc32to16) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc32to8(v *Value) bool { v_0 := v.Args[0] // match: (Trunc32to8 (Const32 [c])) // result: (Const8 [int8(c)]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(c)) return true } // match: (Trunc32to8 (ZeroExt8to32 x)) // result: x for { if v_0.Op != OpZeroExt8to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to8 (SignExt8to32 x)) // result: x for { if v_0.Op != OpSignExt8to32 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc32to8 (And32 (Const32 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc32to8 x) for { if v_0.Op != OpAnd32 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst32 { continue } y := auxIntToInt32(v_0_0.AuxInt) x := v_0_1 if !(y&0xFF == 0xFF) { continue } v.reset(OpTrunc32to8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc64to16(v *Value) bool { v_0 := v.Args[0] // match: (Trunc64to16 (Const64 [c])) // result: (Const16 [int16(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(c)) return true } // match: (Trunc64to16 (ZeroExt8to64 x)) // result: (ZeroExt8to16 x) for { if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpZeroExt8to16) v.AddArg(x) return true } // match: (Trunc64to16 (ZeroExt16to64 x)) // result: x for { if v_0.Op != OpZeroExt16to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to16 (SignExt8to64 x)) // result: (SignExt8to16 x) for { if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpSignExt8to16) v.AddArg(x) return true } // match: (Trunc64to16 (SignExt16to64 x)) // result: x for { if v_0.Op != OpSignExt16to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to16 (And64 (Const64 [y]) x)) // cond: y&0xFFFF == 0xFFFF // result: (Trunc64to16 x) for { if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } y := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(y&0xFFFF == 0xFFFF) { continue } v.reset(OpTrunc64to16) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc64to32(v *Value) bool { v_0 := v.Args[0] // match: (Trunc64to32 (Const64 [c])) // result: (Const32 [int32(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(c)) return true } // match: (Trunc64to32 (ZeroExt8to64 x)) // result: (ZeroExt8to32 x) for { if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.reset(OpZeroExt8to32) v.AddArg(x) return true } // match: (Trunc64to32 (ZeroExt16to64 x)) // result: (ZeroExt16to32 x) for { if v_0.Op != OpZeroExt16to64 { break } x := v_0.Args[0] v.reset(OpZeroExt16to32) v.AddArg(x) return true } // match: (Trunc64to32 (ZeroExt32to64 x)) // result: x for { if v_0.Op != OpZeroExt32to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to32 (SignExt8to64 x)) // result: (SignExt8to32 x) for { if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.reset(OpSignExt8to32) v.AddArg(x) return true } // match: (Trunc64to32 (SignExt16to64 x)) // result: (SignExt16to32 x) for { if v_0.Op != OpSignExt16to64 { break } x := v_0.Args[0] v.reset(OpSignExt16to32) v.AddArg(x) return true } // match: (Trunc64to32 (SignExt32to64 x)) // result: x for { if v_0.Op != OpSignExt32to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to32 (And64 (Const64 [y]) x)) // cond: y&0xFFFFFFFF == 0xFFFFFFFF // result: (Trunc64to32 x) for { if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } y := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(y&0xFFFFFFFF == 0xFFFFFFFF) { continue } v.reset(OpTrunc64to32) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpTrunc64to8(v *Value) bool { v_0 := v.Args[0] // match: (Trunc64to8 (Const64 [c])) // result: (Const8 [int8(c)]) for { if v_0.Op != OpConst64 { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(int8(c)) return true } // match: (Trunc64to8 (ZeroExt8to64 x)) // result: x for { if v_0.Op != OpZeroExt8to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to8 (SignExt8to64 x)) // result: x for { if v_0.Op != OpSignExt8to64 { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (Trunc64to8 (And64 (Const64 [y]) x)) // cond: y&0xFF == 0xFF // result: (Trunc64to8 x) for { if v_0.Op != OpAnd64 { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpConst64 { continue } y := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(y&0xFF == 0xFF) { continue } v.reset(OpTrunc64to8) v.AddArg(x) return true } break } return false } func rewriteValuegeneric_OpXor16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Xor16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpConst16 { continue } d := auxIntToInt16(v_1.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(c ^ d) return true } break } // match: (Xor16 x x) // result: (Const16 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(0) return true } // match: (Xor16 (Const16 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor16 (Com16 x) x) // result: (Const16 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom16 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst16) v.AuxInt = int16ToAuxInt(-1) return true } break } // match: (Xor16 (Const16 [-1]) x) // result: (Com16 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 || auxIntToInt16(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom16) v.AddArg(x) return true } break } // match: (Xor16 x (Xor16 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor16 (Xor16 i:(Const16 ) z) x) // cond: (z.Op != OpConst16 && x.Op != OpConst16) // result: (Xor16 i (Xor16 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor16 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst16 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst16 && x.Op != OpConst16) { continue } v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpXor16, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor16 (Const16 [c]) (Xor16 (Const16 [d]) x)) // result: (Xor16 (Const16 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst16 { continue } t := v_0.Type c := auxIntToInt16(v_0.AuxInt) if v_1.Op != OpXor16 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst16 || v_1_0.Type != t { continue } d := auxIntToInt16(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor16) v0 := b.NewValue0(v.Pos, OpConst16, t) v0.AuxInt = int16ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } // match: (Xor16 (Lsh16x64 x z:(Const64 [c])) (Rsh16Ux64 x (Const64 [d]))) // cond: c < 16 && d == 16-c && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh16x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh16Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 16 && d == 16-c && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Xor16 left:(Lsh16x64 x y) right:(Rsh16Ux64 x (Sub64 (Const64 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Xor16 left:(Lsh16x32 x y) right:(Rsh16Ux32 x (Sub32 (Const32 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Xor16 left:(Lsh16x16 x y) right:(Rsh16Ux16 x (Sub16 (Const16 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Xor16 left:(Lsh16x8 x y) right:(Rsh16Ux8 x (Sub8 (Const8 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh16x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh16Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, y) return true } break } // match: (Xor16 right:(Rsh16Ux64 x y) left:(Lsh16x64 x z:(Sub64 (Const64 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Xor16 right:(Rsh16Ux32 x y) left:(Lsh16x32 x z:(Sub32 (Const32 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Xor16 right:(Rsh16Ux16 x y) left:(Lsh16x16 x z:(Sub16 (Const16 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } // match: (Xor16 right:(Rsh16Ux8 x y) left:(Lsh16x8 x z:(Sub8 (Const8 [16]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) // result: (RotateLeft16 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh16Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh16x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { continue } v.reset(OpRotateLeft16) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpXor32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Xor32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpConst32 { continue } d := auxIntToInt32(v_1.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(c ^ d) return true } break } // match: (Xor32 x x) // result: (Const32 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(0) return true } // match: (Xor32 (Const32 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor32 (Com32 x) x) // result: (Const32 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom32 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst32) v.AuxInt = int32ToAuxInt(-1) return true } break } // match: (Xor32 (Const32 [-1]) x) // result: (Com32 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 || auxIntToInt32(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom32) v.AddArg(x) return true } break } // match: (Xor32 x (Xor32 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor32 (Xor32 i:(Const32 ) z) x) // cond: (z.Op != OpConst32 && x.Op != OpConst32) // result: (Xor32 i (Xor32 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor32 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst32 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst32 && x.Op != OpConst32) { continue } v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpXor32, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor32 (Const32 [c]) (Xor32 (Const32 [d]) x)) // result: (Xor32 (Const32 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst32 { continue } t := v_0.Type c := auxIntToInt32(v_0.AuxInt) if v_1.Op != OpXor32 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst32 || v_1_0.Type != t { continue } d := auxIntToInt32(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor32) v0 := b.NewValue0(v.Pos, OpConst32, t) v0.AuxInt = int32ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } // match: (Xor32 (Lsh32x64 x z:(Const64 [c])) (Rsh32Ux64 x (Const64 [d]))) // cond: c < 32 && d == 32-c && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh32x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh32Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 32 && d == 32-c && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Xor32 left:(Lsh32x64 x y) right:(Rsh32Ux64 x (Sub64 (Const64 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Xor32 left:(Lsh32x32 x y) right:(Rsh32Ux32 x (Sub32 (Const32 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Xor32 left:(Lsh32x16 x y) right:(Rsh32Ux16 x (Sub16 (Const16 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Xor32 left:(Lsh32x8 x y) right:(Rsh32Ux8 x (Sub8 (Const8 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh32x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh32Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, y) return true } break } // match: (Xor32 right:(Rsh32Ux64 x y) left:(Lsh32x64 x z:(Sub64 (Const64 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Xor32 right:(Rsh32Ux32 x y) left:(Lsh32x32 x z:(Sub32 (Const32 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Xor32 right:(Rsh32Ux16 x y) left:(Lsh32x16 x z:(Sub16 (Const16 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } // match: (Xor32 right:(Rsh32Ux8 x y) left:(Lsh32x8 x z:(Sub8 (Const8 [32]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) // result: (RotateLeft32 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh32Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh32x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { continue } v.reset(OpRotateLeft32) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpXor64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Xor64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(c ^ d) return true } break } // match: (Xor64 x x) // result: (Const64 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(0) return true } // match: (Xor64 (Const64 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor64 (Com64 x) x) // result: (Const64 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom64 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst64) v.AuxInt = int64ToAuxInt(-1) return true } break } // match: (Xor64 (Const64 [-1]) x) // result: (Com64 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 || auxIntToInt64(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom64) v.AddArg(x) return true } break } // match: (Xor64 x (Xor64 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor64 (Xor64 i:(Const64 ) z) x) // cond: (z.Op != OpConst64 && x.Op != OpConst64) // result: (Xor64 i (Xor64 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor64 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst64 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst64 && x.Op != OpConst64) { continue } v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpXor64, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor64 (Const64 [c]) (Xor64 (Const64 [d]) x)) // result: (Xor64 (Const64 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst64 { continue } t := v_0.Type c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpXor64 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst64 || v_1_0.Type != t { continue } d := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor64) v0 := b.NewValue0(v.Pos, OpConst64, t) v0.AuxInt = int64ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } // match: (Xor64 (Lsh64x64 x z:(Const64 [c])) (Rsh64Ux64 x (Const64 [d]))) // cond: c < 64 && d == 64-c && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh64x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh64Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 64 && d == 64-c && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Xor64 left:(Lsh64x64 x y) right:(Rsh64Ux64 x (Sub64 (Const64 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Xor64 left:(Lsh64x32 x y) right:(Rsh64Ux32 x (Sub32 (Const32 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Xor64 left:(Lsh64x16 x y) right:(Rsh64Ux16 x (Sub16 (Const16 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Xor64 left:(Lsh64x8 x y) right:(Rsh64Ux8 x (Sub8 (Const8 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh64x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh64Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, y) return true } break } // match: (Xor64 right:(Rsh64Ux64 x y) left:(Lsh64x64 x z:(Sub64 (Const64 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Xor64 right:(Rsh64Ux32 x y) left:(Lsh64x32 x z:(Sub32 (Const32 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Xor64 right:(Rsh64Ux16 x y) left:(Lsh64x16 x z:(Sub16 (Const16 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } // match: (Xor64 right:(Rsh64Ux8 x y) left:(Lsh64x8 x z:(Sub8 (Const8 [64]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) // result: (RotateLeft64 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh64Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh64x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { continue } v.reset(OpRotateLeft64) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpXor8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (Xor8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c^d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpConst8 { continue } d := auxIntToInt8(v_1.AuxInt) v.reset(OpConst8) v.AuxInt = int8ToAuxInt(c ^ d) return true } break } // match: (Xor8 x x) // result: (Const8 [0]) for { x := v_0 if x != v_1 { break } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(0) return true } // match: (Xor8 (Const8 [0]) x) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != 0 { continue } x := v_1 v.copyOf(x) return true } break } // match: (Xor8 (Com8 x) x) // result: (Const8 [-1]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpCom8 { continue } x := v_0.Args[0] if x != v_1 { continue } v.reset(OpConst8) v.AuxInt = int8ToAuxInt(-1) return true } break } // match: (Xor8 (Const8 [-1]) x) // result: (Com8 x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 || auxIntToInt8(v_0.AuxInt) != -1 { continue } x := v_1 v.reset(OpCom8) v.AddArg(x) return true } break } // match: (Xor8 x (Xor8 x y)) // result: y for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpXor8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.copyOf(y) return true } } break } // match: (Xor8 (Xor8 i:(Const8 ) z) x) // cond: (z.Op != OpConst8 && x.Op != OpConst8) // result: (Xor8 i (Xor8 z x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpXor8 { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_0_0, v_0_1 = _i1+1, v_0_1, v_0_0 { i := v_0_0 if i.Op != OpConst8 { continue } t := i.Type z := v_0_1 x := v_1 if !(z.Op != OpConst8 && x.Op != OpConst8) { continue } v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpXor8, t) v0.AddArg2(z, x) v.AddArg2(i, v0) return true } } break } // match: (Xor8 (Const8 [c]) (Xor8 (Const8 [d]) x)) // result: (Xor8 (Const8 [c^d]) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpConst8 { continue } t := v_0.Type c := auxIntToInt8(v_0.AuxInt) if v_1.Op != OpXor8 { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpConst8 || v_1_0.Type != t { continue } d := auxIntToInt8(v_1_0.AuxInt) x := v_1_1 v.reset(OpXor8) v0 := b.NewValue0(v.Pos, OpConst8, t) v0.AuxInt = int8ToAuxInt(c ^ d) v.AddArg2(v0, x) return true } } break } // match: (Xor8 (Lsh8x64 x z:(Const64 [c])) (Rsh8Ux64 x (Const64 [d]))) // cond: c < 8 && d == 8-c && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpLsh8x64 { continue } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpConst64 { continue } c := auxIntToInt64(z.AuxInt) if v_1.Op != OpRsh8Ux64 { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpConst64 { continue } d := auxIntToInt64(v_1_1.AuxInt) if !(c < 8 && d == 8-c && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Xor8 left:(Lsh8x64 x y) right:(Rsh8Ux64 x (Sub64 (Const64 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x64 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux64 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub64 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Xor8 left:(Lsh8x32 x y) right:(Rsh8Ux32 x (Sub32 (Const32 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x32 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux32 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub32 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Xor8 left:(Lsh8x16 x y) right:(Rsh8Ux16 x (Sub16 (Const16 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x16 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux16 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub16 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Xor8 left:(Lsh8x8 x y) right:(Rsh8Ux8 x (Sub8 (Const8 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { left := v_0 if left.Op != OpLsh8x8 { continue } y := left.Args[1] x := left.Args[0] right := v_1 if right.Op != OpRsh8Ux8 { continue } _ = right.Args[1] if x != right.Args[0] { continue } right_1 := right.Args[1] if right_1.Op != OpSub8 { continue } _ = right_1.Args[1] right_1_0 := right_1.Args[0] if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, y) return true } break } // match: (Xor8 right:(Rsh8Ux64 x y) left:(Lsh8x64 x z:(Sub64 (Const64 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux64 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x64 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub64 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Xor8 right:(Rsh8Ux32 x y) left:(Lsh8x32 x z:(Sub32 (Const32 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux32 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x32 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub32 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Xor8 right:(Rsh8Ux16 x y) left:(Lsh8x16 x z:(Sub16 (Const16 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux16 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x16 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub16 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } // match: (Xor8 right:(Rsh8Ux8 x y) left:(Lsh8x8 x z:(Sub8 (Const8 [8]) y))) // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) // result: (RotateLeft8 x z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { right := v_0 if right.Op != OpRsh8Ux8 { continue } y := right.Args[1] x := right.Args[0] left := v_1 if left.Op != OpLsh8x8 { continue } _ = left.Args[1] if x != left.Args[0] { continue } z := left.Args[1] if z.Op != OpSub8 { continue } _ = z.Args[1] z_0 := z.Args[0] if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { continue } v.reset(OpRotateLeft8) v.AddArg2(x, z) return true } break } return false } func rewriteValuegeneric_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Zero (SelectN [0] call:(StaticLECall _ _)) mem:(SelectN [1] call)) // cond: isSameCall(call.Aux, "runtime.newobject") // result: mem for { if v_0.Op != OpSelectN || auxIntToInt64(v_0.AuxInt) != 0 { break } call := v_0.Args[0] if call.Op != OpStaticLECall || len(call.Args) != 2 { break } mem := v_1 if mem.Op != OpSelectN || auxIntToInt64(mem.AuxInt) != 1 || call != mem.Args[0] || !(isSameCall(call.Aux, "runtime.newobject")) { break } v.copyOf(mem) return true } // match: (Zero {t1} [n] p1 store:(Store {t2} (OffPtr [o2] p2) _ mem)) // cond: isSamePtr(p1, p2) && store.Uses == 1 && n >= o2 + t2.Size() && clobber(store) // result: (Zero {t1} [n] p1 mem) for { n := auxIntToInt64(v.AuxInt) t1 := auxToType(v.Aux) p1 := v_0 store := v_1 if store.Op != OpStore { break } t2 := auxToType(store.Aux) mem := store.Args[2] store_0 := store.Args[0] if store_0.Op != OpOffPtr { break } o2 := auxIntToInt64(store_0.AuxInt) p2 := store_0.Args[0] if !(isSamePtr(p1, p2) && store.Uses == 1 && n >= o2+t2.Size() && clobber(store)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t1) v.AddArg2(p1, mem) return true } // match: (Zero {t} [n] dst1 move:(Move {t} [n] dst2 _ mem)) // cond: move.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move) // result: (Zero {t} [n] dst1 mem) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 move := v_1 if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v.AddArg2(dst1, mem) return true } // match: (Zero {t} [n] dst1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem))) // cond: move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move, vardef) // result: (Zero {t} [n] dst1 (VarDef {x} mem)) for { n := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 vardef := v_1 if vardef.Op != OpVarDef { break } x := auxToSym(vardef.Aux) move := vardef.Args[0] if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t { break } mem := move.Args[2] dst2 := move.Args[0] if !(move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && clobber(move, vardef)) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(n) v.Aux = typeToAux(t) v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem) v0.Aux = symToAux(x) v0.AddArg(mem) v.AddArg2(dst1, v0) return true } // match: (Zero {t} [s] dst1 zero:(Zero {t} [s] dst2 _)) // cond: isSamePtr(dst1, dst2) // result: zero for { s := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 zero := v_1 if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != s || auxToType(zero.Aux) != t { break } dst2 := zero.Args[0] if !(isSamePtr(dst1, dst2)) { break } v.copyOf(zero) return true } // match: (Zero {t} [s] dst1 vardef:(VarDef (Zero {t} [s] dst2 _))) // cond: isSamePtr(dst1, dst2) // result: vardef for { s := auxIntToInt64(v.AuxInt) t := auxToType(v.Aux) dst1 := v_0 vardef := v_1 if vardef.Op != OpVarDef { break } vardef_0 := vardef.Args[0] if vardef_0.Op != OpZero || auxIntToInt64(vardef_0.AuxInt) != s || auxToType(vardef_0.Aux) != t { break } dst2 := vardef_0.Args[0] if !(isSamePtr(dst1, dst2)) { break } v.copyOf(vardef) return true } return false } func rewriteValuegeneric_OpZeroExt16to32(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt16to32 (Const16 [c])) // result: (Const32 [int32(uint16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint16(c))) return true } // match: (ZeroExt16to32 (Trunc32to16 x:(Rsh32Ux64 _ (Const64 [s])))) // cond: s >= 16 // result: x for { if v_0.Op != OpTrunc32to16 { break } x := v_0.Args[0] if x.Op != OpRsh32Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 16) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt16to64(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt16to64 (Const16 [c])) // result: (Const64 [int64(uint16(c))]) for { if v_0.Op != OpConst16 { break } c := auxIntToInt16(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint16(c))) return true } // match: (ZeroExt16to64 (Trunc64to16 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 48 // result: x for { if v_0.Op != OpTrunc64to16 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 48) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt32to64(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt32to64 (Const32 [c])) // result: (Const64 [int64(uint32(c))]) for { if v_0.Op != OpConst32 { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint32(c))) return true } // match: (ZeroExt32to64 (Trunc64to32 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 32 // result: x for { if v_0.Op != OpTrunc64to32 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 32) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to16(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt8to16 (Const8 [c])) // result: (Const16 [int16( uint8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst16) v.AuxInt = int16ToAuxInt(int16(uint8(c))) return true } // match: (ZeroExt8to16 (Trunc16to8 x:(Rsh16Ux64 _ (Const64 [s])))) // cond: s >= 8 // result: x for { if v_0.Op != OpTrunc16to8 { break } x := v_0.Args[0] if x.Op != OpRsh16Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 8) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to32(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt8to32 (Const8 [c])) // result: (Const32 [int32( uint8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst32) v.AuxInt = int32ToAuxInt(int32(uint8(c))) return true } // match: (ZeroExt8to32 (Trunc32to8 x:(Rsh32Ux64 _ (Const64 [s])))) // cond: s >= 24 // result: x for { if v_0.Op != OpTrunc32to8 { break } x := v_0.Args[0] if x.Op != OpRsh32Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 24) { break } v.copyOf(x) return true } return false } func rewriteValuegeneric_OpZeroExt8to64(v *Value) bool { v_0 := v.Args[0] // match: (ZeroExt8to64 (Const8 [c])) // result: (Const64 [int64( uint8(c))]) for { if v_0.Op != OpConst8 { break } c := auxIntToInt8(v_0.AuxInt) v.reset(OpConst64) v.AuxInt = int64ToAuxInt(int64(uint8(c))) return true } // match: (ZeroExt8to64 (Trunc64to8 x:(Rsh64Ux64 _ (Const64 [s])))) // cond: s >= 56 // result: x for { if v_0.Op != OpTrunc64to8 { break } x := v_0.Args[0] if x.Op != OpRsh64Ux64 { break } _ = x.Args[1] x_1 := x.Args[1] if x_1.Op != OpConst64 { break } s := auxIntToInt64(x_1.AuxInt) if !(s >= 56) { break } v.copyOf(x) return true } return false } func rewriteBlockgeneric(b *Block) bool { switch b.Kind { case BlockIf: // match: (If (Not cond) yes no) // result: (If cond no yes) for b.Controls[0].Op == OpNot { v_0 := b.Controls[0] cond := v_0.Args[0] b.resetWithControl(BlockIf, cond) b.swapSuccessors() return true } // match: (If (ConstBool [c]) yes no) // cond: c // result: (First yes no) for b.Controls[0].Op == OpConstBool { v_0 := b.Controls[0] c := auxIntToBool(v_0.AuxInt) if !(c) { break } b.Reset(BlockFirst) return true } // match: (If (ConstBool [c]) yes no) // cond: !c // result: (First no yes) for b.Controls[0].Op == OpConstBool { v_0 := b.Controls[0] c := auxIntToBool(v_0.AuxInt) if !(!c) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- diff -- @@ -453,6 +453,7 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Add16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c+d]) for { @@ -724,12 +725,321 @@ } break } + // match: (Add16 (Lsh16x64 x z:(Const64 [c])) (Rsh16Ux64 x (Const64 [d]))) + // cond: c < 16 && d == 16-c && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh16x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh16Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 16 && d == 16-c && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add16 left:(Lsh16x64 x y) right:(Rsh16Ux64 x (Sub64 (Const64 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add16 left:(Lsh16x32 x y) right:(Rsh16Ux32 x (Sub32 (Const32 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add16 left:(Lsh16x16 x y) right:(Rsh16Ux16 x (Sub16 (Const16 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add16 left:(Lsh16x8 x y) right:(Rsh16Ux8 x (Sub8 (Const8 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add16 right:(Rsh16Ux64 x y) left:(Lsh16x64 x z:(Sub64 (Const64 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add16 right:(Rsh16Ux32 x y) left:(Lsh16x32 x z:(Sub32 (Const32 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add16 right:(Rsh16Ux16 x y) left:(Lsh16x16 x z:(Sub16 (Const16 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add16 right:(Rsh16Ux8 x y) left:(Lsh16x8 x z:(Sub8 (Const8 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpAdd32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Add32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c+d]) for { @@ -1001,6 +1311,314 @@ } break } + // match: (Add32 (Lsh32x64 x z:(Const64 [c])) (Rsh32Ux64 x (Const64 [d]))) + // cond: c < 32 && d == 32-c && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh32x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh32Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 32 && d == 32-c && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add32 left:(Lsh32x64 x y) right:(Rsh32Ux64 x (Sub64 (Const64 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add32 left:(Lsh32x32 x y) right:(Rsh32Ux32 x (Sub32 (Const32 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add32 left:(Lsh32x16 x y) right:(Rsh32Ux16 x (Sub16 (Const16 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add32 left:(Lsh32x8 x y) right:(Rsh32Ux8 x (Sub8 (Const8 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add32 right:(Rsh32Ux64 x y) left:(Lsh32x64 x z:(Sub64 (Const64 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add32 right:(Rsh32Ux32 x y) left:(Lsh32x32 x z:(Sub32 (Const32 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add32 right:(Rsh32Ux16 x y) left:(Lsh32x16 x z:(Sub16 (Const16 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add32 right:(Rsh32Ux8 x y) left:(Lsh32x8 x z:(Sub8 (Const8 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpAdd32F(v *Value) bool { @@ -1034,6 +1652,7 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Add64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c+d]) for { @@ -1305,6 +1924,314 @@ } break } + // match: (Add64 (Lsh64x64 x z:(Const64 [c])) (Rsh64Ux64 x (Const64 [d]))) + // cond: c < 64 && d == 64-c && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh64x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh64Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 64 && d == 64-c && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add64 left:(Lsh64x64 x y) right:(Rsh64Ux64 x (Sub64 (Const64 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add64 left:(Lsh64x32 x y) right:(Rsh64Ux32 x (Sub32 (Const32 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add64 left:(Lsh64x16 x y) right:(Rsh64Ux16 x (Sub16 (Const16 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add64 left:(Lsh64x8 x y) right:(Rsh64Ux8 x (Sub8 (Const8 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add64 right:(Rsh64Ux64 x y) left:(Lsh64x64 x z:(Sub64 (Const64 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add64 right:(Rsh64Ux32 x y) left:(Lsh64x32 x z:(Sub32 (Const32 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add64 right:(Rsh64Ux16 x y) left:(Lsh64x16 x z:(Sub16 (Const16 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add64 right:(Rsh64Ux8 x y) left:(Lsh64x8 x z:(Sub8 (Const8 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpAdd64F(v *Value) bool { @@ -1338,6 +2265,7 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Add8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c+d]) for { @@ -1609,6 +2537,314 @@ } break } + // match: (Add8 (Lsh8x64 x z:(Const64 [c])) (Rsh8Ux64 x (Const64 [d]))) + // cond: c < 8 && d == 8-c && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh8x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh8Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 8 && d == 8-c && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add8 left:(Lsh8x64 x y) right:(Rsh8Ux64 x (Sub64 (Const64 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add8 left:(Lsh8x32 x y) right:(Rsh8Ux32 x (Sub32 (Const32 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add8 left:(Lsh8x16 x y) right:(Rsh8Ux16 x (Sub16 (Const16 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add8 left:(Lsh8x8 x y) right:(Rsh8Ux8 x (Sub8 (Const8 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add8 right:(Rsh8Ux64 x y) left:(Lsh8x64 x z:(Sub64 (Const64 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add8 right:(Rsh8Ux32 x y) left:(Lsh8x32 x z:(Sub32 (Const32 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add8 right:(Rsh8Ux16 x y) left:(Lsh8x16 x z:(Sub16 (Const16 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add8 right:(Rsh8Ux8 x y) left:(Lsh8x8 x z:(Sub8 (Const8 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpAddPtr(v *Value) bool { @@ -17106,6 +18342,7 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Or16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c|d]) for { @@ -17295,12 +18532,321 @@ } break } + // match: (Or16 (Lsh16x64 x z:(Const64 [c])) (Rsh16Ux64 x (Const64 [d]))) + // cond: c < 16 && d == 16-c && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh16x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh16Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 16 && d == 16-c && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or16 left:(Lsh16x64 x y) right:(Rsh16Ux64 x (Sub64 (Const64 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or16 left:(Lsh16x32 x y) right:(Rsh16Ux32 x (Sub32 (Const32 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or16 left:(Lsh16x16 x y) right:(Rsh16Ux16 x (Sub16 (Const16 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or16 left:(Lsh16x8 x y) right:(Rsh16Ux8 x (Sub8 (Const8 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or16 right:(Rsh16Ux64 x y) left:(Lsh16x64 x z:(Sub64 (Const64 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or16 right:(Rsh16Ux32 x y) left:(Lsh16x32 x z:(Sub32 (Const32 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or16 right:(Rsh16Ux16 x y) left:(Lsh16x16 x z:(Sub16 (Const16 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or16 right:(Rsh16Ux8 x y) left:(Lsh16x8 x z:(Sub8 (Const8 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpOr32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Or32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c|d]) for { @@ -17490,12 +19036,321 @@ } break } + // match: (Or32 (Lsh32x64 x z:(Const64 [c])) (Rsh32Ux64 x (Const64 [d]))) + // cond: c < 32 && d == 32-c && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh32x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh32Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 32 && d == 32-c && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or32 left:(Lsh32x64 x y) right:(Rsh32Ux64 x (Sub64 (Const64 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or32 left:(Lsh32x32 x y) right:(Rsh32Ux32 x (Sub32 (Const32 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or32 left:(Lsh32x16 x y) right:(Rsh32Ux16 x (Sub16 (Const16 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or32 left:(Lsh32x8 x y) right:(Rsh32Ux8 x (Sub8 (Const8 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or32 right:(Rsh32Ux64 x y) left:(Lsh32x64 x z:(Sub64 (Const64 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or32 right:(Rsh32Ux32 x y) left:(Lsh32x32 x z:(Sub32 (Const32 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or32 right:(Rsh32Ux16 x y) left:(Lsh32x16 x z:(Sub16 (Const16 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or32 right:(Rsh32Ux8 x y) left:(Lsh32x8 x z:(Sub8 (Const8 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpOr64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Or64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c|d]) for { @@ -17685,12 +19540,321 @@ } break } + // match: (Or64 (Lsh64x64 x z:(Const64 [c])) (Rsh64Ux64 x (Const64 [d]))) + // cond: c < 64 && d == 64-c && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh64x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh64Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 64 && d == 64-c && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or64 left:(Lsh64x64 x y) right:(Rsh64Ux64 x (Sub64 (Const64 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or64 left:(Lsh64x32 x y) right:(Rsh64Ux32 x (Sub32 (Const32 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or64 left:(Lsh64x16 x y) right:(Rsh64Ux16 x (Sub16 (Const16 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or64 left:(Lsh64x8 x y) right:(Rsh64Ux8 x (Sub8 (Const8 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or64 right:(Rsh64Ux64 x y) left:(Lsh64x64 x z:(Sub64 (Const64 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or64 right:(Rsh64Ux32 x y) left:(Lsh64x32 x z:(Sub32 (Const32 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or64 right:(Rsh64Ux16 x y) left:(Lsh64x16 x z:(Sub16 (Const16 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or64 right:(Rsh64Ux8 x y) left:(Lsh64x8 x z:(Sub8 (Const8 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpOr8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Or8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c|d]) for { @@ -17880,6 +20044,314 @@ } break } + // match: (Or8 (Lsh8x64 x z:(Const64 [c])) (Rsh8Ux64 x (Const64 [d]))) + // cond: c < 8 && d == 8-c && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh8x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh8Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 8 && d == 8-c && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or8 left:(Lsh8x64 x y) right:(Rsh8Ux64 x (Sub64 (Const64 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or8 left:(Lsh8x32 x y) right:(Rsh8Ux32 x (Sub32 (Const32 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or8 left:(Lsh8x16 x y) right:(Rsh8Ux16 x (Sub16 (Const16 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or8 left:(Lsh8x8 x y) right:(Rsh8Ux8 x (Sub8 (Const8 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or8 right:(Rsh8Ux64 x y) left:(Lsh8x64 x z:(Sub64 (Const64 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or8 right:(Rsh8Ux32 x y) left:(Lsh8x32 x z:(Sub32 (Const32 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or8 right:(Rsh8Ux16 x y) left:(Lsh8x16 x z:(Sub16 (Const16 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or8 right:(Rsh8Ux8 x y) left:(Lsh8x8 x z:(Sub8 (Const8 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpOrB(v *Value) bool { @@ -19330,6 +21802,8 @@ func rewriteValuegeneric_OpRotateLeft16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + b := v.Block + config := b.Func.Config // match: (RotateLeft16 x (Const16 [c])) // cond: c%16 == 0 // result: x @@ -19345,11 +21819,460 @@ v.copyOf(x) return true } + // match: (RotateLeft16 x (And64 y (Const64 [c]))) + // cond: c&15 == 15 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAnd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (And32 y (Const32 [c]))) + // cond: c&15 == 15 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAnd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (And16 y (Const16 [c]))) + // cond: c&15 == 15 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAnd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (And8 y (Const8 [c]))) + // cond: c&15 == 15 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAnd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (Neg64 (And64 y (Const64 [c])))) + // cond: c&15 == 15 + // result: (RotateLeft16 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpNeg64 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_0_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft16 x (Neg32 (And32 y (Const32 [c])))) + // cond: c&15 == 15 + // result: (RotateLeft16 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpNeg32 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_0_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft16 x (Neg16 (And16 y (Const16 [c])))) + // cond: c&15 == 15 + // result: (RotateLeft16 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpNeg16 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd16 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_0_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft16 x (Neg8 (And8 y (Const8 [c])))) + // cond: c&15 == 15 + // result: (RotateLeft16 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpNeg8 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd8 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_0_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft16 x (Add64 y (Const64 [c]))) + // cond: c&15 == 0 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAdd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&15 == 0) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (Add32 y (Const32 [c]))) + // cond: c&15 == 0 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAdd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&15 == 0) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (Add16 y (Const16 [c]))) + // cond: c&15 == 0 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAdd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&15 == 0) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (Add8 y (Const8 [c]))) + // cond: c&15 == 0 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAdd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&15 == 0) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (Sub64 (Const64 [c]) y)) + // cond: c&15 == 0 + // result: (RotateLeft16 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpSub64 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1_0.AuxInt) + if !(c&15 == 0) { + break + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft16 x (Sub32 (Const32 [c]) y)) + // cond: c&15 == 0 + // result: (RotateLeft16 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpSub32 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + if !(c&15 == 0) { + break + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft16 x (Sub16 (Const16 [c]) y)) + // cond: c&15 == 0 + // result: (RotateLeft16 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpSub16 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1_0.AuxInt) + if !(c&15 == 0) { + break + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft16 x (Sub8 (Const8 [c]) y)) + // cond: c&15 == 0 + // result: (RotateLeft16 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpSub8 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1_0.AuxInt) + if !(c&15 == 0) { + break + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft16 x (Const64 [c])) + // cond: config.PtrSize == 4 + // result: (RotateLeft16 x (Const32 [int32(c)])) + for { + x := v_0 + if v_1.Op != OpConst64 { + break + } + t := v_1.Type + c := auxIntToInt64(v_1.AuxInt) + if !(config.PtrSize == 4) { + break + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg2(x, v0) + return true + } return false } func rewriteValuegeneric_OpRotateLeft32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + b := v.Block + config := b.Func.Config // match: (RotateLeft32 x (Const32 [c])) // cond: c%32 == 0 // result: x @@ -19365,11 +22288,460 @@ v.copyOf(x) return true } + // match: (RotateLeft32 x (And64 y (Const64 [c]))) + // cond: c&31 == 31 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAnd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (And32 y (Const32 [c]))) + // cond: c&31 == 31 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAnd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (And16 y (Const16 [c]))) + // cond: c&31 == 31 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAnd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (And8 y (Const8 [c]))) + // cond: c&31 == 31 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAnd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (Neg64 (And64 y (Const64 [c])))) + // cond: c&31 == 31 + // result: (RotateLeft32 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpNeg64 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_0_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft32 x (Neg32 (And32 y (Const32 [c])))) + // cond: c&31 == 31 + // result: (RotateLeft32 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpNeg32 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_0_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft32 x (Neg16 (And16 y (Const16 [c])))) + // cond: c&31 == 31 + // result: (RotateLeft32 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpNeg16 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd16 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_0_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft32 x (Neg8 (And8 y (Const8 [c])))) + // cond: c&31 == 31 + // result: (RotateLeft32 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpNeg8 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd8 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_0_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft32 x (Add64 y (Const64 [c]))) + // cond: c&31 == 0 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAdd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&31 == 0) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (Add32 y (Const32 [c]))) + // cond: c&31 == 0 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAdd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&31 == 0) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (Add16 y (Const16 [c]))) + // cond: c&31 == 0 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAdd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&31 == 0) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (Add8 y (Const8 [c]))) + // cond: c&31 == 0 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAdd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&31 == 0) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (Sub64 (Const64 [c]) y)) + // cond: c&31 == 0 + // result: (RotateLeft32 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpSub64 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1_0.AuxInt) + if !(c&31 == 0) { + break + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft32 x (Sub32 (Const32 [c]) y)) + // cond: c&31 == 0 + // result: (RotateLeft32 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpSub32 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + if !(c&31 == 0) { + break + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft32 x (Sub16 (Const16 [c]) y)) + // cond: c&31 == 0 + // result: (RotateLeft32 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpSub16 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1_0.AuxInt) + if !(c&31 == 0) { + break + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft32 x (Sub8 (Const8 [c]) y)) + // cond: c&31 == 0 + // result: (RotateLeft32 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpSub8 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1_0.AuxInt) + if !(c&31 == 0) { + break + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft32 x (Const64 [c])) + // cond: config.PtrSize == 4 + // result: (RotateLeft32 x (Const32 [int32(c)])) + for { + x := v_0 + if v_1.Op != OpConst64 { + break + } + t := v_1.Type + c := auxIntToInt64(v_1.AuxInt) + if !(config.PtrSize == 4) { + break + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg2(x, v0) + return true + } return false } func rewriteValuegeneric_OpRotateLeft64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + b := v.Block + config := b.Func.Config // match: (RotateLeft64 x (Const64 [c])) // cond: c%64 == 0 // result: x @@ -19385,11 +22757,460 @@ v.copyOf(x) return true } + // match: (RotateLeft64 x (And64 y (Const64 [c]))) + // cond: c&63 == 63 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAnd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (And32 y (Const32 [c]))) + // cond: c&63 == 63 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAnd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (And16 y (Const16 [c]))) + // cond: c&63 == 63 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAnd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (And8 y (Const8 [c]))) + // cond: c&63 == 63 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAnd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (Neg64 (And64 y (Const64 [c])))) + // cond: c&63 == 63 + // result: (RotateLeft64 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpNeg64 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_0_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft64 x (Neg32 (And32 y (Const32 [c])))) + // cond: c&63 == 63 + // result: (RotateLeft64 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpNeg32 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_0_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft64 x (Neg16 (And16 y (Const16 [c])))) + // cond: c&63 == 63 + // result: (RotateLeft64 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpNeg16 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd16 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_0_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft64 x (Neg8 (And8 y (Const8 [c])))) + // cond: c&63 == 63 + // result: (RotateLeft64 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpNeg8 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd8 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_0_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft64 x (Add64 y (Const64 [c]))) + // cond: c&63 == 0 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAdd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&63 == 0) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (Add32 y (Const32 [c]))) + // cond: c&63 == 0 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAdd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&63 == 0) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (Add16 y (Const16 [c]))) + // cond: c&63 == 0 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAdd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&63 == 0) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (Add8 y (Const8 [c]))) + // cond: c&63 == 0 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAdd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&63 == 0) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (Sub64 (Const64 [c]) y)) + // cond: c&63 == 0 + // result: (RotateLeft64 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpSub64 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1_0.AuxInt) + if !(c&63 == 0) { + break + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft64 x (Sub32 (Const32 [c]) y)) + // cond: c&63 == 0 + // result: (RotateLeft64 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpSub32 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + if !(c&63 == 0) { + break + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft64 x (Sub16 (Const16 [c]) y)) + // cond: c&63 == 0 + // result: (RotateLeft64 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpSub16 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1_0.AuxInt) + if !(c&63 == 0) { + break + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft64 x (Sub8 (Const8 [c]) y)) + // cond: c&63 == 0 + // result: (RotateLeft64 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpSub8 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1_0.AuxInt) + if !(c&63 == 0) { + break + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft64 x (Const64 [c])) + // cond: config.PtrSize == 4 + // result: (RotateLeft64 x (Const32 [int32(c)])) + for { + x := v_0 + if v_1.Op != OpConst64 { + break + } + t := v_1.Type + c := auxIntToInt64(v_1.AuxInt) + if !(config.PtrSize == 4) { + break + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg2(x, v0) + return true + } return false } func rewriteValuegeneric_OpRotateLeft8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + b := v.Block + config := b.Func.Config // match: (RotateLeft8 x (Const8 [c])) // cond: c%8 == 0 // result: x @@ -19405,6 +23226,453 @@ v.copyOf(x) return true } + // match: (RotateLeft8 x (And64 y (Const64 [c]))) + // cond: c&7 == 7 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAnd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (And32 y (Const32 [c]))) + // cond: c&7 == 7 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAnd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (And16 y (Const16 [c]))) + // cond: c&7 == 7 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAnd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (And8 y (Const8 [c]))) + // cond: c&7 == 7 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAnd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (Neg64 (And64 y (Const64 [c])))) + // cond: c&7 == 7 + // result: (RotateLeft8 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpNeg64 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_0_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft8 x (Neg32 (And32 y (Const32 [c])))) + // cond: c&7 == 7 + // result: (RotateLeft8 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpNeg32 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_0_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft8 x (Neg16 (And16 y (Const16 [c])))) + // cond: c&7 == 7 + // result: (RotateLeft8 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpNeg16 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd16 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_0_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft8 x (Neg8 (And8 y (Const8 [c])))) + // cond: c&7 == 7 + // result: (RotateLeft8 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpNeg8 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd8 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_0_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft8 x (Add64 y (Const64 [c]))) + // cond: c&7 == 0 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAdd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&7 == 0) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (Add32 y (Const32 [c]))) + // cond: c&7 == 0 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAdd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&7 == 0) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (Add16 y (Const16 [c]))) + // cond: c&7 == 0 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAdd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&7 == 0) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (Add8 y (Const8 [c]))) + // cond: c&7 == 0 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAdd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&7 == 0) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (Sub64 (Const64 [c]) y)) + // cond: c&7 == 0 + // result: (RotateLeft8 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpSub64 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1_0.AuxInt) + if !(c&7 == 0) { + break + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft8 x (Sub32 (Const32 [c]) y)) + // cond: c&7 == 0 + // result: (RotateLeft8 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpSub32 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + if !(c&7 == 0) { + break + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft8 x (Sub16 (Const16 [c]) y)) + // cond: c&7 == 0 + // result: (RotateLeft8 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpSub16 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1_0.AuxInt) + if !(c&7 == 0) { + break + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft8 x (Sub8 (Const8 [c]) y)) + // cond: c&7 == 0 + // result: (RotateLeft8 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpSub8 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1_0.AuxInt) + if !(c&7 == 0) { + break + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft8 x (Const64 [c])) + // cond: config.PtrSize == 4 + // result: (RotateLeft8 x (Const32 [int32(c)])) + for { + x := v_0 + if v_1.Op != OpConst64 { + break + } + t := v_1.Type + c := auxIntToInt64(v_1.AuxInt) + if !(config.PtrSize == 4) { + break + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg2(x, v0) + return true + } return false } func rewriteValuegeneric_OpRound32F(v *Value) bool { @@ -25200,6 +29468,7 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Xor16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c^d]) for { @@ -25356,12 +29625,321 @@ } break } + // match: (Xor16 (Lsh16x64 x z:(Const64 [c])) (Rsh16Ux64 x (Const64 [d]))) + // cond: c < 16 && d == 16-c && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh16x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh16Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 16 && d == 16-c && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor16 left:(Lsh16x64 x y) right:(Rsh16Ux64 x (Sub64 (Const64 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor16 left:(Lsh16x32 x y) right:(Rsh16Ux32 x (Sub32 (Const32 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor16 left:(Lsh16x16 x y) right:(Rsh16Ux16 x (Sub16 (Const16 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor16 left:(Lsh16x8 x y) right:(Rsh16Ux8 x (Sub8 (Const8 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor16 right:(Rsh16Ux64 x y) left:(Lsh16x64 x z:(Sub64 (Const64 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor16 right:(Rsh16Ux32 x y) left:(Lsh16x32 x z:(Sub32 (Const32 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor16 right:(Rsh16Ux16 x y) left:(Lsh16x16 x z:(Sub16 (Const16 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor16 right:(Rsh16Ux8 x y) left:(Lsh16x8 x z:(Sub8 (Const8 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpXor32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Xor32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c^d]) for { @@ -25518,12 +30096,321 @@ } break } + // match: (Xor32 (Lsh32x64 x z:(Const64 [c])) (Rsh32Ux64 x (Const64 [d]))) + // cond: c < 32 && d == 32-c && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh32x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh32Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 32 && d == 32-c && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor32 left:(Lsh32x64 x y) right:(Rsh32Ux64 x (Sub64 (Const64 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor32 left:(Lsh32x32 x y) right:(Rsh32Ux32 x (Sub32 (Const32 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor32 left:(Lsh32x16 x y) right:(Rsh32Ux16 x (Sub16 (Const16 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor32 left:(Lsh32x8 x y) right:(Rsh32Ux8 x (Sub8 (Const8 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor32 right:(Rsh32Ux64 x y) left:(Lsh32x64 x z:(Sub64 (Const64 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor32 right:(Rsh32Ux32 x y) left:(Lsh32x32 x z:(Sub32 (Const32 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor32 right:(Rsh32Ux16 x y) left:(Lsh32x16 x z:(Sub16 (Const16 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor32 right:(Rsh32Ux8 x y) left:(Lsh32x8 x z:(Sub8 (Const8 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpXor64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Xor64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c^d]) for { @@ -25680,12 +30567,321 @@ } break } + // match: (Xor64 (Lsh64x64 x z:(Const64 [c])) (Rsh64Ux64 x (Const64 [d]))) + // cond: c < 64 && d == 64-c && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh64x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh64Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 64 && d == 64-c && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor64 left:(Lsh64x64 x y) right:(Rsh64Ux64 x (Sub64 (Const64 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor64 left:(Lsh64x32 x y) right:(Rsh64Ux32 x (Sub32 (Const32 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor64 left:(Lsh64x16 x y) right:(Rsh64Ux16 x (Sub16 (Const16 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor64 left:(Lsh64x8 x y) right:(Rsh64Ux8 x (Sub8 (Const8 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor64 right:(Rsh64Ux64 x y) left:(Lsh64x64 x z:(Sub64 (Const64 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor64 right:(Rsh64Ux32 x y) left:(Lsh64x32 x z:(Sub32 (Const32 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor64 right:(Rsh64Ux16 x y) left:(Lsh64x16 x z:(Sub16 (Const16 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor64 right:(Rsh64Ux8 x y) left:(Lsh64x8 x z:(Sub8 (Const8 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpXor8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Xor8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c^d]) for { @@ -25839,6 +31035,314 @@ v.AddArg2(v0, x) return true } + } + break + } + // match: (Xor8 (Lsh8x64 x z:(Const64 [c])) (Rsh8Ux64 x (Const64 [d]))) + // cond: c < 8 && d == 8-c && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh8x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh8Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 8 && d == 8-c && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor8 left:(Lsh8x64 x y) right:(Rsh8Ux64 x (Sub64 (Const64 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor8 left:(Lsh8x32 x y) right:(Rsh8Ux32 x (Sub32 (Const32 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor8 left:(Lsh8x16 x y) right:(Rsh8Ux16 x (Sub16 (Const16 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor8 left:(Lsh8x8 x y) right:(Rsh8Ux8 x (Sub8 (Const8 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor8 right:(Rsh8Ux64 x y) left:(Lsh8x64 x z:(Sub64 (Const64 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor8 right:(Rsh8Ux32 x y) left:(Lsh8x32 x z:(Sub32 (Const32 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor8 right:(Rsh8Ux16 x y) left:(Lsh8x16 x z:(Sub16 (Const16 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor8 right:(Rsh8Ux8 x y) left:(Lsh8x8 x z:(Sub8 (Const8 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true } break } -- diff -- # indent-heuristic: true @@ -453,6 +453,7 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Add16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c+d]) for { @@ -724,12 +725,321 @@ } break } + // match: (Add16 (Lsh16x64 x z:(Const64 [c])) (Rsh16Ux64 x (Const64 [d]))) + // cond: c < 16 && d == 16-c && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh16x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh16Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 16 && d == 16-c && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add16 left:(Lsh16x64 x y) right:(Rsh16Ux64 x (Sub64 (Const64 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add16 left:(Lsh16x32 x y) right:(Rsh16Ux32 x (Sub32 (Const32 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add16 left:(Lsh16x16 x y) right:(Rsh16Ux16 x (Sub16 (Const16 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add16 left:(Lsh16x8 x y) right:(Rsh16Ux8 x (Sub8 (Const8 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add16 right:(Rsh16Ux64 x y) left:(Lsh16x64 x z:(Sub64 (Const64 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add16 right:(Rsh16Ux32 x y) left:(Lsh16x32 x z:(Sub32 (Const32 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add16 right:(Rsh16Ux16 x y) left:(Lsh16x16 x z:(Sub16 (Const16 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add16 right:(Rsh16Ux8 x y) left:(Lsh16x8 x z:(Sub8 (Const8 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpAdd32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Add32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c+d]) for { @@ -1001,6 +1311,314 @@ } break } + // match: (Add32 (Lsh32x64 x z:(Const64 [c])) (Rsh32Ux64 x (Const64 [d]))) + // cond: c < 32 && d == 32-c && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh32x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh32Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 32 && d == 32-c && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add32 left:(Lsh32x64 x y) right:(Rsh32Ux64 x (Sub64 (Const64 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add32 left:(Lsh32x32 x y) right:(Rsh32Ux32 x (Sub32 (Const32 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add32 left:(Lsh32x16 x y) right:(Rsh32Ux16 x (Sub16 (Const16 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add32 left:(Lsh32x8 x y) right:(Rsh32Ux8 x (Sub8 (Const8 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add32 right:(Rsh32Ux64 x y) left:(Lsh32x64 x z:(Sub64 (Const64 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add32 right:(Rsh32Ux32 x y) left:(Lsh32x32 x z:(Sub32 (Const32 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add32 right:(Rsh32Ux16 x y) left:(Lsh32x16 x z:(Sub16 (Const16 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add32 right:(Rsh32Ux8 x y) left:(Lsh32x8 x z:(Sub8 (Const8 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpAdd32F(v *Value) bool { @@ -1034,6 +1652,7 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Add64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c+d]) for { @@ -1305,6 +1924,314 @@ } break } + // match: (Add64 (Lsh64x64 x z:(Const64 [c])) (Rsh64Ux64 x (Const64 [d]))) + // cond: c < 64 && d == 64-c && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh64x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh64Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 64 && d == 64-c && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add64 left:(Lsh64x64 x y) right:(Rsh64Ux64 x (Sub64 (Const64 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add64 left:(Lsh64x32 x y) right:(Rsh64Ux32 x (Sub32 (Const32 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add64 left:(Lsh64x16 x y) right:(Rsh64Ux16 x (Sub16 (Const16 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add64 left:(Lsh64x8 x y) right:(Rsh64Ux8 x (Sub8 (Const8 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add64 right:(Rsh64Ux64 x y) left:(Lsh64x64 x z:(Sub64 (Const64 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add64 right:(Rsh64Ux32 x y) left:(Lsh64x32 x z:(Sub32 (Const32 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add64 right:(Rsh64Ux16 x y) left:(Lsh64x16 x z:(Sub16 (Const16 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add64 right:(Rsh64Ux8 x y) left:(Lsh64x8 x z:(Sub8 (Const8 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpAdd64F(v *Value) bool { @@ -1338,6 +2265,7 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Add8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c+d]) for { @@ -1609,6 +2537,314 @@ } break } + // match: (Add8 (Lsh8x64 x z:(Const64 [c])) (Rsh8Ux64 x (Const64 [d]))) + // cond: c < 8 && d == 8-c && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh8x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh8Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 8 && d == 8-c && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add8 left:(Lsh8x64 x y) right:(Rsh8Ux64 x (Sub64 (Const64 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add8 left:(Lsh8x32 x y) right:(Rsh8Ux32 x (Sub32 (Const32 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add8 left:(Lsh8x16 x y) right:(Rsh8Ux16 x (Sub16 (Const16 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add8 left:(Lsh8x8 x y) right:(Rsh8Ux8 x (Sub8 (Const8 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Add8 right:(Rsh8Ux64 x y) left:(Lsh8x64 x z:(Sub64 (Const64 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add8 right:(Rsh8Ux32 x y) left:(Lsh8x32 x z:(Sub32 (Const32 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add8 right:(Rsh8Ux16 x y) left:(Lsh8x16 x z:(Sub16 (Const16 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Add8 right:(Rsh8Ux8 x y) left:(Lsh8x8 x z:(Sub8 (Const8 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpAddPtr(v *Value) bool { @@ -17106,6 +18342,7 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Or16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c|d]) for { @@ -17295,12 +18532,321 @@ } break } + // match: (Or16 (Lsh16x64 x z:(Const64 [c])) (Rsh16Ux64 x (Const64 [d]))) + // cond: c < 16 && d == 16-c && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh16x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh16Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 16 && d == 16-c && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or16 left:(Lsh16x64 x y) right:(Rsh16Ux64 x (Sub64 (Const64 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or16 left:(Lsh16x32 x y) right:(Rsh16Ux32 x (Sub32 (Const32 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or16 left:(Lsh16x16 x y) right:(Rsh16Ux16 x (Sub16 (Const16 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or16 left:(Lsh16x8 x y) right:(Rsh16Ux8 x (Sub8 (Const8 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or16 right:(Rsh16Ux64 x y) left:(Lsh16x64 x z:(Sub64 (Const64 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or16 right:(Rsh16Ux32 x y) left:(Lsh16x32 x z:(Sub32 (Const32 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or16 right:(Rsh16Ux16 x y) left:(Lsh16x16 x z:(Sub16 (Const16 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or16 right:(Rsh16Ux8 x y) left:(Lsh16x8 x z:(Sub8 (Const8 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpOr32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Or32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c|d]) for { @@ -17490,12 +19036,321 @@ } break } + // match: (Or32 (Lsh32x64 x z:(Const64 [c])) (Rsh32Ux64 x (Const64 [d]))) + // cond: c < 32 && d == 32-c && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh32x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh32Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 32 && d == 32-c && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or32 left:(Lsh32x64 x y) right:(Rsh32Ux64 x (Sub64 (Const64 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or32 left:(Lsh32x32 x y) right:(Rsh32Ux32 x (Sub32 (Const32 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or32 left:(Lsh32x16 x y) right:(Rsh32Ux16 x (Sub16 (Const16 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or32 left:(Lsh32x8 x y) right:(Rsh32Ux8 x (Sub8 (Const8 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or32 right:(Rsh32Ux64 x y) left:(Lsh32x64 x z:(Sub64 (Const64 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or32 right:(Rsh32Ux32 x y) left:(Lsh32x32 x z:(Sub32 (Const32 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or32 right:(Rsh32Ux16 x y) left:(Lsh32x16 x z:(Sub16 (Const16 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or32 right:(Rsh32Ux8 x y) left:(Lsh32x8 x z:(Sub8 (Const8 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpOr64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Or64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c|d]) for { @@ -17685,12 +19540,321 @@ } break } + // match: (Or64 (Lsh64x64 x z:(Const64 [c])) (Rsh64Ux64 x (Const64 [d]))) + // cond: c < 64 && d == 64-c && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh64x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh64Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 64 && d == 64-c && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or64 left:(Lsh64x64 x y) right:(Rsh64Ux64 x (Sub64 (Const64 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or64 left:(Lsh64x32 x y) right:(Rsh64Ux32 x (Sub32 (Const32 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or64 left:(Lsh64x16 x y) right:(Rsh64Ux16 x (Sub16 (Const16 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or64 left:(Lsh64x8 x y) right:(Rsh64Ux8 x (Sub8 (Const8 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or64 right:(Rsh64Ux64 x y) left:(Lsh64x64 x z:(Sub64 (Const64 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or64 right:(Rsh64Ux32 x y) left:(Lsh64x32 x z:(Sub32 (Const32 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or64 right:(Rsh64Ux16 x y) left:(Lsh64x16 x z:(Sub16 (Const16 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or64 right:(Rsh64Ux8 x y) left:(Lsh64x8 x z:(Sub8 (Const8 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpOr8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Or8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c|d]) for { @@ -17880,6 +20044,314 @@ } break } + // match: (Or8 (Lsh8x64 x z:(Const64 [c])) (Rsh8Ux64 x (Const64 [d]))) + // cond: c < 8 && d == 8-c && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh8x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh8Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 8 && d == 8-c && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or8 left:(Lsh8x64 x y) right:(Rsh8Ux64 x (Sub64 (Const64 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or8 left:(Lsh8x32 x y) right:(Rsh8Ux32 x (Sub32 (Const32 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or8 left:(Lsh8x16 x y) right:(Rsh8Ux16 x (Sub16 (Const16 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or8 left:(Lsh8x8 x y) right:(Rsh8Ux8 x (Sub8 (Const8 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Or8 right:(Rsh8Ux64 x y) left:(Lsh8x64 x z:(Sub64 (Const64 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or8 right:(Rsh8Ux32 x y) left:(Lsh8x32 x z:(Sub32 (Const32 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or8 right:(Rsh8Ux16 x y) left:(Lsh8x16 x z:(Sub16 (Const16 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Or8 right:(Rsh8Ux8 x y) left:(Lsh8x8 x z:(Sub8 (Const8 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpOrB(v *Value) bool { @@ -19330,6 +21802,8 @@ func rewriteValuegeneric_OpRotateLeft16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + b := v.Block + config := b.Func.Config // match: (RotateLeft16 x (Const16 [c])) // cond: c%16 == 0 // result: x @@ -19345,11 +21819,460 @@ v.copyOf(x) return true } + // match: (RotateLeft16 x (And64 y (Const64 [c]))) + // cond: c&15 == 15 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAnd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (And32 y (Const32 [c]))) + // cond: c&15 == 15 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAnd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (And16 y (Const16 [c]))) + // cond: c&15 == 15 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAnd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (And8 y (Const8 [c]))) + // cond: c&15 == 15 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAnd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (Neg64 (And64 y (Const64 [c])))) + // cond: c&15 == 15 + // result: (RotateLeft16 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpNeg64 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_0_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft16 x (Neg32 (And32 y (Const32 [c])))) + // cond: c&15 == 15 + // result: (RotateLeft16 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpNeg32 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_0_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft16 x (Neg16 (And16 y (Const16 [c])))) + // cond: c&15 == 15 + // result: (RotateLeft16 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpNeg16 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd16 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_0_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft16 x (Neg8 (And8 y (Const8 [c])))) + // cond: c&15 == 15 + // result: (RotateLeft16 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpNeg8 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd8 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_0_1.AuxInt) + if !(c&15 == 15) { + continue + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft16 x (Add64 y (Const64 [c]))) + // cond: c&15 == 0 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAdd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&15 == 0) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (Add32 y (Const32 [c]))) + // cond: c&15 == 0 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAdd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&15 == 0) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (Add16 y (Const16 [c]))) + // cond: c&15 == 0 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAdd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&15 == 0) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (Add8 y (Const8 [c]))) + // cond: c&15 == 0 + // result: (RotateLeft16 x y) + for { + x := v_0 + if v_1.Op != OpAdd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&15 == 0) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft16 x (Sub64 (Const64 [c]) y)) + // cond: c&15 == 0 + // result: (RotateLeft16 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpSub64 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1_0.AuxInt) + if !(c&15 == 0) { + break + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft16 x (Sub32 (Const32 [c]) y)) + // cond: c&15 == 0 + // result: (RotateLeft16 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpSub32 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + if !(c&15 == 0) { + break + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft16 x (Sub16 (Const16 [c]) y)) + // cond: c&15 == 0 + // result: (RotateLeft16 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpSub16 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1_0.AuxInt) + if !(c&15 == 0) { + break + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft16 x (Sub8 (Const8 [c]) y)) + // cond: c&15 == 0 + // result: (RotateLeft16 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpSub8 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1_0.AuxInt) + if !(c&15 == 0) { + break + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft16 x (Const64 [c])) + // cond: config.PtrSize == 4 + // result: (RotateLeft16 x (Const32 [int32(c)])) + for { + x := v_0 + if v_1.Op != OpConst64 { + break + } + t := v_1.Type + c := auxIntToInt64(v_1.AuxInt) + if !(config.PtrSize == 4) { + break + } + v.reset(OpRotateLeft16) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg2(x, v0) + return true + } return false } func rewriteValuegeneric_OpRotateLeft32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + b := v.Block + config := b.Func.Config // match: (RotateLeft32 x (Const32 [c])) // cond: c%32 == 0 // result: x @@ -19365,11 +22288,460 @@ v.copyOf(x) return true } + // match: (RotateLeft32 x (And64 y (Const64 [c]))) + // cond: c&31 == 31 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAnd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (And32 y (Const32 [c]))) + // cond: c&31 == 31 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAnd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (And16 y (Const16 [c]))) + // cond: c&31 == 31 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAnd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (And8 y (Const8 [c]))) + // cond: c&31 == 31 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAnd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (Neg64 (And64 y (Const64 [c])))) + // cond: c&31 == 31 + // result: (RotateLeft32 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpNeg64 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_0_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft32 x (Neg32 (And32 y (Const32 [c])))) + // cond: c&31 == 31 + // result: (RotateLeft32 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpNeg32 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_0_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft32 x (Neg16 (And16 y (Const16 [c])))) + // cond: c&31 == 31 + // result: (RotateLeft32 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpNeg16 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd16 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_0_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft32 x (Neg8 (And8 y (Const8 [c])))) + // cond: c&31 == 31 + // result: (RotateLeft32 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpNeg8 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd8 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_0_1.AuxInt) + if !(c&31 == 31) { + continue + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft32 x (Add64 y (Const64 [c]))) + // cond: c&31 == 0 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAdd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&31 == 0) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (Add32 y (Const32 [c]))) + // cond: c&31 == 0 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAdd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&31 == 0) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (Add16 y (Const16 [c]))) + // cond: c&31 == 0 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAdd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&31 == 0) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (Add8 y (Const8 [c]))) + // cond: c&31 == 0 + // result: (RotateLeft32 x y) + for { + x := v_0 + if v_1.Op != OpAdd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&31 == 0) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft32 x (Sub64 (Const64 [c]) y)) + // cond: c&31 == 0 + // result: (RotateLeft32 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpSub64 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1_0.AuxInt) + if !(c&31 == 0) { + break + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft32 x (Sub32 (Const32 [c]) y)) + // cond: c&31 == 0 + // result: (RotateLeft32 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpSub32 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + if !(c&31 == 0) { + break + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft32 x (Sub16 (Const16 [c]) y)) + // cond: c&31 == 0 + // result: (RotateLeft32 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpSub16 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1_0.AuxInt) + if !(c&31 == 0) { + break + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft32 x (Sub8 (Const8 [c]) y)) + // cond: c&31 == 0 + // result: (RotateLeft32 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpSub8 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1_0.AuxInt) + if !(c&31 == 0) { + break + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft32 x (Const64 [c])) + // cond: config.PtrSize == 4 + // result: (RotateLeft32 x (Const32 [int32(c)])) + for { + x := v_0 + if v_1.Op != OpConst64 { + break + } + t := v_1.Type + c := auxIntToInt64(v_1.AuxInt) + if !(config.PtrSize == 4) { + break + } + v.reset(OpRotateLeft32) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg2(x, v0) + return true + } return false } func rewriteValuegeneric_OpRotateLeft64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + b := v.Block + config := b.Func.Config // match: (RotateLeft64 x (Const64 [c])) // cond: c%64 == 0 // result: x @@ -19385,11 +22757,460 @@ v.copyOf(x) return true } + // match: (RotateLeft64 x (And64 y (Const64 [c]))) + // cond: c&63 == 63 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAnd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (And32 y (Const32 [c]))) + // cond: c&63 == 63 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAnd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (And16 y (Const16 [c]))) + // cond: c&63 == 63 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAnd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (And8 y (Const8 [c]))) + // cond: c&63 == 63 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAnd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (Neg64 (And64 y (Const64 [c])))) + // cond: c&63 == 63 + // result: (RotateLeft64 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpNeg64 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_0_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft64 x (Neg32 (And32 y (Const32 [c])))) + // cond: c&63 == 63 + // result: (RotateLeft64 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpNeg32 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_0_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft64 x (Neg16 (And16 y (Const16 [c])))) + // cond: c&63 == 63 + // result: (RotateLeft64 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpNeg16 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd16 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_0_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft64 x (Neg8 (And8 y (Const8 [c])))) + // cond: c&63 == 63 + // result: (RotateLeft64 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpNeg8 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd8 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_0_1.AuxInt) + if !(c&63 == 63) { + continue + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft64 x (Add64 y (Const64 [c]))) + // cond: c&63 == 0 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAdd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&63 == 0) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (Add32 y (Const32 [c]))) + // cond: c&63 == 0 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAdd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&63 == 0) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (Add16 y (Const16 [c]))) + // cond: c&63 == 0 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAdd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&63 == 0) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (Add8 y (Const8 [c]))) + // cond: c&63 == 0 + // result: (RotateLeft64 x y) + for { + x := v_0 + if v_1.Op != OpAdd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&63 == 0) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft64 x (Sub64 (Const64 [c]) y)) + // cond: c&63 == 0 + // result: (RotateLeft64 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpSub64 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1_0.AuxInt) + if !(c&63 == 0) { + break + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft64 x (Sub32 (Const32 [c]) y)) + // cond: c&63 == 0 + // result: (RotateLeft64 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpSub32 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + if !(c&63 == 0) { + break + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft64 x (Sub16 (Const16 [c]) y)) + // cond: c&63 == 0 + // result: (RotateLeft64 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpSub16 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1_0.AuxInt) + if !(c&63 == 0) { + break + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft64 x (Sub8 (Const8 [c]) y)) + // cond: c&63 == 0 + // result: (RotateLeft64 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpSub8 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1_0.AuxInt) + if !(c&63 == 0) { + break + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft64 x (Const64 [c])) + // cond: config.PtrSize == 4 + // result: (RotateLeft64 x (Const32 [int32(c)])) + for { + x := v_0 + if v_1.Op != OpConst64 { + break + } + t := v_1.Type + c := auxIntToInt64(v_1.AuxInt) + if !(config.PtrSize == 4) { + break + } + v.reset(OpRotateLeft64) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg2(x, v0) + return true + } return false } func rewriteValuegeneric_OpRotateLeft8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] + b := v.Block + config := b.Func.Config // match: (RotateLeft8 x (Const8 [c])) // cond: c%8 == 0 // result: x @@ -19405,6 +23226,453 @@ v.copyOf(x) return true } + // match: (RotateLeft8 x (And64 y (Const64 [c]))) + // cond: c&7 == 7 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAnd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (And32 y (Const32 [c]))) + // cond: c&7 == 7 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAnd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (And16 y (Const16 [c]))) + // cond: c&7 == 7 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAnd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (And8 y (Const8 [c]))) + // cond: c&7 == 7 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAnd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (Neg64 (And64 y (Const64 [c])))) + // cond: c&7 == 7 + // result: (RotateLeft8 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpNeg64 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd64 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_0_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft8 x (Neg32 (And32 y (Const32 [c])))) + // cond: c&7 == 7 + // result: (RotateLeft8 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpNeg32 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd32 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_0_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft8 x (Neg16 (And16 y (Const16 [c])))) + // cond: c&7 == 7 + // result: (RotateLeft8 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpNeg16 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd16 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_0_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft8 x (Neg8 (And8 y (Const8 [c])))) + // cond: c&7 == 7 + // result: (RotateLeft8 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpNeg8 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAnd8 { + break + } + _ = v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + v_1_0_1 := v_1_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0_0, v_1_0_1 = _i0+1, v_1_0_1, v_1_0_0 { + y := v_1_0_0 + if v_1_0_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_0_1.AuxInt) + if !(c&7 == 7) { + continue + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + break + } + // match: (RotateLeft8 x (Add64 y (Const64 [c]))) + // cond: c&7 == 0 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAdd64 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst64 { + continue + } + c := auxIntToInt64(v_1_1.AuxInt) + if !(c&7 == 0) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (Add32 y (Const32 [c]))) + // cond: c&7 == 0 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAdd32 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst32 { + continue + } + c := auxIntToInt32(v_1_1.AuxInt) + if !(c&7 == 0) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (Add16 y (Const16 [c]))) + // cond: c&7 == 0 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAdd16 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst16 { + continue + } + c := auxIntToInt16(v_1_1.AuxInt) + if !(c&7 == 0) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (Add8 y (Const8 [c]))) + // cond: c&7 == 0 + // result: (RotateLeft8 x y) + for { + x := v_0 + if v_1.Op != OpAdd8 { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + y := v_1_0 + if v_1_1.Op != OpConst8 { + continue + } + c := auxIntToInt8(v_1_1.AuxInt) + if !(c&7 == 0) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (RotateLeft8 x (Sub64 (Const64 [c]) y)) + // cond: c&7 == 0 + // result: (RotateLeft8 x (Neg64 y)) + for { + x := v_0 + if v_1.Op != OpSub64 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst64 { + break + } + c := auxIntToInt64(v_1_0.AuxInt) + if !(c&7 == 0) { + break + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg64, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft8 x (Sub32 (Const32 [c]) y)) + // cond: c&7 == 0 + // result: (RotateLeft8 x (Neg32 y)) + for { + x := v_0 + if v_1.Op != OpSub32 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst32 { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + if !(c&7 == 0) { + break + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg32, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft8 x (Sub16 (Const16 [c]) y)) + // cond: c&7 == 0 + // result: (RotateLeft8 x (Neg16 y)) + for { + x := v_0 + if v_1.Op != OpSub16 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst16 { + break + } + c := auxIntToInt16(v_1_0.AuxInt) + if !(c&7 == 0) { + break + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg16, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft8 x (Sub8 (Const8 [c]) y)) + // cond: c&7 == 0 + // result: (RotateLeft8 x (Neg8 y)) + for { + x := v_0 + if v_1.Op != OpSub8 { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpConst8 { + break + } + c := auxIntToInt8(v_1_0.AuxInt) + if !(c&7 == 0) { + break + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpNeg8, y.Type) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (RotateLeft8 x (Const64 [c])) + // cond: config.PtrSize == 4 + // result: (RotateLeft8 x (Const32 [int32(c)])) + for { + x := v_0 + if v_1.Op != OpConst64 { + break + } + t := v_1.Type + c := auxIntToInt64(v_1.AuxInt) + if !(config.PtrSize == 4) { + break + } + v.reset(OpRotateLeft8) + v0 := b.NewValue0(v.Pos, OpConst32, t) + v0.AuxInt = int32ToAuxInt(int32(c)) + v.AddArg2(x, v0) + return true + } return false } func rewriteValuegeneric_OpRound32F(v *Value) bool { @@ -25200,6 +29468,7 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Xor16 (Const16 [c]) (Const16 [d])) // result: (Const16 [c^d]) for { @@ -25356,12 +29625,321 @@ } break } + // match: (Xor16 (Lsh16x64 x z:(Const64 [c])) (Rsh16Ux64 x (Const64 [d]))) + // cond: c < 16 && d == 16-c && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh16x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh16Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 16 && d == 16-c && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor16 left:(Lsh16x64 x y) right:(Rsh16Ux64 x (Sub64 (Const64 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor16 left:(Lsh16x32 x y) right:(Rsh16Ux32 x (Sub32 (Const32 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor16 left:(Lsh16x16 x y) right:(Rsh16Ux16 x (Sub16 (Const16 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor16 left:(Lsh16x8 x y) right:(Rsh16Ux8 x (Sub8 (Const8 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh16x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh16Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 16 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor16 right:(Rsh16Ux64 x y) left:(Lsh16x64 x z:(Sub64 (Const64 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor16 right:(Rsh16Ux32 x y) left:(Lsh16x32 x z:(Sub32 (Const32 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor16 right:(Rsh16Ux16 x y) left:(Lsh16x16 x z:(Sub16 (Const16 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor16 right:(Rsh16Ux8 x y) left:(Lsh16x8 x z:(Sub8 (Const8 [16]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16) + // result: (RotateLeft16 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh16Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh16x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 16 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)) { + continue + } + v.reset(OpRotateLeft16) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpXor32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Xor32 (Const32 [c]) (Const32 [d])) // result: (Const32 [c^d]) for { @@ -25518,12 +30096,321 @@ } break } + // match: (Xor32 (Lsh32x64 x z:(Const64 [c])) (Rsh32Ux64 x (Const64 [d]))) + // cond: c < 32 && d == 32-c && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh32x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh32Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 32 && d == 32-c && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor32 left:(Lsh32x64 x y) right:(Rsh32Ux64 x (Sub64 (Const64 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor32 left:(Lsh32x32 x y) right:(Rsh32Ux32 x (Sub32 (Const32 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor32 left:(Lsh32x16 x y) right:(Rsh32Ux16 x (Sub16 (Const16 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor32 left:(Lsh32x8 x y) right:(Rsh32Ux8 x (Sub8 (Const8 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh32x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh32Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 32 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor32 right:(Rsh32Ux64 x y) left:(Lsh32x64 x z:(Sub64 (Const64 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor32 right:(Rsh32Ux32 x y) left:(Lsh32x32 x z:(Sub32 (Const32 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor32 right:(Rsh32Ux16 x y) left:(Lsh32x16 x z:(Sub16 (Const16 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor32 right:(Rsh32Ux8 x y) left:(Lsh32x8 x z:(Sub8 (Const8 [32]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32) + // result: (RotateLeft32 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh32Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh32x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 32 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 32)) { + continue + } + v.reset(OpRotateLeft32) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpXor64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Xor64 (Const64 [c]) (Const64 [d])) // result: (Const64 [c^d]) for { @@ -25680,12 +30567,321 @@ } break } + // match: (Xor64 (Lsh64x64 x z:(Const64 [c])) (Rsh64Ux64 x (Const64 [d]))) + // cond: c < 64 && d == 64-c && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh64x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh64Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 64 && d == 64-c && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor64 left:(Lsh64x64 x y) right:(Rsh64Ux64 x (Sub64 (Const64 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor64 left:(Lsh64x32 x y) right:(Rsh64Ux32 x (Sub32 (Const32 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor64 left:(Lsh64x16 x y) right:(Rsh64Ux16 x (Sub16 (Const16 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor64 left:(Lsh64x8 x y) right:(Rsh64Ux8 x (Sub8 (Const8 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh64x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh64Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 64 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor64 right:(Rsh64Ux64 x y) left:(Lsh64x64 x z:(Sub64 (Const64 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor64 right:(Rsh64Ux32 x y) left:(Lsh64x32 x z:(Sub32 (Const32 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor64 right:(Rsh64Ux16 x y) left:(Lsh64x16 x z:(Sub16 (Const16 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor64 right:(Rsh64Ux8 x y) left:(Lsh64x8 x z:(Sub8 (Const8 [64]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) + // result: (RotateLeft64 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh64Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh64x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 64 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64)) { + continue + } + v.reset(OpRotateLeft64) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpXor8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + config := b.Func.Config // match: (Xor8 (Const8 [c]) (Const8 [d])) // result: (Const8 [c^d]) for { @@ -25842,6 +31038,314 @@ } break } + // match: (Xor8 (Lsh8x64 x z:(Const64 [c])) (Rsh8Ux64 x (Const64 [d]))) + // cond: c < 8 && d == 8-c && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpLsh8x64 { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + z := v_0.Args[1] + if z.Op != OpConst64 { + continue + } + c := auxIntToInt64(z.AuxInt) + if v_1.Op != OpRsh8Ux64 { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpConst64 { + continue + } + d := auxIntToInt64(v_1_1.AuxInt) + if !(c < 8 && d == 8-c && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor8 left:(Lsh8x64 x y) right:(Rsh8Ux64 x (Sub64 (Const64 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x64 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux64 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub64 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst64 || auxIntToInt64(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor8 left:(Lsh8x32 x y) right:(Rsh8Ux32 x (Sub32 (Const32 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x32 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux32 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub32 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst32 || auxIntToInt32(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor8 left:(Lsh8x16 x y) right:(Rsh8Ux16 x (Sub16 (Const16 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x16 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux16 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub16 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst16 || auxIntToInt16(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor8 left:(Lsh8x8 x y) right:(Rsh8Ux8 x (Sub8 (Const8 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + left := v_0 + if left.Op != OpLsh8x8 { + continue + } + y := left.Args[1] + x := left.Args[0] + right := v_1 + if right.Op != OpRsh8Ux8 { + continue + } + _ = right.Args[1] + if x != right.Args[0] { + continue + } + right_1 := right.Args[1] + if right_1.Op != OpSub8 { + continue + } + _ = right_1.Args[1] + right_1_0 := right_1.Args[0] + if right_1_0.Op != OpConst8 || auxIntToInt8(right_1_0.AuxInt) != 8 || y != right_1.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, y) + return true + } + break + } + // match: (Xor8 right:(Rsh8Ux64 x y) left:(Lsh8x64 x z:(Sub64 (Const64 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux64 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x64 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub64 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst64 || auxIntToInt64(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor8 right:(Rsh8Ux32 x y) left:(Lsh8x32 x z:(Sub32 (Const32 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux32 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x32 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub32 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst32 || auxIntToInt32(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor8 right:(Rsh8Ux16 x y) left:(Lsh8x16 x z:(Sub16 (Const16 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux16 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x16 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub16 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst16 || auxIntToInt16(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } + // match: (Xor8 right:(Rsh8Ux8 x y) left:(Lsh8x8 x z:(Sub8 (Const8 [8]) y))) + // cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8) + // result: (RotateLeft8 x z) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + right := v_0 + if right.Op != OpRsh8Ux8 { + continue + } + y := right.Args[1] + x := right.Args[0] + left := v_1 + if left.Op != OpLsh8x8 { + continue + } + _ = left.Args[1] + if x != left.Args[0] { + continue + } + z := left.Args[1] + if z.Op != OpSub8 { + continue + } + _ = z.Args[1] + z_0 := z.Args[0] + if z_0.Op != OpConst8 || auxIntToInt8(z_0.AuxInt) != 8 || y != z.Args[1] || !((shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 8)) { + continue + } + v.reset(OpRotateLeft8) + v.AddArg2(x, z) + return true + } + break + } return false } func rewriteValuegeneric_OpZero(v *Value) bool { go_66f03f79dadc6005d30a6edf4419b8f6c0fa6398_src_cmd_compile_internal_ssa_rewriteAMD64.go.test000066400000000000000000071376251516001707200357410ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit 66f03f79dadc6005d30a6edf4419b8f6c0fa6398 file src/cmd/compile/internal/ssa/rewriteAMD64.go -- x -- // Code generated from gen/AMD64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "internal/buildcfg" import "math" import "cmd/internal/obj" import "cmd/compile/internal/types" func rewriteValueAMD64(v *Value) bool { switch v.Op { case OpAMD64ADCQ: return rewriteValueAMD64_OpAMD64ADCQ(v) case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst(v) case OpAMD64ADDL: return rewriteValueAMD64_OpAMD64ADDL(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst(v) case OpAMD64ADDLconstmodify: return rewriteValueAMD64_OpAMD64ADDLconstmodify(v) case OpAMD64ADDLload: return rewriteValueAMD64_OpAMD64ADDLload(v) case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify(v) case OpAMD64ADDQ: return rewriteValueAMD64_OpAMD64ADDQ(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry(v) case OpAMD64ADDQconst: return rewriteValueAMD64_OpAMD64ADDQconst(v) case OpAMD64ADDQconstmodify: return rewriteValueAMD64_OpAMD64ADDQconstmodify(v) case OpAMD64ADDQload: return rewriteValueAMD64_OpAMD64ADDQload(v) case OpAMD64ADDQmodify: return rewriteValueAMD64_OpAMD64ADDQmodify(v) case OpAMD64ADDSD: return rewriteValueAMD64_OpAMD64ADDSD(v) case OpAMD64ADDSDload: return rewriteValueAMD64_OpAMD64ADDSDload(v) case OpAMD64ADDSS: return rewriteValueAMD64_OpAMD64ADDSS(v) case OpAMD64ADDSSload: return rewriteValueAMD64_OpAMD64ADDSSload(v) case OpAMD64ANDL: return rewriteValueAMD64_OpAMD64ANDL(v) case OpAMD64ANDLconst: return rewriteValueAMD64_OpAMD64ANDLconst(v) case OpAMD64ANDLconstmodify: return rewriteValueAMD64_OpAMD64ANDLconstmodify(v) case OpAMD64ANDLload: return rewriteValueAMD64_OpAMD64ANDLload(v) case OpAMD64ANDLmodify: return rewriteValueAMD64_OpAMD64ANDLmodify(v) case OpAMD64ANDNL: return rewriteValueAMD64_OpAMD64ANDNL(v) case OpAMD64ANDNQ: return rewriteValueAMD64_OpAMD64ANDNQ(v) case OpAMD64ANDQ: return rewriteValueAMD64_OpAMD64ANDQ(v) case OpAMD64ANDQconst: return rewriteValueAMD64_OpAMD64ANDQconst(v) case OpAMD64ANDQconstmodify: return rewriteValueAMD64_OpAMD64ANDQconstmodify(v) case OpAMD64ANDQload: return rewriteValueAMD64_OpAMD64ANDQload(v) case OpAMD64ANDQmodify: return rewriteValueAMD64_OpAMD64ANDQmodify(v) case OpAMD64BSFQ: return rewriteValueAMD64_OpAMD64BSFQ(v) case OpAMD64BSWAPL: return rewriteValueAMD64_OpAMD64BSWAPL(v) case OpAMD64BSWAPQ: return rewriteValueAMD64_OpAMD64BSWAPQ(v) case OpAMD64BTCLconst: return rewriteValueAMD64_OpAMD64BTCLconst(v) case OpAMD64BTCQconst: return rewriteValueAMD64_OpAMD64BTCQconst(v) case OpAMD64BTLconst: return rewriteValueAMD64_OpAMD64BTLconst(v) case OpAMD64BTQconst: return rewriteValueAMD64_OpAMD64BTQconst(v) case OpAMD64BTRLconst: return rewriteValueAMD64_OpAMD64BTRLconst(v) case OpAMD64BTRQconst: return rewriteValueAMD64_OpAMD64BTRQconst(v) case OpAMD64BTSLconst: return rewriteValueAMD64_OpAMD64BTSLconst(v) case OpAMD64BTSQconst: return rewriteValueAMD64_OpAMD64BTSQconst(v) case OpAMD64CMOVLCC: return rewriteValueAMD64_OpAMD64CMOVLCC(v) case OpAMD64CMOVLCS: return rewriteValueAMD64_OpAMD64CMOVLCS(v) case OpAMD64CMOVLEQ: return rewriteValueAMD64_OpAMD64CMOVLEQ(v) case OpAMD64CMOVLGE: return rewriteValueAMD64_OpAMD64CMOVLGE(v) case OpAMD64CMOVLGT: return rewriteValueAMD64_OpAMD64CMOVLGT(v) case OpAMD64CMOVLHI: return rewriteValueAMD64_OpAMD64CMOVLHI(v) case OpAMD64CMOVLLE: return rewriteValueAMD64_OpAMD64CMOVLLE(v) case OpAMD64CMOVLLS: return rewriteValueAMD64_OpAMD64CMOVLLS(v) case OpAMD64CMOVLLT: return rewriteValueAMD64_OpAMD64CMOVLLT(v) case OpAMD64CMOVLNE: return rewriteValueAMD64_OpAMD64CMOVLNE(v) case OpAMD64CMOVQCC: return rewriteValueAMD64_OpAMD64CMOVQCC(v) case OpAMD64CMOVQCS: return rewriteValueAMD64_OpAMD64CMOVQCS(v) case OpAMD64CMOVQEQ: return rewriteValueAMD64_OpAMD64CMOVQEQ(v) case OpAMD64CMOVQGE: return rewriteValueAMD64_OpAMD64CMOVQGE(v) case OpAMD64CMOVQGT: return rewriteValueAMD64_OpAMD64CMOVQGT(v) case OpAMD64CMOVQHI: return rewriteValueAMD64_OpAMD64CMOVQHI(v) case OpAMD64CMOVQLE: return rewriteValueAMD64_OpAMD64CMOVQLE(v) case OpAMD64CMOVQLS: return rewriteValueAMD64_OpAMD64CMOVQLS(v) case OpAMD64CMOVQLT: return rewriteValueAMD64_OpAMD64CMOVQLT(v) case OpAMD64CMOVQNE: return rewriteValueAMD64_OpAMD64CMOVQNE(v) case OpAMD64CMOVWCC: return rewriteValueAMD64_OpAMD64CMOVWCC(v) case OpAMD64CMOVWCS: return rewriteValueAMD64_OpAMD64CMOVWCS(v) case OpAMD64CMOVWEQ: return rewriteValueAMD64_OpAMD64CMOVWEQ(v) case OpAMD64CMOVWGE: return rewriteValueAMD64_OpAMD64CMOVWGE(v) case OpAMD64CMOVWGT: return rewriteValueAMD64_OpAMD64CMOVWGT(v) case OpAMD64CMOVWHI: return rewriteValueAMD64_OpAMD64CMOVWHI(v) case OpAMD64CMOVWLE: return rewriteValueAMD64_OpAMD64CMOVWLE(v) case OpAMD64CMOVWLS: return rewriteValueAMD64_OpAMD64CMOVWLS(v) case OpAMD64CMOVWLT: return rewriteValueAMD64_OpAMD64CMOVWLT(v) case OpAMD64CMOVWNE: return rewriteValueAMD64_OpAMD64CMOVWNE(v) case OpAMD64CMPB: return rewriteValueAMD64_OpAMD64CMPB(v) case OpAMD64CMPBconst: return rewriteValueAMD64_OpAMD64CMPBconst(v) case OpAMD64CMPBconstload: return rewriteValueAMD64_OpAMD64CMPBconstload(v) case OpAMD64CMPBload: return rewriteValueAMD64_OpAMD64CMPBload(v) case OpAMD64CMPL: return rewriteValueAMD64_OpAMD64CMPL(v) case OpAMD64CMPLconst: return rewriteValueAMD64_OpAMD64CMPLconst(v) case OpAMD64CMPLconstload: return rewriteValueAMD64_OpAMD64CMPLconstload(v) case OpAMD64CMPLload: return rewriteValueAMD64_OpAMD64CMPLload(v) case OpAMD64CMPQ: return rewriteValueAMD64_OpAMD64CMPQ(v) case OpAMD64CMPQconst: return rewriteValueAMD64_OpAMD64CMPQconst(v) case OpAMD64CMPQconstload: return rewriteValueAMD64_OpAMD64CMPQconstload(v) case OpAMD64CMPQload: return rewriteValueAMD64_OpAMD64CMPQload(v) case OpAMD64CMPW: return rewriteValueAMD64_OpAMD64CMPW(v) case OpAMD64CMPWconst: return rewriteValueAMD64_OpAMD64CMPWconst(v) case OpAMD64CMPWconstload: return rewriteValueAMD64_OpAMD64CMPWconstload(v) case OpAMD64CMPWload: return rewriteValueAMD64_OpAMD64CMPWload(v) case OpAMD64CMPXCHGLlock: return rewriteValueAMD64_OpAMD64CMPXCHGLlock(v) case OpAMD64CMPXCHGQlock: return rewriteValueAMD64_OpAMD64CMPXCHGQlock(v) case OpAMD64DIVSD: return rewriteValueAMD64_OpAMD64DIVSD(v) case OpAMD64DIVSDload: return rewriteValueAMD64_OpAMD64DIVSDload(v) case OpAMD64DIVSS: return rewriteValueAMD64_OpAMD64DIVSS(v) case OpAMD64DIVSSload: return rewriteValueAMD64_OpAMD64DIVSSload(v) case OpAMD64HMULL: return rewriteValueAMD64_OpAMD64HMULL(v) case OpAMD64HMULLU: return rewriteValueAMD64_OpAMD64HMULLU(v) case OpAMD64HMULQ: return rewriteValueAMD64_OpAMD64HMULQ(v) case OpAMD64HMULQU: return rewriteValueAMD64_OpAMD64HMULQU(v) case OpAMD64LEAL: return rewriteValueAMD64_OpAMD64LEAL(v) case OpAMD64LEAL1: return rewriteValueAMD64_OpAMD64LEAL1(v) case OpAMD64LEAL2: return rewriteValueAMD64_OpAMD64LEAL2(v) case OpAMD64LEAL4: return rewriteValueAMD64_OpAMD64LEAL4(v) case OpAMD64LEAL8: return rewriteValueAMD64_OpAMD64LEAL8(v) case OpAMD64LEAQ: return rewriteValueAMD64_OpAMD64LEAQ(v) case OpAMD64LEAQ1: return rewriteValueAMD64_OpAMD64LEAQ1(v) case OpAMD64LEAQ2: return rewriteValueAMD64_OpAMD64LEAQ2(v) case OpAMD64LEAQ4: return rewriteValueAMD64_OpAMD64LEAQ4(v) case OpAMD64LEAQ8: return rewriteValueAMD64_OpAMD64LEAQ8(v) case OpAMD64MOVBELstore: return rewriteValueAMD64_OpAMD64MOVBELstore(v) case OpAMD64MOVBEQstore: return rewriteValueAMD64_OpAMD64MOVBEQstore(v) case OpAMD64MOVBEWstore: return rewriteValueAMD64_OpAMD64MOVBEWstore(v) case OpAMD64MOVBQSX: return rewriteValueAMD64_OpAMD64MOVBQSX(v) case OpAMD64MOVBQSXload: return rewriteValueAMD64_OpAMD64MOVBQSXload(v) case OpAMD64MOVBQZX: return rewriteValueAMD64_OpAMD64MOVBQZX(v) case OpAMD64MOVBatomicload: return rewriteValueAMD64_OpAMD64MOVBatomicload(v) case OpAMD64MOVBload: return rewriteValueAMD64_OpAMD64MOVBload(v) case OpAMD64MOVBstore: return rewriteValueAMD64_OpAMD64MOVBstore(v) case OpAMD64MOVBstoreconst: return rewriteValueAMD64_OpAMD64MOVBstoreconst(v) case OpAMD64MOVLQSX: return rewriteValueAMD64_OpAMD64MOVLQSX(v) case OpAMD64MOVLQSXload: return rewriteValueAMD64_OpAMD64MOVLQSXload(v) case OpAMD64MOVLQZX: return rewriteValueAMD64_OpAMD64MOVLQZX(v) case OpAMD64MOVLatomicload: return rewriteValueAMD64_OpAMD64MOVLatomicload(v) case OpAMD64MOVLf2i: return rewriteValueAMD64_OpAMD64MOVLf2i(v) case OpAMD64MOVLi2f: return rewriteValueAMD64_OpAMD64MOVLi2f(v) case OpAMD64MOVLload: return rewriteValueAMD64_OpAMD64MOVLload(v) case OpAMD64MOVLstore: return rewriteValueAMD64_OpAMD64MOVLstore(v) case OpAMD64MOVLstoreconst: return rewriteValueAMD64_OpAMD64MOVLstoreconst(v) case OpAMD64MOVOload: return rewriteValueAMD64_OpAMD64MOVOload(v) case OpAMD64MOVOstore: return rewriteValueAMD64_OpAMD64MOVOstore(v) case OpAMD64MOVOstoreconst: return rewriteValueAMD64_OpAMD64MOVOstoreconst(v) case OpAMD64MOVQatomicload: return rewriteValueAMD64_OpAMD64MOVQatomicload(v) case OpAMD64MOVQf2i: return rewriteValueAMD64_OpAMD64MOVQf2i(v) case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f(v) case OpAMD64MOVQload: return rewriteValueAMD64_OpAMD64MOVQload(v) case OpAMD64MOVQstore: return rewriteValueAMD64_OpAMD64MOVQstore(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst(v) case OpAMD64MOVSDload: return rewriteValueAMD64_OpAMD64MOVSDload(v) case OpAMD64MOVSDstore: return rewriteValueAMD64_OpAMD64MOVSDstore(v) case OpAMD64MOVSSload: return rewriteValueAMD64_OpAMD64MOVSSload(v) case OpAMD64MOVSSstore: return rewriteValueAMD64_OpAMD64MOVSSstore(v) case OpAMD64MOVWQSX: return rewriteValueAMD64_OpAMD64MOVWQSX(v) case OpAMD64MOVWQSXload: return rewriteValueAMD64_OpAMD64MOVWQSXload(v) case OpAMD64MOVWQZX: return rewriteValueAMD64_OpAMD64MOVWQZX(v) case OpAMD64MOVWload: return rewriteValueAMD64_OpAMD64MOVWload(v) case OpAMD64MOVWstore: return rewriteValueAMD64_OpAMD64MOVWstore(v) case OpAMD64MOVWstoreconst: return rewriteValueAMD64_OpAMD64MOVWstoreconst(v) case OpAMD64MULL: return rewriteValueAMD64_OpAMD64MULL(v) case OpAMD64MULLconst: return rewriteValueAMD64_OpAMD64MULLconst(v) case OpAMD64MULQ: return rewriteValueAMD64_OpAMD64MULQ(v) case OpAMD64MULQconst: return rewriteValueAMD64_OpAMD64MULQconst(v) case OpAMD64MULSD: return rewriteValueAMD64_OpAMD64MULSD(v) case OpAMD64MULSDload: return rewriteValueAMD64_OpAMD64MULSDload(v) case OpAMD64MULSS: return rewriteValueAMD64_OpAMD64MULSS(v) case OpAMD64MULSSload: return rewriteValueAMD64_OpAMD64MULSSload(v) case OpAMD64NEGL: return rewriteValueAMD64_OpAMD64NEGL(v) case OpAMD64NEGQ: return rewriteValueAMD64_OpAMD64NEGQ(v) case OpAMD64NOTL: return rewriteValueAMD64_OpAMD64NOTL(v) case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ(v) case OpAMD64ORL: return rewriteValueAMD64_OpAMD64ORL(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst(v) case OpAMD64ORLconstmodify: return rewriteValueAMD64_OpAMD64ORLconstmodify(v) case OpAMD64ORLload: return rewriteValueAMD64_OpAMD64ORLload(v) case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify(v) case OpAMD64ORQ: return rewriteValueAMD64_OpAMD64ORQ(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst(v) case OpAMD64ORQconstmodify: return rewriteValueAMD64_OpAMD64ORQconstmodify(v) case OpAMD64ORQload: return rewriteValueAMD64_OpAMD64ORQload(v) case OpAMD64ORQmodify: return rewriteValueAMD64_OpAMD64ORQmodify(v) case OpAMD64ROLB: return rewriteValueAMD64_OpAMD64ROLB(v) case OpAMD64ROLBconst: return rewriteValueAMD64_OpAMD64ROLBconst(v) case OpAMD64ROLL: return rewriteValueAMD64_OpAMD64ROLL(v) case OpAMD64ROLLconst: return rewriteValueAMD64_OpAMD64ROLLconst(v) case OpAMD64ROLQ: return rewriteValueAMD64_OpAMD64ROLQ(v) case OpAMD64ROLQconst: return rewriteValueAMD64_OpAMD64ROLQconst(v) case OpAMD64ROLW: return rewriteValueAMD64_OpAMD64ROLW(v) case OpAMD64ROLWconst: return rewriteValueAMD64_OpAMD64ROLWconst(v) case OpAMD64RORB: return rewriteValueAMD64_OpAMD64RORB(v) case OpAMD64RORL: return rewriteValueAMD64_OpAMD64RORL(v) case OpAMD64RORQ: return rewriteValueAMD64_OpAMD64RORQ(v) case OpAMD64RORW: return rewriteValueAMD64_OpAMD64RORW(v) case OpAMD64SARB: return rewriteValueAMD64_OpAMD64SARB(v) case OpAMD64SARBconst: return rewriteValueAMD64_OpAMD64SARBconst(v) case OpAMD64SARL: return rewriteValueAMD64_OpAMD64SARL(v) case OpAMD64SARLconst: return rewriteValueAMD64_OpAMD64SARLconst(v) case OpAMD64SARQ: return rewriteValueAMD64_OpAMD64SARQ(v) case OpAMD64SARQconst: return rewriteValueAMD64_OpAMD64SARQconst(v) case OpAMD64SARW: return rewriteValueAMD64_OpAMD64SARW(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst(v) case OpAMD64SARXL: return rewriteValueAMD64_OpAMD64SARXL(v) case OpAMD64SARXQ: return rewriteValueAMD64_OpAMD64SARXQ(v) case OpAMD64SBBLcarrymask: return rewriteValueAMD64_OpAMD64SBBLcarrymask(v) case OpAMD64SBBQ: return rewriteValueAMD64_OpAMD64SBBQ(v) case OpAMD64SBBQcarrymask: return rewriteValueAMD64_OpAMD64SBBQcarrymask(v) case OpAMD64SBBQconst: return rewriteValueAMD64_OpAMD64SBBQconst(v) case OpAMD64SETA: return rewriteValueAMD64_OpAMD64SETA(v) case OpAMD64SETAE: return rewriteValueAMD64_OpAMD64SETAE(v) case OpAMD64SETAEstore: return rewriteValueAMD64_OpAMD64SETAEstore(v) case OpAMD64SETAstore: return rewriteValueAMD64_OpAMD64SETAstore(v) case OpAMD64SETB: return rewriteValueAMD64_OpAMD64SETB(v) case OpAMD64SETBE: return rewriteValueAMD64_OpAMD64SETBE(v) case OpAMD64SETBEstore: return rewriteValueAMD64_OpAMD64SETBEstore(v) case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore(v) case OpAMD64SETEQ: return rewriteValueAMD64_OpAMD64SETEQ(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore(v) case OpAMD64SETG: return rewriteValueAMD64_OpAMD64SETG(v) case OpAMD64SETGE: return rewriteValueAMD64_OpAMD64SETGE(v) case OpAMD64SETGEstore: return rewriteValueAMD64_OpAMD64SETGEstore(v) case OpAMD64SETGstore: return rewriteValueAMD64_OpAMD64SETGstore(v) case OpAMD64SETL: return rewriteValueAMD64_OpAMD64SETL(v) case OpAMD64SETLE: return rewriteValueAMD64_OpAMD64SETLE(v) case OpAMD64SETLEstore: return rewriteValueAMD64_OpAMD64SETLEstore(v) case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore(v) case OpAMD64SETNE: return rewriteValueAMD64_OpAMD64SETNE(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore(v) case OpAMD64SHLL: return rewriteValueAMD64_OpAMD64SHLL(v) case OpAMD64SHLLconst: return rewriteValueAMD64_OpAMD64SHLLconst(v) case OpAMD64SHLQ: return rewriteValueAMD64_OpAMD64SHLQ(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB(v) case OpAMD64SHRBconst: return rewriteValueAMD64_OpAMD64SHRBconst(v) case OpAMD64SHRL: return rewriteValueAMD64_OpAMD64SHRL(v) case OpAMD64SHRLconst: return rewriteValueAMD64_OpAMD64SHRLconst(v) case OpAMD64SHRQ: return rewriteValueAMD64_OpAMD64SHRQ(v) case OpAMD64SHRQconst: return rewriteValueAMD64_OpAMD64SHRQconst(v) case OpAMD64SHRW: return rewriteValueAMD64_OpAMD64SHRW(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL(v) case OpAMD64SUBLconst: return rewriteValueAMD64_OpAMD64SUBLconst(v) case OpAMD64SUBLload: return rewriteValueAMD64_OpAMD64SUBLload(v) case OpAMD64SUBLmodify: return rewriteValueAMD64_OpAMD64SUBLmodify(v) case OpAMD64SUBQ: return rewriteValueAMD64_OpAMD64SUBQ(v) case OpAMD64SUBQborrow: return rewriteValueAMD64_OpAMD64SUBQborrow(v) case OpAMD64SUBQconst: return rewriteValueAMD64_OpAMD64SUBQconst(v) case OpAMD64SUBQload: return rewriteValueAMD64_OpAMD64SUBQload(v) case OpAMD64SUBQmodify: return rewriteValueAMD64_OpAMD64SUBQmodify(v) case OpAMD64SUBSD: return rewriteValueAMD64_OpAMD64SUBSD(v) case OpAMD64SUBSDload: return rewriteValueAMD64_OpAMD64SUBSDload(v) case OpAMD64SUBSS: return rewriteValueAMD64_OpAMD64SUBSS(v) case OpAMD64SUBSSload: return rewriteValueAMD64_OpAMD64SUBSSload(v) case OpAMD64TESTB: return rewriteValueAMD64_OpAMD64TESTB(v) case OpAMD64TESTBconst: return rewriteValueAMD64_OpAMD64TESTBconst(v) case OpAMD64TESTL: return rewriteValueAMD64_OpAMD64TESTL(v) case OpAMD64TESTLconst: return rewriteValueAMD64_OpAMD64TESTLconst(v) case OpAMD64TESTQ: return rewriteValueAMD64_OpAMD64TESTQ(v) case OpAMD64TESTQconst: return rewriteValueAMD64_OpAMD64TESTQconst(v) case OpAMD64TESTW: return rewriteValueAMD64_OpAMD64TESTW(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock(v) case OpAMD64XADDQlock: return rewriteValueAMD64_OpAMD64XADDQlock(v) case OpAMD64XCHGL: return rewriteValueAMD64_OpAMD64XCHGL(v) case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ(v) case OpAMD64XORL: return rewriteValueAMD64_OpAMD64XORL(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst(v) case OpAMD64XORLconstmodify: return rewriteValueAMD64_OpAMD64XORLconstmodify(v) case OpAMD64XORLload: return rewriteValueAMD64_OpAMD64XORLload(v) case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify(v) case OpAMD64XORQ: return rewriteValueAMD64_OpAMD64XORQ(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst(v) case OpAMD64XORQconstmodify: return rewriteValueAMD64_OpAMD64XORQconstmodify(v) case OpAMD64XORQload: return rewriteValueAMD64_OpAMD64XORQload(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify(v) case OpAdd16: v.Op = OpAMD64ADDL return true case OpAdd32: v.Op = OpAMD64ADDL return true case OpAdd32F: v.Op = OpAMD64ADDSS return true case OpAdd64: v.Op = OpAMD64ADDQ return true case OpAdd64F: v.Op = OpAMD64ADDSD return true case OpAdd8: v.Op = OpAMD64ADDL return true case OpAddPtr: v.Op = OpAMD64ADDQ return true case OpAddr: return rewriteValueAMD64_OpAddr(v) case OpAnd16: v.Op = OpAMD64ANDL return true case OpAnd32: v.Op = OpAMD64ANDL return true case OpAnd64: v.Op = OpAMD64ANDQ return true case OpAnd8: v.Op = OpAMD64ANDL return true case OpAndB: v.Op = OpAMD64ANDL return true case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32(v) case OpAtomicAdd64: return rewriteValueAMD64_OpAtomicAdd64(v) case OpAtomicAnd32: return rewriteValueAMD64_OpAtomicAnd32(v) case OpAtomicAnd8: return rewriteValueAMD64_OpAtomicAnd8(v) case OpAtomicCompareAndSwap32: return rewriteValueAMD64_OpAtomicCompareAndSwap32(v) case OpAtomicCompareAndSwap64: return rewriteValueAMD64_OpAtomicCompareAndSwap64(v) case OpAtomicExchange32: return rewriteValueAMD64_OpAtomicExchange32(v) case OpAtomicExchange64: return rewriteValueAMD64_OpAtomicExchange64(v) case OpAtomicLoad32: return rewriteValueAMD64_OpAtomicLoad32(v) case OpAtomicLoad64: return rewriteValueAMD64_OpAtomicLoad64(v) case OpAtomicLoad8: return rewriteValueAMD64_OpAtomicLoad8(v) case OpAtomicLoadPtr: return rewriteValueAMD64_OpAtomicLoadPtr(v) case OpAtomicOr32: return rewriteValueAMD64_OpAtomicOr32(v) case OpAtomicOr8: return rewriteValueAMD64_OpAtomicOr8(v) case OpAtomicStore32: return rewriteValueAMD64_OpAtomicStore32(v) case OpAtomicStore64: return rewriteValueAMD64_OpAtomicStore64(v) case OpAtomicStore8: return rewriteValueAMD64_OpAtomicStore8(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB(v) case OpAvg64u: v.Op = OpAMD64AVGQU return true case OpBitLen16: return rewriteValueAMD64_OpBitLen16(v) case OpBitLen32: return rewriteValueAMD64_OpBitLen32(v) case OpBitLen64: return rewriteValueAMD64_OpBitLen64(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8(v) case OpBswap32: v.Op = OpAMD64BSWAPL return true case OpBswap64: v.Op = OpAMD64BSWAPQ return true case OpCeil: return rewriteValueAMD64_OpCeil(v) case OpClosureCall: v.Op = OpAMD64CALLclosure return true case OpCom16: v.Op = OpAMD64NOTL return true case OpCom32: v.Op = OpAMD64NOTL return true case OpCom64: v.Op = OpAMD64NOTQ return true case OpCom8: v.Op = OpAMD64NOTL return true case OpCondSelect: return rewriteValueAMD64_OpCondSelect(v) case OpConst16: return rewriteValueAMD64_OpConst16(v) case OpConst32: v.Op = OpAMD64MOVLconst return true case OpConst32F: v.Op = OpAMD64MOVSSconst return true case OpConst64: v.Op = OpAMD64MOVQconst return true case OpConst64F: v.Op = OpAMD64MOVSDconst return true case OpConst8: return rewriteValueAMD64_OpConst8(v) case OpConstBool: return rewriteValueAMD64_OpConstBool(v) case OpConstNil: return rewriteValueAMD64_OpConstNil(v) case OpCtz16: return rewriteValueAMD64_OpCtz16(v) case OpCtz16NonZero: return rewriteValueAMD64_OpCtz16NonZero(v) case OpCtz32: return rewriteValueAMD64_OpCtz32(v) case OpCtz32NonZero: return rewriteValueAMD64_OpCtz32NonZero(v) case OpCtz64: return rewriteValueAMD64_OpCtz64(v) case OpCtz64NonZero: return rewriteValueAMD64_OpCtz64NonZero(v) case OpCtz8: return rewriteValueAMD64_OpCtz8(v) case OpCtz8NonZero: return rewriteValueAMD64_OpCtz8NonZero(v) case OpCvt32Fto32: v.Op = OpAMD64CVTTSS2SL return true case OpCvt32Fto64: v.Op = OpAMD64CVTTSS2SQ return true case OpCvt32Fto64F: v.Op = OpAMD64CVTSS2SD return true case OpCvt32to32F: v.Op = OpAMD64CVTSL2SS return true case OpCvt32to64F: v.Op = OpAMD64CVTSL2SD return true case OpCvt64Fto32: v.Op = OpAMD64CVTTSD2SL return true case OpCvt64Fto32F: v.Op = OpAMD64CVTSD2SS return true case OpCvt64Fto64: v.Op = OpAMD64CVTTSD2SQ return true case OpCvt64to32F: v.Op = OpAMD64CVTSQ2SS return true case OpCvt64to64F: v.Op = OpAMD64CVTSQ2SD return true case OpCvtBoolToUint8: v.Op = OpCopy return true case OpDiv128u: v.Op = OpAMD64DIVQU2 return true case OpDiv16: return rewriteValueAMD64_OpDiv16(v) case OpDiv16u: return rewriteValueAMD64_OpDiv16u(v) case OpDiv32: return rewriteValueAMD64_OpDiv32(v) case OpDiv32F: v.Op = OpAMD64DIVSS return true case OpDiv32u: return rewriteValueAMD64_OpDiv32u(v) case OpDiv64: return rewriteValueAMD64_OpDiv64(v) case OpDiv64F: v.Op = OpAMD64DIVSD return true case OpDiv64u: return rewriteValueAMD64_OpDiv64u(v) case OpDiv8: return rewriteValueAMD64_OpDiv8(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u(v) case OpEq16: return rewriteValueAMD64_OpEq16(v) case OpEq32: return rewriteValueAMD64_OpEq32(v) case OpEq32F: return rewriteValueAMD64_OpEq32F(v) case OpEq64: return rewriteValueAMD64_OpEq64(v) case OpEq64F: return rewriteValueAMD64_OpEq64F(v) case OpEq8: return rewriteValueAMD64_OpEq8(v) case OpEqB: return rewriteValueAMD64_OpEqB(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr(v) case OpFMA: return rewriteValueAMD64_OpFMA(v) case OpFloor: return rewriteValueAMD64_OpFloor(v) case OpGetCallerPC: v.Op = OpAMD64LoweredGetCallerPC return true case OpGetCallerSP: v.Op = OpAMD64LoweredGetCallerSP return true case OpGetClosurePtr: v.Op = OpAMD64LoweredGetClosurePtr return true case OpGetG: return rewriteValueAMD64_OpGetG(v) case OpHasCPUFeature: return rewriteValueAMD64_OpHasCPUFeature(v) case OpHmul32: v.Op = OpAMD64HMULL return true case OpHmul32u: v.Op = OpAMD64HMULLU return true case OpHmul64: v.Op = OpAMD64HMULQ return true case OpHmul64u: v.Op = OpAMD64HMULQU return true case OpInterCall: v.Op = OpAMD64CALLinter return true case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueAMD64_OpIsSliceInBounds(v) case OpLeq16: return rewriteValueAMD64_OpLeq16(v) case OpLeq16U: return rewriteValueAMD64_OpLeq16U(v) case OpLeq32: return rewriteValueAMD64_OpLeq32(v) case OpLeq32F: return rewriteValueAMD64_OpLeq32F(v) case OpLeq32U: return rewriteValueAMD64_OpLeq32U(v) case OpLeq64: return rewriteValueAMD64_OpLeq64(v) case OpLeq64F: return rewriteValueAMD64_OpLeq64F(v) case OpLeq64U: return rewriteValueAMD64_OpLeq64U(v) case OpLeq8: return rewriteValueAMD64_OpLeq8(v) case OpLeq8U: return rewriteValueAMD64_OpLeq8U(v) case OpLess16: return rewriteValueAMD64_OpLess16(v) case OpLess16U: return rewriteValueAMD64_OpLess16U(v) case OpLess32: return rewriteValueAMD64_OpLess32(v) case OpLess32F: return rewriteValueAMD64_OpLess32F(v) case OpLess32U: return rewriteValueAMD64_OpLess32U(v) case OpLess64: return rewriteValueAMD64_OpLess64(v) case OpLess64F: return rewriteValueAMD64_OpLess64F(v) case OpLess64U: return rewriteValueAMD64_OpLess64U(v) case OpLess8: return rewriteValueAMD64_OpLess8(v) case OpLess8U: return rewriteValueAMD64_OpLess8U(v) case OpLoad: return rewriteValueAMD64_OpLoad(v) case OpLocalAddr: return rewriteValueAMD64_OpLocalAddr(v) case OpLsh16x16: return rewriteValueAMD64_OpLsh16x16(v) case OpLsh16x32: return rewriteValueAMD64_OpLsh16x32(v) case OpLsh16x64: return rewriteValueAMD64_OpLsh16x64(v) case OpLsh16x8: return rewriteValueAMD64_OpLsh16x8(v) case OpLsh32x16: return rewriteValueAMD64_OpLsh32x16(v) case OpLsh32x32: return rewriteValueAMD64_OpLsh32x32(v) case OpLsh32x64: return rewriteValueAMD64_OpLsh32x64(v) case OpLsh32x8: return rewriteValueAMD64_OpLsh32x8(v) case OpLsh64x16: return rewriteValueAMD64_OpLsh64x16(v) case OpLsh64x32: return rewriteValueAMD64_OpLsh64x32(v) case OpLsh64x64: return rewriteValueAMD64_OpLsh64x64(v) case OpLsh64x8: return rewriteValueAMD64_OpLsh64x8(v) case OpLsh8x16: return rewriteValueAMD64_OpLsh8x16(v) case OpLsh8x32: return rewriteValueAMD64_OpLsh8x32(v) case OpLsh8x64: return rewriteValueAMD64_OpLsh8x64(v) case OpLsh8x8: return rewriteValueAMD64_OpLsh8x8(v) case OpMod16: return rewriteValueAMD64_OpMod16(v) case OpMod16u: return rewriteValueAMD64_OpMod16u(v) case OpMod32: return rewriteValueAMD64_OpMod32(v) case OpMod32u: return rewriteValueAMD64_OpMod32u(v) case OpMod64: return rewriteValueAMD64_OpMod64(v) case OpMod64u: return rewriteValueAMD64_OpMod64u(v) case OpMod8: return rewriteValueAMD64_OpMod8(v) case OpMod8u: return rewriteValueAMD64_OpMod8u(v) case OpMove: return rewriteValueAMD64_OpMove(v) case OpMul16: v.Op = OpAMD64MULL return true case OpMul32: v.Op = OpAMD64MULL return true case OpMul32F: v.Op = OpAMD64MULSS return true case OpMul64: v.Op = OpAMD64MULQ return true case OpMul64F: v.Op = OpAMD64MULSD return true case OpMul64uhilo: v.Op = OpAMD64MULQU2 return true case OpMul8: v.Op = OpAMD64MULL return true case OpNeg16: v.Op = OpAMD64NEGL return true case OpNeg32: v.Op = OpAMD64NEGL return true case OpNeg32F: return rewriteValueAMD64_OpNeg32F(v) case OpNeg64: v.Op = OpAMD64NEGQ return true case OpNeg64F: return rewriteValueAMD64_OpNeg64F(v) case OpNeg8: v.Op = OpAMD64NEGL return true case OpNeq16: return rewriteValueAMD64_OpNeq16(v) case OpNeq32: return rewriteValueAMD64_OpNeq32(v) case OpNeq32F: return rewriteValueAMD64_OpNeq32F(v) case OpNeq64: return rewriteValueAMD64_OpNeq64(v) case OpNeq64F: return rewriteValueAMD64_OpNeq64F(v) case OpNeq8: return rewriteValueAMD64_OpNeq8(v) case OpNeqB: return rewriteValueAMD64_OpNeqB(v) case OpNeqPtr: return rewriteValueAMD64_OpNeqPtr(v) case OpNilCheck: v.Op = OpAMD64LoweredNilCheck return true case OpNot: return rewriteValueAMD64_OpNot(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr(v) case OpOr16: v.Op = OpAMD64ORL return true case OpOr32: v.Op = OpAMD64ORL return true case OpOr64: v.Op = OpAMD64ORQ return true case OpOr8: v.Op = OpAMD64ORL return true case OpOrB: v.Op = OpAMD64ORL return true case OpPanicBounds: return rewriteValueAMD64_OpPanicBounds(v) case OpPopCount16: return rewriteValueAMD64_OpPopCount16(v) case OpPopCount32: v.Op = OpAMD64POPCNTL return true case OpPopCount64: v.Op = OpAMD64POPCNTQ return true case OpPopCount8: return rewriteValueAMD64_OpPopCount8(v) case OpPrefetchCache: v.Op = OpAMD64PrefetchT0 return true case OpPrefetchCacheStreamed: v.Op = OpAMD64PrefetchNTA return true case OpRotateLeft16: v.Op = OpAMD64ROLW return true case OpRotateLeft32: v.Op = OpAMD64ROLL return true case OpRotateLeft64: v.Op = OpAMD64ROLQ return true case OpRotateLeft8: v.Op = OpAMD64ROLB return true case OpRound32F: v.Op = OpCopy return true case OpRound64F: v.Op = OpCopy return true case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven(v) case OpRsh16Ux16: return rewriteValueAMD64_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValueAMD64_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValueAMD64_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValueAMD64_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValueAMD64_OpRsh16x16(v) case OpRsh16x32: return rewriteValueAMD64_OpRsh16x32(v) case OpRsh16x64: return rewriteValueAMD64_OpRsh16x64(v) case OpRsh16x8: return rewriteValueAMD64_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValueAMD64_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValueAMD64_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValueAMD64_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValueAMD64_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValueAMD64_OpRsh32x16(v) case OpRsh32x32: return rewriteValueAMD64_OpRsh32x32(v) case OpRsh32x64: return rewriteValueAMD64_OpRsh32x64(v) case OpRsh32x8: return rewriteValueAMD64_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValueAMD64_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValueAMD64_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValueAMD64_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValueAMD64_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValueAMD64_OpRsh64x16(v) case OpRsh64x32: return rewriteValueAMD64_OpRsh64x32(v) case OpRsh64x64: return rewriteValueAMD64_OpRsh64x64(v) case OpRsh64x8: return rewriteValueAMD64_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValueAMD64_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValueAMD64_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValueAMD64_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValueAMD64_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValueAMD64_OpRsh8x16(v) case OpRsh8x32: return rewriteValueAMD64_OpRsh8x32(v) case OpRsh8x64: return rewriteValueAMD64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8(v) case OpSelect0: return rewriteValueAMD64_OpSelect0(v) case OpSelect1: return rewriteValueAMD64_OpSelect1(v) case OpSelectN: return rewriteValueAMD64_OpSelectN(v) case OpSignExt16to32: v.Op = OpAMD64MOVWQSX return true case OpSignExt16to64: v.Op = OpAMD64MOVWQSX return true case OpSignExt32to64: v.Op = OpAMD64MOVLQSX return true case OpSignExt8to16: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to32: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to64: v.Op = OpAMD64MOVBQSX return true case OpSlicemask: return rewriteValueAMD64_OpSlicemask(v) case OpSpectreIndex: return rewriteValueAMD64_OpSpectreIndex(v) case OpSpectreSliceIndex: return rewriteValueAMD64_OpSpectreSliceIndex(v) case OpSqrt: v.Op = OpAMD64SQRTSD return true case OpSqrt32: v.Op = OpAMD64SQRTSS return true case OpStaticCall: v.Op = OpAMD64CALLstatic return true case OpStore: return rewriteValueAMD64_OpStore(v) case OpSub16: v.Op = OpAMD64SUBL return true case OpSub32: v.Op = OpAMD64SUBL return true case OpSub32F: v.Op = OpAMD64SUBSS return true case OpSub64: v.Op = OpAMD64SUBQ return true case OpSub64F: v.Op = OpAMD64SUBSD return true case OpSub8: v.Op = OpAMD64SUBL return true case OpSubPtr: v.Op = OpAMD64SUBQ return true case OpTailCall: v.Op = OpAMD64CALLtail return true case OpTrunc: return rewriteValueAMD64_OpTrunc(v) case OpTrunc16to8: v.Op = OpCopy return true case OpTrunc32to16: v.Op = OpCopy return true case OpTrunc32to8: v.Op = OpCopy return true case OpTrunc64to16: v.Op = OpCopy return true case OpTrunc64to32: v.Op = OpCopy return true case OpTrunc64to8: v.Op = OpCopy return true case OpWB: v.Op = OpAMD64LoweredWB return true case OpXor16: v.Op = OpAMD64XORL return true case OpXor32: v.Op = OpAMD64XORL return true case OpXor64: v.Op = OpAMD64XORQ return true case OpXor8: v.Op = OpAMD64XORL return true case OpZero: return rewriteValueAMD64_OpZero(v) case OpZeroExt16to32: v.Op = OpAMD64MOVWQZX return true case OpZeroExt16to64: v.Op = OpAMD64MOVWQZX return true case OpZeroExt32to64: v.Op = OpAMD64MOVLQZX return true case OpZeroExt8to16: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to32: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to64: v.Op = OpAMD64MOVBQZX return true } return false } func rewriteValueAMD64_OpAMD64ADCQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) // result: (ADCQconst x [int32(c)] carry) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) carry := v_2 if !(is32Bit(c)) { continue } v.reset(OpAMD64ADCQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, carry) return true } break } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQcarry) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64ADCQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQconst x [c] (FlagEQ)) // result: (ADDQconstcarry x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDL x (MOVLconst [c])) // result: (ADDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRLconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRWconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRBconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAL2) v.AddArg2(y, x) return true } } break } // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAL { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL { continue } y := v_1.Args[0] v.reset(OpAMD64SUBL) v.AddArg2(x, y) return true } break } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDLconst [c] (ADDL x y)) // result: (LEAL1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (SHLLconst [1] x)) // result: (LEAL1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // result: (MOVLconst [c+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c + d) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // result: (ADDLconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDLconst [off] x:(SP)) // result: (LEAL [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (ADDL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ADDQ x (MOVLconst [c])) // result: (ADDQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRQconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAQ2) v.AddArg2(y, x) return true } } break } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ { continue } y := v_1.Args[0] v.reset(OpAMD64SUBQ) v.AddArg2(x, y) return true } break } // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQcarry(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQcarry x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconstcarry x [int32(c)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDQconst [c] (ADDQ x y)) // result: (LEAQ1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (SHLQconst [1] x)) // result: (LEAQ1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDQconst [c] (LEAQ [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ADDQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) + d) return true } // match: (ADDQconst [c] (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (ADDQconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDQconst [off] x:(SP)) // result: (LEAQ [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (ADDQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (ADDSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (ADDSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ANDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTRL) v.AddArg2(x, y) return true } break } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } break } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ANDL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDL x (NOTL y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTL { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNL) v.AddArg2(x, y) return true } break } // match: (ANDL x (NEGL x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIL) v.AddArg(x) return true } break } // match: (ANDL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSRL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSRL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDLconst [c] x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDLconst [c] (BTRLconst [d] x)) // result: (ANDLconst [c &^ (1<= 128 // result: (BTRQconst [int8(log64(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log64(^c))) v.AddArg(x) return true } break } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ANDQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDQ x (NOTQ y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTQ { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNQ) v.AddArg2(x, y) return true } break } // match: (ANDQ x (NEGQ x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIQ) v.AddArg(x) return true } break } // match: (ANDQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSRQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSRQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDQconst [c] x) // cond: isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRQconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDQconst [c] (ANDQconst [d] x)) // result: (ANDQconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDQconst [c] (BTRQconst [d] x)) // cond: is32Bit(int64(c) &^ (1< [1<<8] (MOVBQZX x))) // result: (BSFQ (ORQconst [1<<8] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVBQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 8) v0.AddArg(x) v.AddArg(v0) return true } // match: (BSFQ (ORQconst [1<<16] (MOVWQZX x))) // result: (BSFQ (ORQconst [1<<16] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVWQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPL(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPL (BSWAPL p)) // result: p for { if v_0.Op != OpAMD64BSWAPL { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPL x:(MOVLload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPL (MOVBELload [i] {s} p m)) // result: (MOVLload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBELload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPQ(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPQ (BSWAPQ p)) // result: p for { if v_0.Op != OpAMD64BSWAPQ { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPQ x:(MOVQload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPQ (MOVBEQload [i] {s} p m)) // result: (MOVQload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBEQload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BTCLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTCLconst [c] (XORLconst [d] x)) // result: (XORLconst [d ^ 1<d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 32) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTLconst [c] (SHLLconst [d] x)) // cond: c>d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTQconst(v *Value) bool { v_0 := v.Args[0] // match: (BTQconst [c] (SHRQconst [d] x)) // cond: (c+d)<64 // result: (BTQconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 64) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTQconst [c] (SHLQconst [d] x)) // cond: c>d // result: (BTQconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTQconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTRLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTRLconst [c] (BTSLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTSLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (BTCLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTCLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [d &^ (1<uint8(y) // result: (FlagLT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) < y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x) y && uint8(x) < uint8(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) > y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int8(m) && int8(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPBconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTB x y) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, y) return true } // match: (CMPBconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTBconst [int8(c)] x) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt8(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVBload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPBload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPL x (MOVLconst [c])) // result: (CMPLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64CMPLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // result: (InvertFlags (CMPLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPL y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x==y // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x == y) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: xuint32(y) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x < y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x) y && uint32(x) < uint32(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x > y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) // result: (FlagLT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x < y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x)>uint64(y) // result: (FlagGT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x > y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQ l:(MOVQload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPQload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPQ x l:(MOVQload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPQload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPQload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPQconst (NEGQ (ADDQconst [-16] (ANDQconst [15] _))) [32]) // result: (FlagLT_ULT) for { if auxIntToInt32(v.AuxInt) != 32 || v_0.Op != OpAMD64NEGQ { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_0_0.AuxInt) != -16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_0_0.AuxInt) != 15 { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (NEGQ (ADDQconst [ -8] (ANDQconst [7] _))) [32]) // result: (FlagLT_ULT) for { if auxIntToInt32(v.AuxInt) != 32 || v_0.Op != OpAMD64NEGQ { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_0_0.AuxInt) != -8 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_0_0.AuxInt) != 7 { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x==int64(y) // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x == int64(y)) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: xuint64(int64(y)) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x < int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x) int64(y) && uint64(x) < uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x)>uint64(int64(y)) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x > int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQconst (MOVBQZX _) [c]) // cond: 0xFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVWQZX _) [c]) // cond: 0xFFFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (SHRQconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 64 && (1<uint16(y) // result: (FlagLT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) < y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x) y && uint16(x) < uint16(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) > y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int16(m) && int16(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPWconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTW x y) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, y) return true } // match: (CMPWconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTWconst [int16(c)] x) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt16(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVWload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPWload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGLlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGQlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64HMULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULL x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULL y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULLU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULLU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULLU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULLU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQ x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQ y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64LEAL(v *Value) bool { v_0 := v.Args[0] // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { v_0 := v.Args[0] // match: (LEAQ [c] {s} (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAQ [c] {s} (ADDQ x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg(x) return true } // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ2 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ4 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ8 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64LEAQ { continue } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(y, x) return true } } break } // match: (LEAQ1 [0] x y) // cond: v.Aux == nil // result: (ADDQ x y) for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 y := v_1 if !(v.Aux == nil) { break } v.reset(OpAMD64ADDQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAQ2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil // result: (LEAQ4 [off1+2*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + 2*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ2 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ2 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAQ4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil // result: (LEAQ8 [off1+4*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + 4*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ4 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ4 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAQ8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ8 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ8 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBELstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBELstore [i] {s} p (BSWAPL x) m) // result: (MOVLstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPL { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEQstore [i] {s} p (BSWAPQ x) m) // result: (MOVQstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPQ { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7f) v.AddArg(x) return true } // match: (MOVBQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x) // cond: zeroUpper56Bits(x,3) // result: x for { x := v_0 if !(zeroUpper56Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVBQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xff) v.AddArg(x) return true } // match: (MOVBQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read8(sym, int64(off)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read8(sym, int64(off)))) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) // cond: y.Uses == 1 // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETL { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) // cond: y.Uses == 1 // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETLE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) // cond: y.Uses == 1 // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETG { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) // cond: y.Uses == 1 // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETGE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) // cond: y.Uses == 1 // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETEQ { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) // cond: y.Uses == 1 // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETNE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) // cond: y.Uses == 1 // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETB { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) // cond: y.Uses == 1 // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETBE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) // cond: y.Uses == 1 // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETA { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) // cond: y.Uses == 1 // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETAE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstore [i-1] {s} p (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p1 w x0:(MOVBstore [i] {s} p0 (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0) // result: (MOVWstore [i] {s} p0 (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-1 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-3 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 3) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p3 w x2:(MOVBstore [i] {s} p2 (SHRLconst [8] w) x1:(MOVBstore [i] {s} p1 (SHRLconst [16] w) x0:(MOVBstore [i] {s} p0 (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2) // result: (MOVLstore [i] {s} p0 (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p3 := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i-1 || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] if p != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i-2 || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i-3 || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i-4 || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-5 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-6 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-7 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 7) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p7 w x6:(MOVBstore [i] {s} p6 (SHRQconst [8] w) x5:(MOVBstore [i] {s} p5 (SHRQconst [16] w) x4:(MOVBstore [i] {s} p4 (SHRQconst [24] w) x3:(MOVBstore [i] {s} p3 (SHRQconst [32] w) x2:(MOVBstore [i] {s} p2 (SHRQconst [40] w) x1:(MOVBstore [i] {s} p1 (SHRQconst [48] w) x0:(MOVBstore [i] {s} p0 (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i] {s} p0 (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p7 := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] p6 := x6.Args[0] x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] p5 := x5.Args[0] x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] p4 := x4.Args[0] x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] p3 := x3.Args[0] x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRWconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [7] {s} p1 (SHRQconst [56] w) x1:(MOVWstore [5] {s} p1 (SHRQconst [40] w) x2:(MOVLstore [1] {s} p1 (SHRQconst [8] w) x3:(MOVBstore [0] {s} p1 w mem)))) // cond: x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && clobber(x1, x2, x3) // result: (MOVQstore {s} p1 w mem) for { if auxIntToInt32(v.AuxInt) != 7 { break } s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 56 { break } w := v_1.Args[0] x1 := v_2 if x1.Op != OpAMD64MOVWstore || auxIntToInt32(x1.AuxInt) != 5 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p1 != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 40 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpAMD64MOVLstore || auxIntToInt32(x2.AuxInt) != 1 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p1 != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != 0 || auxToSym(x3.Aux) != s { break } mem := x3.Args[2] if p1 != x3.Args[0] || w != x3.Args[1] || !(x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && clobber(x1, x2, x3)) { break } v.reset(OpAMD64MOVQstore) v.Aux = symToAux(s) v.AddArg3(p1, w, mem) return true } // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVBload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVBstore || auxIntToInt32(mem2.AuxInt) != i-1 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVBload || auxIntToInt32(x2.AuxInt) != j-1 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(j - 1) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && a.Off() + 1 == c.Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && a.Off()+1 == c.Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (MOVBstoreconst [a] {s} p x:(MOVBstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && a.Off() + 1 == c.Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && a.Off()+1 == c.Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX (ANDLconst [c] x)) // cond: uint32(c) & 0x80000000 == 0 // result: (ANDLconst [c & 0x7fffffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(uint32(c)&0x80000000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fffffff) v.AddArg(x) return true } // match: (MOVLQSX (MOVLQSX x)) // result: (MOVLQSX x) for { if v_0.Op != OpAMD64MOVLQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x) // cond: zeroUpper32Bits(x,3) // result: x for { x := v_0 if !(zeroUpper32Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVLQZX (ANDLconst [c] x)) // result: (ANDLconst [c] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (MOVLQZX (MOVLQZX x)) // result: (MOVLQZX x) for { if v_0.Op != OpAMD64MOVLQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLf2i) v.AddArg(val) return true } // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [32] w) x:(MOVLstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [j] w) x:(MOVLstore [i] {s} p0 w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVLload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVLstore || auxIntToInt32(mem2.AuxInt) != i-4 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVLload || auxIntToInt32(x2.AuxInt) != j-4 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(j - 4) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) // result: (MOVSSstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [i] {s} p x:(BSWAPL w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPL { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [c] {s} p x:(MOVLstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && a.Off() + 4 == c.Off() && clobber(x) // result: (MOVQstore [a.Off()] {s} p (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && a.Off()+4 == c.Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p, v0, mem) return true } // match: (MOVLstoreconst [a] {s} p x:(MOVLstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && a.Off() + 4 == c.Off() && clobber(x) // result: (MOVQstore [a.Off()] {s} p (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && a.Off()+4 == c.Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) // cond: symIsRO(srcSym) // result: (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))]) (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))]) mem)) for { dstOff := auxIntToInt32(v.AuxInt) dstSym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVOload { break } srcOff := auxIntToInt32(v_1.AuxInt) srcSym := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } mem := v_2 if !(symIsRO(srcSym)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(dstOff + 8) v.Aux = symToAux(dstSym) v0 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))) v1 := b.NewValue0(v_1.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AuxInt = int32ToAuxInt(dstOff) v1.Aux = symToAux(dstSym) v2 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))) v1.AddArg3(ptr, v2, mem) v.AddArg3(ptr, v0, v1) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVOstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.copyOf(x) return true } // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) // result: (MOVQf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQf2i) v.AddArg(val) return true } // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validVal(c) // result: (MOVQstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(validVal(c)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) // result: (MOVSDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [i] {s} p x:(BSWAPQ w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPQ { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [c] {s} p x:(MOVQstoreconst [a] {s} p mem)) // cond: config.useSSE && x.Uses == 1 && a.Off() + 8 == c.Off() && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(config.useSSE && x.Uses == 1 && a.Off()+8 == c.Off() && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (MOVQstoreconst [a] {s} p x:(MOVQstoreconst [c] {s} p mem)) // cond: config.useSSE && x.Uses == 1 && a.Off() + 8 == c.Off() && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(config.useSSE && x.Uses == 1 && a.Off()+8 == c.Off() && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fff) v.AddArg(x) return true } // match: (MOVWQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x) // cond: zeroUpper48Bits(x,3) // result: x for { x := v_0 if !(zeroUpper48Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVWQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xffff) v.AddArg(x) return true } // match: (MOVWQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVWload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVWstore || auxIntToInt32(mem2.AuxInt) != i-2 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVWload || auxIntToInt32(x2.AuxInt) != j-2 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(j - 2) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && a.Off() + 2 == c.Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && a.Off()+2 == c.Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (MOVWstoreconst [a] {s} p x:(MOVWstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && a.Off() + 2 == c.Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && a.Off()+2 == c.Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } return false } func rewriteValueAMD64_OpAMD64MULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULL x (MOVLconst [c])) // result: (MULLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULLconst [c] (MULLconst [d] x)) // result: (MULLconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULLconst [-9] x) // result: (NEGL (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // result: (NEGL (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // result: (NEGL (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // result: (NEGL x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGL) v.AddArg(x) return true } // match: (MULLconst [ 0] _) // result: (MOVLconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (MULLconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULLconst [ 3] x) // result: (LEAL2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAL2) v.AddArg2(x, x) return true } // match: (MULLconst [ 5] x) // result: (LEAL4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAL4) v.AddArg2(x, x) return true } // match: (MULLconst [ 7] x) // result: (LEAL2 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [ 9] x) // result: (LEAL8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAL8) v.AddArg2(x, x) return true } // match: (MULLconst [11] x) // result: (LEAL2 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [13] x) // result: (LEAL4 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [19] x) // result: (LEAL2 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [21] x) // result: (LEAL4 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [25] x) // result: (LEAL8 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [27] x) // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [37] x) // result: (LEAL4 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [41] x) // result: (LEAL8 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [45] x) // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [73] x) // result: (LEAL8 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [81] x) // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBL (SHLLconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAL1) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLLconst [int8(log32(c/3))] (LEAL2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLLconst [int8(log32(c/5))] (LEAL4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLLconst [int8(log32(c/9))] (LEAL8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] (MOVLconst [d])) // result: (MOVLconst [c*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c * d) return true } return false } func rewriteValueAMD64_OpAMD64MULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (MULQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULQconst [c] (MULQconst [d] x)) // cond: is32Bit(int64(c)*int64(d)) // result: (MULQconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) * int64(d))) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULQconst [-9] x) // result: (NEGQ (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-5] x) // result: (NEGQ (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-3] x) // result: (NEGQ (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-1] x) // result: (NEGQ x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGQ) v.AddArg(x) return true } // match: (MULQconst [ 0] _) // result: (MOVQconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MULQconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULQconst [ 3] x) // result: (LEAQ2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAQ2) v.AddArg2(x, x) return true } // match: (MULQconst [ 5] x) // result: (LEAQ4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAQ4) v.AddArg2(x, x) return true } // match: (MULQconst [ 7] x) // result: (LEAQ2 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [ 9] x) // result: (LEAQ8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAQ8) v.AddArg2(x, x) return true } // match: (MULQconst [11] x) // result: (LEAQ2 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [13] x) // result: (LEAQ4 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [19] x) // result: (LEAQ2 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [21] x) // result: (LEAQ4 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [25] x) // result: (LEAQ8 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [27] x) // result: (LEAQ8 (LEAQ2 x x) (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [37] x) // result: (LEAQ4 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [41] x) // result: (LEAQ8 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [45] x) // result: (LEAQ8 (LEAQ4 x x) (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [73] x) // result: (LEAQ8 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [81] x) // result: (LEAQ8 (LEAQ8 x x) (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBQ (SHLQconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAQ1 (SHLQconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAQ1) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAQ2 (SHLQconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAQ4 (SHLQconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAQ8 (SHLQconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLQconst [int8(log32(c/3))] (LEAQ2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLQconst [int8(log32(c/5))] (LEAQ4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLQconst [int8(log32(c/9))] (LEAQ8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) * d) return true } // match: (MULQconst [c] (NEGQ x)) // cond: c != -(1<<31) // result: (MULQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (MULSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64MULSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (MULSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64NEGL(v *Value) bool { v_0 := v.Args[0] // match: (NEGL (NEGL x)) // result: x for { if v_0.Op != OpAMD64NEGL { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGL s:(SUBL x y)) // cond: s.Uses == 1 // result: (SUBL y x) for { s := v_0 if s.Op != OpAMD64SUBL { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBL) v.AddArg2(y, x) return true } // match: (NEGL (MOVLconst [c])) // result: (MOVLconst [-c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-c) return true } return false } func rewriteValueAMD64_OpAMD64NEGQ(v *Value) bool { v_0 := v.Args[0] // match: (NEGQ (NEGQ x)) // result: x for { if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGQ s:(SUBQ x y)) // cond: s.Uses == 1 // result: (SUBQ y x) for { s := v_0 if s.Op != OpAMD64SUBQ { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBQ) v.AddArg2(y, x) return true } // match: (NEGQ (MOVQconst [c])) // result: (MOVQconst [-c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-c) return true } // match: (NEGQ (ADDQconst [c] (NEGQ x))) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { if v_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } x := v_0_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64NOTL(v *Value) bool { v_0 := v.Args[0] // match: (NOTL (MOVLconst [c])) // result: (MOVLconst [^c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64NOTQ(v *Value) bool { v_0 := v.Args[0] // match: (NOTQ (MOVQconst [c])) // result: (MOVQconst [^c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64ORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTSL) v.AddArg2(x, y) return true } break } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRLconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRWconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRBconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (RORL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (RORL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRW x (ANDQconst y [15])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg2(x, y) return true } break } // match: (ORL (SHRW x (ANDLconst y [15])) (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg2(x, y) return true } break } // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg2(x, y) return true } break } // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg2(x, y) return true } break } // match: (ORL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORL x0:(MOVBload [i0] {s} p mem) sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVBload [i] {s} p0 mem) sh:(SHLLconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVWload [i] {s} p0 mem) sh:(SHLLconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL x1:(MOVBload [i] {s} p1 mem) sh:(SHLLconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORLconst(v *Value) bool { v_0 := v.Args[0] // match: (ORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORLconst [c] (ORLconst [d] x)) // result: (ORLconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORLconst [c] (BTSLconst [d] x)) // result: (ORLconst [c | 1<= 128 // result: (BTSQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ORQ x (MOVLconst [c])) // result: (ORQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRQconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHRQ lo bits) (SHLQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLQ lo bits) (SHRQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (MOVQconst [c]) (MOVQconst [d])) // result: (MOVQconst [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c | d) return true } break } // match: (ORQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORQ x0:(MOVBload [i0] {s} p mem) sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBload [i] {s} p0 mem) sh:(SHLQconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVWload [i] {s} p0 mem) sh:(SHLQconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVLload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVLload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i] {s} p0 mem)) y)) // cond: j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ x1:(MOVBload [i] {s} p1 mem) sh:(SHLQconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i] {s} p1 mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem))) y)) // cond: j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ORQ x0:(MOVBELload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVBELload [i1] {s} p mem))) // cond: i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i1] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i1) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBELload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVBELload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i] {s} p1 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p1, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQconst(v *Value) bool { v_0 := v.Args[0] // match: (ORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORQconst [c] (ORQconst [d] x)) // result: (ORQconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORQconst [c] (BTSQconst [d] x)) // cond: is32Bit(int64(c) | 1<>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int8(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARL x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SARXL x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (MOVLconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SARLconst(v *Value) bool { v_0 := v.Args[0] // match: (SARLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARLconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int32(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int32(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SARXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (MOVLconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SARQconst(v *Value) bool { v_0 := v.Args[0] // match: (SARQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARQconst [c] (MOVQconst [d])) // result: (MOVQconst [d>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SARW x (MOVQconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } // match: (SARW x (MOVLconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SARWconst(v *Value) bool { v_0 := v.Args[0] // match: (SARWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARWconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int16(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int16(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARXL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARXL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARXL x (MOVLconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARXL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SARXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARXQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARXQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARXQ x (MOVLconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARXQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SARXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SBBLcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBLcarrymask (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagLT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagGT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQ x (MOVQconst [c]) borrow) // cond: is32Bit(c) // result: (SBBQconst x [int32(c)] borrow) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) borrow := v_2 if !(is32Bit(c)) { break } v.reset(OpAMD64SBBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, borrow) return true } // match: (SBBQ x y (FlagEQ)) // result: (SUBQborrow x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQborrow) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64SBBQcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBQcarrymask (FlagEQ)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagLT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagLT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagGT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagGT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQconst x [c] (FlagEQ)) // result: (SUBQconstborrow x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SETA(v *Value) bool { v_0 := v.Args[0] // match: (SETA (InvertFlags x)) // result: (SETB x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETA (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAE(v *Value) bool { v_0 := v.Args[0] // match: (SETAE (TESTQ x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTL x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTW x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTB x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (InvertFlags x)) // result: (SETBE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETAstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETB(v *Value) bool { v_0 := v.Args[0] // match: (SETB (TESTQ x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTL x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTW x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTB x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (BTLconst [0] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64BTLconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (BTQconst [0] x)) // result: (ANDQconst [1] x) for { if v_0.Op != OpAMD64BTQconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (InvertFlags x)) // result: (SETA x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBE(v *Value) bool { v_0 := v.Args[0] // match: (SETBE (InvertFlags x)) // result: (SETAE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETBE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAE (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAE (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETNE (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETEQ (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETEQstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETG(v *Value) bool { v_0 := v.Args[0] // match: (SETG (InvertFlags x)) // result: (SETL x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETG (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGE(v *Value) bool { v_0 := v.Args[0] // match: (SETGE (InvertFlags x)) // result: (SETLE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETL(v *Value) bool { v_0 := v.Args[0] // match: (SETL (InvertFlags x)) // result: (SETG x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLE(v *Value) bool { v_0 := v.Args[0] // match: (SETLE (InvertFlags x)) // result: (SETGE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETLE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNE(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETNE (TESTBconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTBconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTWconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTWconst || auxIntToInt16(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETB (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETB (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETEQ (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (InvertFlags x)) // result: (SETNE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETNE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETNEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (MOVLconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL l:(MOVLload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHLXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLLconst [1] (SHRLconst [1] x)) // result: (BTRLconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLLconst [d] (MOVLconst [c])) // result: (MOVLconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (MOVLconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ l:(MOVQload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHLXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLQconst [1] (SHRQconst [1] x)) // result: (BTRQconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLQconst [d] (MOVQconst [c])) // result: (MOVQconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c << uint64(d)) return true } // match: (SHLQconst [d] (MOVLconst [c])) // result: (MOVQconst [int64(c) << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHRB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRB x (MOVQconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB _ (MOVQconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRBconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRBconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (MOVLconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL l:(MOVLload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHRXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRLconst [1] (SHLLconst [1] x)) // result: (BTRLconst [31] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(31) v.AddArg(x) return true } // match: (SHRLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (MOVLconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ l:(MOVQload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHRXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRQconst [1] (SHLQconst [1] x)) // result: (BTRQconst [63] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(63) v.AddArg(x) return true } // match: (SHRQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRW x (MOVQconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW _ (MOVQconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRWconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBL x (MOVLconst [c])) // result: (SUBLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SUBLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // result: (NEGL (SUBLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBLconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (SUBLconst [c] x) // result: (ADDLconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } } func rewriteValueAMD64_OpAMD64SUBLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (SUBL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconst x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } // match: (SUBQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (NEGQ (SUBQconst x [int32(c)])) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBQload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQborrow(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQborrow x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconstborrow x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SUBQconst [c] x) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } // match: (SUBQconst (MOVQconst [d]) [c]) // result: (MOVQconst [d-int64(c)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d - int64(c)) return true } // match: (SUBQconst (SUBQconst x [d]) [c]) // cond: is32Bit(int64(-c)-int64(d)) // result: (ADDQconst [-c-d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SUBQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(-c) - int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c - d) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (SUBQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (SUBSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (SUBSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64TESTB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [int8(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } break } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVBload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTBconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTBconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTL a:(ANDLload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTL (MOVLload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDLload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTL) v0 := b.NewValue0(a.Pos, OpAMD64MOVLload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTLconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTLconst [c] (MOVLconst [c])) // cond: c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTLconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTL x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTL) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (TESTQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { continue } v.reset(OpAMD64TESTQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTQ a:(ANDQload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTQ (MOVQload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDQload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTQ) v0 := b.NewValue0(a.Pos, OpAMD64MOVQload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTQconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTQconst [-1] x) // cond: x.Op != OpAMD64MOVQconst // result: (TESTQ x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVQconst) { break } v.reset(OpAMD64TESTQ) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [int16(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } break } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVWload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTWconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTWconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64XADDLlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDLlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XADDQlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDQlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGL(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGL [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGQ [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTCL) v.AddArg2(x, y) return true } break } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRLconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRWconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRBconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORLconst(v *Value) bool { v_0 := v.Args[0] // match: (XORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORLconst [1] (SETNE x)) // result: (SETEQ x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETNE { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (XORLconst [1] (SETEQ x)) // result: (SETNE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETEQ { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (XORLconst [1] (SETL x)) // result: (SETGE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETL { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (XORLconst [1] (SETGE x)) // result: (SETL x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETGE { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (XORLconst [1] (SETLE x)) // result: (SETG x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETLE { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (XORLconst [1] (SETG x)) // result: (SETLE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETG { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (XORLconst [1] (SETB x)) // result: (SETAE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETB { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (XORLconst [1] (SETAE x)) // result: (SETB x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETAE { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (XORLconst [1] (SETBE x)) // result: (SETA x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETBE { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (XORLconst [1] (SETA x)) // result: (SETBE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETA { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (XORLconst [c] (XORLconst [d] x)) // result: (XORLconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORLconst [c] (BTCLconst [d] x)) // result: (XORLconst [c ^ 1<= 128 // result: (BTCQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (XORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRQconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORQconst(v *Value) bool { v_0 := v.Args[0] // match: (XORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORQconst [c] (XORQconst [d] x)) // result: (XORQconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORQconst [c] (BTCQconst [d] x)) // cond: is32Bit(int64(c) ^ 1< val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore64(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore64 ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore8 ptr val mem) // result: (Select1 (XCHGB val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStorePtrNoWB(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStorePtrNoWB ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen16 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen16 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) v1.AuxInt = int32ToAuxInt(1) v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v2.AddArg(x) v1.AddArg2(v2, v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (BitLen32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // cond: buildcfg.GOAMD64 < 3 // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(1) v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) v1 := b.NewValue0(v.Pos, OpSelect0, t) v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v3.AuxInt = int64ToAuxInt(-1) v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4.AddArg(v2) v0.AddArg3(v1, v3, v4) v.AddArg(v0) return true } // match: (BitLen64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-64] (LZCNTQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-64) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTQ, typ.UInt64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen8 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen8 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCeil(v *Value) bool { v_0 := v.Args[0] // match: (Ceil x) // result: (ROUNDSD [2] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(2) v.AddArg(x) return true } } func rewriteValueAMD64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (CondSelect x y (SETEQ cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is32BitInt(t) // result: (CMOVLEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is32BitInt(t) // result: (CMOVLNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is32BitInt(t) // result: (CMOVLLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is32BitInt(t) // result: (CMOVLGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is32BitInt(t) // result: (CMOVLLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is32BitInt(t) // result: (CMOVLGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is32BitInt(t) // result: (CMOVLHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is32BitInt(t) // result: (CMOVLCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is32BitInt(t) // result: (CMOVLCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is32BitInt(t) // result: (CMOVLLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is32BitInt(t) // result: (CMOVLEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is32BitInt(t) // result: (CMOVLNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is32BitInt(t) // result: (CMOVLGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is32BitInt(t) // result: (CMOVLGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is16BitInt(t) // result: (CMOVWEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is16BitInt(t) // result: (CMOVWNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is16BitInt(t) // result: (CMOVWLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is16BitInt(t) // result: (CMOVWGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is16BitInt(t) // result: (CMOVWLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is16BitInt(t) // result: (CMOVWGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is16BitInt(t) // result: (CMOVWHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is16BitInt(t) // result: (CMOVWCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is16BitInt(t) // result: (CMOVWCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is16BitInt(t) // result: (CMOVWLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is16BitInt(t) // result: (CMOVWEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is16BitInt(t) // result: (CMOVWNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is16BitInt(t) // result: (CMOVWGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is16BitInt(t) // result: (CMOVWGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 1 // result: (CondSelect x y (MOVBQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 1) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 2 // result: (CondSelect x y (MOVWQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 2) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 4 // result: (CondSelect x y (MOVLQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 4) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { break } v.reset(OpAMD64CMOVQNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) // result: (CMOVLNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) // result: (CMOVWNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } return false } func rewriteValueAMD64_OpConst16(v *Value) bool { // match: (Const16 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt16(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConst8(v *Value) bool { // match: (Const8 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt8(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConstBool(v *Value) bool { // match: (ConstBool [c]) // result: (MOVLconst [b2i32(c)]) for { c := auxIntToBool(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(b2i32(c)) return true } } func rewriteValueAMD64_OpConstNil(v *Value) bool { // match: (ConstNil ) // result: (MOVQconst [0]) for { v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } } func rewriteValueAMD64_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (BSFL (BTSLconst [16] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(16) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz16NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ (BTSQconst [32] x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) v1.AuxInt = int8ToAuxInt(32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz32NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64 x) // cond: buildcfg.GOAMD64 < 3 // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v3.AddArg(v1) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueAMD64_OpCtz64NonZero(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ x)) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (BSFL (BTSLconst [ 8] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 [a] x y) // result: (Select0 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (Select0 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32 [a] x y) // result: (Select0 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32u x y) // result: (Select0 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64 [a] x y) // result: (Select0 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64u x y) // result: (Select0 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq16 x y) // result: (SETEQ (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32 x y) // result: (SETEQ (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32F x y) // result: (SETEQF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64 x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64F x y) // result: (SETEQF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq8 x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqB x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqPtr x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpFMA(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMA x y z) // result: (VFMADD231SD z x y) for { x := v_0 y := v_1 z := v_2 v.reset(OpAMD64VFMADD231SD) v.AddArg3(z, x, y) return true } } func rewriteValueAMD64_OpFloor(v *Value) bool { v_0 := v.Args[0] // match: (Floor x) // result: (ROUNDSD [1] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpGetG(v *Value) bool { v_0 := v.Args[0] // match: (GetG mem) // cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal // result: (LoweredGetG mem) for { mem := v_0 if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) { break } v.reset(OpAMD64LoweredGetG) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (HasCPUFeature {s}) // result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s}))) for { s := auxToSym(v.Aux) v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64) v1.Aux = symToAux(s) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsInBounds idx len) // result: (SETB (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsNonNil(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (IsNonNil p) // result: (SETNE (TESTQ p p)) for { p := v_0 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) v0.AddArg2(p, p) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsSliceInBounds idx len) // result: (SETBE (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16 x y) // result: (SETLE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16U x y) // result: (SETBE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32 x y) // result: (SETLE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32F x y) // result: (SETGEF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32U x y) // result: (SETBE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64 x y) // result: (SETLE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64F x y) // result: (SETGEF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64U x y) // result: (SETBE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8 x y) // result: (SETLE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8U x y) // result: (SETBE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16 x y) // result: (SETL (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16U x y) // result: (SETB (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 x y) // result: (SETL (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32F x y) // result: (SETGF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32U x y) // result: (SETB (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 x y) // result: (SETL (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64F x y) // result: (SETGF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64U x y) // result: (SETB (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8 x y) // result: (SETL (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8U x y) // result: (SETB (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVQload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64MOVQload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) // result: (MOVLload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t)) { break } v.reset(OpAMD64MOVLload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t)) { break } v.reset(OpAMD64MOVWload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(OpAMD64MOVBload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitFloat(t)) { break } v.reset(OpAMD64MOVSSload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitFloat(t)) { break } v.reset(OpAMD64MOVSDload) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpLocalAddr(v *Value) bool { v_0 := v.Args[0] // match: (LocalAddr {sym} base _) // result: (LEAQ {sym} base) for { sym := auxToSym(v.Aux) base := v_0 v.reset(OpAMD64LEAQ) v.Aux = symToAux(sym) v.AddArg(base) return true } } func rewriteValueAMD64_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16 [a] x y) // result: (Select1 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Select1 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32 [a] x y) // result: (Select1 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (Select1 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64 [a] x y) // result: (Select1 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (Select1 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [2] dst src mem) // result: (MOVWstore dst (MOVWload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [4] dst src mem) // result: (MOVLstore dst (MOVLload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [8] dst src mem) // result: (MOVQstore dst (MOVQload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVQstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: config.useSSE // result: (MOVOstore dst (MOVOload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: !config.useSSE // result: (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [32] dst src mem) // result: (Move [16] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpMove) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [48] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 48 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [64] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [32]) (OffPtr src [32]) (Move [32] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 64 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(32) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(32) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(32) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(2) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [6] dst src mem) // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [7] dst src mem) // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [10] dst src mem) // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [12] dst src mem) // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s == 11 || s >= 13 && s <= 15 // result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s == 11 || s >= 13 && s <= 15) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(int32(s - 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(int32(s - 8)) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 <= 8 // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 <= 8) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVOstore dst (MOVOload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AuxInt = int32ToAuxInt(8) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AuxInt = int32ToAuxInt(8) v3.AddArg2(src, mem) v4 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v5 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v5.AddArg2(src, mem) v4.AddArg3(dst, v5, mem) v2.AddArg3(dst, v3, v4) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s) // result: (DUFFCOPY [s] dst src mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s)) { break } v.reset(OpAMD64DUFFCOPY) v.AuxInt = int64ToAuxInt(s) v.AddArg3(dst, src, mem) return true } // match: (Move [s] dst src mem) // cond: (s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s) // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !((s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s)) { break } v.reset(OpAMD64REPMOVSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v.AddArg4(dst, src, v0, mem) return true } return false } func rewriteValueAMD64_OpNeg32F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg32F x) // result: (PXOR x (MOVSSconst [float32(math.Copysign(0, -1))])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1))) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeg64F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg64F x) // result: (PXOR x (MOVSDconst [math.Copysign(0, -1)])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) v0.AuxInt = float64ToAuxInt(math.Copysign(0, -1)) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq16 x y) // result: (SETNE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32 x y) // result: (SETNE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32F x y) // result: (SETNEF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64 x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64F x y) // result: (SETNEF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq8 x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqB x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqPtr x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNot(v *Value) bool { v_0 := v.Args[0] // match: (Not x) // result: (XORLconst [1] x) for { x := v_0 v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // cond: is32Bit(off) // result: (ADDQconst [int32(off)] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 if !(is32Bit(off)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(off)) v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDQ (MOVQconst [off]) ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(off) v.AddArg2(v0, ptr) return true } } func rewriteValueAMD64_OpPanicBounds(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 0) { break } v.reset(OpAMD64LoweredPanicBoundsA) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 1) { break } v.reset(OpAMD64LoweredPanicBoundsB) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 2) { break } v.reset(OpAMD64LoweredPanicBoundsC) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } return false } func rewriteValueAMD64_OpPopCount16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTL (MOVWQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpPopCount8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTL (MOVBQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpRoundToEven(v *Value) bool { v_0 := v.Args[0] // match: (RoundToEven x) // result: (ROUNDSD [0] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } } func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpSelect0(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uover x y)) // result: (Select0 (MULQU x y)) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Mul32uover x y)) // result: (Select0 (MULLU x y)) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y c)) // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst32 val tuple)) // result: (ADDL val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDL) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } // match: (Select0 (AddTupleFirst64 val tuple)) // result: (ADDQ val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } return false } func rewriteValueAMD64_OpSelect1(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uover x y)) // result: (SETO (Select1 (MULQU x y))) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul32uover x y)) // result: (SETO (Select1 (MULLU x y))) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Add64carry x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (NEGLflags (MOVQconst [0]))) // result: (FlagEQ) for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 0 { break } v.reset(OpAMD64FlagEQ) return true } // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) // result: x for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64SBBQcarrymask { break } x := v_0_0_0.Args[0] v.copyOf(x) return true } // match: (Select1 (AddTupleFirst32 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } // match: (Select1 (AddTupleFirst64 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } return false } func rewriteValueAMD64_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem))))) // cond: sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call) // result: (Move [sc.Val64()] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpAMD64MOVQstoreconst { break } sc := auxIntToValAndOff(s1.AuxInt) _ = s1.Args[1] s2 := s1.Args[1] if s2.Op != OpAMD64MOVQstore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpAMD64MOVQstore { break } mem := s3.Args[2] dst := s3.Args[1] if !(sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sc.Val64()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem)) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpAMD64MOVQconst { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } return false } func rewriteValueAMD64_OpSlicemask(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Slicemask x) // result: (SARQconst (NEGQ x) [63]) for { t := v.Type x := v_0 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(63) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpSpectreIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreIndex x y) // result: (CMOVQCC x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQCC) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpSpectreSliceIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreSliceIndex x y) // result: (CMOVQHI x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQHI) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && is64BitFloat(val.Type) // result: (MOVSDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSDstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && is32BitFloat(val.Type) // result: (MOVSSstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSSstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 // result: (MOVQstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8) { break } v.reset(OpAMD64MOVQstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 // result: (MOVLstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4) { break } v.reset(OpAMD64MOVLstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 2 // result: (MOVWstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 2) { break } v.reset(OpAMD64MOVWstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 1 // result: (MOVBstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 1) { break } v.reset(OpAMD64MOVBstore) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpTrunc(v *Value) bool { v_0 := v.Args[0] // match: (Trunc x) // result: (ROUNDSD [3] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(3) v.AddArg(x) return true } } func rewriteValueAMD64_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [0] _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_1 v.copyOf(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [2] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [4] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [8] destptr mem) // result: (MOVQstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 2)) v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [5] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [6] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [7] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 3)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%8 != 0 && s > 8 && !config.useSSE // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%8 != 0 && s > 8 && !config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%8) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [24] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 24 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [32] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 24)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 8 && s < 16 && config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,int32(s-8))] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 8 && s < 16 && config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, int32(s-8))) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [32] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [48] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [64] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,48)] destptr (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 48)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice // result: (DUFFZERO [s] destptr mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFZERO) v.AuxInt = int64ToAuxInt(s) v.AddArg2(destptr, mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0 // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !((s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0) { break } v.reset(OpAMD64REPSTOSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(0) v.AddArg4(destptr, v0, v1, mem) return true } return false } func rewriteBlockAMD64(b *Block) bool { switch b.Kind { case BlockAMD64EQ: // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (UGE (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (UGE (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64GE: // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64GT: // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockIf: // match: (If (SETL cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64SETL { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (If (SETLE cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64SETLE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (If (SETG cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64SETG { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (If (SETGE cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64SETGE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (If (SETEQ cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64SETEQ { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (If (SETNE cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64SETNE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (If (SETB cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64SETB { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (If (SETBE cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64SETBE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (If (SETA cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETA { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETAE cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETAE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETO cmp) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64SETO { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (If (SETGF cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETGF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETGEF cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETGEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETEQF cmp) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64SETEQF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (If (SETNEF cmp) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64SETNEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (If cond yes no) // result: (NE (TESTB cond cond) yes no) for { cond := b.Controls[0] v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) v0.AddArg2(cond, cond) b.resetWithControl(BlockAMD64NE, v0) return true } case BlockAMD64LE: // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64LT: // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETL { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETLE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETG { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQ { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETB { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETBE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETA { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETAE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETO { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (ULT (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (ULT (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGE: // match: (UGE (TESTQ x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTL x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTW x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTB x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (UGE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (UGE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGT: // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (UGT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64ULE: // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (ULE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64ULT: // match: (ULT (TESTQ x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTL x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTW x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTB x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (ULT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- y -- // Code generated from gen/AMD64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "internal/buildcfg" import "math" import "cmd/internal/obj" import "cmd/compile/internal/types" func rewriteValueAMD64(v *Value) bool { switch v.Op { case OpAMD64ADCQ: return rewriteValueAMD64_OpAMD64ADCQ(v) case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst(v) case OpAMD64ADDL: return rewriteValueAMD64_OpAMD64ADDL(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst(v) case OpAMD64ADDLconstmodify: return rewriteValueAMD64_OpAMD64ADDLconstmodify(v) case OpAMD64ADDLload: return rewriteValueAMD64_OpAMD64ADDLload(v) case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify(v) case OpAMD64ADDQ: return rewriteValueAMD64_OpAMD64ADDQ(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry(v) case OpAMD64ADDQconst: return rewriteValueAMD64_OpAMD64ADDQconst(v) case OpAMD64ADDQconstmodify: return rewriteValueAMD64_OpAMD64ADDQconstmodify(v) case OpAMD64ADDQload: return rewriteValueAMD64_OpAMD64ADDQload(v) case OpAMD64ADDQmodify: return rewriteValueAMD64_OpAMD64ADDQmodify(v) case OpAMD64ADDSD: return rewriteValueAMD64_OpAMD64ADDSD(v) case OpAMD64ADDSDload: return rewriteValueAMD64_OpAMD64ADDSDload(v) case OpAMD64ADDSS: return rewriteValueAMD64_OpAMD64ADDSS(v) case OpAMD64ADDSSload: return rewriteValueAMD64_OpAMD64ADDSSload(v) case OpAMD64ANDL: return rewriteValueAMD64_OpAMD64ANDL(v) case OpAMD64ANDLconst: return rewriteValueAMD64_OpAMD64ANDLconst(v) case OpAMD64ANDLconstmodify: return rewriteValueAMD64_OpAMD64ANDLconstmodify(v) case OpAMD64ANDLload: return rewriteValueAMD64_OpAMD64ANDLload(v) case OpAMD64ANDLmodify: return rewriteValueAMD64_OpAMD64ANDLmodify(v) case OpAMD64ANDNL: return rewriteValueAMD64_OpAMD64ANDNL(v) case OpAMD64ANDNQ: return rewriteValueAMD64_OpAMD64ANDNQ(v) case OpAMD64ANDQ: return rewriteValueAMD64_OpAMD64ANDQ(v) case OpAMD64ANDQconst: return rewriteValueAMD64_OpAMD64ANDQconst(v) case OpAMD64ANDQconstmodify: return rewriteValueAMD64_OpAMD64ANDQconstmodify(v) case OpAMD64ANDQload: return rewriteValueAMD64_OpAMD64ANDQload(v) case OpAMD64ANDQmodify: return rewriteValueAMD64_OpAMD64ANDQmodify(v) case OpAMD64BSFQ: return rewriteValueAMD64_OpAMD64BSFQ(v) case OpAMD64BSWAPL: return rewriteValueAMD64_OpAMD64BSWAPL(v) case OpAMD64BSWAPQ: return rewriteValueAMD64_OpAMD64BSWAPQ(v) case OpAMD64BTCLconst: return rewriteValueAMD64_OpAMD64BTCLconst(v) case OpAMD64BTCQconst: return rewriteValueAMD64_OpAMD64BTCQconst(v) case OpAMD64BTLconst: return rewriteValueAMD64_OpAMD64BTLconst(v) case OpAMD64BTQconst: return rewriteValueAMD64_OpAMD64BTQconst(v) case OpAMD64BTRLconst: return rewriteValueAMD64_OpAMD64BTRLconst(v) case OpAMD64BTRQconst: return rewriteValueAMD64_OpAMD64BTRQconst(v) case OpAMD64BTSLconst: return rewriteValueAMD64_OpAMD64BTSLconst(v) case OpAMD64BTSQconst: return rewriteValueAMD64_OpAMD64BTSQconst(v) case OpAMD64CMOVLCC: return rewriteValueAMD64_OpAMD64CMOVLCC(v) case OpAMD64CMOVLCS: return rewriteValueAMD64_OpAMD64CMOVLCS(v) case OpAMD64CMOVLEQ: return rewriteValueAMD64_OpAMD64CMOVLEQ(v) case OpAMD64CMOVLGE: return rewriteValueAMD64_OpAMD64CMOVLGE(v) case OpAMD64CMOVLGT: return rewriteValueAMD64_OpAMD64CMOVLGT(v) case OpAMD64CMOVLHI: return rewriteValueAMD64_OpAMD64CMOVLHI(v) case OpAMD64CMOVLLE: return rewriteValueAMD64_OpAMD64CMOVLLE(v) case OpAMD64CMOVLLS: return rewriteValueAMD64_OpAMD64CMOVLLS(v) case OpAMD64CMOVLLT: return rewriteValueAMD64_OpAMD64CMOVLLT(v) case OpAMD64CMOVLNE: return rewriteValueAMD64_OpAMD64CMOVLNE(v) case OpAMD64CMOVQCC: return rewriteValueAMD64_OpAMD64CMOVQCC(v) case OpAMD64CMOVQCS: return rewriteValueAMD64_OpAMD64CMOVQCS(v) case OpAMD64CMOVQEQ: return rewriteValueAMD64_OpAMD64CMOVQEQ(v) case OpAMD64CMOVQGE: return rewriteValueAMD64_OpAMD64CMOVQGE(v) case OpAMD64CMOVQGT: return rewriteValueAMD64_OpAMD64CMOVQGT(v) case OpAMD64CMOVQHI: return rewriteValueAMD64_OpAMD64CMOVQHI(v) case OpAMD64CMOVQLE: return rewriteValueAMD64_OpAMD64CMOVQLE(v) case OpAMD64CMOVQLS: return rewriteValueAMD64_OpAMD64CMOVQLS(v) case OpAMD64CMOVQLT: return rewriteValueAMD64_OpAMD64CMOVQLT(v) case OpAMD64CMOVQNE: return rewriteValueAMD64_OpAMD64CMOVQNE(v) case OpAMD64CMOVWCC: return rewriteValueAMD64_OpAMD64CMOVWCC(v) case OpAMD64CMOVWCS: return rewriteValueAMD64_OpAMD64CMOVWCS(v) case OpAMD64CMOVWEQ: return rewriteValueAMD64_OpAMD64CMOVWEQ(v) case OpAMD64CMOVWGE: return rewriteValueAMD64_OpAMD64CMOVWGE(v) case OpAMD64CMOVWGT: return rewriteValueAMD64_OpAMD64CMOVWGT(v) case OpAMD64CMOVWHI: return rewriteValueAMD64_OpAMD64CMOVWHI(v) case OpAMD64CMOVWLE: return rewriteValueAMD64_OpAMD64CMOVWLE(v) case OpAMD64CMOVWLS: return rewriteValueAMD64_OpAMD64CMOVWLS(v) case OpAMD64CMOVWLT: return rewriteValueAMD64_OpAMD64CMOVWLT(v) case OpAMD64CMOVWNE: return rewriteValueAMD64_OpAMD64CMOVWNE(v) case OpAMD64CMPB: return rewriteValueAMD64_OpAMD64CMPB(v) case OpAMD64CMPBconst: return rewriteValueAMD64_OpAMD64CMPBconst(v) case OpAMD64CMPBconstload: return rewriteValueAMD64_OpAMD64CMPBconstload(v) case OpAMD64CMPBload: return rewriteValueAMD64_OpAMD64CMPBload(v) case OpAMD64CMPL: return rewriteValueAMD64_OpAMD64CMPL(v) case OpAMD64CMPLconst: return rewriteValueAMD64_OpAMD64CMPLconst(v) case OpAMD64CMPLconstload: return rewriteValueAMD64_OpAMD64CMPLconstload(v) case OpAMD64CMPLload: return rewriteValueAMD64_OpAMD64CMPLload(v) case OpAMD64CMPQ: return rewriteValueAMD64_OpAMD64CMPQ(v) case OpAMD64CMPQconst: return rewriteValueAMD64_OpAMD64CMPQconst(v) case OpAMD64CMPQconstload: return rewriteValueAMD64_OpAMD64CMPQconstload(v) case OpAMD64CMPQload: return rewriteValueAMD64_OpAMD64CMPQload(v) case OpAMD64CMPW: return rewriteValueAMD64_OpAMD64CMPW(v) case OpAMD64CMPWconst: return rewriteValueAMD64_OpAMD64CMPWconst(v) case OpAMD64CMPWconstload: return rewriteValueAMD64_OpAMD64CMPWconstload(v) case OpAMD64CMPWload: return rewriteValueAMD64_OpAMD64CMPWload(v) case OpAMD64CMPXCHGLlock: return rewriteValueAMD64_OpAMD64CMPXCHGLlock(v) case OpAMD64CMPXCHGQlock: return rewriteValueAMD64_OpAMD64CMPXCHGQlock(v) case OpAMD64DIVSD: return rewriteValueAMD64_OpAMD64DIVSD(v) case OpAMD64DIVSDload: return rewriteValueAMD64_OpAMD64DIVSDload(v) case OpAMD64DIVSS: return rewriteValueAMD64_OpAMD64DIVSS(v) case OpAMD64DIVSSload: return rewriteValueAMD64_OpAMD64DIVSSload(v) case OpAMD64HMULL: return rewriteValueAMD64_OpAMD64HMULL(v) case OpAMD64HMULLU: return rewriteValueAMD64_OpAMD64HMULLU(v) case OpAMD64HMULQ: return rewriteValueAMD64_OpAMD64HMULQ(v) case OpAMD64HMULQU: return rewriteValueAMD64_OpAMD64HMULQU(v) case OpAMD64LEAL: return rewriteValueAMD64_OpAMD64LEAL(v) case OpAMD64LEAL1: return rewriteValueAMD64_OpAMD64LEAL1(v) case OpAMD64LEAL2: return rewriteValueAMD64_OpAMD64LEAL2(v) case OpAMD64LEAL4: return rewriteValueAMD64_OpAMD64LEAL4(v) case OpAMD64LEAL8: return rewriteValueAMD64_OpAMD64LEAL8(v) case OpAMD64LEAQ: return rewriteValueAMD64_OpAMD64LEAQ(v) case OpAMD64LEAQ1: return rewriteValueAMD64_OpAMD64LEAQ1(v) case OpAMD64LEAQ2: return rewriteValueAMD64_OpAMD64LEAQ2(v) case OpAMD64LEAQ4: return rewriteValueAMD64_OpAMD64LEAQ4(v) case OpAMD64LEAQ8: return rewriteValueAMD64_OpAMD64LEAQ8(v) case OpAMD64MOVBELstore: return rewriteValueAMD64_OpAMD64MOVBELstore(v) case OpAMD64MOVBEQstore: return rewriteValueAMD64_OpAMD64MOVBEQstore(v) case OpAMD64MOVBEWstore: return rewriteValueAMD64_OpAMD64MOVBEWstore(v) case OpAMD64MOVBQSX: return rewriteValueAMD64_OpAMD64MOVBQSX(v) case OpAMD64MOVBQSXload: return rewriteValueAMD64_OpAMD64MOVBQSXload(v) case OpAMD64MOVBQZX: return rewriteValueAMD64_OpAMD64MOVBQZX(v) case OpAMD64MOVBatomicload: return rewriteValueAMD64_OpAMD64MOVBatomicload(v) case OpAMD64MOVBload: return rewriteValueAMD64_OpAMD64MOVBload(v) case OpAMD64MOVBstore: return rewriteValueAMD64_OpAMD64MOVBstore(v) case OpAMD64MOVBstoreconst: return rewriteValueAMD64_OpAMD64MOVBstoreconst(v) case OpAMD64MOVLQSX: return rewriteValueAMD64_OpAMD64MOVLQSX(v) case OpAMD64MOVLQSXload: return rewriteValueAMD64_OpAMD64MOVLQSXload(v) case OpAMD64MOVLQZX: return rewriteValueAMD64_OpAMD64MOVLQZX(v) case OpAMD64MOVLatomicload: return rewriteValueAMD64_OpAMD64MOVLatomicload(v) case OpAMD64MOVLf2i: return rewriteValueAMD64_OpAMD64MOVLf2i(v) case OpAMD64MOVLi2f: return rewriteValueAMD64_OpAMD64MOVLi2f(v) case OpAMD64MOVLload: return rewriteValueAMD64_OpAMD64MOVLload(v) case OpAMD64MOVLstore: return rewriteValueAMD64_OpAMD64MOVLstore(v) case OpAMD64MOVLstoreconst: return rewriteValueAMD64_OpAMD64MOVLstoreconst(v) case OpAMD64MOVOload: return rewriteValueAMD64_OpAMD64MOVOload(v) case OpAMD64MOVOstore: return rewriteValueAMD64_OpAMD64MOVOstore(v) case OpAMD64MOVOstoreconst: return rewriteValueAMD64_OpAMD64MOVOstoreconst(v) case OpAMD64MOVQatomicload: return rewriteValueAMD64_OpAMD64MOVQatomicload(v) case OpAMD64MOVQf2i: return rewriteValueAMD64_OpAMD64MOVQf2i(v) case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f(v) case OpAMD64MOVQload: return rewriteValueAMD64_OpAMD64MOVQload(v) case OpAMD64MOVQstore: return rewriteValueAMD64_OpAMD64MOVQstore(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst(v) case OpAMD64MOVSDload: return rewriteValueAMD64_OpAMD64MOVSDload(v) case OpAMD64MOVSDstore: return rewriteValueAMD64_OpAMD64MOVSDstore(v) case OpAMD64MOVSSload: return rewriteValueAMD64_OpAMD64MOVSSload(v) case OpAMD64MOVSSstore: return rewriteValueAMD64_OpAMD64MOVSSstore(v) case OpAMD64MOVWQSX: return rewriteValueAMD64_OpAMD64MOVWQSX(v) case OpAMD64MOVWQSXload: return rewriteValueAMD64_OpAMD64MOVWQSXload(v) case OpAMD64MOVWQZX: return rewriteValueAMD64_OpAMD64MOVWQZX(v) case OpAMD64MOVWload: return rewriteValueAMD64_OpAMD64MOVWload(v) case OpAMD64MOVWstore: return rewriteValueAMD64_OpAMD64MOVWstore(v) case OpAMD64MOVWstoreconst: return rewriteValueAMD64_OpAMD64MOVWstoreconst(v) case OpAMD64MULL: return rewriteValueAMD64_OpAMD64MULL(v) case OpAMD64MULLconst: return rewriteValueAMD64_OpAMD64MULLconst(v) case OpAMD64MULQ: return rewriteValueAMD64_OpAMD64MULQ(v) case OpAMD64MULQconst: return rewriteValueAMD64_OpAMD64MULQconst(v) case OpAMD64MULSD: return rewriteValueAMD64_OpAMD64MULSD(v) case OpAMD64MULSDload: return rewriteValueAMD64_OpAMD64MULSDload(v) case OpAMD64MULSS: return rewriteValueAMD64_OpAMD64MULSS(v) case OpAMD64MULSSload: return rewriteValueAMD64_OpAMD64MULSSload(v) case OpAMD64NEGL: return rewriteValueAMD64_OpAMD64NEGL(v) case OpAMD64NEGQ: return rewriteValueAMD64_OpAMD64NEGQ(v) case OpAMD64NOTL: return rewriteValueAMD64_OpAMD64NOTL(v) case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ(v) case OpAMD64ORL: return rewriteValueAMD64_OpAMD64ORL(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst(v) case OpAMD64ORLconstmodify: return rewriteValueAMD64_OpAMD64ORLconstmodify(v) case OpAMD64ORLload: return rewriteValueAMD64_OpAMD64ORLload(v) case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify(v) case OpAMD64ORQ: return rewriteValueAMD64_OpAMD64ORQ(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst(v) case OpAMD64ORQconstmodify: return rewriteValueAMD64_OpAMD64ORQconstmodify(v) case OpAMD64ORQload: return rewriteValueAMD64_OpAMD64ORQload(v) case OpAMD64ORQmodify: return rewriteValueAMD64_OpAMD64ORQmodify(v) case OpAMD64ROLB: return rewriteValueAMD64_OpAMD64ROLB(v) case OpAMD64ROLBconst: return rewriteValueAMD64_OpAMD64ROLBconst(v) case OpAMD64ROLL: return rewriteValueAMD64_OpAMD64ROLL(v) case OpAMD64ROLLconst: return rewriteValueAMD64_OpAMD64ROLLconst(v) case OpAMD64ROLQ: return rewriteValueAMD64_OpAMD64ROLQ(v) case OpAMD64ROLQconst: return rewriteValueAMD64_OpAMD64ROLQconst(v) case OpAMD64ROLW: return rewriteValueAMD64_OpAMD64ROLW(v) case OpAMD64ROLWconst: return rewriteValueAMD64_OpAMD64ROLWconst(v) case OpAMD64RORB: return rewriteValueAMD64_OpAMD64RORB(v) case OpAMD64RORL: return rewriteValueAMD64_OpAMD64RORL(v) case OpAMD64RORQ: return rewriteValueAMD64_OpAMD64RORQ(v) case OpAMD64RORW: return rewriteValueAMD64_OpAMD64RORW(v) case OpAMD64SARB: return rewriteValueAMD64_OpAMD64SARB(v) case OpAMD64SARBconst: return rewriteValueAMD64_OpAMD64SARBconst(v) case OpAMD64SARL: return rewriteValueAMD64_OpAMD64SARL(v) case OpAMD64SARLconst: return rewriteValueAMD64_OpAMD64SARLconst(v) case OpAMD64SARQ: return rewriteValueAMD64_OpAMD64SARQ(v) case OpAMD64SARQconst: return rewriteValueAMD64_OpAMD64SARQconst(v) case OpAMD64SARW: return rewriteValueAMD64_OpAMD64SARW(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst(v) case OpAMD64SARXL: return rewriteValueAMD64_OpAMD64SARXL(v) case OpAMD64SARXQ: return rewriteValueAMD64_OpAMD64SARXQ(v) case OpAMD64SBBLcarrymask: return rewriteValueAMD64_OpAMD64SBBLcarrymask(v) case OpAMD64SBBQ: return rewriteValueAMD64_OpAMD64SBBQ(v) case OpAMD64SBBQcarrymask: return rewriteValueAMD64_OpAMD64SBBQcarrymask(v) case OpAMD64SBBQconst: return rewriteValueAMD64_OpAMD64SBBQconst(v) case OpAMD64SETA: return rewriteValueAMD64_OpAMD64SETA(v) case OpAMD64SETAE: return rewriteValueAMD64_OpAMD64SETAE(v) case OpAMD64SETAEstore: return rewriteValueAMD64_OpAMD64SETAEstore(v) case OpAMD64SETAstore: return rewriteValueAMD64_OpAMD64SETAstore(v) case OpAMD64SETB: return rewriteValueAMD64_OpAMD64SETB(v) case OpAMD64SETBE: return rewriteValueAMD64_OpAMD64SETBE(v) case OpAMD64SETBEstore: return rewriteValueAMD64_OpAMD64SETBEstore(v) case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore(v) case OpAMD64SETEQ: return rewriteValueAMD64_OpAMD64SETEQ(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore(v) case OpAMD64SETG: return rewriteValueAMD64_OpAMD64SETG(v) case OpAMD64SETGE: return rewriteValueAMD64_OpAMD64SETGE(v) case OpAMD64SETGEstore: return rewriteValueAMD64_OpAMD64SETGEstore(v) case OpAMD64SETGstore: return rewriteValueAMD64_OpAMD64SETGstore(v) case OpAMD64SETL: return rewriteValueAMD64_OpAMD64SETL(v) case OpAMD64SETLE: return rewriteValueAMD64_OpAMD64SETLE(v) case OpAMD64SETLEstore: return rewriteValueAMD64_OpAMD64SETLEstore(v) case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore(v) case OpAMD64SETNE: return rewriteValueAMD64_OpAMD64SETNE(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore(v) case OpAMD64SHLL: return rewriteValueAMD64_OpAMD64SHLL(v) case OpAMD64SHLLconst: return rewriteValueAMD64_OpAMD64SHLLconst(v) case OpAMD64SHLQ: return rewriteValueAMD64_OpAMD64SHLQ(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst(v) case OpAMD64SHLXL: return rewriteValueAMD64_OpAMD64SHLXL(v) case OpAMD64SHLXQ: return rewriteValueAMD64_OpAMD64SHLXQ(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB(v) case OpAMD64SHRBconst: return rewriteValueAMD64_OpAMD64SHRBconst(v) case OpAMD64SHRL: return rewriteValueAMD64_OpAMD64SHRL(v) case OpAMD64SHRLconst: return rewriteValueAMD64_OpAMD64SHRLconst(v) case OpAMD64SHRQ: return rewriteValueAMD64_OpAMD64SHRQ(v) case OpAMD64SHRQconst: return rewriteValueAMD64_OpAMD64SHRQconst(v) case OpAMD64SHRW: return rewriteValueAMD64_OpAMD64SHRW(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst(v) case OpAMD64SHRXL: return rewriteValueAMD64_OpAMD64SHRXL(v) case OpAMD64SHRXQ: return rewriteValueAMD64_OpAMD64SHRXQ(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL(v) case OpAMD64SUBLconst: return rewriteValueAMD64_OpAMD64SUBLconst(v) case OpAMD64SUBLload: return rewriteValueAMD64_OpAMD64SUBLload(v) case OpAMD64SUBLmodify: return rewriteValueAMD64_OpAMD64SUBLmodify(v) case OpAMD64SUBQ: return rewriteValueAMD64_OpAMD64SUBQ(v) case OpAMD64SUBQborrow: return rewriteValueAMD64_OpAMD64SUBQborrow(v) case OpAMD64SUBQconst: return rewriteValueAMD64_OpAMD64SUBQconst(v) case OpAMD64SUBQload: return rewriteValueAMD64_OpAMD64SUBQload(v) case OpAMD64SUBQmodify: return rewriteValueAMD64_OpAMD64SUBQmodify(v) case OpAMD64SUBSD: return rewriteValueAMD64_OpAMD64SUBSD(v) case OpAMD64SUBSDload: return rewriteValueAMD64_OpAMD64SUBSDload(v) case OpAMD64SUBSS: return rewriteValueAMD64_OpAMD64SUBSS(v) case OpAMD64SUBSSload: return rewriteValueAMD64_OpAMD64SUBSSload(v) case OpAMD64TESTB: return rewriteValueAMD64_OpAMD64TESTB(v) case OpAMD64TESTBconst: return rewriteValueAMD64_OpAMD64TESTBconst(v) case OpAMD64TESTL: return rewriteValueAMD64_OpAMD64TESTL(v) case OpAMD64TESTLconst: return rewriteValueAMD64_OpAMD64TESTLconst(v) case OpAMD64TESTQ: return rewriteValueAMD64_OpAMD64TESTQ(v) case OpAMD64TESTQconst: return rewriteValueAMD64_OpAMD64TESTQconst(v) case OpAMD64TESTW: return rewriteValueAMD64_OpAMD64TESTW(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock(v) case OpAMD64XADDQlock: return rewriteValueAMD64_OpAMD64XADDQlock(v) case OpAMD64XCHGL: return rewriteValueAMD64_OpAMD64XCHGL(v) case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ(v) case OpAMD64XORL: return rewriteValueAMD64_OpAMD64XORL(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst(v) case OpAMD64XORLconstmodify: return rewriteValueAMD64_OpAMD64XORLconstmodify(v) case OpAMD64XORLload: return rewriteValueAMD64_OpAMD64XORLload(v) case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify(v) case OpAMD64XORQ: return rewriteValueAMD64_OpAMD64XORQ(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst(v) case OpAMD64XORQconstmodify: return rewriteValueAMD64_OpAMD64XORQconstmodify(v) case OpAMD64XORQload: return rewriteValueAMD64_OpAMD64XORQload(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify(v) case OpAdd16: v.Op = OpAMD64ADDL return true case OpAdd32: v.Op = OpAMD64ADDL return true case OpAdd32F: v.Op = OpAMD64ADDSS return true case OpAdd64: v.Op = OpAMD64ADDQ return true case OpAdd64F: v.Op = OpAMD64ADDSD return true case OpAdd8: v.Op = OpAMD64ADDL return true case OpAddPtr: v.Op = OpAMD64ADDQ return true case OpAddr: return rewriteValueAMD64_OpAddr(v) case OpAnd16: v.Op = OpAMD64ANDL return true case OpAnd32: v.Op = OpAMD64ANDL return true case OpAnd64: v.Op = OpAMD64ANDQ return true case OpAnd8: v.Op = OpAMD64ANDL return true case OpAndB: v.Op = OpAMD64ANDL return true case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32(v) case OpAtomicAdd64: return rewriteValueAMD64_OpAtomicAdd64(v) case OpAtomicAnd32: return rewriteValueAMD64_OpAtomicAnd32(v) case OpAtomicAnd8: return rewriteValueAMD64_OpAtomicAnd8(v) case OpAtomicCompareAndSwap32: return rewriteValueAMD64_OpAtomicCompareAndSwap32(v) case OpAtomicCompareAndSwap64: return rewriteValueAMD64_OpAtomicCompareAndSwap64(v) case OpAtomicExchange32: return rewriteValueAMD64_OpAtomicExchange32(v) case OpAtomicExchange64: return rewriteValueAMD64_OpAtomicExchange64(v) case OpAtomicLoad32: return rewriteValueAMD64_OpAtomicLoad32(v) case OpAtomicLoad64: return rewriteValueAMD64_OpAtomicLoad64(v) case OpAtomicLoad8: return rewriteValueAMD64_OpAtomicLoad8(v) case OpAtomicLoadPtr: return rewriteValueAMD64_OpAtomicLoadPtr(v) case OpAtomicOr32: return rewriteValueAMD64_OpAtomicOr32(v) case OpAtomicOr8: return rewriteValueAMD64_OpAtomicOr8(v) case OpAtomicStore32: return rewriteValueAMD64_OpAtomicStore32(v) case OpAtomicStore64: return rewriteValueAMD64_OpAtomicStore64(v) case OpAtomicStore8: return rewriteValueAMD64_OpAtomicStore8(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB(v) case OpAvg64u: v.Op = OpAMD64AVGQU return true case OpBitLen16: return rewriteValueAMD64_OpBitLen16(v) case OpBitLen32: return rewriteValueAMD64_OpBitLen32(v) case OpBitLen64: return rewriteValueAMD64_OpBitLen64(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8(v) case OpBswap32: v.Op = OpAMD64BSWAPL return true case OpBswap64: v.Op = OpAMD64BSWAPQ return true case OpCeil: return rewriteValueAMD64_OpCeil(v) case OpClosureCall: v.Op = OpAMD64CALLclosure return true case OpCom16: v.Op = OpAMD64NOTL return true case OpCom32: v.Op = OpAMD64NOTL return true case OpCom64: v.Op = OpAMD64NOTQ return true case OpCom8: v.Op = OpAMD64NOTL return true case OpCondSelect: return rewriteValueAMD64_OpCondSelect(v) case OpConst16: return rewriteValueAMD64_OpConst16(v) case OpConst32: v.Op = OpAMD64MOVLconst return true case OpConst32F: v.Op = OpAMD64MOVSSconst return true case OpConst64: v.Op = OpAMD64MOVQconst return true case OpConst64F: v.Op = OpAMD64MOVSDconst return true case OpConst8: return rewriteValueAMD64_OpConst8(v) case OpConstBool: return rewriteValueAMD64_OpConstBool(v) case OpConstNil: return rewriteValueAMD64_OpConstNil(v) case OpCtz16: return rewriteValueAMD64_OpCtz16(v) case OpCtz16NonZero: return rewriteValueAMD64_OpCtz16NonZero(v) case OpCtz32: return rewriteValueAMD64_OpCtz32(v) case OpCtz32NonZero: return rewriteValueAMD64_OpCtz32NonZero(v) case OpCtz64: return rewriteValueAMD64_OpCtz64(v) case OpCtz64NonZero: return rewriteValueAMD64_OpCtz64NonZero(v) case OpCtz8: return rewriteValueAMD64_OpCtz8(v) case OpCtz8NonZero: return rewriteValueAMD64_OpCtz8NonZero(v) case OpCvt32Fto32: v.Op = OpAMD64CVTTSS2SL return true case OpCvt32Fto64: v.Op = OpAMD64CVTTSS2SQ return true case OpCvt32Fto64F: v.Op = OpAMD64CVTSS2SD return true case OpCvt32to32F: v.Op = OpAMD64CVTSL2SS return true case OpCvt32to64F: v.Op = OpAMD64CVTSL2SD return true case OpCvt64Fto32: v.Op = OpAMD64CVTTSD2SL return true case OpCvt64Fto32F: v.Op = OpAMD64CVTSD2SS return true case OpCvt64Fto64: v.Op = OpAMD64CVTTSD2SQ return true case OpCvt64to32F: v.Op = OpAMD64CVTSQ2SS return true case OpCvt64to64F: v.Op = OpAMD64CVTSQ2SD return true case OpCvtBoolToUint8: v.Op = OpCopy return true case OpDiv128u: v.Op = OpAMD64DIVQU2 return true case OpDiv16: return rewriteValueAMD64_OpDiv16(v) case OpDiv16u: return rewriteValueAMD64_OpDiv16u(v) case OpDiv32: return rewriteValueAMD64_OpDiv32(v) case OpDiv32F: v.Op = OpAMD64DIVSS return true case OpDiv32u: return rewriteValueAMD64_OpDiv32u(v) case OpDiv64: return rewriteValueAMD64_OpDiv64(v) case OpDiv64F: v.Op = OpAMD64DIVSD return true case OpDiv64u: return rewriteValueAMD64_OpDiv64u(v) case OpDiv8: return rewriteValueAMD64_OpDiv8(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u(v) case OpEq16: return rewriteValueAMD64_OpEq16(v) case OpEq32: return rewriteValueAMD64_OpEq32(v) case OpEq32F: return rewriteValueAMD64_OpEq32F(v) case OpEq64: return rewriteValueAMD64_OpEq64(v) case OpEq64F: return rewriteValueAMD64_OpEq64F(v) case OpEq8: return rewriteValueAMD64_OpEq8(v) case OpEqB: return rewriteValueAMD64_OpEqB(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr(v) case OpFMA: return rewriteValueAMD64_OpFMA(v) case OpFloor: return rewriteValueAMD64_OpFloor(v) case OpGetCallerPC: v.Op = OpAMD64LoweredGetCallerPC return true case OpGetCallerSP: v.Op = OpAMD64LoweredGetCallerSP return true case OpGetClosurePtr: v.Op = OpAMD64LoweredGetClosurePtr return true case OpGetG: return rewriteValueAMD64_OpGetG(v) case OpHasCPUFeature: return rewriteValueAMD64_OpHasCPUFeature(v) case OpHmul32: v.Op = OpAMD64HMULL return true case OpHmul32u: v.Op = OpAMD64HMULLU return true case OpHmul64: v.Op = OpAMD64HMULQ return true case OpHmul64u: v.Op = OpAMD64HMULQU return true case OpInterCall: v.Op = OpAMD64CALLinter return true case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueAMD64_OpIsSliceInBounds(v) case OpLeq16: return rewriteValueAMD64_OpLeq16(v) case OpLeq16U: return rewriteValueAMD64_OpLeq16U(v) case OpLeq32: return rewriteValueAMD64_OpLeq32(v) case OpLeq32F: return rewriteValueAMD64_OpLeq32F(v) case OpLeq32U: return rewriteValueAMD64_OpLeq32U(v) case OpLeq64: return rewriteValueAMD64_OpLeq64(v) case OpLeq64F: return rewriteValueAMD64_OpLeq64F(v) case OpLeq64U: return rewriteValueAMD64_OpLeq64U(v) case OpLeq8: return rewriteValueAMD64_OpLeq8(v) case OpLeq8U: return rewriteValueAMD64_OpLeq8U(v) case OpLess16: return rewriteValueAMD64_OpLess16(v) case OpLess16U: return rewriteValueAMD64_OpLess16U(v) case OpLess32: return rewriteValueAMD64_OpLess32(v) case OpLess32F: return rewriteValueAMD64_OpLess32F(v) case OpLess32U: return rewriteValueAMD64_OpLess32U(v) case OpLess64: return rewriteValueAMD64_OpLess64(v) case OpLess64F: return rewriteValueAMD64_OpLess64F(v) case OpLess64U: return rewriteValueAMD64_OpLess64U(v) case OpLess8: return rewriteValueAMD64_OpLess8(v) case OpLess8U: return rewriteValueAMD64_OpLess8U(v) case OpLoad: return rewriteValueAMD64_OpLoad(v) case OpLocalAddr: return rewriteValueAMD64_OpLocalAddr(v) case OpLsh16x16: return rewriteValueAMD64_OpLsh16x16(v) case OpLsh16x32: return rewriteValueAMD64_OpLsh16x32(v) case OpLsh16x64: return rewriteValueAMD64_OpLsh16x64(v) case OpLsh16x8: return rewriteValueAMD64_OpLsh16x8(v) case OpLsh32x16: return rewriteValueAMD64_OpLsh32x16(v) case OpLsh32x32: return rewriteValueAMD64_OpLsh32x32(v) case OpLsh32x64: return rewriteValueAMD64_OpLsh32x64(v) case OpLsh32x8: return rewriteValueAMD64_OpLsh32x8(v) case OpLsh64x16: return rewriteValueAMD64_OpLsh64x16(v) case OpLsh64x32: return rewriteValueAMD64_OpLsh64x32(v) case OpLsh64x64: return rewriteValueAMD64_OpLsh64x64(v) case OpLsh64x8: return rewriteValueAMD64_OpLsh64x8(v) case OpLsh8x16: return rewriteValueAMD64_OpLsh8x16(v) case OpLsh8x32: return rewriteValueAMD64_OpLsh8x32(v) case OpLsh8x64: return rewriteValueAMD64_OpLsh8x64(v) case OpLsh8x8: return rewriteValueAMD64_OpLsh8x8(v) case OpMod16: return rewriteValueAMD64_OpMod16(v) case OpMod16u: return rewriteValueAMD64_OpMod16u(v) case OpMod32: return rewriteValueAMD64_OpMod32(v) case OpMod32u: return rewriteValueAMD64_OpMod32u(v) case OpMod64: return rewriteValueAMD64_OpMod64(v) case OpMod64u: return rewriteValueAMD64_OpMod64u(v) case OpMod8: return rewriteValueAMD64_OpMod8(v) case OpMod8u: return rewriteValueAMD64_OpMod8u(v) case OpMove: return rewriteValueAMD64_OpMove(v) case OpMul16: v.Op = OpAMD64MULL return true case OpMul32: v.Op = OpAMD64MULL return true case OpMul32F: v.Op = OpAMD64MULSS return true case OpMul64: v.Op = OpAMD64MULQ return true case OpMul64F: v.Op = OpAMD64MULSD return true case OpMul64uhilo: v.Op = OpAMD64MULQU2 return true case OpMul8: v.Op = OpAMD64MULL return true case OpNeg16: v.Op = OpAMD64NEGL return true case OpNeg32: v.Op = OpAMD64NEGL return true case OpNeg32F: return rewriteValueAMD64_OpNeg32F(v) case OpNeg64: v.Op = OpAMD64NEGQ return true case OpNeg64F: return rewriteValueAMD64_OpNeg64F(v) case OpNeg8: v.Op = OpAMD64NEGL return true case OpNeq16: return rewriteValueAMD64_OpNeq16(v) case OpNeq32: return rewriteValueAMD64_OpNeq32(v) case OpNeq32F: return rewriteValueAMD64_OpNeq32F(v) case OpNeq64: return rewriteValueAMD64_OpNeq64(v) case OpNeq64F: return rewriteValueAMD64_OpNeq64F(v) case OpNeq8: return rewriteValueAMD64_OpNeq8(v) case OpNeqB: return rewriteValueAMD64_OpNeqB(v) case OpNeqPtr: return rewriteValueAMD64_OpNeqPtr(v) case OpNilCheck: v.Op = OpAMD64LoweredNilCheck return true case OpNot: return rewriteValueAMD64_OpNot(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr(v) case OpOr16: v.Op = OpAMD64ORL return true case OpOr32: v.Op = OpAMD64ORL return true case OpOr64: v.Op = OpAMD64ORQ return true case OpOr8: v.Op = OpAMD64ORL return true case OpOrB: v.Op = OpAMD64ORL return true case OpPanicBounds: return rewriteValueAMD64_OpPanicBounds(v) case OpPopCount16: return rewriteValueAMD64_OpPopCount16(v) case OpPopCount32: v.Op = OpAMD64POPCNTL return true case OpPopCount64: v.Op = OpAMD64POPCNTQ return true case OpPopCount8: return rewriteValueAMD64_OpPopCount8(v) case OpPrefetchCache: v.Op = OpAMD64PrefetchT0 return true case OpPrefetchCacheStreamed: v.Op = OpAMD64PrefetchNTA return true case OpRotateLeft16: v.Op = OpAMD64ROLW return true case OpRotateLeft32: v.Op = OpAMD64ROLL return true case OpRotateLeft64: v.Op = OpAMD64ROLQ return true case OpRotateLeft8: v.Op = OpAMD64ROLB return true case OpRound32F: v.Op = OpCopy return true case OpRound64F: v.Op = OpCopy return true case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven(v) case OpRsh16Ux16: return rewriteValueAMD64_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValueAMD64_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValueAMD64_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValueAMD64_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValueAMD64_OpRsh16x16(v) case OpRsh16x32: return rewriteValueAMD64_OpRsh16x32(v) case OpRsh16x64: return rewriteValueAMD64_OpRsh16x64(v) case OpRsh16x8: return rewriteValueAMD64_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValueAMD64_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValueAMD64_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValueAMD64_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValueAMD64_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValueAMD64_OpRsh32x16(v) case OpRsh32x32: return rewriteValueAMD64_OpRsh32x32(v) case OpRsh32x64: return rewriteValueAMD64_OpRsh32x64(v) case OpRsh32x8: return rewriteValueAMD64_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValueAMD64_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValueAMD64_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValueAMD64_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValueAMD64_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValueAMD64_OpRsh64x16(v) case OpRsh64x32: return rewriteValueAMD64_OpRsh64x32(v) case OpRsh64x64: return rewriteValueAMD64_OpRsh64x64(v) case OpRsh64x8: return rewriteValueAMD64_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValueAMD64_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValueAMD64_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValueAMD64_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValueAMD64_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValueAMD64_OpRsh8x16(v) case OpRsh8x32: return rewriteValueAMD64_OpRsh8x32(v) case OpRsh8x64: return rewriteValueAMD64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8(v) case OpSelect0: return rewriteValueAMD64_OpSelect0(v) case OpSelect1: return rewriteValueAMD64_OpSelect1(v) case OpSelectN: return rewriteValueAMD64_OpSelectN(v) case OpSignExt16to32: v.Op = OpAMD64MOVWQSX return true case OpSignExt16to64: v.Op = OpAMD64MOVWQSX return true case OpSignExt32to64: v.Op = OpAMD64MOVLQSX return true case OpSignExt8to16: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to32: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to64: v.Op = OpAMD64MOVBQSX return true case OpSlicemask: return rewriteValueAMD64_OpSlicemask(v) case OpSpectreIndex: return rewriteValueAMD64_OpSpectreIndex(v) case OpSpectreSliceIndex: return rewriteValueAMD64_OpSpectreSliceIndex(v) case OpSqrt: v.Op = OpAMD64SQRTSD return true case OpSqrt32: v.Op = OpAMD64SQRTSS return true case OpStaticCall: v.Op = OpAMD64CALLstatic return true case OpStore: return rewriteValueAMD64_OpStore(v) case OpSub16: v.Op = OpAMD64SUBL return true case OpSub32: v.Op = OpAMD64SUBL return true case OpSub32F: v.Op = OpAMD64SUBSS return true case OpSub64: v.Op = OpAMD64SUBQ return true case OpSub64F: v.Op = OpAMD64SUBSD return true case OpSub8: v.Op = OpAMD64SUBL return true case OpSubPtr: v.Op = OpAMD64SUBQ return true case OpTailCall: v.Op = OpAMD64CALLtail return true case OpTrunc: return rewriteValueAMD64_OpTrunc(v) case OpTrunc16to8: v.Op = OpCopy return true case OpTrunc32to16: v.Op = OpCopy return true case OpTrunc32to8: v.Op = OpCopy return true case OpTrunc64to16: v.Op = OpCopy return true case OpTrunc64to32: v.Op = OpCopy return true case OpTrunc64to8: v.Op = OpCopy return true case OpWB: v.Op = OpAMD64LoweredWB return true case OpXor16: v.Op = OpAMD64XORL return true case OpXor32: v.Op = OpAMD64XORL return true case OpXor64: v.Op = OpAMD64XORQ return true case OpXor8: v.Op = OpAMD64XORL return true case OpZero: return rewriteValueAMD64_OpZero(v) case OpZeroExt16to32: v.Op = OpAMD64MOVWQZX return true case OpZeroExt16to64: v.Op = OpAMD64MOVWQZX return true case OpZeroExt32to64: v.Op = OpAMD64MOVLQZX return true case OpZeroExt8to16: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to32: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to64: v.Op = OpAMD64MOVBQZX return true } return false } func rewriteValueAMD64_OpAMD64ADCQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) // result: (ADCQconst x [int32(c)] carry) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) carry := v_2 if !(is32Bit(c)) { continue } v.reset(OpAMD64ADCQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, carry) return true } break } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQcarry) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64ADCQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQconst x [c] (FlagEQ)) // result: (ADDQconstcarry x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDL x (MOVLconst [c])) // result: (ADDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRLconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRWconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRBconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAL2) v.AddArg2(y, x) return true } } break } // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAL { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL { continue } y := v_1.Args[0] v.reset(OpAMD64SUBL) v.AddArg2(x, y) return true } break } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDLconst [c] (ADDL x y)) // result: (LEAL1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (SHLLconst [1] x)) // result: (LEAL1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // result: (MOVLconst [c+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c + d) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // result: (ADDLconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDLconst [off] x:(SP)) // result: (LEAL [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (ADDL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ADDQ x (MOVLconst [c])) // result: (ADDQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRQconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAQ2) v.AddArg2(y, x) return true } } break } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ { continue } y := v_1.Args[0] v.reset(OpAMD64SUBQ) v.AddArg2(x, y) return true } break } // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQcarry(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQcarry x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconstcarry x [int32(c)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDQconst [c] (ADDQ x y)) // result: (LEAQ1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (SHLQconst [1] x)) // result: (LEAQ1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDQconst [c] (LEAQ [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ADDQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) + d) return true } // match: (ADDQconst [c] (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (ADDQconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDQconst [off] x:(SP)) // result: (LEAQ [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (ADDQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (ADDSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (ADDSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ANDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTRL) v.AddArg2(x, y) return true } break } // match: (ANDL (NOTL (SHLXL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLXL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTRL) v.AddArg2(x, y) return true } break } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } break } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ANDL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDL x (NOTL y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTL { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNL) v.AddArg2(x, y) return true } break } // match: (ANDL x (NEGL x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIL) v.AddArg(x) return true } break } // match: (ANDL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSRL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSRL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDLconst [c] x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDLconst [c] (BTRLconst [d] x)) // result: (ANDLconst [c &^ (1<= 128 // result: (BTRQconst [int8(log64(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log64(^c))) v.AddArg(x) return true } break } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ANDQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDQ x (NOTQ y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTQ { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNQ) v.AddArg2(x, y) return true } break } // match: (ANDQ x (NEGQ x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIQ) v.AddArg(x) return true } break } // match: (ANDQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSRQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSRQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDQconst [c] x) // cond: isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRQconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDQconst [c] (ANDQconst [d] x)) // result: (ANDQconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDQconst [c] (BTRQconst [d] x)) // cond: is32Bit(int64(c) &^ (1< [1<<8] (MOVBQZX x))) // result: (BSFQ (ORQconst [1<<8] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVBQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 8) v0.AddArg(x) v.AddArg(v0) return true } // match: (BSFQ (ORQconst [1<<16] (MOVWQZX x))) // result: (BSFQ (ORQconst [1<<16] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVWQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPL(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPL (BSWAPL p)) // result: p for { if v_0.Op != OpAMD64BSWAPL { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPL x:(MOVLload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPL (MOVBELload [i] {s} p m)) // result: (MOVLload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBELload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPQ(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPQ (BSWAPQ p)) // result: p for { if v_0.Op != OpAMD64BSWAPQ { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPQ x:(MOVQload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPQ (MOVBEQload [i] {s} p m)) // result: (MOVQload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBEQload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BTCLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTCLconst [c] (XORLconst [d] x)) // result: (XORLconst [d ^ 1<d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTLconst [0] s:(SHRXQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 32) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTLconst [c] (SHLLconst [d] x)) // cond: c>d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } // match: (BTLconst [0] s:(SHRXL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTQconst(v *Value) bool { v_0 := v.Args[0] // match: (BTQconst [c] (SHRQconst [d] x)) // cond: (c+d)<64 // result: (BTQconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 64) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTQconst [c] (SHLQconst [d] x)) // cond: c>d // result: (BTQconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTQconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTQconst [0] s:(SHRXQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTRLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTRLconst [c] (BTSLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTSLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (BTCLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTCLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [d &^ (1<uint8(y) // result: (FlagLT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) < y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x) y && uint8(x) < uint8(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) > y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int8(m) && int8(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPBconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTB x y) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, y) return true } // match: (CMPBconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTBconst [int8(c)] x) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt8(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVBload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPBload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPL x (MOVLconst [c])) // result: (CMPLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64CMPLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // result: (InvertFlags (CMPLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPL y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x==y // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x == y) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: xuint32(y) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x < y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x) y && uint32(x) < uint32(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x > y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) // result: (FlagLT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x < y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x)>uint64(y) // result: (FlagGT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x > y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQ l:(MOVQload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPQload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPQ x l:(MOVQload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPQload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPQload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPQconst (NEGQ (ADDQconst [-16] (ANDQconst [15] _))) [32]) // result: (FlagLT_ULT) for { if auxIntToInt32(v.AuxInt) != 32 || v_0.Op != OpAMD64NEGQ { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_0_0.AuxInt) != -16 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_0_0.AuxInt) != 15 { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (NEGQ (ADDQconst [ -8] (ANDQconst [7] _))) [32]) // result: (FlagLT_ULT) for { if auxIntToInt32(v.AuxInt) != 32 || v_0.Op != OpAMD64NEGQ { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_0_0.AuxInt) != -8 { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_0_0.AuxInt) != 7 { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x==int64(y) // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x == int64(y)) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: xuint64(int64(y)) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x < int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x) int64(y) && uint64(x) < uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x)>uint64(int64(y)) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x > int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQconst (MOVBQZX _) [c]) // cond: 0xFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVWQZX _) [c]) // cond: 0xFFFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (SHRQconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 64 && (1<uint16(y) // result: (FlagLT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) < y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x) y && uint16(x) < uint16(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) > y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int16(m) && int16(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPWconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTW x y) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, y) return true } // match: (CMPWconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTWconst [int16(c)] x) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt16(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVWload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPWload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGLlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGQlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64HMULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULL x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULL y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULLU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULLU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULLU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULLU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQ x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQ y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64LEAL(v *Value) bool { v_0 := v.Args[0] // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { v_0 := v.Args[0] // match: (LEAQ [c] {s} (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAQ [c] {s} (ADDQ x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg(x) return true } // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ2 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ4 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ8 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64LEAQ { continue } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(y, x) return true } } break } // match: (LEAQ1 [0] x y) // cond: v.Aux == nil // result: (ADDQ x y) for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 y := v_1 if !(v.Aux == nil) { break } v.reset(OpAMD64ADDQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAQ2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil // result: (LEAQ4 [off1+2*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + 2*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ2 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ2 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAQ4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil // result: (LEAQ8 [off1+4*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + 4*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ4 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ4 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAQ8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ8 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ8 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBELstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBELstore [i] {s} p (BSWAPL x) m) // result: (MOVLstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPL { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEQstore [i] {s} p (BSWAPQ x) m) // result: (MOVQstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPQ { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7f) v.AddArg(x) return true } // match: (MOVBQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x) // cond: zeroUpper56Bits(x,3) // result: x for { x := v_0 if !(zeroUpper56Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVBQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xff) v.AddArg(x) return true } // match: (MOVBQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read8(sym, int64(off)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read8(sym, int64(off)))) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) // cond: y.Uses == 1 // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETL { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) // cond: y.Uses == 1 // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETLE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) // cond: y.Uses == 1 // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETG { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) // cond: y.Uses == 1 // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETGE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) // cond: y.Uses == 1 // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETEQ { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) // cond: y.Uses == 1 // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETNE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) // cond: y.Uses == 1 // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETB { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) // cond: y.Uses == 1 // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETBE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) // cond: y.Uses == 1 // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETA { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) // cond: y.Uses == 1 // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETAE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstore [i-1] {s} p (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p1 w x0:(MOVBstore [i] {s} p0 (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0) // result: (MOVWstore [i] {s} p0 (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-1 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-3 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 3) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p3 w x2:(MOVBstore [i] {s} p2 (SHRLconst [8] w) x1:(MOVBstore [i] {s} p1 (SHRLconst [16] w) x0:(MOVBstore [i] {s} p0 (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2) // result: (MOVLstore [i] {s} p0 (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p3 := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i-1 || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] if p != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i-2 || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i-3 || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i-4 || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-5 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-6 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-7 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 7) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p7 w x6:(MOVBstore [i] {s} p6 (SHRQconst [8] w) x5:(MOVBstore [i] {s} p5 (SHRQconst [16] w) x4:(MOVBstore [i] {s} p4 (SHRQconst [24] w) x3:(MOVBstore [i] {s} p3 (SHRQconst [32] w) x2:(MOVBstore [i] {s} p2 (SHRQconst [40] w) x1:(MOVBstore [i] {s} p1 (SHRQconst [48] w) x0:(MOVBstore [i] {s} p0 (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i] {s} p0 (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p7 := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] p6 := x6.Args[0] x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] p5 := x5.Args[0] x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] p4 := x4.Args[0] x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] p3 := x3.Args[0] x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRWconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [7] {s} p1 (SHRQconst [56] w) x1:(MOVWstore [5] {s} p1 (SHRQconst [40] w) x2:(MOVLstore [1] {s} p1 (SHRQconst [8] w) x3:(MOVBstore [0] {s} p1 w mem)))) // cond: x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && clobber(x1, x2, x3) // result: (MOVQstore {s} p1 w mem) for { if auxIntToInt32(v.AuxInt) != 7 { break } s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 56 { break } w := v_1.Args[0] x1 := v_2 if x1.Op != OpAMD64MOVWstore || auxIntToInt32(x1.AuxInt) != 5 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p1 != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 40 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpAMD64MOVLstore || auxIntToInt32(x2.AuxInt) != 1 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p1 != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != 0 || auxToSym(x3.Aux) != s { break } mem := x3.Args[2] if p1 != x3.Args[0] || w != x3.Args[1] || !(x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && clobber(x1, x2, x3)) { break } v.reset(OpAMD64MOVQstore) v.Aux = symToAux(s) v.AddArg3(p1, w, mem) return true } // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVBload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVBstore || auxIntToInt32(mem2.AuxInt) != i-1 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVBload || auxIntToInt32(x2.AuxInt) != j-1 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(j - 1) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && a.Off() + 1 == c.Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && a.Off()+1 == c.Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (MOVBstoreconst [a] {s} p x:(MOVBstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && a.Off() + 1 == c.Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && a.Off()+1 == c.Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX (ANDLconst [c] x)) // cond: uint32(c) & 0x80000000 == 0 // result: (ANDLconst [c & 0x7fffffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(uint32(c)&0x80000000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fffffff) v.AddArg(x) return true } // match: (MOVLQSX (MOVLQSX x)) // result: (MOVLQSX x) for { if v_0.Op != OpAMD64MOVLQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x) // cond: zeroUpper32Bits(x,3) // result: x for { x := v_0 if !(zeroUpper32Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVLQZX (ANDLconst [c] x)) // result: (ANDLconst [c] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (MOVLQZX (MOVLQZX x)) // result: (MOVLQZX x) for { if v_0.Op != OpAMD64MOVLQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLf2i) v.AddArg(val) return true } // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [32] w) x:(MOVLstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [j] w) x:(MOVLstore [i] {s} p0 w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVLload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVLstore || auxIntToInt32(mem2.AuxInt) != i-4 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVLload || auxIntToInt32(x2.AuxInt) != j-4 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(j - 4) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) // result: (MOVSSstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [i] {s} p x:(BSWAPL w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPL { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [c] {s} p x:(MOVLstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && a.Off() + 4 == c.Off() && clobber(x) // result: (MOVQstore [a.Off()] {s} p (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && a.Off()+4 == c.Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p, v0, mem) return true } // match: (MOVLstoreconst [a] {s} p x:(MOVLstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && a.Off() + 4 == c.Off() && clobber(x) // result: (MOVQstore [a.Off()] {s} p (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && a.Off()+4 == c.Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) // cond: symIsRO(srcSym) // result: (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))]) (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))]) mem)) for { dstOff := auxIntToInt32(v.AuxInt) dstSym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVOload { break } srcOff := auxIntToInt32(v_1.AuxInt) srcSym := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } mem := v_2 if !(symIsRO(srcSym)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(dstOff + 8) v.Aux = symToAux(dstSym) v0 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))) v1 := b.NewValue0(v_1.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AuxInt = int32ToAuxInt(dstOff) v1.Aux = symToAux(dstSym) v2 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))) v1.AddArg3(ptr, v2, mem) v.AddArg3(ptr, v0, v1) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVOstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.copyOf(x) return true } // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) // result: (MOVQf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQf2i) v.AddArg(val) return true } // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validVal(c) // result: (MOVQstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(validVal(c)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) // result: (MOVSDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [i] {s} p x:(BSWAPQ w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPQ { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [c] {s} p x:(MOVQstoreconst [a] {s} p mem)) // cond: config.useSSE && x.Uses == 1 && a.Off() + 8 == c.Off() && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(config.useSSE && x.Uses == 1 && a.Off()+8 == c.Off() && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (MOVQstoreconst [a] {s} p x:(MOVQstoreconst [c] {s} p mem)) // cond: config.useSSE && x.Uses == 1 && a.Off() + 8 == c.Off() && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(config.useSSE && x.Uses == 1 && a.Off()+8 == c.Off() && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fff) v.AddArg(x) return true } // match: (MOVWQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x) // cond: zeroUpper48Bits(x,3) // result: x for { x := v_0 if !(zeroUpper48Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVWQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xffff) v.AddArg(x) return true } // match: (MOVWQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVWload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVWstore || auxIntToInt32(mem2.AuxInt) != i-2 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVWload || auxIntToInt32(x2.AuxInt) != j-2 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(j - 2) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && a.Off() + 2 == c.Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && a.Off()+2 == c.Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (MOVWstoreconst [a] {s} p x:(MOVWstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && a.Off() + 2 == c.Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && a.Off()+2 == c.Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } return false } func rewriteValueAMD64_OpAMD64MULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULL x (MOVLconst [c])) // result: (MULLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULLconst [c] (MULLconst [d] x)) // result: (MULLconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULLconst [-9] x) // result: (NEGL (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // result: (NEGL (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // result: (NEGL (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // result: (NEGL x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGL) v.AddArg(x) return true } // match: (MULLconst [ 0] _) // result: (MOVLconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (MULLconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULLconst [ 3] x) // result: (LEAL2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAL2) v.AddArg2(x, x) return true } // match: (MULLconst [ 5] x) // result: (LEAL4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAL4) v.AddArg2(x, x) return true } // match: (MULLconst [ 7] x) // result: (LEAL2 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [ 9] x) // result: (LEAL8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAL8) v.AddArg2(x, x) return true } // match: (MULLconst [11] x) // result: (LEAL2 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [13] x) // result: (LEAL4 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [19] x) // result: (LEAL2 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [21] x) // result: (LEAL4 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [25] x) // result: (LEAL8 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [27] x) // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [37] x) // result: (LEAL4 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [41] x) // result: (LEAL8 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [45] x) // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [73] x) // result: (LEAL8 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [81] x) // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBL (SHLLconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAL1) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLLconst [int8(log32(c/3))] (LEAL2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLLconst [int8(log32(c/5))] (LEAL4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLLconst [int8(log32(c/9))] (LEAL8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] (MOVLconst [d])) // result: (MOVLconst [c*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c * d) return true } return false } func rewriteValueAMD64_OpAMD64MULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (MULQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULQconst [c] (MULQconst [d] x)) // cond: is32Bit(int64(c)*int64(d)) // result: (MULQconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) * int64(d))) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULQconst [-9] x) // result: (NEGQ (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-5] x) // result: (NEGQ (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-3] x) // result: (NEGQ (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-1] x) // result: (NEGQ x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGQ) v.AddArg(x) return true } // match: (MULQconst [ 0] _) // result: (MOVQconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MULQconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULQconst [ 3] x) // result: (LEAQ2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAQ2) v.AddArg2(x, x) return true } // match: (MULQconst [ 5] x) // result: (LEAQ4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAQ4) v.AddArg2(x, x) return true } // match: (MULQconst [ 7] x) // result: (LEAQ2 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [ 9] x) // result: (LEAQ8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAQ8) v.AddArg2(x, x) return true } // match: (MULQconst [11] x) // result: (LEAQ2 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [13] x) // result: (LEAQ4 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [19] x) // result: (LEAQ2 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [21] x) // result: (LEAQ4 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [25] x) // result: (LEAQ8 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [27] x) // result: (LEAQ8 (LEAQ2 x x) (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [37] x) // result: (LEAQ4 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [41] x) // result: (LEAQ8 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [45] x) // result: (LEAQ8 (LEAQ4 x x) (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [73] x) // result: (LEAQ8 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [81] x) // result: (LEAQ8 (LEAQ8 x x) (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBQ (SHLQconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAQ1 (SHLQconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAQ1) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAQ2 (SHLQconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAQ4 (SHLQconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAQ8 (SHLQconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLQconst [int8(log32(c/3))] (LEAQ2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLQconst [int8(log32(c/5))] (LEAQ4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLQconst [int8(log32(c/9))] (LEAQ8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) * d) return true } // match: (MULQconst [c] (NEGQ x)) // cond: c != -(1<<31) // result: (MULQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (MULSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64MULSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (MULSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64NEGL(v *Value) bool { v_0 := v.Args[0] // match: (NEGL (NEGL x)) // result: x for { if v_0.Op != OpAMD64NEGL { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGL s:(SUBL x y)) // cond: s.Uses == 1 // result: (SUBL y x) for { s := v_0 if s.Op != OpAMD64SUBL { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBL) v.AddArg2(y, x) return true } // match: (NEGL (MOVLconst [c])) // result: (MOVLconst [-c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-c) return true } return false } func rewriteValueAMD64_OpAMD64NEGQ(v *Value) bool { v_0 := v.Args[0] // match: (NEGQ (NEGQ x)) // result: x for { if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGQ s:(SUBQ x y)) // cond: s.Uses == 1 // result: (SUBQ y x) for { s := v_0 if s.Op != OpAMD64SUBQ { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBQ) v.AddArg2(y, x) return true } // match: (NEGQ (MOVQconst [c])) // result: (MOVQconst [-c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-c) return true } // match: (NEGQ (ADDQconst [c] (NEGQ x))) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { if v_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } x := v_0_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64NOTL(v *Value) bool { v_0 := v.Args[0] // match: (NOTL (MOVLconst [c])) // result: (MOVLconst [^c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64NOTQ(v *Value) bool { v_0 := v.Args[0] // match: (NOTQ (MOVQconst [c])) // result: (MOVQconst [^c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64ORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTSL) v.AddArg2(x, y) return true } break } // match: (ORL (SHLXL (MOVLconst [1]) y) x) // result: (BTSL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTSL) v.AddArg2(x, y) return true } break } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRLconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRWconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRBconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (RORL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (RORL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLXL x y) (ANDL (SHRXL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRXL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLXL x y) (ANDL (SHRXL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRXL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRXL x y) (ANDL (SHLXL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (RORL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRXL x y) (ANDL (SHLXL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (RORL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXL { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRW x (ANDQconst y [15])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg2(x, y) return true } break } // match: (ORL (SHRW x (ANDLconst y [15])) (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg2(x, y) return true } break } // match: (ORL (SHLXL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLXL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRW x (ANDQconst y [15])) (SHLXL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLXL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg2(x, y) return true } break } // match: (ORL (SHRW x (ANDLconst y [15])) (SHLXL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLXL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg2(x, y) return true } break } // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg2(x, y) return true } break } // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg2(x, y) return true } break } // match: (ORL (SHLXL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg2(x, y) return true } } break } // match: (ORL (SHLXL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg2(x, y) return true } } break } // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLXL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLXL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg2(x, y) return true } break } // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLXL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { continue } y := v_0_1.Args[0] if v_1.Op != OpAMD64SHLXL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg2(x, y) return true } break } // match: (ORL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORL x0:(MOVBload [i0] {s} p mem) sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVBload [i] {s} p0 mem) sh:(SHLLconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVWload [i] {s} p0 mem) sh:(SHLLconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL x1:(MOVBload [i] {s} p1 mem) sh:(SHLLconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORLconst(v *Value) bool { v_0 := v.Args[0] // match: (ORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORLconst [c] (ORLconst [d] x)) // result: (ORLconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORLconst [c] (BTSLconst [d] x)) // result: (ORLconst [c | 1<= 128 // result: (BTSQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ORQ x (MOVLconst [c])) // result: (ORQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRQconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHLXQ x y) (ANDQ (SHRXQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRXQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHLXQ x y) (ANDQ (SHRXQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHRXQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHRXQ x y) (ANDQ (SHLXQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHRXQ x y) (ANDQ (SHLXQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXQ { continue } y := v_0.Args[1] x := v_0.Args[0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg2(x, y) return true } } break } // match: (ORQ (SHRQ lo bits) (SHLQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLQ lo bits) (SHRQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHRXQ lo bits) (SHLXQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLXQ lo bits) (SHRXQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (MOVQconst [c]) (MOVQconst [d])) // result: (MOVQconst [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c | d) return true } break } // match: (ORQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORQ x0:(MOVBload [i0] {s} p mem) sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBload [i] {s} p0 mem) sh:(SHLQconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVWload [i] {s} p0 mem) sh:(SHLQconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVLload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVLload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i] {s} p0 mem)) y)) // cond: j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ x1:(MOVBload [i] {s} p1 mem) sh:(SHLQconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i] {s} p1 mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem))) y)) // cond: j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ORQ x0:(MOVBELload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVBELload [i1] {s} p mem))) // cond: i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i1] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i1) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBELload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVBELload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i] {s} p1 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p1, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQconst(v *Value) bool { v_0 := v.Args[0] // match: (ORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORQconst [c] (ORQconst [d] x)) // result: (ORQconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORQconst [c] (BTSQconst [d] x)) // cond: is32Bit(int64(c) | 1<>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int8(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARL x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SARXL x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (MOVLconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SARLconst(v *Value) bool { v_0 := v.Args[0] // match: (SARLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARLconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int32(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int32(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SARXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (MOVLconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SARQconst(v *Value) bool { v_0 := v.Args[0] // match: (SARQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARQconst [c] (MOVQconst [d])) // result: (MOVQconst [d>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SARW x (MOVQconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } // match: (SARW x (MOVLconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SARWconst(v *Value) bool { v_0 := v.Args[0] // match: (SARWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARWconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int16(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int16(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARXL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARXL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARXL x (MOVLconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARXL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v.AddArg2(x, y) return true } // match: (SARXL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SARXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARXQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARXQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARXQ x (MOVLconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARXQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v.AddArg2(x, y) return true } // match: (SARXQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARXQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SARXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SBBLcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBLcarrymask (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagLT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagGT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQ x (MOVQconst [c]) borrow) // cond: is32Bit(c) // result: (SBBQconst x [int32(c)] borrow) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) borrow := v_2 if !(is32Bit(c)) { break } v.reset(OpAMD64SBBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, borrow) return true } // match: (SBBQ x y (FlagEQ)) // result: (SUBQborrow x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQborrow) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64SBBQcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBQcarrymask (FlagEQ)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagLT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagLT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagGT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagGT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQconst x [c] (FlagEQ)) // result: (SUBQconstborrow x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SETA(v *Value) bool { v_0 := v.Args[0] // match: (SETA (InvertFlags x)) // result: (SETB x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETA (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAE(v *Value) bool { v_0 := v.Args[0] // match: (SETAE (TESTQ x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTL x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTW x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTB x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (InvertFlags x)) // result: (SETBE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETAstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETB(v *Value) bool { v_0 := v.Args[0] // match: (SETB (TESTQ x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTL x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTW x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTB x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (BTLconst [0] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64BTLconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (BTQconst [0] x)) // result: (ANDQconst [1] x) for { if v_0.Op != OpAMD64BTQconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (InvertFlags x)) // result: (SETA x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBE(v *Value) bool { v_0 := v.Args[0] // match: (SETBE (InvertFlags x)) // result: (SETAE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETBE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAE (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAE (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETNE (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETEQ (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETEQstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETG(v *Value) bool { v_0 := v.Args[0] // match: (SETG (InvertFlags x)) // result: (SETL x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETG (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGE(v *Value) bool { v_0 := v.Args[0] // match: (SETGE (InvertFlags x)) // result: (SETLE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETL(v *Value) bool { v_0 := v.Args[0] // match: (SETL (InvertFlags x)) // result: (SETG x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLE(v *Value) bool { v_0 := v.Args[0] // match: (SETLE (InvertFlags x)) // result: (SETGE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETLE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNE(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETNE (TESTBconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTBconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTWconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTWconst || auxIntToInt16(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETB (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETB (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETEQ (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (InvertFlags x)) // result: (SETNE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETNE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLXQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETNEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLL x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHLXL x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (MOVLconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLLconst [1] (SHRLconst [1] x)) // result: (BTRLconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLLconst [d] (MOVLconst [c])) // result: (MOVLconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHLXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (MOVLconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLQconst [1] (SHRQconst [1] x)) // result: (BTRQconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLQconst [d] (MOVQconst [c])) // result: (MOVQconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c << uint64(d)) return true } // match: (SHLQconst [d] (MOVLconst [c])) // result: (MOVQconst [int64(c) << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLXL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLXL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLXL x (MOVLconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLXL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } // match: (SHLXL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHLXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLXQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLXQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLXQ x (MOVLconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLXQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true } // match: (SHLXQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLXQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHLXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRB x (MOVQconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB _ (MOVQconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRBconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRBconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRL x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHRXL x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (MOVLconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRLconst [1] (SHLLconst [1] x)) // result: (BTRLconst [31] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(31) v.AddArg(x) return true } // match: (SHRLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHRXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (MOVLconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRQconst [1] (SHLQconst [1] x)) // result: (BTRQconst [63] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(63) v.AddArg(x) return true } // match: (SHRQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRW x (MOVQconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW _ (MOVQconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRWconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRXL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRXL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRXL x (MOVLconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRXL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRXL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRXL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v.AddArg2(x, y) return true } // match: (SHRXL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRXL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRXL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHRXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRXQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRXQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRXQ x (MOVLconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRXQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRXQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRXQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v.AddArg2(x, y) return true } // match: (SHRXQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRXQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRXQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRXQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (SHRXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBL x (MOVLconst [c])) // result: (SUBLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SUBLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // result: (NEGL (SUBLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBLconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (SUBLconst [c] x) // result: (ADDLconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } } func rewriteValueAMD64_OpAMD64SUBLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (SUBL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconst x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } // match: (SUBQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (NEGQ (SUBQconst x [int32(c)])) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBQload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQborrow(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQborrow x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconstborrow x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SUBQconst [c] x) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } // match: (SUBQconst (MOVQconst [d]) [c]) // result: (MOVQconst [d-int64(c)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d - int64(c)) return true } // match: (SUBQconst (SUBQconst x [d]) [c]) // cond: is32Bit(int64(-c)-int64(d)) // result: (ADDQconst [-c-d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SUBQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(-c) - int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c - d) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (SUBQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (SUBSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (SUBSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64TESTB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [int8(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } break } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVBload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTBconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTBconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTL a:(ANDLload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTL (MOVLload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDLload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTL) v0 := b.NewValue0(a.Pos, OpAMD64MOVLload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTLconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTLconst [c] (MOVLconst [c])) // cond: c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTLconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTL x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTL) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (TESTQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { continue } v.reset(OpAMD64TESTQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTQ a:(ANDQload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTQ (MOVQload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDQload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTQ) v0 := b.NewValue0(a.Pos, OpAMD64MOVQload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTQconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTQconst [-1] x) // cond: x.Op != OpAMD64MOVQconst // result: (TESTQ x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVQconst) { break } v.reset(OpAMD64TESTQ) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [int16(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } break } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVWload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTWconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTWconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64XADDLlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDLlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XADDQlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDQlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGL(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGL [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGQ [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTCL) v.AddArg2(x, y) return true } break } // match: (XORL (SHLXL (MOVLconst [1]) y) x) // result: (BTCL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTCL) v.AddArg2(x, y) return true } break } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRLconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRWconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLLconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRBconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORLconst(v *Value) bool { v_0 := v.Args[0] // match: (XORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORLconst [1] (SETNE x)) // result: (SETEQ x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETNE { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (XORLconst [1] (SETEQ x)) // result: (SETNE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETEQ { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (XORLconst [1] (SETL x)) // result: (SETGE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETL { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (XORLconst [1] (SETGE x)) // result: (SETL x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETGE { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (XORLconst [1] (SETLE x)) // result: (SETG x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETLE { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (XORLconst [1] (SETG x)) // result: (SETLE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETG { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (XORLconst [1] (SETB x)) // result: (SETAE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETB { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (XORLconst [1] (SETAE x)) // result: (SETB x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETAE { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (XORLconst [1] (SETBE x)) // result: (SETA x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETBE { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (XORLconst [1] (SETA x)) // result: (SETBE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETA { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (XORLconst [c] (XORLconst [d] x)) // result: (XORLconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORLconst [c] (BTCLconst [d] x)) // result: (XORLconst [c ^ 1<= 128 // result: (BTCQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (XORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQconst { continue } c := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpAMD64SHRQconst { continue } d := auxIntToInt8(v_1.AuxInt) if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORQconst(v *Value) bool { v_0 := v.Args[0] // match: (XORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORQconst [c] (XORQconst [d] x)) // result: (XORQconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORQconst [c] (BTCQconst [d] x)) // cond: is32Bit(int64(c) ^ 1< val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore64(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore64 ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore8 ptr val mem) // result: (Select1 (XCHGB val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStorePtrNoWB(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStorePtrNoWB ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen16 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen16 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) v1.AuxInt = int32ToAuxInt(1) v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v2.AddArg(x) v1.AddArg2(v2, v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (BitLen32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // cond: buildcfg.GOAMD64 < 3 // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(1) v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) v1 := b.NewValue0(v.Pos, OpSelect0, t) v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v3.AuxInt = int64ToAuxInt(-1) v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4.AddArg(v2) v0.AddArg3(v1, v3, v4) v.AddArg(v0) return true } // match: (BitLen64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-64] (LZCNTQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-64) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTQ, typ.UInt64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen8 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen8 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCeil(v *Value) bool { v_0 := v.Args[0] // match: (Ceil x) // result: (ROUNDSD [2] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(2) v.AddArg(x) return true } } func rewriteValueAMD64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (CondSelect x y (SETEQ cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is32BitInt(t) // result: (CMOVLEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is32BitInt(t) // result: (CMOVLNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is32BitInt(t) // result: (CMOVLLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is32BitInt(t) // result: (CMOVLGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is32BitInt(t) // result: (CMOVLLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is32BitInt(t) // result: (CMOVLGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is32BitInt(t) // result: (CMOVLHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is32BitInt(t) // result: (CMOVLCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is32BitInt(t) // result: (CMOVLCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is32BitInt(t) // result: (CMOVLLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is32BitInt(t) // result: (CMOVLEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is32BitInt(t) // result: (CMOVLNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is32BitInt(t) // result: (CMOVLGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is32BitInt(t) // result: (CMOVLGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is16BitInt(t) // result: (CMOVWEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is16BitInt(t) // result: (CMOVWNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is16BitInt(t) // result: (CMOVWLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is16BitInt(t) // result: (CMOVWGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is16BitInt(t) // result: (CMOVWLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is16BitInt(t) // result: (CMOVWGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is16BitInt(t) // result: (CMOVWHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is16BitInt(t) // result: (CMOVWCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is16BitInt(t) // result: (CMOVWCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is16BitInt(t) // result: (CMOVWLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is16BitInt(t) // result: (CMOVWEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is16BitInt(t) // result: (CMOVWNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is16BitInt(t) // result: (CMOVWGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is16BitInt(t) // result: (CMOVWGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 1 // result: (CondSelect x y (MOVBQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 1) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 2 // result: (CondSelect x y (MOVWQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 2) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 4 // result: (CondSelect x y (MOVLQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 4) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { break } v.reset(OpAMD64CMOVQNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) // result: (CMOVLNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) // result: (CMOVWNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } return false } func rewriteValueAMD64_OpConst16(v *Value) bool { // match: (Const16 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt16(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConst8(v *Value) bool { // match: (Const8 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt8(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConstBool(v *Value) bool { // match: (ConstBool [c]) // result: (MOVLconst [b2i32(c)]) for { c := auxIntToBool(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(b2i32(c)) return true } } func rewriteValueAMD64_OpConstNil(v *Value) bool { // match: (ConstNil ) // result: (MOVQconst [0]) for { v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } } func rewriteValueAMD64_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (BSFL (BTSLconst [16] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(16) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz16NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ (BTSQconst [32] x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) v1.AuxInt = int8ToAuxInt(32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz32NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64 x) // cond: buildcfg.GOAMD64 < 3 // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v3.AddArg(v1) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueAMD64_OpCtz64NonZero(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ x)) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (BSFL (BTSLconst [ 8] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 [a] x y) // result: (Select0 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (Select0 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32 [a] x y) // result: (Select0 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32u x y) // result: (Select0 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64 [a] x y) // result: (Select0 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64u x y) // result: (Select0 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq16 x y) // result: (SETEQ (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32 x y) // result: (SETEQ (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32F x y) // result: (SETEQF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64 x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64F x y) // result: (SETEQF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq8 x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqB x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqPtr x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpFMA(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMA x y z) // result: (VFMADD231SD z x y) for { x := v_0 y := v_1 z := v_2 v.reset(OpAMD64VFMADD231SD) v.AddArg3(z, x, y) return true } } func rewriteValueAMD64_OpFloor(v *Value) bool { v_0 := v.Args[0] // match: (Floor x) // result: (ROUNDSD [1] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpGetG(v *Value) bool { v_0 := v.Args[0] // match: (GetG mem) // cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal // result: (LoweredGetG mem) for { mem := v_0 if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) { break } v.reset(OpAMD64LoweredGetG) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (HasCPUFeature {s}) // result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s}))) for { s := auxToSym(v.Aux) v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64) v1.Aux = symToAux(s) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsInBounds idx len) // result: (SETB (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsNonNil(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (IsNonNil p) // result: (SETNE (TESTQ p p)) for { p := v_0 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) v0.AddArg2(p, p) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsSliceInBounds idx len) // result: (SETBE (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16 x y) // result: (SETLE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16U x y) // result: (SETBE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32 x y) // result: (SETLE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32F x y) // result: (SETGEF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32U x y) // result: (SETBE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64 x y) // result: (SETLE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64F x y) // result: (SETGEF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64U x y) // result: (SETBE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8 x y) // result: (SETLE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8U x y) // result: (SETBE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16 x y) // result: (SETL (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16U x y) // result: (SETB (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 x y) // result: (SETL (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32F x y) // result: (SETGF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32U x y) // result: (SETB (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 x y) // result: (SETL (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64F x y) // result: (SETGF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64U x y) // result: (SETB (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8 x y) // result: (SETL (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8U x y) // result: (SETB (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVQload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64MOVQload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) // result: (MOVLload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t)) { break } v.reset(OpAMD64MOVLload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t)) { break } v.reset(OpAMD64MOVWload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(OpAMD64MOVBload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitFloat(t)) { break } v.reset(OpAMD64MOVSSload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitFloat(t)) { break } v.reset(OpAMD64MOVSDload) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpLocalAddr(v *Value) bool { v_0 := v.Args[0] // match: (LocalAddr {sym} base _) // result: (LEAQ {sym} base) for { sym := auxToSym(v.Aux) base := v_0 v.reset(OpAMD64LEAQ) v.Aux = symToAux(sym) v.AddArg(base) return true } } func rewriteValueAMD64_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16 [a] x y) // result: (Select1 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Select1 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32 [a] x y) // result: (Select1 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (Select1 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64 [a] x y) // result: (Select1 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (Select1 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [2] dst src mem) // result: (MOVWstore dst (MOVWload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [4] dst src mem) // result: (MOVLstore dst (MOVLload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [8] dst src mem) // result: (MOVQstore dst (MOVQload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVQstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: config.useSSE // result: (MOVOstore dst (MOVOload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: !config.useSSE // result: (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [32] dst src mem) // result: (Move [16] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpMove) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [48] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 48 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [64] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [32]) (OffPtr src [32]) (Move [32] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 64 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(32) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(32) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(32) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(2) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [6] dst src mem) // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [7] dst src mem) // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [10] dst src mem) // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [12] dst src mem) // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s == 11 || s >= 13 && s <= 15 // result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s == 11 || s >= 13 && s <= 15) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(int32(s - 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(int32(s - 8)) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 <= 8 // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 <= 8) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVOstore dst (MOVOload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AuxInt = int32ToAuxInt(8) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AuxInt = int32ToAuxInt(8) v3.AddArg2(src, mem) v4 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v5 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v5.AddArg2(src, mem) v4.AddArg3(dst, v5, mem) v2.AddArg3(dst, v3, v4) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s) // result: (DUFFCOPY [s] dst src mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s)) { break } v.reset(OpAMD64DUFFCOPY) v.AuxInt = int64ToAuxInt(s) v.AddArg3(dst, src, mem) return true } // match: (Move [s] dst src mem) // cond: (s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s) // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !((s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s)) { break } v.reset(OpAMD64REPMOVSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v.AddArg4(dst, src, v0, mem) return true } return false } func rewriteValueAMD64_OpNeg32F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg32F x) // result: (PXOR x (MOVSSconst [float32(math.Copysign(0, -1))])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1))) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeg64F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg64F x) // result: (PXOR x (MOVSDconst [math.Copysign(0, -1)])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) v0.AuxInt = float64ToAuxInt(math.Copysign(0, -1)) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq16 x y) // result: (SETNE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32 x y) // result: (SETNE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32F x y) // result: (SETNEF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64 x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64F x y) // result: (SETNEF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq8 x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqB x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqPtr x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNot(v *Value) bool { v_0 := v.Args[0] // match: (Not x) // result: (XORLconst [1] x) for { x := v_0 v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // cond: is32Bit(off) // result: (ADDQconst [int32(off)] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 if !(is32Bit(off)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(off)) v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDQ (MOVQconst [off]) ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(off) v.AddArg2(v0, ptr) return true } } func rewriteValueAMD64_OpPanicBounds(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 0) { break } v.reset(OpAMD64LoweredPanicBoundsA) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 1) { break } v.reset(OpAMD64LoweredPanicBoundsB) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 2) { break } v.reset(OpAMD64LoweredPanicBoundsC) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } return false } func rewriteValueAMD64_OpPopCount16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTL (MOVWQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpPopCount8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTL (MOVBQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpRoundToEven(v *Value) bool { v_0 := v.Args[0] // match: (RoundToEven x) // result: (ROUNDSD [0] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } } func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpSelect0(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uover x y)) // result: (Select0 (MULQU x y)) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Mul32uover x y)) // result: (Select0 (MULLU x y)) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y c)) // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst32 val tuple)) // result: (ADDL val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDL) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } // match: (Select0 (AddTupleFirst64 val tuple)) // result: (ADDQ val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } return false } func rewriteValueAMD64_OpSelect1(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uover x y)) // result: (SETO (Select1 (MULQU x y))) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul32uover x y)) // result: (SETO (Select1 (MULLU x y))) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Add64carry x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (NEGLflags (MOVQconst [0]))) // result: (FlagEQ) for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 0 { break } v.reset(OpAMD64FlagEQ) return true } // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) // result: x for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64SBBQcarrymask { break } x := v_0_0_0.Args[0] v.copyOf(x) return true } // match: (Select1 (AddTupleFirst32 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } // match: (Select1 (AddTupleFirst64 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } return false } func rewriteValueAMD64_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem))))) // cond: sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call) // result: (Move [sc.Val64()] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpAMD64MOVQstoreconst { break } sc := auxIntToValAndOff(s1.AuxInt) _ = s1.Args[1] s2 := s1.Args[1] if s2.Op != OpAMD64MOVQstore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpAMD64MOVQstore { break } mem := s3.Args[2] dst := s3.Args[1] if !(sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sc.Val64()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem)) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpAMD64MOVQconst { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } return false } func rewriteValueAMD64_OpSlicemask(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Slicemask x) // result: (SARQconst (NEGQ x) [63]) for { t := v.Type x := v_0 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(63) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpSpectreIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreIndex x y) // result: (CMOVQCC x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQCC) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpSpectreSliceIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreSliceIndex x y) // result: (CMOVQHI x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQHI) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && is64BitFloat(val.Type) // result: (MOVSDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSDstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && is32BitFloat(val.Type) // result: (MOVSSstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSSstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 // result: (MOVQstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8) { break } v.reset(OpAMD64MOVQstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 // result: (MOVLstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4) { break } v.reset(OpAMD64MOVLstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 2 // result: (MOVWstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 2) { break } v.reset(OpAMD64MOVWstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 1 // result: (MOVBstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 1) { break } v.reset(OpAMD64MOVBstore) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpTrunc(v *Value) bool { v_0 := v.Args[0] // match: (Trunc x) // result: (ROUNDSD [3] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(3) v.AddArg(x) return true } } func rewriteValueAMD64_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [0] _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_1 v.copyOf(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [2] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [4] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [8] destptr mem) // result: (MOVQstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 2)) v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [5] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [6] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [7] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 3)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%8 != 0 && s > 8 && !config.useSSE // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%8 != 0 && s > 8 && !config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%8) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [24] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 24 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [32] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 24)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 8 && s < 16 && config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,int32(s-8))] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 8 && s < 16 && config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, int32(s-8))) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [32] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [48] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [64] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,48)] destptr (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 48)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice // result: (DUFFZERO [s] destptr mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFZERO) v.AuxInt = int64ToAuxInt(s) v.AddArg2(destptr, mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0 // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !((s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0) { break } v.reset(OpAMD64REPSTOSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(0) v.AddArg4(destptr, v0, v1, mem) return true } return false } func rewriteBlockAMD64(b *Block) bool { switch b.Kind { case BlockAMD64EQ: // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (UGE (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (UGE (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64GE: // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64GT: // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockIf: // match: (If (SETL cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64SETL { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (If (SETLE cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64SETLE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (If (SETG cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64SETG { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (If (SETGE cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64SETGE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (If (SETEQ cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64SETEQ { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (If (SETNE cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64SETNE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (If (SETB cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64SETB { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (If (SETBE cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64SETBE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (If (SETA cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETA { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETAE cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETAE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETO cmp) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64SETO { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (If (SETGF cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETGF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETGEF cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETGEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETEQF cmp) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64SETEQF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (If (SETNEF cmp) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64SETNEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (If cond yes no) // result: (NE (TESTB cond cond) yes no) for { cond := b.Controls[0] v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) v0.AddArg2(cond, cond) b.resetWithControl(BlockAMD64NE, v0) return true } case BlockAMD64LE: // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64LT: // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETL { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETLE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETG { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQ { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETB { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETBE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETA { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETAE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETO { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL (SHLXL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (ULT (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (ULT (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGE: // match: (UGE (TESTQ x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTL x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTW x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTB x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (UGE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (UGE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGT: // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (UGT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64ULE: // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (ULE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64ULT: // match: (ULT (TESTQ x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTL x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTW x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTB x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (ULT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- diff -- @@ -442,6 +442,10 @@ return rewriteValueAMD64_OpAMD64SHLQ(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst(v) + case OpAMD64SHLXL: + return rewriteValueAMD64_OpAMD64SHLXL(v) + case OpAMD64SHLXQ: + return rewriteValueAMD64_OpAMD64SHLXQ(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB(v) case OpAMD64SHRBconst: @@ -458,6 +462,10 @@ return rewriteValueAMD64_OpAMD64SHRW(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst(v) + case OpAMD64SHRXL: + return rewriteValueAMD64_OpAMD64SHRXL(v) + case OpAMD64SHRXQ: + return rewriteValueAMD64_OpAMD64SHRXQ(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL(v) case OpAMD64SUBLconst: @@ -2704,6 +2712,29 @@ } break } + // match: (ANDL (NOTL (SHLXL (MOVLconst [1]) y)) x) + // result: (BTRL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64NOTL { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SHLXL { + continue + } + y := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTRL) + v.AddArg2(x, y) + return true + } + break + } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) @@ -3121,6 +3152,22 @@ v.AddArg2(x, y) return true } + // match: (ANDNL x (SHLXL (MOVLconst [1]) y)) + // result: (BTRL x y) + for { + x := v_0 + if v_1.Op != OpAMD64SHLXL { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0.AuxInt) != 1 { + break + } + v.reset(OpAMD64BTRL) + v.AddArg2(x, y) + return true + } return false } func rewriteValueAMD64_OpAMD64ANDNQ(v *Value) bool { @@ -3142,6 +3189,22 @@ v.AddArg2(x, y) return true } + // match: (ANDNQ x (SHLXQ (MOVQconst [1]) y)) + // result: (BTRQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64SHLXQ { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0.AuxInt) != 1 { + break + } + v.reset(OpAMD64BTRQ) + v.AddArg2(x, y) + return true + } return false } func rewriteValueAMD64_OpAMD64ANDQ(v *Value) bool { @@ -3170,6 +3233,29 @@ } break } + // match: (ANDQ (NOTQ (SHLXQ (MOVQconst [1]) y)) x) + // result: (BTRQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64NOTQ { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SHLXQ { + continue + } + y := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTRQ) + v.AddArg2(x, y) + return true + } + break + } // match: (ANDQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRQconst [int8(log64(^c))] x) @@ -3873,6 +3959,22 @@ v.AddArg2(y, x) return true } + // match: (BTLconst [0] s:(SHRXQ x y)) + // result: (BTQ y x) + for { + if auxIntToInt8(v.AuxInt) != 0 { + break + } + s := v_0 + if s.Op != OpAMD64SHRXQ { + break + } + y := s.Args[1] + x := s.Args[0] + v.reset(OpAMD64BTQ) + v.AddArg2(y, x) + return true + } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) @@ -3925,6 +4027,22 @@ v.AddArg2(y, x) return true } + // match: (BTLconst [0] s:(SHRXL x y)) + // result: (BTL y x) + for { + if auxIntToInt8(v.AuxInt) != 0 { + break + } + s := v_0 + if s.Op != OpAMD64SHRXL { + break + } + y := s.Args[1] + x := s.Args[0] + v.reset(OpAMD64BTL) + v.AddArg2(y, x) + return true + } return false } func rewriteValueAMD64_OpAMD64BTQconst(v *Value) bool { @@ -3981,6 +4099,22 @@ v.AddArg2(y, x) return true } + // match: (BTQconst [0] s:(SHRXQ x y)) + // result: (BTQ y x) + for { + if auxIntToInt8(v.AuxInt) != 0 { + break + } + s := v_0 + if s.Op != OpAMD64SHRXQ { + break + } + y := s.Args[1] + x := s.Args[0] + v.reset(OpAMD64BTQ) + v.AddArg2(y, x) + return true + } return false } func rewriteValueAMD64_OpAMD64BTRLconst(v *Value) bool { @@ -15890,6 +16024,25 @@ } break } + // match: (ORL (SHLXL (MOVLconst [1]) y) x) + // result: (BTSL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTSL) + v.AddArg2(x, y) + return true + } + break + } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) @@ -16200,6 +16353,206 @@ } break } + // match: (ORL (SHLXL x y) (ANDL (SHRXL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) + // result: (ROLL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRXL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLL) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHLXL x y) (ANDL (SHRXL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) + // result: (ROLL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRXL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLL) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHRXL x y) (ANDL (SHLXL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) + // result: (RORL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRXL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORL) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHRXL x y) (ANDL (SHLXL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) + // result: (RORL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRXL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORL) + v.AddArg2(x, y) + return true + } + } + break + } // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) @@ -16408,6 +16761,214 @@ } break } + // match: (ORL (SHLXL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) + // cond: v.Type.Size() == 2 + // result: (ROLW x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRW { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64ROLW) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHLXL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) + // cond: v.Type.Size() == 2 + // result: (ROLW x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRW { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64ROLW) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHRW x (ANDQconst y [15])) (SHLXL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) + // cond: v.Type.Size() == 2 + // result: (RORW x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64SHLXL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGQ { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64RORW) + v.AddArg2(x, y) + return true + } + break + } + // match: (ORL (SHRW x (ANDLconst y [15])) (SHLXL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) + // cond: v.Type.Size() == 2 + // result: (RORW x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64SHLXL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGL { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64RORW) + v.AddArg2(x, y) + return true + } + break + } // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) @@ -16616,6 +17177,214 @@ } break } + // match: (ORL (SHLXL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) + // cond: v.Type.Size() == 1 + // result: (ROLB x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRB { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64ROLB) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHLXL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) + // cond: v.Type.Size() == 1 + // result: (ROLB x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRB { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64ROLB) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLXL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) + // cond: v.Type.Size() == 1 + // result: (RORB x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRB { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64SHLXL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGQ { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64RORB) + v.AddArg2(x, y) + return true + } + break + } + // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLXL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) + // cond: v.Type.Size() == 1 + // result: (RORB x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRB { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64SHLXL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGL { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64RORB) + v.AddArg2(x, y) + return true + } + break + } // match: (ORL x x) // result: x for { @@ -17509,6 +18278,25 @@ } break } + // match: (ORQ (SHLXQ (MOVQconst [1]) y) x) + // result: (BTSQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXQ { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTSQ) + v.AddArg2(x, y) + return true + } + break + } // match: (ORQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSQconst [int8(log64(c))] x) @@ -17789,6 +18577,206 @@ } break } + // match: (ORQ (SHLXQ x y) (ANDQ (SHRXQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) + // result: (ROLQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRXQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLQ) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORQ (SHLXQ x y) (ANDQ (SHRXQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) + // result: (ROLQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRXQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLQ) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORQ (SHRXQ x y) (ANDQ (SHLXQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) + // result: (RORQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRXQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORQ) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORQ (SHRXQ x y) (ANDQ (SHLXQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) + // result: (RORQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRXQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORQ) + v.AddArg2(x, y) + return true + } + } + break + } // match: (ORQ (SHRQ lo bits) (SHLQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { @@ -17837,6 +18825,54 @@ } break } + // match: (ORQ (SHRXQ lo bits) (SHLXQ hi (NEGQ bits))) + // result: (SHRDQ lo hi bits) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRXQ { + continue + } + bits := v_0.Args[1] + lo := v_0.Args[0] + if v_1.Op != OpAMD64SHLXQ { + continue + } + _ = v_1.Args[1] + hi := v_1.Args[0] + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { + continue + } + v.reset(OpAMD64SHRDQ) + v.AddArg3(lo, hi, bits) + return true + } + break + } + // match: (ORQ (SHLXQ lo bits) (SHRXQ hi (NEGQ bits))) + // result: (SHLDQ lo hi bits) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXQ { + continue + } + bits := v_0.Args[1] + lo := v_0.Args[0] + if v_1.Op != OpAMD64SHRXQ { + continue + } + _ = v_1.Args[1] + hi := v_1.Args[0] + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { + continue + } + v.reset(OpAMD64SHLDQ) + v.AddArg3(lo, hi, bits) + return true + } + break + } // match: (ORQ (MOVQconst [c]) (MOVQconst [d])) // result: (MOVQconst [c|d]) for { @@ -22062,6 +23098,60 @@ } break } + // match: (SETEQ (TESTL (SHLXL (MOVLconst [1]) x) y)) + // result: (SETAE (BTL x y)) + for { + if v_0.Op != OpAMD64TESTL { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (SETEQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) + // result: (SETAE (BTQ x y)) + for { + if v_0.Op != OpAMD64TESTQ { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAE (BTLconst [int8(log32(c))] x)) @@ -22487,6 +23577,72 @@ } break } + // match: (SETEQstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) + // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTL { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXL { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { + continue + } + y := v_1_1 + mem := v_2 + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg3(ptr, v0, mem) + return true + } + break + } + // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) + // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXQ { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { + continue + } + y := v_1_1 + mem := v_2 + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg3(ptr, v0, mem) + return true + } + break + } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) @@ -23978,6 +25134,60 @@ } break } + // match: (SETNE (TESTL (SHLXL (MOVLconst [1]) x) y)) + // result: (SETB (BTL x y)) + for { + if v_0.Op != OpAMD64TESTL { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (SETNE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) + // result: (SETB (BTQ x y)) + for { + if v_0.Op != OpAMD64TESTQ { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETB (BTLconst [int8(log32(c))] x)) @@ -24403,6 +25613,72 @@ } break } + // match: (SETNEstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) + // result: (SETBstore [off] {sym} ptr (BTL x y) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTL { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXL { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { + continue + } + y := v_1_1 + mem := v_2 + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg3(ptr, v0, mem) + return true + } + break + } + // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) + // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXQ { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { + continue + } + y := v_1_1 + mem := v_2 + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg3(ptr, v0, mem) + return true + } + break + } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) @@ -24917,6 +26193,19 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + // match: (SHLL x y) + // cond: buildcfg.GOAMD64 >= 3 + // result: (SHLXL x y) + for { + x := v_0 + y := v_1 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64SHLXL) + v.AddArg2(x, y) + return true + } // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { @@ -25107,28 +26396,6 @@ v.AddArg2(x, v0) return true } - // match: (SHLL l:(MOVLload [off] {sym} ptr mem) x) - // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SHLXLload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVLload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHLXLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { @@ -25173,6 +26440,19 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + // match: (SHLQ x y) + // cond: buildcfg.GOAMD64 >= 3 + // result: (SHLXQ x y) + for { + x := v_0 + y := v_1 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64SHLXQ) + v.AddArg2(x, y) + return true + } // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { @@ -25363,28 +26643,6 @@ v.AddArg2(x, v0) return true } - // match: (SHLQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SHLXQload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHLXQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { @@ -25437,6 +26695,442 @@ } return false } +func rewriteValueAMD64_OpAMD64SHLXL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (SHLXL x (MOVQconst [c])) + // result: (SHLLconst [int8(c&31)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64SHLLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) + return true + } + // match: (SHLXL x (MOVLconst [c])) + // result: (SHLLconst [int8(c&31)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64SHLLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) + return true + } + // match: (SHLXL x (ADDQconst [c] y)) + // cond: c & 31 == 0 + // result: (SHLXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHLXL) + v.AddArg2(x, y) + return true + } + // match: (SHLXL x (NEGQ (ADDQconst [c] y))) + // cond: c & 31 == 0 + // result: (SHLXL x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHLXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXL x (ANDQconst [c] y)) + // cond: c & 31 == 31 + // result: (SHLXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHLXL) + v.AddArg2(x, y) + return true + } + // match: (SHLXL x (NEGQ (ANDQconst [c] y))) + // cond: c & 31 == 31 + // result: (SHLXL x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHLXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXL x (ADDLconst [c] y)) + // cond: c & 31 == 0 + // result: (SHLXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHLXL) + v.AddArg2(x, y) + return true + } + // match: (SHLXL x (NEGL (ADDLconst [c] y))) + // cond: c & 31 == 0 + // result: (SHLXL x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHLXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXL x (ANDLconst [c] y)) + // cond: c & 31 == 31 + // result: (SHLXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHLXL) + v.AddArg2(x, y) + return true + } + // match: (SHLXL x (NEGL (ANDLconst [c] y))) + // cond: c & 31 == 31 + // result: (SHLXL x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHLXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXL l:(MOVLload [off] {sym} ptr mem) x) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (SHLXLload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVLload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHLXLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SHLXQ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (SHLXQ x (MOVQconst [c])) + // result: (SHLQconst [int8(c&63)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64SHLQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v.AddArg(x) + return true + } + // match: (SHLXQ x (MOVLconst [c])) + // result: (SHLQconst [int8(c&63)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64SHLQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v.AddArg(x) + return true + } + // match: (SHLXQ x (ADDQconst [c] y)) + // cond: c & 63 == 0 + // result: (SHLXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHLXQ) + v.AddArg2(x, y) + return true + } + // match: (SHLXQ x (NEGQ (ADDQconst [c] y))) + // cond: c & 63 == 0 + // result: (SHLXQ x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHLXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXQ x (ANDQconst [c] y)) + // cond: c & 63 == 63 + // result: (SHLXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHLXQ) + v.AddArg2(x, y) + return true + } + // match: (SHLXQ x (NEGQ (ANDQconst [c] y))) + // cond: c & 63 == 63 + // result: (SHLXQ x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHLXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXQ x (ADDLconst [c] y)) + // cond: c & 63 == 0 + // result: (SHLXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHLXQ) + v.AddArg2(x, y) + return true + } + // match: (SHLXQ x (NEGL (ADDLconst [c] y))) + // cond: c & 63 == 0 + // result: (SHLXQ x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHLXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXQ x (ANDLconst [c] y)) + // cond: c & 63 == 63 + // result: (SHLXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHLXQ) + v.AddArg2(x, y) + return true + } + // match: (SHLXQ x (NEGL (ANDLconst [c] y))) + // cond: c & 63 == 63 + // result: (SHLXQ x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHLXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXQ l:(MOVQload [off] {sym} ptr mem) x) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (SHLXQload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVQload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHLXQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + return false +} func rewriteValueAMD64_OpAMD64SHRB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -25524,6 +27218,19 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + // match: (SHRL x y) + // cond: buildcfg.GOAMD64 >= 3 + // result: (SHRXL x y) + for { + x := v_0 + y := v_1 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64SHRXL) + v.AddArg2(x, y) + return true + } // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { @@ -25714,28 +27421,6 @@ v.AddArg2(x, v0) return true } - // match: (SHRL l:(MOVLload [off] {sym} ptr mem) x) - // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SHRXLload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVLload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHRXLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { @@ -25768,6 +27453,19 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + // match: (SHRQ x y) + // cond: buildcfg.GOAMD64 >= 3 + // result: (SHRXQ x y) + for { + x := v_0 + y := v_1 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64SHRXQ) + v.AddArg2(x, y) + return true + } // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { @@ -25958,28 +27656,6 @@ v.AddArg2(x, v0) return true } - // match: (SHRQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SHRXQload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHRXQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { @@ -26091,6 +27767,442 @@ } return false } +func rewriteValueAMD64_OpAMD64SHRXL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (SHRXL x (MOVQconst [c])) + // result: (SHRLconst [int8(c&31)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64SHRLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) + return true + } + // match: (SHRXL x (MOVLconst [c])) + // result: (SHRLconst [int8(c&31)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64SHRLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) + return true + } + // match: (SHRXL x (ADDQconst [c] y)) + // cond: c & 31 == 0 + // result: (SHRXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHRXL) + v.AddArg2(x, y) + return true + } + // match: (SHRXL x (NEGQ (ADDQconst [c] y))) + // cond: c & 31 == 0 + // result: (SHRXL x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHRXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXL x (ANDQconst [c] y)) + // cond: c & 31 == 31 + // result: (SHRXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHRXL) + v.AddArg2(x, y) + return true + } + // match: (SHRXL x (NEGQ (ANDQconst [c] y))) + // cond: c & 31 == 31 + // result: (SHRXL x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHRXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXL x (ADDLconst [c] y)) + // cond: c & 31 == 0 + // result: (SHRXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHRXL) + v.AddArg2(x, y) + return true + } + // match: (SHRXL x (NEGL (ADDLconst [c] y))) + // cond: c & 31 == 0 + // result: (SHRXL x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHRXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXL x (ANDLconst [c] y)) + // cond: c & 31 == 31 + // result: (SHRXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHRXL) + v.AddArg2(x, y) + return true + } + // match: (SHRXL x (NEGL (ANDLconst [c] y))) + // cond: c & 31 == 31 + // result: (SHRXL x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHRXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXL l:(MOVLload [off] {sym} ptr mem) x) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (SHRXLload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVLload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHRXLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SHRXQ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (SHRXQ x (MOVQconst [c])) + // result: (SHRQconst [int8(c&63)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64SHRQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v.AddArg(x) + return true + } + // match: (SHRXQ x (MOVLconst [c])) + // result: (SHRQconst [int8(c&63)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64SHRQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v.AddArg(x) + return true + } + // match: (SHRXQ x (ADDQconst [c] y)) + // cond: c & 63 == 0 + // result: (SHRXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHRXQ) + v.AddArg2(x, y) + return true + } + // match: (SHRXQ x (NEGQ (ADDQconst [c] y))) + // cond: c & 63 == 0 + // result: (SHRXQ x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHRXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXQ x (ANDQconst [c] y)) + // cond: c & 63 == 63 + // result: (SHRXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHRXQ) + v.AddArg2(x, y) + return true + } + // match: (SHRXQ x (NEGQ (ANDQconst [c] y))) + // cond: c & 63 == 63 + // result: (SHRXQ x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHRXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXQ x (ADDLconst [c] y)) + // cond: c & 63 == 0 + // result: (SHRXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHRXQ) + v.AddArg2(x, y) + return true + } + // match: (SHRXQ x (NEGL (ADDLconst [c] y))) + // cond: c & 63 == 0 + // result: (SHRXQ x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHRXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXQ x (ANDLconst [c] y)) + // cond: c & 63 == 63 + // result: (SHRXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHRXQ) + v.AddArg2(x, y) + return true + } + // match: (SHRXQ x (NEGL (ANDLconst [c] y))) + // cond: c & 63 == 63 + // result: (SHRXQ x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHRXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXQ l:(MOVQload [off] {sym} ptr mem) x) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (SHRXQload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVQload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHRXQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + return false +} func rewriteValueAMD64_OpAMD64SUBL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -27374,6 +29486,25 @@ } break } + // match: (XORL (SHLXL (MOVLconst [1]) y) x) + // result: (BTCL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTCL) + v.AddArg2(x, y) + return true + } + break + } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) @@ -27911,6 +30042,25 @@ } break } + // match: (XORQ (SHLXQ (MOVQconst [1]) y) x) + // result: (BTCQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXQ { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTCQ) + v.AddArg2(x, y) + return true + } + break + } // match: (XORQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCQconst [int8(log64(c))] x) @@ -34533,6 +36683,54 @@ } break } + // match: (EQ (TESTL (SHLXL (MOVLconst [1]) x) y)) + // result: (UGE (BTL x y)) + for b.Controls[0].Op == OpAMD64TESTL { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + break + } + // match: (EQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) + // result: (UGE (BTQ x y)) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + break + } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (UGE (BTLconst [int8(log32(c))] x)) @@ -35321,6 +37519,54 @@ v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + break + } + // match: (NE (TESTL (SHLXL (MOVLconst [1]) x) y)) + // result: (ULT (BTL x y)) + for b.Controls[0].Op == OpAMD64TESTL { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + break + } + // match: (NE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) + // result: (ULT (BTQ x y)) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXQ { continue } x := v_0_0.Args[1] -- diff -- # indent-heuristic: true @@ -442,6 +442,10 @@ return rewriteValueAMD64_OpAMD64SHLQ(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst(v) + case OpAMD64SHLXL: + return rewriteValueAMD64_OpAMD64SHLXL(v) + case OpAMD64SHLXQ: + return rewriteValueAMD64_OpAMD64SHLXQ(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB(v) case OpAMD64SHRBconst: @@ -458,6 +462,10 @@ return rewriteValueAMD64_OpAMD64SHRW(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst(v) + case OpAMD64SHRXL: + return rewriteValueAMD64_OpAMD64SHRXL(v) + case OpAMD64SHRXQ: + return rewriteValueAMD64_OpAMD64SHRXQ(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL(v) case OpAMD64SUBLconst: @@ -2704,6 +2712,29 @@ } break } + // match: (ANDL (NOTL (SHLXL (MOVLconst [1]) y)) x) + // result: (BTRL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64NOTL { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SHLXL { + continue + } + y := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTRL) + v.AddArg2(x, y) + return true + } + break + } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) @@ -3121,6 +3152,22 @@ v.AddArg2(x, y) return true } + // match: (ANDNL x (SHLXL (MOVLconst [1]) y)) + // result: (BTRL x y) + for { + x := v_0 + if v_1.Op != OpAMD64SHLXL { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0.AuxInt) != 1 { + break + } + v.reset(OpAMD64BTRL) + v.AddArg2(x, y) + return true + } return false } func rewriteValueAMD64_OpAMD64ANDNQ(v *Value) bool { @@ -3142,6 +3189,22 @@ v.AddArg2(x, y) return true } + // match: (ANDNQ x (SHLXQ (MOVQconst [1]) y)) + // result: (BTRQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64SHLXQ { + break + } + y := v_1.Args[1] + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0.AuxInt) != 1 { + break + } + v.reset(OpAMD64BTRQ) + v.AddArg2(x, y) + return true + } return false } func rewriteValueAMD64_OpAMD64ANDQ(v *Value) bool { @@ -3170,6 +3233,29 @@ } break } + // match: (ANDQ (NOTQ (SHLXQ (MOVQconst [1]) y)) x) + // result: (BTRQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64NOTQ { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SHLXQ { + continue + } + y := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTRQ) + v.AddArg2(x, y) + return true + } + break + } // match: (ANDQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRQconst [int8(log64(^c))] x) @@ -3873,6 +3959,22 @@ v.AddArg2(y, x) return true } + // match: (BTLconst [0] s:(SHRXQ x y)) + // result: (BTQ y x) + for { + if auxIntToInt8(v.AuxInt) != 0 { + break + } + s := v_0 + if s.Op != OpAMD64SHRXQ { + break + } + y := s.Args[1] + x := s.Args[0] + v.reset(OpAMD64BTQ) + v.AddArg2(y, x) + return true + } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) @@ -3925,6 +4027,22 @@ v.AddArg2(y, x) return true } + // match: (BTLconst [0] s:(SHRXL x y)) + // result: (BTL y x) + for { + if auxIntToInt8(v.AuxInt) != 0 { + break + } + s := v_0 + if s.Op != OpAMD64SHRXL { + break + } + y := s.Args[1] + x := s.Args[0] + v.reset(OpAMD64BTL) + v.AddArg2(y, x) + return true + } return false } func rewriteValueAMD64_OpAMD64BTQconst(v *Value) bool { @@ -3981,6 +4099,22 @@ v.AddArg2(y, x) return true } + // match: (BTQconst [0] s:(SHRXQ x y)) + // result: (BTQ y x) + for { + if auxIntToInt8(v.AuxInt) != 0 { + break + } + s := v_0 + if s.Op != OpAMD64SHRXQ { + break + } + y := s.Args[1] + x := s.Args[0] + v.reset(OpAMD64BTQ) + v.AddArg2(y, x) + return true + } return false } func rewriteValueAMD64_OpAMD64BTRLconst(v *Value) bool { @@ -15890,6 +16024,25 @@ } break } + // match: (ORL (SHLXL (MOVLconst [1]) y) x) + // result: (BTSL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTSL) + v.AddArg2(x, y) + return true + } + break + } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) @@ -16200,6 +16353,206 @@ } break } + // match: (ORL (SHLXL x y) (ANDL (SHRXL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) + // result: (ROLL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRXL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLL) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHLXL x y) (ANDL (SHRXL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) + // result: (ROLL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRXL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLL) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHRXL x y) (ANDL (SHLXL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) + // result: (RORL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRXL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORL) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHRXL x y) (ANDL (SHLXL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) + // result: (RORL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRXL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORL) + v.AddArg2(x, y) + return true + } + } + break + } // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) @@ -16408,6 +16761,214 @@ } break } + // match: (ORL (SHLXL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) + // cond: v.Type.Size() == 2 + // result: (ROLW x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRW { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64ROLW) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHLXL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) + // cond: v.Type.Size() == 2 + // result: (ROLW x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRW { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -16 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 15 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -16 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64ROLW) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHRW x (ANDQconst y [15])) (SHLXL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) + // cond: v.Type.Size() == 2 + // result: (RORW x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 15 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64SHLXL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGQ { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64RORW) + v.AddArg2(x, y) + return true + } + break + } + // match: (ORL (SHRW x (ANDLconst y [15])) (SHLXL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) + // cond: v.Type.Size() == 2 + // result: (RORW x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 15 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64SHLXL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGL { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64RORW) + v.AddArg2(x, y) + return true + } + break + } // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) @@ -16616,6 +17177,214 @@ } break } + // match: (ORL (SHLXL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) + // cond: v.Type.Size() == 1 + // result: (ROLB x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRB { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64ROLB) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHLXL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) + // cond: v.Type.Size() == 1 + // result: (ROLB x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRB { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_0_1_0.AuxInt) != -8 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_0_1_0_0.AuxInt) != 7 || y != v_1_0_1_0_0.Args[0] || v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -8 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64ROLB) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLXL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) + // cond: v.Type.Size() == 1 + // result: (RORB x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRB { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || auxIntToInt32(v_0_1.AuxInt) != 7 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64SHLXL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGQ { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64RORB) + v.AddArg2(x, y) + return true + } + break + } + // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLXL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) + // cond: v.Type.Size() == 1 + // result: (RORB x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRB { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || auxIntToInt32(v_0_1.AuxInt) != 7 { + continue + } + y := v_0_1.Args[0] + if v_1.Op != OpAMD64SHLXL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGL { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0.AuxInt) != -8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0.AuxInt) != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64RORB) + v.AddArg2(x, y) + return true + } + break + } // match: (ORL x x) // result: x for { @@ -17509,6 +18278,25 @@ } break } + // match: (ORQ (SHLXQ (MOVQconst [1]) y) x) + // result: (BTSQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXQ { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTSQ) + v.AddArg2(x, y) + return true + } + break + } // match: (ORQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSQconst [int8(log64(c))] x) @@ -17789,6 +18577,206 @@ } break } + // match: (ORQ (SHLXQ x y) (ANDQ (SHRXQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) + // result: (ROLQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRXQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLQ) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORQ (SHLXQ x y) (ANDQ (SHRXQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) + // result: (ROLQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHRXQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLQ) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORQ (SHRXQ x y) (ANDQ (SHLXQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) + // result: (RORQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRXQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORQ) + v.AddArg2(x, y) + return true + } + } + break + } + // match: (ORQ (SHRXQ x y) (ANDQ (SHLXQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) + // result: (RORQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRXQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] || v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_1_1_0.AuxInt) != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || auxIntToInt32(v_1_1_0_0_0.AuxInt) != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || auxIntToInt32(v_1_1_0_0_0_0.AuxInt) != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORQ) + v.AddArg2(x, y) + return true + } + } + break + } // match: (ORQ (SHRQ lo bits) (SHLQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { @@ -17837,6 +18825,54 @@ } break } + // match: (ORQ (SHRXQ lo bits) (SHLXQ hi (NEGQ bits))) + // result: (SHRDQ lo hi bits) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHRXQ { + continue + } + bits := v_0.Args[1] + lo := v_0.Args[0] + if v_1.Op != OpAMD64SHLXQ { + continue + } + _ = v_1.Args[1] + hi := v_1.Args[0] + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { + continue + } + v.reset(OpAMD64SHRDQ) + v.AddArg3(lo, hi, bits) + return true + } + break + } + // match: (ORQ (SHLXQ lo bits) (SHRXQ hi (NEGQ bits))) + // result: (SHLDQ lo hi bits) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXQ { + continue + } + bits := v_0.Args[1] + lo := v_0.Args[0] + if v_1.Op != OpAMD64SHRXQ { + continue + } + _ = v_1.Args[1] + hi := v_1.Args[0] + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { + continue + } + v.reset(OpAMD64SHLDQ) + v.AddArg3(lo, hi, bits) + return true + } + break + } // match: (ORQ (MOVQconst [c]) (MOVQconst [d])) // result: (MOVQconst [c|d]) for { @@ -22062,6 +23098,60 @@ } break } + // match: (SETEQ (TESTL (SHLXL (MOVLconst [1]) x) y)) + // result: (SETAE (BTL x y)) + for { + if v_0.Op != OpAMD64TESTL { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (SETEQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) + // result: (SETAE (BTQ x y)) + for { + if v_0.Op != OpAMD64TESTQ { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAE (BTLconst [int8(log32(c))] x)) @@ -22487,6 +23577,72 @@ } break } + // match: (SETEQstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) + // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTL { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXL { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { + continue + } + y := v_1_1 + mem := v_2 + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg3(ptr, v0, mem) + return true + } + break + } + // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) + // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXQ { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { + continue + } + y := v_1_1 + mem := v_2 + v.reset(OpAMD64SETAEstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg3(ptr, v0, mem) + return true + } + break + } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) @@ -23978,6 +25134,60 @@ } break } + // match: (SETNE (TESTL (SHLXL (MOVLconst [1]) x) y)) + // result: (SETB (BTL x y)) + for { + if v_0.Op != OpAMD64TESTL { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } + // match: (SETNE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) + // result: (SETB (BTQ x y)) + for { + if v_0.Op != OpAMD64TESTQ { + break + } + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } + break + } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETB (BTLconst [int8(log32(c))] x)) @@ -24403,6 +25613,72 @@ } break } + // match: (SETNEstore [off] {sym} ptr (TESTL (SHLXL (MOVLconst [1]) x) y) mem) + // result: (SETBstore [off] {sym} ptr (BTL x y) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTL { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXL { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { + continue + } + y := v_1_1 + mem := v_2 + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg3(ptr, v0, mem) + return true + } + break + } + // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLXQ (MOVQconst [1]) x) y) mem) + // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) + for { + off := auxIntToInt32(v.AuxInt) + sym := auxToSym(v.Aux) + ptr := v_0 + if v_1.Op != OpAMD64TESTQ { + break + } + _ = v_1.Args[1] + v_1_0 := v_1.Args[0] + v_1_1 := v_1.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { + if v_1_0.Op != OpAMD64SHLXQ { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { + continue + } + y := v_1_1 + mem := v_2 + v.reset(OpAMD64SETBstore) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg3(ptr, v0, mem) + return true + } + break + } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) @@ -24917,6 +26193,19 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + // match: (SHLL x y) + // cond: buildcfg.GOAMD64 >= 3 + // result: (SHLXL x y) + for { + x := v_0 + y := v_1 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64SHLXL) + v.AddArg2(x, y) + return true + } // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { @@ -25107,28 +26396,6 @@ v.AddArg2(x, v0) return true } - // match: (SHLL l:(MOVLload [off] {sym} ptr mem) x) - // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SHLXLload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVLload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHLXLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { @@ -25173,6 +26440,19 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + // match: (SHLQ x y) + // cond: buildcfg.GOAMD64 >= 3 + // result: (SHLXQ x y) + for { + x := v_0 + y := v_1 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64SHLXQ) + v.AddArg2(x, y) + return true + } // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { @@ -25363,28 +26643,6 @@ v.AddArg2(x, v0) return true } - // match: (SHLQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SHLXQload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHLXQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { @@ -25437,6 +26695,442 @@ } return false } +func rewriteValueAMD64_OpAMD64SHLXL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (SHLXL x (MOVQconst [c])) + // result: (SHLLconst [int8(c&31)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64SHLLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) + return true + } + // match: (SHLXL x (MOVLconst [c])) + // result: (SHLLconst [int8(c&31)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64SHLLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) + return true + } + // match: (SHLXL x (ADDQconst [c] y)) + // cond: c & 31 == 0 + // result: (SHLXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHLXL) + v.AddArg2(x, y) + return true + } + // match: (SHLXL x (NEGQ (ADDQconst [c] y))) + // cond: c & 31 == 0 + // result: (SHLXL x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHLXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXL x (ANDQconst [c] y)) + // cond: c & 31 == 31 + // result: (SHLXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHLXL) + v.AddArg2(x, y) + return true + } + // match: (SHLXL x (NEGQ (ANDQconst [c] y))) + // cond: c & 31 == 31 + // result: (SHLXL x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHLXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXL x (ADDLconst [c] y)) + // cond: c & 31 == 0 + // result: (SHLXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHLXL) + v.AddArg2(x, y) + return true + } + // match: (SHLXL x (NEGL (ADDLconst [c] y))) + // cond: c & 31 == 0 + // result: (SHLXL x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHLXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXL x (ANDLconst [c] y)) + // cond: c & 31 == 31 + // result: (SHLXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHLXL) + v.AddArg2(x, y) + return true + } + // match: (SHLXL x (NEGL (ANDLconst [c] y))) + // cond: c & 31 == 31 + // result: (SHLXL x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHLXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXL l:(MOVLload [off] {sym} ptr mem) x) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (SHLXLload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVLload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHLXLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SHLXQ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (SHLXQ x (MOVQconst [c])) + // result: (SHLQconst [int8(c&63)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64SHLQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v.AddArg(x) + return true + } + // match: (SHLXQ x (MOVLconst [c])) + // result: (SHLQconst [int8(c&63)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64SHLQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v.AddArg(x) + return true + } + // match: (SHLXQ x (ADDQconst [c] y)) + // cond: c & 63 == 0 + // result: (SHLXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHLXQ) + v.AddArg2(x, y) + return true + } + // match: (SHLXQ x (NEGQ (ADDQconst [c] y))) + // cond: c & 63 == 0 + // result: (SHLXQ x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHLXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXQ x (ANDQconst [c] y)) + // cond: c & 63 == 63 + // result: (SHLXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHLXQ) + v.AddArg2(x, y) + return true + } + // match: (SHLXQ x (NEGQ (ANDQconst [c] y))) + // cond: c & 63 == 63 + // result: (SHLXQ x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHLXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXQ x (ADDLconst [c] y)) + // cond: c & 63 == 0 + // result: (SHLXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHLXQ) + v.AddArg2(x, y) + return true + } + // match: (SHLXQ x (NEGL (ADDLconst [c] y))) + // cond: c & 63 == 0 + // result: (SHLXQ x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHLXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXQ x (ANDLconst [c] y)) + // cond: c & 63 == 63 + // result: (SHLXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHLXQ) + v.AddArg2(x, y) + return true + } + // match: (SHLXQ x (NEGL (ANDLconst [c] y))) + // cond: c & 63 == 63 + // result: (SHLXQ x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHLXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHLXQ l:(MOVQload [off] {sym} ptr mem) x) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (SHLXQload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVQload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHLXQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + return false +} func rewriteValueAMD64_OpAMD64SHRB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -25524,6 +27218,19 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + // match: (SHRL x y) + // cond: buildcfg.GOAMD64 >= 3 + // result: (SHRXL x y) + for { + x := v_0 + y := v_1 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64SHRXL) + v.AddArg2(x, y) + return true + } // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { @@ -25714,28 +27421,6 @@ v.AddArg2(x, v0) return true } - // match: (SHRL l:(MOVLload [off] {sym} ptr mem) x) - // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SHRXLload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVLload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHRXLload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { @@ -25768,6 +27453,19 @@ v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block + // match: (SHRQ x y) + // cond: buildcfg.GOAMD64 >= 3 + // result: (SHRXQ x y) + for { + x := v_0 + y := v_1 + if !(buildcfg.GOAMD64 >= 3) { + break + } + v.reset(OpAMD64SHRXQ) + v.AddArg2(x, y) + return true + } // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { @@ -25958,28 +27656,6 @@ v.AddArg2(x, v0) return true } - // match: (SHRQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) - // result: (SHRXQload [off] {sym} ptr x mem) - for { - l := v_0 - if l.Op != OpAMD64MOVQload { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - x := v_1 - if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64SHRXQload) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(ptr, x, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { @@ -26091,6 +27767,442 @@ } return false } +func rewriteValueAMD64_OpAMD64SHRXL(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (SHRXL x (MOVQconst [c])) + // result: (SHRLconst [int8(c&31)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64SHRLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) + return true + } + // match: (SHRXL x (MOVLconst [c])) + // result: (SHRLconst [int8(c&31)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64SHRLconst) + v.AuxInt = int8ToAuxInt(int8(c & 31)) + v.AddArg(x) + return true + } + // match: (SHRXL x (ADDQconst [c] y)) + // cond: c & 31 == 0 + // result: (SHRXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHRXL) + v.AddArg2(x, y) + return true + } + // match: (SHRXL x (NEGQ (ADDQconst [c] y))) + // cond: c & 31 == 0 + // result: (SHRXL x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHRXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXL x (ANDQconst [c] y)) + // cond: c & 31 == 31 + // result: (SHRXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHRXL) + v.AddArg2(x, y) + return true + } + // match: (SHRXL x (NEGQ (ANDQconst [c] y))) + // cond: c & 31 == 31 + // result: (SHRXL x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHRXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXL x (ADDLconst [c] y)) + // cond: c & 31 == 0 + // result: (SHRXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHRXL) + v.AddArg2(x, y) + return true + } + // match: (SHRXL x (NEGL (ADDLconst [c] y))) + // cond: c & 31 == 0 + // result: (SHRXL x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 0) { + break + } + v.reset(OpAMD64SHRXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXL x (ANDLconst [c] y)) + // cond: c & 31 == 31 + // result: (SHRXL x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHRXL) + v.AddArg2(x, y) + return true + } + // match: (SHRXL x (NEGL (ANDLconst [c] y))) + // cond: c & 31 == 31 + // result: (SHRXL x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&31 == 31) { + break + } + v.reset(OpAMD64SHRXL) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXL l:(MOVLload [off] {sym} ptr mem) x) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (SHRXLload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVLload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHRXLload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64SHRXQ(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (SHRXQ x (MOVQconst [c])) + // result: (SHRQconst [int8(c&63)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVQconst { + break + } + c := auxIntToInt64(v_1.AuxInt) + v.reset(OpAMD64SHRQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v.AddArg(x) + return true + } + // match: (SHRXQ x (MOVLconst [c])) + // result: (SHRQconst [int8(c&63)] x) + for { + x := v_0 + if v_1.Op != OpAMD64MOVLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + v.reset(OpAMD64SHRQconst) + v.AuxInt = int8ToAuxInt(int8(c & 63)) + v.AddArg(x) + return true + } + // match: (SHRXQ x (ADDQconst [c] y)) + // cond: c & 63 == 0 + // result: (SHRXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHRXQ) + v.AddArg2(x, y) + return true + } + // match: (SHRXQ x (NEGQ (ADDQconst [c] y))) + // cond: c & 63 == 0 + // result: (SHRXQ x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHRXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXQ x (ANDQconst [c] y)) + // cond: c & 63 == 63 + // result: (SHRXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHRXQ) + v.AddArg2(x, y) + return true + } + // match: (SHRXQ x (NEGQ (ANDQconst [c] y))) + // cond: c & 63 == 63 + // result: (SHRXQ x (NEGQ y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGQ { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDQconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHRXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXQ x (ADDLconst [c] y)) + // cond: c & 63 == 0 + // result: (SHRXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHRXQ) + v.AddArg2(x, y) + return true + } + // match: (SHRXQ x (NEGL (ADDLconst [c] y))) + // cond: c & 63 == 0 + // result: (SHRXQ x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ADDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 0) { + break + } + v.reset(OpAMD64SHRXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXQ x (ANDLconst [c] y)) + // cond: c & 63 == 63 + // result: (SHRXQ x y) + for { + x := v_0 + if v_1.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1.AuxInt) + y := v_1.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHRXQ) + v.AddArg2(x, y) + return true + } + // match: (SHRXQ x (NEGL (ANDLconst [c] y))) + // cond: c & 63 == 63 + // result: (SHRXQ x (NEGL y)) + for { + x := v_0 + if v_1.Op != OpAMD64NEGL { + break + } + t := v_1.Type + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpAMD64ANDLconst { + break + } + c := auxIntToInt32(v_1_0.AuxInt) + y := v_1_0.Args[0] + if !(c&63 == 63) { + break + } + v.reset(OpAMD64SHRXQ) + v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) + v0.AddArg(y) + v.AddArg2(x, v0) + return true + } + // match: (SHRXQ l:(MOVQload [off] {sym} ptr mem) x) + // cond: canMergeLoad(v, l) && clobber(l) + // result: (SHRXQload [off] {sym} ptr x mem) + for { + l := v_0 + if l.Op != OpAMD64MOVQload { + break + } + off := auxIntToInt32(l.AuxInt) + sym := auxToSym(l.Aux) + mem := l.Args[1] + ptr := l.Args[0] + x := v_1 + if !(canMergeLoad(v, l) && clobber(l)) { + break + } + v.reset(OpAMD64SHRXQload) + v.AuxInt = int32ToAuxInt(off) + v.Aux = symToAux(sym) + v.AddArg3(ptr, x, mem) + return true + } + return false +} func rewriteValueAMD64_OpAMD64SUBL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -27374,6 +29486,25 @@ } break } + // match: (XORL (SHLXL (MOVLconst [1]) y) x) + // result: (BTCL x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXL { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTCL) + v.AddArg2(x, y) + return true + } + break + } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) @@ -27911,6 +30042,25 @@ } break } + // match: (XORQ (SHLXQ (MOVQconst [1]) y) x) + // result: (BTCQ x y) + for { + for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { + if v_0.Op != OpAMD64SHLXQ { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 1 { + continue + } + x := v_1 + v.reset(OpAMD64BTCQ) + v.AddArg2(x, y) + return true + } + break + } // match: (XORQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCQconst [int8(log64(c))] x) @@ -34533,6 +36683,54 @@ } break } + // match: (EQ (TESTL (SHLXL (MOVLconst [1]) x) y)) + // result: (UGE (BTL x y)) + for b.Controls[0].Op == OpAMD64TESTL { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + break + } + // match: (EQ (TESTQ (SHLXQ (MOVQconst [1]) x) y)) + // result: (UGE (BTQ x y)) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + b.resetWithControl(BlockAMD64UGE, v0) + return true + } + break + } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (UGE (BTLconst [int8(log32(c))] x)) @@ -35336,6 +37534,54 @@ } break } + // match: (NE (TESTL (SHLXL (MOVLconst [1]) x) y)) + // result: (ULT (BTL x y)) + for b.Controls[0].Op == OpAMD64TESTL { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg2(x, y) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + break + } + // match: (NE (TESTQ (SHLXQ (MOVQconst [1]) x) y)) + // result: (ULT (BTQ x y)) + for b.Controls[0].Op == OpAMD64TESTQ { + v_0 := b.Controls[0] + _ = v_0.Args[1] + v_0_0 := v_0.Args[0] + v_0_1 := v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { + if v_0_0.Op != OpAMD64SHLXQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { + continue + } + y := v_0_1 + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg2(x, y) + b.resetWithControl(BlockAMD64ULT, v0) + return true + } + break + } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (ULT (BTLconst [int8(log32(c))] x)) 2414476de6b831d0b305bfb6a79afabf8a73c601.paxheader00006660000000000000000000000215151600170720020554xustar00rootroot00000000000000141 path=diff-1.0.1/textdiff/testdata/go_78eadf5b3de568297456fe137b65ff16e8cc8bb6_src_cmd_vendor_golang.org_x_sync_errgroup_errgroup.go.test 2414476de6b831d0b305bfb6a79afabf8a73c601.data000066400000000000000000000512061516001707200174200ustar00rootroot00000000000000From https://go.googlesource.com/go commit 78eadf5b3de568297456fe137b65ff16e8cc8bb6 file src/cmd/vendor/golang.org/x/sync/errgroup/errgroup.go -- x -- // Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // Package errgroup provides synchronization, error propagation, and Context // cancelation for groups of goroutines working on subtasks of a common task. // // [errgroup.Group] is related to [sync.WaitGroup] but adds handling of tasks // returning errors. package errgroup import ( "context" "fmt" "sync" ) type token struct{} // A Group is a collection of goroutines working on subtasks that are part of // the same overall task. A Group should not be reused for different tasks. // // A zero Group is valid, has no limit on the number of active goroutines, // and does not cancel on error. type Group struct { cancel func(error) wg sync.WaitGroup sem chan token errOnce sync.Once err error } func (g *Group) done() { if g.sem != nil { <-g.sem } g.wg.Done() } // WithContext returns a new Group and an associated Context derived from ctx. // // The derived Context is canceled the first time a function passed to Go // returns a non-nil error or the first time Wait returns, whichever occurs // first. func WithContext(ctx context.Context) (*Group, context.Context) { ctx, cancel := context.WithCancelCause(ctx) return &Group{cancel: cancel}, ctx } // Wait blocks until all function calls from the Go method have returned, then // returns the first non-nil error (if any) from them. func (g *Group) Wait() error { g.wg.Wait() if g.cancel != nil { g.cancel(g.err) } return g.err } // Go calls the given function in a new goroutine. // The first call to Go must happen before a Wait. // It blocks until the new goroutine can be added without the number of // active goroutines in the group exceeding the configured limit. // // The first call to return a non-nil error cancels the group's context, if the // group was created by calling WithContext. The error will be returned by Wait. func (g *Group) Go(f func() error) { if g.sem != nil { g.sem <- token{} } g.wg.Add(1) go func() { defer g.done() if err := f(); err != nil { g.errOnce.Do(func() { g.err = err if g.cancel != nil { g.cancel(g.err) } }) } }() } // TryGo calls the given function in a new goroutine only if the number of // active goroutines in the group is currently below the configured limit. // // The return value reports whether the goroutine was started. func (g *Group) TryGo(f func() error) bool { if g.sem != nil { select { case g.sem <- token{}: // Note: this allows barging iff channels in general allow barging. default: return false } } g.wg.Add(1) go func() { defer g.done() if err := f(); err != nil { g.errOnce.Do(func() { g.err = err if g.cancel != nil { g.cancel(g.err) } }) } }() return true } // SetLimit limits the number of active goroutines in this group to at most n. // A negative value indicates no limit. // A limit of zero will prevent any new goroutines from being added. // // Any subsequent call to the Go method will block until it can add an active // goroutine without exceeding the configured limit. // // The limit must not be modified while any goroutines in the group are active. func (g *Group) SetLimit(n int) { if n < 0 { g.sem = nil return } if len(g.sem) != 0 { panic(fmt.Errorf("errgroup: modify limit while %v goroutines in the group are still active", len(g.sem))) } g.sem = make(chan token, n) } -- y -- // Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // Package errgroup provides synchronization, error propagation, and Context // cancelation for groups of goroutines working on subtasks of a common task. // // [errgroup.Group] is related to [sync.WaitGroup] but adds handling of tasks // returning errors. package errgroup import ( "context" "fmt" "runtime" "runtime/debug" "sync" ) type token struct{} // A Group is a collection of goroutines working on subtasks that are part of // the same overall task. A Group should not be reused for different tasks. // // A zero Group is valid, has no limit on the number of active goroutines, // and does not cancel on error. type Group struct { cancel func(error) wg sync.WaitGroup sem chan token errOnce sync.Once err error mu sync.Mutex panicValue any // = PanicError | PanicValue; non-nil if some Group.Go goroutine panicked. abnormal bool // some Group.Go goroutine terminated abnormally (panic or goexit). } func (g *Group) done() { if g.sem != nil { <-g.sem } g.wg.Done() } // WithContext returns a new Group and an associated Context derived from ctx. // // The derived Context is canceled the first time a function passed to Go // returns a non-nil error or the first time Wait returns, whichever occurs // first. func WithContext(ctx context.Context) (*Group, context.Context) { ctx, cancel := context.WithCancelCause(ctx) return &Group{cancel: cancel}, ctx } // Wait blocks until all function calls from the Go method have returned // normally, then returns the first non-nil error (if any) from them. // // If any of the calls panics, Wait panics with a [PanicValue]; // and if any of them calls [runtime.Goexit], Wait calls runtime.Goexit. func (g *Group) Wait() error { g.wg.Wait() if g.cancel != nil { g.cancel(g.err) } if g.panicValue != nil { panic(g.panicValue) } if g.abnormal { runtime.Goexit() } return g.err } // Go calls the given function in a new goroutine. // // The first call to Go must happen before a Wait. // It blocks until the new goroutine can be added without the number of // goroutines in the group exceeding the configured limit. // // The first goroutine in the group that returns a non-nil error, panics, or // invokes [runtime.Goexit] will cancel the associated Context, if any. func (g *Group) Go(f func() error) { if g.sem != nil { g.sem <- token{} } g.add(f) } func (g *Group) add(f func() error) { g.wg.Add(1) go func() { defer g.done() normalReturn := false defer func() { if normalReturn { return } v := recover() g.mu.Lock() defer g.mu.Unlock() if !g.abnormal { if g.cancel != nil { g.cancel(g.err) } g.abnormal = true } if v != nil && g.panicValue == nil { switch v := v.(type) { case error: g.panicValue = PanicError{ Recovered: v, Stack: debug.Stack(), } default: g.panicValue = PanicValue{ Recovered: v, Stack: debug.Stack(), } } } }() err := f() normalReturn = true if err != nil { g.errOnce.Do(func() { g.err = err if g.cancel != nil { g.cancel(g.err) } }) } }() } // TryGo calls the given function in a new goroutine only if the number of // active goroutines in the group is currently below the configured limit. // // The return value reports whether the goroutine was started. func (g *Group) TryGo(f func() error) bool { if g.sem != nil { select { case g.sem <- token{}: // Note: this allows barging iff channels in general allow barging. default: return false } } g.add(f) return true } // SetLimit limits the number of active goroutines in this group to at most n. // A negative value indicates no limit. // A limit of zero will prevent any new goroutines from being added. // // Any subsequent call to the Go method will block until it can add an active // goroutine without exceeding the configured limit. // // The limit must not be modified while any goroutines in the group are active. func (g *Group) SetLimit(n int) { if n < 0 { g.sem = nil return } if len(g.sem) != 0 { panic(fmt.Errorf("errgroup: modify limit while %v goroutines in the group are still active", len(g.sem))) } g.sem = make(chan token, n) } // PanicError wraps an error recovered from an unhandled panic // when calling a function passed to Go or TryGo. type PanicError struct { Recovered error Stack []byte // result of call to [debug.Stack] } func (p PanicError) Error() string { if len(p.Stack) > 0 { return fmt.Sprintf("recovered from errgroup.Group: %v\n%s", p.Recovered, p.Stack) } return fmt.Sprintf("recovered from errgroup.Group: %v", p.Recovered) } func (p PanicError) Unwrap() error { return p.Recovered } // PanicValue wraps a value that does not implement the error interface, // recovered from an unhandled panic when calling a function passed to Go or // TryGo. type PanicValue struct { Recovered any Stack []byte // result of call to [debug.Stack] } func (p PanicValue) String() string { if len(p.Stack) > 0 { return fmt.Sprintf("recovered from errgroup.Group: %v\n%s", p.Recovered, p.Stack) } return fmt.Sprintf("recovered from errgroup.Group: %v", p.Recovered) } -- diff -- @@ -12,6 +12,8 @@ import ( "context" "fmt" + "runtime" + "runtime/debug" "sync" ) @@ -31,6 +33,10 @@ errOnce sync.Once err error + + mu sync.Mutex + panicValue any // = PanicError | PanicValue; non-nil if some Group.Go goroutine panicked. + abnormal bool // some Group.Go goroutine terminated abnormally (panic or goexit). } func (g *Group) done() { @@ -50,33 +56,78 @@ return &Group{cancel: cancel}, ctx } -// Wait blocks until all function calls from the Go method have returned, then -// returns the first non-nil error (if any) from them. +// Wait blocks until all function calls from the Go method have returned +// normally, then returns the first non-nil error (if any) from them. +// +// If any of the calls panics, Wait panics with a [PanicValue]; +// and if any of them calls [runtime.Goexit], Wait calls runtime.Goexit. func (g *Group) Wait() error { g.wg.Wait() if g.cancel != nil { g.cancel(g.err) } + if g.panicValue != nil { + panic(g.panicValue) + } + if g.abnormal { + runtime.Goexit() + } return g.err } // Go calls the given function in a new goroutine. +// // The first call to Go must happen before a Wait. // It blocks until the new goroutine can be added without the number of -// active goroutines in the group exceeding the configured limit. +// goroutines in the group exceeding the configured limit. // -// The first call to return a non-nil error cancels the group's context, if the -// group was created by calling WithContext. The error will be returned by Wait. +// The first goroutine in the group that returns a non-nil error, panics, or +// invokes [runtime.Goexit] will cancel the associated Context, if any. func (g *Group) Go(f func() error) { if g.sem != nil { g.sem <- token{} } + g.add(f) +} + +func (g *Group) add(f func() error) { g.wg.Add(1) go func() { defer g.done() + normalReturn := false + defer func() { + if normalReturn { + return + } + v := recover() + g.mu.Lock() + defer g.mu.Unlock() + if !g.abnormal { + if g.cancel != nil { + g.cancel(g.err) + } + g.abnormal = true + } + if v != nil && g.panicValue == nil { + switch v := v.(type) { + case error: + g.panicValue = PanicError{ + Recovered: v, + Stack: debug.Stack(), + } + default: + g.panicValue = PanicValue{ + Recovered: v, + Stack: debug.Stack(), + } + } + } + }() - if err := f(); err != nil { + err := f() + normalReturn = true + if err != nil { g.errOnce.Do(func() { g.err = err if g.cancel != nil { @@ -100,20 +151,8 @@ return false } } - - g.wg.Add(1) - go func() { - defer g.done() - if err := f(); err != nil { - g.errOnce.Do(func() { - g.err = err - if g.cancel != nil { - g.cancel(g.err) - } - }) - } - }() + g.add(f) return true } @@ -134,4 +173,35 @@ panic(fmt.Errorf("errgroup: modify limit while %v goroutines in the group are still active", len(g.sem))) } g.sem = make(chan token, n) +} + +// PanicError wraps an error recovered from an unhandled panic +// when calling a function passed to Go or TryGo. +type PanicError struct { + Recovered error + Stack []byte // result of call to [debug.Stack] +} + +func (p PanicError) Error() string { + if len(p.Stack) > 0 { + return fmt.Sprintf("recovered from errgroup.Group: %v\n%s", p.Recovered, p.Stack) + } + return fmt.Sprintf("recovered from errgroup.Group: %v", p.Recovered) +} + +func (p PanicError) Unwrap() error { return p.Recovered } + +// PanicValue wraps a value that does not implement the error interface, +// recovered from an unhandled panic when calling a function passed to Go or +// TryGo. +type PanicValue struct { + Recovered any + Stack []byte // result of call to [debug.Stack] +} + +func (p PanicValue) String() string { + if len(p.Stack) > 0 { + return fmt.Sprintf("recovered from errgroup.Group: %v\n%s", p.Recovered, p.Stack) + } + return fmt.Sprintf("recovered from errgroup.Group: %v", p.Recovered) } -- diff -- # indent-heuristic: true @@ -12,6 +12,8 @@ import ( "context" "fmt" + "runtime" + "runtime/debug" "sync" ) @@ -31,6 +33,10 @@ errOnce sync.Once err error + + mu sync.Mutex + panicValue any // = PanicError | PanicValue; non-nil if some Group.Go goroutine panicked. + abnormal bool // some Group.Go goroutine terminated abnormally (panic or goexit). } func (g *Group) done() { @@ -50,33 +56,78 @@ return &Group{cancel: cancel}, ctx } -// Wait blocks until all function calls from the Go method have returned, then -// returns the first non-nil error (if any) from them. +// Wait blocks until all function calls from the Go method have returned +// normally, then returns the first non-nil error (if any) from them. +// +// If any of the calls panics, Wait panics with a [PanicValue]; +// and if any of them calls [runtime.Goexit], Wait calls runtime.Goexit. func (g *Group) Wait() error { g.wg.Wait() if g.cancel != nil { g.cancel(g.err) } + if g.panicValue != nil { + panic(g.panicValue) + } + if g.abnormal { + runtime.Goexit() + } return g.err } // Go calls the given function in a new goroutine. +// // The first call to Go must happen before a Wait. // It blocks until the new goroutine can be added without the number of -// active goroutines in the group exceeding the configured limit. +// goroutines in the group exceeding the configured limit. // -// The first call to return a non-nil error cancels the group's context, if the -// group was created by calling WithContext. The error will be returned by Wait. +// The first goroutine in the group that returns a non-nil error, panics, or +// invokes [runtime.Goexit] will cancel the associated Context, if any. func (g *Group) Go(f func() error) { if g.sem != nil { g.sem <- token{} } + g.add(f) +} + +func (g *Group) add(f func() error) { g.wg.Add(1) go func() { defer g.done() + normalReturn := false + defer func() { + if normalReturn { + return + } + v := recover() + g.mu.Lock() + defer g.mu.Unlock() + if !g.abnormal { + if g.cancel != nil { + g.cancel(g.err) + } + g.abnormal = true + } + if v != nil && g.panicValue == nil { + switch v := v.(type) { + case error: + g.panicValue = PanicError{ + Recovered: v, + Stack: debug.Stack(), + } + default: + g.panicValue = PanicValue{ + Recovered: v, + Stack: debug.Stack(), + } + } + } + }() - if err := f(); err != nil { + err := f() + normalReturn = true + if err != nil { g.errOnce.Do(func() { g.err = err if g.cancel != nil { @@ -101,19 +152,7 @@ } } - g.wg.Add(1) - go func() { - defer g.done() - - if err := f(); err != nil { - g.errOnce.Do(func() { - g.err = err - if g.cancel != nil { - g.cancel(g.err) - } - }) - } - }() + g.add(f) return true } @@ -135,3 +174,34 @@ } g.sem = make(chan token, n) } + +// PanicError wraps an error recovered from an unhandled panic +// when calling a function passed to Go or TryGo. +type PanicError struct { + Recovered error + Stack []byte // result of call to [debug.Stack] +} + +func (p PanicError) Error() string { + if len(p.Stack) > 0 { + return fmt.Sprintf("recovered from errgroup.Group: %v\n%s", p.Recovered, p.Stack) + } + return fmt.Sprintf("recovered from errgroup.Group: %v", p.Recovered) +} + +func (p PanicError) Unwrap() error { return p.Recovered } + +// PanicValue wraps a value that does not implement the error interface, +// recovered from an unhandled panic when calling a function passed to Go or +// TryGo. +type PanicValue struct { + Recovered any + Stack []byte // result of call to [debug.Stack] +} + +func (p PanicValue) String() string { + if len(p.Stack) > 0 { + return fmt.Sprintf("recovered from errgroup.Group: %v\n%s", p.Recovered, p.Stack) + } + return fmt.Sprintf("recovered from errgroup.Group: %v", p.Recovered) +} -- diff -- # fast: true @@ -12,6 +12,8 @@ import ( "context" "fmt" + "runtime" + "runtime/debug" "sync" ) @@ -31,6 +33,10 @@ errOnce sync.Once err error + + mu sync.Mutex + panicValue any // = PanicError | PanicValue; non-nil if some Group.Go goroutine panicked. + abnormal bool // some Group.Go goroutine terminated abnormally (panic or goexit). } func (g *Group) done() { @@ -50,33 +56,78 @@ return &Group{cancel: cancel}, ctx } -// Wait blocks until all function calls from the Go method have returned, then -// returns the first non-nil error (if any) from them. +// Wait blocks until all function calls from the Go method have returned +// normally, then returns the first non-nil error (if any) from them. +// +// If any of the calls panics, Wait panics with a [PanicValue]; +// and if any of them calls [runtime.Goexit], Wait calls runtime.Goexit. func (g *Group) Wait() error { g.wg.Wait() if g.cancel != nil { g.cancel(g.err) } + if g.panicValue != nil { + panic(g.panicValue) + } + if g.abnormal { + runtime.Goexit() + } return g.err } // Go calls the given function in a new goroutine. +// // The first call to Go must happen before a Wait. // It blocks until the new goroutine can be added without the number of -// active goroutines in the group exceeding the configured limit. +// goroutines in the group exceeding the configured limit. // -// The first call to return a non-nil error cancels the group's context, if the -// group was created by calling WithContext. The error will be returned by Wait. +// The first goroutine in the group that returns a non-nil error, panics, or +// invokes [runtime.Goexit] will cancel the associated Context, if any. func (g *Group) Go(f func() error) { if g.sem != nil { g.sem <- token{} } - g.wg.Add(1) - go func() { - defer g.done() + g.add(f) +} + +func (g *Group) add(f func() error) { + g.wg.Add(1) + go func() { + defer g.done() + normalReturn := false + defer func() { + if normalReturn { + return + } + v := recover() + g.mu.Lock() + defer g.mu.Unlock() + if !g.abnormal { + if g.cancel != nil { + g.cancel(g.err) + } + g.abnormal = true + } + if v != nil && g.panicValue == nil { + switch v := v.(type) { + case error: + g.panicValue = PanicError{ + Recovered: v, + Stack: debug.Stack(), + } + default: + g.panicValue = PanicValue{ + Recovered: v, + Stack: debug.Stack(), + } + } + } + }() - if err := f(); err != nil { + err := f() + normalReturn = true + if err != nil { g.errOnce.Do(func() { g.err = err if g.cancel != nil { @@ -101,19 +152,7 @@ } } - g.wg.Add(1) - go func() { - defer g.done() - - if err := f(); err != nil { - g.errOnce.Do(func() { - g.err = err - if g.cancel != nil { - g.cancel(g.err) - } - }) - } - }() + g.add(f) return true } @@ -134,4 +173,35 @@ panic(fmt.Errorf("errgroup: modify limit while %v goroutines in the group are still active", len(g.sem))) } g.sem = make(chan token, n) +} + +// PanicError wraps an error recovered from an unhandled panic +// when calling a function passed to Go or TryGo. +type PanicError struct { + Recovered error + Stack []byte // result of call to [debug.Stack] +} + +func (p PanicError) Error() string { + if len(p.Stack) > 0 { + return fmt.Sprintf("recovered from errgroup.Group: %v\n%s", p.Recovered, p.Stack) + } + return fmt.Sprintf("recovered from errgroup.Group: %v", p.Recovered) +} + +func (p PanicError) Unwrap() error { return p.Recovered } + +// PanicValue wraps a value that does not implement the error interface, +// recovered from an unhandled panic when calling a function passed to Go or +// TryGo. +type PanicValue struct { + Recovered any + Stack []byte // result of call to [debug.Stack] +} + +func (p PanicValue) String() string { + if len(p.Stack) > 0 { + return fmt.Sprintf("recovered from errgroup.Group: %v\n%s", p.Recovered, p.Stack) + } + return fmt.Sprintf("recovered from errgroup.Group: %v", p.Recovered) } ae28373911e89e9f988d0ea7c4c0ae868a77043d.paxheader00006660000000000000000000000225151600170720020464xustar00rootroot00000000000000149 path=diff-1.0.1/textdiff/testdata/go_78eadf5b3de568297456fe137b65ff16e8cc8bb6_src_cmd_vendor_golang.org_x_tools_internal_stdlib_manifest.go.test ae28373911e89e9f988d0ea7c4c0ae868a77043d.data000066400000000000000000164756261516001707200173560ustar00rootroot00000000000000From https://go.googlesource.com/go commit 78eadf5b3de568297456fe137b65ff16e8cc8bb6 file src/cmd/vendor/golang.org/x/tools/internal/stdlib/manifest.go -- x -- // Copyright 2025 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // Code generated by generate.go. DO NOT EDIT. package stdlib var PackageSymbols = map[string][]Symbol{ "archive/tar": { {"(*Header).FileInfo", Method, 1}, {"(*Reader).Next", Method, 0}, {"(*Reader).Read", Method, 0}, {"(*Writer).AddFS", Method, 22}, {"(*Writer).Close", Method, 0}, {"(*Writer).Flush", Method, 0}, {"(*Writer).Write", Method, 0}, {"(*Writer).WriteHeader", Method, 0}, {"(Format).String", Method, 10}, {"ErrFieldTooLong", Var, 0}, {"ErrHeader", Var, 0}, {"ErrInsecurePath", Var, 20}, {"ErrWriteAfterClose", Var, 0}, {"ErrWriteTooLong", Var, 0}, {"FileInfoHeader", Func, 1}, {"FileInfoNames", Type, 23}, {"Format", Type, 10}, {"FormatGNU", Const, 10}, {"FormatPAX", Const, 10}, {"FormatUSTAR", Const, 10}, {"FormatUnknown", Const, 10}, {"Header", Type, 0}, {"Header.AccessTime", Field, 0}, {"Header.ChangeTime", Field, 0}, {"Header.Devmajor", Field, 0}, {"Header.Devminor", Field, 0}, {"Header.Format", Field, 10}, {"Header.Gid", Field, 0}, {"Header.Gname", Field, 0}, {"Header.Linkname", Field, 0}, {"Header.ModTime", Field, 0}, {"Header.Mode", Field, 0}, {"Header.Name", Field, 0}, {"Header.PAXRecords", Field, 10}, {"Header.Size", Field, 0}, {"Header.Typeflag", Field, 0}, {"Header.Uid", Field, 0}, {"Header.Uname", Field, 0}, {"Header.Xattrs", Field, 3}, {"NewReader", Func, 0}, {"NewWriter", Func, 0}, {"Reader", Type, 0}, {"TypeBlock", Const, 0}, {"TypeChar", Const, 0}, {"TypeCont", Const, 0}, {"TypeDir", Const, 0}, {"TypeFifo", Const, 0}, {"TypeGNULongLink", Const, 1}, {"TypeGNULongName", Const, 1}, {"TypeGNUSparse", Const, 3}, {"TypeLink", Const, 0}, {"TypeReg", Const, 0}, {"TypeRegA", Const, 0}, {"TypeSymlink", Const, 0}, {"TypeXGlobalHeader", Const, 0}, {"TypeXHeader", Const, 0}, {"Writer", Type, 0}, }, "archive/zip": { {"(*File).DataOffset", Method, 2}, {"(*File).FileInfo", Method, 0}, {"(*File).ModTime", Method, 0}, {"(*File).Mode", Method, 0}, {"(*File).Open", Method, 0}, {"(*File).OpenRaw", Method, 17}, {"(*File).SetModTime", Method, 0}, {"(*File).SetMode", Method, 0}, {"(*FileHeader).FileInfo", Method, 0}, {"(*FileHeader).ModTime", Method, 0}, {"(*FileHeader).Mode", Method, 0}, {"(*FileHeader).SetModTime", Method, 0}, {"(*FileHeader).SetMode", Method, 0}, {"(*ReadCloser).Close", Method, 0}, {"(*ReadCloser).Open", Method, 16}, {"(*ReadCloser).RegisterDecompressor", Method, 6}, {"(*Reader).Open", Method, 16}, {"(*Reader).RegisterDecompressor", Method, 6}, {"(*Writer).AddFS", Method, 22}, {"(*Writer).Close", Method, 0}, {"(*Writer).Copy", Method, 17}, {"(*Writer).Create", Method, 0}, {"(*Writer).CreateHeader", Method, 0}, {"(*Writer).CreateRaw", Method, 17}, {"(*Writer).Flush", Method, 4}, {"(*Writer).RegisterCompressor", Method, 6}, {"(*Writer).SetComment", Method, 10}, {"(*Writer).SetOffset", Method, 5}, {"Compressor", Type, 2}, {"Decompressor", Type, 2}, {"Deflate", Const, 0}, {"ErrAlgorithm", Var, 0}, {"ErrChecksum", Var, 0}, {"ErrFormat", Var, 0}, {"ErrInsecurePath", Var, 20}, {"File", Type, 0}, {"File.FileHeader", Field, 0}, {"FileHeader", Type, 0}, {"FileHeader.CRC32", Field, 0}, {"FileHeader.Comment", Field, 0}, {"FileHeader.CompressedSize", Field, 0}, {"FileHeader.CompressedSize64", Field, 1}, {"FileHeader.CreatorVersion", Field, 0}, {"FileHeader.ExternalAttrs", Field, 0}, {"FileHeader.Extra", Field, 0}, {"FileHeader.Flags", Field, 0}, {"FileHeader.Method", Field, 0}, {"FileHeader.Modified", Field, 10}, {"FileHeader.ModifiedDate", Field, 0}, {"FileHeader.ModifiedTime", Field, 0}, {"FileHeader.Name", Field, 0}, {"FileHeader.NonUTF8", Field, 10}, {"FileHeader.ReaderVersion", Field, 0}, {"FileHeader.UncompressedSize", Field, 0}, {"FileHeader.UncompressedSize64", Field, 1}, {"FileInfoHeader", Func, 0}, {"NewReader", Func, 0}, {"NewWriter", Func, 0}, {"OpenReader", Func, 0}, {"ReadCloser", Type, 0}, {"ReadCloser.Reader", Field, 0}, {"Reader", Type, 0}, {"Reader.Comment", Field, 0}, {"Reader.File", Field, 0}, {"RegisterCompressor", Func, 2}, {"RegisterDecompressor", Func, 2}, {"Store", Const, 0}, {"Writer", Type, 0}, }, "bufio": { {"(*Reader).Buffered", Method, 0}, {"(*Reader).Discard", Method, 5}, {"(*Reader).Peek", Method, 0}, {"(*Reader).Read", Method, 0}, {"(*Reader).ReadByte", Method, 0}, {"(*Reader).ReadBytes", Method, 0}, {"(*Reader).ReadLine", Method, 0}, {"(*Reader).ReadRune", Method, 0}, {"(*Reader).ReadSlice", Method, 0}, {"(*Reader).ReadString", Method, 0}, {"(*Reader).Reset", Method, 2}, {"(*Reader).Size", Method, 10}, {"(*Reader).UnreadByte", Method, 0}, {"(*Reader).UnreadRune", Method, 0}, {"(*Reader).WriteTo", Method, 1}, {"(*Scanner).Buffer", Method, 6}, {"(*Scanner).Bytes", Method, 1}, {"(*Scanner).Err", Method, 1}, {"(*Scanner).Scan", Method, 1}, {"(*Scanner).Split", Method, 1}, {"(*Scanner).Text", Method, 1}, {"(*Writer).Available", Method, 0}, {"(*Writer).AvailableBuffer", Method, 18}, {"(*Writer).Buffered", Method, 0}, {"(*Writer).Flush", Method, 0}, {"(*Writer).ReadFrom", Method, 1}, {"(*Writer).Reset", Method, 2}, {"(*Writer).Size", Method, 10}, {"(*Writer).Write", Method, 0}, {"(*Writer).WriteByte", Method, 0}, {"(*Writer).WriteRune", Method, 0}, {"(*Writer).WriteString", Method, 0}, {"(ReadWriter).Available", Method, 0}, {"(ReadWriter).AvailableBuffer", Method, 18}, {"(ReadWriter).Discard", Method, 5}, {"(ReadWriter).Flush", Method, 0}, {"(ReadWriter).Peek", Method, 0}, {"(ReadWriter).Read", Method, 0}, {"(ReadWriter).ReadByte", Method, 0}, {"(ReadWriter).ReadBytes", Method, 0}, {"(ReadWriter).ReadFrom", Method, 1}, {"(ReadWriter).ReadLine", Method, 0}, {"(ReadWriter).ReadRune", Method, 0}, {"(ReadWriter).ReadSlice", Method, 0}, {"(ReadWriter).ReadString", Method, 0}, {"(ReadWriter).UnreadByte", Method, 0}, {"(ReadWriter).UnreadRune", Method, 0}, {"(ReadWriter).Write", Method, 0}, {"(ReadWriter).WriteByte", Method, 0}, {"(ReadWriter).WriteRune", Method, 0}, {"(ReadWriter).WriteString", Method, 0}, {"(ReadWriter).WriteTo", Method, 1}, {"ErrAdvanceTooFar", Var, 1}, {"ErrBadReadCount", Var, 15}, {"ErrBufferFull", Var, 0}, {"ErrFinalToken", Var, 6}, {"ErrInvalidUnreadByte", Var, 0}, {"ErrInvalidUnreadRune", Var, 0}, {"ErrNegativeAdvance", Var, 1}, {"ErrNegativeCount", Var, 0}, {"ErrTooLong", Var, 1}, {"MaxScanTokenSize", Const, 1}, {"NewReadWriter", Func, 0}, {"NewReader", Func, 0}, {"NewReaderSize", Func, 0}, {"NewScanner", Func, 1}, {"NewWriter", Func, 0}, {"NewWriterSize", Func, 0}, {"ReadWriter", Type, 0}, {"ReadWriter.Reader", Field, 0}, {"ReadWriter.Writer", Field, 0}, {"Reader", Type, 0}, {"ScanBytes", Func, 1}, {"ScanLines", Func, 1}, {"ScanRunes", Func, 1}, {"ScanWords", Func, 1}, {"Scanner", Type, 1}, {"SplitFunc", Type, 1}, {"Writer", Type, 0}, }, "bytes": { {"(*Buffer).Available", Method, 21}, {"(*Buffer).AvailableBuffer", Method, 21}, {"(*Buffer).Bytes", Method, 0}, {"(*Buffer).Cap", Method, 5}, {"(*Buffer).Grow", Method, 1}, {"(*Buffer).Len", Method, 0}, {"(*Buffer).Next", Method, 0}, {"(*Buffer).Read", Method, 0}, {"(*Buffer).ReadByte", Method, 0}, {"(*Buffer).ReadBytes", Method, 0}, {"(*Buffer).ReadFrom", Method, 0}, {"(*Buffer).ReadRune", Method, 0}, {"(*Buffer).ReadString", Method, 0}, {"(*Buffer).Reset", Method, 0}, {"(*Buffer).String", Method, 0}, {"(*Buffer).Truncate", Method, 0}, {"(*Buffer).UnreadByte", Method, 0}, {"(*Buffer).UnreadRune", Method, 0}, {"(*Buffer).Write", Method, 0}, {"(*Buffer).WriteByte", Method, 0}, {"(*Buffer).WriteRune", Method, 0}, {"(*Buffer).WriteString", Method, 0}, {"(*Buffer).WriteTo", Method, 0}, {"(*Reader).Len", Method, 0}, {"(*Reader).Read", Method, 0}, {"(*Reader).ReadAt", Method, 0}, {"(*Reader).ReadByte", Method, 0}, {"(*Reader).ReadRune", Method, 0}, {"(*Reader).Reset", Method, 7}, {"(*Reader).Seek", Method, 0}, {"(*Reader).Size", Method, 5}, {"(*Reader).UnreadByte", Method, 0}, {"(*Reader).UnreadRune", Method, 0}, {"(*Reader).WriteTo", Method, 1}, {"Buffer", Type, 0}, {"Clone", Func, 20}, {"Compare", Func, 0}, {"Contains", Func, 0}, {"ContainsAny", Func, 7}, {"ContainsFunc", Func, 21}, {"ContainsRune", Func, 7}, {"Count", Func, 0}, {"Cut", Func, 18}, {"CutPrefix", Func, 20}, {"CutSuffix", Func, 20}, {"Equal", Func, 0}, {"EqualFold", Func, 0}, {"ErrTooLarge", Var, 0}, {"Fields", Func, 0}, {"FieldsFunc", Func, 0}, {"FieldsFuncSeq", Func, 24}, {"FieldsSeq", Func, 24}, {"HasPrefix", Func, 0}, {"HasSuffix", Func, 0}, {"Index", Func, 0}, {"IndexAny", Func, 0}, {"IndexByte", Func, 0}, {"IndexFunc", Func, 0}, {"IndexRune", Func, 0}, {"Join", Func, 0}, {"LastIndex", Func, 0}, {"LastIndexAny", Func, 0}, {"LastIndexByte", Func, 5}, {"LastIndexFunc", Func, 0}, {"Lines", Func, 24}, {"Map", Func, 0}, {"MinRead", Const, 0}, {"NewBuffer", Func, 0}, {"NewBufferString", Func, 0}, {"NewReader", Func, 0}, {"Reader", Type, 0}, {"Repeat", Func, 0}, {"Replace", Func, 0}, {"ReplaceAll", Func, 12}, {"Runes", Func, 0}, {"Split", Func, 0}, {"SplitAfter", Func, 0}, {"SplitAfterN", Func, 0}, {"SplitAfterSeq", Func, 24}, {"SplitN", Func, 0}, {"SplitSeq", Func, 24}, {"Title", Func, 0}, {"ToLower", Func, 0}, {"ToLowerSpecial", Func, 0}, {"ToTitle", Func, 0}, {"ToTitleSpecial", Func, 0}, {"ToUpper", Func, 0}, {"ToUpperSpecial", Func, 0}, {"ToValidUTF8", Func, 13}, {"Trim", Func, 0}, {"TrimFunc", Func, 0}, {"TrimLeft", Func, 0}, {"TrimLeftFunc", Func, 0}, {"TrimPrefix", Func, 1}, {"TrimRight", Func, 0}, {"TrimRightFunc", Func, 0}, {"TrimSpace", Func, 0}, {"TrimSuffix", Func, 1}, }, "cmp": { {"Compare", Func, 21}, {"Less", Func, 21}, {"Or", Func, 22}, {"Ordered", Type, 21}, }, "compress/bzip2": { {"(StructuralError).Error", Method, 0}, {"NewReader", Func, 0}, {"StructuralError", Type, 0}, }, "compress/flate": { {"(*ReadError).Error", Method, 0}, {"(*WriteError).Error", Method, 0}, {"(*Writer).Close", Method, 0}, {"(*Writer).Flush", Method, 0}, {"(*Writer).Reset", Method, 2}, {"(*Writer).Write", Method, 0}, {"(CorruptInputError).Error", Method, 0}, {"(InternalError).Error", Method, 0}, {"BestCompression", Const, 0}, {"BestSpeed", Const, 0}, {"CorruptInputError", Type, 0}, {"DefaultCompression", Const, 0}, {"HuffmanOnly", Const, 7}, {"InternalError", Type, 0}, {"NewReader", Func, 0}, {"NewReaderDict", Func, 0}, {"NewWriter", Func, 0}, {"NewWriterDict", Func, 0}, {"NoCompression", Const, 0}, {"ReadError", Type, 0}, {"ReadError.Err", Field, 0}, {"ReadError.Offset", Field, 0}, {"Reader", Type, 0}, {"Resetter", Type, 4}, {"WriteError", Type, 0}, {"WriteError.Err", Field, 0}, {"WriteError.Offset", Field, 0}, {"Writer", Type, 0}, }, "compress/gzip": { {"(*Reader).Close", Method, 0}, {"(*Reader).Multistream", Method, 4}, {"(*Reader).Read", Method, 0}, {"(*Reader).Reset", Method, 3}, {"(*Writer).Close", Method, 0}, {"(*Writer).Flush", Method, 1}, {"(*Writer).Reset", Method, 2}, {"(*Writer).Write", Method, 0}, {"BestCompression", Const, 0}, {"BestSpeed", Const, 0}, {"DefaultCompression", Const, 0}, {"ErrChecksum", Var, 0}, {"ErrHeader", Var, 0}, {"Header", Type, 0}, {"Header.Comment", Field, 0}, {"Header.Extra", Field, 0}, {"Header.ModTime", Field, 0}, {"Header.Name", Field, 0}, {"Header.OS", Field, 0}, {"HuffmanOnly", Const, 8}, {"NewReader", Func, 0}, {"NewWriter", Func, 0}, {"NewWriterLevel", Func, 0}, {"NoCompression", Const, 0}, {"Reader", Type, 0}, {"Reader.Header", Field, 0}, {"Writer", Type, 0}, {"Writer.Header", Field, 0}, }, "compress/lzw": { {"(*Reader).Close", Method, 17}, {"(*Reader).Read", Method, 17}, {"(*Reader).Reset", Method, 17}, {"(*Writer).Close", Method, 17}, {"(*Writer).Reset", Method, 17}, {"(*Writer).Write", Method, 17}, {"LSB", Const, 0}, {"MSB", Const, 0}, {"NewReader", Func, 0}, {"NewWriter", Func, 0}, {"Order", Type, 0}, {"Reader", Type, 17}, {"Writer", Type, 17}, }, "compress/zlib": { {"(*Writer).Close", Method, 0}, {"(*Writer).Flush", Method, 0}, {"(*Writer).Reset", Method, 2}, {"(*Writer).Write", Method, 0}, {"BestCompression", Const, 0}, {"BestSpeed", Const, 0}, {"DefaultCompression", Const, 0}, {"ErrChecksum", Var, 0}, {"ErrDictionary", Var, 0}, {"ErrHeader", Var, 0}, {"HuffmanOnly", Const, 8}, {"NewReader", Func, 0}, {"NewReaderDict", Func, 0}, {"NewWriter", Func, 0}, {"NewWriterLevel", Func, 0}, {"NewWriterLevelDict", Func, 0}, {"NoCompression", Const, 0}, {"Resetter", Type, 4}, {"Writer", Type, 0}, }, "container/heap": { {"Fix", Func, 2}, {"Init", Func, 0}, {"Interface", Type, 0}, {"Pop", Func, 0}, {"Push", Func, 0}, {"Remove", Func, 0}, }, "container/list": { {"(*Element).Next", Method, 0}, {"(*Element).Prev", Method, 0}, {"(*List).Back", Method, 0}, {"(*List).Front", Method, 0}, {"(*List).Init", Method, 0}, {"(*List).InsertAfter", Method, 0}, {"(*List).InsertBefore", Method, 0}, {"(*List).Len", Method, 0}, {"(*List).MoveAfter", Method, 2}, {"(*List).MoveBefore", Method, 2}, {"(*List).MoveToBack", Method, 0}, {"(*List).MoveToFront", Method, 0}, {"(*List).PushBack", Method, 0}, {"(*List).PushBackList", Method, 0}, {"(*List).PushFront", Method, 0}, {"(*List).PushFrontList", Method, 0}, {"(*List).Remove", Method, 0}, {"Element", Type, 0}, {"Element.Value", Field, 0}, {"List", Type, 0}, {"New", Func, 0}, }, "container/ring": { {"(*Ring).Do", Method, 0}, {"(*Ring).Len", Method, 0}, {"(*Ring).Link", Method, 0}, {"(*Ring).Move", Method, 0}, {"(*Ring).Next", Method, 0}, {"(*Ring).Prev", Method, 0}, {"(*Ring).Unlink", Method, 0}, {"New", Func, 0}, {"Ring", Type, 0}, {"Ring.Value", Field, 0}, }, "context": { {"AfterFunc", Func, 21}, {"Background", Func, 7}, {"CancelCauseFunc", Type, 20}, {"CancelFunc", Type, 7}, {"Canceled", Var, 7}, {"Cause", Func, 20}, {"Context", Type, 7}, {"DeadlineExceeded", Var, 7}, {"TODO", Func, 7}, {"WithCancel", Func, 7}, {"WithCancelCause", Func, 20}, {"WithDeadline", Func, 7}, {"WithDeadlineCause", Func, 21}, {"WithTimeout", Func, 7}, {"WithTimeoutCause", Func, 21}, {"WithValue", Func, 7}, {"WithoutCancel", Func, 21}, }, "crypto": { {"(Hash).Available", Method, 0}, {"(Hash).HashFunc", Method, 4}, {"(Hash).New", Method, 0}, {"(Hash).Size", Method, 0}, {"(Hash).String", Method, 15}, {"BLAKE2b_256", Const, 9}, {"BLAKE2b_384", Const, 9}, {"BLAKE2b_512", Const, 9}, {"BLAKE2s_256", Const, 9}, {"Decrypter", Type, 5}, {"DecrypterOpts", Type, 5}, {"Hash", Type, 0}, {"MD4", Const, 0}, {"MD5", Const, 0}, {"MD5SHA1", Const, 0}, {"PrivateKey", Type, 0}, {"PublicKey", Type, 2}, {"RIPEMD160", Const, 0}, {"RegisterHash", Func, 0}, {"SHA1", Const, 0}, {"SHA224", Const, 0}, {"SHA256", Const, 0}, {"SHA384", Const, 0}, {"SHA3_224", Const, 4}, {"SHA3_256", Const, 4}, {"SHA3_384", Const, 4}, {"SHA3_512", Const, 4}, {"SHA512", Const, 0}, {"SHA512_224", Const, 5}, {"SHA512_256", Const, 5}, {"Signer", Type, 4}, {"SignerOpts", Type, 4}, }, "crypto/aes": { {"(KeySizeError).Error", Method, 0}, {"BlockSize", Const, 0}, {"KeySizeError", Type, 0}, {"NewCipher", Func, 0}, }, "crypto/cipher": { {"(StreamReader).Read", Method, 0}, {"(StreamWriter).Close", Method, 0}, {"(StreamWriter).Write", Method, 0}, {"AEAD", Type, 2}, {"Block", Type, 0}, {"BlockMode", Type, 0}, {"NewCBCDecrypter", Func, 0}, {"NewCBCEncrypter", Func, 0}, {"NewCFBDecrypter", Func, 0}, {"NewCFBEncrypter", Func, 0}, {"NewCTR", Func, 0}, {"NewGCM", Func, 2}, {"NewGCMWithNonceSize", Func, 5}, {"NewGCMWithRandomNonce", Func, 24}, {"NewGCMWithTagSize", Func, 11}, {"NewOFB", Func, 0}, {"Stream", Type, 0}, {"StreamReader", Type, 0}, {"StreamReader.R", Field, 0}, {"StreamReader.S", Field, 0}, {"StreamWriter", Type, 0}, {"StreamWriter.Err", Field, 0}, {"StreamWriter.S", Field, 0}, {"StreamWriter.W", Field, 0}, }, "crypto/des": { {"(KeySizeError).Error", Method, 0}, {"BlockSize", Const, 0}, {"KeySizeError", Type, 0}, {"NewCipher", Func, 0}, {"NewTripleDESCipher", Func, 0}, }, "crypto/dsa": { {"ErrInvalidPublicKey", Var, 0}, {"GenerateKey", Func, 0}, {"GenerateParameters", Func, 0}, {"L1024N160", Const, 0}, {"L2048N224", Const, 0}, {"L2048N256", Const, 0}, {"L3072N256", Const, 0}, {"ParameterSizes", Type, 0}, {"Parameters", Type, 0}, {"Parameters.G", Field, 0}, {"Parameters.P", Field, 0}, {"Parameters.Q", Field, 0}, {"PrivateKey", Type, 0}, {"PrivateKey.PublicKey", Field, 0}, {"PrivateKey.X", Field, 0}, {"PublicKey", Type, 0}, {"PublicKey.Parameters", Field, 0}, {"PublicKey.Y", Field, 0}, {"Sign", Func, 0}, {"Verify", Func, 0}, }, "crypto/ecdh": { {"(*PrivateKey).Bytes", Method, 20}, {"(*PrivateKey).Curve", Method, 20}, {"(*PrivateKey).ECDH", Method, 20}, {"(*PrivateKey).Equal", Method, 20}, {"(*PrivateKey).Public", Method, 20}, {"(*PrivateKey).PublicKey", Method, 20}, {"(*PublicKey).Bytes", Method, 20}, {"(*PublicKey).Curve", Method, 20}, {"(*PublicKey).Equal", Method, 20}, {"Curve", Type, 20}, {"P256", Func, 20}, {"P384", Func, 20}, {"P521", Func, 20}, {"PrivateKey", Type, 20}, {"PublicKey", Type, 20}, {"X25519", Func, 20}, }, "crypto/ecdsa": { {"(*PrivateKey).ECDH", Method, 20}, {"(*PrivateKey).Equal", Method, 15}, {"(*PrivateKey).Public", Method, 4}, {"(*PrivateKey).Sign", Method, 4}, {"(*PublicKey).ECDH", Method, 20}, {"(*PublicKey).Equal", Method, 15}, {"(PrivateKey).Add", Method, 0}, {"(PrivateKey).Double", Method, 0}, {"(PrivateKey).IsOnCurve", Method, 0}, {"(PrivateKey).Params", Method, 0}, {"(PrivateKey).ScalarBaseMult", Method, 0}, {"(PrivateKey).ScalarMult", Method, 0}, {"(PublicKey).Add", Method, 0}, {"(PublicKey).Double", Method, 0}, {"(PublicKey).IsOnCurve", Method, 0}, {"(PublicKey).Params", Method, 0}, {"(PublicKey).ScalarBaseMult", Method, 0}, {"(PublicKey).ScalarMult", Method, 0}, {"GenerateKey", Func, 0}, {"PrivateKey", Type, 0}, {"PrivateKey.D", Field, 0}, {"PrivateKey.PublicKey", Field, 0}, {"PublicKey", Type, 0}, {"PublicKey.Curve", Field, 0}, {"PublicKey.X", Field, 0}, {"PublicKey.Y", Field, 0}, {"Sign", Func, 0}, {"SignASN1", Func, 15}, {"Verify", Func, 0}, {"VerifyASN1", Func, 15}, }, "crypto/ed25519": { {"(*Options).HashFunc", Method, 20}, {"(PrivateKey).Equal", Method, 15}, {"(PrivateKey).Public", Method, 13}, {"(PrivateKey).Seed", Method, 13}, {"(PrivateKey).Sign", Method, 13}, {"(PublicKey).Equal", Method, 15}, {"GenerateKey", Func, 13}, {"NewKeyFromSeed", Func, 13}, {"Options", Type, 20}, {"Options.Context", Field, 20}, {"Options.Hash", Field, 20}, {"PrivateKey", Type, 13}, {"PrivateKeySize", Const, 13}, {"PublicKey", Type, 13}, {"PublicKeySize", Const, 13}, {"SeedSize", Const, 13}, {"Sign", Func, 13}, {"SignatureSize", Const, 13}, {"Verify", Func, 13}, {"VerifyWithOptions", Func, 20}, }, "crypto/elliptic": { {"(*CurveParams).Add", Method, 0}, {"(*CurveParams).Double", Method, 0}, {"(*CurveParams).IsOnCurve", Method, 0}, {"(*CurveParams).Params", Method, 0}, {"(*CurveParams).ScalarBaseMult", Method, 0}, {"(*CurveParams).ScalarMult", Method, 0}, {"Curve", Type, 0}, {"CurveParams", Type, 0}, {"CurveParams.B", Field, 0}, {"CurveParams.BitSize", Field, 0}, {"CurveParams.Gx", Field, 0}, {"CurveParams.Gy", Field, 0}, {"CurveParams.N", Field, 0}, {"CurveParams.Name", Field, 5}, {"CurveParams.P", Field, 0}, {"GenerateKey", Func, 0}, {"Marshal", Func, 0}, {"MarshalCompressed", Func, 15}, {"P224", Func, 0}, {"P256", Func, 0}, {"P384", Func, 0}, {"P521", Func, 0}, {"Unmarshal", Func, 0}, {"UnmarshalCompressed", Func, 15}, }, "crypto/fips140": { {"Enabled", Func, 24}, }, "crypto/hkdf": { {"Expand", Func, 24}, {"Extract", Func, 24}, {"Key", Func, 24}, }, "crypto/hmac": { {"Equal", Func, 1}, {"New", Func, 0}, }, "crypto/md5": { {"BlockSize", Const, 0}, {"New", Func, 0}, {"Size", Const, 0}, {"Sum", Func, 2}, }, "crypto/mlkem": { {"(*DecapsulationKey1024).Bytes", Method, 24}, {"(*DecapsulationKey1024).Decapsulate", Method, 24}, {"(*DecapsulationKey1024).EncapsulationKey", Method, 24}, {"(*DecapsulationKey768).Bytes", Method, 24}, {"(*DecapsulationKey768).Decapsulate", Method, 24}, {"(*DecapsulationKey768).EncapsulationKey", Method, 24}, {"(*EncapsulationKey1024).Bytes", Method, 24}, {"(*EncapsulationKey1024).Encapsulate", Method, 24}, {"(*EncapsulationKey768).Bytes", Method, 24}, {"(*EncapsulationKey768).Encapsulate", Method, 24}, {"CiphertextSize1024", Const, 24}, {"CiphertextSize768", Const, 24}, {"DecapsulationKey1024", Type, 24}, {"DecapsulationKey768", Type, 24}, {"EncapsulationKey1024", Type, 24}, {"EncapsulationKey768", Type, 24}, {"EncapsulationKeySize1024", Const, 24}, {"EncapsulationKeySize768", Const, 24}, {"GenerateKey1024", Func, 24}, {"GenerateKey768", Func, 24}, {"NewDecapsulationKey1024", Func, 24}, {"NewDecapsulationKey768", Func, 24}, {"NewEncapsulationKey1024", Func, 24}, {"NewEncapsulationKey768", Func, 24}, {"SeedSize", Const, 24}, {"SharedKeySize", Const, 24}, }, "crypto/pbkdf2": { {"Key", Func, 24}, }, "crypto/rand": { {"Int", Func, 0}, {"Prime", Func, 0}, {"Read", Func, 0}, {"Reader", Var, 0}, {"Text", Func, 24}, }, "crypto/rc4": { {"(*Cipher).Reset", Method, 0}, {"(*Cipher).XORKeyStream", Method, 0}, {"(KeySizeError).Error", Method, 0}, {"Cipher", Type, 0}, {"KeySizeError", Type, 0}, {"NewCipher", Func, 0}, }, "crypto/rsa": { {"(*PSSOptions).HashFunc", Method, 4}, {"(*PrivateKey).Decrypt", Method, 5}, {"(*PrivateKey).Equal", Method, 15}, {"(*PrivateKey).Precompute", Method, 0}, {"(*PrivateKey).Public", Method, 4}, {"(*PrivateKey).Sign", Method, 4}, {"(*PrivateKey).Size", Method, 11}, {"(*PrivateKey).Validate", Method, 0}, {"(*PublicKey).Equal", Method, 15}, {"(*PublicKey).Size", Method, 11}, {"CRTValue", Type, 0}, {"CRTValue.Coeff", Field, 0}, {"CRTValue.Exp", Field, 0}, {"CRTValue.R", Field, 0}, {"DecryptOAEP", Func, 0}, {"DecryptPKCS1v15", Func, 0}, {"DecryptPKCS1v15SessionKey", Func, 0}, {"EncryptOAEP", Func, 0}, {"EncryptPKCS1v15", Func, 0}, {"ErrDecryption", Var, 0}, {"ErrMessageTooLong", Var, 0}, {"ErrVerification", Var, 0}, {"GenerateKey", Func, 0}, {"GenerateMultiPrimeKey", Func, 0}, {"OAEPOptions", Type, 5}, {"OAEPOptions.Hash", Field, 5}, {"OAEPOptions.Label", Field, 5}, {"OAEPOptions.MGFHash", Field, 20}, {"PKCS1v15DecryptOptions", Type, 5}, {"PKCS1v15DecryptOptions.SessionKeyLen", Field, 5}, {"PSSOptions", Type, 2}, {"PSSOptions.Hash", Field, 4}, {"PSSOptions.SaltLength", Field, 2}, {"PSSSaltLengthAuto", Const, 2}, {"PSSSaltLengthEqualsHash", Const, 2}, {"PrecomputedValues", Type, 0}, {"PrecomputedValues.CRTValues", Field, 0}, {"PrecomputedValues.Dp", Field, 0}, {"PrecomputedValues.Dq", Field, 0}, {"PrecomputedValues.Qinv", Field, 0}, {"PrivateKey", Type, 0}, {"PrivateKey.D", Field, 0}, {"PrivateKey.Precomputed", Field, 0}, {"PrivateKey.Primes", Field, 0}, {"PrivateKey.PublicKey", Field, 0}, {"PublicKey", Type, 0}, {"PublicKey.E", Field, 0}, {"PublicKey.N", Field, 0}, {"SignPKCS1v15", Func, 0}, {"SignPSS", Func, 2}, {"VerifyPKCS1v15", Func, 0}, {"VerifyPSS", Func, 2}, }, "crypto/sha1": { {"BlockSize", Const, 0}, {"New", Func, 0}, {"Size", Const, 0}, {"Sum", Func, 2}, }, "crypto/sha256": { {"BlockSize", Const, 0}, {"New", Func, 0}, {"New224", Func, 0}, {"Size", Const, 0}, {"Size224", Const, 0}, {"Sum224", Func, 2}, {"Sum256", Func, 2}, }, "crypto/sha3": { {"(*SHA3).AppendBinary", Method, 24}, {"(*SHA3).BlockSize", Method, 24}, {"(*SHA3).MarshalBinary", Method, 24}, {"(*SHA3).Reset", Method, 24}, {"(*SHA3).Size", Method, 24}, {"(*SHA3).Sum", Method, 24}, {"(*SHA3).UnmarshalBinary", Method, 24}, {"(*SHA3).Write", Method, 24}, {"(*SHAKE).AppendBinary", Method, 24}, {"(*SHAKE).BlockSize", Method, 24}, {"(*SHAKE).MarshalBinary", Method, 24}, {"(*SHAKE).Read", Method, 24}, {"(*SHAKE).Reset", Method, 24}, {"(*SHAKE).UnmarshalBinary", Method, 24}, {"(*SHAKE).Write", Method, 24}, {"New224", Func, 24}, {"New256", Func, 24}, {"New384", Func, 24}, {"New512", Func, 24}, {"NewCSHAKE128", Func, 24}, {"NewCSHAKE256", Func, 24}, {"NewSHAKE128", Func, 24}, {"NewSHAKE256", Func, 24}, {"SHA3", Type, 24}, {"SHAKE", Type, 24}, {"Sum224", Func, 24}, {"Sum256", Func, 24}, {"Sum384", Func, 24}, {"Sum512", Func, 24}, {"SumSHAKE128", Func, 24}, {"SumSHAKE256", Func, 24}, }, "crypto/sha512": { {"BlockSize", Const, 0}, {"New", Func, 0}, {"New384", Func, 0}, {"New512_224", Func, 5}, {"New512_256", Func, 5}, {"Size", Const, 0}, {"Size224", Const, 5}, {"Size256", Const, 5}, {"Size384", Const, 0}, {"Sum384", Func, 2}, {"Sum512", Func, 2}, {"Sum512_224", Func, 5}, {"Sum512_256", Func, 5}, }, "crypto/subtle": { {"ConstantTimeByteEq", Func, 0}, {"ConstantTimeCompare", Func, 0}, {"ConstantTimeCopy", Func, 0}, {"ConstantTimeEq", Func, 0}, {"ConstantTimeLessOrEq", Func, 2}, {"ConstantTimeSelect", Func, 0}, {"WithDataIndependentTiming", Func, 24}, {"XORBytes", Func, 20}, }, "crypto/tls": { {"(*CertificateRequestInfo).Context", Method, 17}, {"(*CertificateRequestInfo).SupportsCertificate", Method, 14}, {"(*CertificateVerificationError).Error", Method, 20}, {"(*CertificateVerificationError).Unwrap", Method, 20}, {"(*ClientHelloInfo).Context", Method, 17}, {"(*ClientHelloInfo).SupportsCertificate", Method, 14}, {"(*ClientSessionState).ResumptionState", Method, 21}, {"(*Config).BuildNameToCertificate", Method, 0}, {"(*Config).Clone", Method, 8}, {"(*Config).DecryptTicket", Method, 21}, {"(*Config).EncryptTicket", Method, 21}, {"(*Config).SetSessionTicketKeys", Method, 5}, {"(*Conn).Close", Method, 0}, {"(*Conn).CloseWrite", Method, 8}, {"(*Conn).ConnectionState", Method, 0}, {"(*Conn).Handshake", Method, 0}, {"(*Conn).HandshakeContext", Method, 17}, {"(*Conn).LocalAddr", Method, 0}, {"(*Conn).NetConn", Method, 18}, {"(*Conn).OCSPResponse", Method, 0}, {"(*Conn).Read", Method, 0}, {"(*Conn).RemoteAddr", Method, 0}, {"(*Conn).SetDeadline", Method, 0}, {"(*Conn).SetReadDeadline", Method, 0}, {"(*Conn).SetWriteDeadline", Method, 0}, {"(*Conn).VerifyHostname", Method, 0}, {"(*Conn).Write", Method, 0}, {"(*ConnectionState).ExportKeyingMaterial", Method, 11}, {"(*Dialer).Dial", Method, 15}, {"(*Dialer).DialContext", Method, 15}, {"(*ECHRejectionError).Error", Method, 23}, {"(*QUICConn).Close", Method, 21}, {"(*QUICConn).ConnectionState", Method, 21}, {"(*QUICConn).HandleData", Method, 21}, {"(*QUICConn).NextEvent", Method, 21}, {"(*QUICConn).SendSessionTicket", Method, 21}, {"(*QUICConn).SetTransportParameters", Method, 21}, {"(*QUICConn).Start", Method, 21}, {"(*QUICConn).StoreSession", Method, 23}, {"(*SessionState).Bytes", Method, 21}, {"(AlertError).Error", Method, 21}, {"(ClientAuthType).String", Method, 15}, {"(CurveID).String", Method, 15}, {"(QUICEncryptionLevel).String", Method, 21}, {"(RecordHeaderError).Error", Method, 6}, {"(SignatureScheme).String", Method, 15}, {"AlertError", Type, 21}, {"Certificate", Type, 0}, {"Certificate.Certificate", Field, 0}, {"Certificate.Leaf", Field, 0}, {"Certificate.OCSPStaple", Field, 0}, {"Certificate.PrivateKey", Field, 0}, {"Certificate.SignedCertificateTimestamps", Field, 5}, {"Certificate.SupportedSignatureAlgorithms", Field, 14}, {"CertificateRequestInfo", Type, 8}, {"CertificateRequestInfo.AcceptableCAs", Field, 8}, {"CertificateRequestInfo.SignatureSchemes", Field, 8}, {"CertificateRequestInfo.Version", Field, 14}, {"CertificateVerificationError", Type, 20}, {"CertificateVerificationError.Err", Field, 20}, {"CertificateVerificationError.UnverifiedCertificates", Field, 20}, {"CipherSuite", Type, 14}, {"CipherSuite.ID", Field, 14}, {"CipherSuite.Insecure", Field, 14}, {"CipherSuite.Name", Field, 14}, {"CipherSuite.SupportedVersions", Field, 14}, {"CipherSuiteName", Func, 14}, {"CipherSuites", Func, 14}, {"Client", Func, 0}, {"ClientAuthType", Type, 0}, {"ClientHelloInfo", Type, 4}, {"ClientHelloInfo.CipherSuites", Field, 4}, {"ClientHelloInfo.Conn", Field, 8}, {"ClientHelloInfo.Extensions", Field, 24}, {"ClientHelloInfo.ServerName", Field, 4}, {"ClientHelloInfo.SignatureSchemes", Field, 8}, {"ClientHelloInfo.SupportedCurves", Field, 4}, {"ClientHelloInfo.SupportedPoints", Field, 4}, {"ClientHelloInfo.SupportedProtos", Field, 8}, {"ClientHelloInfo.SupportedVersions", Field, 8}, {"ClientSessionCache", Type, 3}, {"ClientSessionState", Type, 3}, {"Config", Type, 0}, {"Config.Certificates", Field, 0}, {"Config.CipherSuites", Field, 0}, {"Config.ClientAuth", Field, 0}, {"Config.ClientCAs", Field, 0}, {"Config.ClientSessionCache", Field, 3}, {"Config.CurvePreferences", Field, 3}, {"Config.DynamicRecordSizingDisabled", Field, 7}, {"Config.EncryptedClientHelloConfigList", Field, 23}, {"Config.EncryptedClientHelloKeys", Field, 24}, {"Config.EncryptedClientHelloRejectionVerify", Field, 23}, {"Config.GetCertificate", Field, 4}, {"Config.GetClientCertificate", Field, 8}, {"Config.GetConfigForClient", Field, 8}, {"Config.InsecureSkipVerify", Field, 0}, {"Config.KeyLogWriter", Field, 8}, {"Config.MaxVersion", Field, 2}, {"Config.MinVersion", Field, 2}, {"Config.NameToCertificate", Field, 0}, {"Config.NextProtos", Field, 0}, {"Config.PreferServerCipherSuites", Field, 1}, {"Config.Rand", Field, 0}, {"Config.Renegotiation", Field, 7}, {"Config.RootCAs", Field, 0}, {"Config.ServerName", Field, 0}, {"Config.SessionTicketKey", Field, 1}, {"Config.SessionTicketsDisabled", Field, 1}, {"Config.Time", Field, 0}, {"Config.UnwrapSession", Field, 21}, {"Config.VerifyConnection", Field, 15}, {"Config.VerifyPeerCertificate", Field, 8}, {"Config.WrapSession", Field, 21}, {"Conn", Type, 0}, {"ConnectionState", Type, 0}, {"ConnectionState.CipherSuite", Field, 0}, {"ConnectionState.CurveID", Field, 25}, {"ConnectionState.DidResume", Field, 1}, {"ConnectionState.ECHAccepted", Field, 23}, {"ConnectionState.HandshakeComplete", Field, 0}, {"ConnectionState.NegotiatedProtocol", Field, 0}, {"ConnectionState.NegotiatedProtocolIsMutual", Field, 0}, {"ConnectionState.OCSPResponse", Field, 5}, {"ConnectionState.PeerCertificates", Field, 0}, {"ConnectionState.ServerName", Field, 0}, {"ConnectionState.SignedCertificateTimestamps", Field, 5}, {"ConnectionState.TLSUnique", Field, 4}, {"ConnectionState.VerifiedChains", Field, 0}, {"ConnectionState.Version", Field, 3}, {"CurveID", Type, 3}, {"CurveP256", Const, 3}, {"CurveP384", Const, 3}, {"CurveP521", Const, 3}, {"Dial", Func, 0}, {"DialWithDialer", Func, 3}, {"Dialer", Type, 15}, {"Dialer.Config", Field, 15}, {"Dialer.NetDialer", Field, 15}, {"ECDSAWithP256AndSHA256", Const, 8}, {"ECDSAWithP384AndSHA384", Const, 8}, {"ECDSAWithP521AndSHA512", Const, 8}, {"ECDSAWithSHA1", Const, 10}, {"ECHRejectionError", Type, 23}, {"ECHRejectionError.RetryConfigList", Field, 23}, {"Ed25519", Const, 13}, {"EncryptedClientHelloKey", Type, 24}, {"EncryptedClientHelloKey.Config", Field, 24}, {"EncryptedClientHelloKey.PrivateKey", Field, 24}, {"EncryptedClientHelloKey.SendAsRetry", Field, 24}, {"InsecureCipherSuites", Func, 14}, {"Listen", Func, 0}, {"LoadX509KeyPair", Func, 0}, {"NewLRUClientSessionCache", Func, 3}, {"NewListener", Func, 0}, {"NewResumptionState", Func, 21}, {"NoClientCert", Const, 0}, {"PKCS1WithSHA1", Const, 8}, {"PKCS1WithSHA256", Const, 8}, {"PKCS1WithSHA384", Const, 8}, {"PKCS1WithSHA512", Const, 8}, {"PSSWithSHA256", Const, 8}, {"PSSWithSHA384", Const, 8}, {"PSSWithSHA512", Const, 8}, {"ParseSessionState", Func, 21}, {"QUICClient", Func, 21}, {"QUICConfig", Type, 21}, {"QUICConfig.EnableSessionEvents", Field, 23}, {"QUICConfig.TLSConfig", Field, 21}, {"QUICConn", Type, 21}, {"QUICEncryptionLevel", Type, 21}, {"QUICEncryptionLevelApplication", Const, 21}, {"QUICEncryptionLevelEarly", Const, 21}, {"QUICEncryptionLevelHandshake", Const, 21}, {"QUICEncryptionLevelInitial", Const, 21}, {"QUICEvent", Type, 21}, {"QUICEvent.Data", Field, 21}, {"QUICEvent.Kind", Field, 21}, {"QUICEvent.Level", Field, 21}, {"QUICEvent.SessionState", Field, 23}, {"QUICEvent.Suite", Field, 21}, {"QUICEventKind", Type, 21}, {"QUICHandshakeDone", Const, 21}, {"QUICNoEvent", Const, 21}, {"QUICRejectedEarlyData", Const, 21}, {"QUICResumeSession", Const, 23}, {"QUICServer", Func, 21}, {"QUICSessionTicketOptions", Type, 21}, {"QUICSessionTicketOptions.EarlyData", Field, 21}, {"QUICSessionTicketOptions.Extra", Field, 23}, {"QUICSetReadSecret", Const, 21}, {"QUICSetWriteSecret", Const, 21}, {"QUICStoreSession", Const, 23}, {"QUICTransportParameters", Const, 21}, {"QUICTransportParametersRequired", Const, 21}, {"QUICWriteData", Const, 21}, {"RecordHeaderError", Type, 6}, {"RecordHeaderError.Conn", Field, 12}, {"RecordHeaderError.Msg", Field, 6}, {"RecordHeaderError.RecordHeader", Field, 6}, {"RenegotiateFreelyAsClient", Const, 7}, {"RenegotiateNever", Const, 7}, {"RenegotiateOnceAsClient", Const, 7}, {"RenegotiationSupport", Type, 7}, {"RequestClientCert", Const, 0}, {"RequireAndVerifyClientCert", Const, 0}, {"RequireAnyClientCert", Const, 0}, {"Server", Func, 0}, {"SessionState", Type, 21}, {"SessionState.EarlyData", Field, 21}, {"SessionState.Extra", Field, 21}, {"SignatureScheme", Type, 8}, {"TLS_AES_128_GCM_SHA256", Const, 12}, {"TLS_AES_256_GCM_SHA384", Const, 12}, {"TLS_CHACHA20_POLY1305_SHA256", Const, 12}, {"TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA", Const, 2}, {"TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256", Const, 8}, {"TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256", Const, 2}, {"TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA", Const, 2}, {"TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384", Const, 5}, {"TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305", Const, 8}, {"TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256", Const, 14}, {"TLS_ECDHE_ECDSA_WITH_RC4_128_SHA", Const, 2}, {"TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA", Const, 0}, {"TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA", Const, 0}, {"TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256", Const, 8}, {"TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256", Const, 2}, {"TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA", Const, 1}, {"TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384", Const, 5}, {"TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305", Const, 8}, {"TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256", Const, 14}, {"TLS_ECDHE_RSA_WITH_RC4_128_SHA", Const, 0}, {"TLS_FALLBACK_SCSV", Const, 4}, {"TLS_RSA_WITH_3DES_EDE_CBC_SHA", Const, 0}, {"TLS_RSA_WITH_AES_128_CBC_SHA", Const, 0}, {"TLS_RSA_WITH_AES_128_CBC_SHA256", Const, 8}, {"TLS_RSA_WITH_AES_128_GCM_SHA256", Const, 6}, {"TLS_RSA_WITH_AES_256_CBC_SHA", Const, 1}, {"TLS_RSA_WITH_AES_256_GCM_SHA384", Const, 6}, {"TLS_RSA_WITH_RC4_128_SHA", Const, 0}, {"VerifyClientCertIfGiven", Const, 0}, {"VersionName", Func, 21}, {"VersionSSL30", Const, 2}, {"VersionTLS10", Const, 2}, {"VersionTLS11", Const, 2}, {"VersionTLS12", Const, 2}, {"VersionTLS13", Const, 12}, {"X25519", Const, 8}, {"X25519MLKEM768", Const, 24}, {"X509KeyPair", Func, 0}, }, "crypto/x509": { {"(*CertPool).AddCert", Method, 0}, {"(*CertPool).AddCertWithConstraint", Method, 22}, {"(*CertPool).AppendCertsFromPEM", Method, 0}, {"(*CertPool).Clone", Method, 19}, {"(*CertPool).Equal", Method, 19}, {"(*CertPool).Subjects", Method, 0}, {"(*Certificate).CheckCRLSignature", Method, 0}, {"(*Certificate).CheckSignature", Method, 0}, {"(*Certificate).CheckSignatureFrom", Method, 0}, {"(*Certificate).CreateCRL", Method, 0}, {"(*Certificate).Equal", Method, 0}, {"(*Certificate).Verify", Method, 0}, {"(*Certificate).VerifyHostname", Method, 0}, {"(*CertificateRequest).CheckSignature", Method, 5}, {"(*OID).UnmarshalBinary", Method, 23}, {"(*OID).UnmarshalText", Method, 23}, {"(*RevocationList).CheckSignatureFrom", Method, 19}, {"(CertificateInvalidError).Error", Method, 0}, {"(ConstraintViolationError).Error", Method, 0}, {"(HostnameError).Error", Method, 0}, {"(InsecureAlgorithmError).Error", Method, 6}, {"(OID).AppendBinary", Method, 24}, {"(OID).AppendText", Method, 24}, {"(OID).Equal", Method, 22}, {"(OID).EqualASN1OID", Method, 22}, {"(OID).MarshalBinary", Method, 23}, {"(OID).MarshalText", Method, 23}, {"(OID).String", Method, 22}, {"(PublicKeyAlgorithm).String", Method, 10}, {"(SignatureAlgorithm).String", Method, 6}, {"(SystemRootsError).Error", Method, 1}, {"(SystemRootsError).Unwrap", Method, 16}, {"(UnhandledCriticalExtension).Error", Method, 0}, {"(UnknownAuthorityError).Error", Method, 0}, {"CANotAuthorizedForExtKeyUsage", Const, 10}, {"CANotAuthorizedForThisName", Const, 0}, {"CertPool", Type, 0}, {"Certificate", Type, 0}, {"Certificate.AuthorityKeyId", Field, 0}, {"Certificate.BasicConstraintsValid", Field, 0}, {"Certificate.CRLDistributionPoints", Field, 2}, {"Certificate.DNSNames", Field, 0}, {"Certificate.EmailAddresses", Field, 0}, {"Certificate.ExcludedDNSDomains", Field, 9}, {"Certificate.ExcludedEmailAddresses", Field, 10}, {"Certificate.ExcludedIPRanges", Field, 10}, {"Certificate.ExcludedURIDomains", Field, 10}, {"Certificate.ExtKeyUsage", Field, 0}, {"Certificate.Extensions", Field, 2}, {"Certificate.ExtraExtensions", Field, 2}, {"Certificate.IPAddresses", Field, 1}, {"Certificate.InhibitAnyPolicy", Field, 24}, {"Certificate.InhibitAnyPolicyZero", Field, 24}, {"Certificate.InhibitPolicyMapping", Field, 24}, {"Certificate.InhibitPolicyMappingZero", Field, 24}, {"Certificate.IsCA", Field, 0}, {"Certificate.Issuer", Field, 0}, {"Certificate.IssuingCertificateURL", Field, 2}, {"Certificate.KeyUsage", Field, 0}, {"Certificate.MaxPathLen", Field, 0}, {"Certificate.MaxPathLenZero", Field, 4}, {"Certificate.NotAfter", Field, 0}, {"Certificate.NotBefore", Field, 0}, {"Certificate.OCSPServer", Field, 2}, {"Certificate.PermittedDNSDomains", Field, 0}, {"Certificate.PermittedDNSDomainsCritical", Field, 0}, {"Certificate.PermittedEmailAddresses", Field, 10}, {"Certificate.PermittedIPRanges", Field, 10}, {"Certificate.PermittedURIDomains", Field, 10}, {"Certificate.Policies", Field, 22}, {"Certificate.PolicyIdentifiers", Field, 0}, {"Certificate.PolicyMappings", Field, 24}, {"Certificate.PublicKey", Field, 0}, {"Certificate.PublicKeyAlgorithm", Field, 0}, {"Certificate.Raw", Field, 0}, {"Certificate.RawIssuer", Field, 0}, {"Certificate.RawSubject", Field, 0}, {"Certificate.RawSubjectPublicKeyInfo", Field, 0}, {"Certificate.RawTBSCertificate", Field, 0}, {"Certificate.RequireExplicitPolicy", Field, 24}, {"Certificate.RequireExplicitPolicyZero", Field, 24}, {"Certificate.SerialNumber", Field, 0}, {"Certificate.Signature", Field, 0}, {"Certificate.SignatureAlgorithm", Field, 0}, {"Certificate.Subject", Field, 0}, {"Certificate.SubjectKeyId", Field, 0}, {"Certificate.URIs", Field, 10}, {"Certificate.UnhandledCriticalExtensions", Field, 5}, {"Certificate.UnknownExtKeyUsage", Field, 0}, {"Certificate.Version", Field, 0}, {"CertificateInvalidError", Type, 0}, {"CertificateInvalidError.Cert", Field, 0}, {"CertificateInvalidError.Detail", Field, 10}, {"CertificateInvalidError.Reason", Field, 0}, {"CertificateRequest", Type, 3}, {"CertificateRequest.Attributes", Field, 3}, {"CertificateRequest.DNSNames", Field, 3}, {"CertificateRequest.EmailAddresses", Field, 3}, {"CertificateRequest.Extensions", Field, 3}, {"CertificateRequest.ExtraExtensions", Field, 3}, {"CertificateRequest.IPAddresses", Field, 3}, {"CertificateRequest.PublicKey", Field, 3}, {"CertificateRequest.PublicKeyAlgorithm", Field, 3}, {"CertificateRequest.Raw", Field, 3}, {"CertificateRequest.RawSubject", Field, 3}, {"CertificateRequest.RawSubjectPublicKeyInfo", Field, 3}, {"CertificateRequest.RawTBSCertificateRequest", Field, 3}, {"CertificateRequest.Signature", Field, 3}, {"CertificateRequest.SignatureAlgorithm", Field, 3}, {"CertificateRequest.Subject", Field, 3}, {"CertificateRequest.URIs", Field, 10}, {"CertificateRequest.Version", Field, 3}, {"ConstraintViolationError", Type, 0}, {"CreateCertificate", Func, 0}, {"CreateCertificateRequest", Func, 3}, {"CreateRevocationList", Func, 15}, {"DSA", Const, 0}, {"DSAWithSHA1", Const, 0}, {"DSAWithSHA256", Const, 0}, {"DecryptPEMBlock", Func, 1}, {"ECDSA", Const, 1}, {"ECDSAWithSHA1", Const, 1}, {"ECDSAWithSHA256", Const, 1}, {"ECDSAWithSHA384", Const, 1}, {"ECDSAWithSHA512", Const, 1}, {"Ed25519", Const, 13}, {"EncryptPEMBlock", Func, 1}, {"ErrUnsupportedAlgorithm", Var, 0}, {"Expired", Const, 0}, {"ExtKeyUsage", Type, 0}, {"ExtKeyUsageAny", Const, 0}, {"ExtKeyUsageClientAuth", Const, 0}, {"ExtKeyUsageCodeSigning", Const, 0}, {"ExtKeyUsageEmailProtection", Const, 0}, {"ExtKeyUsageIPSECEndSystem", Const, 1}, {"ExtKeyUsageIPSECTunnel", Const, 1}, {"ExtKeyUsageIPSECUser", Const, 1}, {"ExtKeyUsageMicrosoftCommercialCodeSigning", Const, 10}, {"ExtKeyUsageMicrosoftKernelCodeSigning", Const, 10}, {"ExtKeyUsageMicrosoftServerGatedCrypto", Const, 1}, {"ExtKeyUsageNetscapeServerGatedCrypto", Const, 1}, {"ExtKeyUsageOCSPSigning", Const, 0}, {"ExtKeyUsageServerAuth", Const, 0}, {"ExtKeyUsageTimeStamping", Const, 0}, {"HostnameError", Type, 0}, {"HostnameError.Certificate", Field, 0}, {"HostnameError.Host", Field, 0}, {"IncompatibleUsage", Const, 1}, {"IncorrectPasswordError", Var, 1}, {"InsecureAlgorithmError", Type, 6}, {"InvalidReason", Type, 0}, {"IsEncryptedPEMBlock", Func, 1}, {"KeyUsage", Type, 0}, {"KeyUsageCRLSign", Const, 0}, {"KeyUsageCertSign", Const, 0}, {"KeyUsageContentCommitment", Const, 0}, {"KeyUsageDataEncipherment", Const, 0}, {"KeyUsageDecipherOnly", Const, 0}, {"KeyUsageDigitalSignature", Const, 0}, {"KeyUsageEncipherOnly", Const, 0}, {"KeyUsageKeyAgreement", Const, 0}, {"KeyUsageKeyEncipherment", Const, 0}, {"MD2WithRSA", Const, 0}, {"MD5WithRSA", Const, 0}, {"MarshalECPrivateKey", Func, 2}, {"MarshalPKCS1PrivateKey", Func, 0}, {"MarshalPKCS1PublicKey", Func, 10}, {"MarshalPKCS8PrivateKey", Func, 10}, {"MarshalPKIXPublicKey", Func, 0}, {"NameConstraintsWithoutSANs", Const, 10}, {"NameMismatch", Const, 8}, {"NewCertPool", Func, 0}, {"NoValidChains", Const, 24}, {"NotAuthorizedToSign", Const, 0}, {"OID", Type, 22}, {"OIDFromInts", Func, 22}, {"PEMCipher", Type, 1}, {"PEMCipher3DES", Const, 1}, {"PEMCipherAES128", Const, 1}, {"PEMCipherAES192", Const, 1}, {"PEMCipherAES256", Const, 1}, {"PEMCipherDES", Const, 1}, {"ParseCRL", Func, 0}, {"ParseCertificate", Func, 0}, {"ParseCertificateRequest", Func, 3}, {"ParseCertificates", Func, 0}, {"ParseDERCRL", Func, 0}, {"ParseECPrivateKey", Func, 1}, {"ParseOID", Func, 23}, {"ParsePKCS1PrivateKey", Func, 0}, {"ParsePKCS1PublicKey", Func, 10}, {"ParsePKCS8PrivateKey", Func, 0}, {"ParsePKIXPublicKey", Func, 0}, {"ParseRevocationList", Func, 19}, {"PolicyMapping", Type, 24}, {"PolicyMapping.IssuerDomainPolicy", Field, 24}, {"PolicyMapping.SubjectDomainPolicy", Field, 24}, {"PublicKeyAlgorithm", Type, 0}, {"PureEd25519", Const, 13}, {"RSA", Const, 0}, {"RevocationList", Type, 15}, {"RevocationList.AuthorityKeyId", Field, 19}, {"RevocationList.Extensions", Field, 19}, {"RevocationList.ExtraExtensions", Field, 15}, {"RevocationList.Issuer", Field, 19}, {"RevocationList.NextUpdate", Field, 15}, {"RevocationList.Number", Field, 15}, {"RevocationList.Raw", Field, 19}, {"RevocationList.RawIssuer", Field, 19}, {"RevocationList.RawTBSRevocationList", Field, 19}, {"RevocationList.RevokedCertificateEntries", Field, 21}, {"RevocationList.RevokedCertificates", Field, 15}, {"RevocationList.Signature", Field, 19}, {"RevocationList.SignatureAlgorithm", Field, 15}, {"RevocationList.ThisUpdate", Field, 15}, {"RevocationListEntry", Type, 21}, {"RevocationListEntry.Extensions", Field, 21}, {"RevocationListEntry.ExtraExtensions", Field, 21}, {"RevocationListEntry.Raw", Field, 21}, {"RevocationListEntry.ReasonCode", Field, 21}, {"RevocationListEntry.RevocationTime", Field, 21}, {"RevocationListEntry.SerialNumber", Field, 21}, {"SHA1WithRSA", Const, 0}, {"SHA256WithRSA", Const, 0}, {"SHA256WithRSAPSS", Const, 8}, {"SHA384WithRSA", Const, 0}, {"SHA384WithRSAPSS", Const, 8}, {"SHA512WithRSA", Const, 0}, {"SHA512WithRSAPSS", Const, 8}, {"SetFallbackRoots", Func, 20}, {"SignatureAlgorithm", Type, 0}, {"SystemCertPool", Func, 7}, {"SystemRootsError", Type, 1}, {"SystemRootsError.Err", Field, 7}, {"TooManyConstraints", Const, 10}, {"TooManyIntermediates", Const, 0}, {"UnconstrainedName", Const, 10}, {"UnhandledCriticalExtension", Type, 0}, {"UnknownAuthorityError", Type, 0}, {"UnknownAuthorityError.Cert", Field, 8}, {"UnknownPublicKeyAlgorithm", Const, 0}, {"UnknownSignatureAlgorithm", Const, 0}, {"VerifyOptions", Type, 0}, {"VerifyOptions.CertificatePolicies", Field, 24}, {"VerifyOptions.CurrentTime", Field, 0}, {"VerifyOptions.DNSName", Field, 0}, {"VerifyOptions.Intermediates", Field, 0}, {"VerifyOptions.KeyUsages", Field, 1}, {"VerifyOptions.MaxConstraintComparisions", Field, 10}, {"VerifyOptions.Roots", Field, 0}, }, "crypto/x509/pkix": { {"(*CertificateList).HasExpired", Method, 0}, {"(*Name).FillFromRDNSequence", Method, 0}, {"(Name).String", Method, 10}, {"(Name).ToRDNSequence", Method, 0}, {"(RDNSequence).String", Method, 10}, {"AlgorithmIdentifier", Type, 0}, {"AlgorithmIdentifier.Algorithm", Field, 0}, {"AlgorithmIdentifier.Parameters", Field, 0}, {"AttributeTypeAndValue", Type, 0}, {"AttributeTypeAndValue.Type", Field, 0}, {"AttributeTypeAndValue.Value", Field, 0}, {"AttributeTypeAndValueSET", Type, 3}, {"AttributeTypeAndValueSET.Type", Field, 3}, {"AttributeTypeAndValueSET.Value", Field, 3}, {"CertificateList", Type, 0}, {"CertificateList.SignatureAlgorithm", Field, 0}, {"CertificateList.SignatureValue", Field, 0}, {"CertificateList.TBSCertList", Field, 0}, {"Extension", Type, 0}, {"Extension.Critical", Field, 0}, {"Extension.Id", Field, 0}, {"Extension.Value", Field, 0}, {"Name", Type, 0}, {"Name.CommonName", Field, 0}, {"Name.Country", Field, 0}, {"Name.ExtraNames", Field, 5}, {"Name.Locality", Field, 0}, {"Name.Names", Field, 0}, {"Name.Organization", Field, 0}, {"Name.OrganizationalUnit", Field, 0}, {"Name.PostalCode", Field, 0}, {"Name.Province", Field, 0}, {"Name.SerialNumber", Field, 0}, {"Name.StreetAddress", Field, 0}, {"RDNSequence", Type, 0}, {"RelativeDistinguishedNameSET", Type, 0}, {"RevokedCertificate", Type, 0}, {"RevokedCertificate.Extensions", Field, 0}, {"RevokedCertificate.RevocationTime", Field, 0}, {"RevokedCertificate.SerialNumber", Field, 0}, {"TBSCertificateList", Type, 0}, {"TBSCertificateList.Extensions", Field, 0}, {"TBSCertificateList.Issuer", Field, 0}, {"TBSCertificateList.NextUpdate", Field, 0}, {"TBSCertificateList.Raw", Field, 0}, {"TBSCertificateList.RevokedCertificates", Field, 0}, {"TBSCertificateList.Signature", Field, 0}, {"TBSCertificateList.ThisUpdate", Field, 0}, {"TBSCertificateList.Version", Field, 0}, }, "database/sql": { {"(*ColumnType).DatabaseTypeName", Method, 8}, {"(*ColumnType).DecimalSize", Method, 8}, {"(*ColumnType).Length", Method, 8}, {"(*ColumnType).Name", Method, 8}, {"(*ColumnType).Nullable", Method, 8}, {"(*ColumnType).ScanType", Method, 8}, {"(*Conn).BeginTx", Method, 9}, {"(*Conn).Close", Method, 9}, {"(*Conn).ExecContext", Method, 9}, {"(*Conn).PingContext", Method, 9}, {"(*Conn).PrepareContext", Method, 9}, {"(*Conn).QueryContext", Method, 9}, {"(*Conn).QueryRowContext", Method, 9}, {"(*Conn).Raw", Method, 13}, {"(*DB).Begin", Method, 0}, {"(*DB).BeginTx", Method, 8}, {"(*DB).Close", Method, 0}, {"(*DB).Conn", Method, 9}, {"(*DB).Driver", Method, 0}, {"(*DB).Exec", Method, 0}, {"(*DB).ExecContext", Method, 8}, {"(*DB).Ping", Method, 1}, {"(*DB).PingContext", Method, 8}, {"(*DB).Prepare", Method, 0}, {"(*DB).PrepareContext", Method, 8}, {"(*DB).Query", Method, 0}, {"(*DB).QueryContext", Method, 8}, {"(*DB).QueryRow", Method, 0}, {"(*DB).QueryRowContext", Method, 8}, {"(*DB).SetConnMaxIdleTime", Method, 15}, {"(*DB).SetConnMaxLifetime", Method, 6}, {"(*DB).SetMaxIdleConns", Method, 1}, {"(*DB).SetMaxOpenConns", Method, 2}, {"(*DB).Stats", Method, 5}, {"(*Null).Scan", Method, 22}, {"(*NullBool).Scan", Method, 0}, {"(*NullByte).Scan", Method, 17}, {"(*NullFloat64).Scan", Method, 0}, {"(*NullInt16).Scan", Method, 17}, {"(*NullInt32).Scan", Method, 13}, {"(*NullInt64).Scan", Method, 0}, {"(*NullString).Scan", Method, 0}, {"(*NullTime).Scan", Method, 13}, {"(*Row).Err", Method, 15}, {"(*Row).Scan", Method, 0}, {"(*Rows).Close", Method, 0}, {"(*Rows).ColumnTypes", Method, 8}, {"(*Rows).Columns", Method, 0}, {"(*Rows).Err", Method, 0}, {"(*Rows).Next", Method, 0}, {"(*Rows).NextResultSet", Method, 8}, {"(*Rows).Scan", Method, 0}, {"(*Stmt).Close", Method, 0}, {"(*Stmt).Exec", Method, 0}, {"(*Stmt).ExecContext", Method, 8}, {"(*Stmt).Query", Method, 0}, {"(*Stmt).QueryContext", Method, 8}, {"(*Stmt).QueryRow", Method, 0}, {"(*Stmt).QueryRowContext", Method, 8}, {"(*Tx).Commit", Method, 0}, {"(*Tx).Exec", Method, 0}, {"(*Tx).ExecContext", Method, 8}, {"(*Tx).Prepare", Method, 0}, {"(*Tx).PrepareContext", Method, 8}, {"(*Tx).Query", Method, 0}, {"(*Tx).QueryContext", Method, 8}, {"(*Tx).QueryRow", Method, 0}, {"(*Tx).QueryRowContext", Method, 8}, {"(*Tx).Rollback", Method, 0}, {"(*Tx).Stmt", Method, 0}, {"(*Tx).StmtContext", Method, 8}, {"(IsolationLevel).String", Method, 11}, {"(Null).Value", Method, 22}, {"(NullBool).Value", Method, 0}, {"(NullByte).Value", Method, 17}, {"(NullFloat64).Value", Method, 0}, {"(NullInt16).Value", Method, 17}, {"(NullInt32).Value", Method, 13}, {"(NullInt64).Value", Method, 0}, {"(NullString).Value", Method, 0}, {"(NullTime).Value", Method, 13}, {"ColumnType", Type, 8}, {"Conn", Type, 9}, {"DB", Type, 0}, {"DBStats", Type, 5}, {"DBStats.Idle", Field, 11}, {"DBStats.InUse", Field, 11}, {"DBStats.MaxIdleClosed", Field, 11}, {"DBStats.MaxIdleTimeClosed", Field, 15}, {"DBStats.MaxLifetimeClosed", Field, 11}, {"DBStats.MaxOpenConnections", Field, 11}, {"DBStats.OpenConnections", Field, 5}, {"DBStats.WaitCount", Field, 11}, {"DBStats.WaitDuration", Field, 11}, {"Drivers", Func, 4}, {"ErrConnDone", Var, 9}, {"ErrNoRows", Var, 0}, {"ErrTxDone", Var, 0}, {"IsolationLevel", Type, 8}, {"LevelDefault", Const, 8}, {"LevelLinearizable", Const, 8}, {"LevelReadCommitted", Const, 8}, {"LevelReadUncommitted", Const, 8}, {"LevelRepeatableRead", Const, 8}, {"LevelSerializable", Const, 8}, {"LevelSnapshot", Const, 8}, {"LevelWriteCommitted", Const, 8}, {"Named", Func, 8}, {"NamedArg", Type, 8}, {"NamedArg.Name", Field, 8}, {"NamedArg.Value", Field, 8}, {"Null", Type, 22}, {"Null.V", Field, 22}, {"Null.Valid", Field, 22}, {"NullBool", Type, 0}, {"NullBool.Bool", Field, 0}, {"NullBool.Valid", Field, 0}, {"NullByte", Type, 17}, {"NullByte.Byte", Field, 17}, {"NullByte.Valid", Field, 17}, {"NullFloat64", Type, 0}, {"NullFloat64.Float64", Field, 0}, {"NullFloat64.Valid", Field, 0}, {"NullInt16", Type, 17}, {"NullInt16.Int16", Field, 17}, {"NullInt16.Valid", Field, 17}, {"NullInt32", Type, 13}, {"NullInt32.Int32", Field, 13}, {"NullInt32.Valid", Field, 13}, {"NullInt64", Type, 0}, {"NullInt64.Int64", Field, 0}, {"NullInt64.Valid", Field, 0}, {"NullString", Type, 0}, {"NullString.String", Field, 0}, {"NullString.Valid", Field, 0}, {"NullTime", Type, 13}, {"NullTime.Time", Field, 13}, {"NullTime.Valid", Field, 13}, {"Open", Func, 0}, {"OpenDB", Func, 10}, {"Out", Type, 9}, {"Out.Dest", Field, 9}, {"Out.In", Field, 9}, {"RawBytes", Type, 0}, {"Register", Func, 0}, {"Result", Type, 0}, {"Row", Type, 0}, {"Rows", Type, 0}, {"Scanner", Type, 0}, {"Stmt", Type, 0}, {"Tx", Type, 0}, {"TxOptions", Type, 8}, {"TxOptions.Isolation", Field, 8}, {"TxOptions.ReadOnly", Field, 8}, }, "database/sql/driver": { {"(NotNull).ConvertValue", Method, 0}, {"(Null).ConvertValue", Method, 0}, {"(RowsAffected).LastInsertId", Method, 0}, {"(RowsAffected).RowsAffected", Method, 0}, {"Bool", Var, 0}, {"ColumnConverter", Type, 0}, {"Conn", Type, 0}, {"ConnBeginTx", Type, 8}, {"ConnPrepareContext", Type, 8}, {"Connector", Type, 10}, {"DefaultParameterConverter", Var, 0}, {"Driver", Type, 0}, {"DriverContext", Type, 10}, {"ErrBadConn", Var, 0}, {"ErrRemoveArgument", Var, 9}, {"ErrSkip", Var, 0}, {"Execer", Type, 0}, {"ExecerContext", Type, 8}, {"Int32", Var, 0}, {"IsScanValue", Func, 0}, {"IsValue", Func, 0}, {"IsolationLevel", Type, 8}, {"NamedValue", Type, 8}, {"NamedValue.Name", Field, 8}, {"NamedValue.Ordinal", Field, 8}, {"NamedValue.Value", Field, 8}, {"NamedValueChecker", Type, 9}, {"NotNull", Type, 0}, {"NotNull.Converter", Field, 0}, {"Null", Type, 0}, {"Null.Converter", Field, 0}, {"Pinger", Type, 8}, {"Queryer", Type, 1}, {"QueryerContext", Type, 8}, {"Result", Type, 0}, {"ResultNoRows", Var, 0}, {"Rows", Type, 0}, {"RowsAffected", Type, 0}, {"RowsColumnTypeDatabaseTypeName", Type, 8}, {"RowsColumnTypeLength", Type, 8}, {"RowsColumnTypeNullable", Type, 8}, {"RowsColumnTypePrecisionScale", Type, 8}, {"RowsColumnTypeScanType", Type, 8}, {"RowsNextResultSet", Type, 8}, {"SessionResetter", Type, 10}, {"Stmt", Type, 0}, {"StmtExecContext", Type, 8}, {"StmtQueryContext", Type, 8}, {"String", Var, 0}, {"Tx", Type, 0}, {"TxOptions", Type, 8}, {"TxOptions.Isolation", Field, 8}, {"TxOptions.ReadOnly", Field, 8}, {"Validator", Type, 15}, {"Value", Type, 0}, {"ValueConverter", Type, 0}, {"Valuer", Type, 0}, }, "debug/buildinfo": { {"BuildInfo", Type, 18}, {"Read", Func, 18}, {"ReadFile", Func, 18}, }, "debug/dwarf": { {"(*AddrType).Basic", Method, 0}, {"(*AddrType).Common", Method, 0}, {"(*AddrType).Size", Method, 0}, {"(*AddrType).String", Method, 0}, {"(*ArrayType).Common", Method, 0}, {"(*ArrayType).Size", Method, 0}, {"(*ArrayType).String", Method, 0}, {"(*BasicType).Basic", Method, 0}, {"(*BasicType).Common", Method, 0}, {"(*BasicType).Size", Method, 0}, {"(*BasicType).String", Method, 0}, {"(*BoolType).Basic", Method, 0}, {"(*BoolType).Common", Method, 0}, {"(*BoolType).Size", Method, 0}, {"(*BoolType).String", Method, 0}, {"(*CharType).Basic", Method, 0}, {"(*CharType).Common", Method, 0}, {"(*CharType).Size", Method, 0}, {"(*CharType).String", Method, 0}, {"(*CommonType).Common", Method, 0}, {"(*CommonType).Size", Method, 0}, {"(*ComplexType).Basic", Method, 0}, {"(*ComplexType).Common", Method, 0}, {"(*ComplexType).Size", Method, 0}, {"(*ComplexType).String", Method, 0}, {"(*Data).AddSection", Method, 14}, {"(*Data).AddTypes", Method, 3}, {"(*Data).LineReader", Method, 5}, {"(*Data).Ranges", Method, 7}, {"(*Data).Reader", Method, 0}, {"(*Data).Type", Method, 0}, {"(*DotDotDotType).Common", Method, 0}, {"(*DotDotDotType).Size", Method, 0}, {"(*DotDotDotType).String", Method, 0}, {"(*Entry).AttrField", Method, 5}, {"(*Entry).Val", Method, 0}, {"(*EnumType).Common", Method, 0}, {"(*EnumType).Size", Method, 0}, {"(*EnumType).String", Method, 0}, {"(*FloatType).Basic", Method, 0}, {"(*FloatType).Common", Method, 0}, {"(*FloatType).Size", Method, 0}, {"(*FloatType).String", Method, 0}, {"(*FuncType).Common", Method, 0}, {"(*FuncType).Size", Method, 0}, {"(*FuncType).String", Method, 0}, {"(*IntType).Basic", Method, 0}, {"(*IntType).Common", Method, 0}, {"(*IntType).Size", Method, 0}, {"(*IntType).String", Method, 0}, {"(*LineReader).Files", Method, 14}, {"(*LineReader).Next", Method, 5}, {"(*LineReader).Reset", Method, 5}, {"(*LineReader).Seek", Method, 5}, {"(*LineReader).SeekPC", Method, 5}, {"(*LineReader).Tell", Method, 5}, {"(*PtrType).Common", Method, 0}, {"(*PtrType).Size", Method, 0}, {"(*PtrType).String", Method, 0}, {"(*QualType).Common", Method, 0}, {"(*QualType).Size", Method, 0}, {"(*QualType).String", Method, 0}, {"(*Reader).AddressSize", Method, 5}, {"(*Reader).ByteOrder", Method, 14}, {"(*Reader).Next", Method, 0}, {"(*Reader).Seek", Method, 0}, {"(*Reader).SeekPC", Method, 7}, {"(*Reader).SkipChildren", Method, 0}, {"(*StructType).Common", Method, 0}, {"(*StructType).Defn", Method, 0}, {"(*StructType).Size", Method, 0}, {"(*StructType).String", Method, 0}, {"(*TypedefType).Common", Method, 0}, {"(*TypedefType).Size", Method, 0}, {"(*TypedefType).String", Method, 0}, {"(*UcharType).Basic", Method, 0}, {"(*UcharType).Common", Method, 0}, {"(*UcharType).Size", Method, 0}, {"(*UcharType).String", Method, 0}, {"(*UintType).Basic", Method, 0}, {"(*UintType).Common", Method, 0}, {"(*UintType).Size", Method, 0}, {"(*UintType).String", Method, 0}, {"(*UnspecifiedType).Basic", Method, 4}, {"(*UnspecifiedType).Common", Method, 4}, {"(*UnspecifiedType).Size", Method, 4}, {"(*UnspecifiedType).String", Method, 4}, {"(*UnsupportedType).Common", Method, 13}, {"(*UnsupportedType).Size", Method, 13}, {"(*UnsupportedType).String", Method, 13}, {"(*VoidType).Common", Method, 0}, {"(*VoidType).Size", Method, 0}, {"(*VoidType).String", Method, 0}, {"(Attr).GoString", Method, 0}, {"(Attr).String", Method, 0}, {"(Class).GoString", Method, 5}, {"(Class).String", Method, 5}, {"(DecodeError).Error", Method, 0}, {"(Tag).GoString", Method, 0}, {"(Tag).String", Method, 0}, {"AddrType", Type, 0}, {"AddrType.BasicType", Field, 0}, {"ArrayType", Type, 0}, {"ArrayType.CommonType", Field, 0}, {"ArrayType.Count", Field, 0}, {"ArrayType.StrideBitSize", Field, 0}, {"ArrayType.Type", Field, 0}, {"Attr", Type, 0}, {"AttrAbstractOrigin", Const, 0}, {"AttrAccessibility", Const, 0}, {"AttrAddrBase", Const, 14}, {"AttrAddrClass", Const, 0}, {"AttrAlignment", Const, 14}, {"AttrAllocated", Const, 0}, {"AttrArtificial", Const, 0}, {"AttrAssociated", Const, 0}, {"AttrBaseTypes", Const, 0}, {"AttrBinaryScale", Const, 14}, {"AttrBitOffset", Const, 0}, {"AttrBitSize", Const, 0}, {"AttrByteSize", Const, 0}, {"AttrCallAllCalls", Const, 14}, {"AttrCallAllSourceCalls", Const, 14}, {"AttrCallAllTailCalls", Const, 14}, {"AttrCallColumn", Const, 0}, {"AttrCallDataLocation", Const, 14}, {"AttrCallDataValue", Const, 14}, {"AttrCallFile", Const, 0}, {"AttrCallLine", Const, 0}, {"AttrCallOrigin", Const, 14}, {"AttrCallPC", Const, 14}, {"AttrCallParameter", Const, 14}, {"AttrCallReturnPC", Const, 14}, {"AttrCallTailCall", Const, 14}, {"AttrCallTarget", Const, 14}, {"AttrCallTargetClobbered", Const, 14}, {"AttrCallValue", Const, 14}, {"AttrCalling", Const, 0}, {"AttrCommonRef", Const, 0}, {"AttrCompDir", Const, 0}, {"AttrConstExpr", Const, 14}, {"AttrConstValue", Const, 0}, {"AttrContainingType", Const, 0}, {"AttrCount", Const, 0}, {"AttrDataBitOffset", Const, 14}, {"AttrDataLocation", Const, 0}, {"AttrDataMemberLoc", Const, 0}, {"AttrDecimalScale", Const, 14}, {"AttrDecimalSign", Const, 14}, {"AttrDeclColumn", Const, 0}, {"AttrDeclFile", Const, 0}, {"AttrDeclLine", Const, 0}, {"AttrDeclaration", Const, 0}, {"AttrDefaultValue", Const, 0}, {"AttrDefaulted", Const, 14}, {"AttrDeleted", Const, 14}, {"AttrDescription", Const, 0}, {"AttrDigitCount", Const, 14}, {"AttrDiscr", Const, 0}, {"AttrDiscrList", Const, 0}, {"AttrDiscrValue", Const, 0}, {"AttrDwoName", Const, 14}, {"AttrElemental", Const, 14}, {"AttrEncoding", Const, 0}, {"AttrEndianity", Const, 14}, {"AttrEntrypc", Const, 0}, {"AttrEnumClass", Const, 14}, {"AttrExplicit", Const, 14}, {"AttrExportSymbols", Const, 14}, {"AttrExtension", Const, 0}, {"AttrExternal", Const, 0}, {"AttrFrameBase", Const, 0}, {"AttrFriend", Const, 0}, {"AttrHighpc", Const, 0}, {"AttrIdentifierCase", Const, 0}, {"AttrImport", Const, 0}, {"AttrInline", Const, 0}, {"AttrIsOptional", Const, 0}, {"AttrLanguage", Const, 0}, {"AttrLinkageName", Const, 14}, {"AttrLocation", Const, 0}, {"AttrLoclistsBase", Const, 14}, {"AttrLowerBound", Const, 0}, {"AttrLowpc", Const, 0}, {"AttrMacroInfo", Const, 0}, {"AttrMacros", Const, 14}, {"AttrMainSubprogram", Const, 14}, {"AttrMutable", Const, 14}, {"AttrName", Const, 0}, {"AttrNamelistItem", Const, 0}, {"AttrNoreturn", Const, 14}, {"AttrObjectPointer", Const, 14}, {"AttrOrdering", Const, 0}, {"AttrPictureString", Const, 14}, {"AttrPriority", Const, 0}, {"AttrProducer", Const, 0}, {"AttrPrototyped", Const, 0}, {"AttrPure", Const, 14}, {"AttrRanges", Const, 0}, {"AttrRank", Const, 14}, {"AttrRecursive", Const, 14}, {"AttrReference", Const, 14}, {"AttrReturnAddr", Const, 0}, {"AttrRnglistsBase", Const, 14}, {"AttrRvalueReference", Const, 14}, {"AttrSegment", Const, 0}, {"AttrSibling", Const, 0}, {"AttrSignature", Const, 14}, {"AttrSmall", Const, 14}, {"AttrSpecification", Const, 0}, {"AttrStartScope", Const, 0}, {"AttrStaticLink", Const, 0}, {"AttrStmtList", Const, 0}, {"AttrStrOffsetsBase", Const, 14}, {"AttrStride", Const, 0}, {"AttrStrideSize", Const, 0}, {"AttrStringLength", Const, 0}, {"AttrStringLengthBitSize", Const, 14}, {"AttrStringLengthByteSize", Const, 14}, {"AttrThreadsScaled", Const, 14}, {"AttrTrampoline", Const, 0}, {"AttrType", Const, 0}, {"AttrUpperBound", Const, 0}, {"AttrUseLocation", Const, 0}, {"AttrUseUTF8", Const, 0}, {"AttrVarParam", Const, 0}, {"AttrVirtuality", Const, 0}, {"AttrVisibility", Const, 0}, {"AttrVtableElemLoc", Const, 0}, {"BasicType", Type, 0}, {"BasicType.BitOffset", Field, 0}, {"BasicType.BitSize", Field, 0}, {"BasicType.CommonType", Field, 0}, {"BasicType.DataBitOffset", Field, 18}, {"BoolType", Type, 0}, {"BoolType.BasicType", Field, 0}, {"CharType", Type, 0}, {"CharType.BasicType", Field, 0}, {"Class", Type, 5}, {"ClassAddrPtr", Const, 14}, {"ClassAddress", Const, 5}, {"ClassBlock", Const, 5}, {"ClassConstant", Const, 5}, {"ClassExprLoc", Const, 5}, {"ClassFlag", Const, 5}, {"ClassLinePtr", Const, 5}, {"ClassLocList", Const, 14}, {"ClassLocListPtr", Const, 5}, {"ClassMacPtr", Const, 5}, {"ClassRangeListPtr", Const, 5}, {"ClassReference", Const, 5}, {"ClassReferenceAlt", Const, 5}, {"ClassReferenceSig", Const, 5}, {"ClassRngList", Const, 14}, {"ClassRngListsPtr", Const, 14}, {"ClassStrOffsetsPtr", Const, 14}, {"ClassString", Const, 5}, {"ClassStringAlt", Const, 5}, {"ClassUnknown", Const, 6}, {"CommonType", Type, 0}, {"CommonType.ByteSize", Field, 0}, {"CommonType.Name", Field, 0}, {"ComplexType", Type, 0}, {"ComplexType.BasicType", Field, 0}, {"Data", Type, 0}, {"DecodeError", Type, 0}, {"DecodeError.Err", Field, 0}, {"DecodeError.Name", Field, 0}, {"DecodeError.Offset", Field, 0}, {"DotDotDotType", Type, 0}, {"DotDotDotType.CommonType", Field, 0}, {"Entry", Type, 0}, {"Entry.Children", Field, 0}, {"Entry.Field", Field, 0}, {"Entry.Offset", Field, 0}, {"Entry.Tag", Field, 0}, {"EnumType", Type, 0}, {"EnumType.CommonType", Field, 0}, {"EnumType.EnumName", Field, 0}, {"EnumType.Val", Field, 0}, {"EnumValue", Type, 0}, {"EnumValue.Name", Field, 0}, {"EnumValue.Val", Field, 0}, {"ErrUnknownPC", Var, 5}, {"Field", Type, 0}, {"Field.Attr", Field, 0}, {"Field.Class", Field, 5}, {"Field.Val", Field, 0}, {"FloatType", Type, 0}, {"FloatType.BasicType", Field, 0}, {"FuncType", Type, 0}, {"FuncType.CommonType", Field, 0}, {"FuncType.ParamType", Field, 0}, {"FuncType.ReturnType", Field, 0}, {"IntType", Type, 0}, {"IntType.BasicType", Field, 0}, {"LineEntry", Type, 5}, {"LineEntry.Address", Field, 5}, {"LineEntry.BasicBlock", Field, 5}, {"LineEntry.Column", Field, 5}, {"LineEntry.Discriminator", Field, 5}, {"LineEntry.EndSequence", Field, 5}, {"LineEntry.EpilogueBegin", Field, 5}, {"LineEntry.File", Field, 5}, {"LineEntry.ISA", Field, 5}, {"LineEntry.IsStmt", Field, 5}, {"LineEntry.Line", Field, 5}, {"LineEntry.OpIndex", Field, 5}, {"LineEntry.PrologueEnd", Field, 5}, {"LineFile", Type, 5}, {"LineFile.Length", Field, 5}, {"LineFile.Mtime", Field, 5}, {"LineFile.Name", Field, 5}, {"LineReader", Type, 5}, {"LineReaderPos", Type, 5}, {"New", Func, 0}, {"Offset", Type, 0}, {"PtrType", Type, 0}, {"PtrType.CommonType", Field, 0}, {"PtrType.Type", Field, 0}, {"QualType", Type, 0}, {"QualType.CommonType", Field, 0}, {"QualType.Qual", Field, 0}, {"QualType.Type", Field, 0}, {"Reader", Type, 0}, {"StructField", Type, 0}, {"StructField.BitOffset", Field, 0}, {"StructField.BitSize", Field, 0}, {"StructField.ByteOffset", Field, 0}, {"StructField.ByteSize", Field, 0}, {"StructField.DataBitOffset", Field, 18}, {"StructField.Name", Field, 0}, {"StructField.Type", Field, 0}, {"StructType", Type, 0}, {"StructType.CommonType", Field, 0}, {"StructType.Field", Field, 0}, {"StructType.Incomplete", Field, 0}, {"StructType.Kind", Field, 0}, {"StructType.StructName", Field, 0}, {"Tag", Type, 0}, {"TagAccessDeclaration", Const, 0}, {"TagArrayType", Const, 0}, {"TagAtomicType", Const, 14}, {"TagBaseType", Const, 0}, {"TagCallSite", Const, 14}, {"TagCallSiteParameter", Const, 14}, {"TagCatchDwarfBlock", Const, 0}, {"TagClassType", Const, 0}, {"TagCoarrayType", Const, 14}, {"TagCommonDwarfBlock", Const, 0}, {"TagCommonInclusion", Const, 0}, {"TagCompileUnit", Const, 0}, {"TagCondition", Const, 3}, {"TagConstType", Const, 0}, {"TagConstant", Const, 0}, {"TagDwarfProcedure", Const, 0}, {"TagDynamicType", Const, 14}, {"TagEntryPoint", Const, 0}, {"TagEnumerationType", Const, 0}, {"TagEnumerator", Const, 0}, {"TagFileType", Const, 0}, {"TagFormalParameter", Const, 0}, {"TagFriend", Const, 0}, {"TagGenericSubrange", Const, 14}, {"TagImmutableType", Const, 14}, {"TagImportedDeclaration", Const, 0}, {"TagImportedModule", Const, 0}, {"TagImportedUnit", Const, 0}, {"TagInheritance", Const, 0}, {"TagInlinedSubroutine", Const, 0}, {"TagInterfaceType", Const, 0}, {"TagLabel", Const, 0}, {"TagLexDwarfBlock", Const, 0}, {"TagMember", Const, 0}, {"TagModule", Const, 0}, {"TagMutableType", Const, 0}, {"TagNamelist", Const, 0}, {"TagNamelistItem", Const, 0}, {"TagNamespace", Const, 0}, {"TagPackedType", Const, 0}, {"TagPartialUnit", Const, 0}, {"TagPointerType", Const, 0}, {"TagPtrToMemberType", Const, 0}, {"TagReferenceType", Const, 0}, {"TagRestrictType", Const, 0}, {"TagRvalueReferenceType", Const, 3}, {"TagSetType", Const, 0}, {"TagSharedType", Const, 3}, {"TagSkeletonUnit", Const, 14}, {"TagStringType", Const, 0}, {"TagStructType", Const, 0}, {"TagSubprogram", Const, 0}, {"TagSubrangeType", Const, 0}, {"TagSubroutineType", Const, 0}, {"TagTemplateAlias", Const, 3}, {"TagTemplateTypeParameter", Const, 0}, {"TagTemplateValueParameter", Const, 0}, {"TagThrownType", Const, 0}, {"TagTryDwarfBlock", Const, 0}, {"TagTypeUnit", Const, 3}, {"TagTypedef", Const, 0}, {"TagUnionType", Const, 0}, {"TagUnspecifiedParameters", Const, 0}, {"TagUnspecifiedType", Const, 0}, {"TagVariable", Const, 0}, {"TagVariant", Const, 0}, {"TagVariantPart", Const, 0}, {"TagVolatileType", Const, 0}, {"TagWithStmt", Const, 0}, {"Type", Type, 0}, {"TypedefType", Type, 0}, {"TypedefType.CommonType", Field, 0}, {"TypedefType.Type", Field, 0}, {"UcharType", Type, 0}, {"UcharType.BasicType", Field, 0}, {"UintType", Type, 0}, {"UintType.BasicType", Field, 0}, {"UnspecifiedType", Type, 4}, {"UnspecifiedType.BasicType", Field, 4}, {"UnsupportedType", Type, 13}, {"UnsupportedType.CommonType", Field, 13}, {"UnsupportedType.Tag", Field, 13}, {"VoidType", Type, 0}, {"VoidType.CommonType", Field, 0}, }, "debug/elf": { {"(*File).Close", Method, 0}, {"(*File).DWARF", Method, 0}, {"(*File).DynString", Method, 1}, {"(*File).DynValue", Method, 21}, {"(*File).DynamicSymbols", Method, 4}, {"(*File).DynamicVersionNeeds", Method, 24}, {"(*File).DynamicVersions", Method, 24}, {"(*File).ImportedLibraries", Method, 0}, {"(*File).ImportedSymbols", Method, 0}, {"(*File).Section", Method, 0}, {"(*File).SectionByType", Method, 0}, {"(*File).Symbols", Method, 0}, {"(*FormatError).Error", Method, 0}, {"(*Prog).Open", Method, 0}, {"(*Section).Data", Method, 0}, {"(*Section).Open", Method, 0}, {"(Class).GoString", Method, 0}, {"(Class).String", Method, 0}, {"(CompressionType).GoString", Method, 6}, {"(CompressionType).String", Method, 6}, {"(Data).GoString", Method, 0}, {"(Data).String", Method, 0}, {"(DynFlag).GoString", Method, 0}, {"(DynFlag).String", Method, 0}, {"(DynFlag1).GoString", Method, 21}, {"(DynFlag1).String", Method, 21}, {"(DynTag).GoString", Method, 0}, {"(DynTag).String", Method, 0}, {"(Machine).GoString", Method, 0}, {"(Machine).String", Method, 0}, {"(NType).GoString", Method, 0}, {"(NType).String", Method, 0}, {"(OSABI).GoString", Method, 0}, {"(OSABI).String", Method, 0}, {"(Prog).ReadAt", Method, 0}, {"(ProgFlag).GoString", Method, 0}, {"(ProgFlag).String", Method, 0}, {"(ProgType).GoString", Method, 0}, {"(ProgType).String", Method, 0}, {"(R_386).GoString", Method, 0}, {"(R_386).String", Method, 0}, {"(R_390).GoString", Method, 7}, {"(R_390).String", Method, 7}, {"(R_AARCH64).GoString", Method, 4}, {"(R_AARCH64).String", Method, 4}, {"(R_ALPHA).GoString", Method, 0}, {"(R_ALPHA).String", Method, 0}, {"(R_ARM).GoString", Method, 0}, {"(R_ARM).String", Method, 0}, {"(R_LARCH).GoString", Method, 19}, {"(R_LARCH).String", Method, 19}, {"(R_MIPS).GoString", Method, 6}, {"(R_MIPS).String", Method, 6}, {"(R_PPC).GoString", Method, 0}, {"(R_PPC).String", Method, 0}, {"(R_PPC64).GoString", Method, 5}, {"(R_PPC64).String", Method, 5}, {"(R_RISCV).GoString", Method, 11}, {"(R_RISCV).String", Method, 11}, {"(R_SPARC).GoString", Method, 0}, {"(R_SPARC).String", Method, 0}, {"(R_X86_64).GoString", Method, 0}, {"(R_X86_64).String", Method, 0}, {"(Section).ReadAt", Method, 0}, {"(SectionFlag).GoString", Method, 0}, {"(SectionFlag).String", Method, 0}, {"(SectionIndex).GoString", Method, 0}, {"(SectionIndex).String", Method, 0}, {"(SectionType).GoString", Method, 0}, {"(SectionType).String", Method, 0}, {"(SymBind).GoString", Method, 0}, {"(SymBind).String", Method, 0}, {"(SymType).GoString", Method, 0}, {"(SymType).String", Method, 0}, {"(SymVis).GoString", Method, 0}, {"(SymVis).String", Method, 0}, {"(Type).GoString", Method, 0}, {"(Type).String", Method, 0}, {"(Version).GoString", Method, 0}, {"(Version).String", Method, 0}, {"(VersionIndex).Index", Method, 24}, {"(VersionIndex).IsHidden", Method, 24}, {"ARM_MAGIC_TRAMP_NUMBER", Const, 0}, {"COMPRESS_HIOS", Const, 6}, {"COMPRESS_HIPROC", Const, 6}, {"COMPRESS_LOOS", Const, 6}, {"COMPRESS_LOPROC", Const, 6}, {"COMPRESS_ZLIB", Const, 6}, {"COMPRESS_ZSTD", Const, 21}, {"Chdr32", Type, 6}, {"Chdr32.Addralign", Field, 6}, {"Chdr32.Size", Field, 6}, {"Chdr32.Type", Field, 6}, {"Chdr64", Type, 6}, {"Chdr64.Addralign", Field, 6}, {"Chdr64.Size", Field, 6}, {"Chdr64.Type", Field, 6}, {"Class", Type, 0}, {"CompressionType", Type, 6}, {"DF_1_CONFALT", Const, 21}, {"DF_1_DIRECT", Const, 21}, {"DF_1_DISPRELDNE", Const, 21}, {"DF_1_DISPRELPND", Const, 21}, {"DF_1_EDITED", Const, 21}, {"DF_1_ENDFILTEE", Const, 21}, {"DF_1_GLOBAL", Const, 21}, {"DF_1_GLOBAUDIT", Const, 21}, {"DF_1_GROUP", Const, 21}, {"DF_1_IGNMULDEF", Const, 21}, {"DF_1_INITFIRST", Const, 21}, {"DF_1_INTERPOSE", Const, 21}, {"DF_1_KMOD", Const, 21}, {"DF_1_LOADFLTR", Const, 21}, {"DF_1_NOCOMMON", Const, 21}, {"DF_1_NODEFLIB", Const, 21}, {"DF_1_NODELETE", Const, 21}, {"DF_1_NODIRECT", Const, 21}, {"DF_1_NODUMP", Const, 21}, {"DF_1_NOHDR", Const, 21}, {"DF_1_NOKSYMS", Const, 21}, {"DF_1_NOOPEN", Const, 21}, {"DF_1_NORELOC", Const, 21}, {"DF_1_NOW", Const, 21}, {"DF_1_ORIGIN", Const, 21}, {"DF_1_PIE", Const, 21}, {"DF_1_SINGLETON", Const, 21}, {"DF_1_STUB", Const, 21}, {"DF_1_SYMINTPOSE", Const, 21}, {"DF_1_TRANS", Const, 21}, {"DF_1_WEAKFILTER", Const, 21}, {"DF_BIND_NOW", Const, 0}, {"DF_ORIGIN", Const, 0}, {"DF_STATIC_TLS", Const, 0}, {"DF_SYMBOLIC", Const, 0}, {"DF_TEXTREL", Const, 0}, {"DT_ADDRRNGHI", Const, 16}, {"DT_ADDRRNGLO", Const, 16}, {"DT_AUDIT", Const, 16}, {"DT_AUXILIARY", Const, 16}, {"DT_BIND_NOW", Const, 0}, {"DT_CHECKSUM", Const, 16}, {"DT_CONFIG", Const, 16}, {"DT_DEBUG", Const, 0}, {"DT_DEPAUDIT", Const, 16}, {"DT_ENCODING", Const, 0}, {"DT_FEATURE", Const, 16}, {"DT_FILTER", Const, 16}, {"DT_FINI", Const, 0}, {"DT_FINI_ARRAY", Const, 0}, {"DT_FINI_ARRAYSZ", Const, 0}, {"DT_FLAGS", Const, 0}, {"DT_FLAGS_1", Const, 16}, {"DT_GNU_CONFLICT", Const, 16}, {"DT_GNU_CONFLICTSZ", Const, 16}, {"DT_GNU_HASH", Const, 16}, {"DT_GNU_LIBLIST", Const, 16}, {"DT_GNU_LIBLISTSZ", Const, 16}, {"DT_GNU_PRELINKED", Const, 16}, {"DT_HASH", Const, 0}, {"DT_HIOS", Const, 0}, {"DT_HIPROC", Const, 0}, {"DT_INIT", Const, 0}, {"DT_INIT_ARRAY", Const, 0}, {"DT_INIT_ARRAYSZ", Const, 0}, {"DT_JMPREL", Const, 0}, {"DT_LOOS", Const, 0}, {"DT_LOPROC", Const, 0}, {"DT_MIPS_AUX_DYNAMIC", Const, 16}, {"DT_MIPS_BASE_ADDRESS", Const, 16}, {"DT_MIPS_COMPACT_SIZE", Const, 16}, {"DT_MIPS_CONFLICT", Const, 16}, {"DT_MIPS_CONFLICTNO", Const, 16}, {"DT_MIPS_CXX_FLAGS", Const, 16}, {"DT_MIPS_DELTA_CLASS", Const, 16}, {"DT_MIPS_DELTA_CLASSSYM", Const, 16}, {"DT_MIPS_DELTA_CLASSSYM_NO", Const, 16}, {"DT_MIPS_DELTA_CLASS_NO", Const, 16}, {"DT_MIPS_DELTA_INSTANCE", Const, 16}, {"DT_MIPS_DELTA_INSTANCE_NO", Const, 16}, {"DT_MIPS_DELTA_RELOC", Const, 16}, {"DT_MIPS_DELTA_RELOC_NO", Const, 16}, {"DT_MIPS_DELTA_SYM", Const, 16}, {"DT_MIPS_DELTA_SYM_NO", Const, 16}, {"DT_MIPS_DYNSTR_ALIGN", Const, 16}, {"DT_MIPS_FLAGS", Const, 16}, {"DT_MIPS_GOTSYM", Const, 16}, {"DT_MIPS_GP_VALUE", Const, 16}, {"DT_MIPS_HIDDEN_GOTIDX", Const, 16}, {"DT_MIPS_HIPAGENO", Const, 16}, {"DT_MIPS_ICHECKSUM", Const, 16}, {"DT_MIPS_INTERFACE", Const, 16}, {"DT_MIPS_INTERFACE_SIZE", Const, 16}, {"DT_MIPS_IVERSION", Const, 16}, {"DT_MIPS_LIBLIST", Const, 16}, {"DT_MIPS_LIBLISTNO", Const, 16}, {"DT_MIPS_LOCALPAGE_GOTIDX", Const, 16}, {"DT_MIPS_LOCAL_GOTIDX", Const, 16}, {"DT_MIPS_LOCAL_GOTNO", Const, 16}, {"DT_MIPS_MSYM", Const, 16}, {"DT_MIPS_OPTIONS", Const, 16}, {"DT_MIPS_PERF_SUFFIX", Const, 16}, {"DT_MIPS_PIXIE_INIT", Const, 16}, {"DT_MIPS_PLTGOT", Const, 16}, {"DT_MIPS_PROTECTED_GOTIDX", Const, 16}, {"DT_MIPS_RLD_MAP", Const, 16}, {"DT_MIPS_RLD_MAP_REL", Const, 16}, {"DT_MIPS_RLD_TEXT_RESOLVE_ADDR", Const, 16}, {"DT_MIPS_RLD_VERSION", Const, 16}, {"DT_MIPS_RWPLT", Const, 16}, {"DT_MIPS_SYMBOL_LIB", Const, 16}, {"DT_MIPS_SYMTABNO", Const, 16}, {"DT_MIPS_TIME_STAMP", Const, 16}, {"DT_MIPS_UNREFEXTNO", Const, 16}, {"DT_MOVEENT", Const, 16}, {"DT_MOVESZ", Const, 16}, {"DT_MOVETAB", Const, 16}, {"DT_NEEDED", Const, 0}, {"DT_NULL", Const, 0}, {"DT_PLTGOT", Const, 0}, {"DT_PLTPAD", Const, 16}, {"DT_PLTPADSZ", Const, 16}, {"DT_PLTREL", Const, 0}, {"DT_PLTRELSZ", Const, 0}, {"DT_POSFLAG_1", Const, 16}, {"DT_PPC64_GLINK", Const, 16}, {"DT_PPC64_OPD", Const, 16}, {"DT_PPC64_OPDSZ", Const, 16}, {"DT_PPC64_OPT", Const, 16}, {"DT_PPC_GOT", Const, 16}, {"DT_PPC_OPT", Const, 16}, {"DT_PREINIT_ARRAY", Const, 0}, {"DT_PREINIT_ARRAYSZ", Const, 0}, {"DT_REL", Const, 0}, {"DT_RELA", Const, 0}, {"DT_RELACOUNT", Const, 16}, {"DT_RELAENT", Const, 0}, {"DT_RELASZ", Const, 0}, {"DT_RELCOUNT", Const, 16}, {"DT_RELENT", Const, 0}, {"DT_RELSZ", Const, 0}, {"DT_RPATH", Const, 0}, {"DT_RUNPATH", Const, 0}, {"DT_SONAME", Const, 0}, {"DT_SPARC_REGISTER", Const, 16}, {"DT_STRSZ", Const, 0}, {"DT_STRTAB", Const, 0}, {"DT_SYMBOLIC", Const, 0}, {"DT_SYMENT", Const, 0}, {"DT_SYMINENT", Const, 16}, {"DT_SYMINFO", Const, 16}, {"DT_SYMINSZ", Const, 16}, {"DT_SYMTAB", Const, 0}, {"DT_SYMTAB_SHNDX", Const, 16}, {"DT_TEXTREL", Const, 0}, {"DT_TLSDESC_GOT", Const, 16}, {"DT_TLSDESC_PLT", Const, 16}, {"DT_USED", Const, 16}, {"DT_VALRNGHI", Const, 16}, {"DT_VALRNGLO", Const, 16}, {"DT_VERDEF", Const, 16}, {"DT_VERDEFNUM", Const, 16}, {"DT_VERNEED", Const, 0}, {"DT_VERNEEDNUM", Const, 0}, {"DT_VERSYM", Const, 0}, {"Data", Type, 0}, {"Dyn32", Type, 0}, {"Dyn32.Tag", Field, 0}, {"Dyn32.Val", Field, 0}, {"Dyn64", Type, 0}, {"Dyn64.Tag", Field, 0}, {"Dyn64.Val", Field, 0}, {"DynFlag", Type, 0}, {"DynFlag1", Type, 21}, {"DynTag", Type, 0}, {"DynamicVersion", Type, 24}, {"DynamicVersion.Deps", Field, 24}, {"DynamicVersion.Flags", Field, 24}, {"DynamicVersion.Index", Field, 24}, {"DynamicVersion.Name", Field, 24}, {"DynamicVersionDep", Type, 24}, {"DynamicVersionDep.Dep", Field, 24}, {"DynamicVersionDep.Flags", Field, 24}, {"DynamicVersionDep.Index", Field, 24}, {"DynamicVersionFlag", Type, 24}, {"DynamicVersionNeed", Type, 24}, {"DynamicVersionNeed.Name", Field, 24}, {"DynamicVersionNeed.Needs", Field, 24}, {"EI_ABIVERSION", Const, 0}, {"EI_CLASS", Const, 0}, {"EI_DATA", Const, 0}, {"EI_NIDENT", Const, 0}, {"EI_OSABI", Const, 0}, {"EI_PAD", Const, 0}, {"EI_VERSION", Const, 0}, {"ELFCLASS32", Const, 0}, {"ELFCLASS64", Const, 0}, {"ELFCLASSNONE", Const, 0}, {"ELFDATA2LSB", Const, 0}, {"ELFDATA2MSB", Const, 0}, {"ELFDATANONE", Const, 0}, {"ELFMAG", Const, 0}, {"ELFOSABI_86OPEN", Const, 0}, {"ELFOSABI_AIX", Const, 0}, {"ELFOSABI_ARM", Const, 0}, {"ELFOSABI_AROS", Const, 11}, {"ELFOSABI_CLOUDABI", Const, 11}, {"ELFOSABI_FENIXOS", Const, 11}, {"ELFOSABI_FREEBSD", Const, 0}, {"ELFOSABI_HPUX", Const, 0}, {"ELFOSABI_HURD", Const, 0}, {"ELFOSABI_IRIX", Const, 0}, {"ELFOSABI_LINUX", Const, 0}, {"ELFOSABI_MODESTO", Const, 0}, {"ELFOSABI_NETBSD", Const, 0}, {"ELFOSABI_NONE", Const, 0}, {"ELFOSABI_NSK", Const, 0}, {"ELFOSABI_OPENBSD", Const, 0}, {"ELFOSABI_OPENVMS", Const, 0}, {"ELFOSABI_SOLARIS", Const, 0}, {"ELFOSABI_STANDALONE", Const, 0}, {"ELFOSABI_TRU64", Const, 0}, {"EM_386", Const, 0}, {"EM_486", Const, 0}, {"EM_56800EX", Const, 11}, {"EM_68HC05", Const, 11}, {"EM_68HC08", Const, 11}, {"EM_68HC11", Const, 11}, {"EM_68HC12", Const, 0}, {"EM_68HC16", Const, 11}, {"EM_68K", Const, 0}, {"EM_78KOR", Const, 11}, {"EM_8051", Const, 11}, {"EM_860", Const, 0}, {"EM_88K", Const, 0}, {"EM_960", Const, 0}, {"EM_AARCH64", Const, 4}, {"EM_ALPHA", Const, 0}, {"EM_ALPHA_STD", Const, 0}, {"EM_ALTERA_NIOS2", Const, 11}, {"EM_AMDGPU", Const, 11}, {"EM_ARC", Const, 0}, {"EM_ARCA", Const, 11}, {"EM_ARC_COMPACT", Const, 11}, {"EM_ARC_COMPACT2", Const, 11}, {"EM_ARM", Const, 0}, {"EM_AVR", Const, 11}, {"EM_AVR32", Const, 11}, {"EM_BA1", Const, 11}, {"EM_BA2", Const, 11}, {"EM_BLACKFIN", Const, 11}, {"EM_BPF", Const, 11}, {"EM_C166", Const, 11}, {"EM_CDP", Const, 11}, {"EM_CE", Const, 11}, {"EM_CLOUDSHIELD", Const, 11}, {"EM_COGE", Const, 11}, {"EM_COLDFIRE", Const, 0}, {"EM_COOL", Const, 11}, {"EM_COREA_1ST", Const, 11}, {"EM_COREA_2ND", Const, 11}, {"EM_CR", Const, 11}, {"EM_CR16", Const, 11}, {"EM_CRAYNV2", Const, 11}, {"EM_CRIS", Const, 11}, {"EM_CRX", Const, 11}, {"EM_CSR_KALIMBA", Const, 11}, {"EM_CUDA", Const, 11}, {"EM_CYPRESS_M8C", Const, 11}, {"EM_D10V", Const, 11}, {"EM_D30V", Const, 11}, {"EM_DSP24", Const, 11}, {"EM_DSPIC30F", Const, 11}, {"EM_DXP", Const, 11}, {"EM_ECOG1", Const, 11}, {"EM_ECOG16", Const, 11}, {"EM_ECOG1X", Const, 11}, {"EM_ECOG2", Const, 11}, {"EM_ETPU", Const, 11}, {"EM_EXCESS", Const, 11}, {"EM_F2MC16", Const, 11}, {"EM_FIREPATH", Const, 11}, {"EM_FR20", Const, 0}, {"EM_FR30", Const, 11}, {"EM_FT32", Const, 11}, {"EM_FX66", Const, 11}, {"EM_H8S", Const, 0}, {"EM_H8_300", Const, 0}, {"EM_H8_300H", Const, 0}, {"EM_H8_500", Const, 0}, {"EM_HUANY", Const, 11}, {"EM_IA_64", Const, 0}, {"EM_INTEL205", Const, 11}, {"EM_INTEL206", Const, 11}, {"EM_INTEL207", Const, 11}, {"EM_INTEL208", Const, 11}, {"EM_INTEL209", Const, 11}, {"EM_IP2K", Const, 11}, {"EM_JAVELIN", Const, 11}, {"EM_K10M", Const, 11}, {"EM_KM32", Const, 11}, {"EM_KMX16", Const, 11}, {"EM_KMX32", Const, 11}, {"EM_KMX8", Const, 11}, {"EM_KVARC", Const, 11}, {"EM_L10M", Const, 11}, {"EM_LANAI", Const, 11}, {"EM_LATTICEMICO32", Const, 11}, {"EM_LOONGARCH", Const, 19}, {"EM_M16C", Const, 11}, {"EM_M32", Const, 0}, {"EM_M32C", Const, 11}, {"EM_M32R", Const, 11}, {"EM_MANIK", Const, 11}, {"EM_MAX", Const, 11}, {"EM_MAXQ30", Const, 11}, {"EM_MCHP_PIC", Const, 11}, {"EM_MCST_ELBRUS", Const, 11}, {"EM_ME16", Const, 0}, {"EM_METAG", Const, 11}, {"EM_MICROBLAZE", Const, 11}, {"EM_MIPS", Const, 0}, {"EM_MIPS_RS3_LE", Const, 0}, {"EM_MIPS_RS4_BE", Const, 0}, {"EM_MIPS_X", Const, 0}, {"EM_MMA", Const, 0}, {"EM_MMDSP_PLUS", Const, 11}, {"EM_MMIX", Const, 11}, {"EM_MN10200", Const, 11}, {"EM_MN10300", Const, 11}, {"EM_MOXIE", Const, 11}, {"EM_MSP430", Const, 11}, {"EM_NCPU", Const, 0}, {"EM_NDR1", Const, 0}, {"EM_NDS32", Const, 11}, {"EM_NONE", Const, 0}, {"EM_NORC", Const, 11}, {"EM_NS32K", Const, 11}, {"EM_OPEN8", Const, 11}, {"EM_OPENRISC", Const, 11}, {"EM_PARISC", Const, 0}, {"EM_PCP", Const, 0}, {"EM_PDP10", Const, 11}, {"EM_PDP11", Const, 11}, {"EM_PDSP", Const, 11}, {"EM_PJ", Const, 11}, {"EM_PPC", Const, 0}, {"EM_PPC64", Const, 0}, {"EM_PRISM", Const, 11}, {"EM_QDSP6", Const, 11}, {"EM_R32C", Const, 11}, {"EM_RCE", Const, 0}, {"EM_RH32", Const, 0}, {"EM_RISCV", Const, 11}, {"EM_RL78", Const, 11}, {"EM_RS08", Const, 11}, {"EM_RX", Const, 11}, {"EM_S370", Const, 0}, {"EM_S390", Const, 0}, {"EM_SCORE7", Const, 11}, {"EM_SEP", Const, 11}, {"EM_SE_C17", Const, 11}, {"EM_SE_C33", Const, 11}, {"EM_SH", Const, 0}, {"EM_SHARC", Const, 11}, {"EM_SLE9X", Const, 11}, {"EM_SNP1K", Const, 11}, {"EM_SPARC", Const, 0}, {"EM_SPARC32PLUS", Const, 0}, {"EM_SPARCV9", Const, 0}, {"EM_ST100", Const, 0}, {"EM_ST19", Const, 11}, {"EM_ST200", Const, 11}, {"EM_ST7", Const, 11}, {"EM_ST9PLUS", Const, 11}, {"EM_STARCORE", Const, 0}, {"EM_STM8", Const, 11}, {"EM_STXP7X", Const, 11}, {"EM_SVX", Const, 11}, {"EM_TILE64", Const, 11}, {"EM_TILEGX", Const, 11}, {"EM_TILEPRO", Const, 11}, {"EM_TINYJ", Const, 0}, {"EM_TI_ARP32", Const, 11}, {"EM_TI_C2000", Const, 11}, {"EM_TI_C5500", Const, 11}, {"EM_TI_C6000", Const, 11}, {"EM_TI_PRU", Const, 11}, {"EM_TMM_GPP", Const, 11}, {"EM_TPC", Const, 11}, {"EM_TRICORE", Const, 0}, {"EM_TRIMEDIA", Const, 11}, {"EM_TSK3000", Const, 11}, {"EM_UNICORE", Const, 11}, {"EM_V800", Const, 0}, {"EM_V850", Const, 11}, {"EM_VAX", Const, 11}, {"EM_VIDEOCORE", Const, 11}, {"EM_VIDEOCORE3", Const, 11}, {"EM_VIDEOCORE5", Const, 11}, {"EM_VISIUM", Const, 11}, {"EM_VPP500", Const, 0}, {"EM_X86_64", Const, 0}, {"EM_XCORE", Const, 11}, {"EM_XGATE", Const, 11}, {"EM_XIMO16", Const, 11}, {"EM_XTENSA", Const, 11}, {"EM_Z80", Const, 11}, {"EM_ZSP", Const, 11}, {"ET_CORE", Const, 0}, {"ET_DYN", Const, 0}, {"ET_EXEC", Const, 0}, {"ET_HIOS", Const, 0}, {"ET_HIPROC", Const, 0}, {"ET_LOOS", Const, 0}, {"ET_LOPROC", Const, 0}, {"ET_NONE", Const, 0}, {"ET_REL", Const, 0}, {"EV_CURRENT", Const, 0}, {"EV_NONE", Const, 0}, {"ErrNoSymbols", Var, 4}, {"File", Type, 0}, {"File.FileHeader", Field, 0}, {"File.Progs", Field, 0}, {"File.Sections", Field, 0}, {"FileHeader", Type, 0}, {"FileHeader.ABIVersion", Field, 0}, {"FileHeader.ByteOrder", Field, 0}, {"FileHeader.Class", Field, 0}, {"FileHeader.Data", Field, 0}, {"FileHeader.Entry", Field, 1}, {"FileHeader.Machine", Field, 0}, {"FileHeader.OSABI", Field, 0}, {"FileHeader.Type", Field, 0}, {"FileHeader.Version", Field, 0}, {"FormatError", Type, 0}, {"Header32", Type, 0}, {"Header32.Ehsize", Field, 0}, {"Header32.Entry", Field, 0}, {"Header32.Flags", Field, 0}, {"Header32.Ident", Field, 0}, {"Header32.Machine", Field, 0}, {"Header32.Phentsize", Field, 0}, {"Header32.Phnum", Field, 0}, {"Header32.Phoff", Field, 0}, {"Header32.Shentsize", Field, 0}, {"Header32.Shnum", Field, 0}, {"Header32.Shoff", Field, 0}, {"Header32.Shstrndx", Field, 0}, {"Header32.Type", Field, 0}, {"Header32.Version", Field, 0}, {"Header64", Type, 0}, {"Header64.Ehsize", Field, 0}, {"Header64.Entry", Field, 0}, {"Header64.Flags", Field, 0}, {"Header64.Ident", Field, 0}, {"Header64.Machine", Field, 0}, {"Header64.Phentsize", Field, 0}, {"Header64.Phnum", Field, 0}, {"Header64.Phoff", Field, 0}, {"Header64.Shentsize", Field, 0}, {"Header64.Shnum", Field, 0}, {"Header64.Shoff", Field, 0}, {"Header64.Shstrndx", Field, 0}, {"Header64.Type", Field, 0}, {"Header64.Version", Field, 0}, {"ImportedSymbol", Type, 0}, {"ImportedSymbol.Library", Field, 0}, {"ImportedSymbol.Name", Field, 0}, {"ImportedSymbol.Version", Field, 0}, {"Machine", Type, 0}, {"NT_FPREGSET", Const, 0}, {"NT_PRPSINFO", Const, 0}, {"NT_PRSTATUS", Const, 0}, {"NType", Type, 0}, {"NewFile", Func, 0}, {"OSABI", Type, 0}, {"Open", Func, 0}, {"PF_MASKOS", Const, 0}, {"PF_MASKPROC", Const, 0}, {"PF_R", Const, 0}, {"PF_W", Const, 0}, {"PF_X", Const, 0}, {"PT_AARCH64_ARCHEXT", Const, 16}, {"PT_AARCH64_UNWIND", Const, 16}, {"PT_ARM_ARCHEXT", Const, 16}, {"PT_ARM_EXIDX", Const, 16}, {"PT_DYNAMIC", Const, 0}, {"PT_GNU_EH_FRAME", Const, 16}, {"PT_GNU_MBIND_HI", Const, 16}, {"PT_GNU_MBIND_LO", Const, 16}, {"PT_GNU_PROPERTY", Const, 16}, {"PT_GNU_RELRO", Const, 16}, {"PT_GNU_STACK", Const, 16}, {"PT_HIOS", Const, 0}, {"PT_HIPROC", Const, 0}, {"PT_INTERP", Const, 0}, {"PT_LOAD", Const, 0}, {"PT_LOOS", Const, 0}, {"PT_LOPROC", Const, 0}, {"PT_MIPS_ABIFLAGS", Const, 16}, {"PT_MIPS_OPTIONS", Const, 16}, {"PT_MIPS_REGINFO", Const, 16}, {"PT_MIPS_RTPROC", Const, 16}, {"PT_NOTE", Const, 0}, {"PT_NULL", Const, 0}, {"PT_OPENBSD_BOOTDATA", Const, 16}, {"PT_OPENBSD_NOBTCFI", Const, 23}, {"PT_OPENBSD_RANDOMIZE", Const, 16}, {"PT_OPENBSD_WXNEEDED", Const, 16}, {"PT_PAX_FLAGS", Const, 16}, {"PT_PHDR", Const, 0}, {"PT_RISCV_ATTRIBUTES", Const, 25}, {"PT_S390_PGSTE", Const, 16}, {"PT_SHLIB", Const, 0}, {"PT_SUNWSTACK", Const, 16}, {"PT_SUNW_EH_FRAME", Const, 16}, {"PT_TLS", Const, 0}, {"Prog", Type, 0}, {"Prog.ProgHeader", Field, 0}, {"Prog.ReaderAt", Field, 0}, {"Prog32", Type, 0}, {"Prog32.Align", Field, 0}, {"Prog32.Filesz", Field, 0}, {"Prog32.Flags", Field, 0}, {"Prog32.Memsz", Field, 0}, {"Prog32.Off", Field, 0}, {"Prog32.Paddr", Field, 0}, {"Prog32.Type", Field, 0}, {"Prog32.Vaddr", Field, 0}, {"Prog64", Type, 0}, {"Prog64.Align", Field, 0}, {"Prog64.Filesz", Field, 0}, {"Prog64.Flags", Field, 0}, {"Prog64.Memsz", Field, 0}, {"Prog64.Off", Field, 0}, {"Prog64.Paddr", Field, 0}, {"Prog64.Type", Field, 0}, {"Prog64.Vaddr", Field, 0}, {"ProgFlag", Type, 0}, {"ProgHeader", Type, 0}, {"ProgHeader.Align", Field, 0}, {"ProgHeader.Filesz", Field, 0}, {"ProgHeader.Flags", Field, 0}, {"ProgHeader.Memsz", Field, 0}, {"ProgHeader.Off", Field, 0}, {"ProgHeader.Paddr", Field, 0}, {"ProgHeader.Type", Field, 0}, {"ProgHeader.Vaddr", Field, 0}, {"ProgType", Type, 0}, {"R_386", Type, 0}, {"R_386_16", Const, 10}, {"R_386_32", Const, 0}, {"R_386_32PLT", Const, 10}, {"R_386_8", Const, 10}, {"R_386_COPY", Const, 0}, {"R_386_GLOB_DAT", Const, 0}, {"R_386_GOT32", Const, 0}, {"R_386_GOT32X", Const, 10}, {"R_386_GOTOFF", Const, 0}, {"R_386_GOTPC", Const, 0}, {"R_386_IRELATIVE", Const, 10}, {"R_386_JMP_SLOT", Const, 0}, {"R_386_NONE", Const, 0}, {"R_386_PC16", Const, 10}, {"R_386_PC32", Const, 0}, {"R_386_PC8", Const, 10}, {"R_386_PLT32", Const, 0}, {"R_386_RELATIVE", Const, 0}, {"R_386_SIZE32", Const, 10}, {"R_386_TLS_DESC", Const, 10}, {"R_386_TLS_DESC_CALL", Const, 10}, {"R_386_TLS_DTPMOD32", Const, 0}, {"R_386_TLS_DTPOFF32", Const, 0}, {"R_386_TLS_GD", Const, 0}, {"R_386_TLS_GD_32", Const, 0}, {"R_386_TLS_GD_CALL", Const, 0}, {"R_386_TLS_GD_POP", Const, 0}, {"R_386_TLS_GD_PUSH", Const, 0}, {"R_386_TLS_GOTDESC", Const, 10}, {"R_386_TLS_GOTIE", Const, 0}, {"R_386_TLS_IE", Const, 0}, {"R_386_TLS_IE_32", Const, 0}, {"R_386_TLS_LDM", Const, 0}, {"R_386_TLS_LDM_32", Const, 0}, {"R_386_TLS_LDM_CALL", Const, 0}, {"R_386_TLS_LDM_POP", Const, 0}, {"R_386_TLS_LDM_PUSH", Const, 0}, {"R_386_TLS_LDO_32", Const, 0}, {"R_386_TLS_LE", Const, 0}, {"R_386_TLS_LE_32", Const, 0}, {"R_386_TLS_TPOFF", Const, 0}, {"R_386_TLS_TPOFF32", Const, 0}, {"R_390", Type, 7}, {"R_390_12", Const, 7}, {"R_390_16", Const, 7}, {"R_390_20", Const, 7}, {"R_390_32", Const, 7}, {"R_390_64", Const, 7}, {"R_390_8", Const, 7}, {"R_390_COPY", Const, 7}, {"R_390_GLOB_DAT", Const, 7}, {"R_390_GOT12", Const, 7}, {"R_390_GOT16", Const, 7}, {"R_390_GOT20", Const, 7}, {"R_390_GOT32", Const, 7}, {"R_390_GOT64", Const, 7}, {"R_390_GOTENT", Const, 7}, {"R_390_GOTOFF", Const, 7}, {"R_390_GOTOFF16", Const, 7}, {"R_390_GOTOFF64", Const, 7}, {"R_390_GOTPC", Const, 7}, {"R_390_GOTPCDBL", Const, 7}, {"R_390_GOTPLT12", Const, 7}, {"R_390_GOTPLT16", Const, 7}, {"R_390_GOTPLT20", Const, 7}, {"R_390_GOTPLT32", Const, 7}, {"R_390_GOTPLT64", Const, 7}, {"R_390_GOTPLTENT", Const, 7}, {"R_390_GOTPLTOFF16", Const, 7}, {"R_390_GOTPLTOFF32", Const, 7}, {"R_390_GOTPLTOFF64", Const, 7}, {"R_390_JMP_SLOT", Const, 7}, {"R_390_NONE", Const, 7}, {"R_390_PC16", Const, 7}, {"R_390_PC16DBL", Const, 7}, {"R_390_PC32", Const, 7}, {"R_390_PC32DBL", Const, 7}, {"R_390_PC64", Const, 7}, {"R_390_PLT16DBL", Const, 7}, {"R_390_PLT32", Const, 7}, {"R_390_PLT32DBL", Const, 7}, {"R_390_PLT64", Const, 7}, {"R_390_RELATIVE", Const, 7}, {"R_390_TLS_DTPMOD", Const, 7}, {"R_390_TLS_DTPOFF", Const, 7}, {"R_390_TLS_GD32", Const, 7}, {"R_390_TLS_GD64", Const, 7}, {"R_390_TLS_GDCALL", Const, 7}, {"R_390_TLS_GOTIE12", Const, 7}, {"R_390_TLS_GOTIE20", Const, 7}, {"R_390_TLS_GOTIE32", Const, 7}, {"R_390_TLS_GOTIE64", Const, 7}, {"R_390_TLS_IE32", Const, 7}, {"R_390_TLS_IE64", Const, 7}, {"R_390_TLS_IEENT", Const, 7}, {"R_390_TLS_LDCALL", Const, 7}, {"R_390_TLS_LDM32", Const, 7}, {"R_390_TLS_LDM64", Const, 7}, {"R_390_TLS_LDO32", Const, 7}, {"R_390_TLS_LDO64", Const, 7}, {"R_390_TLS_LE32", Const, 7}, {"R_390_TLS_LE64", Const, 7}, {"R_390_TLS_LOAD", Const, 7}, {"R_390_TLS_TPOFF", Const, 7}, {"R_AARCH64", Type, 4}, {"R_AARCH64_ABS16", Const, 4}, {"R_AARCH64_ABS32", Const, 4}, {"R_AARCH64_ABS64", Const, 4}, {"R_AARCH64_ADD_ABS_LO12_NC", Const, 4}, {"R_AARCH64_ADR_GOT_PAGE", Const, 4}, {"R_AARCH64_ADR_PREL_LO21", Const, 4}, {"R_AARCH64_ADR_PREL_PG_HI21", Const, 4}, {"R_AARCH64_ADR_PREL_PG_HI21_NC", Const, 4}, {"R_AARCH64_CALL26", Const, 4}, {"R_AARCH64_CONDBR19", Const, 4}, {"R_AARCH64_COPY", Const, 4}, {"R_AARCH64_GLOB_DAT", Const, 4}, {"R_AARCH64_GOT_LD_PREL19", Const, 4}, {"R_AARCH64_IRELATIVE", Const, 4}, {"R_AARCH64_JUMP26", Const, 4}, {"R_AARCH64_JUMP_SLOT", Const, 4}, {"R_AARCH64_LD64_GOTOFF_LO15", Const, 10}, {"R_AARCH64_LD64_GOTPAGE_LO15", Const, 10}, {"R_AARCH64_LD64_GOT_LO12_NC", Const, 4}, {"R_AARCH64_LDST128_ABS_LO12_NC", Const, 4}, {"R_AARCH64_LDST16_ABS_LO12_NC", Const, 4}, {"R_AARCH64_LDST32_ABS_LO12_NC", Const, 4}, {"R_AARCH64_LDST64_ABS_LO12_NC", Const, 4}, {"R_AARCH64_LDST8_ABS_LO12_NC", Const, 4}, {"R_AARCH64_LD_PREL_LO19", Const, 4}, {"R_AARCH64_MOVW_SABS_G0", Const, 4}, {"R_AARCH64_MOVW_SABS_G1", Const, 4}, {"R_AARCH64_MOVW_SABS_G2", Const, 4}, {"R_AARCH64_MOVW_UABS_G0", Const, 4}, {"R_AARCH64_MOVW_UABS_G0_NC", Const, 4}, {"R_AARCH64_MOVW_UABS_G1", Const, 4}, {"R_AARCH64_MOVW_UABS_G1_NC", Const, 4}, {"R_AARCH64_MOVW_UABS_G2", Const, 4}, {"R_AARCH64_MOVW_UABS_G2_NC", Const, 4}, {"R_AARCH64_MOVW_UABS_G3", Const, 4}, {"R_AARCH64_NONE", Const, 4}, {"R_AARCH64_NULL", Const, 4}, {"R_AARCH64_P32_ABS16", Const, 4}, {"R_AARCH64_P32_ABS32", Const, 4}, {"R_AARCH64_P32_ADD_ABS_LO12_NC", Const, 4}, {"R_AARCH64_P32_ADR_GOT_PAGE", Const, 4}, {"R_AARCH64_P32_ADR_PREL_LO21", Const, 4}, {"R_AARCH64_P32_ADR_PREL_PG_HI21", Const, 4}, {"R_AARCH64_P32_CALL26", Const, 4}, {"R_AARCH64_P32_CONDBR19", Const, 4}, {"R_AARCH64_P32_COPY", Const, 4}, {"R_AARCH64_P32_GLOB_DAT", Const, 4}, {"R_AARCH64_P32_GOT_LD_PREL19", Const, 4}, {"R_AARCH64_P32_IRELATIVE", Const, 4}, {"R_AARCH64_P32_JUMP26", Const, 4}, {"R_AARCH64_P32_JUMP_SLOT", Const, 4}, {"R_AARCH64_P32_LD32_GOT_LO12_NC", Const, 4}, {"R_AARCH64_P32_LDST128_ABS_LO12_NC", Const, 4}, {"R_AARCH64_P32_LDST16_ABS_LO12_NC", Const, 4}, {"R_AARCH64_P32_LDST32_ABS_LO12_NC", Const, 4}, {"R_AARCH64_P32_LDST64_ABS_LO12_NC", Const, 4}, {"R_AARCH64_P32_LDST8_ABS_LO12_NC", Const, 4}, {"R_AARCH64_P32_LD_PREL_LO19", Const, 4}, {"R_AARCH64_P32_MOVW_SABS_G0", Const, 4}, {"R_AARCH64_P32_MOVW_UABS_G0", Const, 4}, {"R_AARCH64_P32_MOVW_UABS_G0_NC", Const, 4}, {"R_AARCH64_P32_MOVW_UABS_G1", Const, 4}, {"R_AARCH64_P32_PREL16", Const, 4}, {"R_AARCH64_P32_PREL32", Const, 4}, {"R_AARCH64_P32_RELATIVE", Const, 4}, {"R_AARCH64_P32_TLSDESC", Const, 4}, {"R_AARCH64_P32_TLSDESC_ADD_LO12_NC", Const, 4}, {"R_AARCH64_P32_TLSDESC_ADR_PAGE21", Const, 4}, {"R_AARCH64_P32_TLSDESC_ADR_PREL21", Const, 4}, {"R_AARCH64_P32_TLSDESC_CALL", Const, 4}, {"R_AARCH64_P32_TLSDESC_LD32_LO12_NC", Const, 4}, {"R_AARCH64_P32_TLSDESC_LD_PREL19", Const, 4}, {"R_AARCH64_P32_TLSGD_ADD_LO12_NC", Const, 4}, {"R_AARCH64_P32_TLSGD_ADR_PAGE21", Const, 4}, {"R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21", Const, 4}, {"R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC", Const, 4}, {"R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19", Const, 4}, {"R_AARCH64_P32_TLSLE_ADD_TPREL_HI12", Const, 4}, {"R_AARCH64_P32_TLSLE_ADD_TPREL_LO12", Const, 4}, {"R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC", Const, 4}, {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G0", Const, 4}, {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC", Const, 4}, {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G1", Const, 4}, {"R_AARCH64_P32_TLS_DTPMOD", Const, 4}, {"R_AARCH64_P32_TLS_DTPREL", Const, 4}, {"R_AARCH64_P32_TLS_TPREL", Const, 4}, {"R_AARCH64_P32_TSTBR14", Const, 4}, {"R_AARCH64_PREL16", Const, 4}, {"R_AARCH64_PREL32", Const, 4}, {"R_AARCH64_PREL64", Const, 4}, {"R_AARCH64_RELATIVE", Const, 4}, {"R_AARCH64_TLSDESC", Const, 4}, {"R_AARCH64_TLSDESC_ADD", Const, 4}, {"R_AARCH64_TLSDESC_ADD_LO12_NC", Const, 4}, {"R_AARCH64_TLSDESC_ADR_PAGE21", Const, 4}, {"R_AARCH64_TLSDESC_ADR_PREL21", Const, 4}, {"R_AARCH64_TLSDESC_CALL", Const, 4}, {"R_AARCH64_TLSDESC_LD64_LO12_NC", Const, 4}, {"R_AARCH64_TLSDESC_LDR", Const, 4}, {"R_AARCH64_TLSDESC_LD_PREL19", Const, 4}, {"R_AARCH64_TLSDESC_OFF_G0_NC", Const, 4}, {"R_AARCH64_TLSDESC_OFF_G1", Const, 4}, {"R_AARCH64_TLSGD_ADD_LO12_NC", Const, 4}, {"R_AARCH64_TLSGD_ADR_PAGE21", Const, 4}, {"R_AARCH64_TLSGD_ADR_PREL21", Const, 10}, {"R_AARCH64_TLSGD_MOVW_G0_NC", Const, 10}, {"R_AARCH64_TLSGD_MOVW_G1", Const, 10}, {"R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21", Const, 4}, {"R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC", Const, 4}, {"R_AARCH64_TLSIE_LD_GOTTPREL_PREL19", Const, 4}, {"R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC", Const, 4}, {"R_AARCH64_TLSIE_MOVW_GOTTPREL_G1", Const, 4}, {"R_AARCH64_TLSLD_ADR_PAGE21", Const, 10}, {"R_AARCH64_TLSLD_ADR_PREL21", Const, 10}, {"R_AARCH64_TLSLD_LDST128_DTPREL_LO12", Const, 10}, {"R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC", Const, 10}, {"R_AARCH64_TLSLE_ADD_TPREL_HI12", Const, 4}, {"R_AARCH64_TLSLE_ADD_TPREL_LO12", Const, 4}, {"R_AARCH64_TLSLE_ADD_TPREL_LO12_NC", Const, 4}, {"R_AARCH64_TLSLE_LDST128_TPREL_LO12", Const, 10}, {"R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC", Const, 10}, {"R_AARCH64_TLSLE_MOVW_TPREL_G0", Const, 4}, {"R_AARCH64_TLSLE_MOVW_TPREL_G0_NC", Const, 4}, {"R_AARCH64_TLSLE_MOVW_TPREL_G1", Const, 4}, {"R_AARCH64_TLSLE_MOVW_TPREL_G1_NC", Const, 4}, {"R_AARCH64_TLSLE_MOVW_TPREL_G2", Const, 4}, {"R_AARCH64_TLS_DTPMOD64", Const, 4}, {"R_AARCH64_TLS_DTPREL64", Const, 4}, {"R_AARCH64_TLS_TPREL64", Const, 4}, {"R_AARCH64_TSTBR14", Const, 4}, {"R_ALPHA", Type, 0}, {"R_ALPHA_BRADDR", Const, 0}, {"R_ALPHA_COPY", Const, 0}, {"R_ALPHA_GLOB_DAT", Const, 0}, {"R_ALPHA_GPDISP", Const, 0}, {"R_ALPHA_GPREL32", Const, 0}, {"R_ALPHA_GPRELHIGH", Const, 0}, {"R_ALPHA_GPRELLOW", Const, 0}, {"R_ALPHA_GPVALUE", Const, 0}, {"R_ALPHA_HINT", Const, 0}, {"R_ALPHA_IMMED_BR_HI32", Const, 0}, {"R_ALPHA_IMMED_GP_16", Const, 0}, {"R_ALPHA_IMMED_GP_HI32", Const, 0}, {"R_ALPHA_IMMED_LO32", Const, 0}, {"R_ALPHA_IMMED_SCN_HI32", Const, 0}, {"R_ALPHA_JMP_SLOT", Const, 0}, {"R_ALPHA_LITERAL", Const, 0}, {"R_ALPHA_LITUSE", Const, 0}, {"R_ALPHA_NONE", Const, 0}, {"R_ALPHA_OP_PRSHIFT", Const, 0}, {"R_ALPHA_OP_PSUB", Const, 0}, {"R_ALPHA_OP_PUSH", Const, 0}, {"R_ALPHA_OP_STORE", Const, 0}, {"R_ALPHA_REFLONG", Const, 0}, {"R_ALPHA_REFQUAD", Const, 0}, {"R_ALPHA_RELATIVE", Const, 0}, {"R_ALPHA_SREL16", Const, 0}, {"R_ALPHA_SREL32", Const, 0}, {"R_ALPHA_SREL64", Const, 0}, {"R_ARM", Type, 0}, {"R_ARM_ABS12", Const, 0}, {"R_ARM_ABS16", Const, 0}, {"R_ARM_ABS32", Const, 0}, {"R_ARM_ABS32_NOI", Const, 10}, {"R_ARM_ABS8", Const, 0}, {"R_ARM_ALU_PCREL_15_8", Const, 10}, {"R_ARM_ALU_PCREL_23_15", Const, 10}, {"R_ARM_ALU_PCREL_7_0", Const, 10}, {"R_ARM_ALU_PC_G0", Const, 10}, {"R_ARM_ALU_PC_G0_NC", Const, 10}, {"R_ARM_ALU_PC_G1", Const, 10}, {"R_ARM_ALU_PC_G1_NC", Const, 10}, {"R_ARM_ALU_PC_G2", Const, 10}, {"R_ARM_ALU_SBREL_19_12_NC", Const, 10}, {"R_ARM_ALU_SBREL_27_20_CK", Const, 10}, {"R_ARM_ALU_SB_G0", Const, 10}, {"R_ARM_ALU_SB_G0_NC", Const, 10}, {"R_ARM_ALU_SB_G1", Const, 10}, {"R_ARM_ALU_SB_G1_NC", Const, 10}, {"R_ARM_ALU_SB_G2", Const, 10}, {"R_ARM_AMP_VCALL9", Const, 0}, {"R_ARM_BASE_ABS", Const, 10}, {"R_ARM_CALL", Const, 10}, {"R_ARM_COPY", Const, 0}, {"R_ARM_GLOB_DAT", Const, 0}, {"R_ARM_GNU_VTENTRY", Const, 0}, {"R_ARM_GNU_VTINHERIT", Const, 0}, {"R_ARM_GOT32", Const, 0}, {"R_ARM_GOTOFF", Const, 0}, {"R_ARM_GOTOFF12", Const, 10}, {"R_ARM_GOTPC", Const, 0}, {"R_ARM_GOTRELAX", Const, 10}, {"R_ARM_GOT_ABS", Const, 10}, {"R_ARM_GOT_BREL12", Const, 10}, {"R_ARM_GOT_PREL", Const, 10}, {"R_ARM_IRELATIVE", Const, 10}, {"R_ARM_JUMP24", Const, 10}, {"R_ARM_JUMP_SLOT", Const, 0}, {"R_ARM_LDC_PC_G0", Const, 10}, {"R_ARM_LDC_PC_G1", Const, 10}, {"R_ARM_LDC_PC_G2", Const, 10}, {"R_ARM_LDC_SB_G0", Const, 10}, {"R_ARM_LDC_SB_G1", Const, 10}, {"R_ARM_LDC_SB_G2", Const, 10}, {"R_ARM_LDRS_PC_G0", Const, 10}, {"R_ARM_LDRS_PC_G1", Const, 10}, {"R_ARM_LDRS_PC_G2", Const, 10}, {"R_ARM_LDRS_SB_G0", Const, 10}, {"R_ARM_LDRS_SB_G1", Const, 10}, {"R_ARM_LDRS_SB_G2", Const, 10}, {"R_ARM_LDR_PC_G1", Const, 10}, {"R_ARM_LDR_PC_G2", Const, 10}, {"R_ARM_LDR_SBREL_11_10_NC", Const, 10}, {"R_ARM_LDR_SB_G0", Const, 10}, {"R_ARM_LDR_SB_G1", Const, 10}, {"R_ARM_LDR_SB_G2", Const, 10}, {"R_ARM_ME_TOO", Const, 10}, {"R_ARM_MOVT_ABS", Const, 10}, {"R_ARM_MOVT_BREL", Const, 10}, {"R_ARM_MOVT_PREL", Const, 10}, {"R_ARM_MOVW_ABS_NC", Const, 10}, {"R_ARM_MOVW_BREL", Const, 10}, {"R_ARM_MOVW_BREL_NC", Const, 10}, {"R_ARM_MOVW_PREL_NC", Const, 10}, {"R_ARM_NONE", Const, 0}, {"R_ARM_PC13", Const, 0}, {"R_ARM_PC24", Const, 0}, {"R_ARM_PLT32", Const, 0}, {"R_ARM_PLT32_ABS", Const, 10}, {"R_ARM_PREL31", Const, 10}, {"R_ARM_PRIVATE_0", Const, 10}, {"R_ARM_PRIVATE_1", Const, 10}, {"R_ARM_PRIVATE_10", Const, 10}, {"R_ARM_PRIVATE_11", Const, 10}, {"R_ARM_PRIVATE_12", Const, 10}, {"R_ARM_PRIVATE_13", Const, 10}, {"R_ARM_PRIVATE_14", Const, 10}, {"R_ARM_PRIVATE_15", Const, 10}, {"R_ARM_PRIVATE_2", Const, 10}, {"R_ARM_PRIVATE_3", Const, 10}, {"R_ARM_PRIVATE_4", Const, 10}, {"R_ARM_PRIVATE_5", Const, 10}, {"R_ARM_PRIVATE_6", Const, 10}, {"R_ARM_PRIVATE_7", Const, 10}, {"R_ARM_PRIVATE_8", Const, 10}, {"R_ARM_PRIVATE_9", Const, 10}, {"R_ARM_RABS32", Const, 0}, {"R_ARM_RBASE", Const, 0}, {"R_ARM_REL32", Const, 0}, {"R_ARM_REL32_NOI", Const, 10}, {"R_ARM_RELATIVE", Const, 0}, {"R_ARM_RPC24", Const, 0}, {"R_ARM_RREL32", Const, 0}, {"R_ARM_RSBREL32", Const, 0}, {"R_ARM_RXPC25", Const, 10}, {"R_ARM_SBREL31", Const, 10}, {"R_ARM_SBREL32", Const, 0}, {"R_ARM_SWI24", Const, 0}, {"R_ARM_TARGET1", Const, 10}, {"R_ARM_TARGET2", Const, 10}, {"R_ARM_THM_ABS5", Const, 0}, {"R_ARM_THM_ALU_ABS_G0_NC", Const, 10}, {"R_ARM_THM_ALU_ABS_G1_NC", Const, 10}, {"R_ARM_THM_ALU_ABS_G2_NC", Const, 10}, {"R_ARM_THM_ALU_ABS_G3", Const, 10}, {"R_ARM_THM_ALU_PREL_11_0", Const, 10}, {"R_ARM_THM_GOT_BREL12", Const, 10}, {"R_ARM_THM_JUMP11", Const, 10}, {"R_ARM_THM_JUMP19", Const, 10}, {"R_ARM_THM_JUMP24", Const, 10}, {"R_ARM_THM_JUMP6", Const, 10}, {"R_ARM_THM_JUMP8", Const, 10}, {"R_ARM_THM_MOVT_ABS", Const, 10}, {"R_ARM_THM_MOVT_BREL", Const, 10}, {"R_ARM_THM_MOVT_PREL", Const, 10}, {"R_ARM_THM_MOVW_ABS_NC", Const, 10}, {"R_ARM_THM_MOVW_BREL", Const, 10}, {"R_ARM_THM_MOVW_BREL_NC", Const, 10}, {"R_ARM_THM_MOVW_PREL_NC", Const, 10}, {"R_ARM_THM_PC12", Const, 10}, {"R_ARM_THM_PC22", Const, 0}, {"R_ARM_THM_PC8", Const, 0}, {"R_ARM_THM_RPC22", Const, 0}, {"R_ARM_THM_SWI8", Const, 0}, {"R_ARM_THM_TLS_CALL", Const, 10}, {"R_ARM_THM_TLS_DESCSEQ16", Const, 10}, {"R_ARM_THM_TLS_DESCSEQ32", Const, 10}, {"R_ARM_THM_XPC22", Const, 0}, {"R_ARM_TLS_CALL", Const, 10}, {"R_ARM_TLS_DESCSEQ", Const, 10}, {"R_ARM_TLS_DTPMOD32", Const, 10}, {"R_ARM_TLS_DTPOFF32", Const, 10}, {"R_ARM_TLS_GD32", Const, 10}, {"R_ARM_TLS_GOTDESC", Const, 10}, {"R_ARM_TLS_IE12GP", Const, 10}, {"R_ARM_TLS_IE32", Const, 10}, {"R_ARM_TLS_LDM32", Const, 10}, {"R_ARM_TLS_LDO12", Const, 10}, {"R_ARM_TLS_LDO32", Const, 10}, {"R_ARM_TLS_LE12", Const, 10}, {"R_ARM_TLS_LE32", Const, 10}, {"R_ARM_TLS_TPOFF32", Const, 10}, {"R_ARM_V4BX", Const, 10}, {"R_ARM_XPC25", Const, 0}, {"R_INFO", Func, 0}, {"R_INFO32", Func, 0}, {"R_LARCH", Type, 19}, {"R_LARCH_32", Const, 19}, {"R_LARCH_32_PCREL", Const, 20}, {"R_LARCH_64", Const, 19}, {"R_LARCH_64_PCREL", Const, 22}, {"R_LARCH_ABS64_HI12", Const, 20}, {"R_LARCH_ABS64_LO20", Const, 20}, {"R_LARCH_ABS_HI20", Const, 20}, {"R_LARCH_ABS_LO12", Const, 20}, {"R_LARCH_ADD16", Const, 19}, {"R_LARCH_ADD24", Const, 19}, {"R_LARCH_ADD32", Const, 19}, {"R_LARCH_ADD6", Const, 22}, {"R_LARCH_ADD64", Const, 19}, {"R_LARCH_ADD8", Const, 19}, {"R_LARCH_ADD_ULEB128", Const, 22}, {"R_LARCH_ALIGN", Const, 22}, {"R_LARCH_B16", Const, 20}, {"R_LARCH_B21", Const, 20}, {"R_LARCH_B26", Const, 20}, {"R_LARCH_CFA", Const, 22}, {"R_LARCH_COPY", Const, 19}, {"R_LARCH_DELETE", Const, 22}, {"R_LARCH_GNU_VTENTRY", Const, 20}, {"R_LARCH_GNU_VTINHERIT", Const, 20}, {"R_LARCH_GOT64_HI12", Const, 20}, {"R_LARCH_GOT64_LO20", Const, 20}, {"R_LARCH_GOT64_PC_HI12", Const, 20}, {"R_LARCH_GOT64_PC_LO20", Const, 20}, {"R_LARCH_GOT_HI20", Const, 20}, {"R_LARCH_GOT_LO12", Const, 20}, {"R_LARCH_GOT_PC_HI20", Const, 20}, {"R_LARCH_GOT_PC_LO12", Const, 20}, {"R_LARCH_IRELATIVE", Const, 19}, {"R_LARCH_JUMP_SLOT", Const, 19}, {"R_LARCH_MARK_LA", Const, 19}, {"R_LARCH_MARK_PCREL", Const, 19}, {"R_LARCH_NONE", Const, 19}, {"R_LARCH_PCALA64_HI12", Const, 20}, {"R_LARCH_PCALA64_LO20", Const, 20}, {"R_LARCH_PCALA_HI20", Const, 20}, {"R_LARCH_PCALA_LO12", Const, 20}, {"R_LARCH_PCREL20_S2", Const, 22}, {"R_LARCH_RELATIVE", Const, 19}, {"R_LARCH_RELAX", Const, 20}, {"R_LARCH_SOP_ADD", Const, 19}, {"R_LARCH_SOP_AND", Const, 19}, {"R_LARCH_SOP_ASSERT", Const, 19}, {"R_LARCH_SOP_IF_ELSE", Const, 19}, {"R_LARCH_SOP_NOT", Const, 19}, {"R_LARCH_SOP_POP_32_S_0_10_10_16_S2", Const, 19}, {"R_LARCH_SOP_POP_32_S_0_5_10_16_S2", Const, 19}, {"R_LARCH_SOP_POP_32_S_10_12", Const, 19}, {"R_LARCH_SOP_POP_32_S_10_16", Const, 19}, {"R_LARCH_SOP_POP_32_S_10_16_S2", Const, 19}, {"R_LARCH_SOP_POP_32_S_10_5", Const, 19}, {"R_LARCH_SOP_POP_32_S_5_20", Const, 19}, {"R_LARCH_SOP_POP_32_U", Const, 19}, {"R_LARCH_SOP_POP_32_U_10_12", Const, 19}, {"R_LARCH_SOP_PUSH_ABSOLUTE", Const, 19}, {"R_LARCH_SOP_PUSH_DUP", Const, 19}, {"R_LARCH_SOP_PUSH_GPREL", Const, 19}, {"R_LARCH_SOP_PUSH_PCREL", Const, 19}, {"R_LARCH_SOP_PUSH_PLT_PCREL", Const, 19}, {"R_LARCH_SOP_PUSH_TLS_GD", Const, 19}, {"R_LARCH_SOP_PUSH_TLS_GOT", Const, 19}, {"R_LARCH_SOP_PUSH_TLS_TPREL", Const, 19}, {"R_LARCH_SOP_SL", Const, 19}, {"R_LARCH_SOP_SR", Const, 19}, {"R_LARCH_SOP_SUB", Const, 19}, {"R_LARCH_SUB16", Const, 19}, {"R_LARCH_SUB24", Const, 19}, {"R_LARCH_SUB32", Const, 19}, {"R_LARCH_SUB6", Const, 22}, {"R_LARCH_SUB64", Const, 19}, {"R_LARCH_SUB8", Const, 19}, {"R_LARCH_SUB_ULEB128", Const, 22}, {"R_LARCH_TLS_DTPMOD32", Const, 19}, {"R_LARCH_TLS_DTPMOD64", Const, 19}, {"R_LARCH_TLS_DTPREL32", Const, 19}, {"R_LARCH_TLS_DTPREL64", Const, 19}, {"R_LARCH_TLS_GD_HI20", Const, 20}, {"R_LARCH_TLS_GD_PC_HI20", Const, 20}, {"R_LARCH_TLS_IE64_HI12", Const, 20}, {"R_LARCH_TLS_IE64_LO20", Const, 20}, {"R_LARCH_TLS_IE64_PC_HI12", Const, 20}, {"R_LARCH_TLS_IE64_PC_LO20", Const, 20}, {"R_LARCH_TLS_IE_HI20", Const, 20}, {"R_LARCH_TLS_IE_LO12", Const, 20}, {"R_LARCH_TLS_IE_PC_HI20", Const, 20}, {"R_LARCH_TLS_IE_PC_LO12", Const, 20}, {"R_LARCH_TLS_LD_HI20", Const, 20}, {"R_LARCH_TLS_LD_PC_HI20", Const, 20}, {"R_LARCH_TLS_LE64_HI12", Const, 20}, {"R_LARCH_TLS_LE64_LO20", Const, 20}, {"R_LARCH_TLS_LE_HI20", Const, 20}, {"R_LARCH_TLS_LE_LO12", Const, 20}, {"R_LARCH_TLS_TPREL32", Const, 19}, {"R_LARCH_TLS_TPREL64", Const, 19}, {"R_MIPS", Type, 6}, {"R_MIPS_16", Const, 6}, {"R_MIPS_26", Const, 6}, {"R_MIPS_32", Const, 6}, {"R_MIPS_64", Const, 6}, {"R_MIPS_ADD_IMMEDIATE", Const, 6}, {"R_MIPS_CALL16", Const, 6}, {"R_MIPS_CALL_HI16", Const, 6}, {"R_MIPS_CALL_LO16", Const, 6}, {"R_MIPS_DELETE", Const, 6}, {"R_MIPS_GOT16", Const, 6}, {"R_MIPS_GOT_DISP", Const, 6}, {"R_MIPS_GOT_HI16", Const, 6}, {"R_MIPS_GOT_LO16", Const, 6}, {"R_MIPS_GOT_OFST", Const, 6}, {"R_MIPS_GOT_PAGE", Const, 6}, {"R_MIPS_GPREL16", Const, 6}, {"R_MIPS_GPREL32", Const, 6}, {"R_MIPS_HI16", Const, 6}, {"R_MIPS_HIGHER", Const, 6}, {"R_MIPS_HIGHEST", Const, 6}, {"R_MIPS_INSERT_A", Const, 6}, {"R_MIPS_INSERT_B", Const, 6}, {"R_MIPS_JALR", Const, 6}, {"R_MIPS_LITERAL", Const, 6}, {"R_MIPS_LO16", Const, 6}, {"R_MIPS_NONE", Const, 6}, {"R_MIPS_PC16", Const, 6}, {"R_MIPS_PC32", Const, 22}, {"R_MIPS_PJUMP", Const, 6}, {"R_MIPS_REL16", Const, 6}, {"R_MIPS_REL32", Const, 6}, {"R_MIPS_RELGOT", Const, 6}, {"R_MIPS_SCN_DISP", Const, 6}, {"R_MIPS_SHIFT5", Const, 6}, {"R_MIPS_SHIFT6", Const, 6}, {"R_MIPS_SUB", Const, 6}, {"R_MIPS_TLS_DTPMOD32", Const, 6}, {"R_MIPS_TLS_DTPMOD64", Const, 6}, {"R_MIPS_TLS_DTPREL32", Const, 6}, {"R_MIPS_TLS_DTPREL64", Const, 6}, {"R_MIPS_TLS_DTPREL_HI16", Const, 6}, {"R_MIPS_TLS_DTPREL_LO16", Const, 6}, {"R_MIPS_TLS_GD", Const, 6}, {"R_MIPS_TLS_GOTTPREL", Const, 6}, {"R_MIPS_TLS_LDM", Const, 6}, {"R_MIPS_TLS_TPREL32", Const, 6}, {"R_MIPS_TLS_TPREL64", Const, 6}, {"R_MIPS_TLS_TPREL_HI16", Const, 6}, {"R_MIPS_TLS_TPREL_LO16", Const, 6}, {"R_PPC", Type, 0}, {"R_PPC64", Type, 5}, {"R_PPC64_ADDR14", Const, 5}, {"R_PPC64_ADDR14_BRNTAKEN", Const, 5}, {"R_PPC64_ADDR14_BRTAKEN", Const, 5}, {"R_PPC64_ADDR16", Const, 5}, {"R_PPC64_ADDR16_DS", Const, 5}, {"R_PPC64_ADDR16_HA", Const, 5}, {"R_PPC64_ADDR16_HI", Const, 5}, {"R_PPC64_ADDR16_HIGH", Const, 10}, {"R_PPC64_ADDR16_HIGHA", Const, 10}, {"R_PPC64_ADDR16_HIGHER", Const, 5}, {"R_PPC64_ADDR16_HIGHER34", Const, 20}, {"R_PPC64_ADDR16_HIGHERA", Const, 5}, {"R_PPC64_ADDR16_HIGHERA34", Const, 20}, {"R_PPC64_ADDR16_HIGHEST", Const, 5}, {"R_PPC64_ADDR16_HIGHEST34", Const, 20}, {"R_PPC64_ADDR16_HIGHESTA", Const, 5}, {"R_PPC64_ADDR16_HIGHESTA34", Const, 20}, {"R_PPC64_ADDR16_LO", Const, 5}, {"R_PPC64_ADDR16_LO_DS", Const, 5}, {"R_PPC64_ADDR24", Const, 5}, {"R_PPC64_ADDR32", Const, 5}, {"R_PPC64_ADDR64", Const, 5}, {"R_PPC64_ADDR64_LOCAL", Const, 10}, {"R_PPC64_COPY", Const, 20}, {"R_PPC64_D28", Const, 20}, {"R_PPC64_D34", Const, 20}, {"R_PPC64_D34_HA30", Const, 20}, {"R_PPC64_D34_HI30", Const, 20}, {"R_PPC64_D34_LO", Const, 20}, {"R_PPC64_DTPMOD64", Const, 5}, {"R_PPC64_DTPREL16", Const, 5}, {"R_PPC64_DTPREL16_DS", Const, 5}, {"R_PPC64_DTPREL16_HA", Const, 5}, {"R_PPC64_DTPREL16_HI", Const, 5}, {"R_PPC64_DTPREL16_HIGH", Const, 10}, {"R_PPC64_DTPREL16_HIGHA", Const, 10}, {"R_PPC64_DTPREL16_HIGHER", Const, 5}, {"R_PPC64_DTPREL16_HIGHERA", Const, 5}, {"R_PPC64_DTPREL16_HIGHEST", Const, 5}, {"R_PPC64_DTPREL16_HIGHESTA", Const, 5}, {"R_PPC64_DTPREL16_LO", Const, 5}, {"R_PPC64_DTPREL16_LO_DS", Const, 5}, {"R_PPC64_DTPREL34", Const, 20}, {"R_PPC64_DTPREL64", Const, 5}, {"R_PPC64_ENTRY", Const, 10}, {"R_PPC64_GLOB_DAT", Const, 20}, {"R_PPC64_GNU_VTENTRY", Const, 20}, {"R_PPC64_GNU_VTINHERIT", Const, 20}, {"R_PPC64_GOT16", Const, 5}, {"R_PPC64_GOT16_DS", Const, 5}, {"R_PPC64_GOT16_HA", Const, 5}, {"R_PPC64_GOT16_HI", Const, 5}, {"R_PPC64_GOT16_LO", Const, 5}, {"R_PPC64_GOT16_LO_DS", Const, 5}, {"R_PPC64_GOT_DTPREL16_DS", Const, 5}, {"R_PPC64_GOT_DTPREL16_HA", Const, 5}, {"R_PPC64_GOT_DTPREL16_HI", Const, 5}, {"R_PPC64_GOT_DTPREL16_LO_DS", Const, 5}, {"R_PPC64_GOT_DTPREL_PCREL34", Const, 20}, {"R_PPC64_GOT_PCREL34", Const, 20}, {"R_PPC64_GOT_TLSGD16", Const, 5}, {"R_PPC64_GOT_TLSGD16_HA", Const, 5}, {"R_PPC64_GOT_TLSGD16_HI", Const, 5}, {"R_PPC64_GOT_TLSGD16_LO", Const, 5}, {"R_PPC64_GOT_TLSGD_PCREL34", Const, 20}, {"R_PPC64_GOT_TLSLD16", Const, 5}, {"R_PPC64_GOT_TLSLD16_HA", Const, 5}, {"R_PPC64_GOT_TLSLD16_HI", Const, 5}, {"R_PPC64_GOT_TLSLD16_LO", Const, 5}, {"R_PPC64_GOT_TLSLD_PCREL34", Const, 20}, {"R_PPC64_GOT_TPREL16_DS", Const, 5}, {"R_PPC64_GOT_TPREL16_HA", Const, 5}, {"R_PPC64_GOT_TPREL16_HI", Const, 5}, {"R_PPC64_GOT_TPREL16_LO_DS", Const, 5}, {"R_PPC64_GOT_TPREL_PCREL34", Const, 20}, {"R_PPC64_IRELATIVE", Const, 10}, {"R_PPC64_JMP_IREL", Const, 10}, {"R_PPC64_JMP_SLOT", Const, 5}, {"R_PPC64_NONE", Const, 5}, {"R_PPC64_PCREL28", Const, 20}, {"R_PPC64_PCREL34", Const, 20}, {"R_PPC64_PCREL_OPT", Const, 20}, {"R_PPC64_PLT16_HA", Const, 20}, {"R_PPC64_PLT16_HI", Const, 20}, {"R_PPC64_PLT16_LO", Const, 20}, {"R_PPC64_PLT16_LO_DS", Const, 10}, {"R_PPC64_PLT32", Const, 20}, {"R_PPC64_PLT64", Const, 20}, {"R_PPC64_PLTCALL", Const, 20}, {"R_PPC64_PLTCALL_NOTOC", Const, 20}, {"R_PPC64_PLTGOT16", Const, 10}, {"R_PPC64_PLTGOT16_DS", Const, 10}, {"R_PPC64_PLTGOT16_HA", Const, 10}, {"R_PPC64_PLTGOT16_HI", Const, 10}, {"R_PPC64_PLTGOT16_LO", Const, 10}, {"R_PPC64_PLTGOT_LO_DS", Const, 10}, {"R_PPC64_PLTREL32", Const, 20}, {"R_PPC64_PLTREL64", Const, 20}, {"R_PPC64_PLTSEQ", Const, 20}, {"R_PPC64_PLTSEQ_NOTOC", Const, 20}, {"R_PPC64_PLT_PCREL34", Const, 20}, {"R_PPC64_PLT_PCREL34_NOTOC", Const, 20}, {"R_PPC64_REL14", Const, 5}, {"R_PPC64_REL14_BRNTAKEN", Const, 5}, {"R_PPC64_REL14_BRTAKEN", Const, 5}, {"R_PPC64_REL16", Const, 5}, {"R_PPC64_REL16DX_HA", Const, 10}, {"R_PPC64_REL16_HA", Const, 5}, {"R_PPC64_REL16_HI", Const, 5}, {"R_PPC64_REL16_HIGH", Const, 20}, {"R_PPC64_REL16_HIGHA", Const, 20}, {"R_PPC64_REL16_HIGHER", Const, 20}, {"R_PPC64_REL16_HIGHER34", Const, 20}, {"R_PPC64_REL16_HIGHERA", Const, 20}, {"R_PPC64_REL16_HIGHERA34", Const, 20}, {"R_PPC64_REL16_HIGHEST", Const, 20}, {"R_PPC64_REL16_HIGHEST34", Const, 20}, {"R_PPC64_REL16_HIGHESTA", Const, 20}, {"R_PPC64_REL16_HIGHESTA34", Const, 20}, {"R_PPC64_REL16_LO", Const, 5}, {"R_PPC64_REL24", Const, 5}, {"R_PPC64_REL24_NOTOC", Const, 10}, {"R_PPC64_REL24_P9NOTOC", Const, 21}, {"R_PPC64_REL30", Const, 20}, {"R_PPC64_REL32", Const, 5}, {"R_PPC64_REL64", Const, 5}, {"R_PPC64_RELATIVE", Const, 18}, {"R_PPC64_SECTOFF", Const, 20}, {"R_PPC64_SECTOFF_DS", Const, 10}, {"R_PPC64_SECTOFF_HA", Const, 20}, {"R_PPC64_SECTOFF_HI", Const, 20}, {"R_PPC64_SECTOFF_LO", Const, 20}, {"R_PPC64_SECTOFF_LO_DS", Const, 10}, {"R_PPC64_TLS", Const, 5}, {"R_PPC64_TLSGD", Const, 5}, {"R_PPC64_TLSLD", Const, 5}, {"R_PPC64_TOC", Const, 5}, {"R_PPC64_TOC16", Const, 5}, {"R_PPC64_TOC16_DS", Const, 5}, {"R_PPC64_TOC16_HA", Const, 5}, {"R_PPC64_TOC16_HI", Const, 5}, {"R_PPC64_TOC16_LO", Const, 5}, {"R_PPC64_TOC16_LO_DS", Const, 5}, {"R_PPC64_TOCSAVE", Const, 10}, {"R_PPC64_TPREL16", Const, 5}, {"R_PPC64_TPREL16_DS", Const, 5}, {"R_PPC64_TPREL16_HA", Const, 5}, {"R_PPC64_TPREL16_HI", Const, 5}, {"R_PPC64_TPREL16_HIGH", Const, 10}, {"R_PPC64_TPREL16_HIGHA", Const, 10}, {"R_PPC64_TPREL16_HIGHER", Const, 5}, {"R_PPC64_TPREL16_HIGHERA", Const, 5}, {"R_PPC64_TPREL16_HIGHEST", Const, 5}, {"R_PPC64_TPREL16_HIGHESTA", Const, 5}, {"R_PPC64_TPREL16_LO", Const, 5}, {"R_PPC64_TPREL16_LO_DS", Const, 5}, {"R_PPC64_TPREL34", Const, 20}, {"R_PPC64_TPREL64", Const, 5}, {"R_PPC64_UADDR16", Const, 20}, {"R_PPC64_UADDR32", Const, 20}, {"R_PPC64_UADDR64", Const, 20}, {"R_PPC_ADDR14", Const, 0}, {"R_PPC_ADDR14_BRNTAKEN", Const, 0}, {"R_PPC_ADDR14_BRTAKEN", Const, 0}, {"R_PPC_ADDR16", Const, 0}, {"R_PPC_ADDR16_HA", Const, 0}, {"R_PPC_ADDR16_HI", Const, 0}, {"R_PPC_ADDR16_LO", Const, 0}, {"R_PPC_ADDR24", Const, 0}, {"R_PPC_ADDR32", Const, 0}, {"R_PPC_COPY", Const, 0}, {"R_PPC_DTPMOD32", Const, 0}, {"R_PPC_DTPREL16", Const, 0}, {"R_PPC_DTPREL16_HA", Const, 0}, {"R_PPC_DTPREL16_HI", Const, 0}, {"R_PPC_DTPREL16_LO", Const, 0}, {"R_PPC_DTPREL32", Const, 0}, {"R_PPC_EMB_BIT_FLD", Const, 0}, {"R_PPC_EMB_MRKREF", Const, 0}, {"R_PPC_EMB_NADDR16", Const, 0}, {"R_PPC_EMB_NADDR16_HA", Const, 0}, {"R_PPC_EMB_NADDR16_HI", Const, 0}, {"R_PPC_EMB_NADDR16_LO", Const, 0}, {"R_PPC_EMB_NADDR32", Const, 0}, {"R_PPC_EMB_RELSDA", Const, 0}, {"R_PPC_EMB_RELSEC16", Const, 0}, {"R_PPC_EMB_RELST_HA", Const, 0}, {"R_PPC_EMB_RELST_HI", Const, 0}, {"R_PPC_EMB_RELST_LO", Const, 0}, {"R_PPC_EMB_SDA21", Const, 0}, {"R_PPC_EMB_SDA2I16", Const, 0}, {"R_PPC_EMB_SDA2REL", Const, 0}, {"R_PPC_EMB_SDAI16", Const, 0}, {"R_PPC_GLOB_DAT", Const, 0}, {"R_PPC_GOT16", Const, 0}, {"R_PPC_GOT16_HA", Const, 0}, {"R_PPC_GOT16_HI", Const, 0}, {"R_PPC_GOT16_LO", Const, 0}, {"R_PPC_GOT_TLSGD16", Const, 0}, {"R_PPC_GOT_TLSGD16_HA", Const, 0}, {"R_PPC_GOT_TLSGD16_HI", Const, 0}, {"R_PPC_GOT_TLSGD16_LO", Const, 0}, {"R_PPC_GOT_TLSLD16", Const, 0}, {"R_PPC_GOT_TLSLD16_HA", Const, 0}, {"R_PPC_GOT_TLSLD16_HI", Const, 0}, {"R_PPC_GOT_TLSLD16_LO", Const, 0}, {"R_PPC_GOT_TPREL16", Const, 0}, {"R_PPC_GOT_TPREL16_HA", Const, 0}, {"R_PPC_GOT_TPREL16_HI", Const, 0}, {"R_PPC_GOT_TPREL16_LO", Const, 0}, {"R_PPC_JMP_SLOT", Const, 0}, {"R_PPC_LOCAL24PC", Const, 0}, {"R_PPC_NONE", Const, 0}, {"R_PPC_PLT16_HA", Const, 0}, {"R_PPC_PLT16_HI", Const, 0}, {"R_PPC_PLT16_LO", Const, 0}, {"R_PPC_PLT32", Const, 0}, {"R_PPC_PLTREL24", Const, 0}, {"R_PPC_PLTREL32", Const, 0}, {"R_PPC_REL14", Const, 0}, {"R_PPC_REL14_BRNTAKEN", Const, 0}, {"R_PPC_REL14_BRTAKEN", Const, 0}, {"R_PPC_REL24", Const, 0}, {"R_PPC_REL32", Const, 0}, {"R_PPC_RELATIVE", Const, 0}, {"R_PPC_SDAREL16", Const, 0}, {"R_PPC_SECTOFF", Const, 0}, {"R_PPC_SECTOFF_HA", Const, 0}, {"R_PPC_SECTOFF_HI", Const, 0}, {"R_PPC_SECTOFF_LO", Const, 0}, {"R_PPC_TLS", Const, 0}, {"R_PPC_TPREL16", Const, 0}, {"R_PPC_TPREL16_HA", Const, 0}, {"R_PPC_TPREL16_HI", Const, 0}, {"R_PPC_TPREL16_LO", Const, 0}, {"R_PPC_TPREL32", Const, 0}, {"R_PPC_UADDR16", Const, 0}, {"R_PPC_UADDR32", Const, 0}, {"R_RISCV", Type, 11}, {"R_RISCV_32", Const, 11}, {"R_RISCV_32_PCREL", Const, 12}, {"R_RISCV_64", Const, 11}, {"R_RISCV_ADD16", Const, 11}, {"R_RISCV_ADD32", Const, 11}, {"R_RISCV_ADD64", Const, 11}, {"R_RISCV_ADD8", Const, 11}, {"R_RISCV_ALIGN", Const, 11}, {"R_RISCV_BRANCH", Const, 11}, {"R_RISCV_CALL", Const, 11}, {"R_RISCV_CALL_PLT", Const, 11}, {"R_RISCV_COPY", Const, 11}, {"R_RISCV_GNU_VTENTRY", Const, 11}, {"R_RISCV_GNU_VTINHERIT", Const, 11}, {"R_RISCV_GOT_HI20", Const, 11}, {"R_RISCV_GPREL_I", Const, 11}, {"R_RISCV_GPREL_S", Const, 11}, {"R_RISCV_HI20", Const, 11}, {"R_RISCV_JAL", Const, 11}, {"R_RISCV_JUMP_SLOT", Const, 11}, {"R_RISCV_LO12_I", Const, 11}, {"R_RISCV_LO12_S", Const, 11}, {"R_RISCV_NONE", Const, 11}, {"R_RISCV_PCREL_HI20", Const, 11}, {"R_RISCV_PCREL_LO12_I", Const, 11}, {"R_RISCV_PCREL_LO12_S", Const, 11}, {"R_RISCV_RELATIVE", Const, 11}, {"R_RISCV_RELAX", Const, 11}, {"R_RISCV_RVC_BRANCH", Const, 11}, {"R_RISCV_RVC_JUMP", Const, 11}, {"R_RISCV_RVC_LUI", Const, 11}, {"R_RISCV_SET16", Const, 11}, {"R_RISCV_SET32", Const, 11}, {"R_RISCV_SET6", Const, 11}, {"R_RISCV_SET8", Const, 11}, {"R_RISCV_SUB16", Const, 11}, {"R_RISCV_SUB32", Const, 11}, {"R_RISCV_SUB6", Const, 11}, {"R_RISCV_SUB64", Const, 11}, {"R_RISCV_SUB8", Const, 11}, {"R_RISCV_TLS_DTPMOD32", Const, 11}, {"R_RISCV_TLS_DTPMOD64", Const, 11}, {"R_RISCV_TLS_DTPREL32", Const, 11}, {"R_RISCV_TLS_DTPREL64", Const, 11}, {"R_RISCV_TLS_GD_HI20", Const, 11}, {"R_RISCV_TLS_GOT_HI20", Const, 11}, {"R_RISCV_TLS_TPREL32", Const, 11}, {"R_RISCV_TLS_TPREL64", Const, 11}, {"R_RISCV_TPREL_ADD", Const, 11}, {"R_RISCV_TPREL_HI20", Const, 11}, {"R_RISCV_TPREL_I", Const, 11}, {"R_RISCV_TPREL_LO12_I", Const, 11}, {"R_RISCV_TPREL_LO12_S", Const, 11}, {"R_RISCV_TPREL_S", Const, 11}, {"R_SPARC", Type, 0}, {"R_SPARC_10", Const, 0}, {"R_SPARC_11", Const, 0}, {"R_SPARC_13", Const, 0}, {"R_SPARC_16", Const, 0}, {"R_SPARC_22", Const, 0}, {"R_SPARC_32", Const, 0}, {"R_SPARC_5", Const, 0}, {"R_SPARC_6", Const, 0}, {"R_SPARC_64", Const, 0}, {"R_SPARC_7", Const, 0}, {"R_SPARC_8", Const, 0}, {"R_SPARC_COPY", Const, 0}, {"R_SPARC_DISP16", Const, 0}, {"R_SPARC_DISP32", Const, 0}, {"R_SPARC_DISP64", Const, 0}, {"R_SPARC_DISP8", Const, 0}, {"R_SPARC_GLOB_DAT", Const, 0}, {"R_SPARC_GLOB_JMP", Const, 0}, {"R_SPARC_GOT10", Const, 0}, {"R_SPARC_GOT13", Const, 0}, {"R_SPARC_GOT22", Const, 0}, {"R_SPARC_H44", Const, 0}, {"R_SPARC_HH22", Const, 0}, {"R_SPARC_HI22", Const, 0}, {"R_SPARC_HIPLT22", Const, 0}, {"R_SPARC_HIX22", Const, 0}, {"R_SPARC_HM10", Const, 0}, {"R_SPARC_JMP_SLOT", Const, 0}, {"R_SPARC_L44", Const, 0}, {"R_SPARC_LM22", Const, 0}, {"R_SPARC_LO10", Const, 0}, {"R_SPARC_LOPLT10", Const, 0}, {"R_SPARC_LOX10", Const, 0}, {"R_SPARC_M44", Const, 0}, {"R_SPARC_NONE", Const, 0}, {"R_SPARC_OLO10", Const, 0}, {"R_SPARC_PC10", Const, 0}, {"R_SPARC_PC22", Const, 0}, {"R_SPARC_PCPLT10", Const, 0}, {"R_SPARC_PCPLT22", Const, 0}, {"R_SPARC_PCPLT32", Const, 0}, {"R_SPARC_PC_HH22", Const, 0}, {"R_SPARC_PC_HM10", Const, 0}, {"R_SPARC_PC_LM22", Const, 0}, {"R_SPARC_PLT32", Const, 0}, {"R_SPARC_PLT64", Const, 0}, {"R_SPARC_REGISTER", Const, 0}, {"R_SPARC_RELATIVE", Const, 0}, {"R_SPARC_UA16", Const, 0}, {"R_SPARC_UA32", Const, 0}, {"R_SPARC_UA64", Const, 0}, {"R_SPARC_WDISP16", Const, 0}, {"R_SPARC_WDISP19", Const, 0}, {"R_SPARC_WDISP22", Const, 0}, {"R_SPARC_WDISP30", Const, 0}, {"R_SPARC_WPLT30", Const, 0}, {"R_SYM32", Func, 0}, {"R_SYM64", Func, 0}, {"R_TYPE32", Func, 0}, {"R_TYPE64", Func, 0}, {"R_X86_64", Type, 0}, {"R_X86_64_16", Const, 0}, {"R_X86_64_32", Const, 0}, {"R_X86_64_32S", Const, 0}, {"R_X86_64_64", Const, 0}, {"R_X86_64_8", Const, 0}, {"R_X86_64_COPY", Const, 0}, {"R_X86_64_DTPMOD64", Const, 0}, {"R_X86_64_DTPOFF32", Const, 0}, {"R_X86_64_DTPOFF64", Const, 0}, {"R_X86_64_GLOB_DAT", Const, 0}, {"R_X86_64_GOT32", Const, 0}, {"R_X86_64_GOT64", Const, 10}, {"R_X86_64_GOTOFF64", Const, 10}, {"R_X86_64_GOTPC32", Const, 10}, {"R_X86_64_GOTPC32_TLSDESC", Const, 10}, {"R_X86_64_GOTPC64", Const, 10}, {"R_X86_64_GOTPCREL", Const, 0}, {"R_X86_64_GOTPCREL64", Const, 10}, {"R_X86_64_GOTPCRELX", Const, 10}, {"R_X86_64_GOTPLT64", Const, 10}, {"R_X86_64_GOTTPOFF", Const, 0}, {"R_X86_64_IRELATIVE", Const, 10}, {"R_X86_64_JMP_SLOT", Const, 0}, {"R_X86_64_NONE", Const, 0}, {"R_X86_64_PC16", Const, 0}, {"R_X86_64_PC32", Const, 0}, {"R_X86_64_PC32_BND", Const, 10}, {"R_X86_64_PC64", Const, 10}, {"R_X86_64_PC8", Const, 0}, {"R_X86_64_PLT32", Const, 0}, {"R_X86_64_PLT32_BND", Const, 10}, {"R_X86_64_PLTOFF64", Const, 10}, {"R_X86_64_RELATIVE", Const, 0}, {"R_X86_64_RELATIVE64", Const, 10}, {"R_X86_64_REX_GOTPCRELX", Const, 10}, {"R_X86_64_SIZE32", Const, 10}, {"R_X86_64_SIZE64", Const, 10}, {"R_X86_64_TLSDESC", Const, 10}, {"R_X86_64_TLSDESC_CALL", Const, 10}, {"R_X86_64_TLSGD", Const, 0}, {"R_X86_64_TLSLD", Const, 0}, {"R_X86_64_TPOFF32", Const, 0}, {"R_X86_64_TPOFF64", Const, 0}, {"Rel32", Type, 0}, {"Rel32.Info", Field, 0}, {"Rel32.Off", Field, 0}, {"Rel64", Type, 0}, {"Rel64.Info", Field, 0}, {"Rel64.Off", Field, 0}, {"Rela32", Type, 0}, {"Rela32.Addend", Field, 0}, {"Rela32.Info", Field, 0}, {"Rela32.Off", Field, 0}, {"Rela64", Type, 0}, {"Rela64.Addend", Field, 0}, {"Rela64.Info", Field, 0}, {"Rela64.Off", Field, 0}, {"SHF_ALLOC", Const, 0}, {"SHF_COMPRESSED", Const, 6}, {"SHF_EXECINSTR", Const, 0}, {"SHF_GROUP", Const, 0}, {"SHF_INFO_LINK", Const, 0}, {"SHF_LINK_ORDER", Const, 0}, {"SHF_MASKOS", Const, 0}, {"SHF_MASKPROC", Const, 0}, {"SHF_MERGE", Const, 0}, {"SHF_OS_NONCONFORMING", Const, 0}, {"SHF_STRINGS", Const, 0}, {"SHF_TLS", Const, 0}, {"SHF_WRITE", Const, 0}, {"SHN_ABS", Const, 0}, {"SHN_COMMON", Const, 0}, {"SHN_HIOS", Const, 0}, {"SHN_HIPROC", Const, 0}, {"SHN_HIRESERVE", Const, 0}, {"SHN_LOOS", Const, 0}, {"SHN_LOPROC", Const, 0}, {"SHN_LORESERVE", Const, 0}, {"SHN_UNDEF", Const, 0}, {"SHN_XINDEX", Const, 0}, {"SHT_DYNAMIC", Const, 0}, {"SHT_DYNSYM", Const, 0}, {"SHT_FINI_ARRAY", Const, 0}, {"SHT_GNU_ATTRIBUTES", Const, 0}, {"SHT_GNU_HASH", Const, 0}, {"SHT_GNU_LIBLIST", Const, 0}, {"SHT_GNU_VERDEF", Const, 0}, {"SHT_GNU_VERNEED", Const, 0}, {"SHT_GNU_VERSYM", Const, 0}, {"SHT_GROUP", Const, 0}, {"SHT_HASH", Const, 0}, {"SHT_HIOS", Const, 0}, {"SHT_HIPROC", Const, 0}, {"SHT_HIUSER", Const, 0}, {"SHT_INIT_ARRAY", Const, 0}, {"SHT_LOOS", Const, 0}, {"SHT_LOPROC", Const, 0}, {"SHT_LOUSER", Const, 0}, {"SHT_MIPS_ABIFLAGS", Const, 17}, {"SHT_NOBITS", Const, 0}, {"SHT_NOTE", Const, 0}, {"SHT_NULL", Const, 0}, {"SHT_PREINIT_ARRAY", Const, 0}, {"SHT_PROGBITS", Const, 0}, {"SHT_REL", Const, 0}, {"SHT_RELA", Const, 0}, {"SHT_RISCV_ATTRIBUTES", Const, 25}, {"SHT_SHLIB", Const, 0}, {"SHT_STRTAB", Const, 0}, {"SHT_SYMTAB", Const, 0}, {"SHT_SYMTAB_SHNDX", Const, 0}, {"STB_GLOBAL", Const, 0}, {"STB_HIOS", Const, 0}, {"STB_HIPROC", Const, 0}, {"STB_LOCAL", Const, 0}, {"STB_LOOS", Const, 0}, {"STB_LOPROC", Const, 0}, {"STB_WEAK", Const, 0}, {"STT_COMMON", Const, 0}, {"STT_FILE", Const, 0}, {"STT_FUNC", Const, 0}, {"STT_GNU_IFUNC", Const, 23}, {"STT_HIOS", Const, 0}, {"STT_HIPROC", Const, 0}, {"STT_LOOS", Const, 0}, {"STT_LOPROC", Const, 0}, {"STT_NOTYPE", Const, 0}, {"STT_OBJECT", Const, 0}, {"STT_RELC", Const, 23}, {"STT_SECTION", Const, 0}, {"STT_SRELC", Const, 23}, {"STT_TLS", Const, 0}, {"STV_DEFAULT", Const, 0}, {"STV_HIDDEN", Const, 0}, {"STV_INTERNAL", Const, 0}, {"STV_PROTECTED", Const, 0}, {"ST_BIND", Func, 0}, {"ST_INFO", Func, 0}, {"ST_TYPE", Func, 0}, {"ST_VISIBILITY", Func, 0}, {"Section", Type, 0}, {"Section.ReaderAt", Field, 0}, {"Section.SectionHeader", Field, 0}, {"Section32", Type, 0}, {"Section32.Addr", Field, 0}, {"Section32.Addralign", Field, 0}, {"Section32.Entsize", Field, 0}, {"Section32.Flags", Field, 0}, {"Section32.Info", Field, 0}, {"Section32.Link", Field, 0}, {"Section32.Name", Field, 0}, {"Section32.Off", Field, 0}, {"Section32.Size", Field, 0}, {"Section32.Type", Field, 0}, {"Section64", Type, 0}, {"Section64.Addr", Field, 0}, {"Section64.Addralign", Field, 0}, {"Section64.Entsize", Field, 0}, {"Section64.Flags", Field, 0}, {"Section64.Info", Field, 0}, {"Section64.Link", Field, 0}, {"Section64.Name", Field, 0}, {"Section64.Off", Field, 0}, {"Section64.Size", Field, 0}, {"Section64.Type", Field, 0}, {"SectionFlag", Type, 0}, {"SectionHeader", Type, 0}, {"SectionHeader.Addr", Field, 0}, {"SectionHeader.Addralign", Field, 0}, {"SectionHeader.Entsize", Field, 0}, {"SectionHeader.FileSize", Field, 6}, {"SectionHeader.Flags", Field, 0}, {"SectionHeader.Info", Field, 0}, {"SectionHeader.Link", Field, 0}, {"SectionHeader.Name", Field, 0}, {"SectionHeader.Offset", Field, 0}, {"SectionHeader.Size", Field, 0}, {"SectionHeader.Type", Field, 0}, {"SectionIndex", Type, 0}, {"SectionType", Type, 0}, {"Sym32", Type, 0}, {"Sym32.Info", Field, 0}, {"Sym32.Name", Field, 0}, {"Sym32.Other", Field, 0}, {"Sym32.Shndx", Field, 0}, {"Sym32.Size", Field, 0}, {"Sym32.Value", Field, 0}, {"Sym32Size", Const, 0}, {"Sym64", Type, 0}, {"Sym64.Info", Field, 0}, {"Sym64.Name", Field, 0}, {"Sym64.Other", Field, 0}, {"Sym64.Shndx", Field, 0}, {"Sym64.Size", Field, 0}, {"Sym64.Value", Field, 0}, {"Sym64Size", Const, 0}, {"SymBind", Type, 0}, {"SymType", Type, 0}, {"SymVis", Type, 0}, {"Symbol", Type, 0}, {"Symbol.HasVersion", Field, 24}, {"Symbol.Info", Field, 0}, {"Symbol.Library", Field, 13}, {"Symbol.Name", Field, 0}, {"Symbol.Other", Field, 0}, {"Symbol.Section", Field, 0}, {"Symbol.Size", Field, 0}, {"Symbol.Value", Field, 0}, {"Symbol.Version", Field, 13}, {"Symbol.VersionIndex", Field, 24}, {"Type", Type, 0}, {"VER_FLG_BASE", Const, 24}, {"VER_FLG_INFO", Const, 24}, {"VER_FLG_WEAK", Const, 24}, {"Version", Type, 0}, {"VersionIndex", Type, 24}, }, "debug/gosym": { {"(*DecodingError).Error", Method, 0}, {"(*LineTable).LineToPC", Method, 0}, {"(*LineTable).PCToLine", Method, 0}, {"(*Sym).BaseName", Method, 0}, {"(*Sym).PackageName", Method, 0}, {"(*Sym).ReceiverName", Method, 0}, {"(*Sym).Static", Method, 0}, {"(*Table).LineToPC", Method, 0}, {"(*Table).LookupFunc", Method, 0}, {"(*Table).LookupSym", Method, 0}, {"(*Table).PCToFunc", Method, 0}, {"(*Table).PCToLine", Method, 0}, {"(*Table).SymByAddr", Method, 0}, {"(*UnknownLineError).Error", Method, 0}, {"(Func).BaseName", Method, 0}, {"(Func).PackageName", Method, 0}, {"(Func).ReceiverName", Method, 0}, {"(Func).Static", Method, 0}, {"(UnknownFileError).Error", Method, 0}, {"DecodingError", Type, 0}, {"Func", Type, 0}, {"Func.End", Field, 0}, {"Func.Entry", Field, 0}, {"Func.FrameSize", Field, 0}, {"Func.LineTable", Field, 0}, {"Func.Locals", Field, 0}, {"Func.Obj", Field, 0}, {"Func.Params", Field, 0}, {"Func.Sym", Field, 0}, {"LineTable", Type, 0}, {"LineTable.Data", Field, 0}, {"LineTable.Line", Field, 0}, {"LineTable.PC", Field, 0}, {"NewLineTable", Func, 0}, {"NewTable", Func, 0}, {"Obj", Type, 0}, {"Obj.Funcs", Field, 0}, {"Obj.Paths", Field, 0}, {"Sym", Type, 0}, {"Sym.Func", Field, 0}, {"Sym.GoType", Field, 0}, {"Sym.Name", Field, 0}, {"Sym.Type", Field, 0}, {"Sym.Value", Field, 0}, {"Table", Type, 0}, {"Table.Files", Field, 0}, {"Table.Funcs", Field, 0}, {"Table.Objs", Field, 0}, {"Table.Syms", Field, 0}, {"UnknownFileError", Type, 0}, {"UnknownLineError", Type, 0}, {"UnknownLineError.File", Field, 0}, {"UnknownLineError.Line", Field, 0}, }, "debug/macho": { {"(*FatFile).Close", Method, 3}, {"(*File).Close", Method, 0}, {"(*File).DWARF", Method, 0}, {"(*File).ImportedLibraries", Method, 0}, {"(*File).ImportedSymbols", Method, 0}, {"(*File).Section", Method, 0}, {"(*File).Segment", Method, 0}, {"(*FormatError).Error", Method, 0}, {"(*Section).Data", Method, 0}, {"(*Section).Open", Method, 0}, {"(*Segment).Data", Method, 0}, {"(*Segment).Open", Method, 0}, {"(Cpu).GoString", Method, 0}, {"(Cpu).String", Method, 0}, {"(Dylib).Raw", Method, 0}, {"(Dysymtab).Raw", Method, 0}, {"(FatArch).Close", Method, 3}, {"(FatArch).DWARF", Method, 3}, {"(FatArch).ImportedLibraries", Method, 3}, {"(FatArch).ImportedSymbols", Method, 3}, {"(FatArch).Section", Method, 3}, {"(FatArch).Segment", Method, 3}, {"(LoadBytes).Raw", Method, 0}, {"(LoadCmd).GoString", Method, 0}, {"(LoadCmd).String", Method, 0}, {"(RelocTypeARM).GoString", Method, 10}, {"(RelocTypeARM).String", Method, 10}, {"(RelocTypeARM64).GoString", Method, 10}, {"(RelocTypeARM64).String", Method, 10}, {"(RelocTypeGeneric).GoString", Method, 10}, {"(RelocTypeGeneric).String", Method, 10}, {"(RelocTypeX86_64).GoString", Method, 10}, {"(RelocTypeX86_64).String", Method, 10}, {"(Rpath).Raw", Method, 10}, {"(Section).ReadAt", Method, 0}, {"(Segment).Raw", Method, 0}, {"(Segment).ReadAt", Method, 0}, {"(Symtab).Raw", Method, 0}, {"(Type).GoString", Method, 10}, {"(Type).String", Method, 10}, {"ARM64_RELOC_ADDEND", Const, 10}, {"ARM64_RELOC_BRANCH26", Const, 10}, {"ARM64_RELOC_GOT_LOAD_PAGE21", Const, 10}, {"ARM64_RELOC_GOT_LOAD_PAGEOFF12", Const, 10}, {"ARM64_RELOC_PAGE21", Const, 10}, {"ARM64_RELOC_PAGEOFF12", Const, 10}, {"ARM64_RELOC_POINTER_TO_GOT", Const, 10}, {"ARM64_RELOC_SUBTRACTOR", Const, 10}, {"ARM64_RELOC_TLVP_LOAD_PAGE21", Const, 10}, {"ARM64_RELOC_TLVP_LOAD_PAGEOFF12", Const, 10}, {"ARM64_RELOC_UNSIGNED", Const, 10}, {"ARM_RELOC_BR24", Const, 10}, {"ARM_RELOC_HALF", Const, 10}, {"ARM_RELOC_HALF_SECTDIFF", Const, 10}, {"ARM_RELOC_LOCAL_SECTDIFF", Const, 10}, {"ARM_RELOC_PAIR", Const, 10}, {"ARM_RELOC_PB_LA_PTR", Const, 10}, {"ARM_RELOC_SECTDIFF", Const, 10}, {"ARM_RELOC_VANILLA", Const, 10}, {"ARM_THUMB_32BIT_BRANCH", Const, 10}, {"ARM_THUMB_RELOC_BR22", Const, 10}, {"Cpu", Type, 0}, {"Cpu386", Const, 0}, {"CpuAmd64", Const, 0}, {"CpuArm", Const, 3}, {"CpuArm64", Const, 11}, {"CpuPpc", Const, 3}, {"CpuPpc64", Const, 3}, {"Dylib", Type, 0}, {"Dylib.CompatVersion", Field, 0}, {"Dylib.CurrentVersion", Field, 0}, {"Dylib.LoadBytes", Field, 0}, {"Dylib.Name", Field, 0}, {"Dylib.Time", Field, 0}, {"DylibCmd", Type, 0}, {"DylibCmd.Cmd", Field, 0}, {"DylibCmd.CompatVersion", Field, 0}, {"DylibCmd.CurrentVersion", Field, 0}, {"DylibCmd.Len", Field, 0}, {"DylibCmd.Name", Field, 0}, {"DylibCmd.Time", Field, 0}, {"Dysymtab", Type, 0}, {"Dysymtab.DysymtabCmd", Field, 0}, {"Dysymtab.IndirectSyms", Field, 0}, {"Dysymtab.LoadBytes", Field, 0}, {"DysymtabCmd", Type, 0}, {"DysymtabCmd.Cmd", Field, 0}, {"DysymtabCmd.Extrefsymoff", Field, 0}, {"DysymtabCmd.Extreloff", Field, 0}, {"DysymtabCmd.Iextdefsym", Field, 0}, {"DysymtabCmd.Ilocalsym", Field, 0}, {"DysymtabCmd.Indirectsymoff", Field, 0}, {"DysymtabCmd.Iundefsym", Field, 0}, {"DysymtabCmd.Len", Field, 0}, {"DysymtabCmd.Locreloff", Field, 0}, {"DysymtabCmd.Modtaboff", Field, 0}, {"DysymtabCmd.Nextdefsym", Field, 0}, {"DysymtabCmd.Nextrefsyms", Field, 0}, {"DysymtabCmd.Nextrel", Field, 0}, {"DysymtabCmd.Nindirectsyms", Field, 0}, {"DysymtabCmd.Nlocalsym", Field, 0}, {"DysymtabCmd.Nlocrel", Field, 0}, {"DysymtabCmd.Nmodtab", Field, 0}, {"DysymtabCmd.Ntoc", Field, 0}, {"DysymtabCmd.Nundefsym", Field, 0}, {"DysymtabCmd.Tocoffset", Field, 0}, {"ErrNotFat", Var, 3}, {"FatArch", Type, 3}, {"FatArch.FatArchHeader", Field, 3}, {"FatArch.File", Field, 3}, {"FatArchHeader", Type, 3}, {"FatArchHeader.Align", Field, 3}, {"FatArchHeader.Cpu", Field, 3}, {"FatArchHeader.Offset", Field, 3}, {"FatArchHeader.Size", Field, 3}, {"FatArchHeader.SubCpu", Field, 3}, {"FatFile", Type, 3}, {"FatFile.Arches", Field, 3}, {"FatFile.Magic", Field, 3}, {"File", Type, 0}, {"File.ByteOrder", Field, 0}, {"File.Dysymtab", Field, 0}, {"File.FileHeader", Field, 0}, {"File.Loads", Field, 0}, {"File.Sections", Field, 0}, {"File.Symtab", Field, 0}, {"FileHeader", Type, 0}, {"FileHeader.Cmdsz", Field, 0}, {"FileHeader.Cpu", Field, 0}, {"FileHeader.Flags", Field, 0}, {"FileHeader.Magic", Field, 0}, {"FileHeader.Ncmd", Field, 0}, {"FileHeader.SubCpu", Field, 0}, {"FileHeader.Type", Field, 0}, {"FlagAllModsBound", Const, 10}, {"FlagAllowStackExecution", Const, 10}, {"FlagAppExtensionSafe", Const, 10}, {"FlagBindAtLoad", Const, 10}, {"FlagBindsToWeak", Const, 10}, {"FlagCanonical", Const, 10}, {"FlagDeadStrippableDylib", Const, 10}, {"FlagDyldLink", Const, 10}, {"FlagForceFlat", Const, 10}, {"FlagHasTLVDescriptors", Const, 10}, {"FlagIncrLink", Const, 10}, {"FlagLazyInit", Const, 10}, {"FlagNoFixPrebinding", Const, 10}, {"FlagNoHeapExecution", Const, 10}, {"FlagNoMultiDefs", Const, 10}, {"FlagNoReexportedDylibs", Const, 10}, {"FlagNoUndefs", Const, 10}, {"FlagPIE", Const, 10}, {"FlagPrebindable", Const, 10}, {"FlagPrebound", Const, 10}, {"FlagRootSafe", Const, 10}, {"FlagSetuidSafe", Const, 10}, {"FlagSplitSegs", Const, 10}, {"FlagSubsectionsViaSymbols", Const, 10}, {"FlagTwoLevel", Const, 10}, {"FlagWeakDefines", Const, 10}, {"FormatError", Type, 0}, {"GENERIC_RELOC_LOCAL_SECTDIFF", Const, 10}, {"GENERIC_RELOC_PAIR", Const, 10}, {"GENERIC_RELOC_PB_LA_PTR", Const, 10}, {"GENERIC_RELOC_SECTDIFF", Const, 10}, {"GENERIC_RELOC_TLV", Const, 10}, {"GENERIC_RELOC_VANILLA", Const, 10}, {"Load", Type, 0}, {"LoadBytes", Type, 0}, {"LoadCmd", Type, 0}, {"LoadCmdDylib", Const, 0}, {"LoadCmdDylinker", Const, 0}, {"LoadCmdDysymtab", Const, 0}, {"LoadCmdRpath", Const, 10}, {"LoadCmdSegment", Const, 0}, {"LoadCmdSegment64", Const, 0}, {"LoadCmdSymtab", Const, 0}, {"LoadCmdThread", Const, 0}, {"LoadCmdUnixThread", Const, 0}, {"Magic32", Const, 0}, {"Magic64", Const, 0}, {"MagicFat", Const, 3}, {"NewFatFile", Func, 3}, {"NewFile", Func, 0}, {"Nlist32", Type, 0}, {"Nlist32.Desc", Field, 0}, {"Nlist32.Name", Field, 0}, {"Nlist32.Sect", Field, 0}, {"Nlist32.Type", Field, 0}, {"Nlist32.Value", Field, 0}, {"Nlist64", Type, 0}, {"Nlist64.Desc", Field, 0}, {"Nlist64.Name", Field, 0}, {"Nlist64.Sect", Field, 0}, {"Nlist64.Type", Field, 0}, {"Nlist64.Value", Field, 0}, {"Open", Func, 0}, {"OpenFat", Func, 3}, {"Regs386", Type, 0}, {"Regs386.AX", Field, 0}, {"Regs386.BP", Field, 0}, {"Regs386.BX", Field, 0}, {"Regs386.CS", Field, 0}, {"Regs386.CX", Field, 0}, {"Regs386.DI", Field, 0}, {"Regs386.DS", Field, 0}, {"Regs386.DX", Field, 0}, {"Regs386.ES", Field, 0}, {"Regs386.FLAGS", Field, 0}, {"Regs386.FS", Field, 0}, {"Regs386.GS", Field, 0}, {"Regs386.IP", Field, 0}, {"Regs386.SI", Field, 0}, {"Regs386.SP", Field, 0}, {"Regs386.SS", Field, 0}, {"RegsAMD64", Type, 0}, {"RegsAMD64.AX", Field, 0}, {"RegsAMD64.BP", Field, 0}, {"RegsAMD64.BX", Field, 0}, {"RegsAMD64.CS", Field, 0}, {"RegsAMD64.CX", Field, 0}, {"RegsAMD64.DI", Field, 0}, {"RegsAMD64.DX", Field, 0}, {"RegsAMD64.FLAGS", Field, 0}, {"RegsAMD64.FS", Field, 0}, {"RegsAMD64.GS", Field, 0}, {"RegsAMD64.IP", Field, 0}, {"RegsAMD64.R10", Field, 0}, {"RegsAMD64.R11", Field, 0}, {"RegsAMD64.R12", Field, 0}, {"RegsAMD64.R13", Field, 0}, {"RegsAMD64.R14", Field, 0}, {"RegsAMD64.R15", Field, 0}, {"RegsAMD64.R8", Field, 0}, {"RegsAMD64.R9", Field, 0}, {"RegsAMD64.SI", Field, 0}, {"RegsAMD64.SP", Field, 0}, {"Reloc", Type, 10}, {"Reloc.Addr", Field, 10}, {"Reloc.Extern", Field, 10}, {"Reloc.Len", Field, 10}, {"Reloc.Pcrel", Field, 10}, {"Reloc.Scattered", Field, 10}, {"Reloc.Type", Field, 10}, {"Reloc.Value", Field, 10}, {"RelocTypeARM", Type, 10}, {"RelocTypeARM64", Type, 10}, {"RelocTypeGeneric", Type, 10}, {"RelocTypeX86_64", Type, 10}, {"Rpath", Type, 10}, {"Rpath.LoadBytes", Field, 10}, {"Rpath.Path", Field, 10}, {"RpathCmd", Type, 10}, {"RpathCmd.Cmd", Field, 10}, {"RpathCmd.Len", Field, 10}, {"RpathCmd.Path", Field, 10}, {"Section", Type, 0}, {"Section.ReaderAt", Field, 0}, {"Section.Relocs", Field, 10}, {"Section.SectionHeader", Field, 0}, {"Section32", Type, 0}, {"Section32.Addr", Field, 0}, {"Section32.Align", Field, 0}, {"Section32.Flags", Field, 0}, {"Section32.Name", Field, 0}, {"Section32.Nreloc", Field, 0}, {"Section32.Offset", Field, 0}, {"Section32.Reloff", Field, 0}, {"Section32.Reserve1", Field, 0}, {"Section32.Reserve2", Field, 0}, {"Section32.Seg", Field, 0}, {"Section32.Size", Field, 0}, {"Section64", Type, 0}, {"Section64.Addr", Field, 0}, {"Section64.Align", Field, 0}, {"Section64.Flags", Field, 0}, {"Section64.Name", Field, 0}, {"Section64.Nreloc", Field, 0}, {"Section64.Offset", Field, 0}, {"Section64.Reloff", Field, 0}, {"Section64.Reserve1", Field, 0}, {"Section64.Reserve2", Field, 0}, {"Section64.Reserve3", Field, 0}, {"Section64.Seg", Field, 0}, {"Section64.Size", Field, 0}, {"SectionHeader", Type, 0}, {"SectionHeader.Addr", Field, 0}, {"SectionHeader.Align", Field, 0}, {"SectionHeader.Flags", Field, 0}, {"SectionHeader.Name", Field, 0}, {"SectionHeader.Nreloc", Field, 0}, {"SectionHeader.Offset", Field, 0}, {"SectionHeader.Reloff", Field, 0}, {"SectionHeader.Seg", Field, 0}, {"SectionHeader.Size", Field, 0}, {"Segment", Type, 0}, {"Segment.LoadBytes", Field, 0}, {"Segment.ReaderAt", Field, 0}, {"Segment.SegmentHeader", Field, 0}, {"Segment32", Type, 0}, {"Segment32.Addr", Field, 0}, {"Segment32.Cmd", Field, 0}, {"Segment32.Filesz", Field, 0}, {"Segment32.Flag", Field, 0}, {"Segment32.Len", Field, 0}, {"Segment32.Maxprot", Field, 0}, {"Segment32.Memsz", Field, 0}, {"Segment32.Name", Field, 0}, {"Segment32.Nsect", Field, 0}, {"Segment32.Offset", Field, 0}, {"Segment32.Prot", Field, 0}, {"Segment64", Type, 0}, {"Segment64.Addr", Field, 0}, {"Segment64.Cmd", Field, 0}, {"Segment64.Filesz", Field, 0}, {"Segment64.Flag", Field, 0}, {"Segment64.Len", Field, 0}, {"Segment64.Maxprot", Field, 0}, {"Segment64.Memsz", Field, 0}, {"Segment64.Name", Field, 0}, {"Segment64.Nsect", Field, 0}, {"Segment64.Offset", Field, 0}, {"Segment64.Prot", Field, 0}, {"SegmentHeader", Type, 0}, {"SegmentHeader.Addr", Field, 0}, {"SegmentHeader.Cmd", Field, 0}, {"SegmentHeader.Filesz", Field, 0}, {"SegmentHeader.Flag", Field, 0}, {"SegmentHeader.Len", Field, 0}, {"SegmentHeader.Maxprot", Field, 0}, {"SegmentHeader.Memsz", Field, 0}, {"SegmentHeader.Name", Field, 0}, {"SegmentHeader.Nsect", Field, 0}, {"SegmentHeader.Offset", Field, 0}, {"SegmentHeader.Prot", Field, 0}, {"Symbol", Type, 0}, {"Symbol.Desc", Field, 0}, {"Symbol.Name", Field, 0}, {"Symbol.Sect", Field, 0}, {"Symbol.Type", Field, 0}, {"Symbol.Value", Field, 0}, {"Symtab", Type, 0}, {"Symtab.LoadBytes", Field, 0}, {"Symtab.Syms", Field, 0}, {"Symtab.SymtabCmd", Field, 0}, {"SymtabCmd", Type, 0}, {"SymtabCmd.Cmd", Field, 0}, {"SymtabCmd.Len", Field, 0}, {"SymtabCmd.Nsyms", Field, 0}, {"SymtabCmd.Stroff", Field, 0}, {"SymtabCmd.Strsize", Field, 0}, {"SymtabCmd.Symoff", Field, 0}, {"Thread", Type, 0}, {"Thread.Cmd", Field, 0}, {"Thread.Data", Field, 0}, {"Thread.Len", Field, 0}, {"Thread.Type", Field, 0}, {"Type", Type, 0}, {"TypeBundle", Const, 3}, {"TypeDylib", Const, 3}, {"TypeExec", Const, 0}, {"TypeObj", Const, 0}, {"X86_64_RELOC_BRANCH", Const, 10}, {"X86_64_RELOC_GOT", Const, 10}, {"X86_64_RELOC_GOT_LOAD", Const, 10}, {"X86_64_RELOC_SIGNED", Const, 10}, {"X86_64_RELOC_SIGNED_1", Const, 10}, {"X86_64_RELOC_SIGNED_2", Const, 10}, {"X86_64_RELOC_SIGNED_4", Const, 10}, {"X86_64_RELOC_SUBTRACTOR", Const, 10}, {"X86_64_RELOC_TLV", Const, 10}, {"X86_64_RELOC_UNSIGNED", Const, 10}, }, "debug/pe": { {"(*COFFSymbol).FullName", Method, 8}, {"(*File).COFFSymbolReadSectionDefAux", Method, 19}, {"(*File).Close", Method, 0}, {"(*File).DWARF", Method, 0}, {"(*File).ImportedLibraries", Method, 0}, {"(*File).ImportedSymbols", Method, 0}, {"(*File).Section", Method, 0}, {"(*FormatError).Error", Method, 0}, {"(*Section).Data", Method, 0}, {"(*Section).Open", Method, 0}, {"(Section).ReadAt", Method, 0}, {"(StringTable).String", Method, 8}, {"COFFSymbol", Type, 1}, {"COFFSymbol.Name", Field, 1}, {"COFFSymbol.NumberOfAuxSymbols", Field, 1}, {"COFFSymbol.SectionNumber", Field, 1}, {"COFFSymbol.StorageClass", Field, 1}, {"COFFSymbol.Type", Field, 1}, {"COFFSymbol.Value", Field, 1}, {"COFFSymbolAuxFormat5", Type, 19}, {"COFFSymbolAuxFormat5.Checksum", Field, 19}, {"COFFSymbolAuxFormat5.NumLineNumbers", Field, 19}, {"COFFSymbolAuxFormat5.NumRelocs", Field, 19}, {"COFFSymbolAuxFormat5.SecNum", Field, 19}, {"COFFSymbolAuxFormat5.Selection", Field, 19}, {"COFFSymbolAuxFormat5.Size", Field, 19}, {"COFFSymbolSize", Const, 1}, {"DataDirectory", Type, 3}, {"DataDirectory.Size", Field, 3}, {"DataDirectory.VirtualAddress", Field, 3}, {"File", Type, 0}, {"File.COFFSymbols", Field, 8}, {"File.FileHeader", Field, 0}, {"File.OptionalHeader", Field, 3}, {"File.Sections", Field, 0}, {"File.StringTable", Field, 8}, {"File.Symbols", Field, 1}, {"FileHeader", Type, 0}, {"FileHeader.Characteristics", Field, 0}, {"FileHeader.Machine", Field, 0}, {"FileHeader.NumberOfSections", Field, 0}, {"FileHeader.NumberOfSymbols", Field, 0}, {"FileHeader.PointerToSymbolTable", Field, 0}, {"FileHeader.SizeOfOptionalHeader", Field, 0}, {"FileHeader.TimeDateStamp", Field, 0}, {"FormatError", Type, 0}, {"IMAGE_COMDAT_SELECT_ANY", Const, 19}, {"IMAGE_COMDAT_SELECT_ASSOCIATIVE", Const, 19}, {"IMAGE_COMDAT_SELECT_EXACT_MATCH", Const, 19}, {"IMAGE_COMDAT_SELECT_LARGEST", Const, 19}, {"IMAGE_COMDAT_SELECT_NODUPLICATES", Const, 19}, {"IMAGE_COMDAT_SELECT_SAME_SIZE", Const, 19}, {"IMAGE_DIRECTORY_ENTRY_ARCHITECTURE", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_BASERELOC", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_BOUND_IMPORT", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_COM_DESCRIPTOR", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_DEBUG", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_DELAY_IMPORT", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_EXCEPTION", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_EXPORT", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_GLOBALPTR", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_IAT", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_IMPORT", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_RESOURCE", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_SECURITY", Const, 11}, {"IMAGE_DIRECTORY_ENTRY_TLS", Const, 11}, {"IMAGE_DLLCHARACTERISTICS_APPCONTAINER", Const, 15}, {"IMAGE_DLLCHARACTERISTICS_DYNAMIC_BASE", Const, 15}, {"IMAGE_DLLCHARACTERISTICS_FORCE_INTEGRITY", Const, 15}, {"IMAGE_DLLCHARACTERISTICS_GUARD_CF", Const, 15}, {"IMAGE_DLLCHARACTERISTICS_HIGH_ENTROPY_VA", Const, 15}, {"IMAGE_DLLCHARACTERISTICS_NO_BIND", Const, 15}, {"IMAGE_DLLCHARACTERISTICS_NO_ISOLATION", Const, 15}, {"IMAGE_DLLCHARACTERISTICS_NO_SEH", Const, 15}, {"IMAGE_DLLCHARACTERISTICS_NX_COMPAT", Const, 15}, {"IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE", Const, 15}, {"IMAGE_DLLCHARACTERISTICS_WDM_DRIVER", Const, 15}, {"IMAGE_FILE_32BIT_MACHINE", Const, 15}, {"IMAGE_FILE_AGGRESIVE_WS_TRIM", Const, 15}, {"IMAGE_FILE_BYTES_REVERSED_HI", Const, 15}, {"IMAGE_FILE_BYTES_REVERSED_LO", Const, 15}, {"IMAGE_FILE_DEBUG_STRIPPED", Const, 15}, {"IMAGE_FILE_DLL", Const, 15}, {"IMAGE_FILE_EXECUTABLE_IMAGE", Const, 15}, {"IMAGE_FILE_LARGE_ADDRESS_AWARE", Const, 15}, {"IMAGE_FILE_LINE_NUMS_STRIPPED", Const, 15}, {"IMAGE_FILE_LOCAL_SYMS_STRIPPED", Const, 15}, {"IMAGE_FILE_MACHINE_AM33", Const, 0}, {"IMAGE_FILE_MACHINE_AMD64", Const, 0}, {"IMAGE_FILE_MACHINE_ARM", Const, 0}, {"IMAGE_FILE_MACHINE_ARM64", Const, 11}, {"IMAGE_FILE_MACHINE_ARMNT", Const, 12}, {"IMAGE_FILE_MACHINE_EBC", Const, 0}, {"IMAGE_FILE_MACHINE_I386", Const, 0}, {"IMAGE_FILE_MACHINE_IA64", Const, 0}, {"IMAGE_FILE_MACHINE_LOONGARCH32", Const, 19}, {"IMAGE_FILE_MACHINE_LOONGARCH64", Const, 19}, {"IMAGE_FILE_MACHINE_M32R", Const, 0}, {"IMAGE_FILE_MACHINE_MIPS16", Const, 0}, {"IMAGE_FILE_MACHINE_MIPSFPU", Const, 0}, {"IMAGE_FILE_MACHINE_MIPSFPU16", Const, 0}, {"IMAGE_FILE_MACHINE_POWERPC", Const, 0}, {"IMAGE_FILE_MACHINE_POWERPCFP", Const, 0}, {"IMAGE_FILE_MACHINE_R4000", Const, 0}, {"IMAGE_FILE_MACHINE_RISCV128", Const, 20}, {"IMAGE_FILE_MACHINE_RISCV32", Const, 20}, {"IMAGE_FILE_MACHINE_RISCV64", Const, 20}, {"IMAGE_FILE_MACHINE_SH3", Const, 0}, {"IMAGE_FILE_MACHINE_SH3DSP", Const, 0}, {"IMAGE_FILE_MACHINE_SH4", Const, 0}, {"IMAGE_FILE_MACHINE_SH5", Const, 0}, {"IMAGE_FILE_MACHINE_THUMB", Const, 0}, {"IMAGE_FILE_MACHINE_UNKNOWN", Const, 0}, {"IMAGE_FILE_MACHINE_WCEMIPSV2", Const, 0}, {"IMAGE_FILE_NET_RUN_FROM_SWAP", Const, 15}, {"IMAGE_FILE_RELOCS_STRIPPED", Const, 15}, {"IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP", Const, 15}, {"IMAGE_FILE_SYSTEM", Const, 15}, {"IMAGE_FILE_UP_SYSTEM_ONLY", Const, 15}, {"IMAGE_SCN_CNT_CODE", Const, 19}, {"IMAGE_SCN_CNT_INITIALIZED_DATA", Const, 19}, {"IMAGE_SCN_CNT_UNINITIALIZED_DATA", Const, 19}, {"IMAGE_SCN_LNK_COMDAT", Const, 19}, {"IMAGE_SCN_MEM_DISCARDABLE", Const, 19}, {"IMAGE_SCN_MEM_EXECUTE", Const, 19}, {"IMAGE_SCN_MEM_READ", Const, 19}, {"IMAGE_SCN_MEM_WRITE", Const, 19}, {"IMAGE_SUBSYSTEM_EFI_APPLICATION", Const, 15}, {"IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER", Const, 15}, {"IMAGE_SUBSYSTEM_EFI_ROM", Const, 15}, {"IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER", Const, 15}, {"IMAGE_SUBSYSTEM_NATIVE", Const, 15}, {"IMAGE_SUBSYSTEM_NATIVE_WINDOWS", Const, 15}, {"IMAGE_SUBSYSTEM_OS2_CUI", Const, 15}, {"IMAGE_SUBSYSTEM_POSIX_CUI", Const, 15}, {"IMAGE_SUBSYSTEM_UNKNOWN", Const, 15}, {"IMAGE_SUBSYSTEM_WINDOWS_BOOT_APPLICATION", Const, 15}, {"IMAGE_SUBSYSTEM_WINDOWS_CE_GUI", Const, 15}, {"IMAGE_SUBSYSTEM_WINDOWS_CUI", Const, 15}, {"IMAGE_SUBSYSTEM_WINDOWS_GUI", Const, 15}, {"IMAGE_SUBSYSTEM_XBOX", Const, 15}, {"ImportDirectory", Type, 0}, {"ImportDirectory.FirstThunk", Field, 0}, {"ImportDirectory.ForwarderChain", Field, 0}, {"ImportDirectory.Name", Field, 0}, {"ImportDirectory.OriginalFirstThunk", Field, 0}, {"ImportDirectory.TimeDateStamp", Field, 0}, {"NewFile", Func, 0}, {"Open", Func, 0}, {"OptionalHeader32", Type, 3}, {"OptionalHeader32.AddressOfEntryPoint", Field, 3}, {"OptionalHeader32.BaseOfCode", Field, 3}, {"OptionalHeader32.BaseOfData", Field, 3}, {"OptionalHeader32.CheckSum", Field, 3}, {"OptionalHeader32.DataDirectory", Field, 3}, {"OptionalHeader32.DllCharacteristics", Field, 3}, {"OptionalHeader32.FileAlignment", Field, 3}, {"OptionalHeader32.ImageBase", Field, 3}, {"OptionalHeader32.LoaderFlags", Field, 3}, {"OptionalHeader32.Magic", Field, 3}, {"OptionalHeader32.MajorImageVersion", Field, 3}, {"OptionalHeader32.MajorLinkerVersion", Field, 3}, {"OptionalHeader32.MajorOperatingSystemVersion", Field, 3}, {"OptionalHeader32.MajorSubsystemVersion", Field, 3}, {"OptionalHeader32.MinorImageVersion", Field, 3}, {"OptionalHeader32.MinorLinkerVersion", Field, 3}, {"OptionalHeader32.MinorOperatingSystemVersion", Field, 3}, {"OptionalHeader32.MinorSubsystemVersion", Field, 3}, {"OptionalHeader32.NumberOfRvaAndSizes", Field, 3}, {"OptionalHeader32.SectionAlignment", Field, 3}, {"OptionalHeader32.SizeOfCode", Field, 3}, {"OptionalHeader32.SizeOfHeaders", Field, 3}, {"OptionalHeader32.SizeOfHeapCommit", Field, 3}, {"OptionalHeader32.SizeOfHeapReserve", Field, 3}, {"OptionalHeader32.SizeOfImage", Field, 3}, {"OptionalHeader32.SizeOfInitializedData", Field, 3}, {"OptionalHeader32.SizeOfStackCommit", Field, 3}, {"OptionalHeader32.SizeOfStackReserve", Field, 3}, {"OptionalHeader32.SizeOfUninitializedData", Field, 3}, {"OptionalHeader32.Subsystem", Field, 3}, {"OptionalHeader32.Win32VersionValue", Field, 3}, {"OptionalHeader64", Type, 3}, {"OptionalHeader64.AddressOfEntryPoint", Field, 3}, {"OptionalHeader64.BaseOfCode", Field, 3}, {"OptionalHeader64.CheckSum", Field, 3}, {"OptionalHeader64.DataDirectory", Field, 3}, {"OptionalHeader64.DllCharacteristics", Field, 3}, {"OptionalHeader64.FileAlignment", Field, 3}, {"OptionalHeader64.ImageBase", Field, 3}, {"OptionalHeader64.LoaderFlags", Field, 3}, {"OptionalHeader64.Magic", Field, 3}, {"OptionalHeader64.MajorImageVersion", Field, 3}, {"OptionalHeader64.MajorLinkerVersion", Field, 3}, {"OptionalHeader64.MajorOperatingSystemVersion", Field, 3}, {"OptionalHeader64.MajorSubsystemVersion", Field, 3}, {"OptionalHeader64.MinorImageVersion", Field, 3}, {"OptionalHeader64.MinorLinkerVersion", Field, 3}, {"OptionalHeader64.MinorOperatingSystemVersion", Field, 3}, {"OptionalHeader64.MinorSubsystemVersion", Field, 3}, {"OptionalHeader64.NumberOfRvaAndSizes", Field, 3}, {"OptionalHeader64.SectionAlignment", Field, 3}, {"OptionalHeader64.SizeOfCode", Field, 3}, {"OptionalHeader64.SizeOfHeaders", Field, 3}, {"OptionalHeader64.SizeOfHeapCommit", Field, 3}, {"OptionalHeader64.SizeOfHeapReserve", Field, 3}, {"OptionalHeader64.SizeOfImage", Field, 3}, {"OptionalHeader64.SizeOfInitializedData", Field, 3}, {"OptionalHeader64.SizeOfStackCommit", Field, 3}, {"OptionalHeader64.SizeOfStackReserve", Field, 3}, {"OptionalHeader64.SizeOfUninitializedData", Field, 3}, {"OptionalHeader64.Subsystem", Field, 3}, {"OptionalHeader64.Win32VersionValue", Field, 3}, {"Reloc", Type, 8}, {"Reloc.SymbolTableIndex", Field, 8}, {"Reloc.Type", Field, 8}, {"Reloc.VirtualAddress", Field, 8}, {"Section", Type, 0}, {"Section.ReaderAt", Field, 0}, {"Section.Relocs", Field, 8}, {"Section.SectionHeader", Field, 0}, {"SectionHeader", Type, 0}, {"SectionHeader.Characteristics", Field, 0}, {"SectionHeader.Name", Field, 0}, {"SectionHeader.NumberOfLineNumbers", Field, 0}, {"SectionHeader.NumberOfRelocations", Field, 0}, {"SectionHeader.Offset", Field, 0}, {"SectionHeader.PointerToLineNumbers", Field, 0}, {"SectionHeader.PointerToRelocations", Field, 0}, {"SectionHeader.Size", Field, 0}, {"SectionHeader.VirtualAddress", Field, 0}, {"SectionHeader.VirtualSize", Field, 0}, {"SectionHeader32", Type, 0}, {"SectionHeader32.Characteristics", Field, 0}, {"SectionHeader32.Name", Field, 0}, {"SectionHeader32.NumberOfLineNumbers", Field, 0}, {"SectionHeader32.NumberOfRelocations", Field, 0}, {"SectionHeader32.PointerToLineNumbers", Field, 0}, {"SectionHeader32.PointerToRawData", Field, 0}, {"SectionHeader32.PointerToRelocations", Field, 0}, {"SectionHeader32.SizeOfRawData", Field, 0}, {"SectionHeader32.VirtualAddress", Field, 0}, {"SectionHeader32.VirtualSize", Field, 0}, {"StringTable", Type, 8}, {"Symbol", Type, 1}, {"Symbol.Name", Field, 1}, {"Symbol.SectionNumber", Field, 1}, {"Symbol.StorageClass", Field, 1}, {"Symbol.Type", Field, 1}, {"Symbol.Value", Field, 1}, }, "debug/plan9obj": { {"(*File).Close", Method, 3}, {"(*File).Section", Method, 3}, {"(*File).Symbols", Method, 3}, {"(*Section).Data", Method, 3}, {"(*Section).Open", Method, 3}, {"(Section).ReadAt", Method, 3}, {"ErrNoSymbols", Var, 18}, {"File", Type, 3}, {"File.FileHeader", Field, 3}, {"File.Sections", Field, 3}, {"FileHeader", Type, 3}, {"FileHeader.Bss", Field, 3}, {"FileHeader.Entry", Field, 3}, {"FileHeader.HdrSize", Field, 4}, {"FileHeader.LoadAddress", Field, 4}, {"FileHeader.Magic", Field, 3}, {"FileHeader.PtrSize", Field, 3}, {"Magic386", Const, 3}, {"Magic64", Const, 3}, {"MagicAMD64", Const, 3}, {"MagicARM", Const, 3}, {"NewFile", Func, 3}, {"Open", Func, 3}, {"Section", Type, 3}, {"Section.ReaderAt", Field, 3}, {"Section.SectionHeader", Field, 3}, {"SectionHeader", Type, 3}, {"SectionHeader.Name", Field, 3}, {"SectionHeader.Offset", Field, 3}, {"SectionHeader.Size", Field, 3}, {"Sym", Type, 3}, {"Sym.Name", Field, 3}, {"Sym.Type", Field, 3}, {"Sym.Value", Field, 3}, }, "embed": { {"(FS).Open", Method, 16}, {"(FS).ReadDir", Method, 16}, {"(FS).ReadFile", Method, 16}, {"FS", Type, 16}, }, "encoding": { {"BinaryAppender", Type, 24}, {"BinaryMarshaler", Type, 2}, {"BinaryUnmarshaler", Type, 2}, {"TextAppender", Type, 24}, {"TextMarshaler", Type, 2}, {"TextUnmarshaler", Type, 2}, }, "encoding/ascii85": { {"(CorruptInputError).Error", Method, 0}, {"CorruptInputError", Type, 0}, {"Decode", Func, 0}, {"Encode", Func, 0}, {"MaxEncodedLen", Func, 0}, {"NewDecoder", Func, 0}, {"NewEncoder", Func, 0}, }, "encoding/asn1": { {"(BitString).At", Method, 0}, {"(BitString).RightAlign", Method, 0}, {"(ObjectIdentifier).Equal", Method, 0}, {"(ObjectIdentifier).String", Method, 3}, {"(StructuralError).Error", Method, 0}, {"(SyntaxError).Error", Method, 0}, {"BitString", Type, 0}, {"BitString.BitLength", Field, 0}, {"BitString.Bytes", Field, 0}, {"ClassApplication", Const, 6}, {"ClassContextSpecific", Const, 6}, {"ClassPrivate", Const, 6}, {"ClassUniversal", Const, 6}, {"Enumerated", Type, 0}, {"Flag", Type, 0}, {"Marshal", Func, 0}, {"MarshalWithParams", Func, 10}, {"NullBytes", Var, 9}, {"NullRawValue", Var, 9}, {"ObjectIdentifier", Type, 0}, {"RawContent", Type, 0}, {"RawValue", Type, 0}, {"RawValue.Bytes", Field, 0}, {"RawValue.Class", Field, 0}, {"RawValue.FullBytes", Field, 0}, {"RawValue.IsCompound", Field, 0}, {"RawValue.Tag", Field, 0}, {"StructuralError", Type, 0}, {"StructuralError.Msg", Field, 0}, {"SyntaxError", Type, 0}, {"SyntaxError.Msg", Field, 0}, {"TagBMPString", Const, 14}, {"TagBitString", Const, 6}, {"TagBoolean", Const, 6}, {"TagEnum", Const, 6}, {"TagGeneralString", Const, 6}, {"TagGeneralizedTime", Const, 6}, {"TagIA5String", Const, 6}, {"TagInteger", Const, 6}, {"TagNull", Const, 9}, {"TagNumericString", Const, 10}, {"TagOID", Const, 6}, {"TagOctetString", Const, 6}, {"TagPrintableString", Const, 6}, {"TagSequence", Const, 6}, {"TagSet", Const, 6}, {"TagT61String", Const, 6}, {"TagUTCTime", Const, 6}, {"TagUTF8String", Const, 6}, {"Unmarshal", Func, 0}, {"UnmarshalWithParams", Func, 0}, }, "encoding/base32": { {"(*Encoding).AppendDecode", Method, 22}, {"(*Encoding).AppendEncode", Method, 22}, {"(*Encoding).Decode", Method, 0}, {"(*Encoding).DecodeString", Method, 0}, {"(*Encoding).DecodedLen", Method, 0}, {"(*Encoding).Encode", Method, 0}, {"(*Encoding).EncodeToString", Method, 0}, {"(*Encoding).EncodedLen", Method, 0}, {"(CorruptInputError).Error", Method, 0}, {"(Encoding).WithPadding", Method, 9}, {"CorruptInputError", Type, 0}, {"Encoding", Type, 0}, {"HexEncoding", Var, 0}, {"NewDecoder", Func, 0}, {"NewEncoder", Func, 0}, {"NewEncoding", Func, 0}, {"NoPadding", Const, 9}, {"StdEncoding", Var, 0}, {"StdPadding", Const, 9}, }, "encoding/base64": { {"(*Encoding).AppendDecode", Method, 22}, {"(*Encoding).AppendEncode", Method, 22}, {"(*Encoding).Decode", Method, 0}, {"(*Encoding).DecodeString", Method, 0}, {"(*Encoding).DecodedLen", Method, 0}, {"(*Encoding).Encode", Method, 0}, {"(*Encoding).EncodeToString", Method, 0}, {"(*Encoding).EncodedLen", Method, 0}, {"(CorruptInputError).Error", Method, 0}, {"(Encoding).Strict", Method, 8}, {"(Encoding).WithPadding", Method, 5}, {"CorruptInputError", Type, 0}, {"Encoding", Type, 0}, {"NewDecoder", Func, 0}, {"NewEncoder", Func, 0}, {"NewEncoding", Func, 0}, {"NoPadding", Const, 5}, {"RawStdEncoding", Var, 5}, {"RawURLEncoding", Var, 5}, {"StdEncoding", Var, 0}, {"StdPadding", Const, 5}, {"URLEncoding", Var, 0}, }, "encoding/binary": { {"Append", Func, 23}, {"AppendByteOrder", Type, 19}, {"AppendUvarint", Func, 19}, {"AppendVarint", Func, 19}, {"BigEndian", Var, 0}, {"ByteOrder", Type, 0}, {"Decode", Func, 23}, {"Encode", Func, 23}, {"LittleEndian", Var, 0}, {"MaxVarintLen16", Const, 0}, {"MaxVarintLen32", Const, 0}, {"MaxVarintLen64", Const, 0}, {"NativeEndian", Var, 21}, {"PutUvarint", Func, 0}, {"PutVarint", Func, 0}, {"Read", Func, 0}, {"ReadUvarint", Func, 0}, {"ReadVarint", Func, 0}, {"Size", Func, 0}, {"Uvarint", Func, 0}, {"Varint", Func, 0}, {"Write", Func, 0}, }, "encoding/csv": { {"(*ParseError).Error", Method, 0}, {"(*ParseError).Unwrap", Method, 13}, {"(*Reader).FieldPos", Method, 17}, {"(*Reader).InputOffset", Method, 19}, {"(*Reader).Read", Method, 0}, {"(*Reader).ReadAll", Method, 0}, {"(*Writer).Error", Method, 1}, {"(*Writer).Flush", Method, 0}, {"(*Writer).Write", Method, 0}, {"(*Writer).WriteAll", Method, 0}, {"ErrBareQuote", Var, 0}, {"ErrFieldCount", Var, 0}, {"ErrQuote", Var, 0}, {"ErrTrailingComma", Var, 0}, {"NewReader", Func, 0}, {"NewWriter", Func, 0}, {"ParseError", Type, 0}, {"ParseError.Column", Field, 0}, {"ParseError.Err", Field, 0}, {"ParseError.Line", Field, 0}, {"ParseError.StartLine", Field, 10}, {"Reader", Type, 0}, {"Reader.Comma", Field, 0}, {"Reader.Comment", Field, 0}, {"Reader.FieldsPerRecord", Field, 0}, {"Reader.LazyQuotes", Field, 0}, {"Reader.ReuseRecord", Field, 9}, {"Reader.TrailingComma", Field, 0}, {"Reader.TrimLeadingSpace", Field, 0}, {"Writer", Type, 0}, {"Writer.Comma", Field, 0}, {"Writer.UseCRLF", Field, 0}, }, "encoding/gob": { {"(*Decoder).Decode", Method, 0}, {"(*Decoder).DecodeValue", Method, 0}, {"(*Encoder).Encode", Method, 0}, {"(*Encoder).EncodeValue", Method, 0}, {"CommonType", Type, 0}, {"CommonType.Id", Field, 0}, {"CommonType.Name", Field, 0}, {"Decoder", Type, 0}, {"Encoder", Type, 0}, {"GobDecoder", Type, 0}, {"GobEncoder", Type, 0}, {"NewDecoder", Func, 0}, {"NewEncoder", Func, 0}, {"Register", Func, 0}, {"RegisterName", Func, 0}, }, "encoding/hex": { {"(InvalidByteError).Error", Method, 0}, {"AppendDecode", Func, 22}, {"AppendEncode", Func, 22}, {"Decode", Func, 0}, {"DecodeString", Func, 0}, {"DecodedLen", Func, 0}, {"Dump", Func, 0}, {"Dumper", Func, 0}, {"Encode", Func, 0}, {"EncodeToString", Func, 0}, {"EncodedLen", Func, 0}, {"ErrLength", Var, 0}, {"InvalidByteError", Type, 0}, {"NewDecoder", Func, 10}, {"NewEncoder", Func, 10}, }, "encoding/json": { {"(*Decoder).Buffered", Method, 1}, {"(*Decoder).Decode", Method, 0}, {"(*Decoder).DisallowUnknownFields", Method, 10}, {"(*Decoder).InputOffset", Method, 14}, {"(*Decoder).More", Method, 5}, {"(*Decoder).Token", Method, 5}, {"(*Decoder).UseNumber", Method, 1}, {"(*Encoder).Encode", Method, 0}, {"(*Encoder).SetEscapeHTML", Method, 7}, {"(*Encoder).SetIndent", Method, 7}, {"(*InvalidUTF8Error).Error", Method, 0}, {"(*InvalidUnmarshalError).Error", Method, 0}, {"(*MarshalerError).Error", Method, 0}, {"(*MarshalerError).Unwrap", Method, 13}, {"(*RawMessage).MarshalJSON", Method, 0}, {"(*RawMessage).UnmarshalJSON", Method, 0}, {"(*SyntaxError).Error", Method, 0}, {"(*UnmarshalFieldError).Error", Method, 0}, {"(*UnmarshalTypeError).Error", Method, 0}, {"(*UnsupportedTypeError).Error", Method, 0}, {"(*UnsupportedValueError).Error", Method, 0}, {"(Delim).String", Method, 5}, {"(Number).Float64", Method, 1}, {"(Number).Int64", Method, 1}, {"(Number).String", Method, 1}, {"(RawMessage).MarshalJSON", Method, 8}, {"Compact", Func, 0}, {"Decoder", Type, 0}, {"Delim", Type, 5}, {"Encoder", Type, 0}, {"HTMLEscape", Func, 0}, {"Indent", Func, 0}, {"InvalidUTF8Error", Type, 0}, {"InvalidUTF8Error.S", Field, 0}, {"InvalidUnmarshalError", Type, 0}, {"InvalidUnmarshalError.Type", Field, 0}, {"Marshal", Func, 0}, {"MarshalIndent", Func, 0}, {"Marshaler", Type, 0}, {"MarshalerError", Type, 0}, {"MarshalerError.Err", Field, 0}, {"MarshalerError.Type", Field, 0}, {"NewDecoder", Func, 0}, {"NewEncoder", Func, 0}, {"Number", Type, 1}, {"RawMessage", Type, 0}, {"SyntaxError", Type, 0}, {"SyntaxError.Offset", Field, 0}, {"Token", Type, 5}, {"Unmarshal", Func, 0}, {"UnmarshalFieldError", Type, 0}, {"UnmarshalFieldError.Field", Field, 0}, {"UnmarshalFieldError.Key", Field, 0}, {"UnmarshalFieldError.Type", Field, 0}, {"UnmarshalTypeError", Type, 0}, {"UnmarshalTypeError.Field", Field, 8}, {"UnmarshalTypeError.Offset", Field, 5}, {"UnmarshalTypeError.Struct", Field, 8}, {"UnmarshalTypeError.Type", Field, 0}, {"UnmarshalTypeError.Value", Field, 0}, {"Unmarshaler", Type, 0}, {"UnsupportedTypeError", Type, 0}, {"UnsupportedTypeError.Type", Field, 0}, {"UnsupportedValueError", Type, 0}, {"UnsupportedValueError.Str", Field, 0}, {"UnsupportedValueError.Value", Field, 0}, {"Valid", Func, 9}, }, "encoding/pem": { {"Block", Type, 0}, {"Block.Bytes", Field, 0}, {"Block.Headers", Field, 0}, {"Block.Type", Field, 0}, {"Decode", Func, 0}, {"Encode", Func, 0}, {"EncodeToMemory", Func, 0}, }, "encoding/xml": { {"(*Decoder).Decode", Method, 0}, {"(*Decoder).DecodeElement", Method, 0}, {"(*Decoder).InputOffset", Method, 4}, {"(*Decoder).InputPos", Method, 19}, {"(*Decoder).RawToken", Method, 0}, {"(*Decoder).Skip", Method, 0}, {"(*Decoder).Token", Method, 0}, {"(*Encoder).Close", Method, 20}, {"(*Encoder).Encode", Method, 0}, {"(*Encoder).EncodeElement", Method, 2}, {"(*Encoder).EncodeToken", Method, 2}, {"(*Encoder).Flush", Method, 2}, {"(*Encoder).Indent", Method, 1}, {"(*SyntaxError).Error", Method, 0}, {"(*TagPathError).Error", Method, 0}, {"(*UnsupportedTypeError).Error", Method, 0}, {"(CharData).Copy", Method, 0}, {"(Comment).Copy", Method, 0}, {"(Directive).Copy", Method, 0}, {"(ProcInst).Copy", Method, 0}, {"(StartElement).Copy", Method, 0}, {"(StartElement).End", Method, 2}, {"(UnmarshalError).Error", Method, 0}, {"Attr", Type, 0}, {"Attr.Name", Field, 0}, {"Attr.Value", Field, 0}, {"CharData", Type, 0}, {"Comment", Type, 0}, {"CopyToken", Func, 0}, {"Decoder", Type, 0}, {"Decoder.AutoClose", Field, 0}, {"Decoder.CharsetReader", Field, 0}, {"Decoder.DefaultSpace", Field, 1}, {"Decoder.Entity", Field, 0}, {"Decoder.Strict", Field, 0}, {"Directive", Type, 0}, {"Encoder", Type, 0}, {"EndElement", Type, 0}, {"EndElement.Name", Field, 0}, {"Escape", Func, 0}, {"EscapeText", Func, 1}, {"HTMLAutoClose", Var, 0}, {"HTMLEntity", Var, 0}, {"Header", Const, 0}, {"Marshal", Func, 0}, {"MarshalIndent", Func, 0}, {"Marshaler", Type, 2}, {"MarshalerAttr", Type, 2}, {"Name", Type, 0}, {"Name.Local", Field, 0}, {"Name.Space", Field, 0}, {"NewDecoder", Func, 0}, {"NewEncoder", Func, 0}, {"NewTokenDecoder", Func, 10}, {"ProcInst", Type, 0}, {"ProcInst.Inst", Field, 0}, {"ProcInst.Target", Field, 0}, {"StartElement", Type, 0}, {"StartElement.Attr", Field, 0}, {"StartElement.Name", Field, 0}, {"SyntaxError", Type, 0}, {"SyntaxError.Line", Field, 0}, {"SyntaxError.Msg", Field, 0}, {"TagPathError", Type, 0}, {"TagPathError.Field1", Field, 0}, {"TagPathError.Field2", Field, 0}, {"TagPathError.Struct", Field, 0}, {"TagPathError.Tag1", Field, 0}, {"TagPathError.Tag2", Field, 0}, {"Token", Type, 0}, {"TokenReader", Type, 10}, {"Unmarshal", Func, 0}, {"UnmarshalError", Type, 0}, {"Unmarshaler", Type, 2}, {"UnmarshalerAttr", Type, 2}, {"UnsupportedTypeError", Type, 0}, {"UnsupportedTypeError.Type", Field, 0}, }, "errors": { {"As", Func, 13}, {"ErrUnsupported", Var, 21}, {"Is", Func, 13}, {"Join", Func, 20}, {"New", Func, 0}, {"Unwrap", Func, 13}, }, "expvar": { {"(*Float).Add", Method, 0}, {"(*Float).Set", Method, 0}, {"(*Float).String", Method, 0}, {"(*Float).Value", Method, 8}, {"(*Int).Add", Method, 0}, {"(*Int).Set", Method, 0}, {"(*Int).String", Method, 0}, {"(*Int).Value", Method, 8}, {"(*Map).Add", Method, 0}, {"(*Map).AddFloat", Method, 0}, {"(*Map).Delete", Method, 12}, {"(*Map).Do", Method, 0}, {"(*Map).Get", Method, 0}, {"(*Map).Init", Method, 0}, {"(*Map).Set", Method, 0}, {"(*Map).String", Method, 0}, {"(*String).Set", Method, 0}, {"(*String).String", Method, 0}, {"(*String).Value", Method, 8}, {"(Func).String", Method, 0}, {"(Func).Value", Method, 8}, {"Do", Func, 0}, {"Float", Type, 0}, {"Func", Type, 0}, {"Get", Func, 0}, {"Handler", Func, 8}, {"Int", Type, 0}, {"KeyValue", Type, 0}, {"KeyValue.Key", Field, 0}, {"KeyValue.Value", Field, 0}, {"Map", Type, 0}, {"NewFloat", Func, 0}, {"NewInt", Func, 0}, {"NewMap", Func, 0}, {"NewString", Func, 0}, {"Publish", Func, 0}, {"String", Type, 0}, {"Var", Type, 0}, }, "flag": { {"(*FlagSet).Arg", Method, 0}, {"(*FlagSet).Args", Method, 0}, {"(*FlagSet).Bool", Method, 0}, {"(*FlagSet).BoolFunc", Method, 21}, {"(*FlagSet).BoolVar", Method, 0}, {"(*FlagSet).Duration", Method, 0}, {"(*FlagSet).DurationVar", Method, 0}, {"(*FlagSet).ErrorHandling", Method, 10}, {"(*FlagSet).Float64", Method, 0}, {"(*FlagSet).Float64Var", Method, 0}, {"(*FlagSet).Func", Method, 16}, {"(*FlagSet).Init", Method, 0}, {"(*FlagSet).Int", Method, 0}, {"(*FlagSet).Int64", Method, 0}, {"(*FlagSet).Int64Var", Method, 0}, {"(*FlagSet).IntVar", Method, 0}, {"(*FlagSet).Lookup", Method, 0}, {"(*FlagSet).NArg", Method, 0}, {"(*FlagSet).NFlag", Method, 0}, {"(*FlagSet).Name", Method, 10}, {"(*FlagSet).Output", Method, 10}, {"(*FlagSet).Parse", Method, 0}, {"(*FlagSet).Parsed", Method, 0}, {"(*FlagSet).PrintDefaults", Method, 0}, {"(*FlagSet).Set", Method, 0}, {"(*FlagSet).SetOutput", Method, 0}, {"(*FlagSet).String", Method, 0}, {"(*FlagSet).StringVar", Method, 0}, {"(*FlagSet).TextVar", Method, 19}, {"(*FlagSet).Uint", Method, 0}, {"(*FlagSet).Uint64", Method, 0}, {"(*FlagSet).Uint64Var", Method, 0}, {"(*FlagSet).UintVar", Method, 0}, {"(*FlagSet).Var", Method, 0}, {"(*FlagSet).Visit", Method, 0}, {"(*FlagSet).VisitAll", Method, 0}, {"Arg", Func, 0}, {"Args", Func, 0}, {"Bool", Func, 0}, {"BoolFunc", Func, 21}, {"BoolVar", Func, 0}, {"CommandLine", Var, 2}, {"ContinueOnError", Const, 0}, {"Duration", Func, 0}, {"DurationVar", Func, 0}, {"ErrHelp", Var, 0}, {"ErrorHandling", Type, 0}, {"ExitOnError", Const, 0}, {"Flag", Type, 0}, {"Flag.DefValue", Field, 0}, {"Flag.Name", Field, 0}, {"Flag.Usage", Field, 0}, {"Flag.Value", Field, 0}, {"FlagSet", Type, 0}, {"FlagSet.Usage", Field, 0}, {"Float64", Func, 0}, {"Float64Var", Func, 0}, {"Func", Func, 16}, {"Getter", Type, 2}, {"Int", Func, 0}, {"Int64", Func, 0}, {"Int64Var", Func, 0}, {"IntVar", Func, 0}, {"Lookup", Func, 0}, {"NArg", Func, 0}, {"NFlag", Func, 0}, {"NewFlagSet", Func, 0}, {"PanicOnError", Const, 0}, {"Parse", Func, 0}, {"Parsed", Func, 0}, {"PrintDefaults", Func, 0}, {"Set", Func, 0}, {"String", Func, 0}, {"StringVar", Func, 0}, {"TextVar", Func, 19}, {"Uint", Func, 0}, {"Uint64", Func, 0}, {"Uint64Var", Func, 0}, {"UintVar", Func, 0}, {"UnquoteUsage", Func, 5}, {"Usage", Var, 0}, {"Value", Type, 0}, {"Var", Func, 0}, {"Visit", Func, 0}, {"VisitAll", Func, 0}, }, "fmt": { {"Append", Func, 19}, {"Appendf", Func, 19}, {"Appendln", Func, 19}, {"Errorf", Func, 0}, {"FormatString", Func, 20}, {"Formatter", Type, 0}, {"Fprint", Func, 0}, {"Fprintf", Func, 0}, {"Fprintln", Func, 0}, {"Fscan", Func, 0}, {"Fscanf", Func, 0}, {"Fscanln", Func, 0}, {"GoStringer", Type, 0}, {"Print", Func, 0}, {"Printf", Func, 0}, {"Println", Func, 0}, {"Scan", Func, 0}, {"ScanState", Type, 0}, {"Scanf", Func, 0}, {"Scanln", Func, 0}, {"Scanner", Type, 0}, {"Sprint", Func, 0}, {"Sprintf", Func, 0}, {"Sprintln", Func, 0}, {"Sscan", Func, 0}, {"Sscanf", Func, 0}, {"Sscanln", Func, 0}, {"State", Type, 0}, {"Stringer", Type, 0}, }, "go/ast": { {"(*ArrayType).End", Method, 0}, {"(*ArrayType).Pos", Method, 0}, {"(*AssignStmt).End", Method, 0}, {"(*AssignStmt).Pos", Method, 0}, {"(*BadDecl).End", Method, 0}, {"(*BadDecl).Pos", Method, 0}, {"(*BadExpr).End", Method, 0}, {"(*BadExpr).Pos", Method, 0}, {"(*BadStmt).End", Method, 0}, {"(*BadStmt).Pos", Method, 0}, {"(*BasicLit).End", Method, 0}, {"(*BasicLit).Pos", Method, 0}, {"(*BinaryExpr).End", Method, 0}, {"(*BinaryExpr).Pos", Method, 0}, {"(*BlockStmt).End", Method, 0}, {"(*BlockStmt).Pos", Method, 0}, {"(*BranchStmt).End", Method, 0}, {"(*BranchStmt).Pos", Method, 0}, {"(*CallExpr).End", Method, 0}, {"(*CallExpr).Pos", Method, 0}, {"(*CaseClause).End", Method, 0}, {"(*CaseClause).Pos", Method, 0}, {"(*ChanType).End", Method, 0}, {"(*ChanType).Pos", Method, 0}, {"(*CommClause).End", Method, 0}, {"(*CommClause).Pos", Method, 0}, {"(*Comment).End", Method, 0}, {"(*Comment).Pos", Method, 0}, {"(*CommentGroup).End", Method, 0}, {"(*CommentGroup).Pos", Method, 0}, {"(*CommentGroup).Text", Method, 0}, {"(*CompositeLit).End", Method, 0}, {"(*CompositeLit).Pos", Method, 0}, {"(*DeclStmt).End", Method, 0}, {"(*DeclStmt).Pos", Method, 0}, {"(*DeferStmt).End", Method, 0}, {"(*DeferStmt).Pos", Method, 0}, {"(*Ellipsis).End", Method, 0}, {"(*Ellipsis).Pos", Method, 0}, {"(*EmptyStmt).End", Method, 0}, {"(*EmptyStmt).Pos", Method, 0}, {"(*ExprStmt).End", Method, 0}, {"(*ExprStmt).Pos", Method, 0}, {"(*Field).End", Method, 0}, {"(*Field).Pos", Method, 0}, {"(*FieldList).End", Method, 0}, {"(*FieldList).NumFields", Method, 0}, {"(*FieldList).Pos", Method, 0}, {"(*File).End", Method, 0}, {"(*File).Pos", Method, 0}, {"(*ForStmt).End", Method, 0}, {"(*ForStmt).Pos", Method, 0}, {"(*FuncDecl).End", Method, 0}, {"(*FuncDecl).Pos", Method, 0}, {"(*FuncLit).End", Method, 0}, {"(*FuncLit).Pos", Method, 0}, {"(*FuncType).End", Method, 0}, {"(*FuncType).Pos", Method, 0}, {"(*GenDecl).End", Method, 0}, {"(*GenDecl).Pos", Method, 0}, {"(*GoStmt).End", Method, 0}, {"(*GoStmt).Pos", Method, 0}, {"(*Ident).End", Method, 0}, {"(*Ident).IsExported", Method, 0}, {"(*Ident).Pos", Method, 0}, {"(*Ident).String", Method, 0}, {"(*IfStmt).End", Method, 0}, {"(*IfStmt).Pos", Method, 0}, {"(*ImportSpec).End", Method, 0}, {"(*ImportSpec).Pos", Method, 0}, {"(*IncDecStmt).End", Method, 0}, {"(*IncDecStmt).Pos", Method, 0}, {"(*IndexExpr).End", Method, 0}, {"(*IndexExpr).Pos", Method, 0}, {"(*IndexListExpr).End", Method, 18}, {"(*IndexListExpr).Pos", Method, 18}, {"(*InterfaceType).End", Method, 0}, {"(*InterfaceType).Pos", Method, 0}, {"(*KeyValueExpr).End", Method, 0}, {"(*KeyValueExpr).Pos", Method, 0}, {"(*LabeledStmt).End", Method, 0}, {"(*LabeledStmt).Pos", Method, 0}, {"(*MapType).End", Method, 0}, {"(*MapType).Pos", Method, 0}, {"(*Object).Pos", Method, 0}, {"(*Package).End", Method, 0}, {"(*Package).Pos", Method, 0}, {"(*ParenExpr).End", Method, 0}, {"(*ParenExpr).Pos", Method, 0}, {"(*RangeStmt).End", Method, 0}, {"(*RangeStmt).Pos", Method, 0}, {"(*ReturnStmt).End", Method, 0}, {"(*ReturnStmt).Pos", Method, 0}, {"(*Scope).Insert", Method, 0}, {"(*Scope).Lookup", Method, 0}, {"(*Scope).String", Method, 0}, {"(*SelectStmt).End", Method, 0}, {"(*SelectStmt).Pos", Method, 0}, {"(*SelectorExpr).End", Method, 0}, {"(*SelectorExpr).Pos", Method, 0}, {"(*SendStmt).End", Method, 0}, {"(*SendStmt).Pos", Method, 0}, {"(*SliceExpr).End", Method, 0}, {"(*SliceExpr).Pos", Method, 0}, {"(*StarExpr).End", Method, 0}, {"(*StarExpr).Pos", Method, 0}, {"(*StructType).End", Method, 0}, {"(*StructType).Pos", Method, 0}, {"(*SwitchStmt).End", Method, 0}, {"(*SwitchStmt).Pos", Method, 0}, {"(*TypeAssertExpr).End", Method, 0}, {"(*TypeAssertExpr).Pos", Method, 0}, {"(*TypeSpec).End", Method, 0}, {"(*TypeSpec).Pos", Method, 0}, {"(*TypeSwitchStmt).End", Method, 0}, {"(*TypeSwitchStmt).Pos", Method, 0}, {"(*UnaryExpr).End", Method, 0}, {"(*UnaryExpr).Pos", Method, 0}, {"(*ValueSpec).End", Method, 0}, {"(*ValueSpec).Pos", Method, 0}, {"(CommentMap).Comments", Method, 1}, {"(CommentMap).Filter", Method, 1}, {"(CommentMap).String", Method, 1}, {"(CommentMap).Update", Method, 1}, {"(ObjKind).String", Method, 0}, {"ArrayType", Type, 0}, {"ArrayType.Elt", Field, 0}, {"ArrayType.Lbrack", Field, 0}, {"ArrayType.Len", Field, 0}, {"AssignStmt", Type, 0}, {"AssignStmt.Lhs", Field, 0}, {"AssignStmt.Rhs", Field, 0}, {"AssignStmt.Tok", Field, 0}, {"AssignStmt.TokPos", Field, 0}, {"Bad", Const, 0}, {"BadDecl", Type, 0}, {"BadDecl.From", Field, 0}, {"BadDecl.To", Field, 0}, {"BadExpr", Type, 0}, {"BadExpr.From", Field, 0}, {"BadExpr.To", Field, 0}, {"BadStmt", Type, 0}, {"BadStmt.From", Field, 0}, {"BadStmt.To", Field, 0}, {"BasicLit", Type, 0}, {"BasicLit.Kind", Field, 0}, {"BasicLit.Value", Field, 0}, {"BasicLit.ValuePos", Field, 0}, {"BinaryExpr", Type, 0}, {"BinaryExpr.Op", Field, 0}, {"BinaryExpr.OpPos", Field, 0}, {"BinaryExpr.X", Field, 0}, {"BinaryExpr.Y", Field, 0}, {"BlockStmt", Type, 0}, {"BlockStmt.Lbrace", Field, 0}, {"BlockStmt.List", Field, 0}, {"BlockStmt.Rbrace", Field, 0}, {"BranchStmt", Type, 0}, {"BranchStmt.Label", Field, 0}, {"BranchStmt.Tok", Field, 0}, {"BranchStmt.TokPos", Field, 0}, {"CallExpr", Type, 0}, {"CallExpr.Args", Field, 0}, {"CallExpr.Ellipsis", Field, 0}, {"CallExpr.Fun", Field, 0}, {"CallExpr.Lparen", Field, 0}, {"CallExpr.Rparen", Field, 0}, {"CaseClause", Type, 0}, {"CaseClause.Body", Field, 0}, {"CaseClause.Case", Field, 0}, {"CaseClause.Colon", Field, 0}, {"CaseClause.List", Field, 0}, {"ChanDir", Type, 0}, {"ChanType", Type, 0}, {"ChanType.Arrow", Field, 1}, {"ChanType.Begin", Field, 0}, {"ChanType.Dir", Field, 0}, {"ChanType.Value", Field, 0}, {"CommClause", Type, 0}, {"CommClause.Body", Field, 0}, {"CommClause.Case", Field, 0}, {"CommClause.Colon", Field, 0}, {"CommClause.Comm", Field, 0}, {"Comment", Type, 0}, {"Comment.Slash", Field, 0}, {"Comment.Text", Field, 0}, {"CommentGroup", Type, 0}, {"CommentGroup.List", Field, 0}, {"CommentMap", Type, 1}, {"CompositeLit", Type, 0}, {"CompositeLit.Elts", Field, 0}, {"CompositeLit.Incomplete", Field, 11}, {"CompositeLit.Lbrace", Field, 0}, {"CompositeLit.Rbrace", Field, 0}, {"CompositeLit.Type", Field, 0}, {"Con", Const, 0}, {"Decl", Type, 0}, {"DeclStmt", Type, 0}, {"DeclStmt.Decl", Field, 0}, {"DeferStmt", Type, 0}, {"DeferStmt.Call", Field, 0}, {"DeferStmt.Defer", Field, 0}, {"Ellipsis", Type, 0}, {"Ellipsis.Ellipsis", Field, 0}, {"Ellipsis.Elt", Field, 0}, {"EmptyStmt", Type, 0}, {"EmptyStmt.Implicit", Field, 5}, {"EmptyStmt.Semicolon", Field, 0}, {"Expr", Type, 0}, {"ExprStmt", Type, 0}, {"ExprStmt.X", Field, 0}, {"Field", Type, 0}, {"Field.Comment", Field, 0}, {"Field.Doc", Field, 0}, {"Field.Names", Field, 0}, {"Field.Tag", Field, 0}, {"Field.Type", Field, 0}, {"FieldFilter", Type, 0}, {"FieldList", Type, 0}, {"FieldList.Closing", Field, 0}, {"FieldList.List", Field, 0}, {"FieldList.Opening", Field, 0}, {"File", Type, 0}, {"File.Comments", Field, 0}, {"File.Decls", Field, 0}, {"File.Doc", Field, 0}, {"File.FileEnd", Field, 20}, {"File.FileStart", Field, 20}, {"File.GoVersion", Field, 21}, {"File.Imports", Field, 0}, {"File.Name", Field, 0}, {"File.Package", Field, 0}, {"File.Scope", Field, 0}, {"File.Unresolved", Field, 0}, {"FileExports", Func, 0}, {"Filter", Type, 0}, {"FilterDecl", Func, 0}, {"FilterFile", Func, 0}, {"FilterFuncDuplicates", Const, 0}, {"FilterImportDuplicates", Const, 0}, {"FilterPackage", Func, 0}, {"FilterUnassociatedComments", Const, 0}, {"ForStmt", Type, 0}, {"ForStmt.Body", Field, 0}, {"ForStmt.Cond", Field, 0}, {"ForStmt.For", Field, 0}, {"ForStmt.Init", Field, 0}, {"ForStmt.Post", Field, 0}, {"Fprint", Func, 0}, {"Fun", Const, 0}, {"FuncDecl", Type, 0}, {"FuncDecl.Body", Field, 0}, {"FuncDecl.Doc", Field, 0}, {"FuncDecl.Name", Field, 0}, {"FuncDecl.Recv", Field, 0}, {"FuncDecl.Type", Field, 0}, {"FuncLit", Type, 0}, {"FuncLit.Body", Field, 0}, {"FuncLit.Type", Field, 0}, {"FuncType", Type, 0}, {"FuncType.Func", Field, 0}, {"FuncType.Params", Field, 0}, {"FuncType.Results", Field, 0}, {"FuncType.TypeParams", Field, 18}, {"GenDecl", Type, 0}, {"GenDecl.Doc", Field, 0}, {"GenDecl.Lparen", Field, 0}, {"GenDecl.Rparen", Field, 0}, {"GenDecl.Specs", Field, 0}, {"GenDecl.Tok", Field, 0}, {"GenDecl.TokPos", Field, 0}, {"GoStmt", Type, 0}, {"GoStmt.Call", Field, 0}, {"GoStmt.Go", Field, 0}, {"Ident", Type, 0}, {"Ident.Name", Field, 0}, {"Ident.NamePos", Field, 0}, {"Ident.Obj", Field, 0}, {"IfStmt", Type, 0}, {"IfStmt.Body", Field, 0}, {"IfStmt.Cond", Field, 0}, {"IfStmt.Else", Field, 0}, {"IfStmt.If", Field, 0}, {"IfStmt.Init", Field, 0}, {"ImportSpec", Type, 0}, {"ImportSpec.Comment", Field, 0}, {"ImportSpec.Doc", Field, 0}, {"ImportSpec.EndPos", Field, 0}, {"ImportSpec.Name", Field, 0}, {"ImportSpec.Path", Field, 0}, {"Importer", Type, 0}, {"IncDecStmt", Type, 0}, {"IncDecStmt.Tok", Field, 0}, {"IncDecStmt.TokPos", Field, 0}, {"IncDecStmt.X", Field, 0}, {"IndexExpr", Type, 0}, {"IndexExpr.Index", Field, 0}, {"IndexExpr.Lbrack", Field, 0}, {"IndexExpr.Rbrack", Field, 0}, {"IndexExpr.X", Field, 0}, {"IndexListExpr", Type, 18}, {"IndexListExpr.Indices", Field, 18}, {"IndexListExpr.Lbrack", Field, 18}, {"IndexListExpr.Rbrack", Field, 18}, {"IndexListExpr.X", Field, 18}, {"Inspect", Func, 0}, {"InterfaceType", Type, 0}, {"InterfaceType.Incomplete", Field, 0}, {"InterfaceType.Interface", Field, 0}, {"InterfaceType.Methods", Field, 0}, {"IsExported", Func, 0}, {"IsGenerated", Func, 21}, {"KeyValueExpr", Type, 0}, {"KeyValueExpr.Colon", Field, 0}, {"KeyValueExpr.Key", Field, 0}, {"KeyValueExpr.Value", Field, 0}, {"LabeledStmt", Type, 0}, {"LabeledStmt.Colon", Field, 0}, {"LabeledStmt.Label", Field, 0}, {"LabeledStmt.Stmt", Field, 0}, {"Lbl", Const, 0}, {"MapType", Type, 0}, {"MapType.Key", Field, 0}, {"MapType.Map", Field, 0}, {"MapType.Value", Field, 0}, {"MergeMode", Type, 0}, {"MergePackageFiles", Func, 0}, {"NewCommentMap", Func, 1}, {"NewIdent", Func, 0}, {"NewObj", Func, 0}, {"NewPackage", Func, 0}, {"NewScope", Func, 0}, {"Node", Type, 0}, {"NotNilFilter", Func, 0}, {"ObjKind", Type, 0}, {"Object", Type, 0}, {"Object.Data", Field, 0}, {"Object.Decl", Field, 0}, {"Object.Kind", Field, 0}, {"Object.Name", Field, 0}, {"Object.Type", Field, 0}, {"Package", Type, 0}, {"Package.Files", Field, 0}, {"Package.Imports", Field, 0}, {"Package.Name", Field, 0}, {"Package.Scope", Field, 0}, {"PackageExports", Func, 0}, {"ParenExpr", Type, 0}, {"ParenExpr.Lparen", Field, 0}, {"ParenExpr.Rparen", Field, 0}, {"ParenExpr.X", Field, 0}, {"Pkg", Const, 0}, {"Preorder", Func, 23}, {"Print", Func, 0}, {"RECV", Const, 0}, {"RangeStmt", Type, 0}, {"RangeStmt.Body", Field, 0}, {"RangeStmt.For", Field, 0}, {"RangeStmt.Key", Field, 0}, {"RangeStmt.Range", Field, 20}, {"RangeStmt.Tok", Field, 0}, {"RangeStmt.TokPos", Field, 0}, {"RangeStmt.Value", Field, 0}, {"RangeStmt.X", Field, 0}, {"ReturnStmt", Type, 0}, {"ReturnStmt.Results", Field, 0}, {"ReturnStmt.Return", Field, 0}, {"SEND", Const, 0}, {"Scope", Type, 0}, {"Scope.Objects", Field, 0}, {"Scope.Outer", Field, 0}, {"SelectStmt", Type, 0}, {"SelectStmt.Body", Field, 0}, {"SelectStmt.Select", Field, 0}, {"SelectorExpr", Type, 0}, {"SelectorExpr.Sel", Field, 0}, {"SelectorExpr.X", Field, 0}, {"SendStmt", Type, 0}, {"SendStmt.Arrow", Field, 0}, {"SendStmt.Chan", Field, 0}, {"SendStmt.Value", Field, 0}, {"SliceExpr", Type, 0}, {"SliceExpr.High", Field, 0}, {"SliceExpr.Lbrack", Field, 0}, {"SliceExpr.Low", Field, 0}, {"SliceExpr.Max", Field, 2}, {"SliceExpr.Rbrack", Field, 0}, {"SliceExpr.Slice3", Field, 2}, {"SliceExpr.X", Field, 0}, {"SortImports", Func, 0}, {"Spec", Type, 0}, {"StarExpr", Type, 0}, {"StarExpr.Star", Field, 0}, {"StarExpr.X", Field, 0}, {"Stmt", Type, 0}, {"StructType", Type, 0}, {"StructType.Fields", Field, 0}, {"StructType.Incomplete", Field, 0}, {"StructType.Struct", Field, 0}, {"SwitchStmt", Type, 0}, {"SwitchStmt.Body", Field, 0}, {"SwitchStmt.Init", Field, 0}, {"SwitchStmt.Switch", Field, 0}, {"SwitchStmt.Tag", Field, 0}, {"Typ", Const, 0}, {"TypeAssertExpr", Type, 0}, {"TypeAssertExpr.Lparen", Field, 2}, {"TypeAssertExpr.Rparen", Field, 2}, {"TypeAssertExpr.Type", Field, 0}, {"TypeAssertExpr.X", Field, 0}, {"TypeSpec", Type, 0}, {"TypeSpec.Assign", Field, 9}, {"TypeSpec.Comment", Field, 0}, {"TypeSpec.Doc", Field, 0}, {"TypeSpec.Name", Field, 0}, {"TypeSpec.Type", Field, 0}, {"TypeSpec.TypeParams", Field, 18}, {"TypeSwitchStmt", Type, 0}, {"TypeSwitchStmt.Assign", Field, 0}, {"TypeSwitchStmt.Body", Field, 0}, {"TypeSwitchStmt.Init", Field, 0}, {"TypeSwitchStmt.Switch", Field, 0}, {"UnaryExpr", Type, 0}, {"UnaryExpr.Op", Field, 0}, {"UnaryExpr.OpPos", Field, 0}, {"UnaryExpr.X", Field, 0}, {"Unparen", Func, 22}, {"ValueSpec", Type, 0}, {"ValueSpec.Comment", Field, 0}, {"ValueSpec.Doc", Field, 0}, {"ValueSpec.Names", Field, 0}, {"ValueSpec.Type", Field, 0}, {"ValueSpec.Values", Field, 0}, {"Var", Const, 0}, {"Visitor", Type, 0}, {"Walk", Func, 0}, }, "go/build": { {"(*Context).Import", Method, 0}, {"(*Context).ImportDir", Method, 0}, {"(*Context).MatchFile", Method, 2}, {"(*Context).SrcDirs", Method, 0}, {"(*MultiplePackageError).Error", Method, 4}, {"(*NoGoError).Error", Method, 0}, {"(*Package).IsCommand", Method, 0}, {"AllowBinary", Const, 0}, {"ArchChar", Func, 0}, {"Context", Type, 0}, {"Context.BuildTags", Field, 0}, {"Context.CgoEnabled", Field, 0}, {"Context.Compiler", Field, 0}, {"Context.Dir", Field, 14}, {"Context.GOARCH", Field, 0}, {"Context.GOOS", Field, 0}, {"Context.GOPATH", Field, 0}, {"Context.GOROOT", Field, 0}, {"Context.HasSubdir", Field, 0}, {"Context.InstallSuffix", Field, 1}, {"Context.IsAbsPath", Field, 0}, {"Context.IsDir", Field, 0}, {"Context.JoinPath", Field, 0}, {"Context.OpenFile", Field, 0}, {"Context.ReadDir", Field, 0}, {"Context.ReleaseTags", Field, 1}, {"Context.SplitPathList", Field, 0}, {"Context.ToolTags", Field, 17}, {"Context.UseAllFiles", Field, 0}, {"Default", Var, 0}, {"Directive", Type, 21}, {"Directive.Pos", Field, 21}, {"Directive.Text", Field, 21}, {"FindOnly", Const, 0}, {"IgnoreVendor", Const, 6}, {"Import", Func, 0}, {"ImportComment", Const, 4}, {"ImportDir", Func, 0}, {"ImportMode", Type, 0}, {"IsLocalImport", Func, 0}, {"MultiplePackageError", Type, 4}, {"MultiplePackageError.Dir", Field, 4}, {"MultiplePackageError.Files", Field, 4}, {"MultiplePackageError.Packages", Field, 4}, {"NoGoError", Type, 0}, {"NoGoError.Dir", Field, 0}, {"Package", Type, 0}, {"Package.AllTags", Field, 2}, {"Package.BinDir", Field, 0}, {"Package.BinaryOnly", Field, 7}, {"Package.CFiles", Field, 0}, {"Package.CXXFiles", Field, 2}, {"Package.CgoCFLAGS", Field, 0}, {"Package.CgoCPPFLAGS", Field, 2}, {"Package.CgoCXXFLAGS", Field, 2}, {"Package.CgoFFLAGS", Field, 7}, {"Package.CgoFiles", Field, 0}, {"Package.CgoLDFLAGS", Field, 0}, {"Package.CgoPkgConfig", Field, 0}, {"Package.ConflictDir", Field, 2}, {"Package.Dir", Field, 0}, {"Package.Directives", Field, 21}, {"Package.Doc", Field, 0}, {"Package.EmbedPatternPos", Field, 16}, {"Package.EmbedPatterns", Field, 16}, {"Package.FFiles", Field, 7}, {"Package.GoFiles", Field, 0}, {"Package.Goroot", Field, 0}, {"Package.HFiles", Field, 0}, {"Package.IgnoredGoFiles", Field, 1}, {"Package.IgnoredOtherFiles", Field, 16}, {"Package.ImportComment", Field, 4}, {"Package.ImportPath", Field, 0}, {"Package.ImportPos", Field, 0}, {"Package.Imports", Field, 0}, {"Package.InvalidGoFiles", Field, 6}, {"Package.MFiles", Field, 3}, {"Package.Name", Field, 0}, {"Package.PkgObj", Field, 0}, {"Package.PkgRoot", Field, 0}, {"Package.PkgTargetRoot", Field, 5}, {"Package.Root", Field, 0}, {"Package.SFiles", Field, 0}, {"Package.SrcRoot", Field, 0}, {"Package.SwigCXXFiles", Field, 1}, {"Package.SwigFiles", Field, 1}, {"Package.SysoFiles", Field, 0}, {"Package.TestDirectives", Field, 21}, {"Package.TestEmbedPatternPos", Field, 16}, {"Package.TestEmbedPatterns", Field, 16}, {"Package.TestGoFiles", Field, 0}, {"Package.TestImportPos", Field, 0}, {"Package.TestImports", Field, 0}, {"Package.XTestDirectives", Field, 21}, {"Package.XTestEmbedPatternPos", Field, 16}, {"Package.XTestEmbedPatterns", Field, 16}, {"Package.XTestGoFiles", Field, 0}, {"Package.XTestImportPos", Field, 0}, {"Package.XTestImports", Field, 0}, {"ToolDir", Var, 0}, }, "go/build/constraint": { {"(*AndExpr).Eval", Method, 16}, {"(*AndExpr).String", Method, 16}, {"(*NotExpr).Eval", Method, 16}, {"(*NotExpr).String", Method, 16}, {"(*OrExpr).Eval", Method, 16}, {"(*OrExpr).String", Method, 16}, {"(*SyntaxError).Error", Method, 16}, {"(*TagExpr).Eval", Method, 16}, {"(*TagExpr).String", Method, 16}, {"AndExpr", Type, 16}, {"AndExpr.X", Field, 16}, {"AndExpr.Y", Field, 16}, {"Expr", Type, 16}, {"GoVersion", Func, 21}, {"IsGoBuild", Func, 16}, {"IsPlusBuild", Func, 16}, {"NotExpr", Type, 16}, {"NotExpr.X", Field, 16}, {"OrExpr", Type, 16}, {"OrExpr.X", Field, 16}, {"OrExpr.Y", Field, 16}, {"Parse", Func, 16}, {"PlusBuildLines", Func, 16}, {"SyntaxError", Type, 16}, {"SyntaxError.Err", Field, 16}, {"SyntaxError.Offset", Field, 16}, {"TagExpr", Type, 16}, {"TagExpr.Tag", Field, 16}, }, "go/constant": { {"(Kind).String", Method, 18}, {"BinaryOp", Func, 5}, {"BitLen", Func, 5}, {"Bool", Const, 5}, {"BoolVal", Func, 5}, {"Bytes", Func, 5}, {"Compare", Func, 5}, {"Complex", Const, 5}, {"Denom", Func, 5}, {"Float", Const, 5}, {"Float32Val", Func, 5}, {"Float64Val", Func, 5}, {"Imag", Func, 5}, {"Int", Const, 5}, {"Int64Val", Func, 5}, {"Kind", Type, 5}, {"Make", Func, 13}, {"MakeBool", Func, 5}, {"MakeFloat64", Func, 5}, {"MakeFromBytes", Func, 5}, {"MakeFromLiteral", Func, 5}, {"MakeImag", Func, 5}, {"MakeInt64", Func, 5}, {"MakeString", Func, 5}, {"MakeUint64", Func, 5}, {"MakeUnknown", Func, 5}, {"Num", Func, 5}, {"Real", Func, 5}, {"Shift", Func, 5}, {"Sign", Func, 5}, {"String", Const, 5}, {"StringVal", Func, 5}, {"ToComplex", Func, 6}, {"ToFloat", Func, 6}, {"ToInt", Func, 6}, {"Uint64Val", Func, 5}, {"UnaryOp", Func, 5}, {"Unknown", Const, 5}, {"Val", Func, 13}, {"Value", Type, 5}, }, "go/doc": { {"(*Package).Filter", Method, 0}, {"(*Package).HTML", Method, 19}, {"(*Package).Markdown", Method, 19}, {"(*Package).Parser", Method, 19}, {"(*Package).Printer", Method, 19}, {"(*Package).Synopsis", Method, 19}, {"(*Package).Text", Method, 19}, {"AllDecls", Const, 0}, {"AllMethods", Const, 0}, {"Example", Type, 0}, {"Example.Code", Field, 0}, {"Example.Comments", Field, 0}, {"Example.Doc", Field, 0}, {"Example.EmptyOutput", Field, 1}, {"Example.Name", Field, 0}, {"Example.Order", Field, 1}, {"Example.Output", Field, 0}, {"Example.Play", Field, 1}, {"Example.Suffix", Field, 14}, {"Example.Unordered", Field, 7}, {"Examples", Func, 0}, {"Filter", Type, 0}, {"Func", Type, 0}, {"Func.Decl", Field, 0}, {"Func.Doc", Field, 0}, {"Func.Examples", Field, 14}, {"Func.Level", Field, 0}, {"Func.Name", Field, 0}, {"Func.Orig", Field, 0}, {"Func.Recv", Field, 0}, {"IllegalPrefixes", Var, 1}, {"IsPredeclared", Func, 8}, {"Mode", Type, 0}, {"New", Func, 0}, {"NewFromFiles", Func, 14}, {"Note", Type, 1}, {"Note.Body", Field, 1}, {"Note.End", Field, 1}, {"Note.Pos", Field, 1}, {"Note.UID", Field, 1}, {"Package", Type, 0}, {"Package.Bugs", Field, 0}, {"Package.Consts", Field, 0}, {"Package.Doc", Field, 0}, {"Package.Examples", Field, 14}, {"Package.Filenames", Field, 0}, {"Package.Funcs", Field, 0}, {"Package.ImportPath", Field, 0}, {"Package.Imports", Field, 0}, {"Package.Name", Field, 0}, {"Package.Notes", Field, 1}, {"Package.Types", Field, 0}, {"Package.Vars", Field, 0}, {"PreserveAST", Const, 12}, {"Synopsis", Func, 0}, {"ToHTML", Func, 0}, {"ToText", Func, 0}, {"Type", Type, 0}, {"Type.Consts", Field, 0}, {"Type.Decl", Field, 0}, {"Type.Doc", Field, 0}, {"Type.Examples", Field, 14}, {"Type.Funcs", Field, 0}, {"Type.Methods", Field, 0}, {"Type.Name", Field, 0}, {"Type.Vars", Field, 0}, {"Value", Type, 0}, {"Value.Decl", Field, 0}, {"Value.Doc", Field, 0}, {"Value.Names", Field, 0}, }, "go/doc/comment": { {"(*DocLink).DefaultURL", Method, 19}, {"(*Heading).DefaultID", Method, 19}, {"(*List).BlankBefore", Method, 19}, {"(*List).BlankBetween", Method, 19}, {"(*Parser).Parse", Method, 19}, {"(*Printer).Comment", Method, 19}, {"(*Printer).HTML", Method, 19}, {"(*Printer).Markdown", Method, 19}, {"(*Printer).Text", Method, 19}, {"Block", Type, 19}, {"Code", Type, 19}, {"Code.Text", Field, 19}, {"DefaultLookupPackage", Func, 19}, {"Doc", Type, 19}, {"Doc.Content", Field, 19}, {"Doc.Links", Field, 19}, {"DocLink", Type, 19}, {"DocLink.ImportPath", Field, 19}, {"DocLink.Name", Field, 19}, {"DocLink.Recv", Field, 19}, {"DocLink.Text", Field, 19}, {"Heading", Type, 19}, {"Heading.Text", Field, 19}, {"Italic", Type, 19}, {"Link", Type, 19}, {"Link.Auto", Field, 19}, {"Link.Text", Field, 19}, {"Link.URL", Field, 19}, {"LinkDef", Type, 19}, {"LinkDef.Text", Field, 19}, {"LinkDef.URL", Field, 19}, {"LinkDef.Used", Field, 19}, {"List", Type, 19}, {"List.ForceBlankBefore", Field, 19}, {"List.ForceBlankBetween", Field, 19}, {"List.Items", Field, 19}, {"ListItem", Type, 19}, {"ListItem.Content", Field, 19}, {"ListItem.Number", Field, 19}, {"Paragraph", Type, 19}, {"Paragraph.Text", Field, 19}, {"Parser", Type, 19}, {"Parser.LookupPackage", Field, 19}, {"Parser.LookupSym", Field, 19}, {"Parser.Words", Field, 19}, {"Plain", Type, 19}, {"Printer", Type, 19}, {"Printer.DocLinkBaseURL", Field, 19}, {"Printer.DocLinkURL", Field, 19}, {"Printer.HeadingID", Field, 19}, {"Printer.HeadingLevel", Field, 19}, {"Printer.TextCodePrefix", Field, 19}, {"Printer.TextPrefix", Field, 19}, {"Printer.TextWidth", Field, 19}, {"Text", Type, 19}, }, "go/format": { {"Node", Func, 1}, {"Source", Func, 1}, }, "go/importer": { {"Default", Func, 5}, {"For", Func, 5}, {"ForCompiler", Func, 12}, {"Lookup", Type, 5}, }, "go/parser": { {"AllErrors", Const, 1}, {"DeclarationErrors", Const, 0}, {"ImportsOnly", Const, 0}, {"Mode", Type, 0}, {"PackageClauseOnly", Const, 0}, {"ParseComments", Const, 0}, {"ParseDir", Func, 0}, {"ParseExpr", Func, 0}, {"ParseExprFrom", Func, 5}, {"ParseFile", Func, 0}, {"SkipObjectResolution", Const, 17}, {"SpuriousErrors", Const, 0}, {"Trace", Const, 0}, }, "go/printer": { {"(*Config).Fprint", Method, 0}, {"CommentedNode", Type, 0}, {"CommentedNode.Comments", Field, 0}, {"CommentedNode.Node", Field, 0}, {"Config", Type, 0}, {"Config.Indent", Field, 1}, {"Config.Mode", Field, 0}, {"Config.Tabwidth", Field, 0}, {"Fprint", Func, 0}, {"Mode", Type, 0}, {"RawFormat", Const, 0}, {"SourcePos", Const, 0}, {"TabIndent", Const, 0}, {"UseSpaces", Const, 0}, }, "go/scanner": { {"(*ErrorList).Add", Method, 0}, {"(*ErrorList).RemoveMultiples", Method, 0}, {"(*ErrorList).Reset", Method, 0}, {"(*Scanner).Init", Method, 0}, {"(*Scanner).Scan", Method, 0}, {"(Error).Error", Method, 0}, {"(ErrorList).Err", Method, 0}, {"(ErrorList).Error", Method, 0}, {"(ErrorList).Len", Method, 0}, {"(ErrorList).Less", Method, 0}, {"(ErrorList).Sort", Method, 0}, {"(ErrorList).Swap", Method, 0}, {"Error", Type, 0}, {"Error.Msg", Field, 0}, {"Error.Pos", Field, 0}, {"ErrorHandler", Type, 0}, {"ErrorList", Type, 0}, {"Mode", Type, 0}, {"PrintError", Func, 0}, {"ScanComments", Const, 0}, {"Scanner", Type, 0}, {"Scanner.ErrorCount", Field, 0}, }, "go/token": { {"(*File).AddLine", Method, 0}, {"(*File).AddLineColumnInfo", Method, 11}, {"(*File).AddLineInfo", Method, 0}, {"(*File).Base", Method, 0}, {"(*File).Line", Method, 0}, {"(*File).LineCount", Method, 0}, {"(*File).LineStart", Method, 12}, {"(*File).Lines", Method, 21}, {"(*File).MergeLine", Method, 2}, {"(*File).Name", Method, 0}, {"(*File).Offset", Method, 0}, {"(*File).Pos", Method, 0}, {"(*File).Position", Method, 0}, {"(*File).PositionFor", Method, 4}, {"(*File).SetLines", Method, 0}, {"(*File).SetLinesForContent", Method, 0}, {"(*File).Size", Method, 0}, {"(*FileSet).AddFile", Method, 0}, {"(*FileSet).Base", Method, 0}, {"(*FileSet).File", Method, 0}, {"(*FileSet).Iterate", Method, 0}, {"(*FileSet).Position", Method, 0}, {"(*FileSet).PositionFor", Method, 4}, {"(*FileSet).Read", Method, 0}, {"(*FileSet).RemoveFile", Method, 20}, {"(*FileSet).Write", Method, 0}, {"(*Position).IsValid", Method, 0}, {"(Pos).IsValid", Method, 0}, {"(Position).String", Method, 0}, {"(Token).IsKeyword", Method, 0}, {"(Token).IsLiteral", Method, 0}, {"(Token).IsOperator", Method, 0}, {"(Token).Precedence", Method, 0}, {"(Token).String", Method, 0}, {"ADD", Const, 0}, {"ADD_ASSIGN", Const, 0}, {"AND", Const, 0}, {"AND_ASSIGN", Const, 0}, {"AND_NOT", Const, 0}, {"AND_NOT_ASSIGN", Const, 0}, {"ARROW", Const, 0}, {"ASSIGN", Const, 0}, {"BREAK", Const, 0}, {"CASE", Const, 0}, {"CHAN", Const, 0}, {"CHAR", Const, 0}, {"COLON", Const, 0}, {"COMMA", Const, 0}, {"COMMENT", Const, 0}, {"CONST", Const, 0}, {"CONTINUE", Const, 0}, {"DEC", Const, 0}, {"DEFAULT", Const, 0}, {"DEFER", Const, 0}, {"DEFINE", Const, 0}, {"ELLIPSIS", Const, 0}, {"ELSE", Const, 0}, {"EOF", Const, 0}, {"EQL", Const, 0}, {"FALLTHROUGH", Const, 0}, {"FLOAT", Const, 0}, {"FOR", Const, 0}, {"FUNC", Const, 0}, {"File", Type, 0}, {"FileSet", Type, 0}, {"GEQ", Const, 0}, {"GO", Const, 0}, {"GOTO", Const, 0}, {"GTR", Const, 0}, {"HighestPrec", Const, 0}, {"IDENT", Const, 0}, {"IF", Const, 0}, {"ILLEGAL", Const, 0}, {"IMAG", Const, 0}, {"IMPORT", Const, 0}, {"INC", Const, 0}, {"INT", Const, 0}, {"INTERFACE", Const, 0}, {"IsExported", Func, 13}, {"IsIdentifier", Func, 13}, {"IsKeyword", Func, 13}, {"LAND", Const, 0}, {"LBRACE", Const, 0}, {"LBRACK", Const, 0}, {"LEQ", Const, 0}, {"LOR", Const, 0}, {"LPAREN", Const, 0}, {"LSS", Const, 0}, {"Lookup", Func, 0}, {"LowestPrec", Const, 0}, {"MAP", Const, 0}, {"MUL", Const, 0}, {"MUL_ASSIGN", Const, 0}, {"NEQ", Const, 0}, {"NOT", Const, 0}, {"NewFileSet", Func, 0}, {"NoPos", Const, 0}, {"OR", Const, 0}, {"OR_ASSIGN", Const, 0}, {"PACKAGE", Const, 0}, {"PERIOD", Const, 0}, {"Pos", Type, 0}, {"Position", Type, 0}, {"Position.Column", Field, 0}, {"Position.Filename", Field, 0}, {"Position.Line", Field, 0}, {"Position.Offset", Field, 0}, {"QUO", Const, 0}, {"QUO_ASSIGN", Const, 0}, {"RANGE", Const, 0}, {"RBRACE", Const, 0}, {"RBRACK", Const, 0}, {"REM", Const, 0}, {"REM_ASSIGN", Const, 0}, {"RETURN", Const, 0}, {"RPAREN", Const, 0}, {"SELECT", Const, 0}, {"SEMICOLON", Const, 0}, {"SHL", Const, 0}, {"SHL_ASSIGN", Const, 0}, {"SHR", Const, 0}, {"SHR_ASSIGN", Const, 0}, {"STRING", Const, 0}, {"STRUCT", Const, 0}, {"SUB", Const, 0}, {"SUB_ASSIGN", Const, 0}, {"SWITCH", Const, 0}, {"TILDE", Const, 18}, {"TYPE", Const, 0}, {"Token", Type, 0}, {"UnaryPrec", Const, 0}, {"VAR", Const, 0}, {"XOR", Const, 0}, {"XOR_ASSIGN", Const, 0}, }, "go/types": { {"(*Alias).Obj", Method, 22}, {"(*Alias).Origin", Method, 23}, {"(*Alias).Rhs", Method, 23}, {"(*Alias).SetTypeParams", Method, 23}, {"(*Alias).String", Method, 22}, {"(*Alias).TypeArgs", Method, 23}, {"(*Alias).TypeParams", Method, 23}, {"(*Alias).Underlying", Method, 22}, {"(*ArgumentError).Error", Method, 18}, {"(*ArgumentError).Unwrap", Method, 18}, {"(*Array).Elem", Method, 5}, {"(*Array).Len", Method, 5}, {"(*Array).String", Method, 5}, {"(*Array).Underlying", Method, 5}, {"(*Basic).Info", Method, 5}, {"(*Basic).Kind", Method, 5}, {"(*Basic).Name", Method, 5}, {"(*Basic).String", Method, 5}, {"(*Basic).Underlying", Method, 5}, {"(*Builtin).Exported", Method, 5}, {"(*Builtin).Id", Method, 5}, {"(*Builtin).Name", Method, 5}, {"(*Builtin).Parent", Method, 5}, {"(*Builtin).Pkg", Method, 5}, {"(*Builtin).Pos", Method, 5}, {"(*Builtin).String", Method, 5}, {"(*Builtin).Type", Method, 5}, {"(*Chan).Dir", Method, 5}, {"(*Chan).Elem", Method, 5}, {"(*Chan).String", Method, 5}, {"(*Chan).Underlying", Method, 5}, {"(*Checker).Files", Method, 5}, {"(*Config).Check", Method, 5}, {"(*Const).Exported", Method, 5}, {"(*Const).Id", Method, 5}, {"(*Const).Name", Method, 5}, {"(*Const).Parent", Method, 5}, {"(*Const).Pkg", Method, 5}, {"(*Const).Pos", Method, 5}, {"(*Const).String", Method, 5}, {"(*Const).Type", Method, 5}, {"(*Const).Val", Method, 5}, {"(*Func).Exported", Method, 5}, {"(*Func).FullName", Method, 5}, {"(*Func).Id", Method, 5}, {"(*Func).Name", Method, 5}, {"(*Func).Origin", Method, 19}, {"(*Func).Parent", Method, 5}, {"(*Func).Pkg", Method, 5}, {"(*Func).Pos", Method, 5}, {"(*Func).Scope", Method, 5}, {"(*Func).Signature", Method, 23}, {"(*Func).String", Method, 5}, {"(*Func).Type", Method, 5}, {"(*Info).ObjectOf", Method, 5}, {"(*Info).PkgNameOf", Method, 22}, {"(*Info).TypeOf", Method, 5}, {"(*Initializer).String", Method, 5}, {"(*Interface).Complete", Method, 5}, {"(*Interface).Embedded", Method, 5}, {"(*Interface).EmbeddedType", Method, 11}, {"(*Interface).EmbeddedTypes", Method, 24}, {"(*Interface).Empty", Method, 5}, {"(*Interface).ExplicitMethod", Method, 5}, {"(*Interface).ExplicitMethods", Method, 24}, {"(*Interface).IsComparable", Method, 18}, {"(*Interface).IsImplicit", Method, 18}, {"(*Interface).IsMethodSet", Method, 18}, {"(*Interface).MarkImplicit", Method, 18}, {"(*Interface).Method", Method, 5}, {"(*Interface).Methods", Method, 24}, {"(*Interface).NumEmbeddeds", Method, 5}, {"(*Interface).NumExplicitMethods", Method, 5}, {"(*Interface).NumMethods", Method, 5}, {"(*Interface).String", Method, 5}, {"(*Interface).Underlying", Method, 5}, {"(*Label).Exported", Method, 5}, {"(*Label).Id", Method, 5}, {"(*Label).Name", Method, 5}, {"(*Label).Parent", Method, 5}, {"(*Label).Pkg", Method, 5}, {"(*Label).Pos", Method, 5}, {"(*Label).String", Method, 5}, {"(*Label).Type", Method, 5}, {"(*Map).Elem", Method, 5}, {"(*Map).Key", Method, 5}, {"(*Map).String", Method, 5}, {"(*Map).Underlying", Method, 5}, {"(*MethodSet).At", Method, 5}, {"(*MethodSet).Len", Method, 5}, {"(*MethodSet).Lookup", Method, 5}, {"(*MethodSet).Methods", Method, 24}, {"(*MethodSet).String", Method, 5}, {"(*Named).AddMethod", Method, 5}, {"(*Named).Method", Method, 5}, {"(*Named).Methods", Method, 24}, {"(*Named).NumMethods", Method, 5}, {"(*Named).Obj", Method, 5}, {"(*Named).Origin", Method, 18}, {"(*Named).SetTypeParams", Method, 18}, {"(*Named).SetUnderlying", Method, 5}, {"(*Named).String", Method, 5}, {"(*Named).TypeArgs", Method, 18}, {"(*Named).TypeParams", Method, 18}, {"(*Named).Underlying", Method, 5}, {"(*Nil).Exported", Method, 5}, {"(*Nil).Id", Method, 5}, {"(*Nil).Name", Method, 5}, {"(*Nil).Parent", Method, 5}, {"(*Nil).Pkg", Method, 5}, {"(*Nil).Pos", Method, 5}, {"(*Nil).String", Method, 5}, {"(*Nil).Type", Method, 5}, {"(*Package).Complete", Method, 5}, {"(*Package).GoVersion", Method, 21}, {"(*Package).Imports", Method, 5}, {"(*Package).MarkComplete", Method, 5}, {"(*Package).Name", Method, 5}, {"(*Package).Path", Method, 5}, {"(*Package).Scope", Method, 5}, {"(*Package).SetImports", Method, 5}, {"(*Package).SetName", Method, 6}, {"(*Package).String", Method, 5}, {"(*PkgName).Exported", Method, 5}, {"(*PkgName).Id", Method, 5}, {"(*PkgName).Imported", Method, 5}, {"(*PkgName).Name", Method, 5}, {"(*PkgName).Parent", Method, 5}, {"(*PkgName).Pkg", Method, 5}, {"(*PkgName).Pos", Method, 5}, {"(*PkgName).String", Method, 5}, {"(*PkgName).Type", Method, 5}, {"(*Pointer).Elem", Method, 5}, {"(*Pointer).String", Method, 5}, {"(*Pointer).Underlying", Method, 5}, {"(*Scope).Child", Method, 5}, {"(*Scope).Children", Method, 24}, {"(*Scope).Contains", Method, 5}, {"(*Scope).End", Method, 5}, {"(*Scope).Innermost", Method, 5}, {"(*Scope).Insert", Method, 5}, {"(*Scope).Len", Method, 5}, {"(*Scope).Lookup", Method, 5}, {"(*Scope).LookupParent", Method, 5}, {"(*Scope).Names", Method, 5}, {"(*Scope).NumChildren", Method, 5}, {"(*Scope).Parent", Method, 5}, {"(*Scope).Pos", Method, 5}, {"(*Scope).String", Method, 5}, {"(*Scope).WriteTo", Method, 5}, {"(*Selection).Index", Method, 5}, {"(*Selection).Indirect", Method, 5}, {"(*Selection).Kind", Method, 5}, {"(*Selection).Obj", Method, 5}, {"(*Selection).Recv", Method, 5}, {"(*Selection).String", Method, 5}, {"(*Selection).Type", Method, 5}, {"(*Signature).Params", Method, 5}, {"(*Signature).Recv", Method, 5}, {"(*Signature).RecvTypeParams", Method, 18}, {"(*Signature).Results", Method, 5}, {"(*Signature).String", Method, 5}, {"(*Signature).TypeParams", Method, 18}, {"(*Signature).Underlying", Method, 5}, {"(*Signature).Variadic", Method, 5}, {"(*Slice).Elem", Method, 5}, {"(*Slice).String", Method, 5}, {"(*Slice).Underlying", Method, 5}, {"(*StdSizes).Alignof", Method, 5}, {"(*StdSizes).Offsetsof", Method, 5}, {"(*StdSizes).Sizeof", Method, 5}, {"(*Struct).Field", Method, 5}, {"(*Struct).Fields", Method, 24}, {"(*Struct).NumFields", Method, 5}, {"(*Struct).String", Method, 5}, {"(*Struct).Tag", Method, 5}, {"(*Struct).Underlying", Method, 5}, {"(*Term).String", Method, 18}, {"(*Term).Tilde", Method, 18}, {"(*Term).Type", Method, 18}, {"(*Tuple).At", Method, 5}, {"(*Tuple).Len", Method, 5}, {"(*Tuple).String", Method, 5}, {"(*Tuple).Underlying", Method, 5}, {"(*Tuple).Variables", Method, 24}, {"(*TypeList).At", Method, 18}, {"(*TypeList).Len", Method, 18}, {"(*TypeList).Types", Method, 24}, {"(*TypeName).Exported", Method, 5}, {"(*TypeName).Id", Method, 5}, {"(*TypeName).IsAlias", Method, 9}, {"(*TypeName).Name", Method, 5}, {"(*TypeName).Parent", Method, 5}, {"(*TypeName).Pkg", Method, 5}, {"(*TypeName).Pos", Method, 5}, {"(*TypeName).String", Method, 5}, {"(*TypeName).Type", Method, 5}, {"(*TypeParam).Constraint", Method, 18}, {"(*TypeParam).Index", Method, 18}, {"(*TypeParam).Obj", Method, 18}, {"(*TypeParam).SetConstraint", Method, 18}, {"(*TypeParam).String", Method, 18}, {"(*TypeParam).Underlying", Method, 18}, {"(*TypeParamList).At", Method, 18}, {"(*TypeParamList).Len", Method, 18}, {"(*TypeParamList).TypeParams", Method, 24}, {"(*Union).Len", Method, 18}, {"(*Union).String", Method, 18}, {"(*Union).Term", Method, 18}, {"(*Union).Terms", Method, 24}, {"(*Union).Underlying", Method, 18}, {"(*Var).Anonymous", Method, 5}, {"(*Var).Embedded", Method, 11}, {"(*Var).Exported", Method, 5}, {"(*Var).Id", Method, 5}, {"(*Var).IsField", Method, 5}, {"(*Var).Kind", Method, 25}, {"(*Var).Name", Method, 5}, {"(*Var).Origin", Method, 19}, {"(*Var).Parent", Method, 5}, {"(*Var).Pkg", Method, 5}, {"(*Var).Pos", Method, 5}, {"(*Var).SetKind", Method, 25}, {"(*Var).String", Method, 5}, {"(*Var).Type", Method, 5}, {"(Checker).ObjectOf", Method, 5}, {"(Checker).PkgNameOf", Method, 22}, {"(Checker).TypeOf", Method, 5}, {"(Error).Error", Method, 5}, {"(TypeAndValue).Addressable", Method, 5}, {"(TypeAndValue).Assignable", Method, 5}, {"(TypeAndValue).HasOk", Method, 5}, {"(TypeAndValue).IsBuiltin", Method, 5}, {"(TypeAndValue).IsNil", Method, 5}, {"(TypeAndValue).IsType", Method, 5}, {"(TypeAndValue).IsValue", Method, 5}, {"(TypeAndValue).IsVoid", Method, 5}, {"(VarKind).String", Method, 25}, {"Alias", Type, 22}, {"ArgumentError", Type, 18}, {"ArgumentError.Err", Field, 18}, {"ArgumentError.Index", Field, 18}, {"Array", Type, 5}, {"AssertableTo", Func, 5}, {"AssignableTo", Func, 5}, {"Basic", Type, 5}, {"BasicInfo", Type, 5}, {"BasicKind", Type, 5}, {"Bool", Const, 5}, {"Builtin", Type, 5}, {"Byte", Const, 5}, {"Chan", Type, 5}, {"ChanDir", Type, 5}, {"CheckExpr", Func, 13}, {"Checker", Type, 5}, {"Checker.Info", Field, 5}, {"Comparable", Func, 5}, {"Complex128", Const, 5}, {"Complex64", Const, 5}, {"Config", Type, 5}, {"Config.Context", Field, 18}, {"Config.DisableUnusedImportCheck", Field, 5}, {"Config.Error", Field, 5}, {"Config.FakeImportC", Field, 5}, {"Config.GoVersion", Field, 18}, {"Config.IgnoreFuncBodies", Field, 5}, {"Config.Importer", Field, 5}, {"Config.Sizes", Field, 5}, {"Const", Type, 5}, {"Context", Type, 18}, {"ConvertibleTo", Func, 5}, {"DefPredeclaredTestFuncs", Func, 5}, {"Default", Func, 8}, {"Error", Type, 5}, {"Error.Fset", Field, 5}, {"Error.Msg", Field, 5}, {"Error.Pos", Field, 5}, {"Error.Soft", Field, 5}, {"Eval", Func, 5}, {"ExprString", Func, 5}, {"FieldVal", Const, 5}, {"FieldVar", Const, 25}, {"Float32", Const, 5}, {"Float64", Const, 5}, {"Func", Type, 5}, {"Id", Func, 5}, {"Identical", Func, 5}, {"IdenticalIgnoreTags", Func, 8}, {"Implements", Func, 5}, {"ImportMode", Type, 6}, {"Importer", Type, 5}, {"ImporterFrom", Type, 6}, {"Info", Type, 5}, {"Info.Defs", Field, 5}, {"Info.FileVersions", Field, 22}, {"Info.Implicits", Field, 5}, {"Info.InitOrder", Field, 5}, {"Info.Instances", Field, 18}, {"Info.Scopes", Field, 5}, {"Info.Selections", Field, 5}, {"Info.Types", Field, 5}, {"Info.Uses", Field, 5}, {"Initializer", Type, 5}, {"Initializer.Lhs", Field, 5}, {"Initializer.Rhs", Field, 5}, {"Instance", Type, 18}, {"Instance.Type", Field, 18}, {"Instance.TypeArgs", Field, 18}, {"Instantiate", Func, 18}, {"Int", Const, 5}, {"Int16", Const, 5}, {"Int32", Const, 5}, {"Int64", Const, 5}, {"Int8", Const, 5}, {"Interface", Type, 5}, {"Invalid", Const, 5}, {"IsBoolean", Const, 5}, {"IsComplex", Const, 5}, {"IsConstType", Const, 5}, {"IsFloat", Const, 5}, {"IsInteger", Const, 5}, {"IsInterface", Func, 5}, {"IsNumeric", Const, 5}, {"IsOrdered", Const, 5}, {"IsString", Const, 5}, {"IsUnsigned", Const, 5}, {"IsUntyped", Const, 5}, {"Label", Type, 5}, {"LocalVar", Const, 25}, {"LookupFieldOrMethod", Func, 5}, {"LookupSelection", Func, 25}, {"Map", Type, 5}, {"MethodExpr", Const, 5}, {"MethodSet", Type, 5}, {"MethodVal", Const, 5}, {"MissingMethod", Func, 5}, {"Named", Type, 5}, {"NewAlias", Func, 22}, {"NewArray", Func, 5}, {"NewChan", Func, 5}, {"NewChecker", Func, 5}, {"NewConst", Func, 5}, {"NewContext", Func, 18}, {"NewField", Func, 5}, {"NewFunc", Func, 5}, {"NewInterface", Func, 5}, {"NewInterfaceType", Func, 11}, {"NewLabel", Func, 5}, {"NewMap", Func, 5}, {"NewMethodSet", Func, 5}, {"NewNamed", Func, 5}, {"NewPackage", Func, 5}, {"NewParam", Func, 5}, {"NewPkgName", Func, 5}, {"NewPointer", Func, 5}, {"NewScope", Func, 5}, {"NewSignature", Func, 5}, {"NewSignatureType", Func, 18}, {"NewSlice", Func, 5}, {"NewStruct", Func, 5}, {"NewTerm", Func, 18}, {"NewTuple", Func, 5}, {"NewTypeName", Func, 5}, {"NewTypeParam", Func, 18}, {"NewUnion", Func, 18}, {"NewVar", Func, 5}, {"Nil", Type, 5}, {"Object", Type, 5}, {"ObjectString", Func, 5}, {"Package", Type, 5}, {"PackageVar", Const, 25}, {"ParamVar", Const, 25}, {"PkgName", Type, 5}, {"Pointer", Type, 5}, {"Qualifier", Type, 5}, {"RecvOnly", Const, 5}, {"RecvVar", Const, 25}, {"RelativeTo", Func, 5}, {"ResultVar", Const, 25}, {"Rune", Const, 5}, {"Satisfies", Func, 20}, {"Scope", Type, 5}, {"Selection", Type, 5}, {"SelectionKind", Type, 5}, {"SelectionString", Func, 5}, {"SendOnly", Const, 5}, {"SendRecv", Const, 5}, {"Signature", Type, 5}, {"Sizes", Type, 5}, {"SizesFor", Func, 9}, {"Slice", Type, 5}, {"StdSizes", Type, 5}, {"StdSizes.MaxAlign", Field, 5}, {"StdSizes.WordSize", Field, 5}, {"String", Const, 5}, {"Struct", Type, 5}, {"Term", Type, 18}, {"Tuple", Type, 5}, {"Typ", Var, 5}, {"Type", Type, 5}, {"TypeAndValue", Type, 5}, {"TypeAndValue.Type", Field, 5}, {"TypeAndValue.Value", Field, 5}, {"TypeList", Type, 18}, {"TypeName", Type, 5}, {"TypeParam", Type, 18}, {"TypeParamList", Type, 18}, {"TypeString", Func, 5}, {"Uint", Const, 5}, {"Uint16", Const, 5}, {"Uint32", Const, 5}, {"Uint64", Const, 5}, {"Uint8", Const, 5}, {"Uintptr", Const, 5}, {"Unalias", Func, 22}, {"Union", Type, 18}, {"Universe", Var, 5}, {"Unsafe", Var, 5}, {"UnsafePointer", Const, 5}, {"UntypedBool", Const, 5}, {"UntypedComplex", Const, 5}, {"UntypedFloat", Const, 5}, {"UntypedInt", Const, 5}, {"UntypedNil", Const, 5}, {"UntypedRune", Const, 5}, {"UntypedString", Const, 5}, {"Var", Type, 5}, {"VarKind", Type, 25}, {"WriteExpr", Func, 5}, {"WriteSignature", Func, 5}, {"WriteType", Func, 5}, }, "go/version": { {"Compare", Func, 22}, {"IsValid", Func, 22}, {"Lang", Func, 22}, }, "hash": { {"Hash", Type, 0}, {"Hash32", Type, 0}, {"Hash64", Type, 0}, }, "hash/adler32": { {"Checksum", Func, 0}, {"New", Func, 0}, {"Size", Const, 0}, }, "hash/crc32": { {"Castagnoli", Const, 0}, {"Checksum", Func, 0}, {"ChecksumIEEE", Func, 0}, {"IEEE", Const, 0}, {"IEEETable", Var, 0}, {"Koopman", Const, 0}, {"MakeTable", Func, 0}, {"New", Func, 0}, {"NewIEEE", Func, 0}, {"Size", Const, 0}, {"Table", Type, 0}, {"Update", Func, 0}, }, "hash/crc64": { {"Checksum", Func, 0}, {"ECMA", Const, 0}, {"ISO", Const, 0}, {"MakeTable", Func, 0}, {"New", Func, 0}, {"Size", Const, 0}, {"Table", Type, 0}, {"Update", Func, 0}, }, "hash/fnv": { {"New128", Func, 9}, {"New128a", Func, 9}, {"New32", Func, 0}, {"New32a", Func, 0}, {"New64", Func, 0}, {"New64a", Func, 0}, }, "hash/maphash": { {"(*Hash).BlockSize", Method, 14}, {"(*Hash).Reset", Method, 14}, {"(*Hash).Seed", Method, 14}, {"(*Hash).SetSeed", Method, 14}, {"(*Hash).Size", Method, 14}, {"(*Hash).Sum", Method, 14}, {"(*Hash).Sum64", Method, 14}, {"(*Hash).Write", Method, 14}, {"(*Hash).WriteByte", Method, 14}, {"(*Hash).WriteString", Method, 14}, {"Bytes", Func, 19}, {"Comparable", Func, 24}, {"Hash", Type, 14}, {"MakeSeed", Func, 14}, {"Seed", Type, 14}, {"String", Func, 19}, {"WriteComparable", Func, 24}, }, "html": { {"EscapeString", Func, 0}, {"UnescapeString", Func, 0}, }, "html/template": { {"(*Error).Error", Method, 0}, {"(*Template).AddParseTree", Method, 0}, {"(*Template).Clone", Method, 0}, {"(*Template).DefinedTemplates", Method, 6}, {"(*Template).Delims", Method, 0}, {"(*Template).Execute", Method, 0}, {"(*Template).ExecuteTemplate", Method, 0}, {"(*Template).Funcs", Method, 0}, {"(*Template).Lookup", Method, 0}, {"(*Template).Name", Method, 0}, {"(*Template).New", Method, 0}, {"(*Template).Option", Method, 5}, {"(*Template).Parse", Method, 0}, {"(*Template).ParseFS", Method, 16}, {"(*Template).ParseFiles", Method, 0}, {"(*Template).ParseGlob", Method, 0}, {"(*Template).Templates", Method, 0}, {"CSS", Type, 0}, {"ErrAmbigContext", Const, 0}, {"ErrBadHTML", Const, 0}, {"ErrBranchEnd", Const, 0}, {"ErrEndContext", Const, 0}, {"ErrJSTemplate", Const, 21}, {"ErrNoSuchTemplate", Const, 0}, {"ErrOutputContext", Const, 0}, {"ErrPartialCharset", Const, 0}, {"ErrPartialEscape", Const, 0}, {"ErrPredefinedEscaper", Const, 9}, {"ErrRangeLoopReentry", Const, 0}, {"ErrSlashAmbig", Const, 0}, {"Error", Type, 0}, {"Error.Description", Field, 0}, {"Error.ErrorCode", Field, 0}, {"Error.Line", Field, 0}, {"Error.Name", Field, 0}, {"Error.Node", Field, 4}, {"ErrorCode", Type, 0}, {"FuncMap", Type, 0}, {"HTML", Type, 0}, {"HTMLAttr", Type, 0}, {"HTMLEscape", Func, 0}, {"HTMLEscapeString", Func, 0}, {"HTMLEscaper", Func, 0}, {"IsTrue", Func, 6}, {"JS", Type, 0}, {"JSEscape", Func, 0}, {"JSEscapeString", Func, 0}, {"JSEscaper", Func, 0}, {"JSStr", Type, 0}, {"Must", Func, 0}, {"New", Func, 0}, {"OK", Const, 0}, {"ParseFS", Func, 16}, {"ParseFiles", Func, 0}, {"ParseGlob", Func, 0}, {"Srcset", Type, 10}, {"Template", Type, 0}, {"Template.Tree", Field, 2}, {"URL", Type, 0}, {"URLQueryEscaper", Func, 0}, }, "image": { {"(*Alpha).AlphaAt", Method, 4}, {"(*Alpha).At", Method, 0}, {"(*Alpha).Bounds", Method, 0}, {"(*Alpha).ColorModel", Method, 0}, {"(*Alpha).Opaque", Method, 0}, {"(*Alpha).PixOffset", Method, 0}, {"(*Alpha).RGBA64At", Method, 17}, {"(*Alpha).Set", Method, 0}, {"(*Alpha).SetAlpha", Method, 0}, {"(*Alpha).SetRGBA64", Method, 17}, {"(*Alpha).SubImage", Method, 0}, {"(*Alpha16).Alpha16At", Method, 4}, {"(*Alpha16).At", Method, 0}, {"(*Alpha16).Bounds", Method, 0}, {"(*Alpha16).ColorModel", Method, 0}, {"(*Alpha16).Opaque", Method, 0}, {"(*Alpha16).PixOffset", Method, 0}, {"(*Alpha16).RGBA64At", Method, 17}, {"(*Alpha16).Set", Method, 0}, {"(*Alpha16).SetAlpha16", Method, 0}, {"(*Alpha16).SetRGBA64", Method, 17}, {"(*Alpha16).SubImage", Method, 0}, {"(*CMYK).At", Method, 5}, {"(*CMYK).Bounds", Method, 5}, {"(*CMYK).CMYKAt", Method, 5}, {"(*CMYK).ColorModel", Method, 5}, {"(*CMYK).Opaque", Method, 5}, {"(*CMYK).PixOffset", Method, 5}, {"(*CMYK).RGBA64At", Method, 17}, {"(*CMYK).Set", Method, 5}, {"(*CMYK).SetCMYK", Method, 5}, {"(*CMYK).SetRGBA64", Method, 17}, {"(*CMYK).SubImage", Method, 5}, {"(*Gray).At", Method, 0}, {"(*Gray).Bounds", Method, 0}, {"(*Gray).ColorModel", Method, 0}, {"(*Gray).GrayAt", Method, 4}, {"(*Gray).Opaque", Method, 0}, {"(*Gray).PixOffset", Method, 0}, {"(*Gray).RGBA64At", Method, 17}, {"(*Gray).Set", Method, 0}, {"(*Gray).SetGray", Method, 0}, {"(*Gray).SetRGBA64", Method, 17}, {"(*Gray).SubImage", Method, 0}, {"(*Gray16).At", Method, 0}, {"(*Gray16).Bounds", Method, 0}, {"(*Gray16).ColorModel", Method, 0}, {"(*Gray16).Gray16At", Method, 4}, {"(*Gray16).Opaque", Method, 0}, {"(*Gray16).PixOffset", Method, 0}, {"(*Gray16).RGBA64At", Method, 17}, {"(*Gray16).Set", Method, 0}, {"(*Gray16).SetGray16", Method, 0}, {"(*Gray16).SetRGBA64", Method, 17}, {"(*Gray16).SubImage", Method, 0}, {"(*NRGBA).At", Method, 0}, {"(*NRGBA).Bounds", Method, 0}, {"(*NRGBA).ColorModel", Method, 0}, {"(*NRGBA).NRGBAAt", Method, 4}, {"(*NRGBA).Opaque", Method, 0}, {"(*NRGBA).PixOffset", Method, 0}, {"(*NRGBA).RGBA64At", Method, 17}, {"(*NRGBA).Set", Method, 0}, {"(*NRGBA).SetNRGBA", Method, 0}, {"(*NRGBA).SetRGBA64", Method, 17}, {"(*NRGBA).SubImage", Method, 0}, {"(*NRGBA64).At", Method, 0}, {"(*NRGBA64).Bounds", Method, 0}, {"(*NRGBA64).ColorModel", Method, 0}, {"(*NRGBA64).NRGBA64At", Method, 4}, {"(*NRGBA64).Opaque", Method, 0}, {"(*NRGBA64).PixOffset", Method, 0}, {"(*NRGBA64).RGBA64At", Method, 17}, {"(*NRGBA64).Set", Method, 0}, {"(*NRGBA64).SetNRGBA64", Method, 0}, {"(*NRGBA64).SetRGBA64", Method, 17}, {"(*NRGBA64).SubImage", Method, 0}, {"(*NYCbCrA).AOffset", Method, 6}, {"(*NYCbCrA).At", Method, 6}, {"(*NYCbCrA).Bounds", Method, 6}, {"(*NYCbCrA).COffset", Method, 6}, {"(*NYCbCrA).ColorModel", Method, 6}, {"(*NYCbCrA).NYCbCrAAt", Method, 6}, {"(*NYCbCrA).Opaque", Method, 6}, {"(*NYCbCrA).RGBA64At", Method, 17}, {"(*NYCbCrA).SubImage", Method, 6}, {"(*NYCbCrA).YCbCrAt", Method, 6}, {"(*NYCbCrA).YOffset", Method, 6}, {"(*Paletted).At", Method, 0}, {"(*Paletted).Bounds", Method, 0}, {"(*Paletted).ColorIndexAt", Method, 0}, {"(*Paletted).ColorModel", Method, 0}, {"(*Paletted).Opaque", Method, 0}, {"(*Paletted).PixOffset", Method, 0}, {"(*Paletted).RGBA64At", Method, 17}, {"(*Paletted).Set", Method, 0}, {"(*Paletted).SetColorIndex", Method, 0}, {"(*Paletted).SetRGBA64", Method, 17}, {"(*Paletted).SubImage", Method, 0}, {"(*RGBA).At", Method, 0}, {"(*RGBA).Bounds", Method, 0}, {"(*RGBA).ColorModel", Method, 0}, {"(*RGBA).Opaque", Method, 0}, {"(*RGBA).PixOffset", Method, 0}, {"(*RGBA).RGBA64At", Method, 17}, {"(*RGBA).RGBAAt", Method, 4}, {"(*RGBA).Set", Method, 0}, {"(*RGBA).SetRGBA", Method, 0}, {"(*RGBA).SetRGBA64", Method, 17}, {"(*RGBA).SubImage", Method, 0}, {"(*RGBA64).At", Method, 0}, {"(*RGBA64).Bounds", Method, 0}, {"(*RGBA64).ColorModel", Method, 0}, {"(*RGBA64).Opaque", Method, 0}, {"(*RGBA64).PixOffset", Method, 0}, {"(*RGBA64).RGBA64At", Method, 4}, {"(*RGBA64).Set", Method, 0}, {"(*RGBA64).SetRGBA64", Method, 0}, {"(*RGBA64).SubImage", Method, 0}, {"(*Uniform).At", Method, 0}, {"(*Uniform).Bounds", Method, 0}, {"(*Uniform).ColorModel", Method, 0}, {"(*Uniform).Convert", Method, 0}, {"(*Uniform).Opaque", Method, 0}, {"(*Uniform).RGBA", Method, 0}, {"(*Uniform).RGBA64At", Method, 17}, {"(*YCbCr).At", Method, 0}, {"(*YCbCr).Bounds", Method, 0}, {"(*YCbCr).COffset", Method, 0}, {"(*YCbCr).ColorModel", Method, 0}, {"(*YCbCr).Opaque", Method, 0}, {"(*YCbCr).RGBA64At", Method, 17}, {"(*YCbCr).SubImage", Method, 0}, {"(*YCbCr).YCbCrAt", Method, 4}, {"(*YCbCr).YOffset", Method, 0}, {"(Point).Add", Method, 0}, {"(Point).Div", Method, 0}, {"(Point).Eq", Method, 0}, {"(Point).In", Method, 0}, {"(Point).Mod", Method, 0}, {"(Point).Mul", Method, 0}, {"(Point).String", Method, 0}, {"(Point).Sub", Method, 0}, {"(Rectangle).Add", Method, 0}, {"(Rectangle).At", Method, 5}, {"(Rectangle).Bounds", Method, 5}, {"(Rectangle).Canon", Method, 0}, {"(Rectangle).ColorModel", Method, 5}, {"(Rectangle).Dx", Method, 0}, {"(Rectangle).Dy", Method, 0}, {"(Rectangle).Empty", Method, 0}, {"(Rectangle).Eq", Method, 0}, {"(Rectangle).In", Method, 0}, {"(Rectangle).Inset", Method, 0}, {"(Rectangle).Intersect", Method, 0}, {"(Rectangle).Overlaps", Method, 0}, {"(Rectangle).RGBA64At", Method, 17}, {"(Rectangle).Size", Method, 0}, {"(Rectangle).String", Method, 0}, {"(Rectangle).Sub", Method, 0}, {"(Rectangle).Union", Method, 0}, {"(YCbCrSubsampleRatio).String", Method, 0}, {"Alpha", Type, 0}, {"Alpha.Pix", Field, 0}, {"Alpha.Rect", Field, 0}, {"Alpha.Stride", Field, 0}, {"Alpha16", Type, 0}, {"Alpha16.Pix", Field, 0}, {"Alpha16.Rect", Field, 0}, {"Alpha16.Stride", Field, 0}, {"Black", Var, 0}, {"CMYK", Type, 5}, {"CMYK.Pix", Field, 5}, {"CMYK.Rect", Field, 5}, {"CMYK.Stride", Field, 5}, {"Config", Type, 0}, {"Config.ColorModel", Field, 0}, {"Config.Height", Field, 0}, {"Config.Width", Field, 0}, {"Decode", Func, 0}, {"DecodeConfig", Func, 0}, {"ErrFormat", Var, 0}, {"Gray", Type, 0}, {"Gray.Pix", Field, 0}, {"Gray.Rect", Field, 0}, {"Gray.Stride", Field, 0}, {"Gray16", Type, 0}, {"Gray16.Pix", Field, 0}, {"Gray16.Rect", Field, 0}, {"Gray16.Stride", Field, 0}, {"Image", Type, 0}, {"NRGBA", Type, 0}, {"NRGBA.Pix", Field, 0}, {"NRGBA.Rect", Field, 0}, {"NRGBA.Stride", Field, 0}, {"NRGBA64", Type, 0}, {"NRGBA64.Pix", Field, 0}, {"NRGBA64.Rect", Field, 0}, {"NRGBA64.Stride", Field, 0}, {"NYCbCrA", Type, 6}, {"NYCbCrA.A", Field, 6}, {"NYCbCrA.AStride", Field, 6}, {"NYCbCrA.YCbCr", Field, 6}, {"NewAlpha", Func, 0}, {"NewAlpha16", Func, 0}, {"NewCMYK", Func, 5}, {"NewGray", Func, 0}, {"NewGray16", Func, 0}, {"NewNRGBA", Func, 0}, {"NewNRGBA64", Func, 0}, {"NewNYCbCrA", Func, 6}, {"NewPaletted", Func, 0}, {"NewRGBA", Func, 0}, {"NewRGBA64", Func, 0}, {"NewUniform", Func, 0}, {"NewYCbCr", Func, 0}, {"Opaque", Var, 0}, {"Paletted", Type, 0}, {"Paletted.Palette", Field, 0}, {"Paletted.Pix", Field, 0}, {"Paletted.Rect", Field, 0}, {"Paletted.Stride", Field, 0}, {"PalettedImage", Type, 0}, {"Point", Type, 0}, {"Point.X", Field, 0}, {"Point.Y", Field, 0}, {"Pt", Func, 0}, {"RGBA", Type, 0}, {"RGBA.Pix", Field, 0}, {"RGBA.Rect", Field, 0}, {"RGBA.Stride", Field, 0}, {"RGBA64", Type, 0}, {"RGBA64.Pix", Field, 0}, {"RGBA64.Rect", Field, 0}, {"RGBA64.Stride", Field, 0}, {"RGBA64Image", Type, 17}, {"Rect", Func, 0}, {"Rectangle", Type, 0}, {"Rectangle.Max", Field, 0}, {"Rectangle.Min", Field, 0}, {"RegisterFormat", Func, 0}, {"Transparent", Var, 0}, {"Uniform", Type, 0}, {"Uniform.C", Field, 0}, {"White", Var, 0}, {"YCbCr", Type, 0}, {"YCbCr.CStride", Field, 0}, {"YCbCr.Cb", Field, 0}, {"YCbCr.Cr", Field, 0}, {"YCbCr.Rect", Field, 0}, {"YCbCr.SubsampleRatio", Field, 0}, {"YCbCr.Y", Field, 0}, {"YCbCr.YStride", Field, 0}, {"YCbCrSubsampleRatio", Type, 0}, {"YCbCrSubsampleRatio410", Const, 5}, {"YCbCrSubsampleRatio411", Const, 5}, {"YCbCrSubsampleRatio420", Const, 0}, {"YCbCrSubsampleRatio422", Const, 0}, {"YCbCrSubsampleRatio440", Const, 1}, {"YCbCrSubsampleRatio444", Const, 0}, {"ZP", Var, 0}, {"ZR", Var, 0}, }, "image/color": { {"(Alpha).RGBA", Method, 0}, {"(Alpha16).RGBA", Method, 0}, {"(CMYK).RGBA", Method, 5}, {"(Gray).RGBA", Method, 0}, {"(Gray16).RGBA", Method, 0}, {"(NRGBA).RGBA", Method, 0}, {"(NRGBA64).RGBA", Method, 0}, {"(NYCbCrA).RGBA", Method, 6}, {"(Palette).Convert", Method, 0}, {"(Palette).Index", Method, 0}, {"(RGBA).RGBA", Method, 0}, {"(RGBA64).RGBA", Method, 0}, {"(YCbCr).RGBA", Method, 0}, {"Alpha", Type, 0}, {"Alpha.A", Field, 0}, {"Alpha16", Type, 0}, {"Alpha16.A", Field, 0}, {"Alpha16Model", Var, 0}, {"AlphaModel", Var, 0}, {"Black", Var, 0}, {"CMYK", Type, 5}, {"CMYK.C", Field, 5}, {"CMYK.K", Field, 5}, {"CMYK.M", Field, 5}, {"CMYK.Y", Field, 5}, {"CMYKModel", Var, 5}, {"CMYKToRGB", Func, 5}, {"Color", Type, 0}, {"Gray", Type, 0}, {"Gray.Y", Field, 0}, {"Gray16", Type, 0}, {"Gray16.Y", Field, 0}, {"Gray16Model", Var, 0}, {"GrayModel", Var, 0}, {"Model", Type, 0}, {"ModelFunc", Func, 0}, {"NRGBA", Type, 0}, {"NRGBA.A", Field, 0}, {"NRGBA.B", Field, 0}, {"NRGBA.G", Field, 0}, {"NRGBA.R", Field, 0}, {"NRGBA64", Type, 0}, {"NRGBA64.A", Field, 0}, {"NRGBA64.B", Field, 0}, {"NRGBA64.G", Field, 0}, {"NRGBA64.R", Field, 0}, {"NRGBA64Model", Var, 0}, {"NRGBAModel", Var, 0}, {"NYCbCrA", Type, 6}, {"NYCbCrA.A", Field, 6}, {"NYCbCrA.YCbCr", Field, 6}, {"NYCbCrAModel", Var, 6}, {"Opaque", Var, 0}, {"Palette", Type, 0}, {"RGBA", Type, 0}, {"RGBA.A", Field, 0}, {"RGBA.B", Field, 0}, {"RGBA.G", Field, 0}, {"RGBA.R", Field, 0}, {"RGBA64", Type, 0}, {"RGBA64.A", Field, 0}, {"RGBA64.B", Field, 0}, {"RGBA64.G", Field, 0}, {"RGBA64.R", Field, 0}, {"RGBA64Model", Var, 0}, {"RGBAModel", Var, 0}, {"RGBToCMYK", Func, 5}, {"RGBToYCbCr", Func, 0}, {"Transparent", Var, 0}, {"White", Var, 0}, {"YCbCr", Type, 0}, {"YCbCr.Cb", Field, 0}, {"YCbCr.Cr", Field, 0}, {"YCbCr.Y", Field, 0}, {"YCbCrModel", Var, 0}, {"YCbCrToRGB", Func, 0}, }, "image/color/palette": { {"Plan9", Var, 2}, {"WebSafe", Var, 2}, }, "image/draw": { {"(Op).Draw", Method, 2}, {"Draw", Func, 0}, {"DrawMask", Func, 0}, {"Drawer", Type, 2}, {"FloydSteinberg", Var, 2}, {"Image", Type, 0}, {"Op", Type, 0}, {"Over", Const, 0}, {"Quantizer", Type, 2}, {"RGBA64Image", Type, 17}, {"Src", Const, 0}, }, "image/gif": { {"Decode", Func, 0}, {"DecodeAll", Func, 0}, {"DecodeConfig", Func, 0}, {"DisposalBackground", Const, 5}, {"DisposalNone", Const, 5}, {"DisposalPrevious", Const, 5}, {"Encode", Func, 2}, {"EncodeAll", Func, 2}, {"GIF", Type, 0}, {"GIF.BackgroundIndex", Field, 5}, {"GIF.Config", Field, 5}, {"GIF.Delay", Field, 0}, {"GIF.Disposal", Field, 5}, {"GIF.Image", Field, 0}, {"GIF.LoopCount", Field, 0}, {"Options", Type, 2}, {"Options.Drawer", Field, 2}, {"Options.NumColors", Field, 2}, {"Options.Quantizer", Field, 2}, }, "image/jpeg": { {"(FormatError).Error", Method, 0}, {"(UnsupportedError).Error", Method, 0}, {"Decode", Func, 0}, {"DecodeConfig", Func, 0}, {"DefaultQuality", Const, 0}, {"Encode", Func, 0}, {"FormatError", Type, 0}, {"Options", Type, 0}, {"Options.Quality", Field, 0}, {"Reader", Type, 0}, {"UnsupportedError", Type, 0}, }, "image/png": { {"(*Encoder).Encode", Method, 4}, {"(FormatError).Error", Method, 0}, {"(UnsupportedError).Error", Method, 0}, {"BestCompression", Const, 4}, {"BestSpeed", Const, 4}, {"CompressionLevel", Type, 4}, {"Decode", Func, 0}, {"DecodeConfig", Func, 0}, {"DefaultCompression", Const, 4}, {"Encode", Func, 0}, {"Encoder", Type, 4}, {"Encoder.BufferPool", Field, 9}, {"Encoder.CompressionLevel", Field, 4}, {"EncoderBuffer", Type, 9}, {"EncoderBufferPool", Type, 9}, {"FormatError", Type, 0}, {"NoCompression", Const, 4}, {"UnsupportedError", Type, 0}, }, "index/suffixarray": { {"(*Index).Bytes", Method, 0}, {"(*Index).FindAllIndex", Method, 0}, {"(*Index).Lookup", Method, 0}, {"(*Index).Read", Method, 0}, {"(*Index).Write", Method, 0}, {"Index", Type, 0}, {"New", Func, 0}, }, "io": { {"(*LimitedReader).Read", Method, 0}, {"(*OffsetWriter).Seek", Method, 20}, {"(*OffsetWriter).Write", Method, 20}, {"(*OffsetWriter).WriteAt", Method, 20}, {"(*PipeReader).Close", Method, 0}, {"(*PipeReader).CloseWithError", Method, 0}, {"(*PipeReader).Read", Method, 0}, {"(*PipeWriter).Close", Method, 0}, {"(*PipeWriter).CloseWithError", Method, 0}, {"(*PipeWriter).Write", Method, 0}, {"(*SectionReader).Outer", Method, 22}, {"(*SectionReader).Read", Method, 0}, {"(*SectionReader).ReadAt", Method, 0}, {"(*SectionReader).Seek", Method, 0}, {"(*SectionReader).Size", Method, 0}, {"ByteReader", Type, 0}, {"ByteScanner", Type, 0}, {"ByteWriter", Type, 1}, {"Closer", Type, 0}, {"Copy", Func, 0}, {"CopyBuffer", Func, 5}, {"CopyN", Func, 0}, {"Discard", Var, 16}, {"EOF", Var, 0}, {"ErrClosedPipe", Var, 0}, {"ErrNoProgress", Var, 1}, {"ErrShortBuffer", Var, 0}, {"ErrShortWrite", Var, 0}, {"ErrUnexpectedEOF", Var, 0}, {"LimitReader", Func, 0}, {"LimitedReader", Type, 0}, {"LimitedReader.N", Field, 0}, {"LimitedReader.R", Field, 0}, {"MultiReader", Func, 0}, {"MultiWriter", Func, 0}, {"NewOffsetWriter", Func, 20}, {"NewSectionReader", Func, 0}, {"NopCloser", Func, 16}, {"OffsetWriter", Type, 20}, {"Pipe", Func, 0}, {"PipeReader", Type, 0}, {"PipeWriter", Type, 0}, {"ReadAll", Func, 16}, {"ReadAtLeast", Func, 0}, {"ReadCloser", Type, 0}, {"ReadFull", Func, 0}, {"ReadSeekCloser", Type, 16}, {"ReadSeeker", Type, 0}, {"ReadWriteCloser", Type, 0}, {"ReadWriteSeeker", Type, 0}, {"ReadWriter", Type, 0}, {"Reader", Type, 0}, {"ReaderAt", Type, 0}, {"ReaderFrom", Type, 0}, {"RuneReader", Type, 0}, {"RuneScanner", Type, 0}, {"SectionReader", Type, 0}, {"SeekCurrent", Const, 7}, {"SeekEnd", Const, 7}, {"SeekStart", Const, 7}, {"Seeker", Type, 0}, {"StringWriter", Type, 12}, {"TeeReader", Func, 0}, {"WriteCloser", Type, 0}, {"WriteSeeker", Type, 0}, {"WriteString", Func, 0}, {"Writer", Type, 0}, {"WriterAt", Type, 0}, {"WriterTo", Type, 0}, }, "io/fs": { {"(*PathError).Error", Method, 16}, {"(*PathError).Timeout", Method, 16}, {"(*PathError).Unwrap", Method, 16}, {"(FileMode).IsDir", Method, 16}, {"(FileMode).IsRegular", Method, 16}, {"(FileMode).Perm", Method, 16}, {"(FileMode).String", Method, 16}, {"(FileMode).Type", Method, 16}, {"DirEntry", Type, 16}, {"ErrClosed", Var, 16}, {"ErrExist", Var, 16}, {"ErrInvalid", Var, 16}, {"ErrNotExist", Var, 16}, {"ErrPermission", Var, 16}, {"FS", Type, 16}, {"File", Type, 16}, {"FileInfo", Type, 16}, {"FileInfoToDirEntry", Func, 17}, {"FileMode", Type, 16}, {"FormatDirEntry", Func, 21}, {"FormatFileInfo", Func, 21}, {"Glob", Func, 16}, {"GlobFS", Type, 16}, {"Lstat", Func, 25}, {"ModeAppend", Const, 16}, {"ModeCharDevice", Const, 16}, {"ModeDevice", Const, 16}, {"ModeDir", Const, 16}, {"ModeExclusive", Const, 16}, {"ModeIrregular", Const, 16}, {"ModeNamedPipe", Const, 16}, {"ModePerm", Const, 16}, {"ModeSetgid", Const, 16}, {"ModeSetuid", Const, 16}, {"ModeSocket", Const, 16}, {"ModeSticky", Const, 16}, {"ModeSymlink", Const, 16}, {"ModeTemporary", Const, 16}, {"ModeType", Const, 16}, {"PathError", Type, 16}, {"PathError.Err", Field, 16}, {"PathError.Op", Field, 16}, {"PathError.Path", Field, 16}, {"ReadDir", Func, 16}, {"ReadDirFS", Type, 16}, {"ReadDirFile", Type, 16}, {"ReadFile", Func, 16}, {"ReadFileFS", Type, 16}, {"ReadLink", Func, 25}, {"ReadLinkFS", Type, 25}, {"SkipAll", Var, 20}, {"SkipDir", Var, 16}, {"Stat", Func, 16}, {"StatFS", Type, 16}, {"Sub", Func, 16}, {"SubFS", Type, 16}, {"ValidPath", Func, 16}, {"WalkDir", Func, 16}, {"WalkDirFunc", Type, 16}, }, "io/ioutil": { {"Discard", Var, 0}, {"NopCloser", Func, 0}, {"ReadAll", Func, 0}, {"ReadDir", Func, 0}, {"ReadFile", Func, 0}, {"TempDir", Func, 0}, {"TempFile", Func, 0}, {"WriteFile", Func, 0}, }, "iter": { {"Pull", Func, 23}, {"Pull2", Func, 23}, {"Seq", Type, 23}, {"Seq2", Type, 23}, }, "log": { {"(*Logger).Fatal", Method, 0}, {"(*Logger).Fatalf", Method, 0}, {"(*Logger).Fatalln", Method, 0}, {"(*Logger).Flags", Method, 0}, {"(*Logger).Output", Method, 0}, {"(*Logger).Panic", Method, 0}, {"(*Logger).Panicf", Method, 0}, {"(*Logger).Panicln", Method, 0}, {"(*Logger).Prefix", Method, 0}, {"(*Logger).Print", Method, 0}, {"(*Logger).Printf", Method, 0}, {"(*Logger).Println", Method, 0}, {"(*Logger).SetFlags", Method, 0}, {"(*Logger).SetOutput", Method, 5}, {"(*Logger).SetPrefix", Method, 0}, {"(*Logger).Writer", Method, 12}, {"Default", Func, 16}, {"Fatal", Func, 0}, {"Fatalf", Func, 0}, {"Fatalln", Func, 0}, {"Flags", Func, 0}, {"LUTC", Const, 5}, {"Ldate", Const, 0}, {"Llongfile", Const, 0}, {"Lmicroseconds", Const, 0}, {"Lmsgprefix", Const, 14}, {"Logger", Type, 0}, {"Lshortfile", Const, 0}, {"LstdFlags", Const, 0}, {"Ltime", Const, 0}, {"New", Func, 0}, {"Output", Func, 5}, {"Panic", Func, 0}, {"Panicf", Func, 0}, {"Panicln", Func, 0}, {"Prefix", Func, 0}, {"Print", Func, 0}, {"Printf", Func, 0}, {"Println", Func, 0}, {"SetFlags", Func, 0}, {"SetOutput", Func, 0}, {"SetPrefix", Func, 0}, {"Writer", Func, 13}, }, "log/slog": { {"(*JSONHandler).Enabled", Method, 21}, {"(*JSONHandler).Handle", Method, 21}, {"(*JSONHandler).WithAttrs", Method, 21}, {"(*JSONHandler).WithGroup", Method, 21}, {"(*Level).UnmarshalJSON", Method, 21}, {"(*Level).UnmarshalText", Method, 21}, {"(*LevelVar).AppendText", Method, 24}, {"(*LevelVar).Level", Method, 21}, {"(*LevelVar).MarshalText", Method, 21}, {"(*LevelVar).Set", Method, 21}, {"(*LevelVar).String", Method, 21}, {"(*LevelVar).UnmarshalText", Method, 21}, {"(*Logger).Debug", Method, 21}, {"(*Logger).DebugContext", Method, 21}, {"(*Logger).Enabled", Method, 21}, {"(*Logger).Error", Method, 21}, {"(*Logger).ErrorContext", Method, 21}, {"(*Logger).Handler", Method, 21}, {"(*Logger).Info", Method, 21}, {"(*Logger).InfoContext", Method, 21}, {"(*Logger).Log", Method, 21}, {"(*Logger).LogAttrs", Method, 21}, {"(*Logger).Warn", Method, 21}, {"(*Logger).WarnContext", Method, 21}, {"(*Logger).With", Method, 21}, {"(*Logger).WithGroup", Method, 21}, {"(*Record).Add", Method, 21}, {"(*Record).AddAttrs", Method, 21}, {"(*TextHandler).Enabled", Method, 21}, {"(*TextHandler).Handle", Method, 21}, {"(*TextHandler).WithAttrs", Method, 21}, {"(*TextHandler).WithGroup", Method, 21}, {"(Attr).Equal", Method, 21}, {"(Attr).String", Method, 21}, {"(Kind).String", Method, 21}, {"(Level).AppendText", Method, 24}, {"(Level).Level", Method, 21}, {"(Level).MarshalJSON", Method, 21}, {"(Level).MarshalText", Method, 21}, {"(Level).String", Method, 21}, {"(Record).Attrs", Method, 21}, {"(Record).Clone", Method, 21}, {"(Record).NumAttrs", Method, 21}, {"(Value).Any", Method, 21}, {"(Value).Bool", Method, 21}, {"(Value).Duration", Method, 21}, {"(Value).Equal", Method, 21}, {"(Value).Float64", Method, 21}, {"(Value).Group", Method, 21}, {"(Value).Int64", Method, 21}, {"(Value).Kind", Method, 21}, {"(Value).LogValuer", Method, 21}, {"(Value).Resolve", Method, 21}, {"(Value).String", Method, 21}, {"(Value).Time", Method, 21}, {"(Value).Uint64", Method, 21}, {"Any", Func, 21}, {"AnyValue", Func, 21}, {"Attr", Type, 21}, {"Attr.Key", Field, 21}, {"Attr.Value", Field, 21}, {"Bool", Func, 21}, {"BoolValue", Func, 21}, {"Debug", Func, 21}, {"DebugContext", Func, 21}, {"Default", Func, 21}, {"DiscardHandler", Var, 24}, {"Duration", Func, 21}, {"DurationValue", Func, 21}, {"Error", Func, 21}, {"ErrorContext", Func, 21}, {"Float64", Func, 21}, {"Float64Value", Func, 21}, {"Group", Func, 21}, {"GroupValue", Func, 21}, {"Handler", Type, 21}, {"HandlerOptions", Type, 21}, {"HandlerOptions.AddSource", Field, 21}, {"HandlerOptions.Level", Field, 21}, {"HandlerOptions.ReplaceAttr", Field, 21}, {"Info", Func, 21}, {"InfoContext", Func, 21}, {"Int", Func, 21}, {"Int64", Func, 21}, {"Int64Value", Func, 21}, {"IntValue", Func, 21}, {"JSONHandler", Type, 21}, {"Kind", Type, 21}, {"KindAny", Const, 21}, {"KindBool", Const, 21}, {"KindDuration", Const, 21}, {"KindFloat64", Const, 21}, {"KindGroup", Const, 21}, {"KindInt64", Const, 21}, {"KindLogValuer", Const, 21}, {"KindString", Const, 21}, {"KindTime", Const, 21}, {"KindUint64", Const, 21}, {"Level", Type, 21}, {"LevelDebug", Const, 21}, {"LevelError", Const, 21}, {"LevelInfo", Const, 21}, {"LevelKey", Const, 21}, {"LevelVar", Type, 21}, {"LevelWarn", Const, 21}, {"Leveler", Type, 21}, {"Log", Func, 21}, {"LogAttrs", Func, 21}, {"LogValuer", Type, 21}, {"Logger", Type, 21}, {"MessageKey", Const, 21}, {"New", Func, 21}, {"NewJSONHandler", Func, 21}, {"NewLogLogger", Func, 21}, {"NewRecord", Func, 21}, {"NewTextHandler", Func, 21}, {"Record", Type, 21}, {"Record.Level", Field, 21}, {"Record.Message", Field, 21}, {"Record.PC", Field, 21}, {"Record.Time", Field, 21}, {"SetDefault", Func, 21}, {"SetLogLoggerLevel", Func, 22}, {"Source", Type, 21}, {"Source.File", Field, 21}, {"Source.Function", Field, 21}, {"Source.Line", Field, 21}, {"SourceKey", Const, 21}, {"String", Func, 21}, {"StringValue", Func, 21}, {"TextHandler", Type, 21}, {"Time", Func, 21}, {"TimeKey", Const, 21}, {"TimeValue", Func, 21}, {"Uint64", Func, 21}, {"Uint64Value", Func, 21}, {"Value", Type, 21}, {"Warn", Func, 21}, {"WarnContext", Func, 21}, {"With", Func, 21}, }, "log/syslog": { {"(*Writer).Alert", Method, 0}, {"(*Writer).Close", Method, 0}, {"(*Writer).Crit", Method, 0}, {"(*Writer).Debug", Method, 0}, {"(*Writer).Emerg", Method, 0}, {"(*Writer).Err", Method, 0}, {"(*Writer).Info", Method, 0}, {"(*Writer).Notice", Method, 0}, {"(*Writer).Warning", Method, 0}, {"(*Writer).Write", Method, 0}, {"Dial", Func, 0}, {"LOG_ALERT", Const, 0}, {"LOG_AUTH", Const, 1}, {"LOG_AUTHPRIV", Const, 1}, {"LOG_CRIT", Const, 0}, {"LOG_CRON", Const, 1}, {"LOG_DAEMON", Const, 1}, {"LOG_DEBUG", Const, 0}, {"LOG_EMERG", Const, 0}, {"LOG_ERR", Const, 0}, {"LOG_FTP", Const, 1}, {"LOG_INFO", Const, 0}, {"LOG_KERN", Const, 1}, {"LOG_LOCAL0", Const, 1}, {"LOG_LOCAL1", Const, 1}, {"LOG_LOCAL2", Const, 1}, {"LOG_LOCAL3", Const, 1}, {"LOG_LOCAL4", Const, 1}, {"LOG_LOCAL5", Const, 1}, {"LOG_LOCAL6", Const, 1}, {"LOG_LOCAL7", Const, 1}, {"LOG_LPR", Const, 1}, {"LOG_MAIL", Const, 1}, {"LOG_NEWS", Const, 1}, {"LOG_NOTICE", Const, 0}, {"LOG_SYSLOG", Const, 1}, {"LOG_USER", Const, 1}, {"LOG_UUCP", Const, 1}, {"LOG_WARNING", Const, 0}, {"New", Func, 0}, {"NewLogger", Func, 0}, {"Priority", Type, 0}, {"Writer", Type, 0}, }, "maps": { {"All", Func, 23}, {"Clone", Func, 21}, {"Collect", Func, 23}, {"Copy", Func, 21}, {"DeleteFunc", Func, 21}, {"Equal", Func, 21}, {"EqualFunc", Func, 21}, {"Insert", Func, 23}, {"Keys", Func, 23}, {"Values", Func, 23}, }, "math": { {"Abs", Func, 0}, {"Acos", Func, 0}, {"Acosh", Func, 0}, {"Asin", Func, 0}, {"Asinh", Func, 0}, {"Atan", Func, 0}, {"Atan2", Func, 0}, {"Atanh", Func, 0}, {"Cbrt", Func, 0}, {"Ceil", Func, 0}, {"Copysign", Func, 0}, {"Cos", Func, 0}, {"Cosh", Func, 0}, {"Dim", Func, 0}, {"E", Const, 0}, {"Erf", Func, 0}, {"Erfc", Func, 0}, {"Erfcinv", Func, 10}, {"Erfinv", Func, 10}, {"Exp", Func, 0}, {"Exp2", Func, 0}, {"Expm1", Func, 0}, {"FMA", Func, 14}, {"Float32bits", Func, 0}, {"Float32frombits", Func, 0}, {"Float64bits", Func, 0}, {"Float64frombits", Func, 0}, {"Floor", Func, 0}, {"Frexp", Func, 0}, {"Gamma", Func, 0}, {"Hypot", Func, 0}, {"Ilogb", Func, 0}, {"Inf", Func, 0}, {"IsInf", Func, 0}, {"IsNaN", Func, 0}, {"J0", Func, 0}, {"J1", Func, 0}, {"Jn", Func, 0}, {"Ldexp", Func, 0}, {"Lgamma", Func, 0}, {"Ln10", Const, 0}, {"Ln2", Const, 0}, {"Log", Func, 0}, {"Log10", Func, 0}, {"Log10E", Const, 0}, {"Log1p", Func, 0}, {"Log2", Func, 0}, {"Log2E", Const, 0}, {"Logb", Func, 0}, {"Max", Func, 0}, {"MaxFloat32", Const, 0}, {"MaxFloat64", Const, 0}, {"MaxInt", Const, 17}, {"MaxInt16", Const, 0}, {"MaxInt32", Const, 0}, {"MaxInt64", Const, 0}, {"MaxInt8", Const, 0}, {"MaxUint", Const, 17}, {"MaxUint16", Const, 0}, {"MaxUint32", Const, 0}, {"MaxUint64", Const, 0}, {"MaxUint8", Const, 0}, {"Min", Func, 0}, {"MinInt", Const, 17}, {"MinInt16", Const, 0}, {"MinInt32", Const, 0}, {"MinInt64", Const, 0}, {"MinInt8", Const, 0}, {"Mod", Func, 0}, {"Modf", Func, 0}, {"NaN", Func, 0}, {"Nextafter", Func, 0}, {"Nextafter32", Func, 4}, {"Phi", Const, 0}, {"Pi", Const, 0}, {"Pow", Func, 0}, {"Pow10", Func, 0}, {"Remainder", Func, 0}, {"Round", Func, 10}, {"RoundToEven", Func, 10}, {"Signbit", Func, 0}, {"Sin", Func, 0}, {"Sincos", Func, 0}, {"Sinh", Func, 0}, {"SmallestNonzeroFloat32", Const, 0}, {"SmallestNonzeroFloat64", Const, 0}, {"Sqrt", Func, 0}, {"Sqrt2", Const, 0}, {"SqrtE", Const, 0}, {"SqrtPhi", Const, 0}, {"SqrtPi", Const, 0}, {"Tan", Func, 0}, {"Tanh", Func, 0}, {"Trunc", Func, 0}, {"Y0", Func, 0}, {"Y1", Func, 0}, {"Yn", Func, 0}, }, "math/big": { {"(*Float).Abs", Method, 5}, {"(*Float).Acc", Method, 5}, {"(*Float).Add", Method, 5}, {"(*Float).Append", Method, 5}, {"(*Float).AppendText", Method, 24}, {"(*Float).Cmp", Method, 5}, {"(*Float).Copy", Method, 5}, {"(*Float).Float32", Method, 5}, {"(*Float).Float64", Method, 5}, {"(*Float).Format", Method, 5}, {"(*Float).GobDecode", Method, 7}, {"(*Float).GobEncode", Method, 7}, {"(*Float).Int", Method, 5}, {"(*Float).Int64", Method, 5}, {"(*Float).IsInf", Method, 5}, {"(*Float).IsInt", Method, 5}, {"(*Float).MantExp", Method, 5}, {"(*Float).MarshalText", Method, 6}, {"(*Float).MinPrec", Method, 5}, {"(*Float).Mode", Method, 5}, {"(*Float).Mul", Method, 5}, {"(*Float).Neg", Method, 5}, {"(*Float).Parse", Method, 5}, {"(*Float).Prec", Method, 5}, {"(*Float).Quo", Method, 5}, {"(*Float).Rat", Method, 5}, {"(*Float).Scan", Method, 8}, {"(*Float).Set", Method, 5}, {"(*Float).SetFloat64", Method, 5}, {"(*Float).SetInf", Method, 5}, {"(*Float).SetInt", Method, 5}, {"(*Float).SetInt64", Method, 5}, {"(*Float).SetMantExp", Method, 5}, {"(*Float).SetMode", Method, 5}, {"(*Float).SetPrec", Method, 5}, {"(*Float).SetRat", Method, 5}, {"(*Float).SetString", Method, 5}, {"(*Float).SetUint64", Method, 5}, {"(*Float).Sign", Method, 5}, {"(*Float).Signbit", Method, 5}, {"(*Float).Sqrt", Method, 10}, {"(*Float).String", Method, 5}, {"(*Float).Sub", Method, 5}, {"(*Float).Text", Method, 5}, {"(*Float).Uint64", Method, 5}, {"(*Float).UnmarshalText", Method, 6}, {"(*Int).Abs", Method, 0}, {"(*Int).Add", Method, 0}, {"(*Int).And", Method, 0}, {"(*Int).AndNot", Method, 0}, {"(*Int).Append", Method, 6}, {"(*Int).AppendText", Method, 24}, {"(*Int).Binomial", Method, 0}, {"(*Int).Bit", Method, 0}, {"(*Int).BitLen", Method, 0}, {"(*Int).Bits", Method, 0}, {"(*Int).Bytes", Method, 0}, {"(*Int).Cmp", Method, 0}, {"(*Int).CmpAbs", Method, 10}, {"(*Int).Div", Method, 0}, {"(*Int).DivMod", Method, 0}, {"(*Int).Exp", Method, 0}, {"(*Int).FillBytes", Method, 15}, {"(*Int).Float64", Method, 21}, {"(*Int).Format", Method, 0}, {"(*Int).GCD", Method, 0}, {"(*Int).GobDecode", Method, 0}, {"(*Int).GobEncode", Method, 0}, {"(*Int).Int64", Method, 0}, {"(*Int).IsInt64", Method, 9}, {"(*Int).IsUint64", Method, 9}, {"(*Int).Lsh", Method, 0}, {"(*Int).MarshalJSON", Method, 1}, {"(*Int).MarshalText", Method, 3}, {"(*Int).Mod", Method, 0}, {"(*Int).ModInverse", Method, 0}, {"(*Int).ModSqrt", Method, 5}, {"(*Int).Mul", Method, 0}, {"(*Int).MulRange", Method, 0}, {"(*Int).Neg", Method, 0}, {"(*Int).Not", Method, 0}, {"(*Int).Or", Method, 0}, {"(*Int).ProbablyPrime", Method, 0}, {"(*Int).Quo", Method, 0}, {"(*Int).QuoRem", Method, 0}, {"(*Int).Rand", Method, 0}, {"(*Int).Rem", Method, 0}, {"(*Int).Rsh", Method, 0}, {"(*Int).Scan", Method, 0}, {"(*Int).Set", Method, 0}, {"(*Int).SetBit", Method, 0}, {"(*Int).SetBits", Method, 0}, {"(*Int).SetBytes", Method, 0}, {"(*Int).SetInt64", Method, 0}, {"(*Int).SetString", Method, 0}, {"(*Int).SetUint64", Method, 1}, {"(*Int).Sign", Method, 0}, {"(*Int).Sqrt", Method, 8}, {"(*Int).String", Method, 0}, {"(*Int).Sub", Method, 0}, {"(*Int).Text", Method, 6}, {"(*Int).TrailingZeroBits", Method, 13}, {"(*Int).Uint64", Method, 1}, {"(*Int).UnmarshalJSON", Method, 1}, {"(*Int).UnmarshalText", Method, 3}, {"(*Int).Xor", Method, 0}, {"(*Rat).Abs", Method, 0}, {"(*Rat).Add", Method, 0}, {"(*Rat).AppendText", Method, 24}, {"(*Rat).Cmp", Method, 0}, {"(*Rat).Denom", Method, 0}, {"(*Rat).Float32", Method, 4}, {"(*Rat).Float64", Method, 1}, {"(*Rat).FloatPrec", Method, 22}, {"(*Rat).FloatString", Method, 0}, {"(*Rat).GobDecode", Method, 0}, {"(*Rat).GobEncode", Method, 0}, {"(*Rat).Inv", Method, 0}, {"(*Rat).IsInt", Method, 0}, {"(*Rat).MarshalText", Method, 3}, {"(*Rat).Mul", Method, 0}, {"(*Rat).Neg", Method, 0}, {"(*Rat).Num", Method, 0}, {"(*Rat).Quo", Method, 0}, {"(*Rat).RatString", Method, 0}, {"(*Rat).Scan", Method, 0}, {"(*Rat).Set", Method, 0}, {"(*Rat).SetFloat64", Method, 1}, {"(*Rat).SetFrac", Method, 0}, {"(*Rat).SetFrac64", Method, 0}, {"(*Rat).SetInt", Method, 0}, {"(*Rat).SetInt64", Method, 0}, {"(*Rat).SetString", Method, 0}, {"(*Rat).SetUint64", Method, 13}, {"(*Rat).Sign", Method, 0}, {"(*Rat).String", Method, 0}, {"(*Rat).Sub", Method, 0}, {"(*Rat).UnmarshalText", Method, 3}, {"(Accuracy).String", Method, 5}, {"(ErrNaN).Error", Method, 5}, {"(RoundingMode).String", Method, 5}, {"Above", Const, 5}, {"Accuracy", Type, 5}, {"AwayFromZero", Const, 5}, {"Below", Const, 5}, {"ErrNaN", Type, 5}, {"Exact", Const, 5}, {"Float", Type, 5}, {"Int", Type, 0}, {"Jacobi", Func, 5}, {"MaxBase", Const, 0}, {"MaxExp", Const, 5}, {"MaxPrec", Const, 5}, {"MinExp", Const, 5}, {"NewFloat", Func, 5}, {"NewInt", Func, 0}, {"NewRat", Func, 0}, {"ParseFloat", Func, 5}, {"Rat", Type, 0}, {"RoundingMode", Type, 5}, {"ToNearestAway", Const, 5}, {"ToNearestEven", Const, 5}, {"ToNegativeInf", Const, 5}, {"ToPositiveInf", Const, 5}, {"ToZero", Const, 5}, {"Word", Type, 0}, }, "math/bits": { {"Add", Func, 12}, {"Add32", Func, 12}, {"Add64", Func, 12}, {"Div", Func, 12}, {"Div32", Func, 12}, {"Div64", Func, 12}, {"LeadingZeros", Func, 9}, {"LeadingZeros16", Func, 9}, {"LeadingZeros32", Func, 9}, {"LeadingZeros64", Func, 9}, {"LeadingZeros8", Func, 9}, {"Len", Func, 9}, {"Len16", Func, 9}, {"Len32", Func, 9}, {"Len64", Func, 9}, {"Len8", Func, 9}, {"Mul", Func, 12}, {"Mul32", Func, 12}, {"Mul64", Func, 12}, {"OnesCount", Func, 9}, {"OnesCount16", Func, 9}, {"OnesCount32", Func, 9}, {"OnesCount64", Func, 9}, {"OnesCount8", Func, 9}, {"Rem", Func, 14}, {"Rem32", Func, 14}, {"Rem64", Func, 14}, {"Reverse", Func, 9}, {"Reverse16", Func, 9}, {"Reverse32", Func, 9}, {"Reverse64", Func, 9}, {"Reverse8", Func, 9}, {"ReverseBytes", Func, 9}, {"ReverseBytes16", Func, 9}, {"ReverseBytes32", Func, 9}, {"ReverseBytes64", Func, 9}, {"RotateLeft", Func, 9}, {"RotateLeft16", Func, 9}, {"RotateLeft32", Func, 9}, {"RotateLeft64", Func, 9}, {"RotateLeft8", Func, 9}, {"Sub", Func, 12}, {"Sub32", Func, 12}, {"Sub64", Func, 12}, {"TrailingZeros", Func, 9}, {"TrailingZeros16", Func, 9}, {"TrailingZeros32", Func, 9}, {"TrailingZeros64", Func, 9}, {"TrailingZeros8", Func, 9}, {"UintSize", Const, 9}, }, "math/cmplx": { {"Abs", Func, 0}, {"Acos", Func, 0}, {"Acosh", Func, 0}, {"Asin", Func, 0}, {"Asinh", Func, 0}, {"Atan", Func, 0}, {"Atanh", Func, 0}, {"Conj", Func, 0}, {"Cos", Func, 0}, {"Cosh", Func, 0}, {"Cot", Func, 0}, {"Exp", Func, 0}, {"Inf", Func, 0}, {"IsInf", Func, 0}, {"IsNaN", Func, 0}, {"Log", Func, 0}, {"Log10", Func, 0}, {"NaN", Func, 0}, {"Phase", Func, 0}, {"Polar", Func, 0}, {"Pow", Func, 0}, {"Rect", Func, 0}, {"Sin", Func, 0}, {"Sinh", Func, 0}, {"Sqrt", Func, 0}, {"Tan", Func, 0}, {"Tanh", Func, 0}, }, "math/rand": { {"(*Rand).ExpFloat64", Method, 0}, {"(*Rand).Float32", Method, 0}, {"(*Rand).Float64", Method, 0}, {"(*Rand).Int", Method, 0}, {"(*Rand).Int31", Method, 0}, {"(*Rand).Int31n", Method, 0}, {"(*Rand).Int63", Method, 0}, {"(*Rand).Int63n", Method, 0}, {"(*Rand).Intn", Method, 0}, {"(*Rand).NormFloat64", Method, 0}, {"(*Rand).Perm", Method, 0}, {"(*Rand).Read", Method, 6}, {"(*Rand).Seed", Method, 0}, {"(*Rand).Shuffle", Method, 10}, {"(*Rand).Uint32", Method, 0}, {"(*Rand).Uint64", Method, 8}, {"(*Zipf).Uint64", Method, 0}, {"ExpFloat64", Func, 0}, {"Float32", Func, 0}, {"Float64", Func, 0}, {"Int", Func, 0}, {"Int31", Func, 0}, {"Int31n", Func, 0}, {"Int63", Func, 0}, {"Int63n", Func, 0}, {"Intn", Func, 0}, {"New", Func, 0}, {"NewSource", Func, 0}, {"NewZipf", Func, 0}, {"NormFloat64", Func, 0}, {"Perm", Func, 0}, {"Rand", Type, 0}, {"Read", Func, 6}, {"Seed", Func, 0}, {"Shuffle", Func, 10}, {"Source", Type, 0}, {"Source64", Type, 8}, {"Uint32", Func, 0}, {"Uint64", Func, 8}, {"Zipf", Type, 0}, }, "math/rand/v2": { {"(*ChaCha8).AppendBinary", Method, 24}, {"(*ChaCha8).MarshalBinary", Method, 22}, {"(*ChaCha8).Read", Method, 23}, {"(*ChaCha8).Seed", Method, 22}, {"(*ChaCha8).Uint64", Method, 22}, {"(*ChaCha8).UnmarshalBinary", Method, 22}, {"(*PCG).AppendBinary", Method, 24}, {"(*PCG).MarshalBinary", Method, 22}, {"(*PCG).Seed", Method, 22}, {"(*PCG).Uint64", Method, 22}, {"(*PCG).UnmarshalBinary", Method, 22}, {"(*Rand).ExpFloat64", Method, 22}, {"(*Rand).Float32", Method, 22}, {"(*Rand).Float64", Method, 22}, {"(*Rand).Int", Method, 22}, {"(*Rand).Int32", Method, 22}, {"(*Rand).Int32N", Method, 22}, {"(*Rand).Int64", Method, 22}, {"(*Rand).Int64N", Method, 22}, {"(*Rand).IntN", Method, 22}, {"(*Rand).NormFloat64", Method, 22}, {"(*Rand).Perm", Method, 22}, {"(*Rand).Shuffle", Method, 22}, {"(*Rand).Uint", Method, 23}, {"(*Rand).Uint32", Method, 22}, {"(*Rand).Uint32N", Method, 22}, {"(*Rand).Uint64", Method, 22}, {"(*Rand).Uint64N", Method, 22}, {"(*Rand).UintN", Method, 22}, {"(*Zipf).Uint64", Method, 22}, {"ChaCha8", Type, 22}, {"ExpFloat64", Func, 22}, {"Float32", Func, 22}, {"Float64", Func, 22}, {"Int", Func, 22}, {"Int32", Func, 22}, {"Int32N", Func, 22}, {"Int64", Func, 22}, {"Int64N", Func, 22}, {"IntN", Func, 22}, {"N", Func, 22}, {"New", Func, 22}, {"NewChaCha8", Func, 22}, {"NewPCG", Func, 22}, {"NewZipf", Func, 22}, {"NormFloat64", Func, 22}, {"PCG", Type, 22}, {"Perm", Func, 22}, {"Rand", Type, 22}, {"Shuffle", Func, 22}, {"Source", Type, 22}, {"Uint", Func, 23}, {"Uint32", Func, 22}, {"Uint32N", Func, 22}, {"Uint64", Func, 22}, {"Uint64N", Func, 22}, {"UintN", Func, 22}, {"Zipf", Type, 22}, }, "mime": { {"(*WordDecoder).Decode", Method, 5}, {"(*WordDecoder).DecodeHeader", Method, 5}, {"(WordEncoder).Encode", Method, 5}, {"AddExtensionType", Func, 0}, {"BEncoding", Const, 5}, {"ErrInvalidMediaParameter", Var, 9}, {"ExtensionsByType", Func, 5}, {"FormatMediaType", Func, 0}, {"ParseMediaType", Func, 0}, {"QEncoding", Const, 5}, {"TypeByExtension", Func, 0}, {"WordDecoder", Type, 5}, {"WordDecoder.CharsetReader", Field, 5}, {"WordEncoder", Type, 5}, }, "mime/multipart": { {"(*FileHeader).Open", Method, 0}, {"(*Form).RemoveAll", Method, 0}, {"(*Part).Close", Method, 0}, {"(*Part).FileName", Method, 0}, {"(*Part).FormName", Method, 0}, {"(*Part).Read", Method, 0}, {"(*Reader).NextPart", Method, 0}, {"(*Reader).NextRawPart", Method, 14}, {"(*Reader).ReadForm", Method, 0}, {"(*Writer).Boundary", Method, 0}, {"(*Writer).Close", Method, 0}, {"(*Writer).CreateFormField", Method, 0}, {"(*Writer).CreateFormFile", Method, 0}, {"(*Writer).CreatePart", Method, 0}, {"(*Writer).FormDataContentType", Method, 0}, {"(*Writer).SetBoundary", Method, 1}, {"(*Writer).WriteField", Method, 0}, {"ErrMessageTooLarge", Var, 9}, {"File", Type, 0}, {"FileContentDisposition", Func, 25}, {"FileHeader", Type, 0}, {"FileHeader.Filename", Field, 0}, {"FileHeader.Header", Field, 0}, {"FileHeader.Size", Field, 9}, {"Form", Type, 0}, {"Form.File", Field, 0}, {"Form.Value", Field, 0}, {"NewReader", Func, 0}, {"NewWriter", Func, 0}, {"Part", Type, 0}, {"Part.Header", Field, 0}, {"Reader", Type, 0}, {"Writer", Type, 0}, }, "mime/quotedprintable": { {"(*Reader).Read", Method, 5}, {"(*Writer).Close", Method, 5}, {"(*Writer).Write", Method, 5}, {"NewReader", Func, 5}, {"NewWriter", Func, 5}, {"Reader", Type, 5}, {"Writer", Type, 5}, {"Writer.Binary", Field, 5}, }, "net": { {"(*AddrError).Error", Method, 0}, {"(*AddrError).Temporary", Method, 0}, {"(*AddrError).Timeout", Method, 0}, {"(*Buffers).Read", Method, 8}, {"(*Buffers).WriteTo", Method, 8}, {"(*DNSConfigError).Error", Method, 0}, {"(*DNSConfigError).Temporary", Method, 0}, {"(*DNSConfigError).Timeout", Method, 0}, {"(*DNSConfigError).Unwrap", Method, 13}, {"(*DNSError).Error", Method, 0}, {"(*DNSError).Temporary", Method, 0}, {"(*DNSError).Timeout", Method, 0}, {"(*DNSError).Unwrap", Method, 23}, {"(*Dialer).Dial", Method, 1}, {"(*Dialer).DialContext", Method, 7}, {"(*Dialer).MultipathTCP", Method, 21}, {"(*Dialer).SetMultipathTCP", Method, 21}, {"(*IP).UnmarshalText", Method, 2}, {"(*IPAddr).Network", Method, 0}, {"(*IPAddr).String", Method, 0}, {"(*IPConn).Close", Method, 0}, {"(*IPConn).File", Method, 0}, {"(*IPConn).LocalAddr", Method, 0}, {"(*IPConn).Read", Method, 0}, {"(*IPConn).ReadFrom", Method, 0}, {"(*IPConn).ReadFromIP", Method, 0}, {"(*IPConn).ReadMsgIP", Method, 1}, {"(*IPConn).RemoteAddr", Method, 0}, {"(*IPConn).SetDeadline", Method, 0}, {"(*IPConn).SetReadBuffer", Method, 0}, {"(*IPConn).SetReadDeadline", Method, 0}, {"(*IPConn).SetWriteBuffer", Method, 0}, {"(*IPConn).SetWriteDeadline", Method, 0}, {"(*IPConn).SyscallConn", Method, 9}, {"(*IPConn).Write", Method, 0}, {"(*IPConn).WriteMsgIP", Method, 1}, {"(*IPConn).WriteTo", Method, 0}, {"(*IPConn).WriteToIP", Method, 0}, {"(*IPNet).Contains", Method, 0}, {"(*IPNet).Network", Method, 0}, {"(*IPNet).String", Method, 0}, {"(*Interface).Addrs", Method, 0}, {"(*Interface).MulticastAddrs", Method, 0}, {"(*ListenConfig).Listen", Method, 11}, {"(*ListenConfig).ListenPacket", Method, 11}, {"(*ListenConfig).MultipathTCP", Method, 21}, {"(*ListenConfig).SetMultipathTCP", Method, 21}, {"(*OpError).Error", Method, 0}, {"(*OpError).Temporary", Method, 0}, {"(*OpError).Timeout", Method, 0}, {"(*OpError).Unwrap", Method, 13}, {"(*ParseError).Error", Method, 0}, {"(*ParseError).Temporary", Method, 17}, {"(*ParseError).Timeout", Method, 17}, {"(*Resolver).LookupAddr", Method, 8}, {"(*Resolver).LookupCNAME", Method, 8}, {"(*Resolver).LookupHost", Method, 8}, {"(*Resolver).LookupIP", Method, 15}, {"(*Resolver).LookupIPAddr", Method, 8}, {"(*Resolver).LookupMX", Method, 8}, {"(*Resolver).LookupNS", Method, 8}, {"(*Resolver).LookupNetIP", Method, 18}, {"(*Resolver).LookupPort", Method, 8}, {"(*Resolver).LookupSRV", Method, 8}, {"(*Resolver).LookupTXT", Method, 8}, {"(*TCPAddr).AddrPort", Method, 18}, {"(*TCPAddr).Network", Method, 0}, {"(*TCPAddr).String", Method, 0}, {"(*TCPConn).Close", Method, 0}, {"(*TCPConn).CloseRead", Method, 0}, {"(*TCPConn).CloseWrite", Method, 0}, {"(*TCPConn).File", Method, 0}, {"(*TCPConn).LocalAddr", Method, 0}, {"(*TCPConn).MultipathTCP", Method, 21}, {"(*TCPConn).Read", Method, 0}, {"(*TCPConn).ReadFrom", Method, 0}, {"(*TCPConn).RemoteAddr", Method, 0}, {"(*TCPConn).SetDeadline", Method, 0}, {"(*TCPConn).SetKeepAlive", Method, 0}, {"(*TCPConn).SetKeepAliveConfig", Method, 23}, {"(*TCPConn).SetKeepAlivePeriod", Method, 2}, {"(*TCPConn).SetLinger", Method, 0}, {"(*TCPConn).SetNoDelay", Method, 0}, {"(*TCPConn).SetReadBuffer", Method, 0}, {"(*TCPConn).SetReadDeadline", Method, 0}, {"(*TCPConn).SetWriteBuffer", Method, 0}, {"(*TCPConn).SetWriteDeadline", Method, 0}, {"(*TCPConn).SyscallConn", Method, 9}, {"(*TCPConn).Write", Method, 0}, {"(*TCPConn).WriteTo", Method, 22}, {"(*TCPListener).Accept", Method, 0}, {"(*TCPListener).AcceptTCP", Method, 0}, {"(*TCPListener).Addr", Method, 0}, {"(*TCPListener).Close", Method, 0}, {"(*TCPListener).File", Method, 0}, {"(*TCPListener).SetDeadline", Method, 0}, {"(*TCPListener).SyscallConn", Method, 10}, {"(*UDPAddr).AddrPort", Method, 18}, {"(*UDPAddr).Network", Method, 0}, {"(*UDPAddr).String", Method, 0}, {"(*UDPConn).Close", Method, 0}, {"(*UDPConn).File", Method, 0}, {"(*UDPConn).LocalAddr", Method, 0}, {"(*UDPConn).Read", Method, 0}, {"(*UDPConn).ReadFrom", Method, 0}, {"(*UDPConn).ReadFromUDP", Method, 0}, {"(*UDPConn).ReadFromUDPAddrPort", Method, 18}, {"(*UDPConn).ReadMsgUDP", Method, 1}, {"(*UDPConn).ReadMsgUDPAddrPort", Method, 18}, {"(*UDPConn).RemoteAddr", Method, 0}, {"(*UDPConn).SetDeadline", Method, 0}, {"(*UDPConn).SetReadBuffer", Method, 0}, {"(*UDPConn).SetReadDeadline", Method, 0}, {"(*UDPConn).SetWriteBuffer", Method, 0}, {"(*UDPConn).SetWriteDeadline", Method, 0}, {"(*UDPConn).SyscallConn", Method, 9}, {"(*UDPConn).Write", Method, 0}, {"(*UDPConn).WriteMsgUDP", Method, 1}, {"(*UDPConn).WriteMsgUDPAddrPort", Method, 18}, {"(*UDPConn).WriteTo", Method, 0}, {"(*UDPConn).WriteToUDP", Method, 0}, {"(*UDPConn).WriteToUDPAddrPort", Method, 18}, {"(*UnixAddr).Network", Method, 0}, {"(*UnixAddr).String", Method, 0}, {"(*UnixConn).Close", Method, 0}, {"(*UnixConn).CloseRead", Method, 1}, {"(*UnixConn).CloseWrite", Method, 1}, {"(*UnixConn).File", Method, 0}, {"(*UnixConn).LocalAddr", Method, 0}, {"(*UnixConn).Read", Method, 0}, {"(*UnixConn).ReadFrom", Method, 0}, {"(*UnixConn).ReadFromUnix", Method, 0}, {"(*UnixConn).ReadMsgUnix", Method, 0}, {"(*UnixConn).RemoteAddr", Method, 0}, {"(*UnixConn).SetDeadline", Method, 0}, {"(*UnixConn).SetReadBuffer", Method, 0}, {"(*UnixConn).SetReadDeadline", Method, 0}, {"(*UnixConn).SetWriteBuffer", Method, 0}, {"(*UnixConn).SetWriteDeadline", Method, 0}, {"(*UnixConn).SyscallConn", Method, 9}, {"(*UnixConn).Write", Method, 0}, {"(*UnixConn).WriteMsgUnix", Method, 0}, {"(*UnixConn).WriteTo", Method, 0}, {"(*UnixConn).WriteToUnix", Method, 0}, {"(*UnixListener).Accept", Method, 0}, {"(*UnixListener).AcceptUnix", Method, 0}, {"(*UnixListener).Addr", Method, 0}, {"(*UnixListener).Close", Method, 0}, {"(*UnixListener).File", Method, 0}, {"(*UnixListener).SetDeadline", Method, 0}, {"(*UnixListener).SetUnlinkOnClose", Method, 8}, {"(*UnixListener).SyscallConn", Method, 10}, {"(Flags).String", Method, 0}, {"(HardwareAddr).String", Method, 0}, {"(IP).AppendText", Method, 24}, {"(IP).DefaultMask", Method, 0}, {"(IP).Equal", Method, 0}, {"(IP).IsGlobalUnicast", Method, 0}, {"(IP).IsInterfaceLocalMulticast", Method, 0}, {"(IP).IsLinkLocalMulticast", Method, 0}, {"(IP).IsLinkLocalUnicast", Method, 0}, {"(IP).IsLoopback", Method, 0}, {"(IP).IsMulticast", Method, 0}, {"(IP).IsPrivate", Method, 17}, {"(IP).IsUnspecified", Method, 0}, {"(IP).MarshalText", Method, 2}, {"(IP).Mask", Method, 0}, {"(IP).String", Method, 0}, {"(IP).To16", Method, 0}, {"(IP).To4", Method, 0}, {"(IPMask).Size", Method, 0}, {"(IPMask).String", Method, 0}, {"(InvalidAddrError).Error", Method, 0}, {"(InvalidAddrError).Temporary", Method, 0}, {"(InvalidAddrError).Timeout", Method, 0}, {"(UnknownNetworkError).Error", Method, 0}, {"(UnknownNetworkError).Temporary", Method, 0}, {"(UnknownNetworkError).Timeout", Method, 0}, {"Addr", Type, 0}, {"AddrError", Type, 0}, {"AddrError.Addr", Field, 0}, {"AddrError.Err", Field, 0}, {"Buffers", Type, 8}, {"CIDRMask", Func, 0}, {"Conn", Type, 0}, {"DNSConfigError", Type, 0}, {"DNSConfigError.Err", Field, 0}, {"DNSError", Type, 0}, {"DNSError.Err", Field, 0}, {"DNSError.IsNotFound", Field, 13}, {"DNSError.IsTemporary", Field, 6}, {"DNSError.IsTimeout", Field, 0}, {"DNSError.Name", Field, 0}, {"DNSError.Server", Field, 0}, {"DNSError.UnwrapErr", Field, 23}, {"DefaultResolver", Var, 8}, {"Dial", Func, 0}, {"DialIP", Func, 0}, {"DialTCP", Func, 0}, {"DialTimeout", Func, 0}, {"DialUDP", Func, 0}, {"DialUnix", Func, 0}, {"Dialer", Type, 1}, {"Dialer.Cancel", Field, 6}, {"Dialer.Control", Field, 11}, {"Dialer.ControlContext", Field, 20}, {"Dialer.Deadline", Field, 1}, {"Dialer.DualStack", Field, 2}, {"Dialer.FallbackDelay", Field, 5}, {"Dialer.KeepAlive", Field, 3}, {"Dialer.KeepAliveConfig", Field, 23}, {"Dialer.LocalAddr", Field, 1}, {"Dialer.Resolver", Field, 8}, {"Dialer.Timeout", Field, 1}, {"ErrClosed", Var, 16}, {"ErrWriteToConnected", Var, 0}, {"Error", Type, 0}, {"FileConn", Func, 0}, {"FileListener", Func, 0}, {"FilePacketConn", Func, 0}, {"FlagBroadcast", Const, 0}, {"FlagLoopback", Const, 0}, {"FlagMulticast", Const, 0}, {"FlagPointToPoint", Const, 0}, {"FlagRunning", Const, 20}, {"FlagUp", Const, 0}, {"Flags", Type, 0}, {"HardwareAddr", Type, 0}, {"IP", Type, 0}, {"IPAddr", Type, 0}, {"IPAddr.IP", Field, 0}, {"IPAddr.Zone", Field, 1}, {"IPConn", Type, 0}, {"IPMask", Type, 0}, {"IPNet", Type, 0}, {"IPNet.IP", Field, 0}, {"IPNet.Mask", Field, 0}, {"IPv4", Func, 0}, {"IPv4Mask", Func, 0}, {"IPv4allrouter", Var, 0}, {"IPv4allsys", Var, 0}, {"IPv4bcast", Var, 0}, {"IPv4len", Const, 0}, {"IPv4zero", Var, 0}, {"IPv6interfacelocalallnodes", Var, 0}, {"IPv6len", Const, 0}, {"IPv6linklocalallnodes", Var, 0}, {"IPv6linklocalallrouters", Var, 0}, {"IPv6loopback", Var, 0}, {"IPv6unspecified", Var, 0}, {"IPv6zero", Var, 0}, {"Interface", Type, 0}, {"Interface.Flags", Field, 0}, {"Interface.HardwareAddr", Field, 0}, {"Interface.Index", Field, 0}, {"Interface.MTU", Field, 0}, {"Interface.Name", Field, 0}, {"InterfaceAddrs", Func, 0}, {"InterfaceByIndex", Func, 0}, {"InterfaceByName", Func, 0}, {"Interfaces", Func, 0}, {"InvalidAddrError", Type, 0}, {"JoinHostPort", Func, 0}, {"KeepAliveConfig", Type, 23}, {"KeepAliveConfig.Count", Field, 23}, {"KeepAliveConfig.Enable", Field, 23}, {"KeepAliveConfig.Idle", Field, 23}, {"KeepAliveConfig.Interval", Field, 23}, {"Listen", Func, 0}, {"ListenConfig", Type, 11}, {"ListenConfig.Control", Field, 11}, {"ListenConfig.KeepAlive", Field, 13}, {"ListenConfig.KeepAliveConfig", Field, 23}, {"ListenIP", Func, 0}, {"ListenMulticastUDP", Func, 0}, {"ListenPacket", Func, 0}, {"ListenTCP", Func, 0}, {"ListenUDP", Func, 0}, {"ListenUnix", Func, 0}, {"ListenUnixgram", Func, 0}, {"Listener", Type, 0}, {"LookupAddr", Func, 0}, {"LookupCNAME", Func, 0}, {"LookupHost", Func, 0}, {"LookupIP", Func, 0}, {"LookupMX", Func, 0}, {"LookupNS", Func, 1}, {"LookupPort", Func, 0}, {"LookupSRV", Func, 0}, {"LookupTXT", Func, 0}, {"MX", Type, 0}, {"MX.Host", Field, 0}, {"MX.Pref", Field, 0}, {"NS", Type, 1}, {"NS.Host", Field, 1}, {"OpError", Type, 0}, {"OpError.Addr", Field, 0}, {"OpError.Err", Field, 0}, {"OpError.Net", Field, 0}, {"OpError.Op", Field, 0}, {"OpError.Source", Field, 5}, {"PacketConn", Type, 0}, {"ParseCIDR", Func, 0}, {"ParseError", Type, 0}, {"ParseError.Text", Field, 0}, {"ParseError.Type", Field, 0}, {"ParseIP", Func, 0}, {"ParseMAC", Func, 0}, {"Pipe", Func, 0}, {"ResolveIPAddr", Func, 0}, {"ResolveTCPAddr", Func, 0}, {"ResolveUDPAddr", Func, 0}, {"ResolveUnixAddr", Func, 0}, {"Resolver", Type, 8}, {"Resolver.Dial", Field, 9}, {"Resolver.PreferGo", Field, 8}, {"Resolver.StrictErrors", Field, 9}, {"SRV", Type, 0}, {"SRV.Port", Field, 0}, {"SRV.Priority", Field, 0}, {"SRV.Target", Field, 0}, {"SRV.Weight", Field, 0}, {"SplitHostPort", Func, 0}, {"TCPAddr", Type, 0}, {"TCPAddr.IP", Field, 0}, {"TCPAddr.Port", Field, 0}, {"TCPAddr.Zone", Field, 1}, {"TCPAddrFromAddrPort", Func, 18}, {"TCPConn", Type, 0}, {"TCPListener", Type, 0}, {"UDPAddr", Type, 0}, {"UDPAddr.IP", Field, 0}, {"UDPAddr.Port", Field, 0}, {"UDPAddr.Zone", Field, 1}, {"UDPAddrFromAddrPort", Func, 18}, {"UDPConn", Type, 0}, {"UnixAddr", Type, 0}, {"UnixAddr.Name", Field, 0}, {"UnixAddr.Net", Field, 0}, {"UnixConn", Type, 0}, {"UnixListener", Type, 0}, {"UnknownNetworkError", Type, 0}, }, "net/http": { {"(*Client).CloseIdleConnections", Method, 12}, {"(*Client).Do", Method, 0}, {"(*Client).Get", Method, 0}, {"(*Client).Head", Method, 0}, {"(*Client).Post", Method, 0}, {"(*Client).PostForm", Method, 0}, {"(*Cookie).String", Method, 0}, {"(*Cookie).Valid", Method, 18}, {"(*MaxBytesError).Error", Method, 19}, {"(*ProtocolError).Error", Method, 0}, {"(*ProtocolError).Is", Method, 21}, {"(*Protocols).SetHTTP1", Method, 24}, {"(*Protocols).SetHTTP2", Method, 24}, {"(*Protocols).SetUnencryptedHTTP2", Method, 24}, {"(*Request).AddCookie", Method, 0}, {"(*Request).BasicAuth", Method, 4}, {"(*Request).Clone", Method, 13}, {"(*Request).Context", Method, 7}, {"(*Request).Cookie", Method, 0}, {"(*Request).Cookies", Method, 0}, {"(*Request).CookiesNamed", Method, 23}, {"(*Request).FormFile", Method, 0}, {"(*Request).FormValue", Method, 0}, {"(*Request).MultipartReader", Method, 0}, {"(*Request).ParseForm", Method, 0}, {"(*Request).ParseMultipartForm", Method, 0}, {"(*Request).PathValue", Method, 22}, {"(*Request).PostFormValue", Method, 1}, {"(*Request).ProtoAtLeast", Method, 0}, {"(*Request).Referer", Method, 0}, {"(*Request).SetBasicAuth", Method, 0}, {"(*Request).SetPathValue", Method, 22}, {"(*Request).UserAgent", Method, 0}, {"(*Request).WithContext", Method, 7}, {"(*Request).Write", Method, 0}, {"(*Request).WriteProxy", Method, 0}, {"(*Response).Cookies", Method, 0}, {"(*Response).Location", Method, 0}, {"(*Response).ProtoAtLeast", Method, 0}, {"(*Response).Write", Method, 0}, {"(*ResponseController).EnableFullDuplex", Method, 21}, {"(*ResponseController).Flush", Method, 20}, {"(*ResponseController).Hijack", Method, 20}, {"(*ResponseController).SetReadDeadline", Method, 20}, {"(*ResponseController).SetWriteDeadline", Method, 20}, {"(*ServeMux).Handle", Method, 0}, {"(*ServeMux).HandleFunc", Method, 0}, {"(*ServeMux).Handler", Method, 1}, {"(*ServeMux).ServeHTTP", Method, 0}, {"(*Server).Close", Method, 8}, {"(*Server).ListenAndServe", Method, 0}, {"(*Server).ListenAndServeTLS", Method, 0}, {"(*Server).RegisterOnShutdown", Method, 9}, {"(*Server).Serve", Method, 0}, {"(*Server).ServeTLS", Method, 9}, {"(*Server).SetKeepAlivesEnabled", Method, 3}, {"(*Server).Shutdown", Method, 8}, {"(*Transport).CancelRequest", Method, 1}, {"(*Transport).Clone", Method, 13}, {"(*Transport).CloseIdleConnections", Method, 0}, {"(*Transport).RegisterProtocol", Method, 0}, {"(*Transport).RoundTrip", Method, 0}, {"(ConnState).String", Method, 3}, {"(Dir).Open", Method, 0}, {"(HandlerFunc).ServeHTTP", Method, 0}, {"(Header).Add", Method, 0}, {"(Header).Clone", Method, 13}, {"(Header).Del", Method, 0}, {"(Header).Get", Method, 0}, {"(Header).Set", Method, 0}, {"(Header).Values", Method, 14}, {"(Header).Write", Method, 0}, {"(Header).WriteSubset", Method, 0}, {"(Protocols).HTTP1", Method, 24}, {"(Protocols).HTTP2", Method, 24}, {"(Protocols).String", Method, 24}, {"(Protocols).UnencryptedHTTP2", Method, 24}, {"AllowQuerySemicolons", Func, 17}, {"CanonicalHeaderKey", Func, 0}, {"Client", Type, 0}, {"Client.CheckRedirect", Field, 0}, {"Client.Jar", Field, 0}, {"Client.Timeout", Field, 3}, {"Client.Transport", Field, 0}, {"CloseNotifier", Type, 1}, {"ConnState", Type, 3}, {"Cookie", Type, 0}, {"Cookie.Domain", Field, 0}, {"Cookie.Expires", Field, 0}, {"Cookie.HttpOnly", Field, 0}, {"Cookie.MaxAge", Field, 0}, {"Cookie.Name", Field, 0}, {"Cookie.Partitioned", Field, 23}, {"Cookie.Path", Field, 0}, {"Cookie.Quoted", Field, 23}, {"Cookie.Raw", Field, 0}, {"Cookie.RawExpires", Field, 0}, {"Cookie.SameSite", Field, 11}, {"Cookie.Secure", Field, 0}, {"Cookie.Unparsed", Field, 0}, {"Cookie.Value", Field, 0}, {"CookieJar", Type, 0}, {"DefaultClient", Var, 0}, {"DefaultMaxHeaderBytes", Const, 0}, {"DefaultMaxIdleConnsPerHost", Const, 0}, {"DefaultServeMux", Var, 0}, {"DefaultTransport", Var, 0}, {"DetectContentType", Func, 0}, {"Dir", Type, 0}, {"ErrAbortHandler", Var, 8}, {"ErrBodyNotAllowed", Var, 0}, {"ErrBodyReadAfterClose", Var, 0}, {"ErrContentLength", Var, 0}, {"ErrHandlerTimeout", Var, 0}, {"ErrHeaderTooLong", Var, 0}, {"ErrHijacked", Var, 0}, {"ErrLineTooLong", Var, 0}, {"ErrMissingBoundary", Var, 0}, {"ErrMissingContentLength", Var, 0}, {"ErrMissingFile", Var, 0}, {"ErrNoCookie", Var, 0}, {"ErrNoLocation", Var, 0}, {"ErrNotMultipart", Var, 0}, {"ErrNotSupported", Var, 0}, {"ErrSchemeMismatch", Var, 21}, {"ErrServerClosed", Var, 8}, {"ErrShortBody", Var, 0}, {"ErrSkipAltProtocol", Var, 6}, {"ErrUnexpectedTrailer", Var, 0}, {"ErrUseLastResponse", Var, 7}, {"ErrWriteAfterFlush", Var, 0}, {"Error", Func, 0}, {"FS", Func, 16}, {"File", Type, 0}, {"FileServer", Func, 0}, {"FileServerFS", Func, 22}, {"FileSystem", Type, 0}, {"Flusher", Type, 0}, {"Get", Func, 0}, {"HTTP2Config", Type, 24}, {"HTTP2Config.CountError", Field, 24}, {"HTTP2Config.MaxConcurrentStreams", Field, 24}, {"HTTP2Config.MaxDecoderHeaderTableSize", Field, 24}, {"HTTP2Config.MaxEncoderHeaderTableSize", Field, 24}, {"HTTP2Config.MaxReadFrameSize", Field, 24}, {"HTTP2Config.MaxReceiveBufferPerConnection", Field, 24}, {"HTTP2Config.MaxReceiveBufferPerStream", Field, 24}, {"HTTP2Config.PermitProhibitedCipherSuites", Field, 24}, {"HTTP2Config.PingTimeout", Field, 24}, {"HTTP2Config.SendPingTimeout", Field, 24}, {"HTTP2Config.WriteByteTimeout", Field, 24}, {"Handle", Func, 0}, {"HandleFunc", Func, 0}, {"Handler", Type, 0}, {"HandlerFunc", Type, 0}, {"Head", Func, 0}, {"Header", Type, 0}, {"Hijacker", Type, 0}, {"ListenAndServe", Func, 0}, {"ListenAndServeTLS", Func, 0}, {"LocalAddrContextKey", Var, 7}, {"MaxBytesError", Type, 19}, {"MaxBytesError.Limit", Field, 19}, {"MaxBytesHandler", Func, 18}, {"MaxBytesReader", Func, 0}, {"MethodConnect", Const, 6}, {"MethodDelete", Const, 6}, {"MethodGet", Const, 6}, {"MethodHead", Const, 6}, {"MethodOptions", Const, 6}, {"MethodPatch", Const, 6}, {"MethodPost", Const, 6}, {"MethodPut", Const, 6}, {"MethodTrace", Const, 6}, {"NewFileTransport", Func, 0}, {"NewFileTransportFS", Func, 22}, {"NewRequest", Func, 0}, {"NewRequestWithContext", Func, 13}, {"NewResponseController", Func, 20}, {"NewServeMux", Func, 0}, {"NoBody", Var, 8}, {"NotFound", Func, 0}, {"NotFoundHandler", Func, 0}, {"ParseCookie", Func, 23}, {"ParseHTTPVersion", Func, 0}, {"ParseSetCookie", Func, 23}, {"ParseTime", Func, 1}, {"Post", Func, 0}, {"PostForm", Func, 0}, {"ProtocolError", Type, 0}, {"ProtocolError.ErrorString", Field, 0}, {"Protocols", Type, 24}, {"ProxyFromEnvironment", Func, 0}, {"ProxyURL", Func, 0}, {"PushOptions", Type, 8}, {"PushOptions.Header", Field, 8}, {"PushOptions.Method", Field, 8}, {"Pusher", Type, 8}, {"ReadRequest", Func, 0}, {"ReadResponse", Func, 0}, {"Redirect", Func, 0}, {"RedirectHandler", Func, 0}, {"Request", Type, 0}, {"Request.Body", Field, 0}, {"Request.Cancel", Field, 5}, {"Request.Close", Field, 0}, {"Request.ContentLength", Field, 0}, {"Request.Form", Field, 0}, {"Request.GetBody", Field, 8}, {"Request.Header", Field, 0}, {"Request.Host", Field, 0}, {"Request.Method", Field, 0}, {"Request.MultipartForm", Field, 0}, {"Request.Pattern", Field, 23}, {"Request.PostForm", Field, 1}, {"Request.Proto", Field, 0}, {"Request.ProtoMajor", Field, 0}, {"Request.ProtoMinor", Field, 0}, {"Request.RemoteAddr", Field, 0}, {"Request.RequestURI", Field, 0}, {"Request.Response", Field, 7}, {"Request.TLS", Field, 0}, {"Request.Trailer", Field, 0}, {"Request.TransferEncoding", Field, 0}, {"Request.URL", Field, 0}, {"Response", Type, 0}, {"Response.Body", Field, 0}, {"Response.Close", Field, 0}, {"Response.ContentLength", Field, 0}, {"Response.Header", Field, 0}, {"Response.Proto", Field, 0}, {"Response.ProtoMajor", Field, 0}, {"Response.ProtoMinor", Field, 0}, {"Response.Request", Field, 0}, {"Response.Status", Field, 0}, {"Response.StatusCode", Field, 0}, {"Response.TLS", Field, 3}, {"Response.Trailer", Field, 0}, {"Response.TransferEncoding", Field, 0}, {"Response.Uncompressed", Field, 7}, {"ResponseController", Type, 20}, {"ResponseWriter", Type, 0}, {"RoundTripper", Type, 0}, {"SameSite", Type, 11}, {"SameSiteDefaultMode", Const, 11}, {"SameSiteLaxMode", Const, 11}, {"SameSiteNoneMode", Const, 13}, {"SameSiteStrictMode", Const, 11}, {"Serve", Func, 0}, {"ServeContent", Func, 0}, {"ServeFile", Func, 0}, {"ServeFileFS", Func, 22}, {"ServeMux", Type, 0}, {"ServeTLS", Func, 9}, {"Server", Type, 0}, {"Server.Addr", Field, 0}, {"Server.BaseContext", Field, 13}, {"Server.ConnContext", Field, 13}, {"Server.ConnState", Field, 3}, {"Server.DisableGeneralOptionsHandler", Field, 20}, {"Server.ErrorLog", Field, 3}, {"Server.HTTP2", Field, 24}, {"Server.Handler", Field, 0}, {"Server.IdleTimeout", Field, 8}, {"Server.MaxHeaderBytes", Field, 0}, {"Server.Protocols", Field, 24}, {"Server.ReadHeaderTimeout", Field, 8}, {"Server.ReadTimeout", Field, 0}, {"Server.TLSConfig", Field, 0}, {"Server.TLSNextProto", Field, 1}, {"Server.WriteTimeout", Field, 0}, {"ServerContextKey", Var, 7}, {"SetCookie", Func, 0}, {"StateActive", Const, 3}, {"StateClosed", Const, 3}, {"StateHijacked", Const, 3}, {"StateIdle", Const, 3}, {"StateNew", Const, 3}, {"StatusAccepted", Const, 0}, {"StatusAlreadyReported", Const, 7}, {"StatusBadGateway", Const, 0}, {"StatusBadRequest", Const, 0}, {"StatusConflict", Const, 0}, {"StatusContinue", Const, 0}, {"StatusCreated", Const, 0}, {"StatusEarlyHints", Const, 13}, {"StatusExpectationFailed", Const, 0}, {"StatusFailedDependency", Const, 7}, {"StatusForbidden", Const, 0}, {"StatusFound", Const, 0}, {"StatusGatewayTimeout", Const, 0}, {"StatusGone", Const, 0}, {"StatusHTTPVersionNotSupported", Const, 0}, {"StatusIMUsed", Const, 7}, {"StatusInsufficientStorage", Const, 7}, {"StatusInternalServerError", Const, 0}, {"StatusLengthRequired", Const, 0}, {"StatusLocked", Const, 7}, {"StatusLoopDetected", Const, 7}, {"StatusMethodNotAllowed", Const, 0}, {"StatusMisdirectedRequest", Const, 11}, {"StatusMovedPermanently", Const, 0}, {"StatusMultiStatus", Const, 7}, {"StatusMultipleChoices", Const, 0}, {"StatusNetworkAuthenticationRequired", Const, 6}, {"StatusNoContent", Const, 0}, {"StatusNonAuthoritativeInfo", Const, 0}, {"StatusNotAcceptable", Const, 0}, {"StatusNotExtended", Const, 7}, {"StatusNotFound", Const, 0}, {"StatusNotImplemented", Const, 0}, {"StatusNotModified", Const, 0}, {"StatusOK", Const, 0}, {"StatusPartialContent", Const, 0}, {"StatusPaymentRequired", Const, 0}, {"StatusPermanentRedirect", Const, 7}, {"StatusPreconditionFailed", Const, 0}, {"StatusPreconditionRequired", Const, 6}, {"StatusProcessing", Const, 7}, {"StatusProxyAuthRequired", Const, 0}, {"StatusRequestEntityTooLarge", Const, 0}, {"StatusRequestHeaderFieldsTooLarge", Const, 6}, {"StatusRequestTimeout", Const, 0}, {"StatusRequestURITooLong", Const, 0}, {"StatusRequestedRangeNotSatisfiable", Const, 0}, {"StatusResetContent", Const, 0}, {"StatusSeeOther", Const, 0}, {"StatusServiceUnavailable", Const, 0}, {"StatusSwitchingProtocols", Const, 0}, {"StatusTeapot", Const, 0}, {"StatusTemporaryRedirect", Const, 0}, {"StatusText", Func, 0}, {"StatusTooEarly", Const, 12}, {"StatusTooManyRequests", Const, 6}, {"StatusUnauthorized", Const, 0}, {"StatusUnavailableForLegalReasons", Const, 6}, {"StatusUnprocessableEntity", Const, 7}, {"StatusUnsupportedMediaType", Const, 0}, {"StatusUpgradeRequired", Const, 7}, {"StatusUseProxy", Const, 0}, {"StatusVariantAlsoNegotiates", Const, 7}, {"StripPrefix", Func, 0}, {"TimeFormat", Const, 0}, {"TimeoutHandler", Func, 0}, {"TrailerPrefix", Const, 8}, {"Transport", Type, 0}, {"Transport.Dial", Field, 0}, {"Transport.DialContext", Field, 7}, {"Transport.DialTLS", Field, 4}, {"Transport.DialTLSContext", Field, 14}, {"Transport.DisableCompression", Field, 0}, {"Transport.DisableKeepAlives", Field, 0}, {"Transport.ExpectContinueTimeout", Field, 6}, {"Transport.ForceAttemptHTTP2", Field, 13}, {"Transport.GetProxyConnectHeader", Field, 16}, {"Transport.HTTP2", Field, 24}, {"Transport.IdleConnTimeout", Field, 7}, {"Transport.MaxConnsPerHost", Field, 11}, {"Transport.MaxIdleConns", Field, 7}, {"Transport.MaxIdleConnsPerHost", Field, 0}, {"Transport.MaxResponseHeaderBytes", Field, 7}, {"Transport.OnProxyConnectResponse", Field, 20}, {"Transport.Protocols", Field, 24}, {"Transport.Proxy", Field, 0}, {"Transport.ProxyConnectHeader", Field, 8}, {"Transport.ReadBufferSize", Field, 13}, {"Transport.ResponseHeaderTimeout", Field, 1}, {"Transport.TLSClientConfig", Field, 0}, {"Transport.TLSHandshakeTimeout", Field, 3}, {"Transport.TLSNextProto", Field, 6}, {"Transport.WriteBufferSize", Field, 13}, }, "net/http/cgi": { {"(*Handler).ServeHTTP", Method, 0}, {"Handler", Type, 0}, {"Handler.Args", Field, 0}, {"Handler.Dir", Field, 0}, {"Handler.Env", Field, 0}, {"Handler.InheritEnv", Field, 0}, {"Handler.Logger", Field, 0}, {"Handler.Path", Field, 0}, {"Handler.PathLocationHandler", Field, 0}, {"Handler.Root", Field, 0}, {"Handler.Stderr", Field, 7}, {"Request", Func, 0}, {"RequestFromMap", Func, 0}, {"Serve", Func, 0}, }, "net/http/cookiejar": { {"(*Jar).Cookies", Method, 1}, {"(*Jar).SetCookies", Method, 1}, {"Jar", Type, 1}, {"New", Func, 1}, {"Options", Type, 1}, {"Options.PublicSuffixList", Field, 1}, {"PublicSuffixList", Type, 1}, }, "net/http/fcgi": { {"ErrConnClosed", Var, 5}, {"ErrRequestAborted", Var, 5}, {"ProcessEnv", Func, 9}, {"Serve", Func, 0}, }, "net/http/httptest": { {"(*ResponseRecorder).Flush", Method, 0}, {"(*ResponseRecorder).Header", Method, 0}, {"(*ResponseRecorder).Result", Method, 7}, {"(*ResponseRecorder).Write", Method, 0}, {"(*ResponseRecorder).WriteHeader", Method, 0}, {"(*ResponseRecorder).WriteString", Method, 6}, {"(*Server).Certificate", Method, 9}, {"(*Server).Client", Method, 9}, {"(*Server).Close", Method, 0}, {"(*Server).CloseClientConnections", Method, 0}, {"(*Server).Start", Method, 0}, {"(*Server).StartTLS", Method, 0}, {"DefaultRemoteAddr", Const, 0}, {"NewRecorder", Func, 0}, {"NewRequest", Func, 7}, {"NewRequestWithContext", Func, 23}, {"NewServer", Func, 0}, {"NewTLSServer", Func, 0}, {"NewUnstartedServer", Func, 0}, {"ResponseRecorder", Type, 0}, {"ResponseRecorder.Body", Field, 0}, {"ResponseRecorder.Code", Field, 0}, {"ResponseRecorder.Flushed", Field, 0}, {"ResponseRecorder.HeaderMap", Field, 0}, {"Server", Type, 0}, {"Server.Config", Field, 0}, {"Server.EnableHTTP2", Field, 14}, {"Server.Listener", Field, 0}, {"Server.TLS", Field, 0}, {"Server.URL", Field, 0}, }, "net/http/httptrace": { {"ClientTrace", Type, 7}, {"ClientTrace.ConnectDone", Field, 7}, {"ClientTrace.ConnectStart", Field, 7}, {"ClientTrace.DNSDone", Field, 7}, {"ClientTrace.DNSStart", Field, 7}, {"ClientTrace.GetConn", Field, 7}, {"ClientTrace.Got100Continue", Field, 7}, {"ClientTrace.Got1xxResponse", Field, 11}, {"ClientTrace.GotConn", Field, 7}, {"ClientTrace.GotFirstResponseByte", Field, 7}, {"ClientTrace.PutIdleConn", Field, 7}, {"ClientTrace.TLSHandshakeDone", Field, 8}, {"ClientTrace.TLSHandshakeStart", Field, 8}, {"ClientTrace.Wait100Continue", Field, 7}, {"ClientTrace.WroteHeaderField", Field, 11}, {"ClientTrace.WroteHeaders", Field, 7}, {"ClientTrace.WroteRequest", Field, 7}, {"ContextClientTrace", Func, 7}, {"DNSDoneInfo", Type, 7}, {"DNSDoneInfo.Addrs", Field, 7}, {"DNSDoneInfo.Coalesced", Field, 7}, {"DNSDoneInfo.Err", Field, 7}, {"DNSStartInfo", Type, 7}, {"DNSStartInfo.Host", Field, 7}, {"GotConnInfo", Type, 7}, {"GotConnInfo.Conn", Field, 7}, {"GotConnInfo.IdleTime", Field, 7}, {"GotConnInfo.Reused", Field, 7}, {"GotConnInfo.WasIdle", Field, 7}, {"WithClientTrace", Func, 7}, {"WroteRequestInfo", Type, 7}, {"WroteRequestInfo.Err", Field, 7}, }, "net/http/httputil": { {"(*ClientConn).Close", Method, 0}, {"(*ClientConn).Do", Method, 0}, {"(*ClientConn).Hijack", Method, 0}, {"(*ClientConn).Pending", Method, 0}, {"(*ClientConn).Read", Method, 0}, {"(*ClientConn).Write", Method, 0}, {"(*ProxyRequest).SetURL", Method, 20}, {"(*ProxyRequest).SetXForwarded", Method, 20}, {"(*ReverseProxy).ServeHTTP", Method, 0}, {"(*ServerConn).Close", Method, 0}, {"(*ServerConn).Hijack", Method, 0}, {"(*ServerConn).Pending", Method, 0}, {"(*ServerConn).Read", Method, 0}, {"(*ServerConn).Write", Method, 0}, {"BufferPool", Type, 6}, {"ClientConn", Type, 0}, {"DumpRequest", Func, 0}, {"DumpRequestOut", Func, 0}, {"DumpResponse", Func, 0}, {"ErrClosed", Var, 0}, {"ErrLineTooLong", Var, 0}, {"ErrPersistEOF", Var, 0}, {"ErrPipeline", Var, 0}, {"NewChunkedReader", Func, 0}, {"NewChunkedWriter", Func, 0}, {"NewClientConn", Func, 0}, {"NewProxyClientConn", Func, 0}, {"NewServerConn", Func, 0}, {"NewSingleHostReverseProxy", Func, 0}, {"ProxyRequest", Type, 20}, {"ProxyRequest.In", Field, 20}, {"ProxyRequest.Out", Field, 20}, {"ReverseProxy", Type, 0}, {"ReverseProxy.BufferPool", Field, 6}, {"ReverseProxy.Director", Field, 0}, {"ReverseProxy.ErrorHandler", Field, 11}, {"ReverseProxy.ErrorLog", Field, 4}, {"ReverseProxy.FlushInterval", Field, 0}, {"ReverseProxy.ModifyResponse", Field, 8}, {"ReverseProxy.Rewrite", Field, 20}, {"ReverseProxy.Transport", Field, 0}, {"ServerConn", Type, 0}, }, "net/http/pprof": { {"Cmdline", Func, 0}, {"Handler", Func, 0}, {"Index", Func, 0}, {"Profile", Func, 0}, {"Symbol", Func, 0}, {"Trace", Func, 5}, }, "net/mail": { {"(*Address).String", Method, 0}, {"(*AddressParser).Parse", Method, 5}, {"(*AddressParser).ParseList", Method, 5}, {"(Header).AddressList", Method, 0}, {"(Header).Date", Method, 0}, {"(Header).Get", Method, 0}, {"Address", Type, 0}, {"Address.Address", Field, 0}, {"Address.Name", Field, 0}, {"AddressParser", Type, 5}, {"AddressParser.WordDecoder", Field, 5}, {"ErrHeaderNotPresent", Var, 0}, {"Header", Type, 0}, {"Message", Type, 0}, {"Message.Body", Field, 0}, {"Message.Header", Field, 0}, {"ParseAddress", Func, 1}, {"ParseAddressList", Func, 1}, {"ParseDate", Func, 8}, {"ReadMessage", Func, 0}, }, "net/netip": { {"(*Addr).UnmarshalBinary", Method, 18}, {"(*Addr).UnmarshalText", Method, 18}, {"(*AddrPort).UnmarshalBinary", Method, 18}, {"(*AddrPort).UnmarshalText", Method, 18}, {"(*Prefix).UnmarshalBinary", Method, 18}, {"(*Prefix).UnmarshalText", Method, 18}, {"(Addr).AppendBinary", Method, 24}, {"(Addr).AppendText", Method, 24}, {"(Addr).AppendTo", Method, 18}, {"(Addr).As16", Method, 18}, {"(Addr).As4", Method, 18}, {"(Addr).AsSlice", Method, 18}, {"(Addr).BitLen", Method, 18}, {"(Addr).Compare", Method, 18}, {"(Addr).Is4", Method, 18}, {"(Addr).Is4In6", Method, 18}, {"(Addr).Is6", Method, 18}, {"(Addr).IsGlobalUnicast", Method, 18}, {"(Addr).IsInterfaceLocalMulticast", Method, 18}, {"(Addr).IsLinkLocalMulticast", Method, 18}, {"(Addr).IsLinkLocalUnicast", Method, 18}, {"(Addr).IsLoopback", Method, 18}, {"(Addr).IsMulticast", Method, 18}, {"(Addr).IsPrivate", Method, 18}, {"(Addr).IsUnspecified", Method, 18}, {"(Addr).IsValid", Method, 18}, {"(Addr).Less", Method, 18}, {"(Addr).MarshalBinary", Method, 18}, {"(Addr).MarshalText", Method, 18}, {"(Addr).Next", Method, 18}, {"(Addr).Prefix", Method, 18}, {"(Addr).Prev", Method, 18}, {"(Addr).String", Method, 18}, {"(Addr).StringExpanded", Method, 18}, {"(Addr).Unmap", Method, 18}, {"(Addr).WithZone", Method, 18}, {"(Addr).Zone", Method, 18}, {"(AddrPort).Addr", Method, 18}, {"(AddrPort).AppendBinary", Method, 24}, {"(AddrPort).AppendText", Method, 24}, {"(AddrPort).AppendTo", Method, 18}, {"(AddrPort).Compare", Method, 22}, {"(AddrPort).IsValid", Method, 18}, {"(AddrPort).MarshalBinary", Method, 18}, {"(AddrPort).MarshalText", Method, 18}, {"(AddrPort).Port", Method, 18}, {"(AddrPort).String", Method, 18}, {"(Prefix).Addr", Method, 18}, {"(Prefix).AppendBinary", Method, 24}, {"(Prefix).AppendText", Method, 24}, {"(Prefix).AppendTo", Method, 18}, {"(Prefix).Bits", Method, 18}, {"(Prefix).Contains", Method, 18}, {"(Prefix).IsSingleIP", Method, 18}, {"(Prefix).IsValid", Method, 18}, {"(Prefix).MarshalBinary", Method, 18}, {"(Prefix).MarshalText", Method, 18}, {"(Prefix).Masked", Method, 18}, {"(Prefix).Overlaps", Method, 18}, {"(Prefix).String", Method, 18}, {"Addr", Type, 18}, {"AddrFrom16", Func, 18}, {"AddrFrom4", Func, 18}, {"AddrFromSlice", Func, 18}, {"AddrPort", Type, 18}, {"AddrPortFrom", Func, 18}, {"IPv4Unspecified", Func, 18}, {"IPv6LinkLocalAllNodes", Func, 18}, {"IPv6LinkLocalAllRouters", Func, 20}, {"IPv6Loopback", Func, 20}, {"IPv6Unspecified", Func, 18}, {"MustParseAddr", Func, 18}, {"MustParseAddrPort", Func, 18}, {"MustParsePrefix", Func, 18}, {"ParseAddr", Func, 18}, {"ParseAddrPort", Func, 18}, {"ParsePrefix", Func, 18}, {"Prefix", Type, 18}, {"PrefixFrom", Func, 18}, }, "net/rpc": { {"(*Client).Call", Method, 0}, {"(*Client).Close", Method, 0}, {"(*Client).Go", Method, 0}, {"(*Server).Accept", Method, 0}, {"(*Server).HandleHTTP", Method, 0}, {"(*Server).Register", Method, 0}, {"(*Server).RegisterName", Method, 0}, {"(*Server).ServeCodec", Method, 0}, {"(*Server).ServeConn", Method, 0}, {"(*Server).ServeHTTP", Method, 0}, {"(*Server).ServeRequest", Method, 0}, {"(ServerError).Error", Method, 0}, {"Accept", Func, 0}, {"Call", Type, 0}, {"Call.Args", Field, 0}, {"Call.Done", Field, 0}, {"Call.Error", Field, 0}, {"Call.Reply", Field, 0}, {"Call.ServiceMethod", Field, 0}, {"Client", Type, 0}, {"ClientCodec", Type, 0}, {"DefaultDebugPath", Const, 0}, {"DefaultRPCPath", Const, 0}, {"DefaultServer", Var, 0}, {"Dial", Func, 0}, {"DialHTTP", Func, 0}, {"DialHTTPPath", Func, 0}, {"ErrShutdown", Var, 0}, {"HandleHTTP", Func, 0}, {"NewClient", Func, 0}, {"NewClientWithCodec", Func, 0}, {"NewServer", Func, 0}, {"Register", Func, 0}, {"RegisterName", Func, 0}, {"Request", Type, 0}, {"Request.Seq", Field, 0}, {"Request.ServiceMethod", Field, 0}, {"Response", Type, 0}, {"Response.Error", Field, 0}, {"Response.Seq", Field, 0}, {"Response.ServiceMethod", Field, 0}, {"ServeCodec", Func, 0}, {"ServeConn", Func, 0}, {"ServeRequest", Func, 0}, {"Server", Type, 0}, {"ServerCodec", Type, 0}, {"ServerError", Type, 0}, }, "net/rpc/jsonrpc": { {"Dial", Func, 0}, {"NewClient", Func, 0}, {"NewClientCodec", Func, 0}, {"NewServerCodec", Func, 0}, {"ServeConn", Func, 0}, }, "net/smtp": { {"(*Client).Auth", Method, 0}, {"(*Client).Close", Method, 2}, {"(*Client).Data", Method, 0}, {"(*Client).Extension", Method, 0}, {"(*Client).Hello", Method, 1}, {"(*Client).Mail", Method, 0}, {"(*Client).Noop", Method, 10}, {"(*Client).Quit", Method, 0}, {"(*Client).Rcpt", Method, 0}, {"(*Client).Reset", Method, 0}, {"(*Client).StartTLS", Method, 0}, {"(*Client).TLSConnectionState", Method, 5}, {"(*Client).Verify", Method, 0}, {"Auth", Type, 0}, {"CRAMMD5Auth", Func, 0}, {"Client", Type, 0}, {"Client.Text", Field, 0}, {"Dial", Func, 0}, {"NewClient", Func, 0}, {"PlainAuth", Func, 0}, {"SendMail", Func, 0}, {"ServerInfo", Type, 0}, {"ServerInfo.Auth", Field, 0}, {"ServerInfo.Name", Field, 0}, {"ServerInfo.TLS", Field, 0}, }, "net/textproto": { {"(*Conn).Close", Method, 0}, {"(*Conn).Cmd", Method, 0}, {"(*Conn).DotReader", Method, 0}, {"(*Conn).DotWriter", Method, 0}, {"(*Conn).EndRequest", Method, 0}, {"(*Conn).EndResponse", Method, 0}, {"(*Conn).Next", Method, 0}, {"(*Conn).PrintfLine", Method, 0}, {"(*Conn).ReadCodeLine", Method, 0}, {"(*Conn).ReadContinuedLine", Method, 0}, {"(*Conn).ReadContinuedLineBytes", Method, 0}, {"(*Conn).ReadDotBytes", Method, 0}, {"(*Conn).ReadDotLines", Method, 0}, {"(*Conn).ReadLine", Method, 0}, {"(*Conn).ReadLineBytes", Method, 0}, {"(*Conn).ReadMIMEHeader", Method, 0}, {"(*Conn).ReadResponse", Method, 0}, {"(*Conn).StartRequest", Method, 0}, {"(*Conn).StartResponse", Method, 0}, {"(*Error).Error", Method, 0}, {"(*Pipeline).EndRequest", Method, 0}, {"(*Pipeline).EndResponse", Method, 0}, {"(*Pipeline).Next", Method, 0}, {"(*Pipeline).StartRequest", Method, 0}, {"(*Pipeline).StartResponse", Method, 0}, {"(*Reader).DotReader", Method, 0}, {"(*Reader).ReadCodeLine", Method, 0}, {"(*Reader).ReadContinuedLine", Method, 0}, {"(*Reader).ReadContinuedLineBytes", Method, 0}, {"(*Reader).ReadDotBytes", Method, 0}, {"(*Reader).ReadDotLines", Method, 0}, {"(*Reader).ReadLine", Method, 0}, {"(*Reader).ReadLineBytes", Method, 0}, {"(*Reader).ReadMIMEHeader", Method, 0}, {"(*Reader).ReadResponse", Method, 0}, {"(*Writer).DotWriter", Method, 0}, {"(*Writer).PrintfLine", Method, 0}, {"(MIMEHeader).Add", Method, 0}, {"(MIMEHeader).Del", Method, 0}, {"(MIMEHeader).Get", Method, 0}, {"(MIMEHeader).Set", Method, 0}, {"(MIMEHeader).Values", Method, 14}, {"(ProtocolError).Error", Method, 0}, {"CanonicalMIMEHeaderKey", Func, 0}, {"Conn", Type, 0}, {"Conn.Pipeline", Field, 0}, {"Conn.Reader", Field, 0}, {"Conn.Writer", Field, 0}, {"Dial", Func, 0}, {"Error", Type, 0}, {"Error.Code", Field, 0}, {"Error.Msg", Field, 0}, {"MIMEHeader", Type, 0}, {"NewConn", Func, 0}, {"NewReader", Func, 0}, {"NewWriter", Func, 0}, {"Pipeline", Type, 0}, {"ProtocolError", Type, 0}, {"Reader", Type, 0}, {"Reader.R", Field, 0}, {"TrimBytes", Func, 1}, {"TrimString", Func, 1}, {"Writer", Type, 0}, {"Writer.W", Field, 0}, }, "net/url": { {"(*Error).Error", Method, 0}, {"(*Error).Temporary", Method, 6}, {"(*Error).Timeout", Method, 6}, {"(*Error).Unwrap", Method, 13}, {"(*URL).AppendBinary", Method, 24}, {"(*URL).EscapedFragment", Method, 15}, {"(*URL).EscapedPath", Method, 5}, {"(*URL).Hostname", Method, 8}, {"(*URL).IsAbs", Method, 0}, {"(*URL).JoinPath", Method, 19}, {"(*URL).MarshalBinary", Method, 8}, {"(*URL).Parse", Method, 0}, {"(*URL).Port", Method, 8}, {"(*URL).Query", Method, 0}, {"(*URL).Redacted", Method, 15}, {"(*URL).RequestURI", Method, 0}, {"(*URL).ResolveReference", Method, 0}, {"(*URL).String", Method, 0}, {"(*URL).UnmarshalBinary", Method, 8}, {"(*Userinfo).Password", Method, 0}, {"(*Userinfo).String", Method, 0}, {"(*Userinfo).Username", Method, 0}, {"(EscapeError).Error", Method, 0}, {"(InvalidHostError).Error", Method, 6}, {"(Values).Add", Method, 0}, {"(Values).Del", Method, 0}, {"(Values).Encode", Method, 0}, {"(Values).Get", Method, 0}, {"(Values).Has", Method, 17}, {"(Values).Set", Method, 0}, {"Error", Type, 0}, {"Error.Err", Field, 0}, {"Error.Op", Field, 0}, {"Error.URL", Field, 0}, {"EscapeError", Type, 0}, {"InvalidHostError", Type, 6}, {"JoinPath", Func, 19}, {"Parse", Func, 0}, {"ParseQuery", Func, 0}, {"ParseRequestURI", Func, 0}, {"PathEscape", Func, 8}, {"PathUnescape", Func, 8}, {"QueryEscape", Func, 0}, {"QueryUnescape", Func, 0}, {"URL", Type, 0}, {"URL.ForceQuery", Field, 7}, {"URL.Fragment", Field, 0}, {"URL.Host", Field, 0}, {"URL.OmitHost", Field, 19}, {"URL.Opaque", Field, 0}, {"URL.Path", Field, 0}, {"URL.RawFragment", Field, 15}, {"URL.RawPath", Field, 5}, {"URL.RawQuery", Field, 0}, {"URL.Scheme", Field, 0}, {"URL.User", Field, 0}, {"User", Func, 0}, {"UserPassword", Func, 0}, {"Userinfo", Type, 0}, {"Values", Type, 0}, }, "os": { {"(*File).Chdir", Method, 0}, {"(*File).Chmod", Method, 0}, {"(*File).Chown", Method, 0}, {"(*File).Close", Method, 0}, {"(*File).Fd", Method, 0}, {"(*File).Name", Method, 0}, {"(*File).Read", Method, 0}, {"(*File).ReadAt", Method, 0}, {"(*File).ReadDir", Method, 16}, {"(*File).ReadFrom", Method, 15}, {"(*File).Readdir", Method, 0}, {"(*File).Readdirnames", Method, 0}, {"(*File).Seek", Method, 0}, {"(*File).SetDeadline", Method, 10}, {"(*File).SetReadDeadline", Method, 10}, {"(*File).SetWriteDeadline", Method, 10}, {"(*File).Stat", Method, 0}, {"(*File).Sync", Method, 0}, {"(*File).SyscallConn", Method, 12}, {"(*File).Truncate", Method, 0}, {"(*File).Write", Method, 0}, {"(*File).WriteAt", Method, 0}, {"(*File).WriteString", Method, 0}, {"(*File).WriteTo", Method, 22}, {"(*LinkError).Error", Method, 0}, {"(*LinkError).Unwrap", Method, 13}, {"(*PathError).Error", Method, 0}, {"(*PathError).Timeout", Method, 10}, {"(*PathError).Unwrap", Method, 13}, {"(*Process).Kill", Method, 0}, {"(*Process).Release", Method, 0}, {"(*Process).Signal", Method, 0}, {"(*Process).Wait", Method, 0}, {"(*ProcessState).ExitCode", Method, 12}, {"(*ProcessState).Exited", Method, 0}, {"(*ProcessState).Pid", Method, 0}, {"(*ProcessState).String", Method, 0}, {"(*ProcessState).Success", Method, 0}, {"(*ProcessState).Sys", Method, 0}, {"(*ProcessState).SysUsage", Method, 0}, {"(*ProcessState).SystemTime", Method, 0}, {"(*ProcessState).UserTime", Method, 0}, {"(*Root).Chmod", Method, 25}, {"(*Root).Chown", Method, 25}, {"(*Root).Chtimes", Method, 25}, {"(*Root).Close", Method, 24}, {"(*Root).Create", Method, 24}, {"(*Root).FS", Method, 24}, {"(*Root).Lchown", Method, 25}, {"(*Root).Link", Method, 25}, {"(*Root).Lstat", Method, 24}, {"(*Root).Mkdir", Method, 24}, {"(*Root).Name", Method, 24}, {"(*Root).Open", Method, 24}, {"(*Root).OpenFile", Method, 24}, {"(*Root).OpenRoot", Method, 24}, {"(*Root).Readlink", Method, 25}, {"(*Root).Remove", Method, 24}, {"(*Root).Rename", Method, 25}, {"(*Root).Stat", Method, 24}, {"(*Root).Symlink", Method, 25}, {"(*SyscallError).Error", Method, 0}, {"(*SyscallError).Timeout", Method, 10}, {"(*SyscallError).Unwrap", Method, 13}, {"(FileMode).IsDir", Method, 0}, {"(FileMode).IsRegular", Method, 1}, {"(FileMode).Perm", Method, 0}, {"(FileMode).String", Method, 0}, {"Args", Var, 0}, {"Chdir", Func, 0}, {"Chmod", Func, 0}, {"Chown", Func, 0}, {"Chtimes", Func, 0}, {"Clearenv", Func, 0}, {"CopyFS", Func, 23}, {"Create", Func, 0}, {"CreateTemp", Func, 16}, {"DevNull", Const, 0}, {"DirEntry", Type, 16}, {"DirFS", Func, 16}, {"Environ", Func, 0}, {"ErrClosed", Var, 8}, {"ErrDeadlineExceeded", Var, 15}, {"ErrExist", Var, 0}, {"ErrInvalid", Var, 0}, {"ErrNoDeadline", Var, 10}, {"ErrNotExist", Var, 0}, {"ErrPermission", Var, 0}, {"ErrProcessDone", Var, 16}, {"Executable", Func, 8}, {"Exit", Func, 0}, {"Expand", Func, 0}, {"ExpandEnv", Func, 0}, {"File", Type, 0}, {"FileInfo", Type, 0}, {"FileMode", Type, 0}, {"FindProcess", Func, 0}, {"Getegid", Func, 0}, {"Getenv", Func, 0}, {"Geteuid", Func, 0}, {"Getgid", Func, 0}, {"Getgroups", Func, 0}, {"Getpagesize", Func, 0}, {"Getpid", Func, 0}, {"Getppid", Func, 0}, {"Getuid", Func, 0}, {"Getwd", Func, 0}, {"Hostname", Func, 0}, {"Interrupt", Var, 0}, {"IsExist", Func, 0}, {"IsNotExist", Func, 0}, {"IsPathSeparator", Func, 0}, {"IsPermission", Func, 0}, {"IsTimeout", Func, 10}, {"Kill", Var, 0}, {"Lchown", Func, 0}, {"Link", Func, 0}, {"LinkError", Type, 0}, {"LinkError.Err", Field, 0}, {"LinkError.New", Field, 0}, {"LinkError.Old", Field, 0}, {"LinkError.Op", Field, 0}, {"LookupEnv", Func, 5}, {"Lstat", Func, 0}, {"Mkdir", Func, 0}, {"MkdirAll", Func, 0}, {"MkdirTemp", Func, 16}, {"ModeAppend", Const, 0}, {"ModeCharDevice", Const, 0}, {"ModeDevice", Const, 0}, {"ModeDir", Const, 0}, {"ModeExclusive", Const, 0}, {"ModeIrregular", Const, 11}, {"ModeNamedPipe", Const, 0}, {"ModePerm", Const, 0}, {"ModeSetgid", Const, 0}, {"ModeSetuid", Const, 0}, {"ModeSocket", Const, 0}, {"ModeSticky", Const, 0}, {"ModeSymlink", Const, 0}, {"ModeTemporary", Const, 0}, {"ModeType", Const, 0}, {"NewFile", Func, 0}, {"NewSyscallError", Func, 0}, {"O_APPEND", Const, 0}, {"O_CREATE", Const, 0}, {"O_EXCL", Const, 0}, {"O_RDONLY", Const, 0}, {"O_RDWR", Const, 0}, {"O_SYNC", Const, 0}, {"O_TRUNC", Const, 0}, {"O_WRONLY", Const, 0}, {"Open", Func, 0}, {"OpenFile", Func, 0}, {"OpenInRoot", Func, 24}, {"OpenRoot", Func, 24}, {"PathError", Type, 0}, {"PathError.Err", Field, 0}, {"PathError.Op", Field, 0}, {"PathError.Path", Field, 0}, {"PathListSeparator", Const, 0}, {"PathSeparator", Const, 0}, {"Pipe", Func, 0}, {"ProcAttr", Type, 0}, {"ProcAttr.Dir", Field, 0}, {"ProcAttr.Env", Field, 0}, {"ProcAttr.Files", Field, 0}, {"ProcAttr.Sys", Field, 0}, {"Process", Type, 0}, {"Process.Pid", Field, 0}, {"ProcessState", Type, 0}, {"ReadDir", Func, 16}, {"ReadFile", Func, 16}, {"Readlink", Func, 0}, {"Remove", Func, 0}, {"RemoveAll", Func, 0}, {"Rename", Func, 0}, {"Root", Type, 24}, {"SEEK_CUR", Const, 0}, {"SEEK_END", Const, 0}, {"SEEK_SET", Const, 0}, {"SameFile", Func, 0}, {"Setenv", Func, 0}, {"Signal", Type, 0}, {"StartProcess", Func, 0}, {"Stat", Func, 0}, {"Stderr", Var, 0}, {"Stdin", Var, 0}, {"Stdout", Var, 0}, {"Symlink", Func, 0}, {"SyscallError", Type, 0}, {"SyscallError.Err", Field, 0}, {"SyscallError.Syscall", Field, 0}, {"TempDir", Func, 0}, {"Truncate", Func, 0}, {"Unsetenv", Func, 4}, {"UserCacheDir", Func, 11}, {"UserConfigDir", Func, 13}, {"UserHomeDir", Func, 12}, {"WriteFile", Func, 16}, }, "os/exec": { {"(*Cmd).CombinedOutput", Method, 0}, {"(*Cmd).Environ", Method, 19}, {"(*Cmd).Output", Method, 0}, {"(*Cmd).Run", Method, 0}, {"(*Cmd).Start", Method, 0}, {"(*Cmd).StderrPipe", Method, 0}, {"(*Cmd).StdinPipe", Method, 0}, {"(*Cmd).StdoutPipe", Method, 0}, {"(*Cmd).String", Method, 13}, {"(*Cmd).Wait", Method, 0}, {"(*Error).Error", Method, 0}, {"(*Error).Unwrap", Method, 13}, {"(*ExitError).Error", Method, 0}, {"(ExitError).ExitCode", Method, 12}, {"(ExitError).Exited", Method, 0}, {"(ExitError).Pid", Method, 0}, {"(ExitError).String", Method, 0}, {"(ExitError).Success", Method, 0}, {"(ExitError).Sys", Method, 0}, {"(ExitError).SysUsage", Method, 0}, {"(ExitError).SystemTime", Method, 0}, {"(ExitError).UserTime", Method, 0}, {"Cmd", Type, 0}, {"Cmd.Args", Field, 0}, {"Cmd.Cancel", Field, 20}, {"Cmd.Dir", Field, 0}, {"Cmd.Env", Field, 0}, {"Cmd.Err", Field, 19}, {"Cmd.ExtraFiles", Field, 0}, {"Cmd.Path", Field, 0}, {"Cmd.Process", Field, 0}, {"Cmd.ProcessState", Field, 0}, {"Cmd.Stderr", Field, 0}, {"Cmd.Stdin", Field, 0}, {"Cmd.Stdout", Field, 0}, {"Cmd.SysProcAttr", Field, 0}, {"Cmd.WaitDelay", Field, 20}, {"Command", Func, 0}, {"CommandContext", Func, 7}, {"ErrDot", Var, 19}, {"ErrNotFound", Var, 0}, {"ErrWaitDelay", Var, 20}, {"Error", Type, 0}, {"Error.Err", Field, 0}, {"Error.Name", Field, 0}, {"ExitError", Type, 0}, {"ExitError.ProcessState", Field, 0}, {"ExitError.Stderr", Field, 6}, {"LookPath", Func, 0}, }, "os/signal": { {"Ignore", Func, 5}, {"Ignored", Func, 11}, {"Notify", Func, 0}, {"NotifyContext", Func, 16}, {"Reset", Func, 5}, {"Stop", Func, 1}, }, "os/user": { {"(*User).GroupIds", Method, 7}, {"(UnknownGroupError).Error", Method, 7}, {"(UnknownGroupIdError).Error", Method, 7}, {"(UnknownUserError).Error", Method, 0}, {"(UnknownUserIdError).Error", Method, 0}, {"Current", Func, 0}, {"Group", Type, 7}, {"Group.Gid", Field, 7}, {"Group.Name", Field, 7}, {"Lookup", Func, 0}, {"LookupGroup", Func, 7}, {"LookupGroupId", Func, 7}, {"LookupId", Func, 0}, {"UnknownGroupError", Type, 7}, {"UnknownGroupIdError", Type, 7}, {"UnknownUserError", Type, 0}, {"UnknownUserIdError", Type, 0}, {"User", Type, 0}, {"User.Gid", Field, 0}, {"User.HomeDir", Field, 0}, {"User.Name", Field, 0}, {"User.Uid", Field, 0}, {"User.Username", Field, 0}, }, "path": { {"Base", Func, 0}, {"Clean", Func, 0}, {"Dir", Func, 0}, {"ErrBadPattern", Var, 0}, {"Ext", Func, 0}, {"IsAbs", Func, 0}, {"Join", Func, 0}, {"Match", Func, 0}, {"Split", Func, 0}, }, "path/filepath": { {"Abs", Func, 0}, {"Base", Func, 0}, {"Clean", Func, 0}, {"Dir", Func, 0}, {"ErrBadPattern", Var, 0}, {"EvalSymlinks", Func, 0}, {"Ext", Func, 0}, {"FromSlash", Func, 0}, {"Glob", Func, 0}, {"HasPrefix", Func, 0}, {"IsAbs", Func, 0}, {"IsLocal", Func, 20}, {"Join", Func, 0}, {"ListSeparator", Const, 0}, {"Localize", Func, 23}, {"Match", Func, 0}, {"Rel", Func, 0}, {"Separator", Const, 0}, {"SkipAll", Var, 20}, {"SkipDir", Var, 0}, {"Split", Func, 0}, {"SplitList", Func, 0}, {"ToSlash", Func, 0}, {"VolumeName", Func, 0}, {"Walk", Func, 0}, {"WalkDir", Func, 16}, {"WalkFunc", Type, 0}, }, "plugin": { {"(*Plugin).Lookup", Method, 8}, {"Open", Func, 8}, {"Plugin", Type, 8}, {"Symbol", Type, 8}, }, "reflect": { {"(*MapIter).Key", Method, 12}, {"(*MapIter).Next", Method, 12}, {"(*MapIter).Reset", Method, 18}, {"(*MapIter).Value", Method, 12}, {"(*ValueError).Error", Method, 0}, {"(ChanDir).String", Method, 0}, {"(Kind).String", Method, 0}, {"(Method).IsExported", Method, 17}, {"(StructField).IsExported", Method, 17}, {"(StructTag).Get", Method, 0}, {"(StructTag).Lookup", Method, 7}, {"(Value).Addr", Method, 0}, {"(Value).Bool", Method, 0}, {"(Value).Bytes", Method, 0}, {"(Value).Call", Method, 0}, {"(Value).CallSlice", Method, 0}, {"(Value).CanAddr", Method, 0}, {"(Value).CanComplex", Method, 18}, {"(Value).CanConvert", Method, 17}, {"(Value).CanFloat", Method, 18}, {"(Value).CanInt", Method, 18}, {"(Value).CanInterface", Method, 0}, {"(Value).CanSet", Method, 0}, {"(Value).CanUint", Method, 18}, {"(Value).Cap", Method, 0}, {"(Value).Clear", Method, 21}, {"(Value).Close", Method, 0}, {"(Value).Comparable", Method, 20}, {"(Value).Complex", Method, 0}, {"(Value).Convert", Method, 1}, {"(Value).Elem", Method, 0}, {"(Value).Equal", Method, 20}, {"(Value).Field", Method, 0}, {"(Value).FieldByIndex", Method, 0}, {"(Value).FieldByIndexErr", Method, 18}, {"(Value).FieldByName", Method, 0}, {"(Value).FieldByNameFunc", Method, 0}, {"(Value).Float", Method, 0}, {"(Value).Grow", Method, 20}, {"(Value).Index", Method, 0}, {"(Value).Int", Method, 0}, {"(Value).Interface", Method, 0}, {"(Value).InterfaceData", Method, 0}, {"(Value).IsNil", Method, 0}, {"(Value).IsValid", Method, 0}, {"(Value).IsZero", Method, 13}, {"(Value).Kind", Method, 0}, {"(Value).Len", Method, 0}, {"(Value).MapIndex", Method, 0}, {"(Value).MapKeys", Method, 0}, {"(Value).MapRange", Method, 12}, {"(Value).Method", Method, 0}, {"(Value).MethodByName", Method, 0}, {"(Value).NumField", Method, 0}, {"(Value).NumMethod", Method, 0}, {"(Value).OverflowComplex", Method, 0}, {"(Value).OverflowFloat", Method, 0}, {"(Value).OverflowInt", Method, 0}, {"(Value).OverflowUint", Method, 0}, {"(Value).Pointer", Method, 0}, {"(Value).Recv", Method, 0}, {"(Value).Send", Method, 0}, {"(Value).Seq", Method, 23}, {"(Value).Seq2", Method, 23}, {"(Value).Set", Method, 0}, {"(Value).SetBool", Method, 0}, {"(Value).SetBytes", Method, 0}, {"(Value).SetCap", Method, 2}, {"(Value).SetComplex", Method, 0}, {"(Value).SetFloat", Method, 0}, {"(Value).SetInt", Method, 0}, {"(Value).SetIterKey", Method, 18}, {"(Value).SetIterValue", Method, 18}, {"(Value).SetLen", Method, 0}, {"(Value).SetMapIndex", Method, 0}, {"(Value).SetPointer", Method, 0}, {"(Value).SetString", Method, 0}, {"(Value).SetUint", Method, 0}, {"(Value).SetZero", Method, 20}, {"(Value).Slice", Method, 0}, {"(Value).Slice3", Method, 2}, {"(Value).String", Method, 0}, {"(Value).TryRecv", Method, 0}, {"(Value).TrySend", Method, 0}, {"(Value).Type", Method, 0}, {"(Value).Uint", Method, 0}, {"(Value).UnsafeAddr", Method, 0}, {"(Value).UnsafePointer", Method, 18}, {"Append", Func, 0}, {"AppendSlice", Func, 0}, {"Array", Const, 0}, {"ArrayOf", Func, 5}, {"Bool", Const, 0}, {"BothDir", Const, 0}, {"Chan", Const, 0}, {"ChanDir", Type, 0}, {"ChanOf", Func, 1}, {"Complex128", Const, 0}, {"Complex64", Const, 0}, {"Copy", Func, 0}, {"DeepEqual", Func, 0}, {"Float32", Const, 0}, {"Float64", Const, 0}, {"Func", Const, 0}, {"FuncOf", Func, 5}, {"Indirect", Func, 0}, {"Int", Const, 0}, {"Int16", Const, 0}, {"Int32", Const, 0}, {"Int64", Const, 0}, {"Int8", Const, 0}, {"Interface", Const, 0}, {"Invalid", Const, 0}, {"Kind", Type, 0}, {"MakeChan", Func, 0}, {"MakeFunc", Func, 1}, {"MakeMap", Func, 0}, {"MakeMapWithSize", Func, 9}, {"MakeSlice", Func, 0}, {"Map", Const, 0}, {"MapIter", Type, 12}, {"MapOf", Func, 1}, {"Method", Type, 0}, {"Method.Func", Field, 0}, {"Method.Index", Field, 0}, {"Method.Name", Field, 0}, {"Method.PkgPath", Field, 0}, {"Method.Type", Field, 0}, {"New", Func, 0}, {"NewAt", Func, 0}, {"Pointer", Const, 18}, {"PointerTo", Func, 18}, {"Ptr", Const, 0}, {"PtrTo", Func, 0}, {"RecvDir", Const, 0}, {"Select", Func, 1}, {"SelectCase", Type, 1}, {"SelectCase.Chan", Field, 1}, {"SelectCase.Dir", Field, 1}, {"SelectCase.Send", Field, 1}, {"SelectDefault", Const, 1}, {"SelectDir", Type, 1}, {"SelectRecv", Const, 1}, {"SelectSend", Const, 1}, {"SendDir", Const, 0}, {"Slice", Const, 0}, {"SliceAt", Func, 23}, {"SliceHeader", Type, 0}, {"SliceHeader.Cap", Field, 0}, {"SliceHeader.Data", Field, 0}, {"SliceHeader.Len", Field, 0}, {"SliceOf", Func, 1}, {"String", Const, 0}, {"StringHeader", Type, 0}, {"StringHeader.Data", Field, 0}, {"StringHeader.Len", Field, 0}, {"Struct", Const, 0}, {"StructField", Type, 0}, {"StructField.Anonymous", Field, 0}, {"StructField.Index", Field, 0}, {"StructField.Name", Field, 0}, {"StructField.Offset", Field, 0}, {"StructField.PkgPath", Field, 0}, {"StructField.Tag", Field, 0}, {"StructField.Type", Field, 0}, {"StructOf", Func, 7}, {"StructTag", Type, 0}, {"Swapper", Func, 8}, {"Type", Type, 0}, {"TypeFor", Func, 22}, {"TypeOf", Func, 0}, {"Uint", Const, 0}, {"Uint16", Const, 0}, {"Uint32", Const, 0}, {"Uint64", Const, 0}, {"Uint8", Const, 0}, {"Uintptr", Const, 0}, {"UnsafePointer", Const, 0}, {"Value", Type, 0}, {"ValueError", Type, 0}, {"ValueError.Kind", Field, 0}, {"ValueError.Method", Field, 0}, {"ValueOf", Func, 0}, {"VisibleFields", Func, 17}, {"Zero", Func, 0}, }, "regexp": { {"(*Regexp).AppendText", Method, 24}, {"(*Regexp).Copy", Method, 6}, {"(*Regexp).Expand", Method, 0}, {"(*Regexp).ExpandString", Method, 0}, {"(*Regexp).Find", Method, 0}, {"(*Regexp).FindAll", Method, 0}, {"(*Regexp).FindAllIndex", Method, 0}, {"(*Regexp).FindAllString", Method, 0}, {"(*Regexp).FindAllStringIndex", Method, 0}, {"(*Regexp).FindAllStringSubmatch", Method, 0}, {"(*Regexp).FindAllStringSubmatchIndex", Method, 0}, {"(*Regexp).FindAllSubmatch", Method, 0}, {"(*Regexp).FindAllSubmatchIndex", Method, 0}, {"(*Regexp).FindIndex", Method, 0}, {"(*Regexp).FindReaderIndex", Method, 0}, {"(*Regexp).FindReaderSubmatchIndex", Method, 0}, {"(*Regexp).FindString", Method, 0}, {"(*Regexp).FindStringIndex", Method, 0}, {"(*Regexp).FindStringSubmatch", Method, 0}, {"(*Regexp).FindStringSubmatchIndex", Method, 0}, {"(*Regexp).FindSubmatch", Method, 0}, {"(*Regexp).FindSubmatchIndex", Method, 0}, {"(*Regexp).LiteralPrefix", Method, 0}, {"(*Regexp).Longest", Method, 1}, {"(*Regexp).MarshalText", Method, 21}, {"(*Regexp).Match", Method, 0}, {"(*Regexp).MatchReader", Method, 0}, {"(*Regexp).MatchString", Method, 0}, {"(*Regexp).NumSubexp", Method, 0}, {"(*Regexp).ReplaceAll", Method, 0}, {"(*Regexp).ReplaceAllFunc", Method, 0}, {"(*Regexp).ReplaceAllLiteral", Method, 0}, {"(*Regexp).ReplaceAllLiteralString", Method, 0}, {"(*Regexp).ReplaceAllString", Method, 0}, {"(*Regexp).ReplaceAllStringFunc", Method, 0}, {"(*Regexp).Split", Method, 1}, {"(*Regexp).String", Method, 0}, {"(*Regexp).SubexpIndex", Method, 15}, {"(*Regexp).SubexpNames", Method, 0}, {"(*Regexp).UnmarshalText", Method, 21}, {"Compile", Func, 0}, {"CompilePOSIX", Func, 0}, {"Match", Func, 0}, {"MatchReader", Func, 0}, {"MatchString", Func, 0}, {"MustCompile", Func, 0}, {"MustCompilePOSIX", Func, 0}, {"QuoteMeta", Func, 0}, {"Regexp", Type, 0}, }, "regexp/syntax": { {"(*Error).Error", Method, 0}, {"(*Inst).MatchEmptyWidth", Method, 0}, {"(*Inst).MatchRune", Method, 0}, {"(*Inst).MatchRunePos", Method, 3}, {"(*Inst).String", Method, 0}, {"(*Prog).Prefix", Method, 0}, {"(*Prog).StartCond", Method, 0}, {"(*Prog).String", Method, 0}, {"(*Regexp).CapNames", Method, 0}, {"(*Regexp).Equal", Method, 0}, {"(*Regexp).MaxCap", Method, 0}, {"(*Regexp).Simplify", Method, 0}, {"(*Regexp).String", Method, 0}, {"(ErrorCode).String", Method, 0}, {"(InstOp).String", Method, 3}, {"(Op).String", Method, 11}, {"ClassNL", Const, 0}, {"Compile", Func, 0}, {"DotNL", Const, 0}, {"EmptyBeginLine", Const, 0}, {"EmptyBeginText", Const, 0}, {"EmptyEndLine", Const, 0}, {"EmptyEndText", Const, 0}, {"EmptyNoWordBoundary", Const, 0}, {"EmptyOp", Type, 0}, {"EmptyOpContext", Func, 0}, {"EmptyWordBoundary", Const, 0}, {"ErrInternalError", Const, 0}, {"ErrInvalidCharClass", Const, 0}, {"ErrInvalidCharRange", Const, 0}, {"ErrInvalidEscape", Const, 0}, {"ErrInvalidNamedCapture", Const, 0}, {"ErrInvalidPerlOp", Const, 0}, {"ErrInvalidRepeatOp", Const, 0}, {"ErrInvalidRepeatSize", Const, 0}, {"ErrInvalidUTF8", Const, 0}, {"ErrLarge", Const, 20}, {"ErrMissingBracket", Const, 0}, {"ErrMissingParen", Const, 0}, {"ErrMissingRepeatArgument", Const, 0}, {"ErrNestingDepth", Const, 19}, {"ErrTrailingBackslash", Const, 0}, {"ErrUnexpectedParen", Const, 1}, {"Error", Type, 0}, {"Error.Code", Field, 0}, {"Error.Expr", Field, 0}, {"ErrorCode", Type, 0}, {"Flags", Type, 0}, {"FoldCase", Const, 0}, {"Inst", Type, 0}, {"Inst.Arg", Field, 0}, {"Inst.Op", Field, 0}, {"Inst.Out", Field, 0}, {"Inst.Rune", Field, 0}, {"InstAlt", Const, 0}, {"InstAltMatch", Const, 0}, {"InstCapture", Const, 0}, {"InstEmptyWidth", Const, 0}, {"InstFail", Const, 0}, {"InstMatch", Const, 0}, {"InstNop", Const, 0}, {"InstOp", Type, 0}, {"InstRune", Const, 0}, {"InstRune1", Const, 0}, {"InstRuneAny", Const, 0}, {"InstRuneAnyNotNL", Const, 0}, {"IsWordChar", Func, 0}, {"Literal", Const, 0}, {"MatchNL", Const, 0}, {"NonGreedy", Const, 0}, {"OneLine", Const, 0}, {"Op", Type, 0}, {"OpAlternate", Const, 0}, {"OpAnyChar", Const, 0}, {"OpAnyCharNotNL", Const, 0}, {"OpBeginLine", Const, 0}, {"OpBeginText", Const, 0}, {"OpCapture", Const, 0}, {"OpCharClass", Const, 0}, {"OpConcat", Const, 0}, {"OpEmptyMatch", Const, 0}, {"OpEndLine", Const, 0}, {"OpEndText", Const, 0}, {"OpLiteral", Const, 0}, {"OpNoMatch", Const, 0}, {"OpNoWordBoundary", Const, 0}, {"OpPlus", Const, 0}, {"OpQuest", Const, 0}, {"OpRepeat", Const, 0}, {"OpStar", Const, 0}, {"OpWordBoundary", Const, 0}, {"POSIX", Const, 0}, {"Parse", Func, 0}, {"Perl", Const, 0}, {"PerlX", Const, 0}, {"Prog", Type, 0}, {"Prog.Inst", Field, 0}, {"Prog.NumCap", Field, 0}, {"Prog.Start", Field, 0}, {"Regexp", Type, 0}, {"Regexp.Cap", Field, 0}, {"Regexp.Flags", Field, 0}, {"Regexp.Max", Field, 0}, {"Regexp.Min", Field, 0}, {"Regexp.Name", Field, 0}, {"Regexp.Op", Field, 0}, {"Regexp.Rune", Field, 0}, {"Regexp.Rune0", Field, 0}, {"Regexp.Sub", Field, 0}, {"Regexp.Sub0", Field, 0}, {"Simple", Const, 0}, {"UnicodeGroups", Const, 0}, {"WasDollar", Const, 0}, }, "runtime": { {"(*BlockProfileRecord).Stack", Method, 1}, {"(*Frames).Next", Method, 7}, {"(*Func).Entry", Method, 0}, {"(*Func).FileLine", Method, 0}, {"(*Func).Name", Method, 0}, {"(*MemProfileRecord).InUseBytes", Method, 0}, {"(*MemProfileRecord).InUseObjects", Method, 0}, {"(*MemProfileRecord).Stack", Method, 0}, {"(*PanicNilError).Error", Method, 21}, {"(*PanicNilError).RuntimeError", Method, 21}, {"(*Pinner).Pin", Method, 21}, {"(*Pinner).Unpin", Method, 21}, {"(*StackRecord).Stack", Method, 0}, {"(*TypeAssertionError).Error", Method, 0}, {"(*TypeAssertionError).RuntimeError", Method, 0}, {"(Cleanup).Stop", Method, 24}, {"AddCleanup", Func, 24}, {"BlockProfile", Func, 1}, {"BlockProfileRecord", Type, 1}, {"BlockProfileRecord.Count", Field, 1}, {"BlockProfileRecord.Cycles", Field, 1}, {"BlockProfileRecord.StackRecord", Field, 1}, {"Breakpoint", Func, 0}, {"CPUProfile", Func, 0}, {"Caller", Func, 0}, {"Callers", Func, 0}, {"CallersFrames", Func, 7}, {"Cleanup", Type, 24}, {"Compiler", Const, 0}, {"Error", Type, 0}, {"Frame", Type, 7}, {"Frame.Entry", Field, 7}, {"Frame.File", Field, 7}, {"Frame.Func", Field, 7}, {"Frame.Function", Field, 7}, {"Frame.Line", Field, 7}, {"Frame.PC", Field, 7}, {"Frames", Type, 7}, {"Func", Type, 0}, {"FuncForPC", Func, 0}, {"GC", Func, 0}, {"GOARCH", Const, 0}, {"GOMAXPROCS", Func, 0}, {"GOOS", Const, 0}, {"GOROOT", Func, 0}, {"Goexit", Func, 0}, {"GoroutineProfile", Func, 0}, {"Gosched", Func, 0}, {"KeepAlive", Func, 7}, {"LockOSThread", Func, 0}, {"MemProfile", Func, 0}, {"MemProfileRate", Var, 0}, {"MemProfileRecord", Type, 0}, {"MemProfileRecord.AllocBytes", Field, 0}, {"MemProfileRecord.AllocObjects", Field, 0}, {"MemProfileRecord.FreeBytes", Field, 0}, {"MemProfileRecord.FreeObjects", Field, 0}, {"MemProfileRecord.Stack0", Field, 0}, {"MemStats", Type, 0}, {"MemStats.Alloc", Field, 0}, {"MemStats.BuckHashSys", Field, 0}, {"MemStats.BySize", Field, 0}, {"MemStats.DebugGC", Field, 0}, {"MemStats.EnableGC", Field, 0}, {"MemStats.Frees", Field, 0}, {"MemStats.GCCPUFraction", Field, 5}, {"MemStats.GCSys", Field, 2}, {"MemStats.HeapAlloc", Field, 0}, {"MemStats.HeapIdle", Field, 0}, {"MemStats.HeapInuse", Field, 0}, {"MemStats.HeapObjects", Field, 0}, {"MemStats.HeapReleased", Field, 0}, {"MemStats.HeapSys", Field, 0}, {"MemStats.LastGC", Field, 0}, {"MemStats.Lookups", Field, 0}, {"MemStats.MCacheInuse", Field, 0}, {"MemStats.MCacheSys", Field, 0}, {"MemStats.MSpanInuse", Field, 0}, {"MemStats.MSpanSys", Field, 0}, {"MemStats.Mallocs", Field, 0}, {"MemStats.NextGC", Field, 0}, {"MemStats.NumForcedGC", Field, 8}, {"MemStats.NumGC", Field, 0}, {"MemStats.OtherSys", Field, 2}, {"MemStats.PauseEnd", Field, 4}, {"MemStats.PauseNs", Field, 0}, {"MemStats.PauseTotalNs", Field, 0}, {"MemStats.StackInuse", Field, 0}, {"MemStats.StackSys", Field, 0}, {"MemStats.Sys", Field, 0}, {"MemStats.TotalAlloc", Field, 0}, {"MutexProfile", Func, 8}, {"NumCPU", Func, 0}, {"NumCgoCall", Func, 0}, {"NumGoroutine", Func, 0}, {"PanicNilError", Type, 21}, {"Pinner", Type, 21}, {"ReadMemStats", Func, 0}, {"ReadTrace", Func, 5}, {"SetBlockProfileRate", Func, 1}, {"SetCPUProfileRate", Func, 0}, {"SetCgoTraceback", Func, 7}, {"SetFinalizer", Func, 0}, {"SetMutexProfileFraction", Func, 8}, {"Stack", Func, 0}, {"StackRecord", Type, 0}, {"StackRecord.Stack0", Field, 0}, {"StartTrace", Func, 5}, {"StopTrace", Func, 5}, {"ThreadCreateProfile", Func, 0}, {"TypeAssertionError", Type, 0}, {"UnlockOSThread", Func, 0}, {"Version", Func, 0}, }, "runtime/cgo": { {"(Handle).Delete", Method, 17}, {"(Handle).Value", Method, 17}, {"Handle", Type, 17}, {"Incomplete", Type, 20}, {"NewHandle", Func, 17}, }, "runtime/coverage": { {"ClearCounters", Func, 20}, {"WriteCounters", Func, 20}, {"WriteCountersDir", Func, 20}, {"WriteMeta", Func, 20}, {"WriteMetaDir", Func, 20}, }, "runtime/debug": { {"(*BuildInfo).String", Method, 18}, {"BuildInfo", Type, 12}, {"BuildInfo.Deps", Field, 12}, {"BuildInfo.GoVersion", Field, 18}, {"BuildInfo.Main", Field, 12}, {"BuildInfo.Path", Field, 12}, {"BuildInfo.Settings", Field, 18}, {"BuildSetting", Type, 18}, {"BuildSetting.Key", Field, 18}, {"BuildSetting.Value", Field, 18}, {"CrashOptions", Type, 23}, {"FreeOSMemory", Func, 1}, {"GCStats", Type, 1}, {"GCStats.LastGC", Field, 1}, {"GCStats.NumGC", Field, 1}, {"GCStats.Pause", Field, 1}, {"GCStats.PauseEnd", Field, 4}, {"GCStats.PauseQuantiles", Field, 1}, {"GCStats.PauseTotal", Field, 1}, {"Module", Type, 12}, {"Module.Path", Field, 12}, {"Module.Replace", Field, 12}, {"Module.Sum", Field, 12}, {"Module.Version", Field, 12}, {"ParseBuildInfo", Func, 18}, {"PrintStack", Func, 0}, {"ReadBuildInfo", Func, 12}, {"ReadGCStats", Func, 1}, {"SetCrashOutput", Func, 23}, {"SetGCPercent", Func, 1}, {"SetMaxStack", Func, 2}, {"SetMaxThreads", Func, 2}, {"SetMemoryLimit", Func, 19}, {"SetPanicOnFault", Func, 3}, {"SetTraceback", Func, 6}, {"Stack", Func, 0}, {"WriteHeapDump", Func, 3}, }, "runtime/metrics": { {"(Value).Float64", Method, 16}, {"(Value).Float64Histogram", Method, 16}, {"(Value).Kind", Method, 16}, {"(Value).Uint64", Method, 16}, {"All", Func, 16}, {"Description", Type, 16}, {"Description.Cumulative", Field, 16}, {"Description.Description", Field, 16}, {"Description.Kind", Field, 16}, {"Description.Name", Field, 16}, {"Float64Histogram", Type, 16}, {"Float64Histogram.Buckets", Field, 16}, {"Float64Histogram.Counts", Field, 16}, {"KindBad", Const, 16}, {"KindFloat64", Const, 16}, {"KindFloat64Histogram", Const, 16}, {"KindUint64", Const, 16}, {"Read", Func, 16}, {"Sample", Type, 16}, {"Sample.Name", Field, 16}, {"Sample.Value", Field, 16}, {"Value", Type, 16}, {"ValueKind", Type, 16}, }, "runtime/pprof": { {"(*Profile).Add", Method, 0}, {"(*Profile).Count", Method, 0}, {"(*Profile).Name", Method, 0}, {"(*Profile).Remove", Method, 0}, {"(*Profile).WriteTo", Method, 0}, {"Do", Func, 9}, {"ForLabels", Func, 9}, {"Label", Func, 9}, {"LabelSet", Type, 9}, {"Labels", Func, 9}, {"Lookup", Func, 0}, {"NewProfile", Func, 0}, {"Profile", Type, 0}, {"Profiles", Func, 0}, {"SetGoroutineLabels", Func, 9}, {"StartCPUProfile", Func, 0}, {"StopCPUProfile", Func, 0}, {"WithLabels", Func, 9}, {"WriteHeapProfile", Func, 0}, }, "runtime/trace": { {"(*Region).End", Method, 11}, {"(*Task).End", Method, 11}, {"IsEnabled", Func, 11}, {"Log", Func, 11}, {"Logf", Func, 11}, {"NewTask", Func, 11}, {"Region", Type, 11}, {"Start", Func, 5}, {"StartRegion", Func, 11}, {"Stop", Func, 5}, {"Task", Type, 11}, {"WithRegion", Func, 11}, }, "slices": { {"All", Func, 23}, {"AppendSeq", Func, 23}, {"Backward", Func, 23}, {"BinarySearch", Func, 21}, {"BinarySearchFunc", Func, 21}, {"Chunk", Func, 23}, {"Clip", Func, 21}, {"Clone", Func, 21}, {"Collect", Func, 23}, {"Compact", Func, 21}, {"CompactFunc", Func, 21}, {"Compare", Func, 21}, {"CompareFunc", Func, 21}, {"Concat", Func, 22}, {"Contains", Func, 21}, {"ContainsFunc", Func, 21}, {"Delete", Func, 21}, {"DeleteFunc", Func, 21}, {"Equal", Func, 21}, {"EqualFunc", Func, 21}, {"Grow", Func, 21}, {"Index", Func, 21}, {"IndexFunc", Func, 21}, {"Insert", Func, 21}, {"IsSorted", Func, 21}, {"IsSortedFunc", Func, 21}, {"Max", Func, 21}, {"MaxFunc", Func, 21}, {"Min", Func, 21}, {"MinFunc", Func, 21}, {"Repeat", Func, 23}, {"Replace", Func, 21}, {"Reverse", Func, 21}, {"Sort", Func, 21}, {"SortFunc", Func, 21}, {"SortStableFunc", Func, 21}, {"Sorted", Func, 23}, {"SortedFunc", Func, 23}, {"SortedStableFunc", Func, 23}, {"Values", Func, 23}, }, "sort": { {"(Float64Slice).Len", Method, 0}, {"(Float64Slice).Less", Method, 0}, {"(Float64Slice).Search", Method, 0}, {"(Float64Slice).Sort", Method, 0}, {"(Float64Slice).Swap", Method, 0}, {"(IntSlice).Len", Method, 0}, {"(IntSlice).Less", Method, 0}, {"(IntSlice).Search", Method, 0}, {"(IntSlice).Sort", Method, 0}, {"(IntSlice).Swap", Method, 0}, {"(StringSlice).Len", Method, 0}, {"(StringSlice).Less", Method, 0}, {"(StringSlice).Search", Method, 0}, {"(StringSlice).Sort", Method, 0}, {"(StringSlice).Swap", Method, 0}, {"Find", Func, 19}, {"Float64Slice", Type, 0}, {"Float64s", Func, 0}, {"Float64sAreSorted", Func, 0}, {"IntSlice", Type, 0}, {"Interface", Type, 0}, {"Ints", Func, 0}, {"IntsAreSorted", Func, 0}, {"IsSorted", Func, 0}, {"Reverse", Func, 1}, {"Search", Func, 0}, {"SearchFloat64s", Func, 0}, {"SearchInts", Func, 0}, {"SearchStrings", Func, 0}, {"Slice", Func, 8}, {"SliceIsSorted", Func, 8}, {"SliceStable", Func, 8}, {"Sort", Func, 0}, {"Stable", Func, 2}, {"StringSlice", Type, 0}, {"Strings", Func, 0}, {"StringsAreSorted", Func, 0}, }, "strconv": { {"(*NumError).Error", Method, 0}, {"(*NumError).Unwrap", Method, 14}, {"AppendBool", Func, 0}, {"AppendFloat", Func, 0}, {"AppendInt", Func, 0}, {"AppendQuote", Func, 0}, {"AppendQuoteRune", Func, 0}, {"AppendQuoteRuneToASCII", Func, 0}, {"AppendQuoteRuneToGraphic", Func, 6}, {"AppendQuoteToASCII", Func, 0}, {"AppendQuoteToGraphic", Func, 6}, {"AppendUint", Func, 0}, {"Atoi", Func, 0}, {"CanBackquote", Func, 0}, {"ErrRange", Var, 0}, {"ErrSyntax", Var, 0}, {"FormatBool", Func, 0}, {"FormatComplex", Func, 15}, {"FormatFloat", Func, 0}, {"FormatInt", Func, 0}, {"FormatUint", Func, 0}, {"IntSize", Const, 0}, {"IsGraphic", Func, 6}, {"IsPrint", Func, 0}, {"Itoa", Func, 0}, {"NumError", Type, 0}, {"NumError.Err", Field, 0}, {"NumError.Func", Field, 0}, {"NumError.Num", Field, 0}, {"ParseBool", Func, 0}, {"ParseComplex", Func, 15}, {"ParseFloat", Func, 0}, {"ParseInt", Func, 0}, {"ParseUint", Func, 0}, {"Quote", Func, 0}, {"QuoteRune", Func, 0}, {"QuoteRuneToASCII", Func, 0}, {"QuoteRuneToGraphic", Func, 6}, {"QuoteToASCII", Func, 0}, {"QuoteToGraphic", Func, 6}, {"QuotedPrefix", Func, 17}, {"Unquote", Func, 0}, {"UnquoteChar", Func, 0}, }, "strings": { {"(*Builder).Cap", Method, 12}, {"(*Builder).Grow", Method, 10}, {"(*Builder).Len", Method, 10}, {"(*Builder).Reset", Method, 10}, {"(*Builder).String", Method, 10}, {"(*Builder).Write", Method, 10}, {"(*Builder).WriteByte", Method, 10}, {"(*Builder).WriteRune", Method, 10}, {"(*Builder).WriteString", Method, 10}, {"(*Reader).Len", Method, 0}, {"(*Reader).Read", Method, 0}, {"(*Reader).ReadAt", Method, 0}, {"(*Reader).ReadByte", Method, 0}, {"(*Reader).ReadRune", Method, 0}, {"(*Reader).Reset", Method, 7}, {"(*Reader).Seek", Method, 0}, {"(*Reader).Size", Method, 5}, {"(*Reader).UnreadByte", Method, 0}, {"(*Reader).UnreadRune", Method, 0}, {"(*Reader).WriteTo", Method, 1}, {"(*Replacer).Replace", Method, 0}, {"(*Replacer).WriteString", Method, 0}, {"Builder", Type, 10}, {"Clone", Func, 18}, {"Compare", Func, 5}, {"Contains", Func, 0}, {"ContainsAny", Func, 0}, {"ContainsFunc", Func, 21}, {"ContainsRune", Func, 0}, {"Count", Func, 0}, {"Cut", Func, 18}, {"CutPrefix", Func, 20}, {"CutSuffix", Func, 20}, {"EqualFold", Func, 0}, {"Fields", Func, 0}, {"FieldsFunc", Func, 0}, {"FieldsFuncSeq", Func, 24}, {"FieldsSeq", Func, 24}, {"HasPrefix", Func, 0}, {"HasSuffix", Func, 0}, {"Index", Func, 0}, {"IndexAny", Func, 0}, {"IndexByte", Func, 2}, {"IndexFunc", Func, 0}, {"IndexRune", Func, 0}, {"Join", Func, 0}, {"LastIndex", Func, 0}, {"LastIndexAny", Func, 0}, {"LastIndexByte", Func, 5}, {"LastIndexFunc", Func, 0}, {"Lines", Func, 24}, {"Map", Func, 0}, {"NewReader", Func, 0}, {"NewReplacer", Func, 0}, {"Reader", Type, 0}, {"Repeat", Func, 0}, {"Replace", Func, 0}, {"ReplaceAll", Func, 12}, {"Replacer", Type, 0}, {"Split", Func, 0}, {"SplitAfter", Func, 0}, {"SplitAfterN", Func, 0}, {"SplitAfterSeq", Func, 24}, {"SplitN", Func, 0}, {"SplitSeq", Func, 24}, {"Title", Func, 0}, {"ToLower", Func, 0}, {"ToLowerSpecial", Func, 0}, {"ToTitle", Func, 0}, {"ToTitleSpecial", Func, 0}, {"ToUpper", Func, 0}, {"ToUpperSpecial", Func, 0}, {"ToValidUTF8", Func, 13}, {"Trim", Func, 0}, {"TrimFunc", Func, 0}, {"TrimLeft", Func, 0}, {"TrimLeftFunc", Func, 0}, {"TrimPrefix", Func, 1}, {"TrimRight", Func, 0}, {"TrimRightFunc", Func, 0}, {"TrimSpace", Func, 0}, {"TrimSuffix", Func, 1}, }, "structs": { {"HostLayout", Type, 23}, }, "sync": { {"(*Cond).Broadcast", Method, 0}, {"(*Cond).Signal", Method, 0}, {"(*Cond).Wait", Method, 0}, {"(*Map).Clear", Method, 23}, {"(*Map).CompareAndDelete", Method, 20}, {"(*Map).CompareAndSwap", Method, 20}, {"(*Map).Delete", Method, 9}, {"(*Map).Load", Method, 9}, {"(*Map).LoadAndDelete", Method, 15}, {"(*Map).LoadOrStore", Method, 9}, {"(*Map).Range", Method, 9}, {"(*Map).Store", Method, 9}, {"(*Map).Swap", Method, 20}, {"(*Mutex).Lock", Method, 0}, {"(*Mutex).TryLock", Method, 18}, {"(*Mutex).Unlock", Method, 0}, {"(*Once).Do", Method, 0}, {"(*Pool).Get", Method, 3}, {"(*Pool).Put", Method, 3}, {"(*RWMutex).Lock", Method, 0}, {"(*RWMutex).RLock", Method, 0}, {"(*RWMutex).RLocker", Method, 0}, {"(*RWMutex).RUnlock", Method, 0}, {"(*RWMutex).TryLock", Method, 18}, {"(*RWMutex).TryRLock", Method, 18}, {"(*RWMutex).Unlock", Method, 0}, {"(*WaitGroup).Add", Method, 0}, {"(*WaitGroup).Done", Method, 0}, {"(*WaitGroup).Go", Method, 25}, {"(*WaitGroup).Wait", Method, 0}, {"Cond", Type, 0}, {"Cond.L", Field, 0}, {"Locker", Type, 0}, {"Map", Type, 9}, {"Mutex", Type, 0}, {"NewCond", Func, 0}, {"Once", Type, 0}, {"OnceFunc", Func, 21}, {"OnceValue", Func, 21}, {"OnceValues", Func, 21}, {"Pool", Type, 3}, {"Pool.New", Field, 3}, {"RWMutex", Type, 0}, {"WaitGroup", Type, 0}, }, "sync/atomic": { {"(*Bool).CompareAndSwap", Method, 19}, {"(*Bool).Load", Method, 19}, {"(*Bool).Store", Method, 19}, {"(*Bool).Swap", Method, 19}, {"(*Int32).Add", Method, 19}, {"(*Int32).And", Method, 23}, {"(*Int32).CompareAndSwap", Method, 19}, {"(*Int32).Load", Method, 19}, {"(*Int32).Or", Method, 23}, {"(*Int32).Store", Method, 19}, {"(*Int32).Swap", Method, 19}, {"(*Int64).Add", Method, 19}, {"(*Int64).And", Method, 23}, {"(*Int64).CompareAndSwap", Method, 19}, {"(*Int64).Load", Method, 19}, {"(*Int64).Or", Method, 23}, {"(*Int64).Store", Method, 19}, {"(*Int64).Swap", Method, 19}, {"(*Pointer).CompareAndSwap", Method, 19}, {"(*Pointer).Load", Method, 19}, {"(*Pointer).Store", Method, 19}, {"(*Pointer).Swap", Method, 19}, {"(*Uint32).Add", Method, 19}, {"(*Uint32).And", Method, 23}, {"(*Uint32).CompareAndSwap", Method, 19}, {"(*Uint32).Load", Method, 19}, {"(*Uint32).Or", Method, 23}, {"(*Uint32).Store", Method, 19}, {"(*Uint32).Swap", Method, 19}, {"(*Uint64).Add", Method, 19}, {"(*Uint64).And", Method, 23}, {"(*Uint64).CompareAndSwap", Method, 19}, {"(*Uint64).Load", Method, 19}, {"(*Uint64).Or", Method, 23}, {"(*Uint64).Store", Method, 19}, {"(*Uint64).Swap", Method, 19}, {"(*Uintptr).Add", Method, 19}, {"(*Uintptr).And", Method, 23}, {"(*Uintptr).CompareAndSwap", Method, 19}, {"(*Uintptr).Load", Method, 19}, {"(*Uintptr).Or", Method, 23}, {"(*Uintptr).Store", Method, 19}, {"(*Uintptr).Swap", Method, 19}, {"(*Value).CompareAndSwap", Method, 17}, {"(*Value).Load", Method, 4}, {"(*Value).Store", Method, 4}, {"(*Value).Swap", Method, 17}, {"AddInt32", Func, 0}, {"AddInt64", Func, 0}, {"AddUint32", Func, 0}, {"AddUint64", Func, 0}, {"AddUintptr", Func, 0}, {"AndInt32", Func, 23}, {"AndInt64", Func, 23}, {"AndUint32", Func, 23}, {"AndUint64", Func, 23}, {"AndUintptr", Func, 23}, {"Bool", Type, 19}, {"CompareAndSwapInt32", Func, 0}, {"CompareAndSwapInt64", Func, 0}, {"CompareAndSwapPointer", Func, 0}, {"CompareAndSwapUint32", Func, 0}, {"CompareAndSwapUint64", Func, 0}, {"CompareAndSwapUintptr", Func, 0}, {"Int32", Type, 19}, {"Int64", Type, 19}, {"LoadInt32", Func, 0}, {"LoadInt64", Func, 0}, {"LoadPointer", Func, 0}, {"LoadUint32", Func, 0}, {"LoadUint64", Func, 0}, {"LoadUintptr", Func, 0}, {"OrInt32", Func, 23}, {"OrInt64", Func, 23}, {"OrUint32", Func, 23}, {"OrUint64", Func, 23}, {"OrUintptr", Func, 23}, {"Pointer", Type, 19}, {"StoreInt32", Func, 0}, {"StoreInt64", Func, 0}, {"StorePointer", Func, 0}, {"StoreUint32", Func, 0}, {"StoreUint64", Func, 0}, {"StoreUintptr", Func, 0}, {"SwapInt32", Func, 2}, {"SwapInt64", Func, 2}, {"SwapPointer", Func, 2}, {"SwapUint32", Func, 2}, {"SwapUint64", Func, 2}, {"SwapUintptr", Func, 2}, {"Uint32", Type, 19}, {"Uint64", Type, 19}, {"Uintptr", Type, 19}, {"Value", Type, 4}, }, "syscall": { {"(*Cmsghdr).SetLen", Method, 0}, {"(*DLL).FindProc", Method, 0}, {"(*DLL).MustFindProc", Method, 0}, {"(*DLL).Release", Method, 0}, {"(*DLLError).Error", Method, 0}, {"(*DLLError).Unwrap", Method, 16}, {"(*Filetime).Nanoseconds", Method, 0}, {"(*Iovec).SetLen", Method, 0}, {"(*LazyDLL).Handle", Method, 0}, {"(*LazyDLL).Load", Method, 0}, {"(*LazyDLL).NewProc", Method, 0}, {"(*LazyProc).Addr", Method, 0}, {"(*LazyProc).Call", Method, 0}, {"(*LazyProc).Find", Method, 0}, {"(*Msghdr).SetControllen", Method, 0}, {"(*Proc).Addr", Method, 0}, {"(*Proc).Call", Method, 0}, {"(*PtraceRegs).PC", Method, 0}, {"(*PtraceRegs).SetPC", Method, 0}, {"(*RawSockaddrAny).Sockaddr", Method, 0}, {"(*SID).Copy", Method, 0}, {"(*SID).Len", Method, 0}, {"(*SID).LookupAccount", Method, 0}, {"(*SID).String", Method, 0}, {"(*Timespec).Nano", Method, 0}, {"(*Timespec).Unix", Method, 0}, {"(*Timeval).Nano", Method, 0}, {"(*Timeval).Nanoseconds", Method, 0}, {"(*Timeval).Unix", Method, 0}, {"(Errno).Error", Method, 0}, {"(Errno).Is", Method, 13}, {"(Errno).Temporary", Method, 0}, {"(Errno).Timeout", Method, 0}, {"(Signal).Signal", Method, 0}, {"(Signal).String", Method, 0}, {"(Token).Close", Method, 0}, {"(Token).GetTokenPrimaryGroup", Method, 0}, {"(Token).GetTokenUser", Method, 0}, {"(Token).GetUserProfileDirectory", Method, 0}, {"(WaitStatus).Continued", Method, 0}, {"(WaitStatus).CoreDump", Method, 0}, {"(WaitStatus).ExitStatus", Method, 0}, {"(WaitStatus).Exited", Method, 0}, {"(WaitStatus).Signal", Method, 0}, {"(WaitStatus).Signaled", Method, 0}, {"(WaitStatus).StopSignal", Method, 0}, {"(WaitStatus).Stopped", Method, 0}, {"(WaitStatus).TrapCause", Method, 0}, {"AF_ALG", Const, 0}, {"AF_APPLETALK", Const, 0}, {"AF_ARP", Const, 0}, {"AF_ASH", Const, 0}, {"AF_ATM", Const, 0}, {"AF_ATMPVC", Const, 0}, {"AF_ATMSVC", Const, 0}, {"AF_AX25", Const, 0}, {"AF_BLUETOOTH", Const, 0}, {"AF_BRIDGE", Const, 0}, {"AF_CAIF", Const, 0}, {"AF_CAN", Const, 0}, {"AF_CCITT", Const, 0}, {"AF_CHAOS", Const, 0}, {"AF_CNT", Const, 0}, {"AF_COIP", Const, 0}, {"AF_DATAKIT", Const, 0}, {"AF_DECnet", Const, 0}, {"AF_DLI", Const, 0}, {"AF_E164", Const, 0}, {"AF_ECMA", Const, 0}, {"AF_ECONET", Const, 0}, {"AF_ENCAP", Const, 1}, {"AF_FILE", Const, 0}, {"AF_HYLINK", Const, 0}, {"AF_IEEE80211", Const, 0}, {"AF_IEEE802154", Const, 0}, {"AF_IMPLINK", Const, 0}, {"AF_INET", Const, 0}, {"AF_INET6", Const, 0}, {"AF_INET6_SDP", Const, 3}, {"AF_INET_SDP", Const, 3}, {"AF_IPX", Const, 0}, {"AF_IRDA", Const, 0}, {"AF_ISDN", Const, 0}, {"AF_ISO", Const, 0}, {"AF_IUCV", Const, 0}, {"AF_KEY", Const, 0}, {"AF_LAT", Const, 0}, {"AF_LINK", Const, 0}, {"AF_LLC", Const, 0}, {"AF_LOCAL", Const, 0}, {"AF_MAX", Const, 0}, {"AF_MPLS", Const, 1}, {"AF_NATM", Const, 0}, {"AF_NDRV", Const, 0}, {"AF_NETBEUI", Const, 0}, {"AF_NETBIOS", Const, 0}, {"AF_NETGRAPH", Const, 0}, {"AF_NETLINK", Const, 0}, {"AF_NETROM", Const, 0}, {"AF_NS", Const, 0}, {"AF_OROUTE", Const, 1}, {"AF_OSI", Const, 0}, {"AF_PACKET", Const, 0}, {"AF_PHONET", Const, 0}, {"AF_PPP", Const, 0}, {"AF_PPPOX", Const, 0}, {"AF_PUP", Const, 0}, {"AF_RDS", Const, 0}, {"AF_RESERVED_36", Const, 0}, {"AF_ROSE", Const, 0}, {"AF_ROUTE", Const, 0}, {"AF_RXRPC", Const, 0}, {"AF_SCLUSTER", Const, 0}, {"AF_SECURITY", Const, 0}, {"AF_SIP", Const, 0}, {"AF_SLOW", Const, 0}, {"AF_SNA", Const, 0}, {"AF_SYSTEM", Const, 0}, {"AF_TIPC", Const, 0}, {"AF_UNIX", Const, 0}, {"AF_UNSPEC", Const, 0}, {"AF_UTUN", Const, 16}, {"AF_VENDOR00", Const, 0}, {"AF_VENDOR01", Const, 0}, {"AF_VENDOR02", Const, 0}, {"AF_VENDOR03", Const, 0}, {"AF_VENDOR04", Const, 0}, {"AF_VENDOR05", Const, 0}, {"AF_VENDOR06", Const, 0}, {"AF_VENDOR07", Const, 0}, {"AF_VENDOR08", Const, 0}, {"AF_VENDOR09", Const, 0}, {"AF_VENDOR10", Const, 0}, {"AF_VENDOR11", Const, 0}, {"AF_VENDOR12", Const, 0}, {"AF_VENDOR13", Const, 0}, {"AF_VENDOR14", Const, 0}, {"AF_VENDOR15", Const, 0}, {"AF_VENDOR16", Const, 0}, {"AF_VENDOR17", Const, 0}, {"AF_VENDOR18", Const, 0}, {"AF_VENDOR19", Const, 0}, {"AF_VENDOR20", Const, 0}, {"AF_VENDOR21", Const, 0}, {"AF_VENDOR22", Const, 0}, {"AF_VENDOR23", Const, 0}, {"AF_VENDOR24", Const, 0}, {"AF_VENDOR25", Const, 0}, {"AF_VENDOR26", Const, 0}, {"AF_VENDOR27", Const, 0}, {"AF_VENDOR28", Const, 0}, {"AF_VENDOR29", Const, 0}, {"AF_VENDOR30", Const, 0}, {"AF_VENDOR31", Const, 0}, {"AF_VENDOR32", Const, 0}, {"AF_VENDOR33", Const, 0}, {"AF_VENDOR34", Const, 0}, {"AF_VENDOR35", Const, 0}, {"AF_VENDOR36", Const, 0}, {"AF_VENDOR37", Const, 0}, {"AF_VENDOR38", Const, 0}, {"AF_VENDOR39", Const, 0}, {"AF_VENDOR40", Const, 0}, {"AF_VENDOR41", Const, 0}, {"AF_VENDOR42", Const, 0}, {"AF_VENDOR43", Const, 0}, {"AF_VENDOR44", Const, 0}, {"AF_VENDOR45", Const, 0}, {"AF_VENDOR46", Const, 0}, {"AF_VENDOR47", Const, 0}, {"AF_WANPIPE", Const, 0}, {"AF_X25", Const, 0}, {"AI_CANONNAME", Const, 1}, {"AI_NUMERICHOST", Const, 1}, {"AI_PASSIVE", Const, 1}, {"APPLICATION_ERROR", Const, 0}, {"ARPHRD_ADAPT", Const, 0}, {"ARPHRD_APPLETLK", Const, 0}, {"ARPHRD_ARCNET", Const, 0}, {"ARPHRD_ASH", Const, 0}, {"ARPHRD_ATM", Const, 0}, {"ARPHRD_AX25", Const, 0}, {"ARPHRD_BIF", Const, 0}, {"ARPHRD_CHAOS", Const, 0}, {"ARPHRD_CISCO", Const, 0}, {"ARPHRD_CSLIP", Const, 0}, {"ARPHRD_CSLIP6", Const, 0}, {"ARPHRD_DDCMP", Const, 0}, {"ARPHRD_DLCI", Const, 0}, {"ARPHRD_ECONET", Const, 0}, {"ARPHRD_EETHER", Const, 0}, {"ARPHRD_ETHER", Const, 0}, {"ARPHRD_EUI64", Const, 0}, {"ARPHRD_FCAL", Const, 0}, {"ARPHRD_FCFABRIC", Const, 0}, {"ARPHRD_FCPL", Const, 0}, {"ARPHRD_FCPP", Const, 0}, {"ARPHRD_FDDI", Const, 0}, {"ARPHRD_FRAD", Const, 0}, {"ARPHRD_FRELAY", Const, 1}, {"ARPHRD_HDLC", Const, 0}, {"ARPHRD_HIPPI", Const, 0}, {"ARPHRD_HWX25", Const, 0}, {"ARPHRD_IEEE1394", Const, 0}, {"ARPHRD_IEEE802", Const, 0}, {"ARPHRD_IEEE80211", Const, 0}, {"ARPHRD_IEEE80211_PRISM", Const, 0}, {"ARPHRD_IEEE80211_RADIOTAP", Const, 0}, {"ARPHRD_IEEE802154", Const, 0}, {"ARPHRD_IEEE802154_PHY", Const, 0}, {"ARPHRD_IEEE802_TR", Const, 0}, {"ARPHRD_INFINIBAND", Const, 0}, {"ARPHRD_IPDDP", Const, 0}, {"ARPHRD_IPGRE", Const, 0}, {"ARPHRD_IRDA", Const, 0}, {"ARPHRD_LAPB", Const, 0}, {"ARPHRD_LOCALTLK", Const, 0}, {"ARPHRD_LOOPBACK", Const, 0}, {"ARPHRD_METRICOM", Const, 0}, {"ARPHRD_NETROM", Const, 0}, {"ARPHRD_NONE", Const, 0}, {"ARPHRD_PIMREG", Const, 0}, {"ARPHRD_PPP", Const, 0}, {"ARPHRD_PRONET", Const, 0}, {"ARPHRD_RAWHDLC", Const, 0}, {"ARPHRD_ROSE", Const, 0}, {"ARPHRD_RSRVD", Const, 0}, {"ARPHRD_SIT", Const, 0}, {"ARPHRD_SKIP", Const, 0}, {"ARPHRD_SLIP", Const, 0}, {"ARPHRD_SLIP6", Const, 0}, {"ARPHRD_STRIP", Const, 1}, {"ARPHRD_TUNNEL", Const, 0}, {"ARPHRD_TUNNEL6", Const, 0}, {"ARPHRD_VOID", Const, 0}, {"ARPHRD_X25", Const, 0}, {"AUTHTYPE_CLIENT", Const, 0}, {"AUTHTYPE_SERVER", Const, 0}, {"Accept", Func, 0}, {"Accept4", Func, 1}, {"AcceptEx", Func, 0}, {"Access", Func, 0}, {"Acct", Func, 0}, {"AddrinfoW", Type, 1}, {"AddrinfoW.Addr", Field, 1}, {"AddrinfoW.Addrlen", Field, 1}, {"AddrinfoW.Canonname", Field, 1}, {"AddrinfoW.Family", Field, 1}, {"AddrinfoW.Flags", Field, 1}, {"AddrinfoW.Next", Field, 1}, {"AddrinfoW.Protocol", Field, 1}, {"AddrinfoW.Socktype", Field, 1}, {"Adjtime", Func, 0}, {"Adjtimex", Func, 0}, {"AllThreadsSyscall", Func, 16}, {"AllThreadsSyscall6", Func, 16}, {"AttachLsf", Func, 0}, {"B0", Const, 0}, {"B1000000", Const, 0}, {"B110", Const, 0}, {"B115200", Const, 0}, {"B1152000", Const, 0}, {"B1200", Const, 0}, {"B134", Const, 0}, {"B14400", Const, 1}, {"B150", Const, 0}, {"B1500000", Const, 0}, {"B1800", Const, 0}, {"B19200", Const, 0}, {"B200", Const, 0}, {"B2000000", Const, 0}, {"B230400", Const, 0}, {"B2400", Const, 0}, {"B2500000", Const, 0}, {"B28800", Const, 1}, {"B300", Const, 0}, {"B3000000", Const, 0}, {"B3500000", Const, 0}, {"B38400", Const, 0}, {"B4000000", Const, 0}, {"B460800", Const, 0}, {"B4800", Const, 0}, {"B50", Const, 0}, {"B500000", Const, 0}, {"B57600", Const, 0}, {"B576000", Const, 0}, {"B600", Const, 0}, {"B7200", Const, 1}, {"B75", Const, 0}, {"B76800", Const, 1}, {"B921600", Const, 0}, {"B9600", Const, 0}, {"BASE_PROTOCOL", Const, 2}, {"BIOCFEEDBACK", Const, 0}, {"BIOCFLUSH", Const, 0}, {"BIOCGBLEN", Const, 0}, {"BIOCGDIRECTION", Const, 0}, {"BIOCGDIRFILT", Const, 1}, {"BIOCGDLT", Const, 0}, {"BIOCGDLTLIST", Const, 0}, {"BIOCGETBUFMODE", Const, 0}, {"BIOCGETIF", Const, 0}, {"BIOCGETZMAX", Const, 0}, {"BIOCGFEEDBACK", Const, 1}, {"BIOCGFILDROP", Const, 1}, {"BIOCGHDRCMPLT", Const, 0}, {"BIOCGRSIG", Const, 0}, {"BIOCGRTIMEOUT", Const, 0}, {"BIOCGSEESENT", Const, 0}, {"BIOCGSTATS", Const, 0}, {"BIOCGSTATSOLD", Const, 1}, {"BIOCGTSTAMP", Const, 1}, {"BIOCIMMEDIATE", Const, 0}, {"BIOCLOCK", Const, 0}, {"BIOCPROMISC", Const, 0}, {"BIOCROTZBUF", Const, 0}, {"BIOCSBLEN", Const, 0}, {"BIOCSDIRECTION", Const, 0}, {"BIOCSDIRFILT", Const, 1}, {"BIOCSDLT", Const, 0}, {"BIOCSETBUFMODE", Const, 0}, {"BIOCSETF", Const, 0}, {"BIOCSETFNR", Const, 0}, {"BIOCSETIF", Const, 0}, {"BIOCSETWF", Const, 0}, {"BIOCSETZBUF", Const, 0}, {"BIOCSFEEDBACK", Const, 1}, {"BIOCSFILDROP", Const, 1}, {"BIOCSHDRCMPLT", Const, 0}, {"BIOCSRSIG", Const, 0}, {"BIOCSRTIMEOUT", Const, 0}, {"BIOCSSEESENT", Const, 0}, {"BIOCSTCPF", Const, 1}, {"BIOCSTSTAMP", Const, 1}, {"BIOCSUDPF", Const, 1}, {"BIOCVERSION", Const, 0}, {"BPF_A", Const, 0}, {"BPF_ABS", Const, 0}, {"BPF_ADD", Const, 0}, {"BPF_ALIGNMENT", Const, 0}, {"BPF_ALIGNMENT32", Const, 1}, {"BPF_ALU", Const, 0}, {"BPF_AND", Const, 0}, {"BPF_B", Const, 0}, {"BPF_BUFMODE_BUFFER", Const, 0}, {"BPF_BUFMODE_ZBUF", Const, 0}, {"BPF_DFLTBUFSIZE", Const, 1}, {"BPF_DIRECTION_IN", Const, 1}, {"BPF_DIRECTION_OUT", Const, 1}, {"BPF_DIV", Const, 0}, {"BPF_H", Const, 0}, {"BPF_IMM", Const, 0}, {"BPF_IND", Const, 0}, {"BPF_JA", Const, 0}, {"BPF_JEQ", Const, 0}, {"BPF_JGE", Const, 0}, {"BPF_JGT", Const, 0}, {"BPF_JMP", Const, 0}, {"BPF_JSET", Const, 0}, {"BPF_K", Const, 0}, {"BPF_LD", Const, 0}, {"BPF_LDX", Const, 0}, {"BPF_LEN", Const, 0}, {"BPF_LSH", Const, 0}, {"BPF_MAJOR_VERSION", Const, 0}, {"BPF_MAXBUFSIZE", Const, 0}, {"BPF_MAXINSNS", Const, 0}, {"BPF_MEM", Const, 0}, {"BPF_MEMWORDS", Const, 0}, {"BPF_MINBUFSIZE", Const, 0}, {"BPF_MINOR_VERSION", Const, 0}, {"BPF_MISC", Const, 0}, {"BPF_MSH", Const, 0}, {"BPF_MUL", Const, 0}, {"BPF_NEG", Const, 0}, {"BPF_OR", Const, 0}, {"BPF_RELEASE", Const, 0}, {"BPF_RET", Const, 0}, {"BPF_RSH", Const, 0}, {"BPF_ST", Const, 0}, {"BPF_STX", Const, 0}, {"BPF_SUB", Const, 0}, {"BPF_TAX", Const, 0}, {"BPF_TXA", Const, 0}, {"BPF_T_BINTIME", Const, 1}, {"BPF_T_BINTIME_FAST", Const, 1}, {"BPF_T_BINTIME_MONOTONIC", Const, 1}, {"BPF_T_BINTIME_MONOTONIC_FAST", Const, 1}, {"BPF_T_FAST", Const, 1}, {"BPF_T_FLAG_MASK", Const, 1}, {"BPF_T_FORMAT_MASK", Const, 1}, {"BPF_T_MICROTIME", Const, 1}, {"BPF_T_MICROTIME_FAST", Const, 1}, {"BPF_T_MICROTIME_MONOTONIC", Const, 1}, {"BPF_T_MICROTIME_MONOTONIC_FAST", Const, 1}, {"BPF_T_MONOTONIC", Const, 1}, {"BPF_T_MONOTONIC_FAST", Const, 1}, {"BPF_T_NANOTIME", Const, 1}, {"BPF_T_NANOTIME_FAST", Const, 1}, {"BPF_T_NANOTIME_MONOTONIC", Const, 1}, {"BPF_T_NANOTIME_MONOTONIC_FAST", Const, 1}, {"BPF_T_NONE", Const, 1}, {"BPF_T_NORMAL", Const, 1}, {"BPF_W", Const, 0}, {"BPF_X", Const, 0}, {"BRKINT", Const, 0}, {"Bind", Func, 0}, {"BindToDevice", Func, 0}, {"BpfBuflen", Func, 0}, {"BpfDatalink", Func, 0}, {"BpfHdr", Type, 0}, {"BpfHdr.Caplen", Field, 0}, {"BpfHdr.Datalen", Field, 0}, {"BpfHdr.Hdrlen", Field, 0}, {"BpfHdr.Pad_cgo_0", Field, 0}, {"BpfHdr.Tstamp", Field, 0}, {"BpfHeadercmpl", Func, 0}, {"BpfInsn", Type, 0}, {"BpfInsn.Code", Field, 0}, {"BpfInsn.Jf", Field, 0}, {"BpfInsn.Jt", Field, 0}, {"BpfInsn.K", Field, 0}, {"BpfInterface", Func, 0}, {"BpfJump", Func, 0}, {"BpfProgram", Type, 0}, {"BpfProgram.Insns", Field, 0}, {"BpfProgram.Len", Field, 0}, {"BpfProgram.Pad_cgo_0", Field, 0}, {"BpfStat", Type, 0}, {"BpfStat.Capt", Field, 2}, {"BpfStat.Drop", Field, 0}, {"BpfStat.Padding", Field, 2}, {"BpfStat.Recv", Field, 0}, {"BpfStats", Func, 0}, {"BpfStmt", Func, 0}, {"BpfTimeout", Func, 0}, {"BpfTimeval", Type, 2}, {"BpfTimeval.Sec", Field, 2}, {"BpfTimeval.Usec", Field, 2}, {"BpfVersion", Type, 0}, {"BpfVersion.Major", Field, 0}, {"BpfVersion.Minor", Field, 0}, {"BpfZbuf", Type, 0}, {"BpfZbuf.Bufa", Field, 0}, {"BpfZbuf.Bufb", Field, 0}, {"BpfZbuf.Buflen", Field, 0}, {"BpfZbufHeader", Type, 0}, {"BpfZbufHeader.Kernel_gen", Field, 0}, {"BpfZbufHeader.Kernel_len", Field, 0}, {"BpfZbufHeader.User_gen", Field, 0}, {"BpfZbufHeader.X_bzh_pad", Field, 0}, {"ByHandleFileInformation", Type, 0}, {"ByHandleFileInformation.CreationTime", Field, 0}, {"ByHandleFileInformation.FileAttributes", Field, 0}, {"ByHandleFileInformation.FileIndexHigh", Field, 0}, {"ByHandleFileInformation.FileIndexLow", Field, 0}, {"ByHandleFileInformation.FileSizeHigh", Field, 0}, {"ByHandleFileInformation.FileSizeLow", Field, 0}, {"ByHandleFileInformation.LastAccessTime", Field, 0}, {"ByHandleFileInformation.LastWriteTime", Field, 0}, {"ByHandleFileInformation.NumberOfLinks", Field, 0}, {"ByHandleFileInformation.VolumeSerialNumber", Field, 0}, {"BytePtrFromString", Func, 1}, {"ByteSliceFromString", Func, 1}, {"CCR0_FLUSH", Const, 1}, {"CERT_CHAIN_POLICY_AUTHENTICODE", Const, 0}, {"CERT_CHAIN_POLICY_AUTHENTICODE_TS", Const, 0}, {"CERT_CHAIN_POLICY_BASE", Const, 0}, {"CERT_CHAIN_POLICY_BASIC_CONSTRAINTS", Const, 0}, {"CERT_CHAIN_POLICY_EV", Const, 0}, {"CERT_CHAIN_POLICY_MICROSOFT_ROOT", Const, 0}, {"CERT_CHAIN_POLICY_NT_AUTH", Const, 0}, {"CERT_CHAIN_POLICY_SSL", Const, 0}, {"CERT_E_CN_NO_MATCH", Const, 0}, {"CERT_E_EXPIRED", Const, 0}, {"CERT_E_PURPOSE", Const, 0}, {"CERT_E_ROLE", Const, 0}, {"CERT_E_UNTRUSTEDROOT", Const, 0}, {"CERT_STORE_ADD_ALWAYS", Const, 0}, {"CERT_STORE_DEFER_CLOSE_UNTIL_LAST_FREE_FLAG", Const, 0}, {"CERT_STORE_PROV_MEMORY", Const, 0}, {"CERT_TRUST_HAS_EXCLUDED_NAME_CONSTRAINT", Const, 0}, {"CERT_TRUST_HAS_NOT_DEFINED_NAME_CONSTRAINT", Const, 0}, {"CERT_TRUST_HAS_NOT_PERMITTED_NAME_CONSTRAINT", Const, 0}, {"CERT_TRUST_HAS_NOT_SUPPORTED_CRITICAL_EXT", Const, 0}, {"CERT_TRUST_HAS_NOT_SUPPORTED_NAME_CONSTRAINT", Const, 0}, {"CERT_TRUST_INVALID_BASIC_CONSTRAINTS", Const, 0}, {"CERT_TRUST_INVALID_EXTENSION", Const, 0}, {"CERT_TRUST_INVALID_NAME_CONSTRAINTS", Const, 0}, {"CERT_TRUST_INVALID_POLICY_CONSTRAINTS", Const, 0}, {"CERT_TRUST_IS_CYCLIC", Const, 0}, {"CERT_TRUST_IS_EXPLICIT_DISTRUST", Const, 0}, {"CERT_TRUST_IS_NOT_SIGNATURE_VALID", Const, 0}, {"CERT_TRUST_IS_NOT_TIME_VALID", Const, 0}, {"CERT_TRUST_IS_NOT_VALID_FOR_USAGE", Const, 0}, {"CERT_TRUST_IS_OFFLINE_REVOCATION", Const, 0}, {"CERT_TRUST_IS_REVOKED", Const, 0}, {"CERT_TRUST_IS_UNTRUSTED_ROOT", Const, 0}, {"CERT_TRUST_NO_ERROR", Const, 0}, {"CERT_TRUST_NO_ISSUANCE_CHAIN_POLICY", Const, 0}, {"CERT_TRUST_REVOCATION_STATUS_UNKNOWN", Const, 0}, {"CFLUSH", Const, 1}, {"CLOCAL", Const, 0}, {"CLONE_CHILD_CLEARTID", Const, 2}, {"CLONE_CHILD_SETTID", Const, 2}, {"CLONE_CLEAR_SIGHAND", Const, 20}, {"CLONE_CSIGNAL", Const, 3}, {"CLONE_DETACHED", Const, 2}, {"CLONE_FILES", Const, 2}, {"CLONE_FS", Const, 2}, {"CLONE_INTO_CGROUP", Const, 20}, {"CLONE_IO", Const, 2}, {"CLONE_NEWCGROUP", Const, 20}, {"CLONE_NEWIPC", Const, 2}, {"CLONE_NEWNET", Const, 2}, {"CLONE_NEWNS", Const, 2}, {"CLONE_NEWPID", Const, 2}, {"CLONE_NEWTIME", Const, 20}, {"CLONE_NEWUSER", Const, 2}, {"CLONE_NEWUTS", Const, 2}, {"CLONE_PARENT", Const, 2}, {"CLONE_PARENT_SETTID", Const, 2}, {"CLONE_PID", Const, 3}, {"CLONE_PIDFD", Const, 20}, {"CLONE_PTRACE", Const, 2}, {"CLONE_SETTLS", Const, 2}, {"CLONE_SIGHAND", Const, 2}, {"CLONE_SYSVSEM", Const, 2}, {"CLONE_THREAD", Const, 2}, {"CLONE_UNTRACED", Const, 2}, {"CLONE_VFORK", Const, 2}, {"CLONE_VM", Const, 2}, {"CPUID_CFLUSH", Const, 1}, {"CREAD", Const, 0}, {"CREATE_ALWAYS", Const, 0}, {"CREATE_NEW", Const, 0}, {"CREATE_NEW_PROCESS_GROUP", Const, 1}, {"CREATE_UNICODE_ENVIRONMENT", Const, 0}, {"CRYPT_DEFAULT_CONTAINER_OPTIONAL", Const, 0}, {"CRYPT_DELETEKEYSET", Const, 0}, {"CRYPT_MACHINE_KEYSET", Const, 0}, {"CRYPT_NEWKEYSET", Const, 0}, {"CRYPT_SILENT", Const, 0}, {"CRYPT_VERIFYCONTEXT", Const, 0}, {"CS5", Const, 0}, {"CS6", Const, 0}, {"CS7", Const, 0}, {"CS8", Const, 0}, {"CSIZE", Const, 0}, {"CSTART", Const, 1}, {"CSTATUS", Const, 1}, {"CSTOP", Const, 1}, {"CSTOPB", Const, 0}, {"CSUSP", Const, 1}, {"CTL_MAXNAME", Const, 0}, {"CTL_NET", Const, 0}, {"CTL_QUERY", Const, 1}, {"CTRL_BREAK_EVENT", Const, 1}, {"CTRL_CLOSE_EVENT", Const, 14}, {"CTRL_C_EVENT", Const, 1}, {"CTRL_LOGOFF_EVENT", Const, 14}, {"CTRL_SHUTDOWN_EVENT", Const, 14}, {"CancelIo", Func, 0}, {"CancelIoEx", Func, 1}, {"CertAddCertificateContextToStore", Func, 0}, {"CertChainContext", Type, 0}, {"CertChainContext.ChainCount", Field, 0}, {"CertChainContext.Chains", Field, 0}, {"CertChainContext.HasRevocationFreshnessTime", Field, 0}, {"CertChainContext.LowerQualityChainCount", Field, 0}, {"CertChainContext.LowerQualityChains", Field, 0}, {"CertChainContext.RevocationFreshnessTime", Field, 0}, {"CertChainContext.Size", Field, 0}, {"CertChainContext.TrustStatus", Field, 0}, {"CertChainElement", Type, 0}, {"CertChainElement.ApplicationUsage", Field, 0}, {"CertChainElement.CertContext", Field, 0}, {"CertChainElement.ExtendedErrorInfo", Field, 0}, {"CertChainElement.IssuanceUsage", Field, 0}, {"CertChainElement.RevocationInfo", Field, 0}, {"CertChainElement.Size", Field, 0}, {"CertChainElement.TrustStatus", Field, 0}, {"CertChainPara", Type, 0}, {"CertChainPara.CacheResync", Field, 0}, {"CertChainPara.CheckRevocationFreshnessTime", Field, 0}, {"CertChainPara.RequestedUsage", Field, 0}, {"CertChainPara.RequstedIssuancePolicy", Field, 0}, {"CertChainPara.RevocationFreshnessTime", Field, 0}, {"CertChainPara.Size", Field, 0}, {"CertChainPara.URLRetrievalTimeout", Field, 0}, {"CertChainPolicyPara", Type, 0}, {"CertChainPolicyPara.ExtraPolicyPara", Field, 0}, {"CertChainPolicyPara.Flags", Field, 0}, {"CertChainPolicyPara.Size", Field, 0}, {"CertChainPolicyStatus", Type, 0}, {"CertChainPolicyStatus.ChainIndex", Field, 0}, {"CertChainPolicyStatus.ElementIndex", Field, 0}, {"CertChainPolicyStatus.Error", Field, 0}, {"CertChainPolicyStatus.ExtraPolicyStatus", Field, 0}, {"CertChainPolicyStatus.Size", Field, 0}, {"CertCloseStore", Func, 0}, {"CertContext", Type, 0}, {"CertContext.CertInfo", Field, 0}, {"CertContext.EncodedCert", Field, 0}, {"CertContext.EncodingType", Field, 0}, {"CertContext.Length", Field, 0}, {"CertContext.Store", Field, 0}, {"CertCreateCertificateContext", Func, 0}, {"CertEnhKeyUsage", Type, 0}, {"CertEnhKeyUsage.Length", Field, 0}, {"CertEnhKeyUsage.UsageIdentifiers", Field, 0}, {"CertEnumCertificatesInStore", Func, 0}, {"CertFreeCertificateChain", Func, 0}, {"CertFreeCertificateContext", Func, 0}, {"CertGetCertificateChain", Func, 0}, {"CertInfo", Type, 11}, {"CertOpenStore", Func, 0}, {"CertOpenSystemStore", Func, 0}, {"CertRevocationCrlInfo", Type, 11}, {"CertRevocationInfo", Type, 0}, {"CertRevocationInfo.CrlInfo", Field, 0}, {"CertRevocationInfo.FreshnessTime", Field, 0}, {"CertRevocationInfo.HasFreshnessTime", Field, 0}, {"CertRevocationInfo.OidSpecificInfo", Field, 0}, {"CertRevocationInfo.RevocationOid", Field, 0}, {"CertRevocationInfo.RevocationResult", Field, 0}, {"CertRevocationInfo.Size", Field, 0}, {"CertSimpleChain", Type, 0}, {"CertSimpleChain.Elements", Field, 0}, {"CertSimpleChain.HasRevocationFreshnessTime", Field, 0}, {"CertSimpleChain.NumElements", Field, 0}, {"CertSimpleChain.RevocationFreshnessTime", Field, 0}, {"CertSimpleChain.Size", Field, 0}, {"CertSimpleChain.TrustListInfo", Field, 0}, {"CertSimpleChain.TrustStatus", Field, 0}, {"CertTrustListInfo", Type, 11}, {"CertTrustStatus", Type, 0}, {"CertTrustStatus.ErrorStatus", Field, 0}, {"CertTrustStatus.InfoStatus", Field, 0}, {"CertUsageMatch", Type, 0}, {"CertUsageMatch.Type", Field, 0}, {"CertUsageMatch.Usage", Field, 0}, {"CertVerifyCertificateChainPolicy", Func, 0}, {"Chdir", Func, 0}, {"CheckBpfVersion", Func, 0}, {"Chflags", Func, 0}, {"Chmod", Func, 0}, {"Chown", Func, 0}, {"Chroot", Func, 0}, {"Clearenv", Func, 0}, {"Close", Func, 0}, {"CloseHandle", Func, 0}, {"CloseOnExec", Func, 0}, {"Closesocket", Func, 0}, {"CmsgLen", Func, 0}, {"CmsgSpace", Func, 0}, {"Cmsghdr", Type, 0}, {"Cmsghdr.Len", Field, 0}, {"Cmsghdr.Level", Field, 0}, {"Cmsghdr.Type", Field, 0}, {"Cmsghdr.X__cmsg_data", Field, 0}, {"CommandLineToArgv", Func, 0}, {"ComputerName", Func, 0}, {"Conn", Type, 9}, {"Connect", Func, 0}, {"ConnectEx", Func, 1}, {"ConvertSidToStringSid", Func, 0}, {"ConvertStringSidToSid", Func, 0}, {"CopySid", Func, 0}, {"Creat", Func, 0}, {"CreateDirectory", Func, 0}, {"CreateFile", Func, 0}, {"CreateFileMapping", Func, 0}, {"CreateHardLink", Func, 4}, {"CreateIoCompletionPort", Func, 0}, {"CreatePipe", Func, 0}, {"CreateProcess", Func, 0}, {"CreateProcessAsUser", Func, 10}, {"CreateSymbolicLink", Func, 4}, {"CreateToolhelp32Snapshot", Func, 4}, {"Credential", Type, 0}, {"Credential.Gid", Field, 0}, {"Credential.Groups", Field, 0}, {"Credential.NoSetGroups", Field, 9}, {"Credential.Uid", Field, 0}, {"CryptAcquireContext", Func, 0}, {"CryptGenRandom", Func, 0}, {"CryptReleaseContext", Func, 0}, {"DIOCBSFLUSH", Const, 1}, {"DIOCOSFPFLUSH", Const, 1}, {"DLL", Type, 0}, {"DLL.Handle", Field, 0}, {"DLL.Name", Field, 0}, {"DLLError", Type, 0}, {"DLLError.Err", Field, 0}, {"DLLError.Msg", Field, 0}, {"DLLError.ObjName", Field, 0}, {"DLT_A429", Const, 0}, {"DLT_A653_ICM", Const, 0}, {"DLT_AIRONET_HEADER", Const, 0}, {"DLT_AOS", Const, 1}, {"DLT_APPLE_IP_OVER_IEEE1394", Const, 0}, {"DLT_ARCNET", Const, 0}, {"DLT_ARCNET_LINUX", Const, 0}, {"DLT_ATM_CLIP", Const, 0}, {"DLT_ATM_RFC1483", Const, 0}, {"DLT_AURORA", Const, 0}, {"DLT_AX25", Const, 0}, {"DLT_AX25_KISS", Const, 0}, {"DLT_BACNET_MS_TP", Const, 0}, {"DLT_BLUETOOTH_HCI_H4", Const, 0}, {"DLT_BLUETOOTH_HCI_H4_WITH_PHDR", Const, 0}, {"DLT_CAN20B", Const, 0}, {"DLT_CAN_SOCKETCAN", Const, 1}, {"DLT_CHAOS", Const, 0}, {"DLT_CHDLC", Const, 0}, {"DLT_CISCO_IOS", Const, 0}, {"DLT_C_HDLC", Const, 0}, {"DLT_C_HDLC_WITH_DIR", Const, 0}, {"DLT_DBUS", Const, 1}, {"DLT_DECT", Const, 1}, {"DLT_DOCSIS", Const, 0}, {"DLT_DVB_CI", Const, 1}, {"DLT_ECONET", Const, 0}, {"DLT_EN10MB", Const, 0}, {"DLT_EN3MB", Const, 0}, {"DLT_ENC", Const, 0}, {"DLT_ERF", Const, 0}, {"DLT_ERF_ETH", Const, 0}, {"DLT_ERF_POS", Const, 0}, {"DLT_FC_2", Const, 1}, {"DLT_FC_2_WITH_FRAME_DELIMS", Const, 1}, {"DLT_FDDI", Const, 0}, {"DLT_FLEXRAY", Const, 0}, {"DLT_FRELAY", Const, 0}, {"DLT_FRELAY_WITH_DIR", Const, 0}, {"DLT_GCOM_SERIAL", Const, 0}, {"DLT_GCOM_T1E1", Const, 0}, {"DLT_GPF_F", Const, 0}, {"DLT_GPF_T", Const, 0}, {"DLT_GPRS_LLC", Const, 0}, {"DLT_GSMTAP_ABIS", Const, 1}, {"DLT_GSMTAP_UM", Const, 1}, {"DLT_HDLC", Const, 1}, {"DLT_HHDLC", Const, 0}, {"DLT_HIPPI", Const, 1}, {"DLT_IBM_SN", Const, 0}, {"DLT_IBM_SP", Const, 0}, {"DLT_IEEE802", Const, 0}, {"DLT_IEEE802_11", Const, 0}, {"DLT_IEEE802_11_RADIO", Const, 0}, {"DLT_IEEE802_11_RADIO_AVS", Const, 0}, {"DLT_IEEE802_15_4", Const, 0}, {"DLT_IEEE802_15_4_LINUX", Const, 0}, {"DLT_IEEE802_15_4_NOFCS", Const, 1}, {"DLT_IEEE802_15_4_NONASK_PHY", Const, 0}, {"DLT_IEEE802_16_MAC_CPS", Const, 0}, {"DLT_IEEE802_16_MAC_CPS_RADIO", Const, 0}, {"DLT_IPFILTER", Const, 0}, {"DLT_IPMB", Const, 0}, {"DLT_IPMB_LINUX", Const, 0}, {"DLT_IPNET", Const, 1}, {"DLT_IPOIB", Const, 1}, {"DLT_IPV4", Const, 1}, {"DLT_IPV6", Const, 1}, {"DLT_IP_OVER_FC", Const, 0}, {"DLT_JUNIPER_ATM1", Const, 0}, {"DLT_JUNIPER_ATM2", Const, 0}, {"DLT_JUNIPER_ATM_CEMIC", Const, 1}, {"DLT_JUNIPER_CHDLC", Const, 0}, {"DLT_JUNIPER_ES", Const, 0}, {"DLT_JUNIPER_ETHER", Const, 0}, {"DLT_JUNIPER_FIBRECHANNEL", Const, 1}, {"DLT_JUNIPER_FRELAY", Const, 0}, {"DLT_JUNIPER_GGSN", Const, 0}, {"DLT_JUNIPER_ISM", Const, 0}, {"DLT_JUNIPER_MFR", Const, 0}, {"DLT_JUNIPER_MLFR", Const, 0}, {"DLT_JUNIPER_MLPPP", Const, 0}, {"DLT_JUNIPER_MONITOR", Const, 0}, {"DLT_JUNIPER_PIC_PEER", Const, 0}, {"DLT_JUNIPER_PPP", Const, 0}, {"DLT_JUNIPER_PPPOE", Const, 0}, {"DLT_JUNIPER_PPPOE_ATM", Const, 0}, {"DLT_JUNIPER_SERVICES", Const, 0}, {"DLT_JUNIPER_SRX_E2E", Const, 1}, {"DLT_JUNIPER_ST", Const, 0}, {"DLT_JUNIPER_VP", Const, 0}, {"DLT_JUNIPER_VS", Const, 1}, {"DLT_LAPB_WITH_DIR", Const, 0}, {"DLT_LAPD", Const, 0}, {"DLT_LIN", Const, 0}, {"DLT_LINUX_EVDEV", Const, 1}, {"DLT_LINUX_IRDA", Const, 0}, {"DLT_LINUX_LAPD", Const, 0}, {"DLT_LINUX_PPP_WITHDIRECTION", Const, 0}, {"DLT_LINUX_SLL", Const, 0}, {"DLT_LOOP", Const, 0}, {"DLT_LTALK", Const, 0}, {"DLT_MATCHING_MAX", Const, 1}, {"DLT_MATCHING_MIN", Const, 1}, {"DLT_MFR", Const, 0}, {"DLT_MOST", Const, 0}, {"DLT_MPEG_2_TS", Const, 1}, {"DLT_MPLS", Const, 1}, {"DLT_MTP2", Const, 0}, {"DLT_MTP2_WITH_PHDR", Const, 0}, {"DLT_MTP3", Const, 0}, {"DLT_MUX27010", Const, 1}, {"DLT_NETANALYZER", Const, 1}, {"DLT_NETANALYZER_TRANSPARENT", Const, 1}, {"DLT_NFC_LLCP", Const, 1}, {"DLT_NFLOG", Const, 1}, {"DLT_NG40", Const, 1}, {"DLT_NULL", Const, 0}, {"DLT_PCI_EXP", Const, 0}, {"DLT_PFLOG", Const, 0}, {"DLT_PFSYNC", Const, 0}, {"DLT_PPI", Const, 0}, {"DLT_PPP", Const, 0}, {"DLT_PPP_BSDOS", Const, 0}, {"DLT_PPP_ETHER", Const, 0}, {"DLT_PPP_PPPD", Const, 0}, {"DLT_PPP_SERIAL", Const, 0}, {"DLT_PPP_WITH_DIR", Const, 0}, {"DLT_PPP_WITH_DIRECTION", Const, 0}, {"DLT_PRISM_HEADER", Const, 0}, {"DLT_PRONET", Const, 0}, {"DLT_RAIF1", Const, 0}, {"DLT_RAW", Const, 0}, {"DLT_RAWAF_MASK", Const, 1}, {"DLT_RIO", Const, 0}, {"DLT_SCCP", Const, 0}, {"DLT_SITA", Const, 0}, {"DLT_SLIP", Const, 0}, {"DLT_SLIP_BSDOS", Const, 0}, {"DLT_STANAG_5066_D_PDU", Const, 1}, {"DLT_SUNATM", Const, 0}, {"DLT_SYMANTEC_FIREWALL", Const, 0}, {"DLT_TZSP", Const, 0}, {"DLT_USB", Const, 0}, {"DLT_USB_LINUX", Const, 0}, {"DLT_USB_LINUX_MMAPPED", Const, 1}, {"DLT_USER0", Const, 0}, {"DLT_USER1", Const, 0}, {"DLT_USER10", Const, 0}, {"DLT_USER11", Const, 0}, {"DLT_USER12", Const, 0}, {"DLT_USER13", Const, 0}, {"DLT_USER14", Const, 0}, {"DLT_USER15", Const, 0}, {"DLT_USER2", Const, 0}, {"DLT_USER3", Const, 0}, {"DLT_USER4", Const, 0}, {"DLT_USER5", Const, 0}, {"DLT_USER6", Const, 0}, {"DLT_USER7", Const, 0}, {"DLT_USER8", Const, 0}, {"DLT_USER9", Const, 0}, {"DLT_WIHART", Const, 1}, {"DLT_X2E_SERIAL", Const, 0}, {"DLT_X2E_XORAYA", Const, 0}, {"DNSMXData", Type, 0}, {"DNSMXData.NameExchange", Field, 0}, {"DNSMXData.Pad", Field, 0}, {"DNSMXData.Preference", Field, 0}, {"DNSPTRData", Type, 0}, {"DNSPTRData.Host", Field, 0}, {"DNSRecord", Type, 0}, {"DNSRecord.Data", Field, 0}, {"DNSRecord.Dw", Field, 0}, {"DNSRecord.Length", Field, 0}, {"DNSRecord.Name", Field, 0}, {"DNSRecord.Next", Field, 0}, {"DNSRecord.Reserved", Field, 0}, {"DNSRecord.Ttl", Field, 0}, {"DNSRecord.Type", Field, 0}, {"DNSSRVData", Type, 0}, {"DNSSRVData.Pad", Field, 0}, {"DNSSRVData.Port", Field, 0}, {"DNSSRVData.Priority", Field, 0}, {"DNSSRVData.Target", Field, 0}, {"DNSSRVData.Weight", Field, 0}, {"DNSTXTData", Type, 0}, {"DNSTXTData.StringArray", Field, 0}, {"DNSTXTData.StringCount", Field, 0}, {"DNS_INFO_NO_RECORDS", Const, 4}, {"DNS_TYPE_A", Const, 0}, {"DNS_TYPE_A6", Const, 0}, {"DNS_TYPE_AAAA", Const, 0}, {"DNS_TYPE_ADDRS", Const, 0}, {"DNS_TYPE_AFSDB", Const, 0}, {"DNS_TYPE_ALL", Const, 0}, {"DNS_TYPE_ANY", Const, 0}, {"DNS_TYPE_ATMA", Const, 0}, {"DNS_TYPE_AXFR", Const, 0}, {"DNS_TYPE_CERT", Const, 0}, {"DNS_TYPE_CNAME", Const, 0}, {"DNS_TYPE_DHCID", Const, 0}, {"DNS_TYPE_DNAME", Const, 0}, {"DNS_TYPE_DNSKEY", Const, 0}, {"DNS_TYPE_DS", Const, 0}, {"DNS_TYPE_EID", Const, 0}, {"DNS_TYPE_GID", Const, 0}, {"DNS_TYPE_GPOS", Const, 0}, {"DNS_TYPE_HINFO", Const, 0}, {"DNS_TYPE_ISDN", Const, 0}, {"DNS_TYPE_IXFR", Const, 0}, {"DNS_TYPE_KEY", Const, 0}, {"DNS_TYPE_KX", Const, 0}, {"DNS_TYPE_LOC", Const, 0}, {"DNS_TYPE_MAILA", Const, 0}, {"DNS_TYPE_MAILB", Const, 0}, {"DNS_TYPE_MB", Const, 0}, {"DNS_TYPE_MD", Const, 0}, {"DNS_TYPE_MF", Const, 0}, {"DNS_TYPE_MG", Const, 0}, {"DNS_TYPE_MINFO", Const, 0}, {"DNS_TYPE_MR", Const, 0}, {"DNS_TYPE_MX", Const, 0}, {"DNS_TYPE_NAPTR", Const, 0}, {"DNS_TYPE_NBSTAT", Const, 0}, {"DNS_TYPE_NIMLOC", Const, 0}, {"DNS_TYPE_NS", Const, 0}, {"DNS_TYPE_NSAP", Const, 0}, {"DNS_TYPE_NSAPPTR", Const, 0}, {"DNS_TYPE_NSEC", Const, 0}, {"DNS_TYPE_NULL", Const, 0}, {"DNS_TYPE_NXT", Const, 0}, {"DNS_TYPE_OPT", Const, 0}, {"DNS_TYPE_PTR", Const, 0}, {"DNS_TYPE_PX", Const, 0}, {"DNS_TYPE_RP", Const, 0}, {"DNS_TYPE_RRSIG", Const, 0}, {"DNS_TYPE_RT", Const, 0}, {"DNS_TYPE_SIG", Const, 0}, {"DNS_TYPE_SINK", Const, 0}, {"DNS_TYPE_SOA", Const, 0}, {"DNS_TYPE_SRV", Const, 0}, {"DNS_TYPE_TEXT", Const, 0}, {"DNS_TYPE_TKEY", Const, 0}, {"DNS_TYPE_TSIG", Const, 0}, {"DNS_TYPE_UID", Const, 0}, {"DNS_TYPE_UINFO", Const, 0}, {"DNS_TYPE_UNSPEC", Const, 0}, {"DNS_TYPE_WINS", Const, 0}, {"DNS_TYPE_WINSR", Const, 0}, {"DNS_TYPE_WKS", Const, 0}, {"DNS_TYPE_X25", Const, 0}, {"DT_BLK", Const, 0}, {"DT_CHR", Const, 0}, {"DT_DIR", Const, 0}, {"DT_FIFO", Const, 0}, {"DT_LNK", Const, 0}, {"DT_REG", Const, 0}, {"DT_SOCK", Const, 0}, {"DT_UNKNOWN", Const, 0}, {"DT_WHT", Const, 0}, {"DUPLICATE_CLOSE_SOURCE", Const, 0}, {"DUPLICATE_SAME_ACCESS", Const, 0}, {"DeleteFile", Func, 0}, {"DetachLsf", Func, 0}, {"DeviceIoControl", Func, 4}, {"Dirent", Type, 0}, {"Dirent.Fileno", Field, 0}, {"Dirent.Ino", Field, 0}, {"Dirent.Name", Field, 0}, {"Dirent.Namlen", Field, 0}, {"Dirent.Off", Field, 0}, {"Dirent.Pad0", Field, 12}, {"Dirent.Pad1", Field, 12}, {"Dirent.Pad_cgo_0", Field, 0}, {"Dirent.Reclen", Field, 0}, {"Dirent.Seekoff", Field, 0}, {"Dirent.Type", Field, 0}, {"Dirent.X__d_padding", Field, 3}, {"DnsNameCompare", Func, 4}, {"DnsQuery", Func, 0}, {"DnsRecordListFree", Func, 0}, {"DnsSectionAdditional", Const, 4}, {"DnsSectionAnswer", Const, 4}, {"DnsSectionAuthority", Const, 4}, {"DnsSectionQuestion", Const, 4}, {"Dup", Func, 0}, {"Dup2", Func, 0}, {"Dup3", Func, 2}, {"DuplicateHandle", Func, 0}, {"E2BIG", Const, 0}, {"EACCES", Const, 0}, {"EADDRINUSE", Const, 0}, {"EADDRNOTAVAIL", Const, 0}, {"EADV", Const, 0}, {"EAFNOSUPPORT", Const, 0}, {"EAGAIN", Const, 0}, {"EALREADY", Const, 0}, {"EAUTH", Const, 0}, {"EBADARCH", Const, 0}, {"EBADE", Const, 0}, {"EBADEXEC", Const, 0}, {"EBADF", Const, 0}, {"EBADFD", Const, 0}, {"EBADMACHO", Const, 0}, {"EBADMSG", Const, 0}, {"EBADR", Const, 0}, {"EBADRPC", Const, 0}, {"EBADRQC", Const, 0}, {"EBADSLT", Const, 0}, {"EBFONT", Const, 0}, {"EBUSY", Const, 0}, {"ECANCELED", Const, 0}, {"ECAPMODE", Const, 1}, {"ECHILD", Const, 0}, {"ECHO", Const, 0}, {"ECHOCTL", Const, 0}, {"ECHOE", Const, 0}, {"ECHOK", Const, 0}, {"ECHOKE", Const, 0}, {"ECHONL", Const, 0}, {"ECHOPRT", Const, 0}, {"ECHRNG", Const, 0}, {"ECOMM", Const, 0}, {"ECONNABORTED", Const, 0}, {"ECONNREFUSED", Const, 0}, {"ECONNRESET", Const, 0}, {"EDEADLK", Const, 0}, {"EDEADLOCK", Const, 0}, {"EDESTADDRREQ", Const, 0}, {"EDEVERR", Const, 0}, {"EDOM", Const, 0}, {"EDOOFUS", Const, 0}, {"EDOTDOT", Const, 0}, {"EDQUOT", Const, 0}, {"EEXIST", Const, 0}, {"EFAULT", Const, 0}, {"EFBIG", Const, 0}, {"EFER_LMA", Const, 1}, {"EFER_LME", Const, 1}, {"EFER_NXE", Const, 1}, {"EFER_SCE", Const, 1}, {"EFTYPE", Const, 0}, {"EHOSTDOWN", Const, 0}, {"EHOSTUNREACH", Const, 0}, {"EHWPOISON", Const, 0}, {"EIDRM", Const, 0}, {"EILSEQ", Const, 0}, {"EINPROGRESS", Const, 0}, {"EINTR", Const, 0}, {"EINVAL", Const, 0}, {"EIO", Const, 0}, {"EIPSEC", Const, 1}, {"EISCONN", Const, 0}, {"EISDIR", Const, 0}, {"EISNAM", Const, 0}, {"EKEYEXPIRED", Const, 0}, {"EKEYREJECTED", Const, 0}, {"EKEYREVOKED", Const, 0}, {"EL2HLT", Const, 0}, {"EL2NSYNC", Const, 0}, {"EL3HLT", Const, 0}, {"EL3RST", Const, 0}, {"ELAST", Const, 0}, {"ELF_NGREG", Const, 0}, {"ELF_PRARGSZ", Const, 0}, {"ELIBACC", Const, 0}, {"ELIBBAD", Const, 0}, {"ELIBEXEC", Const, 0}, {"ELIBMAX", Const, 0}, {"ELIBSCN", Const, 0}, {"ELNRNG", Const, 0}, {"ELOOP", Const, 0}, {"EMEDIUMTYPE", Const, 0}, {"EMFILE", Const, 0}, {"EMLINK", Const, 0}, {"EMSGSIZE", Const, 0}, {"EMT_TAGOVF", Const, 1}, {"EMULTIHOP", Const, 0}, {"EMUL_ENABLED", Const, 1}, {"EMUL_LINUX", Const, 1}, {"EMUL_LINUX32", Const, 1}, {"EMUL_MAXID", Const, 1}, {"EMUL_NATIVE", Const, 1}, {"ENAMETOOLONG", Const, 0}, {"ENAVAIL", Const, 0}, {"ENDRUNDISC", Const, 1}, {"ENEEDAUTH", Const, 0}, {"ENETDOWN", Const, 0}, {"ENETRESET", Const, 0}, {"ENETUNREACH", Const, 0}, {"ENFILE", Const, 0}, {"ENOANO", Const, 0}, {"ENOATTR", Const, 0}, {"ENOBUFS", Const, 0}, {"ENOCSI", Const, 0}, {"ENODATA", Const, 0}, {"ENODEV", Const, 0}, {"ENOENT", Const, 0}, {"ENOEXEC", Const, 0}, {"ENOKEY", Const, 0}, {"ENOLCK", Const, 0}, {"ENOLINK", Const, 0}, {"ENOMEDIUM", Const, 0}, {"ENOMEM", Const, 0}, {"ENOMSG", Const, 0}, {"ENONET", Const, 0}, {"ENOPKG", Const, 0}, {"ENOPOLICY", Const, 0}, {"ENOPROTOOPT", Const, 0}, {"ENOSPC", Const, 0}, {"ENOSR", Const, 0}, {"ENOSTR", Const, 0}, {"ENOSYS", Const, 0}, {"ENOTBLK", Const, 0}, {"ENOTCAPABLE", Const, 0}, {"ENOTCONN", Const, 0}, {"ENOTDIR", Const, 0}, {"ENOTEMPTY", Const, 0}, {"ENOTNAM", Const, 0}, {"ENOTRECOVERABLE", Const, 0}, {"ENOTSOCK", Const, 0}, {"ENOTSUP", Const, 0}, {"ENOTTY", Const, 0}, {"ENOTUNIQ", Const, 0}, {"ENXIO", Const, 0}, {"EN_SW_CTL_INF", Const, 1}, {"EN_SW_CTL_PREC", Const, 1}, {"EN_SW_CTL_ROUND", Const, 1}, {"EN_SW_DATACHAIN", Const, 1}, {"EN_SW_DENORM", Const, 1}, {"EN_SW_INVOP", Const, 1}, {"EN_SW_OVERFLOW", Const, 1}, {"EN_SW_PRECLOSS", Const, 1}, {"EN_SW_UNDERFLOW", Const, 1}, {"EN_SW_ZERODIV", Const, 1}, {"EOPNOTSUPP", Const, 0}, {"EOVERFLOW", Const, 0}, {"EOWNERDEAD", Const, 0}, {"EPERM", Const, 0}, {"EPFNOSUPPORT", Const, 0}, {"EPIPE", Const, 0}, {"EPOLLERR", Const, 0}, {"EPOLLET", Const, 0}, {"EPOLLHUP", Const, 0}, {"EPOLLIN", Const, 0}, {"EPOLLMSG", Const, 0}, {"EPOLLONESHOT", Const, 0}, {"EPOLLOUT", Const, 0}, {"EPOLLPRI", Const, 0}, {"EPOLLRDBAND", Const, 0}, {"EPOLLRDHUP", Const, 0}, {"EPOLLRDNORM", Const, 0}, {"EPOLLWRBAND", Const, 0}, {"EPOLLWRNORM", Const, 0}, {"EPOLL_CLOEXEC", Const, 0}, {"EPOLL_CTL_ADD", Const, 0}, {"EPOLL_CTL_DEL", Const, 0}, {"EPOLL_CTL_MOD", Const, 0}, {"EPOLL_NONBLOCK", Const, 0}, {"EPROCLIM", Const, 0}, {"EPROCUNAVAIL", Const, 0}, {"EPROGMISMATCH", Const, 0}, {"EPROGUNAVAIL", Const, 0}, {"EPROTO", Const, 0}, {"EPROTONOSUPPORT", Const, 0}, {"EPROTOTYPE", Const, 0}, {"EPWROFF", Const, 0}, {"EQFULL", Const, 16}, {"ERANGE", Const, 0}, {"EREMCHG", Const, 0}, {"EREMOTE", Const, 0}, {"EREMOTEIO", Const, 0}, {"ERESTART", Const, 0}, {"ERFKILL", Const, 0}, {"EROFS", Const, 0}, {"ERPCMISMATCH", Const, 0}, {"ERROR_ACCESS_DENIED", Const, 0}, {"ERROR_ALREADY_EXISTS", Const, 0}, {"ERROR_BROKEN_PIPE", Const, 0}, {"ERROR_BUFFER_OVERFLOW", Const, 0}, {"ERROR_DIR_NOT_EMPTY", Const, 8}, {"ERROR_ENVVAR_NOT_FOUND", Const, 0}, {"ERROR_FILE_EXISTS", Const, 0}, {"ERROR_FILE_NOT_FOUND", Const, 0}, {"ERROR_HANDLE_EOF", Const, 2}, {"ERROR_INSUFFICIENT_BUFFER", Const, 0}, {"ERROR_IO_PENDING", Const, 0}, {"ERROR_MOD_NOT_FOUND", Const, 0}, {"ERROR_MORE_DATA", Const, 3}, {"ERROR_NETNAME_DELETED", Const, 3}, {"ERROR_NOT_FOUND", Const, 1}, {"ERROR_NO_MORE_FILES", Const, 0}, {"ERROR_OPERATION_ABORTED", Const, 0}, {"ERROR_PATH_NOT_FOUND", Const, 0}, {"ERROR_PRIVILEGE_NOT_HELD", Const, 4}, {"ERROR_PROC_NOT_FOUND", Const, 0}, {"ESHLIBVERS", Const, 0}, {"ESHUTDOWN", Const, 0}, {"ESOCKTNOSUPPORT", Const, 0}, {"ESPIPE", Const, 0}, {"ESRCH", Const, 0}, {"ESRMNT", Const, 0}, {"ESTALE", Const, 0}, {"ESTRPIPE", Const, 0}, {"ETHERCAP_JUMBO_MTU", Const, 1}, {"ETHERCAP_VLAN_HWTAGGING", Const, 1}, {"ETHERCAP_VLAN_MTU", Const, 1}, {"ETHERMIN", Const, 1}, {"ETHERMTU", Const, 1}, {"ETHERMTU_JUMBO", Const, 1}, {"ETHERTYPE_8023", Const, 1}, {"ETHERTYPE_AARP", Const, 1}, {"ETHERTYPE_ACCTON", Const, 1}, {"ETHERTYPE_AEONIC", Const, 1}, {"ETHERTYPE_ALPHA", Const, 1}, {"ETHERTYPE_AMBER", Const, 1}, {"ETHERTYPE_AMOEBA", Const, 1}, {"ETHERTYPE_AOE", Const, 1}, {"ETHERTYPE_APOLLO", Const, 1}, {"ETHERTYPE_APOLLODOMAIN", Const, 1}, {"ETHERTYPE_APPLETALK", Const, 1}, {"ETHERTYPE_APPLITEK", Const, 1}, {"ETHERTYPE_ARGONAUT", Const, 1}, {"ETHERTYPE_ARP", Const, 1}, {"ETHERTYPE_AT", Const, 1}, {"ETHERTYPE_ATALK", Const, 1}, {"ETHERTYPE_ATOMIC", Const, 1}, {"ETHERTYPE_ATT", Const, 1}, {"ETHERTYPE_ATTSTANFORD", Const, 1}, {"ETHERTYPE_AUTOPHON", Const, 1}, {"ETHERTYPE_AXIS", Const, 1}, {"ETHERTYPE_BCLOOP", Const, 1}, {"ETHERTYPE_BOFL", Const, 1}, {"ETHERTYPE_CABLETRON", Const, 1}, {"ETHERTYPE_CHAOS", Const, 1}, {"ETHERTYPE_COMDESIGN", Const, 1}, {"ETHERTYPE_COMPUGRAPHIC", Const, 1}, {"ETHERTYPE_COUNTERPOINT", Const, 1}, {"ETHERTYPE_CRONUS", Const, 1}, {"ETHERTYPE_CRONUSVLN", Const, 1}, {"ETHERTYPE_DCA", Const, 1}, {"ETHERTYPE_DDE", Const, 1}, {"ETHERTYPE_DEBNI", Const, 1}, {"ETHERTYPE_DECAM", Const, 1}, {"ETHERTYPE_DECCUST", Const, 1}, {"ETHERTYPE_DECDIAG", Const, 1}, {"ETHERTYPE_DECDNS", Const, 1}, {"ETHERTYPE_DECDTS", Const, 1}, {"ETHERTYPE_DECEXPER", Const, 1}, {"ETHERTYPE_DECLAST", Const, 1}, {"ETHERTYPE_DECLTM", Const, 1}, {"ETHERTYPE_DECMUMPS", Const, 1}, {"ETHERTYPE_DECNETBIOS", Const, 1}, {"ETHERTYPE_DELTACON", Const, 1}, {"ETHERTYPE_DIDDLE", Const, 1}, {"ETHERTYPE_DLOG1", Const, 1}, {"ETHERTYPE_DLOG2", Const, 1}, {"ETHERTYPE_DN", Const, 1}, {"ETHERTYPE_DOGFIGHT", Const, 1}, {"ETHERTYPE_DSMD", Const, 1}, {"ETHERTYPE_ECMA", Const, 1}, {"ETHERTYPE_ENCRYPT", Const, 1}, {"ETHERTYPE_ES", Const, 1}, {"ETHERTYPE_EXCELAN", Const, 1}, {"ETHERTYPE_EXPERDATA", Const, 1}, {"ETHERTYPE_FLIP", Const, 1}, {"ETHERTYPE_FLOWCONTROL", Const, 1}, {"ETHERTYPE_FRARP", Const, 1}, {"ETHERTYPE_GENDYN", Const, 1}, {"ETHERTYPE_HAYES", Const, 1}, {"ETHERTYPE_HIPPI_FP", Const, 1}, {"ETHERTYPE_HITACHI", Const, 1}, {"ETHERTYPE_HP", Const, 1}, {"ETHERTYPE_IEEEPUP", Const, 1}, {"ETHERTYPE_IEEEPUPAT", Const, 1}, {"ETHERTYPE_IMLBL", Const, 1}, {"ETHERTYPE_IMLBLDIAG", Const, 1}, {"ETHERTYPE_IP", Const, 1}, {"ETHERTYPE_IPAS", Const, 1}, {"ETHERTYPE_IPV6", Const, 1}, {"ETHERTYPE_IPX", Const, 1}, {"ETHERTYPE_IPXNEW", Const, 1}, {"ETHERTYPE_KALPANA", Const, 1}, {"ETHERTYPE_LANBRIDGE", Const, 1}, {"ETHERTYPE_LANPROBE", Const, 1}, {"ETHERTYPE_LAT", Const, 1}, {"ETHERTYPE_LBACK", Const, 1}, {"ETHERTYPE_LITTLE", Const, 1}, {"ETHERTYPE_LLDP", Const, 1}, {"ETHERTYPE_LOGICRAFT", Const, 1}, {"ETHERTYPE_LOOPBACK", Const, 1}, {"ETHERTYPE_MATRA", Const, 1}, {"ETHERTYPE_MAX", Const, 1}, {"ETHERTYPE_MERIT", Const, 1}, {"ETHERTYPE_MICP", Const, 1}, {"ETHERTYPE_MOPDL", Const, 1}, {"ETHERTYPE_MOPRC", Const, 1}, {"ETHERTYPE_MOTOROLA", Const, 1}, {"ETHERTYPE_MPLS", Const, 1}, {"ETHERTYPE_MPLS_MCAST", Const, 1}, {"ETHERTYPE_MUMPS", Const, 1}, {"ETHERTYPE_NBPCC", Const, 1}, {"ETHERTYPE_NBPCLAIM", Const, 1}, {"ETHERTYPE_NBPCLREQ", Const, 1}, {"ETHERTYPE_NBPCLRSP", Const, 1}, {"ETHERTYPE_NBPCREQ", Const, 1}, {"ETHERTYPE_NBPCRSP", Const, 1}, {"ETHERTYPE_NBPDG", Const, 1}, {"ETHERTYPE_NBPDGB", Const, 1}, {"ETHERTYPE_NBPDLTE", Const, 1}, {"ETHERTYPE_NBPRAR", Const, 1}, {"ETHERTYPE_NBPRAS", Const, 1}, {"ETHERTYPE_NBPRST", Const, 1}, {"ETHERTYPE_NBPSCD", Const, 1}, {"ETHERTYPE_NBPVCD", Const, 1}, {"ETHERTYPE_NBS", Const, 1}, {"ETHERTYPE_NCD", Const, 1}, {"ETHERTYPE_NESTAR", Const, 1}, {"ETHERTYPE_NETBEUI", Const, 1}, {"ETHERTYPE_NOVELL", Const, 1}, {"ETHERTYPE_NS", Const, 1}, {"ETHERTYPE_NSAT", Const, 1}, {"ETHERTYPE_NSCOMPAT", Const, 1}, {"ETHERTYPE_NTRAILER", Const, 1}, {"ETHERTYPE_OS9", Const, 1}, {"ETHERTYPE_OS9NET", Const, 1}, {"ETHERTYPE_PACER", Const, 1}, {"ETHERTYPE_PAE", Const, 1}, {"ETHERTYPE_PCS", Const, 1}, {"ETHERTYPE_PLANNING", Const, 1}, {"ETHERTYPE_PPP", Const, 1}, {"ETHERTYPE_PPPOE", Const, 1}, {"ETHERTYPE_PPPOEDISC", Const, 1}, {"ETHERTYPE_PRIMENTS", Const, 1}, {"ETHERTYPE_PUP", Const, 1}, {"ETHERTYPE_PUPAT", Const, 1}, {"ETHERTYPE_QINQ", Const, 1}, {"ETHERTYPE_RACAL", Const, 1}, {"ETHERTYPE_RATIONAL", Const, 1}, {"ETHERTYPE_RAWFR", Const, 1}, {"ETHERTYPE_RCL", Const, 1}, {"ETHERTYPE_RDP", Const, 1}, {"ETHERTYPE_RETIX", Const, 1}, {"ETHERTYPE_REVARP", Const, 1}, {"ETHERTYPE_SCA", Const, 1}, {"ETHERTYPE_SECTRA", Const, 1}, {"ETHERTYPE_SECUREDATA", Const, 1}, {"ETHERTYPE_SGITW", Const, 1}, {"ETHERTYPE_SG_BOUNCE", Const, 1}, {"ETHERTYPE_SG_DIAG", Const, 1}, {"ETHERTYPE_SG_NETGAMES", Const, 1}, {"ETHERTYPE_SG_RESV", Const, 1}, {"ETHERTYPE_SIMNET", Const, 1}, {"ETHERTYPE_SLOW", Const, 1}, {"ETHERTYPE_SLOWPROTOCOLS", Const, 1}, {"ETHERTYPE_SNA", Const, 1}, {"ETHERTYPE_SNMP", Const, 1}, {"ETHERTYPE_SONIX", Const, 1}, {"ETHERTYPE_SPIDER", Const, 1}, {"ETHERTYPE_SPRITE", Const, 1}, {"ETHERTYPE_STP", Const, 1}, {"ETHERTYPE_TALARIS", Const, 1}, {"ETHERTYPE_TALARISMC", Const, 1}, {"ETHERTYPE_TCPCOMP", Const, 1}, {"ETHERTYPE_TCPSM", Const, 1}, {"ETHERTYPE_TEC", Const, 1}, {"ETHERTYPE_TIGAN", Const, 1}, {"ETHERTYPE_TRAIL", Const, 1}, {"ETHERTYPE_TRANSETHER", Const, 1}, {"ETHERTYPE_TYMSHARE", Const, 1}, {"ETHERTYPE_UBBST", Const, 1}, {"ETHERTYPE_UBDEBUG", Const, 1}, {"ETHERTYPE_UBDIAGLOOP", Const, 1}, {"ETHERTYPE_UBDL", Const, 1}, {"ETHERTYPE_UBNIU", Const, 1}, {"ETHERTYPE_UBNMC", Const, 1}, {"ETHERTYPE_VALID", Const, 1}, {"ETHERTYPE_VARIAN", Const, 1}, {"ETHERTYPE_VAXELN", Const, 1}, {"ETHERTYPE_VEECO", Const, 1}, {"ETHERTYPE_VEXP", Const, 1}, {"ETHERTYPE_VGLAB", Const, 1}, {"ETHERTYPE_VINES", Const, 1}, {"ETHERTYPE_VINESECHO", Const, 1}, {"ETHERTYPE_VINESLOOP", Const, 1}, {"ETHERTYPE_VITAL", Const, 1}, {"ETHERTYPE_VLAN", Const, 1}, {"ETHERTYPE_VLTLMAN", Const, 1}, {"ETHERTYPE_VPROD", Const, 1}, {"ETHERTYPE_VURESERVED", Const, 1}, {"ETHERTYPE_WATERLOO", Const, 1}, {"ETHERTYPE_WELLFLEET", Const, 1}, {"ETHERTYPE_X25", Const, 1}, {"ETHERTYPE_X75", Const, 1}, {"ETHERTYPE_XNSSM", Const, 1}, {"ETHERTYPE_XTP", Const, 1}, {"ETHER_ADDR_LEN", Const, 1}, {"ETHER_ALIGN", Const, 1}, {"ETHER_CRC_LEN", Const, 1}, {"ETHER_CRC_POLY_BE", Const, 1}, {"ETHER_CRC_POLY_LE", Const, 1}, {"ETHER_HDR_LEN", Const, 1}, {"ETHER_MAX_DIX_LEN", Const, 1}, {"ETHER_MAX_LEN", Const, 1}, {"ETHER_MAX_LEN_JUMBO", Const, 1}, {"ETHER_MIN_LEN", Const, 1}, {"ETHER_PPPOE_ENCAP_LEN", Const, 1}, {"ETHER_TYPE_LEN", Const, 1}, {"ETHER_VLAN_ENCAP_LEN", Const, 1}, {"ETH_P_1588", Const, 0}, {"ETH_P_8021Q", Const, 0}, {"ETH_P_802_2", Const, 0}, {"ETH_P_802_3", Const, 0}, {"ETH_P_AARP", Const, 0}, {"ETH_P_ALL", Const, 0}, {"ETH_P_AOE", Const, 0}, {"ETH_P_ARCNET", Const, 0}, {"ETH_P_ARP", Const, 0}, {"ETH_P_ATALK", Const, 0}, {"ETH_P_ATMFATE", Const, 0}, {"ETH_P_ATMMPOA", Const, 0}, {"ETH_P_AX25", Const, 0}, {"ETH_P_BPQ", Const, 0}, {"ETH_P_CAIF", Const, 0}, {"ETH_P_CAN", Const, 0}, {"ETH_P_CONTROL", Const, 0}, {"ETH_P_CUST", Const, 0}, {"ETH_P_DDCMP", Const, 0}, {"ETH_P_DEC", Const, 0}, {"ETH_P_DIAG", Const, 0}, {"ETH_P_DNA_DL", Const, 0}, {"ETH_P_DNA_RC", Const, 0}, {"ETH_P_DNA_RT", Const, 0}, {"ETH_P_DSA", Const, 0}, {"ETH_P_ECONET", Const, 0}, {"ETH_P_EDSA", Const, 0}, {"ETH_P_FCOE", Const, 0}, {"ETH_P_FIP", Const, 0}, {"ETH_P_HDLC", Const, 0}, {"ETH_P_IEEE802154", Const, 0}, {"ETH_P_IEEEPUP", Const, 0}, {"ETH_P_IEEEPUPAT", Const, 0}, {"ETH_P_IP", Const, 0}, {"ETH_P_IPV6", Const, 0}, {"ETH_P_IPX", Const, 0}, {"ETH_P_IRDA", Const, 0}, {"ETH_P_LAT", Const, 0}, {"ETH_P_LINK_CTL", Const, 0}, {"ETH_P_LOCALTALK", Const, 0}, {"ETH_P_LOOP", Const, 0}, {"ETH_P_MOBITEX", Const, 0}, {"ETH_P_MPLS_MC", Const, 0}, {"ETH_P_MPLS_UC", Const, 0}, {"ETH_P_PAE", Const, 0}, {"ETH_P_PAUSE", Const, 0}, {"ETH_P_PHONET", Const, 0}, {"ETH_P_PPPTALK", Const, 0}, {"ETH_P_PPP_DISC", Const, 0}, {"ETH_P_PPP_MP", Const, 0}, {"ETH_P_PPP_SES", Const, 0}, {"ETH_P_PUP", Const, 0}, {"ETH_P_PUPAT", Const, 0}, {"ETH_P_RARP", Const, 0}, {"ETH_P_SCA", Const, 0}, {"ETH_P_SLOW", Const, 0}, {"ETH_P_SNAP", Const, 0}, {"ETH_P_TEB", Const, 0}, {"ETH_P_TIPC", Const, 0}, {"ETH_P_TRAILER", Const, 0}, {"ETH_P_TR_802_2", Const, 0}, {"ETH_P_WAN_PPP", Const, 0}, {"ETH_P_WCCP", Const, 0}, {"ETH_P_X25", Const, 0}, {"ETIME", Const, 0}, {"ETIMEDOUT", Const, 0}, {"ETOOMANYREFS", Const, 0}, {"ETXTBSY", Const, 0}, {"EUCLEAN", Const, 0}, {"EUNATCH", Const, 0}, {"EUSERS", Const, 0}, {"EVFILT_AIO", Const, 0}, {"EVFILT_FS", Const, 0}, {"EVFILT_LIO", Const, 0}, {"EVFILT_MACHPORT", Const, 0}, {"EVFILT_PROC", Const, 0}, {"EVFILT_READ", Const, 0}, {"EVFILT_SIGNAL", Const, 0}, {"EVFILT_SYSCOUNT", Const, 0}, {"EVFILT_THREADMARKER", Const, 0}, {"EVFILT_TIMER", Const, 0}, {"EVFILT_USER", Const, 0}, {"EVFILT_VM", Const, 0}, {"EVFILT_VNODE", Const, 0}, {"EVFILT_WRITE", Const, 0}, {"EV_ADD", Const, 0}, {"EV_CLEAR", Const, 0}, {"EV_DELETE", Const, 0}, {"EV_DISABLE", Const, 0}, {"EV_DISPATCH", Const, 0}, {"EV_DROP", Const, 3}, {"EV_ENABLE", Const, 0}, {"EV_EOF", Const, 0}, {"EV_ERROR", Const, 0}, {"EV_FLAG0", Const, 0}, {"EV_FLAG1", Const, 0}, {"EV_ONESHOT", Const, 0}, {"EV_OOBAND", Const, 0}, {"EV_POLL", Const, 0}, {"EV_RECEIPT", Const, 0}, {"EV_SYSFLAGS", Const, 0}, {"EWINDOWS", Const, 0}, {"EWOULDBLOCK", Const, 0}, {"EXDEV", Const, 0}, {"EXFULL", Const, 0}, {"EXTA", Const, 0}, {"EXTB", Const, 0}, {"EXTPROC", Const, 0}, {"Environ", Func, 0}, {"EpollCreate", Func, 0}, {"EpollCreate1", Func, 0}, {"EpollCtl", Func, 0}, {"EpollEvent", Type, 0}, {"EpollEvent.Events", Field, 0}, {"EpollEvent.Fd", Field, 0}, {"EpollEvent.Pad", Field, 0}, {"EpollEvent.PadFd", Field, 0}, {"EpollWait", Func, 0}, {"Errno", Type, 0}, {"EscapeArg", Func, 0}, {"Exchangedata", Func, 0}, {"Exec", Func, 0}, {"Exit", Func, 0}, {"ExitProcess", Func, 0}, {"FD_CLOEXEC", Const, 0}, {"FD_SETSIZE", Const, 0}, {"FILE_ACTION_ADDED", Const, 0}, {"FILE_ACTION_MODIFIED", Const, 0}, {"FILE_ACTION_REMOVED", Const, 0}, {"FILE_ACTION_RENAMED_NEW_NAME", Const, 0}, {"FILE_ACTION_RENAMED_OLD_NAME", Const, 0}, {"FILE_APPEND_DATA", Const, 0}, {"FILE_ATTRIBUTE_ARCHIVE", Const, 0}, {"FILE_ATTRIBUTE_DIRECTORY", Const, 0}, {"FILE_ATTRIBUTE_HIDDEN", Const, 0}, {"FILE_ATTRIBUTE_NORMAL", Const, 0}, {"FILE_ATTRIBUTE_READONLY", Const, 0}, {"FILE_ATTRIBUTE_REPARSE_POINT", Const, 4}, {"FILE_ATTRIBUTE_SYSTEM", Const, 0}, {"FILE_BEGIN", Const, 0}, {"FILE_CURRENT", Const, 0}, {"FILE_END", Const, 0}, {"FILE_FLAG_BACKUP_SEMANTICS", Const, 0}, {"FILE_FLAG_OPEN_REPARSE_POINT", Const, 4}, {"FILE_FLAG_OVERLAPPED", Const, 0}, {"FILE_LIST_DIRECTORY", Const, 0}, {"FILE_MAP_COPY", Const, 0}, {"FILE_MAP_EXECUTE", Const, 0}, {"FILE_MAP_READ", Const, 0}, {"FILE_MAP_WRITE", Const, 0}, {"FILE_NOTIFY_CHANGE_ATTRIBUTES", Const, 0}, {"FILE_NOTIFY_CHANGE_CREATION", Const, 0}, {"FILE_NOTIFY_CHANGE_DIR_NAME", Const, 0}, {"FILE_NOTIFY_CHANGE_FILE_NAME", Const, 0}, {"FILE_NOTIFY_CHANGE_LAST_ACCESS", Const, 0}, {"FILE_NOTIFY_CHANGE_LAST_WRITE", Const, 0}, {"FILE_NOTIFY_CHANGE_SIZE", Const, 0}, {"FILE_SHARE_DELETE", Const, 0}, {"FILE_SHARE_READ", Const, 0}, {"FILE_SHARE_WRITE", Const, 0}, {"FILE_SKIP_COMPLETION_PORT_ON_SUCCESS", Const, 2}, {"FILE_SKIP_SET_EVENT_ON_HANDLE", Const, 2}, {"FILE_TYPE_CHAR", Const, 0}, {"FILE_TYPE_DISK", Const, 0}, {"FILE_TYPE_PIPE", Const, 0}, {"FILE_TYPE_REMOTE", Const, 0}, {"FILE_TYPE_UNKNOWN", Const, 0}, {"FILE_WRITE_ATTRIBUTES", Const, 0}, {"FLUSHO", Const, 0}, {"FORMAT_MESSAGE_ALLOCATE_BUFFER", Const, 0}, {"FORMAT_MESSAGE_ARGUMENT_ARRAY", Const, 0}, {"FORMAT_MESSAGE_FROM_HMODULE", Const, 0}, {"FORMAT_MESSAGE_FROM_STRING", Const, 0}, {"FORMAT_MESSAGE_FROM_SYSTEM", Const, 0}, {"FORMAT_MESSAGE_IGNORE_INSERTS", Const, 0}, {"FORMAT_MESSAGE_MAX_WIDTH_MASK", Const, 0}, {"FSCTL_GET_REPARSE_POINT", Const, 4}, {"F_ADDFILESIGS", Const, 0}, {"F_ADDSIGS", Const, 0}, {"F_ALLOCATEALL", Const, 0}, {"F_ALLOCATECONTIG", Const, 0}, {"F_CANCEL", Const, 0}, {"F_CHKCLEAN", Const, 0}, {"F_CLOSEM", Const, 1}, {"F_DUP2FD", Const, 0}, {"F_DUP2FD_CLOEXEC", Const, 1}, {"F_DUPFD", Const, 0}, {"F_DUPFD_CLOEXEC", Const, 0}, {"F_EXLCK", Const, 0}, {"F_FINDSIGS", Const, 16}, {"F_FLUSH_DATA", Const, 0}, {"F_FREEZE_FS", Const, 0}, {"F_FSCTL", Const, 1}, {"F_FSDIRMASK", Const, 1}, {"F_FSIN", Const, 1}, {"F_FSINOUT", Const, 1}, {"F_FSOUT", Const, 1}, {"F_FSPRIV", Const, 1}, {"F_FSVOID", Const, 1}, {"F_FULLFSYNC", Const, 0}, {"F_GETCODEDIR", Const, 16}, {"F_GETFD", Const, 0}, {"F_GETFL", Const, 0}, {"F_GETLEASE", Const, 0}, {"F_GETLK", Const, 0}, {"F_GETLK64", Const, 0}, {"F_GETLKPID", Const, 0}, {"F_GETNOSIGPIPE", Const, 0}, {"F_GETOWN", Const, 0}, {"F_GETOWN_EX", Const, 0}, {"F_GETPATH", Const, 0}, {"F_GETPATH_MTMINFO", Const, 0}, {"F_GETPIPE_SZ", Const, 0}, {"F_GETPROTECTIONCLASS", Const, 0}, {"F_GETPROTECTIONLEVEL", Const, 16}, {"F_GETSIG", Const, 0}, {"F_GLOBAL_NOCACHE", Const, 0}, {"F_LOCK", Const, 0}, {"F_LOG2PHYS", Const, 0}, {"F_LOG2PHYS_EXT", Const, 0}, {"F_MARKDEPENDENCY", Const, 0}, {"F_MAXFD", Const, 1}, {"F_NOCACHE", Const, 0}, {"F_NODIRECT", Const, 0}, {"F_NOTIFY", Const, 0}, {"F_OGETLK", Const, 0}, {"F_OK", Const, 0}, {"F_OSETLK", Const, 0}, {"F_OSETLKW", Const, 0}, {"F_PARAM_MASK", Const, 1}, {"F_PARAM_MAX", Const, 1}, {"F_PATHPKG_CHECK", Const, 0}, {"F_PEOFPOSMODE", Const, 0}, {"F_PREALLOCATE", Const, 0}, {"F_RDADVISE", Const, 0}, {"F_RDAHEAD", Const, 0}, {"F_RDLCK", Const, 0}, {"F_READAHEAD", Const, 0}, {"F_READBOOTSTRAP", Const, 0}, {"F_SETBACKINGSTORE", Const, 0}, {"F_SETFD", Const, 0}, {"F_SETFL", Const, 0}, {"F_SETLEASE", Const, 0}, {"F_SETLK", Const, 0}, {"F_SETLK64", Const, 0}, {"F_SETLKW", Const, 0}, {"F_SETLKW64", Const, 0}, {"F_SETLKWTIMEOUT", Const, 16}, {"F_SETLK_REMOTE", Const, 0}, {"F_SETNOSIGPIPE", Const, 0}, {"F_SETOWN", Const, 0}, {"F_SETOWN_EX", Const, 0}, {"F_SETPIPE_SZ", Const, 0}, {"F_SETPROTECTIONCLASS", Const, 0}, {"F_SETSIG", Const, 0}, {"F_SETSIZE", Const, 0}, {"F_SHLCK", Const, 0}, {"F_SINGLE_WRITER", Const, 16}, {"F_TEST", Const, 0}, {"F_THAW_FS", Const, 0}, {"F_TLOCK", Const, 0}, {"F_TRANSCODEKEY", Const, 16}, {"F_ULOCK", Const, 0}, {"F_UNLCK", Const, 0}, {"F_UNLCKSYS", Const, 0}, {"F_VOLPOSMODE", Const, 0}, {"F_WRITEBOOTSTRAP", Const, 0}, {"F_WRLCK", Const, 0}, {"Faccessat", Func, 0}, {"Fallocate", Func, 0}, {"Fbootstraptransfer_t", Type, 0}, {"Fbootstraptransfer_t.Buffer", Field, 0}, {"Fbootstraptransfer_t.Length", Field, 0}, {"Fbootstraptransfer_t.Offset", Field, 0}, {"Fchdir", Func, 0}, {"Fchflags", Func, 0}, {"Fchmod", Func, 0}, {"Fchmodat", Func, 0}, {"Fchown", Func, 0}, {"Fchownat", Func, 0}, {"FcntlFlock", Func, 3}, {"FdSet", Type, 0}, {"FdSet.Bits", Field, 0}, {"FdSet.X__fds_bits", Field, 0}, {"Fdatasync", Func, 0}, {"FileNotifyInformation", Type, 0}, {"FileNotifyInformation.Action", Field, 0}, {"FileNotifyInformation.FileName", Field, 0}, {"FileNotifyInformation.FileNameLength", Field, 0}, {"FileNotifyInformation.NextEntryOffset", Field, 0}, {"Filetime", Type, 0}, {"Filetime.HighDateTime", Field, 0}, {"Filetime.LowDateTime", Field, 0}, {"FindClose", Func, 0}, {"FindFirstFile", Func, 0}, {"FindNextFile", Func, 0}, {"Flock", Func, 0}, {"Flock_t", Type, 0}, {"Flock_t.Len", Field, 0}, {"Flock_t.Pad_cgo_0", Field, 0}, {"Flock_t.Pad_cgo_1", Field, 3}, {"Flock_t.Pid", Field, 0}, {"Flock_t.Start", Field, 0}, {"Flock_t.Sysid", Field, 0}, {"Flock_t.Type", Field, 0}, {"Flock_t.Whence", Field, 0}, {"FlushBpf", Func, 0}, {"FlushFileBuffers", Func, 0}, {"FlushViewOfFile", Func, 0}, {"ForkExec", Func, 0}, {"ForkLock", Var, 0}, {"FormatMessage", Func, 0}, {"Fpathconf", Func, 0}, {"FreeAddrInfoW", Func, 1}, {"FreeEnvironmentStrings", Func, 0}, {"FreeLibrary", Func, 0}, {"Fsid", Type, 0}, {"Fsid.Val", Field, 0}, {"Fsid.X__fsid_val", Field, 2}, {"Fsid.X__val", Field, 0}, {"Fstat", Func, 0}, {"Fstatat", Func, 12}, {"Fstatfs", Func, 0}, {"Fstore_t", Type, 0}, {"Fstore_t.Bytesalloc", Field, 0}, {"Fstore_t.Flags", Field, 0}, {"Fstore_t.Length", Field, 0}, {"Fstore_t.Offset", Field, 0}, {"Fstore_t.Posmode", Field, 0}, {"Fsync", Func, 0}, {"Ftruncate", Func, 0}, {"FullPath", Func, 4}, {"Futimes", Func, 0}, {"Futimesat", Func, 0}, {"GENERIC_ALL", Const, 0}, {"GENERIC_EXECUTE", Const, 0}, {"GENERIC_READ", Const, 0}, {"GENERIC_WRITE", Const, 0}, {"GUID", Type, 1}, {"GUID.Data1", Field, 1}, {"GUID.Data2", Field, 1}, {"GUID.Data3", Field, 1}, {"GUID.Data4", Field, 1}, {"GetAcceptExSockaddrs", Func, 0}, {"GetAdaptersInfo", Func, 0}, {"GetAddrInfoW", Func, 1}, {"GetCommandLine", Func, 0}, {"GetComputerName", Func, 0}, {"GetConsoleMode", Func, 1}, {"GetCurrentDirectory", Func, 0}, {"GetCurrentProcess", Func, 0}, {"GetEnvironmentStrings", Func, 0}, {"GetEnvironmentVariable", Func, 0}, {"GetExitCodeProcess", Func, 0}, {"GetFileAttributes", Func, 0}, {"GetFileAttributesEx", Func, 0}, {"GetFileExInfoStandard", Const, 0}, {"GetFileExMaxInfoLevel", Const, 0}, {"GetFileInformationByHandle", Func, 0}, {"GetFileType", Func, 0}, {"GetFullPathName", Func, 0}, {"GetHostByName", Func, 0}, {"GetIfEntry", Func, 0}, {"GetLastError", Func, 0}, {"GetLengthSid", Func, 0}, {"GetLongPathName", Func, 0}, {"GetProcAddress", Func, 0}, {"GetProcessTimes", Func, 0}, {"GetProtoByName", Func, 0}, {"GetQueuedCompletionStatus", Func, 0}, {"GetServByName", Func, 0}, {"GetShortPathName", Func, 0}, {"GetStartupInfo", Func, 0}, {"GetStdHandle", Func, 0}, {"GetSystemTimeAsFileTime", Func, 0}, {"GetTempPath", Func, 0}, {"GetTimeZoneInformation", Func, 0}, {"GetTokenInformation", Func, 0}, {"GetUserNameEx", Func, 0}, {"GetUserProfileDirectory", Func, 0}, {"GetVersion", Func, 0}, {"Getcwd", Func, 0}, {"Getdents", Func, 0}, {"Getdirentries", Func, 0}, {"Getdtablesize", Func, 0}, {"Getegid", Func, 0}, {"Getenv", Func, 0}, {"Geteuid", Func, 0}, {"Getfsstat", Func, 0}, {"Getgid", Func, 0}, {"Getgroups", Func, 0}, {"Getpagesize", Func, 0}, {"Getpeername", Func, 0}, {"Getpgid", Func, 0}, {"Getpgrp", Func, 0}, {"Getpid", Func, 0}, {"Getppid", Func, 0}, {"Getpriority", Func, 0}, {"Getrlimit", Func, 0}, {"Getrusage", Func, 0}, {"Getsid", Func, 0}, {"Getsockname", Func, 0}, {"Getsockopt", Func, 1}, {"GetsockoptByte", Func, 0}, {"GetsockoptICMPv6Filter", Func, 2}, {"GetsockoptIPMreq", Func, 0}, {"GetsockoptIPMreqn", Func, 0}, {"GetsockoptIPv6MTUInfo", Func, 2}, {"GetsockoptIPv6Mreq", Func, 0}, {"GetsockoptInet4Addr", Func, 0}, {"GetsockoptInt", Func, 0}, {"GetsockoptUcred", Func, 1}, {"Gettid", Func, 0}, {"Gettimeofday", Func, 0}, {"Getuid", Func, 0}, {"Getwd", Func, 0}, {"Getxattr", Func, 1}, {"HANDLE_FLAG_INHERIT", Const, 0}, {"HKEY_CLASSES_ROOT", Const, 0}, {"HKEY_CURRENT_CONFIG", Const, 0}, {"HKEY_CURRENT_USER", Const, 0}, {"HKEY_DYN_DATA", Const, 0}, {"HKEY_LOCAL_MACHINE", Const, 0}, {"HKEY_PERFORMANCE_DATA", Const, 0}, {"HKEY_USERS", Const, 0}, {"HUPCL", Const, 0}, {"Handle", Type, 0}, {"Hostent", Type, 0}, {"Hostent.AddrList", Field, 0}, {"Hostent.AddrType", Field, 0}, {"Hostent.Aliases", Field, 0}, {"Hostent.Length", Field, 0}, {"Hostent.Name", Field, 0}, {"ICANON", Const, 0}, {"ICMP6_FILTER", Const, 2}, {"ICMPV6_FILTER", Const, 2}, {"ICMPv6Filter", Type, 2}, {"ICMPv6Filter.Data", Field, 2}, {"ICMPv6Filter.Filt", Field, 2}, {"ICRNL", Const, 0}, {"IEXTEN", Const, 0}, {"IFAN_ARRIVAL", Const, 1}, {"IFAN_DEPARTURE", Const, 1}, {"IFA_ADDRESS", Const, 0}, {"IFA_ANYCAST", Const, 0}, {"IFA_BROADCAST", Const, 0}, {"IFA_CACHEINFO", Const, 0}, {"IFA_F_DADFAILED", Const, 0}, {"IFA_F_DEPRECATED", Const, 0}, {"IFA_F_HOMEADDRESS", Const, 0}, {"IFA_F_NODAD", Const, 0}, {"IFA_F_OPTIMISTIC", Const, 0}, {"IFA_F_PERMANENT", Const, 0}, {"IFA_F_SECONDARY", Const, 0}, {"IFA_F_TEMPORARY", Const, 0}, {"IFA_F_TENTATIVE", Const, 0}, {"IFA_LABEL", Const, 0}, {"IFA_LOCAL", Const, 0}, {"IFA_MAX", Const, 0}, {"IFA_MULTICAST", Const, 0}, {"IFA_ROUTE", Const, 1}, {"IFA_UNSPEC", Const, 0}, {"IFF_ALLMULTI", Const, 0}, {"IFF_ALTPHYS", Const, 0}, {"IFF_AUTOMEDIA", Const, 0}, {"IFF_BROADCAST", Const, 0}, {"IFF_CANTCHANGE", Const, 0}, {"IFF_CANTCONFIG", Const, 1}, {"IFF_DEBUG", Const, 0}, {"IFF_DRV_OACTIVE", Const, 0}, {"IFF_DRV_RUNNING", Const, 0}, {"IFF_DYING", Const, 0}, {"IFF_DYNAMIC", Const, 0}, {"IFF_LINK0", Const, 0}, {"IFF_LINK1", Const, 0}, {"IFF_LINK2", Const, 0}, {"IFF_LOOPBACK", Const, 0}, {"IFF_MASTER", Const, 0}, {"IFF_MONITOR", Const, 0}, {"IFF_MULTICAST", Const, 0}, {"IFF_NOARP", Const, 0}, {"IFF_NOTRAILERS", Const, 0}, {"IFF_NO_PI", Const, 0}, {"IFF_OACTIVE", Const, 0}, {"IFF_ONE_QUEUE", Const, 0}, {"IFF_POINTOPOINT", Const, 0}, {"IFF_POINTTOPOINT", Const, 0}, {"IFF_PORTSEL", Const, 0}, {"IFF_PPROMISC", Const, 0}, {"IFF_PROMISC", Const, 0}, {"IFF_RENAMING", Const, 0}, {"IFF_RUNNING", Const, 0}, {"IFF_SIMPLEX", Const, 0}, {"IFF_SLAVE", Const, 0}, {"IFF_SMART", Const, 0}, {"IFF_STATICARP", Const, 0}, {"IFF_TAP", Const, 0}, {"IFF_TUN", Const, 0}, {"IFF_TUN_EXCL", Const, 0}, {"IFF_UP", Const, 0}, {"IFF_VNET_HDR", Const, 0}, {"IFLA_ADDRESS", Const, 0}, {"IFLA_BROADCAST", Const, 0}, {"IFLA_COST", Const, 0}, {"IFLA_IFALIAS", Const, 0}, {"IFLA_IFNAME", Const, 0}, {"IFLA_LINK", Const, 0}, {"IFLA_LINKINFO", Const, 0}, {"IFLA_LINKMODE", Const, 0}, {"IFLA_MAP", Const, 0}, {"IFLA_MASTER", Const, 0}, {"IFLA_MAX", Const, 0}, {"IFLA_MTU", Const, 0}, {"IFLA_NET_NS_PID", Const, 0}, {"IFLA_OPERSTATE", Const, 0}, {"IFLA_PRIORITY", Const, 0}, {"IFLA_PROTINFO", Const, 0}, {"IFLA_QDISC", Const, 0}, {"IFLA_STATS", Const, 0}, {"IFLA_TXQLEN", Const, 0}, {"IFLA_UNSPEC", Const, 0}, {"IFLA_WEIGHT", Const, 0}, {"IFLA_WIRELESS", Const, 0}, {"IFNAMSIZ", Const, 0}, {"IFT_1822", Const, 0}, {"IFT_A12MPPSWITCH", Const, 0}, {"IFT_AAL2", Const, 0}, {"IFT_AAL5", Const, 0}, {"IFT_ADSL", Const, 0}, {"IFT_AFLANE8023", Const, 0}, {"IFT_AFLANE8025", Const, 0}, {"IFT_ARAP", Const, 0}, {"IFT_ARCNET", Const, 0}, {"IFT_ARCNETPLUS", Const, 0}, {"IFT_ASYNC", Const, 0}, {"IFT_ATM", Const, 0}, {"IFT_ATMDXI", Const, 0}, {"IFT_ATMFUNI", Const, 0}, {"IFT_ATMIMA", Const, 0}, {"IFT_ATMLOGICAL", Const, 0}, {"IFT_ATMRADIO", Const, 0}, {"IFT_ATMSUBINTERFACE", Const, 0}, {"IFT_ATMVCIENDPT", Const, 0}, {"IFT_ATMVIRTUAL", Const, 0}, {"IFT_BGPPOLICYACCOUNTING", Const, 0}, {"IFT_BLUETOOTH", Const, 1}, {"IFT_BRIDGE", Const, 0}, {"IFT_BSC", Const, 0}, {"IFT_CARP", Const, 0}, {"IFT_CCTEMUL", Const, 0}, {"IFT_CELLULAR", Const, 0}, {"IFT_CEPT", Const, 0}, {"IFT_CES", Const, 0}, {"IFT_CHANNEL", Const, 0}, {"IFT_CNR", Const, 0}, {"IFT_COFFEE", Const, 0}, {"IFT_COMPOSITELINK", Const, 0}, {"IFT_DCN", Const, 0}, {"IFT_DIGITALPOWERLINE", Const, 0}, {"IFT_DIGITALWRAPPEROVERHEADCHANNEL", Const, 0}, {"IFT_DLSW", Const, 0}, {"IFT_DOCSCABLEDOWNSTREAM", Const, 0}, {"IFT_DOCSCABLEMACLAYER", Const, 0}, {"IFT_DOCSCABLEUPSTREAM", Const, 0}, {"IFT_DOCSCABLEUPSTREAMCHANNEL", Const, 1}, {"IFT_DS0", Const, 0}, {"IFT_DS0BUNDLE", Const, 0}, {"IFT_DS1FDL", Const, 0}, {"IFT_DS3", Const, 0}, {"IFT_DTM", Const, 0}, {"IFT_DUMMY", Const, 1}, {"IFT_DVBASILN", Const, 0}, {"IFT_DVBASIOUT", Const, 0}, {"IFT_DVBRCCDOWNSTREAM", Const, 0}, {"IFT_DVBRCCMACLAYER", Const, 0}, {"IFT_DVBRCCUPSTREAM", Const, 0}, {"IFT_ECONET", Const, 1}, {"IFT_ENC", Const, 0}, {"IFT_EON", Const, 0}, {"IFT_EPLRS", Const, 0}, {"IFT_ESCON", Const, 0}, {"IFT_ETHER", Const, 0}, {"IFT_FAITH", Const, 0}, {"IFT_FAST", Const, 0}, {"IFT_FASTETHER", Const, 0}, {"IFT_FASTETHERFX", Const, 0}, {"IFT_FDDI", Const, 0}, {"IFT_FIBRECHANNEL", Const, 0}, {"IFT_FRAMERELAYINTERCONNECT", Const, 0}, {"IFT_FRAMERELAYMPI", Const, 0}, {"IFT_FRDLCIENDPT", Const, 0}, {"IFT_FRELAY", Const, 0}, {"IFT_FRELAYDCE", Const, 0}, {"IFT_FRF16MFRBUNDLE", Const, 0}, {"IFT_FRFORWARD", Const, 0}, {"IFT_G703AT2MB", Const, 0}, {"IFT_G703AT64K", Const, 0}, {"IFT_GIF", Const, 0}, {"IFT_GIGABITETHERNET", Const, 0}, {"IFT_GR303IDT", Const, 0}, {"IFT_GR303RDT", Const, 0}, {"IFT_H323GATEKEEPER", Const, 0}, {"IFT_H323PROXY", Const, 0}, {"IFT_HDH1822", Const, 0}, {"IFT_HDLC", Const, 0}, {"IFT_HDSL2", Const, 0}, {"IFT_HIPERLAN2", Const, 0}, {"IFT_HIPPI", Const, 0}, {"IFT_HIPPIINTERFACE", Const, 0}, {"IFT_HOSTPAD", Const, 0}, {"IFT_HSSI", Const, 0}, {"IFT_HY", Const, 0}, {"IFT_IBM370PARCHAN", Const, 0}, {"IFT_IDSL", Const, 0}, {"IFT_IEEE1394", Const, 0}, {"IFT_IEEE80211", Const, 0}, {"IFT_IEEE80212", Const, 0}, {"IFT_IEEE8023ADLAG", Const, 0}, {"IFT_IFGSN", Const, 0}, {"IFT_IMT", Const, 0}, {"IFT_INFINIBAND", Const, 1}, {"IFT_INTERLEAVE", Const, 0}, {"IFT_IP", Const, 0}, {"IFT_IPFORWARD", Const, 0}, {"IFT_IPOVERATM", Const, 0}, {"IFT_IPOVERCDLC", Const, 0}, {"IFT_IPOVERCLAW", Const, 0}, {"IFT_IPSWITCH", Const, 0}, {"IFT_IPXIP", Const, 0}, {"IFT_ISDN", Const, 0}, {"IFT_ISDNBASIC", Const, 0}, {"IFT_ISDNPRIMARY", Const, 0}, {"IFT_ISDNS", Const, 0}, {"IFT_ISDNU", Const, 0}, {"IFT_ISO88022LLC", Const, 0}, {"IFT_ISO88023", Const, 0}, {"IFT_ISO88024", Const, 0}, {"IFT_ISO88025", Const, 0}, {"IFT_ISO88025CRFPINT", Const, 0}, {"IFT_ISO88025DTR", Const, 0}, {"IFT_ISO88025FIBER", Const, 0}, {"IFT_ISO88026", Const, 0}, {"IFT_ISUP", Const, 0}, {"IFT_L2VLAN", Const, 0}, {"IFT_L3IPVLAN", Const, 0}, {"IFT_L3IPXVLAN", Const, 0}, {"IFT_LAPB", Const, 0}, {"IFT_LAPD", Const, 0}, {"IFT_LAPF", Const, 0}, {"IFT_LINEGROUP", Const, 1}, {"IFT_LOCALTALK", Const, 0}, {"IFT_LOOP", Const, 0}, {"IFT_MEDIAMAILOVERIP", Const, 0}, {"IFT_MFSIGLINK", Const, 0}, {"IFT_MIOX25", Const, 0}, {"IFT_MODEM", Const, 0}, {"IFT_MPC", Const, 0}, {"IFT_MPLS", Const, 0}, {"IFT_MPLSTUNNEL", Const, 0}, {"IFT_MSDSL", Const, 0}, {"IFT_MVL", Const, 0}, {"IFT_MYRINET", Const, 0}, {"IFT_NFAS", Const, 0}, {"IFT_NSIP", Const, 0}, {"IFT_OPTICALCHANNEL", Const, 0}, {"IFT_OPTICALTRANSPORT", Const, 0}, {"IFT_OTHER", Const, 0}, {"IFT_P10", Const, 0}, {"IFT_P80", Const, 0}, {"IFT_PARA", Const, 0}, {"IFT_PDP", Const, 0}, {"IFT_PFLOG", Const, 0}, {"IFT_PFLOW", Const, 1}, {"IFT_PFSYNC", Const, 0}, {"IFT_PLC", Const, 0}, {"IFT_PON155", Const, 1}, {"IFT_PON622", Const, 1}, {"IFT_POS", Const, 0}, {"IFT_PPP", Const, 0}, {"IFT_PPPMULTILINKBUNDLE", Const, 0}, {"IFT_PROPATM", Const, 1}, {"IFT_PROPBWAP2MP", Const, 0}, {"IFT_PROPCNLS", Const, 0}, {"IFT_PROPDOCSWIRELESSDOWNSTREAM", Const, 0}, {"IFT_PROPDOCSWIRELESSMACLAYER", Const, 0}, {"IFT_PROPDOCSWIRELESSUPSTREAM", Const, 0}, {"IFT_PROPMUX", Const, 0}, {"IFT_PROPVIRTUAL", Const, 0}, {"IFT_PROPWIRELESSP2P", Const, 0}, {"IFT_PTPSERIAL", Const, 0}, {"IFT_PVC", Const, 0}, {"IFT_Q2931", Const, 1}, {"IFT_QLLC", Const, 0}, {"IFT_RADIOMAC", Const, 0}, {"IFT_RADSL", Const, 0}, {"IFT_REACHDSL", Const, 0}, {"IFT_RFC1483", Const, 0}, {"IFT_RS232", Const, 0}, {"IFT_RSRB", Const, 0}, {"IFT_SDLC", Const, 0}, {"IFT_SDSL", Const, 0}, {"IFT_SHDSL", Const, 0}, {"IFT_SIP", Const, 0}, {"IFT_SIPSIG", Const, 1}, {"IFT_SIPTG", Const, 1}, {"IFT_SLIP", Const, 0}, {"IFT_SMDSDXI", Const, 0}, {"IFT_SMDSICIP", Const, 0}, {"IFT_SONET", Const, 0}, {"IFT_SONETOVERHEADCHANNEL", Const, 0}, {"IFT_SONETPATH", Const, 0}, {"IFT_SONETVT", Const, 0}, {"IFT_SRP", Const, 0}, {"IFT_SS7SIGLINK", Const, 0}, {"IFT_STACKTOSTACK", Const, 0}, {"IFT_STARLAN", Const, 0}, {"IFT_STF", Const, 0}, {"IFT_T1", Const, 0}, {"IFT_TDLC", Const, 0}, {"IFT_TELINK", Const, 1}, {"IFT_TERMPAD", Const, 0}, {"IFT_TR008", Const, 0}, {"IFT_TRANSPHDLC", Const, 0}, {"IFT_TUNNEL", Const, 0}, {"IFT_ULTRA", Const, 0}, {"IFT_USB", Const, 0}, {"IFT_V11", Const, 0}, {"IFT_V35", Const, 0}, {"IFT_V36", Const, 0}, {"IFT_V37", Const, 0}, {"IFT_VDSL", Const, 0}, {"IFT_VIRTUALIPADDRESS", Const, 0}, {"IFT_VIRTUALTG", Const, 1}, {"IFT_VOICEDID", Const, 1}, {"IFT_VOICEEM", Const, 0}, {"IFT_VOICEEMFGD", Const, 1}, {"IFT_VOICEENCAP", Const, 0}, {"IFT_VOICEFGDEANA", Const, 1}, {"IFT_VOICEFXO", Const, 0}, {"IFT_VOICEFXS", Const, 0}, {"IFT_VOICEOVERATM", Const, 0}, {"IFT_VOICEOVERCABLE", Const, 1}, {"IFT_VOICEOVERFRAMERELAY", Const, 0}, {"IFT_VOICEOVERIP", Const, 0}, {"IFT_X213", Const, 0}, {"IFT_X25", Const, 0}, {"IFT_X25DDN", Const, 0}, {"IFT_X25HUNTGROUP", Const, 0}, {"IFT_X25MLP", Const, 0}, {"IFT_X25PLE", Const, 0}, {"IFT_XETHER", Const, 0}, {"IGNBRK", Const, 0}, {"IGNCR", Const, 0}, {"IGNORE", Const, 0}, {"IGNPAR", Const, 0}, {"IMAXBEL", Const, 0}, {"INFINITE", Const, 0}, {"INLCR", Const, 0}, {"INPCK", Const, 0}, {"INVALID_FILE_ATTRIBUTES", Const, 0}, {"IN_ACCESS", Const, 0}, {"IN_ALL_EVENTS", Const, 0}, {"IN_ATTRIB", Const, 0}, {"IN_CLASSA_HOST", Const, 0}, {"IN_CLASSA_MAX", Const, 0}, {"IN_CLASSA_NET", Const, 0}, {"IN_CLASSA_NSHIFT", Const, 0}, {"IN_CLASSB_HOST", Const, 0}, {"IN_CLASSB_MAX", Const, 0}, {"IN_CLASSB_NET", Const, 0}, {"IN_CLASSB_NSHIFT", Const, 0}, {"IN_CLASSC_HOST", Const, 0}, {"IN_CLASSC_NET", Const, 0}, {"IN_CLASSC_NSHIFT", Const, 0}, {"IN_CLASSD_HOST", Const, 0}, {"IN_CLASSD_NET", Const, 0}, {"IN_CLASSD_NSHIFT", Const, 0}, {"IN_CLOEXEC", Const, 0}, {"IN_CLOSE", Const, 0}, {"IN_CLOSE_NOWRITE", Const, 0}, {"IN_CLOSE_WRITE", Const, 0}, {"IN_CREATE", Const, 0}, {"IN_DELETE", Const, 0}, {"IN_DELETE_SELF", Const, 0}, {"IN_DONT_FOLLOW", Const, 0}, {"IN_EXCL_UNLINK", Const, 0}, {"IN_IGNORED", Const, 0}, {"IN_ISDIR", Const, 0}, {"IN_LINKLOCALNETNUM", Const, 0}, {"IN_LOOPBACKNET", Const, 0}, {"IN_MASK_ADD", Const, 0}, {"IN_MODIFY", Const, 0}, {"IN_MOVE", Const, 0}, {"IN_MOVED_FROM", Const, 0}, {"IN_MOVED_TO", Const, 0}, {"IN_MOVE_SELF", Const, 0}, {"IN_NONBLOCK", Const, 0}, {"IN_ONESHOT", Const, 0}, {"IN_ONLYDIR", Const, 0}, {"IN_OPEN", Const, 0}, {"IN_Q_OVERFLOW", Const, 0}, {"IN_RFC3021_HOST", Const, 1}, {"IN_RFC3021_MASK", Const, 1}, {"IN_RFC3021_NET", Const, 1}, {"IN_RFC3021_NSHIFT", Const, 1}, {"IN_UNMOUNT", Const, 0}, {"IOC_IN", Const, 1}, {"IOC_INOUT", Const, 1}, {"IOC_OUT", Const, 1}, {"IOC_VENDOR", Const, 3}, {"IOC_WS2", Const, 1}, {"IO_REPARSE_TAG_SYMLINK", Const, 4}, {"IPMreq", Type, 0}, {"IPMreq.Interface", Field, 0}, {"IPMreq.Multiaddr", Field, 0}, {"IPMreqn", Type, 0}, {"IPMreqn.Address", Field, 0}, {"IPMreqn.Ifindex", Field, 0}, {"IPMreqn.Multiaddr", Field, 0}, {"IPPROTO_3PC", Const, 0}, {"IPPROTO_ADFS", Const, 0}, {"IPPROTO_AH", Const, 0}, {"IPPROTO_AHIP", Const, 0}, {"IPPROTO_APES", Const, 0}, {"IPPROTO_ARGUS", Const, 0}, {"IPPROTO_AX25", Const, 0}, {"IPPROTO_BHA", Const, 0}, {"IPPROTO_BLT", Const, 0}, {"IPPROTO_BRSATMON", Const, 0}, {"IPPROTO_CARP", Const, 0}, {"IPPROTO_CFTP", Const, 0}, {"IPPROTO_CHAOS", Const, 0}, {"IPPROTO_CMTP", Const, 0}, {"IPPROTO_COMP", Const, 0}, {"IPPROTO_CPHB", Const, 0}, {"IPPROTO_CPNX", Const, 0}, {"IPPROTO_DCCP", Const, 0}, {"IPPROTO_DDP", Const, 0}, {"IPPROTO_DGP", Const, 0}, {"IPPROTO_DIVERT", Const, 0}, {"IPPROTO_DIVERT_INIT", Const, 3}, {"IPPROTO_DIVERT_RESP", Const, 3}, {"IPPROTO_DONE", Const, 0}, {"IPPROTO_DSTOPTS", Const, 0}, {"IPPROTO_EGP", Const, 0}, {"IPPROTO_EMCON", Const, 0}, {"IPPROTO_ENCAP", Const, 0}, {"IPPROTO_EON", Const, 0}, {"IPPROTO_ESP", Const, 0}, {"IPPROTO_ETHERIP", Const, 0}, {"IPPROTO_FRAGMENT", Const, 0}, {"IPPROTO_GGP", Const, 0}, {"IPPROTO_GMTP", Const, 0}, {"IPPROTO_GRE", Const, 0}, {"IPPROTO_HELLO", Const, 0}, {"IPPROTO_HMP", Const, 0}, {"IPPROTO_HOPOPTS", Const, 0}, {"IPPROTO_ICMP", Const, 0}, {"IPPROTO_ICMPV6", Const, 0}, {"IPPROTO_IDP", Const, 0}, {"IPPROTO_IDPR", Const, 0}, {"IPPROTO_IDRP", Const, 0}, {"IPPROTO_IGMP", Const, 0}, {"IPPROTO_IGP", Const, 0}, {"IPPROTO_IGRP", Const, 0}, {"IPPROTO_IL", Const, 0}, {"IPPROTO_INLSP", Const, 0}, {"IPPROTO_INP", Const, 0}, {"IPPROTO_IP", Const, 0}, {"IPPROTO_IPCOMP", Const, 0}, {"IPPROTO_IPCV", Const, 0}, {"IPPROTO_IPEIP", Const, 0}, {"IPPROTO_IPIP", Const, 0}, {"IPPROTO_IPPC", Const, 0}, {"IPPROTO_IPV4", Const, 0}, {"IPPROTO_IPV6", Const, 0}, {"IPPROTO_IPV6_ICMP", Const, 1}, {"IPPROTO_IRTP", Const, 0}, {"IPPROTO_KRYPTOLAN", Const, 0}, {"IPPROTO_LARP", Const, 0}, {"IPPROTO_LEAF1", Const, 0}, {"IPPROTO_LEAF2", Const, 0}, {"IPPROTO_MAX", Const, 0}, {"IPPROTO_MAXID", Const, 0}, {"IPPROTO_MEAS", Const, 0}, {"IPPROTO_MH", Const, 1}, {"IPPROTO_MHRP", Const, 0}, {"IPPROTO_MICP", Const, 0}, {"IPPROTO_MOBILE", Const, 0}, {"IPPROTO_MPLS", Const, 1}, {"IPPROTO_MTP", Const, 0}, {"IPPROTO_MUX", Const, 0}, {"IPPROTO_ND", Const, 0}, {"IPPROTO_NHRP", Const, 0}, {"IPPROTO_NONE", Const, 0}, {"IPPROTO_NSP", Const, 0}, {"IPPROTO_NVPII", Const, 0}, {"IPPROTO_OLD_DIVERT", Const, 0}, {"IPPROTO_OSPFIGP", Const, 0}, {"IPPROTO_PFSYNC", Const, 0}, {"IPPROTO_PGM", Const, 0}, {"IPPROTO_PIGP", Const, 0}, {"IPPROTO_PIM", Const, 0}, {"IPPROTO_PRM", Const, 0}, {"IPPROTO_PUP", Const, 0}, {"IPPROTO_PVP", Const, 0}, {"IPPROTO_RAW", Const, 0}, {"IPPROTO_RCCMON", Const, 0}, {"IPPROTO_RDP", Const, 0}, {"IPPROTO_ROUTING", Const, 0}, {"IPPROTO_RSVP", Const, 0}, {"IPPROTO_RVD", Const, 0}, {"IPPROTO_SATEXPAK", Const, 0}, {"IPPROTO_SATMON", Const, 0}, {"IPPROTO_SCCSP", Const, 0}, {"IPPROTO_SCTP", Const, 0}, {"IPPROTO_SDRP", Const, 0}, {"IPPROTO_SEND", Const, 1}, {"IPPROTO_SEP", Const, 0}, {"IPPROTO_SKIP", Const, 0}, {"IPPROTO_SPACER", Const, 0}, {"IPPROTO_SRPC", Const, 0}, {"IPPROTO_ST", Const, 0}, {"IPPROTO_SVMTP", Const, 0}, {"IPPROTO_SWIPE", Const, 0}, {"IPPROTO_TCF", Const, 0}, {"IPPROTO_TCP", Const, 0}, {"IPPROTO_TLSP", Const, 0}, {"IPPROTO_TP", Const, 0}, {"IPPROTO_TPXX", Const, 0}, {"IPPROTO_TRUNK1", Const, 0}, {"IPPROTO_TRUNK2", Const, 0}, {"IPPROTO_TTP", Const, 0}, {"IPPROTO_UDP", Const, 0}, {"IPPROTO_UDPLITE", Const, 0}, {"IPPROTO_VINES", Const, 0}, {"IPPROTO_VISA", Const, 0}, {"IPPROTO_VMTP", Const, 0}, {"IPPROTO_VRRP", Const, 1}, {"IPPROTO_WBEXPAK", Const, 0}, {"IPPROTO_WBMON", Const, 0}, {"IPPROTO_WSN", Const, 0}, {"IPPROTO_XNET", Const, 0}, {"IPPROTO_XTP", Const, 0}, {"IPV6_2292DSTOPTS", Const, 0}, {"IPV6_2292HOPLIMIT", Const, 0}, {"IPV6_2292HOPOPTS", Const, 0}, {"IPV6_2292NEXTHOP", Const, 0}, {"IPV6_2292PKTINFO", Const, 0}, {"IPV6_2292PKTOPTIONS", Const, 0}, {"IPV6_2292RTHDR", Const, 0}, {"IPV6_ADDRFORM", Const, 0}, {"IPV6_ADD_MEMBERSHIP", Const, 0}, {"IPV6_AUTHHDR", Const, 0}, {"IPV6_AUTH_LEVEL", Const, 1}, {"IPV6_AUTOFLOWLABEL", Const, 0}, {"IPV6_BINDANY", Const, 0}, {"IPV6_BINDV6ONLY", Const, 0}, {"IPV6_BOUND_IF", Const, 0}, {"IPV6_CHECKSUM", Const, 0}, {"IPV6_DEFAULT_MULTICAST_HOPS", Const, 0}, {"IPV6_DEFAULT_MULTICAST_LOOP", Const, 0}, {"IPV6_DEFHLIM", Const, 0}, {"IPV6_DONTFRAG", Const, 0}, {"IPV6_DROP_MEMBERSHIP", Const, 0}, {"IPV6_DSTOPTS", Const, 0}, {"IPV6_ESP_NETWORK_LEVEL", Const, 1}, {"IPV6_ESP_TRANS_LEVEL", Const, 1}, {"IPV6_FAITH", Const, 0}, {"IPV6_FLOWINFO_MASK", Const, 0}, {"IPV6_FLOWLABEL_MASK", Const, 0}, {"IPV6_FRAGTTL", Const, 0}, {"IPV6_FW_ADD", Const, 0}, {"IPV6_FW_DEL", Const, 0}, {"IPV6_FW_FLUSH", Const, 0}, {"IPV6_FW_GET", Const, 0}, {"IPV6_FW_ZERO", Const, 0}, {"IPV6_HLIMDEC", Const, 0}, {"IPV6_HOPLIMIT", Const, 0}, {"IPV6_HOPOPTS", Const, 0}, {"IPV6_IPCOMP_LEVEL", Const, 1}, {"IPV6_IPSEC_POLICY", Const, 0}, {"IPV6_JOIN_ANYCAST", Const, 0}, {"IPV6_JOIN_GROUP", Const, 0}, {"IPV6_LEAVE_ANYCAST", Const, 0}, {"IPV6_LEAVE_GROUP", Const, 0}, {"IPV6_MAXHLIM", Const, 0}, {"IPV6_MAXOPTHDR", Const, 0}, {"IPV6_MAXPACKET", Const, 0}, {"IPV6_MAX_GROUP_SRC_FILTER", Const, 0}, {"IPV6_MAX_MEMBERSHIPS", Const, 0}, {"IPV6_MAX_SOCK_SRC_FILTER", Const, 0}, {"IPV6_MIN_MEMBERSHIPS", Const, 0}, {"IPV6_MMTU", Const, 0}, {"IPV6_MSFILTER", Const, 0}, {"IPV6_MTU", Const, 0}, {"IPV6_MTU_DISCOVER", Const, 0}, {"IPV6_MULTICAST_HOPS", Const, 0}, {"IPV6_MULTICAST_IF", Const, 0}, {"IPV6_MULTICAST_LOOP", Const, 0}, {"IPV6_NEXTHOP", Const, 0}, {"IPV6_OPTIONS", Const, 1}, {"IPV6_PATHMTU", Const, 0}, {"IPV6_PIPEX", Const, 1}, {"IPV6_PKTINFO", Const, 0}, {"IPV6_PMTUDISC_DO", Const, 0}, {"IPV6_PMTUDISC_DONT", Const, 0}, {"IPV6_PMTUDISC_PROBE", Const, 0}, {"IPV6_PMTUDISC_WANT", Const, 0}, {"IPV6_PORTRANGE", Const, 0}, {"IPV6_PORTRANGE_DEFAULT", Const, 0}, {"IPV6_PORTRANGE_HIGH", Const, 0}, {"IPV6_PORTRANGE_LOW", Const, 0}, {"IPV6_PREFER_TEMPADDR", Const, 0}, {"IPV6_RECVDSTOPTS", Const, 0}, {"IPV6_RECVDSTPORT", Const, 3}, {"IPV6_RECVERR", Const, 0}, {"IPV6_RECVHOPLIMIT", Const, 0}, {"IPV6_RECVHOPOPTS", Const, 0}, {"IPV6_RECVPATHMTU", Const, 0}, {"IPV6_RECVPKTINFO", Const, 0}, {"IPV6_RECVRTHDR", Const, 0}, {"IPV6_RECVTCLASS", Const, 0}, {"IPV6_ROUTER_ALERT", Const, 0}, {"IPV6_RTABLE", Const, 1}, {"IPV6_RTHDR", Const, 0}, {"IPV6_RTHDRDSTOPTS", Const, 0}, {"IPV6_RTHDR_LOOSE", Const, 0}, {"IPV6_RTHDR_STRICT", Const, 0}, {"IPV6_RTHDR_TYPE_0", Const, 0}, {"IPV6_RXDSTOPTS", Const, 0}, {"IPV6_RXHOPOPTS", Const, 0}, {"IPV6_SOCKOPT_RESERVED1", Const, 0}, {"IPV6_TCLASS", Const, 0}, {"IPV6_UNICAST_HOPS", Const, 0}, {"IPV6_USE_MIN_MTU", Const, 0}, {"IPV6_V6ONLY", Const, 0}, {"IPV6_VERSION", Const, 0}, {"IPV6_VERSION_MASK", Const, 0}, {"IPV6_XFRM_POLICY", Const, 0}, {"IP_ADD_MEMBERSHIP", Const, 0}, {"IP_ADD_SOURCE_MEMBERSHIP", Const, 0}, {"IP_AUTH_LEVEL", Const, 1}, {"IP_BINDANY", Const, 0}, {"IP_BLOCK_SOURCE", Const, 0}, {"IP_BOUND_IF", Const, 0}, {"IP_DEFAULT_MULTICAST_LOOP", Const, 0}, {"IP_DEFAULT_MULTICAST_TTL", Const, 0}, {"IP_DF", Const, 0}, {"IP_DIVERTFL", Const, 3}, {"IP_DONTFRAG", Const, 0}, {"IP_DROP_MEMBERSHIP", Const, 0}, {"IP_DROP_SOURCE_MEMBERSHIP", Const, 0}, {"IP_DUMMYNET3", Const, 0}, {"IP_DUMMYNET_CONFIGURE", Const, 0}, {"IP_DUMMYNET_DEL", Const, 0}, {"IP_DUMMYNET_FLUSH", Const, 0}, {"IP_DUMMYNET_GET", Const, 0}, {"IP_EF", Const, 1}, {"IP_ERRORMTU", Const, 1}, {"IP_ESP_NETWORK_LEVEL", Const, 1}, {"IP_ESP_TRANS_LEVEL", Const, 1}, {"IP_FAITH", Const, 0}, {"IP_FREEBIND", Const, 0}, {"IP_FW3", Const, 0}, {"IP_FW_ADD", Const, 0}, {"IP_FW_DEL", Const, 0}, {"IP_FW_FLUSH", Const, 0}, {"IP_FW_GET", Const, 0}, {"IP_FW_NAT_CFG", Const, 0}, {"IP_FW_NAT_DEL", Const, 0}, {"IP_FW_NAT_GET_CONFIG", Const, 0}, {"IP_FW_NAT_GET_LOG", Const, 0}, {"IP_FW_RESETLOG", Const, 0}, {"IP_FW_TABLE_ADD", Const, 0}, {"IP_FW_TABLE_DEL", Const, 0}, {"IP_FW_TABLE_FLUSH", Const, 0}, {"IP_FW_TABLE_GETSIZE", Const, 0}, {"IP_FW_TABLE_LIST", Const, 0}, {"IP_FW_ZERO", Const, 0}, {"IP_HDRINCL", Const, 0}, {"IP_IPCOMP_LEVEL", Const, 1}, {"IP_IPSECFLOWINFO", Const, 1}, {"IP_IPSEC_LOCAL_AUTH", Const, 1}, {"IP_IPSEC_LOCAL_CRED", Const, 1}, {"IP_IPSEC_LOCAL_ID", Const, 1}, {"IP_IPSEC_POLICY", Const, 0}, {"IP_IPSEC_REMOTE_AUTH", Const, 1}, {"IP_IPSEC_REMOTE_CRED", Const, 1}, {"IP_IPSEC_REMOTE_ID", Const, 1}, {"IP_MAXPACKET", Const, 0}, {"IP_MAX_GROUP_SRC_FILTER", Const, 0}, {"IP_MAX_MEMBERSHIPS", Const, 0}, {"IP_MAX_SOCK_MUTE_FILTER", Const, 0}, {"IP_MAX_SOCK_SRC_FILTER", Const, 0}, {"IP_MAX_SOURCE_FILTER", Const, 0}, {"IP_MF", Const, 0}, {"IP_MINFRAGSIZE", Const, 1}, {"IP_MINTTL", Const, 0}, {"IP_MIN_MEMBERSHIPS", Const, 0}, {"IP_MSFILTER", Const, 0}, {"IP_MSS", Const, 0}, {"IP_MTU", Const, 0}, {"IP_MTU_DISCOVER", Const, 0}, {"IP_MULTICAST_IF", Const, 0}, {"IP_MULTICAST_IFINDEX", Const, 0}, {"IP_MULTICAST_LOOP", Const, 0}, {"IP_MULTICAST_TTL", Const, 0}, {"IP_MULTICAST_VIF", Const, 0}, {"IP_NAT__XXX", Const, 0}, {"IP_OFFMASK", Const, 0}, {"IP_OLD_FW_ADD", Const, 0}, {"IP_OLD_FW_DEL", Const, 0}, {"IP_OLD_FW_FLUSH", Const, 0}, {"IP_OLD_FW_GET", Const, 0}, {"IP_OLD_FW_RESETLOG", Const, 0}, {"IP_OLD_FW_ZERO", Const, 0}, {"IP_ONESBCAST", Const, 0}, {"IP_OPTIONS", Const, 0}, {"IP_ORIGDSTADDR", Const, 0}, {"IP_PASSSEC", Const, 0}, {"IP_PIPEX", Const, 1}, {"IP_PKTINFO", Const, 0}, {"IP_PKTOPTIONS", Const, 0}, {"IP_PMTUDISC", Const, 0}, {"IP_PMTUDISC_DO", Const, 0}, {"IP_PMTUDISC_DONT", Const, 0}, {"IP_PMTUDISC_PROBE", Const, 0}, {"IP_PMTUDISC_WANT", Const, 0}, {"IP_PORTRANGE", Const, 0}, {"IP_PORTRANGE_DEFAULT", Const, 0}, {"IP_PORTRANGE_HIGH", Const, 0}, {"IP_PORTRANGE_LOW", Const, 0}, {"IP_RECVDSTADDR", Const, 0}, {"IP_RECVDSTPORT", Const, 1}, {"IP_RECVERR", Const, 0}, {"IP_RECVIF", Const, 0}, {"IP_RECVOPTS", Const, 0}, {"IP_RECVORIGDSTADDR", Const, 0}, {"IP_RECVPKTINFO", Const, 0}, {"IP_RECVRETOPTS", Const, 0}, {"IP_RECVRTABLE", Const, 1}, {"IP_RECVTOS", Const, 0}, {"IP_RECVTTL", Const, 0}, {"IP_RETOPTS", Const, 0}, {"IP_RF", Const, 0}, {"IP_ROUTER_ALERT", Const, 0}, {"IP_RSVP_OFF", Const, 0}, {"IP_RSVP_ON", Const, 0}, {"IP_RSVP_VIF_OFF", Const, 0}, {"IP_RSVP_VIF_ON", Const, 0}, {"IP_RTABLE", Const, 1}, {"IP_SENDSRCADDR", Const, 0}, {"IP_STRIPHDR", Const, 0}, {"IP_TOS", Const, 0}, {"IP_TRAFFIC_MGT_BACKGROUND", Const, 0}, {"IP_TRANSPARENT", Const, 0}, {"IP_TTL", Const, 0}, {"IP_UNBLOCK_SOURCE", Const, 0}, {"IP_XFRM_POLICY", Const, 0}, {"IPv6MTUInfo", Type, 2}, {"IPv6MTUInfo.Addr", Field, 2}, {"IPv6MTUInfo.Mtu", Field, 2}, {"IPv6Mreq", Type, 0}, {"IPv6Mreq.Interface", Field, 0}, {"IPv6Mreq.Multiaddr", Field, 0}, {"ISIG", Const, 0}, {"ISTRIP", Const, 0}, {"IUCLC", Const, 0}, {"IUTF8", Const, 0}, {"IXANY", Const, 0}, {"IXOFF", Const, 0}, {"IXON", Const, 0}, {"IfAddrmsg", Type, 0}, {"IfAddrmsg.Family", Field, 0}, {"IfAddrmsg.Flags", Field, 0}, {"IfAddrmsg.Index", Field, 0}, {"IfAddrmsg.Prefixlen", Field, 0}, {"IfAddrmsg.Scope", Field, 0}, {"IfAnnounceMsghdr", Type, 1}, {"IfAnnounceMsghdr.Hdrlen", Field, 2}, {"IfAnnounceMsghdr.Index", Field, 1}, {"IfAnnounceMsghdr.Msglen", Field, 1}, {"IfAnnounceMsghdr.Name", Field, 1}, {"IfAnnounceMsghdr.Type", Field, 1}, {"IfAnnounceMsghdr.Version", Field, 1}, {"IfAnnounceMsghdr.What", Field, 1}, {"IfData", Type, 0}, {"IfData.Addrlen", Field, 0}, {"IfData.Baudrate", Field, 0}, {"IfData.Capabilities", Field, 2}, {"IfData.Collisions", Field, 0}, {"IfData.Datalen", Field, 0}, {"IfData.Epoch", Field, 0}, {"IfData.Hdrlen", Field, 0}, {"IfData.Hwassist", Field, 0}, {"IfData.Ibytes", Field, 0}, {"IfData.Ierrors", Field, 0}, {"IfData.Imcasts", Field, 0}, {"IfData.Ipackets", Field, 0}, {"IfData.Iqdrops", Field, 0}, {"IfData.Lastchange", Field, 0}, {"IfData.Link_state", Field, 0}, {"IfData.Mclpool", Field, 2}, {"IfData.Metric", Field, 0}, {"IfData.Mtu", Field, 0}, {"IfData.Noproto", Field, 0}, {"IfData.Obytes", Field, 0}, {"IfData.Oerrors", Field, 0}, {"IfData.Omcasts", Field, 0}, {"IfData.Opackets", Field, 0}, {"IfData.Pad", Field, 2}, {"IfData.Pad_cgo_0", Field, 2}, {"IfData.Pad_cgo_1", Field, 2}, {"IfData.Physical", Field, 0}, {"IfData.Recvquota", Field, 0}, {"IfData.Recvtiming", Field, 0}, {"IfData.Reserved1", Field, 0}, {"IfData.Reserved2", Field, 0}, {"IfData.Spare_char1", Field, 0}, {"IfData.Spare_char2", Field, 0}, {"IfData.Type", Field, 0}, {"IfData.Typelen", Field, 0}, {"IfData.Unused1", Field, 0}, {"IfData.Unused2", Field, 0}, {"IfData.Xmitquota", Field, 0}, {"IfData.Xmittiming", Field, 0}, {"IfInfomsg", Type, 0}, {"IfInfomsg.Change", Field, 0}, {"IfInfomsg.Family", Field, 0}, {"IfInfomsg.Flags", Field, 0}, {"IfInfomsg.Index", Field, 0}, {"IfInfomsg.Type", Field, 0}, {"IfInfomsg.X__ifi_pad", Field, 0}, {"IfMsghdr", Type, 0}, {"IfMsghdr.Addrs", Field, 0}, {"IfMsghdr.Data", Field, 0}, {"IfMsghdr.Flags", Field, 0}, {"IfMsghdr.Hdrlen", Field, 2}, {"IfMsghdr.Index", Field, 0}, {"IfMsghdr.Msglen", Field, 0}, {"IfMsghdr.Pad1", Field, 2}, {"IfMsghdr.Pad2", Field, 2}, {"IfMsghdr.Pad_cgo_0", Field, 0}, {"IfMsghdr.Pad_cgo_1", Field, 2}, {"IfMsghdr.Tableid", Field, 2}, {"IfMsghdr.Type", Field, 0}, {"IfMsghdr.Version", Field, 0}, {"IfMsghdr.Xflags", Field, 2}, {"IfaMsghdr", Type, 0}, {"IfaMsghdr.Addrs", Field, 0}, {"IfaMsghdr.Flags", Field, 0}, {"IfaMsghdr.Hdrlen", Field, 2}, {"IfaMsghdr.Index", Field, 0}, {"IfaMsghdr.Metric", Field, 0}, {"IfaMsghdr.Msglen", Field, 0}, {"IfaMsghdr.Pad1", Field, 2}, {"IfaMsghdr.Pad2", Field, 2}, {"IfaMsghdr.Pad_cgo_0", Field, 0}, {"IfaMsghdr.Tableid", Field, 2}, {"IfaMsghdr.Type", Field, 0}, {"IfaMsghdr.Version", Field, 0}, {"IfmaMsghdr", Type, 0}, {"IfmaMsghdr.Addrs", Field, 0}, {"IfmaMsghdr.Flags", Field, 0}, {"IfmaMsghdr.Index", Field, 0}, {"IfmaMsghdr.Msglen", Field, 0}, {"IfmaMsghdr.Pad_cgo_0", Field, 0}, {"IfmaMsghdr.Type", Field, 0}, {"IfmaMsghdr.Version", Field, 0}, {"IfmaMsghdr2", Type, 0}, {"IfmaMsghdr2.Addrs", Field, 0}, {"IfmaMsghdr2.Flags", Field, 0}, {"IfmaMsghdr2.Index", Field, 0}, {"IfmaMsghdr2.Msglen", Field, 0}, {"IfmaMsghdr2.Pad_cgo_0", Field, 0}, {"IfmaMsghdr2.Refcount", Field, 0}, {"IfmaMsghdr2.Type", Field, 0}, {"IfmaMsghdr2.Version", Field, 0}, {"ImplementsGetwd", Const, 0}, {"Inet4Pktinfo", Type, 0}, {"Inet4Pktinfo.Addr", Field, 0}, {"Inet4Pktinfo.Ifindex", Field, 0}, {"Inet4Pktinfo.Spec_dst", Field, 0}, {"Inet6Pktinfo", Type, 0}, {"Inet6Pktinfo.Addr", Field, 0}, {"Inet6Pktinfo.Ifindex", Field, 0}, {"InotifyAddWatch", Func, 0}, {"InotifyEvent", Type, 0}, {"InotifyEvent.Cookie", Field, 0}, {"InotifyEvent.Len", Field, 0}, {"InotifyEvent.Mask", Field, 0}, {"InotifyEvent.Name", Field, 0}, {"InotifyEvent.Wd", Field, 0}, {"InotifyInit", Func, 0}, {"InotifyInit1", Func, 0}, {"InotifyRmWatch", Func, 0}, {"InterfaceAddrMessage", Type, 0}, {"InterfaceAddrMessage.Data", Field, 0}, {"InterfaceAddrMessage.Header", Field, 0}, {"InterfaceAnnounceMessage", Type, 1}, {"InterfaceAnnounceMessage.Header", Field, 1}, {"InterfaceInfo", Type, 0}, {"InterfaceInfo.Address", Field, 0}, {"InterfaceInfo.BroadcastAddress", Field, 0}, {"InterfaceInfo.Flags", Field, 0}, {"InterfaceInfo.Netmask", Field, 0}, {"InterfaceMessage", Type, 0}, {"InterfaceMessage.Data", Field, 0}, {"InterfaceMessage.Header", Field, 0}, {"InterfaceMulticastAddrMessage", Type, 0}, {"InterfaceMulticastAddrMessage.Data", Field, 0}, {"InterfaceMulticastAddrMessage.Header", Field, 0}, {"InvalidHandle", Const, 0}, {"Ioperm", Func, 0}, {"Iopl", Func, 0}, {"Iovec", Type, 0}, {"Iovec.Base", Field, 0}, {"Iovec.Len", Field, 0}, {"IpAdapterInfo", Type, 0}, {"IpAdapterInfo.AdapterName", Field, 0}, {"IpAdapterInfo.Address", Field, 0}, {"IpAdapterInfo.AddressLength", Field, 0}, {"IpAdapterInfo.ComboIndex", Field, 0}, {"IpAdapterInfo.CurrentIpAddress", Field, 0}, {"IpAdapterInfo.Description", Field, 0}, {"IpAdapterInfo.DhcpEnabled", Field, 0}, {"IpAdapterInfo.DhcpServer", Field, 0}, {"IpAdapterInfo.GatewayList", Field, 0}, {"IpAdapterInfo.HaveWins", Field, 0}, {"IpAdapterInfo.Index", Field, 0}, {"IpAdapterInfo.IpAddressList", Field, 0}, {"IpAdapterInfo.LeaseExpires", Field, 0}, {"IpAdapterInfo.LeaseObtained", Field, 0}, {"IpAdapterInfo.Next", Field, 0}, {"IpAdapterInfo.PrimaryWinsServer", Field, 0}, {"IpAdapterInfo.SecondaryWinsServer", Field, 0}, {"IpAdapterInfo.Type", Field, 0}, {"IpAddrString", Type, 0}, {"IpAddrString.Context", Field, 0}, {"IpAddrString.IpAddress", Field, 0}, {"IpAddrString.IpMask", Field, 0}, {"IpAddrString.Next", Field, 0}, {"IpAddressString", Type, 0}, {"IpAddressString.String", Field, 0}, {"IpMaskString", Type, 0}, {"IpMaskString.String", Field, 2}, {"Issetugid", Func, 0}, {"KEY_ALL_ACCESS", Const, 0}, {"KEY_CREATE_LINK", Const, 0}, {"KEY_CREATE_SUB_KEY", Const, 0}, {"KEY_ENUMERATE_SUB_KEYS", Const, 0}, {"KEY_EXECUTE", Const, 0}, {"KEY_NOTIFY", Const, 0}, {"KEY_QUERY_VALUE", Const, 0}, {"KEY_READ", Const, 0}, {"KEY_SET_VALUE", Const, 0}, {"KEY_WOW64_32KEY", Const, 0}, {"KEY_WOW64_64KEY", Const, 0}, {"KEY_WRITE", Const, 0}, {"Kevent", Func, 0}, {"Kevent_t", Type, 0}, {"Kevent_t.Data", Field, 0}, {"Kevent_t.Fflags", Field, 0}, {"Kevent_t.Filter", Field, 0}, {"Kevent_t.Flags", Field, 0}, {"Kevent_t.Ident", Field, 0}, {"Kevent_t.Pad_cgo_0", Field, 2}, {"Kevent_t.Udata", Field, 0}, {"Kill", Func, 0}, {"Klogctl", Func, 0}, {"Kqueue", Func, 0}, {"LANG_ENGLISH", Const, 0}, {"LAYERED_PROTOCOL", Const, 2}, {"LCNT_OVERLOAD_FLUSH", Const, 1}, {"LINUX_REBOOT_CMD_CAD_OFF", Const, 0}, {"LINUX_REBOOT_CMD_CAD_ON", Const, 0}, {"LINUX_REBOOT_CMD_HALT", Const, 0}, {"LINUX_REBOOT_CMD_KEXEC", Const, 0}, {"LINUX_REBOOT_CMD_POWER_OFF", Const, 0}, {"LINUX_REBOOT_CMD_RESTART", Const, 0}, {"LINUX_REBOOT_CMD_RESTART2", Const, 0}, {"LINUX_REBOOT_CMD_SW_SUSPEND", Const, 0}, {"LINUX_REBOOT_MAGIC1", Const, 0}, {"LINUX_REBOOT_MAGIC2", Const, 0}, {"LOCK_EX", Const, 0}, {"LOCK_NB", Const, 0}, {"LOCK_SH", Const, 0}, {"LOCK_UN", Const, 0}, {"LazyDLL", Type, 0}, {"LazyDLL.Name", Field, 0}, {"LazyProc", Type, 0}, {"LazyProc.Name", Field, 0}, {"Lchown", Func, 0}, {"Linger", Type, 0}, {"Linger.Linger", Field, 0}, {"Linger.Onoff", Field, 0}, {"Link", Func, 0}, {"Listen", Func, 0}, {"Listxattr", Func, 1}, {"LoadCancelIoEx", Func, 1}, {"LoadConnectEx", Func, 1}, {"LoadCreateSymbolicLink", Func, 4}, {"LoadDLL", Func, 0}, {"LoadGetAddrInfo", Func, 1}, {"LoadLibrary", Func, 0}, {"LoadSetFileCompletionNotificationModes", Func, 2}, {"LocalFree", Func, 0}, {"Log2phys_t", Type, 0}, {"Log2phys_t.Contigbytes", Field, 0}, {"Log2phys_t.Devoffset", Field, 0}, {"Log2phys_t.Flags", Field, 0}, {"LookupAccountName", Func, 0}, {"LookupAccountSid", Func, 0}, {"LookupSID", Func, 0}, {"LsfJump", Func, 0}, {"LsfSocket", Func, 0}, {"LsfStmt", Func, 0}, {"Lstat", Func, 0}, {"MADV_AUTOSYNC", Const, 1}, {"MADV_CAN_REUSE", Const, 0}, {"MADV_CORE", Const, 1}, {"MADV_DOFORK", Const, 0}, {"MADV_DONTFORK", Const, 0}, {"MADV_DONTNEED", Const, 0}, {"MADV_FREE", Const, 0}, {"MADV_FREE_REUSABLE", Const, 0}, {"MADV_FREE_REUSE", Const, 0}, {"MADV_HUGEPAGE", Const, 0}, {"MADV_HWPOISON", Const, 0}, {"MADV_MERGEABLE", Const, 0}, {"MADV_NOCORE", Const, 1}, {"MADV_NOHUGEPAGE", Const, 0}, {"MADV_NORMAL", Const, 0}, {"MADV_NOSYNC", Const, 1}, {"MADV_PROTECT", Const, 1}, {"MADV_RANDOM", Const, 0}, {"MADV_REMOVE", Const, 0}, {"MADV_SEQUENTIAL", Const, 0}, {"MADV_SPACEAVAIL", Const, 3}, {"MADV_UNMERGEABLE", Const, 0}, {"MADV_WILLNEED", Const, 0}, {"MADV_ZERO_WIRED_PAGES", Const, 0}, {"MAP_32BIT", Const, 0}, {"MAP_ALIGNED_SUPER", Const, 3}, {"MAP_ALIGNMENT_16MB", Const, 3}, {"MAP_ALIGNMENT_1TB", Const, 3}, {"MAP_ALIGNMENT_256TB", Const, 3}, {"MAP_ALIGNMENT_4GB", Const, 3}, {"MAP_ALIGNMENT_64KB", Const, 3}, {"MAP_ALIGNMENT_64PB", Const, 3}, {"MAP_ALIGNMENT_MASK", Const, 3}, {"MAP_ALIGNMENT_SHIFT", Const, 3}, {"MAP_ANON", Const, 0}, {"MAP_ANONYMOUS", Const, 0}, {"MAP_COPY", Const, 0}, {"MAP_DENYWRITE", Const, 0}, {"MAP_EXECUTABLE", Const, 0}, {"MAP_FILE", Const, 0}, {"MAP_FIXED", Const, 0}, {"MAP_FLAGMASK", Const, 3}, {"MAP_GROWSDOWN", Const, 0}, {"MAP_HASSEMAPHORE", Const, 0}, {"MAP_HUGETLB", Const, 0}, {"MAP_INHERIT", Const, 3}, {"MAP_INHERIT_COPY", Const, 3}, {"MAP_INHERIT_DEFAULT", Const, 3}, {"MAP_INHERIT_DONATE_COPY", Const, 3}, {"MAP_INHERIT_NONE", Const, 3}, {"MAP_INHERIT_SHARE", Const, 3}, {"MAP_JIT", Const, 0}, {"MAP_LOCKED", Const, 0}, {"MAP_NOCACHE", Const, 0}, {"MAP_NOCORE", Const, 1}, {"MAP_NOEXTEND", Const, 0}, {"MAP_NONBLOCK", Const, 0}, {"MAP_NORESERVE", Const, 0}, {"MAP_NOSYNC", Const, 1}, {"MAP_POPULATE", Const, 0}, {"MAP_PREFAULT_READ", Const, 1}, {"MAP_PRIVATE", Const, 0}, {"MAP_RENAME", Const, 0}, {"MAP_RESERVED0080", Const, 0}, {"MAP_RESERVED0100", Const, 1}, {"MAP_SHARED", Const, 0}, {"MAP_STACK", Const, 0}, {"MAP_TRYFIXED", Const, 3}, {"MAP_TYPE", Const, 0}, {"MAP_WIRED", Const, 3}, {"MAXIMUM_REPARSE_DATA_BUFFER_SIZE", Const, 4}, {"MAXLEN_IFDESCR", Const, 0}, {"MAXLEN_PHYSADDR", Const, 0}, {"MAX_ADAPTER_ADDRESS_LENGTH", Const, 0}, {"MAX_ADAPTER_DESCRIPTION_LENGTH", Const, 0}, {"MAX_ADAPTER_NAME_LENGTH", Const, 0}, {"MAX_COMPUTERNAME_LENGTH", Const, 0}, {"MAX_INTERFACE_NAME_LEN", Const, 0}, {"MAX_LONG_PATH", Const, 0}, {"MAX_PATH", Const, 0}, {"MAX_PROTOCOL_CHAIN", Const, 2}, {"MCL_CURRENT", Const, 0}, {"MCL_FUTURE", Const, 0}, {"MNT_DETACH", Const, 0}, {"MNT_EXPIRE", Const, 0}, {"MNT_FORCE", Const, 0}, {"MSG_BCAST", Const, 1}, {"MSG_CMSG_CLOEXEC", Const, 0}, {"MSG_COMPAT", Const, 0}, {"MSG_CONFIRM", Const, 0}, {"MSG_CONTROLMBUF", Const, 1}, {"MSG_CTRUNC", Const, 0}, {"MSG_DONTROUTE", Const, 0}, {"MSG_DONTWAIT", Const, 0}, {"MSG_EOF", Const, 0}, {"MSG_EOR", Const, 0}, {"MSG_ERRQUEUE", Const, 0}, {"MSG_FASTOPEN", Const, 1}, {"MSG_FIN", Const, 0}, {"MSG_FLUSH", Const, 0}, {"MSG_HAVEMORE", Const, 0}, {"MSG_HOLD", Const, 0}, {"MSG_IOVUSRSPACE", Const, 1}, {"MSG_LENUSRSPACE", Const, 1}, {"MSG_MCAST", Const, 1}, {"MSG_MORE", Const, 0}, {"MSG_NAMEMBUF", Const, 1}, {"MSG_NBIO", Const, 0}, {"MSG_NEEDSA", Const, 0}, {"MSG_NOSIGNAL", Const, 0}, {"MSG_NOTIFICATION", Const, 0}, {"MSG_OOB", Const, 0}, {"MSG_PEEK", Const, 0}, {"MSG_PROXY", Const, 0}, {"MSG_RCVMORE", Const, 0}, {"MSG_RST", Const, 0}, {"MSG_SEND", Const, 0}, {"MSG_SYN", Const, 0}, {"MSG_TRUNC", Const, 0}, {"MSG_TRYHARD", Const, 0}, {"MSG_USERFLAGS", Const, 1}, {"MSG_WAITALL", Const, 0}, {"MSG_WAITFORONE", Const, 0}, {"MSG_WAITSTREAM", Const, 0}, {"MS_ACTIVE", Const, 0}, {"MS_ASYNC", Const, 0}, {"MS_BIND", Const, 0}, {"MS_DEACTIVATE", Const, 0}, {"MS_DIRSYNC", Const, 0}, {"MS_INVALIDATE", Const, 0}, {"MS_I_VERSION", Const, 0}, {"MS_KERNMOUNT", Const, 0}, {"MS_KILLPAGES", Const, 0}, {"MS_MANDLOCK", Const, 0}, {"MS_MGC_MSK", Const, 0}, {"MS_MGC_VAL", Const, 0}, {"MS_MOVE", Const, 0}, {"MS_NOATIME", Const, 0}, {"MS_NODEV", Const, 0}, {"MS_NODIRATIME", Const, 0}, {"MS_NOEXEC", Const, 0}, {"MS_NOSUID", Const, 0}, {"MS_NOUSER", Const, 0}, {"MS_POSIXACL", Const, 0}, {"MS_PRIVATE", Const, 0}, {"MS_RDONLY", Const, 0}, {"MS_REC", Const, 0}, {"MS_RELATIME", Const, 0}, {"MS_REMOUNT", Const, 0}, {"MS_RMT_MASK", Const, 0}, {"MS_SHARED", Const, 0}, {"MS_SILENT", Const, 0}, {"MS_SLAVE", Const, 0}, {"MS_STRICTATIME", Const, 0}, {"MS_SYNC", Const, 0}, {"MS_SYNCHRONOUS", Const, 0}, {"MS_UNBINDABLE", Const, 0}, {"Madvise", Func, 0}, {"MapViewOfFile", Func, 0}, {"MaxTokenInfoClass", Const, 0}, {"Mclpool", Type, 2}, {"Mclpool.Alive", Field, 2}, {"Mclpool.Cwm", Field, 2}, {"Mclpool.Grown", Field, 2}, {"Mclpool.Hwm", Field, 2}, {"Mclpool.Lwm", Field, 2}, {"MibIfRow", Type, 0}, {"MibIfRow.AdminStatus", Field, 0}, {"MibIfRow.Descr", Field, 0}, {"MibIfRow.DescrLen", Field, 0}, {"MibIfRow.InDiscards", Field, 0}, {"MibIfRow.InErrors", Field, 0}, {"MibIfRow.InNUcastPkts", Field, 0}, {"MibIfRow.InOctets", Field, 0}, {"MibIfRow.InUcastPkts", Field, 0}, {"MibIfRow.InUnknownProtos", Field, 0}, {"MibIfRow.Index", Field, 0}, {"MibIfRow.LastChange", Field, 0}, {"MibIfRow.Mtu", Field, 0}, {"MibIfRow.Name", Field, 0}, {"MibIfRow.OperStatus", Field, 0}, {"MibIfRow.OutDiscards", Field, 0}, {"MibIfRow.OutErrors", Field, 0}, {"MibIfRow.OutNUcastPkts", Field, 0}, {"MibIfRow.OutOctets", Field, 0}, {"MibIfRow.OutQLen", Field, 0}, {"MibIfRow.OutUcastPkts", Field, 0}, {"MibIfRow.PhysAddr", Field, 0}, {"MibIfRow.PhysAddrLen", Field, 0}, {"MibIfRow.Speed", Field, 0}, {"MibIfRow.Type", Field, 0}, {"Mkdir", Func, 0}, {"Mkdirat", Func, 0}, {"Mkfifo", Func, 0}, {"Mknod", Func, 0}, {"Mknodat", Func, 0}, {"Mlock", Func, 0}, {"Mlockall", Func, 0}, {"Mmap", Func, 0}, {"Mount", Func, 0}, {"MoveFile", Func, 0}, {"Mprotect", Func, 0}, {"Msghdr", Type, 0}, {"Msghdr.Control", Field, 0}, {"Msghdr.Controllen", Field, 0}, {"Msghdr.Flags", Field, 0}, {"Msghdr.Iov", Field, 0}, {"Msghdr.Iovlen", Field, 0}, {"Msghdr.Name", Field, 0}, {"Msghdr.Namelen", Field, 0}, {"Msghdr.Pad_cgo_0", Field, 0}, {"Msghdr.Pad_cgo_1", Field, 0}, {"Munlock", Func, 0}, {"Munlockall", Func, 0}, {"Munmap", Func, 0}, {"MustLoadDLL", Func, 0}, {"NAME_MAX", Const, 0}, {"NETLINK_ADD_MEMBERSHIP", Const, 0}, {"NETLINK_AUDIT", Const, 0}, {"NETLINK_BROADCAST_ERROR", Const, 0}, {"NETLINK_CONNECTOR", Const, 0}, {"NETLINK_DNRTMSG", Const, 0}, {"NETLINK_DROP_MEMBERSHIP", Const, 0}, {"NETLINK_ECRYPTFS", Const, 0}, {"NETLINK_FIB_LOOKUP", Const, 0}, {"NETLINK_FIREWALL", Const, 0}, {"NETLINK_GENERIC", Const, 0}, {"NETLINK_INET_DIAG", Const, 0}, {"NETLINK_IP6_FW", Const, 0}, {"NETLINK_ISCSI", Const, 0}, {"NETLINK_KOBJECT_UEVENT", Const, 0}, {"NETLINK_NETFILTER", Const, 0}, {"NETLINK_NFLOG", Const, 0}, {"NETLINK_NO_ENOBUFS", Const, 0}, {"NETLINK_PKTINFO", Const, 0}, {"NETLINK_RDMA", Const, 0}, {"NETLINK_ROUTE", Const, 0}, {"NETLINK_SCSITRANSPORT", Const, 0}, {"NETLINK_SELINUX", Const, 0}, {"NETLINK_UNUSED", Const, 0}, {"NETLINK_USERSOCK", Const, 0}, {"NETLINK_XFRM", Const, 0}, {"NET_RT_DUMP", Const, 0}, {"NET_RT_DUMP2", Const, 0}, {"NET_RT_FLAGS", Const, 0}, {"NET_RT_IFLIST", Const, 0}, {"NET_RT_IFLIST2", Const, 0}, {"NET_RT_IFLISTL", Const, 1}, {"NET_RT_IFMALIST", Const, 0}, {"NET_RT_MAXID", Const, 0}, {"NET_RT_OIFLIST", Const, 1}, {"NET_RT_OOIFLIST", Const, 1}, {"NET_RT_STAT", Const, 0}, {"NET_RT_STATS", Const, 1}, {"NET_RT_TABLE", Const, 1}, {"NET_RT_TRASH", Const, 0}, {"NLA_ALIGNTO", Const, 0}, {"NLA_F_NESTED", Const, 0}, {"NLA_F_NET_BYTEORDER", Const, 0}, {"NLA_HDRLEN", Const, 0}, {"NLMSG_ALIGNTO", Const, 0}, {"NLMSG_DONE", Const, 0}, {"NLMSG_ERROR", Const, 0}, {"NLMSG_HDRLEN", Const, 0}, {"NLMSG_MIN_TYPE", Const, 0}, {"NLMSG_NOOP", Const, 0}, {"NLMSG_OVERRUN", Const, 0}, {"NLM_F_ACK", Const, 0}, {"NLM_F_APPEND", Const, 0}, {"NLM_F_ATOMIC", Const, 0}, {"NLM_F_CREATE", Const, 0}, {"NLM_F_DUMP", Const, 0}, {"NLM_F_ECHO", Const, 0}, {"NLM_F_EXCL", Const, 0}, {"NLM_F_MATCH", Const, 0}, {"NLM_F_MULTI", Const, 0}, {"NLM_F_REPLACE", Const, 0}, {"NLM_F_REQUEST", Const, 0}, {"NLM_F_ROOT", Const, 0}, {"NOFLSH", Const, 0}, {"NOTE_ABSOLUTE", Const, 0}, {"NOTE_ATTRIB", Const, 0}, {"NOTE_BACKGROUND", Const, 16}, {"NOTE_CHILD", Const, 0}, {"NOTE_CRITICAL", Const, 16}, {"NOTE_DELETE", Const, 0}, {"NOTE_EOF", Const, 1}, {"NOTE_EXEC", Const, 0}, {"NOTE_EXIT", Const, 0}, {"NOTE_EXITSTATUS", Const, 0}, {"NOTE_EXIT_CSERROR", Const, 16}, {"NOTE_EXIT_DECRYPTFAIL", Const, 16}, {"NOTE_EXIT_DETAIL", Const, 16}, {"NOTE_EXIT_DETAIL_MASK", Const, 16}, {"NOTE_EXIT_MEMORY", Const, 16}, {"NOTE_EXIT_REPARENTED", Const, 16}, {"NOTE_EXTEND", Const, 0}, {"NOTE_FFAND", Const, 0}, {"NOTE_FFCOPY", Const, 0}, {"NOTE_FFCTRLMASK", Const, 0}, {"NOTE_FFLAGSMASK", Const, 0}, {"NOTE_FFNOP", Const, 0}, {"NOTE_FFOR", Const, 0}, {"NOTE_FORK", Const, 0}, {"NOTE_LEEWAY", Const, 16}, {"NOTE_LINK", Const, 0}, {"NOTE_LOWAT", Const, 0}, {"NOTE_NONE", Const, 0}, {"NOTE_NSECONDS", Const, 0}, {"NOTE_PCTRLMASK", Const, 0}, {"NOTE_PDATAMASK", Const, 0}, {"NOTE_REAP", Const, 0}, {"NOTE_RENAME", Const, 0}, {"NOTE_RESOURCEEND", Const, 0}, {"NOTE_REVOKE", Const, 0}, {"NOTE_SECONDS", Const, 0}, {"NOTE_SIGNAL", Const, 0}, {"NOTE_TRACK", Const, 0}, {"NOTE_TRACKERR", Const, 0}, {"NOTE_TRIGGER", Const, 0}, {"NOTE_TRUNCATE", Const, 1}, {"NOTE_USECONDS", Const, 0}, {"NOTE_VM_ERROR", Const, 0}, {"NOTE_VM_PRESSURE", Const, 0}, {"NOTE_VM_PRESSURE_SUDDEN_TERMINATE", Const, 0}, {"NOTE_VM_PRESSURE_TERMINATE", Const, 0}, {"NOTE_WRITE", Const, 0}, {"NameCanonical", Const, 0}, {"NameCanonicalEx", Const, 0}, {"NameDisplay", Const, 0}, {"NameDnsDomain", Const, 0}, {"NameFullyQualifiedDN", Const, 0}, {"NameSamCompatible", Const, 0}, {"NameServicePrincipal", Const, 0}, {"NameUniqueId", Const, 0}, {"NameUnknown", Const, 0}, {"NameUserPrincipal", Const, 0}, {"Nanosleep", Func, 0}, {"NetApiBufferFree", Func, 0}, {"NetGetJoinInformation", Func, 2}, {"NetSetupDomainName", Const, 2}, {"NetSetupUnjoined", Const, 2}, {"NetSetupUnknownStatus", Const, 2}, {"NetSetupWorkgroupName", Const, 2}, {"NetUserGetInfo", Func, 0}, {"NetlinkMessage", Type, 0}, {"NetlinkMessage.Data", Field, 0}, {"NetlinkMessage.Header", Field, 0}, {"NetlinkRIB", Func, 0}, {"NetlinkRouteAttr", Type, 0}, {"NetlinkRouteAttr.Attr", Field, 0}, {"NetlinkRouteAttr.Value", Field, 0}, {"NetlinkRouteRequest", Type, 0}, {"NetlinkRouteRequest.Data", Field, 0}, {"NetlinkRouteRequest.Header", Field, 0}, {"NewCallback", Func, 0}, {"NewCallbackCDecl", Func, 3}, {"NewLazyDLL", Func, 0}, {"NlAttr", Type, 0}, {"NlAttr.Len", Field, 0}, {"NlAttr.Type", Field, 0}, {"NlMsgerr", Type, 0}, {"NlMsgerr.Error", Field, 0}, {"NlMsgerr.Msg", Field, 0}, {"NlMsghdr", Type, 0}, {"NlMsghdr.Flags", Field, 0}, {"NlMsghdr.Len", Field, 0}, {"NlMsghdr.Pid", Field, 0}, {"NlMsghdr.Seq", Field, 0}, {"NlMsghdr.Type", Field, 0}, {"NsecToFiletime", Func, 0}, {"NsecToTimespec", Func, 0}, {"NsecToTimeval", Func, 0}, {"Ntohs", Func, 0}, {"OCRNL", Const, 0}, {"OFDEL", Const, 0}, {"OFILL", Const, 0}, {"OFIOGETBMAP", Const, 1}, {"OID_PKIX_KP_SERVER_AUTH", Var, 0}, {"OID_SERVER_GATED_CRYPTO", Var, 0}, {"OID_SGC_NETSCAPE", Var, 0}, {"OLCUC", Const, 0}, {"ONLCR", Const, 0}, {"ONLRET", Const, 0}, {"ONOCR", Const, 0}, {"ONOEOT", Const, 1}, {"OPEN_ALWAYS", Const, 0}, {"OPEN_EXISTING", Const, 0}, {"OPOST", Const, 0}, {"O_ACCMODE", Const, 0}, {"O_ALERT", Const, 0}, {"O_ALT_IO", Const, 1}, {"O_APPEND", Const, 0}, {"O_ASYNC", Const, 0}, {"O_CLOEXEC", Const, 0}, {"O_CREAT", Const, 0}, {"O_DIRECT", Const, 0}, {"O_DIRECTORY", Const, 0}, {"O_DP_GETRAWENCRYPTED", Const, 16}, {"O_DSYNC", Const, 0}, {"O_EVTONLY", Const, 0}, {"O_EXCL", Const, 0}, {"O_EXEC", Const, 0}, {"O_EXLOCK", Const, 0}, {"O_FSYNC", Const, 0}, {"O_LARGEFILE", Const, 0}, {"O_NDELAY", Const, 0}, {"O_NOATIME", Const, 0}, {"O_NOCTTY", Const, 0}, {"O_NOFOLLOW", Const, 0}, {"O_NONBLOCK", Const, 0}, {"O_NOSIGPIPE", Const, 1}, {"O_POPUP", Const, 0}, {"O_RDONLY", Const, 0}, {"O_RDWR", Const, 0}, {"O_RSYNC", Const, 0}, {"O_SHLOCK", Const, 0}, {"O_SYMLINK", Const, 0}, {"O_SYNC", Const, 0}, {"O_TRUNC", Const, 0}, {"O_TTY_INIT", Const, 0}, {"O_WRONLY", Const, 0}, {"Open", Func, 0}, {"OpenCurrentProcessToken", Func, 0}, {"OpenProcess", Func, 0}, {"OpenProcessToken", Func, 0}, {"Openat", Func, 0}, {"Overlapped", Type, 0}, {"Overlapped.HEvent", Field, 0}, {"Overlapped.Internal", Field, 0}, {"Overlapped.InternalHigh", Field, 0}, {"Overlapped.Offset", Field, 0}, {"Overlapped.OffsetHigh", Field, 0}, {"PACKET_ADD_MEMBERSHIP", Const, 0}, {"PACKET_BROADCAST", Const, 0}, {"PACKET_DROP_MEMBERSHIP", Const, 0}, {"PACKET_FASTROUTE", Const, 0}, {"PACKET_HOST", Const, 0}, {"PACKET_LOOPBACK", Const, 0}, {"PACKET_MR_ALLMULTI", Const, 0}, {"PACKET_MR_MULTICAST", Const, 0}, {"PACKET_MR_PROMISC", Const, 0}, {"PACKET_MULTICAST", Const, 0}, {"PACKET_OTHERHOST", Const, 0}, {"PACKET_OUTGOING", Const, 0}, {"PACKET_RECV_OUTPUT", Const, 0}, {"PACKET_RX_RING", Const, 0}, {"PACKET_STATISTICS", Const, 0}, {"PAGE_EXECUTE_READ", Const, 0}, {"PAGE_EXECUTE_READWRITE", Const, 0}, {"PAGE_EXECUTE_WRITECOPY", Const, 0}, {"PAGE_READONLY", Const, 0}, {"PAGE_READWRITE", Const, 0}, {"PAGE_WRITECOPY", Const, 0}, {"PARENB", Const, 0}, {"PARMRK", Const, 0}, {"PARODD", Const, 0}, {"PENDIN", Const, 0}, {"PFL_HIDDEN", Const, 2}, {"PFL_MATCHES_PROTOCOL_ZERO", Const, 2}, {"PFL_MULTIPLE_PROTO_ENTRIES", Const, 2}, {"PFL_NETWORKDIRECT_PROVIDER", Const, 2}, {"PFL_RECOMMENDED_PROTO_ENTRY", Const, 2}, {"PF_FLUSH", Const, 1}, {"PKCS_7_ASN_ENCODING", Const, 0}, {"PMC5_PIPELINE_FLUSH", Const, 1}, {"PRIO_PGRP", Const, 2}, {"PRIO_PROCESS", Const, 2}, {"PRIO_USER", Const, 2}, {"PRI_IOFLUSH", Const, 1}, {"PROCESS_QUERY_INFORMATION", Const, 0}, {"PROCESS_TERMINATE", Const, 2}, {"PROT_EXEC", Const, 0}, {"PROT_GROWSDOWN", Const, 0}, {"PROT_GROWSUP", Const, 0}, {"PROT_NONE", Const, 0}, {"PROT_READ", Const, 0}, {"PROT_WRITE", Const, 0}, {"PROV_DH_SCHANNEL", Const, 0}, {"PROV_DSS", Const, 0}, {"PROV_DSS_DH", Const, 0}, {"PROV_EC_ECDSA_FULL", Const, 0}, {"PROV_EC_ECDSA_SIG", Const, 0}, {"PROV_EC_ECNRA_FULL", Const, 0}, {"PROV_EC_ECNRA_SIG", Const, 0}, {"PROV_FORTEZZA", Const, 0}, {"PROV_INTEL_SEC", Const, 0}, {"PROV_MS_EXCHANGE", Const, 0}, {"PROV_REPLACE_OWF", Const, 0}, {"PROV_RNG", Const, 0}, {"PROV_RSA_AES", Const, 0}, {"PROV_RSA_FULL", Const, 0}, {"PROV_RSA_SCHANNEL", Const, 0}, {"PROV_RSA_SIG", Const, 0}, {"PROV_SPYRUS_LYNKS", Const, 0}, {"PROV_SSL", Const, 0}, {"PR_CAPBSET_DROP", Const, 0}, {"PR_CAPBSET_READ", Const, 0}, {"PR_CLEAR_SECCOMP_FILTER", Const, 0}, {"PR_ENDIAN_BIG", Const, 0}, {"PR_ENDIAN_LITTLE", Const, 0}, {"PR_ENDIAN_PPC_LITTLE", Const, 0}, {"PR_FPEMU_NOPRINT", Const, 0}, {"PR_FPEMU_SIGFPE", Const, 0}, {"PR_FP_EXC_ASYNC", Const, 0}, {"PR_FP_EXC_DISABLED", Const, 0}, {"PR_FP_EXC_DIV", Const, 0}, {"PR_FP_EXC_INV", Const, 0}, {"PR_FP_EXC_NONRECOV", Const, 0}, {"PR_FP_EXC_OVF", Const, 0}, {"PR_FP_EXC_PRECISE", Const, 0}, {"PR_FP_EXC_RES", Const, 0}, {"PR_FP_EXC_SW_ENABLE", Const, 0}, {"PR_FP_EXC_UND", Const, 0}, {"PR_GET_DUMPABLE", Const, 0}, {"PR_GET_ENDIAN", Const, 0}, {"PR_GET_FPEMU", Const, 0}, {"PR_GET_FPEXC", Const, 0}, {"PR_GET_KEEPCAPS", Const, 0}, {"PR_GET_NAME", Const, 0}, {"PR_GET_PDEATHSIG", Const, 0}, {"PR_GET_SECCOMP", Const, 0}, {"PR_GET_SECCOMP_FILTER", Const, 0}, {"PR_GET_SECUREBITS", Const, 0}, {"PR_GET_TIMERSLACK", Const, 0}, {"PR_GET_TIMING", Const, 0}, {"PR_GET_TSC", Const, 0}, {"PR_GET_UNALIGN", Const, 0}, {"PR_MCE_KILL", Const, 0}, {"PR_MCE_KILL_CLEAR", Const, 0}, {"PR_MCE_KILL_DEFAULT", Const, 0}, {"PR_MCE_KILL_EARLY", Const, 0}, {"PR_MCE_KILL_GET", Const, 0}, {"PR_MCE_KILL_LATE", Const, 0}, {"PR_MCE_KILL_SET", Const, 0}, {"PR_SECCOMP_FILTER_EVENT", Const, 0}, {"PR_SECCOMP_FILTER_SYSCALL", Const, 0}, {"PR_SET_DUMPABLE", Const, 0}, {"PR_SET_ENDIAN", Const, 0}, {"PR_SET_FPEMU", Const, 0}, {"PR_SET_FPEXC", Const, 0}, {"PR_SET_KEEPCAPS", Const, 0}, {"PR_SET_NAME", Const, 0}, {"PR_SET_PDEATHSIG", Const, 0}, {"PR_SET_PTRACER", Const, 0}, {"PR_SET_SECCOMP", Const, 0}, {"PR_SET_SECCOMP_FILTER", Const, 0}, {"PR_SET_SECUREBITS", Const, 0}, {"PR_SET_TIMERSLACK", Const, 0}, {"PR_SET_TIMING", Const, 0}, {"PR_SET_TSC", Const, 0}, {"PR_SET_UNALIGN", Const, 0}, {"PR_TASK_PERF_EVENTS_DISABLE", Const, 0}, {"PR_TASK_PERF_EVENTS_ENABLE", Const, 0}, {"PR_TIMING_STATISTICAL", Const, 0}, {"PR_TIMING_TIMESTAMP", Const, 0}, {"PR_TSC_ENABLE", Const, 0}, {"PR_TSC_SIGSEGV", Const, 0}, {"PR_UNALIGN_NOPRINT", Const, 0}, {"PR_UNALIGN_SIGBUS", Const, 0}, {"PTRACE_ARCH_PRCTL", Const, 0}, {"PTRACE_ATTACH", Const, 0}, {"PTRACE_CONT", Const, 0}, {"PTRACE_DETACH", Const, 0}, {"PTRACE_EVENT_CLONE", Const, 0}, {"PTRACE_EVENT_EXEC", Const, 0}, {"PTRACE_EVENT_EXIT", Const, 0}, {"PTRACE_EVENT_FORK", Const, 0}, {"PTRACE_EVENT_VFORK", Const, 0}, {"PTRACE_EVENT_VFORK_DONE", Const, 0}, {"PTRACE_GETCRUNCHREGS", Const, 0}, {"PTRACE_GETEVENTMSG", Const, 0}, {"PTRACE_GETFPREGS", Const, 0}, {"PTRACE_GETFPXREGS", Const, 0}, {"PTRACE_GETHBPREGS", Const, 0}, {"PTRACE_GETREGS", Const, 0}, {"PTRACE_GETREGSET", Const, 0}, {"PTRACE_GETSIGINFO", Const, 0}, {"PTRACE_GETVFPREGS", Const, 0}, {"PTRACE_GETWMMXREGS", Const, 0}, {"PTRACE_GET_THREAD_AREA", Const, 0}, {"PTRACE_KILL", Const, 0}, {"PTRACE_OLDSETOPTIONS", Const, 0}, {"PTRACE_O_MASK", Const, 0}, {"PTRACE_O_TRACECLONE", Const, 0}, {"PTRACE_O_TRACEEXEC", Const, 0}, {"PTRACE_O_TRACEEXIT", Const, 0}, {"PTRACE_O_TRACEFORK", Const, 0}, {"PTRACE_O_TRACESYSGOOD", Const, 0}, {"PTRACE_O_TRACEVFORK", Const, 0}, {"PTRACE_O_TRACEVFORKDONE", Const, 0}, {"PTRACE_PEEKDATA", Const, 0}, {"PTRACE_PEEKTEXT", Const, 0}, {"PTRACE_PEEKUSR", Const, 0}, {"PTRACE_POKEDATA", Const, 0}, {"PTRACE_POKETEXT", Const, 0}, {"PTRACE_POKEUSR", Const, 0}, {"PTRACE_SETCRUNCHREGS", Const, 0}, {"PTRACE_SETFPREGS", Const, 0}, {"PTRACE_SETFPXREGS", Const, 0}, {"PTRACE_SETHBPREGS", Const, 0}, {"PTRACE_SETOPTIONS", Const, 0}, {"PTRACE_SETREGS", Const, 0}, {"PTRACE_SETREGSET", Const, 0}, {"PTRACE_SETSIGINFO", Const, 0}, {"PTRACE_SETVFPREGS", Const, 0}, {"PTRACE_SETWMMXREGS", Const, 0}, {"PTRACE_SET_SYSCALL", Const, 0}, {"PTRACE_SET_THREAD_AREA", Const, 0}, {"PTRACE_SINGLEBLOCK", Const, 0}, {"PTRACE_SINGLESTEP", Const, 0}, {"PTRACE_SYSCALL", Const, 0}, {"PTRACE_SYSEMU", Const, 0}, {"PTRACE_SYSEMU_SINGLESTEP", Const, 0}, {"PTRACE_TRACEME", Const, 0}, {"PT_ATTACH", Const, 0}, {"PT_ATTACHEXC", Const, 0}, {"PT_CONTINUE", Const, 0}, {"PT_DATA_ADDR", Const, 0}, {"PT_DENY_ATTACH", Const, 0}, {"PT_DETACH", Const, 0}, {"PT_FIRSTMACH", Const, 0}, {"PT_FORCEQUOTA", Const, 0}, {"PT_KILL", Const, 0}, {"PT_MASK", Const, 1}, {"PT_READ_D", Const, 0}, {"PT_READ_I", Const, 0}, {"PT_READ_U", Const, 0}, {"PT_SIGEXC", Const, 0}, {"PT_STEP", Const, 0}, {"PT_TEXT_ADDR", Const, 0}, {"PT_TEXT_END_ADDR", Const, 0}, {"PT_THUPDATE", Const, 0}, {"PT_TRACE_ME", Const, 0}, {"PT_WRITE_D", Const, 0}, {"PT_WRITE_I", Const, 0}, {"PT_WRITE_U", Const, 0}, {"ParseDirent", Func, 0}, {"ParseNetlinkMessage", Func, 0}, {"ParseNetlinkRouteAttr", Func, 0}, {"ParseRoutingMessage", Func, 0}, {"ParseRoutingSockaddr", Func, 0}, {"ParseSocketControlMessage", Func, 0}, {"ParseUnixCredentials", Func, 0}, {"ParseUnixRights", Func, 0}, {"PathMax", Const, 0}, {"Pathconf", Func, 0}, {"Pause", Func, 0}, {"Pipe", Func, 0}, {"Pipe2", Func, 1}, {"PivotRoot", Func, 0}, {"Pointer", Type, 11}, {"PostQueuedCompletionStatus", Func, 0}, {"Pread", Func, 0}, {"Proc", Type, 0}, {"Proc.Dll", Field, 0}, {"Proc.Name", Field, 0}, {"ProcAttr", Type, 0}, {"ProcAttr.Dir", Field, 0}, {"ProcAttr.Env", Field, 0}, {"ProcAttr.Files", Field, 0}, {"ProcAttr.Sys", Field, 0}, {"Process32First", Func, 4}, {"Process32Next", Func, 4}, {"ProcessEntry32", Type, 4}, {"ProcessEntry32.DefaultHeapID", Field, 4}, {"ProcessEntry32.ExeFile", Field, 4}, {"ProcessEntry32.Flags", Field, 4}, {"ProcessEntry32.ModuleID", Field, 4}, {"ProcessEntry32.ParentProcessID", Field, 4}, {"ProcessEntry32.PriClassBase", Field, 4}, {"ProcessEntry32.ProcessID", Field, 4}, {"ProcessEntry32.Size", Field, 4}, {"ProcessEntry32.Threads", Field, 4}, {"ProcessEntry32.Usage", Field, 4}, {"ProcessInformation", Type, 0}, {"ProcessInformation.Process", Field, 0}, {"ProcessInformation.ProcessId", Field, 0}, {"ProcessInformation.Thread", Field, 0}, {"ProcessInformation.ThreadId", Field, 0}, {"Protoent", Type, 0}, {"Protoent.Aliases", Field, 0}, {"Protoent.Name", Field, 0}, {"Protoent.Proto", Field, 0}, {"PtraceAttach", Func, 0}, {"PtraceCont", Func, 0}, {"PtraceDetach", Func, 0}, {"PtraceGetEventMsg", Func, 0}, {"PtraceGetRegs", Func, 0}, {"PtracePeekData", Func, 0}, {"PtracePeekText", Func, 0}, {"PtracePokeData", Func, 0}, {"PtracePokeText", Func, 0}, {"PtraceRegs", Type, 0}, {"PtraceRegs.Cs", Field, 0}, {"PtraceRegs.Ds", Field, 0}, {"PtraceRegs.Eax", Field, 0}, {"PtraceRegs.Ebp", Field, 0}, {"PtraceRegs.Ebx", Field, 0}, {"PtraceRegs.Ecx", Field, 0}, {"PtraceRegs.Edi", Field, 0}, {"PtraceRegs.Edx", Field, 0}, {"PtraceRegs.Eflags", Field, 0}, {"PtraceRegs.Eip", Field, 0}, {"PtraceRegs.Es", Field, 0}, {"PtraceRegs.Esi", Field, 0}, {"PtraceRegs.Esp", Field, 0}, {"PtraceRegs.Fs", Field, 0}, {"PtraceRegs.Fs_base", Field, 0}, {"PtraceRegs.Gs", Field, 0}, {"PtraceRegs.Gs_base", Field, 0}, {"PtraceRegs.Orig_eax", Field, 0}, {"PtraceRegs.Orig_rax", Field, 0}, {"PtraceRegs.R10", Field, 0}, {"PtraceRegs.R11", Field, 0}, {"PtraceRegs.R12", Field, 0}, {"PtraceRegs.R13", Field, 0}, {"PtraceRegs.R14", Field, 0}, {"PtraceRegs.R15", Field, 0}, {"PtraceRegs.R8", Field, 0}, {"PtraceRegs.R9", Field, 0}, {"PtraceRegs.Rax", Field, 0}, {"PtraceRegs.Rbp", Field, 0}, {"PtraceRegs.Rbx", Field, 0}, {"PtraceRegs.Rcx", Field, 0}, {"PtraceRegs.Rdi", Field, 0}, {"PtraceRegs.Rdx", Field, 0}, {"PtraceRegs.Rip", Field, 0}, {"PtraceRegs.Rsi", Field, 0}, {"PtraceRegs.Rsp", Field, 0}, {"PtraceRegs.Ss", Field, 0}, {"PtraceRegs.Uregs", Field, 0}, {"PtraceRegs.Xcs", Field, 0}, {"PtraceRegs.Xds", Field, 0}, {"PtraceRegs.Xes", Field, 0}, {"PtraceRegs.Xfs", Field, 0}, {"PtraceRegs.Xgs", Field, 0}, {"PtraceRegs.Xss", Field, 0}, {"PtraceSetOptions", Func, 0}, {"PtraceSetRegs", Func, 0}, {"PtraceSingleStep", Func, 0}, {"PtraceSyscall", Func, 1}, {"Pwrite", Func, 0}, {"REG_BINARY", Const, 0}, {"REG_DWORD", Const, 0}, {"REG_DWORD_BIG_ENDIAN", Const, 0}, {"REG_DWORD_LITTLE_ENDIAN", Const, 0}, {"REG_EXPAND_SZ", Const, 0}, {"REG_FULL_RESOURCE_DESCRIPTOR", Const, 0}, {"REG_LINK", Const, 0}, {"REG_MULTI_SZ", Const, 0}, {"REG_NONE", Const, 0}, {"REG_QWORD", Const, 0}, {"REG_QWORD_LITTLE_ENDIAN", Const, 0}, {"REG_RESOURCE_LIST", Const, 0}, {"REG_RESOURCE_REQUIREMENTS_LIST", Const, 0}, {"REG_SZ", Const, 0}, {"RLIMIT_AS", Const, 0}, {"RLIMIT_CORE", Const, 0}, {"RLIMIT_CPU", Const, 0}, {"RLIMIT_CPU_USAGE_MONITOR", Const, 16}, {"RLIMIT_DATA", Const, 0}, {"RLIMIT_FSIZE", Const, 0}, {"RLIMIT_NOFILE", Const, 0}, {"RLIMIT_STACK", Const, 0}, {"RLIM_INFINITY", Const, 0}, {"RTAX_ADVMSS", Const, 0}, {"RTAX_AUTHOR", Const, 0}, {"RTAX_BRD", Const, 0}, {"RTAX_CWND", Const, 0}, {"RTAX_DST", Const, 0}, {"RTAX_FEATURES", Const, 0}, {"RTAX_FEATURE_ALLFRAG", Const, 0}, {"RTAX_FEATURE_ECN", Const, 0}, {"RTAX_FEATURE_SACK", Const, 0}, {"RTAX_FEATURE_TIMESTAMP", Const, 0}, {"RTAX_GATEWAY", Const, 0}, {"RTAX_GENMASK", Const, 0}, {"RTAX_HOPLIMIT", Const, 0}, {"RTAX_IFA", Const, 0}, {"RTAX_IFP", Const, 0}, {"RTAX_INITCWND", Const, 0}, {"RTAX_INITRWND", Const, 0}, {"RTAX_LABEL", Const, 1}, {"RTAX_LOCK", Const, 0}, {"RTAX_MAX", Const, 0}, {"RTAX_MTU", Const, 0}, {"RTAX_NETMASK", Const, 0}, {"RTAX_REORDERING", Const, 0}, {"RTAX_RTO_MIN", Const, 0}, {"RTAX_RTT", Const, 0}, {"RTAX_RTTVAR", Const, 0}, {"RTAX_SRC", Const, 1}, {"RTAX_SRCMASK", Const, 1}, {"RTAX_SSTHRESH", Const, 0}, {"RTAX_TAG", Const, 1}, {"RTAX_UNSPEC", Const, 0}, {"RTAX_WINDOW", Const, 0}, {"RTA_ALIGNTO", Const, 0}, {"RTA_AUTHOR", Const, 0}, {"RTA_BRD", Const, 0}, {"RTA_CACHEINFO", Const, 0}, {"RTA_DST", Const, 0}, {"RTA_FLOW", Const, 0}, {"RTA_GATEWAY", Const, 0}, {"RTA_GENMASK", Const, 0}, {"RTA_IFA", Const, 0}, {"RTA_IFP", Const, 0}, {"RTA_IIF", Const, 0}, {"RTA_LABEL", Const, 1}, {"RTA_MAX", Const, 0}, {"RTA_METRICS", Const, 0}, {"RTA_MULTIPATH", Const, 0}, {"RTA_NETMASK", Const, 0}, {"RTA_OIF", Const, 0}, {"RTA_PREFSRC", Const, 0}, {"RTA_PRIORITY", Const, 0}, {"RTA_SRC", Const, 0}, {"RTA_SRCMASK", Const, 1}, {"RTA_TABLE", Const, 0}, {"RTA_TAG", Const, 1}, {"RTA_UNSPEC", Const, 0}, {"RTCF_DIRECTSRC", Const, 0}, {"RTCF_DOREDIRECT", Const, 0}, {"RTCF_LOG", Const, 0}, {"RTCF_MASQ", Const, 0}, {"RTCF_NAT", Const, 0}, {"RTCF_VALVE", Const, 0}, {"RTF_ADDRCLASSMASK", Const, 0}, {"RTF_ADDRCONF", Const, 0}, {"RTF_ALLONLINK", Const, 0}, {"RTF_ANNOUNCE", Const, 1}, {"RTF_BLACKHOLE", Const, 0}, {"RTF_BROADCAST", Const, 0}, {"RTF_CACHE", Const, 0}, {"RTF_CLONED", Const, 1}, {"RTF_CLONING", Const, 0}, {"RTF_CONDEMNED", Const, 0}, {"RTF_DEFAULT", Const, 0}, {"RTF_DELCLONE", Const, 0}, {"RTF_DONE", Const, 0}, {"RTF_DYNAMIC", Const, 0}, {"RTF_FLOW", Const, 0}, {"RTF_FMASK", Const, 0}, {"RTF_GATEWAY", Const, 0}, {"RTF_GWFLAG_COMPAT", Const, 3}, {"RTF_HOST", Const, 0}, {"RTF_IFREF", Const, 0}, {"RTF_IFSCOPE", Const, 0}, {"RTF_INTERFACE", Const, 0}, {"RTF_IRTT", Const, 0}, {"RTF_LINKRT", Const, 0}, {"RTF_LLDATA", Const, 0}, {"RTF_LLINFO", Const, 0}, {"RTF_LOCAL", Const, 0}, {"RTF_MASK", Const, 1}, {"RTF_MODIFIED", Const, 0}, {"RTF_MPATH", Const, 1}, {"RTF_MPLS", Const, 1}, {"RTF_MSS", Const, 0}, {"RTF_MTU", Const, 0}, {"RTF_MULTICAST", Const, 0}, {"RTF_NAT", Const, 0}, {"RTF_NOFORWARD", Const, 0}, {"RTF_NONEXTHOP", Const, 0}, {"RTF_NOPMTUDISC", Const, 0}, {"RTF_PERMANENT_ARP", Const, 1}, {"RTF_PINNED", Const, 0}, {"RTF_POLICY", Const, 0}, {"RTF_PRCLONING", Const, 0}, {"RTF_PROTO1", Const, 0}, {"RTF_PROTO2", Const, 0}, {"RTF_PROTO3", Const, 0}, {"RTF_PROXY", Const, 16}, {"RTF_REINSTATE", Const, 0}, {"RTF_REJECT", Const, 0}, {"RTF_RNH_LOCKED", Const, 0}, {"RTF_ROUTER", Const, 16}, {"RTF_SOURCE", Const, 1}, {"RTF_SRC", Const, 1}, {"RTF_STATIC", Const, 0}, {"RTF_STICKY", Const, 0}, {"RTF_THROW", Const, 0}, {"RTF_TUNNEL", Const, 1}, {"RTF_UP", Const, 0}, {"RTF_USETRAILERS", Const, 1}, {"RTF_WASCLONED", Const, 0}, {"RTF_WINDOW", Const, 0}, {"RTF_XRESOLVE", Const, 0}, {"RTM_ADD", Const, 0}, {"RTM_BASE", Const, 0}, {"RTM_CHANGE", Const, 0}, {"RTM_CHGADDR", Const, 1}, {"RTM_DELACTION", Const, 0}, {"RTM_DELADDR", Const, 0}, {"RTM_DELADDRLABEL", Const, 0}, {"RTM_DELETE", Const, 0}, {"RTM_DELLINK", Const, 0}, {"RTM_DELMADDR", Const, 0}, {"RTM_DELNEIGH", Const, 0}, {"RTM_DELQDISC", Const, 0}, {"RTM_DELROUTE", Const, 0}, {"RTM_DELRULE", Const, 0}, {"RTM_DELTCLASS", Const, 0}, {"RTM_DELTFILTER", Const, 0}, {"RTM_DESYNC", Const, 1}, {"RTM_F_CLONED", Const, 0}, {"RTM_F_EQUALIZE", Const, 0}, {"RTM_F_NOTIFY", Const, 0}, {"RTM_F_PREFIX", Const, 0}, {"RTM_GET", Const, 0}, {"RTM_GET2", Const, 0}, {"RTM_GETACTION", Const, 0}, {"RTM_GETADDR", Const, 0}, {"RTM_GETADDRLABEL", Const, 0}, {"RTM_GETANYCAST", Const, 0}, {"RTM_GETDCB", Const, 0}, {"RTM_GETLINK", Const, 0}, {"RTM_GETMULTICAST", Const, 0}, {"RTM_GETNEIGH", Const, 0}, {"RTM_GETNEIGHTBL", Const, 0}, {"RTM_GETQDISC", Const, 0}, {"RTM_GETROUTE", Const, 0}, {"RTM_GETRULE", Const, 0}, {"RTM_GETTCLASS", Const, 0}, {"RTM_GETTFILTER", Const, 0}, {"RTM_IEEE80211", Const, 0}, {"RTM_IFANNOUNCE", Const, 0}, {"RTM_IFINFO", Const, 0}, {"RTM_IFINFO2", Const, 0}, {"RTM_LLINFO_UPD", Const, 1}, {"RTM_LOCK", Const, 0}, {"RTM_LOSING", Const, 0}, {"RTM_MAX", Const, 0}, {"RTM_MAXSIZE", Const, 1}, {"RTM_MISS", Const, 0}, {"RTM_NEWACTION", Const, 0}, {"RTM_NEWADDR", Const, 0}, {"RTM_NEWADDRLABEL", Const, 0}, {"RTM_NEWLINK", Const, 0}, {"RTM_NEWMADDR", Const, 0}, {"RTM_NEWMADDR2", Const, 0}, {"RTM_NEWNDUSEROPT", Const, 0}, {"RTM_NEWNEIGH", Const, 0}, {"RTM_NEWNEIGHTBL", Const, 0}, {"RTM_NEWPREFIX", Const, 0}, {"RTM_NEWQDISC", Const, 0}, {"RTM_NEWROUTE", Const, 0}, {"RTM_NEWRULE", Const, 0}, {"RTM_NEWTCLASS", Const, 0}, {"RTM_NEWTFILTER", Const, 0}, {"RTM_NR_FAMILIES", Const, 0}, {"RTM_NR_MSGTYPES", Const, 0}, {"RTM_OIFINFO", Const, 1}, {"RTM_OLDADD", Const, 0}, {"RTM_OLDDEL", Const, 0}, {"RTM_OOIFINFO", Const, 1}, {"RTM_REDIRECT", Const, 0}, {"RTM_RESOLVE", Const, 0}, {"RTM_RTTUNIT", Const, 0}, {"RTM_SETDCB", Const, 0}, {"RTM_SETGATE", Const, 1}, {"RTM_SETLINK", Const, 0}, {"RTM_SETNEIGHTBL", Const, 0}, {"RTM_VERSION", Const, 0}, {"RTNH_ALIGNTO", Const, 0}, {"RTNH_F_DEAD", Const, 0}, {"RTNH_F_ONLINK", Const, 0}, {"RTNH_F_PERVASIVE", Const, 0}, {"RTNLGRP_IPV4_IFADDR", Const, 1}, {"RTNLGRP_IPV4_MROUTE", Const, 1}, {"RTNLGRP_IPV4_ROUTE", Const, 1}, {"RTNLGRP_IPV4_RULE", Const, 1}, {"RTNLGRP_IPV6_IFADDR", Const, 1}, {"RTNLGRP_IPV6_IFINFO", Const, 1}, {"RTNLGRP_IPV6_MROUTE", Const, 1}, {"RTNLGRP_IPV6_PREFIX", Const, 1}, {"RTNLGRP_IPV6_ROUTE", Const, 1}, {"RTNLGRP_IPV6_RULE", Const, 1}, {"RTNLGRP_LINK", Const, 1}, {"RTNLGRP_ND_USEROPT", Const, 1}, {"RTNLGRP_NEIGH", Const, 1}, {"RTNLGRP_NONE", Const, 1}, {"RTNLGRP_NOTIFY", Const, 1}, {"RTNLGRP_TC", Const, 1}, {"RTN_ANYCAST", Const, 0}, {"RTN_BLACKHOLE", Const, 0}, {"RTN_BROADCAST", Const, 0}, {"RTN_LOCAL", Const, 0}, {"RTN_MAX", Const, 0}, {"RTN_MULTICAST", Const, 0}, {"RTN_NAT", Const, 0}, {"RTN_PROHIBIT", Const, 0}, {"RTN_THROW", Const, 0}, {"RTN_UNICAST", Const, 0}, {"RTN_UNREACHABLE", Const, 0}, {"RTN_UNSPEC", Const, 0}, {"RTN_XRESOLVE", Const, 0}, {"RTPROT_BIRD", Const, 0}, {"RTPROT_BOOT", Const, 0}, {"RTPROT_DHCP", Const, 0}, {"RTPROT_DNROUTED", Const, 0}, {"RTPROT_GATED", Const, 0}, {"RTPROT_KERNEL", Const, 0}, {"RTPROT_MRT", Const, 0}, {"RTPROT_NTK", Const, 0}, {"RTPROT_RA", Const, 0}, {"RTPROT_REDIRECT", Const, 0}, {"RTPROT_STATIC", Const, 0}, {"RTPROT_UNSPEC", Const, 0}, {"RTPROT_XORP", Const, 0}, {"RTPROT_ZEBRA", Const, 0}, {"RTV_EXPIRE", Const, 0}, {"RTV_HOPCOUNT", Const, 0}, {"RTV_MTU", Const, 0}, {"RTV_RPIPE", Const, 0}, {"RTV_RTT", Const, 0}, {"RTV_RTTVAR", Const, 0}, {"RTV_SPIPE", Const, 0}, {"RTV_SSTHRESH", Const, 0}, {"RTV_WEIGHT", Const, 0}, {"RT_CACHING_CONTEXT", Const, 1}, {"RT_CLASS_DEFAULT", Const, 0}, {"RT_CLASS_LOCAL", Const, 0}, {"RT_CLASS_MAIN", Const, 0}, {"RT_CLASS_MAX", Const, 0}, {"RT_CLASS_UNSPEC", Const, 0}, {"RT_DEFAULT_FIB", Const, 1}, {"RT_NORTREF", Const, 1}, {"RT_SCOPE_HOST", Const, 0}, {"RT_SCOPE_LINK", Const, 0}, {"RT_SCOPE_NOWHERE", Const, 0}, {"RT_SCOPE_SITE", Const, 0}, {"RT_SCOPE_UNIVERSE", Const, 0}, {"RT_TABLEID_MAX", Const, 1}, {"RT_TABLE_COMPAT", Const, 0}, {"RT_TABLE_DEFAULT", Const, 0}, {"RT_TABLE_LOCAL", Const, 0}, {"RT_TABLE_MAIN", Const, 0}, {"RT_TABLE_MAX", Const, 0}, {"RT_TABLE_UNSPEC", Const, 0}, {"RUSAGE_CHILDREN", Const, 0}, {"RUSAGE_SELF", Const, 0}, {"RUSAGE_THREAD", Const, 0}, {"Radvisory_t", Type, 0}, {"Radvisory_t.Count", Field, 0}, {"Radvisory_t.Offset", Field, 0}, {"Radvisory_t.Pad_cgo_0", Field, 0}, {"RawConn", Type, 9}, {"RawSockaddr", Type, 0}, {"RawSockaddr.Data", Field, 0}, {"RawSockaddr.Family", Field, 0}, {"RawSockaddr.Len", Field, 0}, {"RawSockaddrAny", Type, 0}, {"RawSockaddrAny.Addr", Field, 0}, {"RawSockaddrAny.Pad", Field, 0}, {"RawSockaddrDatalink", Type, 0}, {"RawSockaddrDatalink.Alen", Field, 0}, {"RawSockaddrDatalink.Data", Field, 0}, {"RawSockaddrDatalink.Family", Field, 0}, {"RawSockaddrDatalink.Index", Field, 0}, {"RawSockaddrDatalink.Len", Field, 0}, {"RawSockaddrDatalink.Nlen", Field, 0}, {"RawSockaddrDatalink.Pad_cgo_0", Field, 2}, {"RawSockaddrDatalink.Slen", Field, 0}, {"RawSockaddrDatalink.Type", Field, 0}, {"RawSockaddrInet4", Type, 0}, {"RawSockaddrInet4.Addr", Field, 0}, {"RawSockaddrInet4.Family", Field, 0}, {"RawSockaddrInet4.Len", Field, 0}, {"RawSockaddrInet4.Port", Field, 0}, {"RawSockaddrInet4.Zero", Field, 0}, {"RawSockaddrInet6", Type, 0}, {"RawSockaddrInet6.Addr", Field, 0}, {"RawSockaddrInet6.Family", Field, 0}, {"RawSockaddrInet6.Flowinfo", Field, 0}, {"RawSockaddrInet6.Len", Field, 0}, {"RawSockaddrInet6.Port", Field, 0}, {"RawSockaddrInet6.Scope_id", Field, 0}, {"RawSockaddrLinklayer", Type, 0}, {"RawSockaddrLinklayer.Addr", Field, 0}, {"RawSockaddrLinklayer.Family", Field, 0}, {"RawSockaddrLinklayer.Halen", Field, 0}, {"RawSockaddrLinklayer.Hatype", Field, 0}, {"RawSockaddrLinklayer.Ifindex", Field, 0}, {"RawSockaddrLinklayer.Pkttype", Field, 0}, {"RawSockaddrLinklayer.Protocol", Field, 0}, {"RawSockaddrNetlink", Type, 0}, {"RawSockaddrNetlink.Family", Field, 0}, {"RawSockaddrNetlink.Groups", Field, 0}, {"RawSockaddrNetlink.Pad", Field, 0}, {"RawSockaddrNetlink.Pid", Field, 0}, {"RawSockaddrUnix", Type, 0}, {"RawSockaddrUnix.Family", Field, 0}, {"RawSockaddrUnix.Len", Field, 0}, {"RawSockaddrUnix.Pad_cgo_0", Field, 2}, {"RawSockaddrUnix.Path", Field, 0}, {"RawSyscall", Func, 0}, {"RawSyscall6", Func, 0}, {"Read", Func, 0}, {"ReadConsole", Func, 1}, {"ReadDirectoryChanges", Func, 0}, {"ReadDirent", Func, 0}, {"ReadFile", Func, 0}, {"Readlink", Func, 0}, {"Reboot", Func, 0}, {"Recvfrom", Func, 0}, {"Recvmsg", Func, 0}, {"RegCloseKey", Func, 0}, {"RegEnumKeyEx", Func, 0}, {"RegOpenKeyEx", Func, 0}, {"RegQueryInfoKey", Func, 0}, {"RegQueryValueEx", Func, 0}, {"RemoveDirectory", Func, 0}, {"Removexattr", Func, 1}, {"Rename", Func, 0}, {"Renameat", Func, 0}, {"Revoke", Func, 0}, {"Rlimit", Type, 0}, {"Rlimit.Cur", Field, 0}, {"Rlimit.Max", Field, 0}, {"Rmdir", Func, 0}, {"RouteMessage", Type, 0}, {"RouteMessage.Data", Field, 0}, {"RouteMessage.Header", Field, 0}, {"RouteRIB", Func, 0}, {"RoutingMessage", Type, 0}, {"RtAttr", Type, 0}, {"RtAttr.Len", Field, 0}, {"RtAttr.Type", Field, 0}, {"RtGenmsg", Type, 0}, {"RtGenmsg.Family", Field, 0}, {"RtMetrics", Type, 0}, {"RtMetrics.Expire", Field, 0}, {"RtMetrics.Filler", Field, 0}, {"RtMetrics.Hopcount", Field, 0}, {"RtMetrics.Locks", Field, 0}, {"RtMetrics.Mtu", Field, 0}, {"RtMetrics.Pad", Field, 3}, {"RtMetrics.Pksent", Field, 0}, {"RtMetrics.Recvpipe", Field, 0}, {"RtMetrics.Refcnt", Field, 2}, {"RtMetrics.Rtt", Field, 0}, {"RtMetrics.Rttvar", Field, 0}, {"RtMetrics.Sendpipe", Field, 0}, {"RtMetrics.Ssthresh", Field, 0}, {"RtMetrics.Weight", Field, 0}, {"RtMsg", Type, 0}, {"RtMsg.Dst_len", Field, 0}, {"RtMsg.Family", Field, 0}, {"RtMsg.Flags", Field, 0}, {"RtMsg.Protocol", Field, 0}, {"RtMsg.Scope", Field, 0}, {"RtMsg.Src_len", Field, 0}, {"RtMsg.Table", Field, 0}, {"RtMsg.Tos", Field, 0}, {"RtMsg.Type", Field, 0}, {"RtMsghdr", Type, 0}, {"RtMsghdr.Addrs", Field, 0}, {"RtMsghdr.Errno", Field, 0}, {"RtMsghdr.Flags", Field, 0}, {"RtMsghdr.Fmask", Field, 0}, {"RtMsghdr.Hdrlen", Field, 2}, {"RtMsghdr.Index", Field, 0}, {"RtMsghdr.Inits", Field, 0}, {"RtMsghdr.Mpls", Field, 2}, {"RtMsghdr.Msglen", Field, 0}, {"RtMsghdr.Pad_cgo_0", Field, 0}, {"RtMsghdr.Pad_cgo_1", Field, 2}, {"RtMsghdr.Pid", Field, 0}, {"RtMsghdr.Priority", Field, 2}, {"RtMsghdr.Rmx", Field, 0}, {"RtMsghdr.Seq", Field, 0}, {"RtMsghdr.Tableid", Field, 2}, {"RtMsghdr.Type", Field, 0}, {"RtMsghdr.Use", Field, 0}, {"RtMsghdr.Version", Field, 0}, {"RtNexthop", Type, 0}, {"RtNexthop.Flags", Field, 0}, {"RtNexthop.Hops", Field, 0}, {"RtNexthop.Ifindex", Field, 0}, {"RtNexthop.Len", Field, 0}, {"Rusage", Type, 0}, {"Rusage.CreationTime", Field, 0}, {"Rusage.ExitTime", Field, 0}, {"Rusage.Idrss", Field, 0}, {"Rusage.Inblock", Field, 0}, {"Rusage.Isrss", Field, 0}, {"Rusage.Ixrss", Field, 0}, {"Rusage.KernelTime", Field, 0}, {"Rusage.Majflt", Field, 0}, {"Rusage.Maxrss", Field, 0}, {"Rusage.Minflt", Field, 0}, {"Rusage.Msgrcv", Field, 0}, {"Rusage.Msgsnd", Field, 0}, {"Rusage.Nivcsw", Field, 0}, {"Rusage.Nsignals", Field, 0}, {"Rusage.Nswap", Field, 0}, {"Rusage.Nvcsw", Field, 0}, {"Rusage.Oublock", Field, 0}, {"Rusage.Stime", Field, 0}, {"Rusage.UserTime", Field, 0}, {"Rusage.Utime", Field, 0}, {"SCM_BINTIME", Const, 0}, {"SCM_CREDENTIALS", Const, 0}, {"SCM_CREDS", Const, 0}, {"SCM_RIGHTS", Const, 0}, {"SCM_TIMESTAMP", Const, 0}, {"SCM_TIMESTAMPING", Const, 0}, {"SCM_TIMESTAMPNS", Const, 0}, {"SCM_TIMESTAMP_MONOTONIC", Const, 0}, {"SHUT_RD", Const, 0}, {"SHUT_RDWR", Const, 0}, {"SHUT_WR", Const, 0}, {"SID", Type, 0}, {"SIDAndAttributes", Type, 0}, {"SIDAndAttributes.Attributes", Field, 0}, {"SIDAndAttributes.Sid", Field, 0}, {"SIGABRT", Const, 0}, {"SIGALRM", Const, 0}, {"SIGBUS", Const, 0}, {"SIGCHLD", Const, 0}, {"SIGCLD", Const, 0}, {"SIGCONT", Const, 0}, {"SIGEMT", Const, 0}, {"SIGFPE", Const, 0}, {"SIGHUP", Const, 0}, {"SIGILL", Const, 0}, {"SIGINFO", Const, 0}, {"SIGINT", Const, 0}, {"SIGIO", Const, 0}, {"SIGIOT", Const, 0}, {"SIGKILL", Const, 0}, {"SIGLIBRT", Const, 1}, {"SIGLWP", Const, 0}, {"SIGPIPE", Const, 0}, {"SIGPOLL", Const, 0}, {"SIGPROF", Const, 0}, {"SIGPWR", Const, 0}, {"SIGQUIT", Const, 0}, {"SIGSEGV", Const, 0}, {"SIGSTKFLT", Const, 0}, {"SIGSTOP", Const, 0}, {"SIGSYS", Const, 0}, {"SIGTERM", Const, 0}, {"SIGTHR", Const, 0}, {"SIGTRAP", Const, 0}, {"SIGTSTP", Const, 0}, {"SIGTTIN", Const, 0}, {"SIGTTOU", Const, 0}, {"SIGUNUSED", Const, 0}, {"SIGURG", Const, 0}, {"SIGUSR1", Const, 0}, {"SIGUSR2", Const, 0}, {"SIGVTALRM", Const, 0}, {"SIGWINCH", Const, 0}, {"SIGXCPU", Const, 0}, {"SIGXFSZ", Const, 0}, {"SIOCADDDLCI", Const, 0}, {"SIOCADDMULTI", Const, 0}, {"SIOCADDRT", Const, 0}, {"SIOCAIFADDR", Const, 0}, {"SIOCAIFGROUP", Const, 0}, {"SIOCALIFADDR", Const, 0}, {"SIOCARPIPLL", Const, 0}, {"SIOCATMARK", Const, 0}, {"SIOCAUTOADDR", Const, 0}, {"SIOCAUTONETMASK", Const, 0}, {"SIOCBRDGADD", Const, 1}, {"SIOCBRDGADDS", Const, 1}, {"SIOCBRDGARL", Const, 1}, {"SIOCBRDGDADDR", Const, 1}, {"SIOCBRDGDEL", Const, 1}, {"SIOCBRDGDELS", Const, 1}, {"SIOCBRDGFLUSH", Const, 1}, {"SIOCBRDGFRL", Const, 1}, {"SIOCBRDGGCACHE", Const, 1}, {"SIOCBRDGGFD", Const, 1}, {"SIOCBRDGGHT", Const, 1}, {"SIOCBRDGGIFFLGS", Const, 1}, {"SIOCBRDGGMA", Const, 1}, {"SIOCBRDGGPARAM", Const, 1}, {"SIOCBRDGGPRI", Const, 1}, {"SIOCBRDGGRL", Const, 1}, {"SIOCBRDGGSIFS", Const, 1}, {"SIOCBRDGGTO", Const, 1}, {"SIOCBRDGIFS", Const, 1}, {"SIOCBRDGRTS", Const, 1}, {"SIOCBRDGSADDR", Const, 1}, {"SIOCBRDGSCACHE", Const, 1}, {"SIOCBRDGSFD", Const, 1}, {"SIOCBRDGSHT", Const, 1}, {"SIOCBRDGSIFCOST", Const, 1}, {"SIOCBRDGSIFFLGS", Const, 1}, {"SIOCBRDGSIFPRIO", Const, 1}, {"SIOCBRDGSMA", Const, 1}, {"SIOCBRDGSPRI", Const, 1}, {"SIOCBRDGSPROTO", Const, 1}, {"SIOCBRDGSTO", Const, 1}, {"SIOCBRDGSTXHC", Const, 1}, {"SIOCDARP", Const, 0}, {"SIOCDELDLCI", Const, 0}, {"SIOCDELMULTI", Const, 0}, {"SIOCDELRT", Const, 0}, {"SIOCDEVPRIVATE", Const, 0}, {"SIOCDIFADDR", Const, 0}, {"SIOCDIFGROUP", Const, 0}, {"SIOCDIFPHYADDR", Const, 0}, {"SIOCDLIFADDR", Const, 0}, {"SIOCDRARP", Const, 0}, {"SIOCGARP", Const, 0}, {"SIOCGDRVSPEC", Const, 0}, {"SIOCGETKALIVE", Const, 1}, {"SIOCGETLABEL", Const, 1}, {"SIOCGETPFLOW", Const, 1}, {"SIOCGETPFSYNC", Const, 1}, {"SIOCGETSGCNT", Const, 0}, {"SIOCGETVIFCNT", Const, 0}, {"SIOCGETVLAN", Const, 0}, {"SIOCGHIWAT", Const, 0}, {"SIOCGIFADDR", Const, 0}, {"SIOCGIFADDRPREF", Const, 1}, {"SIOCGIFALIAS", Const, 1}, {"SIOCGIFALTMTU", Const, 0}, {"SIOCGIFASYNCMAP", Const, 0}, {"SIOCGIFBOND", Const, 0}, {"SIOCGIFBR", Const, 0}, {"SIOCGIFBRDADDR", Const, 0}, {"SIOCGIFCAP", Const, 0}, {"SIOCGIFCONF", Const, 0}, {"SIOCGIFCOUNT", Const, 0}, {"SIOCGIFDATA", Const, 1}, {"SIOCGIFDESCR", Const, 0}, {"SIOCGIFDEVMTU", Const, 0}, {"SIOCGIFDLT", Const, 1}, {"SIOCGIFDSTADDR", Const, 0}, {"SIOCGIFENCAP", Const, 0}, {"SIOCGIFFIB", Const, 1}, {"SIOCGIFFLAGS", Const, 0}, {"SIOCGIFGATTR", Const, 1}, {"SIOCGIFGENERIC", Const, 0}, {"SIOCGIFGMEMB", Const, 0}, {"SIOCGIFGROUP", Const, 0}, {"SIOCGIFHARDMTU", Const, 3}, {"SIOCGIFHWADDR", Const, 0}, {"SIOCGIFINDEX", Const, 0}, {"SIOCGIFKPI", Const, 0}, {"SIOCGIFMAC", Const, 0}, {"SIOCGIFMAP", Const, 0}, {"SIOCGIFMEDIA", Const, 0}, {"SIOCGIFMEM", Const, 0}, {"SIOCGIFMETRIC", Const, 0}, {"SIOCGIFMTU", Const, 0}, {"SIOCGIFNAME", Const, 0}, {"SIOCGIFNETMASK", Const, 0}, {"SIOCGIFPDSTADDR", Const, 0}, {"SIOCGIFPFLAGS", Const, 0}, {"SIOCGIFPHYS", Const, 0}, {"SIOCGIFPRIORITY", Const, 1}, {"SIOCGIFPSRCADDR", Const, 0}, {"SIOCGIFRDOMAIN", Const, 1}, {"SIOCGIFRTLABEL", Const, 1}, {"SIOCGIFSLAVE", Const, 0}, {"SIOCGIFSTATUS", Const, 0}, {"SIOCGIFTIMESLOT", Const, 1}, {"SIOCGIFTXQLEN", Const, 0}, {"SIOCGIFVLAN", Const, 0}, {"SIOCGIFWAKEFLAGS", Const, 0}, {"SIOCGIFXFLAGS", Const, 1}, {"SIOCGLIFADDR", Const, 0}, {"SIOCGLIFPHYADDR", Const, 0}, {"SIOCGLIFPHYRTABLE", Const, 1}, {"SIOCGLIFPHYTTL", Const, 3}, {"SIOCGLINKSTR", Const, 1}, {"SIOCGLOWAT", Const, 0}, {"SIOCGPGRP", Const, 0}, {"SIOCGPRIVATE_0", Const, 0}, {"SIOCGPRIVATE_1", Const, 0}, {"SIOCGRARP", Const, 0}, {"SIOCGSPPPPARAMS", Const, 3}, {"SIOCGSTAMP", Const, 0}, {"SIOCGSTAMPNS", Const, 0}, {"SIOCGVH", Const, 1}, {"SIOCGVNETID", Const, 3}, {"SIOCIFCREATE", Const, 0}, {"SIOCIFCREATE2", Const, 0}, {"SIOCIFDESTROY", Const, 0}, {"SIOCIFGCLONERS", Const, 0}, {"SIOCINITIFADDR", Const, 1}, {"SIOCPROTOPRIVATE", Const, 0}, {"SIOCRSLVMULTI", Const, 0}, {"SIOCRTMSG", Const, 0}, {"SIOCSARP", Const, 0}, {"SIOCSDRVSPEC", Const, 0}, {"SIOCSETKALIVE", Const, 1}, {"SIOCSETLABEL", Const, 1}, {"SIOCSETPFLOW", Const, 1}, {"SIOCSETPFSYNC", Const, 1}, {"SIOCSETVLAN", Const, 0}, {"SIOCSHIWAT", Const, 0}, {"SIOCSIFADDR", Const, 0}, {"SIOCSIFADDRPREF", Const, 1}, {"SIOCSIFALTMTU", Const, 0}, {"SIOCSIFASYNCMAP", Const, 0}, {"SIOCSIFBOND", Const, 0}, {"SIOCSIFBR", Const, 0}, {"SIOCSIFBRDADDR", Const, 0}, {"SIOCSIFCAP", Const, 0}, {"SIOCSIFDESCR", Const, 0}, {"SIOCSIFDSTADDR", Const, 0}, {"SIOCSIFENCAP", Const, 0}, {"SIOCSIFFIB", Const, 1}, {"SIOCSIFFLAGS", Const, 0}, {"SIOCSIFGATTR", Const, 1}, {"SIOCSIFGENERIC", Const, 0}, {"SIOCSIFHWADDR", Const, 0}, {"SIOCSIFHWBROADCAST", Const, 0}, {"SIOCSIFKPI", Const, 0}, {"SIOCSIFLINK", Const, 0}, {"SIOCSIFLLADDR", Const, 0}, {"SIOCSIFMAC", Const, 0}, {"SIOCSIFMAP", Const, 0}, {"SIOCSIFMEDIA", Const, 0}, {"SIOCSIFMEM", Const, 0}, {"SIOCSIFMETRIC", Const, 0}, {"SIOCSIFMTU", Const, 0}, {"SIOCSIFNAME", Const, 0}, {"SIOCSIFNETMASK", Const, 0}, {"SIOCSIFPFLAGS", Const, 0}, {"SIOCSIFPHYADDR", Const, 0}, {"SIOCSIFPHYS", Const, 0}, {"SIOCSIFPRIORITY", Const, 1}, {"SIOCSIFRDOMAIN", Const, 1}, {"SIOCSIFRTLABEL", Const, 1}, {"SIOCSIFRVNET", Const, 0}, {"SIOCSIFSLAVE", Const, 0}, {"SIOCSIFTIMESLOT", Const, 1}, {"SIOCSIFTXQLEN", Const, 0}, {"SIOCSIFVLAN", Const, 0}, {"SIOCSIFVNET", Const, 0}, {"SIOCSIFXFLAGS", Const, 1}, {"SIOCSLIFPHYADDR", Const, 0}, {"SIOCSLIFPHYRTABLE", Const, 1}, {"SIOCSLIFPHYTTL", Const, 3}, {"SIOCSLINKSTR", Const, 1}, {"SIOCSLOWAT", Const, 0}, {"SIOCSPGRP", Const, 0}, {"SIOCSRARP", Const, 0}, {"SIOCSSPPPPARAMS", Const, 3}, {"SIOCSVH", Const, 1}, {"SIOCSVNETID", Const, 3}, {"SIOCZIFDATA", Const, 1}, {"SIO_GET_EXTENSION_FUNCTION_POINTER", Const, 1}, {"SIO_GET_INTERFACE_LIST", Const, 0}, {"SIO_KEEPALIVE_VALS", Const, 3}, {"SIO_UDP_CONNRESET", Const, 4}, {"SOCK_CLOEXEC", Const, 0}, {"SOCK_DCCP", Const, 0}, {"SOCK_DGRAM", Const, 0}, {"SOCK_FLAGS_MASK", Const, 1}, {"SOCK_MAXADDRLEN", Const, 0}, {"SOCK_NONBLOCK", Const, 0}, {"SOCK_NOSIGPIPE", Const, 1}, {"SOCK_PACKET", Const, 0}, {"SOCK_RAW", Const, 0}, {"SOCK_RDM", Const, 0}, {"SOCK_SEQPACKET", Const, 0}, {"SOCK_STREAM", Const, 0}, {"SOL_AAL", Const, 0}, {"SOL_ATM", Const, 0}, {"SOL_DECNET", Const, 0}, {"SOL_ICMPV6", Const, 0}, {"SOL_IP", Const, 0}, {"SOL_IPV6", Const, 0}, {"SOL_IRDA", Const, 0}, {"SOL_PACKET", Const, 0}, {"SOL_RAW", Const, 0}, {"SOL_SOCKET", Const, 0}, {"SOL_TCP", Const, 0}, {"SOL_X25", Const, 0}, {"SOMAXCONN", Const, 0}, {"SO_ACCEPTCONN", Const, 0}, {"SO_ACCEPTFILTER", Const, 0}, {"SO_ATTACH_FILTER", Const, 0}, {"SO_BINDANY", Const, 1}, {"SO_BINDTODEVICE", Const, 0}, {"SO_BINTIME", Const, 0}, {"SO_BROADCAST", Const, 0}, {"SO_BSDCOMPAT", Const, 0}, {"SO_DEBUG", Const, 0}, {"SO_DETACH_FILTER", Const, 0}, {"SO_DOMAIN", Const, 0}, {"SO_DONTROUTE", Const, 0}, {"SO_DONTTRUNC", Const, 0}, {"SO_ERROR", Const, 0}, {"SO_KEEPALIVE", Const, 0}, {"SO_LABEL", Const, 0}, {"SO_LINGER", Const, 0}, {"SO_LINGER_SEC", Const, 0}, {"SO_LISTENINCQLEN", Const, 0}, {"SO_LISTENQLEN", Const, 0}, {"SO_LISTENQLIMIT", Const, 0}, {"SO_MARK", Const, 0}, {"SO_NETPROC", Const, 1}, {"SO_NKE", Const, 0}, {"SO_NOADDRERR", Const, 0}, {"SO_NOHEADER", Const, 1}, {"SO_NOSIGPIPE", Const, 0}, {"SO_NOTIFYCONFLICT", Const, 0}, {"SO_NO_CHECK", Const, 0}, {"SO_NO_DDP", Const, 0}, {"SO_NO_OFFLOAD", Const, 0}, {"SO_NP_EXTENSIONS", Const, 0}, {"SO_NREAD", Const, 0}, {"SO_NUMRCVPKT", Const, 16}, {"SO_NWRITE", Const, 0}, {"SO_OOBINLINE", Const, 0}, {"SO_OVERFLOWED", Const, 1}, {"SO_PASSCRED", Const, 0}, {"SO_PASSSEC", Const, 0}, {"SO_PEERCRED", Const, 0}, {"SO_PEERLABEL", Const, 0}, {"SO_PEERNAME", Const, 0}, {"SO_PEERSEC", Const, 0}, {"SO_PRIORITY", Const, 0}, {"SO_PROTOCOL", Const, 0}, {"SO_PROTOTYPE", Const, 1}, {"SO_RANDOMPORT", Const, 0}, {"SO_RCVBUF", Const, 0}, {"SO_RCVBUFFORCE", Const, 0}, {"SO_RCVLOWAT", Const, 0}, {"SO_RCVTIMEO", Const, 0}, {"SO_RESTRICTIONS", Const, 0}, {"SO_RESTRICT_DENYIN", Const, 0}, {"SO_RESTRICT_DENYOUT", Const, 0}, {"SO_RESTRICT_DENYSET", Const, 0}, {"SO_REUSEADDR", Const, 0}, {"SO_REUSEPORT", Const, 0}, {"SO_REUSESHAREUID", Const, 0}, {"SO_RTABLE", Const, 1}, {"SO_RXQ_OVFL", Const, 0}, {"SO_SECURITY_AUTHENTICATION", Const, 0}, {"SO_SECURITY_ENCRYPTION_NETWORK", Const, 0}, {"SO_SECURITY_ENCRYPTION_TRANSPORT", Const, 0}, {"SO_SETFIB", Const, 0}, {"SO_SNDBUF", Const, 0}, {"SO_SNDBUFFORCE", Const, 0}, {"SO_SNDLOWAT", Const, 0}, {"SO_SNDTIMEO", Const, 0}, {"SO_SPLICE", Const, 1}, {"SO_TIMESTAMP", Const, 0}, {"SO_TIMESTAMPING", Const, 0}, {"SO_TIMESTAMPNS", Const, 0}, {"SO_TIMESTAMP_MONOTONIC", Const, 0}, {"SO_TYPE", Const, 0}, {"SO_UPCALLCLOSEWAIT", Const, 0}, {"SO_UPDATE_ACCEPT_CONTEXT", Const, 0}, {"SO_UPDATE_CONNECT_CONTEXT", Const, 1}, {"SO_USELOOPBACK", Const, 0}, {"SO_USER_COOKIE", Const, 1}, {"SO_VENDOR", Const, 3}, {"SO_WANTMORE", Const, 0}, {"SO_WANTOOBFLAG", Const, 0}, {"SSLExtraCertChainPolicyPara", Type, 0}, {"SSLExtraCertChainPolicyPara.AuthType", Field, 0}, {"SSLExtraCertChainPolicyPara.Checks", Field, 0}, {"SSLExtraCertChainPolicyPara.ServerName", Field, 0}, {"SSLExtraCertChainPolicyPara.Size", Field, 0}, {"STANDARD_RIGHTS_ALL", Const, 0}, {"STANDARD_RIGHTS_EXECUTE", Const, 0}, {"STANDARD_RIGHTS_READ", Const, 0}, {"STANDARD_RIGHTS_REQUIRED", Const, 0}, {"STANDARD_RIGHTS_WRITE", Const, 0}, {"STARTF_USESHOWWINDOW", Const, 0}, {"STARTF_USESTDHANDLES", Const, 0}, {"STD_ERROR_HANDLE", Const, 0}, {"STD_INPUT_HANDLE", Const, 0}, {"STD_OUTPUT_HANDLE", Const, 0}, {"SUBLANG_ENGLISH_US", Const, 0}, {"SW_FORCEMINIMIZE", Const, 0}, {"SW_HIDE", Const, 0}, {"SW_MAXIMIZE", Const, 0}, {"SW_MINIMIZE", Const, 0}, {"SW_NORMAL", Const, 0}, {"SW_RESTORE", Const, 0}, {"SW_SHOW", Const, 0}, {"SW_SHOWDEFAULT", Const, 0}, {"SW_SHOWMAXIMIZED", Const, 0}, {"SW_SHOWMINIMIZED", Const, 0}, {"SW_SHOWMINNOACTIVE", Const, 0}, {"SW_SHOWNA", Const, 0}, {"SW_SHOWNOACTIVATE", Const, 0}, {"SW_SHOWNORMAL", Const, 0}, {"SYMBOLIC_LINK_FLAG_DIRECTORY", Const, 4}, {"SYNCHRONIZE", Const, 0}, {"SYSCTL_VERSION", Const, 1}, {"SYSCTL_VERS_0", Const, 1}, {"SYSCTL_VERS_1", Const, 1}, {"SYSCTL_VERS_MASK", Const, 1}, {"SYS_ABORT2", Const, 0}, {"SYS_ACCEPT", Const, 0}, {"SYS_ACCEPT4", Const, 0}, {"SYS_ACCEPT_NOCANCEL", Const, 0}, {"SYS_ACCESS", Const, 0}, {"SYS_ACCESS_EXTENDED", Const, 0}, {"SYS_ACCT", Const, 0}, {"SYS_ADD_KEY", Const, 0}, {"SYS_ADD_PROFIL", Const, 0}, {"SYS_ADJFREQ", Const, 1}, {"SYS_ADJTIME", Const, 0}, {"SYS_ADJTIMEX", Const, 0}, {"SYS_AFS_SYSCALL", Const, 0}, {"SYS_AIO_CANCEL", Const, 0}, {"SYS_AIO_ERROR", Const, 0}, {"SYS_AIO_FSYNC", Const, 0}, {"SYS_AIO_MLOCK", Const, 14}, {"SYS_AIO_READ", Const, 0}, {"SYS_AIO_RETURN", Const, 0}, {"SYS_AIO_SUSPEND", Const, 0}, {"SYS_AIO_SUSPEND_NOCANCEL", Const, 0}, {"SYS_AIO_WAITCOMPLETE", Const, 14}, {"SYS_AIO_WRITE", Const, 0}, {"SYS_ALARM", Const, 0}, {"SYS_ARCH_PRCTL", Const, 0}, {"SYS_ARM_FADVISE64_64", Const, 0}, {"SYS_ARM_SYNC_FILE_RANGE", Const, 0}, {"SYS_ATGETMSG", Const, 0}, {"SYS_ATPGETREQ", Const, 0}, {"SYS_ATPGETRSP", Const, 0}, {"SYS_ATPSNDREQ", Const, 0}, {"SYS_ATPSNDRSP", Const, 0}, {"SYS_ATPUTMSG", Const, 0}, {"SYS_ATSOCKET", Const, 0}, {"SYS_AUDIT", Const, 0}, {"SYS_AUDITCTL", Const, 0}, {"SYS_AUDITON", Const, 0}, {"SYS_AUDIT_SESSION_JOIN", Const, 0}, {"SYS_AUDIT_SESSION_PORT", Const, 0}, {"SYS_AUDIT_SESSION_SELF", Const, 0}, {"SYS_BDFLUSH", Const, 0}, {"SYS_BIND", Const, 0}, {"SYS_BINDAT", Const, 3}, {"SYS_BREAK", Const, 0}, {"SYS_BRK", Const, 0}, {"SYS_BSDTHREAD_CREATE", Const, 0}, {"SYS_BSDTHREAD_REGISTER", Const, 0}, {"SYS_BSDTHREAD_TERMINATE", Const, 0}, {"SYS_CAPGET", Const, 0}, {"SYS_CAPSET", Const, 0}, {"SYS_CAP_ENTER", Const, 0}, {"SYS_CAP_FCNTLS_GET", Const, 1}, {"SYS_CAP_FCNTLS_LIMIT", Const, 1}, {"SYS_CAP_GETMODE", Const, 0}, {"SYS_CAP_GETRIGHTS", Const, 0}, {"SYS_CAP_IOCTLS_GET", Const, 1}, {"SYS_CAP_IOCTLS_LIMIT", Const, 1}, {"SYS_CAP_NEW", Const, 0}, {"SYS_CAP_RIGHTS_GET", Const, 1}, {"SYS_CAP_RIGHTS_LIMIT", Const, 1}, {"SYS_CHDIR", Const, 0}, {"SYS_CHFLAGS", Const, 0}, {"SYS_CHFLAGSAT", Const, 3}, {"SYS_CHMOD", Const, 0}, {"SYS_CHMOD_EXTENDED", Const, 0}, {"SYS_CHOWN", Const, 0}, {"SYS_CHOWN32", Const, 0}, {"SYS_CHROOT", Const, 0}, {"SYS_CHUD", Const, 0}, {"SYS_CLOCK_ADJTIME", Const, 0}, {"SYS_CLOCK_GETCPUCLOCKID2", Const, 1}, {"SYS_CLOCK_GETRES", Const, 0}, {"SYS_CLOCK_GETTIME", Const, 0}, {"SYS_CLOCK_NANOSLEEP", Const, 0}, {"SYS_CLOCK_SETTIME", Const, 0}, {"SYS_CLONE", Const, 0}, {"SYS_CLOSE", Const, 0}, {"SYS_CLOSEFROM", Const, 0}, {"SYS_CLOSE_NOCANCEL", Const, 0}, {"SYS_CONNECT", Const, 0}, {"SYS_CONNECTAT", Const, 3}, {"SYS_CONNECT_NOCANCEL", Const, 0}, {"SYS_COPYFILE", Const, 0}, {"SYS_CPUSET", Const, 0}, {"SYS_CPUSET_GETAFFINITY", Const, 0}, {"SYS_CPUSET_GETID", Const, 0}, {"SYS_CPUSET_SETAFFINITY", Const, 0}, {"SYS_CPUSET_SETID", Const, 0}, {"SYS_CREAT", Const, 0}, {"SYS_CREATE_MODULE", Const, 0}, {"SYS_CSOPS", Const, 0}, {"SYS_CSOPS_AUDITTOKEN", Const, 16}, {"SYS_DELETE", Const, 0}, {"SYS_DELETE_MODULE", Const, 0}, {"SYS_DUP", Const, 0}, {"SYS_DUP2", Const, 0}, {"SYS_DUP3", Const, 0}, {"SYS_EACCESS", Const, 0}, {"SYS_EPOLL_CREATE", Const, 0}, {"SYS_EPOLL_CREATE1", Const, 0}, {"SYS_EPOLL_CTL", Const, 0}, {"SYS_EPOLL_CTL_OLD", Const, 0}, {"SYS_EPOLL_PWAIT", Const, 0}, {"SYS_EPOLL_WAIT", Const, 0}, {"SYS_EPOLL_WAIT_OLD", Const, 0}, {"SYS_EVENTFD", Const, 0}, {"SYS_EVENTFD2", Const, 0}, {"SYS_EXCHANGEDATA", Const, 0}, {"SYS_EXECVE", Const, 0}, {"SYS_EXIT", Const, 0}, {"SYS_EXIT_GROUP", Const, 0}, {"SYS_EXTATTRCTL", Const, 0}, {"SYS_EXTATTR_DELETE_FD", Const, 0}, {"SYS_EXTATTR_DELETE_FILE", Const, 0}, {"SYS_EXTATTR_DELETE_LINK", Const, 0}, {"SYS_EXTATTR_GET_FD", Const, 0}, {"SYS_EXTATTR_GET_FILE", Const, 0}, {"SYS_EXTATTR_GET_LINK", Const, 0}, {"SYS_EXTATTR_LIST_FD", Const, 0}, {"SYS_EXTATTR_LIST_FILE", Const, 0}, {"SYS_EXTATTR_LIST_LINK", Const, 0}, {"SYS_EXTATTR_SET_FD", Const, 0}, {"SYS_EXTATTR_SET_FILE", Const, 0}, {"SYS_EXTATTR_SET_LINK", Const, 0}, {"SYS_FACCESSAT", Const, 0}, {"SYS_FADVISE64", Const, 0}, {"SYS_FADVISE64_64", Const, 0}, {"SYS_FALLOCATE", Const, 0}, {"SYS_FANOTIFY_INIT", Const, 0}, {"SYS_FANOTIFY_MARK", Const, 0}, {"SYS_FCHDIR", Const, 0}, {"SYS_FCHFLAGS", Const, 0}, {"SYS_FCHMOD", Const, 0}, {"SYS_FCHMODAT", Const, 0}, {"SYS_FCHMOD_EXTENDED", Const, 0}, {"SYS_FCHOWN", Const, 0}, {"SYS_FCHOWN32", Const, 0}, {"SYS_FCHOWNAT", Const, 0}, {"SYS_FCHROOT", Const, 1}, {"SYS_FCNTL", Const, 0}, {"SYS_FCNTL64", Const, 0}, {"SYS_FCNTL_NOCANCEL", Const, 0}, {"SYS_FDATASYNC", Const, 0}, {"SYS_FEXECVE", Const, 0}, {"SYS_FFCLOCK_GETCOUNTER", Const, 0}, {"SYS_FFCLOCK_GETESTIMATE", Const, 0}, {"SYS_FFCLOCK_SETESTIMATE", Const, 0}, {"SYS_FFSCTL", Const, 0}, {"SYS_FGETATTRLIST", Const, 0}, {"SYS_FGETXATTR", Const, 0}, {"SYS_FHOPEN", Const, 0}, {"SYS_FHSTAT", Const, 0}, {"SYS_FHSTATFS", Const, 0}, {"SYS_FILEPORT_MAKEFD", Const, 0}, {"SYS_FILEPORT_MAKEPORT", Const, 0}, {"SYS_FKTRACE", Const, 1}, {"SYS_FLISTXATTR", Const, 0}, {"SYS_FLOCK", Const, 0}, {"SYS_FORK", Const, 0}, {"SYS_FPATHCONF", Const, 0}, {"SYS_FREEBSD6_FTRUNCATE", Const, 0}, {"SYS_FREEBSD6_LSEEK", Const, 0}, {"SYS_FREEBSD6_MMAP", Const, 0}, {"SYS_FREEBSD6_PREAD", Const, 0}, {"SYS_FREEBSD6_PWRITE", Const, 0}, {"SYS_FREEBSD6_TRUNCATE", Const, 0}, {"SYS_FREMOVEXATTR", Const, 0}, {"SYS_FSCTL", Const, 0}, {"SYS_FSETATTRLIST", Const, 0}, {"SYS_FSETXATTR", Const, 0}, {"SYS_FSGETPATH", Const, 0}, {"SYS_FSTAT", Const, 0}, {"SYS_FSTAT64", Const, 0}, {"SYS_FSTAT64_EXTENDED", Const, 0}, {"SYS_FSTATAT", Const, 0}, {"SYS_FSTATAT64", Const, 0}, {"SYS_FSTATFS", Const, 0}, {"SYS_FSTATFS64", Const, 0}, {"SYS_FSTATV", Const, 0}, {"SYS_FSTATVFS1", Const, 1}, {"SYS_FSTAT_EXTENDED", Const, 0}, {"SYS_FSYNC", Const, 0}, {"SYS_FSYNC_NOCANCEL", Const, 0}, {"SYS_FSYNC_RANGE", Const, 1}, {"SYS_FTIME", Const, 0}, {"SYS_FTRUNCATE", Const, 0}, {"SYS_FTRUNCATE64", Const, 0}, {"SYS_FUTEX", Const, 0}, {"SYS_FUTIMENS", Const, 1}, {"SYS_FUTIMES", Const, 0}, {"SYS_FUTIMESAT", Const, 0}, {"SYS_GETATTRLIST", Const, 0}, {"SYS_GETAUDIT", Const, 0}, {"SYS_GETAUDIT_ADDR", Const, 0}, {"SYS_GETAUID", Const, 0}, {"SYS_GETCONTEXT", Const, 0}, {"SYS_GETCPU", Const, 0}, {"SYS_GETCWD", Const, 0}, {"SYS_GETDENTS", Const, 0}, {"SYS_GETDENTS64", Const, 0}, {"SYS_GETDIRENTRIES", Const, 0}, {"SYS_GETDIRENTRIES64", Const, 0}, {"SYS_GETDIRENTRIESATTR", Const, 0}, {"SYS_GETDTABLECOUNT", Const, 1}, {"SYS_GETDTABLESIZE", Const, 0}, {"SYS_GETEGID", Const, 0}, {"SYS_GETEGID32", Const, 0}, {"SYS_GETEUID", Const, 0}, {"SYS_GETEUID32", Const, 0}, {"SYS_GETFH", Const, 0}, {"SYS_GETFSSTAT", Const, 0}, {"SYS_GETFSSTAT64", Const, 0}, {"SYS_GETGID", Const, 0}, {"SYS_GETGID32", Const, 0}, {"SYS_GETGROUPS", Const, 0}, {"SYS_GETGROUPS32", Const, 0}, {"SYS_GETHOSTUUID", Const, 0}, {"SYS_GETITIMER", Const, 0}, {"SYS_GETLCID", Const, 0}, {"SYS_GETLOGIN", Const, 0}, {"SYS_GETLOGINCLASS", Const, 0}, {"SYS_GETPEERNAME", Const, 0}, {"SYS_GETPGID", Const, 0}, {"SYS_GETPGRP", Const, 0}, {"SYS_GETPID", Const, 0}, {"SYS_GETPMSG", Const, 0}, {"SYS_GETPPID", Const, 0}, {"SYS_GETPRIORITY", Const, 0}, {"SYS_GETRESGID", Const, 0}, {"SYS_GETRESGID32", Const, 0}, {"SYS_GETRESUID", Const, 0}, {"SYS_GETRESUID32", Const, 0}, {"SYS_GETRLIMIT", Const, 0}, {"SYS_GETRTABLE", Const, 1}, {"SYS_GETRUSAGE", Const, 0}, {"SYS_GETSGROUPS", Const, 0}, {"SYS_GETSID", Const, 0}, {"SYS_GETSOCKNAME", Const, 0}, {"SYS_GETSOCKOPT", Const, 0}, {"SYS_GETTHRID", Const, 1}, {"SYS_GETTID", Const, 0}, {"SYS_GETTIMEOFDAY", Const, 0}, {"SYS_GETUID", Const, 0}, {"SYS_GETUID32", Const, 0}, {"SYS_GETVFSSTAT", Const, 1}, {"SYS_GETWGROUPS", Const, 0}, {"SYS_GETXATTR", Const, 0}, {"SYS_GET_KERNEL_SYMS", Const, 0}, {"SYS_GET_MEMPOLICY", Const, 0}, {"SYS_GET_ROBUST_LIST", Const, 0}, {"SYS_GET_THREAD_AREA", Const, 0}, {"SYS_GSSD_SYSCALL", Const, 14}, {"SYS_GTTY", Const, 0}, {"SYS_IDENTITYSVC", Const, 0}, {"SYS_IDLE", Const, 0}, {"SYS_INITGROUPS", Const, 0}, {"SYS_INIT_MODULE", Const, 0}, {"SYS_INOTIFY_ADD_WATCH", Const, 0}, {"SYS_INOTIFY_INIT", Const, 0}, {"SYS_INOTIFY_INIT1", Const, 0}, {"SYS_INOTIFY_RM_WATCH", Const, 0}, {"SYS_IOCTL", Const, 0}, {"SYS_IOPERM", Const, 0}, {"SYS_IOPL", Const, 0}, {"SYS_IOPOLICYSYS", Const, 0}, {"SYS_IOPRIO_GET", Const, 0}, {"SYS_IOPRIO_SET", Const, 0}, {"SYS_IO_CANCEL", Const, 0}, {"SYS_IO_DESTROY", Const, 0}, {"SYS_IO_GETEVENTS", Const, 0}, {"SYS_IO_SETUP", Const, 0}, {"SYS_IO_SUBMIT", Const, 0}, {"SYS_IPC", Const, 0}, {"SYS_ISSETUGID", Const, 0}, {"SYS_JAIL", Const, 0}, {"SYS_JAIL_ATTACH", Const, 0}, {"SYS_JAIL_GET", Const, 0}, {"SYS_JAIL_REMOVE", Const, 0}, {"SYS_JAIL_SET", Const, 0}, {"SYS_KAS_INFO", Const, 16}, {"SYS_KDEBUG_TRACE", Const, 0}, {"SYS_KENV", Const, 0}, {"SYS_KEVENT", Const, 0}, {"SYS_KEVENT64", Const, 0}, {"SYS_KEXEC_LOAD", Const, 0}, {"SYS_KEYCTL", Const, 0}, {"SYS_KILL", Const, 0}, {"SYS_KLDFIND", Const, 0}, {"SYS_KLDFIRSTMOD", Const, 0}, {"SYS_KLDLOAD", Const, 0}, {"SYS_KLDNEXT", Const, 0}, {"SYS_KLDSTAT", Const, 0}, {"SYS_KLDSYM", Const, 0}, {"SYS_KLDUNLOAD", Const, 0}, {"SYS_KLDUNLOADF", Const, 0}, {"SYS_KMQ_NOTIFY", Const, 14}, {"SYS_KMQ_OPEN", Const, 14}, {"SYS_KMQ_SETATTR", Const, 14}, {"SYS_KMQ_TIMEDRECEIVE", Const, 14}, {"SYS_KMQ_TIMEDSEND", Const, 14}, {"SYS_KMQ_UNLINK", Const, 14}, {"SYS_KQUEUE", Const, 0}, {"SYS_KQUEUE1", Const, 1}, {"SYS_KSEM_CLOSE", Const, 14}, {"SYS_KSEM_DESTROY", Const, 14}, {"SYS_KSEM_GETVALUE", Const, 14}, {"SYS_KSEM_INIT", Const, 14}, {"SYS_KSEM_OPEN", Const, 14}, {"SYS_KSEM_POST", Const, 14}, {"SYS_KSEM_TIMEDWAIT", Const, 14}, {"SYS_KSEM_TRYWAIT", Const, 14}, {"SYS_KSEM_UNLINK", Const, 14}, {"SYS_KSEM_WAIT", Const, 14}, {"SYS_KTIMER_CREATE", Const, 0}, {"SYS_KTIMER_DELETE", Const, 0}, {"SYS_KTIMER_GETOVERRUN", Const, 0}, {"SYS_KTIMER_GETTIME", Const, 0}, {"SYS_KTIMER_SETTIME", Const, 0}, {"SYS_KTRACE", Const, 0}, {"SYS_LCHFLAGS", Const, 0}, {"SYS_LCHMOD", Const, 0}, {"SYS_LCHOWN", Const, 0}, {"SYS_LCHOWN32", Const, 0}, {"SYS_LEDGER", Const, 16}, {"SYS_LGETFH", Const, 0}, {"SYS_LGETXATTR", Const, 0}, {"SYS_LINK", Const, 0}, {"SYS_LINKAT", Const, 0}, {"SYS_LIO_LISTIO", Const, 0}, {"SYS_LISTEN", Const, 0}, {"SYS_LISTXATTR", Const, 0}, {"SYS_LLISTXATTR", Const, 0}, {"SYS_LOCK", Const, 0}, {"SYS_LOOKUP_DCOOKIE", Const, 0}, {"SYS_LPATHCONF", Const, 0}, {"SYS_LREMOVEXATTR", Const, 0}, {"SYS_LSEEK", Const, 0}, {"SYS_LSETXATTR", Const, 0}, {"SYS_LSTAT", Const, 0}, {"SYS_LSTAT64", Const, 0}, {"SYS_LSTAT64_EXTENDED", Const, 0}, {"SYS_LSTATV", Const, 0}, {"SYS_LSTAT_EXTENDED", Const, 0}, {"SYS_LUTIMES", Const, 0}, {"SYS_MAC_SYSCALL", Const, 0}, {"SYS_MADVISE", Const, 0}, {"SYS_MADVISE1", Const, 0}, {"SYS_MAXSYSCALL", Const, 0}, {"SYS_MBIND", Const, 0}, {"SYS_MIGRATE_PAGES", Const, 0}, {"SYS_MINCORE", Const, 0}, {"SYS_MINHERIT", Const, 0}, {"SYS_MKCOMPLEX", Const, 0}, {"SYS_MKDIR", Const, 0}, {"SYS_MKDIRAT", Const, 0}, {"SYS_MKDIR_EXTENDED", Const, 0}, {"SYS_MKFIFO", Const, 0}, {"SYS_MKFIFOAT", Const, 0}, {"SYS_MKFIFO_EXTENDED", Const, 0}, {"SYS_MKNOD", Const, 0}, {"SYS_MKNODAT", Const, 0}, {"SYS_MLOCK", Const, 0}, {"SYS_MLOCKALL", Const, 0}, {"SYS_MMAP", Const, 0}, {"SYS_MMAP2", Const, 0}, {"SYS_MODCTL", Const, 1}, {"SYS_MODFIND", Const, 0}, {"SYS_MODFNEXT", Const, 0}, {"SYS_MODIFY_LDT", Const, 0}, {"SYS_MODNEXT", Const, 0}, {"SYS_MODSTAT", Const, 0}, {"SYS_MODWATCH", Const, 0}, {"SYS_MOUNT", Const, 0}, {"SYS_MOVE_PAGES", Const, 0}, {"SYS_MPROTECT", Const, 0}, {"SYS_MPX", Const, 0}, {"SYS_MQUERY", Const, 1}, {"SYS_MQ_GETSETATTR", Const, 0}, {"SYS_MQ_NOTIFY", Const, 0}, {"SYS_MQ_OPEN", Const, 0}, {"SYS_MQ_TIMEDRECEIVE", Const, 0}, {"SYS_MQ_TIMEDSEND", Const, 0}, {"SYS_MQ_UNLINK", Const, 0}, {"SYS_MREMAP", Const, 0}, {"SYS_MSGCTL", Const, 0}, {"SYS_MSGGET", Const, 0}, {"SYS_MSGRCV", Const, 0}, {"SYS_MSGRCV_NOCANCEL", Const, 0}, {"SYS_MSGSND", Const, 0}, {"SYS_MSGSND_NOCANCEL", Const, 0}, {"SYS_MSGSYS", Const, 0}, {"SYS_MSYNC", Const, 0}, {"SYS_MSYNC_NOCANCEL", Const, 0}, {"SYS_MUNLOCK", Const, 0}, {"SYS_MUNLOCKALL", Const, 0}, {"SYS_MUNMAP", Const, 0}, {"SYS_NAME_TO_HANDLE_AT", Const, 0}, {"SYS_NANOSLEEP", Const, 0}, {"SYS_NEWFSTATAT", Const, 0}, {"SYS_NFSCLNT", Const, 0}, {"SYS_NFSSERVCTL", Const, 0}, {"SYS_NFSSVC", Const, 0}, {"SYS_NFSTAT", Const, 0}, {"SYS_NICE", Const, 0}, {"SYS_NLM_SYSCALL", Const, 14}, {"SYS_NLSTAT", Const, 0}, {"SYS_NMOUNT", Const, 0}, {"SYS_NSTAT", Const, 0}, {"SYS_NTP_ADJTIME", Const, 0}, {"SYS_NTP_GETTIME", Const, 0}, {"SYS_NUMA_GETAFFINITY", Const, 14}, {"SYS_NUMA_SETAFFINITY", Const, 14}, {"SYS_OABI_SYSCALL_BASE", Const, 0}, {"SYS_OBREAK", Const, 0}, {"SYS_OLDFSTAT", Const, 0}, {"SYS_OLDLSTAT", Const, 0}, {"SYS_OLDOLDUNAME", Const, 0}, {"SYS_OLDSTAT", Const, 0}, {"SYS_OLDUNAME", Const, 0}, {"SYS_OPEN", Const, 0}, {"SYS_OPENAT", Const, 0}, {"SYS_OPENBSD_POLL", Const, 0}, {"SYS_OPEN_BY_HANDLE_AT", Const, 0}, {"SYS_OPEN_DPROTECTED_NP", Const, 16}, {"SYS_OPEN_EXTENDED", Const, 0}, {"SYS_OPEN_NOCANCEL", Const, 0}, {"SYS_OVADVISE", Const, 0}, {"SYS_PACCEPT", Const, 1}, {"SYS_PATHCONF", Const, 0}, {"SYS_PAUSE", Const, 0}, {"SYS_PCICONFIG_IOBASE", Const, 0}, {"SYS_PCICONFIG_READ", Const, 0}, {"SYS_PCICONFIG_WRITE", Const, 0}, {"SYS_PDFORK", Const, 0}, {"SYS_PDGETPID", Const, 0}, {"SYS_PDKILL", Const, 0}, {"SYS_PERF_EVENT_OPEN", Const, 0}, {"SYS_PERSONALITY", Const, 0}, {"SYS_PID_HIBERNATE", Const, 0}, {"SYS_PID_RESUME", Const, 0}, {"SYS_PID_SHUTDOWN_SOCKETS", Const, 0}, {"SYS_PID_SUSPEND", Const, 0}, {"SYS_PIPE", Const, 0}, {"SYS_PIPE2", Const, 0}, {"SYS_PIVOT_ROOT", Const, 0}, {"SYS_PMC_CONTROL", Const, 1}, {"SYS_PMC_GET_INFO", Const, 1}, {"SYS_POLL", Const, 0}, {"SYS_POLLTS", Const, 1}, {"SYS_POLL_NOCANCEL", Const, 0}, {"SYS_POSIX_FADVISE", Const, 0}, {"SYS_POSIX_FALLOCATE", Const, 0}, {"SYS_POSIX_OPENPT", Const, 0}, {"SYS_POSIX_SPAWN", Const, 0}, {"SYS_PPOLL", Const, 0}, {"SYS_PRCTL", Const, 0}, {"SYS_PREAD", Const, 0}, {"SYS_PREAD64", Const, 0}, {"SYS_PREADV", Const, 0}, {"SYS_PREAD_NOCANCEL", Const, 0}, {"SYS_PRLIMIT64", Const, 0}, {"SYS_PROCCTL", Const, 3}, {"SYS_PROCESS_POLICY", Const, 0}, {"SYS_PROCESS_VM_READV", Const, 0}, {"SYS_PROCESS_VM_WRITEV", Const, 0}, {"SYS_PROC_INFO", Const, 0}, {"SYS_PROF", Const, 0}, {"SYS_PROFIL", Const, 0}, {"SYS_PSELECT", Const, 0}, {"SYS_PSELECT6", Const, 0}, {"SYS_PSET_ASSIGN", Const, 1}, {"SYS_PSET_CREATE", Const, 1}, {"SYS_PSET_DESTROY", Const, 1}, {"SYS_PSYNCH_CVBROAD", Const, 0}, {"SYS_PSYNCH_CVCLRPREPOST", Const, 0}, {"SYS_PSYNCH_CVSIGNAL", Const, 0}, {"SYS_PSYNCH_CVWAIT", Const, 0}, {"SYS_PSYNCH_MUTEXDROP", Const, 0}, {"SYS_PSYNCH_MUTEXWAIT", Const, 0}, {"SYS_PSYNCH_RW_DOWNGRADE", Const, 0}, {"SYS_PSYNCH_RW_LONGRDLOCK", Const, 0}, {"SYS_PSYNCH_RW_RDLOCK", Const, 0}, {"SYS_PSYNCH_RW_UNLOCK", Const, 0}, {"SYS_PSYNCH_RW_UNLOCK2", Const, 0}, {"SYS_PSYNCH_RW_UPGRADE", Const, 0}, {"SYS_PSYNCH_RW_WRLOCK", Const, 0}, {"SYS_PSYNCH_RW_YIELDWRLOCK", Const, 0}, {"SYS_PTRACE", Const, 0}, {"SYS_PUTPMSG", Const, 0}, {"SYS_PWRITE", Const, 0}, {"SYS_PWRITE64", Const, 0}, {"SYS_PWRITEV", Const, 0}, {"SYS_PWRITE_NOCANCEL", Const, 0}, {"SYS_QUERY_MODULE", Const, 0}, {"SYS_QUOTACTL", Const, 0}, {"SYS_RASCTL", Const, 1}, {"SYS_RCTL_ADD_RULE", Const, 0}, {"SYS_RCTL_GET_LIMITS", Const, 0}, {"SYS_RCTL_GET_RACCT", Const, 0}, {"SYS_RCTL_GET_RULES", Const, 0}, {"SYS_RCTL_REMOVE_RULE", Const, 0}, {"SYS_READ", Const, 0}, {"SYS_READAHEAD", Const, 0}, {"SYS_READDIR", Const, 0}, {"SYS_READLINK", Const, 0}, {"SYS_READLINKAT", Const, 0}, {"SYS_READV", Const, 0}, {"SYS_READV_NOCANCEL", Const, 0}, {"SYS_READ_NOCANCEL", Const, 0}, {"SYS_REBOOT", Const, 0}, {"SYS_RECV", Const, 0}, {"SYS_RECVFROM", Const, 0}, {"SYS_RECVFROM_NOCANCEL", Const, 0}, {"SYS_RECVMMSG", Const, 0}, {"SYS_RECVMSG", Const, 0}, {"SYS_RECVMSG_NOCANCEL", Const, 0}, {"SYS_REMAP_FILE_PAGES", Const, 0}, {"SYS_REMOVEXATTR", Const, 0}, {"SYS_RENAME", Const, 0}, {"SYS_RENAMEAT", Const, 0}, {"SYS_REQUEST_KEY", Const, 0}, {"SYS_RESTART_SYSCALL", Const, 0}, {"SYS_REVOKE", Const, 0}, {"SYS_RFORK", Const, 0}, {"SYS_RMDIR", Const, 0}, {"SYS_RTPRIO", Const, 0}, {"SYS_RTPRIO_THREAD", Const, 0}, {"SYS_RT_SIGACTION", Const, 0}, {"SYS_RT_SIGPENDING", Const, 0}, {"SYS_RT_SIGPROCMASK", Const, 0}, {"SYS_RT_SIGQUEUEINFO", Const, 0}, {"SYS_RT_SIGRETURN", Const, 0}, {"SYS_RT_SIGSUSPEND", Const, 0}, {"SYS_RT_SIGTIMEDWAIT", Const, 0}, {"SYS_RT_TGSIGQUEUEINFO", Const, 0}, {"SYS_SBRK", Const, 0}, {"SYS_SCHED_GETAFFINITY", Const, 0}, {"SYS_SCHED_GETPARAM", Const, 0}, {"SYS_SCHED_GETSCHEDULER", Const, 0}, {"SYS_SCHED_GET_PRIORITY_MAX", Const, 0}, {"SYS_SCHED_GET_PRIORITY_MIN", Const, 0}, {"SYS_SCHED_RR_GET_INTERVAL", Const, 0}, {"SYS_SCHED_SETAFFINITY", Const, 0}, {"SYS_SCHED_SETPARAM", Const, 0}, {"SYS_SCHED_SETSCHEDULER", Const, 0}, {"SYS_SCHED_YIELD", Const, 0}, {"SYS_SCTP_GENERIC_RECVMSG", Const, 0}, {"SYS_SCTP_GENERIC_SENDMSG", Const, 0}, {"SYS_SCTP_GENERIC_SENDMSG_IOV", Const, 0}, {"SYS_SCTP_PEELOFF", Const, 0}, {"SYS_SEARCHFS", Const, 0}, {"SYS_SECURITY", Const, 0}, {"SYS_SELECT", Const, 0}, {"SYS_SELECT_NOCANCEL", Const, 0}, {"SYS_SEMCONFIG", Const, 1}, {"SYS_SEMCTL", Const, 0}, {"SYS_SEMGET", Const, 0}, {"SYS_SEMOP", Const, 0}, {"SYS_SEMSYS", Const, 0}, {"SYS_SEMTIMEDOP", Const, 0}, {"SYS_SEM_CLOSE", Const, 0}, {"SYS_SEM_DESTROY", Const, 0}, {"SYS_SEM_GETVALUE", Const, 0}, {"SYS_SEM_INIT", Const, 0}, {"SYS_SEM_OPEN", Const, 0}, {"SYS_SEM_POST", Const, 0}, {"SYS_SEM_TRYWAIT", Const, 0}, {"SYS_SEM_UNLINK", Const, 0}, {"SYS_SEM_WAIT", Const, 0}, {"SYS_SEM_WAIT_NOCANCEL", Const, 0}, {"SYS_SEND", Const, 0}, {"SYS_SENDFILE", Const, 0}, {"SYS_SENDFILE64", Const, 0}, {"SYS_SENDMMSG", Const, 0}, {"SYS_SENDMSG", Const, 0}, {"SYS_SENDMSG_NOCANCEL", Const, 0}, {"SYS_SENDTO", Const, 0}, {"SYS_SENDTO_NOCANCEL", Const, 0}, {"SYS_SETATTRLIST", Const, 0}, {"SYS_SETAUDIT", Const, 0}, {"SYS_SETAUDIT_ADDR", Const, 0}, {"SYS_SETAUID", Const, 0}, {"SYS_SETCONTEXT", Const, 0}, {"SYS_SETDOMAINNAME", Const, 0}, {"SYS_SETEGID", Const, 0}, {"SYS_SETEUID", Const, 0}, {"SYS_SETFIB", Const, 0}, {"SYS_SETFSGID", Const, 0}, {"SYS_SETFSGID32", Const, 0}, {"SYS_SETFSUID", Const, 0}, {"SYS_SETFSUID32", Const, 0}, {"SYS_SETGID", Const, 0}, {"SYS_SETGID32", Const, 0}, {"SYS_SETGROUPS", Const, 0}, {"SYS_SETGROUPS32", Const, 0}, {"SYS_SETHOSTNAME", Const, 0}, {"SYS_SETITIMER", Const, 0}, {"SYS_SETLCID", Const, 0}, {"SYS_SETLOGIN", Const, 0}, {"SYS_SETLOGINCLASS", Const, 0}, {"SYS_SETNS", Const, 0}, {"SYS_SETPGID", Const, 0}, {"SYS_SETPRIORITY", Const, 0}, {"SYS_SETPRIVEXEC", Const, 0}, {"SYS_SETREGID", Const, 0}, {"SYS_SETREGID32", Const, 0}, {"SYS_SETRESGID", Const, 0}, {"SYS_SETRESGID32", Const, 0}, {"SYS_SETRESUID", Const, 0}, {"SYS_SETRESUID32", Const, 0}, {"SYS_SETREUID", Const, 0}, {"SYS_SETREUID32", Const, 0}, {"SYS_SETRLIMIT", Const, 0}, {"SYS_SETRTABLE", Const, 1}, {"SYS_SETSGROUPS", Const, 0}, {"SYS_SETSID", Const, 0}, {"SYS_SETSOCKOPT", Const, 0}, {"SYS_SETTID", Const, 0}, {"SYS_SETTID_WITH_PID", Const, 0}, {"SYS_SETTIMEOFDAY", Const, 0}, {"SYS_SETUID", Const, 0}, {"SYS_SETUID32", Const, 0}, {"SYS_SETWGROUPS", Const, 0}, {"SYS_SETXATTR", Const, 0}, {"SYS_SET_MEMPOLICY", Const, 0}, {"SYS_SET_ROBUST_LIST", Const, 0}, {"SYS_SET_THREAD_AREA", Const, 0}, {"SYS_SET_TID_ADDRESS", Const, 0}, {"SYS_SGETMASK", Const, 0}, {"SYS_SHARED_REGION_CHECK_NP", Const, 0}, {"SYS_SHARED_REGION_MAP_AND_SLIDE_NP", Const, 0}, {"SYS_SHMAT", Const, 0}, {"SYS_SHMCTL", Const, 0}, {"SYS_SHMDT", Const, 0}, {"SYS_SHMGET", Const, 0}, {"SYS_SHMSYS", Const, 0}, {"SYS_SHM_OPEN", Const, 0}, {"SYS_SHM_UNLINK", Const, 0}, {"SYS_SHUTDOWN", Const, 0}, {"SYS_SIGACTION", Const, 0}, {"SYS_SIGALTSTACK", Const, 0}, {"SYS_SIGNAL", Const, 0}, {"SYS_SIGNALFD", Const, 0}, {"SYS_SIGNALFD4", Const, 0}, {"SYS_SIGPENDING", Const, 0}, {"SYS_SIGPROCMASK", Const, 0}, {"SYS_SIGQUEUE", Const, 0}, {"SYS_SIGQUEUEINFO", Const, 1}, {"SYS_SIGRETURN", Const, 0}, {"SYS_SIGSUSPEND", Const, 0}, {"SYS_SIGSUSPEND_NOCANCEL", Const, 0}, {"SYS_SIGTIMEDWAIT", Const, 0}, {"SYS_SIGWAIT", Const, 0}, {"SYS_SIGWAITINFO", Const, 0}, {"SYS_SOCKET", Const, 0}, {"SYS_SOCKETCALL", Const, 0}, {"SYS_SOCKETPAIR", Const, 0}, {"SYS_SPLICE", Const, 0}, {"SYS_SSETMASK", Const, 0}, {"SYS_SSTK", Const, 0}, {"SYS_STACK_SNAPSHOT", Const, 0}, {"SYS_STAT", Const, 0}, {"SYS_STAT64", Const, 0}, {"SYS_STAT64_EXTENDED", Const, 0}, {"SYS_STATFS", Const, 0}, {"SYS_STATFS64", Const, 0}, {"SYS_STATV", Const, 0}, {"SYS_STATVFS1", Const, 1}, {"SYS_STAT_EXTENDED", Const, 0}, {"SYS_STIME", Const, 0}, {"SYS_STTY", Const, 0}, {"SYS_SWAPCONTEXT", Const, 0}, {"SYS_SWAPCTL", Const, 1}, {"SYS_SWAPOFF", Const, 0}, {"SYS_SWAPON", Const, 0}, {"SYS_SYMLINK", Const, 0}, {"SYS_SYMLINKAT", Const, 0}, {"SYS_SYNC", Const, 0}, {"SYS_SYNCFS", Const, 0}, {"SYS_SYNC_FILE_RANGE", Const, 0}, {"SYS_SYSARCH", Const, 0}, {"SYS_SYSCALL", Const, 0}, {"SYS_SYSCALL_BASE", Const, 0}, {"SYS_SYSFS", Const, 0}, {"SYS_SYSINFO", Const, 0}, {"SYS_SYSLOG", Const, 0}, {"SYS_TEE", Const, 0}, {"SYS_TGKILL", Const, 0}, {"SYS_THREAD_SELFID", Const, 0}, {"SYS_THR_CREATE", Const, 0}, {"SYS_THR_EXIT", Const, 0}, {"SYS_THR_KILL", Const, 0}, {"SYS_THR_KILL2", Const, 0}, {"SYS_THR_NEW", Const, 0}, {"SYS_THR_SELF", Const, 0}, {"SYS_THR_SET_NAME", Const, 0}, {"SYS_THR_SUSPEND", Const, 0}, {"SYS_THR_WAKE", Const, 0}, {"SYS_TIME", Const, 0}, {"SYS_TIMERFD_CREATE", Const, 0}, {"SYS_TIMERFD_GETTIME", Const, 0}, {"SYS_TIMERFD_SETTIME", Const, 0}, {"SYS_TIMER_CREATE", Const, 0}, {"SYS_TIMER_DELETE", Const, 0}, {"SYS_TIMER_GETOVERRUN", Const, 0}, {"SYS_TIMER_GETTIME", Const, 0}, {"SYS_TIMER_SETTIME", Const, 0}, {"SYS_TIMES", Const, 0}, {"SYS_TKILL", Const, 0}, {"SYS_TRUNCATE", Const, 0}, {"SYS_TRUNCATE64", Const, 0}, {"SYS_TUXCALL", Const, 0}, {"SYS_UGETRLIMIT", Const, 0}, {"SYS_ULIMIT", Const, 0}, {"SYS_UMASK", Const, 0}, {"SYS_UMASK_EXTENDED", Const, 0}, {"SYS_UMOUNT", Const, 0}, {"SYS_UMOUNT2", Const, 0}, {"SYS_UNAME", Const, 0}, {"SYS_UNDELETE", Const, 0}, {"SYS_UNLINK", Const, 0}, {"SYS_UNLINKAT", Const, 0}, {"SYS_UNMOUNT", Const, 0}, {"SYS_UNSHARE", Const, 0}, {"SYS_USELIB", Const, 0}, {"SYS_USTAT", Const, 0}, {"SYS_UTIME", Const, 0}, {"SYS_UTIMENSAT", Const, 0}, {"SYS_UTIMES", Const, 0}, {"SYS_UTRACE", Const, 0}, {"SYS_UUIDGEN", Const, 0}, {"SYS_VADVISE", Const, 1}, {"SYS_VFORK", Const, 0}, {"SYS_VHANGUP", Const, 0}, {"SYS_VM86", Const, 0}, {"SYS_VM86OLD", Const, 0}, {"SYS_VMSPLICE", Const, 0}, {"SYS_VM_PRESSURE_MONITOR", Const, 0}, {"SYS_VSERVER", Const, 0}, {"SYS_WAIT4", Const, 0}, {"SYS_WAIT4_NOCANCEL", Const, 0}, {"SYS_WAIT6", Const, 1}, {"SYS_WAITEVENT", Const, 0}, {"SYS_WAITID", Const, 0}, {"SYS_WAITID_NOCANCEL", Const, 0}, {"SYS_WAITPID", Const, 0}, {"SYS_WATCHEVENT", Const, 0}, {"SYS_WORKQ_KERNRETURN", Const, 0}, {"SYS_WORKQ_OPEN", Const, 0}, {"SYS_WRITE", Const, 0}, {"SYS_WRITEV", Const, 0}, {"SYS_WRITEV_NOCANCEL", Const, 0}, {"SYS_WRITE_NOCANCEL", Const, 0}, {"SYS_YIELD", Const, 0}, {"SYS__LLSEEK", Const, 0}, {"SYS__LWP_CONTINUE", Const, 1}, {"SYS__LWP_CREATE", Const, 1}, {"SYS__LWP_CTL", Const, 1}, {"SYS__LWP_DETACH", Const, 1}, {"SYS__LWP_EXIT", Const, 1}, {"SYS__LWP_GETNAME", Const, 1}, {"SYS__LWP_GETPRIVATE", Const, 1}, {"SYS__LWP_KILL", Const, 1}, {"SYS__LWP_PARK", Const, 1}, {"SYS__LWP_SELF", Const, 1}, {"SYS__LWP_SETNAME", Const, 1}, {"SYS__LWP_SETPRIVATE", Const, 1}, {"SYS__LWP_SUSPEND", Const, 1}, {"SYS__LWP_UNPARK", Const, 1}, {"SYS__LWP_UNPARK_ALL", Const, 1}, {"SYS__LWP_WAIT", Const, 1}, {"SYS__LWP_WAKEUP", Const, 1}, {"SYS__NEWSELECT", Const, 0}, {"SYS__PSET_BIND", Const, 1}, {"SYS__SCHED_GETAFFINITY", Const, 1}, {"SYS__SCHED_GETPARAM", Const, 1}, {"SYS__SCHED_SETAFFINITY", Const, 1}, {"SYS__SCHED_SETPARAM", Const, 1}, {"SYS__SYSCTL", Const, 0}, {"SYS__UMTX_LOCK", Const, 0}, {"SYS__UMTX_OP", Const, 0}, {"SYS__UMTX_UNLOCK", Const, 0}, {"SYS___ACL_ACLCHECK_FD", Const, 0}, {"SYS___ACL_ACLCHECK_FILE", Const, 0}, {"SYS___ACL_ACLCHECK_LINK", Const, 0}, {"SYS___ACL_DELETE_FD", Const, 0}, {"SYS___ACL_DELETE_FILE", Const, 0}, {"SYS___ACL_DELETE_LINK", Const, 0}, {"SYS___ACL_GET_FD", Const, 0}, {"SYS___ACL_GET_FILE", Const, 0}, {"SYS___ACL_GET_LINK", Const, 0}, {"SYS___ACL_SET_FD", Const, 0}, {"SYS___ACL_SET_FILE", Const, 0}, {"SYS___ACL_SET_LINK", Const, 0}, {"SYS___CAP_RIGHTS_GET", Const, 14}, {"SYS___CLONE", Const, 1}, {"SYS___DISABLE_THREADSIGNAL", Const, 0}, {"SYS___GETCWD", Const, 0}, {"SYS___GETLOGIN", Const, 1}, {"SYS___GET_TCB", Const, 1}, {"SYS___MAC_EXECVE", Const, 0}, {"SYS___MAC_GETFSSTAT", Const, 0}, {"SYS___MAC_GET_FD", Const, 0}, {"SYS___MAC_GET_FILE", Const, 0}, {"SYS___MAC_GET_LCID", Const, 0}, {"SYS___MAC_GET_LCTX", Const, 0}, {"SYS___MAC_GET_LINK", Const, 0}, {"SYS___MAC_GET_MOUNT", Const, 0}, {"SYS___MAC_GET_PID", Const, 0}, {"SYS___MAC_GET_PROC", Const, 0}, {"SYS___MAC_MOUNT", Const, 0}, {"SYS___MAC_SET_FD", Const, 0}, {"SYS___MAC_SET_FILE", Const, 0}, {"SYS___MAC_SET_LCTX", Const, 0}, {"SYS___MAC_SET_LINK", Const, 0}, {"SYS___MAC_SET_PROC", Const, 0}, {"SYS___MAC_SYSCALL", Const, 0}, {"SYS___OLD_SEMWAIT_SIGNAL", Const, 0}, {"SYS___OLD_SEMWAIT_SIGNAL_NOCANCEL", Const, 0}, {"SYS___POSIX_CHOWN", Const, 1}, {"SYS___POSIX_FCHOWN", Const, 1}, {"SYS___POSIX_LCHOWN", Const, 1}, {"SYS___POSIX_RENAME", Const, 1}, {"SYS___PTHREAD_CANCELED", Const, 0}, {"SYS___PTHREAD_CHDIR", Const, 0}, {"SYS___PTHREAD_FCHDIR", Const, 0}, {"SYS___PTHREAD_KILL", Const, 0}, {"SYS___PTHREAD_MARKCANCEL", Const, 0}, {"SYS___PTHREAD_SIGMASK", Const, 0}, {"SYS___QUOTACTL", Const, 1}, {"SYS___SEMCTL", Const, 1}, {"SYS___SEMWAIT_SIGNAL", Const, 0}, {"SYS___SEMWAIT_SIGNAL_NOCANCEL", Const, 0}, {"SYS___SETLOGIN", Const, 1}, {"SYS___SETUGID", Const, 0}, {"SYS___SET_TCB", Const, 1}, {"SYS___SIGACTION_SIGTRAMP", Const, 1}, {"SYS___SIGTIMEDWAIT", Const, 1}, {"SYS___SIGWAIT", Const, 0}, {"SYS___SIGWAIT_NOCANCEL", Const, 0}, {"SYS___SYSCTL", Const, 0}, {"SYS___TFORK", Const, 1}, {"SYS___THREXIT", Const, 1}, {"SYS___THRSIGDIVERT", Const, 1}, {"SYS___THRSLEEP", Const, 1}, {"SYS___THRWAKEUP", Const, 1}, {"S_ARCH1", Const, 1}, {"S_ARCH2", Const, 1}, {"S_BLKSIZE", Const, 0}, {"S_IEXEC", Const, 0}, {"S_IFBLK", Const, 0}, {"S_IFCHR", Const, 0}, {"S_IFDIR", Const, 0}, {"S_IFIFO", Const, 0}, {"S_IFLNK", Const, 0}, {"S_IFMT", Const, 0}, {"S_IFREG", Const, 0}, {"S_IFSOCK", Const, 0}, {"S_IFWHT", Const, 0}, {"S_IREAD", Const, 0}, {"S_IRGRP", Const, 0}, {"S_IROTH", Const, 0}, {"S_IRUSR", Const, 0}, {"S_IRWXG", Const, 0}, {"S_IRWXO", Const, 0}, {"S_IRWXU", Const, 0}, {"S_ISGID", Const, 0}, {"S_ISTXT", Const, 0}, {"S_ISUID", Const, 0}, {"S_ISVTX", Const, 0}, {"S_IWGRP", Const, 0}, {"S_IWOTH", Const, 0}, {"S_IWRITE", Const, 0}, {"S_IWUSR", Const, 0}, {"S_IXGRP", Const, 0}, {"S_IXOTH", Const, 0}, {"S_IXUSR", Const, 0}, {"S_LOGIN_SET", Const, 1}, {"SecurityAttributes", Type, 0}, {"SecurityAttributes.InheritHandle", Field, 0}, {"SecurityAttributes.Length", Field, 0}, {"SecurityAttributes.SecurityDescriptor", Field, 0}, {"Seek", Func, 0}, {"Select", Func, 0}, {"Sendfile", Func, 0}, {"Sendmsg", Func, 0}, {"SendmsgN", Func, 3}, {"Sendto", Func, 0}, {"Servent", Type, 0}, {"Servent.Aliases", Field, 0}, {"Servent.Name", Field, 0}, {"Servent.Port", Field, 0}, {"Servent.Proto", Field, 0}, {"SetBpf", Func, 0}, {"SetBpfBuflen", Func, 0}, {"SetBpfDatalink", Func, 0}, {"SetBpfHeadercmpl", Func, 0}, {"SetBpfImmediate", Func, 0}, {"SetBpfInterface", Func, 0}, {"SetBpfPromisc", Func, 0}, {"SetBpfTimeout", Func, 0}, {"SetCurrentDirectory", Func, 0}, {"SetEndOfFile", Func, 0}, {"SetEnvironmentVariable", Func, 0}, {"SetFileAttributes", Func, 0}, {"SetFileCompletionNotificationModes", Func, 2}, {"SetFilePointer", Func, 0}, {"SetFileTime", Func, 0}, {"SetHandleInformation", Func, 0}, {"SetKevent", Func, 0}, {"SetLsfPromisc", Func, 0}, {"SetNonblock", Func, 0}, {"Setdomainname", Func, 0}, {"Setegid", Func, 0}, {"Setenv", Func, 0}, {"Seteuid", Func, 0}, {"Setfsgid", Func, 0}, {"Setfsuid", Func, 0}, {"Setgid", Func, 0}, {"Setgroups", Func, 0}, {"Sethostname", Func, 0}, {"Setlogin", Func, 0}, {"Setpgid", Func, 0}, {"Setpriority", Func, 0}, {"Setprivexec", Func, 0}, {"Setregid", Func, 0}, {"Setresgid", Func, 0}, {"Setresuid", Func, 0}, {"Setreuid", Func, 0}, {"Setrlimit", Func, 0}, {"Setsid", Func, 0}, {"Setsockopt", Func, 0}, {"SetsockoptByte", Func, 0}, {"SetsockoptICMPv6Filter", Func, 2}, {"SetsockoptIPMreq", Func, 0}, {"SetsockoptIPMreqn", Func, 0}, {"SetsockoptIPv6Mreq", Func, 0}, {"SetsockoptInet4Addr", Func, 0}, {"SetsockoptInt", Func, 0}, {"SetsockoptLinger", Func, 0}, {"SetsockoptString", Func, 0}, {"SetsockoptTimeval", Func, 0}, {"Settimeofday", Func, 0}, {"Setuid", Func, 0}, {"Setxattr", Func, 1}, {"Shutdown", Func, 0}, {"SidTypeAlias", Const, 0}, {"SidTypeComputer", Const, 0}, {"SidTypeDeletedAccount", Const, 0}, {"SidTypeDomain", Const, 0}, {"SidTypeGroup", Const, 0}, {"SidTypeInvalid", Const, 0}, {"SidTypeLabel", Const, 0}, {"SidTypeUnknown", Const, 0}, {"SidTypeUser", Const, 0}, {"SidTypeWellKnownGroup", Const, 0}, {"Signal", Type, 0}, {"SizeofBpfHdr", Const, 0}, {"SizeofBpfInsn", Const, 0}, {"SizeofBpfProgram", Const, 0}, {"SizeofBpfStat", Const, 0}, {"SizeofBpfVersion", Const, 0}, {"SizeofBpfZbuf", Const, 0}, {"SizeofBpfZbufHeader", Const, 0}, {"SizeofCmsghdr", Const, 0}, {"SizeofICMPv6Filter", Const, 2}, {"SizeofIPMreq", Const, 0}, {"SizeofIPMreqn", Const, 0}, {"SizeofIPv6MTUInfo", Const, 2}, {"SizeofIPv6Mreq", Const, 0}, {"SizeofIfAddrmsg", Const, 0}, {"SizeofIfAnnounceMsghdr", Const, 1}, {"SizeofIfData", Const, 0}, {"SizeofIfInfomsg", Const, 0}, {"SizeofIfMsghdr", Const, 0}, {"SizeofIfaMsghdr", Const, 0}, {"SizeofIfmaMsghdr", Const, 0}, {"SizeofIfmaMsghdr2", Const, 0}, {"SizeofInet4Pktinfo", Const, 0}, {"SizeofInet6Pktinfo", Const, 0}, {"SizeofInotifyEvent", Const, 0}, {"SizeofLinger", Const, 0}, {"SizeofMsghdr", Const, 0}, {"SizeofNlAttr", Const, 0}, {"SizeofNlMsgerr", Const, 0}, {"SizeofNlMsghdr", Const, 0}, {"SizeofRtAttr", Const, 0}, {"SizeofRtGenmsg", Const, 0}, {"SizeofRtMetrics", Const, 0}, {"SizeofRtMsg", Const, 0}, {"SizeofRtMsghdr", Const, 0}, {"SizeofRtNexthop", Const, 0}, {"SizeofSockFilter", Const, 0}, {"SizeofSockFprog", Const, 0}, {"SizeofSockaddrAny", Const, 0}, {"SizeofSockaddrDatalink", Const, 0}, {"SizeofSockaddrInet4", Const, 0}, {"SizeofSockaddrInet6", Const, 0}, {"SizeofSockaddrLinklayer", Const, 0}, {"SizeofSockaddrNetlink", Const, 0}, {"SizeofSockaddrUnix", Const, 0}, {"SizeofTCPInfo", Const, 1}, {"SizeofUcred", Const, 0}, {"SlicePtrFromStrings", Func, 1}, {"SockFilter", Type, 0}, {"SockFilter.Code", Field, 0}, {"SockFilter.Jf", Field, 0}, {"SockFilter.Jt", Field, 0}, {"SockFilter.K", Field, 0}, {"SockFprog", Type, 0}, {"SockFprog.Filter", Field, 0}, {"SockFprog.Len", Field, 0}, {"SockFprog.Pad_cgo_0", Field, 0}, {"Sockaddr", Type, 0}, {"SockaddrDatalink", Type, 0}, {"SockaddrDatalink.Alen", Field, 0}, {"SockaddrDatalink.Data", Field, 0}, {"SockaddrDatalink.Family", Field, 0}, {"SockaddrDatalink.Index", Field, 0}, {"SockaddrDatalink.Len", Field, 0}, {"SockaddrDatalink.Nlen", Field, 0}, {"SockaddrDatalink.Slen", Field, 0}, {"SockaddrDatalink.Type", Field, 0}, {"SockaddrGen", Type, 0}, {"SockaddrInet4", Type, 0}, {"SockaddrInet4.Addr", Field, 0}, {"SockaddrInet4.Port", Field, 0}, {"SockaddrInet6", Type, 0}, {"SockaddrInet6.Addr", Field, 0}, {"SockaddrInet6.Port", Field, 0}, {"SockaddrInet6.ZoneId", Field, 0}, {"SockaddrLinklayer", Type, 0}, {"SockaddrLinklayer.Addr", Field, 0}, {"SockaddrLinklayer.Halen", Field, 0}, {"SockaddrLinklayer.Hatype", Field, 0}, {"SockaddrLinklayer.Ifindex", Field, 0}, {"SockaddrLinklayer.Pkttype", Field, 0}, {"SockaddrLinklayer.Protocol", Field, 0}, {"SockaddrNetlink", Type, 0}, {"SockaddrNetlink.Family", Field, 0}, {"SockaddrNetlink.Groups", Field, 0}, {"SockaddrNetlink.Pad", Field, 0}, {"SockaddrNetlink.Pid", Field, 0}, {"SockaddrUnix", Type, 0}, {"SockaddrUnix.Name", Field, 0}, {"Socket", Func, 0}, {"SocketControlMessage", Type, 0}, {"SocketControlMessage.Data", Field, 0}, {"SocketControlMessage.Header", Field, 0}, {"SocketDisableIPv6", Var, 0}, {"Socketpair", Func, 0}, {"Splice", Func, 0}, {"StartProcess", Func, 0}, {"StartupInfo", Type, 0}, {"StartupInfo.Cb", Field, 0}, {"StartupInfo.Desktop", Field, 0}, {"StartupInfo.FillAttribute", Field, 0}, {"StartupInfo.Flags", Field, 0}, {"StartupInfo.ShowWindow", Field, 0}, {"StartupInfo.StdErr", Field, 0}, {"StartupInfo.StdInput", Field, 0}, {"StartupInfo.StdOutput", Field, 0}, {"StartupInfo.Title", Field, 0}, {"StartupInfo.X", Field, 0}, {"StartupInfo.XCountChars", Field, 0}, {"StartupInfo.XSize", Field, 0}, {"StartupInfo.Y", Field, 0}, {"StartupInfo.YCountChars", Field, 0}, {"StartupInfo.YSize", Field, 0}, {"Stat", Func, 0}, {"Stat_t", Type, 0}, {"Stat_t.Atim", Field, 0}, {"Stat_t.Atim_ext", Field, 12}, {"Stat_t.Atimespec", Field, 0}, {"Stat_t.Birthtimespec", Field, 0}, {"Stat_t.Blksize", Field, 0}, {"Stat_t.Blocks", Field, 0}, {"Stat_t.Btim_ext", Field, 12}, {"Stat_t.Ctim", Field, 0}, {"Stat_t.Ctim_ext", Field, 12}, {"Stat_t.Ctimespec", Field, 0}, {"Stat_t.Dev", Field, 0}, {"Stat_t.Flags", Field, 0}, {"Stat_t.Gen", Field, 0}, {"Stat_t.Gid", Field, 0}, {"Stat_t.Ino", Field, 0}, {"Stat_t.Lspare", Field, 0}, {"Stat_t.Lspare0", Field, 2}, {"Stat_t.Lspare1", Field, 2}, {"Stat_t.Mode", Field, 0}, {"Stat_t.Mtim", Field, 0}, {"Stat_t.Mtim_ext", Field, 12}, {"Stat_t.Mtimespec", Field, 0}, {"Stat_t.Nlink", Field, 0}, {"Stat_t.Pad_cgo_0", Field, 0}, {"Stat_t.Pad_cgo_1", Field, 0}, {"Stat_t.Pad_cgo_2", Field, 0}, {"Stat_t.Padding0", Field, 12}, {"Stat_t.Padding1", Field, 12}, {"Stat_t.Qspare", Field, 0}, {"Stat_t.Rdev", Field, 0}, {"Stat_t.Size", Field, 0}, {"Stat_t.Spare", Field, 2}, {"Stat_t.Uid", Field, 0}, {"Stat_t.X__pad0", Field, 0}, {"Stat_t.X__pad1", Field, 0}, {"Stat_t.X__pad2", Field, 0}, {"Stat_t.X__st_birthtim", Field, 2}, {"Stat_t.X__st_ino", Field, 0}, {"Stat_t.X__unused", Field, 0}, {"Statfs", Func, 0}, {"Statfs_t", Type, 0}, {"Statfs_t.Asyncreads", Field, 0}, {"Statfs_t.Asyncwrites", Field, 0}, {"Statfs_t.Bavail", Field, 0}, {"Statfs_t.Bfree", Field, 0}, {"Statfs_t.Blocks", Field, 0}, {"Statfs_t.Bsize", Field, 0}, {"Statfs_t.Charspare", Field, 0}, {"Statfs_t.F_asyncreads", Field, 2}, {"Statfs_t.F_asyncwrites", Field, 2}, {"Statfs_t.F_bavail", Field, 2}, {"Statfs_t.F_bfree", Field, 2}, {"Statfs_t.F_blocks", Field, 2}, {"Statfs_t.F_bsize", Field, 2}, {"Statfs_t.F_ctime", Field, 2}, {"Statfs_t.F_favail", Field, 2}, {"Statfs_t.F_ffree", Field, 2}, {"Statfs_t.F_files", Field, 2}, {"Statfs_t.F_flags", Field, 2}, {"Statfs_t.F_fsid", Field, 2}, {"Statfs_t.F_fstypename", Field, 2}, {"Statfs_t.F_iosize", Field, 2}, {"Statfs_t.F_mntfromname", Field, 2}, {"Statfs_t.F_mntfromspec", Field, 3}, {"Statfs_t.F_mntonname", Field, 2}, {"Statfs_t.F_namemax", Field, 2}, {"Statfs_t.F_owner", Field, 2}, {"Statfs_t.F_spare", Field, 2}, {"Statfs_t.F_syncreads", Field, 2}, {"Statfs_t.F_syncwrites", Field, 2}, {"Statfs_t.Ffree", Field, 0}, {"Statfs_t.Files", Field, 0}, {"Statfs_t.Flags", Field, 0}, {"Statfs_t.Frsize", Field, 0}, {"Statfs_t.Fsid", Field, 0}, {"Statfs_t.Fssubtype", Field, 0}, {"Statfs_t.Fstypename", Field, 0}, {"Statfs_t.Iosize", Field, 0}, {"Statfs_t.Mntfromname", Field, 0}, {"Statfs_t.Mntonname", Field, 0}, {"Statfs_t.Mount_info", Field, 2}, {"Statfs_t.Namelen", Field, 0}, {"Statfs_t.Namemax", Field, 0}, {"Statfs_t.Owner", Field, 0}, {"Statfs_t.Pad_cgo_0", Field, 0}, {"Statfs_t.Pad_cgo_1", Field, 2}, {"Statfs_t.Reserved", Field, 0}, {"Statfs_t.Spare", Field, 0}, {"Statfs_t.Syncreads", Field, 0}, {"Statfs_t.Syncwrites", Field, 0}, {"Statfs_t.Type", Field, 0}, {"Statfs_t.Version", Field, 0}, {"Stderr", Var, 0}, {"Stdin", Var, 0}, {"Stdout", Var, 0}, {"StringBytePtr", Func, 0}, {"StringByteSlice", Func, 0}, {"StringSlicePtr", Func, 0}, {"StringToSid", Func, 0}, {"StringToUTF16", Func, 0}, {"StringToUTF16Ptr", Func, 0}, {"Symlink", Func, 0}, {"Sync", Func, 0}, {"SyncFileRange", Func, 0}, {"SysProcAttr", Type, 0}, {"SysProcAttr.AdditionalInheritedHandles", Field, 17}, {"SysProcAttr.AmbientCaps", Field, 9}, {"SysProcAttr.CgroupFD", Field, 20}, {"SysProcAttr.Chroot", Field, 0}, {"SysProcAttr.Cloneflags", Field, 2}, {"SysProcAttr.CmdLine", Field, 0}, {"SysProcAttr.CreationFlags", Field, 1}, {"SysProcAttr.Credential", Field, 0}, {"SysProcAttr.Ctty", Field, 1}, {"SysProcAttr.Foreground", Field, 5}, {"SysProcAttr.GidMappings", Field, 4}, {"SysProcAttr.GidMappingsEnableSetgroups", Field, 5}, {"SysProcAttr.HideWindow", Field, 0}, {"SysProcAttr.Jail", Field, 21}, {"SysProcAttr.NoInheritHandles", Field, 16}, {"SysProcAttr.Noctty", Field, 0}, {"SysProcAttr.ParentProcess", Field, 17}, {"SysProcAttr.Pdeathsig", Field, 0}, {"SysProcAttr.Pgid", Field, 5}, {"SysProcAttr.PidFD", Field, 22}, {"SysProcAttr.ProcessAttributes", Field, 13}, {"SysProcAttr.Ptrace", Field, 0}, {"SysProcAttr.Setctty", Field, 0}, {"SysProcAttr.Setpgid", Field, 0}, {"SysProcAttr.Setsid", Field, 0}, {"SysProcAttr.ThreadAttributes", Field, 13}, {"SysProcAttr.Token", Field, 10}, {"SysProcAttr.UidMappings", Field, 4}, {"SysProcAttr.Unshareflags", Field, 7}, {"SysProcAttr.UseCgroupFD", Field, 20}, {"SysProcIDMap", Type, 4}, {"SysProcIDMap.ContainerID", Field, 4}, {"SysProcIDMap.HostID", Field, 4}, {"SysProcIDMap.Size", Field, 4}, {"Syscall", Func, 0}, {"Syscall12", Func, 0}, {"Syscall15", Func, 0}, {"Syscall18", Func, 12}, {"Syscall6", Func, 0}, {"Syscall9", Func, 0}, {"SyscallN", Func, 18}, {"Sysctl", Func, 0}, {"SysctlUint32", Func, 0}, {"Sysctlnode", Type, 2}, {"Sysctlnode.Flags", Field, 2}, {"Sysctlnode.Name", Field, 2}, {"Sysctlnode.Num", Field, 2}, {"Sysctlnode.Un", Field, 2}, {"Sysctlnode.Ver", Field, 2}, {"Sysctlnode.X__rsvd", Field, 2}, {"Sysctlnode.X_sysctl_desc", Field, 2}, {"Sysctlnode.X_sysctl_func", Field, 2}, {"Sysctlnode.X_sysctl_parent", Field, 2}, {"Sysctlnode.X_sysctl_size", Field, 2}, {"Sysinfo", Func, 0}, {"Sysinfo_t", Type, 0}, {"Sysinfo_t.Bufferram", Field, 0}, {"Sysinfo_t.Freehigh", Field, 0}, {"Sysinfo_t.Freeram", Field, 0}, {"Sysinfo_t.Freeswap", Field, 0}, {"Sysinfo_t.Loads", Field, 0}, {"Sysinfo_t.Pad", Field, 0}, {"Sysinfo_t.Pad_cgo_0", Field, 0}, {"Sysinfo_t.Pad_cgo_1", Field, 0}, {"Sysinfo_t.Procs", Field, 0}, {"Sysinfo_t.Sharedram", Field, 0}, {"Sysinfo_t.Totalhigh", Field, 0}, {"Sysinfo_t.Totalram", Field, 0}, {"Sysinfo_t.Totalswap", Field, 0}, {"Sysinfo_t.Unit", Field, 0}, {"Sysinfo_t.Uptime", Field, 0}, {"Sysinfo_t.X_f", Field, 0}, {"Systemtime", Type, 0}, {"Systemtime.Day", Field, 0}, {"Systemtime.DayOfWeek", Field, 0}, {"Systemtime.Hour", Field, 0}, {"Systemtime.Milliseconds", Field, 0}, {"Systemtime.Minute", Field, 0}, {"Systemtime.Month", Field, 0}, {"Systemtime.Second", Field, 0}, {"Systemtime.Year", Field, 0}, {"TCGETS", Const, 0}, {"TCIFLUSH", Const, 1}, {"TCIOFLUSH", Const, 1}, {"TCOFLUSH", Const, 1}, {"TCPInfo", Type, 1}, {"TCPInfo.Advmss", Field, 1}, {"TCPInfo.Ato", Field, 1}, {"TCPInfo.Backoff", Field, 1}, {"TCPInfo.Ca_state", Field, 1}, {"TCPInfo.Fackets", Field, 1}, {"TCPInfo.Last_ack_recv", Field, 1}, {"TCPInfo.Last_ack_sent", Field, 1}, {"TCPInfo.Last_data_recv", Field, 1}, {"TCPInfo.Last_data_sent", Field, 1}, {"TCPInfo.Lost", Field, 1}, {"TCPInfo.Options", Field, 1}, {"TCPInfo.Pad_cgo_0", Field, 1}, {"TCPInfo.Pmtu", Field, 1}, {"TCPInfo.Probes", Field, 1}, {"TCPInfo.Rcv_mss", Field, 1}, {"TCPInfo.Rcv_rtt", Field, 1}, {"TCPInfo.Rcv_space", Field, 1}, {"TCPInfo.Rcv_ssthresh", Field, 1}, {"TCPInfo.Reordering", Field, 1}, {"TCPInfo.Retrans", Field, 1}, {"TCPInfo.Retransmits", Field, 1}, {"TCPInfo.Rto", Field, 1}, {"TCPInfo.Rtt", Field, 1}, {"TCPInfo.Rttvar", Field, 1}, {"TCPInfo.Sacked", Field, 1}, {"TCPInfo.Snd_cwnd", Field, 1}, {"TCPInfo.Snd_mss", Field, 1}, {"TCPInfo.Snd_ssthresh", Field, 1}, {"TCPInfo.State", Field, 1}, {"TCPInfo.Total_retrans", Field, 1}, {"TCPInfo.Unacked", Field, 1}, {"TCPKeepalive", Type, 3}, {"TCPKeepalive.Interval", Field, 3}, {"TCPKeepalive.OnOff", Field, 3}, {"TCPKeepalive.Time", Field, 3}, {"TCP_CA_NAME_MAX", Const, 0}, {"TCP_CONGCTL", Const, 1}, {"TCP_CONGESTION", Const, 0}, {"TCP_CONNECTIONTIMEOUT", Const, 0}, {"TCP_CORK", Const, 0}, {"TCP_DEFER_ACCEPT", Const, 0}, {"TCP_ENABLE_ECN", Const, 16}, {"TCP_INFO", Const, 0}, {"TCP_KEEPALIVE", Const, 0}, {"TCP_KEEPCNT", Const, 0}, {"TCP_KEEPIDLE", Const, 0}, {"TCP_KEEPINIT", Const, 1}, {"TCP_KEEPINTVL", Const, 0}, {"TCP_LINGER2", Const, 0}, {"TCP_MAXBURST", Const, 0}, {"TCP_MAXHLEN", Const, 0}, {"TCP_MAXOLEN", Const, 0}, {"TCP_MAXSEG", Const, 0}, {"TCP_MAXWIN", Const, 0}, {"TCP_MAX_SACK", Const, 0}, {"TCP_MAX_WINSHIFT", Const, 0}, {"TCP_MD5SIG", Const, 0}, {"TCP_MD5SIG_MAXKEYLEN", Const, 0}, {"TCP_MINMSS", Const, 0}, {"TCP_MINMSSOVERLOAD", Const, 0}, {"TCP_MSS", Const, 0}, {"TCP_NODELAY", Const, 0}, {"TCP_NOOPT", Const, 0}, {"TCP_NOPUSH", Const, 0}, {"TCP_NOTSENT_LOWAT", Const, 16}, {"TCP_NSTATES", Const, 1}, {"TCP_QUICKACK", Const, 0}, {"TCP_RXT_CONNDROPTIME", Const, 0}, {"TCP_RXT_FINDROP", Const, 0}, {"TCP_SACK_ENABLE", Const, 1}, {"TCP_SENDMOREACKS", Const, 16}, {"TCP_SYNCNT", Const, 0}, {"TCP_VENDOR", Const, 3}, {"TCP_WINDOW_CLAMP", Const, 0}, {"TCSAFLUSH", Const, 1}, {"TCSETS", Const, 0}, {"TF_DISCONNECT", Const, 0}, {"TF_REUSE_SOCKET", Const, 0}, {"TF_USE_DEFAULT_WORKER", Const, 0}, {"TF_USE_KERNEL_APC", Const, 0}, {"TF_USE_SYSTEM_THREAD", Const, 0}, {"TF_WRITE_BEHIND", Const, 0}, {"TH32CS_INHERIT", Const, 4}, {"TH32CS_SNAPALL", Const, 4}, {"TH32CS_SNAPHEAPLIST", Const, 4}, {"TH32CS_SNAPMODULE", Const, 4}, {"TH32CS_SNAPMODULE32", Const, 4}, {"TH32CS_SNAPPROCESS", Const, 4}, {"TH32CS_SNAPTHREAD", Const, 4}, {"TIME_ZONE_ID_DAYLIGHT", Const, 0}, {"TIME_ZONE_ID_STANDARD", Const, 0}, {"TIME_ZONE_ID_UNKNOWN", Const, 0}, {"TIOCCBRK", Const, 0}, {"TIOCCDTR", Const, 0}, {"TIOCCONS", Const, 0}, {"TIOCDCDTIMESTAMP", Const, 0}, {"TIOCDRAIN", Const, 0}, {"TIOCDSIMICROCODE", Const, 0}, {"TIOCEXCL", Const, 0}, {"TIOCEXT", Const, 0}, {"TIOCFLAG_CDTRCTS", Const, 1}, {"TIOCFLAG_CLOCAL", Const, 1}, {"TIOCFLAG_CRTSCTS", Const, 1}, {"TIOCFLAG_MDMBUF", Const, 1}, {"TIOCFLAG_PPS", Const, 1}, {"TIOCFLAG_SOFTCAR", Const, 1}, {"TIOCFLUSH", Const, 0}, {"TIOCGDEV", Const, 0}, {"TIOCGDRAINWAIT", Const, 0}, {"TIOCGETA", Const, 0}, {"TIOCGETD", Const, 0}, {"TIOCGFLAGS", Const, 1}, {"TIOCGICOUNT", Const, 0}, {"TIOCGLCKTRMIOS", Const, 0}, {"TIOCGLINED", Const, 1}, {"TIOCGPGRP", Const, 0}, {"TIOCGPTN", Const, 0}, {"TIOCGQSIZE", Const, 1}, {"TIOCGRANTPT", Const, 1}, {"TIOCGRS485", Const, 0}, {"TIOCGSERIAL", Const, 0}, {"TIOCGSID", Const, 0}, {"TIOCGSIZE", Const, 1}, {"TIOCGSOFTCAR", Const, 0}, {"TIOCGTSTAMP", Const, 1}, {"TIOCGWINSZ", Const, 0}, {"TIOCINQ", Const, 0}, {"TIOCIXOFF", Const, 0}, {"TIOCIXON", Const, 0}, {"TIOCLINUX", Const, 0}, {"TIOCMBIC", Const, 0}, {"TIOCMBIS", Const, 0}, {"TIOCMGDTRWAIT", Const, 0}, {"TIOCMGET", Const, 0}, {"TIOCMIWAIT", Const, 0}, {"TIOCMODG", Const, 0}, {"TIOCMODS", Const, 0}, {"TIOCMSDTRWAIT", Const, 0}, {"TIOCMSET", Const, 0}, {"TIOCM_CAR", Const, 0}, {"TIOCM_CD", Const, 0}, {"TIOCM_CTS", Const, 0}, {"TIOCM_DCD", Const, 0}, {"TIOCM_DSR", Const, 0}, {"TIOCM_DTR", Const, 0}, {"TIOCM_LE", Const, 0}, {"TIOCM_RI", Const, 0}, {"TIOCM_RNG", Const, 0}, {"TIOCM_RTS", Const, 0}, {"TIOCM_SR", Const, 0}, {"TIOCM_ST", Const, 0}, {"TIOCNOTTY", Const, 0}, {"TIOCNXCL", Const, 0}, {"TIOCOUTQ", Const, 0}, {"TIOCPKT", Const, 0}, {"TIOCPKT_DATA", Const, 0}, {"TIOCPKT_DOSTOP", Const, 0}, {"TIOCPKT_FLUSHREAD", Const, 0}, {"TIOCPKT_FLUSHWRITE", Const, 0}, {"TIOCPKT_IOCTL", Const, 0}, {"TIOCPKT_NOSTOP", Const, 0}, {"TIOCPKT_START", Const, 0}, {"TIOCPKT_STOP", Const, 0}, {"TIOCPTMASTER", Const, 0}, {"TIOCPTMGET", Const, 1}, {"TIOCPTSNAME", Const, 1}, {"TIOCPTYGNAME", Const, 0}, {"TIOCPTYGRANT", Const, 0}, {"TIOCPTYUNLK", Const, 0}, {"TIOCRCVFRAME", Const, 1}, {"TIOCREMOTE", Const, 0}, {"TIOCSBRK", Const, 0}, {"TIOCSCONS", Const, 0}, {"TIOCSCTTY", Const, 0}, {"TIOCSDRAINWAIT", Const, 0}, {"TIOCSDTR", Const, 0}, {"TIOCSERCONFIG", Const, 0}, {"TIOCSERGETLSR", Const, 0}, {"TIOCSERGETMULTI", Const, 0}, {"TIOCSERGSTRUCT", Const, 0}, {"TIOCSERGWILD", Const, 0}, {"TIOCSERSETMULTI", Const, 0}, {"TIOCSERSWILD", Const, 0}, {"TIOCSER_TEMT", Const, 0}, {"TIOCSETA", Const, 0}, {"TIOCSETAF", Const, 0}, {"TIOCSETAW", Const, 0}, {"TIOCSETD", Const, 0}, {"TIOCSFLAGS", Const, 1}, {"TIOCSIG", Const, 0}, {"TIOCSLCKTRMIOS", Const, 0}, {"TIOCSLINED", Const, 1}, {"TIOCSPGRP", Const, 0}, {"TIOCSPTLCK", Const, 0}, {"TIOCSQSIZE", Const, 1}, {"TIOCSRS485", Const, 0}, {"TIOCSSERIAL", Const, 0}, {"TIOCSSIZE", Const, 1}, {"TIOCSSOFTCAR", Const, 0}, {"TIOCSTART", Const, 0}, {"TIOCSTAT", Const, 0}, {"TIOCSTI", Const, 0}, {"TIOCSTOP", Const, 0}, {"TIOCSTSTAMP", Const, 1}, {"TIOCSWINSZ", Const, 0}, {"TIOCTIMESTAMP", Const, 0}, {"TIOCUCNTL", Const, 0}, {"TIOCVHANGUP", Const, 0}, {"TIOCXMTFRAME", Const, 1}, {"TOKEN_ADJUST_DEFAULT", Const, 0}, {"TOKEN_ADJUST_GROUPS", Const, 0}, {"TOKEN_ADJUST_PRIVILEGES", Const, 0}, {"TOKEN_ADJUST_SESSIONID", Const, 11}, {"TOKEN_ALL_ACCESS", Const, 0}, {"TOKEN_ASSIGN_PRIMARY", Const, 0}, {"TOKEN_DUPLICATE", Const, 0}, {"TOKEN_EXECUTE", Const, 0}, {"TOKEN_IMPERSONATE", Const, 0}, {"TOKEN_QUERY", Const, 0}, {"TOKEN_QUERY_SOURCE", Const, 0}, {"TOKEN_READ", Const, 0}, {"TOKEN_WRITE", Const, 0}, {"TOSTOP", Const, 0}, {"TRUNCATE_EXISTING", Const, 0}, {"TUNATTACHFILTER", Const, 0}, {"TUNDETACHFILTER", Const, 0}, {"TUNGETFEATURES", Const, 0}, {"TUNGETIFF", Const, 0}, {"TUNGETSNDBUF", Const, 0}, {"TUNGETVNETHDRSZ", Const, 0}, {"TUNSETDEBUG", Const, 0}, {"TUNSETGROUP", Const, 0}, {"TUNSETIFF", Const, 0}, {"TUNSETLINK", Const, 0}, {"TUNSETNOCSUM", Const, 0}, {"TUNSETOFFLOAD", Const, 0}, {"TUNSETOWNER", Const, 0}, {"TUNSETPERSIST", Const, 0}, {"TUNSETSNDBUF", Const, 0}, {"TUNSETTXFILTER", Const, 0}, {"TUNSETVNETHDRSZ", Const, 0}, {"Tee", Func, 0}, {"TerminateProcess", Func, 0}, {"Termios", Type, 0}, {"Termios.Cc", Field, 0}, {"Termios.Cflag", Field, 0}, {"Termios.Iflag", Field, 0}, {"Termios.Ispeed", Field, 0}, {"Termios.Lflag", Field, 0}, {"Termios.Line", Field, 0}, {"Termios.Oflag", Field, 0}, {"Termios.Ospeed", Field, 0}, {"Termios.Pad_cgo_0", Field, 0}, {"Tgkill", Func, 0}, {"Time", Func, 0}, {"Time_t", Type, 0}, {"Times", Func, 0}, {"Timespec", Type, 0}, {"Timespec.Nsec", Field, 0}, {"Timespec.Pad_cgo_0", Field, 2}, {"Timespec.Sec", Field, 0}, {"TimespecToNsec", Func, 0}, {"Timeval", Type, 0}, {"Timeval.Pad_cgo_0", Field, 0}, {"Timeval.Sec", Field, 0}, {"Timeval.Usec", Field, 0}, {"Timeval32", Type, 0}, {"Timeval32.Sec", Field, 0}, {"Timeval32.Usec", Field, 0}, {"TimevalToNsec", Func, 0}, {"Timex", Type, 0}, {"Timex.Calcnt", Field, 0}, {"Timex.Constant", Field, 0}, {"Timex.Errcnt", Field, 0}, {"Timex.Esterror", Field, 0}, {"Timex.Freq", Field, 0}, {"Timex.Jitcnt", Field, 0}, {"Timex.Jitter", Field, 0}, {"Timex.Maxerror", Field, 0}, {"Timex.Modes", Field, 0}, {"Timex.Offset", Field, 0}, {"Timex.Pad_cgo_0", Field, 0}, {"Timex.Pad_cgo_1", Field, 0}, {"Timex.Pad_cgo_2", Field, 0}, {"Timex.Pad_cgo_3", Field, 0}, {"Timex.Ppsfreq", Field, 0}, {"Timex.Precision", Field, 0}, {"Timex.Shift", Field, 0}, {"Timex.Stabil", Field, 0}, {"Timex.Status", Field, 0}, {"Timex.Stbcnt", Field, 0}, {"Timex.Tai", Field, 0}, {"Timex.Tick", Field, 0}, {"Timex.Time", Field, 0}, {"Timex.Tolerance", Field, 0}, {"Timezoneinformation", Type, 0}, {"Timezoneinformation.Bias", Field, 0}, {"Timezoneinformation.DaylightBias", Field, 0}, {"Timezoneinformation.DaylightDate", Field, 0}, {"Timezoneinformation.DaylightName", Field, 0}, {"Timezoneinformation.StandardBias", Field, 0}, {"Timezoneinformation.StandardDate", Field, 0}, {"Timezoneinformation.StandardName", Field, 0}, {"Tms", Type, 0}, {"Tms.Cstime", Field, 0}, {"Tms.Cutime", Field, 0}, {"Tms.Stime", Field, 0}, {"Tms.Utime", Field, 0}, {"Token", Type, 0}, {"TokenAccessInformation", Const, 0}, {"TokenAuditPolicy", Const, 0}, {"TokenDefaultDacl", Const, 0}, {"TokenElevation", Const, 0}, {"TokenElevationType", Const, 0}, {"TokenGroups", Const, 0}, {"TokenGroupsAndPrivileges", Const, 0}, {"TokenHasRestrictions", Const, 0}, {"TokenImpersonationLevel", Const, 0}, {"TokenIntegrityLevel", Const, 0}, {"TokenLinkedToken", Const, 0}, {"TokenLogonSid", Const, 0}, {"TokenMandatoryPolicy", Const, 0}, {"TokenOrigin", Const, 0}, {"TokenOwner", Const, 0}, {"TokenPrimaryGroup", Const, 0}, {"TokenPrivileges", Const, 0}, {"TokenRestrictedSids", Const, 0}, {"TokenSandBoxInert", Const, 0}, {"TokenSessionId", Const, 0}, {"TokenSessionReference", Const, 0}, {"TokenSource", Const, 0}, {"TokenStatistics", Const, 0}, {"TokenType", Const, 0}, {"TokenUIAccess", Const, 0}, {"TokenUser", Const, 0}, {"TokenVirtualizationAllowed", Const, 0}, {"TokenVirtualizationEnabled", Const, 0}, {"Tokenprimarygroup", Type, 0}, {"Tokenprimarygroup.PrimaryGroup", Field, 0}, {"Tokenuser", Type, 0}, {"Tokenuser.User", Field, 0}, {"TranslateAccountName", Func, 0}, {"TranslateName", Func, 0}, {"TransmitFile", Func, 0}, {"TransmitFileBuffers", Type, 0}, {"TransmitFileBuffers.Head", Field, 0}, {"TransmitFileBuffers.HeadLength", Field, 0}, {"TransmitFileBuffers.Tail", Field, 0}, {"TransmitFileBuffers.TailLength", Field, 0}, {"Truncate", Func, 0}, {"UNIX_PATH_MAX", Const, 12}, {"USAGE_MATCH_TYPE_AND", Const, 0}, {"USAGE_MATCH_TYPE_OR", Const, 0}, {"UTF16FromString", Func, 1}, {"UTF16PtrFromString", Func, 1}, {"UTF16ToString", Func, 0}, {"Ucred", Type, 0}, {"Ucred.Gid", Field, 0}, {"Ucred.Pid", Field, 0}, {"Ucred.Uid", Field, 0}, {"Umask", Func, 0}, {"Uname", Func, 0}, {"Undelete", Func, 0}, {"UnixCredentials", Func, 0}, {"UnixRights", Func, 0}, {"Unlink", Func, 0}, {"Unlinkat", Func, 0}, {"UnmapViewOfFile", Func, 0}, {"Unmount", Func, 0}, {"Unsetenv", Func, 4}, {"Unshare", Func, 0}, {"UserInfo10", Type, 0}, {"UserInfo10.Comment", Field, 0}, {"UserInfo10.FullName", Field, 0}, {"UserInfo10.Name", Field, 0}, {"UserInfo10.UsrComment", Field, 0}, {"Ustat", Func, 0}, {"Ustat_t", Type, 0}, {"Ustat_t.Fname", Field, 0}, {"Ustat_t.Fpack", Field, 0}, {"Ustat_t.Pad_cgo_0", Field, 0}, {"Ustat_t.Pad_cgo_1", Field, 0}, {"Ustat_t.Tfree", Field, 0}, {"Ustat_t.Tinode", Field, 0}, {"Utimbuf", Type, 0}, {"Utimbuf.Actime", Field, 0}, {"Utimbuf.Modtime", Field, 0}, {"Utime", Func, 0}, {"Utimes", Func, 0}, {"UtimesNano", Func, 1}, {"Utsname", Type, 0}, {"Utsname.Domainname", Field, 0}, {"Utsname.Machine", Field, 0}, {"Utsname.Nodename", Field, 0}, {"Utsname.Release", Field, 0}, {"Utsname.Sysname", Field, 0}, {"Utsname.Version", Field, 0}, {"VDISCARD", Const, 0}, {"VDSUSP", Const, 1}, {"VEOF", Const, 0}, {"VEOL", Const, 0}, {"VEOL2", Const, 0}, {"VERASE", Const, 0}, {"VERASE2", Const, 1}, {"VINTR", Const, 0}, {"VKILL", Const, 0}, {"VLNEXT", Const, 0}, {"VMIN", Const, 0}, {"VQUIT", Const, 0}, {"VREPRINT", Const, 0}, {"VSTART", Const, 0}, {"VSTATUS", Const, 1}, {"VSTOP", Const, 0}, {"VSUSP", Const, 0}, {"VSWTC", Const, 0}, {"VT0", Const, 1}, {"VT1", Const, 1}, {"VTDLY", Const, 1}, {"VTIME", Const, 0}, {"VWERASE", Const, 0}, {"VirtualLock", Func, 0}, {"VirtualUnlock", Func, 0}, {"WAIT_ABANDONED", Const, 0}, {"WAIT_FAILED", Const, 0}, {"WAIT_OBJECT_0", Const, 0}, {"WAIT_TIMEOUT", Const, 0}, {"WALL", Const, 0}, {"WALLSIG", Const, 1}, {"WALTSIG", Const, 1}, {"WCLONE", Const, 0}, {"WCONTINUED", Const, 0}, {"WCOREFLAG", Const, 0}, {"WEXITED", Const, 0}, {"WLINUXCLONE", Const, 0}, {"WNOHANG", Const, 0}, {"WNOTHREAD", Const, 0}, {"WNOWAIT", Const, 0}, {"WNOZOMBIE", Const, 1}, {"WOPTSCHECKED", Const, 1}, {"WORDSIZE", Const, 0}, {"WSABuf", Type, 0}, {"WSABuf.Buf", Field, 0}, {"WSABuf.Len", Field, 0}, {"WSACleanup", Func, 0}, {"WSADESCRIPTION_LEN", Const, 0}, {"WSAData", Type, 0}, {"WSAData.Description", Field, 0}, {"WSAData.HighVersion", Field, 0}, {"WSAData.MaxSockets", Field, 0}, {"WSAData.MaxUdpDg", Field, 0}, {"WSAData.SystemStatus", Field, 0}, {"WSAData.VendorInfo", Field, 0}, {"WSAData.Version", Field, 0}, {"WSAEACCES", Const, 2}, {"WSAECONNABORTED", Const, 9}, {"WSAECONNRESET", Const, 3}, {"WSAENOPROTOOPT", Const, 23}, {"WSAEnumProtocols", Func, 2}, {"WSAID_CONNECTEX", Var, 1}, {"WSAIoctl", Func, 0}, {"WSAPROTOCOL_LEN", Const, 2}, {"WSAProtocolChain", Type, 2}, {"WSAProtocolChain.ChainEntries", Field, 2}, {"WSAProtocolChain.ChainLen", Field, 2}, {"WSAProtocolInfo", Type, 2}, {"WSAProtocolInfo.AddressFamily", Field, 2}, {"WSAProtocolInfo.CatalogEntryId", Field, 2}, {"WSAProtocolInfo.MaxSockAddr", Field, 2}, {"WSAProtocolInfo.MessageSize", Field, 2}, {"WSAProtocolInfo.MinSockAddr", Field, 2}, {"WSAProtocolInfo.NetworkByteOrder", Field, 2}, {"WSAProtocolInfo.Protocol", Field, 2}, {"WSAProtocolInfo.ProtocolChain", Field, 2}, {"WSAProtocolInfo.ProtocolMaxOffset", Field, 2}, {"WSAProtocolInfo.ProtocolName", Field, 2}, {"WSAProtocolInfo.ProviderFlags", Field, 2}, {"WSAProtocolInfo.ProviderId", Field, 2}, {"WSAProtocolInfo.ProviderReserved", Field, 2}, {"WSAProtocolInfo.SecurityScheme", Field, 2}, {"WSAProtocolInfo.ServiceFlags1", Field, 2}, {"WSAProtocolInfo.ServiceFlags2", Field, 2}, {"WSAProtocolInfo.ServiceFlags3", Field, 2}, {"WSAProtocolInfo.ServiceFlags4", Field, 2}, {"WSAProtocolInfo.SocketType", Field, 2}, {"WSAProtocolInfo.Version", Field, 2}, {"WSARecv", Func, 0}, {"WSARecvFrom", Func, 0}, {"WSASYS_STATUS_LEN", Const, 0}, {"WSASend", Func, 0}, {"WSASendTo", Func, 0}, {"WSASendto", Func, 0}, {"WSAStartup", Func, 0}, {"WSTOPPED", Const, 0}, {"WTRAPPED", Const, 1}, {"WUNTRACED", Const, 0}, {"Wait4", Func, 0}, {"WaitForSingleObject", Func, 0}, {"WaitStatus", Type, 0}, {"WaitStatus.ExitCode", Field, 0}, {"Win32FileAttributeData", Type, 0}, {"Win32FileAttributeData.CreationTime", Field, 0}, {"Win32FileAttributeData.FileAttributes", Field, 0}, {"Win32FileAttributeData.FileSizeHigh", Field, 0}, {"Win32FileAttributeData.FileSizeLow", Field, 0}, {"Win32FileAttributeData.LastAccessTime", Field, 0}, {"Win32FileAttributeData.LastWriteTime", Field, 0}, {"Win32finddata", Type, 0}, {"Win32finddata.AlternateFileName", Field, 0}, {"Win32finddata.CreationTime", Field, 0}, {"Win32finddata.FileAttributes", Field, 0}, {"Win32finddata.FileName", Field, 0}, {"Win32finddata.FileSizeHigh", Field, 0}, {"Win32finddata.FileSizeLow", Field, 0}, {"Win32finddata.LastAccessTime", Field, 0}, {"Win32finddata.LastWriteTime", Field, 0}, {"Win32finddata.Reserved0", Field, 0}, {"Win32finddata.Reserved1", Field, 0}, {"Write", Func, 0}, {"WriteConsole", Func, 1}, {"WriteFile", Func, 0}, {"X509_ASN_ENCODING", Const, 0}, {"XCASE", Const, 0}, {"XP1_CONNECTIONLESS", Const, 2}, {"XP1_CONNECT_DATA", Const, 2}, {"XP1_DISCONNECT_DATA", Const, 2}, {"XP1_EXPEDITED_DATA", Const, 2}, {"XP1_GRACEFUL_CLOSE", Const, 2}, {"XP1_GUARANTEED_DELIVERY", Const, 2}, {"XP1_GUARANTEED_ORDER", Const, 2}, {"XP1_IFS_HANDLES", Const, 2}, {"XP1_MESSAGE_ORIENTED", Const, 2}, {"XP1_MULTIPOINT_CONTROL_PLANE", Const, 2}, {"XP1_MULTIPOINT_DATA_PLANE", Const, 2}, {"XP1_PARTIAL_MESSAGE", Const, 2}, {"XP1_PSEUDO_STREAM", Const, 2}, {"XP1_QOS_SUPPORTED", Const, 2}, {"XP1_SAN_SUPPORT_SDP", Const, 2}, {"XP1_SUPPORT_BROADCAST", Const, 2}, {"XP1_SUPPORT_MULTIPOINT", Const, 2}, {"XP1_UNI_RECV", Const, 2}, {"XP1_UNI_SEND", Const, 2}, }, "syscall/js": { {"CopyBytesToGo", Func, 0}, {"CopyBytesToJS", Func, 0}, {"Error", Type, 0}, {"Func", Type, 0}, {"FuncOf", Func, 0}, {"Global", Func, 0}, {"Null", Func, 0}, {"Type", Type, 0}, {"TypeBoolean", Const, 0}, {"TypeFunction", Const, 0}, {"TypeNull", Const, 0}, {"TypeNumber", Const, 0}, {"TypeObject", Const, 0}, {"TypeString", Const, 0}, {"TypeSymbol", Const, 0}, {"TypeUndefined", Const, 0}, {"Undefined", Func, 0}, {"Value", Type, 0}, {"ValueError", Type, 0}, {"ValueOf", Func, 0}, }, "testing": { {"(*B).Chdir", Method, 24}, {"(*B).Cleanup", Method, 14}, {"(*B).Context", Method, 24}, {"(*B).Elapsed", Method, 20}, {"(*B).Error", Method, 0}, {"(*B).Errorf", Method, 0}, {"(*B).Fail", Method, 0}, {"(*B).FailNow", Method, 0}, {"(*B).Failed", Method, 0}, {"(*B).Fatal", Method, 0}, {"(*B).Fatalf", Method, 0}, {"(*B).Helper", Method, 9}, {"(*B).Log", Method, 0}, {"(*B).Logf", Method, 0}, {"(*B).Loop", Method, 24}, {"(*B).Name", Method, 8}, {"(*B).ReportAllocs", Method, 1}, {"(*B).ReportMetric", Method, 13}, {"(*B).ResetTimer", Method, 0}, {"(*B).Run", Method, 7}, {"(*B).RunParallel", Method, 3}, {"(*B).SetBytes", Method, 0}, {"(*B).SetParallelism", Method, 3}, {"(*B).Setenv", Method, 17}, {"(*B).Skip", Method, 1}, {"(*B).SkipNow", Method, 1}, {"(*B).Skipf", Method, 1}, {"(*B).Skipped", Method, 1}, {"(*B).StartTimer", Method, 0}, {"(*B).StopTimer", Method, 0}, {"(*B).TempDir", Method, 15}, {"(*F).Add", Method, 18}, {"(*F).Chdir", Method, 24}, {"(*F).Cleanup", Method, 18}, {"(*F).Context", Method, 24}, {"(*F).Error", Method, 18}, {"(*F).Errorf", Method, 18}, {"(*F).Fail", Method, 18}, {"(*F).FailNow", Method, 18}, {"(*F).Failed", Method, 18}, {"(*F).Fatal", Method, 18}, {"(*F).Fatalf", Method, 18}, {"(*F).Fuzz", Method, 18}, {"(*F).Helper", Method, 18}, {"(*F).Log", Method, 18}, {"(*F).Logf", Method, 18}, {"(*F).Name", Method, 18}, {"(*F).Setenv", Method, 18}, {"(*F).Skip", Method, 18}, {"(*F).SkipNow", Method, 18}, {"(*F).Skipf", Method, 18}, {"(*F).Skipped", Method, 18}, {"(*F).TempDir", Method, 18}, {"(*M).Run", Method, 4}, {"(*PB).Next", Method, 3}, {"(*T).Chdir", Method, 24}, {"(*T).Cleanup", Method, 14}, {"(*T).Context", Method, 24}, {"(*T).Deadline", Method, 15}, {"(*T).Error", Method, 0}, {"(*T).Errorf", Method, 0}, {"(*T).Fail", Method, 0}, {"(*T).FailNow", Method, 0}, {"(*T).Failed", Method, 0}, {"(*T).Fatal", Method, 0}, {"(*T).Fatalf", Method, 0}, {"(*T).Helper", Method, 9}, {"(*T).Log", Method, 0}, {"(*T).Logf", Method, 0}, {"(*T).Name", Method, 8}, {"(*T).Parallel", Method, 0}, {"(*T).Run", Method, 7}, {"(*T).Setenv", Method, 17}, {"(*T).Skip", Method, 1}, {"(*T).SkipNow", Method, 1}, {"(*T).Skipf", Method, 1}, {"(*T).Skipped", Method, 1}, {"(*T).TempDir", Method, 15}, {"(BenchmarkResult).AllocedBytesPerOp", Method, 1}, {"(BenchmarkResult).AllocsPerOp", Method, 1}, {"(BenchmarkResult).MemString", Method, 1}, {"(BenchmarkResult).NsPerOp", Method, 0}, {"(BenchmarkResult).String", Method, 0}, {"AllocsPerRun", Func, 1}, {"B", Type, 0}, {"B.N", Field, 0}, {"Benchmark", Func, 0}, {"BenchmarkResult", Type, 0}, {"BenchmarkResult.Bytes", Field, 0}, {"BenchmarkResult.Extra", Field, 13}, {"BenchmarkResult.MemAllocs", Field, 1}, {"BenchmarkResult.MemBytes", Field, 1}, {"BenchmarkResult.N", Field, 0}, {"BenchmarkResult.T", Field, 0}, {"Cover", Type, 2}, {"Cover.Blocks", Field, 2}, {"Cover.Counters", Field, 2}, {"Cover.CoveredPackages", Field, 2}, {"Cover.Mode", Field, 2}, {"CoverBlock", Type, 2}, {"CoverBlock.Col0", Field, 2}, {"CoverBlock.Col1", Field, 2}, {"CoverBlock.Line0", Field, 2}, {"CoverBlock.Line1", Field, 2}, {"CoverBlock.Stmts", Field, 2}, {"CoverMode", Func, 8}, {"Coverage", Func, 4}, {"F", Type, 18}, {"Init", Func, 13}, {"InternalBenchmark", Type, 0}, {"InternalBenchmark.F", Field, 0}, {"InternalBenchmark.Name", Field, 0}, {"InternalExample", Type, 0}, {"InternalExample.F", Field, 0}, {"InternalExample.Name", Field, 0}, {"InternalExample.Output", Field, 0}, {"InternalExample.Unordered", Field, 7}, {"InternalFuzzTarget", Type, 18}, {"InternalFuzzTarget.Fn", Field, 18}, {"InternalFuzzTarget.Name", Field, 18}, {"InternalTest", Type, 0}, {"InternalTest.F", Field, 0}, {"InternalTest.Name", Field, 0}, {"M", Type, 4}, {"Main", Func, 0}, {"MainStart", Func, 4}, {"PB", Type, 3}, {"RegisterCover", Func, 2}, {"RunBenchmarks", Func, 0}, {"RunExamples", Func, 0}, {"RunTests", Func, 0}, {"Short", Func, 0}, {"T", Type, 0}, {"TB", Type, 2}, {"Testing", Func, 21}, {"Verbose", Func, 1}, }, "testing/fstest": { {"(MapFS).Glob", Method, 16}, {"(MapFS).Lstat", Method, 25}, {"(MapFS).Open", Method, 16}, {"(MapFS).ReadDir", Method, 16}, {"(MapFS).ReadFile", Method, 16}, {"(MapFS).ReadLink", Method, 25}, {"(MapFS).Stat", Method, 16}, {"(MapFS).Sub", Method, 16}, {"MapFS", Type, 16}, {"MapFile", Type, 16}, {"MapFile.Data", Field, 16}, {"MapFile.ModTime", Field, 16}, {"MapFile.Mode", Field, 16}, {"MapFile.Sys", Field, 16}, {"TestFS", Func, 16}, }, "testing/iotest": { {"DataErrReader", Func, 0}, {"ErrReader", Func, 16}, {"ErrTimeout", Var, 0}, {"HalfReader", Func, 0}, {"NewReadLogger", Func, 0}, {"NewWriteLogger", Func, 0}, {"OneByteReader", Func, 0}, {"TestReader", Func, 16}, {"TimeoutReader", Func, 0}, {"TruncateWriter", Func, 0}, }, "testing/quick": { {"(*CheckEqualError).Error", Method, 0}, {"(*CheckError).Error", Method, 0}, {"(SetupError).Error", Method, 0}, {"Check", Func, 0}, {"CheckEqual", Func, 0}, {"CheckEqualError", Type, 0}, {"CheckEqualError.CheckError", Field, 0}, {"CheckEqualError.Out1", Field, 0}, {"CheckEqualError.Out2", Field, 0}, {"CheckError", Type, 0}, {"CheckError.Count", Field, 0}, {"CheckError.In", Field, 0}, {"Config", Type, 0}, {"Config.MaxCount", Field, 0}, {"Config.MaxCountScale", Field, 0}, {"Config.Rand", Field, 0}, {"Config.Values", Field, 0}, {"Generator", Type, 0}, {"SetupError", Type, 0}, {"Value", Func, 0}, }, "testing/slogtest": { {"Run", Func, 22}, {"TestHandler", Func, 21}, }, "text/scanner": { {"(*Position).IsValid", Method, 0}, {"(*Scanner).Init", Method, 0}, {"(*Scanner).IsValid", Method, 0}, {"(*Scanner).Next", Method, 0}, {"(*Scanner).Peek", Method, 0}, {"(*Scanner).Pos", Method, 0}, {"(*Scanner).Scan", Method, 0}, {"(*Scanner).TokenText", Method, 0}, {"(Position).String", Method, 0}, {"(Scanner).String", Method, 0}, {"Char", Const, 0}, {"Comment", Const, 0}, {"EOF", Const, 0}, {"Float", Const, 0}, {"GoTokens", Const, 0}, {"GoWhitespace", Const, 0}, {"Ident", Const, 0}, {"Int", Const, 0}, {"Position", Type, 0}, {"Position.Column", Field, 0}, {"Position.Filename", Field, 0}, {"Position.Line", Field, 0}, {"Position.Offset", Field, 0}, {"RawString", Const, 0}, {"ScanChars", Const, 0}, {"ScanComments", Const, 0}, {"ScanFloats", Const, 0}, {"ScanIdents", Const, 0}, {"ScanInts", Const, 0}, {"ScanRawStrings", Const, 0}, {"ScanStrings", Const, 0}, {"Scanner", Type, 0}, {"Scanner.Error", Field, 0}, {"Scanner.ErrorCount", Field, 0}, {"Scanner.IsIdentRune", Field, 4}, {"Scanner.Mode", Field, 0}, {"Scanner.Position", Field, 0}, {"Scanner.Whitespace", Field, 0}, {"SkipComments", Const, 0}, {"String", Const, 0}, {"TokenString", Func, 0}, }, "text/tabwriter": { {"(*Writer).Flush", Method, 0}, {"(*Writer).Init", Method, 0}, {"(*Writer).Write", Method, 0}, {"AlignRight", Const, 0}, {"Debug", Const, 0}, {"DiscardEmptyColumns", Const, 0}, {"Escape", Const, 0}, {"FilterHTML", Const, 0}, {"NewWriter", Func, 0}, {"StripEscape", Const, 0}, {"TabIndent", Const, 0}, {"Writer", Type, 0}, }, "text/template": { {"(*Template).AddParseTree", Method, 0}, {"(*Template).Clone", Method, 0}, {"(*Template).DefinedTemplates", Method, 5}, {"(*Template).Delims", Method, 0}, {"(*Template).Execute", Method, 0}, {"(*Template).ExecuteTemplate", Method, 0}, {"(*Template).Funcs", Method, 0}, {"(*Template).Lookup", Method, 0}, {"(*Template).Name", Method, 0}, {"(*Template).New", Method, 0}, {"(*Template).Option", Method, 5}, {"(*Template).Parse", Method, 0}, {"(*Template).ParseFS", Method, 16}, {"(*Template).ParseFiles", Method, 0}, {"(*Template).ParseGlob", Method, 0}, {"(*Template).Templates", Method, 0}, {"(ExecError).Error", Method, 6}, {"(ExecError).Unwrap", Method, 13}, {"(Template).Copy", Method, 2}, {"(Template).ErrorContext", Method, 1}, {"ExecError", Type, 6}, {"ExecError.Err", Field, 6}, {"ExecError.Name", Field, 6}, {"FuncMap", Type, 0}, {"HTMLEscape", Func, 0}, {"HTMLEscapeString", Func, 0}, {"HTMLEscaper", Func, 0}, {"IsTrue", Func, 6}, {"JSEscape", Func, 0}, {"JSEscapeString", Func, 0}, {"JSEscaper", Func, 0}, {"Must", Func, 0}, {"New", Func, 0}, {"ParseFS", Func, 16}, {"ParseFiles", Func, 0}, {"ParseGlob", Func, 0}, {"Template", Type, 0}, {"Template.Tree", Field, 0}, {"URLQueryEscaper", Func, 0}, }, "text/template/parse": { {"(*ActionNode).Copy", Method, 0}, {"(*ActionNode).String", Method, 0}, {"(*BoolNode).Copy", Method, 0}, {"(*BoolNode).String", Method, 0}, {"(*BranchNode).Copy", Method, 4}, {"(*BranchNode).String", Method, 0}, {"(*BreakNode).Copy", Method, 18}, {"(*BreakNode).String", Method, 18}, {"(*ChainNode).Add", Method, 1}, {"(*ChainNode).Copy", Method, 1}, {"(*ChainNode).String", Method, 1}, {"(*CommandNode).Copy", Method, 0}, {"(*CommandNode).String", Method, 0}, {"(*CommentNode).Copy", Method, 16}, {"(*CommentNode).String", Method, 16}, {"(*ContinueNode).Copy", Method, 18}, {"(*ContinueNode).String", Method, 18}, {"(*DotNode).Copy", Method, 0}, {"(*DotNode).String", Method, 0}, {"(*DotNode).Type", Method, 0}, {"(*FieldNode).Copy", Method, 0}, {"(*FieldNode).String", Method, 0}, {"(*IdentifierNode).Copy", Method, 0}, {"(*IdentifierNode).SetPos", Method, 1}, {"(*IdentifierNode).SetTree", Method, 4}, {"(*IdentifierNode).String", Method, 0}, {"(*IfNode).Copy", Method, 0}, {"(*IfNode).String", Method, 0}, {"(*ListNode).Copy", Method, 0}, {"(*ListNode).CopyList", Method, 0}, {"(*ListNode).String", Method, 0}, {"(*NilNode).Copy", Method, 1}, {"(*NilNode).String", Method, 1}, {"(*NilNode).Type", Method, 1}, {"(*NumberNode).Copy", Method, 0}, {"(*NumberNode).String", Method, 0}, {"(*PipeNode).Copy", Method, 0}, {"(*PipeNode).CopyPipe", Method, 0}, {"(*PipeNode).String", Method, 0}, {"(*RangeNode).Copy", Method, 0}, {"(*RangeNode).String", Method, 0}, {"(*StringNode).Copy", Method, 0}, {"(*StringNode).String", Method, 0}, {"(*TemplateNode).Copy", Method, 0}, {"(*TemplateNode).String", Method, 0}, {"(*TextNode).Copy", Method, 0}, {"(*TextNode).String", Method, 0}, {"(*Tree).Copy", Method, 2}, {"(*Tree).ErrorContext", Method, 1}, {"(*Tree).Parse", Method, 0}, {"(*VariableNode).Copy", Method, 0}, {"(*VariableNode).String", Method, 0}, {"(*WithNode).Copy", Method, 0}, {"(*WithNode).String", Method, 0}, {"(ActionNode).Position", Method, 1}, {"(ActionNode).Type", Method, 0}, {"(BoolNode).Position", Method, 1}, {"(BoolNode).Type", Method, 0}, {"(BranchNode).Position", Method, 1}, {"(BranchNode).Type", Method, 0}, {"(BreakNode).Position", Method, 18}, {"(BreakNode).Type", Method, 18}, {"(ChainNode).Position", Method, 1}, {"(ChainNode).Type", Method, 1}, {"(CommandNode).Position", Method, 1}, {"(CommandNode).Type", Method, 0}, {"(CommentNode).Position", Method, 16}, {"(CommentNode).Type", Method, 16}, {"(ContinueNode).Position", Method, 18}, {"(ContinueNode).Type", Method, 18}, {"(DotNode).Position", Method, 1}, {"(FieldNode).Position", Method, 1}, {"(FieldNode).Type", Method, 0}, {"(IdentifierNode).Position", Method, 1}, {"(IdentifierNode).Type", Method, 0}, {"(IfNode).Position", Method, 1}, {"(IfNode).Type", Method, 0}, {"(ListNode).Position", Method, 1}, {"(ListNode).Type", Method, 0}, {"(NilNode).Position", Method, 1}, {"(NodeType).Type", Method, 0}, {"(NumberNode).Position", Method, 1}, {"(NumberNode).Type", Method, 0}, {"(PipeNode).Position", Method, 1}, {"(PipeNode).Type", Method, 0}, {"(Pos).Position", Method, 1}, {"(RangeNode).Position", Method, 1}, {"(RangeNode).Type", Method, 0}, {"(StringNode).Position", Method, 1}, {"(StringNode).Type", Method, 0}, {"(TemplateNode).Position", Method, 1}, {"(TemplateNode).Type", Method, 0}, {"(TextNode).Position", Method, 1}, {"(TextNode).Type", Method, 0}, {"(VariableNode).Position", Method, 1}, {"(VariableNode).Type", Method, 0}, {"(WithNode).Position", Method, 1}, {"(WithNode).Type", Method, 0}, {"ActionNode", Type, 0}, {"ActionNode.Line", Field, 0}, {"ActionNode.NodeType", Field, 0}, {"ActionNode.Pipe", Field, 0}, {"ActionNode.Pos", Field, 1}, {"BoolNode", Type, 0}, {"BoolNode.NodeType", Field, 0}, {"BoolNode.Pos", Field, 1}, {"BoolNode.True", Field, 0}, {"BranchNode", Type, 0}, {"BranchNode.ElseList", Field, 0}, {"BranchNode.Line", Field, 0}, {"BranchNode.List", Field, 0}, {"BranchNode.NodeType", Field, 0}, {"BranchNode.Pipe", Field, 0}, {"BranchNode.Pos", Field, 1}, {"BreakNode", Type, 18}, {"BreakNode.Line", Field, 18}, {"BreakNode.NodeType", Field, 18}, {"BreakNode.Pos", Field, 18}, {"ChainNode", Type, 1}, {"ChainNode.Field", Field, 1}, {"ChainNode.Node", Field, 1}, {"ChainNode.NodeType", Field, 1}, {"ChainNode.Pos", Field, 1}, {"CommandNode", Type, 0}, {"CommandNode.Args", Field, 0}, {"CommandNode.NodeType", Field, 0}, {"CommandNode.Pos", Field, 1}, {"CommentNode", Type, 16}, {"CommentNode.NodeType", Field, 16}, {"CommentNode.Pos", Field, 16}, {"CommentNode.Text", Field, 16}, {"ContinueNode", Type, 18}, {"ContinueNode.Line", Field, 18}, {"ContinueNode.NodeType", Field, 18}, {"ContinueNode.Pos", Field, 18}, {"DotNode", Type, 0}, {"DotNode.NodeType", Field, 4}, {"DotNode.Pos", Field, 1}, {"FieldNode", Type, 0}, {"FieldNode.Ident", Field, 0}, {"FieldNode.NodeType", Field, 0}, {"FieldNode.Pos", Field, 1}, {"IdentifierNode", Type, 0}, {"IdentifierNode.Ident", Field, 0}, {"IdentifierNode.NodeType", Field, 0}, {"IdentifierNode.Pos", Field, 1}, {"IfNode", Type, 0}, {"IfNode.BranchNode", Field, 0}, {"IsEmptyTree", Func, 0}, {"ListNode", Type, 0}, {"ListNode.NodeType", Field, 0}, {"ListNode.Nodes", Field, 0}, {"ListNode.Pos", Field, 1}, {"Mode", Type, 16}, {"New", Func, 0}, {"NewIdentifier", Func, 0}, {"NilNode", Type, 1}, {"NilNode.NodeType", Field, 4}, {"NilNode.Pos", Field, 1}, {"Node", Type, 0}, {"NodeAction", Const, 0}, {"NodeBool", Const, 0}, {"NodeBreak", Const, 18}, {"NodeChain", Const, 1}, {"NodeCommand", Const, 0}, {"NodeComment", Const, 16}, {"NodeContinue", Const, 18}, {"NodeDot", Const, 0}, {"NodeField", Const, 0}, {"NodeIdentifier", Const, 0}, {"NodeIf", Const, 0}, {"NodeList", Const, 0}, {"NodeNil", Const, 1}, {"NodeNumber", Const, 0}, {"NodePipe", Const, 0}, {"NodeRange", Const, 0}, {"NodeString", Const, 0}, {"NodeTemplate", Const, 0}, {"NodeText", Const, 0}, {"NodeType", Type, 0}, {"NodeVariable", Const, 0}, {"NodeWith", Const, 0}, {"NumberNode", Type, 0}, {"NumberNode.Complex128", Field, 0}, {"NumberNode.Float64", Field, 0}, {"NumberNode.Int64", Field, 0}, {"NumberNode.IsComplex", Field, 0}, {"NumberNode.IsFloat", Field, 0}, {"NumberNode.IsInt", Field, 0}, {"NumberNode.IsUint", Field, 0}, {"NumberNode.NodeType", Field, 0}, {"NumberNode.Pos", Field, 1}, {"NumberNode.Text", Field, 0}, {"NumberNode.Uint64", Field, 0}, {"Parse", Func, 0}, {"ParseComments", Const, 16}, {"PipeNode", Type, 0}, {"PipeNode.Cmds", Field, 0}, {"PipeNode.Decl", Field, 0}, {"PipeNode.IsAssign", Field, 11}, {"PipeNode.Line", Field, 0}, {"PipeNode.NodeType", Field, 0}, {"PipeNode.Pos", Field, 1}, {"Pos", Type, 1}, {"RangeNode", Type, 0}, {"RangeNode.BranchNode", Field, 0}, {"SkipFuncCheck", Const, 17}, {"StringNode", Type, 0}, {"StringNode.NodeType", Field, 0}, {"StringNode.Pos", Field, 1}, {"StringNode.Quoted", Field, 0}, {"StringNode.Text", Field, 0}, {"TemplateNode", Type, 0}, {"TemplateNode.Line", Field, 0}, {"TemplateNode.Name", Field, 0}, {"TemplateNode.NodeType", Field, 0}, {"TemplateNode.Pipe", Field, 0}, {"TemplateNode.Pos", Field, 1}, {"TextNode", Type, 0}, {"TextNode.NodeType", Field, 0}, {"TextNode.Pos", Field, 1}, {"TextNode.Text", Field, 0}, {"Tree", Type, 0}, {"Tree.Mode", Field, 16}, {"Tree.Name", Field, 0}, {"Tree.ParseName", Field, 1}, {"Tree.Root", Field, 0}, {"VariableNode", Type, 0}, {"VariableNode.Ident", Field, 0}, {"VariableNode.NodeType", Field, 0}, {"VariableNode.Pos", Field, 1}, {"WithNode", Type, 0}, {"WithNode.BranchNode", Field, 0}, }, "time": { {"(*Location).String", Method, 0}, {"(*ParseError).Error", Method, 0}, {"(*Ticker).Reset", Method, 15}, {"(*Ticker).Stop", Method, 0}, {"(*Time).GobDecode", Method, 0}, {"(*Time).UnmarshalBinary", Method, 2}, {"(*Time).UnmarshalJSON", Method, 0}, {"(*Time).UnmarshalText", Method, 2}, {"(*Timer).Reset", Method, 1}, {"(*Timer).Stop", Method, 0}, {"(Duration).Abs", Method, 19}, {"(Duration).Hours", Method, 0}, {"(Duration).Microseconds", Method, 13}, {"(Duration).Milliseconds", Method, 13}, {"(Duration).Minutes", Method, 0}, {"(Duration).Nanoseconds", Method, 0}, {"(Duration).Round", Method, 9}, {"(Duration).Seconds", Method, 0}, {"(Duration).String", Method, 0}, {"(Duration).Truncate", Method, 9}, {"(Month).String", Method, 0}, {"(Time).Add", Method, 0}, {"(Time).AddDate", Method, 0}, {"(Time).After", Method, 0}, {"(Time).AppendBinary", Method, 24}, {"(Time).AppendFormat", Method, 5}, {"(Time).AppendText", Method, 24}, {"(Time).Before", Method, 0}, {"(Time).Clock", Method, 0}, {"(Time).Compare", Method, 20}, {"(Time).Date", Method, 0}, {"(Time).Day", Method, 0}, {"(Time).Equal", Method, 0}, {"(Time).Format", Method, 0}, {"(Time).GoString", Method, 17}, {"(Time).GobEncode", Method, 0}, {"(Time).Hour", Method, 0}, {"(Time).ISOWeek", Method, 0}, {"(Time).In", Method, 0}, {"(Time).IsDST", Method, 17}, {"(Time).IsZero", Method, 0}, {"(Time).Local", Method, 0}, {"(Time).Location", Method, 0}, {"(Time).MarshalBinary", Method, 2}, {"(Time).MarshalJSON", Method, 0}, {"(Time).MarshalText", Method, 2}, {"(Time).Minute", Method, 0}, {"(Time).Month", Method, 0}, {"(Time).Nanosecond", Method, 0}, {"(Time).Round", Method, 1}, {"(Time).Second", Method, 0}, {"(Time).String", Method, 0}, {"(Time).Sub", Method, 0}, {"(Time).Truncate", Method, 1}, {"(Time).UTC", Method, 0}, {"(Time).Unix", Method, 0}, {"(Time).UnixMicro", Method, 17}, {"(Time).UnixMilli", Method, 17}, {"(Time).UnixNano", Method, 0}, {"(Time).Weekday", Method, 0}, {"(Time).Year", Method, 0}, {"(Time).YearDay", Method, 1}, {"(Time).Zone", Method, 0}, {"(Time).ZoneBounds", Method, 19}, {"(Weekday).String", Method, 0}, {"ANSIC", Const, 0}, {"After", Func, 0}, {"AfterFunc", Func, 0}, {"April", Const, 0}, {"August", Const, 0}, {"Date", Func, 0}, {"DateOnly", Const, 20}, {"DateTime", Const, 20}, {"December", Const, 0}, {"Duration", Type, 0}, {"February", Const, 0}, {"FixedZone", Func, 0}, {"Friday", Const, 0}, {"Hour", Const, 0}, {"January", Const, 0}, {"July", Const, 0}, {"June", Const, 0}, {"Kitchen", Const, 0}, {"Layout", Const, 17}, {"LoadLocation", Func, 0}, {"LoadLocationFromTZData", Func, 10}, {"Local", Var, 0}, {"Location", Type, 0}, {"March", Const, 0}, {"May", Const, 0}, {"Microsecond", Const, 0}, {"Millisecond", Const, 0}, {"Minute", Const, 0}, {"Monday", Const, 0}, {"Month", Type, 0}, {"Nanosecond", Const, 0}, {"NewTicker", Func, 0}, {"NewTimer", Func, 0}, {"November", Const, 0}, {"Now", Func, 0}, {"October", Const, 0}, {"Parse", Func, 0}, {"ParseDuration", Func, 0}, {"ParseError", Type, 0}, {"ParseError.Layout", Field, 0}, {"ParseError.LayoutElem", Field, 0}, {"ParseError.Message", Field, 0}, {"ParseError.Value", Field, 0}, {"ParseError.ValueElem", Field, 0}, {"ParseInLocation", Func, 1}, {"RFC1123", Const, 0}, {"RFC1123Z", Const, 0}, {"RFC3339", Const, 0}, {"RFC3339Nano", Const, 0}, {"RFC822", Const, 0}, {"RFC822Z", Const, 0}, {"RFC850", Const, 0}, {"RubyDate", Const, 0}, {"Saturday", Const, 0}, {"Second", Const, 0}, {"September", Const, 0}, {"Since", Func, 0}, {"Sleep", Func, 0}, {"Stamp", Const, 0}, {"StampMicro", Const, 0}, {"StampMilli", Const, 0}, {"StampNano", Const, 0}, {"Sunday", Const, 0}, {"Thursday", Const, 0}, {"Tick", Func, 0}, {"Ticker", Type, 0}, {"Ticker.C", Field, 0}, {"Time", Type, 0}, {"TimeOnly", Const, 20}, {"Timer", Type, 0}, {"Timer.C", Field, 0}, {"Tuesday", Const, 0}, {"UTC", Var, 0}, {"Unix", Func, 0}, {"UnixDate", Const, 0}, {"UnixMicro", Func, 17}, {"UnixMilli", Func, 17}, {"Until", Func, 8}, {"Wednesday", Const, 0}, {"Weekday", Type, 0}, }, "unicode": { {"(SpecialCase).ToLower", Method, 0}, {"(SpecialCase).ToTitle", Method, 0}, {"(SpecialCase).ToUpper", Method, 0}, {"ASCII_Hex_Digit", Var, 0}, {"Adlam", Var, 7}, {"Ahom", Var, 5}, {"Anatolian_Hieroglyphs", Var, 5}, {"Arabic", Var, 0}, {"Armenian", Var, 0}, {"Avestan", Var, 0}, {"AzeriCase", Var, 0}, {"Balinese", Var, 0}, {"Bamum", Var, 0}, {"Bassa_Vah", Var, 4}, {"Batak", Var, 0}, {"Bengali", Var, 0}, {"Bhaiksuki", Var, 7}, {"Bidi_Control", Var, 0}, {"Bopomofo", Var, 0}, {"Brahmi", Var, 0}, {"Braille", Var, 0}, {"Buginese", Var, 0}, {"Buhid", Var, 0}, {"C", Var, 0}, {"Canadian_Aboriginal", Var, 0}, {"Carian", Var, 0}, {"CaseRange", Type, 0}, {"CaseRange.Delta", Field, 0}, {"CaseRange.Hi", Field, 0}, {"CaseRange.Lo", Field, 0}, {"CaseRanges", Var, 0}, {"Categories", Var, 0}, {"Caucasian_Albanian", Var, 4}, {"Cc", Var, 0}, {"Cf", Var, 0}, {"Chakma", Var, 1}, {"Cham", Var, 0}, {"Cherokee", Var, 0}, {"Chorasmian", Var, 16}, {"Co", Var, 0}, {"Common", Var, 0}, {"Coptic", Var, 0}, {"Cs", Var, 0}, {"Cuneiform", Var, 0}, {"Cypriot", Var, 0}, {"Cypro_Minoan", Var, 21}, {"Cyrillic", Var, 0}, {"Dash", Var, 0}, {"Deprecated", Var, 0}, {"Deseret", Var, 0}, {"Devanagari", Var, 0}, {"Diacritic", Var, 0}, {"Digit", Var, 0}, {"Dives_Akuru", Var, 16}, {"Dogra", Var, 13}, {"Duployan", Var, 4}, {"Egyptian_Hieroglyphs", Var, 0}, {"Elbasan", Var, 4}, {"Elymaic", Var, 14}, {"Ethiopic", Var, 0}, {"Extender", Var, 0}, {"FoldCategory", Var, 0}, {"FoldScript", Var, 0}, {"Georgian", Var, 0}, {"Glagolitic", Var, 0}, {"Gothic", Var, 0}, {"Grantha", Var, 4}, {"GraphicRanges", Var, 0}, {"Greek", Var, 0}, {"Gujarati", Var, 0}, {"Gunjala_Gondi", Var, 13}, {"Gurmukhi", Var, 0}, {"Han", Var, 0}, {"Hangul", Var, 0}, {"Hanifi_Rohingya", Var, 13}, {"Hanunoo", Var, 0}, {"Hatran", Var, 5}, {"Hebrew", Var, 0}, {"Hex_Digit", Var, 0}, {"Hiragana", Var, 0}, {"Hyphen", Var, 0}, {"IDS_Binary_Operator", Var, 0}, {"IDS_Trinary_Operator", Var, 0}, {"Ideographic", Var, 0}, {"Imperial_Aramaic", Var, 0}, {"In", Func, 2}, {"Inherited", Var, 0}, {"Inscriptional_Pahlavi", Var, 0}, {"Inscriptional_Parthian", Var, 0}, {"Is", Func, 0}, {"IsControl", Func, 0}, {"IsDigit", Func, 0}, {"IsGraphic", Func, 0}, {"IsLetter", Func, 0}, {"IsLower", Func, 0}, {"IsMark", Func, 0}, {"IsNumber", Func, 0}, {"IsOneOf", Func, 0}, {"IsPrint", Func, 0}, {"IsPunct", Func, 0}, {"IsSpace", Func, 0}, {"IsSymbol", Func, 0}, {"IsTitle", Func, 0}, {"IsUpper", Func, 0}, {"Javanese", Var, 0}, {"Join_Control", Var, 0}, {"Kaithi", Var, 0}, {"Kannada", Var, 0}, {"Katakana", Var, 0}, {"Kawi", Var, 21}, {"Kayah_Li", Var, 0}, {"Kharoshthi", Var, 0}, {"Khitan_Small_Script", Var, 16}, {"Khmer", Var, 0}, {"Khojki", Var, 4}, {"Khudawadi", Var, 4}, {"L", Var, 0}, {"Lao", Var, 0}, {"Latin", Var, 0}, {"Lepcha", Var, 0}, {"Letter", Var, 0}, {"Limbu", Var, 0}, {"Linear_A", Var, 4}, {"Linear_B", Var, 0}, {"Lisu", Var, 0}, {"Ll", Var, 0}, {"Lm", Var, 0}, {"Lo", Var, 0}, {"Logical_Order_Exception", Var, 0}, {"Lower", Var, 0}, {"LowerCase", Const, 0}, {"Lt", Var, 0}, {"Lu", Var, 0}, {"Lycian", Var, 0}, {"Lydian", Var, 0}, {"M", Var, 0}, {"Mahajani", Var, 4}, {"Makasar", Var, 13}, {"Malayalam", Var, 0}, {"Mandaic", Var, 0}, {"Manichaean", Var, 4}, {"Marchen", Var, 7}, {"Mark", Var, 0}, {"Masaram_Gondi", Var, 10}, {"MaxASCII", Const, 0}, {"MaxCase", Const, 0}, {"MaxLatin1", Const, 0}, {"MaxRune", Const, 0}, {"Mc", Var, 0}, {"Me", Var, 0}, {"Medefaidrin", Var, 13}, {"Meetei_Mayek", Var, 0}, {"Mende_Kikakui", Var, 4}, {"Meroitic_Cursive", Var, 1}, {"Meroitic_Hieroglyphs", Var, 1}, {"Miao", Var, 1}, {"Mn", Var, 0}, {"Modi", Var, 4}, {"Mongolian", Var, 0}, {"Mro", Var, 4}, {"Multani", Var, 5}, {"Myanmar", Var, 0}, {"N", Var, 0}, {"Nabataean", Var, 4}, {"Nag_Mundari", Var, 21}, {"Nandinagari", Var, 14}, {"Nd", Var, 0}, {"New_Tai_Lue", Var, 0}, {"Newa", Var, 7}, {"Nko", Var, 0}, {"Nl", Var, 0}, {"No", Var, 0}, {"Noncharacter_Code_Point", Var, 0}, {"Number", Var, 0}, {"Nushu", Var, 10}, {"Nyiakeng_Puachue_Hmong", Var, 14}, {"Ogham", Var, 0}, {"Ol_Chiki", Var, 0}, {"Old_Hungarian", Var, 5}, {"Old_Italic", Var, 0}, {"Old_North_Arabian", Var, 4}, {"Old_Permic", Var, 4}, {"Old_Persian", Var, 0}, {"Old_Sogdian", Var, 13}, {"Old_South_Arabian", Var, 0}, {"Old_Turkic", Var, 0}, {"Old_Uyghur", Var, 21}, {"Oriya", Var, 0}, {"Osage", Var, 7}, {"Osmanya", Var, 0}, {"Other", Var, 0}, {"Other_Alphabetic", Var, 0}, {"Other_Default_Ignorable_Code_Point", Var, 0}, {"Other_Grapheme_Extend", Var, 0}, {"Other_ID_Continue", Var, 0}, {"Other_ID_Start", Var, 0}, {"Other_Lowercase", Var, 0}, {"Other_Math", Var, 0}, {"Other_Uppercase", Var, 0}, {"P", Var, 0}, {"Pahawh_Hmong", Var, 4}, {"Palmyrene", Var, 4}, {"Pattern_Syntax", Var, 0}, {"Pattern_White_Space", Var, 0}, {"Pau_Cin_Hau", Var, 4}, {"Pc", Var, 0}, {"Pd", Var, 0}, {"Pe", Var, 0}, {"Pf", Var, 0}, {"Phags_Pa", Var, 0}, {"Phoenician", Var, 0}, {"Pi", Var, 0}, {"Po", Var, 0}, {"Prepended_Concatenation_Mark", Var, 7}, {"PrintRanges", Var, 0}, {"Properties", Var, 0}, {"Ps", Var, 0}, {"Psalter_Pahlavi", Var, 4}, {"Punct", Var, 0}, {"Quotation_Mark", Var, 0}, {"Radical", Var, 0}, {"Range16", Type, 0}, {"Range16.Hi", Field, 0}, {"Range16.Lo", Field, 0}, {"Range16.Stride", Field, 0}, {"Range32", Type, 0}, {"Range32.Hi", Field, 0}, {"Range32.Lo", Field, 0}, {"Range32.Stride", Field, 0}, {"RangeTable", Type, 0}, {"RangeTable.LatinOffset", Field, 1}, {"RangeTable.R16", Field, 0}, {"RangeTable.R32", Field, 0}, {"Regional_Indicator", Var, 10}, {"Rejang", Var, 0}, {"ReplacementChar", Const, 0}, {"Runic", Var, 0}, {"S", Var, 0}, {"STerm", Var, 0}, {"Samaritan", Var, 0}, {"Saurashtra", Var, 0}, {"Sc", Var, 0}, {"Scripts", Var, 0}, {"Sentence_Terminal", Var, 7}, {"Sharada", Var, 1}, {"Shavian", Var, 0}, {"Siddham", Var, 4}, {"SignWriting", Var, 5}, {"SimpleFold", Func, 0}, {"Sinhala", Var, 0}, {"Sk", Var, 0}, {"Sm", Var, 0}, {"So", Var, 0}, {"Soft_Dotted", Var, 0}, {"Sogdian", Var, 13}, {"Sora_Sompeng", Var, 1}, {"Soyombo", Var, 10}, {"Space", Var, 0}, {"SpecialCase", Type, 0}, {"Sundanese", Var, 0}, {"Syloti_Nagri", Var, 0}, {"Symbol", Var, 0}, {"Syriac", Var, 0}, {"Tagalog", Var, 0}, {"Tagbanwa", Var, 0}, {"Tai_Le", Var, 0}, {"Tai_Tham", Var, 0}, {"Tai_Viet", Var, 0}, {"Takri", Var, 1}, {"Tamil", Var, 0}, {"Tangsa", Var, 21}, {"Tangut", Var, 7}, {"Telugu", Var, 0}, {"Terminal_Punctuation", Var, 0}, {"Thaana", Var, 0}, {"Thai", Var, 0}, {"Tibetan", Var, 0}, {"Tifinagh", Var, 0}, {"Tirhuta", Var, 4}, {"Title", Var, 0}, {"TitleCase", Const, 0}, {"To", Func, 0}, {"ToLower", Func, 0}, {"ToTitle", Func, 0}, {"ToUpper", Func, 0}, {"Toto", Var, 21}, {"TurkishCase", Var, 0}, {"Ugaritic", Var, 0}, {"Unified_Ideograph", Var, 0}, {"Upper", Var, 0}, {"UpperCase", Const, 0}, {"UpperLower", Const, 0}, {"Vai", Var, 0}, {"Variation_Selector", Var, 0}, {"Version", Const, 0}, {"Vithkuqi", Var, 21}, {"Wancho", Var, 14}, {"Warang_Citi", Var, 4}, {"White_Space", Var, 0}, {"Yezidi", Var, 16}, {"Yi", Var, 0}, {"Z", Var, 0}, {"Zanabazar_Square", Var, 10}, {"Zl", Var, 0}, {"Zp", Var, 0}, {"Zs", Var, 0}, }, "unicode/utf16": { {"AppendRune", Func, 20}, {"Decode", Func, 0}, {"DecodeRune", Func, 0}, {"Encode", Func, 0}, {"EncodeRune", Func, 0}, {"IsSurrogate", Func, 0}, {"RuneLen", Func, 23}, }, "unicode/utf8": { {"AppendRune", Func, 18}, {"DecodeLastRune", Func, 0}, {"DecodeLastRuneInString", Func, 0}, {"DecodeRune", Func, 0}, {"DecodeRuneInString", Func, 0}, {"EncodeRune", Func, 0}, {"FullRune", Func, 0}, {"FullRuneInString", Func, 0}, {"MaxRune", Const, 0}, {"RuneCount", Func, 0}, {"RuneCountInString", Func, 0}, {"RuneError", Const, 0}, {"RuneLen", Func, 0}, {"RuneSelf", Const, 0}, {"RuneStart", Func, 0}, {"UTFMax", Const, 0}, {"Valid", Func, 0}, {"ValidRune", Func, 1}, {"ValidString", Func, 0}, }, "unique": { {"(Handle).Value", Method, 23}, {"Handle", Type, 23}, {"Make", Func, 23}, }, "unsafe": { {"Add", Func, 0}, {"Alignof", Func, 0}, {"Offsetof", Func, 0}, {"Pointer", Type, 0}, {"Sizeof", Func, 0}, {"Slice", Func, 0}, {"SliceData", Func, 0}, {"String", Func, 0}, {"StringData", Func, 0}, }, "weak": { {"(Pointer).Value", Method, 24}, {"Make", Func, 24}, {"Pointer", Type, 24}, }, } -- y -- // Copyright 2025 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // Code generated by generate.go. DO NOT EDIT. package stdlib var PackageSymbols = map[string][]Symbol{ "archive/tar": { {"(*Header).FileInfo", Method, 1, ""}, {"(*Reader).Next", Method, 0, ""}, {"(*Reader).Read", Method, 0, ""}, {"(*Writer).AddFS", Method, 22, ""}, {"(*Writer).Close", Method, 0, ""}, {"(*Writer).Flush", Method, 0, ""}, {"(*Writer).Write", Method, 0, ""}, {"(*Writer).WriteHeader", Method, 0, ""}, {"(Format).String", Method, 10, ""}, {"ErrFieldTooLong", Var, 0, ""}, {"ErrHeader", Var, 0, ""}, {"ErrInsecurePath", Var, 20, ""}, {"ErrWriteAfterClose", Var, 0, ""}, {"ErrWriteTooLong", Var, 0, ""}, {"FileInfoHeader", Func, 1, "func(fi fs.FileInfo, link string) (*Header, error)"}, {"FileInfoNames", Type, 23, ""}, {"Format", Type, 10, ""}, {"FormatGNU", Const, 10, ""}, {"FormatPAX", Const, 10, ""}, {"FormatUSTAR", Const, 10, ""}, {"FormatUnknown", Const, 10, ""}, {"Header", Type, 0, ""}, {"Header.AccessTime", Field, 0, ""}, {"Header.ChangeTime", Field, 0, ""}, {"Header.Devmajor", Field, 0, ""}, {"Header.Devminor", Field, 0, ""}, {"Header.Format", Field, 10, ""}, {"Header.Gid", Field, 0, ""}, {"Header.Gname", Field, 0, ""}, {"Header.Linkname", Field, 0, ""}, {"Header.ModTime", Field, 0, ""}, {"Header.Mode", Field, 0, ""}, {"Header.Name", Field, 0, ""}, {"Header.PAXRecords", Field, 10, ""}, {"Header.Size", Field, 0, ""}, {"Header.Typeflag", Field, 0, ""}, {"Header.Uid", Field, 0, ""}, {"Header.Uname", Field, 0, ""}, {"Header.Xattrs", Field, 3, ""}, {"NewReader", Func, 0, "func(r io.Reader) *Reader"}, {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, {"Reader", Type, 0, ""}, {"TypeBlock", Const, 0, ""}, {"TypeChar", Const, 0, ""}, {"TypeCont", Const, 0, ""}, {"TypeDir", Const, 0, ""}, {"TypeFifo", Const, 0, ""}, {"TypeGNULongLink", Const, 1, ""}, {"TypeGNULongName", Const, 1, ""}, {"TypeGNUSparse", Const, 3, ""}, {"TypeLink", Const, 0, ""}, {"TypeReg", Const, 0, ""}, {"TypeRegA", Const, 0, ""}, {"TypeSymlink", Const, 0, ""}, {"TypeXGlobalHeader", Const, 0, ""}, {"TypeXHeader", Const, 0, ""}, {"Writer", Type, 0, ""}, }, "archive/zip": { {"(*File).DataOffset", Method, 2, ""}, {"(*File).FileInfo", Method, 0, ""}, {"(*File).ModTime", Method, 0, ""}, {"(*File).Mode", Method, 0, ""}, {"(*File).Open", Method, 0, ""}, {"(*File).OpenRaw", Method, 17, ""}, {"(*File).SetModTime", Method, 0, ""}, {"(*File).SetMode", Method, 0, ""}, {"(*FileHeader).FileInfo", Method, 0, ""}, {"(*FileHeader).ModTime", Method, 0, ""}, {"(*FileHeader).Mode", Method, 0, ""}, {"(*FileHeader).SetModTime", Method, 0, ""}, {"(*FileHeader).SetMode", Method, 0, ""}, {"(*ReadCloser).Close", Method, 0, ""}, {"(*ReadCloser).Open", Method, 16, ""}, {"(*ReadCloser).RegisterDecompressor", Method, 6, ""}, {"(*Reader).Open", Method, 16, ""}, {"(*Reader).RegisterDecompressor", Method, 6, ""}, {"(*Writer).AddFS", Method, 22, ""}, {"(*Writer).Close", Method, 0, ""}, {"(*Writer).Copy", Method, 17, ""}, {"(*Writer).Create", Method, 0, ""}, {"(*Writer).CreateHeader", Method, 0, ""}, {"(*Writer).CreateRaw", Method, 17, ""}, {"(*Writer).Flush", Method, 4, ""}, {"(*Writer).RegisterCompressor", Method, 6, ""}, {"(*Writer).SetComment", Method, 10, ""}, {"(*Writer).SetOffset", Method, 5, ""}, {"Compressor", Type, 2, ""}, {"Decompressor", Type, 2, ""}, {"Deflate", Const, 0, ""}, {"ErrAlgorithm", Var, 0, ""}, {"ErrChecksum", Var, 0, ""}, {"ErrFormat", Var, 0, ""}, {"ErrInsecurePath", Var, 20, ""}, {"File", Type, 0, ""}, {"File.FileHeader", Field, 0, ""}, {"FileHeader", Type, 0, ""}, {"FileHeader.CRC32", Field, 0, ""}, {"FileHeader.Comment", Field, 0, ""}, {"FileHeader.CompressedSize", Field, 0, ""}, {"FileHeader.CompressedSize64", Field, 1, ""}, {"FileHeader.CreatorVersion", Field, 0, ""}, {"FileHeader.ExternalAttrs", Field, 0, ""}, {"FileHeader.Extra", Field, 0, ""}, {"FileHeader.Flags", Field, 0, ""}, {"FileHeader.Method", Field, 0, ""}, {"FileHeader.Modified", Field, 10, ""}, {"FileHeader.ModifiedDate", Field, 0, ""}, {"FileHeader.ModifiedTime", Field, 0, ""}, {"FileHeader.Name", Field, 0, ""}, {"FileHeader.NonUTF8", Field, 10, ""}, {"FileHeader.ReaderVersion", Field, 0, ""}, {"FileHeader.UncompressedSize", Field, 0, ""}, {"FileHeader.UncompressedSize64", Field, 1, ""}, {"FileInfoHeader", Func, 0, "func(fi fs.FileInfo) (*FileHeader, error)"}, {"NewReader", Func, 0, "func(r io.ReaderAt, size int64) (*Reader, error)"}, {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, {"OpenReader", Func, 0, "func(name string) (*ReadCloser, error)"}, {"ReadCloser", Type, 0, ""}, {"ReadCloser.Reader", Field, 0, ""}, {"Reader", Type, 0, ""}, {"Reader.Comment", Field, 0, ""}, {"Reader.File", Field, 0, ""}, {"RegisterCompressor", Func, 2, "func(method uint16, comp Compressor)"}, {"RegisterDecompressor", Func, 2, "func(method uint16, dcomp Decompressor)"}, {"Store", Const, 0, ""}, {"Writer", Type, 0, ""}, }, "bufio": { {"(*Reader).Buffered", Method, 0, ""}, {"(*Reader).Discard", Method, 5, ""}, {"(*Reader).Peek", Method, 0, ""}, {"(*Reader).Read", Method, 0, ""}, {"(*Reader).ReadByte", Method, 0, ""}, {"(*Reader).ReadBytes", Method, 0, ""}, {"(*Reader).ReadLine", Method, 0, ""}, {"(*Reader).ReadRune", Method, 0, ""}, {"(*Reader).ReadSlice", Method, 0, ""}, {"(*Reader).ReadString", Method, 0, ""}, {"(*Reader).Reset", Method, 2, ""}, {"(*Reader).Size", Method, 10, ""}, {"(*Reader).UnreadByte", Method, 0, ""}, {"(*Reader).UnreadRune", Method, 0, ""}, {"(*Reader).WriteTo", Method, 1, ""}, {"(*Scanner).Buffer", Method, 6, ""}, {"(*Scanner).Bytes", Method, 1, ""}, {"(*Scanner).Err", Method, 1, ""}, {"(*Scanner).Scan", Method, 1, ""}, {"(*Scanner).Split", Method, 1, ""}, {"(*Scanner).Text", Method, 1, ""}, {"(*Writer).Available", Method, 0, ""}, {"(*Writer).AvailableBuffer", Method, 18, ""}, {"(*Writer).Buffered", Method, 0, ""}, {"(*Writer).Flush", Method, 0, ""}, {"(*Writer).ReadFrom", Method, 1, ""}, {"(*Writer).Reset", Method, 2, ""}, {"(*Writer).Size", Method, 10, ""}, {"(*Writer).Write", Method, 0, ""}, {"(*Writer).WriteByte", Method, 0, ""}, {"(*Writer).WriteRune", Method, 0, ""}, {"(*Writer).WriteString", Method, 0, ""}, {"(ReadWriter).Available", Method, 0, ""}, {"(ReadWriter).AvailableBuffer", Method, 18, ""}, {"(ReadWriter).Discard", Method, 5, ""}, {"(ReadWriter).Flush", Method, 0, ""}, {"(ReadWriter).Peek", Method, 0, ""}, {"(ReadWriter).Read", Method, 0, ""}, {"(ReadWriter).ReadByte", Method, 0, ""}, {"(ReadWriter).ReadBytes", Method, 0, ""}, {"(ReadWriter).ReadFrom", Method, 1, ""}, {"(ReadWriter).ReadLine", Method, 0, ""}, {"(ReadWriter).ReadRune", Method, 0, ""}, {"(ReadWriter).ReadSlice", Method, 0, ""}, {"(ReadWriter).ReadString", Method, 0, ""}, {"(ReadWriter).UnreadByte", Method, 0, ""}, {"(ReadWriter).UnreadRune", Method, 0, ""}, {"(ReadWriter).Write", Method, 0, ""}, {"(ReadWriter).WriteByte", Method, 0, ""}, {"(ReadWriter).WriteRune", Method, 0, ""}, {"(ReadWriter).WriteString", Method, 0, ""}, {"(ReadWriter).WriteTo", Method, 1, ""}, {"ErrAdvanceTooFar", Var, 1, ""}, {"ErrBadReadCount", Var, 15, ""}, {"ErrBufferFull", Var, 0, ""}, {"ErrFinalToken", Var, 6, ""}, {"ErrInvalidUnreadByte", Var, 0, ""}, {"ErrInvalidUnreadRune", Var, 0, ""}, {"ErrNegativeAdvance", Var, 1, ""}, {"ErrNegativeCount", Var, 0, ""}, {"ErrTooLong", Var, 1, ""}, {"MaxScanTokenSize", Const, 1, ""}, {"NewReadWriter", Func, 0, "func(r *Reader, w *Writer) *ReadWriter"}, {"NewReader", Func, 0, "func(rd io.Reader) *Reader"}, {"NewReaderSize", Func, 0, "func(rd io.Reader, size int) *Reader"}, {"NewScanner", Func, 1, "func(r io.Reader) *Scanner"}, {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, {"NewWriterSize", Func, 0, "func(w io.Writer, size int) *Writer"}, {"ReadWriter", Type, 0, ""}, {"ReadWriter.Reader", Field, 0, ""}, {"ReadWriter.Writer", Field, 0, ""}, {"Reader", Type, 0, ""}, {"ScanBytes", Func, 1, "func(data []byte, atEOF bool) (advance int, token []byte, err error)"}, {"ScanLines", Func, 1, "func(data []byte, atEOF bool) (advance int, token []byte, err error)"}, {"ScanRunes", Func, 1, "func(data []byte, atEOF bool) (advance int, token []byte, err error)"}, {"ScanWords", Func, 1, "func(data []byte, atEOF bool) (advance int, token []byte, err error)"}, {"Scanner", Type, 1, ""}, {"SplitFunc", Type, 1, ""}, {"Writer", Type, 0, ""}, }, "bytes": { {"(*Buffer).Available", Method, 21, ""}, {"(*Buffer).AvailableBuffer", Method, 21, ""}, {"(*Buffer).Bytes", Method, 0, ""}, {"(*Buffer).Cap", Method, 5, ""}, {"(*Buffer).Grow", Method, 1, ""}, {"(*Buffer).Len", Method, 0, ""}, {"(*Buffer).Next", Method, 0, ""}, {"(*Buffer).Read", Method, 0, ""}, {"(*Buffer).ReadByte", Method, 0, ""}, {"(*Buffer).ReadBytes", Method, 0, ""}, {"(*Buffer).ReadFrom", Method, 0, ""}, {"(*Buffer).ReadRune", Method, 0, ""}, {"(*Buffer).ReadString", Method, 0, ""}, {"(*Buffer).Reset", Method, 0, ""}, {"(*Buffer).String", Method, 0, ""}, {"(*Buffer).Truncate", Method, 0, ""}, {"(*Buffer).UnreadByte", Method, 0, ""}, {"(*Buffer).UnreadRune", Method, 0, ""}, {"(*Buffer).Write", Method, 0, ""}, {"(*Buffer).WriteByte", Method, 0, ""}, {"(*Buffer).WriteRune", Method, 0, ""}, {"(*Buffer).WriteString", Method, 0, ""}, {"(*Buffer).WriteTo", Method, 0, ""}, {"(*Reader).Len", Method, 0, ""}, {"(*Reader).Read", Method, 0, ""}, {"(*Reader).ReadAt", Method, 0, ""}, {"(*Reader).ReadByte", Method, 0, ""}, {"(*Reader).ReadRune", Method, 0, ""}, {"(*Reader).Reset", Method, 7, ""}, {"(*Reader).Seek", Method, 0, ""}, {"(*Reader).Size", Method, 5, ""}, {"(*Reader).UnreadByte", Method, 0, ""}, {"(*Reader).UnreadRune", Method, 0, ""}, {"(*Reader).WriteTo", Method, 1, ""}, {"Buffer", Type, 0, ""}, {"Clone", Func, 20, "func(b []byte) []byte"}, {"Compare", Func, 0, "func(a []byte, b []byte) int"}, {"Contains", Func, 0, "func(b []byte, subslice []byte) bool"}, {"ContainsAny", Func, 7, "func(b []byte, chars string) bool"}, {"ContainsFunc", Func, 21, "func(b []byte, f func(rune) bool) bool"}, {"ContainsRune", Func, 7, "func(b []byte, r rune) bool"}, {"Count", Func, 0, "func(s []byte, sep []byte) int"}, {"Cut", Func, 18, "func(s []byte, sep []byte) (before []byte, after []byte, found bool)"}, {"CutPrefix", Func, 20, "func(s []byte, prefix []byte) (after []byte, found bool)"}, {"CutSuffix", Func, 20, "func(s []byte, suffix []byte) (before []byte, found bool)"}, {"Equal", Func, 0, "func(a []byte, b []byte) bool"}, {"EqualFold", Func, 0, "func(s []byte, t []byte) bool"}, {"ErrTooLarge", Var, 0, ""}, {"Fields", Func, 0, "func(s []byte) [][]byte"}, {"FieldsFunc", Func, 0, "func(s []byte, f func(rune) bool) [][]byte"}, {"FieldsFuncSeq", Func, 24, "func(s []byte, f func(rune) bool) iter.Seq[[]byte]"}, {"FieldsSeq", Func, 24, "func(s []byte) iter.Seq[[]byte]"}, {"HasPrefix", Func, 0, "func(s []byte, prefix []byte) bool"}, {"HasSuffix", Func, 0, "func(s []byte, suffix []byte) bool"}, {"Index", Func, 0, "func(s []byte, sep []byte) int"}, {"IndexAny", Func, 0, "func(s []byte, chars string) int"}, {"IndexByte", Func, 0, "func(b []byte, c byte) int"}, {"IndexFunc", Func, 0, "func(s []byte, f func(r rune) bool) int"}, {"IndexRune", Func, 0, "func(s []byte, r rune) int"}, {"Join", Func, 0, "func(s [][]byte, sep []byte) []byte"}, {"LastIndex", Func, 0, "func(s []byte, sep []byte) int"}, {"LastIndexAny", Func, 0, "func(s []byte, chars string) int"}, {"LastIndexByte", Func, 5, "func(s []byte, c byte) int"}, {"LastIndexFunc", Func, 0, "func(s []byte, f func(r rune) bool) int"}, {"Lines", Func, 24, "func(s []byte) iter.Seq[[]byte]"}, {"Map", Func, 0, "func(mapping func(r rune) rune, s []byte) []byte"}, {"MinRead", Const, 0, ""}, {"NewBuffer", Func, 0, "func(buf []byte) *Buffer"}, {"NewBufferString", Func, 0, "func(s string) *Buffer"}, {"NewReader", Func, 0, "func(b []byte) *Reader"}, {"Reader", Type, 0, ""}, {"Repeat", Func, 0, "func(b []byte, count int) []byte"}, {"Replace", Func, 0, "func(s []byte, old []byte, new []byte, n int) []byte"}, {"ReplaceAll", Func, 12, "func(s []byte, old []byte, new []byte) []byte"}, {"Runes", Func, 0, "func(s []byte) []rune"}, {"Split", Func, 0, "func(s []byte, sep []byte) [][]byte"}, {"SplitAfter", Func, 0, "func(s []byte, sep []byte) [][]byte"}, {"SplitAfterN", Func, 0, "func(s []byte, sep []byte, n int) [][]byte"}, {"SplitAfterSeq", Func, 24, "func(s []byte, sep []byte) iter.Seq[[]byte]"}, {"SplitN", Func, 0, "func(s []byte, sep []byte, n int) [][]byte"}, {"SplitSeq", Func, 24, "func(s []byte, sep []byte) iter.Seq[[]byte]"}, {"Title", Func, 0, "func(s []byte) []byte"}, {"ToLower", Func, 0, "func(s []byte) []byte"}, {"ToLowerSpecial", Func, 0, "func(c unicode.SpecialCase, s []byte) []byte"}, {"ToTitle", Func, 0, "func(s []byte) []byte"}, {"ToTitleSpecial", Func, 0, "func(c unicode.SpecialCase, s []byte) []byte"}, {"ToUpper", Func, 0, "func(s []byte) []byte"}, {"ToUpperSpecial", Func, 0, "func(c unicode.SpecialCase, s []byte) []byte"}, {"ToValidUTF8", Func, 13, "func(s []byte, replacement []byte) []byte"}, {"Trim", Func, 0, "func(s []byte, cutset string) []byte"}, {"TrimFunc", Func, 0, "func(s []byte, f func(r rune) bool) []byte"}, {"TrimLeft", Func, 0, "func(s []byte, cutset string) []byte"}, {"TrimLeftFunc", Func, 0, "func(s []byte, f func(r rune) bool) []byte"}, {"TrimPrefix", Func, 1, "func(s []byte, prefix []byte) []byte"}, {"TrimRight", Func, 0, "func(s []byte, cutset string) []byte"}, {"TrimRightFunc", Func, 0, "func(s []byte, f func(r rune) bool) []byte"}, {"TrimSpace", Func, 0, "func(s []byte) []byte"}, {"TrimSuffix", Func, 1, "func(s []byte, suffix []byte) []byte"}, }, "cmp": { {"Compare", Func, 21, "func[T Ordered](x T, y T) int"}, {"Less", Func, 21, "func[T Ordered](x T, y T) bool"}, {"Or", Func, 22, "func[T comparable](vals ...T) T"}, {"Ordered", Type, 21, ""}, }, "compress/bzip2": { {"(StructuralError).Error", Method, 0, ""}, {"NewReader", Func, 0, "func(r io.Reader) io.Reader"}, {"StructuralError", Type, 0, ""}, }, "compress/flate": { {"(*ReadError).Error", Method, 0, ""}, {"(*WriteError).Error", Method, 0, ""}, {"(*Writer).Close", Method, 0, ""}, {"(*Writer).Flush", Method, 0, ""}, {"(*Writer).Reset", Method, 2, ""}, {"(*Writer).Write", Method, 0, ""}, {"(CorruptInputError).Error", Method, 0, ""}, {"(InternalError).Error", Method, 0, ""}, {"BestCompression", Const, 0, ""}, {"BestSpeed", Const, 0, ""}, {"CorruptInputError", Type, 0, ""}, {"DefaultCompression", Const, 0, ""}, {"HuffmanOnly", Const, 7, ""}, {"InternalError", Type, 0, ""}, {"NewReader", Func, 0, "func(r io.Reader) io.ReadCloser"}, {"NewReaderDict", Func, 0, "func(r io.Reader, dict []byte) io.ReadCloser"}, {"NewWriter", Func, 0, "func(w io.Writer, level int) (*Writer, error)"}, {"NewWriterDict", Func, 0, "func(w io.Writer, level int, dict []byte) (*Writer, error)"}, {"NoCompression", Const, 0, ""}, {"ReadError", Type, 0, ""}, {"ReadError.Err", Field, 0, ""}, {"ReadError.Offset", Field, 0, ""}, {"Reader", Type, 0, ""}, {"Resetter", Type, 4, ""}, {"WriteError", Type, 0, ""}, {"WriteError.Err", Field, 0, ""}, {"WriteError.Offset", Field, 0, ""}, {"Writer", Type, 0, ""}, }, "compress/gzip": { {"(*Reader).Close", Method, 0, ""}, {"(*Reader).Multistream", Method, 4, ""}, {"(*Reader).Read", Method, 0, ""}, {"(*Reader).Reset", Method, 3, ""}, {"(*Writer).Close", Method, 0, ""}, {"(*Writer).Flush", Method, 1, ""}, {"(*Writer).Reset", Method, 2, ""}, {"(*Writer).Write", Method, 0, ""}, {"BestCompression", Const, 0, ""}, {"BestSpeed", Const, 0, ""}, {"DefaultCompression", Const, 0, ""}, {"ErrChecksum", Var, 0, ""}, {"ErrHeader", Var, 0, ""}, {"Header", Type, 0, ""}, {"Header.Comment", Field, 0, ""}, {"Header.Extra", Field, 0, ""}, {"Header.ModTime", Field, 0, ""}, {"Header.Name", Field, 0, ""}, {"Header.OS", Field, 0, ""}, {"HuffmanOnly", Const, 8, ""}, {"NewReader", Func, 0, "func(r io.Reader) (*Reader, error)"}, {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, {"NewWriterLevel", Func, 0, "func(w io.Writer, level int) (*Writer, error)"}, {"NoCompression", Const, 0, ""}, {"Reader", Type, 0, ""}, {"Reader.Header", Field, 0, ""}, {"Writer", Type, 0, ""}, {"Writer.Header", Field, 0, ""}, }, "compress/lzw": { {"(*Reader).Close", Method, 17, ""}, {"(*Reader).Read", Method, 17, ""}, {"(*Reader).Reset", Method, 17, ""}, {"(*Writer).Close", Method, 17, ""}, {"(*Writer).Reset", Method, 17, ""}, {"(*Writer).Write", Method, 17, ""}, {"LSB", Const, 0, ""}, {"MSB", Const, 0, ""}, {"NewReader", Func, 0, "func(r io.Reader, order Order, litWidth int) io.ReadCloser"}, {"NewWriter", Func, 0, "func(w io.Writer, order Order, litWidth int) io.WriteCloser"}, {"Order", Type, 0, ""}, {"Reader", Type, 17, ""}, {"Writer", Type, 17, ""}, }, "compress/zlib": { {"(*Writer).Close", Method, 0, ""}, {"(*Writer).Flush", Method, 0, ""}, {"(*Writer).Reset", Method, 2, ""}, {"(*Writer).Write", Method, 0, ""}, {"BestCompression", Const, 0, ""}, {"BestSpeed", Const, 0, ""}, {"DefaultCompression", Const, 0, ""}, {"ErrChecksum", Var, 0, ""}, {"ErrDictionary", Var, 0, ""}, {"ErrHeader", Var, 0, ""}, {"HuffmanOnly", Const, 8, ""}, {"NewReader", Func, 0, "func(r io.Reader) (io.ReadCloser, error)"}, {"NewReaderDict", Func, 0, "func(r io.Reader, dict []byte) (io.ReadCloser, error)"}, {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, {"NewWriterLevel", Func, 0, "func(w io.Writer, level int) (*Writer, error)"}, {"NewWriterLevelDict", Func, 0, "func(w io.Writer, level int, dict []byte) (*Writer, error)"}, {"NoCompression", Const, 0, ""}, {"Resetter", Type, 4, ""}, {"Writer", Type, 0, ""}, }, "container/heap": { {"Fix", Func, 2, "func(h Interface, i int)"}, {"Init", Func, 0, "func(h Interface)"}, {"Interface", Type, 0, ""}, {"Pop", Func, 0, "func(h Interface) any"}, {"Push", Func, 0, "func(h Interface, x any)"}, {"Remove", Func, 0, "func(h Interface, i int) any"}, }, "container/list": { {"(*Element).Next", Method, 0, ""}, {"(*Element).Prev", Method, 0, ""}, {"(*List).Back", Method, 0, ""}, {"(*List).Front", Method, 0, ""}, {"(*List).Init", Method, 0, ""}, {"(*List).InsertAfter", Method, 0, ""}, {"(*List).InsertBefore", Method, 0, ""}, {"(*List).Len", Method, 0, ""}, {"(*List).MoveAfter", Method, 2, ""}, {"(*List).MoveBefore", Method, 2, ""}, {"(*List).MoveToBack", Method, 0, ""}, {"(*List).MoveToFront", Method, 0, ""}, {"(*List).PushBack", Method, 0, ""}, {"(*List).PushBackList", Method, 0, ""}, {"(*List).PushFront", Method, 0, ""}, {"(*List).PushFrontList", Method, 0, ""}, {"(*List).Remove", Method, 0, ""}, {"Element", Type, 0, ""}, {"Element.Value", Field, 0, ""}, {"List", Type, 0, ""}, {"New", Func, 0, "func() *List"}, }, "container/ring": { {"(*Ring).Do", Method, 0, ""}, {"(*Ring).Len", Method, 0, ""}, {"(*Ring).Link", Method, 0, ""}, {"(*Ring).Move", Method, 0, ""}, {"(*Ring).Next", Method, 0, ""}, {"(*Ring).Prev", Method, 0, ""}, {"(*Ring).Unlink", Method, 0, ""}, {"New", Func, 0, "func(n int) *Ring"}, {"Ring", Type, 0, ""}, {"Ring.Value", Field, 0, ""}, }, "context": { {"AfterFunc", Func, 21, "func(ctx Context, f func()) (stop func() bool)"}, {"Background", Func, 7, "func() Context"}, {"CancelCauseFunc", Type, 20, ""}, {"CancelFunc", Type, 7, ""}, {"Canceled", Var, 7, ""}, {"Cause", Func, 20, "func(c Context) error"}, {"Context", Type, 7, ""}, {"DeadlineExceeded", Var, 7, ""}, {"TODO", Func, 7, "func() Context"}, {"WithCancel", Func, 7, "func(parent Context) (ctx Context, cancel CancelFunc)"}, {"WithCancelCause", Func, 20, "func(parent Context) (ctx Context, cancel CancelCauseFunc)"}, {"WithDeadline", Func, 7, "func(parent Context, d time.Time) (Context, CancelFunc)"}, {"WithDeadlineCause", Func, 21, "func(parent Context, d time.Time, cause error) (Context, CancelFunc)"}, {"WithTimeout", Func, 7, "func(parent Context, timeout time.Duration) (Context, CancelFunc)"}, {"WithTimeoutCause", Func, 21, "func(parent Context, timeout time.Duration, cause error) (Context, CancelFunc)"}, {"WithValue", Func, 7, "func(parent Context, key any, val any) Context"}, {"WithoutCancel", Func, 21, "func(parent Context) Context"}, }, "crypto": { {"(Hash).Available", Method, 0, ""}, {"(Hash).HashFunc", Method, 4, ""}, {"(Hash).New", Method, 0, ""}, {"(Hash).Size", Method, 0, ""}, {"(Hash).String", Method, 15, ""}, {"BLAKE2b_256", Const, 9, ""}, {"BLAKE2b_384", Const, 9, ""}, {"BLAKE2b_512", Const, 9, ""}, {"BLAKE2s_256", Const, 9, ""}, {"Decrypter", Type, 5, ""}, {"DecrypterOpts", Type, 5, ""}, {"Hash", Type, 0, ""}, {"MD4", Const, 0, ""}, {"MD5", Const, 0, ""}, {"MD5SHA1", Const, 0, ""}, {"PrivateKey", Type, 0, ""}, {"PublicKey", Type, 2, ""}, {"RIPEMD160", Const, 0, ""}, {"RegisterHash", Func, 0, "func(h Hash, f func() hash.Hash)"}, {"SHA1", Const, 0, ""}, {"SHA224", Const, 0, ""}, {"SHA256", Const, 0, ""}, {"SHA384", Const, 0, ""}, {"SHA3_224", Const, 4, ""}, {"SHA3_256", Const, 4, ""}, {"SHA3_384", Const, 4, ""}, {"SHA3_512", Const, 4, ""}, {"SHA512", Const, 0, ""}, {"SHA512_224", Const, 5, ""}, {"SHA512_256", Const, 5, ""}, {"Signer", Type, 4, ""}, {"SignerOpts", Type, 4, ""}, }, "crypto/aes": { {"(KeySizeError).Error", Method, 0, ""}, {"BlockSize", Const, 0, ""}, {"KeySizeError", Type, 0, ""}, {"NewCipher", Func, 0, "func(key []byte) (cipher.Block, error)"}, }, "crypto/cipher": { {"(StreamReader).Read", Method, 0, ""}, {"(StreamWriter).Close", Method, 0, ""}, {"(StreamWriter).Write", Method, 0, ""}, {"AEAD", Type, 2, ""}, {"Block", Type, 0, ""}, {"BlockMode", Type, 0, ""}, {"NewCBCDecrypter", Func, 0, "func(b Block, iv []byte) BlockMode"}, {"NewCBCEncrypter", Func, 0, "func(b Block, iv []byte) BlockMode"}, {"NewCFBDecrypter", Func, 0, "func(block Block, iv []byte) Stream"}, {"NewCFBEncrypter", Func, 0, "func(block Block, iv []byte) Stream"}, {"NewCTR", Func, 0, "func(block Block, iv []byte) Stream"}, {"NewGCM", Func, 2, "func(cipher Block) (AEAD, error)"}, {"NewGCMWithNonceSize", Func, 5, "func(cipher Block, size int) (AEAD, error)"}, {"NewGCMWithRandomNonce", Func, 24, "func(cipher Block) (AEAD, error)"}, {"NewGCMWithTagSize", Func, 11, "func(cipher Block, tagSize int) (AEAD, error)"}, {"NewOFB", Func, 0, "func(b Block, iv []byte) Stream"}, {"Stream", Type, 0, ""}, {"StreamReader", Type, 0, ""}, {"StreamReader.R", Field, 0, ""}, {"StreamReader.S", Field, 0, ""}, {"StreamWriter", Type, 0, ""}, {"StreamWriter.Err", Field, 0, ""}, {"StreamWriter.S", Field, 0, ""}, {"StreamWriter.W", Field, 0, ""}, }, "crypto/des": { {"(KeySizeError).Error", Method, 0, ""}, {"BlockSize", Const, 0, ""}, {"KeySizeError", Type, 0, ""}, {"NewCipher", Func, 0, "func(key []byte) (cipher.Block, error)"}, {"NewTripleDESCipher", Func, 0, "func(key []byte) (cipher.Block, error)"}, }, "crypto/dsa": { {"ErrInvalidPublicKey", Var, 0, ""}, {"GenerateKey", Func, 0, "func(priv *PrivateKey, rand io.Reader) error"}, {"GenerateParameters", Func, 0, "func(params *Parameters, rand io.Reader, sizes ParameterSizes) error"}, {"L1024N160", Const, 0, ""}, {"L2048N224", Const, 0, ""}, {"L2048N256", Const, 0, ""}, {"L3072N256", Const, 0, ""}, {"ParameterSizes", Type, 0, ""}, {"Parameters", Type, 0, ""}, {"Parameters.G", Field, 0, ""}, {"Parameters.P", Field, 0, ""}, {"Parameters.Q", Field, 0, ""}, {"PrivateKey", Type, 0, ""}, {"PrivateKey.PublicKey", Field, 0, ""}, {"PrivateKey.X", Field, 0, ""}, {"PublicKey", Type, 0, ""}, {"PublicKey.Parameters", Field, 0, ""}, {"PublicKey.Y", Field, 0, ""}, {"Sign", Func, 0, "func(rand io.Reader, priv *PrivateKey, hash []byte) (r *big.Int, s *big.Int, err error)"}, {"Verify", Func, 0, "func(pub *PublicKey, hash []byte, r *big.Int, s *big.Int) bool"}, }, "crypto/ecdh": { {"(*PrivateKey).Bytes", Method, 20, ""}, {"(*PrivateKey).Curve", Method, 20, ""}, {"(*PrivateKey).ECDH", Method, 20, ""}, {"(*PrivateKey).Equal", Method, 20, ""}, {"(*PrivateKey).Public", Method, 20, ""}, {"(*PrivateKey).PublicKey", Method, 20, ""}, {"(*PublicKey).Bytes", Method, 20, ""}, {"(*PublicKey).Curve", Method, 20, ""}, {"(*PublicKey).Equal", Method, 20, ""}, {"Curve", Type, 20, ""}, {"P256", Func, 20, "func() Curve"}, {"P384", Func, 20, "func() Curve"}, {"P521", Func, 20, "func() Curve"}, {"PrivateKey", Type, 20, ""}, {"PublicKey", Type, 20, ""}, {"X25519", Func, 20, "func() Curve"}, }, "crypto/ecdsa": { {"(*PrivateKey).ECDH", Method, 20, ""}, {"(*PrivateKey).Equal", Method, 15, ""}, {"(*PrivateKey).Public", Method, 4, ""}, {"(*PrivateKey).Sign", Method, 4, ""}, {"(*PublicKey).ECDH", Method, 20, ""}, {"(*PublicKey).Equal", Method, 15, ""}, {"(PrivateKey).Add", Method, 0, ""}, {"(PrivateKey).Double", Method, 0, ""}, {"(PrivateKey).IsOnCurve", Method, 0, ""}, {"(PrivateKey).Params", Method, 0, ""}, {"(PrivateKey).ScalarBaseMult", Method, 0, ""}, {"(PrivateKey).ScalarMult", Method, 0, ""}, {"(PublicKey).Add", Method, 0, ""}, {"(PublicKey).Double", Method, 0, ""}, {"(PublicKey).IsOnCurve", Method, 0, ""}, {"(PublicKey).Params", Method, 0, ""}, {"(PublicKey).ScalarBaseMult", Method, 0, ""}, {"(PublicKey).ScalarMult", Method, 0, ""}, {"GenerateKey", Func, 0, "func(c elliptic.Curve, rand io.Reader) (*PrivateKey, error)"}, {"PrivateKey", Type, 0, ""}, {"PrivateKey.D", Field, 0, ""}, {"PrivateKey.PublicKey", Field, 0, ""}, {"PublicKey", Type, 0, ""}, {"PublicKey.Curve", Field, 0, ""}, {"PublicKey.X", Field, 0, ""}, {"PublicKey.Y", Field, 0, ""}, {"Sign", Func, 0, "func(rand io.Reader, priv *PrivateKey, hash []byte) (r *big.Int, s *big.Int, err error)"}, {"SignASN1", Func, 15, "func(rand io.Reader, priv *PrivateKey, hash []byte) ([]byte, error)"}, {"Verify", Func, 0, "func(pub *PublicKey, hash []byte, r *big.Int, s *big.Int) bool"}, {"VerifyASN1", Func, 15, "func(pub *PublicKey, hash []byte, sig []byte) bool"}, }, "crypto/ed25519": { {"(*Options).HashFunc", Method, 20, ""}, {"(PrivateKey).Equal", Method, 15, ""}, {"(PrivateKey).Public", Method, 13, ""}, {"(PrivateKey).Seed", Method, 13, ""}, {"(PrivateKey).Sign", Method, 13, ""}, {"(PublicKey).Equal", Method, 15, ""}, {"GenerateKey", Func, 13, "func(rand io.Reader) (PublicKey, PrivateKey, error)"}, {"NewKeyFromSeed", Func, 13, "func(seed []byte) PrivateKey"}, {"Options", Type, 20, ""}, {"Options.Context", Field, 20, ""}, {"Options.Hash", Field, 20, ""}, {"PrivateKey", Type, 13, ""}, {"PrivateKeySize", Const, 13, ""}, {"PublicKey", Type, 13, ""}, {"PublicKeySize", Const, 13, ""}, {"SeedSize", Const, 13, ""}, {"Sign", Func, 13, "func(privateKey PrivateKey, message []byte) []byte"}, {"SignatureSize", Const, 13, ""}, {"Verify", Func, 13, "func(publicKey PublicKey, message []byte, sig []byte) bool"}, {"VerifyWithOptions", Func, 20, "func(publicKey PublicKey, message []byte, sig []byte, opts *Options) error"}, }, "crypto/elliptic": { {"(*CurveParams).Add", Method, 0, ""}, {"(*CurveParams).Double", Method, 0, ""}, {"(*CurveParams).IsOnCurve", Method, 0, ""}, {"(*CurveParams).Params", Method, 0, ""}, {"(*CurveParams).ScalarBaseMult", Method, 0, ""}, {"(*CurveParams).ScalarMult", Method, 0, ""}, {"Curve", Type, 0, ""}, {"CurveParams", Type, 0, ""}, {"CurveParams.B", Field, 0, ""}, {"CurveParams.BitSize", Field, 0, ""}, {"CurveParams.Gx", Field, 0, ""}, {"CurveParams.Gy", Field, 0, ""}, {"CurveParams.N", Field, 0, ""}, {"CurveParams.Name", Field, 5, ""}, {"CurveParams.P", Field, 0, ""}, {"GenerateKey", Func, 0, "func(curve Curve, rand io.Reader) (priv []byte, x *big.Int, y *big.Int, err error)"}, {"Marshal", Func, 0, "func(curve Curve, x *big.Int, y *big.Int) []byte"}, {"MarshalCompressed", Func, 15, "func(curve Curve, x *big.Int, y *big.Int) []byte"}, {"P224", Func, 0, "func() Curve"}, {"P256", Func, 0, "func() Curve"}, {"P384", Func, 0, "func() Curve"}, {"P521", Func, 0, "func() Curve"}, {"Unmarshal", Func, 0, "func(curve Curve, data []byte) (x *big.Int, y *big.Int)"}, {"UnmarshalCompressed", Func, 15, "func(curve Curve, data []byte) (x *big.Int, y *big.Int)"}, }, "crypto/fips140": { {"Enabled", Func, 24, "func() bool"}, }, "crypto/hkdf": { {"Expand", Func, 24, "func[H hash.Hash](h func() H, pseudorandomKey []byte, info string, keyLength int) ([]byte, error)"}, {"Extract", Func, 24, "func[H hash.Hash](h func() H, secret []byte, salt []byte) ([]byte, error)"}, {"Key", Func, 24, "func[Hash hash.Hash](h func() Hash, secret []byte, salt []byte, info string, keyLength int) ([]byte, error)"}, }, "crypto/hmac": { {"Equal", Func, 1, "func(mac1 []byte, mac2 []byte) bool"}, {"New", Func, 0, "func(h func() hash.Hash, key []byte) hash.Hash"}, }, "crypto/md5": { {"BlockSize", Const, 0, ""}, {"New", Func, 0, "func() hash.Hash"}, {"Size", Const, 0, ""}, {"Sum", Func, 2, "func(data []byte) [16]byte"}, }, "crypto/mlkem": { {"(*DecapsulationKey1024).Bytes", Method, 24, ""}, {"(*DecapsulationKey1024).Decapsulate", Method, 24, ""}, {"(*DecapsulationKey1024).EncapsulationKey", Method, 24, ""}, {"(*DecapsulationKey768).Bytes", Method, 24, ""}, {"(*DecapsulationKey768).Decapsulate", Method, 24, ""}, {"(*DecapsulationKey768).EncapsulationKey", Method, 24, ""}, {"(*EncapsulationKey1024).Bytes", Method, 24, ""}, {"(*EncapsulationKey1024).Encapsulate", Method, 24, ""}, {"(*EncapsulationKey768).Bytes", Method, 24, ""}, {"(*EncapsulationKey768).Encapsulate", Method, 24, ""}, {"CiphertextSize1024", Const, 24, ""}, {"CiphertextSize768", Const, 24, ""}, {"DecapsulationKey1024", Type, 24, ""}, {"DecapsulationKey768", Type, 24, ""}, {"EncapsulationKey1024", Type, 24, ""}, {"EncapsulationKey768", Type, 24, ""}, {"EncapsulationKeySize1024", Const, 24, ""}, {"EncapsulationKeySize768", Const, 24, ""}, {"GenerateKey1024", Func, 24, "func() (*DecapsulationKey1024, error)"}, {"GenerateKey768", Func, 24, "func() (*DecapsulationKey768, error)"}, {"NewDecapsulationKey1024", Func, 24, "func(seed []byte) (*DecapsulationKey1024, error)"}, {"NewDecapsulationKey768", Func, 24, "func(seed []byte) (*DecapsulationKey768, error)"}, {"NewEncapsulationKey1024", Func, 24, "func(encapsulationKey []byte) (*EncapsulationKey1024, error)"}, {"NewEncapsulationKey768", Func, 24, "func(encapsulationKey []byte) (*EncapsulationKey768, error)"}, {"SeedSize", Const, 24, ""}, {"SharedKeySize", Const, 24, ""}, }, "crypto/pbkdf2": { {"Key", Func, 24, "func[Hash hash.Hash](h func() Hash, password string, salt []byte, iter int, keyLength int) ([]byte, error)"}, }, "crypto/rand": { {"Int", Func, 0, "func(rand io.Reader, max *big.Int) (n *big.Int, err error)"}, {"Prime", Func, 0, "func(rand io.Reader, bits int) (*big.Int, error)"}, {"Read", Func, 0, "func(b []byte) (n int, err error)"}, {"Reader", Var, 0, ""}, {"Text", Func, 24, "func() string"}, }, "crypto/rc4": { {"(*Cipher).Reset", Method, 0, ""}, {"(*Cipher).XORKeyStream", Method, 0, ""}, {"(KeySizeError).Error", Method, 0, ""}, {"Cipher", Type, 0, ""}, {"KeySizeError", Type, 0, ""}, {"NewCipher", Func, 0, "func(key []byte) (*Cipher, error)"}, }, "crypto/rsa": { {"(*PSSOptions).HashFunc", Method, 4, ""}, {"(*PrivateKey).Decrypt", Method, 5, ""}, {"(*PrivateKey).Equal", Method, 15, ""}, {"(*PrivateKey).Precompute", Method, 0, ""}, {"(*PrivateKey).Public", Method, 4, ""}, {"(*PrivateKey).Sign", Method, 4, ""}, {"(*PrivateKey).Size", Method, 11, ""}, {"(*PrivateKey).Validate", Method, 0, ""}, {"(*PublicKey).Equal", Method, 15, ""}, {"(*PublicKey).Size", Method, 11, ""}, {"CRTValue", Type, 0, ""}, {"CRTValue.Coeff", Field, 0, ""}, {"CRTValue.Exp", Field, 0, ""}, {"CRTValue.R", Field, 0, ""}, {"DecryptOAEP", Func, 0, "func(hash hash.Hash, random io.Reader, priv *PrivateKey, ciphertext []byte, label []byte) ([]byte, error)"}, {"DecryptPKCS1v15", Func, 0, "func(random io.Reader, priv *PrivateKey, ciphertext []byte) ([]byte, error)"}, {"DecryptPKCS1v15SessionKey", Func, 0, "func(random io.Reader, priv *PrivateKey, ciphertext []byte, key []byte) error"}, {"EncryptOAEP", Func, 0, "func(hash hash.Hash, random io.Reader, pub *PublicKey, msg []byte, label []byte) ([]byte, error)"}, {"EncryptPKCS1v15", Func, 0, "func(random io.Reader, pub *PublicKey, msg []byte) ([]byte, error)"}, {"ErrDecryption", Var, 0, ""}, {"ErrMessageTooLong", Var, 0, ""}, {"ErrVerification", Var, 0, ""}, {"GenerateKey", Func, 0, "func(random io.Reader, bits int) (*PrivateKey, error)"}, {"GenerateMultiPrimeKey", Func, 0, "func(random io.Reader, nprimes int, bits int) (*PrivateKey, error)"}, {"OAEPOptions", Type, 5, ""}, {"OAEPOptions.Hash", Field, 5, ""}, {"OAEPOptions.Label", Field, 5, ""}, {"OAEPOptions.MGFHash", Field, 20, ""}, {"PKCS1v15DecryptOptions", Type, 5, ""}, {"PKCS1v15DecryptOptions.SessionKeyLen", Field, 5, ""}, {"PSSOptions", Type, 2, ""}, {"PSSOptions.Hash", Field, 4, ""}, {"PSSOptions.SaltLength", Field, 2, ""}, {"PSSSaltLengthAuto", Const, 2, ""}, {"PSSSaltLengthEqualsHash", Const, 2, ""}, {"PrecomputedValues", Type, 0, ""}, {"PrecomputedValues.CRTValues", Field, 0, ""}, {"PrecomputedValues.Dp", Field, 0, ""}, {"PrecomputedValues.Dq", Field, 0, ""}, {"PrecomputedValues.Qinv", Field, 0, ""}, {"PrivateKey", Type, 0, ""}, {"PrivateKey.D", Field, 0, ""}, {"PrivateKey.Precomputed", Field, 0, ""}, {"PrivateKey.Primes", Field, 0, ""}, {"PrivateKey.PublicKey", Field, 0, ""}, {"PublicKey", Type, 0, ""}, {"PublicKey.E", Field, 0, ""}, {"PublicKey.N", Field, 0, ""}, {"SignPKCS1v15", Func, 0, "func(random io.Reader, priv *PrivateKey, hash crypto.Hash, hashed []byte) ([]byte, error)"}, {"SignPSS", Func, 2, "func(rand io.Reader, priv *PrivateKey, hash crypto.Hash, digest []byte, opts *PSSOptions) ([]byte, error)"}, {"VerifyPKCS1v15", Func, 0, "func(pub *PublicKey, hash crypto.Hash, hashed []byte, sig []byte) error"}, {"VerifyPSS", Func, 2, "func(pub *PublicKey, hash crypto.Hash, digest []byte, sig []byte, opts *PSSOptions) error"}, }, "crypto/sha1": { {"BlockSize", Const, 0, ""}, {"New", Func, 0, "func() hash.Hash"}, {"Size", Const, 0, ""}, {"Sum", Func, 2, "func(data []byte) [20]byte"}, }, "crypto/sha256": { {"BlockSize", Const, 0, ""}, {"New", Func, 0, "func() hash.Hash"}, {"New224", Func, 0, "func() hash.Hash"}, {"Size", Const, 0, ""}, {"Size224", Const, 0, ""}, {"Sum224", Func, 2, "func(data []byte) [28]byte"}, {"Sum256", Func, 2, "func(data []byte) [32]byte"}, }, "crypto/sha3": { {"(*SHA3).AppendBinary", Method, 24, ""}, {"(*SHA3).BlockSize", Method, 24, ""}, {"(*SHA3).MarshalBinary", Method, 24, ""}, {"(*SHA3).Reset", Method, 24, ""}, {"(*SHA3).Size", Method, 24, ""}, {"(*SHA3).Sum", Method, 24, ""}, {"(*SHA3).UnmarshalBinary", Method, 24, ""}, {"(*SHA3).Write", Method, 24, ""}, {"(*SHAKE).AppendBinary", Method, 24, ""}, {"(*SHAKE).BlockSize", Method, 24, ""}, {"(*SHAKE).MarshalBinary", Method, 24, ""}, {"(*SHAKE).Read", Method, 24, ""}, {"(*SHAKE).Reset", Method, 24, ""}, {"(*SHAKE).UnmarshalBinary", Method, 24, ""}, {"(*SHAKE).Write", Method, 24, ""}, {"New224", Func, 24, "func() *SHA3"}, {"New256", Func, 24, "func() *SHA3"}, {"New384", Func, 24, "func() *SHA3"}, {"New512", Func, 24, "func() *SHA3"}, {"NewCSHAKE128", Func, 24, "func(N []byte, S []byte) *SHAKE"}, {"NewCSHAKE256", Func, 24, "func(N []byte, S []byte) *SHAKE"}, {"NewSHAKE128", Func, 24, "func() *SHAKE"}, {"NewSHAKE256", Func, 24, "func() *SHAKE"}, {"SHA3", Type, 24, ""}, {"SHAKE", Type, 24, ""}, {"Sum224", Func, 24, "func(data []byte) [28]byte"}, {"Sum256", Func, 24, "func(data []byte) [32]byte"}, {"Sum384", Func, 24, "func(data []byte) [48]byte"}, {"Sum512", Func, 24, "func(data []byte) [64]byte"}, {"SumSHAKE128", Func, 24, "func(data []byte, length int) []byte"}, {"SumSHAKE256", Func, 24, "func(data []byte, length int) []byte"}, }, "crypto/sha512": { {"BlockSize", Const, 0, ""}, {"New", Func, 0, "func() hash.Hash"}, {"New384", Func, 0, "func() hash.Hash"}, {"New512_224", Func, 5, "func() hash.Hash"}, {"New512_256", Func, 5, "func() hash.Hash"}, {"Size", Const, 0, ""}, {"Size224", Const, 5, ""}, {"Size256", Const, 5, ""}, {"Size384", Const, 0, ""}, {"Sum384", Func, 2, "func(data []byte) [48]byte"}, {"Sum512", Func, 2, "func(data []byte) [64]byte"}, {"Sum512_224", Func, 5, "func(data []byte) [28]byte"}, {"Sum512_256", Func, 5, "func(data []byte) [32]byte"}, }, "crypto/subtle": { {"ConstantTimeByteEq", Func, 0, "func(x uint8, y uint8) int"}, {"ConstantTimeCompare", Func, 0, "func(x []byte, y []byte) int"}, {"ConstantTimeCopy", Func, 0, "func(v int, x []byte, y []byte)"}, {"ConstantTimeEq", Func, 0, "func(x int32, y int32) int"}, {"ConstantTimeLessOrEq", Func, 2, "func(x int, y int) int"}, {"ConstantTimeSelect", Func, 0, "func(v int, x int, y int) int"}, {"WithDataIndependentTiming", Func, 24, "func(f func())"}, {"XORBytes", Func, 20, "func(dst []byte, x []byte, y []byte) int"}, }, "crypto/tls": { {"(*CertificateRequestInfo).Context", Method, 17, ""}, {"(*CertificateRequestInfo).SupportsCertificate", Method, 14, ""}, {"(*CertificateVerificationError).Error", Method, 20, ""}, {"(*CertificateVerificationError).Unwrap", Method, 20, ""}, {"(*ClientHelloInfo).Context", Method, 17, ""}, {"(*ClientHelloInfo).SupportsCertificate", Method, 14, ""}, {"(*ClientSessionState).ResumptionState", Method, 21, ""}, {"(*Config).BuildNameToCertificate", Method, 0, ""}, {"(*Config).Clone", Method, 8, ""}, {"(*Config).DecryptTicket", Method, 21, ""}, {"(*Config).EncryptTicket", Method, 21, ""}, {"(*Config).SetSessionTicketKeys", Method, 5, ""}, {"(*Conn).Close", Method, 0, ""}, {"(*Conn).CloseWrite", Method, 8, ""}, {"(*Conn).ConnectionState", Method, 0, ""}, {"(*Conn).Handshake", Method, 0, ""}, {"(*Conn).HandshakeContext", Method, 17, ""}, {"(*Conn).LocalAddr", Method, 0, ""}, {"(*Conn).NetConn", Method, 18, ""}, {"(*Conn).OCSPResponse", Method, 0, ""}, {"(*Conn).Read", Method, 0, ""}, {"(*Conn).RemoteAddr", Method, 0, ""}, {"(*Conn).SetDeadline", Method, 0, ""}, {"(*Conn).SetReadDeadline", Method, 0, ""}, {"(*Conn).SetWriteDeadline", Method, 0, ""}, {"(*Conn).VerifyHostname", Method, 0, ""}, {"(*Conn).Write", Method, 0, ""}, {"(*ConnectionState).ExportKeyingMaterial", Method, 11, ""}, {"(*Dialer).Dial", Method, 15, ""}, {"(*Dialer).DialContext", Method, 15, ""}, {"(*ECHRejectionError).Error", Method, 23, ""}, {"(*QUICConn).Close", Method, 21, ""}, {"(*QUICConn).ConnectionState", Method, 21, ""}, {"(*QUICConn).HandleData", Method, 21, ""}, {"(*QUICConn).NextEvent", Method, 21, ""}, {"(*QUICConn).SendSessionTicket", Method, 21, ""}, {"(*QUICConn).SetTransportParameters", Method, 21, ""}, {"(*QUICConn).Start", Method, 21, ""}, {"(*QUICConn).StoreSession", Method, 23, ""}, {"(*SessionState).Bytes", Method, 21, ""}, {"(AlertError).Error", Method, 21, ""}, {"(ClientAuthType).String", Method, 15, ""}, {"(CurveID).String", Method, 15, ""}, {"(QUICEncryptionLevel).String", Method, 21, ""}, {"(RecordHeaderError).Error", Method, 6, ""}, {"(SignatureScheme).String", Method, 15, ""}, {"AlertError", Type, 21, ""}, {"Certificate", Type, 0, ""}, {"Certificate.Certificate", Field, 0, ""}, {"Certificate.Leaf", Field, 0, ""}, {"Certificate.OCSPStaple", Field, 0, ""}, {"Certificate.PrivateKey", Field, 0, ""}, {"Certificate.SignedCertificateTimestamps", Field, 5, ""}, {"Certificate.SupportedSignatureAlgorithms", Field, 14, ""}, {"CertificateRequestInfo", Type, 8, ""}, {"CertificateRequestInfo.AcceptableCAs", Field, 8, ""}, {"CertificateRequestInfo.SignatureSchemes", Field, 8, ""}, {"CertificateRequestInfo.Version", Field, 14, ""}, {"CertificateVerificationError", Type, 20, ""}, {"CertificateVerificationError.Err", Field, 20, ""}, {"CertificateVerificationError.UnverifiedCertificates", Field, 20, ""}, {"CipherSuite", Type, 14, ""}, {"CipherSuite.ID", Field, 14, ""}, {"CipherSuite.Insecure", Field, 14, ""}, {"CipherSuite.Name", Field, 14, ""}, {"CipherSuite.SupportedVersions", Field, 14, ""}, {"CipherSuiteName", Func, 14, "func(id uint16) string"}, {"CipherSuites", Func, 14, "func() []*CipherSuite"}, {"Client", Func, 0, "func(conn net.Conn, config *Config) *Conn"}, {"ClientAuthType", Type, 0, ""}, {"ClientHelloInfo", Type, 4, ""}, {"ClientHelloInfo.CipherSuites", Field, 4, ""}, {"ClientHelloInfo.Conn", Field, 8, ""}, {"ClientHelloInfo.Extensions", Field, 24, ""}, {"ClientHelloInfo.ServerName", Field, 4, ""}, {"ClientHelloInfo.SignatureSchemes", Field, 8, ""}, {"ClientHelloInfo.SupportedCurves", Field, 4, ""}, {"ClientHelloInfo.SupportedPoints", Field, 4, ""}, {"ClientHelloInfo.SupportedProtos", Field, 8, ""}, {"ClientHelloInfo.SupportedVersions", Field, 8, ""}, {"ClientSessionCache", Type, 3, ""}, {"ClientSessionState", Type, 3, ""}, {"Config", Type, 0, ""}, {"Config.Certificates", Field, 0, ""}, {"Config.CipherSuites", Field, 0, ""}, {"Config.ClientAuth", Field, 0, ""}, {"Config.ClientCAs", Field, 0, ""}, {"Config.ClientSessionCache", Field, 3, ""}, {"Config.CurvePreferences", Field, 3, ""}, {"Config.DynamicRecordSizingDisabled", Field, 7, ""}, {"Config.EncryptedClientHelloConfigList", Field, 23, ""}, {"Config.EncryptedClientHelloKeys", Field, 24, ""}, {"Config.EncryptedClientHelloRejectionVerify", Field, 23, ""}, {"Config.GetCertificate", Field, 4, ""}, {"Config.GetClientCertificate", Field, 8, ""}, {"Config.GetConfigForClient", Field, 8, ""}, {"Config.InsecureSkipVerify", Field, 0, ""}, {"Config.KeyLogWriter", Field, 8, ""}, {"Config.MaxVersion", Field, 2, ""}, {"Config.MinVersion", Field, 2, ""}, {"Config.NameToCertificate", Field, 0, ""}, {"Config.NextProtos", Field, 0, ""}, {"Config.PreferServerCipherSuites", Field, 1, ""}, {"Config.Rand", Field, 0, ""}, {"Config.Renegotiation", Field, 7, ""}, {"Config.RootCAs", Field, 0, ""}, {"Config.ServerName", Field, 0, ""}, {"Config.SessionTicketKey", Field, 1, ""}, {"Config.SessionTicketsDisabled", Field, 1, ""}, {"Config.Time", Field, 0, ""}, {"Config.UnwrapSession", Field, 21, ""}, {"Config.VerifyConnection", Field, 15, ""}, {"Config.VerifyPeerCertificate", Field, 8, ""}, {"Config.WrapSession", Field, 21, ""}, {"Conn", Type, 0, ""}, {"ConnectionState", Type, 0, ""}, {"ConnectionState.CipherSuite", Field, 0, ""}, {"ConnectionState.CurveID", Field, 25, ""}, {"ConnectionState.DidResume", Field, 1, ""}, {"ConnectionState.ECHAccepted", Field, 23, ""}, {"ConnectionState.HandshakeComplete", Field, 0, ""}, {"ConnectionState.NegotiatedProtocol", Field, 0, ""}, {"ConnectionState.NegotiatedProtocolIsMutual", Field, 0, ""}, {"ConnectionState.OCSPResponse", Field, 5, ""}, {"ConnectionState.PeerCertificates", Field, 0, ""}, {"ConnectionState.ServerName", Field, 0, ""}, {"ConnectionState.SignedCertificateTimestamps", Field, 5, ""}, {"ConnectionState.TLSUnique", Field, 4, ""}, {"ConnectionState.VerifiedChains", Field, 0, ""}, {"ConnectionState.Version", Field, 3, ""}, {"CurveID", Type, 3, ""}, {"CurveP256", Const, 3, ""}, {"CurveP384", Const, 3, ""}, {"CurveP521", Const, 3, ""}, {"Dial", Func, 0, "func(network string, addr string, config *Config) (*Conn, error)"}, {"DialWithDialer", Func, 3, "func(dialer *net.Dialer, network string, addr string, config *Config) (*Conn, error)"}, {"Dialer", Type, 15, ""}, {"Dialer.Config", Field, 15, ""}, {"Dialer.NetDialer", Field, 15, ""}, {"ECDSAWithP256AndSHA256", Const, 8, ""}, {"ECDSAWithP384AndSHA384", Const, 8, ""}, {"ECDSAWithP521AndSHA512", Const, 8, ""}, {"ECDSAWithSHA1", Const, 10, ""}, {"ECHRejectionError", Type, 23, ""}, {"ECHRejectionError.RetryConfigList", Field, 23, ""}, {"Ed25519", Const, 13, ""}, {"EncryptedClientHelloKey", Type, 24, ""}, {"EncryptedClientHelloKey.Config", Field, 24, ""}, {"EncryptedClientHelloKey.PrivateKey", Field, 24, ""}, {"EncryptedClientHelloKey.SendAsRetry", Field, 24, ""}, {"InsecureCipherSuites", Func, 14, "func() []*CipherSuite"}, {"Listen", Func, 0, "func(network string, laddr string, config *Config) (net.Listener, error)"}, {"LoadX509KeyPair", Func, 0, "func(certFile string, keyFile string) (Certificate, error)"}, {"NewLRUClientSessionCache", Func, 3, "func(capacity int) ClientSessionCache"}, {"NewListener", Func, 0, "func(inner net.Listener, config *Config) net.Listener"}, {"NewResumptionState", Func, 21, "func(ticket []byte, state *SessionState) (*ClientSessionState, error)"}, {"NoClientCert", Const, 0, ""}, {"PKCS1WithSHA1", Const, 8, ""}, {"PKCS1WithSHA256", Const, 8, ""}, {"PKCS1WithSHA384", Const, 8, ""}, {"PKCS1WithSHA512", Const, 8, ""}, {"PSSWithSHA256", Const, 8, ""}, {"PSSWithSHA384", Const, 8, ""}, {"PSSWithSHA512", Const, 8, ""}, {"ParseSessionState", Func, 21, "func(data []byte) (*SessionState, error)"}, {"QUICClient", Func, 21, "func(config *QUICConfig) *QUICConn"}, {"QUICConfig", Type, 21, ""}, {"QUICConfig.EnableSessionEvents", Field, 23, ""}, {"QUICConfig.TLSConfig", Field, 21, ""}, {"QUICConn", Type, 21, ""}, {"QUICEncryptionLevel", Type, 21, ""}, {"QUICEncryptionLevelApplication", Const, 21, ""}, {"QUICEncryptionLevelEarly", Const, 21, ""}, {"QUICEncryptionLevelHandshake", Const, 21, ""}, {"QUICEncryptionLevelInitial", Const, 21, ""}, {"QUICEvent", Type, 21, ""}, {"QUICEvent.Data", Field, 21, ""}, {"QUICEvent.Kind", Field, 21, ""}, {"QUICEvent.Level", Field, 21, ""}, {"QUICEvent.SessionState", Field, 23, ""}, {"QUICEvent.Suite", Field, 21, ""}, {"QUICEventKind", Type, 21, ""}, {"QUICHandshakeDone", Const, 21, ""}, {"QUICNoEvent", Const, 21, ""}, {"QUICRejectedEarlyData", Const, 21, ""}, {"QUICResumeSession", Const, 23, ""}, {"QUICServer", Func, 21, "func(config *QUICConfig) *QUICConn"}, {"QUICSessionTicketOptions", Type, 21, ""}, {"QUICSessionTicketOptions.EarlyData", Field, 21, ""}, {"QUICSessionTicketOptions.Extra", Field, 23, ""}, {"QUICSetReadSecret", Const, 21, ""}, {"QUICSetWriteSecret", Const, 21, ""}, {"QUICStoreSession", Const, 23, ""}, {"QUICTransportParameters", Const, 21, ""}, {"QUICTransportParametersRequired", Const, 21, ""}, {"QUICWriteData", Const, 21, ""}, {"RecordHeaderError", Type, 6, ""}, {"RecordHeaderError.Conn", Field, 12, ""}, {"RecordHeaderError.Msg", Field, 6, ""}, {"RecordHeaderError.RecordHeader", Field, 6, ""}, {"RenegotiateFreelyAsClient", Const, 7, ""}, {"RenegotiateNever", Const, 7, ""}, {"RenegotiateOnceAsClient", Const, 7, ""}, {"RenegotiationSupport", Type, 7, ""}, {"RequestClientCert", Const, 0, ""}, {"RequireAndVerifyClientCert", Const, 0, ""}, {"RequireAnyClientCert", Const, 0, ""}, {"Server", Func, 0, "func(conn net.Conn, config *Config) *Conn"}, {"SessionState", Type, 21, ""}, {"SessionState.EarlyData", Field, 21, ""}, {"SessionState.Extra", Field, 21, ""}, {"SignatureScheme", Type, 8, ""}, {"TLS_AES_128_GCM_SHA256", Const, 12, ""}, {"TLS_AES_256_GCM_SHA384", Const, 12, ""}, {"TLS_CHACHA20_POLY1305_SHA256", Const, 12, ""}, {"TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA", Const, 2, ""}, {"TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256", Const, 8, ""}, {"TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256", Const, 2, ""}, {"TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA", Const, 2, ""}, {"TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384", Const, 5, ""}, {"TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305", Const, 8, ""}, {"TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256", Const, 14, ""}, {"TLS_ECDHE_ECDSA_WITH_RC4_128_SHA", Const, 2, ""}, {"TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA", Const, 0, ""}, {"TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA", Const, 0, ""}, {"TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256", Const, 8, ""}, {"TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256", Const, 2, ""}, {"TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA", Const, 1, ""}, {"TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384", Const, 5, ""}, {"TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305", Const, 8, ""}, {"TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256", Const, 14, ""}, {"TLS_ECDHE_RSA_WITH_RC4_128_SHA", Const, 0, ""}, {"TLS_FALLBACK_SCSV", Const, 4, ""}, {"TLS_RSA_WITH_3DES_EDE_CBC_SHA", Const, 0, ""}, {"TLS_RSA_WITH_AES_128_CBC_SHA", Const, 0, ""}, {"TLS_RSA_WITH_AES_128_CBC_SHA256", Const, 8, ""}, {"TLS_RSA_WITH_AES_128_GCM_SHA256", Const, 6, ""}, {"TLS_RSA_WITH_AES_256_CBC_SHA", Const, 1, ""}, {"TLS_RSA_WITH_AES_256_GCM_SHA384", Const, 6, ""}, {"TLS_RSA_WITH_RC4_128_SHA", Const, 0, ""}, {"VerifyClientCertIfGiven", Const, 0, ""}, {"VersionName", Func, 21, "func(version uint16) string"}, {"VersionSSL30", Const, 2, ""}, {"VersionTLS10", Const, 2, ""}, {"VersionTLS11", Const, 2, ""}, {"VersionTLS12", Const, 2, ""}, {"VersionTLS13", Const, 12, ""}, {"X25519", Const, 8, ""}, {"X25519MLKEM768", Const, 24, ""}, {"X509KeyPair", Func, 0, "func(certPEMBlock []byte, keyPEMBlock []byte) (Certificate, error)"}, }, "crypto/x509": { {"(*CertPool).AddCert", Method, 0, ""}, {"(*CertPool).AddCertWithConstraint", Method, 22, ""}, {"(*CertPool).AppendCertsFromPEM", Method, 0, ""}, {"(*CertPool).Clone", Method, 19, ""}, {"(*CertPool).Equal", Method, 19, ""}, {"(*CertPool).Subjects", Method, 0, ""}, {"(*Certificate).CheckCRLSignature", Method, 0, ""}, {"(*Certificate).CheckSignature", Method, 0, ""}, {"(*Certificate).CheckSignatureFrom", Method, 0, ""}, {"(*Certificate).CreateCRL", Method, 0, ""}, {"(*Certificate).Equal", Method, 0, ""}, {"(*Certificate).Verify", Method, 0, ""}, {"(*Certificate).VerifyHostname", Method, 0, ""}, {"(*CertificateRequest).CheckSignature", Method, 5, ""}, {"(*OID).UnmarshalBinary", Method, 23, ""}, {"(*OID).UnmarshalText", Method, 23, ""}, {"(*RevocationList).CheckSignatureFrom", Method, 19, ""}, {"(CertificateInvalidError).Error", Method, 0, ""}, {"(ConstraintViolationError).Error", Method, 0, ""}, {"(HostnameError).Error", Method, 0, ""}, {"(InsecureAlgorithmError).Error", Method, 6, ""}, {"(OID).AppendBinary", Method, 24, ""}, {"(OID).AppendText", Method, 24, ""}, {"(OID).Equal", Method, 22, ""}, {"(OID).EqualASN1OID", Method, 22, ""}, {"(OID).MarshalBinary", Method, 23, ""}, {"(OID).MarshalText", Method, 23, ""}, {"(OID).String", Method, 22, ""}, {"(PublicKeyAlgorithm).String", Method, 10, ""}, {"(SignatureAlgorithm).String", Method, 6, ""}, {"(SystemRootsError).Error", Method, 1, ""}, {"(SystemRootsError).Unwrap", Method, 16, ""}, {"(UnhandledCriticalExtension).Error", Method, 0, ""}, {"(UnknownAuthorityError).Error", Method, 0, ""}, {"CANotAuthorizedForExtKeyUsage", Const, 10, ""}, {"CANotAuthorizedForThisName", Const, 0, ""}, {"CertPool", Type, 0, ""}, {"Certificate", Type, 0, ""}, {"Certificate.AuthorityKeyId", Field, 0, ""}, {"Certificate.BasicConstraintsValid", Field, 0, ""}, {"Certificate.CRLDistributionPoints", Field, 2, ""}, {"Certificate.DNSNames", Field, 0, ""}, {"Certificate.EmailAddresses", Field, 0, ""}, {"Certificate.ExcludedDNSDomains", Field, 9, ""}, {"Certificate.ExcludedEmailAddresses", Field, 10, ""}, {"Certificate.ExcludedIPRanges", Field, 10, ""}, {"Certificate.ExcludedURIDomains", Field, 10, ""}, {"Certificate.ExtKeyUsage", Field, 0, ""}, {"Certificate.Extensions", Field, 2, ""}, {"Certificate.ExtraExtensions", Field, 2, ""}, {"Certificate.IPAddresses", Field, 1, ""}, {"Certificate.InhibitAnyPolicy", Field, 24, ""}, {"Certificate.InhibitAnyPolicyZero", Field, 24, ""}, {"Certificate.InhibitPolicyMapping", Field, 24, ""}, {"Certificate.InhibitPolicyMappingZero", Field, 24, ""}, {"Certificate.IsCA", Field, 0, ""}, {"Certificate.Issuer", Field, 0, ""}, {"Certificate.IssuingCertificateURL", Field, 2, ""}, {"Certificate.KeyUsage", Field, 0, ""}, {"Certificate.MaxPathLen", Field, 0, ""}, {"Certificate.MaxPathLenZero", Field, 4, ""}, {"Certificate.NotAfter", Field, 0, ""}, {"Certificate.NotBefore", Field, 0, ""}, {"Certificate.OCSPServer", Field, 2, ""}, {"Certificate.PermittedDNSDomains", Field, 0, ""}, {"Certificate.PermittedDNSDomainsCritical", Field, 0, ""}, {"Certificate.PermittedEmailAddresses", Field, 10, ""}, {"Certificate.PermittedIPRanges", Field, 10, ""}, {"Certificate.PermittedURIDomains", Field, 10, ""}, {"Certificate.Policies", Field, 22, ""}, {"Certificate.PolicyIdentifiers", Field, 0, ""}, {"Certificate.PolicyMappings", Field, 24, ""}, {"Certificate.PublicKey", Field, 0, ""}, {"Certificate.PublicKeyAlgorithm", Field, 0, ""}, {"Certificate.Raw", Field, 0, ""}, {"Certificate.RawIssuer", Field, 0, ""}, {"Certificate.RawSubject", Field, 0, ""}, {"Certificate.RawSubjectPublicKeyInfo", Field, 0, ""}, {"Certificate.RawTBSCertificate", Field, 0, ""}, {"Certificate.RequireExplicitPolicy", Field, 24, ""}, {"Certificate.RequireExplicitPolicyZero", Field, 24, ""}, {"Certificate.SerialNumber", Field, 0, ""}, {"Certificate.Signature", Field, 0, ""}, {"Certificate.SignatureAlgorithm", Field, 0, ""}, {"Certificate.Subject", Field, 0, ""}, {"Certificate.SubjectKeyId", Field, 0, ""}, {"Certificate.URIs", Field, 10, ""}, {"Certificate.UnhandledCriticalExtensions", Field, 5, ""}, {"Certificate.UnknownExtKeyUsage", Field, 0, ""}, {"Certificate.Version", Field, 0, ""}, {"CertificateInvalidError", Type, 0, ""}, {"CertificateInvalidError.Cert", Field, 0, ""}, {"CertificateInvalidError.Detail", Field, 10, ""}, {"CertificateInvalidError.Reason", Field, 0, ""}, {"CertificateRequest", Type, 3, ""}, {"CertificateRequest.Attributes", Field, 3, ""}, {"CertificateRequest.DNSNames", Field, 3, ""}, {"CertificateRequest.EmailAddresses", Field, 3, ""}, {"CertificateRequest.Extensions", Field, 3, ""}, {"CertificateRequest.ExtraExtensions", Field, 3, ""}, {"CertificateRequest.IPAddresses", Field, 3, ""}, {"CertificateRequest.PublicKey", Field, 3, ""}, {"CertificateRequest.PublicKeyAlgorithm", Field, 3, ""}, {"CertificateRequest.Raw", Field, 3, ""}, {"CertificateRequest.RawSubject", Field, 3, ""}, {"CertificateRequest.RawSubjectPublicKeyInfo", Field, 3, ""}, {"CertificateRequest.RawTBSCertificateRequest", Field, 3, ""}, {"CertificateRequest.Signature", Field, 3, ""}, {"CertificateRequest.SignatureAlgorithm", Field, 3, ""}, {"CertificateRequest.Subject", Field, 3, ""}, {"CertificateRequest.URIs", Field, 10, ""}, {"CertificateRequest.Version", Field, 3, ""}, {"ConstraintViolationError", Type, 0, ""}, {"CreateCertificate", Func, 0, "func(rand io.Reader, template *Certificate, parent *Certificate, pub any, priv any) ([]byte, error)"}, {"CreateCertificateRequest", Func, 3, "func(rand io.Reader, template *CertificateRequest, priv any) (csr []byte, err error)"}, {"CreateRevocationList", Func, 15, "func(rand io.Reader, template *RevocationList, issuer *Certificate, priv crypto.Signer) ([]byte, error)"}, {"DSA", Const, 0, ""}, {"DSAWithSHA1", Const, 0, ""}, {"DSAWithSHA256", Const, 0, ""}, {"DecryptPEMBlock", Func, 1, "func(b *pem.Block, password []byte) ([]byte, error)"}, {"ECDSA", Const, 1, ""}, {"ECDSAWithSHA1", Const, 1, ""}, {"ECDSAWithSHA256", Const, 1, ""}, {"ECDSAWithSHA384", Const, 1, ""}, {"ECDSAWithSHA512", Const, 1, ""}, {"Ed25519", Const, 13, ""}, {"EncryptPEMBlock", Func, 1, "func(rand io.Reader, blockType string, data []byte, password []byte, alg PEMCipher) (*pem.Block, error)"}, {"ErrUnsupportedAlgorithm", Var, 0, ""}, {"Expired", Const, 0, ""}, {"ExtKeyUsage", Type, 0, ""}, {"ExtKeyUsageAny", Const, 0, ""}, {"ExtKeyUsageClientAuth", Const, 0, ""}, {"ExtKeyUsageCodeSigning", Const, 0, ""}, {"ExtKeyUsageEmailProtection", Const, 0, ""}, {"ExtKeyUsageIPSECEndSystem", Const, 1, ""}, {"ExtKeyUsageIPSECTunnel", Const, 1, ""}, {"ExtKeyUsageIPSECUser", Const, 1, ""}, {"ExtKeyUsageMicrosoftCommercialCodeSigning", Const, 10, ""}, {"ExtKeyUsageMicrosoftKernelCodeSigning", Const, 10, ""}, {"ExtKeyUsageMicrosoftServerGatedCrypto", Const, 1, ""}, {"ExtKeyUsageNetscapeServerGatedCrypto", Const, 1, ""}, {"ExtKeyUsageOCSPSigning", Const, 0, ""}, {"ExtKeyUsageServerAuth", Const, 0, ""}, {"ExtKeyUsageTimeStamping", Const, 0, ""}, {"HostnameError", Type, 0, ""}, {"HostnameError.Certificate", Field, 0, ""}, {"HostnameError.Host", Field, 0, ""}, {"IncompatibleUsage", Const, 1, ""}, {"IncorrectPasswordError", Var, 1, ""}, {"InsecureAlgorithmError", Type, 6, ""}, {"InvalidReason", Type, 0, ""}, {"IsEncryptedPEMBlock", Func, 1, "func(b *pem.Block) bool"}, {"KeyUsage", Type, 0, ""}, {"KeyUsageCRLSign", Const, 0, ""}, {"KeyUsageCertSign", Const, 0, ""}, {"KeyUsageContentCommitment", Const, 0, ""}, {"KeyUsageDataEncipherment", Const, 0, ""}, {"KeyUsageDecipherOnly", Const, 0, ""}, {"KeyUsageDigitalSignature", Const, 0, ""}, {"KeyUsageEncipherOnly", Const, 0, ""}, {"KeyUsageKeyAgreement", Const, 0, ""}, {"KeyUsageKeyEncipherment", Const, 0, ""}, {"MD2WithRSA", Const, 0, ""}, {"MD5WithRSA", Const, 0, ""}, {"MarshalECPrivateKey", Func, 2, "func(key *ecdsa.PrivateKey) ([]byte, error)"}, {"MarshalPKCS1PrivateKey", Func, 0, "func(key *rsa.PrivateKey) []byte"}, {"MarshalPKCS1PublicKey", Func, 10, "func(key *rsa.PublicKey) []byte"}, {"MarshalPKCS8PrivateKey", Func, 10, "func(key any) ([]byte, error)"}, {"MarshalPKIXPublicKey", Func, 0, "func(pub any) ([]byte, error)"}, {"NameConstraintsWithoutSANs", Const, 10, ""}, {"NameMismatch", Const, 8, ""}, {"NewCertPool", Func, 0, "func() *CertPool"}, {"NoValidChains", Const, 24, ""}, {"NotAuthorizedToSign", Const, 0, ""}, {"OID", Type, 22, ""}, {"OIDFromInts", Func, 22, "func(oid []uint64) (OID, error)"}, {"PEMCipher", Type, 1, ""}, {"PEMCipher3DES", Const, 1, ""}, {"PEMCipherAES128", Const, 1, ""}, {"PEMCipherAES192", Const, 1, ""}, {"PEMCipherAES256", Const, 1, ""}, {"PEMCipherDES", Const, 1, ""}, {"ParseCRL", Func, 0, "func(crlBytes []byte) (*pkix.CertificateList, error)"}, {"ParseCertificate", Func, 0, "func(der []byte) (*Certificate, error)"}, {"ParseCertificateRequest", Func, 3, "func(asn1Data []byte) (*CertificateRequest, error)"}, {"ParseCertificates", Func, 0, "func(der []byte) ([]*Certificate, error)"}, {"ParseDERCRL", Func, 0, "func(derBytes []byte) (*pkix.CertificateList, error)"}, {"ParseECPrivateKey", Func, 1, "func(der []byte) (*ecdsa.PrivateKey, error)"}, {"ParseOID", Func, 23, "func(oid string) (OID, error)"}, {"ParsePKCS1PrivateKey", Func, 0, "func(der []byte) (*rsa.PrivateKey, error)"}, {"ParsePKCS1PublicKey", Func, 10, "func(der []byte) (*rsa.PublicKey, error)"}, {"ParsePKCS8PrivateKey", Func, 0, "func(der []byte) (key any, err error)"}, {"ParsePKIXPublicKey", Func, 0, "func(derBytes []byte) (pub any, err error)"}, {"ParseRevocationList", Func, 19, "func(der []byte) (*RevocationList, error)"}, {"PolicyMapping", Type, 24, ""}, {"PolicyMapping.IssuerDomainPolicy", Field, 24, ""}, {"PolicyMapping.SubjectDomainPolicy", Field, 24, ""}, {"PublicKeyAlgorithm", Type, 0, ""}, {"PureEd25519", Const, 13, ""}, {"RSA", Const, 0, ""}, {"RevocationList", Type, 15, ""}, {"RevocationList.AuthorityKeyId", Field, 19, ""}, {"RevocationList.Extensions", Field, 19, ""}, {"RevocationList.ExtraExtensions", Field, 15, ""}, {"RevocationList.Issuer", Field, 19, ""}, {"RevocationList.NextUpdate", Field, 15, ""}, {"RevocationList.Number", Field, 15, ""}, {"RevocationList.Raw", Field, 19, ""}, {"RevocationList.RawIssuer", Field, 19, ""}, {"RevocationList.RawTBSRevocationList", Field, 19, ""}, {"RevocationList.RevokedCertificateEntries", Field, 21, ""}, {"RevocationList.RevokedCertificates", Field, 15, ""}, {"RevocationList.Signature", Field, 19, ""}, {"RevocationList.SignatureAlgorithm", Field, 15, ""}, {"RevocationList.ThisUpdate", Field, 15, ""}, {"RevocationListEntry", Type, 21, ""}, {"RevocationListEntry.Extensions", Field, 21, ""}, {"RevocationListEntry.ExtraExtensions", Field, 21, ""}, {"RevocationListEntry.Raw", Field, 21, ""}, {"RevocationListEntry.ReasonCode", Field, 21, ""}, {"RevocationListEntry.RevocationTime", Field, 21, ""}, {"RevocationListEntry.SerialNumber", Field, 21, ""}, {"SHA1WithRSA", Const, 0, ""}, {"SHA256WithRSA", Const, 0, ""}, {"SHA256WithRSAPSS", Const, 8, ""}, {"SHA384WithRSA", Const, 0, ""}, {"SHA384WithRSAPSS", Const, 8, ""}, {"SHA512WithRSA", Const, 0, ""}, {"SHA512WithRSAPSS", Const, 8, ""}, {"SetFallbackRoots", Func, 20, "func(roots *CertPool)"}, {"SignatureAlgorithm", Type, 0, ""}, {"SystemCertPool", Func, 7, "func() (*CertPool, error)"}, {"SystemRootsError", Type, 1, ""}, {"SystemRootsError.Err", Field, 7, ""}, {"TooManyConstraints", Const, 10, ""}, {"TooManyIntermediates", Const, 0, ""}, {"UnconstrainedName", Const, 10, ""}, {"UnhandledCriticalExtension", Type, 0, ""}, {"UnknownAuthorityError", Type, 0, ""}, {"UnknownAuthorityError.Cert", Field, 8, ""}, {"UnknownPublicKeyAlgorithm", Const, 0, ""}, {"UnknownSignatureAlgorithm", Const, 0, ""}, {"VerifyOptions", Type, 0, ""}, {"VerifyOptions.CertificatePolicies", Field, 24, ""}, {"VerifyOptions.CurrentTime", Field, 0, ""}, {"VerifyOptions.DNSName", Field, 0, ""}, {"VerifyOptions.Intermediates", Field, 0, ""}, {"VerifyOptions.KeyUsages", Field, 1, ""}, {"VerifyOptions.MaxConstraintComparisions", Field, 10, ""}, {"VerifyOptions.Roots", Field, 0, ""}, }, "crypto/x509/pkix": { {"(*CertificateList).HasExpired", Method, 0, ""}, {"(*Name).FillFromRDNSequence", Method, 0, ""}, {"(Name).String", Method, 10, ""}, {"(Name).ToRDNSequence", Method, 0, ""}, {"(RDNSequence).String", Method, 10, ""}, {"AlgorithmIdentifier", Type, 0, ""}, {"AlgorithmIdentifier.Algorithm", Field, 0, ""}, {"AlgorithmIdentifier.Parameters", Field, 0, ""}, {"AttributeTypeAndValue", Type, 0, ""}, {"AttributeTypeAndValue.Type", Field, 0, ""}, {"AttributeTypeAndValue.Value", Field, 0, ""}, {"AttributeTypeAndValueSET", Type, 3, ""}, {"AttributeTypeAndValueSET.Type", Field, 3, ""}, {"AttributeTypeAndValueSET.Value", Field, 3, ""}, {"CertificateList", Type, 0, ""}, {"CertificateList.SignatureAlgorithm", Field, 0, ""}, {"CertificateList.SignatureValue", Field, 0, ""}, {"CertificateList.TBSCertList", Field, 0, ""}, {"Extension", Type, 0, ""}, {"Extension.Critical", Field, 0, ""}, {"Extension.Id", Field, 0, ""}, {"Extension.Value", Field, 0, ""}, {"Name", Type, 0, ""}, {"Name.CommonName", Field, 0, ""}, {"Name.Country", Field, 0, ""}, {"Name.ExtraNames", Field, 5, ""}, {"Name.Locality", Field, 0, ""}, {"Name.Names", Field, 0, ""}, {"Name.Organization", Field, 0, ""}, {"Name.OrganizationalUnit", Field, 0, ""}, {"Name.PostalCode", Field, 0, ""}, {"Name.Province", Field, 0, ""}, {"Name.SerialNumber", Field, 0, ""}, {"Name.StreetAddress", Field, 0, ""}, {"RDNSequence", Type, 0, ""}, {"RelativeDistinguishedNameSET", Type, 0, ""}, {"RevokedCertificate", Type, 0, ""}, {"RevokedCertificate.Extensions", Field, 0, ""}, {"RevokedCertificate.RevocationTime", Field, 0, ""}, {"RevokedCertificate.SerialNumber", Field, 0, ""}, {"TBSCertificateList", Type, 0, ""}, {"TBSCertificateList.Extensions", Field, 0, ""}, {"TBSCertificateList.Issuer", Field, 0, ""}, {"TBSCertificateList.NextUpdate", Field, 0, ""}, {"TBSCertificateList.Raw", Field, 0, ""}, {"TBSCertificateList.RevokedCertificates", Field, 0, ""}, {"TBSCertificateList.Signature", Field, 0, ""}, {"TBSCertificateList.ThisUpdate", Field, 0, ""}, {"TBSCertificateList.Version", Field, 0, ""}, }, "database/sql": { {"(*ColumnType).DatabaseTypeName", Method, 8, ""}, {"(*ColumnType).DecimalSize", Method, 8, ""}, {"(*ColumnType).Length", Method, 8, ""}, {"(*ColumnType).Name", Method, 8, ""}, {"(*ColumnType).Nullable", Method, 8, ""}, {"(*ColumnType).ScanType", Method, 8, ""}, {"(*Conn).BeginTx", Method, 9, ""}, {"(*Conn).Close", Method, 9, ""}, {"(*Conn).ExecContext", Method, 9, ""}, {"(*Conn).PingContext", Method, 9, ""}, {"(*Conn).PrepareContext", Method, 9, ""}, {"(*Conn).QueryContext", Method, 9, ""}, {"(*Conn).QueryRowContext", Method, 9, ""}, {"(*Conn).Raw", Method, 13, ""}, {"(*DB).Begin", Method, 0, ""}, {"(*DB).BeginTx", Method, 8, ""}, {"(*DB).Close", Method, 0, ""}, {"(*DB).Conn", Method, 9, ""}, {"(*DB).Driver", Method, 0, ""}, {"(*DB).Exec", Method, 0, ""}, {"(*DB).ExecContext", Method, 8, ""}, {"(*DB).Ping", Method, 1, ""}, {"(*DB).PingContext", Method, 8, ""}, {"(*DB).Prepare", Method, 0, ""}, {"(*DB).PrepareContext", Method, 8, ""}, {"(*DB).Query", Method, 0, ""}, {"(*DB).QueryContext", Method, 8, ""}, {"(*DB).QueryRow", Method, 0, ""}, {"(*DB).QueryRowContext", Method, 8, ""}, {"(*DB).SetConnMaxIdleTime", Method, 15, ""}, {"(*DB).SetConnMaxLifetime", Method, 6, ""}, {"(*DB).SetMaxIdleConns", Method, 1, ""}, {"(*DB).SetMaxOpenConns", Method, 2, ""}, {"(*DB).Stats", Method, 5, ""}, {"(*Null).Scan", Method, 22, ""}, {"(*NullBool).Scan", Method, 0, ""}, {"(*NullByte).Scan", Method, 17, ""}, {"(*NullFloat64).Scan", Method, 0, ""}, {"(*NullInt16).Scan", Method, 17, ""}, {"(*NullInt32).Scan", Method, 13, ""}, {"(*NullInt64).Scan", Method, 0, ""}, {"(*NullString).Scan", Method, 0, ""}, {"(*NullTime).Scan", Method, 13, ""}, {"(*Row).Err", Method, 15, ""}, {"(*Row).Scan", Method, 0, ""}, {"(*Rows).Close", Method, 0, ""}, {"(*Rows).ColumnTypes", Method, 8, ""}, {"(*Rows).Columns", Method, 0, ""}, {"(*Rows).Err", Method, 0, ""}, {"(*Rows).Next", Method, 0, ""}, {"(*Rows).NextResultSet", Method, 8, ""}, {"(*Rows).Scan", Method, 0, ""}, {"(*Stmt).Close", Method, 0, ""}, {"(*Stmt).Exec", Method, 0, ""}, {"(*Stmt).ExecContext", Method, 8, ""}, {"(*Stmt).Query", Method, 0, ""}, {"(*Stmt).QueryContext", Method, 8, ""}, {"(*Stmt).QueryRow", Method, 0, ""}, {"(*Stmt).QueryRowContext", Method, 8, ""}, {"(*Tx).Commit", Method, 0, ""}, {"(*Tx).Exec", Method, 0, ""}, {"(*Tx).ExecContext", Method, 8, ""}, {"(*Tx).Prepare", Method, 0, ""}, {"(*Tx).PrepareContext", Method, 8, ""}, {"(*Tx).Query", Method, 0, ""}, {"(*Tx).QueryContext", Method, 8, ""}, {"(*Tx).QueryRow", Method, 0, ""}, {"(*Tx).QueryRowContext", Method, 8, ""}, {"(*Tx).Rollback", Method, 0, ""}, {"(*Tx).Stmt", Method, 0, ""}, {"(*Tx).StmtContext", Method, 8, ""}, {"(IsolationLevel).String", Method, 11, ""}, {"(Null).Value", Method, 22, ""}, {"(NullBool).Value", Method, 0, ""}, {"(NullByte).Value", Method, 17, ""}, {"(NullFloat64).Value", Method, 0, ""}, {"(NullInt16).Value", Method, 17, ""}, {"(NullInt32).Value", Method, 13, ""}, {"(NullInt64).Value", Method, 0, ""}, {"(NullString).Value", Method, 0, ""}, {"(NullTime).Value", Method, 13, ""}, {"ColumnType", Type, 8, ""}, {"Conn", Type, 9, ""}, {"DB", Type, 0, ""}, {"DBStats", Type, 5, ""}, {"DBStats.Idle", Field, 11, ""}, {"DBStats.InUse", Field, 11, ""}, {"DBStats.MaxIdleClosed", Field, 11, ""}, {"DBStats.MaxIdleTimeClosed", Field, 15, ""}, {"DBStats.MaxLifetimeClosed", Field, 11, ""}, {"DBStats.MaxOpenConnections", Field, 11, ""}, {"DBStats.OpenConnections", Field, 5, ""}, {"DBStats.WaitCount", Field, 11, ""}, {"DBStats.WaitDuration", Field, 11, ""}, {"Drivers", Func, 4, "func() []string"}, {"ErrConnDone", Var, 9, ""}, {"ErrNoRows", Var, 0, ""}, {"ErrTxDone", Var, 0, ""}, {"IsolationLevel", Type, 8, ""}, {"LevelDefault", Const, 8, ""}, {"LevelLinearizable", Const, 8, ""}, {"LevelReadCommitted", Const, 8, ""}, {"LevelReadUncommitted", Const, 8, ""}, {"LevelRepeatableRead", Const, 8, ""}, {"LevelSerializable", Const, 8, ""}, {"LevelSnapshot", Const, 8, ""}, {"LevelWriteCommitted", Const, 8, ""}, {"Named", Func, 8, "func(name string, value any) NamedArg"}, {"NamedArg", Type, 8, ""}, {"NamedArg.Name", Field, 8, ""}, {"NamedArg.Value", Field, 8, ""}, {"Null", Type, 22, ""}, {"Null.V", Field, 22, ""}, {"Null.Valid", Field, 22, ""}, {"NullBool", Type, 0, ""}, {"NullBool.Bool", Field, 0, ""}, {"NullBool.Valid", Field, 0, ""}, {"NullByte", Type, 17, ""}, {"NullByte.Byte", Field, 17, ""}, {"NullByte.Valid", Field, 17, ""}, {"NullFloat64", Type, 0, ""}, {"NullFloat64.Float64", Field, 0, ""}, {"NullFloat64.Valid", Field, 0, ""}, {"NullInt16", Type, 17, ""}, {"NullInt16.Int16", Field, 17, ""}, {"NullInt16.Valid", Field, 17, ""}, {"NullInt32", Type, 13, ""}, {"NullInt32.Int32", Field, 13, ""}, {"NullInt32.Valid", Field, 13, ""}, {"NullInt64", Type, 0, ""}, {"NullInt64.Int64", Field, 0, ""}, {"NullInt64.Valid", Field, 0, ""}, {"NullString", Type, 0, ""}, {"NullString.String", Field, 0, ""}, {"NullString.Valid", Field, 0, ""}, {"NullTime", Type, 13, ""}, {"NullTime.Time", Field, 13, ""}, {"NullTime.Valid", Field, 13, ""}, {"Open", Func, 0, "func(driverName string, dataSourceName string) (*DB, error)"}, {"OpenDB", Func, 10, "func(c driver.Connector) *DB"}, {"Out", Type, 9, ""}, {"Out.Dest", Field, 9, ""}, {"Out.In", Field, 9, ""}, {"RawBytes", Type, 0, ""}, {"Register", Func, 0, "func(name string, driver driver.Driver)"}, {"Result", Type, 0, ""}, {"Row", Type, 0, ""}, {"Rows", Type, 0, ""}, {"Scanner", Type, 0, ""}, {"Stmt", Type, 0, ""}, {"Tx", Type, 0, ""}, {"TxOptions", Type, 8, ""}, {"TxOptions.Isolation", Field, 8, ""}, {"TxOptions.ReadOnly", Field, 8, ""}, }, "database/sql/driver": { {"(NotNull).ConvertValue", Method, 0, ""}, {"(Null).ConvertValue", Method, 0, ""}, {"(RowsAffected).LastInsertId", Method, 0, ""}, {"(RowsAffected).RowsAffected", Method, 0, ""}, {"Bool", Var, 0, ""}, {"ColumnConverter", Type, 0, ""}, {"Conn", Type, 0, ""}, {"ConnBeginTx", Type, 8, ""}, {"ConnPrepareContext", Type, 8, ""}, {"Connector", Type, 10, ""}, {"DefaultParameterConverter", Var, 0, ""}, {"Driver", Type, 0, ""}, {"DriverContext", Type, 10, ""}, {"ErrBadConn", Var, 0, ""}, {"ErrRemoveArgument", Var, 9, ""}, {"ErrSkip", Var, 0, ""}, {"Execer", Type, 0, ""}, {"ExecerContext", Type, 8, ""}, {"Int32", Var, 0, ""}, {"IsScanValue", Func, 0, "func(v any) bool"}, {"IsValue", Func, 0, "func(v any) bool"}, {"IsolationLevel", Type, 8, ""}, {"NamedValue", Type, 8, ""}, {"NamedValue.Name", Field, 8, ""}, {"NamedValue.Ordinal", Field, 8, ""}, {"NamedValue.Value", Field, 8, ""}, {"NamedValueChecker", Type, 9, ""}, {"NotNull", Type, 0, ""}, {"NotNull.Converter", Field, 0, ""}, {"Null", Type, 0, ""}, {"Null.Converter", Field, 0, ""}, {"Pinger", Type, 8, ""}, {"Queryer", Type, 1, ""}, {"QueryerContext", Type, 8, ""}, {"Result", Type, 0, ""}, {"ResultNoRows", Var, 0, ""}, {"Rows", Type, 0, ""}, {"RowsAffected", Type, 0, ""}, {"RowsColumnTypeDatabaseTypeName", Type, 8, ""}, {"RowsColumnTypeLength", Type, 8, ""}, {"RowsColumnTypeNullable", Type, 8, ""}, {"RowsColumnTypePrecisionScale", Type, 8, ""}, {"RowsColumnTypeScanType", Type, 8, ""}, {"RowsNextResultSet", Type, 8, ""}, {"SessionResetter", Type, 10, ""}, {"Stmt", Type, 0, ""}, {"StmtExecContext", Type, 8, ""}, {"StmtQueryContext", Type, 8, ""}, {"String", Var, 0, ""}, {"Tx", Type, 0, ""}, {"TxOptions", Type, 8, ""}, {"TxOptions.Isolation", Field, 8, ""}, {"TxOptions.ReadOnly", Field, 8, ""}, {"Validator", Type, 15, ""}, {"Value", Type, 0, ""}, {"ValueConverter", Type, 0, ""}, {"Valuer", Type, 0, ""}, }, "debug/buildinfo": { {"BuildInfo", Type, 18, ""}, {"Read", Func, 18, "func(r io.ReaderAt) (*BuildInfo, error)"}, {"ReadFile", Func, 18, "func(name string) (info *BuildInfo, err error)"}, }, "debug/dwarf": { {"(*AddrType).Basic", Method, 0, ""}, {"(*AddrType).Common", Method, 0, ""}, {"(*AddrType).Size", Method, 0, ""}, {"(*AddrType).String", Method, 0, ""}, {"(*ArrayType).Common", Method, 0, ""}, {"(*ArrayType).Size", Method, 0, ""}, {"(*ArrayType).String", Method, 0, ""}, {"(*BasicType).Basic", Method, 0, ""}, {"(*BasicType).Common", Method, 0, ""}, {"(*BasicType).Size", Method, 0, ""}, {"(*BasicType).String", Method, 0, ""}, {"(*BoolType).Basic", Method, 0, ""}, {"(*BoolType).Common", Method, 0, ""}, {"(*BoolType).Size", Method, 0, ""}, {"(*BoolType).String", Method, 0, ""}, {"(*CharType).Basic", Method, 0, ""}, {"(*CharType).Common", Method, 0, ""}, {"(*CharType).Size", Method, 0, ""}, {"(*CharType).String", Method, 0, ""}, {"(*CommonType).Common", Method, 0, ""}, {"(*CommonType).Size", Method, 0, ""}, {"(*ComplexType).Basic", Method, 0, ""}, {"(*ComplexType).Common", Method, 0, ""}, {"(*ComplexType).Size", Method, 0, ""}, {"(*ComplexType).String", Method, 0, ""}, {"(*Data).AddSection", Method, 14, ""}, {"(*Data).AddTypes", Method, 3, ""}, {"(*Data).LineReader", Method, 5, ""}, {"(*Data).Ranges", Method, 7, ""}, {"(*Data).Reader", Method, 0, ""}, {"(*Data).Type", Method, 0, ""}, {"(*DotDotDotType).Common", Method, 0, ""}, {"(*DotDotDotType).Size", Method, 0, ""}, {"(*DotDotDotType).String", Method, 0, ""}, {"(*Entry).AttrField", Method, 5, ""}, {"(*Entry).Val", Method, 0, ""}, {"(*EnumType).Common", Method, 0, ""}, {"(*EnumType).Size", Method, 0, ""}, {"(*EnumType).String", Method, 0, ""}, {"(*FloatType).Basic", Method, 0, ""}, {"(*FloatType).Common", Method, 0, ""}, {"(*FloatType).Size", Method, 0, ""}, {"(*FloatType).String", Method, 0, ""}, {"(*FuncType).Common", Method, 0, ""}, {"(*FuncType).Size", Method, 0, ""}, {"(*FuncType).String", Method, 0, ""}, {"(*IntType).Basic", Method, 0, ""}, {"(*IntType).Common", Method, 0, ""}, {"(*IntType).Size", Method, 0, ""}, {"(*IntType).String", Method, 0, ""}, {"(*LineReader).Files", Method, 14, ""}, {"(*LineReader).Next", Method, 5, ""}, {"(*LineReader).Reset", Method, 5, ""}, {"(*LineReader).Seek", Method, 5, ""}, {"(*LineReader).SeekPC", Method, 5, ""}, {"(*LineReader).Tell", Method, 5, ""}, {"(*PtrType).Common", Method, 0, ""}, {"(*PtrType).Size", Method, 0, ""}, {"(*PtrType).String", Method, 0, ""}, {"(*QualType).Common", Method, 0, ""}, {"(*QualType).Size", Method, 0, ""}, {"(*QualType).String", Method, 0, ""}, {"(*Reader).AddressSize", Method, 5, ""}, {"(*Reader).ByteOrder", Method, 14, ""}, {"(*Reader).Next", Method, 0, ""}, {"(*Reader).Seek", Method, 0, ""}, {"(*Reader).SeekPC", Method, 7, ""}, {"(*Reader).SkipChildren", Method, 0, ""}, {"(*StructType).Common", Method, 0, ""}, {"(*StructType).Defn", Method, 0, ""}, {"(*StructType).Size", Method, 0, ""}, {"(*StructType).String", Method, 0, ""}, {"(*TypedefType).Common", Method, 0, ""}, {"(*TypedefType).Size", Method, 0, ""}, {"(*TypedefType).String", Method, 0, ""}, {"(*UcharType).Basic", Method, 0, ""}, {"(*UcharType).Common", Method, 0, ""}, {"(*UcharType).Size", Method, 0, ""}, {"(*UcharType).String", Method, 0, ""}, {"(*UintType).Basic", Method, 0, ""}, {"(*UintType).Common", Method, 0, ""}, {"(*UintType).Size", Method, 0, ""}, {"(*UintType).String", Method, 0, ""}, {"(*UnspecifiedType).Basic", Method, 4, ""}, {"(*UnspecifiedType).Common", Method, 4, ""}, {"(*UnspecifiedType).Size", Method, 4, ""}, {"(*UnspecifiedType).String", Method, 4, ""}, {"(*UnsupportedType).Common", Method, 13, ""}, {"(*UnsupportedType).Size", Method, 13, ""}, {"(*UnsupportedType).String", Method, 13, ""}, {"(*VoidType).Common", Method, 0, ""}, {"(*VoidType).Size", Method, 0, ""}, {"(*VoidType).String", Method, 0, ""}, {"(Attr).GoString", Method, 0, ""}, {"(Attr).String", Method, 0, ""}, {"(Class).GoString", Method, 5, ""}, {"(Class).String", Method, 5, ""}, {"(DecodeError).Error", Method, 0, ""}, {"(Tag).GoString", Method, 0, ""}, {"(Tag).String", Method, 0, ""}, {"AddrType", Type, 0, ""}, {"AddrType.BasicType", Field, 0, ""}, {"ArrayType", Type, 0, ""}, {"ArrayType.CommonType", Field, 0, ""}, {"ArrayType.Count", Field, 0, ""}, {"ArrayType.StrideBitSize", Field, 0, ""}, {"ArrayType.Type", Field, 0, ""}, {"Attr", Type, 0, ""}, {"AttrAbstractOrigin", Const, 0, ""}, {"AttrAccessibility", Const, 0, ""}, {"AttrAddrBase", Const, 14, ""}, {"AttrAddrClass", Const, 0, ""}, {"AttrAlignment", Const, 14, ""}, {"AttrAllocated", Const, 0, ""}, {"AttrArtificial", Const, 0, ""}, {"AttrAssociated", Const, 0, ""}, {"AttrBaseTypes", Const, 0, ""}, {"AttrBinaryScale", Const, 14, ""}, {"AttrBitOffset", Const, 0, ""}, {"AttrBitSize", Const, 0, ""}, {"AttrByteSize", Const, 0, ""}, {"AttrCallAllCalls", Const, 14, ""}, {"AttrCallAllSourceCalls", Const, 14, ""}, {"AttrCallAllTailCalls", Const, 14, ""}, {"AttrCallColumn", Const, 0, ""}, {"AttrCallDataLocation", Const, 14, ""}, {"AttrCallDataValue", Const, 14, ""}, {"AttrCallFile", Const, 0, ""}, {"AttrCallLine", Const, 0, ""}, {"AttrCallOrigin", Const, 14, ""}, {"AttrCallPC", Const, 14, ""}, {"AttrCallParameter", Const, 14, ""}, {"AttrCallReturnPC", Const, 14, ""}, {"AttrCallTailCall", Const, 14, ""}, {"AttrCallTarget", Const, 14, ""}, {"AttrCallTargetClobbered", Const, 14, ""}, {"AttrCallValue", Const, 14, ""}, {"AttrCalling", Const, 0, ""}, {"AttrCommonRef", Const, 0, ""}, {"AttrCompDir", Const, 0, ""}, {"AttrConstExpr", Const, 14, ""}, {"AttrConstValue", Const, 0, ""}, {"AttrContainingType", Const, 0, ""}, {"AttrCount", Const, 0, ""}, {"AttrDataBitOffset", Const, 14, ""}, {"AttrDataLocation", Const, 0, ""}, {"AttrDataMemberLoc", Const, 0, ""}, {"AttrDecimalScale", Const, 14, ""}, {"AttrDecimalSign", Const, 14, ""}, {"AttrDeclColumn", Const, 0, ""}, {"AttrDeclFile", Const, 0, ""}, {"AttrDeclLine", Const, 0, ""}, {"AttrDeclaration", Const, 0, ""}, {"AttrDefaultValue", Const, 0, ""}, {"AttrDefaulted", Const, 14, ""}, {"AttrDeleted", Const, 14, ""}, {"AttrDescription", Const, 0, ""}, {"AttrDigitCount", Const, 14, ""}, {"AttrDiscr", Const, 0, ""}, {"AttrDiscrList", Const, 0, ""}, {"AttrDiscrValue", Const, 0, ""}, {"AttrDwoName", Const, 14, ""}, {"AttrElemental", Const, 14, ""}, {"AttrEncoding", Const, 0, ""}, {"AttrEndianity", Const, 14, ""}, {"AttrEntrypc", Const, 0, ""}, {"AttrEnumClass", Const, 14, ""}, {"AttrExplicit", Const, 14, ""}, {"AttrExportSymbols", Const, 14, ""}, {"AttrExtension", Const, 0, ""}, {"AttrExternal", Const, 0, ""}, {"AttrFrameBase", Const, 0, ""}, {"AttrFriend", Const, 0, ""}, {"AttrHighpc", Const, 0, ""}, {"AttrIdentifierCase", Const, 0, ""}, {"AttrImport", Const, 0, ""}, {"AttrInline", Const, 0, ""}, {"AttrIsOptional", Const, 0, ""}, {"AttrLanguage", Const, 0, ""}, {"AttrLinkageName", Const, 14, ""}, {"AttrLocation", Const, 0, ""}, {"AttrLoclistsBase", Const, 14, ""}, {"AttrLowerBound", Const, 0, ""}, {"AttrLowpc", Const, 0, ""}, {"AttrMacroInfo", Const, 0, ""}, {"AttrMacros", Const, 14, ""}, {"AttrMainSubprogram", Const, 14, ""}, {"AttrMutable", Const, 14, ""}, {"AttrName", Const, 0, ""}, {"AttrNamelistItem", Const, 0, ""}, {"AttrNoreturn", Const, 14, ""}, {"AttrObjectPointer", Const, 14, ""}, {"AttrOrdering", Const, 0, ""}, {"AttrPictureString", Const, 14, ""}, {"AttrPriority", Const, 0, ""}, {"AttrProducer", Const, 0, ""}, {"AttrPrototyped", Const, 0, ""}, {"AttrPure", Const, 14, ""}, {"AttrRanges", Const, 0, ""}, {"AttrRank", Const, 14, ""}, {"AttrRecursive", Const, 14, ""}, {"AttrReference", Const, 14, ""}, {"AttrReturnAddr", Const, 0, ""}, {"AttrRnglistsBase", Const, 14, ""}, {"AttrRvalueReference", Const, 14, ""}, {"AttrSegment", Const, 0, ""}, {"AttrSibling", Const, 0, ""}, {"AttrSignature", Const, 14, ""}, {"AttrSmall", Const, 14, ""}, {"AttrSpecification", Const, 0, ""}, {"AttrStartScope", Const, 0, ""}, {"AttrStaticLink", Const, 0, ""}, {"AttrStmtList", Const, 0, ""}, {"AttrStrOffsetsBase", Const, 14, ""}, {"AttrStride", Const, 0, ""}, {"AttrStrideSize", Const, 0, ""}, {"AttrStringLength", Const, 0, ""}, {"AttrStringLengthBitSize", Const, 14, ""}, {"AttrStringLengthByteSize", Const, 14, ""}, {"AttrThreadsScaled", Const, 14, ""}, {"AttrTrampoline", Const, 0, ""}, {"AttrType", Const, 0, ""}, {"AttrUpperBound", Const, 0, ""}, {"AttrUseLocation", Const, 0, ""}, {"AttrUseUTF8", Const, 0, ""}, {"AttrVarParam", Const, 0, ""}, {"AttrVirtuality", Const, 0, ""}, {"AttrVisibility", Const, 0, ""}, {"AttrVtableElemLoc", Const, 0, ""}, {"BasicType", Type, 0, ""}, {"BasicType.BitOffset", Field, 0, ""}, {"BasicType.BitSize", Field, 0, ""}, {"BasicType.CommonType", Field, 0, ""}, {"BasicType.DataBitOffset", Field, 18, ""}, {"BoolType", Type, 0, ""}, {"BoolType.BasicType", Field, 0, ""}, {"CharType", Type, 0, ""}, {"CharType.BasicType", Field, 0, ""}, {"Class", Type, 5, ""}, {"ClassAddrPtr", Const, 14, ""}, {"ClassAddress", Const, 5, ""}, {"ClassBlock", Const, 5, ""}, {"ClassConstant", Const, 5, ""}, {"ClassExprLoc", Const, 5, ""}, {"ClassFlag", Const, 5, ""}, {"ClassLinePtr", Const, 5, ""}, {"ClassLocList", Const, 14, ""}, {"ClassLocListPtr", Const, 5, ""}, {"ClassMacPtr", Const, 5, ""}, {"ClassRangeListPtr", Const, 5, ""}, {"ClassReference", Const, 5, ""}, {"ClassReferenceAlt", Const, 5, ""}, {"ClassReferenceSig", Const, 5, ""}, {"ClassRngList", Const, 14, ""}, {"ClassRngListsPtr", Const, 14, ""}, {"ClassStrOffsetsPtr", Const, 14, ""}, {"ClassString", Const, 5, ""}, {"ClassStringAlt", Const, 5, ""}, {"ClassUnknown", Const, 6, ""}, {"CommonType", Type, 0, ""}, {"CommonType.ByteSize", Field, 0, ""}, {"CommonType.Name", Field, 0, ""}, {"ComplexType", Type, 0, ""}, {"ComplexType.BasicType", Field, 0, ""}, {"Data", Type, 0, ""}, {"DecodeError", Type, 0, ""}, {"DecodeError.Err", Field, 0, ""}, {"DecodeError.Name", Field, 0, ""}, {"DecodeError.Offset", Field, 0, ""}, {"DotDotDotType", Type, 0, ""}, {"DotDotDotType.CommonType", Field, 0, ""}, {"Entry", Type, 0, ""}, {"Entry.Children", Field, 0, ""}, {"Entry.Field", Field, 0, ""}, {"Entry.Offset", Field, 0, ""}, {"Entry.Tag", Field, 0, ""}, {"EnumType", Type, 0, ""}, {"EnumType.CommonType", Field, 0, ""}, {"EnumType.EnumName", Field, 0, ""}, {"EnumType.Val", Field, 0, ""}, {"EnumValue", Type, 0, ""}, {"EnumValue.Name", Field, 0, ""}, {"EnumValue.Val", Field, 0, ""}, {"ErrUnknownPC", Var, 5, ""}, {"Field", Type, 0, ""}, {"Field.Attr", Field, 0, ""}, {"Field.Class", Field, 5, ""}, {"Field.Val", Field, 0, ""}, {"FloatType", Type, 0, ""}, {"FloatType.BasicType", Field, 0, ""}, {"FuncType", Type, 0, ""}, {"FuncType.CommonType", Field, 0, ""}, {"FuncType.ParamType", Field, 0, ""}, {"FuncType.ReturnType", Field, 0, ""}, {"IntType", Type, 0, ""}, {"IntType.BasicType", Field, 0, ""}, {"LineEntry", Type, 5, ""}, {"LineEntry.Address", Field, 5, ""}, {"LineEntry.BasicBlock", Field, 5, ""}, {"LineEntry.Column", Field, 5, ""}, {"LineEntry.Discriminator", Field, 5, ""}, {"LineEntry.EndSequence", Field, 5, ""}, {"LineEntry.EpilogueBegin", Field, 5, ""}, {"LineEntry.File", Field, 5, ""}, {"LineEntry.ISA", Field, 5, ""}, {"LineEntry.IsStmt", Field, 5, ""}, {"LineEntry.Line", Field, 5, ""}, {"LineEntry.OpIndex", Field, 5, ""}, {"LineEntry.PrologueEnd", Field, 5, ""}, {"LineFile", Type, 5, ""}, {"LineFile.Length", Field, 5, ""}, {"LineFile.Mtime", Field, 5, ""}, {"LineFile.Name", Field, 5, ""}, {"LineReader", Type, 5, ""}, {"LineReaderPos", Type, 5, ""}, {"New", Func, 0, "func(abbrev []byte, aranges []byte, frame []byte, info []byte, line []byte, pubnames []byte, ranges []byte, str []byte) (*Data, error)"}, {"Offset", Type, 0, ""}, {"PtrType", Type, 0, ""}, {"PtrType.CommonType", Field, 0, ""}, {"PtrType.Type", Field, 0, ""}, {"QualType", Type, 0, ""}, {"QualType.CommonType", Field, 0, ""}, {"QualType.Qual", Field, 0, ""}, {"QualType.Type", Field, 0, ""}, {"Reader", Type, 0, ""}, {"StructField", Type, 0, ""}, {"StructField.BitOffset", Field, 0, ""}, {"StructField.BitSize", Field, 0, ""}, {"StructField.ByteOffset", Field, 0, ""}, {"StructField.ByteSize", Field, 0, ""}, {"StructField.DataBitOffset", Field, 18, ""}, {"StructField.Name", Field, 0, ""}, {"StructField.Type", Field, 0, ""}, {"StructType", Type, 0, ""}, {"StructType.CommonType", Field, 0, ""}, {"StructType.Field", Field, 0, ""}, {"StructType.Incomplete", Field, 0, ""}, {"StructType.Kind", Field, 0, ""}, {"StructType.StructName", Field, 0, ""}, {"Tag", Type, 0, ""}, {"TagAccessDeclaration", Const, 0, ""}, {"TagArrayType", Const, 0, ""}, {"TagAtomicType", Const, 14, ""}, {"TagBaseType", Const, 0, ""}, {"TagCallSite", Const, 14, ""}, {"TagCallSiteParameter", Const, 14, ""}, {"TagCatchDwarfBlock", Const, 0, ""}, {"TagClassType", Const, 0, ""}, {"TagCoarrayType", Const, 14, ""}, {"TagCommonDwarfBlock", Const, 0, ""}, {"TagCommonInclusion", Const, 0, ""}, {"TagCompileUnit", Const, 0, ""}, {"TagCondition", Const, 3, ""}, {"TagConstType", Const, 0, ""}, {"TagConstant", Const, 0, ""}, {"TagDwarfProcedure", Const, 0, ""}, {"TagDynamicType", Const, 14, ""}, {"TagEntryPoint", Const, 0, ""}, {"TagEnumerationType", Const, 0, ""}, {"TagEnumerator", Const, 0, ""}, {"TagFileType", Const, 0, ""}, {"TagFormalParameter", Const, 0, ""}, {"TagFriend", Const, 0, ""}, {"TagGenericSubrange", Const, 14, ""}, {"TagImmutableType", Const, 14, ""}, {"TagImportedDeclaration", Const, 0, ""}, {"TagImportedModule", Const, 0, ""}, {"TagImportedUnit", Const, 0, ""}, {"TagInheritance", Const, 0, ""}, {"TagInlinedSubroutine", Const, 0, ""}, {"TagInterfaceType", Const, 0, ""}, {"TagLabel", Const, 0, ""}, {"TagLexDwarfBlock", Const, 0, ""}, {"TagMember", Const, 0, ""}, {"TagModule", Const, 0, ""}, {"TagMutableType", Const, 0, ""}, {"TagNamelist", Const, 0, ""}, {"TagNamelistItem", Const, 0, ""}, {"TagNamespace", Const, 0, ""}, {"TagPackedType", Const, 0, ""}, {"TagPartialUnit", Const, 0, ""}, {"TagPointerType", Const, 0, ""}, {"TagPtrToMemberType", Const, 0, ""}, {"TagReferenceType", Const, 0, ""}, {"TagRestrictType", Const, 0, ""}, {"TagRvalueReferenceType", Const, 3, ""}, {"TagSetType", Const, 0, ""}, {"TagSharedType", Const, 3, ""}, {"TagSkeletonUnit", Const, 14, ""}, {"TagStringType", Const, 0, ""}, {"TagStructType", Const, 0, ""}, {"TagSubprogram", Const, 0, ""}, {"TagSubrangeType", Const, 0, ""}, {"TagSubroutineType", Const, 0, ""}, {"TagTemplateAlias", Const, 3, ""}, {"TagTemplateTypeParameter", Const, 0, ""}, {"TagTemplateValueParameter", Const, 0, ""}, {"TagThrownType", Const, 0, ""}, {"TagTryDwarfBlock", Const, 0, ""}, {"TagTypeUnit", Const, 3, ""}, {"TagTypedef", Const, 0, ""}, {"TagUnionType", Const, 0, ""}, {"TagUnspecifiedParameters", Const, 0, ""}, {"TagUnspecifiedType", Const, 0, ""}, {"TagVariable", Const, 0, ""}, {"TagVariant", Const, 0, ""}, {"TagVariantPart", Const, 0, ""}, {"TagVolatileType", Const, 0, ""}, {"TagWithStmt", Const, 0, ""}, {"Type", Type, 0, ""}, {"TypedefType", Type, 0, ""}, {"TypedefType.CommonType", Field, 0, ""}, {"TypedefType.Type", Field, 0, ""}, {"UcharType", Type, 0, ""}, {"UcharType.BasicType", Field, 0, ""}, {"UintType", Type, 0, ""}, {"UintType.BasicType", Field, 0, ""}, {"UnspecifiedType", Type, 4, ""}, {"UnspecifiedType.BasicType", Field, 4, ""}, {"UnsupportedType", Type, 13, ""}, {"UnsupportedType.CommonType", Field, 13, ""}, {"UnsupportedType.Tag", Field, 13, ""}, {"VoidType", Type, 0, ""}, {"VoidType.CommonType", Field, 0, ""}, }, "debug/elf": { {"(*File).Close", Method, 0, ""}, {"(*File).DWARF", Method, 0, ""}, {"(*File).DynString", Method, 1, ""}, {"(*File).DynValue", Method, 21, ""}, {"(*File).DynamicSymbols", Method, 4, ""}, {"(*File).DynamicVersionNeeds", Method, 24, ""}, {"(*File).DynamicVersions", Method, 24, ""}, {"(*File).ImportedLibraries", Method, 0, ""}, {"(*File).ImportedSymbols", Method, 0, ""}, {"(*File).Section", Method, 0, ""}, {"(*File).SectionByType", Method, 0, ""}, {"(*File).Symbols", Method, 0, ""}, {"(*FormatError).Error", Method, 0, ""}, {"(*Prog).Open", Method, 0, ""}, {"(*Section).Data", Method, 0, ""}, {"(*Section).Open", Method, 0, ""}, {"(Class).GoString", Method, 0, ""}, {"(Class).String", Method, 0, ""}, {"(CompressionType).GoString", Method, 6, ""}, {"(CompressionType).String", Method, 6, ""}, {"(Data).GoString", Method, 0, ""}, {"(Data).String", Method, 0, ""}, {"(DynFlag).GoString", Method, 0, ""}, {"(DynFlag).String", Method, 0, ""}, {"(DynFlag1).GoString", Method, 21, ""}, {"(DynFlag1).String", Method, 21, ""}, {"(DynTag).GoString", Method, 0, ""}, {"(DynTag).String", Method, 0, ""}, {"(Machine).GoString", Method, 0, ""}, {"(Machine).String", Method, 0, ""}, {"(NType).GoString", Method, 0, ""}, {"(NType).String", Method, 0, ""}, {"(OSABI).GoString", Method, 0, ""}, {"(OSABI).String", Method, 0, ""}, {"(Prog).ReadAt", Method, 0, ""}, {"(ProgFlag).GoString", Method, 0, ""}, {"(ProgFlag).String", Method, 0, ""}, {"(ProgType).GoString", Method, 0, ""}, {"(ProgType).String", Method, 0, ""}, {"(R_386).GoString", Method, 0, ""}, {"(R_386).String", Method, 0, ""}, {"(R_390).GoString", Method, 7, ""}, {"(R_390).String", Method, 7, ""}, {"(R_AARCH64).GoString", Method, 4, ""}, {"(R_AARCH64).String", Method, 4, ""}, {"(R_ALPHA).GoString", Method, 0, ""}, {"(R_ALPHA).String", Method, 0, ""}, {"(R_ARM).GoString", Method, 0, ""}, {"(R_ARM).String", Method, 0, ""}, {"(R_LARCH).GoString", Method, 19, ""}, {"(R_LARCH).String", Method, 19, ""}, {"(R_MIPS).GoString", Method, 6, ""}, {"(R_MIPS).String", Method, 6, ""}, {"(R_PPC).GoString", Method, 0, ""}, {"(R_PPC).String", Method, 0, ""}, {"(R_PPC64).GoString", Method, 5, ""}, {"(R_PPC64).String", Method, 5, ""}, {"(R_RISCV).GoString", Method, 11, ""}, {"(R_RISCV).String", Method, 11, ""}, {"(R_SPARC).GoString", Method, 0, ""}, {"(R_SPARC).String", Method, 0, ""}, {"(R_X86_64).GoString", Method, 0, ""}, {"(R_X86_64).String", Method, 0, ""}, {"(Section).ReadAt", Method, 0, ""}, {"(SectionFlag).GoString", Method, 0, ""}, {"(SectionFlag).String", Method, 0, ""}, {"(SectionIndex).GoString", Method, 0, ""}, {"(SectionIndex).String", Method, 0, ""}, {"(SectionType).GoString", Method, 0, ""}, {"(SectionType).String", Method, 0, ""}, {"(SymBind).GoString", Method, 0, ""}, {"(SymBind).String", Method, 0, ""}, {"(SymType).GoString", Method, 0, ""}, {"(SymType).String", Method, 0, ""}, {"(SymVis).GoString", Method, 0, ""}, {"(SymVis).String", Method, 0, ""}, {"(Type).GoString", Method, 0, ""}, {"(Type).String", Method, 0, ""}, {"(Version).GoString", Method, 0, ""}, {"(Version).String", Method, 0, ""}, {"(VersionIndex).Index", Method, 24, ""}, {"(VersionIndex).IsHidden", Method, 24, ""}, {"ARM_MAGIC_TRAMP_NUMBER", Const, 0, ""}, {"COMPRESS_HIOS", Const, 6, ""}, {"COMPRESS_HIPROC", Const, 6, ""}, {"COMPRESS_LOOS", Const, 6, ""}, {"COMPRESS_LOPROC", Const, 6, ""}, {"COMPRESS_ZLIB", Const, 6, ""}, {"COMPRESS_ZSTD", Const, 21, ""}, {"Chdr32", Type, 6, ""}, {"Chdr32.Addralign", Field, 6, ""}, {"Chdr32.Size", Field, 6, ""}, {"Chdr32.Type", Field, 6, ""}, {"Chdr64", Type, 6, ""}, {"Chdr64.Addralign", Field, 6, ""}, {"Chdr64.Size", Field, 6, ""}, {"Chdr64.Type", Field, 6, ""}, {"Class", Type, 0, ""}, {"CompressionType", Type, 6, ""}, {"DF_1_CONFALT", Const, 21, ""}, {"DF_1_DIRECT", Const, 21, ""}, {"DF_1_DISPRELDNE", Const, 21, ""}, {"DF_1_DISPRELPND", Const, 21, ""}, {"DF_1_EDITED", Const, 21, ""}, {"DF_1_ENDFILTEE", Const, 21, ""}, {"DF_1_GLOBAL", Const, 21, ""}, {"DF_1_GLOBAUDIT", Const, 21, ""}, {"DF_1_GROUP", Const, 21, ""}, {"DF_1_IGNMULDEF", Const, 21, ""}, {"DF_1_INITFIRST", Const, 21, ""}, {"DF_1_INTERPOSE", Const, 21, ""}, {"DF_1_KMOD", Const, 21, ""}, {"DF_1_LOADFLTR", Const, 21, ""}, {"DF_1_NOCOMMON", Const, 21, ""}, {"DF_1_NODEFLIB", Const, 21, ""}, {"DF_1_NODELETE", Const, 21, ""}, {"DF_1_NODIRECT", Const, 21, ""}, {"DF_1_NODUMP", Const, 21, ""}, {"DF_1_NOHDR", Const, 21, ""}, {"DF_1_NOKSYMS", Const, 21, ""}, {"DF_1_NOOPEN", Const, 21, ""}, {"DF_1_NORELOC", Const, 21, ""}, {"DF_1_NOW", Const, 21, ""}, {"DF_1_ORIGIN", Const, 21, ""}, {"DF_1_PIE", Const, 21, ""}, {"DF_1_SINGLETON", Const, 21, ""}, {"DF_1_STUB", Const, 21, ""}, {"DF_1_SYMINTPOSE", Const, 21, ""}, {"DF_1_TRANS", Const, 21, ""}, {"DF_1_WEAKFILTER", Const, 21, ""}, {"DF_BIND_NOW", Const, 0, ""}, {"DF_ORIGIN", Const, 0, ""}, {"DF_STATIC_TLS", Const, 0, ""}, {"DF_SYMBOLIC", Const, 0, ""}, {"DF_TEXTREL", Const, 0, ""}, {"DT_ADDRRNGHI", Const, 16, ""}, {"DT_ADDRRNGLO", Const, 16, ""}, {"DT_AUDIT", Const, 16, ""}, {"DT_AUXILIARY", Const, 16, ""}, {"DT_BIND_NOW", Const, 0, ""}, {"DT_CHECKSUM", Const, 16, ""}, {"DT_CONFIG", Const, 16, ""}, {"DT_DEBUG", Const, 0, ""}, {"DT_DEPAUDIT", Const, 16, ""}, {"DT_ENCODING", Const, 0, ""}, {"DT_FEATURE", Const, 16, ""}, {"DT_FILTER", Const, 16, ""}, {"DT_FINI", Const, 0, ""}, {"DT_FINI_ARRAY", Const, 0, ""}, {"DT_FINI_ARRAYSZ", Const, 0, ""}, {"DT_FLAGS", Const, 0, ""}, {"DT_FLAGS_1", Const, 16, ""}, {"DT_GNU_CONFLICT", Const, 16, ""}, {"DT_GNU_CONFLICTSZ", Const, 16, ""}, {"DT_GNU_HASH", Const, 16, ""}, {"DT_GNU_LIBLIST", Const, 16, ""}, {"DT_GNU_LIBLISTSZ", Const, 16, ""}, {"DT_GNU_PRELINKED", Const, 16, ""}, {"DT_HASH", Const, 0, ""}, {"DT_HIOS", Const, 0, ""}, {"DT_HIPROC", Const, 0, ""}, {"DT_INIT", Const, 0, ""}, {"DT_INIT_ARRAY", Const, 0, ""}, {"DT_INIT_ARRAYSZ", Const, 0, ""}, {"DT_JMPREL", Const, 0, ""}, {"DT_LOOS", Const, 0, ""}, {"DT_LOPROC", Const, 0, ""}, {"DT_MIPS_AUX_DYNAMIC", Const, 16, ""}, {"DT_MIPS_BASE_ADDRESS", Const, 16, ""}, {"DT_MIPS_COMPACT_SIZE", Const, 16, ""}, {"DT_MIPS_CONFLICT", Const, 16, ""}, {"DT_MIPS_CONFLICTNO", Const, 16, ""}, {"DT_MIPS_CXX_FLAGS", Const, 16, ""}, {"DT_MIPS_DELTA_CLASS", Const, 16, ""}, {"DT_MIPS_DELTA_CLASSSYM", Const, 16, ""}, {"DT_MIPS_DELTA_CLASSSYM_NO", Const, 16, ""}, {"DT_MIPS_DELTA_CLASS_NO", Const, 16, ""}, {"DT_MIPS_DELTA_INSTANCE", Const, 16, ""}, {"DT_MIPS_DELTA_INSTANCE_NO", Const, 16, ""}, {"DT_MIPS_DELTA_RELOC", Const, 16, ""}, {"DT_MIPS_DELTA_RELOC_NO", Const, 16, ""}, {"DT_MIPS_DELTA_SYM", Const, 16, ""}, {"DT_MIPS_DELTA_SYM_NO", Const, 16, ""}, {"DT_MIPS_DYNSTR_ALIGN", Const, 16, ""}, {"DT_MIPS_FLAGS", Const, 16, ""}, {"DT_MIPS_GOTSYM", Const, 16, ""}, {"DT_MIPS_GP_VALUE", Const, 16, ""}, {"DT_MIPS_HIDDEN_GOTIDX", Const, 16, ""}, {"DT_MIPS_HIPAGENO", Const, 16, ""}, {"DT_MIPS_ICHECKSUM", Const, 16, ""}, {"DT_MIPS_INTERFACE", Const, 16, ""}, {"DT_MIPS_INTERFACE_SIZE", Const, 16, ""}, {"DT_MIPS_IVERSION", Const, 16, ""}, {"DT_MIPS_LIBLIST", Const, 16, ""}, {"DT_MIPS_LIBLISTNO", Const, 16, ""}, {"DT_MIPS_LOCALPAGE_GOTIDX", Const, 16, ""}, {"DT_MIPS_LOCAL_GOTIDX", Const, 16, ""}, {"DT_MIPS_LOCAL_GOTNO", Const, 16, ""}, {"DT_MIPS_MSYM", Const, 16, ""}, {"DT_MIPS_OPTIONS", Const, 16, ""}, {"DT_MIPS_PERF_SUFFIX", Const, 16, ""}, {"DT_MIPS_PIXIE_INIT", Const, 16, ""}, {"DT_MIPS_PLTGOT", Const, 16, ""}, {"DT_MIPS_PROTECTED_GOTIDX", Const, 16, ""}, {"DT_MIPS_RLD_MAP", Const, 16, ""}, {"DT_MIPS_RLD_MAP_REL", Const, 16, ""}, {"DT_MIPS_RLD_TEXT_RESOLVE_ADDR", Const, 16, ""}, {"DT_MIPS_RLD_VERSION", Const, 16, ""}, {"DT_MIPS_RWPLT", Const, 16, ""}, {"DT_MIPS_SYMBOL_LIB", Const, 16, ""}, {"DT_MIPS_SYMTABNO", Const, 16, ""}, {"DT_MIPS_TIME_STAMP", Const, 16, ""}, {"DT_MIPS_UNREFEXTNO", Const, 16, ""}, {"DT_MOVEENT", Const, 16, ""}, {"DT_MOVESZ", Const, 16, ""}, {"DT_MOVETAB", Const, 16, ""}, {"DT_NEEDED", Const, 0, ""}, {"DT_NULL", Const, 0, ""}, {"DT_PLTGOT", Const, 0, ""}, {"DT_PLTPAD", Const, 16, ""}, {"DT_PLTPADSZ", Const, 16, ""}, {"DT_PLTREL", Const, 0, ""}, {"DT_PLTRELSZ", Const, 0, ""}, {"DT_POSFLAG_1", Const, 16, ""}, {"DT_PPC64_GLINK", Const, 16, ""}, {"DT_PPC64_OPD", Const, 16, ""}, {"DT_PPC64_OPDSZ", Const, 16, ""}, {"DT_PPC64_OPT", Const, 16, ""}, {"DT_PPC_GOT", Const, 16, ""}, {"DT_PPC_OPT", Const, 16, ""}, {"DT_PREINIT_ARRAY", Const, 0, ""}, {"DT_PREINIT_ARRAYSZ", Const, 0, ""}, {"DT_REL", Const, 0, ""}, {"DT_RELA", Const, 0, ""}, {"DT_RELACOUNT", Const, 16, ""}, {"DT_RELAENT", Const, 0, ""}, {"DT_RELASZ", Const, 0, ""}, {"DT_RELCOUNT", Const, 16, ""}, {"DT_RELENT", Const, 0, ""}, {"DT_RELSZ", Const, 0, ""}, {"DT_RPATH", Const, 0, ""}, {"DT_RUNPATH", Const, 0, ""}, {"DT_SONAME", Const, 0, ""}, {"DT_SPARC_REGISTER", Const, 16, ""}, {"DT_STRSZ", Const, 0, ""}, {"DT_STRTAB", Const, 0, ""}, {"DT_SYMBOLIC", Const, 0, ""}, {"DT_SYMENT", Const, 0, ""}, {"DT_SYMINENT", Const, 16, ""}, {"DT_SYMINFO", Const, 16, ""}, {"DT_SYMINSZ", Const, 16, ""}, {"DT_SYMTAB", Const, 0, ""}, {"DT_SYMTAB_SHNDX", Const, 16, ""}, {"DT_TEXTREL", Const, 0, ""}, {"DT_TLSDESC_GOT", Const, 16, ""}, {"DT_TLSDESC_PLT", Const, 16, ""}, {"DT_USED", Const, 16, ""}, {"DT_VALRNGHI", Const, 16, ""}, {"DT_VALRNGLO", Const, 16, ""}, {"DT_VERDEF", Const, 16, ""}, {"DT_VERDEFNUM", Const, 16, ""}, {"DT_VERNEED", Const, 0, ""}, {"DT_VERNEEDNUM", Const, 0, ""}, {"DT_VERSYM", Const, 0, ""}, {"Data", Type, 0, ""}, {"Dyn32", Type, 0, ""}, {"Dyn32.Tag", Field, 0, ""}, {"Dyn32.Val", Field, 0, ""}, {"Dyn64", Type, 0, ""}, {"Dyn64.Tag", Field, 0, ""}, {"Dyn64.Val", Field, 0, ""}, {"DynFlag", Type, 0, ""}, {"DynFlag1", Type, 21, ""}, {"DynTag", Type, 0, ""}, {"DynamicVersion", Type, 24, ""}, {"DynamicVersion.Deps", Field, 24, ""}, {"DynamicVersion.Flags", Field, 24, ""}, {"DynamicVersion.Index", Field, 24, ""}, {"DynamicVersion.Name", Field, 24, ""}, {"DynamicVersionDep", Type, 24, ""}, {"DynamicVersionDep.Dep", Field, 24, ""}, {"DynamicVersionDep.Flags", Field, 24, ""}, {"DynamicVersionDep.Index", Field, 24, ""}, {"DynamicVersionFlag", Type, 24, ""}, {"DynamicVersionNeed", Type, 24, ""}, {"DynamicVersionNeed.Name", Field, 24, ""}, {"DynamicVersionNeed.Needs", Field, 24, ""}, {"EI_ABIVERSION", Const, 0, ""}, {"EI_CLASS", Const, 0, ""}, {"EI_DATA", Const, 0, ""}, {"EI_NIDENT", Const, 0, ""}, {"EI_OSABI", Const, 0, ""}, {"EI_PAD", Const, 0, ""}, {"EI_VERSION", Const, 0, ""}, {"ELFCLASS32", Const, 0, ""}, {"ELFCLASS64", Const, 0, ""}, {"ELFCLASSNONE", Const, 0, ""}, {"ELFDATA2LSB", Const, 0, ""}, {"ELFDATA2MSB", Const, 0, ""}, {"ELFDATANONE", Const, 0, ""}, {"ELFMAG", Const, 0, ""}, {"ELFOSABI_86OPEN", Const, 0, ""}, {"ELFOSABI_AIX", Const, 0, ""}, {"ELFOSABI_ARM", Const, 0, ""}, {"ELFOSABI_AROS", Const, 11, ""}, {"ELFOSABI_CLOUDABI", Const, 11, ""}, {"ELFOSABI_FENIXOS", Const, 11, ""}, {"ELFOSABI_FREEBSD", Const, 0, ""}, {"ELFOSABI_HPUX", Const, 0, ""}, {"ELFOSABI_HURD", Const, 0, ""}, {"ELFOSABI_IRIX", Const, 0, ""}, {"ELFOSABI_LINUX", Const, 0, ""}, {"ELFOSABI_MODESTO", Const, 0, ""}, {"ELFOSABI_NETBSD", Const, 0, ""}, {"ELFOSABI_NONE", Const, 0, ""}, {"ELFOSABI_NSK", Const, 0, ""}, {"ELFOSABI_OPENBSD", Const, 0, ""}, {"ELFOSABI_OPENVMS", Const, 0, ""}, {"ELFOSABI_SOLARIS", Const, 0, ""}, {"ELFOSABI_STANDALONE", Const, 0, ""}, {"ELFOSABI_TRU64", Const, 0, ""}, {"EM_386", Const, 0, ""}, {"EM_486", Const, 0, ""}, {"EM_56800EX", Const, 11, ""}, {"EM_68HC05", Const, 11, ""}, {"EM_68HC08", Const, 11, ""}, {"EM_68HC11", Const, 11, ""}, {"EM_68HC12", Const, 0, ""}, {"EM_68HC16", Const, 11, ""}, {"EM_68K", Const, 0, ""}, {"EM_78KOR", Const, 11, ""}, {"EM_8051", Const, 11, ""}, {"EM_860", Const, 0, ""}, {"EM_88K", Const, 0, ""}, {"EM_960", Const, 0, ""}, {"EM_AARCH64", Const, 4, ""}, {"EM_ALPHA", Const, 0, ""}, {"EM_ALPHA_STD", Const, 0, ""}, {"EM_ALTERA_NIOS2", Const, 11, ""}, {"EM_AMDGPU", Const, 11, ""}, {"EM_ARC", Const, 0, ""}, {"EM_ARCA", Const, 11, ""}, {"EM_ARC_COMPACT", Const, 11, ""}, {"EM_ARC_COMPACT2", Const, 11, ""}, {"EM_ARM", Const, 0, ""}, {"EM_AVR", Const, 11, ""}, {"EM_AVR32", Const, 11, ""}, {"EM_BA1", Const, 11, ""}, {"EM_BA2", Const, 11, ""}, {"EM_BLACKFIN", Const, 11, ""}, {"EM_BPF", Const, 11, ""}, {"EM_C166", Const, 11, ""}, {"EM_CDP", Const, 11, ""}, {"EM_CE", Const, 11, ""}, {"EM_CLOUDSHIELD", Const, 11, ""}, {"EM_COGE", Const, 11, ""}, {"EM_COLDFIRE", Const, 0, ""}, {"EM_COOL", Const, 11, ""}, {"EM_COREA_1ST", Const, 11, ""}, {"EM_COREA_2ND", Const, 11, ""}, {"EM_CR", Const, 11, ""}, {"EM_CR16", Const, 11, ""}, {"EM_CRAYNV2", Const, 11, ""}, {"EM_CRIS", Const, 11, ""}, {"EM_CRX", Const, 11, ""}, {"EM_CSR_KALIMBA", Const, 11, ""}, {"EM_CUDA", Const, 11, ""}, {"EM_CYPRESS_M8C", Const, 11, ""}, {"EM_D10V", Const, 11, ""}, {"EM_D30V", Const, 11, ""}, {"EM_DSP24", Const, 11, ""}, {"EM_DSPIC30F", Const, 11, ""}, {"EM_DXP", Const, 11, ""}, {"EM_ECOG1", Const, 11, ""}, {"EM_ECOG16", Const, 11, ""}, {"EM_ECOG1X", Const, 11, ""}, {"EM_ECOG2", Const, 11, ""}, {"EM_ETPU", Const, 11, ""}, {"EM_EXCESS", Const, 11, ""}, {"EM_F2MC16", Const, 11, ""}, {"EM_FIREPATH", Const, 11, ""}, {"EM_FR20", Const, 0, ""}, {"EM_FR30", Const, 11, ""}, {"EM_FT32", Const, 11, ""}, {"EM_FX66", Const, 11, ""}, {"EM_H8S", Const, 0, ""}, {"EM_H8_300", Const, 0, ""}, {"EM_H8_300H", Const, 0, ""}, {"EM_H8_500", Const, 0, ""}, {"EM_HUANY", Const, 11, ""}, {"EM_IA_64", Const, 0, ""}, {"EM_INTEL205", Const, 11, ""}, {"EM_INTEL206", Const, 11, ""}, {"EM_INTEL207", Const, 11, ""}, {"EM_INTEL208", Const, 11, ""}, {"EM_INTEL209", Const, 11, ""}, {"EM_IP2K", Const, 11, ""}, {"EM_JAVELIN", Const, 11, ""}, {"EM_K10M", Const, 11, ""}, {"EM_KM32", Const, 11, ""}, {"EM_KMX16", Const, 11, ""}, {"EM_KMX32", Const, 11, ""}, {"EM_KMX8", Const, 11, ""}, {"EM_KVARC", Const, 11, ""}, {"EM_L10M", Const, 11, ""}, {"EM_LANAI", Const, 11, ""}, {"EM_LATTICEMICO32", Const, 11, ""}, {"EM_LOONGARCH", Const, 19, ""}, {"EM_M16C", Const, 11, ""}, {"EM_M32", Const, 0, ""}, {"EM_M32C", Const, 11, ""}, {"EM_M32R", Const, 11, ""}, {"EM_MANIK", Const, 11, ""}, {"EM_MAX", Const, 11, ""}, {"EM_MAXQ30", Const, 11, ""}, {"EM_MCHP_PIC", Const, 11, ""}, {"EM_MCST_ELBRUS", Const, 11, ""}, {"EM_ME16", Const, 0, ""}, {"EM_METAG", Const, 11, ""}, {"EM_MICROBLAZE", Const, 11, ""}, {"EM_MIPS", Const, 0, ""}, {"EM_MIPS_RS3_LE", Const, 0, ""}, {"EM_MIPS_RS4_BE", Const, 0, ""}, {"EM_MIPS_X", Const, 0, ""}, {"EM_MMA", Const, 0, ""}, {"EM_MMDSP_PLUS", Const, 11, ""}, {"EM_MMIX", Const, 11, ""}, {"EM_MN10200", Const, 11, ""}, {"EM_MN10300", Const, 11, ""}, {"EM_MOXIE", Const, 11, ""}, {"EM_MSP430", Const, 11, ""}, {"EM_NCPU", Const, 0, ""}, {"EM_NDR1", Const, 0, ""}, {"EM_NDS32", Const, 11, ""}, {"EM_NONE", Const, 0, ""}, {"EM_NORC", Const, 11, ""}, {"EM_NS32K", Const, 11, ""}, {"EM_OPEN8", Const, 11, ""}, {"EM_OPENRISC", Const, 11, ""}, {"EM_PARISC", Const, 0, ""}, {"EM_PCP", Const, 0, ""}, {"EM_PDP10", Const, 11, ""}, {"EM_PDP11", Const, 11, ""}, {"EM_PDSP", Const, 11, ""}, {"EM_PJ", Const, 11, ""}, {"EM_PPC", Const, 0, ""}, {"EM_PPC64", Const, 0, ""}, {"EM_PRISM", Const, 11, ""}, {"EM_QDSP6", Const, 11, ""}, {"EM_R32C", Const, 11, ""}, {"EM_RCE", Const, 0, ""}, {"EM_RH32", Const, 0, ""}, {"EM_RISCV", Const, 11, ""}, {"EM_RL78", Const, 11, ""}, {"EM_RS08", Const, 11, ""}, {"EM_RX", Const, 11, ""}, {"EM_S370", Const, 0, ""}, {"EM_S390", Const, 0, ""}, {"EM_SCORE7", Const, 11, ""}, {"EM_SEP", Const, 11, ""}, {"EM_SE_C17", Const, 11, ""}, {"EM_SE_C33", Const, 11, ""}, {"EM_SH", Const, 0, ""}, {"EM_SHARC", Const, 11, ""}, {"EM_SLE9X", Const, 11, ""}, {"EM_SNP1K", Const, 11, ""}, {"EM_SPARC", Const, 0, ""}, {"EM_SPARC32PLUS", Const, 0, ""}, {"EM_SPARCV9", Const, 0, ""}, {"EM_ST100", Const, 0, ""}, {"EM_ST19", Const, 11, ""}, {"EM_ST200", Const, 11, ""}, {"EM_ST7", Const, 11, ""}, {"EM_ST9PLUS", Const, 11, ""}, {"EM_STARCORE", Const, 0, ""}, {"EM_STM8", Const, 11, ""}, {"EM_STXP7X", Const, 11, ""}, {"EM_SVX", Const, 11, ""}, {"EM_TILE64", Const, 11, ""}, {"EM_TILEGX", Const, 11, ""}, {"EM_TILEPRO", Const, 11, ""}, {"EM_TINYJ", Const, 0, ""}, {"EM_TI_ARP32", Const, 11, ""}, {"EM_TI_C2000", Const, 11, ""}, {"EM_TI_C5500", Const, 11, ""}, {"EM_TI_C6000", Const, 11, ""}, {"EM_TI_PRU", Const, 11, ""}, {"EM_TMM_GPP", Const, 11, ""}, {"EM_TPC", Const, 11, ""}, {"EM_TRICORE", Const, 0, ""}, {"EM_TRIMEDIA", Const, 11, ""}, {"EM_TSK3000", Const, 11, ""}, {"EM_UNICORE", Const, 11, ""}, {"EM_V800", Const, 0, ""}, {"EM_V850", Const, 11, ""}, {"EM_VAX", Const, 11, ""}, {"EM_VIDEOCORE", Const, 11, ""}, {"EM_VIDEOCORE3", Const, 11, ""}, {"EM_VIDEOCORE5", Const, 11, ""}, {"EM_VISIUM", Const, 11, ""}, {"EM_VPP500", Const, 0, ""}, {"EM_X86_64", Const, 0, ""}, {"EM_XCORE", Const, 11, ""}, {"EM_XGATE", Const, 11, ""}, {"EM_XIMO16", Const, 11, ""}, {"EM_XTENSA", Const, 11, ""}, {"EM_Z80", Const, 11, ""}, {"EM_ZSP", Const, 11, ""}, {"ET_CORE", Const, 0, ""}, {"ET_DYN", Const, 0, ""}, {"ET_EXEC", Const, 0, ""}, {"ET_HIOS", Const, 0, ""}, {"ET_HIPROC", Const, 0, ""}, {"ET_LOOS", Const, 0, ""}, {"ET_LOPROC", Const, 0, ""}, {"ET_NONE", Const, 0, ""}, {"ET_REL", Const, 0, ""}, {"EV_CURRENT", Const, 0, ""}, {"EV_NONE", Const, 0, ""}, {"ErrNoSymbols", Var, 4, ""}, {"File", Type, 0, ""}, {"File.FileHeader", Field, 0, ""}, {"File.Progs", Field, 0, ""}, {"File.Sections", Field, 0, ""}, {"FileHeader", Type, 0, ""}, {"FileHeader.ABIVersion", Field, 0, ""}, {"FileHeader.ByteOrder", Field, 0, ""}, {"FileHeader.Class", Field, 0, ""}, {"FileHeader.Data", Field, 0, ""}, {"FileHeader.Entry", Field, 1, ""}, {"FileHeader.Machine", Field, 0, ""}, {"FileHeader.OSABI", Field, 0, ""}, {"FileHeader.Type", Field, 0, ""}, {"FileHeader.Version", Field, 0, ""}, {"FormatError", Type, 0, ""}, {"Header32", Type, 0, ""}, {"Header32.Ehsize", Field, 0, ""}, {"Header32.Entry", Field, 0, ""}, {"Header32.Flags", Field, 0, ""}, {"Header32.Ident", Field, 0, ""}, {"Header32.Machine", Field, 0, ""}, {"Header32.Phentsize", Field, 0, ""}, {"Header32.Phnum", Field, 0, ""}, {"Header32.Phoff", Field, 0, ""}, {"Header32.Shentsize", Field, 0, ""}, {"Header32.Shnum", Field, 0, ""}, {"Header32.Shoff", Field, 0, ""}, {"Header32.Shstrndx", Field, 0, ""}, {"Header32.Type", Field, 0, ""}, {"Header32.Version", Field, 0, ""}, {"Header64", Type, 0, ""}, {"Header64.Ehsize", Field, 0, ""}, {"Header64.Entry", Field, 0, ""}, {"Header64.Flags", Field, 0, ""}, {"Header64.Ident", Field, 0, ""}, {"Header64.Machine", Field, 0, ""}, {"Header64.Phentsize", Field, 0, ""}, {"Header64.Phnum", Field, 0, ""}, {"Header64.Phoff", Field, 0, ""}, {"Header64.Shentsize", Field, 0, ""}, {"Header64.Shnum", Field, 0, ""}, {"Header64.Shoff", Field, 0, ""}, {"Header64.Shstrndx", Field, 0, ""}, {"Header64.Type", Field, 0, ""}, {"Header64.Version", Field, 0, ""}, {"ImportedSymbol", Type, 0, ""}, {"ImportedSymbol.Library", Field, 0, ""}, {"ImportedSymbol.Name", Field, 0, ""}, {"ImportedSymbol.Version", Field, 0, ""}, {"Machine", Type, 0, ""}, {"NT_FPREGSET", Const, 0, ""}, {"NT_PRPSINFO", Const, 0, ""}, {"NT_PRSTATUS", Const, 0, ""}, {"NType", Type, 0, ""}, {"NewFile", Func, 0, "func(r io.ReaderAt) (*File, error)"}, {"OSABI", Type, 0, ""}, {"Open", Func, 0, "func(name string) (*File, error)"}, {"PF_MASKOS", Const, 0, ""}, {"PF_MASKPROC", Const, 0, ""}, {"PF_R", Const, 0, ""}, {"PF_W", Const, 0, ""}, {"PF_X", Const, 0, ""}, {"PT_AARCH64_ARCHEXT", Const, 16, ""}, {"PT_AARCH64_UNWIND", Const, 16, ""}, {"PT_ARM_ARCHEXT", Const, 16, ""}, {"PT_ARM_EXIDX", Const, 16, ""}, {"PT_DYNAMIC", Const, 0, ""}, {"PT_GNU_EH_FRAME", Const, 16, ""}, {"PT_GNU_MBIND_HI", Const, 16, ""}, {"PT_GNU_MBIND_LO", Const, 16, ""}, {"PT_GNU_PROPERTY", Const, 16, ""}, {"PT_GNU_RELRO", Const, 16, ""}, {"PT_GNU_STACK", Const, 16, ""}, {"PT_HIOS", Const, 0, ""}, {"PT_HIPROC", Const, 0, ""}, {"PT_INTERP", Const, 0, ""}, {"PT_LOAD", Const, 0, ""}, {"PT_LOOS", Const, 0, ""}, {"PT_LOPROC", Const, 0, ""}, {"PT_MIPS_ABIFLAGS", Const, 16, ""}, {"PT_MIPS_OPTIONS", Const, 16, ""}, {"PT_MIPS_REGINFO", Const, 16, ""}, {"PT_MIPS_RTPROC", Const, 16, ""}, {"PT_NOTE", Const, 0, ""}, {"PT_NULL", Const, 0, ""}, {"PT_OPENBSD_BOOTDATA", Const, 16, ""}, {"PT_OPENBSD_NOBTCFI", Const, 23, ""}, {"PT_OPENBSD_RANDOMIZE", Const, 16, ""}, {"PT_OPENBSD_WXNEEDED", Const, 16, ""}, {"PT_PAX_FLAGS", Const, 16, ""}, {"PT_PHDR", Const, 0, ""}, {"PT_RISCV_ATTRIBUTES", Const, 25, ""}, {"PT_S390_PGSTE", Const, 16, ""}, {"PT_SHLIB", Const, 0, ""}, {"PT_SUNWSTACK", Const, 16, ""}, {"PT_SUNW_EH_FRAME", Const, 16, ""}, {"PT_TLS", Const, 0, ""}, {"Prog", Type, 0, ""}, {"Prog.ProgHeader", Field, 0, ""}, {"Prog.ReaderAt", Field, 0, ""}, {"Prog32", Type, 0, ""}, {"Prog32.Align", Field, 0, ""}, {"Prog32.Filesz", Field, 0, ""}, {"Prog32.Flags", Field, 0, ""}, {"Prog32.Memsz", Field, 0, ""}, {"Prog32.Off", Field, 0, ""}, {"Prog32.Paddr", Field, 0, ""}, {"Prog32.Type", Field, 0, ""}, {"Prog32.Vaddr", Field, 0, ""}, {"Prog64", Type, 0, ""}, {"Prog64.Align", Field, 0, ""}, {"Prog64.Filesz", Field, 0, ""}, {"Prog64.Flags", Field, 0, ""}, {"Prog64.Memsz", Field, 0, ""}, {"Prog64.Off", Field, 0, ""}, {"Prog64.Paddr", Field, 0, ""}, {"Prog64.Type", Field, 0, ""}, {"Prog64.Vaddr", Field, 0, ""}, {"ProgFlag", Type, 0, ""}, {"ProgHeader", Type, 0, ""}, {"ProgHeader.Align", Field, 0, ""}, {"ProgHeader.Filesz", Field, 0, ""}, {"ProgHeader.Flags", Field, 0, ""}, {"ProgHeader.Memsz", Field, 0, ""}, {"ProgHeader.Off", Field, 0, ""}, {"ProgHeader.Paddr", Field, 0, ""}, {"ProgHeader.Type", Field, 0, ""}, {"ProgHeader.Vaddr", Field, 0, ""}, {"ProgType", Type, 0, ""}, {"R_386", Type, 0, ""}, {"R_386_16", Const, 10, ""}, {"R_386_32", Const, 0, ""}, {"R_386_32PLT", Const, 10, ""}, {"R_386_8", Const, 10, ""}, {"R_386_COPY", Const, 0, ""}, {"R_386_GLOB_DAT", Const, 0, ""}, {"R_386_GOT32", Const, 0, ""}, {"R_386_GOT32X", Const, 10, ""}, {"R_386_GOTOFF", Const, 0, ""}, {"R_386_GOTPC", Const, 0, ""}, {"R_386_IRELATIVE", Const, 10, ""}, {"R_386_JMP_SLOT", Const, 0, ""}, {"R_386_NONE", Const, 0, ""}, {"R_386_PC16", Const, 10, ""}, {"R_386_PC32", Const, 0, ""}, {"R_386_PC8", Const, 10, ""}, {"R_386_PLT32", Const, 0, ""}, {"R_386_RELATIVE", Const, 0, ""}, {"R_386_SIZE32", Const, 10, ""}, {"R_386_TLS_DESC", Const, 10, ""}, {"R_386_TLS_DESC_CALL", Const, 10, ""}, {"R_386_TLS_DTPMOD32", Const, 0, ""}, {"R_386_TLS_DTPOFF32", Const, 0, ""}, {"R_386_TLS_GD", Const, 0, ""}, {"R_386_TLS_GD_32", Const, 0, ""}, {"R_386_TLS_GD_CALL", Const, 0, ""}, {"R_386_TLS_GD_POP", Const, 0, ""}, {"R_386_TLS_GD_PUSH", Const, 0, ""}, {"R_386_TLS_GOTDESC", Const, 10, ""}, {"R_386_TLS_GOTIE", Const, 0, ""}, {"R_386_TLS_IE", Const, 0, ""}, {"R_386_TLS_IE_32", Const, 0, ""}, {"R_386_TLS_LDM", Const, 0, ""}, {"R_386_TLS_LDM_32", Const, 0, ""}, {"R_386_TLS_LDM_CALL", Const, 0, ""}, {"R_386_TLS_LDM_POP", Const, 0, ""}, {"R_386_TLS_LDM_PUSH", Const, 0, ""}, {"R_386_TLS_LDO_32", Const, 0, ""}, {"R_386_TLS_LE", Const, 0, ""}, {"R_386_TLS_LE_32", Const, 0, ""}, {"R_386_TLS_TPOFF", Const, 0, ""}, {"R_386_TLS_TPOFF32", Const, 0, ""}, {"R_390", Type, 7, ""}, {"R_390_12", Const, 7, ""}, {"R_390_16", Const, 7, ""}, {"R_390_20", Const, 7, ""}, {"R_390_32", Const, 7, ""}, {"R_390_64", Const, 7, ""}, {"R_390_8", Const, 7, ""}, {"R_390_COPY", Const, 7, ""}, {"R_390_GLOB_DAT", Const, 7, ""}, {"R_390_GOT12", Const, 7, ""}, {"R_390_GOT16", Const, 7, ""}, {"R_390_GOT20", Const, 7, ""}, {"R_390_GOT32", Const, 7, ""}, {"R_390_GOT64", Const, 7, ""}, {"R_390_GOTENT", Const, 7, ""}, {"R_390_GOTOFF", Const, 7, ""}, {"R_390_GOTOFF16", Const, 7, ""}, {"R_390_GOTOFF64", Const, 7, ""}, {"R_390_GOTPC", Const, 7, ""}, {"R_390_GOTPCDBL", Const, 7, ""}, {"R_390_GOTPLT12", Const, 7, ""}, {"R_390_GOTPLT16", Const, 7, ""}, {"R_390_GOTPLT20", Const, 7, ""}, {"R_390_GOTPLT32", Const, 7, ""}, {"R_390_GOTPLT64", Const, 7, ""}, {"R_390_GOTPLTENT", Const, 7, ""}, {"R_390_GOTPLTOFF16", Const, 7, ""}, {"R_390_GOTPLTOFF32", Const, 7, ""}, {"R_390_GOTPLTOFF64", Const, 7, ""}, {"R_390_JMP_SLOT", Const, 7, ""}, {"R_390_NONE", Const, 7, ""}, {"R_390_PC16", Const, 7, ""}, {"R_390_PC16DBL", Const, 7, ""}, {"R_390_PC32", Const, 7, ""}, {"R_390_PC32DBL", Const, 7, ""}, {"R_390_PC64", Const, 7, ""}, {"R_390_PLT16DBL", Const, 7, ""}, {"R_390_PLT32", Const, 7, ""}, {"R_390_PLT32DBL", Const, 7, ""}, {"R_390_PLT64", Const, 7, ""}, {"R_390_RELATIVE", Const, 7, ""}, {"R_390_TLS_DTPMOD", Const, 7, ""}, {"R_390_TLS_DTPOFF", Const, 7, ""}, {"R_390_TLS_GD32", Const, 7, ""}, {"R_390_TLS_GD64", Const, 7, ""}, {"R_390_TLS_GDCALL", Const, 7, ""}, {"R_390_TLS_GOTIE12", Const, 7, ""}, {"R_390_TLS_GOTIE20", Const, 7, ""}, {"R_390_TLS_GOTIE32", Const, 7, ""}, {"R_390_TLS_GOTIE64", Const, 7, ""}, {"R_390_TLS_IE32", Const, 7, ""}, {"R_390_TLS_IE64", Const, 7, ""}, {"R_390_TLS_IEENT", Const, 7, ""}, {"R_390_TLS_LDCALL", Const, 7, ""}, {"R_390_TLS_LDM32", Const, 7, ""}, {"R_390_TLS_LDM64", Const, 7, ""}, {"R_390_TLS_LDO32", Const, 7, ""}, {"R_390_TLS_LDO64", Const, 7, ""}, {"R_390_TLS_LE32", Const, 7, ""}, {"R_390_TLS_LE64", Const, 7, ""}, {"R_390_TLS_LOAD", Const, 7, ""}, {"R_390_TLS_TPOFF", Const, 7, ""}, {"R_AARCH64", Type, 4, ""}, {"R_AARCH64_ABS16", Const, 4, ""}, {"R_AARCH64_ABS32", Const, 4, ""}, {"R_AARCH64_ABS64", Const, 4, ""}, {"R_AARCH64_ADD_ABS_LO12_NC", Const, 4, ""}, {"R_AARCH64_ADR_GOT_PAGE", Const, 4, ""}, {"R_AARCH64_ADR_PREL_LO21", Const, 4, ""}, {"R_AARCH64_ADR_PREL_PG_HI21", Const, 4, ""}, {"R_AARCH64_ADR_PREL_PG_HI21_NC", Const, 4, ""}, {"R_AARCH64_CALL26", Const, 4, ""}, {"R_AARCH64_CONDBR19", Const, 4, ""}, {"R_AARCH64_COPY", Const, 4, ""}, {"R_AARCH64_GLOB_DAT", Const, 4, ""}, {"R_AARCH64_GOT_LD_PREL19", Const, 4, ""}, {"R_AARCH64_IRELATIVE", Const, 4, ""}, {"R_AARCH64_JUMP26", Const, 4, ""}, {"R_AARCH64_JUMP_SLOT", Const, 4, ""}, {"R_AARCH64_LD64_GOTOFF_LO15", Const, 10, ""}, {"R_AARCH64_LD64_GOTPAGE_LO15", Const, 10, ""}, {"R_AARCH64_LD64_GOT_LO12_NC", Const, 4, ""}, {"R_AARCH64_LDST128_ABS_LO12_NC", Const, 4, ""}, {"R_AARCH64_LDST16_ABS_LO12_NC", Const, 4, ""}, {"R_AARCH64_LDST32_ABS_LO12_NC", Const, 4, ""}, {"R_AARCH64_LDST64_ABS_LO12_NC", Const, 4, ""}, {"R_AARCH64_LDST8_ABS_LO12_NC", Const, 4, ""}, {"R_AARCH64_LD_PREL_LO19", Const, 4, ""}, {"R_AARCH64_MOVW_SABS_G0", Const, 4, ""}, {"R_AARCH64_MOVW_SABS_G1", Const, 4, ""}, {"R_AARCH64_MOVW_SABS_G2", Const, 4, ""}, {"R_AARCH64_MOVW_UABS_G0", Const, 4, ""}, {"R_AARCH64_MOVW_UABS_G0_NC", Const, 4, ""}, {"R_AARCH64_MOVW_UABS_G1", Const, 4, ""}, {"R_AARCH64_MOVW_UABS_G1_NC", Const, 4, ""}, {"R_AARCH64_MOVW_UABS_G2", Const, 4, ""}, {"R_AARCH64_MOVW_UABS_G2_NC", Const, 4, ""}, {"R_AARCH64_MOVW_UABS_G3", Const, 4, ""}, {"R_AARCH64_NONE", Const, 4, ""}, {"R_AARCH64_NULL", Const, 4, ""}, {"R_AARCH64_P32_ABS16", Const, 4, ""}, {"R_AARCH64_P32_ABS32", Const, 4, ""}, {"R_AARCH64_P32_ADD_ABS_LO12_NC", Const, 4, ""}, {"R_AARCH64_P32_ADR_GOT_PAGE", Const, 4, ""}, {"R_AARCH64_P32_ADR_PREL_LO21", Const, 4, ""}, {"R_AARCH64_P32_ADR_PREL_PG_HI21", Const, 4, ""}, {"R_AARCH64_P32_CALL26", Const, 4, ""}, {"R_AARCH64_P32_CONDBR19", Const, 4, ""}, {"R_AARCH64_P32_COPY", Const, 4, ""}, {"R_AARCH64_P32_GLOB_DAT", Const, 4, ""}, {"R_AARCH64_P32_GOT_LD_PREL19", Const, 4, ""}, {"R_AARCH64_P32_IRELATIVE", Const, 4, ""}, {"R_AARCH64_P32_JUMP26", Const, 4, ""}, {"R_AARCH64_P32_JUMP_SLOT", Const, 4, ""}, {"R_AARCH64_P32_LD32_GOT_LO12_NC", Const, 4, ""}, {"R_AARCH64_P32_LDST128_ABS_LO12_NC", Const, 4, ""}, {"R_AARCH64_P32_LDST16_ABS_LO12_NC", Const, 4, ""}, {"R_AARCH64_P32_LDST32_ABS_LO12_NC", Const, 4, ""}, {"R_AARCH64_P32_LDST64_ABS_LO12_NC", Const, 4, ""}, {"R_AARCH64_P32_LDST8_ABS_LO12_NC", Const, 4, ""}, {"R_AARCH64_P32_LD_PREL_LO19", Const, 4, ""}, {"R_AARCH64_P32_MOVW_SABS_G0", Const, 4, ""}, {"R_AARCH64_P32_MOVW_UABS_G0", Const, 4, ""}, {"R_AARCH64_P32_MOVW_UABS_G0_NC", Const, 4, ""}, {"R_AARCH64_P32_MOVW_UABS_G1", Const, 4, ""}, {"R_AARCH64_P32_PREL16", Const, 4, ""}, {"R_AARCH64_P32_PREL32", Const, 4, ""}, {"R_AARCH64_P32_RELATIVE", Const, 4, ""}, {"R_AARCH64_P32_TLSDESC", Const, 4, ""}, {"R_AARCH64_P32_TLSDESC_ADD_LO12_NC", Const, 4, ""}, {"R_AARCH64_P32_TLSDESC_ADR_PAGE21", Const, 4, ""}, {"R_AARCH64_P32_TLSDESC_ADR_PREL21", Const, 4, ""}, {"R_AARCH64_P32_TLSDESC_CALL", Const, 4, ""}, {"R_AARCH64_P32_TLSDESC_LD32_LO12_NC", Const, 4, ""}, {"R_AARCH64_P32_TLSDESC_LD_PREL19", Const, 4, ""}, {"R_AARCH64_P32_TLSGD_ADD_LO12_NC", Const, 4, ""}, {"R_AARCH64_P32_TLSGD_ADR_PAGE21", Const, 4, ""}, {"R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21", Const, 4, ""}, {"R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC", Const, 4, ""}, {"R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19", Const, 4, ""}, {"R_AARCH64_P32_TLSLE_ADD_TPREL_HI12", Const, 4, ""}, {"R_AARCH64_P32_TLSLE_ADD_TPREL_LO12", Const, 4, ""}, {"R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC", Const, 4, ""}, {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G0", Const, 4, ""}, {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC", Const, 4, ""}, {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G1", Const, 4, ""}, {"R_AARCH64_P32_TLS_DTPMOD", Const, 4, ""}, {"R_AARCH64_P32_TLS_DTPREL", Const, 4, ""}, {"R_AARCH64_P32_TLS_TPREL", Const, 4, ""}, {"R_AARCH64_P32_TSTBR14", Const, 4, ""}, {"R_AARCH64_PREL16", Const, 4, ""}, {"R_AARCH64_PREL32", Const, 4, ""}, {"R_AARCH64_PREL64", Const, 4, ""}, {"R_AARCH64_RELATIVE", Const, 4, ""}, {"R_AARCH64_TLSDESC", Const, 4, ""}, {"R_AARCH64_TLSDESC_ADD", Const, 4, ""}, {"R_AARCH64_TLSDESC_ADD_LO12_NC", Const, 4, ""}, {"R_AARCH64_TLSDESC_ADR_PAGE21", Const, 4, ""}, {"R_AARCH64_TLSDESC_ADR_PREL21", Const, 4, ""}, {"R_AARCH64_TLSDESC_CALL", Const, 4, ""}, {"R_AARCH64_TLSDESC_LD64_LO12_NC", Const, 4, ""}, {"R_AARCH64_TLSDESC_LDR", Const, 4, ""}, {"R_AARCH64_TLSDESC_LD_PREL19", Const, 4, ""}, {"R_AARCH64_TLSDESC_OFF_G0_NC", Const, 4, ""}, {"R_AARCH64_TLSDESC_OFF_G1", Const, 4, ""}, {"R_AARCH64_TLSGD_ADD_LO12_NC", Const, 4, ""}, {"R_AARCH64_TLSGD_ADR_PAGE21", Const, 4, ""}, {"R_AARCH64_TLSGD_ADR_PREL21", Const, 10, ""}, {"R_AARCH64_TLSGD_MOVW_G0_NC", Const, 10, ""}, {"R_AARCH64_TLSGD_MOVW_G1", Const, 10, ""}, {"R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21", Const, 4, ""}, {"R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC", Const, 4, ""}, {"R_AARCH64_TLSIE_LD_GOTTPREL_PREL19", Const, 4, ""}, {"R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC", Const, 4, ""}, {"R_AARCH64_TLSIE_MOVW_GOTTPREL_G1", Const, 4, ""}, {"R_AARCH64_TLSLD_ADR_PAGE21", Const, 10, ""}, {"R_AARCH64_TLSLD_ADR_PREL21", Const, 10, ""}, {"R_AARCH64_TLSLD_LDST128_DTPREL_LO12", Const, 10, ""}, {"R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC", Const, 10, ""}, {"R_AARCH64_TLSLE_ADD_TPREL_HI12", Const, 4, ""}, {"R_AARCH64_TLSLE_ADD_TPREL_LO12", Const, 4, ""}, {"R_AARCH64_TLSLE_ADD_TPREL_LO12_NC", Const, 4, ""}, {"R_AARCH64_TLSLE_LDST128_TPREL_LO12", Const, 10, ""}, {"R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC", Const, 10, ""}, {"R_AARCH64_TLSLE_MOVW_TPREL_G0", Const, 4, ""}, {"R_AARCH64_TLSLE_MOVW_TPREL_G0_NC", Const, 4, ""}, {"R_AARCH64_TLSLE_MOVW_TPREL_G1", Const, 4, ""}, {"R_AARCH64_TLSLE_MOVW_TPREL_G1_NC", Const, 4, ""}, {"R_AARCH64_TLSLE_MOVW_TPREL_G2", Const, 4, ""}, {"R_AARCH64_TLS_DTPMOD64", Const, 4, ""}, {"R_AARCH64_TLS_DTPREL64", Const, 4, ""}, {"R_AARCH64_TLS_TPREL64", Const, 4, ""}, {"R_AARCH64_TSTBR14", Const, 4, ""}, {"R_ALPHA", Type, 0, ""}, {"R_ALPHA_BRADDR", Const, 0, ""}, {"R_ALPHA_COPY", Const, 0, ""}, {"R_ALPHA_GLOB_DAT", Const, 0, ""}, {"R_ALPHA_GPDISP", Const, 0, ""}, {"R_ALPHA_GPREL32", Const, 0, ""}, {"R_ALPHA_GPRELHIGH", Const, 0, ""}, {"R_ALPHA_GPRELLOW", Const, 0, ""}, {"R_ALPHA_GPVALUE", Const, 0, ""}, {"R_ALPHA_HINT", Const, 0, ""}, {"R_ALPHA_IMMED_BR_HI32", Const, 0, ""}, {"R_ALPHA_IMMED_GP_16", Const, 0, ""}, {"R_ALPHA_IMMED_GP_HI32", Const, 0, ""}, {"R_ALPHA_IMMED_LO32", Const, 0, ""}, {"R_ALPHA_IMMED_SCN_HI32", Const, 0, ""}, {"R_ALPHA_JMP_SLOT", Const, 0, ""}, {"R_ALPHA_LITERAL", Const, 0, ""}, {"R_ALPHA_LITUSE", Const, 0, ""}, {"R_ALPHA_NONE", Const, 0, ""}, {"R_ALPHA_OP_PRSHIFT", Const, 0, ""}, {"R_ALPHA_OP_PSUB", Const, 0, ""}, {"R_ALPHA_OP_PUSH", Const, 0, ""}, {"R_ALPHA_OP_STORE", Const, 0, ""}, {"R_ALPHA_REFLONG", Const, 0, ""}, {"R_ALPHA_REFQUAD", Const, 0, ""}, {"R_ALPHA_RELATIVE", Const, 0, ""}, {"R_ALPHA_SREL16", Const, 0, ""}, {"R_ALPHA_SREL32", Const, 0, ""}, {"R_ALPHA_SREL64", Const, 0, ""}, {"R_ARM", Type, 0, ""}, {"R_ARM_ABS12", Const, 0, ""}, {"R_ARM_ABS16", Const, 0, ""}, {"R_ARM_ABS32", Const, 0, ""}, {"R_ARM_ABS32_NOI", Const, 10, ""}, {"R_ARM_ABS8", Const, 0, ""}, {"R_ARM_ALU_PCREL_15_8", Const, 10, ""}, {"R_ARM_ALU_PCREL_23_15", Const, 10, ""}, {"R_ARM_ALU_PCREL_7_0", Const, 10, ""}, {"R_ARM_ALU_PC_G0", Const, 10, ""}, {"R_ARM_ALU_PC_G0_NC", Const, 10, ""}, {"R_ARM_ALU_PC_G1", Const, 10, ""}, {"R_ARM_ALU_PC_G1_NC", Const, 10, ""}, {"R_ARM_ALU_PC_G2", Const, 10, ""}, {"R_ARM_ALU_SBREL_19_12_NC", Const, 10, ""}, {"R_ARM_ALU_SBREL_27_20_CK", Const, 10, ""}, {"R_ARM_ALU_SB_G0", Const, 10, ""}, {"R_ARM_ALU_SB_G0_NC", Const, 10, ""}, {"R_ARM_ALU_SB_G1", Const, 10, ""}, {"R_ARM_ALU_SB_G1_NC", Const, 10, ""}, {"R_ARM_ALU_SB_G2", Const, 10, ""}, {"R_ARM_AMP_VCALL9", Const, 0, ""}, {"R_ARM_BASE_ABS", Const, 10, ""}, {"R_ARM_CALL", Const, 10, ""}, {"R_ARM_COPY", Const, 0, ""}, {"R_ARM_GLOB_DAT", Const, 0, ""}, {"R_ARM_GNU_VTENTRY", Const, 0, ""}, {"R_ARM_GNU_VTINHERIT", Const, 0, ""}, {"R_ARM_GOT32", Const, 0, ""}, {"R_ARM_GOTOFF", Const, 0, ""}, {"R_ARM_GOTOFF12", Const, 10, ""}, {"R_ARM_GOTPC", Const, 0, ""}, {"R_ARM_GOTRELAX", Const, 10, ""}, {"R_ARM_GOT_ABS", Const, 10, ""}, {"R_ARM_GOT_BREL12", Const, 10, ""}, {"R_ARM_GOT_PREL", Const, 10, ""}, {"R_ARM_IRELATIVE", Const, 10, ""}, {"R_ARM_JUMP24", Const, 10, ""}, {"R_ARM_JUMP_SLOT", Const, 0, ""}, {"R_ARM_LDC_PC_G0", Const, 10, ""}, {"R_ARM_LDC_PC_G1", Const, 10, ""}, {"R_ARM_LDC_PC_G2", Const, 10, ""}, {"R_ARM_LDC_SB_G0", Const, 10, ""}, {"R_ARM_LDC_SB_G1", Const, 10, ""}, {"R_ARM_LDC_SB_G2", Const, 10, ""}, {"R_ARM_LDRS_PC_G0", Const, 10, ""}, {"R_ARM_LDRS_PC_G1", Const, 10, ""}, {"R_ARM_LDRS_PC_G2", Const, 10, ""}, {"R_ARM_LDRS_SB_G0", Const, 10, ""}, {"R_ARM_LDRS_SB_G1", Const, 10, ""}, {"R_ARM_LDRS_SB_G2", Const, 10, ""}, {"R_ARM_LDR_PC_G1", Const, 10, ""}, {"R_ARM_LDR_PC_G2", Const, 10, ""}, {"R_ARM_LDR_SBREL_11_10_NC", Const, 10, ""}, {"R_ARM_LDR_SB_G0", Const, 10, ""}, {"R_ARM_LDR_SB_G1", Const, 10, ""}, {"R_ARM_LDR_SB_G2", Const, 10, ""}, {"R_ARM_ME_TOO", Const, 10, ""}, {"R_ARM_MOVT_ABS", Const, 10, ""}, {"R_ARM_MOVT_BREL", Const, 10, ""}, {"R_ARM_MOVT_PREL", Const, 10, ""}, {"R_ARM_MOVW_ABS_NC", Const, 10, ""}, {"R_ARM_MOVW_BREL", Const, 10, ""}, {"R_ARM_MOVW_BREL_NC", Const, 10, ""}, {"R_ARM_MOVW_PREL_NC", Const, 10, ""}, {"R_ARM_NONE", Const, 0, ""}, {"R_ARM_PC13", Const, 0, ""}, {"R_ARM_PC24", Const, 0, ""}, {"R_ARM_PLT32", Const, 0, ""}, {"R_ARM_PLT32_ABS", Const, 10, ""}, {"R_ARM_PREL31", Const, 10, ""}, {"R_ARM_PRIVATE_0", Const, 10, ""}, {"R_ARM_PRIVATE_1", Const, 10, ""}, {"R_ARM_PRIVATE_10", Const, 10, ""}, {"R_ARM_PRIVATE_11", Const, 10, ""}, {"R_ARM_PRIVATE_12", Const, 10, ""}, {"R_ARM_PRIVATE_13", Const, 10, ""}, {"R_ARM_PRIVATE_14", Const, 10, ""}, {"R_ARM_PRIVATE_15", Const, 10, ""}, {"R_ARM_PRIVATE_2", Const, 10, ""}, {"R_ARM_PRIVATE_3", Const, 10, ""}, {"R_ARM_PRIVATE_4", Const, 10, ""}, {"R_ARM_PRIVATE_5", Const, 10, ""}, {"R_ARM_PRIVATE_6", Const, 10, ""}, {"R_ARM_PRIVATE_7", Const, 10, ""}, {"R_ARM_PRIVATE_8", Const, 10, ""}, {"R_ARM_PRIVATE_9", Const, 10, ""}, {"R_ARM_RABS32", Const, 0, ""}, {"R_ARM_RBASE", Const, 0, ""}, {"R_ARM_REL32", Const, 0, ""}, {"R_ARM_REL32_NOI", Const, 10, ""}, {"R_ARM_RELATIVE", Const, 0, ""}, {"R_ARM_RPC24", Const, 0, ""}, {"R_ARM_RREL32", Const, 0, ""}, {"R_ARM_RSBREL32", Const, 0, ""}, {"R_ARM_RXPC25", Const, 10, ""}, {"R_ARM_SBREL31", Const, 10, ""}, {"R_ARM_SBREL32", Const, 0, ""}, {"R_ARM_SWI24", Const, 0, ""}, {"R_ARM_TARGET1", Const, 10, ""}, {"R_ARM_TARGET2", Const, 10, ""}, {"R_ARM_THM_ABS5", Const, 0, ""}, {"R_ARM_THM_ALU_ABS_G0_NC", Const, 10, ""}, {"R_ARM_THM_ALU_ABS_G1_NC", Const, 10, ""}, {"R_ARM_THM_ALU_ABS_G2_NC", Const, 10, ""}, {"R_ARM_THM_ALU_ABS_G3", Const, 10, ""}, {"R_ARM_THM_ALU_PREL_11_0", Const, 10, ""}, {"R_ARM_THM_GOT_BREL12", Const, 10, ""}, {"R_ARM_THM_JUMP11", Const, 10, ""}, {"R_ARM_THM_JUMP19", Const, 10, ""}, {"R_ARM_THM_JUMP24", Const, 10, ""}, {"R_ARM_THM_JUMP6", Const, 10, ""}, {"R_ARM_THM_JUMP8", Const, 10, ""}, {"R_ARM_THM_MOVT_ABS", Const, 10, ""}, {"R_ARM_THM_MOVT_BREL", Const, 10, ""}, {"R_ARM_THM_MOVT_PREL", Const, 10, ""}, {"R_ARM_THM_MOVW_ABS_NC", Const, 10, ""}, {"R_ARM_THM_MOVW_BREL", Const, 10, ""}, {"R_ARM_THM_MOVW_BREL_NC", Const, 10, ""}, {"R_ARM_THM_MOVW_PREL_NC", Const, 10, ""}, {"R_ARM_THM_PC12", Const, 10, ""}, {"R_ARM_THM_PC22", Const, 0, ""}, {"R_ARM_THM_PC8", Const, 0, ""}, {"R_ARM_THM_RPC22", Const, 0, ""}, {"R_ARM_THM_SWI8", Const, 0, ""}, {"R_ARM_THM_TLS_CALL", Const, 10, ""}, {"R_ARM_THM_TLS_DESCSEQ16", Const, 10, ""}, {"R_ARM_THM_TLS_DESCSEQ32", Const, 10, ""}, {"R_ARM_THM_XPC22", Const, 0, ""}, {"R_ARM_TLS_CALL", Const, 10, ""}, {"R_ARM_TLS_DESCSEQ", Const, 10, ""}, {"R_ARM_TLS_DTPMOD32", Const, 10, ""}, {"R_ARM_TLS_DTPOFF32", Const, 10, ""}, {"R_ARM_TLS_GD32", Const, 10, ""}, {"R_ARM_TLS_GOTDESC", Const, 10, ""}, {"R_ARM_TLS_IE12GP", Const, 10, ""}, {"R_ARM_TLS_IE32", Const, 10, ""}, {"R_ARM_TLS_LDM32", Const, 10, ""}, {"R_ARM_TLS_LDO12", Const, 10, ""}, {"R_ARM_TLS_LDO32", Const, 10, ""}, {"R_ARM_TLS_LE12", Const, 10, ""}, {"R_ARM_TLS_LE32", Const, 10, ""}, {"R_ARM_TLS_TPOFF32", Const, 10, ""}, {"R_ARM_V4BX", Const, 10, ""}, {"R_ARM_XPC25", Const, 0, ""}, {"R_INFO", Func, 0, "func(sym uint32, typ uint32) uint64"}, {"R_INFO32", Func, 0, "func(sym uint32, typ uint32) uint32"}, {"R_LARCH", Type, 19, ""}, {"R_LARCH_32", Const, 19, ""}, {"R_LARCH_32_PCREL", Const, 20, ""}, {"R_LARCH_64", Const, 19, ""}, {"R_LARCH_64_PCREL", Const, 22, ""}, {"R_LARCH_ABS64_HI12", Const, 20, ""}, {"R_LARCH_ABS64_LO20", Const, 20, ""}, {"R_LARCH_ABS_HI20", Const, 20, ""}, {"R_LARCH_ABS_LO12", Const, 20, ""}, {"R_LARCH_ADD16", Const, 19, ""}, {"R_LARCH_ADD24", Const, 19, ""}, {"R_LARCH_ADD32", Const, 19, ""}, {"R_LARCH_ADD6", Const, 22, ""}, {"R_LARCH_ADD64", Const, 19, ""}, {"R_LARCH_ADD8", Const, 19, ""}, {"R_LARCH_ADD_ULEB128", Const, 22, ""}, {"R_LARCH_ALIGN", Const, 22, ""}, {"R_LARCH_B16", Const, 20, ""}, {"R_LARCH_B21", Const, 20, ""}, {"R_LARCH_B26", Const, 20, ""}, {"R_LARCH_CFA", Const, 22, ""}, {"R_LARCH_COPY", Const, 19, ""}, {"R_LARCH_DELETE", Const, 22, ""}, {"R_LARCH_GNU_VTENTRY", Const, 20, ""}, {"R_LARCH_GNU_VTINHERIT", Const, 20, ""}, {"R_LARCH_GOT64_HI12", Const, 20, ""}, {"R_LARCH_GOT64_LO20", Const, 20, ""}, {"R_LARCH_GOT64_PC_HI12", Const, 20, ""}, {"R_LARCH_GOT64_PC_LO20", Const, 20, ""}, {"R_LARCH_GOT_HI20", Const, 20, ""}, {"R_LARCH_GOT_LO12", Const, 20, ""}, {"R_LARCH_GOT_PC_HI20", Const, 20, ""}, {"R_LARCH_GOT_PC_LO12", Const, 20, ""}, {"R_LARCH_IRELATIVE", Const, 19, ""}, {"R_LARCH_JUMP_SLOT", Const, 19, ""}, {"R_LARCH_MARK_LA", Const, 19, ""}, {"R_LARCH_MARK_PCREL", Const, 19, ""}, {"R_LARCH_NONE", Const, 19, ""}, {"R_LARCH_PCALA64_HI12", Const, 20, ""}, {"R_LARCH_PCALA64_LO20", Const, 20, ""}, {"R_LARCH_PCALA_HI20", Const, 20, ""}, {"R_LARCH_PCALA_LO12", Const, 20, ""}, {"R_LARCH_PCREL20_S2", Const, 22, ""}, {"R_LARCH_RELATIVE", Const, 19, ""}, {"R_LARCH_RELAX", Const, 20, ""}, {"R_LARCH_SOP_ADD", Const, 19, ""}, {"R_LARCH_SOP_AND", Const, 19, ""}, {"R_LARCH_SOP_ASSERT", Const, 19, ""}, {"R_LARCH_SOP_IF_ELSE", Const, 19, ""}, {"R_LARCH_SOP_NOT", Const, 19, ""}, {"R_LARCH_SOP_POP_32_S_0_10_10_16_S2", Const, 19, ""}, {"R_LARCH_SOP_POP_32_S_0_5_10_16_S2", Const, 19, ""}, {"R_LARCH_SOP_POP_32_S_10_12", Const, 19, ""}, {"R_LARCH_SOP_POP_32_S_10_16", Const, 19, ""}, {"R_LARCH_SOP_POP_32_S_10_16_S2", Const, 19, ""}, {"R_LARCH_SOP_POP_32_S_10_5", Const, 19, ""}, {"R_LARCH_SOP_POP_32_S_5_20", Const, 19, ""}, {"R_LARCH_SOP_POP_32_U", Const, 19, ""}, {"R_LARCH_SOP_POP_32_U_10_12", Const, 19, ""}, {"R_LARCH_SOP_PUSH_ABSOLUTE", Const, 19, ""}, {"R_LARCH_SOP_PUSH_DUP", Const, 19, ""}, {"R_LARCH_SOP_PUSH_GPREL", Const, 19, ""}, {"R_LARCH_SOP_PUSH_PCREL", Const, 19, ""}, {"R_LARCH_SOP_PUSH_PLT_PCREL", Const, 19, ""}, {"R_LARCH_SOP_PUSH_TLS_GD", Const, 19, ""}, {"R_LARCH_SOP_PUSH_TLS_GOT", Const, 19, ""}, {"R_LARCH_SOP_PUSH_TLS_TPREL", Const, 19, ""}, {"R_LARCH_SOP_SL", Const, 19, ""}, {"R_LARCH_SOP_SR", Const, 19, ""}, {"R_LARCH_SOP_SUB", Const, 19, ""}, {"R_LARCH_SUB16", Const, 19, ""}, {"R_LARCH_SUB24", Const, 19, ""}, {"R_LARCH_SUB32", Const, 19, ""}, {"R_LARCH_SUB6", Const, 22, ""}, {"R_LARCH_SUB64", Const, 19, ""}, {"R_LARCH_SUB8", Const, 19, ""}, {"R_LARCH_SUB_ULEB128", Const, 22, ""}, {"R_LARCH_TLS_DTPMOD32", Const, 19, ""}, {"R_LARCH_TLS_DTPMOD64", Const, 19, ""}, {"R_LARCH_TLS_DTPREL32", Const, 19, ""}, {"R_LARCH_TLS_DTPREL64", Const, 19, ""}, {"R_LARCH_TLS_GD_HI20", Const, 20, ""}, {"R_LARCH_TLS_GD_PC_HI20", Const, 20, ""}, {"R_LARCH_TLS_IE64_HI12", Const, 20, ""}, {"R_LARCH_TLS_IE64_LO20", Const, 20, ""}, {"R_LARCH_TLS_IE64_PC_HI12", Const, 20, ""}, {"R_LARCH_TLS_IE64_PC_LO20", Const, 20, ""}, {"R_LARCH_TLS_IE_HI20", Const, 20, ""}, {"R_LARCH_TLS_IE_LO12", Const, 20, ""}, {"R_LARCH_TLS_IE_PC_HI20", Const, 20, ""}, {"R_LARCH_TLS_IE_PC_LO12", Const, 20, ""}, {"R_LARCH_TLS_LD_HI20", Const, 20, ""}, {"R_LARCH_TLS_LD_PC_HI20", Const, 20, ""}, {"R_LARCH_TLS_LE64_HI12", Const, 20, ""}, {"R_LARCH_TLS_LE64_LO20", Const, 20, ""}, {"R_LARCH_TLS_LE_HI20", Const, 20, ""}, {"R_LARCH_TLS_LE_LO12", Const, 20, ""}, {"R_LARCH_TLS_TPREL32", Const, 19, ""}, {"R_LARCH_TLS_TPREL64", Const, 19, ""}, {"R_MIPS", Type, 6, ""}, {"R_MIPS_16", Const, 6, ""}, {"R_MIPS_26", Const, 6, ""}, {"R_MIPS_32", Const, 6, ""}, {"R_MIPS_64", Const, 6, ""}, {"R_MIPS_ADD_IMMEDIATE", Const, 6, ""}, {"R_MIPS_CALL16", Const, 6, ""}, {"R_MIPS_CALL_HI16", Const, 6, ""}, {"R_MIPS_CALL_LO16", Const, 6, ""}, {"R_MIPS_DELETE", Const, 6, ""}, {"R_MIPS_GOT16", Const, 6, ""}, {"R_MIPS_GOT_DISP", Const, 6, ""}, {"R_MIPS_GOT_HI16", Const, 6, ""}, {"R_MIPS_GOT_LO16", Const, 6, ""}, {"R_MIPS_GOT_OFST", Const, 6, ""}, {"R_MIPS_GOT_PAGE", Const, 6, ""}, {"R_MIPS_GPREL16", Const, 6, ""}, {"R_MIPS_GPREL32", Const, 6, ""}, {"R_MIPS_HI16", Const, 6, ""}, {"R_MIPS_HIGHER", Const, 6, ""}, {"R_MIPS_HIGHEST", Const, 6, ""}, {"R_MIPS_INSERT_A", Const, 6, ""}, {"R_MIPS_INSERT_B", Const, 6, ""}, {"R_MIPS_JALR", Const, 6, ""}, {"R_MIPS_LITERAL", Const, 6, ""}, {"R_MIPS_LO16", Const, 6, ""}, {"R_MIPS_NONE", Const, 6, ""}, {"R_MIPS_PC16", Const, 6, ""}, {"R_MIPS_PC32", Const, 22, ""}, {"R_MIPS_PJUMP", Const, 6, ""}, {"R_MIPS_REL16", Const, 6, ""}, {"R_MIPS_REL32", Const, 6, ""}, {"R_MIPS_RELGOT", Const, 6, ""}, {"R_MIPS_SCN_DISP", Const, 6, ""}, {"R_MIPS_SHIFT5", Const, 6, ""}, {"R_MIPS_SHIFT6", Const, 6, ""}, {"R_MIPS_SUB", Const, 6, ""}, {"R_MIPS_TLS_DTPMOD32", Const, 6, ""}, {"R_MIPS_TLS_DTPMOD64", Const, 6, ""}, {"R_MIPS_TLS_DTPREL32", Const, 6, ""}, {"R_MIPS_TLS_DTPREL64", Const, 6, ""}, {"R_MIPS_TLS_DTPREL_HI16", Const, 6, ""}, {"R_MIPS_TLS_DTPREL_LO16", Const, 6, ""}, {"R_MIPS_TLS_GD", Const, 6, ""}, {"R_MIPS_TLS_GOTTPREL", Const, 6, ""}, {"R_MIPS_TLS_LDM", Const, 6, ""}, {"R_MIPS_TLS_TPREL32", Const, 6, ""}, {"R_MIPS_TLS_TPREL64", Const, 6, ""}, {"R_MIPS_TLS_TPREL_HI16", Const, 6, ""}, {"R_MIPS_TLS_TPREL_LO16", Const, 6, ""}, {"R_PPC", Type, 0, ""}, {"R_PPC64", Type, 5, ""}, {"R_PPC64_ADDR14", Const, 5, ""}, {"R_PPC64_ADDR14_BRNTAKEN", Const, 5, ""}, {"R_PPC64_ADDR14_BRTAKEN", Const, 5, ""}, {"R_PPC64_ADDR16", Const, 5, ""}, {"R_PPC64_ADDR16_DS", Const, 5, ""}, {"R_PPC64_ADDR16_HA", Const, 5, ""}, {"R_PPC64_ADDR16_HI", Const, 5, ""}, {"R_PPC64_ADDR16_HIGH", Const, 10, ""}, {"R_PPC64_ADDR16_HIGHA", Const, 10, ""}, {"R_PPC64_ADDR16_HIGHER", Const, 5, ""}, {"R_PPC64_ADDR16_HIGHER34", Const, 20, ""}, {"R_PPC64_ADDR16_HIGHERA", Const, 5, ""}, {"R_PPC64_ADDR16_HIGHERA34", Const, 20, ""}, {"R_PPC64_ADDR16_HIGHEST", Const, 5, ""}, {"R_PPC64_ADDR16_HIGHEST34", Const, 20, ""}, {"R_PPC64_ADDR16_HIGHESTA", Const, 5, ""}, {"R_PPC64_ADDR16_HIGHESTA34", Const, 20, ""}, {"R_PPC64_ADDR16_LO", Const, 5, ""}, {"R_PPC64_ADDR16_LO_DS", Const, 5, ""}, {"R_PPC64_ADDR24", Const, 5, ""}, {"R_PPC64_ADDR32", Const, 5, ""}, {"R_PPC64_ADDR64", Const, 5, ""}, {"R_PPC64_ADDR64_LOCAL", Const, 10, ""}, {"R_PPC64_COPY", Const, 20, ""}, {"R_PPC64_D28", Const, 20, ""}, {"R_PPC64_D34", Const, 20, ""}, {"R_PPC64_D34_HA30", Const, 20, ""}, {"R_PPC64_D34_HI30", Const, 20, ""}, {"R_PPC64_D34_LO", Const, 20, ""}, {"R_PPC64_DTPMOD64", Const, 5, ""}, {"R_PPC64_DTPREL16", Const, 5, ""}, {"R_PPC64_DTPREL16_DS", Const, 5, ""}, {"R_PPC64_DTPREL16_HA", Const, 5, ""}, {"R_PPC64_DTPREL16_HI", Const, 5, ""}, {"R_PPC64_DTPREL16_HIGH", Const, 10, ""}, {"R_PPC64_DTPREL16_HIGHA", Const, 10, ""}, {"R_PPC64_DTPREL16_HIGHER", Const, 5, ""}, {"R_PPC64_DTPREL16_HIGHERA", Const, 5, ""}, {"R_PPC64_DTPREL16_HIGHEST", Const, 5, ""}, {"R_PPC64_DTPREL16_HIGHESTA", Const, 5, ""}, {"R_PPC64_DTPREL16_LO", Const, 5, ""}, {"R_PPC64_DTPREL16_LO_DS", Const, 5, ""}, {"R_PPC64_DTPREL34", Const, 20, ""}, {"R_PPC64_DTPREL64", Const, 5, ""}, {"R_PPC64_ENTRY", Const, 10, ""}, {"R_PPC64_GLOB_DAT", Const, 20, ""}, {"R_PPC64_GNU_VTENTRY", Const, 20, ""}, {"R_PPC64_GNU_VTINHERIT", Const, 20, ""}, {"R_PPC64_GOT16", Const, 5, ""}, {"R_PPC64_GOT16_DS", Const, 5, ""}, {"R_PPC64_GOT16_HA", Const, 5, ""}, {"R_PPC64_GOT16_HI", Const, 5, ""}, {"R_PPC64_GOT16_LO", Const, 5, ""}, {"R_PPC64_GOT16_LO_DS", Const, 5, ""}, {"R_PPC64_GOT_DTPREL16_DS", Const, 5, ""}, {"R_PPC64_GOT_DTPREL16_HA", Const, 5, ""}, {"R_PPC64_GOT_DTPREL16_HI", Const, 5, ""}, {"R_PPC64_GOT_DTPREL16_LO_DS", Const, 5, ""}, {"R_PPC64_GOT_DTPREL_PCREL34", Const, 20, ""}, {"R_PPC64_GOT_PCREL34", Const, 20, ""}, {"R_PPC64_GOT_TLSGD16", Const, 5, ""}, {"R_PPC64_GOT_TLSGD16_HA", Const, 5, ""}, {"R_PPC64_GOT_TLSGD16_HI", Const, 5, ""}, {"R_PPC64_GOT_TLSGD16_LO", Const, 5, ""}, {"R_PPC64_GOT_TLSGD_PCREL34", Const, 20, ""}, {"R_PPC64_GOT_TLSLD16", Const, 5, ""}, {"R_PPC64_GOT_TLSLD16_HA", Const, 5, ""}, {"R_PPC64_GOT_TLSLD16_HI", Const, 5, ""}, {"R_PPC64_GOT_TLSLD16_LO", Const, 5, ""}, {"R_PPC64_GOT_TLSLD_PCREL34", Const, 20, ""}, {"R_PPC64_GOT_TPREL16_DS", Const, 5, ""}, {"R_PPC64_GOT_TPREL16_HA", Const, 5, ""}, {"R_PPC64_GOT_TPREL16_HI", Const, 5, ""}, {"R_PPC64_GOT_TPREL16_LO_DS", Const, 5, ""}, {"R_PPC64_GOT_TPREL_PCREL34", Const, 20, ""}, {"R_PPC64_IRELATIVE", Const, 10, ""}, {"R_PPC64_JMP_IREL", Const, 10, ""}, {"R_PPC64_JMP_SLOT", Const, 5, ""}, {"R_PPC64_NONE", Const, 5, ""}, {"R_PPC64_PCREL28", Const, 20, ""}, {"R_PPC64_PCREL34", Const, 20, ""}, {"R_PPC64_PCREL_OPT", Const, 20, ""}, {"R_PPC64_PLT16_HA", Const, 20, ""}, {"R_PPC64_PLT16_HI", Const, 20, ""}, {"R_PPC64_PLT16_LO", Const, 20, ""}, {"R_PPC64_PLT16_LO_DS", Const, 10, ""}, {"R_PPC64_PLT32", Const, 20, ""}, {"R_PPC64_PLT64", Const, 20, ""}, {"R_PPC64_PLTCALL", Const, 20, ""}, {"R_PPC64_PLTCALL_NOTOC", Const, 20, ""}, {"R_PPC64_PLTGOT16", Const, 10, ""}, {"R_PPC64_PLTGOT16_DS", Const, 10, ""}, {"R_PPC64_PLTGOT16_HA", Const, 10, ""}, {"R_PPC64_PLTGOT16_HI", Const, 10, ""}, {"R_PPC64_PLTGOT16_LO", Const, 10, ""}, {"R_PPC64_PLTGOT_LO_DS", Const, 10, ""}, {"R_PPC64_PLTREL32", Const, 20, ""}, {"R_PPC64_PLTREL64", Const, 20, ""}, {"R_PPC64_PLTSEQ", Const, 20, ""}, {"R_PPC64_PLTSEQ_NOTOC", Const, 20, ""}, {"R_PPC64_PLT_PCREL34", Const, 20, ""}, {"R_PPC64_PLT_PCREL34_NOTOC", Const, 20, ""}, {"R_PPC64_REL14", Const, 5, ""}, {"R_PPC64_REL14_BRNTAKEN", Const, 5, ""}, {"R_PPC64_REL14_BRTAKEN", Const, 5, ""}, {"R_PPC64_REL16", Const, 5, ""}, {"R_PPC64_REL16DX_HA", Const, 10, ""}, {"R_PPC64_REL16_HA", Const, 5, ""}, {"R_PPC64_REL16_HI", Const, 5, ""}, {"R_PPC64_REL16_HIGH", Const, 20, ""}, {"R_PPC64_REL16_HIGHA", Const, 20, ""}, {"R_PPC64_REL16_HIGHER", Const, 20, ""}, {"R_PPC64_REL16_HIGHER34", Const, 20, ""}, {"R_PPC64_REL16_HIGHERA", Const, 20, ""}, {"R_PPC64_REL16_HIGHERA34", Const, 20, ""}, {"R_PPC64_REL16_HIGHEST", Const, 20, ""}, {"R_PPC64_REL16_HIGHEST34", Const, 20, ""}, {"R_PPC64_REL16_HIGHESTA", Const, 20, ""}, {"R_PPC64_REL16_HIGHESTA34", Const, 20, ""}, {"R_PPC64_REL16_LO", Const, 5, ""}, {"R_PPC64_REL24", Const, 5, ""}, {"R_PPC64_REL24_NOTOC", Const, 10, ""}, {"R_PPC64_REL24_P9NOTOC", Const, 21, ""}, {"R_PPC64_REL30", Const, 20, ""}, {"R_PPC64_REL32", Const, 5, ""}, {"R_PPC64_REL64", Const, 5, ""}, {"R_PPC64_RELATIVE", Const, 18, ""}, {"R_PPC64_SECTOFF", Const, 20, ""}, {"R_PPC64_SECTOFF_DS", Const, 10, ""}, {"R_PPC64_SECTOFF_HA", Const, 20, ""}, {"R_PPC64_SECTOFF_HI", Const, 20, ""}, {"R_PPC64_SECTOFF_LO", Const, 20, ""}, {"R_PPC64_SECTOFF_LO_DS", Const, 10, ""}, {"R_PPC64_TLS", Const, 5, ""}, {"R_PPC64_TLSGD", Const, 5, ""}, {"R_PPC64_TLSLD", Const, 5, ""}, {"R_PPC64_TOC", Const, 5, ""}, {"R_PPC64_TOC16", Const, 5, ""}, {"R_PPC64_TOC16_DS", Const, 5, ""}, {"R_PPC64_TOC16_HA", Const, 5, ""}, {"R_PPC64_TOC16_HI", Const, 5, ""}, {"R_PPC64_TOC16_LO", Const, 5, ""}, {"R_PPC64_TOC16_LO_DS", Const, 5, ""}, {"R_PPC64_TOCSAVE", Const, 10, ""}, {"R_PPC64_TPREL16", Const, 5, ""}, {"R_PPC64_TPREL16_DS", Const, 5, ""}, {"R_PPC64_TPREL16_HA", Const, 5, ""}, {"R_PPC64_TPREL16_HI", Const, 5, ""}, {"R_PPC64_TPREL16_HIGH", Const, 10, ""}, {"R_PPC64_TPREL16_HIGHA", Const, 10, ""}, {"R_PPC64_TPREL16_HIGHER", Const, 5, ""}, {"R_PPC64_TPREL16_HIGHERA", Const, 5, ""}, {"R_PPC64_TPREL16_HIGHEST", Const, 5, ""}, {"R_PPC64_TPREL16_HIGHESTA", Const, 5, ""}, {"R_PPC64_TPREL16_LO", Const, 5, ""}, {"R_PPC64_TPREL16_LO_DS", Const, 5, ""}, {"R_PPC64_TPREL34", Const, 20, ""}, {"R_PPC64_TPREL64", Const, 5, ""}, {"R_PPC64_UADDR16", Const, 20, ""}, {"R_PPC64_UADDR32", Const, 20, ""}, {"R_PPC64_UADDR64", Const, 20, ""}, {"R_PPC_ADDR14", Const, 0, ""}, {"R_PPC_ADDR14_BRNTAKEN", Const, 0, ""}, {"R_PPC_ADDR14_BRTAKEN", Const, 0, ""}, {"R_PPC_ADDR16", Const, 0, ""}, {"R_PPC_ADDR16_HA", Const, 0, ""}, {"R_PPC_ADDR16_HI", Const, 0, ""}, {"R_PPC_ADDR16_LO", Const, 0, ""}, {"R_PPC_ADDR24", Const, 0, ""}, {"R_PPC_ADDR32", Const, 0, ""}, {"R_PPC_COPY", Const, 0, ""}, {"R_PPC_DTPMOD32", Const, 0, ""}, {"R_PPC_DTPREL16", Const, 0, ""}, {"R_PPC_DTPREL16_HA", Const, 0, ""}, {"R_PPC_DTPREL16_HI", Const, 0, ""}, {"R_PPC_DTPREL16_LO", Const, 0, ""}, {"R_PPC_DTPREL32", Const, 0, ""}, {"R_PPC_EMB_BIT_FLD", Const, 0, ""}, {"R_PPC_EMB_MRKREF", Const, 0, ""}, {"R_PPC_EMB_NADDR16", Const, 0, ""}, {"R_PPC_EMB_NADDR16_HA", Const, 0, ""}, {"R_PPC_EMB_NADDR16_HI", Const, 0, ""}, {"R_PPC_EMB_NADDR16_LO", Const, 0, ""}, {"R_PPC_EMB_NADDR32", Const, 0, ""}, {"R_PPC_EMB_RELSDA", Const, 0, ""}, {"R_PPC_EMB_RELSEC16", Const, 0, ""}, {"R_PPC_EMB_RELST_HA", Const, 0, ""}, {"R_PPC_EMB_RELST_HI", Const, 0, ""}, {"R_PPC_EMB_RELST_LO", Const, 0, ""}, {"R_PPC_EMB_SDA21", Const, 0, ""}, {"R_PPC_EMB_SDA2I16", Const, 0, ""}, {"R_PPC_EMB_SDA2REL", Const, 0, ""}, {"R_PPC_EMB_SDAI16", Const, 0, ""}, {"R_PPC_GLOB_DAT", Const, 0, ""}, {"R_PPC_GOT16", Const, 0, ""}, {"R_PPC_GOT16_HA", Const, 0, ""}, {"R_PPC_GOT16_HI", Const, 0, ""}, {"R_PPC_GOT16_LO", Const, 0, ""}, {"R_PPC_GOT_TLSGD16", Const, 0, ""}, {"R_PPC_GOT_TLSGD16_HA", Const, 0, ""}, {"R_PPC_GOT_TLSGD16_HI", Const, 0, ""}, {"R_PPC_GOT_TLSGD16_LO", Const, 0, ""}, {"R_PPC_GOT_TLSLD16", Const, 0, ""}, {"R_PPC_GOT_TLSLD16_HA", Const, 0, ""}, {"R_PPC_GOT_TLSLD16_HI", Const, 0, ""}, {"R_PPC_GOT_TLSLD16_LO", Const, 0, ""}, {"R_PPC_GOT_TPREL16", Const, 0, ""}, {"R_PPC_GOT_TPREL16_HA", Const, 0, ""}, {"R_PPC_GOT_TPREL16_HI", Const, 0, ""}, {"R_PPC_GOT_TPREL16_LO", Const, 0, ""}, {"R_PPC_JMP_SLOT", Const, 0, ""}, {"R_PPC_LOCAL24PC", Const, 0, ""}, {"R_PPC_NONE", Const, 0, ""}, {"R_PPC_PLT16_HA", Const, 0, ""}, {"R_PPC_PLT16_HI", Const, 0, ""}, {"R_PPC_PLT16_LO", Const, 0, ""}, {"R_PPC_PLT32", Const, 0, ""}, {"R_PPC_PLTREL24", Const, 0, ""}, {"R_PPC_PLTREL32", Const, 0, ""}, {"R_PPC_REL14", Const, 0, ""}, {"R_PPC_REL14_BRNTAKEN", Const, 0, ""}, {"R_PPC_REL14_BRTAKEN", Const, 0, ""}, {"R_PPC_REL24", Const, 0, ""}, {"R_PPC_REL32", Const, 0, ""}, {"R_PPC_RELATIVE", Const, 0, ""}, {"R_PPC_SDAREL16", Const, 0, ""}, {"R_PPC_SECTOFF", Const, 0, ""}, {"R_PPC_SECTOFF_HA", Const, 0, ""}, {"R_PPC_SECTOFF_HI", Const, 0, ""}, {"R_PPC_SECTOFF_LO", Const, 0, ""}, {"R_PPC_TLS", Const, 0, ""}, {"R_PPC_TPREL16", Const, 0, ""}, {"R_PPC_TPREL16_HA", Const, 0, ""}, {"R_PPC_TPREL16_HI", Const, 0, ""}, {"R_PPC_TPREL16_LO", Const, 0, ""}, {"R_PPC_TPREL32", Const, 0, ""}, {"R_PPC_UADDR16", Const, 0, ""}, {"R_PPC_UADDR32", Const, 0, ""}, {"R_RISCV", Type, 11, ""}, {"R_RISCV_32", Const, 11, ""}, {"R_RISCV_32_PCREL", Const, 12, ""}, {"R_RISCV_64", Const, 11, ""}, {"R_RISCV_ADD16", Const, 11, ""}, {"R_RISCV_ADD32", Const, 11, ""}, {"R_RISCV_ADD64", Const, 11, ""}, {"R_RISCV_ADD8", Const, 11, ""}, {"R_RISCV_ALIGN", Const, 11, ""}, {"R_RISCV_BRANCH", Const, 11, ""}, {"R_RISCV_CALL", Const, 11, ""}, {"R_RISCV_CALL_PLT", Const, 11, ""}, {"R_RISCV_COPY", Const, 11, ""}, {"R_RISCV_GNU_VTENTRY", Const, 11, ""}, {"R_RISCV_GNU_VTINHERIT", Const, 11, ""}, {"R_RISCV_GOT_HI20", Const, 11, ""}, {"R_RISCV_GPREL_I", Const, 11, ""}, {"R_RISCV_GPREL_S", Const, 11, ""}, {"R_RISCV_HI20", Const, 11, ""}, {"R_RISCV_JAL", Const, 11, ""}, {"R_RISCV_JUMP_SLOT", Const, 11, ""}, {"R_RISCV_LO12_I", Const, 11, ""}, {"R_RISCV_LO12_S", Const, 11, ""}, {"R_RISCV_NONE", Const, 11, ""}, {"R_RISCV_PCREL_HI20", Const, 11, ""}, {"R_RISCV_PCREL_LO12_I", Const, 11, ""}, {"R_RISCV_PCREL_LO12_S", Const, 11, ""}, {"R_RISCV_RELATIVE", Const, 11, ""}, {"R_RISCV_RELAX", Const, 11, ""}, {"R_RISCV_RVC_BRANCH", Const, 11, ""}, {"R_RISCV_RVC_JUMP", Const, 11, ""}, {"R_RISCV_RVC_LUI", Const, 11, ""}, {"R_RISCV_SET16", Const, 11, ""}, {"R_RISCV_SET32", Const, 11, ""}, {"R_RISCV_SET6", Const, 11, ""}, {"R_RISCV_SET8", Const, 11, ""}, {"R_RISCV_SUB16", Const, 11, ""}, {"R_RISCV_SUB32", Const, 11, ""}, {"R_RISCV_SUB6", Const, 11, ""}, {"R_RISCV_SUB64", Const, 11, ""}, {"R_RISCV_SUB8", Const, 11, ""}, {"R_RISCV_TLS_DTPMOD32", Const, 11, ""}, {"R_RISCV_TLS_DTPMOD64", Const, 11, ""}, {"R_RISCV_TLS_DTPREL32", Const, 11, ""}, {"R_RISCV_TLS_DTPREL64", Const, 11, ""}, {"R_RISCV_TLS_GD_HI20", Const, 11, ""}, {"R_RISCV_TLS_GOT_HI20", Const, 11, ""}, {"R_RISCV_TLS_TPREL32", Const, 11, ""}, {"R_RISCV_TLS_TPREL64", Const, 11, ""}, {"R_RISCV_TPREL_ADD", Const, 11, ""}, {"R_RISCV_TPREL_HI20", Const, 11, ""}, {"R_RISCV_TPREL_I", Const, 11, ""}, {"R_RISCV_TPREL_LO12_I", Const, 11, ""}, {"R_RISCV_TPREL_LO12_S", Const, 11, ""}, {"R_RISCV_TPREL_S", Const, 11, ""}, {"R_SPARC", Type, 0, ""}, {"R_SPARC_10", Const, 0, ""}, {"R_SPARC_11", Const, 0, ""}, {"R_SPARC_13", Const, 0, ""}, {"R_SPARC_16", Const, 0, ""}, {"R_SPARC_22", Const, 0, ""}, {"R_SPARC_32", Const, 0, ""}, {"R_SPARC_5", Const, 0, ""}, {"R_SPARC_6", Const, 0, ""}, {"R_SPARC_64", Const, 0, ""}, {"R_SPARC_7", Const, 0, ""}, {"R_SPARC_8", Const, 0, ""}, {"R_SPARC_COPY", Const, 0, ""}, {"R_SPARC_DISP16", Const, 0, ""}, {"R_SPARC_DISP32", Const, 0, ""}, {"R_SPARC_DISP64", Const, 0, ""}, {"R_SPARC_DISP8", Const, 0, ""}, {"R_SPARC_GLOB_DAT", Const, 0, ""}, {"R_SPARC_GLOB_JMP", Const, 0, ""}, {"R_SPARC_GOT10", Const, 0, ""}, {"R_SPARC_GOT13", Const, 0, ""}, {"R_SPARC_GOT22", Const, 0, ""}, {"R_SPARC_H44", Const, 0, ""}, {"R_SPARC_HH22", Const, 0, ""}, {"R_SPARC_HI22", Const, 0, ""}, {"R_SPARC_HIPLT22", Const, 0, ""}, {"R_SPARC_HIX22", Const, 0, ""}, {"R_SPARC_HM10", Const, 0, ""}, {"R_SPARC_JMP_SLOT", Const, 0, ""}, {"R_SPARC_L44", Const, 0, ""}, {"R_SPARC_LM22", Const, 0, ""}, {"R_SPARC_LO10", Const, 0, ""}, {"R_SPARC_LOPLT10", Const, 0, ""}, {"R_SPARC_LOX10", Const, 0, ""}, {"R_SPARC_M44", Const, 0, ""}, {"R_SPARC_NONE", Const, 0, ""}, {"R_SPARC_OLO10", Const, 0, ""}, {"R_SPARC_PC10", Const, 0, ""}, {"R_SPARC_PC22", Const, 0, ""}, {"R_SPARC_PCPLT10", Const, 0, ""}, {"R_SPARC_PCPLT22", Const, 0, ""}, {"R_SPARC_PCPLT32", Const, 0, ""}, {"R_SPARC_PC_HH22", Const, 0, ""}, {"R_SPARC_PC_HM10", Const, 0, ""}, {"R_SPARC_PC_LM22", Const, 0, ""}, {"R_SPARC_PLT32", Const, 0, ""}, {"R_SPARC_PLT64", Const, 0, ""}, {"R_SPARC_REGISTER", Const, 0, ""}, {"R_SPARC_RELATIVE", Const, 0, ""}, {"R_SPARC_UA16", Const, 0, ""}, {"R_SPARC_UA32", Const, 0, ""}, {"R_SPARC_UA64", Const, 0, ""}, {"R_SPARC_WDISP16", Const, 0, ""}, {"R_SPARC_WDISP19", Const, 0, ""}, {"R_SPARC_WDISP22", Const, 0, ""}, {"R_SPARC_WDISP30", Const, 0, ""}, {"R_SPARC_WPLT30", Const, 0, ""}, {"R_SYM32", Func, 0, "func(info uint32) uint32"}, {"R_SYM64", Func, 0, "func(info uint64) uint32"}, {"R_TYPE32", Func, 0, "func(info uint32) uint32"}, {"R_TYPE64", Func, 0, "func(info uint64) uint32"}, {"R_X86_64", Type, 0, ""}, {"R_X86_64_16", Const, 0, ""}, {"R_X86_64_32", Const, 0, ""}, {"R_X86_64_32S", Const, 0, ""}, {"R_X86_64_64", Const, 0, ""}, {"R_X86_64_8", Const, 0, ""}, {"R_X86_64_COPY", Const, 0, ""}, {"R_X86_64_DTPMOD64", Const, 0, ""}, {"R_X86_64_DTPOFF32", Const, 0, ""}, {"R_X86_64_DTPOFF64", Const, 0, ""}, {"R_X86_64_GLOB_DAT", Const, 0, ""}, {"R_X86_64_GOT32", Const, 0, ""}, {"R_X86_64_GOT64", Const, 10, ""}, {"R_X86_64_GOTOFF64", Const, 10, ""}, {"R_X86_64_GOTPC32", Const, 10, ""}, {"R_X86_64_GOTPC32_TLSDESC", Const, 10, ""}, {"R_X86_64_GOTPC64", Const, 10, ""}, {"R_X86_64_GOTPCREL", Const, 0, ""}, {"R_X86_64_GOTPCREL64", Const, 10, ""}, {"R_X86_64_GOTPCRELX", Const, 10, ""}, {"R_X86_64_GOTPLT64", Const, 10, ""}, {"R_X86_64_GOTTPOFF", Const, 0, ""}, {"R_X86_64_IRELATIVE", Const, 10, ""}, {"R_X86_64_JMP_SLOT", Const, 0, ""}, {"R_X86_64_NONE", Const, 0, ""}, {"R_X86_64_PC16", Const, 0, ""}, {"R_X86_64_PC32", Const, 0, ""}, {"R_X86_64_PC32_BND", Const, 10, ""}, {"R_X86_64_PC64", Const, 10, ""}, {"R_X86_64_PC8", Const, 0, ""}, {"R_X86_64_PLT32", Const, 0, ""}, {"R_X86_64_PLT32_BND", Const, 10, ""}, {"R_X86_64_PLTOFF64", Const, 10, ""}, {"R_X86_64_RELATIVE", Const, 0, ""}, {"R_X86_64_RELATIVE64", Const, 10, ""}, {"R_X86_64_REX_GOTPCRELX", Const, 10, ""}, {"R_X86_64_SIZE32", Const, 10, ""}, {"R_X86_64_SIZE64", Const, 10, ""}, {"R_X86_64_TLSDESC", Const, 10, ""}, {"R_X86_64_TLSDESC_CALL", Const, 10, ""}, {"R_X86_64_TLSGD", Const, 0, ""}, {"R_X86_64_TLSLD", Const, 0, ""}, {"R_X86_64_TPOFF32", Const, 0, ""}, {"R_X86_64_TPOFF64", Const, 0, ""}, {"Rel32", Type, 0, ""}, {"Rel32.Info", Field, 0, ""}, {"Rel32.Off", Field, 0, ""}, {"Rel64", Type, 0, ""}, {"Rel64.Info", Field, 0, ""}, {"Rel64.Off", Field, 0, ""}, {"Rela32", Type, 0, ""}, {"Rela32.Addend", Field, 0, ""}, {"Rela32.Info", Field, 0, ""}, {"Rela32.Off", Field, 0, ""}, {"Rela64", Type, 0, ""}, {"Rela64.Addend", Field, 0, ""}, {"Rela64.Info", Field, 0, ""}, {"Rela64.Off", Field, 0, ""}, {"SHF_ALLOC", Const, 0, ""}, {"SHF_COMPRESSED", Const, 6, ""}, {"SHF_EXECINSTR", Const, 0, ""}, {"SHF_GROUP", Const, 0, ""}, {"SHF_INFO_LINK", Const, 0, ""}, {"SHF_LINK_ORDER", Const, 0, ""}, {"SHF_MASKOS", Const, 0, ""}, {"SHF_MASKPROC", Const, 0, ""}, {"SHF_MERGE", Const, 0, ""}, {"SHF_OS_NONCONFORMING", Const, 0, ""}, {"SHF_STRINGS", Const, 0, ""}, {"SHF_TLS", Const, 0, ""}, {"SHF_WRITE", Const, 0, ""}, {"SHN_ABS", Const, 0, ""}, {"SHN_COMMON", Const, 0, ""}, {"SHN_HIOS", Const, 0, ""}, {"SHN_HIPROC", Const, 0, ""}, {"SHN_HIRESERVE", Const, 0, ""}, {"SHN_LOOS", Const, 0, ""}, {"SHN_LOPROC", Const, 0, ""}, {"SHN_LORESERVE", Const, 0, ""}, {"SHN_UNDEF", Const, 0, ""}, {"SHN_XINDEX", Const, 0, ""}, {"SHT_DYNAMIC", Const, 0, ""}, {"SHT_DYNSYM", Const, 0, ""}, {"SHT_FINI_ARRAY", Const, 0, ""}, {"SHT_GNU_ATTRIBUTES", Const, 0, ""}, {"SHT_GNU_HASH", Const, 0, ""}, {"SHT_GNU_LIBLIST", Const, 0, ""}, {"SHT_GNU_VERDEF", Const, 0, ""}, {"SHT_GNU_VERNEED", Const, 0, ""}, {"SHT_GNU_VERSYM", Const, 0, ""}, {"SHT_GROUP", Const, 0, ""}, {"SHT_HASH", Const, 0, ""}, {"SHT_HIOS", Const, 0, ""}, {"SHT_HIPROC", Const, 0, ""}, {"SHT_HIUSER", Const, 0, ""}, {"SHT_INIT_ARRAY", Const, 0, ""}, {"SHT_LOOS", Const, 0, ""}, {"SHT_LOPROC", Const, 0, ""}, {"SHT_LOUSER", Const, 0, ""}, {"SHT_MIPS_ABIFLAGS", Const, 17, ""}, {"SHT_NOBITS", Const, 0, ""}, {"SHT_NOTE", Const, 0, ""}, {"SHT_NULL", Const, 0, ""}, {"SHT_PREINIT_ARRAY", Const, 0, ""}, {"SHT_PROGBITS", Const, 0, ""}, {"SHT_REL", Const, 0, ""}, {"SHT_RELA", Const, 0, ""}, {"SHT_RISCV_ATTRIBUTES", Const, 25, ""}, {"SHT_SHLIB", Const, 0, ""}, {"SHT_STRTAB", Const, 0, ""}, {"SHT_SYMTAB", Const, 0, ""}, {"SHT_SYMTAB_SHNDX", Const, 0, ""}, {"STB_GLOBAL", Const, 0, ""}, {"STB_HIOS", Const, 0, ""}, {"STB_HIPROC", Const, 0, ""}, {"STB_LOCAL", Const, 0, ""}, {"STB_LOOS", Const, 0, ""}, {"STB_LOPROC", Const, 0, ""}, {"STB_WEAK", Const, 0, ""}, {"STT_COMMON", Const, 0, ""}, {"STT_FILE", Const, 0, ""}, {"STT_FUNC", Const, 0, ""}, {"STT_GNU_IFUNC", Const, 23, ""}, {"STT_HIOS", Const, 0, ""}, {"STT_HIPROC", Const, 0, ""}, {"STT_LOOS", Const, 0, ""}, {"STT_LOPROC", Const, 0, ""}, {"STT_NOTYPE", Const, 0, ""}, {"STT_OBJECT", Const, 0, ""}, {"STT_RELC", Const, 23, ""}, {"STT_SECTION", Const, 0, ""}, {"STT_SRELC", Const, 23, ""}, {"STT_TLS", Const, 0, ""}, {"STV_DEFAULT", Const, 0, ""}, {"STV_HIDDEN", Const, 0, ""}, {"STV_INTERNAL", Const, 0, ""}, {"STV_PROTECTED", Const, 0, ""}, {"ST_BIND", Func, 0, "func(info uint8) SymBind"}, {"ST_INFO", Func, 0, "func(bind SymBind, typ SymType) uint8"}, {"ST_TYPE", Func, 0, "func(info uint8) SymType"}, {"ST_VISIBILITY", Func, 0, "func(other uint8) SymVis"}, {"Section", Type, 0, ""}, {"Section.ReaderAt", Field, 0, ""}, {"Section.SectionHeader", Field, 0, ""}, {"Section32", Type, 0, ""}, {"Section32.Addr", Field, 0, ""}, {"Section32.Addralign", Field, 0, ""}, {"Section32.Entsize", Field, 0, ""}, {"Section32.Flags", Field, 0, ""}, {"Section32.Info", Field, 0, ""}, {"Section32.Link", Field, 0, ""}, {"Section32.Name", Field, 0, ""}, {"Section32.Off", Field, 0, ""}, {"Section32.Size", Field, 0, ""}, {"Section32.Type", Field, 0, ""}, {"Section64", Type, 0, ""}, {"Section64.Addr", Field, 0, ""}, {"Section64.Addralign", Field, 0, ""}, {"Section64.Entsize", Field, 0, ""}, {"Section64.Flags", Field, 0, ""}, {"Section64.Info", Field, 0, ""}, {"Section64.Link", Field, 0, ""}, {"Section64.Name", Field, 0, ""}, {"Section64.Off", Field, 0, ""}, {"Section64.Size", Field, 0, ""}, {"Section64.Type", Field, 0, ""}, {"SectionFlag", Type, 0, ""}, {"SectionHeader", Type, 0, ""}, {"SectionHeader.Addr", Field, 0, ""}, {"SectionHeader.Addralign", Field, 0, ""}, {"SectionHeader.Entsize", Field, 0, ""}, {"SectionHeader.FileSize", Field, 6, ""}, {"SectionHeader.Flags", Field, 0, ""}, {"SectionHeader.Info", Field, 0, ""}, {"SectionHeader.Link", Field, 0, ""}, {"SectionHeader.Name", Field, 0, ""}, {"SectionHeader.Offset", Field, 0, ""}, {"SectionHeader.Size", Field, 0, ""}, {"SectionHeader.Type", Field, 0, ""}, {"SectionIndex", Type, 0, ""}, {"SectionType", Type, 0, ""}, {"Sym32", Type, 0, ""}, {"Sym32.Info", Field, 0, ""}, {"Sym32.Name", Field, 0, ""}, {"Sym32.Other", Field, 0, ""}, {"Sym32.Shndx", Field, 0, ""}, {"Sym32.Size", Field, 0, ""}, {"Sym32.Value", Field, 0, ""}, {"Sym32Size", Const, 0, ""}, {"Sym64", Type, 0, ""}, {"Sym64.Info", Field, 0, ""}, {"Sym64.Name", Field, 0, ""}, {"Sym64.Other", Field, 0, ""}, {"Sym64.Shndx", Field, 0, ""}, {"Sym64.Size", Field, 0, ""}, {"Sym64.Value", Field, 0, ""}, {"Sym64Size", Const, 0, ""}, {"SymBind", Type, 0, ""}, {"SymType", Type, 0, ""}, {"SymVis", Type, 0, ""}, {"Symbol", Type, 0, ""}, {"Symbol.HasVersion", Field, 24, ""}, {"Symbol.Info", Field, 0, ""}, {"Symbol.Library", Field, 13, ""}, {"Symbol.Name", Field, 0, ""}, {"Symbol.Other", Field, 0, ""}, {"Symbol.Section", Field, 0, ""}, {"Symbol.Size", Field, 0, ""}, {"Symbol.Value", Field, 0, ""}, {"Symbol.Version", Field, 13, ""}, {"Symbol.VersionIndex", Field, 24, ""}, {"Type", Type, 0, ""}, {"VER_FLG_BASE", Const, 24, ""}, {"VER_FLG_INFO", Const, 24, ""}, {"VER_FLG_WEAK", Const, 24, ""}, {"Version", Type, 0, ""}, {"VersionIndex", Type, 24, ""}, }, "debug/gosym": { {"(*DecodingError).Error", Method, 0, ""}, {"(*LineTable).LineToPC", Method, 0, ""}, {"(*LineTable).PCToLine", Method, 0, ""}, {"(*Sym).BaseName", Method, 0, ""}, {"(*Sym).PackageName", Method, 0, ""}, {"(*Sym).ReceiverName", Method, 0, ""}, {"(*Sym).Static", Method, 0, ""}, {"(*Table).LineToPC", Method, 0, ""}, {"(*Table).LookupFunc", Method, 0, ""}, {"(*Table).LookupSym", Method, 0, ""}, {"(*Table).PCToFunc", Method, 0, ""}, {"(*Table).PCToLine", Method, 0, ""}, {"(*Table).SymByAddr", Method, 0, ""}, {"(*UnknownLineError).Error", Method, 0, ""}, {"(Func).BaseName", Method, 0, ""}, {"(Func).PackageName", Method, 0, ""}, {"(Func).ReceiverName", Method, 0, ""}, {"(Func).Static", Method, 0, ""}, {"(UnknownFileError).Error", Method, 0, ""}, {"DecodingError", Type, 0, ""}, {"Func", Type, 0, ""}, {"Func.End", Field, 0, ""}, {"Func.Entry", Field, 0, ""}, {"Func.FrameSize", Field, 0, ""}, {"Func.LineTable", Field, 0, ""}, {"Func.Locals", Field, 0, ""}, {"Func.Obj", Field, 0, ""}, {"Func.Params", Field, 0, ""}, {"Func.Sym", Field, 0, ""}, {"LineTable", Type, 0, ""}, {"LineTable.Data", Field, 0, ""}, {"LineTable.Line", Field, 0, ""}, {"LineTable.PC", Field, 0, ""}, {"NewLineTable", Func, 0, "func(data []byte, text uint64) *LineTable"}, {"NewTable", Func, 0, "func(symtab []byte, pcln *LineTable) (*Table, error)"}, {"Obj", Type, 0, ""}, {"Obj.Funcs", Field, 0, ""}, {"Obj.Paths", Field, 0, ""}, {"Sym", Type, 0, ""}, {"Sym.Func", Field, 0, ""}, {"Sym.GoType", Field, 0, ""}, {"Sym.Name", Field, 0, ""}, {"Sym.Type", Field, 0, ""}, {"Sym.Value", Field, 0, ""}, {"Table", Type, 0, ""}, {"Table.Files", Field, 0, ""}, {"Table.Funcs", Field, 0, ""}, {"Table.Objs", Field, 0, ""}, {"Table.Syms", Field, 0, ""}, {"UnknownFileError", Type, 0, ""}, {"UnknownLineError", Type, 0, ""}, {"UnknownLineError.File", Field, 0, ""}, {"UnknownLineError.Line", Field, 0, ""}, }, "debug/macho": { {"(*FatFile).Close", Method, 3, ""}, {"(*File).Close", Method, 0, ""}, {"(*File).DWARF", Method, 0, ""}, {"(*File).ImportedLibraries", Method, 0, ""}, {"(*File).ImportedSymbols", Method, 0, ""}, {"(*File).Section", Method, 0, ""}, {"(*File).Segment", Method, 0, ""}, {"(*FormatError).Error", Method, 0, ""}, {"(*Section).Data", Method, 0, ""}, {"(*Section).Open", Method, 0, ""}, {"(*Segment).Data", Method, 0, ""}, {"(*Segment).Open", Method, 0, ""}, {"(Cpu).GoString", Method, 0, ""}, {"(Cpu).String", Method, 0, ""}, {"(Dylib).Raw", Method, 0, ""}, {"(Dysymtab).Raw", Method, 0, ""}, {"(FatArch).Close", Method, 3, ""}, {"(FatArch).DWARF", Method, 3, ""}, {"(FatArch).ImportedLibraries", Method, 3, ""}, {"(FatArch).ImportedSymbols", Method, 3, ""}, {"(FatArch).Section", Method, 3, ""}, {"(FatArch).Segment", Method, 3, ""}, {"(LoadBytes).Raw", Method, 0, ""}, {"(LoadCmd).GoString", Method, 0, ""}, {"(LoadCmd).String", Method, 0, ""}, {"(RelocTypeARM).GoString", Method, 10, ""}, {"(RelocTypeARM).String", Method, 10, ""}, {"(RelocTypeARM64).GoString", Method, 10, ""}, {"(RelocTypeARM64).String", Method, 10, ""}, {"(RelocTypeGeneric).GoString", Method, 10, ""}, {"(RelocTypeGeneric).String", Method, 10, ""}, {"(RelocTypeX86_64).GoString", Method, 10, ""}, {"(RelocTypeX86_64).String", Method, 10, ""}, {"(Rpath).Raw", Method, 10, ""}, {"(Section).ReadAt", Method, 0, ""}, {"(Segment).Raw", Method, 0, ""}, {"(Segment).ReadAt", Method, 0, ""}, {"(Symtab).Raw", Method, 0, ""}, {"(Type).GoString", Method, 10, ""}, {"(Type).String", Method, 10, ""}, {"ARM64_RELOC_ADDEND", Const, 10, ""}, {"ARM64_RELOC_BRANCH26", Const, 10, ""}, {"ARM64_RELOC_GOT_LOAD_PAGE21", Const, 10, ""}, {"ARM64_RELOC_GOT_LOAD_PAGEOFF12", Const, 10, ""}, {"ARM64_RELOC_PAGE21", Const, 10, ""}, {"ARM64_RELOC_PAGEOFF12", Const, 10, ""}, {"ARM64_RELOC_POINTER_TO_GOT", Const, 10, ""}, {"ARM64_RELOC_SUBTRACTOR", Const, 10, ""}, {"ARM64_RELOC_TLVP_LOAD_PAGE21", Const, 10, ""}, {"ARM64_RELOC_TLVP_LOAD_PAGEOFF12", Const, 10, ""}, {"ARM64_RELOC_UNSIGNED", Const, 10, ""}, {"ARM_RELOC_BR24", Const, 10, ""}, {"ARM_RELOC_HALF", Const, 10, ""}, {"ARM_RELOC_HALF_SECTDIFF", Const, 10, ""}, {"ARM_RELOC_LOCAL_SECTDIFF", Const, 10, ""}, {"ARM_RELOC_PAIR", Const, 10, ""}, {"ARM_RELOC_PB_LA_PTR", Const, 10, ""}, {"ARM_RELOC_SECTDIFF", Const, 10, ""}, {"ARM_RELOC_VANILLA", Const, 10, ""}, {"ARM_THUMB_32BIT_BRANCH", Const, 10, ""}, {"ARM_THUMB_RELOC_BR22", Const, 10, ""}, {"Cpu", Type, 0, ""}, {"Cpu386", Const, 0, ""}, {"CpuAmd64", Const, 0, ""}, {"CpuArm", Const, 3, ""}, {"CpuArm64", Const, 11, ""}, {"CpuPpc", Const, 3, ""}, {"CpuPpc64", Const, 3, ""}, {"Dylib", Type, 0, ""}, {"Dylib.CompatVersion", Field, 0, ""}, {"Dylib.CurrentVersion", Field, 0, ""}, {"Dylib.LoadBytes", Field, 0, ""}, {"Dylib.Name", Field, 0, ""}, {"Dylib.Time", Field, 0, ""}, {"DylibCmd", Type, 0, ""}, {"DylibCmd.Cmd", Field, 0, ""}, {"DylibCmd.CompatVersion", Field, 0, ""}, {"DylibCmd.CurrentVersion", Field, 0, ""}, {"DylibCmd.Len", Field, 0, ""}, {"DylibCmd.Name", Field, 0, ""}, {"DylibCmd.Time", Field, 0, ""}, {"Dysymtab", Type, 0, ""}, {"Dysymtab.DysymtabCmd", Field, 0, ""}, {"Dysymtab.IndirectSyms", Field, 0, ""}, {"Dysymtab.LoadBytes", Field, 0, ""}, {"DysymtabCmd", Type, 0, ""}, {"DysymtabCmd.Cmd", Field, 0, ""}, {"DysymtabCmd.Extrefsymoff", Field, 0, ""}, {"DysymtabCmd.Extreloff", Field, 0, ""}, {"DysymtabCmd.Iextdefsym", Field, 0, ""}, {"DysymtabCmd.Ilocalsym", Field, 0, ""}, {"DysymtabCmd.Indirectsymoff", Field, 0, ""}, {"DysymtabCmd.Iundefsym", Field, 0, ""}, {"DysymtabCmd.Len", Field, 0, ""}, {"DysymtabCmd.Locreloff", Field, 0, ""}, {"DysymtabCmd.Modtaboff", Field, 0, ""}, {"DysymtabCmd.Nextdefsym", Field, 0, ""}, {"DysymtabCmd.Nextrefsyms", Field, 0, ""}, {"DysymtabCmd.Nextrel", Field, 0, ""}, {"DysymtabCmd.Nindirectsyms", Field, 0, ""}, {"DysymtabCmd.Nlocalsym", Field, 0, ""}, {"DysymtabCmd.Nlocrel", Field, 0, ""}, {"DysymtabCmd.Nmodtab", Field, 0, ""}, {"DysymtabCmd.Ntoc", Field, 0, ""}, {"DysymtabCmd.Nundefsym", Field, 0, ""}, {"DysymtabCmd.Tocoffset", Field, 0, ""}, {"ErrNotFat", Var, 3, ""}, {"FatArch", Type, 3, ""}, {"FatArch.FatArchHeader", Field, 3, ""}, {"FatArch.File", Field, 3, ""}, {"FatArchHeader", Type, 3, ""}, {"FatArchHeader.Align", Field, 3, ""}, {"FatArchHeader.Cpu", Field, 3, ""}, {"FatArchHeader.Offset", Field, 3, ""}, {"FatArchHeader.Size", Field, 3, ""}, {"FatArchHeader.SubCpu", Field, 3, ""}, {"FatFile", Type, 3, ""}, {"FatFile.Arches", Field, 3, ""}, {"FatFile.Magic", Field, 3, ""}, {"File", Type, 0, ""}, {"File.ByteOrder", Field, 0, ""}, {"File.Dysymtab", Field, 0, ""}, {"File.FileHeader", Field, 0, ""}, {"File.Loads", Field, 0, ""}, {"File.Sections", Field, 0, ""}, {"File.Symtab", Field, 0, ""}, {"FileHeader", Type, 0, ""}, {"FileHeader.Cmdsz", Field, 0, ""}, {"FileHeader.Cpu", Field, 0, ""}, {"FileHeader.Flags", Field, 0, ""}, {"FileHeader.Magic", Field, 0, ""}, {"FileHeader.Ncmd", Field, 0, ""}, {"FileHeader.SubCpu", Field, 0, ""}, {"FileHeader.Type", Field, 0, ""}, {"FlagAllModsBound", Const, 10, ""}, {"FlagAllowStackExecution", Const, 10, ""}, {"FlagAppExtensionSafe", Const, 10, ""}, {"FlagBindAtLoad", Const, 10, ""}, {"FlagBindsToWeak", Const, 10, ""}, {"FlagCanonical", Const, 10, ""}, {"FlagDeadStrippableDylib", Const, 10, ""}, {"FlagDyldLink", Const, 10, ""}, {"FlagForceFlat", Const, 10, ""}, {"FlagHasTLVDescriptors", Const, 10, ""}, {"FlagIncrLink", Const, 10, ""}, {"FlagLazyInit", Const, 10, ""}, {"FlagNoFixPrebinding", Const, 10, ""}, {"FlagNoHeapExecution", Const, 10, ""}, {"FlagNoMultiDefs", Const, 10, ""}, {"FlagNoReexportedDylibs", Const, 10, ""}, {"FlagNoUndefs", Const, 10, ""}, {"FlagPIE", Const, 10, ""}, {"FlagPrebindable", Const, 10, ""}, {"FlagPrebound", Const, 10, ""}, {"FlagRootSafe", Const, 10, ""}, {"FlagSetuidSafe", Const, 10, ""}, {"FlagSplitSegs", Const, 10, ""}, {"FlagSubsectionsViaSymbols", Const, 10, ""}, {"FlagTwoLevel", Const, 10, ""}, {"FlagWeakDefines", Const, 10, ""}, {"FormatError", Type, 0, ""}, {"GENERIC_RELOC_LOCAL_SECTDIFF", Const, 10, ""}, {"GENERIC_RELOC_PAIR", Const, 10, ""}, {"GENERIC_RELOC_PB_LA_PTR", Const, 10, ""}, {"GENERIC_RELOC_SECTDIFF", Const, 10, ""}, {"GENERIC_RELOC_TLV", Const, 10, ""}, {"GENERIC_RELOC_VANILLA", Const, 10, ""}, {"Load", Type, 0, ""}, {"LoadBytes", Type, 0, ""}, {"LoadCmd", Type, 0, ""}, {"LoadCmdDylib", Const, 0, ""}, {"LoadCmdDylinker", Const, 0, ""}, {"LoadCmdDysymtab", Const, 0, ""}, {"LoadCmdRpath", Const, 10, ""}, {"LoadCmdSegment", Const, 0, ""}, {"LoadCmdSegment64", Const, 0, ""}, {"LoadCmdSymtab", Const, 0, ""}, {"LoadCmdThread", Const, 0, ""}, {"LoadCmdUnixThread", Const, 0, ""}, {"Magic32", Const, 0, ""}, {"Magic64", Const, 0, ""}, {"MagicFat", Const, 3, ""}, {"NewFatFile", Func, 3, "func(r io.ReaderAt) (*FatFile, error)"}, {"NewFile", Func, 0, "func(r io.ReaderAt) (*File, error)"}, {"Nlist32", Type, 0, ""}, {"Nlist32.Desc", Field, 0, ""}, {"Nlist32.Name", Field, 0, ""}, {"Nlist32.Sect", Field, 0, ""}, {"Nlist32.Type", Field, 0, ""}, {"Nlist32.Value", Field, 0, ""}, {"Nlist64", Type, 0, ""}, {"Nlist64.Desc", Field, 0, ""}, {"Nlist64.Name", Field, 0, ""}, {"Nlist64.Sect", Field, 0, ""}, {"Nlist64.Type", Field, 0, ""}, {"Nlist64.Value", Field, 0, ""}, {"Open", Func, 0, "func(name string) (*File, error)"}, {"OpenFat", Func, 3, "func(name string) (*FatFile, error)"}, {"Regs386", Type, 0, ""}, {"Regs386.AX", Field, 0, ""}, {"Regs386.BP", Field, 0, ""}, {"Regs386.BX", Field, 0, ""}, {"Regs386.CS", Field, 0, ""}, {"Regs386.CX", Field, 0, ""}, {"Regs386.DI", Field, 0, ""}, {"Regs386.DS", Field, 0, ""}, {"Regs386.DX", Field, 0, ""}, {"Regs386.ES", Field, 0, ""}, {"Regs386.FLAGS", Field, 0, ""}, {"Regs386.FS", Field, 0, ""}, {"Regs386.GS", Field, 0, ""}, {"Regs386.IP", Field, 0, ""}, {"Regs386.SI", Field, 0, ""}, {"Regs386.SP", Field, 0, ""}, {"Regs386.SS", Field, 0, ""}, {"RegsAMD64", Type, 0, ""}, {"RegsAMD64.AX", Field, 0, ""}, {"RegsAMD64.BP", Field, 0, ""}, {"RegsAMD64.BX", Field, 0, ""}, {"RegsAMD64.CS", Field, 0, ""}, {"RegsAMD64.CX", Field, 0, ""}, {"RegsAMD64.DI", Field, 0, ""}, {"RegsAMD64.DX", Field, 0, ""}, {"RegsAMD64.FLAGS", Field, 0, ""}, {"RegsAMD64.FS", Field, 0, ""}, {"RegsAMD64.GS", Field, 0, ""}, {"RegsAMD64.IP", Field, 0, ""}, {"RegsAMD64.R10", Field, 0, ""}, {"RegsAMD64.R11", Field, 0, ""}, {"RegsAMD64.R12", Field, 0, ""}, {"RegsAMD64.R13", Field, 0, ""}, {"RegsAMD64.R14", Field, 0, ""}, {"RegsAMD64.R15", Field, 0, ""}, {"RegsAMD64.R8", Field, 0, ""}, {"RegsAMD64.R9", Field, 0, ""}, {"RegsAMD64.SI", Field, 0, ""}, {"RegsAMD64.SP", Field, 0, ""}, {"Reloc", Type, 10, ""}, {"Reloc.Addr", Field, 10, ""}, {"Reloc.Extern", Field, 10, ""}, {"Reloc.Len", Field, 10, ""}, {"Reloc.Pcrel", Field, 10, ""}, {"Reloc.Scattered", Field, 10, ""}, {"Reloc.Type", Field, 10, ""}, {"Reloc.Value", Field, 10, ""}, {"RelocTypeARM", Type, 10, ""}, {"RelocTypeARM64", Type, 10, ""}, {"RelocTypeGeneric", Type, 10, ""}, {"RelocTypeX86_64", Type, 10, ""}, {"Rpath", Type, 10, ""}, {"Rpath.LoadBytes", Field, 10, ""}, {"Rpath.Path", Field, 10, ""}, {"RpathCmd", Type, 10, ""}, {"RpathCmd.Cmd", Field, 10, ""}, {"RpathCmd.Len", Field, 10, ""}, {"RpathCmd.Path", Field, 10, ""}, {"Section", Type, 0, ""}, {"Section.ReaderAt", Field, 0, ""}, {"Section.Relocs", Field, 10, ""}, {"Section.SectionHeader", Field, 0, ""}, {"Section32", Type, 0, ""}, {"Section32.Addr", Field, 0, ""}, {"Section32.Align", Field, 0, ""}, {"Section32.Flags", Field, 0, ""}, {"Section32.Name", Field, 0, ""}, {"Section32.Nreloc", Field, 0, ""}, {"Section32.Offset", Field, 0, ""}, {"Section32.Reloff", Field, 0, ""}, {"Section32.Reserve1", Field, 0, ""}, {"Section32.Reserve2", Field, 0, ""}, {"Section32.Seg", Field, 0, ""}, {"Section32.Size", Field, 0, ""}, {"Section64", Type, 0, ""}, {"Section64.Addr", Field, 0, ""}, {"Section64.Align", Field, 0, ""}, {"Section64.Flags", Field, 0, ""}, {"Section64.Name", Field, 0, ""}, {"Section64.Nreloc", Field, 0, ""}, {"Section64.Offset", Field, 0, ""}, {"Section64.Reloff", Field, 0, ""}, {"Section64.Reserve1", Field, 0, ""}, {"Section64.Reserve2", Field, 0, ""}, {"Section64.Reserve3", Field, 0, ""}, {"Section64.Seg", Field, 0, ""}, {"Section64.Size", Field, 0, ""}, {"SectionHeader", Type, 0, ""}, {"SectionHeader.Addr", Field, 0, ""}, {"SectionHeader.Align", Field, 0, ""}, {"SectionHeader.Flags", Field, 0, ""}, {"SectionHeader.Name", Field, 0, ""}, {"SectionHeader.Nreloc", Field, 0, ""}, {"SectionHeader.Offset", Field, 0, ""}, {"SectionHeader.Reloff", Field, 0, ""}, {"SectionHeader.Seg", Field, 0, ""}, {"SectionHeader.Size", Field, 0, ""}, {"Segment", Type, 0, ""}, {"Segment.LoadBytes", Field, 0, ""}, {"Segment.ReaderAt", Field, 0, ""}, {"Segment.SegmentHeader", Field, 0, ""}, {"Segment32", Type, 0, ""}, {"Segment32.Addr", Field, 0, ""}, {"Segment32.Cmd", Field, 0, ""}, {"Segment32.Filesz", Field, 0, ""}, {"Segment32.Flag", Field, 0, ""}, {"Segment32.Len", Field, 0, ""}, {"Segment32.Maxprot", Field, 0, ""}, {"Segment32.Memsz", Field, 0, ""}, {"Segment32.Name", Field, 0, ""}, {"Segment32.Nsect", Field, 0, ""}, {"Segment32.Offset", Field, 0, ""}, {"Segment32.Prot", Field, 0, ""}, {"Segment64", Type, 0, ""}, {"Segment64.Addr", Field, 0, ""}, {"Segment64.Cmd", Field, 0, ""}, {"Segment64.Filesz", Field, 0, ""}, {"Segment64.Flag", Field, 0, ""}, {"Segment64.Len", Field, 0, ""}, {"Segment64.Maxprot", Field, 0, ""}, {"Segment64.Memsz", Field, 0, ""}, {"Segment64.Name", Field, 0, ""}, {"Segment64.Nsect", Field, 0, ""}, {"Segment64.Offset", Field, 0, ""}, {"Segment64.Prot", Field, 0, ""}, {"SegmentHeader", Type, 0, ""}, {"SegmentHeader.Addr", Field, 0, ""}, {"SegmentHeader.Cmd", Field, 0, ""}, {"SegmentHeader.Filesz", Field, 0, ""}, {"SegmentHeader.Flag", Field, 0, ""}, {"SegmentHeader.Len", Field, 0, ""}, {"SegmentHeader.Maxprot", Field, 0, ""}, {"SegmentHeader.Memsz", Field, 0, ""}, {"SegmentHeader.Name", Field, 0, ""}, {"SegmentHeader.Nsect", Field, 0, ""}, {"SegmentHeader.Offset", Field, 0, ""}, {"SegmentHeader.Prot", Field, 0, ""}, {"Symbol", Type, 0, ""}, {"Symbol.Desc", Field, 0, ""}, {"Symbol.Name", Field, 0, ""}, {"Symbol.Sect", Field, 0, ""}, {"Symbol.Type", Field, 0, ""}, {"Symbol.Value", Field, 0, ""}, {"Symtab", Type, 0, ""}, {"Symtab.LoadBytes", Field, 0, ""}, {"Symtab.Syms", Field, 0, ""}, {"Symtab.SymtabCmd", Field, 0, ""}, {"SymtabCmd", Type, 0, ""}, {"SymtabCmd.Cmd", Field, 0, ""}, {"SymtabCmd.Len", Field, 0, ""}, {"SymtabCmd.Nsyms", Field, 0, ""}, {"SymtabCmd.Stroff", Field, 0, ""}, {"SymtabCmd.Strsize", Field, 0, ""}, {"SymtabCmd.Symoff", Field, 0, ""}, {"Thread", Type, 0, ""}, {"Thread.Cmd", Field, 0, ""}, {"Thread.Data", Field, 0, ""}, {"Thread.Len", Field, 0, ""}, {"Thread.Type", Field, 0, ""}, {"Type", Type, 0, ""}, {"TypeBundle", Const, 3, ""}, {"TypeDylib", Const, 3, ""}, {"TypeExec", Const, 0, ""}, {"TypeObj", Const, 0, ""}, {"X86_64_RELOC_BRANCH", Const, 10, ""}, {"X86_64_RELOC_GOT", Const, 10, ""}, {"X86_64_RELOC_GOT_LOAD", Const, 10, ""}, {"X86_64_RELOC_SIGNED", Const, 10, ""}, {"X86_64_RELOC_SIGNED_1", Const, 10, ""}, {"X86_64_RELOC_SIGNED_2", Const, 10, ""}, {"X86_64_RELOC_SIGNED_4", Const, 10, ""}, {"X86_64_RELOC_SUBTRACTOR", Const, 10, ""}, {"X86_64_RELOC_TLV", Const, 10, ""}, {"X86_64_RELOC_UNSIGNED", Const, 10, ""}, }, "debug/pe": { {"(*COFFSymbol).FullName", Method, 8, ""}, {"(*File).COFFSymbolReadSectionDefAux", Method, 19, ""}, {"(*File).Close", Method, 0, ""}, {"(*File).DWARF", Method, 0, ""}, {"(*File).ImportedLibraries", Method, 0, ""}, {"(*File).ImportedSymbols", Method, 0, ""}, {"(*File).Section", Method, 0, ""}, {"(*FormatError).Error", Method, 0, ""}, {"(*Section).Data", Method, 0, ""}, {"(*Section).Open", Method, 0, ""}, {"(Section).ReadAt", Method, 0, ""}, {"(StringTable).String", Method, 8, ""}, {"COFFSymbol", Type, 1, ""}, {"COFFSymbol.Name", Field, 1, ""}, {"COFFSymbol.NumberOfAuxSymbols", Field, 1, ""}, {"COFFSymbol.SectionNumber", Field, 1, ""}, {"COFFSymbol.StorageClass", Field, 1, ""}, {"COFFSymbol.Type", Field, 1, ""}, {"COFFSymbol.Value", Field, 1, ""}, {"COFFSymbolAuxFormat5", Type, 19, ""}, {"COFFSymbolAuxFormat5.Checksum", Field, 19, ""}, {"COFFSymbolAuxFormat5.NumLineNumbers", Field, 19, ""}, {"COFFSymbolAuxFormat5.NumRelocs", Field, 19, ""}, {"COFFSymbolAuxFormat5.SecNum", Field, 19, ""}, {"COFFSymbolAuxFormat5.Selection", Field, 19, ""}, {"COFFSymbolAuxFormat5.Size", Field, 19, ""}, {"COFFSymbolSize", Const, 1, ""}, {"DataDirectory", Type, 3, ""}, {"DataDirectory.Size", Field, 3, ""}, {"DataDirectory.VirtualAddress", Field, 3, ""}, {"File", Type, 0, ""}, {"File.COFFSymbols", Field, 8, ""}, {"File.FileHeader", Field, 0, ""}, {"File.OptionalHeader", Field, 3, ""}, {"File.Sections", Field, 0, ""}, {"File.StringTable", Field, 8, ""}, {"File.Symbols", Field, 1, ""}, {"FileHeader", Type, 0, ""}, {"FileHeader.Characteristics", Field, 0, ""}, {"FileHeader.Machine", Field, 0, ""}, {"FileHeader.NumberOfSections", Field, 0, ""}, {"FileHeader.NumberOfSymbols", Field, 0, ""}, {"FileHeader.PointerToSymbolTable", Field, 0, ""}, {"FileHeader.SizeOfOptionalHeader", Field, 0, ""}, {"FileHeader.TimeDateStamp", Field, 0, ""}, {"FormatError", Type, 0, ""}, {"IMAGE_COMDAT_SELECT_ANY", Const, 19, ""}, {"IMAGE_COMDAT_SELECT_ASSOCIATIVE", Const, 19, ""}, {"IMAGE_COMDAT_SELECT_EXACT_MATCH", Const, 19, ""}, {"IMAGE_COMDAT_SELECT_LARGEST", Const, 19, ""}, {"IMAGE_COMDAT_SELECT_NODUPLICATES", Const, 19, ""}, {"IMAGE_COMDAT_SELECT_SAME_SIZE", Const, 19, ""}, {"IMAGE_DIRECTORY_ENTRY_ARCHITECTURE", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_BASERELOC", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_BOUND_IMPORT", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_COM_DESCRIPTOR", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_DEBUG", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_DELAY_IMPORT", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_EXCEPTION", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_EXPORT", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_GLOBALPTR", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_IAT", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_IMPORT", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_RESOURCE", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_SECURITY", Const, 11, ""}, {"IMAGE_DIRECTORY_ENTRY_TLS", Const, 11, ""}, {"IMAGE_DLLCHARACTERISTICS_APPCONTAINER", Const, 15, ""}, {"IMAGE_DLLCHARACTERISTICS_DYNAMIC_BASE", Const, 15, ""}, {"IMAGE_DLLCHARACTERISTICS_FORCE_INTEGRITY", Const, 15, ""}, {"IMAGE_DLLCHARACTERISTICS_GUARD_CF", Const, 15, ""}, {"IMAGE_DLLCHARACTERISTICS_HIGH_ENTROPY_VA", Const, 15, ""}, {"IMAGE_DLLCHARACTERISTICS_NO_BIND", Const, 15, ""}, {"IMAGE_DLLCHARACTERISTICS_NO_ISOLATION", Const, 15, ""}, {"IMAGE_DLLCHARACTERISTICS_NO_SEH", Const, 15, ""}, {"IMAGE_DLLCHARACTERISTICS_NX_COMPAT", Const, 15, ""}, {"IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE", Const, 15, ""}, {"IMAGE_DLLCHARACTERISTICS_WDM_DRIVER", Const, 15, ""}, {"IMAGE_FILE_32BIT_MACHINE", Const, 15, ""}, {"IMAGE_FILE_AGGRESIVE_WS_TRIM", Const, 15, ""}, {"IMAGE_FILE_BYTES_REVERSED_HI", Const, 15, ""}, {"IMAGE_FILE_BYTES_REVERSED_LO", Const, 15, ""}, {"IMAGE_FILE_DEBUG_STRIPPED", Const, 15, ""}, {"IMAGE_FILE_DLL", Const, 15, ""}, {"IMAGE_FILE_EXECUTABLE_IMAGE", Const, 15, ""}, {"IMAGE_FILE_LARGE_ADDRESS_AWARE", Const, 15, ""}, {"IMAGE_FILE_LINE_NUMS_STRIPPED", Const, 15, ""}, {"IMAGE_FILE_LOCAL_SYMS_STRIPPED", Const, 15, ""}, {"IMAGE_FILE_MACHINE_AM33", Const, 0, ""}, {"IMAGE_FILE_MACHINE_AMD64", Const, 0, ""}, {"IMAGE_FILE_MACHINE_ARM", Const, 0, ""}, {"IMAGE_FILE_MACHINE_ARM64", Const, 11, ""}, {"IMAGE_FILE_MACHINE_ARMNT", Const, 12, ""}, {"IMAGE_FILE_MACHINE_EBC", Const, 0, ""}, {"IMAGE_FILE_MACHINE_I386", Const, 0, ""}, {"IMAGE_FILE_MACHINE_IA64", Const, 0, ""}, {"IMAGE_FILE_MACHINE_LOONGARCH32", Const, 19, ""}, {"IMAGE_FILE_MACHINE_LOONGARCH64", Const, 19, ""}, {"IMAGE_FILE_MACHINE_M32R", Const, 0, ""}, {"IMAGE_FILE_MACHINE_MIPS16", Const, 0, ""}, {"IMAGE_FILE_MACHINE_MIPSFPU", Const, 0, ""}, {"IMAGE_FILE_MACHINE_MIPSFPU16", Const, 0, ""}, {"IMAGE_FILE_MACHINE_POWERPC", Const, 0, ""}, {"IMAGE_FILE_MACHINE_POWERPCFP", Const, 0, ""}, {"IMAGE_FILE_MACHINE_R4000", Const, 0, ""}, {"IMAGE_FILE_MACHINE_RISCV128", Const, 20, ""}, {"IMAGE_FILE_MACHINE_RISCV32", Const, 20, ""}, {"IMAGE_FILE_MACHINE_RISCV64", Const, 20, ""}, {"IMAGE_FILE_MACHINE_SH3", Const, 0, ""}, {"IMAGE_FILE_MACHINE_SH3DSP", Const, 0, ""}, {"IMAGE_FILE_MACHINE_SH4", Const, 0, ""}, {"IMAGE_FILE_MACHINE_SH5", Const, 0, ""}, {"IMAGE_FILE_MACHINE_THUMB", Const, 0, ""}, {"IMAGE_FILE_MACHINE_UNKNOWN", Const, 0, ""}, {"IMAGE_FILE_MACHINE_WCEMIPSV2", Const, 0, ""}, {"IMAGE_FILE_NET_RUN_FROM_SWAP", Const, 15, ""}, {"IMAGE_FILE_RELOCS_STRIPPED", Const, 15, ""}, {"IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP", Const, 15, ""}, {"IMAGE_FILE_SYSTEM", Const, 15, ""}, {"IMAGE_FILE_UP_SYSTEM_ONLY", Const, 15, ""}, {"IMAGE_SCN_CNT_CODE", Const, 19, ""}, {"IMAGE_SCN_CNT_INITIALIZED_DATA", Const, 19, ""}, {"IMAGE_SCN_CNT_UNINITIALIZED_DATA", Const, 19, ""}, {"IMAGE_SCN_LNK_COMDAT", Const, 19, ""}, {"IMAGE_SCN_MEM_DISCARDABLE", Const, 19, ""}, {"IMAGE_SCN_MEM_EXECUTE", Const, 19, ""}, {"IMAGE_SCN_MEM_READ", Const, 19, ""}, {"IMAGE_SCN_MEM_WRITE", Const, 19, ""}, {"IMAGE_SUBSYSTEM_EFI_APPLICATION", Const, 15, ""}, {"IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER", Const, 15, ""}, {"IMAGE_SUBSYSTEM_EFI_ROM", Const, 15, ""}, {"IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER", Const, 15, ""}, {"IMAGE_SUBSYSTEM_NATIVE", Const, 15, ""}, {"IMAGE_SUBSYSTEM_NATIVE_WINDOWS", Const, 15, ""}, {"IMAGE_SUBSYSTEM_OS2_CUI", Const, 15, ""}, {"IMAGE_SUBSYSTEM_POSIX_CUI", Const, 15, ""}, {"IMAGE_SUBSYSTEM_UNKNOWN", Const, 15, ""}, {"IMAGE_SUBSYSTEM_WINDOWS_BOOT_APPLICATION", Const, 15, ""}, {"IMAGE_SUBSYSTEM_WINDOWS_CE_GUI", Const, 15, ""}, {"IMAGE_SUBSYSTEM_WINDOWS_CUI", Const, 15, ""}, {"IMAGE_SUBSYSTEM_WINDOWS_GUI", Const, 15, ""}, {"IMAGE_SUBSYSTEM_XBOX", Const, 15, ""}, {"ImportDirectory", Type, 0, ""}, {"ImportDirectory.FirstThunk", Field, 0, ""}, {"ImportDirectory.ForwarderChain", Field, 0, ""}, {"ImportDirectory.Name", Field, 0, ""}, {"ImportDirectory.OriginalFirstThunk", Field, 0, ""}, {"ImportDirectory.TimeDateStamp", Field, 0, ""}, {"NewFile", Func, 0, "func(r io.ReaderAt) (*File, error)"}, {"Open", Func, 0, "func(name string) (*File, error)"}, {"OptionalHeader32", Type, 3, ""}, {"OptionalHeader32.AddressOfEntryPoint", Field, 3, ""}, {"OptionalHeader32.BaseOfCode", Field, 3, ""}, {"OptionalHeader32.BaseOfData", Field, 3, ""}, {"OptionalHeader32.CheckSum", Field, 3, ""}, {"OptionalHeader32.DataDirectory", Field, 3, ""}, {"OptionalHeader32.DllCharacteristics", Field, 3, ""}, {"OptionalHeader32.FileAlignment", Field, 3, ""}, {"OptionalHeader32.ImageBase", Field, 3, ""}, {"OptionalHeader32.LoaderFlags", Field, 3, ""}, {"OptionalHeader32.Magic", Field, 3, ""}, {"OptionalHeader32.MajorImageVersion", Field, 3, ""}, {"OptionalHeader32.MajorLinkerVersion", Field, 3, ""}, {"OptionalHeader32.MajorOperatingSystemVersion", Field, 3, ""}, {"OptionalHeader32.MajorSubsystemVersion", Field, 3, ""}, {"OptionalHeader32.MinorImageVersion", Field, 3, ""}, {"OptionalHeader32.MinorLinkerVersion", Field, 3, ""}, {"OptionalHeader32.MinorOperatingSystemVersion", Field, 3, ""}, {"OptionalHeader32.MinorSubsystemVersion", Field, 3, ""}, {"OptionalHeader32.NumberOfRvaAndSizes", Field, 3, ""}, {"OptionalHeader32.SectionAlignment", Field, 3, ""}, {"OptionalHeader32.SizeOfCode", Field, 3, ""}, {"OptionalHeader32.SizeOfHeaders", Field, 3, ""}, {"OptionalHeader32.SizeOfHeapCommit", Field, 3, ""}, {"OptionalHeader32.SizeOfHeapReserve", Field, 3, ""}, {"OptionalHeader32.SizeOfImage", Field, 3, ""}, {"OptionalHeader32.SizeOfInitializedData", Field, 3, ""}, {"OptionalHeader32.SizeOfStackCommit", Field, 3, ""}, {"OptionalHeader32.SizeOfStackReserve", Field, 3, ""}, {"OptionalHeader32.SizeOfUninitializedData", Field, 3, ""}, {"OptionalHeader32.Subsystem", Field, 3, ""}, {"OptionalHeader32.Win32VersionValue", Field, 3, ""}, {"OptionalHeader64", Type, 3, ""}, {"OptionalHeader64.AddressOfEntryPoint", Field, 3, ""}, {"OptionalHeader64.BaseOfCode", Field, 3, ""}, {"OptionalHeader64.CheckSum", Field, 3, ""}, {"OptionalHeader64.DataDirectory", Field, 3, ""}, {"OptionalHeader64.DllCharacteristics", Field, 3, ""}, {"OptionalHeader64.FileAlignment", Field, 3, ""}, {"OptionalHeader64.ImageBase", Field, 3, ""}, {"OptionalHeader64.LoaderFlags", Field, 3, ""}, {"OptionalHeader64.Magic", Field, 3, ""}, {"OptionalHeader64.MajorImageVersion", Field, 3, ""}, {"OptionalHeader64.MajorLinkerVersion", Field, 3, ""}, {"OptionalHeader64.MajorOperatingSystemVersion", Field, 3, ""}, {"OptionalHeader64.MajorSubsystemVersion", Field, 3, ""}, {"OptionalHeader64.MinorImageVersion", Field, 3, ""}, {"OptionalHeader64.MinorLinkerVersion", Field, 3, ""}, {"OptionalHeader64.MinorOperatingSystemVersion", Field, 3, ""}, {"OptionalHeader64.MinorSubsystemVersion", Field, 3, ""}, {"OptionalHeader64.NumberOfRvaAndSizes", Field, 3, ""}, {"OptionalHeader64.SectionAlignment", Field, 3, ""}, {"OptionalHeader64.SizeOfCode", Field, 3, ""}, {"OptionalHeader64.SizeOfHeaders", Field, 3, ""}, {"OptionalHeader64.SizeOfHeapCommit", Field, 3, ""}, {"OptionalHeader64.SizeOfHeapReserve", Field, 3, ""}, {"OptionalHeader64.SizeOfImage", Field, 3, ""}, {"OptionalHeader64.SizeOfInitializedData", Field, 3, ""}, {"OptionalHeader64.SizeOfStackCommit", Field, 3, ""}, {"OptionalHeader64.SizeOfStackReserve", Field, 3, ""}, {"OptionalHeader64.SizeOfUninitializedData", Field, 3, ""}, {"OptionalHeader64.Subsystem", Field, 3, ""}, {"OptionalHeader64.Win32VersionValue", Field, 3, ""}, {"Reloc", Type, 8, ""}, {"Reloc.SymbolTableIndex", Field, 8, ""}, {"Reloc.Type", Field, 8, ""}, {"Reloc.VirtualAddress", Field, 8, ""}, {"Section", Type, 0, ""}, {"Section.ReaderAt", Field, 0, ""}, {"Section.Relocs", Field, 8, ""}, {"Section.SectionHeader", Field, 0, ""}, {"SectionHeader", Type, 0, ""}, {"SectionHeader.Characteristics", Field, 0, ""}, {"SectionHeader.Name", Field, 0, ""}, {"SectionHeader.NumberOfLineNumbers", Field, 0, ""}, {"SectionHeader.NumberOfRelocations", Field, 0, ""}, {"SectionHeader.Offset", Field, 0, ""}, {"SectionHeader.PointerToLineNumbers", Field, 0, ""}, {"SectionHeader.PointerToRelocations", Field, 0, ""}, {"SectionHeader.Size", Field, 0, ""}, {"SectionHeader.VirtualAddress", Field, 0, ""}, {"SectionHeader.VirtualSize", Field, 0, ""}, {"SectionHeader32", Type, 0, ""}, {"SectionHeader32.Characteristics", Field, 0, ""}, {"SectionHeader32.Name", Field, 0, ""}, {"SectionHeader32.NumberOfLineNumbers", Field, 0, ""}, {"SectionHeader32.NumberOfRelocations", Field, 0, ""}, {"SectionHeader32.PointerToLineNumbers", Field, 0, ""}, {"SectionHeader32.PointerToRawData", Field, 0, ""}, {"SectionHeader32.PointerToRelocations", Field, 0, ""}, {"SectionHeader32.SizeOfRawData", Field, 0, ""}, {"SectionHeader32.VirtualAddress", Field, 0, ""}, {"SectionHeader32.VirtualSize", Field, 0, ""}, {"StringTable", Type, 8, ""}, {"Symbol", Type, 1, ""}, {"Symbol.Name", Field, 1, ""}, {"Symbol.SectionNumber", Field, 1, ""}, {"Symbol.StorageClass", Field, 1, ""}, {"Symbol.Type", Field, 1, ""}, {"Symbol.Value", Field, 1, ""}, }, "debug/plan9obj": { {"(*File).Close", Method, 3, ""}, {"(*File).Section", Method, 3, ""}, {"(*File).Symbols", Method, 3, ""}, {"(*Section).Data", Method, 3, ""}, {"(*Section).Open", Method, 3, ""}, {"(Section).ReadAt", Method, 3, ""}, {"ErrNoSymbols", Var, 18, ""}, {"File", Type, 3, ""}, {"File.FileHeader", Field, 3, ""}, {"File.Sections", Field, 3, ""}, {"FileHeader", Type, 3, ""}, {"FileHeader.Bss", Field, 3, ""}, {"FileHeader.Entry", Field, 3, ""}, {"FileHeader.HdrSize", Field, 4, ""}, {"FileHeader.LoadAddress", Field, 4, ""}, {"FileHeader.Magic", Field, 3, ""}, {"FileHeader.PtrSize", Field, 3, ""}, {"Magic386", Const, 3, ""}, {"Magic64", Const, 3, ""}, {"MagicAMD64", Const, 3, ""}, {"MagicARM", Const, 3, ""}, {"NewFile", Func, 3, "func(r io.ReaderAt) (*File, error)"}, {"Open", Func, 3, "func(name string) (*File, error)"}, {"Section", Type, 3, ""}, {"Section.ReaderAt", Field, 3, ""}, {"Section.SectionHeader", Field, 3, ""}, {"SectionHeader", Type, 3, ""}, {"SectionHeader.Name", Field, 3, ""}, {"SectionHeader.Offset", Field, 3, ""}, {"SectionHeader.Size", Field, 3, ""}, {"Sym", Type, 3, ""}, {"Sym.Name", Field, 3, ""}, {"Sym.Type", Field, 3, ""}, {"Sym.Value", Field, 3, ""}, }, "embed": { {"(FS).Open", Method, 16, ""}, {"(FS).ReadDir", Method, 16, ""}, {"(FS).ReadFile", Method, 16, ""}, {"FS", Type, 16, ""}, }, "encoding": { {"BinaryAppender", Type, 24, ""}, {"BinaryMarshaler", Type, 2, ""}, {"BinaryUnmarshaler", Type, 2, ""}, {"TextAppender", Type, 24, ""}, {"TextMarshaler", Type, 2, ""}, {"TextUnmarshaler", Type, 2, ""}, }, "encoding/ascii85": { {"(CorruptInputError).Error", Method, 0, ""}, {"CorruptInputError", Type, 0, ""}, {"Decode", Func, 0, "func(dst []byte, src []byte, flush bool) (ndst int, nsrc int, err error)"}, {"Encode", Func, 0, "func(dst []byte, src []byte) int"}, {"MaxEncodedLen", Func, 0, "func(n int) int"}, {"NewDecoder", Func, 0, "func(r io.Reader) io.Reader"}, {"NewEncoder", Func, 0, "func(w io.Writer) io.WriteCloser"}, }, "encoding/asn1": { {"(BitString).At", Method, 0, ""}, {"(BitString).RightAlign", Method, 0, ""}, {"(ObjectIdentifier).Equal", Method, 0, ""}, {"(ObjectIdentifier).String", Method, 3, ""}, {"(StructuralError).Error", Method, 0, ""}, {"(SyntaxError).Error", Method, 0, ""}, {"BitString", Type, 0, ""}, {"BitString.BitLength", Field, 0, ""}, {"BitString.Bytes", Field, 0, ""}, {"ClassApplication", Const, 6, ""}, {"ClassContextSpecific", Const, 6, ""}, {"ClassPrivate", Const, 6, ""}, {"ClassUniversal", Const, 6, ""}, {"Enumerated", Type, 0, ""}, {"Flag", Type, 0, ""}, {"Marshal", Func, 0, "func(val any) ([]byte, error)"}, {"MarshalWithParams", Func, 10, "func(val any, params string) ([]byte, error)"}, {"NullBytes", Var, 9, ""}, {"NullRawValue", Var, 9, ""}, {"ObjectIdentifier", Type, 0, ""}, {"RawContent", Type, 0, ""}, {"RawValue", Type, 0, ""}, {"RawValue.Bytes", Field, 0, ""}, {"RawValue.Class", Field, 0, ""}, {"RawValue.FullBytes", Field, 0, ""}, {"RawValue.IsCompound", Field, 0, ""}, {"RawValue.Tag", Field, 0, ""}, {"StructuralError", Type, 0, ""}, {"StructuralError.Msg", Field, 0, ""}, {"SyntaxError", Type, 0, ""}, {"SyntaxError.Msg", Field, 0, ""}, {"TagBMPString", Const, 14, ""}, {"TagBitString", Const, 6, ""}, {"TagBoolean", Const, 6, ""}, {"TagEnum", Const, 6, ""}, {"TagGeneralString", Const, 6, ""}, {"TagGeneralizedTime", Const, 6, ""}, {"TagIA5String", Const, 6, ""}, {"TagInteger", Const, 6, ""}, {"TagNull", Const, 9, ""}, {"TagNumericString", Const, 10, ""}, {"TagOID", Const, 6, ""}, {"TagOctetString", Const, 6, ""}, {"TagPrintableString", Const, 6, ""}, {"TagSequence", Const, 6, ""}, {"TagSet", Const, 6, ""}, {"TagT61String", Const, 6, ""}, {"TagUTCTime", Const, 6, ""}, {"TagUTF8String", Const, 6, ""}, {"Unmarshal", Func, 0, "func(b []byte, val any) (rest []byte, err error)"}, {"UnmarshalWithParams", Func, 0, "func(b []byte, val any, params string) (rest []byte, err error)"}, }, "encoding/base32": { {"(*Encoding).AppendDecode", Method, 22, ""}, {"(*Encoding).AppendEncode", Method, 22, ""}, {"(*Encoding).Decode", Method, 0, ""}, {"(*Encoding).DecodeString", Method, 0, ""}, {"(*Encoding).DecodedLen", Method, 0, ""}, {"(*Encoding).Encode", Method, 0, ""}, {"(*Encoding).EncodeToString", Method, 0, ""}, {"(*Encoding).EncodedLen", Method, 0, ""}, {"(CorruptInputError).Error", Method, 0, ""}, {"(Encoding).WithPadding", Method, 9, ""}, {"CorruptInputError", Type, 0, ""}, {"Encoding", Type, 0, ""}, {"HexEncoding", Var, 0, ""}, {"NewDecoder", Func, 0, "func(enc *Encoding, r io.Reader) io.Reader"}, {"NewEncoder", Func, 0, "func(enc *Encoding, w io.Writer) io.WriteCloser"}, {"NewEncoding", Func, 0, "func(encoder string) *Encoding"}, {"NoPadding", Const, 9, ""}, {"StdEncoding", Var, 0, ""}, {"StdPadding", Const, 9, ""}, }, "encoding/base64": { {"(*Encoding).AppendDecode", Method, 22, ""}, {"(*Encoding).AppendEncode", Method, 22, ""}, {"(*Encoding).Decode", Method, 0, ""}, {"(*Encoding).DecodeString", Method, 0, ""}, {"(*Encoding).DecodedLen", Method, 0, ""}, {"(*Encoding).Encode", Method, 0, ""}, {"(*Encoding).EncodeToString", Method, 0, ""}, {"(*Encoding).EncodedLen", Method, 0, ""}, {"(CorruptInputError).Error", Method, 0, ""}, {"(Encoding).Strict", Method, 8, ""}, {"(Encoding).WithPadding", Method, 5, ""}, {"CorruptInputError", Type, 0, ""}, {"Encoding", Type, 0, ""}, {"NewDecoder", Func, 0, "func(enc *Encoding, r io.Reader) io.Reader"}, {"NewEncoder", Func, 0, "func(enc *Encoding, w io.Writer) io.WriteCloser"}, {"NewEncoding", Func, 0, "func(encoder string) *Encoding"}, {"NoPadding", Const, 5, ""}, {"RawStdEncoding", Var, 5, ""}, {"RawURLEncoding", Var, 5, ""}, {"StdEncoding", Var, 0, ""}, {"StdPadding", Const, 5, ""}, {"URLEncoding", Var, 0, ""}, }, "encoding/binary": { {"Append", Func, 23, "func(buf []byte, order ByteOrder, data any) ([]byte, error)"}, {"AppendByteOrder", Type, 19, ""}, {"AppendUvarint", Func, 19, "func(buf []byte, x uint64) []byte"}, {"AppendVarint", Func, 19, "func(buf []byte, x int64) []byte"}, {"BigEndian", Var, 0, ""}, {"ByteOrder", Type, 0, ""}, {"Decode", Func, 23, "func(buf []byte, order ByteOrder, data any) (int, error)"}, {"Encode", Func, 23, "func(buf []byte, order ByteOrder, data any) (int, error)"}, {"LittleEndian", Var, 0, ""}, {"MaxVarintLen16", Const, 0, ""}, {"MaxVarintLen32", Const, 0, ""}, {"MaxVarintLen64", Const, 0, ""}, {"NativeEndian", Var, 21, ""}, {"PutUvarint", Func, 0, "func(buf []byte, x uint64) int"}, {"PutVarint", Func, 0, "func(buf []byte, x int64) int"}, {"Read", Func, 0, "func(r io.Reader, order ByteOrder, data any) error"}, {"ReadUvarint", Func, 0, "func(r io.ByteReader) (uint64, error)"}, {"ReadVarint", Func, 0, "func(r io.ByteReader) (int64, error)"}, {"Size", Func, 0, "func(v any) int"}, {"Uvarint", Func, 0, "func(buf []byte) (uint64, int)"}, {"Varint", Func, 0, "func(buf []byte) (int64, int)"}, {"Write", Func, 0, "func(w io.Writer, order ByteOrder, data any) error"}, }, "encoding/csv": { {"(*ParseError).Error", Method, 0, ""}, {"(*ParseError).Unwrap", Method, 13, ""}, {"(*Reader).FieldPos", Method, 17, ""}, {"(*Reader).InputOffset", Method, 19, ""}, {"(*Reader).Read", Method, 0, ""}, {"(*Reader).ReadAll", Method, 0, ""}, {"(*Writer).Error", Method, 1, ""}, {"(*Writer).Flush", Method, 0, ""}, {"(*Writer).Write", Method, 0, ""}, {"(*Writer).WriteAll", Method, 0, ""}, {"ErrBareQuote", Var, 0, ""}, {"ErrFieldCount", Var, 0, ""}, {"ErrQuote", Var, 0, ""}, {"ErrTrailingComma", Var, 0, ""}, {"NewReader", Func, 0, "func(r io.Reader) *Reader"}, {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, {"ParseError", Type, 0, ""}, {"ParseError.Column", Field, 0, ""}, {"ParseError.Err", Field, 0, ""}, {"ParseError.Line", Field, 0, ""}, {"ParseError.StartLine", Field, 10, ""}, {"Reader", Type, 0, ""}, {"Reader.Comma", Field, 0, ""}, {"Reader.Comment", Field, 0, ""}, {"Reader.FieldsPerRecord", Field, 0, ""}, {"Reader.LazyQuotes", Field, 0, ""}, {"Reader.ReuseRecord", Field, 9, ""}, {"Reader.TrailingComma", Field, 0, ""}, {"Reader.TrimLeadingSpace", Field, 0, ""}, {"Writer", Type, 0, ""}, {"Writer.Comma", Field, 0, ""}, {"Writer.UseCRLF", Field, 0, ""}, }, "encoding/gob": { {"(*Decoder).Decode", Method, 0, ""}, {"(*Decoder).DecodeValue", Method, 0, ""}, {"(*Encoder).Encode", Method, 0, ""}, {"(*Encoder).EncodeValue", Method, 0, ""}, {"CommonType", Type, 0, ""}, {"CommonType.Id", Field, 0, ""}, {"CommonType.Name", Field, 0, ""}, {"Decoder", Type, 0, ""}, {"Encoder", Type, 0, ""}, {"GobDecoder", Type, 0, ""}, {"GobEncoder", Type, 0, ""}, {"NewDecoder", Func, 0, "func(r io.Reader) *Decoder"}, {"NewEncoder", Func, 0, "func(w io.Writer) *Encoder"}, {"Register", Func, 0, "func(value any)"}, {"RegisterName", Func, 0, "func(name string, value any)"}, }, "encoding/hex": { {"(InvalidByteError).Error", Method, 0, ""}, {"AppendDecode", Func, 22, "func(dst []byte, src []byte) ([]byte, error)"}, {"AppendEncode", Func, 22, "func(dst []byte, src []byte) []byte"}, {"Decode", Func, 0, "func(dst []byte, src []byte) (int, error)"}, {"DecodeString", Func, 0, "func(s string) ([]byte, error)"}, {"DecodedLen", Func, 0, "func(x int) int"}, {"Dump", Func, 0, "func(data []byte) string"}, {"Dumper", Func, 0, "func(w io.Writer) io.WriteCloser"}, {"Encode", Func, 0, "func(dst []byte, src []byte) int"}, {"EncodeToString", Func, 0, "func(src []byte) string"}, {"EncodedLen", Func, 0, "func(n int) int"}, {"ErrLength", Var, 0, ""}, {"InvalidByteError", Type, 0, ""}, {"NewDecoder", Func, 10, "func(r io.Reader) io.Reader"}, {"NewEncoder", Func, 10, "func(w io.Writer) io.Writer"}, }, "encoding/json": { {"(*Decoder).Buffered", Method, 1, ""}, {"(*Decoder).Decode", Method, 0, ""}, {"(*Decoder).DisallowUnknownFields", Method, 10, ""}, {"(*Decoder).InputOffset", Method, 14, ""}, {"(*Decoder).More", Method, 5, ""}, {"(*Decoder).Token", Method, 5, ""}, {"(*Decoder).UseNumber", Method, 1, ""}, {"(*Encoder).Encode", Method, 0, ""}, {"(*Encoder).SetEscapeHTML", Method, 7, ""}, {"(*Encoder).SetIndent", Method, 7, ""}, {"(*InvalidUTF8Error).Error", Method, 0, ""}, {"(*InvalidUnmarshalError).Error", Method, 0, ""}, {"(*MarshalerError).Error", Method, 0, ""}, {"(*MarshalerError).Unwrap", Method, 13, ""}, {"(*RawMessage).MarshalJSON", Method, 0, ""}, {"(*RawMessage).UnmarshalJSON", Method, 0, ""}, {"(*SyntaxError).Error", Method, 0, ""}, {"(*UnmarshalFieldError).Error", Method, 0, ""}, {"(*UnmarshalTypeError).Error", Method, 0, ""}, {"(*UnsupportedTypeError).Error", Method, 0, ""}, {"(*UnsupportedValueError).Error", Method, 0, ""}, {"(Delim).String", Method, 5, ""}, {"(Number).Float64", Method, 1, ""}, {"(Number).Int64", Method, 1, ""}, {"(Number).String", Method, 1, ""}, {"(RawMessage).MarshalJSON", Method, 8, ""}, {"Compact", Func, 0, "func(dst *bytes.Buffer, src []byte) error"}, {"Decoder", Type, 0, ""}, {"Delim", Type, 5, ""}, {"Encoder", Type, 0, ""}, {"HTMLEscape", Func, 0, "func(dst *bytes.Buffer, src []byte)"}, {"Indent", Func, 0, "func(dst *bytes.Buffer, src []byte, prefix string, indent string) error"}, {"InvalidUTF8Error", Type, 0, ""}, {"InvalidUTF8Error.S", Field, 0, ""}, {"InvalidUnmarshalError", Type, 0, ""}, {"InvalidUnmarshalError.Type", Field, 0, ""}, {"Marshal", Func, 0, "func(v any) ([]byte, error)"}, {"MarshalIndent", Func, 0, "func(v any, prefix string, indent string) ([]byte, error)"}, {"Marshaler", Type, 0, ""}, {"MarshalerError", Type, 0, ""}, {"MarshalerError.Err", Field, 0, ""}, {"MarshalerError.Type", Field, 0, ""}, {"NewDecoder", Func, 0, "func(r io.Reader) *Decoder"}, {"NewEncoder", Func, 0, "func(w io.Writer) *Encoder"}, {"Number", Type, 1, ""}, {"RawMessage", Type, 0, ""}, {"SyntaxError", Type, 0, ""}, {"SyntaxError.Offset", Field, 0, ""}, {"Token", Type, 5, ""}, {"Unmarshal", Func, 0, "func(data []byte, v any) error"}, {"UnmarshalFieldError", Type, 0, ""}, {"UnmarshalFieldError.Field", Field, 0, ""}, {"UnmarshalFieldError.Key", Field, 0, ""}, {"UnmarshalFieldError.Type", Field, 0, ""}, {"UnmarshalTypeError", Type, 0, ""}, {"UnmarshalTypeError.Field", Field, 8, ""}, {"UnmarshalTypeError.Offset", Field, 5, ""}, {"UnmarshalTypeError.Struct", Field, 8, ""}, {"UnmarshalTypeError.Type", Field, 0, ""}, {"UnmarshalTypeError.Value", Field, 0, ""}, {"Unmarshaler", Type, 0, ""}, {"UnsupportedTypeError", Type, 0, ""}, {"UnsupportedTypeError.Type", Field, 0, ""}, {"UnsupportedValueError", Type, 0, ""}, {"UnsupportedValueError.Str", Field, 0, ""}, {"UnsupportedValueError.Value", Field, 0, ""}, {"Valid", Func, 9, "func(data []byte) bool"}, }, "encoding/pem": { {"Block", Type, 0, ""}, {"Block.Bytes", Field, 0, ""}, {"Block.Headers", Field, 0, ""}, {"Block.Type", Field, 0, ""}, {"Decode", Func, 0, "func(data []byte) (p *Block, rest []byte)"}, {"Encode", Func, 0, "func(out io.Writer, b *Block) error"}, {"EncodeToMemory", Func, 0, "func(b *Block) []byte"}, }, "encoding/xml": { {"(*Decoder).Decode", Method, 0, ""}, {"(*Decoder).DecodeElement", Method, 0, ""}, {"(*Decoder).InputOffset", Method, 4, ""}, {"(*Decoder).InputPos", Method, 19, ""}, {"(*Decoder).RawToken", Method, 0, ""}, {"(*Decoder).Skip", Method, 0, ""}, {"(*Decoder).Token", Method, 0, ""}, {"(*Encoder).Close", Method, 20, ""}, {"(*Encoder).Encode", Method, 0, ""}, {"(*Encoder).EncodeElement", Method, 2, ""}, {"(*Encoder).EncodeToken", Method, 2, ""}, {"(*Encoder).Flush", Method, 2, ""}, {"(*Encoder).Indent", Method, 1, ""}, {"(*SyntaxError).Error", Method, 0, ""}, {"(*TagPathError).Error", Method, 0, ""}, {"(*UnsupportedTypeError).Error", Method, 0, ""}, {"(CharData).Copy", Method, 0, ""}, {"(Comment).Copy", Method, 0, ""}, {"(Directive).Copy", Method, 0, ""}, {"(ProcInst).Copy", Method, 0, ""}, {"(StartElement).Copy", Method, 0, ""}, {"(StartElement).End", Method, 2, ""}, {"(UnmarshalError).Error", Method, 0, ""}, {"Attr", Type, 0, ""}, {"Attr.Name", Field, 0, ""}, {"Attr.Value", Field, 0, ""}, {"CharData", Type, 0, ""}, {"Comment", Type, 0, ""}, {"CopyToken", Func, 0, "func(t Token) Token"}, {"Decoder", Type, 0, ""}, {"Decoder.AutoClose", Field, 0, ""}, {"Decoder.CharsetReader", Field, 0, ""}, {"Decoder.DefaultSpace", Field, 1, ""}, {"Decoder.Entity", Field, 0, ""}, {"Decoder.Strict", Field, 0, ""}, {"Directive", Type, 0, ""}, {"Encoder", Type, 0, ""}, {"EndElement", Type, 0, ""}, {"EndElement.Name", Field, 0, ""}, {"Escape", Func, 0, "func(w io.Writer, s []byte)"}, {"EscapeText", Func, 1, "func(w io.Writer, s []byte) error"}, {"HTMLAutoClose", Var, 0, ""}, {"HTMLEntity", Var, 0, ""}, {"Header", Const, 0, ""}, {"Marshal", Func, 0, "func(v any) ([]byte, error)"}, {"MarshalIndent", Func, 0, "func(v any, prefix string, indent string) ([]byte, error)"}, {"Marshaler", Type, 2, ""}, {"MarshalerAttr", Type, 2, ""}, {"Name", Type, 0, ""}, {"Name.Local", Field, 0, ""}, {"Name.Space", Field, 0, ""}, {"NewDecoder", Func, 0, "func(r io.Reader) *Decoder"}, {"NewEncoder", Func, 0, "func(w io.Writer) *Encoder"}, {"NewTokenDecoder", Func, 10, "func(t TokenReader) *Decoder"}, {"ProcInst", Type, 0, ""}, {"ProcInst.Inst", Field, 0, ""}, {"ProcInst.Target", Field, 0, ""}, {"StartElement", Type, 0, ""}, {"StartElement.Attr", Field, 0, ""}, {"StartElement.Name", Field, 0, ""}, {"SyntaxError", Type, 0, ""}, {"SyntaxError.Line", Field, 0, ""}, {"SyntaxError.Msg", Field, 0, ""}, {"TagPathError", Type, 0, ""}, {"TagPathError.Field1", Field, 0, ""}, {"TagPathError.Field2", Field, 0, ""}, {"TagPathError.Struct", Field, 0, ""}, {"TagPathError.Tag1", Field, 0, ""}, {"TagPathError.Tag2", Field, 0, ""}, {"Token", Type, 0, ""}, {"TokenReader", Type, 10, ""}, {"Unmarshal", Func, 0, "func(data []byte, v any) error"}, {"UnmarshalError", Type, 0, ""}, {"Unmarshaler", Type, 2, ""}, {"UnmarshalerAttr", Type, 2, ""}, {"UnsupportedTypeError", Type, 0, ""}, {"UnsupportedTypeError.Type", Field, 0, ""}, }, "errors": { {"As", Func, 13, "func(err error, target any) bool"}, {"ErrUnsupported", Var, 21, ""}, {"Is", Func, 13, "func(err error, target error) bool"}, {"Join", Func, 20, "func(errs ...error) error"}, {"New", Func, 0, "func(text string) error"}, {"Unwrap", Func, 13, "func(err error) error"}, }, "expvar": { {"(*Float).Add", Method, 0, ""}, {"(*Float).Set", Method, 0, ""}, {"(*Float).String", Method, 0, ""}, {"(*Float).Value", Method, 8, ""}, {"(*Int).Add", Method, 0, ""}, {"(*Int).Set", Method, 0, ""}, {"(*Int).String", Method, 0, ""}, {"(*Int).Value", Method, 8, ""}, {"(*Map).Add", Method, 0, ""}, {"(*Map).AddFloat", Method, 0, ""}, {"(*Map).Delete", Method, 12, ""}, {"(*Map).Do", Method, 0, ""}, {"(*Map).Get", Method, 0, ""}, {"(*Map).Init", Method, 0, ""}, {"(*Map).Set", Method, 0, ""}, {"(*Map).String", Method, 0, ""}, {"(*String).Set", Method, 0, ""}, {"(*String).String", Method, 0, ""}, {"(*String).Value", Method, 8, ""}, {"(Func).String", Method, 0, ""}, {"(Func).Value", Method, 8, ""}, {"Do", Func, 0, "func(f func(KeyValue))"}, {"Float", Type, 0, ""}, {"Func", Type, 0, ""}, {"Get", Func, 0, "func(name string) Var"}, {"Handler", Func, 8, "func() http.Handler"}, {"Int", Type, 0, ""}, {"KeyValue", Type, 0, ""}, {"KeyValue.Key", Field, 0, ""}, {"KeyValue.Value", Field, 0, ""}, {"Map", Type, 0, ""}, {"NewFloat", Func, 0, "func(name string) *Float"}, {"NewInt", Func, 0, "func(name string) *Int"}, {"NewMap", Func, 0, "func(name string) *Map"}, {"NewString", Func, 0, "func(name string) *String"}, {"Publish", Func, 0, "func(name string, v Var)"}, {"String", Type, 0, ""}, {"Var", Type, 0, ""}, }, "flag": { {"(*FlagSet).Arg", Method, 0, ""}, {"(*FlagSet).Args", Method, 0, ""}, {"(*FlagSet).Bool", Method, 0, ""}, {"(*FlagSet).BoolFunc", Method, 21, ""}, {"(*FlagSet).BoolVar", Method, 0, ""}, {"(*FlagSet).Duration", Method, 0, ""}, {"(*FlagSet).DurationVar", Method, 0, ""}, {"(*FlagSet).ErrorHandling", Method, 10, ""}, {"(*FlagSet).Float64", Method, 0, ""}, {"(*FlagSet).Float64Var", Method, 0, ""}, {"(*FlagSet).Func", Method, 16, ""}, {"(*FlagSet).Init", Method, 0, ""}, {"(*FlagSet).Int", Method, 0, ""}, {"(*FlagSet).Int64", Method, 0, ""}, {"(*FlagSet).Int64Var", Method, 0, ""}, {"(*FlagSet).IntVar", Method, 0, ""}, {"(*FlagSet).Lookup", Method, 0, ""}, {"(*FlagSet).NArg", Method, 0, ""}, {"(*FlagSet).NFlag", Method, 0, ""}, {"(*FlagSet).Name", Method, 10, ""}, {"(*FlagSet).Output", Method, 10, ""}, {"(*FlagSet).Parse", Method, 0, ""}, {"(*FlagSet).Parsed", Method, 0, ""}, {"(*FlagSet).PrintDefaults", Method, 0, ""}, {"(*FlagSet).Set", Method, 0, ""}, {"(*FlagSet).SetOutput", Method, 0, ""}, {"(*FlagSet).String", Method, 0, ""}, {"(*FlagSet).StringVar", Method, 0, ""}, {"(*FlagSet).TextVar", Method, 19, ""}, {"(*FlagSet).Uint", Method, 0, ""}, {"(*FlagSet).Uint64", Method, 0, ""}, {"(*FlagSet).Uint64Var", Method, 0, ""}, {"(*FlagSet).UintVar", Method, 0, ""}, {"(*FlagSet).Var", Method, 0, ""}, {"(*FlagSet).Visit", Method, 0, ""}, {"(*FlagSet).VisitAll", Method, 0, ""}, {"Arg", Func, 0, "func(i int) string"}, {"Args", Func, 0, "func() []string"}, {"Bool", Func, 0, "func(name string, value bool, usage string) *bool"}, {"BoolFunc", Func, 21, "func(name string, usage string, fn func(string) error)"}, {"BoolVar", Func, 0, "func(p *bool, name string, value bool, usage string)"}, {"CommandLine", Var, 2, ""}, {"ContinueOnError", Const, 0, ""}, {"Duration", Func, 0, "func(name string, value time.Duration, usage string) *time.Duration"}, {"DurationVar", Func, 0, "func(p *time.Duration, name string, value time.Duration, usage string)"}, {"ErrHelp", Var, 0, ""}, {"ErrorHandling", Type, 0, ""}, {"ExitOnError", Const, 0, ""}, {"Flag", Type, 0, ""}, {"Flag.DefValue", Field, 0, ""}, {"Flag.Name", Field, 0, ""}, {"Flag.Usage", Field, 0, ""}, {"Flag.Value", Field, 0, ""}, {"FlagSet", Type, 0, ""}, {"FlagSet.Usage", Field, 0, ""}, {"Float64", Func, 0, "func(name string, value float64, usage string) *float64"}, {"Float64Var", Func, 0, "func(p *float64, name string, value float64, usage string)"}, {"Func", Func, 16, "func(name string, usage string, fn func(string) error)"}, {"Getter", Type, 2, ""}, {"Int", Func, 0, "func(name string, value int, usage string) *int"}, {"Int64", Func, 0, "func(name string, value int64, usage string) *int64"}, {"Int64Var", Func, 0, "func(p *int64, name string, value int64, usage string)"}, {"IntVar", Func, 0, "func(p *int, name string, value int, usage string)"}, {"Lookup", Func, 0, "func(name string) *Flag"}, {"NArg", Func, 0, "func() int"}, {"NFlag", Func, 0, "func() int"}, {"NewFlagSet", Func, 0, "func(name string, errorHandling ErrorHandling) *FlagSet"}, {"PanicOnError", Const, 0, ""}, {"Parse", Func, 0, "func()"}, {"Parsed", Func, 0, "func() bool"}, {"PrintDefaults", Func, 0, "func()"}, {"Set", Func, 0, "func(name string, value string) error"}, {"String", Func, 0, "func(name string, value string, usage string) *string"}, {"StringVar", Func, 0, "func(p *string, name string, value string, usage string)"}, {"TextVar", Func, 19, "func(p encoding.TextUnmarshaler, name string, value encoding.TextMarshaler, usage string)"}, {"Uint", Func, 0, "func(name string, value uint, usage string) *uint"}, {"Uint64", Func, 0, "func(name string, value uint64, usage string) *uint64"}, {"Uint64Var", Func, 0, "func(p *uint64, name string, value uint64, usage string)"}, {"UintVar", Func, 0, "func(p *uint, name string, value uint, usage string)"}, {"UnquoteUsage", Func, 5, "func(flag *Flag) (name string, usage string)"}, {"Usage", Var, 0, ""}, {"Value", Type, 0, ""}, {"Var", Func, 0, "func(value Value, name string, usage string)"}, {"Visit", Func, 0, "func(fn func(*Flag))"}, {"VisitAll", Func, 0, "func(fn func(*Flag))"}, }, "fmt": { {"Append", Func, 19, "func(b []byte, a ...any) []byte"}, {"Appendf", Func, 19, "func(b []byte, format string, a ...any) []byte"}, {"Appendln", Func, 19, "func(b []byte, a ...any) []byte"}, {"Errorf", Func, 0, "func(format string, a ...any) error"}, {"FormatString", Func, 20, "func(state State, verb rune) string"}, {"Formatter", Type, 0, ""}, {"Fprint", Func, 0, "func(w io.Writer, a ...any) (n int, err error)"}, {"Fprintf", Func, 0, "func(w io.Writer, format string, a ...any) (n int, err error)"}, {"Fprintln", Func, 0, "func(w io.Writer, a ...any) (n int, err error)"}, {"Fscan", Func, 0, "func(r io.Reader, a ...any) (n int, err error)"}, {"Fscanf", Func, 0, "func(r io.Reader, format string, a ...any) (n int, err error)"}, {"Fscanln", Func, 0, "func(r io.Reader, a ...any) (n int, err error)"}, {"GoStringer", Type, 0, ""}, {"Print", Func, 0, "func(a ...any) (n int, err error)"}, {"Printf", Func, 0, "func(format string, a ...any) (n int, err error)"}, {"Println", Func, 0, "func(a ...any) (n int, err error)"}, {"Scan", Func, 0, "func(a ...any) (n int, err error)"}, {"ScanState", Type, 0, ""}, {"Scanf", Func, 0, "func(format string, a ...any) (n int, err error)"}, {"Scanln", Func, 0, "func(a ...any) (n int, err error)"}, {"Scanner", Type, 0, ""}, {"Sprint", Func, 0, "func(a ...any) string"}, {"Sprintf", Func, 0, "func(format string, a ...any) string"}, {"Sprintln", Func, 0, "func(a ...any) string"}, {"Sscan", Func, 0, "func(str string, a ...any) (n int, err error)"}, {"Sscanf", Func, 0, "func(str string, format string, a ...any) (n int, err error)"}, {"Sscanln", Func, 0, "func(str string, a ...any) (n int, err error)"}, {"State", Type, 0, ""}, {"Stringer", Type, 0, ""}, }, "go/ast": { {"(*ArrayType).End", Method, 0, ""}, {"(*ArrayType).Pos", Method, 0, ""}, {"(*AssignStmt).End", Method, 0, ""}, {"(*AssignStmt).Pos", Method, 0, ""}, {"(*BadDecl).End", Method, 0, ""}, {"(*BadDecl).Pos", Method, 0, ""}, {"(*BadExpr).End", Method, 0, ""}, {"(*BadExpr).Pos", Method, 0, ""}, {"(*BadStmt).End", Method, 0, ""}, {"(*BadStmt).Pos", Method, 0, ""}, {"(*BasicLit).End", Method, 0, ""}, {"(*BasicLit).Pos", Method, 0, ""}, {"(*BinaryExpr).End", Method, 0, ""}, {"(*BinaryExpr).Pos", Method, 0, ""}, {"(*BlockStmt).End", Method, 0, ""}, {"(*BlockStmt).Pos", Method, 0, ""}, {"(*BranchStmt).End", Method, 0, ""}, {"(*BranchStmt).Pos", Method, 0, ""}, {"(*CallExpr).End", Method, 0, ""}, {"(*CallExpr).Pos", Method, 0, ""}, {"(*CaseClause).End", Method, 0, ""}, {"(*CaseClause).Pos", Method, 0, ""}, {"(*ChanType).End", Method, 0, ""}, {"(*ChanType).Pos", Method, 0, ""}, {"(*CommClause).End", Method, 0, ""}, {"(*CommClause).Pos", Method, 0, ""}, {"(*Comment).End", Method, 0, ""}, {"(*Comment).Pos", Method, 0, ""}, {"(*CommentGroup).End", Method, 0, ""}, {"(*CommentGroup).Pos", Method, 0, ""}, {"(*CommentGroup).Text", Method, 0, ""}, {"(*CompositeLit).End", Method, 0, ""}, {"(*CompositeLit).Pos", Method, 0, ""}, {"(*DeclStmt).End", Method, 0, ""}, {"(*DeclStmt).Pos", Method, 0, ""}, {"(*DeferStmt).End", Method, 0, ""}, {"(*DeferStmt).Pos", Method, 0, ""}, {"(*Ellipsis).End", Method, 0, ""}, {"(*Ellipsis).Pos", Method, 0, ""}, {"(*EmptyStmt).End", Method, 0, ""}, {"(*EmptyStmt).Pos", Method, 0, ""}, {"(*ExprStmt).End", Method, 0, ""}, {"(*ExprStmt).Pos", Method, 0, ""}, {"(*Field).End", Method, 0, ""}, {"(*Field).Pos", Method, 0, ""}, {"(*FieldList).End", Method, 0, ""}, {"(*FieldList).NumFields", Method, 0, ""}, {"(*FieldList).Pos", Method, 0, ""}, {"(*File).End", Method, 0, ""}, {"(*File).Pos", Method, 0, ""}, {"(*ForStmt).End", Method, 0, ""}, {"(*ForStmt).Pos", Method, 0, ""}, {"(*FuncDecl).End", Method, 0, ""}, {"(*FuncDecl).Pos", Method, 0, ""}, {"(*FuncLit).End", Method, 0, ""}, {"(*FuncLit).Pos", Method, 0, ""}, {"(*FuncType).End", Method, 0, ""}, {"(*FuncType).Pos", Method, 0, ""}, {"(*GenDecl).End", Method, 0, ""}, {"(*GenDecl).Pos", Method, 0, ""}, {"(*GoStmt).End", Method, 0, ""}, {"(*GoStmt).Pos", Method, 0, ""}, {"(*Ident).End", Method, 0, ""}, {"(*Ident).IsExported", Method, 0, ""}, {"(*Ident).Pos", Method, 0, ""}, {"(*Ident).String", Method, 0, ""}, {"(*IfStmt).End", Method, 0, ""}, {"(*IfStmt).Pos", Method, 0, ""}, {"(*ImportSpec).End", Method, 0, ""}, {"(*ImportSpec).Pos", Method, 0, ""}, {"(*IncDecStmt).End", Method, 0, ""}, {"(*IncDecStmt).Pos", Method, 0, ""}, {"(*IndexExpr).End", Method, 0, ""}, {"(*IndexExpr).Pos", Method, 0, ""}, {"(*IndexListExpr).End", Method, 18, ""}, {"(*IndexListExpr).Pos", Method, 18, ""}, {"(*InterfaceType).End", Method, 0, ""}, {"(*InterfaceType).Pos", Method, 0, ""}, {"(*KeyValueExpr).End", Method, 0, ""}, {"(*KeyValueExpr).Pos", Method, 0, ""}, {"(*LabeledStmt).End", Method, 0, ""}, {"(*LabeledStmt).Pos", Method, 0, ""}, {"(*MapType).End", Method, 0, ""}, {"(*MapType).Pos", Method, 0, ""}, {"(*Object).Pos", Method, 0, ""}, {"(*Package).End", Method, 0, ""}, {"(*Package).Pos", Method, 0, ""}, {"(*ParenExpr).End", Method, 0, ""}, {"(*ParenExpr).Pos", Method, 0, ""}, {"(*RangeStmt).End", Method, 0, ""}, {"(*RangeStmt).Pos", Method, 0, ""}, {"(*ReturnStmt).End", Method, 0, ""}, {"(*ReturnStmt).Pos", Method, 0, ""}, {"(*Scope).Insert", Method, 0, ""}, {"(*Scope).Lookup", Method, 0, ""}, {"(*Scope).String", Method, 0, ""}, {"(*SelectStmt).End", Method, 0, ""}, {"(*SelectStmt).Pos", Method, 0, ""}, {"(*SelectorExpr).End", Method, 0, ""}, {"(*SelectorExpr).Pos", Method, 0, ""}, {"(*SendStmt).End", Method, 0, ""}, {"(*SendStmt).Pos", Method, 0, ""}, {"(*SliceExpr).End", Method, 0, ""}, {"(*SliceExpr).Pos", Method, 0, ""}, {"(*StarExpr).End", Method, 0, ""}, {"(*StarExpr).Pos", Method, 0, ""}, {"(*StructType).End", Method, 0, ""}, {"(*StructType).Pos", Method, 0, ""}, {"(*SwitchStmt).End", Method, 0, ""}, {"(*SwitchStmt).Pos", Method, 0, ""}, {"(*TypeAssertExpr).End", Method, 0, ""}, {"(*TypeAssertExpr).Pos", Method, 0, ""}, {"(*TypeSpec).End", Method, 0, ""}, {"(*TypeSpec).Pos", Method, 0, ""}, {"(*TypeSwitchStmt).End", Method, 0, ""}, {"(*TypeSwitchStmt).Pos", Method, 0, ""}, {"(*UnaryExpr).End", Method, 0, ""}, {"(*UnaryExpr).Pos", Method, 0, ""}, {"(*ValueSpec).End", Method, 0, ""}, {"(*ValueSpec).Pos", Method, 0, ""}, {"(CommentMap).Comments", Method, 1, ""}, {"(CommentMap).Filter", Method, 1, ""}, {"(CommentMap).String", Method, 1, ""}, {"(CommentMap).Update", Method, 1, ""}, {"(ObjKind).String", Method, 0, ""}, {"ArrayType", Type, 0, ""}, {"ArrayType.Elt", Field, 0, ""}, {"ArrayType.Lbrack", Field, 0, ""}, {"ArrayType.Len", Field, 0, ""}, {"AssignStmt", Type, 0, ""}, {"AssignStmt.Lhs", Field, 0, ""}, {"AssignStmt.Rhs", Field, 0, ""}, {"AssignStmt.Tok", Field, 0, ""}, {"AssignStmt.TokPos", Field, 0, ""}, {"Bad", Const, 0, ""}, {"BadDecl", Type, 0, ""}, {"BadDecl.From", Field, 0, ""}, {"BadDecl.To", Field, 0, ""}, {"BadExpr", Type, 0, ""}, {"BadExpr.From", Field, 0, ""}, {"BadExpr.To", Field, 0, ""}, {"BadStmt", Type, 0, ""}, {"BadStmt.From", Field, 0, ""}, {"BadStmt.To", Field, 0, ""}, {"BasicLit", Type, 0, ""}, {"BasicLit.Kind", Field, 0, ""}, {"BasicLit.Value", Field, 0, ""}, {"BasicLit.ValuePos", Field, 0, ""}, {"BinaryExpr", Type, 0, ""}, {"BinaryExpr.Op", Field, 0, ""}, {"BinaryExpr.OpPos", Field, 0, ""}, {"BinaryExpr.X", Field, 0, ""}, {"BinaryExpr.Y", Field, 0, ""}, {"BlockStmt", Type, 0, ""}, {"BlockStmt.Lbrace", Field, 0, ""}, {"BlockStmt.List", Field, 0, ""}, {"BlockStmt.Rbrace", Field, 0, ""}, {"BranchStmt", Type, 0, ""}, {"BranchStmt.Label", Field, 0, ""}, {"BranchStmt.Tok", Field, 0, ""}, {"BranchStmt.TokPos", Field, 0, ""}, {"CallExpr", Type, 0, ""}, {"CallExpr.Args", Field, 0, ""}, {"CallExpr.Ellipsis", Field, 0, ""}, {"CallExpr.Fun", Field, 0, ""}, {"CallExpr.Lparen", Field, 0, ""}, {"CallExpr.Rparen", Field, 0, ""}, {"CaseClause", Type, 0, ""}, {"CaseClause.Body", Field, 0, ""}, {"CaseClause.Case", Field, 0, ""}, {"CaseClause.Colon", Field, 0, ""}, {"CaseClause.List", Field, 0, ""}, {"ChanDir", Type, 0, ""}, {"ChanType", Type, 0, ""}, {"ChanType.Arrow", Field, 1, ""}, {"ChanType.Begin", Field, 0, ""}, {"ChanType.Dir", Field, 0, ""}, {"ChanType.Value", Field, 0, ""}, {"CommClause", Type, 0, ""}, {"CommClause.Body", Field, 0, ""}, {"CommClause.Case", Field, 0, ""}, {"CommClause.Colon", Field, 0, ""}, {"CommClause.Comm", Field, 0, ""}, {"Comment", Type, 0, ""}, {"Comment.Slash", Field, 0, ""}, {"Comment.Text", Field, 0, ""}, {"CommentGroup", Type, 0, ""}, {"CommentGroup.List", Field, 0, ""}, {"CommentMap", Type, 1, ""}, {"CompositeLit", Type, 0, ""}, {"CompositeLit.Elts", Field, 0, ""}, {"CompositeLit.Incomplete", Field, 11, ""}, {"CompositeLit.Lbrace", Field, 0, ""}, {"CompositeLit.Rbrace", Field, 0, ""}, {"CompositeLit.Type", Field, 0, ""}, {"Con", Const, 0, ""}, {"Decl", Type, 0, ""}, {"DeclStmt", Type, 0, ""}, {"DeclStmt.Decl", Field, 0, ""}, {"DeferStmt", Type, 0, ""}, {"DeferStmt.Call", Field, 0, ""}, {"DeferStmt.Defer", Field, 0, ""}, {"Ellipsis", Type, 0, ""}, {"Ellipsis.Ellipsis", Field, 0, ""}, {"Ellipsis.Elt", Field, 0, ""}, {"EmptyStmt", Type, 0, ""}, {"EmptyStmt.Implicit", Field, 5, ""}, {"EmptyStmt.Semicolon", Field, 0, ""}, {"Expr", Type, 0, ""}, {"ExprStmt", Type, 0, ""}, {"ExprStmt.X", Field, 0, ""}, {"Field", Type, 0, ""}, {"Field.Comment", Field, 0, ""}, {"Field.Doc", Field, 0, ""}, {"Field.Names", Field, 0, ""}, {"Field.Tag", Field, 0, ""}, {"Field.Type", Field, 0, ""}, {"FieldFilter", Type, 0, ""}, {"FieldList", Type, 0, ""}, {"FieldList.Closing", Field, 0, ""}, {"FieldList.List", Field, 0, ""}, {"FieldList.Opening", Field, 0, ""}, {"File", Type, 0, ""}, {"File.Comments", Field, 0, ""}, {"File.Decls", Field, 0, ""}, {"File.Doc", Field, 0, ""}, {"File.FileEnd", Field, 20, ""}, {"File.FileStart", Field, 20, ""}, {"File.GoVersion", Field, 21, ""}, {"File.Imports", Field, 0, ""}, {"File.Name", Field, 0, ""}, {"File.Package", Field, 0, ""}, {"File.Scope", Field, 0, ""}, {"File.Unresolved", Field, 0, ""}, {"FileExports", Func, 0, "func(src *File) bool"}, {"Filter", Type, 0, ""}, {"FilterDecl", Func, 0, "func(decl Decl, f Filter) bool"}, {"FilterFile", Func, 0, "func(src *File, f Filter) bool"}, {"FilterFuncDuplicates", Const, 0, ""}, {"FilterImportDuplicates", Const, 0, ""}, {"FilterPackage", Func, 0, "func(pkg *Package, f Filter) bool"}, {"FilterUnassociatedComments", Const, 0, ""}, {"ForStmt", Type, 0, ""}, {"ForStmt.Body", Field, 0, ""}, {"ForStmt.Cond", Field, 0, ""}, {"ForStmt.For", Field, 0, ""}, {"ForStmt.Init", Field, 0, ""}, {"ForStmt.Post", Field, 0, ""}, {"Fprint", Func, 0, "func(w io.Writer, fset *token.FileSet, x any, f FieldFilter) error"}, {"Fun", Const, 0, ""}, {"FuncDecl", Type, 0, ""}, {"FuncDecl.Body", Field, 0, ""}, {"FuncDecl.Doc", Field, 0, ""}, {"FuncDecl.Name", Field, 0, ""}, {"FuncDecl.Recv", Field, 0, ""}, {"FuncDecl.Type", Field, 0, ""}, {"FuncLit", Type, 0, ""}, {"FuncLit.Body", Field, 0, ""}, {"FuncLit.Type", Field, 0, ""}, {"FuncType", Type, 0, ""}, {"FuncType.Func", Field, 0, ""}, {"FuncType.Params", Field, 0, ""}, {"FuncType.Results", Field, 0, ""}, {"FuncType.TypeParams", Field, 18, ""}, {"GenDecl", Type, 0, ""}, {"GenDecl.Doc", Field, 0, ""}, {"GenDecl.Lparen", Field, 0, ""}, {"GenDecl.Rparen", Field, 0, ""}, {"GenDecl.Specs", Field, 0, ""}, {"GenDecl.Tok", Field, 0, ""}, {"GenDecl.TokPos", Field, 0, ""}, {"GoStmt", Type, 0, ""}, {"GoStmt.Call", Field, 0, ""}, {"GoStmt.Go", Field, 0, ""}, {"Ident", Type, 0, ""}, {"Ident.Name", Field, 0, ""}, {"Ident.NamePos", Field, 0, ""}, {"Ident.Obj", Field, 0, ""}, {"IfStmt", Type, 0, ""}, {"IfStmt.Body", Field, 0, ""}, {"IfStmt.Cond", Field, 0, ""}, {"IfStmt.Else", Field, 0, ""}, {"IfStmt.If", Field, 0, ""}, {"IfStmt.Init", Field, 0, ""}, {"ImportSpec", Type, 0, ""}, {"ImportSpec.Comment", Field, 0, ""}, {"ImportSpec.Doc", Field, 0, ""}, {"ImportSpec.EndPos", Field, 0, ""}, {"ImportSpec.Name", Field, 0, ""}, {"ImportSpec.Path", Field, 0, ""}, {"Importer", Type, 0, ""}, {"IncDecStmt", Type, 0, ""}, {"IncDecStmt.Tok", Field, 0, ""}, {"IncDecStmt.TokPos", Field, 0, ""}, {"IncDecStmt.X", Field, 0, ""}, {"IndexExpr", Type, 0, ""}, {"IndexExpr.Index", Field, 0, ""}, {"IndexExpr.Lbrack", Field, 0, ""}, {"IndexExpr.Rbrack", Field, 0, ""}, {"IndexExpr.X", Field, 0, ""}, {"IndexListExpr", Type, 18, ""}, {"IndexListExpr.Indices", Field, 18, ""}, {"IndexListExpr.Lbrack", Field, 18, ""}, {"IndexListExpr.Rbrack", Field, 18, ""}, {"IndexListExpr.X", Field, 18, ""}, {"Inspect", Func, 0, "func(node Node, f func(Node) bool)"}, {"InterfaceType", Type, 0, ""}, {"InterfaceType.Incomplete", Field, 0, ""}, {"InterfaceType.Interface", Field, 0, ""}, {"InterfaceType.Methods", Field, 0, ""}, {"IsExported", Func, 0, "func(name string) bool"}, {"IsGenerated", Func, 21, "func(file *File) bool"}, {"KeyValueExpr", Type, 0, ""}, {"KeyValueExpr.Colon", Field, 0, ""}, {"KeyValueExpr.Key", Field, 0, ""}, {"KeyValueExpr.Value", Field, 0, ""}, {"LabeledStmt", Type, 0, ""}, {"LabeledStmt.Colon", Field, 0, ""}, {"LabeledStmt.Label", Field, 0, ""}, {"LabeledStmt.Stmt", Field, 0, ""}, {"Lbl", Const, 0, ""}, {"MapType", Type, 0, ""}, {"MapType.Key", Field, 0, ""}, {"MapType.Map", Field, 0, ""}, {"MapType.Value", Field, 0, ""}, {"MergeMode", Type, 0, ""}, {"MergePackageFiles", Func, 0, "func(pkg *Package, mode MergeMode) *File"}, {"NewCommentMap", Func, 1, "func(fset *token.FileSet, node Node, comments []*CommentGroup) CommentMap"}, {"NewIdent", Func, 0, "func(name string) *Ident"}, {"NewObj", Func, 0, "func(kind ObjKind, name string) *Object"}, {"NewPackage", Func, 0, "func(fset *token.FileSet, files map[string]*File, importer Importer, universe *Scope) (*Package, error)"}, {"NewScope", Func, 0, "func(outer *Scope) *Scope"}, {"Node", Type, 0, ""}, {"NotNilFilter", Func, 0, "func(_ string, v reflect.Value) bool"}, {"ObjKind", Type, 0, ""}, {"Object", Type, 0, ""}, {"Object.Data", Field, 0, ""}, {"Object.Decl", Field, 0, ""}, {"Object.Kind", Field, 0, ""}, {"Object.Name", Field, 0, ""}, {"Object.Type", Field, 0, ""}, {"Package", Type, 0, ""}, {"Package.Files", Field, 0, ""}, {"Package.Imports", Field, 0, ""}, {"Package.Name", Field, 0, ""}, {"Package.Scope", Field, 0, ""}, {"PackageExports", Func, 0, "func(pkg *Package) bool"}, {"ParenExpr", Type, 0, ""}, {"ParenExpr.Lparen", Field, 0, ""}, {"ParenExpr.Rparen", Field, 0, ""}, {"ParenExpr.X", Field, 0, ""}, {"Pkg", Const, 0, ""}, {"Preorder", Func, 23, "func(root Node) iter.Seq[Node]"}, {"Print", Func, 0, "func(fset *token.FileSet, x any) error"}, {"RECV", Const, 0, ""}, {"RangeStmt", Type, 0, ""}, {"RangeStmt.Body", Field, 0, ""}, {"RangeStmt.For", Field, 0, ""}, {"RangeStmt.Key", Field, 0, ""}, {"RangeStmt.Range", Field, 20, ""}, {"RangeStmt.Tok", Field, 0, ""}, {"RangeStmt.TokPos", Field, 0, ""}, {"RangeStmt.Value", Field, 0, ""}, {"RangeStmt.X", Field, 0, ""}, {"ReturnStmt", Type, 0, ""}, {"ReturnStmt.Results", Field, 0, ""}, {"ReturnStmt.Return", Field, 0, ""}, {"SEND", Const, 0, ""}, {"Scope", Type, 0, ""}, {"Scope.Objects", Field, 0, ""}, {"Scope.Outer", Field, 0, ""}, {"SelectStmt", Type, 0, ""}, {"SelectStmt.Body", Field, 0, ""}, {"SelectStmt.Select", Field, 0, ""}, {"SelectorExpr", Type, 0, ""}, {"SelectorExpr.Sel", Field, 0, ""}, {"SelectorExpr.X", Field, 0, ""}, {"SendStmt", Type, 0, ""}, {"SendStmt.Arrow", Field, 0, ""}, {"SendStmt.Chan", Field, 0, ""}, {"SendStmt.Value", Field, 0, ""}, {"SliceExpr", Type, 0, ""}, {"SliceExpr.High", Field, 0, ""}, {"SliceExpr.Lbrack", Field, 0, ""}, {"SliceExpr.Low", Field, 0, ""}, {"SliceExpr.Max", Field, 2, ""}, {"SliceExpr.Rbrack", Field, 0, ""}, {"SliceExpr.Slice3", Field, 2, ""}, {"SliceExpr.X", Field, 0, ""}, {"SortImports", Func, 0, "func(fset *token.FileSet, f *File)"}, {"Spec", Type, 0, ""}, {"StarExpr", Type, 0, ""}, {"StarExpr.Star", Field, 0, ""}, {"StarExpr.X", Field, 0, ""}, {"Stmt", Type, 0, ""}, {"StructType", Type, 0, ""}, {"StructType.Fields", Field, 0, ""}, {"StructType.Incomplete", Field, 0, ""}, {"StructType.Struct", Field, 0, ""}, {"SwitchStmt", Type, 0, ""}, {"SwitchStmt.Body", Field, 0, ""}, {"SwitchStmt.Init", Field, 0, ""}, {"SwitchStmt.Switch", Field, 0, ""}, {"SwitchStmt.Tag", Field, 0, ""}, {"Typ", Const, 0, ""}, {"TypeAssertExpr", Type, 0, ""}, {"TypeAssertExpr.Lparen", Field, 2, ""}, {"TypeAssertExpr.Rparen", Field, 2, ""}, {"TypeAssertExpr.Type", Field, 0, ""}, {"TypeAssertExpr.X", Field, 0, ""}, {"TypeSpec", Type, 0, ""}, {"TypeSpec.Assign", Field, 9, ""}, {"TypeSpec.Comment", Field, 0, ""}, {"TypeSpec.Doc", Field, 0, ""}, {"TypeSpec.Name", Field, 0, ""}, {"TypeSpec.Type", Field, 0, ""}, {"TypeSpec.TypeParams", Field, 18, ""}, {"TypeSwitchStmt", Type, 0, ""}, {"TypeSwitchStmt.Assign", Field, 0, ""}, {"TypeSwitchStmt.Body", Field, 0, ""}, {"TypeSwitchStmt.Init", Field, 0, ""}, {"TypeSwitchStmt.Switch", Field, 0, ""}, {"UnaryExpr", Type, 0, ""}, {"UnaryExpr.Op", Field, 0, ""}, {"UnaryExpr.OpPos", Field, 0, ""}, {"UnaryExpr.X", Field, 0, ""}, {"Unparen", Func, 22, "func(e Expr) Expr"}, {"ValueSpec", Type, 0, ""}, {"ValueSpec.Comment", Field, 0, ""}, {"ValueSpec.Doc", Field, 0, ""}, {"ValueSpec.Names", Field, 0, ""}, {"ValueSpec.Type", Field, 0, ""}, {"ValueSpec.Values", Field, 0, ""}, {"Var", Const, 0, ""}, {"Visitor", Type, 0, ""}, {"Walk", Func, 0, "func(v Visitor, node Node)"}, }, "go/build": { {"(*Context).Import", Method, 0, ""}, {"(*Context).ImportDir", Method, 0, ""}, {"(*Context).MatchFile", Method, 2, ""}, {"(*Context).SrcDirs", Method, 0, ""}, {"(*MultiplePackageError).Error", Method, 4, ""}, {"(*NoGoError).Error", Method, 0, ""}, {"(*Package).IsCommand", Method, 0, ""}, {"AllowBinary", Const, 0, ""}, {"ArchChar", Func, 0, "func(goarch string) (string, error)"}, {"Context", Type, 0, ""}, {"Context.BuildTags", Field, 0, ""}, {"Context.CgoEnabled", Field, 0, ""}, {"Context.Compiler", Field, 0, ""}, {"Context.Dir", Field, 14, ""}, {"Context.GOARCH", Field, 0, ""}, {"Context.GOOS", Field, 0, ""}, {"Context.GOPATH", Field, 0, ""}, {"Context.GOROOT", Field, 0, ""}, {"Context.HasSubdir", Field, 0, ""}, {"Context.InstallSuffix", Field, 1, ""}, {"Context.IsAbsPath", Field, 0, ""}, {"Context.IsDir", Field, 0, ""}, {"Context.JoinPath", Field, 0, ""}, {"Context.OpenFile", Field, 0, ""}, {"Context.ReadDir", Field, 0, ""}, {"Context.ReleaseTags", Field, 1, ""}, {"Context.SplitPathList", Field, 0, ""}, {"Context.ToolTags", Field, 17, ""}, {"Context.UseAllFiles", Field, 0, ""}, {"Default", Var, 0, ""}, {"Directive", Type, 21, ""}, {"Directive.Pos", Field, 21, ""}, {"Directive.Text", Field, 21, ""}, {"FindOnly", Const, 0, ""}, {"IgnoreVendor", Const, 6, ""}, {"Import", Func, 0, "func(path string, srcDir string, mode ImportMode) (*Package, error)"}, {"ImportComment", Const, 4, ""}, {"ImportDir", Func, 0, "func(dir string, mode ImportMode) (*Package, error)"}, {"ImportMode", Type, 0, ""}, {"IsLocalImport", Func, 0, "func(path string) bool"}, {"MultiplePackageError", Type, 4, ""}, {"MultiplePackageError.Dir", Field, 4, ""}, {"MultiplePackageError.Files", Field, 4, ""}, {"MultiplePackageError.Packages", Field, 4, ""}, {"NoGoError", Type, 0, ""}, {"NoGoError.Dir", Field, 0, ""}, {"Package", Type, 0, ""}, {"Package.AllTags", Field, 2, ""}, {"Package.BinDir", Field, 0, ""}, {"Package.BinaryOnly", Field, 7, ""}, {"Package.CFiles", Field, 0, ""}, {"Package.CXXFiles", Field, 2, ""}, {"Package.CgoCFLAGS", Field, 0, ""}, {"Package.CgoCPPFLAGS", Field, 2, ""}, {"Package.CgoCXXFLAGS", Field, 2, ""}, {"Package.CgoFFLAGS", Field, 7, ""}, {"Package.CgoFiles", Field, 0, ""}, {"Package.CgoLDFLAGS", Field, 0, ""}, {"Package.CgoPkgConfig", Field, 0, ""}, {"Package.ConflictDir", Field, 2, ""}, {"Package.Dir", Field, 0, ""}, {"Package.Directives", Field, 21, ""}, {"Package.Doc", Field, 0, ""}, {"Package.EmbedPatternPos", Field, 16, ""}, {"Package.EmbedPatterns", Field, 16, ""}, {"Package.FFiles", Field, 7, ""}, {"Package.GoFiles", Field, 0, ""}, {"Package.Goroot", Field, 0, ""}, {"Package.HFiles", Field, 0, ""}, {"Package.IgnoredGoFiles", Field, 1, ""}, {"Package.IgnoredOtherFiles", Field, 16, ""}, {"Package.ImportComment", Field, 4, ""}, {"Package.ImportPath", Field, 0, ""}, {"Package.ImportPos", Field, 0, ""}, {"Package.Imports", Field, 0, ""}, {"Package.InvalidGoFiles", Field, 6, ""}, {"Package.MFiles", Field, 3, ""}, {"Package.Name", Field, 0, ""}, {"Package.PkgObj", Field, 0, ""}, {"Package.PkgRoot", Field, 0, ""}, {"Package.PkgTargetRoot", Field, 5, ""}, {"Package.Root", Field, 0, ""}, {"Package.SFiles", Field, 0, ""}, {"Package.SrcRoot", Field, 0, ""}, {"Package.SwigCXXFiles", Field, 1, ""}, {"Package.SwigFiles", Field, 1, ""}, {"Package.SysoFiles", Field, 0, ""}, {"Package.TestDirectives", Field, 21, ""}, {"Package.TestEmbedPatternPos", Field, 16, ""}, {"Package.TestEmbedPatterns", Field, 16, ""}, {"Package.TestGoFiles", Field, 0, ""}, {"Package.TestImportPos", Field, 0, ""}, {"Package.TestImports", Field, 0, ""}, {"Package.XTestDirectives", Field, 21, ""}, {"Package.XTestEmbedPatternPos", Field, 16, ""}, {"Package.XTestEmbedPatterns", Field, 16, ""}, {"Package.XTestGoFiles", Field, 0, ""}, {"Package.XTestImportPos", Field, 0, ""}, {"Package.XTestImports", Field, 0, ""}, {"ToolDir", Var, 0, ""}, }, "go/build/constraint": { {"(*AndExpr).Eval", Method, 16, ""}, {"(*AndExpr).String", Method, 16, ""}, {"(*NotExpr).Eval", Method, 16, ""}, {"(*NotExpr).String", Method, 16, ""}, {"(*OrExpr).Eval", Method, 16, ""}, {"(*OrExpr).String", Method, 16, ""}, {"(*SyntaxError).Error", Method, 16, ""}, {"(*TagExpr).Eval", Method, 16, ""}, {"(*TagExpr).String", Method, 16, ""}, {"AndExpr", Type, 16, ""}, {"AndExpr.X", Field, 16, ""}, {"AndExpr.Y", Field, 16, ""}, {"Expr", Type, 16, ""}, {"GoVersion", Func, 21, "func(x Expr) string"}, {"IsGoBuild", Func, 16, "func(line string) bool"}, {"IsPlusBuild", Func, 16, "func(line string) bool"}, {"NotExpr", Type, 16, ""}, {"NotExpr.X", Field, 16, ""}, {"OrExpr", Type, 16, ""}, {"OrExpr.X", Field, 16, ""}, {"OrExpr.Y", Field, 16, ""}, {"Parse", Func, 16, "func(line string) (Expr, error)"}, {"PlusBuildLines", Func, 16, "func(x Expr) ([]string, error)"}, {"SyntaxError", Type, 16, ""}, {"SyntaxError.Err", Field, 16, ""}, {"SyntaxError.Offset", Field, 16, ""}, {"TagExpr", Type, 16, ""}, {"TagExpr.Tag", Field, 16, ""}, }, "go/constant": { {"(Kind).String", Method, 18, ""}, {"BinaryOp", Func, 5, "func(x_ Value, op token.Token, y_ Value) Value"}, {"BitLen", Func, 5, "func(x Value) int"}, {"Bool", Const, 5, ""}, {"BoolVal", Func, 5, "func(x Value) bool"}, {"Bytes", Func, 5, "func(x Value) []byte"}, {"Compare", Func, 5, "func(x_ Value, op token.Token, y_ Value) bool"}, {"Complex", Const, 5, ""}, {"Denom", Func, 5, "func(x Value) Value"}, {"Float", Const, 5, ""}, {"Float32Val", Func, 5, "func(x Value) (float32, bool)"}, {"Float64Val", Func, 5, "func(x Value) (float64, bool)"}, {"Imag", Func, 5, "func(x Value) Value"}, {"Int", Const, 5, ""}, {"Int64Val", Func, 5, "func(x Value) (int64, bool)"}, {"Kind", Type, 5, ""}, {"Make", Func, 13, "func(x any) Value"}, {"MakeBool", Func, 5, "func(b bool) Value"}, {"MakeFloat64", Func, 5, "func(x float64) Value"}, {"MakeFromBytes", Func, 5, "func(bytes []byte) Value"}, {"MakeFromLiteral", Func, 5, "func(lit string, tok token.Token, zero uint) Value"}, {"MakeImag", Func, 5, "func(x Value) Value"}, {"MakeInt64", Func, 5, "func(x int64) Value"}, {"MakeString", Func, 5, "func(s string) Value"}, {"MakeUint64", Func, 5, "func(x uint64) Value"}, {"MakeUnknown", Func, 5, "func() Value"}, {"Num", Func, 5, "func(x Value) Value"}, {"Real", Func, 5, "func(x Value) Value"}, {"Shift", Func, 5, "func(x Value, op token.Token, s uint) Value"}, {"Sign", Func, 5, "func(x Value) int"}, {"String", Const, 5, ""}, {"StringVal", Func, 5, "func(x Value) string"}, {"ToComplex", Func, 6, "func(x Value) Value"}, {"ToFloat", Func, 6, "func(x Value) Value"}, {"ToInt", Func, 6, "func(x Value) Value"}, {"Uint64Val", Func, 5, "func(x Value) (uint64, bool)"}, {"UnaryOp", Func, 5, "func(op token.Token, y Value, prec uint) Value"}, {"Unknown", Const, 5, ""}, {"Val", Func, 13, "func(x Value) any"}, {"Value", Type, 5, ""}, }, "go/doc": { {"(*Package).Filter", Method, 0, ""}, {"(*Package).HTML", Method, 19, ""}, {"(*Package).Markdown", Method, 19, ""}, {"(*Package).Parser", Method, 19, ""}, {"(*Package).Printer", Method, 19, ""}, {"(*Package).Synopsis", Method, 19, ""}, {"(*Package).Text", Method, 19, ""}, {"AllDecls", Const, 0, ""}, {"AllMethods", Const, 0, ""}, {"Example", Type, 0, ""}, {"Example.Code", Field, 0, ""}, {"Example.Comments", Field, 0, ""}, {"Example.Doc", Field, 0, ""}, {"Example.EmptyOutput", Field, 1, ""}, {"Example.Name", Field, 0, ""}, {"Example.Order", Field, 1, ""}, {"Example.Output", Field, 0, ""}, {"Example.Play", Field, 1, ""}, {"Example.Suffix", Field, 14, ""}, {"Example.Unordered", Field, 7, ""}, {"Examples", Func, 0, "func(testFiles ...*ast.File) []*Example"}, {"Filter", Type, 0, ""}, {"Func", Type, 0, ""}, {"Func.Decl", Field, 0, ""}, {"Func.Doc", Field, 0, ""}, {"Func.Examples", Field, 14, ""}, {"Func.Level", Field, 0, ""}, {"Func.Name", Field, 0, ""}, {"Func.Orig", Field, 0, ""}, {"Func.Recv", Field, 0, ""}, {"IllegalPrefixes", Var, 1, ""}, {"IsPredeclared", Func, 8, "func(s string) bool"}, {"Mode", Type, 0, ""}, {"New", Func, 0, "func(pkg *ast.Package, importPath string, mode Mode) *Package"}, {"NewFromFiles", Func, 14, "func(fset *token.FileSet, files []*ast.File, importPath string, opts ...any) (*Package, error)"}, {"Note", Type, 1, ""}, {"Note.Body", Field, 1, ""}, {"Note.End", Field, 1, ""}, {"Note.Pos", Field, 1, ""}, {"Note.UID", Field, 1, ""}, {"Package", Type, 0, ""}, {"Package.Bugs", Field, 0, ""}, {"Package.Consts", Field, 0, ""}, {"Package.Doc", Field, 0, ""}, {"Package.Examples", Field, 14, ""}, {"Package.Filenames", Field, 0, ""}, {"Package.Funcs", Field, 0, ""}, {"Package.ImportPath", Field, 0, ""}, {"Package.Imports", Field, 0, ""}, {"Package.Name", Field, 0, ""}, {"Package.Notes", Field, 1, ""}, {"Package.Types", Field, 0, ""}, {"Package.Vars", Field, 0, ""}, {"PreserveAST", Const, 12, ""}, {"Synopsis", Func, 0, "func(text string) string"}, {"ToHTML", Func, 0, "func(w io.Writer, text string, words map[string]string)"}, {"ToText", Func, 0, "func(w io.Writer, text string, prefix string, codePrefix string, width int)"}, {"Type", Type, 0, ""}, {"Type.Consts", Field, 0, ""}, {"Type.Decl", Field, 0, ""}, {"Type.Doc", Field, 0, ""}, {"Type.Examples", Field, 14, ""}, {"Type.Funcs", Field, 0, ""}, {"Type.Methods", Field, 0, ""}, {"Type.Name", Field, 0, ""}, {"Type.Vars", Field, 0, ""}, {"Value", Type, 0, ""}, {"Value.Decl", Field, 0, ""}, {"Value.Doc", Field, 0, ""}, {"Value.Names", Field, 0, ""}, }, "go/doc/comment": { {"(*DocLink).DefaultURL", Method, 19, ""}, {"(*Heading).DefaultID", Method, 19, ""}, {"(*List).BlankBefore", Method, 19, ""}, {"(*List).BlankBetween", Method, 19, ""}, {"(*Parser).Parse", Method, 19, ""}, {"(*Printer).Comment", Method, 19, ""}, {"(*Printer).HTML", Method, 19, ""}, {"(*Printer).Markdown", Method, 19, ""}, {"(*Printer).Text", Method, 19, ""}, {"Block", Type, 19, ""}, {"Code", Type, 19, ""}, {"Code.Text", Field, 19, ""}, {"DefaultLookupPackage", Func, 19, "func(name string) (importPath string, ok bool)"}, {"Doc", Type, 19, ""}, {"Doc.Content", Field, 19, ""}, {"Doc.Links", Field, 19, ""}, {"DocLink", Type, 19, ""}, {"DocLink.ImportPath", Field, 19, ""}, {"DocLink.Name", Field, 19, ""}, {"DocLink.Recv", Field, 19, ""}, {"DocLink.Text", Field, 19, ""}, {"Heading", Type, 19, ""}, {"Heading.Text", Field, 19, ""}, {"Italic", Type, 19, ""}, {"Link", Type, 19, ""}, {"Link.Auto", Field, 19, ""}, {"Link.Text", Field, 19, ""}, {"Link.URL", Field, 19, ""}, {"LinkDef", Type, 19, ""}, {"LinkDef.Text", Field, 19, ""}, {"LinkDef.URL", Field, 19, ""}, {"LinkDef.Used", Field, 19, ""}, {"List", Type, 19, ""}, {"List.ForceBlankBefore", Field, 19, ""}, {"List.ForceBlankBetween", Field, 19, ""}, {"List.Items", Field, 19, ""}, {"ListItem", Type, 19, ""}, {"ListItem.Content", Field, 19, ""}, {"ListItem.Number", Field, 19, ""}, {"Paragraph", Type, 19, ""}, {"Paragraph.Text", Field, 19, ""}, {"Parser", Type, 19, ""}, {"Parser.LookupPackage", Field, 19, ""}, {"Parser.LookupSym", Field, 19, ""}, {"Parser.Words", Field, 19, ""}, {"Plain", Type, 19, ""}, {"Printer", Type, 19, ""}, {"Printer.DocLinkBaseURL", Field, 19, ""}, {"Printer.DocLinkURL", Field, 19, ""}, {"Printer.HeadingID", Field, 19, ""}, {"Printer.HeadingLevel", Field, 19, ""}, {"Printer.TextCodePrefix", Field, 19, ""}, {"Printer.TextPrefix", Field, 19, ""}, {"Printer.TextWidth", Field, 19, ""}, {"Text", Type, 19, ""}, }, "go/format": { {"Node", Func, 1, "func(dst io.Writer, fset *token.FileSet, node any) error"}, {"Source", Func, 1, "func(src []byte) ([]byte, error)"}, }, "go/importer": { {"Default", Func, 5, "func() types.Importer"}, {"For", Func, 5, "func(compiler string, lookup Lookup) types.Importer"}, {"ForCompiler", Func, 12, "func(fset *token.FileSet, compiler string, lookup Lookup) types.Importer"}, {"Lookup", Type, 5, ""}, }, "go/parser": { {"AllErrors", Const, 1, ""}, {"DeclarationErrors", Const, 0, ""}, {"ImportsOnly", Const, 0, ""}, {"Mode", Type, 0, ""}, {"PackageClauseOnly", Const, 0, ""}, {"ParseComments", Const, 0, ""}, {"ParseDir", Func, 0, "func(fset *token.FileSet, path string, filter func(fs.FileInfo) bool, mode Mode) (pkgs map[string]*ast.Package, first error)"}, {"ParseExpr", Func, 0, "func(x string) (ast.Expr, error)"}, {"ParseExprFrom", Func, 5, "func(fset *token.FileSet, filename string, src any, mode Mode) (expr ast.Expr, err error)"}, {"ParseFile", Func, 0, "func(fset *token.FileSet, filename string, src any, mode Mode) (f *ast.File, err error)"}, {"SkipObjectResolution", Const, 17, ""}, {"SpuriousErrors", Const, 0, ""}, {"Trace", Const, 0, ""}, }, "go/printer": { {"(*Config).Fprint", Method, 0, ""}, {"CommentedNode", Type, 0, ""}, {"CommentedNode.Comments", Field, 0, ""}, {"CommentedNode.Node", Field, 0, ""}, {"Config", Type, 0, ""}, {"Config.Indent", Field, 1, ""}, {"Config.Mode", Field, 0, ""}, {"Config.Tabwidth", Field, 0, ""}, {"Fprint", Func, 0, "func(output io.Writer, fset *token.FileSet, node any) error"}, {"Mode", Type, 0, ""}, {"RawFormat", Const, 0, ""}, {"SourcePos", Const, 0, ""}, {"TabIndent", Const, 0, ""}, {"UseSpaces", Const, 0, ""}, }, "go/scanner": { {"(*ErrorList).Add", Method, 0, ""}, {"(*ErrorList).RemoveMultiples", Method, 0, ""}, {"(*ErrorList).Reset", Method, 0, ""}, {"(*Scanner).Init", Method, 0, ""}, {"(*Scanner).Scan", Method, 0, ""}, {"(Error).Error", Method, 0, ""}, {"(ErrorList).Err", Method, 0, ""}, {"(ErrorList).Error", Method, 0, ""}, {"(ErrorList).Len", Method, 0, ""}, {"(ErrorList).Less", Method, 0, ""}, {"(ErrorList).Sort", Method, 0, ""}, {"(ErrorList).Swap", Method, 0, ""}, {"Error", Type, 0, ""}, {"Error.Msg", Field, 0, ""}, {"Error.Pos", Field, 0, ""}, {"ErrorHandler", Type, 0, ""}, {"ErrorList", Type, 0, ""}, {"Mode", Type, 0, ""}, {"PrintError", Func, 0, "func(w io.Writer, err error)"}, {"ScanComments", Const, 0, ""}, {"Scanner", Type, 0, ""}, {"Scanner.ErrorCount", Field, 0, ""}, }, "go/token": { {"(*File).AddLine", Method, 0, ""}, {"(*File).AddLineColumnInfo", Method, 11, ""}, {"(*File).AddLineInfo", Method, 0, ""}, {"(*File).Base", Method, 0, ""}, {"(*File).Line", Method, 0, ""}, {"(*File).LineCount", Method, 0, ""}, {"(*File).LineStart", Method, 12, ""}, {"(*File).Lines", Method, 21, ""}, {"(*File).MergeLine", Method, 2, ""}, {"(*File).Name", Method, 0, ""}, {"(*File).Offset", Method, 0, ""}, {"(*File).Pos", Method, 0, ""}, {"(*File).Position", Method, 0, ""}, {"(*File).PositionFor", Method, 4, ""}, {"(*File).SetLines", Method, 0, ""}, {"(*File).SetLinesForContent", Method, 0, ""}, {"(*File).Size", Method, 0, ""}, {"(*FileSet).AddFile", Method, 0, ""}, {"(*FileSet).Base", Method, 0, ""}, {"(*FileSet).File", Method, 0, ""}, {"(*FileSet).Iterate", Method, 0, ""}, {"(*FileSet).Position", Method, 0, ""}, {"(*FileSet).PositionFor", Method, 4, ""}, {"(*FileSet).Read", Method, 0, ""}, {"(*FileSet).RemoveFile", Method, 20, ""}, {"(*FileSet).Write", Method, 0, ""}, {"(*Position).IsValid", Method, 0, ""}, {"(Pos).IsValid", Method, 0, ""}, {"(Position).String", Method, 0, ""}, {"(Token).IsKeyword", Method, 0, ""}, {"(Token).IsLiteral", Method, 0, ""}, {"(Token).IsOperator", Method, 0, ""}, {"(Token).Precedence", Method, 0, ""}, {"(Token).String", Method, 0, ""}, {"ADD", Const, 0, ""}, {"ADD_ASSIGN", Const, 0, ""}, {"AND", Const, 0, ""}, {"AND_ASSIGN", Const, 0, ""}, {"AND_NOT", Const, 0, ""}, {"AND_NOT_ASSIGN", Const, 0, ""}, {"ARROW", Const, 0, ""}, {"ASSIGN", Const, 0, ""}, {"BREAK", Const, 0, ""}, {"CASE", Const, 0, ""}, {"CHAN", Const, 0, ""}, {"CHAR", Const, 0, ""}, {"COLON", Const, 0, ""}, {"COMMA", Const, 0, ""}, {"COMMENT", Const, 0, ""}, {"CONST", Const, 0, ""}, {"CONTINUE", Const, 0, ""}, {"DEC", Const, 0, ""}, {"DEFAULT", Const, 0, ""}, {"DEFER", Const, 0, ""}, {"DEFINE", Const, 0, ""}, {"ELLIPSIS", Const, 0, ""}, {"ELSE", Const, 0, ""}, {"EOF", Const, 0, ""}, {"EQL", Const, 0, ""}, {"FALLTHROUGH", Const, 0, ""}, {"FLOAT", Const, 0, ""}, {"FOR", Const, 0, ""}, {"FUNC", Const, 0, ""}, {"File", Type, 0, ""}, {"FileSet", Type, 0, ""}, {"GEQ", Const, 0, ""}, {"GO", Const, 0, ""}, {"GOTO", Const, 0, ""}, {"GTR", Const, 0, ""}, {"HighestPrec", Const, 0, ""}, {"IDENT", Const, 0, ""}, {"IF", Const, 0, ""}, {"ILLEGAL", Const, 0, ""}, {"IMAG", Const, 0, ""}, {"IMPORT", Const, 0, ""}, {"INC", Const, 0, ""}, {"INT", Const, 0, ""}, {"INTERFACE", Const, 0, ""}, {"IsExported", Func, 13, "func(name string) bool"}, {"IsIdentifier", Func, 13, "func(name string) bool"}, {"IsKeyword", Func, 13, "func(name string) bool"}, {"LAND", Const, 0, ""}, {"LBRACE", Const, 0, ""}, {"LBRACK", Const, 0, ""}, {"LEQ", Const, 0, ""}, {"LOR", Const, 0, ""}, {"LPAREN", Const, 0, ""}, {"LSS", Const, 0, ""}, {"Lookup", Func, 0, "func(ident string) Token"}, {"LowestPrec", Const, 0, ""}, {"MAP", Const, 0, ""}, {"MUL", Const, 0, ""}, {"MUL_ASSIGN", Const, 0, ""}, {"NEQ", Const, 0, ""}, {"NOT", Const, 0, ""}, {"NewFileSet", Func, 0, "func() *FileSet"}, {"NoPos", Const, 0, ""}, {"OR", Const, 0, ""}, {"OR_ASSIGN", Const, 0, ""}, {"PACKAGE", Const, 0, ""}, {"PERIOD", Const, 0, ""}, {"Pos", Type, 0, ""}, {"Position", Type, 0, ""}, {"Position.Column", Field, 0, ""}, {"Position.Filename", Field, 0, ""}, {"Position.Line", Field, 0, ""}, {"Position.Offset", Field, 0, ""}, {"QUO", Const, 0, ""}, {"QUO_ASSIGN", Const, 0, ""}, {"RANGE", Const, 0, ""}, {"RBRACE", Const, 0, ""}, {"RBRACK", Const, 0, ""}, {"REM", Const, 0, ""}, {"REM_ASSIGN", Const, 0, ""}, {"RETURN", Const, 0, ""}, {"RPAREN", Const, 0, ""}, {"SELECT", Const, 0, ""}, {"SEMICOLON", Const, 0, ""}, {"SHL", Const, 0, ""}, {"SHL_ASSIGN", Const, 0, ""}, {"SHR", Const, 0, ""}, {"SHR_ASSIGN", Const, 0, ""}, {"STRING", Const, 0, ""}, {"STRUCT", Const, 0, ""}, {"SUB", Const, 0, ""}, {"SUB_ASSIGN", Const, 0, ""}, {"SWITCH", Const, 0, ""}, {"TILDE", Const, 18, ""}, {"TYPE", Const, 0, ""}, {"Token", Type, 0, ""}, {"UnaryPrec", Const, 0, ""}, {"VAR", Const, 0, ""}, {"XOR", Const, 0, ""}, {"XOR_ASSIGN", Const, 0, ""}, }, "go/types": { {"(*Alias).Obj", Method, 22, ""}, {"(*Alias).Origin", Method, 23, ""}, {"(*Alias).Rhs", Method, 23, ""}, {"(*Alias).SetTypeParams", Method, 23, ""}, {"(*Alias).String", Method, 22, ""}, {"(*Alias).TypeArgs", Method, 23, ""}, {"(*Alias).TypeParams", Method, 23, ""}, {"(*Alias).Underlying", Method, 22, ""}, {"(*ArgumentError).Error", Method, 18, ""}, {"(*ArgumentError).Unwrap", Method, 18, ""}, {"(*Array).Elem", Method, 5, ""}, {"(*Array).Len", Method, 5, ""}, {"(*Array).String", Method, 5, ""}, {"(*Array).Underlying", Method, 5, ""}, {"(*Basic).Info", Method, 5, ""}, {"(*Basic).Kind", Method, 5, ""}, {"(*Basic).Name", Method, 5, ""}, {"(*Basic).String", Method, 5, ""}, {"(*Basic).Underlying", Method, 5, ""}, {"(*Builtin).Exported", Method, 5, ""}, {"(*Builtin).Id", Method, 5, ""}, {"(*Builtin).Name", Method, 5, ""}, {"(*Builtin).Parent", Method, 5, ""}, {"(*Builtin).Pkg", Method, 5, ""}, {"(*Builtin).Pos", Method, 5, ""}, {"(*Builtin).String", Method, 5, ""}, {"(*Builtin).Type", Method, 5, ""}, {"(*Chan).Dir", Method, 5, ""}, {"(*Chan).Elem", Method, 5, ""}, {"(*Chan).String", Method, 5, ""}, {"(*Chan).Underlying", Method, 5, ""}, {"(*Checker).Files", Method, 5, ""}, {"(*Config).Check", Method, 5, ""}, {"(*Const).Exported", Method, 5, ""}, {"(*Const).Id", Method, 5, ""}, {"(*Const).Name", Method, 5, ""}, {"(*Const).Parent", Method, 5, ""}, {"(*Const).Pkg", Method, 5, ""}, {"(*Const).Pos", Method, 5, ""}, {"(*Const).String", Method, 5, ""}, {"(*Const).Type", Method, 5, ""}, {"(*Const).Val", Method, 5, ""}, {"(*Func).Exported", Method, 5, ""}, {"(*Func).FullName", Method, 5, ""}, {"(*Func).Id", Method, 5, ""}, {"(*Func).Name", Method, 5, ""}, {"(*Func).Origin", Method, 19, ""}, {"(*Func).Parent", Method, 5, ""}, {"(*Func).Pkg", Method, 5, ""}, {"(*Func).Pos", Method, 5, ""}, {"(*Func).Scope", Method, 5, ""}, {"(*Func).Signature", Method, 23, ""}, {"(*Func).String", Method, 5, ""}, {"(*Func).Type", Method, 5, ""}, {"(*Info).ObjectOf", Method, 5, ""}, {"(*Info).PkgNameOf", Method, 22, ""}, {"(*Info).TypeOf", Method, 5, ""}, {"(*Initializer).String", Method, 5, ""}, {"(*Interface).Complete", Method, 5, ""}, {"(*Interface).Embedded", Method, 5, ""}, {"(*Interface).EmbeddedType", Method, 11, ""}, {"(*Interface).EmbeddedTypes", Method, 24, ""}, {"(*Interface).Empty", Method, 5, ""}, {"(*Interface).ExplicitMethod", Method, 5, ""}, {"(*Interface).ExplicitMethods", Method, 24, ""}, {"(*Interface).IsComparable", Method, 18, ""}, {"(*Interface).IsImplicit", Method, 18, ""}, {"(*Interface).IsMethodSet", Method, 18, ""}, {"(*Interface).MarkImplicit", Method, 18, ""}, {"(*Interface).Method", Method, 5, ""}, {"(*Interface).Methods", Method, 24, ""}, {"(*Interface).NumEmbeddeds", Method, 5, ""}, {"(*Interface).NumExplicitMethods", Method, 5, ""}, {"(*Interface).NumMethods", Method, 5, ""}, {"(*Interface).String", Method, 5, ""}, {"(*Interface).Underlying", Method, 5, ""}, {"(*Label).Exported", Method, 5, ""}, {"(*Label).Id", Method, 5, ""}, {"(*Label).Name", Method, 5, ""}, {"(*Label).Parent", Method, 5, ""}, {"(*Label).Pkg", Method, 5, ""}, {"(*Label).Pos", Method, 5, ""}, {"(*Label).String", Method, 5, ""}, {"(*Label).Type", Method, 5, ""}, {"(*Map).Elem", Method, 5, ""}, {"(*Map).Key", Method, 5, ""}, {"(*Map).String", Method, 5, ""}, {"(*Map).Underlying", Method, 5, ""}, {"(*MethodSet).At", Method, 5, ""}, {"(*MethodSet).Len", Method, 5, ""}, {"(*MethodSet).Lookup", Method, 5, ""}, {"(*MethodSet).Methods", Method, 24, ""}, {"(*MethodSet).String", Method, 5, ""}, {"(*Named).AddMethod", Method, 5, ""}, {"(*Named).Method", Method, 5, ""}, {"(*Named).Methods", Method, 24, ""}, {"(*Named).NumMethods", Method, 5, ""}, {"(*Named).Obj", Method, 5, ""}, {"(*Named).Origin", Method, 18, ""}, {"(*Named).SetTypeParams", Method, 18, ""}, {"(*Named).SetUnderlying", Method, 5, ""}, {"(*Named).String", Method, 5, ""}, {"(*Named).TypeArgs", Method, 18, ""}, {"(*Named).TypeParams", Method, 18, ""}, {"(*Named).Underlying", Method, 5, ""}, {"(*Nil).Exported", Method, 5, ""}, {"(*Nil).Id", Method, 5, ""}, {"(*Nil).Name", Method, 5, ""}, {"(*Nil).Parent", Method, 5, ""}, {"(*Nil).Pkg", Method, 5, ""}, {"(*Nil).Pos", Method, 5, ""}, {"(*Nil).String", Method, 5, ""}, {"(*Nil).Type", Method, 5, ""}, {"(*Package).Complete", Method, 5, ""}, {"(*Package).GoVersion", Method, 21, ""}, {"(*Package).Imports", Method, 5, ""}, {"(*Package).MarkComplete", Method, 5, ""}, {"(*Package).Name", Method, 5, ""}, {"(*Package).Path", Method, 5, ""}, {"(*Package).Scope", Method, 5, ""}, {"(*Package).SetImports", Method, 5, ""}, {"(*Package).SetName", Method, 6, ""}, {"(*Package).String", Method, 5, ""}, {"(*PkgName).Exported", Method, 5, ""}, {"(*PkgName).Id", Method, 5, ""}, {"(*PkgName).Imported", Method, 5, ""}, {"(*PkgName).Name", Method, 5, ""}, {"(*PkgName).Parent", Method, 5, ""}, {"(*PkgName).Pkg", Method, 5, ""}, {"(*PkgName).Pos", Method, 5, ""}, {"(*PkgName).String", Method, 5, ""}, {"(*PkgName).Type", Method, 5, ""}, {"(*Pointer).Elem", Method, 5, ""}, {"(*Pointer).String", Method, 5, ""}, {"(*Pointer).Underlying", Method, 5, ""}, {"(*Scope).Child", Method, 5, ""}, {"(*Scope).Children", Method, 24, ""}, {"(*Scope).Contains", Method, 5, ""}, {"(*Scope).End", Method, 5, ""}, {"(*Scope).Innermost", Method, 5, ""}, {"(*Scope).Insert", Method, 5, ""}, {"(*Scope).Len", Method, 5, ""}, {"(*Scope).Lookup", Method, 5, ""}, {"(*Scope).LookupParent", Method, 5, ""}, {"(*Scope).Names", Method, 5, ""}, {"(*Scope).NumChildren", Method, 5, ""}, {"(*Scope).Parent", Method, 5, ""}, {"(*Scope).Pos", Method, 5, ""}, {"(*Scope).String", Method, 5, ""}, {"(*Scope).WriteTo", Method, 5, ""}, {"(*Selection).Index", Method, 5, ""}, {"(*Selection).Indirect", Method, 5, ""}, {"(*Selection).Kind", Method, 5, ""}, {"(*Selection).Obj", Method, 5, ""}, {"(*Selection).Recv", Method, 5, ""}, {"(*Selection).String", Method, 5, ""}, {"(*Selection).Type", Method, 5, ""}, {"(*Signature).Params", Method, 5, ""}, {"(*Signature).Recv", Method, 5, ""}, {"(*Signature).RecvTypeParams", Method, 18, ""}, {"(*Signature).Results", Method, 5, ""}, {"(*Signature).String", Method, 5, ""}, {"(*Signature).TypeParams", Method, 18, ""}, {"(*Signature).Underlying", Method, 5, ""}, {"(*Signature).Variadic", Method, 5, ""}, {"(*Slice).Elem", Method, 5, ""}, {"(*Slice).String", Method, 5, ""}, {"(*Slice).Underlying", Method, 5, ""}, {"(*StdSizes).Alignof", Method, 5, ""}, {"(*StdSizes).Offsetsof", Method, 5, ""}, {"(*StdSizes).Sizeof", Method, 5, ""}, {"(*Struct).Field", Method, 5, ""}, {"(*Struct).Fields", Method, 24, ""}, {"(*Struct).NumFields", Method, 5, ""}, {"(*Struct).String", Method, 5, ""}, {"(*Struct).Tag", Method, 5, ""}, {"(*Struct).Underlying", Method, 5, ""}, {"(*Term).String", Method, 18, ""}, {"(*Term).Tilde", Method, 18, ""}, {"(*Term).Type", Method, 18, ""}, {"(*Tuple).At", Method, 5, ""}, {"(*Tuple).Len", Method, 5, ""}, {"(*Tuple).String", Method, 5, ""}, {"(*Tuple).Underlying", Method, 5, ""}, {"(*Tuple).Variables", Method, 24, ""}, {"(*TypeList).At", Method, 18, ""}, {"(*TypeList).Len", Method, 18, ""}, {"(*TypeList).Types", Method, 24, ""}, {"(*TypeName).Exported", Method, 5, ""}, {"(*TypeName).Id", Method, 5, ""}, {"(*TypeName).IsAlias", Method, 9, ""}, {"(*TypeName).Name", Method, 5, ""}, {"(*TypeName).Parent", Method, 5, ""}, {"(*TypeName).Pkg", Method, 5, ""}, {"(*TypeName).Pos", Method, 5, ""}, {"(*TypeName).String", Method, 5, ""}, {"(*TypeName).Type", Method, 5, ""}, {"(*TypeParam).Constraint", Method, 18, ""}, {"(*TypeParam).Index", Method, 18, ""}, {"(*TypeParam).Obj", Method, 18, ""}, {"(*TypeParam).SetConstraint", Method, 18, ""}, {"(*TypeParam).String", Method, 18, ""}, {"(*TypeParam).Underlying", Method, 18, ""}, {"(*TypeParamList).At", Method, 18, ""}, {"(*TypeParamList).Len", Method, 18, ""}, {"(*TypeParamList).TypeParams", Method, 24, ""}, {"(*Union).Len", Method, 18, ""}, {"(*Union).String", Method, 18, ""}, {"(*Union).Term", Method, 18, ""}, {"(*Union).Terms", Method, 24, ""}, {"(*Union).Underlying", Method, 18, ""}, {"(*Var).Anonymous", Method, 5, ""}, {"(*Var).Embedded", Method, 11, ""}, {"(*Var).Exported", Method, 5, ""}, {"(*Var).Id", Method, 5, ""}, {"(*Var).IsField", Method, 5, ""}, {"(*Var).Kind", Method, 25, ""}, {"(*Var).Name", Method, 5, ""}, {"(*Var).Origin", Method, 19, ""}, {"(*Var).Parent", Method, 5, ""}, {"(*Var).Pkg", Method, 5, ""}, {"(*Var).Pos", Method, 5, ""}, {"(*Var).SetKind", Method, 25, ""}, {"(*Var).String", Method, 5, ""}, {"(*Var).Type", Method, 5, ""}, {"(Checker).ObjectOf", Method, 5, ""}, {"(Checker).PkgNameOf", Method, 22, ""}, {"(Checker).TypeOf", Method, 5, ""}, {"(Error).Error", Method, 5, ""}, {"(TypeAndValue).Addressable", Method, 5, ""}, {"(TypeAndValue).Assignable", Method, 5, ""}, {"(TypeAndValue).HasOk", Method, 5, ""}, {"(TypeAndValue).IsBuiltin", Method, 5, ""}, {"(TypeAndValue).IsNil", Method, 5, ""}, {"(TypeAndValue).IsType", Method, 5, ""}, {"(TypeAndValue).IsValue", Method, 5, ""}, {"(TypeAndValue).IsVoid", Method, 5, ""}, {"(VarKind).String", Method, 25, ""}, {"Alias", Type, 22, ""}, {"ArgumentError", Type, 18, ""}, {"ArgumentError.Err", Field, 18, ""}, {"ArgumentError.Index", Field, 18, ""}, {"Array", Type, 5, ""}, {"AssertableTo", Func, 5, "func(V *Interface, T Type) bool"}, {"AssignableTo", Func, 5, "func(V Type, T Type) bool"}, {"Basic", Type, 5, ""}, {"BasicInfo", Type, 5, ""}, {"BasicKind", Type, 5, ""}, {"Bool", Const, 5, ""}, {"Builtin", Type, 5, ""}, {"Byte", Const, 5, ""}, {"Chan", Type, 5, ""}, {"ChanDir", Type, 5, ""}, {"CheckExpr", Func, 13, "func(fset *token.FileSet, pkg *Package, pos token.Pos, expr ast.Expr, info *Info) (err error)"}, {"Checker", Type, 5, ""}, {"Checker.Info", Field, 5, ""}, {"Comparable", Func, 5, "func(T Type) bool"}, {"Complex128", Const, 5, ""}, {"Complex64", Const, 5, ""}, {"Config", Type, 5, ""}, {"Config.Context", Field, 18, ""}, {"Config.DisableUnusedImportCheck", Field, 5, ""}, {"Config.Error", Field, 5, ""}, {"Config.FakeImportC", Field, 5, ""}, {"Config.GoVersion", Field, 18, ""}, {"Config.IgnoreFuncBodies", Field, 5, ""}, {"Config.Importer", Field, 5, ""}, {"Config.Sizes", Field, 5, ""}, {"Const", Type, 5, ""}, {"Context", Type, 18, ""}, {"ConvertibleTo", Func, 5, "func(V Type, T Type) bool"}, {"DefPredeclaredTestFuncs", Func, 5, "func()"}, {"Default", Func, 8, "func(t Type) Type"}, {"Error", Type, 5, ""}, {"Error.Fset", Field, 5, ""}, {"Error.Msg", Field, 5, ""}, {"Error.Pos", Field, 5, ""}, {"Error.Soft", Field, 5, ""}, {"Eval", Func, 5, "func(fset *token.FileSet, pkg *Package, pos token.Pos, expr string) (_ TypeAndValue, err error)"}, {"ExprString", Func, 5, "func(x ast.Expr) string"}, {"FieldVal", Const, 5, ""}, {"FieldVar", Const, 25, ""}, {"Float32", Const, 5, ""}, {"Float64", Const, 5, ""}, {"Func", Type, 5, ""}, {"Id", Func, 5, "func(pkg *Package, name string) string"}, {"Identical", Func, 5, "func(x Type, y Type) bool"}, {"IdenticalIgnoreTags", Func, 8, "func(x Type, y Type) bool"}, {"Implements", Func, 5, "func(V Type, T *Interface) bool"}, {"ImportMode", Type, 6, ""}, {"Importer", Type, 5, ""}, {"ImporterFrom", Type, 6, ""}, {"Info", Type, 5, ""}, {"Info.Defs", Field, 5, ""}, {"Info.FileVersions", Field, 22, ""}, {"Info.Implicits", Field, 5, ""}, {"Info.InitOrder", Field, 5, ""}, {"Info.Instances", Field, 18, ""}, {"Info.Scopes", Field, 5, ""}, {"Info.Selections", Field, 5, ""}, {"Info.Types", Field, 5, ""}, {"Info.Uses", Field, 5, ""}, {"Initializer", Type, 5, ""}, {"Initializer.Lhs", Field, 5, ""}, {"Initializer.Rhs", Field, 5, ""}, {"Instance", Type, 18, ""}, {"Instance.Type", Field, 18, ""}, {"Instance.TypeArgs", Field, 18, ""}, {"Instantiate", Func, 18, "func(ctxt *Context, orig Type, targs []Type, validate bool) (Type, error)"}, {"Int", Const, 5, ""}, {"Int16", Const, 5, ""}, {"Int32", Const, 5, ""}, {"Int64", Const, 5, ""}, {"Int8", Const, 5, ""}, {"Interface", Type, 5, ""}, {"Invalid", Const, 5, ""}, {"IsBoolean", Const, 5, ""}, {"IsComplex", Const, 5, ""}, {"IsConstType", Const, 5, ""}, {"IsFloat", Const, 5, ""}, {"IsInteger", Const, 5, ""}, {"IsInterface", Func, 5, "func(t Type) bool"}, {"IsNumeric", Const, 5, ""}, {"IsOrdered", Const, 5, ""}, {"IsString", Const, 5, ""}, {"IsUnsigned", Const, 5, ""}, {"IsUntyped", Const, 5, ""}, {"Label", Type, 5, ""}, {"LocalVar", Const, 25, ""}, {"LookupFieldOrMethod", Func, 5, "func(T Type, addressable bool, pkg *Package, name string) (obj Object, index []int, indirect bool)"}, {"LookupSelection", Func, 25, ""}, {"Map", Type, 5, ""}, {"MethodExpr", Const, 5, ""}, {"MethodSet", Type, 5, ""}, {"MethodVal", Const, 5, ""}, {"MissingMethod", Func, 5, "func(V Type, T *Interface, static bool) (method *Func, wrongType bool)"}, {"Named", Type, 5, ""}, {"NewAlias", Func, 22, "func(obj *TypeName, rhs Type) *Alias"}, {"NewArray", Func, 5, "func(elem Type, len int64) *Array"}, {"NewChan", Func, 5, "func(dir ChanDir, elem Type) *Chan"}, {"NewChecker", Func, 5, "func(conf *Config, fset *token.FileSet, pkg *Package, info *Info) *Checker"}, {"NewConst", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type, val constant.Value) *Const"}, {"NewContext", Func, 18, "func() *Context"}, {"NewField", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type, embedded bool) *Var"}, {"NewFunc", Func, 5, "func(pos token.Pos, pkg *Package, name string, sig *Signature) *Func"}, {"NewInterface", Func, 5, "func(methods []*Func, embeddeds []*Named) *Interface"}, {"NewInterfaceType", Func, 11, "func(methods []*Func, embeddeds []Type) *Interface"}, {"NewLabel", Func, 5, "func(pos token.Pos, pkg *Package, name string) *Label"}, {"NewMap", Func, 5, "func(key Type, elem Type) *Map"}, {"NewMethodSet", Func, 5, "func(T Type) *MethodSet"}, {"NewNamed", Func, 5, "func(obj *TypeName, underlying Type, methods []*Func) *Named"}, {"NewPackage", Func, 5, "func(path string, name string) *Package"}, {"NewParam", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type) *Var"}, {"NewPkgName", Func, 5, "func(pos token.Pos, pkg *Package, name string, imported *Package) *PkgName"}, {"NewPointer", Func, 5, "func(elem Type) *Pointer"}, {"NewScope", Func, 5, "func(parent *Scope, pos token.Pos, end token.Pos, comment string) *Scope"}, {"NewSignature", Func, 5, "func(recv *Var, params *Tuple, results *Tuple, variadic bool) *Signature"}, {"NewSignatureType", Func, 18, "func(recv *Var, recvTypeParams []*TypeParam, typeParams []*TypeParam, params *Tuple, results *Tuple, variadic bool) *Signature"}, {"NewSlice", Func, 5, "func(elem Type) *Slice"}, {"NewStruct", Func, 5, "func(fields []*Var, tags []string) *Struct"}, {"NewTerm", Func, 18, "func(tilde bool, typ Type) *Term"}, {"NewTuple", Func, 5, "func(x ...*Var) *Tuple"}, {"NewTypeName", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type) *TypeName"}, {"NewTypeParam", Func, 18, "func(obj *TypeName, constraint Type) *TypeParam"}, {"NewUnion", Func, 18, "func(terms []*Term) *Union"}, {"NewVar", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type) *Var"}, {"Nil", Type, 5, ""}, {"Object", Type, 5, ""}, {"ObjectString", Func, 5, "func(obj Object, qf Qualifier) string"}, {"Package", Type, 5, ""}, {"PackageVar", Const, 25, ""}, {"ParamVar", Const, 25, ""}, {"PkgName", Type, 5, ""}, {"Pointer", Type, 5, ""}, {"Qualifier", Type, 5, ""}, {"RecvOnly", Const, 5, ""}, {"RecvVar", Const, 25, ""}, {"RelativeTo", Func, 5, "func(pkg *Package) Qualifier"}, {"ResultVar", Const, 25, ""}, {"Rune", Const, 5, ""}, {"Satisfies", Func, 20, "func(V Type, T *Interface) bool"}, {"Scope", Type, 5, ""}, {"Selection", Type, 5, ""}, {"SelectionKind", Type, 5, ""}, {"SelectionString", Func, 5, "func(s *Selection, qf Qualifier) string"}, {"SendOnly", Const, 5, ""}, {"SendRecv", Const, 5, ""}, {"Signature", Type, 5, ""}, {"Sizes", Type, 5, ""}, {"SizesFor", Func, 9, "func(compiler string, arch string) Sizes"}, {"Slice", Type, 5, ""}, {"StdSizes", Type, 5, ""}, {"StdSizes.MaxAlign", Field, 5, ""}, {"StdSizes.WordSize", Field, 5, ""}, {"String", Const, 5, ""}, {"Struct", Type, 5, ""}, {"Term", Type, 18, ""}, {"Tuple", Type, 5, ""}, {"Typ", Var, 5, ""}, {"Type", Type, 5, ""}, {"TypeAndValue", Type, 5, ""}, {"TypeAndValue.Type", Field, 5, ""}, {"TypeAndValue.Value", Field, 5, ""}, {"TypeList", Type, 18, ""}, {"TypeName", Type, 5, ""}, {"TypeParam", Type, 18, ""}, {"TypeParamList", Type, 18, ""}, {"TypeString", Func, 5, "func(typ Type, qf Qualifier) string"}, {"Uint", Const, 5, ""}, {"Uint16", Const, 5, ""}, {"Uint32", Const, 5, ""}, {"Uint64", Const, 5, ""}, {"Uint8", Const, 5, ""}, {"Uintptr", Const, 5, ""}, {"Unalias", Func, 22, "func(t Type) Type"}, {"Union", Type, 18, ""}, {"Universe", Var, 5, ""}, {"Unsafe", Var, 5, ""}, {"UnsafePointer", Const, 5, ""}, {"UntypedBool", Const, 5, ""}, {"UntypedComplex", Const, 5, ""}, {"UntypedFloat", Const, 5, ""}, {"UntypedInt", Const, 5, ""}, {"UntypedNil", Const, 5, ""}, {"UntypedRune", Const, 5, ""}, {"UntypedString", Const, 5, ""}, {"Var", Type, 5, ""}, {"VarKind", Type, 25, ""}, {"WriteExpr", Func, 5, "func(buf *bytes.Buffer, x ast.Expr)"}, {"WriteSignature", Func, 5, "func(buf *bytes.Buffer, sig *Signature, qf Qualifier)"}, {"WriteType", Func, 5, "func(buf *bytes.Buffer, typ Type, qf Qualifier)"}, }, "go/version": { {"Compare", Func, 22, "func(x string, y string) int"}, {"IsValid", Func, 22, "func(x string) bool"}, {"Lang", Func, 22, "func(x string) string"}, }, "hash": { {"Hash", Type, 0, ""}, {"Hash32", Type, 0, ""}, {"Hash64", Type, 0, ""}, }, "hash/adler32": { {"Checksum", Func, 0, "func(data []byte) uint32"}, {"New", Func, 0, "func() hash.Hash32"}, {"Size", Const, 0, ""}, }, "hash/crc32": { {"Castagnoli", Const, 0, ""}, {"Checksum", Func, 0, "func(data []byte, tab *Table) uint32"}, {"ChecksumIEEE", Func, 0, "func(data []byte) uint32"}, {"IEEE", Const, 0, ""}, {"IEEETable", Var, 0, ""}, {"Koopman", Const, 0, ""}, {"MakeTable", Func, 0, "func(poly uint32) *Table"}, {"New", Func, 0, "func(tab *Table) hash.Hash32"}, {"NewIEEE", Func, 0, "func() hash.Hash32"}, {"Size", Const, 0, ""}, {"Table", Type, 0, ""}, {"Update", Func, 0, "func(crc uint32, tab *Table, p []byte) uint32"}, }, "hash/crc64": { {"Checksum", Func, 0, "func(data []byte, tab *Table) uint64"}, {"ECMA", Const, 0, ""}, {"ISO", Const, 0, ""}, {"MakeTable", Func, 0, "func(poly uint64) *Table"}, {"New", Func, 0, "func(tab *Table) hash.Hash64"}, {"Size", Const, 0, ""}, {"Table", Type, 0, ""}, {"Update", Func, 0, "func(crc uint64, tab *Table, p []byte) uint64"}, }, "hash/fnv": { {"New128", Func, 9, "func() hash.Hash"}, {"New128a", Func, 9, "func() hash.Hash"}, {"New32", Func, 0, "func() hash.Hash32"}, {"New32a", Func, 0, "func() hash.Hash32"}, {"New64", Func, 0, "func() hash.Hash64"}, {"New64a", Func, 0, "func() hash.Hash64"}, }, "hash/maphash": { {"(*Hash).BlockSize", Method, 14, ""}, {"(*Hash).Reset", Method, 14, ""}, {"(*Hash).Seed", Method, 14, ""}, {"(*Hash).SetSeed", Method, 14, ""}, {"(*Hash).Size", Method, 14, ""}, {"(*Hash).Sum", Method, 14, ""}, {"(*Hash).Sum64", Method, 14, ""}, {"(*Hash).Write", Method, 14, ""}, {"(*Hash).WriteByte", Method, 14, ""}, {"(*Hash).WriteString", Method, 14, ""}, {"Bytes", Func, 19, "func(seed Seed, b []byte) uint64"}, {"Comparable", Func, 24, "func[T comparable](seed Seed, v T) uint64"}, {"Hash", Type, 14, ""}, {"MakeSeed", Func, 14, "func() Seed"}, {"Seed", Type, 14, ""}, {"String", Func, 19, "func(seed Seed, s string) uint64"}, {"WriteComparable", Func, 24, "func[T comparable](h *Hash, x T)"}, }, "html": { {"EscapeString", Func, 0, "func(s string) string"}, {"UnescapeString", Func, 0, "func(s string) string"}, }, "html/template": { {"(*Error).Error", Method, 0, ""}, {"(*Template).AddParseTree", Method, 0, ""}, {"(*Template).Clone", Method, 0, ""}, {"(*Template).DefinedTemplates", Method, 6, ""}, {"(*Template).Delims", Method, 0, ""}, {"(*Template).Execute", Method, 0, ""}, {"(*Template).ExecuteTemplate", Method, 0, ""}, {"(*Template).Funcs", Method, 0, ""}, {"(*Template).Lookup", Method, 0, ""}, {"(*Template).Name", Method, 0, ""}, {"(*Template).New", Method, 0, ""}, {"(*Template).Option", Method, 5, ""}, {"(*Template).Parse", Method, 0, ""}, {"(*Template).ParseFS", Method, 16, ""}, {"(*Template).ParseFiles", Method, 0, ""}, {"(*Template).ParseGlob", Method, 0, ""}, {"(*Template).Templates", Method, 0, ""}, {"CSS", Type, 0, ""}, {"ErrAmbigContext", Const, 0, ""}, {"ErrBadHTML", Const, 0, ""}, {"ErrBranchEnd", Const, 0, ""}, {"ErrEndContext", Const, 0, ""}, {"ErrJSTemplate", Const, 21, ""}, {"ErrNoSuchTemplate", Const, 0, ""}, {"ErrOutputContext", Const, 0, ""}, {"ErrPartialCharset", Const, 0, ""}, {"ErrPartialEscape", Const, 0, ""}, {"ErrPredefinedEscaper", Const, 9, ""}, {"ErrRangeLoopReentry", Const, 0, ""}, {"ErrSlashAmbig", Const, 0, ""}, {"Error", Type, 0, ""}, {"Error.Description", Field, 0, ""}, {"Error.ErrorCode", Field, 0, ""}, {"Error.Line", Field, 0, ""}, {"Error.Name", Field, 0, ""}, {"Error.Node", Field, 4, ""}, {"ErrorCode", Type, 0, ""}, {"FuncMap", Type, 0, ""}, {"HTML", Type, 0, ""}, {"HTMLAttr", Type, 0, ""}, {"HTMLEscape", Func, 0, "func(w io.Writer, b []byte)"}, {"HTMLEscapeString", Func, 0, "func(s string) string"}, {"HTMLEscaper", Func, 0, "func(args ...any) string"}, {"IsTrue", Func, 6, "func(val any) (truth bool, ok bool)"}, {"JS", Type, 0, ""}, {"JSEscape", Func, 0, "func(w io.Writer, b []byte)"}, {"JSEscapeString", Func, 0, "func(s string) string"}, {"JSEscaper", Func, 0, "func(args ...any) string"}, {"JSStr", Type, 0, ""}, {"Must", Func, 0, "func(t *Template, err error) *Template"}, {"New", Func, 0, "func(name string) *Template"}, {"OK", Const, 0, ""}, {"ParseFS", Func, 16, "func(fs fs.FS, patterns ...string) (*Template, error)"}, {"ParseFiles", Func, 0, "func(filenames ...string) (*Template, error)"}, {"ParseGlob", Func, 0, "func(pattern string) (*Template, error)"}, {"Srcset", Type, 10, ""}, {"Template", Type, 0, ""}, {"Template.Tree", Field, 2, ""}, {"URL", Type, 0, ""}, {"URLQueryEscaper", Func, 0, "func(args ...any) string"}, }, "image": { {"(*Alpha).AlphaAt", Method, 4, ""}, {"(*Alpha).At", Method, 0, ""}, {"(*Alpha).Bounds", Method, 0, ""}, {"(*Alpha).ColorModel", Method, 0, ""}, {"(*Alpha).Opaque", Method, 0, ""}, {"(*Alpha).PixOffset", Method, 0, ""}, {"(*Alpha).RGBA64At", Method, 17, ""}, {"(*Alpha).Set", Method, 0, ""}, {"(*Alpha).SetAlpha", Method, 0, ""}, {"(*Alpha).SetRGBA64", Method, 17, ""}, {"(*Alpha).SubImage", Method, 0, ""}, {"(*Alpha16).Alpha16At", Method, 4, ""}, {"(*Alpha16).At", Method, 0, ""}, {"(*Alpha16).Bounds", Method, 0, ""}, {"(*Alpha16).ColorModel", Method, 0, ""}, {"(*Alpha16).Opaque", Method, 0, ""}, {"(*Alpha16).PixOffset", Method, 0, ""}, {"(*Alpha16).RGBA64At", Method, 17, ""}, {"(*Alpha16).Set", Method, 0, ""}, {"(*Alpha16).SetAlpha16", Method, 0, ""}, {"(*Alpha16).SetRGBA64", Method, 17, ""}, {"(*Alpha16).SubImage", Method, 0, ""}, {"(*CMYK).At", Method, 5, ""}, {"(*CMYK).Bounds", Method, 5, ""}, {"(*CMYK).CMYKAt", Method, 5, ""}, {"(*CMYK).ColorModel", Method, 5, ""}, {"(*CMYK).Opaque", Method, 5, ""}, {"(*CMYK).PixOffset", Method, 5, ""}, {"(*CMYK).RGBA64At", Method, 17, ""}, {"(*CMYK).Set", Method, 5, ""}, {"(*CMYK).SetCMYK", Method, 5, ""}, {"(*CMYK).SetRGBA64", Method, 17, ""}, {"(*CMYK).SubImage", Method, 5, ""}, {"(*Gray).At", Method, 0, ""}, {"(*Gray).Bounds", Method, 0, ""}, {"(*Gray).ColorModel", Method, 0, ""}, {"(*Gray).GrayAt", Method, 4, ""}, {"(*Gray).Opaque", Method, 0, ""}, {"(*Gray).PixOffset", Method, 0, ""}, {"(*Gray).RGBA64At", Method, 17, ""}, {"(*Gray).Set", Method, 0, ""}, {"(*Gray).SetGray", Method, 0, ""}, {"(*Gray).SetRGBA64", Method, 17, ""}, {"(*Gray).SubImage", Method, 0, ""}, {"(*Gray16).At", Method, 0, ""}, {"(*Gray16).Bounds", Method, 0, ""}, {"(*Gray16).ColorModel", Method, 0, ""}, {"(*Gray16).Gray16At", Method, 4, ""}, {"(*Gray16).Opaque", Method, 0, ""}, {"(*Gray16).PixOffset", Method, 0, ""}, {"(*Gray16).RGBA64At", Method, 17, ""}, {"(*Gray16).Set", Method, 0, ""}, {"(*Gray16).SetGray16", Method, 0, ""}, {"(*Gray16).SetRGBA64", Method, 17, ""}, {"(*Gray16).SubImage", Method, 0, ""}, {"(*NRGBA).At", Method, 0, ""}, {"(*NRGBA).Bounds", Method, 0, ""}, {"(*NRGBA).ColorModel", Method, 0, ""}, {"(*NRGBA).NRGBAAt", Method, 4, ""}, {"(*NRGBA).Opaque", Method, 0, ""}, {"(*NRGBA).PixOffset", Method, 0, ""}, {"(*NRGBA).RGBA64At", Method, 17, ""}, {"(*NRGBA).Set", Method, 0, ""}, {"(*NRGBA).SetNRGBA", Method, 0, ""}, {"(*NRGBA).SetRGBA64", Method, 17, ""}, {"(*NRGBA).SubImage", Method, 0, ""}, {"(*NRGBA64).At", Method, 0, ""}, {"(*NRGBA64).Bounds", Method, 0, ""}, {"(*NRGBA64).ColorModel", Method, 0, ""}, {"(*NRGBA64).NRGBA64At", Method, 4, ""}, {"(*NRGBA64).Opaque", Method, 0, ""}, {"(*NRGBA64).PixOffset", Method, 0, ""}, {"(*NRGBA64).RGBA64At", Method, 17, ""}, {"(*NRGBA64).Set", Method, 0, ""}, {"(*NRGBA64).SetNRGBA64", Method, 0, ""}, {"(*NRGBA64).SetRGBA64", Method, 17, ""}, {"(*NRGBA64).SubImage", Method, 0, ""}, {"(*NYCbCrA).AOffset", Method, 6, ""}, {"(*NYCbCrA).At", Method, 6, ""}, {"(*NYCbCrA).Bounds", Method, 6, ""}, {"(*NYCbCrA).COffset", Method, 6, ""}, {"(*NYCbCrA).ColorModel", Method, 6, ""}, {"(*NYCbCrA).NYCbCrAAt", Method, 6, ""}, {"(*NYCbCrA).Opaque", Method, 6, ""}, {"(*NYCbCrA).RGBA64At", Method, 17, ""}, {"(*NYCbCrA).SubImage", Method, 6, ""}, {"(*NYCbCrA).YCbCrAt", Method, 6, ""}, {"(*NYCbCrA).YOffset", Method, 6, ""}, {"(*Paletted).At", Method, 0, ""}, {"(*Paletted).Bounds", Method, 0, ""}, {"(*Paletted).ColorIndexAt", Method, 0, ""}, {"(*Paletted).ColorModel", Method, 0, ""}, {"(*Paletted).Opaque", Method, 0, ""}, {"(*Paletted).PixOffset", Method, 0, ""}, {"(*Paletted).RGBA64At", Method, 17, ""}, {"(*Paletted).Set", Method, 0, ""}, {"(*Paletted).SetColorIndex", Method, 0, ""}, {"(*Paletted).SetRGBA64", Method, 17, ""}, {"(*Paletted).SubImage", Method, 0, ""}, {"(*RGBA).At", Method, 0, ""}, {"(*RGBA).Bounds", Method, 0, ""}, {"(*RGBA).ColorModel", Method, 0, ""}, {"(*RGBA).Opaque", Method, 0, ""}, {"(*RGBA).PixOffset", Method, 0, ""}, {"(*RGBA).RGBA64At", Method, 17, ""}, {"(*RGBA).RGBAAt", Method, 4, ""}, {"(*RGBA).Set", Method, 0, ""}, {"(*RGBA).SetRGBA", Method, 0, ""}, {"(*RGBA).SetRGBA64", Method, 17, ""}, {"(*RGBA).SubImage", Method, 0, ""}, {"(*RGBA64).At", Method, 0, ""}, {"(*RGBA64).Bounds", Method, 0, ""}, {"(*RGBA64).ColorModel", Method, 0, ""}, {"(*RGBA64).Opaque", Method, 0, ""}, {"(*RGBA64).PixOffset", Method, 0, ""}, {"(*RGBA64).RGBA64At", Method, 4, ""}, {"(*RGBA64).Set", Method, 0, ""}, {"(*RGBA64).SetRGBA64", Method, 0, ""}, {"(*RGBA64).SubImage", Method, 0, ""}, {"(*Uniform).At", Method, 0, ""}, {"(*Uniform).Bounds", Method, 0, ""}, {"(*Uniform).ColorModel", Method, 0, ""}, {"(*Uniform).Convert", Method, 0, ""}, {"(*Uniform).Opaque", Method, 0, ""}, {"(*Uniform).RGBA", Method, 0, ""}, {"(*Uniform).RGBA64At", Method, 17, ""}, {"(*YCbCr).At", Method, 0, ""}, {"(*YCbCr).Bounds", Method, 0, ""}, {"(*YCbCr).COffset", Method, 0, ""}, {"(*YCbCr).ColorModel", Method, 0, ""}, {"(*YCbCr).Opaque", Method, 0, ""}, {"(*YCbCr).RGBA64At", Method, 17, ""}, {"(*YCbCr).SubImage", Method, 0, ""}, {"(*YCbCr).YCbCrAt", Method, 4, ""}, {"(*YCbCr).YOffset", Method, 0, ""}, {"(Point).Add", Method, 0, ""}, {"(Point).Div", Method, 0, ""}, {"(Point).Eq", Method, 0, ""}, {"(Point).In", Method, 0, ""}, {"(Point).Mod", Method, 0, ""}, {"(Point).Mul", Method, 0, ""}, {"(Point).String", Method, 0, ""}, {"(Point).Sub", Method, 0, ""}, {"(Rectangle).Add", Method, 0, ""}, {"(Rectangle).At", Method, 5, ""}, {"(Rectangle).Bounds", Method, 5, ""}, {"(Rectangle).Canon", Method, 0, ""}, {"(Rectangle).ColorModel", Method, 5, ""}, {"(Rectangle).Dx", Method, 0, ""}, {"(Rectangle).Dy", Method, 0, ""}, {"(Rectangle).Empty", Method, 0, ""}, {"(Rectangle).Eq", Method, 0, ""}, {"(Rectangle).In", Method, 0, ""}, {"(Rectangle).Inset", Method, 0, ""}, {"(Rectangle).Intersect", Method, 0, ""}, {"(Rectangle).Overlaps", Method, 0, ""}, {"(Rectangle).RGBA64At", Method, 17, ""}, {"(Rectangle).Size", Method, 0, ""}, {"(Rectangle).String", Method, 0, ""}, {"(Rectangle).Sub", Method, 0, ""}, {"(Rectangle).Union", Method, 0, ""}, {"(YCbCrSubsampleRatio).String", Method, 0, ""}, {"Alpha", Type, 0, ""}, {"Alpha.Pix", Field, 0, ""}, {"Alpha.Rect", Field, 0, ""}, {"Alpha.Stride", Field, 0, ""}, {"Alpha16", Type, 0, ""}, {"Alpha16.Pix", Field, 0, ""}, {"Alpha16.Rect", Field, 0, ""}, {"Alpha16.Stride", Field, 0, ""}, {"Black", Var, 0, ""}, {"CMYK", Type, 5, ""}, {"CMYK.Pix", Field, 5, ""}, {"CMYK.Rect", Field, 5, ""}, {"CMYK.Stride", Field, 5, ""}, {"Config", Type, 0, ""}, {"Config.ColorModel", Field, 0, ""}, {"Config.Height", Field, 0, ""}, {"Config.Width", Field, 0, ""}, {"Decode", Func, 0, "func(r io.Reader) (Image, string, error)"}, {"DecodeConfig", Func, 0, "func(r io.Reader) (Config, string, error)"}, {"ErrFormat", Var, 0, ""}, {"Gray", Type, 0, ""}, {"Gray.Pix", Field, 0, ""}, {"Gray.Rect", Field, 0, ""}, {"Gray.Stride", Field, 0, ""}, {"Gray16", Type, 0, ""}, {"Gray16.Pix", Field, 0, ""}, {"Gray16.Rect", Field, 0, ""}, {"Gray16.Stride", Field, 0, ""}, {"Image", Type, 0, ""}, {"NRGBA", Type, 0, ""}, {"NRGBA.Pix", Field, 0, ""}, {"NRGBA.Rect", Field, 0, ""}, {"NRGBA.Stride", Field, 0, ""}, {"NRGBA64", Type, 0, ""}, {"NRGBA64.Pix", Field, 0, ""}, {"NRGBA64.Rect", Field, 0, ""}, {"NRGBA64.Stride", Field, 0, ""}, {"NYCbCrA", Type, 6, ""}, {"NYCbCrA.A", Field, 6, ""}, {"NYCbCrA.AStride", Field, 6, ""}, {"NYCbCrA.YCbCr", Field, 6, ""}, {"NewAlpha", Func, 0, "func(r Rectangle) *Alpha"}, {"NewAlpha16", Func, 0, "func(r Rectangle) *Alpha16"}, {"NewCMYK", Func, 5, "func(r Rectangle) *CMYK"}, {"NewGray", Func, 0, "func(r Rectangle) *Gray"}, {"NewGray16", Func, 0, "func(r Rectangle) *Gray16"}, {"NewNRGBA", Func, 0, "func(r Rectangle) *NRGBA"}, {"NewNRGBA64", Func, 0, "func(r Rectangle) *NRGBA64"}, {"NewNYCbCrA", Func, 6, "func(r Rectangle, subsampleRatio YCbCrSubsampleRatio) *NYCbCrA"}, {"NewPaletted", Func, 0, "func(r Rectangle, p color.Palette) *Paletted"}, {"NewRGBA", Func, 0, "func(r Rectangle) *RGBA"}, {"NewRGBA64", Func, 0, "func(r Rectangle) *RGBA64"}, {"NewUniform", Func, 0, "func(c color.Color) *Uniform"}, {"NewYCbCr", Func, 0, "func(r Rectangle, subsampleRatio YCbCrSubsampleRatio) *YCbCr"}, {"Opaque", Var, 0, ""}, {"Paletted", Type, 0, ""}, {"Paletted.Palette", Field, 0, ""}, {"Paletted.Pix", Field, 0, ""}, {"Paletted.Rect", Field, 0, ""}, {"Paletted.Stride", Field, 0, ""}, {"PalettedImage", Type, 0, ""}, {"Point", Type, 0, ""}, {"Point.X", Field, 0, ""}, {"Point.Y", Field, 0, ""}, {"Pt", Func, 0, "func(X int, Y int) Point"}, {"RGBA", Type, 0, ""}, {"RGBA.Pix", Field, 0, ""}, {"RGBA.Rect", Field, 0, ""}, {"RGBA.Stride", Field, 0, ""}, {"RGBA64", Type, 0, ""}, {"RGBA64.Pix", Field, 0, ""}, {"RGBA64.Rect", Field, 0, ""}, {"RGBA64.Stride", Field, 0, ""}, {"RGBA64Image", Type, 17, ""}, {"Rect", Func, 0, "func(x0 int, y0 int, x1 int, y1 int) Rectangle"}, {"Rectangle", Type, 0, ""}, {"Rectangle.Max", Field, 0, ""}, {"Rectangle.Min", Field, 0, ""}, {"RegisterFormat", Func, 0, "func(name string, magic string, decode func(io.Reader) (Image, error), decodeConfig func(io.Reader) (Config, error))"}, {"Transparent", Var, 0, ""}, {"Uniform", Type, 0, ""}, {"Uniform.C", Field, 0, ""}, {"White", Var, 0, ""}, {"YCbCr", Type, 0, ""}, {"YCbCr.CStride", Field, 0, ""}, {"YCbCr.Cb", Field, 0, ""}, {"YCbCr.Cr", Field, 0, ""}, {"YCbCr.Rect", Field, 0, ""}, {"YCbCr.SubsampleRatio", Field, 0, ""}, {"YCbCr.Y", Field, 0, ""}, {"YCbCr.YStride", Field, 0, ""}, {"YCbCrSubsampleRatio", Type, 0, ""}, {"YCbCrSubsampleRatio410", Const, 5, ""}, {"YCbCrSubsampleRatio411", Const, 5, ""}, {"YCbCrSubsampleRatio420", Const, 0, ""}, {"YCbCrSubsampleRatio422", Const, 0, ""}, {"YCbCrSubsampleRatio440", Const, 1, ""}, {"YCbCrSubsampleRatio444", Const, 0, ""}, {"ZP", Var, 0, ""}, {"ZR", Var, 0, ""}, }, "image/color": { {"(Alpha).RGBA", Method, 0, ""}, {"(Alpha16).RGBA", Method, 0, ""}, {"(CMYK).RGBA", Method, 5, ""}, {"(Gray).RGBA", Method, 0, ""}, {"(Gray16).RGBA", Method, 0, ""}, {"(NRGBA).RGBA", Method, 0, ""}, {"(NRGBA64).RGBA", Method, 0, ""}, {"(NYCbCrA).RGBA", Method, 6, ""}, {"(Palette).Convert", Method, 0, ""}, {"(Palette).Index", Method, 0, ""}, {"(RGBA).RGBA", Method, 0, ""}, {"(RGBA64).RGBA", Method, 0, ""}, {"(YCbCr).RGBA", Method, 0, ""}, {"Alpha", Type, 0, ""}, {"Alpha.A", Field, 0, ""}, {"Alpha16", Type, 0, ""}, {"Alpha16.A", Field, 0, ""}, {"Alpha16Model", Var, 0, ""}, {"AlphaModel", Var, 0, ""}, {"Black", Var, 0, ""}, {"CMYK", Type, 5, ""}, {"CMYK.C", Field, 5, ""}, {"CMYK.K", Field, 5, ""}, {"CMYK.M", Field, 5, ""}, {"CMYK.Y", Field, 5, ""}, {"CMYKModel", Var, 5, ""}, {"CMYKToRGB", Func, 5, "func(c uint8, m uint8, y uint8, k uint8) (uint8, uint8, uint8)"}, {"Color", Type, 0, ""}, {"Gray", Type, 0, ""}, {"Gray.Y", Field, 0, ""}, {"Gray16", Type, 0, ""}, {"Gray16.Y", Field, 0, ""}, {"Gray16Model", Var, 0, ""}, {"GrayModel", Var, 0, ""}, {"Model", Type, 0, ""}, {"ModelFunc", Func, 0, "func(f func(Color) Color) Model"}, {"NRGBA", Type, 0, ""}, {"NRGBA.A", Field, 0, ""}, {"NRGBA.B", Field, 0, ""}, {"NRGBA.G", Field, 0, ""}, {"NRGBA.R", Field, 0, ""}, {"NRGBA64", Type, 0, ""}, {"NRGBA64.A", Field, 0, ""}, {"NRGBA64.B", Field, 0, ""}, {"NRGBA64.G", Field, 0, ""}, {"NRGBA64.R", Field, 0, ""}, {"NRGBA64Model", Var, 0, ""}, {"NRGBAModel", Var, 0, ""}, {"NYCbCrA", Type, 6, ""}, {"NYCbCrA.A", Field, 6, ""}, {"NYCbCrA.YCbCr", Field, 6, ""}, {"NYCbCrAModel", Var, 6, ""}, {"Opaque", Var, 0, ""}, {"Palette", Type, 0, ""}, {"RGBA", Type, 0, ""}, {"RGBA.A", Field, 0, ""}, {"RGBA.B", Field, 0, ""}, {"RGBA.G", Field, 0, ""}, {"RGBA.R", Field, 0, ""}, {"RGBA64", Type, 0, ""}, {"RGBA64.A", Field, 0, ""}, {"RGBA64.B", Field, 0, ""}, {"RGBA64.G", Field, 0, ""}, {"RGBA64.R", Field, 0, ""}, {"RGBA64Model", Var, 0, ""}, {"RGBAModel", Var, 0, ""}, {"RGBToCMYK", Func, 5, "func(r uint8, g uint8, b uint8) (uint8, uint8, uint8, uint8)"}, {"RGBToYCbCr", Func, 0, "func(r uint8, g uint8, b uint8) (uint8, uint8, uint8)"}, {"Transparent", Var, 0, ""}, {"White", Var, 0, ""}, {"YCbCr", Type, 0, ""}, {"YCbCr.Cb", Field, 0, ""}, {"YCbCr.Cr", Field, 0, ""}, {"YCbCr.Y", Field, 0, ""}, {"YCbCrModel", Var, 0, ""}, {"YCbCrToRGB", Func, 0, "func(y uint8, cb uint8, cr uint8) (uint8, uint8, uint8)"}, }, "image/color/palette": { {"Plan9", Var, 2, ""}, {"WebSafe", Var, 2, ""}, }, "image/draw": { {"(Op).Draw", Method, 2, ""}, {"Draw", Func, 0, "func(dst Image, r image.Rectangle, src image.Image, sp image.Point, op Op)"}, {"DrawMask", Func, 0, "func(dst Image, r image.Rectangle, src image.Image, sp image.Point, mask image.Image, mp image.Point, op Op)"}, {"Drawer", Type, 2, ""}, {"FloydSteinberg", Var, 2, ""}, {"Image", Type, 0, ""}, {"Op", Type, 0, ""}, {"Over", Const, 0, ""}, {"Quantizer", Type, 2, ""}, {"RGBA64Image", Type, 17, ""}, {"Src", Const, 0, ""}, }, "image/gif": { {"Decode", Func, 0, "func(r io.Reader) (image.Image, error)"}, {"DecodeAll", Func, 0, "func(r io.Reader) (*GIF, error)"}, {"DecodeConfig", Func, 0, "func(r io.Reader) (image.Config, error)"}, {"DisposalBackground", Const, 5, ""}, {"DisposalNone", Const, 5, ""}, {"DisposalPrevious", Const, 5, ""}, {"Encode", Func, 2, "func(w io.Writer, m image.Image, o *Options) error"}, {"EncodeAll", Func, 2, "func(w io.Writer, g *GIF) error"}, {"GIF", Type, 0, ""}, {"GIF.BackgroundIndex", Field, 5, ""}, {"GIF.Config", Field, 5, ""}, {"GIF.Delay", Field, 0, ""}, {"GIF.Disposal", Field, 5, ""}, {"GIF.Image", Field, 0, ""}, {"GIF.LoopCount", Field, 0, ""}, {"Options", Type, 2, ""}, {"Options.Drawer", Field, 2, ""}, {"Options.NumColors", Field, 2, ""}, {"Options.Quantizer", Field, 2, ""}, }, "image/jpeg": { {"(FormatError).Error", Method, 0, ""}, {"(UnsupportedError).Error", Method, 0, ""}, {"Decode", Func, 0, "func(r io.Reader) (image.Image, error)"}, {"DecodeConfig", Func, 0, "func(r io.Reader) (image.Config, error)"}, {"DefaultQuality", Const, 0, ""}, {"Encode", Func, 0, "func(w io.Writer, m image.Image, o *Options) error"}, {"FormatError", Type, 0, ""}, {"Options", Type, 0, ""}, {"Options.Quality", Field, 0, ""}, {"Reader", Type, 0, ""}, {"UnsupportedError", Type, 0, ""}, }, "image/png": { {"(*Encoder).Encode", Method, 4, ""}, {"(FormatError).Error", Method, 0, ""}, {"(UnsupportedError).Error", Method, 0, ""}, {"BestCompression", Const, 4, ""}, {"BestSpeed", Const, 4, ""}, {"CompressionLevel", Type, 4, ""}, {"Decode", Func, 0, "func(r io.Reader) (image.Image, error)"}, {"DecodeConfig", Func, 0, "func(r io.Reader) (image.Config, error)"}, {"DefaultCompression", Const, 4, ""}, {"Encode", Func, 0, "func(w io.Writer, m image.Image) error"}, {"Encoder", Type, 4, ""}, {"Encoder.BufferPool", Field, 9, ""}, {"Encoder.CompressionLevel", Field, 4, ""}, {"EncoderBuffer", Type, 9, ""}, {"EncoderBufferPool", Type, 9, ""}, {"FormatError", Type, 0, ""}, {"NoCompression", Const, 4, ""}, {"UnsupportedError", Type, 0, ""}, }, "index/suffixarray": { {"(*Index).Bytes", Method, 0, ""}, {"(*Index).FindAllIndex", Method, 0, ""}, {"(*Index).Lookup", Method, 0, ""}, {"(*Index).Read", Method, 0, ""}, {"(*Index).Write", Method, 0, ""}, {"Index", Type, 0, ""}, {"New", Func, 0, "func(data []byte) *Index"}, }, "io": { {"(*LimitedReader).Read", Method, 0, ""}, {"(*OffsetWriter).Seek", Method, 20, ""}, {"(*OffsetWriter).Write", Method, 20, ""}, {"(*OffsetWriter).WriteAt", Method, 20, ""}, {"(*PipeReader).Close", Method, 0, ""}, {"(*PipeReader).CloseWithError", Method, 0, ""}, {"(*PipeReader).Read", Method, 0, ""}, {"(*PipeWriter).Close", Method, 0, ""}, {"(*PipeWriter).CloseWithError", Method, 0, ""}, {"(*PipeWriter).Write", Method, 0, ""}, {"(*SectionReader).Outer", Method, 22, ""}, {"(*SectionReader).Read", Method, 0, ""}, {"(*SectionReader).ReadAt", Method, 0, ""}, {"(*SectionReader).Seek", Method, 0, ""}, {"(*SectionReader).Size", Method, 0, ""}, {"ByteReader", Type, 0, ""}, {"ByteScanner", Type, 0, ""}, {"ByteWriter", Type, 1, ""}, {"Closer", Type, 0, ""}, {"Copy", Func, 0, "func(dst Writer, src Reader) (written int64, err error)"}, {"CopyBuffer", Func, 5, "func(dst Writer, src Reader, buf []byte) (written int64, err error)"}, {"CopyN", Func, 0, "func(dst Writer, src Reader, n int64) (written int64, err error)"}, {"Discard", Var, 16, ""}, {"EOF", Var, 0, ""}, {"ErrClosedPipe", Var, 0, ""}, {"ErrNoProgress", Var, 1, ""}, {"ErrShortBuffer", Var, 0, ""}, {"ErrShortWrite", Var, 0, ""}, {"ErrUnexpectedEOF", Var, 0, ""}, {"LimitReader", Func, 0, "func(r Reader, n int64) Reader"}, {"LimitedReader", Type, 0, ""}, {"LimitedReader.N", Field, 0, ""}, {"LimitedReader.R", Field, 0, ""}, {"MultiReader", Func, 0, "func(readers ...Reader) Reader"}, {"MultiWriter", Func, 0, "func(writers ...Writer) Writer"}, {"NewOffsetWriter", Func, 20, "func(w WriterAt, off int64) *OffsetWriter"}, {"NewSectionReader", Func, 0, "func(r ReaderAt, off int64, n int64) *SectionReader"}, {"NopCloser", Func, 16, "func(r Reader) ReadCloser"}, {"OffsetWriter", Type, 20, ""}, {"Pipe", Func, 0, "func() (*PipeReader, *PipeWriter)"}, {"PipeReader", Type, 0, ""}, {"PipeWriter", Type, 0, ""}, {"ReadAll", Func, 16, "func(r Reader) ([]byte, error)"}, {"ReadAtLeast", Func, 0, "func(r Reader, buf []byte, min int) (n int, err error)"}, {"ReadCloser", Type, 0, ""}, {"ReadFull", Func, 0, "func(r Reader, buf []byte) (n int, err error)"}, {"ReadSeekCloser", Type, 16, ""}, {"ReadSeeker", Type, 0, ""}, {"ReadWriteCloser", Type, 0, ""}, {"ReadWriteSeeker", Type, 0, ""}, {"ReadWriter", Type, 0, ""}, {"Reader", Type, 0, ""}, {"ReaderAt", Type, 0, ""}, {"ReaderFrom", Type, 0, ""}, {"RuneReader", Type, 0, ""}, {"RuneScanner", Type, 0, ""}, {"SectionReader", Type, 0, ""}, {"SeekCurrent", Const, 7, ""}, {"SeekEnd", Const, 7, ""}, {"SeekStart", Const, 7, ""}, {"Seeker", Type, 0, ""}, {"StringWriter", Type, 12, ""}, {"TeeReader", Func, 0, "func(r Reader, w Writer) Reader"}, {"WriteCloser", Type, 0, ""}, {"WriteSeeker", Type, 0, ""}, {"WriteString", Func, 0, "func(w Writer, s string) (n int, err error)"}, {"Writer", Type, 0, ""}, {"WriterAt", Type, 0, ""}, {"WriterTo", Type, 0, ""}, }, "io/fs": { {"(*PathError).Error", Method, 16, ""}, {"(*PathError).Timeout", Method, 16, ""}, {"(*PathError).Unwrap", Method, 16, ""}, {"(FileMode).IsDir", Method, 16, ""}, {"(FileMode).IsRegular", Method, 16, ""}, {"(FileMode).Perm", Method, 16, ""}, {"(FileMode).String", Method, 16, ""}, {"(FileMode).Type", Method, 16, ""}, {"DirEntry", Type, 16, ""}, {"ErrClosed", Var, 16, ""}, {"ErrExist", Var, 16, ""}, {"ErrInvalid", Var, 16, ""}, {"ErrNotExist", Var, 16, ""}, {"ErrPermission", Var, 16, ""}, {"FS", Type, 16, ""}, {"File", Type, 16, ""}, {"FileInfo", Type, 16, ""}, {"FileInfoToDirEntry", Func, 17, "func(info FileInfo) DirEntry"}, {"FileMode", Type, 16, ""}, {"FormatDirEntry", Func, 21, "func(dir DirEntry) string"}, {"FormatFileInfo", Func, 21, "func(info FileInfo) string"}, {"Glob", Func, 16, "func(fsys FS, pattern string) (matches []string, err error)"}, {"GlobFS", Type, 16, ""}, {"Lstat", Func, 25, ""}, {"ModeAppend", Const, 16, ""}, {"ModeCharDevice", Const, 16, ""}, {"ModeDevice", Const, 16, ""}, {"ModeDir", Const, 16, ""}, {"ModeExclusive", Const, 16, ""}, {"ModeIrregular", Const, 16, ""}, {"ModeNamedPipe", Const, 16, ""}, {"ModePerm", Const, 16, ""}, {"ModeSetgid", Const, 16, ""}, {"ModeSetuid", Const, 16, ""}, {"ModeSocket", Const, 16, ""}, {"ModeSticky", Const, 16, ""}, {"ModeSymlink", Const, 16, ""}, {"ModeTemporary", Const, 16, ""}, {"ModeType", Const, 16, ""}, {"PathError", Type, 16, ""}, {"PathError.Err", Field, 16, ""}, {"PathError.Op", Field, 16, ""}, {"PathError.Path", Field, 16, ""}, {"ReadDir", Func, 16, "func(fsys FS, name string) ([]DirEntry, error)"}, {"ReadDirFS", Type, 16, ""}, {"ReadDirFile", Type, 16, ""}, {"ReadFile", Func, 16, "func(fsys FS, name string) ([]byte, error)"}, {"ReadFileFS", Type, 16, ""}, {"ReadLink", Func, 25, ""}, {"ReadLinkFS", Type, 25, ""}, {"SkipAll", Var, 20, ""}, {"SkipDir", Var, 16, ""}, {"Stat", Func, 16, "func(fsys FS, name string) (FileInfo, error)"}, {"StatFS", Type, 16, ""}, {"Sub", Func, 16, "func(fsys FS, dir string) (FS, error)"}, {"SubFS", Type, 16, ""}, {"ValidPath", Func, 16, "func(name string) bool"}, {"WalkDir", Func, 16, "func(fsys FS, root string, fn WalkDirFunc) error"}, {"WalkDirFunc", Type, 16, ""}, }, "io/ioutil": { {"Discard", Var, 0, ""}, {"NopCloser", Func, 0, "func(r io.Reader) io.ReadCloser"}, {"ReadAll", Func, 0, "func(r io.Reader) ([]byte, error)"}, {"ReadDir", Func, 0, "func(dirname string) ([]fs.FileInfo, error)"}, {"ReadFile", Func, 0, "func(filename string) ([]byte, error)"}, {"TempDir", Func, 0, "func(dir string, pattern string) (name string, err error)"}, {"TempFile", Func, 0, "func(dir string, pattern string) (f *os.File, err error)"}, {"WriteFile", Func, 0, "func(filename string, data []byte, perm fs.FileMode) error"}, }, "iter": { {"Pull", Func, 23, "func[V any](seq Seq[V]) (next func() (V, bool), stop func())"}, {"Pull2", Func, 23, "func[K, V any](seq Seq2[K, V]) (next func() (K, V, bool), stop func())"}, {"Seq", Type, 23, ""}, {"Seq2", Type, 23, ""}, }, "log": { {"(*Logger).Fatal", Method, 0, ""}, {"(*Logger).Fatalf", Method, 0, ""}, {"(*Logger).Fatalln", Method, 0, ""}, {"(*Logger).Flags", Method, 0, ""}, {"(*Logger).Output", Method, 0, ""}, {"(*Logger).Panic", Method, 0, ""}, {"(*Logger).Panicf", Method, 0, ""}, {"(*Logger).Panicln", Method, 0, ""}, {"(*Logger).Prefix", Method, 0, ""}, {"(*Logger).Print", Method, 0, ""}, {"(*Logger).Printf", Method, 0, ""}, {"(*Logger).Println", Method, 0, ""}, {"(*Logger).SetFlags", Method, 0, ""}, {"(*Logger).SetOutput", Method, 5, ""}, {"(*Logger).SetPrefix", Method, 0, ""}, {"(*Logger).Writer", Method, 12, ""}, {"Default", Func, 16, "func() *Logger"}, {"Fatal", Func, 0, "func(v ...any)"}, {"Fatalf", Func, 0, "func(format string, v ...any)"}, {"Fatalln", Func, 0, "func(v ...any)"}, {"Flags", Func, 0, "func() int"}, {"LUTC", Const, 5, ""}, {"Ldate", Const, 0, ""}, {"Llongfile", Const, 0, ""}, {"Lmicroseconds", Const, 0, ""}, {"Lmsgprefix", Const, 14, ""}, {"Logger", Type, 0, ""}, {"Lshortfile", Const, 0, ""}, {"LstdFlags", Const, 0, ""}, {"Ltime", Const, 0, ""}, {"New", Func, 0, "func(out io.Writer, prefix string, flag int) *Logger"}, {"Output", Func, 5, "func(calldepth int, s string) error"}, {"Panic", Func, 0, "func(v ...any)"}, {"Panicf", Func, 0, "func(format string, v ...any)"}, {"Panicln", Func, 0, "func(v ...any)"}, {"Prefix", Func, 0, "func() string"}, {"Print", Func, 0, "func(v ...any)"}, {"Printf", Func, 0, "func(format string, v ...any)"}, {"Println", Func, 0, "func(v ...any)"}, {"SetFlags", Func, 0, "func(flag int)"}, {"SetOutput", Func, 0, "func(w io.Writer)"}, {"SetPrefix", Func, 0, "func(prefix string)"}, {"Writer", Func, 13, "func() io.Writer"}, }, "log/slog": { {"(*JSONHandler).Enabled", Method, 21, ""}, {"(*JSONHandler).Handle", Method, 21, ""}, {"(*JSONHandler).WithAttrs", Method, 21, ""}, {"(*JSONHandler).WithGroup", Method, 21, ""}, {"(*Level).UnmarshalJSON", Method, 21, ""}, {"(*Level).UnmarshalText", Method, 21, ""}, {"(*LevelVar).AppendText", Method, 24, ""}, {"(*LevelVar).Level", Method, 21, ""}, {"(*LevelVar).MarshalText", Method, 21, ""}, {"(*LevelVar).Set", Method, 21, ""}, {"(*LevelVar).String", Method, 21, ""}, {"(*LevelVar).UnmarshalText", Method, 21, ""}, {"(*Logger).Debug", Method, 21, ""}, {"(*Logger).DebugContext", Method, 21, ""}, {"(*Logger).Enabled", Method, 21, ""}, {"(*Logger).Error", Method, 21, ""}, {"(*Logger).ErrorContext", Method, 21, ""}, {"(*Logger).Handler", Method, 21, ""}, {"(*Logger).Info", Method, 21, ""}, {"(*Logger).InfoContext", Method, 21, ""}, {"(*Logger).Log", Method, 21, ""}, {"(*Logger).LogAttrs", Method, 21, ""}, {"(*Logger).Warn", Method, 21, ""}, {"(*Logger).WarnContext", Method, 21, ""}, {"(*Logger).With", Method, 21, ""}, {"(*Logger).WithGroup", Method, 21, ""}, {"(*Record).Add", Method, 21, ""}, {"(*Record).AddAttrs", Method, 21, ""}, {"(*TextHandler).Enabled", Method, 21, ""}, {"(*TextHandler).Handle", Method, 21, ""}, {"(*TextHandler).WithAttrs", Method, 21, ""}, {"(*TextHandler).WithGroup", Method, 21, ""}, {"(Attr).Equal", Method, 21, ""}, {"(Attr).String", Method, 21, ""}, {"(Kind).String", Method, 21, ""}, {"(Level).AppendText", Method, 24, ""}, {"(Level).Level", Method, 21, ""}, {"(Level).MarshalJSON", Method, 21, ""}, {"(Level).MarshalText", Method, 21, ""}, {"(Level).String", Method, 21, ""}, {"(Record).Attrs", Method, 21, ""}, {"(Record).Clone", Method, 21, ""}, {"(Record).NumAttrs", Method, 21, ""}, {"(Value).Any", Method, 21, ""}, {"(Value).Bool", Method, 21, ""}, {"(Value).Duration", Method, 21, ""}, {"(Value).Equal", Method, 21, ""}, {"(Value).Float64", Method, 21, ""}, {"(Value).Group", Method, 21, ""}, {"(Value).Int64", Method, 21, ""}, {"(Value).Kind", Method, 21, ""}, {"(Value).LogValuer", Method, 21, ""}, {"(Value).Resolve", Method, 21, ""}, {"(Value).String", Method, 21, ""}, {"(Value).Time", Method, 21, ""}, {"(Value).Uint64", Method, 21, ""}, {"Any", Func, 21, "func(key string, value any) Attr"}, {"AnyValue", Func, 21, "func(v any) Value"}, {"Attr", Type, 21, ""}, {"Attr.Key", Field, 21, ""}, {"Attr.Value", Field, 21, ""}, {"Bool", Func, 21, "func(key string, v bool) Attr"}, {"BoolValue", Func, 21, "func(v bool) Value"}, {"Debug", Func, 21, "func(msg string, args ...any)"}, {"DebugContext", Func, 21, "func(ctx context.Context, msg string, args ...any)"}, {"Default", Func, 21, "func() *Logger"}, {"DiscardHandler", Var, 24, ""}, {"Duration", Func, 21, "func(key string, v time.Duration) Attr"}, {"DurationValue", Func, 21, "func(v time.Duration) Value"}, {"Error", Func, 21, "func(msg string, args ...any)"}, {"ErrorContext", Func, 21, "func(ctx context.Context, msg string, args ...any)"}, {"Float64", Func, 21, "func(key string, v float64) Attr"}, {"Float64Value", Func, 21, "func(v float64) Value"}, {"Group", Func, 21, "func(key string, args ...any) Attr"}, {"GroupValue", Func, 21, "func(as ...Attr) Value"}, {"Handler", Type, 21, ""}, {"HandlerOptions", Type, 21, ""}, {"HandlerOptions.AddSource", Field, 21, ""}, {"HandlerOptions.Level", Field, 21, ""}, {"HandlerOptions.ReplaceAttr", Field, 21, ""}, {"Info", Func, 21, "func(msg string, args ...any)"}, {"InfoContext", Func, 21, "func(ctx context.Context, msg string, args ...any)"}, {"Int", Func, 21, "func(key string, value int) Attr"}, {"Int64", Func, 21, "func(key string, value int64) Attr"}, {"Int64Value", Func, 21, "func(v int64) Value"}, {"IntValue", Func, 21, "func(v int) Value"}, {"JSONHandler", Type, 21, ""}, {"Kind", Type, 21, ""}, {"KindAny", Const, 21, ""}, {"KindBool", Const, 21, ""}, {"KindDuration", Const, 21, ""}, {"KindFloat64", Const, 21, ""}, {"KindGroup", Const, 21, ""}, {"KindInt64", Const, 21, ""}, {"KindLogValuer", Const, 21, ""}, {"KindString", Const, 21, ""}, {"KindTime", Const, 21, ""}, {"KindUint64", Const, 21, ""}, {"Level", Type, 21, ""}, {"LevelDebug", Const, 21, ""}, {"LevelError", Const, 21, ""}, {"LevelInfo", Const, 21, ""}, {"LevelKey", Const, 21, ""}, {"LevelVar", Type, 21, ""}, {"LevelWarn", Const, 21, ""}, {"Leveler", Type, 21, ""}, {"Log", Func, 21, "func(ctx context.Context, level Level, msg string, args ...any)"}, {"LogAttrs", Func, 21, "func(ctx context.Context, level Level, msg string, attrs ...Attr)"}, {"LogValuer", Type, 21, ""}, {"Logger", Type, 21, ""}, {"MessageKey", Const, 21, ""}, {"New", Func, 21, "func(h Handler) *Logger"}, {"NewJSONHandler", Func, 21, "func(w io.Writer, opts *HandlerOptions) *JSONHandler"}, {"NewLogLogger", Func, 21, "func(h Handler, level Level) *log.Logger"}, {"NewRecord", Func, 21, "func(t time.Time, level Level, msg string, pc uintptr) Record"}, {"NewTextHandler", Func, 21, "func(w io.Writer, opts *HandlerOptions) *TextHandler"}, {"Record", Type, 21, ""}, {"Record.Level", Field, 21, ""}, {"Record.Message", Field, 21, ""}, {"Record.PC", Field, 21, ""}, {"Record.Time", Field, 21, ""}, {"SetDefault", Func, 21, "func(l *Logger)"}, {"SetLogLoggerLevel", Func, 22, "func(level Level) (oldLevel Level)"}, {"Source", Type, 21, ""}, {"Source.File", Field, 21, ""}, {"Source.Function", Field, 21, ""}, {"Source.Line", Field, 21, ""}, {"SourceKey", Const, 21, ""}, {"String", Func, 21, "func(key string, value string) Attr"}, {"StringValue", Func, 21, "func(value string) Value"}, {"TextHandler", Type, 21, ""}, {"Time", Func, 21, "func(key string, v time.Time) Attr"}, {"TimeKey", Const, 21, ""}, {"TimeValue", Func, 21, "func(v time.Time) Value"}, {"Uint64", Func, 21, "func(key string, v uint64) Attr"}, {"Uint64Value", Func, 21, "func(v uint64) Value"}, {"Value", Type, 21, ""}, {"Warn", Func, 21, "func(msg string, args ...any)"}, {"WarnContext", Func, 21, "func(ctx context.Context, msg string, args ...any)"}, {"With", Func, 21, "func(args ...any) *Logger"}, }, "log/syslog": { {"(*Writer).Alert", Method, 0, ""}, {"(*Writer).Close", Method, 0, ""}, {"(*Writer).Crit", Method, 0, ""}, {"(*Writer).Debug", Method, 0, ""}, {"(*Writer).Emerg", Method, 0, ""}, {"(*Writer).Err", Method, 0, ""}, {"(*Writer).Info", Method, 0, ""}, {"(*Writer).Notice", Method, 0, ""}, {"(*Writer).Warning", Method, 0, ""}, {"(*Writer).Write", Method, 0, ""}, {"Dial", Func, 0, "func(network string, raddr string, priority Priority, tag string) (*Writer, error)"}, {"LOG_ALERT", Const, 0, ""}, {"LOG_AUTH", Const, 1, ""}, {"LOG_AUTHPRIV", Const, 1, ""}, {"LOG_CRIT", Const, 0, ""}, {"LOG_CRON", Const, 1, ""}, {"LOG_DAEMON", Const, 1, ""}, {"LOG_DEBUG", Const, 0, ""}, {"LOG_EMERG", Const, 0, ""}, {"LOG_ERR", Const, 0, ""}, {"LOG_FTP", Const, 1, ""}, {"LOG_INFO", Const, 0, ""}, {"LOG_KERN", Const, 1, ""}, {"LOG_LOCAL0", Const, 1, ""}, {"LOG_LOCAL1", Const, 1, ""}, {"LOG_LOCAL2", Const, 1, ""}, {"LOG_LOCAL3", Const, 1, ""}, {"LOG_LOCAL4", Const, 1, ""}, {"LOG_LOCAL5", Const, 1, ""}, {"LOG_LOCAL6", Const, 1, ""}, {"LOG_LOCAL7", Const, 1, ""}, {"LOG_LPR", Const, 1, ""}, {"LOG_MAIL", Const, 1, ""}, {"LOG_NEWS", Const, 1, ""}, {"LOG_NOTICE", Const, 0, ""}, {"LOG_SYSLOG", Const, 1, ""}, {"LOG_USER", Const, 1, ""}, {"LOG_UUCP", Const, 1, ""}, {"LOG_WARNING", Const, 0, ""}, {"New", Func, 0, "func(priority Priority, tag string) (*Writer, error)"}, {"NewLogger", Func, 0, "func(p Priority, logFlag int) (*log.Logger, error)"}, {"Priority", Type, 0, ""}, {"Writer", Type, 0, ""}, }, "maps": { {"All", Func, 23, "func[Map ~map[K]V, K comparable, V any](m Map) iter.Seq2[K, V]"}, {"Clone", Func, 21, "func[M ~map[K]V, K comparable, V any](m M) M"}, {"Collect", Func, 23, "func[K comparable, V any](seq iter.Seq2[K, V]) map[K]V"}, {"Copy", Func, 21, "func[M1 ~map[K]V, M2 ~map[K]V, K comparable, V any](dst M1, src M2)"}, {"DeleteFunc", Func, 21, "func[M ~map[K]V, K comparable, V any](m M, del func(K, V) bool)"}, {"Equal", Func, 21, "func[M1, M2 ~map[K]V, K, V comparable](m1 M1, m2 M2) bool"}, {"EqualFunc", Func, 21, "func[M1 ~map[K]V1, M2 ~map[K]V2, K comparable, V1, V2 any](m1 M1, m2 M2, eq func(V1, V2) bool) bool"}, {"Insert", Func, 23, "func[Map ~map[K]V, K comparable, V any](m Map, seq iter.Seq2[K, V])"}, {"Keys", Func, 23, "func[Map ~map[K]V, K comparable, V any](m Map) iter.Seq[K]"}, {"Values", Func, 23, "func[Map ~map[K]V, K comparable, V any](m Map) iter.Seq[V]"}, }, "math": { {"Abs", Func, 0, "func(x float64) float64"}, {"Acos", Func, 0, "func(x float64) float64"}, {"Acosh", Func, 0, "func(x float64) float64"}, {"Asin", Func, 0, "func(x float64) float64"}, {"Asinh", Func, 0, "func(x float64) float64"}, {"Atan", Func, 0, "func(x float64) float64"}, {"Atan2", Func, 0, "func(y float64, x float64) float64"}, {"Atanh", Func, 0, "func(x float64) float64"}, {"Cbrt", Func, 0, "func(x float64) float64"}, {"Ceil", Func, 0, "func(x float64) float64"}, {"Copysign", Func, 0, "func(f float64, sign float64) float64"}, {"Cos", Func, 0, "func(x float64) float64"}, {"Cosh", Func, 0, "func(x float64) float64"}, {"Dim", Func, 0, "func(x float64, y float64) float64"}, {"E", Const, 0, ""}, {"Erf", Func, 0, "func(x float64) float64"}, {"Erfc", Func, 0, "func(x float64) float64"}, {"Erfcinv", Func, 10, "func(x float64) float64"}, {"Erfinv", Func, 10, "func(x float64) float64"}, {"Exp", Func, 0, "func(x float64) float64"}, {"Exp2", Func, 0, "func(x float64) float64"}, {"Expm1", Func, 0, "func(x float64) float64"}, {"FMA", Func, 14, "func(x float64, y float64, z float64) float64"}, {"Float32bits", Func, 0, "func(f float32) uint32"}, {"Float32frombits", Func, 0, "func(b uint32) float32"}, {"Float64bits", Func, 0, "func(f float64) uint64"}, {"Float64frombits", Func, 0, "func(b uint64) float64"}, {"Floor", Func, 0, "func(x float64) float64"}, {"Frexp", Func, 0, "func(f float64) (frac float64, exp int)"}, {"Gamma", Func, 0, "func(x float64) float64"}, {"Hypot", Func, 0, "func(p float64, q float64) float64"}, {"Ilogb", Func, 0, "func(x float64) int"}, {"Inf", Func, 0, "func(sign int) float64"}, {"IsInf", Func, 0, "func(f float64, sign int) bool"}, {"IsNaN", Func, 0, "func(f float64) (is bool)"}, {"J0", Func, 0, "func(x float64) float64"}, {"J1", Func, 0, "func(x float64) float64"}, {"Jn", Func, 0, "func(n int, x float64) float64"}, {"Ldexp", Func, 0, "func(frac float64, exp int) float64"}, {"Lgamma", Func, 0, "func(x float64) (lgamma float64, sign int)"}, {"Ln10", Const, 0, ""}, {"Ln2", Const, 0, ""}, {"Log", Func, 0, "func(x float64) float64"}, {"Log10", Func, 0, "func(x float64) float64"}, {"Log10E", Const, 0, ""}, {"Log1p", Func, 0, "func(x float64) float64"}, {"Log2", Func, 0, "func(x float64) float64"}, {"Log2E", Const, 0, ""}, {"Logb", Func, 0, "func(x float64) float64"}, {"Max", Func, 0, "func(x float64, y float64) float64"}, {"MaxFloat32", Const, 0, ""}, {"MaxFloat64", Const, 0, ""}, {"MaxInt", Const, 17, ""}, {"MaxInt16", Const, 0, ""}, {"MaxInt32", Const, 0, ""}, {"MaxInt64", Const, 0, ""}, {"MaxInt8", Const, 0, ""}, {"MaxUint", Const, 17, ""}, {"MaxUint16", Const, 0, ""}, {"MaxUint32", Const, 0, ""}, {"MaxUint64", Const, 0, ""}, {"MaxUint8", Const, 0, ""}, {"Min", Func, 0, "func(x float64, y float64) float64"}, {"MinInt", Const, 17, ""}, {"MinInt16", Const, 0, ""}, {"MinInt32", Const, 0, ""}, {"MinInt64", Const, 0, ""}, {"MinInt8", Const, 0, ""}, {"Mod", Func, 0, "func(x float64, y float64) float64"}, {"Modf", Func, 0, "func(f float64) (int float64, frac float64)"}, {"NaN", Func, 0, "func() float64"}, {"Nextafter", Func, 0, "func(x float64, y float64) (r float64)"}, {"Nextafter32", Func, 4, "func(x float32, y float32) (r float32)"}, {"Phi", Const, 0, ""}, {"Pi", Const, 0, ""}, {"Pow", Func, 0, "func(x float64, y float64) float64"}, {"Pow10", Func, 0, "func(n int) float64"}, {"Remainder", Func, 0, "func(x float64, y float64) float64"}, {"Round", Func, 10, "func(x float64) float64"}, {"RoundToEven", Func, 10, "func(x float64) float64"}, {"Signbit", Func, 0, "func(x float64) bool"}, {"Sin", Func, 0, "func(x float64) float64"}, {"Sincos", Func, 0, "func(x float64) (sin float64, cos float64)"}, {"Sinh", Func, 0, "func(x float64) float64"}, {"SmallestNonzeroFloat32", Const, 0, ""}, {"SmallestNonzeroFloat64", Const, 0, ""}, {"Sqrt", Func, 0, "func(x float64) float64"}, {"Sqrt2", Const, 0, ""}, {"SqrtE", Const, 0, ""}, {"SqrtPhi", Const, 0, ""}, {"SqrtPi", Const, 0, ""}, {"Tan", Func, 0, "func(x float64) float64"}, {"Tanh", Func, 0, "func(x float64) float64"}, {"Trunc", Func, 0, "func(x float64) float64"}, {"Y0", Func, 0, "func(x float64) float64"}, {"Y1", Func, 0, "func(x float64) float64"}, {"Yn", Func, 0, "func(n int, x float64) float64"}, }, "math/big": { {"(*Float).Abs", Method, 5, ""}, {"(*Float).Acc", Method, 5, ""}, {"(*Float).Add", Method, 5, ""}, {"(*Float).Append", Method, 5, ""}, {"(*Float).AppendText", Method, 24, ""}, {"(*Float).Cmp", Method, 5, ""}, {"(*Float).Copy", Method, 5, ""}, {"(*Float).Float32", Method, 5, ""}, {"(*Float).Float64", Method, 5, ""}, {"(*Float).Format", Method, 5, ""}, {"(*Float).GobDecode", Method, 7, ""}, {"(*Float).GobEncode", Method, 7, ""}, {"(*Float).Int", Method, 5, ""}, {"(*Float).Int64", Method, 5, ""}, {"(*Float).IsInf", Method, 5, ""}, {"(*Float).IsInt", Method, 5, ""}, {"(*Float).MantExp", Method, 5, ""}, {"(*Float).MarshalText", Method, 6, ""}, {"(*Float).MinPrec", Method, 5, ""}, {"(*Float).Mode", Method, 5, ""}, {"(*Float).Mul", Method, 5, ""}, {"(*Float).Neg", Method, 5, ""}, {"(*Float).Parse", Method, 5, ""}, {"(*Float).Prec", Method, 5, ""}, {"(*Float).Quo", Method, 5, ""}, {"(*Float).Rat", Method, 5, ""}, {"(*Float).Scan", Method, 8, ""}, {"(*Float).Set", Method, 5, ""}, {"(*Float).SetFloat64", Method, 5, ""}, {"(*Float).SetInf", Method, 5, ""}, {"(*Float).SetInt", Method, 5, ""}, {"(*Float).SetInt64", Method, 5, ""}, {"(*Float).SetMantExp", Method, 5, ""}, {"(*Float).SetMode", Method, 5, ""}, {"(*Float).SetPrec", Method, 5, ""}, {"(*Float).SetRat", Method, 5, ""}, {"(*Float).SetString", Method, 5, ""}, {"(*Float).SetUint64", Method, 5, ""}, {"(*Float).Sign", Method, 5, ""}, {"(*Float).Signbit", Method, 5, ""}, {"(*Float).Sqrt", Method, 10, ""}, {"(*Float).String", Method, 5, ""}, {"(*Float).Sub", Method, 5, ""}, {"(*Float).Text", Method, 5, ""}, {"(*Float).Uint64", Method, 5, ""}, {"(*Float).UnmarshalText", Method, 6, ""}, {"(*Int).Abs", Method, 0, ""}, {"(*Int).Add", Method, 0, ""}, {"(*Int).And", Method, 0, ""}, {"(*Int).AndNot", Method, 0, ""}, {"(*Int).Append", Method, 6, ""}, {"(*Int).AppendText", Method, 24, ""}, {"(*Int).Binomial", Method, 0, ""}, {"(*Int).Bit", Method, 0, ""}, {"(*Int).BitLen", Method, 0, ""}, {"(*Int).Bits", Method, 0, ""}, {"(*Int).Bytes", Method, 0, ""}, {"(*Int).Cmp", Method, 0, ""}, {"(*Int).CmpAbs", Method, 10, ""}, {"(*Int).Div", Method, 0, ""}, {"(*Int).DivMod", Method, 0, ""}, {"(*Int).Exp", Method, 0, ""}, {"(*Int).FillBytes", Method, 15, ""}, {"(*Int).Float64", Method, 21, ""}, {"(*Int).Format", Method, 0, ""}, {"(*Int).GCD", Method, 0, ""}, {"(*Int).GobDecode", Method, 0, ""}, {"(*Int).GobEncode", Method, 0, ""}, {"(*Int).Int64", Method, 0, ""}, {"(*Int).IsInt64", Method, 9, ""}, {"(*Int).IsUint64", Method, 9, ""}, {"(*Int).Lsh", Method, 0, ""}, {"(*Int).MarshalJSON", Method, 1, ""}, {"(*Int).MarshalText", Method, 3, ""}, {"(*Int).Mod", Method, 0, ""}, {"(*Int).ModInverse", Method, 0, ""}, {"(*Int).ModSqrt", Method, 5, ""}, {"(*Int).Mul", Method, 0, ""}, {"(*Int).MulRange", Method, 0, ""}, {"(*Int).Neg", Method, 0, ""}, {"(*Int).Not", Method, 0, ""}, {"(*Int).Or", Method, 0, ""}, {"(*Int).ProbablyPrime", Method, 0, ""}, {"(*Int).Quo", Method, 0, ""}, {"(*Int).QuoRem", Method, 0, ""}, {"(*Int).Rand", Method, 0, ""}, {"(*Int).Rem", Method, 0, ""}, {"(*Int).Rsh", Method, 0, ""}, {"(*Int).Scan", Method, 0, ""}, {"(*Int).Set", Method, 0, ""}, {"(*Int).SetBit", Method, 0, ""}, {"(*Int).SetBits", Method, 0, ""}, {"(*Int).SetBytes", Method, 0, ""}, {"(*Int).SetInt64", Method, 0, ""}, {"(*Int).SetString", Method, 0, ""}, {"(*Int).SetUint64", Method, 1, ""}, {"(*Int).Sign", Method, 0, ""}, {"(*Int).Sqrt", Method, 8, ""}, {"(*Int).String", Method, 0, ""}, {"(*Int).Sub", Method, 0, ""}, {"(*Int).Text", Method, 6, ""}, {"(*Int).TrailingZeroBits", Method, 13, ""}, {"(*Int).Uint64", Method, 1, ""}, {"(*Int).UnmarshalJSON", Method, 1, ""}, {"(*Int).UnmarshalText", Method, 3, ""}, {"(*Int).Xor", Method, 0, ""}, {"(*Rat).Abs", Method, 0, ""}, {"(*Rat).Add", Method, 0, ""}, {"(*Rat).AppendText", Method, 24, ""}, {"(*Rat).Cmp", Method, 0, ""}, {"(*Rat).Denom", Method, 0, ""}, {"(*Rat).Float32", Method, 4, ""}, {"(*Rat).Float64", Method, 1, ""}, {"(*Rat).FloatPrec", Method, 22, ""}, {"(*Rat).FloatString", Method, 0, ""}, {"(*Rat).GobDecode", Method, 0, ""}, {"(*Rat).GobEncode", Method, 0, ""}, {"(*Rat).Inv", Method, 0, ""}, {"(*Rat).IsInt", Method, 0, ""}, {"(*Rat).MarshalText", Method, 3, ""}, {"(*Rat).Mul", Method, 0, ""}, {"(*Rat).Neg", Method, 0, ""}, {"(*Rat).Num", Method, 0, ""}, {"(*Rat).Quo", Method, 0, ""}, {"(*Rat).RatString", Method, 0, ""}, {"(*Rat).Scan", Method, 0, ""}, {"(*Rat).Set", Method, 0, ""}, {"(*Rat).SetFloat64", Method, 1, ""}, {"(*Rat).SetFrac", Method, 0, ""}, {"(*Rat).SetFrac64", Method, 0, ""}, {"(*Rat).SetInt", Method, 0, ""}, {"(*Rat).SetInt64", Method, 0, ""}, {"(*Rat).SetString", Method, 0, ""}, {"(*Rat).SetUint64", Method, 13, ""}, {"(*Rat).Sign", Method, 0, ""}, {"(*Rat).String", Method, 0, ""}, {"(*Rat).Sub", Method, 0, ""}, {"(*Rat).UnmarshalText", Method, 3, ""}, {"(Accuracy).String", Method, 5, ""}, {"(ErrNaN).Error", Method, 5, ""}, {"(RoundingMode).String", Method, 5, ""}, {"Above", Const, 5, ""}, {"Accuracy", Type, 5, ""}, {"AwayFromZero", Const, 5, ""}, {"Below", Const, 5, ""}, {"ErrNaN", Type, 5, ""}, {"Exact", Const, 5, ""}, {"Float", Type, 5, ""}, {"Int", Type, 0, ""}, {"Jacobi", Func, 5, "func(x *Int, y *Int) int"}, {"MaxBase", Const, 0, ""}, {"MaxExp", Const, 5, ""}, {"MaxPrec", Const, 5, ""}, {"MinExp", Const, 5, ""}, {"NewFloat", Func, 5, "func(x float64) *Float"}, {"NewInt", Func, 0, "func(x int64) *Int"}, {"NewRat", Func, 0, "func(a int64, b int64) *Rat"}, {"ParseFloat", Func, 5, "func(s string, base int, prec uint, mode RoundingMode) (f *Float, b int, err error)"}, {"Rat", Type, 0, ""}, {"RoundingMode", Type, 5, ""}, {"ToNearestAway", Const, 5, ""}, {"ToNearestEven", Const, 5, ""}, {"ToNegativeInf", Const, 5, ""}, {"ToPositiveInf", Const, 5, ""}, {"ToZero", Const, 5, ""}, {"Word", Type, 0, ""}, }, "math/bits": { {"Add", Func, 12, "func(x uint, y uint, carry uint) (sum uint, carryOut uint)"}, {"Add32", Func, 12, "func(x uint32, y uint32, carry uint32) (sum uint32, carryOut uint32)"}, {"Add64", Func, 12, "func(x uint64, y uint64, carry uint64) (sum uint64, carryOut uint64)"}, {"Div", Func, 12, "func(hi uint, lo uint, y uint) (quo uint, rem uint)"}, {"Div32", Func, 12, "func(hi uint32, lo uint32, y uint32) (quo uint32, rem uint32)"}, {"Div64", Func, 12, "func(hi uint64, lo uint64, y uint64) (quo uint64, rem uint64)"}, {"LeadingZeros", Func, 9, "func(x uint) int"}, {"LeadingZeros16", Func, 9, "func(x uint16) int"}, {"LeadingZeros32", Func, 9, "func(x uint32) int"}, {"LeadingZeros64", Func, 9, "func(x uint64) int"}, {"LeadingZeros8", Func, 9, "func(x uint8) int"}, {"Len", Func, 9, "func(x uint) int"}, {"Len16", Func, 9, "func(x uint16) (n int)"}, {"Len32", Func, 9, "func(x uint32) (n int)"}, {"Len64", Func, 9, "func(x uint64) (n int)"}, {"Len8", Func, 9, "func(x uint8) int"}, {"Mul", Func, 12, "func(x uint, y uint) (hi uint, lo uint)"}, {"Mul32", Func, 12, "func(x uint32, y uint32) (hi uint32, lo uint32)"}, {"Mul64", Func, 12, "func(x uint64, y uint64) (hi uint64, lo uint64)"}, {"OnesCount", Func, 9, "func(x uint) int"}, {"OnesCount16", Func, 9, "func(x uint16) int"}, {"OnesCount32", Func, 9, "func(x uint32) int"}, {"OnesCount64", Func, 9, "func(x uint64) int"}, {"OnesCount8", Func, 9, "func(x uint8) int"}, {"Rem", Func, 14, "func(hi uint, lo uint, y uint) uint"}, {"Rem32", Func, 14, "func(hi uint32, lo uint32, y uint32) uint32"}, {"Rem64", Func, 14, "func(hi uint64, lo uint64, y uint64) uint64"}, {"Reverse", Func, 9, "func(x uint) uint"}, {"Reverse16", Func, 9, "func(x uint16) uint16"}, {"Reverse32", Func, 9, "func(x uint32) uint32"}, {"Reverse64", Func, 9, "func(x uint64) uint64"}, {"Reverse8", Func, 9, "func(x uint8) uint8"}, {"ReverseBytes", Func, 9, "func(x uint) uint"}, {"ReverseBytes16", Func, 9, "func(x uint16) uint16"}, {"ReverseBytes32", Func, 9, "func(x uint32) uint32"}, {"ReverseBytes64", Func, 9, "func(x uint64) uint64"}, {"RotateLeft", Func, 9, "func(x uint, k int) uint"}, {"RotateLeft16", Func, 9, "func(x uint16, k int) uint16"}, {"RotateLeft32", Func, 9, "func(x uint32, k int) uint32"}, {"RotateLeft64", Func, 9, "func(x uint64, k int) uint64"}, {"RotateLeft8", Func, 9, "func(x uint8, k int) uint8"}, {"Sub", Func, 12, "func(x uint, y uint, borrow uint) (diff uint, borrowOut uint)"}, {"Sub32", Func, 12, "func(x uint32, y uint32, borrow uint32) (diff uint32, borrowOut uint32)"}, {"Sub64", Func, 12, "func(x uint64, y uint64, borrow uint64) (diff uint64, borrowOut uint64)"}, {"TrailingZeros", Func, 9, "func(x uint) int"}, {"TrailingZeros16", Func, 9, "func(x uint16) int"}, {"TrailingZeros32", Func, 9, "func(x uint32) int"}, {"TrailingZeros64", Func, 9, "func(x uint64) int"}, {"TrailingZeros8", Func, 9, "func(x uint8) int"}, {"UintSize", Const, 9, ""}, }, "math/cmplx": { {"Abs", Func, 0, "func(x complex128) float64"}, {"Acos", Func, 0, "func(x complex128) complex128"}, {"Acosh", Func, 0, "func(x complex128) complex128"}, {"Asin", Func, 0, "func(x complex128) complex128"}, {"Asinh", Func, 0, "func(x complex128) complex128"}, {"Atan", Func, 0, "func(x complex128) complex128"}, {"Atanh", Func, 0, "func(x complex128) complex128"}, {"Conj", Func, 0, "func(x complex128) complex128"}, {"Cos", Func, 0, "func(x complex128) complex128"}, {"Cosh", Func, 0, "func(x complex128) complex128"}, {"Cot", Func, 0, "func(x complex128) complex128"}, {"Exp", Func, 0, "func(x complex128) complex128"}, {"Inf", Func, 0, "func() complex128"}, {"IsInf", Func, 0, "func(x complex128) bool"}, {"IsNaN", Func, 0, "func(x complex128) bool"}, {"Log", Func, 0, "func(x complex128) complex128"}, {"Log10", Func, 0, "func(x complex128) complex128"}, {"NaN", Func, 0, "func() complex128"}, {"Phase", Func, 0, "func(x complex128) float64"}, {"Polar", Func, 0, "func(x complex128) (r float64, θ float64)"}, {"Pow", Func, 0, "func(x complex128, y complex128) complex128"}, {"Rect", Func, 0, "func(r float64, θ float64) complex128"}, {"Sin", Func, 0, "func(x complex128) complex128"}, {"Sinh", Func, 0, "func(x complex128) complex128"}, {"Sqrt", Func, 0, "func(x complex128) complex128"}, {"Tan", Func, 0, "func(x complex128) complex128"}, {"Tanh", Func, 0, "func(x complex128) complex128"}, }, "math/rand": { {"(*Rand).ExpFloat64", Method, 0, ""}, {"(*Rand).Float32", Method, 0, ""}, {"(*Rand).Float64", Method, 0, ""}, {"(*Rand).Int", Method, 0, ""}, {"(*Rand).Int31", Method, 0, ""}, {"(*Rand).Int31n", Method, 0, ""}, {"(*Rand).Int63", Method, 0, ""}, {"(*Rand).Int63n", Method, 0, ""}, {"(*Rand).Intn", Method, 0, ""}, {"(*Rand).NormFloat64", Method, 0, ""}, {"(*Rand).Perm", Method, 0, ""}, {"(*Rand).Read", Method, 6, ""}, {"(*Rand).Seed", Method, 0, ""}, {"(*Rand).Shuffle", Method, 10, ""}, {"(*Rand).Uint32", Method, 0, ""}, {"(*Rand).Uint64", Method, 8, ""}, {"(*Zipf).Uint64", Method, 0, ""}, {"ExpFloat64", Func, 0, "func() float64"}, {"Float32", Func, 0, "func() float32"}, {"Float64", Func, 0, "func() float64"}, {"Int", Func, 0, "func() int"}, {"Int31", Func, 0, "func() int32"}, {"Int31n", Func, 0, "func(n int32) int32"}, {"Int63", Func, 0, "func() int64"}, {"Int63n", Func, 0, "func(n int64) int64"}, {"Intn", Func, 0, "func(n int) int"}, {"New", Func, 0, "func(src Source) *Rand"}, {"NewSource", Func, 0, "func(seed int64) Source"}, {"NewZipf", Func, 0, "func(r *Rand, s float64, v float64, imax uint64) *Zipf"}, {"NormFloat64", Func, 0, "func() float64"}, {"Perm", Func, 0, "func(n int) []int"}, {"Rand", Type, 0, ""}, {"Read", Func, 6, "func(p []byte) (n int, err error)"}, {"Seed", Func, 0, "func(seed int64)"}, {"Shuffle", Func, 10, "func(n int, swap func(i int, j int))"}, {"Source", Type, 0, ""}, {"Source64", Type, 8, ""}, {"Uint32", Func, 0, "func() uint32"}, {"Uint64", Func, 8, "func() uint64"}, {"Zipf", Type, 0, ""}, }, "math/rand/v2": { {"(*ChaCha8).AppendBinary", Method, 24, ""}, {"(*ChaCha8).MarshalBinary", Method, 22, ""}, {"(*ChaCha8).Read", Method, 23, ""}, {"(*ChaCha8).Seed", Method, 22, ""}, {"(*ChaCha8).Uint64", Method, 22, ""}, {"(*ChaCha8).UnmarshalBinary", Method, 22, ""}, {"(*PCG).AppendBinary", Method, 24, ""}, {"(*PCG).MarshalBinary", Method, 22, ""}, {"(*PCG).Seed", Method, 22, ""}, {"(*PCG).Uint64", Method, 22, ""}, {"(*PCG).UnmarshalBinary", Method, 22, ""}, {"(*Rand).ExpFloat64", Method, 22, ""}, {"(*Rand).Float32", Method, 22, ""}, {"(*Rand).Float64", Method, 22, ""}, {"(*Rand).Int", Method, 22, ""}, {"(*Rand).Int32", Method, 22, ""}, {"(*Rand).Int32N", Method, 22, ""}, {"(*Rand).Int64", Method, 22, ""}, {"(*Rand).Int64N", Method, 22, ""}, {"(*Rand).IntN", Method, 22, ""}, {"(*Rand).NormFloat64", Method, 22, ""}, {"(*Rand).Perm", Method, 22, ""}, {"(*Rand).Shuffle", Method, 22, ""}, {"(*Rand).Uint", Method, 23, ""}, {"(*Rand).Uint32", Method, 22, ""}, {"(*Rand).Uint32N", Method, 22, ""}, {"(*Rand).Uint64", Method, 22, ""}, {"(*Rand).Uint64N", Method, 22, ""}, {"(*Rand).UintN", Method, 22, ""}, {"(*Zipf).Uint64", Method, 22, ""}, {"ChaCha8", Type, 22, ""}, {"ExpFloat64", Func, 22, "func() float64"}, {"Float32", Func, 22, "func() float32"}, {"Float64", Func, 22, "func() float64"}, {"Int", Func, 22, "func() int"}, {"Int32", Func, 22, "func() int32"}, {"Int32N", Func, 22, "func(n int32) int32"}, {"Int64", Func, 22, "func() int64"}, {"Int64N", Func, 22, "func(n int64) int64"}, {"IntN", Func, 22, "func(n int) int"}, {"N", Func, 22, "func[Int intType](n Int) Int"}, {"New", Func, 22, "func(src Source) *Rand"}, {"NewChaCha8", Func, 22, "func(seed [32]byte) *ChaCha8"}, {"NewPCG", Func, 22, "func(seed1 uint64, seed2 uint64) *PCG"}, {"NewZipf", Func, 22, "func(r *Rand, s float64, v float64, imax uint64) *Zipf"}, {"NormFloat64", Func, 22, "func() float64"}, {"PCG", Type, 22, ""}, {"Perm", Func, 22, "func(n int) []int"}, {"Rand", Type, 22, ""}, {"Shuffle", Func, 22, "func(n int, swap func(i int, j int))"}, {"Source", Type, 22, ""}, {"Uint", Func, 23, "func() uint"}, {"Uint32", Func, 22, "func() uint32"}, {"Uint32N", Func, 22, "func(n uint32) uint32"}, {"Uint64", Func, 22, "func() uint64"}, {"Uint64N", Func, 22, "func(n uint64) uint64"}, {"UintN", Func, 22, "func(n uint) uint"}, {"Zipf", Type, 22, ""}, }, "mime": { {"(*WordDecoder).Decode", Method, 5, ""}, {"(*WordDecoder).DecodeHeader", Method, 5, ""}, {"(WordEncoder).Encode", Method, 5, ""}, {"AddExtensionType", Func, 0, "func(ext string, typ string) error"}, {"BEncoding", Const, 5, ""}, {"ErrInvalidMediaParameter", Var, 9, ""}, {"ExtensionsByType", Func, 5, "func(typ string) ([]string, error)"}, {"FormatMediaType", Func, 0, "func(t string, param map[string]string) string"}, {"ParseMediaType", Func, 0, "func(v string) (mediatype string, params map[string]string, err error)"}, {"QEncoding", Const, 5, ""}, {"TypeByExtension", Func, 0, "func(ext string) string"}, {"WordDecoder", Type, 5, ""}, {"WordDecoder.CharsetReader", Field, 5, ""}, {"WordEncoder", Type, 5, ""}, }, "mime/multipart": { {"(*FileHeader).Open", Method, 0, ""}, {"(*Form).RemoveAll", Method, 0, ""}, {"(*Part).Close", Method, 0, ""}, {"(*Part).FileName", Method, 0, ""}, {"(*Part).FormName", Method, 0, ""}, {"(*Part).Read", Method, 0, ""}, {"(*Reader).NextPart", Method, 0, ""}, {"(*Reader).NextRawPart", Method, 14, ""}, {"(*Reader).ReadForm", Method, 0, ""}, {"(*Writer).Boundary", Method, 0, ""}, {"(*Writer).Close", Method, 0, ""}, {"(*Writer).CreateFormField", Method, 0, ""}, {"(*Writer).CreateFormFile", Method, 0, ""}, {"(*Writer).CreatePart", Method, 0, ""}, {"(*Writer).FormDataContentType", Method, 0, ""}, {"(*Writer).SetBoundary", Method, 1, ""}, {"(*Writer).WriteField", Method, 0, ""}, {"ErrMessageTooLarge", Var, 9, ""}, {"File", Type, 0, ""}, {"FileContentDisposition", Func, 25, ""}, {"FileHeader", Type, 0, ""}, {"FileHeader.Filename", Field, 0, ""}, {"FileHeader.Header", Field, 0, ""}, {"FileHeader.Size", Field, 9, ""}, {"Form", Type, 0, ""}, {"Form.File", Field, 0, ""}, {"Form.Value", Field, 0, ""}, {"NewReader", Func, 0, "func(r io.Reader, boundary string) *Reader"}, {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, {"Part", Type, 0, ""}, {"Part.Header", Field, 0, ""}, {"Reader", Type, 0, ""}, {"Writer", Type, 0, ""}, }, "mime/quotedprintable": { {"(*Reader).Read", Method, 5, ""}, {"(*Writer).Close", Method, 5, ""}, {"(*Writer).Write", Method, 5, ""}, {"NewReader", Func, 5, "func(r io.Reader) *Reader"}, {"NewWriter", Func, 5, "func(w io.Writer) *Writer"}, {"Reader", Type, 5, ""}, {"Writer", Type, 5, ""}, {"Writer.Binary", Field, 5, ""}, }, "net": { {"(*AddrError).Error", Method, 0, ""}, {"(*AddrError).Temporary", Method, 0, ""}, {"(*AddrError).Timeout", Method, 0, ""}, {"(*Buffers).Read", Method, 8, ""}, {"(*Buffers).WriteTo", Method, 8, ""}, {"(*DNSConfigError).Error", Method, 0, ""}, {"(*DNSConfigError).Temporary", Method, 0, ""}, {"(*DNSConfigError).Timeout", Method, 0, ""}, {"(*DNSConfigError).Unwrap", Method, 13, ""}, {"(*DNSError).Error", Method, 0, ""}, {"(*DNSError).Temporary", Method, 0, ""}, {"(*DNSError).Timeout", Method, 0, ""}, {"(*DNSError).Unwrap", Method, 23, ""}, {"(*Dialer).Dial", Method, 1, ""}, {"(*Dialer).DialContext", Method, 7, ""}, {"(*Dialer).MultipathTCP", Method, 21, ""}, {"(*Dialer).SetMultipathTCP", Method, 21, ""}, {"(*IP).UnmarshalText", Method, 2, ""}, {"(*IPAddr).Network", Method, 0, ""}, {"(*IPAddr).String", Method, 0, ""}, {"(*IPConn).Close", Method, 0, ""}, {"(*IPConn).File", Method, 0, ""}, {"(*IPConn).LocalAddr", Method, 0, ""}, {"(*IPConn).Read", Method, 0, ""}, {"(*IPConn).ReadFrom", Method, 0, ""}, {"(*IPConn).ReadFromIP", Method, 0, ""}, {"(*IPConn).ReadMsgIP", Method, 1, ""}, {"(*IPConn).RemoteAddr", Method, 0, ""}, {"(*IPConn).SetDeadline", Method, 0, ""}, {"(*IPConn).SetReadBuffer", Method, 0, ""}, {"(*IPConn).SetReadDeadline", Method, 0, ""}, {"(*IPConn).SetWriteBuffer", Method, 0, ""}, {"(*IPConn).SetWriteDeadline", Method, 0, ""}, {"(*IPConn).SyscallConn", Method, 9, ""}, {"(*IPConn).Write", Method, 0, ""}, {"(*IPConn).WriteMsgIP", Method, 1, ""}, {"(*IPConn).WriteTo", Method, 0, ""}, {"(*IPConn).WriteToIP", Method, 0, ""}, {"(*IPNet).Contains", Method, 0, ""}, {"(*IPNet).Network", Method, 0, ""}, {"(*IPNet).String", Method, 0, ""}, {"(*Interface).Addrs", Method, 0, ""}, {"(*Interface).MulticastAddrs", Method, 0, ""}, {"(*ListenConfig).Listen", Method, 11, ""}, {"(*ListenConfig).ListenPacket", Method, 11, ""}, {"(*ListenConfig).MultipathTCP", Method, 21, ""}, {"(*ListenConfig).SetMultipathTCP", Method, 21, ""}, {"(*OpError).Error", Method, 0, ""}, {"(*OpError).Temporary", Method, 0, ""}, {"(*OpError).Timeout", Method, 0, ""}, {"(*OpError).Unwrap", Method, 13, ""}, {"(*ParseError).Error", Method, 0, ""}, {"(*ParseError).Temporary", Method, 17, ""}, {"(*ParseError).Timeout", Method, 17, ""}, {"(*Resolver).LookupAddr", Method, 8, ""}, {"(*Resolver).LookupCNAME", Method, 8, ""}, {"(*Resolver).LookupHost", Method, 8, ""}, {"(*Resolver).LookupIP", Method, 15, ""}, {"(*Resolver).LookupIPAddr", Method, 8, ""}, {"(*Resolver).LookupMX", Method, 8, ""}, {"(*Resolver).LookupNS", Method, 8, ""}, {"(*Resolver).LookupNetIP", Method, 18, ""}, {"(*Resolver).LookupPort", Method, 8, ""}, {"(*Resolver).LookupSRV", Method, 8, ""}, {"(*Resolver).LookupTXT", Method, 8, ""}, {"(*TCPAddr).AddrPort", Method, 18, ""}, {"(*TCPAddr).Network", Method, 0, ""}, {"(*TCPAddr).String", Method, 0, ""}, {"(*TCPConn).Close", Method, 0, ""}, {"(*TCPConn).CloseRead", Method, 0, ""}, {"(*TCPConn).CloseWrite", Method, 0, ""}, {"(*TCPConn).File", Method, 0, ""}, {"(*TCPConn).LocalAddr", Method, 0, ""}, {"(*TCPConn).MultipathTCP", Method, 21, ""}, {"(*TCPConn).Read", Method, 0, ""}, {"(*TCPConn).ReadFrom", Method, 0, ""}, {"(*TCPConn).RemoteAddr", Method, 0, ""}, {"(*TCPConn).SetDeadline", Method, 0, ""}, {"(*TCPConn).SetKeepAlive", Method, 0, ""}, {"(*TCPConn).SetKeepAliveConfig", Method, 23, ""}, {"(*TCPConn).SetKeepAlivePeriod", Method, 2, ""}, {"(*TCPConn).SetLinger", Method, 0, ""}, {"(*TCPConn).SetNoDelay", Method, 0, ""}, {"(*TCPConn).SetReadBuffer", Method, 0, ""}, {"(*TCPConn).SetReadDeadline", Method, 0, ""}, {"(*TCPConn).SetWriteBuffer", Method, 0, ""}, {"(*TCPConn).SetWriteDeadline", Method, 0, ""}, {"(*TCPConn).SyscallConn", Method, 9, ""}, {"(*TCPConn).Write", Method, 0, ""}, {"(*TCPConn).WriteTo", Method, 22, ""}, {"(*TCPListener).Accept", Method, 0, ""}, {"(*TCPListener).AcceptTCP", Method, 0, ""}, {"(*TCPListener).Addr", Method, 0, ""}, {"(*TCPListener).Close", Method, 0, ""}, {"(*TCPListener).File", Method, 0, ""}, {"(*TCPListener).SetDeadline", Method, 0, ""}, {"(*TCPListener).SyscallConn", Method, 10, ""}, {"(*UDPAddr).AddrPort", Method, 18, ""}, {"(*UDPAddr).Network", Method, 0, ""}, {"(*UDPAddr).String", Method, 0, ""}, {"(*UDPConn).Close", Method, 0, ""}, {"(*UDPConn).File", Method, 0, ""}, {"(*UDPConn).LocalAddr", Method, 0, ""}, {"(*UDPConn).Read", Method, 0, ""}, {"(*UDPConn).ReadFrom", Method, 0, ""}, {"(*UDPConn).ReadFromUDP", Method, 0, ""}, {"(*UDPConn).ReadFromUDPAddrPort", Method, 18, ""}, {"(*UDPConn).ReadMsgUDP", Method, 1, ""}, {"(*UDPConn).ReadMsgUDPAddrPort", Method, 18, ""}, {"(*UDPConn).RemoteAddr", Method, 0, ""}, {"(*UDPConn).SetDeadline", Method, 0, ""}, {"(*UDPConn).SetReadBuffer", Method, 0, ""}, {"(*UDPConn).SetReadDeadline", Method, 0, ""}, {"(*UDPConn).SetWriteBuffer", Method, 0, ""}, {"(*UDPConn).SetWriteDeadline", Method, 0, ""}, {"(*UDPConn).SyscallConn", Method, 9, ""}, {"(*UDPConn).Write", Method, 0, ""}, {"(*UDPConn).WriteMsgUDP", Method, 1, ""}, {"(*UDPConn).WriteMsgUDPAddrPort", Method, 18, ""}, {"(*UDPConn).WriteTo", Method, 0, ""}, {"(*UDPConn).WriteToUDP", Method, 0, ""}, {"(*UDPConn).WriteToUDPAddrPort", Method, 18, ""}, {"(*UnixAddr).Network", Method, 0, ""}, {"(*UnixAddr).String", Method, 0, ""}, {"(*UnixConn).Close", Method, 0, ""}, {"(*UnixConn).CloseRead", Method, 1, ""}, {"(*UnixConn).CloseWrite", Method, 1, ""}, {"(*UnixConn).File", Method, 0, ""}, {"(*UnixConn).LocalAddr", Method, 0, ""}, {"(*UnixConn).Read", Method, 0, ""}, {"(*UnixConn).ReadFrom", Method, 0, ""}, {"(*UnixConn).ReadFromUnix", Method, 0, ""}, {"(*UnixConn).ReadMsgUnix", Method, 0, ""}, {"(*UnixConn).RemoteAddr", Method, 0, ""}, {"(*UnixConn).SetDeadline", Method, 0, ""}, {"(*UnixConn).SetReadBuffer", Method, 0, ""}, {"(*UnixConn).SetReadDeadline", Method, 0, ""}, {"(*UnixConn).SetWriteBuffer", Method, 0, ""}, {"(*UnixConn).SetWriteDeadline", Method, 0, ""}, {"(*UnixConn).SyscallConn", Method, 9, ""}, {"(*UnixConn).Write", Method, 0, ""}, {"(*UnixConn).WriteMsgUnix", Method, 0, ""}, {"(*UnixConn).WriteTo", Method, 0, ""}, {"(*UnixConn).WriteToUnix", Method, 0, ""}, {"(*UnixListener).Accept", Method, 0, ""}, {"(*UnixListener).AcceptUnix", Method, 0, ""}, {"(*UnixListener).Addr", Method, 0, ""}, {"(*UnixListener).Close", Method, 0, ""}, {"(*UnixListener).File", Method, 0, ""}, {"(*UnixListener).SetDeadline", Method, 0, ""}, {"(*UnixListener).SetUnlinkOnClose", Method, 8, ""}, {"(*UnixListener).SyscallConn", Method, 10, ""}, {"(Flags).String", Method, 0, ""}, {"(HardwareAddr).String", Method, 0, ""}, {"(IP).AppendText", Method, 24, ""}, {"(IP).DefaultMask", Method, 0, ""}, {"(IP).Equal", Method, 0, ""}, {"(IP).IsGlobalUnicast", Method, 0, ""}, {"(IP).IsInterfaceLocalMulticast", Method, 0, ""}, {"(IP).IsLinkLocalMulticast", Method, 0, ""}, {"(IP).IsLinkLocalUnicast", Method, 0, ""}, {"(IP).IsLoopback", Method, 0, ""}, {"(IP).IsMulticast", Method, 0, ""}, {"(IP).IsPrivate", Method, 17, ""}, {"(IP).IsUnspecified", Method, 0, ""}, {"(IP).MarshalText", Method, 2, ""}, {"(IP).Mask", Method, 0, ""}, {"(IP).String", Method, 0, ""}, {"(IP).To16", Method, 0, ""}, {"(IP).To4", Method, 0, ""}, {"(IPMask).Size", Method, 0, ""}, {"(IPMask).String", Method, 0, ""}, {"(InvalidAddrError).Error", Method, 0, ""}, {"(InvalidAddrError).Temporary", Method, 0, ""}, {"(InvalidAddrError).Timeout", Method, 0, ""}, {"(UnknownNetworkError).Error", Method, 0, ""}, {"(UnknownNetworkError).Temporary", Method, 0, ""}, {"(UnknownNetworkError).Timeout", Method, 0, ""}, {"Addr", Type, 0, ""}, {"AddrError", Type, 0, ""}, {"AddrError.Addr", Field, 0, ""}, {"AddrError.Err", Field, 0, ""}, {"Buffers", Type, 8, ""}, {"CIDRMask", Func, 0, "func(ones int, bits int) IPMask"}, {"Conn", Type, 0, ""}, {"DNSConfigError", Type, 0, ""}, {"DNSConfigError.Err", Field, 0, ""}, {"DNSError", Type, 0, ""}, {"DNSError.Err", Field, 0, ""}, {"DNSError.IsNotFound", Field, 13, ""}, {"DNSError.IsTemporary", Field, 6, ""}, {"DNSError.IsTimeout", Field, 0, ""}, {"DNSError.Name", Field, 0, ""}, {"DNSError.Server", Field, 0, ""}, {"DNSError.UnwrapErr", Field, 23, ""}, {"DefaultResolver", Var, 8, ""}, {"Dial", Func, 0, "func(network string, address string) (Conn, error)"}, {"DialIP", Func, 0, "func(network string, laddr *IPAddr, raddr *IPAddr) (*IPConn, error)"}, {"DialTCP", Func, 0, "func(network string, laddr *TCPAddr, raddr *TCPAddr) (*TCPConn, error)"}, {"DialTimeout", Func, 0, "func(network string, address string, timeout time.Duration) (Conn, error)"}, {"DialUDP", Func, 0, "func(network string, laddr *UDPAddr, raddr *UDPAddr) (*UDPConn, error)"}, {"DialUnix", Func, 0, "func(network string, laddr *UnixAddr, raddr *UnixAddr) (*UnixConn, error)"}, {"Dialer", Type, 1, ""}, {"Dialer.Cancel", Field, 6, ""}, {"Dialer.Control", Field, 11, ""}, {"Dialer.ControlContext", Field, 20, ""}, {"Dialer.Deadline", Field, 1, ""}, {"Dialer.DualStack", Field, 2, ""}, {"Dialer.FallbackDelay", Field, 5, ""}, {"Dialer.KeepAlive", Field, 3, ""}, {"Dialer.KeepAliveConfig", Field, 23, ""}, {"Dialer.LocalAddr", Field, 1, ""}, {"Dialer.Resolver", Field, 8, ""}, {"Dialer.Timeout", Field, 1, ""}, {"ErrClosed", Var, 16, ""}, {"ErrWriteToConnected", Var, 0, ""}, {"Error", Type, 0, ""}, {"FileConn", Func, 0, "func(f *os.File) (c Conn, err error)"}, {"FileListener", Func, 0, "func(f *os.File) (ln Listener, err error)"}, {"FilePacketConn", Func, 0, "func(f *os.File) (c PacketConn, err error)"}, {"FlagBroadcast", Const, 0, ""}, {"FlagLoopback", Const, 0, ""}, {"FlagMulticast", Const, 0, ""}, {"FlagPointToPoint", Const, 0, ""}, {"FlagRunning", Const, 20, ""}, {"FlagUp", Const, 0, ""}, {"Flags", Type, 0, ""}, {"HardwareAddr", Type, 0, ""}, {"IP", Type, 0, ""}, {"IPAddr", Type, 0, ""}, {"IPAddr.IP", Field, 0, ""}, {"IPAddr.Zone", Field, 1, ""}, {"IPConn", Type, 0, ""}, {"IPMask", Type, 0, ""}, {"IPNet", Type, 0, ""}, {"IPNet.IP", Field, 0, ""}, {"IPNet.Mask", Field, 0, ""}, {"IPv4", Func, 0, "func(a byte, b byte, c byte, d byte) IP"}, {"IPv4Mask", Func, 0, "func(a byte, b byte, c byte, d byte) IPMask"}, {"IPv4allrouter", Var, 0, ""}, {"IPv4allsys", Var, 0, ""}, {"IPv4bcast", Var, 0, ""}, {"IPv4len", Const, 0, ""}, {"IPv4zero", Var, 0, ""}, {"IPv6interfacelocalallnodes", Var, 0, ""}, {"IPv6len", Const, 0, ""}, {"IPv6linklocalallnodes", Var, 0, ""}, {"IPv6linklocalallrouters", Var, 0, ""}, {"IPv6loopback", Var, 0, ""}, {"IPv6unspecified", Var, 0, ""}, {"IPv6zero", Var, 0, ""}, {"Interface", Type, 0, ""}, {"Interface.Flags", Field, 0, ""}, {"Interface.HardwareAddr", Field, 0, ""}, {"Interface.Index", Field, 0, ""}, {"Interface.MTU", Field, 0, ""}, {"Interface.Name", Field, 0, ""}, {"InterfaceAddrs", Func, 0, "func() ([]Addr, error)"}, {"InterfaceByIndex", Func, 0, "func(index int) (*Interface, error)"}, {"InterfaceByName", Func, 0, "func(name string) (*Interface, error)"}, {"Interfaces", Func, 0, "func() ([]Interface, error)"}, {"InvalidAddrError", Type, 0, ""}, {"JoinHostPort", Func, 0, "func(host string, port string) string"}, {"KeepAliveConfig", Type, 23, ""}, {"KeepAliveConfig.Count", Field, 23, ""}, {"KeepAliveConfig.Enable", Field, 23, ""}, {"KeepAliveConfig.Idle", Field, 23, ""}, {"KeepAliveConfig.Interval", Field, 23, ""}, {"Listen", Func, 0, "func(network string, address string) (Listener, error)"}, {"ListenConfig", Type, 11, ""}, {"ListenConfig.Control", Field, 11, ""}, {"ListenConfig.KeepAlive", Field, 13, ""}, {"ListenConfig.KeepAliveConfig", Field, 23, ""}, {"ListenIP", Func, 0, "func(network string, laddr *IPAddr) (*IPConn, error)"}, {"ListenMulticastUDP", Func, 0, "func(network string, ifi *Interface, gaddr *UDPAddr) (*UDPConn, error)"}, {"ListenPacket", Func, 0, "func(network string, address string) (PacketConn, error)"}, {"ListenTCP", Func, 0, "func(network string, laddr *TCPAddr) (*TCPListener, error)"}, {"ListenUDP", Func, 0, "func(network string, laddr *UDPAddr) (*UDPConn, error)"}, {"ListenUnix", Func, 0, "func(network string, laddr *UnixAddr) (*UnixListener, error)"}, {"ListenUnixgram", Func, 0, "func(network string, laddr *UnixAddr) (*UnixConn, error)"}, {"Listener", Type, 0, ""}, {"LookupAddr", Func, 0, "func(addr string) (names []string, err error)"}, {"LookupCNAME", Func, 0, "func(host string) (cname string, err error)"}, {"LookupHost", Func, 0, "func(host string) (addrs []string, err error)"}, {"LookupIP", Func, 0, "func(host string) ([]IP, error)"}, {"LookupMX", Func, 0, "func(name string) ([]*MX, error)"}, {"LookupNS", Func, 1, "func(name string) ([]*NS, error)"}, {"LookupPort", Func, 0, "func(network string, service string) (port int, err error)"}, {"LookupSRV", Func, 0, "func(service string, proto string, name string) (cname string, addrs []*SRV, err error)"}, {"LookupTXT", Func, 0, "func(name string) ([]string, error)"}, {"MX", Type, 0, ""}, {"MX.Host", Field, 0, ""}, {"MX.Pref", Field, 0, ""}, {"NS", Type, 1, ""}, {"NS.Host", Field, 1, ""}, {"OpError", Type, 0, ""}, {"OpError.Addr", Field, 0, ""}, {"OpError.Err", Field, 0, ""}, {"OpError.Net", Field, 0, ""}, {"OpError.Op", Field, 0, ""}, {"OpError.Source", Field, 5, ""}, {"PacketConn", Type, 0, ""}, {"ParseCIDR", Func, 0, "func(s string) (IP, *IPNet, error)"}, {"ParseError", Type, 0, ""}, {"ParseError.Text", Field, 0, ""}, {"ParseError.Type", Field, 0, ""}, {"ParseIP", Func, 0, "func(s string) IP"}, {"ParseMAC", Func, 0, "func(s string) (hw HardwareAddr, err error)"}, {"Pipe", Func, 0, "func() (Conn, Conn)"}, {"ResolveIPAddr", Func, 0, "func(network string, address string) (*IPAddr, error)"}, {"ResolveTCPAddr", Func, 0, "func(network string, address string) (*TCPAddr, error)"}, {"ResolveUDPAddr", Func, 0, "func(network string, address string) (*UDPAddr, error)"}, {"ResolveUnixAddr", Func, 0, "func(network string, address string) (*UnixAddr, error)"}, {"Resolver", Type, 8, ""}, {"Resolver.Dial", Field, 9, ""}, {"Resolver.PreferGo", Field, 8, ""}, {"Resolver.StrictErrors", Field, 9, ""}, {"SRV", Type, 0, ""}, {"SRV.Port", Field, 0, ""}, {"SRV.Priority", Field, 0, ""}, {"SRV.Target", Field, 0, ""}, {"SRV.Weight", Field, 0, ""}, {"SplitHostPort", Func, 0, "func(hostport string) (host string, port string, err error)"}, {"TCPAddr", Type, 0, ""}, {"TCPAddr.IP", Field, 0, ""}, {"TCPAddr.Port", Field, 0, ""}, {"TCPAddr.Zone", Field, 1, ""}, {"TCPAddrFromAddrPort", Func, 18, "func(addr netip.AddrPort) *TCPAddr"}, {"TCPConn", Type, 0, ""}, {"TCPListener", Type, 0, ""}, {"UDPAddr", Type, 0, ""}, {"UDPAddr.IP", Field, 0, ""}, {"UDPAddr.Port", Field, 0, ""}, {"UDPAddr.Zone", Field, 1, ""}, {"UDPAddrFromAddrPort", Func, 18, "func(addr netip.AddrPort) *UDPAddr"}, {"UDPConn", Type, 0, ""}, {"UnixAddr", Type, 0, ""}, {"UnixAddr.Name", Field, 0, ""}, {"UnixAddr.Net", Field, 0, ""}, {"UnixConn", Type, 0, ""}, {"UnixListener", Type, 0, ""}, {"UnknownNetworkError", Type, 0, ""}, }, "net/http": { {"(*Client).CloseIdleConnections", Method, 12, ""}, {"(*Client).Do", Method, 0, ""}, {"(*Client).Get", Method, 0, ""}, {"(*Client).Head", Method, 0, ""}, {"(*Client).Post", Method, 0, ""}, {"(*Client).PostForm", Method, 0, ""}, {"(*Cookie).String", Method, 0, ""}, {"(*Cookie).Valid", Method, 18, ""}, {"(*MaxBytesError).Error", Method, 19, ""}, {"(*ProtocolError).Error", Method, 0, ""}, {"(*ProtocolError).Is", Method, 21, ""}, {"(*Protocols).SetHTTP1", Method, 24, ""}, {"(*Protocols).SetHTTP2", Method, 24, ""}, {"(*Protocols).SetUnencryptedHTTP2", Method, 24, ""}, {"(*Request).AddCookie", Method, 0, ""}, {"(*Request).BasicAuth", Method, 4, ""}, {"(*Request).Clone", Method, 13, ""}, {"(*Request).Context", Method, 7, ""}, {"(*Request).Cookie", Method, 0, ""}, {"(*Request).Cookies", Method, 0, ""}, {"(*Request).CookiesNamed", Method, 23, ""}, {"(*Request).FormFile", Method, 0, ""}, {"(*Request).FormValue", Method, 0, ""}, {"(*Request).MultipartReader", Method, 0, ""}, {"(*Request).ParseForm", Method, 0, ""}, {"(*Request).ParseMultipartForm", Method, 0, ""}, {"(*Request).PathValue", Method, 22, ""}, {"(*Request).PostFormValue", Method, 1, ""}, {"(*Request).ProtoAtLeast", Method, 0, ""}, {"(*Request).Referer", Method, 0, ""}, {"(*Request).SetBasicAuth", Method, 0, ""}, {"(*Request).SetPathValue", Method, 22, ""}, {"(*Request).UserAgent", Method, 0, ""}, {"(*Request).WithContext", Method, 7, ""}, {"(*Request).Write", Method, 0, ""}, {"(*Request).WriteProxy", Method, 0, ""}, {"(*Response).Cookies", Method, 0, ""}, {"(*Response).Location", Method, 0, ""}, {"(*Response).ProtoAtLeast", Method, 0, ""}, {"(*Response).Write", Method, 0, ""}, {"(*ResponseController).EnableFullDuplex", Method, 21, ""}, {"(*ResponseController).Flush", Method, 20, ""}, {"(*ResponseController).Hijack", Method, 20, ""}, {"(*ResponseController).SetReadDeadline", Method, 20, ""}, {"(*ResponseController).SetWriteDeadline", Method, 20, ""}, {"(*ServeMux).Handle", Method, 0, ""}, {"(*ServeMux).HandleFunc", Method, 0, ""}, {"(*ServeMux).Handler", Method, 1, ""}, {"(*ServeMux).ServeHTTP", Method, 0, ""}, {"(*Server).Close", Method, 8, ""}, {"(*Server).ListenAndServe", Method, 0, ""}, {"(*Server).ListenAndServeTLS", Method, 0, ""}, {"(*Server).RegisterOnShutdown", Method, 9, ""}, {"(*Server).Serve", Method, 0, ""}, {"(*Server).ServeTLS", Method, 9, ""}, {"(*Server).SetKeepAlivesEnabled", Method, 3, ""}, {"(*Server).Shutdown", Method, 8, ""}, {"(*Transport).CancelRequest", Method, 1, ""}, {"(*Transport).Clone", Method, 13, ""}, {"(*Transport).CloseIdleConnections", Method, 0, ""}, {"(*Transport).RegisterProtocol", Method, 0, ""}, {"(*Transport).RoundTrip", Method, 0, ""}, {"(ConnState).String", Method, 3, ""}, {"(Dir).Open", Method, 0, ""}, {"(HandlerFunc).ServeHTTP", Method, 0, ""}, {"(Header).Add", Method, 0, ""}, {"(Header).Clone", Method, 13, ""}, {"(Header).Del", Method, 0, ""}, {"(Header).Get", Method, 0, ""}, {"(Header).Set", Method, 0, ""}, {"(Header).Values", Method, 14, ""}, {"(Header).Write", Method, 0, ""}, {"(Header).WriteSubset", Method, 0, ""}, {"(Protocols).HTTP1", Method, 24, ""}, {"(Protocols).HTTP2", Method, 24, ""}, {"(Protocols).String", Method, 24, ""}, {"(Protocols).UnencryptedHTTP2", Method, 24, ""}, {"AllowQuerySemicolons", Func, 17, "func(h Handler) Handler"}, {"CanonicalHeaderKey", Func, 0, "func(s string) string"}, {"Client", Type, 0, ""}, {"Client.CheckRedirect", Field, 0, ""}, {"Client.Jar", Field, 0, ""}, {"Client.Timeout", Field, 3, ""}, {"Client.Transport", Field, 0, ""}, {"CloseNotifier", Type, 1, ""}, {"ConnState", Type, 3, ""}, {"Cookie", Type, 0, ""}, {"Cookie.Domain", Field, 0, ""}, {"Cookie.Expires", Field, 0, ""}, {"Cookie.HttpOnly", Field, 0, ""}, {"Cookie.MaxAge", Field, 0, ""}, {"Cookie.Name", Field, 0, ""}, {"Cookie.Partitioned", Field, 23, ""}, {"Cookie.Path", Field, 0, ""}, {"Cookie.Quoted", Field, 23, ""}, {"Cookie.Raw", Field, 0, ""}, {"Cookie.RawExpires", Field, 0, ""}, {"Cookie.SameSite", Field, 11, ""}, {"Cookie.Secure", Field, 0, ""}, {"Cookie.Unparsed", Field, 0, ""}, {"Cookie.Value", Field, 0, ""}, {"CookieJar", Type, 0, ""}, {"DefaultClient", Var, 0, ""}, {"DefaultMaxHeaderBytes", Const, 0, ""}, {"DefaultMaxIdleConnsPerHost", Const, 0, ""}, {"DefaultServeMux", Var, 0, ""}, {"DefaultTransport", Var, 0, ""}, {"DetectContentType", Func, 0, "func(data []byte) string"}, {"Dir", Type, 0, ""}, {"ErrAbortHandler", Var, 8, ""}, {"ErrBodyNotAllowed", Var, 0, ""}, {"ErrBodyReadAfterClose", Var, 0, ""}, {"ErrContentLength", Var, 0, ""}, {"ErrHandlerTimeout", Var, 0, ""}, {"ErrHeaderTooLong", Var, 0, ""}, {"ErrHijacked", Var, 0, ""}, {"ErrLineTooLong", Var, 0, ""}, {"ErrMissingBoundary", Var, 0, ""}, {"ErrMissingContentLength", Var, 0, ""}, {"ErrMissingFile", Var, 0, ""}, {"ErrNoCookie", Var, 0, ""}, {"ErrNoLocation", Var, 0, ""}, {"ErrNotMultipart", Var, 0, ""}, {"ErrNotSupported", Var, 0, ""}, {"ErrSchemeMismatch", Var, 21, ""}, {"ErrServerClosed", Var, 8, ""}, {"ErrShortBody", Var, 0, ""}, {"ErrSkipAltProtocol", Var, 6, ""}, {"ErrUnexpectedTrailer", Var, 0, ""}, {"ErrUseLastResponse", Var, 7, ""}, {"ErrWriteAfterFlush", Var, 0, ""}, {"Error", Func, 0, "func(w ResponseWriter, error string, code int)"}, {"FS", Func, 16, "func(fsys fs.FS) FileSystem"}, {"File", Type, 0, ""}, {"FileServer", Func, 0, "func(root FileSystem) Handler"}, {"FileServerFS", Func, 22, "func(root fs.FS) Handler"}, {"FileSystem", Type, 0, ""}, {"Flusher", Type, 0, ""}, {"Get", Func, 0, "func(url string) (resp *Response, err error)"}, {"HTTP2Config", Type, 24, ""}, {"HTTP2Config.CountError", Field, 24, ""}, {"HTTP2Config.MaxConcurrentStreams", Field, 24, ""}, {"HTTP2Config.MaxDecoderHeaderTableSize", Field, 24, ""}, {"HTTP2Config.MaxEncoderHeaderTableSize", Field, 24, ""}, {"HTTP2Config.MaxReadFrameSize", Field, 24, ""}, {"HTTP2Config.MaxReceiveBufferPerConnection", Field, 24, ""}, {"HTTP2Config.MaxReceiveBufferPerStream", Field, 24, ""}, {"HTTP2Config.PermitProhibitedCipherSuites", Field, 24, ""}, {"HTTP2Config.PingTimeout", Field, 24, ""}, {"HTTP2Config.SendPingTimeout", Field, 24, ""}, {"HTTP2Config.WriteByteTimeout", Field, 24, ""}, {"Handle", Func, 0, "func(pattern string, handler Handler)"}, {"HandleFunc", Func, 0, "func(pattern string, handler func(ResponseWriter, *Request))"}, {"Handler", Type, 0, ""}, {"HandlerFunc", Type, 0, ""}, {"Head", Func, 0, "func(url string) (resp *Response, err error)"}, {"Header", Type, 0, ""}, {"Hijacker", Type, 0, ""}, {"ListenAndServe", Func, 0, "func(addr string, handler Handler) error"}, {"ListenAndServeTLS", Func, 0, "func(addr string, certFile string, keyFile string, handler Handler) error"}, {"LocalAddrContextKey", Var, 7, ""}, {"MaxBytesError", Type, 19, ""}, {"MaxBytesError.Limit", Field, 19, ""}, {"MaxBytesHandler", Func, 18, "func(h Handler, n int64) Handler"}, {"MaxBytesReader", Func, 0, "func(w ResponseWriter, r io.ReadCloser, n int64) io.ReadCloser"}, {"MethodConnect", Const, 6, ""}, {"MethodDelete", Const, 6, ""}, {"MethodGet", Const, 6, ""}, {"MethodHead", Const, 6, ""}, {"MethodOptions", Const, 6, ""}, {"MethodPatch", Const, 6, ""}, {"MethodPost", Const, 6, ""}, {"MethodPut", Const, 6, ""}, {"MethodTrace", Const, 6, ""}, {"NewFileTransport", Func, 0, "func(fs FileSystem) RoundTripper"}, {"NewFileTransportFS", Func, 22, "func(fsys fs.FS) RoundTripper"}, {"NewRequest", Func, 0, "func(method string, url string, body io.Reader) (*Request, error)"}, {"NewRequestWithContext", Func, 13, "func(ctx context.Context, method string, url string, body io.Reader) (*Request, error)"}, {"NewResponseController", Func, 20, "func(rw ResponseWriter) *ResponseController"}, {"NewServeMux", Func, 0, "func() *ServeMux"}, {"NoBody", Var, 8, ""}, {"NotFound", Func, 0, "func(w ResponseWriter, r *Request)"}, {"NotFoundHandler", Func, 0, "func() Handler"}, {"ParseCookie", Func, 23, "func(line string) ([]*Cookie, error)"}, {"ParseHTTPVersion", Func, 0, "func(vers string) (major int, minor int, ok bool)"}, {"ParseSetCookie", Func, 23, "func(line string) (*Cookie, error)"}, {"ParseTime", Func, 1, "func(text string) (t time.Time, err error)"}, {"Post", Func, 0, "func(url string, contentType string, body io.Reader) (resp *Response, err error)"}, {"PostForm", Func, 0, "func(url string, data url.Values) (resp *Response, err error)"}, {"ProtocolError", Type, 0, ""}, {"ProtocolError.ErrorString", Field, 0, ""}, {"Protocols", Type, 24, ""}, {"ProxyFromEnvironment", Func, 0, "func(req *Request) (*url.URL, error)"}, {"ProxyURL", Func, 0, "func(fixedURL *url.URL) func(*Request) (*url.URL, error)"}, {"PushOptions", Type, 8, ""}, {"PushOptions.Header", Field, 8, ""}, {"PushOptions.Method", Field, 8, ""}, {"Pusher", Type, 8, ""}, {"ReadRequest", Func, 0, "func(b *bufio.Reader) (*Request, error)"}, {"ReadResponse", Func, 0, "func(r *bufio.Reader, req *Request) (*Response, error)"}, {"Redirect", Func, 0, "func(w ResponseWriter, r *Request, url string, code int)"}, {"RedirectHandler", Func, 0, "func(url string, code int) Handler"}, {"Request", Type, 0, ""}, {"Request.Body", Field, 0, ""}, {"Request.Cancel", Field, 5, ""}, {"Request.Close", Field, 0, ""}, {"Request.ContentLength", Field, 0, ""}, {"Request.Form", Field, 0, ""}, {"Request.GetBody", Field, 8, ""}, {"Request.Header", Field, 0, ""}, {"Request.Host", Field, 0, ""}, {"Request.Method", Field, 0, ""}, {"Request.MultipartForm", Field, 0, ""}, {"Request.Pattern", Field, 23, ""}, {"Request.PostForm", Field, 1, ""}, {"Request.Proto", Field, 0, ""}, {"Request.ProtoMajor", Field, 0, ""}, {"Request.ProtoMinor", Field, 0, ""}, {"Request.RemoteAddr", Field, 0, ""}, {"Request.RequestURI", Field, 0, ""}, {"Request.Response", Field, 7, ""}, {"Request.TLS", Field, 0, ""}, {"Request.Trailer", Field, 0, ""}, {"Request.TransferEncoding", Field, 0, ""}, {"Request.URL", Field, 0, ""}, {"Response", Type, 0, ""}, {"Response.Body", Field, 0, ""}, {"Response.Close", Field, 0, ""}, {"Response.ContentLength", Field, 0, ""}, {"Response.Header", Field, 0, ""}, {"Response.Proto", Field, 0, ""}, {"Response.ProtoMajor", Field, 0, ""}, {"Response.ProtoMinor", Field, 0, ""}, {"Response.Request", Field, 0, ""}, {"Response.Status", Field, 0, ""}, {"Response.StatusCode", Field, 0, ""}, {"Response.TLS", Field, 3, ""}, {"Response.Trailer", Field, 0, ""}, {"Response.TransferEncoding", Field, 0, ""}, {"Response.Uncompressed", Field, 7, ""}, {"ResponseController", Type, 20, ""}, {"ResponseWriter", Type, 0, ""}, {"RoundTripper", Type, 0, ""}, {"SameSite", Type, 11, ""}, {"SameSiteDefaultMode", Const, 11, ""}, {"SameSiteLaxMode", Const, 11, ""}, {"SameSiteNoneMode", Const, 13, ""}, {"SameSiteStrictMode", Const, 11, ""}, {"Serve", Func, 0, "func(l net.Listener, handler Handler) error"}, {"ServeContent", Func, 0, "func(w ResponseWriter, req *Request, name string, modtime time.Time, content io.ReadSeeker)"}, {"ServeFile", Func, 0, "func(w ResponseWriter, r *Request, name string)"}, {"ServeFileFS", Func, 22, "func(w ResponseWriter, r *Request, fsys fs.FS, name string)"}, {"ServeMux", Type, 0, ""}, {"ServeTLS", Func, 9, "func(l net.Listener, handler Handler, certFile string, keyFile string) error"}, {"Server", Type, 0, ""}, {"Server.Addr", Field, 0, ""}, {"Server.BaseContext", Field, 13, ""}, {"Server.ConnContext", Field, 13, ""}, {"Server.ConnState", Field, 3, ""}, {"Server.DisableGeneralOptionsHandler", Field, 20, ""}, {"Server.ErrorLog", Field, 3, ""}, {"Server.HTTP2", Field, 24, ""}, {"Server.Handler", Field, 0, ""}, {"Server.IdleTimeout", Field, 8, ""}, {"Server.MaxHeaderBytes", Field, 0, ""}, {"Server.Protocols", Field, 24, ""}, {"Server.ReadHeaderTimeout", Field, 8, ""}, {"Server.ReadTimeout", Field, 0, ""}, {"Server.TLSConfig", Field, 0, ""}, {"Server.TLSNextProto", Field, 1, ""}, {"Server.WriteTimeout", Field, 0, ""}, {"ServerContextKey", Var, 7, ""}, {"SetCookie", Func, 0, "func(w ResponseWriter, cookie *Cookie)"}, {"StateActive", Const, 3, ""}, {"StateClosed", Const, 3, ""}, {"StateHijacked", Const, 3, ""}, {"StateIdle", Const, 3, ""}, {"StateNew", Const, 3, ""}, {"StatusAccepted", Const, 0, ""}, {"StatusAlreadyReported", Const, 7, ""}, {"StatusBadGateway", Const, 0, ""}, {"StatusBadRequest", Const, 0, ""}, {"StatusConflict", Const, 0, ""}, {"StatusContinue", Const, 0, ""}, {"StatusCreated", Const, 0, ""}, {"StatusEarlyHints", Const, 13, ""}, {"StatusExpectationFailed", Const, 0, ""}, {"StatusFailedDependency", Const, 7, ""}, {"StatusForbidden", Const, 0, ""}, {"StatusFound", Const, 0, ""}, {"StatusGatewayTimeout", Const, 0, ""}, {"StatusGone", Const, 0, ""}, {"StatusHTTPVersionNotSupported", Const, 0, ""}, {"StatusIMUsed", Const, 7, ""}, {"StatusInsufficientStorage", Const, 7, ""}, {"StatusInternalServerError", Const, 0, ""}, {"StatusLengthRequired", Const, 0, ""}, {"StatusLocked", Const, 7, ""}, {"StatusLoopDetected", Const, 7, ""}, {"StatusMethodNotAllowed", Const, 0, ""}, {"StatusMisdirectedRequest", Const, 11, ""}, {"StatusMovedPermanently", Const, 0, ""}, {"StatusMultiStatus", Const, 7, ""}, {"StatusMultipleChoices", Const, 0, ""}, {"StatusNetworkAuthenticationRequired", Const, 6, ""}, {"StatusNoContent", Const, 0, ""}, {"StatusNonAuthoritativeInfo", Const, 0, ""}, {"StatusNotAcceptable", Const, 0, ""}, {"StatusNotExtended", Const, 7, ""}, {"StatusNotFound", Const, 0, ""}, {"StatusNotImplemented", Const, 0, ""}, {"StatusNotModified", Const, 0, ""}, {"StatusOK", Const, 0, ""}, {"StatusPartialContent", Const, 0, ""}, {"StatusPaymentRequired", Const, 0, ""}, {"StatusPermanentRedirect", Const, 7, ""}, {"StatusPreconditionFailed", Const, 0, ""}, {"StatusPreconditionRequired", Const, 6, ""}, {"StatusProcessing", Const, 7, ""}, {"StatusProxyAuthRequired", Const, 0, ""}, {"StatusRequestEntityTooLarge", Const, 0, ""}, {"StatusRequestHeaderFieldsTooLarge", Const, 6, ""}, {"StatusRequestTimeout", Const, 0, ""}, {"StatusRequestURITooLong", Const, 0, ""}, {"StatusRequestedRangeNotSatisfiable", Const, 0, ""}, {"StatusResetContent", Const, 0, ""}, {"StatusSeeOther", Const, 0, ""}, {"StatusServiceUnavailable", Const, 0, ""}, {"StatusSwitchingProtocols", Const, 0, ""}, {"StatusTeapot", Const, 0, ""}, {"StatusTemporaryRedirect", Const, 0, ""}, {"StatusText", Func, 0, "func(code int) string"}, {"StatusTooEarly", Const, 12, ""}, {"StatusTooManyRequests", Const, 6, ""}, {"StatusUnauthorized", Const, 0, ""}, {"StatusUnavailableForLegalReasons", Const, 6, ""}, {"StatusUnprocessableEntity", Const, 7, ""}, {"StatusUnsupportedMediaType", Const, 0, ""}, {"StatusUpgradeRequired", Const, 7, ""}, {"StatusUseProxy", Const, 0, ""}, {"StatusVariantAlsoNegotiates", Const, 7, ""}, {"StripPrefix", Func, 0, "func(prefix string, h Handler) Handler"}, {"TimeFormat", Const, 0, ""}, {"TimeoutHandler", Func, 0, "func(h Handler, dt time.Duration, msg string) Handler"}, {"TrailerPrefix", Const, 8, ""}, {"Transport", Type, 0, ""}, {"Transport.Dial", Field, 0, ""}, {"Transport.DialContext", Field, 7, ""}, {"Transport.DialTLS", Field, 4, ""}, {"Transport.DialTLSContext", Field, 14, ""}, {"Transport.DisableCompression", Field, 0, ""}, {"Transport.DisableKeepAlives", Field, 0, ""}, {"Transport.ExpectContinueTimeout", Field, 6, ""}, {"Transport.ForceAttemptHTTP2", Field, 13, ""}, {"Transport.GetProxyConnectHeader", Field, 16, ""}, {"Transport.HTTP2", Field, 24, ""}, {"Transport.IdleConnTimeout", Field, 7, ""}, {"Transport.MaxConnsPerHost", Field, 11, ""}, {"Transport.MaxIdleConns", Field, 7, ""}, {"Transport.MaxIdleConnsPerHost", Field, 0, ""}, {"Transport.MaxResponseHeaderBytes", Field, 7, ""}, {"Transport.OnProxyConnectResponse", Field, 20, ""}, {"Transport.Protocols", Field, 24, ""}, {"Transport.Proxy", Field, 0, ""}, {"Transport.ProxyConnectHeader", Field, 8, ""}, {"Transport.ReadBufferSize", Field, 13, ""}, {"Transport.ResponseHeaderTimeout", Field, 1, ""}, {"Transport.TLSClientConfig", Field, 0, ""}, {"Transport.TLSHandshakeTimeout", Field, 3, ""}, {"Transport.TLSNextProto", Field, 6, ""}, {"Transport.WriteBufferSize", Field, 13, ""}, }, "net/http/cgi": { {"(*Handler).ServeHTTP", Method, 0, ""}, {"Handler", Type, 0, ""}, {"Handler.Args", Field, 0, ""}, {"Handler.Dir", Field, 0, ""}, {"Handler.Env", Field, 0, ""}, {"Handler.InheritEnv", Field, 0, ""}, {"Handler.Logger", Field, 0, ""}, {"Handler.Path", Field, 0, ""}, {"Handler.PathLocationHandler", Field, 0, ""}, {"Handler.Root", Field, 0, ""}, {"Handler.Stderr", Field, 7, ""}, {"Request", Func, 0, "func() (*http.Request, error)"}, {"RequestFromMap", Func, 0, "func(params map[string]string) (*http.Request, error)"}, {"Serve", Func, 0, "func(handler http.Handler) error"}, }, "net/http/cookiejar": { {"(*Jar).Cookies", Method, 1, ""}, {"(*Jar).SetCookies", Method, 1, ""}, {"Jar", Type, 1, ""}, {"New", Func, 1, "func(o *Options) (*Jar, error)"}, {"Options", Type, 1, ""}, {"Options.PublicSuffixList", Field, 1, ""}, {"PublicSuffixList", Type, 1, ""}, }, "net/http/fcgi": { {"ErrConnClosed", Var, 5, ""}, {"ErrRequestAborted", Var, 5, ""}, {"ProcessEnv", Func, 9, "func(r *http.Request) map[string]string"}, {"Serve", Func, 0, "func(l net.Listener, handler http.Handler) error"}, }, "net/http/httptest": { {"(*ResponseRecorder).Flush", Method, 0, ""}, {"(*ResponseRecorder).Header", Method, 0, ""}, {"(*ResponseRecorder).Result", Method, 7, ""}, {"(*ResponseRecorder).Write", Method, 0, ""}, {"(*ResponseRecorder).WriteHeader", Method, 0, ""}, {"(*ResponseRecorder).WriteString", Method, 6, ""}, {"(*Server).Certificate", Method, 9, ""}, {"(*Server).Client", Method, 9, ""}, {"(*Server).Close", Method, 0, ""}, {"(*Server).CloseClientConnections", Method, 0, ""}, {"(*Server).Start", Method, 0, ""}, {"(*Server).StartTLS", Method, 0, ""}, {"DefaultRemoteAddr", Const, 0, ""}, {"NewRecorder", Func, 0, "func() *ResponseRecorder"}, {"NewRequest", Func, 7, "func(method string, target string, body io.Reader) *http.Request"}, {"NewRequestWithContext", Func, 23, "func(ctx context.Context, method string, target string, body io.Reader) *http.Request"}, {"NewServer", Func, 0, "func(handler http.Handler) *Server"}, {"NewTLSServer", Func, 0, "func(handler http.Handler) *Server"}, {"NewUnstartedServer", Func, 0, "func(handler http.Handler) *Server"}, {"ResponseRecorder", Type, 0, ""}, {"ResponseRecorder.Body", Field, 0, ""}, {"ResponseRecorder.Code", Field, 0, ""}, {"ResponseRecorder.Flushed", Field, 0, ""}, {"ResponseRecorder.HeaderMap", Field, 0, ""}, {"Server", Type, 0, ""}, {"Server.Config", Field, 0, ""}, {"Server.EnableHTTP2", Field, 14, ""}, {"Server.Listener", Field, 0, ""}, {"Server.TLS", Field, 0, ""}, {"Server.URL", Field, 0, ""}, }, "net/http/httptrace": { {"ClientTrace", Type, 7, ""}, {"ClientTrace.ConnectDone", Field, 7, ""}, {"ClientTrace.ConnectStart", Field, 7, ""}, {"ClientTrace.DNSDone", Field, 7, ""}, {"ClientTrace.DNSStart", Field, 7, ""}, {"ClientTrace.GetConn", Field, 7, ""}, {"ClientTrace.Got100Continue", Field, 7, ""}, {"ClientTrace.Got1xxResponse", Field, 11, ""}, {"ClientTrace.GotConn", Field, 7, ""}, {"ClientTrace.GotFirstResponseByte", Field, 7, ""}, {"ClientTrace.PutIdleConn", Field, 7, ""}, {"ClientTrace.TLSHandshakeDone", Field, 8, ""}, {"ClientTrace.TLSHandshakeStart", Field, 8, ""}, {"ClientTrace.Wait100Continue", Field, 7, ""}, {"ClientTrace.WroteHeaderField", Field, 11, ""}, {"ClientTrace.WroteHeaders", Field, 7, ""}, {"ClientTrace.WroteRequest", Field, 7, ""}, {"ContextClientTrace", Func, 7, "func(ctx context.Context) *ClientTrace"}, {"DNSDoneInfo", Type, 7, ""}, {"DNSDoneInfo.Addrs", Field, 7, ""}, {"DNSDoneInfo.Coalesced", Field, 7, ""}, {"DNSDoneInfo.Err", Field, 7, ""}, {"DNSStartInfo", Type, 7, ""}, {"DNSStartInfo.Host", Field, 7, ""}, {"GotConnInfo", Type, 7, ""}, {"GotConnInfo.Conn", Field, 7, ""}, {"GotConnInfo.IdleTime", Field, 7, ""}, {"GotConnInfo.Reused", Field, 7, ""}, {"GotConnInfo.WasIdle", Field, 7, ""}, {"WithClientTrace", Func, 7, "func(ctx context.Context, trace *ClientTrace) context.Context"}, {"WroteRequestInfo", Type, 7, ""}, {"WroteRequestInfo.Err", Field, 7, ""}, }, "net/http/httputil": { {"(*ClientConn).Close", Method, 0, ""}, {"(*ClientConn).Do", Method, 0, ""}, {"(*ClientConn).Hijack", Method, 0, ""}, {"(*ClientConn).Pending", Method, 0, ""}, {"(*ClientConn).Read", Method, 0, ""}, {"(*ClientConn).Write", Method, 0, ""}, {"(*ProxyRequest).SetURL", Method, 20, ""}, {"(*ProxyRequest).SetXForwarded", Method, 20, ""}, {"(*ReverseProxy).ServeHTTP", Method, 0, ""}, {"(*ServerConn).Close", Method, 0, ""}, {"(*ServerConn).Hijack", Method, 0, ""}, {"(*ServerConn).Pending", Method, 0, ""}, {"(*ServerConn).Read", Method, 0, ""}, {"(*ServerConn).Write", Method, 0, ""}, {"BufferPool", Type, 6, ""}, {"ClientConn", Type, 0, ""}, {"DumpRequest", Func, 0, "func(req *http.Request, body bool) ([]byte, error)"}, {"DumpRequestOut", Func, 0, "func(req *http.Request, body bool) ([]byte, error)"}, {"DumpResponse", Func, 0, "func(resp *http.Response, body bool) ([]byte, error)"}, {"ErrClosed", Var, 0, ""}, {"ErrLineTooLong", Var, 0, ""}, {"ErrPersistEOF", Var, 0, ""}, {"ErrPipeline", Var, 0, ""}, {"NewChunkedReader", Func, 0, "func(r io.Reader) io.Reader"}, {"NewChunkedWriter", Func, 0, "func(w io.Writer) io.WriteCloser"}, {"NewClientConn", Func, 0, "func(c net.Conn, r *bufio.Reader) *ClientConn"}, {"NewProxyClientConn", Func, 0, "func(c net.Conn, r *bufio.Reader) *ClientConn"}, {"NewServerConn", Func, 0, "func(c net.Conn, r *bufio.Reader) *ServerConn"}, {"NewSingleHostReverseProxy", Func, 0, "func(target *url.URL) *ReverseProxy"}, {"ProxyRequest", Type, 20, ""}, {"ProxyRequest.In", Field, 20, ""}, {"ProxyRequest.Out", Field, 20, ""}, {"ReverseProxy", Type, 0, ""}, {"ReverseProxy.BufferPool", Field, 6, ""}, {"ReverseProxy.Director", Field, 0, ""}, {"ReverseProxy.ErrorHandler", Field, 11, ""}, {"ReverseProxy.ErrorLog", Field, 4, ""}, {"ReverseProxy.FlushInterval", Field, 0, ""}, {"ReverseProxy.ModifyResponse", Field, 8, ""}, {"ReverseProxy.Rewrite", Field, 20, ""}, {"ReverseProxy.Transport", Field, 0, ""}, {"ServerConn", Type, 0, ""}, }, "net/http/pprof": { {"Cmdline", Func, 0, "func(w http.ResponseWriter, r *http.Request)"}, {"Handler", Func, 0, "func(name string) http.Handler"}, {"Index", Func, 0, "func(w http.ResponseWriter, r *http.Request)"}, {"Profile", Func, 0, "func(w http.ResponseWriter, r *http.Request)"}, {"Symbol", Func, 0, "func(w http.ResponseWriter, r *http.Request)"}, {"Trace", Func, 5, "func(w http.ResponseWriter, r *http.Request)"}, }, "net/mail": { {"(*Address).String", Method, 0, ""}, {"(*AddressParser).Parse", Method, 5, ""}, {"(*AddressParser).ParseList", Method, 5, ""}, {"(Header).AddressList", Method, 0, ""}, {"(Header).Date", Method, 0, ""}, {"(Header).Get", Method, 0, ""}, {"Address", Type, 0, ""}, {"Address.Address", Field, 0, ""}, {"Address.Name", Field, 0, ""}, {"AddressParser", Type, 5, ""}, {"AddressParser.WordDecoder", Field, 5, ""}, {"ErrHeaderNotPresent", Var, 0, ""}, {"Header", Type, 0, ""}, {"Message", Type, 0, ""}, {"Message.Body", Field, 0, ""}, {"Message.Header", Field, 0, ""}, {"ParseAddress", Func, 1, "func(address string) (*Address, error)"}, {"ParseAddressList", Func, 1, "func(list string) ([]*Address, error)"}, {"ParseDate", Func, 8, "func(date string) (time.Time, error)"}, {"ReadMessage", Func, 0, "func(r io.Reader) (msg *Message, err error)"}, }, "net/netip": { {"(*Addr).UnmarshalBinary", Method, 18, ""}, {"(*Addr).UnmarshalText", Method, 18, ""}, {"(*AddrPort).UnmarshalBinary", Method, 18, ""}, {"(*AddrPort).UnmarshalText", Method, 18, ""}, {"(*Prefix).UnmarshalBinary", Method, 18, ""}, {"(*Prefix).UnmarshalText", Method, 18, ""}, {"(Addr).AppendBinary", Method, 24, ""}, {"(Addr).AppendText", Method, 24, ""}, {"(Addr).AppendTo", Method, 18, ""}, {"(Addr).As16", Method, 18, ""}, {"(Addr).As4", Method, 18, ""}, {"(Addr).AsSlice", Method, 18, ""}, {"(Addr).BitLen", Method, 18, ""}, {"(Addr).Compare", Method, 18, ""}, {"(Addr).Is4", Method, 18, ""}, {"(Addr).Is4In6", Method, 18, ""}, {"(Addr).Is6", Method, 18, ""}, {"(Addr).IsGlobalUnicast", Method, 18, ""}, {"(Addr).IsInterfaceLocalMulticast", Method, 18, ""}, {"(Addr).IsLinkLocalMulticast", Method, 18, ""}, {"(Addr).IsLinkLocalUnicast", Method, 18, ""}, {"(Addr).IsLoopback", Method, 18, ""}, {"(Addr).IsMulticast", Method, 18, ""}, {"(Addr).IsPrivate", Method, 18, ""}, {"(Addr).IsUnspecified", Method, 18, ""}, {"(Addr).IsValid", Method, 18, ""}, {"(Addr).Less", Method, 18, ""}, {"(Addr).MarshalBinary", Method, 18, ""}, {"(Addr).MarshalText", Method, 18, ""}, {"(Addr).Next", Method, 18, ""}, {"(Addr).Prefix", Method, 18, ""}, {"(Addr).Prev", Method, 18, ""}, {"(Addr).String", Method, 18, ""}, {"(Addr).StringExpanded", Method, 18, ""}, {"(Addr).Unmap", Method, 18, ""}, {"(Addr).WithZone", Method, 18, ""}, {"(Addr).Zone", Method, 18, ""}, {"(AddrPort).Addr", Method, 18, ""}, {"(AddrPort).AppendBinary", Method, 24, ""}, {"(AddrPort).AppendText", Method, 24, ""}, {"(AddrPort).AppendTo", Method, 18, ""}, {"(AddrPort).Compare", Method, 22, ""}, {"(AddrPort).IsValid", Method, 18, ""}, {"(AddrPort).MarshalBinary", Method, 18, ""}, {"(AddrPort).MarshalText", Method, 18, ""}, {"(AddrPort).Port", Method, 18, ""}, {"(AddrPort).String", Method, 18, ""}, {"(Prefix).Addr", Method, 18, ""}, {"(Prefix).AppendBinary", Method, 24, ""}, {"(Prefix).AppendText", Method, 24, ""}, {"(Prefix).AppendTo", Method, 18, ""}, {"(Prefix).Bits", Method, 18, ""}, {"(Prefix).Contains", Method, 18, ""}, {"(Prefix).IsSingleIP", Method, 18, ""}, {"(Prefix).IsValid", Method, 18, ""}, {"(Prefix).MarshalBinary", Method, 18, ""}, {"(Prefix).MarshalText", Method, 18, ""}, {"(Prefix).Masked", Method, 18, ""}, {"(Prefix).Overlaps", Method, 18, ""}, {"(Prefix).String", Method, 18, ""}, {"Addr", Type, 18, ""}, {"AddrFrom16", Func, 18, "func(addr [16]byte) Addr"}, {"AddrFrom4", Func, 18, "func(addr [4]byte) Addr"}, {"AddrFromSlice", Func, 18, "func(slice []byte) (ip Addr, ok bool)"}, {"AddrPort", Type, 18, ""}, {"AddrPortFrom", Func, 18, "func(ip Addr, port uint16) AddrPort"}, {"IPv4Unspecified", Func, 18, "func() Addr"}, {"IPv6LinkLocalAllNodes", Func, 18, "func() Addr"}, {"IPv6LinkLocalAllRouters", Func, 20, "func() Addr"}, {"IPv6Loopback", Func, 20, "func() Addr"}, {"IPv6Unspecified", Func, 18, "func() Addr"}, {"MustParseAddr", Func, 18, "func(s string) Addr"}, {"MustParseAddrPort", Func, 18, "func(s string) AddrPort"}, {"MustParsePrefix", Func, 18, "func(s string) Prefix"}, {"ParseAddr", Func, 18, "func(s string) (Addr, error)"}, {"ParseAddrPort", Func, 18, "func(s string) (AddrPort, error)"}, {"ParsePrefix", Func, 18, "func(s string) (Prefix, error)"}, {"Prefix", Type, 18, ""}, {"PrefixFrom", Func, 18, "func(ip Addr, bits int) Prefix"}, }, "net/rpc": { {"(*Client).Call", Method, 0, ""}, {"(*Client).Close", Method, 0, ""}, {"(*Client).Go", Method, 0, ""}, {"(*Server).Accept", Method, 0, ""}, {"(*Server).HandleHTTP", Method, 0, ""}, {"(*Server).Register", Method, 0, ""}, {"(*Server).RegisterName", Method, 0, ""}, {"(*Server).ServeCodec", Method, 0, ""}, {"(*Server).ServeConn", Method, 0, ""}, {"(*Server).ServeHTTP", Method, 0, ""}, {"(*Server).ServeRequest", Method, 0, ""}, {"(ServerError).Error", Method, 0, ""}, {"Accept", Func, 0, "func(lis net.Listener)"}, {"Call", Type, 0, ""}, {"Call.Args", Field, 0, ""}, {"Call.Done", Field, 0, ""}, {"Call.Error", Field, 0, ""}, {"Call.Reply", Field, 0, ""}, {"Call.ServiceMethod", Field, 0, ""}, {"Client", Type, 0, ""}, {"ClientCodec", Type, 0, ""}, {"DefaultDebugPath", Const, 0, ""}, {"DefaultRPCPath", Const, 0, ""}, {"DefaultServer", Var, 0, ""}, {"Dial", Func, 0, "func(network string, address string) (*Client, error)"}, {"DialHTTP", Func, 0, "func(network string, address string) (*Client, error)"}, {"DialHTTPPath", Func, 0, "func(network string, address string, path string) (*Client, error)"}, {"ErrShutdown", Var, 0, ""}, {"HandleHTTP", Func, 0, "func()"}, {"NewClient", Func, 0, "func(conn io.ReadWriteCloser) *Client"}, {"NewClientWithCodec", Func, 0, "func(codec ClientCodec) *Client"}, {"NewServer", Func, 0, "func() *Server"}, {"Register", Func, 0, "func(rcvr any) error"}, {"RegisterName", Func, 0, "func(name string, rcvr any) error"}, {"Request", Type, 0, ""}, {"Request.Seq", Field, 0, ""}, {"Request.ServiceMethod", Field, 0, ""}, {"Response", Type, 0, ""}, {"Response.Error", Field, 0, ""}, {"Response.Seq", Field, 0, ""}, {"Response.ServiceMethod", Field, 0, ""}, {"ServeCodec", Func, 0, "func(codec ServerCodec)"}, {"ServeConn", Func, 0, "func(conn io.ReadWriteCloser)"}, {"ServeRequest", Func, 0, "func(codec ServerCodec) error"}, {"Server", Type, 0, ""}, {"ServerCodec", Type, 0, ""}, {"ServerError", Type, 0, ""}, }, "net/rpc/jsonrpc": { {"Dial", Func, 0, "func(network string, address string) (*rpc.Client, error)"}, {"NewClient", Func, 0, "func(conn io.ReadWriteCloser) *rpc.Client"}, {"NewClientCodec", Func, 0, "func(conn io.ReadWriteCloser) rpc.ClientCodec"}, {"NewServerCodec", Func, 0, "func(conn io.ReadWriteCloser) rpc.ServerCodec"}, {"ServeConn", Func, 0, "func(conn io.ReadWriteCloser)"}, }, "net/smtp": { {"(*Client).Auth", Method, 0, ""}, {"(*Client).Close", Method, 2, ""}, {"(*Client).Data", Method, 0, ""}, {"(*Client).Extension", Method, 0, ""}, {"(*Client).Hello", Method, 1, ""}, {"(*Client).Mail", Method, 0, ""}, {"(*Client).Noop", Method, 10, ""}, {"(*Client).Quit", Method, 0, ""}, {"(*Client).Rcpt", Method, 0, ""}, {"(*Client).Reset", Method, 0, ""}, {"(*Client).StartTLS", Method, 0, ""}, {"(*Client).TLSConnectionState", Method, 5, ""}, {"(*Client).Verify", Method, 0, ""}, {"Auth", Type, 0, ""}, {"CRAMMD5Auth", Func, 0, "func(username string, secret string) Auth"}, {"Client", Type, 0, ""}, {"Client.Text", Field, 0, ""}, {"Dial", Func, 0, "func(addr string) (*Client, error)"}, {"NewClient", Func, 0, "func(conn net.Conn, host string) (*Client, error)"}, {"PlainAuth", Func, 0, "func(identity string, username string, password string, host string) Auth"}, {"SendMail", Func, 0, "func(addr string, a Auth, from string, to []string, msg []byte) error"}, {"ServerInfo", Type, 0, ""}, {"ServerInfo.Auth", Field, 0, ""}, {"ServerInfo.Name", Field, 0, ""}, {"ServerInfo.TLS", Field, 0, ""}, }, "net/textproto": { {"(*Conn).Close", Method, 0, ""}, {"(*Conn).Cmd", Method, 0, ""}, {"(*Conn).DotReader", Method, 0, ""}, {"(*Conn).DotWriter", Method, 0, ""}, {"(*Conn).EndRequest", Method, 0, ""}, {"(*Conn).EndResponse", Method, 0, ""}, {"(*Conn).Next", Method, 0, ""}, {"(*Conn).PrintfLine", Method, 0, ""}, {"(*Conn).ReadCodeLine", Method, 0, ""}, {"(*Conn).ReadContinuedLine", Method, 0, ""}, {"(*Conn).ReadContinuedLineBytes", Method, 0, ""}, {"(*Conn).ReadDotBytes", Method, 0, ""}, {"(*Conn).ReadDotLines", Method, 0, ""}, {"(*Conn).ReadLine", Method, 0, ""}, {"(*Conn).ReadLineBytes", Method, 0, ""}, {"(*Conn).ReadMIMEHeader", Method, 0, ""}, {"(*Conn).ReadResponse", Method, 0, ""}, {"(*Conn).StartRequest", Method, 0, ""}, {"(*Conn).StartResponse", Method, 0, ""}, {"(*Error).Error", Method, 0, ""}, {"(*Pipeline).EndRequest", Method, 0, ""}, {"(*Pipeline).EndResponse", Method, 0, ""}, {"(*Pipeline).Next", Method, 0, ""}, {"(*Pipeline).StartRequest", Method, 0, ""}, {"(*Pipeline).StartResponse", Method, 0, ""}, {"(*Reader).DotReader", Method, 0, ""}, {"(*Reader).ReadCodeLine", Method, 0, ""}, {"(*Reader).ReadContinuedLine", Method, 0, ""}, {"(*Reader).ReadContinuedLineBytes", Method, 0, ""}, {"(*Reader).ReadDotBytes", Method, 0, ""}, {"(*Reader).ReadDotLines", Method, 0, ""}, {"(*Reader).ReadLine", Method, 0, ""}, {"(*Reader).ReadLineBytes", Method, 0, ""}, {"(*Reader).ReadMIMEHeader", Method, 0, ""}, {"(*Reader).ReadResponse", Method, 0, ""}, {"(*Writer).DotWriter", Method, 0, ""}, {"(*Writer).PrintfLine", Method, 0, ""}, {"(MIMEHeader).Add", Method, 0, ""}, {"(MIMEHeader).Del", Method, 0, ""}, {"(MIMEHeader).Get", Method, 0, ""}, {"(MIMEHeader).Set", Method, 0, ""}, {"(MIMEHeader).Values", Method, 14, ""}, {"(ProtocolError).Error", Method, 0, ""}, {"CanonicalMIMEHeaderKey", Func, 0, "func(s string) string"}, {"Conn", Type, 0, ""}, {"Conn.Pipeline", Field, 0, ""}, {"Conn.Reader", Field, 0, ""}, {"Conn.Writer", Field, 0, ""}, {"Dial", Func, 0, "func(network string, addr string) (*Conn, error)"}, {"Error", Type, 0, ""}, {"Error.Code", Field, 0, ""}, {"Error.Msg", Field, 0, ""}, {"MIMEHeader", Type, 0, ""}, {"NewConn", Func, 0, "func(conn io.ReadWriteCloser) *Conn"}, {"NewReader", Func, 0, "func(r *bufio.Reader) *Reader"}, {"NewWriter", Func, 0, "func(w *bufio.Writer) *Writer"}, {"Pipeline", Type, 0, ""}, {"ProtocolError", Type, 0, ""}, {"Reader", Type, 0, ""}, {"Reader.R", Field, 0, ""}, {"TrimBytes", Func, 1, "func(b []byte) []byte"}, {"TrimString", Func, 1, "func(s string) string"}, {"Writer", Type, 0, ""}, {"Writer.W", Field, 0, ""}, }, "net/url": { {"(*Error).Error", Method, 0, ""}, {"(*Error).Temporary", Method, 6, ""}, {"(*Error).Timeout", Method, 6, ""}, {"(*Error).Unwrap", Method, 13, ""}, {"(*URL).AppendBinary", Method, 24, ""}, {"(*URL).EscapedFragment", Method, 15, ""}, {"(*URL).EscapedPath", Method, 5, ""}, {"(*URL).Hostname", Method, 8, ""}, {"(*URL).IsAbs", Method, 0, ""}, {"(*URL).JoinPath", Method, 19, ""}, {"(*URL).MarshalBinary", Method, 8, ""}, {"(*URL).Parse", Method, 0, ""}, {"(*URL).Port", Method, 8, ""}, {"(*URL).Query", Method, 0, ""}, {"(*URL).Redacted", Method, 15, ""}, {"(*URL).RequestURI", Method, 0, ""}, {"(*URL).ResolveReference", Method, 0, ""}, {"(*URL).String", Method, 0, ""}, {"(*URL).UnmarshalBinary", Method, 8, ""}, {"(*Userinfo).Password", Method, 0, ""}, {"(*Userinfo).String", Method, 0, ""}, {"(*Userinfo).Username", Method, 0, ""}, {"(EscapeError).Error", Method, 0, ""}, {"(InvalidHostError).Error", Method, 6, ""}, {"(Values).Add", Method, 0, ""}, {"(Values).Del", Method, 0, ""}, {"(Values).Encode", Method, 0, ""}, {"(Values).Get", Method, 0, ""}, {"(Values).Has", Method, 17, ""}, {"(Values).Set", Method, 0, ""}, {"Error", Type, 0, ""}, {"Error.Err", Field, 0, ""}, {"Error.Op", Field, 0, ""}, {"Error.URL", Field, 0, ""}, {"EscapeError", Type, 0, ""}, {"InvalidHostError", Type, 6, ""}, {"JoinPath", Func, 19, "func(base string, elem ...string) (result string, err error)"}, {"Parse", Func, 0, "func(rawURL string) (*URL, error)"}, {"ParseQuery", Func, 0, "func(query string) (Values, error)"}, {"ParseRequestURI", Func, 0, "func(rawURL string) (*URL, error)"}, {"PathEscape", Func, 8, "func(s string) string"}, {"PathUnescape", Func, 8, "func(s string) (string, error)"}, {"QueryEscape", Func, 0, "func(s string) string"}, {"QueryUnescape", Func, 0, "func(s string) (string, error)"}, {"URL", Type, 0, ""}, {"URL.ForceQuery", Field, 7, ""}, {"URL.Fragment", Field, 0, ""}, {"URL.Host", Field, 0, ""}, {"URL.OmitHost", Field, 19, ""}, {"URL.Opaque", Field, 0, ""}, {"URL.Path", Field, 0, ""}, {"URL.RawFragment", Field, 15, ""}, {"URL.RawPath", Field, 5, ""}, {"URL.RawQuery", Field, 0, ""}, {"URL.Scheme", Field, 0, ""}, {"URL.User", Field, 0, ""}, {"User", Func, 0, "func(username string) *Userinfo"}, {"UserPassword", Func, 0, "func(username string, password string) *Userinfo"}, {"Userinfo", Type, 0, ""}, {"Values", Type, 0, ""}, }, "os": { {"(*File).Chdir", Method, 0, ""}, {"(*File).Chmod", Method, 0, ""}, {"(*File).Chown", Method, 0, ""}, {"(*File).Close", Method, 0, ""}, {"(*File).Fd", Method, 0, ""}, {"(*File).Name", Method, 0, ""}, {"(*File).Read", Method, 0, ""}, {"(*File).ReadAt", Method, 0, ""}, {"(*File).ReadDir", Method, 16, ""}, {"(*File).ReadFrom", Method, 15, ""}, {"(*File).Readdir", Method, 0, ""}, {"(*File).Readdirnames", Method, 0, ""}, {"(*File).Seek", Method, 0, ""}, {"(*File).SetDeadline", Method, 10, ""}, {"(*File).SetReadDeadline", Method, 10, ""}, {"(*File).SetWriteDeadline", Method, 10, ""}, {"(*File).Stat", Method, 0, ""}, {"(*File).Sync", Method, 0, ""}, {"(*File).SyscallConn", Method, 12, ""}, {"(*File).Truncate", Method, 0, ""}, {"(*File).Write", Method, 0, ""}, {"(*File).WriteAt", Method, 0, ""}, {"(*File).WriteString", Method, 0, ""}, {"(*File).WriteTo", Method, 22, ""}, {"(*LinkError).Error", Method, 0, ""}, {"(*LinkError).Unwrap", Method, 13, ""}, {"(*PathError).Error", Method, 0, ""}, {"(*PathError).Timeout", Method, 10, ""}, {"(*PathError).Unwrap", Method, 13, ""}, {"(*Process).Kill", Method, 0, ""}, {"(*Process).Release", Method, 0, ""}, {"(*Process).Signal", Method, 0, ""}, {"(*Process).Wait", Method, 0, ""}, {"(*ProcessState).ExitCode", Method, 12, ""}, {"(*ProcessState).Exited", Method, 0, ""}, {"(*ProcessState).Pid", Method, 0, ""}, {"(*ProcessState).String", Method, 0, ""}, {"(*ProcessState).Success", Method, 0, ""}, {"(*ProcessState).Sys", Method, 0, ""}, {"(*ProcessState).SysUsage", Method, 0, ""}, {"(*ProcessState).SystemTime", Method, 0, ""}, {"(*ProcessState).UserTime", Method, 0, ""}, {"(*Root).Chmod", Method, 25, ""}, {"(*Root).Chown", Method, 25, ""}, {"(*Root).Chtimes", Method, 25, ""}, {"(*Root).Close", Method, 24, ""}, {"(*Root).Create", Method, 24, ""}, {"(*Root).FS", Method, 24, ""}, {"(*Root).Lchown", Method, 25, ""}, {"(*Root).Link", Method, 25, ""}, {"(*Root).Lstat", Method, 24, ""}, {"(*Root).Mkdir", Method, 24, ""}, {"(*Root).Name", Method, 24, ""}, {"(*Root).Open", Method, 24, ""}, {"(*Root).OpenFile", Method, 24, ""}, {"(*Root).OpenRoot", Method, 24, ""}, {"(*Root).Readlink", Method, 25, ""}, {"(*Root).Remove", Method, 24, ""}, {"(*Root).Rename", Method, 25, ""}, {"(*Root).Stat", Method, 24, ""}, {"(*Root).Symlink", Method, 25, ""}, {"(*SyscallError).Error", Method, 0, ""}, {"(*SyscallError).Timeout", Method, 10, ""}, {"(*SyscallError).Unwrap", Method, 13, ""}, {"(FileMode).IsDir", Method, 0, ""}, {"(FileMode).IsRegular", Method, 1, ""}, {"(FileMode).Perm", Method, 0, ""}, {"(FileMode).String", Method, 0, ""}, {"Args", Var, 0, ""}, {"Chdir", Func, 0, "func(dir string) error"}, {"Chmod", Func, 0, "func(name string, mode FileMode) error"}, {"Chown", Func, 0, "func(name string, uid int, gid int) error"}, {"Chtimes", Func, 0, "func(name string, atime time.Time, mtime time.Time) error"}, {"Clearenv", Func, 0, "func()"}, {"CopyFS", Func, 23, "func(dir string, fsys fs.FS) error"}, {"Create", Func, 0, "func(name string) (*File, error)"}, {"CreateTemp", Func, 16, "func(dir string, pattern string) (*File, error)"}, {"DevNull", Const, 0, ""}, {"DirEntry", Type, 16, ""}, {"DirFS", Func, 16, "func(dir string) fs.FS"}, {"Environ", Func, 0, "func() []string"}, {"ErrClosed", Var, 8, ""}, {"ErrDeadlineExceeded", Var, 15, ""}, {"ErrExist", Var, 0, ""}, {"ErrInvalid", Var, 0, ""}, {"ErrNoDeadline", Var, 10, ""}, {"ErrNotExist", Var, 0, ""}, {"ErrPermission", Var, 0, ""}, {"ErrProcessDone", Var, 16, ""}, {"Executable", Func, 8, "func() (string, error)"}, {"Exit", Func, 0, "func(code int)"}, {"Expand", Func, 0, "func(s string, mapping func(string) string) string"}, {"ExpandEnv", Func, 0, "func(s string) string"}, {"File", Type, 0, ""}, {"FileInfo", Type, 0, ""}, {"FileMode", Type, 0, ""}, {"FindProcess", Func, 0, "func(pid int) (*Process, error)"}, {"Getegid", Func, 0, "func() int"}, {"Getenv", Func, 0, "func(key string) string"}, {"Geteuid", Func, 0, "func() int"}, {"Getgid", Func, 0, "func() int"}, {"Getgroups", Func, 0, "func() ([]int, error)"}, {"Getpagesize", Func, 0, "func() int"}, {"Getpid", Func, 0, "func() int"}, {"Getppid", Func, 0, "func() int"}, {"Getuid", Func, 0, "func() int"}, {"Getwd", Func, 0, "func() (dir string, err error)"}, {"Hostname", Func, 0, "func() (name string, err error)"}, {"Interrupt", Var, 0, ""}, {"IsExist", Func, 0, "func(err error) bool"}, {"IsNotExist", Func, 0, "func(err error) bool"}, {"IsPathSeparator", Func, 0, "func(c uint8) bool"}, {"IsPermission", Func, 0, "func(err error) bool"}, {"IsTimeout", Func, 10, "func(err error) bool"}, {"Kill", Var, 0, ""}, {"Lchown", Func, 0, "func(name string, uid int, gid int) error"}, {"Link", Func, 0, "func(oldname string, newname string) error"}, {"LinkError", Type, 0, ""}, {"LinkError.Err", Field, 0, ""}, {"LinkError.New", Field, 0, ""}, {"LinkError.Old", Field, 0, ""}, {"LinkError.Op", Field, 0, ""}, {"LookupEnv", Func, 5, "func(key string) (string, bool)"}, {"Lstat", Func, 0, "func(name string) (FileInfo, error)"}, {"Mkdir", Func, 0, "func(name string, perm FileMode) error"}, {"MkdirAll", Func, 0, "func(path string, perm FileMode) error"}, {"MkdirTemp", Func, 16, "func(dir string, pattern string) (string, error)"}, {"ModeAppend", Const, 0, ""}, {"ModeCharDevice", Const, 0, ""}, {"ModeDevice", Const, 0, ""}, {"ModeDir", Const, 0, ""}, {"ModeExclusive", Const, 0, ""}, {"ModeIrregular", Const, 11, ""}, {"ModeNamedPipe", Const, 0, ""}, {"ModePerm", Const, 0, ""}, {"ModeSetgid", Const, 0, ""}, {"ModeSetuid", Const, 0, ""}, {"ModeSocket", Const, 0, ""}, {"ModeSticky", Const, 0, ""}, {"ModeSymlink", Const, 0, ""}, {"ModeTemporary", Const, 0, ""}, {"ModeType", Const, 0, ""}, {"NewFile", Func, 0, "func(fd uintptr, name string) *File"}, {"NewSyscallError", Func, 0, "func(syscall string, err error) error"}, {"O_APPEND", Const, 0, ""}, {"O_CREATE", Const, 0, ""}, {"O_EXCL", Const, 0, ""}, {"O_RDONLY", Const, 0, ""}, {"O_RDWR", Const, 0, ""}, {"O_SYNC", Const, 0, ""}, {"O_TRUNC", Const, 0, ""}, {"O_WRONLY", Const, 0, ""}, {"Open", Func, 0, "func(name string) (*File, error)"}, {"OpenFile", Func, 0, "func(name string, flag int, perm FileMode) (*File, error)"}, {"OpenInRoot", Func, 24, "func(dir string, name string) (*File, error)"}, {"OpenRoot", Func, 24, "func(name string) (*Root, error)"}, {"PathError", Type, 0, ""}, {"PathError.Err", Field, 0, ""}, {"PathError.Op", Field, 0, ""}, {"PathError.Path", Field, 0, ""}, {"PathListSeparator", Const, 0, ""}, {"PathSeparator", Const, 0, ""}, {"Pipe", Func, 0, "func() (r *File, w *File, err error)"}, {"ProcAttr", Type, 0, ""}, {"ProcAttr.Dir", Field, 0, ""}, {"ProcAttr.Env", Field, 0, ""}, {"ProcAttr.Files", Field, 0, ""}, {"ProcAttr.Sys", Field, 0, ""}, {"Process", Type, 0, ""}, {"Process.Pid", Field, 0, ""}, {"ProcessState", Type, 0, ""}, {"ReadDir", Func, 16, "func(name string) ([]DirEntry, error)"}, {"ReadFile", Func, 16, "func(name string) ([]byte, error)"}, {"Readlink", Func, 0, "func(name string) (string, error)"}, {"Remove", Func, 0, "func(name string) error"}, {"RemoveAll", Func, 0, "func(path string) error"}, {"Rename", Func, 0, "func(oldpath string, newpath string) error"}, {"Root", Type, 24, ""}, {"SEEK_CUR", Const, 0, ""}, {"SEEK_END", Const, 0, ""}, {"SEEK_SET", Const, 0, ""}, {"SameFile", Func, 0, "func(fi1 FileInfo, fi2 FileInfo) bool"}, {"Setenv", Func, 0, "func(key string, value string) error"}, {"Signal", Type, 0, ""}, {"StartProcess", Func, 0, "func(name string, argv []string, attr *ProcAttr) (*Process, error)"}, {"Stat", Func, 0, "func(name string) (FileInfo, error)"}, {"Stderr", Var, 0, ""}, {"Stdin", Var, 0, ""}, {"Stdout", Var, 0, ""}, {"Symlink", Func, 0, "func(oldname string, newname string) error"}, {"SyscallError", Type, 0, ""}, {"SyscallError.Err", Field, 0, ""}, {"SyscallError.Syscall", Field, 0, ""}, {"TempDir", Func, 0, "func() string"}, {"Truncate", Func, 0, "func(name string, size int64) error"}, {"Unsetenv", Func, 4, "func(key string) error"}, {"UserCacheDir", Func, 11, "func() (string, error)"}, {"UserConfigDir", Func, 13, "func() (string, error)"}, {"UserHomeDir", Func, 12, "func() (string, error)"}, {"WriteFile", Func, 16, "func(name string, data []byte, perm FileMode) error"}, }, "os/exec": { {"(*Cmd).CombinedOutput", Method, 0, ""}, {"(*Cmd).Environ", Method, 19, ""}, {"(*Cmd).Output", Method, 0, ""}, {"(*Cmd).Run", Method, 0, ""}, {"(*Cmd).Start", Method, 0, ""}, {"(*Cmd).StderrPipe", Method, 0, ""}, {"(*Cmd).StdinPipe", Method, 0, ""}, {"(*Cmd).StdoutPipe", Method, 0, ""}, {"(*Cmd).String", Method, 13, ""}, {"(*Cmd).Wait", Method, 0, ""}, {"(*Error).Error", Method, 0, ""}, {"(*Error).Unwrap", Method, 13, ""}, {"(*ExitError).Error", Method, 0, ""}, {"(ExitError).ExitCode", Method, 12, ""}, {"(ExitError).Exited", Method, 0, ""}, {"(ExitError).Pid", Method, 0, ""}, {"(ExitError).String", Method, 0, ""}, {"(ExitError).Success", Method, 0, ""}, {"(ExitError).Sys", Method, 0, ""}, {"(ExitError).SysUsage", Method, 0, ""}, {"(ExitError).SystemTime", Method, 0, ""}, {"(ExitError).UserTime", Method, 0, ""}, {"Cmd", Type, 0, ""}, {"Cmd.Args", Field, 0, ""}, {"Cmd.Cancel", Field, 20, ""}, {"Cmd.Dir", Field, 0, ""}, {"Cmd.Env", Field, 0, ""}, {"Cmd.Err", Field, 19, ""}, {"Cmd.ExtraFiles", Field, 0, ""}, {"Cmd.Path", Field, 0, ""}, {"Cmd.Process", Field, 0, ""}, {"Cmd.ProcessState", Field, 0, ""}, {"Cmd.Stderr", Field, 0, ""}, {"Cmd.Stdin", Field, 0, ""}, {"Cmd.Stdout", Field, 0, ""}, {"Cmd.SysProcAttr", Field, 0, ""}, {"Cmd.WaitDelay", Field, 20, ""}, {"Command", Func, 0, "func(name string, arg ...string) *Cmd"}, {"CommandContext", Func, 7, "func(ctx context.Context, name string, arg ...string) *Cmd"}, {"ErrDot", Var, 19, ""}, {"ErrNotFound", Var, 0, ""}, {"ErrWaitDelay", Var, 20, ""}, {"Error", Type, 0, ""}, {"Error.Err", Field, 0, ""}, {"Error.Name", Field, 0, ""}, {"ExitError", Type, 0, ""}, {"ExitError.ProcessState", Field, 0, ""}, {"ExitError.Stderr", Field, 6, ""}, {"LookPath", Func, 0, "func(file string) (string, error)"}, }, "os/signal": { {"Ignore", Func, 5, "func(sig ...os.Signal)"}, {"Ignored", Func, 11, "func(sig os.Signal) bool"}, {"Notify", Func, 0, "func(c chan<- os.Signal, sig ...os.Signal)"}, {"NotifyContext", Func, 16, "func(parent context.Context, signals ...os.Signal) (ctx context.Context, stop context.CancelFunc)"}, {"Reset", Func, 5, "func(sig ...os.Signal)"}, {"Stop", Func, 1, "func(c chan<- os.Signal)"}, }, "os/user": { {"(*User).GroupIds", Method, 7, ""}, {"(UnknownGroupError).Error", Method, 7, ""}, {"(UnknownGroupIdError).Error", Method, 7, ""}, {"(UnknownUserError).Error", Method, 0, ""}, {"(UnknownUserIdError).Error", Method, 0, ""}, {"Current", Func, 0, "func() (*User, error)"}, {"Group", Type, 7, ""}, {"Group.Gid", Field, 7, ""}, {"Group.Name", Field, 7, ""}, {"Lookup", Func, 0, "func(username string) (*User, error)"}, {"LookupGroup", Func, 7, "func(name string) (*Group, error)"}, {"LookupGroupId", Func, 7, "func(gid string) (*Group, error)"}, {"LookupId", Func, 0, "func(uid string) (*User, error)"}, {"UnknownGroupError", Type, 7, ""}, {"UnknownGroupIdError", Type, 7, ""}, {"UnknownUserError", Type, 0, ""}, {"UnknownUserIdError", Type, 0, ""}, {"User", Type, 0, ""}, {"User.Gid", Field, 0, ""}, {"User.HomeDir", Field, 0, ""}, {"User.Name", Field, 0, ""}, {"User.Uid", Field, 0, ""}, {"User.Username", Field, 0, ""}, }, "path": { {"Base", Func, 0, "func(path string) string"}, {"Clean", Func, 0, "func(path string) string"}, {"Dir", Func, 0, "func(path string) string"}, {"ErrBadPattern", Var, 0, ""}, {"Ext", Func, 0, "func(path string) string"}, {"IsAbs", Func, 0, "func(path string) bool"}, {"Join", Func, 0, "func(elem ...string) string"}, {"Match", Func, 0, "func(pattern string, name string) (matched bool, err error)"}, {"Split", Func, 0, "func(path string) (dir string, file string)"}, }, "path/filepath": { {"Abs", Func, 0, "func(path string) (string, error)"}, {"Base", Func, 0, "func(path string) string"}, {"Clean", Func, 0, "func(path string) string"}, {"Dir", Func, 0, "func(path string) string"}, {"ErrBadPattern", Var, 0, ""}, {"EvalSymlinks", Func, 0, "func(path string) (string, error)"}, {"Ext", Func, 0, "func(path string) string"}, {"FromSlash", Func, 0, "func(path string) string"}, {"Glob", Func, 0, "func(pattern string) (matches []string, err error)"}, {"HasPrefix", Func, 0, "func(p string, prefix string) bool"}, {"IsAbs", Func, 0, "func(path string) bool"}, {"IsLocal", Func, 20, "func(path string) bool"}, {"Join", Func, 0, "func(elem ...string) string"}, {"ListSeparator", Const, 0, ""}, {"Localize", Func, 23, "func(path string) (string, error)"}, {"Match", Func, 0, "func(pattern string, name string) (matched bool, err error)"}, {"Rel", Func, 0, "func(basepath string, targpath string) (string, error)"}, {"Separator", Const, 0, ""}, {"SkipAll", Var, 20, ""}, {"SkipDir", Var, 0, ""}, {"Split", Func, 0, "func(path string) (dir string, file string)"}, {"SplitList", Func, 0, "func(path string) []string"}, {"ToSlash", Func, 0, "func(path string) string"}, {"VolumeName", Func, 0, "func(path string) string"}, {"Walk", Func, 0, "func(root string, fn WalkFunc) error"}, {"WalkDir", Func, 16, "func(root string, fn fs.WalkDirFunc) error"}, {"WalkFunc", Type, 0, ""}, }, "plugin": { {"(*Plugin).Lookup", Method, 8, ""}, {"Open", Func, 8, "func(path string) (*Plugin, error)"}, {"Plugin", Type, 8, ""}, {"Symbol", Type, 8, ""}, }, "reflect": { {"(*MapIter).Key", Method, 12, ""}, {"(*MapIter).Next", Method, 12, ""}, {"(*MapIter).Reset", Method, 18, ""}, {"(*MapIter).Value", Method, 12, ""}, {"(*ValueError).Error", Method, 0, ""}, {"(ChanDir).String", Method, 0, ""}, {"(Kind).String", Method, 0, ""}, {"(Method).IsExported", Method, 17, ""}, {"(StructField).IsExported", Method, 17, ""}, {"(StructTag).Get", Method, 0, ""}, {"(StructTag).Lookup", Method, 7, ""}, {"(Value).Addr", Method, 0, ""}, {"(Value).Bool", Method, 0, ""}, {"(Value).Bytes", Method, 0, ""}, {"(Value).Call", Method, 0, ""}, {"(Value).CallSlice", Method, 0, ""}, {"(Value).CanAddr", Method, 0, ""}, {"(Value).CanComplex", Method, 18, ""}, {"(Value).CanConvert", Method, 17, ""}, {"(Value).CanFloat", Method, 18, ""}, {"(Value).CanInt", Method, 18, ""}, {"(Value).CanInterface", Method, 0, ""}, {"(Value).CanSet", Method, 0, ""}, {"(Value).CanUint", Method, 18, ""}, {"(Value).Cap", Method, 0, ""}, {"(Value).Clear", Method, 21, ""}, {"(Value).Close", Method, 0, ""}, {"(Value).Comparable", Method, 20, ""}, {"(Value).Complex", Method, 0, ""}, {"(Value).Convert", Method, 1, ""}, {"(Value).Elem", Method, 0, ""}, {"(Value).Equal", Method, 20, ""}, {"(Value).Field", Method, 0, ""}, {"(Value).FieldByIndex", Method, 0, ""}, {"(Value).FieldByIndexErr", Method, 18, ""}, {"(Value).FieldByName", Method, 0, ""}, {"(Value).FieldByNameFunc", Method, 0, ""}, {"(Value).Float", Method, 0, ""}, {"(Value).Grow", Method, 20, ""}, {"(Value).Index", Method, 0, ""}, {"(Value).Int", Method, 0, ""}, {"(Value).Interface", Method, 0, ""}, {"(Value).InterfaceData", Method, 0, ""}, {"(Value).IsNil", Method, 0, ""}, {"(Value).IsValid", Method, 0, ""}, {"(Value).IsZero", Method, 13, ""}, {"(Value).Kind", Method, 0, ""}, {"(Value).Len", Method, 0, ""}, {"(Value).MapIndex", Method, 0, ""}, {"(Value).MapKeys", Method, 0, ""}, {"(Value).MapRange", Method, 12, ""}, {"(Value).Method", Method, 0, ""}, {"(Value).MethodByName", Method, 0, ""}, {"(Value).NumField", Method, 0, ""}, {"(Value).NumMethod", Method, 0, ""}, {"(Value).OverflowComplex", Method, 0, ""}, {"(Value).OverflowFloat", Method, 0, ""}, {"(Value).OverflowInt", Method, 0, ""}, {"(Value).OverflowUint", Method, 0, ""}, {"(Value).Pointer", Method, 0, ""}, {"(Value).Recv", Method, 0, ""}, {"(Value).Send", Method, 0, ""}, {"(Value).Seq", Method, 23, ""}, {"(Value).Seq2", Method, 23, ""}, {"(Value).Set", Method, 0, ""}, {"(Value).SetBool", Method, 0, ""}, {"(Value).SetBytes", Method, 0, ""}, {"(Value).SetCap", Method, 2, ""}, {"(Value).SetComplex", Method, 0, ""}, {"(Value).SetFloat", Method, 0, ""}, {"(Value).SetInt", Method, 0, ""}, {"(Value).SetIterKey", Method, 18, ""}, {"(Value).SetIterValue", Method, 18, ""}, {"(Value).SetLen", Method, 0, ""}, {"(Value).SetMapIndex", Method, 0, ""}, {"(Value).SetPointer", Method, 0, ""}, {"(Value).SetString", Method, 0, ""}, {"(Value).SetUint", Method, 0, ""}, {"(Value).SetZero", Method, 20, ""}, {"(Value).Slice", Method, 0, ""}, {"(Value).Slice3", Method, 2, ""}, {"(Value).String", Method, 0, ""}, {"(Value).TryRecv", Method, 0, ""}, {"(Value).TrySend", Method, 0, ""}, {"(Value).Type", Method, 0, ""}, {"(Value).Uint", Method, 0, ""}, {"(Value).UnsafeAddr", Method, 0, ""}, {"(Value).UnsafePointer", Method, 18, ""}, {"Append", Func, 0, "func(s Value, x ...Value) Value"}, {"AppendSlice", Func, 0, "func(s Value, t Value) Value"}, {"Array", Const, 0, ""}, {"ArrayOf", Func, 5, "func(length int, elem Type) Type"}, {"Bool", Const, 0, ""}, {"BothDir", Const, 0, ""}, {"Chan", Const, 0, ""}, {"ChanDir", Type, 0, ""}, {"ChanOf", Func, 1, "func(dir ChanDir, t Type) Type"}, {"Complex128", Const, 0, ""}, {"Complex64", Const, 0, ""}, {"Copy", Func, 0, "func(dst Value, src Value) int"}, {"DeepEqual", Func, 0, "func(x any, y any) bool"}, {"Float32", Const, 0, ""}, {"Float64", Const, 0, ""}, {"Func", Const, 0, ""}, {"FuncOf", Func, 5, "func(in []Type, out []Type, variadic bool) Type"}, {"Indirect", Func, 0, "func(v Value) Value"}, {"Int", Const, 0, ""}, {"Int16", Const, 0, ""}, {"Int32", Const, 0, ""}, {"Int64", Const, 0, ""}, {"Int8", Const, 0, ""}, {"Interface", Const, 0, ""}, {"Invalid", Const, 0, ""}, {"Kind", Type, 0, ""}, {"MakeChan", Func, 0, "func(typ Type, buffer int) Value"}, {"MakeFunc", Func, 1, "func(typ Type, fn func(args []Value) (results []Value)) Value"}, {"MakeMap", Func, 0, "func(typ Type) Value"}, {"MakeMapWithSize", Func, 9, "func(typ Type, n int) Value"}, {"MakeSlice", Func, 0, "func(typ Type, len int, cap int) Value"}, {"Map", Const, 0, ""}, {"MapIter", Type, 12, ""}, {"MapOf", Func, 1, "func(key Type, elem Type) Type"}, {"Method", Type, 0, ""}, {"Method.Func", Field, 0, ""}, {"Method.Index", Field, 0, ""}, {"Method.Name", Field, 0, ""}, {"Method.PkgPath", Field, 0, ""}, {"Method.Type", Field, 0, ""}, {"New", Func, 0, "func(typ Type) Value"}, {"NewAt", Func, 0, "func(typ Type, p unsafe.Pointer) Value"}, {"Pointer", Const, 18, ""}, {"PointerTo", Func, 18, "func(t Type) Type"}, {"Ptr", Const, 0, ""}, {"PtrTo", Func, 0, "func(t Type) Type"}, {"RecvDir", Const, 0, ""}, {"Select", Func, 1, "func(cases []SelectCase) (chosen int, recv Value, recvOK bool)"}, {"SelectCase", Type, 1, ""}, {"SelectCase.Chan", Field, 1, ""}, {"SelectCase.Dir", Field, 1, ""}, {"SelectCase.Send", Field, 1, ""}, {"SelectDefault", Const, 1, ""}, {"SelectDir", Type, 1, ""}, {"SelectRecv", Const, 1, ""}, {"SelectSend", Const, 1, ""}, {"SendDir", Const, 0, ""}, {"Slice", Const, 0, ""}, {"SliceAt", Func, 23, "func(typ Type, p unsafe.Pointer, n int) Value"}, {"SliceHeader", Type, 0, ""}, {"SliceHeader.Cap", Field, 0, ""}, {"SliceHeader.Data", Field, 0, ""}, {"SliceHeader.Len", Field, 0, ""}, {"SliceOf", Func, 1, "func(t Type) Type"}, {"String", Const, 0, ""}, {"StringHeader", Type, 0, ""}, {"StringHeader.Data", Field, 0, ""}, {"StringHeader.Len", Field, 0, ""}, {"Struct", Const, 0, ""}, {"StructField", Type, 0, ""}, {"StructField.Anonymous", Field, 0, ""}, {"StructField.Index", Field, 0, ""}, {"StructField.Name", Field, 0, ""}, {"StructField.Offset", Field, 0, ""}, {"StructField.PkgPath", Field, 0, ""}, {"StructField.Tag", Field, 0, ""}, {"StructField.Type", Field, 0, ""}, {"StructOf", Func, 7, "func(fields []StructField) Type"}, {"StructTag", Type, 0, ""}, {"Swapper", Func, 8, "func(slice any) func(i int, j int)"}, {"Type", Type, 0, ""}, {"TypeFor", Func, 22, "func[T any]() Type"}, {"TypeOf", Func, 0, "func(i any) Type"}, {"Uint", Const, 0, ""}, {"Uint16", Const, 0, ""}, {"Uint32", Const, 0, ""}, {"Uint64", Const, 0, ""}, {"Uint8", Const, 0, ""}, {"Uintptr", Const, 0, ""}, {"UnsafePointer", Const, 0, ""}, {"Value", Type, 0, ""}, {"ValueError", Type, 0, ""}, {"ValueError.Kind", Field, 0, ""}, {"ValueError.Method", Field, 0, ""}, {"ValueOf", Func, 0, "func(i any) Value"}, {"VisibleFields", Func, 17, "func(t Type) []StructField"}, {"Zero", Func, 0, "func(typ Type) Value"}, }, "regexp": { {"(*Regexp).AppendText", Method, 24, ""}, {"(*Regexp).Copy", Method, 6, ""}, {"(*Regexp).Expand", Method, 0, ""}, {"(*Regexp).ExpandString", Method, 0, ""}, {"(*Regexp).Find", Method, 0, ""}, {"(*Regexp).FindAll", Method, 0, ""}, {"(*Regexp).FindAllIndex", Method, 0, ""}, {"(*Regexp).FindAllString", Method, 0, ""}, {"(*Regexp).FindAllStringIndex", Method, 0, ""}, {"(*Regexp).FindAllStringSubmatch", Method, 0, ""}, {"(*Regexp).FindAllStringSubmatchIndex", Method, 0, ""}, {"(*Regexp).FindAllSubmatch", Method, 0, ""}, {"(*Regexp).FindAllSubmatchIndex", Method, 0, ""}, {"(*Regexp).FindIndex", Method, 0, ""}, {"(*Regexp).FindReaderIndex", Method, 0, ""}, {"(*Regexp).FindReaderSubmatchIndex", Method, 0, ""}, {"(*Regexp).FindString", Method, 0, ""}, {"(*Regexp).FindStringIndex", Method, 0, ""}, {"(*Regexp).FindStringSubmatch", Method, 0, ""}, {"(*Regexp).FindStringSubmatchIndex", Method, 0, ""}, {"(*Regexp).FindSubmatch", Method, 0, ""}, {"(*Regexp).FindSubmatchIndex", Method, 0, ""}, {"(*Regexp).LiteralPrefix", Method, 0, ""}, {"(*Regexp).Longest", Method, 1, ""}, {"(*Regexp).MarshalText", Method, 21, ""}, {"(*Regexp).Match", Method, 0, ""}, {"(*Regexp).MatchReader", Method, 0, ""}, {"(*Regexp).MatchString", Method, 0, ""}, {"(*Regexp).NumSubexp", Method, 0, ""}, {"(*Regexp).ReplaceAll", Method, 0, ""}, {"(*Regexp).ReplaceAllFunc", Method, 0, ""}, {"(*Regexp).ReplaceAllLiteral", Method, 0, ""}, {"(*Regexp).ReplaceAllLiteralString", Method, 0, ""}, {"(*Regexp).ReplaceAllString", Method, 0, ""}, {"(*Regexp).ReplaceAllStringFunc", Method, 0, ""}, {"(*Regexp).Split", Method, 1, ""}, {"(*Regexp).String", Method, 0, ""}, {"(*Regexp).SubexpIndex", Method, 15, ""}, {"(*Regexp).SubexpNames", Method, 0, ""}, {"(*Regexp).UnmarshalText", Method, 21, ""}, {"Compile", Func, 0, "func(expr string) (*Regexp, error)"}, {"CompilePOSIX", Func, 0, "func(expr string) (*Regexp, error)"}, {"Match", Func, 0, "func(pattern string, b []byte) (matched bool, err error)"}, {"MatchReader", Func, 0, "func(pattern string, r io.RuneReader) (matched bool, err error)"}, {"MatchString", Func, 0, "func(pattern string, s string) (matched bool, err error)"}, {"MustCompile", Func, 0, "func(str string) *Regexp"}, {"MustCompilePOSIX", Func, 0, "func(str string) *Regexp"}, {"QuoteMeta", Func, 0, "func(s string) string"}, {"Regexp", Type, 0, ""}, }, "regexp/syntax": { {"(*Error).Error", Method, 0, ""}, {"(*Inst).MatchEmptyWidth", Method, 0, ""}, {"(*Inst).MatchRune", Method, 0, ""}, {"(*Inst).MatchRunePos", Method, 3, ""}, {"(*Inst).String", Method, 0, ""}, {"(*Prog).Prefix", Method, 0, ""}, {"(*Prog).StartCond", Method, 0, ""}, {"(*Prog).String", Method, 0, ""}, {"(*Regexp).CapNames", Method, 0, ""}, {"(*Regexp).Equal", Method, 0, ""}, {"(*Regexp).MaxCap", Method, 0, ""}, {"(*Regexp).Simplify", Method, 0, ""}, {"(*Regexp).String", Method, 0, ""}, {"(ErrorCode).String", Method, 0, ""}, {"(InstOp).String", Method, 3, ""}, {"(Op).String", Method, 11, ""}, {"ClassNL", Const, 0, ""}, {"Compile", Func, 0, "func(re *Regexp) (*Prog, error)"}, {"DotNL", Const, 0, ""}, {"EmptyBeginLine", Const, 0, ""}, {"EmptyBeginText", Const, 0, ""}, {"EmptyEndLine", Const, 0, ""}, {"EmptyEndText", Const, 0, ""}, {"EmptyNoWordBoundary", Const, 0, ""}, {"EmptyOp", Type, 0, ""}, {"EmptyOpContext", Func, 0, "func(r1 rune, r2 rune) EmptyOp"}, {"EmptyWordBoundary", Const, 0, ""}, {"ErrInternalError", Const, 0, ""}, {"ErrInvalidCharClass", Const, 0, ""}, {"ErrInvalidCharRange", Const, 0, ""}, {"ErrInvalidEscape", Const, 0, ""}, {"ErrInvalidNamedCapture", Const, 0, ""}, {"ErrInvalidPerlOp", Const, 0, ""}, {"ErrInvalidRepeatOp", Const, 0, ""}, {"ErrInvalidRepeatSize", Const, 0, ""}, {"ErrInvalidUTF8", Const, 0, ""}, {"ErrLarge", Const, 20, ""}, {"ErrMissingBracket", Const, 0, ""}, {"ErrMissingParen", Const, 0, ""}, {"ErrMissingRepeatArgument", Const, 0, ""}, {"ErrNestingDepth", Const, 19, ""}, {"ErrTrailingBackslash", Const, 0, ""}, {"ErrUnexpectedParen", Const, 1, ""}, {"Error", Type, 0, ""}, {"Error.Code", Field, 0, ""}, {"Error.Expr", Field, 0, ""}, {"ErrorCode", Type, 0, ""}, {"Flags", Type, 0, ""}, {"FoldCase", Const, 0, ""}, {"Inst", Type, 0, ""}, {"Inst.Arg", Field, 0, ""}, {"Inst.Op", Field, 0, ""}, {"Inst.Out", Field, 0, ""}, {"Inst.Rune", Field, 0, ""}, {"InstAlt", Const, 0, ""}, {"InstAltMatch", Const, 0, ""}, {"InstCapture", Const, 0, ""}, {"InstEmptyWidth", Const, 0, ""}, {"InstFail", Const, 0, ""}, {"InstMatch", Const, 0, ""}, {"InstNop", Const, 0, ""}, {"InstOp", Type, 0, ""}, {"InstRune", Const, 0, ""}, {"InstRune1", Const, 0, ""}, {"InstRuneAny", Const, 0, ""}, {"InstRuneAnyNotNL", Const, 0, ""}, {"IsWordChar", Func, 0, "func(r rune) bool"}, {"Literal", Const, 0, ""}, {"MatchNL", Const, 0, ""}, {"NonGreedy", Const, 0, ""}, {"OneLine", Const, 0, ""}, {"Op", Type, 0, ""}, {"OpAlternate", Const, 0, ""}, {"OpAnyChar", Const, 0, ""}, {"OpAnyCharNotNL", Const, 0, ""}, {"OpBeginLine", Const, 0, ""}, {"OpBeginText", Const, 0, ""}, {"OpCapture", Const, 0, ""}, {"OpCharClass", Const, 0, ""}, {"OpConcat", Const, 0, ""}, {"OpEmptyMatch", Const, 0, ""}, {"OpEndLine", Const, 0, ""}, {"OpEndText", Const, 0, ""}, {"OpLiteral", Const, 0, ""}, {"OpNoMatch", Const, 0, ""}, {"OpNoWordBoundary", Const, 0, ""}, {"OpPlus", Const, 0, ""}, {"OpQuest", Const, 0, ""}, {"OpRepeat", Const, 0, ""}, {"OpStar", Const, 0, ""}, {"OpWordBoundary", Const, 0, ""}, {"POSIX", Const, 0, ""}, {"Parse", Func, 0, "func(s string, flags Flags) (*Regexp, error)"}, {"Perl", Const, 0, ""}, {"PerlX", Const, 0, ""}, {"Prog", Type, 0, ""}, {"Prog.Inst", Field, 0, ""}, {"Prog.NumCap", Field, 0, ""}, {"Prog.Start", Field, 0, ""}, {"Regexp", Type, 0, ""}, {"Regexp.Cap", Field, 0, ""}, {"Regexp.Flags", Field, 0, ""}, {"Regexp.Max", Field, 0, ""}, {"Regexp.Min", Field, 0, ""}, {"Regexp.Name", Field, 0, ""}, {"Regexp.Op", Field, 0, ""}, {"Regexp.Rune", Field, 0, ""}, {"Regexp.Rune0", Field, 0, ""}, {"Regexp.Sub", Field, 0, ""}, {"Regexp.Sub0", Field, 0, ""}, {"Simple", Const, 0, ""}, {"UnicodeGroups", Const, 0, ""}, {"WasDollar", Const, 0, ""}, }, "runtime": { {"(*BlockProfileRecord).Stack", Method, 1, ""}, {"(*Frames).Next", Method, 7, ""}, {"(*Func).Entry", Method, 0, ""}, {"(*Func).FileLine", Method, 0, ""}, {"(*Func).Name", Method, 0, ""}, {"(*MemProfileRecord).InUseBytes", Method, 0, ""}, {"(*MemProfileRecord).InUseObjects", Method, 0, ""}, {"(*MemProfileRecord).Stack", Method, 0, ""}, {"(*PanicNilError).Error", Method, 21, ""}, {"(*PanicNilError).RuntimeError", Method, 21, ""}, {"(*Pinner).Pin", Method, 21, ""}, {"(*Pinner).Unpin", Method, 21, ""}, {"(*StackRecord).Stack", Method, 0, ""}, {"(*TypeAssertionError).Error", Method, 0, ""}, {"(*TypeAssertionError).RuntimeError", Method, 0, ""}, {"(Cleanup).Stop", Method, 24, ""}, {"AddCleanup", Func, 24, "func[T, S any](ptr *T, cleanup func(S), arg S) Cleanup"}, {"BlockProfile", Func, 1, "func(p []BlockProfileRecord) (n int, ok bool)"}, {"BlockProfileRecord", Type, 1, ""}, {"BlockProfileRecord.Count", Field, 1, ""}, {"BlockProfileRecord.Cycles", Field, 1, ""}, {"BlockProfileRecord.StackRecord", Field, 1, ""}, {"Breakpoint", Func, 0, "func()"}, {"CPUProfile", Func, 0, "func() []byte"}, {"Caller", Func, 0, "func(skip int) (pc uintptr, file string, line int, ok bool)"}, {"Callers", Func, 0, "func(skip int, pc []uintptr) int"}, {"CallersFrames", Func, 7, "func(callers []uintptr) *Frames"}, {"Cleanup", Type, 24, ""}, {"Compiler", Const, 0, ""}, {"Error", Type, 0, ""}, {"Frame", Type, 7, ""}, {"Frame.Entry", Field, 7, ""}, {"Frame.File", Field, 7, ""}, {"Frame.Func", Field, 7, ""}, {"Frame.Function", Field, 7, ""}, {"Frame.Line", Field, 7, ""}, {"Frame.PC", Field, 7, ""}, {"Frames", Type, 7, ""}, {"Func", Type, 0, ""}, {"FuncForPC", Func, 0, "func(pc uintptr) *Func"}, {"GC", Func, 0, "func()"}, {"GOARCH", Const, 0, ""}, {"GOMAXPROCS", Func, 0, "func(n int) int"}, {"GOOS", Const, 0, ""}, {"GOROOT", Func, 0, "func() string"}, {"Goexit", Func, 0, "func()"}, {"GoroutineProfile", Func, 0, "func(p []StackRecord) (n int, ok bool)"}, {"Gosched", Func, 0, "func()"}, {"KeepAlive", Func, 7, "func(x any)"}, {"LockOSThread", Func, 0, "func()"}, {"MemProfile", Func, 0, "func(p []MemProfileRecord, inuseZero bool) (n int, ok bool)"}, {"MemProfileRate", Var, 0, ""}, {"MemProfileRecord", Type, 0, ""}, {"MemProfileRecord.AllocBytes", Field, 0, ""}, {"MemProfileRecord.AllocObjects", Field, 0, ""}, {"MemProfileRecord.FreeBytes", Field, 0, ""}, {"MemProfileRecord.FreeObjects", Field, 0, ""}, {"MemProfileRecord.Stack0", Field, 0, ""}, {"MemStats", Type, 0, ""}, {"MemStats.Alloc", Field, 0, ""}, {"MemStats.BuckHashSys", Field, 0, ""}, {"MemStats.BySize", Field, 0, ""}, {"MemStats.DebugGC", Field, 0, ""}, {"MemStats.EnableGC", Field, 0, ""}, {"MemStats.Frees", Field, 0, ""}, {"MemStats.GCCPUFraction", Field, 5, ""}, {"MemStats.GCSys", Field, 2, ""}, {"MemStats.HeapAlloc", Field, 0, ""}, {"MemStats.HeapIdle", Field, 0, ""}, {"MemStats.HeapInuse", Field, 0, ""}, {"MemStats.HeapObjects", Field, 0, ""}, {"MemStats.HeapReleased", Field, 0, ""}, {"MemStats.HeapSys", Field, 0, ""}, {"MemStats.LastGC", Field, 0, ""}, {"MemStats.Lookups", Field, 0, ""}, {"MemStats.MCacheInuse", Field, 0, ""}, {"MemStats.MCacheSys", Field, 0, ""}, {"MemStats.MSpanInuse", Field, 0, ""}, {"MemStats.MSpanSys", Field, 0, ""}, {"MemStats.Mallocs", Field, 0, ""}, {"MemStats.NextGC", Field, 0, ""}, {"MemStats.NumForcedGC", Field, 8, ""}, {"MemStats.NumGC", Field, 0, ""}, {"MemStats.OtherSys", Field, 2, ""}, {"MemStats.PauseEnd", Field, 4, ""}, {"MemStats.PauseNs", Field, 0, ""}, {"MemStats.PauseTotalNs", Field, 0, ""}, {"MemStats.StackInuse", Field, 0, ""}, {"MemStats.StackSys", Field, 0, ""}, {"MemStats.Sys", Field, 0, ""}, {"MemStats.TotalAlloc", Field, 0, ""}, {"MutexProfile", Func, 8, "func(p []BlockProfileRecord) (n int, ok bool)"}, {"NumCPU", Func, 0, "func() int"}, {"NumCgoCall", Func, 0, "func() int64"}, {"NumGoroutine", Func, 0, "func() int"}, {"PanicNilError", Type, 21, ""}, {"Pinner", Type, 21, ""}, {"ReadMemStats", Func, 0, "func(m *MemStats)"}, {"ReadTrace", Func, 5, "func() []byte"}, {"SetBlockProfileRate", Func, 1, "func(rate int)"}, {"SetCPUProfileRate", Func, 0, "func(hz int)"}, {"SetCgoTraceback", Func, 7, "func(version int, traceback unsafe.Pointer, context unsafe.Pointer, symbolizer unsafe.Pointer)"}, {"SetFinalizer", Func, 0, "func(obj any, finalizer any)"}, {"SetMutexProfileFraction", Func, 8, "func(rate int) int"}, {"Stack", Func, 0, "func(buf []byte, all bool) int"}, {"StackRecord", Type, 0, ""}, {"StackRecord.Stack0", Field, 0, ""}, {"StartTrace", Func, 5, "func() error"}, {"StopTrace", Func, 5, "func()"}, {"ThreadCreateProfile", Func, 0, "func(p []StackRecord) (n int, ok bool)"}, {"TypeAssertionError", Type, 0, ""}, {"UnlockOSThread", Func, 0, "func()"}, {"Version", Func, 0, "func() string"}, }, "runtime/cgo": { {"(Handle).Delete", Method, 17, ""}, {"(Handle).Value", Method, 17, ""}, {"Handle", Type, 17, ""}, {"Incomplete", Type, 20, ""}, {"NewHandle", Func, 17, ""}, }, "runtime/coverage": { {"ClearCounters", Func, 20, "func() error"}, {"WriteCounters", Func, 20, "func(w io.Writer) error"}, {"WriteCountersDir", Func, 20, "func(dir string) error"}, {"WriteMeta", Func, 20, "func(w io.Writer) error"}, {"WriteMetaDir", Func, 20, "func(dir string) error"}, }, "runtime/debug": { {"(*BuildInfo).String", Method, 18, ""}, {"BuildInfo", Type, 12, ""}, {"BuildInfo.Deps", Field, 12, ""}, {"BuildInfo.GoVersion", Field, 18, ""}, {"BuildInfo.Main", Field, 12, ""}, {"BuildInfo.Path", Field, 12, ""}, {"BuildInfo.Settings", Field, 18, ""}, {"BuildSetting", Type, 18, ""}, {"BuildSetting.Key", Field, 18, ""}, {"BuildSetting.Value", Field, 18, ""}, {"CrashOptions", Type, 23, ""}, {"FreeOSMemory", Func, 1, "func()"}, {"GCStats", Type, 1, ""}, {"GCStats.LastGC", Field, 1, ""}, {"GCStats.NumGC", Field, 1, ""}, {"GCStats.Pause", Field, 1, ""}, {"GCStats.PauseEnd", Field, 4, ""}, {"GCStats.PauseQuantiles", Field, 1, ""}, {"GCStats.PauseTotal", Field, 1, ""}, {"Module", Type, 12, ""}, {"Module.Path", Field, 12, ""}, {"Module.Replace", Field, 12, ""}, {"Module.Sum", Field, 12, ""}, {"Module.Version", Field, 12, ""}, {"ParseBuildInfo", Func, 18, "func(data string) (bi *BuildInfo, err error)"}, {"PrintStack", Func, 0, "func()"}, {"ReadBuildInfo", Func, 12, "func() (info *BuildInfo, ok bool)"}, {"ReadGCStats", Func, 1, "func(stats *GCStats)"}, {"SetCrashOutput", Func, 23, "func(f *os.File, opts CrashOptions) error"}, {"SetGCPercent", Func, 1, "func(percent int) int"}, {"SetMaxStack", Func, 2, "func(bytes int) int"}, {"SetMaxThreads", Func, 2, "func(threads int) int"}, {"SetMemoryLimit", Func, 19, "func(limit int64) int64"}, {"SetPanicOnFault", Func, 3, "func(enabled bool) bool"}, {"SetTraceback", Func, 6, "func(level string)"}, {"Stack", Func, 0, "func() []byte"}, {"WriteHeapDump", Func, 3, "func(fd uintptr)"}, }, "runtime/metrics": { {"(Value).Float64", Method, 16, ""}, {"(Value).Float64Histogram", Method, 16, ""}, {"(Value).Kind", Method, 16, ""}, {"(Value).Uint64", Method, 16, ""}, {"All", Func, 16, "func() []Description"}, {"Description", Type, 16, ""}, {"Description.Cumulative", Field, 16, ""}, {"Description.Description", Field, 16, ""}, {"Description.Kind", Field, 16, ""}, {"Description.Name", Field, 16, ""}, {"Float64Histogram", Type, 16, ""}, {"Float64Histogram.Buckets", Field, 16, ""}, {"Float64Histogram.Counts", Field, 16, ""}, {"KindBad", Const, 16, ""}, {"KindFloat64", Const, 16, ""}, {"KindFloat64Histogram", Const, 16, ""}, {"KindUint64", Const, 16, ""}, {"Read", Func, 16, "func(m []Sample)"}, {"Sample", Type, 16, ""}, {"Sample.Name", Field, 16, ""}, {"Sample.Value", Field, 16, ""}, {"Value", Type, 16, ""}, {"ValueKind", Type, 16, ""}, }, "runtime/pprof": { {"(*Profile).Add", Method, 0, ""}, {"(*Profile).Count", Method, 0, ""}, {"(*Profile).Name", Method, 0, ""}, {"(*Profile).Remove", Method, 0, ""}, {"(*Profile).WriteTo", Method, 0, ""}, {"Do", Func, 9, "func(ctx context.Context, labels LabelSet, f func(context.Context))"}, {"ForLabels", Func, 9, "func(ctx context.Context, f func(key string, value string) bool)"}, {"Label", Func, 9, "func(ctx context.Context, key string) (string, bool)"}, {"LabelSet", Type, 9, ""}, {"Labels", Func, 9, "func(args ...string) LabelSet"}, {"Lookup", Func, 0, "func(name string) *Profile"}, {"NewProfile", Func, 0, "func(name string) *Profile"}, {"Profile", Type, 0, ""}, {"Profiles", Func, 0, "func() []*Profile"}, {"SetGoroutineLabels", Func, 9, "func(ctx context.Context)"}, {"StartCPUProfile", Func, 0, "func(w io.Writer) error"}, {"StopCPUProfile", Func, 0, "func()"}, {"WithLabels", Func, 9, "func(ctx context.Context, labels LabelSet) context.Context"}, {"WriteHeapProfile", Func, 0, "func(w io.Writer) error"}, }, "runtime/trace": { {"(*Region).End", Method, 11, ""}, {"(*Task).End", Method, 11, ""}, {"IsEnabled", Func, 11, "func() bool"}, {"Log", Func, 11, "func(ctx context.Context, category string, message string)"}, {"Logf", Func, 11, "func(ctx context.Context, category string, format string, args ...any)"}, {"NewTask", Func, 11, "func(pctx context.Context, taskType string) (ctx context.Context, task *Task)"}, {"Region", Type, 11, ""}, {"Start", Func, 5, "func(w io.Writer) error"}, {"StartRegion", Func, 11, "func(ctx context.Context, regionType string) *Region"}, {"Stop", Func, 5, "func()"}, {"Task", Type, 11, ""}, {"WithRegion", Func, 11, "func(ctx context.Context, regionType string, fn func())"}, }, "slices": { {"All", Func, 23, "func[Slice ~[]E, E any](s Slice) iter.Seq2[int, E]"}, {"AppendSeq", Func, 23, "func[Slice ~[]E, E any](s Slice, seq iter.Seq[E]) Slice"}, {"Backward", Func, 23, "func[Slice ~[]E, E any](s Slice) iter.Seq2[int, E]"}, {"BinarySearch", Func, 21, "func[S ~[]E, E cmp.Ordered](x S, target E) (int, bool)"}, {"BinarySearchFunc", Func, 21, "func[S ~[]E, E, T any](x S, target T, cmp func(E, T) int) (int, bool)"}, {"Chunk", Func, 23, "func[Slice ~[]E, E any](s Slice, n int) iter.Seq[Slice]"}, {"Clip", Func, 21, "func[S ~[]E, E any](s S) S"}, {"Clone", Func, 21, "func[S ~[]E, E any](s S) S"}, {"Collect", Func, 23, "func[E any](seq iter.Seq[E]) []E"}, {"Compact", Func, 21, "func[S ~[]E, E comparable](s S) S"}, {"CompactFunc", Func, 21, "func[S ~[]E, E any](s S, eq func(E, E) bool) S"}, {"Compare", Func, 21, "func[S ~[]E, E cmp.Ordered](s1 S, s2 S) int"}, {"CompareFunc", Func, 21, "func[S1 ~[]E1, S2 ~[]E2, E1, E2 any](s1 S1, s2 S2, cmp func(E1, E2) int) int"}, {"Concat", Func, 22, "func[S ~[]E, E any](slices ...S) S"}, {"Contains", Func, 21, "func[S ~[]E, E comparable](s S, v E) bool"}, {"ContainsFunc", Func, 21, "func[S ~[]E, E any](s S, f func(E) bool) bool"}, {"Delete", Func, 21, "func[S ~[]E, E any](s S, i int, j int) S"}, {"DeleteFunc", Func, 21, "func[S ~[]E, E any](s S, del func(E) bool) S"}, {"Equal", Func, 21, "func[S ~[]E, E comparable](s1 S, s2 S) bool"}, {"EqualFunc", Func, 21, "func[S1 ~[]E1, S2 ~[]E2, E1, E2 any](s1 S1, s2 S2, eq func(E1, E2) bool) bool"}, {"Grow", Func, 21, "func[S ~[]E, E any](s S, n int) S"}, {"Index", Func, 21, "func[S ~[]E, E comparable](s S, v E) int"}, {"IndexFunc", Func, 21, "func[S ~[]E, E any](s S, f func(E) bool) int"}, {"Insert", Func, 21, "func[S ~[]E, E any](s S, i int, v ...E) S"}, {"IsSorted", Func, 21, "func[S ~[]E, E cmp.Ordered](x S) bool"}, {"IsSortedFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int) bool"}, {"Max", Func, 21, "func[S ~[]E, E cmp.Ordered](x S) E"}, {"MaxFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int) E"}, {"Min", Func, 21, "func[S ~[]E, E cmp.Ordered](x S) E"}, {"MinFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int) E"}, {"Repeat", Func, 23, "func[S ~[]E, E any](x S, count int) S"}, {"Replace", Func, 21, "func[S ~[]E, E any](s S, i int, j int, v ...E) S"}, {"Reverse", Func, 21, "func[S ~[]E, E any](s S)"}, {"Sort", Func, 21, "func[S ~[]E, E cmp.Ordered](x S)"}, {"SortFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int)"}, {"SortStableFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int)"}, {"Sorted", Func, 23, "func[E cmp.Ordered](seq iter.Seq[E]) []E"}, {"SortedFunc", Func, 23, "func[E any](seq iter.Seq[E], cmp func(E, E) int) []E"}, {"SortedStableFunc", Func, 23, "func[E any](seq iter.Seq[E], cmp func(E, E) int) []E"}, {"Values", Func, 23, "func[Slice ~[]E, E any](s Slice) iter.Seq[E]"}, }, "sort": { {"(Float64Slice).Len", Method, 0, ""}, {"(Float64Slice).Less", Method, 0, ""}, {"(Float64Slice).Search", Method, 0, ""}, {"(Float64Slice).Sort", Method, 0, ""}, {"(Float64Slice).Swap", Method, 0, ""}, {"(IntSlice).Len", Method, 0, ""}, {"(IntSlice).Less", Method, 0, ""}, {"(IntSlice).Search", Method, 0, ""}, {"(IntSlice).Sort", Method, 0, ""}, {"(IntSlice).Swap", Method, 0, ""}, {"(StringSlice).Len", Method, 0, ""}, {"(StringSlice).Less", Method, 0, ""}, {"(StringSlice).Search", Method, 0, ""}, {"(StringSlice).Sort", Method, 0, ""}, {"(StringSlice).Swap", Method, 0, ""}, {"Find", Func, 19, "func(n int, cmp func(int) int) (i int, found bool)"}, {"Float64Slice", Type, 0, ""}, {"Float64s", Func, 0, "func(x []float64)"}, {"Float64sAreSorted", Func, 0, "func(x []float64) bool"}, {"IntSlice", Type, 0, ""}, {"Interface", Type, 0, ""}, {"Ints", Func, 0, "func(x []int)"}, {"IntsAreSorted", Func, 0, "func(x []int) bool"}, {"IsSorted", Func, 0, "func(data Interface) bool"}, {"Reverse", Func, 1, "func(data Interface) Interface"}, {"Search", Func, 0, "func(n int, f func(int) bool) int"}, {"SearchFloat64s", Func, 0, "func(a []float64, x float64) int"}, {"SearchInts", Func, 0, "func(a []int, x int) int"}, {"SearchStrings", Func, 0, "func(a []string, x string) int"}, {"Slice", Func, 8, "func(x any, less func(i int, j int) bool)"}, {"SliceIsSorted", Func, 8, "func(x any, less func(i int, j int) bool) bool"}, {"SliceStable", Func, 8, "func(x any, less func(i int, j int) bool)"}, {"Sort", Func, 0, "func(data Interface)"}, {"Stable", Func, 2, "func(data Interface)"}, {"StringSlice", Type, 0, ""}, {"Strings", Func, 0, "func(x []string)"}, {"StringsAreSorted", Func, 0, "func(x []string) bool"}, }, "strconv": { {"(*NumError).Error", Method, 0, ""}, {"(*NumError).Unwrap", Method, 14, ""}, {"AppendBool", Func, 0, "func(dst []byte, b bool) []byte"}, {"AppendFloat", Func, 0, "func(dst []byte, f float64, fmt byte, prec int, bitSize int) []byte"}, {"AppendInt", Func, 0, "func(dst []byte, i int64, base int) []byte"}, {"AppendQuote", Func, 0, "func(dst []byte, s string) []byte"}, {"AppendQuoteRune", Func, 0, "func(dst []byte, r rune) []byte"}, {"AppendQuoteRuneToASCII", Func, 0, "func(dst []byte, r rune) []byte"}, {"AppendQuoteRuneToGraphic", Func, 6, "func(dst []byte, r rune) []byte"}, {"AppendQuoteToASCII", Func, 0, "func(dst []byte, s string) []byte"}, {"AppendQuoteToGraphic", Func, 6, "func(dst []byte, s string) []byte"}, {"AppendUint", Func, 0, "func(dst []byte, i uint64, base int) []byte"}, {"Atoi", Func, 0, "func(s string) (int, error)"}, {"CanBackquote", Func, 0, "func(s string) bool"}, {"ErrRange", Var, 0, ""}, {"ErrSyntax", Var, 0, ""}, {"FormatBool", Func, 0, "func(b bool) string"}, {"FormatComplex", Func, 15, "func(c complex128, fmt byte, prec int, bitSize int) string"}, {"FormatFloat", Func, 0, "func(f float64, fmt byte, prec int, bitSize int) string"}, {"FormatInt", Func, 0, "func(i int64, base int) string"}, {"FormatUint", Func, 0, "func(i uint64, base int) string"}, {"IntSize", Const, 0, ""}, {"IsGraphic", Func, 6, "func(r rune) bool"}, {"IsPrint", Func, 0, "func(r rune) bool"}, {"Itoa", Func, 0, "func(i int) string"}, {"NumError", Type, 0, ""}, {"NumError.Err", Field, 0, ""}, {"NumError.Func", Field, 0, ""}, {"NumError.Num", Field, 0, ""}, {"ParseBool", Func, 0, "func(str string) (bool, error)"}, {"ParseComplex", Func, 15, "func(s string, bitSize int) (complex128, error)"}, {"ParseFloat", Func, 0, "func(s string, bitSize int) (float64, error)"}, {"ParseInt", Func, 0, "func(s string, base int, bitSize int) (i int64, err error)"}, {"ParseUint", Func, 0, "func(s string, base int, bitSize int) (uint64, error)"}, {"Quote", Func, 0, "func(s string) string"}, {"QuoteRune", Func, 0, "func(r rune) string"}, {"QuoteRuneToASCII", Func, 0, "func(r rune) string"}, {"QuoteRuneToGraphic", Func, 6, "func(r rune) string"}, {"QuoteToASCII", Func, 0, "func(s string) string"}, {"QuoteToGraphic", Func, 6, "func(s string) string"}, {"QuotedPrefix", Func, 17, "func(s string) (string, error)"}, {"Unquote", Func, 0, "func(s string) (string, error)"}, {"UnquoteChar", Func, 0, "func(s string, quote byte) (value rune, multibyte bool, tail string, err error)"}, }, "strings": { {"(*Builder).Cap", Method, 12, ""}, {"(*Builder).Grow", Method, 10, ""}, {"(*Builder).Len", Method, 10, ""}, {"(*Builder).Reset", Method, 10, ""}, {"(*Builder).String", Method, 10, ""}, {"(*Builder).Write", Method, 10, ""}, {"(*Builder).WriteByte", Method, 10, ""}, {"(*Builder).WriteRune", Method, 10, ""}, {"(*Builder).WriteString", Method, 10, ""}, {"(*Reader).Len", Method, 0, ""}, {"(*Reader).Read", Method, 0, ""}, {"(*Reader).ReadAt", Method, 0, ""}, {"(*Reader).ReadByte", Method, 0, ""}, {"(*Reader).ReadRune", Method, 0, ""}, {"(*Reader).Reset", Method, 7, ""}, {"(*Reader).Seek", Method, 0, ""}, {"(*Reader).Size", Method, 5, ""}, {"(*Reader).UnreadByte", Method, 0, ""}, {"(*Reader).UnreadRune", Method, 0, ""}, {"(*Reader).WriteTo", Method, 1, ""}, {"(*Replacer).Replace", Method, 0, ""}, {"(*Replacer).WriteString", Method, 0, ""}, {"Builder", Type, 10, ""}, {"Clone", Func, 18, "func(s string) string"}, {"Compare", Func, 5, "func(a string, b string) int"}, {"Contains", Func, 0, "func(s string, substr string) bool"}, {"ContainsAny", Func, 0, "func(s string, chars string) bool"}, {"ContainsFunc", Func, 21, "func(s string, f func(rune) bool) bool"}, {"ContainsRune", Func, 0, "func(s string, r rune) bool"}, {"Count", Func, 0, "func(s string, substr string) int"}, {"Cut", Func, 18, "func(s string, sep string) (before string, after string, found bool)"}, {"CutPrefix", Func, 20, "func(s string, prefix string) (after string, found bool)"}, {"CutSuffix", Func, 20, "func(s string, suffix string) (before string, found bool)"}, {"EqualFold", Func, 0, "func(s string, t string) bool"}, {"Fields", Func, 0, "func(s string) []string"}, {"FieldsFunc", Func, 0, "func(s string, f func(rune) bool) []string"}, {"FieldsFuncSeq", Func, 24, "func(s string, f func(rune) bool) iter.Seq[string]"}, {"FieldsSeq", Func, 24, "func(s string) iter.Seq[string]"}, {"HasPrefix", Func, 0, "func(s string, prefix string) bool"}, {"HasSuffix", Func, 0, "func(s string, suffix string) bool"}, {"Index", Func, 0, "func(s string, substr string) int"}, {"IndexAny", Func, 0, "func(s string, chars string) int"}, {"IndexByte", Func, 2, "func(s string, c byte) int"}, {"IndexFunc", Func, 0, "func(s string, f func(rune) bool) int"}, {"IndexRune", Func, 0, "func(s string, r rune) int"}, {"Join", Func, 0, "func(elems []string, sep string) string"}, {"LastIndex", Func, 0, "func(s string, substr string) int"}, {"LastIndexAny", Func, 0, "func(s string, chars string) int"}, {"LastIndexByte", Func, 5, "func(s string, c byte) int"}, {"LastIndexFunc", Func, 0, "func(s string, f func(rune) bool) int"}, {"Lines", Func, 24, "func(s string) iter.Seq[string]"}, {"Map", Func, 0, "func(mapping func(rune) rune, s string) string"}, {"NewReader", Func, 0, "func(s string) *Reader"}, {"NewReplacer", Func, 0, "func(oldnew ...string) *Replacer"}, {"Reader", Type, 0, ""}, {"Repeat", Func, 0, "func(s string, count int) string"}, {"Replace", Func, 0, "func(s string, old string, new string, n int) string"}, {"ReplaceAll", Func, 12, "func(s string, old string, new string) string"}, {"Replacer", Type, 0, ""}, {"Split", Func, 0, "func(s string, sep string) []string"}, {"SplitAfter", Func, 0, "func(s string, sep string) []string"}, {"SplitAfterN", Func, 0, "func(s string, sep string, n int) []string"}, {"SplitAfterSeq", Func, 24, "func(s string, sep string) iter.Seq[string]"}, {"SplitN", Func, 0, "func(s string, sep string, n int) []string"}, {"SplitSeq", Func, 24, "func(s string, sep string) iter.Seq[string]"}, {"Title", Func, 0, "func(s string) string"}, {"ToLower", Func, 0, "func(s string) string"}, {"ToLowerSpecial", Func, 0, "func(c unicode.SpecialCase, s string) string"}, {"ToTitle", Func, 0, "func(s string) string"}, {"ToTitleSpecial", Func, 0, "func(c unicode.SpecialCase, s string) string"}, {"ToUpper", Func, 0, "func(s string) string"}, {"ToUpperSpecial", Func, 0, "func(c unicode.SpecialCase, s string) string"}, {"ToValidUTF8", Func, 13, "func(s string, replacement string) string"}, {"Trim", Func, 0, "func(s string, cutset string) string"}, {"TrimFunc", Func, 0, "func(s string, f func(rune) bool) string"}, {"TrimLeft", Func, 0, "func(s string, cutset string) string"}, {"TrimLeftFunc", Func, 0, "func(s string, f func(rune) bool) string"}, {"TrimPrefix", Func, 1, "func(s string, prefix string) string"}, {"TrimRight", Func, 0, "func(s string, cutset string) string"}, {"TrimRightFunc", Func, 0, "func(s string, f func(rune) bool) string"}, {"TrimSpace", Func, 0, "func(s string) string"}, {"TrimSuffix", Func, 1, "func(s string, suffix string) string"}, }, "structs": { {"HostLayout", Type, 23, ""}, }, "sync": { {"(*Cond).Broadcast", Method, 0, ""}, {"(*Cond).Signal", Method, 0, ""}, {"(*Cond).Wait", Method, 0, ""}, {"(*Map).Clear", Method, 23, ""}, {"(*Map).CompareAndDelete", Method, 20, ""}, {"(*Map).CompareAndSwap", Method, 20, ""}, {"(*Map).Delete", Method, 9, ""}, {"(*Map).Load", Method, 9, ""}, {"(*Map).LoadAndDelete", Method, 15, ""}, {"(*Map).LoadOrStore", Method, 9, ""}, {"(*Map).Range", Method, 9, ""}, {"(*Map).Store", Method, 9, ""}, {"(*Map).Swap", Method, 20, ""}, {"(*Mutex).Lock", Method, 0, ""}, {"(*Mutex).TryLock", Method, 18, ""}, {"(*Mutex).Unlock", Method, 0, ""}, {"(*Once).Do", Method, 0, ""}, {"(*Pool).Get", Method, 3, ""}, {"(*Pool).Put", Method, 3, ""}, {"(*RWMutex).Lock", Method, 0, ""}, {"(*RWMutex).RLock", Method, 0, ""}, {"(*RWMutex).RLocker", Method, 0, ""}, {"(*RWMutex).RUnlock", Method, 0, ""}, {"(*RWMutex).TryLock", Method, 18, ""}, {"(*RWMutex).TryRLock", Method, 18, ""}, {"(*RWMutex).Unlock", Method, 0, ""}, {"(*WaitGroup).Add", Method, 0, ""}, {"(*WaitGroup).Done", Method, 0, ""}, {"(*WaitGroup).Go", Method, 25, ""}, {"(*WaitGroup).Wait", Method, 0, ""}, {"Cond", Type, 0, ""}, {"Cond.L", Field, 0, ""}, {"Locker", Type, 0, ""}, {"Map", Type, 9, ""}, {"Mutex", Type, 0, ""}, {"NewCond", Func, 0, "func(l Locker) *Cond"}, {"Once", Type, 0, ""}, {"OnceFunc", Func, 21, "func(f func()) func()"}, {"OnceValue", Func, 21, "func[T any](f func() T) func() T"}, {"OnceValues", Func, 21, "func[T1, T2 any](f func() (T1, T2)) func() (T1, T2)"}, {"Pool", Type, 3, ""}, {"Pool.New", Field, 3, ""}, {"RWMutex", Type, 0, ""}, {"WaitGroup", Type, 0, ""}, }, "sync/atomic": { {"(*Bool).CompareAndSwap", Method, 19, ""}, {"(*Bool).Load", Method, 19, ""}, {"(*Bool).Store", Method, 19, ""}, {"(*Bool).Swap", Method, 19, ""}, {"(*Int32).Add", Method, 19, ""}, {"(*Int32).And", Method, 23, ""}, {"(*Int32).CompareAndSwap", Method, 19, ""}, {"(*Int32).Load", Method, 19, ""}, {"(*Int32).Or", Method, 23, ""}, {"(*Int32).Store", Method, 19, ""}, {"(*Int32).Swap", Method, 19, ""}, {"(*Int64).Add", Method, 19, ""}, {"(*Int64).And", Method, 23, ""}, {"(*Int64).CompareAndSwap", Method, 19, ""}, {"(*Int64).Load", Method, 19, ""}, {"(*Int64).Or", Method, 23, ""}, {"(*Int64).Store", Method, 19, ""}, {"(*Int64).Swap", Method, 19, ""}, {"(*Pointer).CompareAndSwap", Method, 19, ""}, {"(*Pointer).Load", Method, 19, ""}, {"(*Pointer).Store", Method, 19, ""}, {"(*Pointer).Swap", Method, 19, ""}, {"(*Uint32).Add", Method, 19, ""}, {"(*Uint32).And", Method, 23, ""}, {"(*Uint32).CompareAndSwap", Method, 19, ""}, {"(*Uint32).Load", Method, 19, ""}, {"(*Uint32).Or", Method, 23, ""}, {"(*Uint32).Store", Method, 19, ""}, {"(*Uint32).Swap", Method, 19, ""}, {"(*Uint64).Add", Method, 19, ""}, {"(*Uint64).And", Method, 23, ""}, {"(*Uint64).CompareAndSwap", Method, 19, ""}, {"(*Uint64).Load", Method, 19, ""}, {"(*Uint64).Or", Method, 23, ""}, {"(*Uint64).Store", Method, 19, ""}, {"(*Uint64).Swap", Method, 19, ""}, {"(*Uintptr).Add", Method, 19, ""}, {"(*Uintptr).And", Method, 23, ""}, {"(*Uintptr).CompareAndSwap", Method, 19, ""}, {"(*Uintptr).Load", Method, 19, ""}, {"(*Uintptr).Or", Method, 23, ""}, {"(*Uintptr).Store", Method, 19, ""}, {"(*Uintptr).Swap", Method, 19, ""}, {"(*Value).CompareAndSwap", Method, 17, ""}, {"(*Value).Load", Method, 4, ""}, {"(*Value).Store", Method, 4, ""}, {"(*Value).Swap", Method, 17, ""}, {"AddInt32", Func, 0, "func(addr *int32, delta int32) (new int32)"}, {"AddInt64", Func, 0, "func(addr *int64, delta int64) (new int64)"}, {"AddUint32", Func, 0, "func(addr *uint32, delta uint32) (new uint32)"}, {"AddUint64", Func, 0, "func(addr *uint64, delta uint64) (new uint64)"}, {"AddUintptr", Func, 0, "func(addr *uintptr, delta uintptr) (new uintptr)"}, {"AndInt32", Func, 23, "func(addr *int32, mask int32) (old int32)"}, {"AndInt64", Func, 23, "func(addr *int64, mask int64) (old int64)"}, {"AndUint32", Func, 23, "func(addr *uint32, mask uint32) (old uint32)"}, {"AndUint64", Func, 23, "func(addr *uint64, mask uint64) (old uint64)"}, {"AndUintptr", Func, 23, "func(addr *uintptr, mask uintptr) (old uintptr)"}, {"Bool", Type, 19, ""}, {"CompareAndSwapInt32", Func, 0, "func(addr *int32, old int32, new int32) (swapped bool)"}, {"CompareAndSwapInt64", Func, 0, "func(addr *int64, old int64, new int64) (swapped bool)"}, {"CompareAndSwapPointer", Func, 0, "func(addr *unsafe.Pointer, old unsafe.Pointer, new unsafe.Pointer) (swapped bool)"}, {"CompareAndSwapUint32", Func, 0, "func(addr *uint32, old uint32, new uint32) (swapped bool)"}, {"CompareAndSwapUint64", Func, 0, "func(addr *uint64, old uint64, new uint64) (swapped bool)"}, {"CompareAndSwapUintptr", Func, 0, "func(addr *uintptr, old uintptr, new uintptr) (swapped bool)"}, {"Int32", Type, 19, ""}, {"Int64", Type, 19, ""}, {"LoadInt32", Func, 0, "func(addr *int32) (val int32)"}, {"LoadInt64", Func, 0, "func(addr *int64) (val int64)"}, {"LoadPointer", Func, 0, "func(addr *unsafe.Pointer) (val unsafe.Pointer)"}, {"LoadUint32", Func, 0, "func(addr *uint32) (val uint32)"}, {"LoadUint64", Func, 0, "func(addr *uint64) (val uint64)"}, {"LoadUintptr", Func, 0, "func(addr *uintptr) (val uintptr)"}, {"OrInt32", Func, 23, "func(addr *int32, mask int32) (old int32)"}, {"OrInt64", Func, 23, "func(addr *int64, mask int64) (old int64)"}, {"OrUint32", Func, 23, "func(addr *uint32, mask uint32) (old uint32)"}, {"OrUint64", Func, 23, "func(addr *uint64, mask uint64) (old uint64)"}, {"OrUintptr", Func, 23, "func(addr *uintptr, mask uintptr) (old uintptr)"}, {"Pointer", Type, 19, ""}, {"StoreInt32", Func, 0, "func(addr *int32, val int32)"}, {"StoreInt64", Func, 0, "func(addr *int64, val int64)"}, {"StorePointer", Func, 0, "func(addr *unsafe.Pointer, val unsafe.Pointer)"}, {"StoreUint32", Func, 0, "func(addr *uint32, val uint32)"}, {"StoreUint64", Func, 0, "func(addr *uint64, val uint64)"}, {"StoreUintptr", Func, 0, "func(addr *uintptr, val uintptr)"}, {"SwapInt32", Func, 2, "func(addr *int32, new int32) (old int32)"}, {"SwapInt64", Func, 2, "func(addr *int64, new int64) (old int64)"}, {"SwapPointer", Func, 2, "func(addr *unsafe.Pointer, new unsafe.Pointer) (old unsafe.Pointer)"}, {"SwapUint32", Func, 2, "func(addr *uint32, new uint32) (old uint32)"}, {"SwapUint64", Func, 2, "func(addr *uint64, new uint64) (old uint64)"}, {"SwapUintptr", Func, 2, "func(addr *uintptr, new uintptr) (old uintptr)"}, {"Uint32", Type, 19, ""}, {"Uint64", Type, 19, ""}, {"Uintptr", Type, 19, ""}, {"Value", Type, 4, ""}, }, "syscall": { {"(*Cmsghdr).SetLen", Method, 0, ""}, {"(*DLL).FindProc", Method, 0, ""}, {"(*DLL).MustFindProc", Method, 0, ""}, {"(*DLL).Release", Method, 0, ""}, {"(*DLLError).Error", Method, 0, ""}, {"(*DLLError).Unwrap", Method, 16, ""}, {"(*Filetime).Nanoseconds", Method, 0, ""}, {"(*Iovec).SetLen", Method, 0, ""}, {"(*LazyDLL).Handle", Method, 0, ""}, {"(*LazyDLL).Load", Method, 0, ""}, {"(*LazyDLL).NewProc", Method, 0, ""}, {"(*LazyProc).Addr", Method, 0, ""}, {"(*LazyProc).Call", Method, 0, ""}, {"(*LazyProc).Find", Method, 0, ""}, {"(*Msghdr).SetControllen", Method, 0, ""}, {"(*Proc).Addr", Method, 0, ""}, {"(*Proc).Call", Method, 0, ""}, {"(*PtraceRegs).PC", Method, 0, ""}, {"(*PtraceRegs).SetPC", Method, 0, ""}, {"(*RawSockaddrAny).Sockaddr", Method, 0, ""}, {"(*SID).Copy", Method, 0, ""}, {"(*SID).Len", Method, 0, ""}, {"(*SID).LookupAccount", Method, 0, ""}, {"(*SID).String", Method, 0, ""}, {"(*Timespec).Nano", Method, 0, ""}, {"(*Timespec).Unix", Method, 0, ""}, {"(*Timeval).Nano", Method, 0, ""}, {"(*Timeval).Nanoseconds", Method, 0, ""}, {"(*Timeval).Unix", Method, 0, ""}, {"(Errno).Error", Method, 0, ""}, {"(Errno).Is", Method, 13, ""}, {"(Errno).Temporary", Method, 0, ""}, {"(Errno).Timeout", Method, 0, ""}, {"(Signal).Signal", Method, 0, ""}, {"(Signal).String", Method, 0, ""}, {"(Token).Close", Method, 0, ""}, {"(Token).GetTokenPrimaryGroup", Method, 0, ""}, {"(Token).GetTokenUser", Method, 0, ""}, {"(Token).GetUserProfileDirectory", Method, 0, ""}, {"(WaitStatus).Continued", Method, 0, ""}, {"(WaitStatus).CoreDump", Method, 0, ""}, {"(WaitStatus).ExitStatus", Method, 0, ""}, {"(WaitStatus).Exited", Method, 0, ""}, {"(WaitStatus).Signal", Method, 0, ""}, {"(WaitStatus).Signaled", Method, 0, ""}, {"(WaitStatus).StopSignal", Method, 0, ""}, {"(WaitStatus).Stopped", Method, 0, ""}, {"(WaitStatus).TrapCause", Method, 0, ""}, {"AF_ALG", Const, 0, ""}, {"AF_APPLETALK", Const, 0, ""}, {"AF_ARP", Const, 0, ""}, {"AF_ASH", Const, 0, ""}, {"AF_ATM", Const, 0, ""}, {"AF_ATMPVC", Const, 0, ""}, {"AF_ATMSVC", Const, 0, ""}, {"AF_AX25", Const, 0, ""}, {"AF_BLUETOOTH", Const, 0, ""}, {"AF_BRIDGE", Const, 0, ""}, {"AF_CAIF", Const, 0, ""}, {"AF_CAN", Const, 0, ""}, {"AF_CCITT", Const, 0, ""}, {"AF_CHAOS", Const, 0, ""}, {"AF_CNT", Const, 0, ""}, {"AF_COIP", Const, 0, ""}, {"AF_DATAKIT", Const, 0, ""}, {"AF_DECnet", Const, 0, ""}, {"AF_DLI", Const, 0, ""}, {"AF_E164", Const, 0, ""}, {"AF_ECMA", Const, 0, ""}, {"AF_ECONET", Const, 0, ""}, {"AF_ENCAP", Const, 1, ""}, {"AF_FILE", Const, 0, ""}, {"AF_HYLINK", Const, 0, ""}, {"AF_IEEE80211", Const, 0, ""}, {"AF_IEEE802154", Const, 0, ""}, {"AF_IMPLINK", Const, 0, ""}, {"AF_INET", Const, 0, ""}, {"AF_INET6", Const, 0, ""}, {"AF_INET6_SDP", Const, 3, ""}, {"AF_INET_SDP", Const, 3, ""}, {"AF_IPX", Const, 0, ""}, {"AF_IRDA", Const, 0, ""}, {"AF_ISDN", Const, 0, ""}, {"AF_ISO", Const, 0, ""}, {"AF_IUCV", Const, 0, ""}, {"AF_KEY", Const, 0, ""}, {"AF_LAT", Const, 0, ""}, {"AF_LINK", Const, 0, ""}, {"AF_LLC", Const, 0, ""}, {"AF_LOCAL", Const, 0, ""}, {"AF_MAX", Const, 0, ""}, {"AF_MPLS", Const, 1, ""}, {"AF_NATM", Const, 0, ""}, {"AF_NDRV", Const, 0, ""}, {"AF_NETBEUI", Const, 0, ""}, {"AF_NETBIOS", Const, 0, ""}, {"AF_NETGRAPH", Const, 0, ""}, {"AF_NETLINK", Const, 0, ""}, {"AF_NETROM", Const, 0, ""}, {"AF_NS", Const, 0, ""}, {"AF_OROUTE", Const, 1, ""}, {"AF_OSI", Const, 0, ""}, {"AF_PACKET", Const, 0, ""}, {"AF_PHONET", Const, 0, ""}, {"AF_PPP", Const, 0, ""}, {"AF_PPPOX", Const, 0, ""}, {"AF_PUP", Const, 0, ""}, {"AF_RDS", Const, 0, ""}, {"AF_RESERVED_36", Const, 0, ""}, {"AF_ROSE", Const, 0, ""}, {"AF_ROUTE", Const, 0, ""}, {"AF_RXRPC", Const, 0, ""}, {"AF_SCLUSTER", Const, 0, ""}, {"AF_SECURITY", Const, 0, ""}, {"AF_SIP", Const, 0, ""}, {"AF_SLOW", Const, 0, ""}, {"AF_SNA", Const, 0, ""}, {"AF_SYSTEM", Const, 0, ""}, {"AF_TIPC", Const, 0, ""}, {"AF_UNIX", Const, 0, ""}, {"AF_UNSPEC", Const, 0, ""}, {"AF_UTUN", Const, 16, ""}, {"AF_VENDOR00", Const, 0, ""}, {"AF_VENDOR01", Const, 0, ""}, {"AF_VENDOR02", Const, 0, ""}, {"AF_VENDOR03", Const, 0, ""}, {"AF_VENDOR04", Const, 0, ""}, {"AF_VENDOR05", Const, 0, ""}, {"AF_VENDOR06", Const, 0, ""}, {"AF_VENDOR07", Const, 0, ""}, {"AF_VENDOR08", Const, 0, ""}, {"AF_VENDOR09", Const, 0, ""}, {"AF_VENDOR10", Const, 0, ""}, {"AF_VENDOR11", Const, 0, ""}, {"AF_VENDOR12", Const, 0, ""}, {"AF_VENDOR13", Const, 0, ""}, {"AF_VENDOR14", Const, 0, ""}, {"AF_VENDOR15", Const, 0, ""}, {"AF_VENDOR16", Const, 0, ""}, {"AF_VENDOR17", Const, 0, ""}, {"AF_VENDOR18", Const, 0, ""}, {"AF_VENDOR19", Const, 0, ""}, {"AF_VENDOR20", Const, 0, ""}, {"AF_VENDOR21", Const, 0, ""}, {"AF_VENDOR22", Const, 0, ""}, {"AF_VENDOR23", Const, 0, ""}, {"AF_VENDOR24", Const, 0, ""}, {"AF_VENDOR25", Const, 0, ""}, {"AF_VENDOR26", Const, 0, ""}, {"AF_VENDOR27", Const, 0, ""}, {"AF_VENDOR28", Const, 0, ""}, {"AF_VENDOR29", Const, 0, ""}, {"AF_VENDOR30", Const, 0, ""}, {"AF_VENDOR31", Const, 0, ""}, {"AF_VENDOR32", Const, 0, ""}, {"AF_VENDOR33", Const, 0, ""}, {"AF_VENDOR34", Const, 0, ""}, {"AF_VENDOR35", Const, 0, ""}, {"AF_VENDOR36", Const, 0, ""}, {"AF_VENDOR37", Const, 0, ""}, {"AF_VENDOR38", Const, 0, ""}, {"AF_VENDOR39", Const, 0, ""}, {"AF_VENDOR40", Const, 0, ""}, {"AF_VENDOR41", Const, 0, ""}, {"AF_VENDOR42", Const, 0, ""}, {"AF_VENDOR43", Const, 0, ""}, {"AF_VENDOR44", Const, 0, ""}, {"AF_VENDOR45", Const, 0, ""}, {"AF_VENDOR46", Const, 0, ""}, {"AF_VENDOR47", Const, 0, ""}, {"AF_WANPIPE", Const, 0, ""}, {"AF_X25", Const, 0, ""}, {"AI_CANONNAME", Const, 1, ""}, {"AI_NUMERICHOST", Const, 1, ""}, {"AI_PASSIVE", Const, 1, ""}, {"APPLICATION_ERROR", Const, 0, ""}, {"ARPHRD_ADAPT", Const, 0, ""}, {"ARPHRD_APPLETLK", Const, 0, ""}, {"ARPHRD_ARCNET", Const, 0, ""}, {"ARPHRD_ASH", Const, 0, ""}, {"ARPHRD_ATM", Const, 0, ""}, {"ARPHRD_AX25", Const, 0, ""}, {"ARPHRD_BIF", Const, 0, ""}, {"ARPHRD_CHAOS", Const, 0, ""}, {"ARPHRD_CISCO", Const, 0, ""}, {"ARPHRD_CSLIP", Const, 0, ""}, {"ARPHRD_CSLIP6", Const, 0, ""}, {"ARPHRD_DDCMP", Const, 0, ""}, {"ARPHRD_DLCI", Const, 0, ""}, {"ARPHRD_ECONET", Const, 0, ""}, {"ARPHRD_EETHER", Const, 0, ""}, {"ARPHRD_ETHER", Const, 0, ""}, {"ARPHRD_EUI64", Const, 0, ""}, {"ARPHRD_FCAL", Const, 0, ""}, {"ARPHRD_FCFABRIC", Const, 0, ""}, {"ARPHRD_FCPL", Const, 0, ""}, {"ARPHRD_FCPP", Const, 0, ""}, {"ARPHRD_FDDI", Const, 0, ""}, {"ARPHRD_FRAD", Const, 0, ""}, {"ARPHRD_FRELAY", Const, 1, ""}, {"ARPHRD_HDLC", Const, 0, ""}, {"ARPHRD_HIPPI", Const, 0, ""}, {"ARPHRD_HWX25", Const, 0, ""}, {"ARPHRD_IEEE1394", Const, 0, ""}, {"ARPHRD_IEEE802", Const, 0, ""}, {"ARPHRD_IEEE80211", Const, 0, ""}, {"ARPHRD_IEEE80211_PRISM", Const, 0, ""}, {"ARPHRD_IEEE80211_RADIOTAP", Const, 0, ""}, {"ARPHRD_IEEE802154", Const, 0, ""}, {"ARPHRD_IEEE802154_PHY", Const, 0, ""}, {"ARPHRD_IEEE802_TR", Const, 0, ""}, {"ARPHRD_INFINIBAND", Const, 0, ""}, {"ARPHRD_IPDDP", Const, 0, ""}, {"ARPHRD_IPGRE", Const, 0, ""}, {"ARPHRD_IRDA", Const, 0, ""}, {"ARPHRD_LAPB", Const, 0, ""}, {"ARPHRD_LOCALTLK", Const, 0, ""}, {"ARPHRD_LOOPBACK", Const, 0, ""}, {"ARPHRD_METRICOM", Const, 0, ""}, {"ARPHRD_NETROM", Const, 0, ""}, {"ARPHRD_NONE", Const, 0, ""}, {"ARPHRD_PIMREG", Const, 0, ""}, {"ARPHRD_PPP", Const, 0, ""}, {"ARPHRD_PRONET", Const, 0, ""}, {"ARPHRD_RAWHDLC", Const, 0, ""}, {"ARPHRD_ROSE", Const, 0, ""}, {"ARPHRD_RSRVD", Const, 0, ""}, {"ARPHRD_SIT", Const, 0, ""}, {"ARPHRD_SKIP", Const, 0, ""}, {"ARPHRD_SLIP", Const, 0, ""}, {"ARPHRD_SLIP6", Const, 0, ""}, {"ARPHRD_STRIP", Const, 1, ""}, {"ARPHRD_TUNNEL", Const, 0, ""}, {"ARPHRD_TUNNEL6", Const, 0, ""}, {"ARPHRD_VOID", Const, 0, ""}, {"ARPHRD_X25", Const, 0, ""}, {"AUTHTYPE_CLIENT", Const, 0, ""}, {"AUTHTYPE_SERVER", Const, 0, ""}, {"Accept", Func, 0, "func(fd int) (nfd int, sa Sockaddr, err error)"}, {"Accept4", Func, 1, "func(fd int, flags int) (nfd int, sa Sockaddr, err error)"}, {"AcceptEx", Func, 0, ""}, {"Access", Func, 0, "func(path string, mode uint32) (err error)"}, {"Acct", Func, 0, "func(path string) (err error)"}, {"AddrinfoW", Type, 1, ""}, {"AddrinfoW.Addr", Field, 1, ""}, {"AddrinfoW.Addrlen", Field, 1, ""}, {"AddrinfoW.Canonname", Field, 1, ""}, {"AddrinfoW.Family", Field, 1, ""}, {"AddrinfoW.Flags", Field, 1, ""}, {"AddrinfoW.Next", Field, 1, ""}, {"AddrinfoW.Protocol", Field, 1, ""}, {"AddrinfoW.Socktype", Field, 1, ""}, {"Adjtime", Func, 0, ""}, {"Adjtimex", Func, 0, "func(buf *Timex) (state int, err error)"}, {"AllThreadsSyscall", Func, 16, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, {"AllThreadsSyscall6", Func, 16, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr, a4 uintptr, a5 uintptr, a6 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, {"AttachLsf", Func, 0, "func(fd int, i []SockFilter) error"}, {"B0", Const, 0, ""}, {"B1000000", Const, 0, ""}, {"B110", Const, 0, ""}, {"B115200", Const, 0, ""}, {"B1152000", Const, 0, ""}, {"B1200", Const, 0, ""}, {"B134", Const, 0, ""}, {"B14400", Const, 1, ""}, {"B150", Const, 0, ""}, {"B1500000", Const, 0, ""}, {"B1800", Const, 0, ""}, {"B19200", Const, 0, ""}, {"B200", Const, 0, ""}, {"B2000000", Const, 0, ""}, {"B230400", Const, 0, ""}, {"B2400", Const, 0, ""}, {"B2500000", Const, 0, ""}, {"B28800", Const, 1, ""}, {"B300", Const, 0, ""}, {"B3000000", Const, 0, ""}, {"B3500000", Const, 0, ""}, {"B38400", Const, 0, ""}, {"B4000000", Const, 0, ""}, {"B460800", Const, 0, ""}, {"B4800", Const, 0, ""}, {"B50", Const, 0, ""}, {"B500000", Const, 0, ""}, {"B57600", Const, 0, ""}, {"B576000", Const, 0, ""}, {"B600", Const, 0, ""}, {"B7200", Const, 1, ""}, {"B75", Const, 0, ""}, {"B76800", Const, 1, ""}, {"B921600", Const, 0, ""}, {"B9600", Const, 0, ""}, {"BASE_PROTOCOL", Const, 2, ""}, {"BIOCFEEDBACK", Const, 0, ""}, {"BIOCFLUSH", Const, 0, ""}, {"BIOCGBLEN", Const, 0, ""}, {"BIOCGDIRECTION", Const, 0, ""}, {"BIOCGDIRFILT", Const, 1, ""}, {"BIOCGDLT", Const, 0, ""}, {"BIOCGDLTLIST", Const, 0, ""}, {"BIOCGETBUFMODE", Const, 0, ""}, {"BIOCGETIF", Const, 0, ""}, {"BIOCGETZMAX", Const, 0, ""}, {"BIOCGFEEDBACK", Const, 1, ""}, {"BIOCGFILDROP", Const, 1, ""}, {"BIOCGHDRCMPLT", Const, 0, ""}, {"BIOCGRSIG", Const, 0, ""}, {"BIOCGRTIMEOUT", Const, 0, ""}, {"BIOCGSEESENT", Const, 0, ""}, {"BIOCGSTATS", Const, 0, ""}, {"BIOCGSTATSOLD", Const, 1, ""}, {"BIOCGTSTAMP", Const, 1, ""}, {"BIOCIMMEDIATE", Const, 0, ""}, {"BIOCLOCK", Const, 0, ""}, {"BIOCPROMISC", Const, 0, ""}, {"BIOCROTZBUF", Const, 0, ""}, {"BIOCSBLEN", Const, 0, ""}, {"BIOCSDIRECTION", Const, 0, ""}, {"BIOCSDIRFILT", Const, 1, ""}, {"BIOCSDLT", Const, 0, ""}, {"BIOCSETBUFMODE", Const, 0, ""}, {"BIOCSETF", Const, 0, ""}, {"BIOCSETFNR", Const, 0, ""}, {"BIOCSETIF", Const, 0, ""}, {"BIOCSETWF", Const, 0, ""}, {"BIOCSETZBUF", Const, 0, ""}, {"BIOCSFEEDBACK", Const, 1, ""}, {"BIOCSFILDROP", Const, 1, ""}, {"BIOCSHDRCMPLT", Const, 0, ""}, {"BIOCSRSIG", Const, 0, ""}, {"BIOCSRTIMEOUT", Const, 0, ""}, {"BIOCSSEESENT", Const, 0, ""}, {"BIOCSTCPF", Const, 1, ""}, {"BIOCSTSTAMP", Const, 1, ""}, {"BIOCSUDPF", Const, 1, ""}, {"BIOCVERSION", Const, 0, ""}, {"BPF_A", Const, 0, ""}, {"BPF_ABS", Const, 0, ""}, {"BPF_ADD", Const, 0, ""}, {"BPF_ALIGNMENT", Const, 0, ""}, {"BPF_ALIGNMENT32", Const, 1, ""}, {"BPF_ALU", Const, 0, ""}, {"BPF_AND", Const, 0, ""}, {"BPF_B", Const, 0, ""}, {"BPF_BUFMODE_BUFFER", Const, 0, ""}, {"BPF_BUFMODE_ZBUF", Const, 0, ""}, {"BPF_DFLTBUFSIZE", Const, 1, ""}, {"BPF_DIRECTION_IN", Const, 1, ""}, {"BPF_DIRECTION_OUT", Const, 1, ""}, {"BPF_DIV", Const, 0, ""}, {"BPF_H", Const, 0, ""}, {"BPF_IMM", Const, 0, ""}, {"BPF_IND", Const, 0, ""}, {"BPF_JA", Const, 0, ""}, {"BPF_JEQ", Const, 0, ""}, {"BPF_JGE", Const, 0, ""}, {"BPF_JGT", Const, 0, ""}, {"BPF_JMP", Const, 0, ""}, {"BPF_JSET", Const, 0, ""}, {"BPF_K", Const, 0, ""}, {"BPF_LD", Const, 0, ""}, {"BPF_LDX", Const, 0, ""}, {"BPF_LEN", Const, 0, ""}, {"BPF_LSH", Const, 0, ""}, {"BPF_MAJOR_VERSION", Const, 0, ""}, {"BPF_MAXBUFSIZE", Const, 0, ""}, {"BPF_MAXINSNS", Const, 0, ""}, {"BPF_MEM", Const, 0, ""}, {"BPF_MEMWORDS", Const, 0, ""}, {"BPF_MINBUFSIZE", Const, 0, ""}, {"BPF_MINOR_VERSION", Const, 0, ""}, {"BPF_MISC", Const, 0, ""}, {"BPF_MSH", Const, 0, ""}, {"BPF_MUL", Const, 0, ""}, {"BPF_NEG", Const, 0, ""}, {"BPF_OR", Const, 0, ""}, {"BPF_RELEASE", Const, 0, ""}, {"BPF_RET", Const, 0, ""}, {"BPF_RSH", Const, 0, ""}, {"BPF_ST", Const, 0, ""}, {"BPF_STX", Const, 0, ""}, {"BPF_SUB", Const, 0, ""}, {"BPF_TAX", Const, 0, ""}, {"BPF_TXA", Const, 0, ""}, {"BPF_T_BINTIME", Const, 1, ""}, {"BPF_T_BINTIME_FAST", Const, 1, ""}, {"BPF_T_BINTIME_MONOTONIC", Const, 1, ""}, {"BPF_T_BINTIME_MONOTONIC_FAST", Const, 1, ""}, {"BPF_T_FAST", Const, 1, ""}, {"BPF_T_FLAG_MASK", Const, 1, ""}, {"BPF_T_FORMAT_MASK", Const, 1, ""}, {"BPF_T_MICROTIME", Const, 1, ""}, {"BPF_T_MICROTIME_FAST", Const, 1, ""}, {"BPF_T_MICROTIME_MONOTONIC", Const, 1, ""}, {"BPF_T_MICROTIME_MONOTONIC_FAST", Const, 1, ""}, {"BPF_T_MONOTONIC", Const, 1, ""}, {"BPF_T_MONOTONIC_FAST", Const, 1, ""}, {"BPF_T_NANOTIME", Const, 1, ""}, {"BPF_T_NANOTIME_FAST", Const, 1, ""}, {"BPF_T_NANOTIME_MONOTONIC", Const, 1, ""}, {"BPF_T_NANOTIME_MONOTONIC_FAST", Const, 1, ""}, {"BPF_T_NONE", Const, 1, ""}, {"BPF_T_NORMAL", Const, 1, ""}, {"BPF_W", Const, 0, ""}, {"BPF_X", Const, 0, ""}, {"BRKINT", Const, 0, ""}, {"Bind", Func, 0, "func(fd int, sa Sockaddr) (err error)"}, {"BindToDevice", Func, 0, "func(fd int, device string) (err error)"}, {"BpfBuflen", Func, 0, ""}, {"BpfDatalink", Func, 0, ""}, {"BpfHdr", Type, 0, ""}, {"BpfHdr.Caplen", Field, 0, ""}, {"BpfHdr.Datalen", Field, 0, ""}, {"BpfHdr.Hdrlen", Field, 0, ""}, {"BpfHdr.Pad_cgo_0", Field, 0, ""}, {"BpfHdr.Tstamp", Field, 0, ""}, {"BpfHeadercmpl", Func, 0, ""}, {"BpfInsn", Type, 0, ""}, {"BpfInsn.Code", Field, 0, ""}, {"BpfInsn.Jf", Field, 0, ""}, {"BpfInsn.Jt", Field, 0, ""}, {"BpfInsn.K", Field, 0, ""}, {"BpfInterface", Func, 0, ""}, {"BpfJump", Func, 0, ""}, {"BpfProgram", Type, 0, ""}, {"BpfProgram.Insns", Field, 0, ""}, {"BpfProgram.Len", Field, 0, ""}, {"BpfProgram.Pad_cgo_0", Field, 0, ""}, {"BpfStat", Type, 0, ""}, {"BpfStat.Capt", Field, 2, ""}, {"BpfStat.Drop", Field, 0, ""}, {"BpfStat.Padding", Field, 2, ""}, {"BpfStat.Recv", Field, 0, ""}, {"BpfStats", Func, 0, ""}, {"BpfStmt", Func, 0, ""}, {"BpfTimeout", Func, 0, ""}, {"BpfTimeval", Type, 2, ""}, {"BpfTimeval.Sec", Field, 2, ""}, {"BpfTimeval.Usec", Field, 2, ""}, {"BpfVersion", Type, 0, ""}, {"BpfVersion.Major", Field, 0, ""}, {"BpfVersion.Minor", Field, 0, ""}, {"BpfZbuf", Type, 0, ""}, {"BpfZbuf.Bufa", Field, 0, ""}, {"BpfZbuf.Bufb", Field, 0, ""}, {"BpfZbuf.Buflen", Field, 0, ""}, {"BpfZbufHeader", Type, 0, ""}, {"BpfZbufHeader.Kernel_gen", Field, 0, ""}, {"BpfZbufHeader.Kernel_len", Field, 0, ""}, {"BpfZbufHeader.User_gen", Field, 0, ""}, {"BpfZbufHeader.X_bzh_pad", Field, 0, ""}, {"ByHandleFileInformation", Type, 0, ""}, {"ByHandleFileInformation.CreationTime", Field, 0, ""}, {"ByHandleFileInformation.FileAttributes", Field, 0, ""}, {"ByHandleFileInformation.FileIndexHigh", Field, 0, ""}, {"ByHandleFileInformation.FileIndexLow", Field, 0, ""}, {"ByHandleFileInformation.FileSizeHigh", Field, 0, ""}, {"ByHandleFileInformation.FileSizeLow", Field, 0, ""}, {"ByHandleFileInformation.LastAccessTime", Field, 0, ""}, {"ByHandleFileInformation.LastWriteTime", Field, 0, ""}, {"ByHandleFileInformation.NumberOfLinks", Field, 0, ""}, {"ByHandleFileInformation.VolumeSerialNumber", Field, 0, ""}, {"BytePtrFromString", Func, 1, "func(s string) (*byte, error)"}, {"ByteSliceFromString", Func, 1, "func(s string) ([]byte, error)"}, {"CCR0_FLUSH", Const, 1, ""}, {"CERT_CHAIN_POLICY_AUTHENTICODE", Const, 0, ""}, {"CERT_CHAIN_POLICY_AUTHENTICODE_TS", Const, 0, ""}, {"CERT_CHAIN_POLICY_BASE", Const, 0, ""}, {"CERT_CHAIN_POLICY_BASIC_CONSTRAINTS", Const, 0, ""}, {"CERT_CHAIN_POLICY_EV", Const, 0, ""}, {"CERT_CHAIN_POLICY_MICROSOFT_ROOT", Const, 0, ""}, {"CERT_CHAIN_POLICY_NT_AUTH", Const, 0, ""}, {"CERT_CHAIN_POLICY_SSL", Const, 0, ""}, {"CERT_E_CN_NO_MATCH", Const, 0, ""}, {"CERT_E_EXPIRED", Const, 0, ""}, {"CERT_E_PURPOSE", Const, 0, ""}, {"CERT_E_ROLE", Const, 0, ""}, {"CERT_E_UNTRUSTEDROOT", Const, 0, ""}, {"CERT_STORE_ADD_ALWAYS", Const, 0, ""}, {"CERT_STORE_DEFER_CLOSE_UNTIL_LAST_FREE_FLAG", Const, 0, ""}, {"CERT_STORE_PROV_MEMORY", Const, 0, ""}, {"CERT_TRUST_HAS_EXCLUDED_NAME_CONSTRAINT", Const, 0, ""}, {"CERT_TRUST_HAS_NOT_DEFINED_NAME_CONSTRAINT", Const, 0, ""}, {"CERT_TRUST_HAS_NOT_PERMITTED_NAME_CONSTRAINT", Const, 0, ""}, {"CERT_TRUST_HAS_NOT_SUPPORTED_CRITICAL_EXT", Const, 0, ""}, {"CERT_TRUST_HAS_NOT_SUPPORTED_NAME_CONSTRAINT", Const, 0, ""}, {"CERT_TRUST_INVALID_BASIC_CONSTRAINTS", Const, 0, ""}, {"CERT_TRUST_INVALID_EXTENSION", Const, 0, ""}, {"CERT_TRUST_INVALID_NAME_CONSTRAINTS", Const, 0, ""}, {"CERT_TRUST_INVALID_POLICY_CONSTRAINTS", Const, 0, ""}, {"CERT_TRUST_IS_CYCLIC", Const, 0, ""}, {"CERT_TRUST_IS_EXPLICIT_DISTRUST", Const, 0, ""}, {"CERT_TRUST_IS_NOT_SIGNATURE_VALID", Const, 0, ""}, {"CERT_TRUST_IS_NOT_TIME_VALID", Const, 0, ""}, {"CERT_TRUST_IS_NOT_VALID_FOR_USAGE", Const, 0, ""}, {"CERT_TRUST_IS_OFFLINE_REVOCATION", Const, 0, ""}, {"CERT_TRUST_IS_REVOKED", Const, 0, ""}, {"CERT_TRUST_IS_UNTRUSTED_ROOT", Const, 0, ""}, {"CERT_TRUST_NO_ERROR", Const, 0, ""}, {"CERT_TRUST_NO_ISSUANCE_CHAIN_POLICY", Const, 0, ""}, {"CERT_TRUST_REVOCATION_STATUS_UNKNOWN", Const, 0, ""}, {"CFLUSH", Const, 1, ""}, {"CLOCAL", Const, 0, ""}, {"CLONE_CHILD_CLEARTID", Const, 2, ""}, {"CLONE_CHILD_SETTID", Const, 2, ""}, {"CLONE_CLEAR_SIGHAND", Const, 20, ""}, {"CLONE_CSIGNAL", Const, 3, ""}, {"CLONE_DETACHED", Const, 2, ""}, {"CLONE_FILES", Const, 2, ""}, {"CLONE_FS", Const, 2, ""}, {"CLONE_INTO_CGROUP", Const, 20, ""}, {"CLONE_IO", Const, 2, ""}, {"CLONE_NEWCGROUP", Const, 20, ""}, {"CLONE_NEWIPC", Const, 2, ""}, {"CLONE_NEWNET", Const, 2, ""}, {"CLONE_NEWNS", Const, 2, ""}, {"CLONE_NEWPID", Const, 2, ""}, {"CLONE_NEWTIME", Const, 20, ""}, {"CLONE_NEWUSER", Const, 2, ""}, {"CLONE_NEWUTS", Const, 2, ""}, {"CLONE_PARENT", Const, 2, ""}, {"CLONE_PARENT_SETTID", Const, 2, ""}, {"CLONE_PID", Const, 3, ""}, {"CLONE_PIDFD", Const, 20, ""}, {"CLONE_PTRACE", Const, 2, ""}, {"CLONE_SETTLS", Const, 2, ""}, {"CLONE_SIGHAND", Const, 2, ""}, {"CLONE_SYSVSEM", Const, 2, ""}, {"CLONE_THREAD", Const, 2, ""}, {"CLONE_UNTRACED", Const, 2, ""}, {"CLONE_VFORK", Const, 2, ""}, {"CLONE_VM", Const, 2, ""}, {"CPUID_CFLUSH", Const, 1, ""}, {"CREAD", Const, 0, ""}, {"CREATE_ALWAYS", Const, 0, ""}, {"CREATE_NEW", Const, 0, ""}, {"CREATE_NEW_PROCESS_GROUP", Const, 1, ""}, {"CREATE_UNICODE_ENVIRONMENT", Const, 0, ""}, {"CRYPT_DEFAULT_CONTAINER_OPTIONAL", Const, 0, ""}, {"CRYPT_DELETEKEYSET", Const, 0, ""}, {"CRYPT_MACHINE_KEYSET", Const, 0, ""}, {"CRYPT_NEWKEYSET", Const, 0, ""}, {"CRYPT_SILENT", Const, 0, ""}, {"CRYPT_VERIFYCONTEXT", Const, 0, ""}, {"CS5", Const, 0, ""}, {"CS6", Const, 0, ""}, {"CS7", Const, 0, ""}, {"CS8", Const, 0, ""}, {"CSIZE", Const, 0, ""}, {"CSTART", Const, 1, ""}, {"CSTATUS", Const, 1, ""}, {"CSTOP", Const, 1, ""}, {"CSTOPB", Const, 0, ""}, {"CSUSP", Const, 1, ""}, {"CTL_MAXNAME", Const, 0, ""}, {"CTL_NET", Const, 0, ""}, {"CTL_QUERY", Const, 1, ""}, {"CTRL_BREAK_EVENT", Const, 1, ""}, {"CTRL_CLOSE_EVENT", Const, 14, ""}, {"CTRL_C_EVENT", Const, 1, ""}, {"CTRL_LOGOFF_EVENT", Const, 14, ""}, {"CTRL_SHUTDOWN_EVENT", Const, 14, ""}, {"CancelIo", Func, 0, ""}, {"CancelIoEx", Func, 1, ""}, {"CertAddCertificateContextToStore", Func, 0, ""}, {"CertChainContext", Type, 0, ""}, {"CertChainContext.ChainCount", Field, 0, ""}, {"CertChainContext.Chains", Field, 0, ""}, {"CertChainContext.HasRevocationFreshnessTime", Field, 0, ""}, {"CertChainContext.LowerQualityChainCount", Field, 0, ""}, {"CertChainContext.LowerQualityChains", Field, 0, ""}, {"CertChainContext.RevocationFreshnessTime", Field, 0, ""}, {"CertChainContext.Size", Field, 0, ""}, {"CertChainContext.TrustStatus", Field, 0, ""}, {"CertChainElement", Type, 0, ""}, {"CertChainElement.ApplicationUsage", Field, 0, ""}, {"CertChainElement.CertContext", Field, 0, ""}, {"CertChainElement.ExtendedErrorInfo", Field, 0, ""}, {"CertChainElement.IssuanceUsage", Field, 0, ""}, {"CertChainElement.RevocationInfo", Field, 0, ""}, {"CertChainElement.Size", Field, 0, ""}, {"CertChainElement.TrustStatus", Field, 0, ""}, {"CertChainPara", Type, 0, ""}, {"CertChainPara.CacheResync", Field, 0, ""}, {"CertChainPara.CheckRevocationFreshnessTime", Field, 0, ""}, {"CertChainPara.RequestedUsage", Field, 0, ""}, {"CertChainPara.RequstedIssuancePolicy", Field, 0, ""}, {"CertChainPara.RevocationFreshnessTime", Field, 0, ""}, {"CertChainPara.Size", Field, 0, ""}, {"CertChainPara.URLRetrievalTimeout", Field, 0, ""}, {"CertChainPolicyPara", Type, 0, ""}, {"CertChainPolicyPara.ExtraPolicyPara", Field, 0, ""}, {"CertChainPolicyPara.Flags", Field, 0, ""}, {"CertChainPolicyPara.Size", Field, 0, ""}, {"CertChainPolicyStatus", Type, 0, ""}, {"CertChainPolicyStatus.ChainIndex", Field, 0, ""}, {"CertChainPolicyStatus.ElementIndex", Field, 0, ""}, {"CertChainPolicyStatus.Error", Field, 0, ""}, {"CertChainPolicyStatus.ExtraPolicyStatus", Field, 0, ""}, {"CertChainPolicyStatus.Size", Field, 0, ""}, {"CertCloseStore", Func, 0, ""}, {"CertContext", Type, 0, ""}, {"CertContext.CertInfo", Field, 0, ""}, {"CertContext.EncodedCert", Field, 0, ""}, {"CertContext.EncodingType", Field, 0, ""}, {"CertContext.Length", Field, 0, ""}, {"CertContext.Store", Field, 0, ""}, {"CertCreateCertificateContext", Func, 0, ""}, {"CertEnhKeyUsage", Type, 0, ""}, {"CertEnhKeyUsage.Length", Field, 0, ""}, {"CertEnhKeyUsage.UsageIdentifiers", Field, 0, ""}, {"CertEnumCertificatesInStore", Func, 0, ""}, {"CertFreeCertificateChain", Func, 0, ""}, {"CertFreeCertificateContext", Func, 0, ""}, {"CertGetCertificateChain", Func, 0, ""}, {"CertInfo", Type, 11, ""}, {"CertOpenStore", Func, 0, ""}, {"CertOpenSystemStore", Func, 0, ""}, {"CertRevocationCrlInfo", Type, 11, ""}, {"CertRevocationInfo", Type, 0, ""}, {"CertRevocationInfo.CrlInfo", Field, 0, ""}, {"CertRevocationInfo.FreshnessTime", Field, 0, ""}, {"CertRevocationInfo.HasFreshnessTime", Field, 0, ""}, {"CertRevocationInfo.OidSpecificInfo", Field, 0, ""}, {"CertRevocationInfo.RevocationOid", Field, 0, ""}, {"CertRevocationInfo.RevocationResult", Field, 0, ""}, {"CertRevocationInfo.Size", Field, 0, ""}, {"CertSimpleChain", Type, 0, ""}, {"CertSimpleChain.Elements", Field, 0, ""}, {"CertSimpleChain.HasRevocationFreshnessTime", Field, 0, ""}, {"CertSimpleChain.NumElements", Field, 0, ""}, {"CertSimpleChain.RevocationFreshnessTime", Field, 0, ""}, {"CertSimpleChain.Size", Field, 0, ""}, {"CertSimpleChain.TrustListInfo", Field, 0, ""}, {"CertSimpleChain.TrustStatus", Field, 0, ""}, {"CertTrustListInfo", Type, 11, ""}, {"CertTrustStatus", Type, 0, ""}, {"CertTrustStatus.ErrorStatus", Field, 0, ""}, {"CertTrustStatus.InfoStatus", Field, 0, ""}, {"CertUsageMatch", Type, 0, ""}, {"CertUsageMatch.Type", Field, 0, ""}, {"CertUsageMatch.Usage", Field, 0, ""}, {"CertVerifyCertificateChainPolicy", Func, 0, ""}, {"Chdir", Func, 0, "func(path string) (err error)"}, {"CheckBpfVersion", Func, 0, ""}, {"Chflags", Func, 0, ""}, {"Chmod", Func, 0, "func(path string, mode uint32) (err error)"}, {"Chown", Func, 0, "func(path string, uid int, gid int) (err error)"}, {"Chroot", Func, 0, "func(path string) (err error)"}, {"Clearenv", Func, 0, "func()"}, {"Close", Func, 0, "func(fd int) (err error)"}, {"CloseHandle", Func, 0, ""}, {"CloseOnExec", Func, 0, "func(fd int)"}, {"Closesocket", Func, 0, ""}, {"CmsgLen", Func, 0, "func(datalen int) int"}, {"CmsgSpace", Func, 0, "func(datalen int) int"}, {"Cmsghdr", Type, 0, ""}, {"Cmsghdr.Len", Field, 0, ""}, {"Cmsghdr.Level", Field, 0, ""}, {"Cmsghdr.Type", Field, 0, ""}, {"Cmsghdr.X__cmsg_data", Field, 0, ""}, {"CommandLineToArgv", Func, 0, ""}, {"ComputerName", Func, 0, ""}, {"Conn", Type, 9, ""}, {"Connect", Func, 0, "func(fd int, sa Sockaddr) (err error)"}, {"ConnectEx", Func, 1, ""}, {"ConvertSidToStringSid", Func, 0, ""}, {"ConvertStringSidToSid", Func, 0, ""}, {"CopySid", Func, 0, ""}, {"Creat", Func, 0, "func(path string, mode uint32) (fd int, err error)"}, {"CreateDirectory", Func, 0, ""}, {"CreateFile", Func, 0, ""}, {"CreateFileMapping", Func, 0, ""}, {"CreateHardLink", Func, 4, ""}, {"CreateIoCompletionPort", Func, 0, ""}, {"CreatePipe", Func, 0, ""}, {"CreateProcess", Func, 0, ""}, {"CreateProcessAsUser", Func, 10, ""}, {"CreateSymbolicLink", Func, 4, ""}, {"CreateToolhelp32Snapshot", Func, 4, ""}, {"Credential", Type, 0, ""}, {"Credential.Gid", Field, 0, ""}, {"Credential.Groups", Field, 0, ""}, {"Credential.NoSetGroups", Field, 9, ""}, {"Credential.Uid", Field, 0, ""}, {"CryptAcquireContext", Func, 0, ""}, {"CryptGenRandom", Func, 0, ""}, {"CryptReleaseContext", Func, 0, ""}, {"DIOCBSFLUSH", Const, 1, ""}, {"DIOCOSFPFLUSH", Const, 1, ""}, {"DLL", Type, 0, ""}, {"DLL.Handle", Field, 0, ""}, {"DLL.Name", Field, 0, ""}, {"DLLError", Type, 0, ""}, {"DLLError.Err", Field, 0, ""}, {"DLLError.Msg", Field, 0, ""}, {"DLLError.ObjName", Field, 0, ""}, {"DLT_A429", Const, 0, ""}, {"DLT_A653_ICM", Const, 0, ""}, {"DLT_AIRONET_HEADER", Const, 0, ""}, {"DLT_AOS", Const, 1, ""}, {"DLT_APPLE_IP_OVER_IEEE1394", Const, 0, ""}, {"DLT_ARCNET", Const, 0, ""}, {"DLT_ARCNET_LINUX", Const, 0, ""}, {"DLT_ATM_CLIP", Const, 0, ""}, {"DLT_ATM_RFC1483", Const, 0, ""}, {"DLT_AURORA", Const, 0, ""}, {"DLT_AX25", Const, 0, ""}, {"DLT_AX25_KISS", Const, 0, ""}, {"DLT_BACNET_MS_TP", Const, 0, ""}, {"DLT_BLUETOOTH_HCI_H4", Const, 0, ""}, {"DLT_BLUETOOTH_HCI_H4_WITH_PHDR", Const, 0, ""}, {"DLT_CAN20B", Const, 0, ""}, {"DLT_CAN_SOCKETCAN", Const, 1, ""}, {"DLT_CHAOS", Const, 0, ""}, {"DLT_CHDLC", Const, 0, ""}, {"DLT_CISCO_IOS", Const, 0, ""}, {"DLT_C_HDLC", Const, 0, ""}, {"DLT_C_HDLC_WITH_DIR", Const, 0, ""}, {"DLT_DBUS", Const, 1, ""}, {"DLT_DECT", Const, 1, ""}, {"DLT_DOCSIS", Const, 0, ""}, {"DLT_DVB_CI", Const, 1, ""}, {"DLT_ECONET", Const, 0, ""}, {"DLT_EN10MB", Const, 0, ""}, {"DLT_EN3MB", Const, 0, ""}, {"DLT_ENC", Const, 0, ""}, {"DLT_ERF", Const, 0, ""}, {"DLT_ERF_ETH", Const, 0, ""}, {"DLT_ERF_POS", Const, 0, ""}, {"DLT_FC_2", Const, 1, ""}, {"DLT_FC_2_WITH_FRAME_DELIMS", Const, 1, ""}, {"DLT_FDDI", Const, 0, ""}, {"DLT_FLEXRAY", Const, 0, ""}, {"DLT_FRELAY", Const, 0, ""}, {"DLT_FRELAY_WITH_DIR", Const, 0, ""}, {"DLT_GCOM_SERIAL", Const, 0, ""}, {"DLT_GCOM_T1E1", Const, 0, ""}, {"DLT_GPF_F", Const, 0, ""}, {"DLT_GPF_T", Const, 0, ""}, {"DLT_GPRS_LLC", Const, 0, ""}, {"DLT_GSMTAP_ABIS", Const, 1, ""}, {"DLT_GSMTAP_UM", Const, 1, ""}, {"DLT_HDLC", Const, 1, ""}, {"DLT_HHDLC", Const, 0, ""}, {"DLT_HIPPI", Const, 1, ""}, {"DLT_IBM_SN", Const, 0, ""}, {"DLT_IBM_SP", Const, 0, ""}, {"DLT_IEEE802", Const, 0, ""}, {"DLT_IEEE802_11", Const, 0, ""}, {"DLT_IEEE802_11_RADIO", Const, 0, ""}, {"DLT_IEEE802_11_RADIO_AVS", Const, 0, ""}, {"DLT_IEEE802_15_4", Const, 0, ""}, {"DLT_IEEE802_15_4_LINUX", Const, 0, ""}, {"DLT_IEEE802_15_4_NOFCS", Const, 1, ""}, {"DLT_IEEE802_15_4_NONASK_PHY", Const, 0, ""}, {"DLT_IEEE802_16_MAC_CPS", Const, 0, ""}, {"DLT_IEEE802_16_MAC_CPS_RADIO", Const, 0, ""}, {"DLT_IPFILTER", Const, 0, ""}, {"DLT_IPMB", Const, 0, ""}, {"DLT_IPMB_LINUX", Const, 0, ""}, {"DLT_IPNET", Const, 1, ""}, {"DLT_IPOIB", Const, 1, ""}, {"DLT_IPV4", Const, 1, ""}, {"DLT_IPV6", Const, 1, ""}, {"DLT_IP_OVER_FC", Const, 0, ""}, {"DLT_JUNIPER_ATM1", Const, 0, ""}, {"DLT_JUNIPER_ATM2", Const, 0, ""}, {"DLT_JUNIPER_ATM_CEMIC", Const, 1, ""}, {"DLT_JUNIPER_CHDLC", Const, 0, ""}, {"DLT_JUNIPER_ES", Const, 0, ""}, {"DLT_JUNIPER_ETHER", Const, 0, ""}, {"DLT_JUNIPER_FIBRECHANNEL", Const, 1, ""}, {"DLT_JUNIPER_FRELAY", Const, 0, ""}, {"DLT_JUNIPER_GGSN", Const, 0, ""}, {"DLT_JUNIPER_ISM", Const, 0, ""}, {"DLT_JUNIPER_MFR", Const, 0, ""}, {"DLT_JUNIPER_MLFR", Const, 0, ""}, {"DLT_JUNIPER_MLPPP", Const, 0, ""}, {"DLT_JUNIPER_MONITOR", Const, 0, ""}, {"DLT_JUNIPER_PIC_PEER", Const, 0, ""}, {"DLT_JUNIPER_PPP", Const, 0, ""}, {"DLT_JUNIPER_PPPOE", Const, 0, ""}, {"DLT_JUNIPER_PPPOE_ATM", Const, 0, ""}, {"DLT_JUNIPER_SERVICES", Const, 0, ""}, {"DLT_JUNIPER_SRX_E2E", Const, 1, ""}, {"DLT_JUNIPER_ST", Const, 0, ""}, {"DLT_JUNIPER_VP", Const, 0, ""}, {"DLT_JUNIPER_VS", Const, 1, ""}, {"DLT_LAPB_WITH_DIR", Const, 0, ""}, {"DLT_LAPD", Const, 0, ""}, {"DLT_LIN", Const, 0, ""}, {"DLT_LINUX_EVDEV", Const, 1, ""}, {"DLT_LINUX_IRDA", Const, 0, ""}, {"DLT_LINUX_LAPD", Const, 0, ""}, {"DLT_LINUX_PPP_WITHDIRECTION", Const, 0, ""}, {"DLT_LINUX_SLL", Const, 0, ""}, {"DLT_LOOP", Const, 0, ""}, {"DLT_LTALK", Const, 0, ""}, {"DLT_MATCHING_MAX", Const, 1, ""}, {"DLT_MATCHING_MIN", Const, 1, ""}, {"DLT_MFR", Const, 0, ""}, {"DLT_MOST", Const, 0, ""}, {"DLT_MPEG_2_TS", Const, 1, ""}, {"DLT_MPLS", Const, 1, ""}, {"DLT_MTP2", Const, 0, ""}, {"DLT_MTP2_WITH_PHDR", Const, 0, ""}, {"DLT_MTP3", Const, 0, ""}, {"DLT_MUX27010", Const, 1, ""}, {"DLT_NETANALYZER", Const, 1, ""}, {"DLT_NETANALYZER_TRANSPARENT", Const, 1, ""}, {"DLT_NFC_LLCP", Const, 1, ""}, {"DLT_NFLOG", Const, 1, ""}, {"DLT_NG40", Const, 1, ""}, {"DLT_NULL", Const, 0, ""}, {"DLT_PCI_EXP", Const, 0, ""}, {"DLT_PFLOG", Const, 0, ""}, {"DLT_PFSYNC", Const, 0, ""}, {"DLT_PPI", Const, 0, ""}, {"DLT_PPP", Const, 0, ""}, {"DLT_PPP_BSDOS", Const, 0, ""}, {"DLT_PPP_ETHER", Const, 0, ""}, {"DLT_PPP_PPPD", Const, 0, ""}, {"DLT_PPP_SERIAL", Const, 0, ""}, {"DLT_PPP_WITH_DIR", Const, 0, ""}, {"DLT_PPP_WITH_DIRECTION", Const, 0, ""}, {"DLT_PRISM_HEADER", Const, 0, ""}, {"DLT_PRONET", Const, 0, ""}, {"DLT_RAIF1", Const, 0, ""}, {"DLT_RAW", Const, 0, ""}, {"DLT_RAWAF_MASK", Const, 1, ""}, {"DLT_RIO", Const, 0, ""}, {"DLT_SCCP", Const, 0, ""}, {"DLT_SITA", Const, 0, ""}, {"DLT_SLIP", Const, 0, ""}, {"DLT_SLIP_BSDOS", Const, 0, ""}, {"DLT_STANAG_5066_D_PDU", Const, 1, ""}, {"DLT_SUNATM", Const, 0, ""}, {"DLT_SYMANTEC_FIREWALL", Const, 0, ""}, {"DLT_TZSP", Const, 0, ""}, {"DLT_USB", Const, 0, ""}, {"DLT_USB_LINUX", Const, 0, ""}, {"DLT_USB_LINUX_MMAPPED", Const, 1, ""}, {"DLT_USER0", Const, 0, ""}, {"DLT_USER1", Const, 0, ""}, {"DLT_USER10", Const, 0, ""}, {"DLT_USER11", Const, 0, ""}, {"DLT_USER12", Const, 0, ""}, {"DLT_USER13", Const, 0, ""}, {"DLT_USER14", Const, 0, ""}, {"DLT_USER15", Const, 0, ""}, {"DLT_USER2", Const, 0, ""}, {"DLT_USER3", Const, 0, ""}, {"DLT_USER4", Const, 0, ""}, {"DLT_USER5", Const, 0, ""}, {"DLT_USER6", Const, 0, ""}, {"DLT_USER7", Const, 0, ""}, {"DLT_USER8", Const, 0, ""}, {"DLT_USER9", Const, 0, ""}, {"DLT_WIHART", Const, 1, ""}, {"DLT_X2E_SERIAL", Const, 0, ""}, {"DLT_X2E_XORAYA", Const, 0, ""}, {"DNSMXData", Type, 0, ""}, {"DNSMXData.NameExchange", Field, 0, ""}, {"DNSMXData.Pad", Field, 0, ""}, {"DNSMXData.Preference", Field, 0, ""}, {"DNSPTRData", Type, 0, ""}, {"DNSPTRData.Host", Field, 0, ""}, {"DNSRecord", Type, 0, ""}, {"DNSRecord.Data", Field, 0, ""}, {"DNSRecord.Dw", Field, 0, ""}, {"DNSRecord.Length", Field, 0, ""}, {"DNSRecord.Name", Field, 0, ""}, {"DNSRecord.Next", Field, 0, ""}, {"DNSRecord.Reserved", Field, 0, ""}, {"DNSRecord.Ttl", Field, 0, ""}, {"DNSRecord.Type", Field, 0, ""}, {"DNSSRVData", Type, 0, ""}, {"DNSSRVData.Pad", Field, 0, ""}, {"DNSSRVData.Port", Field, 0, ""}, {"DNSSRVData.Priority", Field, 0, ""}, {"DNSSRVData.Target", Field, 0, ""}, {"DNSSRVData.Weight", Field, 0, ""}, {"DNSTXTData", Type, 0, ""}, {"DNSTXTData.StringArray", Field, 0, ""}, {"DNSTXTData.StringCount", Field, 0, ""}, {"DNS_INFO_NO_RECORDS", Const, 4, ""}, {"DNS_TYPE_A", Const, 0, ""}, {"DNS_TYPE_A6", Const, 0, ""}, {"DNS_TYPE_AAAA", Const, 0, ""}, {"DNS_TYPE_ADDRS", Const, 0, ""}, {"DNS_TYPE_AFSDB", Const, 0, ""}, {"DNS_TYPE_ALL", Const, 0, ""}, {"DNS_TYPE_ANY", Const, 0, ""}, {"DNS_TYPE_ATMA", Const, 0, ""}, {"DNS_TYPE_AXFR", Const, 0, ""}, {"DNS_TYPE_CERT", Const, 0, ""}, {"DNS_TYPE_CNAME", Const, 0, ""}, {"DNS_TYPE_DHCID", Const, 0, ""}, {"DNS_TYPE_DNAME", Const, 0, ""}, {"DNS_TYPE_DNSKEY", Const, 0, ""}, {"DNS_TYPE_DS", Const, 0, ""}, {"DNS_TYPE_EID", Const, 0, ""}, {"DNS_TYPE_GID", Const, 0, ""}, {"DNS_TYPE_GPOS", Const, 0, ""}, {"DNS_TYPE_HINFO", Const, 0, ""}, {"DNS_TYPE_ISDN", Const, 0, ""}, {"DNS_TYPE_IXFR", Const, 0, ""}, {"DNS_TYPE_KEY", Const, 0, ""}, {"DNS_TYPE_KX", Const, 0, ""}, {"DNS_TYPE_LOC", Const, 0, ""}, {"DNS_TYPE_MAILA", Const, 0, ""}, {"DNS_TYPE_MAILB", Const, 0, ""}, {"DNS_TYPE_MB", Const, 0, ""}, {"DNS_TYPE_MD", Const, 0, ""}, {"DNS_TYPE_MF", Const, 0, ""}, {"DNS_TYPE_MG", Const, 0, ""}, {"DNS_TYPE_MINFO", Const, 0, ""}, {"DNS_TYPE_MR", Const, 0, ""}, {"DNS_TYPE_MX", Const, 0, ""}, {"DNS_TYPE_NAPTR", Const, 0, ""}, {"DNS_TYPE_NBSTAT", Const, 0, ""}, {"DNS_TYPE_NIMLOC", Const, 0, ""}, {"DNS_TYPE_NS", Const, 0, ""}, {"DNS_TYPE_NSAP", Const, 0, ""}, {"DNS_TYPE_NSAPPTR", Const, 0, ""}, {"DNS_TYPE_NSEC", Const, 0, ""}, {"DNS_TYPE_NULL", Const, 0, ""}, {"DNS_TYPE_NXT", Const, 0, ""}, {"DNS_TYPE_OPT", Const, 0, ""}, {"DNS_TYPE_PTR", Const, 0, ""}, {"DNS_TYPE_PX", Const, 0, ""}, {"DNS_TYPE_RP", Const, 0, ""}, {"DNS_TYPE_RRSIG", Const, 0, ""}, {"DNS_TYPE_RT", Const, 0, ""}, {"DNS_TYPE_SIG", Const, 0, ""}, {"DNS_TYPE_SINK", Const, 0, ""}, {"DNS_TYPE_SOA", Const, 0, ""}, {"DNS_TYPE_SRV", Const, 0, ""}, {"DNS_TYPE_TEXT", Const, 0, ""}, {"DNS_TYPE_TKEY", Const, 0, ""}, {"DNS_TYPE_TSIG", Const, 0, ""}, {"DNS_TYPE_UID", Const, 0, ""}, {"DNS_TYPE_UINFO", Const, 0, ""}, {"DNS_TYPE_UNSPEC", Const, 0, ""}, {"DNS_TYPE_WINS", Const, 0, ""}, {"DNS_TYPE_WINSR", Const, 0, ""}, {"DNS_TYPE_WKS", Const, 0, ""}, {"DNS_TYPE_X25", Const, 0, ""}, {"DT_BLK", Const, 0, ""}, {"DT_CHR", Const, 0, ""}, {"DT_DIR", Const, 0, ""}, {"DT_FIFO", Const, 0, ""}, {"DT_LNK", Const, 0, ""}, {"DT_REG", Const, 0, ""}, {"DT_SOCK", Const, 0, ""}, {"DT_UNKNOWN", Const, 0, ""}, {"DT_WHT", Const, 0, ""}, {"DUPLICATE_CLOSE_SOURCE", Const, 0, ""}, {"DUPLICATE_SAME_ACCESS", Const, 0, ""}, {"DeleteFile", Func, 0, ""}, {"DetachLsf", Func, 0, "func(fd int) error"}, {"DeviceIoControl", Func, 4, ""}, {"Dirent", Type, 0, ""}, {"Dirent.Fileno", Field, 0, ""}, {"Dirent.Ino", Field, 0, ""}, {"Dirent.Name", Field, 0, ""}, {"Dirent.Namlen", Field, 0, ""}, {"Dirent.Off", Field, 0, ""}, {"Dirent.Pad0", Field, 12, ""}, {"Dirent.Pad1", Field, 12, ""}, {"Dirent.Pad_cgo_0", Field, 0, ""}, {"Dirent.Reclen", Field, 0, ""}, {"Dirent.Seekoff", Field, 0, ""}, {"Dirent.Type", Field, 0, ""}, {"Dirent.X__d_padding", Field, 3, ""}, {"DnsNameCompare", Func, 4, ""}, {"DnsQuery", Func, 0, ""}, {"DnsRecordListFree", Func, 0, ""}, {"DnsSectionAdditional", Const, 4, ""}, {"DnsSectionAnswer", Const, 4, ""}, {"DnsSectionAuthority", Const, 4, ""}, {"DnsSectionQuestion", Const, 4, ""}, {"Dup", Func, 0, "func(oldfd int) (fd int, err error)"}, {"Dup2", Func, 0, "func(oldfd int, newfd int) (err error)"}, {"Dup3", Func, 2, "func(oldfd int, newfd int, flags int) (err error)"}, {"DuplicateHandle", Func, 0, ""}, {"E2BIG", Const, 0, ""}, {"EACCES", Const, 0, ""}, {"EADDRINUSE", Const, 0, ""}, {"EADDRNOTAVAIL", Const, 0, ""}, {"EADV", Const, 0, ""}, {"EAFNOSUPPORT", Const, 0, ""}, {"EAGAIN", Const, 0, ""}, {"EALREADY", Const, 0, ""}, {"EAUTH", Const, 0, ""}, {"EBADARCH", Const, 0, ""}, {"EBADE", Const, 0, ""}, {"EBADEXEC", Const, 0, ""}, {"EBADF", Const, 0, ""}, {"EBADFD", Const, 0, ""}, {"EBADMACHO", Const, 0, ""}, {"EBADMSG", Const, 0, ""}, {"EBADR", Const, 0, ""}, {"EBADRPC", Const, 0, ""}, {"EBADRQC", Const, 0, ""}, {"EBADSLT", Const, 0, ""}, {"EBFONT", Const, 0, ""}, {"EBUSY", Const, 0, ""}, {"ECANCELED", Const, 0, ""}, {"ECAPMODE", Const, 1, ""}, {"ECHILD", Const, 0, ""}, {"ECHO", Const, 0, ""}, {"ECHOCTL", Const, 0, ""}, {"ECHOE", Const, 0, ""}, {"ECHOK", Const, 0, ""}, {"ECHOKE", Const, 0, ""}, {"ECHONL", Const, 0, ""}, {"ECHOPRT", Const, 0, ""}, {"ECHRNG", Const, 0, ""}, {"ECOMM", Const, 0, ""}, {"ECONNABORTED", Const, 0, ""}, {"ECONNREFUSED", Const, 0, ""}, {"ECONNRESET", Const, 0, ""}, {"EDEADLK", Const, 0, ""}, {"EDEADLOCK", Const, 0, ""}, {"EDESTADDRREQ", Const, 0, ""}, {"EDEVERR", Const, 0, ""}, {"EDOM", Const, 0, ""}, {"EDOOFUS", Const, 0, ""}, {"EDOTDOT", Const, 0, ""}, {"EDQUOT", Const, 0, ""}, {"EEXIST", Const, 0, ""}, {"EFAULT", Const, 0, ""}, {"EFBIG", Const, 0, ""}, {"EFER_LMA", Const, 1, ""}, {"EFER_LME", Const, 1, ""}, {"EFER_NXE", Const, 1, ""}, {"EFER_SCE", Const, 1, ""}, {"EFTYPE", Const, 0, ""}, {"EHOSTDOWN", Const, 0, ""}, {"EHOSTUNREACH", Const, 0, ""}, {"EHWPOISON", Const, 0, ""}, {"EIDRM", Const, 0, ""}, {"EILSEQ", Const, 0, ""}, {"EINPROGRESS", Const, 0, ""}, {"EINTR", Const, 0, ""}, {"EINVAL", Const, 0, ""}, {"EIO", Const, 0, ""}, {"EIPSEC", Const, 1, ""}, {"EISCONN", Const, 0, ""}, {"EISDIR", Const, 0, ""}, {"EISNAM", Const, 0, ""}, {"EKEYEXPIRED", Const, 0, ""}, {"EKEYREJECTED", Const, 0, ""}, {"EKEYREVOKED", Const, 0, ""}, {"EL2HLT", Const, 0, ""}, {"EL2NSYNC", Const, 0, ""}, {"EL3HLT", Const, 0, ""}, {"EL3RST", Const, 0, ""}, {"ELAST", Const, 0, ""}, {"ELF_NGREG", Const, 0, ""}, {"ELF_PRARGSZ", Const, 0, ""}, {"ELIBACC", Const, 0, ""}, {"ELIBBAD", Const, 0, ""}, {"ELIBEXEC", Const, 0, ""}, {"ELIBMAX", Const, 0, ""}, {"ELIBSCN", Const, 0, ""}, {"ELNRNG", Const, 0, ""}, {"ELOOP", Const, 0, ""}, {"EMEDIUMTYPE", Const, 0, ""}, {"EMFILE", Const, 0, ""}, {"EMLINK", Const, 0, ""}, {"EMSGSIZE", Const, 0, ""}, {"EMT_TAGOVF", Const, 1, ""}, {"EMULTIHOP", Const, 0, ""}, {"EMUL_ENABLED", Const, 1, ""}, {"EMUL_LINUX", Const, 1, ""}, {"EMUL_LINUX32", Const, 1, ""}, {"EMUL_MAXID", Const, 1, ""}, {"EMUL_NATIVE", Const, 1, ""}, {"ENAMETOOLONG", Const, 0, ""}, {"ENAVAIL", Const, 0, ""}, {"ENDRUNDISC", Const, 1, ""}, {"ENEEDAUTH", Const, 0, ""}, {"ENETDOWN", Const, 0, ""}, {"ENETRESET", Const, 0, ""}, {"ENETUNREACH", Const, 0, ""}, {"ENFILE", Const, 0, ""}, {"ENOANO", Const, 0, ""}, {"ENOATTR", Const, 0, ""}, {"ENOBUFS", Const, 0, ""}, {"ENOCSI", Const, 0, ""}, {"ENODATA", Const, 0, ""}, {"ENODEV", Const, 0, ""}, {"ENOENT", Const, 0, ""}, {"ENOEXEC", Const, 0, ""}, {"ENOKEY", Const, 0, ""}, {"ENOLCK", Const, 0, ""}, {"ENOLINK", Const, 0, ""}, {"ENOMEDIUM", Const, 0, ""}, {"ENOMEM", Const, 0, ""}, {"ENOMSG", Const, 0, ""}, {"ENONET", Const, 0, ""}, {"ENOPKG", Const, 0, ""}, {"ENOPOLICY", Const, 0, ""}, {"ENOPROTOOPT", Const, 0, ""}, {"ENOSPC", Const, 0, ""}, {"ENOSR", Const, 0, ""}, {"ENOSTR", Const, 0, ""}, {"ENOSYS", Const, 0, ""}, {"ENOTBLK", Const, 0, ""}, {"ENOTCAPABLE", Const, 0, ""}, {"ENOTCONN", Const, 0, ""}, {"ENOTDIR", Const, 0, ""}, {"ENOTEMPTY", Const, 0, ""}, {"ENOTNAM", Const, 0, ""}, {"ENOTRECOVERABLE", Const, 0, ""}, {"ENOTSOCK", Const, 0, ""}, {"ENOTSUP", Const, 0, ""}, {"ENOTTY", Const, 0, ""}, {"ENOTUNIQ", Const, 0, ""}, {"ENXIO", Const, 0, ""}, {"EN_SW_CTL_INF", Const, 1, ""}, {"EN_SW_CTL_PREC", Const, 1, ""}, {"EN_SW_CTL_ROUND", Const, 1, ""}, {"EN_SW_DATACHAIN", Const, 1, ""}, {"EN_SW_DENORM", Const, 1, ""}, {"EN_SW_INVOP", Const, 1, ""}, {"EN_SW_OVERFLOW", Const, 1, ""}, {"EN_SW_PRECLOSS", Const, 1, ""}, {"EN_SW_UNDERFLOW", Const, 1, ""}, {"EN_SW_ZERODIV", Const, 1, ""}, {"EOPNOTSUPP", Const, 0, ""}, {"EOVERFLOW", Const, 0, ""}, {"EOWNERDEAD", Const, 0, ""}, {"EPERM", Const, 0, ""}, {"EPFNOSUPPORT", Const, 0, ""}, {"EPIPE", Const, 0, ""}, {"EPOLLERR", Const, 0, ""}, {"EPOLLET", Const, 0, ""}, {"EPOLLHUP", Const, 0, ""}, {"EPOLLIN", Const, 0, ""}, {"EPOLLMSG", Const, 0, ""}, {"EPOLLONESHOT", Const, 0, ""}, {"EPOLLOUT", Const, 0, ""}, {"EPOLLPRI", Const, 0, ""}, {"EPOLLRDBAND", Const, 0, ""}, {"EPOLLRDHUP", Const, 0, ""}, {"EPOLLRDNORM", Const, 0, ""}, {"EPOLLWRBAND", Const, 0, ""}, {"EPOLLWRNORM", Const, 0, ""}, {"EPOLL_CLOEXEC", Const, 0, ""}, {"EPOLL_CTL_ADD", Const, 0, ""}, {"EPOLL_CTL_DEL", Const, 0, ""}, {"EPOLL_CTL_MOD", Const, 0, ""}, {"EPOLL_NONBLOCK", Const, 0, ""}, {"EPROCLIM", Const, 0, ""}, {"EPROCUNAVAIL", Const, 0, ""}, {"EPROGMISMATCH", Const, 0, ""}, {"EPROGUNAVAIL", Const, 0, ""}, {"EPROTO", Const, 0, ""}, {"EPROTONOSUPPORT", Const, 0, ""}, {"EPROTOTYPE", Const, 0, ""}, {"EPWROFF", Const, 0, ""}, {"EQFULL", Const, 16, ""}, {"ERANGE", Const, 0, ""}, {"EREMCHG", Const, 0, ""}, {"EREMOTE", Const, 0, ""}, {"EREMOTEIO", Const, 0, ""}, {"ERESTART", Const, 0, ""}, {"ERFKILL", Const, 0, ""}, {"EROFS", Const, 0, ""}, {"ERPCMISMATCH", Const, 0, ""}, {"ERROR_ACCESS_DENIED", Const, 0, ""}, {"ERROR_ALREADY_EXISTS", Const, 0, ""}, {"ERROR_BROKEN_PIPE", Const, 0, ""}, {"ERROR_BUFFER_OVERFLOW", Const, 0, ""}, {"ERROR_DIR_NOT_EMPTY", Const, 8, ""}, {"ERROR_ENVVAR_NOT_FOUND", Const, 0, ""}, {"ERROR_FILE_EXISTS", Const, 0, ""}, {"ERROR_FILE_NOT_FOUND", Const, 0, ""}, {"ERROR_HANDLE_EOF", Const, 2, ""}, {"ERROR_INSUFFICIENT_BUFFER", Const, 0, ""}, {"ERROR_IO_PENDING", Const, 0, ""}, {"ERROR_MOD_NOT_FOUND", Const, 0, ""}, {"ERROR_MORE_DATA", Const, 3, ""}, {"ERROR_NETNAME_DELETED", Const, 3, ""}, {"ERROR_NOT_FOUND", Const, 1, ""}, {"ERROR_NO_MORE_FILES", Const, 0, ""}, {"ERROR_OPERATION_ABORTED", Const, 0, ""}, {"ERROR_PATH_NOT_FOUND", Const, 0, ""}, {"ERROR_PRIVILEGE_NOT_HELD", Const, 4, ""}, {"ERROR_PROC_NOT_FOUND", Const, 0, ""}, {"ESHLIBVERS", Const, 0, ""}, {"ESHUTDOWN", Const, 0, ""}, {"ESOCKTNOSUPPORT", Const, 0, ""}, {"ESPIPE", Const, 0, ""}, {"ESRCH", Const, 0, ""}, {"ESRMNT", Const, 0, ""}, {"ESTALE", Const, 0, ""}, {"ESTRPIPE", Const, 0, ""}, {"ETHERCAP_JUMBO_MTU", Const, 1, ""}, {"ETHERCAP_VLAN_HWTAGGING", Const, 1, ""}, {"ETHERCAP_VLAN_MTU", Const, 1, ""}, {"ETHERMIN", Const, 1, ""}, {"ETHERMTU", Const, 1, ""}, {"ETHERMTU_JUMBO", Const, 1, ""}, {"ETHERTYPE_8023", Const, 1, ""}, {"ETHERTYPE_AARP", Const, 1, ""}, {"ETHERTYPE_ACCTON", Const, 1, ""}, {"ETHERTYPE_AEONIC", Const, 1, ""}, {"ETHERTYPE_ALPHA", Const, 1, ""}, {"ETHERTYPE_AMBER", Const, 1, ""}, {"ETHERTYPE_AMOEBA", Const, 1, ""}, {"ETHERTYPE_AOE", Const, 1, ""}, {"ETHERTYPE_APOLLO", Const, 1, ""}, {"ETHERTYPE_APOLLODOMAIN", Const, 1, ""}, {"ETHERTYPE_APPLETALK", Const, 1, ""}, {"ETHERTYPE_APPLITEK", Const, 1, ""}, {"ETHERTYPE_ARGONAUT", Const, 1, ""}, {"ETHERTYPE_ARP", Const, 1, ""}, {"ETHERTYPE_AT", Const, 1, ""}, {"ETHERTYPE_ATALK", Const, 1, ""}, {"ETHERTYPE_ATOMIC", Const, 1, ""}, {"ETHERTYPE_ATT", Const, 1, ""}, {"ETHERTYPE_ATTSTANFORD", Const, 1, ""}, {"ETHERTYPE_AUTOPHON", Const, 1, ""}, {"ETHERTYPE_AXIS", Const, 1, ""}, {"ETHERTYPE_BCLOOP", Const, 1, ""}, {"ETHERTYPE_BOFL", Const, 1, ""}, {"ETHERTYPE_CABLETRON", Const, 1, ""}, {"ETHERTYPE_CHAOS", Const, 1, ""}, {"ETHERTYPE_COMDESIGN", Const, 1, ""}, {"ETHERTYPE_COMPUGRAPHIC", Const, 1, ""}, {"ETHERTYPE_COUNTERPOINT", Const, 1, ""}, {"ETHERTYPE_CRONUS", Const, 1, ""}, {"ETHERTYPE_CRONUSVLN", Const, 1, ""}, {"ETHERTYPE_DCA", Const, 1, ""}, {"ETHERTYPE_DDE", Const, 1, ""}, {"ETHERTYPE_DEBNI", Const, 1, ""}, {"ETHERTYPE_DECAM", Const, 1, ""}, {"ETHERTYPE_DECCUST", Const, 1, ""}, {"ETHERTYPE_DECDIAG", Const, 1, ""}, {"ETHERTYPE_DECDNS", Const, 1, ""}, {"ETHERTYPE_DECDTS", Const, 1, ""}, {"ETHERTYPE_DECEXPER", Const, 1, ""}, {"ETHERTYPE_DECLAST", Const, 1, ""}, {"ETHERTYPE_DECLTM", Const, 1, ""}, {"ETHERTYPE_DECMUMPS", Const, 1, ""}, {"ETHERTYPE_DECNETBIOS", Const, 1, ""}, {"ETHERTYPE_DELTACON", Const, 1, ""}, {"ETHERTYPE_DIDDLE", Const, 1, ""}, {"ETHERTYPE_DLOG1", Const, 1, ""}, {"ETHERTYPE_DLOG2", Const, 1, ""}, {"ETHERTYPE_DN", Const, 1, ""}, {"ETHERTYPE_DOGFIGHT", Const, 1, ""}, {"ETHERTYPE_DSMD", Const, 1, ""}, {"ETHERTYPE_ECMA", Const, 1, ""}, {"ETHERTYPE_ENCRYPT", Const, 1, ""}, {"ETHERTYPE_ES", Const, 1, ""}, {"ETHERTYPE_EXCELAN", Const, 1, ""}, {"ETHERTYPE_EXPERDATA", Const, 1, ""}, {"ETHERTYPE_FLIP", Const, 1, ""}, {"ETHERTYPE_FLOWCONTROL", Const, 1, ""}, {"ETHERTYPE_FRARP", Const, 1, ""}, {"ETHERTYPE_GENDYN", Const, 1, ""}, {"ETHERTYPE_HAYES", Const, 1, ""}, {"ETHERTYPE_HIPPI_FP", Const, 1, ""}, {"ETHERTYPE_HITACHI", Const, 1, ""}, {"ETHERTYPE_HP", Const, 1, ""}, {"ETHERTYPE_IEEEPUP", Const, 1, ""}, {"ETHERTYPE_IEEEPUPAT", Const, 1, ""}, {"ETHERTYPE_IMLBL", Const, 1, ""}, {"ETHERTYPE_IMLBLDIAG", Const, 1, ""}, {"ETHERTYPE_IP", Const, 1, ""}, {"ETHERTYPE_IPAS", Const, 1, ""}, {"ETHERTYPE_IPV6", Const, 1, ""}, {"ETHERTYPE_IPX", Const, 1, ""}, {"ETHERTYPE_IPXNEW", Const, 1, ""}, {"ETHERTYPE_KALPANA", Const, 1, ""}, {"ETHERTYPE_LANBRIDGE", Const, 1, ""}, {"ETHERTYPE_LANPROBE", Const, 1, ""}, {"ETHERTYPE_LAT", Const, 1, ""}, {"ETHERTYPE_LBACK", Const, 1, ""}, {"ETHERTYPE_LITTLE", Const, 1, ""}, {"ETHERTYPE_LLDP", Const, 1, ""}, {"ETHERTYPE_LOGICRAFT", Const, 1, ""}, {"ETHERTYPE_LOOPBACK", Const, 1, ""}, {"ETHERTYPE_MATRA", Const, 1, ""}, {"ETHERTYPE_MAX", Const, 1, ""}, {"ETHERTYPE_MERIT", Const, 1, ""}, {"ETHERTYPE_MICP", Const, 1, ""}, {"ETHERTYPE_MOPDL", Const, 1, ""}, {"ETHERTYPE_MOPRC", Const, 1, ""}, {"ETHERTYPE_MOTOROLA", Const, 1, ""}, {"ETHERTYPE_MPLS", Const, 1, ""}, {"ETHERTYPE_MPLS_MCAST", Const, 1, ""}, {"ETHERTYPE_MUMPS", Const, 1, ""}, {"ETHERTYPE_NBPCC", Const, 1, ""}, {"ETHERTYPE_NBPCLAIM", Const, 1, ""}, {"ETHERTYPE_NBPCLREQ", Const, 1, ""}, {"ETHERTYPE_NBPCLRSP", Const, 1, ""}, {"ETHERTYPE_NBPCREQ", Const, 1, ""}, {"ETHERTYPE_NBPCRSP", Const, 1, ""}, {"ETHERTYPE_NBPDG", Const, 1, ""}, {"ETHERTYPE_NBPDGB", Const, 1, ""}, {"ETHERTYPE_NBPDLTE", Const, 1, ""}, {"ETHERTYPE_NBPRAR", Const, 1, ""}, {"ETHERTYPE_NBPRAS", Const, 1, ""}, {"ETHERTYPE_NBPRST", Const, 1, ""}, {"ETHERTYPE_NBPSCD", Const, 1, ""}, {"ETHERTYPE_NBPVCD", Const, 1, ""}, {"ETHERTYPE_NBS", Const, 1, ""}, {"ETHERTYPE_NCD", Const, 1, ""}, {"ETHERTYPE_NESTAR", Const, 1, ""}, {"ETHERTYPE_NETBEUI", Const, 1, ""}, {"ETHERTYPE_NOVELL", Const, 1, ""}, {"ETHERTYPE_NS", Const, 1, ""}, {"ETHERTYPE_NSAT", Const, 1, ""}, {"ETHERTYPE_NSCOMPAT", Const, 1, ""}, {"ETHERTYPE_NTRAILER", Const, 1, ""}, {"ETHERTYPE_OS9", Const, 1, ""}, {"ETHERTYPE_OS9NET", Const, 1, ""}, {"ETHERTYPE_PACER", Const, 1, ""}, {"ETHERTYPE_PAE", Const, 1, ""}, {"ETHERTYPE_PCS", Const, 1, ""}, {"ETHERTYPE_PLANNING", Const, 1, ""}, {"ETHERTYPE_PPP", Const, 1, ""}, {"ETHERTYPE_PPPOE", Const, 1, ""}, {"ETHERTYPE_PPPOEDISC", Const, 1, ""}, {"ETHERTYPE_PRIMENTS", Const, 1, ""}, {"ETHERTYPE_PUP", Const, 1, ""}, {"ETHERTYPE_PUPAT", Const, 1, ""}, {"ETHERTYPE_QINQ", Const, 1, ""}, {"ETHERTYPE_RACAL", Const, 1, ""}, {"ETHERTYPE_RATIONAL", Const, 1, ""}, {"ETHERTYPE_RAWFR", Const, 1, ""}, {"ETHERTYPE_RCL", Const, 1, ""}, {"ETHERTYPE_RDP", Const, 1, ""}, {"ETHERTYPE_RETIX", Const, 1, ""}, {"ETHERTYPE_REVARP", Const, 1, ""}, {"ETHERTYPE_SCA", Const, 1, ""}, {"ETHERTYPE_SECTRA", Const, 1, ""}, {"ETHERTYPE_SECUREDATA", Const, 1, ""}, {"ETHERTYPE_SGITW", Const, 1, ""}, {"ETHERTYPE_SG_BOUNCE", Const, 1, ""}, {"ETHERTYPE_SG_DIAG", Const, 1, ""}, {"ETHERTYPE_SG_NETGAMES", Const, 1, ""}, {"ETHERTYPE_SG_RESV", Const, 1, ""}, {"ETHERTYPE_SIMNET", Const, 1, ""}, {"ETHERTYPE_SLOW", Const, 1, ""}, {"ETHERTYPE_SLOWPROTOCOLS", Const, 1, ""}, {"ETHERTYPE_SNA", Const, 1, ""}, {"ETHERTYPE_SNMP", Const, 1, ""}, {"ETHERTYPE_SONIX", Const, 1, ""}, {"ETHERTYPE_SPIDER", Const, 1, ""}, {"ETHERTYPE_SPRITE", Const, 1, ""}, {"ETHERTYPE_STP", Const, 1, ""}, {"ETHERTYPE_TALARIS", Const, 1, ""}, {"ETHERTYPE_TALARISMC", Const, 1, ""}, {"ETHERTYPE_TCPCOMP", Const, 1, ""}, {"ETHERTYPE_TCPSM", Const, 1, ""}, {"ETHERTYPE_TEC", Const, 1, ""}, {"ETHERTYPE_TIGAN", Const, 1, ""}, {"ETHERTYPE_TRAIL", Const, 1, ""}, {"ETHERTYPE_TRANSETHER", Const, 1, ""}, {"ETHERTYPE_TYMSHARE", Const, 1, ""}, {"ETHERTYPE_UBBST", Const, 1, ""}, {"ETHERTYPE_UBDEBUG", Const, 1, ""}, {"ETHERTYPE_UBDIAGLOOP", Const, 1, ""}, {"ETHERTYPE_UBDL", Const, 1, ""}, {"ETHERTYPE_UBNIU", Const, 1, ""}, {"ETHERTYPE_UBNMC", Const, 1, ""}, {"ETHERTYPE_VALID", Const, 1, ""}, {"ETHERTYPE_VARIAN", Const, 1, ""}, {"ETHERTYPE_VAXELN", Const, 1, ""}, {"ETHERTYPE_VEECO", Const, 1, ""}, {"ETHERTYPE_VEXP", Const, 1, ""}, {"ETHERTYPE_VGLAB", Const, 1, ""}, {"ETHERTYPE_VINES", Const, 1, ""}, {"ETHERTYPE_VINESECHO", Const, 1, ""}, {"ETHERTYPE_VINESLOOP", Const, 1, ""}, {"ETHERTYPE_VITAL", Const, 1, ""}, {"ETHERTYPE_VLAN", Const, 1, ""}, {"ETHERTYPE_VLTLMAN", Const, 1, ""}, {"ETHERTYPE_VPROD", Const, 1, ""}, {"ETHERTYPE_VURESERVED", Const, 1, ""}, {"ETHERTYPE_WATERLOO", Const, 1, ""}, {"ETHERTYPE_WELLFLEET", Const, 1, ""}, {"ETHERTYPE_X25", Const, 1, ""}, {"ETHERTYPE_X75", Const, 1, ""}, {"ETHERTYPE_XNSSM", Const, 1, ""}, {"ETHERTYPE_XTP", Const, 1, ""}, {"ETHER_ADDR_LEN", Const, 1, ""}, {"ETHER_ALIGN", Const, 1, ""}, {"ETHER_CRC_LEN", Const, 1, ""}, {"ETHER_CRC_POLY_BE", Const, 1, ""}, {"ETHER_CRC_POLY_LE", Const, 1, ""}, {"ETHER_HDR_LEN", Const, 1, ""}, {"ETHER_MAX_DIX_LEN", Const, 1, ""}, {"ETHER_MAX_LEN", Const, 1, ""}, {"ETHER_MAX_LEN_JUMBO", Const, 1, ""}, {"ETHER_MIN_LEN", Const, 1, ""}, {"ETHER_PPPOE_ENCAP_LEN", Const, 1, ""}, {"ETHER_TYPE_LEN", Const, 1, ""}, {"ETHER_VLAN_ENCAP_LEN", Const, 1, ""}, {"ETH_P_1588", Const, 0, ""}, {"ETH_P_8021Q", Const, 0, ""}, {"ETH_P_802_2", Const, 0, ""}, {"ETH_P_802_3", Const, 0, ""}, {"ETH_P_AARP", Const, 0, ""}, {"ETH_P_ALL", Const, 0, ""}, {"ETH_P_AOE", Const, 0, ""}, {"ETH_P_ARCNET", Const, 0, ""}, {"ETH_P_ARP", Const, 0, ""}, {"ETH_P_ATALK", Const, 0, ""}, {"ETH_P_ATMFATE", Const, 0, ""}, {"ETH_P_ATMMPOA", Const, 0, ""}, {"ETH_P_AX25", Const, 0, ""}, {"ETH_P_BPQ", Const, 0, ""}, {"ETH_P_CAIF", Const, 0, ""}, {"ETH_P_CAN", Const, 0, ""}, {"ETH_P_CONTROL", Const, 0, ""}, {"ETH_P_CUST", Const, 0, ""}, {"ETH_P_DDCMP", Const, 0, ""}, {"ETH_P_DEC", Const, 0, ""}, {"ETH_P_DIAG", Const, 0, ""}, {"ETH_P_DNA_DL", Const, 0, ""}, {"ETH_P_DNA_RC", Const, 0, ""}, {"ETH_P_DNA_RT", Const, 0, ""}, {"ETH_P_DSA", Const, 0, ""}, {"ETH_P_ECONET", Const, 0, ""}, {"ETH_P_EDSA", Const, 0, ""}, {"ETH_P_FCOE", Const, 0, ""}, {"ETH_P_FIP", Const, 0, ""}, {"ETH_P_HDLC", Const, 0, ""}, {"ETH_P_IEEE802154", Const, 0, ""}, {"ETH_P_IEEEPUP", Const, 0, ""}, {"ETH_P_IEEEPUPAT", Const, 0, ""}, {"ETH_P_IP", Const, 0, ""}, {"ETH_P_IPV6", Const, 0, ""}, {"ETH_P_IPX", Const, 0, ""}, {"ETH_P_IRDA", Const, 0, ""}, {"ETH_P_LAT", Const, 0, ""}, {"ETH_P_LINK_CTL", Const, 0, ""}, {"ETH_P_LOCALTALK", Const, 0, ""}, {"ETH_P_LOOP", Const, 0, ""}, {"ETH_P_MOBITEX", Const, 0, ""}, {"ETH_P_MPLS_MC", Const, 0, ""}, {"ETH_P_MPLS_UC", Const, 0, ""}, {"ETH_P_PAE", Const, 0, ""}, {"ETH_P_PAUSE", Const, 0, ""}, {"ETH_P_PHONET", Const, 0, ""}, {"ETH_P_PPPTALK", Const, 0, ""}, {"ETH_P_PPP_DISC", Const, 0, ""}, {"ETH_P_PPP_MP", Const, 0, ""}, {"ETH_P_PPP_SES", Const, 0, ""}, {"ETH_P_PUP", Const, 0, ""}, {"ETH_P_PUPAT", Const, 0, ""}, {"ETH_P_RARP", Const, 0, ""}, {"ETH_P_SCA", Const, 0, ""}, {"ETH_P_SLOW", Const, 0, ""}, {"ETH_P_SNAP", Const, 0, ""}, {"ETH_P_TEB", Const, 0, ""}, {"ETH_P_TIPC", Const, 0, ""}, {"ETH_P_TRAILER", Const, 0, ""}, {"ETH_P_TR_802_2", Const, 0, ""}, {"ETH_P_WAN_PPP", Const, 0, ""}, {"ETH_P_WCCP", Const, 0, ""}, {"ETH_P_X25", Const, 0, ""}, {"ETIME", Const, 0, ""}, {"ETIMEDOUT", Const, 0, ""}, {"ETOOMANYREFS", Const, 0, ""}, {"ETXTBSY", Const, 0, ""}, {"EUCLEAN", Const, 0, ""}, {"EUNATCH", Const, 0, ""}, {"EUSERS", Const, 0, ""}, {"EVFILT_AIO", Const, 0, ""}, {"EVFILT_FS", Const, 0, ""}, {"EVFILT_LIO", Const, 0, ""}, {"EVFILT_MACHPORT", Const, 0, ""}, {"EVFILT_PROC", Const, 0, ""}, {"EVFILT_READ", Const, 0, ""}, {"EVFILT_SIGNAL", Const, 0, ""}, {"EVFILT_SYSCOUNT", Const, 0, ""}, {"EVFILT_THREADMARKER", Const, 0, ""}, {"EVFILT_TIMER", Const, 0, ""}, {"EVFILT_USER", Const, 0, ""}, {"EVFILT_VM", Const, 0, ""}, {"EVFILT_VNODE", Const, 0, ""}, {"EVFILT_WRITE", Const, 0, ""}, {"EV_ADD", Const, 0, ""}, {"EV_CLEAR", Const, 0, ""}, {"EV_DELETE", Const, 0, ""}, {"EV_DISABLE", Const, 0, ""}, {"EV_DISPATCH", Const, 0, ""}, {"EV_DROP", Const, 3, ""}, {"EV_ENABLE", Const, 0, ""}, {"EV_EOF", Const, 0, ""}, {"EV_ERROR", Const, 0, ""}, {"EV_FLAG0", Const, 0, ""}, {"EV_FLAG1", Const, 0, ""}, {"EV_ONESHOT", Const, 0, ""}, {"EV_OOBAND", Const, 0, ""}, {"EV_POLL", Const, 0, ""}, {"EV_RECEIPT", Const, 0, ""}, {"EV_SYSFLAGS", Const, 0, ""}, {"EWINDOWS", Const, 0, ""}, {"EWOULDBLOCK", Const, 0, ""}, {"EXDEV", Const, 0, ""}, {"EXFULL", Const, 0, ""}, {"EXTA", Const, 0, ""}, {"EXTB", Const, 0, ""}, {"EXTPROC", Const, 0, ""}, {"Environ", Func, 0, "func() []string"}, {"EpollCreate", Func, 0, "func(size int) (fd int, err error)"}, {"EpollCreate1", Func, 0, "func(flag int) (fd int, err error)"}, {"EpollCtl", Func, 0, "func(epfd int, op int, fd int, event *EpollEvent) (err error)"}, {"EpollEvent", Type, 0, ""}, {"EpollEvent.Events", Field, 0, ""}, {"EpollEvent.Fd", Field, 0, ""}, {"EpollEvent.Pad", Field, 0, ""}, {"EpollEvent.PadFd", Field, 0, ""}, {"EpollWait", Func, 0, "func(epfd int, events []EpollEvent, msec int) (n int, err error)"}, {"Errno", Type, 0, ""}, {"EscapeArg", Func, 0, ""}, {"Exchangedata", Func, 0, ""}, {"Exec", Func, 0, "func(argv0 string, argv []string, envv []string) (err error)"}, {"Exit", Func, 0, "func(code int)"}, {"ExitProcess", Func, 0, ""}, {"FD_CLOEXEC", Const, 0, ""}, {"FD_SETSIZE", Const, 0, ""}, {"FILE_ACTION_ADDED", Const, 0, ""}, {"FILE_ACTION_MODIFIED", Const, 0, ""}, {"FILE_ACTION_REMOVED", Const, 0, ""}, {"FILE_ACTION_RENAMED_NEW_NAME", Const, 0, ""}, {"FILE_ACTION_RENAMED_OLD_NAME", Const, 0, ""}, {"FILE_APPEND_DATA", Const, 0, ""}, {"FILE_ATTRIBUTE_ARCHIVE", Const, 0, ""}, {"FILE_ATTRIBUTE_DIRECTORY", Const, 0, ""}, {"FILE_ATTRIBUTE_HIDDEN", Const, 0, ""}, {"FILE_ATTRIBUTE_NORMAL", Const, 0, ""}, {"FILE_ATTRIBUTE_READONLY", Const, 0, ""}, {"FILE_ATTRIBUTE_REPARSE_POINT", Const, 4, ""}, {"FILE_ATTRIBUTE_SYSTEM", Const, 0, ""}, {"FILE_BEGIN", Const, 0, ""}, {"FILE_CURRENT", Const, 0, ""}, {"FILE_END", Const, 0, ""}, {"FILE_FLAG_BACKUP_SEMANTICS", Const, 0, ""}, {"FILE_FLAG_OPEN_REPARSE_POINT", Const, 4, ""}, {"FILE_FLAG_OVERLAPPED", Const, 0, ""}, {"FILE_LIST_DIRECTORY", Const, 0, ""}, {"FILE_MAP_COPY", Const, 0, ""}, {"FILE_MAP_EXECUTE", Const, 0, ""}, {"FILE_MAP_READ", Const, 0, ""}, {"FILE_MAP_WRITE", Const, 0, ""}, {"FILE_NOTIFY_CHANGE_ATTRIBUTES", Const, 0, ""}, {"FILE_NOTIFY_CHANGE_CREATION", Const, 0, ""}, {"FILE_NOTIFY_CHANGE_DIR_NAME", Const, 0, ""}, {"FILE_NOTIFY_CHANGE_FILE_NAME", Const, 0, ""}, {"FILE_NOTIFY_CHANGE_LAST_ACCESS", Const, 0, ""}, {"FILE_NOTIFY_CHANGE_LAST_WRITE", Const, 0, ""}, {"FILE_NOTIFY_CHANGE_SIZE", Const, 0, ""}, {"FILE_SHARE_DELETE", Const, 0, ""}, {"FILE_SHARE_READ", Const, 0, ""}, {"FILE_SHARE_WRITE", Const, 0, ""}, {"FILE_SKIP_COMPLETION_PORT_ON_SUCCESS", Const, 2, ""}, {"FILE_SKIP_SET_EVENT_ON_HANDLE", Const, 2, ""}, {"FILE_TYPE_CHAR", Const, 0, ""}, {"FILE_TYPE_DISK", Const, 0, ""}, {"FILE_TYPE_PIPE", Const, 0, ""}, {"FILE_TYPE_REMOTE", Const, 0, ""}, {"FILE_TYPE_UNKNOWN", Const, 0, ""}, {"FILE_WRITE_ATTRIBUTES", Const, 0, ""}, {"FLUSHO", Const, 0, ""}, {"FORMAT_MESSAGE_ALLOCATE_BUFFER", Const, 0, ""}, {"FORMAT_MESSAGE_ARGUMENT_ARRAY", Const, 0, ""}, {"FORMAT_MESSAGE_FROM_HMODULE", Const, 0, ""}, {"FORMAT_MESSAGE_FROM_STRING", Const, 0, ""}, {"FORMAT_MESSAGE_FROM_SYSTEM", Const, 0, ""}, {"FORMAT_MESSAGE_IGNORE_INSERTS", Const, 0, ""}, {"FORMAT_MESSAGE_MAX_WIDTH_MASK", Const, 0, ""}, {"FSCTL_GET_REPARSE_POINT", Const, 4, ""}, {"F_ADDFILESIGS", Const, 0, ""}, {"F_ADDSIGS", Const, 0, ""}, {"F_ALLOCATEALL", Const, 0, ""}, {"F_ALLOCATECONTIG", Const, 0, ""}, {"F_CANCEL", Const, 0, ""}, {"F_CHKCLEAN", Const, 0, ""}, {"F_CLOSEM", Const, 1, ""}, {"F_DUP2FD", Const, 0, ""}, {"F_DUP2FD_CLOEXEC", Const, 1, ""}, {"F_DUPFD", Const, 0, ""}, {"F_DUPFD_CLOEXEC", Const, 0, ""}, {"F_EXLCK", Const, 0, ""}, {"F_FINDSIGS", Const, 16, ""}, {"F_FLUSH_DATA", Const, 0, ""}, {"F_FREEZE_FS", Const, 0, ""}, {"F_FSCTL", Const, 1, ""}, {"F_FSDIRMASK", Const, 1, ""}, {"F_FSIN", Const, 1, ""}, {"F_FSINOUT", Const, 1, ""}, {"F_FSOUT", Const, 1, ""}, {"F_FSPRIV", Const, 1, ""}, {"F_FSVOID", Const, 1, ""}, {"F_FULLFSYNC", Const, 0, ""}, {"F_GETCODEDIR", Const, 16, ""}, {"F_GETFD", Const, 0, ""}, {"F_GETFL", Const, 0, ""}, {"F_GETLEASE", Const, 0, ""}, {"F_GETLK", Const, 0, ""}, {"F_GETLK64", Const, 0, ""}, {"F_GETLKPID", Const, 0, ""}, {"F_GETNOSIGPIPE", Const, 0, ""}, {"F_GETOWN", Const, 0, ""}, {"F_GETOWN_EX", Const, 0, ""}, {"F_GETPATH", Const, 0, ""}, {"F_GETPATH_MTMINFO", Const, 0, ""}, {"F_GETPIPE_SZ", Const, 0, ""}, {"F_GETPROTECTIONCLASS", Const, 0, ""}, {"F_GETPROTECTIONLEVEL", Const, 16, ""}, {"F_GETSIG", Const, 0, ""}, {"F_GLOBAL_NOCACHE", Const, 0, ""}, {"F_LOCK", Const, 0, ""}, {"F_LOG2PHYS", Const, 0, ""}, {"F_LOG2PHYS_EXT", Const, 0, ""}, {"F_MARKDEPENDENCY", Const, 0, ""}, {"F_MAXFD", Const, 1, ""}, {"F_NOCACHE", Const, 0, ""}, {"F_NODIRECT", Const, 0, ""}, {"F_NOTIFY", Const, 0, ""}, {"F_OGETLK", Const, 0, ""}, {"F_OK", Const, 0, ""}, {"F_OSETLK", Const, 0, ""}, {"F_OSETLKW", Const, 0, ""}, {"F_PARAM_MASK", Const, 1, ""}, {"F_PARAM_MAX", Const, 1, ""}, {"F_PATHPKG_CHECK", Const, 0, ""}, {"F_PEOFPOSMODE", Const, 0, ""}, {"F_PREALLOCATE", Const, 0, ""}, {"F_RDADVISE", Const, 0, ""}, {"F_RDAHEAD", Const, 0, ""}, {"F_RDLCK", Const, 0, ""}, {"F_READAHEAD", Const, 0, ""}, {"F_READBOOTSTRAP", Const, 0, ""}, {"F_SETBACKINGSTORE", Const, 0, ""}, {"F_SETFD", Const, 0, ""}, {"F_SETFL", Const, 0, ""}, {"F_SETLEASE", Const, 0, ""}, {"F_SETLK", Const, 0, ""}, {"F_SETLK64", Const, 0, ""}, {"F_SETLKW", Const, 0, ""}, {"F_SETLKW64", Const, 0, ""}, {"F_SETLKWTIMEOUT", Const, 16, ""}, {"F_SETLK_REMOTE", Const, 0, ""}, {"F_SETNOSIGPIPE", Const, 0, ""}, {"F_SETOWN", Const, 0, ""}, {"F_SETOWN_EX", Const, 0, ""}, {"F_SETPIPE_SZ", Const, 0, ""}, {"F_SETPROTECTIONCLASS", Const, 0, ""}, {"F_SETSIG", Const, 0, ""}, {"F_SETSIZE", Const, 0, ""}, {"F_SHLCK", Const, 0, ""}, {"F_SINGLE_WRITER", Const, 16, ""}, {"F_TEST", Const, 0, ""}, {"F_THAW_FS", Const, 0, ""}, {"F_TLOCK", Const, 0, ""}, {"F_TRANSCODEKEY", Const, 16, ""}, {"F_ULOCK", Const, 0, ""}, {"F_UNLCK", Const, 0, ""}, {"F_UNLCKSYS", Const, 0, ""}, {"F_VOLPOSMODE", Const, 0, ""}, {"F_WRITEBOOTSTRAP", Const, 0, ""}, {"F_WRLCK", Const, 0, ""}, {"Faccessat", Func, 0, "func(dirfd int, path string, mode uint32, flags int) (err error)"}, {"Fallocate", Func, 0, "func(fd int, mode uint32, off int64, len int64) (err error)"}, {"Fbootstraptransfer_t", Type, 0, ""}, {"Fbootstraptransfer_t.Buffer", Field, 0, ""}, {"Fbootstraptransfer_t.Length", Field, 0, ""}, {"Fbootstraptransfer_t.Offset", Field, 0, ""}, {"Fchdir", Func, 0, "func(fd int) (err error)"}, {"Fchflags", Func, 0, ""}, {"Fchmod", Func, 0, "func(fd int, mode uint32) (err error)"}, {"Fchmodat", Func, 0, "func(dirfd int, path string, mode uint32, flags int) error"}, {"Fchown", Func, 0, "func(fd int, uid int, gid int) (err error)"}, {"Fchownat", Func, 0, "func(dirfd int, path string, uid int, gid int, flags int) (err error)"}, {"FcntlFlock", Func, 3, "func(fd uintptr, cmd int, lk *Flock_t) error"}, {"FdSet", Type, 0, ""}, {"FdSet.Bits", Field, 0, ""}, {"FdSet.X__fds_bits", Field, 0, ""}, {"Fdatasync", Func, 0, "func(fd int) (err error)"}, {"FileNotifyInformation", Type, 0, ""}, {"FileNotifyInformation.Action", Field, 0, ""}, {"FileNotifyInformation.FileName", Field, 0, ""}, {"FileNotifyInformation.FileNameLength", Field, 0, ""}, {"FileNotifyInformation.NextEntryOffset", Field, 0, ""}, {"Filetime", Type, 0, ""}, {"Filetime.HighDateTime", Field, 0, ""}, {"Filetime.LowDateTime", Field, 0, ""}, {"FindClose", Func, 0, ""}, {"FindFirstFile", Func, 0, ""}, {"FindNextFile", Func, 0, ""}, {"Flock", Func, 0, "func(fd int, how int) (err error)"}, {"Flock_t", Type, 0, ""}, {"Flock_t.Len", Field, 0, ""}, {"Flock_t.Pad_cgo_0", Field, 0, ""}, {"Flock_t.Pad_cgo_1", Field, 3, ""}, {"Flock_t.Pid", Field, 0, ""}, {"Flock_t.Start", Field, 0, ""}, {"Flock_t.Sysid", Field, 0, ""}, {"Flock_t.Type", Field, 0, ""}, {"Flock_t.Whence", Field, 0, ""}, {"FlushBpf", Func, 0, ""}, {"FlushFileBuffers", Func, 0, ""}, {"FlushViewOfFile", Func, 0, ""}, {"ForkExec", Func, 0, "func(argv0 string, argv []string, attr *ProcAttr) (pid int, err error)"}, {"ForkLock", Var, 0, ""}, {"FormatMessage", Func, 0, ""}, {"Fpathconf", Func, 0, ""}, {"FreeAddrInfoW", Func, 1, ""}, {"FreeEnvironmentStrings", Func, 0, ""}, {"FreeLibrary", Func, 0, ""}, {"Fsid", Type, 0, ""}, {"Fsid.Val", Field, 0, ""}, {"Fsid.X__fsid_val", Field, 2, ""}, {"Fsid.X__val", Field, 0, ""}, {"Fstat", Func, 0, "func(fd int, stat *Stat_t) (err error)"}, {"Fstatat", Func, 12, ""}, {"Fstatfs", Func, 0, "func(fd int, buf *Statfs_t) (err error)"}, {"Fstore_t", Type, 0, ""}, {"Fstore_t.Bytesalloc", Field, 0, ""}, {"Fstore_t.Flags", Field, 0, ""}, {"Fstore_t.Length", Field, 0, ""}, {"Fstore_t.Offset", Field, 0, ""}, {"Fstore_t.Posmode", Field, 0, ""}, {"Fsync", Func, 0, "func(fd int) (err error)"}, {"Ftruncate", Func, 0, "func(fd int, length int64) (err error)"}, {"FullPath", Func, 4, ""}, {"Futimes", Func, 0, "func(fd int, tv []Timeval) (err error)"}, {"Futimesat", Func, 0, "func(dirfd int, path string, tv []Timeval) (err error)"}, {"GENERIC_ALL", Const, 0, ""}, {"GENERIC_EXECUTE", Const, 0, ""}, {"GENERIC_READ", Const, 0, ""}, {"GENERIC_WRITE", Const, 0, ""}, {"GUID", Type, 1, ""}, {"GUID.Data1", Field, 1, ""}, {"GUID.Data2", Field, 1, ""}, {"GUID.Data3", Field, 1, ""}, {"GUID.Data4", Field, 1, ""}, {"GetAcceptExSockaddrs", Func, 0, ""}, {"GetAdaptersInfo", Func, 0, ""}, {"GetAddrInfoW", Func, 1, ""}, {"GetCommandLine", Func, 0, ""}, {"GetComputerName", Func, 0, ""}, {"GetConsoleMode", Func, 1, ""}, {"GetCurrentDirectory", Func, 0, ""}, {"GetCurrentProcess", Func, 0, ""}, {"GetEnvironmentStrings", Func, 0, ""}, {"GetEnvironmentVariable", Func, 0, ""}, {"GetExitCodeProcess", Func, 0, ""}, {"GetFileAttributes", Func, 0, ""}, {"GetFileAttributesEx", Func, 0, ""}, {"GetFileExInfoStandard", Const, 0, ""}, {"GetFileExMaxInfoLevel", Const, 0, ""}, {"GetFileInformationByHandle", Func, 0, ""}, {"GetFileType", Func, 0, ""}, {"GetFullPathName", Func, 0, ""}, {"GetHostByName", Func, 0, ""}, {"GetIfEntry", Func, 0, ""}, {"GetLastError", Func, 0, ""}, {"GetLengthSid", Func, 0, ""}, {"GetLongPathName", Func, 0, ""}, {"GetProcAddress", Func, 0, ""}, {"GetProcessTimes", Func, 0, ""}, {"GetProtoByName", Func, 0, ""}, {"GetQueuedCompletionStatus", Func, 0, ""}, {"GetServByName", Func, 0, ""}, {"GetShortPathName", Func, 0, ""}, {"GetStartupInfo", Func, 0, ""}, {"GetStdHandle", Func, 0, ""}, {"GetSystemTimeAsFileTime", Func, 0, ""}, {"GetTempPath", Func, 0, ""}, {"GetTimeZoneInformation", Func, 0, ""}, {"GetTokenInformation", Func, 0, ""}, {"GetUserNameEx", Func, 0, ""}, {"GetUserProfileDirectory", Func, 0, ""}, {"GetVersion", Func, 0, ""}, {"Getcwd", Func, 0, "func(buf []byte) (n int, err error)"}, {"Getdents", Func, 0, "func(fd int, buf []byte) (n int, err error)"}, {"Getdirentries", Func, 0, ""}, {"Getdtablesize", Func, 0, ""}, {"Getegid", Func, 0, "func() (egid int)"}, {"Getenv", Func, 0, "func(key string) (value string, found bool)"}, {"Geteuid", Func, 0, "func() (euid int)"}, {"Getfsstat", Func, 0, ""}, {"Getgid", Func, 0, "func() (gid int)"}, {"Getgroups", Func, 0, "func() (gids []int, err error)"}, {"Getpagesize", Func, 0, "func() int"}, {"Getpeername", Func, 0, "func(fd int) (sa Sockaddr, err error)"}, {"Getpgid", Func, 0, "func(pid int) (pgid int, err error)"}, {"Getpgrp", Func, 0, "func() (pid int)"}, {"Getpid", Func, 0, "func() (pid int)"}, {"Getppid", Func, 0, "func() (ppid int)"}, {"Getpriority", Func, 0, "func(which int, who int) (prio int, err error)"}, {"Getrlimit", Func, 0, "func(resource int, rlim *Rlimit) (err error)"}, {"Getrusage", Func, 0, "func(who int, rusage *Rusage) (err error)"}, {"Getsid", Func, 0, ""}, {"Getsockname", Func, 0, "func(fd int) (sa Sockaddr, err error)"}, {"Getsockopt", Func, 1, ""}, {"GetsockoptByte", Func, 0, ""}, {"GetsockoptICMPv6Filter", Func, 2, "func(fd int, level int, opt int) (*ICMPv6Filter, error)"}, {"GetsockoptIPMreq", Func, 0, "func(fd int, level int, opt int) (*IPMreq, error)"}, {"GetsockoptIPMreqn", Func, 0, "func(fd int, level int, opt int) (*IPMreqn, error)"}, {"GetsockoptIPv6MTUInfo", Func, 2, "func(fd int, level int, opt int) (*IPv6MTUInfo, error)"}, {"GetsockoptIPv6Mreq", Func, 0, "func(fd int, level int, opt int) (*IPv6Mreq, error)"}, {"GetsockoptInet4Addr", Func, 0, "func(fd int, level int, opt int) (value [4]byte, err error)"}, {"GetsockoptInt", Func, 0, "func(fd int, level int, opt int) (value int, err error)"}, {"GetsockoptUcred", Func, 1, "func(fd int, level int, opt int) (*Ucred, error)"}, {"Gettid", Func, 0, "func() (tid int)"}, {"Gettimeofday", Func, 0, "func(tv *Timeval) (err error)"}, {"Getuid", Func, 0, "func() (uid int)"}, {"Getwd", Func, 0, "func() (wd string, err error)"}, {"Getxattr", Func, 1, "func(path string, attr string, dest []byte) (sz int, err error)"}, {"HANDLE_FLAG_INHERIT", Const, 0, ""}, {"HKEY_CLASSES_ROOT", Const, 0, ""}, {"HKEY_CURRENT_CONFIG", Const, 0, ""}, {"HKEY_CURRENT_USER", Const, 0, ""}, {"HKEY_DYN_DATA", Const, 0, ""}, {"HKEY_LOCAL_MACHINE", Const, 0, ""}, {"HKEY_PERFORMANCE_DATA", Const, 0, ""}, {"HKEY_USERS", Const, 0, ""}, {"HUPCL", Const, 0, ""}, {"Handle", Type, 0, ""}, {"Hostent", Type, 0, ""}, {"Hostent.AddrList", Field, 0, ""}, {"Hostent.AddrType", Field, 0, ""}, {"Hostent.Aliases", Field, 0, ""}, {"Hostent.Length", Field, 0, ""}, {"Hostent.Name", Field, 0, ""}, {"ICANON", Const, 0, ""}, {"ICMP6_FILTER", Const, 2, ""}, {"ICMPV6_FILTER", Const, 2, ""}, {"ICMPv6Filter", Type, 2, ""}, {"ICMPv6Filter.Data", Field, 2, ""}, {"ICMPv6Filter.Filt", Field, 2, ""}, {"ICRNL", Const, 0, ""}, {"IEXTEN", Const, 0, ""}, {"IFAN_ARRIVAL", Const, 1, ""}, {"IFAN_DEPARTURE", Const, 1, ""}, {"IFA_ADDRESS", Const, 0, ""}, {"IFA_ANYCAST", Const, 0, ""}, {"IFA_BROADCAST", Const, 0, ""}, {"IFA_CACHEINFO", Const, 0, ""}, {"IFA_F_DADFAILED", Const, 0, ""}, {"IFA_F_DEPRECATED", Const, 0, ""}, {"IFA_F_HOMEADDRESS", Const, 0, ""}, {"IFA_F_NODAD", Const, 0, ""}, {"IFA_F_OPTIMISTIC", Const, 0, ""}, {"IFA_F_PERMANENT", Const, 0, ""}, {"IFA_F_SECONDARY", Const, 0, ""}, {"IFA_F_TEMPORARY", Const, 0, ""}, {"IFA_F_TENTATIVE", Const, 0, ""}, {"IFA_LABEL", Const, 0, ""}, {"IFA_LOCAL", Const, 0, ""}, {"IFA_MAX", Const, 0, ""}, {"IFA_MULTICAST", Const, 0, ""}, {"IFA_ROUTE", Const, 1, ""}, {"IFA_UNSPEC", Const, 0, ""}, {"IFF_ALLMULTI", Const, 0, ""}, {"IFF_ALTPHYS", Const, 0, ""}, {"IFF_AUTOMEDIA", Const, 0, ""}, {"IFF_BROADCAST", Const, 0, ""}, {"IFF_CANTCHANGE", Const, 0, ""}, {"IFF_CANTCONFIG", Const, 1, ""}, {"IFF_DEBUG", Const, 0, ""}, {"IFF_DRV_OACTIVE", Const, 0, ""}, {"IFF_DRV_RUNNING", Const, 0, ""}, {"IFF_DYING", Const, 0, ""}, {"IFF_DYNAMIC", Const, 0, ""}, {"IFF_LINK0", Const, 0, ""}, {"IFF_LINK1", Const, 0, ""}, {"IFF_LINK2", Const, 0, ""}, {"IFF_LOOPBACK", Const, 0, ""}, {"IFF_MASTER", Const, 0, ""}, {"IFF_MONITOR", Const, 0, ""}, {"IFF_MULTICAST", Const, 0, ""}, {"IFF_NOARP", Const, 0, ""}, {"IFF_NOTRAILERS", Const, 0, ""}, {"IFF_NO_PI", Const, 0, ""}, {"IFF_OACTIVE", Const, 0, ""}, {"IFF_ONE_QUEUE", Const, 0, ""}, {"IFF_POINTOPOINT", Const, 0, ""}, {"IFF_POINTTOPOINT", Const, 0, ""}, {"IFF_PORTSEL", Const, 0, ""}, {"IFF_PPROMISC", Const, 0, ""}, {"IFF_PROMISC", Const, 0, ""}, {"IFF_RENAMING", Const, 0, ""}, {"IFF_RUNNING", Const, 0, ""}, {"IFF_SIMPLEX", Const, 0, ""}, {"IFF_SLAVE", Const, 0, ""}, {"IFF_SMART", Const, 0, ""}, {"IFF_STATICARP", Const, 0, ""}, {"IFF_TAP", Const, 0, ""}, {"IFF_TUN", Const, 0, ""}, {"IFF_TUN_EXCL", Const, 0, ""}, {"IFF_UP", Const, 0, ""}, {"IFF_VNET_HDR", Const, 0, ""}, {"IFLA_ADDRESS", Const, 0, ""}, {"IFLA_BROADCAST", Const, 0, ""}, {"IFLA_COST", Const, 0, ""}, {"IFLA_IFALIAS", Const, 0, ""}, {"IFLA_IFNAME", Const, 0, ""}, {"IFLA_LINK", Const, 0, ""}, {"IFLA_LINKINFO", Const, 0, ""}, {"IFLA_LINKMODE", Const, 0, ""}, {"IFLA_MAP", Const, 0, ""}, {"IFLA_MASTER", Const, 0, ""}, {"IFLA_MAX", Const, 0, ""}, {"IFLA_MTU", Const, 0, ""}, {"IFLA_NET_NS_PID", Const, 0, ""}, {"IFLA_OPERSTATE", Const, 0, ""}, {"IFLA_PRIORITY", Const, 0, ""}, {"IFLA_PROTINFO", Const, 0, ""}, {"IFLA_QDISC", Const, 0, ""}, {"IFLA_STATS", Const, 0, ""}, {"IFLA_TXQLEN", Const, 0, ""}, {"IFLA_UNSPEC", Const, 0, ""}, {"IFLA_WEIGHT", Const, 0, ""}, {"IFLA_WIRELESS", Const, 0, ""}, {"IFNAMSIZ", Const, 0, ""}, {"IFT_1822", Const, 0, ""}, {"IFT_A12MPPSWITCH", Const, 0, ""}, {"IFT_AAL2", Const, 0, ""}, {"IFT_AAL5", Const, 0, ""}, {"IFT_ADSL", Const, 0, ""}, {"IFT_AFLANE8023", Const, 0, ""}, {"IFT_AFLANE8025", Const, 0, ""}, {"IFT_ARAP", Const, 0, ""}, {"IFT_ARCNET", Const, 0, ""}, {"IFT_ARCNETPLUS", Const, 0, ""}, {"IFT_ASYNC", Const, 0, ""}, {"IFT_ATM", Const, 0, ""}, {"IFT_ATMDXI", Const, 0, ""}, {"IFT_ATMFUNI", Const, 0, ""}, {"IFT_ATMIMA", Const, 0, ""}, {"IFT_ATMLOGICAL", Const, 0, ""}, {"IFT_ATMRADIO", Const, 0, ""}, {"IFT_ATMSUBINTERFACE", Const, 0, ""}, {"IFT_ATMVCIENDPT", Const, 0, ""}, {"IFT_ATMVIRTUAL", Const, 0, ""}, {"IFT_BGPPOLICYACCOUNTING", Const, 0, ""}, {"IFT_BLUETOOTH", Const, 1, ""}, {"IFT_BRIDGE", Const, 0, ""}, {"IFT_BSC", Const, 0, ""}, {"IFT_CARP", Const, 0, ""}, {"IFT_CCTEMUL", Const, 0, ""}, {"IFT_CELLULAR", Const, 0, ""}, {"IFT_CEPT", Const, 0, ""}, {"IFT_CES", Const, 0, ""}, {"IFT_CHANNEL", Const, 0, ""}, {"IFT_CNR", Const, 0, ""}, {"IFT_COFFEE", Const, 0, ""}, {"IFT_COMPOSITELINK", Const, 0, ""}, {"IFT_DCN", Const, 0, ""}, {"IFT_DIGITALPOWERLINE", Const, 0, ""}, {"IFT_DIGITALWRAPPEROVERHEADCHANNEL", Const, 0, ""}, {"IFT_DLSW", Const, 0, ""}, {"IFT_DOCSCABLEDOWNSTREAM", Const, 0, ""}, {"IFT_DOCSCABLEMACLAYER", Const, 0, ""}, {"IFT_DOCSCABLEUPSTREAM", Const, 0, ""}, {"IFT_DOCSCABLEUPSTREAMCHANNEL", Const, 1, ""}, {"IFT_DS0", Const, 0, ""}, {"IFT_DS0BUNDLE", Const, 0, ""}, {"IFT_DS1FDL", Const, 0, ""}, {"IFT_DS3", Const, 0, ""}, {"IFT_DTM", Const, 0, ""}, {"IFT_DUMMY", Const, 1, ""}, {"IFT_DVBASILN", Const, 0, ""}, {"IFT_DVBASIOUT", Const, 0, ""}, {"IFT_DVBRCCDOWNSTREAM", Const, 0, ""}, {"IFT_DVBRCCMACLAYER", Const, 0, ""}, {"IFT_DVBRCCUPSTREAM", Const, 0, ""}, {"IFT_ECONET", Const, 1, ""}, {"IFT_ENC", Const, 0, ""}, {"IFT_EON", Const, 0, ""}, {"IFT_EPLRS", Const, 0, ""}, {"IFT_ESCON", Const, 0, ""}, {"IFT_ETHER", Const, 0, ""}, {"IFT_FAITH", Const, 0, ""}, {"IFT_FAST", Const, 0, ""}, {"IFT_FASTETHER", Const, 0, ""}, {"IFT_FASTETHERFX", Const, 0, ""}, {"IFT_FDDI", Const, 0, ""}, {"IFT_FIBRECHANNEL", Const, 0, ""}, {"IFT_FRAMERELAYINTERCONNECT", Const, 0, ""}, {"IFT_FRAMERELAYMPI", Const, 0, ""}, {"IFT_FRDLCIENDPT", Const, 0, ""}, {"IFT_FRELAY", Const, 0, ""}, {"IFT_FRELAYDCE", Const, 0, ""}, {"IFT_FRF16MFRBUNDLE", Const, 0, ""}, {"IFT_FRFORWARD", Const, 0, ""}, {"IFT_G703AT2MB", Const, 0, ""}, {"IFT_G703AT64K", Const, 0, ""}, {"IFT_GIF", Const, 0, ""}, {"IFT_GIGABITETHERNET", Const, 0, ""}, {"IFT_GR303IDT", Const, 0, ""}, {"IFT_GR303RDT", Const, 0, ""}, {"IFT_H323GATEKEEPER", Const, 0, ""}, {"IFT_H323PROXY", Const, 0, ""}, {"IFT_HDH1822", Const, 0, ""}, {"IFT_HDLC", Const, 0, ""}, {"IFT_HDSL2", Const, 0, ""}, {"IFT_HIPERLAN2", Const, 0, ""}, {"IFT_HIPPI", Const, 0, ""}, {"IFT_HIPPIINTERFACE", Const, 0, ""}, {"IFT_HOSTPAD", Const, 0, ""}, {"IFT_HSSI", Const, 0, ""}, {"IFT_HY", Const, 0, ""}, {"IFT_IBM370PARCHAN", Const, 0, ""}, {"IFT_IDSL", Const, 0, ""}, {"IFT_IEEE1394", Const, 0, ""}, {"IFT_IEEE80211", Const, 0, ""}, {"IFT_IEEE80212", Const, 0, ""}, {"IFT_IEEE8023ADLAG", Const, 0, ""}, {"IFT_IFGSN", Const, 0, ""}, {"IFT_IMT", Const, 0, ""}, {"IFT_INFINIBAND", Const, 1, ""}, {"IFT_INTERLEAVE", Const, 0, ""}, {"IFT_IP", Const, 0, ""}, {"IFT_IPFORWARD", Const, 0, ""}, {"IFT_IPOVERATM", Const, 0, ""}, {"IFT_IPOVERCDLC", Const, 0, ""}, {"IFT_IPOVERCLAW", Const, 0, ""}, {"IFT_IPSWITCH", Const, 0, ""}, {"IFT_IPXIP", Const, 0, ""}, {"IFT_ISDN", Const, 0, ""}, {"IFT_ISDNBASIC", Const, 0, ""}, {"IFT_ISDNPRIMARY", Const, 0, ""}, {"IFT_ISDNS", Const, 0, ""}, {"IFT_ISDNU", Const, 0, ""}, {"IFT_ISO88022LLC", Const, 0, ""}, {"IFT_ISO88023", Const, 0, ""}, {"IFT_ISO88024", Const, 0, ""}, {"IFT_ISO88025", Const, 0, ""}, {"IFT_ISO88025CRFPINT", Const, 0, ""}, {"IFT_ISO88025DTR", Const, 0, ""}, {"IFT_ISO88025FIBER", Const, 0, ""}, {"IFT_ISO88026", Const, 0, ""}, {"IFT_ISUP", Const, 0, ""}, {"IFT_L2VLAN", Const, 0, ""}, {"IFT_L3IPVLAN", Const, 0, ""}, {"IFT_L3IPXVLAN", Const, 0, ""}, {"IFT_LAPB", Const, 0, ""}, {"IFT_LAPD", Const, 0, ""}, {"IFT_LAPF", Const, 0, ""}, {"IFT_LINEGROUP", Const, 1, ""}, {"IFT_LOCALTALK", Const, 0, ""}, {"IFT_LOOP", Const, 0, ""}, {"IFT_MEDIAMAILOVERIP", Const, 0, ""}, {"IFT_MFSIGLINK", Const, 0, ""}, {"IFT_MIOX25", Const, 0, ""}, {"IFT_MODEM", Const, 0, ""}, {"IFT_MPC", Const, 0, ""}, {"IFT_MPLS", Const, 0, ""}, {"IFT_MPLSTUNNEL", Const, 0, ""}, {"IFT_MSDSL", Const, 0, ""}, {"IFT_MVL", Const, 0, ""}, {"IFT_MYRINET", Const, 0, ""}, {"IFT_NFAS", Const, 0, ""}, {"IFT_NSIP", Const, 0, ""}, {"IFT_OPTICALCHANNEL", Const, 0, ""}, {"IFT_OPTICALTRANSPORT", Const, 0, ""}, {"IFT_OTHER", Const, 0, ""}, {"IFT_P10", Const, 0, ""}, {"IFT_P80", Const, 0, ""}, {"IFT_PARA", Const, 0, ""}, {"IFT_PDP", Const, 0, ""}, {"IFT_PFLOG", Const, 0, ""}, {"IFT_PFLOW", Const, 1, ""}, {"IFT_PFSYNC", Const, 0, ""}, {"IFT_PLC", Const, 0, ""}, {"IFT_PON155", Const, 1, ""}, {"IFT_PON622", Const, 1, ""}, {"IFT_POS", Const, 0, ""}, {"IFT_PPP", Const, 0, ""}, {"IFT_PPPMULTILINKBUNDLE", Const, 0, ""}, {"IFT_PROPATM", Const, 1, ""}, {"IFT_PROPBWAP2MP", Const, 0, ""}, {"IFT_PROPCNLS", Const, 0, ""}, {"IFT_PROPDOCSWIRELESSDOWNSTREAM", Const, 0, ""}, {"IFT_PROPDOCSWIRELESSMACLAYER", Const, 0, ""}, {"IFT_PROPDOCSWIRELESSUPSTREAM", Const, 0, ""}, {"IFT_PROPMUX", Const, 0, ""}, {"IFT_PROPVIRTUAL", Const, 0, ""}, {"IFT_PROPWIRELESSP2P", Const, 0, ""}, {"IFT_PTPSERIAL", Const, 0, ""}, {"IFT_PVC", Const, 0, ""}, {"IFT_Q2931", Const, 1, ""}, {"IFT_QLLC", Const, 0, ""}, {"IFT_RADIOMAC", Const, 0, ""}, {"IFT_RADSL", Const, 0, ""}, {"IFT_REACHDSL", Const, 0, ""}, {"IFT_RFC1483", Const, 0, ""}, {"IFT_RS232", Const, 0, ""}, {"IFT_RSRB", Const, 0, ""}, {"IFT_SDLC", Const, 0, ""}, {"IFT_SDSL", Const, 0, ""}, {"IFT_SHDSL", Const, 0, ""}, {"IFT_SIP", Const, 0, ""}, {"IFT_SIPSIG", Const, 1, ""}, {"IFT_SIPTG", Const, 1, ""}, {"IFT_SLIP", Const, 0, ""}, {"IFT_SMDSDXI", Const, 0, ""}, {"IFT_SMDSICIP", Const, 0, ""}, {"IFT_SONET", Const, 0, ""}, {"IFT_SONETOVERHEADCHANNEL", Const, 0, ""}, {"IFT_SONETPATH", Const, 0, ""}, {"IFT_SONETVT", Const, 0, ""}, {"IFT_SRP", Const, 0, ""}, {"IFT_SS7SIGLINK", Const, 0, ""}, {"IFT_STACKTOSTACK", Const, 0, ""}, {"IFT_STARLAN", Const, 0, ""}, {"IFT_STF", Const, 0, ""}, {"IFT_T1", Const, 0, ""}, {"IFT_TDLC", Const, 0, ""}, {"IFT_TELINK", Const, 1, ""}, {"IFT_TERMPAD", Const, 0, ""}, {"IFT_TR008", Const, 0, ""}, {"IFT_TRANSPHDLC", Const, 0, ""}, {"IFT_TUNNEL", Const, 0, ""}, {"IFT_ULTRA", Const, 0, ""}, {"IFT_USB", Const, 0, ""}, {"IFT_V11", Const, 0, ""}, {"IFT_V35", Const, 0, ""}, {"IFT_V36", Const, 0, ""}, {"IFT_V37", Const, 0, ""}, {"IFT_VDSL", Const, 0, ""}, {"IFT_VIRTUALIPADDRESS", Const, 0, ""}, {"IFT_VIRTUALTG", Const, 1, ""}, {"IFT_VOICEDID", Const, 1, ""}, {"IFT_VOICEEM", Const, 0, ""}, {"IFT_VOICEEMFGD", Const, 1, ""}, {"IFT_VOICEENCAP", Const, 0, ""}, {"IFT_VOICEFGDEANA", Const, 1, ""}, {"IFT_VOICEFXO", Const, 0, ""}, {"IFT_VOICEFXS", Const, 0, ""}, {"IFT_VOICEOVERATM", Const, 0, ""}, {"IFT_VOICEOVERCABLE", Const, 1, ""}, {"IFT_VOICEOVERFRAMERELAY", Const, 0, ""}, {"IFT_VOICEOVERIP", Const, 0, ""}, {"IFT_X213", Const, 0, ""}, {"IFT_X25", Const, 0, ""}, {"IFT_X25DDN", Const, 0, ""}, {"IFT_X25HUNTGROUP", Const, 0, ""}, {"IFT_X25MLP", Const, 0, ""}, {"IFT_X25PLE", Const, 0, ""}, {"IFT_XETHER", Const, 0, ""}, {"IGNBRK", Const, 0, ""}, {"IGNCR", Const, 0, ""}, {"IGNORE", Const, 0, ""}, {"IGNPAR", Const, 0, ""}, {"IMAXBEL", Const, 0, ""}, {"INFINITE", Const, 0, ""}, {"INLCR", Const, 0, ""}, {"INPCK", Const, 0, ""}, {"INVALID_FILE_ATTRIBUTES", Const, 0, ""}, {"IN_ACCESS", Const, 0, ""}, {"IN_ALL_EVENTS", Const, 0, ""}, {"IN_ATTRIB", Const, 0, ""}, {"IN_CLASSA_HOST", Const, 0, ""}, {"IN_CLASSA_MAX", Const, 0, ""}, {"IN_CLASSA_NET", Const, 0, ""}, {"IN_CLASSA_NSHIFT", Const, 0, ""}, {"IN_CLASSB_HOST", Const, 0, ""}, {"IN_CLASSB_MAX", Const, 0, ""}, {"IN_CLASSB_NET", Const, 0, ""}, {"IN_CLASSB_NSHIFT", Const, 0, ""}, {"IN_CLASSC_HOST", Const, 0, ""}, {"IN_CLASSC_NET", Const, 0, ""}, {"IN_CLASSC_NSHIFT", Const, 0, ""}, {"IN_CLASSD_HOST", Const, 0, ""}, {"IN_CLASSD_NET", Const, 0, ""}, {"IN_CLASSD_NSHIFT", Const, 0, ""}, {"IN_CLOEXEC", Const, 0, ""}, {"IN_CLOSE", Const, 0, ""}, {"IN_CLOSE_NOWRITE", Const, 0, ""}, {"IN_CLOSE_WRITE", Const, 0, ""}, {"IN_CREATE", Const, 0, ""}, {"IN_DELETE", Const, 0, ""}, {"IN_DELETE_SELF", Const, 0, ""}, {"IN_DONT_FOLLOW", Const, 0, ""}, {"IN_EXCL_UNLINK", Const, 0, ""}, {"IN_IGNORED", Const, 0, ""}, {"IN_ISDIR", Const, 0, ""}, {"IN_LINKLOCALNETNUM", Const, 0, ""}, {"IN_LOOPBACKNET", Const, 0, ""}, {"IN_MASK_ADD", Const, 0, ""}, {"IN_MODIFY", Const, 0, ""}, {"IN_MOVE", Const, 0, ""}, {"IN_MOVED_FROM", Const, 0, ""}, {"IN_MOVED_TO", Const, 0, ""}, {"IN_MOVE_SELF", Const, 0, ""}, {"IN_NONBLOCK", Const, 0, ""}, {"IN_ONESHOT", Const, 0, ""}, {"IN_ONLYDIR", Const, 0, ""}, {"IN_OPEN", Const, 0, ""}, {"IN_Q_OVERFLOW", Const, 0, ""}, {"IN_RFC3021_HOST", Const, 1, ""}, {"IN_RFC3021_MASK", Const, 1, ""}, {"IN_RFC3021_NET", Const, 1, ""}, {"IN_RFC3021_NSHIFT", Const, 1, ""}, {"IN_UNMOUNT", Const, 0, ""}, {"IOC_IN", Const, 1, ""}, {"IOC_INOUT", Const, 1, ""}, {"IOC_OUT", Const, 1, ""}, {"IOC_VENDOR", Const, 3, ""}, {"IOC_WS2", Const, 1, ""}, {"IO_REPARSE_TAG_SYMLINK", Const, 4, ""}, {"IPMreq", Type, 0, ""}, {"IPMreq.Interface", Field, 0, ""}, {"IPMreq.Multiaddr", Field, 0, ""}, {"IPMreqn", Type, 0, ""}, {"IPMreqn.Address", Field, 0, ""}, {"IPMreqn.Ifindex", Field, 0, ""}, {"IPMreqn.Multiaddr", Field, 0, ""}, {"IPPROTO_3PC", Const, 0, ""}, {"IPPROTO_ADFS", Const, 0, ""}, {"IPPROTO_AH", Const, 0, ""}, {"IPPROTO_AHIP", Const, 0, ""}, {"IPPROTO_APES", Const, 0, ""}, {"IPPROTO_ARGUS", Const, 0, ""}, {"IPPROTO_AX25", Const, 0, ""}, {"IPPROTO_BHA", Const, 0, ""}, {"IPPROTO_BLT", Const, 0, ""}, {"IPPROTO_BRSATMON", Const, 0, ""}, {"IPPROTO_CARP", Const, 0, ""}, {"IPPROTO_CFTP", Const, 0, ""}, {"IPPROTO_CHAOS", Const, 0, ""}, {"IPPROTO_CMTP", Const, 0, ""}, {"IPPROTO_COMP", Const, 0, ""}, {"IPPROTO_CPHB", Const, 0, ""}, {"IPPROTO_CPNX", Const, 0, ""}, {"IPPROTO_DCCP", Const, 0, ""}, {"IPPROTO_DDP", Const, 0, ""}, {"IPPROTO_DGP", Const, 0, ""}, {"IPPROTO_DIVERT", Const, 0, ""}, {"IPPROTO_DIVERT_INIT", Const, 3, ""}, {"IPPROTO_DIVERT_RESP", Const, 3, ""}, {"IPPROTO_DONE", Const, 0, ""}, {"IPPROTO_DSTOPTS", Const, 0, ""}, {"IPPROTO_EGP", Const, 0, ""}, {"IPPROTO_EMCON", Const, 0, ""}, {"IPPROTO_ENCAP", Const, 0, ""}, {"IPPROTO_EON", Const, 0, ""}, {"IPPROTO_ESP", Const, 0, ""}, {"IPPROTO_ETHERIP", Const, 0, ""}, {"IPPROTO_FRAGMENT", Const, 0, ""}, {"IPPROTO_GGP", Const, 0, ""}, {"IPPROTO_GMTP", Const, 0, ""}, {"IPPROTO_GRE", Const, 0, ""}, {"IPPROTO_HELLO", Const, 0, ""}, {"IPPROTO_HMP", Const, 0, ""}, {"IPPROTO_HOPOPTS", Const, 0, ""}, {"IPPROTO_ICMP", Const, 0, ""}, {"IPPROTO_ICMPV6", Const, 0, ""}, {"IPPROTO_IDP", Const, 0, ""}, {"IPPROTO_IDPR", Const, 0, ""}, {"IPPROTO_IDRP", Const, 0, ""}, {"IPPROTO_IGMP", Const, 0, ""}, {"IPPROTO_IGP", Const, 0, ""}, {"IPPROTO_IGRP", Const, 0, ""}, {"IPPROTO_IL", Const, 0, ""}, {"IPPROTO_INLSP", Const, 0, ""}, {"IPPROTO_INP", Const, 0, ""}, {"IPPROTO_IP", Const, 0, ""}, {"IPPROTO_IPCOMP", Const, 0, ""}, {"IPPROTO_IPCV", Const, 0, ""}, {"IPPROTO_IPEIP", Const, 0, ""}, {"IPPROTO_IPIP", Const, 0, ""}, {"IPPROTO_IPPC", Const, 0, ""}, {"IPPROTO_IPV4", Const, 0, ""}, {"IPPROTO_IPV6", Const, 0, ""}, {"IPPROTO_IPV6_ICMP", Const, 1, ""}, {"IPPROTO_IRTP", Const, 0, ""}, {"IPPROTO_KRYPTOLAN", Const, 0, ""}, {"IPPROTO_LARP", Const, 0, ""}, {"IPPROTO_LEAF1", Const, 0, ""}, {"IPPROTO_LEAF2", Const, 0, ""}, {"IPPROTO_MAX", Const, 0, ""}, {"IPPROTO_MAXID", Const, 0, ""}, {"IPPROTO_MEAS", Const, 0, ""}, {"IPPROTO_MH", Const, 1, ""}, {"IPPROTO_MHRP", Const, 0, ""}, {"IPPROTO_MICP", Const, 0, ""}, {"IPPROTO_MOBILE", Const, 0, ""}, {"IPPROTO_MPLS", Const, 1, ""}, {"IPPROTO_MTP", Const, 0, ""}, {"IPPROTO_MUX", Const, 0, ""}, {"IPPROTO_ND", Const, 0, ""}, {"IPPROTO_NHRP", Const, 0, ""}, {"IPPROTO_NONE", Const, 0, ""}, {"IPPROTO_NSP", Const, 0, ""}, {"IPPROTO_NVPII", Const, 0, ""}, {"IPPROTO_OLD_DIVERT", Const, 0, ""}, {"IPPROTO_OSPFIGP", Const, 0, ""}, {"IPPROTO_PFSYNC", Const, 0, ""}, {"IPPROTO_PGM", Const, 0, ""}, {"IPPROTO_PIGP", Const, 0, ""}, {"IPPROTO_PIM", Const, 0, ""}, {"IPPROTO_PRM", Const, 0, ""}, {"IPPROTO_PUP", Const, 0, ""}, {"IPPROTO_PVP", Const, 0, ""}, {"IPPROTO_RAW", Const, 0, ""}, {"IPPROTO_RCCMON", Const, 0, ""}, {"IPPROTO_RDP", Const, 0, ""}, {"IPPROTO_ROUTING", Const, 0, ""}, {"IPPROTO_RSVP", Const, 0, ""}, {"IPPROTO_RVD", Const, 0, ""}, {"IPPROTO_SATEXPAK", Const, 0, ""}, {"IPPROTO_SATMON", Const, 0, ""}, {"IPPROTO_SCCSP", Const, 0, ""}, {"IPPROTO_SCTP", Const, 0, ""}, {"IPPROTO_SDRP", Const, 0, ""}, {"IPPROTO_SEND", Const, 1, ""}, {"IPPROTO_SEP", Const, 0, ""}, {"IPPROTO_SKIP", Const, 0, ""}, {"IPPROTO_SPACER", Const, 0, ""}, {"IPPROTO_SRPC", Const, 0, ""}, {"IPPROTO_ST", Const, 0, ""}, {"IPPROTO_SVMTP", Const, 0, ""}, {"IPPROTO_SWIPE", Const, 0, ""}, {"IPPROTO_TCF", Const, 0, ""}, {"IPPROTO_TCP", Const, 0, ""}, {"IPPROTO_TLSP", Const, 0, ""}, {"IPPROTO_TP", Const, 0, ""}, {"IPPROTO_TPXX", Const, 0, ""}, {"IPPROTO_TRUNK1", Const, 0, ""}, {"IPPROTO_TRUNK2", Const, 0, ""}, {"IPPROTO_TTP", Const, 0, ""}, {"IPPROTO_UDP", Const, 0, ""}, {"IPPROTO_UDPLITE", Const, 0, ""}, {"IPPROTO_VINES", Const, 0, ""}, {"IPPROTO_VISA", Const, 0, ""}, {"IPPROTO_VMTP", Const, 0, ""}, {"IPPROTO_VRRP", Const, 1, ""}, {"IPPROTO_WBEXPAK", Const, 0, ""}, {"IPPROTO_WBMON", Const, 0, ""}, {"IPPROTO_WSN", Const, 0, ""}, {"IPPROTO_XNET", Const, 0, ""}, {"IPPROTO_XTP", Const, 0, ""}, {"IPV6_2292DSTOPTS", Const, 0, ""}, {"IPV6_2292HOPLIMIT", Const, 0, ""}, {"IPV6_2292HOPOPTS", Const, 0, ""}, {"IPV6_2292NEXTHOP", Const, 0, ""}, {"IPV6_2292PKTINFO", Const, 0, ""}, {"IPV6_2292PKTOPTIONS", Const, 0, ""}, {"IPV6_2292RTHDR", Const, 0, ""}, {"IPV6_ADDRFORM", Const, 0, ""}, {"IPV6_ADD_MEMBERSHIP", Const, 0, ""}, {"IPV6_AUTHHDR", Const, 0, ""}, {"IPV6_AUTH_LEVEL", Const, 1, ""}, {"IPV6_AUTOFLOWLABEL", Const, 0, ""}, {"IPV6_BINDANY", Const, 0, ""}, {"IPV6_BINDV6ONLY", Const, 0, ""}, {"IPV6_BOUND_IF", Const, 0, ""}, {"IPV6_CHECKSUM", Const, 0, ""}, {"IPV6_DEFAULT_MULTICAST_HOPS", Const, 0, ""}, {"IPV6_DEFAULT_MULTICAST_LOOP", Const, 0, ""}, {"IPV6_DEFHLIM", Const, 0, ""}, {"IPV6_DONTFRAG", Const, 0, ""}, {"IPV6_DROP_MEMBERSHIP", Const, 0, ""}, {"IPV6_DSTOPTS", Const, 0, ""}, {"IPV6_ESP_NETWORK_LEVEL", Const, 1, ""}, {"IPV6_ESP_TRANS_LEVEL", Const, 1, ""}, {"IPV6_FAITH", Const, 0, ""}, {"IPV6_FLOWINFO_MASK", Const, 0, ""}, {"IPV6_FLOWLABEL_MASK", Const, 0, ""}, {"IPV6_FRAGTTL", Const, 0, ""}, {"IPV6_FW_ADD", Const, 0, ""}, {"IPV6_FW_DEL", Const, 0, ""}, {"IPV6_FW_FLUSH", Const, 0, ""}, {"IPV6_FW_GET", Const, 0, ""}, {"IPV6_FW_ZERO", Const, 0, ""}, {"IPV6_HLIMDEC", Const, 0, ""}, {"IPV6_HOPLIMIT", Const, 0, ""}, {"IPV6_HOPOPTS", Const, 0, ""}, {"IPV6_IPCOMP_LEVEL", Const, 1, ""}, {"IPV6_IPSEC_POLICY", Const, 0, ""}, {"IPV6_JOIN_ANYCAST", Const, 0, ""}, {"IPV6_JOIN_GROUP", Const, 0, ""}, {"IPV6_LEAVE_ANYCAST", Const, 0, ""}, {"IPV6_LEAVE_GROUP", Const, 0, ""}, {"IPV6_MAXHLIM", Const, 0, ""}, {"IPV6_MAXOPTHDR", Const, 0, ""}, {"IPV6_MAXPACKET", Const, 0, ""}, {"IPV6_MAX_GROUP_SRC_FILTER", Const, 0, ""}, {"IPV6_MAX_MEMBERSHIPS", Const, 0, ""}, {"IPV6_MAX_SOCK_SRC_FILTER", Const, 0, ""}, {"IPV6_MIN_MEMBERSHIPS", Const, 0, ""}, {"IPV6_MMTU", Const, 0, ""}, {"IPV6_MSFILTER", Const, 0, ""}, {"IPV6_MTU", Const, 0, ""}, {"IPV6_MTU_DISCOVER", Const, 0, ""}, {"IPV6_MULTICAST_HOPS", Const, 0, ""}, {"IPV6_MULTICAST_IF", Const, 0, ""}, {"IPV6_MULTICAST_LOOP", Const, 0, ""}, {"IPV6_NEXTHOP", Const, 0, ""}, {"IPV6_OPTIONS", Const, 1, ""}, {"IPV6_PATHMTU", Const, 0, ""}, {"IPV6_PIPEX", Const, 1, ""}, {"IPV6_PKTINFO", Const, 0, ""}, {"IPV6_PMTUDISC_DO", Const, 0, ""}, {"IPV6_PMTUDISC_DONT", Const, 0, ""}, {"IPV6_PMTUDISC_PROBE", Const, 0, ""}, {"IPV6_PMTUDISC_WANT", Const, 0, ""}, {"IPV6_PORTRANGE", Const, 0, ""}, {"IPV6_PORTRANGE_DEFAULT", Const, 0, ""}, {"IPV6_PORTRANGE_HIGH", Const, 0, ""}, {"IPV6_PORTRANGE_LOW", Const, 0, ""}, {"IPV6_PREFER_TEMPADDR", Const, 0, ""}, {"IPV6_RECVDSTOPTS", Const, 0, ""}, {"IPV6_RECVDSTPORT", Const, 3, ""}, {"IPV6_RECVERR", Const, 0, ""}, {"IPV6_RECVHOPLIMIT", Const, 0, ""}, {"IPV6_RECVHOPOPTS", Const, 0, ""}, {"IPV6_RECVPATHMTU", Const, 0, ""}, {"IPV6_RECVPKTINFO", Const, 0, ""}, {"IPV6_RECVRTHDR", Const, 0, ""}, {"IPV6_RECVTCLASS", Const, 0, ""}, {"IPV6_ROUTER_ALERT", Const, 0, ""}, {"IPV6_RTABLE", Const, 1, ""}, {"IPV6_RTHDR", Const, 0, ""}, {"IPV6_RTHDRDSTOPTS", Const, 0, ""}, {"IPV6_RTHDR_LOOSE", Const, 0, ""}, {"IPV6_RTHDR_STRICT", Const, 0, ""}, {"IPV6_RTHDR_TYPE_0", Const, 0, ""}, {"IPV6_RXDSTOPTS", Const, 0, ""}, {"IPV6_RXHOPOPTS", Const, 0, ""}, {"IPV6_SOCKOPT_RESERVED1", Const, 0, ""}, {"IPV6_TCLASS", Const, 0, ""}, {"IPV6_UNICAST_HOPS", Const, 0, ""}, {"IPV6_USE_MIN_MTU", Const, 0, ""}, {"IPV6_V6ONLY", Const, 0, ""}, {"IPV6_VERSION", Const, 0, ""}, {"IPV6_VERSION_MASK", Const, 0, ""}, {"IPV6_XFRM_POLICY", Const, 0, ""}, {"IP_ADD_MEMBERSHIP", Const, 0, ""}, {"IP_ADD_SOURCE_MEMBERSHIP", Const, 0, ""}, {"IP_AUTH_LEVEL", Const, 1, ""}, {"IP_BINDANY", Const, 0, ""}, {"IP_BLOCK_SOURCE", Const, 0, ""}, {"IP_BOUND_IF", Const, 0, ""}, {"IP_DEFAULT_MULTICAST_LOOP", Const, 0, ""}, {"IP_DEFAULT_MULTICAST_TTL", Const, 0, ""}, {"IP_DF", Const, 0, ""}, {"IP_DIVERTFL", Const, 3, ""}, {"IP_DONTFRAG", Const, 0, ""}, {"IP_DROP_MEMBERSHIP", Const, 0, ""}, {"IP_DROP_SOURCE_MEMBERSHIP", Const, 0, ""}, {"IP_DUMMYNET3", Const, 0, ""}, {"IP_DUMMYNET_CONFIGURE", Const, 0, ""}, {"IP_DUMMYNET_DEL", Const, 0, ""}, {"IP_DUMMYNET_FLUSH", Const, 0, ""}, {"IP_DUMMYNET_GET", Const, 0, ""}, {"IP_EF", Const, 1, ""}, {"IP_ERRORMTU", Const, 1, ""}, {"IP_ESP_NETWORK_LEVEL", Const, 1, ""}, {"IP_ESP_TRANS_LEVEL", Const, 1, ""}, {"IP_FAITH", Const, 0, ""}, {"IP_FREEBIND", Const, 0, ""}, {"IP_FW3", Const, 0, ""}, {"IP_FW_ADD", Const, 0, ""}, {"IP_FW_DEL", Const, 0, ""}, {"IP_FW_FLUSH", Const, 0, ""}, {"IP_FW_GET", Const, 0, ""}, {"IP_FW_NAT_CFG", Const, 0, ""}, {"IP_FW_NAT_DEL", Const, 0, ""}, {"IP_FW_NAT_GET_CONFIG", Const, 0, ""}, {"IP_FW_NAT_GET_LOG", Const, 0, ""}, {"IP_FW_RESETLOG", Const, 0, ""}, {"IP_FW_TABLE_ADD", Const, 0, ""}, {"IP_FW_TABLE_DEL", Const, 0, ""}, {"IP_FW_TABLE_FLUSH", Const, 0, ""}, {"IP_FW_TABLE_GETSIZE", Const, 0, ""}, {"IP_FW_TABLE_LIST", Const, 0, ""}, {"IP_FW_ZERO", Const, 0, ""}, {"IP_HDRINCL", Const, 0, ""}, {"IP_IPCOMP_LEVEL", Const, 1, ""}, {"IP_IPSECFLOWINFO", Const, 1, ""}, {"IP_IPSEC_LOCAL_AUTH", Const, 1, ""}, {"IP_IPSEC_LOCAL_CRED", Const, 1, ""}, {"IP_IPSEC_LOCAL_ID", Const, 1, ""}, {"IP_IPSEC_POLICY", Const, 0, ""}, {"IP_IPSEC_REMOTE_AUTH", Const, 1, ""}, {"IP_IPSEC_REMOTE_CRED", Const, 1, ""}, {"IP_IPSEC_REMOTE_ID", Const, 1, ""}, {"IP_MAXPACKET", Const, 0, ""}, {"IP_MAX_GROUP_SRC_FILTER", Const, 0, ""}, {"IP_MAX_MEMBERSHIPS", Const, 0, ""}, {"IP_MAX_SOCK_MUTE_FILTER", Const, 0, ""}, {"IP_MAX_SOCK_SRC_FILTER", Const, 0, ""}, {"IP_MAX_SOURCE_FILTER", Const, 0, ""}, {"IP_MF", Const, 0, ""}, {"IP_MINFRAGSIZE", Const, 1, ""}, {"IP_MINTTL", Const, 0, ""}, {"IP_MIN_MEMBERSHIPS", Const, 0, ""}, {"IP_MSFILTER", Const, 0, ""}, {"IP_MSS", Const, 0, ""}, {"IP_MTU", Const, 0, ""}, {"IP_MTU_DISCOVER", Const, 0, ""}, {"IP_MULTICAST_IF", Const, 0, ""}, {"IP_MULTICAST_IFINDEX", Const, 0, ""}, {"IP_MULTICAST_LOOP", Const, 0, ""}, {"IP_MULTICAST_TTL", Const, 0, ""}, {"IP_MULTICAST_VIF", Const, 0, ""}, {"IP_NAT__XXX", Const, 0, ""}, {"IP_OFFMASK", Const, 0, ""}, {"IP_OLD_FW_ADD", Const, 0, ""}, {"IP_OLD_FW_DEL", Const, 0, ""}, {"IP_OLD_FW_FLUSH", Const, 0, ""}, {"IP_OLD_FW_GET", Const, 0, ""}, {"IP_OLD_FW_RESETLOG", Const, 0, ""}, {"IP_OLD_FW_ZERO", Const, 0, ""}, {"IP_ONESBCAST", Const, 0, ""}, {"IP_OPTIONS", Const, 0, ""}, {"IP_ORIGDSTADDR", Const, 0, ""}, {"IP_PASSSEC", Const, 0, ""}, {"IP_PIPEX", Const, 1, ""}, {"IP_PKTINFO", Const, 0, ""}, {"IP_PKTOPTIONS", Const, 0, ""}, {"IP_PMTUDISC", Const, 0, ""}, {"IP_PMTUDISC_DO", Const, 0, ""}, {"IP_PMTUDISC_DONT", Const, 0, ""}, {"IP_PMTUDISC_PROBE", Const, 0, ""}, {"IP_PMTUDISC_WANT", Const, 0, ""}, {"IP_PORTRANGE", Const, 0, ""}, {"IP_PORTRANGE_DEFAULT", Const, 0, ""}, {"IP_PORTRANGE_HIGH", Const, 0, ""}, {"IP_PORTRANGE_LOW", Const, 0, ""}, {"IP_RECVDSTADDR", Const, 0, ""}, {"IP_RECVDSTPORT", Const, 1, ""}, {"IP_RECVERR", Const, 0, ""}, {"IP_RECVIF", Const, 0, ""}, {"IP_RECVOPTS", Const, 0, ""}, {"IP_RECVORIGDSTADDR", Const, 0, ""}, {"IP_RECVPKTINFO", Const, 0, ""}, {"IP_RECVRETOPTS", Const, 0, ""}, {"IP_RECVRTABLE", Const, 1, ""}, {"IP_RECVTOS", Const, 0, ""}, {"IP_RECVTTL", Const, 0, ""}, {"IP_RETOPTS", Const, 0, ""}, {"IP_RF", Const, 0, ""}, {"IP_ROUTER_ALERT", Const, 0, ""}, {"IP_RSVP_OFF", Const, 0, ""}, {"IP_RSVP_ON", Const, 0, ""}, {"IP_RSVP_VIF_OFF", Const, 0, ""}, {"IP_RSVP_VIF_ON", Const, 0, ""}, {"IP_RTABLE", Const, 1, ""}, {"IP_SENDSRCADDR", Const, 0, ""}, {"IP_STRIPHDR", Const, 0, ""}, {"IP_TOS", Const, 0, ""}, {"IP_TRAFFIC_MGT_BACKGROUND", Const, 0, ""}, {"IP_TRANSPARENT", Const, 0, ""}, {"IP_TTL", Const, 0, ""}, {"IP_UNBLOCK_SOURCE", Const, 0, ""}, {"IP_XFRM_POLICY", Const, 0, ""}, {"IPv6MTUInfo", Type, 2, ""}, {"IPv6MTUInfo.Addr", Field, 2, ""}, {"IPv6MTUInfo.Mtu", Field, 2, ""}, {"IPv6Mreq", Type, 0, ""}, {"IPv6Mreq.Interface", Field, 0, ""}, {"IPv6Mreq.Multiaddr", Field, 0, ""}, {"ISIG", Const, 0, ""}, {"ISTRIP", Const, 0, ""}, {"IUCLC", Const, 0, ""}, {"IUTF8", Const, 0, ""}, {"IXANY", Const, 0, ""}, {"IXOFF", Const, 0, ""}, {"IXON", Const, 0, ""}, {"IfAddrmsg", Type, 0, ""}, {"IfAddrmsg.Family", Field, 0, ""}, {"IfAddrmsg.Flags", Field, 0, ""}, {"IfAddrmsg.Index", Field, 0, ""}, {"IfAddrmsg.Prefixlen", Field, 0, ""}, {"IfAddrmsg.Scope", Field, 0, ""}, {"IfAnnounceMsghdr", Type, 1, ""}, {"IfAnnounceMsghdr.Hdrlen", Field, 2, ""}, {"IfAnnounceMsghdr.Index", Field, 1, ""}, {"IfAnnounceMsghdr.Msglen", Field, 1, ""}, {"IfAnnounceMsghdr.Name", Field, 1, ""}, {"IfAnnounceMsghdr.Type", Field, 1, ""}, {"IfAnnounceMsghdr.Version", Field, 1, ""}, {"IfAnnounceMsghdr.What", Field, 1, ""}, {"IfData", Type, 0, ""}, {"IfData.Addrlen", Field, 0, ""}, {"IfData.Baudrate", Field, 0, ""}, {"IfData.Capabilities", Field, 2, ""}, {"IfData.Collisions", Field, 0, ""}, {"IfData.Datalen", Field, 0, ""}, {"IfData.Epoch", Field, 0, ""}, {"IfData.Hdrlen", Field, 0, ""}, {"IfData.Hwassist", Field, 0, ""}, {"IfData.Ibytes", Field, 0, ""}, {"IfData.Ierrors", Field, 0, ""}, {"IfData.Imcasts", Field, 0, ""}, {"IfData.Ipackets", Field, 0, ""}, {"IfData.Iqdrops", Field, 0, ""}, {"IfData.Lastchange", Field, 0, ""}, {"IfData.Link_state", Field, 0, ""}, {"IfData.Mclpool", Field, 2, ""}, {"IfData.Metric", Field, 0, ""}, {"IfData.Mtu", Field, 0, ""}, {"IfData.Noproto", Field, 0, ""}, {"IfData.Obytes", Field, 0, ""}, {"IfData.Oerrors", Field, 0, ""}, {"IfData.Omcasts", Field, 0, ""}, {"IfData.Opackets", Field, 0, ""}, {"IfData.Pad", Field, 2, ""}, {"IfData.Pad_cgo_0", Field, 2, ""}, {"IfData.Pad_cgo_1", Field, 2, ""}, {"IfData.Physical", Field, 0, ""}, {"IfData.Recvquota", Field, 0, ""}, {"IfData.Recvtiming", Field, 0, ""}, {"IfData.Reserved1", Field, 0, ""}, {"IfData.Reserved2", Field, 0, ""}, {"IfData.Spare_char1", Field, 0, ""}, {"IfData.Spare_char2", Field, 0, ""}, {"IfData.Type", Field, 0, ""}, {"IfData.Typelen", Field, 0, ""}, {"IfData.Unused1", Field, 0, ""}, {"IfData.Unused2", Field, 0, ""}, {"IfData.Xmitquota", Field, 0, ""}, {"IfData.Xmittiming", Field, 0, ""}, {"IfInfomsg", Type, 0, ""}, {"IfInfomsg.Change", Field, 0, ""}, {"IfInfomsg.Family", Field, 0, ""}, {"IfInfomsg.Flags", Field, 0, ""}, {"IfInfomsg.Index", Field, 0, ""}, {"IfInfomsg.Type", Field, 0, ""}, {"IfInfomsg.X__ifi_pad", Field, 0, ""}, {"IfMsghdr", Type, 0, ""}, {"IfMsghdr.Addrs", Field, 0, ""}, {"IfMsghdr.Data", Field, 0, ""}, {"IfMsghdr.Flags", Field, 0, ""}, {"IfMsghdr.Hdrlen", Field, 2, ""}, {"IfMsghdr.Index", Field, 0, ""}, {"IfMsghdr.Msglen", Field, 0, ""}, {"IfMsghdr.Pad1", Field, 2, ""}, {"IfMsghdr.Pad2", Field, 2, ""}, {"IfMsghdr.Pad_cgo_0", Field, 0, ""}, {"IfMsghdr.Pad_cgo_1", Field, 2, ""}, {"IfMsghdr.Tableid", Field, 2, ""}, {"IfMsghdr.Type", Field, 0, ""}, {"IfMsghdr.Version", Field, 0, ""}, {"IfMsghdr.Xflags", Field, 2, ""}, {"IfaMsghdr", Type, 0, ""}, {"IfaMsghdr.Addrs", Field, 0, ""}, {"IfaMsghdr.Flags", Field, 0, ""}, {"IfaMsghdr.Hdrlen", Field, 2, ""}, {"IfaMsghdr.Index", Field, 0, ""}, {"IfaMsghdr.Metric", Field, 0, ""}, {"IfaMsghdr.Msglen", Field, 0, ""}, {"IfaMsghdr.Pad1", Field, 2, ""}, {"IfaMsghdr.Pad2", Field, 2, ""}, {"IfaMsghdr.Pad_cgo_0", Field, 0, ""}, {"IfaMsghdr.Tableid", Field, 2, ""}, {"IfaMsghdr.Type", Field, 0, ""}, {"IfaMsghdr.Version", Field, 0, ""}, {"IfmaMsghdr", Type, 0, ""}, {"IfmaMsghdr.Addrs", Field, 0, ""}, {"IfmaMsghdr.Flags", Field, 0, ""}, {"IfmaMsghdr.Index", Field, 0, ""}, {"IfmaMsghdr.Msglen", Field, 0, ""}, {"IfmaMsghdr.Pad_cgo_0", Field, 0, ""}, {"IfmaMsghdr.Type", Field, 0, ""}, {"IfmaMsghdr.Version", Field, 0, ""}, {"IfmaMsghdr2", Type, 0, ""}, {"IfmaMsghdr2.Addrs", Field, 0, ""}, {"IfmaMsghdr2.Flags", Field, 0, ""}, {"IfmaMsghdr2.Index", Field, 0, ""}, {"IfmaMsghdr2.Msglen", Field, 0, ""}, {"IfmaMsghdr2.Pad_cgo_0", Field, 0, ""}, {"IfmaMsghdr2.Refcount", Field, 0, ""}, {"IfmaMsghdr2.Type", Field, 0, ""}, {"IfmaMsghdr2.Version", Field, 0, ""}, {"ImplementsGetwd", Const, 0, ""}, {"Inet4Pktinfo", Type, 0, ""}, {"Inet4Pktinfo.Addr", Field, 0, ""}, {"Inet4Pktinfo.Ifindex", Field, 0, ""}, {"Inet4Pktinfo.Spec_dst", Field, 0, ""}, {"Inet6Pktinfo", Type, 0, ""}, {"Inet6Pktinfo.Addr", Field, 0, ""}, {"Inet6Pktinfo.Ifindex", Field, 0, ""}, {"InotifyAddWatch", Func, 0, "func(fd int, pathname string, mask uint32) (watchdesc int, err error)"}, {"InotifyEvent", Type, 0, ""}, {"InotifyEvent.Cookie", Field, 0, ""}, {"InotifyEvent.Len", Field, 0, ""}, {"InotifyEvent.Mask", Field, 0, ""}, {"InotifyEvent.Name", Field, 0, ""}, {"InotifyEvent.Wd", Field, 0, ""}, {"InotifyInit", Func, 0, "func() (fd int, err error)"}, {"InotifyInit1", Func, 0, "func(flags int) (fd int, err error)"}, {"InotifyRmWatch", Func, 0, "func(fd int, watchdesc uint32) (success int, err error)"}, {"InterfaceAddrMessage", Type, 0, ""}, {"InterfaceAddrMessage.Data", Field, 0, ""}, {"InterfaceAddrMessage.Header", Field, 0, ""}, {"InterfaceAnnounceMessage", Type, 1, ""}, {"InterfaceAnnounceMessage.Header", Field, 1, ""}, {"InterfaceInfo", Type, 0, ""}, {"InterfaceInfo.Address", Field, 0, ""}, {"InterfaceInfo.BroadcastAddress", Field, 0, ""}, {"InterfaceInfo.Flags", Field, 0, ""}, {"InterfaceInfo.Netmask", Field, 0, ""}, {"InterfaceMessage", Type, 0, ""}, {"InterfaceMessage.Data", Field, 0, ""}, {"InterfaceMessage.Header", Field, 0, ""}, {"InterfaceMulticastAddrMessage", Type, 0, ""}, {"InterfaceMulticastAddrMessage.Data", Field, 0, ""}, {"InterfaceMulticastAddrMessage.Header", Field, 0, ""}, {"InvalidHandle", Const, 0, ""}, {"Ioperm", Func, 0, "func(from int, num int, on int) (err error)"}, {"Iopl", Func, 0, "func(level int) (err error)"}, {"Iovec", Type, 0, ""}, {"Iovec.Base", Field, 0, ""}, {"Iovec.Len", Field, 0, ""}, {"IpAdapterInfo", Type, 0, ""}, {"IpAdapterInfo.AdapterName", Field, 0, ""}, {"IpAdapterInfo.Address", Field, 0, ""}, {"IpAdapterInfo.AddressLength", Field, 0, ""}, {"IpAdapterInfo.ComboIndex", Field, 0, ""}, {"IpAdapterInfo.CurrentIpAddress", Field, 0, ""}, {"IpAdapterInfo.Description", Field, 0, ""}, {"IpAdapterInfo.DhcpEnabled", Field, 0, ""}, {"IpAdapterInfo.DhcpServer", Field, 0, ""}, {"IpAdapterInfo.GatewayList", Field, 0, ""}, {"IpAdapterInfo.HaveWins", Field, 0, ""}, {"IpAdapterInfo.Index", Field, 0, ""}, {"IpAdapterInfo.IpAddressList", Field, 0, ""}, {"IpAdapterInfo.LeaseExpires", Field, 0, ""}, {"IpAdapterInfo.LeaseObtained", Field, 0, ""}, {"IpAdapterInfo.Next", Field, 0, ""}, {"IpAdapterInfo.PrimaryWinsServer", Field, 0, ""}, {"IpAdapterInfo.SecondaryWinsServer", Field, 0, ""}, {"IpAdapterInfo.Type", Field, 0, ""}, {"IpAddrString", Type, 0, ""}, {"IpAddrString.Context", Field, 0, ""}, {"IpAddrString.IpAddress", Field, 0, ""}, {"IpAddrString.IpMask", Field, 0, ""}, {"IpAddrString.Next", Field, 0, ""}, {"IpAddressString", Type, 0, ""}, {"IpAddressString.String", Field, 0, ""}, {"IpMaskString", Type, 0, ""}, {"IpMaskString.String", Field, 2, ""}, {"Issetugid", Func, 0, ""}, {"KEY_ALL_ACCESS", Const, 0, ""}, {"KEY_CREATE_LINK", Const, 0, ""}, {"KEY_CREATE_SUB_KEY", Const, 0, ""}, {"KEY_ENUMERATE_SUB_KEYS", Const, 0, ""}, {"KEY_EXECUTE", Const, 0, ""}, {"KEY_NOTIFY", Const, 0, ""}, {"KEY_QUERY_VALUE", Const, 0, ""}, {"KEY_READ", Const, 0, ""}, {"KEY_SET_VALUE", Const, 0, ""}, {"KEY_WOW64_32KEY", Const, 0, ""}, {"KEY_WOW64_64KEY", Const, 0, ""}, {"KEY_WRITE", Const, 0, ""}, {"Kevent", Func, 0, ""}, {"Kevent_t", Type, 0, ""}, {"Kevent_t.Data", Field, 0, ""}, {"Kevent_t.Fflags", Field, 0, ""}, {"Kevent_t.Filter", Field, 0, ""}, {"Kevent_t.Flags", Field, 0, ""}, {"Kevent_t.Ident", Field, 0, ""}, {"Kevent_t.Pad_cgo_0", Field, 2, ""}, {"Kevent_t.Udata", Field, 0, ""}, {"Kill", Func, 0, "func(pid int, sig Signal) (err error)"}, {"Klogctl", Func, 0, "func(typ int, buf []byte) (n int, err error)"}, {"Kqueue", Func, 0, ""}, {"LANG_ENGLISH", Const, 0, ""}, {"LAYERED_PROTOCOL", Const, 2, ""}, {"LCNT_OVERLOAD_FLUSH", Const, 1, ""}, {"LINUX_REBOOT_CMD_CAD_OFF", Const, 0, ""}, {"LINUX_REBOOT_CMD_CAD_ON", Const, 0, ""}, {"LINUX_REBOOT_CMD_HALT", Const, 0, ""}, {"LINUX_REBOOT_CMD_KEXEC", Const, 0, ""}, {"LINUX_REBOOT_CMD_POWER_OFF", Const, 0, ""}, {"LINUX_REBOOT_CMD_RESTART", Const, 0, ""}, {"LINUX_REBOOT_CMD_RESTART2", Const, 0, ""}, {"LINUX_REBOOT_CMD_SW_SUSPEND", Const, 0, ""}, {"LINUX_REBOOT_MAGIC1", Const, 0, ""}, {"LINUX_REBOOT_MAGIC2", Const, 0, ""}, {"LOCK_EX", Const, 0, ""}, {"LOCK_NB", Const, 0, ""}, {"LOCK_SH", Const, 0, ""}, {"LOCK_UN", Const, 0, ""}, {"LazyDLL", Type, 0, ""}, {"LazyDLL.Name", Field, 0, ""}, {"LazyProc", Type, 0, ""}, {"LazyProc.Name", Field, 0, ""}, {"Lchown", Func, 0, "func(path string, uid int, gid int) (err error)"}, {"Linger", Type, 0, ""}, {"Linger.Linger", Field, 0, ""}, {"Linger.Onoff", Field, 0, ""}, {"Link", Func, 0, "func(oldpath string, newpath string) (err error)"}, {"Listen", Func, 0, "func(s int, n int) (err error)"}, {"Listxattr", Func, 1, "func(path string, dest []byte) (sz int, err error)"}, {"LoadCancelIoEx", Func, 1, ""}, {"LoadConnectEx", Func, 1, ""}, {"LoadCreateSymbolicLink", Func, 4, ""}, {"LoadDLL", Func, 0, ""}, {"LoadGetAddrInfo", Func, 1, ""}, {"LoadLibrary", Func, 0, ""}, {"LoadSetFileCompletionNotificationModes", Func, 2, ""}, {"LocalFree", Func, 0, ""}, {"Log2phys_t", Type, 0, ""}, {"Log2phys_t.Contigbytes", Field, 0, ""}, {"Log2phys_t.Devoffset", Field, 0, ""}, {"Log2phys_t.Flags", Field, 0, ""}, {"LookupAccountName", Func, 0, ""}, {"LookupAccountSid", Func, 0, ""}, {"LookupSID", Func, 0, ""}, {"LsfJump", Func, 0, "func(code int, k int, jt int, jf int) *SockFilter"}, {"LsfSocket", Func, 0, "func(ifindex int, proto int) (int, error)"}, {"LsfStmt", Func, 0, "func(code int, k int) *SockFilter"}, {"Lstat", Func, 0, "func(path string, stat *Stat_t) (err error)"}, {"MADV_AUTOSYNC", Const, 1, ""}, {"MADV_CAN_REUSE", Const, 0, ""}, {"MADV_CORE", Const, 1, ""}, {"MADV_DOFORK", Const, 0, ""}, {"MADV_DONTFORK", Const, 0, ""}, {"MADV_DONTNEED", Const, 0, ""}, {"MADV_FREE", Const, 0, ""}, {"MADV_FREE_REUSABLE", Const, 0, ""}, {"MADV_FREE_REUSE", Const, 0, ""}, {"MADV_HUGEPAGE", Const, 0, ""}, {"MADV_HWPOISON", Const, 0, ""}, {"MADV_MERGEABLE", Const, 0, ""}, {"MADV_NOCORE", Const, 1, ""}, {"MADV_NOHUGEPAGE", Const, 0, ""}, {"MADV_NORMAL", Const, 0, ""}, {"MADV_NOSYNC", Const, 1, ""}, {"MADV_PROTECT", Const, 1, ""}, {"MADV_RANDOM", Const, 0, ""}, {"MADV_REMOVE", Const, 0, ""}, {"MADV_SEQUENTIAL", Const, 0, ""}, {"MADV_SPACEAVAIL", Const, 3, ""}, {"MADV_UNMERGEABLE", Const, 0, ""}, {"MADV_WILLNEED", Const, 0, ""}, {"MADV_ZERO_WIRED_PAGES", Const, 0, ""}, {"MAP_32BIT", Const, 0, ""}, {"MAP_ALIGNED_SUPER", Const, 3, ""}, {"MAP_ALIGNMENT_16MB", Const, 3, ""}, {"MAP_ALIGNMENT_1TB", Const, 3, ""}, {"MAP_ALIGNMENT_256TB", Const, 3, ""}, {"MAP_ALIGNMENT_4GB", Const, 3, ""}, {"MAP_ALIGNMENT_64KB", Const, 3, ""}, {"MAP_ALIGNMENT_64PB", Const, 3, ""}, {"MAP_ALIGNMENT_MASK", Const, 3, ""}, {"MAP_ALIGNMENT_SHIFT", Const, 3, ""}, {"MAP_ANON", Const, 0, ""}, {"MAP_ANONYMOUS", Const, 0, ""}, {"MAP_COPY", Const, 0, ""}, {"MAP_DENYWRITE", Const, 0, ""}, {"MAP_EXECUTABLE", Const, 0, ""}, {"MAP_FILE", Const, 0, ""}, {"MAP_FIXED", Const, 0, ""}, {"MAP_FLAGMASK", Const, 3, ""}, {"MAP_GROWSDOWN", Const, 0, ""}, {"MAP_HASSEMAPHORE", Const, 0, ""}, {"MAP_HUGETLB", Const, 0, ""}, {"MAP_INHERIT", Const, 3, ""}, {"MAP_INHERIT_COPY", Const, 3, ""}, {"MAP_INHERIT_DEFAULT", Const, 3, ""}, {"MAP_INHERIT_DONATE_COPY", Const, 3, ""}, {"MAP_INHERIT_NONE", Const, 3, ""}, {"MAP_INHERIT_SHARE", Const, 3, ""}, {"MAP_JIT", Const, 0, ""}, {"MAP_LOCKED", Const, 0, ""}, {"MAP_NOCACHE", Const, 0, ""}, {"MAP_NOCORE", Const, 1, ""}, {"MAP_NOEXTEND", Const, 0, ""}, {"MAP_NONBLOCK", Const, 0, ""}, {"MAP_NORESERVE", Const, 0, ""}, {"MAP_NOSYNC", Const, 1, ""}, {"MAP_POPULATE", Const, 0, ""}, {"MAP_PREFAULT_READ", Const, 1, ""}, {"MAP_PRIVATE", Const, 0, ""}, {"MAP_RENAME", Const, 0, ""}, {"MAP_RESERVED0080", Const, 0, ""}, {"MAP_RESERVED0100", Const, 1, ""}, {"MAP_SHARED", Const, 0, ""}, {"MAP_STACK", Const, 0, ""}, {"MAP_TRYFIXED", Const, 3, ""}, {"MAP_TYPE", Const, 0, ""}, {"MAP_WIRED", Const, 3, ""}, {"MAXIMUM_REPARSE_DATA_BUFFER_SIZE", Const, 4, ""}, {"MAXLEN_IFDESCR", Const, 0, ""}, {"MAXLEN_PHYSADDR", Const, 0, ""}, {"MAX_ADAPTER_ADDRESS_LENGTH", Const, 0, ""}, {"MAX_ADAPTER_DESCRIPTION_LENGTH", Const, 0, ""}, {"MAX_ADAPTER_NAME_LENGTH", Const, 0, ""}, {"MAX_COMPUTERNAME_LENGTH", Const, 0, ""}, {"MAX_INTERFACE_NAME_LEN", Const, 0, ""}, {"MAX_LONG_PATH", Const, 0, ""}, {"MAX_PATH", Const, 0, ""}, {"MAX_PROTOCOL_CHAIN", Const, 2, ""}, {"MCL_CURRENT", Const, 0, ""}, {"MCL_FUTURE", Const, 0, ""}, {"MNT_DETACH", Const, 0, ""}, {"MNT_EXPIRE", Const, 0, ""}, {"MNT_FORCE", Const, 0, ""}, {"MSG_BCAST", Const, 1, ""}, {"MSG_CMSG_CLOEXEC", Const, 0, ""}, {"MSG_COMPAT", Const, 0, ""}, {"MSG_CONFIRM", Const, 0, ""}, {"MSG_CONTROLMBUF", Const, 1, ""}, {"MSG_CTRUNC", Const, 0, ""}, {"MSG_DONTROUTE", Const, 0, ""}, {"MSG_DONTWAIT", Const, 0, ""}, {"MSG_EOF", Const, 0, ""}, {"MSG_EOR", Const, 0, ""}, {"MSG_ERRQUEUE", Const, 0, ""}, {"MSG_FASTOPEN", Const, 1, ""}, {"MSG_FIN", Const, 0, ""}, {"MSG_FLUSH", Const, 0, ""}, {"MSG_HAVEMORE", Const, 0, ""}, {"MSG_HOLD", Const, 0, ""}, {"MSG_IOVUSRSPACE", Const, 1, ""}, {"MSG_LENUSRSPACE", Const, 1, ""}, {"MSG_MCAST", Const, 1, ""}, {"MSG_MORE", Const, 0, ""}, {"MSG_NAMEMBUF", Const, 1, ""}, {"MSG_NBIO", Const, 0, ""}, {"MSG_NEEDSA", Const, 0, ""}, {"MSG_NOSIGNAL", Const, 0, ""}, {"MSG_NOTIFICATION", Const, 0, ""}, {"MSG_OOB", Const, 0, ""}, {"MSG_PEEK", Const, 0, ""}, {"MSG_PROXY", Const, 0, ""}, {"MSG_RCVMORE", Const, 0, ""}, {"MSG_RST", Const, 0, ""}, {"MSG_SEND", Const, 0, ""}, {"MSG_SYN", Const, 0, ""}, {"MSG_TRUNC", Const, 0, ""}, {"MSG_TRYHARD", Const, 0, ""}, {"MSG_USERFLAGS", Const, 1, ""}, {"MSG_WAITALL", Const, 0, ""}, {"MSG_WAITFORONE", Const, 0, ""}, {"MSG_WAITSTREAM", Const, 0, ""}, {"MS_ACTIVE", Const, 0, ""}, {"MS_ASYNC", Const, 0, ""}, {"MS_BIND", Const, 0, ""}, {"MS_DEACTIVATE", Const, 0, ""}, {"MS_DIRSYNC", Const, 0, ""}, {"MS_INVALIDATE", Const, 0, ""}, {"MS_I_VERSION", Const, 0, ""}, {"MS_KERNMOUNT", Const, 0, ""}, {"MS_KILLPAGES", Const, 0, ""}, {"MS_MANDLOCK", Const, 0, ""}, {"MS_MGC_MSK", Const, 0, ""}, {"MS_MGC_VAL", Const, 0, ""}, {"MS_MOVE", Const, 0, ""}, {"MS_NOATIME", Const, 0, ""}, {"MS_NODEV", Const, 0, ""}, {"MS_NODIRATIME", Const, 0, ""}, {"MS_NOEXEC", Const, 0, ""}, {"MS_NOSUID", Const, 0, ""}, {"MS_NOUSER", Const, 0, ""}, {"MS_POSIXACL", Const, 0, ""}, {"MS_PRIVATE", Const, 0, ""}, {"MS_RDONLY", Const, 0, ""}, {"MS_REC", Const, 0, ""}, {"MS_RELATIME", Const, 0, ""}, {"MS_REMOUNT", Const, 0, ""}, {"MS_RMT_MASK", Const, 0, ""}, {"MS_SHARED", Const, 0, ""}, {"MS_SILENT", Const, 0, ""}, {"MS_SLAVE", Const, 0, ""}, {"MS_STRICTATIME", Const, 0, ""}, {"MS_SYNC", Const, 0, ""}, {"MS_SYNCHRONOUS", Const, 0, ""}, {"MS_UNBINDABLE", Const, 0, ""}, {"Madvise", Func, 0, "func(b []byte, advice int) (err error)"}, {"MapViewOfFile", Func, 0, ""}, {"MaxTokenInfoClass", Const, 0, ""}, {"Mclpool", Type, 2, ""}, {"Mclpool.Alive", Field, 2, ""}, {"Mclpool.Cwm", Field, 2, ""}, {"Mclpool.Grown", Field, 2, ""}, {"Mclpool.Hwm", Field, 2, ""}, {"Mclpool.Lwm", Field, 2, ""}, {"MibIfRow", Type, 0, ""}, {"MibIfRow.AdminStatus", Field, 0, ""}, {"MibIfRow.Descr", Field, 0, ""}, {"MibIfRow.DescrLen", Field, 0, ""}, {"MibIfRow.InDiscards", Field, 0, ""}, {"MibIfRow.InErrors", Field, 0, ""}, {"MibIfRow.InNUcastPkts", Field, 0, ""}, {"MibIfRow.InOctets", Field, 0, ""}, {"MibIfRow.InUcastPkts", Field, 0, ""}, {"MibIfRow.InUnknownProtos", Field, 0, ""}, {"MibIfRow.Index", Field, 0, ""}, {"MibIfRow.LastChange", Field, 0, ""}, {"MibIfRow.Mtu", Field, 0, ""}, {"MibIfRow.Name", Field, 0, ""}, {"MibIfRow.OperStatus", Field, 0, ""}, {"MibIfRow.OutDiscards", Field, 0, ""}, {"MibIfRow.OutErrors", Field, 0, ""}, {"MibIfRow.OutNUcastPkts", Field, 0, ""}, {"MibIfRow.OutOctets", Field, 0, ""}, {"MibIfRow.OutQLen", Field, 0, ""}, {"MibIfRow.OutUcastPkts", Field, 0, ""}, {"MibIfRow.PhysAddr", Field, 0, ""}, {"MibIfRow.PhysAddrLen", Field, 0, ""}, {"MibIfRow.Speed", Field, 0, ""}, {"MibIfRow.Type", Field, 0, ""}, {"Mkdir", Func, 0, "func(path string, mode uint32) (err error)"}, {"Mkdirat", Func, 0, "func(dirfd int, path string, mode uint32) (err error)"}, {"Mkfifo", Func, 0, "func(path string, mode uint32) (err error)"}, {"Mknod", Func, 0, "func(path string, mode uint32, dev int) (err error)"}, {"Mknodat", Func, 0, "func(dirfd int, path string, mode uint32, dev int) (err error)"}, {"Mlock", Func, 0, "func(b []byte) (err error)"}, {"Mlockall", Func, 0, "func(flags int) (err error)"}, {"Mmap", Func, 0, "func(fd int, offset int64, length int, prot int, flags int) (data []byte, err error)"}, {"Mount", Func, 0, "func(source string, target string, fstype string, flags uintptr, data string) (err error)"}, {"MoveFile", Func, 0, ""}, {"Mprotect", Func, 0, "func(b []byte, prot int) (err error)"}, {"Msghdr", Type, 0, ""}, {"Msghdr.Control", Field, 0, ""}, {"Msghdr.Controllen", Field, 0, ""}, {"Msghdr.Flags", Field, 0, ""}, {"Msghdr.Iov", Field, 0, ""}, {"Msghdr.Iovlen", Field, 0, ""}, {"Msghdr.Name", Field, 0, ""}, {"Msghdr.Namelen", Field, 0, ""}, {"Msghdr.Pad_cgo_0", Field, 0, ""}, {"Msghdr.Pad_cgo_1", Field, 0, ""}, {"Munlock", Func, 0, "func(b []byte) (err error)"}, {"Munlockall", Func, 0, "func() (err error)"}, {"Munmap", Func, 0, "func(b []byte) (err error)"}, {"MustLoadDLL", Func, 0, ""}, {"NAME_MAX", Const, 0, ""}, {"NETLINK_ADD_MEMBERSHIP", Const, 0, ""}, {"NETLINK_AUDIT", Const, 0, ""}, {"NETLINK_BROADCAST_ERROR", Const, 0, ""}, {"NETLINK_CONNECTOR", Const, 0, ""}, {"NETLINK_DNRTMSG", Const, 0, ""}, {"NETLINK_DROP_MEMBERSHIP", Const, 0, ""}, {"NETLINK_ECRYPTFS", Const, 0, ""}, {"NETLINK_FIB_LOOKUP", Const, 0, ""}, {"NETLINK_FIREWALL", Const, 0, ""}, {"NETLINK_GENERIC", Const, 0, ""}, {"NETLINK_INET_DIAG", Const, 0, ""}, {"NETLINK_IP6_FW", Const, 0, ""}, {"NETLINK_ISCSI", Const, 0, ""}, {"NETLINK_KOBJECT_UEVENT", Const, 0, ""}, {"NETLINK_NETFILTER", Const, 0, ""}, {"NETLINK_NFLOG", Const, 0, ""}, {"NETLINK_NO_ENOBUFS", Const, 0, ""}, {"NETLINK_PKTINFO", Const, 0, ""}, {"NETLINK_RDMA", Const, 0, ""}, {"NETLINK_ROUTE", Const, 0, ""}, {"NETLINK_SCSITRANSPORT", Const, 0, ""}, {"NETLINK_SELINUX", Const, 0, ""}, {"NETLINK_UNUSED", Const, 0, ""}, {"NETLINK_USERSOCK", Const, 0, ""}, {"NETLINK_XFRM", Const, 0, ""}, {"NET_RT_DUMP", Const, 0, ""}, {"NET_RT_DUMP2", Const, 0, ""}, {"NET_RT_FLAGS", Const, 0, ""}, {"NET_RT_IFLIST", Const, 0, ""}, {"NET_RT_IFLIST2", Const, 0, ""}, {"NET_RT_IFLISTL", Const, 1, ""}, {"NET_RT_IFMALIST", Const, 0, ""}, {"NET_RT_MAXID", Const, 0, ""}, {"NET_RT_OIFLIST", Const, 1, ""}, {"NET_RT_OOIFLIST", Const, 1, ""}, {"NET_RT_STAT", Const, 0, ""}, {"NET_RT_STATS", Const, 1, ""}, {"NET_RT_TABLE", Const, 1, ""}, {"NET_RT_TRASH", Const, 0, ""}, {"NLA_ALIGNTO", Const, 0, ""}, {"NLA_F_NESTED", Const, 0, ""}, {"NLA_F_NET_BYTEORDER", Const, 0, ""}, {"NLA_HDRLEN", Const, 0, ""}, {"NLMSG_ALIGNTO", Const, 0, ""}, {"NLMSG_DONE", Const, 0, ""}, {"NLMSG_ERROR", Const, 0, ""}, {"NLMSG_HDRLEN", Const, 0, ""}, {"NLMSG_MIN_TYPE", Const, 0, ""}, {"NLMSG_NOOP", Const, 0, ""}, {"NLMSG_OVERRUN", Const, 0, ""}, {"NLM_F_ACK", Const, 0, ""}, {"NLM_F_APPEND", Const, 0, ""}, {"NLM_F_ATOMIC", Const, 0, ""}, {"NLM_F_CREATE", Const, 0, ""}, {"NLM_F_DUMP", Const, 0, ""}, {"NLM_F_ECHO", Const, 0, ""}, {"NLM_F_EXCL", Const, 0, ""}, {"NLM_F_MATCH", Const, 0, ""}, {"NLM_F_MULTI", Const, 0, ""}, {"NLM_F_REPLACE", Const, 0, ""}, {"NLM_F_REQUEST", Const, 0, ""}, {"NLM_F_ROOT", Const, 0, ""}, {"NOFLSH", Const, 0, ""}, {"NOTE_ABSOLUTE", Const, 0, ""}, {"NOTE_ATTRIB", Const, 0, ""}, {"NOTE_BACKGROUND", Const, 16, ""}, {"NOTE_CHILD", Const, 0, ""}, {"NOTE_CRITICAL", Const, 16, ""}, {"NOTE_DELETE", Const, 0, ""}, {"NOTE_EOF", Const, 1, ""}, {"NOTE_EXEC", Const, 0, ""}, {"NOTE_EXIT", Const, 0, ""}, {"NOTE_EXITSTATUS", Const, 0, ""}, {"NOTE_EXIT_CSERROR", Const, 16, ""}, {"NOTE_EXIT_DECRYPTFAIL", Const, 16, ""}, {"NOTE_EXIT_DETAIL", Const, 16, ""}, {"NOTE_EXIT_DETAIL_MASK", Const, 16, ""}, {"NOTE_EXIT_MEMORY", Const, 16, ""}, {"NOTE_EXIT_REPARENTED", Const, 16, ""}, {"NOTE_EXTEND", Const, 0, ""}, {"NOTE_FFAND", Const, 0, ""}, {"NOTE_FFCOPY", Const, 0, ""}, {"NOTE_FFCTRLMASK", Const, 0, ""}, {"NOTE_FFLAGSMASK", Const, 0, ""}, {"NOTE_FFNOP", Const, 0, ""}, {"NOTE_FFOR", Const, 0, ""}, {"NOTE_FORK", Const, 0, ""}, {"NOTE_LEEWAY", Const, 16, ""}, {"NOTE_LINK", Const, 0, ""}, {"NOTE_LOWAT", Const, 0, ""}, {"NOTE_NONE", Const, 0, ""}, {"NOTE_NSECONDS", Const, 0, ""}, {"NOTE_PCTRLMASK", Const, 0, ""}, {"NOTE_PDATAMASK", Const, 0, ""}, {"NOTE_REAP", Const, 0, ""}, {"NOTE_RENAME", Const, 0, ""}, {"NOTE_RESOURCEEND", Const, 0, ""}, {"NOTE_REVOKE", Const, 0, ""}, {"NOTE_SECONDS", Const, 0, ""}, {"NOTE_SIGNAL", Const, 0, ""}, {"NOTE_TRACK", Const, 0, ""}, {"NOTE_TRACKERR", Const, 0, ""}, {"NOTE_TRIGGER", Const, 0, ""}, {"NOTE_TRUNCATE", Const, 1, ""}, {"NOTE_USECONDS", Const, 0, ""}, {"NOTE_VM_ERROR", Const, 0, ""}, {"NOTE_VM_PRESSURE", Const, 0, ""}, {"NOTE_VM_PRESSURE_SUDDEN_TERMINATE", Const, 0, ""}, {"NOTE_VM_PRESSURE_TERMINATE", Const, 0, ""}, {"NOTE_WRITE", Const, 0, ""}, {"NameCanonical", Const, 0, ""}, {"NameCanonicalEx", Const, 0, ""}, {"NameDisplay", Const, 0, ""}, {"NameDnsDomain", Const, 0, ""}, {"NameFullyQualifiedDN", Const, 0, ""}, {"NameSamCompatible", Const, 0, ""}, {"NameServicePrincipal", Const, 0, ""}, {"NameUniqueId", Const, 0, ""}, {"NameUnknown", Const, 0, ""}, {"NameUserPrincipal", Const, 0, ""}, {"Nanosleep", Func, 0, "func(time *Timespec, leftover *Timespec) (err error)"}, {"NetApiBufferFree", Func, 0, ""}, {"NetGetJoinInformation", Func, 2, ""}, {"NetSetupDomainName", Const, 2, ""}, {"NetSetupUnjoined", Const, 2, ""}, {"NetSetupUnknownStatus", Const, 2, ""}, {"NetSetupWorkgroupName", Const, 2, ""}, {"NetUserGetInfo", Func, 0, ""}, {"NetlinkMessage", Type, 0, ""}, {"NetlinkMessage.Data", Field, 0, ""}, {"NetlinkMessage.Header", Field, 0, ""}, {"NetlinkRIB", Func, 0, "func(proto int, family int) ([]byte, error)"}, {"NetlinkRouteAttr", Type, 0, ""}, {"NetlinkRouteAttr.Attr", Field, 0, ""}, {"NetlinkRouteAttr.Value", Field, 0, ""}, {"NetlinkRouteRequest", Type, 0, ""}, {"NetlinkRouteRequest.Data", Field, 0, ""}, {"NetlinkRouteRequest.Header", Field, 0, ""}, {"NewCallback", Func, 0, ""}, {"NewCallbackCDecl", Func, 3, ""}, {"NewLazyDLL", Func, 0, ""}, {"NlAttr", Type, 0, ""}, {"NlAttr.Len", Field, 0, ""}, {"NlAttr.Type", Field, 0, ""}, {"NlMsgerr", Type, 0, ""}, {"NlMsgerr.Error", Field, 0, ""}, {"NlMsgerr.Msg", Field, 0, ""}, {"NlMsghdr", Type, 0, ""}, {"NlMsghdr.Flags", Field, 0, ""}, {"NlMsghdr.Len", Field, 0, ""}, {"NlMsghdr.Pid", Field, 0, ""}, {"NlMsghdr.Seq", Field, 0, ""}, {"NlMsghdr.Type", Field, 0, ""}, {"NsecToFiletime", Func, 0, ""}, {"NsecToTimespec", Func, 0, "func(nsec int64) Timespec"}, {"NsecToTimeval", Func, 0, "func(nsec int64) Timeval"}, {"Ntohs", Func, 0, ""}, {"OCRNL", Const, 0, ""}, {"OFDEL", Const, 0, ""}, {"OFILL", Const, 0, ""}, {"OFIOGETBMAP", Const, 1, ""}, {"OID_PKIX_KP_SERVER_AUTH", Var, 0, ""}, {"OID_SERVER_GATED_CRYPTO", Var, 0, ""}, {"OID_SGC_NETSCAPE", Var, 0, ""}, {"OLCUC", Const, 0, ""}, {"ONLCR", Const, 0, ""}, {"ONLRET", Const, 0, ""}, {"ONOCR", Const, 0, ""}, {"ONOEOT", Const, 1, ""}, {"OPEN_ALWAYS", Const, 0, ""}, {"OPEN_EXISTING", Const, 0, ""}, {"OPOST", Const, 0, ""}, {"O_ACCMODE", Const, 0, ""}, {"O_ALERT", Const, 0, ""}, {"O_ALT_IO", Const, 1, ""}, {"O_APPEND", Const, 0, ""}, {"O_ASYNC", Const, 0, ""}, {"O_CLOEXEC", Const, 0, ""}, {"O_CREAT", Const, 0, ""}, {"O_DIRECT", Const, 0, ""}, {"O_DIRECTORY", Const, 0, ""}, {"O_DP_GETRAWENCRYPTED", Const, 16, ""}, {"O_DSYNC", Const, 0, ""}, {"O_EVTONLY", Const, 0, ""}, {"O_EXCL", Const, 0, ""}, {"O_EXEC", Const, 0, ""}, {"O_EXLOCK", Const, 0, ""}, {"O_FSYNC", Const, 0, ""}, {"O_LARGEFILE", Const, 0, ""}, {"O_NDELAY", Const, 0, ""}, {"O_NOATIME", Const, 0, ""}, {"O_NOCTTY", Const, 0, ""}, {"O_NOFOLLOW", Const, 0, ""}, {"O_NONBLOCK", Const, 0, ""}, {"O_NOSIGPIPE", Const, 1, ""}, {"O_POPUP", Const, 0, ""}, {"O_RDONLY", Const, 0, ""}, {"O_RDWR", Const, 0, ""}, {"O_RSYNC", Const, 0, ""}, {"O_SHLOCK", Const, 0, ""}, {"O_SYMLINK", Const, 0, ""}, {"O_SYNC", Const, 0, ""}, {"O_TRUNC", Const, 0, ""}, {"O_TTY_INIT", Const, 0, ""}, {"O_WRONLY", Const, 0, ""}, {"Open", Func, 0, "func(path string, mode int, perm uint32) (fd int, err error)"}, {"OpenCurrentProcessToken", Func, 0, ""}, {"OpenProcess", Func, 0, ""}, {"OpenProcessToken", Func, 0, ""}, {"Openat", Func, 0, "func(dirfd int, path string, flags int, mode uint32) (fd int, err error)"}, {"Overlapped", Type, 0, ""}, {"Overlapped.HEvent", Field, 0, ""}, {"Overlapped.Internal", Field, 0, ""}, {"Overlapped.InternalHigh", Field, 0, ""}, {"Overlapped.Offset", Field, 0, ""}, {"Overlapped.OffsetHigh", Field, 0, ""}, {"PACKET_ADD_MEMBERSHIP", Const, 0, ""}, {"PACKET_BROADCAST", Const, 0, ""}, {"PACKET_DROP_MEMBERSHIP", Const, 0, ""}, {"PACKET_FASTROUTE", Const, 0, ""}, {"PACKET_HOST", Const, 0, ""}, {"PACKET_LOOPBACK", Const, 0, ""}, {"PACKET_MR_ALLMULTI", Const, 0, ""}, {"PACKET_MR_MULTICAST", Const, 0, ""}, {"PACKET_MR_PROMISC", Const, 0, ""}, {"PACKET_MULTICAST", Const, 0, ""}, {"PACKET_OTHERHOST", Const, 0, ""}, {"PACKET_OUTGOING", Const, 0, ""}, {"PACKET_RECV_OUTPUT", Const, 0, ""}, {"PACKET_RX_RING", Const, 0, ""}, {"PACKET_STATISTICS", Const, 0, ""}, {"PAGE_EXECUTE_READ", Const, 0, ""}, {"PAGE_EXECUTE_READWRITE", Const, 0, ""}, {"PAGE_EXECUTE_WRITECOPY", Const, 0, ""}, {"PAGE_READONLY", Const, 0, ""}, {"PAGE_READWRITE", Const, 0, ""}, {"PAGE_WRITECOPY", Const, 0, ""}, {"PARENB", Const, 0, ""}, {"PARMRK", Const, 0, ""}, {"PARODD", Const, 0, ""}, {"PENDIN", Const, 0, ""}, {"PFL_HIDDEN", Const, 2, ""}, {"PFL_MATCHES_PROTOCOL_ZERO", Const, 2, ""}, {"PFL_MULTIPLE_PROTO_ENTRIES", Const, 2, ""}, {"PFL_NETWORKDIRECT_PROVIDER", Const, 2, ""}, {"PFL_RECOMMENDED_PROTO_ENTRY", Const, 2, ""}, {"PF_FLUSH", Const, 1, ""}, {"PKCS_7_ASN_ENCODING", Const, 0, ""}, {"PMC5_PIPELINE_FLUSH", Const, 1, ""}, {"PRIO_PGRP", Const, 2, ""}, {"PRIO_PROCESS", Const, 2, ""}, {"PRIO_USER", Const, 2, ""}, {"PRI_IOFLUSH", Const, 1, ""}, {"PROCESS_QUERY_INFORMATION", Const, 0, ""}, {"PROCESS_TERMINATE", Const, 2, ""}, {"PROT_EXEC", Const, 0, ""}, {"PROT_GROWSDOWN", Const, 0, ""}, {"PROT_GROWSUP", Const, 0, ""}, {"PROT_NONE", Const, 0, ""}, {"PROT_READ", Const, 0, ""}, {"PROT_WRITE", Const, 0, ""}, {"PROV_DH_SCHANNEL", Const, 0, ""}, {"PROV_DSS", Const, 0, ""}, {"PROV_DSS_DH", Const, 0, ""}, {"PROV_EC_ECDSA_FULL", Const, 0, ""}, {"PROV_EC_ECDSA_SIG", Const, 0, ""}, {"PROV_EC_ECNRA_FULL", Const, 0, ""}, {"PROV_EC_ECNRA_SIG", Const, 0, ""}, {"PROV_FORTEZZA", Const, 0, ""}, {"PROV_INTEL_SEC", Const, 0, ""}, {"PROV_MS_EXCHANGE", Const, 0, ""}, {"PROV_REPLACE_OWF", Const, 0, ""}, {"PROV_RNG", Const, 0, ""}, {"PROV_RSA_AES", Const, 0, ""}, {"PROV_RSA_FULL", Const, 0, ""}, {"PROV_RSA_SCHANNEL", Const, 0, ""}, {"PROV_RSA_SIG", Const, 0, ""}, {"PROV_SPYRUS_LYNKS", Const, 0, ""}, {"PROV_SSL", Const, 0, ""}, {"PR_CAPBSET_DROP", Const, 0, ""}, {"PR_CAPBSET_READ", Const, 0, ""}, {"PR_CLEAR_SECCOMP_FILTER", Const, 0, ""}, {"PR_ENDIAN_BIG", Const, 0, ""}, {"PR_ENDIAN_LITTLE", Const, 0, ""}, {"PR_ENDIAN_PPC_LITTLE", Const, 0, ""}, {"PR_FPEMU_NOPRINT", Const, 0, ""}, {"PR_FPEMU_SIGFPE", Const, 0, ""}, {"PR_FP_EXC_ASYNC", Const, 0, ""}, {"PR_FP_EXC_DISABLED", Const, 0, ""}, {"PR_FP_EXC_DIV", Const, 0, ""}, {"PR_FP_EXC_INV", Const, 0, ""}, {"PR_FP_EXC_NONRECOV", Const, 0, ""}, {"PR_FP_EXC_OVF", Const, 0, ""}, {"PR_FP_EXC_PRECISE", Const, 0, ""}, {"PR_FP_EXC_RES", Const, 0, ""}, {"PR_FP_EXC_SW_ENABLE", Const, 0, ""}, {"PR_FP_EXC_UND", Const, 0, ""}, {"PR_GET_DUMPABLE", Const, 0, ""}, {"PR_GET_ENDIAN", Const, 0, ""}, {"PR_GET_FPEMU", Const, 0, ""}, {"PR_GET_FPEXC", Const, 0, ""}, {"PR_GET_KEEPCAPS", Const, 0, ""}, {"PR_GET_NAME", Const, 0, ""}, {"PR_GET_PDEATHSIG", Const, 0, ""}, {"PR_GET_SECCOMP", Const, 0, ""}, {"PR_GET_SECCOMP_FILTER", Const, 0, ""}, {"PR_GET_SECUREBITS", Const, 0, ""}, {"PR_GET_TIMERSLACK", Const, 0, ""}, {"PR_GET_TIMING", Const, 0, ""}, {"PR_GET_TSC", Const, 0, ""}, {"PR_GET_UNALIGN", Const, 0, ""}, {"PR_MCE_KILL", Const, 0, ""}, {"PR_MCE_KILL_CLEAR", Const, 0, ""}, {"PR_MCE_KILL_DEFAULT", Const, 0, ""}, {"PR_MCE_KILL_EARLY", Const, 0, ""}, {"PR_MCE_KILL_GET", Const, 0, ""}, {"PR_MCE_KILL_LATE", Const, 0, ""}, {"PR_MCE_KILL_SET", Const, 0, ""}, {"PR_SECCOMP_FILTER_EVENT", Const, 0, ""}, {"PR_SECCOMP_FILTER_SYSCALL", Const, 0, ""}, {"PR_SET_DUMPABLE", Const, 0, ""}, {"PR_SET_ENDIAN", Const, 0, ""}, {"PR_SET_FPEMU", Const, 0, ""}, {"PR_SET_FPEXC", Const, 0, ""}, {"PR_SET_KEEPCAPS", Const, 0, ""}, {"PR_SET_NAME", Const, 0, ""}, {"PR_SET_PDEATHSIG", Const, 0, ""}, {"PR_SET_PTRACER", Const, 0, ""}, {"PR_SET_SECCOMP", Const, 0, ""}, {"PR_SET_SECCOMP_FILTER", Const, 0, ""}, {"PR_SET_SECUREBITS", Const, 0, ""}, {"PR_SET_TIMERSLACK", Const, 0, ""}, {"PR_SET_TIMING", Const, 0, ""}, {"PR_SET_TSC", Const, 0, ""}, {"PR_SET_UNALIGN", Const, 0, ""}, {"PR_TASK_PERF_EVENTS_DISABLE", Const, 0, ""}, {"PR_TASK_PERF_EVENTS_ENABLE", Const, 0, ""}, {"PR_TIMING_STATISTICAL", Const, 0, ""}, {"PR_TIMING_TIMESTAMP", Const, 0, ""}, {"PR_TSC_ENABLE", Const, 0, ""}, {"PR_TSC_SIGSEGV", Const, 0, ""}, {"PR_UNALIGN_NOPRINT", Const, 0, ""}, {"PR_UNALIGN_SIGBUS", Const, 0, ""}, {"PTRACE_ARCH_PRCTL", Const, 0, ""}, {"PTRACE_ATTACH", Const, 0, ""}, {"PTRACE_CONT", Const, 0, ""}, {"PTRACE_DETACH", Const, 0, ""}, {"PTRACE_EVENT_CLONE", Const, 0, ""}, {"PTRACE_EVENT_EXEC", Const, 0, ""}, {"PTRACE_EVENT_EXIT", Const, 0, ""}, {"PTRACE_EVENT_FORK", Const, 0, ""}, {"PTRACE_EVENT_VFORK", Const, 0, ""}, {"PTRACE_EVENT_VFORK_DONE", Const, 0, ""}, {"PTRACE_GETCRUNCHREGS", Const, 0, ""}, {"PTRACE_GETEVENTMSG", Const, 0, ""}, {"PTRACE_GETFPREGS", Const, 0, ""}, {"PTRACE_GETFPXREGS", Const, 0, ""}, {"PTRACE_GETHBPREGS", Const, 0, ""}, {"PTRACE_GETREGS", Const, 0, ""}, {"PTRACE_GETREGSET", Const, 0, ""}, {"PTRACE_GETSIGINFO", Const, 0, ""}, {"PTRACE_GETVFPREGS", Const, 0, ""}, {"PTRACE_GETWMMXREGS", Const, 0, ""}, {"PTRACE_GET_THREAD_AREA", Const, 0, ""}, {"PTRACE_KILL", Const, 0, ""}, {"PTRACE_OLDSETOPTIONS", Const, 0, ""}, {"PTRACE_O_MASK", Const, 0, ""}, {"PTRACE_O_TRACECLONE", Const, 0, ""}, {"PTRACE_O_TRACEEXEC", Const, 0, ""}, {"PTRACE_O_TRACEEXIT", Const, 0, ""}, {"PTRACE_O_TRACEFORK", Const, 0, ""}, {"PTRACE_O_TRACESYSGOOD", Const, 0, ""}, {"PTRACE_O_TRACEVFORK", Const, 0, ""}, {"PTRACE_O_TRACEVFORKDONE", Const, 0, ""}, {"PTRACE_PEEKDATA", Const, 0, ""}, {"PTRACE_PEEKTEXT", Const, 0, ""}, {"PTRACE_PEEKUSR", Const, 0, ""}, {"PTRACE_POKEDATA", Const, 0, ""}, {"PTRACE_POKETEXT", Const, 0, ""}, {"PTRACE_POKEUSR", Const, 0, ""}, {"PTRACE_SETCRUNCHREGS", Const, 0, ""}, {"PTRACE_SETFPREGS", Const, 0, ""}, {"PTRACE_SETFPXREGS", Const, 0, ""}, {"PTRACE_SETHBPREGS", Const, 0, ""}, {"PTRACE_SETOPTIONS", Const, 0, ""}, {"PTRACE_SETREGS", Const, 0, ""}, {"PTRACE_SETREGSET", Const, 0, ""}, {"PTRACE_SETSIGINFO", Const, 0, ""}, {"PTRACE_SETVFPREGS", Const, 0, ""}, {"PTRACE_SETWMMXREGS", Const, 0, ""}, {"PTRACE_SET_SYSCALL", Const, 0, ""}, {"PTRACE_SET_THREAD_AREA", Const, 0, ""}, {"PTRACE_SINGLEBLOCK", Const, 0, ""}, {"PTRACE_SINGLESTEP", Const, 0, ""}, {"PTRACE_SYSCALL", Const, 0, ""}, {"PTRACE_SYSEMU", Const, 0, ""}, {"PTRACE_SYSEMU_SINGLESTEP", Const, 0, ""}, {"PTRACE_TRACEME", Const, 0, ""}, {"PT_ATTACH", Const, 0, ""}, {"PT_ATTACHEXC", Const, 0, ""}, {"PT_CONTINUE", Const, 0, ""}, {"PT_DATA_ADDR", Const, 0, ""}, {"PT_DENY_ATTACH", Const, 0, ""}, {"PT_DETACH", Const, 0, ""}, {"PT_FIRSTMACH", Const, 0, ""}, {"PT_FORCEQUOTA", Const, 0, ""}, {"PT_KILL", Const, 0, ""}, {"PT_MASK", Const, 1, ""}, {"PT_READ_D", Const, 0, ""}, {"PT_READ_I", Const, 0, ""}, {"PT_READ_U", Const, 0, ""}, {"PT_SIGEXC", Const, 0, ""}, {"PT_STEP", Const, 0, ""}, {"PT_TEXT_ADDR", Const, 0, ""}, {"PT_TEXT_END_ADDR", Const, 0, ""}, {"PT_THUPDATE", Const, 0, ""}, {"PT_TRACE_ME", Const, 0, ""}, {"PT_WRITE_D", Const, 0, ""}, {"PT_WRITE_I", Const, 0, ""}, {"PT_WRITE_U", Const, 0, ""}, {"ParseDirent", Func, 0, "func(buf []byte, max int, names []string) (consumed int, count int, newnames []string)"}, {"ParseNetlinkMessage", Func, 0, "func(b []byte) ([]NetlinkMessage, error)"}, {"ParseNetlinkRouteAttr", Func, 0, "func(m *NetlinkMessage) ([]NetlinkRouteAttr, error)"}, {"ParseRoutingMessage", Func, 0, ""}, {"ParseRoutingSockaddr", Func, 0, ""}, {"ParseSocketControlMessage", Func, 0, "func(b []byte) ([]SocketControlMessage, error)"}, {"ParseUnixCredentials", Func, 0, "func(m *SocketControlMessage) (*Ucred, error)"}, {"ParseUnixRights", Func, 0, "func(m *SocketControlMessage) ([]int, error)"}, {"PathMax", Const, 0, ""}, {"Pathconf", Func, 0, ""}, {"Pause", Func, 0, "func() (err error)"}, {"Pipe", Func, 0, "func(p []int) error"}, {"Pipe2", Func, 1, "func(p []int, flags int) error"}, {"PivotRoot", Func, 0, "func(newroot string, putold string) (err error)"}, {"Pointer", Type, 11, ""}, {"PostQueuedCompletionStatus", Func, 0, ""}, {"Pread", Func, 0, "func(fd int, p []byte, offset int64) (n int, err error)"}, {"Proc", Type, 0, ""}, {"Proc.Dll", Field, 0, ""}, {"Proc.Name", Field, 0, ""}, {"ProcAttr", Type, 0, ""}, {"ProcAttr.Dir", Field, 0, ""}, {"ProcAttr.Env", Field, 0, ""}, {"ProcAttr.Files", Field, 0, ""}, {"ProcAttr.Sys", Field, 0, ""}, {"Process32First", Func, 4, ""}, {"Process32Next", Func, 4, ""}, {"ProcessEntry32", Type, 4, ""}, {"ProcessEntry32.DefaultHeapID", Field, 4, ""}, {"ProcessEntry32.ExeFile", Field, 4, ""}, {"ProcessEntry32.Flags", Field, 4, ""}, {"ProcessEntry32.ModuleID", Field, 4, ""}, {"ProcessEntry32.ParentProcessID", Field, 4, ""}, {"ProcessEntry32.PriClassBase", Field, 4, ""}, {"ProcessEntry32.ProcessID", Field, 4, ""}, {"ProcessEntry32.Size", Field, 4, ""}, {"ProcessEntry32.Threads", Field, 4, ""}, {"ProcessEntry32.Usage", Field, 4, ""}, {"ProcessInformation", Type, 0, ""}, {"ProcessInformation.Process", Field, 0, ""}, {"ProcessInformation.ProcessId", Field, 0, ""}, {"ProcessInformation.Thread", Field, 0, ""}, {"ProcessInformation.ThreadId", Field, 0, ""}, {"Protoent", Type, 0, ""}, {"Protoent.Aliases", Field, 0, ""}, {"Protoent.Name", Field, 0, ""}, {"Protoent.Proto", Field, 0, ""}, {"PtraceAttach", Func, 0, "func(pid int) (err error)"}, {"PtraceCont", Func, 0, "func(pid int, signal int) (err error)"}, {"PtraceDetach", Func, 0, "func(pid int) (err error)"}, {"PtraceGetEventMsg", Func, 0, "func(pid int) (msg uint, err error)"}, {"PtraceGetRegs", Func, 0, "func(pid int, regsout *PtraceRegs) (err error)"}, {"PtracePeekData", Func, 0, "func(pid int, addr uintptr, out []byte) (count int, err error)"}, {"PtracePeekText", Func, 0, "func(pid int, addr uintptr, out []byte) (count int, err error)"}, {"PtracePokeData", Func, 0, "func(pid int, addr uintptr, data []byte) (count int, err error)"}, {"PtracePokeText", Func, 0, "func(pid int, addr uintptr, data []byte) (count int, err error)"}, {"PtraceRegs", Type, 0, ""}, {"PtraceRegs.Cs", Field, 0, ""}, {"PtraceRegs.Ds", Field, 0, ""}, {"PtraceRegs.Eax", Field, 0, ""}, {"PtraceRegs.Ebp", Field, 0, ""}, {"PtraceRegs.Ebx", Field, 0, ""}, {"PtraceRegs.Ecx", Field, 0, ""}, {"PtraceRegs.Edi", Field, 0, ""}, {"PtraceRegs.Edx", Field, 0, ""}, {"PtraceRegs.Eflags", Field, 0, ""}, {"PtraceRegs.Eip", Field, 0, ""}, {"PtraceRegs.Es", Field, 0, ""}, {"PtraceRegs.Esi", Field, 0, ""}, {"PtraceRegs.Esp", Field, 0, ""}, {"PtraceRegs.Fs", Field, 0, ""}, {"PtraceRegs.Fs_base", Field, 0, ""}, {"PtraceRegs.Gs", Field, 0, ""}, {"PtraceRegs.Gs_base", Field, 0, ""}, {"PtraceRegs.Orig_eax", Field, 0, ""}, {"PtraceRegs.Orig_rax", Field, 0, ""}, {"PtraceRegs.R10", Field, 0, ""}, {"PtraceRegs.R11", Field, 0, ""}, {"PtraceRegs.R12", Field, 0, ""}, {"PtraceRegs.R13", Field, 0, ""}, {"PtraceRegs.R14", Field, 0, ""}, {"PtraceRegs.R15", Field, 0, ""}, {"PtraceRegs.R8", Field, 0, ""}, {"PtraceRegs.R9", Field, 0, ""}, {"PtraceRegs.Rax", Field, 0, ""}, {"PtraceRegs.Rbp", Field, 0, ""}, {"PtraceRegs.Rbx", Field, 0, ""}, {"PtraceRegs.Rcx", Field, 0, ""}, {"PtraceRegs.Rdi", Field, 0, ""}, {"PtraceRegs.Rdx", Field, 0, ""}, {"PtraceRegs.Rip", Field, 0, ""}, {"PtraceRegs.Rsi", Field, 0, ""}, {"PtraceRegs.Rsp", Field, 0, ""}, {"PtraceRegs.Ss", Field, 0, ""}, {"PtraceRegs.Uregs", Field, 0, ""}, {"PtraceRegs.Xcs", Field, 0, ""}, {"PtraceRegs.Xds", Field, 0, ""}, {"PtraceRegs.Xes", Field, 0, ""}, {"PtraceRegs.Xfs", Field, 0, ""}, {"PtraceRegs.Xgs", Field, 0, ""}, {"PtraceRegs.Xss", Field, 0, ""}, {"PtraceSetOptions", Func, 0, "func(pid int, options int) (err error)"}, {"PtraceSetRegs", Func, 0, "func(pid int, regs *PtraceRegs) (err error)"}, {"PtraceSingleStep", Func, 0, "func(pid int) (err error)"}, {"PtraceSyscall", Func, 1, "func(pid int, signal int) (err error)"}, {"Pwrite", Func, 0, "func(fd int, p []byte, offset int64) (n int, err error)"}, {"REG_BINARY", Const, 0, ""}, {"REG_DWORD", Const, 0, ""}, {"REG_DWORD_BIG_ENDIAN", Const, 0, ""}, {"REG_DWORD_LITTLE_ENDIAN", Const, 0, ""}, {"REG_EXPAND_SZ", Const, 0, ""}, {"REG_FULL_RESOURCE_DESCRIPTOR", Const, 0, ""}, {"REG_LINK", Const, 0, ""}, {"REG_MULTI_SZ", Const, 0, ""}, {"REG_NONE", Const, 0, ""}, {"REG_QWORD", Const, 0, ""}, {"REG_QWORD_LITTLE_ENDIAN", Const, 0, ""}, {"REG_RESOURCE_LIST", Const, 0, ""}, {"REG_RESOURCE_REQUIREMENTS_LIST", Const, 0, ""}, {"REG_SZ", Const, 0, ""}, {"RLIMIT_AS", Const, 0, ""}, {"RLIMIT_CORE", Const, 0, ""}, {"RLIMIT_CPU", Const, 0, ""}, {"RLIMIT_CPU_USAGE_MONITOR", Const, 16, ""}, {"RLIMIT_DATA", Const, 0, ""}, {"RLIMIT_FSIZE", Const, 0, ""}, {"RLIMIT_NOFILE", Const, 0, ""}, {"RLIMIT_STACK", Const, 0, ""}, {"RLIM_INFINITY", Const, 0, ""}, {"RTAX_ADVMSS", Const, 0, ""}, {"RTAX_AUTHOR", Const, 0, ""}, {"RTAX_BRD", Const, 0, ""}, {"RTAX_CWND", Const, 0, ""}, {"RTAX_DST", Const, 0, ""}, {"RTAX_FEATURES", Const, 0, ""}, {"RTAX_FEATURE_ALLFRAG", Const, 0, ""}, {"RTAX_FEATURE_ECN", Const, 0, ""}, {"RTAX_FEATURE_SACK", Const, 0, ""}, {"RTAX_FEATURE_TIMESTAMP", Const, 0, ""}, {"RTAX_GATEWAY", Const, 0, ""}, {"RTAX_GENMASK", Const, 0, ""}, {"RTAX_HOPLIMIT", Const, 0, ""}, {"RTAX_IFA", Const, 0, ""}, {"RTAX_IFP", Const, 0, ""}, {"RTAX_INITCWND", Const, 0, ""}, {"RTAX_INITRWND", Const, 0, ""}, {"RTAX_LABEL", Const, 1, ""}, {"RTAX_LOCK", Const, 0, ""}, {"RTAX_MAX", Const, 0, ""}, {"RTAX_MTU", Const, 0, ""}, {"RTAX_NETMASK", Const, 0, ""}, {"RTAX_REORDERING", Const, 0, ""}, {"RTAX_RTO_MIN", Const, 0, ""}, {"RTAX_RTT", Const, 0, ""}, {"RTAX_RTTVAR", Const, 0, ""}, {"RTAX_SRC", Const, 1, ""}, {"RTAX_SRCMASK", Const, 1, ""}, {"RTAX_SSTHRESH", Const, 0, ""}, {"RTAX_TAG", Const, 1, ""}, {"RTAX_UNSPEC", Const, 0, ""}, {"RTAX_WINDOW", Const, 0, ""}, {"RTA_ALIGNTO", Const, 0, ""}, {"RTA_AUTHOR", Const, 0, ""}, {"RTA_BRD", Const, 0, ""}, {"RTA_CACHEINFO", Const, 0, ""}, {"RTA_DST", Const, 0, ""}, {"RTA_FLOW", Const, 0, ""}, {"RTA_GATEWAY", Const, 0, ""}, {"RTA_GENMASK", Const, 0, ""}, {"RTA_IFA", Const, 0, ""}, {"RTA_IFP", Const, 0, ""}, {"RTA_IIF", Const, 0, ""}, {"RTA_LABEL", Const, 1, ""}, {"RTA_MAX", Const, 0, ""}, {"RTA_METRICS", Const, 0, ""}, {"RTA_MULTIPATH", Const, 0, ""}, {"RTA_NETMASK", Const, 0, ""}, {"RTA_OIF", Const, 0, ""}, {"RTA_PREFSRC", Const, 0, ""}, {"RTA_PRIORITY", Const, 0, ""}, {"RTA_SRC", Const, 0, ""}, {"RTA_SRCMASK", Const, 1, ""}, {"RTA_TABLE", Const, 0, ""}, {"RTA_TAG", Const, 1, ""}, {"RTA_UNSPEC", Const, 0, ""}, {"RTCF_DIRECTSRC", Const, 0, ""}, {"RTCF_DOREDIRECT", Const, 0, ""}, {"RTCF_LOG", Const, 0, ""}, {"RTCF_MASQ", Const, 0, ""}, {"RTCF_NAT", Const, 0, ""}, {"RTCF_VALVE", Const, 0, ""}, {"RTF_ADDRCLASSMASK", Const, 0, ""}, {"RTF_ADDRCONF", Const, 0, ""}, {"RTF_ALLONLINK", Const, 0, ""}, {"RTF_ANNOUNCE", Const, 1, ""}, {"RTF_BLACKHOLE", Const, 0, ""}, {"RTF_BROADCAST", Const, 0, ""}, {"RTF_CACHE", Const, 0, ""}, {"RTF_CLONED", Const, 1, ""}, {"RTF_CLONING", Const, 0, ""}, {"RTF_CONDEMNED", Const, 0, ""}, {"RTF_DEFAULT", Const, 0, ""}, {"RTF_DELCLONE", Const, 0, ""}, {"RTF_DONE", Const, 0, ""}, {"RTF_DYNAMIC", Const, 0, ""}, {"RTF_FLOW", Const, 0, ""}, {"RTF_FMASK", Const, 0, ""}, {"RTF_GATEWAY", Const, 0, ""}, {"RTF_GWFLAG_COMPAT", Const, 3, ""}, {"RTF_HOST", Const, 0, ""}, {"RTF_IFREF", Const, 0, ""}, {"RTF_IFSCOPE", Const, 0, ""}, {"RTF_INTERFACE", Const, 0, ""}, {"RTF_IRTT", Const, 0, ""}, {"RTF_LINKRT", Const, 0, ""}, {"RTF_LLDATA", Const, 0, ""}, {"RTF_LLINFO", Const, 0, ""}, {"RTF_LOCAL", Const, 0, ""}, {"RTF_MASK", Const, 1, ""}, {"RTF_MODIFIED", Const, 0, ""}, {"RTF_MPATH", Const, 1, ""}, {"RTF_MPLS", Const, 1, ""}, {"RTF_MSS", Const, 0, ""}, {"RTF_MTU", Const, 0, ""}, {"RTF_MULTICAST", Const, 0, ""}, {"RTF_NAT", Const, 0, ""}, {"RTF_NOFORWARD", Const, 0, ""}, {"RTF_NONEXTHOP", Const, 0, ""}, {"RTF_NOPMTUDISC", Const, 0, ""}, {"RTF_PERMANENT_ARP", Const, 1, ""}, {"RTF_PINNED", Const, 0, ""}, {"RTF_POLICY", Const, 0, ""}, {"RTF_PRCLONING", Const, 0, ""}, {"RTF_PROTO1", Const, 0, ""}, {"RTF_PROTO2", Const, 0, ""}, {"RTF_PROTO3", Const, 0, ""}, {"RTF_PROXY", Const, 16, ""}, {"RTF_REINSTATE", Const, 0, ""}, {"RTF_REJECT", Const, 0, ""}, {"RTF_RNH_LOCKED", Const, 0, ""}, {"RTF_ROUTER", Const, 16, ""}, {"RTF_SOURCE", Const, 1, ""}, {"RTF_SRC", Const, 1, ""}, {"RTF_STATIC", Const, 0, ""}, {"RTF_STICKY", Const, 0, ""}, {"RTF_THROW", Const, 0, ""}, {"RTF_TUNNEL", Const, 1, ""}, {"RTF_UP", Const, 0, ""}, {"RTF_USETRAILERS", Const, 1, ""}, {"RTF_WASCLONED", Const, 0, ""}, {"RTF_WINDOW", Const, 0, ""}, {"RTF_XRESOLVE", Const, 0, ""}, {"RTM_ADD", Const, 0, ""}, {"RTM_BASE", Const, 0, ""}, {"RTM_CHANGE", Const, 0, ""}, {"RTM_CHGADDR", Const, 1, ""}, {"RTM_DELACTION", Const, 0, ""}, {"RTM_DELADDR", Const, 0, ""}, {"RTM_DELADDRLABEL", Const, 0, ""}, {"RTM_DELETE", Const, 0, ""}, {"RTM_DELLINK", Const, 0, ""}, {"RTM_DELMADDR", Const, 0, ""}, {"RTM_DELNEIGH", Const, 0, ""}, {"RTM_DELQDISC", Const, 0, ""}, {"RTM_DELROUTE", Const, 0, ""}, {"RTM_DELRULE", Const, 0, ""}, {"RTM_DELTCLASS", Const, 0, ""}, {"RTM_DELTFILTER", Const, 0, ""}, {"RTM_DESYNC", Const, 1, ""}, {"RTM_F_CLONED", Const, 0, ""}, {"RTM_F_EQUALIZE", Const, 0, ""}, {"RTM_F_NOTIFY", Const, 0, ""}, {"RTM_F_PREFIX", Const, 0, ""}, {"RTM_GET", Const, 0, ""}, {"RTM_GET2", Const, 0, ""}, {"RTM_GETACTION", Const, 0, ""}, {"RTM_GETADDR", Const, 0, ""}, {"RTM_GETADDRLABEL", Const, 0, ""}, {"RTM_GETANYCAST", Const, 0, ""}, {"RTM_GETDCB", Const, 0, ""}, {"RTM_GETLINK", Const, 0, ""}, {"RTM_GETMULTICAST", Const, 0, ""}, {"RTM_GETNEIGH", Const, 0, ""}, {"RTM_GETNEIGHTBL", Const, 0, ""}, {"RTM_GETQDISC", Const, 0, ""}, {"RTM_GETROUTE", Const, 0, ""}, {"RTM_GETRULE", Const, 0, ""}, {"RTM_GETTCLASS", Const, 0, ""}, {"RTM_GETTFILTER", Const, 0, ""}, {"RTM_IEEE80211", Const, 0, ""}, {"RTM_IFANNOUNCE", Const, 0, ""}, {"RTM_IFINFO", Const, 0, ""}, {"RTM_IFINFO2", Const, 0, ""}, {"RTM_LLINFO_UPD", Const, 1, ""}, {"RTM_LOCK", Const, 0, ""}, {"RTM_LOSING", Const, 0, ""}, {"RTM_MAX", Const, 0, ""}, {"RTM_MAXSIZE", Const, 1, ""}, {"RTM_MISS", Const, 0, ""}, {"RTM_NEWACTION", Const, 0, ""}, {"RTM_NEWADDR", Const, 0, ""}, {"RTM_NEWADDRLABEL", Const, 0, ""}, {"RTM_NEWLINK", Const, 0, ""}, {"RTM_NEWMADDR", Const, 0, ""}, {"RTM_NEWMADDR2", Const, 0, ""}, {"RTM_NEWNDUSEROPT", Const, 0, ""}, {"RTM_NEWNEIGH", Const, 0, ""}, {"RTM_NEWNEIGHTBL", Const, 0, ""}, {"RTM_NEWPREFIX", Const, 0, ""}, {"RTM_NEWQDISC", Const, 0, ""}, {"RTM_NEWROUTE", Const, 0, ""}, {"RTM_NEWRULE", Const, 0, ""}, {"RTM_NEWTCLASS", Const, 0, ""}, {"RTM_NEWTFILTER", Const, 0, ""}, {"RTM_NR_FAMILIES", Const, 0, ""}, {"RTM_NR_MSGTYPES", Const, 0, ""}, {"RTM_OIFINFO", Const, 1, ""}, {"RTM_OLDADD", Const, 0, ""}, {"RTM_OLDDEL", Const, 0, ""}, {"RTM_OOIFINFO", Const, 1, ""}, {"RTM_REDIRECT", Const, 0, ""}, {"RTM_RESOLVE", Const, 0, ""}, {"RTM_RTTUNIT", Const, 0, ""}, {"RTM_SETDCB", Const, 0, ""}, {"RTM_SETGATE", Const, 1, ""}, {"RTM_SETLINK", Const, 0, ""}, {"RTM_SETNEIGHTBL", Const, 0, ""}, {"RTM_VERSION", Const, 0, ""}, {"RTNH_ALIGNTO", Const, 0, ""}, {"RTNH_F_DEAD", Const, 0, ""}, {"RTNH_F_ONLINK", Const, 0, ""}, {"RTNH_F_PERVASIVE", Const, 0, ""}, {"RTNLGRP_IPV4_IFADDR", Const, 1, ""}, {"RTNLGRP_IPV4_MROUTE", Const, 1, ""}, {"RTNLGRP_IPV4_ROUTE", Const, 1, ""}, {"RTNLGRP_IPV4_RULE", Const, 1, ""}, {"RTNLGRP_IPV6_IFADDR", Const, 1, ""}, {"RTNLGRP_IPV6_IFINFO", Const, 1, ""}, {"RTNLGRP_IPV6_MROUTE", Const, 1, ""}, {"RTNLGRP_IPV6_PREFIX", Const, 1, ""}, {"RTNLGRP_IPV6_ROUTE", Const, 1, ""}, {"RTNLGRP_IPV6_RULE", Const, 1, ""}, {"RTNLGRP_LINK", Const, 1, ""}, {"RTNLGRP_ND_USEROPT", Const, 1, ""}, {"RTNLGRP_NEIGH", Const, 1, ""}, {"RTNLGRP_NONE", Const, 1, ""}, {"RTNLGRP_NOTIFY", Const, 1, ""}, {"RTNLGRP_TC", Const, 1, ""}, {"RTN_ANYCAST", Const, 0, ""}, {"RTN_BLACKHOLE", Const, 0, ""}, {"RTN_BROADCAST", Const, 0, ""}, {"RTN_LOCAL", Const, 0, ""}, {"RTN_MAX", Const, 0, ""}, {"RTN_MULTICAST", Const, 0, ""}, {"RTN_NAT", Const, 0, ""}, {"RTN_PROHIBIT", Const, 0, ""}, {"RTN_THROW", Const, 0, ""}, {"RTN_UNICAST", Const, 0, ""}, {"RTN_UNREACHABLE", Const, 0, ""}, {"RTN_UNSPEC", Const, 0, ""}, {"RTN_XRESOLVE", Const, 0, ""}, {"RTPROT_BIRD", Const, 0, ""}, {"RTPROT_BOOT", Const, 0, ""}, {"RTPROT_DHCP", Const, 0, ""}, {"RTPROT_DNROUTED", Const, 0, ""}, {"RTPROT_GATED", Const, 0, ""}, {"RTPROT_KERNEL", Const, 0, ""}, {"RTPROT_MRT", Const, 0, ""}, {"RTPROT_NTK", Const, 0, ""}, {"RTPROT_RA", Const, 0, ""}, {"RTPROT_REDIRECT", Const, 0, ""}, {"RTPROT_STATIC", Const, 0, ""}, {"RTPROT_UNSPEC", Const, 0, ""}, {"RTPROT_XORP", Const, 0, ""}, {"RTPROT_ZEBRA", Const, 0, ""}, {"RTV_EXPIRE", Const, 0, ""}, {"RTV_HOPCOUNT", Const, 0, ""}, {"RTV_MTU", Const, 0, ""}, {"RTV_RPIPE", Const, 0, ""}, {"RTV_RTT", Const, 0, ""}, {"RTV_RTTVAR", Const, 0, ""}, {"RTV_SPIPE", Const, 0, ""}, {"RTV_SSTHRESH", Const, 0, ""}, {"RTV_WEIGHT", Const, 0, ""}, {"RT_CACHING_CONTEXT", Const, 1, ""}, {"RT_CLASS_DEFAULT", Const, 0, ""}, {"RT_CLASS_LOCAL", Const, 0, ""}, {"RT_CLASS_MAIN", Const, 0, ""}, {"RT_CLASS_MAX", Const, 0, ""}, {"RT_CLASS_UNSPEC", Const, 0, ""}, {"RT_DEFAULT_FIB", Const, 1, ""}, {"RT_NORTREF", Const, 1, ""}, {"RT_SCOPE_HOST", Const, 0, ""}, {"RT_SCOPE_LINK", Const, 0, ""}, {"RT_SCOPE_NOWHERE", Const, 0, ""}, {"RT_SCOPE_SITE", Const, 0, ""}, {"RT_SCOPE_UNIVERSE", Const, 0, ""}, {"RT_TABLEID_MAX", Const, 1, ""}, {"RT_TABLE_COMPAT", Const, 0, ""}, {"RT_TABLE_DEFAULT", Const, 0, ""}, {"RT_TABLE_LOCAL", Const, 0, ""}, {"RT_TABLE_MAIN", Const, 0, ""}, {"RT_TABLE_MAX", Const, 0, ""}, {"RT_TABLE_UNSPEC", Const, 0, ""}, {"RUSAGE_CHILDREN", Const, 0, ""}, {"RUSAGE_SELF", Const, 0, ""}, {"RUSAGE_THREAD", Const, 0, ""}, {"Radvisory_t", Type, 0, ""}, {"Radvisory_t.Count", Field, 0, ""}, {"Radvisory_t.Offset", Field, 0, ""}, {"Radvisory_t.Pad_cgo_0", Field, 0, ""}, {"RawConn", Type, 9, ""}, {"RawSockaddr", Type, 0, ""}, {"RawSockaddr.Data", Field, 0, ""}, {"RawSockaddr.Family", Field, 0, ""}, {"RawSockaddr.Len", Field, 0, ""}, {"RawSockaddrAny", Type, 0, ""}, {"RawSockaddrAny.Addr", Field, 0, ""}, {"RawSockaddrAny.Pad", Field, 0, ""}, {"RawSockaddrDatalink", Type, 0, ""}, {"RawSockaddrDatalink.Alen", Field, 0, ""}, {"RawSockaddrDatalink.Data", Field, 0, ""}, {"RawSockaddrDatalink.Family", Field, 0, ""}, {"RawSockaddrDatalink.Index", Field, 0, ""}, {"RawSockaddrDatalink.Len", Field, 0, ""}, {"RawSockaddrDatalink.Nlen", Field, 0, ""}, {"RawSockaddrDatalink.Pad_cgo_0", Field, 2, ""}, {"RawSockaddrDatalink.Slen", Field, 0, ""}, {"RawSockaddrDatalink.Type", Field, 0, ""}, {"RawSockaddrInet4", Type, 0, ""}, {"RawSockaddrInet4.Addr", Field, 0, ""}, {"RawSockaddrInet4.Family", Field, 0, ""}, {"RawSockaddrInet4.Len", Field, 0, ""}, {"RawSockaddrInet4.Port", Field, 0, ""}, {"RawSockaddrInet4.Zero", Field, 0, ""}, {"RawSockaddrInet6", Type, 0, ""}, {"RawSockaddrInet6.Addr", Field, 0, ""}, {"RawSockaddrInet6.Family", Field, 0, ""}, {"RawSockaddrInet6.Flowinfo", Field, 0, ""}, {"RawSockaddrInet6.Len", Field, 0, ""}, {"RawSockaddrInet6.Port", Field, 0, ""}, {"RawSockaddrInet6.Scope_id", Field, 0, ""}, {"RawSockaddrLinklayer", Type, 0, ""}, {"RawSockaddrLinklayer.Addr", Field, 0, ""}, {"RawSockaddrLinklayer.Family", Field, 0, ""}, {"RawSockaddrLinklayer.Halen", Field, 0, ""}, {"RawSockaddrLinklayer.Hatype", Field, 0, ""}, {"RawSockaddrLinklayer.Ifindex", Field, 0, ""}, {"RawSockaddrLinklayer.Pkttype", Field, 0, ""}, {"RawSockaddrLinklayer.Protocol", Field, 0, ""}, {"RawSockaddrNetlink", Type, 0, ""}, {"RawSockaddrNetlink.Family", Field, 0, ""}, {"RawSockaddrNetlink.Groups", Field, 0, ""}, {"RawSockaddrNetlink.Pad", Field, 0, ""}, {"RawSockaddrNetlink.Pid", Field, 0, ""}, {"RawSockaddrUnix", Type, 0, ""}, {"RawSockaddrUnix.Family", Field, 0, ""}, {"RawSockaddrUnix.Len", Field, 0, ""}, {"RawSockaddrUnix.Pad_cgo_0", Field, 2, ""}, {"RawSockaddrUnix.Path", Field, 0, ""}, {"RawSyscall", Func, 0, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, {"RawSyscall6", Func, 0, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr, a4 uintptr, a5 uintptr, a6 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, {"Read", Func, 0, "func(fd int, p []byte) (n int, err error)"}, {"ReadConsole", Func, 1, ""}, {"ReadDirectoryChanges", Func, 0, ""}, {"ReadDirent", Func, 0, "func(fd int, buf []byte) (n int, err error)"}, {"ReadFile", Func, 0, ""}, {"Readlink", Func, 0, "func(path string, buf []byte) (n int, err error)"}, {"Reboot", Func, 0, "func(cmd int) (err error)"}, {"Recvfrom", Func, 0, "func(fd int, p []byte, flags int) (n int, from Sockaddr, err error)"}, {"Recvmsg", Func, 0, "func(fd int, p []byte, oob []byte, flags int) (n int, oobn int, recvflags int, from Sockaddr, err error)"}, {"RegCloseKey", Func, 0, ""}, {"RegEnumKeyEx", Func, 0, ""}, {"RegOpenKeyEx", Func, 0, ""}, {"RegQueryInfoKey", Func, 0, ""}, {"RegQueryValueEx", Func, 0, ""}, {"RemoveDirectory", Func, 0, ""}, {"Removexattr", Func, 1, "func(path string, attr string) (err error)"}, {"Rename", Func, 0, "func(oldpath string, newpath string) (err error)"}, {"Renameat", Func, 0, "func(olddirfd int, oldpath string, newdirfd int, newpath string) (err error)"}, {"Revoke", Func, 0, ""}, {"Rlimit", Type, 0, ""}, {"Rlimit.Cur", Field, 0, ""}, {"Rlimit.Max", Field, 0, ""}, {"Rmdir", Func, 0, "func(path string) error"}, {"RouteMessage", Type, 0, ""}, {"RouteMessage.Data", Field, 0, ""}, {"RouteMessage.Header", Field, 0, ""}, {"RouteRIB", Func, 0, ""}, {"RoutingMessage", Type, 0, ""}, {"RtAttr", Type, 0, ""}, {"RtAttr.Len", Field, 0, ""}, {"RtAttr.Type", Field, 0, ""}, {"RtGenmsg", Type, 0, ""}, {"RtGenmsg.Family", Field, 0, ""}, {"RtMetrics", Type, 0, ""}, {"RtMetrics.Expire", Field, 0, ""}, {"RtMetrics.Filler", Field, 0, ""}, {"RtMetrics.Hopcount", Field, 0, ""}, {"RtMetrics.Locks", Field, 0, ""}, {"RtMetrics.Mtu", Field, 0, ""}, {"RtMetrics.Pad", Field, 3, ""}, {"RtMetrics.Pksent", Field, 0, ""}, {"RtMetrics.Recvpipe", Field, 0, ""}, {"RtMetrics.Refcnt", Field, 2, ""}, {"RtMetrics.Rtt", Field, 0, ""}, {"RtMetrics.Rttvar", Field, 0, ""}, {"RtMetrics.Sendpipe", Field, 0, ""}, {"RtMetrics.Ssthresh", Field, 0, ""}, {"RtMetrics.Weight", Field, 0, ""}, {"RtMsg", Type, 0, ""}, {"RtMsg.Dst_len", Field, 0, ""}, {"RtMsg.Family", Field, 0, ""}, {"RtMsg.Flags", Field, 0, ""}, {"RtMsg.Protocol", Field, 0, ""}, {"RtMsg.Scope", Field, 0, ""}, {"RtMsg.Src_len", Field, 0, ""}, {"RtMsg.Table", Field, 0, ""}, {"RtMsg.Tos", Field, 0, ""}, {"RtMsg.Type", Field, 0, ""}, {"RtMsghdr", Type, 0, ""}, {"RtMsghdr.Addrs", Field, 0, ""}, {"RtMsghdr.Errno", Field, 0, ""}, {"RtMsghdr.Flags", Field, 0, ""}, {"RtMsghdr.Fmask", Field, 0, ""}, {"RtMsghdr.Hdrlen", Field, 2, ""}, {"RtMsghdr.Index", Field, 0, ""}, {"RtMsghdr.Inits", Field, 0, ""}, {"RtMsghdr.Mpls", Field, 2, ""}, {"RtMsghdr.Msglen", Field, 0, ""}, {"RtMsghdr.Pad_cgo_0", Field, 0, ""}, {"RtMsghdr.Pad_cgo_1", Field, 2, ""}, {"RtMsghdr.Pid", Field, 0, ""}, {"RtMsghdr.Priority", Field, 2, ""}, {"RtMsghdr.Rmx", Field, 0, ""}, {"RtMsghdr.Seq", Field, 0, ""}, {"RtMsghdr.Tableid", Field, 2, ""}, {"RtMsghdr.Type", Field, 0, ""}, {"RtMsghdr.Use", Field, 0, ""}, {"RtMsghdr.Version", Field, 0, ""}, {"RtNexthop", Type, 0, ""}, {"RtNexthop.Flags", Field, 0, ""}, {"RtNexthop.Hops", Field, 0, ""}, {"RtNexthop.Ifindex", Field, 0, ""}, {"RtNexthop.Len", Field, 0, ""}, {"Rusage", Type, 0, ""}, {"Rusage.CreationTime", Field, 0, ""}, {"Rusage.ExitTime", Field, 0, ""}, {"Rusage.Idrss", Field, 0, ""}, {"Rusage.Inblock", Field, 0, ""}, {"Rusage.Isrss", Field, 0, ""}, {"Rusage.Ixrss", Field, 0, ""}, {"Rusage.KernelTime", Field, 0, ""}, {"Rusage.Majflt", Field, 0, ""}, {"Rusage.Maxrss", Field, 0, ""}, {"Rusage.Minflt", Field, 0, ""}, {"Rusage.Msgrcv", Field, 0, ""}, {"Rusage.Msgsnd", Field, 0, ""}, {"Rusage.Nivcsw", Field, 0, ""}, {"Rusage.Nsignals", Field, 0, ""}, {"Rusage.Nswap", Field, 0, ""}, {"Rusage.Nvcsw", Field, 0, ""}, {"Rusage.Oublock", Field, 0, ""}, {"Rusage.Stime", Field, 0, ""}, {"Rusage.UserTime", Field, 0, ""}, {"Rusage.Utime", Field, 0, ""}, {"SCM_BINTIME", Const, 0, ""}, {"SCM_CREDENTIALS", Const, 0, ""}, {"SCM_CREDS", Const, 0, ""}, {"SCM_RIGHTS", Const, 0, ""}, {"SCM_TIMESTAMP", Const, 0, ""}, {"SCM_TIMESTAMPING", Const, 0, ""}, {"SCM_TIMESTAMPNS", Const, 0, ""}, {"SCM_TIMESTAMP_MONOTONIC", Const, 0, ""}, {"SHUT_RD", Const, 0, ""}, {"SHUT_RDWR", Const, 0, ""}, {"SHUT_WR", Const, 0, ""}, {"SID", Type, 0, ""}, {"SIDAndAttributes", Type, 0, ""}, {"SIDAndAttributes.Attributes", Field, 0, ""}, {"SIDAndAttributes.Sid", Field, 0, ""}, {"SIGABRT", Const, 0, ""}, {"SIGALRM", Const, 0, ""}, {"SIGBUS", Const, 0, ""}, {"SIGCHLD", Const, 0, ""}, {"SIGCLD", Const, 0, ""}, {"SIGCONT", Const, 0, ""}, {"SIGEMT", Const, 0, ""}, {"SIGFPE", Const, 0, ""}, {"SIGHUP", Const, 0, ""}, {"SIGILL", Const, 0, ""}, {"SIGINFO", Const, 0, ""}, {"SIGINT", Const, 0, ""}, {"SIGIO", Const, 0, ""}, {"SIGIOT", Const, 0, ""}, {"SIGKILL", Const, 0, ""}, {"SIGLIBRT", Const, 1, ""}, {"SIGLWP", Const, 0, ""}, {"SIGPIPE", Const, 0, ""}, {"SIGPOLL", Const, 0, ""}, {"SIGPROF", Const, 0, ""}, {"SIGPWR", Const, 0, ""}, {"SIGQUIT", Const, 0, ""}, {"SIGSEGV", Const, 0, ""}, {"SIGSTKFLT", Const, 0, ""}, {"SIGSTOP", Const, 0, ""}, {"SIGSYS", Const, 0, ""}, {"SIGTERM", Const, 0, ""}, {"SIGTHR", Const, 0, ""}, {"SIGTRAP", Const, 0, ""}, {"SIGTSTP", Const, 0, ""}, {"SIGTTIN", Const, 0, ""}, {"SIGTTOU", Const, 0, ""}, {"SIGUNUSED", Const, 0, ""}, {"SIGURG", Const, 0, ""}, {"SIGUSR1", Const, 0, ""}, {"SIGUSR2", Const, 0, ""}, {"SIGVTALRM", Const, 0, ""}, {"SIGWINCH", Const, 0, ""}, {"SIGXCPU", Const, 0, ""}, {"SIGXFSZ", Const, 0, ""}, {"SIOCADDDLCI", Const, 0, ""}, {"SIOCADDMULTI", Const, 0, ""}, {"SIOCADDRT", Const, 0, ""}, {"SIOCAIFADDR", Const, 0, ""}, {"SIOCAIFGROUP", Const, 0, ""}, {"SIOCALIFADDR", Const, 0, ""}, {"SIOCARPIPLL", Const, 0, ""}, {"SIOCATMARK", Const, 0, ""}, {"SIOCAUTOADDR", Const, 0, ""}, {"SIOCAUTONETMASK", Const, 0, ""}, {"SIOCBRDGADD", Const, 1, ""}, {"SIOCBRDGADDS", Const, 1, ""}, {"SIOCBRDGARL", Const, 1, ""}, {"SIOCBRDGDADDR", Const, 1, ""}, {"SIOCBRDGDEL", Const, 1, ""}, {"SIOCBRDGDELS", Const, 1, ""}, {"SIOCBRDGFLUSH", Const, 1, ""}, {"SIOCBRDGFRL", Const, 1, ""}, {"SIOCBRDGGCACHE", Const, 1, ""}, {"SIOCBRDGGFD", Const, 1, ""}, {"SIOCBRDGGHT", Const, 1, ""}, {"SIOCBRDGGIFFLGS", Const, 1, ""}, {"SIOCBRDGGMA", Const, 1, ""}, {"SIOCBRDGGPARAM", Const, 1, ""}, {"SIOCBRDGGPRI", Const, 1, ""}, {"SIOCBRDGGRL", Const, 1, ""}, {"SIOCBRDGGSIFS", Const, 1, ""}, {"SIOCBRDGGTO", Const, 1, ""}, {"SIOCBRDGIFS", Const, 1, ""}, {"SIOCBRDGRTS", Const, 1, ""}, {"SIOCBRDGSADDR", Const, 1, ""}, {"SIOCBRDGSCACHE", Const, 1, ""}, {"SIOCBRDGSFD", Const, 1, ""}, {"SIOCBRDGSHT", Const, 1, ""}, {"SIOCBRDGSIFCOST", Const, 1, ""}, {"SIOCBRDGSIFFLGS", Const, 1, ""}, {"SIOCBRDGSIFPRIO", Const, 1, ""}, {"SIOCBRDGSMA", Const, 1, ""}, {"SIOCBRDGSPRI", Const, 1, ""}, {"SIOCBRDGSPROTO", Const, 1, ""}, {"SIOCBRDGSTO", Const, 1, ""}, {"SIOCBRDGSTXHC", Const, 1, ""}, {"SIOCDARP", Const, 0, ""}, {"SIOCDELDLCI", Const, 0, ""}, {"SIOCDELMULTI", Const, 0, ""}, {"SIOCDELRT", Const, 0, ""}, {"SIOCDEVPRIVATE", Const, 0, ""}, {"SIOCDIFADDR", Const, 0, ""}, {"SIOCDIFGROUP", Const, 0, ""}, {"SIOCDIFPHYADDR", Const, 0, ""}, {"SIOCDLIFADDR", Const, 0, ""}, {"SIOCDRARP", Const, 0, ""}, {"SIOCGARP", Const, 0, ""}, {"SIOCGDRVSPEC", Const, 0, ""}, {"SIOCGETKALIVE", Const, 1, ""}, {"SIOCGETLABEL", Const, 1, ""}, {"SIOCGETPFLOW", Const, 1, ""}, {"SIOCGETPFSYNC", Const, 1, ""}, {"SIOCGETSGCNT", Const, 0, ""}, {"SIOCGETVIFCNT", Const, 0, ""}, {"SIOCGETVLAN", Const, 0, ""}, {"SIOCGHIWAT", Const, 0, ""}, {"SIOCGIFADDR", Const, 0, ""}, {"SIOCGIFADDRPREF", Const, 1, ""}, {"SIOCGIFALIAS", Const, 1, ""}, {"SIOCGIFALTMTU", Const, 0, ""}, {"SIOCGIFASYNCMAP", Const, 0, ""}, {"SIOCGIFBOND", Const, 0, ""}, {"SIOCGIFBR", Const, 0, ""}, {"SIOCGIFBRDADDR", Const, 0, ""}, {"SIOCGIFCAP", Const, 0, ""}, {"SIOCGIFCONF", Const, 0, ""}, {"SIOCGIFCOUNT", Const, 0, ""}, {"SIOCGIFDATA", Const, 1, ""}, {"SIOCGIFDESCR", Const, 0, ""}, {"SIOCGIFDEVMTU", Const, 0, ""}, {"SIOCGIFDLT", Const, 1, ""}, {"SIOCGIFDSTADDR", Const, 0, ""}, {"SIOCGIFENCAP", Const, 0, ""}, {"SIOCGIFFIB", Const, 1, ""}, {"SIOCGIFFLAGS", Const, 0, ""}, {"SIOCGIFGATTR", Const, 1, ""}, {"SIOCGIFGENERIC", Const, 0, ""}, {"SIOCGIFGMEMB", Const, 0, ""}, {"SIOCGIFGROUP", Const, 0, ""}, {"SIOCGIFHARDMTU", Const, 3, ""}, {"SIOCGIFHWADDR", Const, 0, ""}, {"SIOCGIFINDEX", Const, 0, ""}, {"SIOCGIFKPI", Const, 0, ""}, {"SIOCGIFMAC", Const, 0, ""}, {"SIOCGIFMAP", Const, 0, ""}, {"SIOCGIFMEDIA", Const, 0, ""}, {"SIOCGIFMEM", Const, 0, ""}, {"SIOCGIFMETRIC", Const, 0, ""}, {"SIOCGIFMTU", Const, 0, ""}, {"SIOCGIFNAME", Const, 0, ""}, {"SIOCGIFNETMASK", Const, 0, ""}, {"SIOCGIFPDSTADDR", Const, 0, ""}, {"SIOCGIFPFLAGS", Const, 0, ""}, {"SIOCGIFPHYS", Const, 0, ""}, {"SIOCGIFPRIORITY", Const, 1, ""}, {"SIOCGIFPSRCADDR", Const, 0, ""}, {"SIOCGIFRDOMAIN", Const, 1, ""}, {"SIOCGIFRTLABEL", Const, 1, ""}, {"SIOCGIFSLAVE", Const, 0, ""}, {"SIOCGIFSTATUS", Const, 0, ""}, {"SIOCGIFTIMESLOT", Const, 1, ""}, {"SIOCGIFTXQLEN", Const, 0, ""}, {"SIOCGIFVLAN", Const, 0, ""}, {"SIOCGIFWAKEFLAGS", Const, 0, ""}, {"SIOCGIFXFLAGS", Const, 1, ""}, {"SIOCGLIFADDR", Const, 0, ""}, {"SIOCGLIFPHYADDR", Const, 0, ""}, {"SIOCGLIFPHYRTABLE", Const, 1, ""}, {"SIOCGLIFPHYTTL", Const, 3, ""}, {"SIOCGLINKSTR", Const, 1, ""}, {"SIOCGLOWAT", Const, 0, ""}, {"SIOCGPGRP", Const, 0, ""}, {"SIOCGPRIVATE_0", Const, 0, ""}, {"SIOCGPRIVATE_1", Const, 0, ""}, {"SIOCGRARP", Const, 0, ""}, {"SIOCGSPPPPARAMS", Const, 3, ""}, {"SIOCGSTAMP", Const, 0, ""}, {"SIOCGSTAMPNS", Const, 0, ""}, {"SIOCGVH", Const, 1, ""}, {"SIOCGVNETID", Const, 3, ""}, {"SIOCIFCREATE", Const, 0, ""}, {"SIOCIFCREATE2", Const, 0, ""}, {"SIOCIFDESTROY", Const, 0, ""}, {"SIOCIFGCLONERS", Const, 0, ""}, {"SIOCINITIFADDR", Const, 1, ""}, {"SIOCPROTOPRIVATE", Const, 0, ""}, {"SIOCRSLVMULTI", Const, 0, ""}, {"SIOCRTMSG", Const, 0, ""}, {"SIOCSARP", Const, 0, ""}, {"SIOCSDRVSPEC", Const, 0, ""}, {"SIOCSETKALIVE", Const, 1, ""}, {"SIOCSETLABEL", Const, 1, ""}, {"SIOCSETPFLOW", Const, 1, ""}, {"SIOCSETPFSYNC", Const, 1, ""}, {"SIOCSETVLAN", Const, 0, ""}, {"SIOCSHIWAT", Const, 0, ""}, {"SIOCSIFADDR", Const, 0, ""}, {"SIOCSIFADDRPREF", Const, 1, ""}, {"SIOCSIFALTMTU", Const, 0, ""}, {"SIOCSIFASYNCMAP", Const, 0, ""}, {"SIOCSIFBOND", Const, 0, ""}, {"SIOCSIFBR", Const, 0, ""}, {"SIOCSIFBRDADDR", Const, 0, ""}, {"SIOCSIFCAP", Const, 0, ""}, {"SIOCSIFDESCR", Const, 0, ""}, {"SIOCSIFDSTADDR", Const, 0, ""}, {"SIOCSIFENCAP", Const, 0, ""}, {"SIOCSIFFIB", Const, 1, ""}, {"SIOCSIFFLAGS", Const, 0, ""}, {"SIOCSIFGATTR", Const, 1, ""}, {"SIOCSIFGENERIC", Const, 0, ""}, {"SIOCSIFHWADDR", Const, 0, ""}, {"SIOCSIFHWBROADCAST", Const, 0, ""}, {"SIOCSIFKPI", Const, 0, ""}, {"SIOCSIFLINK", Const, 0, ""}, {"SIOCSIFLLADDR", Const, 0, ""}, {"SIOCSIFMAC", Const, 0, ""}, {"SIOCSIFMAP", Const, 0, ""}, {"SIOCSIFMEDIA", Const, 0, ""}, {"SIOCSIFMEM", Const, 0, ""}, {"SIOCSIFMETRIC", Const, 0, ""}, {"SIOCSIFMTU", Const, 0, ""}, {"SIOCSIFNAME", Const, 0, ""}, {"SIOCSIFNETMASK", Const, 0, ""}, {"SIOCSIFPFLAGS", Const, 0, ""}, {"SIOCSIFPHYADDR", Const, 0, ""}, {"SIOCSIFPHYS", Const, 0, ""}, {"SIOCSIFPRIORITY", Const, 1, ""}, {"SIOCSIFRDOMAIN", Const, 1, ""}, {"SIOCSIFRTLABEL", Const, 1, ""}, {"SIOCSIFRVNET", Const, 0, ""}, {"SIOCSIFSLAVE", Const, 0, ""}, {"SIOCSIFTIMESLOT", Const, 1, ""}, {"SIOCSIFTXQLEN", Const, 0, ""}, {"SIOCSIFVLAN", Const, 0, ""}, {"SIOCSIFVNET", Const, 0, ""}, {"SIOCSIFXFLAGS", Const, 1, ""}, {"SIOCSLIFPHYADDR", Const, 0, ""}, {"SIOCSLIFPHYRTABLE", Const, 1, ""}, {"SIOCSLIFPHYTTL", Const, 3, ""}, {"SIOCSLINKSTR", Const, 1, ""}, {"SIOCSLOWAT", Const, 0, ""}, {"SIOCSPGRP", Const, 0, ""}, {"SIOCSRARP", Const, 0, ""}, {"SIOCSSPPPPARAMS", Const, 3, ""}, {"SIOCSVH", Const, 1, ""}, {"SIOCSVNETID", Const, 3, ""}, {"SIOCZIFDATA", Const, 1, ""}, {"SIO_GET_EXTENSION_FUNCTION_POINTER", Const, 1, ""}, {"SIO_GET_INTERFACE_LIST", Const, 0, ""}, {"SIO_KEEPALIVE_VALS", Const, 3, ""}, {"SIO_UDP_CONNRESET", Const, 4, ""}, {"SOCK_CLOEXEC", Const, 0, ""}, {"SOCK_DCCP", Const, 0, ""}, {"SOCK_DGRAM", Const, 0, ""}, {"SOCK_FLAGS_MASK", Const, 1, ""}, {"SOCK_MAXADDRLEN", Const, 0, ""}, {"SOCK_NONBLOCK", Const, 0, ""}, {"SOCK_NOSIGPIPE", Const, 1, ""}, {"SOCK_PACKET", Const, 0, ""}, {"SOCK_RAW", Const, 0, ""}, {"SOCK_RDM", Const, 0, ""}, {"SOCK_SEQPACKET", Const, 0, ""}, {"SOCK_STREAM", Const, 0, ""}, {"SOL_AAL", Const, 0, ""}, {"SOL_ATM", Const, 0, ""}, {"SOL_DECNET", Const, 0, ""}, {"SOL_ICMPV6", Const, 0, ""}, {"SOL_IP", Const, 0, ""}, {"SOL_IPV6", Const, 0, ""}, {"SOL_IRDA", Const, 0, ""}, {"SOL_PACKET", Const, 0, ""}, {"SOL_RAW", Const, 0, ""}, {"SOL_SOCKET", Const, 0, ""}, {"SOL_TCP", Const, 0, ""}, {"SOL_X25", Const, 0, ""}, {"SOMAXCONN", Const, 0, ""}, {"SO_ACCEPTCONN", Const, 0, ""}, {"SO_ACCEPTFILTER", Const, 0, ""}, {"SO_ATTACH_FILTER", Const, 0, ""}, {"SO_BINDANY", Const, 1, ""}, {"SO_BINDTODEVICE", Const, 0, ""}, {"SO_BINTIME", Const, 0, ""}, {"SO_BROADCAST", Const, 0, ""}, {"SO_BSDCOMPAT", Const, 0, ""}, {"SO_DEBUG", Const, 0, ""}, {"SO_DETACH_FILTER", Const, 0, ""}, {"SO_DOMAIN", Const, 0, ""}, {"SO_DONTROUTE", Const, 0, ""}, {"SO_DONTTRUNC", Const, 0, ""}, {"SO_ERROR", Const, 0, ""}, {"SO_KEEPALIVE", Const, 0, ""}, {"SO_LABEL", Const, 0, ""}, {"SO_LINGER", Const, 0, ""}, {"SO_LINGER_SEC", Const, 0, ""}, {"SO_LISTENINCQLEN", Const, 0, ""}, {"SO_LISTENQLEN", Const, 0, ""}, {"SO_LISTENQLIMIT", Const, 0, ""}, {"SO_MARK", Const, 0, ""}, {"SO_NETPROC", Const, 1, ""}, {"SO_NKE", Const, 0, ""}, {"SO_NOADDRERR", Const, 0, ""}, {"SO_NOHEADER", Const, 1, ""}, {"SO_NOSIGPIPE", Const, 0, ""}, {"SO_NOTIFYCONFLICT", Const, 0, ""}, {"SO_NO_CHECK", Const, 0, ""}, {"SO_NO_DDP", Const, 0, ""}, {"SO_NO_OFFLOAD", Const, 0, ""}, {"SO_NP_EXTENSIONS", Const, 0, ""}, {"SO_NREAD", Const, 0, ""}, {"SO_NUMRCVPKT", Const, 16, ""}, {"SO_NWRITE", Const, 0, ""}, {"SO_OOBINLINE", Const, 0, ""}, {"SO_OVERFLOWED", Const, 1, ""}, {"SO_PASSCRED", Const, 0, ""}, {"SO_PASSSEC", Const, 0, ""}, {"SO_PEERCRED", Const, 0, ""}, {"SO_PEERLABEL", Const, 0, ""}, {"SO_PEERNAME", Const, 0, ""}, {"SO_PEERSEC", Const, 0, ""}, {"SO_PRIORITY", Const, 0, ""}, {"SO_PROTOCOL", Const, 0, ""}, {"SO_PROTOTYPE", Const, 1, ""}, {"SO_RANDOMPORT", Const, 0, ""}, {"SO_RCVBUF", Const, 0, ""}, {"SO_RCVBUFFORCE", Const, 0, ""}, {"SO_RCVLOWAT", Const, 0, ""}, {"SO_RCVTIMEO", Const, 0, ""}, {"SO_RESTRICTIONS", Const, 0, ""}, {"SO_RESTRICT_DENYIN", Const, 0, ""}, {"SO_RESTRICT_DENYOUT", Const, 0, ""}, {"SO_RESTRICT_DENYSET", Const, 0, ""}, {"SO_REUSEADDR", Const, 0, ""}, {"SO_REUSEPORT", Const, 0, ""}, {"SO_REUSESHAREUID", Const, 0, ""}, {"SO_RTABLE", Const, 1, ""}, {"SO_RXQ_OVFL", Const, 0, ""}, {"SO_SECURITY_AUTHENTICATION", Const, 0, ""}, {"SO_SECURITY_ENCRYPTION_NETWORK", Const, 0, ""}, {"SO_SECURITY_ENCRYPTION_TRANSPORT", Const, 0, ""}, {"SO_SETFIB", Const, 0, ""}, {"SO_SNDBUF", Const, 0, ""}, {"SO_SNDBUFFORCE", Const, 0, ""}, {"SO_SNDLOWAT", Const, 0, ""}, {"SO_SNDTIMEO", Const, 0, ""}, {"SO_SPLICE", Const, 1, ""}, {"SO_TIMESTAMP", Const, 0, ""}, {"SO_TIMESTAMPING", Const, 0, ""}, {"SO_TIMESTAMPNS", Const, 0, ""}, {"SO_TIMESTAMP_MONOTONIC", Const, 0, ""}, {"SO_TYPE", Const, 0, ""}, {"SO_UPCALLCLOSEWAIT", Const, 0, ""}, {"SO_UPDATE_ACCEPT_CONTEXT", Const, 0, ""}, {"SO_UPDATE_CONNECT_CONTEXT", Const, 1, ""}, {"SO_USELOOPBACK", Const, 0, ""}, {"SO_USER_COOKIE", Const, 1, ""}, {"SO_VENDOR", Const, 3, ""}, {"SO_WANTMORE", Const, 0, ""}, {"SO_WANTOOBFLAG", Const, 0, ""}, {"SSLExtraCertChainPolicyPara", Type, 0, ""}, {"SSLExtraCertChainPolicyPara.AuthType", Field, 0, ""}, {"SSLExtraCertChainPolicyPara.Checks", Field, 0, ""}, {"SSLExtraCertChainPolicyPara.ServerName", Field, 0, ""}, {"SSLExtraCertChainPolicyPara.Size", Field, 0, ""}, {"STANDARD_RIGHTS_ALL", Const, 0, ""}, {"STANDARD_RIGHTS_EXECUTE", Const, 0, ""}, {"STANDARD_RIGHTS_READ", Const, 0, ""}, {"STANDARD_RIGHTS_REQUIRED", Const, 0, ""}, {"STANDARD_RIGHTS_WRITE", Const, 0, ""}, {"STARTF_USESHOWWINDOW", Const, 0, ""}, {"STARTF_USESTDHANDLES", Const, 0, ""}, {"STD_ERROR_HANDLE", Const, 0, ""}, {"STD_INPUT_HANDLE", Const, 0, ""}, {"STD_OUTPUT_HANDLE", Const, 0, ""}, {"SUBLANG_ENGLISH_US", Const, 0, ""}, {"SW_FORCEMINIMIZE", Const, 0, ""}, {"SW_HIDE", Const, 0, ""}, {"SW_MAXIMIZE", Const, 0, ""}, {"SW_MINIMIZE", Const, 0, ""}, {"SW_NORMAL", Const, 0, ""}, {"SW_RESTORE", Const, 0, ""}, {"SW_SHOW", Const, 0, ""}, {"SW_SHOWDEFAULT", Const, 0, ""}, {"SW_SHOWMAXIMIZED", Const, 0, ""}, {"SW_SHOWMINIMIZED", Const, 0, ""}, {"SW_SHOWMINNOACTIVE", Const, 0, ""}, {"SW_SHOWNA", Const, 0, ""}, {"SW_SHOWNOACTIVATE", Const, 0, ""}, {"SW_SHOWNORMAL", Const, 0, ""}, {"SYMBOLIC_LINK_FLAG_DIRECTORY", Const, 4, ""}, {"SYNCHRONIZE", Const, 0, ""}, {"SYSCTL_VERSION", Const, 1, ""}, {"SYSCTL_VERS_0", Const, 1, ""}, {"SYSCTL_VERS_1", Const, 1, ""}, {"SYSCTL_VERS_MASK", Const, 1, ""}, {"SYS_ABORT2", Const, 0, ""}, {"SYS_ACCEPT", Const, 0, ""}, {"SYS_ACCEPT4", Const, 0, ""}, {"SYS_ACCEPT_NOCANCEL", Const, 0, ""}, {"SYS_ACCESS", Const, 0, ""}, {"SYS_ACCESS_EXTENDED", Const, 0, ""}, {"SYS_ACCT", Const, 0, ""}, {"SYS_ADD_KEY", Const, 0, ""}, {"SYS_ADD_PROFIL", Const, 0, ""}, {"SYS_ADJFREQ", Const, 1, ""}, {"SYS_ADJTIME", Const, 0, ""}, {"SYS_ADJTIMEX", Const, 0, ""}, {"SYS_AFS_SYSCALL", Const, 0, ""}, {"SYS_AIO_CANCEL", Const, 0, ""}, {"SYS_AIO_ERROR", Const, 0, ""}, {"SYS_AIO_FSYNC", Const, 0, ""}, {"SYS_AIO_MLOCK", Const, 14, ""}, {"SYS_AIO_READ", Const, 0, ""}, {"SYS_AIO_RETURN", Const, 0, ""}, {"SYS_AIO_SUSPEND", Const, 0, ""}, {"SYS_AIO_SUSPEND_NOCANCEL", Const, 0, ""}, {"SYS_AIO_WAITCOMPLETE", Const, 14, ""}, {"SYS_AIO_WRITE", Const, 0, ""}, {"SYS_ALARM", Const, 0, ""}, {"SYS_ARCH_PRCTL", Const, 0, ""}, {"SYS_ARM_FADVISE64_64", Const, 0, ""}, {"SYS_ARM_SYNC_FILE_RANGE", Const, 0, ""}, {"SYS_ATGETMSG", Const, 0, ""}, {"SYS_ATPGETREQ", Const, 0, ""}, {"SYS_ATPGETRSP", Const, 0, ""}, {"SYS_ATPSNDREQ", Const, 0, ""}, {"SYS_ATPSNDRSP", Const, 0, ""}, {"SYS_ATPUTMSG", Const, 0, ""}, {"SYS_ATSOCKET", Const, 0, ""}, {"SYS_AUDIT", Const, 0, ""}, {"SYS_AUDITCTL", Const, 0, ""}, {"SYS_AUDITON", Const, 0, ""}, {"SYS_AUDIT_SESSION_JOIN", Const, 0, ""}, {"SYS_AUDIT_SESSION_PORT", Const, 0, ""}, {"SYS_AUDIT_SESSION_SELF", Const, 0, ""}, {"SYS_BDFLUSH", Const, 0, ""}, {"SYS_BIND", Const, 0, ""}, {"SYS_BINDAT", Const, 3, ""}, {"SYS_BREAK", Const, 0, ""}, {"SYS_BRK", Const, 0, ""}, {"SYS_BSDTHREAD_CREATE", Const, 0, ""}, {"SYS_BSDTHREAD_REGISTER", Const, 0, ""}, {"SYS_BSDTHREAD_TERMINATE", Const, 0, ""}, {"SYS_CAPGET", Const, 0, ""}, {"SYS_CAPSET", Const, 0, ""}, {"SYS_CAP_ENTER", Const, 0, ""}, {"SYS_CAP_FCNTLS_GET", Const, 1, ""}, {"SYS_CAP_FCNTLS_LIMIT", Const, 1, ""}, {"SYS_CAP_GETMODE", Const, 0, ""}, {"SYS_CAP_GETRIGHTS", Const, 0, ""}, {"SYS_CAP_IOCTLS_GET", Const, 1, ""}, {"SYS_CAP_IOCTLS_LIMIT", Const, 1, ""}, {"SYS_CAP_NEW", Const, 0, ""}, {"SYS_CAP_RIGHTS_GET", Const, 1, ""}, {"SYS_CAP_RIGHTS_LIMIT", Const, 1, ""}, {"SYS_CHDIR", Const, 0, ""}, {"SYS_CHFLAGS", Const, 0, ""}, {"SYS_CHFLAGSAT", Const, 3, ""}, {"SYS_CHMOD", Const, 0, ""}, {"SYS_CHMOD_EXTENDED", Const, 0, ""}, {"SYS_CHOWN", Const, 0, ""}, {"SYS_CHOWN32", Const, 0, ""}, {"SYS_CHROOT", Const, 0, ""}, {"SYS_CHUD", Const, 0, ""}, {"SYS_CLOCK_ADJTIME", Const, 0, ""}, {"SYS_CLOCK_GETCPUCLOCKID2", Const, 1, ""}, {"SYS_CLOCK_GETRES", Const, 0, ""}, {"SYS_CLOCK_GETTIME", Const, 0, ""}, {"SYS_CLOCK_NANOSLEEP", Const, 0, ""}, {"SYS_CLOCK_SETTIME", Const, 0, ""}, {"SYS_CLONE", Const, 0, ""}, {"SYS_CLOSE", Const, 0, ""}, {"SYS_CLOSEFROM", Const, 0, ""}, {"SYS_CLOSE_NOCANCEL", Const, 0, ""}, {"SYS_CONNECT", Const, 0, ""}, {"SYS_CONNECTAT", Const, 3, ""}, {"SYS_CONNECT_NOCANCEL", Const, 0, ""}, {"SYS_COPYFILE", Const, 0, ""}, {"SYS_CPUSET", Const, 0, ""}, {"SYS_CPUSET_GETAFFINITY", Const, 0, ""}, {"SYS_CPUSET_GETID", Const, 0, ""}, {"SYS_CPUSET_SETAFFINITY", Const, 0, ""}, {"SYS_CPUSET_SETID", Const, 0, ""}, {"SYS_CREAT", Const, 0, ""}, {"SYS_CREATE_MODULE", Const, 0, ""}, {"SYS_CSOPS", Const, 0, ""}, {"SYS_CSOPS_AUDITTOKEN", Const, 16, ""}, {"SYS_DELETE", Const, 0, ""}, {"SYS_DELETE_MODULE", Const, 0, ""}, {"SYS_DUP", Const, 0, ""}, {"SYS_DUP2", Const, 0, ""}, {"SYS_DUP3", Const, 0, ""}, {"SYS_EACCESS", Const, 0, ""}, {"SYS_EPOLL_CREATE", Const, 0, ""}, {"SYS_EPOLL_CREATE1", Const, 0, ""}, {"SYS_EPOLL_CTL", Const, 0, ""}, {"SYS_EPOLL_CTL_OLD", Const, 0, ""}, {"SYS_EPOLL_PWAIT", Const, 0, ""}, {"SYS_EPOLL_WAIT", Const, 0, ""}, {"SYS_EPOLL_WAIT_OLD", Const, 0, ""}, {"SYS_EVENTFD", Const, 0, ""}, {"SYS_EVENTFD2", Const, 0, ""}, {"SYS_EXCHANGEDATA", Const, 0, ""}, {"SYS_EXECVE", Const, 0, ""}, {"SYS_EXIT", Const, 0, ""}, {"SYS_EXIT_GROUP", Const, 0, ""}, {"SYS_EXTATTRCTL", Const, 0, ""}, {"SYS_EXTATTR_DELETE_FD", Const, 0, ""}, {"SYS_EXTATTR_DELETE_FILE", Const, 0, ""}, {"SYS_EXTATTR_DELETE_LINK", Const, 0, ""}, {"SYS_EXTATTR_GET_FD", Const, 0, ""}, {"SYS_EXTATTR_GET_FILE", Const, 0, ""}, {"SYS_EXTATTR_GET_LINK", Const, 0, ""}, {"SYS_EXTATTR_LIST_FD", Const, 0, ""}, {"SYS_EXTATTR_LIST_FILE", Const, 0, ""}, {"SYS_EXTATTR_LIST_LINK", Const, 0, ""}, {"SYS_EXTATTR_SET_FD", Const, 0, ""}, {"SYS_EXTATTR_SET_FILE", Const, 0, ""}, {"SYS_EXTATTR_SET_LINK", Const, 0, ""}, {"SYS_FACCESSAT", Const, 0, ""}, {"SYS_FADVISE64", Const, 0, ""}, {"SYS_FADVISE64_64", Const, 0, ""}, {"SYS_FALLOCATE", Const, 0, ""}, {"SYS_FANOTIFY_INIT", Const, 0, ""}, {"SYS_FANOTIFY_MARK", Const, 0, ""}, {"SYS_FCHDIR", Const, 0, ""}, {"SYS_FCHFLAGS", Const, 0, ""}, {"SYS_FCHMOD", Const, 0, ""}, {"SYS_FCHMODAT", Const, 0, ""}, {"SYS_FCHMOD_EXTENDED", Const, 0, ""}, {"SYS_FCHOWN", Const, 0, ""}, {"SYS_FCHOWN32", Const, 0, ""}, {"SYS_FCHOWNAT", Const, 0, ""}, {"SYS_FCHROOT", Const, 1, ""}, {"SYS_FCNTL", Const, 0, ""}, {"SYS_FCNTL64", Const, 0, ""}, {"SYS_FCNTL_NOCANCEL", Const, 0, ""}, {"SYS_FDATASYNC", Const, 0, ""}, {"SYS_FEXECVE", Const, 0, ""}, {"SYS_FFCLOCK_GETCOUNTER", Const, 0, ""}, {"SYS_FFCLOCK_GETESTIMATE", Const, 0, ""}, {"SYS_FFCLOCK_SETESTIMATE", Const, 0, ""}, {"SYS_FFSCTL", Const, 0, ""}, {"SYS_FGETATTRLIST", Const, 0, ""}, {"SYS_FGETXATTR", Const, 0, ""}, {"SYS_FHOPEN", Const, 0, ""}, {"SYS_FHSTAT", Const, 0, ""}, {"SYS_FHSTATFS", Const, 0, ""}, {"SYS_FILEPORT_MAKEFD", Const, 0, ""}, {"SYS_FILEPORT_MAKEPORT", Const, 0, ""}, {"SYS_FKTRACE", Const, 1, ""}, {"SYS_FLISTXATTR", Const, 0, ""}, {"SYS_FLOCK", Const, 0, ""}, {"SYS_FORK", Const, 0, ""}, {"SYS_FPATHCONF", Const, 0, ""}, {"SYS_FREEBSD6_FTRUNCATE", Const, 0, ""}, {"SYS_FREEBSD6_LSEEK", Const, 0, ""}, {"SYS_FREEBSD6_MMAP", Const, 0, ""}, {"SYS_FREEBSD6_PREAD", Const, 0, ""}, {"SYS_FREEBSD6_PWRITE", Const, 0, ""}, {"SYS_FREEBSD6_TRUNCATE", Const, 0, ""}, {"SYS_FREMOVEXATTR", Const, 0, ""}, {"SYS_FSCTL", Const, 0, ""}, {"SYS_FSETATTRLIST", Const, 0, ""}, {"SYS_FSETXATTR", Const, 0, ""}, {"SYS_FSGETPATH", Const, 0, ""}, {"SYS_FSTAT", Const, 0, ""}, {"SYS_FSTAT64", Const, 0, ""}, {"SYS_FSTAT64_EXTENDED", Const, 0, ""}, {"SYS_FSTATAT", Const, 0, ""}, {"SYS_FSTATAT64", Const, 0, ""}, {"SYS_FSTATFS", Const, 0, ""}, {"SYS_FSTATFS64", Const, 0, ""}, {"SYS_FSTATV", Const, 0, ""}, {"SYS_FSTATVFS1", Const, 1, ""}, {"SYS_FSTAT_EXTENDED", Const, 0, ""}, {"SYS_FSYNC", Const, 0, ""}, {"SYS_FSYNC_NOCANCEL", Const, 0, ""}, {"SYS_FSYNC_RANGE", Const, 1, ""}, {"SYS_FTIME", Const, 0, ""}, {"SYS_FTRUNCATE", Const, 0, ""}, {"SYS_FTRUNCATE64", Const, 0, ""}, {"SYS_FUTEX", Const, 0, ""}, {"SYS_FUTIMENS", Const, 1, ""}, {"SYS_FUTIMES", Const, 0, ""}, {"SYS_FUTIMESAT", Const, 0, ""}, {"SYS_GETATTRLIST", Const, 0, ""}, {"SYS_GETAUDIT", Const, 0, ""}, {"SYS_GETAUDIT_ADDR", Const, 0, ""}, {"SYS_GETAUID", Const, 0, ""}, {"SYS_GETCONTEXT", Const, 0, ""}, {"SYS_GETCPU", Const, 0, ""}, {"SYS_GETCWD", Const, 0, ""}, {"SYS_GETDENTS", Const, 0, ""}, {"SYS_GETDENTS64", Const, 0, ""}, {"SYS_GETDIRENTRIES", Const, 0, ""}, {"SYS_GETDIRENTRIES64", Const, 0, ""}, {"SYS_GETDIRENTRIESATTR", Const, 0, ""}, {"SYS_GETDTABLECOUNT", Const, 1, ""}, {"SYS_GETDTABLESIZE", Const, 0, ""}, {"SYS_GETEGID", Const, 0, ""}, {"SYS_GETEGID32", Const, 0, ""}, {"SYS_GETEUID", Const, 0, ""}, {"SYS_GETEUID32", Const, 0, ""}, {"SYS_GETFH", Const, 0, ""}, {"SYS_GETFSSTAT", Const, 0, ""}, {"SYS_GETFSSTAT64", Const, 0, ""}, {"SYS_GETGID", Const, 0, ""}, {"SYS_GETGID32", Const, 0, ""}, {"SYS_GETGROUPS", Const, 0, ""}, {"SYS_GETGROUPS32", Const, 0, ""}, {"SYS_GETHOSTUUID", Const, 0, ""}, {"SYS_GETITIMER", Const, 0, ""}, {"SYS_GETLCID", Const, 0, ""}, {"SYS_GETLOGIN", Const, 0, ""}, {"SYS_GETLOGINCLASS", Const, 0, ""}, {"SYS_GETPEERNAME", Const, 0, ""}, {"SYS_GETPGID", Const, 0, ""}, {"SYS_GETPGRP", Const, 0, ""}, {"SYS_GETPID", Const, 0, ""}, {"SYS_GETPMSG", Const, 0, ""}, {"SYS_GETPPID", Const, 0, ""}, {"SYS_GETPRIORITY", Const, 0, ""}, {"SYS_GETRESGID", Const, 0, ""}, {"SYS_GETRESGID32", Const, 0, ""}, {"SYS_GETRESUID", Const, 0, ""}, {"SYS_GETRESUID32", Const, 0, ""}, {"SYS_GETRLIMIT", Const, 0, ""}, {"SYS_GETRTABLE", Const, 1, ""}, {"SYS_GETRUSAGE", Const, 0, ""}, {"SYS_GETSGROUPS", Const, 0, ""}, {"SYS_GETSID", Const, 0, ""}, {"SYS_GETSOCKNAME", Const, 0, ""}, {"SYS_GETSOCKOPT", Const, 0, ""}, {"SYS_GETTHRID", Const, 1, ""}, {"SYS_GETTID", Const, 0, ""}, {"SYS_GETTIMEOFDAY", Const, 0, ""}, {"SYS_GETUID", Const, 0, ""}, {"SYS_GETUID32", Const, 0, ""}, {"SYS_GETVFSSTAT", Const, 1, ""}, {"SYS_GETWGROUPS", Const, 0, ""}, {"SYS_GETXATTR", Const, 0, ""}, {"SYS_GET_KERNEL_SYMS", Const, 0, ""}, {"SYS_GET_MEMPOLICY", Const, 0, ""}, {"SYS_GET_ROBUST_LIST", Const, 0, ""}, {"SYS_GET_THREAD_AREA", Const, 0, ""}, {"SYS_GSSD_SYSCALL", Const, 14, ""}, {"SYS_GTTY", Const, 0, ""}, {"SYS_IDENTITYSVC", Const, 0, ""}, {"SYS_IDLE", Const, 0, ""}, {"SYS_INITGROUPS", Const, 0, ""}, {"SYS_INIT_MODULE", Const, 0, ""}, {"SYS_INOTIFY_ADD_WATCH", Const, 0, ""}, {"SYS_INOTIFY_INIT", Const, 0, ""}, {"SYS_INOTIFY_INIT1", Const, 0, ""}, {"SYS_INOTIFY_RM_WATCH", Const, 0, ""}, {"SYS_IOCTL", Const, 0, ""}, {"SYS_IOPERM", Const, 0, ""}, {"SYS_IOPL", Const, 0, ""}, {"SYS_IOPOLICYSYS", Const, 0, ""}, {"SYS_IOPRIO_GET", Const, 0, ""}, {"SYS_IOPRIO_SET", Const, 0, ""}, {"SYS_IO_CANCEL", Const, 0, ""}, {"SYS_IO_DESTROY", Const, 0, ""}, {"SYS_IO_GETEVENTS", Const, 0, ""}, {"SYS_IO_SETUP", Const, 0, ""}, {"SYS_IO_SUBMIT", Const, 0, ""}, {"SYS_IPC", Const, 0, ""}, {"SYS_ISSETUGID", Const, 0, ""}, {"SYS_JAIL", Const, 0, ""}, {"SYS_JAIL_ATTACH", Const, 0, ""}, {"SYS_JAIL_GET", Const, 0, ""}, {"SYS_JAIL_REMOVE", Const, 0, ""}, {"SYS_JAIL_SET", Const, 0, ""}, {"SYS_KAS_INFO", Const, 16, ""}, {"SYS_KDEBUG_TRACE", Const, 0, ""}, {"SYS_KENV", Const, 0, ""}, {"SYS_KEVENT", Const, 0, ""}, {"SYS_KEVENT64", Const, 0, ""}, {"SYS_KEXEC_LOAD", Const, 0, ""}, {"SYS_KEYCTL", Const, 0, ""}, {"SYS_KILL", Const, 0, ""}, {"SYS_KLDFIND", Const, 0, ""}, {"SYS_KLDFIRSTMOD", Const, 0, ""}, {"SYS_KLDLOAD", Const, 0, ""}, {"SYS_KLDNEXT", Const, 0, ""}, {"SYS_KLDSTAT", Const, 0, ""}, {"SYS_KLDSYM", Const, 0, ""}, {"SYS_KLDUNLOAD", Const, 0, ""}, {"SYS_KLDUNLOADF", Const, 0, ""}, {"SYS_KMQ_NOTIFY", Const, 14, ""}, {"SYS_KMQ_OPEN", Const, 14, ""}, {"SYS_KMQ_SETATTR", Const, 14, ""}, {"SYS_KMQ_TIMEDRECEIVE", Const, 14, ""}, {"SYS_KMQ_TIMEDSEND", Const, 14, ""}, {"SYS_KMQ_UNLINK", Const, 14, ""}, {"SYS_KQUEUE", Const, 0, ""}, {"SYS_KQUEUE1", Const, 1, ""}, {"SYS_KSEM_CLOSE", Const, 14, ""}, {"SYS_KSEM_DESTROY", Const, 14, ""}, {"SYS_KSEM_GETVALUE", Const, 14, ""}, {"SYS_KSEM_INIT", Const, 14, ""}, {"SYS_KSEM_OPEN", Const, 14, ""}, {"SYS_KSEM_POST", Const, 14, ""}, {"SYS_KSEM_TIMEDWAIT", Const, 14, ""}, {"SYS_KSEM_TRYWAIT", Const, 14, ""}, {"SYS_KSEM_UNLINK", Const, 14, ""}, {"SYS_KSEM_WAIT", Const, 14, ""}, {"SYS_KTIMER_CREATE", Const, 0, ""}, {"SYS_KTIMER_DELETE", Const, 0, ""}, {"SYS_KTIMER_GETOVERRUN", Const, 0, ""}, {"SYS_KTIMER_GETTIME", Const, 0, ""}, {"SYS_KTIMER_SETTIME", Const, 0, ""}, {"SYS_KTRACE", Const, 0, ""}, {"SYS_LCHFLAGS", Const, 0, ""}, {"SYS_LCHMOD", Const, 0, ""}, {"SYS_LCHOWN", Const, 0, ""}, {"SYS_LCHOWN32", Const, 0, ""}, {"SYS_LEDGER", Const, 16, ""}, {"SYS_LGETFH", Const, 0, ""}, {"SYS_LGETXATTR", Const, 0, ""}, {"SYS_LINK", Const, 0, ""}, {"SYS_LINKAT", Const, 0, ""}, {"SYS_LIO_LISTIO", Const, 0, ""}, {"SYS_LISTEN", Const, 0, ""}, {"SYS_LISTXATTR", Const, 0, ""}, {"SYS_LLISTXATTR", Const, 0, ""}, {"SYS_LOCK", Const, 0, ""}, {"SYS_LOOKUP_DCOOKIE", Const, 0, ""}, {"SYS_LPATHCONF", Const, 0, ""}, {"SYS_LREMOVEXATTR", Const, 0, ""}, {"SYS_LSEEK", Const, 0, ""}, {"SYS_LSETXATTR", Const, 0, ""}, {"SYS_LSTAT", Const, 0, ""}, {"SYS_LSTAT64", Const, 0, ""}, {"SYS_LSTAT64_EXTENDED", Const, 0, ""}, {"SYS_LSTATV", Const, 0, ""}, {"SYS_LSTAT_EXTENDED", Const, 0, ""}, {"SYS_LUTIMES", Const, 0, ""}, {"SYS_MAC_SYSCALL", Const, 0, ""}, {"SYS_MADVISE", Const, 0, ""}, {"SYS_MADVISE1", Const, 0, ""}, {"SYS_MAXSYSCALL", Const, 0, ""}, {"SYS_MBIND", Const, 0, ""}, {"SYS_MIGRATE_PAGES", Const, 0, ""}, {"SYS_MINCORE", Const, 0, ""}, {"SYS_MINHERIT", Const, 0, ""}, {"SYS_MKCOMPLEX", Const, 0, ""}, {"SYS_MKDIR", Const, 0, ""}, {"SYS_MKDIRAT", Const, 0, ""}, {"SYS_MKDIR_EXTENDED", Const, 0, ""}, {"SYS_MKFIFO", Const, 0, ""}, {"SYS_MKFIFOAT", Const, 0, ""}, {"SYS_MKFIFO_EXTENDED", Const, 0, ""}, {"SYS_MKNOD", Const, 0, ""}, {"SYS_MKNODAT", Const, 0, ""}, {"SYS_MLOCK", Const, 0, ""}, {"SYS_MLOCKALL", Const, 0, ""}, {"SYS_MMAP", Const, 0, ""}, {"SYS_MMAP2", Const, 0, ""}, {"SYS_MODCTL", Const, 1, ""}, {"SYS_MODFIND", Const, 0, ""}, {"SYS_MODFNEXT", Const, 0, ""}, {"SYS_MODIFY_LDT", Const, 0, ""}, {"SYS_MODNEXT", Const, 0, ""}, {"SYS_MODSTAT", Const, 0, ""}, {"SYS_MODWATCH", Const, 0, ""}, {"SYS_MOUNT", Const, 0, ""}, {"SYS_MOVE_PAGES", Const, 0, ""}, {"SYS_MPROTECT", Const, 0, ""}, {"SYS_MPX", Const, 0, ""}, {"SYS_MQUERY", Const, 1, ""}, {"SYS_MQ_GETSETATTR", Const, 0, ""}, {"SYS_MQ_NOTIFY", Const, 0, ""}, {"SYS_MQ_OPEN", Const, 0, ""}, {"SYS_MQ_TIMEDRECEIVE", Const, 0, ""}, {"SYS_MQ_TIMEDSEND", Const, 0, ""}, {"SYS_MQ_UNLINK", Const, 0, ""}, {"SYS_MREMAP", Const, 0, ""}, {"SYS_MSGCTL", Const, 0, ""}, {"SYS_MSGGET", Const, 0, ""}, {"SYS_MSGRCV", Const, 0, ""}, {"SYS_MSGRCV_NOCANCEL", Const, 0, ""}, {"SYS_MSGSND", Const, 0, ""}, {"SYS_MSGSND_NOCANCEL", Const, 0, ""}, {"SYS_MSGSYS", Const, 0, ""}, {"SYS_MSYNC", Const, 0, ""}, {"SYS_MSYNC_NOCANCEL", Const, 0, ""}, {"SYS_MUNLOCK", Const, 0, ""}, {"SYS_MUNLOCKALL", Const, 0, ""}, {"SYS_MUNMAP", Const, 0, ""}, {"SYS_NAME_TO_HANDLE_AT", Const, 0, ""}, {"SYS_NANOSLEEP", Const, 0, ""}, {"SYS_NEWFSTATAT", Const, 0, ""}, {"SYS_NFSCLNT", Const, 0, ""}, {"SYS_NFSSERVCTL", Const, 0, ""}, {"SYS_NFSSVC", Const, 0, ""}, {"SYS_NFSTAT", Const, 0, ""}, {"SYS_NICE", Const, 0, ""}, {"SYS_NLM_SYSCALL", Const, 14, ""}, {"SYS_NLSTAT", Const, 0, ""}, {"SYS_NMOUNT", Const, 0, ""}, {"SYS_NSTAT", Const, 0, ""}, {"SYS_NTP_ADJTIME", Const, 0, ""}, {"SYS_NTP_GETTIME", Const, 0, ""}, {"SYS_NUMA_GETAFFINITY", Const, 14, ""}, {"SYS_NUMA_SETAFFINITY", Const, 14, ""}, {"SYS_OABI_SYSCALL_BASE", Const, 0, ""}, {"SYS_OBREAK", Const, 0, ""}, {"SYS_OLDFSTAT", Const, 0, ""}, {"SYS_OLDLSTAT", Const, 0, ""}, {"SYS_OLDOLDUNAME", Const, 0, ""}, {"SYS_OLDSTAT", Const, 0, ""}, {"SYS_OLDUNAME", Const, 0, ""}, {"SYS_OPEN", Const, 0, ""}, {"SYS_OPENAT", Const, 0, ""}, {"SYS_OPENBSD_POLL", Const, 0, ""}, {"SYS_OPEN_BY_HANDLE_AT", Const, 0, ""}, {"SYS_OPEN_DPROTECTED_NP", Const, 16, ""}, {"SYS_OPEN_EXTENDED", Const, 0, ""}, {"SYS_OPEN_NOCANCEL", Const, 0, ""}, {"SYS_OVADVISE", Const, 0, ""}, {"SYS_PACCEPT", Const, 1, ""}, {"SYS_PATHCONF", Const, 0, ""}, {"SYS_PAUSE", Const, 0, ""}, {"SYS_PCICONFIG_IOBASE", Const, 0, ""}, {"SYS_PCICONFIG_READ", Const, 0, ""}, {"SYS_PCICONFIG_WRITE", Const, 0, ""}, {"SYS_PDFORK", Const, 0, ""}, {"SYS_PDGETPID", Const, 0, ""}, {"SYS_PDKILL", Const, 0, ""}, {"SYS_PERF_EVENT_OPEN", Const, 0, ""}, {"SYS_PERSONALITY", Const, 0, ""}, {"SYS_PID_HIBERNATE", Const, 0, ""}, {"SYS_PID_RESUME", Const, 0, ""}, {"SYS_PID_SHUTDOWN_SOCKETS", Const, 0, ""}, {"SYS_PID_SUSPEND", Const, 0, ""}, {"SYS_PIPE", Const, 0, ""}, {"SYS_PIPE2", Const, 0, ""}, {"SYS_PIVOT_ROOT", Const, 0, ""}, {"SYS_PMC_CONTROL", Const, 1, ""}, {"SYS_PMC_GET_INFO", Const, 1, ""}, {"SYS_POLL", Const, 0, ""}, {"SYS_POLLTS", Const, 1, ""}, {"SYS_POLL_NOCANCEL", Const, 0, ""}, {"SYS_POSIX_FADVISE", Const, 0, ""}, {"SYS_POSIX_FALLOCATE", Const, 0, ""}, {"SYS_POSIX_OPENPT", Const, 0, ""}, {"SYS_POSIX_SPAWN", Const, 0, ""}, {"SYS_PPOLL", Const, 0, ""}, {"SYS_PRCTL", Const, 0, ""}, {"SYS_PREAD", Const, 0, ""}, {"SYS_PREAD64", Const, 0, ""}, {"SYS_PREADV", Const, 0, ""}, {"SYS_PREAD_NOCANCEL", Const, 0, ""}, {"SYS_PRLIMIT64", Const, 0, ""}, {"SYS_PROCCTL", Const, 3, ""}, {"SYS_PROCESS_POLICY", Const, 0, ""}, {"SYS_PROCESS_VM_READV", Const, 0, ""}, {"SYS_PROCESS_VM_WRITEV", Const, 0, ""}, {"SYS_PROC_INFO", Const, 0, ""}, {"SYS_PROF", Const, 0, ""}, {"SYS_PROFIL", Const, 0, ""}, {"SYS_PSELECT", Const, 0, ""}, {"SYS_PSELECT6", Const, 0, ""}, {"SYS_PSET_ASSIGN", Const, 1, ""}, {"SYS_PSET_CREATE", Const, 1, ""}, {"SYS_PSET_DESTROY", Const, 1, ""}, {"SYS_PSYNCH_CVBROAD", Const, 0, ""}, {"SYS_PSYNCH_CVCLRPREPOST", Const, 0, ""}, {"SYS_PSYNCH_CVSIGNAL", Const, 0, ""}, {"SYS_PSYNCH_CVWAIT", Const, 0, ""}, {"SYS_PSYNCH_MUTEXDROP", Const, 0, ""}, {"SYS_PSYNCH_MUTEXWAIT", Const, 0, ""}, {"SYS_PSYNCH_RW_DOWNGRADE", Const, 0, ""}, {"SYS_PSYNCH_RW_LONGRDLOCK", Const, 0, ""}, {"SYS_PSYNCH_RW_RDLOCK", Const, 0, ""}, {"SYS_PSYNCH_RW_UNLOCK", Const, 0, ""}, {"SYS_PSYNCH_RW_UNLOCK2", Const, 0, ""}, {"SYS_PSYNCH_RW_UPGRADE", Const, 0, ""}, {"SYS_PSYNCH_RW_WRLOCK", Const, 0, ""}, {"SYS_PSYNCH_RW_YIELDWRLOCK", Const, 0, ""}, {"SYS_PTRACE", Const, 0, ""}, {"SYS_PUTPMSG", Const, 0, ""}, {"SYS_PWRITE", Const, 0, ""}, {"SYS_PWRITE64", Const, 0, ""}, {"SYS_PWRITEV", Const, 0, ""}, {"SYS_PWRITE_NOCANCEL", Const, 0, ""}, {"SYS_QUERY_MODULE", Const, 0, ""}, {"SYS_QUOTACTL", Const, 0, ""}, {"SYS_RASCTL", Const, 1, ""}, {"SYS_RCTL_ADD_RULE", Const, 0, ""}, {"SYS_RCTL_GET_LIMITS", Const, 0, ""}, {"SYS_RCTL_GET_RACCT", Const, 0, ""}, {"SYS_RCTL_GET_RULES", Const, 0, ""}, {"SYS_RCTL_REMOVE_RULE", Const, 0, ""}, {"SYS_READ", Const, 0, ""}, {"SYS_READAHEAD", Const, 0, ""}, {"SYS_READDIR", Const, 0, ""}, {"SYS_READLINK", Const, 0, ""}, {"SYS_READLINKAT", Const, 0, ""}, {"SYS_READV", Const, 0, ""}, {"SYS_READV_NOCANCEL", Const, 0, ""}, {"SYS_READ_NOCANCEL", Const, 0, ""}, {"SYS_REBOOT", Const, 0, ""}, {"SYS_RECV", Const, 0, ""}, {"SYS_RECVFROM", Const, 0, ""}, {"SYS_RECVFROM_NOCANCEL", Const, 0, ""}, {"SYS_RECVMMSG", Const, 0, ""}, {"SYS_RECVMSG", Const, 0, ""}, {"SYS_RECVMSG_NOCANCEL", Const, 0, ""}, {"SYS_REMAP_FILE_PAGES", Const, 0, ""}, {"SYS_REMOVEXATTR", Const, 0, ""}, {"SYS_RENAME", Const, 0, ""}, {"SYS_RENAMEAT", Const, 0, ""}, {"SYS_REQUEST_KEY", Const, 0, ""}, {"SYS_RESTART_SYSCALL", Const, 0, ""}, {"SYS_REVOKE", Const, 0, ""}, {"SYS_RFORK", Const, 0, ""}, {"SYS_RMDIR", Const, 0, ""}, {"SYS_RTPRIO", Const, 0, ""}, {"SYS_RTPRIO_THREAD", Const, 0, ""}, {"SYS_RT_SIGACTION", Const, 0, ""}, {"SYS_RT_SIGPENDING", Const, 0, ""}, {"SYS_RT_SIGPROCMASK", Const, 0, ""}, {"SYS_RT_SIGQUEUEINFO", Const, 0, ""}, {"SYS_RT_SIGRETURN", Const, 0, ""}, {"SYS_RT_SIGSUSPEND", Const, 0, ""}, {"SYS_RT_SIGTIMEDWAIT", Const, 0, ""}, {"SYS_RT_TGSIGQUEUEINFO", Const, 0, ""}, {"SYS_SBRK", Const, 0, ""}, {"SYS_SCHED_GETAFFINITY", Const, 0, ""}, {"SYS_SCHED_GETPARAM", Const, 0, ""}, {"SYS_SCHED_GETSCHEDULER", Const, 0, ""}, {"SYS_SCHED_GET_PRIORITY_MAX", Const, 0, ""}, {"SYS_SCHED_GET_PRIORITY_MIN", Const, 0, ""}, {"SYS_SCHED_RR_GET_INTERVAL", Const, 0, ""}, {"SYS_SCHED_SETAFFINITY", Const, 0, ""}, {"SYS_SCHED_SETPARAM", Const, 0, ""}, {"SYS_SCHED_SETSCHEDULER", Const, 0, ""}, {"SYS_SCHED_YIELD", Const, 0, ""}, {"SYS_SCTP_GENERIC_RECVMSG", Const, 0, ""}, {"SYS_SCTP_GENERIC_SENDMSG", Const, 0, ""}, {"SYS_SCTP_GENERIC_SENDMSG_IOV", Const, 0, ""}, {"SYS_SCTP_PEELOFF", Const, 0, ""}, {"SYS_SEARCHFS", Const, 0, ""}, {"SYS_SECURITY", Const, 0, ""}, {"SYS_SELECT", Const, 0, ""}, {"SYS_SELECT_NOCANCEL", Const, 0, ""}, {"SYS_SEMCONFIG", Const, 1, ""}, {"SYS_SEMCTL", Const, 0, ""}, {"SYS_SEMGET", Const, 0, ""}, {"SYS_SEMOP", Const, 0, ""}, {"SYS_SEMSYS", Const, 0, ""}, {"SYS_SEMTIMEDOP", Const, 0, ""}, {"SYS_SEM_CLOSE", Const, 0, ""}, {"SYS_SEM_DESTROY", Const, 0, ""}, {"SYS_SEM_GETVALUE", Const, 0, ""}, {"SYS_SEM_INIT", Const, 0, ""}, {"SYS_SEM_OPEN", Const, 0, ""}, {"SYS_SEM_POST", Const, 0, ""}, {"SYS_SEM_TRYWAIT", Const, 0, ""}, {"SYS_SEM_UNLINK", Const, 0, ""}, {"SYS_SEM_WAIT", Const, 0, ""}, {"SYS_SEM_WAIT_NOCANCEL", Const, 0, ""}, {"SYS_SEND", Const, 0, ""}, {"SYS_SENDFILE", Const, 0, ""}, {"SYS_SENDFILE64", Const, 0, ""}, {"SYS_SENDMMSG", Const, 0, ""}, {"SYS_SENDMSG", Const, 0, ""}, {"SYS_SENDMSG_NOCANCEL", Const, 0, ""}, {"SYS_SENDTO", Const, 0, ""}, {"SYS_SENDTO_NOCANCEL", Const, 0, ""}, {"SYS_SETATTRLIST", Const, 0, ""}, {"SYS_SETAUDIT", Const, 0, ""}, {"SYS_SETAUDIT_ADDR", Const, 0, ""}, {"SYS_SETAUID", Const, 0, ""}, {"SYS_SETCONTEXT", Const, 0, ""}, {"SYS_SETDOMAINNAME", Const, 0, ""}, {"SYS_SETEGID", Const, 0, ""}, {"SYS_SETEUID", Const, 0, ""}, {"SYS_SETFIB", Const, 0, ""}, {"SYS_SETFSGID", Const, 0, ""}, {"SYS_SETFSGID32", Const, 0, ""}, {"SYS_SETFSUID", Const, 0, ""}, {"SYS_SETFSUID32", Const, 0, ""}, {"SYS_SETGID", Const, 0, ""}, {"SYS_SETGID32", Const, 0, ""}, {"SYS_SETGROUPS", Const, 0, ""}, {"SYS_SETGROUPS32", Const, 0, ""}, {"SYS_SETHOSTNAME", Const, 0, ""}, {"SYS_SETITIMER", Const, 0, ""}, {"SYS_SETLCID", Const, 0, ""}, {"SYS_SETLOGIN", Const, 0, ""}, {"SYS_SETLOGINCLASS", Const, 0, ""}, {"SYS_SETNS", Const, 0, ""}, {"SYS_SETPGID", Const, 0, ""}, {"SYS_SETPRIORITY", Const, 0, ""}, {"SYS_SETPRIVEXEC", Const, 0, ""}, {"SYS_SETREGID", Const, 0, ""}, {"SYS_SETREGID32", Const, 0, ""}, {"SYS_SETRESGID", Const, 0, ""}, {"SYS_SETRESGID32", Const, 0, ""}, {"SYS_SETRESUID", Const, 0, ""}, {"SYS_SETRESUID32", Const, 0, ""}, {"SYS_SETREUID", Const, 0, ""}, {"SYS_SETREUID32", Const, 0, ""}, {"SYS_SETRLIMIT", Const, 0, ""}, {"SYS_SETRTABLE", Const, 1, ""}, {"SYS_SETSGROUPS", Const, 0, ""}, {"SYS_SETSID", Const, 0, ""}, {"SYS_SETSOCKOPT", Const, 0, ""}, {"SYS_SETTID", Const, 0, ""}, {"SYS_SETTID_WITH_PID", Const, 0, ""}, {"SYS_SETTIMEOFDAY", Const, 0, ""}, {"SYS_SETUID", Const, 0, ""}, {"SYS_SETUID32", Const, 0, ""}, {"SYS_SETWGROUPS", Const, 0, ""}, {"SYS_SETXATTR", Const, 0, ""}, {"SYS_SET_MEMPOLICY", Const, 0, ""}, {"SYS_SET_ROBUST_LIST", Const, 0, ""}, {"SYS_SET_THREAD_AREA", Const, 0, ""}, {"SYS_SET_TID_ADDRESS", Const, 0, ""}, {"SYS_SGETMASK", Const, 0, ""}, {"SYS_SHARED_REGION_CHECK_NP", Const, 0, ""}, {"SYS_SHARED_REGION_MAP_AND_SLIDE_NP", Const, 0, ""}, {"SYS_SHMAT", Const, 0, ""}, {"SYS_SHMCTL", Const, 0, ""}, {"SYS_SHMDT", Const, 0, ""}, {"SYS_SHMGET", Const, 0, ""}, {"SYS_SHMSYS", Const, 0, ""}, {"SYS_SHM_OPEN", Const, 0, ""}, {"SYS_SHM_UNLINK", Const, 0, ""}, {"SYS_SHUTDOWN", Const, 0, ""}, {"SYS_SIGACTION", Const, 0, ""}, {"SYS_SIGALTSTACK", Const, 0, ""}, {"SYS_SIGNAL", Const, 0, ""}, {"SYS_SIGNALFD", Const, 0, ""}, {"SYS_SIGNALFD4", Const, 0, ""}, {"SYS_SIGPENDING", Const, 0, ""}, {"SYS_SIGPROCMASK", Const, 0, ""}, {"SYS_SIGQUEUE", Const, 0, ""}, {"SYS_SIGQUEUEINFO", Const, 1, ""}, {"SYS_SIGRETURN", Const, 0, ""}, {"SYS_SIGSUSPEND", Const, 0, ""}, {"SYS_SIGSUSPEND_NOCANCEL", Const, 0, ""}, {"SYS_SIGTIMEDWAIT", Const, 0, ""}, {"SYS_SIGWAIT", Const, 0, ""}, {"SYS_SIGWAITINFO", Const, 0, ""}, {"SYS_SOCKET", Const, 0, ""}, {"SYS_SOCKETCALL", Const, 0, ""}, {"SYS_SOCKETPAIR", Const, 0, ""}, {"SYS_SPLICE", Const, 0, ""}, {"SYS_SSETMASK", Const, 0, ""}, {"SYS_SSTK", Const, 0, ""}, {"SYS_STACK_SNAPSHOT", Const, 0, ""}, {"SYS_STAT", Const, 0, ""}, {"SYS_STAT64", Const, 0, ""}, {"SYS_STAT64_EXTENDED", Const, 0, ""}, {"SYS_STATFS", Const, 0, ""}, {"SYS_STATFS64", Const, 0, ""}, {"SYS_STATV", Const, 0, ""}, {"SYS_STATVFS1", Const, 1, ""}, {"SYS_STAT_EXTENDED", Const, 0, ""}, {"SYS_STIME", Const, 0, ""}, {"SYS_STTY", Const, 0, ""}, {"SYS_SWAPCONTEXT", Const, 0, ""}, {"SYS_SWAPCTL", Const, 1, ""}, {"SYS_SWAPOFF", Const, 0, ""}, {"SYS_SWAPON", Const, 0, ""}, {"SYS_SYMLINK", Const, 0, ""}, {"SYS_SYMLINKAT", Const, 0, ""}, {"SYS_SYNC", Const, 0, ""}, {"SYS_SYNCFS", Const, 0, ""}, {"SYS_SYNC_FILE_RANGE", Const, 0, ""}, {"SYS_SYSARCH", Const, 0, ""}, {"SYS_SYSCALL", Const, 0, ""}, {"SYS_SYSCALL_BASE", Const, 0, ""}, {"SYS_SYSFS", Const, 0, ""}, {"SYS_SYSINFO", Const, 0, ""}, {"SYS_SYSLOG", Const, 0, ""}, {"SYS_TEE", Const, 0, ""}, {"SYS_TGKILL", Const, 0, ""}, {"SYS_THREAD_SELFID", Const, 0, ""}, {"SYS_THR_CREATE", Const, 0, ""}, {"SYS_THR_EXIT", Const, 0, ""}, {"SYS_THR_KILL", Const, 0, ""}, {"SYS_THR_KILL2", Const, 0, ""}, {"SYS_THR_NEW", Const, 0, ""}, {"SYS_THR_SELF", Const, 0, ""}, {"SYS_THR_SET_NAME", Const, 0, ""}, {"SYS_THR_SUSPEND", Const, 0, ""}, {"SYS_THR_WAKE", Const, 0, ""}, {"SYS_TIME", Const, 0, ""}, {"SYS_TIMERFD_CREATE", Const, 0, ""}, {"SYS_TIMERFD_GETTIME", Const, 0, ""}, {"SYS_TIMERFD_SETTIME", Const, 0, ""}, {"SYS_TIMER_CREATE", Const, 0, ""}, {"SYS_TIMER_DELETE", Const, 0, ""}, {"SYS_TIMER_GETOVERRUN", Const, 0, ""}, {"SYS_TIMER_GETTIME", Const, 0, ""}, {"SYS_TIMER_SETTIME", Const, 0, ""}, {"SYS_TIMES", Const, 0, ""}, {"SYS_TKILL", Const, 0, ""}, {"SYS_TRUNCATE", Const, 0, ""}, {"SYS_TRUNCATE64", Const, 0, ""}, {"SYS_TUXCALL", Const, 0, ""}, {"SYS_UGETRLIMIT", Const, 0, ""}, {"SYS_ULIMIT", Const, 0, ""}, {"SYS_UMASK", Const, 0, ""}, {"SYS_UMASK_EXTENDED", Const, 0, ""}, {"SYS_UMOUNT", Const, 0, ""}, {"SYS_UMOUNT2", Const, 0, ""}, {"SYS_UNAME", Const, 0, ""}, {"SYS_UNDELETE", Const, 0, ""}, {"SYS_UNLINK", Const, 0, ""}, {"SYS_UNLINKAT", Const, 0, ""}, {"SYS_UNMOUNT", Const, 0, ""}, {"SYS_UNSHARE", Const, 0, ""}, {"SYS_USELIB", Const, 0, ""}, {"SYS_USTAT", Const, 0, ""}, {"SYS_UTIME", Const, 0, ""}, {"SYS_UTIMENSAT", Const, 0, ""}, {"SYS_UTIMES", Const, 0, ""}, {"SYS_UTRACE", Const, 0, ""}, {"SYS_UUIDGEN", Const, 0, ""}, {"SYS_VADVISE", Const, 1, ""}, {"SYS_VFORK", Const, 0, ""}, {"SYS_VHANGUP", Const, 0, ""}, {"SYS_VM86", Const, 0, ""}, {"SYS_VM86OLD", Const, 0, ""}, {"SYS_VMSPLICE", Const, 0, ""}, {"SYS_VM_PRESSURE_MONITOR", Const, 0, ""}, {"SYS_VSERVER", Const, 0, ""}, {"SYS_WAIT4", Const, 0, ""}, {"SYS_WAIT4_NOCANCEL", Const, 0, ""}, {"SYS_WAIT6", Const, 1, ""}, {"SYS_WAITEVENT", Const, 0, ""}, {"SYS_WAITID", Const, 0, ""}, {"SYS_WAITID_NOCANCEL", Const, 0, ""}, {"SYS_WAITPID", Const, 0, ""}, {"SYS_WATCHEVENT", Const, 0, ""}, {"SYS_WORKQ_KERNRETURN", Const, 0, ""}, {"SYS_WORKQ_OPEN", Const, 0, ""}, {"SYS_WRITE", Const, 0, ""}, {"SYS_WRITEV", Const, 0, ""}, {"SYS_WRITEV_NOCANCEL", Const, 0, ""}, {"SYS_WRITE_NOCANCEL", Const, 0, ""}, {"SYS_YIELD", Const, 0, ""}, {"SYS__LLSEEK", Const, 0, ""}, {"SYS__LWP_CONTINUE", Const, 1, ""}, {"SYS__LWP_CREATE", Const, 1, ""}, {"SYS__LWP_CTL", Const, 1, ""}, {"SYS__LWP_DETACH", Const, 1, ""}, {"SYS__LWP_EXIT", Const, 1, ""}, {"SYS__LWP_GETNAME", Const, 1, ""}, {"SYS__LWP_GETPRIVATE", Const, 1, ""}, {"SYS__LWP_KILL", Const, 1, ""}, {"SYS__LWP_PARK", Const, 1, ""}, {"SYS__LWP_SELF", Const, 1, ""}, {"SYS__LWP_SETNAME", Const, 1, ""}, {"SYS__LWP_SETPRIVATE", Const, 1, ""}, {"SYS__LWP_SUSPEND", Const, 1, ""}, {"SYS__LWP_UNPARK", Const, 1, ""}, {"SYS__LWP_UNPARK_ALL", Const, 1, ""}, {"SYS__LWP_WAIT", Const, 1, ""}, {"SYS__LWP_WAKEUP", Const, 1, ""}, {"SYS__NEWSELECT", Const, 0, ""}, {"SYS__PSET_BIND", Const, 1, ""}, {"SYS__SCHED_GETAFFINITY", Const, 1, ""}, {"SYS__SCHED_GETPARAM", Const, 1, ""}, {"SYS__SCHED_SETAFFINITY", Const, 1, ""}, {"SYS__SCHED_SETPARAM", Const, 1, ""}, {"SYS__SYSCTL", Const, 0, ""}, {"SYS__UMTX_LOCK", Const, 0, ""}, {"SYS__UMTX_OP", Const, 0, ""}, {"SYS__UMTX_UNLOCK", Const, 0, ""}, {"SYS___ACL_ACLCHECK_FD", Const, 0, ""}, {"SYS___ACL_ACLCHECK_FILE", Const, 0, ""}, {"SYS___ACL_ACLCHECK_LINK", Const, 0, ""}, {"SYS___ACL_DELETE_FD", Const, 0, ""}, {"SYS___ACL_DELETE_FILE", Const, 0, ""}, {"SYS___ACL_DELETE_LINK", Const, 0, ""}, {"SYS___ACL_GET_FD", Const, 0, ""}, {"SYS___ACL_GET_FILE", Const, 0, ""}, {"SYS___ACL_GET_LINK", Const, 0, ""}, {"SYS___ACL_SET_FD", Const, 0, ""}, {"SYS___ACL_SET_FILE", Const, 0, ""}, {"SYS___ACL_SET_LINK", Const, 0, ""}, {"SYS___CAP_RIGHTS_GET", Const, 14, ""}, {"SYS___CLONE", Const, 1, ""}, {"SYS___DISABLE_THREADSIGNAL", Const, 0, ""}, {"SYS___GETCWD", Const, 0, ""}, {"SYS___GETLOGIN", Const, 1, ""}, {"SYS___GET_TCB", Const, 1, ""}, {"SYS___MAC_EXECVE", Const, 0, ""}, {"SYS___MAC_GETFSSTAT", Const, 0, ""}, {"SYS___MAC_GET_FD", Const, 0, ""}, {"SYS___MAC_GET_FILE", Const, 0, ""}, {"SYS___MAC_GET_LCID", Const, 0, ""}, {"SYS___MAC_GET_LCTX", Const, 0, ""}, {"SYS___MAC_GET_LINK", Const, 0, ""}, {"SYS___MAC_GET_MOUNT", Const, 0, ""}, {"SYS___MAC_GET_PID", Const, 0, ""}, {"SYS___MAC_GET_PROC", Const, 0, ""}, {"SYS___MAC_MOUNT", Const, 0, ""}, {"SYS___MAC_SET_FD", Const, 0, ""}, {"SYS___MAC_SET_FILE", Const, 0, ""}, {"SYS___MAC_SET_LCTX", Const, 0, ""}, {"SYS___MAC_SET_LINK", Const, 0, ""}, {"SYS___MAC_SET_PROC", Const, 0, ""}, {"SYS___MAC_SYSCALL", Const, 0, ""}, {"SYS___OLD_SEMWAIT_SIGNAL", Const, 0, ""}, {"SYS___OLD_SEMWAIT_SIGNAL_NOCANCEL", Const, 0, ""}, {"SYS___POSIX_CHOWN", Const, 1, ""}, {"SYS___POSIX_FCHOWN", Const, 1, ""}, {"SYS___POSIX_LCHOWN", Const, 1, ""}, {"SYS___POSIX_RENAME", Const, 1, ""}, {"SYS___PTHREAD_CANCELED", Const, 0, ""}, {"SYS___PTHREAD_CHDIR", Const, 0, ""}, {"SYS___PTHREAD_FCHDIR", Const, 0, ""}, {"SYS___PTHREAD_KILL", Const, 0, ""}, {"SYS___PTHREAD_MARKCANCEL", Const, 0, ""}, {"SYS___PTHREAD_SIGMASK", Const, 0, ""}, {"SYS___QUOTACTL", Const, 1, ""}, {"SYS___SEMCTL", Const, 1, ""}, {"SYS___SEMWAIT_SIGNAL", Const, 0, ""}, {"SYS___SEMWAIT_SIGNAL_NOCANCEL", Const, 0, ""}, {"SYS___SETLOGIN", Const, 1, ""}, {"SYS___SETUGID", Const, 0, ""}, {"SYS___SET_TCB", Const, 1, ""}, {"SYS___SIGACTION_SIGTRAMP", Const, 1, ""}, {"SYS___SIGTIMEDWAIT", Const, 1, ""}, {"SYS___SIGWAIT", Const, 0, ""}, {"SYS___SIGWAIT_NOCANCEL", Const, 0, ""}, {"SYS___SYSCTL", Const, 0, ""}, {"SYS___TFORK", Const, 1, ""}, {"SYS___THREXIT", Const, 1, ""}, {"SYS___THRSIGDIVERT", Const, 1, ""}, {"SYS___THRSLEEP", Const, 1, ""}, {"SYS___THRWAKEUP", Const, 1, ""}, {"S_ARCH1", Const, 1, ""}, {"S_ARCH2", Const, 1, ""}, {"S_BLKSIZE", Const, 0, ""}, {"S_IEXEC", Const, 0, ""}, {"S_IFBLK", Const, 0, ""}, {"S_IFCHR", Const, 0, ""}, {"S_IFDIR", Const, 0, ""}, {"S_IFIFO", Const, 0, ""}, {"S_IFLNK", Const, 0, ""}, {"S_IFMT", Const, 0, ""}, {"S_IFREG", Const, 0, ""}, {"S_IFSOCK", Const, 0, ""}, {"S_IFWHT", Const, 0, ""}, {"S_IREAD", Const, 0, ""}, {"S_IRGRP", Const, 0, ""}, {"S_IROTH", Const, 0, ""}, {"S_IRUSR", Const, 0, ""}, {"S_IRWXG", Const, 0, ""}, {"S_IRWXO", Const, 0, ""}, {"S_IRWXU", Const, 0, ""}, {"S_ISGID", Const, 0, ""}, {"S_ISTXT", Const, 0, ""}, {"S_ISUID", Const, 0, ""}, {"S_ISVTX", Const, 0, ""}, {"S_IWGRP", Const, 0, ""}, {"S_IWOTH", Const, 0, ""}, {"S_IWRITE", Const, 0, ""}, {"S_IWUSR", Const, 0, ""}, {"S_IXGRP", Const, 0, ""}, {"S_IXOTH", Const, 0, ""}, {"S_IXUSR", Const, 0, ""}, {"S_LOGIN_SET", Const, 1, ""}, {"SecurityAttributes", Type, 0, ""}, {"SecurityAttributes.InheritHandle", Field, 0, ""}, {"SecurityAttributes.Length", Field, 0, ""}, {"SecurityAttributes.SecurityDescriptor", Field, 0, ""}, {"Seek", Func, 0, "func(fd int, offset int64, whence int) (off int64, err error)"}, {"Select", Func, 0, "func(nfd int, r *FdSet, w *FdSet, e *FdSet, timeout *Timeval) (n int, err error)"}, {"Sendfile", Func, 0, "func(outfd int, infd int, offset *int64, count int) (written int, err error)"}, {"Sendmsg", Func, 0, "func(fd int, p []byte, oob []byte, to Sockaddr, flags int) (err error)"}, {"SendmsgN", Func, 3, "func(fd int, p []byte, oob []byte, to Sockaddr, flags int) (n int, err error)"}, {"Sendto", Func, 0, "func(fd int, p []byte, flags int, to Sockaddr) (err error)"}, {"Servent", Type, 0, ""}, {"Servent.Aliases", Field, 0, ""}, {"Servent.Name", Field, 0, ""}, {"Servent.Port", Field, 0, ""}, {"Servent.Proto", Field, 0, ""}, {"SetBpf", Func, 0, ""}, {"SetBpfBuflen", Func, 0, ""}, {"SetBpfDatalink", Func, 0, ""}, {"SetBpfHeadercmpl", Func, 0, ""}, {"SetBpfImmediate", Func, 0, ""}, {"SetBpfInterface", Func, 0, ""}, {"SetBpfPromisc", Func, 0, ""}, {"SetBpfTimeout", Func, 0, ""}, {"SetCurrentDirectory", Func, 0, ""}, {"SetEndOfFile", Func, 0, ""}, {"SetEnvironmentVariable", Func, 0, ""}, {"SetFileAttributes", Func, 0, ""}, {"SetFileCompletionNotificationModes", Func, 2, ""}, {"SetFilePointer", Func, 0, ""}, {"SetFileTime", Func, 0, ""}, {"SetHandleInformation", Func, 0, ""}, {"SetKevent", Func, 0, ""}, {"SetLsfPromisc", Func, 0, "func(name string, m bool) error"}, {"SetNonblock", Func, 0, "func(fd int, nonblocking bool) (err error)"}, {"Setdomainname", Func, 0, "func(p []byte) (err error)"}, {"Setegid", Func, 0, "func(egid int) (err error)"}, {"Setenv", Func, 0, "func(key string, value string) error"}, {"Seteuid", Func, 0, "func(euid int) (err error)"}, {"Setfsgid", Func, 0, "func(gid int) (err error)"}, {"Setfsuid", Func, 0, "func(uid int) (err error)"}, {"Setgid", Func, 0, "func(gid int) (err error)"}, {"Setgroups", Func, 0, "func(gids []int) (err error)"}, {"Sethostname", Func, 0, "func(p []byte) (err error)"}, {"Setlogin", Func, 0, ""}, {"Setpgid", Func, 0, "func(pid int, pgid int) (err error)"}, {"Setpriority", Func, 0, "func(which int, who int, prio int) (err error)"}, {"Setprivexec", Func, 0, ""}, {"Setregid", Func, 0, "func(rgid int, egid int) (err error)"}, {"Setresgid", Func, 0, "func(rgid int, egid int, sgid int) (err error)"}, {"Setresuid", Func, 0, "func(ruid int, euid int, suid int) (err error)"}, {"Setreuid", Func, 0, "func(ruid int, euid int) (err error)"}, {"Setrlimit", Func, 0, "func(resource int, rlim *Rlimit) error"}, {"Setsid", Func, 0, "func() (pid int, err error)"}, {"Setsockopt", Func, 0, ""}, {"SetsockoptByte", Func, 0, "func(fd int, level int, opt int, value byte) (err error)"}, {"SetsockoptICMPv6Filter", Func, 2, "func(fd int, level int, opt int, filter *ICMPv6Filter) error"}, {"SetsockoptIPMreq", Func, 0, "func(fd int, level int, opt int, mreq *IPMreq) (err error)"}, {"SetsockoptIPMreqn", Func, 0, "func(fd int, level int, opt int, mreq *IPMreqn) (err error)"}, {"SetsockoptIPv6Mreq", Func, 0, "func(fd int, level int, opt int, mreq *IPv6Mreq) (err error)"}, {"SetsockoptInet4Addr", Func, 0, "func(fd int, level int, opt int, value [4]byte) (err error)"}, {"SetsockoptInt", Func, 0, "func(fd int, level int, opt int, value int) (err error)"}, {"SetsockoptLinger", Func, 0, "func(fd int, level int, opt int, l *Linger) (err error)"}, {"SetsockoptString", Func, 0, "func(fd int, level int, opt int, s string) (err error)"}, {"SetsockoptTimeval", Func, 0, "func(fd int, level int, opt int, tv *Timeval) (err error)"}, {"Settimeofday", Func, 0, "func(tv *Timeval) (err error)"}, {"Setuid", Func, 0, "func(uid int) (err error)"}, {"Setxattr", Func, 1, "func(path string, attr string, data []byte, flags int) (err error)"}, {"Shutdown", Func, 0, "func(fd int, how int) (err error)"}, {"SidTypeAlias", Const, 0, ""}, {"SidTypeComputer", Const, 0, ""}, {"SidTypeDeletedAccount", Const, 0, ""}, {"SidTypeDomain", Const, 0, ""}, {"SidTypeGroup", Const, 0, ""}, {"SidTypeInvalid", Const, 0, ""}, {"SidTypeLabel", Const, 0, ""}, {"SidTypeUnknown", Const, 0, ""}, {"SidTypeUser", Const, 0, ""}, {"SidTypeWellKnownGroup", Const, 0, ""}, {"Signal", Type, 0, ""}, {"SizeofBpfHdr", Const, 0, ""}, {"SizeofBpfInsn", Const, 0, ""}, {"SizeofBpfProgram", Const, 0, ""}, {"SizeofBpfStat", Const, 0, ""}, {"SizeofBpfVersion", Const, 0, ""}, {"SizeofBpfZbuf", Const, 0, ""}, {"SizeofBpfZbufHeader", Const, 0, ""}, {"SizeofCmsghdr", Const, 0, ""}, {"SizeofICMPv6Filter", Const, 2, ""}, {"SizeofIPMreq", Const, 0, ""}, {"SizeofIPMreqn", Const, 0, ""}, {"SizeofIPv6MTUInfo", Const, 2, ""}, {"SizeofIPv6Mreq", Const, 0, ""}, {"SizeofIfAddrmsg", Const, 0, ""}, {"SizeofIfAnnounceMsghdr", Const, 1, ""}, {"SizeofIfData", Const, 0, ""}, {"SizeofIfInfomsg", Const, 0, ""}, {"SizeofIfMsghdr", Const, 0, ""}, {"SizeofIfaMsghdr", Const, 0, ""}, {"SizeofIfmaMsghdr", Const, 0, ""}, {"SizeofIfmaMsghdr2", Const, 0, ""}, {"SizeofInet4Pktinfo", Const, 0, ""}, {"SizeofInet6Pktinfo", Const, 0, ""}, {"SizeofInotifyEvent", Const, 0, ""}, {"SizeofLinger", Const, 0, ""}, {"SizeofMsghdr", Const, 0, ""}, {"SizeofNlAttr", Const, 0, ""}, {"SizeofNlMsgerr", Const, 0, ""}, {"SizeofNlMsghdr", Const, 0, ""}, {"SizeofRtAttr", Const, 0, ""}, {"SizeofRtGenmsg", Const, 0, ""}, {"SizeofRtMetrics", Const, 0, ""}, {"SizeofRtMsg", Const, 0, ""}, {"SizeofRtMsghdr", Const, 0, ""}, {"SizeofRtNexthop", Const, 0, ""}, {"SizeofSockFilter", Const, 0, ""}, {"SizeofSockFprog", Const, 0, ""}, {"SizeofSockaddrAny", Const, 0, ""}, {"SizeofSockaddrDatalink", Const, 0, ""}, {"SizeofSockaddrInet4", Const, 0, ""}, {"SizeofSockaddrInet6", Const, 0, ""}, {"SizeofSockaddrLinklayer", Const, 0, ""}, {"SizeofSockaddrNetlink", Const, 0, ""}, {"SizeofSockaddrUnix", Const, 0, ""}, {"SizeofTCPInfo", Const, 1, ""}, {"SizeofUcred", Const, 0, ""}, {"SlicePtrFromStrings", Func, 1, "func(ss []string) ([]*byte, error)"}, {"SockFilter", Type, 0, ""}, {"SockFilter.Code", Field, 0, ""}, {"SockFilter.Jf", Field, 0, ""}, {"SockFilter.Jt", Field, 0, ""}, {"SockFilter.K", Field, 0, ""}, {"SockFprog", Type, 0, ""}, {"SockFprog.Filter", Field, 0, ""}, {"SockFprog.Len", Field, 0, ""}, {"SockFprog.Pad_cgo_0", Field, 0, ""}, {"Sockaddr", Type, 0, ""}, {"SockaddrDatalink", Type, 0, ""}, {"SockaddrDatalink.Alen", Field, 0, ""}, {"SockaddrDatalink.Data", Field, 0, ""}, {"SockaddrDatalink.Family", Field, 0, ""}, {"SockaddrDatalink.Index", Field, 0, ""}, {"SockaddrDatalink.Len", Field, 0, ""}, {"SockaddrDatalink.Nlen", Field, 0, ""}, {"SockaddrDatalink.Slen", Field, 0, ""}, {"SockaddrDatalink.Type", Field, 0, ""}, {"SockaddrGen", Type, 0, ""}, {"SockaddrInet4", Type, 0, ""}, {"SockaddrInet4.Addr", Field, 0, ""}, {"SockaddrInet4.Port", Field, 0, ""}, {"SockaddrInet6", Type, 0, ""}, {"SockaddrInet6.Addr", Field, 0, ""}, {"SockaddrInet6.Port", Field, 0, ""}, {"SockaddrInet6.ZoneId", Field, 0, ""}, {"SockaddrLinklayer", Type, 0, ""}, {"SockaddrLinklayer.Addr", Field, 0, ""}, {"SockaddrLinklayer.Halen", Field, 0, ""}, {"SockaddrLinklayer.Hatype", Field, 0, ""}, {"SockaddrLinklayer.Ifindex", Field, 0, ""}, {"SockaddrLinklayer.Pkttype", Field, 0, ""}, {"SockaddrLinklayer.Protocol", Field, 0, ""}, {"SockaddrNetlink", Type, 0, ""}, {"SockaddrNetlink.Family", Field, 0, ""}, {"SockaddrNetlink.Groups", Field, 0, ""}, {"SockaddrNetlink.Pad", Field, 0, ""}, {"SockaddrNetlink.Pid", Field, 0, ""}, {"SockaddrUnix", Type, 0, ""}, {"SockaddrUnix.Name", Field, 0, ""}, {"Socket", Func, 0, "func(domain int, typ int, proto int) (fd int, err error)"}, {"SocketControlMessage", Type, 0, ""}, {"SocketControlMessage.Data", Field, 0, ""}, {"SocketControlMessage.Header", Field, 0, ""}, {"SocketDisableIPv6", Var, 0, ""}, {"Socketpair", Func, 0, "func(domain int, typ int, proto int) (fd [2]int, err error)"}, {"Splice", Func, 0, "func(rfd int, roff *int64, wfd int, woff *int64, len int, flags int) (n int64, err error)"}, {"StartProcess", Func, 0, "func(argv0 string, argv []string, attr *ProcAttr) (pid int, handle uintptr, err error)"}, {"StartupInfo", Type, 0, ""}, {"StartupInfo.Cb", Field, 0, ""}, {"StartupInfo.Desktop", Field, 0, ""}, {"StartupInfo.FillAttribute", Field, 0, ""}, {"StartupInfo.Flags", Field, 0, ""}, {"StartupInfo.ShowWindow", Field, 0, ""}, {"StartupInfo.StdErr", Field, 0, ""}, {"StartupInfo.StdInput", Field, 0, ""}, {"StartupInfo.StdOutput", Field, 0, ""}, {"StartupInfo.Title", Field, 0, ""}, {"StartupInfo.X", Field, 0, ""}, {"StartupInfo.XCountChars", Field, 0, ""}, {"StartupInfo.XSize", Field, 0, ""}, {"StartupInfo.Y", Field, 0, ""}, {"StartupInfo.YCountChars", Field, 0, ""}, {"StartupInfo.YSize", Field, 0, ""}, {"Stat", Func, 0, "func(path string, stat *Stat_t) (err error)"}, {"Stat_t", Type, 0, ""}, {"Stat_t.Atim", Field, 0, ""}, {"Stat_t.Atim_ext", Field, 12, ""}, {"Stat_t.Atimespec", Field, 0, ""}, {"Stat_t.Birthtimespec", Field, 0, ""}, {"Stat_t.Blksize", Field, 0, ""}, {"Stat_t.Blocks", Field, 0, ""}, {"Stat_t.Btim_ext", Field, 12, ""}, {"Stat_t.Ctim", Field, 0, ""}, {"Stat_t.Ctim_ext", Field, 12, ""}, {"Stat_t.Ctimespec", Field, 0, ""}, {"Stat_t.Dev", Field, 0, ""}, {"Stat_t.Flags", Field, 0, ""}, {"Stat_t.Gen", Field, 0, ""}, {"Stat_t.Gid", Field, 0, ""}, {"Stat_t.Ino", Field, 0, ""}, {"Stat_t.Lspare", Field, 0, ""}, {"Stat_t.Lspare0", Field, 2, ""}, {"Stat_t.Lspare1", Field, 2, ""}, {"Stat_t.Mode", Field, 0, ""}, {"Stat_t.Mtim", Field, 0, ""}, {"Stat_t.Mtim_ext", Field, 12, ""}, {"Stat_t.Mtimespec", Field, 0, ""}, {"Stat_t.Nlink", Field, 0, ""}, {"Stat_t.Pad_cgo_0", Field, 0, ""}, {"Stat_t.Pad_cgo_1", Field, 0, ""}, {"Stat_t.Pad_cgo_2", Field, 0, ""}, {"Stat_t.Padding0", Field, 12, ""}, {"Stat_t.Padding1", Field, 12, ""}, {"Stat_t.Qspare", Field, 0, ""}, {"Stat_t.Rdev", Field, 0, ""}, {"Stat_t.Size", Field, 0, ""}, {"Stat_t.Spare", Field, 2, ""}, {"Stat_t.Uid", Field, 0, ""}, {"Stat_t.X__pad0", Field, 0, ""}, {"Stat_t.X__pad1", Field, 0, ""}, {"Stat_t.X__pad2", Field, 0, ""}, {"Stat_t.X__st_birthtim", Field, 2, ""}, {"Stat_t.X__st_ino", Field, 0, ""}, {"Stat_t.X__unused", Field, 0, ""}, {"Statfs", Func, 0, "func(path string, buf *Statfs_t) (err error)"}, {"Statfs_t", Type, 0, ""}, {"Statfs_t.Asyncreads", Field, 0, ""}, {"Statfs_t.Asyncwrites", Field, 0, ""}, {"Statfs_t.Bavail", Field, 0, ""}, {"Statfs_t.Bfree", Field, 0, ""}, {"Statfs_t.Blocks", Field, 0, ""}, {"Statfs_t.Bsize", Field, 0, ""}, {"Statfs_t.Charspare", Field, 0, ""}, {"Statfs_t.F_asyncreads", Field, 2, ""}, {"Statfs_t.F_asyncwrites", Field, 2, ""}, {"Statfs_t.F_bavail", Field, 2, ""}, {"Statfs_t.F_bfree", Field, 2, ""}, {"Statfs_t.F_blocks", Field, 2, ""}, {"Statfs_t.F_bsize", Field, 2, ""}, {"Statfs_t.F_ctime", Field, 2, ""}, {"Statfs_t.F_favail", Field, 2, ""}, {"Statfs_t.F_ffree", Field, 2, ""}, {"Statfs_t.F_files", Field, 2, ""}, {"Statfs_t.F_flags", Field, 2, ""}, {"Statfs_t.F_fsid", Field, 2, ""}, {"Statfs_t.F_fstypename", Field, 2, ""}, {"Statfs_t.F_iosize", Field, 2, ""}, {"Statfs_t.F_mntfromname", Field, 2, ""}, {"Statfs_t.F_mntfromspec", Field, 3, ""}, {"Statfs_t.F_mntonname", Field, 2, ""}, {"Statfs_t.F_namemax", Field, 2, ""}, {"Statfs_t.F_owner", Field, 2, ""}, {"Statfs_t.F_spare", Field, 2, ""}, {"Statfs_t.F_syncreads", Field, 2, ""}, {"Statfs_t.F_syncwrites", Field, 2, ""}, {"Statfs_t.Ffree", Field, 0, ""}, {"Statfs_t.Files", Field, 0, ""}, {"Statfs_t.Flags", Field, 0, ""}, {"Statfs_t.Frsize", Field, 0, ""}, {"Statfs_t.Fsid", Field, 0, ""}, {"Statfs_t.Fssubtype", Field, 0, ""}, {"Statfs_t.Fstypename", Field, 0, ""}, {"Statfs_t.Iosize", Field, 0, ""}, {"Statfs_t.Mntfromname", Field, 0, ""}, {"Statfs_t.Mntonname", Field, 0, ""}, {"Statfs_t.Mount_info", Field, 2, ""}, {"Statfs_t.Namelen", Field, 0, ""}, {"Statfs_t.Namemax", Field, 0, ""}, {"Statfs_t.Owner", Field, 0, ""}, {"Statfs_t.Pad_cgo_0", Field, 0, ""}, {"Statfs_t.Pad_cgo_1", Field, 2, ""}, {"Statfs_t.Reserved", Field, 0, ""}, {"Statfs_t.Spare", Field, 0, ""}, {"Statfs_t.Syncreads", Field, 0, ""}, {"Statfs_t.Syncwrites", Field, 0, ""}, {"Statfs_t.Type", Field, 0, ""}, {"Statfs_t.Version", Field, 0, ""}, {"Stderr", Var, 0, ""}, {"Stdin", Var, 0, ""}, {"Stdout", Var, 0, ""}, {"StringBytePtr", Func, 0, "func(s string) *byte"}, {"StringByteSlice", Func, 0, "func(s string) []byte"}, {"StringSlicePtr", Func, 0, "func(ss []string) []*byte"}, {"StringToSid", Func, 0, ""}, {"StringToUTF16", Func, 0, ""}, {"StringToUTF16Ptr", Func, 0, ""}, {"Symlink", Func, 0, "func(oldpath string, newpath string) (err error)"}, {"Sync", Func, 0, "func()"}, {"SyncFileRange", Func, 0, "func(fd int, off int64, n int64, flags int) (err error)"}, {"SysProcAttr", Type, 0, ""}, {"SysProcAttr.AdditionalInheritedHandles", Field, 17, ""}, {"SysProcAttr.AmbientCaps", Field, 9, ""}, {"SysProcAttr.CgroupFD", Field, 20, ""}, {"SysProcAttr.Chroot", Field, 0, ""}, {"SysProcAttr.Cloneflags", Field, 2, ""}, {"SysProcAttr.CmdLine", Field, 0, ""}, {"SysProcAttr.CreationFlags", Field, 1, ""}, {"SysProcAttr.Credential", Field, 0, ""}, {"SysProcAttr.Ctty", Field, 1, ""}, {"SysProcAttr.Foreground", Field, 5, ""}, {"SysProcAttr.GidMappings", Field, 4, ""}, {"SysProcAttr.GidMappingsEnableSetgroups", Field, 5, ""}, {"SysProcAttr.HideWindow", Field, 0, ""}, {"SysProcAttr.Jail", Field, 21, ""}, {"SysProcAttr.NoInheritHandles", Field, 16, ""}, {"SysProcAttr.Noctty", Field, 0, ""}, {"SysProcAttr.ParentProcess", Field, 17, ""}, {"SysProcAttr.Pdeathsig", Field, 0, ""}, {"SysProcAttr.Pgid", Field, 5, ""}, {"SysProcAttr.PidFD", Field, 22, ""}, {"SysProcAttr.ProcessAttributes", Field, 13, ""}, {"SysProcAttr.Ptrace", Field, 0, ""}, {"SysProcAttr.Setctty", Field, 0, ""}, {"SysProcAttr.Setpgid", Field, 0, ""}, {"SysProcAttr.Setsid", Field, 0, ""}, {"SysProcAttr.ThreadAttributes", Field, 13, ""}, {"SysProcAttr.Token", Field, 10, ""}, {"SysProcAttr.UidMappings", Field, 4, ""}, {"SysProcAttr.Unshareflags", Field, 7, ""}, {"SysProcAttr.UseCgroupFD", Field, 20, ""}, {"SysProcIDMap", Type, 4, ""}, {"SysProcIDMap.ContainerID", Field, 4, ""}, {"SysProcIDMap.HostID", Field, 4, ""}, {"SysProcIDMap.Size", Field, 4, ""}, {"Syscall", Func, 0, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, {"Syscall12", Func, 0, ""}, {"Syscall15", Func, 0, ""}, {"Syscall18", Func, 12, ""}, {"Syscall6", Func, 0, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr, a4 uintptr, a5 uintptr, a6 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, {"Syscall9", Func, 0, ""}, {"SyscallN", Func, 18, ""}, {"Sysctl", Func, 0, ""}, {"SysctlUint32", Func, 0, ""}, {"Sysctlnode", Type, 2, ""}, {"Sysctlnode.Flags", Field, 2, ""}, {"Sysctlnode.Name", Field, 2, ""}, {"Sysctlnode.Num", Field, 2, ""}, {"Sysctlnode.Un", Field, 2, ""}, {"Sysctlnode.Ver", Field, 2, ""}, {"Sysctlnode.X__rsvd", Field, 2, ""}, {"Sysctlnode.X_sysctl_desc", Field, 2, ""}, {"Sysctlnode.X_sysctl_func", Field, 2, ""}, {"Sysctlnode.X_sysctl_parent", Field, 2, ""}, {"Sysctlnode.X_sysctl_size", Field, 2, ""}, {"Sysinfo", Func, 0, "func(info *Sysinfo_t) (err error)"}, {"Sysinfo_t", Type, 0, ""}, {"Sysinfo_t.Bufferram", Field, 0, ""}, {"Sysinfo_t.Freehigh", Field, 0, ""}, {"Sysinfo_t.Freeram", Field, 0, ""}, {"Sysinfo_t.Freeswap", Field, 0, ""}, {"Sysinfo_t.Loads", Field, 0, ""}, {"Sysinfo_t.Pad", Field, 0, ""}, {"Sysinfo_t.Pad_cgo_0", Field, 0, ""}, {"Sysinfo_t.Pad_cgo_1", Field, 0, ""}, {"Sysinfo_t.Procs", Field, 0, ""}, {"Sysinfo_t.Sharedram", Field, 0, ""}, {"Sysinfo_t.Totalhigh", Field, 0, ""}, {"Sysinfo_t.Totalram", Field, 0, ""}, {"Sysinfo_t.Totalswap", Field, 0, ""}, {"Sysinfo_t.Unit", Field, 0, ""}, {"Sysinfo_t.Uptime", Field, 0, ""}, {"Sysinfo_t.X_f", Field, 0, ""}, {"Systemtime", Type, 0, ""}, {"Systemtime.Day", Field, 0, ""}, {"Systemtime.DayOfWeek", Field, 0, ""}, {"Systemtime.Hour", Field, 0, ""}, {"Systemtime.Milliseconds", Field, 0, ""}, {"Systemtime.Minute", Field, 0, ""}, {"Systemtime.Month", Field, 0, ""}, {"Systemtime.Second", Field, 0, ""}, {"Systemtime.Year", Field, 0, ""}, {"TCGETS", Const, 0, ""}, {"TCIFLUSH", Const, 1, ""}, {"TCIOFLUSH", Const, 1, ""}, {"TCOFLUSH", Const, 1, ""}, {"TCPInfo", Type, 1, ""}, {"TCPInfo.Advmss", Field, 1, ""}, {"TCPInfo.Ato", Field, 1, ""}, {"TCPInfo.Backoff", Field, 1, ""}, {"TCPInfo.Ca_state", Field, 1, ""}, {"TCPInfo.Fackets", Field, 1, ""}, {"TCPInfo.Last_ack_recv", Field, 1, ""}, {"TCPInfo.Last_ack_sent", Field, 1, ""}, {"TCPInfo.Last_data_recv", Field, 1, ""}, {"TCPInfo.Last_data_sent", Field, 1, ""}, {"TCPInfo.Lost", Field, 1, ""}, {"TCPInfo.Options", Field, 1, ""}, {"TCPInfo.Pad_cgo_0", Field, 1, ""}, {"TCPInfo.Pmtu", Field, 1, ""}, {"TCPInfo.Probes", Field, 1, ""}, {"TCPInfo.Rcv_mss", Field, 1, ""}, {"TCPInfo.Rcv_rtt", Field, 1, ""}, {"TCPInfo.Rcv_space", Field, 1, ""}, {"TCPInfo.Rcv_ssthresh", Field, 1, ""}, {"TCPInfo.Reordering", Field, 1, ""}, {"TCPInfo.Retrans", Field, 1, ""}, {"TCPInfo.Retransmits", Field, 1, ""}, {"TCPInfo.Rto", Field, 1, ""}, {"TCPInfo.Rtt", Field, 1, ""}, {"TCPInfo.Rttvar", Field, 1, ""}, {"TCPInfo.Sacked", Field, 1, ""}, {"TCPInfo.Snd_cwnd", Field, 1, ""}, {"TCPInfo.Snd_mss", Field, 1, ""}, {"TCPInfo.Snd_ssthresh", Field, 1, ""}, {"TCPInfo.State", Field, 1, ""}, {"TCPInfo.Total_retrans", Field, 1, ""}, {"TCPInfo.Unacked", Field, 1, ""}, {"TCPKeepalive", Type, 3, ""}, {"TCPKeepalive.Interval", Field, 3, ""}, {"TCPKeepalive.OnOff", Field, 3, ""}, {"TCPKeepalive.Time", Field, 3, ""}, {"TCP_CA_NAME_MAX", Const, 0, ""}, {"TCP_CONGCTL", Const, 1, ""}, {"TCP_CONGESTION", Const, 0, ""}, {"TCP_CONNECTIONTIMEOUT", Const, 0, ""}, {"TCP_CORK", Const, 0, ""}, {"TCP_DEFER_ACCEPT", Const, 0, ""}, {"TCP_ENABLE_ECN", Const, 16, ""}, {"TCP_INFO", Const, 0, ""}, {"TCP_KEEPALIVE", Const, 0, ""}, {"TCP_KEEPCNT", Const, 0, ""}, {"TCP_KEEPIDLE", Const, 0, ""}, {"TCP_KEEPINIT", Const, 1, ""}, {"TCP_KEEPINTVL", Const, 0, ""}, {"TCP_LINGER2", Const, 0, ""}, {"TCP_MAXBURST", Const, 0, ""}, {"TCP_MAXHLEN", Const, 0, ""}, {"TCP_MAXOLEN", Const, 0, ""}, {"TCP_MAXSEG", Const, 0, ""}, {"TCP_MAXWIN", Const, 0, ""}, {"TCP_MAX_SACK", Const, 0, ""}, {"TCP_MAX_WINSHIFT", Const, 0, ""}, {"TCP_MD5SIG", Const, 0, ""}, {"TCP_MD5SIG_MAXKEYLEN", Const, 0, ""}, {"TCP_MINMSS", Const, 0, ""}, {"TCP_MINMSSOVERLOAD", Const, 0, ""}, {"TCP_MSS", Const, 0, ""}, {"TCP_NODELAY", Const, 0, ""}, {"TCP_NOOPT", Const, 0, ""}, {"TCP_NOPUSH", Const, 0, ""}, {"TCP_NOTSENT_LOWAT", Const, 16, ""}, {"TCP_NSTATES", Const, 1, ""}, {"TCP_QUICKACK", Const, 0, ""}, {"TCP_RXT_CONNDROPTIME", Const, 0, ""}, {"TCP_RXT_FINDROP", Const, 0, ""}, {"TCP_SACK_ENABLE", Const, 1, ""}, {"TCP_SENDMOREACKS", Const, 16, ""}, {"TCP_SYNCNT", Const, 0, ""}, {"TCP_VENDOR", Const, 3, ""}, {"TCP_WINDOW_CLAMP", Const, 0, ""}, {"TCSAFLUSH", Const, 1, ""}, {"TCSETS", Const, 0, ""}, {"TF_DISCONNECT", Const, 0, ""}, {"TF_REUSE_SOCKET", Const, 0, ""}, {"TF_USE_DEFAULT_WORKER", Const, 0, ""}, {"TF_USE_KERNEL_APC", Const, 0, ""}, {"TF_USE_SYSTEM_THREAD", Const, 0, ""}, {"TF_WRITE_BEHIND", Const, 0, ""}, {"TH32CS_INHERIT", Const, 4, ""}, {"TH32CS_SNAPALL", Const, 4, ""}, {"TH32CS_SNAPHEAPLIST", Const, 4, ""}, {"TH32CS_SNAPMODULE", Const, 4, ""}, {"TH32CS_SNAPMODULE32", Const, 4, ""}, {"TH32CS_SNAPPROCESS", Const, 4, ""}, {"TH32CS_SNAPTHREAD", Const, 4, ""}, {"TIME_ZONE_ID_DAYLIGHT", Const, 0, ""}, {"TIME_ZONE_ID_STANDARD", Const, 0, ""}, {"TIME_ZONE_ID_UNKNOWN", Const, 0, ""}, {"TIOCCBRK", Const, 0, ""}, {"TIOCCDTR", Const, 0, ""}, {"TIOCCONS", Const, 0, ""}, {"TIOCDCDTIMESTAMP", Const, 0, ""}, {"TIOCDRAIN", Const, 0, ""}, {"TIOCDSIMICROCODE", Const, 0, ""}, {"TIOCEXCL", Const, 0, ""}, {"TIOCEXT", Const, 0, ""}, {"TIOCFLAG_CDTRCTS", Const, 1, ""}, {"TIOCFLAG_CLOCAL", Const, 1, ""}, {"TIOCFLAG_CRTSCTS", Const, 1, ""}, {"TIOCFLAG_MDMBUF", Const, 1, ""}, {"TIOCFLAG_PPS", Const, 1, ""}, {"TIOCFLAG_SOFTCAR", Const, 1, ""}, {"TIOCFLUSH", Const, 0, ""}, {"TIOCGDEV", Const, 0, ""}, {"TIOCGDRAINWAIT", Const, 0, ""}, {"TIOCGETA", Const, 0, ""}, {"TIOCGETD", Const, 0, ""}, {"TIOCGFLAGS", Const, 1, ""}, {"TIOCGICOUNT", Const, 0, ""}, {"TIOCGLCKTRMIOS", Const, 0, ""}, {"TIOCGLINED", Const, 1, ""}, {"TIOCGPGRP", Const, 0, ""}, {"TIOCGPTN", Const, 0, ""}, {"TIOCGQSIZE", Const, 1, ""}, {"TIOCGRANTPT", Const, 1, ""}, {"TIOCGRS485", Const, 0, ""}, {"TIOCGSERIAL", Const, 0, ""}, {"TIOCGSID", Const, 0, ""}, {"TIOCGSIZE", Const, 1, ""}, {"TIOCGSOFTCAR", Const, 0, ""}, {"TIOCGTSTAMP", Const, 1, ""}, {"TIOCGWINSZ", Const, 0, ""}, {"TIOCINQ", Const, 0, ""}, {"TIOCIXOFF", Const, 0, ""}, {"TIOCIXON", Const, 0, ""}, {"TIOCLINUX", Const, 0, ""}, {"TIOCMBIC", Const, 0, ""}, {"TIOCMBIS", Const, 0, ""}, {"TIOCMGDTRWAIT", Const, 0, ""}, {"TIOCMGET", Const, 0, ""}, {"TIOCMIWAIT", Const, 0, ""}, {"TIOCMODG", Const, 0, ""}, {"TIOCMODS", Const, 0, ""}, {"TIOCMSDTRWAIT", Const, 0, ""}, {"TIOCMSET", Const, 0, ""}, {"TIOCM_CAR", Const, 0, ""}, {"TIOCM_CD", Const, 0, ""}, {"TIOCM_CTS", Const, 0, ""}, {"TIOCM_DCD", Const, 0, ""}, {"TIOCM_DSR", Const, 0, ""}, {"TIOCM_DTR", Const, 0, ""}, {"TIOCM_LE", Const, 0, ""}, {"TIOCM_RI", Const, 0, ""}, {"TIOCM_RNG", Const, 0, ""}, {"TIOCM_RTS", Const, 0, ""}, {"TIOCM_SR", Const, 0, ""}, {"TIOCM_ST", Const, 0, ""}, {"TIOCNOTTY", Const, 0, ""}, {"TIOCNXCL", Const, 0, ""}, {"TIOCOUTQ", Const, 0, ""}, {"TIOCPKT", Const, 0, ""}, {"TIOCPKT_DATA", Const, 0, ""}, {"TIOCPKT_DOSTOP", Const, 0, ""}, {"TIOCPKT_FLUSHREAD", Const, 0, ""}, {"TIOCPKT_FLUSHWRITE", Const, 0, ""}, {"TIOCPKT_IOCTL", Const, 0, ""}, {"TIOCPKT_NOSTOP", Const, 0, ""}, {"TIOCPKT_START", Const, 0, ""}, {"TIOCPKT_STOP", Const, 0, ""}, {"TIOCPTMASTER", Const, 0, ""}, {"TIOCPTMGET", Const, 1, ""}, {"TIOCPTSNAME", Const, 1, ""}, {"TIOCPTYGNAME", Const, 0, ""}, {"TIOCPTYGRANT", Const, 0, ""}, {"TIOCPTYUNLK", Const, 0, ""}, {"TIOCRCVFRAME", Const, 1, ""}, {"TIOCREMOTE", Const, 0, ""}, {"TIOCSBRK", Const, 0, ""}, {"TIOCSCONS", Const, 0, ""}, {"TIOCSCTTY", Const, 0, ""}, {"TIOCSDRAINWAIT", Const, 0, ""}, {"TIOCSDTR", Const, 0, ""}, {"TIOCSERCONFIG", Const, 0, ""}, {"TIOCSERGETLSR", Const, 0, ""}, {"TIOCSERGETMULTI", Const, 0, ""}, {"TIOCSERGSTRUCT", Const, 0, ""}, {"TIOCSERGWILD", Const, 0, ""}, {"TIOCSERSETMULTI", Const, 0, ""}, {"TIOCSERSWILD", Const, 0, ""}, {"TIOCSER_TEMT", Const, 0, ""}, {"TIOCSETA", Const, 0, ""}, {"TIOCSETAF", Const, 0, ""}, {"TIOCSETAW", Const, 0, ""}, {"TIOCSETD", Const, 0, ""}, {"TIOCSFLAGS", Const, 1, ""}, {"TIOCSIG", Const, 0, ""}, {"TIOCSLCKTRMIOS", Const, 0, ""}, {"TIOCSLINED", Const, 1, ""}, {"TIOCSPGRP", Const, 0, ""}, {"TIOCSPTLCK", Const, 0, ""}, {"TIOCSQSIZE", Const, 1, ""}, {"TIOCSRS485", Const, 0, ""}, {"TIOCSSERIAL", Const, 0, ""}, {"TIOCSSIZE", Const, 1, ""}, {"TIOCSSOFTCAR", Const, 0, ""}, {"TIOCSTART", Const, 0, ""}, {"TIOCSTAT", Const, 0, ""}, {"TIOCSTI", Const, 0, ""}, {"TIOCSTOP", Const, 0, ""}, {"TIOCSTSTAMP", Const, 1, ""}, {"TIOCSWINSZ", Const, 0, ""}, {"TIOCTIMESTAMP", Const, 0, ""}, {"TIOCUCNTL", Const, 0, ""}, {"TIOCVHANGUP", Const, 0, ""}, {"TIOCXMTFRAME", Const, 1, ""}, {"TOKEN_ADJUST_DEFAULT", Const, 0, ""}, {"TOKEN_ADJUST_GROUPS", Const, 0, ""}, {"TOKEN_ADJUST_PRIVILEGES", Const, 0, ""}, {"TOKEN_ADJUST_SESSIONID", Const, 11, ""}, {"TOKEN_ALL_ACCESS", Const, 0, ""}, {"TOKEN_ASSIGN_PRIMARY", Const, 0, ""}, {"TOKEN_DUPLICATE", Const, 0, ""}, {"TOKEN_EXECUTE", Const, 0, ""}, {"TOKEN_IMPERSONATE", Const, 0, ""}, {"TOKEN_QUERY", Const, 0, ""}, {"TOKEN_QUERY_SOURCE", Const, 0, ""}, {"TOKEN_READ", Const, 0, ""}, {"TOKEN_WRITE", Const, 0, ""}, {"TOSTOP", Const, 0, ""}, {"TRUNCATE_EXISTING", Const, 0, ""}, {"TUNATTACHFILTER", Const, 0, ""}, {"TUNDETACHFILTER", Const, 0, ""}, {"TUNGETFEATURES", Const, 0, ""}, {"TUNGETIFF", Const, 0, ""}, {"TUNGETSNDBUF", Const, 0, ""}, {"TUNGETVNETHDRSZ", Const, 0, ""}, {"TUNSETDEBUG", Const, 0, ""}, {"TUNSETGROUP", Const, 0, ""}, {"TUNSETIFF", Const, 0, ""}, {"TUNSETLINK", Const, 0, ""}, {"TUNSETNOCSUM", Const, 0, ""}, {"TUNSETOFFLOAD", Const, 0, ""}, {"TUNSETOWNER", Const, 0, ""}, {"TUNSETPERSIST", Const, 0, ""}, {"TUNSETSNDBUF", Const, 0, ""}, {"TUNSETTXFILTER", Const, 0, ""}, {"TUNSETVNETHDRSZ", Const, 0, ""}, {"Tee", Func, 0, "func(rfd int, wfd int, len int, flags int) (n int64, err error)"}, {"TerminateProcess", Func, 0, ""}, {"Termios", Type, 0, ""}, {"Termios.Cc", Field, 0, ""}, {"Termios.Cflag", Field, 0, ""}, {"Termios.Iflag", Field, 0, ""}, {"Termios.Ispeed", Field, 0, ""}, {"Termios.Lflag", Field, 0, ""}, {"Termios.Line", Field, 0, ""}, {"Termios.Oflag", Field, 0, ""}, {"Termios.Ospeed", Field, 0, ""}, {"Termios.Pad_cgo_0", Field, 0, ""}, {"Tgkill", Func, 0, "func(tgid int, tid int, sig Signal) (err error)"}, {"Time", Func, 0, "func(t *Time_t) (tt Time_t, err error)"}, {"Time_t", Type, 0, ""}, {"Times", Func, 0, "func(tms *Tms) (ticks uintptr, err error)"}, {"Timespec", Type, 0, ""}, {"Timespec.Nsec", Field, 0, ""}, {"Timespec.Pad_cgo_0", Field, 2, ""}, {"Timespec.Sec", Field, 0, ""}, {"TimespecToNsec", Func, 0, "func(ts Timespec) int64"}, {"Timeval", Type, 0, ""}, {"Timeval.Pad_cgo_0", Field, 0, ""}, {"Timeval.Sec", Field, 0, ""}, {"Timeval.Usec", Field, 0, ""}, {"Timeval32", Type, 0, ""}, {"Timeval32.Sec", Field, 0, ""}, {"Timeval32.Usec", Field, 0, ""}, {"TimevalToNsec", Func, 0, "func(tv Timeval) int64"}, {"Timex", Type, 0, ""}, {"Timex.Calcnt", Field, 0, ""}, {"Timex.Constant", Field, 0, ""}, {"Timex.Errcnt", Field, 0, ""}, {"Timex.Esterror", Field, 0, ""}, {"Timex.Freq", Field, 0, ""}, {"Timex.Jitcnt", Field, 0, ""}, {"Timex.Jitter", Field, 0, ""}, {"Timex.Maxerror", Field, 0, ""}, {"Timex.Modes", Field, 0, ""}, {"Timex.Offset", Field, 0, ""}, {"Timex.Pad_cgo_0", Field, 0, ""}, {"Timex.Pad_cgo_1", Field, 0, ""}, {"Timex.Pad_cgo_2", Field, 0, ""}, {"Timex.Pad_cgo_3", Field, 0, ""}, {"Timex.Ppsfreq", Field, 0, ""}, {"Timex.Precision", Field, 0, ""}, {"Timex.Shift", Field, 0, ""}, {"Timex.Stabil", Field, 0, ""}, {"Timex.Status", Field, 0, ""}, {"Timex.Stbcnt", Field, 0, ""}, {"Timex.Tai", Field, 0, ""}, {"Timex.Tick", Field, 0, ""}, {"Timex.Time", Field, 0, ""}, {"Timex.Tolerance", Field, 0, ""}, {"Timezoneinformation", Type, 0, ""}, {"Timezoneinformation.Bias", Field, 0, ""}, {"Timezoneinformation.DaylightBias", Field, 0, ""}, {"Timezoneinformation.DaylightDate", Field, 0, ""}, {"Timezoneinformation.DaylightName", Field, 0, ""}, {"Timezoneinformation.StandardBias", Field, 0, ""}, {"Timezoneinformation.StandardDate", Field, 0, ""}, {"Timezoneinformation.StandardName", Field, 0, ""}, {"Tms", Type, 0, ""}, {"Tms.Cstime", Field, 0, ""}, {"Tms.Cutime", Field, 0, ""}, {"Tms.Stime", Field, 0, ""}, {"Tms.Utime", Field, 0, ""}, {"Token", Type, 0, ""}, {"TokenAccessInformation", Const, 0, ""}, {"TokenAuditPolicy", Const, 0, ""}, {"TokenDefaultDacl", Const, 0, ""}, {"TokenElevation", Const, 0, ""}, {"TokenElevationType", Const, 0, ""}, {"TokenGroups", Const, 0, ""}, {"TokenGroupsAndPrivileges", Const, 0, ""}, {"TokenHasRestrictions", Const, 0, ""}, {"TokenImpersonationLevel", Const, 0, ""}, {"TokenIntegrityLevel", Const, 0, ""}, {"TokenLinkedToken", Const, 0, ""}, {"TokenLogonSid", Const, 0, ""}, {"TokenMandatoryPolicy", Const, 0, ""}, {"TokenOrigin", Const, 0, ""}, {"TokenOwner", Const, 0, ""}, {"TokenPrimaryGroup", Const, 0, ""}, {"TokenPrivileges", Const, 0, ""}, {"TokenRestrictedSids", Const, 0, ""}, {"TokenSandBoxInert", Const, 0, ""}, {"TokenSessionId", Const, 0, ""}, {"TokenSessionReference", Const, 0, ""}, {"TokenSource", Const, 0, ""}, {"TokenStatistics", Const, 0, ""}, {"TokenType", Const, 0, ""}, {"TokenUIAccess", Const, 0, ""}, {"TokenUser", Const, 0, ""}, {"TokenVirtualizationAllowed", Const, 0, ""}, {"TokenVirtualizationEnabled", Const, 0, ""}, {"Tokenprimarygroup", Type, 0, ""}, {"Tokenprimarygroup.PrimaryGroup", Field, 0, ""}, {"Tokenuser", Type, 0, ""}, {"Tokenuser.User", Field, 0, ""}, {"TranslateAccountName", Func, 0, ""}, {"TranslateName", Func, 0, ""}, {"TransmitFile", Func, 0, ""}, {"TransmitFileBuffers", Type, 0, ""}, {"TransmitFileBuffers.Head", Field, 0, ""}, {"TransmitFileBuffers.HeadLength", Field, 0, ""}, {"TransmitFileBuffers.Tail", Field, 0, ""}, {"TransmitFileBuffers.TailLength", Field, 0, ""}, {"Truncate", Func, 0, "func(path string, length int64) (err error)"}, {"UNIX_PATH_MAX", Const, 12, ""}, {"USAGE_MATCH_TYPE_AND", Const, 0, ""}, {"USAGE_MATCH_TYPE_OR", Const, 0, ""}, {"UTF16FromString", Func, 1, ""}, {"UTF16PtrFromString", Func, 1, ""}, {"UTF16ToString", Func, 0, ""}, {"Ucred", Type, 0, ""}, {"Ucred.Gid", Field, 0, ""}, {"Ucred.Pid", Field, 0, ""}, {"Ucred.Uid", Field, 0, ""}, {"Umask", Func, 0, "func(mask int) (oldmask int)"}, {"Uname", Func, 0, "func(buf *Utsname) (err error)"}, {"Undelete", Func, 0, ""}, {"UnixCredentials", Func, 0, "func(ucred *Ucred) []byte"}, {"UnixRights", Func, 0, "func(fds ...int) []byte"}, {"Unlink", Func, 0, "func(path string) error"}, {"Unlinkat", Func, 0, "func(dirfd int, path string) error"}, {"UnmapViewOfFile", Func, 0, ""}, {"Unmount", Func, 0, "func(target string, flags int) (err error)"}, {"Unsetenv", Func, 4, "func(key string) error"}, {"Unshare", Func, 0, "func(flags int) (err error)"}, {"UserInfo10", Type, 0, ""}, {"UserInfo10.Comment", Field, 0, ""}, {"UserInfo10.FullName", Field, 0, ""}, {"UserInfo10.Name", Field, 0, ""}, {"UserInfo10.UsrComment", Field, 0, ""}, {"Ustat", Func, 0, "func(dev int, ubuf *Ustat_t) (err error)"}, {"Ustat_t", Type, 0, ""}, {"Ustat_t.Fname", Field, 0, ""}, {"Ustat_t.Fpack", Field, 0, ""}, {"Ustat_t.Pad_cgo_0", Field, 0, ""}, {"Ustat_t.Pad_cgo_1", Field, 0, ""}, {"Ustat_t.Tfree", Field, 0, ""}, {"Ustat_t.Tinode", Field, 0, ""}, {"Utimbuf", Type, 0, ""}, {"Utimbuf.Actime", Field, 0, ""}, {"Utimbuf.Modtime", Field, 0, ""}, {"Utime", Func, 0, "func(path string, buf *Utimbuf) (err error)"}, {"Utimes", Func, 0, "func(path string, tv []Timeval) (err error)"}, {"UtimesNano", Func, 1, "func(path string, ts []Timespec) (err error)"}, {"Utsname", Type, 0, ""}, {"Utsname.Domainname", Field, 0, ""}, {"Utsname.Machine", Field, 0, ""}, {"Utsname.Nodename", Field, 0, ""}, {"Utsname.Release", Field, 0, ""}, {"Utsname.Sysname", Field, 0, ""}, {"Utsname.Version", Field, 0, ""}, {"VDISCARD", Const, 0, ""}, {"VDSUSP", Const, 1, ""}, {"VEOF", Const, 0, ""}, {"VEOL", Const, 0, ""}, {"VEOL2", Const, 0, ""}, {"VERASE", Const, 0, ""}, {"VERASE2", Const, 1, ""}, {"VINTR", Const, 0, ""}, {"VKILL", Const, 0, ""}, {"VLNEXT", Const, 0, ""}, {"VMIN", Const, 0, ""}, {"VQUIT", Const, 0, ""}, {"VREPRINT", Const, 0, ""}, {"VSTART", Const, 0, ""}, {"VSTATUS", Const, 1, ""}, {"VSTOP", Const, 0, ""}, {"VSUSP", Const, 0, ""}, {"VSWTC", Const, 0, ""}, {"VT0", Const, 1, ""}, {"VT1", Const, 1, ""}, {"VTDLY", Const, 1, ""}, {"VTIME", Const, 0, ""}, {"VWERASE", Const, 0, ""}, {"VirtualLock", Func, 0, ""}, {"VirtualUnlock", Func, 0, ""}, {"WAIT_ABANDONED", Const, 0, ""}, {"WAIT_FAILED", Const, 0, ""}, {"WAIT_OBJECT_0", Const, 0, ""}, {"WAIT_TIMEOUT", Const, 0, ""}, {"WALL", Const, 0, ""}, {"WALLSIG", Const, 1, ""}, {"WALTSIG", Const, 1, ""}, {"WCLONE", Const, 0, ""}, {"WCONTINUED", Const, 0, ""}, {"WCOREFLAG", Const, 0, ""}, {"WEXITED", Const, 0, ""}, {"WLINUXCLONE", Const, 0, ""}, {"WNOHANG", Const, 0, ""}, {"WNOTHREAD", Const, 0, ""}, {"WNOWAIT", Const, 0, ""}, {"WNOZOMBIE", Const, 1, ""}, {"WOPTSCHECKED", Const, 1, ""}, {"WORDSIZE", Const, 0, ""}, {"WSABuf", Type, 0, ""}, {"WSABuf.Buf", Field, 0, ""}, {"WSABuf.Len", Field, 0, ""}, {"WSACleanup", Func, 0, ""}, {"WSADESCRIPTION_LEN", Const, 0, ""}, {"WSAData", Type, 0, ""}, {"WSAData.Description", Field, 0, ""}, {"WSAData.HighVersion", Field, 0, ""}, {"WSAData.MaxSockets", Field, 0, ""}, {"WSAData.MaxUdpDg", Field, 0, ""}, {"WSAData.SystemStatus", Field, 0, ""}, {"WSAData.VendorInfo", Field, 0, ""}, {"WSAData.Version", Field, 0, ""}, {"WSAEACCES", Const, 2, ""}, {"WSAECONNABORTED", Const, 9, ""}, {"WSAECONNRESET", Const, 3, ""}, {"WSAENOPROTOOPT", Const, 23, ""}, {"WSAEnumProtocols", Func, 2, ""}, {"WSAID_CONNECTEX", Var, 1, ""}, {"WSAIoctl", Func, 0, ""}, {"WSAPROTOCOL_LEN", Const, 2, ""}, {"WSAProtocolChain", Type, 2, ""}, {"WSAProtocolChain.ChainEntries", Field, 2, ""}, {"WSAProtocolChain.ChainLen", Field, 2, ""}, {"WSAProtocolInfo", Type, 2, ""}, {"WSAProtocolInfo.AddressFamily", Field, 2, ""}, {"WSAProtocolInfo.CatalogEntryId", Field, 2, ""}, {"WSAProtocolInfo.MaxSockAddr", Field, 2, ""}, {"WSAProtocolInfo.MessageSize", Field, 2, ""}, {"WSAProtocolInfo.MinSockAddr", Field, 2, ""}, {"WSAProtocolInfo.NetworkByteOrder", Field, 2, ""}, {"WSAProtocolInfo.Protocol", Field, 2, ""}, {"WSAProtocolInfo.ProtocolChain", Field, 2, ""}, {"WSAProtocolInfo.ProtocolMaxOffset", Field, 2, ""}, {"WSAProtocolInfo.ProtocolName", Field, 2, ""}, {"WSAProtocolInfo.ProviderFlags", Field, 2, ""}, {"WSAProtocolInfo.ProviderId", Field, 2, ""}, {"WSAProtocolInfo.ProviderReserved", Field, 2, ""}, {"WSAProtocolInfo.SecurityScheme", Field, 2, ""}, {"WSAProtocolInfo.ServiceFlags1", Field, 2, ""}, {"WSAProtocolInfo.ServiceFlags2", Field, 2, ""}, {"WSAProtocolInfo.ServiceFlags3", Field, 2, ""}, {"WSAProtocolInfo.ServiceFlags4", Field, 2, ""}, {"WSAProtocolInfo.SocketType", Field, 2, ""}, {"WSAProtocolInfo.Version", Field, 2, ""}, {"WSARecv", Func, 0, ""}, {"WSARecvFrom", Func, 0, ""}, {"WSASYS_STATUS_LEN", Const, 0, ""}, {"WSASend", Func, 0, ""}, {"WSASendTo", Func, 0, ""}, {"WSASendto", Func, 0, ""}, {"WSAStartup", Func, 0, ""}, {"WSTOPPED", Const, 0, ""}, {"WTRAPPED", Const, 1, ""}, {"WUNTRACED", Const, 0, ""}, {"Wait4", Func, 0, "func(pid int, wstatus *WaitStatus, options int, rusage *Rusage) (wpid int, err error)"}, {"WaitForSingleObject", Func, 0, ""}, {"WaitStatus", Type, 0, ""}, {"WaitStatus.ExitCode", Field, 0, ""}, {"Win32FileAttributeData", Type, 0, ""}, {"Win32FileAttributeData.CreationTime", Field, 0, ""}, {"Win32FileAttributeData.FileAttributes", Field, 0, ""}, {"Win32FileAttributeData.FileSizeHigh", Field, 0, ""}, {"Win32FileAttributeData.FileSizeLow", Field, 0, ""}, {"Win32FileAttributeData.LastAccessTime", Field, 0, ""}, {"Win32FileAttributeData.LastWriteTime", Field, 0, ""}, {"Win32finddata", Type, 0, ""}, {"Win32finddata.AlternateFileName", Field, 0, ""}, {"Win32finddata.CreationTime", Field, 0, ""}, {"Win32finddata.FileAttributes", Field, 0, ""}, {"Win32finddata.FileName", Field, 0, ""}, {"Win32finddata.FileSizeHigh", Field, 0, ""}, {"Win32finddata.FileSizeLow", Field, 0, ""}, {"Win32finddata.LastAccessTime", Field, 0, ""}, {"Win32finddata.LastWriteTime", Field, 0, ""}, {"Win32finddata.Reserved0", Field, 0, ""}, {"Win32finddata.Reserved1", Field, 0, ""}, {"Write", Func, 0, "func(fd int, p []byte) (n int, err error)"}, {"WriteConsole", Func, 1, ""}, {"WriteFile", Func, 0, ""}, {"X509_ASN_ENCODING", Const, 0, ""}, {"XCASE", Const, 0, ""}, {"XP1_CONNECTIONLESS", Const, 2, ""}, {"XP1_CONNECT_DATA", Const, 2, ""}, {"XP1_DISCONNECT_DATA", Const, 2, ""}, {"XP1_EXPEDITED_DATA", Const, 2, ""}, {"XP1_GRACEFUL_CLOSE", Const, 2, ""}, {"XP1_GUARANTEED_DELIVERY", Const, 2, ""}, {"XP1_GUARANTEED_ORDER", Const, 2, ""}, {"XP1_IFS_HANDLES", Const, 2, ""}, {"XP1_MESSAGE_ORIENTED", Const, 2, ""}, {"XP1_MULTIPOINT_CONTROL_PLANE", Const, 2, ""}, {"XP1_MULTIPOINT_DATA_PLANE", Const, 2, ""}, {"XP1_PARTIAL_MESSAGE", Const, 2, ""}, {"XP1_PSEUDO_STREAM", Const, 2, ""}, {"XP1_QOS_SUPPORTED", Const, 2, ""}, {"XP1_SAN_SUPPORT_SDP", Const, 2, ""}, {"XP1_SUPPORT_BROADCAST", Const, 2, ""}, {"XP1_SUPPORT_MULTIPOINT", Const, 2, ""}, {"XP1_UNI_RECV", Const, 2, ""}, {"XP1_UNI_SEND", Const, 2, ""}, }, "syscall/js": { {"CopyBytesToGo", Func, 0, ""}, {"CopyBytesToJS", Func, 0, ""}, {"Error", Type, 0, ""}, {"Func", Type, 0, ""}, {"FuncOf", Func, 0, ""}, {"Global", Func, 0, ""}, {"Null", Func, 0, ""}, {"Type", Type, 0, ""}, {"TypeBoolean", Const, 0, ""}, {"TypeFunction", Const, 0, ""}, {"TypeNull", Const, 0, ""}, {"TypeNumber", Const, 0, ""}, {"TypeObject", Const, 0, ""}, {"TypeString", Const, 0, ""}, {"TypeSymbol", Const, 0, ""}, {"TypeUndefined", Const, 0, ""}, {"Undefined", Func, 0, ""}, {"Value", Type, 0, ""}, {"ValueError", Type, 0, ""}, {"ValueOf", Func, 0, ""}, }, "testing": { {"(*B).Chdir", Method, 24, ""}, {"(*B).Cleanup", Method, 14, ""}, {"(*B).Context", Method, 24, ""}, {"(*B).Elapsed", Method, 20, ""}, {"(*B).Error", Method, 0, ""}, {"(*B).Errorf", Method, 0, ""}, {"(*B).Fail", Method, 0, ""}, {"(*B).FailNow", Method, 0, ""}, {"(*B).Failed", Method, 0, ""}, {"(*B).Fatal", Method, 0, ""}, {"(*B).Fatalf", Method, 0, ""}, {"(*B).Helper", Method, 9, ""}, {"(*B).Log", Method, 0, ""}, {"(*B).Logf", Method, 0, ""}, {"(*B).Loop", Method, 24, ""}, {"(*B).Name", Method, 8, ""}, {"(*B).ReportAllocs", Method, 1, ""}, {"(*B).ReportMetric", Method, 13, ""}, {"(*B).ResetTimer", Method, 0, ""}, {"(*B).Run", Method, 7, ""}, {"(*B).RunParallel", Method, 3, ""}, {"(*B).SetBytes", Method, 0, ""}, {"(*B).SetParallelism", Method, 3, ""}, {"(*B).Setenv", Method, 17, ""}, {"(*B).Skip", Method, 1, ""}, {"(*B).SkipNow", Method, 1, ""}, {"(*B).Skipf", Method, 1, ""}, {"(*B).Skipped", Method, 1, ""}, {"(*B).StartTimer", Method, 0, ""}, {"(*B).StopTimer", Method, 0, ""}, {"(*B).TempDir", Method, 15, ""}, {"(*F).Add", Method, 18, ""}, {"(*F).Chdir", Method, 24, ""}, {"(*F).Cleanup", Method, 18, ""}, {"(*F).Context", Method, 24, ""}, {"(*F).Error", Method, 18, ""}, {"(*F).Errorf", Method, 18, ""}, {"(*F).Fail", Method, 18, ""}, {"(*F).FailNow", Method, 18, ""}, {"(*F).Failed", Method, 18, ""}, {"(*F).Fatal", Method, 18, ""}, {"(*F).Fatalf", Method, 18, ""}, {"(*F).Fuzz", Method, 18, ""}, {"(*F).Helper", Method, 18, ""}, {"(*F).Log", Method, 18, ""}, {"(*F).Logf", Method, 18, ""}, {"(*F).Name", Method, 18, ""}, {"(*F).Setenv", Method, 18, ""}, {"(*F).Skip", Method, 18, ""}, {"(*F).SkipNow", Method, 18, ""}, {"(*F).Skipf", Method, 18, ""}, {"(*F).Skipped", Method, 18, ""}, {"(*F).TempDir", Method, 18, ""}, {"(*M).Run", Method, 4, ""}, {"(*PB).Next", Method, 3, ""}, {"(*T).Chdir", Method, 24, ""}, {"(*T).Cleanup", Method, 14, ""}, {"(*T).Context", Method, 24, ""}, {"(*T).Deadline", Method, 15, ""}, {"(*T).Error", Method, 0, ""}, {"(*T).Errorf", Method, 0, ""}, {"(*T).Fail", Method, 0, ""}, {"(*T).FailNow", Method, 0, ""}, {"(*T).Failed", Method, 0, ""}, {"(*T).Fatal", Method, 0, ""}, {"(*T).Fatalf", Method, 0, ""}, {"(*T).Helper", Method, 9, ""}, {"(*T).Log", Method, 0, ""}, {"(*T).Logf", Method, 0, ""}, {"(*T).Name", Method, 8, ""}, {"(*T).Parallel", Method, 0, ""}, {"(*T).Run", Method, 7, ""}, {"(*T).Setenv", Method, 17, ""}, {"(*T).Skip", Method, 1, ""}, {"(*T).SkipNow", Method, 1, ""}, {"(*T).Skipf", Method, 1, ""}, {"(*T).Skipped", Method, 1, ""}, {"(*T).TempDir", Method, 15, ""}, {"(BenchmarkResult).AllocedBytesPerOp", Method, 1, ""}, {"(BenchmarkResult).AllocsPerOp", Method, 1, ""}, {"(BenchmarkResult).MemString", Method, 1, ""}, {"(BenchmarkResult).NsPerOp", Method, 0, ""}, {"(BenchmarkResult).String", Method, 0, ""}, {"AllocsPerRun", Func, 1, "func(runs int, f func()) (avg float64)"}, {"B", Type, 0, ""}, {"B.N", Field, 0, ""}, {"Benchmark", Func, 0, "func(f func(b *B)) BenchmarkResult"}, {"BenchmarkResult", Type, 0, ""}, {"BenchmarkResult.Bytes", Field, 0, ""}, {"BenchmarkResult.Extra", Field, 13, ""}, {"BenchmarkResult.MemAllocs", Field, 1, ""}, {"BenchmarkResult.MemBytes", Field, 1, ""}, {"BenchmarkResult.N", Field, 0, ""}, {"BenchmarkResult.T", Field, 0, ""}, {"Cover", Type, 2, ""}, {"Cover.Blocks", Field, 2, ""}, {"Cover.Counters", Field, 2, ""}, {"Cover.CoveredPackages", Field, 2, ""}, {"Cover.Mode", Field, 2, ""}, {"CoverBlock", Type, 2, ""}, {"CoverBlock.Col0", Field, 2, ""}, {"CoverBlock.Col1", Field, 2, ""}, {"CoverBlock.Line0", Field, 2, ""}, {"CoverBlock.Line1", Field, 2, ""}, {"CoverBlock.Stmts", Field, 2, ""}, {"CoverMode", Func, 8, "func() string"}, {"Coverage", Func, 4, "func() float64"}, {"F", Type, 18, ""}, {"Init", Func, 13, "func()"}, {"InternalBenchmark", Type, 0, ""}, {"InternalBenchmark.F", Field, 0, ""}, {"InternalBenchmark.Name", Field, 0, ""}, {"InternalExample", Type, 0, ""}, {"InternalExample.F", Field, 0, ""}, {"InternalExample.Name", Field, 0, ""}, {"InternalExample.Output", Field, 0, ""}, {"InternalExample.Unordered", Field, 7, ""}, {"InternalFuzzTarget", Type, 18, ""}, {"InternalFuzzTarget.Fn", Field, 18, ""}, {"InternalFuzzTarget.Name", Field, 18, ""}, {"InternalTest", Type, 0, ""}, {"InternalTest.F", Field, 0, ""}, {"InternalTest.Name", Field, 0, ""}, {"M", Type, 4, ""}, {"Main", Func, 0, "func(matchString func(pat string, str string) (bool, error), tests []InternalTest, benchmarks []InternalBenchmark, examples []InternalExample)"}, {"MainStart", Func, 4, "func(deps testDeps, tests []InternalTest, benchmarks []InternalBenchmark, fuzzTargets []InternalFuzzTarget, examples []InternalExample) *M"}, {"PB", Type, 3, ""}, {"RegisterCover", Func, 2, "func(c Cover)"}, {"RunBenchmarks", Func, 0, "func(matchString func(pat string, str string) (bool, error), benchmarks []InternalBenchmark)"}, {"RunExamples", Func, 0, "func(matchString func(pat string, str string) (bool, error), examples []InternalExample) (ok bool)"}, {"RunTests", Func, 0, "func(matchString func(pat string, str string) (bool, error), tests []InternalTest) (ok bool)"}, {"Short", Func, 0, "func() bool"}, {"T", Type, 0, ""}, {"TB", Type, 2, ""}, {"Testing", Func, 21, "func() bool"}, {"Verbose", Func, 1, "func() bool"}, }, "testing/fstest": { {"(MapFS).Glob", Method, 16, ""}, {"(MapFS).Lstat", Method, 25, ""}, {"(MapFS).Open", Method, 16, ""}, {"(MapFS).ReadDir", Method, 16, ""}, {"(MapFS).ReadFile", Method, 16, ""}, {"(MapFS).ReadLink", Method, 25, ""}, {"(MapFS).Stat", Method, 16, ""}, {"(MapFS).Sub", Method, 16, ""}, {"MapFS", Type, 16, ""}, {"MapFile", Type, 16, ""}, {"MapFile.Data", Field, 16, ""}, {"MapFile.ModTime", Field, 16, ""}, {"MapFile.Mode", Field, 16, ""}, {"MapFile.Sys", Field, 16, ""}, {"TestFS", Func, 16, "func(fsys fs.FS, expected ...string) error"}, }, "testing/iotest": { {"DataErrReader", Func, 0, "func(r io.Reader) io.Reader"}, {"ErrReader", Func, 16, "func(err error) io.Reader"}, {"ErrTimeout", Var, 0, ""}, {"HalfReader", Func, 0, "func(r io.Reader) io.Reader"}, {"NewReadLogger", Func, 0, "func(prefix string, r io.Reader) io.Reader"}, {"NewWriteLogger", Func, 0, "func(prefix string, w io.Writer) io.Writer"}, {"OneByteReader", Func, 0, "func(r io.Reader) io.Reader"}, {"TestReader", Func, 16, "func(r io.Reader, content []byte) error"}, {"TimeoutReader", Func, 0, "func(r io.Reader) io.Reader"}, {"TruncateWriter", Func, 0, "func(w io.Writer, n int64) io.Writer"}, }, "testing/quick": { {"(*CheckEqualError).Error", Method, 0, ""}, {"(*CheckError).Error", Method, 0, ""}, {"(SetupError).Error", Method, 0, ""}, {"Check", Func, 0, "func(f any, config *Config) error"}, {"CheckEqual", Func, 0, "func(f any, g any, config *Config) error"}, {"CheckEqualError", Type, 0, ""}, {"CheckEqualError.CheckError", Field, 0, ""}, {"CheckEqualError.Out1", Field, 0, ""}, {"CheckEqualError.Out2", Field, 0, ""}, {"CheckError", Type, 0, ""}, {"CheckError.Count", Field, 0, ""}, {"CheckError.In", Field, 0, ""}, {"Config", Type, 0, ""}, {"Config.MaxCount", Field, 0, ""}, {"Config.MaxCountScale", Field, 0, ""}, {"Config.Rand", Field, 0, ""}, {"Config.Values", Field, 0, ""}, {"Generator", Type, 0, ""}, {"SetupError", Type, 0, ""}, {"Value", Func, 0, "func(t reflect.Type, rand *rand.Rand) (value reflect.Value, ok bool)"}, }, "testing/slogtest": { {"Run", Func, 22, "func(t *testing.T, newHandler func(*testing.T) slog.Handler, result func(*testing.T) map[string]any)"}, {"TestHandler", Func, 21, "func(h slog.Handler, results func() []map[string]any) error"}, }, "text/scanner": { {"(*Position).IsValid", Method, 0, ""}, {"(*Scanner).Init", Method, 0, ""}, {"(*Scanner).IsValid", Method, 0, ""}, {"(*Scanner).Next", Method, 0, ""}, {"(*Scanner).Peek", Method, 0, ""}, {"(*Scanner).Pos", Method, 0, ""}, {"(*Scanner).Scan", Method, 0, ""}, {"(*Scanner).TokenText", Method, 0, ""}, {"(Position).String", Method, 0, ""}, {"(Scanner).String", Method, 0, ""}, {"Char", Const, 0, ""}, {"Comment", Const, 0, ""}, {"EOF", Const, 0, ""}, {"Float", Const, 0, ""}, {"GoTokens", Const, 0, ""}, {"GoWhitespace", Const, 0, ""}, {"Ident", Const, 0, ""}, {"Int", Const, 0, ""}, {"Position", Type, 0, ""}, {"Position.Column", Field, 0, ""}, {"Position.Filename", Field, 0, ""}, {"Position.Line", Field, 0, ""}, {"Position.Offset", Field, 0, ""}, {"RawString", Const, 0, ""}, {"ScanChars", Const, 0, ""}, {"ScanComments", Const, 0, ""}, {"ScanFloats", Const, 0, ""}, {"ScanIdents", Const, 0, ""}, {"ScanInts", Const, 0, ""}, {"ScanRawStrings", Const, 0, ""}, {"ScanStrings", Const, 0, ""}, {"Scanner", Type, 0, ""}, {"Scanner.Error", Field, 0, ""}, {"Scanner.ErrorCount", Field, 0, ""}, {"Scanner.IsIdentRune", Field, 4, ""}, {"Scanner.Mode", Field, 0, ""}, {"Scanner.Position", Field, 0, ""}, {"Scanner.Whitespace", Field, 0, ""}, {"SkipComments", Const, 0, ""}, {"String", Const, 0, ""}, {"TokenString", Func, 0, "func(tok rune) string"}, }, "text/tabwriter": { {"(*Writer).Flush", Method, 0, ""}, {"(*Writer).Init", Method, 0, ""}, {"(*Writer).Write", Method, 0, ""}, {"AlignRight", Const, 0, ""}, {"Debug", Const, 0, ""}, {"DiscardEmptyColumns", Const, 0, ""}, {"Escape", Const, 0, ""}, {"FilterHTML", Const, 0, ""}, {"NewWriter", Func, 0, "func(output io.Writer, minwidth int, tabwidth int, padding int, padchar byte, flags uint) *Writer"}, {"StripEscape", Const, 0, ""}, {"TabIndent", Const, 0, ""}, {"Writer", Type, 0, ""}, }, "text/template": { {"(*Template).AddParseTree", Method, 0, ""}, {"(*Template).Clone", Method, 0, ""}, {"(*Template).DefinedTemplates", Method, 5, ""}, {"(*Template).Delims", Method, 0, ""}, {"(*Template).Execute", Method, 0, ""}, {"(*Template).ExecuteTemplate", Method, 0, ""}, {"(*Template).Funcs", Method, 0, ""}, {"(*Template).Lookup", Method, 0, ""}, {"(*Template).Name", Method, 0, ""}, {"(*Template).New", Method, 0, ""}, {"(*Template).Option", Method, 5, ""}, {"(*Template).Parse", Method, 0, ""}, {"(*Template).ParseFS", Method, 16, ""}, {"(*Template).ParseFiles", Method, 0, ""}, {"(*Template).ParseGlob", Method, 0, ""}, {"(*Template).Templates", Method, 0, ""}, {"(ExecError).Error", Method, 6, ""}, {"(ExecError).Unwrap", Method, 13, ""}, {"(Template).Copy", Method, 2, ""}, {"(Template).ErrorContext", Method, 1, ""}, {"ExecError", Type, 6, ""}, {"ExecError.Err", Field, 6, ""}, {"ExecError.Name", Field, 6, ""}, {"FuncMap", Type, 0, ""}, {"HTMLEscape", Func, 0, "func(w io.Writer, b []byte)"}, {"HTMLEscapeString", Func, 0, "func(s string) string"}, {"HTMLEscaper", Func, 0, "func(args ...any) string"}, {"IsTrue", Func, 6, "func(val any) (truth bool, ok bool)"}, {"JSEscape", Func, 0, "func(w io.Writer, b []byte)"}, {"JSEscapeString", Func, 0, "func(s string) string"}, {"JSEscaper", Func, 0, "func(args ...any) string"}, {"Must", Func, 0, "func(t *Template, err error) *Template"}, {"New", Func, 0, "func(name string) *Template"}, {"ParseFS", Func, 16, "func(fsys fs.FS, patterns ...string) (*Template, error)"}, {"ParseFiles", Func, 0, "func(filenames ...string) (*Template, error)"}, {"ParseGlob", Func, 0, "func(pattern string) (*Template, error)"}, {"Template", Type, 0, ""}, {"Template.Tree", Field, 0, ""}, {"URLQueryEscaper", Func, 0, "func(args ...any) string"}, }, "text/template/parse": { {"(*ActionNode).Copy", Method, 0, ""}, {"(*ActionNode).String", Method, 0, ""}, {"(*BoolNode).Copy", Method, 0, ""}, {"(*BoolNode).String", Method, 0, ""}, {"(*BranchNode).Copy", Method, 4, ""}, {"(*BranchNode).String", Method, 0, ""}, {"(*BreakNode).Copy", Method, 18, ""}, {"(*BreakNode).String", Method, 18, ""}, {"(*ChainNode).Add", Method, 1, ""}, {"(*ChainNode).Copy", Method, 1, ""}, {"(*ChainNode).String", Method, 1, ""}, {"(*CommandNode).Copy", Method, 0, ""}, {"(*CommandNode).String", Method, 0, ""}, {"(*CommentNode).Copy", Method, 16, ""}, {"(*CommentNode).String", Method, 16, ""}, {"(*ContinueNode).Copy", Method, 18, ""}, {"(*ContinueNode).String", Method, 18, ""}, {"(*DotNode).Copy", Method, 0, ""}, {"(*DotNode).String", Method, 0, ""}, {"(*DotNode).Type", Method, 0, ""}, {"(*FieldNode).Copy", Method, 0, ""}, {"(*FieldNode).String", Method, 0, ""}, {"(*IdentifierNode).Copy", Method, 0, ""}, {"(*IdentifierNode).SetPos", Method, 1, ""}, {"(*IdentifierNode).SetTree", Method, 4, ""}, {"(*IdentifierNode).String", Method, 0, ""}, {"(*IfNode).Copy", Method, 0, ""}, {"(*IfNode).String", Method, 0, ""}, {"(*ListNode).Copy", Method, 0, ""}, {"(*ListNode).CopyList", Method, 0, ""}, {"(*ListNode).String", Method, 0, ""}, {"(*NilNode).Copy", Method, 1, ""}, {"(*NilNode).String", Method, 1, ""}, {"(*NilNode).Type", Method, 1, ""}, {"(*NumberNode).Copy", Method, 0, ""}, {"(*NumberNode).String", Method, 0, ""}, {"(*PipeNode).Copy", Method, 0, ""}, {"(*PipeNode).CopyPipe", Method, 0, ""}, {"(*PipeNode).String", Method, 0, ""}, {"(*RangeNode).Copy", Method, 0, ""}, {"(*RangeNode).String", Method, 0, ""}, {"(*StringNode).Copy", Method, 0, ""}, {"(*StringNode).String", Method, 0, ""}, {"(*TemplateNode).Copy", Method, 0, ""}, {"(*TemplateNode).String", Method, 0, ""}, {"(*TextNode).Copy", Method, 0, ""}, {"(*TextNode).String", Method, 0, ""}, {"(*Tree).Copy", Method, 2, ""}, {"(*Tree).ErrorContext", Method, 1, ""}, {"(*Tree).Parse", Method, 0, ""}, {"(*VariableNode).Copy", Method, 0, ""}, {"(*VariableNode).String", Method, 0, ""}, {"(*WithNode).Copy", Method, 0, ""}, {"(*WithNode).String", Method, 0, ""}, {"(ActionNode).Position", Method, 1, ""}, {"(ActionNode).Type", Method, 0, ""}, {"(BoolNode).Position", Method, 1, ""}, {"(BoolNode).Type", Method, 0, ""}, {"(BranchNode).Position", Method, 1, ""}, {"(BranchNode).Type", Method, 0, ""}, {"(BreakNode).Position", Method, 18, ""}, {"(BreakNode).Type", Method, 18, ""}, {"(ChainNode).Position", Method, 1, ""}, {"(ChainNode).Type", Method, 1, ""}, {"(CommandNode).Position", Method, 1, ""}, {"(CommandNode).Type", Method, 0, ""}, {"(CommentNode).Position", Method, 16, ""}, {"(CommentNode).Type", Method, 16, ""}, {"(ContinueNode).Position", Method, 18, ""}, {"(ContinueNode).Type", Method, 18, ""}, {"(DotNode).Position", Method, 1, ""}, {"(FieldNode).Position", Method, 1, ""}, {"(FieldNode).Type", Method, 0, ""}, {"(IdentifierNode).Position", Method, 1, ""}, {"(IdentifierNode).Type", Method, 0, ""}, {"(IfNode).Position", Method, 1, ""}, {"(IfNode).Type", Method, 0, ""}, {"(ListNode).Position", Method, 1, ""}, {"(ListNode).Type", Method, 0, ""}, {"(NilNode).Position", Method, 1, ""}, {"(NodeType).Type", Method, 0, ""}, {"(NumberNode).Position", Method, 1, ""}, {"(NumberNode).Type", Method, 0, ""}, {"(PipeNode).Position", Method, 1, ""}, {"(PipeNode).Type", Method, 0, ""}, {"(Pos).Position", Method, 1, ""}, {"(RangeNode).Position", Method, 1, ""}, {"(RangeNode).Type", Method, 0, ""}, {"(StringNode).Position", Method, 1, ""}, {"(StringNode).Type", Method, 0, ""}, {"(TemplateNode).Position", Method, 1, ""}, {"(TemplateNode).Type", Method, 0, ""}, {"(TextNode).Position", Method, 1, ""}, {"(TextNode).Type", Method, 0, ""}, {"(VariableNode).Position", Method, 1, ""}, {"(VariableNode).Type", Method, 0, ""}, {"(WithNode).Position", Method, 1, ""}, {"(WithNode).Type", Method, 0, ""}, {"ActionNode", Type, 0, ""}, {"ActionNode.Line", Field, 0, ""}, {"ActionNode.NodeType", Field, 0, ""}, {"ActionNode.Pipe", Field, 0, ""}, {"ActionNode.Pos", Field, 1, ""}, {"BoolNode", Type, 0, ""}, {"BoolNode.NodeType", Field, 0, ""}, {"BoolNode.Pos", Field, 1, ""}, {"BoolNode.True", Field, 0, ""}, {"BranchNode", Type, 0, ""}, {"BranchNode.ElseList", Field, 0, ""}, {"BranchNode.Line", Field, 0, ""}, {"BranchNode.List", Field, 0, ""}, {"BranchNode.NodeType", Field, 0, ""}, {"BranchNode.Pipe", Field, 0, ""}, {"BranchNode.Pos", Field, 1, ""}, {"BreakNode", Type, 18, ""}, {"BreakNode.Line", Field, 18, ""}, {"BreakNode.NodeType", Field, 18, ""}, {"BreakNode.Pos", Field, 18, ""}, {"ChainNode", Type, 1, ""}, {"ChainNode.Field", Field, 1, ""}, {"ChainNode.Node", Field, 1, ""}, {"ChainNode.NodeType", Field, 1, ""}, {"ChainNode.Pos", Field, 1, ""}, {"CommandNode", Type, 0, ""}, {"CommandNode.Args", Field, 0, ""}, {"CommandNode.NodeType", Field, 0, ""}, {"CommandNode.Pos", Field, 1, ""}, {"CommentNode", Type, 16, ""}, {"CommentNode.NodeType", Field, 16, ""}, {"CommentNode.Pos", Field, 16, ""}, {"CommentNode.Text", Field, 16, ""}, {"ContinueNode", Type, 18, ""}, {"ContinueNode.Line", Field, 18, ""}, {"ContinueNode.NodeType", Field, 18, ""}, {"ContinueNode.Pos", Field, 18, ""}, {"DotNode", Type, 0, ""}, {"DotNode.NodeType", Field, 4, ""}, {"DotNode.Pos", Field, 1, ""}, {"FieldNode", Type, 0, ""}, {"FieldNode.Ident", Field, 0, ""}, {"FieldNode.NodeType", Field, 0, ""}, {"FieldNode.Pos", Field, 1, ""}, {"IdentifierNode", Type, 0, ""}, {"IdentifierNode.Ident", Field, 0, ""}, {"IdentifierNode.NodeType", Field, 0, ""}, {"IdentifierNode.Pos", Field, 1, ""}, {"IfNode", Type, 0, ""}, {"IfNode.BranchNode", Field, 0, ""}, {"IsEmptyTree", Func, 0, "func(n Node) bool"}, {"ListNode", Type, 0, ""}, {"ListNode.NodeType", Field, 0, ""}, {"ListNode.Nodes", Field, 0, ""}, {"ListNode.Pos", Field, 1, ""}, {"Mode", Type, 16, ""}, {"New", Func, 0, "func(name string, funcs ...map[string]any) *Tree"}, {"NewIdentifier", Func, 0, "func(ident string) *IdentifierNode"}, {"NilNode", Type, 1, ""}, {"NilNode.NodeType", Field, 4, ""}, {"NilNode.Pos", Field, 1, ""}, {"Node", Type, 0, ""}, {"NodeAction", Const, 0, ""}, {"NodeBool", Const, 0, ""}, {"NodeBreak", Const, 18, ""}, {"NodeChain", Const, 1, ""}, {"NodeCommand", Const, 0, ""}, {"NodeComment", Const, 16, ""}, {"NodeContinue", Const, 18, ""}, {"NodeDot", Const, 0, ""}, {"NodeField", Const, 0, ""}, {"NodeIdentifier", Const, 0, ""}, {"NodeIf", Const, 0, ""}, {"NodeList", Const, 0, ""}, {"NodeNil", Const, 1, ""}, {"NodeNumber", Const, 0, ""}, {"NodePipe", Const, 0, ""}, {"NodeRange", Const, 0, ""}, {"NodeString", Const, 0, ""}, {"NodeTemplate", Const, 0, ""}, {"NodeText", Const, 0, ""}, {"NodeType", Type, 0, ""}, {"NodeVariable", Const, 0, ""}, {"NodeWith", Const, 0, ""}, {"NumberNode", Type, 0, ""}, {"NumberNode.Complex128", Field, 0, ""}, {"NumberNode.Float64", Field, 0, ""}, {"NumberNode.Int64", Field, 0, ""}, {"NumberNode.IsComplex", Field, 0, ""}, {"NumberNode.IsFloat", Field, 0, ""}, {"NumberNode.IsInt", Field, 0, ""}, {"NumberNode.IsUint", Field, 0, ""}, {"NumberNode.NodeType", Field, 0, ""}, {"NumberNode.Pos", Field, 1, ""}, {"NumberNode.Text", Field, 0, ""}, {"NumberNode.Uint64", Field, 0, ""}, {"Parse", Func, 0, "func(name string, text string, leftDelim string, rightDelim string, funcs ...map[string]any) (map[string]*Tree, error)"}, {"ParseComments", Const, 16, ""}, {"PipeNode", Type, 0, ""}, {"PipeNode.Cmds", Field, 0, ""}, {"PipeNode.Decl", Field, 0, ""}, {"PipeNode.IsAssign", Field, 11, ""}, {"PipeNode.Line", Field, 0, ""}, {"PipeNode.NodeType", Field, 0, ""}, {"PipeNode.Pos", Field, 1, ""}, {"Pos", Type, 1, ""}, {"RangeNode", Type, 0, ""}, {"RangeNode.BranchNode", Field, 0, ""}, {"SkipFuncCheck", Const, 17, ""}, {"StringNode", Type, 0, ""}, {"StringNode.NodeType", Field, 0, ""}, {"StringNode.Pos", Field, 1, ""}, {"StringNode.Quoted", Field, 0, ""}, {"StringNode.Text", Field, 0, ""}, {"TemplateNode", Type, 0, ""}, {"TemplateNode.Line", Field, 0, ""}, {"TemplateNode.Name", Field, 0, ""}, {"TemplateNode.NodeType", Field, 0, ""}, {"TemplateNode.Pipe", Field, 0, ""}, {"TemplateNode.Pos", Field, 1, ""}, {"TextNode", Type, 0, ""}, {"TextNode.NodeType", Field, 0, ""}, {"TextNode.Pos", Field, 1, ""}, {"TextNode.Text", Field, 0, ""}, {"Tree", Type, 0, ""}, {"Tree.Mode", Field, 16, ""}, {"Tree.Name", Field, 0, ""}, {"Tree.ParseName", Field, 1, ""}, {"Tree.Root", Field, 0, ""}, {"VariableNode", Type, 0, ""}, {"VariableNode.Ident", Field, 0, ""}, {"VariableNode.NodeType", Field, 0, ""}, {"VariableNode.Pos", Field, 1, ""}, {"WithNode", Type, 0, ""}, {"WithNode.BranchNode", Field, 0, ""}, }, "time": { {"(*Location).String", Method, 0, ""}, {"(*ParseError).Error", Method, 0, ""}, {"(*Ticker).Reset", Method, 15, ""}, {"(*Ticker).Stop", Method, 0, ""}, {"(*Time).GobDecode", Method, 0, ""}, {"(*Time).UnmarshalBinary", Method, 2, ""}, {"(*Time).UnmarshalJSON", Method, 0, ""}, {"(*Time).UnmarshalText", Method, 2, ""}, {"(*Timer).Reset", Method, 1, ""}, {"(*Timer).Stop", Method, 0, ""}, {"(Duration).Abs", Method, 19, ""}, {"(Duration).Hours", Method, 0, ""}, {"(Duration).Microseconds", Method, 13, ""}, {"(Duration).Milliseconds", Method, 13, ""}, {"(Duration).Minutes", Method, 0, ""}, {"(Duration).Nanoseconds", Method, 0, ""}, {"(Duration).Round", Method, 9, ""}, {"(Duration).Seconds", Method, 0, ""}, {"(Duration).String", Method, 0, ""}, {"(Duration).Truncate", Method, 9, ""}, {"(Month).String", Method, 0, ""}, {"(Time).Add", Method, 0, ""}, {"(Time).AddDate", Method, 0, ""}, {"(Time).After", Method, 0, ""}, {"(Time).AppendBinary", Method, 24, ""}, {"(Time).AppendFormat", Method, 5, ""}, {"(Time).AppendText", Method, 24, ""}, {"(Time).Before", Method, 0, ""}, {"(Time).Clock", Method, 0, ""}, {"(Time).Compare", Method, 20, ""}, {"(Time).Date", Method, 0, ""}, {"(Time).Day", Method, 0, ""}, {"(Time).Equal", Method, 0, ""}, {"(Time).Format", Method, 0, ""}, {"(Time).GoString", Method, 17, ""}, {"(Time).GobEncode", Method, 0, ""}, {"(Time).Hour", Method, 0, ""}, {"(Time).ISOWeek", Method, 0, ""}, {"(Time).In", Method, 0, ""}, {"(Time).IsDST", Method, 17, ""}, {"(Time).IsZero", Method, 0, ""}, {"(Time).Local", Method, 0, ""}, {"(Time).Location", Method, 0, ""}, {"(Time).MarshalBinary", Method, 2, ""}, {"(Time).MarshalJSON", Method, 0, ""}, {"(Time).MarshalText", Method, 2, ""}, {"(Time).Minute", Method, 0, ""}, {"(Time).Month", Method, 0, ""}, {"(Time).Nanosecond", Method, 0, ""}, {"(Time).Round", Method, 1, ""}, {"(Time).Second", Method, 0, ""}, {"(Time).String", Method, 0, ""}, {"(Time).Sub", Method, 0, ""}, {"(Time).Truncate", Method, 1, ""}, {"(Time).UTC", Method, 0, ""}, {"(Time).Unix", Method, 0, ""}, {"(Time).UnixMicro", Method, 17, ""}, {"(Time).UnixMilli", Method, 17, ""}, {"(Time).UnixNano", Method, 0, ""}, {"(Time).Weekday", Method, 0, ""}, {"(Time).Year", Method, 0, ""}, {"(Time).YearDay", Method, 1, ""}, {"(Time).Zone", Method, 0, ""}, {"(Time).ZoneBounds", Method, 19, ""}, {"(Weekday).String", Method, 0, ""}, {"ANSIC", Const, 0, ""}, {"After", Func, 0, "func(d Duration) <-chan Time"}, {"AfterFunc", Func, 0, "func(d Duration, f func()) *Timer"}, {"April", Const, 0, ""}, {"August", Const, 0, ""}, {"Date", Func, 0, "func(year int, month Month, day int, hour int, min int, sec int, nsec int, loc *Location) Time"}, {"DateOnly", Const, 20, ""}, {"DateTime", Const, 20, ""}, {"December", Const, 0, ""}, {"Duration", Type, 0, ""}, {"February", Const, 0, ""}, {"FixedZone", Func, 0, "func(name string, offset int) *Location"}, {"Friday", Const, 0, ""}, {"Hour", Const, 0, ""}, {"January", Const, 0, ""}, {"July", Const, 0, ""}, {"June", Const, 0, ""}, {"Kitchen", Const, 0, ""}, {"Layout", Const, 17, ""}, {"LoadLocation", Func, 0, "func(name string) (*Location, error)"}, {"LoadLocationFromTZData", Func, 10, "func(name string, data []byte) (*Location, error)"}, {"Local", Var, 0, ""}, {"Location", Type, 0, ""}, {"March", Const, 0, ""}, {"May", Const, 0, ""}, {"Microsecond", Const, 0, ""}, {"Millisecond", Const, 0, ""}, {"Minute", Const, 0, ""}, {"Monday", Const, 0, ""}, {"Month", Type, 0, ""}, {"Nanosecond", Const, 0, ""}, {"NewTicker", Func, 0, "func(d Duration) *Ticker"}, {"NewTimer", Func, 0, "func(d Duration) *Timer"}, {"November", Const, 0, ""}, {"Now", Func, 0, "func() Time"}, {"October", Const, 0, ""}, {"Parse", Func, 0, "func(layout string, value string) (Time, error)"}, {"ParseDuration", Func, 0, "func(s string) (Duration, error)"}, {"ParseError", Type, 0, ""}, {"ParseError.Layout", Field, 0, ""}, {"ParseError.LayoutElem", Field, 0, ""}, {"ParseError.Message", Field, 0, ""}, {"ParseError.Value", Field, 0, ""}, {"ParseError.ValueElem", Field, 0, ""}, {"ParseInLocation", Func, 1, "func(layout string, value string, loc *Location) (Time, error)"}, {"RFC1123", Const, 0, ""}, {"RFC1123Z", Const, 0, ""}, {"RFC3339", Const, 0, ""}, {"RFC3339Nano", Const, 0, ""}, {"RFC822", Const, 0, ""}, {"RFC822Z", Const, 0, ""}, {"RFC850", Const, 0, ""}, {"RubyDate", Const, 0, ""}, {"Saturday", Const, 0, ""}, {"Second", Const, 0, ""}, {"September", Const, 0, ""}, {"Since", Func, 0, "func(t Time) Duration"}, {"Sleep", Func, 0, "func(d Duration)"}, {"Stamp", Const, 0, ""}, {"StampMicro", Const, 0, ""}, {"StampMilli", Const, 0, ""}, {"StampNano", Const, 0, ""}, {"Sunday", Const, 0, ""}, {"Thursday", Const, 0, ""}, {"Tick", Func, 0, "func(d Duration) <-chan Time"}, {"Ticker", Type, 0, ""}, {"Ticker.C", Field, 0, ""}, {"Time", Type, 0, ""}, {"TimeOnly", Const, 20, ""}, {"Timer", Type, 0, ""}, {"Timer.C", Field, 0, ""}, {"Tuesday", Const, 0, ""}, {"UTC", Var, 0, ""}, {"Unix", Func, 0, "func(sec int64, nsec int64) Time"}, {"UnixDate", Const, 0, ""}, {"UnixMicro", Func, 17, "func(usec int64) Time"}, {"UnixMilli", Func, 17, "func(msec int64) Time"}, {"Until", Func, 8, "func(t Time) Duration"}, {"Wednesday", Const, 0, ""}, {"Weekday", Type, 0, ""}, }, "unicode": { {"(SpecialCase).ToLower", Method, 0, ""}, {"(SpecialCase).ToTitle", Method, 0, ""}, {"(SpecialCase).ToUpper", Method, 0, ""}, {"ASCII_Hex_Digit", Var, 0, ""}, {"Adlam", Var, 7, ""}, {"Ahom", Var, 5, ""}, {"Anatolian_Hieroglyphs", Var, 5, ""}, {"Arabic", Var, 0, ""}, {"Armenian", Var, 0, ""}, {"Avestan", Var, 0, ""}, {"AzeriCase", Var, 0, ""}, {"Balinese", Var, 0, ""}, {"Bamum", Var, 0, ""}, {"Bassa_Vah", Var, 4, ""}, {"Batak", Var, 0, ""}, {"Bengali", Var, 0, ""}, {"Bhaiksuki", Var, 7, ""}, {"Bidi_Control", Var, 0, ""}, {"Bopomofo", Var, 0, ""}, {"Brahmi", Var, 0, ""}, {"Braille", Var, 0, ""}, {"Buginese", Var, 0, ""}, {"Buhid", Var, 0, ""}, {"C", Var, 0, ""}, {"Canadian_Aboriginal", Var, 0, ""}, {"Carian", Var, 0, ""}, {"CaseRange", Type, 0, ""}, {"CaseRange.Delta", Field, 0, ""}, {"CaseRange.Hi", Field, 0, ""}, {"CaseRange.Lo", Field, 0, ""}, {"CaseRanges", Var, 0, ""}, {"Categories", Var, 0, ""}, {"Caucasian_Albanian", Var, 4, ""}, {"Cc", Var, 0, ""}, {"Cf", Var, 0, ""}, {"Chakma", Var, 1, ""}, {"Cham", Var, 0, ""}, {"Cherokee", Var, 0, ""}, {"Chorasmian", Var, 16, ""}, {"Co", Var, 0, ""}, {"Common", Var, 0, ""}, {"Coptic", Var, 0, ""}, {"Cs", Var, 0, ""}, {"Cuneiform", Var, 0, ""}, {"Cypriot", Var, 0, ""}, {"Cypro_Minoan", Var, 21, ""}, {"Cyrillic", Var, 0, ""}, {"Dash", Var, 0, ""}, {"Deprecated", Var, 0, ""}, {"Deseret", Var, 0, ""}, {"Devanagari", Var, 0, ""}, {"Diacritic", Var, 0, ""}, {"Digit", Var, 0, ""}, {"Dives_Akuru", Var, 16, ""}, {"Dogra", Var, 13, ""}, {"Duployan", Var, 4, ""}, {"Egyptian_Hieroglyphs", Var, 0, ""}, {"Elbasan", Var, 4, ""}, {"Elymaic", Var, 14, ""}, {"Ethiopic", Var, 0, ""}, {"Extender", Var, 0, ""}, {"FoldCategory", Var, 0, ""}, {"FoldScript", Var, 0, ""}, {"Georgian", Var, 0, ""}, {"Glagolitic", Var, 0, ""}, {"Gothic", Var, 0, ""}, {"Grantha", Var, 4, ""}, {"GraphicRanges", Var, 0, ""}, {"Greek", Var, 0, ""}, {"Gujarati", Var, 0, ""}, {"Gunjala_Gondi", Var, 13, ""}, {"Gurmukhi", Var, 0, ""}, {"Han", Var, 0, ""}, {"Hangul", Var, 0, ""}, {"Hanifi_Rohingya", Var, 13, ""}, {"Hanunoo", Var, 0, ""}, {"Hatran", Var, 5, ""}, {"Hebrew", Var, 0, ""}, {"Hex_Digit", Var, 0, ""}, {"Hiragana", Var, 0, ""}, {"Hyphen", Var, 0, ""}, {"IDS_Binary_Operator", Var, 0, ""}, {"IDS_Trinary_Operator", Var, 0, ""}, {"Ideographic", Var, 0, ""}, {"Imperial_Aramaic", Var, 0, ""}, {"In", Func, 2, "func(r rune, ranges ...*RangeTable) bool"}, {"Inherited", Var, 0, ""}, {"Inscriptional_Pahlavi", Var, 0, ""}, {"Inscriptional_Parthian", Var, 0, ""}, {"Is", Func, 0, "func(rangeTab *RangeTable, r rune) bool"}, {"IsControl", Func, 0, "func(r rune) bool"}, {"IsDigit", Func, 0, "func(r rune) bool"}, {"IsGraphic", Func, 0, "func(r rune) bool"}, {"IsLetter", Func, 0, "func(r rune) bool"}, {"IsLower", Func, 0, "func(r rune) bool"}, {"IsMark", Func, 0, "func(r rune) bool"}, {"IsNumber", Func, 0, "func(r rune) bool"}, {"IsOneOf", Func, 0, "func(ranges []*RangeTable, r rune) bool"}, {"IsPrint", Func, 0, "func(r rune) bool"}, {"IsPunct", Func, 0, "func(r rune) bool"}, {"IsSpace", Func, 0, "func(r rune) bool"}, {"IsSymbol", Func, 0, "func(r rune) bool"}, {"IsTitle", Func, 0, "func(r rune) bool"}, {"IsUpper", Func, 0, "func(r rune) bool"}, {"Javanese", Var, 0, ""}, {"Join_Control", Var, 0, ""}, {"Kaithi", Var, 0, ""}, {"Kannada", Var, 0, ""}, {"Katakana", Var, 0, ""}, {"Kawi", Var, 21, ""}, {"Kayah_Li", Var, 0, ""}, {"Kharoshthi", Var, 0, ""}, {"Khitan_Small_Script", Var, 16, ""}, {"Khmer", Var, 0, ""}, {"Khojki", Var, 4, ""}, {"Khudawadi", Var, 4, ""}, {"L", Var, 0, ""}, {"Lao", Var, 0, ""}, {"Latin", Var, 0, ""}, {"Lepcha", Var, 0, ""}, {"Letter", Var, 0, ""}, {"Limbu", Var, 0, ""}, {"Linear_A", Var, 4, ""}, {"Linear_B", Var, 0, ""}, {"Lisu", Var, 0, ""}, {"Ll", Var, 0, ""}, {"Lm", Var, 0, ""}, {"Lo", Var, 0, ""}, {"Logical_Order_Exception", Var, 0, ""}, {"Lower", Var, 0, ""}, {"LowerCase", Const, 0, ""}, {"Lt", Var, 0, ""}, {"Lu", Var, 0, ""}, {"Lycian", Var, 0, ""}, {"Lydian", Var, 0, ""}, {"M", Var, 0, ""}, {"Mahajani", Var, 4, ""}, {"Makasar", Var, 13, ""}, {"Malayalam", Var, 0, ""}, {"Mandaic", Var, 0, ""}, {"Manichaean", Var, 4, ""}, {"Marchen", Var, 7, ""}, {"Mark", Var, 0, ""}, {"Masaram_Gondi", Var, 10, ""}, {"MaxASCII", Const, 0, ""}, {"MaxCase", Const, 0, ""}, {"MaxLatin1", Const, 0, ""}, {"MaxRune", Const, 0, ""}, {"Mc", Var, 0, ""}, {"Me", Var, 0, ""}, {"Medefaidrin", Var, 13, ""}, {"Meetei_Mayek", Var, 0, ""}, {"Mende_Kikakui", Var, 4, ""}, {"Meroitic_Cursive", Var, 1, ""}, {"Meroitic_Hieroglyphs", Var, 1, ""}, {"Miao", Var, 1, ""}, {"Mn", Var, 0, ""}, {"Modi", Var, 4, ""}, {"Mongolian", Var, 0, ""}, {"Mro", Var, 4, ""}, {"Multani", Var, 5, ""}, {"Myanmar", Var, 0, ""}, {"N", Var, 0, ""}, {"Nabataean", Var, 4, ""}, {"Nag_Mundari", Var, 21, ""}, {"Nandinagari", Var, 14, ""}, {"Nd", Var, 0, ""}, {"New_Tai_Lue", Var, 0, ""}, {"Newa", Var, 7, ""}, {"Nko", Var, 0, ""}, {"Nl", Var, 0, ""}, {"No", Var, 0, ""}, {"Noncharacter_Code_Point", Var, 0, ""}, {"Number", Var, 0, ""}, {"Nushu", Var, 10, ""}, {"Nyiakeng_Puachue_Hmong", Var, 14, ""}, {"Ogham", Var, 0, ""}, {"Ol_Chiki", Var, 0, ""}, {"Old_Hungarian", Var, 5, ""}, {"Old_Italic", Var, 0, ""}, {"Old_North_Arabian", Var, 4, ""}, {"Old_Permic", Var, 4, ""}, {"Old_Persian", Var, 0, ""}, {"Old_Sogdian", Var, 13, ""}, {"Old_South_Arabian", Var, 0, ""}, {"Old_Turkic", Var, 0, ""}, {"Old_Uyghur", Var, 21, ""}, {"Oriya", Var, 0, ""}, {"Osage", Var, 7, ""}, {"Osmanya", Var, 0, ""}, {"Other", Var, 0, ""}, {"Other_Alphabetic", Var, 0, ""}, {"Other_Default_Ignorable_Code_Point", Var, 0, ""}, {"Other_Grapheme_Extend", Var, 0, ""}, {"Other_ID_Continue", Var, 0, ""}, {"Other_ID_Start", Var, 0, ""}, {"Other_Lowercase", Var, 0, ""}, {"Other_Math", Var, 0, ""}, {"Other_Uppercase", Var, 0, ""}, {"P", Var, 0, ""}, {"Pahawh_Hmong", Var, 4, ""}, {"Palmyrene", Var, 4, ""}, {"Pattern_Syntax", Var, 0, ""}, {"Pattern_White_Space", Var, 0, ""}, {"Pau_Cin_Hau", Var, 4, ""}, {"Pc", Var, 0, ""}, {"Pd", Var, 0, ""}, {"Pe", Var, 0, ""}, {"Pf", Var, 0, ""}, {"Phags_Pa", Var, 0, ""}, {"Phoenician", Var, 0, ""}, {"Pi", Var, 0, ""}, {"Po", Var, 0, ""}, {"Prepended_Concatenation_Mark", Var, 7, ""}, {"PrintRanges", Var, 0, ""}, {"Properties", Var, 0, ""}, {"Ps", Var, 0, ""}, {"Psalter_Pahlavi", Var, 4, ""}, {"Punct", Var, 0, ""}, {"Quotation_Mark", Var, 0, ""}, {"Radical", Var, 0, ""}, {"Range16", Type, 0, ""}, {"Range16.Hi", Field, 0, ""}, {"Range16.Lo", Field, 0, ""}, {"Range16.Stride", Field, 0, ""}, {"Range32", Type, 0, ""}, {"Range32.Hi", Field, 0, ""}, {"Range32.Lo", Field, 0, ""}, {"Range32.Stride", Field, 0, ""}, {"RangeTable", Type, 0, ""}, {"RangeTable.LatinOffset", Field, 1, ""}, {"RangeTable.R16", Field, 0, ""}, {"RangeTable.R32", Field, 0, ""}, {"Regional_Indicator", Var, 10, ""}, {"Rejang", Var, 0, ""}, {"ReplacementChar", Const, 0, ""}, {"Runic", Var, 0, ""}, {"S", Var, 0, ""}, {"STerm", Var, 0, ""}, {"Samaritan", Var, 0, ""}, {"Saurashtra", Var, 0, ""}, {"Sc", Var, 0, ""}, {"Scripts", Var, 0, ""}, {"Sentence_Terminal", Var, 7, ""}, {"Sharada", Var, 1, ""}, {"Shavian", Var, 0, ""}, {"Siddham", Var, 4, ""}, {"SignWriting", Var, 5, ""}, {"SimpleFold", Func, 0, "func(r rune) rune"}, {"Sinhala", Var, 0, ""}, {"Sk", Var, 0, ""}, {"Sm", Var, 0, ""}, {"So", Var, 0, ""}, {"Soft_Dotted", Var, 0, ""}, {"Sogdian", Var, 13, ""}, {"Sora_Sompeng", Var, 1, ""}, {"Soyombo", Var, 10, ""}, {"Space", Var, 0, ""}, {"SpecialCase", Type, 0, ""}, {"Sundanese", Var, 0, ""}, {"Syloti_Nagri", Var, 0, ""}, {"Symbol", Var, 0, ""}, {"Syriac", Var, 0, ""}, {"Tagalog", Var, 0, ""}, {"Tagbanwa", Var, 0, ""}, {"Tai_Le", Var, 0, ""}, {"Tai_Tham", Var, 0, ""}, {"Tai_Viet", Var, 0, ""}, {"Takri", Var, 1, ""}, {"Tamil", Var, 0, ""}, {"Tangsa", Var, 21, ""}, {"Tangut", Var, 7, ""}, {"Telugu", Var, 0, ""}, {"Terminal_Punctuation", Var, 0, ""}, {"Thaana", Var, 0, ""}, {"Thai", Var, 0, ""}, {"Tibetan", Var, 0, ""}, {"Tifinagh", Var, 0, ""}, {"Tirhuta", Var, 4, ""}, {"Title", Var, 0, ""}, {"TitleCase", Const, 0, ""}, {"To", Func, 0, "func(_case int, r rune) rune"}, {"ToLower", Func, 0, "func(r rune) rune"}, {"ToTitle", Func, 0, "func(r rune) rune"}, {"ToUpper", Func, 0, "func(r rune) rune"}, {"Toto", Var, 21, ""}, {"TurkishCase", Var, 0, ""}, {"Ugaritic", Var, 0, ""}, {"Unified_Ideograph", Var, 0, ""}, {"Upper", Var, 0, ""}, {"UpperCase", Const, 0, ""}, {"UpperLower", Const, 0, ""}, {"Vai", Var, 0, ""}, {"Variation_Selector", Var, 0, ""}, {"Version", Const, 0, ""}, {"Vithkuqi", Var, 21, ""}, {"Wancho", Var, 14, ""}, {"Warang_Citi", Var, 4, ""}, {"White_Space", Var, 0, ""}, {"Yezidi", Var, 16, ""}, {"Yi", Var, 0, ""}, {"Z", Var, 0, ""}, {"Zanabazar_Square", Var, 10, ""}, {"Zl", Var, 0, ""}, {"Zp", Var, 0, ""}, {"Zs", Var, 0, ""}, }, "unicode/utf16": { {"AppendRune", Func, 20, "func(a []uint16, r rune) []uint16"}, {"Decode", Func, 0, "func(s []uint16) []rune"}, {"DecodeRune", Func, 0, "func(r1 rune, r2 rune) rune"}, {"Encode", Func, 0, "func(s []rune) []uint16"}, {"EncodeRune", Func, 0, "func(r rune) (r1 rune, r2 rune)"}, {"IsSurrogate", Func, 0, "func(r rune) bool"}, {"RuneLen", Func, 23, "func(r rune) int"}, }, "unicode/utf8": { {"AppendRune", Func, 18, "func(p []byte, r rune) []byte"}, {"DecodeLastRune", Func, 0, "func(p []byte) (r rune, size int)"}, {"DecodeLastRuneInString", Func, 0, "func(s string) (r rune, size int)"}, {"DecodeRune", Func, 0, "func(p []byte) (r rune, size int)"}, {"DecodeRuneInString", Func, 0, "func(s string) (r rune, size int)"}, {"EncodeRune", Func, 0, "func(p []byte, r rune) int"}, {"FullRune", Func, 0, "func(p []byte) bool"}, {"FullRuneInString", Func, 0, "func(s string) bool"}, {"MaxRune", Const, 0, ""}, {"RuneCount", Func, 0, "func(p []byte) int"}, {"RuneCountInString", Func, 0, "func(s string) (n int)"}, {"RuneError", Const, 0, ""}, {"RuneLen", Func, 0, "func(r rune) int"}, {"RuneSelf", Const, 0, ""}, {"RuneStart", Func, 0, "func(b byte) bool"}, {"UTFMax", Const, 0, ""}, {"Valid", Func, 0, "func(p []byte) bool"}, {"ValidRune", Func, 1, "func(r rune) bool"}, {"ValidString", Func, 0, "func(s string) bool"}, }, "unique": { {"(Handle).Value", Method, 23, ""}, {"Handle", Type, 23, ""}, {"Make", Func, 23, "func[T comparable](value T) Handle[T]"}, }, "unsafe": { {"Add", Func, 0, ""}, {"Alignof", Func, 0, ""}, {"Offsetof", Func, 0, ""}, {"Pointer", Type, 0, ""}, {"Sizeof", Func, 0, ""}, {"Slice", Func, 0, ""}, {"SliceData", Func, 0, ""}, {"String", Func, 0, ""}, {"StringData", Func, 0, ""}, }, "weak": { {"(Pointer).Value", Method, 24, ""}, {"Make", Func, 24, "func[T any](ptr *T) Pointer[T]"}, {"Pointer", Type, 24, ""}, }, } -- diff -- @@ -8,17669 +8,17669 @@ var PackageSymbols = map[string][]Symbol{ "archive/tar": { - {"(*Header).FileInfo", Method, 1}, - {"(*Reader).Next", Method, 0}, - {"(*Reader).Read", Method, 0}, - {"(*Writer).AddFS", Method, 22}, - {"(*Writer).Close", Method, 0}, - {"(*Writer).Flush", Method, 0}, - {"(*Writer).Write", Method, 0}, - {"(*Writer).WriteHeader", Method, 0}, - {"(Format).String", Method, 10}, - {"ErrFieldTooLong", Var, 0}, - {"ErrHeader", Var, 0}, - {"ErrInsecurePath", Var, 20}, - {"ErrWriteAfterClose", Var, 0}, - {"ErrWriteTooLong", Var, 0}, - {"FileInfoHeader", Func, 1}, - {"FileInfoNames", Type, 23}, - {"Format", Type, 10}, - {"FormatGNU", Const, 10}, - {"FormatPAX", Const, 10}, - {"FormatUSTAR", Const, 10}, - {"FormatUnknown", Const, 10}, - {"Header", Type, 0}, - {"Header.AccessTime", Field, 0}, - {"Header.ChangeTime", Field, 0}, - {"Header.Devmajor", Field, 0}, - {"Header.Devminor", Field, 0}, - {"Header.Format", Field, 10}, - {"Header.Gid", Field, 0}, - {"Header.Gname", Field, 0}, - {"Header.Linkname", Field, 0}, - {"Header.ModTime", Field, 0}, - {"Header.Mode", Field, 0}, - {"Header.Name", Field, 0}, - {"Header.PAXRecords", Field, 10}, - {"Header.Size", Field, 0}, - {"Header.Typeflag", Field, 0}, - {"Header.Uid", Field, 0}, - {"Header.Uname", Field, 0}, - {"Header.Xattrs", Field, 3}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"Reader", Type, 0}, - {"TypeBlock", Const, 0}, - {"TypeChar", Const, 0}, - {"TypeCont", Const, 0}, - {"TypeDir", Const, 0}, - {"TypeFifo", Const, 0}, - {"TypeGNULongLink", Const, 1}, - {"TypeGNULongName", Const, 1}, - {"TypeGNUSparse", Const, 3}, - {"TypeLink", Const, 0}, - {"TypeReg", Const, 0}, - {"TypeRegA", Const, 0}, - {"TypeSymlink", Const, 0}, - {"TypeXGlobalHeader", Const, 0}, - {"TypeXHeader", Const, 0}, - {"Writer", Type, 0}, + {"(*Header).FileInfo", Method, 1, ""}, + {"(*Reader).Next", Method, 0, ""}, + {"(*Reader).Read", Method, 0, ""}, + {"(*Writer).AddFS", Method, 22, ""}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).Flush", Method, 0, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"(*Writer).WriteHeader", Method, 0, ""}, + {"(Format).String", Method, 10, ""}, + {"ErrFieldTooLong", Var, 0, ""}, + {"ErrHeader", Var, 0, ""}, + {"ErrInsecurePath", Var, 20, ""}, + {"ErrWriteAfterClose", Var, 0, ""}, + {"ErrWriteTooLong", Var, 0, ""}, + {"FileInfoHeader", Func, 1, "func(fi fs.FileInfo, link string) (*Header, error)"}, + {"FileInfoNames", Type, 23, ""}, + {"Format", Type, 10, ""}, + {"FormatGNU", Const, 10, ""}, + {"FormatPAX", Const, 10, ""}, + {"FormatUSTAR", Const, 10, ""}, + {"FormatUnknown", Const, 10, ""}, + {"Header", Type, 0, ""}, + {"Header.AccessTime", Field, 0, ""}, + {"Header.ChangeTime", Field, 0, ""}, + {"Header.Devmajor", Field, 0, ""}, + {"Header.Devminor", Field, 0, ""}, + {"Header.Format", Field, 10, ""}, + {"Header.Gid", Field, 0, ""}, + {"Header.Gname", Field, 0, ""}, + {"Header.Linkname", Field, 0, ""}, + {"Header.ModTime", Field, 0, ""}, + {"Header.Mode", Field, 0, ""}, + {"Header.Name", Field, 0, ""}, + {"Header.PAXRecords", Field, 10, ""}, + {"Header.Size", Field, 0, ""}, + {"Header.Typeflag", Field, 0, ""}, + {"Header.Uid", Field, 0, ""}, + {"Header.Uname", Field, 0, ""}, + {"Header.Xattrs", Field, 3, ""}, + {"NewReader", Func, 0, "func(r io.Reader) *Reader"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"Reader", Type, 0, ""}, + {"TypeBlock", Const, 0, ""}, + {"TypeChar", Const, 0, ""}, + {"TypeCont", Const, 0, ""}, + {"TypeDir", Const, 0, ""}, + {"TypeFifo", Const, 0, ""}, + {"TypeGNULongLink", Const, 1, ""}, + {"TypeGNULongName", Const, 1, ""}, + {"TypeGNUSparse", Const, 3, ""}, + {"TypeLink", Const, 0, ""}, + {"TypeReg", Const, 0, ""}, + {"TypeRegA", Const, 0, ""}, + {"TypeSymlink", Const, 0, ""}, + {"TypeXGlobalHeader", Const, 0, ""}, + {"TypeXHeader", Const, 0, ""}, + {"Writer", Type, 0, ""}, }, "archive/zip": { - {"(*File).DataOffset", Method, 2}, - {"(*File).FileInfo", Method, 0}, - {"(*File).ModTime", Method, 0}, - {"(*File).Mode", Method, 0}, - {"(*File).Open", Method, 0}, - {"(*File).OpenRaw", Method, 17}, - {"(*File).SetModTime", Method, 0}, - {"(*File).SetMode", Method, 0}, - {"(*FileHeader).FileInfo", Method, 0}, - {"(*FileHeader).ModTime", Method, 0}, - {"(*FileHeader).Mode", Method, 0}, - {"(*FileHeader).SetModTime", Method, 0}, - {"(*FileHeader).SetMode", Method, 0}, - {"(*ReadCloser).Close", Method, 0}, - {"(*ReadCloser).Open", Method, 16}, - {"(*ReadCloser).RegisterDecompressor", Method, 6}, - {"(*Reader).Open", Method, 16}, - {"(*Reader).RegisterDecompressor", Method, 6}, - {"(*Writer).AddFS", Method, 22}, - {"(*Writer).Close", Method, 0}, - {"(*Writer).Copy", Method, 17}, - {"(*Writer).Create", Method, 0}, - {"(*Writer).CreateHeader", Method, 0}, - {"(*Writer).CreateRaw", Method, 17}, - {"(*Writer).Flush", Method, 4}, - {"(*Writer).RegisterCompressor", Method, 6}, - {"(*Writer).SetComment", Method, 10}, - {"(*Writer).SetOffset", Method, 5}, - {"Compressor", Type, 2}, - {"Decompressor", Type, 2}, - {"Deflate", Const, 0}, - {"ErrAlgorithm", Var, 0}, - {"ErrChecksum", Var, 0}, - {"ErrFormat", Var, 0}, - {"ErrInsecurePath", Var, 20}, - {"File", Type, 0}, - {"File.FileHeader", Field, 0}, - {"FileHeader", Type, 0}, - {"FileHeader.CRC32", Field, 0}, - {"FileHeader.Comment", Field, 0}, - {"FileHeader.CompressedSize", Field, 0}, - {"FileHeader.CompressedSize64", Field, 1}, - {"FileHeader.CreatorVersion", Field, 0}, - {"FileHeader.ExternalAttrs", Field, 0}, - {"FileHeader.Extra", Field, 0}, - {"FileHeader.Flags", Field, 0}, - {"FileHeader.Method", Field, 0}, - {"FileHeader.Modified", Field, 10}, - {"FileHeader.ModifiedDate", Field, 0}, - {"FileHeader.ModifiedTime", Field, 0}, - {"FileHeader.Name", Field, 0}, - {"FileHeader.NonUTF8", Field, 10}, - {"FileHeader.ReaderVersion", Field, 0}, - {"FileHeader.UncompressedSize", Field, 0}, - {"FileHeader.UncompressedSize64", Field, 1}, - {"FileInfoHeader", Func, 0}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"OpenReader", Func, 0}, - {"ReadCloser", Type, 0}, - {"ReadCloser.Reader", Field, 0}, - {"Reader", Type, 0}, - {"Reader.Comment", Field, 0}, - {"Reader.File", Field, 0}, - {"RegisterCompressor", Func, 2}, - {"RegisterDecompressor", Func, 2}, - {"Store", Const, 0}, - {"Writer", Type, 0}, + {"(*File).DataOffset", Method, 2, ""}, + {"(*File).FileInfo", Method, 0, ""}, + {"(*File).ModTime", Method, 0, ""}, + {"(*File).Mode", Method, 0, ""}, + {"(*File).Open", Method, 0, ""}, + {"(*File).OpenRaw", Method, 17, ""}, + {"(*File).SetModTime", Method, 0, ""}, + {"(*File).SetMode", Method, 0, ""}, + {"(*FileHeader).FileInfo", Method, 0, ""}, + {"(*FileHeader).ModTime", Method, 0, ""}, + {"(*FileHeader).Mode", Method, 0, ""}, + {"(*FileHeader).SetModTime", Method, 0, ""}, + {"(*FileHeader).SetMode", Method, 0, ""}, + {"(*ReadCloser).Close", Method, 0, ""}, + {"(*ReadCloser).Open", Method, 16, ""}, + {"(*ReadCloser).RegisterDecompressor", Method, 6, ""}, + {"(*Reader).Open", Method, 16, ""}, + {"(*Reader).RegisterDecompressor", Method, 6, ""}, + {"(*Writer).AddFS", Method, 22, ""}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).Copy", Method, 17, ""}, + {"(*Writer).Create", Method, 0, ""}, + {"(*Writer).CreateHeader", Method, 0, ""}, + {"(*Writer).CreateRaw", Method, 17, ""}, + {"(*Writer).Flush", Method, 4, ""}, + {"(*Writer).RegisterCompressor", Method, 6, ""}, + {"(*Writer).SetComment", Method, 10, ""}, + {"(*Writer).SetOffset", Method, 5, ""}, + {"Compressor", Type, 2, ""}, + {"Decompressor", Type, 2, ""}, + {"Deflate", Const, 0, ""}, + {"ErrAlgorithm", Var, 0, ""}, + {"ErrChecksum", Var, 0, ""}, + {"ErrFormat", Var, 0, ""}, + {"ErrInsecurePath", Var, 20, ""}, + {"File", Type, 0, ""}, + {"File.FileHeader", Field, 0, ""}, + {"FileHeader", Type, 0, ""}, + {"FileHeader.CRC32", Field, 0, ""}, + {"FileHeader.Comment", Field, 0, ""}, + {"FileHeader.CompressedSize", Field, 0, ""}, + {"FileHeader.CompressedSize64", Field, 1, ""}, + {"FileHeader.CreatorVersion", Field, 0, ""}, + {"FileHeader.ExternalAttrs", Field, 0, ""}, + {"FileHeader.Extra", Field, 0, ""}, + {"FileHeader.Flags", Field, 0, ""}, + {"FileHeader.Method", Field, 0, ""}, + {"FileHeader.Modified", Field, 10, ""}, + {"FileHeader.ModifiedDate", Field, 0, ""}, + {"FileHeader.ModifiedTime", Field, 0, ""}, + {"FileHeader.Name", Field, 0, ""}, + {"FileHeader.NonUTF8", Field, 10, ""}, + {"FileHeader.ReaderVersion", Field, 0, ""}, + {"FileHeader.UncompressedSize", Field, 0, ""}, + {"FileHeader.UncompressedSize64", Field, 1, ""}, + {"FileInfoHeader", Func, 0, "func(fi fs.FileInfo) (*FileHeader, error)"}, + {"NewReader", Func, 0, "func(r io.ReaderAt, size int64) (*Reader, error)"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"OpenReader", Func, 0, "func(name string) (*ReadCloser, error)"}, + {"ReadCloser", Type, 0, ""}, + {"ReadCloser.Reader", Field, 0, ""}, + {"Reader", Type, 0, ""}, + {"Reader.Comment", Field, 0, ""}, + {"Reader.File", Field, 0, ""}, + {"RegisterCompressor", Func, 2, "func(method uint16, comp Compressor)"}, + {"RegisterDecompressor", Func, 2, "func(method uint16, dcomp Decompressor)"}, + {"Store", Const, 0, ""}, + {"Writer", Type, 0, ""}, }, "bufio": { - {"(*Reader).Buffered", Method, 0}, - {"(*Reader).Discard", Method, 5}, - {"(*Reader).Peek", Method, 0}, - {"(*Reader).Read", Method, 0}, - {"(*Reader).ReadByte", Method, 0}, - {"(*Reader).ReadBytes", Method, 0}, - {"(*Reader).ReadLine", Method, 0}, - {"(*Reader).ReadRune", Method, 0}, - {"(*Reader).ReadSlice", Method, 0}, - {"(*Reader).ReadString", Method, 0}, - {"(*Reader).Reset", Method, 2}, - {"(*Reader).Size", Method, 10}, - {"(*Reader).UnreadByte", Method, 0}, - {"(*Reader).UnreadRune", Method, 0}, - {"(*Reader).WriteTo", Method, 1}, - {"(*Scanner).Buffer", Method, 6}, - {"(*Scanner).Bytes", Method, 1}, - {"(*Scanner).Err", Method, 1}, - {"(*Scanner).Scan", Method, 1}, - {"(*Scanner).Split", Method, 1}, - {"(*Scanner).Text", Method, 1}, - {"(*Writer).Available", Method, 0}, - {"(*Writer).AvailableBuffer", Method, 18}, - {"(*Writer).Buffered", Method, 0}, - {"(*Writer).Flush", Method, 0}, - {"(*Writer).ReadFrom", Method, 1}, - {"(*Writer).Reset", Method, 2}, - {"(*Writer).Size", Method, 10}, - {"(*Writer).Write", Method, 0}, - {"(*Writer).WriteByte", Method, 0}, - {"(*Writer).WriteRune", Method, 0}, - {"(*Writer).WriteString", Method, 0}, - {"(ReadWriter).Available", Method, 0}, - {"(ReadWriter).AvailableBuffer", Method, 18}, - {"(ReadWriter).Discard", Method, 5}, - {"(ReadWriter).Flush", Method, 0}, - {"(ReadWriter).Peek", Method, 0}, - {"(ReadWriter).Read", Method, 0}, - {"(ReadWriter).ReadByte", Method, 0}, - {"(ReadWriter).ReadBytes", Method, 0}, - {"(ReadWriter).ReadFrom", Method, 1}, - {"(ReadWriter).ReadLine", Method, 0}, - {"(ReadWriter).ReadRune", Method, 0}, - {"(ReadWriter).ReadSlice", Method, 0}, - {"(ReadWriter).ReadString", Method, 0}, - {"(ReadWriter).UnreadByte", Method, 0}, - {"(ReadWriter).UnreadRune", Method, 0}, - {"(ReadWriter).Write", Method, 0}, - {"(ReadWriter).WriteByte", Method, 0}, - {"(ReadWriter).WriteRune", Method, 0}, - {"(ReadWriter).WriteString", Method, 0}, - {"(ReadWriter).WriteTo", Method, 1}, - {"ErrAdvanceTooFar", Var, 1}, - {"ErrBadReadCount", Var, 15}, - {"ErrBufferFull", Var, 0}, - {"ErrFinalToken", Var, 6}, - {"ErrInvalidUnreadByte", Var, 0}, - {"ErrInvalidUnreadRune", Var, 0}, - {"ErrNegativeAdvance", Var, 1}, - {"ErrNegativeCount", Var, 0}, - {"ErrTooLong", Var, 1}, - {"MaxScanTokenSize", Const, 1}, - {"NewReadWriter", Func, 0}, - {"NewReader", Func, 0}, - {"NewReaderSize", Func, 0}, - {"NewScanner", Func, 1}, - {"NewWriter", Func, 0}, - {"NewWriterSize", Func, 0}, - {"ReadWriter", Type, 0}, - {"ReadWriter.Reader", Field, 0}, - {"ReadWriter.Writer", Field, 0}, - {"Reader", Type, 0}, - {"ScanBytes", Func, 1}, - {"ScanLines", Func, 1}, - {"ScanRunes", Func, 1}, - {"ScanWords", Func, 1}, - {"Scanner", Type, 1}, - {"SplitFunc", Type, 1}, - {"Writer", Type, 0}, + {"(*Reader).Buffered", Method, 0, ""}, + {"(*Reader).Discard", Method, 5, ""}, + {"(*Reader).Peek", Method, 0, ""}, + {"(*Reader).Read", Method, 0, ""}, + {"(*Reader).ReadByte", Method, 0, ""}, + {"(*Reader).ReadBytes", Method, 0, ""}, + {"(*Reader).ReadLine", Method, 0, ""}, + {"(*Reader).ReadRune", Method, 0, ""}, + {"(*Reader).ReadSlice", Method, 0, ""}, + {"(*Reader).ReadString", Method, 0, ""}, + {"(*Reader).Reset", Method, 2, ""}, + {"(*Reader).Size", Method, 10, ""}, + {"(*Reader).UnreadByte", Method, 0, ""}, + {"(*Reader).UnreadRune", Method, 0, ""}, + {"(*Reader).WriteTo", Method, 1, ""}, + {"(*Scanner).Buffer", Method, 6, ""}, + {"(*Scanner).Bytes", Method, 1, ""}, + {"(*Scanner).Err", Method, 1, ""}, + {"(*Scanner).Scan", Method, 1, ""}, + {"(*Scanner).Split", Method, 1, ""}, + {"(*Scanner).Text", Method, 1, ""}, + {"(*Writer).Available", Method, 0, ""}, + {"(*Writer).AvailableBuffer", Method, 18, ""}, + {"(*Writer).Buffered", Method, 0, ""}, + {"(*Writer).Flush", Method, 0, ""}, + {"(*Writer).ReadFrom", Method, 1, ""}, + {"(*Writer).Reset", Method, 2, ""}, + {"(*Writer).Size", Method, 10, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"(*Writer).WriteByte", Method, 0, ""}, + {"(*Writer).WriteRune", Method, 0, ""}, + {"(*Writer).WriteString", Method, 0, ""}, + {"(ReadWriter).Available", Method, 0, ""}, + {"(ReadWriter).AvailableBuffer", Method, 18, ""}, + {"(ReadWriter).Discard", Method, 5, ""}, + {"(ReadWriter).Flush", Method, 0, ""}, + {"(ReadWriter).Peek", Method, 0, ""}, + {"(ReadWriter).Read", Method, 0, ""}, + {"(ReadWriter).ReadByte", Method, 0, ""}, + {"(ReadWriter).ReadBytes", Method, 0, ""}, + {"(ReadWriter).ReadFrom", Method, 1, ""}, + {"(ReadWriter).ReadLine", Method, 0, ""}, + {"(ReadWriter).ReadRune", Method, 0, ""}, + {"(ReadWriter).ReadSlice", Method, 0, ""}, + {"(ReadWriter).ReadString", Method, 0, ""}, + {"(ReadWriter).UnreadByte", Method, 0, ""}, + {"(ReadWriter).UnreadRune", Method, 0, ""}, + {"(ReadWriter).Write", Method, 0, ""}, + {"(ReadWriter).WriteByte", Method, 0, ""}, + {"(ReadWriter).WriteRune", Method, 0, ""}, + {"(ReadWriter).WriteString", Method, 0, ""}, + {"(ReadWriter).WriteTo", Method, 1, ""}, + {"ErrAdvanceTooFar", Var, 1, ""}, + {"ErrBadReadCount", Var, 15, ""}, + {"ErrBufferFull", Var, 0, ""}, + {"ErrFinalToken", Var, 6, ""}, + {"ErrInvalidUnreadByte", Var, 0, ""}, + {"ErrInvalidUnreadRune", Var, 0, ""}, + {"ErrNegativeAdvance", Var, 1, ""}, + {"ErrNegativeCount", Var, 0, ""}, + {"ErrTooLong", Var, 1, ""}, + {"MaxScanTokenSize", Const, 1, ""}, + {"NewReadWriter", Func, 0, "func(r *Reader, w *Writer) *ReadWriter"}, + {"NewReader", Func, 0, "func(rd io.Reader) *Reader"}, + {"NewReaderSize", Func, 0, "func(rd io.Reader, size int) *Reader"}, + {"NewScanner", Func, 1, "func(r io.Reader) *Scanner"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"NewWriterSize", Func, 0, "func(w io.Writer, size int) *Writer"}, + {"ReadWriter", Type, 0, ""}, + {"ReadWriter.Reader", Field, 0, ""}, + {"ReadWriter.Writer", Field, 0, ""}, + {"Reader", Type, 0, ""}, + {"ScanBytes", Func, 1, "func(data []byte, atEOF bool) (advance int, token []byte, err error)"}, + {"ScanLines", Func, 1, "func(data []byte, atEOF bool) (advance int, token []byte, err error)"}, + {"ScanRunes", Func, 1, "func(data []byte, atEOF bool) (advance int, token []byte, err error)"}, + {"ScanWords", Func, 1, "func(data []byte, atEOF bool) (advance int, token []byte, err error)"}, + {"Scanner", Type, 1, ""}, + {"SplitFunc", Type, 1, ""}, + {"Writer", Type, 0, ""}, }, "bytes": { - {"(*Buffer).Available", Method, 21}, - {"(*Buffer).AvailableBuffer", Method, 21}, - {"(*Buffer).Bytes", Method, 0}, - {"(*Buffer).Cap", Method, 5}, - {"(*Buffer).Grow", Method, 1}, - {"(*Buffer).Len", Method, 0}, - {"(*Buffer).Next", Method, 0}, - {"(*Buffer).Read", Method, 0}, - {"(*Buffer).ReadByte", Method, 0}, - {"(*Buffer).ReadBytes", Method, 0}, - {"(*Buffer).ReadFrom", Method, 0}, - {"(*Buffer).ReadRune", Method, 0}, - {"(*Buffer).ReadString", Method, 0}, - {"(*Buffer).Reset", Method, 0}, - {"(*Buffer).String", Method, 0}, - {"(*Buffer).Truncate", Method, 0}, - {"(*Buffer).UnreadByte", Method, 0}, - {"(*Buffer).UnreadRune", Method, 0}, - {"(*Buffer).Write", Method, 0}, - {"(*Buffer).WriteByte", Method, 0}, - {"(*Buffer).WriteRune", Method, 0}, - {"(*Buffer).WriteString", Method, 0}, - {"(*Buffer).WriteTo", Method, 0}, - {"(*Reader).Len", Method, 0}, - {"(*Reader).Read", Method, 0}, - {"(*Reader).ReadAt", Method, 0}, - {"(*Reader).ReadByte", Method, 0}, - {"(*Reader).ReadRune", Method, 0}, - {"(*Reader).Reset", Method, 7}, - {"(*Reader).Seek", Method, 0}, - {"(*Reader).Size", Method, 5}, - {"(*Reader).UnreadByte", Method, 0}, - {"(*Reader).UnreadRune", Method, 0}, - {"(*Reader).WriteTo", Method, 1}, - {"Buffer", Type, 0}, - {"Clone", Func, 20}, - {"Compare", Func, 0}, - {"Contains", Func, 0}, - {"ContainsAny", Func, 7}, - {"ContainsFunc", Func, 21}, - {"ContainsRune", Func, 7}, - {"Count", Func, 0}, - {"Cut", Func, 18}, - {"CutPrefix", Func, 20}, - {"CutSuffix", Func, 20}, - {"Equal", Func, 0}, - {"EqualFold", Func, 0}, - {"ErrTooLarge", Var, 0}, - {"Fields", Func, 0}, - {"FieldsFunc", Func, 0}, - {"FieldsFuncSeq", Func, 24}, - {"FieldsSeq", Func, 24}, - {"HasPrefix", Func, 0}, - {"HasSuffix", Func, 0}, - {"Index", Func, 0}, - {"IndexAny", Func, 0}, - {"IndexByte", Func, 0}, - {"IndexFunc", Func, 0}, - {"IndexRune", Func, 0}, - {"Join", Func, 0}, - {"LastIndex", Func, 0}, - {"LastIndexAny", Func, 0}, - {"LastIndexByte", Func, 5}, - {"LastIndexFunc", Func, 0}, - {"Lines", Func, 24}, - {"Map", Func, 0}, - {"MinRead", Const, 0}, - {"NewBuffer", Func, 0}, - {"NewBufferString", Func, 0}, - {"NewReader", Func, 0}, - {"Reader", Type, 0}, - {"Repeat", Func, 0}, - {"Replace", Func, 0}, - {"ReplaceAll", Func, 12}, - {"Runes", Func, 0}, - {"Split", Func, 0}, - {"SplitAfter", Func, 0}, - {"SplitAfterN", Func, 0}, - {"SplitAfterSeq", Func, 24}, - {"SplitN", Func, 0}, - {"SplitSeq", Func, 24}, - {"Title", Func, 0}, - {"ToLower", Func, 0}, - {"ToLowerSpecial", Func, 0}, - {"ToTitle", Func, 0}, - {"ToTitleSpecial", Func, 0}, - {"ToUpper", Func, 0}, - {"ToUpperSpecial", Func, 0}, - {"ToValidUTF8", Func, 13}, - {"Trim", Func, 0}, - {"TrimFunc", Func, 0}, - {"TrimLeft", Func, 0}, - {"TrimLeftFunc", Func, 0}, - {"TrimPrefix", Func, 1}, - {"TrimRight", Func, 0}, - {"TrimRightFunc", Func, 0}, - {"TrimSpace", Func, 0}, - {"TrimSuffix", Func, 1}, + {"(*Buffer).Available", Method, 21, ""}, + {"(*Buffer).AvailableBuffer", Method, 21, ""}, + {"(*Buffer).Bytes", Method, 0, ""}, + {"(*Buffer).Cap", Method, 5, ""}, + {"(*Buffer).Grow", Method, 1, ""}, + {"(*Buffer).Len", Method, 0, ""}, + {"(*Buffer).Next", Method, 0, ""}, + {"(*Buffer).Read", Method, 0, ""}, + {"(*Buffer).ReadByte", Method, 0, ""}, + {"(*Buffer).ReadBytes", Method, 0, ""}, + {"(*Buffer).ReadFrom", Method, 0, ""}, + {"(*Buffer).ReadRune", Method, 0, ""}, + {"(*Buffer).ReadString", Method, 0, ""}, + {"(*Buffer).Reset", Method, 0, ""}, + {"(*Buffer).String", Method, 0, ""}, + {"(*Buffer).Truncate", Method, 0, ""}, + {"(*Buffer).UnreadByte", Method, 0, ""}, + {"(*Buffer).UnreadRune", Method, 0, ""}, + {"(*Buffer).Write", Method, 0, ""}, + {"(*Buffer).WriteByte", Method, 0, ""}, + {"(*Buffer).WriteRune", Method, 0, ""}, + {"(*Buffer).WriteString", Method, 0, ""}, + {"(*Buffer).WriteTo", Method, 0, ""}, + {"(*Reader).Len", Method, 0, ""}, + {"(*Reader).Read", Method, 0, ""}, + {"(*Reader).ReadAt", Method, 0, ""}, + {"(*Reader).ReadByte", Method, 0, ""}, + {"(*Reader).ReadRune", Method, 0, ""}, + {"(*Reader).Reset", Method, 7, ""}, + {"(*Reader).Seek", Method, 0, ""}, + {"(*Reader).Size", Method, 5, ""}, + {"(*Reader).UnreadByte", Method, 0, ""}, + {"(*Reader).UnreadRune", Method, 0, ""}, + {"(*Reader).WriteTo", Method, 1, ""}, + {"Buffer", Type, 0, ""}, + {"Clone", Func, 20, "func(b []byte) []byte"}, + {"Compare", Func, 0, "func(a []byte, b []byte) int"}, + {"Contains", Func, 0, "func(b []byte, subslice []byte) bool"}, + {"ContainsAny", Func, 7, "func(b []byte, chars string) bool"}, + {"ContainsFunc", Func, 21, "func(b []byte, f func(rune) bool) bool"}, + {"ContainsRune", Func, 7, "func(b []byte, r rune) bool"}, + {"Count", Func, 0, "func(s []byte, sep []byte) int"}, + {"Cut", Func, 18, "func(s []byte, sep []byte) (before []byte, after []byte, found bool)"}, + {"CutPrefix", Func, 20, "func(s []byte, prefix []byte) (after []byte, found bool)"}, + {"CutSuffix", Func, 20, "func(s []byte, suffix []byte) (before []byte, found bool)"}, + {"Equal", Func, 0, "func(a []byte, b []byte) bool"}, + {"EqualFold", Func, 0, "func(s []byte, t []byte) bool"}, + {"ErrTooLarge", Var, 0, ""}, + {"Fields", Func, 0, "func(s []byte) [][]byte"}, + {"FieldsFunc", Func, 0, "func(s []byte, f func(rune) bool) [][]byte"}, + {"FieldsFuncSeq", Func, 24, "func(s []byte, f func(rune) bool) iter.Seq[[]byte]"}, + {"FieldsSeq", Func, 24, "func(s []byte) iter.Seq[[]byte]"}, + {"HasPrefix", Func, 0, "func(s []byte, prefix []byte) bool"}, + {"HasSuffix", Func, 0, "func(s []byte, suffix []byte) bool"}, + {"Index", Func, 0, "func(s []byte, sep []byte) int"}, + {"IndexAny", Func, 0, "func(s []byte, chars string) int"}, + {"IndexByte", Func, 0, "func(b []byte, c byte) int"}, + {"IndexFunc", Func, 0, "func(s []byte, f func(r rune) bool) int"}, + {"IndexRune", Func, 0, "func(s []byte, r rune) int"}, + {"Join", Func, 0, "func(s [][]byte, sep []byte) []byte"}, + {"LastIndex", Func, 0, "func(s []byte, sep []byte) int"}, + {"LastIndexAny", Func, 0, "func(s []byte, chars string) int"}, + {"LastIndexByte", Func, 5, "func(s []byte, c byte) int"}, + {"LastIndexFunc", Func, 0, "func(s []byte, f func(r rune) bool) int"}, + {"Lines", Func, 24, "func(s []byte) iter.Seq[[]byte]"}, + {"Map", Func, 0, "func(mapping func(r rune) rune, s []byte) []byte"}, + {"MinRead", Const, 0, ""}, + {"NewBuffer", Func, 0, "func(buf []byte) *Buffer"}, + {"NewBufferString", Func, 0, "func(s string) *Buffer"}, + {"NewReader", Func, 0, "func(b []byte) *Reader"}, + {"Reader", Type, 0, ""}, + {"Repeat", Func, 0, "func(b []byte, count int) []byte"}, + {"Replace", Func, 0, "func(s []byte, old []byte, new []byte, n int) []byte"}, + {"ReplaceAll", Func, 12, "func(s []byte, old []byte, new []byte) []byte"}, + {"Runes", Func, 0, "func(s []byte) []rune"}, + {"Split", Func, 0, "func(s []byte, sep []byte) [][]byte"}, + {"SplitAfter", Func, 0, "func(s []byte, sep []byte) [][]byte"}, + {"SplitAfterN", Func, 0, "func(s []byte, sep []byte, n int) [][]byte"}, + {"SplitAfterSeq", Func, 24, "func(s []byte, sep []byte) iter.Seq[[]byte]"}, + {"SplitN", Func, 0, "func(s []byte, sep []byte, n int) [][]byte"}, + {"SplitSeq", Func, 24, "func(s []byte, sep []byte) iter.Seq[[]byte]"}, + {"Title", Func, 0, "func(s []byte) []byte"}, + {"ToLower", Func, 0, "func(s []byte) []byte"}, + {"ToLowerSpecial", Func, 0, "func(c unicode.SpecialCase, s []byte) []byte"}, + {"ToTitle", Func, 0, "func(s []byte) []byte"}, + {"ToTitleSpecial", Func, 0, "func(c unicode.SpecialCase, s []byte) []byte"}, + {"ToUpper", Func, 0, "func(s []byte) []byte"}, + {"ToUpperSpecial", Func, 0, "func(c unicode.SpecialCase, s []byte) []byte"}, + {"ToValidUTF8", Func, 13, "func(s []byte, replacement []byte) []byte"}, + {"Trim", Func, 0, "func(s []byte, cutset string) []byte"}, + {"TrimFunc", Func, 0, "func(s []byte, f func(r rune) bool) []byte"}, + {"TrimLeft", Func, 0, "func(s []byte, cutset string) []byte"}, + {"TrimLeftFunc", Func, 0, "func(s []byte, f func(r rune) bool) []byte"}, + {"TrimPrefix", Func, 1, "func(s []byte, prefix []byte) []byte"}, + {"TrimRight", Func, 0, "func(s []byte, cutset string) []byte"}, + {"TrimRightFunc", Func, 0, "func(s []byte, f func(r rune) bool) []byte"}, + {"TrimSpace", Func, 0, "func(s []byte) []byte"}, + {"TrimSuffix", Func, 1, "func(s []byte, suffix []byte) []byte"}, }, "cmp": { - {"Compare", Func, 21}, - {"Less", Func, 21}, - {"Or", Func, 22}, - {"Ordered", Type, 21}, + {"Compare", Func, 21, "func[T Ordered](x T, y T) int"}, + {"Less", Func, 21, "func[T Ordered](x T, y T) bool"}, + {"Or", Func, 22, "func[T comparable](vals ...T) T"}, + {"Ordered", Type, 21, ""}, }, "compress/bzip2": { - {"(StructuralError).Error", Method, 0}, - {"NewReader", Func, 0}, - {"StructuralError", Type, 0}, + {"(StructuralError).Error", Method, 0, ""}, + {"NewReader", Func, 0, "func(r io.Reader) io.Reader"}, + {"StructuralError", Type, 0, ""}, }, "compress/flate": { - {"(*ReadError).Error", Method, 0}, - {"(*WriteError).Error", Method, 0}, - {"(*Writer).Close", Method, 0}, - {"(*Writer).Flush", Method, 0}, - {"(*Writer).Reset", Method, 2}, - {"(*Writer).Write", Method, 0}, - {"(CorruptInputError).Error", Method, 0}, - {"(InternalError).Error", Method, 0}, - {"BestCompression", Const, 0}, - {"BestSpeed", Const, 0}, - {"CorruptInputError", Type, 0}, - {"DefaultCompression", Const, 0}, - {"HuffmanOnly", Const, 7}, - {"InternalError", Type, 0}, - {"NewReader", Func, 0}, - {"NewReaderDict", Func, 0}, - {"NewWriter", Func, 0}, - {"NewWriterDict", Func, 0}, - {"NoCompression", Const, 0}, - {"ReadError", Type, 0}, - {"ReadError.Err", Field, 0}, - {"ReadError.Offset", Field, 0}, - {"Reader", Type, 0}, - {"Resetter", Type, 4}, - {"WriteError", Type, 0}, - {"WriteError.Err", Field, 0}, - {"WriteError.Offset", Field, 0}, - {"Writer", Type, 0}, + {"(*ReadError).Error", Method, 0, ""}, + {"(*WriteError).Error", Method, 0, ""}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).Flush", Method, 0, ""}, + {"(*Writer).Reset", Method, 2, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"(CorruptInputError).Error", Method, 0, ""}, + {"(InternalError).Error", Method, 0, ""}, + {"BestCompression", Const, 0, ""}, + {"BestSpeed", Const, 0, ""}, + {"CorruptInputError", Type, 0, ""}, + {"DefaultCompression", Const, 0, ""}, + {"HuffmanOnly", Const, 7, ""}, + {"InternalError", Type, 0, ""}, + {"NewReader", Func, 0, "func(r io.Reader) io.ReadCloser"}, + {"NewReaderDict", Func, 0, "func(r io.Reader, dict []byte) io.ReadCloser"}, + {"NewWriter", Func, 0, "func(w io.Writer, level int) (*Writer, error)"}, + {"NewWriterDict", Func, 0, "func(w io.Writer, level int, dict []byte) (*Writer, error)"}, + {"NoCompression", Const, 0, ""}, + {"ReadError", Type, 0, ""}, + {"ReadError.Err", Field, 0, ""}, + {"ReadError.Offset", Field, 0, ""}, + {"Reader", Type, 0, ""}, + {"Resetter", Type, 4, ""}, + {"WriteError", Type, 0, ""}, + {"WriteError.Err", Field, 0, ""}, + {"WriteError.Offset", Field, 0, ""}, + {"Writer", Type, 0, ""}, }, "compress/gzip": { - {"(*Reader).Close", Method, 0}, - {"(*Reader).Multistream", Method, 4}, - {"(*Reader).Read", Method, 0}, - {"(*Reader).Reset", Method, 3}, - {"(*Writer).Close", Method, 0}, - {"(*Writer).Flush", Method, 1}, - {"(*Writer).Reset", Method, 2}, - {"(*Writer).Write", Method, 0}, - {"BestCompression", Const, 0}, - {"BestSpeed", Const, 0}, - {"DefaultCompression", Const, 0}, - {"ErrChecksum", Var, 0}, - {"ErrHeader", Var, 0}, - {"Header", Type, 0}, - {"Header.Comment", Field, 0}, - {"Header.Extra", Field, 0}, - {"Header.ModTime", Field, 0}, - {"Header.Name", Field, 0}, - {"Header.OS", Field, 0}, - {"HuffmanOnly", Const, 8}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"NewWriterLevel", Func, 0}, - {"NoCompression", Const, 0}, - {"Reader", Type, 0}, - {"Reader.Header", Field, 0}, - {"Writer", Type, 0}, - {"Writer.Header", Field, 0}, + {"(*Reader).Close", Method, 0, ""}, + {"(*Reader).Multistream", Method, 4, ""}, + {"(*Reader).Read", Method, 0, ""}, + {"(*Reader).Reset", Method, 3, ""}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).Flush", Method, 1, ""}, + {"(*Writer).Reset", Method, 2, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"BestCompression", Const, 0, ""}, + {"BestSpeed", Const, 0, ""}, + {"DefaultCompression", Const, 0, ""}, + {"ErrChecksum", Var, 0, ""}, + {"ErrHeader", Var, 0, ""}, + {"Header", Type, 0, ""}, + {"Header.Comment", Field, 0, ""}, + {"Header.Extra", Field, 0, ""}, + {"Header.ModTime", Field, 0, ""}, + {"Header.Name", Field, 0, ""}, + {"Header.OS", Field, 0, ""}, + {"HuffmanOnly", Const, 8, ""}, + {"NewReader", Func, 0, "func(r io.Reader) (*Reader, error)"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"NewWriterLevel", Func, 0, "func(w io.Writer, level int) (*Writer, error)"}, + {"NoCompression", Const, 0, ""}, + {"Reader", Type, 0, ""}, + {"Reader.Header", Field, 0, ""}, + {"Writer", Type, 0, ""}, + {"Writer.Header", Field, 0, ""}, }, "compress/lzw": { - {"(*Reader).Close", Method, 17}, - {"(*Reader).Read", Method, 17}, - {"(*Reader).Reset", Method, 17}, - {"(*Writer).Close", Method, 17}, - {"(*Writer).Reset", Method, 17}, - {"(*Writer).Write", Method, 17}, - {"LSB", Const, 0}, - {"MSB", Const, 0}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"Order", Type, 0}, - {"Reader", Type, 17}, - {"Writer", Type, 17}, + {"(*Reader).Close", Method, 17, ""}, + {"(*Reader).Read", Method, 17, ""}, + {"(*Reader).Reset", Method, 17, ""}, + {"(*Writer).Close", Method, 17, ""}, + {"(*Writer).Reset", Method, 17, ""}, + {"(*Writer).Write", Method, 17, ""}, + {"LSB", Const, 0, ""}, + {"MSB", Const, 0, ""}, + {"NewReader", Func, 0, "func(r io.Reader, order Order, litWidth int) io.ReadCloser"}, + {"NewWriter", Func, 0, "func(w io.Writer, order Order, litWidth int) io.WriteCloser"}, + {"Order", Type, 0, ""}, + {"Reader", Type, 17, ""}, + {"Writer", Type, 17, ""}, }, "compress/zlib": { - {"(*Writer).Close", Method, 0}, - {"(*Writer).Flush", Method, 0}, - {"(*Writer).Reset", Method, 2}, - {"(*Writer).Write", Method, 0}, - {"BestCompression", Const, 0}, - {"BestSpeed", Const, 0}, - {"DefaultCompression", Const, 0}, - {"ErrChecksum", Var, 0}, - {"ErrDictionary", Var, 0}, - {"ErrHeader", Var, 0}, - {"HuffmanOnly", Const, 8}, - {"NewReader", Func, 0}, - {"NewReaderDict", Func, 0}, - {"NewWriter", Func, 0}, - {"NewWriterLevel", Func, 0}, - {"NewWriterLevelDict", Func, 0}, - {"NoCompression", Const, 0}, - {"Resetter", Type, 4}, - {"Writer", Type, 0}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).Flush", Method, 0, ""}, + {"(*Writer).Reset", Method, 2, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"BestCompression", Const, 0, ""}, + {"BestSpeed", Const, 0, ""}, + {"DefaultCompression", Const, 0, ""}, + {"ErrChecksum", Var, 0, ""}, + {"ErrDictionary", Var, 0, ""}, + {"ErrHeader", Var, 0, ""}, + {"HuffmanOnly", Const, 8, ""}, + {"NewReader", Func, 0, "func(r io.Reader) (io.ReadCloser, error)"}, + {"NewReaderDict", Func, 0, "func(r io.Reader, dict []byte) (io.ReadCloser, error)"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"NewWriterLevel", Func, 0, "func(w io.Writer, level int) (*Writer, error)"}, + {"NewWriterLevelDict", Func, 0, "func(w io.Writer, level int, dict []byte) (*Writer, error)"}, + {"NoCompression", Const, 0, ""}, + {"Resetter", Type, 4, ""}, + {"Writer", Type, 0, ""}, }, "container/heap": { - {"Fix", Func, 2}, - {"Init", Func, 0}, - {"Interface", Type, 0}, - {"Pop", Func, 0}, - {"Push", Func, 0}, - {"Remove", Func, 0}, + {"Fix", Func, 2, "func(h Interface, i int)"}, + {"Init", Func, 0, "func(h Interface)"}, + {"Interface", Type, 0, ""}, + {"Pop", Func, 0, "func(h Interface) any"}, + {"Push", Func, 0, "func(h Interface, x any)"}, + {"Remove", Func, 0, "func(h Interface, i int) any"}, }, "container/list": { - {"(*Element).Next", Method, 0}, - {"(*Element).Prev", Method, 0}, - {"(*List).Back", Method, 0}, - {"(*List).Front", Method, 0}, - {"(*List).Init", Method, 0}, - {"(*List).InsertAfter", Method, 0}, - {"(*List).InsertBefore", Method, 0}, - {"(*List).Len", Method, 0}, - {"(*List).MoveAfter", Method, 2}, - {"(*List).MoveBefore", Method, 2}, - {"(*List).MoveToBack", Method, 0}, - {"(*List).MoveToFront", Method, 0}, - {"(*List).PushBack", Method, 0}, - {"(*List).PushBackList", Method, 0}, - {"(*List).PushFront", Method, 0}, - {"(*List).PushFrontList", Method, 0}, - {"(*List).Remove", Method, 0}, - {"Element", Type, 0}, - {"Element.Value", Field, 0}, - {"List", Type, 0}, - {"New", Func, 0}, + {"(*Element).Next", Method, 0, ""}, + {"(*Element).Prev", Method, 0, ""}, + {"(*List).Back", Method, 0, ""}, + {"(*List).Front", Method, 0, ""}, + {"(*List).Init", Method, 0, ""}, + {"(*List).InsertAfter", Method, 0, ""}, + {"(*List).InsertBefore", Method, 0, ""}, + {"(*List).Len", Method, 0, ""}, + {"(*List).MoveAfter", Method, 2, ""}, + {"(*List).MoveBefore", Method, 2, ""}, + {"(*List).MoveToBack", Method, 0, ""}, + {"(*List).MoveToFront", Method, 0, ""}, + {"(*List).PushBack", Method, 0, ""}, + {"(*List).PushBackList", Method, 0, ""}, + {"(*List).PushFront", Method, 0, ""}, + {"(*List).PushFrontList", Method, 0, ""}, + {"(*List).Remove", Method, 0, ""}, + {"Element", Type, 0, ""}, + {"Element.Value", Field, 0, ""}, + {"List", Type, 0, ""}, + {"New", Func, 0, "func() *List"}, }, "container/ring": { - {"(*Ring).Do", Method, 0}, - {"(*Ring).Len", Method, 0}, - {"(*Ring).Link", Method, 0}, - {"(*Ring).Move", Method, 0}, - {"(*Ring).Next", Method, 0}, - {"(*Ring).Prev", Method, 0}, - {"(*Ring).Unlink", Method, 0}, - {"New", Func, 0}, - {"Ring", Type, 0}, - {"Ring.Value", Field, 0}, + {"(*Ring).Do", Method, 0, ""}, + {"(*Ring).Len", Method, 0, ""}, + {"(*Ring).Link", Method, 0, ""}, + {"(*Ring).Move", Method, 0, ""}, + {"(*Ring).Next", Method, 0, ""}, + {"(*Ring).Prev", Method, 0, ""}, + {"(*Ring).Unlink", Method, 0, ""}, + {"New", Func, 0, "func(n int) *Ring"}, + {"Ring", Type, 0, ""}, + {"Ring.Value", Field, 0, ""}, }, "context": { - {"AfterFunc", Func, 21}, - {"Background", Func, 7}, - {"CancelCauseFunc", Type, 20}, - {"CancelFunc", Type, 7}, - {"Canceled", Var, 7}, - {"Cause", Func, 20}, - {"Context", Type, 7}, - {"DeadlineExceeded", Var, 7}, - {"TODO", Func, 7}, - {"WithCancel", Func, 7}, - {"WithCancelCause", Func, 20}, - {"WithDeadline", Func, 7}, - {"WithDeadlineCause", Func, 21}, - {"WithTimeout", Func, 7}, - {"WithTimeoutCause", Func, 21}, - {"WithValue", Func, 7}, - {"WithoutCancel", Func, 21}, + {"AfterFunc", Func, 21, "func(ctx Context, f func()) (stop func() bool)"}, + {"Background", Func, 7, "func() Context"}, + {"CancelCauseFunc", Type, 20, ""}, + {"CancelFunc", Type, 7, ""}, + {"Canceled", Var, 7, ""}, + {"Cause", Func, 20, "func(c Context) error"}, + {"Context", Type, 7, ""}, + {"DeadlineExceeded", Var, 7, ""}, + {"TODO", Func, 7, "func() Context"}, + {"WithCancel", Func, 7, "func(parent Context) (ctx Context, cancel CancelFunc)"}, + {"WithCancelCause", Func, 20, "func(parent Context) (ctx Context, cancel CancelCauseFunc)"}, + {"WithDeadline", Func, 7, "func(parent Context, d time.Time) (Context, CancelFunc)"}, + {"WithDeadlineCause", Func, 21, "func(parent Context, d time.Time, cause error) (Context, CancelFunc)"}, + {"WithTimeout", Func, 7, "func(parent Context, timeout time.Duration) (Context, CancelFunc)"}, + {"WithTimeoutCause", Func, 21, "func(parent Context, timeout time.Duration, cause error) (Context, CancelFunc)"}, + {"WithValue", Func, 7, "func(parent Context, key any, val any) Context"}, + {"WithoutCancel", Func, 21, "func(parent Context) Context"}, }, "crypto": { - {"(Hash).Available", Method, 0}, - {"(Hash).HashFunc", Method, 4}, - {"(Hash).New", Method, 0}, - {"(Hash).Size", Method, 0}, - {"(Hash).String", Method, 15}, - {"BLAKE2b_256", Const, 9}, - {"BLAKE2b_384", Const, 9}, - {"BLAKE2b_512", Const, 9}, - {"BLAKE2s_256", Const, 9}, - {"Decrypter", Type, 5}, - {"DecrypterOpts", Type, 5}, - {"Hash", Type, 0}, - {"MD4", Const, 0}, - {"MD5", Const, 0}, - {"MD5SHA1", Const, 0}, - {"PrivateKey", Type, 0}, - {"PublicKey", Type, 2}, - {"RIPEMD160", Const, 0}, - {"RegisterHash", Func, 0}, - {"SHA1", Const, 0}, - {"SHA224", Const, 0}, - {"SHA256", Const, 0}, - {"SHA384", Const, 0}, - {"SHA3_224", Const, 4}, - {"SHA3_256", Const, 4}, - {"SHA3_384", Const, 4}, - {"SHA3_512", Const, 4}, - {"SHA512", Const, 0}, - {"SHA512_224", Const, 5}, - {"SHA512_256", Const, 5}, - {"Signer", Type, 4}, - {"SignerOpts", Type, 4}, + {"(Hash).Available", Method, 0, ""}, + {"(Hash).HashFunc", Method, 4, ""}, + {"(Hash).New", Method, 0, ""}, + {"(Hash).Size", Method, 0, ""}, + {"(Hash).String", Method, 15, ""}, + {"BLAKE2b_256", Const, 9, ""}, + {"BLAKE2b_384", Const, 9, ""}, + {"BLAKE2b_512", Const, 9, ""}, + {"BLAKE2s_256", Const, 9, ""}, + {"Decrypter", Type, 5, ""}, + {"DecrypterOpts", Type, 5, ""}, + {"Hash", Type, 0, ""}, + {"MD4", Const, 0, ""}, + {"MD5", Const, 0, ""}, + {"MD5SHA1", Const, 0, ""}, + {"PrivateKey", Type, 0, ""}, + {"PublicKey", Type, 2, ""}, + {"RIPEMD160", Const, 0, ""}, + {"RegisterHash", Func, 0, "func(h Hash, f func() hash.Hash)"}, + {"SHA1", Const, 0, ""}, + {"SHA224", Const, 0, ""}, + {"SHA256", Const, 0, ""}, + {"SHA384", Const, 0, ""}, + {"SHA3_224", Const, 4, ""}, + {"SHA3_256", Const, 4, ""}, + {"SHA3_384", Const, 4, ""}, + {"SHA3_512", Const, 4, ""}, + {"SHA512", Const, 0, ""}, + {"SHA512_224", Const, 5, ""}, + {"SHA512_256", Const, 5, ""}, + {"Signer", Type, 4, ""}, + {"SignerOpts", Type, 4, ""}, }, "crypto/aes": { - {"(KeySizeError).Error", Method, 0}, - {"BlockSize", Const, 0}, - {"KeySizeError", Type, 0}, - {"NewCipher", Func, 0}, + {"(KeySizeError).Error", Method, 0, ""}, + {"BlockSize", Const, 0, ""}, + {"KeySizeError", Type, 0, ""}, + {"NewCipher", Func, 0, "func(key []byte) (cipher.Block, error)"}, }, "crypto/cipher": { - {"(StreamReader).Read", Method, 0}, - {"(StreamWriter).Close", Method, 0}, - {"(StreamWriter).Write", Method, 0}, - {"AEAD", Type, 2}, - {"Block", Type, 0}, - {"BlockMode", Type, 0}, - {"NewCBCDecrypter", Func, 0}, - {"NewCBCEncrypter", Func, 0}, - {"NewCFBDecrypter", Func, 0}, - {"NewCFBEncrypter", Func, 0}, - {"NewCTR", Func, 0}, - {"NewGCM", Func, 2}, - {"NewGCMWithNonceSize", Func, 5}, - {"NewGCMWithRandomNonce", Func, 24}, - {"NewGCMWithTagSize", Func, 11}, - {"NewOFB", Func, 0}, - {"Stream", Type, 0}, - {"StreamReader", Type, 0}, - {"StreamReader.R", Field, 0}, - {"StreamReader.S", Field, 0}, - {"StreamWriter", Type, 0}, - {"StreamWriter.Err", Field, 0}, - {"StreamWriter.S", Field, 0}, - {"StreamWriter.W", Field, 0}, + {"(StreamReader).Read", Method, 0, ""}, + {"(StreamWriter).Close", Method, 0, ""}, + {"(StreamWriter).Write", Method, 0, ""}, + {"AEAD", Type, 2, ""}, + {"Block", Type, 0, ""}, + {"BlockMode", Type, 0, ""}, + {"NewCBCDecrypter", Func, 0, "func(b Block, iv []byte) BlockMode"}, + {"NewCBCEncrypter", Func, 0, "func(b Block, iv []byte) BlockMode"}, + {"NewCFBDecrypter", Func, 0, "func(block Block, iv []byte) Stream"}, + {"NewCFBEncrypter", Func, 0, "func(block Block, iv []byte) Stream"}, + {"NewCTR", Func, 0, "func(block Block, iv []byte) Stream"}, + {"NewGCM", Func, 2, "func(cipher Block) (AEAD, error)"}, + {"NewGCMWithNonceSize", Func, 5, "func(cipher Block, size int) (AEAD, error)"}, + {"NewGCMWithRandomNonce", Func, 24, "func(cipher Block) (AEAD, error)"}, + {"NewGCMWithTagSize", Func, 11, "func(cipher Block, tagSize int) (AEAD, error)"}, + {"NewOFB", Func, 0, "func(b Block, iv []byte) Stream"}, + {"Stream", Type, 0, ""}, + {"StreamReader", Type, 0, ""}, + {"StreamReader.R", Field, 0, ""}, + {"StreamReader.S", Field, 0, ""}, + {"StreamWriter", Type, 0, ""}, + {"StreamWriter.Err", Field, 0, ""}, + {"StreamWriter.S", Field, 0, ""}, + {"StreamWriter.W", Field, 0, ""}, }, "crypto/des": { - {"(KeySizeError).Error", Method, 0}, - {"BlockSize", Const, 0}, - {"KeySizeError", Type, 0}, - {"NewCipher", Func, 0}, - {"NewTripleDESCipher", Func, 0}, + {"(KeySizeError).Error", Method, 0, ""}, + {"BlockSize", Const, 0, ""}, + {"KeySizeError", Type, 0, ""}, + {"NewCipher", Func, 0, "func(key []byte) (cipher.Block, error)"}, + {"NewTripleDESCipher", Func, 0, "func(key []byte) (cipher.Block, error)"}, }, "crypto/dsa": { - {"ErrInvalidPublicKey", Var, 0}, - {"GenerateKey", Func, 0}, - {"GenerateParameters", Func, 0}, - {"L1024N160", Const, 0}, - {"L2048N224", Const, 0}, - {"L2048N256", Const, 0}, - {"L3072N256", Const, 0}, - {"ParameterSizes", Type, 0}, - {"Parameters", Type, 0}, - {"Parameters.G", Field, 0}, - {"Parameters.P", Field, 0}, - {"Parameters.Q", Field, 0}, - {"PrivateKey", Type, 0}, - {"PrivateKey.PublicKey", Field, 0}, - {"PrivateKey.X", Field, 0}, - {"PublicKey", Type, 0}, - {"PublicKey.Parameters", Field, 0}, - {"PublicKey.Y", Field, 0}, - {"Sign", Func, 0}, - {"Verify", Func, 0}, + {"ErrInvalidPublicKey", Var, 0, ""}, + {"GenerateKey", Func, 0, "func(priv *PrivateKey, rand io.Reader) error"}, + {"GenerateParameters", Func, 0, "func(params *Parameters, rand io.Reader, sizes ParameterSizes) error"}, + {"L1024N160", Const, 0, ""}, + {"L2048N224", Const, 0, ""}, + {"L2048N256", Const, 0, ""}, + {"L3072N256", Const, 0, ""}, + {"ParameterSizes", Type, 0, ""}, + {"Parameters", Type, 0, ""}, + {"Parameters.G", Field, 0, ""}, + {"Parameters.P", Field, 0, ""}, + {"Parameters.Q", Field, 0, ""}, + {"PrivateKey", Type, 0, ""}, + {"PrivateKey.PublicKey", Field, 0, ""}, + {"PrivateKey.X", Field, 0, ""}, + {"PublicKey", Type, 0, ""}, + {"PublicKey.Parameters", Field, 0, ""}, + {"PublicKey.Y", Field, 0, ""}, + {"Sign", Func, 0, "func(rand io.Reader, priv *PrivateKey, hash []byte) (r *big.Int, s *big.Int, err error)"}, + {"Verify", Func, 0, "func(pub *PublicKey, hash []byte, r *big.Int, s *big.Int) bool"}, }, "crypto/ecdh": { - {"(*PrivateKey).Bytes", Method, 20}, - {"(*PrivateKey).Curve", Method, 20}, - {"(*PrivateKey).ECDH", Method, 20}, - {"(*PrivateKey).Equal", Method, 20}, - {"(*PrivateKey).Public", Method, 20}, - {"(*PrivateKey).PublicKey", Method, 20}, - {"(*PublicKey).Bytes", Method, 20}, - {"(*PublicKey).Curve", Method, 20}, - {"(*PublicKey).Equal", Method, 20}, - {"Curve", Type, 20}, - {"P256", Func, 20}, - {"P384", Func, 20}, - {"P521", Func, 20}, - {"PrivateKey", Type, 20}, - {"PublicKey", Type, 20}, - {"X25519", Func, 20}, + {"(*PrivateKey).Bytes", Method, 20, ""}, + {"(*PrivateKey).Curve", Method, 20, ""}, + {"(*PrivateKey).ECDH", Method, 20, ""}, + {"(*PrivateKey).Equal", Method, 20, ""}, + {"(*PrivateKey).Public", Method, 20, ""}, + {"(*PrivateKey).PublicKey", Method, 20, ""}, + {"(*PublicKey).Bytes", Method, 20, ""}, + {"(*PublicKey).Curve", Method, 20, ""}, + {"(*PublicKey).Equal", Method, 20, ""}, + {"Curve", Type, 20, ""}, + {"P256", Func, 20, "func() Curve"}, + {"P384", Func, 20, "func() Curve"}, + {"P521", Func, 20, "func() Curve"}, + {"PrivateKey", Type, 20, ""}, + {"PublicKey", Type, 20, ""}, + {"X25519", Func, 20, "func() Curve"}, }, "crypto/ecdsa": { - {"(*PrivateKey).ECDH", Method, 20}, - {"(*PrivateKey).Equal", Method, 15}, - {"(*PrivateKey).Public", Method, 4}, - {"(*PrivateKey).Sign", Method, 4}, - {"(*PublicKey).ECDH", Method, 20}, - {"(*PublicKey).Equal", Method, 15}, - {"(PrivateKey).Add", Method, 0}, - {"(PrivateKey).Double", Method, 0}, - {"(PrivateKey).IsOnCurve", Method, 0}, - {"(PrivateKey).Params", Method, 0}, - {"(PrivateKey).ScalarBaseMult", Method, 0}, - {"(PrivateKey).ScalarMult", Method, 0}, - {"(PublicKey).Add", Method, 0}, - {"(PublicKey).Double", Method, 0}, - {"(PublicKey).IsOnCurve", Method, 0}, - {"(PublicKey).Params", Method, 0}, - {"(PublicKey).ScalarBaseMult", Method, 0}, - {"(PublicKey).ScalarMult", Method, 0}, - {"GenerateKey", Func, 0}, - {"PrivateKey", Type, 0}, - {"PrivateKey.D", Field, 0}, - {"PrivateKey.PublicKey", Field, 0}, - {"PublicKey", Type, 0}, - {"PublicKey.Curve", Field, 0}, - {"PublicKey.X", Field, 0}, - {"PublicKey.Y", Field, 0}, - {"Sign", Func, 0}, - {"SignASN1", Func, 15}, - {"Verify", Func, 0}, - {"VerifyASN1", Func, 15}, + {"(*PrivateKey).ECDH", Method, 20, ""}, + {"(*PrivateKey).Equal", Method, 15, ""}, + {"(*PrivateKey).Public", Method, 4, ""}, + {"(*PrivateKey).Sign", Method, 4, ""}, + {"(*PublicKey).ECDH", Method, 20, ""}, + {"(*PublicKey).Equal", Method, 15, ""}, + {"(PrivateKey).Add", Method, 0, ""}, + {"(PrivateKey).Double", Method, 0, ""}, + {"(PrivateKey).IsOnCurve", Method, 0, ""}, + {"(PrivateKey).Params", Method, 0, ""}, + {"(PrivateKey).ScalarBaseMult", Method, 0, ""}, + {"(PrivateKey).ScalarMult", Method, 0, ""}, + {"(PublicKey).Add", Method, 0, ""}, + {"(PublicKey).Double", Method, 0, ""}, + {"(PublicKey).IsOnCurve", Method, 0, ""}, + {"(PublicKey).Params", Method, 0, ""}, + {"(PublicKey).ScalarBaseMult", Method, 0, ""}, + {"(PublicKey).ScalarMult", Method, 0, ""}, + {"GenerateKey", Func, 0, "func(c elliptic.Curve, rand io.Reader) (*PrivateKey, error)"}, + {"PrivateKey", Type, 0, ""}, + {"PrivateKey.D", Field, 0, ""}, + {"PrivateKey.PublicKey", Field, 0, ""}, + {"PublicKey", Type, 0, ""}, + {"PublicKey.Curve", Field, 0, ""}, + {"PublicKey.X", Field, 0, ""}, + {"PublicKey.Y", Field, 0, ""}, + {"Sign", Func, 0, "func(rand io.Reader, priv *PrivateKey, hash []byte) (r *big.Int, s *big.Int, err error)"}, + {"SignASN1", Func, 15, "func(rand io.Reader, priv *PrivateKey, hash []byte) ([]byte, error)"}, + {"Verify", Func, 0, "func(pub *PublicKey, hash []byte, r *big.Int, s *big.Int) bool"}, + {"VerifyASN1", Func, 15, "func(pub *PublicKey, hash []byte, sig []byte) bool"}, }, "crypto/ed25519": { - {"(*Options).HashFunc", Method, 20}, - {"(PrivateKey).Equal", Method, 15}, - {"(PrivateKey).Public", Method, 13}, - {"(PrivateKey).Seed", Method, 13}, - {"(PrivateKey).Sign", Method, 13}, - {"(PublicKey).Equal", Method, 15}, - {"GenerateKey", Func, 13}, - {"NewKeyFromSeed", Func, 13}, - {"Options", Type, 20}, - {"Options.Context", Field, 20}, - {"Options.Hash", Field, 20}, - {"PrivateKey", Type, 13}, - {"PrivateKeySize", Const, 13}, - {"PublicKey", Type, 13}, - {"PublicKeySize", Const, 13}, - {"SeedSize", Const, 13}, - {"Sign", Func, 13}, - {"SignatureSize", Const, 13}, - {"Verify", Func, 13}, - {"VerifyWithOptions", Func, 20}, + {"(*Options).HashFunc", Method, 20, ""}, + {"(PrivateKey).Equal", Method, 15, ""}, + {"(PrivateKey).Public", Method, 13, ""}, + {"(PrivateKey).Seed", Method, 13, ""}, + {"(PrivateKey).Sign", Method, 13, ""}, + {"(PublicKey).Equal", Method, 15, ""}, + {"GenerateKey", Func, 13, "func(rand io.Reader) (PublicKey, PrivateKey, error)"}, + {"NewKeyFromSeed", Func, 13, "func(seed []byte) PrivateKey"}, + {"Options", Type, 20, ""}, + {"Options.Context", Field, 20, ""}, + {"Options.Hash", Field, 20, ""}, + {"PrivateKey", Type, 13, ""}, + {"PrivateKeySize", Const, 13, ""}, + {"PublicKey", Type, 13, ""}, + {"PublicKeySize", Const, 13, ""}, + {"SeedSize", Const, 13, ""}, + {"Sign", Func, 13, "func(privateKey PrivateKey, message []byte) []byte"}, + {"SignatureSize", Const, 13, ""}, + {"Verify", Func, 13, "func(publicKey PublicKey, message []byte, sig []byte) bool"}, + {"VerifyWithOptions", Func, 20, "func(publicKey PublicKey, message []byte, sig []byte, opts *Options) error"}, }, "crypto/elliptic": { - {"(*CurveParams).Add", Method, 0}, - {"(*CurveParams).Double", Method, 0}, - {"(*CurveParams).IsOnCurve", Method, 0}, - {"(*CurveParams).Params", Method, 0}, - {"(*CurveParams).ScalarBaseMult", Method, 0}, - {"(*CurveParams).ScalarMult", Method, 0}, - {"Curve", Type, 0}, - {"CurveParams", Type, 0}, - {"CurveParams.B", Field, 0}, - {"CurveParams.BitSize", Field, 0}, - {"CurveParams.Gx", Field, 0}, - {"CurveParams.Gy", Field, 0}, - {"CurveParams.N", Field, 0}, - {"CurveParams.Name", Field, 5}, - {"CurveParams.P", Field, 0}, - {"GenerateKey", Func, 0}, - {"Marshal", Func, 0}, - {"MarshalCompressed", Func, 15}, - {"P224", Func, 0}, - {"P256", Func, 0}, - {"P384", Func, 0}, - {"P521", Func, 0}, - {"Unmarshal", Func, 0}, - {"UnmarshalCompressed", Func, 15}, + {"(*CurveParams).Add", Method, 0, ""}, + {"(*CurveParams).Double", Method, 0, ""}, + {"(*CurveParams).IsOnCurve", Method, 0, ""}, + {"(*CurveParams).Params", Method, 0, ""}, + {"(*CurveParams).ScalarBaseMult", Method, 0, ""}, + {"(*CurveParams).ScalarMult", Method, 0, ""}, + {"Curve", Type, 0, ""}, + {"CurveParams", Type, 0, ""}, + {"CurveParams.B", Field, 0, ""}, + {"CurveParams.BitSize", Field, 0, ""}, + {"CurveParams.Gx", Field, 0, ""}, + {"CurveParams.Gy", Field, 0, ""}, + {"CurveParams.N", Field, 0, ""}, + {"CurveParams.Name", Field, 5, ""}, + {"CurveParams.P", Field, 0, ""}, + {"GenerateKey", Func, 0, "func(curve Curve, rand io.Reader) (priv []byte, x *big.Int, y *big.Int, err error)"}, + {"Marshal", Func, 0, "func(curve Curve, x *big.Int, y *big.Int) []byte"}, + {"MarshalCompressed", Func, 15, "func(curve Curve, x *big.Int, y *big.Int) []byte"}, + {"P224", Func, 0, "func() Curve"}, + {"P256", Func, 0, "func() Curve"}, + {"P384", Func, 0, "func() Curve"}, + {"P521", Func, 0, "func() Curve"}, + {"Unmarshal", Func, 0, "func(curve Curve, data []byte) (x *big.Int, y *big.Int)"}, + {"UnmarshalCompressed", Func, 15, "func(curve Curve, data []byte) (x *big.Int, y *big.Int)"}, }, "crypto/fips140": { - {"Enabled", Func, 24}, + {"Enabled", Func, 24, "func() bool"}, }, "crypto/hkdf": { - {"Expand", Func, 24}, - {"Extract", Func, 24}, - {"Key", Func, 24}, + {"Expand", Func, 24, "func[H hash.Hash](h func() H, pseudorandomKey []byte, info string, keyLength int) ([]byte, error)"}, + {"Extract", Func, 24, "func[H hash.Hash](h func() H, secret []byte, salt []byte) ([]byte, error)"}, + {"Key", Func, 24, "func[Hash hash.Hash](h func() Hash, secret []byte, salt []byte, info string, keyLength int) ([]byte, error)"}, }, "crypto/hmac": { - {"Equal", Func, 1}, - {"New", Func, 0}, + {"Equal", Func, 1, "func(mac1 []byte, mac2 []byte) bool"}, + {"New", Func, 0, "func(h func() hash.Hash, key []byte) hash.Hash"}, }, "crypto/md5": { - {"BlockSize", Const, 0}, - {"New", Func, 0}, - {"Size", Const, 0}, - {"Sum", Func, 2}, + {"BlockSize", Const, 0, ""}, + {"New", Func, 0, "func() hash.Hash"}, + {"Size", Const, 0, ""}, + {"Sum", Func, 2, "func(data []byte) [16]byte"}, }, "crypto/mlkem": { - {"(*DecapsulationKey1024).Bytes", Method, 24}, - {"(*DecapsulationKey1024).Decapsulate", Method, 24}, - {"(*DecapsulationKey1024).EncapsulationKey", Method, 24}, - {"(*DecapsulationKey768).Bytes", Method, 24}, - {"(*DecapsulationKey768).Decapsulate", Method, 24}, - {"(*DecapsulationKey768).EncapsulationKey", Method, 24}, - {"(*EncapsulationKey1024).Bytes", Method, 24}, - {"(*EncapsulationKey1024).Encapsulate", Method, 24}, - {"(*EncapsulationKey768).Bytes", Method, 24}, - {"(*EncapsulationKey768).Encapsulate", Method, 24}, - {"CiphertextSize1024", Const, 24}, - {"CiphertextSize768", Const, 24}, - {"DecapsulationKey1024", Type, 24}, - {"DecapsulationKey768", Type, 24}, - {"EncapsulationKey1024", Type, 24}, - {"EncapsulationKey768", Type, 24}, - {"EncapsulationKeySize1024", Const, 24}, - {"EncapsulationKeySize768", Const, 24}, - {"GenerateKey1024", Func, 24}, - {"GenerateKey768", Func, 24}, - {"NewDecapsulationKey1024", Func, 24}, - {"NewDecapsulationKey768", Func, 24}, - {"NewEncapsulationKey1024", Func, 24}, - {"NewEncapsulationKey768", Func, 24}, - {"SeedSize", Const, 24}, - {"SharedKeySize", Const, 24}, + {"(*DecapsulationKey1024).Bytes", Method, 24, ""}, + {"(*DecapsulationKey1024).Decapsulate", Method, 24, ""}, + {"(*DecapsulationKey1024).EncapsulationKey", Method, 24, ""}, + {"(*DecapsulationKey768).Bytes", Method, 24, ""}, + {"(*DecapsulationKey768).Decapsulate", Method, 24, ""}, + {"(*DecapsulationKey768).EncapsulationKey", Method, 24, ""}, + {"(*EncapsulationKey1024).Bytes", Method, 24, ""}, + {"(*EncapsulationKey1024).Encapsulate", Method, 24, ""}, + {"(*EncapsulationKey768).Bytes", Method, 24, ""}, + {"(*EncapsulationKey768).Encapsulate", Method, 24, ""}, + {"CiphertextSize1024", Const, 24, ""}, + {"CiphertextSize768", Const, 24, ""}, + {"DecapsulationKey1024", Type, 24, ""}, + {"DecapsulationKey768", Type, 24, ""}, + {"EncapsulationKey1024", Type, 24, ""}, + {"EncapsulationKey768", Type, 24, ""}, + {"EncapsulationKeySize1024", Const, 24, ""}, + {"EncapsulationKeySize768", Const, 24, ""}, + {"GenerateKey1024", Func, 24, "func() (*DecapsulationKey1024, error)"}, + {"GenerateKey768", Func, 24, "func() (*DecapsulationKey768, error)"}, + {"NewDecapsulationKey1024", Func, 24, "func(seed []byte) (*DecapsulationKey1024, error)"}, + {"NewDecapsulationKey768", Func, 24, "func(seed []byte) (*DecapsulationKey768, error)"}, + {"NewEncapsulationKey1024", Func, 24, "func(encapsulationKey []byte) (*EncapsulationKey1024, error)"}, + {"NewEncapsulationKey768", Func, 24, "func(encapsulationKey []byte) (*EncapsulationKey768, error)"}, + {"SeedSize", Const, 24, ""}, + {"SharedKeySize", Const, 24, ""}, }, "crypto/pbkdf2": { - {"Key", Func, 24}, + {"Key", Func, 24, "func[Hash hash.Hash](h func() Hash, password string, salt []byte, iter int, keyLength int) ([]byte, error)"}, }, "crypto/rand": { - {"Int", Func, 0}, - {"Prime", Func, 0}, - {"Read", Func, 0}, - {"Reader", Var, 0}, - {"Text", Func, 24}, + {"Int", Func, 0, "func(rand io.Reader, max *big.Int) (n *big.Int, err error)"}, + {"Prime", Func, 0, "func(rand io.Reader, bits int) (*big.Int, error)"}, + {"Read", Func, 0, "func(b []byte) (n int, err error)"}, + {"Reader", Var, 0, ""}, + {"Text", Func, 24, "func() string"}, }, "crypto/rc4": { - {"(*Cipher).Reset", Method, 0}, - {"(*Cipher).XORKeyStream", Method, 0}, - {"(KeySizeError).Error", Method, 0}, - {"Cipher", Type, 0}, - {"KeySizeError", Type, 0}, - {"NewCipher", Func, 0}, + {"(*Cipher).Reset", Method, 0, ""}, + {"(*Cipher).XORKeyStream", Method, 0, ""}, + {"(KeySizeError).Error", Method, 0, ""}, + {"Cipher", Type, 0, ""}, + {"KeySizeError", Type, 0, ""}, + {"NewCipher", Func, 0, "func(key []byte) (*Cipher, error)"}, }, "crypto/rsa": { - {"(*PSSOptions).HashFunc", Method, 4}, - {"(*PrivateKey).Decrypt", Method, 5}, - {"(*PrivateKey).Equal", Method, 15}, - {"(*PrivateKey).Precompute", Method, 0}, - {"(*PrivateKey).Public", Method, 4}, - {"(*PrivateKey).Sign", Method, 4}, - {"(*PrivateKey).Size", Method, 11}, - {"(*PrivateKey).Validate", Method, 0}, - {"(*PublicKey).Equal", Method, 15}, - {"(*PublicKey).Size", Method, 11}, - {"CRTValue", Type, 0}, - {"CRTValue.Coeff", Field, 0}, - {"CRTValue.Exp", Field, 0}, - {"CRTValue.R", Field, 0}, - {"DecryptOAEP", Func, 0}, - {"DecryptPKCS1v15", Func, 0}, - {"DecryptPKCS1v15SessionKey", Func, 0}, - {"EncryptOAEP", Func, 0}, - {"EncryptPKCS1v15", Func, 0}, - {"ErrDecryption", Var, 0}, - {"ErrMessageTooLong", Var, 0}, - {"ErrVerification", Var, 0}, - {"GenerateKey", Func, 0}, - {"GenerateMultiPrimeKey", Func, 0}, - {"OAEPOptions", Type, 5}, - {"OAEPOptions.Hash", Field, 5}, - {"OAEPOptions.Label", Field, 5}, - {"OAEPOptions.MGFHash", Field, 20}, - {"PKCS1v15DecryptOptions", Type, 5}, - {"PKCS1v15DecryptOptions.SessionKeyLen", Field, 5}, - {"PSSOptions", Type, 2}, - {"PSSOptions.Hash", Field, 4}, - {"PSSOptions.SaltLength", Field, 2}, - {"PSSSaltLengthAuto", Const, 2}, - {"PSSSaltLengthEqualsHash", Const, 2}, - {"PrecomputedValues", Type, 0}, - {"PrecomputedValues.CRTValues", Field, 0}, - {"PrecomputedValues.Dp", Field, 0}, - {"PrecomputedValues.Dq", Field, 0}, - {"PrecomputedValues.Qinv", Field, 0}, - {"PrivateKey", Type, 0}, - {"PrivateKey.D", Field, 0}, - {"PrivateKey.Precomputed", Field, 0}, - {"PrivateKey.Primes", Field, 0}, - {"PrivateKey.PublicKey", Field, 0}, - {"PublicKey", Type, 0}, - {"PublicKey.E", Field, 0}, - {"PublicKey.N", Field, 0}, - {"SignPKCS1v15", Func, 0}, - {"SignPSS", Func, 2}, - {"VerifyPKCS1v15", Func, 0}, - {"VerifyPSS", Func, 2}, + {"(*PSSOptions).HashFunc", Method, 4, ""}, + {"(*PrivateKey).Decrypt", Method, 5, ""}, + {"(*PrivateKey).Equal", Method, 15, ""}, + {"(*PrivateKey).Precompute", Method, 0, ""}, + {"(*PrivateKey).Public", Method, 4, ""}, + {"(*PrivateKey).Sign", Method, 4, ""}, + {"(*PrivateKey).Size", Method, 11, ""}, + {"(*PrivateKey).Validate", Method, 0, ""}, + {"(*PublicKey).Equal", Method, 15, ""}, + {"(*PublicKey).Size", Method, 11, ""}, + {"CRTValue", Type, 0, ""}, + {"CRTValue.Coeff", Field, 0, ""}, + {"CRTValue.Exp", Field, 0, ""}, + {"CRTValue.R", Field, 0, ""}, + {"DecryptOAEP", Func, 0, "func(hash hash.Hash, random io.Reader, priv *PrivateKey, ciphertext []byte, label []byte) ([]byte, error)"}, + {"DecryptPKCS1v15", Func, 0, "func(random io.Reader, priv *PrivateKey, ciphertext []byte) ([]byte, error)"}, + {"DecryptPKCS1v15SessionKey", Func, 0, "func(random io.Reader, priv *PrivateKey, ciphertext []byte, key []byte) error"}, + {"EncryptOAEP", Func, 0, "func(hash hash.Hash, random io.Reader, pub *PublicKey, msg []byte, label []byte) ([]byte, error)"}, + {"EncryptPKCS1v15", Func, 0, "func(random io.Reader, pub *PublicKey, msg []byte) ([]byte, error)"}, + {"ErrDecryption", Var, 0, ""}, + {"ErrMessageTooLong", Var, 0, ""}, + {"ErrVerification", Var, 0, ""}, + {"GenerateKey", Func, 0, "func(random io.Reader, bits int) (*PrivateKey, error)"}, + {"GenerateMultiPrimeKey", Func, 0, "func(random io.Reader, nprimes int, bits int) (*PrivateKey, error)"}, + {"OAEPOptions", Type, 5, ""}, + {"OAEPOptions.Hash", Field, 5, ""}, + {"OAEPOptions.Label", Field, 5, ""}, + {"OAEPOptions.MGFHash", Field, 20, ""}, + {"PKCS1v15DecryptOptions", Type, 5, ""}, + {"PKCS1v15DecryptOptions.SessionKeyLen", Field, 5, ""}, + {"PSSOptions", Type, 2, ""}, + {"PSSOptions.Hash", Field, 4, ""}, + {"PSSOptions.SaltLength", Field, 2, ""}, + {"PSSSaltLengthAuto", Const, 2, ""}, + {"PSSSaltLengthEqualsHash", Const, 2, ""}, + {"PrecomputedValues", Type, 0, ""}, + {"PrecomputedValues.CRTValues", Field, 0, ""}, + {"PrecomputedValues.Dp", Field, 0, ""}, + {"PrecomputedValues.Dq", Field, 0, ""}, + {"PrecomputedValues.Qinv", Field, 0, ""}, + {"PrivateKey", Type, 0, ""}, + {"PrivateKey.D", Field, 0, ""}, + {"PrivateKey.Precomputed", Field, 0, ""}, + {"PrivateKey.Primes", Field, 0, ""}, + {"PrivateKey.PublicKey", Field, 0, ""}, + {"PublicKey", Type, 0, ""}, + {"PublicKey.E", Field, 0, ""}, + {"PublicKey.N", Field, 0, ""}, + {"SignPKCS1v15", Func, 0, "func(random io.Reader, priv *PrivateKey, hash crypto.Hash, hashed []byte) ([]byte, error)"}, + {"SignPSS", Func, 2, "func(rand io.Reader, priv *PrivateKey, hash crypto.Hash, digest []byte, opts *PSSOptions) ([]byte, error)"}, + {"VerifyPKCS1v15", Func, 0, "func(pub *PublicKey, hash crypto.Hash, hashed []byte, sig []byte) error"}, + {"VerifyPSS", Func, 2, "func(pub *PublicKey, hash crypto.Hash, digest []byte, sig []byte, opts *PSSOptions) error"}, }, "crypto/sha1": { - {"BlockSize", Const, 0}, - {"New", Func, 0}, - {"Size", Const, 0}, - {"Sum", Func, 2}, + {"BlockSize", Const, 0, ""}, + {"New", Func, 0, "func() hash.Hash"}, + {"Size", Const, 0, ""}, + {"Sum", Func, 2, "func(data []byte) [20]byte"}, }, "crypto/sha256": { - {"BlockSize", Const, 0}, - {"New", Func, 0}, - {"New224", Func, 0}, - {"Size", Const, 0}, - {"Size224", Const, 0}, - {"Sum224", Func, 2}, - {"Sum256", Func, 2}, + {"BlockSize", Const, 0, ""}, + {"New", Func, 0, "func() hash.Hash"}, + {"New224", Func, 0, "func() hash.Hash"}, + {"Size", Const, 0, ""}, + {"Size224", Const, 0, ""}, + {"Sum224", Func, 2, "func(data []byte) [28]byte"}, + {"Sum256", Func, 2, "func(data []byte) [32]byte"}, }, "crypto/sha3": { - {"(*SHA3).AppendBinary", Method, 24}, - {"(*SHA3).BlockSize", Method, 24}, - {"(*SHA3).MarshalBinary", Method, 24}, - {"(*SHA3).Reset", Method, 24}, - {"(*SHA3).Size", Method, 24}, - {"(*SHA3).Sum", Method, 24}, - {"(*SHA3).UnmarshalBinary", Method, 24}, - {"(*SHA3).Write", Method, 24}, - {"(*SHAKE).AppendBinary", Method, 24}, - {"(*SHAKE).BlockSize", Method, 24}, - {"(*SHAKE).MarshalBinary", Method, 24}, - {"(*SHAKE).Read", Method, 24}, - {"(*SHAKE).Reset", Method, 24}, - {"(*SHAKE).UnmarshalBinary", Method, 24}, - {"(*SHAKE).Write", Method, 24}, - {"New224", Func, 24}, - {"New256", Func, 24}, - {"New384", Func, 24}, - {"New512", Func, 24}, - {"NewCSHAKE128", Func, 24}, - {"NewCSHAKE256", Func, 24}, - {"NewSHAKE128", Func, 24}, - {"NewSHAKE256", Func, 24}, - {"SHA3", Type, 24}, - {"SHAKE", Type, 24}, - {"Sum224", Func, 24}, - {"Sum256", Func, 24}, - {"Sum384", Func, 24}, - {"Sum512", Func, 24}, - {"SumSHAKE128", Func, 24}, - {"SumSHAKE256", Func, 24}, + {"(*SHA3).AppendBinary", Method, 24, ""}, + {"(*SHA3).BlockSize", Method, 24, ""}, + {"(*SHA3).MarshalBinary", Method, 24, ""}, + {"(*SHA3).Reset", Method, 24, ""}, + {"(*SHA3).Size", Method, 24, ""}, + {"(*SHA3).Sum", Method, 24, ""}, + {"(*SHA3).UnmarshalBinary", Method, 24, ""}, + {"(*SHA3).Write", Method, 24, ""}, + {"(*SHAKE).AppendBinary", Method, 24, ""}, + {"(*SHAKE).BlockSize", Method, 24, ""}, + {"(*SHAKE).MarshalBinary", Method, 24, ""}, + {"(*SHAKE).Read", Method, 24, ""}, + {"(*SHAKE).Reset", Method, 24, ""}, + {"(*SHAKE).UnmarshalBinary", Method, 24, ""}, + {"(*SHAKE).Write", Method, 24, ""}, + {"New224", Func, 24, "func() *SHA3"}, + {"New256", Func, 24, "func() *SHA3"}, + {"New384", Func, 24, "func() *SHA3"}, + {"New512", Func, 24, "func() *SHA3"}, + {"NewCSHAKE128", Func, 24, "func(N []byte, S []byte) *SHAKE"}, + {"NewCSHAKE256", Func, 24, "func(N []byte, S []byte) *SHAKE"}, + {"NewSHAKE128", Func, 24, "func() *SHAKE"}, + {"NewSHAKE256", Func, 24, "func() *SHAKE"}, + {"SHA3", Type, 24, ""}, + {"SHAKE", Type, 24, ""}, + {"Sum224", Func, 24, "func(data []byte) [28]byte"}, + {"Sum256", Func, 24, "func(data []byte) [32]byte"}, + {"Sum384", Func, 24, "func(data []byte) [48]byte"}, + {"Sum512", Func, 24, "func(data []byte) [64]byte"}, + {"SumSHAKE128", Func, 24, "func(data []byte, length int) []byte"}, + {"SumSHAKE256", Func, 24, "func(data []byte, length int) []byte"}, }, "crypto/sha512": { - {"BlockSize", Const, 0}, - {"New", Func, 0}, - {"New384", Func, 0}, - {"New512_224", Func, 5}, - {"New512_256", Func, 5}, - {"Size", Const, 0}, - {"Size224", Const, 5}, - {"Size256", Const, 5}, - {"Size384", Const, 0}, - {"Sum384", Func, 2}, - {"Sum512", Func, 2}, - {"Sum512_224", Func, 5}, - {"Sum512_256", Func, 5}, + {"BlockSize", Const, 0, ""}, + {"New", Func, 0, "func() hash.Hash"}, + {"New384", Func, 0, "func() hash.Hash"}, + {"New512_224", Func, 5, "func() hash.Hash"}, + {"New512_256", Func, 5, "func() hash.Hash"}, + {"Size", Const, 0, ""}, + {"Size224", Const, 5, ""}, + {"Size256", Const, 5, ""}, + {"Size384", Const, 0, ""}, + {"Sum384", Func, 2, "func(data []byte) [48]byte"}, + {"Sum512", Func, 2, "func(data []byte) [64]byte"}, + {"Sum512_224", Func, 5, "func(data []byte) [28]byte"}, + {"Sum512_256", Func, 5, "func(data []byte) [32]byte"}, }, "crypto/subtle": { - {"ConstantTimeByteEq", Func, 0}, - {"ConstantTimeCompare", Func, 0}, - {"ConstantTimeCopy", Func, 0}, - {"ConstantTimeEq", Func, 0}, - {"ConstantTimeLessOrEq", Func, 2}, - {"ConstantTimeSelect", Func, 0}, - {"WithDataIndependentTiming", Func, 24}, - {"XORBytes", Func, 20}, + {"ConstantTimeByteEq", Func, 0, "func(x uint8, y uint8) int"}, + {"ConstantTimeCompare", Func, 0, "func(x []byte, y []byte) int"}, + {"ConstantTimeCopy", Func, 0, "func(v int, x []byte, y []byte)"}, + {"ConstantTimeEq", Func, 0, "func(x int32, y int32) int"}, + {"ConstantTimeLessOrEq", Func, 2, "func(x int, y int) int"}, + {"ConstantTimeSelect", Func, 0, "func(v int, x int, y int) int"}, + {"WithDataIndependentTiming", Func, 24, "func(f func())"}, + {"XORBytes", Func, 20, "func(dst []byte, x []byte, y []byte) int"}, }, "crypto/tls": { - {"(*CertificateRequestInfo).Context", Method, 17}, - {"(*CertificateRequestInfo).SupportsCertificate", Method, 14}, - {"(*CertificateVerificationError).Error", Method, 20}, - {"(*CertificateVerificationError).Unwrap", Method, 20}, - {"(*ClientHelloInfo).Context", Method, 17}, - {"(*ClientHelloInfo).SupportsCertificate", Method, 14}, - {"(*ClientSessionState).ResumptionState", Method, 21}, - {"(*Config).BuildNameToCertificate", Method, 0}, - {"(*Config).Clone", Method, 8}, - {"(*Config).DecryptTicket", Method, 21}, - {"(*Config).EncryptTicket", Method, 21}, - {"(*Config).SetSessionTicketKeys", Method, 5}, - {"(*Conn).Close", Method, 0}, - {"(*Conn).CloseWrite", Method, 8}, - {"(*Conn).ConnectionState", Method, 0}, - {"(*Conn).Handshake", Method, 0}, - {"(*Conn).HandshakeContext", Method, 17}, - {"(*Conn).LocalAddr", Method, 0}, - {"(*Conn).NetConn", Method, 18}, - {"(*Conn).OCSPResponse", Method, 0}, - {"(*Conn).Read", Method, 0}, - {"(*Conn).RemoteAddr", Method, 0}, - {"(*Conn).SetDeadline", Method, 0}, - {"(*Conn).SetReadDeadline", Method, 0}, - {"(*Conn).SetWriteDeadline", Method, 0}, - {"(*Conn).VerifyHostname", Method, 0}, - {"(*Conn).Write", Method, 0}, - {"(*ConnectionState).ExportKeyingMaterial", Method, 11}, - {"(*Dialer).Dial", Method, 15}, - {"(*Dialer).DialContext", Method, 15}, - {"(*ECHRejectionError).Error", Method, 23}, - {"(*QUICConn).Close", Method, 21}, - {"(*QUICConn).ConnectionState", Method, 21}, - {"(*QUICConn).HandleData", Method, 21}, - {"(*QUICConn).NextEvent", Method, 21}, - {"(*QUICConn).SendSessionTicket", Method, 21}, - {"(*QUICConn).SetTransportParameters", Method, 21}, - {"(*QUICConn).Start", Method, 21}, - {"(*QUICConn).StoreSession", Method, 23}, - {"(*SessionState).Bytes", Method, 21}, - {"(AlertError).Error", Method, 21}, - {"(ClientAuthType).String", Method, 15}, - {"(CurveID).String", Method, 15}, - {"(QUICEncryptionLevel).String", Method, 21}, - {"(RecordHeaderError).Error", Method, 6}, - {"(SignatureScheme).String", Method, 15}, - {"AlertError", Type, 21}, - {"Certificate", Type, 0}, - {"Certificate.Certificate", Field, 0}, - {"Certificate.Leaf", Field, 0}, - {"Certificate.OCSPStaple", Field, 0}, - {"Certificate.PrivateKey", Field, 0}, - {"Certificate.SignedCertificateTimestamps", Field, 5}, - {"Certificate.SupportedSignatureAlgorithms", Field, 14}, - {"CertificateRequestInfo", Type, 8}, - {"CertificateRequestInfo.AcceptableCAs", Field, 8}, - {"CertificateRequestInfo.SignatureSchemes", Field, 8}, - {"CertificateRequestInfo.Version", Field, 14}, - {"CertificateVerificationError", Type, 20}, - {"CertificateVerificationError.Err", Field, 20}, - {"CertificateVerificationError.UnverifiedCertificates", Field, 20}, - {"CipherSuite", Type, 14}, - {"CipherSuite.ID", Field, 14}, - {"CipherSuite.Insecure", Field, 14}, - {"CipherSuite.Name", Field, 14}, - {"CipherSuite.SupportedVersions", Field, 14}, - {"CipherSuiteName", Func, 14}, - {"CipherSuites", Func, 14}, - {"Client", Func, 0}, - {"ClientAuthType", Type, 0}, - {"ClientHelloInfo", Type, 4}, - {"ClientHelloInfo.CipherSuites", Field, 4}, - {"ClientHelloInfo.Conn", Field, 8}, - {"ClientHelloInfo.Extensions", Field, 24}, - {"ClientHelloInfo.ServerName", Field, 4}, - {"ClientHelloInfo.SignatureSchemes", Field, 8}, - {"ClientHelloInfo.SupportedCurves", Field, 4}, - {"ClientHelloInfo.SupportedPoints", Field, 4}, - {"ClientHelloInfo.SupportedProtos", Field, 8}, - {"ClientHelloInfo.SupportedVersions", Field, 8}, - {"ClientSessionCache", Type, 3}, - {"ClientSessionState", Type, 3}, - {"Config", Type, 0}, - {"Config.Certificates", Field, 0}, - {"Config.CipherSuites", Field, 0}, - {"Config.ClientAuth", Field, 0}, - {"Config.ClientCAs", Field, 0}, - {"Config.ClientSessionCache", Field, 3}, - {"Config.CurvePreferences", Field, 3}, - {"Config.DynamicRecordSizingDisabled", Field, 7}, - {"Config.EncryptedClientHelloConfigList", Field, 23}, - {"Config.EncryptedClientHelloKeys", Field, 24}, - {"Config.EncryptedClientHelloRejectionVerify", Field, 23}, - {"Config.GetCertificate", Field, 4}, - {"Config.GetClientCertificate", Field, 8}, - {"Config.GetConfigForClient", Field, 8}, - {"Config.InsecureSkipVerify", Field, 0}, - {"Config.KeyLogWriter", Field, 8}, - {"Config.MaxVersion", Field, 2}, - {"Config.MinVersion", Field, 2}, - {"Config.NameToCertificate", Field, 0}, - {"Config.NextProtos", Field, 0}, - {"Config.PreferServerCipherSuites", Field, 1}, - {"Config.Rand", Field, 0}, - {"Config.Renegotiation", Field, 7}, - {"Config.RootCAs", Field, 0}, - {"Config.ServerName", Field, 0}, - {"Config.SessionTicketKey", Field, 1}, - {"Config.SessionTicketsDisabled", Field, 1}, - {"Config.Time", Field, 0}, - {"Config.UnwrapSession", Field, 21}, - {"Config.VerifyConnection", Field, 15}, - {"Config.VerifyPeerCertificate", Field, 8}, - {"Config.WrapSession", Field, 21}, - {"Conn", Type, 0}, - {"ConnectionState", Type, 0}, - {"ConnectionState.CipherSuite", Field, 0}, - {"ConnectionState.CurveID", Field, 25}, - {"ConnectionState.DidResume", Field, 1}, - {"ConnectionState.ECHAccepted", Field, 23}, - {"ConnectionState.HandshakeComplete", Field, 0}, - {"ConnectionState.NegotiatedProtocol", Field, 0}, - {"ConnectionState.NegotiatedProtocolIsMutual", Field, 0}, - {"ConnectionState.OCSPResponse", Field, 5}, - {"ConnectionState.PeerCertificates", Field, 0}, - {"ConnectionState.ServerName", Field, 0}, - {"ConnectionState.SignedCertificateTimestamps", Field, 5}, - {"ConnectionState.TLSUnique", Field, 4}, - {"ConnectionState.VerifiedChains", Field, 0}, - {"ConnectionState.Version", Field, 3}, - {"CurveID", Type, 3}, - {"CurveP256", Const, 3}, - {"CurveP384", Const, 3}, - {"CurveP521", Const, 3}, - {"Dial", Func, 0}, - {"DialWithDialer", Func, 3}, - {"Dialer", Type, 15}, - {"Dialer.Config", Field, 15}, - {"Dialer.NetDialer", Field, 15}, - {"ECDSAWithP256AndSHA256", Const, 8}, - {"ECDSAWithP384AndSHA384", Const, 8}, - {"ECDSAWithP521AndSHA512", Const, 8}, - {"ECDSAWithSHA1", Const, 10}, - {"ECHRejectionError", Type, 23}, - {"ECHRejectionError.RetryConfigList", Field, 23}, - {"Ed25519", Const, 13}, - {"EncryptedClientHelloKey", Type, 24}, - {"EncryptedClientHelloKey.Config", Field, 24}, - {"EncryptedClientHelloKey.PrivateKey", Field, 24}, - {"EncryptedClientHelloKey.SendAsRetry", Field, 24}, - {"InsecureCipherSuites", Func, 14}, - {"Listen", Func, 0}, - {"LoadX509KeyPair", Func, 0}, - {"NewLRUClientSessionCache", Func, 3}, - {"NewListener", Func, 0}, - {"NewResumptionState", Func, 21}, - {"NoClientCert", Const, 0}, - {"PKCS1WithSHA1", Const, 8}, - {"PKCS1WithSHA256", Const, 8}, - {"PKCS1WithSHA384", Const, 8}, - {"PKCS1WithSHA512", Const, 8}, - {"PSSWithSHA256", Const, 8}, - {"PSSWithSHA384", Const, 8}, - {"PSSWithSHA512", Const, 8}, - {"ParseSessionState", Func, 21}, - {"QUICClient", Func, 21}, - {"QUICConfig", Type, 21}, - {"QUICConfig.EnableSessionEvents", Field, 23}, - {"QUICConfig.TLSConfig", Field, 21}, - {"QUICConn", Type, 21}, - {"QUICEncryptionLevel", Type, 21}, - {"QUICEncryptionLevelApplication", Const, 21}, - {"QUICEncryptionLevelEarly", Const, 21}, - {"QUICEncryptionLevelHandshake", Const, 21}, - {"QUICEncryptionLevelInitial", Const, 21}, - {"QUICEvent", Type, 21}, - {"QUICEvent.Data", Field, 21}, - {"QUICEvent.Kind", Field, 21}, - {"QUICEvent.Level", Field, 21}, - {"QUICEvent.SessionState", Field, 23}, - {"QUICEvent.Suite", Field, 21}, - {"QUICEventKind", Type, 21}, - {"QUICHandshakeDone", Const, 21}, - {"QUICNoEvent", Const, 21}, - {"QUICRejectedEarlyData", Const, 21}, - {"QUICResumeSession", Const, 23}, - {"QUICServer", Func, 21}, - {"QUICSessionTicketOptions", Type, 21}, - {"QUICSessionTicketOptions.EarlyData", Field, 21}, - {"QUICSessionTicketOptions.Extra", Field, 23}, - {"QUICSetReadSecret", Const, 21}, - {"QUICSetWriteSecret", Const, 21}, - {"QUICStoreSession", Const, 23}, - {"QUICTransportParameters", Const, 21}, - {"QUICTransportParametersRequired", Const, 21}, - {"QUICWriteData", Const, 21}, - {"RecordHeaderError", Type, 6}, - {"RecordHeaderError.Conn", Field, 12}, - {"RecordHeaderError.Msg", Field, 6}, - {"RecordHeaderError.RecordHeader", Field, 6}, - {"RenegotiateFreelyAsClient", Const, 7}, - {"RenegotiateNever", Const, 7}, - {"RenegotiateOnceAsClient", Const, 7}, - {"RenegotiationSupport", Type, 7}, - {"RequestClientCert", Const, 0}, - {"RequireAndVerifyClientCert", Const, 0}, - {"RequireAnyClientCert", Const, 0}, - {"Server", Func, 0}, - {"SessionState", Type, 21}, - {"SessionState.EarlyData", Field, 21}, - {"SessionState.Extra", Field, 21}, - {"SignatureScheme", Type, 8}, - {"TLS_AES_128_GCM_SHA256", Const, 12}, - {"TLS_AES_256_GCM_SHA384", Const, 12}, - {"TLS_CHACHA20_POLY1305_SHA256", Const, 12}, - {"TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA", Const, 2}, - {"TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256", Const, 8}, - {"TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256", Const, 2}, - {"TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA", Const, 2}, - {"TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384", Const, 5}, - {"TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305", Const, 8}, - {"TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256", Const, 14}, - {"TLS_ECDHE_ECDSA_WITH_RC4_128_SHA", Const, 2}, - {"TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA", Const, 0}, - {"TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA", Const, 0}, - {"TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256", Const, 8}, - {"TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256", Const, 2}, - {"TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA", Const, 1}, - {"TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384", Const, 5}, - {"TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305", Const, 8}, - {"TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256", Const, 14}, - {"TLS_ECDHE_RSA_WITH_RC4_128_SHA", Const, 0}, - {"TLS_FALLBACK_SCSV", Const, 4}, - {"TLS_RSA_WITH_3DES_EDE_CBC_SHA", Const, 0}, - {"TLS_RSA_WITH_AES_128_CBC_SHA", Const, 0}, - {"TLS_RSA_WITH_AES_128_CBC_SHA256", Const, 8}, - {"TLS_RSA_WITH_AES_128_GCM_SHA256", Const, 6}, - {"TLS_RSA_WITH_AES_256_CBC_SHA", Const, 1}, - {"TLS_RSA_WITH_AES_256_GCM_SHA384", Const, 6}, - {"TLS_RSA_WITH_RC4_128_SHA", Const, 0}, - {"VerifyClientCertIfGiven", Const, 0}, - {"VersionName", Func, 21}, - {"VersionSSL30", Const, 2}, - {"VersionTLS10", Const, 2}, - {"VersionTLS11", Const, 2}, - {"VersionTLS12", Const, 2}, - {"VersionTLS13", Const, 12}, - {"X25519", Const, 8}, - {"X25519MLKEM768", Const, 24}, - {"X509KeyPair", Func, 0}, + {"(*CertificateRequestInfo).Context", Method, 17, ""}, + {"(*CertificateRequestInfo).SupportsCertificate", Method, 14, ""}, + {"(*CertificateVerificationError).Error", Method, 20, ""}, + {"(*CertificateVerificationError).Unwrap", Method, 20, ""}, + {"(*ClientHelloInfo).Context", Method, 17, ""}, + {"(*ClientHelloInfo).SupportsCertificate", Method, 14, ""}, + {"(*ClientSessionState).ResumptionState", Method, 21, ""}, + {"(*Config).BuildNameToCertificate", Method, 0, ""}, + {"(*Config).Clone", Method, 8, ""}, + {"(*Config).DecryptTicket", Method, 21, ""}, + {"(*Config).EncryptTicket", Method, 21, ""}, + {"(*Config).SetSessionTicketKeys", Method, 5, ""}, + {"(*Conn).Close", Method, 0, ""}, + {"(*Conn).CloseWrite", Method, 8, ""}, + {"(*Conn).ConnectionState", Method, 0, ""}, + {"(*Conn).Handshake", Method, 0, ""}, + {"(*Conn).HandshakeContext", Method, 17, ""}, + {"(*Conn).LocalAddr", Method, 0, ""}, + {"(*Conn).NetConn", Method, 18, ""}, + {"(*Conn).OCSPResponse", Method, 0, ""}, + {"(*Conn).Read", Method, 0, ""}, + {"(*Conn).RemoteAddr", Method, 0, ""}, + {"(*Conn).SetDeadline", Method, 0, ""}, + {"(*Conn).SetReadDeadline", Method, 0, ""}, + {"(*Conn).SetWriteDeadline", Method, 0, ""}, + {"(*Conn).VerifyHostname", Method, 0, ""}, + {"(*Conn).Write", Method, 0, ""}, + {"(*ConnectionState).ExportKeyingMaterial", Method, 11, ""}, + {"(*Dialer).Dial", Method, 15, ""}, + {"(*Dialer).DialContext", Method, 15, ""}, + {"(*ECHRejectionError).Error", Method, 23, ""}, + {"(*QUICConn).Close", Method, 21, ""}, + {"(*QUICConn).ConnectionState", Method, 21, ""}, + {"(*QUICConn).HandleData", Method, 21, ""}, + {"(*QUICConn).NextEvent", Method, 21, ""}, + {"(*QUICConn).SendSessionTicket", Method, 21, ""}, + {"(*QUICConn).SetTransportParameters", Method, 21, ""}, + {"(*QUICConn).Start", Method, 21, ""}, + {"(*QUICConn).StoreSession", Method, 23, ""}, + {"(*SessionState).Bytes", Method, 21, ""}, + {"(AlertError).Error", Method, 21, ""}, + {"(ClientAuthType).String", Method, 15, ""}, + {"(CurveID).String", Method, 15, ""}, + {"(QUICEncryptionLevel).String", Method, 21, ""}, + {"(RecordHeaderError).Error", Method, 6, ""}, + {"(SignatureScheme).String", Method, 15, ""}, + {"AlertError", Type, 21, ""}, + {"Certificate", Type, 0, ""}, + {"Certificate.Certificate", Field, 0, ""}, + {"Certificate.Leaf", Field, 0, ""}, + {"Certificate.OCSPStaple", Field, 0, ""}, + {"Certificate.PrivateKey", Field, 0, ""}, + {"Certificate.SignedCertificateTimestamps", Field, 5, ""}, + {"Certificate.SupportedSignatureAlgorithms", Field, 14, ""}, + {"CertificateRequestInfo", Type, 8, ""}, + {"CertificateRequestInfo.AcceptableCAs", Field, 8, ""}, + {"CertificateRequestInfo.SignatureSchemes", Field, 8, ""}, + {"CertificateRequestInfo.Version", Field, 14, ""}, + {"CertificateVerificationError", Type, 20, ""}, + {"CertificateVerificationError.Err", Field, 20, ""}, + {"CertificateVerificationError.UnverifiedCertificates", Field, 20, ""}, + {"CipherSuite", Type, 14, ""}, + {"CipherSuite.ID", Field, 14, ""}, + {"CipherSuite.Insecure", Field, 14, ""}, + {"CipherSuite.Name", Field, 14, ""}, + {"CipherSuite.SupportedVersions", Field, 14, ""}, + {"CipherSuiteName", Func, 14, "func(id uint16) string"}, + {"CipherSuites", Func, 14, "func() []*CipherSuite"}, + {"Client", Func, 0, "func(conn net.Conn, config *Config) *Conn"}, + {"ClientAuthType", Type, 0, ""}, + {"ClientHelloInfo", Type, 4, ""}, + {"ClientHelloInfo.CipherSuites", Field, 4, ""}, + {"ClientHelloInfo.Conn", Field, 8, ""}, + {"ClientHelloInfo.Extensions", Field, 24, ""}, + {"ClientHelloInfo.ServerName", Field, 4, ""}, + {"ClientHelloInfo.SignatureSchemes", Field, 8, ""}, + {"ClientHelloInfo.SupportedCurves", Field, 4, ""}, + {"ClientHelloInfo.SupportedPoints", Field, 4, ""}, + {"ClientHelloInfo.SupportedProtos", Field, 8, ""}, + {"ClientHelloInfo.SupportedVersions", Field, 8, ""}, + {"ClientSessionCache", Type, 3, ""}, + {"ClientSessionState", Type, 3, ""}, + {"Config", Type, 0, ""}, + {"Config.Certificates", Field, 0, ""}, + {"Config.CipherSuites", Field, 0, ""}, + {"Config.ClientAuth", Field, 0, ""}, + {"Config.ClientCAs", Field, 0, ""}, + {"Config.ClientSessionCache", Field, 3, ""}, + {"Config.CurvePreferences", Field, 3, ""}, + {"Config.DynamicRecordSizingDisabled", Field, 7, ""}, + {"Config.EncryptedClientHelloConfigList", Field, 23, ""}, + {"Config.EncryptedClientHelloKeys", Field, 24, ""}, + {"Config.EncryptedClientHelloRejectionVerify", Field, 23, ""}, + {"Config.GetCertificate", Field, 4, ""}, + {"Config.GetClientCertificate", Field, 8, ""}, + {"Config.GetConfigForClient", Field, 8, ""}, + {"Config.InsecureSkipVerify", Field, 0, ""}, + {"Config.KeyLogWriter", Field, 8, ""}, + {"Config.MaxVersion", Field, 2, ""}, + {"Config.MinVersion", Field, 2, ""}, + {"Config.NameToCertificate", Field, 0, ""}, + {"Config.NextProtos", Field, 0, ""}, + {"Config.PreferServerCipherSuites", Field, 1, ""}, + {"Config.Rand", Field, 0, ""}, + {"Config.Renegotiation", Field, 7, ""}, + {"Config.RootCAs", Field, 0, ""}, + {"Config.ServerName", Field, 0, ""}, + {"Config.SessionTicketKey", Field, 1, ""}, + {"Config.SessionTicketsDisabled", Field, 1, ""}, + {"Config.Time", Field, 0, ""}, + {"Config.UnwrapSession", Field, 21, ""}, + {"Config.VerifyConnection", Field, 15, ""}, + {"Config.VerifyPeerCertificate", Field, 8, ""}, + {"Config.WrapSession", Field, 21, ""}, + {"Conn", Type, 0, ""}, + {"ConnectionState", Type, 0, ""}, + {"ConnectionState.CipherSuite", Field, 0, ""}, + {"ConnectionState.CurveID", Field, 25, ""}, + {"ConnectionState.DidResume", Field, 1, ""}, + {"ConnectionState.ECHAccepted", Field, 23, ""}, + {"ConnectionState.HandshakeComplete", Field, 0, ""}, + {"ConnectionState.NegotiatedProtocol", Field, 0, ""}, + {"ConnectionState.NegotiatedProtocolIsMutual", Field, 0, ""}, + {"ConnectionState.OCSPResponse", Field, 5, ""}, + {"ConnectionState.PeerCertificates", Field, 0, ""}, + {"ConnectionState.ServerName", Field, 0, ""}, + {"ConnectionState.SignedCertificateTimestamps", Field, 5, ""}, + {"ConnectionState.TLSUnique", Field, 4, ""}, + {"ConnectionState.VerifiedChains", Field, 0, ""}, + {"ConnectionState.Version", Field, 3, ""}, + {"CurveID", Type, 3, ""}, + {"CurveP256", Const, 3, ""}, + {"CurveP384", Const, 3, ""}, + {"CurveP521", Const, 3, ""}, + {"Dial", Func, 0, "func(network string, addr string, config *Config) (*Conn, error)"}, + {"DialWithDialer", Func, 3, "func(dialer *net.Dialer, network string, addr string, config *Config) (*Conn, error)"}, + {"Dialer", Type, 15, ""}, + {"Dialer.Config", Field, 15, ""}, + {"Dialer.NetDialer", Field, 15, ""}, + {"ECDSAWithP256AndSHA256", Const, 8, ""}, + {"ECDSAWithP384AndSHA384", Const, 8, ""}, + {"ECDSAWithP521AndSHA512", Const, 8, ""}, + {"ECDSAWithSHA1", Const, 10, ""}, + {"ECHRejectionError", Type, 23, ""}, + {"ECHRejectionError.RetryConfigList", Field, 23, ""}, + {"Ed25519", Const, 13, ""}, + {"EncryptedClientHelloKey", Type, 24, ""}, + {"EncryptedClientHelloKey.Config", Field, 24, ""}, + {"EncryptedClientHelloKey.PrivateKey", Field, 24, ""}, + {"EncryptedClientHelloKey.SendAsRetry", Field, 24, ""}, + {"InsecureCipherSuites", Func, 14, "func() []*CipherSuite"}, + {"Listen", Func, 0, "func(network string, laddr string, config *Config) (net.Listener, error)"}, + {"LoadX509KeyPair", Func, 0, "func(certFile string, keyFile string) (Certificate, error)"}, + {"NewLRUClientSessionCache", Func, 3, "func(capacity int) ClientSessionCache"}, + {"NewListener", Func, 0, "func(inner net.Listener, config *Config) net.Listener"}, + {"NewResumptionState", Func, 21, "func(ticket []byte, state *SessionState) (*ClientSessionState, error)"}, + {"NoClientCert", Const, 0, ""}, + {"PKCS1WithSHA1", Const, 8, ""}, + {"PKCS1WithSHA256", Const, 8, ""}, + {"PKCS1WithSHA384", Const, 8, ""}, + {"PKCS1WithSHA512", Const, 8, ""}, + {"PSSWithSHA256", Const, 8, ""}, + {"PSSWithSHA384", Const, 8, ""}, + {"PSSWithSHA512", Const, 8, ""}, + {"ParseSessionState", Func, 21, "func(data []byte) (*SessionState, error)"}, + {"QUICClient", Func, 21, "func(config *QUICConfig) *QUICConn"}, + {"QUICConfig", Type, 21, ""}, + {"QUICConfig.EnableSessionEvents", Field, 23, ""}, + {"QUICConfig.TLSConfig", Field, 21, ""}, + {"QUICConn", Type, 21, ""}, + {"QUICEncryptionLevel", Type, 21, ""}, + {"QUICEncryptionLevelApplication", Const, 21, ""}, + {"QUICEncryptionLevelEarly", Const, 21, ""}, + {"QUICEncryptionLevelHandshake", Const, 21, ""}, + {"QUICEncryptionLevelInitial", Const, 21, ""}, + {"QUICEvent", Type, 21, ""}, + {"QUICEvent.Data", Field, 21, ""}, + {"QUICEvent.Kind", Field, 21, ""}, + {"QUICEvent.Level", Field, 21, ""}, + {"QUICEvent.SessionState", Field, 23, ""}, + {"QUICEvent.Suite", Field, 21, ""}, + {"QUICEventKind", Type, 21, ""}, + {"QUICHandshakeDone", Const, 21, ""}, + {"QUICNoEvent", Const, 21, ""}, + {"QUICRejectedEarlyData", Const, 21, ""}, + {"QUICResumeSession", Const, 23, ""}, + {"QUICServer", Func, 21, "func(config *QUICConfig) *QUICConn"}, + {"QUICSessionTicketOptions", Type, 21, ""}, + {"QUICSessionTicketOptions.EarlyData", Field, 21, ""}, + {"QUICSessionTicketOptions.Extra", Field, 23, ""}, + {"QUICSetReadSecret", Const, 21, ""}, + {"QUICSetWriteSecret", Const, 21, ""}, + {"QUICStoreSession", Const, 23, ""}, + {"QUICTransportParameters", Const, 21, ""}, + {"QUICTransportParametersRequired", Const, 21, ""}, + {"QUICWriteData", Const, 21, ""}, + {"RecordHeaderError", Type, 6, ""}, + {"RecordHeaderError.Conn", Field, 12, ""}, + {"RecordHeaderError.Msg", Field, 6, ""}, + {"RecordHeaderError.RecordHeader", Field, 6, ""}, + {"RenegotiateFreelyAsClient", Const, 7, ""}, + {"RenegotiateNever", Const, 7, ""}, + {"RenegotiateOnceAsClient", Const, 7, ""}, + {"RenegotiationSupport", Type, 7, ""}, + {"RequestClientCert", Const, 0, ""}, + {"RequireAndVerifyClientCert", Const, 0, ""}, + {"RequireAnyClientCert", Const, 0, ""}, + {"Server", Func, 0, "func(conn net.Conn, config *Config) *Conn"}, + {"SessionState", Type, 21, ""}, + {"SessionState.EarlyData", Field, 21, ""}, + {"SessionState.Extra", Field, 21, ""}, + {"SignatureScheme", Type, 8, ""}, + {"TLS_AES_128_GCM_SHA256", Const, 12, ""}, + {"TLS_AES_256_GCM_SHA384", Const, 12, ""}, + {"TLS_CHACHA20_POLY1305_SHA256", Const, 12, ""}, + {"TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA", Const, 2, ""}, + {"TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256", Const, 8, ""}, + {"TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256", Const, 2, ""}, + {"TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA", Const, 2, ""}, + {"TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384", Const, 5, ""}, + {"TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305", Const, 8, ""}, + {"TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256", Const, 14, ""}, + {"TLS_ECDHE_ECDSA_WITH_RC4_128_SHA", Const, 2, ""}, + {"TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA", Const, 0, ""}, + {"TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA", Const, 0, ""}, + {"TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256", Const, 8, ""}, + {"TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256", Const, 2, ""}, + {"TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA", Const, 1, ""}, + {"TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384", Const, 5, ""}, + {"TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305", Const, 8, ""}, + {"TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256", Const, 14, ""}, + {"TLS_ECDHE_RSA_WITH_RC4_128_SHA", Const, 0, ""}, + {"TLS_FALLBACK_SCSV", Const, 4, ""}, + {"TLS_RSA_WITH_3DES_EDE_CBC_SHA", Const, 0, ""}, + {"TLS_RSA_WITH_AES_128_CBC_SHA", Const, 0, ""}, + {"TLS_RSA_WITH_AES_128_CBC_SHA256", Const, 8, ""}, + {"TLS_RSA_WITH_AES_128_GCM_SHA256", Const, 6, ""}, + {"TLS_RSA_WITH_AES_256_CBC_SHA", Const, 1, ""}, + {"TLS_RSA_WITH_AES_256_GCM_SHA384", Const, 6, ""}, + {"TLS_RSA_WITH_RC4_128_SHA", Const, 0, ""}, + {"VerifyClientCertIfGiven", Const, 0, ""}, + {"VersionName", Func, 21, "func(version uint16) string"}, + {"VersionSSL30", Const, 2, ""}, + {"VersionTLS10", Const, 2, ""}, + {"VersionTLS11", Const, 2, ""}, + {"VersionTLS12", Const, 2, ""}, + {"VersionTLS13", Const, 12, ""}, + {"X25519", Const, 8, ""}, + {"X25519MLKEM768", Const, 24, ""}, + {"X509KeyPair", Func, 0, "func(certPEMBlock []byte, keyPEMBlock []byte) (Certificate, error)"}, }, "crypto/x509": { - {"(*CertPool).AddCert", Method, 0}, - {"(*CertPool).AddCertWithConstraint", Method, 22}, - {"(*CertPool).AppendCertsFromPEM", Method, 0}, - {"(*CertPool).Clone", Method, 19}, - {"(*CertPool).Equal", Method, 19}, - {"(*CertPool).Subjects", Method, 0}, - {"(*Certificate).CheckCRLSignature", Method, 0}, - {"(*Certificate).CheckSignature", Method, 0}, - {"(*Certificate).CheckSignatureFrom", Method, 0}, - {"(*Certificate).CreateCRL", Method, 0}, - {"(*Certificate).Equal", Method, 0}, - {"(*Certificate).Verify", Method, 0}, - {"(*Certificate).VerifyHostname", Method, 0}, - {"(*CertificateRequest).CheckSignature", Method, 5}, - {"(*OID).UnmarshalBinary", Method, 23}, - {"(*OID).UnmarshalText", Method, 23}, - {"(*RevocationList).CheckSignatureFrom", Method, 19}, - {"(CertificateInvalidError).Error", Method, 0}, - {"(ConstraintViolationError).Error", Method, 0}, - {"(HostnameError).Error", Method, 0}, - {"(InsecureAlgorithmError).Error", Method, 6}, - {"(OID).AppendBinary", Method, 24}, - {"(OID).AppendText", Method, 24}, - {"(OID).Equal", Method, 22}, - {"(OID).EqualASN1OID", Method, 22}, - {"(OID).MarshalBinary", Method, 23}, - {"(OID).MarshalText", Method, 23}, - {"(OID).String", Method, 22}, - {"(PublicKeyAlgorithm).String", Method, 10}, - {"(SignatureAlgorithm).String", Method, 6}, - {"(SystemRootsError).Error", Method, 1}, - {"(SystemRootsError).Unwrap", Method, 16}, - {"(UnhandledCriticalExtension).Error", Method, 0}, - {"(UnknownAuthorityError).Error", Method, 0}, - {"CANotAuthorizedForExtKeyUsage", Const, 10}, - {"CANotAuthorizedForThisName", Const, 0}, - {"CertPool", Type, 0}, - {"Certificate", Type, 0}, - {"Certificate.AuthorityKeyId", Field, 0}, - {"Certificate.BasicConstraintsValid", Field, 0}, - {"Certificate.CRLDistributionPoints", Field, 2}, - {"Certificate.DNSNames", Field, 0}, - {"Certificate.EmailAddresses", Field, 0}, - {"Certificate.ExcludedDNSDomains", Field, 9}, - {"Certificate.ExcludedEmailAddresses", Field, 10}, - {"Certificate.ExcludedIPRanges", Field, 10}, - {"Certificate.ExcludedURIDomains", Field, 10}, - {"Certificate.ExtKeyUsage", Field, 0}, - {"Certificate.Extensions", Field, 2}, - {"Certificate.ExtraExtensions", Field, 2}, - {"Certificate.IPAddresses", Field, 1}, - {"Certificate.InhibitAnyPolicy", Field, 24}, - {"Certificate.InhibitAnyPolicyZero", Field, 24}, - {"Certificate.InhibitPolicyMapping", Field, 24}, - {"Certificate.InhibitPolicyMappingZero", Field, 24}, - {"Certificate.IsCA", Field, 0}, - {"Certificate.Issuer", Field, 0}, - {"Certificate.IssuingCertificateURL", Field, 2}, - {"Certificate.KeyUsage", Field, 0}, - {"Certificate.MaxPathLen", Field, 0}, - {"Certificate.MaxPathLenZero", Field, 4}, - {"Certificate.NotAfter", Field, 0}, - {"Certificate.NotBefore", Field, 0}, - {"Certificate.OCSPServer", Field, 2}, - {"Certificate.PermittedDNSDomains", Field, 0}, - {"Certificate.PermittedDNSDomainsCritical", Field, 0}, - {"Certificate.PermittedEmailAddresses", Field, 10}, - {"Certificate.PermittedIPRanges", Field, 10}, - {"Certificate.PermittedURIDomains", Field, 10}, - {"Certificate.Policies", Field, 22}, - {"Certificate.PolicyIdentifiers", Field, 0}, - {"Certificate.PolicyMappings", Field, 24}, - {"Certificate.PublicKey", Field, 0}, - {"Certificate.PublicKeyAlgorithm", Field, 0}, - {"Certificate.Raw", Field, 0}, - {"Certificate.RawIssuer", Field, 0}, - {"Certificate.RawSubject", Field, 0}, - {"Certificate.RawSubjectPublicKeyInfo", Field, 0}, - {"Certificate.RawTBSCertificate", Field, 0}, - {"Certificate.RequireExplicitPolicy", Field, 24}, - {"Certificate.RequireExplicitPolicyZero", Field, 24}, - {"Certificate.SerialNumber", Field, 0}, - {"Certificate.Signature", Field, 0}, - {"Certificate.SignatureAlgorithm", Field, 0}, - {"Certificate.Subject", Field, 0}, - {"Certificate.SubjectKeyId", Field, 0}, - {"Certificate.URIs", Field, 10}, - {"Certificate.UnhandledCriticalExtensions", Field, 5}, - {"Certificate.UnknownExtKeyUsage", Field, 0}, - {"Certificate.Version", Field, 0}, - {"CertificateInvalidError", Type, 0}, - {"CertificateInvalidError.Cert", Field, 0}, - {"CertificateInvalidError.Detail", Field, 10}, - {"CertificateInvalidError.Reason", Field, 0}, - {"CertificateRequest", Type, 3}, - {"CertificateRequest.Attributes", Field, 3}, - {"CertificateRequest.DNSNames", Field, 3}, - {"CertificateRequest.EmailAddresses", Field, 3}, - {"CertificateRequest.Extensions", Field, 3}, - {"CertificateRequest.ExtraExtensions", Field, 3}, - {"CertificateRequest.IPAddresses", Field, 3}, - {"CertificateRequest.PublicKey", Field, 3}, - {"CertificateRequest.PublicKeyAlgorithm", Field, 3}, - {"CertificateRequest.Raw", Field, 3}, - {"CertificateRequest.RawSubject", Field, 3}, - {"CertificateRequest.RawSubjectPublicKeyInfo", Field, 3}, - {"CertificateRequest.RawTBSCertificateRequest", Field, 3}, - {"CertificateRequest.Signature", Field, 3}, - {"CertificateRequest.SignatureAlgorithm", Field, 3}, - {"CertificateRequest.Subject", Field, 3}, - {"CertificateRequest.URIs", Field, 10}, - {"CertificateRequest.Version", Field, 3}, - {"ConstraintViolationError", Type, 0}, - {"CreateCertificate", Func, 0}, - {"CreateCertificateRequest", Func, 3}, - {"CreateRevocationList", Func, 15}, - {"DSA", Const, 0}, - {"DSAWithSHA1", Const, 0}, - {"DSAWithSHA256", Const, 0}, - {"DecryptPEMBlock", Func, 1}, - {"ECDSA", Const, 1}, - {"ECDSAWithSHA1", Const, 1}, - {"ECDSAWithSHA256", Const, 1}, - {"ECDSAWithSHA384", Const, 1}, - {"ECDSAWithSHA512", Const, 1}, - {"Ed25519", Const, 13}, - {"EncryptPEMBlock", Func, 1}, - {"ErrUnsupportedAlgorithm", Var, 0}, - {"Expired", Const, 0}, - {"ExtKeyUsage", Type, 0}, - {"ExtKeyUsageAny", Const, 0}, - {"ExtKeyUsageClientAuth", Const, 0}, - {"ExtKeyUsageCodeSigning", Const, 0}, - {"ExtKeyUsageEmailProtection", Const, 0}, - {"ExtKeyUsageIPSECEndSystem", Const, 1}, - {"ExtKeyUsageIPSECTunnel", Const, 1}, - {"ExtKeyUsageIPSECUser", Const, 1}, - {"ExtKeyUsageMicrosoftCommercialCodeSigning", Const, 10}, - {"ExtKeyUsageMicrosoftKernelCodeSigning", Const, 10}, - {"ExtKeyUsageMicrosoftServerGatedCrypto", Const, 1}, - {"ExtKeyUsageNetscapeServerGatedCrypto", Const, 1}, - {"ExtKeyUsageOCSPSigning", Const, 0}, - {"ExtKeyUsageServerAuth", Const, 0}, - {"ExtKeyUsageTimeStamping", Const, 0}, - {"HostnameError", Type, 0}, - {"HostnameError.Certificate", Field, 0}, - {"HostnameError.Host", Field, 0}, - {"IncompatibleUsage", Const, 1}, - {"IncorrectPasswordError", Var, 1}, - {"InsecureAlgorithmError", Type, 6}, - {"InvalidReason", Type, 0}, - {"IsEncryptedPEMBlock", Func, 1}, - {"KeyUsage", Type, 0}, - {"KeyUsageCRLSign", Const, 0}, - {"KeyUsageCertSign", Const, 0}, - {"KeyUsageContentCommitment", Const, 0}, - {"KeyUsageDataEncipherment", Const, 0}, - {"KeyUsageDecipherOnly", Const, 0}, - {"KeyUsageDigitalSignature", Const, 0}, - {"KeyUsageEncipherOnly", Const, 0}, - {"KeyUsageKeyAgreement", Const, 0}, - {"KeyUsageKeyEncipherment", Const, 0}, - {"MD2WithRSA", Const, 0}, - {"MD5WithRSA", Const, 0}, - {"MarshalECPrivateKey", Func, 2}, - {"MarshalPKCS1PrivateKey", Func, 0}, - {"MarshalPKCS1PublicKey", Func, 10}, - {"MarshalPKCS8PrivateKey", Func, 10}, - {"MarshalPKIXPublicKey", Func, 0}, - {"NameConstraintsWithoutSANs", Const, 10}, - {"NameMismatch", Const, 8}, - {"NewCertPool", Func, 0}, - {"NoValidChains", Const, 24}, - {"NotAuthorizedToSign", Const, 0}, - {"OID", Type, 22}, - {"OIDFromInts", Func, 22}, - {"PEMCipher", Type, 1}, - {"PEMCipher3DES", Const, 1}, - {"PEMCipherAES128", Const, 1}, - {"PEMCipherAES192", Const, 1}, - {"PEMCipherAES256", Const, 1}, - {"PEMCipherDES", Const, 1}, - {"ParseCRL", Func, 0}, - {"ParseCertificate", Func, 0}, - {"ParseCertificateRequest", Func, 3}, - {"ParseCertificates", Func, 0}, - {"ParseDERCRL", Func, 0}, - {"ParseECPrivateKey", Func, 1}, - {"ParseOID", Func, 23}, - {"ParsePKCS1PrivateKey", Func, 0}, - {"ParsePKCS1PublicKey", Func, 10}, - {"ParsePKCS8PrivateKey", Func, 0}, - {"ParsePKIXPublicKey", Func, 0}, - {"ParseRevocationList", Func, 19}, - {"PolicyMapping", Type, 24}, - {"PolicyMapping.IssuerDomainPolicy", Field, 24}, - {"PolicyMapping.SubjectDomainPolicy", Field, 24}, - {"PublicKeyAlgorithm", Type, 0}, - {"PureEd25519", Const, 13}, - {"RSA", Const, 0}, - {"RevocationList", Type, 15}, - {"RevocationList.AuthorityKeyId", Field, 19}, - {"RevocationList.Extensions", Field, 19}, - {"RevocationList.ExtraExtensions", Field, 15}, - {"RevocationList.Issuer", Field, 19}, - {"RevocationList.NextUpdate", Field, 15}, - {"RevocationList.Number", Field, 15}, - {"RevocationList.Raw", Field, 19}, - {"RevocationList.RawIssuer", Field, 19}, - {"RevocationList.RawTBSRevocationList", Field, 19}, - {"RevocationList.RevokedCertificateEntries", Field, 21}, - {"RevocationList.RevokedCertificates", Field, 15}, - {"RevocationList.Signature", Field, 19}, - {"RevocationList.SignatureAlgorithm", Field, 15}, - {"RevocationList.ThisUpdate", Field, 15}, - {"RevocationListEntry", Type, 21}, - {"RevocationListEntry.Extensions", Field, 21}, - {"RevocationListEntry.ExtraExtensions", Field, 21}, - {"RevocationListEntry.Raw", Field, 21}, - {"RevocationListEntry.ReasonCode", Field, 21}, - {"RevocationListEntry.RevocationTime", Field, 21}, - {"RevocationListEntry.SerialNumber", Field, 21}, - {"SHA1WithRSA", Const, 0}, - {"SHA256WithRSA", Const, 0}, - {"SHA256WithRSAPSS", Const, 8}, - {"SHA384WithRSA", Const, 0}, - {"SHA384WithRSAPSS", Const, 8}, - {"SHA512WithRSA", Const, 0}, - {"SHA512WithRSAPSS", Const, 8}, - {"SetFallbackRoots", Func, 20}, - {"SignatureAlgorithm", Type, 0}, - {"SystemCertPool", Func, 7}, - {"SystemRootsError", Type, 1}, - {"SystemRootsError.Err", Field, 7}, - {"TooManyConstraints", Const, 10}, - {"TooManyIntermediates", Const, 0}, - {"UnconstrainedName", Const, 10}, - {"UnhandledCriticalExtension", Type, 0}, - {"UnknownAuthorityError", Type, 0}, - {"UnknownAuthorityError.Cert", Field, 8}, - {"UnknownPublicKeyAlgorithm", Const, 0}, - {"UnknownSignatureAlgorithm", Const, 0}, - {"VerifyOptions", Type, 0}, - {"VerifyOptions.CertificatePolicies", Field, 24}, - {"VerifyOptions.CurrentTime", Field, 0}, - {"VerifyOptions.DNSName", Field, 0}, - {"VerifyOptions.Intermediates", Field, 0}, - {"VerifyOptions.KeyUsages", Field, 1}, - {"VerifyOptions.MaxConstraintComparisions", Field, 10}, - {"VerifyOptions.Roots", Field, 0}, + {"(*CertPool).AddCert", Method, 0, ""}, + {"(*CertPool).AddCertWithConstraint", Method, 22, ""}, + {"(*CertPool).AppendCertsFromPEM", Method, 0, ""}, + {"(*CertPool).Clone", Method, 19, ""}, + {"(*CertPool).Equal", Method, 19, ""}, + {"(*CertPool).Subjects", Method, 0, ""}, + {"(*Certificate).CheckCRLSignature", Method, 0, ""}, + {"(*Certificate).CheckSignature", Method, 0, ""}, + {"(*Certificate).CheckSignatureFrom", Method, 0, ""}, + {"(*Certificate).CreateCRL", Method, 0, ""}, + {"(*Certificate).Equal", Method, 0, ""}, + {"(*Certificate).Verify", Method, 0, ""}, + {"(*Certificate).VerifyHostname", Method, 0, ""}, + {"(*CertificateRequest).CheckSignature", Method, 5, ""}, + {"(*OID).UnmarshalBinary", Method, 23, ""}, + {"(*OID).UnmarshalText", Method, 23, ""}, + {"(*RevocationList).CheckSignatureFrom", Method, 19, ""}, + {"(CertificateInvalidError).Error", Method, 0, ""}, + {"(ConstraintViolationError).Error", Method, 0, ""}, + {"(HostnameError).Error", Method, 0, ""}, + {"(InsecureAlgorithmError).Error", Method, 6, ""}, + {"(OID).AppendBinary", Method, 24, ""}, + {"(OID).AppendText", Method, 24, ""}, + {"(OID).Equal", Method, 22, ""}, + {"(OID).EqualASN1OID", Method, 22, ""}, + {"(OID).MarshalBinary", Method, 23, ""}, + {"(OID).MarshalText", Method, 23, ""}, + {"(OID).String", Method, 22, ""}, + {"(PublicKeyAlgorithm).String", Method, 10, ""}, + {"(SignatureAlgorithm).String", Method, 6, ""}, + {"(SystemRootsError).Error", Method, 1, ""}, + {"(SystemRootsError).Unwrap", Method, 16, ""}, + {"(UnhandledCriticalExtension).Error", Method, 0, ""}, + {"(UnknownAuthorityError).Error", Method, 0, ""}, + {"CANotAuthorizedForExtKeyUsage", Const, 10, ""}, + {"CANotAuthorizedForThisName", Const, 0, ""}, + {"CertPool", Type, 0, ""}, + {"Certificate", Type, 0, ""}, + {"Certificate.AuthorityKeyId", Field, 0, ""}, + {"Certificate.BasicConstraintsValid", Field, 0, ""}, + {"Certificate.CRLDistributionPoints", Field, 2, ""}, + {"Certificate.DNSNames", Field, 0, ""}, + {"Certificate.EmailAddresses", Field, 0, ""}, + {"Certificate.ExcludedDNSDomains", Field, 9, ""}, + {"Certificate.ExcludedEmailAddresses", Field, 10, ""}, + {"Certificate.ExcludedIPRanges", Field, 10, ""}, + {"Certificate.ExcludedURIDomains", Field, 10, ""}, + {"Certificate.ExtKeyUsage", Field, 0, ""}, + {"Certificate.Extensions", Field, 2, ""}, + {"Certificate.ExtraExtensions", Field, 2, ""}, + {"Certificate.IPAddresses", Field, 1, ""}, + {"Certificate.InhibitAnyPolicy", Field, 24, ""}, + {"Certificate.InhibitAnyPolicyZero", Field, 24, ""}, + {"Certificate.InhibitPolicyMapping", Field, 24, ""}, + {"Certificate.InhibitPolicyMappingZero", Field, 24, ""}, + {"Certificate.IsCA", Field, 0, ""}, + {"Certificate.Issuer", Field, 0, ""}, + {"Certificate.IssuingCertificateURL", Field, 2, ""}, + {"Certificate.KeyUsage", Field, 0, ""}, + {"Certificate.MaxPathLen", Field, 0, ""}, + {"Certificate.MaxPathLenZero", Field, 4, ""}, + {"Certificate.NotAfter", Field, 0, ""}, + {"Certificate.NotBefore", Field, 0, ""}, + {"Certificate.OCSPServer", Field, 2, ""}, + {"Certificate.PermittedDNSDomains", Field, 0, ""}, + {"Certificate.PermittedDNSDomainsCritical", Field, 0, ""}, + {"Certificate.PermittedEmailAddresses", Field, 10, ""}, + {"Certificate.PermittedIPRanges", Field, 10, ""}, + {"Certificate.PermittedURIDomains", Field, 10, ""}, + {"Certificate.Policies", Field, 22, ""}, + {"Certificate.PolicyIdentifiers", Field, 0, ""}, + {"Certificate.PolicyMappings", Field, 24, ""}, + {"Certificate.PublicKey", Field, 0, ""}, + {"Certificate.PublicKeyAlgorithm", Field, 0, ""}, + {"Certificate.Raw", Field, 0, ""}, + {"Certificate.RawIssuer", Field, 0, ""}, + {"Certificate.RawSubject", Field, 0, ""}, + {"Certificate.RawSubjectPublicKeyInfo", Field, 0, ""}, + {"Certificate.RawTBSCertificate", Field, 0, ""}, + {"Certificate.RequireExplicitPolicy", Field, 24, ""}, + {"Certificate.RequireExplicitPolicyZero", Field, 24, ""}, + {"Certificate.SerialNumber", Field, 0, ""}, + {"Certificate.Signature", Field, 0, ""}, + {"Certificate.SignatureAlgorithm", Field, 0, ""}, + {"Certificate.Subject", Field, 0, ""}, + {"Certificate.SubjectKeyId", Field, 0, ""}, + {"Certificate.URIs", Field, 10, ""}, + {"Certificate.UnhandledCriticalExtensions", Field, 5, ""}, + {"Certificate.UnknownExtKeyUsage", Field, 0, ""}, + {"Certificate.Version", Field, 0, ""}, + {"CertificateInvalidError", Type, 0, ""}, + {"CertificateInvalidError.Cert", Field, 0, ""}, + {"CertificateInvalidError.Detail", Field, 10, ""}, + {"CertificateInvalidError.Reason", Field, 0, ""}, + {"CertificateRequest", Type, 3, ""}, + {"CertificateRequest.Attributes", Field, 3, ""}, + {"CertificateRequest.DNSNames", Field, 3, ""}, + {"CertificateRequest.EmailAddresses", Field, 3, ""}, + {"CertificateRequest.Extensions", Field, 3, ""}, + {"CertificateRequest.ExtraExtensions", Field, 3, ""}, + {"CertificateRequest.IPAddresses", Field, 3, ""}, + {"CertificateRequest.PublicKey", Field, 3, ""}, + {"CertificateRequest.PublicKeyAlgorithm", Field, 3, ""}, + {"CertificateRequest.Raw", Field, 3, ""}, + {"CertificateRequest.RawSubject", Field, 3, ""}, + {"CertificateRequest.RawSubjectPublicKeyInfo", Field, 3, ""}, + {"CertificateRequest.RawTBSCertificateRequest", Field, 3, ""}, + {"CertificateRequest.Signature", Field, 3, ""}, + {"CertificateRequest.SignatureAlgorithm", Field, 3, ""}, + {"CertificateRequest.Subject", Field, 3, ""}, + {"CertificateRequest.URIs", Field, 10, ""}, + {"CertificateRequest.Version", Field, 3, ""}, + {"ConstraintViolationError", Type, 0, ""}, + {"CreateCertificate", Func, 0, "func(rand io.Reader, template *Certificate, parent *Certificate, pub any, priv any) ([]byte, error)"}, + {"CreateCertificateRequest", Func, 3, "func(rand io.Reader, template *CertificateRequest, priv any) (csr []byte, err error)"}, + {"CreateRevocationList", Func, 15, "func(rand io.Reader, template *RevocationList, issuer *Certificate, priv crypto.Signer) ([]byte, error)"}, + {"DSA", Const, 0, ""}, + {"DSAWithSHA1", Const, 0, ""}, + {"DSAWithSHA256", Const, 0, ""}, + {"DecryptPEMBlock", Func, 1, "func(b *pem.Block, password []byte) ([]byte, error)"}, + {"ECDSA", Const, 1, ""}, + {"ECDSAWithSHA1", Const, 1, ""}, + {"ECDSAWithSHA256", Const, 1, ""}, + {"ECDSAWithSHA384", Const, 1, ""}, + {"ECDSAWithSHA512", Const, 1, ""}, + {"Ed25519", Const, 13, ""}, + {"EncryptPEMBlock", Func, 1, "func(rand io.Reader, blockType string, data []byte, password []byte, alg PEMCipher) (*pem.Block, error)"}, + {"ErrUnsupportedAlgorithm", Var, 0, ""}, + {"Expired", Const, 0, ""}, + {"ExtKeyUsage", Type, 0, ""}, + {"ExtKeyUsageAny", Const, 0, ""}, + {"ExtKeyUsageClientAuth", Const, 0, ""}, + {"ExtKeyUsageCodeSigning", Const, 0, ""}, + {"ExtKeyUsageEmailProtection", Const, 0, ""}, + {"ExtKeyUsageIPSECEndSystem", Const, 1, ""}, + {"ExtKeyUsageIPSECTunnel", Const, 1, ""}, + {"ExtKeyUsageIPSECUser", Const, 1, ""}, + {"ExtKeyUsageMicrosoftCommercialCodeSigning", Const, 10, ""}, + {"ExtKeyUsageMicrosoftKernelCodeSigning", Const, 10, ""}, + {"ExtKeyUsageMicrosoftServerGatedCrypto", Const, 1, ""}, + {"ExtKeyUsageNetscapeServerGatedCrypto", Const, 1, ""}, + {"ExtKeyUsageOCSPSigning", Const, 0, ""}, + {"ExtKeyUsageServerAuth", Const, 0, ""}, + {"ExtKeyUsageTimeStamping", Const, 0, ""}, + {"HostnameError", Type, 0, ""}, + {"HostnameError.Certificate", Field, 0, ""}, + {"HostnameError.Host", Field, 0, ""}, + {"IncompatibleUsage", Const, 1, ""}, + {"IncorrectPasswordError", Var, 1, ""}, + {"InsecureAlgorithmError", Type, 6, ""}, + {"InvalidReason", Type, 0, ""}, + {"IsEncryptedPEMBlock", Func, 1, "func(b *pem.Block) bool"}, + {"KeyUsage", Type, 0, ""}, + {"KeyUsageCRLSign", Const, 0, ""}, + {"KeyUsageCertSign", Const, 0, ""}, + {"KeyUsageContentCommitment", Const, 0, ""}, + {"KeyUsageDataEncipherment", Const, 0, ""}, + {"KeyUsageDecipherOnly", Const, 0, ""}, + {"KeyUsageDigitalSignature", Const, 0, ""}, + {"KeyUsageEncipherOnly", Const, 0, ""}, + {"KeyUsageKeyAgreement", Const, 0, ""}, + {"KeyUsageKeyEncipherment", Const, 0, ""}, + {"MD2WithRSA", Const, 0, ""}, + {"MD5WithRSA", Const, 0, ""}, + {"MarshalECPrivateKey", Func, 2, "func(key *ecdsa.PrivateKey) ([]byte, error)"}, + {"MarshalPKCS1PrivateKey", Func, 0, "func(key *rsa.PrivateKey) []byte"}, + {"MarshalPKCS1PublicKey", Func, 10, "func(key *rsa.PublicKey) []byte"}, + {"MarshalPKCS8PrivateKey", Func, 10, "func(key any) ([]byte, error)"}, + {"MarshalPKIXPublicKey", Func, 0, "func(pub any) ([]byte, error)"}, + {"NameConstraintsWithoutSANs", Const, 10, ""}, + {"NameMismatch", Const, 8, ""}, + {"NewCertPool", Func, 0, "func() *CertPool"}, + {"NoValidChains", Const, 24, ""}, + {"NotAuthorizedToSign", Const, 0, ""}, + {"OID", Type, 22, ""}, + {"OIDFromInts", Func, 22, "func(oid []uint64) (OID, error)"}, + {"PEMCipher", Type, 1, ""}, + {"PEMCipher3DES", Const, 1, ""}, + {"PEMCipherAES128", Const, 1, ""}, + {"PEMCipherAES192", Const, 1, ""}, + {"PEMCipherAES256", Const, 1, ""}, + {"PEMCipherDES", Const, 1, ""}, + {"ParseCRL", Func, 0, "func(crlBytes []byte) (*pkix.CertificateList, error)"}, + {"ParseCertificate", Func, 0, "func(der []byte) (*Certificate, error)"}, + {"ParseCertificateRequest", Func, 3, "func(asn1Data []byte) (*CertificateRequest, error)"}, + {"ParseCertificates", Func, 0, "func(der []byte) ([]*Certificate, error)"}, + {"ParseDERCRL", Func, 0, "func(derBytes []byte) (*pkix.CertificateList, error)"}, + {"ParseECPrivateKey", Func, 1, "func(der []byte) (*ecdsa.PrivateKey, error)"}, + {"ParseOID", Func, 23, "func(oid string) (OID, error)"}, + {"ParsePKCS1PrivateKey", Func, 0, "func(der []byte) (*rsa.PrivateKey, error)"}, + {"ParsePKCS1PublicKey", Func, 10, "func(der []byte) (*rsa.PublicKey, error)"}, + {"ParsePKCS8PrivateKey", Func, 0, "func(der []byte) (key any, err error)"}, + {"ParsePKIXPublicKey", Func, 0, "func(derBytes []byte) (pub any, err error)"}, + {"ParseRevocationList", Func, 19, "func(der []byte) (*RevocationList, error)"}, + {"PolicyMapping", Type, 24, ""}, + {"PolicyMapping.IssuerDomainPolicy", Field, 24, ""}, + {"PolicyMapping.SubjectDomainPolicy", Field, 24, ""}, + {"PublicKeyAlgorithm", Type, 0, ""}, + {"PureEd25519", Const, 13, ""}, + {"RSA", Const, 0, ""}, + {"RevocationList", Type, 15, ""}, + {"RevocationList.AuthorityKeyId", Field, 19, ""}, + {"RevocationList.Extensions", Field, 19, ""}, + {"RevocationList.ExtraExtensions", Field, 15, ""}, + {"RevocationList.Issuer", Field, 19, ""}, + {"RevocationList.NextUpdate", Field, 15, ""}, + {"RevocationList.Number", Field, 15, ""}, + {"RevocationList.Raw", Field, 19, ""}, + {"RevocationList.RawIssuer", Field, 19, ""}, + {"RevocationList.RawTBSRevocationList", Field, 19, ""}, + {"RevocationList.RevokedCertificateEntries", Field, 21, ""}, + {"RevocationList.RevokedCertificates", Field, 15, ""}, + {"RevocationList.Signature", Field, 19, ""}, + {"RevocationList.SignatureAlgorithm", Field, 15, ""}, + {"RevocationList.ThisUpdate", Field, 15, ""}, + {"RevocationListEntry", Type, 21, ""}, + {"RevocationListEntry.Extensions", Field, 21, ""}, + {"RevocationListEntry.ExtraExtensions", Field, 21, ""}, + {"RevocationListEntry.Raw", Field, 21, ""}, + {"RevocationListEntry.ReasonCode", Field, 21, ""}, + {"RevocationListEntry.RevocationTime", Field, 21, ""}, + {"RevocationListEntry.SerialNumber", Field, 21, ""}, + {"SHA1WithRSA", Const, 0, ""}, + {"SHA256WithRSA", Const, 0, ""}, + {"SHA256WithRSAPSS", Const, 8, ""}, + {"SHA384WithRSA", Const, 0, ""}, + {"SHA384WithRSAPSS", Const, 8, ""}, + {"SHA512WithRSA", Const, 0, ""}, + {"SHA512WithRSAPSS", Const, 8, ""}, + {"SetFallbackRoots", Func, 20, "func(roots *CertPool)"}, + {"SignatureAlgorithm", Type, 0, ""}, + {"SystemCertPool", Func, 7, "func() (*CertPool, error)"}, + {"SystemRootsError", Type, 1, ""}, + {"SystemRootsError.Err", Field, 7, ""}, + {"TooManyConstraints", Const, 10, ""}, + {"TooManyIntermediates", Const, 0, ""}, + {"UnconstrainedName", Const, 10, ""}, + {"UnhandledCriticalExtension", Type, 0, ""}, + {"UnknownAuthorityError", Type, 0, ""}, + {"UnknownAuthorityError.Cert", Field, 8, ""}, + {"UnknownPublicKeyAlgorithm", Const, 0, ""}, + {"UnknownSignatureAlgorithm", Const, 0, ""}, + {"VerifyOptions", Type, 0, ""}, + {"VerifyOptions.CertificatePolicies", Field, 24, ""}, + {"VerifyOptions.CurrentTime", Field, 0, ""}, + {"VerifyOptions.DNSName", Field, 0, ""}, + {"VerifyOptions.Intermediates", Field, 0, ""}, + {"VerifyOptions.KeyUsages", Field, 1, ""}, + {"VerifyOptions.MaxConstraintComparisions", Field, 10, ""}, + {"VerifyOptions.Roots", Field, 0, ""}, }, "crypto/x509/pkix": { - {"(*CertificateList).HasExpired", Method, 0}, - {"(*Name).FillFromRDNSequence", Method, 0}, - {"(Name).String", Method, 10}, - {"(Name).ToRDNSequence", Method, 0}, - {"(RDNSequence).String", Method, 10}, - {"AlgorithmIdentifier", Type, 0}, - {"AlgorithmIdentifier.Algorithm", Field, 0}, - {"AlgorithmIdentifier.Parameters", Field, 0}, - {"AttributeTypeAndValue", Type, 0}, - {"AttributeTypeAndValue.Type", Field, 0}, - {"AttributeTypeAndValue.Value", Field, 0}, - {"AttributeTypeAndValueSET", Type, 3}, - {"AttributeTypeAndValueSET.Type", Field, 3}, - {"AttributeTypeAndValueSET.Value", Field, 3}, - {"CertificateList", Type, 0}, - {"CertificateList.SignatureAlgorithm", Field, 0}, - {"CertificateList.SignatureValue", Field, 0}, - {"CertificateList.TBSCertList", Field, 0}, - {"Extension", Type, 0}, - {"Extension.Critical", Field, 0}, - {"Extension.Id", Field, 0}, - {"Extension.Value", Field, 0}, - {"Name", Type, 0}, - {"Name.CommonName", Field, 0}, - {"Name.Country", Field, 0}, - {"Name.ExtraNames", Field, 5}, - {"Name.Locality", Field, 0}, - {"Name.Names", Field, 0}, - {"Name.Organization", Field, 0}, - {"Name.OrganizationalUnit", Field, 0}, - {"Name.PostalCode", Field, 0}, - {"Name.Province", Field, 0}, - {"Name.SerialNumber", Field, 0}, - {"Name.StreetAddress", Field, 0}, - {"RDNSequence", Type, 0}, - {"RelativeDistinguishedNameSET", Type, 0}, - {"RevokedCertificate", Type, 0}, - {"RevokedCertificate.Extensions", Field, 0}, - {"RevokedCertificate.RevocationTime", Field, 0}, - {"RevokedCertificate.SerialNumber", Field, 0}, - {"TBSCertificateList", Type, 0}, - {"TBSCertificateList.Extensions", Field, 0}, - {"TBSCertificateList.Issuer", Field, 0}, - {"TBSCertificateList.NextUpdate", Field, 0}, - {"TBSCertificateList.Raw", Field, 0}, - {"TBSCertificateList.RevokedCertificates", Field, 0}, - {"TBSCertificateList.Signature", Field, 0}, - {"TBSCertificateList.ThisUpdate", Field, 0}, - {"TBSCertificateList.Version", Field, 0}, + {"(*CertificateList).HasExpired", Method, 0, ""}, + {"(*Name).FillFromRDNSequence", Method, 0, ""}, + {"(Name).String", Method, 10, ""}, + {"(Name).ToRDNSequence", Method, 0, ""}, + {"(RDNSequence).String", Method, 10, ""}, + {"AlgorithmIdentifier", Type, 0, ""}, + {"AlgorithmIdentifier.Algorithm", Field, 0, ""}, + {"AlgorithmIdentifier.Parameters", Field, 0, ""}, + {"AttributeTypeAndValue", Type, 0, ""}, + {"AttributeTypeAndValue.Type", Field, 0, ""}, + {"AttributeTypeAndValue.Value", Field, 0, ""}, + {"AttributeTypeAndValueSET", Type, 3, ""}, + {"AttributeTypeAndValueSET.Type", Field, 3, ""}, + {"AttributeTypeAndValueSET.Value", Field, 3, ""}, + {"CertificateList", Type, 0, ""}, + {"CertificateList.SignatureAlgorithm", Field, 0, ""}, + {"CertificateList.SignatureValue", Field, 0, ""}, + {"CertificateList.TBSCertList", Field, 0, ""}, + {"Extension", Type, 0, ""}, + {"Extension.Critical", Field, 0, ""}, + {"Extension.Id", Field, 0, ""}, + {"Extension.Value", Field, 0, ""}, + {"Name", Type, 0, ""}, + {"Name.CommonName", Field, 0, ""}, + {"Name.Country", Field, 0, ""}, + {"Name.ExtraNames", Field, 5, ""}, + {"Name.Locality", Field, 0, ""}, + {"Name.Names", Field, 0, ""}, + {"Name.Organization", Field, 0, ""}, + {"Name.OrganizationalUnit", Field, 0, ""}, + {"Name.PostalCode", Field, 0, ""}, + {"Name.Province", Field, 0, ""}, + {"Name.SerialNumber", Field, 0, ""}, + {"Name.StreetAddress", Field, 0, ""}, + {"RDNSequence", Type, 0, ""}, + {"RelativeDistinguishedNameSET", Type, 0, ""}, + {"RevokedCertificate", Type, 0, ""}, + {"RevokedCertificate.Extensions", Field, 0, ""}, + {"RevokedCertificate.RevocationTime", Field, 0, ""}, + {"RevokedCertificate.SerialNumber", Field, 0, ""}, + {"TBSCertificateList", Type, 0, ""}, + {"TBSCertificateList.Extensions", Field, 0, ""}, + {"TBSCertificateList.Issuer", Field, 0, ""}, + {"TBSCertificateList.NextUpdate", Field, 0, ""}, + {"TBSCertificateList.Raw", Field, 0, ""}, + {"TBSCertificateList.RevokedCertificates", Field, 0, ""}, + {"TBSCertificateList.Signature", Field, 0, ""}, + {"TBSCertificateList.ThisUpdate", Field, 0, ""}, + {"TBSCertificateList.Version", Field, 0, ""}, }, "database/sql": { - {"(*ColumnType).DatabaseTypeName", Method, 8}, - {"(*ColumnType).DecimalSize", Method, 8}, - {"(*ColumnType).Length", Method, 8}, - {"(*ColumnType).Name", Method, 8}, - {"(*ColumnType).Nullable", Method, 8}, - {"(*ColumnType).ScanType", Method, 8}, - {"(*Conn).BeginTx", Method, 9}, - {"(*Conn).Close", Method, 9}, - {"(*Conn).ExecContext", Method, 9}, - {"(*Conn).PingContext", Method, 9}, - {"(*Conn).PrepareContext", Method, 9}, - {"(*Conn).QueryContext", Method, 9}, - {"(*Conn).QueryRowContext", Method, 9}, - {"(*Conn).Raw", Method, 13}, - {"(*DB).Begin", Method, 0}, - {"(*DB).BeginTx", Method, 8}, - {"(*DB).Close", Method, 0}, - {"(*DB).Conn", Method, 9}, - {"(*DB).Driver", Method, 0}, - {"(*DB).Exec", Method, 0}, - {"(*DB).ExecContext", Method, 8}, - {"(*DB).Ping", Method, 1}, - {"(*DB).PingContext", Method, 8}, - {"(*DB).Prepare", Method, 0}, - {"(*DB).PrepareContext", Method, 8}, - {"(*DB).Query", Method, 0}, - {"(*DB).QueryContext", Method, 8}, - {"(*DB).QueryRow", Method, 0}, - {"(*DB).QueryRowContext", Method, 8}, - {"(*DB).SetConnMaxIdleTime", Method, 15}, - {"(*DB).SetConnMaxLifetime", Method, 6}, - {"(*DB).SetMaxIdleConns", Method, 1}, - {"(*DB).SetMaxOpenConns", Method, 2}, - {"(*DB).Stats", Method, 5}, - {"(*Null).Scan", Method, 22}, - {"(*NullBool).Scan", Method, 0}, - {"(*NullByte).Scan", Method, 17}, - {"(*NullFloat64).Scan", Method, 0}, - {"(*NullInt16).Scan", Method, 17}, - {"(*NullInt32).Scan", Method, 13}, - {"(*NullInt64).Scan", Method, 0}, - {"(*NullString).Scan", Method, 0}, - {"(*NullTime).Scan", Method, 13}, - {"(*Row).Err", Method, 15}, - {"(*Row).Scan", Method, 0}, - {"(*Rows).Close", Method, 0}, - {"(*Rows).ColumnTypes", Method, 8}, - {"(*Rows).Columns", Method, 0}, - {"(*Rows).Err", Method, 0}, - {"(*Rows).Next", Method, 0}, - {"(*Rows).NextResultSet", Method, 8}, - {"(*Rows).Scan", Method, 0}, - {"(*Stmt).Close", Method, 0}, - {"(*Stmt).Exec", Method, 0}, - {"(*Stmt).ExecContext", Method, 8}, - {"(*Stmt).Query", Method, 0}, - {"(*Stmt).QueryContext", Method, 8}, - {"(*Stmt).QueryRow", Method, 0}, - {"(*Stmt).QueryRowContext", Method, 8}, - {"(*Tx).Commit", Method, 0}, - {"(*Tx).Exec", Method, 0}, - {"(*Tx).ExecContext", Method, 8}, - {"(*Tx).Prepare", Method, 0}, - {"(*Tx).PrepareContext", Method, 8}, - {"(*Tx).Query", Method, 0}, - {"(*Tx).QueryContext", Method, 8}, - {"(*Tx).QueryRow", Method, 0}, - {"(*Tx).QueryRowContext", Method, 8}, - {"(*Tx).Rollback", Method, 0}, - {"(*Tx).Stmt", Method, 0}, - {"(*Tx).StmtContext", Method, 8}, - {"(IsolationLevel).String", Method, 11}, - {"(Null).Value", Method, 22}, - {"(NullBool).Value", Method, 0}, - {"(NullByte).Value", Method, 17}, - {"(NullFloat64).Value", Method, 0}, - {"(NullInt16).Value", Method, 17}, - {"(NullInt32).Value", Method, 13}, - {"(NullInt64).Value", Method, 0}, - {"(NullString).Value", Method, 0}, - {"(NullTime).Value", Method, 13}, - {"ColumnType", Type, 8}, - {"Conn", Type, 9}, - {"DB", Type, 0}, - {"DBStats", Type, 5}, - {"DBStats.Idle", Field, 11}, - {"DBStats.InUse", Field, 11}, - {"DBStats.MaxIdleClosed", Field, 11}, - {"DBStats.MaxIdleTimeClosed", Field, 15}, - {"DBStats.MaxLifetimeClosed", Field, 11}, - {"DBStats.MaxOpenConnections", Field, 11}, - {"DBStats.OpenConnections", Field, 5}, - {"DBStats.WaitCount", Field, 11}, - {"DBStats.WaitDuration", Field, 11}, - {"Drivers", Func, 4}, - {"ErrConnDone", Var, 9}, - {"ErrNoRows", Var, 0}, - {"ErrTxDone", Var, 0}, - {"IsolationLevel", Type, 8}, - {"LevelDefault", Const, 8}, - {"LevelLinearizable", Const, 8}, - {"LevelReadCommitted", Const, 8}, - {"LevelReadUncommitted", Const, 8}, - {"LevelRepeatableRead", Const, 8}, - {"LevelSerializable", Const, 8}, - {"LevelSnapshot", Const, 8}, - {"LevelWriteCommitted", Const, 8}, - {"Named", Func, 8}, - {"NamedArg", Type, 8}, - {"NamedArg.Name", Field, 8}, - {"NamedArg.Value", Field, 8}, - {"Null", Type, 22}, - {"Null.V", Field, 22}, - {"Null.Valid", Field, 22}, - {"NullBool", Type, 0}, - {"NullBool.Bool", Field, 0}, - {"NullBool.Valid", Field, 0}, - {"NullByte", Type, 17}, - {"NullByte.Byte", Field, 17}, - {"NullByte.Valid", Field, 17}, - {"NullFloat64", Type, 0}, - {"NullFloat64.Float64", Field, 0}, - {"NullFloat64.Valid", Field, 0}, - {"NullInt16", Type, 17}, - {"NullInt16.Int16", Field, 17}, - {"NullInt16.Valid", Field, 17}, - {"NullInt32", Type, 13}, - {"NullInt32.Int32", Field, 13}, - {"NullInt32.Valid", Field, 13}, - {"NullInt64", Type, 0}, - {"NullInt64.Int64", Field, 0}, - {"NullInt64.Valid", Field, 0}, - {"NullString", Type, 0}, - {"NullString.String", Field, 0}, - {"NullString.Valid", Field, 0}, - {"NullTime", Type, 13}, - {"NullTime.Time", Field, 13}, - {"NullTime.Valid", Field, 13}, - {"Open", Func, 0}, - {"OpenDB", Func, 10}, - {"Out", Type, 9}, - {"Out.Dest", Field, 9}, - {"Out.In", Field, 9}, - {"RawBytes", Type, 0}, - {"Register", Func, 0}, - {"Result", Type, 0}, - {"Row", Type, 0}, - {"Rows", Type, 0}, - {"Scanner", Type, 0}, - {"Stmt", Type, 0}, - {"Tx", Type, 0}, - {"TxOptions", Type, 8}, - {"TxOptions.Isolation", Field, 8}, - {"TxOptions.ReadOnly", Field, 8}, + {"(*ColumnType).DatabaseTypeName", Method, 8, ""}, + {"(*ColumnType).DecimalSize", Method, 8, ""}, + {"(*ColumnType).Length", Method, 8, ""}, + {"(*ColumnType).Name", Method, 8, ""}, + {"(*ColumnType).Nullable", Method, 8, ""}, + {"(*ColumnType).ScanType", Method, 8, ""}, + {"(*Conn).BeginTx", Method, 9, ""}, + {"(*Conn).Close", Method, 9, ""}, + {"(*Conn).ExecContext", Method, 9, ""}, + {"(*Conn).PingContext", Method, 9, ""}, + {"(*Conn).PrepareContext", Method, 9, ""}, + {"(*Conn).QueryContext", Method, 9, ""}, + {"(*Conn).QueryRowContext", Method, 9, ""}, + {"(*Conn).Raw", Method, 13, ""}, + {"(*DB).Begin", Method, 0, ""}, + {"(*DB).BeginTx", Method, 8, ""}, + {"(*DB).Close", Method, 0, ""}, + {"(*DB).Conn", Method, 9, ""}, + {"(*DB).Driver", Method, 0, ""}, + {"(*DB).Exec", Method, 0, ""}, + {"(*DB).ExecContext", Method, 8, ""}, + {"(*DB).Ping", Method, 1, ""}, + {"(*DB).PingContext", Method, 8, ""}, + {"(*DB).Prepare", Method, 0, ""}, + {"(*DB).PrepareContext", Method, 8, ""}, + {"(*DB).Query", Method, 0, ""}, + {"(*DB).QueryContext", Method, 8, ""}, + {"(*DB).QueryRow", Method, 0, ""}, + {"(*DB).QueryRowContext", Method, 8, ""}, + {"(*DB).SetConnMaxIdleTime", Method, 15, ""}, + {"(*DB).SetConnMaxLifetime", Method, 6, ""}, + {"(*DB).SetMaxIdleConns", Method, 1, ""}, + {"(*DB).SetMaxOpenConns", Method, 2, ""}, + {"(*DB).Stats", Method, 5, ""}, + {"(*Null).Scan", Method, 22, ""}, + {"(*NullBool).Scan", Method, 0, ""}, + {"(*NullByte).Scan", Method, 17, ""}, + {"(*NullFloat64).Scan", Method, 0, ""}, + {"(*NullInt16).Scan", Method, 17, ""}, + {"(*NullInt32).Scan", Method, 13, ""}, + {"(*NullInt64).Scan", Method, 0, ""}, + {"(*NullString).Scan", Method, 0, ""}, + {"(*NullTime).Scan", Method, 13, ""}, + {"(*Row).Err", Method, 15, ""}, + {"(*Row).Scan", Method, 0, ""}, + {"(*Rows).Close", Method, 0, ""}, + {"(*Rows).ColumnTypes", Method, 8, ""}, + {"(*Rows).Columns", Method, 0, ""}, + {"(*Rows).Err", Method, 0, ""}, + {"(*Rows).Next", Method, 0, ""}, + {"(*Rows).NextResultSet", Method, 8, ""}, + {"(*Rows).Scan", Method, 0, ""}, + {"(*Stmt).Close", Method, 0, ""}, + {"(*Stmt).Exec", Method, 0, ""}, + {"(*Stmt).ExecContext", Method, 8, ""}, + {"(*Stmt).Query", Method, 0, ""}, + {"(*Stmt).QueryContext", Method, 8, ""}, + {"(*Stmt).QueryRow", Method, 0, ""}, + {"(*Stmt).QueryRowContext", Method, 8, ""}, + {"(*Tx).Commit", Method, 0, ""}, + {"(*Tx).Exec", Method, 0, ""}, + {"(*Tx).ExecContext", Method, 8, ""}, + {"(*Tx).Prepare", Method, 0, ""}, + {"(*Tx).PrepareContext", Method, 8, ""}, + {"(*Tx).Query", Method, 0, ""}, + {"(*Tx).QueryContext", Method, 8, ""}, + {"(*Tx).QueryRow", Method, 0, ""}, + {"(*Tx).QueryRowContext", Method, 8, ""}, + {"(*Tx).Rollback", Method, 0, ""}, + {"(*Tx).Stmt", Method, 0, ""}, + {"(*Tx).StmtContext", Method, 8, ""}, + {"(IsolationLevel).String", Method, 11, ""}, + {"(Null).Value", Method, 22, ""}, + {"(NullBool).Value", Method, 0, ""}, + {"(NullByte).Value", Method, 17, ""}, + {"(NullFloat64).Value", Method, 0, ""}, + {"(NullInt16).Value", Method, 17, ""}, + {"(NullInt32).Value", Method, 13, ""}, + {"(NullInt64).Value", Method, 0, ""}, + {"(NullString).Value", Method, 0, ""}, + {"(NullTime).Value", Method, 13, ""}, + {"ColumnType", Type, 8, ""}, + {"Conn", Type, 9, ""}, + {"DB", Type, 0, ""}, + {"DBStats", Type, 5, ""}, + {"DBStats.Idle", Field, 11, ""}, + {"DBStats.InUse", Field, 11, ""}, + {"DBStats.MaxIdleClosed", Field, 11, ""}, + {"DBStats.MaxIdleTimeClosed", Field, 15, ""}, + {"DBStats.MaxLifetimeClosed", Field, 11, ""}, + {"DBStats.MaxOpenConnections", Field, 11, ""}, + {"DBStats.OpenConnections", Field, 5, ""}, + {"DBStats.WaitCount", Field, 11, ""}, + {"DBStats.WaitDuration", Field, 11, ""}, + {"Drivers", Func, 4, "func() []string"}, + {"ErrConnDone", Var, 9, ""}, + {"ErrNoRows", Var, 0, ""}, + {"ErrTxDone", Var, 0, ""}, + {"IsolationLevel", Type, 8, ""}, + {"LevelDefault", Const, 8, ""}, + {"LevelLinearizable", Const, 8, ""}, + {"LevelReadCommitted", Const, 8, ""}, + {"LevelReadUncommitted", Const, 8, ""}, + {"LevelRepeatableRead", Const, 8, ""}, + {"LevelSerializable", Const, 8, ""}, + {"LevelSnapshot", Const, 8, ""}, + {"LevelWriteCommitted", Const, 8, ""}, + {"Named", Func, 8, "func(name string, value any) NamedArg"}, + {"NamedArg", Type, 8, ""}, + {"NamedArg.Name", Field, 8, ""}, + {"NamedArg.Value", Field, 8, ""}, + {"Null", Type, 22, ""}, + {"Null.V", Field, 22, ""}, + {"Null.Valid", Field, 22, ""}, + {"NullBool", Type, 0, ""}, + {"NullBool.Bool", Field, 0, ""}, + {"NullBool.Valid", Field, 0, ""}, + {"NullByte", Type, 17, ""}, + {"NullByte.Byte", Field, 17, ""}, + {"NullByte.Valid", Field, 17, ""}, + {"NullFloat64", Type, 0, ""}, + {"NullFloat64.Float64", Field, 0, ""}, + {"NullFloat64.Valid", Field, 0, ""}, + {"NullInt16", Type, 17, ""}, + {"NullInt16.Int16", Field, 17, ""}, + {"NullInt16.Valid", Field, 17, ""}, + {"NullInt32", Type, 13, ""}, + {"NullInt32.Int32", Field, 13, ""}, + {"NullInt32.Valid", Field, 13, ""}, + {"NullInt64", Type, 0, ""}, + {"NullInt64.Int64", Field, 0, ""}, + {"NullInt64.Valid", Field, 0, ""}, + {"NullString", Type, 0, ""}, + {"NullString.String", Field, 0, ""}, + {"NullString.Valid", Field, 0, ""}, + {"NullTime", Type, 13, ""}, + {"NullTime.Time", Field, 13, ""}, + {"NullTime.Valid", Field, 13, ""}, + {"Open", Func, 0, "func(driverName string, dataSourceName string) (*DB, error)"}, + {"OpenDB", Func, 10, "func(c driver.Connector) *DB"}, + {"Out", Type, 9, ""}, + {"Out.Dest", Field, 9, ""}, + {"Out.In", Field, 9, ""}, + {"RawBytes", Type, 0, ""}, + {"Register", Func, 0, "func(name string, driver driver.Driver)"}, + {"Result", Type, 0, ""}, + {"Row", Type, 0, ""}, + {"Rows", Type, 0, ""}, + {"Scanner", Type, 0, ""}, + {"Stmt", Type, 0, ""}, + {"Tx", Type, 0, ""}, + {"TxOptions", Type, 8, ""}, + {"TxOptions.Isolation", Field, 8, ""}, + {"TxOptions.ReadOnly", Field, 8, ""}, }, "database/sql/driver": { - {"(NotNull).ConvertValue", Method, 0}, - {"(Null).ConvertValue", Method, 0}, - {"(RowsAffected).LastInsertId", Method, 0}, - {"(RowsAffected).RowsAffected", Method, 0}, - {"Bool", Var, 0}, - {"ColumnConverter", Type, 0}, - {"Conn", Type, 0}, - {"ConnBeginTx", Type, 8}, - {"ConnPrepareContext", Type, 8}, - {"Connector", Type, 10}, - {"DefaultParameterConverter", Var, 0}, - {"Driver", Type, 0}, - {"DriverContext", Type, 10}, - {"ErrBadConn", Var, 0}, - {"ErrRemoveArgument", Var, 9}, - {"ErrSkip", Var, 0}, - {"Execer", Type, 0}, - {"ExecerContext", Type, 8}, - {"Int32", Var, 0}, - {"IsScanValue", Func, 0}, - {"IsValue", Func, 0}, - {"IsolationLevel", Type, 8}, - {"NamedValue", Type, 8}, - {"NamedValue.Name", Field, 8}, - {"NamedValue.Ordinal", Field, 8}, - {"NamedValue.Value", Field, 8}, - {"NamedValueChecker", Type, 9}, - {"NotNull", Type, 0}, - {"NotNull.Converter", Field, 0}, - {"Null", Type, 0}, - {"Null.Converter", Field, 0}, - {"Pinger", Type, 8}, - {"Queryer", Type, 1}, - {"QueryerContext", Type, 8}, - {"Result", Type, 0}, - {"ResultNoRows", Var, 0}, - {"Rows", Type, 0}, - {"RowsAffected", Type, 0}, - {"RowsColumnTypeDatabaseTypeName", Type, 8}, - {"RowsColumnTypeLength", Type, 8}, - {"RowsColumnTypeNullable", Type, 8}, - {"RowsColumnTypePrecisionScale", Type, 8}, - {"RowsColumnTypeScanType", Type, 8}, - {"RowsNextResultSet", Type, 8}, - {"SessionResetter", Type, 10}, - {"Stmt", Type, 0}, - {"StmtExecContext", Type, 8}, - {"StmtQueryContext", Type, 8}, - {"String", Var, 0}, - {"Tx", Type, 0}, - {"TxOptions", Type, 8}, - {"TxOptions.Isolation", Field, 8}, - {"TxOptions.ReadOnly", Field, 8}, - {"Validator", Type, 15}, - {"Value", Type, 0}, - {"ValueConverter", Type, 0}, - {"Valuer", Type, 0}, + {"(NotNull).ConvertValue", Method, 0, ""}, + {"(Null).ConvertValue", Method, 0, ""}, + {"(RowsAffected).LastInsertId", Method, 0, ""}, + {"(RowsAffected).RowsAffected", Method, 0, ""}, + {"Bool", Var, 0, ""}, + {"ColumnConverter", Type, 0, ""}, + {"Conn", Type, 0, ""}, + {"ConnBeginTx", Type, 8, ""}, + {"ConnPrepareContext", Type, 8, ""}, + {"Connector", Type, 10, ""}, + {"DefaultParameterConverter", Var, 0, ""}, + {"Driver", Type, 0, ""}, + {"DriverContext", Type, 10, ""}, + {"ErrBadConn", Var, 0, ""}, + {"ErrRemoveArgument", Var, 9, ""}, + {"ErrSkip", Var, 0, ""}, + {"Execer", Type, 0, ""}, + {"ExecerContext", Type, 8, ""}, + {"Int32", Var, 0, ""}, + {"IsScanValue", Func, 0, "func(v any) bool"}, + {"IsValue", Func, 0, "func(v any) bool"}, + {"IsolationLevel", Type, 8, ""}, + {"NamedValue", Type, 8, ""}, + {"NamedValue.Name", Field, 8, ""}, + {"NamedValue.Ordinal", Field, 8, ""}, + {"NamedValue.Value", Field, 8, ""}, + {"NamedValueChecker", Type, 9, ""}, + {"NotNull", Type, 0, ""}, + {"NotNull.Converter", Field, 0, ""}, + {"Null", Type, 0, ""}, + {"Null.Converter", Field, 0, ""}, + {"Pinger", Type, 8, ""}, + {"Queryer", Type, 1, ""}, + {"QueryerContext", Type, 8, ""}, + {"Result", Type, 0, ""}, + {"ResultNoRows", Var, 0, ""}, + {"Rows", Type, 0, ""}, + {"RowsAffected", Type, 0, ""}, + {"RowsColumnTypeDatabaseTypeName", Type, 8, ""}, + {"RowsColumnTypeLength", Type, 8, ""}, + {"RowsColumnTypeNullable", Type, 8, ""}, + {"RowsColumnTypePrecisionScale", Type, 8, ""}, + {"RowsColumnTypeScanType", Type, 8, ""}, + {"RowsNextResultSet", Type, 8, ""}, + {"SessionResetter", Type, 10, ""}, + {"Stmt", Type, 0, ""}, + {"StmtExecContext", Type, 8, ""}, + {"StmtQueryContext", Type, 8, ""}, + {"String", Var, 0, ""}, + {"Tx", Type, 0, ""}, + {"TxOptions", Type, 8, ""}, + {"TxOptions.Isolation", Field, 8, ""}, + {"TxOptions.ReadOnly", Field, 8, ""}, + {"Validator", Type, 15, ""}, + {"Value", Type, 0, ""}, + {"ValueConverter", Type, 0, ""}, + {"Valuer", Type, 0, ""}, }, "debug/buildinfo": { - {"BuildInfo", Type, 18}, - {"Read", Func, 18}, - {"ReadFile", Func, 18}, + {"BuildInfo", Type, 18, ""}, + {"Read", Func, 18, "func(r io.ReaderAt) (*BuildInfo, error)"}, + {"ReadFile", Func, 18, "func(name string) (info *BuildInfo, err error)"}, }, "debug/dwarf": { - {"(*AddrType).Basic", Method, 0}, - {"(*AddrType).Common", Method, 0}, - {"(*AddrType).Size", Method, 0}, - {"(*AddrType).String", Method, 0}, - {"(*ArrayType).Common", Method, 0}, - {"(*ArrayType).Size", Method, 0}, - {"(*ArrayType).String", Method, 0}, - {"(*BasicType).Basic", Method, 0}, - {"(*BasicType).Common", Method, 0}, - {"(*BasicType).Size", Method, 0}, - {"(*BasicType).String", Method, 0}, - {"(*BoolType).Basic", Method, 0}, - {"(*BoolType).Common", Method, 0}, - {"(*BoolType).Size", Method, 0}, - {"(*BoolType).String", Method, 0}, - {"(*CharType).Basic", Method, 0}, - {"(*CharType).Common", Method, 0}, - {"(*CharType).Size", Method, 0}, - {"(*CharType).String", Method, 0}, - {"(*CommonType).Common", Method, 0}, - {"(*CommonType).Size", Method, 0}, - {"(*ComplexType).Basic", Method, 0}, - {"(*ComplexType).Common", Method, 0}, - {"(*ComplexType).Size", Method, 0}, - {"(*ComplexType).String", Method, 0}, - {"(*Data).AddSection", Method, 14}, - {"(*Data).AddTypes", Method, 3}, - {"(*Data).LineReader", Method, 5}, - {"(*Data).Ranges", Method, 7}, - {"(*Data).Reader", Method, 0}, - {"(*Data).Type", Method, 0}, - {"(*DotDotDotType).Common", Method, 0}, - {"(*DotDotDotType).Size", Method, 0}, - {"(*DotDotDotType).String", Method, 0}, - {"(*Entry).AttrField", Method, 5}, - {"(*Entry).Val", Method, 0}, - {"(*EnumType).Common", Method, 0}, - {"(*EnumType).Size", Method, 0}, - {"(*EnumType).String", Method, 0}, - {"(*FloatType).Basic", Method, 0}, - {"(*FloatType).Common", Method, 0}, - {"(*FloatType).Size", Method, 0}, - {"(*FloatType).String", Method, 0}, - {"(*FuncType).Common", Method, 0}, - {"(*FuncType).Size", Method, 0}, - {"(*FuncType).String", Method, 0}, - {"(*IntType).Basic", Method, 0}, - {"(*IntType).Common", Method, 0}, - {"(*IntType).Size", Method, 0}, - {"(*IntType).String", Method, 0}, - {"(*LineReader).Files", Method, 14}, - {"(*LineReader).Next", Method, 5}, - {"(*LineReader).Reset", Method, 5}, - {"(*LineReader).Seek", Method, 5}, - {"(*LineReader).SeekPC", Method, 5}, - {"(*LineReader).Tell", Method, 5}, - {"(*PtrType).Common", Method, 0}, - {"(*PtrType).Size", Method, 0}, - {"(*PtrType).String", Method, 0}, - {"(*QualType).Common", Method, 0}, - {"(*QualType).Size", Method, 0}, - {"(*QualType).String", Method, 0}, - {"(*Reader).AddressSize", Method, 5}, - {"(*Reader).ByteOrder", Method, 14}, - {"(*Reader).Next", Method, 0}, - {"(*Reader).Seek", Method, 0}, - {"(*Reader).SeekPC", Method, 7}, - {"(*Reader).SkipChildren", Method, 0}, - {"(*StructType).Common", Method, 0}, - {"(*StructType).Defn", Method, 0}, - {"(*StructType).Size", Method, 0}, - {"(*StructType).String", Method, 0}, - {"(*TypedefType).Common", Method, 0}, - {"(*TypedefType).Size", Method, 0}, - {"(*TypedefType).String", Method, 0}, - {"(*UcharType).Basic", Method, 0}, - {"(*UcharType).Common", Method, 0}, - {"(*UcharType).Size", Method, 0}, - {"(*UcharType).String", Method, 0}, - {"(*UintType).Basic", Method, 0}, - {"(*UintType).Common", Method, 0}, - {"(*UintType).Size", Method, 0}, - {"(*UintType).String", Method, 0}, - {"(*UnspecifiedType).Basic", Method, 4}, - {"(*UnspecifiedType).Common", Method, 4}, - {"(*UnspecifiedType).Size", Method, 4}, - {"(*UnspecifiedType).String", Method, 4}, - {"(*UnsupportedType).Common", Method, 13}, - {"(*UnsupportedType).Size", Method, 13}, - {"(*UnsupportedType).String", Method, 13}, - {"(*VoidType).Common", Method, 0}, - {"(*VoidType).Size", Method, 0}, - {"(*VoidType).String", Method, 0}, - {"(Attr).GoString", Method, 0}, - {"(Attr).String", Method, 0}, - {"(Class).GoString", Method, 5}, - {"(Class).String", Method, 5}, - {"(DecodeError).Error", Method, 0}, - {"(Tag).GoString", Method, 0}, - {"(Tag).String", Method, 0}, - {"AddrType", Type, 0}, - {"AddrType.BasicType", Field, 0}, - {"ArrayType", Type, 0}, - {"ArrayType.CommonType", Field, 0}, - {"ArrayType.Count", Field, 0}, - {"ArrayType.StrideBitSize", Field, 0}, - {"ArrayType.Type", Field, 0}, - {"Attr", Type, 0}, - {"AttrAbstractOrigin", Const, 0}, - {"AttrAccessibility", Const, 0}, - {"AttrAddrBase", Const, 14}, - {"AttrAddrClass", Const, 0}, - {"AttrAlignment", Const, 14}, - {"AttrAllocated", Const, 0}, - {"AttrArtificial", Const, 0}, - {"AttrAssociated", Const, 0}, - {"AttrBaseTypes", Const, 0}, - {"AttrBinaryScale", Const, 14}, - {"AttrBitOffset", Const, 0}, - {"AttrBitSize", Const, 0}, - {"AttrByteSize", Const, 0}, - {"AttrCallAllCalls", Const, 14}, - {"AttrCallAllSourceCalls", Const, 14}, - {"AttrCallAllTailCalls", Const, 14}, - {"AttrCallColumn", Const, 0}, - {"AttrCallDataLocation", Const, 14}, - {"AttrCallDataValue", Const, 14}, - {"AttrCallFile", Const, 0}, - {"AttrCallLine", Const, 0}, - {"AttrCallOrigin", Const, 14}, - {"AttrCallPC", Const, 14}, - {"AttrCallParameter", Const, 14}, - {"AttrCallReturnPC", Const, 14}, - {"AttrCallTailCall", Const, 14}, - {"AttrCallTarget", Const, 14}, - {"AttrCallTargetClobbered", Const, 14}, - {"AttrCallValue", Const, 14}, - {"AttrCalling", Const, 0}, - {"AttrCommonRef", Const, 0}, - {"AttrCompDir", Const, 0}, - {"AttrConstExpr", Const, 14}, - {"AttrConstValue", Const, 0}, - {"AttrContainingType", Const, 0}, - {"AttrCount", Const, 0}, - {"AttrDataBitOffset", Const, 14}, - {"AttrDataLocation", Const, 0}, - {"AttrDataMemberLoc", Const, 0}, - {"AttrDecimalScale", Const, 14}, - {"AttrDecimalSign", Const, 14}, - {"AttrDeclColumn", Const, 0}, - {"AttrDeclFile", Const, 0}, - {"AttrDeclLine", Const, 0}, - {"AttrDeclaration", Const, 0}, - {"AttrDefaultValue", Const, 0}, - {"AttrDefaulted", Const, 14}, - {"AttrDeleted", Const, 14}, - {"AttrDescription", Const, 0}, - {"AttrDigitCount", Const, 14}, - {"AttrDiscr", Const, 0}, - {"AttrDiscrList", Const, 0}, - {"AttrDiscrValue", Const, 0}, - {"AttrDwoName", Const, 14}, - {"AttrElemental", Const, 14}, - {"AttrEncoding", Const, 0}, - {"AttrEndianity", Const, 14}, - {"AttrEntrypc", Const, 0}, - {"AttrEnumClass", Const, 14}, - {"AttrExplicit", Const, 14}, - {"AttrExportSymbols", Const, 14}, - {"AttrExtension", Const, 0}, - {"AttrExternal", Const, 0}, - {"AttrFrameBase", Const, 0}, - {"AttrFriend", Const, 0}, - {"AttrHighpc", Const, 0}, - {"AttrIdentifierCase", Const, 0}, - {"AttrImport", Const, 0}, - {"AttrInline", Const, 0}, - {"AttrIsOptional", Const, 0}, - {"AttrLanguage", Const, 0}, - {"AttrLinkageName", Const, 14}, - {"AttrLocation", Const, 0}, - {"AttrLoclistsBase", Const, 14}, - {"AttrLowerBound", Const, 0}, - {"AttrLowpc", Const, 0}, - {"AttrMacroInfo", Const, 0}, - {"AttrMacros", Const, 14}, - {"AttrMainSubprogram", Const, 14}, - {"AttrMutable", Const, 14}, - {"AttrName", Const, 0}, - {"AttrNamelistItem", Const, 0}, - {"AttrNoreturn", Const, 14}, - {"AttrObjectPointer", Const, 14}, - {"AttrOrdering", Const, 0}, - {"AttrPictureString", Const, 14}, - {"AttrPriority", Const, 0}, - {"AttrProducer", Const, 0}, - {"AttrPrototyped", Const, 0}, - {"AttrPure", Const, 14}, - {"AttrRanges", Const, 0}, - {"AttrRank", Const, 14}, - {"AttrRecursive", Const, 14}, - {"AttrReference", Const, 14}, - {"AttrReturnAddr", Const, 0}, - {"AttrRnglistsBase", Const, 14}, - {"AttrRvalueReference", Const, 14}, - {"AttrSegment", Const, 0}, - {"AttrSibling", Const, 0}, - {"AttrSignature", Const, 14}, - {"AttrSmall", Const, 14}, - {"AttrSpecification", Const, 0}, - {"AttrStartScope", Const, 0}, - {"AttrStaticLink", Const, 0}, - {"AttrStmtList", Const, 0}, - {"AttrStrOffsetsBase", Const, 14}, - {"AttrStride", Const, 0}, - {"AttrStrideSize", Const, 0}, - {"AttrStringLength", Const, 0}, - {"AttrStringLengthBitSize", Const, 14}, - {"AttrStringLengthByteSize", Const, 14}, - {"AttrThreadsScaled", Const, 14}, - {"AttrTrampoline", Const, 0}, - {"AttrType", Const, 0}, - {"AttrUpperBound", Const, 0}, - {"AttrUseLocation", Const, 0}, - {"AttrUseUTF8", Const, 0}, - {"AttrVarParam", Const, 0}, - {"AttrVirtuality", Const, 0}, - {"AttrVisibility", Const, 0}, - {"AttrVtableElemLoc", Const, 0}, - {"BasicType", Type, 0}, - {"BasicType.BitOffset", Field, 0}, - {"BasicType.BitSize", Field, 0}, - {"BasicType.CommonType", Field, 0}, - {"BasicType.DataBitOffset", Field, 18}, - {"BoolType", Type, 0}, - {"BoolType.BasicType", Field, 0}, - {"CharType", Type, 0}, - {"CharType.BasicType", Field, 0}, - {"Class", Type, 5}, - {"ClassAddrPtr", Const, 14}, - {"ClassAddress", Const, 5}, - {"ClassBlock", Const, 5}, - {"ClassConstant", Const, 5}, - {"ClassExprLoc", Const, 5}, - {"ClassFlag", Const, 5}, - {"ClassLinePtr", Const, 5}, - {"ClassLocList", Const, 14}, - {"ClassLocListPtr", Const, 5}, - {"ClassMacPtr", Const, 5}, - {"ClassRangeListPtr", Const, 5}, - {"ClassReference", Const, 5}, - {"ClassReferenceAlt", Const, 5}, - {"ClassReferenceSig", Const, 5}, - {"ClassRngList", Const, 14}, - {"ClassRngListsPtr", Const, 14}, - {"ClassStrOffsetsPtr", Const, 14}, - {"ClassString", Const, 5}, - {"ClassStringAlt", Const, 5}, - {"ClassUnknown", Const, 6}, - {"CommonType", Type, 0}, - {"CommonType.ByteSize", Field, 0}, - {"CommonType.Name", Field, 0}, - {"ComplexType", Type, 0}, - {"ComplexType.BasicType", Field, 0}, - {"Data", Type, 0}, - {"DecodeError", Type, 0}, - {"DecodeError.Err", Field, 0}, - {"DecodeError.Name", Field, 0}, - {"DecodeError.Offset", Field, 0}, - {"DotDotDotType", Type, 0}, - {"DotDotDotType.CommonType", Field, 0}, - {"Entry", Type, 0}, - {"Entry.Children", Field, 0}, - {"Entry.Field", Field, 0}, - {"Entry.Offset", Field, 0}, - {"Entry.Tag", Field, 0}, - {"EnumType", Type, 0}, - {"EnumType.CommonType", Field, 0}, - {"EnumType.EnumName", Field, 0}, - {"EnumType.Val", Field, 0}, - {"EnumValue", Type, 0}, - {"EnumValue.Name", Field, 0}, - {"EnumValue.Val", Field, 0}, - {"ErrUnknownPC", Var, 5}, - {"Field", Type, 0}, - {"Field.Attr", Field, 0}, - {"Field.Class", Field, 5}, - {"Field.Val", Field, 0}, - {"FloatType", Type, 0}, - {"FloatType.BasicType", Field, 0}, - {"FuncType", Type, 0}, - {"FuncType.CommonType", Field, 0}, - {"FuncType.ParamType", Field, 0}, - {"FuncType.ReturnType", Field, 0}, - {"IntType", Type, 0}, - {"IntType.BasicType", Field, 0}, - {"LineEntry", Type, 5}, - {"LineEntry.Address", Field, 5}, - {"LineEntry.BasicBlock", Field, 5}, - {"LineEntry.Column", Field, 5}, - {"LineEntry.Discriminator", Field, 5}, - {"LineEntry.EndSequence", Field, 5}, - {"LineEntry.EpilogueBegin", Field, 5}, - {"LineEntry.File", Field, 5}, - {"LineEntry.ISA", Field, 5}, - {"LineEntry.IsStmt", Field, 5}, - {"LineEntry.Line", Field, 5}, - {"LineEntry.OpIndex", Field, 5}, - {"LineEntry.PrologueEnd", Field, 5}, - {"LineFile", Type, 5}, - {"LineFile.Length", Field, 5}, - {"LineFile.Mtime", Field, 5}, - {"LineFile.Name", Field, 5}, - {"LineReader", Type, 5}, - {"LineReaderPos", Type, 5}, - {"New", Func, 0}, - {"Offset", Type, 0}, - {"PtrType", Type, 0}, - {"PtrType.CommonType", Field, 0}, - {"PtrType.Type", Field, 0}, - {"QualType", Type, 0}, - {"QualType.CommonType", Field, 0}, - {"QualType.Qual", Field, 0}, - {"QualType.Type", Field, 0}, - {"Reader", Type, 0}, - {"StructField", Type, 0}, - {"StructField.BitOffset", Field, 0}, - {"StructField.BitSize", Field, 0}, - {"StructField.ByteOffset", Field, 0}, - {"StructField.ByteSize", Field, 0}, - {"StructField.DataBitOffset", Field, 18}, - {"StructField.Name", Field, 0}, - {"StructField.Type", Field, 0}, - {"StructType", Type, 0}, - {"StructType.CommonType", Field, 0}, - {"StructType.Field", Field, 0}, - {"StructType.Incomplete", Field, 0}, - {"StructType.Kind", Field, 0}, - {"StructType.StructName", Field, 0}, - {"Tag", Type, 0}, - {"TagAccessDeclaration", Const, 0}, - {"TagArrayType", Const, 0}, - {"TagAtomicType", Const, 14}, - {"TagBaseType", Const, 0}, - {"TagCallSite", Const, 14}, - {"TagCallSiteParameter", Const, 14}, - {"TagCatchDwarfBlock", Const, 0}, - {"TagClassType", Const, 0}, - {"TagCoarrayType", Const, 14}, - {"TagCommonDwarfBlock", Const, 0}, - {"TagCommonInclusion", Const, 0}, - {"TagCompileUnit", Const, 0}, - {"TagCondition", Const, 3}, - {"TagConstType", Const, 0}, - {"TagConstant", Const, 0}, - {"TagDwarfProcedure", Const, 0}, - {"TagDynamicType", Const, 14}, - {"TagEntryPoint", Const, 0}, - {"TagEnumerationType", Const, 0}, - {"TagEnumerator", Const, 0}, - {"TagFileType", Const, 0}, - {"TagFormalParameter", Const, 0}, - {"TagFriend", Const, 0}, - {"TagGenericSubrange", Const, 14}, - {"TagImmutableType", Const, 14}, - {"TagImportedDeclaration", Const, 0}, - {"TagImportedModule", Const, 0}, - {"TagImportedUnit", Const, 0}, - {"TagInheritance", Const, 0}, - {"TagInlinedSubroutine", Const, 0}, - {"TagInterfaceType", Const, 0}, - {"TagLabel", Const, 0}, - {"TagLexDwarfBlock", Const, 0}, - {"TagMember", Const, 0}, - {"TagModule", Const, 0}, - {"TagMutableType", Const, 0}, - {"TagNamelist", Const, 0}, - {"TagNamelistItem", Const, 0}, - {"TagNamespace", Const, 0}, - {"TagPackedType", Const, 0}, - {"TagPartialUnit", Const, 0}, - {"TagPointerType", Const, 0}, - {"TagPtrToMemberType", Const, 0}, - {"TagReferenceType", Const, 0}, - {"TagRestrictType", Const, 0}, - {"TagRvalueReferenceType", Const, 3}, - {"TagSetType", Const, 0}, - {"TagSharedType", Const, 3}, - {"TagSkeletonUnit", Const, 14}, - {"TagStringType", Const, 0}, - {"TagStructType", Const, 0}, - {"TagSubprogram", Const, 0}, - {"TagSubrangeType", Const, 0}, - {"TagSubroutineType", Const, 0}, - {"TagTemplateAlias", Const, 3}, - {"TagTemplateTypeParameter", Const, 0}, - {"TagTemplateValueParameter", Const, 0}, - {"TagThrownType", Const, 0}, - {"TagTryDwarfBlock", Const, 0}, - {"TagTypeUnit", Const, 3}, - {"TagTypedef", Const, 0}, - {"TagUnionType", Const, 0}, - {"TagUnspecifiedParameters", Const, 0}, - {"TagUnspecifiedType", Const, 0}, - {"TagVariable", Const, 0}, - {"TagVariant", Const, 0}, - {"TagVariantPart", Const, 0}, - {"TagVolatileType", Const, 0}, - {"TagWithStmt", Const, 0}, - {"Type", Type, 0}, - {"TypedefType", Type, 0}, - {"TypedefType.CommonType", Field, 0}, - {"TypedefType.Type", Field, 0}, - {"UcharType", Type, 0}, - {"UcharType.BasicType", Field, 0}, - {"UintType", Type, 0}, - {"UintType.BasicType", Field, 0}, - {"UnspecifiedType", Type, 4}, - {"UnspecifiedType.BasicType", Field, 4}, - {"UnsupportedType", Type, 13}, - {"UnsupportedType.CommonType", Field, 13}, - {"UnsupportedType.Tag", Field, 13}, - {"VoidType", Type, 0}, - {"VoidType.CommonType", Field, 0}, + {"(*AddrType).Basic", Method, 0, ""}, + {"(*AddrType).Common", Method, 0, ""}, + {"(*AddrType).Size", Method, 0, ""}, + {"(*AddrType).String", Method, 0, ""}, + {"(*ArrayType).Common", Method, 0, ""}, + {"(*ArrayType).Size", Method, 0, ""}, + {"(*ArrayType).String", Method, 0, ""}, + {"(*BasicType).Basic", Method, 0, ""}, + {"(*BasicType).Common", Method, 0, ""}, + {"(*BasicType).Size", Method, 0, ""}, + {"(*BasicType).String", Method, 0, ""}, + {"(*BoolType).Basic", Method, 0, ""}, + {"(*BoolType).Common", Method, 0, ""}, + {"(*BoolType).Size", Method, 0, ""}, + {"(*BoolType).String", Method, 0, ""}, + {"(*CharType).Basic", Method, 0, ""}, + {"(*CharType).Common", Method, 0, ""}, + {"(*CharType).Size", Method, 0, ""}, + {"(*CharType).String", Method, 0, ""}, + {"(*CommonType).Common", Method, 0, ""}, + {"(*CommonType).Size", Method, 0, ""}, + {"(*ComplexType).Basic", Method, 0, ""}, + {"(*ComplexType).Common", Method, 0, ""}, + {"(*ComplexType).Size", Method, 0, ""}, + {"(*ComplexType).String", Method, 0, ""}, + {"(*Data).AddSection", Method, 14, ""}, + {"(*Data).AddTypes", Method, 3, ""}, + {"(*Data).LineReader", Method, 5, ""}, + {"(*Data).Ranges", Method, 7, ""}, + {"(*Data).Reader", Method, 0, ""}, + {"(*Data).Type", Method, 0, ""}, + {"(*DotDotDotType).Common", Method, 0, ""}, + {"(*DotDotDotType).Size", Method, 0, ""}, + {"(*DotDotDotType).String", Method, 0, ""}, + {"(*Entry).AttrField", Method, 5, ""}, + {"(*Entry).Val", Method, 0, ""}, + {"(*EnumType).Common", Method, 0, ""}, + {"(*EnumType).Size", Method, 0, ""}, + {"(*EnumType).String", Method, 0, ""}, + {"(*FloatType).Basic", Method, 0, ""}, + {"(*FloatType).Common", Method, 0, ""}, + {"(*FloatType).Size", Method, 0, ""}, + {"(*FloatType).String", Method, 0, ""}, + {"(*FuncType).Common", Method, 0, ""}, + {"(*FuncType).Size", Method, 0, ""}, + {"(*FuncType).String", Method, 0, ""}, + {"(*IntType).Basic", Method, 0, ""}, + {"(*IntType).Common", Method, 0, ""}, + {"(*IntType).Size", Method, 0, ""}, + {"(*IntType).String", Method, 0, ""}, + {"(*LineReader).Files", Method, 14, ""}, + {"(*LineReader).Next", Method, 5, ""}, + {"(*LineReader).Reset", Method, 5, ""}, + {"(*LineReader).Seek", Method, 5, ""}, + {"(*LineReader).SeekPC", Method, 5, ""}, + {"(*LineReader).Tell", Method, 5, ""}, + {"(*PtrType).Common", Method, 0, ""}, + {"(*PtrType).Size", Method, 0, ""}, + {"(*PtrType).String", Method, 0, ""}, + {"(*QualType).Common", Method, 0, ""}, + {"(*QualType).Size", Method, 0, ""}, + {"(*QualType).String", Method, 0, ""}, + {"(*Reader).AddressSize", Method, 5, ""}, + {"(*Reader).ByteOrder", Method, 14, ""}, + {"(*Reader).Next", Method, 0, ""}, + {"(*Reader).Seek", Method, 0, ""}, + {"(*Reader).SeekPC", Method, 7, ""}, + {"(*Reader).SkipChildren", Method, 0, ""}, + {"(*StructType).Common", Method, 0, ""}, + {"(*StructType).Defn", Method, 0, ""}, + {"(*StructType).Size", Method, 0, ""}, + {"(*StructType).String", Method, 0, ""}, + {"(*TypedefType).Common", Method, 0, ""}, + {"(*TypedefType).Size", Method, 0, ""}, + {"(*TypedefType).String", Method, 0, ""}, + {"(*UcharType).Basic", Method, 0, ""}, + {"(*UcharType).Common", Method, 0, ""}, + {"(*UcharType).Size", Method, 0, ""}, + {"(*UcharType).String", Method, 0, ""}, + {"(*UintType).Basic", Method, 0, ""}, + {"(*UintType).Common", Method, 0, ""}, + {"(*UintType).Size", Method, 0, ""}, + {"(*UintType).String", Method, 0, ""}, + {"(*UnspecifiedType).Basic", Method, 4, ""}, + {"(*UnspecifiedType).Common", Method, 4, ""}, + {"(*UnspecifiedType).Size", Method, 4, ""}, + {"(*UnspecifiedType).String", Method, 4, ""}, + {"(*UnsupportedType).Common", Method, 13, ""}, + {"(*UnsupportedType).Size", Method, 13, ""}, + {"(*UnsupportedType).String", Method, 13, ""}, + {"(*VoidType).Common", Method, 0, ""}, + {"(*VoidType).Size", Method, 0, ""}, + {"(*VoidType).String", Method, 0, ""}, + {"(Attr).GoString", Method, 0, ""}, + {"(Attr).String", Method, 0, ""}, + {"(Class).GoString", Method, 5, ""}, + {"(Class).String", Method, 5, ""}, + {"(DecodeError).Error", Method, 0, ""}, + {"(Tag).GoString", Method, 0, ""}, + {"(Tag).String", Method, 0, ""}, + {"AddrType", Type, 0, ""}, + {"AddrType.BasicType", Field, 0, ""}, + {"ArrayType", Type, 0, ""}, + {"ArrayType.CommonType", Field, 0, ""}, + {"ArrayType.Count", Field, 0, ""}, + {"ArrayType.StrideBitSize", Field, 0, ""}, + {"ArrayType.Type", Field, 0, ""}, + {"Attr", Type, 0, ""}, + {"AttrAbstractOrigin", Const, 0, ""}, + {"AttrAccessibility", Const, 0, ""}, + {"AttrAddrBase", Const, 14, ""}, + {"AttrAddrClass", Const, 0, ""}, + {"AttrAlignment", Const, 14, ""}, + {"AttrAllocated", Const, 0, ""}, + {"AttrArtificial", Const, 0, ""}, + {"AttrAssociated", Const, 0, ""}, + {"AttrBaseTypes", Const, 0, ""}, + {"AttrBinaryScale", Const, 14, ""}, + {"AttrBitOffset", Const, 0, ""}, + {"AttrBitSize", Const, 0, ""}, + {"AttrByteSize", Const, 0, ""}, + {"AttrCallAllCalls", Const, 14, ""}, + {"AttrCallAllSourceCalls", Const, 14, ""}, + {"AttrCallAllTailCalls", Const, 14, ""}, + {"AttrCallColumn", Const, 0, ""}, + {"AttrCallDataLocation", Const, 14, ""}, + {"AttrCallDataValue", Const, 14, ""}, + {"AttrCallFile", Const, 0, ""}, + {"AttrCallLine", Const, 0, ""}, + {"AttrCallOrigin", Const, 14, ""}, + {"AttrCallPC", Const, 14, ""}, + {"AttrCallParameter", Const, 14, ""}, + {"AttrCallReturnPC", Const, 14, ""}, + {"AttrCallTailCall", Const, 14, ""}, + {"AttrCallTarget", Const, 14, ""}, + {"AttrCallTargetClobbered", Const, 14, ""}, + {"AttrCallValue", Const, 14, ""}, + {"AttrCalling", Const, 0, ""}, + {"AttrCommonRef", Const, 0, ""}, + {"AttrCompDir", Const, 0, ""}, + {"AttrConstExpr", Const, 14, ""}, + {"AttrConstValue", Const, 0, ""}, + {"AttrContainingType", Const, 0, ""}, + {"AttrCount", Const, 0, ""}, + {"AttrDataBitOffset", Const, 14, ""}, + {"AttrDataLocation", Const, 0, ""}, + {"AttrDataMemberLoc", Const, 0, ""}, + {"AttrDecimalScale", Const, 14, ""}, + {"AttrDecimalSign", Const, 14, ""}, + {"AttrDeclColumn", Const, 0, ""}, + {"AttrDeclFile", Const, 0, ""}, + {"AttrDeclLine", Const, 0, ""}, + {"AttrDeclaration", Const, 0, ""}, + {"AttrDefaultValue", Const, 0, ""}, + {"AttrDefaulted", Const, 14, ""}, + {"AttrDeleted", Const, 14, ""}, + {"AttrDescription", Const, 0, ""}, + {"AttrDigitCount", Const, 14, ""}, + {"AttrDiscr", Const, 0, ""}, + {"AttrDiscrList", Const, 0, ""}, + {"AttrDiscrValue", Const, 0, ""}, + {"AttrDwoName", Const, 14, ""}, + {"AttrElemental", Const, 14, ""}, + {"AttrEncoding", Const, 0, ""}, + {"AttrEndianity", Const, 14, ""}, + {"AttrEntrypc", Const, 0, ""}, + {"AttrEnumClass", Const, 14, ""}, + {"AttrExplicit", Const, 14, ""}, + {"AttrExportSymbols", Const, 14, ""}, + {"AttrExtension", Const, 0, ""}, + {"AttrExternal", Const, 0, ""}, + {"AttrFrameBase", Const, 0, ""}, + {"AttrFriend", Const, 0, ""}, + {"AttrHighpc", Const, 0, ""}, + {"AttrIdentifierCase", Const, 0, ""}, + {"AttrImport", Const, 0, ""}, + {"AttrInline", Const, 0, ""}, + {"AttrIsOptional", Const, 0, ""}, + {"AttrLanguage", Const, 0, ""}, + {"AttrLinkageName", Const, 14, ""}, + {"AttrLocation", Const, 0, ""}, + {"AttrLoclistsBase", Const, 14, ""}, + {"AttrLowerBound", Const, 0, ""}, + {"AttrLowpc", Const, 0, ""}, + {"AttrMacroInfo", Const, 0, ""}, + {"AttrMacros", Const, 14, ""}, + {"AttrMainSubprogram", Const, 14, ""}, + {"AttrMutable", Const, 14, ""}, + {"AttrName", Const, 0, ""}, + {"AttrNamelistItem", Const, 0, ""}, + {"AttrNoreturn", Const, 14, ""}, + {"AttrObjectPointer", Const, 14, ""}, + {"AttrOrdering", Const, 0, ""}, + {"AttrPictureString", Const, 14, ""}, + {"AttrPriority", Const, 0, ""}, + {"AttrProducer", Const, 0, ""}, + {"AttrPrototyped", Const, 0, ""}, + {"AttrPure", Const, 14, ""}, + {"AttrRanges", Const, 0, ""}, + {"AttrRank", Const, 14, ""}, + {"AttrRecursive", Const, 14, ""}, + {"AttrReference", Const, 14, ""}, + {"AttrReturnAddr", Const, 0, ""}, + {"AttrRnglistsBase", Const, 14, ""}, + {"AttrRvalueReference", Const, 14, ""}, + {"AttrSegment", Const, 0, ""}, + {"AttrSibling", Const, 0, ""}, + {"AttrSignature", Const, 14, ""}, + {"AttrSmall", Const, 14, ""}, + {"AttrSpecification", Const, 0, ""}, + {"AttrStartScope", Const, 0, ""}, + {"AttrStaticLink", Const, 0, ""}, + {"AttrStmtList", Const, 0, ""}, + {"AttrStrOffsetsBase", Const, 14, ""}, + {"AttrStride", Const, 0, ""}, + {"AttrStrideSize", Const, 0, ""}, + {"AttrStringLength", Const, 0, ""}, + {"AttrStringLengthBitSize", Const, 14, ""}, + {"AttrStringLengthByteSize", Const, 14, ""}, + {"AttrThreadsScaled", Const, 14, ""}, + {"AttrTrampoline", Const, 0, ""}, + {"AttrType", Const, 0, ""}, + {"AttrUpperBound", Const, 0, ""}, + {"AttrUseLocation", Const, 0, ""}, + {"AttrUseUTF8", Const, 0, ""}, + {"AttrVarParam", Const, 0, ""}, + {"AttrVirtuality", Const, 0, ""}, + {"AttrVisibility", Const, 0, ""}, + {"AttrVtableElemLoc", Const, 0, ""}, + {"BasicType", Type, 0, ""}, + {"BasicType.BitOffset", Field, 0, ""}, + {"BasicType.BitSize", Field, 0, ""}, + {"BasicType.CommonType", Field, 0, ""}, + {"BasicType.DataBitOffset", Field, 18, ""}, + {"BoolType", Type, 0, ""}, + {"BoolType.BasicType", Field, 0, ""}, + {"CharType", Type, 0, ""}, + {"CharType.BasicType", Field, 0, ""}, + {"Class", Type, 5, ""}, + {"ClassAddrPtr", Const, 14, ""}, + {"ClassAddress", Const, 5, ""}, + {"ClassBlock", Const, 5, ""}, + {"ClassConstant", Const, 5, ""}, + {"ClassExprLoc", Const, 5, ""}, + {"ClassFlag", Const, 5, ""}, + {"ClassLinePtr", Const, 5, ""}, + {"ClassLocList", Const, 14, ""}, + {"ClassLocListPtr", Const, 5, ""}, + {"ClassMacPtr", Const, 5, ""}, + {"ClassRangeListPtr", Const, 5, ""}, + {"ClassReference", Const, 5, ""}, + {"ClassReferenceAlt", Const, 5, ""}, + {"ClassReferenceSig", Const, 5, ""}, + {"ClassRngList", Const, 14, ""}, + {"ClassRngListsPtr", Const, 14, ""}, + {"ClassStrOffsetsPtr", Const, 14, ""}, + {"ClassString", Const, 5, ""}, + {"ClassStringAlt", Const, 5, ""}, + {"ClassUnknown", Const, 6, ""}, + {"CommonType", Type, 0, ""}, + {"CommonType.ByteSize", Field, 0, ""}, + {"CommonType.Name", Field, 0, ""}, + {"ComplexType", Type, 0, ""}, + {"ComplexType.BasicType", Field, 0, ""}, + {"Data", Type, 0, ""}, + {"DecodeError", Type, 0, ""}, + {"DecodeError.Err", Field, 0, ""}, + {"DecodeError.Name", Field, 0, ""}, + {"DecodeError.Offset", Field, 0, ""}, + {"DotDotDotType", Type, 0, ""}, + {"DotDotDotType.CommonType", Field, 0, ""}, + {"Entry", Type, 0, ""}, + {"Entry.Children", Field, 0, ""}, + {"Entry.Field", Field, 0, ""}, + {"Entry.Offset", Field, 0, ""}, + {"Entry.Tag", Field, 0, ""}, + {"EnumType", Type, 0, ""}, + {"EnumType.CommonType", Field, 0, ""}, + {"EnumType.EnumName", Field, 0, ""}, + {"EnumType.Val", Field, 0, ""}, + {"EnumValue", Type, 0, ""}, + {"EnumValue.Name", Field, 0, ""}, + {"EnumValue.Val", Field, 0, ""}, + {"ErrUnknownPC", Var, 5, ""}, + {"Field", Type, 0, ""}, + {"Field.Attr", Field, 0, ""}, + {"Field.Class", Field, 5, ""}, + {"Field.Val", Field, 0, ""}, + {"FloatType", Type, 0, ""}, + {"FloatType.BasicType", Field, 0, ""}, + {"FuncType", Type, 0, ""}, + {"FuncType.CommonType", Field, 0, ""}, + {"FuncType.ParamType", Field, 0, ""}, + {"FuncType.ReturnType", Field, 0, ""}, + {"IntType", Type, 0, ""}, + {"IntType.BasicType", Field, 0, ""}, + {"LineEntry", Type, 5, ""}, + {"LineEntry.Address", Field, 5, ""}, + {"LineEntry.BasicBlock", Field, 5, ""}, + {"LineEntry.Column", Field, 5, ""}, + {"LineEntry.Discriminator", Field, 5, ""}, + {"LineEntry.EndSequence", Field, 5, ""}, + {"LineEntry.EpilogueBegin", Field, 5, ""}, + {"LineEntry.File", Field, 5, ""}, + {"LineEntry.ISA", Field, 5, ""}, + {"LineEntry.IsStmt", Field, 5, ""}, + {"LineEntry.Line", Field, 5, ""}, + {"LineEntry.OpIndex", Field, 5, ""}, + {"LineEntry.PrologueEnd", Field, 5, ""}, + {"LineFile", Type, 5, ""}, + {"LineFile.Length", Field, 5, ""}, + {"LineFile.Mtime", Field, 5, ""}, + {"LineFile.Name", Field, 5, ""}, + {"LineReader", Type, 5, ""}, + {"LineReaderPos", Type, 5, ""}, + {"New", Func, 0, "func(abbrev []byte, aranges []byte, frame []byte, info []byte, line []byte, pubnames []byte, ranges []byte, str []byte) (*Data, error)"}, + {"Offset", Type, 0, ""}, + {"PtrType", Type, 0, ""}, + {"PtrType.CommonType", Field, 0, ""}, + {"PtrType.Type", Field, 0, ""}, + {"QualType", Type, 0, ""}, + {"QualType.CommonType", Field, 0, ""}, + {"QualType.Qual", Field, 0, ""}, + {"QualType.Type", Field, 0, ""}, + {"Reader", Type, 0, ""}, + {"StructField", Type, 0, ""}, + {"StructField.BitOffset", Field, 0, ""}, + {"StructField.BitSize", Field, 0, ""}, + {"StructField.ByteOffset", Field, 0, ""}, + {"StructField.ByteSize", Field, 0, ""}, + {"StructField.DataBitOffset", Field, 18, ""}, + {"StructField.Name", Field, 0, ""}, + {"StructField.Type", Field, 0, ""}, + {"StructType", Type, 0, ""}, + {"StructType.CommonType", Field, 0, ""}, + {"StructType.Field", Field, 0, ""}, + {"StructType.Incomplete", Field, 0, ""}, + {"StructType.Kind", Field, 0, ""}, + {"StructType.StructName", Field, 0, ""}, + {"Tag", Type, 0, ""}, + {"TagAccessDeclaration", Const, 0, ""}, + {"TagArrayType", Const, 0, ""}, + {"TagAtomicType", Const, 14, ""}, + {"TagBaseType", Const, 0, ""}, + {"TagCallSite", Const, 14, ""}, + {"TagCallSiteParameter", Const, 14, ""}, + {"TagCatchDwarfBlock", Const, 0, ""}, + {"TagClassType", Const, 0, ""}, + {"TagCoarrayType", Const, 14, ""}, + {"TagCommonDwarfBlock", Const, 0, ""}, + {"TagCommonInclusion", Const, 0, ""}, + {"TagCompileUnit", Const, 0, ""}, + {"TagCondition", Const, 3, ""}, + {"TagConstType", Const, 0, ""}, + {"TagConstant", Const, 0, ""}, + {"TagDwarfProcedure", Const, 0, ""}, + {"TagDynamicType", Const, 14, ""}, + {"TagEntryPoint", Const, 0, ""}, + {"TagEnumerationType", Const, 0, ""}, + {"TagEnumerator", Const, 0, ""}, + {"TagFileType", Const, 0, ""}, + {"TagFormalParameter", Const, 0, ""}, + {"TagFriend", Const, 0, ""}, + {"TagGenericSubrange", Const, 14, ""}, + {"TagImmutableType", Const, 14, ""}, + {"TagImportedDeclaration", Const, 0, ""}, + {"TagImportedModule", Const, 0, ""}, + {"TagImportedUnit", Const, 0, ""}, + {"TagInheritance", Const, 0, ""}, + {"TagInlinedSubroutine", Const, 0, ""}, + {"TagInterfaceType", Const, 0, ""}, + {"TagLabel", Const, 0, ""}, + {"TagLexDwarfBlock", Const, 0, ""}, + {"TagMember", Const, 0, ""}, + {"TagModule", Const, 0, ""}, + {"TagMutableType", Const, 0, ""}, + {"TagNamelist", Const, 0, ""}, + {"TagNamelistItem", Const, 0, ""}, + {"TagNamespace", Const, 0, ""}, + {"TagPackedType", Const, 0, ""}, + {"TagPartialUnit", Const, 0, ""}, + {"TagPointerType", Const, 0, ""}, + {"TagPtrToMemberType", Const, 0, ""}, + {"TagReferenceType", Const, 0, ""}, + {"TagRestrictType", Const, 0, ""}, + {"TagRvalueReferenceType", Const, 3, ""}, + {"TagSetType", Const, 0, ""}, + {"TagSharedType", Const, 3, ""}, + {"TagSkeletonUnit", Const, 14, ""}, + {"TagStringType", Const, 0, ""}, + {"TagStructType", Const, 0, ""}, + {"TagSubprogram", Const, 0, ""}, + {"TagSubrangeType", Const, 0, ""}, + {"TagSubroutineType", Const, 0, ""}, + {"TagTemplateAlias", Const, 3, ""}, + {"TagTemplateTypeParameter", Const, 0, ""}, + {"TagTemplateValueParameter", Const, 0, ""}, + {"TagThrownType", Const, 0, ""}, + {"TagTryDwarfBlock", Const, 0, ""}, + {"TagTypeUnit", Const, 3, ""}, + {"TagTypedef", Const, 0, ""}, + {"TagUnionType", Const, 0, ""}, + {"TagUnspecifiedParameters", Const, 0, ""}, + {"TagUnspecifiedType", Const, 0, ""}, + {"TagVariable", Const, 0, ""}, + {"TagVariant", Const, 0, ""}, + {"TagVariantPart", Const, 0, ""}, + {"TagVolatileType", Const, 0, ""}, + {"TagWithStmt", Const, 0, ""}, + {"Type", Type, 0, ""}, + {"TypedefType", Type, 0, ""}, + {"TypedefType.CommonType", Field, 0, ""}, + {"TypedefType.Type", Field, 0, ""}, + {"UcharType", Type, 0, ""}, + {"UcharType.BasicType", Field, 0, ""}, + {"UintType", Type, 0, ""}, + {"UintType.BasicType", Field, 0, ""}, + {"UnspecifiedType", Type, 4, ""}, + {"UnspecifiedType.BasicType", Field, 4, ""}, + {"UnsupportedType", Type, 13, ""}, + {"UnsupportedType.CommonType", Field, 13, ""}, + {"UnsupportedType.Tag", Field, 13, ""}, + {"VoidType", Type, 0, ""}, + {"VoidType.CommonType", Field, 0, ""}, }, "debug/elf": { - {"(*File).Close", Method, 0}, - {"(*File).DWARF", Method, 0}, - {"(*File).DynString", Method, 1}, - {"(*File).DynValue", Method, 21}, - {"(*File).DynamicSymbols", Method, 4}, - {"(*File).DynamicVersionNeeds", Method, 24}, - {"(*File).DynamicVersions", Method, 24}, - {"(*File).ImportedLibraries", Method, 0}, - {"(*File).ImportedSymbols", Method, 0}, - {"(*File).Section", Method, 0}, - {"(*File).SectionByType", Method, 0}, - {"(*File).Symbols", Method, 0}, - {"(*FormatError).Error", Method, 0}, - {"(*Prog).Open", Method, 0}, - {"(*Section).Data", Method, 0}, - {"(*Section).Open", Method, 0}, - {"(Class).GoString", Method, 0}, - {"(Class).String", Method, 0}, - {"(CompressionType).GoString", Method, 6}, - {"(CompressionType).String", Method, 6}, - {"(Data).GoString", Method, 0}, - {"(Data).String", Method, 0}, - {"(DynFlag).GoString", Method, 0}, - {"(DynFlag).String", Method, 0}, - {"(DynFlag1).GoString", Method, 21}, - {"(DynFlag1).String", Method, 21}, - {"(DynTag).GoString", Method, 0}, - {"(DynTag).String", Method, 0}, - {"(Machine).GoString", Method, 0}, - {"(Machine).String", Method, 0}, - {"(NType).GoString", Method, 0}, - {"(NType).String", Method, 0}, - {"(OSABI).GoString", Method, 0}, - {"(OSABI).String", Method, 0}, - {"(Prog).ReadAt", Method, 0}, - {"(ProgFlag).GoString", Method, 0}, - {"(ProgFlag).String", Method, 0}, - {"(ProgType).GoString", Method, 0}, - {"(ProgType).String", Method, 0}, - {"(R_386).GoString", Method, 0}, - {"(R_386).String", Method, 0}, - {"(R_390).GoString", Method, 7}, - {"(R_390).String", Method, 7}, - {"(R_AARCH64).GoString", Method, 4}, - {"(R_AARCH64).String", Method, 4}, - {"(R_ALPHA).GoString", Method, 0}, - {"(R_ALPHA).String", Method, 0}, - {"(R_ARM).GoString", Method, 0}, - {"(R_ARM).String", Method, 0}, - {"(R_LARCH).GoString", Method, 19}, - {"(R_LARCH).String", Method, 19}, - {"(R_MIPS).GoString", Method, 6}, - {"(R_MIPS).String", Method, 6}, - {"(R_PPC).GoString", Method, 0}, - {"(R_PPC).String", Method, 0}, - {"(R_PPC64).GoString", Method, 5}, - {"(R_PPC64).String", Method, 5}, - {"(R_RISCV).GoString", Method, 11}, - {"(R_RISCV).String", Method, 11}, - {"(R_SPARC).GoString", Method, 0}, - {"(R_SPARC).String", Method, 0}, - {"(R_X86_64).GoString", Method, 0}, - {"(R_X86_64).String", Method, 0}, - {"(Section).ReadAt", Method, 0}, - {"(SectionFlag).GoString", Method, 0}, - {"(SectionFlag).String", Method, 0}, - {"(SectionIndex).GoString", Method, 0}, - {"(SectionIndex).String", Method, 0}, - {"(SectionType).GoString", Method, 0}, - {"(SectionType).String", Method, 0}, - {"(SymBind).GoString", Method, 0}, - {"(SymBind).String", Method, 0}, - {"(SymType).GoString", Method, 0}, - {"(SymType).String", Method, 0}, - {"(SymVis).GoString", Method, 0}, - {"(SymVis).String", Method, 0}, - {"(Type).GoString", Method, 0}, - {"(Type).String", Method, 0}, - {"(Version).GoString", Method, 0}, - {"(Version).String", Method, 0}, - {"(VersionIndex).Index", Method, 24}, - {"(VersionIndex).IsHidden", Method, 24}, - {"ARM_MAGIC_TRAMP_NUMBER", Const, 0}, - {"COMPRESS_HIOS", Const, 6}, - {"COMPRESS_HIPROC", Const, 6}, - {"COMPRESS_LOOS", Const, 6}, - {"COMPRESS_LOPROC", Const, 6}, - {"COMPRESS_ZLIB", Const, 6}, - {"COMPRESS_ZSTD", Const, 21}, - {"Chdr32", Type, 6}, - {"Chdr32.Addralign", Field, 6}, - {"Chdr32.Size", Field, 6}, - {"Chdr32.Type", Field, 6}, - {"Chdr64", Type, 6}, - {"Chdr64.Addralign", Field, 6}, - {"Chdr64.Size", Field, 6}, - {"Chdr64.Type", Field, 6}, - {"Class", Type, 0}, - {"CompressionType", Type, 6}, - {"DF_1_CONFALT", Const, 21}, - {"DF_1_DIRECT", Const, 21}, - {"DF_1_DISPRELDNE", Const, 21}, - {"DF_1_DISPRELPND", Const, 21}, - {"DF_1_EDITED", Const, 21}, - {"DF_1_ENDFILTEE", Const, 21}, - {"DF_1_GLOBAL", Const, 21}, - {"DF_1_GLOBAUDIT", Const, 21}, - {"DF_1_GROUP", Const, 21}, - {"DF_1_IGNMULDEF", Const, 21}, - {"DF_1_INITFIRST", Const, 21}, - {"DF_1_INTERPOSE", Const, 21}, - {"DF_1_KMOD", Const, 21}, - {"DF_1_LOADFLTR", Const, 21}, - {"DF_1_NOCOMMON", Const, 21}, - {"DF_1_NODEFLIB", Const, 21}, - {"DF_1_NODELETE", Const, 21}, - {"DF_1_NODIRECT", Const, 21}, - {"DF_1_NODUMP", Const, 21}, - {"DF_1_NOHDR", Const, 21}, - {"DF_1_NOKSYMS", Const, 21}, - {"DF_1_NOOPEN", Const, 21}, - {"DF_1_NORELOC", Const, 21}, - {"DF_1_NOW", Const, 21}, - {"DF_1_ORIGIN", Const, 21}, - {"DF_1_PIE", Const, 21}, - {"DF_1_SINGLETON", Const, 21}, - {"DF_1_STUB", Const, 21}, - {"DF_1_SYMINTPOSE", Const, 21}, - {"DF_1_TRANS", Const, 21}, - {"DF_1_WEAKFILTER", Const, 21}, - {"DF_BIND_NOW", Const, 0}, - {"DF_ORIGIN", Const, 0}, - {"DF_STATIC_TLS", Const, 0}, - {"DF_SYMBOLIC", Const, 0}, - {"DF_TEXTREL", Const, 0}, - {"DT_ADDRRNGHI", Const, 16}, - {"DT_ADDRRNGLO", Const, 16}, - {"DT_AUDIT", Const, 16}, - {"DT_AUXILIARY", Const, 16}, - {"DT_BIND_NOW", Const, 0}, - {"DT_CHECKSUM", Const, 16}, - {"DT_CONFIG", Const, 16}, - {"DT_DEBUG", Const, 0}, - {"DT_DEPAUDIT", Const, 16}, - {"DT_ENCODING", Const, 0}, - {"DT_FEATURE", Const, 16}, - {"DT_FILTER", Const, 16}, - {"DT_FINI", Const, 0}, - {"DT_FINI_ARRAY", Const, 0}, - {"DT_FINI_ARRAYSZ", Const, 0}, - {"DT_FLAGS", Const, 0}, - {"DT_FLAGS_1", Const, 16}, - {"DT_GNU_CONFLICT", Const, 16}, - {"DT_GNU_CONFLICTSZ", Const, 16}, - {"DT_GNU_HASH", Const, 16}, - {"DT_GNU_LIBLIST", Const, 16}, - {"DT_GNU_LIBLISTSZ", Const, 16}, - {"DT_GNU_PRELINKED", Const, 16}, - {"DT_HASH", Const, 0}, - {"DT_HIOS", Const, 0}, - {"DT_HIPROC", Const, 0}, - {"DT_INIT", Const, 0}, - {"DT_INIT_ARRAY", Const, 0}, - {"DT_INIT_ARRAYSZ", Const, 0}, - {"DT_JMPREL", Const, 0}, - {"DT_LOOS", Const, 0}, - {"DT_LOPROC", Const, 0}, - {"DT_MIPS_AUX_DYNAMIC", Const, 16}, - {"DT_MIPS_BASE_ADDRESS", Const, 16}, - {"DT_MIPS_COMPACT_SIZE", Const, 16}, - {"DT_MIPS_CONFLICT", Const, 16}, - {"DT_MIPS_CONFLICTNO", Const, 16}, - {"DT_MIPS_CXX_FLAGS", Const, 16}, - {"DT_MIPS_DELTA_CLASS", Const, 16}, - {"DT_MIPS_DELTA_CLASSSYM", Const, 16}, - {"DT_MIPS_DELTA_CLASSSYM_NO", Const, 16}, - {"DT_MIPS_DELTA_CLASS_NO", Const, 16}, - {"DT_MIPS_DELTA_INSTANCE", Const, 16}, - {"DT_MIPS_DELTA_INSTANCE_NO", Const, 16}, - {"DT_MIPS_DELTA_RELOC", Const, 16}, - {"DT_MIPS_DELTA_RELOC_NO", Const, 16}, - {"DT_MIPS_DELTA_SYM", Const, 16}, - {"DT_MIPS_DELTA_SYM_NO", Const, 16}, - {"DT_MIPS_DYNSTR_ALIGN", Const, 16}, - {"DT_MIPS_FLAGS", Const, 16}, - {"DT_MIPS_GOTSYM", Const, 16}, - {"DT_MIPS_GP_VALUE", Const, 16}, - {"DT_MIPS_HIDDEN_GOTIDX", Const, 16}, - {"DT_MIPS_HIPAGENO", Const, 16}, - {"DT_MIPS_ICHECKSUM", Const, 16}, - {"DT_MIPS_INTERFACE", Const, 16}, - {"DT_MIPS_INTERFACE_SIZE", Const, 16}, - {"DT_MIPS_IVERSION", Const, 16}, - {"DT_MIPS_LIBLIST", Const, 16}, - {"DT_MIPS_LIBLISTNO", Const, 16}, - {"DT_MIPS_LOCALPAGE_GOTIDX", Const, 16}, - {"DT_MIPS_LOCAL_GOTIDX", Const, 16}, - {"DT_MIPS_LOCAL_GOTNO", Const, 16}, - {"DT_MIPS_MSYM", Const, 16}, - {"DT_MIPS_OPTIONS", Const, 16}, - {"DT_MIPS_PERF_SUFFIX", Const, 16}, - {"DT_MIPS_PIXIE_INIT", Const, 16}, - {"DT_MIPS_PLTGOT", Const, 16}, - {"DT_MIPS_PROTECTED_GOTIDX", Const, 16}, - {"DT_MIPS_RLD_MAP", Const, 16}, - {"DT_MIPS_RLD_MAP_REL", Const, 16}, - {"DT_MIPS_RLD_TEXT_RESOLVE_ADDR", Const, 16}, - {"DT_MIPS_RLD_VERSION", Const, 16}, - {"DT_MIPS_RWPLT", Const, 16}, - {"DT_MIPS_SYMBOL_LIB", Const, 16}, - {"DT_MIPS_SYMTABNO", Const, 16}, - {"DT_MIPS_TIME_STAMP", Const, 16}, - {"DT_MIPS_UNREFEXTNO", Const, 16}, - {"DT_MOVEENT", Const, 16}, - {"DT_MOVESZ", Const, 16}, - {"DT_MOVETAB", Const, 16}, - {"DT_NEEDED", Const, 0}, - {"DT_NULL", Const, 0}, - {"DT_PLTGOT", Const, 0}, - {"DT_PLTPAD", Const, 16}, - {"DT_PLTPADSZ", Const, 16}, - {"DT_PLTREL", Const, 0}, - {"DT_PLTRELSZ", Const, 0}, - {"DT_POSFLAG_1", Const, 16}, - {"DT_PPC64_GLINK", Const, 16}, - {"DT_PPC64_OPD", Const, 16}, - {"DT_PPC64_OPDSZ", Const, 16}, - {"DT_PPC64_OPT", Const, 16}, - {"DT_PPC_GOT", Const, 16}, - {"DT_PPC_OPT", Const, 16}, - {"DT_PREINIT_ARRAY", Const, 0}, - {"DT_PREINIT_ARRAYSZ", Const, 0}, - {"DT_REL", Const, 0}, - {"DT_RELA", Const, 0}, - {"DT_RELACOUNT", Const, 16}, - {"DT_RELAENT", Const, 0}, - {"DT_RELASZ", Const, 0}, - {"DT_RELCOUNT", Const, 16}, - {"DT_RELENT", Const, 0}, - {"DT_RELSZ", Const, 0}, - {"DT_RPATH", Const, 0}, - {"DT_RUNPATH", Const, 0}, - {"DT_SONAME", Const, 0}, - {"DT_SPARC_REGISTER", Const, 16}, - {"DT_STRSZ", Const, 0}, - {"DT_STRTAB", Const, 0}, - {"DT_SYMBOLIC", Const, 0}, - {"DT_SYMENT", Const, 0}, - {"DT_SYMINENT", Const, 16}, - {"DT_SYMINFO", Const, 16}, - {"DT_SYMINSZ", Const, 16}, - {"DT_SYMTAB", Const, 0}, - {"DT_SYMTAB_SHNDX", Const, 16}, - {"DT_TEXTREL", Const, 0}, - {"DT_TLSDESC_GOT", Const, 16}, - {"DT_TLSDESC_PLT", Const, 16}, - {"DT_USED", Const, 16}, - {"DT_VALRNGHI", Const, 16}, - {"DT_VALRNGLO", Const, 16}, - {"DT_VERDEF", Const, 16}, - {"DT_VERDEFNUM", Const, 16}, - {"DT_VERNEED", Const, 0}, - {"DT_VERNEEDNUM", Const, 0}, - {"DT_VERSYM", Const, 0}, - {"Data", Type, 0}, - {"Dyn32", Type, 0}, - {"Dyn32.Tag", Field, 0}, - {"Dyn32.Val", Field, 0}, - {"Dyn64", Type, 0}, - {"Dyn64.Tag", Field, 0}, - {"Dyn64.Val", Field, 0}, - {"DynFlag", Type, 0}, - {"DynFlag1", Type, 21}, - {"DynTag", Type, 0}, - {"DynamicVersion", Type, 24}, - {"DynamicVersion.Deps", Field, 24}, - {"DynamicVersion.Flags", Field, 24}, - {"DynamicVersion.Index", Field, 24}, - {"DynamicVersion.Name", Field, 24}, - {"DynamicVersionDep", Type, 24}, - {"DynamicVersionDep.Dep", Field, 24}, - {"DynamicVersionDep.Flags", Field, 24}, - {"DynamicVersionDep.Index", Field, 24}, - {"DynamicVersionFlag", Type, 24}, - {"DynamicVersionNeed", Type, 24}, - {"DynamicVersionNeed.Name", Field, 24}, - {"DynamicVersionNeed.Needs", Field, 24}, - {"EI_ABIVERSION", Const, 0}, - {"EI_CLASS", Const, 0}, - {"EI_DATA", Const, 0}, - {"EI_NIDENT", Const, 0}, - {"EI_OSABI", Const, 0}, - {"EI_PAD", Const, 0}, - {"EI_VERSION", Const, 0}, - {"ELFCLASS32", Const, 0}, - {"ELFCLASS64", Const, 0}, - {"ELFCLASSNONE", Const, 0}, - {"ELFDATA2LSB", Const, 0}, - {"ELFDATA2MSB", Const, 0}, - {"ELFDATANONE", Const, 0}, - {"ELFMAG", Const, 0}, - {"ELFOSABI_86OPEN", Const, 0}, - {"ELFOSABI_AIX", Const, 0}, - {"ELFOSABI_ARM", Const, 0}, - {"ELFOSABI_AROS", Const, 11}, - {"ELFOSABI_CLOUDABI", Const, 11}, - {"ELFOSABI_FENIXOS", Const, 11}, - {"ELFOSABI_FREEBSD", Const, 0}, - {"ELFOSABI_HPUX", Const, 0}, - {"ELFOSABI_HURD", Const, 0}, - {"ELFOSABI_IRIX", Const, 0}, - {"ELFOSABI_LINUX", Const, 0}, - {"ELFOSABI_MODESTO", Const, 0}, - {"ELFOSABI_NETBSD", Const, 0}, - {"ELFOSABI_NONE", Const, 0}, - {"ELFOSABI_NSK", Const, 0}, - {"ELFOSABI_OPENBSD", Const, 0}, - {"ELFOSABI_OPENVMS", Const, 0}, - {"ELFOSABI_SOLARIS", Const, 0}, - {"ELFOSABI_STANDALONE", Const, 0}, - {"ELFOSABI_TRU64", Const, 0}, - {"EM_386", Const, 0}, - {"EM_486", Const, 0}, - {"EM_56800EX", Const, 11}, - {"EM_68HC05", Const, 11}, - {"EM_68HC08", Const, 11}, - {"EM_68HC11", Const, 11}, - {"EM_68HC12", Const, 0}, - {"EM_68HC16", Const, 11}, - {"EM_68K", Const, 0}, - {"EM_78KOR", Const, 11}, - {"EM_8051", Const, 11}, - {"EM_860", Const, 0}, - {"EM_88K", Const, 0}, - {"EM_960", Const, 0}, - {"EM_AARCH64", Const, 4}, - {"EM_ALPHA", Const, 0}, - {"EM_ALPHA_STD", Const, 0}, - {"EM_ALTERA_NIOS2", Const, 11}, - {"EM_AMDGPU", Const, 11}, - {"EM_ARC", Const, 0}, - {"EM_ARCA", Const, 11}, - {"EM_ARC_COMPACT", Const, 11}, - {"EM_ARC_COMPACT2", Const, 11}, - {"EM_ARM", Const, 0}, - {"EM_AVR", Const, 11}, - {"EM_AVR32", Const, 11}, - {"EM_BA1", Const, 11}, - {"EM_BA2", Const, 11}, - {"EM_BLACKFIN", Const, 11}, - {"EM_BPF", Const, 11}, - {"EM_C166", Const, 11}, - {"EM_CDP", Const, 11}, - {"EM_CE", Const, 11}, - {"EM_CLOUDSHIELD", Const, 11}, - {"EM_COGE", Const, 11}, - {"EM_COLDFIRE", Const, 0}, - {"EM_COOL", Const, 11}, - {"EM_COREA_1ST", Const, 11}, - {"EM_COREA_2ND", Const, 11}, - {"EM_CR", Const, 11}, - {"EM_CR16", Const, 11}, - {"EM_CRAYNV2", Const, 11}, - {"EM_CRIS", Const, 11}, - {"EM_CRX", Const, 11}, - {"EM_CSR_KALIMBA", Const, 11}, - {"EM_CUDA", Const, 11}, - {"EM_CYPRESS_M8C", Const, 11}, - {"EM_D10V", Const, 11}, - {"EM_D30V", Const, 11}, - {"EM_DSP24", Const, 11}, - {"EM_DSPIC30F", Const, 11}, - {"EM_DXP", Const, 11}, - {"EM_ECOG1", Const, 11}, - {"EM_ECOG16", Const, 11}, - {"EM_ECOG1X", Const, 11}, - {"EM_ECOG2", Const, 11}, - {"EM_ETPU", Const, 11}, - {"EM_EXCESS", Const, 11}, - {"EM_F2MC16", Const, 11}, - {"EM_FIREPATH", Const, 11}, - {"EM_FR20", Const, 0}, - {"EM_FR30", Const, 11}, - {"EM_FT32", Const, 11}, - {"EM_FX66", Const, 11}, - {"EM_H8S", Const, 0}, - {"EM_H8_300", Const, 0}, - {"EM_H8_300H", Const, 0}, - {"EM_H8_500", Const, 0}, - {"EM_HUANY", Const, 11}, - {"EM_IA_64", Const, 0}, - {"EM_INTEL205", Const, 11}, - {"EM_INTEL206", Const, 11}, - {"EM_INTEL207", Const, 11}, - {"EM_INTEL208", Const, 11}, - {"EM_INTEL209", Const, 11}, - {"EM_IP2K", Const, 11}, - {"EM_JAVELIN", Const, 11}, - {"EM_K10M", Const, 11}, - {"EM_KM32", Const, 11}, - {"EM_KMX16", Const, 11}, - {"EM_KMX32", Const, 11}, - {"EM_KMX8", Const, 11}, - {"EM_KVARC", Const, 11}, - {"EM_L10M", Const, 11}, - {"EM_LANAI", Const, 11}, - {"EM_LATTICEMICO32", Const, 11}, - {"EM_LOONGARCH", Const, 19}, - {"EM_M16C", Const, 11}, - {"EM_M32", Const, 0}, - {"EM_M32C", Const, 11}, - {"EM_M32R", Const, 11}, - {"EM_MANIK", Const, 11}, - {"EM_MAX", Const, 11}, - {"EM_MAXQ30", Const, 11}, - {"EM_MCHP_PIC", Const, 11}, - {"EM_MCST_ELBRUS", Const, 11}, - {"EM_ME16", Const, 0}, - {"EM_METAG", Const, 11}, - {"EM_MICROBLAZE", Const, 11}, - {"EM_MIPS", Const, 0}, - {"EM_MIPS_RS3_LE", Const, 0}, - {"EM_MIPS_RS4_BE", Const, 0}, - {"EM_MIPS_X", Const, 0}, - {"EM_MMA", Const, 0}, - {"EM_MMDSP_PLUS", Const, 11}, - {"EM_MMIX", Const, 11}, - {"EM_MN10200", Const, 11}, - {"EM_MN10300", Const, 11}, - {"EM_MOXIE", Const, 11}, - {"EM_MSP430", Const, 11}, - {"EM_NCPU", Const, 0}, - {"EM_NDR1", Const, 0}, - {"EM_NDS32", Const, 11}, - {"EM_NONE", Const, 0}, - {"EM_NORC", Const, 11}, - {"EM_NS32K", Const, 11}, - {"EM_OPEN8", Const, 11}, - {"EM_OPENRISC", Const, 11}, - {"EM_PARISC", Const, 0}, - {"EM_PCP", Const, 0}, - {"EM_PDP10", Const, 11}, - {"EM_PDP11", Const, 11}, - {"EM_PDSP", Const, 11}, - {"EM_PJ", Const, 11}, - {"EM_PPC", Const, 0}, - {"EM_PPC64", Const, 0}, - {"EM_PRISM", Const, 11}, - {"EM_QDSP6", Const, 11}, - {"EM_R32C", Const, 11}, - {"EM_RCE", Const, 0}, - {"EM_RH32", Const, 0}, - {"EM_RISCV", Const, 11}, - {"EM_RL78", Const, 11}, - {"EM_RS08", Const, 11}, - {"EM_RX", Const, 11}, - {"EM_S370", Const, 0}, - {"EM_S390", Const, 0}, - {"EM_SCORE7", Const, 11}, - {"EM_SEP", Const, 11}, - {"EM_SE_C17", Const, 11}, - {"EM_SE_C33", Const, 11}, - {"EM_SH", Const, 0}, - {"EM_SHARC", Const, 11}, - {"EM_SLE9X", Const, 11}, - {"EM_SNP1K", Const, 11}, - {"EM_SPARC", Const, 0}, - {"EM_SPARC32PLUS", Const, 0}, - {"EM_SPARCV9", Const, 0}, - {"EM_ST100", Const, 0}, - {"EM_ST19", Const, 11}, - {"EM_ST200", Const, 11}, - {"EM_ST7", Const, 11}, - {"EM_ST9PLUS", Const, 11}, - {"EM_STARCORE", Const, 0}, - {"EM_STM8", Const, 11}, - {"EM_STXP7X", Const, 11}, - {"EM_SVX", Const, 11}, - {"EM_TILE64", Const, 11}, - {"EM_TILEGX", Const, 11}, - {"EM_TILEPRO", Const, 11}, - {"EM_TINYJ", Const, 0}, - {"EM_TI_ARP32", Const, 11}, - {"EM_TI_C2000", Const, 11}, - {"EM_TI_C5500", Const, 11}, - {"EM_TI_C6000", Const, 11}, - {"EM_TI_PRU", Const, 11}, - {"EM_TMM_GPP", Const, 11}, - {"EM_TPC", Const, 11}, - {"EM_TRICORE", Const, 0}, - {"EM_TRIMEDIA", Const, 11}, - {"EM_TSK3000", Const, 11}, - {"EM_UNICORE", Const, 11}, - {"EM_V800", Const, 0}, - {"EM_V850", Const, 11}, - {"EM_VAX", Const, 11}, - {"EM_VIDEOCORE", Const, 11}, - {"EM_VIDEOCORE3", Const, 11}, - {"EM_VIDEOCORE5", Const, 11}, - {"EM_VISIUM", Const, 11}, - {"EM_VPP500", Const, 0}, - {"EM_X86_64", Const, 0}, - {"EM_XCORE", Const, 11}, - {"EM_XGATE", Const, 11}, - {"EM_XIMO16", Const, 11}, - {"EM_XTENSA", Const, 11}, - {"EM_Z80", Const, 11}, - {"EM_ZSP", Const, 11}, - {"ET_CORE", Const, 0}, - {"ET_DYN", Const, 0}, - {"ET_EXEC", Const, 0}, - {"ET_HIOS", Const, 0}, - {"ET_HIPROC", Const, 0}, - {"ET_LOOS", Const, 0}, - {"ET_LOPROC", Const, 0}, - {"ET_NONE", Const, 0}, - {"ET_REL", Const, 0}, - {"EV_CURRENT", Const, 0}, - {"EV_NONE", Const, 0}, - {"ErrNoSymbols", Var, 4}, - {"File", Type, 0}, - {"File.FileHeader", Field, 0}, - {"File.Progs", Field, 0}, - {"File.Sections", Field, 0}, - {"FileHeader", Type, 0}, - {"FileHeader.ABIVersion", Field, 0}, - {"FileHeader.ByteOrder", Field, 0}, - {"FileHeader.Class", Field, 0}, - {"FileHeader.Data", Field, 0}, - {"FileHeader.Entry", Field, 1}, - {"FileHeader.Machine", Field, 0}, - {"FileHeader.OSABI", Field, 0}, - {"FileHeader.Type", Field, 0}, - {"FileHeader.Version", Field, 0}, - {"FormatError", Type, 0}, - {"Header32", Type, 0}, - {"Header32.Ehsize", Field, 0}, - {"Header32.Entry", Field, 0}, - {"Header32.Flags", Field, 0}, - {"Header32.Ident", Field, 0}, - {"Header32.Machine", Field, 0}, - {"Header32.Phentsize", Field, 0}, - {"Header32.Phnum", Field, 0}, - {"Header32.Phoff", Field, 0}, - {"Header32.Shentsize", Field, 0}, - {"Header32.Shnum", Field, 0}, - {"Header32.Shoff", Field, 0}, - {"Header32.Shstrndx", Field, 0}, - {"Header32.Type", Field, 0}, - {"Header32.Version", Field, 0}, - {"Header64", Type, 0}, - {"Header64.Ehsize", Field, 0}, - {"Header64.Entry", Field, 0}, - {"Header64.Flags", Field, 0}, - {"Header64.Ident", Field, 0}, - {"Header64.Machine", Field, 0}, - {"Header64.Phentsize", Field, 0}, - {"Header64.Phnum", Field, 0}, - {"Header64.Phoff", Field, 0}, - {"Header64.Shentsize", Field, 0}, - {"Header64.Shnum", Field, 0}, - {"Header64.Shoff", Field, 0}, - {"Header64.Shstrndx", Field, 0}, - {"Header64.Type", Field, 0}, - {"Header64.Version", Field, 0}, - {"ImportedSymbol", Type, 0}, - {"ImportedSymbol.Library", Field, 0}, - {"ImportedSymbol.Name", Field, 0}, - {"ImportedSymbol.Version", Field, 0}, - {"Machine", Type, 0}, - {"NT_FPREGSET", Const, 0}, - {"NT_PRPSINFO", Const, 0}, - {"NT_PRSTATUS", Const, 0}, - {"NType", Type, 0}, - {"NewFile", Func, 0}, - {"OSABI", Type, 0}, - {"Open", Func, 0}, - {"PF_MASKOS", Const, 0}, - {"PF_MASKPROC", Const, 0}, - {"PF_R", Const, 0}, - {"PF_W", Const, 0}, - {"PF_X", Const, 0}, - {"PT_AARCH64_ARCHEXT", Const, 16}, - {"PT_AARCH64_UNWIND", Const, 16}, - {"PT_ARM_ARCHEXT", Const, 16}, - {"PT_ARM_EXIDX", Const, 16}, - {"PT_DYNAMIC", Const, 0}, - {"PT_GNU_EH_FRAME", Const, 16}, - {"PT_GNU_MBIND_HI", Const, 16}, - {"PT_GNU_MBIND_LO", Const, 16}, - {"PT_GNU_PROPERTY", Const, 16}, - {"PT_GNU_RELRO", Const, 16}, - {"PT_GNU_STACK", Const, 16}, - {"PT_HIOS", Const, 0}, - {"PT_HIPROC", Const, 0}, - {"PT_INTERP", Const, 0}, - {"PT_LOAD", Const, 0}, - {"PT_LOOS", Const, 0}, - {"PT_LOPROC", Const, 0}, - {"PT_MIPS_ABIFLAGS", Const, 16}, - {"PT_MIPS_OPTIONS", Const, 16}, - {"PT_MIPS_REGINFO", Const, 16}, - {"PT_MIPS_RTPROC", Const, 16}, - {"PT_NOTE", Const, 0}, - {"PT_NULL", Const, 0}, - {"PT_OPENBSD_BOOTDATA", Const, 16}, - {"PT_OPENBSD_NOBTCFI", Const, 23}, - {"PT_OPENBSD_RANDOMIZE", Const, 16}, - {"PT_OPENBSD_WXNEEDED", Const, 16}, - {"PT_PAX_FLAGS", Const, 16}, - {"PT_PHDR", Const, 0}, - {"PT_RISCV_ATTRIBUTES", Const, 25}, - {"PT_S390_PGSTE", Const, 16}, - {"PT_SHLIB", Const, 0}, - {"PT_SUNWSTACK", Const, 16}, - {"PT_SUNW_EH_FRAME", Const, 16}, - {"PT_TLS", Const, 0}, - {"Prog", Type, 0}, - {"Prog.ProgHeader", Field, 0}, - {"Prog.ReaderAt", Field, 0}, - {"Prog32", Type, 0}, - {"Prog32.Align", Field, 0}, - {"Prog32.Filesz", Field, 0}, - {"Prog32.Flags", Field, 0}, - {"Prog32.Memsz", Field, 0}, - {"Prog32.Off", Field, 0}, - {"Prog32.Paddr", Field, 0}, - {"Prog32.Type", Field, 0}, - {"Prog32.Vaddr", Field, 0}, - {"Prog64", Type, 0}, - {"Prog64.Align", Field, 0}, - {"Prog64.Filesz", Field, 0}, - {"Prog64.Flags", Field, 0}, - {"Prog64.Memsz", Field, 0}, - {"Prog64.Off", Field, 0}, - {"Prog64.Paddr", Field, 0}, - {"Prog64.Type", Field, 0}, - {"Prog64.Vaddr", Field, 0}, - {"ProgFlag", Type, 0}, - {"ProgHeader", Type, 0}, - {"ProgHeader.Align", Field, 0}, - {"ProgHeader.Filesz", Field, 0}, - {"ProgHeader.Flags", Field, 0}, - {"ProgHeader.Memsz", Field, 0}, - {"ProgHeader.Off", Field, 0}, - {"ProgHeader.Paddr", Field, 0}, - {"ProgHeader.Type", Field, 0}, - {"ProgHeader.Vaddr", Field, 0}, - {"ProgType", Type, 0}, - {"R_386", Type, 0}, - {"R_386_16", Const, 10}, - {"R_386_32", Const, 0}, - {"R_386_32PLT", Const, 10}, - {"R_386_8", Const, 10}, - {"R_386_COPY", Const, 0}, - {"R_386_GLOB_DAT", Const, 0}, - {"R_386_GOT32", Const, 0}, - {"R_386_GOT32X", Const, 10}, - {"R_386_GOTOFF", Const, 0}, - {"R_386_GOTPC", Const, 0}, - {"R_386_IRELATIVE", Const, 10}, - {"R_386_JMP_SLOT", Const, 0}, - {"R_386_NONE", Const, 0}, - {"R_386_PC16", Const, 10}, - {"R_386_PC32", Const, 0}, - {"R_386_PC8", Const, 10}, - {"R_386_PLT32", Const, 0}, - {"R_386_RELATIVE", Const, 0}, - {"R_386_SIZE32", Const, 10}, - {"R_386_TLS_DESC", Const, 10}, - {"R_386_TLS_DESC_CALL", Const, 10}, - {"R_386_TLS_DTPMOD32", Const, 0}, - {"R_386_TLS_DTPOFF32", Const, 0}, - {"R_386_TLS_GD", Const, 0}, - {"R_386_TLS_GD_32", Const, 0}, - {"R_386_TLS_GD_CALL", Const, 0}, - {"R_386_TLS_GD_POP", Const, 0}, - {"R_386_TLS_GD_PUSH", Const, 0}, - {"R_386_TLS_GOTDESC", Const, 10}, - {"R_386_TLS_GOTIE", Const, 0}, - {"R_386_TLS_IE", Const, 0}, - {"R_386_TLS_IE_32", Const, 0}, - {"R_386_TLS_LDM", Const, 0}, - {"R_386_TLS_LDM_32", Const, 0}, - {"R_386_TLS_LDM_CALL", Const, 0}, - {"R_386_TLS_LDM_POP", Const, 0}, - {"R_386_TLS_LDM_PUSH", Const, 0}, - {"R_386_TLS_LDO_32", Const, 0}, - {"R_386_TLS_LE", Const, 0}, - {"R_386_TLS_LE_32", Const, 0}, - {"R_386_TLS_TPOFF", Const, 0}, - {"R_386_TLS_TPOFF32", Const, 0}, - {"R_390", Type, 7}, - {"R_390_12", Const, 7}, - {"R_390_16", Const, 7}, - {"R_390_20", Const, 7}, - {"R_390_32", Const, 7}, - {"R_390_64", Const, 7}, - {"R_390_8", Const, 7}, - {"R_390_COPY", Const, 7}, - {"R_390_GLOB_DAT", Const, 7}, - {"R_390_GOT12", Const, 7}, - {"R_390_GOT16", Const, 7}, - {"R_390_GOT20", Const, 7}, - {"R_390_GOT32", Const, 7}, - {"R_390_GOT64", Const, 7}, - {"R_390_GOTENT", Const, 7}, - {"R_390_GOTOFF", Const, 7}, - {"R_390_GOTOFF16", Const, 7}, - {"R_390_GOTOFF64", Const, 7}, - {"R_390_GOTPC", Const, 7}, - {"R_390_GOTPCDBL", Const, 7}, - {"R_390_GOTPLT12", Const, 7}, - {"R_390_GOTPLT16", Const, 7}, - {"R_390_GOTPLT20", Const, 7}, - {"R_390_GOTPLT32", Const, 7}, - {"R_390_GOTPLT64", Const, 7}, - {"R_390_GOTPLTENT", Const, 7}, - {"R_390_GOTPLTOFF16", Const, 7}, - {"R_390_GOTPLTOFF32", Const, 7}, - {"R_390_GOTPLTOFF64", Const, 7}, - {"R_390_JMP_SLOT", Const, 7}, - {"R_390_NONE", Const, 7}, - {"R_390_PC16", Const, 7}, - {"R_390_PC16DBL", Const, 7}, - {"R_390_PC32", Const, 7}, - {"R_390_PC32DBL", Const, 7}, - {"R_390_PC64", Const, 7}, - {"R_390_PLT16DBL", Const, 7}, - {"R_390_PLT32", Const, 7}, - {"R_390_PLT32DBL", Const, 7}, - {"R_390_PLT64", Const, 7}, - {"R_390_RELATIVE", Const, 7}, - {"R_390_TLS_DTPMOD", Const, 7}, - {"R_390_TLS_DTPOFF", Const, 7}, - {"R_390_TLS_GD32", Const, 7}, - {"R_390_TLS_GD64", Const, 7}, - {"R_390_TLS_GDCALL", Const, 7}, - {"R_390_TLS_GOTIE12", Const, 7}, - {"R_390_TLS_GOTIE20", Const, 7}, - {"R_390_TLS_GOTIE32", Const, 7}, - {"R_390_TLS_GOTIE64", Const, 7}, - {"R_390_TLS_IE32", Const, 7}, - {"R_390_TLS_IE64", Const, 7}, - {"R_390_TLS_IEENT", Const, 7}, - {"R_390_TLS_LDCALL", Const, 7}, - {"R_390_TLS_LDM32", Const, 7}, - {"R_390_TLS_LDM64", Const, 7}, - {"R_390_TLS_LDO32", Const, 7}, - {"R_390_TLS_LDO64", Const, 7}, - {"R_390_TLS_LE32", Const, 7}, - {"R_390_TLS_LE64", Const, 7}, - {"R_390_TLS_LOAD", Const, 7}, - {"R_390_TLS_TPOFF", Const, 7}, - {"R_AARCH64", Type, 4}, - {"R_AARCH64_ABS16", Const, 4}, - {"R_AARCH64_ABS32", Const, 4}, - {"R_AARCH64_ABS64", Const, 4}, - {"R_AARCH64_ADD_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_ADR_GOT_PAGE", Const, 4}, - {"R_AARCH64_ADR_PREL_LO21", Const, 4}, - {"R_AARCH64_ADR_PREL_PG_HI21", Const, 4}, - {"R_AARCH64_ADR_PREL_PG_HI21_NC", Const, 4}, - {"R_AARCH64_CALL26", Const, 4}, - {"R_AARCH64_CONDBR19", Const, 4}, - {"R_AARCH64_COPY", Const, 4}, - {"R_AARCH64_GLOB_DAT", Const, 4}, - {"R_AARCH64_GOT_LD_PREL19", Const, 4}, - {"R_AARCH64_IRELATIVE", Const, 4}, - {"R_AARCH64_JUMP26", Const, 4}, - {"R_AARCH64_JUMP_SLOT", Const, 4}, - {"R_AARCH64_LD64_GOTOFF_LO15", Const, 10}, - {"R_AARCH64_LD64_GOTPAGE_LO15", Const, 10}, - {"R_AARCH64_LD64_GOT_LO12_NC", Const, 4}, - {"R_AARCH64_LDST128_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_LDST16_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_LDST32_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_LDST64_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_LDST8_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_LD_PREL_LO19", Const, 4}, - {"R_AARCH64_MOVW_SABS_G0", Const, 4}, - {"R_AARCH64_MOVW_SABS_G1", Const, 4}, - {"R_AARCH64_MOVW_SABS_G2", Const, 4}, - {"R_AARCH64_MOVW_UABS_G0", Const, 4}, - {"R_AARCH64_MOVW_UABS_G0_NC", Const, 4}, - {"R_AARCH64_MOVW_UABS_G1", Const, 4}, - {"R_AARCH64_MOVW_UABS_G1_NC", Const, 4}, - {"R_AARCH64_MOVW_UABS_G2", Const, 4}, - {"R_AARCH64_MOVW_UABS_G2_NC", Const, 4}, - {"R_AARCH64_MOVW_UABS_G3", Const, 4}, - {"R_AARCH64_NONE", Const, 4}, - {"R_AARCH64_NULL", Const, 4}, - {"R_AARCH64_P32_ABS16", Const, 4}, - {"R_AARCH64_P32_ABS32", Const, 4}, - {"R_AARCH64_P32_ADD_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_P32_ADR_GOT_PAGE", Const, 4}, - {"R_AARCH64_P32_ADR_PREL_LO21", Const, 4}, - {"R_AARCH64_P32_ADR_PREL_PG_HI21", Const, 4}, - {"R_AARCH64_P32_CALL26", Const, 4}, - {"R_AARCH64_P32_CONDBR19", Const, 4}, - {"R_AARCH64_P32_COPY", Const, 4}, - {"R_AARCH64_P32_GLOB_DAT", Const, 4}, - {"R_AARCH64_P32_GOT_LD_PREL19", Const, 4}, - {"R_AARCH64_P32_IRELATIVE", Const, 4}, - {"R_AARCH64_P32_JUMP26", Const, 4}, - {"R_AARCH64_P32_JUMP_SLOT", Const, 4}, - {"R_AARCH64_P32_LD32_GOT_LO12_NC", Const, 4}, - {"R_AARCH64_P32_LDST128_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_P32_LDST16_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_P32_LDST32_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_P32_LDST64_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_P32_LDST8_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_P32_LD_PREL_LO19", Const, 4}, - {"R_AARCH64_P32_MOVW_SABS_G0", Const, 4}, - {"R_AARCH64_P32_MOVW_UABS_G0", Const, 4}, - {"R_AARCH64_P32_MOVW_UABS_G0_NC", Const, 4}, - {"R_AARCH64_P32_MOVW_UABS_G1", Const, 4}, - {"R_AARCH64_P32_PREL16", Const, 4}, - {"R_AARCH64_P32_PREL32", Const, 4}, - {"R_AARCH64_P32_RELATIVE", Const, 4}, - {"R_AARCH64_P32_TLSDESC", Const, 4}, - {"R_AARCH64_P32_TLSDESC_ADD_LO12_NC", Const, 4}, - {"R_AARCH64_P32_TLSDESC_ADR_PAGE21", Const, 4}, - {"R_AARCH64_P32_TLSDESC_ADR_PREL21", Const, 4}, - {"R_AARCH64_P32_TLSDESC_CALL", Const, 4}, - {"R_AARCH64_P32_TLSDESC_LD32_LO12_NC", Const, 4}, - {"R_AARCH64_P32_TLSDESC_LD_PREL19", Const, 4}, - {"R_AARCH64_P32_TLSGD_ADD_LO12_NC", Const, 4}, - {"R_AARCH64_P32_TLSGD_ADR_PAGE21", Const, 4}, - {"R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21", Const, 4}, - {"R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC", Const, 4}, - {"R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19", Const, 4}, - {"R_AARCH64_P32_TLSLE_ADD_TPREL_HI12", Const, 4}, - {"R_AARCH64_P32_TLSLE_ADD_TPREL_LO12", Const, 4}, - {"R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC", Const, 4}, - {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G0", Const, 4}, - {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC", Const, 4}, - {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G1", Const, 4}, - {"R_AARCH64_P32_TLS_DTPMOD", Const, 4}, - {"R_AARCH64_P32_TLS_DTPREL", Const, 4}, - {"R_AARCH64_P32_TLS_TPREL", Const, 4}, - {"R_AARCH64_P32_TSTBR14", Const, 4}, - {"R_AARCH64_PREL16", Const, 4}, - {"R_AARCH64_PREL32", Const, 4}, - {"R_AARCH64_PREL64", Const, 4}, - {"R_AARCH64_RELATIVE", Const, 4}, - {"R_AARCH64_TLSDESC", Const, 4}, - {"R_AARCH64_TLSDESC_ADD", Const, 4}, - {"R_AARCH64_TLSDESC_ADD_LO12_NC", Const, 4}, - {"R_AARCH64_TLSDESC_ADR_PAGE21", Const, 4}, - {"R_AARCH64_TLSDESC_ADR_PREL21", Const, 4}, - {"R_AARCH64_TLSDESC_CALL", Const, 4}, - {"R_AARCH64_TLSDESC_LD64_LO12_NC", Const, 4}, - {"R_AARCH64_TLSDESC_LDR", Const, 4}, - {"R_AARCH64_TLSDESC_LD_PREL19", Const, 4}, - {"R_AARCH64_TLSDESC_OFF_G0_NC", Const, 4}, - {"R_AARCH64_TLSDESC_OFF_G1", Const, 4}, - {"R_AARCH64_TLSGD_ADD_LO12_NC", Const, 4}, - {"R_AARCH64_TLSGD_ADR_PAGE21", Const, 4}, - {"R_AARCH64_TLSGD_ADR_PREL21", Const, 10}, - {"R_AARCH64_TLSGD_MOVW_G0_NC", Const, 10}, - {"R_AARCH64_TLSGD_MOVW_G1", Const, 10}, - {"R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21", Const, 4}, - {"R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC", Const, 4}, - {"R_AARCH64_TLSIE_LD_GOTTPREL_PREL19", Const, 4}, - {"R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC", Const, 4}, - {"R_AARCH64_TLSIE_MOVW_GOTTPREL_G1", Const, 4}, - {"R_AARCH64_TLSLD_ADR_PAGE21", Const, 10}, - {"R_AARCH64_TLSLD_ADR_PREL21", Const, 10}, - {"R_AARCH64_TLSLD_LDST128_DTPREL_LO12", Const, 10}, - {"R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC", Const, 10}, - {"R_AARCH64_TLSLE_ADD_TPREL_HI12", Const, 4}, - {"R_AARCH64_TLSLE_ADD_TPREL_LO12", Const, 4}, - {"R_AARCH64_TLSLE_ADD_TPREL_LO12_NC", Const, 4}, - {"R_AARCH64_TLSLE_LDST128_TPREL_LO12", Const, 10}, - {"R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC", Const, 10}, - {"R_AARCH64_TLSLE_MOVW_TPREL_G0", Const, 4}, - {"R_AARCH64_TLSLE_MOVW_TPREL_G0_NC", Const, 4}, - {"R_AARCH64_TLSLE_MOVW_TPREL_G1", Const, 4}, - {"R_AARCH64_TLSLE_MOVW_TPREL_G1_NC", Const, 4}, - {"R_AARCH64_TLSLE_MOVW_TPREL_G2", Const, 4}, - {"R_AARCH64_TLS_DTPMOD64", Const, 4}, - {"R_AARCH64_TLS_DTPREL64", Const, 4}, - {"R_AARCH64_TLS_TPREL64", Const, 4}, - {"R_AARCH64_TSTBR14", Const, 4}, - {"R_ALPHA", Type, 0}, - {"R_ALPHA_BRADDR", Const, 0}, - {"R_ALPHA_COPY", Const, 0}, - {"R_ALPHA_GLOB_DAT", Const, 0}, - {"R_ALPHA_GPDISP", Const, 0}, - {"R_ALPHA_GPREL32", Const, 0}, - {"R_ALPHA_GPRELHIGH", Const, 0}, - {"R_ALPHA_GPRELLOW", Const, 0}, - {"R_ALPHA_GPVALUE", Const, 0}, - {"R_ALPHA_HINT", Const, 0}, - {"R_ALPHA_IMMED_BR_HI32", Const, 0}, - {"R_ALPHA_IMMED_GP_16", Const, 0}, - {"R_ALPHA_IMMED_GP_HI32", Const, 0}, - {"R_ALPHA_IMMED_LO32", Const, 0}, - {"R_ALPHA_IMMED_SCN_HI32", Const, 0}, - {"R_ALPHA_JMP_SLOT", Const, 0}, - {"R_ALPHA_LITERAL", Const, 0}, - {"R_ALPHA_LITUSE", Const, 0}, - {"R_ALPHA_NONE", Const, 0}, - {"R_ALPHA_OP_PRSHIFT", Const, 0}, - {"R_ALPHA_OP_PSUB", Const, 0}, - {"R_ALPHA_OP_PUSH", Const, 0}, - {"R_ALPHA_OP_STORE", Const, 0}, - {"R_ALPHA_REFLONG", Const, 0}, - {"R_ALPHA_REFQUAD", Const, 0}, - {"R_ALPHA_RELATIVE", Const, 0}, - {"R_ALPHA_SREL16", Const, 0}, - {"R_ALPHA_SREL32", Const, 0}, - {"R_ALPHA_SREL64", Const, 0}, - {"R_ARM", Type, 0}, - {"R_ARM_ABS12", Const, 0}, - {"R_ARM_ABS16", Const, 0}, - {"R_ARM_ABS32", Const, 0}, - {"R_ARM_ABS32_NOI", Const, 10}, - {"R_ARM_ABS8", Const, 0}, - {"R_ARM_ALU_PCREL_15_8", Const, 10}, - {"R_ARM_ALU_PCREL_23_15", Const, 10}, - {"R_ARM_ALU_PCREL_7_0", Const, 10}, - {"R_ARM_ALU_PC_G0", Const, 10}, - {"R_ARM_ALU_PC_G0_NC", Const, 10}, - {"R_ARM_ALU_PC_G1", Const, 10}, - {"R_ARM_ALU_PC_G1_NC", Const, 10}, - {"R_ARM_ALU_PC_G2", Const, 10}, - {"R_ARM_ALU_SBREL_19_12_NC", Const, 10}, - {"R_ARM_ALU_SBREL_27_20_CK", Const, 10}, - {"R_ARM_ALU_SB_G0", Const, 10}, - {"R_ARM_ALU_SB_G0_NC", Const, 10}, - {"R_ARM_ALU_SB_G1", Const, 10}, - {"R_ARM_ALU_SB_G1_NC", Const, 10}, - {"R_ARM_ALU_SB_G2", Const, 10}, - {"R_ARM_AMP_VCALL9", Const, 0}, - {"R_ARM_BASE_ABS", Const, 10}, - {"R_ARM_CALL", Const, 10}, - {"R_ARM_COPY", Const, 0}, - {"R_ARM_GLOB_DAT", Const, 0}, - {"R_ARM_GNU_VTENTRY", Const, 0}, - {"R_ARM_GNU_VTINHERIT", Const, 0}, - {"R_ARM_GOT32", Const, 0}, - {"R_ARM_GOTOFF", Const, 0}, - {"R_ARM_GOTOFF12", Const, 10}, - {"R_ARM_GOTPC", Const, 0}, - {"R_ARM_GOTRELAX", Const, 10}, - {"R_ARM_GOT_ABS", Const, 10}, - {"R_ARM_GOT_BREL12", Const, 10}, - {"R_ARM_GOT_PREL", Const, 10}, - {"R_ARM_IRELATIVE", Const, 10}, - {"R_ARM_JUMP24", Const, 10}, - {"R_ARM_JUMP_SLOT", Const, 0}, - {"R_ARM_LDC_PC_G0", Const, 10}, - {"R_ARM_LDC_PC_G1", Const, 10}, - {"R_ARM_LDC_PC_G2", Const, 10}, - {"R_ARM_LDC_SB_G0", Const, 10}, - {"R_ARM_LDC_SB_G1", Const, 10}, - {"R_ARM_LDC_SB_G2", Const, 10}, - {"R_ARM_LDRS_PC_G0", Const, 10}, - {"R_ARM_LDRS_PC_G1", Const, 10}, - {"R_ARM_LDRS_PC_G2", Const, 10}, - {"R_ARM_LDRS_SB_G0", Const, 10}, - {"R_ARM_LDRS_SB_G1", Const, 10}, - {"R_ARM_LDRS_SB_G2", Const, 10}, - {"R_ARM_LDR_PC_G1", Const, 10}, - {"R_ARM_LDR_PC_G2", Const, 10}, - {"R_ARM_LDR_SBREL_11_10_NC", Const, 10}, - {"R_ARM_LDR_SB_G0", Const, 10}, - {"R_ARM_LDR_SB_G1", Const, 10}, - {"R_ARM_LDR_SB_G2", Const, 10}, - {"R_ARM_ME_TOO", Const, 10}, - {"R_ARM_MOVT_ABS", Const, 10}, - {"R_ARM_MOVT_BREL", Const, 10}, - {"R_ARM_MOVT_PREL", Const, 10}, - {"R_ARM_MOVW_ABS_NC", Const, 10}, - {"R_ARM_MOVW_BREL", Const, 10}, - {"R_ARM_MOVW_BREL_NC", Const, 10}, - {"R_ARM_MOVW_PREL_NC", Const, 10}, - {"R_ARM_NONE", Const, 0}, - {"R_ARM_PC13", Const, 0}, - {"R_ARM_PC24", Const, 0}, - {"R_ARM_PLT32", Const, 0}, - {"R_ARM_PLT32_ABS", Const, 10}, - {"R_ARM_PREL31", Const, 10}, - {"R_ARM_PRIVATE_0", Const, 10}, - {"R_ARM_PRIVATE_1", Const, 10}, - {"R_ARM_PRIVATE_10", Const, 10}, - {"R_ARM_PRIVATE_11", Const, 10}, - {"R_ARM_PRIVATE_12", Const, 10}, - {"R_ARM_PRIVATE_13", Const, 10}, - {"R_ARM_PRIVATE_14", Const, 10}, - {"R_ARM_PRIVATE_15", Const, 10}, - {"R_ARM_PRIVATE_2", Const, 10}, - {"R_ARM_PRIVATE_3", Const, 10}, - {"R_ARM_PRIVATE_4", Const, 10}, - {"R_ARM_PRIVATE_5", Const, 10}, - {"R_ARM_PRIVATE_6", Const, 10}, - {"R_ARM_PRIVATE_7", Const, 10}, - {"R_ARM_PRIVATE_8", Const, 10}, - {"R_ARM_PRIVATE_9", Const, 10}, - {"R_ARM_RABS32", Const, 0}, - {"R_ARM_RBASE", Const, 0}, - {"R_ARM_REL32", Const, 0}, - {"R_ARM_REL32_NOI", Const, 10}, - {"R_ARM_RELATIVE", Const, 0}, - {"R_ARM_RPC24", Const, 0}, - {"R_ARM_RREL32", Const, 0}, - {"R_ARM_RSBREL32", Const, 0}, - {"R_ARM_RXPC25", Const, 10}, - {"R_ARM_SBREL31", Const, 10}, - {"R_ARM_SBREL32", Const, 0}, - {"R_ARM_SWI24", Const, 0}, - {"R_ARM_TARGET1", Const, 10}, - {"R_ARM_TARGET2", Const, 10}, - {"R_ARM_THM_ABS5", Const, 0}, - {"R_ARM_THM_ALU_ABS_G0_NC", Const, 10}, - {"R_ARM_THM_ALU_ABS_G1_NC", Const, 10}, - {"R_ARM_THM_ALU_ABS_G2_NC", Const, 10}, - {"R_ARM_THM_ALU_ABS_G3", Const, 10}, - {"R_ARM_THM_ALU_PREL_11_0", Const, 10}, - {"R_ARM_THM_GOT_BREL12", Const, 10}, - {"R_ARM_THM_JUMP11", Const, 10}, - {"R_ARM_THM_JUMP19", Const, 10}, - {"R_ARM_THM_JUMP24", Const, 10}, - {"R_ARM_THM_JUMP6", Const, 10}, - {"R_ARM_THM_JUMP8", Const, 10}, - {"R_ARM_THM_MOVT_ABS", Const, 10}, - {"R_ARM_THM_MOVT_BREL", Const, 10}, - {"R_ARM_THM_MOVT_PREL", Const, 10}, - {"R_ARM_THM_MOVW_ABS_NC", Const, 10}, - {"R_ARM_THM_MOVW_BREL", Const, 10}, - {"R_ARM_THM_MOVW_BREL_NC", Const, 10}, - {"R_ARM_THM_MOVW_PREL_NC", Const, 10}, - {"R_ARM_THM_PC12", Const, 10}, - {"R_ARM_THM_PC22", Const, 0}, - {"R_ARM_THM_PC8", Const, 0}, - {"R_ARM_THM_RPC22", Const, 0}, - {"R_ARM_THM_SWI8", Const, 0}, - {"R_ARM_THM_TLS_CALL", Const, 10}, - {"R_ARM_THM_TLS_DESCSEQ16", Const, 10}, - {"R_ARM_THM_TLS_DESCSEQ32", Const, 10}, - {"R_ARM_THM_XPC22", Const, 0}, - {"R_ARM_TLS_CALL", Const, 10}, - {"R_ARM_TLS_DESCSEQ", Const, 10}, - {"R_ARM_TLS_DTPMOD32", Const, 10}, - {"R_ARM_TLS_DTPOFF32", Const, 10}, - {"R_ARM_TLS_GD32", Const, 10}, - {"R_ARM_TLS_GOTDESC", Const, 10}, - {"R_ARM_TLS_IE12GP", Const, 10}, - {"R_ARM_TLS_IE32", Const, 10}, - {"R_ARM_TLS_LDM32", Const, 10}, - {"R_ARM_TLS_LDO12", Const, 10}, - {"R_ARM_TLS_LDO32", Const, 10}, - {"R_ARM_TLS_LE12", Const, 10}, - {"R_ARM_TLS_LE32", Const, 10}, - {"R_ARM_TLS_TPOFF32", Const, 10}, - {"R_ARM_V4BX", Const, 10}, - {"R_ARM_XPC25", Const, 0}, - {"R_INFO", Func, 0}, - {"R_INFO32", Func, 0}, - {"R_LARCH", Type, 19}, - {"R_LARCH_32", Const, 19}, - {"R_LARCH_32_PCREL", Const, 20}, - {"R_LARCH_64", Const, 19}, - {"R_LARCH_64_PCREL", Const, 22}, - {"R_LARCH_ABS64_HI12", Const, 20}, - {"R_LARCH_ABS64_LO20", Const, 20}, - {"R_LARCH_ABS_HI20", Const, 20}, - {"R_LARCH_ABS_LO12", Const, 20}, - {"R_LARCH_ADD16", Const, 19}, - {"R_LARCH_ADD24", Const, 19}, - {"R_LARCH_ADD32", Const, 19}, - {"R_LARCH_ADD6", Const, 22}, - {"R_LARCH_ADD64", Const, 19}, - {"R_LARCH_ADD8", Const, 19}, - {"R_LARCH_ADD_ULEB128", Const, 22}, - {"R_LARCH_ALIGN", Const, 22}, - {"R_LARCH_B16", Const, 20}, - {"R_LARCH_B21", Const, 20}, - {"R_LARCH_B26", Const, 20}, - {"R_LARCH_CFA", Const, 22}, - {"R_LARCH_COPY", Const, 19}, - {"R_LARCH_DELETE", Const, 22}, - {"R_LARCH_GNU_VTENTRY", Const, 20}, - {"R_LARCH_GNU_VTINHERIT", Const, 20}, - {"R_LARCH_GOT64_HI12", Const, 20}, - {"R_LARCH_GOT64_LO20", Const, 20}, - {"R_LARCH_GOT64_PC_HI12", Const, 20}, - {"R_LARCH_GOT64_PC_LO20", Const, 20}, - {"R_LARCH_GOT_HI20", Const, 20}, - {"R_LARCH_GOT_LO12", Const, 20}, - {"R_LARCH_GOT_PC_HI20", Const, 20}, - {"R_LARCH_GOT_PC_LO12", Const, 20}, - {"R_LARCH_IRELATIVE", Const, 19}, - {"R_LARCH_JUMP_SLOT", Const, 19}, - {"R_LARCH_MARK_LA", Const, 19}, - {"R_LARCH_MARK_PCREL", Const, 19}, - {"R_LARCH_NONE", Const, 19}, - {"R_LARCH_PCALA64_HI12", Const, 20}, - {"R_LARCH_PCALA64_LO20", Const, 20}, - {"R_LARCH_PCALA_HI20", Const, 20}, - {"R_LARCH_PCALA_LO12", Const, 20}, - {"R_LARCH_PCREL20_S2", Const, 22}, - {"R_LARCH_RELATIVE", Const, 19}, - {"R_LARCH_RELAX", Const, 20}, - {"R_LARCH_SOP_ADD", Const, 19}, - {"R_LARCH_SOP_AND", Const, 19}, - {"R_LARCH_SOP_ASSERT", Const, 19}, - {"R_LARCH_SOP_IF_ELSE", Const, 19}, - {"R_LARCH_SOP_NOT", Const, 19}, - {"R_LARCH_SOP_POP_32_S_0_10_10_16_S2", Const, 19}, - {"R_LARCH_SOP_POP_32_S_0_5_10_16_S2", Const, 19}, - {"R_LARCH_SOP_POP_32_S_10_12", Const, 19}, - {"R_LARCH_SOP_POP_32_S_10_16", Const, 19}, - {"R_LARCH_SOP_POP_32_S_10_16_S2", Const, 19}, - {"R_LARCH_SOP_POP_32_S_10_5", Const, 19}, - {"R_LARCH_SOP_POP_32_S_5_20", Const, 19}, - {"R_LARCH_SOP_POP_32_U", Const, 19}, - {"R_LARCH_SOP_POP_32_U_10_12", Const, 19}, - {"R_LARCH_SOP_PUSH_ABSOLUTE", Const, 19}, - {"R_LARCH_SOP_PUSH_DUP", Const, 19}, - {"R_LARCH_SOP_PUSH_GPREL", Const, 19}, - {"R_LARCH_SOP_PUSH_PCREL", Const, 19}, - {"R_LARCH_SOP_PUSH_PLT_PCREL", Const, 19}, - {"R_LARCH_SOP_PUSH_TLS_GD", Const, 19}, - {"R_LARCH_SOP_PUSH_TLS_GOT", Const, 19}, - {"R_LARCH_SOP_PUSH_TLS_TPREL", Const, 19}, - {"R_LARCH_SOP_SL", Const, 19}, - {"R_LARCH_SOP_SR", Const, 19}, - {"R_LARCH_SOP_SUB", Const, 19}, - {"R_LARCH_SUB16", Const, 19}, - {"R_LARCH_SUB24", Const, 19}, - {"R_LARCH_SUB32", Const, 19}, - {"R_LARCH_SUB6", Const, 22}, - {"R_LARCH_SUB64", Const, 19}, - {"R_LARCH_SUB8", Const, 19}, - {"R_LARCH_SUB_ULEB128", Const, 22}, - {"R_LARCH_TLS_DTPMOD32", Const, 19}, - {"R_LARCH_TLS_DTPMOD64", Const, 19}, - {"R_LARCH_TLS_DTPREL32", Const, 19}, - {"R_LARCH_TLS_DTPREL64", Const, 19}, - {"R_LARCH_TLS_GD_HI20", Const, 20}, - {"R_LARCH_TLS_GD_PC_HI20", Const, 20}, - {"R_LARCH_TLS_IE64_HI12", Const, 20}, - {"R_LARCH_TLS_IE64_LO20", Const, 20}, - {"R_LARCH_TLS_IE64_PC_HI12", Const, 20}, - {"R_LARCH_TLS_IE64_PC_LO20", Const, 20}, - {"R_LARCH_TLS_IE_HI20", Const, 20}, - {"R_LARCH_TLS_IE_LO12", Const, 20}, - {"R_LARCH_TLS_IE_PC_HI20", Const, 20}, - {"R_LARCH_TLS_IE_PC_LO12", Const, 20}, - {"R_LARCH_TLS_LD_HI20", Const, 20}, - {"R_LARCH_TLS_LD_PC_HI20", Const, 20}, - {"R_LARCH_TLS_LE64_HI12", Const, 20}, - {"R_LARCH_TLS_LE64_LO20", Const, 20}, - {"R_LARCH_TLS_LE_HI20", Const, 20}, - {"R_LARCH_TLS_LE_LO12", Const, 20}, - {"R_LARCH_TLS_TPREL32", Const, 19}, - {"R_LARCH_TLS_TPREL64", Const, 19}, - {"R_MIPS", Type, 6}, - {"R_MIPS_16", Const, 6}, - {"R_MIPS_26", Const, 6}, - {"R_MIPS_32", Const, 6}, - {"R_MIPS_64", Const, 6}, - {"R_MIPS_ADD_IMMEDIATE", Const, 6}, - {"R_MIPS_CALL16", Const, 6}, - {"R_MIPS_CALL_HI16", Const, 6}, - {"R_MIPS_CALL_LO16", Const, 6}, - {"R_MIPS_DELETE", Const, 6}, - {"R_MIPS_GOT16", Const, 6}, - {"R_MIPS_GOT_DISP", Const, 6}, - {"R_MIPS_GOT_HI16", Const, 6}, - {"R_MIPS_GOT_LO16", Const, 6}, - {"R_MIPS_GOT_OFST", Const, 6}, - {"R_MIPS_GOT_PAGE", Const, 6}, - {"R_MIPS_GPREL16", Const, 6}, - {"R_MIPS_GPREL32", Const, 6}, - {"R_MIPS_HI16", Const, 6}, - {"R_MIPS_HIGHER", Const, 6}, - {"R_MIPS_HIGHEST", Const, 6}, - {"R_MIPS_INSERT_A", Const, 6}, - {"R_MIPS_INSERT_B", Const, 6}, - {"R_MIPS_JALR", Const, 6}, - {"R_MIPS_LITERAL", Const, 6}, - {"R_MIPS_LO16", Const, 6}, - {"R_MIPS_NONE", Const, 6}, - {"R_MIPS_PC16", Const, 6}, - {"R_MIPS_PC32", Const, 22}, - {"R_MIPS_PJUMP", Const, 6}, - {"R_MIPS_REL16", Const, 6}, - {"R_MIPS_REL32", Const, 6}, - {"R_MIPS_RELGOT", Const, 6}, - {"R_MIPS_SCN_DISP", Const, 6}, - {"R_MIPS_SHIFT5", Const, 6}, - {"R_MIPS_SHIFT6", Const, 6}, - {"R_MIPS_SUB", Const, 6}, - {"R_MIPS_TLS_DTPMOD32", Const, 6}, - {"R_MIPS_TLS_DTPMOD64", Const, 6}, - {"R_MIPS_TLS_DTPREL32", Const, 6}, - {"R_MIPS_TLS_DTPREL64", Const, 6}, - {"R_MIPS_TLS_DTPREL_HI16", Const, 6}, - {"R_MIPS_TLS_DTPREL_LO16", Const, 6}, - {"R_MIPS_TLS_GD", Const, 6}, - {"R_MIPS_TLS_GOTTPREL", Const, 6}, - {"R_MIPS_TLS_LDM", Const, 6}, - {"R_MIPS_TLS_TPREL32", Const, 6}, - {"R_MIPS_TLS_TPREL64", Const, 6}, - {"R_MIPS_TLS_TPREL_HI16", Const, 6}, - {"R_MIPS_TLS_TPREL_LO16", Const, 6}, - {"R_PPC", Type, 0}, - {"R_PPC64", Type, 5}, - {"R_PPC64_ADDR14", Const, 5}, - {"R_PPC64_ADDR14_BRNTAKEN", Const, 5}, - {"R_PPC64_ADDR14_BRTAKEN", Const, 5}, - {"R_PPC64_ADDR16", Const, 5}, - {"R_PPC64_ADDR16_DS", Const, 5}, - {"R_PPC64_ADDR16_HA", Const, 5}, - {"R_PPC64_ADDR16_HI", Const, 5}, - {"R_PPC64_ADDR16_HIGH", Const, 10}, - {"R_PPC64_ADDR16_HIGHA", Const, 10}, - {"R_PPC64_ADDR16_HIGHER", Const, 5}, - {"R_PPC64_ADDR16_HIGHER34", Const, 20}, - {"R_PPC64_ADDR16_HIGHERA", Const, 5}, - {"R_PPC64_ADDR16_HIGHERA34", Const, 20}, - {"R_PPC64_ADDR16_HIGHEST", Const, 5}, - {"R_PPC64_ADDR16_HIGHEST34", Const, 20}, - {"R_PPC64_ADDR16_HIGHESTA", Const, 5}, - {"R_PPC64_ADDR16_HIGHESTA34", Const, 20}, - {"R_PPC64_ADDR16_LO", Const, 5}, - {"R_PPC64_ADDR16_LO_DS", Const, 5}, - {"R_PPC64_ADDR24", Const, 5}, - {"R_PPC64_ADDR32", Const, 5}, - {"R_PPC64_ADDR64", Const, 5}, - {"R_PPC64_ADDR64_LOCAL", Const, 10}, - {"R_PPC64_COPY", Const, 20}, - {"R_PPC64_D28", Const, 20}, - {"R_PPC64_D34", Const, 20}, - {"R_PPC64_D34_HA30", Const, 20}, - {"R_PPC64_D34_HI30", Const, 20}, - {"R_PPC64_D34_LO", Const, 20}, - {"R_PPC64_DTPMOD64", Const, 5}, - {"R_PPC64_DTPREL16", Const, 5}, - {"R_PPC64_DTPREL16_DS", Const, 5}, - {"R_PPC64_DTPREL16_HA", Const, 5}, - {"R_PPC64_DTPREL16_HI", Const, 5}, - {"R_PPC64_DTPREL16_HIGH", Const, 10}, - {"R_PPC64_DTPREL16_HIGHA", Const, 10}, - {"R_PPC64_DTPREL16_HIGHER", Const, 5}, - {"R_PPC64_DTPREL16_HIGHERA", Const, 5}, - {"R_PPC64_DTPREL16_HIGHEST", Const, 5}, - {"R_PPC64_DTPREL16_HIGHESTA", Const, 5}, - {"R_PPC64_DTPREL16_LO", Const, 5}, - {"R_PPC64_DTPREL16_LO_DS", Const, 5}, - {"R_PPC64_DTPREL34", Const, 20}, - {"R_PPC64_DTPREL64", Const, 5}, - {"R_PPC64_ENTRY", Const, 10}, - {"R_PPC64_GLOB_DAT", Const, 20}, - {"R_PPC64_GNU_VTENTRY", Const, 20}, - {"R_PPC64_GNU_VTINHERIT", Const, 20}, - {"R_PPC64_GOT16", Const, 5}, - {"R_PPC64_GOT16_DS", Const, 5}, - {"R_PPC64_GOT16_HA", Const, 5}, - {"R_PPC64_GOT16_HI", Const, 5}, - {"R_PPC64_GOT16_LO", Const, 5}, - {"R_PPC64_GOT16_LO_DS", Const, 5}, - {"R_PPC64_GOT_DTPREL16_DS", Const, 5}, - {"R_PPC64_GOT_DTPREL16_HA", Const, 5}, - {"R_PPC64_GOT_DTPREL16_HI", Const, 5}, - {"R_PPC64_GOT_DTPREL16_LO_DS", Const, 5}, - {"R_PPC64_GOT_DTPREL_PCREL34", Const, 20}, - {"R_PPC64_GOT_PCREL34", Const, 20}, - {"R_PPC64_GOT_TLSGD16", Const, 5}, - {"R_PPC64_GOT_TLSGD16_HA", Const, 5}, - {"R_PPC64_GOT_TLSGD16_HI", Const, 5}, - {"R_PPC64_GOT_TLSGD16_LO", Const, 5}, - {"R_PPC64_GOT_TLSGD_PCREL34", Const, 20}, - {"R_PPC64_GOT_TLSLD16", Const, 5}, - {"R_PPC64_GOT_TLSLD16_HA", Const, 5}, - {"R_PPC64_GOT_TLSLD16_HI", Const, 5}, - {"R_PPC64_GOT_TLSLD16_LO", Const, 5}, - {"R_PPC64_GOT_TLSLD_PCREL34", Const, 20}, - {"R_PPC64_GOT_TPREL16_DS", Const, 5}, - {"R_PPC64_GOT_TPREL16_HA", Const, 5}, - {"R_PPC64_GOT_TPREL16_HI", Const, 5}, - {"R_PPC64_GOT_TPREL16_LO_DS", Const, 5}, - {"R_PPC64_GOT_TPREL_PCREL34", Const, 20}, - {"R_PPC64_IRELATIVE", Const, 10}, - {"R_PPC64_JMP_IREL", Const, 10}, - {"R_PPC64_JMP_SLOT", Const, 5}, - {"R_PPC64_NONE", Const, 5}, - {"R_PPC64_PCREL28", Const, 20}, - {"R_PPC64_PCREL34", Const, 20}, - {"R_PPC64_PCREL_OPT", Const, 20}, - {"R_PPC64_PLT16_HA", Const, 20}, - {"R_PPC64_PLT16_HI", Const, 20}, - {"R_PPC64_PLT16_LO", Const, 20}, - {"R_PPC64_PLT16_LO_DS", Const, 10}, - {"R_PPC64_PLT32", Const, 20}, - {"R_PPC64_PLT64", Const, 20}, - {"R_PPC64_PLTCALL", Const, 20}, - {"R_PPC64_PLTCALL_NOTOC", Const, 20}, - {"R_PPC64_PLTGOT16", Const, 10}, - {"R_PPC64_PLTGOT16_DS", Const, 10}, - {"R_PPC64_PLTGOT16_HA", Const, 10}, - {"R_PPC64_PLTGOT16_HI", Const, 10}, - {"R_PPC64_PLTGOT16_LO", Const, 10}, - {"R_PPC64_PLTGOT_LO_DS", Const, 10}, - {"R_PPC64_PLTREL32", Const, 20}, - {"R_PPC64_PLTREL64", Const, 20}, - {"R_PPC64_PLTSEQ", Const, 20}, - {"R_PPC64_PLTSEQ_NOTOC", Const, 20}, - {"R_PPC64_PLT_PCREL34", Const, 20}, - {"R_PPC64_PLT_PCREL34_NOTOC", Const, 20}, - {"R_PPC64_REL14", Const, 5}, - {"R_PPC64_REL14_BRNTAKEN", Const, 5}, - {"R_PPC64_REL14_BRTAKEN", Const, 5}, - {"R_PPC64_REL16", Const, 5}, - {"R_PPC64_REL16DX_HA", Const, 10}, - {"R_PPC64_REL16_HA", Const, 5}, - {"R_PPC64_REL16_HI", Const, 5}, - {"R_PPC64_REL16_HIGH", Const, 20}, - {"R_PPC64_REL16_HIGHA", Const, 20}, - {"R_PPC64_REL16_HIGHER", Const, 20}, - {"R_PPC64_REL16_HIGHER34", Const, 20}, - {"R_PPC64_REL16_HIGHERA", Const, 20}, - {"R_PPC64_REL16_HIGHERA34", Const, 20}, - {"R_PPC64_REL16_HIGHEST", Const, 20}, - {"R_PPC64_REL16_HIGHEST34", Const, 20}, - {"R_PPC64_REL16_HIGHESTA", Const, 20}, - {"R_PPC64_REL16_HIGHESTA34", Const, 20}, - {"R_PPC64_REL16_LO", Const, 5}, - {"R_PPC64_REL24", Const, 5}, - {"R_PPC64_REL24_NOTOC", Const, 10}, - {"R_PPC64_REL24_P9NOTOC", Const, 21}, - {"R_PPC64_REL30", Const, 20}, - {"R_PPC64_REL32", Const, 5}, - {"R_PPC64_REL64", Const, 5}, - {"R_PPC64_RELATIVE", Const, 18}, - {"R_PPC64_SECTOFF", Const, 20}, - {"R_PPC64_SECTOFF_DS", Const, 10}, - {"R_PPC64_SECTOFF_HA", Const, 20}, - {"R_PPC64_SECTOFF_HI", Const, 20}, - {"R_PPC64_SECTOFF_LO", Const, 20}, - {"R_PPC64_SECTOFF_LO_DS", Const, 10}, - {"R_PPC64_TLS", Const, 5}, - {"R_PPC64_TLSGD", Const, 5}, - {"R_PPC64_TLSLD", Const, 5}, - {"R_PPC64_TOC", Const, 5}, - {"R_PPC64_TOC16", Const, 5}, - {"R_PPC64_TOC16_DS", Const, 5}, - {"R_PPC64_TOC16_HA", Const, 5}, - {"R_PPC64_TOC16_HI", Const, 5}, - {"R_PPC64_TOC16_LO", Const, 5}, - {"R_PPC64_TOC16_LO_DS", Const, 5}, - {"R_PPC64_TOCSAVE", Const, 10}, - {"R_PPC64_TPREL16", Const, 5}, - {"R_PPC64_TPREL16_DS", Const, 5}, - {"R_PPC64_TPREL16_HA", Const, 5}, - {"R_PPC64_TPREL16_HI", Const, 5}, - {"R_PPC64_TPREL16_HIGH", Const, 10}, - {"R_PPC64_TPREL16_HIGHA", Const, 10}, - {"R_PPC64_TPREL16_HIGHER", Const, 5}, - {"R_PPC64_TPREL16_HIGHERA", Const, 5}, - {"R_PPC64_TPREL16_HIGHEST", Const, 5}, - {"R_PPC64_TPREL16_HIGHESTA", Const, 5}, - {"R_PPC64_TPREL16_LO", Const, 5}, - {"R_PPC64_TPREL16_LO_DS", Const, 5}, - {"R_PPC64_TPREL34", Const, 20}, - {"R_PPC64_TPREL64", Const, 5}, - {"R_PPC64_UADDR16", Const, 20}, - {"R_PPC64_UADDR32", Const, 20}, - {"R_PPC64_UADDR64", Const, 20}, - {"R_PPC_ADDR14", Const, 0}, - {"R_PPC_ADDR14_BRNTAKEN", Const, 0}, - {"R_PPC_ADDR14_BRTAKEN", Const, 0}, - {"R_PPC_ADDR16", Const, 0}, - {"R_PPC_ADDR16_HA", Const, 0}, - {"R_PPC_ADDR16_HI", Const, 0}, - {"R_PPC_ADDR16_LO", Const, 0}, - {"R_PPC_ADDR24", Const, 0}, - {"R_PPC_ADDR32", Const, 0}, - {"R_PPC_COPY", Const, 0}, - {"R_PPC_DTPMOD32", Const, 0}, - {"R_PPC_DTPREL16", Const, 0}, - {"R_PPC_DTPREL16_HA", Const, 0}, - {"R_PPC_DTPREL16_HI", Const, 0}, - {"R_PPC_DTPREL16_LO", Const, 0}, - {"R_PPC_DTPREL32", Const, 0}, - {"R_PPC_EMB_BIT_FLD", Const, 0}, - {"R_PPC_EMB_MRKREF", Const, 0}, - {"R_PPC_EMB_NADDR16", Const, 0}, - {"R_PPC_EMB_NADDR16_HA", Const, 0}, - {"R_PPC_EMB_NADDR16_HI", Const, 0}, - {"R_PPC_EMB_NADDR16_LO", Const, 0}, - {"R_PPC_EMB_NADDR32", Const, 0}, - {"R_PPC_EMB_RELSDA", Const, 0}, - {"R_PPC_EMB_RELSEC16", Const, 0}, - {"R_PPC_EMB_RELST_HA", Const, 0}, - {"R_PPC_EMB_RELST_HI", Const, 0}, - {"R_PPC_EMB_RELST_LO", Const, 0}, - {"R_PPC_EMB_SDA21", Const, 0}, - {"R_PPC_EMB_SDA2I16", Const, 0}, - {"R_PPC_EMB_SDA2REL", Const, 0}, - {"R_PPC_EMB_SDAI16", Const, 0}, - {"R_PPC_GLOB_DAT", Const, 0}, - {"R_PPC_GOT16", Const, 0}, - {"R_PPC_GOT16_HA", Const, 0}, - {"R_PPC_GOT16_HI", Const, 0}, - {"R_PPC_GOT16_LO", Const, 0}, - {"R_PPC_GOT_TLSGD16", Const, 0}, - {"R_PPC_GOT_TLSGD16_HA", Const, 0}, - {"R_PPC_GOT_TLSGD16_HI", Const, 0}, - {"R_PPC_GOT_TLSGD16_LO", Const, 0}, - {"R_PPC_GOT_TLSLD16", Const, 0}, - {"R_PPC_GOT_TLSLD16_HA", Const, 0}, - {"R_PPC_GOT_TLSLD16_HI", Const, 0}, - {"R_PPC_GOT_TLSLD16_LO", Const, 0}, - {"R_PPC_GOT_TPREL16", Const, 0}, - {"R_PPC_GOT_TPREL16_HA", Const, 0}, - {"R_PPC_GOT_TPREL16_HI", Const, 0}, - {"R_PPC_GOT_TPREL16_LO", Const, 0}, - {"R_PPC_JMP_SLOT", Const, 0}, - {"R_PPC_LOCAL24PC", Const, 0}, - {"R_PPC_NONE", Const, 0}, - {"R_PPC_PLT16_HA", Const, 0}, - {"R_PPC_PLT16_HI", Const, 0}, - {"R_PPC_PLT16_LO", Const, 0}, - {"R_PPC_PLT32", Const, 0}, - {"R_PPC_PLTREL24", Const, 0}, - {"R_PPC_PLTREL32", Const, 0}, - {"R_PPC_REL14", Const, 0}, - {"R_PPC_REL14_BRNTAKEN", Const, 0}, - {"R_PPC_REL14_BRTAKEN", Const, 0}, - {"R_PPC_REL24", Const, 0}, - {"R_PPC_REL32", Const, 0}, - {"R_PPC_RELATIVE", Const, 0}, - {"R_PPC_SDAREL16", Const, 0}, - {"R_PPC_SECTOFF", Const, 0}, - {"R_PPC_SECTOFF_HA", Const, 0}, - {"R_PPC_SECTOFF_HI", Const, 0}, - {"R_PPC_SECTOFF_LO", Const, 0}, - {"R_PPC_TLS", Const, 0}, - {"R_PPC_TPREL16", Const, 0}, - {"R_PPC_TPREL16_HA", Const, 0}, - {"R_PPC_TPREL16_HI", Const, 0}, - {"R_PPC_TPREL16_LO", Const, 0}, - {"R_PPC_TPREL32", Const, 0}, - {"R_PPC_UADDR16", Const, 0}, - {"R_PPC_UADDR32", Const, 0}, - {"R_RISCV", Type, 11}, - {"R_RISCV_32", Const, 11}, - {"R_RISCV_32_PCREL", Const, 12}, - {"R_RISCV_64", Const, 11}, - {"R_RISCV_ADD16", Const, 11}, - {"R_RISCV_ADD32", Const, 11}, - {"R_RISCV_ADD64", Const, 11}, - {"R_RISCV_ADD8", Const, 11}, - {"R_RISCV_ALIGN", Const, 11}, - {"R_RISCV_BRANCH", Const, 11}, - {"R_RISCV_CALL", Const, 11}, - {"R_RISCV_CALL_PLT", Const, 11}, - {"R_RISCV_COPY", Const, 11}, - {"R_RISCV_GNU_VTENTRY", Const, 11}, - {"R_RISCV_GNU_VTINHERIT", Const, 11}, - {"R_RISCV_GOT_HI20", Const, 11}, - {"R_RISCV_GPREL_I", Const, 11}, - {"R_RISCV_GPREL_S", Const, 11}, - {"R_RISCV_HI20", Const, 11}, - {"R_RISCV_JAL", Const, 11}, - {"R_RISCV_JUMP_SLOT", Const, 11}, - {"R_RISCV_LO12_I", Const, 11}, - {"R_RISCV_LO12_S", Const, 11}, - {"R_RISCV_NONE", Const, 11}, - {"R_RISCV_PCREL_HI20", Const, 11}, - {"R_RISCV_PCREL_LO12_I", Const, 11}, - {"R_RISCV_PCREL_LO12_S", Const, 11}, - {"R_RISCV_RELATIVE", Const, 11}, - {"R_RISCV_RELAX", Const, 11}, - {"R_RISCV_RVC_BRANCH", Const, 11}, - {"R_RISCV_RVC_JUMP", Const, 11}, - {"R_RISCV_RVC_LUI", Const, 11}, - {"R_RISCV_SET16", Const, 11}, - {"R_RISCV_SET32", Const, 11}, - {"R_RISCV_SET6", Const, 11}, - {"R_RISCV_SET8", Const, 11}, - {"R_RISCV_SUB16", Const, 11}, - {"R_RISCV_SUB32", Const, 11}, - {"R_RISCV_SUB6", Const, 11}, - {"R_RISCV_SUB64", Const, 11}, - {"R_RISCV_SUB8", Const, 11}, - {"R_RISCV_TLS_DTPMOD32", Const, 11}, - {"R_RISCV_TLS_DTPMOD64", Const, 11}, - {"R_RISCV_TLS_DTPREL32", Const, 11}, - {"R_RISCV_TLS_DTPREL64", Const, 11}, - {"R_RISCV_TLS_GD_HI20", Const, 11}, - {"R_RISCV_TLS_GOT_HI20", Const, 11}, - {"R_RISCV_TLS_TPREL32", Const, 11}, - {"R_RISCV_TLS_TPREL64", Const, 11}, - {"R_RISCV_TPREL_ADD", Const, 11}, - {"R_RISCV_TPREL_HI20", Const, 11}, - {"R_RISCV_TPREL_I", Const, 11}, - {"R_RISCV_TPREL_LO12_I", Const, 11}, - {"R_RISCV_TPREL_LO12_S", Const, 11}, - {"R_RISCV_TPREL_S", Const, 11}, - {"R_SPARC", Type, 0}, - {"R_SPARC_10", Const, 0}, - {"R_SPARC_11", Const, 0}, - {"R_SPARC_13", Const, 0}, - {"R_SPARC_16", Const, 0}, - {"R_SPARC_22", Const, 0}, - {"R_SPARC_32", Const, 0}, - {"R_SPARC_5", Const, 0}, - {"R_SPARC_6", Const, 0}, - {"R_SPARC_64", Const, 0}, - {"R_SPARC_7", Const, 0}, - {"R_SPARC_8", Const, 0}, - {"R_SPARC_COPY", Const, 0}, - {"R_SPARC_DISP16", Const, 0}, - {"R_SPARC_DISP32", Const, 0}, - {"R_SPARC_DISP64", Const, 0}, - {"R_SPARC_DISP8", Const, 0}, - {"R_SPARC_GLOB_DAT", Const, 0}, - {"R_SPARC_GLOB_JMP", Const, 0}, - {"R_SPARC_GOT10", Const, 0}, - {"R_SPARC_GOT13", Const, 0}, - {"R_SPARC_GOT22", Const, 0}, - {"R_SPARC_H44", Const, 0}, - {"R_SPARC_HH22", Const, 0}, - {"R_SPARC_HI22", Const, 0}, - {"R_SPARC_HIPLT22", Const, 0}, - {"R_SPARC_HIX22", Const, 0}, - {"R_SPARC_HM10", Const, 0}, - {"R_SPARC_JMP_SLOT", Const, 0}, - {"R_SPARC_L44", Const, 0}, - {"R_SPARC_LM22", Const, 0}, - {"R_SPARC_LO10", Const, 0}, - {"R_SPARC_LOPLT10", Const, 0}, - {"R_SPARC_LOX10", Const, 0}, - {"R_SPARC_M44", Const, 0}, - {"R_SPARC_NONE", Const, 0}, - {"R_SPARC_OLO10", Const, 0}, - {"R_SPARC_PC10", Const, 0}, - {"R_SPARC_PC22", Const, 0}, - {"R_SPARC_PCPLT10", Const, 0}, - {"R_SPARC_PCPLT22", Const, 0}, - {"R_SPARC_PCPLT32", Const, 0}, - {"R_SPARC_PC_HH22", Const, 0}, - {"R_SPARC_PC_HM10", Const, 0}, - {"R_SPARC_PC_LM22", Const, 0}, - {"R_SPARC_PLT32", Const, 0}, - {"R_SPARC_PLT64", Const, 0}, - {"R_SPARC_REGISTER", Const, 0}, - {"R_SPARC_RELATIVE", Const, 0}, - {"R_SPARC_UA16", Const, 0}, - {"R_SPARC_UA32", Const, 0}, - {"R_SPARC_UA64", Const, 0}, - {"R_SPARC_WDISP16", Const, 0}, - {"R_SPARC_WDISP19", Const, 0}, - {"R_SPARC_WDISP22", Const, 0}, - {"R_SPARC_WDISP30", Const, 0}, - {"R_SPARC_WPLT30", Const, 0}, - {"R_SYM32", Func, 0}, - {"R_SYM64", Func, 0}, - {"R_TYPE32", Func, 0}, - {"R_TYPE64", Func, 0}, - {"R_X86_64", Type, 0}, - {"R_X86_64_16", Const, 0}, - {"R_X86_64_32", Const, 0}, - {"R_X86_64_32S", Const, 0}, - {"R_X86_64_64", Const, 0}, - {"R_X86_64_8", Const, 0}, - {"R_X86_64_COPY", Const, 0}, - {"R_X86_64_DTPMOD64", Const, 0}, - {"R_X86_64_DTPOFF32", Const, 0}, - {"R_X86_64_DTPOFF64", Const, 0}, - {"R_X86_64_GLOB_DAT", Const, 0}, - {"R_X86_64_GOT32", Const, 0}, - {"R_X86_64_GOT64", Const, 10}, - {"R_X86_64_GOTOFF64", Const, 10}, - {"R_X86_64_GOTPC32", Const, 10}, - {"R_X86_64_GOTPC32_TLSDESC", Const, 10}, - {"R_X86_64_GOTPC64", Const, 10}, - {"R_X86_64_GOTPCREL", Const, 0}, - {"R_X86_64_GOTPCREL64", Const, 10}, - {"R_X86_64_GOTPCRELX", Const, 10}, - {"R_X86_64_GOTPLT64", Const, 10}, - {"R_X86_64_GOTTPOFF", Const, 0}, - {"R_X86_64_IRELATIVE", Const, 10}, - {"R_X86_64_JMP_SLOT", Const, 0}, - {"R_X86_64_NONE", Const, 0}, - {"R_X86_64_PC16", Const, 0}, - {"R_X86_64_PC32", Const, 0}, - {"R_X86_64_PC32_BND", Const, 10}, - {"R_X86_64_PC64", Const, 10}, - {"R_X86_64_PC8", Const, 0}, - {"R_X86_64_PLT32", Const, 0}, - {"R_X86_64_PLT32_BND", Const, 10}, - {"R_X86_64_PLTOFF64", Const, 10}, - {"R_X86_64_RELATIVE", Const, 0}, - {"R_X86_64_RELATIVE64", Const, 10}, - {"R_X86_64_REX_GOTPCRELX", Const, 10}, - {"R_X86_64_SIZE32", Const, 10}, - {"R_X86_64_SIZE64", Const, 10}, - {"R_X86_64_TLSDESC", Const, 10}, - {"R_X86_64_TLSDESC_CALL", Const, 10}, - {"R_X86_64_TLSGD", Const, 0}, - {"R_X86_64_TLSLD", Const, 0}, - {"R_X86_64_TPOFF32", Const, 0}, - {"R_X86_64_TPOFF64", Const, 0}, - {"Rel32", Type, 0}, - {"Rel32.Info", Field, 0}, - {"Rel32.Off", Field, 0}, - {"Rel64", Type, 0}, - {"Rel64.Info", Field, 0}, - {"Rel64.Off", Field, 0}, - {"Rela32", Type, 0}, - {"Rela32.Addend", Field, 0}, - {"Rela32.Info", Field, 0}, - {"Rela32.Off", Field, 0}, - {"Rela64", Type, 0}, - {"Rela64.Addend", Field, 0}, - {"Rela64.Info", Field, 0}, - {"Rela64.Off", Field, 0}, - {"SHF_ALLOC", Const, 0}, - {"SHF_COMPRESSED", Const, 6}, - {"SHF_EXECINSTR", Const, 0}, - {"SHF_GROUP", Const, 0}, - {"SHF_INFO_LINK", Const, 0}, - {"SHF_LINK_ORDER", Const, 0}, - {"SHF_MASKOS", Const, 0}, - {"SHF_MASKPROC", Const, 0}, - {"SHF_MERGE", Const, 0}, - {"SHF_OS_NONCONFORMING", Const, 0}, - {"SHF_STRINGS", Const, 0}, - {"SHF_TLS", Const, 0}, - {"SHF_WRITE", Const, 0}, - {"SHN_ABS", Const, 0}, - {"SHN_COMMON", Const, 0}, - {"SHN_HIOS", Const, 0}, - {"SHN_HIPROC", Const, 0}, - {"SHN_HIRESERVE", Const, 0}, - {"SHN_LOOS", Const, 0}, - {"SHN_LOPROC", Const, 0}, - {"SHN_LORESERVE", Const, 0}, - {"SHN_UNDEF", Const, 0}, - {"SHN_XINDEX", Const, 0}, - {"SHT_DYNAMIC", Const, 0}, - {"SHT_DYNSYM", Const, 0}, - {"SHT_FINI_ARRAY", Const, 0}, - {"SHT_GNU_ATTRIBUTES", Const, 0}, - {"SHT_GNU_HASH", Const, 0}, - {"SHT_GNU_LIBLIST", Const, 0}, - {"SHT_GNU_VERDEF", Const, 0}, - {"SHT_GNU_VERNEED", Const, 0}, - {"SHT_GNU_VERSYM", Const, 0}, - {"SHT_GROUP", Const, 0}, - {"SHT_HASH", Const, 0}, - {"SHT_HIOS", Const, 0}, - {"SHT_HIPROC", Const, 0}, - {"SHT_HIUSER", Const, 0}, - {"SHT_INIT_ARRAY", Const, 0}, - {"SHT_LOOS", Const, 0}, - {"SHT_LOPROC", Const, 0}, - {"SHT_LOUSER", Const, 0}, - {"SHT_MIPS_ABIFLAGS", Const, 17}, - {"SHT_NOBITS", Const, 0}, - {"SHT_NOTE", Const, 0}, - {"SHT_NULL", Const, 0}, - {"SHT_PREINIT_ARRAY", Const, 0}, - {"SHT_PROGBITS", Const, 0}, - {"SHT_REL", Const, 0}, - {"SHT_RELA", Const, 0}, - {"SHT_RISCV_ATTRIBUTES", Const, 25}, - {"SHT_SHLIB", Const, 0}, - {"SHT_STRTAB", Const, 0}, - {"SHT_SYMTAB", Const, 0}, - {"SHT_SYMTAB_SHNDX", Const, 0}, - {"STB_GLOBAL", Const, 0}, - {"STB_HIOS", Const, 0}, - {"STB_HIPROC", Const, 0}, - {"STB_LOCAL", Const, 0}, - {"STB_LOOS", Const, 0}, - {"STB_LOPROC", Const, 0}, - {"STB_WEAK", Const, 0}, - {"STT_COMMON", Const, 0}, - {"STT_FILE", Const, 0}, - {"STT_FUNC", Const, 0}, - {"STT_GNU_IFUNC", Const, 23}, - {"STT_HIOS", Const, 0}, - {"STT_HIPROC", Const, 0}, - {"STT_LOOS", Const, 0}, - {"STT_LOPROC", Const, 0}, - {"STT_NOTYPE", Const, 0}, - {"STT_OBJECT", Const, 0}, - {"STT_RELC", Const, 23}, - {"STT_SECTION", Const, 0}, - {"STT_SRELC", Const, 23}, - {"STT_TLS", Const, 0}, - {"STV_DEFAULT", Const, 0}, - {"STV_HIDDEN", Const, 0}, - {"STV_INTERNAL", Const, 0}, - {"STV_PROTECTED", Const, 0}, - {"ST_BIND", Func, 0}, - {"ST_INFO", Func, 0}, - {"ST_TYPE", Func, 0}, - {"ST_VISIBILITY", Func, 0}, - {"Section", Type, 0}, - {"Section.ReaderAt", Field, 0}, - {"Section.SectionHeader", Field, 0}, - {"Section32", Type, 0}, - {"Section32.Addr", Field, 0}, - {"Section32.Addralign", Field, 0}, - {"Section32.Entsize", Field, 0}, - {"Section32.Flags", Field, 0}, - {"Section32.Info", Field, 0}, - {"Section32.Link", Field, 0}, - {"Section32.Name", Field, 0}, - {"Section32.Off", Field, 0}, - {"Section32.Size", Field, 0}, - {"Section32.Type", Field, 0}, - {"Section64", Type, 0}, - {"Section64.Addr", Field, 0}, - {"Section64.Addralign", Field, 0}, - {"Section64.Entsize", Field, 0}, - {"Section64.Flags", Field, 0}, - {"Section64.Info", Field, 0}, - {"Section64.Link", Field, 0}, - {"Section64.Name", Field, 0}, - {"Section64.Off", Field, 0}, - {"Section64.Size", Field, 0}, - {"Section64.Type", Field, 0}, - {"SectionFlag", Type, 0}, - {"SectionHeader", Type, 0}, - {"SectionHeader.Addr", Field, 0}, - {"SectionHeader.Addralign", Field, 0}, - {"SectionHeader.Entsize", Field, 0}, - {"SectionHeader.FileSize", Field, 6}, - {"SectionHeader.Flags", Field, 0}, - {"SectionHeader.Info", Field, 0}, - {"SectionHeader.Link", Field, 0}, - {"SectionHeader.Name", Field, 0}, - {"SectionHeader.Offset", Field, 0}, - {"SectionHeader.Size", Field, 0}, - {"SectionHeader.Type", Field, 0}, - {"SectionIndex", Type, 0}, - {"SectionType", Type, 0}, - {"Sym32", Type, 0}, - {"Sym32.Info", Field, 0}, - {"Sym32.Name", Field, 0}, - {"Sym32.Other", Field, 0}, - {"Sym32.Shndx", Field, 0}, - {"Sym32.Size", Field, 0}, - {"Sym32.Value", Field, 0}, - {"Sym32Size", Const, 0}, - {"Sym64", Type, 0}, - {"Sym64.Info", Field, 0}, - {"Sym64.Name", Field, 0}, - {"Sym64.Other", Field, 0}, - {"Sym64.Shndx", Field, 0}, - {"Sym64.Size", Field, 0}, - {"Sym64.Value", Field, 0}, - {"Sym64Size", Const, 0}, - {"SymBind", Type, 0}, - {"SymType", Type, 0}, - {"SymVis", Type, 0}, - {"Symbol", Type, 0}, - {"Symbol.HasVersion", Field, 24}, - {"Symbol.Info", Field, 0}, - {"Symbol.Library", Field, 13}, - {"Symbol.Name", Field, 0}, - {"Symbol.Other", Field, 0}, - {"Symbol.Section", Field, 0}, - {"Symbol.Size", Field, 0}, - {"Symbol.Value", Field, 0}, - {"Symbol.Version", Field, 13}, - {"Symbol.VersionIndex", Field, 24}, - {"Type", Type, 0}, - {"VER_FLG_BASE", Const, 24}, - {"VER_FLG_INFO", Const, 24}, - {"VER_FLG_WEAK", Const, 24}, - {"Version", Type, 0}, - {"VersionIndex", Type, 24}, + {"(*File).Close", Method, 0, ""}, + {"(*File).DWARF", Method, 0, ""}, + {"(*File).DynString", Method, 1, ""}, + {"(*File).DynValue", Method, 21, ""}, + {"(*File).DynamicSymbols", Method, 4, ""}, + {"(*File).DynamicVersionNeeds", Method, 24, ""}, + {"(*File).DynamicVersions", Method, 24, ""}, + {"(*File).ImportedLibraries", Method, 0, ""}, + {"(*File).ImportedSymbols", Method, 0, ""}, + {"(*File).Section", Method, 0, ""}, + {"(*File).SectionByType", Method, 0, ""}, + {"(*File).Symbols", Method, 0, ""}, + {"(*FormatError).Error", Method, 0, ""}, + {"(*Prog).Open", Method, 0, ""}, + {"(*Section).Data", Method, 0, ""}, + {"(*Section).Open", Method, 0, ""}, + {"(Class).GoString", Method, 0, ""}, + {"(Class).String", Method, 0, ""}, + {"(CompressionType).GoString", Method, 6, ""}, + {"(CompressionType).String", Method, 6, ""}, + {"(Data).GoString", Method, 0, ""}, + {"(Data).String", Method, 0, ""}, + {"(DynFlag).GoString", Method, 0, ""}, + {"(DynFlag).String", Method, 0, ""}, + {"(DynFlag1).GoString", Method, 21, ""}, + {"(DynFlag1).String", Method, 21, ""}, + {"(DynTag).GoString", Method, 0, ""}, + {"(DynTag).String", Method, 0, ""}, + {"(Machine).GoString", Method, 0, ""}, + {"(Machine).String", Method, 0, ""}, + {"(NType).GoString", Method, 0, ""}, + {"(NType).String", Method, 0, ""}, + {"(OSABI).GoString", Method, 0, ""}, + {"(OSABI).String", Method, 0, ""}, + {"(Prog).ReadAt", Method, 0, ""}, + {"(ProgFlag).GoString", Method, 0, ""}, + {"(ProgFlag).String", Method, 0, ""}, + {"(ProgType).GoString", Method, 0, ""}, + {"(ProgType).String", Method, 0, ""}, + {"(R_386).GoString", Method, 0, ""}, + {"(R_386).String", Method, 0, ""}, + {"(R_390).GoString", Method, 7, ""}, + {"(R_390).String", Method, 7, ""}, + {"(R_AARCH64).GoString", Method, 4, ""}, + {"(R_AARCH64).String", Method, 4, ""}, + {"(R_ALPHA).GoString", Method, 0, ""}, + {"(R_ALPHA).String", Method, 0, ""}, + {"(R_ARM).GoString", Method, 0, ""}, + {"(R_ARM).String", Method, 0, ""}, + {"(R_LARCH).GoString", Method, 19, ""}, + {"(R_LARCH).String", Method, 19, ""}, + {"(R_MIPS).GoString", Method, 6, ""}, + {"(R_MIPS).String", Method, 6, ""}, + {"(R_PPC).GoString", Method, 0, ""}, + {"(R_PPC).String", Method, 0, ""}, + {"(R_PPC64).GoString", Method, 5, ""}, + {"(R_PPC64).String", Method, 5, ""}, + {"(R_RISCV).GoString", Method, 11, ""}, + {"(R_RISCV).String", Method, 11, ""}, + {"(R_SPARC).GoString", Method, 0, ""}, + {"(R_SPARC).String", Method, 0, ""}, + {"(R_X86_64).GoString", Method, 0, ""}, + {"(R_X86_64).String", Method, 0, ""}, + {"(Section).ReadAt", Method, 0, ""}, + {"(SectionFlag).GoString", Method, 0, ""}, + {"(SectionFlag).String", Method, 0, ""}, + {"(SectionIndex).GoString", Method, 0, ""}, + {"(SectionIndex).String", Method, 0, ""}, + {"(SectionType).GoString", Method, 0, ""}, + {"(SectionType).String", Method, 0, ""}, + {"(SymBind).GoString", Method, 0, ""}, + {"(SymBind).String", Method, 0, ""}, + {"(SymType).GoString", Method, 0, ""}, + {"(SymType).String", Method, 0, ""}, + {"(SymVis).GoString", Method, 0, ""}, + {"(SymVis).String", Method, 0, ""}, + {"(Type).GoString", Method, 0, ""}, + {"(Type).String", Method, 0, ""}, + {"(Version).GoString", Method, 0, ""}, + {"(Version).String", Method, 0, ""}, + {"(VersionIndex).Index", Method, 24, ""}, + {"(VersionIndex).IsHidden", Method, 24, ""}, + {"ARM_MAGIC_TRAMP_NUMBER", Const, 0, ""}, + {"COMPRESS_HIOS", Const, 6, ""}, + {"COMPRESS_HIPROC", Const, 6, ""}, + {"COMPRESS_LOOS", Const, 6, ""}, + {"COMPRESS_LOPROC", Const, 6, ""}, + {"COMPRESS_ZLIB", Const, 6, ""}, + {"COMPRESS_ZSTD", Const, 21, ""}, + {"Chdr32", Type, 6, ""}, + {"Chdr32.Addralign", Field, 6, ""}, + {"Chdr32.Size", Field, 6, ""}, + {"Chdr32.Type", Field, 6, ""}, + {"Chdr64", Type, 6, ""}, + {"Chdr64.Addralign", Field, 6, ""}, + {"Chdr64.Size", Field, 6, ""}, + {"Chdr64.Type", Field, 6, ""}, + {"Class", Type, 0, ""}, + {"CompressionType", Type, 6, ""}, + {"DF_1_CONFALT", Const, 21, ""}, + {"DF_1_DIRECT", Const, 21, ""}, + {"DF_1_DISPRELDNE", Const, 21, ""}, + {"DF_1_DISPRELPND", Const, 21, ""}, + {"DF_1_EDITED", Const, 21, ""}, + {"DF_1_ENDFILTEE", Const, 21, ""}, + {"DF_1_GLOBAL", Const, 21, ""}, + {"DF_1_GLOBAUDIT", Const, 21, ""}, + {"DF_1_GROUP", Const, 21, ""}, + {"DF_1_IGNMULDEF", Const, 21, ""}, + {"DF_1_INITFIRST", Const, 21, ""}, + {"DF_1_INTERPOSE", Const, 21, ""}, + {"DF_1_KMOD", Const, 21, ""}, + {"DF_1_LOADFLTR", Const, 21, ""}, + {"DF_1_NOCOMMON", Const, 21, ""}, + {"DF_1_NODEFLIB", Const, 21, ""}, + {"DF_1_NODELETE", Const, 21, ""}, + {"DF_1_NODIRECT", Const, 21, ""}, + {"DF_1_NODUMP", Const, 21, ""}, + {"DF_1_NOHDR", Const, 21, ""}, + {"DF_1_NOKSYMS", Const, 21, ""}, + {"DF_1_NOOPEN", Const, 21, ""}, + {"DF_1_NORELOC", Const, 21, ""}, + {"DF_1_NOW", Const, 21, ""}, + {"DF_1_ORIGIN", Const, 21, ""}, + {"DF_1_PIE", Const, 21, ""}, + {"DF_1_SINGLETON", Const, 21, ""}, + {"DF_1_STUB", Const, 21, ""}, + {"DF_1_SYMINTPOSE", Const, 21, ""}, + {"DF_1_TRANS", Const, 21, ""}, + {"DF_1_WEAKFILTER", Const, 21, ""}, + {"DF_BIND_NOW", Const, 0, ""}, + {"DF_ORIGIN", Const, 0, ""}, + {"DF_STATIC_TLS", Const, 0, ""}, + {"DF_SYMBOLIC", Const, 0, ""}, + {"DF_TEXTREL", Const, 0, ""}, + {"DT_ADDRRNGHI", Const, 16, ""}, + {"DT_ADDRRNGLO", Const, 16, ""}, + {"DT_AUDIT", Const, 16, ""}, + {"DT_AUXILIARY", Const, 16, ""}, + {"DT_BIND_NOW", Const, 0, ""}, + {"DT_CHECKSUM", Const, 16, ""}, + {"DT_CONFIG", Const, 16, ""}, + {"DT_DEBUG", Const, 0, ""}, + {"DT_DEPAUDIT", Const, 16, ""}, + {"DT_ENCODING", Const, 0, ""}, + {"DT_FEATURE", Const, 16, ""}, + {"DT_FILTER", Const, 16, ""}, + {"DT_FINI", Const, 0, ""}, + {"DT_FINI_ARRAY", Const, 0, ""}, + {"DT_FINI_ARRAYSZ", Const, 0, ""}, + {"DT_FLAGS", Const, 0, ""}, + {"DT_FLAGS_1", Const, 16, ""}, + {"DT_GNU_CONFLICT", Const, 16, ""}, + {"DT_GNU_CONFLICTSZ", Const, 16, ""}, + {"DT_GNU_HASH", Const, 16, ""}, + {"DT_GNU_LIBLIST", Const, 16, ""}, + {"DT_GNU_LIBLISTSZ", Const, 16, ""}, + {"DT_GNU_PRELINKED", Const, 16, ""}, + {"DT_HASH", Const, 0, ""}, + {"DT_HIOS", Const, 0, ""}, + {"DT_HIPROC", Const, 0, ""}, + {"DT_INIT", Const, 0, ""}, + {"DT_INIT_ARRAY", Const, 0, ""}, + {"DT_INIT_ARRAYSZ", Const, 0, ""}, + {"DT_JMPREL", Const, 0, ""}, + {"DT_LOOS", Const, 0, ""}, + {"DT_LOPROC", Const, 0, ""}, + {"DT_MIPS_AUX_DYNAMIC", Const, 16, ""}, + {"DT_MIPS_BASE_ADDRESS", Const, 16, ""}, + {"DT_MIPS_COMPACT_SIZE", Const, 16, ""}, + {"DT_MIPS_CONFLICT", Const, 16, ""}, + {"DT_MIPS_CONFLICTNO", Const, 16, ""}, + {"DT_MIPS_CXX_FLAGS", Const, 16, ""}, + {"DT_MIPS_DELTA_CLASS", Const, 16, ""}, + {"DT_MIPS_DELTA_CLASSSYM", Const, 16, ""}, + {"DT_MIPS_DELTA_CLASSSYM_NO", Const, 16, ""}, + {"DT_MIPS_DELTA_CLASS_NO", Const, 16, ""}, + {"DT_MIPS_DELTA_INSTANCE", Const, 16, ""}, + {"DT_MIPS_DELTA_INSTANCE_NO", Const, 16, ""}, + {"DT_MIPS_DELTA_RELOC", Const, 16, ""}, + {"DT_MIPS_DELTA_RELOC_NO", Const, 16, ""}, + {"DT_MIPS_DELTA_SYM", Const, 16, ""}, + {"DT_MIPS_DELTA_SYM_NO", Const, 16, ""}, + {"DT_MIPS_DYNSTR_ALIGN", Const, 16, ""}, + {"DT_MIPS_FLAGS", Const, 16, ""}, + {"DT_MIPS_GOTSYM", Const, 16, ""}, + {"DT_MIPS_GP_VALUE", Const, 16, ""}, + {"DT_MIPS_HIDDEN_GOTIDX", Const, 16, ""}, + {"DT_MIPS_HIPAGENO", Const, 16, ""}, + {"DT_MIPS_ICHECKSUM", Const, 16, ""}, + {"DT_MIPS_INTERFACE", Const, 16, ""}, + {"DT_MIPS_INTERFACE_SIZE", Const, 16, ""}, + {"DT_MIPS_IVERSION", Const, 16, ""}, + {"DT_MIPS_LIBLIST", Const, 16, ""}, + {"DT_MIPS_LIBLISTNO", Const, 16, ""}, + {"DT_MIPS_LOCALPAGE_GOTIDX", Const, 16, ""}, + {"DT_MIPS_LOCAL_GOTIDX", Const, 16, ""}, + {"DT_MIPS_LOCAL_GOTNO", Const, 16, ""}, + {"DT_MIPS_MSYM", Const, 16, ""}, + {"DT_MIPS_OPTIONS", Const, 16, ""}, + {"DT_MIPS_PERF_SUFFIX", Const, 16, ""}, + {"DT_MIPS_PIXIE_INIT", Const, 16, ""}, + {"DT_MIPS_PLTGOT", Const, 16, ""}, + {"DT_MIPS_PROTECTED_GOTIDX", Const, 16, ""}, + {"DT_MIPS_RLD_MAP", Const, 16, ""}, + {"DT_MIPS_RLD_MAP_REL", Const, 16, ""}, + {"DT_MIPS_RLD_TEXT_RESOLVE_ADDR", Const, 16, ""}, + {"DT_MIPS_RLD_VERSION", Const, 16, ""}, + {"DT_MIPS_RWPLT", Const, 16, ""}, + {"DT_MIPS_SYMBOL_LIB", Const, 16, ""}, + {"DT_MIPS_SYMTABNO", Const, 16, ""}, + {"DT_MIPS_TIME_STAMP", Const, 16, ""}, + {"DT_MIPS_UNREFEXTNO", Const, 16, ""}, + {"DT_MOVEENT", Const, 16, ""}, + {"DT_MOVESZ", Const, 16, ""}, + {"DT_MOVETAB", Const, 16, ""}, + {"DT_NEEDED", Const, 0, ""}, + {"DT_NULL", Const, 0, ""}, + {"DT_PLTGOT", Const, 0, ""}, + {"DT_PLTPAD", Const, 16, ""}, + {"DT_PLTPADSZ", Const, 16, ""}, + {"DT_PLTREL", Const, 0, ""}, + {"DT_PLTRELSZ", Const, 0, ""}, + {"DT_POSFLAG_1", Const, 16, ""}, + {"DT_PPC64_GLINK", Const, 16, ""}, + {"DT_PPC64_OPD", Const, 16, ""}, + {"DT_PPC64_OPDSZ", Const, 16, ""}, + {"DT_PPC64_OPT", Const, 16, ""}, + {"DT_PPC_GOT", Const, 16, ""}, + {"DT_PPC_OPT", Const, 16, ""}, + {"DT_PREINIT_ARRAY", Const, 0, ""}, + {"DT_PREINIT_ARRAYSZ", Const, 0, ""}, + {"DT_REL", Const, 0, ""}, + {"DT_RELA", Const, 0, ""}, + {"DT_RELACOUNT", Const, 16, ""}, + {"DT_RELAENT", Const, 0, ""}, + {"DT_RELASZ", Const, 0, ""}, + {"DT_RELCOUNT", Const, 16, ""}, + {"DT_RELENT", Const, 0, ""}, + {"DT_RELSZ", Const, 0, ""}, + {"DT_RPATH", Const, 0, ""}, + {"DT_RUNPATH", Const, 0, ""}, + {"DT_SONAME", Const, 0, ""}, + {"DT_SPARC_REGISTER", Const, 16, ""}, + {"DT_STRSZ", Const, 0, ""}, + {"DT_STRTAB", Const, 0, ""}, + {"DT_SYMBOLIC", Const, 0, ""}, + {"DT_SYMENT", Const, 0, ""}, + {"DT_SYMINENT", Const, 16, ""}, + {"DT_SYMINFO", Const, 16, ""}, + {"DT_SYMINSZ", Const, 16, ""}, + {"DT_SYMTAB", Const, 0, ""}, + {"DT_SYMTAB_SHNDX", Const, 16, ""}, + {"DT_TEXTREL", Const, 0, ""}, + {"DT_TLSDESC_GOT", Const, 16, ""}, + {"DT_TLSDESC_PLT", Const, 16, ""}, + {"DT_USED", Const, 16, ""}, + {"DT_VALRNGHI", Const, 16, ""}, + {"DT_VALRNGLO", Const, 16, ""}, + {"DT_VERDEF", Const, 16, ""}, + {"DT_VERDEFNUM", Const, 16, ""}, + {"DT_VERNEED", Const, 0, ""}, + {"DT_VERNEEDNUM", Const, 0, ""}, + {"DT_VERSYM", Const, 0, ""}, + {"Data", Type, 0, ""}, + {"Dyn32", Type, 0, ""}, + {"Dyn32.Tag", Field, 0, ""}, + {"Dyn32.Val", Field, 0, ""}, + {"Dyn64", Type, 0, ""}, + {"Dyn64.Tag", Field, 0, ""}, + {"Dyn64.Val", Field, 0, ""}, + {"DynFlag", Type, 0, ""}, + {"DynFlag1", Type, 21, ""}, + {"DynTag", Type, 0, ""}, + {"DynamicVersion", Type, 24, ""}, + {"DynamicVersion.Deps", Field, 24, ""}, + {"DynamicVersion.Flags", Field, 24, ""}, + {"DynamicVersion.Index", Field, 24, ""}, + {"DynamicVersion.Name", Field, 24, ""}, + {"DynamicVersionDep", Type, 24, ""}, + {"DynamicVersionDep.Dep", Field, 24, ""}, + {"DynamicVersionDep.Flags", Field, 24, ""}, + {"DynamicVersionDep.Index", Field, 24, ""}, + {"DynamicVersionFlag", Type, 24, ""}, + {"DynamicVersionNeed", Type, 24, ""}, + {"DynamicVersionNeed.Name", Field, 24, ""}, + {"DynamicVersionNeed.Needs", Field, 24, ""}, + {"EI_ABIVERSION", Const, 0, ""}, + {"EI_CLASS", Const, 0, ""}, + {"EI_DATA", Const, 0, ""}, + {"EI_NIDENT", Const, 0, ""}, + {"EI_OSABI", Const, 0, ""}, + {"EI_PAD", Const, 0, ""}, + {"EI_VERSION", Const, 0, ""}, + {"ELFCLASS32", Const, 0, ""}, + {"ELFCLASS64", Const, 0, ""}, + {"ELFCLASSNONE", Const, 0, ""}, + {"ELFDATA2LSB", Const, 0, ""}, + {"ELFDATA2MSB", Const, 0, ""}, + {"ELFDATANONE", Const, 0, ""}, + {"ELFMAG", Const, 0, ""}, + {"ELFOSABI_86OPEN", Const, 0, ""}, + {"ELFOSABI_AIX", Const, 0, ""}, + {"ELFOSABI_ARM", Const, 0, ""}, + {"ELFOSABI_AROS", Const, 11, ""}, + {"ELFOSABI_CLOUDABI", Const, 11, ""}, + {"ELFOSABI_FENIXOS", Const, 11, ""}, + {"ELFOSABI_FREEBSD", Const, 0, ""}, + {"ELFOSABI_HPUX", Const, 0, ""}, + {"ELFOSABI_HURD", Const, 0, ""}, + {"ELFOSABI_IRIX", Const, 0, ""}, + {"ELFOSABI_LINUX", Const, 0, ""}, + {"ELFOSABI_MODESTO", Const, 0, ""}, + {"ELFOSABI_NETBSD", Const, 0, ""}, + {"ELFOSABI_NONE", Const, 0, ""}, + {"ELFOSABI_NSK", Const, 0, ""}, + {"ELFOSABI_OPENBSD", Const, 0, ""}, + {"ELFOSABI_OPENVMS", Const, 0, ""}, + {"ELFOSABI_SOLARIS", Const, 0, ""}, + {"ELFOSABI_STANDALONE", Const, 0, ""}, + {"ELFOSABI_TRU64", Const, 0, ""}, + {"EM_386", Const, 0, ""}, + {"EM_486", Const, 0, ""}, + {"EM_56800EX", Const, 11, ""}, + {"EM_68HC05", Const, 11, ""}, + {"EM_68HC08", Const, 11, ""}, + {"EM_68HC11", Const, 11, ""}, + {"EM_68HC12", Const, 0, ""}, + {"EM_68HC16", Const, 11, ""}, + {"EM_68K", Const, 0, ""}, + {"EM_78KOR", Const, 11, ""}, + {"EM_8051", Const, 11, ""}, + {"EM_860", Const, 0, ""}, + {"EM_88K", Const, 0, ""}, + {"EM_960", Const, 0, ""}, + {"EM_AARCH64", Const, 4, ""}, + {"EM_ALPHA", Const, 0, ""}, + {"EM_ALPHA_STD", Const, 0, ""}, + {"EM_ALTERA_NIOS2", Const, 11, ""}, + {"EM_AMDGPU", Const, 11, ""}, + {"EM_ARC", Const, 0, ""}, + {"EM_ARCA", Const, 11, ""}, + {"EM_ARC_COMPACT", Const, 11, ""}, + {"EM_ARC_COMPACT2", Const, 11, ""}, + {"EM_ARM", Const, 0, ""}, + {"EM_AVR", Const, 11, ""}, + {"EM_AVR32", Const, 11, ""}, + {"EM_BA1", Const, 11, ""}, + {"EM_BA2", Const, 11, ""}, + {"EM_BLACKFIN", Const, 11, ""}, + {"EM_BPF", Const, 11, ""}, + {"EM_C166", Const, 11, ""}, + {"EM_CDP", Const, 11, ""}, + {"EM_CE", Const, 11, ""}, + {"EM_CLOUDSHIELD", Const, 11, ""}, + {"EM_COGE", Const, 11, ""}, + {"EM_COLDFIRE", Const, 0, ""}, + {"EM_COOL", Const, 11, ""}, + {"EM_COREA_1ST", Const, 11, ""}, + {"EM_COREA_2ND", Const, 11, ""}, + {"EM_CR", Const, 11, ""}, + {"EM_CR16", Const, 11, ""}, + {"EM_CRAYNV2", Const, 11, ""}, + {"EM_CRIS", Const, 11, ""}, + {"EM_CRX", Const, 11, ""}, + {"EM_CSR_KALIMBA", Const, 11, ""}, + {"EM_CUDA", Const, 11, ""}, + {"EM_CYPRESS_M8C", Const, 11, ""}, + {"EM_D10V", Const, 11, ""}, + {"EM_D30V", Const, 11, ""}, + {"EM_DSP24", Const, 11, ""}, + {"EM_DSPIC30F", Const, 11, ""}, + {"EM_DXP", Const, 11, ""}, + {"EM_ECOG1", Const, 11, ""}, + {"EM_ECOG16", Const, 11, ""}, + {"EM_ECOG1X", Const, 11, ""}, + {"EM_ECOG2", Const, 11, ""}, + {"EM_ETPU", Const, 11, ""}, + {"EM_EXCESS", Const, 11, ""}, + {"EM_F2MC16", Const, 11, ""}, + {"EM_FIREPATH", Const, 11, ""}, + {"EM_FR20", Const, 0, ""}, + {"EM_FR30", Const, 11, ""}, + {"EM_FT32", Const, 11, ""}, + {"EM_FX66", Const, 11, ""}, + {"EM_H8S", Const, 0, ""}, + {"EM_H8_300", Const, 0, ""}, + {"EM_H8_300H", Const, 0, ""}, + {"EM_H8_500", Const, 0, ""}, + {"EM_HUANY", Const, 11, ""}, + {"EM_IA_64", Const, 0, ""}, + {"EM_INTEL205", Const, 11, ""}, + {"EM_INTEL206", Const, 11, ""}, + {"EM_INTEL207", Const, 11, ""}, + {"EM_INTEL208", Const, 11, ""}, + {"EM_INTEL209", Const, 11, ""}, + {"EM_IP2K", Const, 11, ""}, + {"EM_JAVELIN", Const, 11, ""}, + {"EM_K10M", Const, 11, ""}, + {"EM_KM32", Const, 11, ""}, + {"EM_KMX16", Const, 11, ""}, + {"EM_KMX32", Const, 11, ""}, + {"EM_KMX8", Const, 11, ""}, + {"EM_KVARC", Const, 11, ""}, + {"EM_L10M", Const, 11, ""}, + {"EM_LANAI", Const, 11, ""}, + {"EM_LATTICEMICO32", Const, 11, ""}, + {"EM_LOONGARCH", Const, 19, ""}, + {"EM_M16C", Const, 11, ""}, + {"EM_M32", Const, 0, ""}, + {"EM_M32C", Const, 11, ""}, + {"EM_M32R", Const, 11, ""}, + {"EM_MANIK", Const, 11, ""}, + {"EM_MAX", Const, 11, ""}, + {"EM_MAXQ30", Const, 11, ""}, + {"EM_MCHP_PIC", Const, 11, ""}, + {"EM_MCST_ELBRUS", Const, 11, ""}, + {"EM_ME16", Const, 0, ""}, + {"EM_METAG", Const, 11, ""}, + {"EM_MICROBLAZE", Const, 11, ""}, + {"EM_MIPS", Const, 0, ""}, + {"EM_MIPS_RS3_LE", Const, 0, ""}, + {"EM_MIPS_RS4_BE", Const, 0, ""}, + {"EM_MIPS_X", Const, 0, ""}, + {"EM_MMA", Const, 0, ""}, + {"EM_MMDSP_PLUS", Const, 11, ""}, + {"EM_MMIX", Const, 11, ""}, + {"EM_MN10200", Const, 11, ""}, + {"EM_MN10300", Const, 11, ""}, + {"EM_MOXIE", Const, 11, ""}, + {"EM_MSP430", Const, 11, ""}, + {"EM_NCPU", Const, 0, ""}, + {"EM_NDR1", Const, 0, ""}, + {"EM_NDS32", Const, 11, ""}, + {"EM_NONE", Const, 0, ""}, + {"EM_NORC", Const, 11, ""}, + {"EM_NS32K", Const, 11, ""}, + {"EM_OPEN8", Const, 11, ""}, + {"EM_OPENRISC", Const, 11, ""}, + {"EM_PARISC", Const, 0, ""}, + {"EM_PCP", Const, 0, ""}, + {"EM_PDP10", Const, 11, ""}, + {"EM_PDP11", Const, 11, ""}, + {"EM_PDSP", Const, 11, ""}, + {"EM_PJ", Const, 11, ""}, + {"EM_PPC", Const, 0, ""}, + {"EM_PPC64", Const, 0, ""}, + {"EM_PRISM", Const, 11, ""}, + {"EM_QDSP6", Const, 11, ""}, + {"EM_R32C", Const, 11, ""}, + {"EM_RCE", Const, 0, ""}, + {"EM_RH32", Const, 0, ""}, + {"EM_RISCV", Const, 11, ""}, + {"EM_RL78", Const, 11, ""}, + {"EM_RS08", Const, 11, ""}, + {"EM_RX", Const, 11, ""}, + {"EM_S370", Const, 0, ""}, + {"EM_S390", Const, 0, ""}, + {"EM_SCORE7", Const, 11, ""}, + {"EM_SEP", Const, 11, ""}, + {"EM_SE_C17", Const, 11, ""}, + {"EM_SE_C33", Const, 11, ""}, + {"EM_SH", Const, 0, ""}, + {"EM_SHARC", Const, 11, ""}, + {"EM_SLE9X", Const, 11, ""}, + {"EM_SNP1K", Const, 11, ""}, + {"EM_SPARC", Const, 0, ""}, + {"EM_SPARC32PLUS", Const, 0, ""}, + {"EM_SPARCV9", Const, 0, ""}, + {"EM_ST100", Const, 0, ""}, + {"EM_ST19", Const, 11, ""}, + {"EM_ST200", Const, 11, ""}, + {"EM_ST7", Const, 11, ""}, + {"EM_ST9PLUS", Const, 11, ""}, + {"EM_STARCORE", Const, 0, ""}, + {"EM_STM8", Const, 11, ""}, + {"EM_STXP7X", Const, 11, ""}, + {"EM_SVX", Const, 11, ""}, + {"EM_TILE64", Const, 11, ""}, + {"EM_TILEGX", Const, 11, ""}, + {"EM_TILEPRO", Const, 11, ""}, + {"EM_TINYJ", Const, 0, ""}, + {"EM_TI_ARP32", Const, 11, ""}, + {"EM_TI_C2000", Const, 11, ""}, + {"EM_TI_C5500", Const, 11, ""}, + {"EM_TI_C6000", Const, 11, ""}, + {"EM_TI_PRU", Const, 11, ""}, + {"EM_TMM_GPP", Const, 11, ""}, + {"EM_TPC", Const, 11, ""}, + {"EM_TRICORE", Const, 0, ""}, + {"EM_TRIMEDIA", Const, 11, ""}, + {"EM_TSK3000", Const, 11, ""}, + {"EM_UNICORE", Const, 11, ""}, + {"EM_V800", Const, 0, ""}, + {"EM_V850", Const, 11, ""}, + {"EM_VAX", Const, 11, ""}, + {"EM_VIDEOCORE", Const, 11, ""}, + {"EM_VIDEOCORE3", Const, 11, ""}, + {"EM_VIDEOCORE5", Const, 11, ""}, + {"EM_VISIUM", Const, 11, ""}, + {"EM_VPP500", Const, 0, ""}, + {"EM_X86_64", Const, 0, ""}, + {"EM_XCORE", Const, 11, ""}, + {"EM_XGATE", Const, 11, ""}, + {"EM_XIMO16", Const, 11, ""}, + {"EM_XTENSA", Const, 11, ""}, + {"EM_Z80", Const, 11, ""}, + {"EM_ZSP", Const, 11, ""}, + {"ET_CORE", Const, 0, ""}, + {"ET_DYN", Const, 0, ""}, + {"ET_EXEC", Const, 0, ""}, + {"ET_HIOS", Const, 0, ""}, + {"ET_HIPROC", Const, 0, ""}, + {"ET_LOOS", Const, 0, ""}, + {"ET_LOPROC", Const, 0, ""}, + {"ET_NONE", Const, 0, ""}, + {"ET_REL", Const, 0, ""}, + {"EV_CURRENT", Const, 0, ""}, + {"EV_NONE", Const, 0, ""}, + {"ErrNoSymbols", Var, 4, ""}, + {"File", Type, 0, ""}, + {"File.FileHeader", Field, 0, ""}, + {"File.Progs", Field, 0, ""}, + {"File.Sections", Field, 0, ""}, + {"FileHeader", Type, 0, ""}, + {"FileHeader.ABIVersion", Field, 0, ""}, + {"FileHeader.ByteOrder", Field, 0, ""}, + {"FileHeader.Class", Field, 0, ""}, + {"FileHeader.Data", Field, 0, ""}, + {"FileHeader.Entry", Field, 1, ""}, + {"FileHeader.Machine", Field, 0, ""}, + {"FileHeader.OSABI", Field, 0, ""}, + {"FileHeader.Type", Field, 0, ""}, + {"FileHeader.Version", Field, 0, ""}, + {"FormatError", Type, 0, ""}, + {"Header32", Type, 0, ""}, + {"Header32.Ehsize", Field, 0, ""}, + {"Header32.Entry", Field, 0, ""}, + {"Header32.Flags", Field, 0, ""}, + {"Header32.Ident", Field, 0, ""}, + {"Header32.Machine", Field, 0, ""}, + {"Header32.Phentsize", Field, 0, ""}, + {"Header32.Phnum", Field, 0, ""}, + {"Header32.Phoff", Field, 0, ""}, + {"Header32.Shentsize", Field, 0, ""}, + {"Header32.Shnum", Field, 0, ""}, + {"Header32.Shoff", Field, 0, ""}, + {"Header32.Shstrndx", Field, 0, ""}, + {"Header32.Type", Field, 0, ""}, + {"Header32.Version", Field, 0, ""}, + {"Header64", Type, 0, ""}, + {"Header64.Ehsize", Field, 0, ""}, + {"Header64.Entry", Field, 0, ""}, + {"Header64.Flags", Field, 0, ""}, + {"Header64.Ident", Field, 0, ""}, + {"Header64.Machine", Field, 0, ""}, + {"Header64.Phentsize", Field, 0, ""}, + {"Header64.Phnum", Field, 0, ""}, + {"Header64.Phoff", Field, 0, ""}, + {"Header64.Shentsize", Field, 0, ""}, + {"Header64.Shnum", Field, 0, ""}, + {"Header64.Shoff", Field, 0, ""}, + {"Header64.Shstrndx", Field, 0, ""}, + {"Header64.Type", Field, 0, ""}, + {"Header64.Version", Field, 0, ""}, + {"ImportedSymbol", Type, 0, ""}, + {"ImportedSymbol.Library", Field, 0, ""}, + {"ImportedSymbol.Name", Field, 0, ""}, + {"ImportedSymbol.Version", Field, 0, ""}, + {"Machine", Type, 0, ""}, + {"NT_FPREGSET", Const, 0, ""}, + {"NT_PRPSINFO", Const, 0, ""}, + {"NT_PRSTATUS", Const, 0, ""}, + {"NType", Type, 0, ""}, + {"NewFile", Func, 0, "func(r io.ReaderAt) (*File, error)"}, + {"OSABI", Type, 0, ""}, + {"Open", Func, 0, "func(name string) (*File, error)"}, + {"PF_MASKOS", Const, 0, ""}, + {"PF_MASKPROC", Const, 0, ""}, + {"PF_R", Const, 0, ""}, + {"PF_W", Const, 0, ""}, + {"PF_X", Const, 0, ""}, + {"PT_AARCH64_ARCHEXT", Const, 16, ""}, + {"PT_AARCH64_UNWIND", Const, 16, ""}, + {"PT_ARM_ARCHEXT", Const, 16, ""}, + {"PT_ARM_EXIDX", Const, 16, ""}, + {"PT_DYNAMIC", Const, 0, ""}, + {"PT_GNU_EH_FRAME", Const, 16, ""}, + {"PT_GNU_MBIND_HI", Const, 16, ""}, + {"PT_GNU_MBIND_LO", Const, 16, ""}, + {"PT_GNU_PROPERTY", Const, 16, ""}, + {"PT_GNU_RELRO", Const, 16, ""}, + {"PT_GNU_STACK", Const, 16, ""}, + {"PT_HIOS", Const, 0, ""}, + {"PT_HIPROC", Const, 0, ""}, + {"PT_INTERP", Const, 0, ""}, + {"PT_LOAD", Const, 0, ""}, + {"PT_LOOS", Const, 0, ""}, + {"PT_LOPROC", Const, 0, ""}, + {"PT_MIPS_ABIFLAGS", Const, 16, ""}, + {"PT_MIPS_OPTIONS", Const, 16, ""}, + {"PT_MIPS_REGINFO", Const, 16, ""}, + {"PT_MIPS_RTPROC", Const, 16, ""}, + {"PT_NOTE", Const, 0, ""}, + {"PT_NULL", Const, 0, ""}, + {"PT_OPENBSD_BOOTDATA", Const, 16, ""}, + {"PT_OPENBSD_NOBTCFI", Const, 23, ""}, + {"PT_OPENBSD_RANDOMIZE", Const, 16, ""}, + {"PT_OPENBSD_WXNEEDED", Const, 16, ""}, + {"PT_PAX_FLAGS", Const, 16, ""}, + {"PT_PHDR", Const, 0, ""}, + {"PT_RISCV_ATTRIBUTES", Const, 25, ""}, + {"PT_S390_PGSTE", Const, 16, ""}, + {"PT_SHLIB", Const, 0, ""}, + {"PT_SUNWSTACK", Const, 16, ""}, + {"PT_SUNW_EH_FRAME", Const, 16, ""}, + {"PT_TLS", Const, 0, ""}, + {"Prog", Type, 0, ""}, + {"Prog.ProgHeader", Field, 0, ""}, + {"Prog.ReaderAt", Field, 0, ""}, + {"Prog32", Type, 0, ""}, + {"Prog32.Align", Field, 0, ""}, + {"Prog32.Filesz", Field, 0, ""}, + {"Prog32.Flags", Field, 0, ""}, + {"Prog32.Memsz", Field, 0, ""}, + {"Prog32.Off", Field, 0, ""}, + {"Prog32.Paddr", Field, 0, ""}, + {"Prog32.Type", Field, 0, ""}, + {"Prog32.Vaddr", Field, 0, ""}, + {"Prog64", Type, 0, ""}, + {"Prog64.Align", Field, 0, ""}, + {"Prog64.Filesz", Field, 0, ""}, + {"Prog64.Flags", Field, 0, ""}, + {"Prog64.Memsz", Field, 0, ""}, + {"Prog64.Off", Field, 0, ""}, + {"Prog64.Paddr", Field, 0, ""}, + {"Prog64.Type", Field, 0, ""}, + {"Prog64.Vaddr", Field, 0, ""}, + {"ProgFlag", Type, 0, ""}, + {"ProgHeader", Type, 0, ""}, + {"ProgHeader.Align", Field, 0, ""}, + {"ProgHeader.Filesz", Field, 0, ""}, + {"ProgHeader.Flags", Field, 0, ""}, + {"ProgHeader.Memsz", Field, 0, ""}, + {"ProgHeader.Off", Field, 0, ""}, + {"ProgHeader.Paddr", Field, 0, ""}, + {"ProgHeader.Type", Field, 0, ""}, + {"ProgHeader.Vaddr", Field, 0, ""}, + {"ProgType", Type, 0, ""}, + {"R_386", Type, 0, ""}, + {"R_386_16", Const, 10, ""}, + {"R_386_32", Const, 0, ""}, + {"R_386_32PLT", Const, 10, ""}, + {"R_386_8", Const, 10, ""}, + {"R_386_COPY", Const, 0, ""}, + {"R_386_GLOB_DAT", Const, 0, ""}, + {"R_386_GOT32", Const, 0, ""}, + {"R_386_GOT32X", Const, 10, ""}, + {"R_386_GOTOFF", Const, 0, ""}, + {"R_386_GOTPC", Const, 0, ""}, + {"R_386_IRELATIVE", Const, 10, ""}, + {"R_386_JMP_SLOT", Const, 0, ""}, + {"R_386_NONE", Const, 0, ""}, + {"R_386_PC16", Const, 10, ""}, + {"R_386_PC32", Const, 0, ""}, + {"R_386_PC8", Const, 10, ""}, + {"R_386_PLT32", Const, 0, ""}, + {"R_386_RELATIVE", Const, 0, ""}, + {"R_386_SIZE32", Const, 10, ""}, + {"R_386_TLS_DESC", Const, 10, ""}, + {"R_386_TLS_DESC_CALL", Const, 10, ""}, + {"R_386_TLS_DTPMOD32", Const, 0, ""}, + {"R_386_TLS_DTPOFF32", Const, 0, ""}, + {"R_386_TLS_GD", Const, 0, ""}, + {"R_386_TLS_GD_32", Const, 0, ""}, + {"R_386_TLS_GD_CALL", Const, 0, ""}, + {"R_386_TLS_GD_POP", Const, 0, ""}, + {"R_386_TLS_GD_PUSH", Const, 0, ""}, + {"R_386_TLS_GOTDESC", Const, 10, ""}, + {"R_386_TLS_GOTIE", Const, 0, ""}, + {"R_386_TLS_IE", Const, 0, ""}, + {"R_386_TLS_IE_32", Const, 0, ""}, + {"R_386_TLS_LDM", Const, 0, ""}, + {"R_386_TLS_LDM_32", Const, 0, ""}, + {"R_386_TLS_LDM_CALL", Const, 0, ""}, + {"R_386_TLS_LDM_POP", Const, 0, ""}, + {"R_386_TLS_LDM_PUSH", Const, 0, ""}, + {"R_386_TLS_LDO_32", Const, 0, ""}, + {"R_386_TLS_LE", Const, 0, ""}, + {"R_386_TLS_LE_32", Const, 0, ""}, + {"R_386_TLS_TPOFF", Const, 0, ""}, + {"R_386_TLS_TPOFF32", Const, 0, ""}, + {"R_390", Type, 7, ""}, + {"R_390_12", Const, 7, ""}, + {"R_390_16", Const, 7, ""}, + {"R_390_20", Const, 7, ""}, + {"R_390_32", Const, 7, ""}, + {"R_390_64", Const, 7, ""}, + {"R_390_8", Const, 7, ""}, + {"R_390_COPY", Const, 7, ""}, + {"R_390_GLOB_DAT", Const, 7, ""}, + {"R_390_GOT12", Const, 7, ""}, + {"R_390_GOT16", Const, 7, ""}, + {"R_390_GOT20", Const, 7, ""}, + {"R_390_GOT32", Const, 7, ""}, + {"R_390_GOT64", Const, 7, ""}, + {"R_390_GOTENT", Const, 7, ""}, + {"R_390_GOTOFF", Const, 7, ""}, + {"R_390_GOTOFF16", Const, 7, ""}, + {"R_390_GOTOFF64", Const, 7, ""}, + {"R_390_GOTPC", Const, 7, ""}, + {"R_390_GOTPCDBL", Const, 7, ""}, + {"R_390_GOTPLT12", Const, 7, ""}, + {"R_390_GOTPLT16", Const, 7, ""}, + {"R_390_GOTPLT20", Const, 7, ""}, + {"R_390_GOTPLT32", Const, 7, ""}, + {"R_390_GOTPLT64", Const, 7, ""}, + {"R_390_GOTPLTENT", Const, 7, ""}, + {"R_390_GOTPLTOFF16", Const, 7, ""}, + {"R_390_GOTPLTOFF32", Const, 7, ""}, + {"R_390_GOTPLTOFF64", Const, 7, ""}, + {"R_390_JMP_SLOT", Const, 7, ""}, + {"R_390_NONE", Const, 7, ""}, + {"R_390_PC16", Const, 7, ""}, + {"R_390_PC16DBL", Const, 7, ""}, + {"R_390_PC32", Const, 7, ""}, + {"R_390_PC32DBL", Const, 7, ""}, + {"R_390_PC64", Const, 7, ""}, + {"R_390_PLT16DBL", Const, 7, ""}, + {"R_390_PLT32", Const, 7, ""}, + {"R_390_PLT32DBL", Const, 7, ""}, + {"R_390_PLT64", Const, 7, ""}, + {"R_390_RELATIVE", Const, 7, ""}, + {"R_390_TLS_DTPMOD", Const, 7, ""}, + {"R_390_TLS_DTPOFF", Const, 7, ""}, + {"R_390_TLS_GD32", Const, 7, ""}, + {"R_390_TLS_GD64", Const, 7, ""}, + {"R_390_TLS_GDCALL", Const, 7, ""}, + {"R_390_TLS_GOTIE12", Const, 7, ""}, + {"R_390_TLS_GOTIE20", Const, 7, ""}, + {"R_390_TLS_GOTIE32", Const, 7, ""}, + {"R_390_TLS_GOTIE64", Const, 7, ""}, + {"R_390_TLS_IE32", Const, 7, ""}, + {"R_390_TLS_IE64", Const, 7, ""}, + {"R_390_TLS_IEENT", Const, 7, ""}, + {"R_390_TLS_LDCALL", Const, 7, ""}, + {"R_390_TLS_LDM32", Const, 7, ""}, + {"R_390_TLS_LDM64", Const, 7, ""}, + {"R_390_TLS_LDO32", Const, 7, ""}, + {"R_390_TLS_LDO64", Const, 7, ""}, + {"R_390_TLS_LE32", Const, 7, ""}, + {"R_390_TLS_LE64", Const, 7, ""}, + {"R_390_TLS_LOAD", Const, 7, ""}, + {"R_390_TLS_TPOFF", Const, 7, ""}, + {"R_AARCH64", Type, 4, ""}, + {"R_AARCH64_ABS16", Const, 4, ""}, + {"R_AARCH64_ABS32", Const, 4, ""}, + {"R_AARCH64_ABS64", Const, 4, ""}, + {"R_AARCH64_ADD_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_ADR_GOT_PAGE", Const, 4, ""}, + {"R_AARCH64_ADR_PREL_LO21", Const, 4, ""}, + {"R_AARCH64_ADR_PREL_PG_HI21", Const, 4, ""}, + {"R_AARCH64_ADR_PREL_PG_HI21_NC", Const, 4, ""}, + {"R_AARCH64_CALL26", Const, 4, ""}, + {"R_AARCH64_CONDBR19", Const, 4, ""}, + {"R_AARCH64_COPY", Const, 4, ""}, + {"R_AARCH64_GLOB_DAT", Const, 4, ""}, + {"R_AARCH64_GOT_LD_PREL19", Const, 4, ""}, + {"R_AARCH64_IRELATIVE", Const, 4, ""}, + {"R_AARCH64_JUMP26", Const, 4, ""}, + {"R_AARCH64_JUMP_SLOT", Const, 4, ""}, + {"R_AARCH64_LD64_GOTOFF_LO15", Const, 10, ""}, + {"R_AARCH64_LD64_GOTPAGE_LO15", Const, 10, ""}, + {"R_AARCH64_LD64_GOT_LO12_NC", Const, 4, ""}, + {"R_AARCH64_LDST128_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_LDST16_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_LDST32_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_LDST64_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_LDST8_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_LD_PREL_LO19", Const, 4, ""}, + {"R_AARCH64_MOVW_SABS_G0", Const, 4, ""}, + {"R_AARCH64_MOVW_SABS_G1", Const, 4, ""}, + {"R_AARCH64_MOVW_SABS_G2", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G0", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G0_NC", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G1", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G1_NC", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G2", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G2_NC", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G3", Const, 4, ""}, + {"R_AARCH64_NONE", Const, 4, ""}, + {"R_AARCH64_NULL", Const, 4, ""}, + {"R_AARCH64_P32_ABS16", Const, 4, ""}, + {"R_AARCH64_P32_ABS32", Const, 4, ""}, + {"R_AARCH64_P32_ADD_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_ADR_GOT_PAGE", Const, 4, ""}, + {"R_AARCH64_P32_ADR_PREL_LO21", Const, 4, ""}, + {"R_AARCH64_P32_ADR_PREL_PG_HI21", Const, 4, ""}, + {"R_AARCH64_P32_CALL26", Const, 4, ""}, + {"R_AARCH64_P32_CONDBR19", Const, 4, ""}, + {"R_AARCH64_P32_COPY", Const, 4, ""}, + {"R_AARCH64_P32_GLOB_DAT", Const, 4, ""}, + {"R_AARCH64_P32_GOT_LD_PREL19", Const, 4, ""}, + {"R_AARCH64_P32_IRELATIVE", Const, 4, ""}, + {"R_AARCH64_P32_JUMP26", Const, 4, ""}, + {"R_AARCH64_P32_JUMP_SLOT", Const, 4, ""}, + {"R_AARCH64_P32_LD32_GOT_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_LDST128_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_LDST16_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_LDST32_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_LDST64_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_LDST8_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_LD_PREL_LO19", Const, 4, ""}, + {"R_AARCH64_P32_MOVW_SABS_G0", Const, 4, ""}, + {"R_AARCH64_P32_MOVW_UABS_G0", Const, 4, ""}, + {"R_AARCH64_P32_MOVW_UABS_G0_NC", Const, 4, ""}, + {"R_AARCH64_P32_MOVW_UABS_G1", Const, 4, ""}, + {"R_AARCH64_P32_PREL16", Const, 4, ""}, + {"R_AARCH64_P32_PREL32", Const, 4, ""}, + {"R_AARCH64_P32_RELATIVE", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC_ADD_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC_ADR_PAGE21", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC_ADR_PREL21", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC_CALL", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC_LD32_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC_LD_PREL19", Const, 4, ""}, + {"R_AARCH64_P32_TLSGD_ADD_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_TLSGD_ADR_PAGE21", Const, 4, ""}, + {"R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21", Const, 4, ""}, + {"R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19", Const, 4, ""}, + {"R_AARCH64_P32_TLSLE_ADD_TPREL_HI12", Const, 4, ""}, + {"R_AARCH64_P32_TLSLE_ADD_TPREL_LO12", Const, 4, ""}, + {"R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G0", Const, 4, ""}, + {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC", Const, 4, ""}, + {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G1", Const, 4, ""}, + {"R_AARCH64_P32_TLS_DTPMOD", Const, 4, ""}, + {"R_AARCH64_P32_TLS_DTPREL", Const, 4, ""}, + {"R_AARCH64_P32_TLS_TPREL", Const, 4, ""}, + {"R_AARCH64_P32_TSTBR14", Const, 4, ""}, + {"R_AARCH64_PREL16", Const, 4, ""}, + {"R_AARCH64_PREL32", Const, 4, ""}, + {"R_AARCH64_PREL64", Const, 4, ""}, + {"R_AARCH64_RELATIVE", Const, 4, ""}, + {"R_AARCH64_TLSDESC", Const, 4, ""}, + {"R_AARCH64_TLSDESC_ADD", Const, 4, ""}, + {"R_AARCH64_TLSDESC_ADD_LO12_NC", Const, 4, ""}, + {"R_AARCH64_TLSDESC_ADR_PAGE21", Const, 4, ""}, + {"R_AARCH64_TLSDESC_ADR_PREL21", Const, 4, ""}, + {"R_AARCH64_TLSDESC_CALL", Const, 4, ""}, + {"R_AARCH64_TLSDESC_LD64_LO12_NC", Const, 4, ""}, + {"R_AARCH64_TLSDESC_LDR", Const, 4, ""}, + {"R_AARCH64_TLSDESC_LD_PREL19", Const, 4, ""}, + {"R_AARCH64_TLSDESC_OFF_G0_NC", Const, 4, ""}, + {"R_AARCH64_TLSDESC_OFF_G1", Const, 4, ""}, + {"R_AARCH64_TLSGD_ADD_LO12_NC", Const, 4, ""}, + {"R_AARCH64_TLSGD_ADR_PAGE21", Const, 4, ""}, + {"R_AARCH64_TLSGD_ADR_PREL21", Const, 10, ""}, + {"R_AARCH64_TLSGD_MOVW_G0_NC", Const, 10, ""}, + {"R_AARCH64_TLSGD_MOVW_G1", Const, 10, ""}, + {"R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21", Const, 4, ""}, + {"R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC", Const, 4, ""}, + {"R_AARCH64_TLSIE_LD_GOTTPREL_PREL19", Const, 4, ""}, + {"R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC", Const, 4, ""}, + {"R_AARCH64_TLSIE_MOVW_GOTTPREL_G1", Const, 4, ""}, + {"R_AARCH64_TLSLD_ADR_PAGE21", Const, 10, ""}, + {"R_AARCH64_TLSLD_ADR_PREL21", Const, 10, ""}, + {"R_AARCH64_TLSLD_LDST128_DTPREL_LO12", Const, 10, ""}, + {"R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC", Const, 10, ""}, + {"R_AARCH64_TLSLE_ADD_TPREL_HI12", Const, 4, ""}, + {"R_AARCH64_TLSLE_ADD_TPREL_LO12", Const, 4, ""}, + {"R_AARCH64_TLSLE_ADD_TPREL_LO12_NC", Const, 4, ""}, + {"R_AARCH64_TLSLE_LDST128_TPREL_LO12", Const, 10, ""}, + {"R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC", Const, 10, ""}, + {"R_AARCH64_TLSLE_MOVW_TPREL_G0", Const, 4, ""}, + {"R_AARCH64_TLSLE_MOVW_TPREL_G0_NC", Const, 4, ""}, + {"R_AARCH64_TLSLE_MOVW_TPREL_G1", Const, 4, ""}, + {"R_AARCH64_TLSLE_MOVW_TPREL_G1_NC", Const, 4, ""}, + {"R_AARCH64_TLSLE_MOVW_TPREL_G2", Const, 4, ""}, + {"R_AARCH64_TLS_DTPMOD64", Const, 4, ""}, + {"R_AARCH64_TLS_DTPREL64", Const, 4, ""}, + {"R_AARCH64_TLS_TPREL64", Const, 4, ""}, + {"R_AARCH64_TSTBR14", Const, 4, ""}, + {"R_ALPHA", Type, 0, ""}, + {"R_ALPHA_BRADDR", Const, 0, ""}, + {"R_ALPHA_COPY", Const, 0, ""}, + {"R_ALPHA_GLOB_DAT", Const, 0, ""}, + {"R_ALPHA_GPDISP", Const, 0, ""}, + {"R_ALPHA_GPREL32", Const, 0, ""}, + {"R_ALPHA_GPRELHIGH", Const, 0, ""}, + {"R_ALPHA_GPRELLOW", Const, 0, ""}, + {"R_ALPHA_GPVALUE", Const, 0, ""}, + {"R_ALPHA_HINT", Const, 0, ""}, + {"R_ALPHA_IMMED_BR_HI32", Const, 0, ""}, + {"R_ALPHA_IMMED_GP_16", Const, 0, ""}, + {"R_ALPHA_IMMED_GP_HI32", Const, 0, ""}, + {"R_ALPHA_IMMED_LO32", Const, 0, ""}, + {"R_ALPHA_IMMED_SCN_HI32", Const, 0, ""}, + {"R_ALPHA_JMP_SLOT", Const, 0, ""}, + {"R_ALPHA_LITERAL", Const, 0, ""}, + {"R_ALPHA_LITUSE", Const, 0, ""}, + {"R_ALPHA_NONE", Const, 0, ""}, + {"R_ALPHA_OP_PRSHIFT", Const, 0, ""}, + {"R_ALPHA_OP_PSUB", Const, 0, ""}, + {"R_ALPHA_OP_PUSH", Const, 0, ""}, + {"R_ALPHA_OP_STORE", Const, 0, ""}, + {"R_ALPHA_REFLONG", Const, 0, ""}, + {"R_ALPHA_REFQUAD", Const, 0, ""}, + {"R_ALPHA_RELATIVE", Const, 0, ""}, + {"R_ALPHA_SREL16", Const, 0, ""}, + {"R_ALPHA_SREL32", Const, 0, ""}, + {"R_ALPHA_SREL64", Const, 0, ""}, + {"R_ARM", Type, 0, ""}, + {"R_ARM_ABS12", Const, 0, ""}, + {"R_ARM_ABS16", Const, 0, ""}, + {"R_ARM_ABS32", Const, 0, ""}, + {"R_ARM_ABS32_NOI", Const, 10, ""}, + {"R_ARM_ABS8", Const, 0, ""}, + {"R_ARM_ALU_PCREL_15_8", Const, 10, ""}, + {"R_ARM_ALU_PCREL_23_15", Const, 10, ""}, + {"R_ARM_ALU_PCREL_7_0", Const, 10, ""}, + {"R_ARM_ALU_PC_G0", Const, 10, ""}, + {"R_ARM_ALU_PC_G0_NC", Const, 10, ""}, + {"R_ARM_ALU_PC_G1", Const, 10, ""}, + {"R_ARM_ALU_PC_G1_NC", Const, 10, ""}, + {"R_ARM_ALU_PC_G2", Const, 10, ""}, + {"R_ARM_ALU_SBREL_19_12_NC", Const, 10, ""}, + {"R_ARM_ALU_SBREL_27_20_CK", Const, 10, ""}, + {"R_ARM_ALU_SB_G0", Const, 10, ""}, + {"R_ARM_ALU_SB_G0_NC", Const, 10, ""}, + {"R_ARM_ALU_SB_G1", Const, 10, ""}, + {"R_ARM_ALU_SB_G1_NC", Const, 10, ""}, + {"R_ARM_ALU_SB_G2", Const, 10, ""}, + {"R_ARM_AMP_VCALL9", Const, 0, ""}, + {"R_ARM_BASE_ABS", Const, 10, ""}, + {"R_ARM_CALL", Const, 10, ""}, + {"R_ARM_COPY", Const, 0, ""}, + {"R_ARM_GLOB_DAT", Const, 0, ""}, + {"R_ARM_GNU_VTENTRY", Const, 0, ""}, + {"R_ARM_GNU_VTINHERIT", Const, 0, ""}, + {"R_ARM_GOT32", Const, 0, ""}, + {"R_ARM_GOTOFF", Const, 0, ""}, + {"R_ARM_GOTOFF12", Const, 10, ""}, + {"R_ARM_GOTPC", Const, 0, ""}, + {"R_ARM_GOTRELAX", Const, 10, ""}, + {"R_ARM_GOT_ABS", Const, 10, ""}, + {"R_ARM_GOT_BREL12", Const, 10, ""}, + {"R_ARM_GOT_PREL", Const, 10, ""}, + {"R_ARM_IRELATIVE", Const, 10, ""}, + {"R_ARM_JUMP24", Const, 10, ""}, + {"R_ARM_JUMP_SLOT", Const, 0, ""}, + {"R_ARM_LDC_PC_G0", Const, 10, ""}, + {"R_ARM_LDC_PC_G1", Const, 10, ""}, + {"R_ARM_LDC_PC_G2", Const, 10, ""}, + {"R_ARM_LDC_SB_G0", Const, 10, ""}, + {"R_ARM_LDC_SB_G1", Const, 10, ""}, + {"R_ARM_LDC_SB_G2", Const, 10, ""}, + {"R_ARM_LDRS_PC_G0", Const, 10, ""}, + {"R_ARM_LDRS_PC_G1", Const, 10, ""}, + {"R_ARM_LDRS_PC_G2", Const, 10, ""}, + {"R_ARM_LDRS_SB_G0", Const, 10, ""}, + {"R_ARM_LDRS_SB_G1", Const, 10, ""}, + {"R_ARM_LDRS_SB_G2", Const, 10, ""}, + {"R_ARM_LDR_PC_G1", Const, 10, ""}, + {"R_ARM_LDR_PC_G2", Const, 10, ""}, + {"R_ARM_LDR_SBREL_11_10_NC", Const, 10, ""}, + {"R_ARM_LDR_SB_G0", Const, 10, ""}, + {"R_ARM_LDR_SB_G1", Const, 10, ""}, + {"R_ARM_LDR_SB_G2", Const, 10, ""}, + {"R_ARM_ME_TOO", Const, 10, ""}, + {"R_ARM_MOVT_ABS", Const, 10, ""}, + {"R_ARM_MOVT_BREL", Const, 10, ""}, + {"R_ARM_MOVT_PREL", Const, 10, ""}, + {"R_ARM_MOVW_ABS_NC", Const, 10, ""}, + {"R_ARM_MOVW_BREL", Const, 10, ""}, + {"R_ARM_MOVW_BREL_NC", Const, 10, ""}, + {"R_ARM_MOVW_PREL_NC", Const, 10, ""}, + {"R_ARM_NONE", Const, 0, ""}, + {"R_ARM_PC13", Const, 0, ""}, + {"R_ARM_PC24", Const, 0, ""}, + {"R_ARM_PLT32", Const, 0, ""}, + {"R_ARM_PLT32_ABS", Const, 10, ""}, + {"R_ARM_PREL31", Const, 10, ""}, + {"R_ARM_PRIVATE_0", Const, 10, ""}, + {"R_ARM_PRIVATE_1", Const, 10, ""}, + {"R_ARM_PRIVATE_10", Const, 10, ""}, + {"R_ARM_PRIVATE_11", Const, 10, ""}, + {"R_ARM_PRIVATE_12", Const, 10, ""}, + {"R_ARM_PRIVATE_13", Const, 10, ""}, + {"R_ARM_PRIVATE_14", Const, 10, ""}, + {"R_ARM_PRIVATE_15", Const, 10, ""}, + {"R_ARM_PRIVATE_2", Const, 10, ""}, + {"R_ARM_PRIVATE_3", Const, 10, ""}, + {"R_ARM_PRIVATE_4", Const, 10, ""}, + {"R_ARM_PRIVATE_5", Const, 10, ""}, + {"R_ARM_PRIVATE_6", Const, 10, ""}, + {"R_ARM_PRIVATE_7", Const, 10, ""}, + {"R_ARM_PRIVATE_8", Const, 10, ""}, + {"R_ARM_PRIVATE_9", Const, 10, ""}, + {"R_ARM_RABS32", Const, 0, ""}, + {"R_ARM_RBASE", Const, 0, ""}, + {"R_ARM_REL32", Const, 0, ""}, + {"R_ARM_REL32_NOI", Const, 10, ""}, + {"R_ARM_RELATIVE", Const, 0, ""}, + {"R_ARM_RPC24", Const, 0, ""}, + {"R_ARM_RREL32", Const, 0, ""}, + {"R_ARM_RSBREL32", Const, 0, ""}, + {"R_ARM_RXPC25", Const, 10, ""}, + {"R_ARM_SBREL31", Const, 10, ""}, + {"R_ARM_SBREL32", Const, 0, ""}, + {"R_ARM_SWI24", Const, 0, ""}, + {"R_ARM_TARGET1", Const, 10, ""}, + {"R_ARM_TARGET2", Const, 10, ""}, + {"R_ARM_THM_ABS5", Const, 0, ""}, + {"R_ARM_THM_ALU_ABS_G0_NC", Const, 10, ""}, + {"R_ARM_THM_ALU_ABS_G1_NC", Const, 10, ""}, + {"R_ARM_THM_ALU_ABS_G2_NC", Const, 10, ""}, + {"R_ARM_THM_ALU_ABS_G3", Const, 10, ""}, + {"R_ARM_THM_ALU_PREL_11_0", Const, 10, ""}, + {"R_ARM_THM_GOT_BREL12", Const, 10, ""}, + {"R_ARM_THM_JUMP11", Const, 10, ""}, + {"R_ARM_THM_JUMP19", Const, 10, ""}, + {"R_ARM_THM_JUMP24", Const, 10, ""}, + {"R_ARM_THM_JUMP6", Const, 10, ""}, + {"R_ARM_THM_JUMP8", Const, 10, ""}, + {"R_ARM_THM_MOVT_ABS", Const, 10, ""}, + {"R_ARM_THM_MOVT_BREL", Const, 10, ""}, + {"R_ARM_THM_MOVT_PREL", Const, 10, ""}, + {"R_ARM_THM_MOVW_ABS_NC", Const, 10, ""}, + {"R_ARM_THM_MOVW_BREL", Const, 10, ""}, + {"R_ARM_THM_MOVW_BREL_NC", Const, 10, ""}, + {"R_ARM_THM_MOVW_PREL_NC", Const, 10, ""}, + {"R_ARM_THM_PC12", Const, 10, ""}, + {"R_ARM_THM_PC22", Const, 0, ""}, + {"R_ARM_THM_PC8", Const, 0, ""}, + {"R_ARM_THM_RPC22", Const, 0, ""}, + {"R_ARM_THM_SWI8", Const, 0, ""}, + {"R_ARM_THM_TLS_CALL", Const, 10, ""}, + {"R_ARM_THM_TLS_DESCSEQ16", Const, 10, ""}, + {"R_ARM_THM_TLS_DESCSEQ32", Const, 10, ""}, + {"R_ARM_THM_XPC22", Const, 0, ""}, + {"R_ARM_TLS_CALL", Const, 10, ""}, + {"R_ARM_TLS_DESCSEQ", Const, 10, ""}, + {"R_ARM_TLS_DTPMOD32", Const, 10, ""}, + {"R_ARM_TLS_DTPOFF32", Const, 10, ""}, + {"R_ARM_TLS_GD32", Const, 10, ""}, + {"R_ARM_TLS_GOTDESC", Const, 10, ""}, + {"R_ARM_TLS_IE12GP", Const, 10, ""}, + {"R_ARM_TLS_IE32", Const, 10, ""}, + {"R_ARM_TLS_LDM32", Const, 10, ""}, + {"R_ARM_TLS_LDO12", Const, 10, ""}, + {"R_ARM_TLS_LDO32", Const, 10, ""}, + {"R_ARM_TLS_LE12", Const, 10, ""}, + {"R_ARM_TLS_LE32", Const, 10, ""}, + {"R_ARM_TLS_TPOFF32", Const, 10, ""}, + {"R_ARM_V4BX", Const, 10, ""}, + {"R_ARM_XPC25", Const, 0, ""}, + {"R_INFO", Func, 0, "func(sym uint32, typ uint32) uint64"}, + {"R_INFO32", Func, 0, "func(sym uint32, typ uint32) uint32"}, + {"R_LARCH", Type, 19, ""}, + {"R_LARCH_32", Const, 19, ""}, + {"R_LARCH_32_PCREL", Const, 20, ""}, + {"R_LARCH_64", Const, 19, ""}, + {"R_LARCH_64_PCREL", Const, 22, ""}, + {"R_LARCH_ABS64_HI12", Const, 20, ""}, + {"R_LARCH_ABS64_LO20", Const, 20, ""}, + {"R_LARCH_ABS_HI20", Const, 20, ""}, + {"R_LARCH_ABS_LO12", Const, 20, ""}, + {"R_LARCH_ADD16", Const, 19, ""}, + {"R_LARCH_ADD24", Const, 19, ""}, + {"R_LARCH_ADD32", Const, 19, ""}, + {"R_LARCH_ADD6", Const, 22, ""}, + {"R_LARCH_ADD64", Const, 19, ""}, + {"R_LARCH_ADD8", Const, 19, ""}, + {"R_LARCH_ADD_ULEB128", Const, 22, ""}, + {"R_LARCH_ALIGN", Const, 22, ""}, + {"R_LARCH_B16", Const, 20, ""}, + {"R_LARCH_B21", Const, 20, ""}, + {"R_LARCH_B26", Const, 20, ""}, + {"R_LARCH_CFA", Const, 22, ""}, + {"R_LARCH_COPY", Const, 19, ""}, + {"R_LARCH_DELETE", Const, 22, ""}, + {"R_LARCH_GNU_VTENTRY", Const, 20, ""}, + {"R_LARCH_GNU_VTINHERIT", Const, 20, ""}, + {"R_LARCH_GOT64_HI12", Const, 20, ""}, + {"R_LARCH_GOT64_LO20", Const, 20, ""}, + {"R_LARCH_GOT64_PC_HI12", Const, 20, ""}, + {"R_LARCH_GOT64_PC_LO20", Const, 20, ""}, + {"R_LARCH_GOT_HI20", Const, 20, ""}, + {"R_LARCH_GOT_LO12", Const, 20, ""}, + {"R_LARCH_GOT_PC_HI20", Const, 20, ""}, + {"R_LARCH_GOT_PC_LO12", Const, 20, ""}, + {"R_LARCH_IRELATIVE", Const, 19, ""}, + {"R_LARCH_JUMP_SLOT", Const, 19, ""}, + {"R_LARCH_MARK_LA", Const, 19, ""}, + {"R_LARCH_MARK_PCREL", Const, 19, ""}, + {"R_LARCH_NONE", Const, 19, ""}, + {"R_LARCH_PCALA64_HI12", Const, 20, ""}, + {"R_LARCH_PCALA64_LO20", Const, 20, ""}, + {"R_LARCH_PCALA_HI20", Const, 20, ""}, + {"R_LARCH_PCALA_LO12", Const, 20, ""}, + {"R_LARCH_PCREL20_S2", Const, 22, ""}, + {"R_LARCH_RELATIVE", Const, 19, ""}, + {"R_LARCH_RELAX", Const, 20, ""}, + {"R_LARCH_SOP_ADD", Const, 19, ""}, + {"R_LARCH_SOP_AND", Const, 19, ""}, + {"R_LARCH_SOP_ASSERT", Const, 19, ""}, + {"R_LARCH_SOP_IF_ELSE", Const, 19, ""}, + {"R_LARCH_SOP_NOT", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_0_10_10_16_S2", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_0_5_10_16_S2", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_10_12", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_10_16", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_10_16_S2", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_10_5", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_5_20", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_U", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_U_10_12", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_ABSOLUTE", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_DUP", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_GPREL", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_PCREL", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_PLT_PCREL", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_TLS_GD", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_TLS_GOT", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_TLS_TPREL", Const, 19, ""}, + {"R_LARCH_SOP_SL", Const, 19, ""}, + {"R_LARCH_SOP_SR", Const, 19, ""}, + {"R_LARCH_SOP_SUB", Const, 19, ""}, + {"R_LARCH_SUB16", Const, 19, ""}, + {"R_LARCH_SUB24", Const, 19, ""}, + {"R_LARCH_SUB32", Const, 19, ""}, + {"R_LARCH_SUB6", Const, 22, ""}, + {"R_LARCH_SUB64", Const, 19, ""}, + {"R_LARCH_SUB8", Const, 19, ""}, + {"R_LARCH_SUB_ULEB128", Const, 22, ""}, + {"R_LARCH_TLS_DTPMOD32", Const, 19, ""}, + {"R_LARCH_TLS_DTPMOD64", Const, 19, ""}, + {"R_LARCH_TLS_DTPREL32", Const, 19, ""}, + {"R_LARCH_TLS_DTPREL64", Const, 19, ""}, + {"R_LARCH_TLS_GD_HI20", Const, 20, ""}, + {"R_LARCH_TLS_GD_PC_HI20", Const, 20, ""}, + {"R_LARCH_TLS_IE64_HI12", Const, 20, ""}, + {"R_LARCH_TLS_IE64_LO20", Const, 20, ""}, + {"R_LARCH_TLS_IE64_PC_HI12", Const, 20, ""}, + {"R_LARCH_TLS_IE64_PC_LO20", Const, 20, ""}, + {"R_LARCH_TLS_IE_HI20", Const, 20, ""}, + {"R_LARCH_TLS_IE_LO12", Const, 20, ""}, + {"R_LARCH_TLS_IE_PC_HI20", Const, 20, ""}, + {"R_LARCH_TLS_IE_PC_LO12", Const, 20, ""}, + {"R_LARCH_TLS_LD_HI20", Const, 20, ""}, + {"R_LARCH_TLS_LD_PC_HI20", Const, 20, ""}, + {"R_LARCH_TLS_LE64_HI12", Const, 20, ""}, + {"R_LARCH_TLS_LE64_LO20", Const, 20, ""}, + {"R_LARCH_TLS_LE_HI20", Const, 20, ""}, + {"R_LARCH_TLS_LE_LO12", Const, 20, ""}, + {"R_LARCH_TLS_TPREL32", Const, 19, ""}, + {"R_LARCH_TLS_TPREL64", Const, 19, ""}, + {"R_MIPS", Type, 6, ""}, + {"R_MIPS_16", Const, 6, ""}, + {"R_MIPS_26", Const, 6, ""}, + {"R_MIPS_32", Const, 6, ""}, + {"R_MIPS_64", Const, 6, ""}, + {"R_MIPS_ADD_IMMEDIATE", Const, 6, ""}, + {"R_MIPS_CALL16", Const, 6, ""}, + {"R_MIPS_CALL_HI16", Const, 6, ""}, + {"R_MIPS_CALL_LO16", Const, 6, ""}, + {"R_MIPS_DELETE", Const, 6, ""}, + {"R_MIPS_GOT16", Const, 6, ""}, + {"R_MIPS_GOT_DISP", Const, 6, ""}, + {"R_MIPS_GOT_HI16", Const, 6, ""}, + {"R_MIPS_GOT_LO16", Const, 6, ""}, + {"R_MIPS_GOT_OFST", Const, 6, ""}, + {"R_MIPS_GOT_PAGE", Const, 6, ""}, + {"R_MIPS_GPREL16", Const, 6, ""}, + {"R_MIPS_GPREL32", Const, 6, ""}, + {"R_MIPS_HI16", Const, 6, ""}, + {"R_MIPS_HIGHER", Const, 6, ""}, + {"R_MIPS_HIGHEST", Const, 6, ""}, + {"R_MIPS_INSERT_A", Const, 6, ""}, + {"R_MIPS_INSERT_B", Const, 6, ""}, + {"R_MIPS_JALR", Const, 6, ""}, + {"R_MIPS_LITERAL", Const, 6, ""}, + {"R_MIPS_LO16", Const, 6, ""}, + {"R_MIPS_NONE", Const, 6, ""}, + {"R_MIPS_PC16", Const, 6, ""}, + {"R_MIPS_PC32", Const, 22, ""}, + {"R_MIPS_PJUMP", Const, 6, ""}, + {"R_MIPS_REL16", Const, 6, ""}, + {"R_MIPS_REL32", Const, 6, ""}, + {"R_MIPS_RELGOT", Const, 6, ""}, + {"R_MIPS_SCN_DISP", Const, 6, ""}, + {"R_MIPS_SHIFT5", Const, 6, ""}, + {"R_MIPS_SHIFT6", Const, 6, ""}, + {"R_MIPS_SUB", Const, 6, ""}, + {"R_MIPS_TLS_DTPMOD32", Const, 6, ""}, + {"R_MIPS_TLS_DTPMOD64", Const, 6, ""}, + {"R_MIPS_TLS_DTPREL32", Const, 6, ""}, + {"R_MIPS_TLS_DTPREL64", Const, 6, ""}, + {"R_MIPS_TLS_DTPREL_HI16", Const, 6, ""}, + {"R_MIPS_TLS_DTPREL_LO16", Const, 6, ""}, + {"R_MIPS_TLS_GD", Const, 6, ""}, + {"R_MIPS_TLS_GOTTPREL", Const, 6, ""}, + {"R_MIPS_TLS_LDM", Const, 6, ""}, + {"R_MIPS_TLS_TPREL32", Const, 6, ""}, + {"R_MIPS_TLS_TPREL64", Const, 6, ""}, + {"R_MIPS_TLS_TPREL_HI16", Const, 6, ""}, + {"R_MIPS_TLS_TPREL_LO16", Const, 6, ""}, + {"R_PPC", Type, 0, ""}, + {"R_PPC64", Type, 5, ""}, + {"R_PPC64_ADDR14", Const, 5, ""}, + {"R_PPC64_ADDR14_BRNTAKEN", Const, 5, ""}, + {"R_PPC64_ADDR14_BRTAKEN", Const, 5, ""}, + {"R_PPC64_ADDR16", Const, 5, ""}, + {"R_PPC64_ADDR16_DS", Const, 5, ""}, + {"R_PPC64_ADDR16_HA", Const, 5, ""}, + {"R_PPC64_ADDR16_HI", Const, 5, ""}, + {"R_PPC64_ADDR16_HIGH", Const, 10, ""}, + {"R_PPC64_ADDR16_HIGHA", Const, 10, ""}, + {"R_PPC64_ADDR16_HIGHER", Const, 5, ""}, + {"R_PPC64_ADDR16_HIGHER34", Const, 20, ""}, + {"R_PPC64_ADDR16_HIGHERA", Const, 5, ""}, + {"R_PPC64_ADDR16_HIGHERA34", Const, 20, ""}, + {"R_PPC64_ADDR16_HIGHEST", Const, 5, ""}, + {"R_PPC64_ADDR16_HIGHEST34", Const, 20, ""}, + {"R_PPC64_ADDR16_HIGHESTA", Const, 5, ""}, + {"R_PPC64_ADDR16_HIGHESTA34", Const, 20, ""}, + {"R_PPC64_ADDR16_LO", Const, 5, ""}, + {"R_PPC64_ADDR16_LO_DS", Const, 5, ""}, + {"R_PPC64_ADDR24", Const, 5, ""}, + {"R_PPC64_ADDR32", Const, 5, ""}, + {"R_PPC64_ADDR64", Const, 5, ""}, + {"R_PPC64_ADDR64_LOCAL", Const, 10, ""}, + {"R_PPC64_COPY", Const, 20, ""}, + {"R_PPC64_D28", Const, 20, ""}, + {"R_PPC64_D34", Const, 20, ""}, + {"R_PPC64_D34_HA30", Const, 20, ""}, + {"R_PPC64_D34_HI30", Const, 20, ""}, + {"R_PPC64_D34_LO", Const, 20, ""}, + {"R_PPC64_DTPMOD64", Const, 5, ""}, + {"R_PPC64_DTPREL16", Const, 5, ""}, + {"R_PPC64_DTPREL16_DS", Const, 5, ""}, + {"R_PPC64_DTPREL16_HA", Const, 5, ""}, + {"R_PPC64_DTPREL16_HI", Const, 5, ""}, + {"R_PPC64_DTPREL16_HIGH", Const, 10, ""}, + {"R_PPC64_DTPREL16_HIGHA", Const, 10, ""}, + {"R_PPC64_DTPREL16_HIGHER", Const, 5, ""}, + {"R_PPC64_DTPREL16_HIGHERA", Const, 5, ""}, + {"R_PPC64_DTPREL16_HIGHEST", Const, 5, ""}, + {"R_PPC64_DTPREL16_HIGHESTA", Const, 5, ""}, + {"R_PPC64_DTPREL16_LO", Const, 5, ""}, + {"R_PPC64_DTPREL16_LO_DS", Const, 5, ""}, + {"R_PPC64_DTPREL34", Const, 20, ""}, + {"R_PPC64_DTPREL64", Const, 5, ""}, + {"R_PPC64_ENTRY", Const, 10, ""}, + {"R_PPC64_GLOB_DAT", Const, 20, ""}, + {"R_PPC64_GNU_VTENTRY", Const, 20, ""}, + {"R_PPC64_GNU_VTINHERIT", Const, 20, ""}, + {"R_PPC64_GOT16", Const, 5, ""}, + {"R_PPC64_GOT16_DS", Const, 5, ""}, + {"R_PPC64_GOT16_HA", Const, 5, ""}, + {"R_PPC64_GOT16_HI", Const, 5, ""}, + {"R_PPC64_GOT16_LO", Const, 5, ""}, + {"R_PPC64_GOT16_LO_DS", Const, 5, ""}, + {"R_PPC64_GOT_DTPREL16_DS", Const, 5, ""}, + {"R_PPC64_GOT_DTPREL16_HA", Const, 5, ""}, + {"R_PPC64_GOT_DTPREL16_HI", Const, 5, ""}, + {"R_PPC64_GOT_DTPREL16_LO_DS", Const, 5, ""}, + {"R_PPC64_GOT_DTPREL_PCREL34", Const, 20, ""}, + {"R_PPC64_GOT_PCREL34", Const, 20, ""}, + {"R_PPC64_GOT_TLSGD16", Const, 5, ""}, + {"R_PPC64_GOT_TLSGD16_HA", Const, 5, ""}, + {"R_PPC64_GOT_TLSGD16_HI", Const, 5, ""}, + {"R_PPC64_GOT_TLSGD16_LO", Const, 5, ""}, + {"R_PPC64_GOT_TLSGD_PCREL34", Const, 20, ""}, + {"R_PPC64_GOT_TLSLD16", Const, 5, ""}, + {"R_PPC64_GOT_TLSLD16_HA", Const, 5, ""}, + {"R_PPC64_GOT_TLSLD16_HI", Const, 5, ""}, + {"R_PPC64_GOT_TLSLD16_LO", Const, 5, ""}, + {"R_PPC64_GOT_TLSLD_PCREL34", Const, 20, ""}, + {"R_PPC64_GOT_TPREL16_DS", Const, 5, ""}, + {"R_PPC64_GOT_TPREL16_HA", Const, 5, ""}, + {"R_PPC64_GOT_TPREL16_HI", Const, 5, ""}, + {"R_PPC64_GOT_TPREL16_LO_DS", Const, 5, ""}, + {"R_PPC64_GOT_TPREL_PCREL34", Const, 20, ""}, + {"R_PPC64_IRELATIVE", Const, 10, ""}, + {"R_PPC64_JMP_IREL", Const, 10, ""}, + {"R_PPC64_JMP_SLOT", Const, 5, ""}, + {"R_PPC64_NONE", Const, 5, ""}, + {"R_PPC64_PCREL28", Const, 20, ""}, + {"R_PPC64_PCREL34", Const, 20, ""}, + {"R_PPC64_PCREL_OPT", Const, 20, ""}, + {"R_PPC64_PLT16_HA", Const, 20, ""}, + {"R_PPC64_PLT16_HI", Const, 20, ""}, + {"R_PPC64_PLT16_LO", Const, 20, ""}, + {"R_PPC64_PLT16_LO_DS", Const, 10, ""}, + {"R_PPC64_PLT32", Const, 20, ""}, + {"R_PPC64_PLT64", Const, 20, ""}, + {"R_PPC64_PLTCALL", Const, 20, ""}, + {"R_PPC64_PLTCALL_NOTOC", Const, 20, ""}, + {"R_PPC64_PLTGOT16", Const, 10, ""}, + {"R_PPC64_PLTGOT16_DS", Const, 10, ""}, + {"R_PPC64_PLTGOT16_HA", Const, 10, ""}, + {"R_PPC64_PLTGOT16_HI", Const, 10, ""}, + {"R_PPC64_PLTGOT16_LO", Const, 10, ""}, + {"R_PPC64_PLTGOT_LO_DS", Const, 10, ""}, + {"R_PPC64_PLTREL32", Const, 20, ""}, + {"R_PPC64_PLTREL64", Const, 20, ""}, + {"R_PPC64_PLTSEQ", Const, 20, ""}, + {"R_PPC64_PLTSEQ_NOTOC", Const, 20, ""}, + {"R_PPC64_PLT_PCREL34", Const, 20, ""}, + {"R_PPC64_PLT_PCREL34_NOTOC", Const, 20, ""}, + {"R_PPC64_REL14", Const, 5, ""}, + {"R_PPC64_REL14_BRNTAKEN", Const, 5, ""}, + {"R_PPC64_REL14_BRTAKEN", Const, 5, ""}, + {"R_PPC64_REL16", Const, 5, ""}, + {"R_PPC64_REL16DX_HA", Const, 10, ""}, + {"R_PPC64_REL16_HA", Const, 5, ""}, + {"R_PPC64_REL16_HI", Const, 5, ""}, + {"R_PPC64_REL16_HIGH", Const, 20, ""}, + {"R_PPC64_REL16_HIGHA", Const, 20, ""}, + {"R_PPC64_REL16_HIGHER", Const, 20, ""}, + {"R_PPC64_REL16_HIGHER34", Const, 20, ""}, + {"R_PPC64_REL16_HIGHERA", Const, 20, ""}, + {"R_PPC64_REL16_HIGHERA34", Const, 20, ""}, + {"R_PPC64_REL16_HIGHEST", Const, 20, ""}, + {"R_PPC64_REL16_HIGHEST34", Const, 20, ""}, + {"R_PPC64_REL16_HIGHESTA", Const, 20, ""}, + {"R_PPC64_REL16_HIGHESTA34", Const, 20, ""}, + {"R_PPC64_REL16_LO", Const, 5, ""}, + {"R_PPC64_REL24", Const, 5, ""}, + {"R_PPC64_REL24_NOTOC", Const, 10, ""}, + {"R_PPC64_REL24_P9NOTOC", Const, 21, ""}, + {"R_PPC64_REL30", Const, 20, ""}, + {"R_PPC64_REL32", Const, 5, ""}, + {"R_PPC64_REL64", Const, 5, ""}, + {"R_PPC64_RELATIVE", Const, 18, ""}, + {"R_PPC64_SECTOFF", Const, 20, ""}, + {"R_PPC64_SECTOFF_DS", Const, 10, ""}, + {"R_PPC64_SECTOFF_HA", Const, 20, ""}, + {"R_PPC64_SECTOFF_HI", Const, 20, ""}, + {"R_PPC64_SECTOFF_LO", Const, 20, ""}, + {"R_PPC64_SECTOFF_LO_DS", Const, 10, ""}, + {"R_PPC64_TLS", Const, 5, ""}, + {"R_PPC64_TLSGD", Const, 5, ""}, + {"R_PPC64_TLSLD", Const, 5, ""}, + {"R_PPC64_TOC", Const, 5, ""}, + {"R_PPC64_TOC16", Const, 5, ""}, + {"R_PPC64_TOC16_DS", Const, 5, ""}, + {"R_PPC64_TOC16_HA", Const, 5, ""}, + {"R_PPC64_TOC16_HI", Const, 5, ""}, + {"R_PPC64_TOC16_LO", Const, 5, ""}, + {"R_PPC64_TOC16_LO_DS", Const, 5, ""}, + {"R_PPC64_TOCSAVE", Const, 10, ""}, + {"R_PPC64_TPREL16", Const, 5, ""}, + {"R_PPC64_TPREL16_DS", Const, 5, ""}, + {"R_PPC64_TPREL16_HA", Const, 5, ""}, + {"R_PPC64_TPREL16_HI", Const, 5, ""}, + {"R_PPC64_TPREL16_HIGH", Const, 10, ""}, + {"R_PPC64_TPREL16_HIGHA", Const, 10, ""}, + {"R_PPC64_TPREL16_HIGHER", Const, 5, ""}, + {"R_PPC64_TPREL16_HIGHERA", Const, 5, ""}, + {"R_PPC64_TPREL16_HIGHEST", Const, 5, ""}, + {"R_PPC64_TPREL16_HIGHESTA", Const, 5, ""}, + {"R_PPC64_TPREL16_LO", Const, 5, ""}, + {"R_PPC64_TPREL16_LO_DS", Const, 5, ""}, + {"R_PPC64_TPREL34", Const, 20, ""}, + {"R_PPC64_TPREL64", Const, 5, ""}, + {"R_PPC64_UADDR16", Const, 20, ""}, + {"R_PPC64_UADDR32", Const, 20, ""}, + {"R_PPC64_UADDR64", Const, 20, ""}, + {"R_PPC_ADDR14", Const, 0, ""}, + {"R_PPC_ADDR14_BRNTAKEN", Const, 0, ""}, + {"R_PPC_ADDR14_BRTAKEN", Const, 0, ""}, + {"R_PPC_ADDR16", Const, 0, ""}, + {"R_PPC_ADDR16_HA", Const, 0, ""}, + {"R_PPC_ADDR16_HI", Const, 0, ""}, + {"R_PPC_ADDR16_LO", Const, 0, ""}, + {"R_PPC_ADDR24", Const, 0, ""}, + {"R_PPC_ADDR32", Const, 0, ""}, + {"R_PPC_COPY", Const, 0, ""}, + {"R_PPC_DTPMOD32", Const, 0, ""}, + {"R_PPC_DTPREL16", Const, 0, ""}, + {"R_PPC_DTPREL16_HA", Const, 0, ""}, + {"R_PPC_DTPREL16_HI", Const, 0, ""}, + {"R_PPC_DTPREL16_LO", Const, 0, ""}, + {"R_PPC_DTPREL32", Const, 0, ""}, + {"R_PPC_EMB_BIT_FLD", Const, 0, ""}, + {"R_PPC_EMB_MRKREF", Const, 0, ""}, + {"R_PPC_EMB_NADDR16", Const, 0, ""}, + {"R_PPC_EMB_NADDR16_HA", Const, 0, ""}, + {"R_PPC_EMB_NADDR16_HI", Const, 0, ""}, + {"R_PPC_EMB_NADDR16_LO", Const, 0, ""}, + {"R_PPC_EMB_NADDR32", Const, 0, ""}, + {"R_PPC_EMB_RELSDA", Const, 0, ""}, + {"R_PPC_EMB_RELSEC16", Const, 0, ""}, + {"R_PPC_EMB_RELST_HA", Const, 0, ""}, + {"R_PPC_EMB_RELST_HI", Const, 0, ""}, + {"R_PPC_EMB_RELST_LO", Const, 0, ""}, + {"R_PPC_EMB_SDA21", Const, 0, ""}, + {"R_PPC_EMB_SDA2I16", Const, 0, ""}, + {"R_PPC_EMB_SDA2REL", Const, 0, ""}, + {"R_PPC_EMB_SDAI16", Const, 0, ""}, + {"R_PPC_GLOB_DAT", Const, 0, ""}, + {"R_PPC_GOT16", Const, 0, ""}, + {"R_PPC_GOT16_HA", Const, 0, ""}, + {"R_PPC_GOT16_HI", Const, 0, ""}, + {"R_PPC_GOT16_LO", Const, 0, ""}, + {"R_PPC_GOT_TLSGD16", Const, 0, ""}, + {"R_PPC_GOT_TLSGD16_HA", Const, 0, ""}, + {"R_PPC_GOT_TLSGD16_HI", Const, 0, ""}, + {"R_PPC_GOT_TLSGD16_LO", Const, 0, ""}, + {"R_PPC_GOT_TLSLD16", Const, 0, ""}, + {"R_PPC_GOT_TLSLD16_HA", Const, 0, ""}, + {"R_PPC_GOT_TLSLD16_HI", Const, 0, ""}, + {"R_PPC_GOT_TLSLD16_LO", Const, 0, ""}, + {"R_PPC_GOT_TPREL16", Const, 0, ""}, + {"R_PPC_GOT_TPREL16_HA", Const, 0, ""}, + {"R_PPC_GOT_TPREL16_HI", Const, 0, ""}, + {"R_PPC_GOT_TPREL16_LO", Const, 0, ""}, + {"R_PPC_JMP_SLOT", Const, 0, ""}, + {"R_PPC_LOCAL24PC", Const, 0, ""}, + {"R_PPC_NONE", Const, 0, ""}, + {"R_PPC_PLT16_HA", Const, 0, ""}, + {"R_PPC_PLT16_HI", Const, 0, ""}, + {"R_PPC_PLT16_LO", Const, 0, ""}, + {"R_PPC_PLT32", Const, 0, ""}, + {"R_PPC_PLTREL24", Const, 0, ""}, + {"R_PPC_PLTREL32", Const, 0, ""}, + {"R_PPC_REL14", Const, 0, ""}, + {"R_PPC_REL14_BRNTAKEN", Const, 0, ""}, + {"R_PPC_REL14_BRTAKEN", Const, 0, ""}, + {"R_PPC_REL24", Const, 0, ""}, + {"R_PPC_REL32", Const, 0, ""}, + {"R_PPC_RELATIVE", Const, 0, ""}, + {"R_PPC_SDAREL16", Const, 0, ""}, + {"R_PPC_SECTOFF", Const, 0, ""}, + {"R_PPC_SECTOFF_HA", Const, 0, ""}, + {"R_PPC_SECTOFF_HI", Const, 0, ""}, + {"R_PPC_SECTOFF_LO", Const, 0, ""}, + {"R_PPC_TLS", Const, 0, ""}, + {"R_PPC_TPREL16", Const, 0, ""}, + {"R_PPC_TPREL16_HA", Const, 0, ""}, + {"R_PPC_TPREL16_HI", Const, 0, ""}, + {"R_PPC_TPREL16_LO", Const, 0, ""}, + {"R_PPC_TPREL32", Const, 0, ""}, + {"R_PPC_UADDR16", Const, 0, ""}, + {"R_PPC_UADDR32", Const, 0, ""}, + {"R_RISCV", Type, 11, ""}, + {"R_RISCV_32", Const, 11, ""}, + {"R_RISCV_32_PCREL", Const, 12, ""}, + {"R_RISCV_64", Const, 11, ""}, + {"R_RISCV_ADD16", Const, 11, ""}, + {"R_RISCV_ADD32", Const, 11, ""}, + {"R_RISCV_ADD64", Const, 11, ""}, + {"R_RISCV_ADD8", Const, 11, ""}, + {"R_RISCV_ALIGN", Const, 11, ""}, + {"R_RISCV_BRANCH", Const, 11, ""}, + {"R_RISCV_CALL", Const, 11, ""}, + {"R_RISCV_CALL_PLT", Const, 11, ""}, + {"R_RISCV_COPY", Const, 11, ""}, + {"R_RISCV_GNU_VTENTRY", Const, 11, ""}, + {"R_RISCV_GNU_VTINHERIT", Const, 11, ""}, + {"R_RISCV_GOT_HI20", Const, 11, ""}, + {"R_RISCV_GPREL_I", Const, 11, ""}, + {"R_RISCV_GPREL_S", Const, 11, ""}, + {"R_RISCV_HI20", Const, 11, ""}, + {"R_RISCV_JAL", Const, 11, ""}, + {"R_RISCV_JUMP_SLOT", Const, 11, ""}, + {"R_RISCV_LO12_I", Const, 11, ""}, + {"R_RISCV_LO12_S", Const, 11, ""}, + {"R_RISCV_NONE", Const, 11, ""}, + {"R_RISCV_PCREL_HI20", Const, 11, ""}, + {"R_RISCV_PCREL_LO12_I", Const, 11, ""}, + {"R_RISCV_PCREL_LO12_S", Const, 11, ""}, + {"R_RISCV_RELATIVE", Const, 11, ""}, + {"R_RISCV_RELAX", Const, 11, ""}, + {"R_RISCV_RVC_BRANCH", Const, 11, ""}, + {"R_RISCV_RVC_JUMP", Const, 11, ""}, + {"R_RISCV_RVC_LUI", Const, 11, ""}, + {"R_RISCV_SET16", Const, 11, ""}, + {"R_RISCV_SET32", Const, 11, ""}, + {"R_RISCV_SET6", Const, 11, ""}, + {"R_RISCV_SET8", Const, 11, ""}, + {"R_RISCV_SUB16", Const, 11, ""}, + {"R_RISCV_SUB32", Const, 11, ""}, + {"R_RISCV_SUB6", Const, 11, ""}, + {"R_RISCV_SUB64", Const, 11, ""}, + {"R_RISCV_SUB8", Const, 11, ""}, + {"R_RISCV_TLS_DTPMOD32", Const, 11, ""}, + {"R_RISCV_TLS_DTPMOD64", Const, 11, ""}, + {"R_RISCV_TLS_DTPREL32", Const, 11, ""}, + {"R_RISCV_TLS_DTPREL64", Const, 11, ""}, + {"R_RISCV_TLS_GD_HI20", Const, 11, ""}, + {"R_RISCV_TLS_GOT_HI20", Const, 11, ""}, + {"R_RISCV_TLS_TPREL32", Const, 11, ""}, + {"R_RISCV_TLS_TPREL64", Const, 11, ""}, + {"R_RISCV_TPREL_ADD", Const, 11, ""}, + {"R_RISCV_TPREL_HI20", Const, 11, ""}, + {"R_RISCV_TPREL_I", Const, 11, ""}, + {"R_RISCV_TPREL_LO12_I", Const, 11, ""}, + {"R_RISCV_TPREL_LO12_S", Const, 11, ""}, + {"R_RISCV_TPREL_S", Const, 11, ""}, + {"R_SPARC", Type, 0, ""}, + {"R_SPARC_10", Const, 0, ""}, + {"R_SPARC_11", Const, 0, ""}, + {"R_SPARC_13", Const, 0, ""}, + {"R_SPARC_16", Const, 0, ""}, + {"R_SPARC_22", Const, 0, ""}, + {"R_SPARC_32", Const, 0, ""}, + {"R_SPARC_5", Const, 0, ""}, + {"R_SPARC_6", Const, 0, ""}, + {"R_SPARC_64", Const, 0, ""}, + {"R_SPARC_7", Const, 0, ""}, + {"R_SPARC_8", Const, 0, ""}, + {"R_SPARC_COPY", Const, 0, ""}, + {"R_SPARC_DISP16", Const, 0, ""}, + {"R_SPARC_DISP32", Const, 0, ""}, + {"R_SPARC_DISP64", Const, 0, ""}, + {"R_SPARC_DISP8", Const, 0, ""}, + {"R_SPARC_GLOB_DAT", Const, 0, ""}, + {"R_SPARC_GLOB_JMP", Const, 0, ""}, + {"R_SPARC_GOT10", Const, 0, ""}, + {"R_SPARC_GOT13", Const, 0, ""}, + {"R_SPARC_GOT22", Const, 0, ""}, + {"R_SPARC_H44", Const, 0, ""}, + {"R_SPARC_HH22", Const, 0, ""}, + {"R_SPARC_HI22", Const, 0, ""}, + {"R_SPARC_HIPLT22", Const, 0, ""}, + {"R_SPARC_HIX22", Const, 0, ""}, + {"R_SPARC_HM10", Const, 0, ""}, + {"R_SPARC_JMP_SLOT", Const, 0, ""}, + {"R_SPARC_L44", Const, 0, ""}, + {"R_SPARC_LM22", Const, 0, ""}, + {"R_SPARC_LO10", Const, 0, ""}, + {"R_SPARC_LOPLT10", Const, 0, ""}, + {"R_SPARC_LOX10", Const, 0, ""}, + {"R_SPARC_M44", Const, 0, ""}, + {"R_SPARC_NONE", Const, 0, ""}, + {"R_SPARC_OLO10", Const, 0, ""}, + {"R_SPARC_PC10", Const, 0, ""}, + {"R_SPARC_PC22", Const, 0, ""}, + {"R_SPARC_PCPLT10", Const, 0, ""}, + {"R_SPARC_PCPLT22", Const, 0, ""}, + {"R_SPARC_PCPLT32", Const, 0, ""}, + {"R_SPARC_PC_HH22", Const, 0, ""}, + {"R_SPARC_PC_HM10", Const, 0, ""}, + {"R_SPARC_PC_LM22", Const, 0, ""}, + {"R_SPARC_PLT32", Const, 0, ""}, + {"R_SPARC_PLT64", Const, 0, ""}, + {"R_SPARC_REGISTER", Const, 0, ""}, + {"R_SPARC_RELATIVE", Const, 0, ""}, + {"R_SPARC_UA16", Const, 0, ""}, + {"R_SPARC_UA32", Const, 0, ""}, + {"R_SPARC_UA64", Const, 0, ""}, + {"R_SPARC_WDISP16", Const, 0, ""}, + {"R_SPARC_WDISP19", Const, 0, ""}, + {"R_SPARC_WDISP22", Const, 0, ""}, + {"R_SPARC_WDISP30", Const, 0, ""}, + {"R_SPARC_WPLT30", Const, 0, ""}, + {"R_SYM32", Func, 0, "func(info uint32) uint32"}, + {"R_SYM64", Func, 0, "func(info uint64) uint32"}, + {"R_TYPE32", Func, 0, "func(info uint32) uint32"}, + {"R_TYPE64", Func, 0, "func(info uint64) uint32"}, + {"R_X86_64", Type, 0, ""}, + {"R_X86_64_16", Const, 0, ""}, + {"R_X86_64_32", Const, 0, ""}, + {"R_X86_64_32S", Const, 0, ""}, + {"R_X86_64_64", Const, 0, ""}, + {"R_X86_64_8", Const, 0, ""}, + {"R_X86_64_COPY", Const, 0, ""}, + {"R_X86_64_DTPMOD64", Const, 0, ""}, + {"R_X86_64_DTPOFF32", Const, 0, ""}, + {"R_X86_64_DTPOFF64", Const, 0, ""}, + {"R_X86_64_GLOB_DAT", Const, 0, ""}, + {"R_X86_64_GOT32", Const, 0, ""}, + {"R_X86_64_GOT64", Const, 10, ""}, + {"R_X86_64_GOTOFF64", Const, 10, ""}, + {"R_X86_64_GOTPC32", Const, 10, ""}, + {"R_X86_64_GOTPC32_TLSDESC", Const, 10, ""}, + {"R_X86_64_GOTPC64", Const, 10, ""}, + {"R_X86_64_GOTPCREL", Const, 0, ""}, + {"R_X86_64_GOTPCREL64", Const, 10, ""}, + {"R_X86_64_GOTPCRELX", Const, 10, ""}, + {"R_X86_64_GOTPLT64", Const, 10, ""}, + {"R_X86_64_GOTTPOFF", Const, 0, ""}, + {"R_X86_64_IRELATIVE", Const, 10, ""}, + {"R_X86_64_JMP_SLOT", Const, 0, ""}, + {"R_X86_64_NONE", Const, 0, ""}, + {"R_X86_64_PC16", Const, 0, ""}, + {"R_X86_64_PC32", Const, 0, ""}, + {"R_X86_64_PC32_BND", Const, 10, ""}, + {"R_X86_64_PC64", Const, 10, ""}, + {"R_X86_64_PC8", Const, 0, ""}, + {"R_X86_64_PLT32", Const, 0, ""}, + {"R_X86_64_PLT32_BND", Const, 10, ""}, + {"R_X86_64_PLTOFF64", Const, 10, ""}, + {"R_X86_64_RELATIVE", Const, 0, ""}, + {"R_X86_64_RELATIVE64", Const, 10, ""}, + {"R_X86_64_REX_GOTPCRELX", Const, 10, ""}, + {"R_X86_64_SIZE32", Const, 10, ""}, + {"R_X86_64_SIZE64", Const, 10, ""}, + {"R_X86_64_TLSDESC", Const, 10, ""}, + {"R_X86_64_TLSDESC_CALL", Const, 10, ""}, + {"R_X86_64_TLSGD", Const, 0, ""}, + {"R_X86_64_TLSLD", Const, 0, ""}, + {"R_X86_64_TPOFF32", Const, 0, ""}, + {"R_X86_64_TPOFF64", Const, 0, ""}, + {"Rel32", Type, 0, ""}, + {"Rel32.Info", Field, 0, ""}, + {"Rel32.Off", Field, 0, ""}, + {"Rel64", Type, 0, ""}, + {"Rel64.Info", Field, 0, ""}, + {"Rel64.Off", Field, 0, ""}, + {"Rela32", Type, 0, ""}, + {"Rela32.Addend", Field, 0, ""}, + {"Rela32.Info", Field, 0, ""}, + {"Rela32.Off", Field, 0, ""}, + {"Rela64", Type, 0, ""}, + {"Rela64.Addend", Field, 0, ""}, + {"Rela64.Info", Field, 0, ""}, + {"Rela64.Off", Field, 0, ""}, + {"SHF_ALLOC", Const, 0, ""}, + {"SHF_COMPRESSED", Const, 6, ""}, + {"SHF_EXECINSTR", Const, 0, ""}, + {"SHF_GROUP", Const, 0, ""}, + {"SHF_INFO_LINK", Const, 0, ""}, + {"SHF_LINK_ORDER", Const, 0, ""}, + {"SHF_MASKOS", Const, 0, ""}, + {"SHF_MASKPROC", Const, 0, ""}, + {"SHF_MERGE", Const, 0, ""}, + {"SHF_OS_NONCONFORMING", Const, 0, ""}, + {"SHF_STRINGS", Const, 0, ""}, + {"SHF_TLS", Const, 0, ""}, + {"SHF_WRITE", Const, 0, ""}, + {"SHN_ABS", Const, 0, ""}, + {"SHN_COMMON", Const, 0, ""}, + {"SHN_HIOS", Const, 0, ""}, + {"SHN_HIPROC", Const, 0, ""}, + {"SHN_HIRESERVE", Const, 0, ""}, + {"SHN_LOOS", Const, 0, ""}, + {"SHN_LOPROC", Const, 0, ""}, + {"SHN_LORESERVE", Const, 0, ""}, + {"SHN_UNDEF", Const, 0, ""}, + {"SHN_XINDEX", Const, 0, ""}, + {"SHT_DYNAMIC", Const, 0, ""}, + {"SHT_DYNSYM", Const, 0, ""}, + {"SHT_FINI_ARRAY", Const, 0, ""}, + {"SHT_GNU_ATTRIBUTES", Const, 0, ""}, + {"SHT_GNU_HASH", Const, 0, ""}, + {"SHT_GNU_LIBLIST", Const, 0, ""}, + {"SHT_GNU_VERDEF", Const, 0, ""}, + {"SHT_GNU_VERNEED", Const, 0, ""}, + {"SHT_GNU_VERSYM", Const, 0, ""}, + {"SHT_GROUP", Const, 0, ""}, + {"SHT_HASH", Const, 0, ""}, + {"SHT_HIOS", Const, 0, ""}, + {"SHT_HIPROC", Const, 0, ""}, + {"SHT_HIUSER", Const, 0, ""}, + {"SHT_INIT_ARRAY", Const, 0, ""}, + {"SHT_LOOS", Const, 0, ""}, + {"SHT_LOPROC", Const, 0, ""}, + {"SHT_LOUSER", Const, 0, ""}, + {"SHT_MIPS_ABIFLAGS", Const, 17, ""}, + {"SHT_NOBITS", Const, 0, ""}, + {"SHT_NOTE", Const, 0, ""}, + {"SHT_NULL", Const, 0, ""}, + {"SHT_PREINIT_ARRAY", Const, 0, ""}, + {"SHT_PROGBITS", Const, 0, ""}, + {"SHT_REL", Const, 0, ""}, + {"SHT_RELA", Const, 0, ""}, + {"SHT_RISCV_ATTRIBUTES", Const, 25, ""}, + {"SHT_SHLIB", Const, 0, ""}, + {"SHT_STRTAB", Const, 0, ""}, + {"SHT_SYMTAB", Const, 0, ""}, + {"SHT_SYMTAB_SHNDX", Const, 0, ""}, + {"STB_GLOBAL", Const, 0, ""}, + {"STB_HIOS", Const, 0, ""}, + {"STB_HIPROC", Const, 0, ""}, + {"STB_LOCAL", Const, 0, ""}, + {"STB_LOOS", Const, 0, ""}, + {"STB_LOPROC", Const, 0, ""}, + {"STB_WEAK", Const, 0, ""}, + {"STT_COMMON", Const, 0, ""}, + {"STT_FILE", Const, 0, ""}, + {"STT_FUNC", Const, 0, ""}, + {"STT_GNU_IFUNC", Const, 23, ""}, + {"STT_HIOS", Const, 0, ""}, + {"STT_HIPROC", Const, 0, ""}, + {"STT_LOOS", Const, 0, ""}, + {"STT_LOPROC", Const, 0, ""}, + {"STT_NOTYPE", Const, 0, ""}, + {"STT_OBJECT", Const, 0, ""}, + {"STT_RELC", Const, 23, ""}, + {"STT_SECTION", Const, 0, ""}, + {"STT_SRELC", Const, 23, ""}, + {"STT_TLS", Const, 0, ""}, + {"STV_DEFAULT", Const, 0, ""}, + {"STV_HIDDEN", Const, 0, ""}, + {"STV_INTERNAL", Const, 0, ""}, + {"STV_PROTECTED", Const, 0, ""}, + {"ST_BIND", Func, 0, "func(info uint8) SymBind"}, + {"ST_INFO", Func, 0, "func(bind SymBind, typ SymType) uint8"}, + {"ST_TYPE", Func, 0, "func(info uint8) SymType"}, + {"ST_VISIBILITY", Func, 0, "func(other uint8) SymVis"}, + {"Section", Type, 0, ""}, + {"Section.ReaderAt", Field, 0, ""}, + {"Section.SectionHeader", Field, 0, ""}, + {"Section32", Type, 0, ""}, + {"Section32.Addr", Field, 0, ""}, + {"Section32.Addralign", Field, 0, ""}, + {"Section32.Entsize", Field, 0, ""}, + {"Section32.Flags", Field, 0, ""}, + {"Section32.Info", Field, 0, ""}, + {"Section32.Link", Field, 0, ""}, + {"Section32.Name", Field, 0, ""}, + {"Section32.Off", Field, 0, ""}, + {"Section32.Size", Field, 0, ""}, + {"Section32.Type", Field, 0, ""}, + {"Section64", Type, 0, ""}, + {"Section64.Addr", Field, 0, ""}, + {"Section64.Addralign", Field, 0, ""}, + {"Section64.Entsize", Field, 0, ""}, + {"Section64.Flags", Field, 0, ""}, + {"Section64.Info", Field, 0, ""}, + {"Section64.Link", Field, 0, ""}, + {"Section64.Name", Field, 0, ""}, + {"Section64.Off", Field, 0, ""}, + {"Section64.Size", Field, 0, ""}, + {"Section64.Type", Field, 0, ""}, + {"SectionFlag", Type, 0, ""}, + {"SectionHeader", Type, 0, ""}, + {"SectionHeader.Addr", Field, 0, ""}, + {"SectionHeader.Addralign", Field, 0, ""}, + {"SectionHeader.Entsize", Field, 0, ""}, + {"SectionHeader.FileSize", Field, 6, ""}, + {"SectionHeader.Flags", Field, 0, ""}, + {"SectionHeader.Info", Field, 0, ""}, + {"SectionHeader.Link", Field, 0, ""}, + {"SectionHeader.Name", Field, 0, ""}, + {"SectionHeader.Offset", Field, 0, ""}, + {"SectionHeader.Size", Field, 0, ""}, + {"SectionHeader.Type", Field, 0, ""}, + {"SectionIndex", Type, 0, ""}, + {"SectionType", Type, 0, ""}, + {"Sym32", Type, 0, ""}, + {"Sym32.Info", Field, 0, ""}, + {"Sym32.Name", Field, 0, ""}, + {"Sym32.Other", Field, 0, ""}, + {"Sym32.Shndx", Field, 0, ""}, + {"Sym32.Size", Field, 0, ""}, + {"Sym32.Value", Field, 0, ""}, + {"Sym32Size", Const, 0, ""}, + {"Sym64", Type, 0, ""}, + {"Sym64.Info", Field, 0, ""}, + {"Sym64.Name", Field, 0, ""}, + {"Sym64.Other", Field, 0, ""}, + {"Sym64.Shndx", Field, 0, ""}, + {"Sym64.Size", Field, 0, ""}, + {"Sym64.Value", Field, 0, ""}, + {"Sym64Size", Const, 0, ""}, + {"SymBind", Type, 0, ""}, + {"SymType", Type, 0, ""}, + {"SymVis", Type, 0, ""}, + {"Symbol", Type, 0, ""}, + {"Symbol.HasVersion", Field, 24, ""}, + {"Symbol.Info", Field, 0, ""}, + {"Symbol.Library", Field, 13, ""}, + {"Symbol.Name", Field, 0, ""}, + {"Symbol.Other", Field, 0, ""}, + {"Symbol.Section", Field, 0, ""}, + {"Symbol.Size", Field, 0, ""}, + {"Symbol.Value", Field, 0, ""}, + {"Symbol.Version", Field, 13, ""}, + {"Symbol.VersionIndex", Field, 24, ""}, + {"Type", Type, 0, ""}, + {"VER_FLG_BASE", Const, 24, ""}, + {"VER_FLG_INFO", Const, 24, ""}, + {"VER_FLG_WEAK", Const, 24, ""}, + {"Version", Type, 0, ""}, + {"VersionIndex", Type, 24, ""}, }, "debug/gosym": { - {"(*DecodingError).Error", Method, 0}, - {"(*LineTable).LineToPC", Method, 0}, - {"(*LineTable).PCToLine", Method, 0}, - {"(*Sym).BaseName", Method, 0}, - {"(*Sym).PackageName", Method, 0}, - {"(*Sym).ReceiverName", Method, 0}, - {"(*Sym).Static", Method, 0}, - {"(*Table).LineToPC", Method, 0}, - {"(*Table).LookupFunc", Method, 0}, - {"(*Table).LookupSym", Method, 0}, - {"(*Table).PCToFunc", Method, 0}, - {"(*Table).PCToLine", Method, 0}, - {"(*Table).SymByAddr", Method, 0}, - {"(*UnknownLineError).Error", Method, 0}, - {"(Func).BaseName", Method, 0}, - {"(Func).PackageName", Method, 0}, - {"(Func).ReceiverName", Method, 0}, - {"(Func).Static", Method, 0}, - {"(UnknownFileError).Error", Method, 0}, - {"DecodingError", Type, 0}, - {"Func", Type, 0}, - {"Func.End", Field, 0}, - {"Func.Entry", Field, 0}, - {"Func.FrameSize", Field, 0}, - {"Func.LineTable", Field, 0}, - {"Func.Locals", Field, 0}, - {"Func.Obj", Field, 0}, - {"Func.Params", Field, 0}, - {"Func.Sym", Field, 0}, - {"LineTable", Type, 0}, - {"LineTable.Data", Field, 0}, - {"LineTable.Line", Field, 0}, - {"LineTable.PC", Field, 0}, - {"NewLineTable", Func, 0}, - {"NewTable", Func, 0}, - {"Obj", Type, 0}, - {"Obj.Funcs", Field, 0}, - {"Obj.Paths", Field, 0}, - {"Sym", Type, 0}, - {"Sym.Func", Field, 0}, - {"Sym.GoType", Field, 0}, - {"Sym.Name", Field, 0}, - {"Sym.Type", Field, 0}, - {"Sym.Value", Field, 0}, - {"Table", Type, 0}, - {"Table.Files", Field, 0}, - {"Table.Funcs", Field, 0}, - {"Table.Objs", Field, 0}, - {"Table.Syms", Field, 0}, - {"UnknownFileError", Type, 0}, - {"UnknownLineError", Type, 0}, - {"UnknownLineError.File", Field, 0}, - {"UnknownLineError.Line", Field, 0}, + {"(*DecodingError).Error", Method, 0, ""}, + {"(*LineTable).LineToPC", Method, 0, ""}, + {"(*LineTable).PCToLine", Method, 0, ""}, + {"(*Sym).BaseName", Method, 0, ""}, + {"(*Sym).PackageName", Method, 0, ""}, + {"(*Sym).ReceiverName", Method, 0, ""}, + {"(*Sym).Static", Method, 0, ""}, + {"(*Table).LineToPC", Method, 0, ""}, + {"(*Table).LookupFunc", Method, 0, ""}, + {"(*Table).LookupSym", Method, 0, ""}, + {"(*Table).PCToFunc", Method, 0, ""}, + {"(*Table).PCToLine", Method, 0, ""}, + {"(*Table).SymByAddr", Method, 0, ""}, + {"(*UnknownLineError).Error", Method, 0, ""}, + {"(Func).BaseName", Method, 0, ""}, + {"(Func).PackageName", Method, 0, ""}, + {"(Func).ReceiverName", Method, 0, ""}, + {"(Func).Static", Method, 0, ""}, + {"(UnknownFileError).Error", Method, 0, ""}, + {"DecodingError", Type, 0, ""}, + {"Func", Type, 0, ""}, + {"Func.End", Field, 0, ""}, + {"Func.Entry", Field, 0, ""}, + {"Func.FrameSize", Field, 0, ""}, + {"Func.LineTable", Field, 0, ""}, + {"Func.Locals", Field, 0, ""}, + {"Func.Obj", Field, 0, ""}, + {"Func.Params", Field, 0, ""}, + {"Func.Sym", Field, 0, ""}, + {"LineTable", Type, 0, ""}, + {"LineTable.Data", Field, 0, ""}, + {"LineTable.Line", Field, 0, ""}, + {"LineTable.PC", Field, 0, ""}, + {"NewLineTable", Func, 0, "func(data []byte, text uint64) *LineTable"}, + {"NewTable", Func, 0, "func(symtab []byte, pcln *LineTable) (*Table, error)"}, + {"Obj", Type, 0, ""}, + {"Obj.Funcs", Field, 0, ""}, + {"Obj.Paths", Field, 0, ""}, + {"Sym", Type, 0, ""}, + {"Sym.Func", Field, 0, ""}, + {"Sym.GoType", Field, 0, ""}, + {"Sym.Name", Field, 0, ""}, + {"Sym.Type", Field, 0, ""}, + {"Sym.Value", Field, 0, ""}, + {"Table", Type, 0, ""}, + {"Table.Files", Field, 0, ""}, + {"Table.Funcs", Field, 0, ""}, + {"Table.Objs", Field, 0, ""}, + {"Table.Syms", Field, 0, ""}, + {"UnknownFileError", Type, 0, ""}, + {"UnknownLineError", Type, 0, ""}, + {"UnknownLineError.File", Field, 0, ""}, + {"UnknownLineError.Line", Field, 0, ""}, }, "debug/macho": { - {"(*FatFile).Close", Method, 3}, - {"(*File).Close", Method, 0}, - {"(*File).DWARF", Method, 0}, - {"(*File).ImportedLibraries", Method, 0}, - {"(*File).ImportedSymbols", Method, 0}, - {"(*File).Section", Method, 0}, - {"(*File).Segment", Method, 0}, - {"(*FormatError).Error", Method, 0}, - {"(*Section).Data", Method, 0}, - {"(*Section).Open", Method, 0}, - {"(*Segment).Data", Method, 0}, - {"(*Segment).Open", Method, 0}, - {"(Cpu).GoString", Method, 0}, - {"(Cpu).String", Method, 0}, - {"(Dylib).Raw", Method, 0}, - {"(Dysymtab).Raw", Method, 0}, - {"(FatArch).Close", Method, 3}, - {"(FatArch).DWARF", Method, 3}, - {"(FatArch).ImportedLibraries", Method, 3}, - {"(FatArch).ImportedSymbols", Method, 3}, - {"(FatArch).Section", Method, 3}, - {"(FatArch).Segment", Method, 3}, - {"(LoadBytes).Raw", Method, 0}, - {"(LoadCmd).GoString", Method, 0}, - {"(LoadCmd).String", Method, 0}, - {"(RelocTypeARM).GoString", Method, 10}, - {"(RelocTypeARM).String", Method, 10}, - {"(RelocTypeARM64).GoString", Method, 10}, - {"(RelocTypeARM64).String", Method, 10}, - {"(RelocTypeGeneric).GoString", Method, 10}, - {"(RelocTypeGeneric).String", Method, 10}, - {"(RelocTypeX86_64).GoString", Method, 10}, - {"(RelocTypeX86_64).String", Method, 10}, - {"(Rpath).Raw", Method, 10}, - {"(Section).ReadAt", Method, 0}, - {"(Segment).Raw", Method, 0}, - {"(Segment).ReadAt", Method, 0}, - {"(Symtab).Raw", Method, 0}, - {"(Type).GoString", Method, 10}, - {"(Type).String", Method, 10}, - {"ARM64_RELOC_ADDEND", Const, 10}, - {"ARM64_RELOC_BRANCH26", Const, 10}, - {"ARM64_RELOC_GOT_LOAD_PAGE21", Const, 10}, - {"ARM64_RELOC_GOT_LOAD_PAGEOFF12", Const, 10}, - {"ARM64_RELOC_PAGE21", Const, 10}, - {"ARM64_RELOC_PAGEOFF12", Const, 10}, - {"ARM64_RELOC_POINTER_TO_GOT", Const, 10}, - {"ARM64_RELOC_SUBTRACTOR", Const, 10}, - {"ARM64_RELOC_TLVP_LOAD_PAGE21", Const, 10}, - {"ARM64_RELOC_TLVP_LOAD_PAGEOFF12", Const, 10}, - {"ARM64_RELOC_UNSIGNED", Const, 10}, - {"ARM_RELOC_BR24", Const, 10}, - {"ARM_RELOC_HALF", Const, 10}, - {"ARM_RELOC_HALF_SECTDIFF", Const, 10}, - {"ARM_RELOC_LOCAL_SECTDIFF", Const, 10}, - {"ARM_RELOC_PAIR", Const, 10}, - {"ARM_RELOC_PB_LA_PTR", Const, 10}, - {"ARM_RELOC_SECTDIFF", Const, 10}, - {"ARM_RELOC_VANILLA", Const, 10}, - {"ARM_THUMB_32BIT_BRANCH", Const, 10}, - {"ARM_THUMB_RELOC_BR22", Const, 10}, - {"Cpu", Type, 0}, - {"Cpu386", Const, 0}, - {"CpuAmd64", Const, 0}, - {"CpuArm", Const, 3}, - {"CpuArm64", Const, 11}, - {"CpuPpc", Const, 3}, - {"CpuPpc64", Const, 3}, - {"Dylib", Type, 0}, - {"Dylib.CompatVersion", Field, 0}, - {"Dylib.CurrentVersion", Field, 0}, - {"Dylib.LoadBytes", Field, 0}, - {"Dylib.Name", Field, 0}, - {"Dylib.Time", Field, 0}, - {"DylibCmd", Type, 0}, - {"DylibCmd.Cmd", Field, 0}, - {"DylibCmd.CompatVersion", Field, 0}, - {"DylibCmd.CurrentVersion", Field, 0}, - {"DylibCmd.Len", Field, 0}, - {"DylibCmd.Name", Field, 0}, - {"DylibCmd.Time", Field, 0}, - {"Dysymtab", Type, 0}, - {"Dysymtab.DysymtabCmd", Field, 0}, - {"Dysymtab.IndirectSyms", Field, 0}, - {"Dysymtab.LoadBytes", Field, 0}, - {"DysymtabCmd", Type, 0}, - {"DysymtabCmd.Cmd", Field, 0}, - {"DysymtabCmd.Extrefsymoff", Field, 0}, - {"DysymtabCmd.Extreloff", Field, 0}, - {"DysymtabCmd.Iextdefsym", Field, 0}, - {"DysymtabCmd.Ilocalsym", Field, 0}, - {"DysymtabCmd.Indirectsymoff", Field, 0}, - {"DysymtabCmd.Iundefsym", Field, 0}, - {"DysymtabCmd.Len", Field, 0}, - {"DysymtabCmd.Locreloff", Field, 0}, - {"DysymtabCmd.Modtaboff", Field, 0}, - {"DysymtabCmd.Nextdefsym", Field, 0}, - {"DysymtabCmd.Nextrefsyms", Field, 0}, - {"DysymtabCmd.Nextrel", Field, 0}, - {"DysymtabCmd.Nindirectsyms", Field, 0}, - {"DysymtabCmd.Nlocalsym", Field, 0}, - {"DysymtabCmd.Nlocrel", Field, 0}, - {"DysymtabCmd.Nmodtab", Field, 0}, - {"DysymtabCmd.Ntoc", Field, 0}, - {"DysymtabCmd.Nundefsym", Field, 0}, - {"DysymtabCmd.Tocoffset", Field, 0}, - {"ErrNotFat", Var, 3}, - {"FatArch", Type, 3}, - {"FatArch.FatArchHeader", Field, 3}, - {"FatArch.File", Field, 3}, - {"FatArchHeader", Type, 3}, - {"FatArchHeader.Align", Field, 3}, - {"FatArchHeader.Cpu", Field, 3}, - {"FatArchHeader.Offset", Field, 3}, - {"FatArchHeader.Size", Field, 3}, - {"FatArchHeader.SubCpu", Field, 3}, - {"FatFile", Type, 3}, - {"FatFile.Arches", Field, 3}, - {"FatFile.Magic", Field, 3}, - {"File", Type, 0}, - {"File.ByteOrder", Field, 0}, - {"File.Dysymtab", Field, 0}, - {"File.FileHeader", Field, 0}, - {"File.Loads", Field, 0}, - {"File.Sections", Field, 0}, - {"File.Symtab", Field, 0}, - {"FileHeader", Type, 0}, - {"FileHeader.Cmdsz", Field, 0}, - {"FileHeader.Cpu", Field, 0}, - {"FileHeader.Flags", Field, 0}, - {"FileHeader.Magic", Field, 0}, - {"FileHeader.Ncmd", Field, 0}, - {"FileHeader.SubCpu", Field, 0}, - {"FileHeader.Type", Field, 0}, - {"FlagAllModsBound", Const, 10}, - {"FlagAllowStackExecution", Const, 10}, - {"FlagAppExtensionSafe", Const, 10}, - {"FlagBindAtLoad", Const, 10}, - {"FlagBindsToWeak", Const, 10}, - {"FlagCanonical", Const, 10}, - {"FlagDeadStrippableDylib", Const, 10}, - {"FlagDyldLink", Const, 10}, - {"FlagForceFlat", Const, 10}, - {"FlagHasTLVDescriptors", Const, 10}, - {"FlagIncrLink", Const, 10}, - {"FlagLazyInit", Const, 10}, - {"FlagNoFixPrebinding", Const, 10}, - {"FlagNoHeapExecution", Const, 10}, - {"FlagNoMultiDefs", Const, 10}, - {"FlagNoReexportedDylibs", Const, 10}, - {"FlagNoUndefs", Const, 10}, - {"FlagPIE", Const, 10}, - {"FlagPrebindable", Const, 10}, - {"FlagPrebound", Const, 10}, - {"FlagRootSafe", Const, 10}, - {"FlagSetuidSafe", Const, 10}, - {"FlagSplitSegs", Const, 10}, - {"FlagSubsectionsViaSymbols", Const, 10}, - {"FlagTwoLevel", Const, 10}, - {"FlagWeakDefines", Const, 10}, - {"FormatError", Type, 0}, - {"GENERIC_RELOC_LOCAL_SECTDIFF", Const, 10}, - {"GENERIC_RELOC_PAIR", Const, 10}, - {"GENERIC_RELOC_PB_LA_PTR", Const, 10}, - {"GENERIC_RELOC_SECTDIFF", Const, 10}, - {"GENERIC_RELOC_TLV", Const, 10}, - {"GENERIC_RELOC_VANILLA", Const, 10}, - {"Load", Type, 0}, - {"LoadBytes", Type, 0}, - {"LoadCmd", Type, 0}, - {"LoadCmdDylib", Const, 0}, - {"LoadCmdDylinker", Const, 0}, - {"LoadCmdDysymtab", Const, 0}, - {"LoadCmdRpath", Const, 10}, - {"LoadCmdSegment", Const, 0}, - {"LoadCmdSegment64", Const, 0}, - {"LoadCmdSymtab", Const, 0}, - {"LoadCmdThread", Const, 0}, - {"LoadCmdUnixThread", Const, 0}, - {"Magic32", Const, 0}, - {"Magic64", Const, 0}, - {"MagicFat", Const, 3}, - {"NewFatFile", Func, 3}, - {"NewFile", Func, 0}, - {"Nlist32", Type, 0}, - {"Nlist32.Desc", Field, 0}, - {"Nlist32.Name", Field, 0}, - {"Nlist32.Sect", Field, 0}, - {"Nlist32.Type", Field, 0}, - {"Nlist32.Value", Field, 0}, - {"Nlist64", Type, 0}, - {"Nlist64.Desc", Field, 0}, - {"Nlist64.Name", Field, 0}, - {"Nlist64.Sect", Field, 0}, - {"Nlist64.Type", Field, 0}, - {"Nlist64.Value", Field, 0}, - {"Open", Func, 0}, - {"OpenFat", Func, 3}, - {"Regs386", Type, 0}, - {"Regs386.AX", Field, 0}, - {"Regs386.BP", Field, 0}, - {"Regs386.BX", Field, 0}, - {"Regs386.CS", Field, 0}, - {"Regs386.CX", Field, 0}, - {"Regs386.DI", Field, 0}, - {"Regs386.DS", Field, 0}, - {"Regs386.DX", Field, 0}, - {"Regs386.ES", Field, 0}, - {"Regs386.FLAGS", Field, 0}, - {"Regs386.FS", Field, 0}, - {"Regs386.GS", Field, 0}, - {"Regs386.IP", Field, 0}, - {"Regs386.SI", Field, 0}, - {"Regs386.SP", Field, 0}, - {"Regs386.SS", Field, 0}, - {"RegsAMD64", Type, 0}, - {"RegsAMD64.AX", Field, 0}, - {"RegsAMD64.BP", Field, 0}, - {"RegsAMD64.BX", Field, 0}, - {"RegsAMD64.CS", Field, 0}, - {"RegsAMD64.CX", Field, 0}, - {"RegsAMD64.DI", Field, 0}, - {"RegsAMD64.DX", Field, 0}, - {"RegsAMD64.FLAGS", Field, 0}, - {"RegsAMD64.FS", Field, 0}, - {"RegsAMD64.GS", Field, 0}, - {"RegsAMD64.IP", Field, 0}, - {"RegsAMD64.R10", Field, 0}, - {"RegsAMD64.R11", Field, 0}, - {"RegsAMD64.R12", Field, 0}, - {"RegsAMD64.R13", Field, 0}, - {"RegsAMD64.R14", Field, 0}, - {"RegsAMD64.R15", Field, 0}, - {"RegsAMD64.R8", Field, 0}, - {"RegsAMD64.R9", Field, 0}, - {"RegsAMD64.SI", Field, 0}, - {"RegsAMD64.SP", Field, 0}, - {"Reloc", Type, 10}, - {"Reloc.Addr", Field, 10}, - {"Reloc.Extern", Field, 10}, - {"Reloc.Len", Field, 10}, - {"Reloc.Pcrel", Field, 10}, - {"Reloc.Scattered", Field, 10}, - {"Reloc.Type", Field, 10}, - {"Reloc.Value", Field, 10}, - {"RelocTypeARM", Type, 10}, - {"RelocTypeARM64", Type, 10}, - {"RelocTypeGeneric", Type, 10}, - {"RelocTypeX86_64", Type, 10}, - {"Rpath", Type, 10}, - {"Rpath.LoadBytes", Field, 10}, - {"Rpath.Path", Field, 10}, - {"RpathCmd", Type, 10}, - {"RpathCmd.Cmd", Field, 10}, - {"RpathCmd.Len", Field, 10}, - {"RpathCmd.Path", Field, 10}, - {"Section", Type, 0}, - {"Section.ReaderAt", Field, 0}, - {"Section.Relocs", Field, 10}, - {"Section.SectionHeader", Field, 0}, - {"Section32", Type, 0}, - {"Section32.Addr", Field, 0}, - {"Section32.Align", Field, 0}, - {"Section32.Flags", Field, 0}, - {"Section32.Name", Field, 0}, - {"Section32.Nreloc", Field, 0}, - {"Section32.Offset", Field, 0}, - {"Section32.Reloff", Field, 0}, - {"Section32.Reserve1", Field, 0}, - {"Section32.Reserve2", Field, 0}, - {"Section32.Seg", Field, 0}, - {"Section32.Size", Field, 0}, - {"Section64", Type, 0}, - {"Section64.Addr", Field, 0}, - {"Section64.Align", Field, 0}, - {"Section64.Flags", Field, 0}, - {"Section64.Name", Field, 0}, - {"Section64.Nreloc", Field, 0}, - {"Section64.Offset", Field, 0}, - {"Section64.Reloff", Field, 0}, - {"Section64.Reserve1", Field, 0}, - {"Section64.Reserve2", Field, 0}, - {"Section64.Reserve3", Field, 0}, - {"Section64.Seg", Field, 0}, - {"Section64.Size", Field, 0}, - {"SectionHeader", Type, 0}, - {"SectionHeader.Addr", Field, 0}, - {"SectionHeader.Align", Field, 0}, - {"SectionHeader.Flags", Field, 0}, - {"SectionHeader.Name", Field, 0}, - {"SectionHeader.Nreloc", Field, 0}, - {"SectionHeader.Offset", Field, 0}, - {"SectionHeader.Reloff", Field, 0}, - {"SectionHeader.Seg", Field, 0}, - {"SectionHeader.Size", Field, 0}, - {"Segment", Type, 0}, - {"Segment.LoadBytes", Field, 0}, - {"Segment.ReaderAt", Field, 0}, - {"Segment.SegmentHeader", Field, 0}, - {"Segment32", Type, 0}, - {"Segment32.Addr", Field, 0}, - {"Segment32.Cmd", Field, 0}, - {"Segment32.Filesz", Field, 0}, - {"Segment32.Flag", Field, 0}, - {"Segment32.Len", Field, 0}, - {"Segment32.Maxprot", Field, 0}, - {"Segment32.Memsz", Field, 0}, - {"Segment32.Name", Field, 0}, - {"Segment32.Nsect", Field, 0}, - {"Segment32.Offset", Field, 0}, - {"Segment32.Prot", Field, 0}, - {"Segment64", Type, 0}, - {"Segment64.Addr", Field, 0}, - {"Segment64.Cmd", Field, 0}, - {"Segment64.Filesz", Field, 0}, - {"Segment64.Flag", Field, 0}, - {"Segment64.Len", Field, 0}, - {"Segment64.Maxprot", Field, 0}, - {"Segment64.Memsz", Field, 0}, - {"Segment64.Name", Field, 0}, - {"Segment64.Nsect", Field, 0}, - {"Segment64.Offset", Field, 0}, - {"Segment64.Prot", Field, 0}, - {"SegmentHeader", Type, 0}, - {"SegmentHeader.Addr", Field, 0}, - {"SegmentHeader.Cmd", Field, 0}, - {"SegmentHeader.Filesz", Field, 0}, - {"SegmentHeader.Flag", Field, 0}, - {"SegmentHeader.Len", Field, 0}, - {"SegmentHeader.Maxprot", Field, 0}, - {"SegmentHeader.Memsz", Field, 0}, - {"SegmentHeader.Name", Field, 0}, - {"SegmentHeader.Nsect", Field, 0}, - {"SegmentHeader.Offset", Field, 0}, - {"SegmentHeader.Prot", Field, 0}, - {"Symbol", Type, 0}, - {"Symbol.Desc", Field, 0}, - {"Symbol.Name", Field, 0}, - {"Symbol.Sect", Field, 0}, - {"Symbol.Type", Field, 0}, - {"Symbol.Value", Field, 0}, - {"Symtab", Type, 0}, - {"Symtab.LoadBytes", Field, 0}, - {"Symtab.Syms", Field, 0}, - {"Symtab.SymtabCmd", Field, 0}, - {"SymtabCmd", Type, 0}, - {"SymtabCmd.Cmd", Field, 0}, - {"SymtabCmd.Len", Field, 0}, - {"SymtabCmd.Nsyms", Field, 0}, - {"SymtabCmd.Stroff", Field, 0}, - {"SymtabCmd.Strsize", Field, 0}, - {"SymtabCmd.Symoff", Field, 0}, - {"Thread", Type, 0}, - {"Thread.Cmd", Field, 0}, - {"Thread.Data", Field, 0}, - {"Thread.Len", Field, 0}, - {"Thread.Type", Field, 0}, - {"Type", Type, 0}, - {"TypeBundle", Const, 3}, - {"TypeDylib", Const, 3}, - {"TypeExec", Const, 0}, - {"TypeObj", Const, 0}, - {"X86_64_RELOC_BRANCH", Const, 10}, - {"X86_64_RELOC_GOT", Const, 10}, - {"X86_64_RELOC_GOT_LOAD", Const, 10}, - {"X86_64_RELOC_SIGNED", Const, 10}, - {"X86_64_RELOC_SIGNED_1", Const, 10}, - {"X86_64_RELOC_SIGNED_2", Const, 10}, - {"X86_64_RELOC_SIGNED_4", Const, 10}, - {"X86_64_RELOC_SUBTRACTOR", Const, 10}, - {"X86_64_RELOC_TLV", Const, 10}, - {"X86_64_RELOC_UNSIGNED", Const, 10}, + {"(*FatFile).Close", Method, 3, ""}, + {"(*File).Close", Method, 0, ""}, + {"(*File).DWARF", Method, 0, ""}, + {"(*File).ImportedLibraries", Method, 0, ""}, + {"(*File).ImportedSymbols", Method, 0, ""}, + {"(*File).Section", Method, 0, ""}, + {"(*File).Segment", Method, 0, ""}, + {"(*FormatError).Error", Method, 0, ""}, + {"(*Section).Data", Method, 0, ""}, + {"(*Section).Open", Method, 0, ""}, + {"(*Segment).Data", Method, 0, ""}, + {"(*Segment).Open", Method, 0, ""}, + {"(Cpu).GoString", Method, 0, ""}, + {"(Cpu).String", Method, 0, ""}, + {"(Dylib).Raw", Method, 0, ""}, + {"(Dysymtab).Raw", Method, 0, ""}, + {"(FatArch).Close", Method, 3, ""}, + {"(FatArch).DWARF", Method, 3, ""}, + {"(FatArch).ImportedLibraries", Method, 3, ""}, + {"(FatArch).ImportedSymbols", Method, 3, ""}, + {"(FatArch).Section", Method, 3, ""}, + {"(FatArch).Segment", Method, 3, ""}, + {"(LoadBytes).Raw", Method, 0, ""}, + {"(LoadCmd).GoString", Method, 0, ""}, + {"(LoadCmd).String", Method, 0, ""}, + {"(RelocTypeARM).GoString", Method, 10, ""}, + {"(RelocTypeARM).String", Method, 10, ""}, + {"(RelocTypeARM64).GoString", Method, 10, ""}, + {"(RelocTypeARM64).String", Method, 10, ""}, + {"(RelocTypeGeneric).GoString", Method, 10, ""}, + {"(RelocTypeGeneric).String", Method, 10, ""}, + {"(RelocTypeX86_64).GoString", Method, 10, ""}, + {"(RelocTypeX86_64).String", Method, 10, ""}, + {"(Rpath).Raw", Method, 10, ""}, + {"(Section).ReadAt", Method, 0, ""}, + {"(Segment).Raw", Method, 0, ""}, + {"(Segment).ReadAt", Method, 0, ""}, + {"(Symtab).Raw", Method, 0, ""}, + {"(Type).GoString", Method, 10, ""}, + {"(Type).String", Method, 10, ""}, + {"ARM64_RELOC_ADDEND", Const, 10, ""}, + {"ARM64_RELOC_BRANCH26", Const, 10, ""}, + {"ARM64_RELOC_GOT_LOAD_PAGE21", Const, 10, ""}, + {"ARM64_RELOC_GOT_LOAD_PAGEOFF12", Const, 10, ""}, + {"ARM64_RELOC_PAGE21", Const, 10, ""}, + {"ARM64_RELOC_PAGEOFF12", Const, 10, ""}, + {"ARM64_RELOC_POINTER_TO_GOT", Const, 10, ""}, + {"ARM64_RELOC_SUBTRACTOR", Const, 10, ""}, + {"ARM64_RELOC_TLVP_LOAD_PAGE21", Const, 10, ""}, + {"ARM64_RELOC_TLVP_LOAD_PAGEOFF12", Const, 10, ""}, + {"ARM64_RELOC_UNSIGNED", Const, 10, ""}, + {"ARM_RELOC_BR24", Const, 10, ""}, + {"ARM_RELOC_HALF", Const, 10, ""}, + {"ARM_RELOC_HALF_SECTDIFF", Const, 10, ""}, + {"ARM_RELOC_LOCAL_SECTDIFF", Const, 10, ""}, + {"ARM_RELOC_PAIR", Const, 10, ""}, + {"ARM_RELOC_PB_LA_PTR", Const, 10, ""}, + {"ARM_RELOC_SECTDIFF", Const, 10, ""}, + {"ARM_RELOC_VANILLA", Const, 10, ""}, + {"ARM_THUMB_32BIT_BRANCH", Const, 10, ""}, + {"ARM_THUMB_RELOC_BR22", Const, 10, ""}, + {"Cpu", Type, 0, ""}, + {"Cpu386", Const, 0, ""}, + {"CpuAmd64", Const, 0, ""}, + {"CpuArm", Const, 3, ""}, + {"CpuArm64", Const, 11, ""}, + {"CpuPpc", Const, 3, ""}, + {"CpuPpc64", Const, 3, ""}, + {"Dylib", Type, 0, ""}, + {"Dylib.CompatVersion", Field, 0, ""}, + {"Dylib.CurrentVersion", Field, 0, ""}, + {"Dylib.LoadBytes", Field, 0, ""}, + {"Dylib.Name", Field, 0, ""}, + {"Dylib.Time", Field, 0, ""}, + {"DylibCmd", Type, 0, ""}, + {"DylibCmd.Cmd", Field, 0, ""}, + {"DylibCmd.CompatVersion", Field, 0, ""}, + {"DylibCmd.CurrentVersion", Field, 0, ""}, + {"DylibCmd.Len", Field, 0, ""}, + {"DylibCmd.Name", Field, 0, ""}, + {"DylibCmd.Time", Field, 0, ""}, + {"Dysymtab", Type, 0, ""}, + {"Dysymtab.DysymtabCmd", Field, 0, ""}, + {"Dysymtab.IndirectSyms", Field, 0, ""}, + {"Dysymtab.LoadBytes", Field, 0, ""}, + {"DysymtabCmd", Type, 0, ""}, + {"DysymtabCmd.Cmd", Field, 0, ""}, + {"DysymtabCmd.Extrefsymoff", Field, 0, ""}, + {"DysymtabCmd.Extreloff", Field, 0, ""}, + {"DysymtabCmd.Iextdefsym", Field, 0, ""}, + {"DysymtabCmd.Ilocalsym", Field, 0, ""}, + {"DysymtabCmd.Indirectsymoff", Field, 0, ""}, + {"DysymtabCmd.Iundefsym", Field, 0, ""}, + {"DysymtabCmd.Len", Field, 0, ""}, + {"DysymtabCmd.Locreloff", Field, 0, ""}, + {"DysymtabCmd.Modtaboff", Field, 0, ""}, + {"DysymtabCmd.Nextdefsym", Field, 0, ""}, + {"DysymtabCmd.Nextrefsyms", Field, 0, ""}, + {"DysymtabCmd.Nextrel", Field, 0, ""}, + {"DysymtabCmd.Nindirectsyms", Field, 0, ""}, + {"DysymtabCmd.Nlocalsym", Field, 0, ""}, + {"DysymtabCmd.Nlocrel", Field, 0, ""}, + {"DysymtabCmd.Nmodtab", Field, 0, ""}, + {"DysymtabCmd.Ntoc", Field, 0, ""}, + {"DysymtabCmd.Nundefsym", Field, 0, ""}, + {"DysymtabCmd.Tocoffset", Field, 0, ""}, + {"ErrNotFat", Var, 3, ""}, + {"FatArch", Type, 3, ""}, + {"FatArch.FatArchHeader", Field, 3, ""}, + {"FatArch.File", Field, 3, ""}, + {"FatArchHeader", Type, 3, ""}, + {"FatArchHeader.Align", Field, 3, ""}, + {"FatArchHeader.Cpu", Field, 3, ""}, + {"FatArchHeader.Offset", Field, 3, ""}, + {"FatArchHeader.Size", Field, 3, ""}, + {"FatArchHeader.SubCpu", Field, 3, ""}, + {"FatFile", Type, 3, ""}, + {"FatFile.Arches", Field, 3, ""}, + {"FatFile.Magic", Field, 3, ""}, + {"File", Type, 0, ""}, + {"File.ByteOrder", Field, 0, ""}, + {"File.Dysymtab", Field, 0, ""}, + {"File.FileHeader", Field, 0, ""}, + {"File.Loads", Field, 0, ""}, + {"File.Sections", Field, 0, ""}, + {"File.Symtab", Field, 0, ""}, + {"FileHeader", Type, 0, ""}, + {"FileHeader.Cmdsz", Field, 0, ""}, + {"FileHeader.Cpu", Field, 0, ""}, + {"FileHeader.Flags", Field, 0, ""}, + {"FileHeader.Magic", Field, 0, ""}, + {"FileHeader.Ncmd", Field, 0, ""}, + {"FileHeader.SubCpu", Field, 0, ""}, + {"FileHeader.Type", Field, 0, ""}, + {"FlagAllModsBound", Const, 10, ""}, + {"FlagAllowStackExecution", Const, 10, ""}, + {"FlagAppExtensionSafe", Const, 10, ""}, + {"FlagBindAtLoad", Const, 10, ""}, + {"FlagBindsToWeak", Const, 10, ""}, + {"FlagCanonical", Const, 10, ""}, + {"FlagDeadStrippableDylib", Const, 10, ""}, + {"FlagDyldLink", Const, 10, ""}, + {"FlagForceFlat", Const, 10, ""}, + {"FlagHasTLVDescriptors", Const, 10, ""}, + {"FlagIncrLink", Const, 10, ""}, + {"FlagLazyInit", Const, 10, ""}, + {"FlagNoFixPrebinding", Const, 10, ""}, + {"FlagNoHeapExecution", Const, 10, ""}, + {"FlagNoMultiDefs", Const, 10, ""}, + {"FlagNoReexportedDylibs", Const, 10, ""}, + {"FlagNoUndefs", Const, 10, ""}, + {"FlagPIE", Const, 10, ""}, + {"FlagPrebindable", Const, 10, ""}, + {"FlagPrebound", Const, 10, ""}, + {"FlagRootSafe", Const, 10, ""}, + {"FlagSetuidSafe", Const, 10, ""}, + {"FlagSplitSegs", Const, 10, ""}, + {"FlagSubsectionsViaSymbols", Const, 10, ""}, + {"FlagTwoLevel", Const, 10, ""}, + {"FlagWeakDefines", Const, 10, ""}, + {"FormatError", Type, 0, ""}, + {"GENERIC_RELOC_LOCAL_SECTDIFF", Const, 10, ""}, + {"GENERIC_RELOC_PAIR", Const, 10, ""}, + {"GENERIC_RELOC_PB_LA_PTR", Const, 10, ""}, + {"GENERIC_RELOC_SECTDIFF", Const, 10, ""}, + {"GENERIC_RELOC_TLV", Const, 10, ""}, + {"GENERIC_RELOC_VANILLA", Const, 10, ""}, + {"Load", Type, 0, ""}, + {"LoadBytes", Type, 0, ""}, + {"LoadCmd", Type, 0, ""}, + {"LoadCmdDylib", Const, 0, ""}, + {"LoadCmdDylinker", Const, 0, ""}, + {"LoadCmdDysymtab", Const, 0, ""}, + {"LoadCmdRpath", Const, 10, ""}, + {"LoadCmdSegment", Const, 0, ""}, + {"LoadCmdSegment64", Const, 0, ""}, + {"LoadCmdSymtab", Const, 0, ""}, + {"LoadCmdThread", Const, 0, ""}, + {"LoadCmdUnixThread", Const, 0, ""}, + {"Magic32", Const, 0, ""}, + {"Magic64", Const, 0, ""}, + {"MagicFat", Const, 3, ""}, + {"NewFatFile", Func, 3, "func(r io.ReaderAt) (*FatFile, error)"}, + {"NewFile", Func, 0, "func(r io.ReaderAt) (*File, error)"}, + {"Nlist32", Type, 0, ""}, + {"Nlist32.Desc", Field, 0, ""}, + {"Nlist32.Name", Field, 0, ""}, + {"Nlist32.Sect", Field, 0, ""}, + {"Nlist32.Type", Field, 0, ""}, + {"Nlist32.Value", Field, 0, ""}, + {"Nlist64", Type, 0, ""}, + {"Nlist64.Desc", Field, 0, ""}, + {"Nlist64.Name", Field, 0, ""}, + {"Nlist64.Sect", Field, 0, ""}, + {"Nlist64.Type", Field, 0, ""}, + {"Nlist64.Value", Field, 0, ""}, + {"Open", Func, 0, "func(name string) (*File, error)"}, + {"OpenFat", Func, 3, "func(name string) (*FatFile, error)"}, + {"Regs386", Type, 0, ""}, + {"Regs386.AX", Field, 0, ""}, + {"Regs386.BP", Field, 0, ""}, + {"Regs386.BX", Field, 0, ""}, + {"Regs386.CS", Field, 0, ""}, + {"Regs386.CX", Field, 0, ""}, + {"Regs386.DI", Field, 0, ""}, + {"Regs386.DS", Field, 0, ""}, + {"Regs386.DX", Field, 0, ""}, + {"Regs386.ES", Field, 0, ""}, + {"Regs386.FLAGS", Field, 0, ""}, + {"Regs386.FS", Field, 0, ""}, + {"Regs386.GS", Field, 0, ""}, + {"Regs386.IP", Field, 0, ""}, + {"Regs386.SI", Field, 0, ""}, + {"Regs386.SP", Field, 0, ""}, + {"Regs386.SS", Field, 0, ""}, + {"RegsAMD64", Type, 0, ""}, + {"RegsAMD64.AX", Field, 0, ""}, + {"RegsAMD64.BP", Field, 0, ""}, + {"RegsAMD64.BX", Field, 0, ""}, + {"RegsAMD64.CS", Field, 0, ""}, + {"RegsAMD64.CX", Field, 0, ""}, + {"RegsAMD64.DI", Field, 0, ""}, + {"RegsAMD64.DX", Field, 0, ""}, + {"RegsAMD64.FLAGS", Field, 0, ""}, + {"RegsAMD64.FS", Field, 0, ""}, + {"RegsAMD64.GS", Field, 0, ""}, + {"RegsAMD64.IP", Field, 0, ""}, + {"RegsAMD64.R10", Field, 0, ""}, + {"RegsAMD64.R11", Field, 0, ""}, + {"RegsAMD64.R12", Field, 0, ""}, + {"RegsAMD64.R13", Field, 0, ""}, + {"RegsAMD64.R14", Field, 0, ""}, + {"RegsAMD64.R15", Field, 0, ""}, + {"RegsAMD64.R8", Field, 0, ""}, + {"RegsAMD64.R9", Field, 0, ""}, + {"RegsAMD64.SI", Field, 0, ""}, + {"RegsAMD64.SP", Field, 0, ""}, + {"Reloc", Type, 10, ""}, + {"Reloc.Addr", Field, 10, ""}, + {"Reloc.Extern", Field, 10, ""}, + {"Reloc.Len", Field, 10, ""}, + {"Reloc.Pcrel", Field, 10, ""}, + {"Reloc.Scattered", Field, 10, ""}, + {"Reloc.Type", Field, 10, ""}, + {"Reloc.Value", Field, 10, ""}, + {"RelocTypeARM", Type, 10, ""}, + {"RelocTypeARM64", Type, 10, ""}, + {"RelocTypeGeneric", Type, 10, ""}, + {"RelocTypeX86_64", Type, 10, ""}, + {"Rpath", Type, 10, ""}, + {"Rpath.LoadBytes", Field, 10, ""}, + {"Rpath.Path", Field, 10, ""}, + {"RpathCmd", Type, 10, ""}, + {"RpathCmd.Cmd", Field, 10, ""}, + {"RpathCmd.Len", Field, 10, ""}, + {"RpathCmd.Path", Field, 10, ""}, + {"Section", Type, 0, ""}, + {"Section.ReaderAt", Field, 0, ""}, + {"Section.Relocs", Field, 10, ""}, + {"Section.SectionHeader", Field, 0, ""}, + {"Section32", Type, 0, ""}, + {"Section32.Addr", Field, 0, ""}, + {"Section32.Align", Field, 0, ""}, + {"Section32.Flags", Field, 0, ""}, + {"Section32.Name", Field, 0, ""}, + {"Section32.Nreloc", Field, 0, ""}, + {"Section32.Offset", Field, 0, ""}, + {"Section32.Reloff", Field, 0, ""}, + {"Section32.Reserve1", Field, 0, ""}, + {"Section32.Reserve2", Field, 0, ""}, + {"Section32.Seg", Field, 0, ""}, + {"Section32.Size", Field, 0, ""}, + {"Section64", Type, 0, ""}, + {"Section64.Addr", Field, 0, ""}, + {"Section64.Align", Field, 0, ""}, + {"Section64.Flags", Field, 0, ""}, + {"Section64.Name", Field, 0, ""}, + {"Section64.Nreloc", Field, 0, ""}, + {"Section64.Offset", Field, 0, ""}, + {"Section64.Reloff", Field, 0, ""}, + {"Section64.Reserve1", Field, 0, ""}, + {"Section64.Reserve2", Field, 0, ""}, + {"Section64.Reserve3", Field, 0, ""}, + {"Section64.Seg", Field, 0, ""}, + {"Section64.Size", Field, 0, ""}, + {"SectionHeader", Type, 0, ""}, + {"SectionHeader.Addr", Field, 0, ""}, + {"SectionHeader.Align", Field, 0, ""}, + {"SectionHeader.Flags", Field, 0, ""}, + {"SectionHeader.Name", Field, 0, ""}, + {"SectionHeader.Nreloc", Field, 0, ""}, + {"SectionHeader.Offset", Field, 0, ""}, + {"SectionHeader.Reloff", Field, 0, ""}, + {"SectionHeader.Seg", Field, 0, ""}, + {"SectionHeader.Size", Field, 0, ""}, + {"Segment", Type, 0, ""}, + {"Segment.LoadBytes", Field, 0, ""}, + {"Segment.ReaderAt", Field, 0, ""}, + {"Segment.SegmentHeader", Field, 0, ""}, + {"Segment32", Type, 0, ""}, + {"Segment32.Addr", Field, 0, ""}, + {"Segment32.Cmd", Field, 0, ""}, + {"Segment32.Filesz", Field, 0, ""}, + {"Segment32.Flag", Field, 0, ""}, + {"Segment32.Len", Field, 0, ""}, + {"Segment32.Maxprot", Field, 0, ""}, + {"Segment32.Memsz", Field, 0, ""}, + {"Segment32.Name", Field, 0, ""}, + {"Segment32.Nsect", Field, 0, ""}, + {"Segment32.Offset", Field, 0, ""}, + {"Segment32.Prot", Field, 0, ""}, + {"Segment64", Type, 0, ""}, + {"Segment64.Addr", Field, 0, ""}, + {"Segment64.Cmd", Field, 0, ""}, + {"Segment64.Filesz", Field, 0, ""}, + {"Segment64.Flag", Field, 0, ""}, + {"Segment64.Len", Field, 0, ""}, + {"Segment64.Maxprot", Field, 0, ""}, + {"Segment64.Memsz", Field, 0, ""}, + {"Segment64.Name", Field, 0, ""}, + {"Segment64.Nsect", Field, 0, ""}, + {"Segment64.Offset", Field, 0, ""}, + {"Segment64.Prot", Field, 0, ""}, + {"SegmentHeader", Type, 0, ""}, + {"SegmentHeader.Addr", Field, 0, ""}, + {"SegmentHeader.Cmd", Field, 0, ""}, + {"SegmentHeader.Filesz", Field, 0, ""}, + {"SegmentHeader.Flag", Field, 0, ""}, + {"SegmentHeader.Len", Field, 0, ""}, + {"SegmentHeader.Maxprot", Field, 0, ""}, + {"SegmentHeader.Memsz", Field, 0, ""}, + {"SegmentHeader.Name", Field, 0, ""}, + {"SegmentHeader.Nsect", Field, 0, ""}, + {"SegmentHeader.Offset", Field, 0, ""}, + {"SegmentHeader.Prot", Field, 0, ""}, + {"Symbol", Type, 0, ""}, + {"Symbol.Desc", Field, 0, ""}, + {"Symbol.Name", Field, 0, ""}, + {"Symbol.Sect", Field, 0, ""}, + {"Symbol.Type", Field, 0, ""}, + {"Symbol.Value", Field, 0, ""}, + {"Symtab", Type, 0, ""}, + {"Symtab.LoadBytes", Field, 0, ""}, + {"Symtab.Syms", Field, 0, ""}, + {"Symtab.SymtabCmd", Field, 0, ""}, + {"SymtabCmd", Type, 0, ""}, + {"SymtabCmd.Cmd", Field, 0, ""}, + {"SymtabCmd.Len", Field, 0, ""}, + {"SymtabCmd.Nsyms", Field, 0, ""}, + {"SymtabCmd.Stroff", Field, 0, ""}, + {"SymtabCmd.Strsize", Field, 0, ""}, + {"SymtabCmd.Symoff", Field, 0, ""}, + {"Thread", Type, 0, ""}, + {"Thread.Cmd", Field, 0, ""}, + {"Thread.Data", Field, 0, ""}, + {"Thread.Len", Field, 0, ""}, + {"Thread.Type", Field, 0, ""}, + {"Type", Type, 0, ""}, + {"TypeBundle", Const, 3, ""}, + {"TypeDylib", Const, 3, ""}, + {"TypeExec", Const, 0, ""}, + {"TypeObj", Const, 0, ""}, + {"X86_64_RELOC_BRANCH", Const, 10, ""}, + {"X86_64_RELOC_GOT", Const, 10, ""}, + {"X86_64_RELOC_GOT_LOAD", Const, 10, ""}, + {"X86_64_RELOC_SIGNED", Const, 10, ""}, + {"X86_64_RELOC_SIGNED_1", Const, 10, ""}, + {"X86_64_RELOC_SIGNED_2", Const, 10, ""}, + {"X86_64_RELOC_SIGNED_4", Const, 10, ""}, + {"X86_64_RELOC_SUBTRACTOR", Const, 10, ""}, + {"X86_64_RELOC_TLV", Const, 10, ""}, + {"X86_64_RELOC_UNSIGNED", Const, 10, ""}, }, "debug/pe": { - {"(*COFFSymbol).FullName", Method, 8}, - {"(*File).COFFSymbolReadSectionDefAux", Method, 19}, - {"(*File).Close", Method, 0}, - {"(*File).DWARF", Method, 0}, - {"(*File).ImportedLibraries", Method, 0}, - {"(*File).ImportedSymbols", Method, 0}, - {"(*File).Section", Method, 0}, - {"(*FormatError).Error", Method, 0}, - {"(*Section).Data", Method, 0}, - {"(*Section).Open", Method, 0}, - {"(Section).ReadAt", Method, 0}, - {"(StringTable).String", Method, 8}, - {"COFFSymbol", Type, 1}, - {"COFFSymbol.Name", Field, 1}, - {"COFFSymbol.NumberOfAuxSymbols", Field, 1}, - {"COFFSymbol.SectionNumber", Field, 1}, - {"COFFSymbol.StorageClass", Field, 1}, - {"COFFSymbol.Type", Field, 1}, - {"COFFSymbol.Value", Field, 1}, - {"COFFSymbolAuxFormat5", Type, 19}, - {"COFFSymbolAuxFormat5.Checksum", Field, 19}, - {"COFFSymbolAuxFormat5.NumLineNumbers", Field, 19}, - {"COFFSymbolAuxFormat5.NumRelocs", Field, 19}, - {"COFFSymbolAuxFormat5.SecNum", Field, 19}, - {"COFFSymbolAuxFormat5.Selection", Field, 19}, - {"COFFSymbolAuxFormat5.Size", Field, 19}, - {"COFFSymbolSize", Const, 1}, - {"DataDirectory", Type, 3}, - {"DataDirectory.Size", Field, 3}, - {"DataDirectory.VirtualAddress", Field, 3}, - {"File", Type, 0}, - {"File.COFFSymbols", Field, 8}, - {"File.FileHeader", Field, 0}, - {"File.OptionalHeader", Field, 3}, - {"File.Sections", Field, 0}, - {"File.StringTable", Field, 8}, - {"File.Symbols", Field, 1}, - {"FileHeader", Type, 0}, - {"FileHeader.Characteristics", Field, 0}, - {"FileHeader.Machine", Field, 0}, - {"FileHeader.NumberOfSections", Field, 0}, - {"FileHeader.NumberOfSymbols", Field, 0}, - {"FileHeader.PointerToSymbolTable", Field, 0}, - {"FileHeader.SizeOfOptionalHeader", Field, 0}, - {"FileHeader.TimeDateStamp", Field, 0}, - {"FormatError", Type, 0}, - {"IMAGE_COMDAT_SELECT_ANY", Const, 19}, - {"IMAGE_COMDAT_SELECT_ASSOCIATIVE", Const, 19}, - {"IMAGE_COMDAT_SELECT_EXACT_MATCH", Const, 19}, - {"IMAGE_COMDAT_SELECT_LARGEST", Const, 19}, - {"IMAGE_COMDAT_SELECT_NODUPLICATES", Const, 19}, - {"IMAGE_COMDAT_SELECT_SAME_SIZE", Const, 19}, - {"IMAGE_DIRECTORY_ENTRY_ARCHITECTURE", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_BASERELOC", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_BOUND_IMPORT", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_COM_DESCRIPTOR", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_DEBUG", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_DELAY_IMPORT", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_EXCEPTION", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_EXPORT", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_GLOBALPTR", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_IAT", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_IMPORT", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_RESOURCE", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_SECURITY", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_TLS", Const, 11}, - {"IMAGE_DLLCHARACTERISTICS_APPCONTAINER", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_DYNAMIC_BASE", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_FORCE_INTEGRITY", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_GUARD_CF", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_HIGH_ENTROPY_VA", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_NO_BIND", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_NO_ISOLATION", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_NO_SEH", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_NX_COMPAT", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_WDM_DRIVER", Const, 15}, - {"IMAGE_FILE_32BIT_MACHINE", Const, 15}, - {"IMAGE_FILE_AGGRESIVE_WS_TRIM", Const, 15}, - {"IMAGE_FILE_BYTES_REVERSED_HI", Const, 15}, - {"IMAGE_FILE_BYTES_REVERSED_LO", Const, 15}, - {"IMAGE_FILE_DEBUG_STRIPPED", Const, 15}, - {"IMAGE_FILE_DLL", Const, 15}, - {"IMAGE_FILE_EXECUTABLE_IMAGE", Const, 15}, - {"IMAGE_FILE_LARGE_ADDRESS_AWARE", Const, 15}, - {"IMAGE_FILE_LINE_NUMS_STRIPPED", Const, 15}, - {"IMAGE_FILE_LOCAL_SYMS_STRIPPED", Const, 15}, - {"IMAGE_FILE_MACHINE_AM33", Const, 0}, - {"IMAGE_FILE_MACHINE_AMD64", Const, 0}, - {"IMAGE_FILE_MACHINE_ARM", Const, 0}, - {"IMAGE_FILE_MACHINE_ARM64", Const, 11}, - {"IMAGE_FILE_MACHINE_ARMNT", Const, 12}, - {"IMAGE_FILE_MACHINE_EBC", Const, 0}, - {"IMAGE_FILE_MACHINE_I386", Const, 0}, - {"IMAGE_FILE_MACHINE_IA64", Const, 0}, - {"IMAGE_FILE_MACHINE_LOONGARCH32", Const, 19}, - {"IMAGE_FILE_MACHINE_LOONGARCH64", Const, 19}, - {"IMAGE_FILE_MACHINE_M32R", Const, 0}, - {"IMAGE_FILE_MACHINE_MIPS16", Const, 0}, - {"IMAGE_FILE_MACHINE_MIPSFPU", Const, 0}, - {"IMAGE_FILE_MACHINE_MIPSFPU16", Const, 0}, - {"IMAGE_FILE_MACHINE_POWERPC", Const, 0}, - {"IMAGE_FILE_MACHINE_POWERPCFP", Const, 0}, - {"IMAGE_FILE_MACHINE_R4000", Const, 0}, - {"IMAGE_FILE_MACHINE_RISCV128", Const, 20}, - {"IMAGE_FILE_MACHINE_RISCV32", Const, 20}, - {"IMAGE_FILE_MACHINE_RISCV64", Const, 20}, - {"IMAGE_FILE_MACHINE_SH3", Const, 0}, - {"IMAGE_FILE_MACHINE_SH3DSP", Const, 0}, - {"IMAGE_FILE_MACHINE_SH4", Const, 0}, - {"IMAGE_FILE_MACHINE_SH5", Const, 0}, - {"IMAGE_FILE_MACHINE_THUMB", Const, 0}, - {"IMAGE_FILE_MACHINE_UNKNOWN", Const, 0}, - {"IMAGE_FILE_MACHINE_WCEMIPSV2", Const, 0}, - {"IMAGE_FILE_NET_RUN_FROM_SWAP", Const, 15}, - {"IMAGE_FILE_RELOCS_STRIPPED", Const, 15}, - {"IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP", Const, 15}, - {"IMAGE_FILE_SYSTEM", Const, 15}, - {"IMAGE_FILE_UP_SYSTEM_ONLY", Const, 15}, - {"IMAGE_SCN_CNT_CODE", Const, 19}, - {"IMAGE_SCN_CNT_INITIALIZED_DATA", Const, 19}, - {"IMAGE_SCN_CNT_UNINITIALIZED_DATA", Const, 19}, - {"IMAGE_SCN_LNK_COMDAT", Const, 19}, - {"IMAGE_SCN_MEM_DISCARDABLE", Const, 19}, - {"IMAGE_SCN_MEM_EXECUTE", Const, 19}, - {"IMAGE_SCN_MEM_READ", Const, 19}, - {"IMAGE_SCN_MEM_WRITE", Const, 19}, - {"IMAGE_SUBSYSTEM_EFI_APPLICATION", Const, 15}, - {"IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER", Const, 15}, - {"IMAGE_SUBSYSTEM_EFI_ROM", Const, 15}, - {"IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER", Const, 15}, - {"IMAGE_SUBSYSTEM_NATIVE", Const, 15}, - {"IMAGE_SUBSYSTEM_NATIVE_WINDOWS", Const, 15}, - {"IMAGE_SUBSYSTEM_OS2_CUI", Const, 15}, - {"IMAGE_SUBSYSTEM_POSIX_CUI", Const, 15}, - {"IMAGE_SUBSYSTEM_UNKNOWN", Const, 15}, - {"IMAGE_SUBSYSTEM_WINDOWS_BOOT_APPLICATION", Const, 15}, - {"IMAGE_SUBSYSTEM_WINDOWS_CE_GUI", Const, 15}, - {"IMAGE_SUBSYSTEM_WINDOWS_CUI", Const, 15}, - {"IMAGE_SUBSYSTEM_WINDOWS_GUI", Const, 15}, - {"IMAGE_SUBSYSTEM_XBOX", Const, 15}, - {"ImportDirectory", Type, 0}, - {"ImportDirectory.FirstThunk", Field, 0}, - {"ImportDirectory.ForwarderChain", Field, 0}, - {"ImportDirectory.Name", Field, 0}, - {"ImportDirectory.OriginalFirstThunk", Field, 0}, - {"ImportDirectory.TimeDateStamp", Field, 0}, - {"NewFile", Func, 0}, - {"Open", Func, 0}, - {"OptionalHeader32", Type, 3}, - {"OptionalHeader32.AddressOfEntryPoint", Field, 3}, - {"OptionalHeader32.BaseOfCode", Field, 3}, - {"OptionalHeader32.BaseOfData", Field, 3}, - {"OptionalHeader32.CheckSum", Field, 3}, - {"OptionalHeader32.DataDirectory", Field, 3}, - {"OptionalHeader32.DllCharacteristics", Field, 3}, - {"OptionalHeader32.FileAlignment", Field, 3}, - {"OptionalHeader32.ImageBase", Field, 3}, - {"OptionalHeader32.LoaderFlags", Field, 3}, - {"OptionalHeader32.Magic", Field, 3}, - {"OptionalHeader32.MajorImageVersion", Field, 3}, - {"OptionalHeader32.MajorLinkerVersion", Field, 3}, - {"OptionalHeader32.MajorOperatingSystemVersion", Field, 3}, - {"OptionalHeader32.MajorSubsystemVersion", Field, 3}, - {"OptionalHeader32.MinorImageVersion", Field, 3}, - {"OptionalHeader32.MinorLinkerVersion", Field, 3}, - {"OptionalHeader32.MinorOperatingSystemVersion", Field, 3}, - {"OptionalHeader32.MinorSubsystemVersion", Field, 3}, - {"OptionalHeader32.NumberOfRvaAndSizes", Field, 3}, - {"OptionalHeader32.SectionAlignment", Field, 3}, - {"OptionalHeader32.SizeOfCode", Field, 3}, - {"OptionalHeader32.SizeOfHeaders", Field, 3}, - {"OptionalHeader32.SizeOfHeapCommit", Field, 3}, - {"OptionalHeader32.SizeOfHeapReserve", Field, 3}, - {"OptionalHeader32.SizeOfImage", Field, 3}, - {"OptionalHeader32.SizeOfInitializedData", Field, 3}, - {"OptionalHeader32.SizeOfStackCommit", Field, 3}, - {"OptionalHeader32.SizeOfStackReserve", Field, 3}, - {"OptionalHeader32.SizeOfUninitializedData", Field, 3}, - {"OptionalHeader32.Subsystem", Field, 3}, - {"OptionalHeader32.Win32VersionValue", Field, 3}, - {"OptionalHeader64", Type, 3}, - {"OptionalHeader64.AddressOfEntryPoint", Field, 3}, - {"OptionalHeader64.BaseOfCode", Field, 3}, - {"OptionalHeader64.CheckSum", Field, 3}, - {"OptionalHeader64.DataDirectory", Field, 3}, - {"OptionalHeader64.DllCharacteristics", Field, 3}, - {"OptionalHeader64.FileAlignment", Field, 3}, - {"OptionalHeader64.ImageBase", Field, 3}, - {"OptionalHeader64.LoaderFlags", Field, 3}, - {"OptionalHeader64.Magic", Field, 3}, - {"OptionalHeader64.MajorImageVersion", Field, 3}, - {"OptionalHeader64.MajorLinkerVersion", Field, 3}, - {"OptionalHeader64.MajorOperatingSystemVersion", Field, 3}, - {"OptionalHeader64.MajorSubsystemVersion", Field, 3}, - {"OptionalHeader64.MinorImageVersion", Field, 3}, - {"OptionalHeader64.MinorLinkerVersion", Field, 3}, - {"OptionalHeader64.MinorOperatingSystemVersion", Field, 3}, - {"OptionalHeader64.MinorSubsystemVersion", Field, 3}, - {"OptionalHeader64.NumberOfRvaAndSizes", Field, 3}, - {"OptionalHeader64.SectionAlignment", Field, 3}, - {"OptionalHeader64.SizeOfCode", Field, 3}, - {"OptionalHeader64.SizeOfHeaders", Field, 3}, - {"OptionalHeader64.SizeOfHeapCommit", Field, 3}, - {"OptionalHeader64.SizeOfHeapReserve", Field, 3}, - {"OptionalHeader64.SizeOfImage", Field, 3}, - {"OptionalHeader64.SizeOfInitializedData", Field, 3}, - {"OptionalHeader64.SizeOfStackCommit", Field, 3}, - {"OptionalHeader64.SizeOfStackReserve", Field, 3}, - {"OptionalHeader64.SizeOfUninitializedData", Field, 3}, - {"OptionalHeader64.Subsystem", Field, 3}, - {"OptionalHeader64.Win32VersionValue", Field, 3}, - {"Reloc", Type, 8}, - {"Reloc.SymbolTableIndex", Field, 8}, - {"Reloc.Type", Field, 8}, - {"Reloc.VirtualAddress", Field, 8}, - {"Section", Type, 0}, - {"Section.ReaderAt", Field, 0}, - {"Section.Relocs", Field, 8}, - {"Section.SectionHeader", Field, 0}, - {"SectionHeader", Type, 0}, - {"SectionHeader.Characteristics", Field, 0}, - {"SectionHeader.Name", Field, 0}, - {"SectionHeader.NumberOfLineNumbers", Field, 0}, - {"SectionHeader.NumberOfRelocations", Field, 0}, - {"SectionHeader.Offset", Field, 0}, - {"SectionHeader.PointerToLineNumbers", Field, 0}, - {"SectionHeader.PointerToRelocations", Field, 0}, - {"SectionHeader.Size", Field, 0}, - {"SectionHeader.VirtualAddress", Field, 0}, - {"SectionHeader.VirtualSize", Field, 0}, - {"SectionHeader32", Type, 0}, - {"SectionHeader32.Characteristics", Field, 0}, - {"SectionHeader32.Name", Field, 0}, - {"SectionHeader32.NumberOfLineNumbers", Field, 0}, - {"SectionHeader32.NumberOfRelocations", Field, 0}, - {"SectionHeader32.PointerToLineNumbers", Field, 0}, - {"SectionHeader32.PointerToRawData", Field, 0}, - {"SectionHeader32.PointerToRelocations", Field, 0}, - {"SectionHeader32.SizeOfRawData", Field, 0}, - {"SectionHeader32.VirtualAddress", Field, 0}, - {"SectionHeader32.VirtualSize", Field, 0}, - {"StringTable", Type, 8}, - {"Symbol", Type, 1}, - {"Symbol.Name", Field, 1}, - {"Symbol.SectionNumber", Field, 1}, - {"Symbol.StorageClass", Field, 1}, - {"Symbol.Type", Field, 1}, - {"Symbol.Value", Field, 1}, + {"(*COFFSymbol).FullName", Method, 8, ""}, + {"(*File).COFFSymbolReadSectionDefAux", Method, 19, ""}, + {"(*File).Close", Method, 0, ""}, + {"(*File).DWARF", Method, 0, ""}, + {"(*File).ImportedLibraries", Method, 0, ""}, + {"(*File).ImportedSymbols", Method, 0, ""}, + {"(*File).Section", Method, 0, ""}, + {"(*FormatError).Error", Method, 0, ""}, + {"(*Section).Data", Method, 0, ""}, + {"(*Section).Open", Method, 0, ""}, + {"(Section).ReadAt", Method, 0, ""}, + {"(StringTable).String", Method, 8, ""}, + {"COFFSymbol", Type, 1, ""}, + {"COFFSymbol.Name", Field, 1, ""}, + {"COFFSymbol.NumberOfAuxSymbols", Field, 1, ""}, + {"COFFSymbol.SectionNumber", Field, 1, ""}, + {"COFFSymbol.StorageClass", Field, 1, ""}, + {"COFFSymbol.Type", Field, 1, ""}, + {"COFFSymbol.Value", Field, 1, ""}, + {"COFFSymbolAuxFormat5", Type, 19, ""}, + {"COFFSymbolAuxFormat5.Checksum", Field, 19, ""}, + {"COFFSymbolAuxFormat5.NumLineNumbers", Field, 19, ""}, + {"COFFSymbolAuxFormat5.NumRelocs", Field, 19, ""}, + {"COFFSymbolAuxFormat5.SecNum", Field, 19, ""}, + {"COFFSymbolAuxFormat5.Selection", Field, 19, ""}, + {"COFFSymbolAuxFormat5.Size", Field, 19, ""}, + {"COFFSymbolSize", Const, 1, ""}, + {"DataDirectory", Type, 3, ""}, + {"DataDirectory.Size", Field, 3, ""}, + {"DataDirectory.VirtualAddress", Field, 3, ""}, + {"File", Type, 0, ""}, + {"File.COFFSymbols", Field, 8, ""}, + {"File.FileHeader", Field, 0, ""}, + {"File.OptionalHeader", Field, 3, ""}, + {"File.Sections", Field, 0, ""}, + {"File.StringTable", Field, 8, ""}, + {"File.Symbols", Field, 1, ""}, + {"FileHeader", Type, 0, ""}, + {"FileHeader.Characteristics", Field, 0, ""}, + {"FileHeader.Machine", Field, 0, ""}, + {"FileHeader.NumberOfSections", Field, 0, ""}, + {"FileHeader.NumberOfSymbols", Field, 0, ""}, + {"FileHeader.PointerToSymbolTable", Field, 0, ""}, + {"FileHeader.SizeOfOptionalHeader", Field, 0, ""}, + {"FileHeader.TimeDateStamp", Field, 0, ""}, + {"FormatError", Type, 0, ""}, + {"IMAGE_COMDAT_SELECT_ANY", Const, 19, ""}, + {"IMAGE_COMDAT_SELECT_ASSOCIATIVE", Const, 19, ""}, + {"IMAGE_COMDAT_SELECT_EXACT_MATCH", Const, 19, ""}, + {"IMAGE_COMDAT_SELECT_LARGEST", Const, 19, ""}, + {"IMAGE_COMDAT_SELECT_NODUPLICATES", Const, 19, ""}, + {"IMAGE_COMDAT_SELECT_SAME_SIZE", Const, 19, ""}, + {"IMAGE_DIRECTORY_ENTRY_ARCHITECTURE", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_BASERELOC", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_BOUND_IMPORT", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_COM_DESCRIPTOR", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_DEBUG", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_DELAY_IMPORT", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_EXCEPTION", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_EXPORT", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_GLOBALPTR", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_IAT", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_IMPORT", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_RESOURCE", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_SECURITY", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_TLS", Const, 11, ""}, + {"IMAGE_DLLCHARACTERISTICS_APPCONTAINER", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_DYNAMIC_BASE", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_FORCE_INTEGRITY", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_GUARD_CF", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_HIGH_ENTROPY_VA", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_NO_BIND", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_NO_ISOLATION", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_NO_SEH", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_NX_COMPAT", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_WDM_DRIVER", Const, 15, ""}, + {"IMAGE_FILE_32BIT_MACHINE", Const, 15, ""}, + {"IMAGE_FILE_AGGRESIVE_WS_TRIM", Const, 15, ""}, + {"IMAGE_FILE_BYTES_REVERSED_HI", Const, 15, ""}, + {"IMAGE_FILE_BYTES_REVERSED_LO", Const, 15, ""}, + {"IMAGE_FILE_DEBUG_STRIPPED", Const, 15, ""}, + {"IMAGE_FILE_DLL", Const, 15, ""}, + {"IMAGE_FILE_EXECUTABLE_IMAGE", Const, 15, ""}, + {"IMAGE_FILE_LARGE_ADDRESS_AWARE", Const, 15, ""}, + {"IMAGE_FILE_LINE_NUMS_STRIPPED", Const, 15, ""}, + {"IMAGE_FILE_LOCAL_SYMS_STRIPPED", Const, 15, ""}, + {"IMAGE_FILE_MACHINE_AM33", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_AMD64", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_ARM", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_ARM64", Const, 11, ""}, + {"IMAGE_FILE_MACHINE_ARMNT", Const, 12, ""}, + {"IMAGE_FILE_MACHINE_EBC", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_I386", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_IA64", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_LOONGARCH32", Const, 19, ""}, + {"IMAGE_FILE_MACHINE_LOONGARCH64", Const, 19, ""}, + {"IMAGE_FILE_MACHINE_M32R", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_MIPS16", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_MIPSFPU", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_MIPSFPU16", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_POWERPC", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_POWERPCFP", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_R4000", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_RISCV128", Const, 20, ""}, + {"IMAGE_FILE_MACHINE_RISCV32", Const, 20, ""}, + {"IMAGE_FILE_MACHINE_RISCV64", Const, 20, ""}, + {"IMAGE_FILE_MACHINE_SH3", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_SH3DSP", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_SH4", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_SH5", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_THUMB", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_UNKNOWN", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_WCEMIPSV2", Const, 0, ""}, + {"IMAGE_FILE_NET_RUN_FROM_SWAP", Const, 15, ""}, + {"IMAGE_FILE_RELOCS_STRIPPED", Const, 15, ""}, + {"IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP", Const, 15, ""}, + {"IMAGE_FILE_SYSTEM", Const, 15, ""}, + {"IMAGE_FILE_UP_SYSTEM_ONLY", Const, 15, ""}, + {"IMAGE_SCN_CNT_CODE", Const, 19, ""}, + {"IMAGE_SCN_CNT_INITIALIZED_DATA", Const, 19, ""}, + {"IMAGE_SCN_CNT_UNINITIALIZED_DATA", Const, 19, ""}, + {"IMAGE_SCN_LNK_COMDAT", Const, 19, ""}, + {"IMAGE_SCN_MEM_DISCARDABLE", Const, 19, ""}, + {"IMAGE_SCN_MEM_EXECUTE", Const, 19, ""}, + {"IMAGE_SCN_MEM_READ", Const, 19, ""}, + {"IMAGE_SCN_MEM_WRITE", Const, 19, ""}, + {"IMAGE_SUBSYSTEM_EFI_APPLICATION", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_EFI_ROM", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_NATIVE", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_NATIVE_WINDOWS", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_OS2_CUI", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_POSIX_CUI", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_UNKNOWN", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_WINDOWS_BOOT_APPLICATION", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_WINDOWS_CE_GUI", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_WINDOWS_CUI", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_WINDOWS_GUI", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_XBOX", Const, 15, ""}, + {"ImportDirectory", Type, 0, ""}, + {"ImportDirectory.FirstThunk", Field, 0, ""}, + {"ImportDirectory.ForwarderChain", Field, 0, ""}, + {"ImportDirectory.Name", Field, 0, ""}, + {"ImportDirectory.OriginalFirstThunk", Field, 0, ""}, + {"ImportDirectory.TimeDateStamp", Field, 0, ""}, + {"NewFile", Func, 0, "func(r io.ReaderAt) (*File, error)"}, + {"Open", Func, 0, "func(name string) (*File, error)"}, + {"OptionalHeader32", Type, 3, ""}, + {"OptionalHeader32.AddressOfEntryPoint", Field, 3, ""}, + {"OptionalHeader32.BaseOfCode", Field, 3, ""}, + {"OptionalHeader32.BaseOfData", Field, 3, ""}, + {"OptionalHeader32.CheckSum", Field, 3, ""}, + {"OptionalHeader32.DataDirectory", Field, 3, ""}, + {"OptionalHeader32.DllCharacteristics", Field, 3, ""}, + {"OptionalHeader32.FileAlignment", Field, 3, ""}, + {"OptionalHeader32.ImageBase", Field, 3, ""}, + {"OptionalHeader32.LoaderFlags", Field, 3, ""}, + {"OptionalHeader32.Magic", Field, 3, ""}, + {"OptionalHeader32.MajorImageVersion", Field, 3, ""}, + {"OptionalHeader32.MajorLinkerVersion", Field, 3, ""}, + {"OptionalHeader32.MajorOperatingSystemVersion", Field, 3, ""}, + {"OptionalHeader32.MajorSubsystemVersion", Field, 3, ""}, + {"OptionalHeader32.MinorImageVersion", Field, 3, ""}, + {"OptionalHeader32.MinorLinkerVersion", Field, 3, ""}, + {"OptionalHeader32.MinorOperatingSystemVersion", Field, 3, ""}, + {"OptionalHeader32.MinorSubsystemVersion", Field, 3, ""}, + {"OptionalHeader32.NumberOfRvaAndSizes", Field, 3, ""}, + {"OptionalHeader32.SectionAlignment", Field, 3, ""}, + {"OptionalHeader32.SizeOfCode", Field, 3, ""}, + {"OptionalHeader32.SizeOfHeaders", Field, 3, ""}, + {"OptionalHeader32.SizeOfHeapCommit", Field, 3, ""}, + {"OptionalHeader32.SizeOfHeapReserve", Field, 3, ""}, + {"OptionalHeader32.SizeOfImage", Field, 3, ""}, + {"OptionalHeader32.SizeOfInitializedData", Field, 3, ""}, + {"OptionalHeader32.SizeOfStackCommit", Field, 3, ""}, + {"OptionalHeader32.SizeOfStackReserve", Field, 3, ""}, + {"OptionalHeader32.SizeOfUninitializedData", Field, 3, ""}, + {"OptionalHeader32.Subsystem", Field, 3, ""}, + {"OptionalHeader32.Win32VersionValue", Field, 3, ""}, + {"OptionalHeader64", Type, 3, ""}, + {"OptionalHeader64.AddressOfEntryPoint", Field, 3, ""}, + {"OptionalHeader64.BaseOfCode", Field, 3, ""}, + {"OptionalHeader64.CheckSum", Field, 3, ""}, + {"OptionalHeader64.DataDirectory", Field, 3, ""}, + {"OptionalHeader64.DllCharacteristics", Field, 3, ""}, + {"OptionalHeader64.FileAlignment", Field, 3, ""}, + {"OptionalHeader64.ImageBase", Field, 3, ""}, + {"OptionalHeader64.LoaderFlags", Field, 3, ""}, + {"OptionalHeader64.Magic", Field, 3, ""}, + {"OptionalHeader64.MajorImageVersion", Field, 3, ""}, + {"OptionalHeader64.MajorLinkerVersion", Field, 3, ""}, + {"OptionalHeader64.MajorOperatingSystemVersion", Field, 3, ""}, + {"OptionalHeader64.MajorSubsystemVersion", Field, 3, ""}, + {"OptionalHeader64.MinorImageVersion", Field, 3, ""}, + {"OptionalHeader64.MinorLinkerVersion", Field, 3, ""}, + {"OptionalHeader64.MinorOperatingSystemVersion", Field, 3, ""}, + {"OptionalHeader64.MinorSubsystemVersion", Field, 3, ""}, + {"OptionalHeader64.NumberOfRvaAndSizes", Field, 3, ""}, + {"OptionalHeader64.SectionAlignment", Field, 3, ""}, + {"OptionalHeader64.SizeOfCode", Field, 3, ""}, + {"OptionalHeader64.SizeOfHeaders", Field, 3, ""}, + {"OptionalHeader64.SizeOfHeapCommit", Field, 3, ""}, + {"OptionalHeader64.SizeOfHeapReserve", Field, 3, ""}, + {"OptionalHeader64.SizeOfImage", Field, 3, ""}, + {"OptionalHeader64.SizeOfInitializedData", Field, 3, ""}, + {"OptionalHeader64.SizeOfStackCommit", Field, 3, ""}, + {"OptionalHeader64.SizeOfStackReserve", Field, 3, ""}, + {"OptionalHeader64.SizeOfUninitializedData", Field, 3, ""}, + {"OptionalHeader64.Subsystem", Field, 3, ""}, + {"OptionalHeader64.Win32VersionValue", Field, 3, ""}, + {"Reloc", Type, 8, ""}, + {"Reloc.SymbolTableIndex", Field, 8, ""}, + {"Reloc.Type", Field, 8, ""}, + {"Reloc.VirtualAddress", Field, 8, ""}, + {"Section", Type, 0, ""}, + {"Section.ReaderAt", Field, 0, ""}, + {"Section.Relocs", Field, 8, ""}, + {"Section.SectionHeader", Field, 0, ""}, + {"SectionHeader", Type, 0, ""}, + {"SectionHeader.Characteristics", Field, 0, ""}, + {"SectionHeader.Name", Field, 0, ""}, + {"SectionHeader.NumberOfLineNumbers", Field, 0, ""}, + {"SectionHeader.NumberOfRelocations", Field, 0, ""}, + {"SectionHeader.Offset", Field, 0, ""}, + {"SectionHeader.PointerToLineNumbers", Field, 0, ""}, + {"SectionHeader.PointerToRelocations", Field, 0, ""}, + {"SectionHeader.Size", Field, 0, ""}, + {"SectionHeader.VirtualAddress", Field, 0, ""}, + {"SectionHeader.VirtualSize", Field, 0, ""}, + {"SectionHeader32", Type, 0, ""}, + {"SectionHeader32.Characteristics", Field, 0, ""}, + {"SectionHeader32.Name", Field, 0, ""}, + {"SectionHeader32.NumberOfLineNumbers", Field, 0, ""}, + {"SectionHeader32.NumberOfRelocations", Field, 0, ""}, + {"SectionHeader32.PointerToLineNumbers", Field, 0, ""}, + {"SectionHeader32.PointerToRawData", Field, 0, ""}, + {"SectionHeader32.PointerToRelocations", Field, 0, ""}, + {"SectionHeader32.SizeOfRawData", Field, 0, ""}, + {"SectionHeader32.VirtualAddress", Field, 0, ""}, + {"SectionHeader32.VirtualSize", Field, 0, ""}, + {"StringTable", Type, 8, ""}, + {"Symbol", Type, 1, ""}, + {"Symbol.Name", Field, 1, ""}, + {"Symbol.SectionNumber", Field, 1, ""}, + {"Symbol.StorageClass", Field, 1, ""}, + {"Symbol.Type", Field, 1, ""}, + {"Symbol.Value", Field, 1, ""}, }, "debug/plan9obj": { - {"(*File).Close", Method, 3}, - {"(*File).Section", Method, 3}, - {"(*File).Symbols", Method, 3}, - {"(*Section).Data", Method, 3}, - {"(*Section).Open", Method, 3}, - {"(Section).ReadAt", Method, 3}, - {"ErrNoSymbols", Var, 18}, - {"File", Type, 3}, - {"File.FileHeader", Field, 3}, - {"File.Sections", Field, 3}, - {"FileHeader", Type, 3}, - {"FileHeader.Bss", Field, 3}, - {"FileHeader.Entry", Field, 3}, - {"FileHeader.HdrSize", Field, 4}, - {"FileHeader.LoadAddress", Field, 4}, - {"FileHeader.Magic", Field, 3}, - {"FileHeader.PtrSize", Field, 3}, - {"Magic386", Const, 3}, - {"Magic64", Const, 3}, - {"MagicAMD64", Const, 3}, - {"MagicARM", Const, 3}, - {"NewFile", Func, 3}, - {"Open", Func, 3}, - {"Section", Type, 3}, - {"Section.ReaderAt", Field, 3}, - {"Section.SectionHeader", Field, 3}, - {"SectionHeader", Type, 3}, - {"SectionHeader.Name", Field, 3}, - {"SectionHeader.Offset", Field, 3}, - {"SectionHeader.Size", Field, 3}, - {"Sym", Type, 3}, - {"Sym.Name", Field, 3}, - {"Sym.Type", Field, 3}, - {"Sym.Value", Field, 3}, + {"(*File).Close", Method, 3, ""}, + {"(*File).Section", Method, 3, ""}, + {"(*File).Symbols", Method, 3, ""}, + {"(*Section).Data", Method, 3, ""}, + {"(*Section).Open", Method, 3, ""}, + {"(Section).ReadAt", Method, 3, ""}, + {"ErrNoSymbols", Var, 18, ""}, + {"File", Type, 3, ""}, + {"File.FileHeader", Field, 3, ""}, + {"File.Sections", Field, 3, ""}, + {"FileHeader", Type, 3, ""}, + {"FileHeader.Bss", Field, 3, ""}, + {"FileHeader.Entry", Field, 3, ""}, + {"FileHeader.HdrSize", Field, 4, ""}, + {"FileHeader.LoadAddress", Field, 4, ""}, + {"FileHeader.Magic", Field, 3, ""}, + {"FileHeader.PtrSize", Field, 3, ""}, + {"Magic386", Const, 3, ""}, + {"Magic64", Const, 3, ""}, + {"MagicAMD64", Const, 3, ""}, + {"MagicARM", Const, 3, ""}, + {"NewFile", Func, 3, "func(r io.ReaderAt) (*File, error)"}, + {"Open", Func, 3, "func(name string) (*File, error)"}, + {"Section", Type, 3, ""}, + {"Section.ReaderAt", Field, 3, ""}, + {"Section.SectionHeader", Field, 3, ""}, + {"SectionHeader", Type, 3, ""}, + {"SectionHeader.Name", Field, 3, ""}, + {"SectionHeader.Offset", Field, 3, ""}, + {"SectionHeader.Size", Field, 3, ""}, + {"Sym", Type, 3, ""}, + {"Sym.Name", Field, 3, ""}, + {"Sym.Type", Field, 3, ""}, + {"Sym.Value", Field, 3, ""}, }, "embed": { - {"(FS).Open", Method, 16}, - {"(FS).ReadDir", Method, 16}, - {"(FS).ReadFile", Method, 16}, - {"FS", Type, 16}, + {"(FS).Open", Method, 16, ""}, + {"(FS).ReadDir", Method, 16, ""}, + {"(FS).ReadFile", Method, 16, ""}, + {"FS", Type, 16, ""}, }, "encoding": { - {"BinaryAppender", Type, 24}, - {"BinaryMarshaler", Type, 2}, - {"BinaryUnmarshaler", Type, 2}, - {"TextAppender", Type, 24}, - {"TextMarshaler", Type, 2}, - {"TextUnmarshaler", Type, 2}, + {"BinaryAppender", Type, 24, ""}, + {"BinaryMarshaler", Type, 2, ""}, + {"BinaryUnmarshaler", Type, 2, ""}, + {"TextAppender", Type, 24, ""}, + {"TextMarshaler", Type, 2, ""}, + {"TextUnmarshaler", Type, 2, ""}, }, "encoding/ascii85": { - {"(CorruptInputError).Error", Method, 0}, - {"CorruptInputError", Type, 0}, - {"Decode", Func, 0}, - {"Encode", Func, 0}, - {"MaxEncodedLen", Func, 0}, - {"NewDecoder", Func, 0}, - {"NewEncoder", Func, 0}, + {"(CorruptInputError).Error", Method, 0, ""}, + {"CorruptInputError", Type, 0, ""}, + {"Decode", Func, 0, "func(dst []byte, src []byte, flush bool) (ndst int, nsrc int, err error)"}, + {"Encode", Func, 0, "func(dst []byte, src []byte) int"}, + {"MaxEncodedLen", Func, 0, "func(n int) int"}, + {"NewDecoder", Func, 0, "func(r io.Reader) io.Reader"}, + {"NewEncoder", Func, 0, "func(w io.Writer) io.WriteCloser"}, }, "encoding/asn1": { - {"(BitString).At", Method, 0}, - {"(BitString).RightAlign", Method, 0}, - {"(ObjectIdentifier).Equal", Method, 0}, - {"(ObjectIdentifier).String", Method, 3}, - {"(StructuralError).Error", Method, 0}, - {"(SyntaxError).Error", Method, 0}, - {"BitString", Type, 0}, - {"BitString.BitLength", Field, 0}, - {"BitString.Bytes", Field, 0}, - {"ClassApplication", Const, 6}, - {"ClassContextSpecific", Const, 6}, - {"ClassPrivate", Const, 6}, - {"ClassUniversal", Const, 6}, - {"Enumerated", Type, 0}, - {"Flag", Type, 0}, - {"Marshal", Func, 0}, - {"MarshalWithParams", Func, 10}, - {"NullBytes", Var, 9}, - {"NullRawValue", Var, 9}, - {"ObjectIdentifier", Type, 0}, - {"RawContent", Type, 0}, - {"RawValue", Type, 0}, - {"RawValue.Bytes", Field, 0}, - {"RawValue.Class", Field, 0}, - {"RawValue.FullBytes", Field, 0}, - {"RawValue.IsCompound", Field, 0}, - {"RawValue.Tag", Field, 0}, - {"StructuralError", Type, 0}, - {"StructuralError.Msg", Field, 0}, - {"SyntaxError", Type, 0}, - {"SyntaxError.Msg", Field, 0}, - {"TagBMPString", Const, 14}, - {"TagBitString", Const, 6}, - {"TagBoolean", Const, 6}, - {"TagEnum", Const, 6}, - {"TagGeneralString", Const, 6}, - {"TagGeneralizedTime", Const, 6}, - {"TagIA5String", Const, 6}, - {"TagInteger", Const, 6}, - {"TagNull", Const, 9}, - {"TagNumericString", Const, 10}, - {"TagOID", Const, 6}, - {"TagOctetString", Const, 6}, - {"TagPrintableString", Const, 6}, - {"TagSequence", Const, 6}, - {"TagSet", Const, 6}, - {"TagT61String", Const, 6}, - {"TagUTCTime", Const, 6}, - {"TagUTF8String", Const, 6}, - {"Unmarshal", Func, 0}, - {"UnmarshalWithParams", Func, 0}, + {"(BitString).At", Method, 0, ""}, + {"(BitString).RightAlign", Method, 0, ""}, + {"(ObjectIdentifier).Equal", Method, 0, ""}, + {"(ObjectIdentifier).String", Method, 3, ""}, + {"(StructuralError).Error", Method, 0, ""}, + {"(SyntaxError).Error", Method, 0, ""}, + {"BitString", Type, 0, ""}, + {"BitString.BitLength", Field, 0, ""}, + {"BitString.Bytes", Field, 0, ""}, + {"ClassApplication", Const, 6, ""}, + {"ClassContextSpecific", Const, 6, ""}, + {"ClassPrivate", Const, 6, ""}, + {"ClassUniversal", Const, 6, ""}, + {"Enumerated", Type, 0, ""}, + {"Flag", Type, 0, ""}, + {"Marshal", Func, 0, "func(val any) ([]byte, error)"}, + {"MarshalWithParams", Func, 10, "func(val any, params string) ([]byte, error)"}, + {"NullBytes", Var, 9, ""}, + {"NullRawValue", Var, 9, ""}, + {"ObjectIdentifier", Type, 0, ""}, + {"RawContent", Type, 0, ""}, + {"RawValue", Type, 0, ""}, + {"RawValue.Bytes", Field, 0, ""}, + {"RawValue.Class", Field, 0, ""}, + {"RawValue.FullBytes", Field, 0, ""}, + {"RawValue.IsCompound", Field, 0, ""}, + {"RawValue.Tag", Field, 0, ""}, + {"StructuralError", Type, 0, ""}, + {"StructuralError.Msg", Field, 0, ""}, + {"SyntaxError", Type, 0, ""}, + {"SyntaxError.Msg", Field, 0, ""}, + {"TagBMPString", Const, 14, ""}, + {"TagBitString", Const, 6, ""}, + {"TagBoolean", Const, 6, ""}, + {"TagEnum", Const, 6, ""}, + {"TagGeneralString", Const, 6, ""}, + {"TagGeneralizedTime", Const, 6, ""}, + {"TagIA5String", Const, 6, ""}, + {"TagInteger", Const, 6, ""}, + {"TagNull", Const, 9, ""}, + {"TagNumericString", Const, 10, ""}, + {"TagOID", Const, 6, ""}, + {"TagOctetString", Const, 6, ""}, + {"TagPrintableString", Const, 6, ""}, + {"TagSequence", Const, 6, ""}, + {"TagSet", Const, 6, ""}, + {"TagT61String", Const, 6, ""}, + {"TagUTCTime", Const, 6, ""}, + {"TagUTF8String", Const, 6, ""}, + {"Unmarshal", Func, 0, "func(b []byte, val any) (rest []byte, err error)"}, + {"UnmarshalWithParams", Func, 0, "func(b []byte, val any, params string) (rest []byte, err error)"}, }, "encoding/base32": { - {"(*Encoding).AppendDecode", Method, 22}, - {"(*Encoding).AppendEncode", Method, 22}, - {"(*Encoding).Decode", Method, 0}, - {"(*Encoding).DecodeString", Method, 0}, - {"(*Encoding).DecodedLen", Method, 0}, - {"(*Encoding).Encode", Method, 0}, - {"(*Encoding).EncodeToString", Method, 0}, - {"(*Encoding).EncodedLen", Method, 0}, - {"(CorruptInputError).Error", Method, 0}, - {"(Encoding).WithPadding", Method, 9}, - {"CorruptInputError", Type, 0}, - {"Encoding", Type, 0}, - {"HexEncoding", Var, 0}, - {"NewDecoder", Func, 0}, - {"NewEncoder", Func, 0}, - {"NewEncoding", Func, 0}, - {"NoPadding", Const, 9}, - {"StdEncoding", Var, 0}, - {"StdPadding", Const, 9}, + {"(*Encoding).AppendDecode", Method, 22, ""}, + {"(*Encoding).AppendEncode", Method, 22, ""}, + {"(*Encoding).Decode", Method, 0, ""}, + {"(*Encoding).DecodeString", Method, 0, ""}, + {"(*Encoding).DecodedLen", Method, 0, ""}, + {"(*Encoding).Encode", Method, 0, ""}, + {"(*Encoding).EncodeToString", Method, 0, ""}, + {"(*Encoding).EncodedLen", Method, 0, ""}, + {"(CorruptInputError).Error", Method, 0, ""}, + {"(Encoding).WithPadding", Method, 9, ""}, + {"CorruptInputError", Type, 0, ""}, + {"Encoding", Type, 0, ""}, + {"HexEncoding", Var, 0, ""}, + {"NewDecoder", Func, 0, "func(enc *Encoding, r io.Reader) io.Reader"}, + {"NewEncoder", Func, 0, "func(enc *Encoding, w io.Writer) io.WriteCloser"}, + {"NewEncoding", Func, 0, "func(encoder string) *Encoding"}, + {"NoPadding", Const, 9, ""}, + {"StdEncoding", Var, 0, ""}, + {"StdPadding", Const, 9, ""}, }, "encoding/base64": { - {"(*Encoding).AppendDecode", Method, 22}, - {"(*Encoding).AppendEncode", Method, 22}, - {"(*Encoding).Decode", Method, 0}, - {"(*Encoding).DecodeString", Method, 0}, - {"(*Encoding).DecodedLen", Method, 0}, - {"(*Encoding).Encode", Method, 0}, - {"(*Encoding).EncodeToString", Method, 0}, - {"(*Encoding).EncodedLen", Method, 0}, - {"(CorruptInputError).Error", Method, 0}, - {"(Encoding).Strict", Method, 8}, - {"(Encoding).WithPadding", Method, 5}, - {"CorruptInputError", Type, 0}, - {"Encoding", Type, 0}, - {"NewDecoder", Func, 0}, - {"NewEncoder", Func, 0}, - {"NewEncoding", Func, 0}, - {"NoPadding", Const, 5}, - {"RawStdEncoding", Var, 5}, - {"RawURLEncoding", Var, 5}, - {"StdEncoding", Var, 0}, - {"StdPadding", Const, 5}, - {"URLEncoding", Var, 0}, + {"(*Encoding).AppendDecode", Method, 22, ""}, + {"(*Encoding).AppendEncode", Method, 22, ""}, + {"(*Encoding).Decode", Method, 0, ""}, + {"(*Encoding).DecodeString", Method, 0, ""}, + {"(*Encoding).DecodedLen", Method, 0, ""}, + {"(*Encoding).Encode", Method, 0, ""}, + {"(*Encoding).EncodeToString", Method, 0, ""}, + {"(*Encoding).EncodedLen", Method, 0, ""}, + {"(CorruptInputError).Error", Method, 0, ""}, + {"(Encoding).Strict", Method, 8, ""}, + {"(Encoding).WithPadding", Method, 5, ""}, + {"CorruptInputError", Type, 0, ""}, + {"Encoding", Type, 0, ""}, + {"NewDecoder", Func, 0, "func(enc *Encoding, r io.Reader) io.Reader"}, + {"NewEncoder", Func, 0, "func(enc *Encoding, w io.Writer) io.WriteCloser"}, + {"NewEncoding", Func, 0, "func(encoder string) *Encoding"}, + {"NoPadding", Const, 5, ""}, + {"RawStdEncoding", Var, 5, ""}, + {"RawURLEncoding", Var, 5, ""}, + {"StdEncoding", Var, 0, ""}, + {"StdPadding", Const, 5, ""}, + {"URLEncoding", Var, 0, ""}, }, "encoding/binary": { - {"Append", Func, 23}, - {"AppendByteOrder", Type, 19}, - {"AppendUvarint", Func, 19}, - {"AppendVarint", Func, 19}, - {"BigEndian", Var, 0}, - {"ByteOrder", Type, 0}, - {"Decode", Func, 23}, - {"Encode", Func, 23}, - {"LittleEndian", Var, 0}, - {"MaxVarintLen16", Const, 0}, - {"MaxVarintLen32", Const, 0}, - {"MaxVarintLen64", Const, 0}, - {"NativeEndian", Var, 21}, - {"PutUvarint", Func, 0}, - {"PutVarint", Func, 0}, - {"Read", Func, 0}, - {"ReadUvarint", Func, 0}, - {"ReadVarint", Func, 0}, - {"Size", Func, 0}, - {"Uvarint", Func, 0}, - {"Varint", Func, 0}, - {"Write", Func, 0}, + {"Append", Func, 23, "func(buf []byte, order ByteOrder, data any) ([]byte, error)"}, + {"AppendByteOrder", Type, 19, ""}, + {"AppendUvarint", Func, 19, "func(buf []byte, x uint64) []byte"}, + {"AppendVarint", Func, 19, "func(buf []byte, x int64) []byte"}, + {"BigEndian", Var, 0, ""}, + {"ByteOrder", Type, 0, ""}, + {"Decode", Func, 23, "func(buf []byte, order ByteOrder, data any) (int, error)"}, + {"Encode", Func, 23, "func(buf []byte, order ByteOrder, data any) (int, error)"}, + {"LittleEndian", Var, 0, ""}, + {"MaxVarintLen16", Const, 0, ""}, + {"MaxVarintLen32", Const, 0, ""}, + {"MaxVarintLen64", Const, 0, ""}, + {"NativeEndian", Var, 21, ""}, + {"PutUvarint", Func, 0, "func(buf []byte, x uint64) int"}, + {"PutVarint", Func, 0, "func(buf []byte, x int64) int"}, + {"Read", Func, 0, "func(r io.Reader, order ByteOrder, data any) error"}, + {"ReadUvarint", Func, 0, "func(r io.ByteReader) (uint64, error)"}, + {"ReadVarint", Func, 0, "func(r io.ByteReader) (int64, error)"}, + {"Size", Func, 0, "func(v any) int"}, + {"Uvarint", Func, 0, "func(buf []byte) (uint64, int)"}, + {"Varint", Func, 0, "func(buf []byte) (int64, int)"}, + {"Write", Func, 0, "func(w io.Writer, order ByteOrder, data any) error"}, }, "encoding/csv": { - {"(*ParseError).Error", Method, 0}, - {"(*ParseError).Unwrap", Method, 13}, - {"(*Reader).FieldPos", Method, 17}, - {"(*Reader).InputOffset", Method, 19}, - {"(*Reader).Read", Method, 0}, - {"(*Reader).ReadAll", Method, 0}, - {"(*Writer).Error", Method, 1}, - {"(*Writer).Flush", Method, 0}, - {"(*Writer).Write", Method, 0}, - {"(*Writer).WriteAll", Method, 0}, - {"ErrBareQuote", Var, 0}, - {"ErrFieldCount", Var, 0}, - {"ErrQuote", Var, 0}, - {"ErrTrailingComma", Var, 0}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"ParseError", Type, 0}, - {"ParseError.Column", Field, 0}, - {"ParseError.Err", Field, 0}, - {"ParseError.Line", Field, 0}, - {"ParseError.StartLine", Field, 10}, - {"Reader", Type, 0}, - {"Reader.Comma", Field, 0}, - {"Reader.Comment", Field, 0}, - {"Reader.FieldsPerRecord", Field, 0}, - {"Reader.LazyQuotes", Field, 0}, - {"Reader.ReuseRecord", Field, 9}, - {"Reader.TrailingComma", Field, 0}, - {"Reader.TrimLeadingSpace", Field, 0}, - {"Writer", Type, 0}, - {"Writer.Comma", Field, 0}, - {"Writer.UseCRLF", Field, 0}, + {"(*ParseError).Error", Method, 0, ""}, + {"(*ParseError).Unwrap", Method, 13, ""}, + {"(*Reader).FieldPos", Method, 17, ""}, + {"(*Reader).InputOffset", Method, 19, ""}, + {"(*Reader).Read", Method, 0, ""}, + {"(*Reader).ReadAll", Method, 0, ""}, + {"(*Writer).Error", Method, 1, ""}, + {"(*Writer).Flush", Method, 0, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"(*Writer).WriteAll", Method, 0, ""}, + {"ErrBareQuote", Var, 0, ""}, + {"ErrFieldCount", Var, 0, ""}, + {"ErrQuote", Var, 0, ""}, + {"ErrTrailingComma", Var, 0, ""}, + {"NewReader", Func, 0, "func(r io.Reader) *Reader"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"ParseError", Type, 0, ""}, + {"ParseError.Column", Field, 0, ""}, + {"ParseError.Err", Field, 0, ""}, + {"ParseError.Line", Field, 0, ""}, + {"ParseError.StartLine", Field, 10, ""}, + {"Reader", Type, 0, ""}, + {"Reader.Comma", Field, 0, ""}, + {"Reader.Comment", Field, 0, ""}, + {"Reader.FieldsPerRecord", Field, 0, ""}, + {"Reader.LazyQuotes", Field, 0, ""}, + {"Reader.ReuseRecord", Field, 9, ""}, + {"Reader.TrailingComma", Field, 0, ""}, + {"Reader.TrimLeadingSpace", Field, 0, ""}, + {"Writer", Type, 0, ""}, + {"Writer.Comma", Field, 0, ""}, + {"Writer.UseCRLF", Field, 0, ""}, }, "encoding/gob": { - {"(*Decoder).Decode", Method, 0}, - {"(*Decoder).DecodeValue", Method, 0}, - {"(*Encoder).Encode", Method, 0}, - {"(*Encoder).EncodeValue", Method, 0}, - {"CommonType", Type, 0}, - {"CommonType.Id", Field, 0}, - {"CommonType.Name", Field, 0}, - {"Decoder", Type, 0}, - {"Encoder", Type, 0}, - {"GobDecoder", Type, 0}, - {"GobEncoder", Type, 0}, - {"NewDecoder", Func, 0}, - {"NewEncoder", Func, 0}, - {"Register", Func, 0}, - {"RegisterName", Func, 0}, + {"(*Decoder).Decode", Method, 0, ""}, + {"(*Decoder).DecodeValue", Method, 0, ""}, + {"(*Encoder).Encode", Method, 0, ""}, + {"(*Encoder).EncodeValue", Method, 0, ""}, + {"CommonType", Type, 0, ""}, + {"CommonType.Id", Field, 0, ""}, + {"CommonType.Name", Field, 0, ""}, + {"Decoder", Type, 0, ""}, + {"Encoder", Type, 0, ""}, + {"GobDecoder", Type, 0, ""}, + {"GobEncoder", Type, 0, ""}, + {"NewDecoder", Func, 0, "func(r io.Reader) *Decoder"}, + {"NewEncoder", Func, 0, "func(w io.Writer) *Encoder"}, + {"Register", Func, 0, "func(value any)"}, + {"RegisterName", Func, 0, "func(name string, value any)"}, }, "encoding/hex": { - {"(InvalidByteError).Error", Method, 0}, - {"AppendDecode", Func, 22}, - {"AppendEncode", Func, 22}, - {"Decode", Func, 0}, - {"DecodeString", Func, 0}, - {"DecodedLen", Func, 0}, - {"Dump", Func, 0}, - {"Dumper", Func, 0}, - {"Encode", Func, 0}, - {"EncodeToString", Func, 0}, - {"EncodedLen", Func, 0}, - {"ErrLength", Var, 0}, - {"InvalidByteError", Type, 0}, - {"NewDecoder", Func, 10}, - {"NewEncoder", Func, 10}, + {"(InvalidByteError).Error", Method, 0, ""}, + {"AppendDecode", Func, 22, "func(dst []byte, src []byte) ([]byte, error)"}, + {"AppendEncode", Func, 22, "func(dst []byte, src []byte) []byte"}, + {"Decode", Func, 0, "func(dst []byte, src []byte) (int, error)"}, + {"DecodeString", Func, 0, "func(s string) ([]byte, error)"}, + {"DecodedLen", Func, 0, "func(x int) int"}, + {"Dump", Func, 0, "func(data []byte) string"}, + {"Dumper", Func, 0, "func(w io.Writer) io.WriteCloser"}, + {"Encode", Func, 0, "func(dst []byte, src []byte) int"}, + {"EncodeToString", Func, 0, "func(src []byte) string"}, + {"EncodedLen", Func, 0, "func(n int) int"}, + {"ErrLength", Var, 0, ""}, + {"InvalidByteError", Type, 0, ""}, + {"NewDecoder", Func, 10, "func(r io.Reader) io.Reader"}, + {"NewEncoder", Func, 10, "func(w io.Writer) io.Writer"}, }, "encoding/json": { - {"(*Decoder).Buffered", Method, 1}, - {"(*Decoder).Decode", Method, 0}, - {"(*Decoder).DisallowUnknownFields", Method, 10}, - {"(*Decoder).InputOffset", Method, 14}, - {"(*Decoder).More", Method, 5}, - {"(*Decoder).Token", Method, 5}, - {"(*Decoder).UseNumber", Method, 1}, - {"(*Encoder).Encode", Method, 0}, - {"(*Encoder).SetEscapeHTML", Method, 7}, - {"(*Encoder).SetIndent", Method, 7}, - {"(*InvalidUTF8Error).Error", Method, 0}, - {"(*InvalidUnmarshalError).Error", Method, 0}, - {"(*MarshalerError).Error", Method, 0}, - {"(*MarshalerError).Unwrap", Method, 13}, - {"(*RawMessage).MarshalJSON", Method, 0}, - {"(*RawMessage).UnmarshalJSON", Method, 0}, - {"(*SyntaxError).Error", Method, 0}, - {"(*UnmarshalFieldError).Error", Method, 0}, - {"(*UnmarshalTypeError).Error", Method, 0}, - {"(*UnsupportedTypeError).Error", Method, 0}, - {"(*UnsupportedValueError).Error", Method, 0}, - {"(Delim).String", Method, 5}, - {"(Number).Float64", Method, 1}, - {"(Number).Int64", Method, 1}, - {"(Number).String", Method, 1}, - {"(RawMessage).MarshalJSON", Method, 8}, - {"Compact", Func, 0}, - {"Decoder", Type, 0}, - {"Delim", Type, 5}, - {"Encoder", Type, 0}, - {"HTMLEscape", Func, 0}, - {"Indent", Func, 0}, - {"InvalidUTF8Error", Type, 0}, - {"InvalidUTF8Error.S", Field, 0}, - {"InvalidUnmarshalError", Type, 0}, - {"InvalidUnmarshalError.Type", Field, 0}, - {"Marshal", Func, 0}, - {"MarshalIndent", Func, 0}, - {"Marshaler", Type, 0}, - {"MarshalerError", Type, 0}, - {"MarshalerError.Err", Field, 0}, - {"MarshalerError.Type", Field, 0}, - {"NewDecoder", Func, 0}, - {"NewEncoder", Func, 0}, - {"Number", Type, 1}, - {"RawMessage", Type, 0}, - {"SyntaxError", Type, 0}, - {"SyntaxError.Offset", Field, 0}, - {"Token", Type, 5}, - {"Unmarshal", Func, 0}, - {"UnmarshalFieldError", Type, 0}, - {"UnmarshalFieldError.Field", Field, 0}, - {"UnmarshalFieldError.Key", Field, 0}, - {"UnmarshalFieldError.Type", Field, 0}, - {"UnmarshalTypeError", Type, 0}, - {"UnmarshalTypeError.Field", Field, 8}, - {"UnmarshalTypeError.Offset", Field, 5}, - {"UnmarshalTypeError.Struct", Field, 8}, - {"UnmarshalTypeError.Type", Field, 0}, - {"UnmarshalTypeError.Value", Field, 0}, - {"Unmarshaler", Type, 0}, - {"UnsupportedTypeError", Type, 0}, - {"UnsupportedTypeError.Type", Field, 0}, - {"UnsupportedValueError", Type, 0}, - {"UnsupportedValueError.Str", Field, 0}, - {"UnsupportedValueError.Value", Field, 0}, - {"Valid", Func, 9}, + {"(*Decoder).Buffered", Method, 1, ""}, + {"(*Decoder).Decode", Method, 0, ""}, + {"(*Decoder).DisallowUnknownFields", Method, 10, ""}, + {"(*Decoder).InputOffset", Method, 14, ""}, + {"(*Decoder).More", Method, 5, ""}, + {"(*Decoder).Token", Method, 5, ""}, + {"(*Decoder).UseNumber", Method, 1, ""}, + {"(*Encoder).Encode", Method, 0, ""}, + {"(*Encoder).SetEscapeHTML", Method, 7, ""}, + {"(*Encoder).SetIndent", Method, 7, ""}, + {"(*InvalidUTF8Error).Error", Method, 0, ""}, + {"(*InvalidUnmarshalError).Error", Method, 0, ""}, + {"(*MarshalerError).Error", Method, 0, ""}, + {"(*MarshalerError).Unwrap", Method, 13, ""}, + {"(*RawMessage).MarshalJSON", Method, 0, ""}, + {"(*RawMessage).UnmarshalJSON", Method, 0, ""}, + {"(*SyntaxError).Error", Method, 0, ""}, + {"(*UnmarshalFieldError).Error", Method, 0, ""}, + {"(*UnmarshalTypeError).Error", Method, 0, ""}, + {"(*UnsupportedTypeError).Error", Method, 0, ""}, + {"(*UnsupportedValueError).Error", Method, 0, ""}, + {"(Delim).String", Method, 5, ""}, + {"(Number).Float64", Method, 1, ""}, + {"(Number).Int64", Method, 1, ""}, + {"(Number).String", Method, 1, ""}, + {"(RawMessage).MarshalJSON", Method, 8, ""}, + {"Compact", Func, 0, "func(dst *bytes.Buffer, src []byte) error"}, + {"Decoder", Type, 0, ""}, + {"Delim", Type, 5, ""}, + {"Encoder", Type, 0, ""}, + {"HTMLEscape", Func, 0, "func(dst *bytes.Buffer, src []byte)"}, + {"Indent", Func, 0, "func(dst *bytes.Buffer, src []byte, prefix string, indent string) error"}, + {"InvalidUTF8Error", Type, 0, ""}, + {"InvalidUTF8Error.S", Field, 0, ""}, + {"InvalidUnmarshalError", Type, 0, ""}, + {"InvalidUnmarshalError.Type", Field, 0, ""}, + {"Marshal", Func, 0, "func(v any) ([]byte, error)"}, + {"MarshalIndent", Func, 0, "func(v any, prefix string, indent string) ([]byte, error)"}, + {"Marshaler", Type, 0, ""}, + {"MarshalerError", Type, 0, ""}, + {"MarshalerError.Err", Field, 0, ""}, + {"MarshalerError.Type", Field, 0, ""}, + {"NewDecoder", Func, 0, "func(r io.Reader) *Decoder"}, + {"NewEncoder", Func, 0, "func(w io.Writer) *Encoder"}, + {"Number", Type, 1, ""}, + {"RawMessage", Type, 0, ""}, + {"SyntaxError", Type, 0, ""}, + {"SyntaxError.Offset", Field, 0, ""}, + {"Token", Type, 5, ""}, + {"Unmarshal", Func, 0, "func(data []byte, v any) error"}, + {"UnmarshalFieldError", Type, 0, ""}, + {"UnmarshalFieldError.Field", Field, 0, ""}, + {"UnmarshalFieldError.Key", Field, 0, ""}, + {"UnmarshalFieldError.Type", Field, 0, ""}, + {"UnmarshalTypeError", Type, 0, ""}, + {"UnmarshalTypeError.Field", Field, 8, ""}, + {"UnmarshalTypeError.Offset", Field, 5, ""}, + {"UnmarshalTypeError.Struct", Field, 8, ""}, + {"UnmarshalTypeError.Type", Field, 0, ""}, + {"UnmarshalTypeError.Value", Field, 0, ""}, + {"Unmarshaler", Type, 0, ""}, + {"UnsupportedTypeError", Type, 0, ""}, + {"UnsupportedTypeError.Type", Field, 0, ""}, + {"UnsupportedValueError", Type, 0, ""}, + {"UnsupportedValueError.Str", Field, 0, ""}, + {"UnsupportedValueError.Value", Field, 0, ""}, + {"Valid", Func, 9, "func(data []byte) bool"}, }, "encoding/pem": { - {"Block", Type, 0}, - {"Block.Bytes", Field, 0}, - {"Block.Headers", Field, 0}, - {"Block.Type", Field, 0}, - {"Decode", Func, 0}, - {"Encode", Func, 0}, - {"EncodeToMemory", Func, 0}, + {"Block", Type, 0, ""}, + {"Block.Bytes", Field, 0, ""}, + {"Block.Headers", Field, 0, ""}, + {"Block.Type", Field, 0, ""}, + {"Decode", Func, 0, "func(data []byte) (p *Block, rest []byte)"}, + {"Encode", Func, 0, "func(out io.Writer, b *Block) error"}, + {"EncodeToMemory", Func, 0, "func(b *Block) []byte"}, }, "encoding/xml": { - {"(*Decoder).Decode", Method, 0}, - {"(*Decoder).DecodeElement", Method, 0}, - {"(*Decoder).InputOffset", Method, 4}, - {"(*Decoder).InputPos", Method, 19}, - {"(*Decoder).RawToken", Method, 0}, - {"(*Decoder).Skip", Method, 0}, - {"(*Decoder).Token", Method, 0}, - {"(*Encoder).Close", Method, 20}, - {"(*Encoder).Encode", Method, 0}, - {"(*Encoder).EncodeElement", Method, 2}, - {"(*Encoder).EncodeToken", Method, 2}, - {"(*Encoder).Flush", Method, 2}, - {"(*Encoder).Indent", Method, 1}, - {"(*SyntaxError).Error", Method, 0}, - {"(*TagPathError).Error", Method, 0}, - {"(*UnsupportedTypeError).Error", Method, 0}, - {"(CharData).Copy", Method, 0}, - {"(Comment).Copy", Method, 0}, - {"(Directive).Copy", Method, 0}, - {"(ProcInst).Copy", Method, 0}, - {"(StartElement).Copy", Method, 0}, - {"(StartElement).End", Method, 2}, - {"(UnmarshalError).Error", Method, 0}, - {"Attr", Type, 0}, - {"Attr.Name", Field, 0}, - {"Attr.Value", Field, 0}, - {"CharData", Type, 0}, - {"Comment", Type, 0}, - {"CopyToken", Func, 0}, - {"Decoder", Type, 0}, - {"Decoder.AutoClose", Field, 0}, - {"Decoder.CharsetReader", Field, 0}, - {"Decoder.DefaultSpace", Field, 1}, - {"Decoder.Entity", Field, 0}, - {"Decoder.Strict", Field, 0}, - {"Directive", Type, 0}, - {"Encoder", Type, 0}, - {"EndElement", Type, 0}, - {"EndElement.Name", Field, 0}, - {"Escape", Func, 0}, - {"EscapeText", Func, 1}, - {"HTMLAutoClose", Var, 0}, - {"HTMLEntity", Var, 0}, - {"Header", Const, 0}, - {"Marshal", Func, 0}, - {"MarshalIndent", Func, 0}, - {"Marshaler", Type, 2}, - {"MarshalerAttr", Type, 2}, - {"Name", Type, 0}, - {"Name.Local", Field, 0}, - {"Name.Space", Field, 0}, - {"NewDecoder", Func, 0}, - {"NewEncoder", Func, 0}, - {"NewTokenDecoder", Func, 10}, - {"ProcInst", Type, 0}, - {"ProcInst.Inst", Field, 0}, - {"ProcInst.Target", Field, 0}, - {"StartElement", Type, 0}, - {"StartElement.Attr", Field, 0}, - {"StartElement.Name", Field, 0}, - {"SyntaxError", Type, 0}, - {"SyntaxError.Line", Field, 0}, - {"SyntaxError.Msg", Field, 0}, - {"TagPathError", Type, 0}, - {"TagPathError.Field1", Field, 0}, - {"TagPathError.Field2", Field, 0}, - {"TagPathError.Struct", Field, 0}, - {"TagPathError.Tag1", Field, 0}, - {"TagPathError.Tag2", Field, 0}, - {"Token", Type, 0}, - {"TokenReader", Type, 10}, - {"Unmarshal", Func, 0}, - {"UnmarshalError", Type, 0}, - {"Unmarshaler", Type, 2}, - {"UnmarshalerAttr", Type, 2}, - {"UnsupportedTypeError", Type, 0}, - {"UnsupportedTypeError.Type", Field, 0}, + {"(*Decoder).Decode", Method, 0, ""}, + {"(*Decoder).DecodeElement", Method, 0, ""}, + {"(*Decoder).InputOffset", Method, 4, ""}, + {"(*Decoder).InputPos", Method, 19, ""}, + {"(*Decoder).RawToken", Method, 0, ""}, + {"(*Decoder).Skip", Method, 0, ""}, + {"(*Decoder).Token", Method, 0, ""}, + {"(*Encoder).Close", Method, 20, ""}, + {"(*Encoder).Encode", Method, 0, ""}, + {"(*Encoder).EncodeElement", Method, 2, ""}, + {"(*Encoder).EncodeToken", Method, 2, ""}, + {"(*Encoder).Flush", Method, 2, ""}, + {"(*Encoder).Indent", Method, 1, ""}, + {"(*SyntaxError).Error", Method, 0, ""}, + {"(*TagPathError).Error", Method, 0, ""}, + {"(*UnsupportedTypeError).Error", Method, 0, ""}, + {"(CharData).Copy", Method, 0, ""}, + {"(Comment).Copy", Method, 0, ""}, + {"(Directive).Copy", Method, 0, ""}, + {"(ProcInst).Copy", Method, 0, ""}, + {"(StartElement).Copy", Method, 0, ""}, + {"(StartElement).End", Method, 2, ""}, + {"(UnmarshalError).Error", Method, 0, ""}, + {"Attr", Type, 0, ""}, + {"Attr.Name", Field, 0, ""}, + {"Attr.Value", Field, 0, ""}, + {"CharData", Type, 0, ""}, + {"Comment", Type, 0, ""}, + {"CopyToken", Func, 0, "func(t Token) Token"}, + {"Decoder", Type, 0, ""}, + {"Decoder.AutoClose", Field, 0, ""}, + {"Decoder.CharsetReader", Field, 0, ""}, + {"Decoder.DefaultSpace", Field, 1, ""}, + {"Decoder.Entity", Field, 0, ""}, + {"Decoder.Strict", Field, 0, ""}, + {"Directive", Type, 0, ""}, + {"Encoder", Type, 0, ""}, + {"EndElement", Type, 0, ""}, + {"EndElement.Name", Field, 0, ""}, + {"Escape", Func, 0, "func(w io.Writer, s []byte)"}, + {"EscapeText", Func, 1, "func(w io.Writer, s []byte) error"}, + {"HTMLAutoClose", Var, 0, ""}, + {"HTMLEntity", Var, 0, ""}, + {"Header", Const, 0, ""}, + {"Marshal", Func, 0, "func(v any) ([]byte, error)"}, + {"MarshalIndent", Func, 0, "func(v any, prefix string, indent string) ([]byte, error)"}, + {"Marshaler", Type, 2, ""}, + {"MarshalerAttr", Type, 2, ""}, + {"Name", Type, 0, ""}, + {"Name.Local", Field, 0, ""}, + {"Name.Space", Field, 0, ""}, + {"NewDecoder", Func, 0, "func(r io.Reader) *Decoder"}, + {"NewEncoder", Func, 0, "func(w io.Writer) *Encoder"}, + {"NewTokenDecoder", Func, 10, "func(t TokenReader) *Decoder"}, + {"ProcInst", Type, 0, ""}, + {"ProcInst.Inst", Field, 0, ""}, + {"ProcInst.Target", Field, 0, ""}, + {"StartElement", Type, 0, ""}, + {"StartElement.Attr", Field, 0, ""}, + {"StartElement.Name", Field, 0, ""}, + {"SyntaxError", Type, 0, ""}, + {"SyntaxError.Line", Field, 0, ""}, + {"SyntaxError.Msg", Field, 0, ""}, + {"TagPathError", Type, 0, ""}, + {"TagPathError.Field1", Field, 0, ""}, + {"TagPathError.Field2", Field, 0, ""}, + {"TagPathError.Struct", Field, 0, ""}, + {"TagPathError.Tag1", Field, 0, ""}, + {"TagPathError.Tag2", Field, 0, ""}, + {"Token", Type, 0, ""}, + {"TokenReader", Type, 10, ""}, + {"Unmarshal", Func, 0, "func(data []byte, v any) error"}, + {"UnmarshalError", Type, 0, ""}, + {"Unmarshaler", Type, 2, ""}, + {"UnmarshalerAttr", Type, 2, ""}, + {"UnsupportedTypeError", Type, 0, ""}, + {"UnsupportedTypeError.Type", Field, 0, ""}, }, "errors": { - {"As", Func, 13}, - {"ErrUnsupported", Var, 21}, - {"Is", Func, 13}, - {"Join", Func, 20}, - {"New", Func, 0}, - {"Unwrap", Func, 13}, + {"As", Func, 13, "func(err error, target any) bool"}, + {"ErrUnsupported", Var, 21, ""}, + {"Is", Func, 13, "func(err error, target error) bool"}, + {"Join", Func, 20, "func(errs ...error) error"}, + {"New", Func, 0, "func(text string) error"}, + {"Unwrap", Func, 13, "func(err error) error"}, }, "expvar": { - {"(*Float).Add", Method, 0}, - {"(*Float).Set", Method, 0}, - {"(*Float).String", Method, 0}, - {"(*Float).Value", Method, 8}, - {"(*Int).Add", Method, 0}, - {"(*Int).Set", Method, 0}, - {"(*Int).String", Method, 0}, - {"(*Int).Value", Method, 8}, - {"(*Map).Add", Method, 0}, - {"(*Map).AddFloat", Method, 0}, - {"(*Map).Delete", Method, 12}, - {"(*Map).Do", Method, 0}, - {"(*Map).Get", Method, 0}, - {"(*Map).Init", Method, 0}, - {"(*Map).Set", Method, 0}, - {"(*Map).String", Method, 0}, - {"(*String).Set", Method, 0}, - {"(*String).String", Method, 0}, - {"(*String).Value", Method, 8}, - {"(Func).String", Method, 0}, - {"(Func).Value", Method, 8}, - {"Do", Func, 0}, - {"Float", Type, 0}, - {"Func", Type, 0}, - {"Get", Func, 0}, - {"Handler", Func, 8}, - {"Int", Type, 0}, - {"KeyValue", Type, 0}, - {"KeyValue.Key", Field, 0}, - {"KeyValue.Value", Field, 0}, - {"Map", Type, 0}, - {"NewFloat", Func, 0}, - {"NewInt", Func, 0}, - {"NewMap", Func, 0}, - {"NewString", Func, 0}, - {"Publish", Func, 0}, - {"String", Type, 0}, - {"Var", Type, 0}, + {"(*Float).Add", Method, 0, ""}, + {"(*Float).Set", Method, 0, ""}, + {"(*Float).String", Method, 0, ""}, + {"(*Float).Value", Method, 8, ""}, + {"(*Int).Add", Method, 0, ""}, + {"(*Int).Set", Method, 0, ""}, + {"(*Int).String", Method, 0, ""}, + {"(*Int).Value", Method, 8, ""}, + {"(*Map).Add", Method, 0, ""}, + {"(*Map).AddFloat", Method, 0, ""}, + {"(*Map).Delete", Method, 12, ""}, + {"(*Map).Do", Method, 0, ""}, + {"(*Map).Get", Method, 0, ""}, + {"(*Map).Init", Method, 0, ""}, + {"(*Map).Set", Method, 0, ""}, + {"(*Map).String", Method, 0, ""}, + {"(*String).Set", Method, 0, ""}, + {"(*String).String", Method, 0, ""}, + {"(*String).Value", Method, 8, ""}, + {"(Func).String", Method, 0, ""}, + {"(Func).Value", Method, 8, ""}, + {"Do", Func, 0, "func(f func(KeyValue))"}, + {"Float", Type, 0, ""}, + {"Func", Type, 0, ""}, + {"Get", Func, 0, "func(name string) Var"}, + {"Handler", Func, 8, "func() http.Handler"}, + {"Int", Type, 0, ""}, + {"KeyValue", Type, 0, ""}, + {"KeyValue.Key", Field, 0, ""}, + {"KeyValue.Value", Field, 0, ""}, + {"Map", Type, 0, ""}, + {"NewFloat", Func, 0, "func(name string) *Float"}, + {"NewInt", Func, 0, "func(name string) *Int"}, + {"NewMap", Func, 0, "func(name string) *Map"}, + {"NewString", Func, 0, "func(name string) *String"}, + {"Publish", Func, 0, "func(name string, v Var)"}, + {"String", Type, 0, ""}, + {"Var", Type, 0, ""}, }, "flag": { - {"(*FlagSet).Arg", Method, 0}, - {"(*FlagSet).Args", Method, 0}, - {"(*FlagSet).Bool", Method, 0}, - {"(*FlagSet).BoolFunc", Method, 21}, - {"(*FlagSet).BoolVar", Method, 0}, - {"(*FlagSet).Duration", Method, 0}, - {"(*FlagSet).DurationVar", Method, 0}, - {"(*FlagSet).ErrorHandling", Method, 10}, - {"(*FlagSet).Float64", Method, 0}, - {"(*FlagSet).Float64Var", Method, 0}, - {"(*FlagSet).Func", Method, 16}, - {"(*FlagSet).Init", Method, 0}, - {"(*FlagSet).Int", Method, 0}, - {"(*FlagSet).Int64", Method, 0}, - {"(*FlagSet).Int64Var", Method, 0}, - {"(*FlagSet).IntVar", Method, 0}, - {"(*FlagSet).Lookup", Method, 0}, - {"(*FlagSet).NArg", Method, 0}, - {"(*FlagSet).NFlag", Method, 0}, - {"(*FlagSet).Name", Method, 10}, - {"(*FlagSet).Output", Method, 10}, - {"(*FlagSet).Parse", Method, 0}, - {"(*FlagSet).Parsed", Method, 0}, - {"(*FlagSet).PrintDefaults", Method, 0}, - {"(*FlagSet).Set", Method, 0}, - {"(*FlagSet).SetOutput", Method, 0}, - {"(*FlagSet).String", Method, 0}, - {"(*FlagSet).StringVar", Method, 0}, - {"(*FlagSet).TextVar", Method, 19}, - {"(*FlagSet).Uint", Method, 0}, - {"(*FlagSet).Uint64", Method, 0}, - {"(*FlagSet).Uint64Var", Method, 0}, - {"(*FlagSet).UintVar", Method, 0}, - {"(*FlagSet).Var", Method, 0}, - {"(*FlagSet).Visit", Method, 0}, - {"(*FlagSet).VisitAll", Method, 0}, - {"Arg", Func, 0}, - {"Args", Func, 0}, - {"Bool", Func, 0}, - {"BoolFunc", Func, 21}, - {"BoolVar", Func, 0}, - {"CommandLine", Var, 2}, - {"ContinueOnError", Const, 0}, - {"Duration", Func, 0}, - {"DurationVar", Func, 0}, - {"ErrHelp", Var, 0}, - {"ErrorHandling", Type, 0}, - {"ExitOnError", Const, 0}, - {"Flag", Type, 0}, - {"Flag.DefValue", Field, 0}, - {"Flag.Name", Field, 0}, - {"Flag.Usage", Field, 0}, - {"Flag.Value", Field, 0}, - {"FlagSet", Type, 0}, - {"FlagSet.Usage", Field, 0}, - {"Float64", Func, 0}, - {"Float64Var", Func, 0}, - {"Func", Func, 16}, - {"Getter", Type, 2}, - {"Int", Func, 0}, - {"Int64", Func, 0}, - {"Int64Var", Func, 0}, - {"IntVar", Func, 0}, - {"Lookup", Func, 0}, - {"NArg", Func, 0}, - {"NFlag", Func, 0}, - {"NewFlagSet", Func, 0}, - {"PanicOnError", Const, 0}, - {"Parse", Func, 0}, - {"Parsed", Func, 0}, - {"PrintDefaults", Func, 0}, - {"Set", Func, 0}, - {"String", Func, 0}, - {"StringVar", Func, 0}, - {"TextVar", Func, 19}, - {"Uint", Func, 0}, - {"Uint64", Func, 0}, - {"Uint64Var", Func, 0}, - {"UintVar", Func, 0}, - {"UnquoteUsage", Func, 5}, - {"Usage", Var, 0}, - {"Value", Type, 0}, - {"Var", Func, 0}, - {"Visit", Func, 0}, - {"VisitAll", Func, 0}, + {"(*FlagSet).Arg", Method, 0, ""}, + {"(*FlagSet).Args", Method, 0, ""}, + {"(*FlagSet).Bool", Method, 0, ""}, + {"(*FlagSet).BoolFunc", Method, 21, ""}, + {"(*FlagSet).BoolVar", Method, 0, ""}, + {"(*FlagSet).Duration", Method, 0, ""}, + {"(*FlagSet).DurationVar", Method, 0, ""}, + {"(*FlagSet).ErrorHandling", Method, 10, ""}, + {"(*FlagSet).Float64", Method, 0, ""}, + {"(*FlagSet).Float64Var", Method, 0, ""}, + {"(*FlagSet).Func", Method, 16, ""}, + {"(*FlagSet).Init", Method, 0, ""}, + {"(*FlagSet).Int", Method, 0, ""}, + {"(*FlagSet).Int64", Method, 0, ""}, + {"(*FlagSet).Int64Var", Method, 0, ""}, + {"(*FlagSet).IntVar", Method, 0, ""}, + {"(*FlagSet).Lookup", Method, 0, ""}, + {"(*FlagSet).NArg", Method, 0, ""}, + {"(*FlagSet).NFlag", Method, 0, ""}, + {"(*FlagSet).Name", Method, 10, ""}, + {"(*FlagSet).Output", Method, 10, ""}, + {"(*FlagSet).Parse", Method, 0, ""}, + {"(*FlagSet).Parsed", Method, 0, ""}, + {"(*FlagSet).PrintDefaults", Method, 0, ""}, + {"(*FlagSet).Set", Method, 0, ""}, + {"(*FlagSet).SetOutput", Method, 0, ""}, + {"(*FlagSet).String", Method, 0, ""}, + {"(*FlagSet).StringVar", Method, 0, ""}, + {"(*FlagSet).TextVar", Method, 19, ""}, + {"(*FlagSet).Uint", Method, 0, ""}, + {"(*FlagSet).Uint64", Method, 0, ""}, + {"(*FlagSet).Uint64Var", Method, 0, ""}, + {"(*FlagSet).UintVar", Method, 0, ""}, + {"(*FlagSet).Var", Method, 0, ""}, + {"(*FlagSet).Visit", Method, 0, ""}, + {"(*FlagSet).VisitAll", Method, 0, ""}, + {"Arg", Func, 0, "func(i int) string"}, + {"Args", Func, 0, "func() []string"}, + {"Bool", Func, 0, "func(name string, value bool, usage string) *bool"}, + {"BoolFunc", Func, 21, "func(name string, usage string, fn func(string) error)"}, + {"BoolVar", Func, 0, "func(p *bool, name string, value bool, usage string)"}, + {"CommandLine", Var, 2, ""}, + {"ContinueOnError", Const, 0, ""}, + {"Duration", Func, 0, "func(name string, value time.Duration, usage string) *time.Duration"}, + {"DurationVar", Func, 0, "func(p *time.Duration, name string, value time.Duration, usage string)"}, + {"ErrHelp", Var, 0, ""}, + {"ErrorHandling", Type, 0, ""}, + {"ExitOnError", Const, 0, ""}, + {"Flag", Type, 0, ""}, + {"Flag.DefValue", Field, 0, ""}, + {"Flag.Name", Field, 0, ""}, + {"Flag.Usage", Field, 0, ""}, + {"Flag.Value", Field, 0, ""}, + {"FlagSet", Type, 0, ""}, + {"FlagSet.Usage", Field, 0, ""}, + {"Float64", Func, 0, "func(name string, value float64, usage string) *float64"}, + {"Float64Var", Func, 0, "func(p *float64, name string, value float64, usage string)"}, + {"Func", Func, 16, "func(name string, usage string, fn func(string) error)"}, + {"Getter", Type, 2, ""}, + {"Int", Func, 0, "func(name string, value int, usage string) *int"}, + {"Int64", Func, 0, "func(name string, value int64, usage string) *int64"}, + {"Int64Var", Func, 0, "func(p *int64, name string, value int64, usage string)"}, + {"IntVar", Func, 0, "func(p *int, name string, value int, usage string)"}, + {"Lookup", Func, 0, "func(name string) *Flag"}, + {"NArg", Func, 0, "func() int"}, + {"NFlag", Func, 0, "func() int"}, + {"NewFlagSet", Func, 0, "func(name string, errorHandling ErrorHandling) *FlagSet"}, + {"PanicOnError", Const, 0, ""}, + {"Parse", Func, 0, "func()"}, + {"Parsed", Func, 0, "func() bool"}, + {"PrintDefaults", Func, 0, "func()"}, + {"Set", Func, 0, "func(name string, value string) error"}, + {"String", Func, 0, "func(name string, value string, usage string) *string"}, + {"StringVar", Func, 0, "func(p *string, name string, value string, usage string)"}, + {"TextVar", Func, 19, "func(p encoding.TextUnmarshaler, name string, value encoding.TextMarshaler, usage string)"}, + {"Uint", Func, 0, "func(name string, value uint, usage string) *uint"}, + {"Uint64", Func, 0, "func(name string, value uint64, usage string) *uint64"}, + {"Uint64Var", Func, 0, "func(p *uint64, name string, value uint64, usage string)"}, + {"UintVar", Func, 0, "func(p *uint, name string, value uint, usage string)"}, + {"UnquoteUsage", Func, 5, "func(flag *Flag) (name string, usage string)"}, + {"Usage", Var, 0, ""}, + {"Value", Type, 0, ""}, + {"Var", Func, 0, "func(value Value, name string, usage string)"}, + {"Visit", Func, 0, "func(fn func(*Flag))"}, + {"VisitAll", Func, 0, "func(fn func(*Flag))"}, }, "fmt": { - {"Append", Func, 19}, - {"Appendf", Func, 19}, - {"Appendln", Func, 19}, - {"Errorf", Func, 0}, - {"FormatString", Func, 20}, - {"Formatter", Type, 0}, - {"Fprint", Func, 0}, - {"Fprintf", Func, 0}, - {"Fprintln", Func, 0}, - {"Fscan", Func, 0}, - {"Fscanf", Func, 0}, - {"Fscanln", Func, 0}, - {"GoStringer", Type, 0}, - {"Print", Func, 0}, - {"Printf", Func, 0}, - {"Println", Func, 0}, - {"Scan", Func, 0}, - {"ScanState", Type, 0}, - {"Scanf", Func, 0}, - {"Scanln", Func, 0}, - {"Scanner", Type, 0}, - {"Sprint", Func, 0}, - {"Sprintf", Func, 0}, - {"Sprintln", Func, 0}, - {"Sscan", Func, 0}, - {"Sscanf", Func, 0}, - {"Sscanln", Func, 0}, - {"State", Type, 0}, - {"Stringer", Type, 0}, + {"Append", Func, 19, "func(b []byte, a ...any) []byte"}, + {"Appendf", Func, 19, "func(b []byte, format string, a ...any) []byte"}, + {"Appendln", Func, 19, "func(b []byte, a ...any) []byte"}, + {"Errorf", Func, 0, "func(format string, a ...any) error"}, + {"FormatString", Func, 20, "func(state State, verb rune) string"}, + {"Formatter", Type, 0, ""}, + {"Fprint", Func, 0, "func(w io.Writer, a ...any) (n int, err error)"}, + {"Fprintf", Func, 0, "func(w io.Writer, format string, a ...any) (n int, err error)"}, + {"Fprintln", Func, 0, "func(w io.Writer, a ...any) (n int, err error)"}, + {"Fscan", Func, 0, "func(r io.Reader, a ...any) (n int, err error)"}, + {"Fscanf", Func, 0, "func(r io.Reader, format string, a ...any) (n int, err error)"}, + {"Fscanln", Func, 0, "func(r io.Reader, a ...any) (n int, err error)"}, + {"GoStringer", Type, 0, ""}, + {"Print", Func, 0, "func(a ...any) (n int, err error)"}, + {"Printf", Func, 0, "func(format string, a ...any) (n int, err error)"}, + {"Println", Func, 0, "func(a ...any) (n int, err error)"}, + {"Scan", Func, 0, "func(a ...any) (n int, err error)"}, + {"ScanState", Type, 0, ""}, + {"Scanf", Func, 0, "func(format string, a ...any) (n int, err error)"}, + {"Scanln", Func, 0, "func(a ...any) (n int, err error)"}, + {"Scanner", Type, 0, ""}, + {"Sprint", Func, 0, "func(a ...any) string"}, + {"Sprintf", Func, 0, "func(format string, a ...any) string"}, + {"Sprintln", Func, 0, "func(a ...any) string"}, + {"Sscan", Func, 0, "func(str string, a ...any) (n int, err error)"}, + {"Sscanf", Func, 0, "func(str string, format string, a ...any) (n int, err error)"}, + {"Sscanln", Func, 0, "func(str string, a ...any) (n int, err error)"}, + {"State", Type, 0, ""}, + {"Stringer", Type, 0, ""}, }, "go/ast": { - {"(*ArrayType).End", Method, 0}, - {"(*ArrayType).Pos", Method, 0}, - {"(*AssignStmt).End", Method, 0}, - {"(*AssignStmt).Pos", Method, 0}, - {"(*BadDecl).End", Method, 0}, - {"(*BadDecl).Pos", Method, 0}, - {"(*BadExpr).End", Method, 0}, - {"(*BadExpr).Pos", Method, 0}, - {"(*BadStmt).End", Method, 0}, - {"(*BadStmt).Pos", Method, 0}, - {"(*BasicLit).End", Method, 0}, - {"(*BasicLit).Pos", Method, 0}, - {"(*BinaryExpr).End", Method, 0}, - {"(*BinaryExpr).Pos", Method, 0}, - {"(*BlockStmt).End", Method, 0}, - {"(*BlockStmt).Pos", Method, 0}, - {"(*BranchStmt).End", Method, 0}, - {"(*BranchStmt).Pos", Method, 0}, - {"(*CallExpr).End", Method, 0}, - {"(*CallExpr).Pos", Method, 0}, - {"(*CaseClause).End", Method, 0}, - {"(*CaseClause).Pos", Method, 0}, - {"(*ChanType).End", Method, 0}, - {"(*ChanType).Pos", Method, 0}, - {"(*CommClause).End", Method, 0}, - {"(*CommClause).Pos", Method, 0}, - {"(*Comment).End", Method, 0}, - {"(*Comment).Pos", Method, 0}, - {"(*CommentGroup).End", Method, 0}, - {"(*CommentGroup).Pos", Method, 0}, - {"(*CommentGroup).Text", Method, 0}, - {"(*CompositeLit).End", Method, 0}, - {"(*CompositeLit).Pos", Method, 0}, - {"(*DeclStmt).End", Method, 0}, - {"(*DeclStmt).Pos", Method, 0}, - {"(*DeferStmt).End", Method, 0}, - {"(*DeferStmt).Pos", Method, 0}, - {"(*Ellipsis).End", Method, 0}, - {"(*Ellipsis).Pos", Method, 0}, - {"(*EmptyStmt).End", Method, 0}, - {"(*EmptyStmt).Pos", Method, 0}, - {"(*ExprStmt).End", Method, 0}, - {"(*ExprStmt).Pos", Method, 0}, - {"(*Field).End", Method, 0}, - {"(*Field).Pos", Method, 0}, - {"(*FieldList).End", Method, 0}, - {"(*FieldList).NumFields", Method, 0}, - {"(*FieldList).Pos", Method, 0}, - {"(*File).End", Method, 0}, - {"(*File).Pos", Method, 0}, - {"(*ForStmt).End", Method, 0}, - {"(*ForStmt).Pos", Method, 0}, - {"(*FuncDecl).End", Method, 0}, - {"(*FuncDecl).Pos", Method, 0}, - {"(*FuncLit).End", Method, 0}, - {"(*FuncLit).Pos", Method, 0}, - {"(*FuncType).End", Method, 0}, - {"(*FuncType).Pos", Method, 0}, - {"(*GenDecl).End", Method, 0}, - {"(*GenDecl).Pos", Method, 0}, - {"(*GoStmt).End", Method, 0}, - {"(*GoStmt).Pos", Method, 0}, - {"(*Ident).End", Method, 0}, - {"(*Ident).IsExported", Method, 0}, - {"(*Ident).Pos", Method, 0}, - {"(*Ident).String", Method, 0}, - {"(*IfStmt).End", Method, 0}, - {"(*IfStmt).Pos", Method, 0}, - {"(*ImportSpec).End", Method, 0}, - {"(*ImportSpec).Pos", Method, 0}, - {"(*IncDecStmt).End", Method, 0}, - {"(*IncDecStmt).Pos", Method, 0}, - {"(*IndexExpr).End", Method, 0}, - {"(*IndexExpr).Pos", Method, 0}, - {"(*IndexListExpr).End", Method, 18}, - {"(*IndexListExpr).Pos", Method, 18}, - {"(*InterfaceType).End", Method, 0}, - {"(*InterfaceType).Pos", Method, 0}, - {"(*KeyValueExpr).End", Method, 0}, - {"(*KeyValueExpr).Pos", Method, 0}, - {"(*LabeledStmt).End", Method, 0}, - {"(*LabeledStmt).Pos", Method, 0}, - {"(*MapType).End", Method, 0}, - {"(*MapType).Pos", Method, 0}, - {"(*Object).Pos", Method, 0}, - {"(*Package).End", Method, 0}, - {"(*Package).Pos", Method, 0}, - {"(*ParenExpr).End", Method, 0}, - {"(*ParenExpr).Pos", Method, 0}, - {"(*RangeStmt).End", Method, 0}, - {"(*RangeStmt).Pos", Method, 0}, - {"(*ReturnStmt).End", Method, 0}, - {"(*ReturnStmt).Pos", Method, 0}, - {"(*Scope).Insert", Method, 0}, - {"(*Scope).Lookup", Method, 0}, - {"(*Scope).String", Method, 0}, - {"(*SelectStmt).End", Method, 0}, - {"(*SelectStmt).Pos", Method, 0}, - {"(*SelectorExpr).End", Method, 0}, - {"(*SelectorExpr).Pos", Method, 0}, - {"(*SendStmt).End", Method, 0}, - {"(*SendStmt).Pos", Method, 0}, - {"(*SliceExpr).End", Method, 0}, - {"(*SliceExpr).Pos", Method, 0}, - {"(*StarExpr).End", Method, 0}, - {"(*StarExpr).Pos", Method, 0}, - {"(*StructType).End", Method, 0}, - {"(*StructType).Pos", Method, 0}, - {"(*SwitchStmt).End", Method, 0}, - {"(*SwitchStmt).Pos", Method, 0}, - {"(*TypeAssertExpr).End", Method, 0}, - {"(*TypeAssertExpr).Pos", Method, 0}, - {"(*TypeSpec).End", Method, 0}, - {"(*TypeSpec).Pos", Method, 0}, - {"(*TypeSwitchStmt).End", Method, 0}, - {"(*TypeSwitchStmt).Pos", Method, 0}, - {"(*UnaryExpr).End", Method, 0}, - {"(*UnaryExpr).Pos", Method, 0}, - {"(*ValueSpec).End", Method, 0}, - {"(*ValueSpec).Pos", Method, 0}, - {"(CommentMap).Comments", Method, 1}, - {"(CommentMap).Filter", Method, 1}, - {"(CommentMap).String", Method, 1}, - {"(CommentMap).Update", Method, 1}, - {"(ObjKind).String", Method, 0}, - {"ArrayType", Type, 0}, - {"ArrayType.Elt", Field, 0}, - {"ArrayType.Lbrack", Field, 0}, - {"ArrayType.Len", Field, 0}, - {"AssignStmt", Type, 0}, - {"AssignStmt.Lhs", Field, 0}, - {"AssignStmt.Rhs", Field, 0}, - {"AssignStmt.Tok", Field, 0}, - {"AssignStmt.TokPos", Field, 0}, - {"Bad", Const, 0}, - {"BadDecl", Type, 0}, - {"BadDecl.From", Field, 0}, - {"BadDecl.To", Field, 0}, - {"BadExpr", Type, 0}, - {"BadExpr.From", Field, 0}, - {"BadExpr.To", Field, 0}, - {"BadStmt", Type, 0}, - {"BadStmt.From", Field, 0}, - {"BadStmt.To", Field, 0}, - {"BasicLit", Type, 0}, - {"BasicLit.Kind", Field, 0}, - {"BasicLit.Value", Field, 0}, - {"BasicLit.ValuePos", Field, 0}, - {"BinaryExpr", Type, 0}, - {"BinaryExpr.Op", Field, 0}, - {"BinaryExpr.OpPos", Field, 0}, - {"BinaryExpr.X", Field, 0}, - {"BinaryExpr.Y", Field, 0}, - {"BlockStmt", Type, 0}, - {"BlockStmt.Lbrace", Field, 0}, - {"BlockStmt.List", Field, 0}, - {"BlockStmt.Rbrace", Field, 0}, - {"BranchStmt", Type, 0}, - {"BranchStmt.Label", Field, 0}, - {"BranchStmt.Tok", Field, 0}, - {"BranchStmt.TokPos", Field, 0}, - {"CallExpr", Type, 0}, - {"CallExpr.Args", Field, 0}, - {"CallExpr.Ellipsis", Field, 0}, - {"CallExpr.Fun", Field, 0}, - {"CallExpr.Lparen", Field, 0}, - {"CallExpr.Rparen", Field, 0}, - {"CaseClause", Type, 0}, - {"CaseClause.Body", Field, 0}, - {"CaseClause.Case", Field, 0}, - {"CaseClause.Colon", Field, 0}, - {"CaseClause.List", Field, 0}, - {"ChanDir", Type, 0}, - {"ChanType", Type, 0}, - {"ChanType.Arrow", Field, 1}, - {"ChanType.Begin", Field, 0}, - {"ChanType.Dir", Field, 0}, - {"ChanType.Value", Field, 0}, - {"CommClause", Type, 0}, - {"CommClause.Body", Field, 0}, - {"CommClause.Case", Field, 0}, - {"CommClause.Colon", Field, 0}, - {"CommClause.Comm", Field, 0}, - {"Comment", Type, 0}, - {"Comment.Slash", Field, 0}, - {"Comment.Text", Field, 0}, - {"CommentGroup", Type, 0}, - {"CommentGroup.List", Field, 0}, - {"CommentMap", Type, 1}, - {"CompositeLit", Type, 0}, - {"CompositeLit.Elts", Field, 0}, - {"CompositeLit.Incomplete", Field, 11}, - {"CompositeLit.Lbrace", Field, 0}, - {"CompositeLit.Rbrace", Field, 0}, - {"CompositeLit.Type", Field, 0}, - {"Con", Const, 0}, - {"Decl", Type, 0}, - {"DeclStmt", Type, 0}, - {"DeclStmt.Decl", Field, 0}, - {"DeferStmt", Type, 0}, - {"DeferStmt.Call", Field, 0}, - {"DeferStmt.Defer", Field, 0}, - {"Ellipsis", Type, 0}, - {"Ellipsis.Ellipsis", Field, 0}, - {"Ellipsis.Elt", Field, 0}, - {"EmptyStmt", Type, 0}, - {"EmptyStmt.Implicit", Field, 5}, - {"EmptyStmt.Semicolon", Field, 0}, - {"Expr", Type, 0}, - {"ExprStmt", Type, 0}, - {"ExprStmt.X", Field, 0}, - {"Field", Type, 0}, - {"Field.Comment", Field, 0}, - {"Field.Doc", Field, 0}, - {"Field.Names", Field, 0}, - {"Field.Tag", Field, 0}, - {"Field.Type", Field, 0}, - {"FieldFilter", Type, 0}, - {"FieldList", Type, 0}, - {"FieldList.Closing", Field, 0}, - {"FieldList.List", Field, 0}, - {"FieldList.Opening", Field, 0}, - {"File", Type, 0}, - {"File.Comments", Field, 0}, - {"File.Decls", Field, 0}, - {"File.Doc", Field, 0}, - {"File.FileEnd", Field, 20}, - {"File.FileStart", Field, 20}, - {"File.GoVersion", Field, 21}, - {"File.Imports", Field, 0}, - {"File.Name", Field, 0}, - {"File.Package", Field, 0}, - {"File.Scope", Field, 0}, - {"File.Unresolved", Field, 0}, - {"FileExports", Func, 0}, - {"Filter", Type, 0}, - {"FilterDecl", Func, 0}, - {"FilterFile", Func, 0}, - {"FilterFuncDuplicates", Const, 0}, - {"FilterImportDuplicates", Const, 0}, - {"FilterPackage", Func, 0}, - {"FilterUnassociatedComments", Const, 0}, - {"ForStmt", Type, 0}, - {"ForStmt.Body", Field, 0}, - {"ForStmt.Cond", Field, 0}, - {"ForStmt.For", Field, 0}, - {"ForStmt.Init", Field, 0}, - {"ForStmt.Post", Field, 0}, - {"Fprint", Func, 0}, - {"Fun", Const, 0}, - {"FuncDecl", Type, 0}, - {"FuncDecl.Body", Field, 0}, - {"FuncDecl.Doc", Field, 0}, - {"FuncDecl.Name", Field, 0}, - {"FuncDecl.Recv", Field, 0}, - {"FuncDecl.Type", Field, 0}, - {"FuncLit", Type, 0}, - {"FuncLit.Body", Field, 0}, - {"FuncLit.Type", Field, 0}, - {"FuncType", Type, 0}, - {"FuncType.Func", Field, 0}, - {"FuncType.Params", Field, 0}, - {"FuncType.Results", Field, 0}, - {"FuncType.TypeParams", Field, 18}, - {"GenDecl", Type, 0}, - {"GenDecl.Doc", Field, 0}, - {"GenDecl.Lparen", Field, 0}, - {"GenDecl.Rparen", Field, 0}, - {"GenDecl.Specs", Field, 0}, - {"GenDecl.Tok", Field, 0}, - {"GenDecl.TokPos", Field, 0}, - {"GoStmt", Type, 0}, - {"GoStmt.Call", Field, 0}, - {"GoStmt.Go", Field, 0}, - {"Ident", Type, 0}, - {"Ident.Name", Field, 0}, - {"Ident.NamePos", Field, 0}, - {"Ident.Obj", Field, 0}, - {"IfStmt", Type, 0}, - {"IfStmt.Body", Field, 0}, - {"IfStmt.Cond", Field, 0}, - {"IfStmt.Else", Field, 0}, - {"IfStmt.If", Field, 0}, - {"IfStmt.Init", Field, 0}, - {"ImportSpec", Type, 0}, - {"ImportSpec.Comment", Field, 0}, - {"ImportSpec.Doc", Field, 0}, - {"ImportSpec.EndPos", Field, 0}, - {"ImportSpec.Name", Field, 0}, - {"ImportSpec.Path", Field, 0}, - {"Importer", Type, 0}, - {"IncDecStmt", Type, 0}, - {"IncDecStmt.Tok", Field, 0}, - {"IncDecStmt.TokPos", Field, 0}, - {"IncDecStmt.X", Field, 0}, - {"IndexExpr", Type, 0}, - {"IndexExpr.Index", Field, 0}, - {"IndexExpr.Lbrack", Field, 0}, - {"IndexExpr.Rbrack", Field, 0}, - {"IndexExpr.X", Field, 0}, - {"IndexListExpr", Type, 18}, - {"IndexListExpr.Indices", Field, 18}, - {"IndexListExpr.Lbrack", Field, 18}, - {"IndexListExpr.Rbrack", Field, 18}, - {"IndexListExpr.X", Field, 18}, - {"Inspect", Func, 0}, - {"InterfaceType", Type, 0}, - {"InterfaceType.Incomplete", Field, 0}, - {"InterfaceType.Interface", Field, 0}, - {"InterfaceType.Methods", Field, 0}, - {"IsExported", Func, 0}, - {"IsGenerated", Func, 21}, - {"KeyValueExpr", Type, 0}, - {"KeyValueExpr.Colon", Field, 0}, - {"KeyValueExpr.Key", Field, 0}, - {"KeyValueExpr.Value", Field, 0}, - {"LabeledStmt", Type, 0}, - {"LabeledStmt.Colon", Field, 0}, - {"LabeledStmt.Label", Field, 0}, - {"LabeledStmt.Stmt", Field, 0}, - {"Lbl", Const, 0}, - {"MapType", Type, 0}, - {"MapType.Key", Field, 0}, - {"MapType.Map", Field, 0}, - {"MapType.Value", Field, 0}, - {"MergeMode", Type, 0}, - {"MergePackageFiles", Func, 0}, - {"NewCommentMap", Func, 1}, - {"NewIdent", Func, 0}, - {"NewObj", Func, 0}, - {"NewPackage", Func, 0}, - {"NewScope", Func, 0}, - {"Node", Type, 0}, - {"NotNilFilter", Func, 0}, - {"ObjKind", Type, 0}, - {"Object", Type, 0}, - {"Object.Data", Field, 0}, - {"Object.Decl", Field, 0}, - {"Object.Kind", Field, 0}, - {"Object.Name", Field, 0}, - {"Object.Type", Field, 0}, - {"Package", Type, 0}, - {"Package.Files", Field, 0}, - {"Package.Imports", Field, 0}, - {"Package.Name", Field, 0}, - {"Package.Scope", Field, 0}, - {"PackageExports", Func, 0}, - {"ParenExpr", Type, 0}, - {"ParenExpr.Lparen", Field, 0}, - {"ParenExpr.Rparen", Field, 0}, - {"ParenExpr.X", Field, 0}, - {"Pkg", Const, 0}, - {"Preorder", Func, 23}, - {"Print", Func, 0}, - {"RECV", Const, 0}, - {"RangeStmt", Type, 0}, - {"RangeStmt.Body", Field, 0}, - {"RangeStmt.For", Field, 0}, - {"RangeStmt.Key", Field, 0}, - {"RangeStmt.Range", Field, 20}, - {"RangeStmt.Tok", Field, 0}, - {"RangeStmt.TokPos", Field, 0}, - {"RangeStmt.Value", Field, 0}, - {"RangeStmt.X", Field, 0}, - {"ReturnStmt", Type, 0}, - {"ReturnStmt.Results", Field, 0}, - {"ReturnStmt.Return", Field, 0}, - {"SEND", Const, 0}, - {"Scope", Type, 0}, - {"Scope.Objects", Field, 0}, - {"Scope.Outer", Field, 0}, - {"SelectStmt", Type, 0}, - {"SelectStmt.Body", Field, 0}, - {"SelectStmt.Select", Field, 0}, - {"SelectorExpr", Type, 0}, - {"SelectorExpr.Sel", Field, 0}, - {"SelectorExpr.X", Field, 0}, - {"SendStmt", Type, 0}, - {"SendStmt.Arrow", Field, 0}, - {"SendStmt.Chan", Field, 0}, - {"SendStmt.Value", Field, 0}, - {"SliceExpr", Type, 0}, - {"SliceExpr.High", Field, 0}, - {"SliceExpr.Lbrack", Field, 0}, - {"SliceExpr.Low", Field, 0}, - {"SliceExpr.Max", Field, 2}, - {"SliceExpr.Rbrack", Field, 0}, - {"SliceExpr.Slice3", Field, 2}, - {"SliceExpr.X", Field, 0}, - {"SortImports", Func, 0}, - {"Spec", Type, 0}, - {"StarExpr", Type, 0}, - {"StarExpr.Star", Field, 0}, - {"StarExpr.X", Field, 0}, - {"Stmt", Type, 0}, - {"StructType", Type, 0}, - {"StructType.Fields", Field, 0}, - {"StructType.Incomplete", Field, 0}, - {"StructType.Struct", Field, 0}, - {"SwitchStmt", Type, 0}, - {"SwitchStmt.Body", Field, 0}, - {"SwitchStmt.Init", Field, 0}, - {"SwitchStmt.Switch", Field, 0}, - {"SwitchStmt.Tag", Field, 0}, - {"Typ", Const, 0}, - {"TypeAssertExpr", Type, 0}, - {"TypeAssertExpr.Lparen", Field, 2}, - {"TypeAssertExpr.Rparen", Field, 2}, - {"TypeAssertExpr.Type", Field, 0}, - {"TypeAssertExpr.X", Field, 0}, - {"TypeSpec", Type, 0}, - {"TypeSpec.Assign", Field, 9}, - {"TypeSpec.Comment", Field, 0}, - {"TypeSpec.Doc", Field, 0}, - {"TypeSpec.Name", Field, 0}, - {"TypeSpec.Type", Field, 0}, - {"TypeSpec.TypeParams", Field, 18}, - {"TypeSwitchStmt", Type, 0}, - {"TypeSwitchStmt.Assign", Field, 0}, - {"TypeSwitchStmt.Body", Field, 0}, - {"TypeSwitchStmt.Init", Field, 0}, - {"TypeSwitchStmt.Switch", Field, 0}, - {"UnaryExpr", Type, 0}, - {"UnaryExpr.Op", Field, 0}, - {"UnaryExpr.OpPos", Field, 0}, - {"UnaryExpr.X", Field, 0}, - {"Unparen", Func, 22}, - {"ValueSpec", Type, 0}, - {"ValueSpec.Comment", Field, 0}, - {"ValueSpec.Doc", Field, 0}, - {"ValueSpec.Names", Field, 0}, - {"ValueSpec.Type", Field, 0}, - {"ValueSpec.Values", Field, 0}, - {"Var", Const, 0}, - {"Visitor", Type, 0}, - {"Walk", Func, 0}, + {"(*ArrayType).End", Method, 0, ""}, + {"(*ArrayType).Pos", Method, 0, ""}, + {"(*AssignStmt).End", Method, 0, ""}, + {"(*AssignStmt).Pos", Method, 0, ""}, + {"(*BadDecl).End", Method, 0, ""}, + {"(*BadDecl).Pos", Method, 0, ""}, + {"(*BadExpr).End", Method, 0, ""}, + {"(*BadExpr).Pos", Method, 0, ""}, + {"(*BadStmt).End", Method, 0, ""}, + {"(*BadStmt).Pos", Method, 0, ""}, + {"(*BasicLit).End", Method, 0, ""}, + {"(*BasicLit).Pos", Method, 0, ""}, + {"(*BinaryExpr).End", Method, 0, ""}, + {"(*BinaryExpr).Pos", Method, 0, ""}, + {"(*BlockStmt).End", Method, 0, ""}, + {"(*BlockStmt).Pos", Method, 0, ""}, + {"(*BranchStmt).End", Method, 0, ""}, + {"(*BranchStmt).Pos", Method, 0, ""}, + {"(*CallExpr).End", Method, 0, ""}, + {"(*CallExpr).Pos", Method, 0, ""}, + {"(*CaseClause).End", Method, 0, ""}, + {"(*CaseClause).Pos", Method, 0, ""}, + {"(*ChanType).End", Method, 0, ""}, + {"(*ChanType).Pos", Method, 0, ""}, + {"(*CommClause).End", Method, 0, ""}, + {"(*CommClause).Pos", Method, 0, ""}, + {"(*Comment).End", Method, 0, ""}, + {"(*Comment).Pos", Method, 0, ""}, + {"(*CommentGroup).End", Method, 0, ""}, + {"(*CommentGroup).Pos", Method, 0, ""}, + {"(*CommentGroup).Text", Method, 0, ""}, + {"(*CompositeLit).End", Method, 0, ""}, + {"(*CompositeLit).Pos", Method, 0, ""}, + {"(*DeclStmt).End", Method, 0, ""}, + {"(*DeclStmt).Pos", Method, 0, ""}, + {"(*DeferStmt).End", Method, 0, ""}, + {"(*DeferStmt).Pos", Method, 0, ""}, + {"(*Ellipsis).End", Method, 0, ""}, + {"(*Ellipsis).Pos", Method, 0, ""}, + {"(*EmptyStmt).End", Method, 0, ""}, + {"(*EmptyStmt).Pos", Method, 0, ""}, + {"(*ExprStmt).End", Method, 0, ""}, + {"(*ExprStmt).Pos", Method, 0, ""}, + {"(*Field).End", Method, 0, ""}, + {"(*Field).Pos", Method, 0, ""}, + {"(*FieldList).End", Method, 0, ""}, + {"(*FieldList).NumFields", Method, 0, ""}, + {"(*FieldList).Pos", Method, 0, ""}, + {"(*File).End", Method, 0, ""}, + {"(*File).Pos", Method, 0, ""}, + {"(*ForStmt).End", Method, 0, ""}, + {"(*ForStmt).Pos", Method, 0, ""}, + {"(*FuncDecl).End", Method, 0, ""}, + {"(*FuncDecl).Pos", Method, 0, ""}, + {"(*FuncLit).End", Method, 0, ""}, + {"(*FuncLit).Pos", Method, 0, ""}, + {"(*FuncType).End", Method, 0, ""}, + {"(*FuncType).Pos", Method, 0, ""}, + {"(*GenDecl).End", Method, 0, ""}, + {"(*GenDecl).Pos", Method, 0, ""}, + {"(*GoStmt).End", Method, 0, ""}, + {"(*GoStmt).Pos", Method, 0, ""}, + {"(*Ident).End", Method, 0, ""}, + {"(*Ident).IsExported", Method, 0, ""}, + {"(*Ident).Pos", Method, 0, ""}, + {"(*Ident).String", Method, 0, ""}, + {"(*IfStmt).End", Method, 0, ""}, + {"(*IfStmt).Pos", Method, 0, ""}, + {"(*ImportSpec).End", Method, 0, ""}, + {"(*ImportSpec).Pos", Method, 0, ""}, + {"(*IncDecStmt).End", Method, 0, ""}, + {"(*IncDecStmt).Pos", Method, 0, ""}, + {"(*IndexExpr).End", Method, 0, ""}, + {"(*IndexExpr).Pos", Method, 0, ""}, + {"(*IndexListExpr).End", Method, 18, ""}, + {"(*IndexListExpr).Pos", Method, 18, ""}, + {"(*InterfaceType).End", Method, 0, ""}, + {"(*InterfaceType).Pos", Method, 0, ""}, + {"(*KeyValueExpr).End", Method, 0, ""}, + {"(*KeyValueExpr).Pos", Method, 0, ""}, + {"(*LabeledStmt).End", Method, 0, ""}, + {"(*LabeledStmt).Pos", Method, 0, ""}, + {"(*MapType).End", Method, 0, ""}, + {"(*MapType).Pos", Method, 0, ""}, + {"(*Object).Pos", Method, 0, ""}, + {"(*Package).End", Method, 0, ""}, + {"(*Package).Pos", Method, 0, ""}, + {"(*ParenExpr).End", Method, 0, ""}, + {"(*ParenExpr).Pos", Method, 0, ""}, + {"(*RangeStmt).End", Method, 0, ""}, + {"(*RangeStmt).Pos", Method, 0, ""}, + {"(*ReturnStmt).End", Method, 0, ""}, + {"(*ReturnStmt).Pos", Method, 0, ""}, + {"(*Scope).Insert", Method, 0, ""}, + {"(*Scope).Lookup", Method, 0, ""}, + {"(*Scope).String", Method, 0, ""}, + {"(*SelectStmt).End", Method, 0, ""}, + {"(*SelectStmt).Pos", Method, 0, ""}, + {"(*SelectorExpr).End", Method, 0, ""}, + {"(*SelectorExpr).Pos", Method, 0, ""}, + {"(*SendStmt).End", Method, 0, ""}, + {"(*SendStmt).Pos", Method, 0, ""}, + {"(*SliceExpr).End", Method, 0, ""}, + {"(*SliceExpr).Pos", Method, 0, ""}, + {"(*StarExpr).End", Method, 0, ""}, + {"(*StarExpr).Pos", Method, 0, ""}, + {"(*StructType).End", Method, 0, ""}, + {"(*StructType).Pos", Method, 0, ""}, + {"(*SwitchStmt).End", Method, 0, ""}, + {"(*SwitchStmt).Pos", Method, 0, ""}, + {"(*TypeAssertExpr).End", Method, 0, ""}, + {"(*TypeAssertExpr).Pos", Method, 0, ""}, + {"(*TypeSpec).End", Method, 0, ""}, + {"(*TypeSpec).Pos", Method, 0, ""}, + {"(*TypeSwitchStmt).End", Method, 0, ""}, + {"(*TypeSwitchStmt).Pos", Method, 0, ""}, + {"(*UnaryExpr).End", Method, 0, ""}, + {"(*UnaryExpr).Pos", Method, 0, ""}, + {"(*ValueSpec).End", Method, 0, ""}, + {"(*ValueSpec).Pos", Method, 0, ""}, + {"(CommentMap).Comments", Method, 1, ""}, + {"(CommentMap).Filter", Method, 1, ""}, + {"(CommentMap).String", Method, 1, ""}, + {"(CommentMap).Update", Method, 1, ""}, + {"(ObjKind).String", Method, 0, ""}, + {"ArrayType", Type, 0, ""}, + {"ArrayType.Elt", Field, 0, ""}, + {"ArrayType.Lbrack", Field, 0, ""}, + {"ArrayType.Len", Field, 0, ""}, + {"AssignStmt", Type, 0, ""}, + {"AssignStmt.Lhs", Field, 0, ""}, + {"AssignStmt.Rhs", Field, 0, ""}, + {"AssignStmt.Tok", Field, 0, ""}, + {"AssignStmt.TokPos", Field, 0, ""}, + {"Bad", Const, 0, ""}, + {"BadDecl", Type, 0, ""}, + {"BadDecl.From", Field, 0, ""}, + {"BadDecl.To", Field, 0, ""}, + {"BadExpr", Type, 0, ""}, + {"BadExpr.From", Field, 0, ""}, + {"BadExpr.To", Field, 0, ""}, + {"BadStmt", Type, 0, ""}, + {"BadStmt.From", Field, 0, ""}, + {"BadStmt.To", Field, 0, ""}, + {"BasicLit", Type, 0, ""}, + {"BasicLit.Kind", Field, 0, ""}, + {"BasicLit.Value", Field, 0, ""}, + {"BasicLit.ValuePos", Field, 0, ""}, + {"BinaryExpr", Type, 0, ""}, + {"BinaryExpr.Op", Field, 0, ""}, + {"BinaryExpr.OpPos", Field, 0, ""}, + {"BinaryExpr.X", Field, 0, ""}, + {"BinaryExpr.Y", Field, 0, ""}, + {"BlockStmt", Type, 0, ""}, + {"BlockStmt.Lbrace", Field, 0, ""}, + {"BlockStmt.List", Field, 0, ""}, + {"BlockStmt.Rbrace", Field, 0, ""}, + {"BranchStmt", Type, 0, ""}, + {"BranchStmt.Label", Field, 0, ""}, + {"BranchStmt.Tok", Field, 0, ""}, + {"BranchStmt.TokPos", Field, 0, ""}, + {"CallExpr", Type, 0, ""}, + {"CallExpr.Args", Field, 0, ""}, + {"CallExpr.Ellipsis", Field, 0, ""}, + {"CallExpr.Fun", Field, 0, ""}, + {"CallExpr.Lparen", Field, 0, ""}, + {"CallExpr.Rparen", Field, 0, ""}, + {"CaseClause", Type, 0, ""}, + {"CaseClause.Body", Field, 0, ""}, + {"CaseClause.Case", Field, 0, ""}, + {"CaseClause.Colon", Field, 0, ""}, + {"CaseClause.List", Field, 0, ""}, + {"ChanDir", Type, 0, ""}, + {"ChanType", Type, 0, ""}, + {"ChanType.Arrow", Field, 1, ""}, + {"ChanType.Begin", Field, 0, ""}, + {"ChanType.Dir", Field, 0, ""}, + {"ChanType.Value", Field, 0, ""}, + {"CommClause", Type, 0, ""}, + {"CommClause.Body", Field, 0, ""}, + {"CommClause.Case", Field, 0, ""}, + {"CommClause.Colon", Field, 0, ""}, + {"CommClause.Comm", Field, 0, ""}, + {"Comment", Type, 0, ""}, + {"Comment.Slash", Field, 0, ""}, + {"Comment.Text", Field, 0, ""}, + {"CommentGroup", Type, 0, ""}, + {"CommentGroup.List", Field, 0, ""}, + {"CommentMap", Type, 1, ""}, + {"CompositeLit", Type, 0, ""}, + {"CompositeLit.Elts", Field, 0, ""}, + {"CompositeLit.Incomplete", Field, 11, ""}, + {"CompositeLit.Lbrace", Field, 0, ""}, + {"CompositeLit.Rbrace", Field, 0, ""}, + {"CompositeLit.Type", Field, 0, ""}, + {"Con", Const, 0, ""}, + {"Decl", Type, 0, ""}, + {"DeclStmt", Type, 0, ""}, + {"DeclStmt.Decl", Field, 0, ""}, + {"DeferStmt", Type, 0, ""}, + {"DeferStmt.Call", Field, 0, ""}, + {"DeferStmt.Defer", Field, 0, ""}, + {"Ellipsis", Type, 0, ""}, + {"Ellipsis.Ellipsis", Field, 0, ""}, + {"Ellipsis.Elt", Field, 0, ""}, + {"EmptyStmt", Type, 0, ""}, + {"EmptyStmt.Implicit", Field, 5, ""}, + {"EmptyStmt.Semicolon", Field, 0, ""}, + {"Expr", Type, 0, ""}, + {"ExprStmt", Type, 0, ""}, + {"ExprStmt.X", Field, 0, ""}, + {"Field", Type, 0, ""}, + {"Field.Comment", Field, 0, ""}, + {"Field.Doc", Field, 0, ""}, + {"Field.Names", Field, 0, ""}, + {"Field.Tag", Field, 0, ""}, + {"Field.Type", Field, 0, ""}, + {"FieldFilter", Type, 0, ""}, + {"FieldList", Type, 0, ""}, + {"FieldList.Closing", Field, 0, ""}, + {"FieldList.List", Field, 0, ""}, + {"FieldList.Opening", Field, 0, ""}, + {"File", Type, 0, ""}, + {"File.Comments", Field, 0, ""}, + {"File.Decls", Field, 0, ""}, + {"File.Doc", Field, 0, ""}, + {"File.FileEnd", Field, 20, ""}, + {"File.FileStart", Field, 20, ""}, + {"File.GoVersion", Field, 21, ""}, + {"File.Imports", Field, 0, ""}, + {"File.Name", Field, 0, ""}, + {"File.Package", Field, 0, ""}, + {"File.Scope", Field, 0, ""}, + {"File.Unresolved", Field, 0, ""}, + {"FileExports", Func, 0, "func(src *File) bool"}, + {"Filter", Type, 0, ""}, + {"FilterDecl", Func, 0, "func(decl Decl, f Filter) bool"}, + {"FilterFile", Func, 0, "func(src *File, f Filter) bool"}, + {"FilterFuncDuplicates", Const, 0, ""}, + {"FilterImportDuplicates", Const, 0, ""}, + {"FilterPackage", Func, 0, "func(pkg *Package, f Filter) bool"}, + {"FilterUnassociatedComments", Const, 0, ""}, + {"ForStmt", Type, 0, ""}, + {"ForStmt.Body", Field, 0, ""}, + {"ForStmt.Cond", Field, 0, ""}, + {"ForStmt.For", Field, 0, ""}, + {"ForStmt.Init", Field, 0, ""}, + {"ForStmt.Post", Field, 0, ""}, + {"Fprint", Func, 0, "func(w io.Writer, fset *token.FileSet, x any, f FieldFilter) error"}, + {"Fun", Const, 0, ""}, + {"FuncDecl", Type, 0, ""}, + {"FuncDecl.Body", Field, 0, ""}, + {"FuncDecl.Doc", Field, 0, ""}, + {"FuncDecl.Name", Field, 0, ""}, + {"FuncDecl.Recv", Field, 0, ""}, + {"FuncDecl.Type", Field, 0, ""}, + {"FuncLit", Type, 0, ""}, + {"FuncLit.Body", Field, 0, ""}, + {"FuncLit.Type", Field, 0, ""}, + {"FuncType", Type, 0, ""}, + {"FuncType.Func", Field, 0, ""}, + {"FuncType.Params", Field, 0, ""}, + {"FuncType.Results", Field, 0, ""}, + {"FuncType.TypeParams", Field, 18, ""}, + {"GenDecl", Type, 0, ""}, + {"GenDecl.Doc", Field, 0, ""}, + {"GenDecl.Lparen", Field, 0, ""}, + {"GenDecl.Rparen", Field, 0, ""}, + {"GenDecl.Specs", Field, 0, ""}, + {"GenDecl.Tok", Field, 0, ""}, + {"GenDecl.TokPos", Field, 0, ""}, + {"GoStmt", Type, 0, ""}, + {"GoStmt.Call", Field, 0, ""}, + {"GoStmt.Go", Field, 0, ""}, + {"Ident", Type, 0, ""}, + {"Ident.Name", Field, 0, ""}, + {"Ident.NamePos", Field, 0, ""}, + {"Ident.Obj", Field, 0, ""}, + {"IfStmt", Type, 0, ""}, + {"IfStmt.Body", Field, 0, ""}, + {"IfStmt.Cond", Field, 0, ""}, + {"IfStmt.Else", Field, 0, ""}, + {"IfStmt.If", Field, 0, ""}, + {"IfStmt.Init", Field, 0, ""}, + {"ImportSpec", Type, 0, ""}, + {"ImportSpec.Comment", Field, 0, ""}, + {"ImportSpec.Doc", Field, 0, ""}, + {"ImportSpec.EndPos", Field, 0, ""}, + {"ImportSpec.Name", Field, 0, ""}, + {"ImportSpec.Path", Field, 0, ""}, + {"Importer", Type, 0, ""}, + {"IncDecStmt", Type, 0, ""}, + {"IncDecStmt.Tok", Field, 0, ""}, + {"IncDecStmt.TokPos", Field, 0, ""}, + {"IncDecStmt.X", Field, 0, ""}, + {"IndexExpr", Type, 0, ""}, + {"IndexExpr.Index", Field, 0, ""}, + {"IndexExpr.Lbrack", Field, 0, ""}, + {"IndexExpr.Rbrack", Field, 0, ""}, + {"IndexExpr.X", Field, 0, ""}, + {"IndexListExpr", Type, 18, ""}, + {"IndexListExpr.Indices", Field, 18, ""}, + {"IndexListExpr.Lbrack", Field, 18, ""}, + {"IndexListExpr.Rbrack", Field, 18, ""}, + {"IndexListExpr.X", Field, 18, ""}, + {"Inspect", Func, 0, "func(node Node, f func(Node) bool)"}, + {"InterfaceType", Type, 0, ""}, + {"InterfaceType.Incomplete", Field, 0, ""}, + {"InterfaceType.Interface", Field, 0, ""}, + {"InterfaceType.Methods", Field, 0, ""}, + {"IsExported", Func, 0, "func(name string) bool"}, + {"IsGenerated", Func, 21, "func(file *File) bool"}, + {"KeyValueExpr", Type, 0, ""}, + {"KeyValueExpr.Colon", Field, 0, ""}, + {"KeyValueExpr.Key", Field, 0, ""}, + {"KeyValueExpr.Value", Field, 0, ""}, + {"LabeledStmt", Type, 0, ""}, + {"LabeledStmt.Colon", Field, 0, ""}, + {"LabeledStmt.Label", Field, 0, ""}, + {"LabeledStmt.Stmt", Field, 0, ""}, + {"Lbl", Const, 0, ""}, + {"MapType", Type, 0, ""}, + {"MapType.Key", Field, 0, ""}, + {"MapType.Map", Field, 0, ""}, + {"MapType.Value", Field, 0, ""}, + {"MergeMode", Type, 0, ""}, + {"MergePackageFiles", Func, 0, "func(pkg *Package, mode MergeMode) *File"}, + {"NewCommentMap", Func, 1, "func(fset *token.FileSet, node Node, comments []*CommentGroup) CommentMap"}, + {"NewIdent", Func, 0, "func(name string) *Ident"}, + {"NewObj", Func, 0, "func(kind ObjKind, name string) *Object"}, + {"NewPackage", Func, 0, "func(fset *token.FileSet, files map[string]*File, importer Importer, universe *Scope) (*Package, error)"}, + {"NewScope", Func, 0, "func(outer *Scope) *Scope"}, + {"Node", Type, 0, ""}, + {"NotNilFilter", Func, 0, "func(_ string, v reflect.Value) bool"}, + {"ObjKind", Type, 0, ""}, + {"Object", Type, 0, ""}, + {"Object.Data", Field, 0, ""}, + {"Object.Decl", Field, 0, ""}, + {"Object.Kind", Field, 0, ""}, + {"Object.Name", Field, 0, ""}, + {"Object.Type", Field, 0, ""}, + {"Package", Type, 0, ""}, + {"Package.Files", Field, 0, ""}, + {"Package.Imports", Field, 0, ""}, + {"Package.Name", Field, 0, ""}, + {"Package.Scope", Field, 0, ""}, + {"PackageExports", Func, 0, "func(pkg *Package) bool"}, + {"ParenExpr", Type, 0, ""}, + {"ParenExpr.Lparen", Field, 0, ""}, + {"ParenExpr.Rparen", Field, 0, ""}, + {"ParenExpr.X", Field, 0, ""}, + {"Pkg", Const, 0, ""}, + {"Preorder", Func, 23, "func(root Node) iter.Seq[Node]"}, + {"Print", Func, 0, "func(fset *token.FileSet, x any) error"}, + {"RECV", Const, 0, ""}, + {"RangeStmt", Type, 0, ""}, + {"RangeStmt.Body", Field, 0, ""}, + {"RangeStmt.For", Field, 0, ""}, + {"RangeStmt.Key", Field, 0, ""}, + {"RangeStmt.Range", Field, 20, ""}, + {"RangeStmt.Tok", Field, 0, ""}, + {"RangeStmt.TokPos", Field, 0, ""}, + {"RangeStmt.Value", Field, 0, ""}, + {"RangeStmt.X", Field, 0, ""}, + {"ReturnStmt", Type, 0, ""}, + {"ReturnStmt.Results", Field, 0, ""}, + {"ReturnStmt.Return", Field, 0, ""}, + {"SEND", Const, 0, ""}, + {"Scope", Type, 0, ""}, + {"Scope.Objects", Field, 0, ""}, + {"Scope.Outer", Field, 0, ""}, + {"SelectStmt", Type, 0, ""}, + {"SelectStmt.Body", Field, 0, ""}, + {"SelectStmt.Select", Field, 0, ""}, + {"SelectorExpr", Type, 0, ""}, + {"SelectorExpr.Sel", Field, 0, ""}, + {"SelectorExpr.X", Field, 0, ""}, + {"SendStmt", Type, 0, ""}, + {"SendStmt.Arrow", Field, 0, ""}, + {"SendStmt.Chan", Field, 0, ""}, + {"SendStmt.Value", Field, 0, ""}, + {"SliceExpr", Type, 0, ""}, + {"SliceExpr.High", Field, 0, ""}, + {"SliceExpr.Lbrack", Field, 0, ""}, + {"SliceExpr.Low", Field, 0, ""}, + {"SliceExpr.Max", Field, 2, ""}, + {"SliceExpr.Rbrack", Field, 0, ""}, + {"SliceExpr.Slice3", Field, 2, ""}, + {"SliceExpr.X", Field, 0, ""}, + {"SortImports", Func, 0, "func(fset *token.FileSet, f *File)"}, + {"Spec", Type, 0, ""}, + {"StarExpr", Type, 0, ""}, + {"StarExpr.Star", Field, 0, ""}, + {"StarExpr.X", Field, 0, ""}, + {"Stmt", Type, 0, ""}, + {"StructType", Type, 0, ""}, + {"StructType.Fields", Field, 0, ""}, + {"StructType.Incomplete", Field, 0, ""}, + {"StructType.Struct", Field, 0, ""}, + {"SwitchStmt", Type, 0, ""}, + {"SwitchStmt.Body", Field, 0, ""}, + {"SwitchStmt.Init", Field, 0, ""}, + {"SwitchStmt.Switch", Field, 0, ""}, + {"SwitchStmt.Tag", Field, 0, ""}, + {"Typ", Const, 0, ""}, + {"TypeAssertExpr", Type, 0, ""}, + {"TypeAssertExpr.Lparen", Field, 2, ""}, + {"TypeAssertExpr.Rparen", Field, 2, ""}, + {"TypeAssertExpr.Type", Field, 0, ""}, + {"TypeAssertExpr.X", Field, 0, ""}, + {"TypeSpec", Type, 0, ""}, + {"TypeSpec.Assign", Field, 9, ""}, + {"TypeSpec.Comment", Field, 0, ""}, + {"TypeSpec.Doc", Field, 0, ""}, + {"TypeSpec.Name", Field, 0, ""}, + {"TypeSpec.Type", Field, 0, ""}, + {"TypeSpec.TypeParams", Field, 18, ""}, + {"TypeSwitchStmt", Type, 0, ""}, + {"TypeSwitchStmt.Assign", Field, 0, ""}, + {"TypeSwitchStmt.Body", Field, 0, ""}, + {"TypeSwitchStmt.Init", Field, 0, ""}, + {"TypeSwitchStmt.Switch", Field, 0, ""}, + {"UnaryExpr", Type, 0, ""}, + {"UnaryExpr.Op", Field, 0, ""}, + {"UnaryExpr.OpPos", Field, 0, ""}, + {"UnaryExpr.X", Field, 0, ""}, + {"Unparen", Func, 22, "func(e Expr) Expr"}, + {"ValueSpec", Type, 0, ""}, + {"ValueSpec.Comment", Field, 0, ""}, + {"ValueSpec.Doc", Field, 0, ""}, + {"ValueSpec.Names", Field, 0, ""}, + {"ValueSpec.Type", Field, 0, ""}, + {"ValueSpec.Values", Field, 0, ""}, + {"Var", Const, 0, ""}, + {"Visitor", Type, 0, ""}, + {"Walk", Func, 0, "func(v Visitor, node Node)"}, }, "go/build": { - {"(*Context).Import", Method, 0}, - {"(*Context).ImportDir", Method, 0}, - {"(*Context).MatchFile", Method, 2}, - {"(*Context).SrcDirs", Method, 0}, - {"(*MultiplePackageError).Error", Method, 4}, - {"(*NoGoError).Error", Method, 0}, - {"(*Package).IsCommand", Method, 0}, - {"AllowBinary", Const, 0}, - {"ArchChar", Func, 0}, - {"Context", Type, 0}, - {"Context.BuildTags", Field, 0}, - {"Context.CgoEnabled", Field, 0}, - {"Context.Compiler", Field, 0}, - {"Context.Dir", Field, 14}, - {"Context.GOARCH", Field, 0}, - {"Context.GOOS", Field, 0}, - {"Context.GOPATH", Field, 0}, - {"Context.GOROOT", Field, 0}, - {"Context.HasSubdir", Field, 0}, - {"Context.InstallSuffix", Field, 1}, - {"Context.IsAbsPath", Field, 0}, - {"Context.IsDir", Field, 0}, - {"Context.JoinPath", Field, 0}, - {"Context.OpenFile", Field, 0}, - {"Context.ReadDir", Field, 0}, - {"Context.ReleaseTags", Field, 1}, - {"Context.SplitPathList", Field, 0}, - {"Context.ToolTags", Field, 17}, - {"Context.UseAllFiles", Field, 0}, - {"Default", Var, 0}, - {"Directive", Type, 21}, - {"Directive.Pos", Field, 21}, - {"Directive.Text", Field, 21}, - {"FindOnly", Const, 0}, - {"IgnoreVendor", Const, 6}, - {"Import", Func, 0}, - {"ImportComment", Const, 4}, - {"ImportDir", Func, 0}, - {"ImportMode", Type, 0}, - {"IsLocalImport", Func, 0}, - {"MultiplePackageError", Type, 4}, - {"MultiplePackageError.Dir", Field, 4}, - {"MultiplePackageError.Files", Field, 4}, - {"MultiplePackageError.Packages", Field, 4}, - {"NoGoError", Type, 0}, - {"NoGoError.Dir", Field, 0}, - {"Package", Type, 0}, - {"Package.AllTags", Field, 2}, - {"Package.BinDir", Field, 0}, - {"Package.BinaryOnly", Field, 7}, - {"Package.CFiles", Field, 0}, - {"Package.CXXFiles", Field, 2}, - {"Package.CgoCFLAGS", Field, 0}, - {"Package.CgoCPPFLAGS", Field, 2}, - {"Package.CgoCXXFLAGS", Field, 2}, - {"Package.CgoFFLAGS", Field, 7}, - {"Package.CgoFiles", Field, 0}, - {"Package.CgoLDFLAGS", Field, 0}, - {"Package.CgoPkgConfig", Field, 0}, - {"Package.ConflictDir", Field, 2}, - {"Package.Dir", Field, 0}, - {"Package.Directives", Field, 21}, - {"Package.Doc", Field, 0}, - {"Package.EmbedPatternPos", Field, 16}, - {"Package.EmbedPatterns", Field, 16}, - {"Package.FFiles", Field, 7}, - {"Package.GoFiles", Field, 0}, - {"Package.Goroot", Field, 0}, - {"Package.HFiles", Field, 0}, - {"Package.IgnoredGoFiles", Field, 1}, - {"Package.IgnoredOtherFiles", Field, 16}, - {"Package.ImportComment", Field, 4}, - {"Package.ImportPath", Field, 0}, - {"Package.ImportPos", Field, 0}, - {"Package.Imports", Field, 0}, - {"Package.InvalidGoFiles", Field, 6}, - {"Package.MFiles", Field, 3}, - {"Package.Name", Field, 0}, - {"Package.PkgObj", Field, 0}, - {"Package.PkgRoot", Field, 0}, - {"Package.PkgTargetRoot", Field, 5}, - {"Package.Root", Field, 0}, - {"Package.SFiles", Field, 0}, - {"Package.SrcRoot", Field, 0}, - {"Package.SwigCXXFiles", Field, 1}, - {"Package.SwigFiles", Field, 1}, - {"Package.SysoFiles", Field, 0}, - {"Package.TestDirectives", Field, 21}, - {"Package.TestEmbedPatternPos", Field, 16}, - {"Package.TestEmbedPatterns", Field, 16}, - {"Package.TestGoFiles", Field, 0}, - {"Package.TestImportPos", Field, 0}, - {"Package.TestImports", Field, 0}, - {"Package.XTestDirectives", Field, 21}, - {"Package.XTestEmbedPatternPos", Field, 16}, - {"Package.XTestEmbedPatterns", Field, 16}, - {"Package.XTestGoFiles", Field, 0}, - {"Package.XTestImportPos", Field, 0}, - {"Package.XTestImports", Field, 0}, - {"ToolDir", Var, 0}, + {"(*Context).Import", Method, 0, ""}, + {"(*Context).ImportDir", Method, 0, ""}, + {"(*Context).MatchFile", Method, 2, ""}, + {"(*Context).SrcDirs", Method, 0, ""}, + {"(*MultiplePackageError).Error", Method, 4, ""}, + {"(*NoGoError).Error", Method, 0, ""}, + {"(*Package).IsCommand", Method, 0, ""}, + {"AllowBinary", Const, 0, ""}, + {"ArchChar", Func, 0, "func(goarch string) (string, error)"}, + {"Context", Type, 0, ""}, + {"Context.BuildTags", Field, 0, ""}, + {"Context.CgoEnabled", Field, 0, ""}, + {"Context.Compiler", Field, 0, ""}, + {"Context.Dir", Field, 14, ""}, + {"Context.GOARCH", Field, 0, ""}, + {"Context.GOOS", Field, 0, ""}, + {"Context.GOPATH", Field, 0, ""}, + {"Context.GOROOT", Field, 0, ""}, + {"Context.HasSubdir", Field, 0, ""}, + {"Context.InstallSuffix", Field, 1, ""}, + {"Context.IsAbsPath", Field, 0, ""}, + {"Context.IsDir", Field, 0, ""}, + {"Context.JoinPath", Field, 0, ""}, + {"Context.OpenFile", Field, 0, ""}, + {"Context.ReadDir", Field, 0, ""}, + {"Context.ReleaseTags", Field, 1, ""}, + {"Context.SplitPathList", Field, 0, ""}, + {"Context.ToolTags", Field, 17, ""}, + {"Context.UseAllFiles", Field, 0, ""}, + {"Default", Var, 0, ""}, + {"Directive", Type, 21, ""}, + {"Directive.Pos", Field, 21, ""}, + {"Directive.Text", Field, 21, ""}, + {"FindOnly", Const, 0, ""}, + {"IgnoreVendor", Const, 6, ""}, + {"Import", Func, 0, "func(path string, srcDir string, mode ImportMode) (*Package, error)"}, + {"ImportComment", Const, 4, ""}, + {"ImportDir", Func, 0, "func(dir string, mode ImportMode) (*Package, error)"}, + {"ImportMode", Type, 0, ""}, + {"IsLocalImport", Func, 0, "func(path string) bool"}, + {"MultiplePackageError", Type, 4, ""}, + {"MultiplePackageError.Dir", Field, 4, ""}, + {"MultiplePackageError.Files", Field, 4, ""}, + {"MultiplePackageError.Packages", Field, 4, ""}, + {"NoGoError", Type, 0, ""}, + {"NoGoError.Dir", Field, 0, ""}, + {"Package", Type, 0, ""}, + {"Package.AllTags", Field, 2, ""}, + {"Package.BinDir", Field, 0, ""}, + {"Package.BinaryOnly", Field, 7, ""}, + {"Package.CFiles", Field, 0, ""}, + {"Package.CXXFiles", Field, 2, ""}, + {"Package.CgoCFLAGS", Field, 0, ""}, + {"Package.CgoCPPFLAGS", Field, 2, ""}, + {"Package.CgoCXXFLAGS", Field, 2, ""}, + {"Package.CgoFFLAGS", Field, 7, ""}, + {"Package.CgoFiles", Field, 0, ""}, + {"Package.CgoLDFLAGS", Field, 0, ""}, + {"Package.CgoPkgConfig", Field, 0, ""}, + {"Package.ConflictDir", Field, 2, ""}, + {"Package.Dir", Field, 0, ""}, + {"Package.Directives", Field, 21, ""}, + {"Package.Doc", Field, 0, ""}, + {"Package.EmbedPatternPos", Field, 16, ""}, + {"Package.EmbedPatterns", Field, 16, ""}, + {"Package.FFiles", Field, 7, ""}, + {"Package.GoFiles", Field, 0, ""}, + {"Package.Goroot", Field, 0, ""}, + {"Package.HFiles", Field, 0, ""}, + {"Package.IgnoredGoFiles", Field, 1, ""}, + {"Package.IgnoredOtherFiles", Field, 16, ""}, + {"Package.ImportComment", Field, 4, ""}, + {"Package.ImportPath", Field, 0, ""}, + {"Package.ImportPos", Field, 0, ""}, + {"Package.Imports", Field, 0, ""}, + {"Package.InvalidGoFiles", Field, 6, ""}, + {"Package.MFiles", Field, 3, ""}, + {"Package.Name", Field, 0, ""}, + {"Package.PkgObj", Field, 0, ""}, + {"Package.PkgRoot", Field, 0, ""}, + {"Package.PkgTargetRoot", Field, 5, ""}, + {"Package.Root", Field, 0, ""}, + {"Package.SFiles", Field, 0, ""}, + {"Package.SrcRoot", Field, 0, ""}, + {"Package.SwigCXXFiles", Field, 1, ""}, + {"Package.SwigFiles", Field, 1, ""}, + {"Package.SysoFiles", Field, 0, ""}, + {"Package.TestDirectives", Field, 21, ""}, + {"Package.TestEmbedPatternPos", Field, 16, ""}, + {"Package.TestEmbedPatterns", Field, 16, ""}, + {"Package.TestGoFiles", Field, 0, ""}, + {"Package.TestImportPos", Field, 0, ""}, + {"Package.TestImports", Field, 0, ""}, + {"Package.XTestDirectives", Field, 21, ""}, + {"Package.XTestEmbedPatternPos", Field, 16, ""}, + {"Package.XTestEmbedPatterns", Field, 16, ""}, + {"Package.XTestGoFiles", Field, 0, ""}, + {"Package.XTestImportPos", Field, 0, ""}, + {"Package.XTestImports", Field, 0, ""}, + {"ToolDir", Var, 0, ""}, }, "go/build/constraint": { - {"(*AndExpr).Eval", Method, 16}, - {"(*AndExpr).String", Method, 16}, - {"(*NotExpr).Eval", Method, 16}, - {"(*NotExpr).String", Method, 16}, - {"(*OrExpr).Eval", Method, 16}, - {"(*OrExpr).String", Method, 16}, - {"(*SyntaxError).Error", Method, 16}, - {"(*TagExpr).Eval", Method, 16}, - {"(*TagExpr).String", Method, 16}, - {"AndExpr", Type, 16}, - {"AndExpr.X", Field, 16}, - {"AndExpr.Y", Field, 16}, - {"Expr", Type, 16}, - {"GoVersion", Func, 21}, - {"IsGoBuild", Func, 16}, - {"IsPlusBuild", Func, 16}, - {"NotExpr", Type, 16}, - {"NotExpr.X", Field, 16}, - {"OrExpr", Type, 16}, - {"OrExpr.X", Field, 16}, - {"OrExpr.Y", Field, 16}, - {"Parse", Func, 16}, - {"PlusBuildLines", Func, 16}, - {"SyntaxError", Type, 16}, - {"SyntaxError.Err", Field, 16}, - {"SyntaxError.Offset", Field, 16}, - {"TagExpr", Type, 16}, - {"TagExpr.Tag", Field, 16}, + {"(*AndExpr).Eval", Method, 16, ""}, + {"(*AndExpr).String", Method, 16, ""}, + {"(*NotExpr).Eval", Method, 16, ""}, + {"(*NotExpr).String", Method, 16, ""}, + {"(*OrExpr).Eval", Method, 16, ""}, + {"(*OrExpr).String", Method, 16, ""}, + {"(*SyntaxError).Error", Method, 16, ""}, + {"(*TagExpr).Eval", Method, 16, ""}, + {"(*TagExpr).String", Method, 16, ""}, + {"AndExpr", Type, 16, ""}, + {"AndExpr.X", Field, 16, ""}, + {"AndExpr.Y", Field, 16, ""}, + {"Expr", Type, 16, ""}, + {"GoVersion", Func, 21, "func(x Expr) string"}, + {"IsGoBuild", Func, 16, "func(line string) bool"}, + {"IsPlusBuild", Func, 16, "func(line string) bool"}, + {"NotExpr", Type, 16, ""}, + {"NotExpr.X", Field, 16, ""}, + {"OrExpr", Type, 16, ""}, + {"OrExpr.X", Field, 16, ""}, + {"OrExpr.Y", Field, 16, ""}, + {"Parse", Func, 16, "func(line string) (Expr, error)"}, + {"PlusBuildLines", Func, 16, "func(x Expr) ([]string, error)"}, + {"SyntaxError", Type, 16, ""}, + {"SyntaxError.Err", Field, 16, ""}, + {"SyntaxError.Offset", Field, 16, ""}, + {"TagExpr", Type, 16, ""}, + {"TagExpr.Tag", Field, 16, ""}, }, "go/constant": { - {"(Kind).String", Method, 18}, - {"BinaryOp", Func, 5}, - {"BitLen", Func, 5}, - {"Bool", Const, 5}, - {"BoolVal", Func, 5}, - {"Bytes", Func, 5}, - {"Compare", Func, 5}, - {"Complex", Const, 5}, - {"Denom", Func, 5}, - {"Float", Const, 5}, - {"Float32Val", Func, 5}, - {"Float64Val", Func, 5}, - {"Imag", Func, 5}, - {"Int", Const, 5}, - {"Int64Val", Func, 5}, - {"Kind", Type, 5}, - {"Make", Func, 13}, - {"MakeBool", Func, 5}, - {"MakeFloat64", Func, 5}, - {"MakeFromBytes", Func, 5}, - {"MakeFromLiteral", Func, 5}, - {"MakeImag", Func, 5}, - {"MakeInt64", Func, 5}, - {"MakeString", Func, 5}, - {"MakeUint64", Func, 5}, - {"MakeUnknown", Func, 5}, - {"Num", Func, 5}, - {"Real", Func, 5}, - {"Shift", Func, 5}, - {"Sign", Func, 5}, - {"String", Const, 5}, - {"StringVal", Func, 5}, - {"ToComplex", Func, 6}, - {"ToFloat", Func, 6}, - {"ToInt", Func, 6}, - {"Uint64Val", Func, 5}, - {"UnaryOp", Func, 5}, - {"Unknown", Const, 5}, - {"Val", Func, 13}, - {"Value", Type, 5}, + {"(Kind).String", Method, 18, ""}, + {"BinaryOp", Func, 5, "func(x_ Value, op token.Token, y_ Value) Value"}, + {"BitLen", Func, 5, "func(x Value) int"}, + {"Bool", Const, 5, ""}, + {"BoolVal", Func, 5, "func(x Value) bool"}, + {"Bytes", Func, 5, "func(x Value) []byte"}, + {"Compare", Func, 5, "func(x_ Value, op token.Token, y_ Value) bool"}, + {"Complex", Const, 5, ""}, + {"Denom", Func, 5, "func(x Value) Value"}, + {"Float", Const, 5, ""}, + {"Float32Val", Func, 5, "func(x Value) (float32, bool)"}, + {"Float64Val", Func, 5, "func(x Value) (float64, bool)"}, + {"Imag", Func, 5, "func(x Value) Value"}, + {"Int", Const, 5, ""}, + {"Int64Val", Func, 5, "func(x Value) (int64, bool)"}, + {"Kind", Type, 5, ""}, + {"Make", Func, 13, "func(x any) Value"}, + {"MakeBool", Func, 5, "func(b bool) Value"}, + {"MakeFloat64", Func, 5, "func(x float64) Value"}, + {"MakeFromBytes", Func, 5, "func(bytes []byte) Value"}, + {"MakeFromLiteral", Func, 5, "func(lit string, tok token.Token, zero uint) Value"}, + {"MakeImag", Func, 5, "func(x Value) Value"}, + {"MakeInt64", Func, 5, "func(x int64) Value"}, + {"MakeString", Func, 5, "func(s string) Value"}, + {"MakeUint64", Func, 5, "func(x uint64) Value"}, + {"MakeUnknown", Func, 5, "func() Value"}, + {"Num", Func, 5, "func(x Value) Value"}, + {"Real", Func, 5, "func(x Value) Value"}, + {"Shift", Func, 5, "func(x Value, op token.Token, s uint) Value"}, + {"Sign", Func, 5, "func(x Value) int"}, + {"String", Const, 5, ""}, + {"StringVal", Func, 5, "func(x Value) string"}, + {"ToComplex", Func, 6, "func(x Value) Value"}, + {"ToFloat", Func, 6, "func(x Value) Value"}, + {"ToInt", Func, 6, "func(x Value) Value"}, + {"Uint64Val", Func, 5, "func(x Value) (uint64, bool)"}, + {"UnaryOp", Func, 5, "func(op token.Token, y Value, prec uint) Value"}, + {"Unknown", Const, 5, ""}, + {"Val", Func, 13, "func(x Value) any"}, + {"Value", Type, 5, ""}, }, "go/doc": { - {"(*Package).Filter", Method, 0}, - {"(*Package).HTML", Method, 19}, - {"(*Package).Markdown", Method, 19}, - {"(*Package).Parser", Method, 19}, - {"(*Package).Printer", Method, 19}, - {"(*Package).Synopsis", Method, 19}, - {"(*Package).Text", Method, 19}, - {"AllDecls", Const, 0}, - {"AllMethods", Const, 0}, - {"Example", Type, 0}, - {"Example.Code", Field, 0}, - {"Example.Comments", Field, 0}, - {"Example.Doc", Field, 0}, - {"Example.EmptyOutput", Field, 1}, - {"Example.Name", Field, 0}, - {"Example.Order", Field, 1}, - {"Example.Output", Field, 0}, - {"Example.Play", Field, 1}, - {"Example.Suffix", Field, 14}, - {"Example.Unordered", Field, 7}, - {"Examples", Func, 0}, - {"Filter", Type, 0}, - {"Func", Type, 0}, - {"Func.Decl", Field, 0}, - {"Func.Doc", Field, 0}, - {"Func.Examples", Field, 14}, - {"Func.Level", Field, 0}, - {"Func.Name", Field, 0}, - {"Func.Orig", Field, 0}, - {"Func.Recv", Field, 0}, - {"IllegalPrefixes", Var, 1}, - {"IsPredeclared", Func, 8}, - {"Mode", Type, 0}, - {"New", Func, 0}, - {"NewFromFiles", Func, 14}, - {"Note", Type, 1}, - {"Note.Body", Field, 1}, - {"Note.End", Field, 1}, - {"Note.Pos", Field, 1}, - {"Note.UID", Field, 1}, - {"Package", Type, 0}, - {"Package.Bugs", Field, 0}, - {"Package.Consts", Field, 0}, - {"Package.Doc", Field, 0}, - {"Package.Examples", Field, 14}, - {"Package.Filenames", Field, 0}, - {"Package.Funcs", Field, 0}, - {"Package.ImportPath", Field, 0}, - {"Package.Imports", Field, 0}, - {"Package.Name", Field, 0}, - {"Package.Notes", Field, 1}, - {"Package.Types", Field, 0}, - {"Package.Vars", Field, 0}, - {"PreserveAST", Const, 12}, - {"Synopsis", Func, 0}, - {"ToHTML", Func, 0}, - {"ToText", Func, 0}, - {"Type", Type, 0}, - {"Type.Consts", Field, 0}, - {"Type.Decl", Field, 0}, - {"Type.Doc", Field, 0}, - {"Type.Examples", Field, 14}, - {"Type.Funcs", Field, 0}, - {"Type.Methods", Field, 0}, - {"Type.Name", Field, 0}, - {"Type.Vars", Field, 0}, - {"Value", Type, 0}, - {"Value.Decl", Field, 0}, - {"Value.Doc", Field, 0}, - {"Value.Names", Field, 0}, + {"(*Package).Filter", Method, 0, ""}, + {"(*Package).HTML", Method, 19, ""}, + {"(*Package).Markdown", Method, 19, ""}, + {"(*Package).Parser", Method, 19, ""}, + {"(*Package).Printer", Method, 19, ""}, + {"(*Package).Synopsis", Method, 19, ""}, + {"(*Package).Text", Method, 19, ""}, + {"AllDecls", Const, 0, ""}, + {"AllMethods", Const, 0, ""}, + {"Example", Type, 0, ""}, + {"Example.Code", Field, 0, ""}, + {"Example.Comments", Field, 0, ""}, + {"Example.Doc", Field, 0, ""}, + {"Example.EmptyOutput", Field, 1, ""}, + {"Example.Name", Field, 0, ""}, + {"Example.Order", Field, 1, ""}, + {"Example.Output", Field, 0, ""}, + {"Example.Play", Field, 1, ""}, + {"Example.Suffix", Field, 14, ""}, + {"Example.Unordered", Field, 7, ""}, + {"Examples", Func, 0, "func(testFiles ...*ast.File) []*Example"}, + {"Filter", Type, 0, ""}, + {"Func", Type, 0, ""}, + {"Func.Decl", Field, 0, ""}, + {"Func.Doc", Field, 0, ""}, + {"Func.Examples", Field, 14, ""}, + {"Func.Level", Field, 0, ""}, + {"Func.Name", Field, 0, ""}, + {"Func.Orig", Field, 0, ""}, + {"Func.Recv", Field, 0, ""}, + {"IllegalPrefixes", Var, 1, ""}, + {"IsPredeclared", Func, 8, "func(s string) bool"}, + {"Mode", Type, 0, ""}, + {"New", Func, 0, "func(pkg *ast.Package, importPath string, mode Mode) *Package"}, + {"NewFromFiles", Func, 14, "func(fset *token.FileSet, files []*ast.File, importPath string, opts ...any) (*Package, error)"}, + {"Note", Type, 1, ""}, + {"Note.Body", Field, 1, ""}, + {"Note.End", Field, 1, ""}, + {"Note.Pos", Field, 1, ""}, + {"Note.UID", Field, 1, ""}, + {"Package", Type, 0, ""}, + {"Package.Bugs", Field, 0, ""}, + {"Package.Consts", Field, 0, ""}, + {"Package.Doc", Field, 0, ""}, + {"Package.Examples", Field, 14, ""}, + {"Package.Filenames", Field, 0, ""}, + {"Package.Funcs", Field, 0, ""}, + {"Package.ImportPath", Field, 0, ""}, + {"Package.Imports", Field, 0, ""}, + {"Package.Name", Field, 0, ""}, + {"Package.Notes", Field, 1, ""}, + {"Package.Types", Field, 0, ""}, + {"Package.Vars", Field, 0, ""}, + {"PreserveAST", Const, 12, ""}, + {"Synopsis", Func, 0, "func(text string) string"}, + {"ToHTML", Func, 0, "func(w io.Writer, text string, words map[string]string)"}, + {"ToText", Func, 0, "func(w io.Writer, text string, prefix string, codePrefix string, width int)"}, + {"Type", Type, 0, ""}, + {"Type.Consts", Field, 0, ""}, + {"Type.Decl", Field, 0, ""}, + {"Type.Doc", Field, 0, ""}, + {"Type.Examples", Field, 14, ""}, + {"Type.Funcs", Field, 0, ""}, + {"Type.Methods", Field, 0, ""}, + {"Type.Name", Field, 0, ""}, + {"Type.Vars", Field, 0, ""}, + {"Value", Type, 0, ""}, + {"Value.Decl", Field, 0, ""}, + {"Value.Doc", Field, 0, ""}, + {"Value.Names", Field, 0, ""}, }, "go/doc/comment": { - {"(*DocLink).DefaultURL", Method, 19}, - {"(*Heading).DefaultID", Method, 19}, - {"(*List).BlankBefore", Method, 19}, - {"(*List).BlankBetween", Method, 19}, - {"(*Parser).Parse", Method, 19}, - {"(*Printer).Comment", Method, 19}, - {"(*Printer).HTML", Method, 19}, - {"(*Printer).Markdown", Method, 19}, - {"(*Printer).Text", Method, 19}, - {"Block", Type, 19}, - {"Code", Type, 19}, - {"Code.Text", Field, 19}, - {"DefaultLookupPackage", Func, 19}, - {"Doc", Type, 19}, - {"Doc.Content", Field, 19}, - {"Doc.Links", Field, 19}, - {"DocLink", Type, 19}, - {"DocLink.ImportPath", Field, 19}, - {"DocLink.Name", Field, 19}, - {"DocLink.Recv", Field, 19}, - {"DocLink.Text", Field, 19}, - {"Heading", Type, 19}, - {"Heading.Text", Field, 19}, - {"Italic", Type, 19}, - {"Link", Type, 19}, - {"Link.Auto", Field, 19}, - {"Link.Text", Field, 19}, - {"Link.URL", Field, 19}, - {"LinkDef", Type, 19}, - {"LinkDef.Text", Field, 19}, - {"LinkDef.URL", Field, 19}, - {"LinkDef.Used", Field, 19}, - {"List", Type, 19}, - {"List.ForceBlankBefore", Field, 19}, - {"List.ForceBlankBetween", Field, 19}, - {"List.Items", Field, 19}, - {"ListItem", Type, 19}, - {"ListItem.Content", Field, 19}, - {"ListItem.Number", Field, 19}, - {"Paragraph", Type, 19}, - {"Paragraph.Text", Field, 19}, - {"Parser", Type, 19}, - {"Parser.LookupPackage", Field, 19}, - {"Parser.LookupSym", Field, 19}, - {"Parser.Words", Field, 19}, - {"Plain", Type, 19}, - {"Printer", Type, 19}, - {"Printer.DocLinkBaseURL", Field, 19}, - {"Printer.DocLinkURL", Field, 19}, - {"Printer.HeadingID", Field, 19}, - {"Printer.HeadingLevel", Field, 19}, - {"Printer.TextCodePrefix", Field, 19}, - {"Printer.TextPrefix", Field, 19}, - {"Printer.TextWidth", Field, 19}, - {"Text", Type, 19}, + {"(*DocLink).DefaultURL", Method, 19, ""}, + {"(*Heading).DefaultID", Method, 19, ""}, + {"(*List).BlankBefore", Method, 19, ""}, + {"(*List).BlankBetween", Method, 19, ""}, + {"(*Parser).Parse", Method, 19, ""}, + {"(*Printer).Comment", Method, 19, ""}, + {"(*Printer).HTML", Method, 19, ""}, + {"(*Printer).Markdown", Method, 19, ""}, + {"(*Printer).Text", Method, 19, ""}, + {"Block", Type, 19, ""}, + {"Code", Type, 19, ""}, + {"Code.Text", Field, 19, ""}, + {"DefaultLookupPackage", Func, 19, "func(name string) (importPath string, ok bool)"}, + {"Doc", Type, 19, ""}, + {"Doc.Content", Field, 19, ""}, + {"Doc.Links", Field, 19, ""}, + {"DocLink", Type, 19, ""}, + {"DocLink.ImportPath", Field, 19, ""}, + {"DocLink.Name", Field, 19, ""}, + {"DocLink.Recv", Field, 19, ""}, + {"DocLink.Text", Field, 19, ""}, + {"Heading", Type, 19, ""}, + {"Heading.Text", Field, 19, ""}, + {"Italic", Type, 19, ""}, + {"Link", Type, 19, ""}, + {"Link.Auto", Field, 19, ""}, + {"Link.Text", Field, 19, ""}, + {"Link.URL", Field, 19, ""}, + {"LinkDef", Type, 19, ""}, + {"LinkDef.Text", Field, 19, ""}, + {"LinkDef.URL", Field, 19, ""}, + {"LinkDef.Used", Field, 19, ""}, + {"List", Type, 19, ""}, + {"List.ForceBlankBefore", Field, 19, ""}, + {"List.ForceBlankBetween", Field, 19, ""}, + {"List.Items", Field, 19, ""}, + {"ListItem", Type, 19, ""}, + {"ListItem.Content", Field, 19, ""}, + {"ListItem.Number", Field, 19, ""}, + {"Paragraph", Type, 19, ""}, + {"Paragraph.Text", Field, 19, ""}, + {"Parser", Type, 19, ""}, + {"Parser.LookupPackage", Field, 19, ""}, + {"Parser.LookupSym", Field, 19, ""}, + {"Parser.Words", Field, 19, ""}, + {"Plain", Type, 19, ""}, + {"Printer", Type, 19, ""}, + {"Printer.DocLinkBaseURL", Field, 19, ""}, + {"Printer.DocLinkURL", Field, 19, ""}, + {"Printer.HeadingID", Field, 19, ""}, + {"Printer.HeadingLevel", Field, 19, ""}, + {"Printer.TextCodePrefix", Field, 19, ""}, + {"Printer.TextPrefix", Field, 19, ""}, + {"Printer.TextWidth", Field, 19, ""}, + {"Text", Type, 19, ""}, }, "go/format": { - {"Node", Func, 1}, - {"Source", Func, 1}, + {"Node", Func, 1, "func(dst io.Writer, fset *token.FileSet, node any) error"}, + {"Source", Func, 1, "func(src []byte) ([]byte, error)"}, }, "go/importer": { - {"Default", Func, 5}, - {"For", Func, 5}, - {"ForCompiler", Func, 12}, - {"Lookup", Type, 5}, + {"Default", Func, 5, "func() types.Importer"}, + {"For", Func, 5, "func(compiler string, lookup Lookup) types.Importer"}, + {"ForCompiler", Func, 12, "func(fset *token.FileSet, compiler string, lookup Lookup) types.Importer"}, + {"Lookup", Type, 5, ""}, }, "go/parser": { - {"AllErrors", Const, 1}, - {"DeclarationErrors", Const, 0}, - {"ImportsOnly", Const, 0}, - {"Mode", Type, 0}, - {"PackageClauseOnly", Const, 0}, - {"ParseComments", Const, 0}, - {"ParseDir", Func, 0}, - {"ParseExpr", Func, 0}, - {"ParseExprFrom", Func, 5}, - {"ParseFile", Func, 0}, - {"SkipObjectResolution", Const, 17}, - {"SpuriousErrors", Const, 0}, - {"Trace", Const, 0}, + {"AllErrors", Const, 1, ""}, + {"DeclarationErrors", Const, 0, ""}, + {"ImportsOnly", Const, 0, ""}, + {"Mode", Type, 0, ""}, + {"PackageClauseOnly", Const, 0, ""}, + {"ParseComments", Const, 0, ""}, + {"ParseDir", Func, 0, "func(fset *token.FileSet, path string, filter func(fs.FileInfo) bool, mode Mode) (pkgs map[string]*ast.Package, first error)"}, + {"ParseExpr", Func, 0, "func(x string) (ast.Expr, error)"}, + {"ParseExprFrom", Func, 5, "func(fset *token.FileSet, filename string, src any, mode Mode) (expr ast.Expr, err error)"}, + {"ParseFile", Func, 0, "func(fset *token.FileSet, filename string, src any, mode Mode) (f *ast.File, err error)"}, + {"SkipObjectResolution", Const, 17, ""}, + {"SpuriousErrors", Const, 0, ""}, + {"Trace", Const, 0, ""}, }, "go/printer": { - {"(*Config).Fprint", Method, 0}, - {"CommentedNode", Type, 0}, - {"CommentedNode.Comments", Field, 0}, - {"CommentedNode.Node", Field, 0}, - {"Config", Type, 0}, - {"Config.Indent", Field, 1}, - {"Config.Mode", Field, 0}, - {"Config.Tabwidth", Field, 0}, - {"Fprint", Func, 0}, - {"Mode", Type, 0}, - {"RawFormat", Const, 0}, - {"SourcePos", Const, 0}, - {"TabIndent", Const, 0}, - {"UseSpaces", Const, 0}, + {"(*Config).Fprint", Method, 0, ""}, + {"CommentedNode", Type, 0, ""}, + {"CommentedNode.Comments", Field, 0, ""}, + {"CommentedNode.Node", Field, 0, ""}, + {"Config", Type, 0, ""}, + {"Config.Indent", Field, 1, ""}, + {"Config.Mode", Field, 0, ""}, + {"Config.Tabwidth", Field, 0, ""}, + {"Fprint", Func, 0, "func(output io.Writer, fset *token.FileSet, node any) error"}, + {"Mode", Type, 0, ""}, + {"RawFormat", Const, 0, ""}, + {"SourcePos", Const, 0, ""}, + {"TabIndent", Const, 0, ""}, + {"UseSpaces", Const, 0, ""}, }, "go/scanner": { - {"(*ErrorList).Add", Method, 0}, - {"(*ErrorList).RemoveMultiples", Method, 0}, - {"(*ErrorList).Reset", Method, 0}, - {"(*Scanner).Init", Method, 0}, - {"(*Scanner).Scan", Method, 0}, - {"(Error).Error", Method, 0}, - {"(ErrorList).Err", Method, 0}, - {"(ErrorList).Error", Method, 0}, - {"(ErrorList).Len", Method, 0}, - {"(ErrorList).Less", Method, 0}, - {"(ErrorList).Sort", Method, 0}, - {"(ErrorList).Swap", Method, 0}, - {"Error", Type, 0}, - {"Error.Msg", Field, 0}, - {"Error.Pos", Field, 0}, - {"ErrorHandler", Type, 0}, - {"ErrorList", Type, 0}, - {"Mode", Type, 0}, - {"PrintError", Func, 0}, - {"ScanComments", Const, 0}, - {"Scanner", Type, 0}, - {"Scanner.ErrorCount", Field, 0}, + {"(*ErrorList).Add", Method, 0, ""}, + {"(*ErrorList).RemoveMultiples", Method, 0, ""}, + {"(*ErrorList).Reset", Method, 0, ""}, + {"(*Scanner).Init", Method, 0, ""}, + {"(*Scanner).Scan", Method, 0, ""}, + {"(Error).Error", Method, 0, ""}, + {"(ErrorList).Err", Method, 0, ""}, + {"(ErrorList).Error", Method, 0, ""}, + {"(ErrorList).Len", Method, 0, ""}, + {"(ErrorList).Less", Method, 0, ""}, + {"(ErrorList).Sort", Method, 0, ""}, + {"(ErrorList).Swap", Method, 0, ""}, + {"Error", Type, 0, ""}, + {"Error.Msg", Field, 0, ""}, + {"Error.Pos", Field, 0, ""}, + {"ErrorHandler", Type, 0, ""}, + {"ErrorList", Type, 0, ""}, + {"Mode", Type, 0, ""}, + {"PrintError", Func, 0, "func(w io.Writer, err error)"}, + {"ScanComments", Const, 0, ""}, + {"Scanner", Type, 0, ""}, + {"Scanner.ErrorCount", Field, 0, ""}, }, "go/token": { - {"(*File).AddLine", Method, 0}, - {"(*File).AddLineColumnInfo", Method, 11}, - {"(*File).AddLineInfo", Method, 0}, - {"(*File).Base", Method, 0}, - {"(*File).Line", Method, 0}, - {"(*File).LineCount", Method, 0}, - {"(*File).LineStart", Method, 12}, - {"(*File).Lines", Method, 21}, - {"(*File).MergeLine", Method, 2}, - {"(*File).Name", Method, 0}, - {"(*File).Offset", Method, 0}, - {"(*File).Pos", Method, 0}, - {"(*File).Position", Method, 0}, - {"(*File).PositionFor", Method, 4}, - {"(*File).SetLines", Method, 0}, - {"(*File).SetLinesForContent", Method, 0}, - {"(*File).Size", Method, 0}, - {"(*FileSet).AddFile", Method, 0}, - {"(*FileSet).Base", Method, 0}, - {"(*FileSet).File", Method, 0}, - {"(*FileSet).Iterate", Method, 0}, - {"(*FileSet).Position", Method, 0}, - {"(*FileSet).PositionFor", Method, 4}, - {"(*FileSet).Read", Method, 0}, - {"(*FileSet).RemoveFile", Method, 20}, - {"(*FileSet).Write", Method, 0}, - {"(*Position).IsValid", Method, 0}, - {"(Pos).IsValid", Method, 0}, - {"(Position).String", Method, 0}, - {"(Token).IsKeyword", Method, 0}, - {"(Token).IsLiteral", Method, 0}, - {"(Token).IsOperator", Method, 0}, - {"(Token).Precedence", Method, 0}, - {"(Token).String", Method, 0}, - {"ADD", Const, 0}, - {"ADD_ASSIGN", Const, 0}, - {"AND", Const, 0}, - {"AND_ASSIGN", Const, 0}, - {"AND_NOT", Const, 0}, - {"AND_NOT_ASSIGN", Const, 0}, - {"ARROW", Const, 0}, - {"ASSIGN", Const, 0}, - {"BREAK", Const, 0}, - {"CASE", Const, 0}, - {"CHAN", Const, 0}, - {"CHAR", Const, 0}, - {"COLON", Const, 0}, - {"COMMA", Const, 0}, - {"COMMENT", Const, 0}, - {"CONST", Const, 0}, - {"CONTINUE", Const, 0}, - {"DEC", Const, 0}, - {"DEFAULT", Const, 0}, - {"DEFER", Const, 0}, - {"DEFINE", Const, 0}, - {"ELLIPSIS", Const, 0}, - {"ELSE", Const, 0}, - {"EOF", Const, 0}, - {"EQL", Const, 0}, - {"FALLTHROUGH", Const, 0}, - {"FLOAT", Const, 0}, - {"FOR", Const, 0}, - {"FUNC", Const, 0}, - {"File", Type, 0}, - {"FileSet", Type, 0}, - {"GEQ", Const, 0}, - {"GO", Const, 0}, - {"GOTO", Const, 0}, - {"GTR", Const, 0}, - {"HighestPrec", Const, 0}, - {"IDENT", Const, 0}, - {"IF", Const, 0}, - {"ILLEGAL", Const, 0}, - {"IMAG", Const, 0}, - {"IMPORT", Const, 0}, - {"INC", Const, 0}, - {"INT", Const, 0}, - {"INTERFACE", Const, 0}, - {"IsExported", Func, 13}, - {"IsIdentifier", Func, 13}, - {"IsKeyword", Func, 13}, - {"LAND", Const, 0}, - {"LBRACE", Const, 0}, - {"LBRACK", Const, 0}, - {"LEQ", Const, 0}, - {"LOR", Const, 0}, - {"LPAREN", Const, 0}, - {"LSS", Const, 0}, - {"Lookup", Func, 0}, - {"LowestPrec", Const, 0}, - {"MAP", Const, 0}, - {"MUL", Const, 0}, - {"MUL_ASSIGN", Const, 0}, - {"NEQ", Const, 0}, - {"NOT", Const, 0}, - {"NewFileSet", Func, 0}, - {"NoPos", Const, 0}, - {"OR", Const, 0}, - {"OR_ASSIGN", Const, 0}, - {"PACKAGE", Const, 0}, - {"PERIOD", Const, 0}, - {"Pos", Type, 0}, - {"Position", Type, 0}, - {"Position.Column", Field, 0}, - {"Position.Filename", Field, 0}, - {"Position.Line", Field, 0}, - {"Position.Offset", Field, 0}, - {"QUO", Const, 0}, - {"QUO_ASSIGN", Const, 0}, - {"RANGE", Const, 0}, - {"RBRACE", Const, 0}, - {"RBRACK", Const, 0}, - {"REM", Const, 0}, - {"REM_ASSIGN", Const, 0}, - {"RETURN", Const, 0}, - {"RPAREN", Const, 0}, - {"SELECT", Const, 0}, - {"SEMICOLON", Const, 0}, - {"SHL", Const, 0}, - {"SHL_ASSIGN", Const, 0}, - {"SHR", Const, 0}, - {"SHR_ASSIGN", Const, 0}, - {"STRING", Const, 0}, - {"STRUCT", Const, 0}, - {"SUB", Const, 0}, - {"SUB_ASSIGN", Const, 0}, - {"SWITCH", Const, 0}, - {"TILDE", Const, 18}, - {"TYPE", Const, 0}, - {"Token", Type, 0}, - {"UnaryPrec", Const, 0}, - {"VAR", Const, 0}, - {"XOR", Const, 0}, - {"XOR_ASSIGN", Const, 0}, + {"(*File).AddLine", Method, 0, ""}, + {"(*File).AddLineColumnInfo", Method, 11, ""}, + {"(*File).AddLineInfo", Method, 0, ""}, + {"(*File).Base", Method, 0, ""}, + {"(*File).Line", Method, 0, ""}, + {"(*File).LineCount", Method, 0, ""}, + {"(*File).LineStart", Method, 12, ""}, + {"(*File).Lines", Method, 21, ""}, + {"(*File).MergeLine", Method, 2, ""}, + {"(*File).Name", Method, 0, ""}, + {"(*File).Offset", Method, 0, ""}, + {"(*File).Pos", Method, 0, ""}, + {"(*File).Position", Method, 0, ""}, + {"(*File).PositionFor", Method, 4, ""}, + {"(*File).SetLines", Method, 0, ""}, + {"(*File).SetLinesForContent", Method, 0, ""}, + {"(*File).Size", Method, 0, ""}, + {"(*FileSet).AddFile", Method, 0, ""}, + {"(*FileSet).Base", Method, 0, ""}, + {"(*FileSet).File", Method, 0, ""}, + {"(*FileSet).Iterate", Method, 0, ""}, + {"(*FileSet).Position", Method, 0, ""}, + {"(*FileSet).PositionFor", Method, 4, ""}, + {"(*FileSet).Read", Method, 0, ""}, + {"(*FileSet).RemoveFile", Method, 20, ""}, + {"(*FileSet).Write", Method, 0, ""}, + {"(*Position).IsValid", Method, 0, ""}, + {"(Pos).IsValid", Method, 0, ""}, + {"(Position).String", Method, 0, ""}, + {"(Token).IsKeyword", Method, 0, ""}, + {"(Token).IsLiteral", Method, 0, ""}, + {"(Token).IsOperator", Method, 0, ""}, + {"(Token).Precedence", Method, 0, ""}, + {"(Token).String", Method, 0, ""}, + {"ADD", Const, 0, ""}, + {"ADD_ASSIGN", Const, 0, ""}, + {"AND", Const, 0, ""}, + {"AND_ASSIGN", Const, 0, ""}, + {"AND_NOT", Const, 0, ""}, + {"AND_NOT_ASSIGN", Const, 0, ""}, + {"ARROW", Const, 0, ""}, + {"ASSIGN", Const, 0, ""}, + {"BREAK", Const, 0, ""}, + {"CASE", Const, 0, ""}, + {"CHAN", Const, 0, ""}, + {"CHAR", Const, 0, ""}, + {"COLON", Const, 0, ""}, + {"COMMA", Const, 0, ""}, + {"COMMENT", Const, 0, ""}, + {"CONST", Const, 0, ""}, + {"CONTINUE", Const, 0, ""}, + {"DEC", Const, 0, ""}, + {"DEFAULT", Const, 0, ""}, + {"DEFER", Const, 0, ""}, + {"DEFINE", Const, 0, ""}, + {"ELLIPSIS", Const, 0, ""}, + {"ELSE", Const, 0, ""}, + {"EOF", Const, 0, ""}, + {"EQL", Const, 0, ""}, + {"FALLTHROUGH", Const, 0, ""}, + {"FLOAT", Const, 0, ""}, + {"FOR", Const, 0, ""}, + {"FUNC", Const, 0, ""}, + {"File", Type, 0, ""}, + {"FileSet", Type, 0, ""}, + {"GEQ", Const, 0, ""}, + {"GO", Const, 0, ""}, + {"GOTO", Const, 0, ""}, + {"GTR", Const, 0, ""}, + {"HighestPrec", Const, 0, ""}, + {"IDENT", Const, 0, ""}, + {"IF", Const, 0, ""}, + {"ILLEGAL", Const, 0, ""}, + {"IMAG", Const, 0, ""}, + {"IMPORT", Const, 0, ""}, + {"INC", Const, 0, ""}, + {"INT", Const, 0, ""}, + {"INTERFACE", Const, 0, ""}, + {"IsExported", Func, 13, "func(name string) bool"}, + {"IsIdentifier", Func, 13, "func(name string) bool"}, + {"IsKeyword", Func, 13, "func(name string) bool"}, + {"LAND", Const, 0, ""}, + {"LBRACE", Const, 0, ""}, + {"LBRACK", Const, 0, ""}, + {"LEQ", Const, 0, ""}, + {"LOR", Const, 0, ""}, + {"LPAREN", Const, 0, ""}, + {"LSS", Const, 0, ""}, + {"Lookup", Func, 0, "func(ident string) Token"}, + {"LowestPrec", Const, 0, ""}, + {"MAP", Const, 0, ""}, + {"MUL", Const, 0, ""}, + {"MUL_ASSIGN", Const, 0, ""}, + {"NEQ", Const, 0, ""}, + {"NOT", Const, 0, ""}, + {"NewFileSet", Func, 0, "func() *FileSet"}, + {"NoPos", Const, 0, ""}, + {"OR", Const, 0, ""}, + {"OR_ASSIGN", Const, 0, ""}, + {"PACKAGE", Const, 0, ""}, + {"PERIOD", Const, 0, ""}, + {"Pos", Type, 0, ""}, + {"Position", Type, 0, ""}, + {"Position.Column", Field, 0, ""}, + {"Position.Filename", Field, 0, ""}, + {"Position.Line", Field, 0, ""}, + {"Position.Offset", Field, 0, ""}, + {"QUO", Const, 0, ""}, + {"QUO_ASSIGN", Const, 0, ""}, + {"RANGE", Const, 0, ""}, + {"RBRACE", Const, 0, ""}, + {"RBRACK", Const, 0, ""}, + {"REM", Const, 0, ""}, + {"REM_ASSIGN", Const, 0, ""}, + {"RETURN", Const, 0, ""}, + {"RPAREN", Const, 0, ""}, + {"SELECT", Const, 0, ""}, + {"SEMICOLON", Const, 0, ""}, + {"SHL", Const, 0, ""}, + {"SHL_ASSIGN", Const, 0, ""}, + {"SHR", Const, 0, ""}, + {"SHR_ASSIGN", Const, 0, ""}, + {"STRING", Const, 0, ""}, + {"STRUCT", Const, 0, ""}, + {"SUB", Const, 0, ""}, + {"SUB_ASSIGN", Const, 0, ""}, + {"SWITCH", Const, 0, ""}, + {"TILDE", Const, 18, ""}, + {"TYPE", Const, 0, ""}, + {"Token", Type, 0, ""}, + {"UnaryPrec", Const, 0, ""}, + {"VAR", Const, 0, ""}, + {"XOR", Const, 0, ""}, + {"XOR_ASSIGN", Const, 0, ""}, }, "go/types": { - {"(*Alias).Obj", Method, 22}, - {"(*Alias).Origin", Method, 23}, - {"(*Alias).Rhs", Method, 23}, - {"(*Alias).SetTypeParams", Method, 23}, - {"(*Alias).String", Method, 22}, - {"(*Alias).TypeArgs", Method, 23}, - {"(*Alias).TypeParams", Method, 23}, - {"(*Alias).Underlying", Method, 22}, - {"(*ArgumentError).Error", Method, 18}, - {"(*ArgumentError).Unwrap", Method, 18}, - {"(*Array).Elem", Method, 5}, - {"(*Array).Len", Method, 5}, - {"(*Array).String", Method, 5}, - {"(*Array).Underlying", Method, 5}, - {"(*Basic).Info", Method, 5}, - {"(*Basic).Kind", Method, 5}, - {"(*Basic).Name", Method, 5}, - {"(*Basic).String", Method, 5}, - {"(*Basic).Underlying", Method, 5}, - {"(*Builtin).Exported", Method, 5}, - {"(*Builtin).Id", Method, 5}, - {"(*Builtin).Name", Method, 5}, - {"(*Builtin).Parent", Method, 5}, - {"(*Builtin).Pkg", Method, 5}, - {"(*Builtin).Pos", Method, 5}, - {"(*Builtin).String", Method, 5}, - {"(*Builtin).Type", Method, 5}, - {"(*Chan).Dir", Method, 5}, - {"(*Chan).Elem", Method, 5}, - {"(*Chan).String", Method, 5}, - {"(*Chan).Underlying", Method, 5}, - {"(*Checker).Files", Method, 5}, - {"(*Config).Check", Method, 5}, - {"(*Const).Exported", Method, 5}, - {"(*Const).Id", Method, 5}, - {"(*Const).Name", Method, 5}, - {"(*Const).Parent", Method, 5}, - {"(*Const).Pkg", Method, 5}, - {"(*Const).Pos", Method, 5}, - {"(*Const).String", Method, 5}, - {"(*Const).Type", Method, 5}, - {"(*Const).Val", Method, 5}, - {"(*Func).Exported", Method, 5}, - {"(*Func).FullName", Method, 5}, - {"(*Func).Id", Method, 5}, - {"(*Func).Name", Method, 5}, - {"(*Func).Origin", Method, 19}, - {"(*Func).Parent", Method, 5}, - {"(*Func).Pkg", Method, 5}, - {"(*Func).Pos", Method, 5}, - {"(*Func).Scope", Method, 5}, - {"(*Func).Signature", Method, 23}, - {"(*Func).String", Method, 5}, - {"(*Func).Type", Method, 5}, - {"(*Info).ObjectOf", Method, 5}, - {"(*Info).PkgNameOf", Method, 22}, - {"(*Info).TypeOf", Method, 5}, - {"(*Initializer).String", Method, 5}, - {"(*Interface).Complete", Method, 5}, - {"(*Interface).Embedded", Method, 5}, - {"(*Interface).EmbeddedType", Method, 11}, - {"(*Interface).EmbeddedTypes", Method, 24}, - {"(*Interface).Empty", Method, 5}, - {"(*Interface).ExplicitMethod", Method, 5}, - {"(*Interface).ExplicitMethods", Method, 24}, - {"(*Interface).IsComparable", Method, 18}, - {"(*Interface).IsImplicit", Method, 18}, - {"(*Interface).IsMethodSet", Method, 18}, - {"(*Interface).MarkImplicit", Method, 18}, - {"(*Interface).Method", Method, 5}, - {"(*Interface).Methods", Method, 24}, - {"(*Interface).NumEmbeddeds", Method, 5}, - {"(*Interface).NumExplicitMethods", Method, 5}, - {"(*Interface).NumMethods", Method, 5}, - {"(*Interface).String", Method, 5}, - {"(*Interface).Underlying", Method, 5}, - {"(*Label).Exported", Method, 5}, - {"(*Label).Id", Method, 5}, - {"(*Label).Name", Method, 5}, - {"(*Label).Parent", Method, 5}, - {"(*Label).Pkg", Method, 5}, - {"(*Label).Pos", Method, 5}, - {"(*Label).String", Method, 5}, - {"(*Label).Type", Method, 5}, - {"(*Map).Elem", Method, 5}, - {"(*Map).Key", Method, 5}, - {"(*Map).String", Method, 5}, - {"(*Map).Underlying", Method, 5}, - {"(*MethodSet).At", Method, 5}, - {"(*MethodSet).Len", Method, 5}, - {"(*MethodSet).Lookup", Method, 5}, - {"(*MethodSet).Methods", Method, 24}, - {"(*MethodSet).String", Method, 5}, - {"(*Named).AddMethod", Method, 5}, - {"(*Named).Method", Method, 5}, - {"(*Named).Methods", Method, 24}, - {"(*Named).NumMethods", Method, 5}, - {"(*Named).Obj", Method, 5}, - {"(*Named).Origin", Method, 18}, - {"(*Named).SetTypeParams", Method, 18}, - {"(*Named).SetUnderlying", Method, 5}, - {"(*Named).String", Method, 5}, - {"(*Named).TypeArgs", Method, 18}, - {"(*Named).TypeParams", Method, 18}, - {"(*Named).Underlying", Method, 5}, - {"(*Nil).Exported", Method, 5}, - {"(*Nil).Id", Method, 5}, - {"(*Nil).Name", Method, 5}, - {"(*Nil).Parent", Method, 5}, - {"(*Nil).Pkg", Method, 5}, - {"(*Nil).Pos", Method, 5}, - {"(*Nil).String", Method, 5}, - {"(*Nil).Type", Method, 5}, - {"(*Package).Complete", Method, 5}, - {"(*Package).GoVersion", Method, 21}, - {"(*Package).Imports", Method, 5}, - {"(*Package).MarkComplete", Method, 5}, - {"(*Package).Name", Method, 5}, - {"(*Package).Path", Method, 5}, - {"(*Package).Scope", Method, 5}, - {"(*Package).SetImports", Method, 5}, - {"(*Package).SetName", Method, 6}, - {"(*Package).String", Method, 5}, - {"(*PkgName).Exported", Method, 5}, - {"(*PkgName).Id", Method, 5}, - {"(*PkgName).Imported", Method, 5}, - {"(*PkgName).Name", Method, 5}, - {"(*PkgName).Parent", Method, 5}, - {"(*PkgName).Pkg", Method, 5}, - {"(*PkgName).Pos", Method, 5}, - {"(*PkgName).String", Method, 5}, - {"(*PkgName).Type", Method, 5}, - {"(*Pointer).Elem", Method, 5}, - {"(*Pointer).String", Method, 5}, - {"(*Pointer).Underlying", Method, 5}, - {"(*Scope).Child", Method, 5}, - {"(*Scope).Children", Method, 24}, - {"(*Scope).Contains", Method, 5}, - {"(*Scope).End", Method, 5}, - {"(*Scope).Innermost", Method, 5}, - {"(*Scope).Insert", Method, 5}, - {"(*Scope).Len", Method, 5}, - {"(*Scope).Lookup", Method, 5}, - {"(*Scope).LookupParent", Method, 5}, - {"(*Scope).Names", Method, 5}, - {"(*Scope).NumChildren", Method, 5}, - {"(*Scope).Parent", Method, 5}, - {"(*Scope).Pos", Method, 5}, - {"(*Scope).String", Method, 5}, - {"(*Scope).WriteTo", Method, 5}, - {"(*Selection).Index", Method, 5}, - {"(*Selection).Indirect", Method, 5}, - {"(*Selection).Kind", Method, 5}, - {"(*Selection).Obj", Method, 5}, - {"(*Selection).Recv", Method, 5}, - {"(*Selection).String", Method, 5}, - {"(*Selection).Type", Method, 5}, - {"(*Signature).Params", Method, 5}, - {"(*Signature).Recv", Method, 5}, - {"(*Signature).RecvTypeParams", Method, 18}, - {"(*Signature).Results", Method, 5}, - {"(*Signature).String", Method, 5}, - {"(*Signature).TypeParams", Method, 18}, - {"(*Signature).Underlying", Method, 5}, - {"(*Signature).Variadic", Method, 5}, - {"(*Slice).Elem", Method, 5}, - {"(*Slice).String", Method, 5}, - {"(*Slice).Underlying", Method, 5}, - {"(*StdSizes).Alignof", Method, 5}, - {"(*StdSizes).Offsetsof", Method, 5}, - {"(*StdSizes).Sizeof", Method, 5}, - {"(*Struct).Field", Method, 5}, - {"(*Struct).Fields", Method, 24}, - {"(*Struct).NumFields", Method, 5}, - {"(*Struct).String", Method, 5}, - {"(*Struct).Tag", Method, 5}, - {"(*Struct).Underlying", Method, 5}, - {"(*Term).String", Method, 18}, - {"(*Term).Tilde", Method, 18}, - {"(*Term).Type", Method, 18}, - {"(*Tuple).At", Method, 5}, - {"(*Tuple).Len", Method, 5}, - {"(*Tuple).String", Method, 5}, - {"(*Tuple).Underlying", Method, 5}, - {"(*Tuple).Variables", Method, 24}, - {"(*TypeList).At", Method, 18}, - {"(*TypeList).Len", Method, 18}, - {"(*TypeList).Types", Method, 24}, - {"(*TypeName).Exported", Method, 5}, - {"(*TypeName).Id", Method, 5}, - {"(*TypeName).IsAlias", Method, 9}, - {"(*TypeName).Name", Method, 5}, - {"(*TypeName).Parent", Method, 5}, - {"(*TypeName).Pkg", Method, 5}, - {"(*TypeName).Pos", Method, 5}, - {"(*TypeName).String", Method, 5}, - {"(*TypeName).Type", Method, 5}, - {"(*TypeParam).Constraint", Method, 18}, - {"(*TypeParam).Index", Method, 18}, - {"(*TypeParam).Obj", Method, 18}, - {"(*TypeParam).SetConstraint", Method, 18}, - {"(*TypeParam).String", Method, 18}, - {"(*TypeParam).Underlying", Method, 18}, - {"(*TypeParamList).At", Method, 18}, - {"(*TypeParamList).Len", Method, 18}, - {"(*TypeParamList).TypeParams", Method, 24}, - {"(*Union).Len", Method, 18}, - {"(*Union).String", Method, 18}, - {"(*Union).Term", Method, 18}, - {"(*Union).Terms", Method, 24}, - {"(*Union).Underlying", Method, 18}, - {"(*Var).Anonymous", Method, 5}, - {"(*Var).Embedded", Method, 11}, - {"(*Var).Exported", Method, 5}, - {"(*Var).Id", Method, 5}, - {"(*Var).IsField", Method, 5}, - {"(*Var).Kind", Method, 25}, - {"(*Var).Name", Method, 5}, - {"(*Var).Origin", Method, 19}, - {"(*Var).Parent", Method, 5}, - {"(*Var).Pkg", Method, 5}, - {"(*Var).Pos", Method, 5}, - {"(*Var).SetKind", Method, 25}, - {"(*Var).String", Method, 5}, - {"(*Var).Type", Method, 5}, - {"(Checker).ObjectOf", Method, 5}, - {"(Checker).PkgNameOf", Method, 22}, - {"(Checker).TypeOf", Method, 5}, - {"(Error).Error", Method, 5}, - {"(TypeAndValue).Addressable", Method, 5}, - {"(TypeAndValue).Assignable", Method, 5}, - {"(TypeAndValue).HasOk", Method, 5}, - {"(TypeAndValue).IsBuiltin", Method, 5}, - {"(TypeAndValue).IsNil", Method, 5}, - {"(TypeAndValue).IsType", Method, 5}, - {"(TypeAndValue).IsValue", Method, 5}, - {"(TypeAndValue).IsVoid", Method, 5}, - {"(VarKind).String", Method, 25}, - {"Alias", Type, 22}, - {"ArgumentError", Type, 18}, - {"ArgumentError.Err", Field, 18}, - {"ArgumentError.Index", Field, 18}, - {"Array", Type, 5}, - {"AssertableTo", Func, 5}, - {"AssignableTo", Func, 5}, - {"Basic", Type, 5}, - {"BasicInfo", Type, 5}, - {"BasicKind", Type, 5}, - {"Bool", Const, 5}, - {"Builtin", Type, 5}, - {"Byte", Const, 5}, - {"Chan", Type, 5}, - {"ChanDir", Type, 5}, - {"CheckExpr", Func, 13}, - {"Checker", Type, 5}, - {"Checker.Info", Field, 5}, - {"Comparable", Func, 5}, - {"Complex128", Const, 5}, - {"Complex64", Const, 5}, - {"Config", Type, 5}, - {"Config.Context", Field, 18}, - {"Config.DisableUnusedImportCheck", Field, 5}, - {"Config.Error", Field, 5}, - {"Config.FakeImportC", Field, 5}, - {"Config.GoVersion", Field, 18}, - {"Config.IgnoreFuncBodies", Field, 5}, - {"Config.Importer", Field, 5}, - {"Config.Sizes", Field, 5}, - {"Const", Type, 5}, - {"Context", Type, 18}, - {"ConvertibleTo", Func, 5}, - {"DefPredeclaredTestFuncs", Func, 5}, - {"Default", Func, 8}, - {"Error", Type, 5}, - {"Error.Fset", Field, 5}, - {"Error.Msg", Field, 5}, - {"Error.Pos", Field, 5}, - {"Error.Soft", Field, 5}, - {"Eval", Func, 5}, - {"ExprString", Func, 5}, - {"FieldVal", Const, 5}, - {"FieldVar", Const, 25}, - {"Float32", Const, 5}, - {"Float64", Const, 5}, - {"Func", Type, 5}, - {"Id", Func, 5}, - {"Identical", Func, 5}, - {"IdenticalIgnoreTags", Func, 8}, - {"Implements", Func, 5}, - {"ImportMode", Type, 6}, - {"Importer", Type, 5}, - {"ImporterFrom", Type, 6}, - {"Info", Type, 5}, - {"Info.Defs", Field, 5}, - {"Info.FileVersions", Field, 22}, - {"Info.Implicits", Field, 5}, - {"Info.InitOrder", Field, 5}, - {"Info.Instances", Field, 18}, - {"Info.Scopes", Field, 5}, - {"Info.Selections", Field, 5}, - {"Info.Types", Field, 5}, - {"Info.Uses", Field, 5}, - {"Initializer", Type, 5}, - {"Initializer.Lhs", Field, 5}, - {"Initializer.Rhs", Field, 5}, - {"Instance", Type, 18}, - {"Instance.Type", Field, 18}, - {"Instance.TypeArgs", Field, 18}, - {"Instantiate", Func, 18}, - {"Int", Const, 5}, - {"Int16", Const, 5}, - {"Int32", Const, 5}, - {"Int64", Const, 5}, - {"Int8", Const, 5}, - {"Interface", Type, 5}, - {"Invalid", Const, 5}, - {"IsBoolean", Const, 5}, - {"IsComplex", Const, 5}, - {"IsConstType", Const, 5}, - {"IsFloat", Const, 5}, - {"IsInteger", Const, 5}, - {"IsInterface", Func, 5}, - {"IsNumeric", Const, 5}, - {"IsOrdered", Const, 5}, - {"IsString", Const, 5}, - {"IsUnsigned", Const, 5}, - {"IsUntyped", Const, 5}, - {"Label", Type, 5}, - {"LocalVar", Const, 25}, - {"LookupFieldOrMethod", Func, 5}, - {"LookupSelection", Func, 25}, - {"Map", Type, 5}, - {"MethodExpr", Const, 5}, - {"MethodSet", Type, 5}, - {"MethodVal", Const, 5}, - {"MissingMethod", Func, 5}, - {"Named", Type, 5}, - {"NewAlias", Func, 22}, - {"NewArray", Func, 5}, - {"NewChan", Func, 5}, - {"NewChecker", Func, 5}, - {"NewConst", Func, 5}, - {"NewContext", Func, 18}, - {"NewField", Func, 5}, - {"NewFunc", Func, 5}, - {"NewInterface", Func, 5}, - {"NewInterfaceType", Func, 11}, - {"NewLabel", Func, 5}, - {"NewMap", Func, 5}, - {"NewMethodSet", Func, 5}, - {"NewNamed", Func, 5}, - {"NewPackage", Func, 5}, - {"NewParam", Func, 5}, - {"NewPkgName", Func, 5}, - {"NewPointer", Func, 5}, - {"NewScope", Func, 5}, - {"NewSignature", Func, 5}, - {"NewSignatureType", Func, 18}, - {"NewSlice", Func, 5}, - {"NewStruct", Func, 5}, - {"NewTerm", Func, 18}, - {"NewTuple", Func, 5}, - {"NewTypeName", Func, 5}, - {"NewTypeParam", Func, 18}, - {"NewUnion", Func, 18}, - {"NewVar", Func, 5}, - {"Nil", Type, 5}, - {"Object", Type, 5}, - {"ObjectString", Func, 5}, - {"Package", Type, 5}, - {"PackageVar", Const, 25}, - {"ParamVar", Const, 25}, - {"PkgName", Type, 5}, - {"Pointer", Type, 5}, - {"Qualifier", Type, 5}, - {"RecvOnly", Const, 5}, - {"RecvVar", Const, 25}, - {"RelativeTo", Func, 5}, - {"ResultVar", Const, 25}, - {"Rune", Const, 5}, - {"Satisfies", Func, 20}, - {"Scope", Type, 5}, - {"Selection", Type, 5}, - {"SelectionKind", Type, 5}, - {"SelectionString", Func, 5}, - {"SendOnly", Const, 5}, - {"SendRecv", Const, 5}, - {"Signature", Type, 5}, - {"Sizes", Type, 5}, - {"SizesFor", Func, 9}, - {"Slice", Type, 5}, - {"StdSizes", Type, 5}, - {"StdSizes.MaxAlign", Field, 5}, - {"StdSizes.WordSize", Field, 5}, - {"String", Const, 5}, - {"Struct", Type, 5}, - {"Term", Type, 18}, - {"Tuple", Type, 5}, - {"Typ", Var, 5}, - {"Type", Type, 5}, - {"TypeAndValue", Type, 5}, - {"TypeAndValue.Type", Field, 5}, - {"TypeAndValue.Value", Field, 5}, - {"TypeList", Type, 18}, - {"TypeName", Type, 5}, - {"TypeParam", Type, 18}, - {"TypeParamList", Type, 18}, - {"TypeString", Func, 5}, - {"Uint", Const, 5}, - {"Uint16", Const, 5}, - {"Uint32", Const, 5}, - {"Uint64", Const, 5}, - {"Uint8", Const, 5}, - {"Uintptr", Const, 5}, - {"Unalias", Func, 22}, - {"Union", Type, 18}, - {"Universe", Var, 5}, - {"Unsafe", Var, 5}, - {"UnsafePointer", Const, 5}, - {"UntypedBool", Const, 5}, - {"UntypedComplex", Const, 5}, - {"UntypedFloat", Const, 5}, - {"UntypedInt", Const, 5}, - {"UntypedNil", Const, 5}, - {"UntypedRune", Const, 5}, - {"UntypedString", Const, 5}, - {"Var", Type, 5}, - {"VarKind", Type, 25}, - {"WriteExpr", Func, 5}, - {"WriteSignature", Func, 5}, - {"WriteType", Func, 5}, + {"(*Alias).Obj", Method, 22, ""}, + {"(*Alias).Origin", Method, 23, ""}, + {"(*Alias).Rhs", Method, 23, ""}, + {"(*Alias).SetTypeParams", Method, 23, ""}, + {"(*Alias).String", Method, 22, ""}, + {"(*Alias).TypeArgs", Method, 23, ""}, + {"(*Alias).TypeParams", Method, 23, ""}, + {"(*Alias).Underlying", Method, 22, ""}, + {"(*ArgumentError).Error", Method, 18, ""}, + {"(*ArgumentError).Unwrap", Method, 18, ""}, + {"(*Array).Elem", Method, 5, ""}, + {"(*Array).Len", Method, 5, ""}, + {"(*Array).String", Method, 5, ""}, + {"(*Array).Underlying", Method, 5, ""}, + {"(*Basic).Info", Method, 5, ""}, + {"(*Basic).Kind", Method, 5, ""}, + {"(*Basic).Name", Method, 5, ""}, + {"(*Basic).String", Method, 5, ""}, + {"(*Basic).Underlying", Method, 5, ""}, + {"(*Builtin).Exported", Method, 5, ""}, + {"(*Builtin).Id", Method, 5, ""}, + {"(*Builtin).Name", Method, 5, ""}, + {"(*Builtin).Parent", Method, 5, ""}, + {"(*Builtin).Pkg", Method, 5, ""}, + {"(*Builtin).Pos", Method, 5, ""}, + {"(*Builtin).String", Method, 5, ""}, + {"(*Builtin).Type", Method, 5, ""}, + {"(*Chan).Dir", Method, 5, ""}, + {"(*Chan).Elem", Method, 5, ""}, + {"(*Chan).String", Method, 5, ""}, + {"(*Chan).Underlying", Method, 5, ""}, + {"(*Checker).Files", Method, 5, ""}, + {"(*Config).Check", Method, 5, ""}, + {"(*Const).Exported", Method, 5, ""}, + {"(*Const).Id", Method, 5, ""}, + {"(*Const).Name", Method, 5, ""}, + {"(*Const).Parent", Method, 5, ""}, + {"(*Const).Pkg", Method, 5, ""}, + {"(*Const).Pos", Method, 5, ""}, + {"(*Const).String", Method, 5, ""}, + {"(*Const).Type", Method, 5, ""}, + {"(*Const).Val", Method, 5, ""}, + {"(*Func).Exported", Method, 5, ""}, + {"(*Func).FullName", Method, 5, ""}, + {"(*Func).Id", Method, 5, ""}, + {"(*Func).Name", Method, 5, ""}, + {"(*Func).Origin", Method, 19, ""}, + {"(*Func).Parent", Method, 5, ""}, + {"(*Func).Pkg", Method, 5, ""}, + {"(*Func).Pos", Method, 5, ""}, + {"(*Func).Scope", Method, 5, ""}, + {"(*Func).Signature", Method, 23, ""}, + {"(*Func).String", Method, 5, ""}, + {"(*Func).Type", Method, 5, ""}, + {"(*Info).ObjectOf", Method, 5, ""}, + {"(*Info).PkgNameOf", Method, 22, ""}, + {"(*Info).TypeOf", Method, 5, ""}, + {"(*Initializer).String", Method, 5, ""}, + {"(*Interface).Complete", Method, 5, ""}, + {"(*Interface).Embedded", Method, 5, ""}, + {"(*Interface).EmbeddedType", Method, 11, ""}, + {"(*Interface).EmbeddedTypes", Method, 24, ""}, + {"(*Interface).Empty", Method, 5, ""}, + {"(*Interface).ExplicitMethod", Method, 5, ""}, + {"(*Interface).ExplicitMethods", Method, 24, ""}, + {"(*Interface).IsComparable", Method, 18, ""}, + {"(*Interface).IsImplicit", Method, 18, ""}, + {"(*Interface).IsMethodSet", Method, 18, ""}, + {"(*Interface).MarkImplicit", Method, 18, ""}, + {"(*Interface).Method", Method, 5, ""}, + {"(*Interface).Methods", Method, 24, ""}, + {"(*Interface).NumEmbeddeds", Method, 5, ""}, + {"(*Interface).NumExplicitMethods", Method, 5, ""}, + {"(*Interface).NumMethods", Method, 5, ""}, + {"(*Interface).String", Method, 5, ""}, + {"(*Interface).Underlying", Method, 5, ""}, + {"(*Label).Exported", Method, 5, ""}, + {"(*Label).Id", Method, 5, ""}, + {"(*Label).Name", Method, 5, ""}, + {"(*Label).Parent", Method, 5, ""}, + {"(*Label).Pkg", Method, 5, ""}, + {"(*Label).Pos", Method, 5, ""}, + {"(*Label).String", Method, 5, ""}, + {"(*Label).Type", Method, 5, ""}, + {"(*Map).Elem", Method, 5, ""}, + {"(*Map).Key", Method, 5, ""}, + {"(*Map).String", Method, 5, ""}, + {"(*Map).Underlying", Method, 5, ""}, + {"(*MethodSet).At", Method, 5, ""}, + {"(*MethodSet).Len", Method, 5, ""}, + {"(*MethodSet).Lookup", Method, 5, ""}, + {"(*MethodSet).Methods", Method, 24, ""}, + {"(*MethodSet).String", Method, 5, ""}, + {"(*Named).AddMethod", Method, 5, ""}, + {"(*Named).Method", Method, 5, ""}, + {"(*Named).Methods", Method, 24, ""}, + {"(*Named).NumMethods", Method, 5, ""}, + {"(*Named).Obj", Method, 5, ""}, + {"(*Named).Origin", Method, 18, ""}, + {"(*Named).SetTypeParams", Method, 18, ""}, + {"(*Named).SetUnderlying", Method, 5, ""}, + {"(*Named).String", Method, 5, ""}, + {"(*Named).TypeArgs", Method, 18, ""}, + {"(*Named).TypeParams", Method, 18, ""}, + {"(*Named).Underlying", Method, 5, ""}, + {"(*Nil).Exported", Method, 5, ""}, + {"(*Nil).Id", Method, 5, ""}, + {"(*Nil).Name", Method, 5, ""}, + {"(*Nil).Parent", Method, 5, ""}, + {"(*Nil).Pkg", Method, 5, ""}, + {"(*Nil).Pos", Method, 5, ""}, + {"(*Nil).String", Method, 5, ""}, + {"(*Nil).Type", Method, 5, ""}, + {"(*Package).Complete", Method, 5, ""}, + {"(*Package).GoVersion", Method, 21, ""}, + {"(*Package).Imports", Method, 5, ""}, + {"(*Package).MarkComplete", Method, 5, ""}, + {"(*Package).Name", Method, 5, ""}, + {"(*Package).Path", Method, 5, ""}, + {"(*Package).Scope", Method, 5, ""}, + {"(*Package).SetImports", Method, 5, ""}, + {"(*Package).SetName", Method, 6, ""}, + {"(*Package).String", Method, 5, ""}, + {"(*PkgName).Exported", Method, 5, ""}, + {"(*PkgName).Id", Method, 5, ""}, + {"(*PkgName).Imported", Method, 5, ""}, + {"(*PkgName).Name", Method, 5, ""}, + {"(*PkgName).Parent", Method, 5, ""}, + {"(*PkgName).Pkg", Method, 5, ""}, + {"(*PkgName).Pos", Method, 5, ""}, + {"(*PkgName).String", Method, 5, ""}, + {"(*PkgName).Type", Method, 5, ""}, + {"(*Pointer).Elem", Method, 5, ""}, + {"(*Pointer).String", Method, 5, ""}, + {"(*Pointer).Underlying", Method, 5, ""}, + {"(*Scope).Child", Method, 5, ""}, + {"(*Scope).Children", Method, 24, ""}, + {"(*Scope).Contains", Method, 5, ""}, + {"(*Scope).End", Method, 5, ""}, + {"(*Scope).Innermost", Method, 5, ""}, + {"(*Scope).Insert", Method, 5, ""}, + {"(*Scope).Len", Method, 5, ""}, + {"(*Scope).Lookup", Method, 5, ""}, + {"(*Scope).LookupParent", Method, 5, ""}, + {"(*Scope).Names", Method, 5, ""}, + {"(*Scope).NumChildren", Method, 5, ""}, + {"(*Scope).Parent", Method, 5, ""}, + {"(*Scope).Pos", Method, 5, ""}, + {"(*Scope).String", Method, 5, ""}, + {"(*Scope).WriteTo", Method, 5, ""}, + {"(*Selection).Index", Method, 5, ""}, + {"(*Selection).Indirect", Method, 5, ""}, + {"(*Selection).Kind", Method, 5, ""}, + {"(*Selection).Obj", Method, 5, ""}, + {"(*Selection).Recv", Method, 5, ""}, + {"(*Selection).String", Method, 5, ""}, + {"(*Selection).Type", Method, 5, ""}, + {"(*Signature).Params", Method, 5, ""}, + {"(*Signature).Recv", Method, 5, ""}, + {"(*Signature).RecvTypeParams", Method, 18, ""}, + {"(*Signature).Results", Method, 5, ""}, + {"(*Signature).String", Method, 5, ""}, + {"(*Signature).TypeParams", Method, 18, ""}, + {"(*Signature).Underlying", Method, 5, ""}, + {"(*Signature).Variadic", Method, 5, ""}, + {"(*Slice).Elem", Method, 5, ""}, + {"(*Slice).String", Method, 5, ""}, + {"(*Slice).Underlying", Method, 5, ""}, + {"(*StdSizes).Alignof", Method, 5, ""}, + {"(*StdSizes).Offsetsof", Method, 5, ""}, + {"(*StdSizes).Sizeof", Method, 5, ""}, + {"(*Struct).Field", Method, 5, ""}, + {"(*Struct).Fields", Method, 24, ""}, + {"(*Struct).NumFields", Method, 5, ""}, + {"(*Struct).String", Method, 5, ""}, + {"(*Struct).Tag", Method, 5, ""}, + {"(*Struct).Underlying", Method, 5, ""}, + {"(*Term).String", Method, 18, ""}, + {"(*Term).Tilde", Method, 18, ""}, + {"(*Term).Type", Method, 18, ""}, + {"(*Tuple).At", Method, 5, ""}, + {"(*Tuple).Len", Method, 5, ""}, + {"(*Tuple).String", Method, 5, ""}, + {"(*Tuple).Underlying", Method, 5, ""}, + {"(*Tuple).Variables", Method, 24, ""}, + {"(*TypeList).At", Method, 18, ""}, + {"(*TypeList).Len", Method, 18, ""}, + {"(*TypeList).Types", Method, 24, ""}, + {"(*TypeName).Exported", Method, 5, ""}, + {"(*TypeName).Id", Method, 5, ""}, + {"(*TypeName).IsAlias", Method, 9, ""}, + {"(*TypeName).Name", Method, 5, ""}, + {"(*TypeName).Parent", Method, 5, ""}, + {"(*TypeName).Pkg", Method, 5, ""}, + {"(*TypeName).Pos", Method, 5, ""}, + {"(*TypeName).String", Method, 5, ""}, + {"(*TypeName).Type", Method, 5, ""}, + {"(*TypeParam).Constraint", Method, 18, ""}, + {"(*TypeParam).Index", Method, 18, ""}, + {"(*TypeParam).Obj", Method, 18, ""}, + {"(*TypeParam).SetConstraint", Method, 18, ""}, + {"(*TypeParam).String", Method, 18, ""}, + {"(*TypeParam).Underlying", Method, 18, ""}, + {"(*TypeParamList).At", Method, 18, ""}, + {"(*TypeParamList).Len", Method, 18, ""}, + {"(*TypeParamList).TypeParams", Method, 24, ""}, + {"(*Union).Len", Method, 18, ""}, + {"(*Union).String", Method, 18, ""}, + {"(*Union).Term", Method, 18, ""}, + {"(*Union).Terms", Method, 24, ""}, + {"(*Union).Underlying", Method, 18, ""}, + {"(*Var).Anonymous", Method, 5, ""}, + {"(*Var).Embedded", Method, 11, ""}, + {"(*Var).Exported", Method, 5, ""}, + {"(*Var).Id", Method, 5, ""}, + {"(*Var).IsField", Method, 5, ""}, + {"(*Var).Kind", Method, 25, ""}, + {"(*Var).Name", Method, 5, ""}, + {"(*Var).Origin", Method, 19, ""}, + {"(*Var).Parent", Method, 5, ""}, + {"(*Var).Pkg", Method, 5, ""}, + {"(*Var).Pos", Method, 5, ""}, + {"(*Var).SetKind", Method, 25, ""}, + {"(*Var).String", Method, 5, ""}, + {"(*Var).Type", Method, 5, ""}, + {"(Checker).ObjectOf", Method, 5, ""}, + {"(Checker).PkgNameOf", Method, 22, ""}, + {"(Checker).TypeOf", Method, 5, ""}, + {"(Error).Error", Method, 5, ""}, + {"(TypeAndValue).Addressable", Method, 5, ""}, + {"(TypeAndValue).Assignable", Method, 5, ""}, + {"(TypeAndValue).HasOk", Method, 5, ""}, + {"(TypeAndValue).IsBuiltin", Method, 5, ""}, + {"(TypeAndValue).IsNil", Method, 5, ""}, + {"(TypeAndValue).IsType", Method, 5, ""}, + {"(TypeAndValue).IsValue", Method, 5, ""}, + {"(TypeAndValue).IsVoid", Method, 5, ""}, + {"(VarKind).String", Method, 25, ""}, + {"Alias", Type, 22, ""}, + {"ArgumentError", Type, 18, ""}, + {"ArgumentError.Err", Field, 18, ""}, + {"ArgumentError.Index", Field, 18, ""}, + {"Array", Type, 5, ""}, + {"AssertableTo", Func, 5, "func(V *Interface, T Type) bool"}, + {"AssignableTo", Func, 5, "func(V Type, T Type) bool"}, + {"Basic", Type, 5, ""}, + {"BasicInfo", Type, 5, ""}, + {"BasicKind", Type, 5, ""}, + {"Bool", Const, 5, ""}, + {"Builtin", Type, 5, ""}, + {"Byte", Const, 5, ""}, + {"Chan", Type, 5, ""}, + {"ChanDir", Type, 5, ""}, + {"CheckExpr", Func, 13, "func(fset *token.FileSet, pkg *Package, pos token.Pos, expr ast.Expr, info *Info) (err error)"}, + {"Checker", Type, 5, ""}, + {"Checker.Info", Field, 5, ""}, + {"Comparable", Func, 5, "func(T Type) bool"}, + {"Complex128", Const, 5, ""}, + {"Complex64", Const, 5, ""}, + {"Config", Type, 5, ""}, + {"Config.Context", Field, 18, ""}, + {"Config.DisableUnusedImportCheck", Field, 5, ""}, + {"Config.Error", Field, 5, ""}, + {"Config.FakeImportC", Field, 5, ""}, + {"Config.GoVersion", Field, 18, ""}, + {"Config.IgnoreFuncBodies", Field, 5, ""}, + {"Config.Importer", Field, 5, ""}, + {"Config.Sizes", Field, 5, ""}, + {"Const", Type, 5, ""}, + {"Context", Type, 18, ""}, + {"ConvertibleTo", Func, 5, "func(V Type, T Type) bool"}, + {"DefPredeclaredTestFuncs", Func, 5, "func()"}, + {"Default", Func, 8, "func(t Type) Type"}, + {"Error", Type, 5, ""}, + {"Error.Fset", Field, 5, ""}, + {"Error.Msg", Field, 5, ""}, + {"Error.Pos", Field, 5, ""}, + {"Error.Soft", Field, 5, ""}, + {"Eval", Func, 5, "func(fset *token.FileSet, pkg *Package, pos token.Pos, expr string) (_ TypeAndValue, err error)"}, + {"ExprString", Func, 5, "func(x ast.Expr) string"}, + {"FieldVal", Const, 5, ""}, + {"FieldVar", Const, 25, ""}, + {"Float32", Const, 5, ""}, + {"Float64", Const, 5, ""}, + {"Func", Type, 5, ""}, + {"Id", Func, 5, "func(pkg *Package, name string) string"}, + {"Identical", Func, 5, "func(x Type, y Type) bool"}, + {"IdenticalIgnoreTags", Func, 8, "func(x Type, y Type) bool"}, + {"Implements", Func, 5, "func(V Type, T *Interface) bool"}, + {"ImportMode", Type, 6, ""}, + {"Importer", Type, 5, ""}, + {"ImporterFrom", Type, 6, ""}, + {"Info", Type, 5, ""}, + {"Info.Defs", Field, 5, ""}, + {"Info.FileVersions", Field, 22, ""}, + {"Info.Implicits", Field, 5, ""}, + {"Info.InitOrder", Field, 5, ""}, + {"Info.Instances", Field, 18, ""}, + {"Info.Scopes", Field, 5, ""}, + {"Info.Selections", Field, 5, ""}, + {"Info.Types", Field, 5, ""}, + {"Info.Uses", Field, 5, ""}, + {"Initializer", Type, 5, ""}, + {"Initializer.Lhs", Field, 5, ""}, + {"Initializer.Rhs", Field, 5, ""}, + {"Instance", Type, 18, ""}, + {"Instance.Type", Field, 18, ""}, + {"Instance.TypeArgs", Field, 18, ""}, + {"Instantiate", Func, 18, "func(ctxt *Context, orig Type, targs []Type, validate bool) (Type, error)"}, + {"Int", Const, 5, ""}, + {"Int16", Const, 5, ""}, + {"Int32", Const, 5, ""}, + {"Int64", Const, 5, ""}, + {"Int8", Const, 5, ""}, + {"Interface", Type, 5, ""}, + {"Invalid", Const, 5, ""}, + {"IsBoolean", Const, 5, ""}, + {"IsComplex", Const, 5, ""}, + {"IsConstType", Const, 5, ""}, + {"IsFloat", Const, 5, ""}, + {"IsInteger", Const, 5, ""}, + {"IsInterface", Func, 5, "func(t Type) bool"}, + {"IsNumeric", Const, 5, ""}, + {"IsOrdered", Const, 5, ""}, + {"IsString", Const, 5, ""}, + {"IsUnsigned", Const, 5, ""}, + {"IsUntyped", Const, 5, ""}, + {"Label", Type, 5, ""}, + {"LocalVar", Const, 25, ""}, + {"LookupFieldOrMethod", Func, 5, "func(T Type, addressable bool, pkg *Package, name string) (obj Object, index []int, indirect bool)"}, + {"LookupSelection", Func, 25, ""}, + {"Map", Type, 5, ""}, + {"MethodExpr", Const, 5, ""}, + {"MethodSet", Type, 5, ""}, + {"MethodVal", Const, 5, ""}, + {"MissingMethod", Func, 5, "func(V Type, T *Interface, static bool) (method *Func, wrongType bool)"}, + {"Named", Type, 5, ""}, + {"NewAlias", Func, 22, "func(obj *TypeName, rhs Type) *Alias"}, + {"NewArray", Func, 5, "func(elem Type, len int64) *Array"}, + {"NewChan", Func, 5, "func(dir ChanDir, elem Type) *Chan"}, + {"NewChecker", Func, 5, "func(conf *Config, fset *token.FileSet, pkg *Package, info *Info) *Checker"}, + {"NewConst", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type, val constant.Value) *Const"}, + {"NewContext", Func, 18, "func() *Context"}, + {"NewField", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type, embedded bool) *Var"}, + {"NewFunc", Func, 5, "func(pos token.Pos, pkg *Package, name string, sig *Signature) *Func"}, + {"NewInterface", Func, 5, "func(methods []*Func, embeddeds []*Named) *Interface"}, + {"NewInterfaceType", Func, 11, "func(methods []*Func, embeddeds []Type) *Interface"}, + {"NewLabel", Func, 5, "func(pos token.Pos, pkg *Package, name string) *Label"}, + {"NewMap", Func, 5, "func(key Type, elem Type) *Map"}, + {"NewMethodSet", Func, 5, "func(T Type) *MethodSet"}, + {"NewNamed", Func, 5, "func(obj *TypeName, underlying Type, methods []*Func) *Named"}, + {"NewPackage", Func, 5, "func(path string, name string) *Package"}, + {"NewParam", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type) *Var"}, + {"NewPkgName", Func, 5, "func(pos token.Pos, pkg *Package, name string, imported *Package) *PkgName"}, + {"NewPointer", Func, 5, "func(elem Type) *Pointer"}, + {"NewScope", Func, 5, "func(parent *Scope, pos token.Pos, end token.Pos, comment string) *Scope"}, + {"NewSignature", Func, 5, "func(recv *Var, params *Tuple, results *Tuple, variadic bool) *Signature"}, + {"NewSignatureType", Func, 18, "func(recv *Var, recvTypeParams []*TypeParam, typeParams []*TypeParam, params *Tuple, results *Tuple, variadic bool) *Signature"}, + {"NewSlice", Func, 5, "func(elem Type) *Slice"}, + {"NewStruct", Func, 5, "func(fields []*Var, tags []string) *Struct"}, + {"NewTerm", Func, 18, "func(tilde bool, typ Type) *Term"}, + {"NewTuple", Func, 5, "func(x ...*Var) *Tuple"}, + {"NewTypeName", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type) *TypeName"}, + {"NewTypeParam", Func, 18, "func(obj *TypeName, constraint Type) *TypeParam"}, + {"NewUnion", Func, 18, "func(terms []*Term) *Union"}, + {"NewVar", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type) *Var"}, + {"Nil", Type, 5, ""}, + {"Object", Type, 5, ""}, + {"ObjectString", Func, 5, "func(obj Object, qf Qualifier) string"}, + {"Package", Type, 5, ""}, + {"PackageVar", Const, 25, ""}, + {"ParamVar", Const, 25, ""}, + {"PkgName", Type, 5, ""}, + {"Pointer", Type, 5, ""}, + {"Qualifier", Type, 5, ""}, + {"RecvOnly", Const, 5, ""}, + {"RecvVar", Const, 25, ""}, + {"RelativeTo", Func, 5, "func(pkg *Package) Qualifier"}, + {"ResultVar", Const, 25, ""}, + {"Rune", Const, 5, ""}, + {"Satisfies", Func, 20, "func(V Type, T *Interface) bool"}, + {"Scope", Type, 5, ""}, + {"Selection", Type, 5, ""}, + {"SelectionKind", Type, 5, ""}, + {"SelectionString", Func, 5, "func(s *Selection, qf Qualifier) string"}, + {"SendOnly", Const, 5, ""}, + {"SendRecv", Const, 5, ""}, + {"Signature", Type, 5, ""}, + {"Sizes", Type, 5, ""}, + {"SizesFor", Func, 9, "func(compiler string, arch string) Sizes"}, + {"Slice", Type, 5, ""}, + {"StdSizes", Type, 5, ""}, + {"StdSizes.MaxAlign", Field, 5, ""}, + {"StdSizes.WordSize", Field, 5, ""}, + {"String", Const, 5, ""}, + {"Struct", Type, 5, ""}, + {"Term", Type, 18, ""}, + {"Tuple", Type, 5, ""}, + {"Typ", Var, 5, ""}, + {"Type", Type, 5, ""}, + {"TypeAndValue", Type, 5, ""}, + {"TypeAndValue.Type", Field, 5, ""}, + {"TypeAndValue.Value", Field, 5, ""}, + {"TypeList", Type, 18, ""}, + {"TypeName", Type, 5, ""}, + {"TypeParam", Type, 18, ""}, + {"TypeParamList", Type, 18, ""}, + {"TypeString", Func, 5, "func(typ Type, qf Qualifier) string"}, + {"Uint", Const, 5, ""}, + {"Uint16", Const, 5, ""}, + {"Uint32", Const, 5, ""}, + {"Uint64", Const, 5, ""}, + {"Uint8", Const, 5, ""}, + {"Uintptr", Const, 5, ""}, + {"Unalias", Func, 22, "func(t Type) Type"}, + {"Union", Type, 18, ""}, + {"Universe", Var, 5, ""}, + {"Unsafe", Var, 5, ""}, + {"UnsafePointer", Const, 5, ""}, + {"UntypedBool", Const, 5, ""}, + {"UntypedComplex", Const, 5, ""}, + {"UntypedFloat", Const, 5, ""}, + {"UntypedInt", Const, 5, ""}, + {"UntypedNil", Const, 5, ""}, + {"UntypedRune", Const, 5, ""}, + {"UntypedString", Const, 5, ""}, + {"Var", Type, 5, ""}, + {"VarKind", Type, 25, ""}, + {"WriteExpr", Func, 5, "func(buf *bytes.Buffer, x ast.Expr)"}, + {"WriteSignature", Func, 5, "func(buf *bytes.Buffer, sig *Signature, qf Qualifier)"}, + {"WriteType", Func, 5, "func(buf *bytes.Buffer, typ Type, qf Qualifier)"}, }, "go/version": { - {"Compare", Func, 22}, - {"IsValid", Func, 22}, - {"Lang", Func, 22}, + {"Compare", Func, 22, "func(x string, y string) int"}, + {"IsValid", Func, 22, "func(x string) bool"}, + {"Lang", Func, 22, "func(x string) string"}, }, "hash": { - {"Hash", Type, 0}, - {"Hash32", Type, 0}, - {"Hash64", Type, 0}, + {"Hash", Type, 0, ""}, + {"Hash32", Type, 0, ""}, + {"Hash64", Type, 0, ""}, }, "hash/adler32": { - {"Checksum", Func, 0}, - {"New", Func, 0}, - {"Size", Const, 0}, + {"Checksum", Func, 0, "func(data []byte) uint32"}, + {"New", Func, 0, "func() hash.Hash32"}, + {"Size", Const, 0, ""}, }, "hash/crc32": { - {"Castagnoli", Const, 0}, - {"Checksum", Func, 0}, - {"ChecksumIEEE", Func, 0}, - {"IEEE", Const, 0}, - {"IEEETable", Var, 0}, - {"Koopman", Const, 0}, - {"MakeTable", Func, 0}, - {"New", Func, 0}, - {"NewIEEE", Func, 0}, - {"Size", Const, 0}, - {"Table", Type, 0}, - {"Update", Func, 0}, + {"Castagnoli", Const, 0, ""}, + {"Checksum", Func, 0, "func(data []byte, tab *Table) uint32"}, + {"ChecksumIEEE", Func, 0, "func(data []byte) uint32"}, + {"IEEE", Const, 0, ""}, + {"IEEETable", Var, 0, ""}, + {"Koopman", Const, 0, ""}, + {"MakeTable", Func, 0, "func(poly uint32) *Table"}, + {"New", Func, 0, "func(tab *Table) hash.Hash32"}, + {"NewIEEE", Func, 0, "func() hash.Hash32"}, + {"Size", Const, 0, ""}, + {"Table", Type, 0, ""}, + {"Update", Func, 0, "func(crc uint32, tab *Table, p []byte) uint32"}, }, "hash/crc64": { - {"Checksum", Func, 0}, - {"ECMA", Const, 0}, - {"ISO", Const, 0}, - {"MakeTable", Func, 0}, - {"New", Func, 0}, - {"Size", Const, 0}, - {"Table", Type, 0}, - {"Update", Func, 0}, + {"Checksum", Func, 0, "func(data []byte, tab *Table) uint64"}, + {"ECMA", Const, 0, ""}, + {"ISO", Const, 0, ""}, + {"MakeTable", Func, 0, "func(poly uint64) *Table"}, + {"New", Func, 0, "func(tab *Table) hash.Hash64"}, + {"Size", Const, 0, ""}, + {"Table", Type, 0, ""}, + {"Update", Func, 0, "func(crc uint64, tab *Table, p []byte) uint64"}, }, "hash/fnv": { - {"New128", Func, 9}, - {"New128a", Func, 9}, - {"New32", Func, 0}, - {"New32a", Func, 0}, - {"New64", Func, 0}, - {"New64a", Func, 0}, + {"New128", Func, 9, "func() hash.Hash"}, + {"New128a", Func, 9, "func() hash.Hash"}, + {"New32", Func, 0, "func() hash.Hash32"}, + {"New32a", Func, 0, "func() hash.Hash32"}, + {"New64", Func, 0, "func() hash.Hash64"}, + {"New64a", Func, 0, "func() hash.Hash64"}, }, "hash/maphash": { - {"(*Hash).BlockSize", Method, 14}, - {"(*Hash).Reset", Method, 14}, - {"(*Hash).Seed", Method, 14}, - {"(*Hash).SetSeed", Method, 14}, - {"(*Hash).Size", Method, 14}, - {"(*Hash).Sum", Method, 14}, - {"(*Hash).Sum64", Method, 14}, - {"(*Hash).Write", Method, 14}, - {"(*Hash).WriteByte", Method, 14}, - {"(*Hash).WriteString", Method, 14}, - {"Bytes", Func, 19}, - {"Comparable", Func, 24}, - {"Hash", Type, 14}, - {"MakeSeed", Func, 14}, - {"Seed", Type, 14}, - {"String", Func, 19}, - {"WriteComparable", Func, 24}, + {"(*Hash).BlockSize", Method, 14, ""}, + {"(*Hash).Reset", Method, 14, ""}, + {"(*Hash).Seed", Method, 14, ""}, + {"(*Hash).SetSeed", Method, 14, ""}, + {"(*Hash).Size", Method, 14, ""}, + {"(*Hash).Sum", Method, 14, ""}, + {"(*Hash).Sum64", Method, 14, ""}, + {"(*Hash).Write", Method, 14, ""}, + {"(*Hash).WriteByte", Method, 14, ""}, + {"(*Hash).WriteString", Method, 14, ""}, + {"Bytes", Func, 19, "func(seed Seed, b []byte) uint64"}, + {"Comparable", Func, 24, "func[T comparable](seed Seed, v T) uint64"}, + {"Hash", Type, 14, ""}, + {"MakeSeed", Func, 14, "func() Seed"}, + {"Seed", Type, 14, ""}, + {"String", Func, 19, "func(seed Seed, s string) uint64"}, + {"WriteComparable", Func, 24, "func[T comparable](h *Hash, x T)"}, }, "html": { - {"EscapeString", Func, 0}, - {"UnescapeString", Func, 0}, + {"EscapeString", Func, 0, "func(s string) string"}, + {"UnescapeString", Func, 0, "func(s string) string"}, }, "html/template": { - {"(*Error).Error", Method, 0}, - {"(*Template).AddParseTree", Method, 0}, - {"(*Template).Clone", Method, 0}, - {"(*Template).DefinedTemplates", Method, 6}, - {"(*Template).Delims", Method, 0}, - {"(*Template).Execute", Method, 0}, - {"(*Template).ExecuteTemplate", Method, 0}, - {"(*Template).Funcs", Method, 0}, - {"(*Template).Lookup", Method, 0}, - {"(*Template).Name", Method, 0}, - {"(*Template).New", Method, 0}, - {"(*Template).Option", Method, 5}, - {"(*Template).Parse", Method, 0}, - {"(*Template).ParseFS", Method, 16}, - {"(*Template).ParseFiles", Method, 0}, - {"(*Template).ParseGlob", Method, 0}, - {"(*Template).Templates", Method, 0}, - {"CSS", Type, 0}, - {"ErrAmbigContext", Const, 0}, - {"ErrBadHTML", Const, 0}, - {"ErrBranchEnd", Const, 0}, - {"ErrEndContext", Const, 0}, - {"ErrJSTemplate", Const, 21}, - {"ErrNoSuchTemplate", Const, 0}, - {"ErrOutputContext", Const, 0}, - {"ErrPartialCharset", Const, 0}, - {"ErrPartialEscape", Const, 0}, - {"ErrPredefinedEscaper", Const, 9}, - {"ErrRangeLoopReentry", Const, 0}, - {"ErrSlashAmbig", Const, 0}, - {"Error", Type, 0}, - {"Error.Description", Field, 0}, - {"Error.ErrorCode", Field, 0}, - {"Error.Line", Field, 0}, - {"Error.Name", Field, 0}, - {"Error.Node", Field, 4}, - {"ErrorCode", Type, 0}, - {"FuncMap", Type, 0}, - {"HTML", Type, 0}, - {"HTMLAttr", Type, 0}, - {"HTMLEscape", Func, 0}, - {"HTMLEscapeString", Func, 0}, - {"HTMLEscaper", Func, 0}, - {"IsTrue", Func, 6}, - {"JS", Type, 0}, - {"JSEscape", Func, 0}, - {"JSEscapeString", Func, 0}, - {"JSEscaper", Func, 0}, - {"JSStr", Type, 0}, - {"Must", Func, 0}, - {"New", Func, 0}, - {"OK", Const, 0}, - {"ParseFS", Func, 16}, - {"ParseFiles", Func, 0}, - {"ParseGlob", Func, 0}, - {"Srcset", Type, 10}, - {"Template", Type, 0}, - {"Template.Tree", Field, 2}, - {"URL", Type, 0}, - {"URLQueryEscaper", Func, 0}, + {"(*Error).Error", Method, 0, ""}, + {"(*Template).AddParseTree", Method, 0, ""}, + {"(*Template).Clone", Method, 0, ""}, + {"(*Template).DefinedTemplates", Method, 6, ""}, + {"(*Template).Delims", Method, 0, ""}, + {"(*Template).Execute", Method, 0, ""}, + {"(*Template).ExecuteTemplate", Method, 0, ""}, + {"(*Template).Funcs", Method, 0, ""}, + {"(*Template).Lookup", Method, 0, ""}, + {"(*Template).Name", Method, 0, ""}, + {"(*Template).New", Method, 0, ""}, + {"(*Template).Option", Method, 5, ""}, + {"(*Template).Parse", Method, 0, ""}, + {"(*Template).ParseFS", Method, 16, ""}, + {"(*Template).ParseFiles", Method, 0, ""}, + {"(*Template).ParseGlob", Method, 0, ""}, + {"(*Template).Templates", Method, 0, ""}, + {"CSS", Type, 0, ""}, + {"ErrAmbigContext", Const, 0, ""}, + {"ErrBadHTML", Const, 0, ""}, + {"ErrBranchEnd", Const, 0, ""}, + {"ErrEndContext", Const, 0, ""}, + {"ErrJSTemplate", Const, 21, ""}, + {"ErrNoSuchTemplate", Const, 0, ""}, + {"ErrOutputContext", Const, 0, ""}, + {"ErrPartialCharset", Const, 0, ""}, + {"ErrPartialEscape", Const, 0, ""}, + {"ErrPredefinedEscaper", Const, 9, ""}, + {"ErrRangeLoopReentry", Const, 0, ""}, + {"ErrSlashAmbig", Const, 0, ""}, + {"Error", Type, 0, ""}, + {"Error.Description", Field, 0, ""}, + {"Error.ErrorCode", Field, 0, ""}, + {"Error.Line", Field, 0, ""}, + {"Error.Name", Field, 0, ""}, + {"Error.Node", Field, 4, ""}, + {"ErrorCode", Type, 0, ""}, + {"FuncMap", Type, 0, ""}, + {"HTML", Type, 0, ""}, + {"HTMLAttr", Type, 0, ""}, + {"HTMLEscape", Func, 0, "func(w io.Writer, b []byte)"}, + {"HTMLEscapeString", Func, 0, "func(s string) string"}, + {"HTMLEscaper", Func, 0, "func(args ...any) string"}, + {"IsTrue", Func, 6, "func(val any) (truth bool, ok bool)"}, + {"JS", Type, 0, ""}, + {"JSEscape", Func, 0, "func(w io.Writer, b []byte)"}, + {"JSEscapeString", Func, 0, "func(s string) string"}, + {"JSEscaper", Func, 0, "func(args ...any) string"}, + {"JSStr", Type, 0, ""}, + {"Must", Func, 0, "func(t *Template, err error) *Template"}, + {"New", Func, 0, "func(name string) *Template"}, + {"OK", Const, 0, ""}, + {"ParseFS", Func, 16, "func(fs fs.FS, patterns ...string) (*Template, error)"}, + {"ParseFiles", Func, 0, "func(filenames ...string) (*Template, error)"}, + {"ParseGlob", Func, 0, "func(pattern string) (*Template, error)"}, + {"Srcset", Type, 10, ""}, + {"Template", Type, 0, ""}, + {"Template.Tree", Field, 2, ""}, + {"URL", Type, 0, ""}, + {"URLQueryEscaper", Func, 0, "func(args ...any) string"}, }, "image": { - {"(*Alpha).AlphaAt", Method, 4}, - {"(*Alpha).At", Method, 0}, - {"(*Alpha).Bounds", Method, 0}, - {"(*Alpha).ColorModel", Method, 0}, - {"(*Alpha).Opaque", Method, 0}, - {"(*Alpha).PixOffset", Method, 0}, - {"(*Alpha).RGBA64At", Method, 17}, - {"(*Alpha).Set", Method, 0}, - {"(*Alpha).SetAlpha", Method, 0}, - {"(*Alpha).SetRGBA64", Method, 17}, - {"(*Alpha).SubImage", Method, 0}, - {"(*Alpha16).Alpha16At", Method, 4}, - {"(*Alpha16).At", Method, 0}, - {"(*Alpha16).Bounds", Method, 0}, - {"(*Alpha16).ColorModel", Method, 0}, - {"(*Alpha16).Opaque", Method, 0}, - {"(*Alpha16).PixOffset", Method, 0}, - {"(*Alpha16).RGBA64At", Method, 17}, - {"(*Alpha16).Set", Method, 0}, - {"(*Alpha16).SetAlpha16", Method, 0}, - {"(*Alpha16).SetRGBA64", Method, 17}, - {"(*Alpha16).SubImage", Method, 0}, - {"(*CMYK).At", Method, 5}, - {"(*CMYK).Bounds", Method, 5}, - {"(*CMYK).CMYKAt", Method, 5}, - {"(*CMYK).ColorModel", Method, 5}, - {"(*CMYK).Opaque", Method, 5}, - {"(*CMYK).PixOffset", Method, 5}, - {"(*CMYK).RGBA64At", Method, 17}, - {"(*CMYK).Set", Method, 5}, - {"(*CMYK).SetCMYK", Method, 5}, - {"(*CMYK).SetRGBA64", Method, 17}, - {"(*CMYK).SubImage", Method, 5}, - {"(*Gray).At", Method, 0}, - {"(*Gray).Bounds", Method, 0}, - {"(*Gray).ColorModel", Method, 0}, - {"(*Gray).GrayAt", Method, 4}, - {"(*Gray).Opaque", Method, 0}, - {"(*Gray).PixOffset", Method, 0}, - {"(*Gray).RGBA64At", Method, 17}, - {"(*Gray).Set", Method, 0}, - {"(*Gray).SetGray", Method, 0}, - {"(*Gray).SetRGBA64", Method, 17}, - {"(*Gray).SubImage", Method, 0}, - {"(*Gray16).At", Method, 0}, - {"(*Gray16).Bounds", Method, 0}, - {"(*Gray16).ColorModel", Method, 0}, - {"(*Gray16).Gray16At", Method, 4}, - {"(*Gray16).Opaque", Method, 0}, - {"(*Gray16).PixOffset", Method, 0}, - {"(*Gray16).RGBA64At", Method, 17}, - {"(*Gray16).Set", Method, 0}, - {"(*Gray16).SetGray16", Method, 0}, - {"(*Gray16).SetRGBA64", Method, 17}, - {"(*Gray16).SubImage", Method, 0}, - {"(*NRGBA).At", Method, 0}, - {"(*NRGBA).Bounds", Method, 0}, - {"(*NRGBA).ColorModel", Method, 0}, - {"(*NRGBA).NRGBAAt", Method, 4}, - {"(*NRGBA).Opaque", Method, 0}, - {"(*NRGBA).PixOffset", Method, 0}, - {"(*NRGBA).RGBA64At", Method, 17}, - {"(*NRGBA).Set", Method, 0}, - {"(*NRGBA).SetNRGBA", Method, 0}, - {"(*NRGBA).SetRGBA64", Method, 17}, - {"(*NRGBA).SubImage", Method, 0}, - {"(*NRGBA64).At", Method, 0}, - {"(*NRGBA64).Bounds", Method, 0}, - {"(*NRGBA64).ColorModel", Method, 0}, - {"(*NRGBA64).NRGBA64At", Method, 4}, - {"(*NRGBA64).Opaque", Method, 0}, - {"(*NRGBA64).PixOffset", Method, 0}, - {"(*NRGBA64).RGBA64At", Method, 17}, - {"(*NRGBA64).Set", Method, 0}, - {"(*NRGBA64).SetNRGBA64", Method, 0}, - {"(*NRGBA64).SetRGBA64", Method, 17}, - {"(*NRGBA64).SubImage", Method, 0}, - {"(*NYCbCrA).AOffset", Method, 6}, - {"(*NYCbCrA).At", Method, 6}, - {"(*NYCbCrA).Bounds", Method, 6}, - {"(*NYCbCrA).COffset", Method, 6}, - {"(*NYCbCrA).ColorModel", Method, 6}, - {"(*NYCbCrA).NYCbCrAAt", Method, 6}, - {"(*NYCbCrA).Opaque", Method, 6}, - {"(*NYCbCrA).RGBA64At", Method, 17}, - {"(*NYCbCrA).SubImage", Method, 6}, - {"(*NYCbCrA).YCbCrAt", Method, 6}, - {"(*NYCbCrA).YOffset", Method, 6}, - {"(*Paletted).At", Method, 0}, - {"(*Paletted).Bounds", Method, 0}, - {"(*Paletted).ColorIndexAt", Method, 0}, - {"(*Paletted).ColorModel", Method, 0}, - {"(*Paletted).Opaque", Method, 0}, - {"(*Paletted).PixOffset", Method, 0}, - {"(*Paletted).RGBA64At", Method, 17}, - {"(*Paletted).Set", Method, 0}, - {"(*Paletted).SetColorIndex", Method, 0}, - {"(*Paletted).SetRGBA64", Method, 17}, - {"(*Paletted).SubImage", Method, 0}, - {"(*RGBA).At", Method, 0}, - {"(*RGBA).Bounds", Method, 0}, - {"(*RGBA).ColorModel", Method, 0}, - {"(*RGBA).Opaque", Method, 0}, - {"(*RGBA).PixOffset", Method, 0}, - {"(*RGBA).RGBA64At", Method, 17}, - {"(*RGBA).RGBAAt", Method, 4}, - {"(*RGBA).Set", Method, 0}, - {"(*RGBA).SetRGBA", Method, 0}, - {"(*RGBA).SetRGBA64", Method, 17}, - {"(*RGBA).SubImage", Method, 0}, - {"(*RGBA64).At", Method, 0}, - {"(*RGBA64).Bounds", Method, 0}, - {"(*RGBA64).ColorModel", Method, 0}, - {"(*RGBA64).Opaque", Method, 0}, - {"(*RGBA64).PixOffset", Method, 0}, - {"(*RGBA64).RGBA64At", Method, 4}, - {"(*RGBA64).Set", Method, 0}, - {"(*RGBA64).SetRGBA64", Method, 0}, - {"(*RGBA64).SubImage", Method, 0}, - {"(*Uniform).At", Method, 0}, - {"(*Uniform).Bounds", Method, 0}, - {"(*Uniform).ColorModel", Method, 0}, - {"(*Uniform).Convert", Method, 0}, - {"(*Uniform).Opaque", Method, 0}, - {"(*Uniform).RGBA", Method, 0}, - {"(*Uniform).RGBA64At", Method, 17}, - {"(*YCbCr).At", Method, 0}, - {"(*YCbCr).Bounds", Method, 0}, - {"(*YCbCr).COffset", Method, 0}, - {"(*YCbCr).ColorModel", Method, 0}, - {"(*YCbCr).Opaque", Method, 0}, - {"(*YCbCr).RGBA64At", Method, 17}, - {"(*YCbCr).SubImage", Method, 0}, - {"(*YCbCr).YCbCrAt", Method, 4}, - {"(*YCbCr).YOffset", Method, 0}, - {"(Point).Add", Method, 0}, - {"(Point).Div", Method, 0}, - {"(Point).Eq", Method, 0}, - {"(Point).In", Method, 0}, - {"(Point).Mod", Method, 0}, - {"(Point).Mul", Method, 0}, - {"(Point).String", Method, 0}, - {"(Point).Sub", Method, 0}, - {"(Rectangle).Add", Method, 0}, - {"(Rectangle).At", Method, 5}, - {"(Rectangle).Bounds", Method, 5}, - {"(Rectangle).Canon", Method, 0}, - {"(Rectangle).ColorModel", Method, 5}, - {"(Rectangle).Dx", Method, 0}, - {"(Rectangle).Dy", Method, 0}, - {"(Rectangle).Empty", Method, 0}, - {"(Rectangle).Eq", Method, 0}, - {"(Rectangle).In", Method, 0}, - {"(Rectangle).Inset", Method, 0}, - {"(Rectangle).Intersect", Method, 0}, - {"(Rectangle).Overlaps", Method, 0}, - {"(Rectangle).RGBA64At", Method, 17}, - {"(Rectangle).Size", Method, 0}, - {"(Rectangle).String", Method, 0}, - {"(Rectangle).Sub", Method, 0}, - {"(Rectangle).Union", Method, 0}, - {"(YCbCrSubsampleRatio).String", Method, 0}, - {"Alpha", Type, 0}, - {"Alpha.Pix", Field, 0}, - {"Alpha.Rect", Field, 0}, - {"Alpha.Stride", Field, 0}, - {"Alpha16", Type, 0}, - {"Alpha16.Pix", Field, 0}, - {"Alpha16.Rect", Field, 0}, - {"Alpha16.Stride", Field, 0}, - {"Black", Var, 0}, - {"CMYK", Type, 5}, - {"CMYK.Pix", Field, 5}, - {"CMYK.Rect", Field, 5}, - {"CMYK.Stride", Field, 5}, - {"Config", Type, 0}, - {"Config.ColorModel", Field, 0}, - {"Config.Height", Field, 0}, - {"Config.Width", Field, 0}, - {"Decode", Func, 0}, - {"DecodeConfig", Func, 0}, - {"ErrFormat", Var, 0}, - {"Gray", Type, 0}, - {"Gray.Pix", Field, 0}, - {"Gray.Rect", Field, 0}, - {"Gray.Stride", Field, 0}, - {"Gray16", Type, 0}, - {"Gray16.Pix", Field, 0}, - {"Gray16.Rect", Field, 0}, - {"Gray16.Stride", Field, 0}, - {"Image", Type, 0}, - {"NRGBA", Type, 0}, - {"NRGBA.Pix", Field, 0}, - {"NRGBA.Rect", Field, 0}, - {"NRGBA.Stride", Field, 0}, - {"NRGBA64", Type, 0}, - {"NRGBA64.Pix", Field, 0}, - {"NRGBA64.Rect", Field, 0}, - {"NRGBA64.Stride", Field, 0}, - {"NYCbCrA", Type, 6}, - {"NYCbCrA.A", Field, 6}, - {"NYCbCrA.AStride", Field, 6}, - {"NYCbCrA.YCbCr", Field, 6}, - {"NewAlpha", Func, 0}, - {"NewAlpha16", Func, 0}, - {"NewCMYK", Func, 5}, - {"NewGray", Func, 0}, - {"NewGray16", Func, 0}, - {"NewNRGBA", Func, 0}, - {"NewNRGBA64", Func, 0}, - {"NewNYCbCrA", Func, 6}, - {"NewPaletted", Func, 0}, - {"NewRGBA", Func, 0}, - {"NewRGBA64", Func, 0}, - {"NewUniform", Func, 0}, - {"NewYCbCr", Func, 0}, - {"Opaque", Var, 0}, - {"Paletted", Type, 0}, - {"Paletted.Palette", Field, 0}, - {"Paletted.Pix", Field, 0}, - {"Paletted.Rect", Field, 0}, - {"Paletted.Stride", Field, 0}, - {"PalettedImage", Type, 0}, - {"Point", Type, 0}, - {"Point.X", Field, 0}, - {"Point.Y", Field, 0}, - {"Pt", Func, 0}, - {"RGBA", Type, 0}, - {"RGBA.Pix", Field, 0}, - {"RGBA.Rect", Field, 0}, - {"RGBA.Stride", Field, 0}, - {"RGBA64", Type, 0}, - {"RGBA64.Pix", Field, 0}, - {"RGBA64.Rect", Field, 0}, - {"RGBA64.Stride", Field, 0}, - {"RGBA64Image", Type, 17}, - {"Rect", Func, 0}, - {"Rectangle", Type, 0}, - {"Rectangle.Max", Field, 0}, - {"Rectangle.Min", Field, 0}, - {"RegisterFormat", Func, 0}, - {"Transparent", Var, 0}, - {"Uniform", Type, 0}, - {"Uniform.C", Field, 0}, - {"White", Var, 0}, - {"YCbCr", Type, 0}, - {"YCbCr.CStride", Field, 0}, - {"YCbCr.Cb", Field, 0}, - {"YCbCr.Cr", Field, 0}, - {"YCbCr.Rect", Field, 0}, - {"YCbCr.SubsampleRatio", Field, 0}, - {"YCbCr.Y", Field, 0}, - {"YCbCr.YStride", Field, 0}, - {"YCbCrSubsampleRatio", Type, 0}, - {"YCbCrSubsampleRatio410", Const, 5}, - {"YCbCrSubsampleRatio411", Const, 5}, - {"YCbCrSubsampleRatio420", Const, 0}, - {"YCbCrSubsampleRatio422", Const, 0}, - {"YCbCrSubsampleRatio440", Const, 1}, - {"YCbCrSubsampleRatio444", Const, 0}, - {"ZP", Var, 0}, - {"ZR", Var, 0}, + {"(*Alpha).AlphaAt", Method, 4, ""}, + {"(*Alpha).At", Method, 0, ""}, + {"(*Alpha).Bounds", Method, 0, ""}, + {"(*Alpha).ColorModel", Method, 0, ""}, + {"(*Alpha).Opaque", Method, 0, ""}, + {"(*Alpha).PixOffset", Method, 0, ""}, + {"(*Alpha).RGBA64At", Method, 17, ""}, + {"(*Alpha).Set", Method, 0, ""}, + {"(*Alpha).SetAlpha", Method, 0, ""}, + {"(*Alpha).SetRGBA64", Method, 17, ""}, + {"(*Alpha).SubImage", Method, 0, ""}, + {"(*Alpha16).Alpha16At", Method, 4, ""}, + {"(*Alpha16).At", Method, 0, ""}, + {"(*Alpha16).Bounds", Method, 0, ""}, + {"(*Alpha16).ColorModel", Method, 0, ""}, + {"(*Alpha16).Opaque", Method, 0, ""}, + {"(*Alpha16).PixOffset", Method, 0, ""}, + {"(*Alpha16).RGBA64At", Method, 17, ""}, + {"(*Alpha16).Set", Method, 0, ""}, + {"(*Alpha16).SetAlpha16", Method, 0, ""}, + {"(*Alpha16).SetRGBA64", Method, 17, ""}, + {"(*Alpha16).SubImage", Method, 0, ""}, + {"(*CMYK).At", Method, 5, ""}, + {"(*CMYK).Bounds", Method, 5, ""}, + {"(*CMYK).CMYKAt", Method, 5, ""}, + {"(*CMYK).ColorModel", Method, 5, ""}, + {"(*CMYK).Opaque", Method, 5, ""}, + {"(*CMYK).PixOffset", Method, 5, ""}, + {"(*CMYK).RGBA64At", Method, 17, ""}, + {"(*CMYK).Set", Method, 5, ""}, + {"(*CMYK).SetCMYK", Method, 5, ""}, + {"(*CMYK).SetRGBA64", Method, 17, ""}, + {"(*CMYK).SubImage", Method, 5, ""}, + {"(*Gray).At", Method, 0, ""}, + {"(*Gray).Bounds", Method, 0, ""}, + {"(*Gray).ColorModel", Method, 0, ""}, + {"(*Gray).GrayAt", Method, 4, ""}, + {"(*Gray).Opaque", Method, 0, ""}, + {"(*Gray).PixOffset", Method, 0, ""}, + {"(*Gray).RGBA64At", Method, 17, ""}, + {"(*Gray).Set", Method, 0, ""}, + {"(*Gray).SetGray", Method, 0, ""}, + {"(*Gray).SetRGBA64", Method, 17, ""}, + {"(*Gray).SubImage", Method, 0, ""}, + {"(*Gray16).At", Method, 0, ""}, + {"(*Gray16).Bounds", Method, 0, ""}, + {"(*Gray16).ColorModel", Method, 0, ""}, + {"(*Gray16).Gray16At", Method, 4, ""}, + {"(*Gray16).Opaque", Method, 0, ""}, + {"(*Gray16).PixOffset", Method, 0, ""}, + {"(*Gray16).RGBA64At", Method, 17, ""}, + {"(*Gray16).Set", Method, 0, ""}, + {"(*Gray16).SetGray16", Method, 0, ""}, + {"(*Gray16).SetRGBA64", Method, 17, ""}, + {"(*Gray16).SubImage", Method, 0, ""}, + {"(*NRGBA).At", Method, 0, ""}, + {"(*NRGBA).Bounds", Method, 0, ""}, + {"(*NRGBA).ColorModel", Method, 0, ""}, + {"(*NRGBA).NRGBAAt", Method, 4, ""}, + {"(*NRGBA).Opaque", Method, 0, ""}, + {"(*NRGBA).PixOffset", Method, 0, ""}, + {"(*NRGBA).RGBA64At", Method, 17, ""}, + {"(*NRGBA).Set", Method, 0, ""}, + {"(*NRGBA).SetNRGBA", Method, 0, ""}, + {"(*NRGBA).SetRGBA64", Method, 17, ""}, + {"(*NRGBA).SubImage", Method, 0, ""}, + {"(*NRGBA64).At", Method, 0, ""}, + {"(*NRGBA64).Bounds", Method, 0, ""}, + {"(*NRGBA64).ColorModel", Method, 0, ""}, + {"(*NRGBA64).NRGBA64At", Method, 4, ""}, + {"(*NRGBA64).Opaque", Method, 0, ""}, + {"(*NRGBA64).PixOffset", Method, 0, ""}, + {"(*NRGBA64).RGBA64At", Method, 17, ""}, + {"(*NRGBA64).Set", Method, 0, ""}, + {"(*NRGBA64).SetNRGBA64", Method, 0, ""}, + {"(*NRGBA64).SetRGBA64", Method, 17, ""}, + {"(*NRGBA64).SubImage", Method, 0, ""}, + {"(*NYCbCrA).AOffset", Method, 6, ""}, + {"(*NYCbCrA).At", Method, 6, ""}, + {"(*NYCbCrA).Bounds", Method, 6, ""}, + {"(*NYCbCrA).COffset", Method, 6, ""}, + {"(*NYCbCrA).ColorModel", Method, 6, ""}, + {"(*NYCbCrA).NYCbCrAAt", Method, 6, ""}, + {"(*NYCbCrA).Opaque", Method, 6, ""}, + {"(*NYCbCrA).RGBA64At", Method, 17, ""}, + {"(*NYCbCrA).SubImage", Method, 6, ""}, + {"(*NYCbCrA).YCbCrAt", Method, 6, ""}, + {"(*NYCbCrA).YOffset", Method, 6, ""}, + {"(*Paletted).At", Method, 0, ""}, + {"(*Paletted).Bounds", Method, 0, ""}, + {"(*Paletted).ColorIndexAt", Method, 0, ""}, + {"(*Paletted).ColorModel", Method, 0, ""}, + {"(*Paletted).Opaque", Method, 0, ""}, + {"(*Paletted).PixOffset", Method, 0, ""}, + {"(*Paletted).RGBA64At", Method, 17, ""}, + {"(*Paletted).Set", Method, 0, ""}, + {"(*Paletted).SetColorIndex", Method, 0, ""}, + {"(*Paletted).SetRGBA64", Method, 17, ""}, + {"(*Paletted).SubImage", Method, 0, ""}, + {"(*RGBA).At", Method, 0, ""}, + {"(*RGBA).Bounds", Method, 0, ""}, + {"(*RGBA).ColorModel", Method, 0, ""}, + {"(*RGBA).Opaque", Method, 0, ""}, + {"(*RGBA).PixOffset", Method, 0, ""}, + {"(*RGBA).RGBA64At", Method, 17, ""}, + {"(*RGBA).RGBAAt", Method, 4, ""}, + {"(*RGBA).Set", Method, 0, ""}, + {"(*RGBA).SetRGBA", Method, 0, ""}, + {"(*RGBA).SetRGBA64", Method, 17, ""}, + {"(*RGBA).SubImage", Method, 0, ""}, + {"(*RGBA64).At", Method, 0, ""}, + {"(*RGBA64).Bounds", Method, 0, ""}, + {"(*RGBA64).ColorModel", Method, 0, ""}, + {"(*RGBA64).Opaque", Method, 0, ""}, + {"(*RGBA64).PixOffset", Method, 0, ""}, + {"(*RGBA64).RGBA64At", Method, 4, ""}, + {"(*RGBA64).Set", Method, 0, ""}, + {"(*RGBA64).SetRGBA64", Method, 0, ""}, + {"(*RGBA64).SubImage", Method, 0, ""}, + {"(*Uniform).At", Method, 0, ""}, + {"(*Uniform).Bounds", Method, 0, ""}, + {"(*Uniform).ColorModel", Method, 0, ""}, + {"(*Uniform).Convert", Method, 0, ""}, + {"(*Uniform).Opaque", Method, 0, ""}, + {"(*Uniform).RGBA", Method, 0, ""}, + {"(*Uniform).RGBA64At", Method, 17, ""}, + {"(*YCbCr).At", Method, 0, ""}, + {"(*YCbCr).Bounds", Method, 0, ""}, + {"(*YCbCr).COffset", Method, 0, ""}, + {"(*YCbCr).ColorModel", Method, 0, ""}, + {"(*YCbCr).Opaque", Method, 0, ""}, + {"(*YCbCr).RGBA64At", Method, 17, ""}, + {"(*YCbCr).SubImage", Method, 0, ""}, + {"(*YCbCr).YCbCrAt", Method, 4, ""}, + {"(*YCbCr).YOffset", Method, 0, ""}, + {"(Point).Add", Method, 0, ""}, + {"(Point).Div", Method, 0, ""}, + {"(Point).Eq", Method, 0, ""}, + {"(Point).In", Method, 0, ""}, + {"(Point).Mod", Method, 0, ""}, + {"(Point).Mul", Method, 0, ""}, + {"(Point).String", Method, 0, ""}, + {"(Point).Sub", Method, 0, ""}, + {"(Rectangle).Add", Method, 0, ""}, + {"(Rectangle).At", Method, 5, ""}, + {"(Rectangle).Bounds", Method, 5, ""}, + {"(Rectangle).Canon", Method, 0, ""}, + {"(Rectangle).ColorModel", Method, 5, ""}, + {"(Rectangle).Dx", Method, 0, ""}, + {"(Rectangle).Dy", Method, 0, ""}, + {"(Rectangle).Empty", Method, 0, ""}, + {"(Rectangle).Eq", Method, 0, ""}, + {"(Rectangle).In", Method, 0, ""}, + {"(Rectangle).Inset", Method, 0, ""}, + {"(Rectangle).Intersect", Method, 0, ""}, + {"(Rectangle).Overlaps", Method, 0, ""}, + {"(Rectangle).RGBA64At", Method, 17, ""}, + {"(Rectangle).Size", Method, 0, ""}, + {"(Rectangle).String", Method, 0, ""}, + {"(Rectangle).Sub", Method, 0, ""}, + {"(Rectangle).Union", Method, 0, ""}, + {"(YCbCrSubsampleRatio).String", Method, 0, ""}, + {"Alpha", Type, 0, ""}, + {"Alpha.Pix", Field, 0, ""}, + {"Alpha.Rect", Field, 0, ""}, + {"Alpha.Stride", Field, 0, ""}, + {"Alpha16", Type, 0, ""}, + {"Alpha16.Pix", Field, 0, ""}, + {"Alpha16.Rect", Field, 0, ""}, + {"Alpha16.Stride", Field, 0, ""}, + {"Black", Var, 0, ""}, + {"CMYK", Type, 5, ""}, + {"CMYK.Pix", Field, 5, ""}, + {"CMYK.Rect", Field, 5, ""}, + {"CMYK.Stride", Field, 5, ""}, + {"Config", Type, 0, ""}, + {"Config.ColorModel", Field, 0, ""}, + {"Config.Height", Field, 0, ""}, + {"Config.Width", Field, 0, ""}, + {"Decode", Func, 0, "func(r io.Reader) (Image, string, error)"}, + {"DecodeConfig", Func, 0, "func(r io.Reader) (Config, string, error)"}, + {"ErrFormat", Var, 0, ""}, + {"Gray", Type, 0, ""}, + {"Gray.Pix", Field, 0, ""}, + {"Gray.Rect", Field, 0, ""}, + {"Gray.Stride", Field, 0, ""}, + {"Gray16", Type, 0, ""}, + {"Gray16.Pix", Field, 0, ""}, + {"Gray16.Rect", Field, 0, ""}, + {"Gray16.Stride", Field, 0, ""}, + {"Image", Type, 0, ""}, + {"NRGBA", Type, 0, ""}, + {"NRGBA.Pix", Field, 0, ""}, + {"NRGBA.Rect", Field, 0, ""}, + {"NRGBA.Stride", Field, 0, ""}, + {"NRGBA64", Type, 0, ""}, + {"NRGBA64.Pix", Field, 0, ""}, + {"NRGBA64.Rect", Field, 0, ""}, + {"NRGBA64.Stride", Field, 0, ""}, + {"NYCbCrA", Type, 6, ""}, + {"NYCbCrA.A", Field, 6, ""}, + {"NYCbCrA.AStride", Field, 6, ""}, + {"NYCbCrA.YCbCr", Field, 6, ""}, + {"NewAlpha", Func, 0, "func(r Rectangle) *Alpha"}, + {"NewAlpha16", Func, 0, "func(r Rectangle) *Alpha16"}, + {"NewCMYK", Func, 5, "func(r Rectangle) *CMYK"}, + {"NewGray", Func, 0, "func(r Rectangle) *Gray"}, + {"NewGray16", Func, 0, "func(r Rectangle) *Gray16"}, + {"NewNRGBA", Func, 0, "func(r Rectangle) *NRGBA"}, + {"NewNRGBA64", Func, 0, "func(r Rectangle) *NRGBA64"}, + {"NewNYCbCrA", Func, 6, "func(r Rectangle, subsampleRatio YCbCrSubsampleRatio) *NYCbCrA"}, + {"NewPaletted", Func, 0, "func(r Rectangle, p color.Palette) *Paletted"}, + {"NewRGBA", Func, 0, "func(r Rectangle) *RGBA"}, + {"NewRGBA64", Func, 0, "func(r Rectangle) *RGBA64"}, + {"NewUniform", Func, 0, "func(c color.Color) *Uniform"}, + {"NewYCbCr", Func, 0, "func(r Rectangle, subsampleRatio YCbCrSubsampleRatio) *YCbCr"}, + {"Opaque", Var, 0, ""}, + {"Paletted", Type, 0, ""}, + {"Paletted.Palette", Field, 0, ""}, + {"Paletted.Pix", Field, 0, ""}, + {"Paletted.Rect", Field, 0, ""}, + {"Paletted.Stride", Field, 0, ""}, + {"PalettedImage", Type, 0, ""}, + {"Point", Type, 0, ""}, + {"Point.X", Field, 0, ""}, + {"Point.Y", Field, 0, ""}, + {"Pt", Func, 0, "func(X int, Y int) Point"}, + {"RGBA", Type, 0, ""}, + {"RGBA.Pix", Field, 0, ""}, + {"RGBA.Rect", Field, 0, ""}, + {"RGBA.Stride", Field, 0, ""}, + {"RGBA64", Type, 0, ""}, + {"RGBA64.Pix", Field, 0, ""}, + {"RGBA64.Rect", Field, 0, ""}, + {"RGBA64.Stride", Field, 0, ""}, + {"RGBA64Image", Type, 17, ""}, + {"Rect", Func, 0, "func(x0 int, y0 int, x1 int, y1 int) Rectangle"}, + {"Rectangle", Type, 0, ""}, + {"Rectangle.Max", Field, 0, ""}, + {"Rectangle.Min", Field, 0, ""}, + {"RegisterFormat", Func, 0, "func(name string, magic string, decode func(io.Reader) (Image, error), decodeConfig func(io.Reader) (Config, error))"}, + {"Transparent", Var, 0, ""}, + {"Uniform", Type, 0, ""}, + {"Uniform.C", Field, 0, ""}, + {"White", Var, 0, ""}, + {"YCbCr", Type, 0, ""}, + {"YCbCr.CStride", Field, 0, ""}, + {"YCbCr.Cb", Field, 0, ""}, + {"YCbCr.Cr", Field, 0, ""}, + {"YCbCr.Rect", Field, 0, ""}, + {"YCbCr.SubsampleRatio", Field, 0, ""}, + {"YCbCr.Y", Field, 0, ""}, + {"YCbCr.YStride", Field, 0, ""}, + {"YCbCrSubsampleRatio", Type, 0, ""}, + {"YCbCrSubsampleRatio410", Const, 5, ""}, + {"YCbCrSubsampleRatio411", Const, 5, ""}, + {"YCbCrSubsampleRatio420", Const, 0, ""}, + {"YCbCrSubsampleRatio422", Const, 0, ""}, + {"YCbCrSubsampleRatio440", Const, 1, ""}, + {"YCbCrSubsampleRatio444", Const, 0, ""}, + {"ZP", Var, 0, ""}, + {"ZR", Var, 0, ""}, }, "image/color": { - {"(Alpha).RGBA", Method, 0}, - {"(Alpha16).RGBA", Method, 0}, - {"(CMYK).RGBA", Method, 5}, - {"(Gray).RGBA", Method, 0}, - {"(Gray16).RGBA", Method, 0}, - {"(NRGBA).RGBA", Method, 0}, - {"(NRGBA64).RGBA", Method, 0}, - {"(NYCbCrA).RGBA", Method, 6}, - {"(Palette).Convert", Method, 0}, - {"(Palette).Index", Method, 0}, - {"(RGBA).RGBA", Method, 0}, - {"(RGBA64).RGBA", Method, 0}, - {"(YCbCr).RGBA", Method, 0}, - {"Alpha", Type, 0}, - {"Alpha.A", Field, 0}, - {"Alpha16", Type, 0}, - {"Alpha16.A", Field, 0}, - {"Alpha16Model", Var, 0}, - {"AlphaModel", Var, 0}, - {"Black", Var, 0}, - {"CMYK", Type, 5}, - {"CMYK.C", Field, 5}, - {"CMYK.K", Field, 5}, - {"CMYK.M", Field, 5}, - {"CMYK.Y", Field, 5}, - {"CMYKModel", Var, 5}, - {"CMYKToRGB", Func, 5}, - {"Color", Type, 0}, - {"Gray", Type, 0}, - {"Gray.Y", Field, 0}, - {"Gray16", Type, 0}, - {"Gray16.Y", Field, 0}, - {"Gray16Model", Var, 0}, - {"GrayModel", Var, 0}, - {"Model", Type, 0}, - {"ModelFunc", Func, 0}, - {"NRGBA", Type, 0}, - {"NRGBA.A", Field, 0}, - {"NRGBA.B", Field, 0}, - {"NRGBA.G", Field, 0}, - {"NRGBA.R", Field, 0}, - {"NRGBA64", Type, 0}, - {"NRGBA64.A", Field, 0}, - {"NRGBA64.B", Field, 0}, - {"NRGBA64.G", Field, 0}, - {"NRGBA64.R", Field, 0}, - {"NRGBA64Model", Var, 0}, - {"NRGBAModel", Var, 0}, - {"NYCbCrA", Type, 6}, - {"NYCbCrA.A", Field, 6}, - {"NYCbCrA.YCbCr", Field, 6}, - {"NYCbCrAModel", Var, 6}, - {"Opaque", Var, 0}, - {"Palette", Type, 0}, - {"RGBA", Type, 0}, - {"RGBA.A", Field, 0}, - {"RGBA.B", Field, 0}, - {"RGBA.G", Field, 0}, - {"RGBA.R", Field, 0}, - {"RGBA64", Type, 0}, - {"RGBA64.A", Field, 0}, - {"RGBA64.B", Field, 0}, - {"RGBA64.G", Field, 0}, - {"RGBA64.R", Field, 0}, - {"RGBA64Model", Var, 0}, - {"RGBAModel", Var, 0}, - {"RGBToCMYK", Func, 5}, - {"RGBToYCbCr", Func, 0}, - {"Transparent", Var, 0}, - {"White", Var, 0}, - {"YCbCr", Type, 0}, - {"YCbCr.Cb", Field, 0}, - {"YCbCr.Cr", Field, 0}, - {"YCbCr.Y", Field, 0}, - {"YCbCrModel", Var, 0}, - {"YCbCrToRGB", Func, 0}, + {"(Alpha).RGBA", Method, 0, ""}, + {"(Alpha16).RGBA", Method, 0, ""}, + {"(CMYK).RGBA", Method, 5, ""}, + {"(Gray).RGBA", Method, 0, ""}, + {"(Gray16).RGBA", Method, 0, ""}, + {"(NRGBA).RGBA", Method, 0, ""}, + {"(NRGBA64).RGBA", Method, 0, ""}, + {"(NYCbCrA).RGBA", Method, 6, ""}, + {"(Palette).Convert", Method, 0, ""}, + {"(Palette).Index", Method, 0, ""}, + {"(RGBA).RGBA", Method, 0, ""}, + {"(RGBA64).RGBA", Method, 0, ""}, + {"(YCbCr).RGBA", Method, 0, ""}, + {"Alpha", Type, 0, ""}, + {"Alpha.A", Field, 0, ""}, + {"Alpha16", Type, 0, ""}, + {"Alpha16.A", Field, 0, ""}, + {"Alpha16Model", Var, 0, ""}, + {"AlphaModel", Var, 0, ""}, + {"Black", Var, 0, ""}, + {"CMYK", Type, 5, ""}, + {"CMYK.C", Field, 5, ""}, + {"CMYK.K", Field, 5, ""}, + {"CMYK.M", Field, 5, ""}, + {"CMYK.Y", Field, 5, ""}, + {"CMYKModel", Var, 5, ""}, + {"CMYKToRGB", Func, 5, "func(c uint8, m uint8, y uint8, k uint8) (uint8, uint8, uint8)"}, + {"Color", Type, 0, ""}, + {"Gray", Type, 0, ""}, + {"Gray.Y", Field, 0, ""}, + {"Gray16", Type, 0, ""}, + {"Gray16.Y", Field, 0, ""}, + {"Gray16Model", Var, 0, ""}, + {"GrayModel", Var, 0, ""}, + {"Model", Type, 0, ""}, + {"ModelFunc", Func, 0, "func(f func(Color) Color) Model"}, + {"NRGBA", Type, 0, ""}, + {"NRGBA.A", Field, 0, ""}, + {"NRGBA.B", Field, 0, ""}, + {"NRGBA.G", Field, 0, ""}, + {"NRGBA.R", Field, 0, ""}, + {"NRGBA64", Type, 0, ""}, + {"NRGBA64.A", Field, 0, ""}, + {"NRGBA64.B", Field, 0, ""}, + {"NRGBA64.G", Field, 0, ""}, + {"NRGBA64.R", Field, 0, ""}, + {"NRGBA64Model", Var, 0, ""}, + {"NRGBAModel", Var, 0, ""}, + {"NYCbCrA", Type, 6, ""}, + {"NYCbCrA.A", Field, 6, ""}, + {"NYCbCrA.YCbCr", Field, 6, ""}, + {"NYCbCrAModel", Var, 6, ""}, + {"Opaque", Var, 0, ""}, + {"Palette", Type, 0, ""}, + {"RGBA", Type, 0, ""}, + {"RGBA.A", Field, 0, ""}, + {"RGBA.B", Field, 0, ""}, + {"RGBA.G", Field, 0, ""}, + {"RGBA.R", Field, 0, ""}, + {"RGBA64", Type, 0, ""}, + {"RGBA64.A", Field, 0, ""}, + {"RGBA64.B", Field, 0, ""}, + {"RGBA64.G", Field, 0, ""}, + {"RGBA64.R", Field, 0, ""}, + {"RGBA64Model", Var, 0, ""}, + {"RGBAModel", Var, 0, ""}, + {"RGBToCMYK", Func, 5, "func(r uint8, g uint8, b uint8) (uint8, uint8, uint8, uint8)"}, + {"RGBToYCbCr", Func, 0, "func(r uint8, g uint8, b uint8) (uint8, uint8, uint8)"}, + {"Transparent", Var, 0, ""}, + {"White", Var, 0, ""}, + {"YCbCr", Type, 0, ""}, + {"YCbCr.Cb", Field, 0, ""}, + {"YCbCr.Cr", Field, 0, ""}, + {"YCbCr.Y", Field, 0, ""}, + {"YCbCrModel", Var, 0, ""}, + {"YCbCrToRGB", Func, 0, "func(y uint8, cb uint8, cr uint8) (uint8, uint8, uint8)"}, }, "image/color/palette": { - {"Plan9", Var, 2}, - {"WebSafe", Var, 2}, + {"Plan9", Var, 2, ""}, + {"WebSafe", Var, 2, ""}, }, "image/draw": { - {"(Op).Draw", Method, 2}, - {"Draw", Func, 0}, - {"DrawMask", Func, 0}, - {"Drawer", Type, 2}, - {"FloydSteinberg", Var, 2}, - {"Image", Type, 0}, - {"Op", Type, 0}, - {"Over", Const, 0}, - {"Quantizer", Type, 2}, - {"RGBA64Image", Type, 17}, - {"Src", Const, 0}, + {"(Op).Draw", Method, 2, ""}, + {"Draw", Func, 0, "func(dst Image, r image.Rectangle, src image.Image, sp image.Point, op Op)"}, + {"DrawMask", Func, 0, "func(dst Image, r image.Rectangle, src image.Image, sp image.Point, mask image.Image, mp image.Point, op Op)"}, + {"Drawer", Type, 2, ""}, + {"FloydSteinberg", Var, 2, ""}, + {"Image", Type, 0, ""}, + {"Op", Type, 0, ""}, + {"Over", Const, 0, ""}, + {"Quantizer", Type, 2, ""}, + {"RGBA64Image", Type, 17, ""}, + {"Src", Const, 0, ""}, }, "image/gif": { - {"Decode", Func, 0}, - {"DecodeAll", Func, 0}, - {"DecodeConfig", Func, 0}, - {"DisposalBackground", Const, 5}, - {"DisposalNone", Const, 5}, - {"DisposalPrevious", Const, 5}, - {"Encode", Func, 2}, - {"EncodeAll", Func, 2}, - {"GIF", Type, 0}, - {"GIF.BackgroundIndex", Field, 5}, - {"GIF.Config", Field, 5}, - {"GIF.Delay", Field, 0}, - {"GIF.Disposal", Field, 5}, - {"GIF.Image", Field, 0}, - {"GIF.LoopCount", Field, 0}, - {"Options", Type, 2}, - {"Options.Drawer", Field, 2}, - {"Options.NumColors", Field, 2}, - {"Options.Quantizer", Field, 2}, + {"Decode", Func, 0, "func(r io.Reader) (image.Image, error)"}, + {"DecodeAll", Func, 0, "func(r io.Reader) (*GIF, error)"}, + {"DecodeConfig", Func, 0, "func(r io.Reader) (image.Config, error)"}, + {"DisposalBackground", Const, 5, ""}, + {"DisposalNone", Const, 5, ""}, + {"DisposalPrevious", Const, 5, ""}, + {"Encode", Func, 2, "func(w io.Writer, m image.Image, o *Options) error"}, + {"EncodeAll", Func, 2, "func(w io.Writer, g *GIF) error"}, + {"GIF", Type, 0, ""}, + {"GIF.BackgroundIndex", Field, 5, ""}, + {"GIF.Config", Field, 5, ""}, + {"GIF.Delay", Field, 0, ""}, + {"GIF.Disposal", Field, 5, ""}, + {"GIF.Image", Field, 0, ""}, + {"GIF.LoopCount", Field, 0, ""}, + {"Options", Type, 2, ""}, + {"Options.Drawer", Field, 2, ""}, + {"Options.NumColors", Field, 2, ""}, + {"Options.Quantizer", Field, 2, ""}, }, "image/jpeg": { - {"(FormatError).Error", Method, 0}, - {"(UnsupportedError).Error", Method, 0}, - {"Decode", Func, 0}, - {"DecodeConfig", Func, 0}, - {"DefaultQuality", Const, 0}, - {"Encode", Func, 0}, - {"FormatError", Type, 0}, - {"Options", Type, 0}, - {"Options.Quality", Field, 0}, - {"Reader", Type, 0}, - {"UnsupportedError", Type, 0}, + {"(FormatError).Error", Method, 0, ""}, + {"(UnsupportedError).Error", Method, 0, ""}, + {"Decode", Func, 0, "func(r io.Reader) (image.Image, error)"}, + {"DecodeConfig", Func, 0, "func(r io.Reader) (image.Config, error)"}, + {"DefaultQuality", Const, 0, ""}, + {"Encode", Func, 0, "func(w io.Writer, m image.Image, o *Options) error"}, + {"FormatError", Type, 0, ""}, + {"Options", Type, 0, ""}, + {"Options.Quality", Field, 0, ""}, + {"Reader", Type, 0, ""}, + {"UnsupportedError", Type, 0, ""}, }, "image/png": { - {"(*Encoder).Encode", Method, 4}, - {"(FormatError).Error", Method, 0}, - {"(UnsupportedError).Error", Method, 0}, - {"BestCompression", Const, 4}, - {"BestSpeed", Const, 4}, - {"CompressionLevel", Type, 4}, - {"Decode", Func, 0}, - {"DecodeConfig", Func, 0}, - {"DefaultCompression", Const, 4}, - {"Encode", Func, 0}, - {"Encoder", Type, 4}, - {"Encoder.BufferPool", Field, 9}, - {"Encoder.CompressionLevel", Field, 4}, - {"EncoderBuffer", Type, 9}, - {"EncoderBufferPool", Type, 9}, - {"FormatError", Type, 0}, - {"NoCompression", Const, 4}, - {"UnsupportedError", Type, 0}, + {"(*Encoder).Encode", Method, 4, ""}, + {"(FormatError).Error", Method, 0, ""}, + {"(UnsupportedError).Error", Method, 0, ""}, + {"BestCompression", Const, 4, ""}, + {"BestSpeed", Const, 4, ""}, + {"CompressionLevel", Type, 4, ""}, + {"Decode", Func, 0, "func(r io.Reader) (image.Image, error)"}, + {"DecodeConfig", Func, 0, "func(r io.Reader) (image.Config, error)"}, + {"DefaultCompression", Const, 4, ""}, + {"Encode", Func, 0, "func(w io.Writer, m image.Image) error"}, + {"Encoder", Type, 4, ""}, + {"Encoder.BufferPool", Field, 9, ""}, + {"Encoder.CompressionLevel", Field, 4, ""}, + {"EncoderBuffer", Type, 9, ""}, + {"EncoderBufferPool", Type, 9, ""}, + {"FormatError", Type, 0, ""}, + {"NoCompression", Const, 4, ""}, + {"UnsupportedError", Type, 0, ""}, }, "index/suffixarray": { - {"(*Index).Bytes", Method, 0}, - {"(*Index).FindAllIndex", Method, 0}, - {"(*Index).Lookup", Method, 0}, - {"(*Index).Read", Method, 0}, - {"(*Index).Write", Method, 0}, - {"Index", Type, 0}, - {"New", Func, 0}, + {"(*Index).Bytes", Method, 0, ""}, + {"(*Index).FindAllIndex", Method, 0, ""}, + {"(*Index).Lookup", Method, 0, ""}, + {"(*Index).Read", Method, 0, ""}, + {"(*Index).Write", Method, 0, ""}, + {"Index", Type, 0, ""}, + {"New", Func, 0, "func(data []byte) *Index"}, }, "io": { - {"(*LimitedReader).Read", Method, 0}, - {"(*OffsetWriter).Seek", Method, 20}, - {"(*OffsetWriter).Write", Method, 20}, - {"(*OffsetWriter).WriteAt", Method, 20}, - {"(*PipeReader).Close", Method, 0}, - {"(*PipeReader).CloseWithError", Method, 0}, - {"(*PipeReader).Read", Method, 0}, - {"(*PipeWriter).Close", Method, 0}, - {"(*PipeWriter).CloseWithError", Method, 0}, - {"(*PipeWriter).Write", Method, 0}, - {"(*SectionReader).Outer", Method, 22}, - {"(*SectionReader).Read", Method, 0}, - {"(*SectionReader).ReadAt", Method, 0}, - {"(*SectionReader).Seek", Method, 0}, - {"(*SectionReader).Size", Method, 0}, - {"ByteReader", Type, 0}, - {"ByteScanner", Type, 0}, - {"ByteWriter", Type, 1}, - {"Closer", Type, 0}, - {"Copy", Func, 0}, - {"CopyBuffer", Func, 5}, - {"CopyN", Func, 0}, - {"Discard", Var, 16}, - {"EOF", Var, 0}, - {"ErrClosedPipe", Var, 0}, - {"ErrNoProgress", Var, 1}, - {"ErrShortBuffer", Var, 0}, - {"ErrShortWrite", Var, 0}, - {"ErrUnexpectedEOF", Var, 0}, - {"LimitReader", Func, 0}, - {"LimitedReader", Type, 0}, - {"LimitedReader.N", Field, 0}, - {"LimitedReader.R", Field, 0}, - {"MultiReader", Func, 0}, - {"MultiWriter", Func, 0}, - {"NewOffsetWriter", Func, 20}, - {"NewSectionReader", Func, 0}, - {"NopCloser", Func, 16}, - {"OffsetWriter", Type, 20}, - {"Pipe", Func, 0}, - {"PipeReader", Type, 0}, - {"PipeWriter", Type, 0}, - {"ReadAll", Func, 16}, - {"ReadAtLeast", Func, 0}, - {"ReadCloser", Type, 0}, - {"ReadFull", Func, 0}, - {"ReadSeekCloser", Type, 16}, - {"ReadSeeker", Type, 0}, - {"ReadWriteCloser", Type, 0}, - {"ReadWriteSeeker", Type, 0}, - {"ReadWriter", Type, 0}, - {"Reader", Type, 0}, - {"ReaderAt", Type, 0}, - {"ReaderFrom", Type, 0}, - {"RuneReader", Type, 0}, - {"RuneScanner", Type, 0}, - {"SectionReader", Type, 0}, - {"SeekCurrent", Const, 7}, - {"SeekEnd", Const, 7}, - {"SeekStart", Const, 7}, - {"Seeker", Type, 0}, - {"StringWriter", Type, 12}, - {"TeeReader", Func, 0}, - {"WriteCloser", Type, 0}, - {"WriteSeeker", Type, 0}, - {"WriteString", Func, 0}, - {"Writer", Type, 0}, - {"WriterAt", Type, 0}, - {"WriterTo", Type, 0}, + {"(*LimitedReader).Read", Method, 0, ""}, + {"(*OffsetWriter).Seek", Method, 20, ""}, + {"(*OffsetWriter).Write", Method, 20, ""}, + {"(*OffsetWriter).WriteAt", Method, 20, ""}, + {"(*PipeReader).Close", Method, 0, ""}, + {"(*PipeReader).CloseWithError", Method, 0, ""}, + {"(*PipeReader).Read", Method, 0, ""}, + {"(*PipeWriter).Close", Method, 0, ""}, + {"(*PipeWriter).CloseWithError", Method, 0, ""}, + {"(*PipeWriter).Write", Method, 0, ""}, + {"(*SectionReader).Outer", Method, 22, ""}, + {"(*SectionReader).Read", Method, 0, ""}, + {"(*SectionReader).ReadAt", Method, 0, ""}, + {"(*SectionReader).Seek", Method, 0, ""}, + {"(*SectionReader).Size", Method, 0, ""}, + {"ByteReader", Type, 0, ""}, + {"ByteScanner", Type, 0, ""}, + {"ByteWriter", Type, 1, ""}, + {"Closer", Type, 0, ""}, + {"Copy", Func, 0, "func(dst Writer, src Reader) (written int64, err error)"}, + {"CopyBuffer", Func, 5, "func(dst Writer, src Reader, buf []byte) (written int64, err error)"}, + {"CopyN", Func, 0, "func(dst Writer, src Reader, n int64) (written int64, err error)"}, + {"Discard", Var, 16, ""}, + {"EOF", Var, 0, ""}, + {"ErrClosedPipe", Var, 0, ""}, + {"ErrNoProgress", Var, 1, ""}, + {"ErrShortBuffer", Var, 0, ""}, + {"ErrShortWrite", Var, 0, ""}, + {"ErrUnexpectedEOF", Var, 0, ""}, + {"LimitReader", Func, 0, "func(r Reader, n int64) Reader"}, + {"LimitedReader", Type, 0, ""}, + {"LimitedReader.N", Field, 0, ""}, + {"LimitedReader.R", Field, 0, ""}, + {"MultiReader", Func, 0, "func(readers ...Reader) Reader"}, + {"MultiWriter", Func, 0, "func(writers ...Writer) Writer"}, + {"NewOffsetWriter", Func, 20, "func(w WriterAt, off int64) *OffsetWriter"}, + {"NewSectionReader", Func, 0, "func(r ReaderAt, off int64, n int64) *SectionReader"}, + {"NopCloser", Func, 16, "func(r Reader) ReadCloser"}, + {"OffsetWriter", Type, 20, ""}, + {"Pipe", Func, 0, "func() (*PipeReader, *PipeWriter)"}, + {"PipeReader", Type, 0, ""}, + {"PipeWriter", Type, 0, ""}, + {"ReadAll", Func, 16, "func(r Reader) ([]byte, error)"}, + {"ReadAtLeast", Func, 0, "func(r Reader, buf []byte, min int) (n int, err error)"}, + {"ReadCloser", Type, 0, ""}, + {"ReadFull", Func, 0, "func(r Reader, buf []byte) (n int, err error)"}, + {"ReadSeekCloser", Type, 16, ""}, + {"ReadSeeker", Type, 0, ""}, + {"ReadWriteCloser", Type, 0, ""}, + {"ReadWriteSeeker", Type, 0, ""}, + {"ReadWriter", Type, 0, ""}, + {"Reader", Type, 0, ""}, + {"ReaderAt", Type, 0, ""}, + {"ReaderFrom", Type, 0, ""}, + {"RuneReader", Type, 0, ""}, + {"RuneScanner", Type, 0, ""}, + {"SectionReader", Type, 0, ""}, + {"SeekCurrent", Const, 7, ""}, + {"SeekEnd", Const, 7, ""}, + {"SeekStart", Const, 7, ""}, + {"Seeker", Type, 0, ""}, + {"StringWriter", Type, 12, ""}, + {"TeeReader", Func, 0, "func(r Reader, w Writer) Reader"}, + {"WriteCloser", Type, 0, ""}, + {"WriteSeeker", Type, 0, ""}, + {"WriteString", Func, 0, "func(w Writer, s string) (n int, err error)"}, + {"Writer", Type, 0, ""}, + {"WriterAt", Type, 0, ""}, + {"WriterTo", Type, 0, ""}, }, "io/fs": { - {"(*PathError).Error", Method, 16}, - {"(*PathError).Timeout", Method, 16}, - {"(*PathError).Unwrap", Method, 16}, - {"(FileMode).IsDir", Method, 16}, - {"(FileMode).IsRegular", Method, 16}, - {"(FileMode).Perm", Method, 16}, - {"(FileMode).String", Method, 16}, - {"(FileMode).Type", Method, 16}, - {"DirEntry", Type, 16}, - {"ErrClosed", Var, 16}, - {"ErrExist", Var, 16}, - {"ErrInvalid", Var, 16}, - {"ErrNotExist", Var, 16}, - {"ErrPermission", Var, 16}, - {"FS", Type, 16}, - {"File", Type, 16}, - {"FileInfo", Type, 16}, - {"FileInfoToDirEntry", Func, 17}, - {"FileMode", Type, 16}, - {"FormatDirEntry", Func, 21}, - {"FormatFileInfo", Func, 21}, - {"Glob", Func, 16}, - {"GlobFS", Type, 16}, - {"Lstat", Func, 25}, - {"ModeAppend", Const, 16}, - {"ModeCharDevice", Const, 16}, - {"ModeDevice", Const, 16}, - {"ModeDir", Const, 16}, - {"ModeExclusive", Const, 16}, - {"ModeIrregular", Const, 16}, - {"ModeNamedPipe", Const, 16}, - {"ModePerm", Const, 16}, - {"ModeSetgid", Const, 16}, - {"ModeSetuid", Const, 16}, - {"ModeSocket", Const, 16}, - {"ModeSticky", Const, 16}, - {"ModeSymlink", Const, 16}, - {"ModeTemporary", Const, 16}, - {"ModeType", Const, 16}, - {"PathError", Type, 16}, - {"PathError.Err", Field, 16}, - {"PathError.Op", Field, 16}, - {"PathError.Path", Field, 16}, - {"ReadDir", Func, 16}, - {"ReadDirFS", Type, 16}, - {"ReadDirFile", Type, 16}, - {"ReadFile", Func, 16}, - {"ReadFileFS", Type, 16}, - {"ReadLink", Func, 25}, - {"ReadLinkFS", Type, 25}, - {"SkipAll", Var, 20}, - {"SkipDir", Var, 16}, - {"Stat", Func, 16}, - {"StatFS", Type, 16}, - {"Sub", Func, 16}, - {"SubFS", Type, 16}, - {"ValidPath", Func, 16}, - {"WalkDir", Func, 16}, - {"WalkDirFunc", Type, 16}, + {"(*PathError).Error", Method, 16, ""}, + {"(*PathError).Timeout", Method, 16, ""}, + {"(*PathError).Unwrap", Method, 16, ""}, + {"(FileMode).IsDir", Method, 16, ""}, + {"(FileMode).IsRegular", Method, 16, ""}, + {"(FileMode).Perm", Method, 16, ""}, + {"(FileMode).String", Method, 16, ""}, + {"(FileMode).Type", Method, 16, ""}, + {"DirEntry", Type, 16, ""}, + {"ErrClosed", Var, 16, ""}, + {"ErrExist", Var, 16, ""}, + {"ErrInvalid", Var, 16, ""}, + {"ErrNotExist", Var, 16, ""}, + {"ErrPermission", Var, 16, ""}, + {"FS", Type, 16, ""}, + {"File", Type, 16, ""}, + {"FileInfo", Type, 16, ""}, + {"FileInfoToDirEntry", Func, 17, "func(info FileInfo) DirEntry"}, + {"FileMode", Type, 16, ""}, + {"FormatDirEntry", Func, 21, "func(dir DirEntry) string"}, + {"FormatFileInfo", Func, 21, "func(info FileInfo) string"}, + {"Glob", Func, 16, "func(fsys FS, pattern string) (matches []string, err error)"}, + {"GlobFS", Type, 16, ""}, + {"Lstat", Func, 25, ""}, + {"ModeAppend", Const, 16, ""}, + {"ModeCharDevice", Const, 16, ""}, + {"ModeDevice", Const, 16, ""}, + {"ModeDir", Const, 16, ""}, + {"ModeExclusive", Const, 16, ""}, + {"ModeIrregular", Const, 16, ""}, + {"ModeNamedPipe", Const, 16, ""}, + {"ModePerm", Const, 16, ""}, + {"ModeSetgid", Const, 16, ""}, + {"ModeSetuid", Const, 16, ""}, + {"ModeSocket", Const, 16, ""}, + {"ModeSticky", Const, 16, ""}, + {"ModeSymlink", Const, 16, ""}, + {"ModeTemporary", Const, 16, ""}, + {"ModeType", Const, 16, ""}, + {"PathError", Type, 16, ""}, + {"PathError.Err", Field, 16, ""}, + {"PathError.Op", Field, 16, ""}, + {"PathError.Path", Field, 16, ""}, + {"ReadDir", Func, 16, "func(fsys FS, name string) ([]DirEntry, error)"}, + {"ReadDirFS", Type, 16, ""}, + {"ReadDirFile", Type, 16, ""}, + {"ReadFile", Func, 16, "func(fsys FS, name string) ([]byte, error)"}, + {"ReadFileFS", Type, 16, ""}, + {"ReadLink", Func, 25, ""}, + {"ReadLinkFS", Type, 25, ""}, + {"SkipAll", Var, 20, ""}, + {"SkipDir", Var, 16, ""}, + {"Stat", Func, 16, "func(fsys FS, name string) (FileInfo, error)"}, + {"StatFS", Type, 16, ""}, + {"Sub", Func, 16, "func(fsys FS, dir string) (FS, error)"}, + {"SubFS", Type, 16, ""}, + {"ValidPath", Func, 16, "func(name string) bool"}, + {"WalkDir", Func, 16, "func(fsys FS, root string, fn WalkDirFunc) error"}, + {"WalkDirFunc", Type, 16, ""}, }, "io/ioutil": { - {"Discard", Var, 0}, - {"NopCloser", Func, 0}, - {"ReadAll", Func, 0}, - {"ReadDir", Func, 0}, - {"ReadFile", Func, 0}, - {"TempDir", Func, 0}, - {"TempFile", Func, 0}, - {"WriteFile", Func, 0}, + {"Discard", Var, 0, ""}, + {"NopCloser", Func, 0, "func(r io.Reader) io.ReadCloser"}, + {"ReadAll", Func, 0, "func(r io.Reader) ([]byte, error)"}, + {"ReadDir", Func, 0, "func(dirname string) ([]fs.FileInfo, error)"}, + {"ReadFile", Func, 0, "func(filename string) ([]byte, error)"}, + {"TempDir", Func, 0, "func(dir string, pattern string) (name string, err error)"}, + {"TempFile", Func, 0, "func(dir string, pattern string) (f *os.File, err error)"}, + {"WriteFile", Func, 0, "func(filename string, data []byte, perm fs.FileMode) error"}, }, "iter": { - {"Pull", Func, 23}, - {"Pull2", Func, 23}, - {"Seq", Type, 23}, - {"Seq2", Type, 23}, + {"Pull", Func, 23, "func[V any](seq Seq[V]) (next func() (V, bool), stop func())"}, + {"Pull2", Func, 23, "func[K, V any](seq Seq2[K, V]) (next func() (K, V, bool), stop func())"}, + {"Seq", Type, 23, ""}, + {"Seq2", Type, 23, ""}, }, "log": { - {"(*Logger).Fatal", Method, 0}, - {"(*Logger).Fatalf", Method, 0}, - {"(*Logger).Fatalln", Method, 0}, - {"(*Logger).Flags", Method, 0}, - {"(*Logger).Output", Method, 0}, - {"(*Logger).Panic", Method, 0}, - {"(*Logger).Panicf", Method, 0}, - {"(*Logger).Panicln", Method, 0}, - {"(*Logger).Prefix", Method, 0}, - {"(*Logger).Print", Method, 0}, - {"(*Logger).Printf", Method, 0}, - {"(*Logger).Println", Method, 0}, - {"(*Logger).SetFlags", Method, 0}, - {"(*Logger).SetOutput", Method, 5}, - {"(*Logger).SetPrefix", Method, 0}, - {"(*Logger).Writer", Method, 12}, - {"Default", Func, 16}, - {"Fatal", Func, 0}, - {"Fatalf", Func, 0}, - {"Fatalln", Func, 0}, - {"Flags", Func, 0}, - {"LUTC", Const, 5}, - {"Ldate", Const, 0}, - {"Llongfile", Const, 0}, - {"Lmicroseconds", Const, 0}, - {"Lmsgprefix", Const, 14}, - {"Logger", Type, 0}, - {"Lshortfile", Const, 0}, - {"LstdFlags", Const, 0}, - {"Ltime", Const, 0}, - {"New", Func, 0}, - {"Output", Func, 5}, - {"Panic", Func, 0}, - {"Panicf", Func, 0}, - {"Panicln", Func, 0}, - {"Prefix", Func, 0}, - {"Print", Func, 0}, - {"Printf", Func, 0}, - {"Println", Func, 0}, - {"SetFlags", Func, 0}, - {"SetOutput", Func, 0}, - {"SetPrefix", Func, 0}, - {"Writer", Func, 13}, + {"(*Logger).Fatal", Method, 0, ""}, + {"(*Logger).Fatalf", Method, 0, ""}, + {"(*Logger).Fatalln", Method, 0, ""}, + {"(*Logger).Flags", Method, 0, ""}, + {"(*Logger).Output", Method, 0, ""}, + {"(*Logger).Panic", Method, 0, ""}, + {"(*Logger).Panicf", Method, 0, ""}, + {"(*Logger).Panicln", Method, 0, ""}, + {"(*Logger).Prefix", Method, 0, ""}, + {"(*Logger).Print", Method, 0, ""}, + {"(*Logger).Printf", Method, 0, ""}, + {"(*Logger).Println", Method, 0, ""}, + {"(*Logger).SetFlags", Method, 0, ""}, + {"(*Logger).SetOutput", Method, 5, ""}, + {"(*Logger).SetPrefix", Method, 0, ""}, + {"(*Logger).Writer", Method, 12, ""}, + {"Default", Func, 16, "func() *Logger"}, + {"Fatal", Func, 0, "func(v ...any)"}, + {"Fatalf", Func, 0, "func(format string, v ...any)"}, + {"Fatalln", Func, 0, "func(v ...any)"}, + {"Flags", Func, 0, "func() int"}, + {"LUTC", Const, 5, ""}, + {"Ldate", Const, 0, ""}, + {"Llongfile", Const, 0, ""}, + {"Lmicroseconds", Const, 0, ""}, + {"Lmsgprefix", Const, 14, ""}, + {"Logger", Type, 0, ""}, + {"Lshortfile", Const, 0, ""}, + {"LstdFlags", Const, 0, ""}, + {"Ltime", Const, 0, ""}, + {"New", Func, 0, "func(out io.Writer, prefix string, flag int) *Logger"}, + {"Output", Func, 5, "func(calldepth int, s string) error"}, + {"Panic", Func, 0, "func(v ...any)"}, + {"Panicf", Func, 0, "func(format string, v ...any)"}, + {"Panicln", Func, 0, "func(v ...any)"}, + {"Prefix", Func, 0, "func() string"}, + {"Print", Func, 0, "func(v ...any)"}, + {"Printf", Func, 0, "func(format string, v ...any)"}, + {"Println", Func, 0, "func(v ...any)"}, + {"SetFlags", Func, 0, "func(flag int)"}, + {"SetOutput", Func, 0, "func(w io.Writer)"}, + {"SetPrefix", Func, 0, "func(prefix string)"}, + {"Writer", Func, 13, "func() io.Writer"}, }, "log/slog": { - {"(*JSONHandler).Enabled", Method, 21}, - {"(*JSONHandler).Handle", Method, 21}, - {"(*JSONHandler).WithAttrs", Method, 21}, - {"(*JSONHandler).WithGroup", Method, 21}, - {"(*Level).UnmarshalJSON", Method, 21}, - {"(*Level).UnmarshalText", Method, 21}, - {"(*LevelVar).AppendText", Method, 24}, - {"(*LevelVar).Level", Method, 21}, - {"(*LevelVar).MarshalText", Method, 21}, - {"(*LevelVar).Set", Method, 21}, - {"(*LevelVar).String", Method, 21}, - {"(*LevelVar).UnmarshalText", Method, 21}, - {"(*Logger).Debug", Method, 21}, - {"(*Logger).DebugContext", Method, 21}, - {"(*Logger).Enabled", Method, 21}, - {"(*Logger).Error", Method, 21}, - {"(*Logger).ErrorContext", Method, 21}, - {"(*Logger).Handler", Method, 21}, - {"(*Logger).Info", Method, 21}, - {"(*Logger).InfoContext", Method, 21}, - {"(*Logger).Log", Method, 21}, - {"(*Logger).LogAttrs", Method, 21}, - {"(*Logger).Warn", Method, 21}, - {"(*Logger).WarnContext", Method, 21}, - {"(*Logger).With", Method, 21}, - {"(*Logger).WithGroup", Method, 21}, - {"(*Record).Add", Method, 21}, - {"(*Record).AddAttrs", Method, 21}, - {"(*TextHandler).Enabled", Method, 21}, - {"(*TextHandler).Handle", Method, 21}, - {"(*TextHandler).WithAttrs", Method, 21}, - {"(*TextHandler).WithGroup", Method, 21}, - {"(Attr).Equal", Method, 21}, - {"(Attr).String", Method, 21}, - {"(Kind).String", Method, 21}, - {"(Level).AppendText", Method, 24}, - {"(Level).Level", Method, 21}, - {"(Level).MarshalJSON", Method, 21}, - {"(Level).MarshalText", Method, 21}, - {"(Level).String", Method, 21}, - {"(Record).Attrs", Method, 21}, - {"(Record).Clone", Method, 21}, - {"(Record).NumAttrs", Method, 21}, - {"(Value).Any", Method, 21}, - {"(Value).Bool", Method, 21}, - {"(Value).Duration", Method, 21}, - {"(Value).Equal", Method, 21}, - {"(Value).Float64", Method, 21}, - {"(Value).Group", Method, 21}, - {"(Value).Int64", Method, 21}, - {"(Value).Kind", Method, 21}, - {"(Value).LogValuer", Method, 21}, - {"(Value).Resolve", Method, 21}, - {"(Value).String", Method, 21}, - {"(Value).Time", Method, 21}, - {"(Value).Uint64", Method, 21}, - {"Any", Func, 21}, - {"AnyValue", Func, 21}, - {"Attr", Type, 21}, - {"Attr.Key", Field, 21}, - {"Attr.Value", Field, 21}, - {"Bool", Func, 21}, - {"BoolValue", Func, 21}, - {"Debug", Func, 21}, - {"DebugContext", Func, 21}, - {"Default", Func, 21}, - {"DiscardHandler", Var, 24}, - {"Duration", Func, 21}, - {"DurationValue", Func, 21}, - {"Error", Func, 21}, - {"ErrorContext", Func, 21}, - {"Float64", Func, 21}, - {"Float64Value", Func, 21}, - {"Group", Func, 21}, - {"GroupValue", Func, 21}, - {"Handler", Type, 21}, - {"HandlerOptions", Type, 21}, - {"HandlerOptions.AddSource", Field, 21}, - {"HandlerOptions.Level", Field, 21}, - {"HandlerOptions.ReplaceAttr", Field, 21}, - {"Info", Func, 21}, - {"InfoContext", Func, 21}, - {"Int", Func, 21}, - {"Int64", Func, 21}, - {"Int64Value", Func, 21}, - {"IntValue", Func, 21}, - {"JSONHandler", Type, 21}, - {"Kind", Type, 21}, - {"KindAny", Const, 21}, - {"KindBool", Const, 21}, - {"KindDuration", Const, 21}, - {"KindFloat64", Const, 21}, - {"KindGroup", Const, 21}, - {"KindInt64", Const, 21}, - {"KindLogValuer", Const, 21}, - {"KindString", Const, 21}, - {"KindTime", Const, 21}, - {"KindUint64", Const, 21}, - {"Level", Type, 21}, - {"LevelDebug", Const, 21}, - {"LevelError", Const, 21}, - {"LevelInfo", Const, 21}, - {"LevelKey", Const, 21}, - {"LevelVar", Type, 21}, - {"LevelWarn", Const, 21}, - {"Leveler", Type, 21}, - {"Log", Func, 21}, - {"LogAttrs", Func, 21}, - {"LogValuer", Type, 21}, - {"Logger", Type, 21}, - {"MessageKey", Const, 21}, - {"New", Func, 21}, - {"NewJSONHandler", Func, 21}, - {"NewLogLogger", Func, 21}, - {"NewRecord", Func, 21}, - {"NewTextHandler", Func, 21}, - {"Record", Type, 21}, - {"Record.Level", Field, 21}, - {"Record.Message", Field, 21}, - {"Record.PC", Field, 21}, - {"Record.Time", Field, 21}, - {"SetDefault", Func, 21}, - {"SetLogLoggerLevel", Func, 22}, - {"Source", Type, 21}, - {"Source.File", Field, 21}, - {"Source.Function", Field, 21}, - {"Source.Line", Field, 21}, - {"SourceKey", Const, 21}, - {"String", Func, 21}, - {"StringValue", Func, 21}, - {"TextHandler", Type, 21}, - {"Time", Func, 21}, - {"TimeKey", Const, 21}, - {"TimeValue", Func, 21}, - {"Uint64", Func, 21}, - {"Uint64Value", Func, 21}, - {"Value", Type, 21}, - {"Warn", Func, 21}, - {"WarnContext", Func, 21}, - {"With", Func, 21}, + {"(*JSONHandler).Enabled", Method, 21, ""}, + {"(*JSONHandler).Handle", Method, 21, ""}, + {"(*JSONHandler).WithAttrs", Method, 21, ""}, + {"(*JSONHandler).WithGroup", Method, 21, ""}, + {"(*Level).UnmarshalJSON", Method, 21, ""}, + {"(*Level).UnmarshalText", Method, 21, ""}, + {"(*LevelVar).AppendText", Method, 24, ""}, + {"(*LevelVar).Level", Method, 21, ""}, + {"(*LevelVar).MarshalText", Method, 21, ""}, + {"(*LevelVar).Set", Method, 21, ""}, + {"(*LevelVar).String", Method, 21, ""}, + {"(*LevelVar).UnmarshalText", Method, 21, ""}, + {"(*Logger).Debug", Method, 21, ""}, + {"(*Logger).DebugContext", Method, 21, ""}, + {"(*Logger).Enabled", Method, 21, ""}, + {"(*Logger).Error", Method, 21, ""}, + {"(*Logger).ErrorContext", Method, 21, ""}, + {"(*Logger).Handler", Method, 21, ""}, + {"(*Logger).Info", Method, 21, ""}, + {"(*Logger).InfoContext", Method, 21, ""}, + {"(*Logger).Log", Method, 21, ""}, + {"(*Logger).LogAttrs", Method, 21, ""}, + {"(*Logger).Warn", Method, 21, ""}, + {"(*Logger).WarnContext", Method, 21, ""}, + {"(*Logger).With", Method, 21, ""}, + {"(*Logger).WithGroup", Method, 21, ""}, + {"(*Record).Add", Method, 21, ""}, + {"(*Record).AddAttrs", Method, 21, ""}, + {"(*TextHandler).Enabled", Method, 21, ""}, + {"(*TextHandler).Handle", Method, 21, ""}, + {"(*TextHandler).WithAttrs", Method, 21, ""}, + {"(*TextHandler).WithGroup", Method, 21, ""}, + {"(Attr).Equal", Method, 21, ""}, + {"(Attr).String", Method, 21, ""}, + {"(Kind).String", Method, 21, ""}, + {"(Level).AppendText", Method, 24, ""}, + {"(Level).Level", Method, 21, ""}, + {"(Level).MarshalJSON", Method, 21, ""}, + {"(Level).MarshalText", Method, 21, ""}, + {"(Level).String", Method, 21, ""}, + {"(Record).Attrs", Method, 21, ""}, + {"(Record).Clone", Method, 21, ""}, + {"(Record).NumAttrs", Method, 21, ""}, + {"(Value).Any", Method, 21, ""}, + {"(Value).Bool", Method, 21, ""}, + {"(Value).Duration", Method, 21, ""}, + {"(Value).Equal", Method, 21, ""}, + {"(Value).Float64", Method, 21, ""}, + {"(Value).Group", Method, 21, ""}, + {"(Value).Int64", Method, 21, ""}, + {"(Value).Kind", Method, 21, ""}, + {"(Value).LogValuer", Method, 21, ""}, + {"(Value).Resolve", Method, 21, ""}, + {"(Value).String", Method, 21, ""}, + {"(Value).Time", Method, 21, ""}, + {"(Value).Uint64", Method, 21, ""}, + {"Any", Func, 21, "func(key string, value any) Attr"}, + {"AnyValue", Func, 21, "func(v any) Value"}, + {"Attr", Type, 21, ""}, + {"Attr.Key", Field, 21, ""}, + {"Attr.Value", Field, 21, ""}, + {"Bool", Func, 21, "func(key string, v bool) Attr"}, + {"BoolValue", Func, 21, "func(v bool) Value"}, + {"Debug", Func, 21, "func(msg string, args ...any)"}, + {"DebugContext", Func, 21, "func(ctx context.Context, msg string, args ...any)"}, + {"Default", Func, 21, "func() *Logger"}, + {"DiscardHandler", Var, 24, ""}, + {"Duration", Func, 21, "func(key string, v time.Duration) Attr"}, + {"DurationValue", Func, 21, "func(v time.Duration) Value"}, + {"Error", Func, 21, "func(msg string, args ...any)"}, + {"ErrorContext", Func, 21, "func(ctx context.Context, msg string, args ...any)"}, + {"Float64", Func, 21, "func(key string, v float64) Attr"}, + {"Float64Value", Func, 21, "func(v float64) Value"}, + {"Group", Func, 21, "func(key string, args ...any) Attr"}, + {"GroupValue", Func, 21, "func(as ...Attr) Value"}, + {"Handler", Type, 21, ""}, + {"HandlerOptions", Type, 21, ""}, + {"HandlerOptions.AddSource", Field, 21, ""}, + {"HandlerOptions.Level", Field, 21, ""}, + {"HandlerOptions.ReplaceAttr", Field, 21, ""}, + {"Info", Func, 21, "func(msg string, args ...any)"}, + {"InfoContext", Func, 21, "func(ctx context.Context, msg string, args ...any)"}, + {"Int", Func, 21, "func(key string, value int) Attr"}, + {"Int64", Func, 21, "func(key string, value int64) Attr"}, + {"Int64Value", Func, 21, "func(v int64) Value"}, + {"IntValue", Func, 21, "func(v int) Value"}, + {"JSONHandler", Type, 21, ""}, + {"Kind", Type, 21, ""}, + {"KindAny", Const, 21, ""}, + {"KindBool", Const, 21, ""}, + {"KindDuration", Const, 21, ""}, + {"KindFloat64", Const, 21, ""}, + {"KindGroup", Const, 21, ""}, + {"KindInt64", Const, 21, ""}, + {"KindLogValuer", Const, 21, ""}, + {"KindString", Const, 21, ""}, + {"KindTime", Const, 21, ""}, + {"KindUint64", Const, 21, ""}, + {"Level", Type, 21, ""}, + {"LevelDebug", Const, 21, ""}, + {"LevelError", Const, 21, ""}, + {"LevelInfo", Const, 21, ""}, + {"LevelKey", Const, 21, ""}, + {"LevelVar", Type, 21, ""}, + {"LevelWarn", Const, 21, ""}, + {"Leveler", Type, 21, ""}, + {"Log", Func, 21, "func(ctx context.Context, level Level, msg string, args ...any)"}, + {"LogAttrs", Func, 21, "func(ctx context.Context, level Level, msg string, attrs ...Attr)"}, + {"LogValuer", Type, 21, ""}, + {"Logger", Type, 21, ""}, + {"MessageKey", Const, 21, ""}, + {"New", Func, 21, "func(h Handler) *Logger"}, + {"NewJSONHandler", Func, 21, "func(w io.Writer, opts *HandlerOptions) *JSONHandler"}, + {"NewLogLogger", Func, 21, "func(h Handler, level Level) *log.Logger"}, + {"NewRecord", Func, 21, "func(t time.Time, level Level, msg string, pc uintptr) Record"}, + {"NewTextHandler", Func, 21, "func(w io.Writer, opts *HandlerOptions) *TextHandler"}, + {"Record", Type, 21, ""}, + {"Record.Level", Field, 21, ""}, + {"Record.Message", Field, 21, ""}, + {"Record.PC", Field, 21, ""}, + {"Record.Time", Field, 21, ""}, + {"SetDefault", Func, 21, "func(l *Logger)"}, + {"SetLogLoggerLevel", Func, 22, "func(level Level) (oldLevel Level)"}, + {"Source", Type, 21, ""}, + {"Source.File", Field, 21, ""}, + {"Source.Function", Field, 21, ""}, + {"Source.Line", Field, 21, ""}, + {"SourceKey", Const, 21, ""}, + {"String", Func, 21, "func(key string, value string) Attr"}, + {"StringValue", Func, 21, "func(value string) Value"}, + {"TextHandler", Type, 21, ""}, + {"Time", Func, 21, "func(key string, v time.Time) Attr"}, + {"TimeKey", Const, 21, ""}, + {"TimeValue", Func, 21, "func(v time.Time) Value"}, + {"Uint64", Func, 21, "func(key string, v uint64) Attr"}, + {"Uint64Value", Func, 21, "func(v uint64) Value"}, + {"Value", Type, 21, ""}, + {"Warn", Func, 21, "func(msg string, args ...any)"}, + {"WarnContext", Func, 21, "func(ctx context.Context, msg string, args ...any)"}, + {"With", Func, 21, "func(args ...any) *Logger"}, }, "log/syslog": { - {"(*Writer).Alert", Method, 0}, - {"(*Writer).Close", Method, 0}, - {"(*Writer).Crit", Method, 0}, - {"(*Writer).Debug", Method, 0}, - {"(*Writer).Emerg", Method, 0}, - {"(*Writer).Err", Method, 0}, - {"(*Writer).Info", Method, 0}, - {"(*Writer).Notice", Method, 0}, - {"(*Writer).Warning", Method, 0}, - {"(*Writer).Write", Method, 0}, - {"Dial", Func, 0}, - {"LOG_ALERT", Const, 0}, - {"LOG_AUTH", Const, 1}, - {"LOG_AUTHPRIV", Const, 1}, - {"LOG_CRIT", Const, 0}, - {"LOG_CRON", Const, 1}, - {"LOG_DAEMON", Const, 1}, - {"LOG_DEBUG", Const, 0}, - {"LOG_EMERG", Const, 0}, - {"LOG_ERR", Const, 0}, - {"LOG_FTP", Const, 1}, - {"LOG_INFO", Const, 0}, - {"LOG_KERN", Const, 1}, - {"LOG_LOCAL0", Const, 1}, - {"LOG_LOCAL1", Const, 1}, - {"LOG_LOCAL2", Const, 1}, - {"LOG_LOCAL3", Const, 1}, - {"LOG_LOCAL4", Const, 1}, - {"LOG_LOCAL5", Const, 1}, - {"LOG_LOCAL6", Const, 1}, - {"LOG_LOCAL7", Const, 1}, - {"LOG_LPR", Const, 1}, - {"LOG_MAIL", Const, 1}, - {"LOG_NEWS", Const, 1}, - {"LOG_NOTICE", Const, 0}, - {"LOG_SYSLOG", Const, 1}, - {"LOG_USER", Const, 1}, - {"LOG_UUCP", Const, 1}, - {"LOG_WARNING", Const, 0}, - {"New", Func, 0}, - {"NewLogger", Func, 0}, - {"Priority", Type, 0}, - {"Writer", Type, 0}, + {"(*Writer).Alert", Method, 0, ""}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).Crit", Method, 0, ""}, + {"(*Writer).Debug", Method, 0, ""}, + {"(*Writer).Emerg", Method, 0, ""}, + {"(*Writer).Err", Method, 0, ""}, + {"(*Writer).Info", Method, 0, ""}, + {"(*Writer).Notice", Method, 0, ""}, + {"(*Writer).Warning", Method, 0, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"Dial", Func, 0, "func(network string, raddr string, priority Priority, tag string) (*Writer, error)"}, + {"LOG_ALERT", Const, 0, ""}, + {"LOG_AUTH", Const, 1, ""}, + {"LOG_AUTHPRIV", Const, 1, ""}, + {"LOG_CRIT", Const, 0, ""}, + {"LOG_CRON", Const, 1, ""}, + {"LOG_DAEMON", Const, 1, ""}, + {"LOG_DEBUG", Const, 0, ""}, + {"LOG_EMERG", Const, 0, ""}, + {"LOG_ERR", Const, 0, ""}, + {"LOG_FTP", Const, 1, ""}, + {"LOG_INFO", Const, 0, ""}, + {"LOG_KERN", Const, 1, ""}, + {"LOG_LOCAL0", Const, 1, ""}, + {"LOG_LOCAL1", Const, 1, ""}, + {"LOG_LOCAL2", Const, 1, ""}, + {"LOG_LOCAL3", Const, 1, ""}, + {"LOG_LOCAL4", Const, 1, ""}, + {"LOG_LOCAL5", Const, 1, ""}, + {"LOG_LOCAL6", Const, 1, ""}, + {"LOG_LOCAL7", Const, 1, ""}, + {"LOG_LPR", Const, 1, ""}, + {"LOG_MAIL", Const, 1, ""}, + {"LOG_NEWS", Const, 1, ""}, + {"LOG_NOTICE", Const, 0, ""}, + {"LOG_SYSLOG", Const, 1, ""}, + {"LOG_USER", Const, 1, ""}, + {"LOG_UUCP", Const, 1, ""}, + {"LOG_WARNING", Const, 0, ""}, + {"New", Func, 0, "func(priority Priority, tag string) (*Writer, error)"}, + {"NewLogger", Func, 0, "func(p Priority, logFlag int) (*log.Logger, error)"}, + {"Priority", Type, 0, ""}, + {"Writer", Type, 0, ""}, }, "maps": { - {"All", Func, 23}, - {"Clone", Func, 21}, - {"Collect", Func, 23}, - {"Copy", Func, 21}, - {"DeleteFunc", Func, 21}, - {"Equal", Func, 21}, - {"EqualFunc", Func, 21}, - {"Insert", Func, 23}, - {"Keys", Func, 23}, - {"Values", Func, 23}, + {"All", Func, 23, "func[Map ~map[K]V, K comparable, V any](m Map) iter.Seq2[K, V]"}, + {"Clone", Func, 21, "func[M ~map[K]V, K comparable, V any](m M) M"}, + {"Collect", Func, 23, "func[K comparable, V any](seq iter.Seq2[K, V]) map[K]V"}, + {"Copy", Func, 21, "func[M1 ~map[K]V, M2 ~map[K]V, K comparable, V any](dst M1, src M2)"}, + {"DeleteFunc", Func, 21, "func[M ~map[K]V, K comparable, V any](m M, del func(K, V) bool)"}, + {"Equal", Func, 21, "func[M1, M2 ~map[K]V, K, V comparable](m1 M1, m2 M2) bool"}, + {"EqualFunc", Func, 21, "func[M1 ~map[K]V1, M2 ~map[K]V2, K comparable, V1, V2 any](m1 M1, m2 M2, eq func(V1, V2) bool) bool"}, + {"Insert", Func, 23, "func[Map ~map[K]V, K comparable, V any](m Map, seq iter.Seq2[K, V])"}, + {"Keys", Func, 23, "func[Map ~map[K]V, K comparable, V any](m Map) iter.Seq[K]"}, + {"Values", Func, 23, "func[Map ~map[K]V, K comparable, V any](m Map) iter.Seq[V]"}, }, "math": { - {"Abs", Func, 0}, - {"Acos", Func, 0}, - {"Acosh", Func, 0}, - {"Asin", Func, 0}, - {"Asinh", Func, 0}, - {"Atan", Func, 0}, - {"Atan2", Func, 0}, - {"Atanh", Func, 0}, - {"Cbrt", Func, 0}, - {"Ceil", Func, 0}, - {"Copysign", Func, 0}, - {"Cos", Func, 0}, - {"Cosh", Func, 0}, - {"Dim", Func, 0}, - {"E", Const, 0}, - {"Erf", Func, 0}, - {"Erfc", Func, 0}, - {"Erfcinv", Func, 10}, - {"Erfinv", Func, 10}, - {"Exp", Func, 0}, - {"Exp2", Func, 0}, - {"Expm1", Func, 0}, - {"FMA", Func, 14}, - {"Float32bits", Func, 0}, - {"Float32frombits", Func, 0}, - {"Float64bits", Func, 0}, - {"Float64frombits", Func, 0}, - {"Floor", Func, 0}, - {"Frexp", Func, 0}, - {"Gamma", Func, 0}, - {"Hypot", Func, 0}, - {"Ilogb", Func, 0}, - {"Inf", Func, 0}, - {"IsInf", Func, 0}, - {"IsNaN", Func, 0}, - {"J0", Func, 0}, - {"J1", Func, 0}, - {"Jn", Func, 0}, - {"Ldexp", Func, 0}, - {"Lgamma", Func, 0}, - {"Ln10", Const, 0}, - {"Ln2", Const, 0}, - {"Log", Func, 0}, - {"Log10", Func, 0}, - {"Log10E", Const, 0}, - {"Log1p", Func, 0}, - {"Log2", Func, 0}, - {"Log2E", Const, 0}, - {"Logb", Func, 0}, - {"Max", Func, 0}, - {"MaxFloat32", Const, 0}, - {"MaxFloat64", Const, 0}, - {"MaxInt", Const, 17}, - {"MaxInt16", Const, 0}, - {"MaxInt32", Const, 0}, - {"MaxInt64", Const, 0}, - {"MaxInt8", Const, 0}, - {"MaxUint", Const, 17}, - {"MaxUint16", Const, 0}, - {"MaxUint32", Const, 0}, - {"MaxUint64", Const, 0}, - {"MaxUint8", Const, 0}, - {"Min", Func, 0}, - {"MinInt", Const, 17}, - {"MinInt16", Const, 0}, - {"MinInt32", Const, 0}, - {"MinInt64", Const, 0}, - {"MinInt8", Const, 0}, - {"Mod", Func, 0}, - {"Modf", Func, 0}, - {"NaN", Func, 0}, - {"Nextafter", Func, 0}, - {"Nextafter32", Func, 4}, - {"Phi", Const, 0}, - {"Pi", Const, 0}, - {"Pow", Func, 0}, - {"Pow10", Func, 0}, - {"Remainder", Func, 0}, - {"Round", Func, 10}, - {"RoundToEven", Func, 10}, - {"Signbit", Func, 0}, - {"Sin", Func, 0}, - {"Sincos", Func, 0}, - {"Sinh", Func, 0}, - {"SmallestNonzeroFloat32", Const, 0}, - {"SmallestNonzeroFloat64", Const, 0}, - {"Sqrt", Func, 0}, - {"Sqrt2", Const, 0}, - {"SqrtE", Const, 0}, - {"SqrtPhi", Const, 0}, - {"SqrtPi", Const, 0}, - {"Tan", Func, 0}, - {"Tanh", Func, 0}, - {"Trunc", Func, 0}, - {"Y0", Func, 0}, - {"Y1", Func, 0}, - {"Yn", Func, 0}, + {"Abs", Func, 0, "func(x float64) float64"}, + {"Acos", Func, 0, "func(x float64) float64"}, + {"Acosh", Func, 0, "func(x float64) float64"}, + {"Asin", Func, 0, "func(x float64) float64"}, + {"Asinh", Func, 0, "func(x float64) float64"}, + {"Atan", Func, 0, "func(x float64) float64"}, + {"Atan2", Func, 0, "func(y float64, x float64) float64"}, + {"Atanh", Func, 0, "func(x float64) float64"}, + {"Cbrt", Func, 0, "func(x float64) float64"}, + {"Ceil", Func, 0, "func(x float64) float64"}, + {"Copysign", Func, 0, "func(f float64, sign float64) float64"}, + {"Cos", Func, 0, "func(x float64) float64"}, + {"Cosh", Func, 0, "func(x float64) float64"}, + {"Dim", Func, 0, "func(x float64, y float64) float64"}, + {"E", Const, 0, ""}, + {"Erf", Func, 0, "func(x float64) float64"}, + {"Erfc", Func, 0, "func(x float64) float64"}, + {"Erfcinv", Func, 10, "func(x float64) float64"}, + {"Erfinv", Func, 10, "func(x float64) float64"}, + {"Exp", Func, 0, "func(x float64) float64"}, + {"Exp2", Func, 0, "func(x float64) float64"}, + {"Expm1", Func, 0, "func(x float64) float64"}, + {"FMA", Func, 14, "func(x float64, y float64, z float64) float64"}, + {"Float32bits", Func, 0, "func(f float32) uint32"}, + {"Float32frombits", Func, 0, "func(b uint32) float32"}, + {"Float64bits", Func, 0, "func(f float64) uint64"}, + {"Float64frombits", Func, 0, "func(b uint64) float64"}, + {"Floor", Func, 0, "func(x float64) float64"}, + {"Frexp", Func, 0, "func(f float64) (frac float64, exp int)"}, + {"Gamma", Func, 0, "func(x float64) float64"}, + {"Hypot", Func, 0, "func(p float64, q float64) float64"}, + {"Ilogb", Func, 0, "func(x float64) int"}, + {"Inf", Func, 0, "func(sign int) float64"}, + {"IsInf", Func, 0, "func(f float64, sign int) bool"}, + {"IsNaN", Func, 0, "func(f float64) (is bool)"}, + {"J0", Func, 0, "func(x float64) float64"}, + {"J1", Func, 0, "func(x float64) float64"}, + {"Jn", Func, 0, "func(n int, x float64) float64"}, + {"Ldexp", Func, 0, "func(frac float64, exp int) float64"}, + {"Lgamma", Func, 0, "func(x float64) (lgamma float64, sign int)"}, + {"Ln10", Const, 0, ""}, + {"Ln2", Const, 0, ""}, + {"Log", Func, 0, "func(x float64) float64"}, + {"Log10", Func, 0, "func(x float64) float64"}, + {"Log10E", Const, 0, ""}, + {"Log1p", Func, 0, "func(x float64) float64"}, + {"Log2", Func, 0, "func(x float64) float64"}, + {"Log2E", Const, 0, ""}, + {"Logb", Func, 0, "func(x float64) float64"}, + {"Max", Func, 0, "func(x float64, y float64) float64"}, + {"MaxFloat32", Const, 0, ""}, + {"MaxFloat64", Const, 0, ""}, + {"MaxInt", Const, 17, ""}, + {"MaxInt16", Const, 0, ""}, + {"MaxInt32", Const, 0, ""}, + {"MaxInt64", Const, 0, ""}, + {"MaxInt8", Const, 0, ""}, + {"MaxUint", Const, 17, ""}, + {"MaxUint16", Const, 0, ""}, + {"MaxUint32", Const, 0, ""}, + {"MaxUint64", Const, 0, ""}, + {"MaxUint8", Const, 0, ""}, + {"Min", Func, 0, "func(x float64, y float64) float64"}, + {"MinInt", Const, 17, ""}, + {"MinInt16", Const, 0, ""}, + {"MinInt32", Const, 0, ""}, + {"MinInt64", Const, 0, ""}, + {"MinInt8", Const, 0, ""}, + {"Mod", Func, 0, "func(x float64, y float64) float64"}, + {"Modf", Func, 0, "func(f float64) (int float64, frac float64)"}, + {"NaN", Func, 0, "func() float64"}, + {"Nextafter", Func, 0, "func(x float64, y float64) (r float64)"}, + {"Nextafter32", Func, 4, "func(x float32, y float32) (r float32)"}, + {"Phi", Const, 0, ""}, + {"Pi", Const, 0, ""}, + {"Pow", Func, 0, "func(x float64, y float64) float64"}, + {"Pow10", Func, 0, "func(n int) float64"}, + {"Remainder", Func, 0, "func(x float64, y float64) float64"}, + {"Round", Func, 10, "func(x float64) float64"}, + {"RoundToEven", Func, 10, "func(x float64) float64"}, + {"Signbit", Func, 0, "func(x float64) bool"}, + {"Sin", Func, 0, "func(x float64) float64"}, + {"Sincos", Func, 0, "func(x float64) (sin float64, cos float64)"}, + {"Sinh", Func, 0, "func(x float64) float64"}, + {"SmallestNonzeroFloat32", Const, 0, ""}, + {"SmallestNonzeroFloat64", Const, 0, ""}, + {"Sqrt", Func, 0, "func(x float64) float64"}, + {"Sqrt2", Const, 0, ""}, + {"SqrtE", Const, 0, ""}, + {"SqrtPhi", Const, 0, ""}, + {"SqrtPi", Const, 0, ""}, + {"Tan", Func, 0, "func(x float64) float64"}, + {"Tanh", Func, 0, "func(x float64) float64"}, + {"Trunc", Func, 0, "func(x float64) float64"}, + {"Y0", Func, 0, "func(x float64) float64"}, + {"Y1", Func, 0, "func(x float64) float64"}, + {"Yn", Func, 0, "func(n int, x float64) float64"}, }, "math/big": { - {"(*Float).Abs", Method, 5}, - {"(*Float).Acc", Method, 5}, - {"(*Float).Add", Method, 5}, - {"(*Float).Append", Method, 5}, - {"(*Float).AppendText", Method, 24}, - {"(*Float).Cmp", Method, 5}, - {"(*Float).Copy", Method, 5}, - {"(*Float).Float32", Method, 5}, - {"(*Float).Float64", Method, 5}, - {"(*Float).Format", Method, 5}, - {"(*Float).GobDecode", Method, 7}, - {"(*Float).GobEncode", Method, 7}, - {"(*Float).Int", Method, 5}, - {"(*Float).Int64", Method, 5}, - {"(*Float).IsInf", Method, 5}, - {"(*Float).IsInt", Method, 5}, - {"(*Float).MantExp", Method, 5}, - {"(*Float).MarshalText", Method, 6}, - {"(*Float).MinPrec", Method, 5}, - {"(*Float).Mode", Method, 5}, - {"(*Float).Mul", Method, 5}, - {"(*Float).Neg", Method, 5}, - {"(*Float).Parse", Method, 5}, - {"(*Float).Prec", Method, 5}, - {"(*Float).Quo", Method, 5}, - {"(*Float).Rat", Method, 5}, - {"(*Float).Scan", Method, 8}, - {"(*Float).Set", Method, 5}, - {"(*Float).SetFloat64", Method, 5}, - {"(*Float).SetInf", Method, 5}, - {"(*Float).SetInt", Method, 5}, - {"(*Float).SetInt64", Method, 5}, - {"(*Float).SetMantExp", Method, 5}, - {"(*Float).SetMode", Method, 5}, - {"(*Float).SetPrec", Method, 5}, - {"(*Float).SetRat", Method, 5}, - {"(*Float).SetString", Method, 5}, - {"(*Float).SetUint64", Method, 5}, - {"(*Float).Sign", Method, 5}, - {"(*Float).Signbit", Method, 5}, - {"(*Float).Sqrt", Method, 10}, - {"(*Float).String", Method, 5}, - {"(*Float).Sub", Method, 5}, - {"(*Float).Text", Method, 5}, - {"(*Float).Uint64", Method, 5}, - {"(*Float).UnmarshalText", Method, 6}, - {"(*Int).Abs", Method, 0}, - {"(*Int).Add", Method, 0}, - {"(*Int).And", Method, 0}, - {"(*Int).AndNot", Method, 0}, - {"(*Int).Append", Method, 6}, - {"(*Int).AppendText", Method, 24}, - {"(*Int).Binomial", Method, 0}, - {"(*Int).Bit", Method, 0}, - {"(*Int).BitLen", Method, 0}, - {"(*Int).Bits", Method, 0}, - {"(*Int).Bytes", Method, 0}, - {"(*Int).Cmp", Method, 0}, - {"(*Int).CmpAbs", Method, 10}, - {"(*Int).Div", Method, 0}, - {"(*Int).DivMod", Method, 0}, - {"(*Int).Exp", Method, 0}, - {"(*Int).FillBytes", Method, 15}, - {"(*Int).Float64", Method, 21}, - {"(*Int).Format", Method, 0}, - {"(*Int).GCD", Method, 0}, - {"(*Int).GobDecode", Method, 0}, - {"(*Int).GobEncode", Method, 0}, - {"(*Int).Int64", Method, 0}, - {"(*Int).IsInt64", Method, 9}, - {"(*Int).IsUint64", Method, 9}, - {"(*Int).Lsh", Method, 0}, - {"(*Int).MarshalJSON", Method, 1}, - {"(*Int).MarshalText", Method, 3}, - {"(*Int).Mod", Method, 0}, - {"(*Int).ModInverse", Method, 0}, - {"(*Int).ModSqrt", Method, 5}, - {"(*Int).Mul", Method, 0}, - {"(*Int).MulRange", Method, 0}, - {"(*Int).Neg", Method, 0}, - {"(*Int).Not", Method, 0}, - {"(*Int).Or", Method, 0}, - {"(*Int).ProbablyPrime", Method, 0}, - {"(*Int).Quo", Method, 0}, - {"(*Int).QuoRem", Method, 0}, - {"(*Int).Rand", Method, 0}, - {"(*Int).Rem", Method, 0}, - {"(*Int).Rsh", Method, 0}, - {"(*Int).Scan", Method, 0}, - {"(*Int).Set", Method, 0}, - {"(*Int).SetBit", Method, 0}, - {"(*Int).SetBits", Method, 0}, - {"(*Int).SetBytes", Method, 0}, - {"(*Int).SetInt64", Method, 0}, - {"(*Int).SetString", Method, 0}, - {"(*Int).SetUint64", Method, 1}, - {"(*Int).Sign", Method, 0}, - {"(*Int).Sqrt", Method, 8}, - {"(*Int).String", Method, 0}, - {"(*Int).Sub", Method, 0}, - {"(*Int).Text", Method, 6}, - {"(*Int).TrailingZeroBits", Method, 13}, - {"(*Int).Uint64", Method, 1}, - {"(*Int).UnmarshalJSON", Method, 1}, - {"(*Int).UnmarshalText", Method, 3}, - {"(*Int).Xor", Method, 0}, - {"(*Rat).Abs", Method, 0}, - {"(*Rat).Add", Method, 0}, - {"(*Rat).AppendText", Method, 24}, - {"(*Rat).Cmp", Method, 0}, - {"(*Rat).Denom", Method, 0}, - {"(*Rat).Float32", Method, 4}, - {"(*Rat).Float64", Method, 1}, - {"(*Rat).FloatPrec", Method, 22}, - {"(*Rat).FloatString", Method, 0}, - {"(*Rat).GobDecode", Method, 0}, - {"(*Rat).GobEncode", Method, 0}, - {"(*Rat).Inv", Method, 0}, - {"(*Rat).IsInt", Method, 0}, - {"(*Rat).MarshalText", Method, 3}, - {"(*Rat).Mul", Method, 0}, - {"(*Rat).Neg", Method, 0}, - {"(*Rat).Num", Method, 0}, - {"(*Rat).Quo", Method, 0}, - {"(*Rat).RatString", Method, 0}, - {"(*Rat).Scan", Method, 0}, - {"(*Rat).Set", Method, 0}, - {"(*Rat).SetFloat64", Method, 1}, - {"(*Rat).SetFrac", Method, 0}, - {"(*Rat).SetFrac64", Method, 0}, - {"(*Rat).SetInt", Method, 0}, - {"(*Rat).SetInt64", Method, 0}, - {"(*Rat).SetString", Method, 0}, - {"(*Rat).SetUint64", Method, 13}, - {"(*Rat).Sign", Method, 0}, - {"(*Rat).String", Method, 0}, - {"(*Rat).Sub", Method, 0}, - {"(*Rat).UnmarshalText", Method, 3}, - {"(Accuracy).String", Method, 5}, - {"(ErrNaN).Error", Method, 5}, - {"(RoundingMode).String", Method, 5}, - {"Above", Const, 5}, - {"Accuracy", Type, 5}, - {"AwayFromZero", Const, 5}, - {"Below", Const, 5}, - {"ErrNaN", Type, 5}, - {"Exact", Const, 5}, - {"Float", Type, 5}, - {"Int", Type, 0}, - {"Jacobi", Func, 5}, - {"MaxBase", Const, 0}, - {"MaxExp", Const, 5}, - {"MaxPrec", Const, 5}, - {"MinExp", Const, 5}, - {"NewFloat", Func, 5}, - {"NewInt", Func, 0}, - {"NewRat", Func, 0}, - {"ParseFloat", Func, 5}, - {"Rat", Type, 0}, - {"RoundingMode", Type, 5}, - {"ToNearestAway", Const, 5}, - {"ToNearestEven", Const, 5}, - {"ToNegativeInf", Const, 5}, - {"ToPositiveInf", Const, 5}, - {"ToZero", Const, 5}, - {"Word", Type, 0}, + {"(*Float).Abs", Method, 5, ""}, + {"(*Float).Acc", Method, 5, ""}, + {"(*Float).Add", Method, 5, ""}, + {"(*Float).Append", Method, 5, ""}, + {"(*Float).AppendText", Method, 24, ""}, + {"(*Float).Cmp", Method, 5, ""}, + {"(*Float).Copy", Method, 5, ""}, + {"(*Float).Float32", Method, 5, ""}, + {"(*Float).Float64", Method, 5, ""}, + {"(*Float).Format", Method, 5, ""}, + {"(*Float).GobDecode", Method, 7, ""}, + {"(*Float).GobEncode", Method, 7, ""}, + {"(*Float).Int", Method, 5, ""}, + {"(*Float).Int64", Method, 5, ""}, + {"(*Float).IsInf", Method, 5, ""}, + {"(*Float).IsInt", Method, 5, ""}, + {"(*Float).MantExp", Method, 5, ""}, + {"(*Float).MarshalText", Method, 6, ""}, + {"(*Float).MinPrec", Method, 5, ""}, + {"(*Float).Mode", Method, 5, ""}, + {"(*Float).Mul", Method, 5, ""}, + {"(*Float).Neg", Method, 5, ""}, + {"(*Float).Parse", Method, 5, ""}, + {"(*Float).Prec", Method, 5, ""}, + {"(*Float).Quo", Method, 5, ""}, + {"(*Float).Rat", Method, 5, ""}, + {"(*Float).Scan", Method, 8, ""}, + {"(*Float).Set", Method, 5, ""}, + {"(*Float).SetFloat64", Method, 5, ""}, + {"(*Float).SetInf", Method, 5, ""}, + {"(*Float).SetInt", Method, 5, ""}, + {"(*Float).SetInt64", Method, 5, ""}, + {"(*Float).SetMantExp", Method, 5, ""}, + {"(*Float).SetMode", Method, 5, ""}, + {"(*Float).SetPrec", Method, 5, ""}, + {"(*Float).SetRat", Method, 5, ""}, + {"(*Float).SetString", Method, 5, ""}, + {"(*Float).SetUint64", Method, 5, ""}, + {"(*Float).Sign", Method, 5, ""}, + {"(*Float).Signbit", Method, 5, ""}, + {"(*Float).Sqrt", Method, 10, ""}, + {"(*Float).String", Method, 5, ""}, + {"(*Float).Sub", Method, 5, ""}, + {"(*Float).Text", Method, 5, ""}, + {"(*Float).Uint64", Method, 5, ""}, + {"(*Float).UnmarshalText", Method, 6, ""}, + {"(*Int).Abs", Method, 0, ""}, + {"(*Int).Add", Method, 0, ""}, + {"(*Int).And", Method, 0, ""}, + {"(*Int).AndNot", Method, 0, ""}, + {"(*Int).Append", Method, 6, ""}, + {"(*Int).AppendText", Method, 24, ""}, + {"(*Int).Binomial", Method, 0, ""}, + {"(*Int).Bit", Method, 0, ""}, + {"(*Int).BitLen", Method, 0, ""}, + {"(*Int).Bits", Method, 0, ""}, + {"(*Int).Bytes", Method, 0, ""}, + {"(*Int).Cmp", Method, 0, ""}, + {"(*Int).CmpAbs", Method, 10, ""}, + {"(*Int).Div", Method, 0, ""}, + {"(*Int).DivMod", Method, 0, ""}, + {"(*Int).Exp", Method, 0, ""}, + {"(*Int).FillBytes", Method, 15, ""}, + {"(*Int).Float64", Method, 21, ""}, + {"(*Int).Format", Method, 0, ""}, + {"(*Int).GCD", Method, 0, ""}, + {"(*Int).GobDecode", Method, 0, ""}, + {"(*Int).GobEncode", Method, 0, ""}, + {"(*Int).Int64", Method, 0, ""}, + {"(*Int).IsInt64", Method, 9, ""}, + {"(*Int).IsUint64", Method, 9, ""}, + {"(*Int).Lsh", Method, 0, ""}, + {"(*Int).MarshalJSON", Method, 1, ""}, + {"(*Int).MarshalText", Method, 3, ""}, + {"(*Int).Mod", Method, 0, ""}, + {"(*Int).ModInverse", Method, 0, ""}, + {"(*Int).ModSqrt", Method, 5, ""}, + {"(*Int).Mul", Method, 0, ""}, + {"(*Int).MulRange", Method, 0, ""}, + {"(*Int).Neg", Method, 0, ""}, + {"(*Int).Not", Method, 0, ""}, + {"(*Int).Or", Method, 0, ""}, + {"(*Int).ProbablyPrime", Method, 0, ""}, + {"(*Int).Quo", Method, 0, ""}, + {"(*Int).QuoRem", Method, 0, ""}, + {"(*Int).Rand", Method, 0, ""}, + {"(*Int).Rem", Method, 0, ""}, + {"(*Int).Rsh", Method, 0, ""}, + {"(*Int).Scan", Method, 0, ""}, + {"(*Int).Set", Method, 0, ""}, + {"(*Int).SetBit", Method, 0, ""}, + {"(*Int).SetBits", Method, 0, ""}, + {"(*Int).SetBytes", Method, 0, ""}, + {"(*Int).SetInt64", Method, 0, ""}, + {"(*Int).SetString", Method, 0, ""}, + {"(*Int).SetUint64", Method, 1, ""}, + {"(*Int).Sign", Method, 0, ""}, + {"(*Int).Sqrt", Method, 8, ""}, + {"(*Int).String", Method, 0, ""}, + {"(*Int).Sub", Method, 0, ""}, + {"(*Int).Text", Method, 6, ""}, + {"(*Int).TrailingZeroBits", Method, 13, ""}, + {"(*Int).Uint64", Method, 1, ""}, + {"(*Int).UnmarshalJSON", Method, 1, ""}, + {"(*Int).UnmarshalText", Method, 3, ""}, + {"(*Int).Xor", Method, 0, ""}, + {"(*Rat).Abs", Method, 0, ""}, + {"(*Rat).Add", Method, 0, ""}, + {"(*Rat).AppendText", Method, 24, ""}, + {"(*Rat).Cmp", Method, 0, ""}, + {"(*Rat).Denom", Method, 0, ""}, + {"(*Rat).Float32", Method, 4, ""}, + {"(*Rat).Float64", Method, 1, ""}, + {"(*Rat).FloatPrec", Method, 22, ""}, + {"(*Rat).FloatString", Method, 0, ""}, + {"(*Rat).GobDecode", Method, 0, ""}, + {"(*Rat).GobEncode", Method, 0, ""}, + {"(*Rat).Inv", Method, 0, ""}, + {"(*Rat).IsInt", Method, 0, ""}, + {"(*Rat).MarshalText", Method, 3, ""}, + {"(*Rat).Mul", Method, 0, ""}, + {"(*Rat).Neg", Method, 0, ""}, + {"(*Rat).Num", Method, 0, ""}, + {"(*Rat).Quo", Method, 0, ""}, + {"(*Rat).RatString", Method, 0, ""}, + {"(*Rat).Scan", Method, 0, ""}, + {"(*Rat).Set", Method, 0, ""}, + {"(*Rat).SetFloat64", Method, 1, ""}, + {"(*Rat).SetFrac", Method, 0, ""}, + {"(*Rat).SetFrac64", Method, 0, ""}, + {"(*Rat).SetInt", Method, 0, ""}, + {"(*Rat).SetInt64", Method, 0, ""}, + {"(*Rat).SetString", Method, 0, ""}, + {"(*Rat).SetUint64", Method, 13, ""}, + {"(*Rat).Sign", Method, 0, ""}, + {"(*Rat).String", Method, 0, ""}, + {"(*Rat).Sub", Method, 0, ""}, + {"(*Rat).UnmarshalText", Method, 3, ""}, + {"(Accuracy).String", Method, 5, ""}, + {"(ErrNaN).Error", Method, 5, ""}, + {"(RoundingMode).String", Method, 5, ""}, + {"Above", Const, 5, ""}, + {"Accuracy", Type, 5, ""}, + {"AwayFromZero", Const, 5, ""}, + {"Below", Const, 5, ""}, + {"ErrNaN", Type, 5, ""}, + {"Exact", Const, 5, ""}, + {"Float", Type, 5, ""}, + {"Int", Type, 0, ""}, + {"Jacobi", Func, 5, "func(x *Int, y *Int) int"}, + {"MaxBase", Const, 0, ""}, + {"MaxExp", Const, 5, ""}, + {"MaxPrec", Const, 5, ""}, + {"MinExp", Const, 5, ""}, + {"NewFloat", Func, 5, "func(x float64) *Float"}, + {"NewInt", Func, 0, "func(x int64) *Int"}, + {"NewRat", Func, 0, "func(a int64, b int64) *Rat"}, + {"ParseFloat", Func, 5, "func(s string, base int, prec uint, mode RoundingMode) (f *Float, b int, err error)"}, + {"Rat", Type, 0, ""}, + {"RoundingMode", Type, 5, ""}, + {"ToNearestAway", Const, 5, ""}, + {"ToNearestEven", Const, 5, ""}, + {"ToNegativeInf", Const, 5, ""}, + {"ToPositiveInf", Const, 5, ""}, + {"ToZero", Const, 5, ""}, + {"Word", Type, 0, ""}, }, "math/bits": { - {"Add", Func, 12}, - {"Add32", Func, 12}, - {"Add64", Func, 12}, - {"Div", Func, 12}, - {"Div32", Func, 12}, - {"Div64", Func, 12}, - {"LeadingZeros", Func, 9}, - {"LeadingZeros16", Func, 9}, - {"LeadingZeros32", Func, 9}, - {"LeadingZeros64", Func, 9}, - {"LeadingZeros8", Func, 9}, - {"Len", Func, 9}, - {"Len16", Func, 9}, - {"Len32", Func, 9}, - {"Len64", Func, 9}, - {"Len8", Func, 9}, - {"Mul", Func, 12}, - {"Mul32", Func, 12}, - {"Mul64", Func, 12}, - {"OnesCount", Func, 9}, - {"OnesCount16", Func, 9}, - {"OnesCount32", Func, 9}, - {"OnesCount64", Func, 9}, - {"OnesCount8", Func, 9}, - {"Rem", Func, 14}, - {"Rem32", Func, 14}, - {"Rem64", Func, 14}, - {"Reverse", Func, 9}, - {"Reverse16", Func, 9}, - {"Reverse32", Func, 9}, - {"Reverse64", Func, 9}, - {"Reverse8", Func, 9}, - {"ReverseBytes", Func, 9}, - {"ReverseBytes16", Func, 9}, - {"ReverseBytes32", Func, 9}, - {"ReverseBytes64", Func, 9}, - {"RotateLeft", Func, 9}, - {"RotateLeft16", Func, 9}, - {"RotateLeft32", Func, 9}, - {"RotateLeft64", Func, 9}, - {"RotateLeft8", Func, 9}, - {"Sub", Func, 12}, - {"Sub32", Func, 12}, - {"Sub64", Func, 12}, - {"TrailingZeros", Func, 9}, - {"TrailingZeros16", Func, 9}, - {"TrailingZeros32", Func, 9}, - {"TrailingZeros64", Func, 9}, - {"TrailingZeros8", Func, 9}, - {"UintSize", Const, 9}, + {"Add", Func, 12, "func(x uint, y uint, carry uint) (sum uint, carryOut uint)"}, + {"Add32", Func, 12, "func(x uint32, y uint32, carry uint32) (sum uint32, carryOut uint32)"}, + {"Add64", Func, 12, "func(x uint64, y uint64, carry uint64) (sum uint64, carryOut uint64)"}, + {"Div", Func, 12, "func(hi uint, lo uint, y uint) (quo uint, rem uint)"}, + {"Div32", Func, 12, "func(hi uint32, lo uint32, y uint32) (quo uint32, rem uint32)"}, + {"Div64", Func, 12, "func(hi uint64, lo uint64, y uint64) (quo uint64, rem uint64)"}, + {"LeadingZeros", Func, 9, "func(x uint) int"}, + {"LeadingZeros16", Func, 9, "func(x uint16) int"}, + {"LeadingZeros32", Func, 9, "func(x uint32) int"}, + {"LeadingZeros64", Func, 9, "func(x uint64) int"}, + {"LeadingZeros8", Func, 9, "func(x uint8) int"}, + {"Len", Func, 9, "func(x uint) int"}, + {"Len16", Func, 9, "func(x uint16) (n int)"}, + {"Len32", Func, 9, "func(x uint32) (n int)"}, + {"Len64", Func, 9, "func(x uint64) (n int)"}, + {"Len8", Func, 9, "func(x uint8) int"}, + {"Mul", Func, 12, "func(x uint, y uint) (hi uint, lo uint)"}, + {"Mul32", Func, 12, "func(x uint32, y uint32) (hi uint32, lo uint32)"}, + {"Mul64", Func, 12, "func(x uint64, y uint64) (hi uint64, lo uint64)"}, + {"OnesCount", Func, 9, "func(x uint) int"}, + {"OnesCount16", Func, 9, "func(x uint16) int"}, + {"OnesCount32", Func, 9, "func(x uint32) int"}, + {"OnesCount64", Func, 9, "func(x uint64) int"}, + {"OnesCount8", Func, 9, "func(x uint8) int"}, + {"Rem", Func, 14, "func(hi uint, lo uint, y uint) uint"}, + {"Rem32", Func, 14, "func(hi uint32, lo uint32, y uint32) uint32"}, + {"Rem64", Func, 14, "func(hi uint64, lo uint64, y uint64) uint64"}, + {"Reverse", Func, 9, "func(x uint) uint"}, + {"Reverse16", Func, 9, "func(x uint16) uint16"}, + {"Reverse32", Func, 9, "func(x uint32) uint32"}, + {"Reverse64", Func, 9, "func(x uint64) uint64"}, + {"Reverse8", Func, 9, "func(x uint8) uint8"}, + {"ReverseBytes", Func, 9, "func(x uint) uint"}, + {"ReverseBytes16", Func, 9, "func(x uint16) uint16"}, + {"ReverseBytes32", Func, 9, "func(x uint32) uint32"}, + {"ReverseBytes64", Func, 9, "func(x uint64) uint64"}, + {"RotateLeft", Func, 9, "func(x uint, k int) uint"}, + {"RotateLeft16", Func, 9, "func(x uint16, k int) uint16"}, + {"RotateLeft32", Func, 9, "func(x uint32, k int) uint32"}, + {"RotateLeft64", Func, 9, "func(x uint64, k int) uint64"}, + {"RotateLeft8", Func, 9, "func(x uint8, k int) uint8"}, + {"Sub", Func, 12, "func(x uint, y uint, borrow uint) (diff uint, borrowOut uint)"}, + {"Sub32", Func, 12, "func(x uint32, y uint32, borrow uint32) (diff uint32, borrowOut uint32)"}, + {"Sub64", Func, 12, "func(x uint64, y uint64, borrow uint64) (diff uint64, borrowOut uint64)"}, + {"TrailingZeros", Func, 9, "func(x uint) int"}, + {"TrailingZeros16", Func, 9, "func(x uint16) int"}, + {"TrailingZeros32", Func, 9, "func(x uint32) int"}, + {"TrailingZeros64", Func, 9, "func(x uint64) int"}, + {"TrailingZeros8", Func, 9, "func(x uint8) int"}, + {"UintSize", Const, 9, ""}, }, "math/cmplx": { - {"Abs", Func, 0}, - {"Acos", Func, 0}, - {"Acosh", Func, 0}, - {"Asin", Func, 0}, - {"Asinh", Func, 0}, - {"Atan", Func, 0}, - {"Atanh", Func, 0}, - {"Conj", Func, 0}, - {"Cos", Func, 0}, - {"Cosh", Func, 0}, - {"Cot", Func, 0}, - {"Exp", Func, 0}, - {"Inf", Func, 0}, - {"IsInf", Func, 0}, - {"IsNaN", Func, 0}, - {"Log", Func, 0}, - {"Log10", Func, 0}, - {"NaN", Func, 0}, - {"Phase", Func, 0}, - {"Polar", Func, 0}, - {"Pow", Func, 0}, - {"Rect", Func, 0}, - {"Sin", Func, 0}, - {"Sinh", Func, 0}, - {"Sqrt", Func, 0}, - {"Tan", Func, 0}, - {"Tanh", Func, 0}, + {"Abs", Func, 0, "func(x complex128) float64"}, + {"Acos", Func, 0, "func(x complex128) complex128"}, + {"Acosh", Func, 0, "func(x complex128) complex128"}, + {"Asin", Func, 0, "func(x complex128) complex128"}, + {"Asinh", Func, 0, "func(x complex128) complex128"}, + {"Atan", Func, 0, "func(x complex128) complex128"}, + {"Atanh", Func, 0, "func(x complex128) complex128"}, + {"Conj", Func, 0, "func(x complex128) complex128"}, + {"Cos", Func, 0, "func(x complex128) complex128"}, + {"Cosh", Func, 0, "func(x complex128) complex128"}, + {"Cot", Func, 0, "func(x complex128) complex128"}, + {"Exp", Func, 0, "func(x complex128) complex128"}, + {"Inf", Func, 0, "func() complex128"}, + {"IsInf", Func, 0, "func(x complex128) bool"}, + {"IsNaN", Func, 0, "func(x complex128) bool"}, + {"Log", Func, 0, "func(x complex128) complex128"}, + {"Log10", Func, 0, "func(x complex128) complex128"}, + {"NaN", Func, 0, "func() complex128"}, + {"Phase", Func, 0, "func(x complex128) float64"}, + {"Polar", Func, 0, "func(x complex128) (r float64, θ float64)"}, + {"Pow", Func, 0, "func(x complex128, y complex128) complex128"}, + {"Rect", Func, 0, "func(r float64, θ float64) complex128"}, + {"Sin", Func, 0, "func(x complex128) complex128"}, + {"Sinh", Func, 0, "func(x complex128) complex128"}, + {"Sqrt", Func, 0, "func(x complex128) complex128"}, + {"Tan", Func, 0, "func(x complex128) complex128"}, + {"Tanh", Func, 0, "func(x complex128) complex128"}, }, "math/rand": { - {"(*Rand).ExpFloat64", Method, 0}, - {"(*Rand).Float32", Method, 0}, - {"(*Rand).Float64", Method, 0}, - {"(*Rand).Int", Method, 0}, - {"(*Rand).Int31", Method, 0}, - {"(*Rand).Int31n", Method, 0}, - {"(*Rand).Int63", Method, 0}, - {"(*Rand).Int63n", Method, 0}, - {"(*Rand).Intn", Method, 0}, - {"(*Rand).NormFloat64", Method, 0}, - {"(*Rand).Perm", Method, 0}, - {"(*Rand).Read", Method, 6}, - {"(*Rand).Seed", Method, 0}, - {"(*Rand).Shuffle", Method, 10}, - {"(*Rand).Uint32", Method, 0}, - {"(*Rand).Uint64", Method, 8}, - {"(*Zipf).Uint64", Method, 0}, - {"ExpFloat64", Func, 0}, - {"Float32", Func, 0}, - {"Float64", Func, 0}, - {"Int", Func, 0}, - {"Int31", Func, 0}, - {"Int31n", Func, 0}, - {"Int63", Func, 0}, - {"Int63n", Func, 0}, - {"Intn", Func, 0}, - {"New", Func, 0}, - {"NewSource", Func, 0}, - {"NewZipf", Func, 0}, - {"NormFloat64", Func, 0}, - {"Perm", Func, 0}, - {"Rand", Type, 0}, - {"Read", Func, 6}, - {"Seed", Func, 0}, - {"Shuffle", Func, 10}, - {"Source", Type, 0}, - {"Source64", Type, 8}, - {"Uint32", Func, 0}, - {"Uint64", Func, 8}, - {"Zipf", Type, 0}, + {"(*Rand).ExpFloat64", Method, 0, ""}, + {"(*Rand).Float32", Method, 0, ""}, + {"(*Rand).Float64", Method, 0, ""}, + {"(*Rand).Int", Method, 0, ""}, + {"(*Rand).Int31", Method, 0, ""}, + {"(*Rand).Int31n", Method, 0, ""}, + {"(*Rand).Int63", Method, 0, ""}, + {"(*Rand).Int63n", Method, 0, ""}, + {"(*Rand).Intn", Method, 0, ""}, + {"(*Rand).NormFloat64", Method, 0, ""}, + {"(*Rand).Perm", Method, 0, ""}, + {"(*Rand).Read", Method, 6, ""}, + {"(*Rand).Seed", Method, 0, ""}, + {"(*Rand).Shuffle", Method, 10, ""}, + {"(*Rand).Uint32", Method, 0, ""}, + {"(*Rand).Uint64", Method, 8, ""}, + {"(*Zipf).Uint64", Method, 0, ""}, + {"ExpFloat64", Func, 0, "func() float64"}, + {"Float32", Func, 0, "func() float32"}, + {"Float64", Func, 0, "func() float64"}, + {"Int", Func, 0, "func() int"}, + {"Int31", Func, 0, "func() int32"}, + {"Int31n", Func, 0, "func(n int32) int32"}, + {"Int63", Func, 0, "func() int64"}, + {"Int63n", Func, 0, "func(n int64) int64"}, + {"Intn", Func, 0, "func(n int) int"}, + {"New", Func, 0, "func(src Source) *Rand"}, + {"NewSource", Func, 0, "func(seed int64) Source"}, + {"NewZipf", Func, 0, "func(r *Rand, s float64, v float64, imax uint64) *Zipf"}, + {"NormFloat64", Func, 0, "func() float64"}, + {"Perm", Func, 0, "func(n int) []int"}, + {"Rand", Type, 0, ""}, + {"Read", Func, 6, "func(p []byte) (n int, err error)"}, + {"Seed", Func, 0, "func(seed int64)"}, + {"Shuffle", Func, 10, "func(n int, swap func(i int, j int))"}, + {"Source", Type, 0, ""}, + {"Source64", Type, 8, ""}, + {"Uint32", Func, 0, "func() uint32"}, + {"Uint64", Func, 8, "func() uint64"}, + {"Zipf", Type, 0, ""}, }, "math/rand/v2": { - {"(*ChaCha8).AppendBinary", Method, 24}, - {"(*ChaCha8).MarshalBinary", Method, 22}, - {"(*ChaCha8).Read", Method, 23}, - {"(*ChaCha8).Seed", Method, 22}, - {"(*ChaCha8).Uint64", Method, 22}, - {"(*ChaCha8).UnmarshalBinary", Method, 22}, - {"(*PCG).AppendBinary", Method, 24}, - {"(*PCG).MarshalBinary", Method, 22}, - {"(*PCG).Seed", Method, 22}, - {"(*PCG).Uint64", Method, 22}, - {"(*PCG).UnmarshalBinary", Method, 22}, - {"(*Rand).ExpFloat64", Method, 22}, - {"(*Rand).Float32", Method, 22}, - {"(*Rand).Float64", Method, 22}, - {"(*Rand).Int", Method, 22}, - {"(*Rand).Int32", Method, 22}, - {"(*Rand).Int32N", Method, 22}, - {"(*Rand).Int64", Method, 22}, - {"(*Rand).Int64N", Method, 22}, - {"(*Rand).IntN", Method, 22}, - {"(*Rand).NormFloat64", Method, 22}, - {"(*Rand).Perm", Method, 22}, - {"(*Rand).Shuffle", Method, 22}, - {"(*Rand).Uint", Method, 23}, - {"(*Rand).Uint32", Method, 22}, - {"(*Rand).Uint32N", Method, 22}, - {"(*Rand).Uint64", Method, 22}, - {"(*Rand).Uint64N", Method, 22}, - {"(*Rand).UintN", Method, 22}, - {"(*Zipf).Uint64", Method, 22}, - {"ChaCha8", Type, 22}, - {"ExpFloat64", Func, 22}, - {"Float32", Func, 22}, - {"Float64", Func, 22}, - {"Int", Func, 22}, - {"Int32", Func, 22}, - {"Int32N", Func, 22}, - {"Int64", Func, 22}, - {"Int64N", Func, 22}, - {"IntN", Func, 22}, - {"N", Func, 22}, - {"New", Func, 22}, - {"NewChaCha8", Func, 22}, - {"NewPCG", Func, 22}, - {"NewZipf", Func, 22}, - {"NormFloat64", Func, 22}, - {"PCG", Type, 22}, - {"Perm", Func, 22}, - {"Rand", Type, 22}, - {"Shuffle", Func, 22}, - {"Source", Type, 22}, - {"Uint", Func, 23}, - {"Uint32", Func, 22}, - {"Uint32N", Func, 22}, - {"Uint64", Func, 22}, - {"Uint64N", Func, 22}, - {"UintN", Func, 22}, - {"Zipf", Type, 22}, + {"(*ChaCha8).AppendBinary", Method, 24, ""}, + {"(*ChaCha8).MarshalBinary", Method, 22, ""}, + {"(*ChaCha8).Read", Method, 23, ""}, + {"(*ChaCha8).Seed", Method, 22, ""}, + {"(*ChaCha8).Uint64", Method, 22, ""}, + {"(*ChaCha8).UnmarshalBinary", Method, 22, ""}, + {"(*PCG).AppendBinary", Method, 24, ""}, + {"(*PCG).MarshalBinary", Method, 22, ""}, + {"(*PCG).Seed", Method, 22, ""}, + {"(*PCG).Uint64", Method, 22, ""}, + {"(*PCG).UnmarshalBinary", Method, 22, ""}, + {"(*Rand).ExpFloat64", Method, 22, ""}, + {"(*Rand).Float32", Method, 22, ""}, + {"(*Rand).Float64", Method, 22, ""}, + {"(*Rand).Int", Method, 22, ""}, + {"(*Rand).Int32", Method, 22, ""}, + {"(*Rand).Int32N", Method, 22, ""}, + {"(*Rand).Int64", Method, 22, ""}, + {"(*Rand).Int64N", Method, 22, ""}, + {"(*Rand).IntN", Method, 22, ""}, + {"(*Rand).NormFloat64", Method, 22, ""}, + {"(*Rand).Perm", Method, 22, ""}, + {"(*Rand).Shuffle", Method, 22, ""}, + {"(*Rand).Uint", Method, 23, ""}, + {"(*Rand).Uint32", Method, 22, ""}, + {"(*Rand).Uint32N", Method, 22, ""}, + {"(*Rand).Uint64", Method, 22, ""}, + {"(*Rand).Uint64N", Method, 22, ""}, + {"(*Rand).UintN", Method, 22, ""}, + {"(*Zipf).Uint64", Method, 22, ""}, + {"ChaCha8", Type, 22, ""}, + {"ExpFloat64", Func, 22, "func() float64"}, + {"Float32", Func, 22, "func() float32"}, + {"Float64", Func, 22, "func() float64"}, + {"Int", Func, 22, "func() int"}, + {"Int32", Func, 22, "func() int32"}, + {"Int32N", Func, 22, "func(n int32) int32"}, + {"Int64", Func, 22, "func() int64"}, + {"Int64N", Func, 22, "func(n int64) int64"}, + {"IntN", Func, 22, "func(n int) int"}, + {"N", Func, 22, "func[Int intType](n Int) Int"}, + {"New", Func, 22, "func(src Source) *Rand"}, + {"NewChaCha8", Func, 22, "func(seed [32]byte) *ChaCha8"}, + {"NewPCG", Func, 22, "func(seed1 uint64, seed2 uint64) *PCG"}, + {"NewZipf", Func, 22, "func(r *Rand, s float64, v float64, imax uint64) *Zipf"}, + {"NormFloat64", Func, 22, "func() float64"}, + {"PCG", Type, 22, ""}, + {"Perm", Func, 22, "func(n int) []int"}, + {"Rand", Type, 22, ""}, + {"Shuffle", Func, 22, "func(n int, swap func(i int, j int))"}, + {"Source", Type, 22, ""}, + {"Uint", Func, 23, "func() uint"}, + {"Uint32", Func, 22, "func() uint32"}, + {"Uint32N", Func, 22, "func(n uint32) uint32"}, + {"Uint64", Func, 22, "func() uint64"}, + {"Uint64N", Func, 22, "func(n uint64) uint64"}, + {"UintN", Func, 22, "func(n uint) uint"}, + {"Zipf", Type, 22, ""}, }, "mime": { - {"(*WordDecoder).Decode", Method, 5}, - {"(*WordDecoder).DecodeHeader", Method, 5}, - {"(WordEncoder).Encode", Method, 5}, - {"AddExtensionType", Func, 0}, - {"BEncoding", Const, 5}, - {"ErrInvalidMediaParameter", Var, 9}, - {"ExtensionsByType", Func, 5}, - {"FormatMediaType", Func, 0}, - {"ParseMediaType", Func, 0}, - {"QEncoding", Const, 5}, - {"TypeByExtension", Func, 0}, - {"WordDecoder", Type, 5}, - {"WordDecoder.CharsetReader", Field, 5}, - {"WordEncoder", Type, 5}, + {"(*WordDecoder).Decode", Method, 5, ""}, + {"(*WordDecoder).DecodeHeader", Method, 5, ""}, + {"(WordEncoder).Encode", Method, 5, ""}, + {"AddExtensionType", Func, 0, "func(ext string, typ string) error"}, + {"BEncoding", Const, 5, ""}, + {"ErrInvalidMediaParameter", Var, 9, ""}, + {"ExtensionsByType", Func, 5, "func(typ string) ([]string, error)"}, + {"FormatMediaType", Func, 0, "func(t string, param map[string]string) string"}, + {"ParseMediaType", Func, 0, "func(v string) (mediatype string, params map[string]string, err error)"}, + {"QEncoding", Const, 5, ""}, + {"TypeByExtension", Func, 0, "func(ext string) string"}, + {"WordDecoder", Type, 5, ""}, + {"WordDecoder.CharsetReader", Field, 5, ""}, + {"WordEncoder", Type, 5, ""}, }, "mime/multipart": { - {"(*FileHeader).Open", Method, 0}, - {"(*Form).RemoveAll", Method, 0}, - {"(*Part).Close", Method, 0}, - {"(*Part).FileName", Method, 0}, - {"(*Part).FormName", Method, 0}, - {"(*Part).Read", Method, 0}, - {"(*Reader).NextPart", Method, 0}, - {"(*Reader).NextRawPart", Method, 14}, - {"(*Reader).ReadForm", Method, 0}, - {"(*Writer).Boundary", Method, 0}, - {"(*Writer).Close", Method, 0}, - {"(*Writer).CreateFormField", Method, 0}, - {"(*Writer).CreateFormFile", Method, 0}, - {"(*Writer).CreatePart", Method, 0}, - {"(*Writer).FormDataContentType", Method, 0}, - {"(*Writer).SetBoundary", Method, 1}, - {"(*Writer).WriteField", Method, 0}, - {"ErrMessageTooLarge", Var, 9}, - {"File", Type, 0}, - {"FileContentDisposition", Func, 25}, - {"FileHeader", Type, 0}, - {"FileHeader.Filename", Field, 0}, - {"FileHeader.Header", Field, 0}, - {"FileHeader.Size", Field, 9}, - {"Form", Type, 0}, - {"Form.File", Field, 0}, - {"Form.Value", Field, 0}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"Part", Type, 0}, - {"Part.Header", Field, 0}, - {"Reader", Type, 0}, - {"Writer", Type, 0}, + {"(*FileHeader).Open", Method, 0, ""}, + {"(*Form).RemoveAll", Method, 0, ""}, + {"(*Part).Close", Method, 0, ""}, + {"(*Part).FileName", Method, 0, ""}, + {"(*Part).FormName", Method, 0, ""}, + {"(*Part).Read", Method, 0, ""}, + {"(*Reader).NextPart", Method, 0, ""}, + {"(*Reader).NextRawPart", Method, 14, ""}, + {"(*Reader).ReadForm", Method, 0, ""}, + {"(*Writer).Boundary", Method, 0, ""}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).CreateFormField", Method, 0, ""}, + {"(*Writer).CreateFormFile", Method, 0, ""}, + {"(*Writer).CreatePart", Method, 0, ""}, + {"(*Writer).FormDataContentType", Method, 0, ""}, + {"(*Writer).SetBoundary", Method, 1, ""}, + {"(*Writer).WriteField", Method, 0, ""}, + {"ErrMessageTooLarge", Var, 9, ""}, + {"File", Type, 0, ""}, + {"FileContentDisposition", Func, 25, ""}, + {"FileHeader", Type, 0, ""}, + {"FileHeader.Filename", Field, 0, ""}, + {"FileHeader.Header", Field, 0, ""}, + {"FileHeader.Size", Field, 9, ""}, + {"Form", Type, 0, ""}, + {"Form.File", Field, 0, ""}, + {"Form.Value", Field, 0, ""}, + {"NewReader", Func, 0, "func(r io.Reader, boundary string) *Reader"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"Part", Type, 0, ""}, + {"Part.Header", Field, 0, ""}, + {"Reader", Type, 0, ""}, + {"Writer", Type, 0, ""}, }, "mime/quotedprintable": { - {"(*Reader).Read", Method, 5}, - {"(*Writer).Close", Method, 5}, - {"(*Writer).Write", Method, 5}, - {"NewReader", Func, 5}, - {"NewWriter", Func, 5}, - {"Reader", Type, 5}, - {"Writer", Type, 5}, - {"Writer.Binary", Field, 5}, + {"(*Reader).Read", Method, 5, ""}, + {"(*Writer).Close", Method, 5, ""}, + {"(*Writer).Write", Method, 5, ""}, + {"NewReader", Func, 5, "func(r io.Reader) *Reader"}, + {"NewWriter", Func, 5, "func(w io.Writer) *Writer"}, + {"Reader", Type, 5, ""}, + {"Writer", Type, 5, ""}, + {"Writer.Binary", Field, 5, ""}, }, "net": { - {"(*AddrError).Error", Method, 0}, - {"(*AddrError).Temporary", Method, 0}, - {"(*AddrError).Timeout", Method, 0}, - {"(*Buffers).Read", Method, 8}, - {"(*Buffers).WriteTo", Method, 8}, - {"(*DNSConfigError).Error", Method, 0}, - {"(*DNSConfigError).Temporary", Method, 0}, - {"(*DNSConfigError).Timeout", Method, 0}, - {"(*DNSConfigError).Unwrap", Method, 13}, - {"(*DNSError).Error", Method, 0}, - {"(*DNSError).Temporary", Method, 0}, - {"(*DNSError).Timeout", Method, 0}, - {"(*DNSError).Unwrap", Method, 23}, - {"(*Dialer).Dial", Method, 1}, - {"(*Dialer).DialContext", Method, 7}, - {"(*Dialer).MultipathTCP", Method, 21}, - {"(*Dialer).SetMultipathTCP", Method, 21}, - {"(*IP).UnmarshalText", Method, 2}, - {"(*IPAddr).Network", Method, 0}, - {"(*IPAddr).String", Method, 0}, - {"(*IPConn).Close", Method, 0}, - {"(*IPConn).File", Method, 0}, - {"(*IPConn).LocalAddr", Method, 0}, - {"(*IPConn).Read", Method, 0}, - {"(*IPConn).ReadFrom", Method, 0}, - {"(*IPConn).ReadFromIP", Method, 0}, - {"(*IPConn).ReadMsgIP", Method, 1}, - {"(*IPConn).RemoteAddr", Method, 0}, - {"(*IPConn).SetDeadline", Method, 0}, - {"(*IPConn).SetReadBuffer", Method, 0}, - {"(*IPConn).SetReadDeadline", Method, 0}, - {"(*IPConn).SetWriteBuffer", Method, 0}, - {"(*IPConn).SetWriteDeadline", Method, 0}, - {"(*IPConn).SyscallConn", Method, 9}, - {"(*IPConn).Write", Method, 0}, - {"(*IPConn).WriteMsgIP", Method, 1}, - {"(*IPConn).WriteTo", Method, 0}, - {"(*IPConn).WriteToIP", Method, 0}, - {"(*IPNet).Contains", Method, 0}, - {"(*IPNet).Network", Method, 0}, - {"(*IPNet).String", Method, 0}, - {"(*Interface).Addrs", Method, 0}, - {"(*Interface).MulticastAddrs", Method, 0}, - {"(*ListenConfig).Listen", Method, 11}, - {"(*ListenConfig).ListenPacket", Method, 11}, - {"(*ListenConfig).MultipathTCP", Method, 21}, - {"(*ListenConfig).SetMultipathTCP", Method, 21}, - {"(*OpError).Error", Method, 0}, - {"(*OpError).Temporary", Method, 0}, - {"(*OpError).Timeout", Method, 0}, - {"(*OpError).Unwrap", Method, 13}, - {"(*ParseError).Error", Method, 0}, - {"(*ParseError).Temporary", Method, 17}, - {"(*ParseError).Timeout", Method, 17}, - {"(*Resolver).LookupAddr", Method, 8}, - {"(*Resolver).LookupCNAME", Method, 8}, - {"(*Resolver).LookupHost", Method, 8}, - {"(*Resolver).LookupIP", Method, 15}, - {"(*Resolver).LookupIPAddr", Method, 8}, - {"(*Resolver).LookupMX", Method, 8}, - {"(*Resolver).LookupNS", Method, 8}, - {"(*Resolver).LookupNetIP", Method, 18}, - {"(*Resolver).LookupPort", Method, 8}, - {"(*Resolver).LookupSRV", Method, 8}, - {"(*Resolver).LookupTXT", Method, 8}, - {"(*TCPAddr).AddrPort", Method, 18}, - {"(*TCPAddr).Network", Method, 0}, - {"(*TCPAddr).String", Method, 0}, - {"(*TCPConn).Close", Method, 0}, - {"(*TCPConn).CloseRead", Method, 0}, - {"(*TCPConn).CloseWrite", Method, 0}, - {"(*TCPConn).File", Method, 0}, - {"(*TCPConn).LocalAddr", Method, 0}, - {"(*TCPConn).MultipathTCP", Method, 21}, - {"(*TCPConn).Read", Method, 0}, - {"(*TCPConn).ReadFrom", Method, 0}, - {"(*TCPConn).RemoteAddr", Method, 0}, - {"(*TCPConn).SetDeadline", Method, 0}, - {"(*TCPConn).SetKeepAlive", Method, 0}, - {"(*TCPConn).SetKeepAliveConfig", Method, 23}, - {"(*TCPConn).SetKeepAlivePeriod", Method, 2}, - {"(*TCPConn).SetLinger", Method, 0}, - {"(*TCPConn).SetNoDelay", Method, 0}, - {"(*TCPConn).SetReadBuffer", Method, 0}, - {"(*TCPConn).SetReadDeadline", Method, 0}, - {"(*TCPConn).SetWriteBuffer", Method, 0}, - {"(*TCPConn).SetWriteDeadline", Method, 0}, - {"(*TCPConn).SyscallConn", Method, 9}, - {"(*TCPConn).Write", Method, 0}, - {"(*TCPConn).WriteTo", Method, 22}, - {"(*TCPListener).Accept", Method, 0}, - {"(*TCPListener).AcceptTCP", Method, 0}, - {"(*TCPListener).Addr", Method, 0}, - {"(*TCPListener).Close", Method, 0}, - {"(*TCPListener).File", Method, 0}, - {"(*TCPListener).SetDeadline", Method, 0}, - {"(*TCPListener).SyscallConn", Method, 10}, - {"(*UDPAddr).AddrPort", Method, 18}, - {"(*UDPAddr).Network", Method, 0}, - {"(*UDPAddr).String", Method, 0}, - {"(*UDPConn).Close", Method, 0}, - {"(*UDPConn).File", Method, 0}, - {"(*UDPConn).LocalAddr", Method, 0}, - {"(*UDPConn).Read", Method, 0}, - {"(*UDPConn).ReadFrom", Method, 0}, - {"(*UDPConn).ReadFromUDP", Method, 0}, - {"(*UDPConn).ReadFromUDPAddrPort", Method, 18}, - {"(*UDPConn).ReadMsgUDP", Method, 1}, - {"(*UDPConn).ReadMsgUDPAddrPort", Method, 18}, - {"(*UDPConn).RemoteAddr", Method, 0}, - {"(*UDPConn).SetDeadline", Method, 0}, - {"(*UDPConn).SetReadBuffer", Method, 0}, - {"(*UDPConn).SetReadDeadline", Method, 0}, - {"(*UDPConn).SetWriteBuffer", Method, 0}, - {"(*UDPConn).SetWriteDeadline", Method, 0}, - {"(*UDPConn).SyscallConn", Method, 9}, - {"(*UDPConn).Write", Method, 0}, - {"(*UDPConn).WriteMsgUDP", Method, 1}, - {"(*UDPConn).WriteMsgUDPAddrPort", Method, 18}, - {"(*UDPConn).WriteTo", Method, 0}, - {"(*UDPConn).WriteToUDP", Method, 0}, - {"(*UDPConn).WriteToUDPAddrPort", Method, 18}, - {"(*UnixAddr).Network", Method, 0}, - {"(*UnixAddr).String", Method, 0}, - {"(*UnixConn).Close", Method, 0}, - {"(*UnixConn).CloseRead", Method, 1}, - {"(*UnixConn).CloseWrite", Method, 1}, - {"(*UnixConn).File", Method, 0}, - {"(*UnixConn).LocalAddr", Method, 0}, - {"(*UnixConn).Read", Method, 0}, - {"(*UnixConn).ReadFrom", Method, 0}, - {"(*UnixConn).ReadFromUnix", Method, 0}, - {"(*UnixConn).ReadMsgUnix", Method, 0}, - {"(*UnixConn).RemoteAddr", Method, 0}, - {"(*UnixConn).SetDeadline", Method, 0}, - {"(*UnixConn).SetReadBuffer", Method, 0}, - {"(*UnixConn).SetReadDeadline", Method, 0}, - {"(*UnixConn).SetWriteBuffer", Method, 0}, - {"(*UnixConn).SetWriteDeadline", Method, 0}, - {"(*UnixConn).SyscallConn", Method, 9}, - {"(*UnixConn).Write", Method, 0}, - {"(*UnixConn).WriteMsgUnix", Method, 0}, - {"(*UnixConn).WriteTo", Method, 0}, - {"(*UnixConn).WriteToUnix", Method, 0}, - {"(*UnixListener).Accept", Method, 0}, - {"(*UnixListener).AcceptUnix", Method, 0}, - {"(*UnixListener).Addr", Method, 0}, - {"(*UnixListener).Close", Method, 0}, - {"(*UnixListener).File", Method, 0}, - {"(*UnixListener).SetDeadline", Method, 0}, - {"(*UnixListener).SetUnlinkOnClose", Method, 8}, - {"(*UnixListener).SyscallConn", Method, 10}, - {"(Flags).String", Method, 0}, - {"(HardwareAddr).String", Method, 0}, - {"(IP).AppendText", Method, 24}, - {"(IP).DefaultMask", Method, 0}, - {"(IP).Equal", Method, 0}, - {"(IP).IsGlobalUnicast", Method, 0}, - {"(IP).IsInterfaceLocalMulticast", Method, 0}, - {"(IP).IsLinkLocalMulticast", Method, 0}, - {"(IP).IsLinkLocalUnicast", Method, 0}, - {"(IP).IsLoopback", Method, 0}, - {"(IP).IsMulticast", Method, 0}, - {"(IP).IsPrivate", Method, 17}, - {"(IP).IsUnspecified", Method, 0}, - {"(IP).MarshalText", Method, 2}, - {"(IP).Mask", Method, 0}, - {"(IP).String", Method, 0}, - {"(IP).To16", Method, 0}, - {"(IP).To4", Method, 0}, - {"(IPMask).Size", Method, 0}, - {"(IPMask).String", Method, 0}, - {"(InvalidAddrError).Error", Method, 0}, - {"(InvalidAddrError).Temporary", Method, 0}, - {"(InvalidAddrError).Timeout", Method, 0}, - {"(UnknownNetworkError).Error", Method, 0}, - {"(UnknownNetworkError).Temporary", Method, 0}, - {"(UnknownNetworkError).Timeout", Method, 0}, - {"Addr", Type, 0}, - {"AddrError", Type, 0}, - {"AddrError.Addr", Field, 0}, - {"AddrError.Err", Field, 0}, - {"Buffers", Type, 8}, - {"CIDRMask", Func, 0}, - {"Conn", Type, 0}, - {"DNSConfigError", Type, 0}, - {"DNSConfigError.Err", Field, 0}, - {"DNSError", Type, 0}, - {"DNSError.Err", Field, 0}, - {"DNSError.IsNotFound", Field, 13}, - {"DNSError.IsTemporary", Field, 6}, - {"DNSError.IsTimeout", Field, 0}, - {"DNSError.Name", Field, 0}, - {"DNSError.Server", Field, 0}, - {"DNSError.UnwrapErr", Field, 23}, - {"DefaultResolver", Var, 8}, - {"Dial", Func, 0}, - {"DialIP", Func, 0}, - {"DialTCP", Func, 0}, - {"DialTimeout", Func, 0}, - {"DialUDP", Func, 0}, - {"DialUnix", Func, 0}, - {"Dialer", Type, 1}, - {"Dialer.Cancel", Field, 6}, - {"Dialer.Control", Field, 11}, - {"Dialer.ControlContext", Field, 20}, - {"Dialer.Deadline", Field, 1}, - {"Dialer.DualStack", Field, 2}, - {"Dialer.FallbackDelay", Field, 5}, - {"Dialer.KeepAlive", Field, 3}, - {"Dialer.KeepAliveConfig", Field, 23}, - {"Dialer.LocalAddr", Field, 1}, - {"Dialer.Resolver", Field, 8}, - {"Dialer.Timeout", Field, 1}, - {"ErrClosed", Var, 16}, - {"ErrWriteToConnected", Var, 0}, - {"Error", Type, 0}, - {"FileConn", Func, 0}, - {"FileListener", Func, 0}, - {"FilePacketConn", Func, 0}, - {"FlagBroadcast", Const, 0}, - {"FlagLoopback", Const, 0}, - {"FlagMulticast", Const, 0}, - {"FlagPointToPoint", Const, 0}, - {"FlagRunning", Const, 20}, - {"FlagUp", Const, 0}, - {"Flags", Type, 0}, - {"HardwareAddr", Type, 0}, - {"IP", Type, 0}, - {"IPAddr", Type, 0}, - {"IPAddr.IP", Field, 0}, - {"IPAddr.Zone", Field, 1}, - {"IPConn", Type, 0}, - {"IPMask", Type, 0}, - {"IPNet", Type, 0}, - {"IPNet.IP", Field, 0}, - {"IPNet.Mask", Field, 0}, - {"IPv4", Func, 0}, - {"IPv4Mask", Func, 0}, - {"IPv4allrouter", Var, 0}, - {"IPv4allsys", Var, 0}, - {"IPv4bcast", Var, 0}, - {"IPv4len", Const, 0}, - {"IPv4zero", Var, 0}, - {"IPv6interfacelocalallnodes", Var, 0}, - {"IPv6len", Const, 0}, - {"IPv6linklocalallnodes", Var, 0}, - {"IPv6linklocalallrouters", Var, 0}, - {"IPv6loopback", Var, 0}, - {"IPv6unspecified", Var, 0}, - {"IPv6zero", Var, 0}, - {"Interface", Type, 0}, - {"Interface.Flags", Field, 0}, - {"Interface.HardwareAddr", Field, 0}, - {"Interface.Index", Field, 0}, - {"Interface.MTU", Field, 0}, - {"Interface.Name", Field, 0}, - {"InterfaceAddrs", Func, 0}, - {"InterfaceByIndex", Func, 0}, - {"InterfaceByName", Func, 0}, - {"Interfaces", Func, 0}, - {"InvalidAddrError", Type, 0}, - {"JoinHostPort", Func, 0}, - {"KeepAliveConfig", Type, 23}, - {"KeepAliveConfig.Count", Field, 23}, - {"KeepAliveConfig.Enable", Field, 23}, - {"KeepAliveConfig.Idle", Field, 23}, - {"KeepAliveConfig.Interval", Field, 23}, - {"Listen", Func, 0}, - {"ListenConfig", Type, 11}, - {"ListenConfig.Control", Field, 11}, - {"ListenConfig.KeepAlive", Field, 13}, - {"ListenConfig.KeepAliveConfig", Field, 23}, - {"ListenIP", Func, 0}, - {"ListenMulticastUDP", Func, 0}, - {"ListenPacket", Func, 0}, - {"ListenTCP", Func, 0}, - {"ListenUDP", Func, 0}, - {"ListenUnix", Func, 0}, - {"ListenUnixgram", Func, 0}, - {"Listener", Type, 0}, - {"LookupAddr", Func, 0}, - {"LookupCNAME", Func, 0}, - {"LookupHost", Func, 0}, - {"LookupIP", Func, 0}, - {"LookupMX", Func, 0}, - {"LookupNS", Func, 1}, - {"LookupPort", Func, 0}, - {"LookupSRV", Func, 0}, - {"LookupTXT", Func, 0}, - {"MX", Type, 0}, - {"MX.Host", Field, 0}, - {"MX.Pref", Field, 0}, - {"NS", Type, 1}, - {"NS.Host", Field, 1}, - {"OpError", Type, 0}, - {"OpError.Addr", Field, 0}, - {"OpError.Err", Field, 0}, - {"OpError.Net", Field, 0}, - {"OpError.Op", Field, 0}, - {"OpError.Source", Field, 5}, - {"PacketConn", Type, 0}, - {"ParseCIDR", Func, 0}, - {"ParseError", Type, 0}, - {"ParseError.Text", Field, 0}, - {"ParseError.Type", Field, 0}, - {"ParseIP", Func, 0}, - {"ParseMAC", Func, 0}, - {"Pipe", Func, 0}, - {"ResolveIPAddr", Func, 0}, - {"ResolveTCPAddr", Func, 0}, - {"ResolveUDPAddr", Func, 0}, - {"ResolveUnixAddr", Func, 0}, - {"Resolver", Type, 8}, - {"Resolver.Dial", Field, 9}, - {"Resolver.PreferGo", Field, 8}, - {"Resolver.StrictErrors", Field, 9}, - {"SRV", Type, 0}, - {"SRV.Port", Field, 0}, - {"SRV.Priority", Field, 0}, - {"SRV.Target", Field, 0}, - {"SRV.Weight", Field, 0}, - {"SplitHostPort", Func, 0}, - {"TCPAddr", Type, 0}, - {"TCPAddr.IP", Field, 0}, - {"TCPAddr.Port", Field, 0}, - {"TCPAddr.Zone", Field, 1}, - {"TCPAddrFromAddrPort", Func, 18}, - {"TCPConn", Type, 0}, - {"TCPListener", Type, 0}, - {"UDPAddr", Type, 0}, - {"UDPAddr.IP", Field, 0}, - {"UDPAddr.Port", Field, 0}, - {"UDPAddr.Zone", Field, 1}, - {"UDPAddrFromAddrPort", Func, 18}, - {"UDPConn", Type, 0}, - {"UnixAddr", Type, 0}, - {"UnixAddr.Name", Field, 0}, - {"UnixAddr.Net", Field, 0}, - {"UnixConn", Type, 0}, - {"UnixListener", Type, 0}, - {"UnknownNetworkError", Type, 0}, + {"(*AddrError).Error", Method, 0, ""}, + {"(*AddrError).Temporary", Method, 0, ""}, + {"(*AddrError).Timeout", Method, 0, ""}, + {"(*Buffers).Read", Method, 8, ""}, + {"(*Buffers).WriteTo", Method, 8, ""}, + {"(*DNSConfigError).Error", Method, 0, ""}, + {"(*DNSConfigError).Temporary", Method, 0, ""}, + {"(*DNSConfigError).Timeout", Method, 0, ""}, + {"(*DNSConfigError).Unwrap", Method, 13, ""}, + {"(*DNSError).Error", Method, 0, ""}, + {"(*DNSError).Temporary", Method, 0, ""}, + {"(*DNSError).Timeout", Method, 0, ""}, + {"(*DNSError).Unwrap", Method, 23, ""}, + {"(*Dialer).Dial", Method, 1, ""}, + {"(*Dialer).DialContext", Method, 7, ""}, + {"(*Dialer).MultipathTCP", Method, 21, ""}, + {"(*Dialer).SetMultipathTCP", Method, 21, ""}, + {"(*IP).UnmarshalText", Method, 2, ""}, + {"(*IPAddr).Network", Method, 0, ""}, + {"(*IPAddr).String", Method, 0, ""}, + {"(*IPConn).Close", Method, 0, ""}, + {"(*IPConn).File", Method, 0, ""}, + {"(*IPConn).LocalAddr", Method, 0, ""}, + {"(*IPConn).Read", Method, 0, ""}, + {"(*IPConn).ReadFrom", Method, 0, ""}, + {"(*IPConn).ReadFromIP", Method, 0, ""}, + {"(*IPConn).ReadMsgIP", Method, 1, ""}, + {"(*IPConn).RemoteAddr", Method, 0, ""}, + {"(*IPConn).SetDeadline", Method, 0, ""}, + {"(*IPConn).SetReadBuffer", Method, 0, ""}, + {"(*IPConn).SetReadDeadline", Method, 0, ""}, + {"(*IPConn).SetWriteBuffer", Method, 0, ""}, + {"(*IPConn).SetWriteDeadline", Method, 0, ""}, + {"(*IPConn).SyscallConn", Method, 9, ""}, + {"(*IPConn).Write", Method, 0, ""}, + {"(*IPConn).WriteMsgIP", Method, 1, ""}, + {"(*IPConn).WriteTo", Method, 0, ""}, + {"(*IPConn).WriteToIP", Method, 0, ""}, + {"(*IPNet).Contains", Method, 0, ""}, + {"(*IPNet).Network", Method, 0, ""}, + {"(*IPNet).String", Method, 0, ""}, + {"(*Interface).Addrs", Method, 0, ""}, + {"(*Interface).MulticastAddrs", Method, 0, ""}, + {"(*ListenConfig).Listen", Method, 11, ""}, + {"(*ListenConfig).ListenPacket", Method, 11, ""}, + {"(*ListenConfig).MultipathTCP", Method, 21, ""}, + {"(*ListenConfig).SetMultipathTCP", Method, 21, ""}, + {"(*OpError).Error", Method, 0, ""}, + {"(*OpError).Temporary", Method, 0, ""}, + {"(*OpError).Timeout", Method, 0, ""}, + {"(*OpError).Unwrap", Method, 13, ""}, + {"(*ParseError).Error", Method, 0, ""}, + {"(*ParseError).Temporary", Method, 17, ""}, + {"(*ParseError).Timeout", Method, 17, ""}, + {"(*Resolver).LookupAddr", Method, 8, ""}, + {"(*Resolver).LookupCNAME", Method, 8, ""}, + {"(*Resolver).LookupHost", Method, 8, ""}, + {"(*Resolver).LookupIP", Method, 15, ""}, + {"(*Resolver).LookupIPAddr", Method, 8, ""}, + {"(*Resolver).LookupMX", Method, 8, ""}, + {"(*Resolver).LookupNS", Method, 8, ""}, + {"(*Resolver).LookupNetIP", Method, 18, ""}, + {"(*Resolver).LookupPort", Method, 8, ""}, + {"(*Resolver).LookupSRV", Method, 8, ""}, + {"(*Resolver).LookupTXT", Method, 8, ""}, + {"(*TCPAddr).AddrPort", Method, 18, ""}, + {"(*TCPAddr).Network", Method, 0, ""}, + {"(*TCPAddr).String", Method, 0, ""}, + {"(*TCPConn).Close", Method, 0, ""}, + {"(*TCPConn).CloseRead", Method, 0, ""}, + {"(*TCPConn).CloseWrite", Method, 0, ""}, + {"(*TCPConn).File", Method, 0, ""}, + {"(*TCPConn).LocalAddr", Method, 0, ""}, + {"(*TCPConn).MultipathTCP", Method, 21, ""}, + {"(*TCPConn).Read", Method, 0, ""}, + {"(*TCPConn).ReadFrom", Method, 0, ""}, + {"(*TCPConn).RemoteAddr", Method, 0, ""}, + {"(*TCPConn).SetDeadline", Method, 0, ""}, + {"(*TCPConn).SetKeepAlive", Method, 0, ""}, + {"(*TCPConn).SetKeepAliveConfig", Method, 23, ""}, + {"(*TCPConn).SetKeepAlivePeriod", Method, 2, ""}, + {"(*TCPConn).SetLinger", Method, 0, ""}, + {"(*TCPConn).SetNoDelay", Method, 0, ""}, + {"(*TCPConn).SetReadBuffer", Method, 0, ""}, + {"(*TCPConn).SetReadDeadline", Method, 0, ""}, + {"(*TCPConn).SetWriteBuffer", Method, 0, ""}, + {"(*TCPConn).SetWriteDeadline", Method, 0, ""}, + {"(*TCPConn).SyscallConn", Method, 9, ""}, + {"(*TCPConn).Write", Method, 0, ""}, + {"(*TCPConn).WriteTo", Method, 22, ""}, + {"(*TCPListener).Accept", Method, 0, ""}, + {"(*TCPListener).AcceptTCP", Method, 0, ""}, + {"(*TCPListener).Addr", Method, 0, ""}, + {"(*TCPListener).Close", Method, 0, ""}, + {"(*TCPListener).File", Method, 0, ""}, + {"(*TCPListener).SetDeadline", Method, 0, ""}, + {"(*TCPListener).SyscallConn", Method, 10, ""}, + {"(*UDPAddr).AddrPort", Method, 18, ""}, + {"(*UDPAddr).Network", Method, 0, ""}, + {"(*UDPAddr).String", Method, 0, ""}, + {"(*UDPConn).Close", Method, 0, ""}, + {"(*UDPConn).File", Method, 0, ""}, + {"(*UDPConn).LocalAddr", Method, 0, ""}, + {"(*UDPConn).Read", Method, 0, ""}, + {"(*UDPConn).ReadFrom", Method, 0, ""}, + {"(*UDPConn).ReadFromUDP", Method, 0, ""}, + {"(*UDPConn).ReadFromUDPAddrPort", Method, 18, ""}, + {"(*UDPConn).ReadMsgUDP", Method, 1, ""}, + {"(*UDPConn).ReadMsgUDPAddrPort", Method, 18, ""}, + {"(*UDPConn).RemoteAddr", Method, 0, ""}, + {"(*UDPConn).SetDeadline", Method, 0, ""}, + {"(*UDPConn).SetReadBuffer", Method, 0, ""}, + {"(*UDPConn).SetReadDeadline", Method, 0, ""}, + {"(*UDPConn).SetWriteBuffer", Method, 0, ""}, + {"(*UDPConn).SetWriteDeadline", Method, 0, ""}, + {"(*UDPConn).SyscallConn", Method, 9, ""}, + {"(*UDPConn).Write", Method, 0, ""}, + {"(*UDPConn).WriteMsgUDP", Method, 1, ""}, + {"(*UDPConn).WriteMsgUDPAddrPort", Method, 18, ""}, + {"(*UDPConn).WriteTo", Method, 0, ""}, + {"(*UDPConn).WriteToUDP", Method, 0, ""}, + {"(*UDPConn).WriteToUDPAddrPort", Method, 18, ""}, + {"(*UnixAddr).Network", Method, 0, ""}, + {"(*UnixAddr).String", Method, 0, ""}, + {"(*UnixConn).Close", Method, 0, ""}, + {"(*UnixConn).CloseRead", Method, 1, ""}, + {"(*UnixConn).CloseWrite", Method, 1, ""}, + {"(*UnixConn).File", Method, 0, ""}, + {"(*UnixConn).LocalAddr", Method, 0, ""}, + {"(*UnixConn).Read", Method, 0, ""}, + {"(*UnixConn).ReadFrom", Method, 0, ""}, + {"(*UnixConn).ReadFromUnix", Method, 0, ""}, + {"(*UnixConn).ReadMsgUnix", Method, 0, ""}, + {"(*UnixConn).RemoteAddr", Method, 0, ""}, + {"(*UnixConn).SetDeadline", Method, 0, ""}, + {"(*UnixConn).SetReadBuffer", Method, 0, ""}, + {"(*UnixConn).SetReadDeadline", Method, 0, ""}, + {"(*UnixConn).SetWriteBuffer", Method, 0, ""}, + {"(*UnixConn).SetWriteDeadline", Method, 0, ""}, + {"(*UnixConn).SyscallConn", Method, 9, ""}, + {"(*UnixConn).Write", Method, 0, ""}, + {"(*UnixConn).WriteMsgUnix", Method, 0, ""}, + {"(*UnixConn).WriteTo", Method, 0, ""}, + {"(*UnixConn).WriteToUnix", Method, 0, ""}, + {"(*UnixListener).Accept", Method, 0, ""}, + {"(*UnixListener).AcceptUnix", Method, 0, ""}, + {"(*UnixListener).Addr", Method, 0, ""}, + {"(*UnixListener).Close", Method, 0, ""}, + {"(*UnixListener).File", Method, 0, ""}, + {"(*UnixListener).SetDeadline", Method, 0, ""}, + {"(*UnixListener).SetUnlinkOnClose", Method, 8, ""}, + {"(*UnixListener).SyscallConn", Method, 10, ""}, + {"(Flags).String", Method, 0, ""}, + {"(HardwareAddr).String", Method, 0, ""}, + {"(IP).AppendText", Method, 24, ""}, + {"(IP).DefaultMask", Method, 0, ""}, + {"(IP).Equal", Method, 0, ""}, + {"(IP).IsGlobalUnicast", Method, 0, ""}, + {"(IP).IsInterfaceLocalMulticast", Method, 0, ""}, + {"(IP).IsLinkLocalMulticast", Method, 0, ""}, + {"(IP).IsLinkLocalUnicast", Method, 0, ""}, + {"(IP).IsLoopback", Method, 0, ""}, + {"(IP).IsMulticast", Method, 0, ""}, + {"(IP).IsPrivate", Method, 17, ""}, + {"(IP).IsUnspecified", Method, 0, ""}, + {"(IP).MarshalText", Method, 2, ""}, + {"(IP).Mask", Method, 0, ""}, + {"(IP).String", Method, 0, ""}, + {"(IP).To16", Method, 0, ""}, + {"(IP).To4", Method, 0, ""}, + {"(IPMask).Size", Method, 0, ""}, + {"(IPMask).String", Method, 0, ""}, + {"(InvalidAddrError).Error", Method, 0, ""}, + {"(InvalidAddrError).Temporary", Method, 0, ""}, + {"(InvalidAddrError).Timeout", Method, 0, ""}, + {"(UnknownNetworkError).Error", Method, 0, ""}, + {"(UnknownNetworkError).Temporary", Method, 0, ""}, + {"(UnknownNetworkError).Timeout", Method, 0, ""}, + {"Addr", Type, 0, ""}, + {"AddrError", Type, 0, ""}, + {"AddrError.Addr", Field, 0, ""}, + {"AddrError.Err", Field, 0, ""}, + {"Buffers", Type, 8, ""}, + {"CIDRMask", Func, 0, "func(ones int, bits int) IPMask"}, + {"Conn", Type, 0, ""}, + {"DNSConfigError", Type, 0, ""}, + {"DNSConfigError.Err", Field, 0, ""}, + {"DNSError", Type, 0, ""}, + {"DNSError.Err", Field, 0, ""}, + {"DNSError.IsNotFound", Field, 13, ""}, + {"DNSError.IsTemporary", Field, 6, ""}, + {"DNSError.IsTimeout", Field, 0, ""}, + {"DNSError.Name", Field, 0, ""}, + {"DNSError.Server", Field, 0, ""}, + {"DNSError.UnwrapErr", Field, 23, ""}, + {"DefaultResolver", Var, 8, ""}, + {"Dial", Func, 0, "func(network string, address string) (Conn, error)"}, + {"DialIP", Func, 0, "func(network string, laddr *IPAddr, raddr *IPAddr) (*IPConn, error)"}, + {"DialTCP", Func, 0, "func(network string, laddr *TCPAddr, raddr *TCPAddr) (*TCPConn, error)"}, + {"DialTimeout", Func, 0, "func(network string, address string, timeout time.Duration) (Conn, error)"}, + {"DialUDP", Func, 0, "func(network string, laddr *UDPAddr, raddr *UDPAddr) (*UDPConn, error)"}, + {"DialUnix", Func, 0, "func(network string, laddr *UnixAddr, raddr *UnixAddr) (*UnixConn, error)"}, + {"Dialer", Type, 1, ""}, + {"Dialer.Cancel", Field, 6, ""}, + {"Dialer.Control", Field, 11, ""}, + {"Dialer.ControlContext", Field, 20, ""}, + {"Dialer.Deadline", Field, 1, ""}, + {"Dialer.DualStack", Field, 2, ""}, + {"Dialer.FallbackDelay", Field, 5, ""}, + {"Dialer.KeepAlive", Field, 3, ""}, + {"Dialer.KeepAliveConfig", Field, 23, ""}, + {"Dialer.LocalAddr", Field, 1, ""}, + {"Dialer.Resolver", Field, 8, ""}, + {"Dialer.Timeout", Field, 1, ""}, + {"ErrClosed", Var, 16, ""}, + {"ErrWriteToConnected", Var, 0, ""}, + {"Error", Type, 0, ""}, + {"FileConn", Func, 0, "func(f *os.File) (c Conn, err error)"}, + {"FileListener", Func, 0, "func(f *os.File) (ln Listener, err error)"}, + {"FilePacketConn", Func, 0, "func(f *os.File) (c PacketConn, err error)"}, + {"FlagBroadcast", Const, 0, ""}, + {"FlagLoopback", Const, 0, ""}, + {"FlagMulticast", Const, 0, ""}, + {"FlagPointToPoint", Const, 0, ""}, + {"FlagRunning", Const, 20, ""}, + {"FlagUp", Const, 0, ""}, + {"Flags", Type, 0, ""}, + {"HardwareAddr", Type, 0, ""}, + {"IP", Type, 0, ""}, + {"IPAddr", Type, 0, ""}, + {"IPAddr.IP", Field, 0, ""}, + {"IPAddr.Zone", Field, 1, ""}, + {"IPConn", Type, 0, ""}, + {"IPMask", Type, 0, ""}, + {"IPNet", Type, 0, ""}, + {"IPNet.IP", Field, 0, ""}, + {"IPNet.Mask", Field, 0, ""}, + {"IPv4", Func, 0, "func(a byte, b byte, c byte, d byte) IP"}, + {"IPv4Mask", Func, 0, "func(a byte, b byte, c byte, d byte) IPMask"}, + {"IPv4allrouter", Var, 0, ""}, + {"IPv4allsys", Var, 0, ""}, + {"IPv4bcast", Var, 0, ""}, + {"IPv4len", Const, 0, ""}, + {"IPv4zero", Var, 0, ""}, + {"IPv6interfacelocalallnodes", Var, 0, ""}, + {"IPv6len", Const, 0, ""}, + {"IPv6linklocalallnodes", Var, 0, ""}, + {"IPv6linklocalallrouters", Var, 0, ""}, + {"IPv6loopback", Var, 0, ""}, + {"IPv6unspecified", Var, 0, ""}, + {"IPv6zero", Var, 0, ""}, + {"Interface", Type, 0, ""}, + {"Interface.Flags", Field, 0, ""}, + {"Interface.HardwareAddr", Field, 0, ""}, + {"Interface.Index", Field, 0, ""}, + {"Interface.MTU", Field, 0, ""}, + {"Interface.Name", Field, 0, ""}, + {"InterfaceAddrs", Func, 0, "func() ([]Addr, error)"}, + {"InterfaceByIndex", Func, 0, "func(index int) (*Interface, error)"}, + {"InterfaceByName", Func, 0, "func(name string) (*Interface, error)"}, + {"Interfaces", Func, 0, "func() ([]Interface, error)"}, + {"InvalidAddrError", Type, 0, ""}, + {"JoinHostPort", Func, 0, "func(host string, port string) string"}, + {"KeepAliveConfig", Type, 23, ""}, + {"KeepAliveConfig.Count", Field, 23, ""}, + {"KeepAliveConfig.Enable", Field, 23, ""}, + {"KeepAliveConfig.Idle", Field, 23, ""}, + {"KeepAliveConfig.Interval", Field, 23, ""}, + {"Listen", Func, 0, "func(network string, address string) (Listener, error)"}, + {"ListenConfig", Type, 11, ""}, + {"ListenConfig.Control", Field, 11, ""}, + {"ListenConfig.KeepAlive", Field, 13, ""}, + {"ListenConfig.KeepAliveConfig", Field, 23, ""}, + {"ListenIP", Func, 0, "func(network string, laddr *IPAddr) (*IPConn, error)"}, + {"ListenMulticastUDP", Func, 0, "func(network string, ifi *Interface, gaddr *UDPAddr) (*UDPConn, error)"}, + {"ListenPacket", Func, 0, "func(network string, address string) (PacketConn, error)"}, + {"ListenTCP", Func, 0, "func(network string, laddr *TCPAddr) (*TCPListener, error)"}, + {"ListenUDP", Func, 0, "func(network string, laddr *UDPAddr) (*UDPConn, error)"}, + {"ListenUnix", Func, 0, "func(network string, laddr *UnixAddr) (*UnixListener, error)"}, + {"ListenUnixgram", Func, 0, "func(network string, laddr *UnixAddr) (*UnixConn, error)"}, + {"Listener", Type, 0, ""}, + {"LookupAddr", Func, 0, "func(addr string) (names []string, err error)"}, + {"LookupCNAME", Func, 0, "func(host string) (cname string, err error)"}, + {"LookupHost", Func, 0, "func(host string) (addrs []string, err error)"}, + {"LookupIP", Func, 0, "func(host string) ([]IP, error)"}, + {"LookupMX", Func, 0, "func(name string) ([]*MX, error)"}, + {"LookupNS", Func, 1, "func(name string) ([]*NS, error)"}, + {"LookupPort", Func, 0, "func(network string, service string) (port int, err error)"}, + {"LookupSRV", Func, 0, "func(service string, proto string, name string) (cname string, addrs []*SRV, err error)"}, + {"LookupTXT", Func, 0, "func(name string) ([]string, error)"}, + {"MX", Type, 0, ""}, + {"MX.Host", Field, 0, ""}, + {"MX.Pref", Field, 0, ""}, + {"NS", Type, 1, ""}, + {"NS.Host", Field, 1, ""}, + {"OpError", Type, 0, ""}, + {"OpError.Addr", Field, 0, ""}, + {"OpError.Err", Field, 0, ""}, + {"OpError.Net", Field, 0, ""}, + {"OpError.Op", Field, 0, ""}, + {"OpError.Source", Field, 5, ""}, + {"PacketConn", Type, 0, ""}, + {"ParseCIDR", Func, 0, "func(s string) (IP, *IPNet, error)"}, + {"ParseError", Type, 0, ""}, + {"ParseError.Text", Field, 0, ""}, + {"ParseError.Type", Field, 0, ""}, + {"ParseIP", Func, 0, "func(s string) IP"}, + {"ParseMAC", Func, 0, "func(s string) (hw HardwareAddr, err error)"}, + {"Pipe", Func, 0, "func() (Conn, Conn)"}, + {"ResolveIPAddr", Func, 0, "func(network string, address string) (*IPAddr, error)"}, + {"ResolveTCPAddr", Func, 0, "func(network string, address string) (*TCPAddr, error)"}, + {"ResolveUDPAddr", Func, 0, "func(network string, address string) (*UDPAddr, error)"}, + {"ResolveUnixAddr", Func, 0, "func(network string, address string) (*UnixAddr, error)"}, + {"Resolver", Type, 8, ""}, + {"Resolver.Dial", Field, 9, ""}, + {"Resolver.PreferGo", Field, 8, ""}, + {"Resolver.StrictErrors", Field, 9, ""}, + {"SRV", Type, 0, ""}, + {"SRV.Port", Field, 0, ""}, + {"SRV.Priority", Field, 0, ""}, + {"SRV.Target", Field, 0, ""}, + {"SRV.Weight", Field, 0, ""}, + {"SplitHostPort", Func, 0, "func(hostport string) (host string, port string, err error)"}, + {"TCPAddr", Type, 0, ""}, + {"TCPAddr.IP", Field, 0, ""}, + {"TCPAddr.Port", Field, 0, ""}, + {"TCPAddr.Zone", Field, 1, ""}, + {"TCPAddrFromAddrPort", Func, 18, "func(addr netip.AddrPort) *TCPAddr"}, + {"TCPConn", Type, 0, ""}, + {"TCPListener", Type, 0, ""}, + {"UDPAddr", Type, 0, ""}, + {"UDPAddr.IP", Field, 0, ""}, + {"UDPAddr.Port", Field, 0, ""}, + {"UDPAddr.Zone", Field, 1, ""}, + {"UDPAddrFromAddrPort", Func, 18, "func(addr netip.AddrPort) *UDPAddr"}, + {"UDPConn", Type, 0, ""}, + {"UnixAddr", Type, 0, ""}, + {"UnixAddr.Name", Field, 0, ""}, + {"UnixAddr.Net", Field, 0, ""}, + {"UnixConn", Type, 0, ""}, + {"UnixListener", Type, 0, ""}, + {"UnknownNetworkError", Type, 0, ""}, }, "net/http": { - {"(*Client).CloseIdleConnections", Method, 12}, - {"(*Client).Do", Method, 0}, - {"(*Client).Get", Method, 0}, - {"(*Client).Head", Method, 0}, - {"(*Client).Post", Method, 0}, - {"(*Client).PostForm", Method, 0}, - {"(*Cookie).String", Method, 0}, - {"(*Cookie).Valid", Method, 18}, - {"(*MaxBytesError).Error", Method, 19}, - {"(*ProtocolError).Error", Method, 0}, - {"(*ProtocolError).Is", Method, 21}, - {"(*Protocols).SetHTTP1", Method, 24}, - {"(*Protocols).SetHTTP2", Method, 24}, - {"(*Protocols).SetUnencryptedHTTP2", Method, 24}, - {"(*Request).AddCookie", Method, 0}, - {"(*Request).BasicAuth", Method, 4}, - {"(*Request).Clone", Method, 13}, - {"(*Request).Context", Method, 7}, - {"(*Request).Cookie", Method, 0}, - {"(*Request).Cookies", Method, 0}, - {"(*Request).CookiesNamed", Method, 23}, - {"(*Request).FormFile", Method, 0}, - {"(*Request).FormValue", Method, 0}, - {"(*Request).MultipartReader", Method, 0}, - {"(*Request).ParseForm", Method, 0}, - {"(*Request).ParseMultipartForm", Method, 0}, - {"(*Request).PathValue", Method, 22}, - {"(*Request).PostFormValue", Method, 1}, - {"(*Request).ProtoAtLeast", Method, 0}, - {"(*Request).Referer", Method, 0}, - {"(*Request).SetBasicAuth", Method, 0}, - {"(*Request).SetPathValue", Method, 22}, - {"(*Request).UserAgent", Method, 0}, - {"(*Request).WithContext", Method, 7}, - {"(*Request).Write", Method, 0}, - {"(*Request).WriteProxy", Method, 0}, - {"(*Response).Cookies", Method, 0}, - {"(*Response).Location", Method, 0}, - {"(*Response).ProtoAtLeast", Method, 0}, - {"(*Response).Write", Method, 0}, - {"(*ResponseController).EnableFullDuplex", Method, 21}, - {"(*ResponseController).Flush", Method, 20}, - {"(*ResponseController).Hijack", Method, 20}, - {"(*ResponseController).SetReadDeadline", Method, 20}, - {"(*ResponseController).SetWriteDeadline", Method, 20}, - {"(*ServeMux).Handle", Method, 0}, - {"(*ServeMux).HandleFunc", Method, 0}, - {"(*ServeMux).Handler", Method, 1}, - {"(*ServeMux).ServeHTTP", Method, 0}, - {"(*Server).Close", Method, 8}, - {"(*Server).ListenAndServe", Method, 0}, - {"(*Server).ListenAndServeTLS", Method, 0}, - {"(*Server).RegisterOnShutdown", Method, 9}, - {"(*Server).Serve", Method, 0}, - {"(*Server).ServeTLS", Method, 9}, - {"(*Server).SetKeepAlivesEnabled", Method, 3}, - {"(*Server).Shutdown", Method, 8}, - {"(*Transport).CancelRequest", Method, 1}, - {"(*Transport).Clone", Method, 13}, - {"(*Transport).CloseIdleConnections", Method, 0}, - {"(*Transport).RegisterProtocol", Method, 0}, - {"(*Transport).RoundTrip", Method, 0}, - {"(ConnState).String", Method, 3}, - {"(Dir).Open", Method, 0}, - {"(HandlerFunc).ServeHTTP", Method, 0}, - {"(Header).Add", Method, 0}, - {"(Header).Clone", Method, 13}, - {"(Header).Del", Method, 0}, - {"(Header).Get", Method, 0}, - {"(Header).Set", Method, 0}, - {"(Header).Values", Method, 14}, - {"(Header).Write", Method, 0}, - {"(Header).WriteSubset", Method, 0}, - {"(Protocols).HTTP1", Method, 24}, - {"(Protocols).HTTP2", Method, 24}, - {"(Protocols).String", Method, 24}, - {"(Protocols).UnencryptedHTTP2", Method, 24}, - {"AllowQuerySemicolons", Func, 17}, - {"CanonicalHeaderKey", Func, 0}, - {"Client", Type, 0}, - {"Client.CheckRedirect", Field, 0}, - {"Client.Jar", Field, 0}, - {"Client.Timeout", Field, 3}, - {"Client.Transport", Field, 0}, - {"CloseNotifier", Type, 1}, - {"ConnState", Type, 3}, - {"Cookie", Type, 0}, - {"Cookie.Domain", Field, 0}, - {"Cookie.Expires", Field, 0}, - {"Cookie.HttpOnly", Field, 0}, - {"Cookie.MaxAge", Field, 0}, - {"Cookie.Name", Field, 0}, - {"Cookie.Partitioned", Field, 23}, - {"Cookie.Path", Field, 0}, - {"Cookie.Quoted", Field, 23}, - {"Cookie.Raw", Field, 0}, - {"Cookie.RawExpires", Field, 0}, - {"Cookie.SameSite", Field, 11}, - {"Cookie.Secure", Field, 0}, - {"Cookie.Unparsed", Field, 0}, - {"Cookie.Value", Field, 0}, - {"CookieJar", Type, 0}, - {"DefaultClient", Var, 0}, - {"DefaultMaxHeaderBytes", Const, 0}, - {"DefaultMaxIdleConnsPerHost", Const, 0}, - {"DefaultServeMux", Var, 0}, - {"DefaultTransport", Var, 0}, - {"DetectContentType", Func, 0}, - {"Dir", Type, 0}, - {"ErrAbortHandler", Var, 8}, - {"ErrBodyNotAllowed", Var, 0}, - {"ErrBodyReadAfterClose", Var, 0}, - {"ErrContentLength", Var, 0}, - {"ErrHandlerTimeout", Var, 0}, - {"ErrHeaderTooLong", Var, 0}, - {"ErrHijacked", Var, 0}, - {"ErrLineTooLong", Var, 0}, - {"ErrMissingBoundary", Var, 0}, - {"ErrMissingContentLength", Var, 0}, - {"ErrMissingFile", Var, 0}, - {"ErrNoCookie", Var, 0}, - {"ErrNoLocation", Var, 0}, - {"ErrNotMultipart", Var, 0}, - {"ErrNotSupported", Var, 0}, - {"ErrSchemeMismatch", Var, 21}, - {"ErrServerClosed", Var, 8}, - {"ErrShortBody", Var, 0}, - {"ErrSkipAltProtocol", Var, 6}, - {"ErrUnexpectedTrailer", Var, 0}, - {"ErrUseLastResponse", Var, 7}, - {"ErrWriteAfterFlush", Var, 0}, - {"Error", Func, 0}, - {"FS", Func, 16}, - {"File", Type, 0}, - {"FileServer", Func, 0}, - {"FileServerFS", Func, 22}, - {"FileSystem", Type, 0}, - {"Flusher", Type, 0}, - {"Get", Func, 0}, - {"HTTP2Config", Type, 24}, - {"HTTP2Config.CountError", Field, 24}, - {"HTTP2Config.MaxConcurrentStreams", Field, 24}, - {"HTTP2Config.MaxDecoderHeaderTableSize", Field, 24}, - {"HTTP2Config.MaxEncoderHeaderTableSize", Field, 24}, - {"HTTP2Config.MaxReadFrameSize", Field, 24}, - {"HTTP2Config.MaxReceiveBufferPerConnection", Field, 24}, - {"HTTP2Config.MaxReceiveBufferPerStream", Field, 24}, - {"HTTP2Config.PermitProhibitedCipherSuites", Field, 24}, - {"HTTP2Config.PingTimeout", Field, 24}, - {"HTTP2Config.SendPingTimeout", Field, 24}, - {"HTTP2Config.WriteByteTimeout", Field, 24}, - {"Handle", Func, 0}, - {"HandleFunc", Func, 0}, - {"Handler", Type, 0}, - {"HandlerFunc", Type, 0}, - {"Head", Func, 0}, - {"Header", Type, 0}, - {"Hijacker", Type, 0}, - {"ListenAndServe", Func, 0}, - {"ListenAndServeTLS", Func, 0}, - {"LocalAddrContextKey", Var, 7}, - {"MaxBytesError", Type, 19}, - {"MaxBytesError.Limit", Field, 19}, - {"MaxBytesHandler", Func, 18}, - {"MaxBytesReader", Func, 0}, - {"MethodConnect", Const, 6}, - {"MethodDelete", Const, 6}, - {"MethodGet", Const, 6}, - {"MethodHead", Const, 6}, - {"MethodOptions", Const, 6}, - {"MethodPatch", Const, 6}, - {"MethodPost", Const, 6}, - {"MethodPut", Const, 6}, - {"MethodTrace", Const, 6}, - {"NewFileTransport", Func, 0}, - {"NewFileTransportFS", Func, 22}, - {"NewRequest", Func, 0}, - {"NewRequestWithContext", Func, 13}, - {"NewResponseController", Func, 20}, - {"NewServeMux", Func, 0}, - {"NoBody", Var, 8}, - {"NotFound", Func, 0}, - {"NotFoundHandler", Func, 0}, - {"ParseCookie", Func, 23}, - {"ParseHTTPVersion", Func, 0}, - {"ParseSetCookie", Func, 23}, - {"ParseTime", Func, 1}, - {"Post", Func, 0}, - {"PostForm", Func, 0}, - {"ProtocolError", Type, 0}, - {"ProtocolError.ErrorString", Field, 0}, - {"Protocols", Type, 24}, - {"ProxyFromEnvironment", Func, 0}, - {"ProxyURL", Func, 0}, - {"PushOptions", Type, 8}, - {"PushOptions.Header", Field, 8}, - {"PushOptions.Method", Field, 8}, - {"Pusher", Type, 8}, - {"ReadRequest", Func, 0}, - {"ReadResponse", Func, 0}, - {"Redirect", Func, 0}, - {"RedirectHandler", Func, 0}, - {"Request", Type, 0}, - {"Request.Body", Field, 0}, - {"Request.Cancel", Field, 5}, - {"Request.Close", Field, 0}, - {"Request.ContentLength", Field, 0}, - {"Request.Form", Field, 0}, - {"Request.GetBody", Field, 8}, - {"Request.Header", Field, 0}, - {"Request.Host", Field, 0}, - {"Request.Method", Field, 0}, - {"Request.MultipartForm", Field, 0}, - {"Request.Pattern", Field, 23}, - {"Request.PostForm", Field, 1}, - {"Request.Proto", Field, 0}, - {"Request.ProtoMajor", Field, 0}, - {"Request.ProtoMinor", Field, 0}, - {"Request.RemoteAddr", Field, 0}, - {"Request.RequestURI", Field, 0}, - {"Request.Response", Field, 7}, - {"Request.TLS", Field, 0}, - {"Request.Trailer", Field, 0}, - {"Request.TransferEncoding", Field, 0}, - {"Request.URL", Field, 0}, - {"Response", Type, 0}, - {"Response.Body", Field, 0}, - {"Response.Close", Field, 0}, - {"Response.ContentLength", Field, 0}, - {"Response.Header", Field, 0}, - {"Response.Proto", Field, 0}, - {"Response.ProtoMajor", Field, 0}, - {"Response.ProtoMinor", Field, 0}, - {"Response.Request", Field, 0}, - {"Response.Status", Field, 0}, - {"Response.StatusCode", Field, 0}, - {"Response.TLS", Field, 3}, - {"Response.Trailer", Field, 0}, - {"Response.TransferEncoding", Field, 0}, - {"Response.Uncompressed", Field, 7}, - {"ResponseController", Type, 20}, - {"ResponseWriter", Type, 0}, - {"RoundTripper", Type, 0}, - {"SameSite", Type, 11}, - {"SameSiteDefaultMode", Const, 11}, - {"SameSiteLaxMode", Const, 11}, - {"SameSiteNoneMode", Const, 13}, - {"SameSiteStrictMode", Const, 11}, - {"Serve", Func, 0}, - {"ServeContent", Func, 0}, - {"ServeFile", Func, 0}, - {"ServeFileFS", Func, 22}, - {"ServeMux", Type, 0}, - {"ServeTLS", Func, 9}, - {"Server", Type, 0}, - {"Server.Addr", Field, 0}, - {"Server.BaseContext", Field, 13}, - {"Server.ConnContext", Field, 13}, - {"Server.ConnState", Field, 3}, - {"Server.DisableGeneralOptionsHandler", Field, 20}, - {"Server.ErrorLog", Field, 3}, - {"Server.HTTP2", Field, 24}, - {"Server.Handler", Field, 0}, - {"Server.IdleTimeout", Field, 8}, - {"Server.MaxHeaderBytes", Field, 0}, - {"Server.Protocols", Field, 24}, - {"Server.ReadHeaderTimeout", Field, 8}, - {"Server.ReadTimeout", Field, 0}, - {"Server.TLSConfig", Field, 0}, - {"Server.TLSNextProto", Field, 1}, - {"Server.WriteTimeout", Field, 0}, - {"ServerContextKey", Var, 7}, - {"SetCookie", Func, 0}, - {"StateActive", Const, 3}, - {"StateClosed", Const, 3}, - {"StateHijacked", Const, 3}, - {"StateIdle", Const, 3}, - {"StateNew", Const, 3}, - {"StatusAccepted", Const, 0}, - {"StatusAlreadyReported", Const, 7}, - {"StatusBadGateway", Const, 0}, - {"StatusBadRequest", Const, 0}, - {"StatusConflict", Const, 0}, - {"StatusContinue", Const, 0}, - {"StatusCreated", Const, 0}, - {"StatusEarlyHints", Const, 13}, - {"StatusExpectationFailed", Const, 0}, - {"StatusFailedDependency", Const, 7}, - {"StatusForbidden", Const, 0}, - {"StatusFound", Const, 0}, - {"StatusGatewayTimeout", Const, 0}, - {"StatusGone", Const, 0}, - {"StatusHTTPVersionNotSupported", Const, 0}, - {"StatusIMUsed", Const, 7}, - {"StatusInsufficientStorage", Const, 7}, - {"StatusInternalServerError", Const, 0}, - {"StatusLengthRequired", Const, 0}, - {"StatusLocked", Const, 7}, - {"StatusLoopDetected", Const, 7}, - {"StatusMethodNotAllowed", Const, 0}, - {"StatusMisdirectedRequest", Const, 11}, - {"StatusMovedPermanently", Const, 0}, - {"StatusMultiStatus", Const, 7}, - {"StatusMultipleChoices", Const, 0}, - {"StatusNetworkAuthenticationRequired", Const, 6}, - {"StatusNoContent", Const, 0}, - {"StatusNonAuthoritativeInfo", Const, 0}, - {"StatusNotAcceptable", Const, 0}, - {"StatusNotExtended", Const, 7}, - {"StatusNotFound", Const, 0}, - {"StatusNotImplemented", Const, 0}, - {"StatusNotModified", Const, 0}, - {"StatusOK", Const, 0}, - {"StatusPartialContent", Const, 0}, - {"StatusPaymentRequired", Const, 0}, - {"StatusPermanentRedirect", Const, 7}, - {"StatusPreconditionFailed", Const, 0}, - {"StatusPreconditionRequired", Const, 6}, - {"StatusProcessing", Const, 7}, - {"StatusProxyAuthRequired", Const, 0}, - {"StatusRequestEntityTooLarge", Const, 0}, - {"StatusRequestHeaderFieldsTooLarge", Const, 6}, - {"StatusRequestTimeout", Const, 0}, - {"StatusRequestURITooLong", Const, 0}, - {"StatusRequestedRangeNotSatisfiable", Const, 0}, - {"StatusResetContent", Const, 0}, - {"StatusSeeOther", Const, 0}, - {"StatusServiceUnavailable", Const, 0}, - {"StatusSwitchingProtocols", Const, 0}, - {"StatusTeapot", Const, 0}, - {"StatusTemporaryRedirect", Const, 0}, - {"StatusText", Func, 0}, - {"StatusTooEarly", Const, 12}, - {"StatusTooManyRequests", Const, 6}, - {"StatusUnauthorized", Const, 0}, - {"StatusUnavailableForLegalReasons", Const, 6}, - {"StatusUnprocessableEntity", Const, 7}, - {"StatusUnsupportedMediaType", Const, 0}, - {"StatusUpgradeRequired", Const, 7}, - {"StatusUseProxy", Const, 0}, - {"StatusVariantAlsoNegotiates", Const, 7}, - {"StripPrefix", Func, 0}, - {"TimeFormat", Const, 0}, - {"TimeoutHandler", Func, 0}, - {"TrailerPrefix", Const, 8}, - {"Transport", Type, 0}, - {"Transport.Dial", Field, 0}, - {"Transport.DialContext", Field, 7}, - {"Transport.DialTLS", Field, 4}, - {"Transport.DialTLSContext", Field, 14}, - {"Transport.DisableCompression", Field, 0}, - {"Transport.DisableKeepAlives", Field, 0}, - {"Transport.ExpectContinueTimeout", Field, 6}, - {"Transport.ForceAttemptHTTP2", Field, 13}, - {"Transport.GetProxyConnectHeader", Field, 16}, - {"Transport.HTTP2", Field, 24}, - {"Transport.IdleConnTimeout", Field, 7}, - {"Transport.MaxConnsPerHost", Field, 11}, - {"Transport.MaxIdleConns", Field, 7}, - {"Transport.MaxIdleConnsPerHost", Field, 0}, - {"Transport.MaxResponseHeaderBytes", Field, 7}, - {"Transport.OnProxyConnectResponse", Field, 20}, - {"Transport.Protocols", Field, 24}, - {"Transport.Proxy", Field, 0}, - {"Transport.ProxyConnectHeader", Field, 8}, - {"Transport.ReadBufferSize", Field, 13}, - {"Transport.ResponseHeaderTimeout", Field, 1}, - {"Transport.TLSClientConfig", Field, 0}, - {"Transport.TLSHandshakeTimeout", Field, 3}, - {"Transport.TLSNextProto", Field, 6}, - {"Transport.WriteBufferSize", Field, 13}, + {"(*Client).CloseIdleConnections", Method, 12, ""}, + {"(*Client).Do", Method, 0, ""}, + {"(*Client).Get", Method, 0, ""}, + {"(*Client).Head", Method, 0, ""}, + {"(*Client).Post", Method, 0, ""}, + {"(*Client).PostForm", Method, 0, ""}, + {"(*Cookie).String", Method, 0, ""}, + {"(*Cookie).Valid", Method, 18, ""}, + {"(*MaxBytesError).Error", Method, 19, ""}, + {"(*ProtocolError).Error", Method, 0, ""}, + {"(*ProtocolError).Is", Method, 21, ""}, + {"(*Protocols).SetHTTP1", Method, 24, ""}, + {"(*Protocols).SetHTTP2", Method, 24, ""}, + {"(*Protocols).SetUnencryptedHTTP2", Method, 24, ""}, + {"(*Request).AddCookie", Method, 0, ""}, + {"(*Request).BasicAuth", Method, 4, ""}, + {"(*Request).Clone", Method, 13, ""}, + {"(*Request).Context", Method, 7, ""}, + {"(*Request).Cookie", Method, 0, ""}, + {"(*Request).Cookies", Method, 0, ""}, + {"(*Request).CookiesNamed", Method, 23, ""}, + {"(*Request).FormFile", Method, 0, ""}, + {"(*Request).FormValue", Method, 0, ""}, + {"(*Request).MultipartReader", Method, 0, ""}, + {"(*Request).ParseForm", Method, 0, ""}, + {"(*Request).ParseMultipartForm", Method, 0, ""}, + {"(*Request).PathValue", Method, 22, ""}, + {"(*Request).PostFormValue", Method, 1, ""}, + {"(*Request).ProtoAtLeast", Method, 0, ""}, + {"(*Request).Referer", Method, 0, ""}, + {"(*Request).SetBasicAuth", Method, 0, ""}, + {"(*Request).SetPathValue", Method, 22, ""}, + {"(*Request).UserAgent", Method, 0, ""}, + {"(*Request).WithContext", Method, 7, ""}, + {"(*Request).Write", Method, 0, ""}, + {"(*Request).WriteProxy", Method, 0, ""}, + {"(*Response).Cookies", Method, 0, ""}, + {"(*Response).Location", Method, 0, ""}, + {"(*Response).ProtoAtLeast", Method, 0, ""}, + {"(*Response).Write", Method, 0, ""}, + {"(*ResponseController).EnableFullDuplex", Method, 21, ""}, + {"(*ResponseController).Flush", Method, 20, ""}, + {"(*ResponseController).Hijack", Method, 20, ""}, + {"(*ResponseController).SetReadDeadline", Method, 20, ""}, + {"(*ResponseController).SetWriteDeadline", Method, 20, ""}, + {"(*ServeMux).Handle", Method, 0, ""}, + {"(*ServeMux).HandleFunc", Method, 0, ""}, + {"(*ServeMux).Handler", Method, 1, ""}, + {"(*ServeMux).ServeHTTP", Method, 0, ""}, + {"(*Server).Close", Method, 8, ""}, + {"(*Server).ListenAndServe", Method, 0, ""}, + {"(*Server).ListenAndServeTLS", Method, 0, ""}, + {"(*Server).RegisterOnShutdown", Method, 9, ""}, + {"(*Server).Serve", Method, 0, ""}, + {"(*Server).ServeTLS", Method, 9, ""}, + {"(*Server).SetKeepAlivesEnabled", Method, 3, ""}, + {"(*Server).Shutdown", Method, 8, ""}, + {"(*Transport).CancelRequest", Method, 1, ""}, + {"(*Transport).Clone", Method, 13, ""}, + {"(*Transport).CloseIdleConnections", Method, 0, ""}, + {"(*Transport).RegisterProtocol", Method, 0, ""}, + {"(*Transport).RoundTrip", Method, 0, ""}, + {"(ConnState).String", Method, 3, ""}, + {"(Dir).Open", Method, 0, ""}, + {"(HandlerFunc).ServeHTTP", Method, 0, ""}, + {"(Header).Add", Method, 0, ""}, + {"(Header).Clone", Method, 13, ""}, + {"(Header).Del", Method, 0, ""}, + {"(Header).Get", Method, 0, ""}, + {"(Header).Set", Method, 0, ""}, + {"(Header).Values", Method, 14, ""}, + {"(Header).Write", Method, 0, ""}, + {"(Header).WriteSubset", Method, 0, ""}, + {"(Protocols).HTTP1", Method, 24, ""}, + {"(Protocols).HTTP2", Method, 24, ""}, + {"(Protocols).String", Method, 24, ""}, + {"(Protocols).UnencryptedHTTP2", Method, 24, ""}, + {"AllowQuerySemicolons", Func, 17, "func(h Handler) Handler"}, + {"CanonicalHeaderKey", Func, 0, "func(s string) string"}, + {"Client", Type, 0, ""}, + {"Client.CheckRedirect", Field, 0, ""}, + {"Client.Jar", Field, 0, ""}, + {"Client.Timeout", Field, 3, ""}, + {"Client.Transport", Field, 0, ""}, + {"CloseNotifier", Type, 1, ""}, + {"ConnState", Type, 3, ""}, + {"Cookie", Type, 0, ""}, + {"Cookie.Domain", Field, 0, ""}, + {"Cookie.Expires", Field, 0, ""}, + {"Cookie.HttpOnly", Field, 0, ""}, + {"Cookie.MaxAge", Field, 0, ""}, + {"Cookie.Name", Field, 0, ""}, + {"Cookie.Partitioned", Field, 23, ""}, + {"Cookie.Path", Field, 0, ""}, + {"Cookie.Quoted", Field, 23, ""}, + {"Cookie.Raw", Field, 0, ""}, + {"Cookie.RawExpires", Field, 0, ""}, + {"Cookie.SameSite", Field, 11, ""}, + {"Cookie.Secure", Field, 0, ""}, + {"Cookie.Unparsed", Field, 0, ""}, + {"Cookie.Value", Field, 0, ""}, + {"CookieJar", Type, 0, ""}, + {"DefaultClient", Var, 0, ""}, + {"DefaultMaxHeaderBytes", Const, 0, ""}, + {"DefaultMaxIdleConnsPerHost", Const, 0, ""}, + {"DefaultServeMux", Var, 0, ""}, + {"DefaultTransport", Var, 0, ""}, + {"DetectContentType", Func, 0, "func(data []byte) string"}, + {"Dir", Type, 0, ""}, + {"ErrAbortHandler", Var, 8, ""}, + {"ErrBodyNotAllowed", Var, 0, ""}, + {"ErrBodyReadAfterClose", Var, 0, ""}, + {"ErrContentLength", Var, 0, ""}, + {"ErrHandlerTimeout", Var, 0, ""}, + {"ErrHeaderTooLong", Var, 0, ""}, + {"ErrHijacked", Var, 0, ""}, + {"ErrLineTooLong", Var, 0, ""}, + {"ErrMissingBoundary", Var, 0, ""}, + {"ErrMissingContentLength", Var, 0, ""}, + {"ErrMissingFile", Var, 0, ""}, + {"ErrNoCookie", Var, 0, ""}, + {"ErrNoLocation", Var, 0, ""}, + {"ErrNotMultipart", Var, 0, ""}, + {"ErrNotSupported", Var, 0, ""}, + {"ErrSchemeMismatch", Var, 21, ""}, + {"ErrServerClosed", Var, 8, ""}, + {"ErrShortBody", Var, 0, ""}, + {"ErrSkipAltProtocol", Var, 6, ""}, + {"ErrUnexpectedTrailer", Var, 0, ""}, + {"ErrUseLastResponse", Var, 7, ""}, + {"ErrWriteAfterFlush", Var, 0, ""}, + {"Error", Func, 0, "func(w ResponseWriter, error string, code int)"}, + {"FS", Func, 16, "func(fsys fs.FS) FileSystem"}, + {"File", Type, 0, ""}, + {"FileServer", Func, 0, "func(root FileSystem) Handler"}, + {"FileServerFS", Func, 22, "func(root fs.FS) Handler"}, + {"FileSystem", Type, 0, ""}, + {"Flusher", Type, 0, ""}, + {"Get", Func, 0, "func(url string) (resp *Response, err error)"}, + {"HTTP2Config", Type, 24, ""}, + {"HTTP2Config.CountError", Field, 24, ""}, + {"HTTP2Config.MaxConcurrentStreams", Field, 24, ""}, + {"HTTP2Config.MaxDecoderHeaderTableSize", Field, 24, ""}, + {"HTTP2Config.MaxEncoderHeaderTableSize", Field, 24, ""}, + {"HTTP2Config.MaxReadFrameSize", Field, 24, ""}, + {"HTTP2Config.MaxReceiveBufferPerConnection", Field, 24, ""}, + {"HTTP2Config.MaxReceiveBufferPerStream", Field, 24, ""}, + {"HTTP2Config.PermitProhibitedCipherSuites", Field, 24, ""}, + {"HTTP2Config.PingTimeout", Field, 24, ""}, + {"HTTP2Config.SendPingTimeout", Field, 24, ""}, + {"HTTP2Config.WriteByteTimeout", Field, 24, ""}, + {"Handle", Func, 0, "func(pattern string, handler Handler)"}, + {"HandleFunc", Func, 0, "func(pattern string, handler func(ResponseWriter, *Request))"}, + {"Handler", Type, 0, ""}, + {"HandlerFunc", Type, 0, ""}, + {"Head", Func, 0, "func(url string) (resp *Response, err error)"}, + {"Header", Type, 0, ""}, + {"Hijacker", Type, 0, ""}, + {"ListenAndServe", Func, 0, "func(addr string, handler Handler) error"}, + {"ListenAndServeTLS", Func, 0, "func(addr string, certFile string, keyFile string, handler Handler) error"}, + {"LocalAddrContextKey", Var, 7, ""}, + {"MaxBytesError", Type, 19, ""}, + {"MaxBytesError.Limit", Field, 19, ""}, + {"MaxBytesHandler", Func, 18, "func(h Handler, n int64) Handler"}, + {"MaxBytesReader", Func, 0, "func(w ResponseWriter, r io.ReadCloser, n int64) io.ReadCloser"}, + {"MethodConnect", Const, 6, ""}, + {"MethodDelete", Const, 6, ""}, + {"MethodGet", Const, 6, ""}, + {"MethodHead", Const, 6, ""}, + {"MethodOptions", Const, 6, ""}, + {"MethodPatch", Const, 6, ""}, + {"MethodPost", Const, 6, ""}, + {"MethodPut", Const, 6, ""}, + {"MethodTrace", Const, 6, ""}, + {"NewFileTransport", Func, 0, "func(fs FileSystem) RoundTripper"}, + {"NewFileTransportFS", Func, 22, "func(fsys fs.FS) RoundTripper"}, + {"NewRequest", Func, 0, "func(method string, url string, body io.Reader) (*Request, error)"}, + {"NewRequestWithContext", Func, 13, "func(ctx context.Context, method string, url string, body io.Reader) (*Request, error)"}, + {"NewResponseController", Func, 20, "func(rw ResponseWriter) *ResponseController"}, + {"NewServeMux", Func, 0, "func() *ServeMux"}, + {"NoBody", Var, 8, ""}, + {"NotFound", Func, 0, "func(w ResponseWriter, r *Request)"}, + {"NotFoundHandler", Func, 0, "func() Handler"}, + {"ParseCookie", Func, 23, "func(line string) ([]*Cookie, error)"}, + {"ParseHTTPVersion", Func, 0, "func(vers string) (major int, minor int, ok bool)"}, + {"ParseSetCookie", Func, 23, "func(line string) (*Cookie, error)"}, + {"ParseTime", Func, 1, "func(text string) (t time.Time, err error)"}, + {"Post", Func, 0, "func(url string, contentType string, body io.Reader) (resp *Response, err error)"}, + {"PostForm", Func, 0, "func(url string, data url.Values) (resp *Response, err error)"}, + {"ProtocolError", Type, 0, ""}, + {"ProtocolError.ErrorString", Field, 0, ""}, + {"Protocols", Type, 24, ""}, + {"ProxyFromEnvironment", Func, 0, "func(req *Request) (*url.URL, error)"}, + {"ProxyURL", Func, 0, "func(fixedURL *url.URL) func(*Request) (*url.URL, error)"}, + {"PushOptions", Type, 8, ""}, + {"PushOptions.Header", Field, 8, ""}, + {"PushOptions.Method", Field, 8, ""}, + {"Pusher", Type, 8, ""}, + {"ReadRequest", Func, 0, "func(b *bufio.Reader) (*Request, error)"}, + {"ReadResponse", Func, 0, "func(r *bufio.Reader, req *Request) (*Response, error)"}, + {"Redirect", Func, 0, "func(w ResponseWriter, r *Request, url string, code int)"}, + {"RedirectHandler", Func, 0, "func(url string, code int) Handler"}, + {"Request", Type, 0, ""}, + {"Request.Body", Field, 0, ""}, + {"Request.Cancel", Field, 5, ""}, + {"Request.Close", Field, 0, ""}, + {"Request.ContentLength", Field, 0, ""}, + {"Request.Form", Field, 0, ""}, + {"Request.GetBody", Field, 8, ""}, + {"Request.Header", Field, 0, ""}, + {"Request.Host", Field, 0, ""}, + {"Request.Method", Field, 0, ""}, + {"Request.MultipartForm", Field, 0, ""}, + {"Request.Pattern", Field, 23, ""}, + {"Request.PostForm", Field, 1, ""}, + {"Request.Proto", Field, 0, ""}, + {"Request.ProtoMajor", Field, 0, ""}, + {"Request.ProtoMinor", Field, 0, ""}, + {"Request.RemoteAddr", Field, 0, ""}, + {"Request.RequestURI", Field, 0, ""}, + {"Request.Response", Field, 7, ""}, + {"Request.TLS", Field, 0, ""}, + {"Request.Trailer", Field, 0, ""}, + {"Request.TransferEncoding", Field, 0, ""}, + {"Request.URL", Field, 0, ""}, + {"Response", Type, 0, ""}, + {"Response.Body", Field, 0, ""}, + {"Response.Close", Field, 0, ""}, + {"Response.ContentLength", Field, 0, ""}, + {"Response.Header", Field, 0, ""}, + {"Response.Proto", Field, 0, ""}, + {"Response.ProtoMajor", Field, 0, ""}, + {"Response.ProtoMinor", Field, 0, ""}, + {"Response.Request", Field, 0, ""}, + {"Response.Status", Field, 0, ""}, + {"Response.StatusCode", Field, 0, ""}, + {"Response.TLS", Field, 3, ""}, + {"Response.Trailer", Field, 0, ""}, + {"Response.TransferEncoding", Field, 0, ""}, + {"Response.Uncompressed", Field, 7, ""}, + {"ResponseController", Type, 20, ""}, + {"ResponseWriter", Type, 0, ""}, + {"RoundTripper", Type, 0, ""}, + {"SameSite", Type, 11, ""}, + {"SameSiteDefaultMode", Const, 11, ""}, + {"SameSiteLaxMode", Const, 11, ""}, + {"SameSiteNoneMode", Const, 13, ""}, + {"SameSiteStrictMode", Const, 11, ""}, + {"Serve", Func, 0, "func(l net.Listener, handler Handler) error"}, + {"ServeContent", Func, 0, "func(w ResponseWriter, req *Request, name string, modtime time.Time, content io.ReadSeeker)"}, + {"ServeFile", Func, 0, "func(w ResponseWriter, r *Request, name string)"}, + {"ServeFileFS", Func, 22, "func(w ResponseWriter, r *Request, fsys fs.FS, name string)"}, + {"ServeMux", Type, 0, ""}, + {"ServeTLS", Func, 9, "func(l net.Listener, handler Handler, certFile string, keyFile string) error"}, + {"Server", Type, 0, ""}, + {"Server.Addr", Field, 0, ""}, + {"Server.BaseContext", Field, 13, ""}, + {"Server.ConnContext", Field, 13, ""}, + {"Server.ConnState", Field, 3, ""}, + {"Server.DisableGeneralOptionsHandler", Field, 20, ""}, + {"Server.ErrorLog", Field, 3, ""}, + {"Server.HTTP2", Field, 24, ""}, + {"Server.Handler", Field, 0, ""}, + {"Server.IdleTimeout", Field, 8, ""}, + {"Server.MaxHeaderBytes", Field, 0, ""}, + {"Server.Protocols", Field, 24, ""}, + {"Server.ReadHeaderTimeout", Field, 8, ""}, + {"Server.ReadTimeout", Field, 0, ""}, + {"Server.TLSConfig", Field, 0, ""}, + {"Server.TLSNextProto", Field, 1, ""}, + {"Server.WriteTimeout", Field, 0, ""}, + {"ServerContextKey", Var, 7, ""}, + {"SetCookie", Func, 0, "func(w ResponseWriter, cookie *Cookie)"}, + {"StateActive", Const, 3, ""}, + {"StateClosed", Const, 3, ""}, + {"StateHijacked", Const, 3, ""}, + {"StateIdle", Const, 3, ""}, + {"StateNew", Const, 3, ""}, + {"StatusAccepted", Const, 0, ""}, + {"StatusAlreadyReported", Const, 7, ""}, + {"StatusBadGateway", Const, 0, ""}, + {"StatusBadRequest", Const, 0, ""}, + {"StatusConflict", Const, 0, ""}, + {"StatusContinue", Const, 0, ""}, + {"StatusCreated", Const, 0, ""}, + {"StatusEarlyHints", Const, 13, ""}, + {"StatusExpectationFailed", Const, 0, ""}, + {"StatusFailedDependency", Const, 7, ""}, + {"StatusForbidden", Const, 0, ""}, + {"StatusFound", Const, 0, ""}, + {"StatusGatewayTimeout", Const, 0, ""}, + {"StatusGone", Const, 0, ""}, + {"StatusHTTPVersionNotSupported", Const, 0, ""}, + {"StatusIMUsed", Const, 7, ""}, + {"StatusInsufficientStorage", Const, 7, ""}, + {"StatusInternalServerError", Const, 0, ""}, + {"StatusLengthRequired", Const, 0, ""}, + {"StatusLocked", Const, 7, ""}, + {"StatusLoopDetected", Const, 7, ""}, + {"StatusMethodNotAllowed", Const, 0, ""}, + {"StatusMisdirectedRequest", Const, 11, ""}, + {"StatusMovedPermanently", Const, 0, ""}, + {"StatusMultiStatus", Const, 7, ""}, + {"StatusMultipleChoices", Const, 0, ""}, + {"StatusNetworkAuthenticationRequired", Const, 6, ""}, + {"StatusNoContent", Const, 0, ""}, + {"StatusNonAuthoritativeInfo", Const, 0, ""}, + {"StatusNotAcceptable", Const, 0, ""}, + {"StatusNotExtended", Const, 7, ""}, + {"StatusNotFound", Const, 0, ""}, + {"StatusNotImplemented", Const, 0, ""}, + {"StatusNotModified", Const, 0, ""}, + {"StatusOK", Const, 0, ""}, + {"StatusPartialContent", Const, 0, ""}, + {"StatusPaymentRequired", Const, 0, ""}, + {"StatusPermanentRedirect", Const, 7, ""}, + {"StatusPreconditionFailed", Const, 0, ""}, + {"StatusPreconditionRequired", Const, 6, ""}, + {"StatusProcessing", Const, 7, ""}, + {"StatusProxyAuthRequired", Const, 0, ""}, + {"StatusRequestEntityTooLarge", Const, 0, ""}, + {"StatusRequestHeaderFieldsTooLarge", Const, 6, ""}, + {"StatusRequestTimeout", Const, 0, ""}, + {"StatusRequestURITooLong", Const, 0, ""}, + {"StatusRequestedRangeNotSatisfiable", Const, 0, ""}, + {"StatusResetContent", Const, 0, ""}, + {"StatusSeeOther", Const, 0, ""}, + {"StatusServiceUnavailable", Const, 0, ""}, + {"StatusSwitchingProtocols", Const, 0, ""}, + {"StatusTeapot", Const, 0, ""}, + {"StatusTemporaryRedirect", Const, 0, ""}, + {"StatusText", Func, 0, "func(code int) string"}, + {"StatusTooEarly", Const, 12, ""}, + {"StatusTooManyRequests", Const, 6, ""}, + {"StatusUnauthorized", Const, 0, ""}, + {"StatusUnavailableForLegalReasons", Const, 6, ""}, + {"StatusUnprocessableEntity", Const, 7, ""}, + {"StatusUnsupportedMediaType", Const, 0, ""}, + {"StatusUpgradeRequired", Const, 7, ""}, + {"StatusUseProxy", Const, 0, ""}, + {"StatusVariantAlsoNegotiates", Const, 7, ""}, + {"StripPrefix", Func, 0, "func(prefix string, h Handler) Handler"}, + {"TimeFormat", Const, 0, ""}, + {"TimeoutHandler", Func, 0, "func(h Handler, dt time.Duration, msg string) Handler"}, + {"TrailerPrefix", Const, 8, ""}, + {"Transport", Type, 0, ""}, + {"Transport.Dial", Field, 0, ""}, + {"Transport.DialContext", Field, 7, ""}, + {"Transport.DialTLS", Field, 4, ""}, + {"Transport.DialTLSContext", Field, 14, ""}, + {"Transport.DisableCompression", Field, 0, ""}, + {"Transport.DisableKeepAlives", Field, 0, ""}, + {"Transport.ExpectContinueTimeout", Field, 6, ""}, + {"Transport.ForceAttemptHTTP2", Field, 13, ""}, + {"Transport.GetProxyConnectHeader", Field, 16, ""}, + {"Transport.HTTP2", Field, 24, ""}, + {"Transport.IdleConnTimeout", Field, 7, ""}, + {"Transport.MaxConnsPerHost", Field, 11, ""}, + {"Transport.MaxIdleConns", Field, 7, ""}, + {"Transport.MaxIdleConnsPerHost", Field, 0, ""}, + {"Transport.MaxResponseHeaderBytes", Field, 7, ""}, + {"Transport.OnProxyConnectResponse", Field, 20, ""}, + {"Transport.Protocols", Field, 24, ""}, + {"Transport.Proxy", Field, 0, ""}, + {"Transport.ProxyConnectHeader", Field, 8, ""}, + {"Transport.ReadBufferSize", Field, 13, ""}, + {"Transport.ResponseHeaderTimeout", Field, 1, ""}, + {"Transport.TLSClientConfig", Field, 0, ""}, + {"Transport.TLSHandshakeTimeout", Field, 3, ""}, + {"Transport.TLSNextProto", Field, 6, ""}, + {"Transport.WriteBufferSize", Field, 13, ""}, }, "net/http/cgi": { - {"(*Handler).ServeHTTP", Method, 0}, - {"Handler", Type, 0}, - {"Handler.Args", Field, 0}, - {"Handler.Dir", Field, 0}, - {"Handler.Env", Field, 0}, - {"Handler.InheritEnv", Field, 0}, - {"Handler.Logger", Field, 0}, - {"Handler.Path", Field, 0}, - {"Handler.PathLocationHandler", Field, 0}, - {"Handler.Root", Field, 0}, - {"Handler.Stderr", Field, 7}, - {"Request", Func, 0}, - {"RequestFromMap", Func, 0}, - {"Serve", Func, 0}, + {"(*Handler).ServeHTTP", Method, 0, ""}, + {"Handler", Type, 0, ""}, + {"Handler.Args", Field, 0, ""}, + {"Handler.Dir", Field, 0, ""}, + {"Handler.Env", Field, 0, ""}, + {"Handler.InheritEnv", Field, 0, ""}, + {"Handler.Logger", Field, 0, ""}, + {"Handler.Path", Field, 0, ""}, + {"Handler.PathLocationHandler", Field, 0, ""}, + {"Handler.Root", Field, 0, ""}, + {"Handler.Stderr", Field, 7, ""}, + {"Request", Func, 0, "func() (*http.Request, error)"}, + {"RequestFromMap", Func, 0, "func(params map[string]string) (*http.Request, error)"}, + {"Serve", Func, 0, "func(handler http.Handler) error"}, }, "net/http/cookiejar": { - {"(*Jar).Cookies", Method, 1}, - {"(*Jar).SetCookies", Method, 1}, - {"Jar", Type, 1}, - {"New", Func, 1}, - {"Options", Type, 1}, - {"Options.PublicSuffixList", Field, 1}, - {"PublicSuffixList", Type, 1}, + {"(*Jar).Cookies", Method, 1, ""}, + {"(*Jar).SetCookies", Method, 1, ""}, + {"Jar", Type, 1, ""}, + {"New", Func, 1, "func(o *Options) (*Jar, error)"}, + {"Options", Type, 1, ""}, + {"Options.PublicSuffixList", Field, 1, ""}, + {"PublicSuffixList", Type, 1, ""}, }, "net/http/fcgi": { - {"ErrConnClosed", Var, 5}, - {"ErrRequestAborted", Var, 5}, - {"ProcessEnv", Func, 9}, - {"Serve", Func, 0}, + {"ErrConnClosed", Var, 5, ""}, + {"ErrRequestAborted", Var, 5, ""}, + {"ProcessEnv", Func, 9, "func(r *http.Request) map[string]string"}, + {"Serve", Func, 0, "func(l net.Listener, handler http.Handler) error"}, }, "net/http/httptest": { - {"(*ResponseRecorder).Flush", Method, 0}, - {"(*ResponseRecorder).Header", Method, 0}, - {"(*ResponseRecorder).Result", Method, 7}, - {"(*ResponseRecorder).Write", Method, 0}, - {"(*ResponseRecorder).WriteHeader", Method, 0}, - {"(*ResponseRecorder).WriteString", Method, 6}, - {"(*Server).Certificate", Method, 9}, - {"(*Server).Client", Method, 9}, - {"(*Server).Close", Method, 0}, - {"(*Server).CloseClientConnections", Method, 0}, - {"(*Server).Start", Method, 0}, - {"(*Server).StartTLS", Method, 0}, - {"DefaultRemoteAddr", Const, 0}, - {"NewRecorder", Func, 0}, - {"NewRequest", Func, 7}, - {"NewRequestWithContext", Func, 23}, - {"NewServer", Func, 0}, - {"NewTLSServer", Func, 0}, - {"NewUnstartedServer", Func, 0}, - {"ResponseRecorder", Type, 0}, - {"ResponseRecorder.Body", Field, 0}, - {"ResponseRecorder.Code", Field, 0}, - {"ResponseRecorder.Flushed", Field, 0}, - {"ResponseRecorder.HeaderMap", Field, 0}, - {"Server", Type, 0}, - {"Server.Config", Field, 0}, - {"Server.EnableHTTP2", Field, 14}, - {"Server.Listener", Field, 0}, - {"Server.TLS", Field, 0}, - {"Server.URL", Field, 0}, + {"(*ResponseRecorder).Flush", Method, 0, ""}, + {"(*ResponseRecorder).Header", Method, 0, ""}, + {"(*ResponseRecorder).Result", Method, 7, ""}, + {"(*ResponseRecorder).Write", Method, 0, ""}, + {"(*ResponseRecorder).WriteHeader", Method, 0, ""}, + {"(*ResponseRecorder).WriteString", Method, 6, ""}, + {"(*Server).Certificate", Method, 9, ""}, + {"(*Server).Client", Method, 9, ""}, + {"(*Server).Close", Method, 0, ""}, + {"(*Server).CloseClientConnections", Method, 0, ""}, + {"(*Server).Start", Method, 0, ""}, + {"(*Server).StartTLS", Method, 0, ""}, + {"DefaultRemoteAddr", Const, 0, ""}, + {"NewRecorder", Func, 0, "func() *ResponseRecorder"}, + {"NewRequest", Func, 7, "func(method string, target string, body io.Reader) *http.Request"}, + {"NewRequestWithContext", Func, 23, "func(ctx context.Context, method string, target string, body io.Reader) *http.Request"}, + {"NewServer", Func, 0, "func(handler http.Handler) *Server"}, + {"NewTLSServer", Func, 0, "func(handler http.Handler) *Server"}, + {"NewUnstartedServer", Func, 0, "func(handler http.Handler) *Server"}, + {"ResponseRecorder", Type, 0, ""}, + {"ResponseRecorder.Body", Field, 0, ""}, + {"ResponseRecorder.Code", Field, 0, ""}, + {"ResponseRecorder.Flushed", Field, 0, ""}, + {"ResponseRecorder.HeaderMap", Field, 0, ""}, + {"Server", Type, 0, ""}, + {"Server.Config", Field, 0, ""}, + {"Server.EnableHTTP2", Field, 14, ""}, + {"Server.Listener", Field, 0, ""}, + {"Server.TLS", Field, 0, ""}, + {"Server.URL", Field, 0, ""}, }, "net/http/httptrace": { - {"ClientTrace", Type, 7}, - {"ClientTrace.ConnectDone", Field, 7}, - {"ClientTrace.ConnectStart", Field, 7}, - {"ClientTrace.DNSDone", Field, 7}, - {"ClientTrace.DNSStart", Field, 7}, - {"ClientTrace.GetConn", Field, 7}, - {"ClientTrace.Got100Continue", Field, 7}, - {"ClientTrace.Got1xxResponse", Field, 11}, - {"ClientTrace.GotConn", Field, 7}, - {"ClientTrace.GotFirstResponseByte", Field, 7}, - {"ClientTrace.PutIdleConn", Field, 7}, - {"ClientTrace.TLSHandshakeDone", Field, 8}, - {"ClientTrace.TLSHandshakeStart", Field, 8}, - {"ClientTrace.Wait100Continue", Field, 7}, - {"ClientTrace.WroteHeaderField", Field, 11}, - {"ClientTrace.WroteHeaders", Field, 7}, - {"ClientTrace.WroteRequest", Field, 7}, - {"ContextClientTrace", Func, 7}, - {"DNSDoneInfo", Type, 7}, - {"DNSDoneInfo.Addrs", Field, 7}, - {"DNSDoneInfo.Coalesced", Field, 7}, - {"DNSDoneInfo.Err", Field, 7}, - {"DNSStartInfo", Type, 7}, - {"DNSStartInfo.Host", Field, 7}, - {"GotConnInfo", Type, 7}, - {"GotConnInfo.Conn", Field, 7}, - {"GotConnInfo.IdleTime", Field, 7}, - {"GotConnInfo.Reused", Field, 7}, - {"GotConnInfo.WasIdle", Field, 7}, - {"WithClientTrace", Func, 7}, - {"WroteRequestInfo", Type, 7}, - {"WroteRequestInfo.Err", Field, 7}, + {"ClientTrace", Type, 7, ""}, + {"ClientTrace.ConnectDone", Field, 7, ""}, + {"ClientTrace.ConnectStart", Field, 7, ""}, + {"ClientTrace.DNSDone", Field, 7, ""}, + {"ClientTrace.DNSStart", Field, 7, ""}, + {"ClientTrace.GetConn", Field, 7, ""}, + {"ClientTrace.Got100Continue", Field, 7, ""}, + {"ClientTrace.Got1xxResponse", Field, 11, ""}, + {"ClientTrace.GotConn", Field, 7, ""}, + {"ClientTrace.GotFirstResponseByte", Field, 7, ""}, + {"ClientTrace.PutIdleConn", Field, 7, ""}, + {"ClientTrace.TLSHandshakeDone", Field, 8, ""}, + {"ClientTrace.TLSHandshakeStart", Field, 8, ""}, + {"ClientTrace.Wait100Continue", Field, 7, ""}, + {"ClientTrace.WroteHeaderField", Field, 11, ""}, + {"ClientTrace.WroteHeaders", Field, 7, ""}, + {"ClientTrace.WroteRequest", Field, 7, ""}, + {"ContextClientTrace", Func, 7, "func(ctx context.Context) *ClientTrace"}, + {"DNSDoneInfo", Type, 7, ""}, + {"DNSDoneInfo.Addrs", Field, 7, ""}, + {"DNSDoneInfo.Coalesced", Field, 7, ""}, + {"DNSDoneInfo.Err", Field, 7, ""}, + {"DNSStartInfo", Type, 7, ""}, + {"DNSStartInfo.Host", Field, 7, ""}, + {"GotConnInfo", Type, 7, ""}, + {"GotConnInfo.Conn", Field, 7, ""}, + {"GotConnInfo.IdleTime", Field, 7, ""}, + {"GotConnInfo.Reused", Field, 7, ""}, + {"GotConnInfo.WasIdle", Field, 7, ""}, + {"WithClientTrace", Func, 7, "func(ctx context.Context, trace *ClientTrace) context.Context"}, + {"WroteRequestInfo", Type, 7, ""}, + {"WroteRequestInfo.Err", Field, 7, ""}, }, "net/http/httputil": { - {"(*ClientConn).Close", Method, 0}, - {"(*ClientConn).Do", Method, 0}, - {"(*ClientConn).Hijack", Method, 0}, - {"(*ClientConn).Pending", Method, 0}, - {"(*ClientConn).Read", Method, 0}, - {"(*ClientConn).Write", Method, 0}, - {"(*ProxyRequest).SetURL", Method, 20}, - {"(*ProxyRequest).SetXForwarded", Method, 20}, - {"(*ReverseProxy).ServeHTTP", Method, 0}, - {"(*ServerConn).Close", Method, 0}, - {"(*ServerConn).Hijack", Method, 0}, - {"(*ServerConn).Pending", Method, 0}, - {"(*ServerConn).Read", Method, 0}, - {"(*ServerConn).Write", Method, 0}, - {"BufferPool", Type, 6}, - {"ClientConn", Type, 0}, - {"DumpRequest", Func, 0}, - {"DumpRequestOut", Func, 0}, - {"DumpResponse", Func, 0}, - {"ErrClosed", Var, 0}, - {"ErrLineTooLong", Var, 0}, - {"ErrPersistEOF", Var, 0}, - {"ErrPipeline", Var, 0}, - {"NewChunkedReader", Func, 0}, - {"NewChunkedWriter", Func, 0}, - {"NewClientConn", Func, 0}, - {"NewProxyClientConn", Func, 0}, - {"NewServerConn", Func, 0}, - {"NewSingleHostReverseProxy", Func, 0}, - {"ProxyRequest", Type, 20}, - {"ProxyRequest.In", Field, 20}, - {"ProxyRequest.Out", Field, 20}, - {"ReverseProxy", Type, 0}, - {"ReverseProxy.BufferPool", Field, 6}, - {"ReverseProxy.Director", Field, 0}, - {"ReverseProxy.ErrorHandler", Field, 11}, - {"ReverseProxy.ErrorLog", Field, 4}, - {"ReverseProxy.FlushInterval", Field, 0}, - {"ReverseProxy.ModifyResponse", Field, 8}, - {"ReverseProxy.Rewrite", Field, 20}, - {"ReverseProxy.Transport", Field, 0}, - {"ServerConn", Type, 0}, + {"(*ClientConn).Close", Method, 0, ""}, + {"(*ClientConn).Do", Method, 0, ""}, + {"(*ClientConn).Hijack", Method, 0, ""}, + {"(*ClientConn).Pending", Method, 0, ""}, + {"(*ClientConn).Read", Method, 0, ""}, + {"(*ClientConn).Write", Method, 0, ""}, + {"(*ProxyRequest).SetURL", Method, 20, ""}, + {"(*ProxyRequest).SetXForwarded", Method, 20, ""}, + {"(*ReverseProxy).ServeHTTP", Method, 0, ""}, + {"(*ServerConn).Close", Method, 0, ""}, + {"(*ServerConn).Hijack", Method, 0, ""}, + {"(*ServerConn).Pending", Method, 0, ""}, + {"(*ServerConn).Read", Method, 0, ""}, + {"(*ServerConn).Write", Method, 0, ""}, + {"BufferPool", Type, 6, ""}, + {"ClientConn", Type, 0, ""}, + {"DumpRequest", Func, 0, "func(req *http.Request, body bool) ([]byte, error)"}, + {"DumpRequestOut", Func, 0, "func(req *http.Request, body bool) ([]byte, error)"}, + {"DumpResponse", Func, 0, "func(resp *http.Response, body bool) ([]byte, error)"}, + {"ErrClosed", Var, 0, ""}, + {"ErrLineTooLong", Var, 0, ""}, + {"ErrPersistEOF", Var, 0, ""}, + {"ErrPipeline", Var, 0, ""}, + {"NewChunkedReader", Func, 0, "func(r io.Reader) io.Reader"}, + {"NewChunkedWriter", Func, 0, "func(w io.Writer) io.WriteCloser"}, + {"NewClientConn", Func, 0, "func(c net.Conn, r *bufio.Reader) *ClientConn"}, + {"NewProxyClientConn", Func, 0, "func(c net.Conn, r *bufio.Reader) *ClientConn"}, + {"NewServerConn", Func, 0, "func(c net.Conn, r *bufio.Reader) *ServerConn"}, + {"NewSingleHostReverseProxy", Func, 0, "func(target *url.URL) *ReverseProxy"}, + {"ProxyRequest", Type, 20, ""}, + {"ProxyRequest.In", Field, 20, ""}, + {"ProxyRequest.Out", Field, 20, ""}, + {"ReverseProxy", Type, 0, ""}, + {"ReverseProxy.BufferPool", Field, 6, ""}, + {"ReverseProxy.Director", Field, 0, ""}, + {"ReverseProxy.ErrorHandler", Field, 11, ""}, + {"ReverseProxy.ErrorLog", Field, 4, ""}, + {"ReverseProxy.FlushInterval", Field, 0, ""}, + {"ReverseProxy.ModifyResponse", Field, 8, ""}, + {"ReverseProxy.Rewrite", Field, 20, ""}, + {"ReverseProxy.Transport", Field, 0, ""}, + {"ServerConn", Type, 0, ""}, }, "net/http/pprof": { - {"Cmdline", Func, 0}, - {"Handler", Func, 0}, - {"Index", Func, 0}, - {"Profile", Func, 0}, - {"Symbol", Func, 0}, - {"Trace", Func, 5}, + {"Cmdline", Func, 0, "func(w http.ResponseWriter, r *http.Request)"}, + {"Handler", Func, 0, "func(name string) http.Handler"}, + {"Index", Func, 0, "func(w http.ResponseWriter, r *http.Request)"}, + {"Profile", Func, 0, "func(w http.ResponseWriter, r *http.Request)"}, + {"Symbol", Func, 0, "func(w http.ResponseWriter, r *http.Request)"}, + {"Trace", Func, 5, "func(w http.ResponseWriter, r *http.Request)"}, }, "net/mail": { - {"(*Address).String", Method, 0}, - {"(*AddressParser).Parse", Method, 5}, - {"(*AddressParser).ParseList", Method, 5}, - {"(Header).AddressList", Method, 0}, - {"(Header).Date", Method, 0}, - {"(Header).Get", Method, 0}, - {"Address", Type, 0}, - {"Address.Address", Field, 0}, - {"Address.Name", Field, 0}, - {"AddressParser", Type, 5}, - {"AddressParser.WordDecoder", Field, 5}, - {"ErrHeaderNotPresent", Var, 0}, - {"Header", Type, 0}, - {"Message", Type, 0}, - {"Message.Body", Field, 0}, - {"Message.Header", Field, 0}, - {"ParseAddress", Func, 1}, - {"ParseAddressList", Func, 1}, - {"ParseDate", Func, 8}, - {"ReadMessage", Func, 0}, + {"(*Address).String", Method, 0, ""}, + {"(*AddressParser).Parse", Method, 5, ""}, + {"(*AddressParser).ParseList", Method, 5, ""}, + {"(Header).AddressList", Method, 0, ""}, + {"(Header).Date", Method, 0, ""}, + {"(Header).Get", Method, 0, ""}, + {"Address", Type, 0, ""}, + {"Address.Address", Field, 0, ""}, + {"Address.Name", Field, 0, ""}, + {"AddressParser", Type, 5, ""}, + {"AddressParser.WordDecoder", Field, 5, ""}, + {"ErrHeaderNotPresent", Var, 0, ""}, + {"Header", Type, 0, ""}, + {"Message", Type, 0, ""}, + {"Message.Body", Field, 0, ""}, + {"Message.Header", Field, 0, ""}, + {"ParseAddress", Func, 1, "func(address string) (*Address, error)"}, + {"ParseAddressList", Func, 1, "func(list string) ([]*Address, error)"}, + {"ParseDate", Func, 8, "func(date string) (time.Time, error)"}, + {"ReadMessage", Func, 0, "func(r io.Reader) (msg *Message, err error)"}, }, "net/netip": { - {"(*Addr).UnmarshalBinary", Method, 18}, - {"(*Addr).UnmarshalText", Method, 18}, - {"(*AddrPort).UnmarshalBinary", Method, 18}, - {"(*AddrPort).UnmarshalText", Method, 18}, - {"(*Prefix).UnmarshalBinary", Method, 18}, - {"(*Prefix).UnmarshalText", Method, 18}, - {"(Addr).AppendBinary", Method, 24}, - {"(Addr).AppendText", Method, 24}, - {"(Addr).AppendTo", Method, 18}, - {"(Addr).As16", Method, 18}, - {"(Addr).As4", Method, 18}, - {"(Addr).AsSlice", Method, 18}, - {"(Addr).BitLen", Method, 18}, - {"(Addr).Compare", Method, 18}, - {"(Addr).Is4", Method, 18}, - {"(Addr).Is4In6", Method, 18}, - {"(Addr).Is6", Method, 18}, - {"(Addr).IsGlobalUnicast", Method, 18}, - {"(Addr).IsInterfaceLocalMulticast", Method, 18}, - {"(Addr).IsLinkLocalMulticast", Method, 18}, - {"(Addr).IsLinkLocalUnicast", Method, 18}, - {"(Addr).IsLoopback", Method, 18}, - {"(Addr).IsMulticast", Method, 18}, - {"(Addr).IsPrivate", Method, 18}, - {"(Addr).IsUnspecified", Method, 18}, - {"(Addr).IsValid", Method, 18}, - {"(Addr).Less", Method, 18}, - {"(Addr).MarshalBinary", Method, 18}, - {"(Addr).MarshalText", Method, 18}, - {"(Addr).Next", Method, 18}, - {"(Addr).Prefix", Method, 18}, - {"(Addr).Prev", Method, 18}, - {"(Addr).String", Method, 18}, - {"(Addr).StringExpanded", Method, 18}, - {"(Addr).Unmap", Method, 18}, - {"(Addr).WithZone", Method, 18}, - {"(Addr).Zone", Method, 18}, - {"(AddrPort).Addr", Method, 18}, - {"(AddrPort).AppendBinary", Method, 24}, - {"(AddrPort).AppendText", Method, 24}, - {"(AddrPort).AppendTo", Method, 18}, - {"(AddrPort).Compare", Method, 22}, - {"(AddrPort).IsValid", Method, 18}, - {"(AddrPort).MarshalBinary", Method, 18}, - {"(AddrPort).MarshalText", Method, 18}, - {"(AddrPort).Port", Method, 18}, - {"(AddrPort).String", Method, 18}, - {"(Prefix).Addr", Method, 18}, - {"(Prefix).AppendBinary", Method, 24}, - {"(Prefix).AppendText", Method, 24}, - {"(Prefix).AppendTo", Method, 18}, - {"(Prefix).Bits", Method, 18}, - {"(Prefix).Contains", Method, 18}, - {"(Prefix).IsSingleIP", Method, 18}, - {"(Prefix).IsValid", Method, 18}, - {"(Prefix).MarshalBinary", Method, 18}, - {"(Prefix).MarshalText", Method, 18}, - {"(Prefix).Masked", Method, 18}, - {"(Prefix).Overlaps", Method, 18}, - {"(Prefix).String", Method, 18}, - {"Addr", Type, 18}, - {"AddrFrom16", Func, 18}, - {"AddrFrom4", Func, 18}, - {"AddrFromSlice", Func, 18}, - {"AddrPort", Type, 18}, - {"AddrPortFrom", Func, 18}, - {"IPv4Unspecified", Func, 18}, - {"IPv6LinkLocalAllNodes", Func, 18}, - {"IPv6LinkLocalAllRouters", Func, 20}, - {"IPv6Loopback", Func, 20}, - {"IPv6Unspecified", Func, 18}, - {"MustParseAddr", Func, 18}, - {"MustParseAddrPort", Func, 18}, - {"MustParsePrefix", Func, 18}, - {"ParseAddr", Func, 18}, - {"ParseAddrPort", Func, 18}, - {"ParsePrefix", Func, 18}, - {"Prefix", Type, 18}, - {"PrefixFrom", Func, 18}, + {"(*Addr).UnmarshalBinary", Method, 18, ""}, + {"(*Addr).UnmarshalText", Method, 18, ""}, + {"(*AddrPort).UnmarshalBinary", Method, 18, ""}, + {"(*AddrPort).UnmarshalText", Method, 18, ""}, + {"(*Prefix).UnmarshalBinary", Method, 18, ""}, + {"(*Prefix).UnmarshalText", Method, 18, ""}, + {"(Addr).AppendBinary", Method, 24, ""}, + {"(Addr).AppendText", Method, 24, ""}, + {"(Addr).AppendTo", Method, 18, ""}, + {"(Addr).As16", Method, 18, ""}, + {"(Addr).As4", Method, 18, ""}, + {"(Addr).AsSlice", Method, 18, ""}, + {"(Addr).BitLen", Method, 18, ""}, + {"(Addr).Compare", Method, 18, ""}, + {"(Addr).Is4", Method, 18, ""}, + {"(Addr).Is4In6", Method, 18, ""}, + {"(Addr).Is6", Method, 18, ""}, + {"(Addr).IsGlobalUnicast", Method, 18, ""}, + {"(Addr).IsInterfaceLocalMulticast", Method, 18, ""}, + {"(Addr).IsLinkLocalMulticast", Method, 18, ""}, + {"(Addr).IsLinkLocalUnicast", Method, 18, ""}, + {"(Addr).IsLoopback", Method, 18, ""}, + {"(Addr).IsMulticast", Method, 18, ""}, + {"(Addr).IsPrivate", Method, 18, ""}, + {"(Addr).IsUnspecified", Method, 18, ""}, + {"(Addr).IsValid", Method, 18, ""}, + {"(Addr).Less", Method, 18, ""}, + {"(Addr).MarshalBinary", Method, 18, ""}, + {"(Addr).MarshalText", Method, 18, ""}, + {"(Addr).Next", Method, 18, ""}, + {"(Addr).Prefix", Method, 18, ""}, + {"(Addr).Prev", Method, 18, ""}, + {"(Addr).String", Method, 18, ""}, + {"(Addr).StringExpanded", Method, 18, ""}, + {"(Addr).Unmap", Method, 18, ""}, + {"(Addr).WithZone", Method, 18, ""}, + {"(Addr).Zone", Method, 18, ""}, + {"(AddrPort).Addr", Method, 18, ""}, + {"(AddrPort).AppendBinary", Method, 24, ""}, + {"(AddrPort).AppendText", Method, 24, ""}, + {"(AddrPort).AppendTo", Method, 18, ""}, + {"(AddrPort).Compare", Method, 22, ""}, + {"(AddrPort).IsValid", Method, 18, ""}, + {"(AddrPort).MarshalBinary", Method, 18, ""}, + {"(AddrPort).MarshalText", Method, 18, ""}, + {"(AddrPort).Port", Method, 18, ""}, + {"(AddrPort).String", Method, 18, ""}, + {"(Prefix).Addr", Method, 18, ""}, + {"(Prefix).AppendBinary", Method, 24, ""}, + {"(Prefix).AppendText", Method, 24, ""}, + {"(Prefix).AppendTo", Method, 18, ""}, + {"(Prefix).Bits", Method, 18, ""}, + {"(Prefix).Contains", Method, 18, ""}, + {"(Prefix).IsSingleIP", Method, 18, ""}, + {"(Prefix).IsValid", Method, 18, ""}, + {"(Prefix).MarshalBinary", Method, 18, ""}, + {"(Prefix).MarshalText", Method, 18, ""}, + {"(Prefix).Masked", Method, 18, ""}, + {"(Prefix).Overlaps", Method, 18, ""}, + {"(Prefix).String", Method, 18, ""}, + {"Addr", Type, 18, ""}, + {"AddrFrom16", Func, 18, "func(addr [16]byte) Addr"}, + {"AddrFrom4", Func, 18, "func(addr [4]byte) Addr"}, + {"AddrFromSlice", Func, 18, "func(slice []byte) (ip Addr, ok bool)"}, + {"AddrPort", Type, 18, ""}, + {"AddrPortFrom", Func, 18, "func(ip Addr, port uint16) AddrPort"}, + {"IPv4Unspecified", Func, 18, "func() Addr"}, + {"IPv6LinkLocalAllNodes", Func, 18, "func() Addr"}, + {"IPv6LinkLocalAllRouters", Func, 20, "func() Addr"}, + {"IPv6Loopback", Func, 20, "func() Addr"}, + {"IPv6Unspecified", Func, 18, "func() Addr"}, + {"MustParseAddr", Func, 18, "func(s string) Addr"}, + {"MustParseAddrPort", Func, 18, "func(s string) AddrPort"}, + {"MustParsePrefix", Func, 18, "func(s string) Prefix"}, + {"ParseAddr", Func, 18, "func(s string) (Addr, error)"}, + {"ParseAddrPort", Func, 18, "func(s string) (AddrPort, error)"}, + {"ParsePrefix", Func, 18, "func(s string) (Prefix, error)"}, + {"Prefix", Type, 18, ""}, + {"PrefixFrom", Func, 18, "func(ip Addr, bits int) Prefix"}, }, "net/rpc": { - {"(*Client).Call", Method, 0}, - {"(*Client).Close", Method, 0}, - {"(*Client).Go", Method, 0}, - {"(*Server).Accept", Method, 0}, - {"(*Server).HandleHTTP", Method, 0}, - {"(*Server).Register", Method, 0}, - {"(*Server).RegisterName", Method, 0}, - {"(*Server).ServeCodec", Method, 0}, - {"(*Server).ServeConn", Method, 0}, - {"(*Server).ServeHTTP", Method, 0}, - {"(*Server).ServeRequest", Method, 0}, - {"(ServerError).Error", Method, 0}, - {"Accept", Func, 0}, - {"Call", Type, 0}, - {"Call.Args", Field, 0}, - {"Call.Done", Field, 0}, - {"Call.Error", Field, 0}, - {"Call.Reply", Field, 0}, - {"Call.ServiceMethod", Field, 0}, - {"Client", Type, 0}, - {"ClientCodec", Type, 0}, - {"DefaultDebugPath", Const, 0}, - {"DefaultRPCPath", Const, 0}, - {"DefaultServer", Var, 0}, - {"Dial", Func, 0}, - {"DialHTTP", Func, 0}, - {"DialHTTPPath", Func, 0}, - {"ErrShutdown", Var, 0}, - {"HandleHTTP", Func, 0}, - {"NewClient", Func, 0}, - {"NewClientWithCodec", Func, 0}, - {"NewServer", Func, 0}, - {"Register", Func, 0}, - {"RegisterName", Func, 0}, - {"Request", Type, 0}, - {"Request.Seq", Field, 0}, - {"Request.ServiceMethod", Field, 0}, - {"Response", Type, 0}, - {"Response.Error", Field, 0}, - {"Response.Seq", Field, 0}, - {"Response.ServiceMethod", Field, 0}, - {"ServeCodec", Func, 0}, - {"ServeConn", Func, 0}, - {"ServeRequest", Func, 0}, - {"Server", Type, 0}, - {"ServerCodec", Type, 0}, - {"ServerError", Type, 0}, + {"(*Client).Call", Method, 0, ""}, + {"(*Client).Close", Method, 0, ""}, + {"(*Client).Go", Method, 0, ""}, + {"(*Server).Accept", Method, 0, ""}, + {"(*Server).HandleHTTP", Method, 0, ""}, + {"(*Server).Register", Method, 0, ""}, + {"(*Server).RegisterName", Method, 0, ""}, + {"(*Server).ServeCodec", Method, 0, ""}, + {"(*Server).ServeConn", Method, 0, ""}, + {"(*Server).ServeHTTP", Method, 0, ""}, + {"(*Server).ServeRequest", Method, 0, ""}, + {"(ServerError).Error", Method, 0, ""}, + {"Accept", Func, 0, "func(lis net.Listener)"}, + {"Call", Type, 0, ""}, + {"Call.Args", Field, 0, ""}, + {"Call.Done", Field, 0, ""}, + {"Call.Error", Field, 0, ""}, + {"Call.Reply", Field, 0, ""}, + {"Call.ServiceMethod", Field, 0, ""}, + {"Client", Type, 0, ""}, + {"ClientCodec", Type, 0, ""}, + {"DefaultDebugPath", Const, 0, ""}, + {"DefaultRPCPath", Const, 0, ""}, + {"DefaultServer", Var, 0, ""}, + {"Dial", Func, 0, "func(network string, address string) (*Client, error)"}, + {"DialHTTP", Func, 0, "func(network string, address string) (*Client, error)"}, + {"DialHTTPPath", Func, 0, "func(network string, address string, path string) (*Client, error)"}, + {"ErrShutdown", Var, 0, ""}, + {"HandleHTTP", Func, 0, "func()"}, + {"NewClient", Func, 0, "func(conn io.ReadWriteCloser) *Client"}, + {"NewClientWithCodec", Func, 0, "func(codec ClientCodec) *Client"}, + {"NewServer", Func, 0, "func() *Server"}, + {"Register", Func, 0, "func(rcvr any) error"}, + {"RegisterName", Func, 0, "func(name string, rcvr any) error"}, + {"Request", Type, 0, ""}, + {"Request.Seq", Field, 0, ""}, + {"Request.ServiceMethod", Field, 0, ""}, + {"Response", Type, 0, ""}, + {"Response.Error", Field, 0, ""}, + {"Response.Seq", Field, 0, ""}, + {"Response.ServiceMethod", Field, 0, ""}, + {"ServeCodec", Func, 0, "func(codec ServerCodec)"}, + {"ServeConn", Func, 0, "func(conn io.ReadWriteCloser)"}, + {"ServeRequest", Func, 0, "func(codec ServerCodec) error"}, + {"Server", Type, 0, ""}, + {"ServerCodec", Type, 0, ""}, + {"ServerError", Type, 0, ""}, }, "net/rpc/jsonrpc": { - {"Dial", Func, 0}, - {"NewClient", Func, 0}, - {"NewClientCodec", Func, 0}, - {"NewServerCodec", Func, 0}, - {"ServeConn", Func, 0}, + {"Dial", Func, 0, "func(network string, address string) (*rpc.Client, error)"}, + {"NewClient", Func, 0, "func(conn io.ReadWriteCloser) *rpc.Client"}, + {"NewClientCodec", Func, 0, "func(conn io.ReadWriteCloser) rpc.ClientCodec"}, + {"NewServerCodec", Func, 0, "func(conn io.ReadWriteCloser) rpc.ServerCodec"}, + {"ServeConn", Func, 0, "func(conn io.ReadWriteCloser)"}, }, "net/smtp": { - {"(*Client).Auth", Method, 0}, - {"(*Client).Close", Method, 2}, - {"(*Client).Data", Method, 0}, - {"(*Client).Extension", Method, 0}, - {"(*Client).Hello", Method, 1}, - {"(*Client).Mail", Method, 0}, - {"(*Client).Noop", Method, 10}, - {"(*Client).Quit", Method, 0}, - {"(*Client).Rcpt", Method, 0}, - {"(*Client).Reset", Method, 0}, - {"(*Client).StartTLS", Method, 0}, - {"(*Client).TLSConnectionState", Method, 5}, - {"(*Client).Verify", Method, 0}, - {"Auth", Type, 0}, - {"CRAMMD5Auth", Func, 0}, - {"Client", Type, 0}, - {"Client.Text", Field, 0}, - {"Dial", Func, 0}, - {"NewClient", Func, 0}, - {"PlainAuth", Func, 0}, - {"SendMail", Func, 0}, - {"ServerInfo", Type, 0}, - {"ServerInfo.Auth", Field, 0}, - {"ServerInfo.Name", Field, 0}, - {"ServerInfo.TLS", Field, 0}, + {"(*Client).Auth", Method, 0, ""}, + {"(*Client).Close", Method, 2, ""}, + {"(*Client).Data", Method, 0, ""}, + {"(*Client).Extension", Method, 0, ""}, + {"(*Client).Hello", Method, 1, ""}, + {"(*Client).Mail", Method, 0, ""}, + {"(*Client).Noop", Method, 10, ""}, + {"(*Client).Quit", Method, 0, ""}, + {"(*Client).Rcpt", Method, 0, ""}, + {"(*Client).Reset", Method, 0, ""}, + {"(*Client).StartTLS", Method, 0, ""}, + {"(*Client).TLSConnectionState", Method, 5, ""}, + {"(*Client).Verify", Method, 0, ""}, + {"Auth", Type, 0, ""}, + {"CRAMMD5Auth", Func, 0, "func(username string, secret string) Auth"}, + {"Client", Type, 0, ""}, + {"Client.Text", Field, 0, ""}, + {"Dial", Func, 0, "func(addr string) (*Client, error)"}, + {"NewClient", Func, 0, "func(conn net.Conn, host string) (*Client, error)"}, + {"PlainAuth", Func, 0, "func(identity string, username string, password string, host string) Auth"}, + {"SendMail", Func, 0, "func(addr string, a Auth, from string, to []string, msg []byte) error"}, + {"ServerInfo", Type, 0, ""}, + {"ServerInfo.Auth", Field, 0, ""}, + {"ServerInfo.Name", Field, 0, ""}, + {"ServerInfo.TLS", Field, 0, ""}, }, "net/textproto": { - {"(*Conn).Close", Method, 0}, - {"(*Conn).Cmd", Method, 0}, - {"(*Conn).DotReader", Method, 0}, - {"(*Conn).DotWriter", Method, 0}, - {"(*Conn).EndRequest", Method, 0}, - {"(*Conn).EndResponse", Method, 0}, - {"(*Conn).Next", Method, 0}, - {"(*Conn).PrintfLine", Method, 0}, - {"(*Conn).ReadCodeLine", Method, 0}, - {"(*Conn).ReadContinuedLine", Method, 0}, - {"(*Conn).ReadContinuedLineBytes", Method, 0}, - {"(*Conn).ReadDotBytes", Method, 0}, - {"(*Conn).ReadDotLines", Method, 0}, - {"(*Conn).ReadLine", Method, 0}, - {"(*Conn).ReadLineBytes", Method, 0}, - {"(*Conn).ReadMIMEHeader", Method, 0}, - {"(*Conn).ReadResponse", Method, 0}, - {"(*Conn).StartRequest", Method, 0}, - {"(*Conn).StartResponse", Method, 0}, - {"(*Error).Error", Method, 0}, - {"(*Pipeline).EndRequest", Method, 0}, - {"(*Pipeline).EndResponse", Method, 0}, - {"(*Pipeline).Next", Method, 0}, - {"(*Pipeline).StartRequest", Method, 0}, - {"(*Pipeline).StartResponse", Method, 0}, - {"(*Reader).DotReader", Method, 0}, - {"(*Reader).ReadCodeLine", Method, 0}, - {"(*Reader).ReadContinuedLine", Method, 0}, - {"(*Reader).ReadContinuedLineBytes", Method, 0}, - {"(*Reader).ReadDotBytes", Method, 0}, - {"(*Reader).ReadDotLines", Method, 0}, - {"(*Reader).ReadLine", Method, 0}, - {"(*Reader).ReadLineBytes", Method, 0}, - {"(*Reader).ReadMIMEHeader", Method, 0}, - {"(*Reader).ReadResponse", Method, 0}, - {"(*Writer).DotWriter", Method, 0}, - {"(*Writer).PrintfLine", Method, 0}, - {"(MIMEHeader).Add", Method, 0}, - {"(MIMEHeader).Del", Method, 0}, - {"(MIMEHeader).Get", Method, 0}, - {"(MIMEHeader).Set", Method, 0}, - {"(MIMEHeader).Values", Method, 14}, - {"(ProtocolError).Error", Method, 0}, - {"CanonicalMIMEHeaderKey", Func, 0}, - {"Conn", Type, 0}, - {"Conn.Pipeline", Field, 0}, - {"Conn.Reader", Field, 0}, - {"Conn.Writer", Field, 0}, - {"Dial", Func, 0}, - {"Error", Type, 0}, - {"Error.Code", Field, 0}, - {"Error.Msg", Field, 0}, - {"MIMEHeader", Type, 0}, - {"NewConn", Func, 0}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"Pipeline", Type, 0}, - {"ProtocolError", Type, 0}, - {"Reader", Type, 0}, - {"Reader.R", Field, 0}, - {"TrimBytes", Func, 1}, - {"TrimString", Func, 1}, - {"Writer", Type, 0}, - {"Writer.W", Field, 0}, + {"(*Conn).Close", Method, 0, ""}, + {"(*Conn).Cmd", Method, 0, ""}, + {"(*Conn).DotReader", Method, 0, ""}, + {"(*Conn).DotWriter", Method, 0, ""}, + {"(*Conn).EndRequest", Method, 0, ""}, + {"(*Conn).EndResponse", Method, 0, ""}, + {"(*Conn).Next", Method, 0, ""}, + {"(*Conn).PrintfLine", Method, 0, ""}, + {"(*Conn).ReadCodeLine", Method, 0, ""}, + {"(*Conn).ReadContinuedLine", Method, 0, ""}, + {"(*Conn).ReadContinuedLineBytes", Method, 0, ""}, + {"(*Conn).ReadDotBytes", Method, 0, ""}, + {"(*Conn).ReadDotLines", Method, 0, ""}, + {"(*Conn).ReadLine", Method, 0, ""}, + {"(*Conn).ReadLineBytes", Method, 0, ""}, + {"(*Conn).ReadMIMEHeader", Method, 0, ""}, + {"(*Conn).ReadResponse", Method, 0, ""}, + {"(*Conn).StartRequest", Method, 0, ""}, + {"(*Conn).StartResponse", Method, 0, ""}, + {"(*Error).Error", Method, 0, ""}, + {"(*Pipeline).EndRequest", Method, 0, ""}, + {"(*Pipeline).EndResponse", Method, 0, ""}, + {"(*Pipeline).Next", Method, 0, ""}, + {"(*Pipeline).StartRequest", Method, 0, ""}, + {"(*Pipeline).StartResponse", Method, 0, ""}, + {"(*Reader).DotReader", Method, 0, ""}, + {"(*Reader).ReadCodeLine", Method, 0, ""}, + {"(*Reader).ReadContinuedLine", Method, 0, ""}, + {"(*Reader).ReadContinuedLineBytes", Method, 0, ""}, + {"(*Reader).ReadDotBytes", Method, 0, ""}, + {"(*Reader).ReadDotLines", Method, 0, ""}, + {"(*Reader).ReadLine", Method, 0, ""}, + {"(*Reader).ReadLineBytes", Method, 0, ""}, + {"(*Reader).ReadMIMEHeader", Method, 0, ""}, + {"(*Reader).ReadResponse", Method, 0, ""}, + {"(*Writer).DotWriter", Method, 0, ""}, + {"(*Writer).PrintfLine", Method, 0, ""}, + {"(MIMEHeader).Add", Method, 0, ""}, + {"(MIMEHeader).Del", Method, 0, ""}, + {"(MIMEHeader).Get", Method, 0, ""}, + {"(MIMEHeader).Set", Method, 0, ""}, + {"(MIMEHeader).Values", Method, 14, ""}, + {"(ProtocolError).Error", Method, 0, ""}, + {"CanonicalMIMEHeaderKey", Func, 0, "func(s string) string"}, + {"Conn", Type, 0, ""}, + {"Conn.Pipeline", Field, 0, ""}, + {"Conn.Reader", Field, 0, ""}, + {"Conn.Writer", Field, 0, ""}, + {"Dial", Func, 0, "func(network string, addr string) (*Conn, error)"}, + {"Error", Type, 0, ""}, + {"Error.Code", Field, 0, ""}, + {"Error.Msg", Field, 0, ""}, + {"MIMEHeader", Type, 0, ""}, + {"NewConn", Func, 0, "func(conn io.ReadWriteCloser) *Conn"}, + {"NewReader", Func, 0, "func(r *bufio.Reader) *Reader"}, + {"NewWriter", Func, 0, "func(w *bufio.Writer) *Writer"}, + {"Pipeline", Type, 0, ""}, + {"ProtocolError", Type, 0, ""}, + {"Reader", Type, 0, ""}, + {"Reader.R", Field, 0, ""}, + {"TrimBytes", Func, 1, "func(b []byte) []byte"}, + {"TrimString", Func, 1, "func(s string) string"}, + {"Writer", Type, 0, ""}, + {"Writer.W", Field, 0, ""}, }, "net/url": { - {"(*Error).Error", Method, 0}, - {"(*Error).Temporary", Method, 6}, - {"(*Error).Timeout", Method, 6}, - {"(*Error).Unwrap", Method, 13}, - {"(*URL).AppendBinary", Method, 24}, - {"(*URL).EscapedFragment", Method, 15}, - {"(*URL).EscapedPath", Method, 5}, - {"(*URL).Hostname", Method, 8}, - {"(*URL).IsAbs", Method, 0}, - {"(*URL).JoinPath", Method, 19}, - {"(*URL).MarshalBinary", Method, 8}, - {"(*URL).Parse", Method, 0}, - {"(*URL).Port", Method, 8}, - {"(*URL).Query", Method, 0}, - {"(*URL).Redacted", Method, 15}, - {"(*URL).RequestURI", Method, 0}, - {"(*URL).ResolveReference", Method, 0}, - {"(*URL).String", Method, 0}, - {"(*URL).UnmarshalBinary", Method, 8}, - {"(*Userinfo).Password", Method, 0}, - {"(*Userinfo).String", Method, 0}, - {"(*Userinfo).Username", Method, 0}, - {"(EscapeError).Error", Method, 0}, - {"(InvalidHostError).Error", Method, 6}, - {"(Values).Add", Method, 0}, - {"(Values).Del", Method, 0}, - {"(Values).Encode", Method, 0}, - {"(Values).Get", Method, 0}, - {"(Values).Has", Method, 17}, - {"(Values).Set", Method, 0}, - {"Error", Type, 0}, - {"Error.Err", Field, 0}, - {"Error.Op", Field, 0}, - {"Error.URL", Field, 0}, - {"EscapeError", Type, 0}, - {"InvalidHostError", Type, 6}, - {"JoinPath", Func, 19}, - {"Parse", Func, 0}, - {"ParseQuery", Func, 0}, - {"ParseRequestURI", Func, 0}, - {"PathEscape", Func, 8}, - {"PathUnescape", Func, 8}, - {"QueryEscape", Func, 0}, - {"QueryUnescape", Func, 0}, - {"URL", Type, 0}, - {"URL.ForceQuery", Field, 7}, - {"URL.Fragment", Field, 0}, - {"URL.Host", Field, 0}, - {"URL.OmitHost", Field, 19}, - {"URL.Opaque", Field, 0}, - {"URL.Path", Field, 0}, - {"URL.RawFragment", Field, 15}, - {"URL.RawPath", Field, 5}, - {"URL.RawQuery", Field, 0}, - {"URL.Scheme", Field, 0}, - {"URL.User", Field, 0}, - {"User", Func, 0}, - {"UserPassword", Func, 0}, - {"Userinfo", Type, 0}, - {"Values", Type, 0}, + {"(*Error).Error", Method, 0, ""}, + {"(*Error).Temporary", Method, 6, ""}, + {"(*Error).Timeout", Method, 6, ""}, + {"(*Error).Unwrap", Method, 13, ""}, + {"(*URL).AppendBinary", Method, 24, ""}, + {"(*URL).EscapedFragment", Method, 15, ""}, + {"(*URL).EscapedPath", Method, 5, ""}, + {"(*URL).Hostname", Method, 8, ""}, + {"(*URL).IsAbs", Method, 0, ""}, + {"(*URL).JoinPath", Method, 19, ""}, + {"(*URL).MarshalBinary", Method, 8, ""}, + {"(*URL).Parse", Method, 0, ""}, + {"(*URL).Port", Method, 8, ""}, + {"(*URL).Query", Method, 0, ""}, + {"(*URL).Redacted", Method, 15, ""}, + {"(*URL).RequestURI", Method, 0, ""}, + {"(*URL).ResolveReference", Method, 0, ""}, + {"(*URL).String", Method, 0, ""}, + {"(*URL).UnmarshalBinary", Method, 8, ""}, + {"(*Userinfo).Password", Method, 0, ""}, + {"(*Userinfo).String", Method, 0, ""}, + {"(*Userinfo).Username", Method, 0, ""}, + {"(EscapeError).Error", Method, 0, ""}, + {"(InvalidHostError).Error", Method, 6, ""}, + {"(Values).Add", Method, 0, ""}, + {"(Values).Del", Method, 0, ""}, + {"(Values).Encode", Method, 0, ""}, + {"(Values).Get", Method, 0, ""}, + {"(Values).Has", Method, 17, ""}, + {"(Values).Set", Method, 0, ""}, + {"Error", Type, 0, ""}, + {"Error.Err", Field, 0, ""}, + {"Error.Op", Field, 0, ""}, + {"Error.URL", Field, 0, ""}, + {"EscapeError", Type, 0, ""}, + {"InvalidHostError", Type, 6, ""}, + {"JoinPath", Func, 19, "func(base string, elem ...string) (result string, err error)"}, + {"Parse", Func, 0, "func(rawURL string) (*URL, error)"}, + {"ParseQuery", Func, 0, "func(query string) (Values, error)"}, + {"ParseRequestURI", Func, 0, "func(rawURL string) (*URL, error)"}, + {"PathEscape", Func, 8, "func(s string) string"}, + {"PathUnescape", Func, 8, "func(s string) (string, error)"}, + {"QueryEscape", Func, 0, "func(s string) string"}, + {"QueryUnescape", Func, 0, "func(s string) (string, error)"}, + {"URL", Type, 0, ""}, + {"URL.ForceQuery", Field, 7, ""}, + {"URL.Fragment", Field, 0, ""}, + {"URL.Host", Field, 0, ""}, + {"URL.OmitHost", Field, 19, ""}, + {"URL.Opaque", Field, 0, ""}, + {"URL.Path", Field, 0, ""}, + {"URL.RawFragment", Field, 15, ""}, + {"URL.RawPath", Field, 5, ""}, + {"URL.RawQuery", Field, 0, ""}, + {"URL.Scheme", Field, 0, ""}, + {"URL.User", Field, 0, ""}, + {"User", Func, 0, "func(username string) *Userinfo"}, + {"UserPassword", Func, 0, "func(username string, password string) *Userinfo"}, + {"Userinfo", Type, 0, ""}, + {"Values", Type, 0, ""}, }, "os": { - {"(*File).Chdir", Method, 0}, - {"(*File).Chmod", Method, 0}, - {"(*File).Chown", Method, 0}, - {"(*File).Close", Method, 0}, - {"(*File).Fd", Method, 0}, - {"(*File).Name", Method, 0}, - {"(*File).Read", Method, 0}, - {"(*File).ReadAt", Method, 0}, - {"(*File).ReadDir", Method, 16}, - {"(*File).ReadFrom", Method, 15}, - {"(*File).Readdir", Method, 0}, - {"(*File).Readdirnames", Method, 0}, - {"(*File).Seek", Method, 0}, - {"(*File).SetDeadline", Method, 10}, - {"(*File).SetReadDeadline", Method, 10}, - {"(*File).SetWriteDeadline", Method, 10}, - {"(*File).Stat", Method, 0}, - {"(*File).Sync", Method, 0}, - {"(*File).SyscallConn", Method, 12}, - {"(*File).Truncate", Method, 0}, - {"(*File).Write", Method, 0}, - {"(*File).WriteAt", Method, 0}, - {"(*File).WriteString", Method, 0}, - {"(*File).WriteTo", Method, 22}, - {"(*LinkError).Error", Method, 0}, - {"(*LinkError).Unwrap", Method, 13}, - {"(*PathError).Error", Method, 0}, - {"(*PathError).Timeout", Method, 10}, - {"(*PathError).Unwrap", Method, 13}, - {"(*Process).Kill", Method, 0}, - {"(*Process).Release", Method, 0}, - {"(*Process).Signal", Method, 0}, - {"(*Process).Wait", Method, 0}, - {"(*ProcessState).ExitCode", Method, 12}, - {"(*ProcessState).Exited", Method, 0}, - {"(*ProcessState).Pid", Method, 0}, - {"(*ProcessState).String", Method, 0}, - {"(*ProcessState).Success", Method, 0}, - {"(*ProcessState).Sys", Method, 0}, - {"(*ProcessState).SysUsage", Method, 0}, - {"(*ProcessState).SystemTime", Method, 0}, - {"(*ProcessState).UserTime", Method, 0}, - {"(*Root).Chmod", Method, 25}, - {"(*Root).Chown", Method, 25}, - {"(*Root).Chtimes", Method, 25}, - {"(*Root).Close", Method, 24}, - {"(*Root).Create", Method, 24}, - {"(*Root).FS", Method, 24}, - {"(*Root).Lchown", Method, 25}, - {"(*Root).Link", Method, 25}, - {"(*Root).Lstat", Method, 24}, - {"(*Root).Mkdir", Method, 24}, - {"(*Root).Name", Method, 24}, - {"(*Root).Open", Method, 24}, - {"(*Root).OpenFile", Method, 24}, - {"(*Root).OpenRoot", Method, 24}, - {"(*Root).Readlink", Method, 25}, - {"(*Root).Remove", Method, 24}, - {"(*Root).Rename", Method, 25}, - {"(*Root).Stat", Method, 24}, - {"(*Root).Symlink", Method, 25}, - {"(*SyscallError).Error", Method, 0}, - {"(*SyscallError).Timeout", Method, 10}, - {"(*SyscallError).Unwrap", Method, 13}, - {"(FileMode).IsDir", Method, 0}, - {"(FileMode).IsRegular", Method, 1}, - {"(FileMode).Perm", Method, 0}, - {"(FileMode).String", Method, 0}, - {"Args", Var, 0}, - {"Chdir", Func, 0}, - {"Chmod", Func, 0}, - {"Chown", Func, 0}, - {"Chtimes", Func, 0}, - {"Clearenv", Func, 0}, - {"CopyFS", Func, 23}, - {"Create", Func, 0}, - {"CreateTemp", Func, 16}, - {"DevNull", Const, 0}, - {"DirEntry", Type, 16}, - {"DirFS", Func, 16}, - {"Environ", Func, 0}, - {"ErrClosed", Var, 8}, - {"ErrDeadlineExceeded", Var, 15}, - {"ErrExist", Var, 0}, - {"ErrInvalid", Var, 0}, - {"ErrNoDeadline", Var, 10}, - {"ErrNotExist", Var, 0}, - {"ErrPermission", Var, 0}, - {"ErrProcessDone", Var, 16}, - {"Executable", Func, 8}, - {"Exit", Func, 0}, - {"Expand", Func, 0}, - {"ExpandEnv", Func, 0}, - {"File", Type, 0}, - {"FileInfo", Type, 0}, - {"FileMode", Type, 0}, - {"FindProcess", Func, 0}, - {"Getegid", Func, 0}, - {"Getenv", Func, 0}, - {"Geteuid", Func, 0}, - {"Getgid", Func, 0}, - {"Getgroups", Func, 0}, - {"Getpagesize", Func, 0}, - {"Getpid", Func, 0}, - {"Getppid", Func, 0}, - {"Getuid", Func, 0}, - {"Getwd", Func, 0}, - {"Hostname", Func, 0}, - {"Interrupt", Var, 0}, - {"IsExist", Func, 0}, - {"IsNotExist", Func, 0}, - {"IsPathSeparator", Func, 0}, - {"IsPermission", Func, 0}, - {"IsTimeout", Func, 10}, - {"Kill", Var, 0}, - {"Lchown", Func, 0}, - {"Link", Func, 0}, - {"LinkError", Type, 0}, - {"LinkError.Err", Field, 0}, - {"LinkError.New", Field, 0}, - {"LinkError.Old", Field, 0}, - {"LinkError.Op", Field, 0}, - {"LookupEnv", Func, 5}, - {"Lstat", Func, 0}, - {"Mkdir", Func, 0}, - {"MkdirAll", Func, 0}, - {"MkdirTemp", Func, 16}, - {"ModeAppend", Const, 0}, - {"ModeCharDevice", Const, 0}, - {"ModeDevice", Const, 0}, - {"ModeDir", Const, 0}, - {"ModeExclusive", Const, 0}, - {"ModeIrregular", Const, 11}, - {"ModeNamedPipe", Const, 0}, - {"ModePerm", Const, 0}, - {"ModeSetgid", Const, 0}, - {"ModeSetuid", Const, 0}, - {"ModeSocket", Const, 0}, - {"ModeSticky", Const, 0}, - {"ModeSymlink", Const, 0}, - {"ModeTemporary", Const, 0}, - {"ModeType", Const, 0}, - {"NewFile", Func, 0}, - {"NewSyscallError", Func, 0}, - {"O_APPEND", Const, 0}, - {"O_CREATE", Const, 0}, - {"O_EXCL", Const, 0}, - {"O_RDONLY", Const, 0}, - {"O_RDWR", Const, 0}, - {"O_SYNC", Const, 0}, - {"O_TRUNC", Const, 0}, - {"O_WRONLY", Const, 0}, - {"Open", Func, 0}, - {"OpenFile", Func, 0}, - {"OpenInRoot", Func, 24}, - {"OpenRoot", Func, 24}, - {"PathError", Type, 0}, - {"PathError.Err", Field, 0}, - {"PathError.Op", Field, 0}, - {"PathError.Path", Field, 0}, - {"PathListSeparator", Const, 0}, - {"PathSeparator", Const, 0}, - {"Pipe", Func, 0}, - {"ProcAttr", Type, 0}, - {"ProcAttr.Dir", Field, 0}, - {"ProcAttr.Env", Field, 0}, - {"ProcAttr.Files", Field, 0}, - {"ProcAttr.Sys", Field, 0}, - {"Process", Type, 0}, - {"Process.Pid", Field, 0}, - {"ProcessState", Type, 0}, - {"ReadDir", Func, 16}, - {"ReadFile", Func, 16}, - {"Readlink", Func, 0}, - {"Remove", Func, 0}, - {"RemoveAll", Func, 0}, - {"Rename", Func, 0}, - {"Root", Type, 24}, - {"SEEK_CUR", Const, 0}, - {"SEEK_END", Const, 0}, - {"SEEK_SET", Const, 0}, - {"SameFile", Func, 0}, - {"Setenv", Func, 0}, - {"Signal", Type, 0}, - {"StartProcess", Func, 0}, - {"Stat", Func, 0}, - {"Stderr", Var, 0}, - {"Stdin", Var, 0}, - {"Stdout", Var, 0}, - {"Symlink", Func, 0}, - {"SyscallError", Type, 0}, - {"SyscallError.Err", Field, 0}, - {"SyscallError.Syscall", Field, 0}, - {"TempDir", Func, 0}, - {"Truncate", Func, 0}, - {"Unsetenv", Func, 4}, - {"UserCacheDir", Func, 11}, - {"UserConfigDir", Func, 13}, - {"UserHomeDir", Func, 12}, - {"WriteFile", Func, 16}, + {"(*File).Chdir", Method, 0, ""}, + {"(*File).Chmod", Method, 0, ""}, + {"(*File).Chown", Method, 0, ""}, + {"(*File).Close", Method, 0, ""}, + {"(*File).Fd", Method, 0, ""}, + {"(*File).Name", Method, 0, ""}, + {"(*File).Read", Method, 0, ""}, + {"(*File).ReadAt", Method, 0, ""}, + {"(*File).ReadDir", Method, 16, ""}, + {"(*File).ReadFrom", Method, 15, ""}, + {"(*File).Readdir", Method, 0, ""}, + {"(*File).Readdirnames", Method, 0, ""}, + {"(*File).Seek", Method, 0, ""}, + {"(*File).SetDeadline", Method, 10, ""}, + {"(*File).SetReadDeadline", Method, 10, ""}, + {"(*File).SetWriteDeadline", Method, 10, ""}, + {"(*File).Stat", Method, 0, ""}, + {"(*File).Sync", Method, 0, ""}, + {"(*File).SyscallConn", Method, 12, ""}, + {"(*File).Truncate", Method, 0, ""}, + {"(*File).Write", Method, 0, ""}, + {"(*File).WriteAt", Method, 0, ""}, + {"(*File).WriteString", Method, 0, ""}, + {"(*File).WriteTo", Method, 22, ""}, + {"(*LinkError).Error", Method, 0, ""}, + {"(*LinkError).Unwrap", Method, 13, ""}, + {"(*PathError).Error", Method, 0, ""}, + {"(*PathError).Timeout", Method, 10, ""}, + {"(*PathError).Unwrap", Method, 13, ""}, + {"(*Process).Kill", Method, 0, ""}, + {"(*Process).Release", Method, 0, ""}, + {"(*Process).Signal", Method, 0, ""}, + {"(*Process).Wait", Method, 0, ""}, + {"(*ProcessState).ExitCode", Method, 12, ""}, + {"(*ProcessState).Exited", Method, 0, ""}, + {"(*ProcessState).Pid", Method, 0, ""}, + {"(*ProcessState).String", Method, 0, ""}, + {"(*ProcessState).Success", Method, 0, ""}, + {"(*ProcessState).Sys", Method, 0, ""}, + {"(*ProcessState).SysUsage", Method, 0, ""}, + {"(*ProcessState).SystemTime", Method, 0, ""}, + {"(*ProcessState).UserTime", Method, 0, ""}, + {"(*Root).Chmod", Method, 25, ""}, + {"(*Root).Chown", Method, 25, ""}, + {"(*Root).Chtimes", Method, 25, ""}, + {"(*Root).Close", Method, 24, ""}, + {"(*Root).Create", Method, 24, ""}, + {"(*Root).FS", Method, 24, ""}, + {"(*Root).Lchown", Method, 25, ""}, + {"(*Root).Link", Method, 25, ""}, + {"(*Root).Lstat", Method, 24, ""}, + {"(*Root).Mkdir", Method, 24, ""}, + {"(*Root).Name", Method, 24, ""}, + {"(*Root).Open", Method, 24, ""}, + {"(*Root).OpenFile", Method, 24, ""}, + {"(*Root).OpenRoot", Method, 24, ""}, + {"(*Root).Readlink", Method, 25, ""}, + {"(*Root).Remove", Method, 24, ""}, + {"(*Root).Rename", Method, 25, ""}, + {"(*Root).Stat", Method, 24, ""}, + {"(*Root).Symlink", Method, 25, ""}, + {"(*SyscallError).Error", Method, 0, ""}, + {"(*SyscallError).Timeout", Method, 10, ""}, + {"(*SyscallError).Unwrap", Method, 13, ""}, + {"(FileMode).IsDir", Method, 0, ""}, + {"(FileMode).IsRegular", Method, 1, ""}, + {"(FileMode).Perm", Method, 0, ""}, + {"(FileMode).String", Method, 0, ""}, + {"Args", Var, 0, ""}, + {"Chdir", Func, 0, "func(dir string) error"}, + {"Chmod", Func, 0, "func(name string, mode FileMode) error"}, + {"Chown", Func, 0, "func(name string, uid int, gid int) error"}, + {"Chtimes", Func, 0, "func(name string, atime time.Time, mtime time.Time) error"}, + {"Clearenv", Func, 0, "func()"}, + {"CopyFS", Func, 23, "func(dir string, fsys fs.FS) error"}, + {"Create", Func, 0, "func(name string) (*File, error)"}, + {"CreateTemp", Func, 16, "func(dir string, pattern string) (*File, error)"}, + {"DevNull", Const, 0, ""}, + {"DirEntry", Type, 16, ""}, + {"DirFS", Func, 16, "func(dir string) fs.FS"}, + {"Environ", Func, 0, "func() []string"}, + {"ErrClosed", Var, 8, ""}, + {"ErrDeadlineExceeded", Var, 15, ""}, + {"ErrExist", Var, 0, ""}, + {"ErrInvalid", Var, 0, ""}, + {"ErrNoDeadline", Var, 10, ""}, + {"ErrNotExist", Var, 0, ""}, + {"ErrPermission", Var, 0, ""}, + {"ErrProcessDone", Var, 16, ""}, + {"Executable", Func, 8, "func() (string, error)"}, + {"Exit", Func, 0, "func(code int)"}, + {"Expand", Func, 0, "func(s string, mapping func(string) string) string"}, + {"ExpandEnv", Func, 0, "func(s string) string"}, + {"File", Type, 0, ""}, + {"FileInfo", Type, 0, ""}, + {"FileMode", Type, 0, ""}, + {"FindProcess", Func, 0, "func(pid int) (*Process, error)"}, + {"Getegid", Func, 0, "func() int"}, + {"Getenv", Func, 0, "func(key string) string"}, + {"Geteuid", Func, 0, "func() int"}, + {"Getgid", Func, 0, "func() int"}, + {"Getgroups", Func, 0, "func() ([]int, error)"}, + {"Getpagesize", Func, 0, "func() int"}, + {"Getpid", Func, 0, "func() int"}, + {"Getppid", Func, 0, "func() int"}, + {"Getuid", Func, 0, "func() int"}, + {"Getwd", Func, 0, "func() (dir string, err error)"}, + {"Hostname", Func, 0, "func() (name string, err error)"}, + {"Interrupt", Var, 0, ""}, + {"IsExist", Func, 0, "func(err error) bool"}, + {"IsNotExist", Func, 0, "func(err error) bool"}, + {"IsPathSeparator", Func, 0, "func(c uint8) bool"}, + {"IsPermission", Func, 0, "func(err error) bool"}, + {"IsTimeout", Func, 10, "func(err error) bool"}, + {"Kill", Var, 0, ""}, + {"Lchown", Func, 0, "func(name string, uid int, gid int) error"}, + {"Link", Func, 0, "func(oldname string, newname string) error"}, + {"LinkError", Type, 0, ""}, + {"LinkError.Err", Field, 0, ""}, + {"LinkError.New", Field, 0, ""}, + {"LinkError.Old", Field, 0, ""}, + {"LinkError.Op", Field, 0, ""}, + {"LookupEnv", Func, 5, "func(key string) (string, bool)"}, + {"Lstat", Func, 0, "func(name string) (FileInfo, error)"}, + {"Mkdir", Func, 0, "func(name string, perm FileMode) error"}, + {"MkdirAll", Func, 0, "func(path string, perm FileMode) error"}, + {"MkdirTemp", Func, 16, "func(dir string, pattern string) (string, error)"}, + {"ModeAppend", Const, 0, ""}, + {"ModeCharDevice", Const, 0, ""}, + {"ModeDevice", Const, 0, ""}, + {"ModeDir", Const, 0, ""}, + {"ModeExclusive", Const, 0, ""}, + {"ModeIrregular", Const, 11, ""}, + {"ModeNamedPipe", Const, 0, ""}, + {"ModePerm", Const, 0, ""}, + {"ModeSetgid", Const, 0, ""}, + {"ModeSetuid", Const, 0, ""}, + {"ModeSocket", Const, 0, ""}, + {"ModeSticky", Const, 0, ""}, + {"ModeSymlink", Const, 0, ""}, + {"ModeTemporary", Const, 0, ""}, + {"ModeType", Const, 0, ""}, + {"NewFile", Func, 0, "func(fd uintptr, name string) *File"}, + {"NewSyscallError", Func, 0, "func(syscall string, err error) error"}, + {"O_APPEND", Const, 0, ""}, + {"O_CREATE", Const, 0, ""}, + {"O_EXCL", Const, 0, ""}, + {"O_RDONLY", Const, 0, ""}, + {"O_RDWR", Const, 0, ""}, + {"O_SYNC", Const, 0, ""}, + {"O_TRUNC", Const, 0, ""}, + {"O_WRONLY", Const, 0, ""}, + {"Open", Func, 0, "func(name string) (*File, error)"}, + {"OpenFile", Func, 0, "func(name string, flag int, perm FileMode) (*File, error)"}, + {"OpenInRoot", Func, 24, "func(dir string, name string) (*File, error)"}, + {"OpenRoot", Func, 24, "func(name string) (*Root, error)"}, + {"PathError", Type, 0, ""}, + {"PathError.Err", Field, 0, ""}, + {"PathError.Op", Field, 0, ""}, + {"PathError.Path", Field, 0, ""}, + {"PathListSeparator", Const, 0, ""}, + {"PathSeparator", Const, 0, ""}, + {"Pipe", Func, 0, "func() (r *File, w *File, err error)"}, + {"ProcAttr", Type, 0, ""}, + {"ProcAttr.Dir", Field, 0, ""}, + {"ProcAttr.Env", Field, 0, ""}, + {"ProcAttr.Files", Field, 0, ""}, + {"ProcAttr.Sys", Field, 0, ""}, + {"Process", Type, 0, ""}, + {"Process.Pid", Field, 0, ""}, + {"ProcessState", Type, 0, ""}, + {"ReadDir", Func, 16, "func(name string) ([]DirEntry, error)"}, + {"ReadFile", Func, 16, "func(name string) ([]byte, error)"}, + {"Readlink", Func, 0, "func(name string) (string, error)"}, + {"Remove", Func, 0, "func(name string) error"}, + {"RemoveAll", Func, 0, "func(path string) error"}, + {"Rename", Func, 0, "func(oldpath string, newpath string) error"}, + {"Root", Type, 24, ""}, + {"SEEK_CUR", Const, 0, ""}, + {"SEEK_END", Const, 0, ""}, + {"SEEK_SET", Const, 0, ""}, + {"SameFile", Func, 0, "func(fi1 FileInfo, fi2 FileInfo) bool"}, + {"Setenv", Func, 0, "func(key string, value string) error"}, + {"Signal", Type, 0, ""}, + {"StartProcess", Func, 0, "func(name string, argv []string, attr *ProcAttr) (*Process, error)"}, + {"Stat", Func, 0, "func(name string) (FileInfo, error)"}, + {"Stderr", Var, 0, ""}, + {"Stdin", Var, 0, ""}, + {"Stdout", Var, 0, ""}, + {"Symlink", Func, 0, "func(oldname string, newname string) error"}, + {"SyscallError", Type, 0, ""}, + {"SyscallError.Err", Field, 0, ""}, + {"SyscallError.Syscall", Field, 0, ""}, + {"TempDir", Func, 0, "func() string"}, + {"Truncate", Func, 0, "func(name string, size int64) error"}, + {"Unsetenv", Func, 4, "func(key string) error"}, + {"UserCacheDir", Func, 11, "func() (string, error)"}, + {"UserConfigDir", Func, 13, "func() (string, error)"}, + {"UserHomeDir", Func, 12, "func() (string, error)"}, + {"WriteFile", Func, 16, "func(name string, data []byte, perm FileMode) error"}, }, "os/exec": { - {"(*Cmd).CombinedOutput", Method, 0}, - {"(*Cmd).Environ", Method, 19}, - {"(*Cmd).Output", Method, 0}, - {"(*Cmd).Run", Method, 0}, - {"(*Cmd).Start", Method, 0}, - {"(*Cmd).StderrPipe", Method, 0}, - {"(*Cmd).StdinPipe", Method, 0}, - {"(*Cmd).StdoutPipe", Method, 0}, - {"(*Cmd).String", Method, 13}, - {"(*Cmd).Wait", Method, 0}, - {"(*Error).Error", Method, 0}, - {"(*Error).Unwrap", Method, 13}, - {"(*ExitError).Error", Method, 0}, - {"(ExitError).ExitCode", Method, 12}, - {"(ExitError).Exited", Method, 0}, - {"(ExitError).Pid", Method, 0}, - {"(ExitError).String", Method, 0}, - {"(ExitError).Success", Method, 0}, - {"(ExitError).Sys", Method, 0}, - {"(ExitError).SysUsage", Method, 0}, - {"(ExitError).SystemTime", Method, 0}, - {"(ExitError).UserTime", Method, 0}, - {"Cmd", Type, 0}, - {"Cmd.Args", Field, 0}, - {"Cmd.Cancel", Field, 20}, - {"Cmd.Dir", Field, 0}, - {"Cmd.Env", Field, 0}, - {"Cmd.Err", Field, 19}, - {"Cmd.ExtraFiles", Field, 0}, - {"Cmd.Path", Field, 0}, - {"Cmd.Process", Field, 0}, - {"Cmd.ProcessState", Field, 0}, - {"Cmd.Stderr", Field, 0}, - {"Cmd.Stdin", Field, 0}, - {"Cmd.Stdout", Field, 0}, - {"Cmd.SysProcAttr", Field, 0}, - {"Cmd.WaitDelay", Field, 20}, - {"Command", Func, 0}, - {"CommandContext", Func, 7}, - {"ErrDot", Var, 19}, - {"ErrNotFound", Var, 0}, - {"ErrWaitDelay", Var, 20}, - {"Error", Type, 0}, - {"Error.Err", Field, 0}, - {"Error.Name", Field, 0}, - {"ExitError", Type, 0}, - {"ExitError.ProcessState", Field, 0}, - {"ExitError.Stderr", Field, 6}, - {"LookPath", Func, 0}, + {"(*Cmd).CombinedOutput", Method, 0, ""}, + {"(*Cmd).Environ", Method, 19, ""}, + {"(*Cmd).Output", Method, 0, ""}, + {"(*Cmd).Run", Method, 0, ""}, + {"(*Cmd).Start", Method, 0, ""}, + {"(*Cmd).StderrPipe", Method, 0, ""}, + {"(*Cmd).StdinPipe", Method, 0, ""}, + {"(*Cmd).StdoutPipe", Method, 0, ""}, + {"(*Cmd).String", Method, 13, ""}, + {"(*Cmd).Wait", Method, 0, ""}, + {"(*Error).Error", Method, 0, ""}, + {"(*Error).Unwrap", Method, 13, ""}, + {"(*ExitError).Error", Method, 0, ""}, + {"(ExitError).ExitCode", Method, 12, ""}, + {"(ExitError).Exited", Method, 0, ""}, + {"(ExitError).Pid", Method, 0, ""}, + {"(ExitError).String", Method, 0, ""}, + {"(ExitError).Success", Method, 0, ""}, + {"(ExitError).Sys", Method, 0, ""}, + {"(ExitError).SysUsage", Method, 0, ""}, + {"(ExitError).SystemTime", Method, 0, ""}, + {"(ExitError).UserTime", Method, 0, ""}, + {"Cmd", Type, 0, ""}, + {"Cmd.Args", Field, 0, ""}, + {"Cmd.Cancel", Field, 20, ""}, + {"Cmd.Dir", Field, 0, ""}, + {"Cmd.Env", Field, 0, ""}, + {"Cmd.Err", Field, 19, ""}, + {"Cmd.ExtraFiles", Field, 0, ""}, + {"Cmd.Path", Field, 0, ""}, + {"Cmd.Process", Field, 0, ""}, + {"Cmd.ProcessState", Field, 0, ""}, + {"Cmd.Stderr", Field, 0, ""}, + {"Cmd.Stdin", Field, 0, ""}, + {"Cmd.Stdout", Field, 0, ""}, + {"Cmd.SysProcAttr", Field, 0, ""}, + {"Cmd.WaitDelay", Field, 20, ""}, + {"Command", Func, 0, "func(name string, arg ...string) *Cmd"}, + {"CommandContext", Func, 7, "func(ctx context.Context, name string, arg ...string) *Cmd"}, + {"ErrDot", Var, 19, ""}, + {"ErrNotFound", Var, 0, ""}, + {"ErrWaitDelay", Var, 20, ""}, + {"Error", Type, 0, ""}, + {"Error.Err", Field, 0, ""}, + {"Error.Name", Field, 0, ""}, + {"ExitError", Type, 0, ""}, + {"ExitError.ProcessState", Field, 0, ""}, + {"ExitError.Stderr", Field, 6, ""}, + {"LookPath", Func, 0, "func(file string) (string, error)"}, }, "os/signal": { - {"Ignore", Func, 5}, - {"Ignored", Func, 11}, - {"Notify", Func, 0}, - {"NotifyContext", Func, 16}, - {"Reset", Func, 5}, - {"Stop", Func, 1}, + {"Ignore", Func, 5, "func(sig ...os.Signal)"}, + {"Ignored", Func, 11, "func(sig os.Signal) bool"}, + {"Notify", Func, 0, "func(c chan<- os.Signal, sig ...os.Signal)"}, + {"NotifyContext", Func, 16, "func(parent context.Context, signals ...os.Signal) (ctx context.Context, stop context.CancelFunc)"}, + {"Reset", Func, 5, "func(sig ...os.Signal)"}, + {"Stop", Func, 1, "func(c chan<- os.Signal)"}, }, "os/user": { - {"(*User).GroupIds", Method, 7}, - {"(UnknownGroupError).Error", Method, 7}, - {"(UnknownGroupIdError).Error", Method, 7}, - {"(UnknownUserError).Error", Method, 0}, - {"(UnknownUserIdError).Error", Method, 0}, - {"Current", Func, 0}, - {"Group", Type, 7}, - {"Group.Gid", Field, 7}, - {"Group.Name", Field, 7}, - {"Lookup", Func, 0}, - {"LookupGroup", Func, 7}, - {"LookupGroupId", Func, 7}, - {"LookupId", Func, 0}, - {"UnknownGroupError", Type, 7}, - {"UnknownGroupIdError", Type, 7}, - {"UnknownUserError", Type, 0}, - {"UnknownUserIdError", Type, 0}, - {"User", Type, 0}, - {"User.Gid", Field, 0}, - {"User.HomeDir", Field, 0}, - {"User.Name", Field, 0}, - {"User.Uid", Field, 0}, - {"User.Username", Field, 0}, + {"(*User).GroupIds", Method, 7, ""}, + {"(UnknownGroupError).Error", Method, 7, ""}, + {"(UnknownGroupIdError).Error", Method, 7, ""}, + {"(UnknownUserError).Error", Method, 0, ""}, + {"(UnknownUserIdError).Error", Method, 0, ""}, + {"Current", Func, 0, "func() (*User, error)"}, + {"Group", Type, 7, ""}, + {"Group.Gid", Field, 7, ""}, + {"Group.Name", Field, 7, ""}, + {"Lookup", Func, 0, "func(username string) (*User, error)"}, + {"LookupGroup", Func, 7, "func(name string) (*Group, error)"}, + {"LookupGroupId", Func, 7, "func(gid string) (*Group, error)"}, + {"LookupId", Func, 0, "func(uid string) (*User, error)"}, + {"UnknownGroupError", Type, 7, ""}, + {"UnknownGroupIdError", Type, 7, ""}, + {"UnknownUserError", Type, 0, ""}, + {"UnknownUserIdError", Type, 0, ""}, + {"User", Type, 0, ""}, + {"User.Gid", Field, 0, ""}, + {"User.HomeDir", Field, 0, ""}, + {"User.Name", Field, 0, ""}, + {"User.Uid", Field, 0, ""}, + {"User.Username", Field, 0, ""}, }, "path": { - {"Base", Func, 0}, - {"Clean", Func, 0}, - {"Dir", Func, 0}, - {"ErrBadPattern", Var, 0}, - {"Ext", Func, 0}, - {"IsAbs", Func, 0}, - {"Join", Func, 0}, - {"Match", Func, 0}, - {"Split", Func, 0}, + {"Base", Func, 0, "func(path string) string"}, + {"Clean", Func, 0, "func(path string) string"}, + {"Dir", Func, 0, "func(path string) string"}, + {"ErrBadPattern", Var, 0, ""}, + {"Ext", Func, 0, "func(path string) string"}, + {"IsAbs", Func, 0, "func(path string) bool"}, + {"Join", Func, 0, "func(elem ...string) string"}, + {"Match", Func, 0, "func(pattern string, name string) (matched bool, err error)"}, + {"Split", Func, 0, "func(path string) (dir string, file string)"}, }, "path/filepath": { - {"Abs", Func, 0}, - {"Base", Func, 0}, - {"Clean", Func, 0}, - {"Dir", Func, 0}, - {"ErrBadPattern", Var, 0}, - {"EvalSymlinks", Func, 0}, - {"Ext", Func, 0}, - {"FromSlash", Func, 0}, - {"Glob", Func, 0}, - {"HasPrefix", Func, 0}, - {"IsAbs", Func, 0}, - {"IsLocal", Func, 20}, - {"Join", Func, 0}, - {"ListSeparator", Const, 0}, - {"Localize", Func, 23}, - {"Match", Func, 0}, - {"Rel", Func, 0}, - {"Separator", Const, 0}, - {"SkipAll", Var, 20}, - {"SkipDir", Var, 0}, - {"Split", Func, 0}, - {"SplitList", Func, 0}, - {"ToSlash", Func, 0}, - {"VolumeName", Func, 0}, - {"Walk", Func, 0}, - {"WalkDir", Func, 16}, - {"WalkFunc", Type, 0}, + {"Abs", Func, 0, "func(path string) (string, error)"}, + {"Base", Func, 0, "func(path string) string"}, + {"Clean", Func, 0, "func(path string) string"}, + {"Dir", Func, 0, "func(path string) string"}, + {"ErrBadPattern", Var, 0, ""}, + {"EvalSymlinks", Func, 0, "func(path string) (string, error)"}, + {"Ext", Func, 0, "func(path string) string"}, + {"FromSlash", Func, 0, "func(path string) string"}, + {"Glob", Func, 0, "func(pattern string) (matches []string, err error)"}, + {"HasPrefix", Func, 0, "func(p string, prefix string) bool"}, + {"IsAbs", Func, 0, "func(path string) bool"}, + {"IsLocal", Func, 20, "func(path string) bool"}, + {"Join", Func, 0, "func(elem ...string) string"}, + {"ListSeparator", Const, 0, ""}, + {"Localize", Func, 23, "func(path string) (string, error)"}, + {"Match", Func, 0, "func(pattern string, name string) (matched bool, err error)"}, + {"Rel", Func, 0, "func(basepath string, targpath string) (string, error)"}, + {"Separator", Const, 0, ""}, + {"SkipAll", Var, 20, ""}, + {"SkipDir", Var, 0, ""}, + {"Split", Func, 0, "func(path string) (dir string, file string)"}, + {"SplitList", Func, 0, "func(path string) []string"}, + {"ToSlash", Func, 0, "func(path string) string"}, + {"VolumeName", Func, 0, "func(path string) string"}, + {"Walk", Func, 0, "func(root string, fn WalkFunc) error"}, + {"WalkDir", Func, 16, "func(root string, fn fs.WalkDirFunc) error"}, + {"WalkFunc", Type, 0, ""}, }, "plugin": { - {"(*Plugin).Lookup", Method, 8}, - {"Open", Func, 8}, - {"Plugin", Type, 8}, - {"Symbol", Type, 8}, + {"(*Plugin).Lookup", Method, 8, ""}, + {"Open", Func, 8, "func(path string) (*Plugin, error)"}, + {"Plugin", Type, 8, ""}, + {"Symbol", Type, 8, ""}, }, "reflect": { - {"(*MapIter).Key", Method, 12}, - {"(*MapIter).Next", Method, 12}, - {"(*MapIter).Reset", Method, 18}, - {"(*MapIter).Value", Method, 12}, - {"(*ValueError).Error", Method, 0}, - {"(ChanDir).String", Method, 0}, - {"(Kind).String", Method, 0}, - {"(Method).IsExported", Method, 17}, - {"(StructField).IsExported", Method, 17}, - {"(StructTag).Get", Method, 0}, - {"(StructTag).Lookup", Method, 7}, - {"(Value).Addr", Method, 0}, - {"(Value).Bool", Method, 0}, - {"(Value).Bytes", Method, 0}, - {"(Value).Call", Method, 0}, - {"(Value).CallSlice", Method, 0}, - {"(Value).CanAddr", Method, 0}, - {"(Value).CanComplex", Method, 18}, - {"(Value).CanConvert", Method, 17}, - {"(Value).CanFloat", Method, 18}, - {"(Value).CanInt", Method, 18}, - {"(Value).CanInterface", Method, 0}, - {"(Value).CanSet", Method, 0}, - {"(Value).CanUint", Method, 18}, - {"(Value).Cap", Method, 0}, - {"(Value).Clear", Method, 21}, - {"(Value).Close", Method, 0}, - {"(Value).Comparable", Method, 20}, - {"(Value).Complex", Method, 0}, - {"(Value).Convert", Method, 1}, - {"(Value).Elem", Method, 0}, - {"(Value).Equal", Method, 20}, - {"(Value).Field", Method, 0}, - {"(Value).FieldByIndex", Method, 0}, - {"(Value).FieldByIndexErr", Method, 18}, - {"(Value).FieldByName", Method, 0}, - {"(Value).FieldByNameFunc", Method, 0}, - {"(Value).Float", Method, 0}, - {"(Value).Grow", Method, 20}, - {"(Value).Index", Method, 0}, - {"(Value).Int", Method, 0}, - {"(Value).Interface", Method, 0}, - {"(Value).InterfaceData", Method, 0}, - {"(Value).IsNil", Method, 0}, - {"(Value).IsValid", Method, 0}, - {"(Value).IsZero", Method, 13}, - {"(Value).Kind", Method, 0}, - {"(Value).Len", Method, 0}, - {"(Value).MapIndex", Method, 0}, - {"(Value).MapKeys", Method, 0}, - {"(Value).MapRange", Method, 12}, - {"(Value).Method", Method, 0}, - {"(Value).MethodByName", Method, 0}, - {"(Value).NumField", Method, 0}, - {"(Value).NumMethod", Method, 0}, - {"(Value).OverflowComplex", Method, 0}, - {"(Value).OverflowFloat", Method, 0}, - {"(Value).OverflowInt", Method, 0}, - {"(Value).OverflowUint", Method, 0}, - {"(Value).Pointer", Method, 0}, - {"(Value).Recv", Method, 0}, - {"(Value).Send", Method, 0}, - {"(Value).Seq", Method, 23}, - {"(Value).Seq2", Method, 23}, - {"(Value).Set", Method, 0}, - {"(Value).SetBool", Method, 0}, - {"(Value).SetBytes", Method, 0}, - {"(Value).SetCap", Method, 2}, - {"(Value).SetComplex", Method, 0}, - {"(Value).SetFloat", Method, 0}, - {"(Value).SetInt", Method, 0}, - {"(Value).SetIterKey", Method, 18}, - {"(Value).SetIterValue", Method, 18}, - {"(Value).SetLen", Method, 0}, - {"(Value).SetMapIndex", Method, 0}, - {"(Value).SetPointer", Method, 0}, - {"(Value).SetString", Method, 0}, - {"(Value).SetUint", Method, 0}, - {"(Value).SetZero", Method, 20}, - {"(Value).Slice", Method, 0}, - {"(Value).Slice3", Method, 2}, - {"(Value).String", Method, 0}, - {"(Value).TryRecv", Method, 0}, - {"(Value).TrySend", Method, 0}, - {"(Value).Type", Method, 0}, - {"(Value).Uint", Method, 0}, - {"(Value).UnsafeAddr", Method, 0}, - {"(Value).UnsafePointer", Method, 18}, - {"Append", Func, 0}, - {"AppendSlice", Func, 0}, - {"Array", Const, 0}, - {"ArrayOf", Func, 5}, - {"Bool", Const, 0}, - {"BothDir", Const, 0}, - {"Chan", Const, 0}, - {"ChanDir", Type, 0}, - {"ChanOf", Func, 1}, - {"Complex128", Const, 0}, - {"Complex64", Const, 0}, - {"Copy", Func, 0}, - {"DeepEqual", Func, 0}, - {"Float32", Const, 0}, - {"Float64", Const, 0}, - {"Func", Const, 0}, - {"FuncOf", Func, 5}, - {"Indirect", Func, 0}, - {"Int", Const, 0}, - {"Int16", Const, 0}, - {"Int32", Const, 0}, - {"Int64", Const, 0}, - {"Int8", Const, 0}, - {"Interface", Const, 0}, - {"Invalid", Const, 0}, - {"Kind", Type, 0}, - {"MakeChan", Func, 0}, - {"MakeFunc", Func, 1}, - {"MakeMap", Func, 0}, - {"MakeMapWithSize", Func, 9}, - {"MakeSlice", Func, 0}, - {"Map", Const, 0}, - {"MapIter", Type, 12}, - {"MapOf", Func, 1}, - {"Method", Type, 0}, - {"Method.Func", Field, 0}, - {"Method.Index", Field, 0}, - {"Method.Name", Field, 0}, - {"Method.PkgPath", Field, 0}, - {"Method.Type", Field, 0}, - {"New", Func, 0}, - {"NewAt", Func, 0}, - {"Pointer", Const, 18}, - {"PointerTo", Func, 18}, - {"Ptr", Const, 0}, - {"PtrTo", Func, 0}, - {"RecvDir", Const, 0}, - {"Select", Func, 1}, - {"SelectCase", Type, 1}, - {"SelectCase.Chan", Field, 1}, - {"SelectCase.Dir", Field, 1}, - {"SelectCase.Send", Field, 1}, - {"SelectDefault", Const, 1}, - {"SelectDir", Type, 1}, - {"SelectRecv", Const, 1}, - {"SelectSend", Const, 1}, - {"SendDir", Const, 0}, - {"Slice", Const, 0}, - {"SliceAt", Func, 23}, - {"SliceHeader", Type, 0}, - {"SliceHeader.Cap", Field, 0}, - {"SliceHeader.Data", Field, 0}, - {"SliceHeader.Len", Field, 0}, - {"SliceOf", Func, 1}, - {"String", Const, 0}, - {"StringHeader", Type, 0}, - {"StringHeader.Data", Field, 0}, - {"StringHeader.Len", Field, 0}, - {"Struct", Const, 0}, - {"StructField", Type, 0}, - {"StructField.Anonymous", Field, 0}, - {"StructField.Index", Field, 0}, - {"StructField.Name", Field, 0}, - {"StructField.Offset", Field, 0}, - {"StructField.PkgPath", Field, 0}, - {"StructField.Tag", Field, 0}, - {"StructField.Type", Field, 0}, - {"StructOf", Func, 7}, - {"StructTag", Type, 0}, - {"Swapper", Func, 8}, - {"Type", Type, 0}, - {"TypeFor", Func, 22}, - {"TypeOf", Func, 0}, - {"Uint", Const, 0}, - {"Uint16", Const, 0}, - {"Uint32", Const, 0}, - {"Uint64", Const, 0}, - {"Uint8", Const, 0}, - {"Uintptr", Const, 0}, - {"UnsafePointer", Const, 0}, - {"Value", Type, 0}, - {"ValueError", Type, 0}, - {"ValueError.Kind", Field, 0}, - {"ValueError.Method", Field, 0}, - {"ValueOf", Func, 0}, - {"VisibleFields", Func, 17}, - {"Zero", Func, 0}, + {"(*MapIter).Key", Method, 12, ""}, + {"(*MapIter).Next", Method, 12, ""}, + {"(*MapIter).Reset", Method, 18, ""}, + {"(*MapIter).Value", Method, 12, ""}, + {"(*ValueError).Error", Method, 0, ""}, + {"(ChanDir).String", Method, 0, ""}, + {"(Kind).String", Method, 0, ""}, + {"(Method).IsExported", Method, 17, ""}, + {"(StructField).IsExported", Method, 17, ""}, + {"(StructTag).Get", Method, 0, ""}, + {"(StructTag).Lookup", Method, 7, ""}, + {"(Value).Addr", Method, 0, ""}, + {"(Value).Bool", Method, 0, ""}, + {"(Value).Bytes", Method, 0, ""}, + {"(Value).Call", Method, 0, ""}, + {"(Value).CallSlice", Method, 0, ""}, + {"(Value).CanAddr", Method, 0, ""}, + {"(Value).CanComplex", Method, 18, ""}, + {"(Value).CanConvert", Method, 17, ""}, + {"(Value).CanFloat", Method, 18, ""}, + {"(Value).CanInt", Method, 18, ""}, + {"(Value).CanInterface", Method, 0, ""}, + {"(Value).CanSet", Method, 0, ""}, + {"(Value).CanUint", Method, 18, ""}, + {"(Value).Cap", Method, 0, ""}, + {"(Value).Clear", Method, 21, ""}, + {"(Value).Close", Method, 0, ""}, + {"(Value).Comparable", Method, 20, ""}, + {"(Value).Complex", Method, 0, ""}, + {"(Value).Convert", Method, 1, ""}, + {"(Value).Elem", Method, 0, ""}, + {"(Value).Equal", Method, 20, ""}, + {"(Value).Field", Method, 0, ""}, + {"(Value).FieldByIndex", Method, 0, ""}, + {"(Value).FieldByIndexErr", Method, 18, ""}, + {"(Value).FieldByName", Method, 0, ""}, + {"(Value).FieldByNameFunc", Method, 0, ""}, + {"(Value).Float", Method, 0, ""}, + {"(Value).Grow", Method, 20, ""}, + {"(Value).Index", Method, 0, ""}, + {"(Value).Int", Method, 0, ""}, + {"(Value).Interface", Method, 0, ""}, + {"(Value).InterfaceData", Method, 0, ""}, + {"(Value).IsNil", Method, 0, ""}, + {"(Value).IsValid", Method, 0, ""}, + {"(Value).IsZero", Method, 13, ""}, + {"(Value).Kind", Method, 0, ""}, + {"(Value).Len", Method, 0, ""}, + {"(Value).MapIndex", Method, 0, ""}, + {"(Value).MapKeys", Method, 0, ""}, + {"(Value).MapRange", Method, 12, ""}, + {"(Value).Method", Method, 0, ""}, + {"(Value).MethodByName", Method, 0, ""}, + {"(Value).NumField", Method, 0, ""}, + {"(Value).NumMethod", Method, 0, ""}, + {"(Value).OverflowComplex", Method, 0, ""}, + {"(Value).OverflowFloat", Method, 0, ""}, + {"(Value).OverflowInt", Method, 0, ""}, + {"(Value).OverflowUint", Method, 0, ""}, + {"(Value).Pointer", Method, 0, ""}, + {"(Value).Recv", Method, 0, ""}, + {"(Value).Send", Method, 0, ""}, + {"(Value).Seq", Method, 23, ""}, + {"(Value).Seq2", Method, 23, ""}, + {"(Value).Set", Method, 0, ""}, + {"(Value).SetBool", Method, 0, ""}, + {"(Value).SetBytes", Method, 0, ""}, + {"(Value).SetCap", Method, 2, ""}, + {"(Value).SetComplex", Method, 0, ""}, + {"(Value).SetFloat", Method, 0, ""}, + {"(Value).SetInt", Method, 0, ""}, + {"(Value).SetIterKey", Method, 18, ""}, + {"(Value).SetIterValue", Method, 18, ""}, + {"(Value).SetLen", Method, 0, ""}, + {"(Value).SetMapIndex", Method, 0, ""}, + {"(Value).SetPointer", Method, 0, ""}, + {"(Value).SetString", Method, 0, ""}, + {"(Value).SetUint", Method, 0, ""}, + {"(Value).SetZero", Method, 20, ""}, + {"(Value).Slice", Method, 0, ""}, + {"(Value).Slice3", Method, 2, ""}, + {"(Value).String", Method, 0, ""}, + {"(Value).TryRecv", Method, 0, ""}, + {"(Value).TrySend", Method, 0, ""}, + {"(Value).Type", Method, 0, ""}, + {"(Value).Uint", Method, 0, ""}, + {"(Value).UnsafeAddr", Method, 0, ""}, + {"(Value).UnsafePointer", Method, 18, ""}, + {"Append", Func, 0, "func(s Value, x ...Value) Value"}, + {"AppendSlice", Func, 0, "func(s Value, t Value) Value"}, + {"Array", Const, 0, ""}, + {"ArrayOf", Func, 5, "func(length int, elem Type) Type"}, + {"Bool", Const, 0, ""}, + {"BothDir", Const, 0, ""}, + {"Chan", Const, 0, ""}, + {"ChanDir", Type, 0, ""}, + {"ChanOf", Func, 1, "func(dir ChanDir, t Type) Type"}, + {"Complex128", Const, 0, ""}, + {"Complex64", Const, 0, ""}, + {"Copy", Func, 0, "func(dst Value, src Value) int"}, + {"DeepEqual", Func, 0, "func(x any, y any) bool"}, + {"Float32", Const, 0, ""}, + {"Float64", Const, 0, ""}, + {"Func", Const, 0, ""}, + {"FuncOf", Func, 5, "func(in []Type, out []Type, variadic bool) Type"}, + {"Indirect", Func, 0, "func(v Value) Value"}, + {"Int", Const, 0, ""}, + {"Int16", Const, 0, ""}, + {"Int32", Const, 0, ""}, + {"Int64", Const, 0, ""}, + {"Int8", Const, 0, ""}, + {"Interface", Const, 0, ""}, + {"Invalid", Const, 0, ""}, + {"Kind", Type, 0, ""}, + {"MakeChan", Func, 0, "func(typ Type, buffer int) Value"}, + {"MakeFunc", Func, 1, "func(typ Type, fn func(args []Value) (results []Value)) Value"}, + {"MakeMap", Func, 0, "func(typ Type) Value"}, + {"MakeMapWithSize", Func, 9, "func(typ Type, n int) Value"}, + {"MakeSlice", Func, 0, "func(typ Type, len int, cap int) Value"}, + {"Map", Const, 0, ""}, + {"MapIter", Type, 12, ""}, + {"MapOf", Func, 1, "func(key Type, elem Type) Type"}, + {"Method", Type, 0, ""}, + {"Method.Func", Field, 0, ""}, + {"Method.Index", Field, 0, ""}, + {"Method.Name", Field, 0, ""}, + {"Method.PkgPath", Field, 0, ""}, + {"Method.Type", Field, 0, ""}, + {"New", Func, 0, "func(typ Type) Value"}, + {"NewAt", Func, 0, "func(typ Type, p unsafe.Pointer) Value"}, + {"Pointer", Const, 18, ""}, + {"PointerTo", Func, 18, "func(t Type) Type"}, + {"Ptr", Const, 0, ""}, + {"PtrTo", Func, 0, "func(t Type) Type"}, + {"RecvDir", Const, 0, ""}, + {"Select", Func, 1, "func(cases []SelectCase) (chosen int, recv Value, recvOK bool)"}, + {"SelectCase", Type, 1, ""}, + {"SelectCase.Chan", Field, 1, ""}, + {"SelectCase.Dir", Field, 1, ""}, + {"SelectCase.Send", Field, 1, ""}, + {"SelectDefault", Const, 1, ""}, + {"SelectDir", Type, 1, ""}, + {"SelectRecv", Const, 1, ""}, + {"SelectSend", Const, 1, ""}, + {"SendDir", Const, 0, ""}, + {"Slice", Const, 0, ""}, + {"SliceAt", Func, 23, "func(typ Type, p unsafe.Pointer, n int) Value"}, + {"SliceHeader", Type, 0, ""}, + {"SliceHeader.Cap", Field, 0, ""}, + {"SliceHeader.Data", Field, 0, ""}, + {"SliceHeader.Len", Field, 0, ""}, + {"SliceOf", Func, 1, "func(t Type) Type"}, + {"String", Const, 0, ""}, + {"StringHeader", Type, 0, ""}, + {"StringHeader.Data", Field, 0, ""}, + {"StringHeader.Len", Field, 0, ""}, + {"Struct", Const, 0, ""}, + {"StructField", Type, 0, ""}, + {"StructField.Anonymous", Field, 0, ""}, + {"StructField.Index", Field, 0, ""}, + {"StructField.Name", Field, 0, ""}, + {"StructField.Offset", Field, 0, ""}, + {"StructField.PkgPath", Field, 0, ""}, + {"StructField.Tag", Field, 0, ""}, + {"StructField.Type", Field, 0, ""}, + {"StructOf", Func, 7, "func(fields []StructField) Type"}, + {"StructTag", Type, 0, ""}, + {"Swapper", Func, 8, "func(slice any) func(i int, j int)"}, + {"Type", Type, 0, ""}, + {"TypeFor", Func, 22, "func[T any]() Type"}, + {"TypeOf", Func, 0, "func(i any) Type"}, + {"Uint", Const, 0, ""}, + {"Uint16", Const, 0, ""}, + {"Uint32", Const, 0, ""}, + {"Uint64", Const, 0, ""}, + {"Uint8", Const, 0, ""}, + {"Uintptr", Const, 0, ""}, + {"UnsafePointer", Const, 0, ""}, + {"Value", Type, 0, ""}, + {"ValueError", Type, 0, ""}, + {"ValueError.Kind", Field, 0, ""}, + {"ValueError.Method", Field, 0, ""}, + {"ValueOf", Func, 0, "func(i any) Value"}, + {"VisibleFields", Func, 17, "func(t Type) []StructField"}, + {"Zero", Func, 0, "func(typ Type) Value"}, }, "regexp": { - {"(*Regexp).AppendText", Method, 24}, - {"(*Regexp).Copy", Method, 6}, - {"(*Regexp).Expand", Method, 0}, - {"(*Regexp).ExpandString", Method, 0}, - {"(*Regexp).Find", Method, 0}, - {"(*Regexp).FindAll", Method, 0}, - {"(*Regexp).FindAllIndex", Method, 0}, - {"(*Regexp).FindAllString", Method, 0}, - {"(*Regexp).FindAllStringIndex", Method, 0}, - {"(*Regexp).FindAllStringSubmatch", Method, 0}, - {"(*Regexp).FindAllStringSubmatchIndex", Method, 0}, - {"(*Regexp).FindAllSubmatch", Method, 0}, - {"(*Regexp).FindAllSubmatchIndex", Method, 0}, - {"(*Regexp).FindIndex", Method, 0}, - {"(*Regexp).FindReaderIndex", Method, 0}, - {"(*Regexp).FindReaderSubmatchIndex", Method, 0}, - {"(*Regexp).FindString", Method, 0}, - {"(*Regexp).FindStringIndex", Method, 0}, - {"(*Regexp).FindStringSubmatch", Method, 0}, - {"(*Regexp).FindStringSubmatchIndex", Method, 0}, - {"(*Regexp).FindSubmatch", Method, 0}, - {"(*Regexp).FindSubmatchIndex", Method, 0}, - {"(*Regexp).LiteralPrefix", Method, 0}, - {"(*Regexp).Longest", Method, 1}, - {"(*Regexp).MarshalText", Method, 21}, - {"(*Regexp).Match", Method, 0}, - {"(*Regexp).MatchReader", Method, 0}, - {"(*Regexp).MatchString", Method, 0}, - {"(*Regexp).NumSubexp", Method, 0}, - {"(*Regexp).ReplaceAll", Method, 0}, - {"(*Regexp).ReplaceAllFunc", Method, 0}, - {"(*Regexp).ReplaceAllLiteral", Method, 0}, - {"(*Regexp).ReplaceAllLiteralString", Method, 0}, - {"(*Regexp).ReplaceAllString", Method, 0}, - {"(*Regexp).ReplaceAllStringFunc", Method, 0}, - {"(*Regexp).Split", Method, 1}, - {"(*Regexp).String", Method, 0}, - {"(*Regexp).SubexpIndex", Method, 15}, - {"(*Regexp).SubexpNames", Method, 0}, - {"(*Regexp).UnmarshalText", Method, 21}, - {"Compile", Func, 0}, - {"CompilePOSIX", Func, 0}, - {"Match", Func, 0}, - {"MatchReader", Func, 0}, - {"MatchString", Func, 0}, - {"MustCompile", Func, 0}, - {"MustCompilePOSIX", Func, 0}, - {"QuoteMeta", Func, 0}, - {"Regexp", Type, 0}, + {"(*Regexp).AppendText", Method, 24, ""}, + {"(*Regexp).Copy", Method, 6, ""}, + {"(*Regexp).Expand", Method, 0, ""}, + {"(*Regexp).ExpandString", Method, 0, ""}, + {"(*Regexp).Find", Method, 0, ""}, + {"(*Regexp).FindAll", Method, 0, ""}, + {"(*Regexp).FindAllIndex", Method, 0, ""}, + {"(*Regexp).FindAllString", Method, 0, ""}, + {"(*Regexp).FindAllStringIndex", Method, 0, ""}, + {"(*Regexp).FindAllStringSubmatch", Method, 0, ""}, + {"(*Regexp).FindAllStringSubmatchIndex", Method, 0, ""}, + {"(*Regexp).FindAllSubmatch", Method, 0, ""}, + {"(*Regexp).FindAllSubmatchIndex", Method, 0, ""}, + {"(*Regexp).FindIndex", Method, 0, ""}, + {"(*Regexp).FindReaderIndex", Method, 0, ""}, + {"(*Regexp).FindReaderSubmatchIndex", Method, 0, ""}, + {"(*Regexp).FindString", Method, 0, ""}, + {"(*Regexp).FindStringIndex", Method, 0, ""}, + {"(*Regexp).FindStringSubmatch", Method, 0, ""}, + {"(*Regexp).FindStringSubmatchIndex", Method, 0, ""}, + {"(*Regexp).FindSubmatch", Method, 0, ""}, + {"(*Regexp).FindSubmatchIndex", Method, 0, ""}, + {"(*Regexp).LiteralPrefix", Method, 0, ""}, + {"(*Regexp).Longest", Method, 1, ""}, + {"(*Regexp).MarshalText", Method, 21, ""}, + {"(*Regexp).Match", Method, 0, ""}, + {"(*Regexp).MatchReader", Method, 0, ""}, + {"(*Regexp).MatchString", Method, 0, ""}, + {"(*Regexp).NumSubexp", Method, 0, ""}, + {"(*Regexp).ReplaceAll", Method, 0, ""}, + {"(*Regexp).ReplaceAllFunc", Method, 0, ""}, + {"(*Regexp).ReplaceAllLiteral", Method, 0, ""}, + {"(*Regexp).ReplaceAllLiteralString", Method, 0, ""}, + {"(*Regexp).ReplaceAllString", Method, 0, ""}, + {"(*Regexp).ReplaceAllStringFunc", Method, 0, ""}, + {"(*Regexp).Split", Method, 1, ""}, + {"(*Regexp).String", Method, 0, ""}, + {"(*Regexp).SubexpIndex", Method, 15, ""}, + {"(*Regexp).SubexpNames", Method, 0, ""}, + {"(*Regexp).UnmarshalText", Method, 21, ""}, + {"Compile", Func, 0, "func(expr string) (*Regexp, error)"}, + {"CompilePOSIX", Func, 0, "func(expr string) (*Regexp, error)"}, + {"Match", Func, 0, "func(pattern string, b []byte) (matched bool, err error)"}, + {"MatchReader", Func, 0, "func(pattern string, r io.RuneReader) (matched bool, err error)"}, + {"MatchString", Func, 0, "func(pattern string, s string) (matched bool, err error)"}, + {"MustCompile", Func, 0, "func(str string) *Regexp"}, + {"MustCompilePOSIX", Func, 0, "func(str string) *Regexp"}, + {"QuoteMeta", Func, 0, "func(s string) string"}, + {"Regexp", Type, 0, ""}, }, "regexp/syntax": { - {"(*Error).Error", Method, 0}, - {"(*Inst).MatchEmptyWidth", Method, 0}, - {"(*Inst).MatchRune", Method, 0}, - {"(*Inst).MatchRunePos", Method, 3}, - {"(*Inst).String", Method, 0}, - {"(*Prog).Prefix", Method, 0}, - {"(*Prog).StartCond", Method, 0}, - {"(*Prog).String", Method, 0}, - {"(*Regexp).CapNames", Method, 0}, - {"(*Regexp).Equal", Method, 0}, - {"(*Regexp).MaxCap", Method, 0}, - {"(*Regexp).Simplify", Method, 0}, - {"(*Regexp).String", Method, 0}, - {"(ErrorCode).String", Method, 0}, - {"(InstOp).String", Method, 3}, - {"(Op).String", Method, 11}, - {"ClassNL", Const, 0}, - {"Compile", Func, 0}, - {"DotNL", Const, 0}, - {"EmptyBeginLine", Const, 0}, - {"EmptyBeginText", Const, 0}, - {"EmptyEndLine", Const, 0}, - {"EmptyEndText", Const, 0}, - {"EmptyNoWordBoundary", Const, 0}, - {"EmptyOp", Type, 0}, - {"EmptyOpContext", Func, 0}, - {"EmptyWordBoundary", Const, 0}, - {"ErrInternalError", Const, 0}, - {"ErrInvalidCharClass", Const, 0}, - {"ErrInvalidCharRange", Const, 0}, - {"ErrInvalidEscape", Const, 0}, - {"ErrInvalidNamedCapture", Const, 0}, - {"ErrInvalidPerlOp", Const, 0}, - {"ErrInvalidRepeatOp", Const, 0}, - {"ErrInvalidRepeatSize", Const, 0}, - {"ErrInvalidUTF8", Const, 0}, - {"ErrLarge", Const, 20}, - {"ErrMissingBracket", Const, 0}, - {"ErrMissingParen", Const, 0}, - {"ErrMissingRepeatArgument", Const, 0}, - {"ErrNestingDepth", Const, 19}, - {"ErrTrailingBackslash", Const, 0}, - {"ErrUnexpectedParen", Const, 1}, - {"Error", Type, 0}, - {"Error.Code", Field, 0}, - {"Error.Expr", Field, 0}, - {"ErrorCode", Type, 0}, - {"Flags", Type, 0}, - {"FoldCase", Const, 0}, - {"Inst", Type, 0}, - {"Inst.Arg", Field, 0}, - {"Inst.Op", Field, 0}, - {"Inst.Out", Field, 0}, - {"Inst.Rune", Field, 0}, - {"InstAlt", Const, 0}, - {"InstAltMatch", Const, 0}, - {"InstCapture", Const, 0}, - {"InstEmptyWidth", Const, 0}, - {"InstFail", Const, 0}, - {"InstMatch", Const, 0}, - {"InstNop", Const, 0}, - {"InstOp", Type, 0}, - {"InstRune", Const, 0}, - {"InstRune1", Const, 0}, - {"InstRuneAny", Const, 0}, - {"InstRuneAnyNotNL", Const, 0}, - {"IsWordChar", Func, 0}, - {"Literal", Const, 0}, - {"MatchNL", Const, 0}, - {"NonGreedy", Const, 0}, - {"OneLine", Const, 0}, - {"Op", Type, 0}, - {"OpAlternate", Const, 0}, - {"OpAnyChar", Const, 0}, - {"OpAnyCharNotNL", Const, 0}, - {"OpBeginLine", Const, 0}, - {"OpBeginText", Const, 0}, - {"OpCapture", Const, 0}, - {"OpCharClass", Const, 0}, - {"OpConcat", Const, 0}, - {"OpEmptyMatch", Const, 0}, - {"OpEndLine", Const, 0}, - {"OpEndText", Const, 0}, - {"OpLiteral", Const, 0}, - {"OpNoMatch", Const, 0}, - {"OpNoWordBoundary", Const, 0}, - {"OpPlus", Const, 0}, - {"OpQuest", Const, 0}, - {"OpRepeat", Const, 0}, - {"OpStar", Const, 0}, - {"OpWordBoundary", Const, 0}, - {"POSIX", Const, 0}, - {"Parse", Func, 0}, - {"Perl", Const, 0}, - {"PerlX", Const, 0}, - {"Prog", Type, 0}, - {"Prog.Inst", Field, 0}, - {"Prog.NumCap", Field, 0}, - {"Prog.Start", Field, 0}, - {"Regexp", Type, 0}, - {"Regexp.Cap", Field, 0}, - {"Regexp.Flags", Field, 0}, - {"Regexp.Max", Field, 0}, - {"Regexp.Min", Field, 0}, - {"Regexp.Name", Field, 0}, - {"Regexp.Op", Field, 0}, - {"Regexp.Rune", Field, 0}, - {"Regexp.Rune0", Field, 0}, - {"Regexp.Sub", Field, 0}, - {"Regexp.Sub0", Field, 0}, - {"Simple", Const, 0}, - {"UnicodeGroups", Const, 0}, - {"WasDollar", Const, 0}, + {"(*Error).Error", Method, 0, ""}, + {"(*Inst).MatchEmptyWidth", Method, 0, ""}, + {"(*Inst).MatchRune", Method, 0, ""}, + {"(*Inst).MatchRunePos", Method, 3, ""}, + {"(*Inst).String", Method, 0, ""}, + {"(*Prog).Prefix", Method, 0, ""}, + {"(*Prog).StartCond", Method, 0, ""}, + {"(*Prog).String", Method, 0, ""}, + {"(*Regexp).CapNames", Method, 0, ""}, + {"(*Regexp).Equal", Method, 0, ""}, + {"(*Regexp).MaxCap", Method, 0, ""}, + {"(*Regexp).Simplify", Method, 0, ""}, + {"(*Regexp).String", Method, 0, ""}, + {"(ErrorCode).String", Method, 0, ""}, + {"(InstOp).String", Method, 3, ""}, + {"(Op).String", Method, 11, ""}, + {"ClassNL", Const, 0, ""}, + {"Compile", Func, 0, "func(re *Regexp) (*Prog, error)"}, + {"DotNL", Const, 0, ""}, + {"EmptyBeginLine", Const, 0, ""}, + {"EmptyBeginText", Const, 0, ""}, + {"EmptyEndLine", Const, 0, ""}, + {"EmptyEndText", Const, 0, ""}, + {"EmptyNoWordBoundary", Const, 0, ""}, + {"EmptyOp", Type, 0, ""}, + {"EmptyOpContext", Func, 0, "func(r1 rune, r2 rune) EmptyOp"}, + {"EmptyWordBoundary", Const, 0, ""}, + {"ErrInternalError", Const, 0, ""}, + {"ErrInvalidCharClass", Const, 0, ""}, + {"ErrInvalidCharRange", Const, 0, ""}, + {"ErrInvalidEscape", Const, 0, ""}, + {"ErrInvalidNamedCapture", Const, 0, ""}, + {"ErrInvalidPerlOp", Const, 0, ""}, + {"ErrInvalidRepeatOp", Const, 0, ""}, + {"ErrInvalidRepeatSize", Const, 0, ""}, + {"ErrInvalidUTF8", Const, 0, ""}, + {"ErrLarge", Const, 20, ""}, + {"ErrMissingBracket", Const, 0, ""}, + {"ErrMissingParen", Const, 0, ""}, + {"ErrMissingRepeatArgument", Const, 0, ""}, + {"ErrNestingDepth", Const, 19, ""}, + {"ErrTrailingBackslash", Const, 0, ""}, + {"ErrUnexpectedParen", Const, 1, ""}, + {"Error", Type, 0, ""}, + {"Error.Code", Field, 0, ""}, + {"Error.Expr", Field, 0, ""}, + {"ErrorCode", Type, 0, ""}, + {"Flags", Type, 0, ""}, + {"FoldCase", Const, 0, ""}, + {"Inst", Type, 0, ""}, + {"Inst.Arg", Field, 0, ""}, + {"Inst.Op", Field, 0, ""}, + {"Inst.Out", Field, 0, ""}, + {"Inst.Rune", Field, 0, ""}, + {"InstAlt", Const, 0, ""}, + {"InstAltMatch", Const, 0, ""}, + {"InstCapture", Const, 0, ""}, + {"InstEmptyWidth", Const, 0, ""}, + {"InstFail", Const, 0, ""}, + {"InstMatch", Const, 0, ""}, + {"InstNop", Const, 0, ""}, + {"InstOp", Type, 0, ""}, + {"InstRune", Const, 0, ""}, + {"InstRune1", Const, 0, ""}, + {"InstRuneAny", Const, 0, ""}, + {"InstRuneAnyNotNL", Const, 0, ""}, + {"IsWordChar", Func, 0, "func(r rune) bool"}, + {"Literal", Const, 0, ""}, + {"MatchNL", Const, 0, ""}, + {"NonGreedy", Const, 0, ""}, + {"OneLine", Const, 0, ""}, + {"Op", Type, 0, ""}, + {"OpAlternate", Const, 0, ""}, + {"OpAnyChar", Const, 0, ""}, + {"OpAnyCharNotNL", Const, 0, ""}, + {"OpBeginLine", Const, 0, ""}, + {"OpBeginText", Const, 0, ""}, + {"OpCapture", Const, 0, ""}, + {"OpCharClass", Const, 0, ""}, + {"OpConcat", Const, 0, ""}, + {"OpEmptyMatch", Const, 0, ""}, + {"OpEndLine", Const, 0, ""}, + {"OpEndText", Const, 0, ""}, + {"OpLiteral", Const, 0, ""}, + {"OpNoMatch", Const, 0, ""}, + {"OpNoWordBoundary", Const, 0, ""}, + {"OpPlus", Const, 0, ""}, + {"OpQuest", Const, 0, ""}, + {"OpRepeat", Const, 0, ""}, + {"OpStar", Const, 0, ""}, + {"OpWordBoundary", Const, 0, ""}, + {"POSIX", Const, 0, ""}, + {"Parse", Func, 0, "func(s string, flags Flags) (*Regexp, error)"}, + {"Perl", Const, 0, ""}, + {"PerlX", Const, 0, ""}, + {"Prog", Type, 0, ""}, + {"Prog.Inst", Field, 0, ""}, + {"Prog.NumCap", Field, 0, ""}, + {"Prog.Start", Field, 0, ""}, + {"Regexp", Type, 0, ""}, + {"Regexp.Cap", Field, 0, ""}, + {"Regexp.Flags", Field, 0, ""}, + {"Regexp.Max", Field, 0, ""}, + {"Regexp.Min", Field, 0, ""}, + {"Regexp.Name", Field, 0, ""}, + {"Regexp.Op", Field, 0, ""}, + {"Regexp.Rune", Field, 0, ""}, + {"Regexp.Rune0", Field, 0, ""}, + {"Regexp.Sub", Field, 0, ""}, + {"Regexp.Sub0", Field, 0, ""}, + {"Simple", Const, 0, ""}, + {"UnicodeGroups", Const, 0, ""}, + {"WasDollar", Const, 0, ""}, }, "runtime": { - {"(*BlockProfileRecord).Stack", Method, 1}, - {"(*Frames).Next", Method, 7}, - {"(*Func).Entry", Method, 0}, - {"(*Func).FileLine", Method, 0}, - {"(*Func).Name", Method, 0}, - {"(*MemProfileRecord).InUseBytes", Method, 0}, - {"(*MemProfileRecord).InUseObjects", Method, 0}, - {"(*MemProfileRecord).Stack", Method, 0}, - {"(*PanicNilError).Error", Method, 21}, - {"(*PanicNilError).RuntimeError", Method, 21}, - {"(*Pinner).Pin", Method, 21}, - {"(*Pinner).Unpin", Method, 21}, - {"(*StackRecord).Stack", Method, 0}, - {"(*TypeAssertionError).Error", Method, 0}, - {"(*TypeAssertionError).RuntimeError", Method, 0}, - {"(Cleanup).Stop", Method, 24}, - {"AddCleanup", Func, 24}, - {"BlockProfile", Func, 1}, - {"BlockProfileRecord", Type, 1}, - {"BlockProfileRecord.Count", Field, 1}, - {"BlockProfileRecord.Cycles", Field, 1}, - {"BlockProfileRecord.StackRecord", Field, 1}, - {"Breakpoint", Func, 0}, - {"CPUProfile", Func, 0}, - {"Caller", Func, 0}, - {"Callers", Func, 0}, - {"CallersFrames", Func, 7}, - {"Cleanup", Type, 24}, - {"Compiler", Const, 0}, - {"Error", Type, 0}, - {"Frame", Type, 7}, - {"Frame.Entry", Field, 7}, - {"Frame.File", Field, 7}, - {"Frame.Func", Field, 7}, - {"Frame.Function", Field, 7}, - {"Frame.Line", Field, 7}, - {"Frame.PC", Field, 7}, - {"Frames", Type, 7}, - {"Func", Type, 0}, - {"FuncForPC", Func, 0}, - {"GC", Func, 0}, - {"GOARCH", Const, 0}, - {"GOMAXPROCS", Func, 0}, - {"GOOS", Const, 0}, - {"GOROOT", Func, 0}, - {"Goexit", Func, 0}, - {"GoroutineProfile", Func, 0}, - {"Gosched", Func, 0}, - {"KeepAlive", Func, 7}, - {"LockOSThread", Func, 0}, - {"MemProfile", Func, 0}, - {"MemProfileRate", Var, 0}, - {"MemProfileRecord", Type, 0}, - {"MemProfileRecord.AllocBytes", Field, 0}, - {"MemProfileRecord.AllocObjects", Field, 0}, - {"MemProfileRecord.FreeBytes", Field, 0}, - {"MemProfileRecord.FreeObjects", Field, 0}, - {"MemProfileRecord.Stack0", Field, 0}, - {"MemStats", Type, 0}, - {"MemStats.Alloc", Field, 0}, - {"MemStats.BuckHashSys", Field, 0}, - {"MemStats.BySize", Field, 0}, - {"MemStats.DebugGC", Field, 0}, - {"MemStats.EnableGC", Field, 0}, - {"MemStats.Frees", Field, 0}, - {"MemStats.GCCPUFraction", Field, 5}, - {"MemStats.GCSys", Field, 2}, - {"MemStats.HeapAlloc", Field, 0}, - {"MemStats.HeapIdle", Field, 0}, - {"MemStats.HeapInuse", Field, 0}, - {"MemStats.HeapObjects", Field, 0}, - {"MemStats.HeapReleased", Field, 0}, - {"MemStats.HeapSys", Field, 0}, - {"MemStats.LastGC", Field, 0}, - {"MemStats.Lookups", Field, 0}, - {"MemStats.MCacheInuse", Field, 0}, - {"MemStats.MCacheSys", Field, 0}, - {"MemStats.MSpanInuse", Field, 0}, - {"MemStats.MSpanSys", Field, 0}, - {"MemStats.Mallocs", Field, 0}, - {"MemStats.NextGC", Field, 0}, - {"MemStats.NumForcedGC", Field, 8}, - {"MemStats.NumGC", Field, 0}, - {"MemStats.OtherSys", Field, 2}, - {"MemStats.PauseEnd", Field, 4}, - {"MemStats.PauseNs", Field, 0}, - {"MemStats.PauseTotalNs", Field, 0}, - {"MemStats.StackInuse", Field, 0}, - {"MemStats.StackSys", Field, 0}, - {"MemStats.Sys", Field, 0}, - {"MemStats.TotalAlloc", Field, 0}, - {"MutexProfile", Func, 8}, - {"NumCPU", Func, 0}, - {"NumCgoCall", Func, 0}, - {"NumGoroutine", Func, 0}, - {"PanicNilError", Type, 21}, - {"Pinner", Type, 21}, - {"ReadMemStats", Func, 0}, - {"ReadTrace", Func, 5}, - {"SetBlockProfileRate", Func, 1}, - {"SetCPUProfileRate", Func, 0}, - {"SetCgoTraceback", Func, 7}, - {"SetFinalizer", Func, 0}, - {"SetMutexProfileFraction", Func, 8}, - {"Stack", Func, 0}, - {"StackRecord", Type, 0}, - {"StackRecord.Stack0", Field, 0}, - {"StartTrace", Func, 5}, - {"StopTrace", Func, 5}, - {"ThreadCreateProfile", Func, 0}, - {"TypeAssertionError", Type, 0}, - {"UnlockOSThread", Func, 0}, - {"Version", Func, 0}, + {"(*BlockProfileRecord).Stack", Method, 1, ""}, + {"(*Frames).Next", Method, 7, ""}, + {"(*Func).Entry", Method, 0, ""}, + {"(*Func).FileLine", Method, 0, ""}, + {"(*Func).Name", Method, 0, ""}, + {"(*MemProfileRecord).InUseBytes", Method, 0, ""}, + {"(*MemProfileRecord).InUseObjects", Method, 0, ""}, + {"(*MemProfileRecord).Stack", Method, 0, ""}, + {"(*PanicNilError).Error", Method, 21, ""}, + {"(*PanicNilError).RuntimeError", Method, 21, ""}, + {"(*Pinner).Pin", Method, 21, ""}, + {"(*Pinner).Unpin", Method, 21, ""}, + {"(*StackRecord).Stack", Method, 0, ""}, + {"(*TypeAssertionError).Error", Method, 0, ""}, + {"(*TypeAssertionError).RuntimeError", Method, 0, ""}, + {"(Cleanup).Stop", Method, 24, ""}, + {"AddCleanup", Func, 24, "func[T, S any](ptr *T, cleanup func(S), arg S) Cleanup"}, + {"BlockProfile", Func, 1, "func(p []BlockProfileRecord) (n int, ok bool)"}, + {"BlockProfileRecord", Type, 1, ""}, + {"BlockProfileRecord.Count", Field, 1, ""}, + {"BlockProfileRecord.Cycles", Field, 1, ""}, + {"BlockProfileRecord.StackRecord", Field, 1, ""}, + {"Breakpoint", Func, 0, "func()"}, + {"CPUProfile", Func, 0, "func() []byte"}, + {"Caller", Func, 0, "func(skip int) (pc uintptr, file string, line int, ok bool)"}, + {"Callers", Func, 0, "func(skip int, pc []uintptr) int"}, + {"CallersFrames", Func, 7, "func(callers []uintptr) *Frames"}, + {"Cleanup", Type, 24, ""}, + {"Compiler", Const, 0, ""}, + {"Error", Type, 0, ""}, + {"Frame", Type, 7, ""}, + {"Frame.Entry", Field, 7, ""}, + {"Frame.File", Field, 7, ""}, + {"Frame.Func", Field, 7, ""}, + {"Frame.Function", Field, 7, ""}, + {"Frame.Line", Field, 7, ""}, + {"Frame.PC", Field, 7, ""}, + {"Frames", Type, 7, ""}, + {"Func", Type, 0, ""}, + {"FuncForPC", Func, 0, "func(pc uintptr) *Func"}, + {"GC", Func, 0, "func()"}, + {"GOARCH", Const, 0, ""}, + {"GOMAXPROCS", Func, 0, "func(n int) int"}, + {"GOOS", Const, 0, ""}, + {"GOROOT", Func, 0, "func() string"}, + {"Goexit", Func, 0, "func()"}, + {"GoroutineProfile", Func, 0, "func(p []StackRecord) (n int, ok bool)"}, + {"Gosched", Func, 0, "func()"}, + {"KeepAlive", Func, 7, "func(x any)"}, + {"LockOSThread", Func, 0, "func()"}, + {"MemProfile", Func, 0, "func(p []MemProfileRecord, inuseZero bool) (n int, ok bool)"}, + {"MemProfileRate", Var, 0, ""}, + {"MemProfileRecord", Type, 0, ""}, + {"MemProfileRecord.AllocBytes", Field, 0, ""}, + {"MemProfileRecord.AllocObjects", Field, 0, ""}, + {"MemProfileRecord.FreeBytes", Field, 0, ""}, + {"MemProfileRecord.FreeObjects", Field, 0, ""}, + {"MemProfileRecord.Stack0", Field, 0, ""}, + {"MemStats", Type, 0, ""}, + {"MemStats.Alloc", Field, 0, ""}, + {"MemStats.BuckHashSys", Field, 0, ""}, + {"MemStats.BySize", Field, 0, ""}, + {"MemStats.DebugGC", Field, 0, ""}, + {"MemStats.EnableGC", Field, 0, ""}, + {"MemStats.Frees", Field, 0, ""}, + {"MemStats.GCCPUFraction", Field, 5, ""}, + {"MemStats.GCSys", Field, 2, ""}, + {"MemStats.HeapAlloc", Field, 0, ""}, + {"MemStats.HeapIdle", Field, 0, ""}, + {"MemStats.HeapInuse", Field, 0, ""}, + {"MemStats.HeapObjects", Field, 0, ""}, + {"MemStats.HeapReleased", Field, 0, ""}, + {"MemStats.HeapSys", Field, 0, ""}, + {"MemStats.LastGC", Field, 0, ""}, + {"MemStats.Lookups", Field, 0, ""}, + {"MemStats.MCacheInuse", Field, 0, ""}, + {"MemStats.MCacheSys", Field, 0, ""}, + {"MemStats.MSpanInuse", Field, 0, ""}, + {"MemStats.MSpanSys", Field, 0, ""}, + {"MemStats.Mallocs", Field, 0, ""}, + {"MemStats.NextGC", Field, 0, ""}, + {"MemStats.NumForcedGC", Field, 8, ""}, + {"MemStats.NumGC", Field, 0, ""}, + {"MemStats.OtherSys", Field, 2, ""}, + {"MemStats.PauseEnd", Field, 4, ""}, + {"MemStats.PauseNs", Field, 0, ""}, + {"MemStats.PauseTotalNs", Field, 0, ""}, + {"MemStats.StackInuse", Field, 0, ""}, + {"MemStats.StackSys", Field, 0, ""}, + {"MemStats.Sys", Field, 0, ""}, + {"MemStats.TotalAlloc", Field, 0, ""}, + {"MutexProfile", Func, 8, "func(p []BlockProfileRecord) (n int, ok bool)"}, + {"NumCPU", Func, 0, "func() int"}, + {"NumCgoCall", Func, 0, "func() int64"}, + {"NumGoroutine", Func, 0, "func() int"}, + {"PanicNilError", Type, 21, ""}, + {"Pinner", Type, 21, ""}, + {"ReadMemStats", Func, 0, "func(m *MemStats)"}, + {"ReadTrace", Func, 5, "func() []byte"}, + {"SetBlockProfileRate", Func, 1, "func(rate int)"}, + {"SetCPUProfileRate", Func, 0, "func(hz int)"}, + {"SetCgoTraceback", Func, 7, "func(version int, traceback unsafe.Pointer, context unsafe.Pointer, symbolizer unsafe.Pointer)"}, + {"SetFinalizer", Func, 0, "func(obj any, finalizer any)"}, + {"SetMutexProfileFraction", Func, 8, "func(rate int) int"}, + {"Stack", Func, 0, "func(buf []byte, all bool) int"}, + {"StackRecord", Type, 0, ""}, + {"StackRecord.Stack0", Field, 0, ""}, + {"StartTrace", Func, 5, "func() error"}, + {"StopTrace", Func, 5, "func()"}, + {"ThreadCreateProfile", Func, 0, "func(p []StackRecord) (n int, ok bool)"}, + {"TypeAssertionError", Type, 0, ""}, + {"UnlockOSThread", Func, 0, "func()"}, + {"Version", Func, 0, "func() string"}, }, "runtime/cgo": { - {"(Handle).Delete", Method, 17}, - {"(Handle).Value", Method, 17}, - {"Handle", Type, 17}, - {"Incomplete", Type, 20}, - {"NewHandle", Func, 17}, + {"(Handle).Delete", Method, 17, ""}, + {"(Handle).Value", Method, 17, ""}, + {"Handle", Type, 17, ""}, + {"Incomplete", Type, 20, ""}, + {"NewHandle", Func, 17, ""}, }, "runtime/coverage": { - {"ClearCounters", Func, 20}, - {"WriteCounters", Func, 20}, - {"WriteCountersDir", Func, 20}, - {"WriteMeta", Func, 20}, - {"WriteMetaDir", Func, 20}, + {"ClearCounters", Func, 20, "func() error"}, + {"WriteCounters", Func, 20, "func(w io.Writer) error"}, + {"WriteCountersDir", Func, 20, "func(dir string) error"}, + {"WriteMeta", Func, 20, "func(w io.Writer) error"}, + {"WriteMetaDir", Func, 20, "func(dir string) error"}, }, "runtime/debug": { - {"(*BuildInfo).String", Method, 18}, - {"BuildInfo", Type, 12}, - {"BuildInfo.Deps", Field, 12}, - {"BuildInfo.GoVersion", Field, 18}, - {"BuildInfo.Main", Field, 12}, - {"BuildInfo.Path", Field, 12}, - {"BuildInfo.Settings", Field, 18}, - {"BuildSetting", Type, 18}, - {"BuildSetting.Key", Field, 18}, - {"BuildSetting.Value", Field, 18}, - {"CrashOptions", Type, 23}, - {"FreeOSMemory", Func, 1}, - {"GCStats", Type, 1}, - {"GCStats.LastGC", Field, 1}, - {"GCStats.NumGC", Field, 1}, - {"GCStats.Pause", Field, 1}, - {"GCStats.PauseEnd", Field, 4}, - {"GCStats.PauseQuantiles", Field, 1}, - {"GCStats.PauseTotal", Field, 1}, - {"Module", Type, 12}, - {"Module.Path", Field, 12}, - {"Module.Replace", Field, 12}, - {"Module.Sum", Field, 12}, - {"Module.Version", Field, 12}, - {"ParseBuildInfo", Func, 18}, - {"PrintStack", Func, 0}, - {"ReadBuildInfo", Func, 12}, - {"ReadGCStats", Func, 1}, - {"SetCrashOutput", Func, 23}, - {"SetGCPercent", Func, 1}, - {"SetMaxStack", Func, 2}, - {"SetMaxThreads", Func, 2}, - {"SetMemoryLimit", Func, 19}, - {"SetPanicOnFault", Func, 3}, - {"SetTraceback", Func, 6}, - {"Stack", Func, 0}, - {"WriteHeapDump", Func, 3}, + {"(*BuildInfo).String", Method, 18, ""}, + {"BuildInfo", Type, 12, ""}, + {"BuildInfo.Deps", Field, 12, ""}, + {"BuildInfo.GoVersion", Field, 18, ""}, + {"BuildInfo.Main", Field, 12, ""}, + {"BuildInfo.Path", Field, 12, ""}, + {"BuildInfo.Settings", Field, 18, ""}, + {"BuildSetting", Type, 18, ""}, + {"BuildSetting.Key", Field, 18, ""}, + {"BuildSetting.Value", Field, 18, ""}, + {"CrashOptions", Type, 23, ""}, + {"FreeOSMemory", Func, 1, "func()"}, + {"GCStats", Type, 1, ""}, + {"GCStats.LastGC", Field, 1, ""}, + {"GCStats.NumGC", Field, 1, ""}, + {"GCStats.Pause", Field, 1, ""}, + {"GCStats.PauseEnd", Field, 4, ""}, + {"GCStats.PauseQuantiles", Field, 1, ""}, + {"GCStats.PauseTotal", Field, 1, ""}, + {"Module", Type, 12, ""}, + {"Module.Path", Field, 12, ""}, + {"Module.Replace", Field, 12, ""}, + {"Module.Sum", Field, 12, ""}, + {"Module.Version", Field, 12, ""}, + {"ParseBuildInfo", Func, 18, "func(data string) (bi *BuildInfo, err error)"}, + {"PrintStack", Func, 0, "func()"}, + {"ReadBuildInfo", Func, 12, "func() (info *BuildInfo, ok bool)"}, + {"ReadGCStats", Func, 1, "func(stats *GCStats)"}, + {"SetCrashOutput", Func, 23, "func(f *os.File, opts CrashOptions) error"}, + {"SetGCPercent", Func, 1, "func(percent int) int"}, + {"SetMaxStack", Func, 2, "func(bytes int) int"}, + {"SetMaxThreads", Func, 2, "func(threads int) int"}, + {"SetMemoryLimit", Func, 19, "func(limit int64) int64"}, + {"SetPanicOnFault", Func, 3, "func(enabled bool) bool"}, + {"SetTraceback", Func, 6, "func(level string)"}, + {"Stack", Func, 0, "func() []byte"}, + {"WriteHeapDump", Func, 3, "func(fd uintptr)"}, }, "runtime/metrics": { - {"(Value).Float64", Method, 16}, - {"(Value).Float64Histogram", Method, 16}, - {"(Value).Kind", Method, 16}, - {"(Value).Uint64", Method, 16}, - {"All", Func, 16}, - {"Description", Type, 16}, - {"Description.Cumulative", Field, 16}, - {"Description.Description", Field, 16}, - {"Description.Kind", Field, 16}, - {"Description.Name", Field, 16}, - {"Float64Histogram", Type, 16}, - {"Float64Histogram.Buckets", Field, 16}, - {"Float64Histogram.Counts", Field, 16}, - {"KindBad", Const, 16}, - {"KindFloat64", Const, 16}, - {"KindFloat64Histogram", Const, 16}, - {"KindUint64", Const, 16}, - {"Read", Func, 16}, - {"Sample", Type, 16}, - {"Sample.Name", Field, 16}, - {"Sample.Value", Field, 16}, - {"Value", Type, 16}, - {"ValueKind", Type, 16}, + {"(Value).Float64", Method, 16, ""}, + {"(Value).Float64Histogram", Method, 16, ""}, + {"(Value).Kind", Method, 16, ""}, + {"(Value).Uint64", Method, 16, ""}, + {"All", Func, 16, "func() []Description"}, + {"Description", Type, 16, ""}, + {"Description.Cumulative", Field, 16, ""}, + {"Description.Description", Field, 16, ""}, + {"Description.Kind", Field, 16, ""}, + {"Description.Name", Field, 16, ""}, + {"Float64Histogram", Type, 16, ""}, + {"Float64Histogram.Buckets", Field, 16, ""}, + {"Float64Histogram.Counts", Field, 16, ""}, + {"KindBad", Const, 16, ""}, + {"KindFloat64", Const, 16, ""}, + {"KindFloat64Histogram", Const, 16, ""}, + {"KindUint64", Const, 16, ""}, + {"Read", Func, 16, "func(m []Sample)"}, + {"Sample", Type, 16, ""}, + {"Sample.Name", Field, 16, ""}, + {"Sample.Value", Field, 16, ""}, + {"Value", Type, 16, ""}, + {"ValueKind", Type, 16, ""}, }, "runtime/pprof": { - {"(*Profile).Add", Method, 0}, - {"(*Profile).Count", Method, 0}, - {"(*Profile).Name", Method, 0}, - {"(*Profile).Remove", Method, 0}, - {"(*Profile).WriteTo", Method, 0}, - {"Do", Func, 9}, - {"ForLabels", Func, 9}, - {"Label", Func, 9}, - {"LabelSet", Type, 9}, - {"Labels", Func, 9}, - {"Lookup", Func, 0}, - {"NewProfile", Func, 0}, - {"Profile", Type, 0}, - {"Profiles", Func, 0}, - {"SetGoroutineLabels", Func, 9}, - {"StartCPUProfile", Func, 0}, - {"StopCPUProfile", Func, 0}, - {"WithLabels", Func, 9}, - {"WriteHeapProfile", Func, 0}, + {"(*Profile).Add", Method, 0, ""}, + {"(*Profile).Count", Method, 0, ""}, + {"(*Profile).Name", Method, 0, ""}, + {"(*Profile).Remove", Method, 0, ""}, + {"(*Profile).WriteTo", Method, 0, ""}, + {"Do", Func, 9, "func(ctx context.Context, labels LabelSet, f func(context.Context))"}, + {"ForLabels", Func, 9, "func(ctx context.Context, f func(key string, value string) bool)"}, + {"Label", Func, 9, "func(ctx context.Context, key string) (string, bool)"}, + {"LabelSet", Type, 9, ""}, + {"Labels", Func, 9, "func(args ...string) LabelSet"}, + {"Lookup", Func, 0, "func(name string) *Profile"}, + {"NewProfile", Func, 0, "func(name string) *Profile"}, + {"Profile", Type, 0, ""}, + {"Profiles", Func, 0, "func() []*Profile"}, + {"SetGoroutineLabels", Func, 9, "func(ctx context.Context)"}, + {"StartCPUProfile", Func, 0, "func(w io.Writer) error"}, + {"StopCPUProfile", Func, 0, "func()"}, + {"WithLabels", Func, 9, "func(ctx context.Context, labels LabelSet) context.Context"}, + {"WriteHeapProfile", Func, 0, "func(w io.Writer) error"}, }, "runtime/trace": { - {"(*Region).End", Method, 11}, - {"(*Task).End", Method, 11}, - {"IsEnabled", Func, 11}, - {"Log", Func, 11}, - {"Logf", Func, 11}, - {"NewTask", Func, 11}, - {"Region", Type, 11}, - {"Start", Func, 5}, - {"StartRegion", Func, 11}, - {"Stop", Func, 5}, - {"Task", Type, 11}, - {"WithRegion", Func, 11}, + {"(*Region).End", Method, 11, ""}, + {"(*Task).End", Method, 11, ""}, + {"IsEnabled", Func, 11, "func() bool"}, + {"Log", Func, 11, "func(ctx context.Context, category string, message string)"}, + {"Logf", Func, 11, "func(ctx context.Context, category string, format string, args ...any)"}, + {"NewTask", Func, 11, "func(pctx context.Context, taskType string) (ctx context.Context, task *Task)"}, + {"Region", Type, 11, ""}, + {"Start", Func, 5, "func(w io.Writer) error"}, + {"StartRegion", Func, 11, "func(ctx context.Context, regionType string) *Region"}, + {"Stop", Func, 5, "func()"}, + {"Task", Type, 11, ""}, + {"WithRegion", Func, 11, "func(ctx context.Context, regionType string, fn func())"}, }, "slices": { - {"All", Func, 23}, - {"AppendSeq", Func, 23}, - {"Backward", Func, 23}, - {"BinarySearch", Func, 21}, - {"BinarySearchFunc", Func, 21}, - {"Chunk", Func, 23}, - {"Clip", Func, 21}, - {"Clone", Func, 21}, - {"Collect", Func, 23}, - {"Compact", Func, 21}, - {"CompactFunc", Func, 21}, - {"Compare", Func, 21}, - {"CompareFunc", Func, 21}, - {"Concat", Func, 22}, - {"Contains", Func, 21}, - {"ContainsFunc", Func, 21}, - {"Delete", Func, 21}, - {"DeleteFunc", Func, 21}, - {"Equal", Func, 21}, - {"EqualFunc", Func, 21}, - {"Grow", Func, 21}, - {"Index", Func, 21}, - {"IndexFunc", Func, 21}, - {"Insert", Func, 21}, - {"IsSorted", Func, 21}, - {"IsSortedFunc", Func, 21}, - {"Max", Func, 21}, - {"MaxFunc", Func, 21}, - {"Min", Func, 21}, - {"MinFunc", Func, 21}, - {"Repeat", Func, 23}, - {"Replace", Func, 21}, - {"Reverse", Func, 21}, - {"Sort", Func, 21}, - {"SortFunc", Func, 21}, - {"SortStableFunc", Func, 21}, - {"Sorted", Func, 23}, - {"SortedFunc", Func, 23}, - {"SortedStableFunc", Func, 23}, - {"Values", Func, 23}, + {"All", Func, 23, "func[Slice ~[]E, E any](s Slice) iter.Seq2[int, E]"}, + {"AppendSeq", Func, 23, "func[Slice ~[]E, E any](s Slice, seq iter.Seq[E]) Slice"}, + {"Backward", Func, 23, "func[Slice ~[]E, E any](s Slice) iter.Seq2[int, E]"}, + {"BinarySearch", Func, 21, "func[S ~[]E, E cmp.Ordered](x S, target E) (int, bool)"}, + {"BinarySearchFunc", Func, 21, "func[S ~[]E, E, T any](x S, target T, cmp func(E, T) int) (int, bool)"}, + {"Chunk", Func, 23, "func[Slice ~[]E, E any](s Slice, n int) iter.Seq[Slice]"}, + {"Clip", Func, 21, "func[S ~[]E, E any](s S) S"}, + {"Clone", Func, 21, "func[S ~[]E, E any](s S) S"}, + {"Collect", Func, 23, "func[E any](seq iter.Seq[E]) []E"}, + {"Compact", Func, 21, "func[S ~[]E, E comparable](s S) S"}, + {"CompactFunc", Func, 21, "func[S ~[]E, E any](s S, eq func(E, E) bool) S"}, + {"Compare", Func, 21, "func[S ~[]E, E cmp.Ordered](s1 S, s2 S) int"}, + {"CompareFunc", Func, 21, "func[S1 ~[]E1, S2 ~[]E2, E1, E2 any](s1 S1, s2 S2, cmp func(E1, E2) int) int"}, + {"Concat", Func, 22, "func[S ~[]E, E any](slices ...S) S"}, + {"Contains", Func, 21, "func[S ~[]E, E comparable](s S, v E) bool"}, + {"ContainsFunc", Func, 21, "func[S ~[]E, E any](s S, f func(E) bool) bool"}, + {"Delete", Func, 21, "func[S ~[]E, E any](s S, i int, j int) S"}, + {"DeleteFunc", Func, 21, "func[S ~[]E, E any](s S, del func(E) bool) S"}, + {"Equal", Func, 21, "func[S ~[]E, E comparable](s1 S, s2 S) bool"}, + {"EqualFunc", Func, 21, "func[S1 ~[]E1, S2 ~[]E2, E1, E2 any](s1 S1, s2 S2, eq func(E1, E2) bool) bool"}, + {"Grow", Func, 21, "func[S ~[]E, E any](s S, n int) S"}, + {"Index", Func, 21, "func[S ~[]E, E comparable](s S, v E) int"}, + {"IndexFunc", Func, 21, "func[S ~[]E, E any](s S, f func(E) bool) int"}, + {"Insert", Func, 21, "func[S ~[]E, E any](s S, i int, v ...E) S"}, + {"IsSorted", Func, 21, "func[S ~[]E, E cmp.Ordered](x S) bool"}, + {"IsSortedFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int) bool"}, + {"Max", Func, 21, "func[S ~[]E, E cmp.Ordered](x S) E"}, + {"MaxFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int) E"}, + {"Min", Func, 21, "func[S ~[]E, E cmp.Ordered](x S) E"}, + {"MinFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int) E"}, + {"Repeat", Func, 23, "func[S ~[]E, E any](x S, count int) S"}, + {"Replace", Func, 21, "func[S ~[]E, E any](s S, i int, j int, v ...E) S"}, + {"Reverse", Func, 21, "func[S ~[]E, E any](s S)"}, + {"Sort", Func, 21, "func[S ~[]E, E cmp.Ordered](x S)"}, + {"SortFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int)"}, + {"SortStableFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int)"}, + {"Sorted", Func, 23, "func[E cmp.Ordered](seq iter.Seq[E]) []E"}, + {"SortedFunc", Func, 23, "func[E any](seq iter.Seq[E], cmp func(E, E) int) []E"}, + {"SortedStableFunc", Func, 23, "func[E any](seq iter.Seq[E], cmp func(E, E) int) []E"}, + {"Values", Func, 23, "func[Slice ~[]E, E any](s Slice) iter.Seq[E]"}, }, "sort": { - {"(Float64Slice).Len", Method, 0}, - {"(Float64Slice).Less", Method, 0}, - {"(Float64Slice).Search", Method, 0}, - {"(Float64Slice).Sort", Method, 0}, - {"(Float64Slice).Swap", Method, 0}, - {"(IntSlice).Len", Method, 0}, - {"(IntSlice).Less", Method, 0}, - {"(IntSlice).Search", Method, 0}, - {"(IntSlice).Sort", Method, 0}, - {"(IntSlice).Swap", Method, 0}, - {"(StringSlice).Len", Method, 0}, - {"(StringSlice).Less", Method, 0}, - {"(StringSlice).Search", Method, 0}, - {"(StringSlice).Sort", Method, 0}, - {"(StringSlice).Swap", Method, 0}, - {"Find", Func, 19}, - {"Float64Slice", Type, 0}, - {"Float64s", Func, 0}, - {"Float64sAreSorted", Func, 0}, - {"IntSlice", Type, 0}, - {"Interface", Type, 0}, - {"Ints", Func, 0}, - {"IntsAreSorted", Func, 0}, - {"IsSorted", Func, 0}, - {"Reverse", Func, 1}, - {"Search", Func, 0}, - {"SearchFloat64s", Func, 0}, - {"SearchInts", Func, 0}, - {"SearchStrings", Func, 0}, - {"Slice", Func, 8}, - {"SliceIsSorted", Func, 8}, - {"SliceStable", Func, 8}, - {"Sort", Func, 0}, - {"Stable", Func, 2}, - {"StringSlice", Type, 0}, - {"Strings", Func, 0}, - {"StringsAreSorted", Func, 0}, + {"(Float64Slice).Len", Method, 0, ""}, + {"(Float64Slice).Less", Method, 0, ""}, + {"(Float64Slice).Search", Method, 0, ""}, + {"(Float64Slice).Sort", Method, 0, ""}, + {"(Float64Slice).Swap", Method, 0, ""}, + {"(IntSlice).Len", Method, 0, ""}, + {"(IntSlice).Less", Method, 0, ""}, + {"(IntSlice).Search", Method, 0, ""}, + {"(IntSlice).Sort", Method, 0, ""}, + {"(IntSlice).Swap", Method, 0, ""}, + {"(StringSlice).Len", Method, 0, ""}, + {"(StringSlice).Less", Method, 0, ""}, + {"(StringSlice).Search", Method, 0, ""}, + {"(StringSlice).Sort", Method, 0, ""}, + {"(StringSlice).Swap", Method, 0, ""}, + {"Find", Func, 19, "func(n int, cmp func(int) int) (i int, found bool)"}, + {"Float64Slice", Type, 0, ""}, + {"Float64s", Func, 0, "func(x []float64)"}, + {"Float64sAreSorted", Func, 0, "func(x []float64) bool"}, + {"IntSlice", Type, 0, ""}, + {"Interface", Type, 0, ""}, + {"Ints", Func, 0, "func(x []int)"}, + {"IntsAreSorted", Func, 0, "func(x []int) bool"}, + {"IsSorted", Func, 0, "func(data Interface) bool"}, + {"Reverse", Func, 1, "func(data Interface) Interface"}, + {"Search", Func, 0, "func(n int, f func(int) bool) int"}, + {"SearchFloat64s", Func, 0, "func(a []float64, x float64) int"}, + {"SearchInts", Func, 0, "func(a []int, x int) int"}, + {"SearchStrings", Func, 0, "func(a []string, x string) int"}, + {"Slice", Func, 8, "func(x any, less func(i int, j int) bool)"}, + {"SliceIsSorted", Func, 8, "func(x any, less func(i int, j int) bool) bool"}, + {"SliceStable", Func, 8, "func(x any, less func(i int, j int) bool)"}, + {"Sort", Func, 0, "func(data Interface)"}, + {"Stable", Func, 2, "func(data Interface)"}, + {"StringSlice", Type, 0, ""}, + {"Strings", Func, 0, "func(x []string)"}, + {"StringsAreSorted", Func, 0, "func(x []string) bool"}, }, "strconv": { - {"(*NumError).Error", Method, 0}, - {"(*NumError).Unwrap", Method, 14}, - {"AppendBool", Func, 0}, - {"AppendFloat", Func, 0}, - {"AppendInt", Func, 0}, - {"AppendQuote", Func, 0}, - {"AppendQuoteRune", Func, 0}, - {"AppendQuoteRuneToASCII", Func, 0}, - {"AppendQuoteRuneToGraphic", Func, 6}, - {"AppendQuoteToASCII", Func, 0}, - {"AppendQuoteToGraphic", Func, 6}, - {"AppendUint", Func, 0}, - {"Atoi", Func, 0}, - {"CanBackquote", Func, 0}, - {"ErrRange", Var, 0}, - {"ErrSyntax", Var, 0}, - {"FormatBool", Func, 0}, - {"FormatComplex", Func, 15}, - {"FormatFloat", Func, 0}, - {"FormatInt", Func, 0}, - {"FormatUint", Func, 0}, - {"IntSize", Const, 0}, - {"IsGraphic", Func, 6}, - {"IsPrint", Func, 0}, - {"Itoa", Func, 0}, - {"NumError", Type, 0}, - {"NumError.Err", Field, 0}, - {"NumError.Func", Field, 0}, - {"NumError.Num", Field, 0}, - {"ParseBool", Func, 0}, - {"ParseComplex", Func, 15}, - {"ParseFloat", Func, 0}, - {"ParseInt", Func, 0}, - {"ParseUint", Func, 0}, - {"Quote", Func, 0}, - {"QuoteRune", Func, 0}, - {"QuoteRuneToASCII", Func, 0}, - {"QuoteRuneToGraphic", Func, 6}, - {"QuoteToASCII", Func, 0}, - {"QuoteToGraphic", Func, 6}, - {"QuotedPrefix", Func, 17}, - {"Unquote", Func, 0}, - {"UnquoteChar", Func, 0}, + {"(*NumError).Error", Method, 0, ""}, + {"(*NumError).Unwrap", Method, 14, ""}, + {"AppendBool", Func, 0, "func(dst []byte, b bool) []byte"}, + {"AppendFloat", Func, 0, "func(dst []byte, f float64, fmt byte, prec int, bitSize int) []byte"}, + {"AppendInt", Func, 0, "func(dst []byte, i int64, base int) []byte"}, + {"AppendQuote", Func, 0, "func(dst []byte, s string) []byte"}, + {"AppendQuoteRune", Func, 0, "func(dst []byte, r rune) []byte"}, + {"AppendQuoteRuneToASCII", Func, 0, "func(dst []byte, r rune) []byte"}, + {"AppendQuoteRuneToGraphic", Func, 6, "func(dst []byte, r rune) []byte"}, + {"AppendQuoteToASCII", Func, 0, "func(dst []byte, s string) []byte"}, + {"AppendQuoteToGraphic", Func, 6, "func(dst []byte, s string) []byte"}, + {"AppendUint", Func, 0, "func(dst []byte, i uint64, base int) []byte"}, + {"Atoi", Func, 0, "func(s string) (int, error)"}, + {"CanBackquote", Func, 0, "func(s string) bool"}, + {"ErrRange", Var, 0, ""}, + {"ErrSyntax", Var, 0, ""}, + {"FormatBool", Func, 0, "func(b bool) string"}, + {"FormatComplex", Func, 15, "func(c complex128, fmt byte, prec int, bitSize int) string"}, + {"FormatFloat", Func, 0, "func(f float64, fmt byte, prec int, bitSize int) string"}, + {"FormatInt", Func, 0, "func(i int64, base int) string"}, + {"FormatUint", Func, 0, "func(i uint64, base int) string"}, + {"IntSize", Const, 0, ""}, + {"IsGraphic", Func, 6, "func(r rune) bool"}, + {"IsPrint", Func, 0, "func(r rune) bool"}, + {"Itoa", Func, 0, "func(i int) string"}, + {"NumError", Type, 0, ""}, + {"NumError.Err", Field, 0, ""}, + {"NumError.Func", Field, 0, ""}, + {"NumError.Num", Field, 0, ""}, + {"ParseBool", Func, 0, "func(str string) (bool, error)"}, + {"ParseComplex", Func, 15, "func(s string, bitSize int) (complex128, error)"}, + {"ParseFloat", Func, 0, "func(s string, bitSize int) (float64, error)"}, + {"ParseInt", Func, 0, "func(s string, base int, bitSize int) (i int64, err error)"}, + {"ParseUint", Func, 0, "func(s string, base int, bitSize int) (uint64, error)"}, + {"Quote", Func, 0, "func(s string) string"}, + {"QuoteRune", Func, 0, "func(r rune) string"}, + {"QuoteRuneToASCII", Func, 0, "func(r rune) string"}, + {"QuoteRuneToGraphic", Func, 6, "func(r rune) string"}, + {"QuoteToASCII", Func, 0, "func(s string) string"}, + {"QuoteToGraphic", Func, 6, "func(s string) string"}, + {"QuotedPrefix", Func, 17, "func(s string) (string, error)"}, + {"Unquote", Func, 0, "func(s string) (string, error)"}, + {"UnquoteChar", Func, 0, "func(s string, quote byte) (value rune, multibyte bool, tail string, err error)"}, }, "strings": { - {"(*Builder).Cap", Method, 12}, - {"(*Builder).Grow", Method, 10}, - {"(*Builder).Len", Method, 10}, - {"(*Builder).Reset", Method, 10}, - {"(*Builder).String", Method, 10}, - {"(*Builder).Write", Method, 10}, - {"(*Builder).WriteByte", Method, 10}, - {"(*Builder).WriteRune", Method, 10}, - {"(*Builder).WriteString", Method, 10}, - {"(*Reader).Len", Method, 0}, - {"(*Reader).Read", Method, 0}, - {"(*Reader).ReadAt", Method, 0}, - {"(*Reader).ReadByte", Method, 0}, - {"(*Reader).ReadRune", Method, 0}, - {"(*Reader).Reset", Method, 7}, - {"(*Reader).Seek", Method, 0}, - {"(*Reader).Size", Method, 5}, - {"(*Reader).UnreadByte", Method, 0}, - {"(*Reader).UnreadRune", Method, 0}, - {"(*Reader).WriteTo", Method, 1}, - {"(*Replacer).Replace", Method, 0}, - {"(*Replacer).WriteString", Method, 0}, - {"Builder", Type, 10}, - {"Clone", Func, 18}, - {"Compare", Func, 5}, - {"Contains", Func, 0}, - {"ContainsAny", Func, 0}, - {"ContainsFunc", Func, 21}, - {"ContainsRune", Func, 0}, - {"Count", Func, 0}, - {"Cut", Func, 18}, - {"CutPrefix", Func, 20}, - {"CutSuffix", Func, 20}, - {"EqualFold", Func, 0}, - {"Fields", Func, 0}, - {"FieldsFunc", Func, 0}, - {"FieldsFuncSeq", Func, 24}, - {"FieldsSeq", Func, 24}, - {"HasPrefix", Func, 0}, - {"HasSuffix", Func, 0}, - {"Index", Func, 0}, - {"IndexAny", Func, 0}, - {"IndexByte", Func, 2}, - {"IndexFunc", Func, 0}, - {"IndexRune", Func, 0}, - {"Join", Func, 0}, - {"LastIndex", Func, 0}, - {"LastIndexAny", Func, 0}, - {"LastIndexByte", Func, 5}, - {"LastIndexFunc", Func, 0}, - {"Lines", Func, 24}, - {"Map", Func, 0}, - {"NewReader", Func, 0}, - {"NewReplacer", Func, 0}, - {"Reader", Type, 0}, - {"Repeat", Func, 0}, - {"Replace", Func, 0}, - {"ReplaceAll", Func, 12}, - {"Replacer", Type, 0}, - {"Split", Func, 0}, - {"SplitAfter", Func, 0}, - {"SplitAfterN", Func, 0}, - {"SplitAfterSeq", Func, 24}, - {"SplitN", Func, 0}, - {"SplitSeq", Func, 24}, - {"Title", Func, 0}, - {"ToLower", Func, 0}, - {"ToLowerSpecial", Func, 0}, - {"ToTitle", Func, 0}, - {"ToTitleSpecial", Func, 0}, - {"ToUpper", Func, 0}, - {"ToUpperSpecial", Func, 0}, - {"ToValidUTF8", Func, 13}, - {"Trim", Func, 0}, - {"TrimFunc", Func, 0}, - {"TrimLeft", Func, 0}, - {"TrimLeftFunc", Func, 0}, - {"TrimPrefix", Func, 1}, - {"TrimRight", Func, 0}, - {"TrimRightFunc", Func, 0}, - {"TrimSpace", Func, 0}, - {"TrimSuffix", Func, 1}, + {"(*Builder).Cap", Method, 12, ""}, + {"(*Builder).Grow", Method, 10, ""}, + {"(*Builder).Len", Method, 10, ""}, + {"(*Builder).Reset", Method, 10, ""}, + {"(*Builder).String", Method, 10, ""}, + {"(*Builder).Write", Method, 10, ""}, + {"(*Builder).WriteByte", Method, 10, ""}, + {"(*Builder).WriteRune", Method, 10, ""}, + {"(*Builder).WriteString", Method, 10, ""}, + {"(*Reader).Len", Method, 0, ""}, + {"(*Reader).Read", Method, 0, ""}, + {"(*Reader).ReadAt", Method, 0, ""}, + {"(*Reader).ReadByte", Method, 0, ""}, + {"(*Reader).ReadRune", Method, 0, ""}, + {"(*Reader).Reset", Method, 7, ""}, + {"(*Reader).Seek", Method, 0, ""}, + {"(*Reader).Size", Method, 5, ""}, + {"(*Reader).UnreadByte", Method, 0, ""}, + {"(*Reader).UnreadRune", Method, 0, ""}, + {"(*Reader).WriteTo", Method, 1, ""}, + {"(*Replacer).Replace", Method, 0, ""}, + {"(*Replacer).WriteString", Method, 0, ""}, + {"Builder", Type, 10, ""}, + {"Clone", Func, 18, "func(s string) string"}, + {"Compare", Func, 5, "func(a string, b string) int"}, + {"Contains", Func, 0, "func(s string, substr string) bool"}, + {"ContainsAny", Func, 0, "func(s string, chars string) bool"}, + {"ContainsFunc", Func, 21, "func(s string, f func(rune) bool) bool"}, + {"ContainsRune", Func, 0, "func(s string, r rune) bool"}, + {"Count", Func, 0, "func(s string, substr string) int"}, + {"Cut", Func, 18, "func(s string, sep string) (before string, after string, found bool)"}, + {"CutPrefix", Func, 20, "func(s string, prefix string) (after string, found bool)"}, + {"CutSuffix", Func, 20, "func(s string, suffix string) (before string, found bool)"}, + {"EqualFold", Func, 0, "func(s string, t string) bool"}, + {"Fields", Func, 0, "func(s string) []string"}, + {"FieldsFunc", Func, 0, "func(s string, f func(rune) bool) []string"}, + {"FieldsFuncSeq", Func, 24, "func(s string, f func(rune) bool) iter.Seq[string]"}, + {"FieldsSeq", Func, 24, "func(s string) iter.Seq[string]"}, + {"HasPrefix", Func, 0, "func(s string, prefix string) bool"}, + {"HasSuffix", Func, 0, "func(s string, suffix string) bool"}, + {"Index", Func, 0, "func(s string, substr string) int"}, + {"IndexAny", Func, 0, "func(s string, chars string) int"}, + {"IndexByte", Func, 2, "func(s string, c byte) int"}, + {"IndexFunc", Func, 0, "func(s string, f func(rune) bool) int"}, + {"IndexRune", Func, 0, "func(s string, r rune) int"}, + {"Join", Func, 0, "func(elems []string, sep string) string"}, + {"LastIndex", Func, 0, "func(s string, substr string) int"}, + {"LastIndexAny", Func, 0, "func(s string, chars string) int"}, + {"LastIndexByte", Func, 5, "func(s string, c byte) int"}, + {"LastIndexFunc", Func, 0, "func(s string, f func(rune) bool) int"}, + {"Lines", Func, 24, "func(s string) iter.Seq[string]"}, + {"Map", Func, 0, "func(mapping func(rune) rune, s string) string"}, + {"NewReader", Func, 0, "func(s string) *Reader"}, + {"NewReplacer", Func, 0, "func(oldnew ...string) *Replacer"}, + {"Reader", Type, 0, ""}, + {"Repeat", Func, 0, "func(s string, count int) string"}, + {"Replace", Func, 0, "func(s string, old string, new string, n int) string"}, + {"ReplaceAll", Func, 12, "func(s string, old string, new string) string"}, + {"Replacer", Type, 0, ""}, + {"Split", Func, 0, "func(s string, sep string) []string"}, + {"SplitAfter", Func, 0, "func(s string, sep string) []string"}, + {"SplitAfterN", Func, 0, "func(s string, sep string, n int) []string"}, + {"SplitAfterSeq", Func, 24, "func(s string, sep string) iter.Seq[string]"}, + {"SplitN", Func, 0, "func(s string, sep string, n int) []string"}, + {"SplitSeq", Func, 24, "func(s string, sep string) iter.Seq[string]"}, + {"Title", Func, 0, "func(s string) string"}, + {"ToLower", Func, 0, "func(s string) string"}, + {"ToLowerSpecial", Func, 0, "func(c unicode.SpecialCase, s string) string"}, + {"ToTitle", Func, 0, "func(s string) string"}, + {"ToTitleSpecial", Func, 0, "func(c unicode.SpecialCase, s string) string"}, + {"ToUpper", Func, 0, "func(s string) string"}, + {"ToUpperSpecial", Func, 0, "func(c unicode.SpecialCase, s string) string"}, + {"ToValidUTF8", Func, 13, "func(s string, replacement string) string"}, + {"Trim", Func, 0, "func(s string, cutset string) string"}, + {"TrimFunc", Func, 0, "func(s string, f func(rune) bool) string"}, + {"TrimLeft", Func, 0, "func(s string, cutset string) string"}, + {"TrimLeftFunc", Func, 0, "func(s string, f func(rune) bool) string"}, + {"TrimPrefix", Func, 1, "func(s string, prefix string) string"}, + {"TrimRight", Func, 0, "func(s string, cutset string) string"}, + {"TrimRightFunc", Func, 0, "func(s string, f func(rune) bool) string"}, + {"TrimSpace", Func, 0, "func(s string) string"}, + {"TrimSuffix", Func, 1, "func(s string, suffix string) string"}, }, "structs": { - {"HostLayout", Type, 23}, + {"HostLayout", Type, 23, ""}, }, "sync": { - {"(*Cond).Broadcast", Method, 0}, - {"(*Cond).Signal", Method, 0}, - {"(*Cond).Wait", Method, 0}, - {"(*Map).Clear", Method, 23}, - {"(*Map).CompareAndDelete", Method, 20}, - {"(*Map).CompareAndSwap", Method, 20}, - {"(*Map).Delete", Method, 9}, - {"(*Map).Load", Method, 9}, - {"(*Map).LoadAndDelete", Method, 15}, - {"(*Map).LoadOrStore", Method, 9}, - {"(*Map).Range", Method, 9}, - {"(*Map).Store", Method, 9}, - {"(*Map).Swap", Method, 20}, - {"(*Mutex).Lock", Method, 0}, - {"(*Mutex).TryLock", Method, 18}, - {"(*Mutex).Unlock", Method, 0}, - {"(*Once).Do", Method, 0}, - {"(*Pool).Get", Method, 3}, - {"(*Pool).Put", Method, 3}, - {"(*RWMutex).Lock", Method, 0}, - {"(*RWMutex).RLock", Method, 0}, - {"(*RWMutex).RLocker", Method, 0}, - {"(*RWMutex).RUnlock", Method, 0}, - {"(*RWMutex).TryLock", Method, 18}, - {"(*RWMutex).TryRLock", Method, 18}, - {"(*RWMutex).Unlock", Method, 0}, - {"(*WaitGroup).Add", Method, 0}, - {"(*WaitGroup).Done", Method, 0}, - {"(*WaitGroup).Go", Method, 25}, - {"(*WaitGroup).Wait", Method, 0}, - {"Cond", Type, 0}, - {"Cond.L", Field, 0}, - {"Locker", Type, 0}, - {"Map", Type, 9}, - {"Mutex", Type, 0}, - {"NewCond", Func, 0}, - {"Once", Type, 0}, - {"OnceFunc", Func, 21}, - {"OnceValue", Func, 21}, - {"OnceValues", Func, 21}, - {"Pool", Type, 3}, - {"Pool.New", Field, 3}, - {"RWMutex", Type, 0}, - {"WaitGroup", Type, 0}, + {"(*Cond).Broadcast", Method, 0, ""}, + {"(*Cond).Signal", Method, 0, ""}, + {"(*Cond).Wait", Method, 0, ""}, + {"(*Map).Clear", Method, 23, ""}, + {"(*Map).CompareAndDelete", Method, 20, ""}, + {"(*Map).CompareAndSwap", Method, 20, ""}, + {"(*Map).Delete", Method, 9, ""}, + {"(*Map).Load", Method, 9, ""}, + {"(*Map).LoadAndDelete", Method, 15, ""}, + {"(*Map).LoadOrStore", Method, 9, ""}, + {"(*Map).Range", Method, 9, ""}, + {"(*Map).Store", Method, 9, ""}, + {"(*Map).Swap", Method, 20, ""}, + {"(*Mutex).Lock", Method, 0, ""}, + {"(*Mutex).TryLock", Method, 18, ""}, + {"(*Mutex).Unlock", Method, 0, ""}, + {"(*Once).Do", Method, 0, ""}, + {"(*Pool).Get", Method, 3, ""}, + {"(*Pool).Put", Method, 3, ""}, + {"(*RWMutex).Lock", Method, 0, ""}, + {"(*RWMutex).RLock", Method, 0, ""}, + {"(*RWMutex).RLocker", Method, 0, ""}, + {"(*RWMutex).RUnlock", Method, 0, ""}, + {"(*RWMutex).TryLock", Method, 18, ""}, + {"(*RWMutex).TryRLock", Method, 18, ""}, + {"(*RWMutex).Unlock", Method, 0, ""}, + {"(*WaitGroup).Add", Method, 0, ""}, + {"(*WaitGroup).Done", Method, 0, ""}, + {"(*WaitGroup).Go", Method, 25, ""}, + {"(*WaitGroup).Wait", Method, 0, ""}, + {"Cond", Type, 0, ""}, + {"Cond.L", Field, 0, ""}, + {"Locker", Type, 0, ""}, + {"Map", Type, 9, ""}, + {"Mutex", Type, 0, ""}, + {"NewCond", Func, 0, "func(l Locker) *Cond"}, + {"Once", Type, 0, ""}, + {"OnceFunc", Func, 21, "func(f func()) func()"}, + {"OnceValue", Func, 21, "func[T any](f func() T) func() T"}, + {"OnceValues", Func, 21, "func[T1, T2 any](f func() (T1, T2)) func() (T1, T2)"}, + {"Pool", Type, 3, ""}, + {"Pool.New", Field, 3, ""}, + {"RWMutex", Type, 0, ""}, + {"WaitGroup", Type, 0, ""}, }, "sync/atomic": { - {"(*Bool).CompareAndSwap", Method, 19}, - {"(*Bool).Load", Method, 19}, - {"(*Bool).Store", Method, 19}, - {"(*Bool).Swap", Method, 19}, - {"(*Int32).Add", Method, 19}, - {"(*Int32).And", Method, 23}, - {"(*Int32).CompareAndSwap", Method, 19}, - {"(*Int32).Load", Method, 19}, - {"(*Int32).Or", Method, 23}, - {"(*Int32).Store", Method, 19}, - {"(*Int32).Swap", Method, 19}, - {"(*Int64).Add", Method, 19}, - {"(*Int64).And", Method, 23}, - {"(*Int64).CompareAndSwap", Method, 19}, - {"(*Int64).Load", Method, 19}, - {"(*Int64).Or", Method, 23}, - {"(*Int64).Store", Method, 19}, - {"(*Int64).Swap", Method, 19}, - {"(*Pointer).CompareAndSwap", Method, 19}, - {"(*Pointer).Load", Method, 19}, - {"(*Pointer).Store", Method, 19}, - {"(*Pointer).Swap", Method, 19}, - {"(*Uint32).Add", Method, 19}, - {"(*Uint32).And", Method, 23}, - {"(*Uint32).CompareAndSwap", Method, 19}, - {"(*Uint32).Load", Method, 19}, - {"(*Uint32).Or", Method, 23}, - {"(*Uint32).Store", Method, 19}, - {"(*Uint32).Swap", Method, 19}, - {"(*Uint64).Add", Method, 19}, - {"(*Uint64).And", Method, 23}, - {"(*Uint64).CompareAndSwap", Method, 19}, - {"(*Uint64).Load", Method, 19}, - {"(*Uint64).Or", Method, 23}, - {"(*Uint64).Store", Method, 19}, - {"(*Uint64).Swap", Method, 19}, - {"(*Uintptr).Add", Method, 19}, - {"(*Uintptr).And", Method, 23}, - {"(*Uintptr).CompareAndSwap", Method, 19}, - {"(*Uintptr).Load", Method, 19}, - {"(*Uintptr).Or", Method, 23}, - {"(*Uintptr).Store", Method, 19}, - {"(*Uintptr).Swap", Method, 19}, - {"(*Value).CompareAndSwap", Method, 17}, - {"(*Value).Load", Method, 4}, - {"(*Value).Store", Method, 4}, - {"(*Value).Swap", Method, 17}, - {"AddInt32", Func, 0}, - {"AddInt64", Func, 0}, - {"AddUint32", Func, 0}, - {"AddUint64", Func, 0}, - {"AddUintptr", Func, 0}, - {"AndInt32", Func, 23}, - {"AndInt64", Func, 23}, - {"AndUint32", Func, 23}, - {"AndUint64", Func, 23}, - {"AndUintptr", Func, 23}, - {"Bool", Type, 19}, - {"CompareAndSwapInt32", Func, 0}, - {"CompareAndSwapInt64", Func, 0}, - {"CompareAndSwapPointer", Func, 0}, - {"CompareAndSwapUint32", Func, 0}, - {"CompareAndSwapUint64", Func, 0}, - {"CompareAndSwapUintptr", Func, 0}, - {"Int32", Type, 19}, - {"Int64", Type, 19}, - {"LoadInt32", Func, 0}, - {"LoadInt64", Func, 0}, - {"LoadPointer", Func, 0}, - {"LoadUint32", Func, 0}, - {"LoadUint64", Func, 0}, - {"LoadUintptr", Func, 0}, - {"OrInt32", Func, 23}, - {"OrInt64", Func, 23}, - {"OrUint32", Func, 23}, - {"OrUint64", Func, 23}, - {"OrUintptr", Func, 23}, - {"Pointer", Type, 19}, - {"StoreInt32", Func, 0}, - {"StoreInt64", Func, 0}, - {"StorePointer", Func, 0}, - {"StoreUint32", Func, 0}, - {"StoreUint64", Func, 0}, - {"StoreUintptr", Func, 0}, - {"SwapInt32", Func, 2}, - {"SwapInt64", Func, 2}, - {"SwapPointer", Func, 2}, - {"SwapUint32", Func, 2}, - {"SwapUint64", Func, 2}, - {"SwapUintptr", Func, 2}, - {"Uint32", Type, 19}, - {"Uint64", Type, 19}, - {"Uintptr", Type, 19}, - {"Value", Type, 4}, + {"(*Bool).CompareAndSwap", Method, 19, ""}, + {"(*Bool).Load", Method, 19, ""}, + {"(*Bool).Store", Method, 19, ""}, + {"(*Bool).Swap", Method, 19, ""}, + {"(*Int32).Add", Method, 19, ""}, + {"(*Int32).And", Method, 23, ""}, + {"(*Int32).CompareAndSwap", Method, 19, ""}, + {"(*Int32).Load", Method, 19, ""}, + {"(*Int32).Or", Method, 23, ""}, + {"(*Int32).Store", Method, 19, ""}, + {"(*Int32).Swap", Method, 19, ""}, + {"(*Int64).Add", Method, 19, ""}, + {"(*Int64).And", Method, 23, ""}, + {"(*Int64).CompareAndSwap", Method, 19, ""}, + {"(*Int64).Load", Method, 19, ""}, + {"(*Int64).Or", Method, 23, ""}, + {"(*Int64).Store", Method, 19, ""}, + {"(*Int64).Swap", Method, 19, ""}, + {"(*Pointer).CompareAndSwap", Method, 19, ""}, + {"(*Pointer).Load", Method, 19, ""}, + {"(*Pointer).Store", Method, 19, ""}, + {"(*Pointer).Swap", Method, 19, ""}, + {"(*Uint32).Add", Method, 19, ""}, + {"(*Uint32).And", Method, 23, ""}, + {"(*Uint32).CompareAndSwap", Method, 19, ""}, + {"(*Uint32).Load", Method, 19, ""}, + {"(*Uint32).Or", Method, 23, ""}, + {"(*Uint32).Store", Method, 19, ""}, + {"(*Uint32).Swap", Method, 19, ""}, + {"(*Uint64).Add", Method, 19, ""}, + {"(*Uint64).And", Method, 23, ""}, + {"(*Uint64).CompareAndSwap", Method, 19, ""}, + {"(*Uint64).Load", Method, 19, ""}, + {"(*Uint64).Or", Method, 23, ""}, + {"(*Uint64).Store", Method, 19, ""}, + {"(*Uint64).Swap", Method, 19, ""}, + {"(*Uintptr).Add", Method, 19, ""}, + {"(*Uintptr).And", Method, 23, ""}, + {"(*Uintptr).CompareAndSwap", Method, 19, ""}, + {"(*Uintptr).Load", Method, 19, ""}, + {"(*Uintptr).Or", Method, 23, ""}, + {"(*Uintptr).Store", Method, 19, ""}, + {"(*Uintptr).Swap", Method, 19, ""}, + {"(*Value).CompareAndSwap", Method, 17, ""}, + {"(*Value).Load", Method, 4, ""}, + {"(*Value).Store", Method, 4, ""}, + {"(*Value).Swap", Method, 17, ""}, + {"AddInt32", Func, 0, "func(addr *int32, delta int32) (new int32)"}, + {"AddInt64", Func, 0, "func(addr *int64, delta int64) (new int64)"}, + {"AddUint32", Func, 0, "func(addr *uint32, delta uint32) (new uint32)"}, + {"AddUint64", Func, 0, "func(addr *uint64, delta uint64) (new uint64)"}, + {"AddUintptr", Func, 0, "func(addr *uintptr, delta uintptr) (new uintptr)"}, + {"AndInt32", Func, 23, "func(addr *int32, mask int32) (old int32)"}, + {"AndInt64", Func, 23, "func(addr *int64, mask int64) (old int64)"}, + {"AndUint32", Func, 23, "func(addr *uint32, mask uint32) (old uint32)"}, + {"AndUint64", Func, 23, "func(addr *uint64, mask uint64) (old uint64)"}, + {"AndUintptr", Func, 23, "func(addr *uintptr, mask uintptr) (old uintptr)"}, + {"Bool", Type, 19, ""}, + {"CompareAndSwapInt32", Func, 0, "func(addr *int32, old int32, new int32) (swapped bool)"}, + {"CompareAndSwapInt64", Func, 0, "func(addr *int64, old int64, new int64) (swapped bool)"}, + {"CompareAndSwapPointer", Func, 0, "func(addr *unsafe.Pointer, old unsafe.Pointer, new unsafe.Pointer) (swapped bool)"}, + {"CompareAndSwapUint32", Func, 0, "func(addr *uint32, old uint32, new uint32) (swapped bool)"}, + {"CompareAndSwapUint64", Func, 0, "func(addr *uint64, old uint64, new uint64) (swapped bool)"}, + {"CompareAndSwapUintptr", Func, 0, "func(addr *uintptr, old uintptr, new uintptr) (swapped bool)"}, + {"Int32", Type, 19, ""}, + {"Int64", Type, 19, ""}, + {"LoadInt32", Func, 0, "func(addr *int32) (val int32)"}, + {"LoadInt64", Func, 0, "func(addr *int64) (val int64)"}, + {"LoadPointer", Func, 0, "func(addr *unsafe.Pointer) (val unsafe.Pointer)"}, + {"LoadUint32", Func, 0, "func(addr *uint32) (val uint32)"}, + {"LoadUint64", Func, 0, "func(addr *uint64) (val uint64)"}, + {"LoadUintptr", Func, 0, "func(addr *uintptr) (val uintptr)"}, + {"OrInt32", Func, 23, "func(addr *int32, mask int32) (old int32)"}, + {"OrInt64", Func, 23, "func(addr *int64, mask int64) (old int64)"}, + {"OrUint32", Func, 23, "func(addr *uint32, mask uint32) (old uint32)"}, + {"OrUint64", Func, 23, "func(addr *uint64, mask uint64) (old uint64)"}, + {"OrUintptr", Func, 23, "func(addr *uintptr, mask uintptr) (old uintptr)"}, + {"Pointer", Type, 19, ""}, + {"StoreInt32", Func, 0, "func(addr *int32, val int32)"}, + {"StoreInt64", Func, 0, "func(addr *int64, val int64)"}, + {"StorePointer", Func, 0, "func(addr *unsafe.Pointer, val unsafe.Pointer)"}, + {"StoreUint32", Func, 0, "func(addr *uint32, val uint32)"}, + {"StoreUint64", Func, 0, "func(addr *uint64, val uint64)"}, + {"StoreUintptr", Func, 0, "func(addr *uintptr, val uintptr)"}, + {"SwapInt32", Func, 2, "func(addr *int32, new int32) (old int32)"}, + {"SwapInt64", Func, 2, "func(addr *int64, new int64) (old int64)"}, + {"SwapPointer", Func, 2, "func(addr *unsafe.Pointer, new unsafe.Pointer) (old unsafe.Pointer)"}, + {"SwapUint32", Func, 2, "func(addr *uint32, new uint32) (old uint32)"}, + {"SwapUint64", Func, 2, "func(addr *uint64, new uint64) (old uint64)"}, + {"SwapUintptr", Func, 2, "func(addr *uintptr, new uintptr) (old uintptr)"}, + {"Uint32", Type, 19, ""}, + {"Uint64", Type, 19, ""}, + {"Uintptr", Type, 19, ""}, + {"Value", Type, 4, ""}, }, "syscall": { - {"(*Cmsghdr).SetLen", Method, 0}, - {"(*DLL).FindProc", Method, 0}, - {"(*DLL).MustFindProc", Method, 0}, - {"(*DLL).Release", Method, 0}, - {"(*DLLError).Error", Method, 0}, - {"(*DLLError).Unwrap", Method, 16}, - {"(*Filetime).Nanoseconds", Method, 0}, - {"(*Iovec).SetLen", Method, 0}, - {"(*LazyDLL).Handle", Method, 0}, - {"(*LazyDLL).Load", Method, 0}, - {"(*LazyDLL).NewProc", Method, 0}, - {"(*LazyProc).Addr", Method, 0}, - {"(*LazyProc).Call", Method, 0}, - {"(*LazyProc).Find", Method, 0}, - {"(*Msghdr).SetControllen", Method, 0}, - {"(*Proc).Addr", Method, 0}, - {"(*Proc).Call", Method, 0}, - {"(*PtraceRegs).PC", Method, 0}, - {"(*PtraceRegs).SetPC", Method, 0}, - {"(*RawSockaddrAny).Sockaddr", Method, 0}, - {"(*SID).Copy", Method, 0}, - {"(*SID).Len", Method, 0}, - {"(*SID).LookupAccount", Method, 0}, - {"(*SID).String", Method, 0}, - {"(*Timespec).Nano", Method, 0}, - {"(*Timespec).Unix", Method, 0}, - {"(*Timeval).Nano", Method, 0}, - {"(*Timeval).Nanoseconds", Method, 0}, - {"(*Timeval).Unix", Method, 0}, - {"(Errno).Error", Method, 0}, - {"(Errno).Is", Method, 13}, - {"(Errno).Temporary", Method, 0}, - {"(Errno).Timeout", Method, 0}, - {"(Signal).Signal", Method, 0}, - {"(Signal).String", Method, 0}, - {"(Token).Close", Method, 0}, - {"(Token).GetTokenPrimaryGroup", Method, 0}, - {"(Token).GetTokenUser", Method, 0}, - {"(Token).GetUserProfileDirectory", Method, 0}, - {"(WaitStatus).Continued", Method, 0}, - {"(WaitStatus).CoreDump", Method, 0}, - {"(WaitStatus).ExitStatus", Method, 0}, - {"(WaitStatus).Exited", Method, 0}, - {"(WaitStatus).Signal", Method, 0}, - {"(WaitStatus).Signaled", Method, 0}, - {"(WaitStatus).StopSignal", Method, 0}, - {"(WaitStatus).Stopped", Method, 0}, - {"(WaitStatus).TrapCause", Method, 0}, - {"AF_ALG", Const, 0}, - {"AF_APPLETALK", Const, 0}, - {"AF_ARP", Const, 0}, - {"AF_ASH", Const, 0}, - {"AF_ATM", Const, 0}, - {"AF_ATMPVC", Const, 0}, - {"AF_ATMSVC", Const, 0}, - {"AF_AX25", Const, 0}, - {"AF_BLUETOOTH", Const, 0}, - {"AF_BRIDGE", Const, 0}, - {"AF_CAIF", Const, 0}, - {"AF_CAN", Const, 0}, - {"AF_CCITT", Const, 0}, - {"AF_CHAOS", Const, 0}, - {"AF_CNT", Const, 0}, - {"AF_COIP", Const, 0}, - {"AF_DATAKIT", Const, 0}, - {"AF_DECnet", Const, 0}, - {"AF_DLI", Const, 0}, - {"AF_E164", Const, 0}, - {"AF_ECMA", Const, 0}, - {"AF_ECONET", Const, 0}, - {"AF_ENCAP", Const, 1}, - {"AF_FILE", Const, 0}, - {"AF_HYLINK", Const, 0}, - {"AF_IEEE80211", Const, 0}, - {"AF_IEEE802154", Const, 0}, - {"AF_IMPLINK", Const, 0}, - {"AF_INET", Const, 0}, - {"AF_INET6", Const, 0}, - {"AF_INET6_SDP", Const, 3}, - {"AF_INET_SDP", Const, 3}, - {"AF_IPX", Const, 0}, - {"AF_IRDA", Const, 0}, - {"AF_ISDN", Const, 0}, - {"AF_ISO", Const, 0}, - {"AF_IUCV", Const, 0}, - {"AF_KEY", Const, 0}, - {"AF_LAT", Const, 0}, - {"AF_LINK", Const, 0}, - {"AF_LLC", Const, 0}, - {"AF_LOCAL", Const, 0}, - {"AF_MAX", Const, 0}, - {"AF_MPLS", Const, 1}, - {"AF_NATM", Const, 0}, - {"AF_NDRV", Const, 0}, - {"AF_NETBEUI", Const, 0}, - {"AF_NETBIOS", Const, 0}, - {"AF_NETGRAPH", Const, 0}, - {"AF_NETLINK", Const, 0}, - {"AF_NETROM", Const, 0}, - {"AF_NS", Const, 0}, - {"AF_OROUTE", Const, 1}, - {"AF_OSI", Const, 0}, - {"AF_PACKET", Const, 0}, - {"AF_PHONET", Const, 0}, - {"AF_PPP", Const, 0}, - {"AF_PPPOX", Const, 0}, - {"AF_PUP", Const, 0}, - {"AF_RDS", Const, 0}, - {"AF_RESERVED_36", Const, 0}, - {"AF_ROSE", Const, 0}, - {"AF_ROUTE", Const, 0}, - {"AF_RXRPC", Const, 0}, - {"AF_SCLUSTER", Const, 0}, - {"AF_SECURITY", Const, 0}, - {"AF_SIP", Const, 0}, - {"AF_SLOW", Const, 0}, - {"AF_SNA", Const, 0}, - {"AF_SYSTEM", Const, 0}, - {"AF_TIPC", Const, 0}, - {"AF_UNIX", Const, 0}, - {"AF_UNSPEC", Const, 0}, - {"AF_UTUN", Const, 16}, - {"AF_VENDOR00", Const, 0}, - {"AF_VENDOR01", Const, 0}, - {"AF_VENDOR02", Const, 0}, - {"AF_VENDOR03", Const, 0}, - {"AF_VENDOR04", Const, 0}, - {"AF_VENDOR05", Const, 0}, - {"AF_VENDOR06", Const, 0}, - {"AF_VENDOR07", Const, 0}, - {"AF_VENDOR08", Const, 0}, - {"AF_VENDOR09", Const, 0}, - {"AF_VENDOR10", Const, 0}, - {"AF_VENDOR11", Const, 0}, - {"AF_VENDOR12", Const, 0}, - {"AF_VENDOR13", Const, 0}, - {"AF_VENDOR14", Const, 0}, - {"AF_VENDOR15", Const, 0}, - {"AF_VENDOR16", Const, 0}, - {"AF_VENDOR17", Const, 0}, - {"AF_VENDOR18", Const, 0}, - {"AF_VENDOR19", Const, 0}, - {"AF_VENDOR20", Const, 0}, - {"AF_VENDOR21", Const, 0}, - {"AF_VENDOR22", Const, 0}, - {"AF_VENDOR23", Const, 0}, - {"AF_VENDOR24", Const, 0}, - {"AF_VENDOR25", Const, 0}, - {"AF_VENDOR26", Const, 0}, - {"AF_VENDOR27", Const, 0}, - {"AF_VENDOR28", Const, 0}, - {"AF_VENDOR29", Const, 0}, - {"AF_VENDOR30", Const, 0}, - {"AF_VENDOR31", Const, 0}, - {"AF_VENDOR32", Const, 0}, - {"AF_VENDOR33", Const, 0}, - {"AF_VENDOR34", Const, 0}, - {"AF_VENDOR35", Const, 0}, - {"AF_VENDOR36", Const, 0}, - {"AF_VENDOR37", Const, 0}, - {"AF_VENDOR38", Const, 0}, - {"AF_VENDOR39", Const, 0}, - {"AF_VENDOR40", Const, 0}, - {"AF_VENDOR41", Const, 0}, - {"AF_VENDOR42", Const, 0}, - {"AF_VENDOR43", Const, 0}, - {"AF_VENDOR44", Const, 0}, - {"AF_VENDOR45", Const, 0}, - {"AF_VENDOR46", Const, 0}, - {"AF_VENDOR47", Const, 0}, - {"AF_WANPIPE", Const, 0}, - {"AF_X25", Const, 0}, - {"AI_CANONNAME", Const, 1}, - {"AI_NUMERICHOST", Const, 1}, - {"AI_PASSIVE", Const, 1}, - {"APPLICATION_ERROR", Const, 0}, - {"ARPHRD_ADAPT", Const, 0}, - {"ARPHRD_APPLETLK", Const, 0}, - {"ARPHRD_ARCNET", Const, 0}, - {"ARPHRD_ASH", Const, 0}, - {"ARPHRD_ATM", Const, 0}, - {"ARPHRD_AX25", Const, 0}, - {"ARPHRD_BIF", Const, 0}, - {"ARPHRD_CHAOS", Const, 0}, - {"ARPHRD_CISCO", Const, 0}, - {"ARPHRD_CSLIP", Const, 0}, - {"ARPHRD_CSLIP6", Const, 0}, - {"ARPHRD_DDCMP", Const, 0}, - {"ARPHRD_DLCI", Const, 0}, - {"ARPHRD_ECONET", Const, 0}, - {"ARPHRD_EETHER", Const, 0}, - {"ARPHRD_ETHER", Const, 0}, - {"ARPHRD_EUI64", Const, 0}, - {"ARPHRD_FCAL", Const, 0}, - {"ARPHRD_FCFABRIC", Const, 0}, - {"ARPHRD_FCPL", Const, 0}, - {"ARPHRD_FCPP", Const, 0}, - {"ARPHRD_FDDI", Const, 0}, - {"ARPHRD_FRAD", Const, 0}, - {"ARPHRD_FRELAY", Const, 1}, - {"ARPHRD_HDLC", Const, 0}, - {"ARPHRD_HIPPI", Const, 0}, - {"ARPHRD_HWX25", Const, 0}, - {"ARPHRD_IEEE1394", Const, 0}, - {"ARPHRD_IEEE802", Const, 0}, - {"ARPHRD_IEEE80211", Const, 0}, - {"ARPHRD_IEEE80211_PRISM", Const, 0}, - {"ARPHRD_IEEE80211_RADIOTAP", Const, 0}, - {"ARPHRD_IEEE802154", Const, 0}, - {"ARPHRD_IEEE802154_PHY", Const, 0}, - {"ARPHRD_IEEE802_TR", Const, 0}, - {"ARPHRD_INFINIBAND", Const, 0}, - {"ARPHRD_IPDDP", Const, 0}, - {"ARPHRD_IPGRE", Const, 0}, - {"ARPHRD_IRDA", Const, 0}, - {"ARPHRD_LAPB", Const, 0}, - {"ARPHRD_LOCALTLK", Const, 0}, - {"ARPHRD_LOOPBACK", Const, 0}, - {"ARPHRD_METRICOM", Const, 0}, - {"ARPHRD_NETROM", Const, 0}, - {"ARPHRD_NONE", Const, 0}, - {"ARPHRD_PIMREG", Const, 0}, - {"ARPHRD_PPP", Const, 0}, - {"ARPHRD_PRONET", Const, 0}, - {"ARPHRD_RAWHDLC", Const, 0}, - {"ARPHRD_ROSE", Const, 0}, - {"ARPHRD_RSRVD", Const, 0}, - {"ARPHRD_SIT", Const, 0}, - {"ARPHRD_SKIP", Const, 0}, - {"ARPHRD_SLIP", Const, 0}, - {"ARPHRD_SLIP6", Const, 0}, - {"ARPHRD_STRIP", Const, 1}, - {"ARPHRD_TUNNEL", Const, 0}, - {"ARPHRD_TUNNEL6", Const, 0}, - {"ARPHRD_VOID", Const, 0}, - {"ARPHRD_X25", Const, 0}, - {"AUTHTYPE_CLIENT", Const, 0}, - {"AUTHTYPE_SERVER", Const, 0}, - {"Accept", Func, 0}, - {"Accept4", Func, 1}, - {"AcceptEx", Func, 0}, - {"Access", Func, 0}, - {"Acct", Func, 0}, - {"AddrinfoW", Type, 1}, - {"AddrinfoW.Addr", Field, 1}, - {"AddrinfoW.Addrlen", Field, 1}, - {"AddrinfoW.Canonname", Field, 1}, - {"AddrinfoW.Family", Field, 1}, - {"AddrinfoW.Flags", Field, 1}, - {"AddrinfoW.Next", Field, 1}, - {"AddrinfoW.Protocol", Field, 1}, - {"AddrinfoW.Socktype", Field, 1}, - {"Adjtime", Func, 0}, - {"Adjtimex", Func, 0}, - {"AllThreadsSyscall", Func, 16}, - {"AllThreadsSyscall6", Func, 16}, - {"AttachLsf", Func, 0}, - {"B0", Const, 0}, - {"B1000000", Const, 0}, - {"B110", Const, 0}, - {"B115200", Const, 0}, - {"B1152000", Const, 0}, - {"B1200", Const, 0}, - {"B134", Const, 0}, - {"B14400", Const, 1}, - {"B150", Const, 0}, - {"B1500000", Const, 0}, - {"B1800", Const, 0}, - {"B19200", Const, 0}, - {"B200", Const, 0}, - {"B2000000", Const, 0}, - {"B230400", Const, 0}, - {"B2400", Const, 0}, - {"B2500000", Const, 0}, - {"B28800", Const, 1}, - {"B300", Const, 0}, - {"B3000000", Const, 0}, - {"B3500000", Const, 0}, - {"B38400", Const, 0}, - {"B4000000", Const, 0}, - {"B460800", Const, 0}, - {"B4800", Const, 0}, - {"B50", Const, 0}, - {"B500000", Const, 0}, - {"B57600", Const, 0}, - {"B576000", Const, 0}, - {"B600", Const, 0}, - {"B7200", Const, 1}, - {"B75", Const, 0}, - {"B76800", Const, 1}, - {"B921600", Const, 0}, - {"B9600", Const, 0}, - {"BASE_PROTOCOL", Const, 2}, - {"BIOCFEEDBACK", Const, 0}, - {"BIOCFLUSH", Const, 0}, - {"BIOCGBLEN", Const, 0}, - {"BIOCGDIRECTION", Const, 0}, - {"BIOCGDIRFILT", Const, 1}, - {"BIOCGDLT", Const, 0}, - {"BIOCGDLTLIST", Const, 0}, - {"BIOCGETBUFMODE", Const, 0}, - {"BIOCGETIF", Const, 0}, - {"BIOCGETZMAX", Const, 0}, - {"BIOCGFEEDBACK", Const, 1}, - {"BIOCGFILDROP", Const, 1}, - {"BIOCGHDRCMPLT", Const, 0}, - {"BIOCGRSIG", Const, 0}, - {"BIOCGRTIMEOUT", Const, 0}, - {"BIOCGSEESENT", Const, 0}, - {"BIOCGSTATS", Const, 0}, - {"BIOCGSTATSOLD", Const, 1}, - {"BIOCGTSTAMP", Const, 1}, - {"BIOCIMMEDIATE", Const, 0}, - {"BIOCLOCK", Const, 0}, - {"BIOCPROMISC", Const, 0}, - {"BIOCROTZBUF", Const, 0}, - {"BIOCSBLEN", Const, 0}, - {"BIOCSDIRECTION", Const, 0}, - {"BIOCSDIRFILT", Const, 1}, - {"BIOCSDLT", Const, 0}, - {"BIOCSETBUFMODE", Const, 0}, - {"BIOCSETF", Const, 0}, - {"BIOCSETFNR", Const, 0}, - {"BIOCSETIF", Const, 0}, - {"BIOCSETWF", Const, 0}, - {"BIOCSETZBUF", Const, 0}, - {"BIOCSFEEDBACK", Const, 1}, - {"BIOCSFILDROP", Const, 1}, - {"BIOCSHDRCMPLT", Const, 0}, - {"BIOCSRSIG", Const, 0}, - {"BIOCSRTIMEOUT", Const, 0}, - {"BIOCSSEESENT", Const, 0}, - {"BIOCSTCPF", Const, 1}, - {"BIOCSTSTAMP", Const, 1}, - {"BIOCSUDPF", Const, 1}, - {"BIOCVERSION", Const, 0}, - {"BPF_A", Const, 0}, - {"BPF_ABS", Const, 0}, - {"BPF_ADD", Const, 0}, - {"BPF_ALIGNMENT", Const, 0}, - {"BPF_ALIGNMENT32", Const, 1}, - {"BPF_ALU", Const, 0}, - {"BPF_AND", Const, 0}, - {"BPF_B", Const, 0}, - {"BPF_BUFMODE_BUFFER", Const, 0}, - {"BPF_BUFMODE_ZBUF", Const, 0}, - {"BPF_DFLTBUFSIZE", Const, 1}, - {"BPF_DIRECTION_IN", Const, 1}, - {"BPF_DIRECTION_OUT", Const, 1}, - {"BPF_DIV", Const, 0}, - {"BPF_H", Const, 0}, - {"BPF_IMM", Const, 0}, - {"BPF_IND", Const, 0}, - {"BPF_JA", Const, 0}, - {"BPF_JEQ", Const, 0}, - {"BPF_JGE", Const, 0}, - {"BPF_JGT", Const, 0}, - {"BPF_JMP", Const, 0}, - {"BPF_JSET", Const, 0}, - {"BPF_K", Const, 0}, - {"BPF_LD", Const, 0}, - {"BPF_LDX", Const, 0}, - {"BPF_LEN", Const, 0}, - {"BPF_LSH", Const, 0}, - {"BPF_MAJOR_VERSION", Const, 0}, - {"BPF_MAXBUFSIZE", Const, 0}, - {"BPF_MAXINSNS", Const, 0}, - {"BPF_MEM", Const, 0}, - {"BPF_MEMWORDS", Const, 0}, - {"BPF_MINBUFSIZE", Const, 0}, - {"BPF_MINOR_VERSION", Const, 0}, - {"BPF_MISC", Const, 0}, - {"BPF_MSH", Const, 0}, - {"BPF_MUL", Const, 0}, - {"BPF_NEG", Const, 0}, - {"BPF_OR", Const, 0}, - {"BPF_RELEASE", Const, 0}, - {"BPF_RET", Const, 0}, - {"BPF_RSH", Const, 0}, - {"BPF_ST", Const, 0}, - {"BPF_STX", Const, 0}, - {"BPF_SUB", Const, 0}, - {"BPF_TAX", Const, 0}, - {"BPF_TXA", Const, 0}, - {"BPF_T_BINTIME", Const, 1}, - {"BPF_T_BINTIME_FAST", Const, 1}, - {"BPF_T_BINTIME_MONOTONIC", Const, 1}, - {"BPF_T_BINTIME_MONOTONIC_FAST", Const, 1}, - {"BPF_T_FAST", Const, 1}, - {"BPF_T_FLAG_MASK", Const, 1}, - {"BPF_T_FORMAT_MASK", Const, 1}, - {"BPF_T_MICROTIME", Const, 1}, - {"BPF_T_MICROTIME_FAST", Const, 1}, - {"BPF_T_MICROTIME_MONOTONIC", Const, 1}, - {"BPF_T_MICROTIME_MONOTONIC_FAST", Const, 1}, - {"BPF_T_MONOTONIC", Const, 1}, - {"BPF_T_MONOTONIC_FAST", Const, 1}, - {"BPF_T_NANOTIME", Const, 1}, - {"BPF_T_NANOTIME_FAST", Const, 1}, - {"BPF_T_NANOTIME_MONOTONIC", Const, 1}, - {"BPF_T_NANOTIME_MONOTONIC_FAST", Const, 1}, - {"BPF_T_NONE", Const, 1}, - {"BPF_T_NORMAL", Const, 1}, - {"BPF_W", Const, 0}, - {"BPF_X", Const, 0}, - {"BRKINT", Const, 0}, - {"Bind", Func, 0}, - {"BindToDevice", Func, 0}, - {"BpfBuflen", Func, 0}, - {"BpfDatalink", Func, 0}, - {"BpfHdr", Type, 0}, - {"BpfHdr.Caplen", Field, 0}, - {"BpfHdr.Datalen", Field, 0}, - {"BpfHdr.Hdrlen", Field, 0}, - {"BpfHdr.Pad_cgo_0", Field, 0}, - {"BpfHdr.Tstamp", Field, 0}, - {"BpfHeadercmpl", Func, 0}, - {"BpfInsn", Type, 0}, - {"BpfInsn.Code", Field, 0}, - {"BpfInsn.Jf", Field, 0}, - {"BpfInsn.Jt", Field, 0}, - {"BpfInsn.K", Field, 0}, - {"BpfInterface", Func, 0}, - {"BpfJump", Func, 0}, - {"BpfProgram", Type, 0}, - {"BpfProgram.Insns", Field, 0}, - {"BpfProgram.Len", Field, 0}, - {"BpfProgram.Pad_cgo_0", Field, 0}, - {"BpfStat", Type, 0}, - {"BpfStat.Capt", Field, 2}, - {"BpfStat.Drop", Field, 0}, - {"BpfStat.Padding", Field, 2}, - {"BpfStat.Recv", Field, 0}, - {"BpfStats", Func, 0}, - {"BpfStmt", Func, 0}, - {"BpfTimeout", Func, 0}, - {"BpfTimeval", Type, 2}, - {"BpfTimeval.Sec", Field, 2}, - {"BpfTimeval.Usec", Field, 2}, - {"BpfVersion", Type, 0}, - {"BpfVersion.Major", Field, 0}, - {"BpfVersion.Minor", Field, 0}, - {"BpfZbuf", Type, 0}, - {"BpfZbuf.Bufa", Field, 0}, - {"BpfZbuf.Bufb", Field, 0}, - {"BpfZbuf.Buflen", Field, 0}, - {"BpfZbufHeader", Type, 0}, - {"BpfZbufHeader.Kernel_gen", Field, 0}, - {"BpfZbufHeader.Kernel_len", Field, 0}, - {"BpfZbufHeader.User_gen", Field, 0}, - {"BpfZbufHeader.X_bzh_pad", Field, 0}, - {"ByHandleFileInformation", Type, 0}, - {"ByHandleFileInformation.CreationTime", Field, 0}, - {"ByHandleFileInformation.FileAttributes", Field, 0}, - {"ByHandleFileInformation.FileIndexHigh", Field, 0}, - {"ByHandleFileInformation.FileIndexLow", Field, 0}, - {"ByHandleFileInformation.FileSizeHigh", Field, 0}, - {"ByHandleFileInformation.FileSizeLow", Field, 0}, - {"ByHandleFileInformation.LastAccessTime", Field, 0}, - {"ByHandleFileInformation.LastWriteTime", Field, 0}, - {"ByHandleFileInformation.NumberOfLinks", Field, 0}, - {"ByHandleFileInformation.VolumeSerialNumber", Field, 0}, - {"BytePtrFromString", Func, 1}, - {"ByteSliceFromString", Func, 1}, - {"CCR0_FLUSH", Const, 1}, - {"CERT_CHAIN_POLICY_AUTHENTICODE", Const, 0}, - {"CERT_CHAIN_POLICY_AUTHENTICODE_TS", Const, 0}, - {"CERT_CHAIN_POLICY_BASE", Const, 0}, - {"CERT_CHAIN_POLICY_BASIC_CONSTRAINTS", Const, 0}, - {"CERT_CHAIN_POLICY_EV", Const, 0}, - {"CERT_CHAIN_POLICY_MICROSOFT_ROOT", Const, 0}, - {"CERT_CHAIN_POLICY_NT_AUTH", Const, 0}, - {"CERT_CHAIN_POLICY_SSL", Const, 0}, - {"CERT_E_CN_NO_MATCH", Const, 0}, - {"CERT_E_EXPIRED", Const, 0}, - {"CERT_E_PURPOSE", Const, 0}, - {"CERT_E_ROLE", Const, 0}, - {"CERT_E_UNTRUSTEDROOT", Const, 0}, - {"CERT_STORE_ADD_ALWAYS", Const, 0}, - {"CERT_STORE_DEFER_CLOSE_UNTIL_LAST_FREE_FLAG", Const, 0}, - {"CERT_STORE_PROV_MEMORY", Const, 0}, - {"CERT_TRUST_HAS_EXCLUDED_NAME_CONSTRAINT", Const, 0}, - {"CERT_TRUST_HAS_NOT_DEFINED_NAME_CONSTRAINT", Const, 0}, - {"CERT_TRUST_HAS_NOT_PERMITTED_NAME_CONSTRAINT", Const, 0}, - {"CERT_TRUST_HAS_NOT_SUPPORTED_CRITICAL_EXT", Const, 0}, - {"CERT_TRUST_HAS_NOT_SUPPORTED_NAME_CONSTRAINT", Const, 0}, - {"CERT_TRUST_INVALID_BASIC_CONSTRAINTS", Const, 0}, - {"CERT_TRUST_INVALID_EXTENSION", Const, 0}, - {"CERT_TRUST_INVALID_NAME_CONSTRAINTS", Const, 0}, - {"CERT_TRUST_INVALID_POLICY_CONSTRAINTS", Const, 0}, - {"CERT_TRUST_IS_CYCLIC", Const, 0}, - {"CERT_TRUST_IS_EXPLICIT_DISTRUST", Const, 0}, - {"CERT_TRUST_IS_NOT_SIGNATURE_VALID", Const, 0}, - {"CERT_TRUST_IS_NOT_TIME_VALID", Const, 0}, - {"CERT_TRUST_IS_NOT_VALID_FOR_USAGE", Const, 0}, - {"CERT_TRUST_IS_OFFLINE_REVOCATION", Const, 0}, - {"CERT_TRUST_IS_REVOKED", Const, 0}, - {"CERT_TRUST_IS_UNTRUSTED_ROOT", Const, 0}, - {"CERT_TRUST_NO_ERROR", Const, 0}, - {"CERT_TRUST_NO_ISSUANCE_CHAIN_POLICY", Const, 0}, - {"CERT_TRUST_REVOCATION_STATUS_UNKNOWN", Const, 0}, - {"CFLUSH", Const, 1}, - {"CLOCAL", Const, 0}, - {"CLONE_CHILD_CLEARTID", Const, 2}, - {"CLONE_CHILD_SETTID", Const, 2}, - {"CLONE_CLEAR_SIGHAND", Const, 20}, - {"CLONE_CSIGNAL", Const, 3}, - {"CLONE_DETACHED", Const, 2}, - {"CLONE_FILES", Const, 2}, - {"CLONE_FS", Const, 2}, - {"CLONE_INTO_CGROUP", Const, 20}, - {"CLONE_IO", Const, 2}, - {"CLONE_NEWCGROUP", Const, 20}, - {"CLONE_NEWIPC", Const, 2}, - {"CLONE_NEWNET", Const, 2}, - {"CLONE_NEWNS", Const, 2}, - {"CLONE_NEWPID", Const, 2}, - {"CLONE_NEWTIME", Const, 20}, - {"CLONE_NEWUSER", Const, 2}, - {"CLONE_NEWUTS", Const, 2}, - {"CLONE_PARENT", Const, 2}, - {"CLONE_PARENT_SETTID", Const, 2}, - {"CLONE_PID", Const, 3}, - {"CLONE_PIDFD", Const, 20}, - {"CLONE_PTRACE", Const, 2}, - {"CLONE_SETTLS", Const, 2}, - {"CLONE_SIGHAND", Const, 2}, - {"CLONE_SYSVSEM", Const, 2}, - {"CLONE_THREAD", Const, 2}, - {"CLONE_UNTRACED", Const, 2}, - {"CLONE_VFORK", Const, 2}, - {"CLONE_VM", Const, 2}, - {"CPUID_CFLUSH", Const, 1}, - {"CREAD", Const, 0}, - {"CREATE_ALWAYS", Const, 0}, - {"CREATE_NEW", Const, 0}, - {"CREATE_NEW_PROCESS_GROUP", Const, 1}, - {"CREATE_UNICODE_ENVIRONMENT", Const, 0}, - {"CRYPT_DEFAULT_CONTAINER_OPTIONAL", Const, 0}, - {"CRYPT_DELETEKEYSET", Const, 0}, - {"CRYPT_MACHINE_KEYSET", Const, 0}, - {"CRYPT_NEWKEYSET", Const, 0}, - {"CRYPT_SILENT", Const, 0}, - {"CRYPT_VERIFYCONTEXT", Const, 0}, - {"CS5", Const, 0}, - {"CS6", Const, 0}, - {"CS7", Const, 0}, - {"CS8", Const, 0}, - {"CSIZE", Const, 0}, - {"CSTART", Const, 1}, - {"CSTATUS", Const, 1}, - {"CSTOP", Const, 1}, - {"CSTOPB", Const, 0}, - {"CSUSP", Const, 1}, - {"CTL_MAXNAME", Const, 0}, - {"CTL_NET", Const, 0}, - {"CTL_QUERY", Const, 1}, - {"CTRL_BREAK_EVENT", Const, 1}, - {"CTRL_CLOSE_EVENT", Const, 14}, - {"CTRL_C_EVENT", Const, 1}, - {"CTRL_LOGOFF_EVENT", Const, 14}, - {"CTRL_SHUTDOWN_EVENT", Const, 14}, - {"CancelIo", Func, 0}, - {"CancelIoEx", Func, 1}, - {"CertAddCertificateContextToStore", Func, 0}, - {"CertChainContext", Type, 0}, - {"CertChainContext.ChainCount", Field, 0}, - {"CertChainContext.Chains", Field, 0}, - {"CertChainContext.HasRevocationFreshnessTime", Field, 0}, - {"CertChainContext.LowerQualityChainCount", Field, 0}, - {"CertChainContext.LowerQualityChains", Field, 0}, - {"CertChainContext.RevocationFreshnessTime", Field, 0}, - {"CertChainContext.Size", Field, 0}, - {"CertChainContext.TrustStatus", Field, 0}, - {"CertChainElement", Type, 0}, - {"CertChainElement.ApplicationUsage", Field, 0}, - {"CertChainElement.CertContext", Field, 0}, - {"CertChainElement.ExtendedErrorInfo", Field, 0}, - {"CertChainElement.IssuanceUsage", Field, 0}, - {"CertChainElement.RevocationInfo", Field, 0}, - {"CertChainElement.Size", Field, 0}, - {"CertChainElement.TrustStatus", Field, 0}, - {"CertChainPara", Type, 0}, - {"CertChainPara.CacheResync", Field, 0}, - {"CertChainPara.CheckRevocationFreshnessTime", Field, 0}, - {"CertChainPara.RequestedUsage", Field, 0}, - {"CertChainPara.RequstedIssuancePolicy", Field, 0}, - {"CertChainPara.RevocationFreshnessTime", Field, 0}, - {"CertChainPara.Size", Field, 0}, - {"CertChainPara.URLRetrievalTimeout", Field, 0}, - {"CertChainPolicyPara", Type, 0}, - {"CertChainPolicyPara.ExtraPolicyPara", Field, 0}, - {"CertChainPolicyPara.Flags", Field, 0}, - {"CertChainPolicyPara.Size", Field, 0}, - {"CertChainPolicyStatus", Type, 0}, - {"CertChainPolicyStatus.ChainIndex", Field, 0}, - {"CertChainPolicyStatus.ElementIndex", Field, 0}, - {"CertChainPolicyStatus.Error", Field, 0}, - {"CertChainPolicyStatus.ExtraPolicyStatus", Field, 0}, - {"CertChainPolicyStatus.Size", Field, 0}, - {"CertCloseStore", Func, 0}, - {"CertContext", Type, 0}, - {"CertContext.CertInfo", Field, 0}, - {"CertContext.EncodedCert", Field, 0}, - {"CertContext.EncodingType", Field, 0}, - {"CertContext.Length", Field, 0}, - {"CertContext.Store", Field, 0}, - {"CertCreateCertificateContext", Func, 0}, - {"CertEnhKeyUsage", Type, 0}, - {"CertEnhKeyUsage.Length", Field, 0}, - {"CertEnhKeyUsage.UsageIdentifiers", Field, 0}, - {"CertEnumCertificatesInStore", Func, 0}, - {"CertFreeCertificateChain", Func, 0}, - {"CertFreeCertificateContext", Func, 0}, - {"CertGetCertificateChain", Func, 0}, - {"CertInfo", Type, 11}, - {"CertOpenStore", Func, 0}, - {"CertOpenSystemStore", Func, 0}, - {"CertRevocationCrlInfo", Type, 11}, - {"CertRevocationInfo", Type, 0}, - {"CertRevocationInfo.CrlInfo", Field, 0}, - {"CertRevocationInfo.FreshnessTime", Field, 0}, - {"CertRevocationInfo.HasFreshnessTime", Field, 0}, - {"CertRevocationInfo.OidSpecificInfo", Field, 0}, - {"CertRevocationInfo.RevocationOid", Field, 0}, - {"CertRevocationInfo.RevocationResult", Field, 0}, - {"CertRevocationInfo.Size", Field, 0}, - {"CertSimpleChain", Type, 0}, - {"CertSimpleChain.Elements", Field, 0}, - {"CertSimpleChain.HasRevocationFreshnessTime", Field, 0}, - {"CertSimpleChain.NumElements", Field, 0}, - {"CertSimpleChain.RevocationFreshnessTime", Field, 0}, - {"CertSimpleChain.Size", Field, 0}, - {"CertSimpleChain.TrustListInfo", Field, 0}, - {"CertSimpleChain.TrustStatus", Field, 0}, - {"CertTrustListInfo", Type, 11}, - {"CertTrustStatus", Type, 0}, - {"CertTrustStatus.ErrorStatus", Field, 0}, - {"CertTrustStatus.InfoStatus", Field, 0}, - {"CertUsageMatch", Type, 0}, - {"CertUsageMatch.Type", Field, 0}, - {"CertUsageMatch.Usage", Field, 0}, - {"CertVerifyCertificateChainPolicy", Func, 0}, - {"Chdir", Func, 0}, - {"CheckBpfVersion", Func, 0}, - {"Chflags", Func, 0}, - {"Chmod", Func, 0}, - {"Chown", Func, 0}, - {"Chroot", Func, 0}, - {"Clearenv", Func, 0}, - {"Close", Func, 0}, - {"CloseHandle", Func, 0}, - {"CloseOnExec", Func, 0}, - {"Closesocket", Func, 0}, - {"CmsgLen", Func, 0}, - {"CmsgSpace", Func, 0}, - {"Cmsghdr", Type, 0}, - {"Cmsghdr.Len", Field, 0}, - {"Cmsghdr.Level", Field, 0}, - {"Cmsghdr.Type", Field, 0}, - {"Cmsghdr.X__cmsg_data", Field, 0}, - {"CommandLineToArgv", Func, 0}, - {"ComputerName", Func, 0}, - {"Conn", Type, 9}, - {"Connect", Func, 0}, - {"ConnectEx", Func, 1}, - {"ConvertSidToStringSid", Func, 0}, - {"ConvertStringSidToSid", Func, 0}, - {"CopySid", Func, 0}, - {"Creat", Func, 0}, - {"CreateDirectory", Func, 0}, - {"CreateFile", Func, 0}, - {"CreateFileMapping", Func, 0}, - {"CreateHardLink", Func, 4}, - {"CreateIoCompletionPort", Func, 0}, - {"CreatePipe", Func, 0}, - {"CreateProcess", Func, 0}, - {"CreateProcessAsUser", Func, 10}, - {"CreateSymbolicLink", Func, 4}, - {"CreateToolhelp32Snapshot", Func, 4}, - {"Credential", Type, 0}, - {"Credential.Gid", Field, 0}, - {"Credential.Groups", Field, 0}, - {"Credential.NoSetGroups", Field, 9}, - {"Credential.Uid", Field, 0}, - {"CryptAcquireContext", Func, 0}, - {"CryptGenRandom", Func, 0}, - {"CryptReleaseContext", Func, 0}, - {"DIOCBSFLUSH", Const, 1}, - {"DIOCOSFPFLUSH", Const, 1}, - {"DLL", Type, 0}, - {"DLL.Handle", Field, 0}, - {"DLL.Name", Field, 0}, - {"DLLError", Type, 0}, - {"DLLError.Err", Field, 0}, - {"DLLError.Msg", Field, 0}, - {"DLLError.ObjName", Field, 0}, - {"DLT_A429", Const, 0}, - {"DLT_A653_ICM", Const, 0}, - {"DLT_AIRONET_HEADER", Const, 0}, - {"DLT_AOS", Const, 1}, - {"DLT_APPLE_IP_OVER_IEEE1394", Const, 0}, - {"DLT_ARCNET", Const, 0}, - {"DLT_ARCNET_LINUX", Const, 0}, - {"DLT_ATM_CLIP", Const, 0}, - {"DLT_ATM_RFC1483", Const, 0}, - {"DLT_AURORA", Const, 0}, - {"DLT_AX25", Const, 0}, - {"DLT_AX25_KISS", Const, 0}, - {"DLT_BACNET_MS_TP", Const, 0}, - {"DLT_BLUETOOTH_HCI_H4", Const, 0}, - {"DLT_BLUETOOTH_HCI_H4_WITH_PHDR", Const, 0}, - {"DLT_CAN20B", Const, 0}, - {"DLT_CAN_SOCKETCAN", Const, 1}, - {"DLT_CHAOS", Const, 0}, - {"DLT_CHDLC", Const, 0}, - {"DLT_CISCO_IOS", Const, 0}, - {"DLT_C_HDLC", Const, 0}, - {"DLT_C_HDLC_WITH_DIR", Const, 0}, - {"DLT_DBUS", Const, 1}, - {"DLT_DECT", Const, 1}, - {"DLT_DOCSIS", Const, 0}, - {"DLT_DVB_CI", Const, 1}, - {"DLT_ECONET", Const, 0}, - {"DLT_EN10MB", Const, 0}, - {"DLT_EN3MB", Const, 0}, - {"DLT_ENC", Const, 0}, - {"DLT_ERF", Const, 0}, - {"DLT_ERF_ETH", Const, 0}, - {"DLT_ERF_POS", Const, 0}, - {"DLT_FC_2", Const, 1}, - {"DLT_FC_2_WITH_FRAME_DELIMS", Const, 1}, - {"DLT_FDDI", Const, 0}, - {"DLT_FLEXRAY", Const, 0}, - {"DLT_FRELAY", Const, 0}, - {"DLT_FRELAY_WITH_DIR", Const, 0}, - {"DLT_GCOM_SERIAL", Const, 0}, - {"DLT_GCOM_T1E1", Const, 0}, - {"DLT_GPF_F", Const, 0}, - {"DLT_GPF_T", Const, 0}, - {"DLT_GPRS_LLC", Const, 0}, - {"DLT_GSMTAP_ABIS", Const, 1}, - {"DLT_GSMTAP_UM", Const, 1}, - {"DLT_HDLC", Const, 1}, - {"DLT_HHDLC", Const, 0}, - {"DLT_HIPPI", Const, 1}, - {"DLT_IBM_SN", Const, 0}, - {"DLT_IBM_SP", Const, 0}, - {"DLT_IEEE802", Const, 0}, - {"DLT_IEEE802_11", Const, 0}, - {"DLT_IEEE802_11_RADIO", Const, 0}, - {"DLT_IEEE802_11_RADIO_AVS", Const, 0}, - {"DLT_IEEE802_15_4", Const, 0}, - {"DLT_IEEE802_15_4_LINUX", Const, 0}, - {"DLT_IEEE802_15_4_NOFCS", Const, 1}, - {"DLT_IEEE802_15_4_NONASK_PHY", Const, 0}, - {"DLT_IEEE802_16_MAC_CPS", Const, 0}, - {"DLT_IEEE802_16_MAC_CPS_RADIO", Const, 0}, - {"DLT_IPFILTER", Const, 0}, - {"DLT_IPMB", Const, 0}, - {"DLT_IPMB_LINUX", Const, 0}, - {"DLT_IPNET", Const, 1}, - {"DLT_IPOIB", Const, 1}, - {"DLT_IPV4", Const, 1}, - {"DLT_IPV6", Const, 1}, - {"DLT_IP_OVER_FC", Const, 0}, - {"DLT_JUNIPER_ATM1", Const, 0}, - {"DLT_JUNIPER_ATM2", Const, 0}, - {"DLT_JUNIPER_ATM_CEMIC", Const, 1}, - {"DLT_JUNIPER_CHDLC", Const, 0}, - {"DLT_JUNIPER_ES", Const, 0}, - {"DLT_JUNIPER_ETHER", Const, 0}, - {"DLT_JUNIPER_FIBRECHANNEL", Const, 1}, - {"DLT_JUNIPER_FRELAY", Const, 0}, - {"DLT_JUNIPER_GGSN", Const, 0}, - {"DLT_JUNIPER_ISM", Const, 0}, - {"DLT_JUNIPER_MFR", Const, 0}, - {"DLT_JUNIPER_MLFR", Const, 0}, - {"DLT_JUNIPER_MLPPP", Const, 0}, - {"DLT_JUNIPER_MONITOR", Const, 0}, - {"DLT_JUNIPER_PIC_PEER", Const, 0}, - {"DLT_JUNIPER_PPP", Const, 0}, - {"DLT_JUNIPER_PPPOE", Const, 0}, - {"DLT_JUNIPER_PPPOE_ATM", Const, 0}, - {"DLT_JUNIPER_SERVICES", Const, 0}, - {"DLT_JUNIPER_SRX_E2E", Const, 1}, - {"DLT_JUNIPER_ST", Const, 0}, - {"DLT_JUNIPER_VP", Const, 0}, - {"DLT_JUNIPER_VS", Const, 1}, - {"DLT_LAPB_WITH_DIR", Const, 0}, - {"DLT_LAPD", Const, 0}, - {"DLT_LIN", Const, 0}, - {"DLT_LINUX_EVDEV", Const, 1}, - {"DLT_LINUX_IRDA", Const, 0}, - {"DLT_LINUX_LAPD", Const, 0}, - {"DLT_LINUX_PPP_WITHDIRECTION", Const, 0}, - {"DLT_LINUX_SLL", Const, 0}, - {"DLT_LOOP", Const, 0}, - {"DLT_LTALK", Const, 0}, - {"DLT_MATCHING_MAX", Const, 1}, - {"DLT_MATCHING_MIN", Const, 1}, - {"DLT_MFR", Const, 0}, - {"DLT_MOST", Const, 0}, - {"DLT_MPEG_2_TS", Const, 1}, - {"DLT_MPLS", Const, 1}, - {"DLT_MTP2", Const, 0}, - {"DLT_MTP2_WITH_PHDR", Const, 0}, - {"DLT_MTP3", Const, 0}, - {"DLT_MUX27010", Const, 1}, - {"DLT_NETANALYZER", Const, 1}, - {"DLT_NETANALYZER_TRANSPARENT", Const, 1}, - {"DLT_NFC_LLCP", Const, 1}, - {"DLT_NFLOG", Const, 1}, - {"DLT_NG40", Const, 1}, - {"DLT_NULL", Const, 0}, - {"DLT_PCI_EXP", Const, 0}, - {"DLT_PFLOG", Const, 0}, - {"DLT_PFSYNC", Const, 0}, - {"DLT_PPI", Const, 0}, - {"DLT_PPP", Const, 0}, - {"DLT_PPP_BSDOS", Const, 0}, - {"DLT_PPP_ETHER", Const, 0}, - {"DLT_PPP_PPPD", Const, 0}, - {"DLT_PPP_SERIAL", Const, 0}, - {"DLT_PPP_WITH_DIR", Const, 0}, - {"DLT_PPP_WITH_DIRECTION", Const, 0}, - {"DLT_PRISM_HEADER", Const, 0}, - {"DLT_PRONET", Const, 0}, - {"DLT_RAIF1", Const, 0}, - {"DLT_RAW", Const, 0}, - {"DLT_RAWAF_MASK", Const, 1}, - {"DLT_RIO", Const, 0}, - {"DLT_SCCP", Const, 0}, - {"DLT_SITA", Const, 0}, - {"DLT_SLIP", Const, 0}, - {"DLT_SLIP_BSDOS", Const, 0}, - {"DLT_STANAG_5066_D_PDU", Const, 1}, - {"DLT_SUNATM", Const, 0}, - {"DLT_SYMANTEC_FIREWALL", Const, 0}, - {"DLT_TZSP", Const, 0}, - {"DLT_USB", Const, 0}, - {"DLT_USB_LINUX", Const, 0}, - {"DLT_USB_LINUX_MMAPPED", Const, 1}, - {"DLT_USER0", Const, 0}, - {"DLT_USER1", Const, 0}, - {"DLT_USER10", Const, 0}, - {"DLT_USER11", Const, 0}, - {"DLT_USER12", Const, 0}, - {"DLT_USER13", Const, 0}, - {"DLT_USER14", Const, 0}, - {"DLT_USER15", Const, 0}, - {"DLT_USER2", Const, 0}, - {"DLT_USER3", Const, 0}, - {"DLT_USER4", Const, 0}, - {"DLT_USER5", Const, 0}, - {"DLT_USER6", Const, 0}, - {"DLT_USER7", Const, 0}, - {"DLT_USER8", Const, 0}, - {"DLT_USER9", Const, 0}, - {"DLT_WIHART", Const, 1}, - {"DLT_X2E_SERIAL", Const, 0}, - {"DLT_X2E_XORAYA", Const, 0}, - {"DNSMXData", Type, 0}, - {"DNSMXData.NameExchange", Field, 0}, - {"DNSMXData.Pad", Field, 0}, - {"DNSMXData.Preference", Field, 0}, - {"DNSPTRData", Type, 0}, - {"DNSPTRData.Host", Field, 0}, - {"DNSRecord", Type, 0}, - {"DNSRecord.Data", Field, 0}, - {"DNSRecord.Dw", Field, 0}, - {"DNSRecord.Length", Field, 0}, - {"DNSRecord.Name", Field, 0}, - {"DNSRecord.Next", Field, 0}, - {"DNSRecord.Reserved", Field, 0}, - {"DNSRecord.Ttl", Field, 0}, - {"DNSRecord.Type", Field, 0}, - {"DNSSRVData", Type, 0}, - {"DNSSRVData.Pad", Field, 0}, - {"DNSSRVData.Port", Field, 0}, - {"DNSSRVData.Priority", Field, 0}, - {"DNSSRVData.Target", Field, 0}, - {"DNSSRVData.Weight", Field, 0}, - {"DNSTXTData", Type, 0}, - {"DNSTXTData.StringArray", Field, 0}, - {"DNSTXTData.StringCount", Field, 0}, - {"DNS_INFO_NO_RECORDS", Const, 4}, - {"DNS_TYPE_A", Const, 0}, - {"DNS_TYPE_A6", Const, 0}, - {"DNS_TYPE_AAAA", Const, 0}, - {"DNS_TYPE_ADDRS", Const, 0}, - {"DNS_TYPE_AFSDB", Const, 0}, - {"DNS_TYPE_ALL", Const, 0}, - {"DNS_TYPE_ANY", Const, 0}, - {"DNS_TYPE_ATMA", Const, 0}, - {"DNS_TYPE_AXFR", Const, 0}, - {"DNS_TYPE_CERT", Const, 0}, - {"DNS_TYPE_CNAME", Const, 0}, - {"DNS_TYPE_DHCID", Const, 0}, - {"DNS_TYPE_DNAME", Const, 0}, - {"DNS_TYPE_DNSKEY", Const, 0}, - {"DNS_TYPE_DS", Const, 0}, - {"DNS_TYPE_EID", Const, 0}, - {"DNS_TYPE_GID", Const, 0}, - {"DNS_TYPE_GPOS", Const, 0}, - {"DNS_TYPE_HINFO", Const, 0}, - {"DNS_TYPE_ISDN", Const, 0}, - {"DNS_TYPE_IXFR", Const, 0}, - {"DNS_TYPE_KEY", Const, 0}, - {"DNS_TYPE_KX", Const, 0}, - {"DNS_TYPE_LOC", Const, 0}, - {"DNS_TYPE_MAILA", Const, 0}, - {"DNS_TYPE_MAILB", Const, 0}, - {"DNS_TYPE_MB", Const, 0}, - {"DNS_TYPE_MD", Const, 0}, - {"DNS_TYPE_MF", Const, 0}, - {"DNS_TYPE_MG", Const, 0}, - {"DNS_TYPE_MINFO", Const, 0}, - {"DNS_TYPE_MR", Const, 0}, - {"DNS_TYPE_MX", Const, 0}, - {"DNS_TYPE_NAPTR", Const, 0}, - {"DNS_TYPE_NBSTAT", Const, 0}, - {"DNS_TYPE_NIMLOC", Const, 0}, - {"DNS_TYPE_NS", Const, 0}, - {"DNS_TYPE_NSAP", Const, 0}, - {"DNS_TYPE_NSAPPTR", Const, 0}, - {"DNS_TYPE_NSEC", Const, 0}, - {"DNS_TYPE_NULL", Const, 0}, - {"DNS_TYPE_NXT", Const, 0}, - {"DNS_TYPE_OPT", Const, 0}, - {"DNS_TYPE_PTR", Const, 0}, - {"DNS_TYPE_PX", Const, 0}, - {"DNS_TYPE_RP", Const, 0}, - {"DNS_TYPE_RRSIG", Const, 0}, - {"DNS_TYPE_RT", Const, 0}, - {"DNS_TYPE_SIG", Const, 0}, - {"DNS_TYPE_SINK", Const, 0}, - {"DNS_TYPE_SOA", Const, 0}, - {"DNS_TYPE_SRV", Const, 0}, - {"DNS_TYPE_TEXT", Const, 0}, - {"DNS_TYPE_TKEY", Const, 0}, - {"DNS_TYPE_TSIG", Const, 0}, - {"DNS_TYPE_UID", Const, 0}, - {"DNS_TYPE_UINFO", Const, 0}, - {"DNS_TYPE_UNSPEC", Const, 0}, - {"DNS_TYPE_WINS", Const, 0}, - {"DNS_TYPE_WINSR", Const, 0}, - {"DNS_TYPE_WKS", Const, 0}, - {"DNS_TYPE_X25", Const, 0}, - {"DT_BLK", Const, 0}, - {"DT_CHR", Const, 0}, - {"DT_DIR", Const, 0}, - {"DT_FIFO", Const, 0}, - {"DT_LNK", Const, 0}, - {"DT_REG", Const, 0}, - {"DT_SOCK", Const, 0}, - {"DT_UNKNOWN", Const, 0}, - {"DT_WHT", Const, 0}, - {"DUPLICATE_CLOSE_SOURCE", Const, 0}, - {"DUPLICATE_SAME_ACCESS", Const, 0}, - {"DeleteFile", Func, 0}, - {"DetachLsf", Func, 0}, - {"DeviceIoControl", Func, 4}, - {"Dirent", Type, 0}, - {"Dirent.Fileno", Field, 0}, - {"Dirent.Ino", Field, 0}, - {"Dirent.Name", Field, 0}, - {"Dirent.Namlen", Field, 0}, - {"Dirent.Off", Field, 0}, - {"Dirent.Pad0", Field, 12}, - {"Dirent.Pad1", Field, 12}, - {"Dirent.Pad_cgo_0", Field, 0}, - {"Dirent.Reclen", Field, 0}, - {"Dirent.Seekoff", Field, 0}, - {"Dirent.Type", Field, 0}, - {"Dirent.X__d_padding", Field, 3}, - {"DnsNameCompare", Func, 4}, - {"DnsQuery", Func, 0}, - {"DnsRecordListFree", Func, 0}, - {"DnsSectionAdditional", Const, 4}, - {"DnsSectionAnswer", Const, 4}, - {"DnsSectionAuthority", Const, 4}, - {"DnsSectionQuestion", Const, 4}, - {"Dup", Func, 0}, - {"Dup2", Func, 0}, - {"Dup3", Func, 2}, - {"DuplicateHandle", Func, 0}, - {"E2BIG", Const, 0}, - {"EACCES", Const, 0}, - {"EADDRINUSE", Const, 0}, - {"EADDRNOTAVAIL", Const, 0}, - {"EADV", Const, 0}, - {"EAFNOSUPPORT", Const, 0}, - {"EAGAIN", Const, 0}, - {"EALREADY", Const, 0}, - {"EAUTH", Const, 0}, - {"EBADARCH", Const, 0}, - {"EBADE", Const, 0}, - {"EBADEXEC", Const, 0}, - {"EBADF", Const, 0}, - {"EBADFD", Const, 0}, - {"EBADMACHO", Const, 0}, - {"EBADMSG", Const, 0}, - {"EBADR", Const, 0}, - {"EBADRPC", Const, 0}, - {"EBADRQC", Const, 0}, - {"EBADSLT", Const, 0}, - {"EBFONT", Const, 0}, - {"EBUSY", Const, 0}, - {"ECANCELED", Const, 0}, - {"ECAPMODE", Const, 1}, - {"ECHILD", Const, 0}, - {"ECHO", Const, 0}, - {"ECHOCTL", Const, 0}, - {"ECHOE", Const, 0}, - {"ECHOK", Const, 0}, - {"ECHOKE", Const, 0}, - {"ECHONL", Const, 0}, - {"ECHOPRT", Const, 0}, - {"ECHRNG", Const, 0}, - {"ECOMM", Const, 0}, - {"ECONNABORTED", Const, 0}, - {"ECONNREFUSED", Const, 0}, - {"ECONNRESET", Const, 0}, - {"EDEADLK", Const, 0}, - {"EDEADLOCK", Const, 0}, - {"EDESTADDRREQ", Const, 0}, - {"EDEVERR", Const, 0}, - {"EDOM", Const, 0}, - {"EDOOFUS", Const, 0}, - {"EDOTDOT", Const, 0}, - {"EDQUOT", Const, 0}, - {"EEXIST", Const, 0}, - {"EFAULT", Const, 0}, - {"EFBIG", Const, 0}, - {"EFER_LMA", Const, 1}, - {"EFER_LME", Const, 1}, - {"EFER_NXE", Const, 1}, - {"EFER_SCE", Const, 1}, - {"EFTYPE", Const, 0}, - {"EHOSTDOWN", Const, 0}, - {"EHOSTUNREACH", Const, 0}, - {"EHWPOISON", Const, 0}, - {"EIDRM", Const, 0}, - {"EILSEQ", Const, 0}, - {"EINPROGRESS", Const, 0}, - {"EINTR", Const, 0}, - {"EINVAL", Const, 0}, - {"EIO", Const, 0}, - {"EIPSEC", Const, 1}, - {"EISCONN", Const, 0}, - {"EISDIR", Const, 0}, - {"EISNAM", Const, 0}, - {"EKEYEXPIRED", Const, 0}, - {"EKEYREJECTED", Const, 0}, - {"EKEYREVOKED", Const, 0}, - {"EL2HLT", Const, 0}, - {"EL2NSYNC", Const, 0}, - {"EL3HLT", Const, 0}, - {"EL3RST", Const, 0}, - {"ELAST", Const, 0}, - {"ELF_NGREG", Const, 0}, - {"ELF_PRARGSZ", Const, 0}, - {"ELIBACC", Const, 0}, - {"ELIBBAD", Const, 0}, - {"ELIBEXEC", Const, 0}, - {"ELIBMAX", Const, 0}, - {"ELIBSCN", Const, 0}, - {"ELNRNG", Const, 0}, - {"ELOOP", Const, 0}, - {"EMEDIUMTYPE", Const, 0}, - {"EMFILE", Const, 0}, - {"EMLINK", Const, 0}, - {"EMSGSIZE", Const, 0}, - {"EMT_TAGOVF", Const, 1}, - {"EMULTIHOP", Const, 0}, - {"EMUL_ENABLED", Const, 1}, - {"EMUL_LINUX", Const, 1}, - {"EMUL_LINUX32", Const, 1}, - {"EMUL_MAXID", Const, 1}, - {"EMUL_NATIVE", Const, 1}, - {"ENAMETOOLONG", Const, 0}, - {"ENAVAIL", Const, 0}, - {"ENDRUNDISC", Const, 1}, - {"ENEEDAUTH", Const, 0}, - {"ENETDOWN", Const, 0}, - {"ENETRESET", Const, 0}, - {"ENETUNREACH", Const, 0}, - {"ENFILE", Const, 0}, - {"ENOANO", Const, 0}, - {"ENOATTR", Const, 0}, - {"ENOBUFS", Const, 0}, - {"ENOCSI", Const, 0}, - {"ENODATA", Const, 0}, - {"ENODEV", Const, 0}, - {"ENOENT", Const, 0}, - {"ENOEXEC", Const, 0}, - {"ENOKEY", Const, 0}, - {"ENOLCK", Const, 0}, - {"ENOLINK", Const, 0}, - {"ENOMEDIUM", Const, 0}, - {"ENOMEM", Const, 0}, - {"ENOMSG", Const, 0}, - {"ENONET", Const, 0}, - {"ENOPKG", Const, 0}, - {"ENOPOLICY", Const, 0}, - {"ENOPROTOOPT", Const, 0}, - {"ENOSPC", Const, 0}, - {"ENOSR", Const, 0}, - {"ENOSTR", Const, 0}, - {"ENOSYS", Const, 0}, - {"ENOTBLK", Const, 0}, - {"ENOTCAPABLE", Const, 0}, - {"ENOTCONN", Const, 0}, - {"ENOTDIR", Const, 0}, - {"ENOTEMPTY", Const, 0}, - {"ENOTNAM", Const, 0}, - {"ENOTRECOVERABLE", Const, 0}, - {"ENOTSOCK", Const, 0}, - {"ENOTSUP", Const, 0}, - {"ENOTTY", Const, 0}, - {"ENOTUNIQ", Const, 0}, - {"ENXIO", Const, 0}, - {"EN_SW_CTL_INF", Const, 1}, - {"EN_SW_CTL_PREC", Const, 1}, - {"EN_SW_CTL_ROUND", Const, 1}, - {"EN_SW_DATACHAIN", Const, 1}, - {"EN_SW_DENORM", Const, 1}, - {"EN_SW_INVOP", Const, 1}, - {"EN_SW_OVERFLOW", Const, 1}, - {"EN_SW_PRECLOSS", Const, 1}, - {"EN_SW_UNDERFLOW", Const, 1}, - {"EN_SW_ZERODIV", Const, 1}, - {"EOPNOTSUPP", Const, 0}, - {"EOVERFLOW", Const, 0}, - {"EOWNERDEAD", Const, 0}, - {"EPERM", Const, 0}, - {"EPFNOSUPPORT", Const, 0}, - {"EPIPE", Const, 0}, - {"EPOLLERR", Const, 0}, - {"EPOLLET", Const, 0}, - {"EPOLLHUP", Const, 0}, - {"EPOLLIN", Const, 0}, - {"EPOLLMSG", Const, 0}, - {"EPOLLONESHOT", Const, 0}, - {"EPOLLOUT", Const, 0}, - {"EPOLLPRI", Const, 0}, - {"EPOLLRDBAND", Const, 0}, - {"EPOLLRDHUP", Const, 0}, - {"EPOLLRDNORM", Const, 0}, - {"EPOLLWRBAND", Const, 0}, - {"EPOLLWRNORM", Const, 0}, - {"EPOLL_CLOEXEC", Const, 0}, - {"EPOLL_CTL_ADD", Const, 0}, - {"EPOLL_CTL_DEL", Const, 0}, - {"EPOLL_CTL_MOD", Const, 0}, - {"EPOLL_NONBLOCK", Const, 0}, - {"EPROCLIM", Const, 0}, - {"EPROCUNAVAIL", Const, 0}, - {"EPROGMISMATCH", Const, 0}, - {"EPROGUNAVAIL", Const, 0}, - {"EPROTO", Const, 0}, - {"EPROTONOSUPPORT", Const, 0}, - {"EPROTOTYPE", Const, 0}, - {"EPWROFF", Const, 0}, - {"EQFULL", Const, 16}, - {"ERANGE", Const, 0}, - {"EREMCHG", Const, 0}, - {"EREMOTE", Const, 0}, - {"EREMOTEIO", Const, 0}, - {"ERESTART", Const, 0}, - {"ERFKILL", Const, 0}, - {"EROFS", Const, 0}, - {"ERPCMISMATCH", Const, 0}, - {"ERROR_ACCESS_DENIED", Const, 0}, - {"ERROR_ALREADY_EXISTS", Const, 0}, - {"ERROR_BROKEN_PIPE", Const, 0}, - {"ERROR_BUFFER_OVERFLOW", Const, 0}, - {"ERROR_DIR_NOT_EMPTY", Const, 8}, - {"ERROR_ENVVAR_NOT_FOUND", Const, 0}, - {"ERROR_FILE_EXISTS", Const, 0}, - {"ERROR_FILE_NOT_FOUND", Const, 0}, - {"ERROR_HANDLE_EOF", Const, 2}, - {"ERROR_INSUFFICIENT_BUFFER", Const, 0}, - {"ERROR_IO_PENDING", Const, 0}, - {"ERROR_MOD_NOT_FOUND", Const, 0}, - {"ERROR_MORE_DATA", Const, 3}, - {"ERROR_NETNAME_DELETED", Const, 3}, - {"ERROR_NOT_FOUND", Const, 1}, - {"ERROR_NO_MORE_FILES", Const, 0}, - {"ERROR_OPERATION_ABORTED", Const, 0}, - {"ERROR_PATH_NOT_FOUND", Const, 0}, - {"ERROR_PRIVILEGE_NOT_HELD", Const, 4}, - {"ERROR_PROC_NOT_FOUND", Const, 0}, - {"ESHLIBVERS", Const, 0}, - {"ESHUTDOWN", Const, 0}, - {"ESOCKTNOSUPPORT", Const, 0}, - {"ESPIPE", Const, 0}, - {"ESRCH", Const, 0}, - {"ESRMNT", Const, 0}, - {"ESTALE", Const, 0}, - {"ESTRPIPE", Const, 0}, - {"ETHERCAP_JUMBO_MTU", Const, 1}, - {"ETHERCAP_VLAN_HWTAGGING", Const, 1}, - {"ETHERCAP_VLAN_MTU", Const, 1}, - {"ETHERMIN", Const, 1}, - {"ETHERMTU", Const, 1}, - {"ETHERMTU_JUMBO", Const, 1}, - {"ETHERTYPE_8023", Const, 1}, - {"ETHERTYPE_AARP", Const, 1}, - {"ETHERTYPE_ACCTON", Const, 1}, - {"ETHERTYPE_AEONIC", Const, 1}, - {"ETHERTYPE_ALPHA", Const, 1}, - {"ETHERTYPE_AMBER", Const, 1}, - {"ETHERTYPE_AMOEBA", Const, 1}, - {"ETHERTYPE_AOE", Const, 1}, - {"ETHERTYPE_APOLLO", Const, 1}, - {"ETHERTYPE_APOLLODOMAIN", Const, 1}, - {"ETHERTYPE_APPLETALK", Const, 1}, - {"ETHERTYPE_APPLITEK", Const, 1}, - {"ETHERTYPE_ARGONAUT", Const, 1}, - {"ETHERTYPE_ARP", Const, 1}, - {"ETHERTYPE_AT", Const, 1}, - {"ETHERTYPE_ATALK", Const, 1}, - {"ETHERTYPE_ATOMIC", Const, 1}, - {"ETHERTYPE_ATT", Const, 1}, - {"ETHERTYPE_ATTSTANFORD", Const, 1}, - {"ETHERTYPE_AUTOPHON", Const, 1}, - {"ETHERTYPE_AXIS", Const, 1}, - {"ETHERTYPE_BCLOOP", Const, 1}, - {"ETHERTYPE_BOFL", Const, 1}, - {"ETHERTYPE_CABLETRON", Const, 1}, - {"ETHERTYPE_CHAOS", Const, 1}, - {"ETHERTYPE_COMDESIGN", Const, 1}, - {"ETHERTYPE_COMPUGRAPHIC", Const, 1}, - {"ETHERTYPE_COUNTERPOINT", Const, 1}, - {"ETHERTYPE_CRONUS", Const, 1}, - {"ETHERTYPE_CRONUSVLN", Const, 1}, - {"ETHERTYPE_DCA", Const, 1}, - {"ETHERTYPE_DDE", Const, 1}, - {"ETHERTYPE_DEBNI", Const, 1}, - {"ETHERTYPE_DECAM", Const, 1}, - {"ETHERTYPE_DECCUST", Const, 1}, - {"ETHERTYPE_DECDIAG", Const, 1}, - {"ETHERTYPE_DECDNS", Const, 1}, - {"ETHERTYPE_DECDTS", Const, 1}, - {"ETHERTYPE_DECEXPER", Const, 1}, - {"ETHERTYPE_DECLAST", Const, 1}, - {"ETHERTYPE_DECLTM", Const, 1}, - {"ETHERTYPE_DECMUMPS", Const, 1}, - {"ETHERTYPE_DECNETBIOS", Const, 1}, - {"ETHERTYPE_DELTACON", Const, 1}, - {"ETHERTYPE_DIDDLE", Const, 1}, - {"ETHERTYPE_DLOG1", Const, 1}, - {"ETHERTYPE_DLOG2", Const, 1}, - {"ETHERTYPE_DN", Const, 1}, - {"ETHERTYPE_DOGFIGHT", Const, 1}, - {"ETHERTYPE_DSMD", Const, 1}, - {"ETHERTYPE_ECMA", Const, 1}, - {"ETHERTYPE_ENCRYPT", Const, 1}, - {"ETHERTYPE_ES", Const, 1}, - {"ETHERTYPE_EXCELAN", Const, 1}, - {"ETHERTYPE_EXPERDATA", Const, 1}, - {"ETHERTYPE_FLIP", Const, 1}, - {"ETHERTYPE_FLOWCONTROL", Const, 1}, - {"ETHERTYPE_FRARP", Const, 1}, - {"ETHERTYPE_GENDYN", Const, 1}, - {"ETHERTYPE_HAYES", Const, 1}, - {"ETHERTYPE_HIPPI_FP", Const, 1}, - {"ETHERTYPE_HITACHI", Const, 1}, - {"ETHERTYPE_HP", Const, 1}, - {"ETHERTYPE_IEEEPUP", Const, 1}, - {"ETHERTYPE_IEEEPUPAT", Const, 1}, - {"ETHERTYPE_IMLBL", Const, 1}, - {"ETHERTYPE_IMLBLDIAG", Const, 1}, - {"ETHERTYPE_IP", Const, 1}, - {"ETHERTYPE_IPAS", Const, 1}, - {"ETHERTYPE_IPV6", Const, 1}, - {"ETHERTYPE_IPX", Const, 1}, - {"ETHERTYPE_IPXNEW", Const, 1}, - {"ETHERTYPE_KALPANA", Const, 1}, - {"ETHERTYPE_LANBRIDGE", Const, 1}, - {"ETHERTYPE_LANPROBE", Const, 1}, - {"ETHERTYPE_LAT", Const, 1}, - {"ETHERTYPE_LBACK", Const, 1}, - {"ETHERTYPE_LITTLE", Const, 1}, - {"ETHERTYPE_LLDP", Const, 1}, - {"ETHERTYPE_LOGICRAFT", Const, 1}, - {"ETHERTYPE_LOOPBACK", Const, 1}, - {"ETHERTYPE_MATRA", Const, 1}, - {"ETHERTYPE_MAX", Const, 1}, - {"ETHERTYPE_MERIT", Const, 1}, - {"ETHERTYPE_MICP", Const, 1}, - {"ETHERTYPE_MOPDL", Const, 1}, - {"ETHERTYPE_MOPRC", Const, 1}, - {"ETHERTYPE_MOTOROLA", Const, 1}, - {"ETHERTYPE_MPLS", Const, 1}, - {"ETHERTYPE_MPLS_MCAST", Const, 1}, - {"ETHERTYPE_MUMPS", Const, 1}, - {"ETHERTYPE_NBPCC", Const, 1}, - {"ETHERTYPE_NBPCLAIM", Const, 1}, - {"ETHERTYPE_NBPCLREQ", Const, 1}, - {"ETHERTYPE_NBPCLRSP", Const, 1}, - {"ETHERTYPE_NBPCREQ", Const, 1}, - {"ETHERTYPE_NBPCRSP", Const, 1}, - {"ETHERTYPE_NBPDG", Const, 1}, - {"ETHERTYPE_NBPDGB", Const, 1}, - {"ETHERTYPE_NBPDLTE", Const, 1}, - {"ETHERTYPE_NBPRAR", Const, 1}, - {"ETHERTYPE_NBPRAS", Const, 1}, - {"ETHERTYPE_NBPRST", Const, 1}, - {"ETHERTYPE_NBPSCD", Const, 1}, - {"ETHERTYPE_NBPVCD", Const, 1}, - {"ETHERTYPE_NBS", Const, 1}, - {"ETHERTYPE_NCD", Const, 1}, - {"ETHERTYPE_NESTAR", Const, 1}, - {"ETHERTYPE_NETBEUI", Const, 1}, - {"ETHERTYPE_NOVELL", Const, 1}, - {"ETHERTYPE_NS", Const, 1}, - {"ETHERTYPE_NSAT", Const, 1}, - {"ETHERTYPE_NSCOMPAT", Const, 1}, - {"ETHERTYPE_NTRAILER", Const, 1}, - {"ETHERTYPE_OS9", Const, 1}, - {"ETHERTYPE_OS9NET", Const, 1}, - {"ETHERTYPE_PACER", Const, 1}, - {"ETHERTYPE_PAE", Const, 1}, - {"ETHERTYPE_PCS", Const, 1}, - {"ETHERTYPE_PLANNING", Const, 1}, - {"ETHERTYPE_PPP", Const, 1}, - {"ETHERTYPE_PPPOE", Const, 1}, - {"ETHERTYPE_PPPOEDISC", Const, 1}, - {"ETHERTYPE_PRIMENTS", Const, 1}, - {"ETHERTYPE_PUP", Const, 1}, - {"ETHERTYPE_PUPAT", Const, 1}, - {"ETHERTYPE_QINQ", Const, 1}, - {"ETHERTYPE_RACAL", Const, 1}, - {"ETHERTYPE_RATIONAL", Const, 1}, - {"ETHERTYPE_RAWFR", Const, 1}, - {"ETHERTYPE_RCL", Const, 1}, - {"ETHERTYPE_RDP", Const, 1}, - {"ETHERTYPE_RETIX", Const, 1}, - {"ETHERTYPE_REVARP", Const, 1}, - {"ETHERTYPE_SCA", Const, 1}, - {"ETHERTYPE_SECTRA", Const, 1}, - {"ETHERTYPE_SECUREDATA", Const, 1}, - {"ETHERTYPE_SGITW", Const, 1}, - {"ETHERTYPE_SG_BOUNCE", Const, 1}, - {"ETHERTYPE_SG_DIAG", Const, 1}, - {"ETHERTYPE_SG_NETGAMES", Const, 1}, - {"ETHERTYPE_SG_RESV", Const, 1}, - {"ETHERTYPE_SIMNET", Const, 1}, - {"ETHERTYPE_SLOW", Const, 1}, - {"ETHERTYPE_SLOWPROTOCOLS", Const, 1}, - {"ETHERTYPE_SNA", Const, 1}, - {"ETHERTYPE_SNMP", Const, 1}, - {"ETHERTYPE_SONIX", Const, 1}, - {"ETHERTYPE_SPIDER", Const, 1}, - {"ETHERTYPE_SPRITE", Const, 1}, - {"ETHERTYPE_STP", Const, 1}, - {"ETHERTYPE_TALARIS", Const, 1}, - {"ETHERTYPE_TALARISMC", Const, 1}, - {"ETHERTYPE_TCPCOMP", Const, 1}, - {"ETHERTYPE_TCPSM", Const, 1}, - {"ETHERTYPE_TEC", Const, 1}, - {"ETHERTYPE_TIGAN", Const, 1}, - {"ETHERTYPE_TRAIL", Const, 1}, - {"ETHERTYPE_TRANSETHER", Const, 1}, - {"ETHERTYPE_TYMSHARE", Const, 1}, - {"ETHERTYPE_UBBST", Const, 1}, - {"ETHERTYPE_UBDEBUG", Const, 1}, - {"ETHERTYPE_UBDIAGLOOP", Const, 1}, - {"ETHERTYPE_UBDL", Const, 1}, - {"ETHERTYPE_UBNIU", Const, 1}, - {"ETHERTYPE_UBNMC", Const, 1}, - {"ETHERTYPE_VALID", Const, 1}, - {"ETHERTYPE_VARIAN", Const, 1}, - {"ETHERTYPE_VAXELN", Const, 1}, - {"ETHERTYPE_VEECO", Const, 1}, - {"ETHERTYPE_VEXP", Const, 1}, - {"ETHERTYPE_VGLAB", Const, 1}, - {"ETHERTYPE_VINES", Const, 1}, - {"ETHERTYPE_VINESECHO", Const, 1}, - {"ETHERTYPE_VINESLOOP", Const, 1}, - {"ETHERTYPE_VITAL", Const, 1}, - {"ETHERTYPE_VLAN", Const, 1}, - {"ETHERTYPE_VLTLMAN", Const, 1}, - {"ETHERTYPE_VPROD", Const, 1}, - {"ETHERTYPE_VURESERVED", Const, 1}, - {"ETHERTYPE_WATERLOO", Const, 1}, - {"ETHERTYPE_WELLFLEET", Const, 1}, - {"ETHERTYPE_X25", Const, 1}, - {"ETHERTYPE_X75", Const, 1}, - {"ETHERTYPE_XNSSM", Const, 1}, - {"ETHERTYPE_XTP", Const, 1}, - {"ETHER_ADDR_LEN", Const, 1}, - {"ETHER_ALIGN", Const, 1}, - {"ETHER_CRC_LEN", Const, 1}, - {"ETHER_CRC_POLY_BE", Const, 1}, - {"ETHER_CRC_POLY_LE", Const, 1}, - {"ETHER_HDR_LEN", Const, 1}, - {"ETHER_MAX_DIX_LEN", Const, 1}, - {"ETHER_MAX_LEN", Const, 1}, - {"ETHER_MAX_LEN_JUMBO", Const, 1}, - {"ETHER_MIN_LEN", Const, 1}, - {"ETHER_PPPOE_ENCAP_LEN", Const, 1}, - {"ETHER_TYPE_LEN", Const, 1}, - {"ETHER_VLAN_ENCAP_LEN", Const, 1}, - {"ETH_P_1588", Const, 0}, - {"ETH_P_8021Q", Const, 0}, - {"ETH_P_802_2", Const, 0}, - {"ETH_P_802_3", Const, 0}, - {"ETH_P_AARP", Const, 0}, - {"ETH_P_ALL", Const, 0}, - {"ETH_P_AOE", Const, 0}, - {"ETH_P_ARCNET", Const, 0}, - {"ETH_P_ARP", Const, 0}, - {"ETH_P_ATALK", Const, 0}, - {"ETH_P_ATMFATE", Const, 0}, - {"ETH_P_ATMMPOA", Const, 0}, - {"ETH_P_AX25", Const, 0}, - {"ETH_P_BPQ", Const, 0}, - {"ETH_P_CAIF", Const, 0}, - {"ETH_P_CAN", Const, 0}, - {"ETH_P_CONTROL", Const, 0}, - {"ETH_P_CUST", Const, 0}, - {"ETH_P_DDCMP", Const, 0}, - {"ETH_P_DEC", Const, 0}, - {"ETH_P_DIAG", Const, 0}, - {"ETH_P_DNA_DL", Const, 0}, - {"ETH_P_DNA_RC", Const, 0}, - {"ETH_P_DNA_RT", Const, 0}, - {"ETH_P_DSA", Const, 0}, - {"ETH_P_ECONET", Const, 0}, - {"ETH_P_EDSA", Const, 0}, - {"ETH_P_FCOE", Const, 0}, - {"ETH_P_FIP", Const, 0}, - {"ETH_P_HDLC", Const, 0}, - {"ETH_P_IEEE802154", Const, 0}, - {"ETH_P_IEEEPUP", Const, 0}, - {"ETH_P_IEEEPUPAT", Const, 0}, - {"ETH_P_IP", Const, 0}, - {"ETH_P_IPV6", Const, 0}, - {"ETH_P_IPX", Const, 0}, - {"ETH_P_IRDA", Const, 0}, - {"ETH_P_LAT", Const, 0}, - {"ETH_P_LINK_CTL", Const, 0}, - {"ETH_P_LOCALTALK", Const, 0}, - {"ETH_P_LOOP", Const, 0}, - {"ETH_P_MOBITEX", Const, 0}, - {"ETH_P_MPLS_MC", Const, 0}, - {"ETH_P_MPLS_UC", Const, 0}, - {"ETH_P_PAE", Const, 0}, - {"ETH_P_PAUSE", Const, 0}, - {"ETH_P_PHONET", Const, 0}, - {"ETH_P_PPPTALK", Const, 0}, - {"ETH_P_PPP_DISC", Const, 0}, - {"ETH_P_PPP_MP", Const, 0}, - {"ETH_P_PPP_SES", Const, 0}, - {"ETH_P_PUP", Const, 0}, - {"ETH_P_PUPAT", Const, 0}, - {"ETH_P_RARP", Const, 0}, - {"ETH_P_SCA", Const, 0}, - {"ETH_P_SLOW", Const, 0}, - {"ETH_P_SNAP", Const, 0}, - {"ETH_P_TEB", Const, 0}, - {"ETH_P_TIPC", Const, 0}, - {"ETH_P_TRAILER", Const, 0}, - {"ETH_P_TR_802_2", Const, 0}, - {"ETH_P_WAN_PPP", Const, 0}, - {"ETH_P_WCCP", Const, 0}, - {"ETH_P_X25", Const, 0}, - {"ETIME", Const, 0}, - {"ETIMEDOUT", Const, 0}, - {"ETOOMANYREFS", Const, 0}, - {"ETXTBSY", Const, 0}, - {"EUCLEAN", Const, 0}, - {"EUNATCH", Const, 0}, - {"EUSERS", Const, 0}, - {"EVFILT_AIO", Const, 0}, - {"EVFILT_FS", Const, 0}, - {"EVFILT_LIO", Const, 0}, - {"EVFILT_MACHPORT", Const, 0}, - {"EVFILT_PROC", Const, 0}, - {"EVFILT_READ", Const, 0}, - {"EVFILT_SIGNAL", Const, 0}, - {"EVFILT_SYSCOUNT", Const, 0}, - {"EVFILT_THREADMARKER", Const, 0}, - {"EVFILT_TIMER", Const, 0}, - {"EVFILT_USER", Const, 0}, - {"EVFILT_VM", Const, 0}, - {"EVFILT_VNODE", Const, 0}, - {"EVFILT_WRITE", Const, 0}, - {"EV_ADD", Const, 0}, - {"EV_CLEAR", Const, 0}, - {"EV_DELETE", Const, 0}, - {"EV_DISABLE", Const, 0}, - {"EV_DISPATCH", Const, 0}, - {"EV_DROP", Const, 3}, - {"EV_ENABLE", Const, 0}, - {"EV_EOF", Const, 0}, - {"EV_ERROR", Const, 0}, - {"EV_FLAG0", Const, 0}, - {"EV_FLAG1", Const, 0}, - {"EV_ONESHOT", Const, 0}, - {"EV_OOBAND", Const, 0}, - {"EV_POLL", Const, 0}, - {"EV_RECEIPT", Const, 0}, - {"EV_SYSFLAGS", Const, 0}, - {"EWINDOWS", Const, 0}, - {"EWOULDBLOCK", Const, 0}, - {"EXDEV", Const, 0}, - {"EXFULL", Const, 0}, - {"EXTA", Const, 0}, - {"EXTB", Const, 0}, - {"EXTPROC", Const, 0}, - {"Environ", Func, 0}, - {"EpollCreate", Func, 0}, - {"EpollCreate1", Func, 0}, - {"EpollCtl", Func, 0}, - {"EpollEvent", Type, 0}, - {"EpollEvent.Events", Field, 0}, - {"EpollEvent.Fd", Field, 0}, - {"EpollEvent.Pad", Field, 0}, - {"EpollEvent.PadFd", Field, 0}, - {"EpollWait", Func, 0}, - {"Errno", Type, 0}, - {"EscapeArg", Func, 0}, - {"Exchangedata", Func, 0}, - {"Exec", Func, 0}, - {"Exit", Func, 0}, - {"ExitProcess", Func, 0}, - {"FD_CLOEXEC", Const, 0}, - {"FD_SETSIZE", Const, 0}, - {"FILE_ACTION_ADDED", Const, 0}, - {"FILE_ACTION_MODIFIED", Const, 0}, - {"FILE_ACTION_REMOVED", Const, 0}, - {"FILE_ACTION_RENAMED_NEW_NAME", Const, 0}, - {"FILE_ACTION_RENAMED_OLD_NAME", Const, 0}, - {"FILE_APPEND_DATA", Const, 0}, - {"FILE_ATTRIBUTE_ARCHIVE", Const, 0}, - {"FILE_ATTRIBUTE_DIRECTORY", Const, 0}, - {"FILE_ATTRIBUTE_HIDDEN", Const, 0}, - {"FILE_ATTRIBUTE_NORMAL", Const, 0}, - {"FILE_ATTRIBUTE_READONLY", Const, 0}, - {"FILE_ATTRIBUTE_REPARSE_POINT", Const, 4}, - {"FILE_ATTRIBUTE_SYSTEM", Const, 0}, - {"FILE_BEGIN", Const, 0}, - {"FILE_CURRENT", Const, 0}, - {"FILE_END", Const, 0}, - {"FILE_FLAG_BACKUP_SEMANTICS", Const, 0}, - {"FILE_FLAG_OPEN_REPARSE_POINT", Const, 4}, - {"FILE_FLAG_OVERLAPPED", Const, 0}, - {"FILE_LIST_DIRECTORY", Const, 0}, - {"FILE_MAP_COPY", Const, 0}, - {"FILE_MAP_EXECUTE", Const, 0}, - {"FILE_MAP_READ", Const, 0}, - {"FILE_MAP_WRITE", Const, 0}, - {"FILE_NOTIFY_CHANGE_ATTRIBUTES", Const, 0}, - {"FILE_NOTIFY_CHANGE_CREATION", Const, 0}, - {"FILE_NOTIFY_CHANGE_DIR_NAME", Const, 0}, - {"FILE_NOTIFY_CHANGE_FILE_NAME", Const, 0}, - {"FILE_NOTIFY_CHANGE_LAST_ACCESS", Const, 0}, - {"FILE_NOTIFY_CHANGE_LAST_WRITE", Const, 0}, - {"FILE_NOTIFY_CHANGE_SIZE", Const, 0}, - {"FILE_SHARE_DELETE", Const, 0}, - {"FILE_SHARE_READ", Const, 0}, - {"FILE_SHARE_WRITE", Const, 0}, - {"FILE_SKIP_COMPLETION_PORT_ON_SUCCESS", Const, 2}, - {"FILE_SKIP_SET_EVENT_ON_HANDLE", Const, 2}, - {"FILE_TYPE_CHAR", Const, 0}, - {"FILE_TYPE_DISK", Const, 0}, - {"FILE_TYPE_PIPE", Const, 0}, - {"FILE_TYPE_REMOTE", Const, 0}, - {"FILE_TYPE_UNKNOWN", Const, 0}, - {"FILE_WRITE_ATTRIBUTES", Const, 0}, - {"FLUSHO", Const, 0}, - {"FORMAT_MESSAGE_ALLOCATE_BUFFER", Const, 0}, - {"FORMAT_MESSAGE_ARGUMENT_ARRAY", Const, 0}, - {"FORMAT_MESSAGE_FROM_HMODULE", Const, 0}, - {"FORMAT_MESSAGE_FROM_STRING", Const, 0}, - {"FORMAT_MESSAGE_FROM_SYSTEM", Const, 0}, - {"FORMAT_MESSAGE_IGNORE_INSERTS", Const, 0}, - {"FORMAT_MESSAGE_MAX_WIDTH_MASK", Const, 0}, - {"FSCTL_GET_REPARSE_POINT", Const, 4}, - {"F_ADDFILESIGS", Const, 0}, - {"F_ADDSIGS", Const, 0}, - {"F_ALLOCATEALL", Const, 0}, - {"F_ALLOCATECONTIG", Const, 0}, - {"F_CANCEL", Const, 0}, - {"F_CHKCLEAN", Const, 0}, - {"F_CLOSEM", Const, 1}, - {"F_DUP2FD", Const, 0}, - {"F_DUP2FD_CLOEXEC", Const, 1}, - {"F_DUPFD", Const, 0}, - {"F_DUPFD_CLOEXEC", Const, 0}, - {"F_EXLCK", Const, 0}, - {"F_FINDSIGS", Const, 16}, - {"F_FLUSH_DATA", Const, 0}, - {"F_FREEZE_FS", Const, 0}, - {"F_FSCTL", Const, 1}, - {"F_FSDIRMASK", Const, 1}, - {"F_FSIN", Const, 1}, - {"F_FSINOUT", Const, 1}, - {"F_FSOUT", Const, 1}, - {"F_FSPRIV", Const, 1}, - {"F_FSVOID", Const, 1}, - {"F_FULLFSYNC", Const, 0}, - {"F_GETCODEDIR", Const, 16}, - {"F_GETFD", Const, 0}, - {"F_GETFL", Const, 0}, - {"F_GETLEASE", Const, 0}, - {"F_GETLK", Const, 0}, - {"F_GETLK64", Const, 0}, - {"F_GETLKPID", Const, 0}, - {"F_GETNOSIGPIPE", Const, 0}, - {"F_GETOWN", Const, 0}, - {"F_GETOWN_EX", Const, 0}, - {"F_GETPATH", Const, 0}, - {"F_GETPATH_MTMINFO", Const, 0}, - {"F_GETPIPE_SZ", Const, 0}, - {"F_GETPROTECTIONCLASS", Const, 0}, - {"F_GETPROTECTIONLEVEL", Const, 16}, - {"F_GETSIG", Const, 0}, - {"F_GLOBAL_NOCACHE", Const, 0}, - {"F_LOCK", Const, 0}, - {"F_LOG2PHYS", Const, 0}, - {"F_LOG2PHYS_EXT", Const, 0}, - {"F_MARKDEPENDENCY", Const, 0}, - {"F_MAXFD", Const, 1}, - {"F_NOCACHE", Const, 0}, - {"F_NODIRECT", Const, 0}, - {"F_NOTIFY", Const, 0}, - {"F_OGETLK", Const, 0}, - {"F_OK", Const, 0}, - {"F_OSETLK", Const, 0}, - {"F_OSETLKW", Const, 0}, - {"F_PARAM_MASK", Const, 1}, - {"F_PARAM_MAX", Const, 1}, - {"F_PATHPKG_CHECK", Const, 0}, - {"F_PEOFPOSMODE", Const, 0}, - {"F_PREALLOCATE", Const, 0}, - {"F_RDADVISE", Const, 0}, - {"F_RDAHEAD", Const, 0}, - {"F_RDLCK", Const, 0}, - {"F_READAHEAD", Const, 0}, - {"F_READBOOTSTRAP", Const, 0}, - {"F_SETBACKINGSTORE", Const, 0}, - {"F_SETFD", Const, 0}, - {"F_SETFL", Const, 0}, - {"F_SETLEASE", Const, 0}, - {"F_SETLK", Const, 0}, - {"F_SETLK64", Const, 0}, - {"F_SETLKW", Const, 0}, - {"F_SETLKW64", Const, 0}, - {"F_SETLKWTIMEOUT", Const, 16}, - {"F_SETLK_REMOTE", Const, 0}, - {"F_SETNOSIGPIPE", Const, 0}, - {"F_SETOWN", Const, 0}, - {"F_SETOWN_EX", Const, 0}, - {"F_SETPIPE_SZ", Const, 0}, - {"F_SETPROTECTIONCLASS", Const, 0}, - {"F_SETSIG", Const, 0}, - {"F_SETSIZE", Const, 0}, - {"F_SHLCK", Const, 0}, - {"F_SINGLE_WRITER", Const, 16}, - {"F_TEST", Const, 0}, - {"F_THAW_FS", Const, 0}, - {"F_TLOCK", Const, 0}, - {"F_TRANSCODEKEY", Const, 16}, - {"F_ULOCK", Const, 0}, - {"F_UNLCK", Const, 0}, - {"F_UNLCKSYS", Const, 0}, - {"F_VOLPOSMODE", Const, 0}, - {"F_WRITEBOOTSTRAP", Const, 0}, - {"F_WRLCK", Const, 0}, - {"Faccessat", Func, 0}, - {"Fallocate", Func, 0}, - {"Fbootstraptransfer_t", Type, 0}, - {"Fbootstraptransfer_t.Buffer", Field, 0}, - {"Fbootstraptransfer_t.Length", Field, 0}, - {"Fbootstraptransfer_t.Offset", Field, 0}, - {"Fchdir", Func, 0}, - {"Fchflags", Func, 0}, - {"Fchmod", Func, 0}, - {"Fchmodat", Func, 0}, - {"Fchown", Func, 0}, - {"Fchownat", Func, 0}, - {"FcntlFlock", Func, 3}, - {"FdSet", Type, 0}, - {"FdSet.Bits", Field, 0}, - {"FdSet.X__fds_bits", Field, 0}, - {"Fdatasync", Func, 0}, - {"FileNotifyInformation", Type, 0}, - {"FileNotifyInformation.Action", Field, 0}, - {"FileNotifyInformation.FileName", Field, 0}, - {"FileNotifyInformation.FileNameLength", Field, 0}, - {"FileNotifyInformation.NextEntryOffset", Field, 0}, - {"Filetime", Type, 0}, - {"Filetime.HighDateTime", Field, 0}, - {"Filetime.LowDateTime", Field, 0}, - {"FindClose", Func, 0}, - {"FindFirstFile", Func, 0}, - {"FindNextFile", Func, 0}, - {"Flock", Func, 0}, - {"Flock_t", Type, 0}, - {"Flock_t.Len", Field, 0}, - {"Flock_t.Pad_cgo_0", Field, 0}, - {"Flock_t.Pad_cgo_1", Field, 3}, - {"Flock_t.Pid", Field, 0}, - {"Flock_t.Start", Field, 0}, - {"Flock_t.Sysid", Field, 0}, - {"Flock_t.Type", Field, 0}, - {"Flock_t.Whence", Field, 0}, - {"FlushBpf", Func, 0}, - {"FlushFileBuffers", Func, 0}, - {"FlushViewOfFile", Func, 0}, - {"ForkExec", Func, 0}, - {"ForkLock", Var, 0}, - {"FormatMessage", Func, 0}, - {"Fpathconf", Func, 0}, - {"FreeAddrInfoW", Func, 1}, - {"FreeEnvironmentStrings", Func, 0}, - {"FreeLibrary", Func, 0}, - {"Fsid", Type, 0}, - {"Fsid.Val", Field, 0}, - {"Fsid.X__fsid_val", Field, 2}, - {"Fsid.X__val", Field, 0}, - {"Fstat", Func, 0}, - {"Fstatat", Func, 12}, - {"Fstatfs", Func, 0}, - {"Fstore_t", Type, 0}, - {"Fstore_t.Bytesalloc", Field, 0}, - {"Fstore_t.Flags", Field, 0}, - {"Fstore_t.Length", Field, 0}, - {"Fstore_t.Offset", Field, 0}, - {"Fstore_t.Posmode", Field, 0}, - {"Fsync", Func, 0}, - {"Ftruncate", Func, 0}, - {"FullPath", Func, 4}, - {"Futimes", Func, 0}, - {"Futimesat", Func, 0}, - {"GENERIC_ALL", Const, 0}, - {"GENERIC_EXECUTE", Const, 0}, - {"GENERIC_READ", Const, 0}, - {"GENERIC_WRITE", Const, 0}, - {"GUID", Type, 1}, - {"GUID.Data1", Field, 1}, - {"GUID.Data2", Field, 1}, - {"GUID.Data3", Field, 1}, - {"GUID.Data4", Field, 1}, - {"GetAcceptExSockaddrs", Func, 0}, - {"GetAdaptersInfo", Func, 0}, - {"GetAddrInfoW", Func, 1}, - {"GetCommandLine", Func, 0}, - {"GetComputerName", Func, 0}, - {"GetConsoleMode", Func, 1}, - {"GetCurrentDirectory", Func, 0}, - {"GetCurrentProcess", Func, 0}, - {"GetEnvironmentStrings", Func, 0}, - {"GetEnvironmentVariable", Func, 0}, - {"GetExitCodeProcess", Func, 0}, - {"GetFileAttributes", Func, 0}, - {"GetFileAttributesEx", Func, 0}, - {"GetFileExInfoStandard", Const, 0}, - {"GetFileExMaxInfoLevel", Const, 0}, - {"GetFileInformationByHandle", Func, 0}, - {"GetFileType", Func, 0}, - {"GetFullPathName", Func, 0}, - {"GetHostByName", Func, 0}, - {"GetIfEntry", Func, 0}, - {"GetLastError", Func, 0}, - {"GetLengthSid", Func, 0}, - {"GetLongPathName", Func, 0}, - {"GetProcAddress", Func, 0}, - {"GetProcessTimes", Func, 0}, - {"GetProtoByName", Func, 0}, - {"GetQueuedCompletionStatus", Func, 0}, - {"GetServByName", Func, 0}, - {"GetShortPathName", Func, 0}, - {"GetStartupInfo", Func, 0}, - {"GetStdHandle", Func, 0}, - {"GetSystemTimeAsFileTime", Func, 0}, - {"GetTempPath", Func, 0}, - {"GetTimeZoneInformation", Func, 0}, - {"GetTokenInformation", Func, 0}, - {"GetUserNameEx", Func, 0}, - {"GetUserProfileDirectory", Func, 0}, - {"GetVersion", Func, 0}, - {"Getcwd", Func, 0}, - {"Getdents", Func, 0}, - {"Getdirentries", Func, 0}, - {"Getdtablesize", Func, 0}, - {"Getegid", Func, 0}, - {"Getenv", Func, 0}, - {"Geteuid", Func, 0}, - {"Getfsstat", Func, 0}, - {"Getgid", Func, 0}, - {"Getgroups", Func, 0}, - {"Getpagesize", Func, 0}, - {"Getpeername", Func, 0}, - {"Getpgid", Func, 0}, - {"Getpgrp", Func, 0}, - {"Getpid", Func, 0}, - {"Getppid", Func, 0}, - {"Getpriority", Func, 0}, - {"Getrlimit", Func, 0}, - {"Getrusage", Func, 0}, - {"Getsid", Func, 0}, - {"Getsockname", Func, 0}, - {"Getsockopt", Func, 1}, - {"GetsockoptByte", Func, 0}, - {"GetsockoptICMPv6Filter", Func, 2}, - {"GetsockoptIPMreq", Func, 0}, - {"GetsockoptIPMreqn", Func, 0}, - {"GetsockoptIPv6MTUInfo", Func, 2}, - {"GetsockoptIPv6Mreq", Func, 0}, - {"GetsockoptInet4Addr", Func, 0}, - {"GetsockoptInt", Func, 0}, - {"GetsockoptUcred", Func, 1}, - {"Gettid", Func, 0}, - {"Gettimeofday", Func, 0}, - {"Getuid", Func, 0}, - {"Getwd", Func, 0}, - {"Getxattr", Func, 1}, - {"HANDLE_FLAG_INHERIT", Const, 0}, - {"HKEY_CLASSES_ROOT", Const, 0}, - {"HKEY_CURRENT_CONFIG", Const, 0}, - {"HKEY_CURRENT_USER", Const, 0}, - {"HKEY_DYN_DATA", Const, 0}, - {"HKEY_LOCAL_MACHINE", Const, 0}, - {"HKEY_PERFORMANCE_DATA", Const, 0}, - {"HKEY_USERS", Const, 0}, - {"HUPCL", Const, 0}, - {"Handle", Type, 0}, - {"Hostent", Type, 0}, - {"Hostent.AddrList", Field, 0}, - {"Hostent.AddrType", Field, 0}, - {"Hostent.Aliases", Field, 0}, - {"Hostent.Length", Field, 0}, - {"Hostent.Name", Field, 0}, - {"ICANON", Const, 0}, - {"ICMP6_FILTER", Const, 2}, - {"ICMPV6_FILTER", Const, 2}, - {"ICMPv6Filter", Type, 2}, - {"ICMPv6Filter.Data", Field, 2}, - {"ICMPv6Filter.Filt", Field, 2}, - {"ICRNL", Const, 0}, - {"IEXTEN", Const, 0}, - {"IFAN_ARRIVAL", Const, 1}, - {"IFAN_DEPARTURE", Const, 1}, - {"IFA_ADDRESS", Const, 0}, - {"IFA_ANYCAST", Const, 0}, - {"IFA_BROADCAST", Const, 0}, - {"IFA_CACHEINFO", Const, 0}, - {"IFA_F_DADFAILED", Const, 0}, - {"IFA_F_DEPRECATED", Const, 0}, - {"IFA_F_HOMEADDRESS", Const, 0}, - {"IFA_F_NODAD", Const, 0}, - {"IFA_F_OPTIMISTIC", Const, 0}, - {"IFA_F_PERMANENT", Const, 0}, - {"IFA_F_SECONDARY", Const, 0}, - {"IFA_F_TEMPORARY", Const, 0}, - {"IFA_F_TENTATIVE", Const, 0}, - {"IFA_LABEL", Const, 0}, - {"IFA_LOCAL", Const, 0}, - {"IFA_MAX", Const, 0}, - {"IFA_MULTICAST", Const, 0}, - {"IFA_ROUTE", Const, 1}, - {"IFA_UNSPEC", Const, 0}, - {"IFF_ALLMULTI", Const, 0}, - {"IFF_ALTPHYS", Const, 0}, - {"IFF_AUTOMEDIA", Const, 0}, - {"IFF_BROADCAST", Const, 0}, - {"IFF_CANTCHANGE", Const, 0}, - {"IFF_CANTCONFIG", Const, 1}, - {"IFF_DEBUG", Const, 0}, - {"IFF_DRV_OACTIVE", Const, 0}, - {"IFF_DRV_RUNNING", Const, 0}, - {"IFF_DYING", Const, 0}, - {"IFF_DYNAMIC", Const, 0}, - {"IFF_LINK0", Const, 0}, - {"IFF_LINK1", Const, 0}, - {"IFF_LINK2", Const, 0}, - {"IFF_LOOPBACK", Const, 0}, - {"IFF_MASTER", Const, 0}, - {"IFF_MONITOR", Const, 0}, - {"IFF_MULTICAST", Const, 0}, - {"IFF_NOARP", Const, 0}, - {"IFF_NOTRAILERS", Const, 0}, - {"IFF_NO_PI", Const, 0}, - {"IFF_OACTIVE", Const, 0}, - {"IFF_ONE_QUEUE", Const, 0}, - {"IFF_POINTOPOINT", Const, 0}, - {"IFF_POINTTOPOINT", Const, 0}, - {"IFF_PORTSEL", Const, 0}, - {"IFF_PPROMISC", Const, 0}, - {"IFF_PROMISC", Const, 0}, - {"IFF_RENAMING", Const, 0}, - {"IFF_RUNNING", Const, 0}, - {"IFF_SIMPLEX", Const, 0}, - {"IFF_SLAVE", Const, 0}, - {"IFF_SMART", Const, 0}, - {"IFF_STATICARP", Const, 0}, - {"IFF_TAP", Const, 0}, - {"IFF_TUN", Const, 0}, - {"IFF_TUN_EXCL", Const, 0}, - {"IFF_UP", Const, 0}, - {"IFF_VNET_HDR", Const, 0}, - {"IFLA_ADDRESS", Const, 0}, - {"IFLA_BROADCAST", Const, 0}, - {"IFLA_COST", Const, 0}, - {"IFLA_IFALIAS", Const, 0}, - {"IFLA_IFNAME", Const, 0}, - {"IFLA_LINK", Const, 0}, - {"IFLA_LINKINFO", Const, 0}, - {"IFLA_LINKMODE", Const, 0}, - {"IFLA_MAP", Const, 0}, - {"IFLA_MASTER", Const, 0}, - {"IFLA_MAX", Const, 0}, - {"IFLA_MTU", Const, 0}, - {"IFLA_NET_NS_PID", Const, 0}, - {"IFLA_OPERSTATE", Const, 0}, - {"IFLA_PRIORITY", Const, 0}, - {"IFLA_PROTINFO", Const, 0}, - {"IFLA_QDISC", Const, 0}, - {"IFLA_STATS", Const, 0}, - {"IFLA_TXQLEN", Const, 0}, - {"IFLA_UNSPEC", Const, 0}, - {"IFLA_WEIGHT", Const, 0}, - {"IFLA_WIRELESS", Const, 0}, - {"IFNAMSIZ", Const, 0}, - {"IFT_1822", Const, 0}, - {"IFT_A12MPPSWITCH", Const, 0}, - {"IFT_AAL2", Const, 0}, - {"IFT_AAL5", Const, 0}, - {"IFT_ADSL", Const, 0}, - {"IFT_AFLANE8023", Const, 0}, - {"IFT_AFLANE8025", Const, 0}, - {"IFT_ARAP", Const, 0}, - {"IFT_ARCNET", Const, 0}, - {"IFT_ARCNETPLUS", Const, 0}, - {"IFT_ASYNC", Const, 0}, - {"IFT_ATM", Const, 0}, - {"IFT_ATMDXI", Const, 0}, - {"IFT_ATMFUNI", Const, 0}, - {"IFT_ATMIMA", Const, 0}, - {"IFT_ATMLOGICAL", Const, 0}, - {"IFT_ATMRADIO", Const, 0}, - {"IFT_ATMSUBINTERFACE", Const, 0}, - {"IFT_ATMVCIENDPT", Const, 0}, - {"IFT_ATMVIRTUAL", Const, 0}, - {"IFT_BGPPOLICYACCOUNTING", Const, 0}, - {"IFT_BLUETOOTH", Const, 1}, - {"IFT_BRIDGE", Const, 0}, - {"IFT_BSC", Const, 0}, - {"IFT_CARP", Const, 0}, - {"IFT_CCTEMUL", Const, 0}, - {"IFT_CELLULAR", Const, 0}, - {"IFT_CEPT", Const, 0}, - {"IFT_CES", Const, 0}, - {"IFT_CHANNEL", Const, 0}, - {"IFT_CNR", Const, 0}, - {"IFT_COFFEE", Const, 0}, - {"IFT_COMPOSITELINK", Const, 0}, - {"IFT_DCN", Const, 0}, - {"IFT_DIGITALPOWERLINE", Const, 0}, - {"IFT_DIGITALWRAPPEROVERHEADCHANNEL", Const, 0}, - {"IFT_DLSW", Const, 0}, - {"IFT_DOCSCABLEDOWNSTREAM", Const, 0}, - {"IFT_DOCSCABLEMACLAYER", Const, 0}, - {"IFT_DOCSCABLEUPSTREAM", Const, 0}, - {"IFT_DOCSCABLEUPSTREAMCHANNEL", Const, 1}, - {"IFT_DS0", Const, 0}, - {"IFT_DS0BUNDLE", Const, 0}, - {"IFT_DS1FDL", Const, 0}, - {"IFT_DS3", Const, 0}, - {"IFT_DTM", Const, 0}, - {"IFT_DUMMY", Const, 1}, - {"IFT_DVBASILN", Const, 0}, - {"IFT_DVBASIOUT", Const, 0}, - {"IFT_DVBRCCDOWNSTREAM", Const, 0}, - {"IFT_DVBRCCMACLAYER", Const, 0}, - {"IFT_DVBRCCUPSTREAM", Const, 0}, - {"IFT_ECONET", Const, 1}, - {"IFT_ENC", Const, 0}, - {"IFT_EON", Const, 0}, - {"IFT_EPLRS", Const, 0}, - {"IFT_ESCON", Const, 0}, - {"IFT_ETHER", Const, 0}, - {"IFT_FAITH", Const, 0}, - {"IFT_FAST", Const, 0}, - {"IFT_FASTETHER", Const, 0}, - {"IFT_FASTETHERFX", Const, 0}, - {"IFT_FDDI", Const, 0}, - {"IFT_FIBRECHANNEL", Const, 0}, - {"IFT_FRAMERELAYINTERCONNECT", Const, 0}, - {"IFT_FRAMERELAYMPI", Const, 0}, - {"IFT_FRDLCIENDPT", Const, 0}, - {"IFT_FRELAY", Const, 0}, - {"IFT_FRELAYDCE", Const, 0}, - {"IFT_FRF16MFRBUNDLE", Const, 0}, - {"IFT_FRFORWARD", Const, 0}, - {"IFT_G703AT2MB", Const, 0}, - {"IFT_G703AT64K", Const, 0}, - {"IFT_GIF", Const, 0}, - {"IFT_GIGABITETHERNET", Const, 0}, - {"IFT_GR303IDT", Const, 0}, - {"IFT_GR303RDT", Const, 0}, - {"IFT_H323GATEKEEPER", Const, 0}, - {"IFT_H323PROXY", Const, 0}, - {"IFT_HDH1822", Const, 0}, - {"IFT_HDLC", Const, 0}, - {"IFT_HDSL2", Const, 0}, - {"IFT_HIPERLAN2", Const, 0}, - {"IFT_HIPPI", Const, 0}, - {"IFT_HIPPIINTERFACE", Const, 0}, - {"IFT_HOSTPAD", Const, 0}, - {"IFT_HSSI", Const, 0}, - {"IFT_HY", Const, 0}, - {"IFT_IBM370PARCHAN", Const, 0}, - {"IFT_IDSL", Const, 0}, - {"IFT_IEEE1394", Const, 0}, - {"IFT_IEEE80211", Const, 0}, - {"IFT_IEEE80212", Const, 0}, - {"IFT_IEEE8023ADLAG", Const, 0}, - {"IFT_IFGSN", Const, 0}, - {"IFT_IMT", Const, 0}, - {"IFT_INFINIBAND", Const, 1}, - {"IFT_INTERLEAVE", Const, 0}, - {"IFT_IP", Const, 0}, - {"IFT_IPFORWARD", Const, 0}, - {"IFT_IPOVERATM", Const, 0}, - {"IFT_IPOVERCDLC", Const, 0}, - {"IFT_IPOVERCLAW", Const, 0}, - {"IFT_IPSWITCH", Const, 0}, - {"IFT_IPXIP", Const, 0}, - {"IFT_ISDN", Const, 0}, - {"IFT_ISDNBASIC", Const, 0}, - {"IFT_ISDNPRIMARY", Const, 0}, - {"IFT_ISDNS", Const, 0}, - {"IFT_ISDNU", Const, 0}, - {"IFT_ISO88022LLC", Const, 0}, - {"IFT_ISO88023", Const, 0}, - {"IFT_ISO88024", Const, 0}, - {"IFT_ISO88025", Const, 0}, - {"IFT_ISO88025CRFPINT", Const, 0}, - {"IFT_ISO88025DTR", Const, 0}, - {"IFT_ISO88025FIBER", Const, 0}, - {"IFT_ISO88026", Const, 0}, - {"IFT_ISUP", Const, 0}, - {"IFT_L2VLAN", Const, 0}, - {"IFT_L3IPVLAN", Const, 0}, - {"IFT_L3IPXVLAN", Const, 0}, - {"IFT_LAPB", Const, 0}, - {"IFT_LAPD", Const, 0}, - {"IFT_LAPF", Const, 0}, - {"IFT_LINEGROUP", Const, 1}, - {"IFT_LOCALTALK", Const, 0}, - {"IFT_LOOP", Const, 0}, - {"IFT_MEDIAMAILOVERIP", Const, 0}, - {"IFT_MFSIGLINK", Const, 0}, - {"IFT_MIOX25", Const, 0}, - {"IFT_MODEM", Const, 0}, - {"IFT_MPC", Const, 0}, - {"IFT_MPLS", Const, 0}, - {"IFT_MPLSTUNNEL", Const, 0}, - {"IFT_MSDSL", Const, 0}, - {"IFT_MVL", Const, 0}, - {"IFT_MYRINET", Const, 0}, - {"IFT_NFAS", Const, 0}, - {"IFT_NSIP", Const, 0}, - {"IFT_OPTICALCHANNEL", Const, 0}, - {"IFT_OPTICALTRANSPORT", Const, 0}, - {"IFT_OTHER", Const, 0}, - {"IFT_P10", Const, 0}, - {"IFT_P80", Const, 0}, - {"IFT_PARA", Const, 0}, - {"IFT_PDP", Const, 0}, - {"IFT_PFLOG", Const, 0}, - {"IFT_PFLOW", Const, 1}, - {"IFT_PFSYNC", Const, 0}, - {"IFT_PLC", Const, 0}, - {"IFT_PON155", Const, 1}, - {"IFT_PON622", Const, 1}, - {"IFT_POS", Const, 0}, - {"IFT_PPP", Const, 0}, - {"IFT_PPPMULTILINKBUNDLE", Const, 0}, - {"IFT_PROPATM", Const, 1}, - {"IFT_PROPBWAP2MP", Const, 0}, - {"IFT_PROPCNLS", Const, 0}, - {"IFT_PROPDOCSWIRELESSDOWNSTREAM", Const, 0}, - {"IFT_PROPDOCSWIRELESSMACLAYER", Const, 0}, - {"IFT_PROPDOCSWIRELESSUPSTREAM", Const, 0}, - {"IFT_PROPMUX", Const, 0}, - {"IFT_PROPVIRTUAL", Const, 0}, - {"IFT_PROPWIRELESSP2P", Const, 0}, - {"IFT_PTPSERIAL", Const, 0}, - {"IFT_PVC", Const, 0}, - {"IFT_Q2931", Const, 1}, - {"IFT_QLLC", Const, 0}, - {"IFT_RADIOMAC", Const, 0}, - {"IFT_RADSL", Const, 0}, - {"IFT_REACHDSL", Const, 0}, - {"IFT_RFC1483", Const, 0}, - {"IFT_RS232", Const, 0}, - {"IFT_RSRB", Const, 0}, - {"IFT_SDLC", Const, 0}, - {"IFT_SDSL", Const, 0}, - {"IFT_SHDSL", Const, 0}, - {"IFT_SIP", Const, 0}, - {"IFT_SIPSIG", Const, 1}, - {"IFT_SIPTG", Const, 1}, - {"IFT_SLIP", Const, 0}, - {"IFT_SMDSDXI", Const, 0}, - {"IFT_SMDSICIP", Const, 0}, - {"IFT_SONET", Const, 0}, - {"IFT_SONETOVERHEADCHANNEL", Const, 0}, - {"IFT_SONETPATH", Const, 0}, - {"IFT_SONETVT", Const, 0}, - {"IFT_SRP", Const, 0}, - {"IFT_SS7SIGLINK", Const, 0}, - {"IFT_STACKTOSTACK", Const, 0}, - {"IFT_STARLAN", Const, 0}, - {"IFT_STF", Const, 0}, - {"IFT_T1", Const, 0}, - {"IFT_TDLC", Const, 0}, - {"IFT_TELINK", Const, 1}, - {"IFT_TERMPAD", Const, 0}, - {"IFT_TR008", Const, 0}, - {"IFT_TRANSPHDLC", Const, 0}, - {"IFT_TUNNEL", Const, 0}, - {"IFT_ULTRA", Const, 0}, - {"IFT_USB", Const, 0}, - {"IFT_V11", Const, 0}, - {"IFT_V35", Const, 0}, - {"IFT_V36", Const, 0}, - {"IFT_V37", Const, 0}, - {"IFT_VDSL", Const, 0}, - {"IFT_VIRTUALIPADDRESS", Const, 0}, - {"IFT_VIRTUALTG", Const, 1}, - {"IFT_VOICEDID", Const, 1}, - {"IFT_VOICEEM", Const, 0}, - {"IFT_VOICEEMFGD", Const, 1}, - {"IFT_VOICEENCAP", Const, 0}, - {"IFT_VOICEFGDEANA", Const, 1}, - {"IFT_VOICEFXO", Const, 0}, - {"IFT_VOICEFXS", Const, 0}, - {"IFT_VOICEOVERATM", Const, 0}, - {"IFT_VOICEOVERCABLE", Const, 1}, - {"IFT_VOICEOVERFRAMERELAY", Const, 0}, - {"IFT_VOICEOVERIP", Const, 0}, - {"IFT_X213", Const, 0}, - {"IFT_X25", Const, 0}, - {"IFT_X25DDN", Const, 0}, - {"IFT_X25HUNTGROUP", Const, 0}, - {"IFT_X25MLP", Const, 0}, - {"IFT_X25PLE", Const, 0}, - {"IFT_XETHER", Const, 0}, - {"IGNBRK", Const, 0}, - {"IGNCR", Const, 0}, - {"IGNORE", Const, 0}, - {"IGNPAR", Const, 0}, - {"IMAXBEL", Const, 0}, - {"INFINITE", Const, 0}, - {"INLCR", Const, 0}, - {"INPCK", Const, 0}, - {"INVALID_FILE_ATTRIBUTES", Const, 0}, - {"IN_ACCESS", Const, 0}, - {"IN_ALL_EVENTS", Const, 0}, - {"IN_ATTRIB", Const, 0}, - {"IN_CLASSA_HOST", Const, 0}, - {"IN_CLASSA_MAX", Const, 0}, - {"IN_CLASSA_NET", Const, 0}, - {"IN_CLASSA_NSHIFT", Const, 0}, - {"IN_CLASSB_HOST", Const, 0}, - {"IN_CLASSB_MAX", Const, 0}, - {"IN_CLASSB_NET", Const, 0}, - {"IN_CLASSB_NSHIFT", Const, 0}, - {"IN_CLASSC_HOST", Const, 0}, - {"IN_CLASSC_NET", Const, 0}, - {"IN_CLASSC_NSHIFT", Const, 0}, - {"IN_CLASSD_HOST", Const, 0}, - {"IN_CLASSD_NET", Const, 0}, - {"IN_CLASSD_NSHIFT", Const, 0}, - {"IN_CLOEXEC", Const, 0}, - {"IN_CLOSE", Const, 0}, - {"IN_CLOSE_NOWRITE", Const, 0}, - {"IN_CLOSE_WRITE", Const, 0}, - {"IN_CREATE", Const, 0}, - {"IN_DELETE", Const, 0}, - {"IN_DELETE_SELF", Const, 0}, - {"IN_DONT_FOLLOW", Const, 0}, - {"IN_EXCL_UNLINK", Const, 0}, - {"IN_IGNORED", Const, 0}, - {"IN_ISDIR", Const, 0}, - {"IN_LINKLOCALNETNUM", Const, 0}, - {"IN_LOOPBACKNET", Const, 0}, - {"IN_MASK_ADD", Const, 0}, - {"IN_MODIFY", Const, 0}, - {"IN_MOVE", Const, 0}, - {"IN_MOVED_FROM", Const, 0}, - {"IN_MOVED_TO", Const, 0}, - {"IN_MOVE_SELF", Const, 0}, - {"IN_NONBLOCK", Const, 0}, - {"IN_ONESHOT", Const, 0}, - {"IN_ONLYDIR", Const, 0}, - {"IN_OPEN", Const, 0}, - {"IN_Q_OVERFLOW", Const, 0}, - {"IN_RFC3021_HOST", Const, 1}, - {"IN_RFC3021_MASK", Const, 1}, - {"IN_RFC3021_NET", Const, 1}, - {"IN_RFC3021_NSHIFT", Const, 1}, - {"IN_UNMOUNT", Const, 0}, - {"IOC_IN", Const, 1}, - {"IOC_INOUT", Const, 1}, - {"IOC_OUT", Const, 1}, - {"IOC_VENDOR", Const, 3}, - {"IOC_WS2", Const, 1}, - {"IO_REPARSE_TAG_SYMLINK", Const, 4}, - {"IPMreq", Type, 0}, - {"IPMreq.Interface", Field, 0}, - {"IPMreq.Multiaddr", Field, 0}, - {"IPMreqn", Type, 0}, - {"IPMreqn.Address", Field, 0}, - {"IPMreqn.Ifindex", Field, 0}, - {"IPMreqn.Multiaddr", Field, 0}, - {"IPPROTO_3PC", Const, 0}, - {"IPPROTO_ADFS", Const, 0}, - {"IPPROTO_AH", Const, 0}, - {"IPPROTO_AHIP", Const, 0}, - {"IPPROTO_APES", Const, 0}, - {"IPPROTO_ARGUS", Const, 0}, - {"IPPROTO_AX25", Const, 0}, - {"IPPROTO_BHA", Const, 0}, - {"IPPROTO_BLT", Const, 0}, - {"IPPROTO_BRSATMON", Const, 0}, - {"IPPROTO_CARP", Const, 0}, - {"IPPROTO_CFTP", Const, 0}, - {"IPPROTO_CHAOS", Const, 0}, - {"IPPROTO_CMTP", Const, 0}, - {"IPPROTO_COMP", Const, 0}, - {"IPPROTO_CPHB", Const, 0}, - {"IPPROTO_CPNX", Const, 0}, - {"IPPROTO_DCCP", Const, 0}, - {"IPPROTO_DDP", Const, 0}, - {"IPPROTO_DGP", Const, 0}, - {"IPPROTO_DIVERT", Const, 0}, - {"IPPROTO_DIVERT_INIT", Const, 3}, - {"IPPROTO_DIVERT_RESP", Const, 3}, - {"IPPROTO_DONE", Const, 0}, - {"IPPROTO_DSTOPTS", Const, 0}, - {"IPPROTO_EGP", Const, 0}, - {"IPPROTO_EMCON", Const, 0}, - {"IPPROTO_ENCAP", Const, 0}, - {"IPPROTO_EON", Const, 0}, - {"IPPROTO_ESP", Const, 0}, - {"IPPROTO_ETHERIP", Const, 0}, - {"IPPROTO_FRAGMENT", Const, 0}, - {"IPPROTO_GGP", Const, 0}, - {"IPPROTO_GMTP", Const, 0}, - {"IPPROTO_GRE", Const, 0}, - {"IPPROTO_HELLO", Const, 0}, - {"IPPROTO_HMP", Const, 0}, - {"IPPROTO_HOPOPTS", Const, 0}, - {"IPPROTO_ICMP", Const, 0}, - {"IPPROTO_ICMPV6", Const, 0}, - {"IPPROTO_IDP", Const, 0}, - {"IPPROTO_IDPR", Const, 0}, - {"IPPROTO_IDRP", Const, 0}, - {"IPPROTO_IGMP", Const, 0}, - {"IPPROTO_IGP", Const, 0}, - {"IPPROTO_IGRP", Const, 0}, - {"IPPROTO_IL", Const, 0}, - {"IPPROTO_INLSP", Const, 0}, - {"IPPROTO_INP", Const, 0}, - {"IPPROTO_IP", Const, 0}, - {"IPPROTO_IPCOMP", Const, 0}, - {"IPPROTO_IPCV", Const, 0}, - {"IPPROTO_IPEIP", Const, 0}, - {"IPPROTO_IPIP", Const, 0}, - {"IPPROTO_IPPC", Const, 0}, - {"IPPROTO_IPV4", Const, 0}, - {"IPPROTO_IPV6", Const, 0}, - {"IPPROTO_IPV6_ICMP", Const, 1}, - {"IPPROTO_IRTP", Const, 0}, - {"IPPROTO_KRYPTOLAN", Const, 0}, - {"IPPROTO_LARP", Const, 0}, - {"IPPROTO_LEAF1", Const, 0}, - {"IPPROTO_LEAF2", Const, 0}, - {"IPPROTO_MAX", Const, 0}, - {"IPPROTO_MAXID", Const, 0}, - {"IPPROTO_MEAS", Const, 0}, - {"IPPROTO_MH", Const, 1}, - {"IPPROTO_MHRP", Const, 0}, - {"IPPROTO_MICP", Const, 0}, - {"IPPROTO_MOBILE", Const, 0}, - {"IPPROTO_MPLS", Const, 1}, - {"IPPROTO_MTP", Const, 0}, - {"IPPROTO_MUX", Const, 0}, - {"IPPROTO_ND", Const, 0}, - {"IPPROTO_NHRP", Const, 0}, - {"IPPROTO_NONE", Const, 0}, - {"IPPROTO_NSP", Const, 0}, - {"IPPROTO_NVPII", Const, 0}, - {"IPPROTO_OLD_DIVERT", Const, 0}, - {"IPPROTO_OSPFIGP", Const, 0}, - {"IPPROTO_PFSYNC", Const, 0}, - {"IPPROTO_PGM", Const, 0}, - {"IPPROTO_PIGP", Const, 0}, - {"IPPROTO_PIM", Const, 0}, - {"IPPROTO_PRM", Const, 0}, - {"IPPROTO_PUP", Const, 0}, - {"IPPROTO_PVP", Const, 0}, - {"IPPROTO_RAW", Const, 0}, - {"IPPROTO_RCCMON", Const, 0}, - {"IPPROTO_RDP", Const, 0}, - {"IPPROTO_ROUTING", Const, 0}, - {"IPPROTO_RSVP", Const, 0}, - {"IPPROTO_RVD", Const, 0}, - {"IPPROTO_SATEXPAK", Const, 0}, - {"IPPROTO_SATMON", Const, 0}, - {"IPPROTO_SCCSP", Const, 0}, - {"IPPROTO_SCTP", Const, 0}, - {"IPPROTO_SDRP", Const, 0}, - {"IPPROTO_SEND", Const, 1}, - {"IPPROTO_SEP", Const, 0}, - {"IPPROTO_SKIP", Const, 0}, - {"IPPROTO_SPACER", Const, 0}, - {"IPPROTO_SRPC", Const, 0}, - {"IPPROTO_ST", Const, 0}, - {"IPPROTO_SVMTP", Const, 0}, - {"IPPROTO_SWIPE", Const, 0}, - {"IPPROTO_TCF", Const, 0}, - {"IPPROTO_TCP", Const, 0}, - {"IPPROTO_TLSP", Const, 0}, - {"IPPROTO_TP", Const, 0}, - {"IPPROTO_TPXX", Const, 0}, - {"IPPROTO_TRUNK1", Const, 0}, - {"IPPROTO_TRUNK2", Const, 0}, - {"IPPROTO_TTP", Const, 0}, - {"IPPROTO_UDP", Const, 0}, - {"IPPROTO_UDPLITE", Const, 0}, - {"IPPROTO_VINES", Const, 0}, - {"IPPROTO_VISA", Const, 0}, - {"IPPROTO_VMTP", Const, 0}, - {"IPPROTO_VRRP", Const, 1}, - {"IPPROTO_WBEXPAK", Const, 0}, - {"IPPROTO_WBMON", Const, 0}, - {"IPPROTO_WSN", Const, 0}, - {"IPPROTO_XNET", Const, 0}, - {"IPPROTO_XTP", Const, 0}, - {"IPV6_2292DSTOPTS", Const, 0}, - {"IPV6_2292HOPLIMIT", Const, 0}, - {"IPV6_2292HOPOPTS", Const, 0}, - {"IPV6_2292NEXTHOP", Const, 0}, - {"IPV6_2292PKTINFO", Const, 0}, - {"IPV6_2292PKTOPTIONS", Const, 0}, - {"IPV6_2292RTHDR", Const, 0}, - {"IPV6_ADDRFORM", Const, 0}, - {"IPV6_ADD_MEMBERSHIP", Const, 0}, - {"IPV6_AUTHHDR", Const, 0}, - {"IPV6_AUTH_LEVEL", Const, 1}, - {"IPV6_AUTOFLOWLABEL", Const, 0}, - {"IPV6_BINDANY", Const, 0}, - {"IPV6_BINDV6ONLY", Const, 0}, - {"IPV6_BOUND_IF", Const, 0}, - {"IPV6_CHECKSUM", Const, 0}, - {"IPV6_DEFAULT_MULTICAST_HOPS", Const, 0}, - {"IPV6_DEFAULT_MULTICAST_LOOP", Const, 0}, - {"IPV6_DEFHLIM", Const, 0}, - {"IPV6_DONTFRAG", Const, 0}, - {"IPV6_DROP_MEMBERSHIP", Const, 0}, - {"IPV6_DSTOPTS", Const, 0}, - {"IPV6_ESP_NETWORK_LEVEL", Const, 1}, - {"IPV6_ESP_TRANS_LEVEL", Const, 1}, - {"IPV6_FAITH", Const, 0}, - {"IPV6_FLOWINFO_MASK", Const, 0}, - {"IPV6_FLOWLABEL_MASK", Const, 0}, - {"IPV6_FRAGTTL", Const, 0}, - {"IPV6_FW_ADD", Const, 0}, - {"IPV6_FW_DEL", Const, 0}, - {"IPV6_FW_FLUSH", Const, 0}, - {"IPV6_FW_GET", Const, 0}, - {"IPV6_FW_ZERO", Const, 0}, - {"IPV6_HLIMDEC", Const, 0}, - {"IPV6_HOPLIMIT", Const, 0}, - {"IPV6_HOPOPTS", Const, 0}, - {"IPV6_IPCOMP_LEVEL", Const, 1}, - {"IPV6_IPSEC_POLICY", Const, 0}, - {"IPV6_JOIN_ANYCAST", Const, 0}, - {"IPV6_JOIN_GROUP", Const, 0}, - {"IPV6_LEAVE_ANYCAST", Const, 0}, - {"IPV6_LEAVE_GROUP", Const, 0}, - {"IPV6_MAXHLIM", Const, 0}, - {"IPV6_MAXOPTHDR", Const, 0}, - {"IPV6_MAXPACKET", Const, 0}, - {"IPV6_MAX_GROUP_SRC_FILTER", Const, 0}, - {"IPV6_MAX_MEMBERSHIPS", Const, 0}, - {"IPV6_MAX_SOCK_SRC_FILTER", Const, 0}, - {"IPV6_MIN_MEMBERSHIPS", Const, 0}, - {"IPV6_MMTU", Const, 0}, - {"IPV6_MSFILTER", Const, 0}, - {"IPV6_MTU", Const, 0}, - {"IPV6_MTU_DISCOVER", Const, 0}, - {"IPV6_MULTICAST_HOPS", Const, 0}, - {"IPV6_MULTICAST_IF", Const, 0}, - {"IPV6_MULTICAST_LOOP", Const, 0}, - {"IPV6_NEXTHOP", Const, 0}, - {"IPV6_OPTIONS", Const, 1}, - {"IPV6_PATHMTU", Const, 0}, - {"IPV6_PIPEX", Const, 1}, - {"IPV6_PKTINFO", Const, 0}, - {"IPV6_PMTUDISC_DO", Const, 0}, - {"IPV6_PMTUDISC_DONT", Const, 0}, - {"IPV6_PMTUDISC_PROBE", Const, 0}, - {"IPV6_PMTUDISC_WANT", Const, 0}, - {"IPV6_PORTRANGE", Const, 0}, - {"IPV6_PORTRANGE_DEFAULT", Const, 0}, - {"IPV6_PORTRANGE_HIGH", Const, 0}, - {"IPV6_PORTRANGE_LOW", Const, 0}, - {"IPV6_PREFER_TEMPADDR", Const, 0}, - {"IPV6_RECVDSTOPTS", Const, 0}, - {"IPV6_RECVDSTPORT", Const, 3}, - {"IPV6_RECVERR", Const, 0}, - {"IPV6_RECVHOPLIMIT", Const, 0}, - {"IPV6_RECVHOPOPTS", Const, 0}, - {"IPV6_RECVPATHMTU", Const, 0}, - {"IPV6_RECVPKTINFO", Const, 0}, - {"IPV6_RECVRTHDR", Const, 0}, - {"IPV6_RECVTCLASS", Const, 0}, - {"IPV6_ROUTER_ALERT", Const, 0}, - {"IPV6_RTABLE", Const, 1}, - {"IPV6_RTHDR", Const, 0}, - {"IPV6_RTHDRDSTOPTS", Const, 0}, - {"IPV6_RTHDR_LOOSE", Const, 0}, - {"IPV6_RTHDR_STRICT", Const, 0}, - {"IPV6_RTHDR_TYPE_0", Const, 0}, - {"IPV6_RXDSTOPTS", Const, 0}, - {"IPV6_RXHOPOPTS", Const, 0}, - {"IPV6_SOCKOPT_RESERVED1", Const, 0}, - {"IPV6_TCLASS", Const, 0}, - {"IPV6_UNICAST_HOPS", Const, 0}, - {"IPV6_USE_MIN_MTU", Const, 0}, - {"IPV6_V6ONLY", Const, 0}, - {"IPV6_VERSION", Const, 0}, - {"IPV6_VERSION_MASK", Const, 0}, - {"IPV6_XFRM_POLICY", Const, 0}, - {"IP_ADD_MEMBERSHIP", Const, 0}, - {"IP_ADD_SOURCE_MEMBERSHIP", Const, 0}, - {"IP_AUTH_LEVEL", Const, 1}, - {"IP_BINDANY", Const, 0}, - {"IP_BLOCK_SOURCE", Const, 0}, - {"IP_BOUND_IF", Const, 0}, - {"IP_DEFAULT_MULTICAST_LOOP", Const, 0}, - {"IP_DEFAULT_MULTICAST_TTL", Const, 0}, - {"IP_DF", Const, 0}, - {"IP_DIVERTFL", Const, 3}, - {"IP_DONTFRAG", Const, 0}, - {"IP_DROP_MEMBERSHIP", Const, 0}, - {"IP_DROP_SOURCE_MEMBERSHIP", Const, 0}, - {"IP_DUMMYNET3", Const, 0}, - {"IP_DUMMYNET_CONFIGURE", Const, 0}, - {"IP_DUMMYNET_DEL", Const, 0}, - {"IP_DUMMYNET_FLUSH", Const, 0}, - {"IP_DUMMYNET_GET", Const, 0}, - {"IP_EF", Const, 1}, - {"IP_ERRORMTU", Const, 1}, - {"IP_ESP_NETWORK_LEVEL", Const, 1}, - {"IP_ESP_TRANS_LEVEL", Const, 1}, - {"IP_FAITH", Const, 0}, - {"IP_FREEBIND", Const, 0}, - {"IP_FW3", Const, 0}, - {"IP_FW_ADD", Const, 0}, - {"IP_FW_DEL", Const, 0}, - {"IP_FW_FLUSH", Const, 0}, - {"IP_FW_GET", Const, 0}, - {"IP_FW_NAT_CFG", Const, 0}, - {"IP_FW_NAT_DEL", Const, 0}, - {"IP_FW_NAT_GET_CONFIG", Const, 0}, - {"IP_FW_NAT_GET_LOG", Const, 0}, - {"IP_FW_RESETLOG", Const, 0}, - {"IP_FW_TABLE_ADD", Const, 0}, - {"IP_FW_TABLE_DEL", Const, 0}, - {"IP_FW_TABLE_FLUSH", Const, 0}, - {"IP_FW_TABLE_GETSIZE", Const, 0}, - {"IP_FW_TABLE_LIST", Const, 0}, - {"IP_FW_ZERO", Const, 0}, - {"IP_HDRINCL", Const, 0}, - {"IP_IPCOMP_LEVEL", Const, 1}, - {"IP_IPSECFLOWINFO", Const, 1}, - {"IP_IPSEC_LOCAL_AUTH", Const, 1}, - {"IP_IPSEC_LOCAL_CRED", Const, 1}, - {"IP_IPSEC_LOCAL_ID", Const, 1}, - {"IP_IPSEC_POLICY", Const, 0}, - {"IP_IPSEC_REMOTE_AUTH", Const, 1}, - {"IP_IPSEC_REMOTE_CRED", Const, 1}, - {"IP_IPSEC_REMOTE_ID", Const, 1}, - {"IP_MAXPACKET", Const, 0}, - {"IP_MAX_GROUP_SRC_FILTER", Const, 0}, - {"IP_MAX_MEMBERSHIPS", Const, 0}, - {"IP_MAX_SOCK_MUTE_FILTER", Const, 0}, - {"IP_MAX_SOCK_SRC_FILTER", Const, 0}, - {"IP_MAX_SOURCE_FILTER", Const, 0}, - {"IP_MF", Const, 0}, - {"IP_MINFRAGSIZE", Const, 1}, - {"IP_MINTTL", Const, 0}, - {"IP_MIN_MEMBERSHIPS", Const, 0}, - {"IP_MSFILTER", Const, 0}, - {"IP_MSS", Const, 0}, - {"IP_MTU", Const, 0}, - {"IP_MTU_DISCOVER", Const, 0}, - {"IP_MULTICAST_IF", Const, 0}, - {"IP_MULTICAST_IFINDEX", Const, 0}, - {"IP_MULTICAST_LOOP", Const, 0}, - {"IP_MULTICAST_TTL", Const, 0}, - {"IP_MULTICAST_VIF", Const, 0}, - {"IP_NAT__XXX", Const, 0}, - {"IP_OFFMASK", Const, 0}, - {"IP_OLD_FW_ADD", Const, 0}, - {"IP_OLD_FW_DEL", Const, 0}, - {"IP_OLD_FW_FLUSH", Const, 0}, - {"IP_OLD_FW_GET", Const, 0}, - {"IP_OLD_FW_RESETLOG", Const, 0}, - {"IP_OLD_FW_ZERO", Const, 0}, - {"IP_ONESBCAST", Const, 0}, - {"IP_OPTIONS", Const, 0}, - {"IP_ORIGDSTADDR", Const, 0}, - {"IP_PASSSEC", Const, 0}, - {"IP_PIPEX", Const, 1}, - {"IP_PKTINFO", Const, 0}, - {"IP_PKTOPTIONS", Const, 0}, - {"IP_PMTUDISC", Const, 0}, - {"IP_PMTUDISC_DO", Const, 0}, - {"IP_PMTUDISC_DONT", Const, 0}, - {"IP_PMTUDISC_PROBE", Const, 0}, - {"IP_PMTUDISC_WANT", Const, 0}, - {"IP_PORTRANGE", Const, 0}, - {"IP_PORTRANGE_DEFAULT", Const, 0}, - {"IP_PORTRANGE_HIGH", Const, 0}, - {"IP_PORTRANGE_LOW", Const, 0}, - {"IP_RECVDSTADDR", Const, 0}, - {"IP_RECVDSTPORT", Const, 1}, - {"IP_RECVERR", Const, 0}, - {"IP_RECVIF", Const, 0}, - {"IP_RECVOPTS", Const, 0}, - {"IP_RECVORIGDSTADDR", Const, 0}, - {"IP_RECVPKTINFO", Const, 0}, - {"IP_RECVRETOPTS", Const, 0}, - {"IP_RECVRTABLE", Const, 1}, - {"IP_RECVTOS", Const, 0}, - {"IP_RECVTTL", Const, 0}, - {"IP_RETOPTS", Const, 0}, - {"IP_RF", Const, 0}, - {"IP_ROUTER_ALERT", Const, 0}, - {"IP_RSVP_OFF", Const, 0}, - {"IP_RSVP_ON", Const, 0}, - {"IP_RSVP_VIF_OFF", Const, 0}, - {"IP_RSVP_VIF_ON", Const, 0}, - {"IP_RTABLE", Const, 1}, - {"IP_SENDSRCADDR", Const, 0}, - {"IP_STRIPHDR", Const, 0}, - {"IP_TOS", Const, 0}, - {"IP_TRAFFIC_MGT_BACKGROUND", Const, 0}, - {"IP_TRANSPARENT", Const, 0}, - {"IP_TTL", Const, 0}, - {"IP_UNBLOCK_SOURCE", Const, 0}, - {"IP_XFRM_POLICY", Const, 0}, - {"IPv6MTUInfo", Type, 2}, - {"IPv6MTUInfo.Addr", Field, 2}, - {"IPv6MTUInfo.Mtu", Field, 2}, - {"IPv6Mreq", Type, 0}, - {"IPv6Mreq.Interface", Field, 0}, - {"IPv6Mreq.Multiaddr", Field, 0}, - {"ISIG", Const, 0}, - {"ISTRIP", Const, 0}, - {"IUCLC", Const, 0}, - {"IUTF8", Const, 0}, - {"IXANY", Const, 0}, - {"IXOFF", Const, 0}, - {"IXON", Const, 0}, - {"IfAddrmsg", Type, 0}, - {"IfAddrmsg.Family", Field, 0}, - {"IfAddrmsg.Flags", Field, 0}, - {"IfAddrmsg.Index", Field, 0}, - {"IfAddrmsg.Prefixlen", Field, 0}, - {"IfAddrmsg.Scope", Field, 0}, - {"IfAnnounceMsghdr", Type, 1}, - {"IfAnnounceMsghdr.Hdrlen", Field, 2}, - {"IfAnnounceMsghdr.Index", Field, 1}, - {"IfAnnounceMsghdr.Msglen", Field, 1}, - {"IfAnnounceMsghdr.Name", Field, 1}, - {"IfAnnounceMsghdr.Type", Field, 1}, - {"IfAnnounceMsghdr.Version", Field, 1}, - {"IfAnnounceMsghdr.What", Field, 1}, - {"IfData", Type, 0}, - {"IfData.Addrlen", Field, 0}, - {"IfData.Baudrate", Field, 0}, - {"IfData.Capabilities", Field, 2}, - {"IfData.Collisions", Field, 0}, - {"IfData.Datalen", Field, 0}, - {"IfData.Epoch", Field, 0}, - {"IfData.Hdrlen", Field, 0}, - {"IfData.Hwassist", Field, 0}, - {"IfData.Ibytes", Field, 0}, - {"IfData.Ierrors", Field, 0}, - {"IfData.Imcasts", Field, 0}, - {"IfData.Ipackets", Field, 0}, - {"IfData.Iqdrops", Field, 0}, - {"IfData.Lastchange", Field, 0}, - {"IfData.Link_state", Field, 0}, - {"IfData.Mclpool", Field, 2}, - {"IfData.Metric", Field, 0}, - {"IfData.Mtu", Field, 0}, - {"IfData.Noproto", Field, 0}, - {"IfData.Obytes", Field, 0}, - {"IfData.Oerrors", Field, 0}, - {"IfData.Omcasts", Field, 0}, - {"IfData.Opackets", Field, 0}, - {"IfData.Pad", Field, 2}, - {"IfData.Pad_cgo_0", Field, 2}, - {"IfData.Pad_cgo_1", Field, 2}, - {"IfData.Physical", Field, 0}, - {"IfData.Recvquota", Field, 0}, - {"IfData.Recvtiming", Field, 0}, - {"IfData.Reserved1", Field, 0}, - {"IfData.Reserved2", Field, 0}, - {"IfData.Spare_char1", Field, 0}, - {"IfData.Spare_char2", Field, 0}, - {"IfData.Type", Field, 0}, - {"IfData.Typelen", Field, 0}, - {"IfData.Unused1", Field, 0}, - {"IfData.Unused2", Field, 0}, - {"IfData.Xmitquota", Field, 0}, - {"IfData.Xmittiming", Field, 0}, - {"IfInfomsg", Type, 0}, - {"IfInfomsg.Change", Field, 0}, - {"IfInfomsg.Family", Field, 0}, - {"IfInfomsg.Flags", Field, 0}, - {"IfInfomsg.Index", Field, 0}, - {"IfInfomsg.Type", Field, 0}, - {"IfInfomsg.X__ifi_pad", Field, 0}, - {"IfMsghdr", Type, 0}, - {"IfMsghdr.Addrs", Field, 0}, - {"IfMsghdr.Data", Field, 0}, - {"IfMsghdr.Flags", Field, 0}, - {"IfMsghdr.Hdrlen", Field, 2}, - {"IfMsghdr.Index", Field, 0}, - {"IfMsghdr.Msglen", Field, 0}, - {"IfMsghdr.Pad1", Field, 2}, - {"IfMsghdr.Pad2", Field, 2}, - {"IfMsghdr.Pad_cgo_0", Field, 0}, - {"IfMsghdr.Pad_cgo_1", Field, 2}, - {"IfMsghdr.Tableid", Field, 2}, - {"IfMsghdr.Type", Field, 0}, - {"IfMsghdr.Version", Field, 0}, - {"IfMsghdr.Xflags", Field, 2}, - {"IfaMsghdr", Type, 0}, - {"IfaMsghdr.Addrs", Field, 0}, - {"IfaMsghdr.Flags", Field, 0}, - {"IfaMsghdr.Hdrlen", Field, 2}, - {"IfaMsghdr.Index", Field, 0}, - {"IfaMsghdr.Metric", Field, 0}, - {"IfaMsghdr.Msglen", Field, 0}, - {"IfaMsghdr.Pad1", Field, 2}, - {"IfaMsghdr.Pad2", Field, 2}, - {"IfaMsghdr.Pad_cgo_0", Field, 0}, - {"IfaMsghdr.Tableid", Field, 2}, - {"IfaMsghdr.Type", Field, 0}, - {"IfaMsghdr.Version", Field, 0}, - {"IfmaMsghdr", Type, 0}, - {"IfmaMsghdr.Addrs", Field, 0}, - {"IfmaMsghdr.Flags", Field, 0}, - {"IfmaMsghdr.Index", Field, 0}, - {"IfmaMsghdr.Msglen", Field, 0}, - {"IfmaMsghdr.Pad_cgo_0", Field, 0}, - {"IfmaMsghdr.Type", Field, 0}, - {"IfmaMsghdr.Version", Field, 0}, - {"IfmaMsghdr2", Type, 0}, - {"IfmaMsghdr2.Addrs", Field, 0}, - {"IfmaMsghdr2.Flags", Field, 0}, - {"IfmaMsghdr2.Index", Field, 0}, - {"IfmaMsghdr2.Msglen", Field, 0}, - {"IfmaMsghdr2.Pad_cgo_0", Field, 0}, - {"IfmaMsghdr2.Refcount", Field, 0}, - {"IfmaMsghdr2.Type", Field, 0}, - {"IfmaMsghdr2.Version", Field, 0}, - {"ImplementsGetwd", Const, 0}, - {"Inet4Pktinfo", Type, 0}, - {"Inet4Pktinfo.Addr", Field, 0}, - {"Inet4Pktinfo.Ifindex", Field, 0}, - {"Inet4Pktinfo.Spec_dst", Field, 0}, - {"Inet6Pktinfo", Type, 0}, - {"Inet6Pktinfo.Addr", Field, 0}, - {"Inet6Pktinfo.Ifindex", Field, 0}, - {"InotifyAddWatch", Func, 0}, - {"InotifyEvent", Type, 0}, - {"InotifyEvent.Cookie", Field, 0}, - {"InotifyEvent.Len", Field, 0}, - {"InotifyEvent.Mask", Field, 0}, - {"InotifyEvent.Name", Field, 0}, - {"InotifyEvent.Wd", Field, 0}, - {"InotifyInit", Func, 0}, - {"InotifyInit1", Func, 0}, - {"InotifyRmWatch", Func, 0}, - {"InterfaceAddrMessage", Type, 0}, - {"InterfaceAddrMessage.Data", Field, 0}, - {"InterfaceAddrMessage.Header", Field, 0}, - {"InterfaceAnnounceMessage", Type, 1}, - {"InterfaceAnnounceMessage.Header", Field, 1}, - {"InterfaceInfo", Type, 0}, - {"InterfaceInfo.Address", Field, 0}, - {"InterfaceInfo.BroadcastAddress", Field, 0}, - {"InterfaceInfo.Flags", Field, 0}, - {"InterfaceInfo.Netmask", Field, 0}, - {"InterfaceMessage", Type, 0}, - {"InterfaceMessage.Data", Field, 0}, - {"InterfaceMessage.Header", Field, 0}, - {"InterfaceMulticastAddrMessage", Type, 0}, - {"InterfaceMulticastAddrMessage.Data", Field, 0}, - {"InterfaceMulticastAddrMessage.Header", Field, 0}, - {"InvalidHandle", Const, 0}, - {"Ioperm", Func, 0}, - {"Iopl", Func, 0}, - {"Iovec", Type, 0}, - {"Iovec.Base", Field, 0}, - {"Iovec.Len", Field, 0}, - {"IpAdapterInfo", Type, 0}, - {"IpAdapterInfo.AdapterName", Field, 0}, - {"IpAdapterInfo.Address", Field, 0}, - {"IpAdapterInfo.AddressLength", Field, 0}, - {"IpAdapterInfo.ComboIndex", Field, 0}, - {"IpAdapterInfo.CurrentIpAddress", Field, 0}, - {"IpAdapterInfo.Description", Field, 0}, - {"IpAdapterInfo.DhcpEnabled", Field, 0}, - {"IpAdapterInfo.DhcpServer", Field, 0}, - {"IpAdapterInfo.GatewayList", Field, 0}, - {"IpAdapterInfo.HaveWins", Field, 0}, - {"IpAdapterInfo.Index", Field, 0}, - {"IpAdapterInfo.IpAddressList", Field, 0}, - {"IpAdapterInfo.LeaseExpires", Field, 0}, - {"IpAdapterInfo.LeaseObtained", Field, 0}, - {"IpAdapterInfo.Next", Field, 0}, - {"IpAdapterInfo.PrimaryWinsServer", Field, 0}, - {"IpAdapterInfo.SecondaryWinsServer", Field, 0}, - {"IpAdapterInfo.Type", Field, 0}, - {"IpAddrString", Type, 0}, - {"IpAddrString.Context", Field, 0}, - {"IpAddrString.IpAddress", Field, 0}, - {"IpAddrString.IpMask", Field, 0}, - {"IpAddrString.Next", Field, 0}, - {"IpAddressString", Type, 0}, - {"IpAddressString.String", Field, 0}, - {"IpMaskString", Type, 0}, - {"IpMaskString.String", Field, 2}, - {"Issetugid", Func, 0}, - {"KEY_ALL_ACCESS", Const, 0}, - {"KEY_CREATE_LINK", Const, 0}, - {"KEY_CREATE_SUB_KEY", Const, 0}, - {"KEY_ENUMERATE_SUB_KEYS", Const, 0}, - {"KEY_EXECUTE", Const, 0}, - {"KEY_NOTIFY", Const, 0}, - {"KEY_QUERY_VALUE", Const, 0}, - {"KEY_READ", Const, 0}, - {"KEY_SET_VALUE", Const, 0}, - {"KEY_WOW64_32KEY", Const, 0}, - {"KEY_WOW64_64KEY", Const, 0}, - {"KEY_WRITE", Const, 0}, - {"Kevent", Func, 0}, - {"Kevent_t", Type, 0}, - {"Kevent_t.Data", Field, 0}, - {"Kevent_t.Fflags", Field, 0}, - {"Kevent_t.Filter", Field, 0}, - {"Kevent_t.Flags", Field, 0}, - {"Kevent_t.Ident", Field, 0}, - {"Kevent_t.Pad_cgo_0", Field, 2}, - {"Kevent_t.Udata", Field, 0}, - {"Kill", Func, 0}, - {"Klogctl", Func, 0}, - {"Kqueue", Func, 0}, - {"LANG_ENGLISH", Const, 0}, - {"LAYERED_PROTOCOL", Const, 2}, - {"LCNT_OVERLOAD_FLUSH", Const, 1}, - {"LINUX_REBOOT_CMD_CAD_OFF", Const, 0}, - {"LINUX_REBOOT_CMD_CAD_ON", Const, 0}, - {"LINUX_REBOOT_CMD_HALT", Const, 0}, - {"LINUX_REBOOT_CMD_KEXEC", Const, 0}, - {"LINUX_REBOOT_CMD_POWER_OFF", Const, 0}, - {"LINUX_REBOOT_CMD_RESTART", Const, 0}, - {"LINUX_REBOOT_CMD_RESTART2", Const, 0}, - {"LINUX_REBOOT_CMD_SW_SUSPEND", Const, 0}, - {"LINUX_REBOOT_MAGIC1", Const, 0}, - {"LINUX_REBOOT_MAGIC2", Const, 0}, - {"LOCK_EX", Const, 0}, - {"LOCK_NB", Const, 0}, - {"LOCK_SH", Const, 0}, - {"LOCK_UN", Const, 0}, - {"LazyDLL", Type, 0}, - {"LazyDLL.Name", Field, 0}, - {"LazyProc", Type, 0}, - {"LazyProc.Name", Field, 0}, - {"Lchown", Func, 0}, - {"Linger", Type, 0}, - {"Linger.Linger", Field, 0}, - {"Linger.Onoff", Field, 0}, - {"Link", Func, 0}, - {"Listen", Func, 0}, - {"Listxattr", Func, 1}, - {"LoadCancelIoEx", Func, 1}, - {"LoadConnectEx", Func, 1}, - {"LoadCreateSymbolicLink", Func, 4}, - {"LoadDLL", Func, 0}, - {"LoadGetAddrInfo", Func, 1}, - {"LoadLibrary", Func, 0}, - {"LoadSetFileCompletionNotificationModes", Func, 2}, - {"LocalFree", Func, 0}, - {"Log2phys_t", Type, 0}, - {"Log2phys_t.Contigbytes", Field, 0}, - {"Log2phys_t.Devoffset", Field, 0}, - {"Log2phys_t.Flags", Field, 0}, - {"LookupAccountName", Func, 0}, - {"LookupAccountSid", Func, 0}, - {"LookupSID", Func, 0}, - {"LsfJump", Func, 0}, - {"LsfSocket", Func, 0}, - {"LsfStmt", Func, 0}, - {"Lstat", Func, 0}, - {"MADV_AUTOSYNC", Const, 1}, - {"MADV_CAN_REUSE", Const, 0}, - {"MADV_CORE", Const, 1}, - {"MADV_DOFORK", Const, 0}, - {"MADV_DONTFORK", Const, 0}, - {"MADV_DONTNEED", Const, 0}, - {"MADV_FREE", Const, 0}, - {"MADV_FREE_REUSABLE", Const, 0}, - {"MADV_FREE_REUSE", Const, 0}, - {"MADV_HUGEPAGE", Const, 0}, - {"MADV_HWPOISON", Const, 0}, - {"MADV_MERGEABLE", Const, 0}, - {"MADV_NOCORE", Const, 1}, - {"MADV_NOHUGEPAGE", Const, 0}, - {"MADV_NORMAL", Const, 0}, - {"MADV_NOSYNC", Const, 1}, - {"MADV_PROTECT", Const, 1}, - {"MADV_RANDOM", Const, 0}, - {"MADV_REMOVE", Const, 0}, - {"MADV_SEQUENTIAL", Const, 0}, - {"MADV_SPACEAVAIL", Const, 3}, - {"MADV_UNMERGEABLE", Const, 0}, - {"MADV_WILLNEED", Const, 0}, - {"MADV_ZERO_WIRED_PAGES", Const, 0}, - {"MAP_32BIT", Const, 0}, - {"MAP_ALIGNED_SUPER", Const, 3}, - {"MAP_ALIGNMENT_16MB", Const, 3}, - {"MAP_ALIGNMENT_1TB", Const, 3}, - {"MAP_ALIGNMENT_256TB", Const, 3}, - {"MAP_ALIGNMENT_4GB", Const, 3}, - {"MAP_ALIGNMENT_64KB", Const, 3}, - {"MAP_ALIGNMENT_64PB", Const, 3}, - {"MAP_ALIGNMENT_MASK", Const, 3}, - {"MAP_ALIGNMENT_SHIFT", Const, 3}, - {"MAP_ANON", Const, 0}, - {"MAP_ANONYMOUS", Const, 0}, - {"MAP_COPY", Const, 0}, - {"MAP_DENYWRITE", Const, 0}, - {"MAP_EXECUTABLE", Const, 0}, - {"MAP_FILE", Const, 0}, - {"MAP_FIXED", Const, 0}, - {"MAP_FLAGMASK", Const, 3}, - {"MAP_GROWSDOWN", Const, 0}, - {"MAP_HASSEMAPHORE", Const, 0}, - {"MAP_HUGETLB", Const, 0}, - {"MAP_INHERIT", Const, 3}, - {"MAP_INHERIT_COPY", Const, 3}, - {"MAP_INHERIT_DEFAULT", Const, 3}, - {"MAP_INHERIT_DONATE_COPY", Const, 3}, - {"MAP_INHERIT_NONE", Const, 3}, - {"MAP_INHERIT_SHARE", Const, 3}, - {"MAP_JIT", Const, 0}, - {"MAP_LOCKED", Const, 0}, - {"MAP_NOCACHE", Const, 0}, - {"MAP_NOCORE", Const, 1}, - {"MAP_NOEXTEND", Const, 0}, - {"MAP_NONBLOCK", Const, 0}, - {"MAP_NORESERVE", Const, 0}, - {"MAP_NOSYNC", Const, 1}, - {"MAP_POPULATE", Const, 0}, - {"MAP_PREFAULT_READ", Const, 1}, - {"MAP_PRIVATE", Const, 0}, - {"MAP_RENAME", Const, 0}, - {"MAP_RESERVED0080", Const, 0}, - {"MAP_RESERVED0100", Const, 1}, - {"MAP_SHARED", Const, 0}, - {"MAP_STACK", Const, 0}, - {"MAP_TRYFIXED", Const, 3}, - {"MAP_TYPE", Const, 0}, - {"MAP_WIRED", Const, 3}, - {"MAXIMUM_REPARSE_DATA_BUFFER_SIZE", Const, 4}, - {"MAXLEN_IFDESCR", Const, 0}, - {"MAXLEN_PHYSADDR", Const, 0}, - {"MAX_ADAPTER_ADDRESS_LENGTH", Const, 0}, - {"MAX_ADAPTER_DESCRIPTION_LENGTH", Const, 0}, - {"MAX_ADAPTER_NAME_LENGTH", Const, 0}, - {"MAX_COMPUTERNAME_LENGTH", Const, 0}, - {"MAX_INTERFACE_NAME_LEN", Const, 0}, - {"MAX_LONG_PATH", Const, 0}, - {"MAX_PATH", Const, 0}, - {"MAX_PROTOCOL_CHAIN", Const, 2}, - {"MCL_CURRENT", Const, 0}, - {"MCL_FUTURE", Const, 0}, - {"MNT_DETACH", Const, 0}, - {"MNT_EXPIRE", Const, 0}, - {"MNT_FORCE", Const, 0}, - {"MSG_BCAST", Const, 1}, - {"MSG_CMSG_CLOEXEC", Const, 0}, - {"MSG_COMPAT", Const, 0}, - {"MSG_CONFIRM", Const, 0}, - {"MSG_CONTROLMBUF", Const, 1}, - {"MSG_CTRUNC", Const, 0}, - {"MSG_DONTROUTE", Const, 0}, - {"MSG_DONTWAIT", Const, 0}, - {"MSG_EOF", Const, 0}, - {"MSG_EOR", Const, 0}, - {"MSG_ERRQUEUE", Const, 0}, - {"MSG_FASTOPEN", Const, 1}, - {"MSG_FIN", Const, 0}, - {"MSG_FLUSH", Const, 0}, - {"MSG_HAVEMORE", Const, 0}, - {"MSG_HOLD", Const, 0}, - {"MSG_IOVUSRSPACE", Const, 1}, - {"MSG_LENUSRSPACE", Const, 1}, - {"MSG_MCAST", Const, 1}, - {"MSG_MORE", Const, 0}, - {"MSG_NAMEMBUF", Const, 1}, - {"MSG_NBIO", Const, 0}, - {"MSG_NEEDSA", Const, 0}, - {"MSG_NOSIGNAL", Const, 0}, - {"MSG_NOTIFICATION", Const, 0}, - {"MSG_OOB", Const, 0}, - {"MSG_PEEK", Const, 0}, - {"MSG_PROXY", Const, 0}, - {"MSG_RCVMORE", Const, 0}, - {"MSG_RST", Const, 0}, - {"MSG_SEND", Const, 0}, - {"MSG_SYN", Const, 0}, - {"MSG_TRUNC", Const, 0}, - {"MSG_TRYHARD", Const, 0}, - {"MSG_USERFLAGS", Const, 1}, - {"MSG_WAITALL", Const, 0}, - {"MSG_WAITFORONE", Const, 0}, - {"MSG_WAITSTREAM", Const, 0}, - {"MS_ACTIVE", Const, 0}, - {"MS_ASYNC", Const, 0}, - {"MS_BIND", Const, 0}, - {"MS_DEACTIVATE", Const, 0}, - {"MS_DIRSYNC", Const, 0}, - {"MS_INVALIDATE", Const, 0}, - {"MS_I_VERSION", Const, 0}, - {"MS_KERNMOUNT", Const, 0}, - {"MS_KILLPAGES", Const, 0}, - {"MS_MANDLOCK", Const, 0}, - {"MS_MGC_MSK", Const, 0}, - {"MS_MGC_VAL", Const, 0}, - {"MS_MOVE", Const, 0}, - {"MS_NOATIME", Const, 0}, - {"MS_NODEV", Const, 0}, - {"MS_NODIRATIME", Const, 0}, - {"MS_NOEXEC", Const, 0}, - {"MS_NOSUID", Const, 0}, - {"MS_NOUSER", Const, 0}, - {"MS_POSIXACL", Const, 0}, - {"MS_PRIVATE", Const, 0}, - {"MS_RDONLY", Const, 0}, - {"MS_REC", Const, 0}, - {"MS_RELATIME", Const, 0}, - {"MS_REMOUNT", Const, 0}, - {"MS_RMT_MASK", Const, 0}, - {"MS_SHARED", Const, 0}, - {"MS_SILENT", Const, 0}, - {"MS_SLAVE", Const, 0}, - {"MS_STRICTATIME", Const, 0}, - {"MS_SYNC", Const, 0}, - {"MS_SYNCHRONOUS", Const, 0}, - {"MS_UNBINDABLE", Const, 0}, - {"Madvise", Func, 0}, - {"MapViewOfFile", Func, 0}, - {"MaxTokenInfoClass", Const, 0}, - {"Mclpool", Type, 2}, - {"Mclpool.Alive", Field, 2}, - {"Mclpool.Cwm", Field, 2}, - {"Mclpool.Grown", Field, 2}, - {"Mclpool.Hwm", Field, 2}, - {"Mclpool.Lwm", Field, 2}, - {"MibIfRow", Type, 0}, - {"MibIfRow.AdminStatus", Field, 0}, - {"MibIfRow.Descr", Field, 0}, - {"MibIfRow.DescrLen", Field, 0}, - {"MibIfRow.InDiscards", Field, 0}, - {"MibIfRow.InErrors", Field, 0}, - {"MibIfRow.InNUcastPkts", Field, 0}, - {"MibIfRow.InOctets", Field, 0}, - {"MibIfRow.InUcastPkts", Field, 0}, - {"MibIfRow.InUnknownProtos", Field, 0}, - {"MibIfRow.Index", Field, 0}, - {"MibIfRow.LastChange", Field, 0}, - {"MibIfRow.Mtu", Field, 0}, - {"MibIfRow.Name", Field, 0}, - {"MibIfRow.OperStatus", Field, 0}, - {"MibIfRow.OutDiscards", Field, 0}, - {"MibIfRow.OutErrors", Field, 0}, - {"MibIfRow.OutNUcastPkts", Field, 0}, - {"MibIfRow.OutOctets", Field, 0}, - {"MibIfRow.OutQLen", Field, 0}, - {"MibIfRow.OutUcastPkts", Field, 0}, - {"MibIfRow.PhysAddr", Field, 0}, - {"MibIfRow.PhysAddrLen", Field, 0}, - {"MibIfRow.Speed", Field, 0}, - {"MibIfRow.Type", Field, 0}, - {"Mkdir", Func, 0}, - {"Mkdirat", Func, 0}, - {"Mkfifo", Func, 0}, - {"Mknod", Func, 0}, - {"Mknodat", Func, 0}, - {"Mlock", Func, 0}, - {"Mlockall", Func, 0}, - {"Mmap", Func, 0}, - {"Mount", Func, 0}, - {"MoveFile", Func, 0}, - {"Mprotect", Func, 0}, - {"Msghdr", Type, 0}, - {"Msghdr.Control", Field, 0}, - {"Msghdr.Controllen", Field, 0}, - {"Msghdr.Flags", Field, 0}, - {"Msghdr.Iov", Field, 0}, - {"Msghdr.Iovlen", Field, 0}, - {"Msghdr.Name", Field, 0}, - {"Msghdr.Namelen", Field, 0}, - {"Msghdr.Pad_cgo_0", Field, 0}, - {"Msghdr.Pad_cgo_1", Field, 0}, - {"Munlock", Func, 0}, - {"Munlockall", Func, 0}, - {"Munmap", Func, 0}, - {"MustLoadDLL", Func, 0}, - {"NAME_MAX", Const, 0}, - {"NETLINK_ADD_MEMBERSHIP", Const, 0}, - {"NETLINK_AUDIT", Const, 0}, - {"NETLINK_BROADCAST_ERROR", Const, 0}, - {"NETLINK_CONNECTOR", Const, 0}, - {"NETLINK_DNRTMSG", Const, 0}, - {"NETLINK_DROP_MEMBERSHIP", Const, 0}, - {"NETLINK_ECRYPTFS", Const, 0}, - {"NETLINK_FIB_LOOKUP", Const, 0}, - {"NETLINK_FIREWALL", Const, 0}, - {"NETLINK_GENERIC", Const, 0}, - {"NETLINK_INET_DIAG", Const, 0}, - {"NETLINK_IP6_FW", Const, 0}, - {"NETLINK_ISCSI", Const, 0}, - {"NETLINK_KOBJECT_UEVENT", Const, 0}, - {"NETLINK_NETFILTER", Const, 0}, - {"NETLINK_NFLOG", Const, 0}, - {"NETLINK_NO_ENOBUFS", Const, 0}, - {"NETLINK_PKTINFO", Const, 0}, - {"NETLINK_RDMA", Const, 0}, - {"NETLINK_ROUTE", Const, 0}, - {"NETLINK_SCSITRANSPORT", Const, 0}, - {"NETLINK_SELINUX", Const, 0}, - {"NETLINK_UNUSED", Const, 0}, - {"NETLINK_USERSOCK", Const, 0}, - {"NETLINK_XFRM", Const, 0}, - {"NET_RT_DUMP", Const, 0}, - {"NET_RT_DUMP2", Const, 0}, - {"NET_RT_FLAGS", Const, 0}, - {"NET_RT_IFLIST", Const, 0}, - {"NET_RT_IFLIST2", Const, 0}, - {"NET_RT_IFLISTL", Const, 1}, - {"NET_RT_IFMALIST", Const, 0}, - {"NET_RT_MAXID", Const, 0}, - {"NET_RT_OIFLIST", Const, 1}, - {"NET_RT_OOIFLIST", Const, 1}, - {"NET_RT_STAT", Const, 0}, - {"NET_RT_STATS", Const, 1}, - {"NET_RT_TABLE", Const, 1}, - {"NET_RT_TRASH", Const, 0}, - {"NLA_ALIGNTO", Const, 0}, - {"NLA_F_NESTED", Const, 0}, - {"NLA_F_NET_BYTEORDER", Const, 0}, - {"NLA_HDRLEN", Const, 0}, - {"NLMSG_ALIGNTO", Const, 0}, - {"NLMSG_DONE", Const, 0}, - {"NLMSG_ERROR", Const, 0}, - {"NLMSG_HDRLEN", Const, 0}, - {"NLMSG_MIN_TYPE", Const, 0}, - {"NLMSG_NOOP", Const, 0}, - {"NLMSG_OVERRUN", Const, 0}, - {"NLM_F_ACK", Const, 0}, - {"NLM_F_APPEND", Const, 0}, - {"NLM_F_ATOMIC", Const, 0}, - {"NLM_F_CREATE", Const, 0}, - {"NLM_F_DUMP", Const, 0}, - {"NLM_F_ECHO", Const, 0}, - {"NLM_F_EXCL", Const, 0}, - {"NLM_F_MATCH", Const, 0}, - {"NLM_F_MULTI", Const, 0}, - {"NLM_F_REPLACE", Const, 0}, - {"NLM_F_REQUEST", Const, 0}, - {"NLM_F_ROOT", Const, 0}, - {"NOFLSH", Const, 0}, - {"NOTE_ABSOLUTE", Const, 0}, - {"NOTE_ATTRIB", Const, 0}, - {"NOTE_BACKGROUND", Const, 16}, - {"NOTE_CHILD", Const, 0}, - {"NOTE_CRITICAL", Const, 16}, - {"NOTE_DELETE", Const, 0}, - {"NOTE_EOF", Const, 1}, - {"NOTE_EXEC", Const, 0}, - {"NOTE_EXIT", Const, 0}, - {"NOTE_EXITSTATUS", Const, 0}, - {"NOTE_EXIT_CSERROR", Const, 16}, - {"NOTE_EXIT_DECRYPTFAIL", Const, 16}, - {"NOTE_EXIT_DETAIL", Const, 16}, - {"NOTE_EXIT_DETAIL_MASK", Const, 16}, - {"NOTE_EXIT_MEMORY", Const, 16}, - {"NOTE_EXIT_REPARENTED", Const, 16}, - {"NOTE_EXTEND", Const, 0}, - {"NOTE_FFAND", Const, 0}, - {"NOTE_FFCOPY", Const, 0}, - {"NOTE_FFCTRLMASK", Const, 0}, - {"NOTE_FFLAGSMASK", Const, 0}, - {"NOTE_FFNOP", Const, 0}, - {"NOTE_FFOR", Const, 0}, - {"NOTE_FORK", Const, 0}, - {"NOTE_LEEWAY", Const, 16}, - {"NOTE_LINK", Const, 0}, - {"NOTE_LOWAT", Const, 0}, - {"NOTE_NONE", Const, 0}, - {"NOTE_NSECONDS", Const, 0}, - {"NOTE_PCTRLMASK", Const, 0}, - {"NOTE_PDATAMASK", Const, 0}, - {"NOTE_REAP", Const, 0}, - {"NOTE_RENAME", Const, 0}, - {"NOTE_RESOURCEEND", Const, 0}, - {"NOTE_REVOKE", Const, 0}, - {"NOTE_SECONDS", Const, 0}, - {"NOTE_SIGNAL", Const, 0}, - {"NOTE_TRACK", Const, 0}, - {"NOTE_TRACKERR", Const, 0}, - {"NOTE_TRIGGER", Const, 0}, - {"NOTE_TRUNCATE", Const, 1}, - {"NOTE_USECONDS", Const, 0}, - {"NOTE_VM_ERROR", Const, 0}, - {"NOTE_VM_PRESSURE", Const, 0}, - {"NOTE_VM_PRESSURE_SUDDEN_TERMINATE", Const, 0}, - {"NOTE_VM_PRESSURE_TERMINATE", Const, 0}, - {"NOTE_WRITE", Const, 0}, - {"NameCanonical", Const, 0}, - {"NameCanonicalEx", Const, 0}, - {"NameDisplay", Const, 0}, - {"NameDnsDomain", Const, 0}, - {"NameFullyQualifiedDN", Const, 0}, - {"NameSamCompatible", Const, 0}, - {"NameServicePrincipal", Const, 0}, - {"NameUniqueId", Const, 0}, - {"NameUnknown", Const, 0}, - {"NameUserPrincipal", Const, 0}, - {"Nanosleep", Func, 0}, - {"NetApiBufferFree", Func, 0}, - {"NetGetJoinInformation", Func, 2}, - {"NetSetupDomainName", Const, 2}, - {"NetSetupUnjoined", Const, 2}, - {"NetSetupUnknownStatus", Const, 2}, - {"NetSetupWorkgroupName", Const, 2}, - {"NetUserGetInfo", Func, 0}, - {"NetlinkMessage", Type, 0}, - {"NetlinkMessage.Data", Field, 0}, - {"NetlinkMessage.Header", Field, 0}, - {"NetlinkRIB", Func, 0}, - {"NetlinkRouteAttr", Type, 0}, - {"NetlinkRouteAttr.Attr", Field, 0}, - {"NetlinkRouteAttr.Value", Field, 0}, - {"NetlinkRouteRequest", Type, 0}, - {"NetlinkRouteRequest.Data", Field, 0}, - {"NetlinkRouteRequest.Header", Field, 0}, - {"NewCallback", Func, 0}, - {"NewCallbackCDecl", Func, 3}, - {"NewLazyDLL", Func, 0}, - {"NlAttr", Type, 0}, - {"NlAttr.Len", Field, 0}, - {"NlAttr.Type", Field, 0}, - {"NlMsgerr", Type, 0}, - {"NlMsgerr.Error", Field, 0}, - {"NlMsgerr.Msg", Field, 0}, - {"NlMsghdr", Type, 0}, - {"NlMsghdr.Flags", Field, 0}, - {"NlMsghdr.Len", Field, 0}, - {"NlMsghdr.Pid", Field, 0}, - {"NlMsghdr.Seq", Field, 0}, - {"NlMsghdr.Type", Field, 0}, - {"NsecToFiletime", Func, 0}, - {"NsecToTimespec", Func, 0}, - {"NsecToTimeval", Func, 0}, - {"Ntohs", Func, 0}, - {"OCRNL", Const, 0}, - {"OFDEL", Const, 0}, - {"OFILL", Const, 0}, - {"OFIOGETBMAP", Const, 1}, - {"OID_PKIX_KP_SERVER_AUTH", Var, 0}, - {"OID_SERVER_GATED_CRYPTO", Var, 0}, - {"OID_SGC_NETSCAPE", Var, 0}, - {"OLCUC", Const, 0}, - {"ONLCR", Const, 0}, - {"ONLRET", Const, 0}, - {"ONOCR", Const, 0}, - {"ONOEOT", Const, 1}, - {"OPEN_ALWAYS", Const, 0}, - {"OPEN_EXISTING", Const, 0}, - {"OPOST", Const, 0}, - {"O_ACCMODE", Const, 0}, - {"O_ALERT", Const, 0}, - {"O_ALT_IO", Const, 1}, - {"O_APPEND", Const, 0}, - {"O_ASYNC", Const, 0}, - {"O_CLOEXEC", Const, 0}, - {"O_CREAT", Const, 0}, - {"O_DIRECT", Const, 0}, - {"O_DIRECTORY", Const, 0}, - {"O_DP_GETRAWENCRYPTED", Const, 16}, - {"O_DSYNC", Const, 0}, - {"O_EVTONLY", Const, 0}, - {"O_EXCL", Const, 0}, - {"O_EXEC", Const, 0}, - {"O_EXLOCK", Const, 0}, - {"O_FSYNC", Const, 0}, - {"O_LARGEFILE", Const, 0}, - {"O_NDELAY", Const, 0}, - {"O_NOATIME", Const, 0}, - {"O_NOCTTY", Const, 0}, - {"O_NOFOLLOW", Const, 0}, - {"O_NONBLOCK", Const, 0}, - {"O_NOSIGPIPE", Const, 1}, - {"O_POPUP", Const, 0}, - {"O_RDONLY", Const, 0}, - {"O_RDWR", Const, 0}, - {"O_RSYNC", Const, 0}, - {"O_SHLOCK", Const, 0}, - {"O_SYMLINK", Const, 0}, - {"O_SYNC", Const, 0}, - {"O_TRUNC", Const, 0}, - {"O_TTY_INIT", Const, 0}, - {"O_WRONLY", Const, 0}, - {"Open", Func, 0}, - {"OpenCurrentProcessToken", Func, 0}, - {"OpenProcess", Func, 0}, - {"OpenProcessToken", Func, 0}, - {"Openat", Func, 0}, - {"Overlapped", Type, 0}, - {"Overlapped.HEvent", Field, 0}, - {"Overlapped.Internal", Field, 0}, - {"Overlapped.InternalHigh", Field, 0}, - {"Overlapped.Offset", Field, 0}, - {"Overlapped.OffsetHigh", Field, 0}, - {"PACKET_ADD_MEMBERSHIP", Const, 0}, - {"PACKET_BROADCAST", Const, 0}, - {"PACKET_DROP_MEMBERSHIP", Const, 0}, - {"PACKET_FASTROUTE", Const, 0}, - {"PACKET_HOST", Const, 0}, - {"PACKET_LOOPBACK", Const, 0}, - {"PACKET_MR_ALLMULTI", Const, 0}, - {"PACKET_MR_MULTICAST", Const, 0}, - {"PACKET_MR_PROMISC", Const, 0}, - {"PACKET_MULTICAST", Const, 0}, - {"PACKET_OTHERHOST", Const, 0}, - {"PACKET_OUTGOING", Const, 0}, - {"PACKET_RECV_OUTPUT", Const, 0}, - {"PACKET_RX_RING", Const, 0}, - {"PACKET_STATISTICS", Const, 0}, - {"PAGE_EXECUTE_READ", Const, 0}, - {"PAGE_EXECUTE_READWRITE", Const, 0}, - {"PAGE_EXECUTE_WRITECOPY", Const, 0}, - {"PAGE_READONLY", Const, 0}, - {"PAGE_READWRITE", Const, 0}, - {"PAGE_WRITECOPY", Const, 0}, - {"PARENB", Const, 0}, - {"PARMRK", Const, 0}, - {"PARODD", Const, 0}, - {"PENDIN", Const, 0}, - {"PFL_HIDDEN", Const, 2}, - {"PFL_MATCHES_PROTOCOL_ZERO", Const, 2}, - {"PFL_MULTIPLE_PROTO_ENTRIES", Const, 2}, - {"PFL_NETWORKDIRECT_PROVIDER", Const, 2}, - {"PFL_RECOMMENDED_PROTO_ENTRY", Const, 2}, - {"PF_FLUSH", Const, 1}, - {"PKCS_7_ASN_ENCODING", Const, 0}, - {"PMC5_PIPELINE_FLUSH", Const, 1}, - {"PRIO_PGRP", Const, 2}, - {"PRIO_PROCESS", Const, 2}, - {"PRIO_USER", Const, 2}, - {"PRI_IOFLUSH", Const, 1}, - {"PROCESS_QUERY_INFORMATION", Const, 0}, - {"PROCESS_TERMINATE", Const, 2}, - {"PROT_EXEC", Const, 0}, - {"PROT_GROWSDOWN", Const, 0}, - {"PROT_GROWSUP", Const, 0}, - {"PROT_NONE", Const, 0}, - {"PROT_READ", Const, 0}, - {"PROT_WRITE", Const, 0}, - {"PROV_DH_SCHANNEL", Const, 0}, - {"PROV_DSS", Const, 0}, - {"PROV_DSS_DH", Const, 0}, - {"PROV_EC_ECDSA_FULL", Const, 0}, - {"PROV_EC_ECDSA_SIG", Const, 0}, - {"PROV_EC_ECNRA_FULL", Const, 0}, - {"PROV_EC_ECNRA_SIG", Const, 0}, - {"PROV_FORTEZZA", Const, 0}, - {"PROV_INTEL_SEC", Const, 0}, - {"PROV_MS_EXCHANGE", Const, 0}, - {"PROV_REPLACE_OWF", Const, 0}, - {"PROV_RNG", Const, 0}, - {"PROV_RSA_AES", Const, 0}, - {"PROV_RSA_FULL", Const, 0}, - {"PROV_RSA_SCHANNEL", Const, 0}, - {"PROV_RSA_SIG", Const, 0}, - {"PROV_SPYRUS_LYNKS", Const, 0}, - {"PROV_SSL", Const, 0}, - {"PR_CAPBSET_DROP", Const, 0}, - {"PR_CAPBSET_READ", Const, 0}, - {"PR_CLEAR_SECCOMP_FILTER", Const, 0}, - {"PR_ENDIAN_BIG", Const, 0}, - {"PR_ENDIAN_LITTLE", Const, 0}, - {"PR_ENDIAN_PPC_LITTLE", Const, 0}, - {"PR_FPEMU_NOPRINT", Const, 0}, - {"PR_FPEMU_SIGFPE", Const, 0}, - {"PR_FP_EXC_ASYNC", Const, 0}, - {"PR_FP_EXC_DISABLED", Const, 0}, - {"PR_FP_EXC_DIV", Const, 0}, - {"PR_FP_EXC_INV", Const, 0}, - {"PR_FP_EXC_NONRECOV", Const, 0}, - {"PR_FP_EXC_OVF", Const, 0}, - {"PR_FP_EXC_PRECISE", Const, 0}, - {"PR_FP_EXC_RES", Const, 0}, - {"PR_FP_EXC_SW_ENABLE", Const, 0}, - {"PR_FP_EXC_UND", Const, 0}, - {"PR_GET_DUMPABLE", Const, 0}, - {"PR_GET_ENDIAN", Const, 0}, - {"PR_GET_FPEMU", Const, 0}, - {"PR_GET_FPEXC", Const, 0}, - {"PR_GET_KEEPCAPS", Const, 0}, - {"PR_GET_NAME", Const, 0}, - {"PR_GET_PDEATHSIG", Const, 0}, - {"PR_GET_SECCOMP", Const, 0}, - {"PR_GET_SECCOMP_FILTER", Const, 0}, - {"PR_GET_SECUREBITS", Const, 0}, - {"PR_GET_TIMERSLACK", Const, 0}, - {"PR_GET_TIMING", Const, 0}, - {"PR_GET_TSC", Const, 0}, - {"PR_GET_UNALIGN", Const, 0}, - {"PR_MCE_KILL", Const, 0}, - {"PR_MCE_KILL_CLEAR", Const, 0}, - {"PR_MCE_KILL_DEFAULT", Const, 0}, - {"PR_MCE_KILL_EARLY", Const, 0}, - {"PR_MCE_KILL_GET", Const, 0}, - {"PR_MCE_KILL_LATE", Const, 0}, - {"PR_MCE_KILL_SET", Const, 0}, - {"PR_SECCOMP_FILTER_EVENT", Const, 0}, - {"PR_SECCOMP_FILTER_SYSCALL", Const, 0}, - {"PR_SET_DUMPABLE", Const, 0}, - {"PR_SET_ENDIAN", Const, 0}, - {"PR_SET_FPEMU", Const, 0}, - {"PR_SET_FPEXC", Const, 0}, - {"PR_SET_KEEPCAPS", Const, 0}, - {"PR_SET_NAME", Const, 0}, - {"PR_SET_PDEATHSIG", Const, 0}, - {"PR_SET_PTRACER", Const, 0}, - {"PR_SET_SECCOMP", Const, 0}, - {"PR_SET_SECCOMP_FILTER", Const, 0}, - {"PR_SET_SECUREBITS", Const, 0}, - {"PR_SET_TIMERSLACK", Const, 0}, - {"PR_SET_TIMING", Const, 0}, - {"PR_SET_TSC", Const, 0}, - {"PR_SET_UNALIGN", Const, 0}, - {"PR_TASK_PERF_EVENTS_DISABLE", Const, 0}, - {"PR_TASK_PERF_EVENTS_ENABLE", Const, 0}, - {"PR_TIMING_STATISTICAL", Const, 0}, - {"PR_TIMING_TIMESTAMP", Const, 0}, - {"PR_TSC_ENABLE", Const, 0}, - {"PR_TSC_SIGSEGV", Const, 0}, - {"PR_UNALIGN_NOPRINT", Const, 0}, - {"PR_UNALIGN_SIGBUS", Const, 0}, - {"PTRACE_ARCH_PRCTL", Const, 0}, - {"PTRACE_ATTACH", Const, 0}, - {"PTRACE_CONT", Const, 0}, - {"PTRACE_DETACH", Const, 0}, - {"PTRACE_EVENT_CLONE", Const, 0}, - {"PTRACE_EVENT_EXEC", Const, 0}, - {"PTRACE_EVENT_EXIT", Const, 0}, - {"PTRACE_EVENT_FORK", Const, 0}, - {"PTRACE_EVENT_VFORK", Const, 0}, - {"PTRACE_EVENT_VFORK_DONE", Const, 0}, - {"PTRACE_GETCRUNCHREGS", Const, 0}, - {"PTRACE_GETEVENTMSG", Const, 0}, - {"PTRACE_GETFPREGS", Const, 0}, - {"PTRACE_GETFPXREGS", Const, 0}, - {"PTRACE_GETHBPREGS", Const, 0}, - {"PTRACE_GETREGS", Const, 0}, - {"PTRACE_GETREGSET", Const, 0}, - {"PTRACE_GETSIGINFO", Const, 0}, - {"PTRACE_GETVFPREGS", Const, 0}, - {"PTRACE_GETWMMXREGS", Const, 0}, - {"PTRACE_GET_THREAD_AREA", Const, 0}, - {"PTRACE_KILL", Const, 0}, - {"PTRACE_OLDSETOPTIONS", Const, 0}, - {"PTRACE_O_MASK", Const, 0}, - {"PTRACE_O_TRACECLONE", Const, 0}, - {"PTRACE_O_TRACEEXEC", Const, 0}, - {"PTRACE_O_TRACEEXIT", Const, 0}, - {"PTRACE_O_TRACEFORK", Const, 0}, - {"PTRACE_O_TRACESYSGOOD", Const, 0}, - {"PTRACE_O_TRACEVFORK", Const, 0}, - {"PTRACE_O_TRACEVFORKDONE", Const, 0}, - {"PTRACE_PEEKDATA", Const, 0}, - {"PTRACE_PEEKTEXT", Const, 0}, - {"PTRACE_PEEKUSR", Const, 0}, - {"PTRACE_POKEDATA", Const, 0}, - {"PTRACE_POKETEXT", Const, 0}, - {"PTRACE_POKEUSR", Const, 0}, - {"PTRACE_SETCRUNCHREGS", Const, 0}, - {"PTRACE_SETFPREGS", Const, 0}, - {"PTRACE_SETFPXREGS", Const, 0}, - {"PTRACE_SETHBPREGS", Const, 0}, - {"PTRACE_SETOPTIONS", Const, 0}, - {"PTRACE_SETREGS", Const, 0}, - {"PTRACE_SETREGSET", Const, 0}, - {"PTRACE_SETSIGINFO", Const, 0}, - {"PTRACE_SETVFPREGS", Const, 0}, - {"PTRACE_SETWMMXREGS", Const, 0}, - {"PTRACE_SET_SYSCALL", Const, 0}, - {"PTRACE_SET_THREAD_AREA", Const, 0}, - {"PTRACE_SINGLEBLOCK", Const, 0}, - {"PTRACE_SINGLESTEP", Const, 0}, - {"PTRACE_SYSCALL", Const, 0}, - {"PTRACE_SYSEMU", Const, 0}, - {"PTRACE_SYSEMU_SINGLESTEP", Const, 0}, - {"PTRACE_TRACEME", Const, 0}, - {"PT_ATTACH", Const, 0}, - {"PT_ATTACHEXC", Const, 0}, - {"PT_CONTINUE", Const, 0}, - {"PT_DATA_ADDR", Const, 0}, - {"PT_DENY_ATTACH", Const, 0}, - {"PT_DETACH", Const, 0}, - {"PT_FIRSTMACH", Const, 0}, - {"PT_FORCEQUOTA", Const, 0}, - {"PT_KILL", Const, 0}, - {"PT_MASK", Const, 1}, - {"PT_READ_D", Const, 0}, - {"PT_READ_I", Const, 0}, - {"PT_READ_U", Const, 0}, - {"PT_SIGEXC", Const, 0}, - {"PT_STEP", Const, 0}, - {"PT_TEXT_ADDR", Const, 0}, - {"PT_TEXT_END_ADDR", Const, 0}, - {"PT_THUPDATE", Const, 0}, - {"PT_TRACE_ME", Const, 0}, - {"PT_WRITE_D", Const, 0}, - {"PT_WRITE_I", Const, 0}, - {"PT_WRITE_U", Const, 0}, - {"ParseDirent", Func, 0}, - {"ParseNetlinkMessage", Func, 0}, - {"ParseNetlinkRouteAttr", Func, 0}, - {"ParseRoutingMessage", Func, 0}, - {"ParseRoutingSockaddr", Func, 0}, - {"ParseSocketControlMessage", Func, 0}, - {"ParseUnixCredentials", Func, 0}, - {"ParseUnixRights", Func, 0}, - {"PathMax", Const, 0}, - {"Pathconf", Func, 0}, - {"Pause", Func, 0}, - {"Pipe", Func, 0}, - {"Pipe2", Func, 1}, - {"PivotRoot", Func, 0}, - {"Pointer", Type, 11}, - {"PostQueuedCompletionStatus", Func, 0}, - {"Pread", Func, 0}, - {"Proc", Type, 0}, - {"Proc.Dll", Field, 0}, - {"Proc.Name", Field, 0}, - {"ProcAttr", Type, 0}, - {"ProcAttr.Dir", Field, 0}, - {"ProcAttr.Env", Field, 0}, - {"ProcAttr.Files", Field, 0}, - {"ProcAttr.Sys", Field, 0}, - {"Process32First", Func, 4}, - {"Process32Next", Func, 4}, - {"ProcessEntry32", Type, 4}, - {"ProcessEntry32.DefaultHeapID", Field, 4}, - {"ProcessEntry32.ExeFile", Field, 4}, - {"ProcessEntry32.Flags", Field, 4}, - {"ProcessEntry32.ModuleID", Field, 4}, - {"ProcessEntry32.ParentProcessID", Field, 4}, - {"ProcessEntry32.PriClassBase", Field, 4}, - {"ProcessEntry32.ProcessID", Field, 4}, - {"ProcessEntry32.Size", Field, 4}, - {"ProcessEntry32.Threads", Field, 4}, - {"ProcessEntry32.Usage", Field, 4}, - {"ProcessInformation", Type, 0}, - {"ProcessInformation.Process", Field, 0}, - {"ProcessInformation.ProcessId", Field, 0}, - {"ProcessInformation.Thread", Field, 0}, - {"ProcessInformation.ThreadId", Field, 0}, - {"Protoent", Type, 0}, - {"Protoent.Aliases", Field, 0}, - {"Protoent.Name", Field, 0}, - {"Protoent.Proto", Field, 0}, - {"PtraceAttach", Func, 0}, - {"PtraceCont", Func, 0}, - {"PtraceDetach", Func, 0}, - {"PtraceGetEventMsg", Func, 0}, - {"PtraceGetRegs", Func, 0}, - {"PtracePeekData", Func, 0}, - {"PtracePeekText", Func, 0}, - {"PtracePokeData", Func, 0}, - {"PtracePokeText", Func, 0}, - {"PtraceRegs", Type, 0}, - {"PtraceRegs.Cs", Field, 0}, - {"PtraceRegs.Ds", Field, 0}, - {"PtraceRegs.Eax", Field, 0}, - {"PtraceRegs.Ebp", Field, 0}, - {"PtraceRegs.Ebx", Field, 0}, - {"PtraceRegs.Ecx", Field, 0}, - {"PtraceRegs.Edi", Field, 0}, - {"PtraceRegs.Edx", Field, 0}, - {"PtraceRegs.Eflags", Field, 0}, - {"PtraceRegs.Eip", Field, 0}, - {"PtraceRegs.Es", Field, 0}, - {"PtraceRegs.Esi", Field, 0}, - {"PtraceRegs.Esp", Field, 0}, - {"PtraceRegs.Fs", Field, 0}, - {"PtraceRegs.Fs_base", Field, 0}, - {"PtraceRegs.Gs", Field, 0}, - {"PtraceRegs.Gs_base", Field, 0}, - {"PtraceRegs.Orig_eax", Field, 0}, - {"PtraceRegs.Orig_rax", Field, 0}, - {"PtraceRegs.R10", Field, 0}, - {"PtraceRegs.R11", Field, 0}, - {"PtraceRegs.R12", Field, 0}, - {"PtraceRegs.R13", Field, 0}, - {"PtraceRegs.R14", Field, 0}, - {"PtraceRegs.R15", Field, 0}, - {"PtraceRegs.R8", Field, 0}, - {"PtraceRegs.R9", Field, 0}, - {"PtraceRegs.Rax", Field, 0}, - {"PtraceRegs.Rbp", Field, 0}, - {"PtraceRegs.Rbx", Field, 0}, - {"PtraceRegs.Rcx", Field, 0}, - {"PtraceRegs.Rdi", Field, 0}, - {"PtraceRegs.Rdx", Field, 0}, - {"PtraceRegs.Rip", Field, 0}, - {"PtraceRegs.Rsi", Field, 0}, - {"PtraceRegs.Rsp", Field, 0}, - {"PtraceRegs.Ss", Field, 0}, - {"PtraceRegs.Uregs", Field, 0}, - {"PtraceRegs.Xcs", Field, 0}, - {"PtraceRegs.Xds", Field, 0}, - {"PtraceRegs.Xes", Field, 0}, - {"PtraceRegs.Xfs", Field, 0}, - {"PtraceRegs.Xgs", Field, 0}, - {"PtraceRegs.Xss", Field, 0}, - {"PtraceSetOptions", Func, 0}, - {"PtraceSetRegs", Func, 0}, - {"PtraceSingleStep", Func, 0}, - {"PtraceSyscall", Func, 1}, - {"Pwrite", Func, 0}, - {"REG_BINARY", Const, 0}, - {"REG_DWORD", Const, 0}, - {"REG_DWORD_BIG_ENDIAN", Const, 0}, - {"REG_DWORD_LITTLE_ENDIAN", Const, 0}, - {"REG_EXPAND_SZ", Const, 0}, - {"REG_FULL_RESOURCE_DESCRIPTOR", Const, 0}, - {"REG_LINK", Const, 0}, - {"REG_MULTI_SZ", Const, 0}, - {"REG_NONE", Const, 0}, - {"REG_QWORD", Const, 0}, - {"REG_QWORD_LITTLE_ENDIAN", Const, 0}, - {"REG_RESOURCE_LIST", Const, 0}, - {"REG_RESOURCE_REQUIREMENTS_LIST", Const, 0}, - {"REG_SZ", Const, 0}, - {"RLIMIT_AS", Const, 0}, - {"RLIMIT_CORE", Const, 0}, - {"RLIMIT_CPU", Const, 0}, - {"RLIMIT_CPU_USAGE_MONITOR", Const, 16}, - {"RLIMIT_DATA", Const, 0}, - {"RLIMIT_FSIZE", Const, 0}, - {"RLIMIT_NOFILE", Const, 0}, - {"RLIMIT_STACK", Const, 0}, - {"RLIM_INFINITY", Const, 0}, - {"RTAX_ADVMSS", Const, 0}, - {"RTAX_AUTHOR", Const, 0}, - {"RTAX_BRD", Const, 0}, - {"RTAX_CWND", Const, 0}, - {"RTAX_DST", Const, 0}, - {"RTAX_FEATURES", Const, 0}, - {"RTAX_FEATURE_ALLFRAG", Const, 0}, - {"RTAX_FEATURE_ECN", Const, 0}, - {"RTAX_FEATURE_SACK", Const, 0}, - {"RTAX_FEATURE_TIMESTAMP", Const, 0}, - {"RTAX_GATEWAY", Const, 0}, - {"RTAX_GENMASK", Const, 0}, - {"RTAX_HOPLIMIT", Const, 0}, - {"RTAX_IFA", Const, 0}, - {"RTAX_IFP", Const, 0}, - {"RTAX_INITCWND", Const, 0}, - {"RTAX_INITRWND", Const, 0}, - {"RTAX_LABEL", Const, 1}, - {"RTAX_LOCK", Const, 0}, - {"RTAX_MAX", Const, 0}, - {"RTAX_MTU", Const, 0}, - {"RTAX_NETMASK", Const, 0}, - {"RTAX_REORDERING", Const, 0}, - {"RTAX_RTO_MIN", Const, 0}, - {"RTAX_RTT", Const, 0}, - {"RTAX_RTTVAR", Const, 0}, - {"RTAX_SRC", Const, 1}, - {"RTAX_SRCMASK", Const, 1}, - {"RTAX_SSTHRESH", Const, 0}, - {"RTAX_TAG", Const, 1}, - {"RTAX_UNSPEC", Const, 0}, - {"RTAX_WINDOW", Const, 0}, - {"RTA_ALIGNTO", Const, 0}, - {"RTA_AUTHOR", Const, 0}, - {"RTA_BRD", Const, 0}, - {"RTA_CACHEINFO", Const, 0}, - {"RTA_DST", Const, 0}, - {"RTA_FLOW", Const, 0}, - {"RTA_GATEWAY", Const, 0}, - {"RTA_GENMASK", Const, 0}, - {"RTA_IFA", Const, 0}, - {"RTA_IFP", Const, 0}, - {"RTA_IIF", Const, 0}, - {"RTA_LABEL", Const, 1}, - {"RTA_MAX", Const, 0}, - {"RTA_METRICS", Const, 0}, - {"RTA_MULTIPATH", Const, 0}, - {"RTA_NETMASK", Const, 0}, - {"RTA_OIF", Const, 0}, - {"RTA_PREFSRC", Const, 0}, - {"RTA_PRIORITY", Const, 0}, - {"RTA_SRC", Const, 0}, - {"RTA_SRCMASK", Const, 1}, - {"RTA_TABLE", Const, 0}, - {"RTA_TAG", Const, 1}, - {"RTA_UNSPEC", Const, 0}, - {"RTCF_DIRECTSRC", Const, 0}, - {"RTCF_DOREDIRECT", Const, 0}, - {"RTCF_LOG", Const, 0}, - {"RTCF_MASQ", Const, 0}, - {"RTCF_NAT", Const, 0}, - {"RTCF_VALVE", Const, 0}, - {"RTF_ADDRCLASSMASK", Const, 0}, - {"RTF_ADDRCONF", Const, 0}, - {"RTF_ALLONLINK", Const, 0}, - {"RTF_ANNOUNCE", Const, 1}, - {"RTF_BLACKHOLE", Const, 0}, - {"RTF_BROADCAST", Const, 0}, - {"RTF_CACHE", Const, 0}, - {"RTF_CLONED", Const, 1}, - {"RTF_CLONING", Const, 0}, - {"RTF_CONDEMNED", Const, 0}, - {"RTF_DEFAULT", Const, 0}, - {"RTF_DELCLONE", Const, 0}, - {"RTF_DONE", Const, 0}, - {"RTF_DYNAMIC", Const, 0}, - {"RTF_FLOW", Const, 0}, - {"RTF_FMASK", Const, 0}, - {"RTF_GATEWAY", Const, 0}, - {"RTF_GWFLAG_COMPAT", Const, 3}, - {"RTF_HOST", Const, 0}, - {"RTF_IFREF", Const, 0}, - {"RTF_IFSCOPE", Const, 0}, - {"RTF_INTERFACE", Const, 0}, - {"RTF_IRTT", Const, 0}, - {"RTF_LINKRT", Const, 0}, - {"RTF_LLDATA", Const, 0}, - {"RTF_LLINFO", Const, 0}, - {"RTF_LOCAL", Const, 0}, - {"RTF_MASK", Const, 1}, - {"RTF_MODIFIED", Const, 0}, - {"RTF_MPATH", Const, 1}, - {"RTF_MPLS", Const, 1}, - {"RTF_MSS", Const, 0}, - {"RTF_MTU", Const, 0}, - {"RTF_MULTICAST", Const, 0}, - {"RTF_NAT", Const, 0}, - {"RTF_NOFORWARD", Const, 0}, - {"RTF_NONEXTHOP", Const, 0}, - {"RTF_NOPMTUDISC", Const, 0}, - {"RTF_PERMANENT_ARP", Const, 1}, - {"RTF_PINNED", Const, 0}, - {"RTF_POLICY", Const, 0}, - {"RTF_PRCLONING", Const, 0}, - {"RTF_PROTO1", Const, 0}, - {"RTF_PROTO2", Const, 0}, - {"RTF_PROTO3", Const, 0}, - {"RTF_PROXY", Const, 16}, - {"RTF_REINSTATE", Const, 0}, - {"RTF_REJECT", Const, 0}, - {"RTF_RNH_LOCKED", Const, 0}, - {"RTF_ROUTER", Const, 16}, - {"RTF_SOURCE", Const, 1}, - {"RTF_SRC", Const, 1}, - {"RTF_STATIC", Const, 0}, - {"RTF_STICKY", Const, 0}, - {"RTF_THROW", Const, 0}, - {"RTF_TUNNEL", Const, 1}, - {"RTF_UP", Const, 0}, - {"RTF_USETRAILERS", Const, 1}, - {"RTF_WASCLONED", Const, 0}, - {"RTF_WINDOW", Const, 0}, - {"RTF_XRESOLVE", Const, 0}, - {"RTM_ADD", Const, 0}, - {"RTM_BASE", Const, 0}, - {"RTM_CHANGE", Const, 0}, - {"RTM_CHGADDR", Const, 1}, - {"RTM_DELACTION", Const, 0}, - {"RTM_DELADDR", Const, 0}, - {"RTM_DELADDRLABEL", Const, 0}, - {"RTM_DELETE", Const, 0}, - {"RTM_DELLINK", Const, 0}, - {"RTM_DELMADDR", Const, 0}, - {"RTM_DELNEIGH", Const, 0}, - {"RTM_DELQDISC", Const, 0}, - {"RTM_DELROUTE", Const, 0}, - {"RTM_DELRULE", Const, 0}, - {"RTM_DELTCLASS", Const, 0}, - {"RTM_DELTFILTER", Const, 0}, - {"RTM_DESYNC", Const, 1}, - {"RTM_F_CLONED", Const, 0}, - {"RTM_F_EQUALIZE", Const, 0}, - {"RTM_F_NOTIFY", Const, 0}, - {"RTM_F_PREFIX", Const, 0}, - {"RTM_GET", Const, 0}, - {"RTM_GET2", Const, 0}, - {"RTM_GETACTION", Const, 0}, - {"RTM_GETADDR", Const, 0}, - {"RTM_GETADDRLABEL", Const, 0}, - {"RTM_GETANYCAST", Const, 0}, - {"RTM_GETDCB", Const, 0}, - {"RTM_GETLINK", Const, 0}, - {"RTM_GETMULTICAST", Const, 0}, - {"RTM_GETNEIGH", Const, 0}, - {"RTM_GETNEIGHTBL", Const, 0}, - {"RTM_GETQDISC", Const, 0}, - {"RTM_GETROUTE", Const, 0}, - {"RTM_GETRULE", Const, 0}, - {"RTM_GETTCLASS", Const, 0}, - {"RTM_GETTFILTER", Const, 0}, - {"RTM_IEEE80211", Const, 0}, - {"RTM_IFANNOUNCE", Const, 0}, - {"RTM_IFINFO", Const, 0}, - {"RTM_IFINFO2", Const, 0}, - {"RTM_LLINFO_UPD", Const, 1}, - {"RTM_LOCK", Const, 0}, - {"RTM_LOSING", Const, 0}, - {"RTM_MAX", Const, 0}, - {"RTM_MAXSIZE", Const, 1}, - {"RTM_MISS", Const, 0}, - {"RTM_NEWACTION", Const, 0}, - {"RTM_NEWADDR", Const, 0}, - {"RTM_NEWADDRLABEL", Const, 0}, - {"RTM_NEWLINK", Const, 0}, - {"RTM_NEWMADDR", Const, 0}, - {"RTM_NEWMADDR2", Const, 0}, - {"RTM_NEWNDUSEROPT", Const, 0}, - {"RTM_NEWNEIGH", Const, 0}, - {"RTM_NEWNEIGHTBL", Const, 0}, - {"RTM_NEWPREFIX", Const, 0}, - {"RTM_NEWQDISC", Const, 0}, - {"RTM_NEWROUTE", Const, 0}, - {"RTM_NEWRULE", Const, 0}, - {"RTM_NEWTCLASS", Const, 0}, - {"RTM_NEWTFILTER", Const, 0}, - {"RTM_NR_FAMILIES", Const, 0}, - {"RTM_NR_MSGTYPES", Const, 0}, - {"RTM_OIFINFO", Const, 1}, - {"RTM_OLDADD", Const, 0}, - {"RTM_OLDDEL", Const, 0}, - {"RTM_OOIFINFO", Const, 1}, - {"RTM_REDIRECT", Const, 0}, - {"RTM_RESOLVE", Const, 0}, - {"RTM_RTTUNIT", Const, 0}, - {"RTM_SETDCB", Const, 0}, - {"RTM_SETGATE", Const, 1}, - {"RTM_SETLINK", Const, 0}, - {"RTM_SETNEIGHTBL", Const, 0}, - {"RTM_VERSION", Const, 0}, - {"RTNH_ALIGNTO", Const, 0}, - {"RTNH_F_DEAD", Const, 0}, - {"RTNH_F_ONLINK", Const, 0}, - {"RTNH_F_PERVASIVE", Const, 0}, - {"RTNLGRP_IPV4_IFADDR", Const, 1}, - {"RTNLGRP_IPV4_MROUTE", Const, 1}, - {"RTNLGRP_IPV4_ROUTE", Const, 1}, - {"RTNLGRP_IPV4_RULE", Const, 1}, - {"RTNLGRP_IPV6_IFADDR", Const, 1}, - {"RTNLGRP_IPV6_IFINFO", Const, 1}, - {"RTNLGRP_IPV6_MROUTE", Const, 1}, - {"RTNLGRP_IPV6_PREFIX", Const, 1}, - {"RTNLGRP_IPV6_ROUTE", Const, 1}, - {"RTNLGRP_IPV6_RULE", Const, 1}, - {"RTNLGRP_LINK", Const, 1}, - {"RTNLGRP_ND_USEROPT", Const, 1}, - {"RTNLGRP_NEIGH", Const, 1}, - {"RTNLGRP_NONE", Const, 1}, - {"RTNLGRP_NOTIFY", Const, 1}, - {"RTNLGRP_TC", Const, 1}, - {"RTN_ANYCAST", Const, 0}, - {"RTN_BLACKHOLE", Const, 0}, - {"RTN_BROADCAST", Const, 0}, - {"RTN_LOCAL", Const, 0}, - {"RTN_MAX", Const, 0}, - {"RTN_MULTICAST", Const, 0}, - {"RTN_NAT", Const, 0}, - {"RTN_PROHIBIT", Const, 0}, - {"RTN_THROW", Const, 0}, - {"RTN_UNICAST", Const, 0}, - {"RTN_UNREACHABLE", Const, 0}, - {"RTN_UNSPEC", Const, 0}, - {"RTN_XRESOLVE", Const, 0}, - {"RTPROT_BIRD", Const, 0}, - {"RTPROT_BOOT", Const, 0}, - {"RTPROT_DHCP", Const, 0}, - {"RTPROT_DNROUTED", Const, 0}, - {"RTPROT_GATED", Const, 0}, - {"RTPROT_KERNEL", Const, 0}, - {"RTPROT_MRT", Const, 0}, - {"RTPROT_NTK", Const, 0}, - {"RTPROT_RA", Const, 0}, - {"RTPROT_REDIRECT", Const, 0}, - {"RTPROT_STATIC", Const, 0}, - {"RTPROT_UNSPEC", Const, 0}, - {"RTPROT_XORP", Const, 0}, - {"RTPROT_ZEBRA", Const, 0}, - {"RTV_EXPIRE", Const, 0}, - {"RTV_HOPCOUNT", Const, 0}, - {"RTV_MTU", Const, 0}, - {"RTV_RPIPE", Const, 0}, - {"RTV_RTT", Const, 0}, - {"RTV_RTTVAR", Const, 0}, - {"RTV_SPIPE", Const, 0}, - {"RTV_SSTHRESH", Const, 0}, - {"RTV_WEIGHT", Const, 0}, - {"RT_CACHING_CONTEXT", Const, 1}, - {"RT_CLASS_DEFAULT", Const, 0}, - {"RT_CLASS_LOCAL", Const, 0}, - {"RT_CLASS_MAIN", Const, 0}, - {"RT_CLASS_MAX", Const, 0}, - {"RT_CLASS_UNSPEC", Const, 0}, - {"RT_DEFAULT_FIB", Const, 1}, - {"RT_NORTREF", Const, 1}, - {"RT_SCOPE_HOST", Const, 0}, - {"RT_SCOPE_LINK", Const, 0}, - {"RT_SCOPE_NOWHERE", Const, 0}, - {"RT_SCOPE_SITE", Const, 0}, - {"RT_SCOPE_UNIVERSE", Const, 0}, - {"RT_TABLEID_MAX", Const, 1}, - {"RT_TABLE_COMPAT", Const, 0}, - {"RT_TABLE_DEFAULT", Const, 0}, - {"RT_TABLE_LOCAL", Const, 0}, - {"RT_TABLE_MAIN", Const, 0}, - {"RT_TABLE_MAX", Const, 0}, - {"RT_TABLE_UNSPEC", Const, 0}, - {"RUSAGE_CHILDREN", Const, 0}, - {"RUSAGE_SELF", Const, 0}, - {"RUSAGE_THREAD", Const, 0}, - {"Radvisory_t", Type, 0}, - {"Radvisory_t.Count", Field, 0}, - {"Radvisory_t.Offset", Field, 0}, - {"Radvisory_t.Pad_cgo_0", Field, 0}, - {"RawConn", Type, 9}, - {"RawSockaddr", Type, 0}, - {"RawSockaddr.Data", Field, 0}, - {"RawSockaddr.Family", Field, 0}, - {"RawSockaddr.Len", Field, 0}, - {"RawSockaddrAny", Type, 0}, - {"RawSockaddrAny.Addr", Field, 0}, - {"RawSockaddrAny.Pad", Field, 0}, - {"RawSockaddrDatalink", Type, 0}, - {"RawSockaddrDatalink.Alen", Field, 0}, - {"RawSockaddrDatalink.Data", Field, 0}, - {"RawSockaddrDatalink.Family", Field, 0}, - {"RawSockaddrDatalink.Index", Field, 0}, - {"RawSockaddrDatalink.Len", Field, 0}, - {"RawSockaddrDatalink.Nlen", Field, 0}, - {"RawSockaddrDatalink.Pad_cgo_0", Field, 2}, - {"RawSockaddrDatalink.Slen", Field, 0}, - {"RawSockaddrDatalink.Type", Field, 0}, - {"RawSockaddrInet4", Type, 0}, - {"RawSockaddrInet4.Addr", Field, 0}, - {"RawSockaddrInet4.Family", Field, 0}, - {"RawSockaddrInet4.Len", Field, 0}, - {"RawSockaddrInet4.Port", Field, 0}, - {"RawSockaddrInet4.Zero", Field, 0}, - {"RawSockaddrInet6", Type, 0}, - {"RawSockaddrInet6.Addr", Field, 0}, - {"RawSockaddrInet6.Family", Field, 0}, - {"RawSockaddrInet6.Flowinfo", Field, 0}, - {"RawSockaddrInet6.Len", Field, 0}, - {"RawSockaddrInet6.Port", Field, 0}, - {"RawSockaddrInet6.Scope_id", Field, 0}, - {"RawSockaddrLinklayer", Type, 0}, - {"RawSockaddrLinklayer.Addr", Field, 0}, - {"RawSockaddrLinklayer.Family", Field, 0}, - {"RawSockaddrLinklayer.Halen", Field, 0}, - {"RawSockaddrLinklayer.Hatype", Field, 0}, - {"RawSockaddrLinklayer.Ifindex", Field, 0}, - {"RawSockaddrLinklayer.Pkttype", Field, 0}, - {"RawSockaddrLinklayer.Protocol", Field, 0}, - {"RawSockaddrNetlink", Type, 0}, - {"RawSockaddrNetlink.Family", Field, 0}, - {"RawSockaddrNetlink.Groups", Field, 0}, - {"RawSockaddrNetlink.Pad", Field, 0}, - {"RawSockaddrNetlink.Pid", Field, 0}, - {"RawSockaddrUnix", Type, 0}, - {"RawSockaddrUnix.Family", Field, 0}, - {"RawSockaddrUnix.Len", Field, 0}, - {"RawSockaddrUnix.Pad_cgo_0", Field, 2}, - {"RawSockaddrUnix.Path", Field, 0}, - {"RawSyscall", Func, 0}, - {"RawSyscall6", Func, 0}, - {"Read", Func, 0}, - {"ReadConsole", Func, 1}, - {"ReadDirectoryChanges", Func, 0}, - {"ReadDirent", Func, 0}, - {"ReadFile", Func, 0}, - {"Readlink", Func, 0}, - {"Reboot", Func, 0}, - {"Recvfrom", Func, 0}, - {"Recvmsg", Func, 0}, - {"RegCloseKey", Func, 0}, - {"RegEnumKeyEx", Func, 0}, - {"RegOpenKeyEx", Func, 0}, - {"RegQueryInfoKey", Func, 0}, - {"RegQueryValueEx", Func, 0}, - {"RemoveDirectory", Func, 0}, - {"Removexattr", Func, 1}, - {"Rename", Func, 0}, - {"Renameat", Func, 0}, - {"Revoke", Func, 0}, - {"Rlimit", Type, 0}, - {"Rlimit.Cur", Field, 0}, - {"Rlimit.Max", Field, 0}, - {"Rmdir", Func, 0}, - {"RouteMessage", Type, 0}, - {"RouteMessage.Data", Field, 0}, - {"RouteMessage.Header", Field, 0}, - {"RouteRIB", Func, 0}, - {"RoutingMessage", Type, 0}, - {"RtAttr", Type, 0}, - {"RtAttr.Len", Field, 0}, - {"RtAttr.Type", Field, 0}, - {"RtGenmsg", Type, 0}, - {"RtGenmsg.Family", Field, 0}, - {"RtMetrics", Type, 0}, - {"RtMetrics.Expire", Field, 0}, - {"RtMetrics.Filler", Field, 0}, - {"RtMetrics.Hopcount", Field, 0}, - {"RtMetrics.Locks", Field, 0}, - {"RtMetrics.Mtu", Field, 0}, - {"RtMetrics.Pad", Field, 3}, - {"RtMetrics.Pksent", Field, 0}, - {"RtMetrics.Recvpipe", Field, 0}, - {"RtMetrics.Refcnt", Field, 2}, - {"RtMetrics.Rtt", Field, 0}, - {"RtMetrics.Rttvar", Field, 0}, - {"RtMetrics.Sendpipe", Field, 0}, - {"RtMetrics.Ssthresh", Field, 0}, - {"RtMetrics.Weight", Field, 0}, - {"RtMsg", Type, 0}, - {"RtMsg.Dst_len", Field, 0}, - {"RtMsg.Family", Field, 0}, - {"RtMsg.Flags", Field, 0}, - {"RtMsg.Protocol", Field, 0}, - {"RtMsg.Scope", Field, 0}, - {"RtMsg.Src_len", Field, 0}, - {"RtMsg.Table", Field, 0}, - {"RtMsg.Tos", Field, 0}, - {"RtMsg.Type", Field, 0}, - {"RtMsghdr", Type, 0}, - {"RtMsghdr.Addrs", Field, 0}, - {"RtMsghdr.Errno", Field, 0}, - {"RtMsghdr.Flags", Field, 0}, - {"RtMsghdr.Fmask", Field, 0}, - {"RtMsghdr.Hdrlen", Field, 2}, - {"RtMsghdr.Index", Field, 0}, - {"RtMsghdr.Inits", Field, 0}, - {"RtMsghdr.Mpls", Field, 2}, - {"RtMsghdr.Msglen", Field, 0}, - {"RtMsghdr.Pad_cgo_0", Field, 0}, - {"RtMsghdr.Pad_cgo_1", Field, 2}, - {"RtMsghdr.Pid", Field, 0}, - {"RtMsghdr.Priority", Field, 2}, - {"RtMsghdr.Rmx", Field, 0}, - {"RtMsghdr.Seq", Field, 0}, - {"RtMsghdr.Tableid", Field, 2}, - {"RtMsghdr.Type", Field, 0}, - {"RtMsghdr.Use", Field, 0}, - {"RtMsghdr.Version", Field, 0}, - {"RtNexthop", Type, 0}, - {"RtNexthop.Flags", Field, 0}, - {"RtNexthop.Hops", Field, 0}, - {"RtNexthop.Ifindex", Field, 0}, - {"RtNexthop.Len", Field, 0}, - {"Rusage", Type, 0}, - {"Rusage.CreationTime", Field, 0}, - {"Rusage.ExitTime", Field, 0}, - {"Rusage.Idrss", Field, 0}, - {"Rusage.Inblock", Field, 0}, - {"Rusage.Isrss", Field, 0}, - {"Rusage.Ixrss", Field, 0}, - {"Rusage.KernelTime", Field, 0}, - {"Rusage.Majflt", Field, 0}, - {"Rusage.Maxrss", Field, 0}, - {"Rusage.Minflt", Field, 0}, - {"Rusage.Msgrcv", Field, 0}, - {"Rusage.Msgsnd", Field, 0}, - {"Rusage.Nivcsw", Field, 0}, - {"Rusage.Nsignals", Field, 0}, - {"Rusage.Nswap", Field, 0}, - {"Rusage.Nvcsw", Field, 0}, - {"Rusage.Oublock", Field, 0}, - {"Rusage.Stime", Field, 0}, - {"Rusage.UserTime", Field, 0}, - {"Rusage.Utime", Field, 0}, - {"SCM_BINTIME", Const, 0}, - {"SCM_CREDENTIALS", Const, 0}, - {"SCM_CREDS", Const, 0}, - {"SCM_RIGHTS", Const, 0}, - {"SCM_TIMESTAMP", Const, 0}, - {"SCM_TIMESTAMPING", Const, 0}, - {"SCM_TIMESTAMPNS", Const, 0}, - {"SCM_TIMESTAMP_MONOTONIC", Const, 0}, - {"SHUT_RD", Const, 0}, - {"SHUT_RDWR", Const, 0}, - {"SHUT_WR", Const, 0}, - {"SID", Type, 0}, - {"SIDAndAttributes", Type, 0}, - {"SIDAndAttributes.Attributes", Field, 0}, - {"SIDAndAttributes.Sid", Field, 0}, - {"SIGABRT", Const, 0}, - {"SIGALRM", Const, 0}, - {"SIGBUS", Const, 0}, - {"SIGCHLD", Const, 0}, - {"SIGCLD", Const, 0}, - {"SIGCONT", Const, 0}, - {"SIGEMT", Const, 0}, - {"SIGFPE", Const, 0}, - {"SIGHUP", Const, 0}, - {"SIGILL", Const, 0}, - {"SIGINFO", Const, 0}, - {"SIGINT", Const, 0}, - {"SIGIO", Const, 0}, - {"SIGIOT", Const, 0}, - {"SIGKILL", Const, 0}, - {"SIGLIBRT", Const, 1}, - {"SIGLWP", Const, 0}, - {"SIGPIPE", Const, 0}, - {"SIGPOLL", Const, 0}, - {"SIGPROF", Const, 0}, - {"SIGPWR", Const, 0}, - {"SIGQUIT", Const, 0}, - {"SIGSEGV", Const, 0}, - {"SIGSTKFLT", Const, 0}, - {"SIGSTOP", Const, 0}, - {"SIGSYS", Const, 0}, - {"SIGTERM", Const, 0}, - {"SIGTHR", Const, 0}, - {"SIGTRAP", Const, 0}, - {"SIGTSTP", Const, 0}, - {"SIGTTIN", Const, 0}, - {"SIGTTOU", Const, 0}, - {"SIGUNUSED", Const, 0}, - {"SIGURG", Const, 0}, - {"SIGUSR1", Const, 0}, - {"SIGUSR2", Const, 0}, - {"SIGVTALRM", Const, 0}, - {"SIGWINCH", Const, 0}, - {"SIGXCPU", Const, 0}, - {"SIGXFSZ", Const, 0}, - {"SIOCADDDLCI", Const, 0}, - {"SIOCADDMULTI", Const, 0}, - {"SIOCADDRT", Const, 0}, - {"SIOCAIFADDR", Const, 0}, - {"SIOCAIFGROUP", Const, 0}, - {"SIOCALIFADDR", Const, 0}, - {"SIOCARPIPLL", Const, 0}, - {"SIOCATMARK", Const, 0}, - {"SIOCAUTOADDR", Const, 0}, - {"SIOCAUTONETMASK", Const, 0}, - {"SIOCBRDGADD", Const, 1}, - {"SIOCBRDGADDS", Const, 1}, - {"SIOCBRDGARL", Const, 1}, - {"SIOCBRDGDADDR", Const, 1}, - {"SIOCBRDGDEL", Const, 1}, - {"SIOCBRDGDELS", Const, 1}, - {"SIOCBRDGFLUSH", Const, 1}, - {"SIOCBRDGFRL", Const, 1}, - {"SIOCBRDGGCACHE", Const, 1}, - {"SIOCBRDGGFD", Const, 1}, - {"SIOCBRDGGHT", Const, 1}, - {"SIOCBRDGGIFFLGS", Const, 1}, - {"SIOCBRDGGMA", Const, 1}, - {"SIOCBRDGGPARAM", Const, 1}, - {"SIOCBRDGGPRI", Const, 1}, - {"SIOCBRDGGRL", Const, 1}, - {"SIOCBRDGGSIFS", Const, 1}, - {"SIOCBRDGGTO", Const, 1}, - {"SIOCBRDGIFS", Const, 1}, - {"SIOCBRDGRTS", Const, 1}, - {"SIOCBRDGSADDR", Const, 1}, - {"SIOCBRDGSCACHE", Const, 1}, - {"SIOCBRDGSFD", Const, 1}, - {"SIOCBRDGSHT", Const, 1}, - {"SIOCBRDGSIFCOST", Const, 1}, - {"SIOCBRDGSIFFLGS", Const, 1}, - {"SIOCBRDGSIFPRIO", Const, 1}, - {"SIOCBRDGSMA", Const, 1}, - {"SIOCBRDGSPRI", Const, 1}, - {"SIOCBRDGSPROTO", Const, 1}, - {"SIOCBRDGSTO", Const, 1}, - {"SIOCBRDGSTXHC", Const, 1}, - {"SIOCDARP", Const, 0}, - {"SIOCDELDLCI", Const, 0}, - {"SIOCDELMULTI", Const, 0}, - {"SIOCDELRT", Const, 0}, - {"SIOCDEVPRIVATE", Const, 0}, - {"SIOCDIFADDR", Const, 0}, - {"SIOCDIFGROUP", Const, 0}, - {"SIOCDIFPHYADDR", Const, 0}, - {"SIOCDLIFADDR", Const, 0}, - {"SIOCDRARP", Const, 0}, - {"SIOCGARP", Const, 0}, - {"SIOCGDRVSPEC", Const, 0}, - {"SIOCGETKALIVE", Const, 1}, - {"SIOCGETLABEL", Const, 1}, - {"SIOCGETPFLOW", Const, 1}, - {"SIOCGETPFSYNC", Const, 1}, - {"SIOCGETSGCNT", Const, 0}, - {"SIOCGETVIFCNT", Const, 0}, - {"SIOCGETVLAN", Const, 0}, - {"SIOCGHIWAT", Const, 0}, - {"SIOCGIFADDR", Const, 0}, - {"SIOCGIFADDRPREF", Const, 1}, - {"SIOCGIFALIAS", Const, 1}, - {"SIOCGIFALTMTU", Const, 0}, - {"SIOCGIFASYNCMAP", Const, 0}, - {"SIOCGIFBOND", Const, 0}, - {"SIOCGIFBR", Const, 0}, - {"SIOCGIFBRDADDR", Const, 0}, - {"SIOCGIFCAP", Const, 0}, - {"SIOCGIFCONF", Const, 0}, - {"SIOCGIFCOUNT", Const, 0}, - {"SIOCGIFDATA", Const, 1}, - {"SIOCGIFDESCR", Const, 0}, - {"SIOCGIFDEVMTU", Const, 0}, - {"SIOCGIFDLT", Const, 1}, - {"SIOCGIFDSTADDR", Const, 0}, - {"SIOCGIFENCAP", Const, 0}, - {"SIOCGIFFIB", Const, 1}, - {"SIOCGIFFLAGS", Const, 0}, - {"SIOCGIFGATTR", Const, 1}, - {"SIOCGIFGENERIC", Const, 0}, - {"SIOCGIFGMEMB", Const, 0}, - {"SIOCGIFGROUP", Const, 0}, - {"SIOCGIFHARDMTU", Const, 3}, - {"SIOCGIFHWADDR", Const, 0}, - {"SIOCGIFINDEX", Const, 0}, - {"SIOCGIFKPI", Const, 0}, - {"SIOCGIFMAC", Const, 0}, - {"SIOCGIFMAP", Const, 0}, - {"SIOCGIFMEDIA", Const, 0}, - {"SIOCGIFMEM", Const, 0}, - {"SIOCGIFMETRIC", Const, 0}, - {"SIOCGIFMTU", Const, 0}, - {"SIOCGIFNAME", Const, 0}, - {"SIOCGIFNETMASK", Const, 0}, - {"SIOCGIFPDSTADDR", Const, 0}, - {"SIOCGIFPFLAGS", Const, 0}, - {"SIOCGIFPHYS", Const, 0}, - {"SIOCGIFPRIORITY", Const, 1}, - {"SIOCGIFPSRCADDR", Const, 0}, - {"SIOCGIFRDOMAIN", Const, 1}, - {"SIOCGIFRTLABEL", Const, 1}, - {"SIOCGIFSLAVE", Const, 0}, - {"SIOCGIFSTATUS", Const, 0}, - {"SIOCGIFTIMESLOT", Const, 1}, - {"SIOCGIFTXQLEN", Const, 0}, - {"SIOCGIFVLAN", Const, 0}, - {"SIOCGIFWAKEFLAGS", Const, 0}, - {"SIOCGIFXFLAGS", Const, 1}, - {"SIOCGLIFADDR", Const, 0}, - {"SIOCGLIFPHYADDR", Const, 0}, - {"SIOCGLIFPHYRTABLE", Const, 1}, - {"SIOCGLIFPHYTTL", Const, 3}, - {"SIOCGLINKSTR", Const, 1}, - {"SIOCGLOWAT", Const, 0}, - {"SIOCGPGRP", Const, 0}, - {"SIOCGPRIVATE_0", Const, 0}, - {"SIOCGPRIVATE_1", Const, 0}, - {"SIOCGRARP", Const, 0}, - {"SIOCGSPPPPARAMS", Const, 3}, - {"SIOCGSTAMP", Const, 0}, - {"SIOCGSTAMPNS", Const, 0}, - {"SIOCGVH", Const, 1}, - {"SIOCGVNETID", Const, 3}, - {"SIOCIFCREATE", Const, 0}, - {"SIOCIFCREATE2", Const, 0}, - {"SIOCIFDESTROY", Const, 0}, - {"SIOCIFGCLONERS", Const, 0}, - {"SIOCINITIFADDR", Const, 1}, - {"SIOCPROTOPRIVATE", Const, 0}, - {"SIOCRSLVMULTI", Const, 0}, - {"SIOCRTMSG", Const, 0}, - {"SIOCSARP", Const, 0}, - {"SIOCSDRVSPEC", Const, 0}, - {"SIOCSETKALIVE", Const, 1}, - {"SIOCSETLABEL", Const, 1}, - {"SIOCSETPFLOW", Const, 1}, - {"SIOCSETPFSYNC", Const, 1}, - {"SIOCSETVLAN", Const, 0}, - {"SIOCSHIWAT", Const, 0}, - {"SIOCSIFADDR", Const, 0}, - {"SIOCSIFADDRPREF", Const, 1}, - {"SIOCSIFALTMTU", Const, 0}, - {"SIOCSIFASYNCMAP", Const, 0}, - {"SIOCSIFBOND", Const, 0}, - {"SIOCSIFBR", Const, 0}, - {"SIOCSIFBRDADDR", Const, 0}, - {"SIOCSIFCAP", Const, 0}, - {"SIOCSIFDESCR", Const, 0}, - {"SIOCSIFDSTADDR", Const, 0}, - {"SIOCSIFENCAP", Const, 0}, - {"SIOCSIFFIB", Const, 1}, - {"SIOCSIFFLAGS", Const, 0}, - {"SIOCSIFGATTR", Const, 1}, - {"SIOCSIFGENERIC", Const, 0}, - {"SIOCSIFHWADDR", Const, 0}, - {"SIOCSIFHWBROADCAST", Const, 0}, - {"SIOCSIFKPI", Const, 0}, - {"SIOCSIFLINK", Const, 0}, - {"SIOCSIFLLADDR", Const, 0}, - {"SIOCSIFMAC", Const, 0}, - {"SIOCSIFMAP", Const, 0}, - {"SIOCSIFMEDIA", Const, 0}, - {"SIOCSIFMEM", Const, 0}, - {"SIOCSIFMETRIC", Const, 0}, - {"SIOCSIFMTU", Const, 0}, - {"SIOCSIFNAME", Const, 0}, - {"SIOCSIFNETMASK", Const, 0}, - {"SIOCSIFPFLAGS", Const, 0}, - {"SIOCSIFPHYADDR", Const, 0}, - {"SIOCSIFPHYS", Const, 0}, - {"SIOCSIFPRIORITY", Const, 1}, - {"SIOCSIFRDOMAIN", Const, 1}, - {"SIOCSIFRTLABEL", Const, 1}, - {"SIOCSIFRVNET", Const, 0}, - {"SIOCSIFSLAVE", Const, 0}, - {"SIOCSIFTIMESLOT", Const, 1}, - {"SIOCSIFTXQLEN", Const, 0}, - {"SIOCSIFVLAN", Const, 0}, - {"SIOCSIFVNET", Const, 0}, - {"SIOCSIFXFLAGS", Const, 1}, - {"SIOCSLIFPHYADDR", Const, 0}, - {"SIOCSLIFPHYRTABLE", Const, 1}, - {"SIOCSLIFPHYTTL", Const, 3}, - {"SIOCSLINKSTR", Const, 1}, - {"SIOCSLOWAT", Const, 0}, - {"SIOCSPGRP", Const, 0}, - {"SIOCSRARP", Const, 0}, - {"SIOCSSPPPPARAMS", Const, 3}, - {"SIOCSVH", Const, 1}, - {"SIOCSVNETID", Const, 3}, - {"SIOCZIFDATA", Const, 1}, - {"SIO_GET_EXTENSION_FUNCTION_POINTER", Const, 1}, - {"SIO_GET_INTERFACE_LIST", Const, 0}, - {"SIO_KEEPALIVE_VALS", Const, 3}, - {"SIO_UDP_CONNRESET", Const, 4}, - {"SOCK_CLOEXEC", Const, 0}, - {"SOCK_DCCP", Const, 0}, - {"SOCK_DGRAM", Const, 0}, - {"SOCK_FLAGS_MASK", Const, 1}, - {"SOCK_MAXADDRLEN", Const, 0}, - {"SOCK_NONBLOCK", Const, 0}, - {"SOCK_NOSIGPIPE", Const, 1}, - {"SOCK_PACKET", Const, 0}, - {"SOCK_RAW", Const, 0}, - {"SOCK_RDM", Const, 0}, - {"SOCK_SEQPACKET", Const, 0}, - {"SOCK_STREAM", Const, 0}, - {"SOL_AAL", Const, 0}, - {"SOL_ATM", Const, 0}, - {"SOL_DECNET", Const, 0}, - {"SOL_ICMPV6", Const, 0}, - {"SOL_IP", Const, 0}, - {"SOL_IPV6", Const, 0}, - {"SOL_IRDA", Const, 0}, - {"SOL_PACKET", Const, 0}, - {"SOL_RAW", Const, 0}, - {"SOL_SOCKET", Const, 0}, - {"SOL_TCP", Const, 0}, - {"SOL_X25", Const, 0}, - {"SOMAXCONN", Const, 0}, - {"SO_ACCEPTCONN", Const, 0}, - {"SO_ACCEPTFILTER", Const, 0}, - {"SO_ATTACH_FILTER", Const, 0}, - {"SO_BINDANY", Const, 1}, - {"SO_BINDTODEVICE", Const, 0}, - {"SO_BINTIME", Const, 0}, - {"SO_BROADCAST", Const, 0}, - {"SO_BSDCOMPAT", Const, 0}, - {"SO_DEBUG", Const, 0}, - {"SO_DETACH_FILTER", Const, 0}, - {"SO_DOMAIN", Const, 0}, - {"SO_DONTROUTE", Const, 0}, - {"SO_DONTTRUNC", Const, 0}, - {"SO_ERROR", Const, 0}, - {"SO_KEEPALIVE", Const, 0}, - {"SO_LABEL", Const, 0}, - {"SO_LINGER", Const, 0}, - {"SO_LINGER_SEC", Const, 0}, - {"SO_LISTENINCQLEN", Const, 0}, - {"SO_LISTENQLEN", Const, 0}, - {"SO_LISTENQLIMIT", Const, 0}, - {"SO_MARK", Const, 0}, - {"SO_NETPROC", Const, 1}, - {"SO_NKE", Const, 0}, - {"SO_NOADDRERR", Const, 0}, - {"SO_NOHEADER", Const, 1}, - {"SO_NOSIGPIPE", Const, 0}, - {"SO_NOTIFYCONFLICT", Const, 0}, - {"SO_NO_CHECK", Const, 0}, - {"SO_NO_DDP", Const, 0}, - {"SO_NO_OFFLOAD", Const, 0}, - {"SO_NP_EXTENSIONS", Const, 0}, - {"SO_NREAD", Const, 0}, - {"SO_NUMRCVPKT", Const, 16}, - {"SO_NWRITE", Const, 0}, - {"SO_OOBINLINE", Const, 0}, - {"SO_OVERFLOWED", Const, 1}, - {"SO_PASSCRED", Const, 0}, - {"SO_PASSSEC", Const, 0}, - {"SO_PEERCRED", Const, 0}, - {"SO_PEERLABEL", Const, 0}, - {"SO_PEERNAME", Const, 0}, - {"SO_PEERSEC", Const, 0}, - {"SO_PRIORITY", Const, 0}, - {"SO_PROTOCOL", Const, 0}, - {"SO_PROTOTYPE", Const, 1}, - {"SO_RANDOMPORT", Const, 0}, - {"SO_RCVBUF", Const, 0}, - {"SO_RCVBUFFORCE", Const, 0}, - {"SO_RCVLOWAT", Const, 0}, - {"SO_RCVTIMEO", Const, 0}, - {"SO_RESTRICTIONS", Const, 0}, - {"SO_RESTRICT_DENYIN", Const, 0}, - {"SO_RESTRICT_DENYOUT", Const, 0}, - {"SO_RESTRICT_DENYSET", Const, 0}, - {"SO_REUSEADDR", Const, 0}, - {"SO_REUSEPORT", Const, 0}, - {"SO_REUSESHAREUID", Const, 0}, - {"SO_RTABLE", Const, 1}, - {"SO_RXQ_OVFL", Const, 0}, - {"SO_SECURITY_AUTHENTICATION", Const, 0}, - {"SO_SECURITY_ENCRYPTION_NETWORK", Const, 0}, - {"SO_SECURITY_ENCRYPTION_TRANSPORT", Const, 0}, - {"SO_SETFIB", Const, 0}, - {"SO_SNDBUF", Const, 0}, - {"SO_SNDBUFFORCE", Const, 0}, - {"SO_SNDLOWAT", Const, 0}, - {"SO_SNDTIMEO", Const, 0}, - {"SO_SPLICE", Const, 1}, - {"SO_TIMESTAMP", Const, 0}, - {"SO_TIMESTAMPING", Const, 0}, - {"SO_TIMESTAMPNS", Const, 0}, - {"SO_TIMESTAMP_MONOTONIC", Const, 0}, - {"SO_TYPE", Const, 0}, - {"SO_UPCALLCLOSEWAIT", Const, 0}, - {"SO_UPDATE_ACCEPT_CONTEXT", Const, 0}, - {"SO_UPDATE_CONNECT_CONTEXT", Const, 1}, - {"SO_USELOOPBACK", Const, 0}, - {"SO_USER_COOKIE", Const, 1}, - {"SO_VENDOR", Const, 3}, - {"SO_WANTMORE", Const, 0}, - {"SO_WANTOOBFLAG", Const, 0}, - {"SSLExtraCertChainPolicyPara", Type, 0}, - {"SSLExtraCertChainPolicyPara.AuthType", Field, 0}, - {"SSLExtraCertChainPolicyPara.Checks", Field, 0}, - {"SSLExtraCertChainPolicyPara.ServerName", Field, 0}, - {"SSLExtraCertChainPolicyPara.Size", Field, 0}, - {"STANDARD_RIGHTS_ALL", Const, 0}, - {"STANDARD_RIGHTS_EXECUTE", Const, 0}, - {"STANDARD_RIGHTS_READ", Const, 0}, - {"STANDARD_RIGHTS_REQUIRED", Const, 0}, - {"STANDARD_RIGHTS_WRITE", Const, 0}, - {"STARTF_USESHOWWINDOW", Const, 0}, - {"STARTF_USESTDHANDLES", Const, 0}, - {"STD_ERROR_HANDLE", Const, 0}, - {"STD_INPUT_HANDLE", Const, 0}, - {"STD_OUTPUT_HANDLE", Const, 0}, - {"SUBLANG_ENGLISH_US", Const, 0}, - {"SW_FORCEMINIMIZE", Const, 0}, - {"SW_HIDE", Const, 0}, - {"SW_MAXIMIZE", Const, 0}, - {"SW_MINIMIZE", Const, 0}, - {"SW_NORMAL", Const, 0}, - {"SW_RESTORE", Const, 0}, - {"SW_SHOW", Const, 0}, - {"SW_SHOWDEFAULT", Const, 0}, - {"SW_SHOWMAXIMIZED", Const, 0}, - {"SW_SHOWMINIMIZED", Const, 0}, - {"SW_SHOWMINNOACTIVE", Const, 0}, - {"SW_SHOWNA", Const, 0}, - {"SW_SHOWNOACTIVATE", Const, 0}, - {"SW_SHOWNORMAL", Const, 0}, - {"SYMBOLIC_LINK_FLAG_DIRECTORY", Const, 4}, - {"SYNCHRONIZE", Const, 0}, - {"SYSCTL_VERSION", Const, 1}, - {"SYSCTL_VERS_0", Const, 1}, - {"SYSCTL_VERS_1", Const, 1}, - {"SYSCTL_VERS_MASK", Const, 1}, - {"SYS_ABORT2", Const, 0}, - {"SYS_ACCEPT", Const, 0}, - {"SYS_ACCEPT4", Const, 0}, - {"SYS_ACCEPT_NOCANCEL", Const, 0}, - {"SYS_ACCESS", Const, 0}, - {"SYS_ACCESS_EXTENDED", Const, 0}, - {"SYS_ACCT", Const, 0}, - {"SYS_ADD_KEY", Const, 0}, - {"SYS_ADD_PROFIL", Const, 0}, - {"SYS_ADJFREQ", Const, 1}, - {"SYS_ADJTIME", Const, 0}, - {"SYS_ADJTIMEX", Const, 0}, - {"SYS_AFS_SYSCALL", Const, 0}, - {"SYS_AIO_CANCEL", Const, 0}, - {"SYS_AIO_ERROR", Const, 0}, - {"SYS_AIO_FSYNC", Const, 0}, - {"SYS_AIO_MLOCK", Const, 14}, - {"SYS_AIO_READ", Const, 0}, - {"SYS_AIO_RETURN", Const, 0}, - {"SYS_AIO_SUSPEND", Const, 0}, - {"SYS_AIO_SUSPEND_NOCANCEL", Const, 0}, - {"SYS_AIO_WAITCOMPLETE", Const, 14}, - {"SYS_AIO_WRITE", Const, 0}, - {"SYS_ALARM", Const, 0}, - {"SYS_ARCH_PRCTL", Const, 0}, - {"SYS_ARM_FADVISE64_64", Const, 0}, - {"SYS_ARM_SYNC_FILE_RANGE", Const, 0}, - {"SYS_ATGETMSG", Const, 0}, - {"SYS_ATPGETREQ", Const, 0}, - {"SYS_ATPGETRSP", Const, 0}, - {"SYS_ATPSNDREQ", Const, 0}, - {"SYS_ATPSNDRSP", Const, 0}, - {"SYS_ATPUTMSG", Const, 0}, - {"SYS_ATSOCKET", Const, 0}, - {"SYS_AUDIT", Const, 0}, - {"SYS_AUDITCTL", Const, 0}, - {"SYS_AUDITON", Const, 0}, - {"SYS_AUDIT_SESSION_JOIN", Const, 0}, - {"SYS_AUDIT_SESSION_PORT", Const, 0}, - {"SYS_AUDIT_SESSION_SELF", Const, 0}, - {"SYS_BDFLUSH", Const, 0}, - {"SYS_BIND", Const, 0}, - {"SYS_BINDAT", Const, 3}, - {"SYS_BREAK", Const, 0}, - {"SYS_BRK", Const, 0}, - {"SYS_BSDTHREAD_CREATE", Const, 0}, - {"SYS_BSDTHREAD_REGISTER", Const, 0}, - {"SYS_BSDTHREAD_TERMINATE", Const, 0}, - {"SYS_CAPGET", Const, 0}, - {"SYS_CAPSET", Const, 0}, - {"SYS_CAP_ENTER", Const, 0}, - {"SYS_CAP_FCNTLS_GET", Const, 1}, - {"SYS_CAP_FCNTLS_LIMIT", Const, 1}, - {"SYS_CAP_GETMODE", Const, 0}, - {"SYS_CAP_GETRIGHTS", Const, 0}, - {"SYS_CAP_IOCTLS_GET", Const, 1}, - {"SYS_CAP_IOCTLS_LIMIT", Const, 1}, - {"SYS_CAP_NEW", Const, 0}, - {"SYS_CAP_RIGHTS_GET", Const, 1}, - {"SYS_CAP_RIGHTS_LIMIT", Const, 1}, - {"SYS_CHDIR", Const, 0}, - {"SYS_CHFLAGS", Const, 0}, - {"SYS_CHFLAGSAT", Const, 3}, - {"SYS_CHMOD", Const, 0}, - {"SYS_CHMOD_EXTENDED", Const, 0}, - {"SYS_CHOWN", Const, 0}, - {"SYS_CHOWN32", Const, 0}, - {"SYS_CHROOT", Const, 0}, - {"SYS_CHUD", Const, 0}, - {"SYS_CLOCK_ADJTIME", Const, 0}, - {"SYS_CLOCK_GETCPUCLOCKID2", Const, 1}, - {"SYS_CLOCK_GETRES", Const, 0}, - {"SYS_CLOCK_GETTIME", Const, 0}, - {"SYS_CLOCK_NANOSLEEP", Const, 0}, - {"SYS_CLOCK_SETTIME", Const, 0}, - {"SYS_CLONE", Const, 0}, - {"SYS_CLOSE", Const, 0}, - {"SYS_CLOSEFROM", Const, 0}, - {"SYS_CLOSE_NOCANCEL", Const, 0}, - {"SYS_CONNECT", Const, 0}, - {"SYS_CONNECTAT", Const, 3}, - {"SYS_CONNECT_NOCANCEL", Const, 0}, - {"SYS_COPYFILE", Const, 0}, - {"SYS_CPUSET", Const, 0}, - {"SYS_CPUSET_GETAFFINITY", Const, 0}, - {"SYS_CPUSET_GETID", Const, 0}, - {"SYS_CPUSET_SETAFFINITY", Const, 0}, - {"SYS_CPUSET_SETID", Const, 0}, - {"SYS_CREAT", Const, 0}, - {"SYS_CREATE_MODULE", Const, 0}, - {"SYS_CSOPS", Const, 0}, - {"SYS_CSOPS_AUDITTOKEN", Const, 16}, - {"SYS_DELETE", Const, 0}, - {"SYS_DELETE_MODULE", Const, 0}, - {"SYS_DUP", Const, 0}, - {"SYS_DUP2", Const, 0}, - {"SYS_DUP3", Const, 0}, - {"SYS_EACCESS", Const, 0}, - {"SYS_EPOLL_CREATE", Const, 0}, - {"SYS_EPOLL_CREATE1", Const, 0}, - {"SYS_EPOLL_CTL", Const, 0}, - {"SYS_EPOLL_CTL_OLD", Const, 0}, - {"SYS_EPOLL_PWAIT", Const, 0}, - {"SYS_EPOLL_WAIT", Const, 0}, - {"SYS_EPOLL_WAIT_OLD", Const, 0}, - {"SYS_EVENTFD", Const, 0}, - {"SYS_EVENTFD2", Const, 0}, - {"SYS_EXCHANGEDATA", Const, 0}, - {"SYS_EXECVE", Const, 0}, - {"SYS_EXIT", Const, 0}, - {"SYS_EXIT_GROUP", Const, 0}, - {"SYS_EXTATTRCTL", Const, 0}, - {"SYS_EXTATTR_DELETE_FD", Const, 0}, - {"SYS_EXTATTR_DELETE_FILE", Const, 0}, - {"SYS_EXTATTR_DELETE_LINK", Const, 0}, - {"SYS_EXTATTR_GET_FD", Const, 0}, - {"SYS_EXTATTR_GET_FILE", Const, 0}, - {"SYS_EXTATTR_GET_LINK", Const, 0}, - {"SYS_EXTATTR_LIST_FD", Const, 0}, - {"SYS_EXTATTR_LIST_FILE", Const, 0}, - {"SYS_EXTATTR_LIST_LINK", Const, 0}, - {"SYS_EXTATTR_SET_FD", Const, 0}, - {"SYS_EXTATTR_SET_FILE", Const, 0}, - {"SYS_EXTATTR_SET_LINK", Const, 0}, - {"SYS_FACCESSAT", Const, 0}, - {"SYS_FADVISE64", Const, 0}, - {"SYS_FADVISE64_64", Const, 0}, - {"SYS_FALLOCATE", Const, 0}, - {"SYS_FANOTIFY_INIT", Const, 0}, - {"SYS_FANOTIFY_MARK", Const, 0}, - {"SYS_FCHDIR", Const, 0}, - {"SYS_FCHFLAGS", Const, 0}, - {"SYS_FCHMOD", Const, 0}, - {"SYS_FCHMODAT", Const, 0}, - {"SYS_FCHMOD_EXTENDED", Const, 0}, - {"SYS_FCHOWN", Const, 0}, - {"SYS_FCHOWN32", Const, 0}, - {"SYS_FCHOWNAT", Const, 0}, - {"SYS_FCHROOT", Const, 1}, - {"SYS_FCNTL", Const, 0}, - {"SYS_FCNTL64", Const, 0}, - {"SYS_FCNTL_NOCANCEL", Const, 0}, - {"SYS_FDATASYNC", Const, 0}, - {"SYS_FEXECVE", Const, 0}, - {"SYS_FFCLOCK_GETCOUNTER", Const, 0}, - {"SYS_FFCLOCK_GETESTIMATE", Const, 0}, - {"SYS_FFCLOCK_SETESTIMATE", Const, 0}, - {"SYS_FFSCTL", Const, 0}, - {"SYS_FGETATTRLIST", Const, 0}, - {"SYS_FGETXATTR", Const, 0}, - {"SYS_FHOPEN", Const, 0}, - {"SYS_FHSTAT", Const, 0}, - {"SYS_FHSTATFS", Const, 0}, - {"SYS_FILEPORT_MAKEFD", Const, 0}, - {"SYS_FILEPORT_MAKEPORT", Const, 0}, - {"SYS_FKTRACE", Const, 1}, - {"SYS_FLISTXATTR", Const, 0}, - {"SYS_FLOCK", Const, 0}, - {"SYS_FORK", Const, 0}, - {"SYS_FPATHCONF", Const, 0}, - {"SYS_FREEBSD6_FTRUNCATE", Const, 0}, - {"SYS_FREEBSD6_LSEEK", Const, 0}, - {"SYS_FREEBSD6_MMAP", Const, 0}, - {"SYS_FREEBSD6_PREAD", Const, 0}, - {"SYS_FREEBSD6_PWRITE", Const, 0}, - {"SYS_FREEBSD6_TRUNCATE", Const, 0}, - {"SYS_FREMOVEXATTR", Const, 0}, - {"SYS_FSCTL", Const, 0}, - {"SYS_FSETATTRLIST", Const, 0}, - {"SYS_FSETXATTR", Const, 0}, - {"SYS_FSGETPATH", Const, 0}, - {"SYS_FSTAT", Const, 0}, - {"SYS_FSTAT64", Const, 0}, - {"SYS_FSTAT64_EXTENDED", Const, 0}, - {"SYS_FSTATAT", Const, 0}, - {"SYS_FSTATAT64", Const, 0}, - {"SYS_FSTATFS", Const, 0}, - {"SYS_FSTATFS64", Const, 0}, - {"SYS_FSTATV", Const, 0}, - {"SYS_FSTATVFS1", Const, 1}, - {"SYS_FSTAT_EXTENDED", Const, 0}, - {"SYS_FSYNC", Const, 0}, - {"SYS_FSYNC_NOCANCEL", Const, 0}, - {"SYS_FSYNC_RANGE", Const, 1}, - {"SYS_FTIME", Const, 0}, - {"SYS_FTRUNCATE", Const, 0}, - {"SYS_FTRUNCATE64", Const, 0}, - {"SYS_FUTEX", Const, 0}, - {"SYS_FUTIMENS", Const, 1}, - {"SYS_FUTIMES", Const, 0}, - {"SYS_FUTIMESAT", Const, 0}, - {"SYS_GETATTRLIST", Const, 0}, - {"SYS_GETAUDIT", Const, 0}, - {"SYS_GETAUDIT_ADDR", Const, 0}, - {"SYS_GETAUID", Const, 0}, - {"SYS_GETCONTEXT", Const, 0}, - {"SYS_GETCPU", Const, 0}, - {"SYS_GETCWD", Const, 0}, - {"SYS_GETDENTS", Const, 0}, - {"SYS_GETDENTS64", Const, 0}, - {"SYS_GETDIRENTRIES", Const, 0}, - {"SYS_GETDIRENTRIES64", Const, 0}, - {"SYS_GETDIRENTRIESATTR", Const, 0}, - {"SYS_GETDTABLECOUNT", Const, 1}, - {"SYS_GETDTABLESIZE", Const, 0}, - {"SYS_GETEGID", Const, 0}, - {"SYS_GETEGID32", Const, 0}, - {"SYS_GETEUID", Const, 0}, - {"SYS_GETEUID32", Const, 0}, - {"SYS_GETFH", Const, 0}, - {"SYS_GETFSSTAT", Const, 0}, - {"SYS_GETFSSTAT64", Const, 0}, - {"SYS_GETGID", Const, 0}, - {"SYS_GETGID32", Const, 0}, - {"SYS_GETGROUPS", Const, 0}, - {"SYS_GETGROUPS32", Const, 0}, - {"SYS_GETHOSTUUID", Const, 0}, - {"SYS_GETITIMER", Const, 0}, - {"SYS_GETLCID", Const, 0}, - {"SYS_GETLOGIN", Const, 0}, - {"SYS_GETLOGINCLASS", Const, 0}, - {"SYS_GETPEERNAME", Const, 0}, - {"SYS_GETPGID", Const, 0}, - {"SYS_GETPGRP", Const, 0}, - {"SYS_GETPID", Const, 0}, - {"SYS_GETPMSG", Const, 0}, - {"SYS_GETPPID", Const, 0}, - {"SYS_GETPRIORITY", Const, 0}, - {"SYS_GETRESGID", Const, 0}, - {"SYS_GETRESGID32", Const, 0}, - {"SYS_GETRESUID", Const, 0}, - {"SYS_GETRESUID32", Const, 0}, - {"SYS_GETRLIMIT", Const, 0}, - {"SYS_GETRTABLE", Const, 1}, - {"SYS_GETRUSAGE", Const, 0}, - {"SYS_GETSGROUPS", Const, 0}, - {"SYS_GETSID", Const, 0}, - {"SYS_GETSOCKNAME", Const, 0}, - {"SYS_GETSOCKOPT", Const, 0}, - {"SYS_GETTHRID", Const, 1}, - {"SYS_GETTID", Const, 0}, - {"SYS_GETTIMEOFDAY", Const, 0}, - {"SYS_GETUID", Const, 0}, - {"SYS_GETUID32", Const, 0}, - {"SYS_GETVFSSTAT", Const, 1}, - {"SYS_GETWGROUPS", Const, 0}, - {"SYS_GETXATTR", Const, 0}, - {"SYS_GET_KERNEL_SYMS", Const, 0}, - {"SYS_GET_MEMPOLICY", Const, 0}, - {"SYS_GET_ROBUST_LIST", Const, 0}, - {"SYS_GET_THREAD_AREA", Const, 0}, - {"SYS_GSSD_SYSCALL", Const, 14}, - {"SYS_GTTY", Const, 0}, - {"SYS_IDENTITYSVC", Const, 0}, - {"SYS_IDLE", Const, 0}, - {"SYS_INITGROUPS", Const, 0}, - {"SYS_INIT_MODULE", Const, 0}, - {"SYS_INOTIFY_ADD_WATCH", Const, 0}, - {"SYS_INOTIFY_INIT", Const, 0}, - {"SYS_INOTIFY_INIT1", Const, 0}, - {"SYS_INOTIFY_RM_WATCH", Const, 0}, - {"SYS_IOCTL", Const, 0}, - {"SYS_IOPERM", Const, 0}, - {"SYS_IOPL", Const, 0}, - {"SYS_IOPOLICYSYS", Const, 0}, - {"SYS_IOPRIO_GET", Const, 0}, - {"SYS_IOPRIO_SET", Const, 0}, - {"SYS_IO_CANCEL", Const, 0}, - {"SYS_IO_DESTROY", Const, 0}, - {"SYS_IO_GETEVENTS", Const, 0}, - {"SYS_IO_SETUP", Const, 0}, - {"SYS_IO_SUBMIT", Const, 0}, - {"SYS_IPC", Const, 0}, - {"SYS_ISSETUGID", Const, 0}, - {"SYS_JAIL", Const, 0}, - {"SYS_JAIL_ATTACH", Const, 0}, - {"SYS_JAIL_GET", Const, 0}, - {"SYS_JAIL_REMOVE", Const, 0}, - {"SYS_JAIL_SET", Const, 0}, - {"SYS_KAS_INFO", Const, 16}, - {"SYS_KDEBUG_TRACE", Const, 0}, - {"SYS_KENV", Const, 0}, - {"SYS_KEVENT", Const, 0}, - {"SYS_KEVENT64", Const, 0}, - {"SYS_KEXEC_LOAD", Const, 0}, - {"SYS_KEYCTL", Const, 0}, - {"SYS_KILL", Const, 0}, - {"SYS_KLDFIND", Const, 0}, - {"SYS_KLDFIRSTMOD", Const, 0}, - {"SYS_KLDLOAD", Const, 0}, - {"SYS_KLDNEXT", Const, 0}, - {"SYS_KLDSTAT", Const, 0}, - {"SYS_KLDSYM", Const, 0}, - {"SYS_KLDUNLOAD", Const, 0}, - {"SYS_KLDUNLOADF", Const, 0}, - {"SYS_KMQ_NOTIFY", Const, 14}, - {"SYS_KMQ_OPEN", Const, 14}, - {"SYS_KMQ_SETATTR", Const, 14}, - {"SYS_KMQ_TIMEDRECEIVE", Const, 14}, - {"SYS_KMQ_TIMEDSEND", Const, 14}, - {"SYS_KMQ_UNLINK", Const, 14}, - {"SYS_KQUEUE", Const, 0}, - {"SYS_KQUEUE1", Const, 1}, - {"SYS_KSEM_CLOSE", Const, 14}, - {"SYS_KSEM_DESTROY", Const, 14}, - {"SYS_KSEM_GETVALUE", Const, 14}, - {"SYS_KSEM_INIT", Const, 14}, - {"SYS_KSEM_OPEN", Const, 14}, - {"SYS_KSEM_POST", Const, 14}, - {"SYS_KSEM_TIMEDWAIT", Const, 14}, - {"SYS_KSEM_TRYWAIT", Const, 14}, - {"SYS_KSEM_UNLINK", Const, 14}, - {"SYS_KSEM_WAIT", Const, 14}, - {"SYS_KTIMER_CREATE", Const, 0}, - {"SYS_KTIMER_DELETE", Const, 0}, - {"SYS_KTIMER_GETOVERRUN", Const, 0}, - {"SYS_KTIMER_GETTIME", Const, 0}, - {"SYS_KTIMER_SETTIME", Const, 0}, - {"SYS_KTRACE", Const, 0}, - {"SYS_LCHFLAGS", Const, 0}, - {"SYS_LCHMOD", Const, 0}, - {"SYS_LCHOWN", Const, 0}, - {"SYS_LCHOWN32", Const, 0}, - {"SYS_LEDGER", Const, 16}, - {"SYS_LGETFH", Const, 0}, - {"SYS_LGETXATTR", Const, 0}, - {"SYS_LINK", Const, 0}, - {"SYS_LINKAT", Const, 0}, - {"SYS_LIO_LISTIO", Const, 0}, - {"SYS_LISTEN", Const, 0}, - {"SYS_LISTXATTR", Const, 0}, - {"SYS_LLISTXATTR", Const, 0}, - {"SYS_LOCK", Const, 0}, - {"SYS_LOOKUP_DCOOKIE", Const, 0}, - {"SYS_LPATHCONF", Const, 0}, - {"SYS_LREMOVEXATTR", Const, 0}, - {"SYS_LSEEK", Const, 0}, - {"SYS_LSETXATTR", Const, 0}, - {"SYS_LSTAT", Const, 0}, - {"SYS_LSTAT64", Const, 0}, - {"SYS_LSTAT64_EXTENDED", Const, 0}, - {"SYS_LSTATV", Const, 0}, - {"SYS_LSTAT_EXTENDED", Const, 0}, - {"SYS_LUTIMES", Const, 0}, - {"SYS_MAC_SYSCALL", Const, 0}, - {"SYS_MADVISE", Const, 0}, - {"SYS_MADVISE1", Const, 0}, - {"SYS_MAXSYSCALL", Const, 0}, - {"SYS_MBIND", Const, 0}, - {"SYS_MIGRATE_PAGES", Const, 0}, - {"SYS_MINCORE", Const, 0}, - {"SYS_MINHERIT", Const, 0}, - {"SYS_MKCOMPLEX", Const, 0}, - {"SYS_MKDIR", Const, 0}, - {"SYS_MKDIRAT", Const, 0}, - {"SYS_MKDIR_EXTENDED", Const, 0}, - {"SYS_MKFIFO", Const, 0}, - {"SYS_MKFIFOAT", Const, 0}, - {"SYS_MKFIFO_EXTENDED", Const, 0}, - {"SYS_MKNOD", Const, 0}, - {"SYS_MKNODAT", Const, 0}, - {"SYS_MLOCK", Const, 0}, - {"SYS_MLOCKALL", Const, 0}, - {"SYS_MMAP", Const, 0}, - {"SYS_MMAP2", Const, 0}, - {"SYS_MODCTL", Const, 1}, - {"SYS_MODFIND", Const, 0}, - {"SYS_MODFNEXT", Const, 0}, - {"SYS_MODIFY_LDT", Const, 0}, - {"SYS_MODNEXT", Const, 0}, - {"SYS_MODSTAT", Const, 0}, - {"SYS_MODWATCH", Const, 0}, - {"SYS_MOUNT", Const, 0}, - {"SYS_MOVE_PAGES", Const, 0}, - {"SYS_MPROTECT", Const, 0}, - {"SYS_MPX", Const, 0}, - {"SYS_MQUERY", Const, 1}, - {"SYS_MQ_GETSETATTR", Const, 0}, - {"SYS_MQ_NOTIFY", Const, 0}, - {"SYS_MQ_OPEN", Const, 0}, - {"SYS_MQ_TIMEDRECEIVE", Const, 0}, - {"SYS_MQ_TIMEDSEND", Const, 0}, - {"SYS_MQ_UNLINK", Const, 0}, - {"SYS_MREMAP", Const, 0}, - {"SYS_MSGCTL", Const, 0}, - {"SYS_MSGGET", Const, 0}, - {"SYS_MSGRCV", Const, 0}, - {"SYS_MSGRCV_NOCANCEL", Const, 0}, - {"SYS_MSGSND", Const, 0}, - {"SYS_MSGSND_NOCANCEL", Const, 0}, - {"SYS_MSGSYS", Const, 0}, - {"SYS_MSYNC", Const, 0}, - {"SYS_MSYNC_NOCANCEL", Const, 0}, - {"SYS_MUNLOCK", Const, 0}, - {"SYS_MUNLOCKALL", Const, 0}, - {"SYS_MUNMAP", Const, 0}, - {"SYS_NAME_TO_HANDLE_AT", Const, 0}, - {"SYS_NANOSLEEP", Const, 0}, - {"SYS_NEWFSTATAT", Const, 0}, - {"SYS_NFSCLNT", Const, 0}, - {"SYS_NFSSERVCTL", Const, 0}, - {"SYS_NFSSVC", Const, 0}, - {"SYS_NFSTAT", Const, 0}, - {"SYS_NICE", Const, 0}, - {"SYS_NLM_SYSCALL", Const, 14}, - {"SYS_NLSTAT", Const, 0}, - {"SYS_NMOUNT", Const, 0}, - {"SYS_NSTAT", Const, 0}, - {"SYS_NTP_ADJTIME", Const, 0}, - {"SYS_NTP_GETTIME", Const, 0}, - {"SYS_NUMA_GETAFFINITY", Const, 14}, - {"SYS_NUMA_SETAFFINITY", Const, 14}, - {"SYS_OABI_SYSCALL_BASE", Const, 0}, - {"SYS_OBREAK", Const, 0}, - {"SYS_OLDFSTAT", Const, 0}, - {"SYS_OLDLSTAT", Const, 0}, - {"SYS_OLDOLDUNAME", Const, 0}, - {"SYS_OLDSTAT", Const, 0}, - {"SYS_OLDUNAME", Const, 0}, - {"SYS_OPEN", Const, 0}, - {"SYS_OPENAT", Const, 0}, - {"SYS_OPENBSD_POLL", Const, 0}, - {"SYS_OPEN_BY_HANDLE_AT", Const, 0}, - {"SYS_OPEN_DPROTECTED_NP", Const, 16}, - {"SYS_OPEN_EXTENDED", Const, 0}, - {"SYS_OPEN_NOCANCEL", Const, 0}, - {"SYS_OVADVISE", Const, 0}, - {"SYS_PACCEPT", Const, 1}, - {"SYS_PATHCONF", Const, 0}, - {"SYS_PAUSE", Const, 0}, - {"SYS_PCICONFIG_IOBASE", Const, 0}, - {"SYS_PCICONFIG_READ", Const, 0}, - {"SYS_PCICONFIG_WRITE", Const, 0}, - {"SYS_PDFORK", Const, 0}, - {"SYS_PDGETPID", Const, 0}, - {"SYS_PDKILL", Const, 0}, - {"SYS_PERF_EVENT_OPEN", Const, 0}, - {"SYS_PERSONALITY", Const, 0}, - {"SYS_PID_HIBERNATE", Const, 0}, - {"SYS_PID_RESUME", Const, 0}, - {"SYS_PID_SHUTDOWN_SOCKETS", Const, 0}, - {"SYS_PID_SUSPEND", Const, 0}, - {"SYS_PIPE", Const, 0}, - {"SYS_PIPE2", Const, 0}, - {"SYS_PIVOT_ROOT", Const, 0}, - {"SYS_PMC_CONTROL", Const, 1}, - {"SYS_PMC_GET_INFO", Const, 1}, - {"SYS_POLL", Const, 0}, - {"SYS_POLLTS", Const, 1}, - {"SYS_POLL_NOCANCEL", Const, 0}, - {"SYS_POSIX_FADVISE", Const, 0}, - {"SYS_POSIX_FALLOCATE", Const, 0}, - {"SYS_POSIX_OPENPT", Const, 0}, - {"SYS_POSIX_SPAWN", Const, 0}, - {"SYS_PPOLL", Const, 0}, - {"SYS_PRCTL", Const, 0}, - {"SYS_PREAD", Const, 0}, - {"SYS_PREAD64", Const, 0}, - {"SYS_PREADV", Const, 0}, - {"SYS_PREAD_NOCANCEL", Const, 0}, - {"SYS_PRLIMIT64", Const, 0}, - {"SYS_PROCCTL", Const, 3}, - {"SYS_PROCESS_POLICY", Const, 0}, - {"SYS_PROCESS_VM_READV", Const, 0}, - {"SYS_PROCESS_VM_WRITEV", Const, 0}, - {"SYS_PROC_INFO", Const, 0}, - {"SYS_PROF", Const, 0}, - {"SYS_PROFIL", Const, 0}, - {"SYS_PSELECT", Const, 0}, - {"SYS_PSELECT6", Const, 0}, - {"SYS_PSET_ASSIGN", Const, 1}, - {"SYS_PSET_CREATE", Const, 1}, - {"SYS_PSET_DESTROY", Const, 1}, - {"SYS_PSYNCH_CVBROAD", Const, 0}, - {"SYS_PSYNCH_CVCLRPREPOST", Const, 0}, - {"SYS_PSYNCH_CVSIGNAL", Const, 0}, - {"SYS_PSYNCH_CVWAIT", Const, 0}, - {"SYS_PSYNCH_MUTEXDROP", Const, 0}, - {"SYS_PSYNCH_MUTEXWAIT", Const, 0}, - {"SYS_PSYNCH_RW_DOWNGRADE", Const, 0}, - {"SYS_PSYNCH_RW_LONGRDLOCK", Const, 0}, - {"SYS_PSYNCH_RW_RDLOCK", Const, 0}, - {"SYS_PSYNCH_RW_UNLOCK", Const, 0}, - {"SYS_PSYNCH_RW_UNLOCK2", Const, 0}, - {"SYS_PSYNCH_RW_UPGRADE", Const, 0}, - {"SYS_PSYNCH_RW_WRLOCK", Const, 0}, - {"SYS_PSYNCH_RW_YIELDWRLOCK", Const, 0}, - {"SYS_PTRACE", Const, 0}, - {"SYS_PUTPMSG", Const, 0}, - {"SYS_PWRITE", Const, 0}, - {"SYS_PWRITE64", Const, 0}, - {"SYS_PWRITEV", Const, 0}, - {"SYS_PWRITE_NOCANCEL", Const, 0}, - {"SYS_QUERY_MODULE", Const, 0}, - {"SYS_QUOTACTL", Const, 0}, - {"SYS_RASCTL", Const, 1}, - {"SYS_RCTL_ADD_RULE", Const, 0}, - {"SYS_RCTL_GET_LIMITS", Const, 0}, - {"SYS_RCTL_GET_RACCT", Const, 0}, - {"SYS_RCTL_GET_RULES", Const, 0}, - {"SYS_RCTL_REMOVE_RULE", Const, 0}, - {"SYS_READ", Const, 0}, - {"SYS_READAHEAD", Const, 0}, - {"SYS_READDIR", Const, 0}, - {"SYS_READLINK", Const, 0}, - {"SYS_READLINKAT", Const, 0}, - {"SYS_READV", Const, 0}, - {"SYS_READV_NOCANCEL", Const, 0}, - {"SYS_READ_NOCANCEL", Const, 0}, - {"SYS_REBOOT", Const, 0}, - {"SYS_RECV", Const, 0}, - {"SYS_RECVFROM", Const, 0}, - {"SYS_RECVFROM_NOCANCEL", Const, 0}, - {"SYS_RECVMMSG", Const, 0}, - {"SYS_RECVMSG", Const, 0}, - {"SYS_RECVMSG_NOCANCEL", Const, 0}, - {"SYS_REMAP_FILE_PAGES", Const, 0}, - {"SYS_REMOVEXATTR", Const, 0}, - {"SYS_RENAME", Const, 0}, - {"SYS_RENAMEAT", Const, 0}, - {"SYS_REQUEST_KEY", Const, 0}, - {"SYS_RESTART_SYSCALL", Const, 0}, - {"SYS_REVOKE", Const, 0}, - {"SYS_RFORK", Const, 0}, - {"SYS_RMDIR", Const, 0}, - {"SYS_RTPRIO", Const, 0}, - {"SYS_RTPRIO_THREAD", Const, 0}, - {"SYS_RT_SIGACTION", Const, 0}, - {"SYS_RT_SIGPENDING", Const, 0}, - {"SYS_RT_SIGPROCMASK", Const, 0}, - {"SYS_RT_SIGQUEUEINFO", Const, 0}, - {"SYS_RT_SIGRETURN", Const, 0}, - {"SYS_RT_SIGSUSPEND", Const, 0}, - {"SYS_RT_SIGTIMEDWAIT", Const, 0}, - {"SYS_RT_TGSIGQUEUEINFO", Const, 0}, - {"SYS_SBRK", Const, 0}, - {"SYS_SCHED_GETAFFINITY", Const, 0}, - {"SYS_SCHED_GETPARAM", Const, 0}, - {"SYS_SCHED_GETSCHEDULER", Const, 0}, - {"SYS_SCHED_GET_PRIORITY_MAX", Const, 0}, - {"SYS_SCHED_GET_PRIORITY_MIN", Const, 0}, - {"SYS_SCHED_RR_GET_INTERVAL", Const, 0}, - {"SYS_SCHED_SETAFFINITY", Const, 0}, - {"SYS_SCHED_SETPARAM", Const, 0}, - {"SYS_SCHED_SETSCHEDULER", Const, 0}, - {"SYS_SCHED_YIELD", Const, 0}, - {"SYS_SCTP_GENERIC_RECVMSG", Const, 0}, - {"SYS_SCTP_GENERIC_SENDMSG", Const, 0}, - {"SYS_SCTP_GENERIC_SENDMSG_IOV", Const, 0}, - {"SYS_SCTP_PEELOFF", Const, 0}, - {"SYS_SEARCHFS", Const, 0}, - {"SYS_SECURITY", Const, 0}, - {"SYS_SELECT", Const, 0}, - {"SYS_SELECT_NOCANCEL", Const, 0}, - {"SYS_SEMCONFIG", Const, 1}, - {"SYS_SEMCTL", Const, 0}, - {"SYS_SEMGET", Const, 0}, - {"SYS_SEMOP", Const, 0}, - {"SYS_SEMSYS", Const, 0}, - {"SYS_SEMTIMEDOP", Const, 0}, - {"SYS_SEM_CLOSE", Const, 0}, - {"SYS_SEM_DESTROY", Const, 0}, - {"SYS_SEM_GETVALUE", Const, 0}, - {"SYS_SEM_INIT", Const, 0}, - {"SYS_SEM_OPEN", Const, 0}, - {"SYS_SEM_POST", Const, 0}, - {"SYS_SEM_TRYWAIT", Const, 0}, - {"SYS_SEM_UNLINK", Const, 0}, - {"SYS_SEM_WAIT", Const, 0}, - {"SYS_SEM_WAIT_NOCANCEL", Const, 0}, - {"SYS_SEND", Const, 0}, - {"SYS_SENDFILE", Const, 0}, - {"SYS_SENDFILE64", Const, 0}, - {"SYS_SENDMMSG", Const, 0}, - {"SYS_SENDMSG", Const, 0}, - {"SYS_SENDMSG_NOCANCEL", Const, 0}, - {"SYS_SENDTO", Const, 0}, - {"SYS_SENDTO_NOCANCEL", Const, 0}, - {"SYS_SETATTRLIST", Const, 0}, - {"SYS_SETAUDIT", Const, 0}, - {"SYS_SETAUDIT_ADDR", Const, 0}, - {"SYS_SETAUID", Const, 0}, - {"SYS_SETCONTEXT", Const, 0}, - {"SYS_SETDOMAINNAME", Const, 0}, - {"SYS_SETEGID", Const, 0}, - {"SYS_SETEUID", Const, 0}, - {"SYS_SETFIB", Const, 0}, - {"SYS_SETFSGID", Const, 0}, - {"SYS_SETFSGID32", Const, 0}, - {"SYS_SETFSUID", Const, 0}, - {"SYS_SETFSUID32", Const, 0}, - {"SYS_SETGID", Const, 0}, - {"SYS_SETGID32", Const, 0}, - {"SYS_SETGROUPS", Const, 0}, - {"SYS_SETGROUPS32", Const, 0}, - {"SYS_SETHOSTNAME", Const, 0}, - {"SYS_SETITIMER", Const, 0}, - {"SYS_SETLCID", Const, 0}, - {"SYS_SETLOGIN", Const, 0}, - {"SYS_SETLOGINCLASS", Const, 0}, - {"SYS_SETNS", Const, 0}, - {"SYS_SETPGID", Const, 0}, - {"SYS_SETPRIORITY", Const, 0}, - {"SYS_SETPRIVEXEC", Const, 0}, - {"SYS_SETREGID", Const, 0}, - {"SYS_SETREGID32", Const, 0}, - {"SYS_SETRESGID", Const, 0}, - {"SYS_SETRESGID32", Const, 0}, - {"SYS_SETRESUID", Const, 0}, - {"SYS_SETRESUID32", Const, 0}, - {"SYS_SETREUID", Const, 0}, - {"SYS_SETREUID32", Const, 0}, - {"SYS_SETRLIMIT", Const, 0}, - {"SYS_SETRTABLE", Const, 1}, - {"SYS_SETSGROUPS", Const, 0}, - {"SYS_SETSID", Const, 0}, - {"SYS_SETSOCKOPT", Const, 0}, - {"SYS_SETTID", Const, 0}, - {"SYS_SETTID_WITH_PID", Const, 0}, - {"SYS_SETTIMEOFDAY", Const, 0}, - {"SYS_SETUID", Const, 0}, - {"SYS_SETUID32", Const, 0}, - {"SYS_SETWGROUPS", Const, 0}, - {"SYS_SETXATTR", Const, 0}, - {"SYS_SET_MEMPOLICY", Const, 0}, - {"SYS_SET_ROBUST_LIST", Const, 0}, - {"SYS_SET_THREAD_AREA", Const, 0}, - {"SYS_SET_TID_ADDRESS", Const, 0}, - {"SYS_SGETMASK", Const, 0}, - {"SYS_SHARED_REGION_CHECK_NP", Const, 0}, - {"SYS_SHARED_REGION_MAP_AND_SLIDE_NP", Const, 0}, - {"SYS_SHMAT", Const, 0}, - {"SYS_SHMCTL", Const, 0}, - {"SYS_SHMDT", Const, 0}, - {"SYS_SHMGET", Const, 0}, - {"SYS_SHMSYS", Const, 0}, - {"SYS_SHM_OPEN", Const, 0}, - {"SYS_SHM_UNLINK", Const, 0}, - {"SYS_SHUTDOWN", Const, 0}, - {"SYS_SIGACTION", Const, 0}, - {"SYS_SIGALTSTACK", Const, 0}, - {"SYS_SIGNAL", Const, 0}, - {"SYS_SIGNALFD", Const, 0}, - {"SYS_SIGNALFD4", Const, 0}, - {"SYS_SIGPENDING", Const, 0}, - {"SYS_SIGPROCMASK", Const, 0}, - {"SYS_SIGQUEUE", Const, 0}, - {"SYS_SIGQUEUEINFO", Const, 1}, - {"SYS_SIGRETURN", Const, 0}, - {"SYS_SIGSUSPEND", Const, 0}, - {"SYS_SIGSUSPEND_NOCANCEL", Const, 0}, - {"SYS_SIGTIMEDWAIT", Const, 0}, - {"SYS_SIGWAIT", Const, 0}, - {"SYS_SIGWAITINFO", Const, 0}, - {"SYS_SOCKET", Const, 0}, - {"SYS_SOCKETCALL", Const, 0}, - {"SYS_SOCKETPAIR", Const, 0}, - {"SYS_SPLICE", Const, 0}, - {"SYS_SSETMASK", Const, 0}, - {"SYS_SSTK", Const, 0}, - {"SYS_STACK_SNAPSHOT", Const, 0}, - {"SYS_STAT", Const, 0}, - {"SYS_STAT64", Const, 0}, - {"SYS_STAT64_EXTENDED", Const, 0}, - {"SYS_STATFS", Const, 0}, - {"SYS_STATFS64", Const, 0}, - {"SYS_STATV", Const, 0}, - {"SYS_STATVFS1", Const, 1}, - {"SYS_STAT_EXTENDED", Const, 0}, - {"SYS_STIME", Const, 0}, - {"SYS_STTY", Const, 0}, - {"SYS_SWAPCONTEXT", Const, 0}, - {"SYS_SWAPCTL", Const, 1}, - {"SYS_SWAPOFF", Const, 0}, - {"SYS_SWAPON", Const, 0}, - {"SYS_SYMLINK", Const, 0}, - {"SYS_SYMLINKAT", Const, 0}, - {"SYS_SYNC", Const, 0}, - {"SYS_SYNCFS", Const, 0}, - {"SYS_SYNC_FILE_RANGE", Const, 0}, - {"SYS_SYSARCH", Const, 0}, - {"SYS_SYSCALL", Const, 0}, - {"SYS_SYSCALL_BASE", Const, 0}, - {"SYS_SYSFS", Const, 0}, - {"SYS_SYSINFO", Const, 0}, - {"SYS_SYSLOG", Const, 0}, - {"SYS_TEE", Const, 0}, - {"SYS_TGKILL", Const, 0}, - {"SYS_THREAD_SELFID", Const, 0}, - {"SYS_THR_CREATE", Const, 0}, - {"SYS_THR_EXIT", Const, 0}, - {"SYS_THR_KILL", Const, 0}, - {"SYS_THR_KILL2", Const, 0}, - {"SYS_THR_NEW", Const, 0}, - {"SYS_THR_SELF", Const, 0}, - {"SYS_THR_SET_NAME", Const, 0}, - {"SYS_THR_SUSPEND", Const, 0}, - {"SYS_THR_WAKE", Const, 0}, - {"SYS_TIME", Const, 0}, - {"SYS_TIMERFD_CREATE", Const, 0}, - {"SYS_TIMERFD_GETTIME", Const, 0}, - {"SYS_TIMERFD_SETTIME", Const, 0}, - {"SYS_TIMER_CREATE", Const, 0}, - {"SYS_TIMER_DELETE", Const, 0}, - {"SYS_TIMER_GETOVERRUN", Const, 0}, - {"SYS_TIMER_GETTIME", Const, 0}, - {"SYS_TIMER_SETTIME", Const, 0}, - {"SYS_TIMES", Const, 0}, - {"SYS_TKILL", Const, 0}, - {"SYS_TRUNCATE", Const, 0}, - {"SYS_TRUNCATE64", Const, 0}, - {"SYS_TUXCALL", Const, 0}, - {"SYS_UGETRLIMIT", Const, 0}, - {"SYS_ULIMIT", Const, 0}, - {"SYS_UMASK", Const, 0}, - {"SYS_UMASK_EXTENDED", Const, 0}, - {"SYS_UMOUNT", Const, 0}, - {"SYS_UMOUNT2", Const, 0}, - {"SYS_UNAME", Const, 0}, - {"SYS_UNDELETE", Const, 0}, - {"SYS_UNLINK", Const, 0}, - {"SYS_UNLINKAT", Const, 0}, - {"SYS_UNMOUNT", Const, 0}, - {"SYS_UNSHARE", Const, 0}, - {"SYS_USELIB", Const, 0}, - {"SYS_USTAT", Const, 0}, - {"SYS_UTIME", Const, 0}, - {"SYS_UTIMENSAT", Const, 0}, - {"SYS_UTIMES", Const, 0}, - {"SYS_UTRACE", Const, 0}, - {"SYS_UUIDGEN", Const, 0}, - {"SYS_VADVISE", Const, 1}, - {"SYS_VFORK", Const, 0}, - {"SYS_VHANGUP", Const, 0}, - {"SYS_VM86", Const, 0}, - {"SYS_VM86OLD", Const, 0}, - {"SYS_VMSPLICE", Const, 0}, - {"SYS_VM_PRESSURE_MONITOR", Const, 0}, - {"SYS_VSERVER", Const, 0}, - {"SYS_WAIT4", Const, 0}, - {"SYS_WAIT4_NOCANCEL", Const, 0}, - {"SYS_WAIT6", Const, 1}, - {"SYS_WAITEVENT", Const, 0}, - {"SYS_WAITID", Const, 0}, - {"SYS_WAITID_NOCANCEL", Const, 0}, - {"SYS_WAITPID", Const, 0}, - {"SYS_WATCHEVENT", Const, 0}, - {"SYS_WORKQ_KERNRETURN", Const, 0}, - {"SYS_WORKQ_OPEN", Const, 0}, - {"SYS_WRITE", Const, 0}, - {"SYS_WRITEV", Const, 0}, - {"SYS_WRITEV_NOCANCEL", Const, 0}, - {"SYS_WRITE_NOCANCEL", Const, 0}, - {"SYS_YIELD", Const, 0}, - {"SYS__LLSEEK", Const, 0}, - {"SYS__LWP_CONTINUE", Const, 1}, - {"SYS__LWP_CREATE", Const, 1}, - {"SYS__LWP_CTL", Const, 1}, - {"SYS__LWP_DETACH", Const, 1}, - {"SYS__LWP_EXIT", Const, 1}, - {"SYS__LWP_GETNAME", Const, 1}, - {"SYS__LWP_GETPRIVATE", Const, 1}, - {"SYS__LWP_KILL", Const, 1}, - {"SYS__LWP_PARK", Const, 1}, - {"SYS__LWP_SELF", Const, 1}, - {"SYS__LWP_SETNAME", Const, 1}, - {"SYS__LWP_SETPRIVATE", Const, 1}, - {"SYS__LWP_SUSPEND", Const, 1}, - {"SYS__LWP_UNPARK", Const, 1}, - {"SYS__LWP_UNPARK_ALL", Const, 1}, - {"SYS__LWP_WAIT", Const, 1}, - {"SYS__LWP_WAKEUP", Const, 1}, - {"SYS__NEWSELECT", Const, 0}, - {"SYS__PSET_BIND", Const, 1}, - {"SYS__SCHED_GETAFFINITY", Const, 1}, - {"SYS__SCHED_GETPARAM", Const, 1}, - {"SYS__SCHED_SETAFFINITY", Const, 1}, - {"SYS__SCHED_SETPARAM", Const, 1}, - {"SYS__SYSCTL", Const, 0}, - {"SYS__UMTX_LOCK", Const, 0}, - {"SYS__UMTX_OP", Const, 0}, - {"SYS__UMTX_UNLOCK", Const, 0}, - {"SYS___ACL_ACLCHECK_FD", Const, 0}, - {"SYS___ACL_ACLCHECK_FILE", Const, 0}, - {"SYS___ACL_ACLCHECK_LINK", Const, 0}, - {"SYS___ACL_DELETE_FD", Const, 0}, - {"SYS___ACL_DELETE_FILE", Const, 0}, - {"SYS___ACL_DELETE_LINK", Const, 0}, - {"SYS___ACL_GET_FD", Const, 0}, - {"SYS___ACL_GET_FILE", Const, 0}, - {"SYS___ACL_GET_LINK", Const, 0}, - {"SYS___ACL_SET_FD", Const, 0}, - {"SYS___ACL_SET_FILE", Const, 0}, - {"SYS___ACL_SET_LINK", Const, 0}, - {"SYS___CAP_RIGHTS_GET", Const, 14}, - {"SYS___CLONE", Const, 1}, - {"SYS___DISABLE_THREADSIGNAL", Const, 0}, - {"SYS___GETCWD", Const, 0}, - {"SYS___GETLOGIN", Const, 1}, - {"SYS___GET_TCB", Const, 1}, - {"SYS___MAC_EXECVE", Const, 0}, - {"SYS___MAC_GETFSSTAT", Const, 0}, - {"SYS___MAC_GET_FD", Const, 0}, - {"SYS___MAC_GET_FILE", Const, 0}, - {"SYS___MAC_GET_LCID", Const, 0}, - {"SYS___MAC_GET_LCTX", Const, 0}, - {"SYS___MAC_GET_LINK", Const, 0}, - {"SYS___MAC_GET_MOUNT", Const, 0}, - {"SYS___MAC_GET_PID", Const, 0}, - {"SYS___MAC_GET_PROC", Const, 0}, - {"SYS___MAC_MOUNT", Const, 0}, - {"SYS___MAC_SET_FD", Const, 0}, - {"SYS___MAC_SET_FILE", Const, 0}, - {"SYS___MAC_SET_LCTX", Const, 0}, - {"SYS___MAC_SET_LINK", Const, 0}, - {"SYS___MAC_SET_PROC", Const, 0}, - {"SYS___MAC_SYSCALL", Const, 0}, - {"SYS___OLD_SEMWAIT_SIGNAL", Const, 0}, - {"SYS___OLD_SEMWAIT_SIGNAL_NOCANCEL", Const, 0}, - {"SYS___POSIX_CHOWN", Const, 1}, - {"SYS___POSIX_FCHOWN", Const, 1}, - {"SYS___POSIX_LCHOWN", Const, 1}, - {"SYS___POSIX_RENAME", Const, 1}, - {"SYS___PTHREAD_CANCELED", Const, 0}, - {"SYS___PTHREAD_CHDIR", Const, 0}, - {"SYS___PTHREAD_FCHDIR", Const, 0}, - {"SYS___PTHREAD_KILL", Const, 0}, - {"SYS___PTHREAD_MARKCANCEL", Const, 0}, - {"SYS___PTHREAD_SIGMASK", Const, 0}, - {"SYS___QUOTACTL", Const, 1}, - {"SYS___SEMCTL", Const, 1}, - {"SYS___SEMWAIT_SIGNAL", Const, 0}, - {"SYS___SEMWAIT_SIGNAL_NOCANCEL", Const, 0}, - {"SYS___SETLOGIN", Const, 1}, - {"SYS___SETUGID", Const, 0}, - {"SYS___SET_TCB", Const, 1}, - {"SYS___SIGACTION_SIGTRAMP", Const, 1}, - {"SYS___SIGTIMEDWAIT", Const, 1}, - {"SYS___SIGWAIT", Const, 0}, - {"SYS___SIGWAIT_NOCANCEL", Const, 0}, - {"SYS___SYSCTL", Const, 0}, - {"SYS___TFORK", Const, 1}, - {"SYS___THREXIT", Const, 1}, - {"SYS___THRSIGDIVERT", Const, 1}, - {"SYS___THRSLEEP", Const, 1}, - {"SYS___THRWAKEUP", Const, 1}, - {"S_ARCH1", Const, 1}, - {"S_ARCH2", Const, 1}, - {"S_BLKSIZE", Const, 0}, - {"S_IEXEC", Const, 0}, - {"S_IFBLK", Const, 0}, - {"S_IFCHR", Const, 0}, - {"S_IFDIR", Const, 0}, - {"S_IFIFO", Const, 0}, - {"S_IFLNK", Const, 0}, - {"S_IFMT", Const, 0}, - {"S_IFREG", Const, 0}, - {"S_IFSOCK", Const, 0}, - {"S_IFWHT", Const, 0}, - {"S_IREAD", Const, 0}, - {"S_IRGRP", Const, 0}, - {"S_IROTH", Const, 0}, - {"S_IRUSR", Const, 0}, - {"S_IRWXG", Const, 0}, - {"S_IRWXO", Const, 0}, - {"S_IRWXU", Const, 0}, - {"S_ISGID", Const, 0}, - {"S_ISTXT", Const, 0}, - {"S_ISUID", Const, 0}, - {"S_ISVTX", Const, 0}, - {"S_IWGRP", Const, 0}, - {"S_IWOTH", Const, 0}, - {"S_IWRITE", Const, 0}, - {"S_IWUSR", Const, 0}, - {"S_IXGRP", Const, 0}, - {"S_IXOTH", Const, 0}, - {"S_IXUSR", Const, 0}, - {"S_LOGIN_SET", Const, 1}, - {"SecurityAttributes", Type, 0}, - {"SecurityAttributes.InheritHandle", Field, 0}, - {"SecurityAttributes.Length", Field, 0}, - {"SecurityAttributes.SecurityDescriptor", Field, 0}, - {"Seek", Func, 0}, - {"Select", Func, 0}, - {"Sendfile", Func, 0}, - {"Sendmsg", Func, 0}, - {"SendmsgN", Func, 3}, - {"Sendto", Func, 0}, - {"Servent", Type, 0}, - {"Servent.Aliases", Field, 0}, - {"Servent.Name", Field, 0}, - {"Servent.Port", Field, 0}, - {"Servent.Proto", Field, 0}, - {"SetBpf", Func, 0}, - {"SetBpfBuflen", Func, 0}, - {"SetBpfDatalink", Func, 0}, - {"SetBpfHeadercmpl", Func, 0}, - {"SetBpfImmediate", Func, 0}, - {"SetBpfInterface", Func, 0}, - {"SetBpfPromisc", Func, 0}, - {"SetBpfTimeout", Func, 0}, - {"SetCurrentDirectory", Func, 0}, - {"SetEndOfFile", Func, 0}, - {"SetEnvironmentVariable", Func, 0}, - {"SetFileAttributes", Func, 0}, - {"SetFileCompletionNotificationModes", Func, 2}, - {"SetFilePointer", Func, 0}, - {"SetFileTime", Func, 0}, - {"SetHandleInformation", Func, 0}, - {"SetKevent", Func, 0}, - {"SetLsfPromisc", Func, 0}, - {"SetNonblock", Func, 0}, - {"Setdomainname", Func, 0}, - {"Setegid", Func, 0}, - {"Setenv", Func, 0}, - {"Seteuid", Func, 0}, - {"Setfsgid", Func, 0}, - {"Setfsuid", Func, 0}, - {"Setgid", Func, 0}, - {"Setgroups", Func, 0}, - {"Sethostname", Func, 0}, - {"Setlogin", Func, 0}, - {"Setpgid", Func, 0}, - {"Setpriority", Func, 0}, - {"Setprivexec", Func, 0}, - {"Setregid", Func, 0}, - {"Setresgid", Func, 0}, - {"Setresuid", Func, 0}, - {"Setreuid", Func, 0}, - {"Setrlimit", Func, 0}, - {"Setsid", Func, 0}, - {"Setsockopt", Func, 0}, - {"SetsockoptByte", Func, 0}, - {"SetsockoptICMPv6Filter", Func, 2}, - {"SetsockoptIPMreq", Func, 0}, - {"SetsockoptIPMreqn", Func, 0}, - {"SetsockoptIPv6Mreq", Func, 0}, - {"SetsockoptInet4Addr", Func, 0}, - {"SetsockoptInt", Func, 0}, - {"SetsockoptLinger", Func, 0}, - {"SetsockoptString", Func, 0}, - {"SetsockoptTimeval", Func, 0}, - {"Settimeofday", Func, 0}, - {"Setuid", Func, 0}, - {"Setxattr", Func, 1}, - {"Shutdown", Func, 0}, - {"SidTypeAlias", Const, 0}, - {"SidTypeComputer", Const, 0}, - {"SidTypeDeletedAccount", Const, 0}, - {"SidTypeDomain", Const, 0}, - {"SidTypeGroup", Const, 0}, - {"SidTypeInvalid", Const, 0}, - {"SidTypeLabel", Const, 0}, - {"SidTypeUnknown", Const, 0}, - {"SidTypeUser", Const, 0}, - {"SidTypeWellKnownGroup", Const, 0}, - {"Signal", Type, 0}, - {"SizeofBpfHdr", Const, 0}, - {"SizeofBpfInsn", Const, 0}, - {"SizeofBpfProgram", Const, 0}, - {"SizeofBpfStat", Const, 0}, - {"SizeofBpfVersion", Const, 0}, - {"SizeofBpfZbuf", Const, 0}, - {"SizeofBpfZbufHeader", Const, 0}, - {"SizeofCmsghdr", Const, 0}, - {"SizeofICMPv6Filter", Const, 2}, - {"SizeofIPMreq", Const, 0}, - {"SizeofIPMreqn", Const, 0}, - {"SizeofIPv6MTUInfo", Const, 2}, - {"SizeofIPv6Mreq", Const, 0}, - {"SizeofIfAddrmsg", Const, 0}, - {"SizeofIfAnnounceMsghdr", Const, 1}, - {"SizeofIfData", Const, 0}, - {"SizeofIfInfomsg", Const, 0}, - {"SizeofIfMsghdr", Const, 0}, - {"SizeofIfaMsghdr", Const, 0}, - {"SizeofIfmaMsghdr", Const, 0}, - {"SizeofIfmaMsghdr2", Const, 0}, - {"SizeofInet4Pktinfo", Const, 0}, - {"SizeofInet6Pktinfo", Const, 0}, - {"SizeofInotifyEvent", Const, 0}, - {"SizeofLinger", Const, 0}, - {"SizeofMsghdr", Const, 0}, - {"SizeofNlAttr", Const, 0}, - {"SizeofNlMsgerr", Const, 0}, - {"SizeofNlMsghdr", Const, 0}, - {"SizeofRtAttr", Const, 0}, - {"SizeofRtGenmsg", Const, 0}, - {"SizeofRtMetrics", Const, 0}, - {"SizeofRtMsg", Const, 0}, - {"SizeofRtMsghdr", Const, 0}, - {"SizeofRtNexthop", Const, 0}, - {"SizeofSockFilter", Const, 0}, - {"SizeofSockFprog", Const, 0}, - {"SizeofSockaddrAny", Const, 0}, - {"SizeofSockaddrDatalink", Const, 0}, - {"SizeofSockaddrInet4", Const, 0}, - {"SizeofSockaddrInet6", Const, 0}, - {"SizeofSockaddrLinklayer", Const, 0}, - {"SizeofSockaddrNetlink", Const, 0}, - {"SizeofSockaddrUnix", Const, 0}, - {"SizeofTCPInfo", Const, 1}, - {"SizeofUcred", Const, 0}, - {"SlicePtrFromStrings", Func, 1}, - {"SockFilter", Type, 0}, - {"SockFilter.Code", Field, 0}, - {"SockFilter.Jf", Field, 0}, - {"SockFilter.Jt", Field, 0}, - {"SockFilter.K", Field, 0}, - {"SockFprog", Type, 0}, - {"SockFprog.Filter", Field, 0}, - {"SockFprog.Len", Field, 0}, - {"SockFprog.Pad_cgo_0", Field, 0}, - {"Sockaddr", Type, 0}, - {"SockaddrDatalink", Type, 0}, - {"SockaddrDatalink.Alen", Field, 0}, - {"SockaddrDatalink.Data", Field, 0}, - {"SockaddrDatalink.Family", Field, 0}, - {"SockaddrDatalink.Index", Field, 0}, - {"SockaddrDatalink.Len", Field, 0}, - {"SockaddrDatalink.Nlen", Field, 0}, - {"SockaddrDatalink.Slen", Field, 0}, - {"SockaddrDatalink.Type", Field, 0}, - {"SockaddrGen", Type, 0}, - {"SockaddrInet4", Type, 0}, - {"SockaddrInet4.Addr", Field, 0}, - {"SockaddrInet4.Port", Field, 0}, - {"SockaddrInet6", Type, 0}, - {"SockaddrInet6.Addr", Field, 0}, - {"SockaddrInet6.Port", Field, 0}, - {"SockaddrInet6.ZoneId", Field, 0}, - {"SockaddrLinklayer", Type, 0}, - {"SockaddrLinklayer.Addr", Field, 0}, - {"SockaddrLinklayer.Halen", Field, 0}, - {"SockaddrLinklayer.Hatype", Field, 0}, - {"SockaddrLinklayer.Ifindex", Field, 0}, - {"SockaddrLinklayer.Pkttype", Field, 0}, - {"SockaddrLinklayer.Protocol", Field, 0}, - {"SockaddrNetlink", Type, 0}, - {"SockaddrNetlink.Family", Field, 0}, - {"SockaddrNetlink.Groups", Field, 0}, - {"SockaddrNetlink.Pad", Field, 0}, - {"SockaddrNetlink.Pid", Field, 0}, - {"SockaddrUnix", Type, 0}, - {"SockaddrUnix.Name", Field, 0}, - {"Socket", Func, 0}, - {"SocketControlMessage", Type, 0}, - {"SocketControlMessage.Data", Field, 0}, - {"SocketControlMessage.Header", Field, 0}, - {"SocketDisableIPv6", Var, 0}, - {"Socketpair", Func, 0}, - {"Splice", Func, 0}, - {"StartProcess", Func, 0}, - {"StartupInfo", Type, 0}, - {"StartupInfo.Cb", Field, 0}, - {"StartupInfo.Desktop", Field, 0}, - {"StartupInfo.FillAttribute", Field, 0}, - {"StartupInfo.Flags", Field, 0}, - {"StartupInfo.ShowWindow", Field, 0}, - {"StartupInfo.StdErr", Field, 0}, - {"StartupInfo.StdInput", Field, 0}, - {"StartupInfo.StdOutput", Field, 0}, - {"StartupInfo.Title", Field, 0}, - {"StartupInfo.X", Field, 0}, - {"StartupInfo.XCountChars", Field, 0}, - {"StartupInfo.XSize", Field, 0}, - {"StartupInfo.Y", Field, 0}, - {"StartupInfo.YCountChars", Field, 0}, - {"StartupInfo.YSize", Field, 0}, - {"Stat", Func, 0}, - {"Stat_t", Type, 0}, - {"Stat_t.Atim", Field, 0}, - {"Stat_t.Atim_ext", Field, 12}, - {"Stat_t.Atimespec", Field, 0}, - {"Stat_t.Birthtimespec", Field, 0}, - {"Stat_t.Blksize", Field, 0}, - {"Stat_t.Blocks", Field, 0}, - {"Stat_t.Btim_ext", Field, 12}, - {"Stat_t.Ctim", Field, 0}, - {"Stat_t.Ctim_ext", Field, 12}, - {"Stat_t.Ctimespec", Field, 0}, - {"Stat_t.Dev", Field, 0}, - {"Stat_t.Flags", Field, 0}, - {"Stat_t.Gen", Field, 0}, - {"Stat_t.Gid", Field, 0}, - {"Stat_t.Ino", Field, 0}, - {"Stat_t.Lspare", Field, 0}, - {"Stat_t.Lspare0", Field, 2}, - {"Stat_t.Lspare1", Field, 2}, - {"Stat_t.Mode", Field, 0}, - {"Stat_t.Mtim", Field, 0}, - {"Stat_t.Mtim_ext", Field, 12}, - {"Stat_t.Mtimespec", Field, 0}, - {"Stat_t.Nlink", Field, 0}, - {"Stat_t.Pad_cgo_0", Field, 0}, - {"Stat_t.Pad_cgo_1", Field, 0}, - {"Stat_t.Pad_cgo_2", Field, 0}, - {"Stat_t.Padding0", Field, 12}, - {"Stat_t.Padding1", Field, 12}, - {"Stat_t.Qspare", Field, 0}, - {"Stat_t.Rdev", Field, 0}, - {"Stat_t.Size", Field, 0}, - {"Stat_t.Spare", Field, 2}, - {"Stat_t.Uid", Field, 0}, - {"Stat_t.X__pad0", Field, 0}, - {"Stat_t.X__pad1", Field, 0}, - {"Stat_t.X__pad2", Field, 0}, - {"Stat_t.X__st_birthtim", Field, 2}, - {"Stat_t.X__st_ino", Field, 0}, - {"Stat_t.X__unused", Field, 0}, - {"Statfs", Func, 0}, - {"Statfs_t", Type, 0}, - {"Statfs_t.Asyncreads", Field, 0}, - {"Statfs_t.Asyncwrites", Field, 0}, - {"Statfs_t.Bavail", Field, 0}, - {"Statfs_t.Bfree", Field, 0}, - {"Statfs_t.Blocks", Field, 0}, - {"Statfs_t.Bsize", Field, 0}, - {"Statfs_t.Charspare", Field, 0}, - {"Statfs_t.F_asyncreads", Field, 2}, - {"Statfs_t.F_asyncwrites", Field, 2}, - {"Statfs_t.F_bavail", Field, 2}, - {"Statfs_t.F_bfree", Field, 2}, - {"Statfs_t.F_blocks", Field, 2}, - {"Statfs_t.F_bsize", Field, 2}, - {"Statfs_t.F_ctime", Field, 2}, - {"Statfs_t.F_favail", Field, 2}, - {"Statfs_t.F_ffree", Field, 2}, - {"Statfs_t.F_files", Field, 2}, - {"Statfs_t.F_flags", Field, 2}, - {"Statfs_t.F_fsid", Field, 2}, - {"Statfs_t.F_fstypename", Field, 2}, - {"Statfs_t.F_iosize", Field, 2}, - {"Statfs_t.F_mntfromname", Field, 2}, - {"Statfs_t.F_mntfromspec", Field, 3}, - {"Statfs_t.F_mntonname", Field, 2}, - {"Statfs_t.F_namemax", Field, 2}, - {"Statfs_t.F_owner", Field, 2}, - {"Statfs_t.F_spare", Field, 2}, - {"Statfs_t.F_syncreads", Field, 2}, - {"Statfs_t.F_syncwrites", Field, 2}, - {"Statfs_t.Ffree", Field, 0}, - {"Statfs_t.Files", Field, 0}, - {"Statfs_t.Flags", Field, 0}, - {"Statfs_t.Frsize", Field, 0}, - {"Statfs_t.Fsid", Field, 0}, - {"Statfs_t.Fssubtype", Field, 0}, - {"Statfs_t.Fstypename", Field, 0}, - {"Statfs_t.Iosize", Field, 0}, - {"Statfs_t.Mntfromname", Field, 0}, - {"Statfs_t.Mntonname", Field, 0}, - {"Statfs_t.Mount_info", Field, 2}, - {"Statfs_t.Namelen", Field, 0}, - {"Statfs_t.Namemax", Field, 0}, - {"Statfs_t.Owner", Field, 0}, - {"Statfs_t.Pad_cgo_0", Field, 0}, - {"Statfs_t.Pad_cgo_1", Field, 2}, - {"Statfs_t.Reserved", Field, 0}, - {"Statfs_t.Spare", Field, 0}, - {"Statfs_t.Syncreads", Field, 0}, - {"Statfs_t.Syncwrites", Field, 0}, - {"Statfs_t.Type", Field, 0}, - {"Statfs_t.Version", Field, 0}, - {"Stderr", Var, 0}, - {"Stdin", Var, 0}, - {"Stdout", Var, 0}, - {"StringBytePtr", Func, 0}, - {"StringByteSlice", Func, 0}, - {"StringSlicePtr", Func, 0}, - {"StringToSid", Func, 0}, - {"StringToUTF16", Func, 0}, - {"StringToUTF16Ptr", Func, 0}, - {"Symlink", Func, 0}, - {"Sync", Func, 0}, - {"SyncFileRange", Func, 0}, - {"SysProcAttr", Type, 0}, - {"SysProcAttr.AdditionalInheritedHandles", Field, 17}, - {"SysProcAttr.AmbientCaps", Field, 9}, - {"SysProcAttr.CgroupFD", Field, 20}, - {"SysProcAttr.Chroot", Field, 0}, - {"SysProcAttr.Cloneflags", Field, 2}, - {"SysProcAttr.CmdLine", Field, 0}, - {"SysProcAttr.CreationFlags", Field, 1}, - {"SysProcAttr.Credential", Field, 0}, - {"SysProcAttr.Ctty", Field, 1}, - {"SysProcAttr.Foreground", Field, 5}, - {"SysProcAttr.GidMappings", Field, 4}, - {"SysProcAttr.GidMappingsEnableSetgroups", Field, 5}, - {"SysProcAttr.HideWindow", Field, 0}, - {"SysProcAttr.Jail", Field, 21}, - {"SysProcAttr.NoInheritHandles", Field, 16}, - {"SysProcAttr.Noctty", Field, 0}, - {"SysProcAttr.ParentProcess", Field, 17}, - {"SysProcAttr.Pdeathsig", Field, 0}, - {"SysProcAttr.Pgid", Field, 5}, - {"SysProcAttr.PidFD", Field, 22}, - {"SysProcAttr.ProcessAttributes", Field, 13}, - {"SysProcAttr.Ptrace", Field, 0}, - {"SysProcAttr.Setctty", Field, 0}, - {"SysProcAttr.Setpgid", Field, 0}, - {"SysProcAttr.Setsid", Field, 0}, - {"SysProcAttr.ThreadAttributes", Field, 13}, - {"SysProcAttr.Token", Field, 10}, - {"SysProcAttr.UidMappings", Field, 4}, - {"SysProcAttr.Unshareflags", Field, 7}, - {"SysProcAttr.UseCgroupFD", Field, 20}, - {"SysProcIDMap", Type, 4}, - {"SysProcIDMap.ContainerID", Field, 4}, - {"SysProcIDMap.HostID", Field, 4}, - {"SysProcIDMap.Size", Field, 4}, - {"Syscall", Func, 0}, - {"Syscall12", Func, 0}, - {"Syscall15", Func, 0}, - {"Syscall18", Func, 12}, - {"Syscall6", Func, 0}, - {"Syscall9", Func, 0}, - {"SyscallN", Func, 18}, - {"Sysctl", Func, 0}, - {"SysctlUint32", Func, 0}, - {"Sysctlnode", Type, 2}, - {"Sysctlnode.Flags", Field, 2}, - {"Sysctlnode.Name", Field, 2}, - {"Sysctlnode.Num", Field, 2}, - {"Sysctlnode.Un", Field, 2}, - {"Sysctlnode.Ver", Field, 2}, - {"Sysctlnode.X__rsvd", Field, 2}, - {"Sysctlnode.X_sysctl_desc", Field, 2}, - {"Sysctlnode.X_sysctl_func", Field, 2}, - {"Sysctlnode.X_sysctl_parent", Field, 2}, - {"Sysctlnode.X_sysctl_size", Field, 2}, - {"Sysinfo", Func, 0}, - {"Sysinfo_t", Type, 0}, - {"Sysinfo_t.Bufferram", Field, 0}, - {"Sysinfo_t.Freehigh", Field, 0}, - {"Sysinfo_t.Freeram", Field, 0}, - {"Sysinfo_t.Freeswap", Field, 0}, - {"Sysinfo_t.Loads", Field, 0}, - {"Sysinfo_t.Pad", Field, 0}, - {"Sysinfo_t.Pad_cgo_0", Field, 0}, - {"Sysinfo_t.Pad_cgo_1", Field, 0}, - {"Sysinfo_t.Procs", Field, 0}, - {"Sysinfo_t.Sharedram", Field, 0}, - {"Sysinfo_t.Totalhigh", Field, 0}, - {"Sysinfo_t.Totalram", Field, 0}, - {"Sysinfo_t.Totalswap", Field, 0}, - {"Sysinfo_t.Unit", Field, 0}, - {"Sysinfo_t.Uptime", Field, 0}, - {"Sysinfo_t.X_f", Field, 0}, - {"Systemtime", Type, 0}, - {"Systemtime.Day", Field, 0}, - {"Systemtime.DayOfWeek", Field, 0}, - {"Systemtime.Hour", Field, 0}, - {"Systemtime.Milliseconds", Field, 0}, - {"Systemtime.Minute", Field, 0}, - {"Systemtime.Month", Field, 0}, - {"Systemtime.Second", Field, 0}, - {"Systemtime.Year", Field, 0}, - {"TCGETS", Const, 0}, - {"TCIFLUSH", Const, 1}, - {"TCIOFLUSH", Const, 1}, - {"TCOFLUSH", Const, 1}, - {"TCPInfo", Type, 1}, - {"TCPInfo.Advmss", Field, 1}, - {"TCPInfo.Ato", Field, 1}, - {"TCPInfo.Backoff", Field, 1}, - {"TCPInfo.Ca_state", Field, 1}, - {"TCPInfo.Fackets", Field, 1}, - {"TCPInfo.Last_ack_recv", Field, 1}, - {"TCPInfo.Last_ack_sent", Field, 1}, - {"TCPInfo.Last_data_recv", Field, 1}, - {"TCPInfo.Last_data_sent", Field, 1}, - {"TCPInfo.Lost", Field, 1}, - {"TCPInfo.Options", Field, 1}, - {"TCPInfo.Pad_cgo_0", Field, 1}, - {"TCPInfo.Pmtu", Field, 1}, - {"TCPInfo.Probes", Field, 1}, - {"TCPInfo.Rcv_mss", Field, 1}, - {"TCPInfo.Rcv_rtt", Field, 1}, - {"TCPInfo.Rcv_space", Field, 1}, - {"TCPInfo.Rcv_ssthresh", Field, 1}, - {"TCPInfo.Reordering", Field, 1}, - {"TCPInfo.Retrans", Field, 1}, - {"TCPInfo.Retransmits", Field, 1}, - {"TCPInfo.Rto", Field, 1}, - {"TCPInfo.Rtt", Field, 1}, - {"TCPInfo.Rttvar", Field, 1}, - {"TCPInfo.Sacked", Field, 1}, - {"TCPInfo.Snd_cwnd", Field, 1}, - {"TCPInfo.Snd_mss", Field, 1}, - {"TCPInfo.Snd_ssthresh", Field, 1}, - {"TCPInfo.State", Field, 1}, - {"TCPInfo.Total_retrans", Field, 1}, - {"TCPInfo.Unacked", Field, 1}, - {"TCPKeepalive", Type, 3}, - {"TCPKeepalive.Interval", Field, 3}, - {"TCPKeepalive.OnOff", Field, 3}, - {"TCPKeepalive.Time", Field, 3}, - {"TCP_CA_NAME_MAX", Const, 0}, - {"TCP_CONGCTL", Const, 1}, - {"TCP_CONGESTION", Const, 0}, - {"TCP_CONNECTIONTIMEOUT", Const, 0}, - {"TCP_CORK", Const, 0}, - {"TCP_DEFER_ACCEPT", Const, 0}, - {"TCP_ENABLE_ECN", Const, 16}, - {"TCP_INFO", Const, 0}, - {"TCP_KEEPALIVE", Const, 0}, - {"TCP_KEEPCNT", Const, 0}, - {"TCP_KEEPIDLE", Const, 0}, - {"TCP_KEEPINIT", Const, 1}, - {"TCP_KEEPINTVL", Const, 0}, - {"TCP_LINGER2", Const, 0}, - {"TCP_MAXBURST", Const, 0}, - {"TCP_MAXHLEN", Const, 0}, - {"TCP_MAXOLEN", Const, 0}, - {"TCP_MAXSEG", Const, 0}, - {"TCP_MAXWIN", Const, 0}, - {"TCP_MAX_SACK", Const, 0}, - {"TCP_MAX_WINSHIFT", Const, 0}, - {"TCP_MD5SIG", Const, 0}, - {"TCP_MD5SIG_MAXKEYLEN", Const, 0}, - {"TCP_MINMSS", Const, 0}, - {"TCP_MINMSSOVERLOAD", Const, 0}, - {"TCP_MSS", Const, 0}, - {"TCP_NODELAY", Const, 0}, - {"TCP_NOOPT", Const, 0}, - {"TCP_NOPUSH", Const, 0}, - {"TCP_NOTSENT_LOWAT", Const, 16}, - {"TCP_NSTATES", Const, 1}, - {"TCP_QUICKACK", Const, 0}, - {"TCP_RXT_CONNDROPTIME", Const, 0}, - {"TCP_RXT_FINDROP", Const, 0}, - {"TCP_SACK_ENABLE", Const, 1}, - {"TCP_SENDMOREACKS", Const, 16}, - {"TCP_SYNCNT", Const, 0}, - {"TCP_VENDOR", Const, 3}, - {"TCP_WINDOW_CLAMP", Const, 0}, - {"TCSAFLUSH", Const, 1}, - {"TCSETS", Const, 0}, - {"TF_DISCONNECT", Const, 0}, - {"TF_REUSE_SOCKET", Const, 0}, - {"TF_USE_DEFAULT_WORKER", Const, 0}, - {"TF_USE_KERNEL_APC", Const, 0}, - {"TF_USE_SYSTEM_THREAD", Const, 0}, - {"TF_WRITE_BEHIND", Const, 0}, - {"TH32CS_INHERIT", Const, 4}, - {"TH32CS_SNAPALL", Const, 4}, - {"TH32CS_SNAPHEAPLIST", Const, 4}, - {"TH32CS_SNAPMODULE", Const, 4}, - {"TH32CS_SNAPMODULE32", Const, 4}, - {"TH32CS_SNAPPROCESS", Const, 4}, - {"TH32CS_SNAPTHREAD", Const, 4}, - {"TIME_ZONE_ID_DAYLIGHT", Const, 0}, - {"TIME_ZONE_ID_STANDARD", Const, 0}, - {"TIME_ZONE_ID_UNKNOWN", Const, 0}, - {"TIOCCBRK", Const, 0}, - {"TIOCCDTR", Const, 0}, - {"TIOCCONS", Const, 0}, - {"TIOCDCDTIMESTAMP", Const, 0}, - {"TIOCDRAIN", Const, 0}, - {"TIOCDSIMICROCODE", Const, 0}, - {"TIOCEXCL", Const, 0}, - {"TIOCEXT", Const, 0}, - {"TIOCFLAG_CDTRCTS", Const, 1}, - {"TIOCFLAG_CLOCAL", Const, 1}, - {"TIOCFLAG_CRTSCTS", Const, 1}, - {"TIOCFLAG_MDMBUF", Const, 1}, - {"TIOCFLAG_PPS", Const, 1}, - {"TIOCFLAG_SOFTCAR", Const, 1}, - {"TIOCFLUSH", Const, 0}, - {"TIOCGDEV", Const, 0}, - {"TIOCGDRAINWAIT", Const, 0}, - {"TIOCGETA", Const, 0}, - {"TIOCGETD", Const, 0}, - {"TIOCGFLAGS", Const, 1}, - {"TIOCGICOUNT", Const, 0}, - {"TIOCGLCKTRMIOS", Const, 0}, - {"TIOCGLINED", Const, 1}, - {"TIOCGPGRP", Const, 0}, - {"TIOCGPTN", Const, 0}, - {"TIOCGQSIZE", Const, 1}, - {"TIOCGRANTPT", Const, 1}, - {"TIOCGRS485", Const, 0}, - {"TIOCGSERIAL", Const, 0}, - {"TIOCGSID", Const, 0}, - {"TIOCGSIZE", Const, 1}, - {"TIOCGSOFTCAR", Const, 0}, - {"TIOCGTSTAMP", Const, 1}, - {"TIOCGWINSZ", Const, 0}, - {"TIOCINQ", Const, 0}, - {"TIOCIXOFF", Const, 0}, - {"TIOCIXON", Const, 0}, - {"TIOCLINUX", Const, 0}, - {"TIOCMBIC", Const, 0}, - {"TIOCMBIS", Const, 0}, - {"TIOCMGDTRWAIT", Const, 0}, - {"TIOCMGET", Const, 0}, - {"TIOCMIWAIT", Const, 0}, - {"TIOCMODG", Const, 0}, - {"TIOCMODS", Const, 0}, - {"TIOCMSDTRWAIT", Const, 0}, - {"TIOCMSET", Const, 0}, - {"TIOCM_CAR", Const, 0}, - {"TIOCM_CD", Const, 0}, - {"TIOCM_CTS", Const, 0}, - {"TIOCM_DCD", Const, 0}, - {"TIOCM_DSR", Const, 0}, - {"TIOCM_DTR", Const, 0}, - {"TIOCM_LE", Const, 0}, - {"TIOCM_RI", Const, 0}, - {"TIOCM_RNG", Const, 0}, - {"TIOCM_RTS", Const, 0}, - {"TIOCM_SR", Const, 0}, - {"TIOCM_ST", Const, 0}, - {"TIOCNOTTY", Const, 0}, - {"TIOCNXCL", Const, 0}, - {"TIOCOUTQ", Const, 0}, - {"TIOCPKT", Const, 0}, - {"TIOCPKT_DATA", Const, 0}, - {"TIOCPKT_DOSTOP", Const, 0}, - {"TIOCPKT_FLUSHREAD", Const, 0}, - {"TIOCPKT_FLUSHWRITE", Const, 0}, - {"TIOCPKT_IOCTL", Const, 0}, - {"TIOCPKT_NOSTOP", Const, 0}, - {"TIOCPKT_START", Const, 0}, - {"TIOCPKT_STOP", Const, 0}, - {"TIOCPTMASTER", Const, 0}, - {"TIOCPTMGET", Const, 1}, - {"TIOCPTSNAME", Const, 1}, - {"TIOCPTYGNAME", Const, 0}, - {"TIOCPTYGRANT", Const, 0}, - {"TIOCPTYUNLK", Const, 0}, - {"TIOCRCVFRAME", Const, 1}, - {"TIOCREMOTE", Const, 0}, - {"TIOCSBRK", Const, 0}, - {"TIOCSCONS", Const, 0}, - {"TIOCSCTTY", Const, 0}, - {"TIOCSDRAINWAIT", Const, 0}, - {"TIOCSDTR", Const, 0}, - {"TIOCSERCONFIG", Const, 0}, - {"TIOCSERGETLSR", Const, 0}, - {"TIOCSERGETMULTI", Const, 0}, - {"TIOCSERGSTRUCT", Const, 0}, - {"TIOCSERGWILD", Const, 0}, - {"TIOCSERSETMULTI", Const, 0}, - {"TIOCSERSWILD", Const, 0}, - {"TIOCSER_TEMT", Const, 0}, - {"TIOCSETA", Const, 0}, - {"TIOCSETAF", Const, 0}, - {"TIOCSETAW", Const, 0}, - {"TIOCSETD", Const, 0}, - {"TIOCSFLAGS", Const, 1}, - {"TIOCSIG", Const, 0}, - {"TIOCSLCKTRMIOS", Const, 0}, - {"TIOCSLINED", Const, 1}, - {"TIOCSPGRP", Const, 0}, - {"TIOCSPTLCK", Const, 0}, - {"TIOCSQSIZE", Const, 1}, - {"TIOCSRS485", Const, 0}, - {"TIOCSSERIAL", Const, 0}, - {"TIOCSSIZE", Const, 1}, - {"TIOCSSOFTCAR", Const, 0}, - {"TIOCSTART", Const, 0}, - {"TIOCSTAT", Const, 0}, - {"TIOCSTI", Const, 0}, - {"TIOCSTOP", Const, 0}, - {"TIOCSTSTAMP", Const, 1}, - {"TIOCSWINSZ", Const, 0}, - {"TIOCTIMESTAMP", Const, 0}, - {"TIOCUCNTL", Const, 0}, - {"TIOCVHANGUP", Const, 0}, - {"TIOCXMTFRAME", Const, 1}, - {"TOKEN_ADJUST_DEFAULT", Const, 0}, - {"TOKEN_ADJUST_GROUPS", Const, 0}, - {"TOKEN_ADJUST_PRIVILEGES", Const, 0}, - {"TOKEN_ADJUST_SESSIONID", Const, 11}, - {"TOKEN_ALL_ACCESS", Const, 0}, - {"TOKEN_ASSIGN_PRIMARY", Const, 0}, - {"TOKEN_DUPLICATE", Const, 0}, - {"TOKEN_EXECUTE", Const, 0}, - {"TOKEN_IMPERSONATE", Const, 0}, - {"TOKEN_QUERY", Const, 0}, - {"TOKEN_QUERY_SOURCE", Const, 0}, - {"TOKEN_READ", Const, 0}, - {"TOKEN_WRITE", Const, 0}, - {"TOSTOP", Const, 0}, - {"TRUNCATE_EXISTING", Const, 0}, - {"TUNATTACHFILTER", Const, 0}, - {"TUNDETACHFILTER", Const, 0}, - {"TUNGETFEATURES", Const, 0}, - {"TUNGETIFF", Const, 0}, - {"TUNGETSNDBUF", Const, 0}, - {"TUNGETVNETHDRSZ", Const, 0}, - {"TUNSETDEBUG", Const, 0}, - {"TUNSETGROUP", Const, 0}, - {"TUNSETIFF", Const, 0}, - {"TUNSETLINK", Const, 0}, - {"TUNSETNOCSUM", Const, 0}, - {"TUNSETOFFLOAD", Const, 0}, - {"TUNSETOWNER", Const, 0}, - {"TUNSETPERSIST", Const, 0}, - {"TUNSETSNDBUF", Const, 0}, - {"TUNSETTXFILTER", Const, 0}, - {"TUNSETVNETHDRSZ", Const, 0}, - {"Tee", Func, 0}, - {"TerminateProcess", Func, 0}, - {"Termios", Type, 0}, - {"Termios.Cc", Field, 0}, - {"Termios.Cflag", Field, 0}, - {"Termios.Iflag", Field, 0}, - {"Termios.Ispeed", Field, 0}, - {"Termios.Lflag", Field, 0}, - {"Termios.Line", Field, 0}, - {"Termios.Oflag", Field, 0}, - {"Termios.Ospeed", Field, 0}, - {"Termios.Pad_cgo_0", Field, 0}, - {"Tgkill", Func, 0}, - {"Time", Func, 0}, - {"Time_t", Type, 0}, - {"Times", Func, 0}, - {"Timespec", Type, 0}, - {"Timespec.Nsec", Field, 0}, - {"Timespec.Pad_cgo_0", Field, 2}, - {"Timespec.Sec", Field, 0}, - {"TimespecToNsec", Func, 0}, - {"Timeval", Type, 0}, - {"Timeval.Pad_cgo_0", Field, 0}, - {"Timeval.Sec", Field, 0}, - {"Timeval.Usec", Field, 0}, - {"Timeval32", Type, 0}, - {"Timeval32.Sec", Field, 0}, - {"Timeval32.Usec", Field, 0}, - {"TimevalToNsec", Func, 0}, - {"Timex", Type, 0}, - {"Timex.Calcnt", Field, 0}, - {"Timex.Constant", Field, 0}, - {"Timex.Errcnt", Field, 0}, - {"Timex.Esterror", Field, 0}, - {"Timex.Freq", Field, 0}, - {"Timex.Jitcnt", Field, 0}, - {"Timex.Jitter", Field, 0}, - {"Timex.Maxerror", Field, 0}, - {"Timex.Modes", Field, 0}, - {"Timex.Offset", Field, 0}, - {"Timex.Pad_cgo_0", Field, 0}, - {"Timex.Pad_cgo_1", Field, 0}, - {"Timex.Pad_cgo_2", Field, 0}, - {"Timex.Pad_cgo_3", Field, 0}, - {"Timex.Ppsfreq", Field, 0}, - {"Timex.Precision", Field, 0}, - {"Timex.Shift", Field, 0}, - {"Timex.Stabil", Field, 0}, - {"Timex.Status", Field, 0}, - {"Timex.Stbcnt", Field, 0}, - {"Timex.Tai", Field, 0}, - {"Timex.Tick", Field, 0}, - {"Timex.Time", Field, 0}, - {"Timex.Tolerance", Field, 0}, - {"Timezoneinformation", Type, 0}, - {"Timezoneinformation.Bias", Field, 0}, - {"Timezoneinformation.DaylightBias", Field, 0}, - {"Timezoneinformation.DaylightDate", Field, 0}, - {"Timezoneinformation.DaylightName", Field, 0}, - {"Timezoneinformation.StandardBias", Field, 0}, - {"Timezoneinformation.StandardDate", Field, 0}, - {"Timezoneinformation.StandardName", Field, 0}, - {"Tms", Type, 0}, - {"Tms.Cstime", Field, 0}, - {"Tms.Cutime", Field, 0}, - {"Tms.Stime", Field, 0}, - {"Tms.Utime", Field, 0}, - {"Token", Type, 0}, - {"TokenAccessInformation", Const, 0}, - {"TokenAuditPolicy", Const, 0}, - {"TokenDefaultDacl", Const, 0}, - {"TokenElevation", Const, 0}, - {"TokenElevationType", Const, 0}, - {"TokenGroups", Const, 0}, - {"TokenGroupsAndPrivileges", Const, 0}, - {"TokenHasRestrictions", Const, 0}, - {"TokenImpersonationLevel", Const, 0}, - {"TokenIntegrityLevel", Const, 0}, - {"TokenLinkedToken", Const, 0}, - {"TokenLogonSid", Const, 0}, - {"TokenMandatoryPolicy", Const, 0}, - {"TokenOrigin", Const, 0}, - {"TokenOwner", Const, 0}, - {"TokenPrimaryGroup", Const, 0}, - {"TokenPrivileges", Const, 0}, - {"TokenRestrictedSids", Const, 0}, - {"TokenSandBoxInert", Const, 0}, - {"TokenSessionId", Const, 0}, - {"TokenSessionReference", Const, 0}, - {"TokenSource", Const, 0}, - {"TokenStatistics", Const, 0}, - {"TokenType", Const, 0}, - {"TokenUIAccess", Const, 0}, - {"TokenUser", Const, 0}, - {"TokenVirtualizationAllowed", Const, 0}, - {"TokenVirtualizationEnabled", Const, 0}, - {"Tokenprimarygroup", Type, 0}, - {"Tokenprimarygroup.PrimaryGroup", Field, 0}, - {"Tokenuser", Type, 0}, - {"Tokenuser.User", Field, 0}, - {"TranslateAccountName", Func, 0}, - {"TranslateName", Func, 0}, - {"TransmitFile", Func, 0}, - {"TransmitFileBuffers", Type, 0}, - {"TransmitFileBuffers.Head", Field, 0}, - {"TransmitFileBuffers.HeadLength", Field, 0}, - {"TransmitFileBuffers.Tail", Field, 0}, - {"TransmitFileBuffers.TailLength", Field, 0}, - {"Truncate", Func, 0}, - {"UNIX_PATH_MAX", Const, 12}, - {"USAGE_MATCH_TYPE_AND", Const, 0}, - {"USAGE_MATCH_TYPE_OR", Const, 0}, - {"UTF16FromString", Func, 1}, - {"UTF16PtrFromString", Func, 1}, - {"UTF16ToString", Func, 0}, - {"Ucred", Type, 0}, - {"Ucred.Gid", Field, 0}, - {"Ucred.Pid", Field, 0}, - {"Ucred.Uid", Field, 0}, - {"Umask", Func, 0}, - {"Uname", Func, 0}, - {"Undelete", Func, 0}, - {"UnixCredentials", Func, 0}, - {"UnixRights", Func, 0}, - {"Unlink", Func, 0}, - {"Unlinkat", Func, 0}, - {"UnmapViewOfFile", Func, 0}, - {"Unmount", Func, 0}, - {"Unsetenv", Func, 4}, - {"Unshare", Func, 0}, - {"UserInfo10", Type, 0}, - {"UserInfo10.Comment", Field, 0}, - {"UserInfo10.FullName", Field, 0}, - {"UserInfo10.Name", Field, 0}, - {"UserInfo10.UsrComment", Field, 0}, - {"Ustat", Func, 0}, - {"Ustat_t", Type, 0}, - {"Ustat_t.Fname", Field, 0}, - {"Ustat_t.Fpack", Field, 0}, - {"Ustat_t.Pad_cgo_0", Field, 0}, - {"Ustat_t.Pad_cgo_1", Field, 0}, - {"Ustat_t.Tfree", Field, 0}, - {"Ustat_t.Tinode", Field, 0}, - {"Utimbuf", Type, 0}, - {"Utimbuf.Actime", Field, 0}, - {"Utimbuf.Modtime", Field, 0}, - {"Utime", Func, 0}, - {"Utimes", Func, 0}, - {"UtimesNano", Func, 1}, - {"Utsname", Type, 0}, - {"Utsname.Domainname", Field, 0}, - {"Utsname.Machine", Field, 0}, - {"Utsname.Nodename", Field, 0}, - {"Utsname.Release", Field, 0}, - {"Utsname.Sysname", Field, 0}, - {"Utsname.Version", Field, 0}, - {"VDISCARD", Const, 0}, - {"VDSUSP", Const, 1}, - {"VEOF", Const, 0}, - {"VEOL", Const, 0}, - {"VEOL2", Const, 0}, - {"VERASE", Const, 0}, - {"VERASE2", Const, 1}, - {"VINTR", Const, 0}, - {"VKILL", Const, 0}, - {"VLNEXT", Const, 0}, - {"VMIN", Const, 0}, - {"VQUIT", Const, 0}, - {"VREPRINT", Const, 0}, - {"VSTART", Const, 0}, - {"VSTATUS", Const, 1}, - {"VSTOP", Const, 0}, - {"VSUSP", Const, 0}, - {"VSWTC", Const, 0}, - {"VT0", Const, 1}, - {"VT1", Const, 1}, - {"VTDLY", Const, 1}, - {"VTIME", Const, 0}, - {"VWERASE", Const, 0}, - {"VirtualLock", Func, 0}, - {"VirtualUnlock", Func, 0}, - {"WAIT_ABANDONED", Const, 0}, - {"WAIT_FAILED", Const, 0}, - {"WAIT_OBJECT_0", Const, 0}, - {"WAIT_TIMEOUT", Const, 0}, - {"WALL", Const, 0}, - {"WALLSIG", Const, 1}, - {"WALTSIG", Const, 1}, - {"WCLONE", Const, 0}, - {"WCONTINUED", Const, 0}, - {"WCOREFLAG", Const, 0}, - {"WEXITED", Const, 0}, - {"WLINUXCLONE", Const, 0}, - {"WNOHANG", Const, 0}, - {"WNOTHREAD", Const, 0}, - {"WNOWAIT", Const, 0}, - {"WNOZOMBIE", Const, 1}, - {"WOPTSCHECKED", Const, 1}, - {"WORDSIZE", Const, 0}, - {"WSABuf", Type, 0}, - {"WSABuf.Buf", Field, 0}, - {"WSABuf.Len", Field, 0}, - {"WSACleanup", Func, 0}, - {"WSADESCRIPTION_LEN", Const, 0}, - {"WSAData", Type, 0}, - {"WSAData.Description", Field, 0}, - {"WSAData.HighVersion", Field, 0}, - {"WSAData.MaxSockets", Field, 0}, - {"WSAData.MaxUdpDg", Field, 0}, - {"WSAData.SystemStatus", Field, 0}, - {"WSAData.VendorInfo", Field, 0}, - {"WSAData.Version", Field, 0}, - {"WSAEACCES", Const, 2}, - {"WSAECONNABORTED", Const, 9}, - {"WSAECONNRESET", Const, 3}, - {"WSAENOPROTOOPT", Const, 23}, - {"WSAEnumProtocols", Func, 2}, - {"WSAID_CONNECTEX", Var, 1}, - {"WSAIoctl", Func, 0}, - {"WSAPROTOCOL_LEN", Const, 2}, - {"WSAProtocolChain", Type, 2}, - {"WSAProtocolChain.ChainEntries", Field, 2}, - {"WSAProtocolChain.ChainLen", Field, 2}, - {"WSAProtocolInfo", Type, 2}, - {"WSAProtocolInfo.AddressFamily", Field, 2}, - {"WSAProtocolInfo.CatalogEntryId", Field, 2}, - {"WSAProtocolInfo.MaxSockAddr", Field, 2}, - {"WSAProtocolInfo.MessageSize", Field, 2}, - {"WSAProtocolInfo.MinSockAddr", Field, 2}, - {"WSAProtocolInfo.NetworkByteOrder", Field, 2}, - {"WSAProtocolInfo.Protocol", Field, 2}, - {"WSAProtocolInfo.ProtocolChain", Field, 2}, - {"WSAProtocolInfo.ProtocolMaxOffset", Field, 2}, - {"WSAProtocolInfo.ProtocolName", Field, 2}, - {"WSAProtocolInfo.ProviderFlags", Field, 2}, - {"WSAProtocolInfo.ProviderId", Field, 2}, - {"WSAProtocolInfo.ProviderReserved", Field, 2}, - {"WSAProtocolInfo.SecurityScheme", Field, 2}, - {"WSAProtocolInfo.ServiceFlags1", Field, 2}, - {"WSAProtocolInfo.ServiceFlags2", Field, 2}, - {"WSAProtocolInfo.ServiceFlags3", Field, 2}, - {"WSAProtocolInfo.ServiceFlags4", Field, 2}, - {"WSAProtocolInfo.SocketType", Field, 2}, - {"WSAProtocolInfo.Version", Field, 2}, - {"WSARecv", Func, 0}, - {"WSARecvFrom", Func, 0}, - {"WSASYS_STATUS_LEN", Const, 0}, - {"WSASend", Func, 0}, - {"WSASendTo", Func, 0}, - {"WSASendto", Func, 0}, - {"WSAStartup", Func, 0}, - {"WSTOPPED", Const, 0}, - {"WTRAPPED", Const, 1}, - {"WUNTRACED", Const, 0}, - {"Wait4", Func, 0}, - {"WaitForSingleObject", Func, 0}, - {"WaitStatus", Type, 0}, - {"WaitStatus.ExitCode", Field, 0}, - {"Win32FileAttributeData", Type, 0}, - {"Win32FileAttributeData.CreationTime", Field, 0}, - {"Win32FileAttributeData.FileAttributes", Field, 0}, - {"Win32FileAttributeData.FileSizeHigh", Field, 0}, - {"Win32FileAttributeData.FileSizeLow", Field, 0}, - {"Win32FileAttributeData.LastAccessTime", Field, 0}, - {"Win32FileAttributeData.LastWriteTime", Field, 0}, - {"Win32finddata", Type, 0}, - {"Win32finddata.AlternateFileName", Field, 0}, - {"Win32finddata.CreationTime", Field, 0}, - {"Win32finddata.FileAttributes", Field, 0}, - {"Win32finddata.FileName", Field, 0}, - {"Win32finddata.FileSizeHigh", Field, 0}, - {"Win32finddata.FileSizeLow", Field, 0}, - {"Win32finddata.LastAccessTime", Field, 0}, - {"Win32finddata.LastWriteTime", Field, 0}, - {"Win32finddata.Reserved0", Field, 0}, - {"Win32finddata.Reserved1", Field, 0}, - {"Write", Func, 0}, - {"WriteConsole", Func, 1}, - {"WriteFile", Func, 0}, - {"X509_ASN_ENCODING", Const, 0}, - {"XCASE", Const, 0}, - {"XP1_CONNECTIONLESS", Const, 2}, - {"XP1_CONNECT_DATA", Const, 2}, - {"XP1_DISCONNECT_DATA", Const, 2}, - {"XP1_EXPEDITED_DATA", Const, 2}, - {"XP1_GRACEFUL_CLOSE", Const, 2}, - {"XP1_GUARANTEED_DELIVERY", Const, 2}, - {"XP1_GUARANTEED_ORDER", Const, 2}, - {"XP1_IFS_HANDLES", Const, 2}, - {"XP1_MESSAGE_ORIENTED", Const, 2}, - {"XP1_MULTIPOINT_CONTROL_PLANE", Const, 2}, - {"XP1_MULTIPOINT_DATA_PLANE", Const, 2}, - {"XP1_PARTIAL_MESSAGE", Const, 2}, - {"XP1_PSEUDO_STREAM", Const, 2}, - {"XP1_QOS_SUPPORTED", Const, 2}, - {"XP1_SAN_SUPPORT_SDP", Const, 2}, - {"XP1_SUPPORT_BROADCAST", Const, 2}, - {"XP1_SUPPORT_MULTIPOINT", Const, 2}, - {"XP1_UNI_RECV", Const, 2}, - {"XP1_UNI_SEND", Const, 2}, + {"(*Cmsghdr).SetLen", Method, 0, ""}, + {"(*DLL).FindProc", Method, 0, ""}, + {"(*DLL).MustFindProc", Method, 0, ""}, + {"(*DLL).Release", Method, 0, ""}, + {"(*DLLError).Error", Method, 0, ""}, + {"(*DLLError).Unwrap", Method, 16, ""}, + {"(*Filetime).Nanoseconds", Method, 0, ""}, + {"(*Iovec).SetLen", Method, 0, ""}, + {"(*LazyDLL).Handle", Method, 0, ""}, + {"(*LazyDLL).Load", Method, 0, ""}, + {"(*LazyDLL).NewProc", Method, 0, ""}, + {"(*LazyProc).Addr", Method, 0, ""}, + {"(*LazyProc).Call", Method, 0, ""}, + {"(*LazyProc).Find", Method, 0, ""}, + {"(*Msghdr).SetControllen", Method, 0, ""}, + {"(*Proc).Addr", Method, 0, ""}, + {"(*Proc).Call", Method, 0, ""}, + {"(*PtraceRegs).PC", Method, 0, ""}, + {"(*PtraceRegs).SetPC", Method, 0, ""}, + {"(*RawSockaddrAny).Sockaddr", Method, 0, ""}, + {"(*SID).Copy", Method, 0, ""}, + {"(*SID).Len", Method, 0, ""}, + {"(*SID).LookupAccount", Method, 0, ""}, + {"(*SID).String", Method, 0, ""}, + {"(*Timespec).Nano", Method, 0, ""}, + {"(*Timespec).Unix", Method, 0, ""}, + {"(*Timeval).Nano", Method, 0, ""}, + {"(*Timeval).Nanoseconds", Method, 0, ""}, + {"(*Timeval).Unix", Method, 0, ""}, + {"(Errno).Error", Method, 0, ""}, + {"(Errno).Is", Method, 13, ""}, + {"(Errno).Temporary", Method, 0, ""}, + {"(Errno).Timeout", Method, 0, ""}, + {"(Signal).Signal", Method, 0, ""}, + {"(Signal).String", Method, 0, ""}, + {"(Token).Close", Method, 0, ""}, + {"(Token).GetTokenPrimaryGroup", Method, 0, ""}, + {"(Token).GetTokenUser", Method, 0, ""}, + {"(Token).GetUserProfileDirectory", Method, 0, ""}, + {"(WaitStatus).Continued", Method, 0, ""}, + {"(WaitStatus).CoreDump", Method, 0, ""}, + {"(WaitStatus).ExitStatus", Method, 0, ""}, + {"(WaitStatus).Exited", Method, 0, ""}, + {"(WaitStatus).Signal", Method, 0, ""}, + {"(WaitStatus).Signaled", Method, 0, ""}, + {"(WaitStatus).StopSignal", Method, 0, ""}, + {"(WaitStatus).Stopped", Method, 0, ""}, + {"(WaitStatus).TrapCause", Method, 0, ""}, + {"AF_ALG", Const, 0, ""}, + {"AF_APPLETALK", Const, 0, ""}, + {"AF_ARP", Const, 0, ""}, + {"AF_ASH", Const, 0, ""}, + {"AF_ATM", Const, 0, ""}, + {"AF_ATMPVC", Const, 0, ""}, + {"AF_ATMSVC", Const, 0, ""}, + {"AF_AX25", Const, 0, ""}, + {"AF_BLUETOOTH", Const, 0, ""}, + {"AF_BRIDGE", Const, 0, ""}, + {"AF_CAIF", Const, 0, ""}, + {"AF_CAN", Const, 0, ""}, + {"AF_CCITT", Const, 0, ""}, + {"AF_CHAOS", Const, 0, ""}, + {"AF_CNT", Const, 0, ""}, + {"AF_COIP", Const, 0, ""}, + {"AF_DATAKIT", Const, 0, ""}, + {"AF_DECnet", Const, 0, ""}, + {"AF_DLI", Const, 0, ""}, + {"AF_E164", Const, 0, ""}, + {"AF_ECMA", Const, 0, ""}, + {"AF_ECONET", Const, 0, ""}, + {"AF_ENCAP", Const, 1, ""}, + {"AF_FILE", Const, 0, ""}, + {"AF_HYLINK", Const, 0, ""}, + {"AF_IEEE80211", Const, 0, ""}, + {"AF_IEEE802154", Const, 0, ""}, + {"AF_IMPLINK", Const, 0, ""}, + {"AF_INET", Const, 0, ""}, + {"AF_INET6", Const, 0, ""}, + {"AF_INET6_SDP", Const, 3, ""}, + {"AF_INET_SDP", Const, 3, ""}, + {"AF_IPX", Const, 0, ""}, + {"AF_IRDA", Const, 0, ""}, + {"AF_ISDN", Const, 0, ""}, + {"AF_ISO", Const, 0, ""}, + {"AF_IUCV", Const, 0, ""}, + {"AF_KEY", Const, 0, ""}, + {"AF_LAT", Const, 0, ""}, + {"AF_LINK", Const, 0, ""}, + {"AF_LLC", Const, 0, ""}, + {"AF_LOCAL", Const, 0, ""}, + {"AF_MAX", Const, 0, ""}, + {"AF_MPLS", Const, 1, ""}, + {"AF_NATM", Const, 0, ""}, + {"AF_NDRV", Const, 0, ""}, + {"AF_NETBEUI", Const, 0, ""}, + {"AF_NETBIOS", Const, 0, ""}, + {"AF_NETGRAPH", Const, 0, ""}, + {"AF_NETLINK", Const, 0, ""}, + {"AF_NETROM", Const, 0, ""}, + {"AF_NS", Const, 0, ""}, + {"AF_OROUTE", Const, 1, ""}, + {"AF_OSI", Const, 0, ""}, + {"AF_PACKET", Const, 0, ""}, + {"AF_PHONET", Const, 0, ""}, + {"AF_PPP", Const, 0, ""}, + {"AF_PPPOX", Const, 0, ""}, + {"AF_PUP", Const, 0, ""}, + {"AF_RDS", Const, 0, ""}, + {"AF_RESERVED_36", Const, 0, ""}, + {"AF_ROSE", Const, 0, ""}, + {"AF_ROUTE", Const, 0, ""}, + {"AF_RXRPC", Const, 0, ""}, + {"AF_SCLUSTER", Const, 0, ""}, + {"AF_SECURITY", Const, 0, ""}, + {"AF_SIP", Const, 0, ""}, + {"AF_SLOW", Const, 0, ""}, + {"AF_SNA", Const, 0, ""}, + {"AF_SYSTEM", Const, 0, ""}, + {"AF_TIPC", Const, 0, ""}, + {"AF_UNIX", Const, 0, ""}, + {"AF_UNSPEC", Const, 0, ""}, + {"AF_UTUN", Const, 16, ""}, + {"AF_VENDOR00", Const, 0, ""}, + {"AF_VENDOR01", Const, 0, ""}, + {"AF_VENDOR02", Const, 0, ""}, + {"AF_VENDOR03", Const, 0, ""}, + {"AF_VENDOR04", Const, 0, ""}, + {"AF_VENDOR05", Const, 0, ""}, + {"AF_VENDOR06", Const, 0, ""}, + {"AF_VENDOR07", Const, 0, ""}, + {"AF_VENDOR08", Const, 0, ""}, + {"AF_VENDOR09", Const, 0, ""}, + {"AF_VENDOR10", Const, 0, ""}, + {"AF_VENDOR11", Const, 0, ""}, + {"AF_VENDOR12", Const, 0, ""}, + {"AF_VENDOR13", Const, 0, ""}, + {"AF_VENDOR14", Const, 0, ""}, + {"AF_VENDOR15", Const, 0, ""}, + {"AF_VENDOR16", Const, 0, ""}, + {"AF_VENDOR17", Const, 0, ""}, + {"AF_VENDOR18", Const, 0, ""}, + {"AF_VENDOR19", Const, 0, ""}, + {"AF_VENDOR20", Const, 0, ""}, + {"AF_VENDOR21", Const, 0, ""}, + {"AF_VENDOR22", Const, 0, ""}, + {"AF_VENDOR23", Const, 0, ""}, + {"AF_VENDOR24", Const, 0, ""}, + {"AF_VENDOR25", Const, 0, ""}, + {"AF_VENDOR26", Const, 0, ""}, + {"AF_VENDOR27", Const, 0, ""}, + {"AF_VENDOR28", Const, 0, ""}, + {"AF_VENDOR29", Const, 0, ""}, + {"AF_VENDOR30", Const, 0, ""}, + {"AF_VENDOR31", Const, 0, ""}, + {"AF_VENDOR32", Const, 0, ""}, + {"AF_VENDOR33", Const, 0, ""}, + {"AF_VENDOR34", Const, 0, ""}, + {"AF_VENDOR35", Const, 0, ""}, + {"AF_VENDOR36", Const, 0, ""}, + {"AF_VENDOR37", Const, 0, ""}, + {"AF_VENDOR38", Const, 0, ""}, + {"AF_VENDOR39", Const, 0, ""}, + {"AF_VENDOR40", Const, 0, ""}, + {"AF_VENDOR41", Const, 0, ""}, + {"AF_VENDOR42", Const, 0, ""}, + {"AF_VENDOR43", Const, 0, ""}, + {"AF_VENDOR44", Const, 0, ""}, + {"AF_VENDOR45", Const, 0, ""}, + {"AF_VENDOR46", Const, 0, ""}, + {"AF_VENDOR47", Const, 0, ""}, + {"AF_WANPIPE", Const, 0, ""}, + {"AF_X25", Const, 0, ""}, + {"AI_CANONNAME", Const, 1, ""}, + {"AI_NUMERICHOST", Const, 1, ""}, + {"AI_PASSIVE", Const, 1, ""}, + {"APPLICATION_ERROR", Const, 0, ""}, + {"ARPHRD_ADAPT", Const, 0, ""}, + {"ARPHRD_APPLETLK", Const, 0, ""}, + {"ARPHRD_ARCNET", Const, 0, ""}, + {"ARPHRD_ASH", Const, 0, ""}, + {"ARPHRD_ATM", Const, 0, ""}, + {"ARPHRD_AX25", Const, 0, ""}, + {"ARPHRD_BIF", Const, 0, ""}, + {"ARPHRD_CHAOS", Const, 0, ""}, + {"ARPHRD_CISCO", Const, 0, ""}, + {"ARPHRD_CSLIP", Const, 0, ""}, + {"ARPHRD_CSLIP6", Const, 0, ""}, + {"ARPHRD_DDCMP", Const, 0, ""}, + {"ARPHRD_DLCI", Const, 0, ""}, + {"ARPHRD_ECONET", Const, 0, ""}, + {"ARPHRD_EETHER", Const, 0, ""}, + {"ARPHRD_ETHER", Const, 0, ""}, + {"ARPHRD_EUI64", Const, 0, ""}, + {"ARPHRD_FCAL", Const, 0, ""}, + {"ARPHRD_FCFABRIC", Const, 0, ""}, + {"ARPHRD_FCPL", Const, 0, ""}, + {"ARPHRD_FCPP", Const, 0, ""}, + {"ARPHRD_FDDI", Const, 0, ""}, + {"ARPHRD_FRAD", Const, 0, ""}, + {"ARPHRD_FRELAY", Const, 1, ""}, + {"ARPHRD_HDLC", Const, 0, ""}, + {"ARPHRD_HIPPI", Const, 0, ""}, + {"ARPHRD_HWX25", Const, 0, ""}, + {"ARPHRD_IEEE1394", Const, 0, ""}, + {"ARPHRD_IEEE802", Const, 0, ""}, + {"ARPHRD_IEEE80211", Const, 0, ""}, + {"ARPHRD_IEEE80211_PRISM", Const, 0, ""}, + {"ARPHRD_IEEE80211_RADIOTAP", Const, 0, ""}, + {"ARPHRD_IEEE802154", Const, 0, ""}, + {"ARPHRD_IEEE802154_PHY", Const, 0, ""}, + {"ARPHRD_IEEE802_TR", Const, 0, ""}, + {"ARPHRD_INFINIBAND", Const, 0, ""}, + {"ARPHRD_IPDDP", Const, 0, ""}, + {"ARPHRD_IPGRE", Const, 0, ""}, + {"ARPHRD_IRDA", Const, 0, ""}, + {"ARPHRD_LAPB", Const, 0, ""}, + {"ARPHRD_LOCALTLK", Const, 0, ""}, + {"ARPHRD_LOOPBACK", Const, 0, ""}, + {"ARPHRD_METRICOM", Const, 0, ""}, + {"ARPHRD_NETROM", Const, 0, ""}, + {"ARPHRD_NONE", Const, 0, ""}, + {"ARPHRD_PIMREG", Const, 0, ""}, + {"ARPHRD_PPP", Const, 0, ""}, + {"ARPHRD_PRONET", Const, 0, ""}, + {"ARPHRD_RAWHDLC", Const, 0, ""}, + {"ARPHRD_ROSE", Const, 0, ""}, + {"ARPHRD_RSRVD", Const, 0, ""}, + {"ARPHRD_SIT", Const, 0, ""}, + {"ARPHRD_SKIP", Const, 0, ""}, + {"ARPHRD_SLIP", Const, 0, ""}, + {"ARPHRD_SLIP6", Const, 0, ""}, + {"ARPHRD_STRIP", Const, 1, ""}, + {"ARPHRD_TUNNEL", Const, 0, ""}, + {"ARPHRD_TUNNEL6", Const, 0, ""}, + {"ARPHRD_VOID", Const, 0, ""}, + {"ARPHRD_X25", Const, 0, ""}, + {"AUTHTYPE_CLIENT", Const, 0, ""}, + {"AUTHTYPE_SERVER", Const, 0, ""}, + {"Accept", Func, 0, "func(fd int) (nfd int, sa Sockaddr, err error)"}, + {"Accept4", Func, 1, "func(fd int, flags int) (nfd int, sa Sockaddr, err error)"}, + {"AcceptEx", Func, 0, ""}, + {"Access", Func, 0, "func(path string, mode uint32) (err error)"}, + {"Acct", Func, 0, "func(path string) (err error)"}, + {"AddrinfoW", Type, 1, ""}, + {"AddrinfoW.Addr", Field, 1, ""}, + {"AddrinfoW.Addrlen", Field, 1, ""}, + {"AddrinfoW.Canonname", Field, 1, ""}, + {"AddrinfoW.Family", Field, 1, ""}, + {"AddrinfoW.Flags", Field, 1, ""}, + {"AddrinfoW.Next", Field, 1, ""}, + {"AddrinfoW.Protocol", Field, 1, ""}, + {"AddrinfoW.Socktype", Field, 1, ""}, + {"Adjtime", Func, 0, ""}, + {"Adjtimex", Func, 0, "func(buf *Timex) (state int, err error)"}, + {"AllThreadsSyscall", Func, 16, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, + {"AllThreadsSyscall6", Func, 16, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr, a4 uintptr, a5 uintptr, a6 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, + {"AttachLsf", Func, 0, "func(fd int, i []SockFilter) error"}, + {"B0", Const, 0, ""}, + {"B1000000", Const, 0, ""}, + {"B110", Const, 0, ""}, + {"B115200", Const, 0, ""}, + {"B1152000", Const, 0, ""}, + {"B1200", Const, 0, ""}, + {"B134", Const, 0, ""}, + {"B14400", Const, 1, ""}, + {"B150", Const, 0, ""}, + {"B1500000", Const, 0, ""}, + {"B1800", Const, 0, ""}, + {"B19200", Const, 0, ""}, + {"B200", Const, 0, ""}, + {"B2000000", Const, 0, ""}, + {"B230400", Const, 0, ""}, + {"B2400", Const, 0, ""}, + {"B2500000", Const, 0, ""}, + {"B28800", Const, 1, ""}, + {"B300", Const, 0, ""}, + {"B3000000", Const, 0, ""}, + {"B3500000", Const, 0, ""}, + {"B38400", Const, 0, ""}, + {"B4000000", Const, 0, ""}, + {"B460800", Const, 0, ""}, + {"B4800", Const, 0, ""}, + {"B50", Const, 0, ""}, + {"B500000", Const, 0, ""}, + {"B57600", Const, 0, ""}, + {"B576000", Const, 0, ""}, + {"B600", Const, 0, ""}, + {"B7200", Const, 1, ""}, + {"B75", Const, 0, ""}, + {"B76800", Const, 1, ""}, + {"B921600", Const, 0, ""}, + {"B9600", Const, 0, ""}, + {"BASE_PROTOCOL", Const, 2, ""}, + {"BIOCFEEDBACK", Const, 0, ""}, + {"BIOCFLUSH", Const, 0, ""}, + {"BIOCGBLEN", Const, 0, ""}, + {"BIOCGDIRECTION", Const, 0, ""}, + {"BIOCGDIRFILT", Const, 1, ""}, + {"BIOCGDLT", Const, 0, ""}, + {"BIOCGDLTLIST", Const, 0, ""}, + {"BIOCGETBUFMODE", Const, 0, ""}, + {"BIOCGETIF", Const, 0, ""}, + {"BIOCGETZMAX", Const, 0, ""}, + {"BIOCGFEEDBACK", Const, 1, ""}, + {"BIOCGFILDROP", Const, 1, ""}, + {"BIOCGHDRCMPLT", Const, 0, ""}, + {"BIOCGRSIG", Const, 0, ""}, + {"BIOCGRTIMEOUT", Const, 0, ""}, + {"BIOCGSEESENT", Const, 0, ""}, + {"BIOCGSTATS", Const, 0, ""}, + {"BIOCGSTATSOLD", Const, 1, ""}, + {"BIOCGTSTAMP", Const, 1, ""}, + {"BIOCIMMEDIATE", Const, 0, ""}, + {"BIOCLOCK", Const, 0, ""}, + {"BIOCPROMISC", Const, 0, ""}, + {"BIOCROTZBUF", Const, 0, ""}, + {"BIOCSBLEN", Const, 0, ""}, + {"BIOCSDIRECTION", Const, 0, ""}, + {"BIOCSDIRFILT", Const, 1, ""}, + {"BIOCSDLT", Const, 0, ""}, + {"BIOCSETBUFMODE", Const, 0, ""}, + {"BIOCSETF", Const, 0, ""}, + {"BIOCSETFNR", Const, 0, ""}, + {"BIOCSETIF", Const, 0, ""}, + {"BIOCSETWF", Const, 0, ""}, + {"BIOCSETZBUF", Const, 0, ""}, + {"BIOCSFEEDBACK", Const, 1, ""}, + {"BIOCSFILDROP", Const, 1, ""}, + {"BIOCSHDRCMPLT", Const, 0, ""}, + {"BIOCSRSIG", Const, 0, ""}, + {"BIOCSRTIMEOUT", Const, 0, ""}, + {"BIOCSSEESENT", Const, 0, ""}, + {"BIOCSTCPF", Const, 1, ""}, + {"BIOCSTSTAMP", Const, 1, ""}, + {"BIOCSUDPF", Const, 1, ""}, + {"BIOCVERSION", Const, 0, ""}, + {"BPF_A", Const, 0, ""}, + {"BPF_ABS", Const, 0, ""}, + {"BPF_ADD", Const, 0, ""}, + {"BPF_ALIGNMENT", Const, 0, ""}, + {"BPF_ALIGNMENT32", Const, 1, ""}, + {"BPF_ALU", Const, 0, ""}, + {"BPF_AND", Const, 0, ""}, + {"BPF_B", Const, 0, ""}, + {"BPF_BUFMODE_BUFFER", Const, 0, ""}, + {"BPF_BUFMODE_ZBUF", Const, 0, ""}, + {"BPF_DFLTBUFSIZE", Const, 1, ""}, + {"BPF_DIRECTION_IN", Const, 1, ""}, + {"BPF_DIRECTION_OUT", Const, 1, ""}, + {"BPF_DIV", Const, 0, ""}, + {"BPF_H", Const, 0, ""}, + {"BPF_IMM", Const, 0, ""}, + {"BPF_IND", Const, 0, ""}, + {"BPF_JA", Const, 0, ""}, + {"BPF_JEQ", Const, 0, ""}, + {"BPF_JGE", Const, 0, ""}, + {"BPF_JGT", Const, 0, ""}, + {"BPF_JMP", Const, 0, ""}, + {"BPF_JSET", Const, 0, ""}, + {"BPF_K", Const, 0, ""}, + {"BPF_LD", Const, 0, ""}, + {"BPF_LDX", Const, 0, ""}, + {"BPF_LEN", Const, 0, ""}, + {"BPF_LSH", Const, 0, ""}, + {"BPF_MAJOR_VERSION", Const, 0, ""}, + {"BPF_MAXBUFSIZE", Const, 0, ""}, + {"BPF_MAXINSNS", Const, 0, ""}, + {"BPF_MEM", Const, 0, ""}, + {"BPF_MEMWORDS", Const, 0, ""}, + {"BPF_MINBUFSIZE", Const, 0, ""}, + {"BPF_MINOR_VERSION", Const, 0, ""}, + {"BPF_MISC", Const, 0, ""}, + {"BPF_MSH", Const, 0, ""}, + {"BPF_MUL", Const, 0, ""}, + {"BPF_NEG", Const, 0, ""}, + {"BPF_OR", Const, 0, ""}, + {"BPF_RELEASE", Const, 0, ""}, + {"BPF_RET", Const, 0, ""}, + {"BPF_RSH", Const, 0, ""}, + {"BPF_ST", Const, 0, ""}, + {"BPF_STX", Const, 0, ""}, + {"BPF_SUB", Const, 0, ""}, + {"BPF_TAX", Const, 0, ""}, + {"BPF_TXA", Const, 0, ""}, + {"BPF_T_BINTIME", Const, 1, ""}, + {"BPF_T_BINTIME_FAST", Const, 1, ""}, + {"BPF_T_BINTIME_MONOTONIC", Const, 1, ""}, + {"BPF_T_BINTIME_MONOTONIC_FAST", Const, 1, ""}, + {"BPF_T_FAST", Const, 1, ""}, + {"BPF_T_FLAG_MASK", Const, 1, ""}, + {"BPF_T_FORMAT_MASK", Const, 1, ""}, + {"BPF_T_MICROTIME", Const, 1, ""}, + {"BPF_T_MICROTIME_FAST", Const, 1, ""}, + {"BPF_T_MICROTIME_MONOTONIC", Const, 1, ""}, + {"BPF_T_MICROTIME_MONOTONIC_FAST", Const, 1, ""}, + {"BPF_T_MONOTONIC", Const, 1, ""}, + {"BPF_T_MONOTONIC_FAST", Const, 1, ""}, + {"BPF_T_NANOTIME", Const, 1, ""}, + {"BPF_T_NANOTIME_FAST", Const, 1, ""}, + {"BPF_T_NANOTIME_MONOTONIC", Const, 1, ""}, + {"BPF_T_NANOTIME_MONOTONIC_FAST", Const, 1, ""}, + {"BPF_T_NONE", Const, 1, ""}, + {"BPF_T_NORMAL", Const, 1, ""}, + {"BPF_W", Const, 0, ""}, + {"BPF_X", Const, 0, ""}, + {"BRKINT", Const, 0, ""}, + {"Bind", Func, 0, "func(fd int, sa Sockaddr) (err error)"}, + {"BindToDevice", Func, 0, "func(fd int, device string) (err error)"}, + {"BpfBuflen", Func, 0, ""}, + {"BpfDatalink", Func, 0, ""}, + {"BpfHdr", Type, 0, ""}, + {"BpfHdr.Caplen", Field, 0, ""}, + {"BpfHdr.Datalen", Field, 0, ""}, + {"BpfHdr.Hdrlen", Field, 0, ""}, + {"BpfHdr.Pad_cgo_0", Field, 0, ""}, + {"BpfHdr.Tstamp", Field, 0, ""}, + {"BpfHeadercmpl", Func, 0, ""}, + {"BpfInsn", Type, 0, ""}, + {"BpfInsn.Code", Field, 0, ""}, + {"BpfInsn.Jf", Field, 0, ""}, + {"BpfInsn.Jt", Field, 0, ""}, + {"BpfInsn.K", Field, 0, ""}, + {"BpfInterface", Func, 0, ""}, + {"BpfJump", Func, 0, ""}, + {"BpfProgram", Type, 0, ""}, + {"BpfProgram.Insns", Field, 0, ""}, + {"BpfProgram.Len", Field, 0, ""}, + {"BpfProgram.Pad_cgo_0", Field, 0, ""}, + {"BpfStat", Type, 0, ""}, + {"BpfStat.Capt", Field, 2, ""}, + {"BpfStat.Drop", Field, 0, ""}, + {"BpfStat.Padding", Field, 2, ""}, + {"BpfStat.Recv", Field, 0, ""}, + {"BpfStats", Func, 0, ""}, + {"BpfStmt", Func, 0, ""}, + {"BpfTimeout", Func, 0, ""}, + {"BpfTimeval", Type, 2, ""}, + {"BpfTimeval.Sec", Field, 2, ""}, + {"BpfTimeval.Usec", Field, 2, ""}, + {"BpfVersion", Type, 0, ""}, + {"BpfVersion.Major", Field, 0, ""}, + {"BpfVersion.Minor", Field, 0, ""}, + {"BpfZbuf", Type, 0, ""}, + {"BpfZbuf.Bufa", Field, 0, ""}, + {"BpfZbuf.Bufb", Field, 0, ""}, + {"BpfZbuf.Buflen", Field, 0, ""}, + {"BpfZbufHeader", Type, 0, ""}, + {"BpfZbufHeader.Kernel_gen", Field, 0, ""}, + {"BpfZbufHeader.Kernel_len", Field, 0, ""}, + {"BpfZbufHeader.User_gen", Field, 0, ""}, + {"BpfZbufHeader.X_bzh_pad", Field, 0, ""}, + {"ByHandleFileInformation", Type, 0, ""}, + {"ByHandleFileInformation.CreationTime", Field, 0, ""}, + {"ByHandleFileInformation.FileAttributes", Field, 0, ""}, + {"ByHandleFileInformation.FileIndexHigh", Field, 0, ""}, + {"ByHandleFileInformation.FileIndexLow", Field, 0, ""}, + {"ByHandleFileInformation.FileSizeHigh", Field, 0, ""}, + {"ByHandleFileInformation.FileSizeLow", Field, 0, ""}, + {"ByHandleFileInformation.LastAccessTime", Field, 0, ""}, + {"ByHandleFileInformation.LastWriteTime", Field, 0, ""}, + {"ByHandleFileInformation.NumberOfLinks", Field, 0, ""}, + {"ByHandleFileInformation.VolumeSerialNumber", Field, 0, ""}, + {"BytePtrFromString", Func, 1, "func(s string) (*byte, error)"}, + {"ByteSliceFromString", Func, 1, "func(s string) ([]byte, error)"}, + {"CCR0_FLUSH", Const, 1, ""}, + {"CERT_CHAIN_POLICY_AUTHENTICODE", Const, 0, ""}, + {"CERT_CHAIN_POLICY_AUTHENTICODE_TS", Const, 0, ""}, + {"CERT_CHAIN_POLICY_BASE", Const, 0, ""}, + {"CERT_CHAIN_POLICY_BASIC_CONSTRAINTS", Const, 0, ""}, + {"CERT_CHAIN_POLICY_EV", Const, 0, ""}, + {"CERT_CHAIN_POLICY_MICROSOFT_ROOT", Const, 0, ""}, + {"CERT_CHAIN_POLICY_NT_AUTH", Const, 0, ""}, + {"CERT_CHAIN_POLICY_SSL", Const, 0, ""}, + {"CERT_E_CN_NO_MATCH", Const, 0, ""}, + {"CERT_E_EXPIRED", Const, 0, ""}, + {"CERT_E_PURPOSE", Const, 0, ""}, + {"CERT_E_ROLE", Const, 0, ""}, + {"CERT_E_UNTRUSTEDROOT", Const, 0, ""}, + {"CERT_STORE_ADD_ALWAYS", Const, 0, ""}, + {"CERT_STORE_DEFER_CLOSE_UNTIL_LAST_FREE_FLAG", Const, 0, ""}, + {"CERT_STORE_PROV_MEMORY", Const, 0, ""}, + {"CERT_TRUST_HAS_EXCLUDED_NAME_CONSTRAINT", Const, 0, ""}, + {"CERT_TRUST_HAS_NOT_DEFINED_NAME_CONSTRAINT", Const, 0, ""}, + {"CERT_TRUST_HAS_NOT_PERMITTED_NAME_CONSTRAINT", Const, 0, ""}, + {"CERT_TRUST_HAS_NOT_SUPPORTED_CRITICAL_EXT", Const, 0, ""}, + {"CERT_TRUST_HAS_NOT_SUPPORTED_NAME_CONSTRAINT", Const, 0, ""}, + {"CERT_TRUST_INVALID_BASIC_CONSTRAINTS", Const, 0, ""}, + {"CERT_TRUST_INVALID_EXTENSION", Const, 0, ""}, + {"CERT_TRUST_INVALID_NAME_CONSTRAINTS", Const, 0, ""}, + {"CERT_TRUST_INVALID_POLICY_CONSTRAINTS", Const, 0, ""}, + {"CERT_TRUST_IS_CYCLIC", Const, 0, ""}, + {"CERT_TRUST_IS_EXPLICIT_DISTRUST", Const, 0, ""}, + {"CERT_TRUST_IS_NOT_SIGNATURE_VALID", Const, 0, ""}, + {"CERT_TRUST_IS_NOT_TIME_VALID", Const, 0, ""}, + {"CERT_TRUST_IS_NOT_VALID_FOR_USAGE", Const, 0, ""}, + {"CERT_TRUST_IS_OFFLINE_REVOCATION", Const, 0, ""}, + {"CERT_TRUST_IS_REVOKED", Const, 0, ""}, + {"CERT_TRUST_IS_UNTRUSTED_ROOT", Const, 0, ""}, + {"CERT_TRUST_NO_ERROR", Const, 0, ""}, + {"CERT_TRUST_NO_ISSUANCE_CHAIN_POLICY", Const, 0, ""}, + {"CERT_TRUST_REVOCATION_STATUS_UNKNOWN", Const, 0, ""}, + {"CFLUSH", Const, 1, ""}, + {"CLOCAL", Const, 0, ""}, + {"CLONE_CHILD_CLEARTID", Const, 2, ""}, + {"CLONE_CHILD_SETTID", Const, 2, ""}, + {"CLONE_CLEAR_SIGHAND", Const, 20, ""}, + {"CLONE_CSIGNAL", Const, 3, ""}, + {"CLONE_DETACHED", Const, 2, ""}, + {"CLONE_FILES", Const, 2, ""}, + {"CLONE_FS", Const, 2, ""}, + {"CLONE_INTO_CGROUP", Const, 20, ""}, + {"CLONE_IO", Const, 2, ""}, + {"CLONE_NEWCGROUP", Const, 20, ""}, + {"CLONE_NEWIPC", Const, 2, ""}, + {"CLONE_NEWNET", Const, 2, ""}, + {"CLONE_NEWNS", Const, 2, ""}, + {"CLONE_NEWPID", Const, 2, ""}, + {"CLONE_NEWTIME", Const, 20, ""}, + {"CLONE_NEWUSER", Const, 2, ""}, + {"CLONE_NEWUTS", Const, 2, ""}, + {"CLONE_PARENT", Const, 2, ""}, + {"CLONE_PARENT_SETTID", Const, 2, ""}, + {"CLONE_PID", Const, 3, ""}, + {"CLONE_PIDFD", Const, 20, ""}, + {"CLONE_PTRACE", Const, 2, ""}, + {"CLONE_SETTLS", Const, 2, ""}, + {"CLONE_SIGHAND", Const, 2, ""}, + {"CLONE_SYSVSEM", Const, 2, ""}, + {"CLONE_THREAD", Const, 2, ""}, + {"CLONE_UNTRACED", Const, 2, ""}, + {"CLONE_VFORK", Const, 2, ""}, + {"CLONE_VM", Const, 2, ""}, + {"CPUID_CFLUSH", Const, 1, ""}, + {"CREAD", Const, 0, ""}, + {"CREATE_ALWAYS", Const, 0, ""}, + {"CREATE_NEW", Const, 0, ""}, + {"CREATE_NEW_PROCESS_GROUP", Const, 1, ""}, + {"CREATE_UNICODE_ENVIRONMENT", Const, 0, ""}, + {"CRYPT_DEFAULT_CONTAINER_OPTIONAL", Const, 0, ""}, + {"CRYPT_DELETEKEYSET", Const, 0, ""}, + {"CRYPT_MACHINE_KEYSET", Const, 0, ""}, + {"CRYPT_NEWKEYSET", Const, 0, ""}, + {"CRYPT_SILENT", Const, 0, ""}, + {"CRYPT_VERIFYCONTEXT", Const, 0, ""}, + {"CS5", Const, 0, ""}, + {"CS6", Const, 0, ""}, + {"CS7", Const, 0, ""}, + {"CS8", Const, 0, ""}, + {"CSIZE", Const, 0, ""}, + {"CSTART", Const, 1, ""}, + {"CSTATUS", Const, 1, ""}, + {"CSTOP", Const, 1, ""}, + {"CSTOPB", Const, 0, ""}, + {"CSUSP", Const, 1, ""}, + {"CTL_MAXNAME", Const, 0, ""}, + {"CTL_NET", Const, 0, ""}, + {"CTL_QUERY", Const, 1, ""}, + {"CTRL_BREAK_EVENT", Const, 1, ""}, + {"CTRL_CLOSE_EVENT", Const, 14, ""}, + {"CTRL_C_EVENT", Const, 1, ""}, + {"CTRL_LOGOFF_EVENT", Const, 14, ""}, + {"CTRL_SHUTDOWN_EVENT", Const, 14, ""}, + {"CancelIo", Func, 0, ""}, + {"CancelIoEx", Func, 1, ""}, + {"CertAddCertificateContextToStore", Func, 0, ""}, + {"CertChainContext", Type, 0, ""}, + {"CertChainContext.ChainCount", Field, 0, ""}, + {"CertChainContext.Chains", Field, 0, ""}, + {"CertChainContext.HasRevocationFreshnessTime", Field, 0, ""}, + {"CertChainContext.LowerQualityChainCount", Field, 0, ""}, + {"CertChainContext.LowerQualityChains", Field, 0, ""}, + {"CertChainContext.RevocationFreshnessTime", Field, 0, ""}, + {"CertChainContext.Size", Field, 0, ""}, + {"CertChainContext.TrustStatus", Field, 0, ""}, + {"CertChainElement", Type, 0, ""}, + {"CertChainElement.ApplicationUsage", Field, 0, ""}, + {"CertChainElement.CertContext", Field, 0, ""}, + {"CertChainElement.ExtendedErrorInfo", Field, 0, ""}, + {"CertChainElement.IssuanceUsage", Field, 0, ""}, + {"CertChainElement.RevocationInfo", Field, 0, ""}, + {"CertChainElement.Size", Field, 0, ""}, + {"CertChainElement.TrustStatus", Field, 0, ""}, + {"CertChainPara", Type, 0, ""}, + {"CertChainPara.CacheResync", Field, 0, ""}, + {"CertChainPara.CheckRevocationFreshnessTime", Field, 0, ""}, + {"CertChainPara.RequestedUsage", Field, 0, ""}, + {"CertChainPara.RequstedIssuancePolicy", Field, 0, ""}, + {"CertChainPara.RevocationFreshnessTime", Field, 0, ""}, + {"CertChainPara.Size", Field, 0, ""}, + {"CertChainPara.URLRetrievalTimeout", Field, 0, ""}, + {"CertChainPolicyPara", Type, 0, ""}, + {"CertChainPolicyPara.ExtraPolicyPara", Field, 0, ""}, + {"CertChainPolicyPara.Flags", Field, 0, ""}, + {"CertChainPolicyPara.Size", Field, 0, ""}, + {"CertChainPolicyStatus", Type, 0, ""}, + {"CertChainPolicyStatus.ChainIndex", Field, 0, ""}, + {"CertChainPolicyStatus.ElementIndex", Field, 0, ""}, + {"CertChainPolicyStatus.Error", Field, 0, ""}, + {"CertChainPolicyStatus.ExtraPolicyStatus", Field, 0, ""}, + {"CertChainPolicyStatus.Size", Field, 0, ""}, + {"CertCloseStore", Func, 0, ""}, + {"CertContext", Type, 0, ""}, + {"CertContext.CertInfo", Field, 0, ""}, + {"CertContext.EncodedCert", Field, 0, ""}, + {"CertContext.EncodingType", Field, 0, ""}, + {"CertContext.Length", Field, 0, ""}, + {"CertContext.Store", Field, 0, ""}, + {"CertCreateCertificateContext", Func, 0, ""}, + {"CertEnhKeyUsage", Type, 0, ""}, + {"CertEnhKeyUsage.Length", Field, 0, ""}, + {"CertEnhKeyUsage.UsageIdentifiers", Field, 0, ""}, + {"CertEnumCertificatesInStore", Func, 0, ""}, + {"CertFreeCertificateChain", Func, 0, ""}, + {"CertFreeCertificateContext", Func, 0, ""}, + {"CertGetCertificateChain", Func, 0, ""}, + {"CertInfo", Type, 11, ""}, + {"CertOpenStore", Func, 0, ""}, + {"CertOpenSystemStore", Func, 0, ""}, + {"CertRevocationCrlInfo", Type, 11, ""}, + {"CertRevocationInfo", Type, 0, ""}, + {"CertRevocationInfo.CrlInfo", Field, 0, ""}, + {"CertRevocationInfo.FreshnessTime", Field, 0, ""}, + {"CertRevocationInfo.HasFreshnessTime", Field, 0, ""}, + {"CertRevocationInfo.OidSpecificInfo", Field, 0, ""}, + {"CertRevocationInfo.RevocationOid", Field, 0, ""}, + {"CertRevocationInfo.RevocationResult", Field, 0, ""}, + {"CertRevocationInfo.Size", Field, 0, ""}, + {"CertSimpleChain", Type, 0, ""}, + {"CertSimpleChain.Elements", Field, 0, ""}, + {"CertSimpleChain.HasRevocationFreshnessTime", Field, 0, ""}, + {"CertSimpleChain.NumElements", Field, 0, ""}, + {"CertSimpleChain.RevocationFreshnessTime", Field, 0, ""}, + {"CertSimpleChain.Size", Field, 0, ""}, + {"CertSimpleChain.TrustListInfo", Field, 0, ""}, + {"CertSimpleChain.TrustStatus", Field, 0, ""}, + {"CertTrustListInfo", Type, 11, ""}, + {"CertTrustStatus", Type, 0, ""}, + {"CertTrustStatus.ErrorStatus", Field, 0, ""}, + {"CertTrustStatus.InfoStatus", Field, 0, ""}, + {"CertUsageMatch", Type, 0, ""}, + {"CertUsageMatch.Type", Field, 0, ""}, + {"CertUsageMatch.Usage", Field, 0, ""}, + {"CertVerifyCertificateChainPolicy", Func, 0, ""}, + {"Chdir", Func, 0, "func(path string) (err error)"}, + {"CheckBpfVersion", Func, 0, ""}, + {"Chflags", Func, 0, ""}, + {"Chmod", Func, 0, "func(path string, mode uint32) (err error)"}, + {"Chown", Func, 0, "func(path string, uid int, gid int) (err error)"}, + {"Chroot", Func, 0, "func(path string) (err error)"}, + {"Clearenv", Func, 0, "func()"}, + {"Close", Func, 0, "func(fd int) (err error)"}, + {"CloseHandle", Func, 0, ""}, + {"CloseOnExec", Func, 0, "func(fd int)"}, + {"Closesocket", Func, 0, ""}, + {"CmsgLen", Func, 0, "func(datalen int) int"}, + {"CmsgSpace", Func, 0, "func(datalen int) int"}, + {"Cmsghdr", Type, 0, ""}, + {"Cmsghdr.Len", Field, 0, ""}, + {"Cmsghdr.Level", Field, 0, ""}, + {"Cmsghdr.Type", Field, 0, ""}, + {"Cmsghdr.X__cmsg_data", Field, 0, ""}, + {"CommandLineToArgv", Func, 0, ""}, + {"ComputerName", Func, 0, ""}, + {"Conn", Type, 9, ""}, + {"Connect", Func, 0, "func(fd int, sa Sockaddr) (err error)"}, + {"ConnectEx", Func, 1, ""}, + {"ConvertSidToStringSid", Func, 0, ""}, + {"ConvertStringSidToSid", Func, 0, ""}, + {"CopySid", Func, 0, ""}, + {"Creat", Func, 0, "func(path string, mode uint32) (fd int, err error)"}, + {"CreateDirectory", Func, 0, ""}, + {"CreateFile", Func, 0, ""}, + {"CreateFileMapping", Func, 0, ""}, + {"CreateHardLink", Func, 4, ""}, + {"CreateIoCompletionPort", Func, 0, ""}, + {"CreatePipe", Func, 0, ""}, + {"CreateProcess", Func, 0, ""}, + {"CreateProcessAsUser", Func, 10, ""}, + {"CreateSymbolicLink", Func, 4, ""}, + {"CreateToolhelp32Snapshot", Func, 4, ""}, + {"Credential", Type, 0, ""}, + {"Credential.Gid", Field, 0, ""}, + {"Credential.Groups", Field, 0, ""}, + {"Credential.NoSetGroups", Field, 9, ""}, + {"Credential.Uid", Field, 0, ""}, + {"CryptAcquireContext", Func, 0, ""}, + {"CryptGenRandom", Func, 0, ""}, + {"CryptReleaseContext", Func, 0, ""}, + {"DIOCBSFLUSH", Const, 1, ""}, + {"DIOCOSFPFLUSH", Const, 1, ""}, + {"DLL", Type, 0, ""}, + {"DLL.Handle", Field, 0, ""}, + {"DLL.Name", Field, 0, ""}, + {"DLLError", Type, 0, ""}, + {"DLLError.Err", Field, 0, ""}, + {"DLLError.Msg", Field, 0, ""}, + {"DLLError.ObjName", Field, 0, ""}, + {"DLT_A429", Const, 0, ""}, + {"DLT_A653_ICM", Const, 0, ""}, + {"DLT_AIRONET_HEADER", Const, 0, ""}, + {"DLT_AOS", Const, 1, ""}, + {"DLT_APPLE_IP_OVER_IEEE1394", Const, 0, ""}, + {"DLT_ARCNET", Const, 0, ""}, + {"DLT_ARCNET_LINUX", Const, 0, ""}, + {"DLT_ATM_CLIP", Const, 0, ""}, + {"DLT_ATM_RFC1483", Const, 0, ""}, + {"DLT_AURORA", Const, 0, ""}, + {"DLT_AX25", Const, 0, ""}, + {"DLT_AX25_KISS", Const, 0, ""}, + {"DLT_BACNET_MS_TP", Const, 0, ""}, + {"DLT_BLUETOOTH_HCI_H4", Const, 0, ""}, + {"DLT_BLUETOOTH_HCI_H4_WITH_PHDR", Const, 0, ""}, + {"DLT_CAN20B", Const, 0, ""}, + {"DLT_CAN_SOCKETCAN", Const, 1, ""}, + {"DLT_CHAOS", Const, 0, ""}, + {"DLT_CHDLC", Const, 0, ""}, + {"DLT_CISCO_IOS", Const, 0, ""}, + {"DLT_C_HDLC", Const, 0, ""}, + {"DLT_C_HDLC_WITH_DIR", Const, 0, ""}, + {"DLT_DBUS", Const, 1, ""}, + {"DLT_DECT", Const, 1, ""}, + {"DLT_DOCSIS", Const, 0, ""}, + {"DLT_DVB_CI", Const, 1, ""}, + {"DLT_ECONET", Const, 0, ""}, + {"DLT_EN10MB", Const, 0, ""}, + {"DLT_EN3MB", Const, 0, ""}, + {"DLT_ENC", Const, 0, ""}, + {"DLT_ERF", Const, 0, ""}, + {"DLT_ERF_ETH", Const, 0, ""}, + {"DLT_ERF_POS", Const, 0, ""}, + {"DLT_FC_2", Const, 1, ""}, + {"DLT_FC_2_WITH_FRAME_DELIMS", Const, 1, ""}, + {"DLT_FDDI", Const, 0, ""}, + {"DLT_FLEXRAY", Const, 0, ""}, + {"DLT_FRELAY", Const, 0, ""}, + {"DLT_FRELAY_WITH_DIR", Const, 0, ""}, + {"DLT_GCOM_SERIAL", Const, 0, ""}, + {"DLT_GCOM_T1E1", Const, 0, ""}, + {"DLT_GPF_F", Const, 0, ""}, + {"DLT_GPF_T", Const, 0, ""}, + {"DLT_GPRS_LLC", Const, 0, ""}, + {"DLT_GSMTAP_ABIS", Const, 1, ""}, + {"DLT_GSMTAP_UM", Const, 1, ""}, + {"DLT_HDLC", Const, 1, ""}, + {"DLT_HHDLC", Const, 0, ""}, + {"DLT_HIPPI", Const, 1, ""}, + {"DLT_IBM_SN", Const, 0, ""}, + {"DLT_IBM_SP", Const, 0, ""}, + {"DLT_IEEE802", Const, 0, ""}, + {"DLT_IEEE802_11", Const, 0, ""}, + {"DLT_IEEE802_11_RADIO", Const, 0, ""}, + {"DLT_IEEE802_11_RADIO_AVS", Const, 0, ""}, + {"DLT_IEEE802_15_4", Const, 0, ""}, + {"DLT_IEEE802_15_4_LINUX", Const, 0, ""}, + {"DLT_IEEE802_15_4_NOFCS", Const, 1, ""}, + {"DLT_IEEE802_15_4_NONASK_PHY", Const, 0, ""}, + {"DLT_IEEE802_16_MAC_CPS", Const, 0, ""}, + {"DLT_IEEE802_16_MAC_CPS_RADIO", Const, 0, ""}, + {"DLT_IPFILTER", Const, 0, ""}, + {"DLT_IPMB", Const, 0, ""}, + {"DLT_IPMB_LINUX", Const, 0, ""}, + {"DLT_IPNET", Const, 1, ""}, + {"DLT_IPOIB", Const, 1, ""}, + {"DLT_IPV4", Const, 1, ""}, + {"DLT_IPV6", Const, 1, ""}, + {"DLT_IP_OVER_FC", Const, 0, ""}, + {"DLT_JUNIPER_ATM1", Const, 0, ""}, + {"DLT_JUNIPER_ATM2", Const, 0, ""}, + {"DLT_JUNIPER_ATM_CEMIC", Const, 1, ""}, + {"DLT_JUNIPER_CHDLC", Const, 0, ""}, + {"DLT_JUNIPER_ES", Const, 0, ""}, + {"DLT_JUNIPER_ETHER", Const, 0, ""}, + {"DLT_JUNIPER_FIBRECHANNEL", Const, 1, ""}, + {"DLT_JUNIPER_FRELAY", Const, 0, ""}, + {"DLT_JUNIPER_GGSN", Const, 0, ""}, + {"DLT_JUNIPER_ISM", Const, 0, ""}, + {"DLT_JUNIPER_MFR", Const, 0, ""}, + {"DLT_JUNIPER_MLFR", Const, 0, ""}, + {"DLT_JUNIPER_MLPPP", Const, 0, ""}, + {"DLT_JUNIPER_MONITOR", Const, 0, ""}, + {"DLT_JUNIPER_PIC_PEER", Const, 0, ""}, + {"DLT_JUNIPER_PPP", Const, 0, ""}, + {"DLT_JUNIPER_PPPOE", Const, 0, ""}, + {"DLT_JUNIPER_PPPOE_ATM", Const, 0, ""}, + {"DLT_JUNIPER_SERVICES", Const, 0, ""}, + {"DLT_JUNIPER_SRX_E2E", Const, 1, ""}, + {"DLT_JUNIPER_ST", Const, 0, ""}, + {"DLT_JUNIPER_VP", Const, 0, ""}, + {"DLT_JUNIPER_VS", Const, 1, ""}, + {"DLT_LAPB_WITH_DIR", Const, 0, ""}, + {"DLT_LAPD", Const, 0, ""}, + {"DLT_LIN", Const, 0, ""}, + {"DLT_LINUX_EVDEV", Const, 1, ""}, + {"DLT_LINUX_IRDA", Const, 0, ""}, + {"DLT_LINUX_LAPD", Const, 0, ""}, + {"DLT_LINUX_PPP_WITHDIRECTION", Const, 0, ""}, + {"DLT_LINUX_SLL", Const, 0, ""}, + {"DLT_LOOP", Const, 0, ""}, + {"DLT_LTALK", Const, 0, ""}, + {"DLT_MATCHING_MAX", Const, 1, ""}, + {"DLT_MATCHING_MIN", Const, 1, ""}, + {"DLT_MFR", Const, 0, ""}, + {"DLT_MOST", Const, 0, ""}, + {"DLT_MPEG_2_TS", Const, 1, ""}, + {"DLT_MPLS", Const, 1, ""}, + {"DLT_MTP2", Const, 0, ""}, + {"DLT_MTP2_WITH_PHDR", Const, 0, ""}, + {"DLT_MTP3", Const, 0, ""}, + {"DLT_MUX27010", Const, 1, ""}, + {"DLT_NETANALYZER", Const, 1, ""}, + {"DLT_NETANALYZER_TRANSPARENT", Const, 1, ""}, + {"DLT_NFC_LLCP", Const, 1, ""}, + {"DLT_NFLOG", Const, 1, ""}, + {"DLT_NG40", Const, 1, ""}, + {"DLT_NULL", Const, 0, ""}, + {"DLT_PCI_EXP", Const, 0, ""}, + {"DLT_PFLOG", Const, 0, ""}, + {"DLT_PFSYNC", Const, 0, ""}, + {"DLT_PPI", Const, 0, ""}, + {"DLT_PPP", Const, 0, ""}, + {"DLT_PPP_BSDOS", Const, 0, ""}, + {"DLT_PPP_ETHER", Const, 0, ""}, + {"DLT_PPP_PPPD", Const, 0, ""}, + {"DLT_PPP_SERIAL", Const, 0, ""}, + {"DLT_PPP_WITH_DIR", Const, 0, ""}, + {"DLT_PPP_WITH_DIRECTION", Const, 0, ""}, + {"DLT_PRISM_HEADER", Const, 0, ""}, + {"DLT_PRONET", Const, 0, ""}, + {"DLT_RAIF1", Const, 0, ""}, + {"DLT_RAW", Const, 0, ""}, + {"DLT_RAWAF_MASK", Const, 1, ""}, + {"DLT_RIO", Const, 0, ""}, + {"DLT_SCCP", Const, 0, ""}, + {"DLT_SITA", Const, 0, ""}, + {"DLT_SLIP", Const, 0, ""}, + {"DLT_SLIP_BSDOS", Const, 0, ""}, + {"DLT_STANAG_5066_D_PDU", Const, 1, ""}, + {"DLT_SUNATM", Const, 0, ""}, + {"DLT_SYMANTEC_FIREWALL", Const, 0, ""}, + {"DLT_TZSP", Const, 0, ""}, + {"DLT_USB", Const, 0, ""}, + {"DLT_USB_LINUX", Const, 0, ""}, + {"DLT_USB_LINUX_MMAPPED", Const, 1, ""}, + {"DLT_USER0", Const, 0, ""}, + {"DLT_USER1", Const, 0, ""}, + {"DLT_USER10", Const, 0, ""}, + {"DLT_USER11", Const, 0, ""}, + {"DLT_USER12", Const, 0, ""}, + {"DLT_USER13", Const, 0, ""}, + {"DLT_USER14", Const, 0, ""}, + {"DLT_USER15", Const, 0, ""}, + {"DLT_USER2", Const, 0, ""}, + {"DLT_USER3", Const, 0, ""}, + {"DLT_USER4", Const, 0, ""}, + {"DLT_USER5", Const, 0, ""}, + {"DLT_USER6", Const, 0, ""}, + {"DLT_USER7", Const, 0, ""}, + {"DLT_USER8", Const, 0, ""}, + {"DLT_USER9", Const, 0, ""}, + {"DLT_WIHART", Const, 1, ""}, + {"DLT_X2E_SERIAL", Const, 0, ""}, + {"DLT_X2E_XORAYA", Const, 0, ""}, + {"DNSMXData", Type, 0, ""}, + {"DNSMXData.NameExchange", Field, 0, ""}, + {"DNSMXData.Pad", Field, 0, ""}, + {"DNSMXData.Preference", Field, 0, ""}, + {"DNSPTRData", Type, 0, ""}, + {"DNSPTRData.Host", Field, 0, ""}, + {"DNSRecord", Type, 0, ""}, + {"DNSRecord.Data", Field, 0, ""}, + {"DNSRecord.Dw", Field, 0, ""}, + {"DNSRecord.Length", Field, 0, ""}, + {"DNSRecord.Name", Field, 0, ""}, + {"DNSRecord.Next", Field, 0, ""}, + {"DNSRecord.Reserved", Field, 0, ""}, + {"DNSRecord.Ttl", Field, 0, ""}, + {"DNSRecord.Type", Field, 0, ""}, + {"DNSSRVData", Type, 0, ""}, + {"DNSSRVData.Pad", Field, 0, ""}, + {"DNSSRVData.Port", Field, 0, ""}, + {"DNSSRVData.Priority", Field, 0, ""}, + {"DNSSRVData.Target", Field, 0, ""}, + {"DNSSRVData.Weight", Field, 0, ""}, + {"DNSTXTData", Type, 0, ""}, + {"DNSTXTData.StringArray", Field, 0, ""}, + {"DNSTXTData.StringCount", Field, 0, ""}, + {"DNS_INFO_NO_RECORDS", Const, 4, ""}, + {"DNS_TYPE_A", Const, 0, ""}, + {"DNS_TYPE_A6", Const, 0, ""}, + {"DNS_TYPE_AAAA", Const, 0, ""}, + {"DNS_TYPE_ADDRS", Const, 0, ""}, + {"DNS_TYPE_AFSDB", Const, 0, ""}, + {"DNS_TYPE_ALL", Const, 0, ""}, + {"DNS_TYPE_ANY", Const, 0, ""}, + {"DNS_TYPE_ATMA", Const, 0, ""}, + {"DNS_TYPE_AXFR", Const, 0, ""}, + {"DNS_TYPE_CERT", Const, 0, ""}, + {"DNS_TYPE_CNAME", Const, 0, ""}, + {"DNS_TYPE_DHCID", Const, 0, ""}, + {"DNS_TYPE_DNAME", Const, 0, ""}, + {"DNS_TYPE_DNSKEY", Const, 0, ""}, + {"DNS_TYPE_DS", Const, 0, ""}, + {"DNS_TYPE_EID", Const, 0, ""}, + {"DNS_TYPE_GID", Const, 0, ""}, + {"DNS_TYPE_GPOS", Const, 0, ""}, + {"DNS_TYPE_HINFO", Const, 0, ""}, + {"DNS_TYPE_ISDN", Const, 0, ""}, + {"DNS_TYPE_IXFR", Const, 0, ""}, + {"DNS_TYPE_KEY", Const, 0, ""}, + {"DNS_TYPE_KX", Const, 0, ""}, + {"DNS_TYPE_LOC", Const, 0, ""}, + {"DNS_TYPE_MAILA", Const, 0, ""}, + {"DNS_TYPE_MAILB", Const, 0, ""}, + {"DNS_TYPE_MB", Const, 0, ""}, + {"DNS_TYPE_MD", Const, 0, ""}, + {"DNS_TYPE_MF", Const, 0, ""}, + {"DNS_TYPE_MG", Const, 0, ""}, + {"DNS_TYPE_MINFO", Const, 0, ""}, + {"DNS_TYPE_MR", Const, 0, ""}, + {"DNS_TYPE_MX", Const, 0, ""}, + {"DNS_TYPE_NAPTR", Const, 0, ""}, + {"DNS_TYPE_NBSTAT", Const, 0, ""}, + {"DNS_TYPE_NIMLOC", Const, 0, ""}, + {"DNS_TYPE_NS", Const, 0, ""}, + {"DNS_TYPE_NSAP", Const, 0, ""}, + {"DNS_TYPE_NSAPPTR", Const, 0, ""}, + {"DNS_TYPE_NSEC", Const, 0, ""}, + {"DNS_TYPE_NULL", Const, 0, ""}, + {"DNS_TYPE_NXT", Const, 0, ""}, + {"DNS_TYPE_OPT", Const, 0, ""}, + {"DNS_TYPE_PTR", Const, 0, ""}, + {"DNS_TYPE_PX", Const, 0, ""}, + {"DNS_TYPE_RP", Const, 0, ""}, + {"DNS_TYPE_RRSIG", Const, 0, ""}, + {"DNS_TYPE_RT", Const, 0, ""}, + {"DNS_TYPE_SIG", Const, 0, ""}, + {"DNS_TYPE_SINK", Const, 0, ""}, + {"DNS_TYPE_SOA", Const, 0, ""}, + {"DNS_TYPE_SRV", Const, 0, ""}, + {"DNS_TYPE_TEXT", Const, 0, ""}, + {"DNS_TYPE_TKEY", Const, 0, ""}, + {"DNS_TYPE_TSIG", Const, 0, ""}, + {"DNS_TYPE_UID", Const, 0, ""}, + {"DNS_TYPE_UINFO", Const, 0, ""}, + {"DNS_TYPE_UNSPEC", Const, 0, ""}, + {"DNS_TYPE_WINS", Const, 0, ""}, + {"DNS_TYPE_WINSR", Const, 0, ""}, + {"DNS_TYPE_WKS", Const, 0, ""}, + {"DNS_TYPE_X25", Const, 0, ""}, + {"DT_BLK", Const, 0, ""}, + {"DT_CHR", Const, 0, ""}, + {"DT_DIR", Const, 0, ""}, + {"DT_FIFO", Const, 0, ""}, + {"DT_LNK", Const, 0, ""}, + {"DT_REG", Const, 0, ""}, + {"DT_SOCK", Const, 0, ""}, + {"DT_UNKNOWN", Const, 0, ""}, + {"DT_WHT", Const, 0, ""}, + {"DUPLICATE_CLOSE_SOURCE", Const, 0, ""}, + {"DUPLICATE_SAME_ACCESS", Const, 0, ""}, + {"DeleteFile", Func, 0, ""}, + {"DetachLsf", Func, 0, "func(fd int) error"}, + {"DeviceIoControl", Func, 4, ""}, + {"Dirent", Type, 0, ""}, + {"Dirent.Fileno", Field, 0, ""}, + {"Dirent.Ino", Field, 0, ""}, + {"Dirent.Name", Field, 0, ""}, + {"Dirent.Namlen", Field, 0, ""}, + {"Dirent.Off", Field, 0, ""}, + {"Dirent.Pad0", Field, 12, ""}, + {"Dirent.Pad1", Field, 12, ""}, + {"Dirent.Pad_cgo_0", Field, 0, ""}, + {"Dirent.Reclen", Field, 0, ""}, + {"Dirent.Seekoff", Field, 0, ""}, + {"Dirent.Type", Field, 0, ""}, + {"Dirent.X__d_padding", Field, 3, ""}, + {"DnsNameCompare", Func, 4, ""}, + {"DnsQuery", Func, 0, ""}, + {"DnsRecordListFree", Func, 0, ""}, + {"DnsSectionAdditional", Const, 4, ""}, + {"DnsSectionAnswer", Const, 4, ""}, + {"DnsSectionAuthority", Const, 4, ""}, + {"DnsSectionQuestion", Const, 4, ""}, + {"Dup", Func, 0, "func(oldfd int) (fd int, err error)"}, + {"Dup2", Func, 0, "func(oldfd int, newfd int) (err error)"}, + {"Dup3", Func, 2, "func(oldfd int, newfd int, flags int) (err error)"}, + {"DuplicateHandle", Func, 0, ""}, + {"E2BIG", Const, 0, ""}, + {"EACCES", Const, 0, ""}, + {"EADDRINUSE", Const, 0, ""}, + {"EADDRNOTAVAIL", Const, 0, ""}, + {"EADV", Const, 0, ""}, + {"EAFNOSUPPORT", Const, 0, ""}, + {"EAGAIN", Const, 0, ""}, + {"EALREADY", Const, 0, ""}, + {"EAUTH", Const, 0, ""}, + {"EBADARCH", Const, 0, ""}, + {"EBADE", Const, 0, ""}, + {"EBADEXEC", Const, 0, ""}, + {"EBADF", Const, 0, ""}, + {"EBADFD", Const, 0, ""}, + {"EBADMACHO", Const, 0, ""}, + {"EBADMSG", Const, 0, ""}, + {"EBADR", Const, 0, ""}, + {"EBADRPC", Const, 0, ""}, + {"EBADRQC", Const, 0, ""}, + {"EBADSLT", Const, 0, ""}, + {"EBFONT", Const, 0, ""}, + {"EBUSY", Const, 0, ""}, + {"ECANCELED", Const, 0, ""}, + {"ECAPMODE", Const, 1, ""}, + {"ECHILD", Const, 0, ""}, + {"ECHO", Const, 0, ""}, + {"ECHOCTL", Const, 0, ""}, + {"ECHOE", Const, 0, ""}, + {"ECHOK", Const, 0, ""}, + {"ECHOKE", Const, 0, ""}, + {"ECHONL", Const, 0, ""}, + {"ECHOPRT", Const, 0, ""}, + {"ECHRNG", Const, 0, ""}, + {"ECOMM", Const, 0, ""}, + {"ECONNABORTED", Const, 0, ""}, + {"ECONNREFUSED", Const, 0, ""}, + {"ECONNRESET", Const, 0, ""}, + {"EDEADLK", Const, 0, ""}, + {"EDEADLOCK", Const, 0, ""}, + {"EDESTADDRREQ", Const, 0, ""}, + {"EDEVERR", Const, 0, ""}, + {"EDOM", Const, 0, ""}, + {"EDOOFUS", Const, 0, ""}, + {"EDOTDOT", Const, 0, ""}, + {"EDQUOT", Const, 0, ""}, + {"EEXIST", Const, 0, ""}, + {"EFAULT", Const, 0, ""}, + {"EFBIG", Const, 0, ""}, + {"EFER_LMA", Const, 1, ""}, + {"EFER_LME", Const, 1, ""}, + {"EFER_NXE", Const, 1, ""}, + {"EFER_SCE", Const, 1, ""}, + {"EFTYPE", Const, 0, ""}, + {"EHOSTDOWN", Const, 0, ""}, + {"EHOSTUNREACH", Const, 0, ""}, + {"EHWPOISON", Const, 0, ""}, + {"EIDRM", Const, 0, ""}, + {"EILSEQ", Const, 0, ""}, + {"EINPROGRESS", Const, 0, ""}, + {"EINTR", Const, 0, ""}, + {"EINVAL", Const, 0, ""}, + {"EIO", Const, 0, ""}, + {"EIPSEC", Const, 1, ""}, + {"EISCONN", Const, 0, ""}, + {"EISDIR", Const, 0, ""}, + {"EISNAM", Const, 0, ""}, + {"EKEYEXPIRED", Const, 0, ""}, + {"EKEYREJECTED", Const, 0, ""}, + {"EKEYREVOKED", Const, 0, ""}, + {"EL2HLT", Const, 0, ""}, + {"EL2NSYNC", Const, 0, ""}, + {"EL3HLT", Const, 0, ""}, + {"EL3RST", Const, 0, ""}, + {"ELAST", Const, 0, ""}, + {"ELF_NGREG", Const, 0, ""}, + {"ELF_PRARGSZ", Const, 0, ""}, + {"ELIBACC", Const, 0, ""}, + {"ELIBBAD", Const, 0, ""}, + {"ELIBEXEC", Const, 0, ""}, + {"ELIBMAX", Const, 0, ""}, + {"ELIBSCN", Const, 0, ""}, + {"ELNRNG", Const, 0, ""}, + {"ELOOP", Const, 0, ""}, + {"EMEDIUMTYPE", Const, 0, ""}, + {"EMFILE", Const, 0, ""}, + {"EMLINK", Const, 0, ""}, + {"EMSGSIZE", Const, 0, ""}, + {"EMT_TAGOVF", Const, 1, ""}, + {"EMULTIHOP", Const, 0, ""}, + {"EMUL_ENABLED", Const, 1, ""}, + {"EMUL_LINUX", Const, 1, ""}, + {"EMUL_LINUX32", Const, 1, ""}, + {"EMUL_MAXID", Const, 1, ""}, + {"EMUL_NATIVE", Const, 1, ""}, + {"ENAMETOOLONG", Const, 0, ""}, + {"ENAVAIL", Const, 0, ""}, + {"ENDRUNDISC", Const, 1, ""}, + {"ENEEDAUTH", Const, 0, ""}, + {"ENETDOWN", Const, 0, ""}, + {"ENETRESET", Const, 0, ""}, + {"ENETUNREACH", Const, 0, ""}, + {"ENFILE", Const, 0, ""}, + {"ENOANO", Const, 0, ""}, + {"ENOATTR", Const, 0, ""}, + {"ENOBUFS", Const, 0, ""}, + {"ENOCSI", Const, 0, ""}, + {"ENODATA", Const, 0, ""}, + {"ENODEV", Const, 0, ""}, + {"ENOENT", Const, 0, ""}, + {"ENOEXEC", Const, 0, ""}, + {"ENOKEY", Const, 0, ""}, + {"ENOLCK", Const, 0, ""}, + {"ENOLINK", Const, 0, ""}, + {"ENOMEDIUM", Const, 0, ""}, + {"ENOMEM", Const, 0, ""}, + {"ENOMSG", Const, 0, ""}, + {"ENONET", Const, 0, ""}, + {"ENOPKG", Const, 0, ""}, + {"ENOPOLICY", Const, 0, ""}, + {"ENOPROTOOPT", Const, 0, ""}, + {"ENOSPC", Const, 0, ""}, + {"ENOSR", Const, 0, ""}, + {"ENOSTR", Const, 0, ""}, + {"ENOSYS", Const, 0, ""}, + {"ENOTBLK", Const, 0, ""}, + {"ENOTCAPABLE", Const, 0, ""}, + {"ENOTCONN", Const, 0, ""}, + {"ENOTDIR", Const, 0, ""}, + {"ENOTEMPTY", Const, 0, ""}, + {"ENOTNAM", Const, 0, ""}, + {"ENOTRECOVERABLE", Const, 0, ""}, + {"ENOTSOCK", Const, 0, ""}, + {"ENOTSUP", Const, 0, ""}, + {"ENOTTY", Const, 0, ""}, + {"ENOTUNIQ", Const, 0, ""}, + {"ENXIO", Const, 0, ""}, + {"EN_SW_CTL_INF", Const, 1, ""}, + {"EN_SW_CTL_PREC", Const, 1, ""}, + {"EN_SW_CTL_ROUND", Const, 1, ""}, + {"EN_SW_DATACHAIN", Const, 1, ""}, + {"EN_SW_DENORM", Const, 1, ""}, + {"EN_SW_INVOP", Const, 1, ""}, + {"EN_SW_OVERFLOW", Const, 1, ""}, + {"EN_SW_PRECLOSS", Const, 1, ""}, + {"EN_SW_UNDERFLOW", Const, 1, ""}, + {"EN_SW_ZERODIV", Const, 1, ""}, + {"EOPNOTSUPP", Const, 0, ""}, + {"EOVERFLOW", Const, 0, ""}, + {"EOWNERDEAD", Const, 0, ""}, + {"EPERM", Const, 0, ""}, + {"EPFNOSUPPORT", Const, 0, ""}, + {"EPIPE", Const, 0, ""}, + {"EPOLLERR", Const, 0, ""}, + {"EPOLLET", Const, 0, ""}, + {"EPOLLHUP", Const, 0, ""}, + {"EPOLLIN", Const, 0, ""}, + {"EPOLLMSG", Const, 0, ""}, + {"EPOLLONESHOT", Const, 0, ""}, + {"EPOLLOUT", Const, 0, ""}, + {"EPOLLPRI", Const, 0, ""}, + {"EPOLLRDBAND", Const, 0, ""}, + {"EPOLLRDHUP", Const, 0, ""}, + {"EPOLLRDNORM", Const, 0, ""}, + {"EPOLLWRBAND", Const, 0, ""}, + {"EPOLLWRNORM", Const, 0, ""}, + {"EPOLL_CLOEXEC", Const, 0, ""}, + {"EPOLL_CTL_ADD", Const, 0, ""}, + {"EPOLL_CTL_DEL", Const, 0, ""}, + {"EPOLL_CTL_MOD", Const, 0, ""}, + {"EPOLL_NONBLOCK", Const, 0, ""}, + {"EPROCLIM", Const, 0, ""}, + {"EPROCUNAVAIL", Const, 0, ""}, + {"EPROGMISMATCH", Const, 0, ""}, + {"EPROGUNAVAIL", Const, 0, ""}, + {"EPROTO", Const, 0, ""}, + {"EPROTONOSUPPORT", Const, 0, ""}, + {"EPROTOTYPE", Const, 0, ""}, + {"EPWROFF", Const, 0, ""}, + {"EQFULL", Const, 16, ""}, + {"ERANGE", Const, 0, ""}, + {"EREMCHG", Const, 0, ""}, + {"EREMOTE", Const, 0, ""}, + {"EREMOTEIO", Const, 0, ""}, + {"ERESTART", Const, 0, ""}, + {"ERFKILL", Const, 0, ""}, + {"EROFS", Const, 0, ""}, + {"ERPCMISMATCH", Const, 0, ""}, + {"ERROR_ACCESS_DENIED", Const, 0, ""}, + {"ERROR_ALREADY_EXISTS", Const, 0, ""}, + {"ERROR_BROKEN_PIPE", Const, 0, ""}, + {"ERROR_BUFFER_OVERFLOW", Const, 0, ""}, + {"ERROR_DIR_NOT_EMPTY", Const, 8, ""}, + {"ERROR_ENVVAR_NOT_FOUND", Const, 0, ""}, + {"ERROR_FILE_EXISTS", Const, 0, ""}, + {"ERROR_FILE_NOT_FOUND", Const, 0, ""}, + {"ERROR_HANDLE_EOF", Const, 2, ""}, + {"ERROR_INSUFFICIENT_BUFFER", Const, 0, ""}, + {"ERROR_IO_PENDING", Const, 0, ""}, + {"ERROR_MOD_NOT_FOUND", Const, 0, ""}, + {"ERROR_MORE_DATA", Const, 3, ""}, + {"ERROR_NETNAME_DELETED", Const, 3, ""}, + {"ERROR_NOT_FOUND", Const, 1, ""}, + {"ERROR_NO_MORE_FILES", Const, 0, ""}, + {"ERROR_OPERATION_ABORTED", Const, 0, ""}, + {"ERROR_PATH_NOT_FOUND", Const, 0, ""}, + {"ERROR_PRIVILEGE_NOT_HELD", Const, 4, ""}, + {"ERROR_PROC_NOT_FOUND", Const, 0, ""}, + {"ESHLIBVERS", Const, 0, ""}, + {"ESHUTDOWN", Const, 0, ""}, + {"ESOCKTNOSUPPORT", Const, 0, ""}, + {"ESPIPE", Const, 0, ""}, + {"ESRCH", Const, 0, ""}, + {"ESRMNT", Const, 0, ""}, + {"ESTALE", Const, 0, ""}, + {"ESTRPIPE", Const, 0, ""}, + {"ETHERCAP_JUMBO_MTU", Const, 1, ""}, + {"ETHERCAP_VLAN_HWTAGGING", Const, 1, ""}, + {"ETHERCAP_VLAN_MTU", Const, 1, ""}, + {"ETHERMIN", Const, 1, ""}, + {"ETHERMTU", Const, 1, ""}, + {"ETHERMTU_JUMBO", Const, 1, ""}, + {"ETHERTYPE_8023", Const, 1, ""}, + {"ETHERTYPE_AARP", Const, 1, ""}, + {"ETHERTYPE_ACCTON", Const, 1, ""}, + {"ETHERTYPE_AEONIC", Const, 1, ""}, + {"ETHERTYPE_ALPHA", Const, 1, ""}, + {"ETHERTYPE_AMBER", Const, 1, ""}, + {"ETHERTYPE_AMOEBA", Const, 1, ""}, + {"ETHERTYPE_AOE", Const, 1, ""}, + {"ETHERTYPE_APOLLO", Const, 1, ""}, + {"ETHERTYPE_APOLLODOMAIN", Const, 1, ""}, + {"ETHERTYPE_APPLETALK", Const, 1, ""}, + {"ETHERTYPE_APPLITEK", Const, 1, ""}, + {"ETHERTYPE_ARGONAUT", Const, 1, ""}, + {"ETHERTYPE_ARP", Const, 1, ""}, + {"ETHERTYPE_AT", Const, 1, ""}, + {"ETHERTYPE_ATALK", Const, 1, ""}, + {"ETHERTYPE_ATOMIC", Const, 1, ""}, + {"ETHERTYPE_ATT", Const, 1, ""}, + {"ETHERTYPE_ATTSTANFORD", Const, 1, ""}, + {"ETHERTYPE_AUTOPHON", Const, 1, ""}, + {"ETHERTYPE_AXIS", Const, 1, ""}, + {"ETHERTYPE_BCLOOP", Const, 1, ""}, + {"ETHERTYPE_BOFL", Const, 1, ""}, + {"ETHERTYPE_CABLETRON", Const, 1, ""}, + {"ETHERTYPE_CHAOS", Const, 1, ""}, + {"ETHERTYPE_COMDESIGN", Const, 1, ""}, + {"ETHERTYPE_COMPUGRAPHIC", Const, 1, ""}, + {"ETHERTYPE_COUNTERPOINT", Const, 1, ""}, + {"ETHERTYPE_CRONUS", Const, 1, ""}, + {"ETHERTYPE_CRONUSVLN", Const, 1, ""}, + {"ETHERTYPE_DCA", Const, 1, ""}, + {"ETHERTYPE_DDE", Const, 1, ""}, + {"ETHERTYPE_DEBNI", Const, 1, ""}, + {"ETHERTYPE_DECAM", Const, 1, ""}, + {"ETHERTYPE_DECCUST", Const, 1, ""}, + {"ETHERTYPE_DECDIAG", Const, 1, ""}, + {"ETHERTYPE_DECDNS", Const, 1, ""}, + {"ETHERTYPE_DECDTS", Const, 1, ""}, + {"ETHERTYPE_DECEXPER", Const, 1, ""}, + {"ETHERTYPE_DECLAST", Const, 1, ""}, + {"ETHERTYPE_DECLTM", Const, 1, ""}, + {"ETHERTYPE_DECMUMPS", Const, 1, ""}, + {"ETHERTYPE_DECNETBIOS", Const, 1, ""}, + {"ETHERTYPE_DELTACON", Const, 1, ""}, + {"ETHERTYPE_DIDDLE", Const, 1, ""}, + {"ETHERTYPE_DLOG1", Const, 1, ""}, + {"ETHERTYPE_DLOG2", Const, 1, ""}, + {"ETHERTYPE_DN", Const, 1, ""}, + {"ETHERTYPE_DOGFIGHT", Const, 1, ""}, + {"ETHERTYPE_DSMD", Const, 1, ""}, + {"ETHERTYPE_ECMA", Const, 1, ""}, + {"ETHERTYPE_ENCRYPT", Const, 1, ""}, + {"ETHERTYPE_ES", Const, 1, ""}, + {"ETHERTYPE_EXCELAN", Const, 1, ""}, + {"ETHERTYPE_EXPERDATA", Const, 1, ""}, + {"ETHERTYPE_FLIP", Const, 1, ""}, + {"ETHERTYPE_FLOWCONTROL", Const, 1, ""}, + {"ETHERTYPE_FRARP", Const, 1, ""}, + {"ETHERTYPE_GENDYN", Const, 1, ""}, + {"ETHERTYPE_HAYES", Const, 1, ""}, + {"ETHERTYPE_HIPPI_FP", Const, 1, ""}, + {"ETHERTYPE_HITACHI", Const, 1, ""}, + {"ETHERTYPE_HP", Const, 1, ""}, + {"ETHERTYPE_IEEEPUP", Const, 1, ""}, + {"ETHERTYPE_IEEEPUPAT", Const, 1, ""}, + {"ETHERTYPE_IMLBL", Const, 1, ""}, + {"ETHERTYPE_IMLBLDIAG", Const, 1, ""}, + {"ETHERTYPE_IP", Const, 1, ""}, + {"ETHERTYPE_IPAS", Const, 1, ""}, + {"ETHERTYPE_IPV6", Const, 1, ""}, + {"ETHERTYPE_IPX", Const, 1, ""}, + {"ETHERTYPE_IPXNEW", Const, 1, ""}, + {"ETHERTYPE_KALPANA", Const, 1, ""}, + {"ETHERTYPE_LANBRIDGE", Const, 1, ""}, + {"ETHERTYPE_LANPROBE", Const, 1, ""}, + {"ETHERTYPE_LAT", Const, 1, ""}, + {"ETHERTYPE_LBACK", Const, 1, ""}, + {"ETHERTYPE_LITTLE", Const, 1, ""}, + {"ETHERTYPE_LLDP", Const, 1, ""}, + {"ETHERTYPE_LOGICRAFT", Const, 1, ""}, + {"ETHERTYPE_LOOPBACK", Const, 1, ""}, + {"ETHERTYPE_MATRA", Const, 1, ""}, + {"ETHERTYPE_MAX", Const, 1, ""}, + {"ETHERTYPE_MERIT", Const, 1, ""}, + {"ETHERTYPE_MICP", Const, 1, ""}, + {"ETHERTYPE_MOPDL", Const, 1, ""}, + {"ETHERTYPE_MOPRC", Const, 1, ""}, + {"ETHERTYPE_MOTOROLA", Const, 1, ""}, + {"ETHERTYPE_MPLS", Const, 1, ""}, + {"ETHERTYPE_MPLS_MCAST", Const, 1, ""}, + {"ETHERTYPE_MUMPS", Const, 1, ""}, + {"ETHERTYPE_NBPCC", Const, 1, ""}, + {"ETHERTYPE_NBPCLAIM", Const, 1, ""}, + {"ETHERTYPE_NBPCLREQ", Const, 1, ""}, + {"ETHERTYPE_NBPCLRSP", Const, 1, ""}, + {"ETHERTYPE_NBPCREQ", Const, 1, ""}, + {"ETHERTYPE_NBPCRSP", Const, 1, ""}, + {"ETHERTYPE_NBPDG", Const, 1, ""}, + {"ETHERTYPE_NBPDGB", Const, 1, ""}, + {"ETHERTYPE_NBPDLTE", Const, 1, ""}, + {"ETHERTYPE_NBPRAR", Const, 1, ""}, + {"ETHERTYPE_NBPRAS", Const, 1, ""}, + {"ETHERTYPE_NBPRST", Const, 1, ""}, + {"ETHERTYPE_NBPSCD", Const, 1, ""}, + {"ETHERTYPE_NBPVCD", Const, 1, ""}, + {"ETHERTYPE_NBS", Const, 1, ""}, + {"ETHERTYPE_NCD", Const, 1, ""}, + {"ETHERTYPE_NESTAR", Const, 1, ""}, + {"ETHERTYPE_NETBEUI", Const, 1, ""}, + {"ETHERTYPE_NOVELL", Const, 1, ""}, + {"ETHERTYPE_NS", Const, 1, ""}, + {"ETHERTYPE_NSAT", Const, 1, ""}, + {"ETHERTYPE_NSCOMPAT", Const, 1, ""}, + {"ETHERTYPE_NTRAILER", Const, 1, ""}, + {"ETHERTYPE_OS9", Const, 1, ""}, + {"ETHERTYPE_OS9NET", Const, 1, ""}, + {"ETHERTYPE_PACER", Const, 1, ""}, + {"ETHERTYPE_PAE", Const, 1, ""}, + {"ETHERTYPE_PCS", Const, 1, ""}, + {"ETHERTYPE_PLANNING", Const, 1, ""}, + {"ETHERTYPE_PPP", Const, 1, ""}, + {"ETHERTYPE_PPPOE", Const, 1, ""}, + {"ETHERTYPE_PPPOEDISC", Const, 1, ""}, + {"ETHERTYPE_PRIMENTS", Const, 1, ""}, + {"ETHERTYPE_PUP", Const, 1, ""}, + {"ETHERTYPE_PUPAT", Const, 1, ""}, + {"ETHERTYPE_QINQ", Const, 1, ""}, + {"ETHERTYPE_RACAL", Const, 1, ""}, + {"ETHERTYPE_RATIONAL", Const, 1, ""}, + {"ETHERTYPE_RAWFR", Const, 1, ""}, + {"ETHERTYPE_RCL", Const, 1, ""}, + {"ETHERTYPE_RDP", Const, 1, ""}, + {"ETHERTYPE_RETIX", Const, 1, ""}, + {"ETHERTYPE_REVARP", Const, 1, ""}, + {"ETHERTYPE_SCA", Const, 1, ""}, + {"ETHERTYPE_SECTRA", Const, 1, ""}, + {"ETHERTYPE_SECUREDATA", Const, 1, ""}, + {"ETHERTYPE_SGITW", Const, 1, ""}, + {"ETHERTYPE_SG_BOUNCE", Const, 1, ""}, + {"ETHERTYPE_SG_DIAG", Const, 1, ""}, + {"ETHERTYPE_SG_NETGAMES", Const, 1, ""}, + {"ETHERTYPE_SG_RESV", Const, 1, ""}, + {"ETHERTYPE_SIMNET", Const, 1, ""}, + {"ETHERTYPE_SLOW", Const, 1, ""}, + {"ETHERTYPE_SLOWPROTOCOLS", Const, 1, ""}, + {"ETHERTYPE_SNA", Const, 1, ""}, + {"ETHERTYPE_SNMP", Const, 1, ""}, + {"ETHERTYPE_SONIX", Const, 1, ""}, + {"ETHERTYPE_SPIDER", Const, 1, ""}, + {"ETHERTYPE_SPRITE", Const, 1, ""}, + {"ETHERTYPE_STP", Const, 1, ""}, + {"ETHERTYPE_TALARIS", Const, 1, ""}, + {"ETHERTYPE_TALARISMC", Const, 1, ""}, + {"ETHERTYPE_TCPCOMP", Const, 1, ""}, + {"ETHERTYPE_TCPSM", Const, 1, ""}, + {"ETHERTYPE_TEC", Const, 1, ""}, + {"ETHERTYPE_TIGAN", Const, 1, ""}, + {"ETHERTYPE_TRAIL", Const, 1, ""}, + {"ETHERTYPE_TRANSETHER", Const, 1, ""}, + {"ETHERTYPE_TYMSHARE", Const, 1, ""}, + {"ETHERTYPE_UBBST", Const, 1, ""}, + {"ETHERTYPE_UBDEBUG", Const, 1, ""}, + {"ETHERTYPE_UBDIAGLOOP", Const, 1, ""}, + {"ETHERTYPE_UBDL", Const, 1, ""}, + {"ETHERTYPE_UBNIU", Const, 1, ""}, + {"ETHERTYPE_UBNMC", Const, 1, ""}, + {"ETHERTYPE_VALID", Const, 1, ""}, + {"ETHERTYPE_VARIAN", Const, 1, ""}, + {"ETHERTYPE_VAXELN", Const, 1, ""}, + {"ETHERTYPE_VEECO", Const, 1, ""}, + {"ETHERTYPE_VEXP", Const, 1, ""}, + {"ETHERTYPE_VGLAB", Const, 1, ""}, + {"ETHERTYPE_VINES", Const, 1, ""}, + {"ETHERTYPE_VINESECHO", Const, 1, ""}, + {"ETHERTYPE_VINESLOOP", Const, 1, ""}, + {"ETHERTYPE_VITAL", Const, 1, ""}, + {"ETHERTYPE_VLAN", Const, 1, ""}, + {"ETHERTYPE_VLTLMAN", Const, 1, ""}, + {"ETHERTYPE_VPROD", Const, 1, ""}, + {"ETHERTYPE_VURESERVED", Const, 1, ""}, + {"ETHERTYPE_WATERLOO", Const, 1, ""}, + {"ETHERTYPE_WELLFLEET", Const, 1, ""}, + {"ETHERTYPE_X25", Const, 1, ""}, + {"ETHERTYPE_X75", Const, 1, ""}, + {"ETHERTYPE_XNSSM", Const, 1, ""}, + {"ETHERTYPE_XTP", Const, 1, ""}, + {"ETHER_ADDR_LEN", Const, 1, ""}, + {"ETHER_ALIGN", Const, 1, ""}, + {"ETHER_CRC_LEN", Const, 1, ""}, + {"ETHER_CRC_POLY_BE", Const, 1, ""}, + {"ETHER_CRC_POLY_LE", Const, 1, ""}, + {"ETHER_HDR_LEN", Const, 1, ""}, + {"ETHER_MAX_DIX_LEN", Const, 1, ""}, + {"ETHER_MAX_LEN", Const, 1, ""}, + {"ETHER_MAX_LEN_JUMBO", Const, 1, ""}, + {"ETHER_MIN_LEN", Const, 1, ""}, + {"ETHER_PPPOE_ENCAP_LEN", Const, 1, ""}, + {"ETHER_TYPE_LEN", Const, 1, ""}, + {"ETHER_VLAN_ENCAP_LEN", Const, 1, ""}, + {"ETH_P_1588", Const, 0, ""}, + {"ETH_P_8021Q", Const, 0, ""}, + {"ETH_P_802_2", Const, 0, ""}, + {"ETH_P_802_3", Const, 0, ""}, + {"ETH_P_AARP", Const, 0, ""}, + {"ETH_P_ALL", Const, 0, ""}, + {"ETH_P_AOE", Const, 0, ""}, + {"ETH_P_ARCNET", Const, 0, ""}, + {"ETH_P_ARP", Const, 0, ""}, + {"ETH_P_ATALK", Const, 0, ""}, + {"ETH_P_ATMFATE", Const, 0, ""}, + {"ETH_P_ATMMPOA", Const, 0, ""}, + {"ETH_P_AX25", Const, 0, ""}, + {"ETH_P_BPQ", Const, 0, ""}, + {"ETH_P_CAIF", Const, 0, ""}, + {"ETH_P_CAN", Const, 0, ""}, + {"ETH_P_CONTROL", Const, 0, ""}, + {"ETH_P_CUST", Const, 0, ""}, + {"ETH_P_DDCMP", Const, 0, ""}, + {"ETH_P_DEC", Const, 0, ""}, + {"ETH_P_DIAG", Const, 0, ""}, + {"ETH_P_DNA_DL", Const, 0, ""}, + {"ETH_P_DNA_RC", Const, 0, ""}, + {"ETH_P_DNA_RT", Const, 0, ""}, + {"ETH_P_DSA", Const, 0, ""}, + {"ETH_P_ECONET", Const, 0, ""}, + {"ETH_P_EDSA", Const, 0, ""}, + {"ETH_P_FCOE", Const, 0, ""}, + {"ETH_P_FIP", Const, 0, ""}, + {"ETH_P_HDLC", Const, 0, ""}, + {"ETH_P_IEEE802154", Const, 0, ""}, + {"ETH_P_IEEEPUP", Const, 0, ""}, + {"ETH_P_IEEEPUPAT", Const, 0, ""}, + {"ETH_P_IP", Const, 0, ""}, + {"ETH_P_IPV6", Const, 0, ""}, + {"ETH_P_IPX", Const, 0, ""}, + {"ETH_P_IRDA", Const, 0, ""}, + {"ETH_P_LAT", Const, 0, ""}, + {"ETH_P_LINK_CTL", Const, 0, ""}, + {"ETH_P_LOCALTALK", Const, 0, ""}, + {"ETH_P_LOOP", Const, 0, ""}, + {"ETH_P_MOBITEX", Const, 0, ""}, + {"ETH_P_MPLS_MC", Const, 0, ""}, + {"ETH_P_MPLS_UC", Const, 0, ""}, + {"ETH_P_PAE", Const, 0, ""}, + {"ETH_P_PAUSE", Const, 0, ""}, + {"ETH_P_PHONET", Const, 0, ""}, + {"ETH_P_PPPTALK", Const, 0, ""}, + {"ETH_P_PPP_DISC", Const, 0, ""}, + {"ETH_P_PPP_MP", Const, 0, ""}, + {"ETH_P_PPP_SES", Const, 0, ""}, + {"ETH_P_PUP", Const, 0, ""}, + {"ETH_P_PUPAT", Const, 0, ""}, + {"ETH_P_RARP", Const, 0, ""}, + {"ETH_P_SCA", Const, 0, ""}, + {"ETH_P_SLOW", Const, 0, ""}, + {"ETH_P_SNAP", Const, 0, ""}, + {"ETH_P_TEB", Const, 0, ""}, + {"ETH_P_TIPC", Const, 0, ""}, + {"ETH_P_TRAILER", Const, 0, ""}, + {"ETH_P_TR_802_2", Const, 0, ""}, + {"ETH_P_WAN_PPP", Const, 0, ""}, + {"ETH_P_WCCP", Const, 0, ""}, + {"ETH_P_X25", Const, 0, ""}, + {"ETIME", Const, 0, ""}, + {"ETIMEDOUT", Const, 0, ""}, + {"ETOOMANYREFS", Const, 0, ""}, + {"ETXTBSY", Const, 0, ""}, + {"EUCLEAN", Const, 0, ""}, + {"EUNATCH", Const, 0, ""}, + {"EUSERS", Const, 0, ""}, + {"EVFILT_AIO", Const, 0, ""}, + {"EVFILT_FS", Const, 0, ""}, + {"EVFILT_LIO", Const, 0, ""}, + {"EVFILT_MACHPORT", Const, 0, ""}, + {"EVFILT_PROC", Const, 0, ""}, + {"EVFILT_READ", Const, 0, ""}, + {"EVFILT_SIGNAL", Const, 0, ""}, + {"EVFILT_SYSCOUNT", Const, 0, ""}, + {"EVFILT_THREADMARKER", Const, 0, ""}, + {"EVFILT_TIMER", Const, 0, ""}, + {"EVFILT_USER", Const, 0, ""}, + {"EVFILT_VM", Const, 0, ""}, + {"EVFILT_VNODE", Const, 0, ""}, + {"EVFILT_WRITE", Const, 0, ""}, + {"EV_ADD", Const, 0, ""}, + {"EV_CLEAR", Const, 0, ""}, + {"EV_DELETE", Const, 0, ""}, + {"EV_DISABLE", Const, 0, ""}, + {"EV_DISPATCH", Const, 0, ""}, + {"EV_DROP", Const, 3, ""}, + {"EV_ENABLE", Const, 0, ""}, + {"EV_EOF", Const, 0, ""}, + {"EV_ERROR", Const, 0, ""}, + {"EV_FLAG0", Const, 0, ""}, + {"EV_FLAG1", Const, 0, ""}, + {"EV_ONESHOT", Const, 0, ""}, + {"EV_OOBAND", Const, 0, ""}, + {"EV_POLL", Const, 0, ""}, + {"EV_RECEIPT", Const, 0, ""}, + {"EV_SYSFLAGS", Const, 0, ""}, + {"EWINDOWS", Const, 0, ""}, + {"EWOULDBLOCK", Const, 0, ""}, + {"EXDEV", Const, 0, ""}, + {"EXFULL", Const, 0, ""}, + {"EXTA", Const, 0, ""}, + {"EXTB", Const, 0, ""}, + {"EXTPROC", Const, 0, ""}, + {"Environ", Func, 0, "func() []string"}, + {"EpollCreate", Func, 0, "func(size int) (fd int, err error)"}, + {"EpollCreate1", Func, 0, "func(flag int) (fd int, err error)"}, + {"EpollCtl", Func, 0, "func(epfd int, op int, fd int, event *EpollEvent) (err error)"}, + {"EpollEvent", Type, 0, ""}, + {"EpollEvent.Events", Field, 0, ""}, + {"EpollEvent.Fd", Field, 0, ""}, + {"EpollEvent.Pad", Field, 0, ""}, + {"EpollEvent.PadFd", Field, 0, ""}, + {"EpollWait", Func, 0, "func(epfd int, events []EpollEvent, msec int) (n int, err error)"}, + {"Errno", Type, 0, ""}, + {"EscapeArg", Func, 0, ""}, + {"Exchangedata", Func, 0, ""}, + {"Exec", Func, 0, "func(argv0 string, argv []string, envv []string) (err error)"}, + {"Exit", Func, 0, "func(code int)"}, + {"ExitProcess", Func, 0, ""}, + {"FD_CLOEXEC", Const, 0, ""}, + {"FD_SETSIZE", Const, 0, ""}, + {"FILE_ACTION_ADDED", Const, 0, ""}, + {"FILE_ACTION_MODIFIED", Const, 0, ""}, + {"FILE_ACTION_REMOVED", Const, 0, ""}, + {"FILE_ACTION_RENAMED_NEW_NAME", Const, 0, ""}, + {"FILE_ACTION_RENAMED_OLD_NAME", Const, 0, ""}, + {"FILE_APPEND_DATA", Const, 0, ""}, + {"FILE_ATTRIBUTE_ARCHIVE", Const, 0, ""}, + {"FILE_ATTRIBUTE_DIRECTORY", Const, 0, ""}, + {"FILE_ATTRIBUTE_HIDDEN", Const, 0, ""}, + {"FILE_ATTRIBUTE_NORMAL", Const, 0, ""}, + {"FILE_ATTRIBUTE_READONLY", Const, 0, ""}, + {"FILE_ATTRIBUTE_REPARSE_POINT", Const, 4, ""}, + {"FILE_ATTRIBUTE_SYSTEM", Const, 0, ""}, + {"FILE_BEGIN", Const, 0, ""}, + {"FILE_CURRENT", Const, 0, ""}, + {"FILE_END", Const, 0, ""}, + {"FILE_FLAG_BACKUP_SEMANTICS", Const, 0, ""}, + {"FILE_FLAG_OPEN_REPARSE_POINT", Const, 4, ""}, + {"FILE_FLAG_OVERLAPPED", Const, 0, ""}, + {"FILE_LIST_DIRECTORY", Const, 0, ""}, + {"FILE_MAP_COPY", Const, 0, ""}, + {"FILE_MAP_EXECUTE", Const, 0, ""}, + {"FILE_MAP_READ", Const, 0, ""}, + {"FILE_MAP_WRITE", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_ATTRIBUTES", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_CREATION", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_DIR_NAME", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_FILE_NAME", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_LAST_ACCESS", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_LAST_WRITE", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_SIZE", Const, 0, ""}, + {"FILE_SHARE_DELETE", Const, 0, ""}, + {"FILE_SHARE_READ", Const, 0, ""}, + {"FILE_SHARE_WRITE", Const, 0, ""}, + {"FILE_SKIP_COMPLETION_PORT_ON_SUCCESS", Const, 2, ""}, + {"FILE_SKIP_SET_EVENT_ON_HANDLE", Const, 2, ""}, + {"FILE_TYPE_CHAR", Const, 0, ""}, + {"FILE_TYPE_DISK", Const, 0, ""}, + {"FILE_TYPE_PIPE", Const, 0, ""}, + {"FILE_TYPE_REMOTE", Const, 0, ""}, + {"FILE_TYPE_UNKNOWN", Const, 0, ""}, + {"FILE_WRITE_ATTRIBUTES", Const, 0, ""}, + {"FLUSHO", Const, 0, ""}, + {"FORMAT_MESSAGE_ALLOCATE_BUFFER", Const, 0, ""}, + {"FORMAT_MESSAGE_ARGUMENT_ARRAY", Const, 0, ""}, + {"FORMAT_MESSAGE_FROM_HMODULE", Const, 0, ""}, + {"FORMAT_MESSAGE_FROM_STRING", Const, 0, ""}, + {"FORMAT_MESSAGE_FROM_SYSTEM", Const, 0, ""}, + {"FORMAT_MESSAGE_IGNORE_INSERTS", Const, 0, ""}, + {"FORMAT_MESSAGE_MAX_WIDTH_MASK", Const, 0, ""}, + {"FSCTL_GET_REPARSE_POINT", Const, 4, ""}, + {"F_ADDFILESIGS", Const, 0, ""}, + {"F_ADDSIGS", Const, 0, ""}, + {"F_ALLOCATEALL", Const, 0, ""}, + {"F_ALLOCATECONTIG", Const, 0, ""}, + {"F_CANCEL", Const, 0, ""}, + {"F_CHKCLEAN", Const, 0, ""}, + {"F_CLOSEM", Const, 1, ""}, + {"F_DUP2FD", Const, 0, ""}, + {"F_DUP2FD_CLOEXEC", Const, 1, ""}, + {"F_DUPFD", Const, 0, ""}, + {"F_DUPFD_CLOEXEC", Const, 0, ""}, + {"F_EXLCK", Const, 0, ""}, + {"F_FINDSIGS", Const, 16, ""}, + {"F_FLUSH_DATA", Const, 0, ""}, + {"F_FREEZE_FS", Const, 0, ""}, + {"F_FSCTL", Const, 1, ""}, + {"F_FSDIRMASK", Const, 1, ""}, + {"F_FSIN", Const, 1, ""}, + {"F_FSINOUT", Const, 1, ""}, + {"F_FSOUT", Const, 1, ""}, + {"F_FSPRIV", Const, 1, ""}, + {"F_FSVOID", Const, 1, ""}, + {"F_FULLFSYNC", Const, 0, ""}, + {"F_GETCODEDIR", Const, 16, ""}, + {"F_GETFD", Const, 0, ""}, + {"F_GETFL", Const, 0, ""}, + {"F_GETLEASE", Const, 0, ""}, + {"F_GETLK", Const, 0, ""}, + {"F_GETLK64", Const, 0, ""}, + {"F_GETLKPID", Const, 0, ""}, + {"F_GETNOSIGPIPE", Const, 0, ""}, + {"F_GETOWN", Const, 0, ""}, + {"F_GETOWN_EX", Const, 0, ""}, + {"F_GETPATH", Const, 0, ""}, + {"F_GETPATH_MTMINFO", Const, 0, ""}, + {"F_GETPIPE_SZ", Const, 0, ""}, + {"F_GETPROTECTIONCLASS", Const, 0, ""}, + {"F_GETPROTECTIONLEVEL", Const, 16, ""}, + {"F_GETSIG", Const, 0, ""}, + {"F_GLOBAL_NOCACHE", Const, 0, ""}, + {"F_LOCK", Const, 0, ""}, + {"F_LOG2PHYS", Const, 0, ""}, + {"F_LOG2PHYS_EXT", Const, 0, ""}, + {"F_MARKDEPENDENCY", Const, 0, ""}, + {"F_MAXFD", Const, 1, ""}, + {"F_NOCACHE", Const, 0, ""}, + {"F_NODIRECT", Const, 0, ""}, + {"F_NOTIFY", Const, 0, ""}, + {"F_OGETLK", Const, 0, ""}, + {"F_OK", Const, 0, ""}, + {"F_OSETLK", Const, 0, ""}, + {"F_OSETLKW", Const, 0, ""}, + {"F_PARAM_MASK", Const, 1, ""}, + {"F_PARAM_MAX", Const, 1, ""}, + {"F_PATHPKG_CHECK", Const, 0, ""}, + {"F_PEOFPOSMODE", Const, 0, ""}, + {"F_PREALLOCATE", Const, 0, ""}, + {"F_RDADVISE", Const, 0, ""}, + {"F_RDAHEAD", Const, 0, ""}, + {"F_RDLCK", Const, 0, ""}, + {"F_READAHEAD", Const, 0, ""}, + {"F_READBOOTSTRAP", Const, 0, ""}, + {"F_SETBACKINGSTORE", Const, 0, ""}, + {"F_SETFD", Const, 0, ""}, + {"F_SETFL", Const, 0, ""}, + {"F_SETLEASE", Const, 0, ""}, + {"F_SETLK", Const, 0, ""}, + {"F_SETLK64", Const, 0, ""}, + {"F_SETLKW", Const, 0, ""}, + {"F_SETLKW64", Const, 0, ""}, + {"F_SETLKWTIMEOUT", Const, 16, ""}, + {"F_SETLK_REMOTE", Const, 0, ""}, + {"F_SETNOSIGPIPE", Const, 0, ""}, + {"F_SETOWN", Const, 0, ""}, + {"F_SETOWN_EX", Const, 0, ""}, + {"F_SETPIPE_SZ", Const, 0, ""}, + {"F_SETPROTECTIONCLASS", Const, 0, ""}, + {"F_SETSIG", Const, 0, ""}, + {"F_SETSIZE", Const, 0, ""}, + {"F_SHLCK", Const, 0, ""}, + {"F_SINGLE_WRITER", Const, 16, ""}, + {"F_TEST", Const, 0, ""}, + {"F_THAW_FS", Const, 0, ""}, + {"F_TLOCK", Const, 0, ""}, + {"F_TRANSCODEKEY", Const, 16, ""}, + {"F_ULOCK", Const, 0, ""}, + {"F_UNLCK", Const, 0, ""}, + {"F_UNLCKSYS", Const, 0, ""}, + {"F_VOLPOSMODE", Const, 0, ""}, + {"F_WRITEBOOTSTRAP", Const, 0, ""}, + {"F_WRLCK", Const, 0, ""}, + {"Faccessat", Func, 0, "func(dirfd int, path string, mode uint32, flags int) (err error)"}, + {"Fallocate", Func, 0, "func(fd int, mode uint32, off int64, len int64) (err error)"}, + {"Fbootstraptransfer_t", Type, 0, ""}, + {"Fbootstraptransfer_t.Buffer", Field, 0, ""}, + {"Fbootstraptransfer_t.Length", Field, 0, ""}, + {"Fbootstraptransfer_t.Offset", Field, 0, ""}, + {"Fchdir", Func, 0, "func(fd int) (err error)"}, + {"Fchflags", Func, 0, ""}, + {"Fchmod", Func, 0, "func(fd int, mode uint32) (err error)"}, + {"Fchmodat", Func, 0, "func(dirfd int, path string, mode uint32, flags int) error"}, + {"Fchown", Func, 0, "func(fd int, uid int, gid int) (err error)"}, + {"Fchownat", Func, 0, "func(dirfd int, path string, uid int, gid int, flags int) (err error)"}, + {"FcntlFlock", Func, 3, "func(fd uintptr, cmd int, lk *Flock_t) error"}, + {"FdSet", Type, 0, ""}, + {"FdSet.Bits", Field, 0, ""}, + {"FdSet.X__fds_bits", Field, 0, ""}, + {"Fdatasync", Func, 0, "func(fd int) (err error)"}, + {"FileNotifyInformation", Type, 0, ""}, + {"FileNotifyInformation.Action", Field, 0, ""}, + {"FileNotifyInformation.FileName", Field, 0, ""}, + {"FileNotifyInformation.FileNameLength", Field, 0, ""}, + {"FileNotifyInformation.NextEntryOffset", Field, 0, ""}, + {"Filetime", Type, 0, ""}, + {"Filetime.HighDateTime", Field, 0, ""}, + {"Filetime.LowDateTime", Field, 0, ""}, + {"FindClose", Func, 0, ""}, + {"FindFirstFile", Func, 0, ""}, + {"FindNextFile", Func, 0, ""}, + {"Flock", Func, 0, "func(fd int, how int) (err error)"}, + {"Flock_t", Type, 0, ""}, + {"Flock_t.Len", Field, 0, ""}, + {"Flock_t.Pad_cgo_0", Field, 0, ""}, + {"Flock_t.Pad_cgo_1", Field, 3, ""}, + {"Flock_t.Pid", Field, 0, ""}, + {"Flock_t.Start", Field, 0, ""}, + {"Flock_t.Sysid", Field, 0, ""}, + {"Flock_t.Type", Field, 0, ""}, + {"Flock_t.Whence", Field, 0, ""}, + {"FlushBpf", Func, 0, ""}, + {"FlushFileBuffers", Func, 0, ""}, + {"FlushViewOfFile", Func, 0, ""}, + {"ForkExec", Func, 0, "func(argv0 string, argv []string, attr *ProcAttr) (pid int, err error)"}, + {"ForkLock", Var, 0, ""}, + {"FormatMessage", Func, 0, ""}, + {"Fpathconf", Func, 0, ""}, + {"FreeAddrInfoW", Func, 1, ""}, + {"FreeEnvironmentStrings", Func, 0, ""}, + {"FreeLibrary", Func, 0, ""}, + {"Fsid", Type, 0, ""}, + {"Fsid.Val", Field, 0, ""}, + {"Fsid.X__fsid_val", Field, 2, ""}, + {"Fsid.X__val", Field, 0, ""}, + {"Fstat", Func, 0, "func(fd int, stat *Stat_t) (err error)"}, + {"Fstatat", Func, 12, ""}, + {"Fstatfs", Func, 0, "func(fd int, buf *Statfs_t) (err error)"}, + {"Fstore_t", Type, 0, ""}, + {"Fstore_t.Bytesalloc", Field, 0, ""}, + {"Fstore_t.Flags", Field, 0, ""}, + {"Fstore_t.Length", Field, 0, ""}, + {"Fstore_t.Offset", Field, 0, ""}, + {"Fstore_t.Posmode", Field, 0, ""}, + {"Fsync", Func, 0, "func(fd int) (err error)"}, + {"Ftruncate", Func, 0, "func(fd int, length int64) (err error)"}, + {"FullPath", Func, 4, ""}, + {"Futimes", Func, 0, "func(fd int, tv []Timeval) (err error)"}, + {"Futimesat", Func, 0, "func(dirfd int, path string, tv []Timeval) (err error)"}, + {"GENERIC_ALL", Const, 0, ""}, + {"GENERIC_EXECUTE", Const, 0, ""}, + {"GENERIC_READ", Const, 0, ""}, + {"GENERIC_WRITE", Const, 0, ""}, + {"GUID", Type, 1, ""}, + {"GUID.Data1", Field, 1, ""}, + {"GUID.Data2", Field, 1, ""}, + {"GUID.Data3", Field, 1, ""}, + {"GUID.Data4", Field, 1, ""}, + {"GetAcceptExSockaddrs", Func, 0, ""}, + {"GetAdaptersInfo", Func, 0, ""}, + {"GetAddrInfoW", Func, 1, ""}, + {"GetCommandLine", Func, 0, ""}, + {"GetComputerName", Func, 0, ""}, + {"GetConsoleMode", Func, 1, ""}, + {"GetCurrentDirectory", Func, 0, ""}, + {"GetCurrentProcess", Func, 0, ""}, + {"GetEnvironmentStrings", Func, 0, ""}, + {"GetEnvironmentVariable", Func, 0, ""}, + {"GetExitCodeProcess", Func, 0, ""}, + {"GetFileAttributes", Func, 0, ""}, + {"GetFileAttributesEx", Func, 0, ""}, + {"GetFileExInfoStandard", Const, 0, ""}, + {"GetFileExMaxInfoLevel", Const, 0, ""}, + {"GetFileInformationByHandle", Func, 0, ""}, + {"GetFileType", Func, 0, ""}, + {"GetFullPathName", Func, 0, ""}, + {"GetHostByName", Func, 0, ""}, + {"GetIfEntry", Func, 0, ""}, + {"GetLastError", Func, 0, ""}, + {"GetLengthSid", Func, 0, ""}, + {"GetLongPathName", Func, 0, ""}, + {"GetProcAddress", Func, 0, ""}, + {"GetProcessTimes", Func, 0, ""}, + {"GetProtoByName", Func, 0, ""}, + {"GetQueuedCompletionStatus", Func, 0, ""}, + {"GetServByName", Func, 0, ""}, + {"GetShortPathName", Func, 0, ""}, + {"GetStartupInfo", Func, 0, ""}, + {"GetStdHandle", Func, 0, ""}, + {"GetSystemTimeAsFileTime", Func, 0, ""}, + {"GetTempPath", Func, 0, ""}, + {"GetTimeZoneInformation", Func, 0, ""}, + {"GetTokenInformation", Func, 0, ""}, + {"GetUserNameEx", Func, 0, ""}, + {"GetUserProfileDirectory", Func, 0, ""}, + {"GetVersion", Func, 0, ""}, + {"Getcwd", Func, 0, "func(buf []byte) (n int, err error)"}, + {"Getdents", Func, 0, "func(fd int, buf []byte) (n int, err error)"}, + {"Getdirentries", Func, 0, ""}, + {"Getdtablesize", Func, 0, ""}, + {"Getegid", Func, 0, "func() (egid int)"}, + {"Getenv", Func, 0, "func(key string) (value string, found bool)"}, + {"Geteuid", Func, 0, "func() (euid int)"}, + {"Getfsstat", Func, 0, ""}, + {"Getgid", Func, 0, "func() (gid int)"}, + {"Getgroups", Func, 0, "func() (gids []int, err error)"}, + {"Getpagesize", Func, 0, "func() int"}, + {"Getpeername", Func, 0, "func(fd int) (sa Sockaddr, err error)"}, + {"Getpgid", Func, 0, "func(pid int) (pgid int, err error)"}, + {"Getpgrp", Func, 0, "func() (pid int)"}, + {"Getpid", Func, 0, "func() (pid int)"}, + {"Getppid", Func, 0, "func() (ppid int)"}, + {"Getpriority", Func, 0, "func(which int, who int) (prio int, err error)"}, + {"Getrlimit", Func, 0, "func(resource int, rlim *Rlimit) (err error)"}, + {"Getrusage", Func, 0, "func(who int, rusage *Rusage) (err error)"}, + {"Getsid", Func, 0, ""}, + {"Getsockname", Func, 0, "func(fd int) (sa Sockaddr, err error)"}, + {"Getsockopt", Func, 1, ""}, + {"GetsockoptByte", Func, 0, ""}, + {"GetsockoptICMPv6Filter", Func, 2, "func(fd int, level int, opt int) (*ICMPv6Filter, error)"}, + {"GetsockoptIPMreq", Func, 0, "func(fd int, level int, opt int) (*IPMreq, error)"}, + {"GetsockoptIPMreqn", Func, 0, "func(fd int, level int, opt int) (*IPMreqn, error)"}, + {"GetsockoptIPv6MTUInfo", Func, 2, "func(fd int, level int, opt int) (*IPv6MTUInfo, error)"}, + {"GetsockoptIPv6Mreq", Func, 0, "func(fd int, level int, opt int) (*IPv6Mreq, error)"}, + {"GetsockoptInet4Addr", Func, 0, "func(fd int, level int, opt int) (value [4]byte, err error)"}, + {"GetsockoptInt", Func, 0, "func(fd int, level int, opt int) (value int, err error)"}, + {"GetsockoptUcred", Func, 1, "func(fd int, level int, opt int) (*Ucred, error)"}, + {"Gettid", Func, 0, "func() (tid int)"}, + {"Gettimeofday", Func, 0, "func(tv *Timeval) (err error)"}, + {"Getuid", Func, 0, "func() (uid int)"}, + {"Getwd", Func, 0, "func() (wd string, err error)"}, + {"Getxattr", Func, 1, "func(path string, attr string, dest []byte) (sz int, err error)"}, + {"HANDLE_FLAG_INHERIT", Const, 0, ""}, + {"HKEY_CLASSES_ROOT", Const, 0, ""}, + {"HKEY_CURRENT_CONFIG", Const, 0, ""}, + {"HKEY_CURRENT_USER", Const, 0, ""}, + {"HKEY_DYN_DATA", Const, 0, ""}, + {"HKEY_LOCAL_MACHINE", Const, 0, ""}, + {"HKEY_PERFORMANCE_DATA", Const, 0, ""}, + {"HKEY_USERS", Const, 0, ""}, + {"HUPCL", Const, 0, ""}, + {"Handle", Type, 0, ""}, + {"Hostent", Type, 0, ""}, + {"Hostent.AddrList", Field, 0, ""}, + {"Hostent.AddrType", Field, 0, ""}, + {"Hostent.Aliases", Field, 0, ""}, + {"Hostent.Length", Field, 0, ""}, + {"Hostent.Name", Field, 0, ""}, + {"ICANON", Const, 0, ""}, + {"ICMP6_FILTER", Const, 2, ""}, + {"ICMPV6_FILTER", Const, 2, ""}, + {"ICMPv6Filter", Type, 2, ""}, + {"ICMPv6Filter.Data", Field, 2, ""}, + {"ICMPv6Filter.Filt", Field, 2, ""}, + {"ICRNL", Const, 0, ""}, + {"IEXTEN", Const, 0, ""}, + {"IFAN_ARRIVAL", Const, 1, ""}, + {"IFAN_DEPARTURE", Const, 1, ""}, + {"IFA_ADDRESS", Const, 0, ""}, + {"IFA_ANYCAST", Const, 0, ""}, + {"IFA_BROADCAST", Const, 0, ""}, + {"IFA_CACHEINFO", Const, 0, ""}, + {"IFA_F_DADFAILED", Const, 0, ""}, + {"IFA_F_DEPRECATED", Const, 0, ""}, + {"IFA_F_HOMEADDRESS", Const, 0, ""}, + {"IFA_F_NODAD", Const, 0, ""}, + {"IFA_F_OPTIMISTIC", Const, 0, ""}, + {"IFA_F_PERMANENT", Const, 0, ""}, + {"IFA_F_SECONDARY", Const, 0, ""}, + {"IFA_F_TEMPORARY", Const, 0, ""}, + {"IFA_F_TENTATIVE", Const, 0, ""}, + {"IFA_LABEL", Const, 0, ""}, + {"IFA_LOCAL", Const, 0, ""}, + {"IFA_MAX", Const, 0, ""}, + {"IFA_MULTICAST", Const, 0, ""}, + {"IFA_ROUTE", Const, 1, ""}, + {"IFA_UNSPEC", Const, 0, ""}, + {"IFF_ALLMULTI", Const, 0, ""}, + {"IFF_ALTPHYS", Const, 0, ""}, + {"IFF_AUTOMEDIA", Const, 0, ""}, + {"IFF_BROADCAST", Const, 0, ""}, + {"IFF_CANTCHANGE", Const, 0, ""}, + {"IFF_CANTCONFIG", Const, 1, ""}, + {"IFF_DEBUG", Const, 0, ""}, + {"IFF_DRV_OACTIVE", Const, 0, ""}, + {"IFF_DRV_RUNNING", Const, 0, ""}, + {"IFF_DYING", Const, 0, ""}, + {"IFF_DYNAMIC", Const, 0, ""}, + {"IFF_LINK0", Const, 0, ""}, + {"IFF_LINK1", Const, 0, ""}, + {"IFF_LINK2", Const, 0, ""}, + {"IFF_LOOPBACK", Const, 0, ""}, + {"IFF_MASTER", Const, 0, ""}, + {"IFF_MONITOR", Const, 0, ""}, + {"IFF_MULTICAST", Const, 0, ""}, + {"IFF_NOARP", Const, 0, ""}, + {"IFF_NOTRAILERS", Const, 0, ""}, + {"IFF_NO_PI", Const, 0, ""}, + {"IFF_OACTIVE", Const, 0, ""}, + {"IFF_ONE_QUEUE", Const, 0, ""}, + {"IFF_POINTOPOINT", Const, 0, ""}, + {"IFF_POINTTOPOINT", Const, 0, ""}, + {"IFF_PORTSEL", Const, 0, ""}, + {"IFF_PPROMISC", Const, 0, ""}, + {"IFF_PROMISC", Const, 0, ""}, + {"IFF_RENAMING", Const, 0, ""}, + {"IFF_RUNNING", Const, 0, ""}, + {"IFF_SIMPLEX", Const, 0, ""}, + {"IFF_SLAVE", Const, 0, ""}, + {"IFF_SMART", Const, 0, ""}, + {"IFF_STATICARP", Const, 0, ""}, + {"IFF_TAP", Const, 0, ""}, + {"IFF_TUN", Const, 0, ""}, + {"IFF_TUN_EXCL", Const, 0, ""}, + {"IFF_UP", Const, 0, ""}, + {"IFF_VNET_HDR", Const, 0, ""}, + {"IFLA_ADDRESS", Const, 0, ""}, + {"IFLA_BROADCAST", Const, 0, ""}, + {"IFLA_COST", Const, 0, ""}, + {"IFLA_IFALIAS", Const, 0, ""}, + {"IFLA_IFNAME", Const, 0, ""}, + {"IFLA_LINK", Const, 0, ""}, + {"IFLA_LINKINFO", Const, 0, ""}, + {"IFLA_LINKMODE", Const, 0, ""}, + {"IFLA_MAP", Const, 0, ""}, + {"IFLA_MASTER", Const, 0, ""}, + {"IFLA_MAX", Const, 0, ""}, + {"IFLA_MTU", Const, 0, ""}, + {"IFLA_NET_NS_PID", Const, 0, ""}, + {"IFLA_OPERSTATE", Const, 0, ""}, + {"IFLA_PRIORITY", Const, 0, ""}, + {"IFLA_PROTINFO", Const, 0, ""}, + {"IFLA_QDISC", Const, 0, ""}, + {"IFLA_STATS", Const, 0, ""}, + {"IFLA_TXQLEN", Const, 0, ""}, + {"IFLA_UNSPEC", Const, 0, ""}, + {"IFLA_WEIGHT", Const, 0, ""}, + {"IFLA_WIRELESS", Const, 0, ""}, + {"IFNAMSIZ", Const, 0, ""}, + {"IFT_1822", Const, 0, ""}, + {"IFT_A12MPPSWITCH", Const, 0, ""}, + {"IFT_AAL2", Const, 0, ""}, + {"IFT_AAL5", Const, 0, ""}, + {"IFT_ADSL", Const, 0, ""}, + {"IFT_AFLANE8023", Const, 0, ""}, + {"IFT_AFLANE8025", Const, 0, ""}, + {"IFT_ARAP", Const, 0, ""}, + {"IFT_ARCNET", Const, 0, ""}, + {"IFT_ARCNETPLUS", Const, 0, ""}, + {"IFT_ASYNC", Const, 0, ""}, + {"IFT_ATM", Const, 0, ""}, + {"IFT_ATMDXI", Const, 0, ""}, + {"IFT_ATMFUNI", Const, 0, ""}, + {"IFT_ATMIMA", Const, 0, ""}, + {"IFT_ATMLOGICAL", Const, 0, ""}, + {"IFT_ATMRADIO", Const, 0, ""}, + {"IFT_ATMSUBINTERFACE", Const, 0, ""}, + {"IFT_ATMVCIENDPT", Const, 0, ""}, + {"IFT_ATMVIRTUAL", Const, 0, ""}, + {"IFT_BGPPOLICYACCOUNTING", Const, 0, ""}, + {"IFT_BLUETOOTH", Const, 1, ""}, + {"IFT_BRIDGE", Const, 0, ""}, + {"IFT_BSC", Const, 0, ""}, + {"IFT_CARP", Const, 0, ""}, + {"IFT_CCTEMUL", Const, 0, ""}, + {"IFT_CELLULAR", Const, 0, ""}, + {"IFT_CEPT", Const, 0, ""}, + {"IFT_CES", Const, 0, ""}, + {"IFT_CHANNEL", Const, 0, ""}, + {"IFT_CNR", Const, 0, ""}, + {"IFT_COFFEE", Const, 0, ""}, + {"IFT_COMPOSITELINK", Const, 0, ""}, + {"IFT_DCN", Const, 0, ""}, + {"IFT_DIGITALPOWERLINE", Const, 0, ""}, + {"IFT_DIGITALWRAPPEROVERHEADCHANNEL", Const, 0, ""}, + {"IFT_DLSW", Const, 0, ""}, + {"IFT_DOCSCABLEDOWNSTREAM", Const, 0, ""}, + {"IFT_DOCSCABLEMACLAYER", Const, 0, ""}, + {"IFT_DOCSCABLEUPSTREAM", Const, 0, ""}, + {"IFT_DOCSCABLEUPSTREAMCHANNEL", Const, 1, ""}, + {"IFT_DS0", Const, 0, ""}, + {"IFT_DS0BUNDLE", Const, 0, ""}, + {"IFT_DS1FDL", Const, 0, ""}, + {"IFT_DS3", Const, 0, ""}, + {"IFT_DTM", Const, 0, ""}, + {"IFT_DUMMY", Const, 1, ""}, + {"IFT_DVBASILN", Const, 0, ""}, + {"IFT_DVBASIOUT", Const, 0, ""}, + {"IFT_DVBRCCDOWNSTREAM", Const, 0, ""}, + {"IFT_DVBRCCMACLAYER", Const, 0, ""}, + {"IFT_DVBRCCUPSTREAM", Const, 0, ""}, + {"IFT_ECONET", Const, 1, ""}, + {"IFT_ENC", Const, 0, ""}, + {"IFT_EON", Const, 0, ""}, + {"IFT_EPLRS", Const, 0, ""}, + {"IFT_ESCON", Const, 0, ""}, + {"IFT_ETHER", Const, 0, ""}, + {"IFT_FAITH", Const, 0, ""}, + {"IFT_FAST", Const, 0, ""}, + {"IFT_FASTETHER", Const, 0, ""}, + {"IFT_FASTETHERFX", Const, 0, ""}, + {"IFT_FDDI", Const, 0, ""}, + {"IFT_FIBRECHANNEL", Const, 0, ""}, + {"IFT_FRAMERELAYINTERCONNECT", Const, 0, ""}, + {"IFT_FRAMERELAYMPI", Const, 0, ""}, + {"IFT_FRDLCIENDPT", Const, 0, ""}, + {"IFT_FRELAY", Const, 0, ""}, + {"IFT_FRELAYDCE", Const, 0, ""}, + {"IFT_FRF16MFRBUNDLE", Const, 0, ""}, + {"IFT_FRFORWARD", Const, 0, ""}, + {"IFT_G703AT2MB", Const, 0, ""}, + {"IFT_G703AT64K", Const, 0, ""}, + {"IFT_GIF", Const, 0, ""}, + {"IFT_GIGABITETHERNET", Const, 0, ""}, + {"IFT_GR303IDT", Const, 0, ""}, + {"IFT_GR303RDT", Const, 0, ""}, + {"IFT_H323GATEKEEPER", Const, 0, ""}, + {"IFT_H323PROXY", Const, 0, ""}, + {"IFT_HDH1822", Const, 0, ""}, + {"IFT_HDLC", Const, 0, ""}, + {"IFT_HDSL2", Const, 0, ""}, + {"IFT_HIPERLAN2", Const, 0, ""}, + {"IFT_HIPPI", Const, 0, ""}, + {"IFT_HIPPIINTERFACE", Const, 0, ""}, + {"IFT_HOSTPAD", Const, 0, ""}, + {"IFT_HSSI", Const, 0, ""}, + {"IFT_HY", Const, 0, ""}, + {"IFT_IBM370PARCHAN", Const, 0, ""}, + {"IFT_IDSL", Const, 0, ""}, + {"IFT_IEEE1394", Const, 0, ""}, + {"IFT_IEEE80211", Const, 0, ""}, + {"IFT_IEEE80212", Const, 0, ""}, + {"IFT_IEEE8023ADLAG", Const, 0, ""}, + {"IFT_IFGSN", Const, 0, ""}, + {"IFT_IMT", Const, 0, ""}, + {"IFT_INFINIBAND", Const, 1, ""}, + {"IFT_INTERLEAVE", Const, 0, ""}, + {"IFT_IP", Const, 0, ""}, + {"IFT_IPFORWARD", Const, 0, ""}, + {"IFT_IPOVERATM", Const, 0, ""}, + {"IFT_IPOVERCDLC", Const, 0, ""}, + {"IFT_IPOVERCLAW", Const, 0, ""}, + {"IFT_IPSWITCH", Const, 0, ""}, + {"IFT_IPXIP", Const, 0, ""}, + {"IFT_ISDN", Const, 0, ""}, + {"IFT_ISDNBASIC", Const, 0, ""}, + {"IFT_ISDNPRIMARY", Const, 0, ""}, + {"IFT_ISDNS", Const, 0, ""}, + {"IFT_ISDNU", Const, 0, ""}, + {"IFT_ISO88022LLC", Const, 0, ""}, + {"IFT_ISO88023", Const, 0, ""}, + {"IFT_ISO88024", Const, 0, ""}, + {"IFT_ISO88025", Const, 0, ""}, + {"IFT_ISO88025CRFPINT", Const, 0, ""}, + {"IFT_ISO88025DTR", Const, 0, ""}, + {"IFT_ISO88025FIBER", Const, 0, ""}, + {"IFT_ISO88026", Const, 0, ""}, + {"IFT_ISUP", Const, 0, ""}, + {"IFT_L2VLAN", Const, 0, ""}, + {"IFT_L3IPVLAN", Const, 0, ""}, + {"IFT_L3IPXVLAN", Const, 0, ""}, + {"IFT_LAPB", Const, 0, ""}, + {"IFT_LAPD", Const, 0, ""}, + {"IFT_LAPF", Const, 0, ""}, + {"IFT_LINEGROUP", Const, 1, ""}, + {"IFT_LOCALTALK", Const, 0, ""}, + {"IFT_LOOP", Const, 0, ""}, + {"IFT_MEDIAMAILOVERIP", Const, 0, ""}, + {"IFT_MFSIGLINK", Const, 0, ""}, + {"IFT_MIOX25", Const, 0, ""}, + {"IFT_MODEM", Const, 0, ""}, + {"IFT_MPC", Const, 0, ""}, + {"IFT_MPLS", Const, 0, ""}, + {"IFT_MPLSTUNNEL", Const, 0, ""}, + {"IFT_MSDSL", Const, 0, ""}, + {"IFT_MVL", Const, 0, ""}, + {"IFT_MYRINET", Const, 0, ""}, + {"IFT_NFAS", Const, 0, ""}, + {"IFT_NSIP", Const, 0, ""}, + {"IFT_OPTICALCHANNEL", Const, 0, ""}, + {"IFT_OPTICALTRANSPORT", Const, 0, ""}, + {"IFT_OTHER", Const, 0, ""}, + {"IFT_P10", Const, 0, ""}, + {"IFT_P80", Const, 0, ""}, + {"IFT_PARA", Const, 0, ""}, + {"IFT_PDP", Const, 0, ""}, + {"IFT_PFLOG", Const, 0, ""}, + {"IFT_PFLOW", Const, 1, ""}, + {"IFT_PFSYNC", Const, 0, ""}, + {"IFT_PLC", Const, 0, ""}, + {"IFT_PON155", Const, 1, ""}, + {"IFT_PON622", Const, 1, ""}, + {"IFT_POS", Const, 0, ""}, + {"IFT_PPP", Const, 0, ""}, + {"IFT_PPPMULTILINKBUNDLE", Const, 0, ""}, + {"IFT_PROPATM", Const, 1, ""}, + {"IFT_PROPBWAP2MP", Const, 0, ""}, + {"IFT_PROPCNLS", Const, 0, ""}, + {"IFT_PROPDOCSWIRELESSDOWNSTREAM", Const, 0, ""}, + {"IFT_PROPDOCSWIRELESSMACLAYER", Const, 0, ""}, + {"IFT_PROPDOCSWIRELESSUPSTREAM", Const, 0, ""}, + {"IFT_PROPMUX", Const, 0, ""}, + {"IFT_PROPVIRTUAL", Const, 0, ""}, + {"IFT_PROPWIRELESSP2P", Const, 0, ""}, + {"IFT_PTPSERIAL", Const, 0, ""}, + {"IFT_PVC", Const, 0, ""}, + {"IFT_Q2931", Const, 1, ""}, + {"IFT_QLLC", Const, 0, ""}, + {"IFT_RADIOMAC", Const, 0, ""}, + {"IFT_RADSL", Const, 0, ""}, + {"IFT_REACHDSL", Const, 0, ""}, + {"IFT_RFC1483", Const, 0, ""}, + {"IFT_RS232", Const, 0, ""}, + {"IFT_RSRB", Const, 0, ""}, + {"IFT_SDLC", Const, 0, ""}, + {"IFT_SDSL", Const, 0, ""}, + {"IFT_SHDSL", Const, 0, ""}, + {"IFT_SIP", Const, 0, ""}, + {"IFT_SIPSIG", Const, 1, ""}, + {"IFT_SIPTG", Const, 1, ""}, + {"IFT_SLIP", Const, 0, ""}, + {"IFT_SMDSDXI", Const, 0, ""}, + {"IFT_SMDSICIP", Const, 0, ""}, + {"IFT_SONET", Const, 0, ""}, + {"IFT_SONETOVERHEADCHANNEL", Const, 0, ""}, + {"IFT_SONETPATH", Const, 0, ""}, + {"IFT_SONETVT", Const, 0, ""}, + {"IFT_SRP", Const, 0, ""}, + {"IFT_SS7SIGLINK", Const, 0, ""}, + {"IFT_STACKTOSTACK", Const, 0, ""}, + {"IFT_STARLAN", Const, 0, ""}, + {"IFT_STF", Const, 0, ""}, + {"IFT_T1", Const, 0, ""}, + {"IFT_TDLC", Const, 0, ""}, + {"IFT_TELINK", Const, 1, ""}, + {"IFT_TERMPAD", Const, 0, ""}, + {"IFT_TR008", Const, 0, ""}, + {"IFT_TRANSPHDLC", Const, 0, ""}, + {"IFT_TUNNEL", Const, 0, ""}, + {"IFT_ULTRA", Const, 0, ""}, + {"IFT_USB", Const, 0, ""}, + {"IFT_V11", Const, 0, ""}, + {"IFT_V35", Const, 0, ""}, + {"IFT_V36", Const, 0, ""}, + {"IFT_V37", Const, 0, ""}, + {"IFT_VDSL", Const, 0, ""}, + {"IFT_VIRTUALIPADDRESS", Const, 0, ""}, + {"IFT_VIRTUALTG", Const, 1, ""}, + {"IFT_VOICEDID", Const, 1, ""}, + {"IFT_VOICEEM", Const, 0, ""}, + {"IFT_VOICEEMFGD", Const, 1, ""}, + {"IFT_VOICEENCAP", Const, 0, ""}, + {"IFT_VOICEFGDEANA", Const, 1, ""}, + {"IFT_VOICEFXO", Const, 0, ""}, + {"IFT_VOICEFXS", Const, 0, ""}, + {"IFT_VOICEOVERATM", Const, 0, ""}, + {"IFT_VOICEOVERCABLE", Const, 1, ""}, + {"IFT_VOICEOVERFRAMERELAY", Const, 0, ""}, + {"IFT_VOICEOVERIP", Const, 0, ""}, + {"IFT_X213", Const, 0, ""}, + {"IFT_X25", Const, 0, ""}, + {"IFT_X25DDN", Const, 0, ""}, + {"IFT_X25HUNTGROUP", Const, 0, ""}, + {"IFT_X25MLP", Const, 0, ""}, + {"IFT_X25PLE", Const, 0, ""}, + {"IFT_XETHER", Const, 0, ""}, + {"IGNBRK", Const, 0, ""}, + {"IGNCR", Const, 0, ""}, + {"IGNORE", Const, 0, ""}, + {"IGNPAR", Const, 0, ""}, + {"IMAXBEL", Const, 0, ""}, + {"INFINITE", Const, 0, ""}, + {"INLCR", Const, 0, ""}, + {"INPCK", Const, 0, ""}, + {"INVALID_FILE_ATTRIBUTES", Const, 0, ""}, + {"IN_ACCESS", Const, 0, ""}, + {"IN_ALL_EVENTS", Const, 0, ""}, + {"IN_ATTRIB", Const, 0, ""}, + {"IN_CLASSA_HOST", Const, 0, ""}, + {"IN_CLASSA_MAX", Const, 0, ""}, + {"IN_CLASSA_NET", Const, 0, ""}, + {"IN_CLASSA_NSHIFT", Const, 0, ""}, + {"IN_CLASSB_HOST", Const, 0, ""}, + {"IN_CLASSB_MAX", Const, 0, ""}, + {"IN_CLASSB_NET", Const, 0, ""}, + {"IN_CLASSB_NSHIFT", Const, 0, ""}, + {"IN_CLASSC_HOST", Const, 0, ""}, + {"IN_CLASSC_NET", Const, 0, ""}, + {"IN_CLASSC_NSHIFT", Const, 0, ""}, + {"IN_CLASSD_HOST", Const, 0, ""}, + {"IN_CLASSD_NET", Const, 0, ""}, + {"IN_CLASSD_NSHIFT", Const, 0, ""}, + {"IN_CLOEXEC", Const, 0, ""}, + {"IN_CLOSE", Const, 0, ""}, + {"IN_CLOSE_NOWRITE", Const, 0, ""}, + {"IN_CLOSE_WRITE", Const, 0, ""}, + {"IN_CREATE", Const, 0, ""}, + {"IN_DELETE", Const, 0, ""}, + {"IN_DELETE_SELF", Const, 0, ""}, + {"IN_DONT_FOLLOW", Const, 0, ""}, + {"IN_EXCL_UNLINK", Const, 0, ""}, + {"IN_IGNORED", Const, 0, ""}, + {"IN_ISDIR", Const, 0, ""}, + {"IN_LINKLOCALNETNUM", Const, 0, ""}, + {"IN_LOOPBACKNET", Const, 0, ""}, + {"IN_MASK_ADD", Const, 0, ""}, + {"IN_MODIFY", Const, 0, ""}, + {"IN_MOVE", Const, 0, ""}, + {"IN_MOVED_FROM", Const, 0, ""}, + {"IN_MOVED_TO", Const, 0, ""}, + {"IN_MOVE_SELF", Const, 0, ""}, + {"IN_NONBLOCK", Const, 0, ""}, + {"IN_ONESHOT", Const, 0, ""}, + {"IN_ONLYDIR", Const, 0, ""}, + {"IN_OPEN", Const, 0, ""}, + {"IN_Q_OVERFLOW", Const, 0, ""}, + {"IN_RFC3021_HOST", Const, 1, ""}, + {"IN_RFC3021_MASK", Const, 1, ""}, + {"IN_RFC3021_NET", Const, 1, ""}, + {"IN_RFC3021_NSHIFT", Const, 1, ""}, + {"IN_UNMOUNT", Const, 0, ""}, + {"IOC_IN", Const, 1, ""}, + {"IOC_INOUT", Const, 1, ""}, + {"IOC_OUT", Const, 1, ""}, + {"IOC_VENDOR", Const, 3, ""}, + {"IOC_WS2", Const, 1, ""}, + {"IO_REPARSE_TAG_SYMLINK", Const, 4, ""}, + {"IPMreq", Type, 0, ""}, + {"IPMreq.Interface", Field, 0, ""}, + {"IPMreq.Multiaddr", Field, 0, ""}, + {"IPMreqn", Type, 0, ""}, + {"IPMreqn.Address", Field, 0, ""}, + {"IPMreqn.Ifindex", Field, 0, ""}, + {"IPMreqn.Multiaddr", Field, 0, ""}, + {"IPPROTO_3PC", Const, 0, ""}, + {"IPPROTO_ADFS", Const, 0, ""}, + {"IPPROTO_AH", Const, 0, ""}, + {"IPPROTO_AHIP", Const, 0, ""}, + {"IPPROTO_APES", Const, 0, ""}, + {"IPPROTO_ARGUS", Const, 0, ""}, + {"IPPROTO_AX25", Const, 0, ""}, + {"IPPROTO_BHA", Const, 0, ""}, + {"IPPROTO_BLT", Const, 0, ""}, + {"IPPROTO_BRSATMON", Const, 0, ""}, + {"IPPROTO_CARP", Const, 0, ""}, + {"IPPROTO_CFTP", Const, 0, ""}, + {"IPPROTO_CHAOS", Const, 0, ""}, + {"IPPROTO_CMTP", Const, 0, ""}, + {"IPPROTO_COMP", Const, 0, ""}, + {"IPPROTO_CPHB", Const, 0, ""}, + {"IPPROTO_CPNX", Const, 0, ""}, + {"IPPROTO_DCCP", Const, 0, ""}, + {"IPPROTO_DDP", Const, 0, ""}, + {"IPPROTO_DGP", Const, 0, ""}, + {"IPPROTO_DIVERT", Const, 0, ""}, + {"IPPROTO_DIVERT_INIT", Const, 3, ""}, + {"IPPROTO_DIVERT_RESP", Const, 3, ""}, + {"IPPROTO_DONE", Const, 0, ""}, + {"IPPROTO_DSTOPTS", Const, 0, ""}, + {"IPPROTO_EGP", Const, 0, ""}, + {"IPPROTO_EMCON", Const, 0, ""}, + {"IPPROTO_ENCAP", Const, 0, ""}, + {"IPPROTO_EON", Const, 0, ""}, + {"IPPROTO_ESP", Const, 0, ""}, + {"IPPROTO_ETHERIP", Const, 0, ""}, + {"IPPROTO_FRAGMENT", Const, 0, ""}, + {"IPPROTO_GGP", Const, 0, ""}, + {"IPPROTO_GMTP", Const, 0, ""}, + {"IPPROTO_GRE", Const, 0, ""}, + {"IPPROTO_HELLO", Const, 0, ""}, + {"IPPROTO_HMP", Const, 0, ""}, + {"IPPROTO_HOPOPTS", Const, 0, ""}, + {"IPPROTO_ICMP", Const, 0, ""}, + {"IPPROTO_ICMPV6", Const, 0, ""}, + {"IPPROTO_IDP", Const, 0, ""}, + {"IPPROTO_IDPR", Const, 0, ""}, + {"IPPROTO_IDRP", Const, 0, ""}, + {"IPPROTO_IGMP", Const, 0, ""}, + {"IPPROTO_IGP", Const, 0, ""}, + {"IPPROTO_IGRP", Const, 0, ""}, + {"IPPROTO_IL", Const, 0, ""}, + {"IPPROTO_INLSP", Const, 0, ""}, + {"IPPROTO_INP", Const, 0, ""}, + {"IPPROTO_IP", Const, 0, ""}, + {"IPPROTO_IPCOMP", Const, 0, ""}, + {"IPPROTO_IPCV", Const, 0, ""}, + {"IPPROTO_IPEIP", Const, 0, ""}, + {"IPPROTO_IPIP", Const, 0, ""}, + {"IPPROTO_IPPC", Const, 0, ""}, + {"IPPROTO_IPV4", Const, 0, ""}, + {"IPPROTO_IPV6", Const, 0, ""}, + {"IPPROTO_IPV6_ICMP", Const, 1, ""}, + {"IPPROTO_IRTP", Const, 0, ""}, + {"IPPROTO_KRYPTOLAN", Const, 0, ""}, + {"IPPROTO_LARP", Const, 0, ""}, + {"IPPROTO_LEAF1", Const, 0, ""}, + {"IPPROTO_LEAF2", Const, 0, ""}, + {"IPPROTO_MAX", Const, 0, ""}, + {"IPPROTO_MAXID", Const, 0, ""}, + {"IPPROTO_MEAS", Const, 0, ""}, + {"IPPROTO_MH", Const, 1, ""}, + {"IPPROTO_MHRP", Const, 0, ""}, + {"IPPROTO_MICP", Const, 0, ""}, + {"IPPROTO_MOBILE", Const, 0, ""}, + {"IPPROTO_MPLS", Const, 1, ""}, + {"IPPROTO_MTP", Const, 0, ""}, + {"IPPROTO_MUX", Const, 0, ""}, + {"IPPROTO_ND", Const, 0, ""}, + {"IPPROTO_NHRP", Const, 0, ""}, + {"IPPROTO_NONE", Const, 0, ""}, + {"IPPROTO_NSP", Const, 0, ""}, + {"IPPROTO_NVPII", Const, 0, ""}, + {"IPPROTO_OLD_DIVERT", Const, 0, ""}, + {"IPPROTO_OSPFIGP", Const, 0, ""}, + {"IPPROTO_PFSYNC", Const, 0, ""}, + {"IPPROTO_PGM", Const, 0, ""}, + {"IPPROTO_PIGP", Const, 0, ""}, + {"IPPROTO_PIM", Const, 0, ""}, + {"IPPROTO_PRM", Const, 0, ""}, + {"IPPROTO_PUP", Const, 0, ""}, + {"IPPROTO_PVP", Const, 0, ""}, + {"IPPROTO_RAW", Const, 0, ""}, + {"IPPROTO_RCCMON", Const, 0, ""}, + {"IPPROTO_RDP", Const, 0, ""}, + {"IPPROTO_ROUTING", Const, 0, ""}, + {"IPPROTO_RSVP", Const, 0, ""}, + {"IPPROTO_RVD", Const, 0, ""}, + {"IPPROTO_SATEXPAK", Const, 0, ""}, + {"IPPROTO_SATMON", Const, 0, ""}, + {"IPPROTO_SCCSP", Const, 0, ""}, + {"IPPROTO_SCTP", Const, 0, ""}, + {"IPPROTO_SDRP", Const, 0, ""}, + {"IPPROTO_SEND", Const, 1, ""}, + {"IPPROTO_SEP", Const, 0, ""}, + {"IPPROTO_SKIP", Const, 0, ""}, + {"IPPROTO_SPACER", Const, 0, ""}, + {"IPPROTO_SRPC", Const, 0, ""}, + {"IPPROTO_ST", Const, 0, ""}, + {"IPPROTO_SVMTP", Const, 0, ""}, + {"IPPROTO_SWIPE", Const, 0, ""}, + {"IPPROTO_TCF", Const, 0, ""}, + {"IPPROTO_TCP", Const, 0, ""}, + {"IPPROTO_TLSP", Const, 0, ""}, + {"IPPROTO_TP", Const, 0, ""}, + {"IPPROTO_TPXX", Const, 0, ""}, + {"IPPROTO_TRUNK1", Const, 0, ""}, + {"IPPROTO_TRUNK2", Const, 0, ""}, + {"IPPROTO_TTP", Const, 0, ""}, + {"IPPROTO_UDP", Const, 0, ""}, + {"IPPROTO_UDPLITE", Const, 0, ""}, + {"IPPROTO_VINES", Const, 0, ""}, + {"IPPROTO_VISA", Const, 0, ""}, + {"IPPROTO_VMTP", Const, 0, ""}, + {"IPPROTO_VRRP", Const, 1, ""}, + {"IPPROTO_WBEXPAK", Const, 0, ""}, + {"IPPROTO_WBMON", Const, 0, ""}, + {"IPPROTO_WSN", Const, 0, ""}, + {"IPPROTO_XNET", Const, 0, ""}, + {"IPPROTO_XTP", Const, 0, ""}, + {"IPV6_2292DSTOPTS", Const, 0, ""}, + {"IPV6_2292HOPLIMIT", Const, 0, ""}, + {"IPV6_2292HOPOPTS", Const, 0, ""}, + {"IPV6_2292NEXTHOP", Const, 0, ""}, + {"IPV6_2292PKTINFO", Const, 0, ""}, + {"IPV6_2292PKTOPTIONS", Const, 0, ""}, + {"IPV6_2292RTHDR", Const, 0, ""}, + {"IPV6_ADDRFORM", Const, 0, ""}, + {"IPV6_ADD_MEMBERSHIP", Const, 0, ""}, + {"IPV6_AUTHHDR", Const, 0, ""}, + {"IPV6_AUTH_LEVEL", Const, 1, ""}, + {"IPV6_AUTOFLOWLABEL", Const, 0, ""}, + {"IPV6_BINDANY", Const, 0, ""}, + {"IPV6_BINDV6ONLY", Const, 0, ""}, + {"IPV6_BOUND_IF", Const, 0, ""}, + {"IPV6_CHECKSUM", Const, 0, ""}, + {"IPV6_DEFAULT_MULTICAST_HOPS", Const, 0, ""}, + {"IPV6_DEFAULT_MULTICAST_LOOP", Const, 0, ""}, + {"IPV6_DEFHLIM", Const, 0, ""}, + {"IPV6_DONTFRAG", Const, 0, ""}, + {"IPV6_DROP_MEMBERSHIP", Const, 0, ""}, + {"IPV6_DSTOPTS", Const, 0, ""}, + {"IPV6_ESP_NETWORK_LEVEL", Const, 1, ""}, + {"IPV6_ESP_TRANS_LEVEL", Const, 1, ""}, + {"IPV6_FAITH", Const, 0, ""}, + {"IPV6_FLOWINFO_MASK", Const, 0, ""}, + {"IPV6_FLOWLABEL_MASK", Const, 0, ""}, + {"IPV6_FRAGTTL", Const, 0, ""}, + {"IPV6_FW_ADD", Const, 0, ""}, + {"IPV6_FW_DEL", Const, 0, ""}, + {"IPV6_FW_FLUSH", Const, 0, ""}, + {"IPV6_FW_GET", Const, 0, ""}, + {"IPV6_FW_ZERO", Const, 0, ""}, + {"IPV6_HLIMDEC", Const, 0, ""}, + {"IPV6_HOPLIMIT", Const, 0, ""}, + {"IPV6_HOPOPTS", Const, 0, ""}, + {"IPV6_IPCOMP_LEVEL", Const, 1, ""}, + {"IPV6_IPSEC_POLICY", Const, 0, ""}, + {"IPV6_JOIN_ANYCAST", Const, 0, ""}, + {"IPV6_JOIN_GROUP", Const, 0, ""}, + {"IPV6_LEAVE_ANYCAST", Const, 0, ""}, + {"IPV6_LEAVE_GROUP", Const, 0, ""}, + {"IPV6_MAXHLIM", Const, 0, ""}, + {"IPV6_MAXOPTHDR", Const, 0, ""}, + {"IPV6_MAXPACKET", Const, 0, ""}, + {"IPV6_MAX_GROUP_SRC_FILTER", Const, 0, ""}, + {"IPV6_MAX_MEMBERSHIPS", Const, 0, ""}, + {"IPV6_MAX_SOCK_SRC_FILTER", Const, 0, ""}, + {"IPV6_MIN_MEMBERSHIPS", Const, 0, ""}, + {"IPV6_MMTU", Const, 0, ""}, + {"IPV6_MSFILTER", Const, 0, ""}, + {"IPV6_MTU", Const, 0, ""}, + {"IPV6_MTU_DISCOVER", Const, 0, ""}, + {"IPV6_MULTICAST_HOPS", Const, 0, ""}, + {"IPV6_MULTICAST_IF", Const, 0, ""}, + {"IPV6_MULTICAST_LOOP", Const, 0, ""}, + {"IPV6_NEXTHOP", Const, 0, ""}, + {"IPV6_OPTIONS", Const, 1, ""}, + {"IPV6_PATHMTU", Const, 0, ""}, + {"IPV6_PIPEX", Const, 1, ""}, + {"IPV6_PKTINFO", Const, 0, ""}, + {"IPV6_PMTUDISC_DO", Const, 0, ""}, + {"IPV6_PMTUDISC_DONT", Const, 0, ""}, + {"IPV6_PMTUDISC_PROBE", Const, 0, ""}, + {"IPV6_PMTUDISC_WANT", Const, 0, ""}, + {"IPV6_PORTRANGE", Const, 0, ""}, + {"IPV6_PORTRANGE_DEFAULT", Const, 0, ""}, + {"IPV6_PORTRANGE_HIGH", Const, 0, ""}, + {"IPV6_PORTRANGE_LOW", Const, 0, ""}, + {"IPV6_PREFER_TEMPADDR", Const, 0, ""}, + {"IPV6_RECVDSTOPTS", Const, 0, ""}, + {"IPV6_RECVDSTPORT", Const, 3, ""}, + {"IPV6_RECVERR", Const, 0, ""}, + {"IPV6_RECVHOPLIMIT", Const, 0, ""}, + {"IPV6_RECVHOPOPTS", Const, 0, ""}, + {"IPV6_RECVPATHMTU", Const, 0, ""}, + {"IPV6_RECVPKTINFO", Const, 0, ""}, + {"IPV6_RECVRTHDR", Const, 0, ""}, + {"IPV6_RECVTCLASS", Const, 0, ""}, + {"IPV6_ROUTER_ALERT", Const, 0, ""}, + {"IPV6_RTABLE", Const, 1, ""}, + {"IPV6_RTHDR", Const, 0, ""}, + {"IPV6_RTHDRDSTOPTS", Const, 0, ""}, + {"IPV6_RTHDR_LOOSE", Const, 0, ""}, + {"IPV6_RTHDR_STRICT", Const, 0, ""}, + {"IPV6_RTHDR_TYPE_0", Const, 0, ""}, + {"IPV6_RXDSTOPTS", Const, 0, ""}, + {"IPV6_RXHOPOPTS", Const, 0, ""}, + {"IPV6_SOCKOPT_RESERVED1", Const, 0, ""}, + {"IPV6_TCLASS", Const, 0, ""}, + {"IPV6_UNICAST_HOPS", Const, 0, ""}, + {"IPV6_USE_MIN_MTU", Const, 0, ""}, + {"IPV6_V6ONLY", Const, 0, ""}, + {"IPV6_VERSION", Const, 0, ""}, + {"IPV6_VERSION_MASK", Const, 0, ""}, + {"IPV6_XFRM_POLICY", Const, 0, ""}, + {"IP_ADD_MEMBERSHIP", Const, 0, ""}, + {"IP_ADD_SOURCE_MEMBERSHIP", Const, 0, ""}, + {"IP_AUTH_LEVEL", Const, 1, ""}, + {"IP_BINDANY", Const, 0, ""}, + {"IP_BLOCK_SOURCE", Const, 0, ""}, + {"IP_BOUND_IF", Const, 0, ""}, + {"IP_DEFAULT_MULTICAST_LOOP", Const, 0, ""}, + {"IP_DEFAULT_MULTICAST_TTL", Const, 0, ""}, + {"IP_DF", Const, 0, ""}, + {"IP_DIVERTFL", Const, 3, ""}, + {"IP_DONTFRAG", Const, 0, ""}, + {"IP_DROP_MEMBERSHIP", Const, 0, ""}, + {"IP_DROP_SOURCE_MEMBERSHIP", Const, 0, ""}, + {"IP_DUMMYNET3", Const, 0, ""}, + {"IP_DUMMYNET_CONFIGURE", Const, 0, ""}, + {"IP_DUMMYNET_DEL", Const, 0, ""}, + {"IP_DUMMYNET_FLUSH", Const, 0, ""}, + {"IP_DUMMYNET_GET", Const, 0, ""}, + {"IP_EF", Const, 1, ""}, + {"IP_ERRORMTU", Const, 1, ""}, + {"IP_ESP_NETWORK_LEVEL", Const, 1, ""}, + {"IP_ESP_TRANS_LEVEL", Const, 1, ""}, + {"IP_FAITH", Const, 0, ""}, + {"IP_FREEBIND", Const, 0, ""}, + {"IP_FW3", Const, 0, ""}, + {"IP_FW_ADD", Const, 0, ""}, + {"IP_FW_DEL", Const, 0, ""}, + {"IP_FW_FLUSH", Const, 0, ""}, + {"IP_FW_GET", Const, 0, ""}, + {"IP_FW_NAT_CFG", Const, 0, ""}, + {"IP_FW_NAT_DEL", Const, 0, ""}, + {"IP_FW_NAT_GET_CONFIG", Const, 0, ""}, + {"IP_FW_NAT_GET_LOG", Const, 0, ""}, + {"IP_FW_RESETLOG", Const, 0, ""}, + {"IP_FW_TABLE_ADD", Const, 0, ""}, + {"IP_FW_TABLE_DEL", Const, 0, ""}, + {"IP_FW_TABLE_FLUSH", Const, 0, ""}, + {"IP_FW_TABLE_GETSIZE", Const, 0, ""}, + {"IP_FW_TABLE_LIST", Const, 0, ""}, + {"IP_FW_ZERO", Const, 0, ""}, + {"IP_HDRINCL", Const, 0, ""}, + {"IP_IPCOMP_LEVEL", Const, 1, ""}, + {"IP_IPSECFLOWINFO", Const, 1, ""}, + {"IP_IPSEC_LOCAL_AUTH", Const, 1, ""}, + {"IP_IPSEC_LOCAL_CRED", Const, 1, ""}, + {"IP_IPSEC_LOCAL_ID", Const, 1, ""}, + {"IP_IPSEC_POLICY", Const, 0, ""}, + {"IP_IPSEC_REMOTE_AUTH", Const, 1, ""}, + {"IP_IPSEC_REMOTE_CRED", Const, 1, ""}, + {"IP_IPSEC_REMOTE_ID", Const, 1, ""}, + {"IP_MAXPACKET", Const, 0, ""}, + {"IP_MAX_GROUP_SRC_FILTER", Const, 0, ""}, + {"IP_MAX_MEMBERSHIPS", Const, 0, ""}, + {"IP_MAX_SOCK_MUTE_FILTER", Const, 0, ""}, + {"IP_MAX_SOCK_SRC_FILTER", Const, 0, ""}, + {"IP_MAX_SOURCE_FILTER", Const, 0, ""}, + {"IP_MF", Const, 0, ""}, + {"IP_MINFRAGSIZE", Const, 1, ""}, + {"IP_MINTTL", Const, 0, ""}, + {"IP_MIN_MEMBERSHIPS", Const, 0, ""}, + {"IP_MSFILTER", Const, 0, ""}, + {"IP_MSS", Const, 0, ""}, + {"IP_MTU", Const, 0, ""}, + {"IP_MTU_DISCOVER", Const, 0, ""}, + {"IP_MULTICAST_IF", Const, 0, ""}, + {"IP_MULTICAST_IFINDEX", Const, 0, ""}, + {"IP_MULTICAST_LOOP", Const, 0, ""}, + {"IP_MULTICAST_TTL", Const, 0, ""}, + {"IP_MULTICAST_VIF", Const, 0, ""}, + {"IP_NAT__XXX", Const, 0, ""}, + {"IP_OFFMASK", Const, 0, ""}, + {"IP_OLD_FW_ADD", Const, 0, ""}, + {"IP_OLD_FW_DEL", Const, 0, ""}, + {"IP_OLD_FW_FLUSH", Const, 0, ""}, + {"IP_OLD_FW_GET", Const, 0, ""}, + {"IP_OLD_FW_RESETLOG", Const, 0, ""}, + {"IP_OLD_FW_ZERO", Const, 0, ""}, + {"IP_ONESBCAST", Const, 0, ""}, + {"IP_OPTIONS", Const, 0, ""}, + {"IP_ORIGDSTADDR", Const, 0, ""}, + {"IP_PASSSEC", Const, 0, ""}, + {"IP_PIPEX", Const, 1, ""}, + {"IP_PKTINFO", Const, 0, ""}, + {"IP_PKTOPTIONS", Const, 0, ""}, + {"IP_PMTUDISC", Const, 0, ""}, + {"IP_PMTUDISC_DO", Const, 0, ""}, + {"IP_PMTUDISC_DONT", Const, 0, ""}, + {"IP_PMTUDISC_PROBE", Const, 0, ""}, + {"IP_PMTUDISC_WANT", Const, 0, ""}, + {"IP_PORTRANGE", Const, 0, ""}, + {"IP_PORTRANGE_DEFAULT", Const, 0, ""}, + {"IP_PORTRANGE_HIGH", Const, 0, ""}, + {"IP_PORTRANGE_LOW", Const, 0, ""}, + {"IP_RECVDSTADDR", Const, 0, ""}, + {"IP_RECVDSTPORT", Const, 1, ""}, + {"IP_RECVERR", Const, 0, ""}, + {"IP_RECVIF", Const, 0, ""}, + {"IP_RECVOPTS", Const, 0, ""}, + {"IP_RECVORIGDSTADDR", Const, 0, ""}, + {"IP_RECVPKTINFO", Const, 0, ""}, + {"IP_RECVRETOPTS", Const, 0, ""}, + {"IP_RECVRTABLE", Const, 1, ""}, + {"IP_RECVTOS", Const, 0, ""}, + {"IP_RECVTTL", Const, 0, ""}, + {"IP_RETOPTS", Const, 0, ""}, + {"IP_RF", Const, 0, ""}, + {"IP_ROUTER_ALERT", Const, 0, ""}, + {"IP_RSVP_OFF", Const, 0, ""}, + {"IP_RSVP_ON", Const, 0, ""}, + {"IP_RSVP_VIF_OFF", Const, 0, ""}, + {"IP_RSVP_VIF_ON", Const, 0, ""}, + {"IP_RTABLE", Const, 1, ""}, + {"IP_SENDSRCADDR", Const, 0, ""}, + {"IP_STRIPHDR", Const, 0, ""}, + {"IP_TOS", Const, 0, ""}, + {"IP_TRAFFIC_MGT_BACKGROUND", Const, 0, ""}, + {"IP_TRANSPARENT", Const, 0, ""}, + {"IP_TTL", Const, 0, ""}, + {"IP_UNBLOCK_SOURCE", Const, 0, ""}, + {"IP_XFRM_POLICY", Const, 0, ""}, + {"IPv6MTUInfo", Type, 2, ""}, + {"IPv6MTUInfo.Addr", Field, 2, ""}, + {"IPv6MTUInfo.Mtu", Field, 2, ""}, + {"IPv6Mreq", Type, 0, ""}, + {"IPv6Mreq.Interface", Field, 0, ""}, + {"IPv6Mreq.Multiaddr", Field, 0, ""}, + {"ISIG", Const, 0, ""}, + {"ISTRIP", Const, 0, ""}, + {"IUCLC", Const, 0, ""}, + {"IUTF8", Const, 0, ""}, + {"IXANY", Const, 0, ""}, + {"IXOFF", Const, 0, ""}, + {"IXON", Const, 0, ""}, + {"IfAddrmsg", Type, 0, ""}, + {"IfAddrmsg.Family", Field, 0, ""}, + {"IfAddrmsg.Flags", Field, 0, ""}, + {"IfAddrmsg.Index", Field, 0, ""}, + {"IfAddrmsg.Prefixlen", Field, 0, ""}, + {"IfAddrmsg.Scope", Field, 0, ""}, + {"IfAnnounceMsghdr", Type, 1, ""}, + {"IfAnnounceMsghdr.Hdrlen", Field, 2, ""}, + {"IfAnnounceMsghdr.Index", Field, 1, ""}, + {"IfAnnounceMsghdr.Msglen", Field, 1, ""}, + {"IfAnnounceMsghdr.Name", Field, 1, ""}, + {"IfAnnounceMsghdr.Type", Field, 1, ""}, + {"IfAnnounceMsghdr.Version", Field, 1, ""}, + {"IfAnnounceMsghdr.What", Field, 1, ""}, + {"IfData", Type, 0, ""}, + {"IfData.Addrlen", Field, 0, ""}, + {"IfData.Baudrate", Field, 0, ""}, + {"IfData.Capabilities", Field, 2, ""}, + {"IfData.Collisions", Field, 0, ""}, + {"IfData.Datalen", Field, 0, ""}, + {"IfData.Epoch", Field, 0, ""}, + {"IfData.Hdrlen", Field, 0, ""}, + {"IfData.Hwassist", Field, 0, ""}, + {"IfData.Ibytes", Field, 0, ""}, + {"IfData.Ierrors", Field, 0, ""}, + {"IfData.Imcasts", Field, 0, ""}, + {"IfData.Ipackets", Field, 0, ""}, + {"IfData.Iqdrops", Field, 0, ""}, + {"IfData.Lastchange", Field, 0, ""}, + {"IfData.Link_state", Field, 0, ""}, + {"IfData.Mclpool", Field, 2, ""}, + {"IfData.Metric", Field, 0, ""}, + {"IfData.Mtu", Field, 0, ""}, + {"IfData.Noproto", Field, 0, ""}, + {"IfData.Obytes", Field, 0, ""}, + {"IfData.Oerrors", Field, 0, ""}, + {"IfData.Omcasts", Field, 0, ""}, + {"IfData.Opackets", Field, 0, ""}, + {"IfData.Pad", Field, 2, ""}, + {"IfData.Pad_cgo_0", Field, 2, ""}, + {"IfData.Pad_cgo_1", Field, 2, ""}, + {"IfData.Physical", Field, 0, ""}, + {"IfData.Recvquota", Field, 0, ""}, + {"IfData.Recvtiming", Field, 0, ""}, + {"IfData.Reserved1", Field, 0, ""}, + {"IfData.Reserved2", Field, 0, ""}, + {"IfData.Spare_char1", Field, 0, ""}, + {"IfData.Spare_char2", Field, 0, ""}, + {"IfData.Type", Field, 0, ""}, + {"IfData.Typelen", Field, 0, ""}, + {"IfData.Unused1", Field, 0, ""}, + {"IfData.Unused2", Field, 0, ""}, + {"IfData.Xmitquota", Field, 0, ""}, + {"IfData.Xmittiming", Field, 0, ""}, + {"IfInfomsg", Type, 0, ""}, + {"IfInfomsg.Change", Field, 0, ""}, + {"IfInfomsg.Family", Field, 0, ""}, + {"IfInfomsg.Flags", Field, 0, ""}, + {"IfInfomsg.Index", Field, 0, ""}, + {"IfInfomsg.Type", Field, 0, ""}, + {"IfInfomsg.X__ifi_pad", Field, 0, ""}, + {"IfMsghdr", Type, 0, ""}, + {"IfMsghdr.Addrs", Field, 0, ""}, + {"IfMsghdr.Data", Field, 0, ""}, + {"IfMsghdr.Flags", Field, 0, ""}, + {"IfMsghdr.Hdrlen", Field, 2, ""}, + {"IfMsghdr.Index", Field, 0, ""}, + {"IfMsghdr.Msglen", Field, 0, ""}, + {"IfMsghdr.Pad1", Field, 2, ""}, + {"IfMsghdr.Pad2", Field, 2, ""}, + {"IfMsghdr.Pad_cgo_0", Field, 0, ""}, + {"IfMsghdr.Pad_cgo_1", Field, 2, ""}, + {"IfMsghdr.Tableid", Field, 2, ""}, + {"IfMsghdr.Type", Field, 0, ""}, + {"IfMsghdr.Version", Field, 0, ""}, + {"IfMsghdr.Xflags", Field, 2, ""}, + {"IfaMsghdr", Type, 0, ""}, + {"IfaMsghdr.Addrs", Field, 0, ""}, + {"IfaMsghdr.Flags", Field, 0, ""}, + {"IfaMsghdr.Hdrlen", Field, 2, ""}, + {"IfaMsghdr.Index", Field, 0, ""}, + {"IfaMsghdr.Metric", Field, 0, ""}, + {"IfaMsghdr.Msglen", Field, 0, ""}, + {"IfaMsghdr.Pad1", Field, 2, ""}, + {"IfaMsghdr.Pad2", Field, 2, ""}, + {"IfaMsghdr.Pad_cgo_0", Field, 0, ""}, + {"IfaMsghdr.Tableid", Field, 2, ""}, + {"IfaMsghdr.Type", Field, 0, ""}, + {"IfaMsghdr.Version", Field, 0, ""}, + {"IfmaMsghdr", Type, 0, ""}, + {"IfmaMsghdr.Addrs", Field, 0, ""}, + {"IfmaMsghdr.Flags", Field, 0, ""}, + {"IfmaMsghdr.Index", Field, 0, ""}, + {"IfmaMsghdr.Msglen", Field, 0, ""}, + {"IfmaMsghdr.Pad_cgo_0", Field, 0, ""}, + {"IfmaMsghdr.Type", Field, 0, ""}, + {"IfmaMsghdr.Version", Field, 0, ""}, + {"IfmaMsghdr2", Type, 0, ""}, + {"IfmaMsghdr2.Addrs", Field, 0, ""}, + {"IfmaMsghdr2.Flags", Field, 0, ""}, + {"IfmaMsghdr2.Index", Field, 0, ""}, + {"IfmaMsghdr2.Msglen", Field, 0, ""}, + {"IfmaMsghdr2.Pad_cgo_0", Field, 0, ""}, + {"IfmaMsghdr2.Refcount", Field, 0, ""}, + {"IfmaMsghdr2.Type", Field, 0, ""}, + {"IfmaMsghdr2.Version", Field, 0, ""}, + {"ImplementsGetwd", Const, 0, ""}, + {"Inet4Pktinfo", Type, 0, ""}, + {"Inet4Pktinfo.Addr", Field, 0, ""}, + {"Inet4Pktinfo.Ifindex", Field, 0, ""}, + {"Inet4Pktinfo.Spec_dst", Field, 0, ""}, + {"Inet6Pktinfo", Type, 0, ""}, + {"Inet6Pktinfo.Addr", Field, 0, ""}, + {"Inet6Pktinfo.Ifindex", Field, 0, ""}, + {"InotifyAddWatch", Func, 0, "func(fd int, pathname string, mask uint32) (watchdesc int, err error)"}, + {"InotifyEvent", Type, 0, ""}, + {"InotifyEvent.Cookie", Field, 0, ""}, + {"InotifyEvent.Len", Field, 0, ""}, + {"InotifyEvent.Mask", Field, 0, ""}, + {"InotifyEvent.Name", Field, 0, ""}, + {"InotifyEvent.Wd", Field, 0, ""}, + {"InotifyInit", Func, 0, "func() (fd int, err error)"}, + {"InotifyInit1", Func, 0, "func(flags int) (fd int, err error)"}, + {"InotifyRmWatch", Func, 0, "func(fd int, watchdesc uint32) (success int, err error)"}, + {"InterfaceAddrMessage", Type, 0, ""}, + {"InterfaceAddrMessage.Data", Field, 0, ""}, + {"InterfaceAddrMessage.Header", Field, 0, ""}, + {"InterfaceAnnounceMessage", Type, 1, ""}, + {"InterfaceAnnounceMessage.Header", Field, 1, ""}, + {"InterfaceInfo", Type, 0, ""}, + {"InterfaceInfo.Address", Field, 0, ""}, + {"InterfaceInfo.BroadcastAddress", Field, 0, ""}, + {"InterfaceInfo.Flags", Field, 0, ""}, + {"InterfaceInfo.Netmask", Field, 0, ""}, + {"InterfaceMessage", Type, 0, ""}, + {"InterfaceMessage.Data", Field, 0, ""}, + {"InterfaceMessage.Header", Field, 0, ""}, + {"InterfaceMulticastAddrMessage", Type, 0, ""}, + {"InterfaceMulticastAddrMessage.Data", Field, 0, ""}, + {"InterfaceMulticastAddrMessage.Header", Field, 0, ""}, + {"InvalidHandle", Const, 0, ""}, + {"Ioperm", Func, 0, "func(from int, num int, on int) (err error)"}, + {"Iopl", Func, 0, "func(level int) (err error)"}, + {"Iovec", Type, 0, ""}, + {"Iovec.Base", Field, 0, ""}, + {"Iovec.Len", Field, 0, ""}, + {"IpAdapterInfo", Type, 0, ""}, + {"IpAdapterInfo.AdapterName", Field, 0, ""}, + {"IpAdapterInfo.Address", Field, 0, ""}, + {"IpAdapterInfo.AddressLength", Field, 0, ""}, + {"IpAdapterInfo.ComboIndex", Field, 0, ""}, + {"IpAdapterInfo.CurrentIpAddress", Field, 0, ""}, + {"IpAdapterInfo.Description", Field, 0, ""}, + {"IpAdapterInfo.DhcpEnabled", Field, 0, ""}, + {"IpAdapterInfo.DhcpServer", Field, 0, ""}, + {"IpAdapterInfo.GatewayList", Field, 0, ""}, + {"IpAdapterInfo.HaveWins", Field, 0, ""}, + {"IpAdapterInfo.Index", Field, 0, ""}, + {"IpAdapterInfo.IpAddressList", Field, 0, ""}, + {"IpAdapterInfo.LeaseExpires", Field, 0, ""}, + {"IpAdapterInfo.LeaseObtained", Field, 0, ""}, + {"IpAdapterInfo.Next", Field, 0, ""}, + {"IpAdapterInfo.PrimaryWinsServer", Field, 0, ""}, + {"IpAdapterInfo.SecondaryWinsServer", Field, 0, ""}, + {"IpAdapterInfo.Type", Field, 0, ""}, + {"IpAddrString", Type, 0, ""}, + {"IpAddrString.Context", Field, 0, ""}, + {"IpAddrString.IpAddress", Field, 0, ""}, + {"IpAddrString.IpMask", Field, 0, ""}, + {"IpAddrString.Next", Field, 0, ""}, + {"IpAddressString", Type, 0, ""}, + {"IpAddressString.String", Field, 0, ""}, + {"IpMaskString", Type, 0, ""}, + {"IpMaskString.String", Field, 2, ""}, + {"Issetugid", Func, 0, ""}, + {"KEY_ALL_ACCESS", Const, 0, ""}, + {"KEY_CREATE_LINK", Const, 0, ""}, + {"KEY_CREATE_SUB_KEY", Const, 0, ""}, + {"KEY_ENUMERATE_SUB_KEYS", Const, 0, ""}, + {"KEY_EXECUTE", Const, 0, ""}, + {"KEY_NOTIFY", Const, 0, ""}, + {"KEY_QUERY_VALUE", Const, 0, ""}, + {"KEY_READ", Const, 0, ""}, + {"KEY_SET_VALUE", Const, 0, ""}, + {"KEY_WOW64_32KEY", Const, 0, ""}, + {"KEY_WOW64_64KEY", Const, 0, ""}, + {"KEY_WRITE", Const, 0, ""}, + {"Kevent", Func, 0, ""}, + {"Kevent_t", Type, 0, ""}, + {"Kevent_t.Data", Field, 0, ""}, + {"Kevent_t.Fflags", Field, 0, ""}, + {"Kevent_t.Filter", Field, 0, ""}, + {"Kevent_t.Flags", Field, 0, ""}, + {"Kevent_t.Ident", Field, 0, ""}, + {"Kevent_t.Pad_cgo_0", Field, 2, ""}, + {"Kevent_t.Udata", Field, 0, ""}, + {"Kill", Func, 0, "func(pid int, sig Signal) (err error)"}, + {"Klogctl", Func, 0, "func(typ int, buf []byte) (n int, err error)"}, + {"Kqueue", Func, 0, ""}, + {"LANG_ENGLISH", Const, 0, ""}, + {"LAYERED_PROTOCOL", Const, 2, ""}, + {"LCNT_OVERLOAD_FLUSH", Const, 1, ""}, + {"LINUX_REBOOT_CMD_CAD_OFF", Const, 0, ""}, + {"LINUX_REBOOT_CMD_CAD_ON", Const, 0, ""}, + {"LINUX_REBOOT_CMD_HALT", Const, 0, ""}, + {"LINUX_REBOOT_CMD_KEXEC", Const, 0, ""}, + {"LINUX_REBOOT_CMD_POWER_OFF", Const, 0, ""}, + {"LINUX_REBOOT_CMD_RESTART", Const, 0, ""}, + {"LINUX_REBOOT_CMD_RESTART2", Const, 0, ""}, + {"LINUX_REBOOT_CMD_SW_SUSPEND", Const, 0, ""}, + {"LINUX_REBOOT_MAGIC1", Const, 0, ""}, + {"LINUX_REBOOT_MAGIC2", Const, 0, ""}, + {"LOCK_EX", Const, 0, ""}, + {"LOCK_NB", Const, 0, ""}, + {"LOCK_SH", Const, 0, ""}, + {"LOCK_UN", Const, 0, ""}, + {"LazyDLL", Type, 0, ""}, + {"LazyDLL.Name", Field, 0, ""}, + {"LazyProc", Type, 0, ""}, + {"LazyProc.Name", Field, 0, ""}, + {"Lchown", Func, 0, "func(path string, uid int, gid int) (err error)"}, + {"Linger", Type, 0, ""}, + {"Linger.Linger", Field, 0, ""}, + {"Linger.Onoff", Field, 0, ""}, + {"Link", Func, 0, "func(oldpath string, newpath string) (err error)"}, + {"Listen", Func, 0, "func(s int, n int) (err error)"}, + {"Listxattr", Func, 1, "func(path string, dest []byte) (sz int, err error)"}, + {"LoadCancelIoEx", Func, 1, ""}, + {"LoadConnectEx", Func, 1, ""}, + {"LoadCreateSymbolicLink", Func, 4, ""}, + {"LoadDLL", Func, 0, ""}, + {"LoadGetAddrInfo", Func, 1, ""}, + {"LoadLibrary", Func, 0, ""}, + {"LoadSetFileCompletionNotificationModes", Func, 2, ""}, + {"LocalFree", Func, 0, ""}, + {"Log2phys_t", Type, 0, ""}, + {"Log2phys_t.Contigbytes", Field, 0, ""}, + {"Log2phys_t.Devoffset", Field, 0, ""}, + {"Log2phys_t.Flags", Field, 0, ""}, + {"LookupAccountName", Func, 0, ""}, + {"LookupAccountSid", Func, 0, ""}, + {"LookupSID", Func, 0, ""}, + {"LsfJump", Func, 0, "func(code int, k int, jt int, jf int) *SockFilter"}, + {"LsfSocket", Func, 0, "func(ifindex int, proto int) (int, error)"}, + {"LsfStmt", Func, 0, "func(code int, k int) *SockFilter"}, + {"Lstat", Func, 0, "func(path string, stat *Stat_t) (err error)"}, + {"MADV_AUTOSYNC", Const, 1, ""}, + {"MADV_CAN_REUSE", Const, 0, ""}, + {"MADV_CORE", Const, 1, ""}, + {"MADV_DOFORK", Const, 0, ""}, + {"MADV_DONTFORK", Const, 0, ""}, + {"MADV_DONTNEED", Const, 0, ""}, + {"MADV_FREE", Const, 0, ""}, + {"MADV_FREE_REUSABLE", Const, 0, ""}, + {"MADV_FREE_REUSE", Const, 0, ""}, + {"MADV_HUGEPAGE", Const, 0, ""}, + {"MADV_HWPOISON", Const, 0, ""}, + {"MADV_MERGEABLE", Const, 0, ""}, + {"MADV_NOCORE", Const, 1, ""}, + {"MADV_NOHUGEPAGE", Const, 0, ""}, + {"MADV_NORMAL", Const, 0, ""}, + {"MADV_NOSYNC", Const, 1, ""}, + {"MADV_PROTECT", Const, 1, ""}, + {"MADV_RANDOM", Const, 0, ""}, + {"MADV_REMOVE", Const, 0, ""}, + {"MADV_SEQUENTIAL", Const, 0, ""}, + {"MADV_SPACEAVAIL", Const, 3, ""}, + {"MADV_UNMERGEABLE", Const, 0, ""}, + {"MADV_WILLNEED", Const, 0, ""}, + {"MADV_ZERO_WIRED_PAGES", Const, 0, ""}, + {"MAP_32BIT", Const, 0, ""}, + {"MAP_ALIGNED_SUPER", Const, 3, ""}, + {"MAP_ALIGNMENT_16MB", Const, 3, ""}, + {"MAP_ALIGNMENT_1TB", Const, 3, ""}, + {"MAP_ALIGNMENT_256TB", Const, 3, ""}, + {"MAP_ALIGNMENT_4GB", Const, 3, ""}, + {"MAP_ALIGNMENT_64KB", Const, 3, ""}, + {"MAP_ALIGNMENT_64PB", Const, 3, ""}, + {"MAP_ALIGNMENT_MASK", Const, 3, ""}, + {"MAP_ALIGNMENT_SHIFT", Const, 3, ""}, + {"MAP_ANON", Const, 0, ""}, + {"MAP_ANONYMOUS", Const, 0, ""}, + {"MAP_COPY", Const, 0, ""}, + {"MAP_DENYWRITE", Const, 0, ""}, + {"MAP_EXECUTABLE", Const, 0, ""}, + {"MAP_FILE", Const, 0, ""}, + {"MAP_FIXED", Const, 0, ""}, + {"MAP_FLAGMASK", Const, 3, ""}, + {"MAP_GROWSDOWN", Const, 0, ""}, + {"MAP_HASSEMAPHORE", Const, 0, ""}, + {"MAP_HUGETLB", Const, 0, ""}, + {"MAP_INHERIT", Const, 3, ""}, + {"MAP_INHERIT_COPY", Const, 3, ""}, + {"MAP_INHERIT_DEFAULT", Const, 3, ""}, + {"MAP_INHERIT_DONATE_COPY", Const, 3, ""}, + {"MAP_INHERIT_NONE", Const, 3, ""}, + {"MAP_INHERIT_SHARE", Const, 3, ""}, + {"MAP_JIT", Const, 0, ""}, + {"MAP_LOCKED", Const, 0, ""}, + {"MAP_NOCACHE", Const, 0, ""}, + {"MAP_NOCORE", Const, 1, ""}, + {"MAP_NOEXTEND", Const, 0, ""}, + {"MAP_NONBLOCK", Const, 0, ""}, + {"MAP_NORESERVE", Const, 0, ""}, + {"MAP_NOSYNC", Const, 1, ""}, + {"MAP_POPULATE", Const, 0, ""}, + {"MAP_PREFAULT_READ", Const, 1, ""}, + {"MAP_PRIVATE", Const, 0, ""}, + {"MAP_RENAME", Const, 0, ""}, + {"MAP_RESERVED0080", Const, 0, ""}, + {"MAP_RESERVED0100", Const, 1, ""}, + {"MAP_SHARED", Const, 0, ""}, + {"MAP_STACK", Const, 0, ""}, + {"MAP_TRYFIXED", Const, 3, ""}, + {"MAP_TYPE", Const, 0, ""}, + {"MAP_WIRED", Const, 3, ""}, + {"MAXIMUM_REPARSE_DATA_BUFFER_SIZE", Const, 4, ""}, + {"MAXLEN_IFDESCR", Const, 0, ""}, + {"MAXLEN_PHYSADDR", Const, 0, ""}, + {"MAX_ADAPTER_ADDRESS_LENGTH", Const, 0, ""}, + {"MAX_ADAPTER_DESCRIPTION_LENGTH", Const, 0, ""}, + {"MAX_ADAPTER_NAME_LENGTH", Const, 0, ""}, + {"MAX_COMPUTERNAME_LENGTH", Const, 0, ""}, + {"MAX_INTERFACE_NAME_LEN", Const, 0, ""}, + {"MAX_LONG_PATH", Const, 0, ""}, + {"MAX_PATH", Const, 0, ""}, + {"MAX_PROTOCOL_CHAIN", Const, 2, ""}, + {"MCL_CURRENT", Const, 0, ""}, + {"MCL_FUTURE", Const, 0, ""}, + {"MNT_DETACH", Const, 0, ""}, + {"MNT_EXPIRE", Const, 0, ""}, + {"MNT_FORCE", Const, 0, ""}, + {"MSG_BCAST", Const, 1, ""}, + {"MSG_CMSG_CLOEXEC", Const, 0, ""}, + {"MSG_COMPAT", Const, 0, ""}, + {"MSG_CONFIRM", Const, 0, ""}, + {"MSG_CONTROLMBUF", Const, 1, ""}, + {"MSG_CTRUNC", Const, 0, ""}, + {"MSG_DONTROUTE", Const, 0, ""}, + {"MSG_DONTWAIT", Const, 0, ""}, + {"MSG_EOF", Const, 0, ""}, + {"MSG_EOR", Const, 0, ""}, + {"MSG_ERRQUEUE", Const, 0, ""}, + {"MSG_FASTOPEN", Const, 1, ""}, + {"MSG_FIN", Const, 0, ""}, + {"MSG_FLUSH", Const, 0, ""}, + {"MSG_HAVEMORE", Const, 0, ""}, + {"MSG_HOLD", Const, 0, ""}, + {"MSG_IOVUSRSPACE", Const, 1, ""}, + {"MSG_LENUSRSPACE", Const, 1, ""}, + {"MSG_MCAST", Const, 1, ""}, + {"MSG_MORE", Const, 0, ""}, + {"MSG_NAMEMBUF", Const, 1, ""}, + {"MSG_NBIO", Const, 0, ""}, + {"MSG_NEEDSA", Const, 0, ""}, + {"MSG_NOSIGNAL", Const, 0, ""}, + {"MSG_NOTIFICATION", Const, 0, ""}, + {"MSG_OOB", Const, 0, ""}, + {"MSG_PEEK", Const, 0, ""}, + {"MSG_PROXY", Const, 0, ""}, + {"MSG_RCVMORE", Const, 0, ""}, + {"MSG_RST", Const, 0, ""}, + {"MSG_SEND", Const, 0, ""}, + {"MSG_SYN", Const, 0, ""}, + {"MSG_TRUNC", Const, 0, ""}, + {"MSG_TRYHARD", Const, 0, ""}, + {"MSG_USERFLAGS", Const, 1, ""}, + {"MSG_WAITALL", Const, 0, ""}, + {"MSG_WAITFORONE", Const, 0, ""}, + {"MSG_WAITSTREAM", Const, 0, ""}, + {"MS_ACTIVE", Const, 0, ""}, + {"MS_ASYNC", Const, 0, ""}, + {"MS_BIND", Const, 0, ""}, + {"MS_DEACTIVATE", Const, 0, ""}, + {"MS_DIRSYNC", Const, 0, ""}, + {"MS_INVALIDATE", Const, 0, ""}, + {"MS_I_VERSION", Const, 0, ""}, + {"MS_KERNMOUNT", Const, 0, ""}, + {"MS_KILLPAGES", Const, 0, ""}, + {"MS_MANDLOCK", Const, 0, ""}, + {"MS_MGC_MSK", Const, 0, ""}, + {"MS_MGC_VAL", Const, 0, ""}, + {"MS_MOVE", Const, 0, ""}, + {"MS_NOATIME", Const, 0, ""}, + {"MS_NODEV", Const, 0, ""}, + {"MS_NODIRATIME", Const, 0, ""}, + {"MS_NOEXEC", Const, 0, ""}, + {"MS_NOSUID", Const, 0, ""}, + {"MS_NOUSER", Const, 0, ""}, + {"MS_POSIXACL", Const, 0, ""}, + {"MS_PRIVATE", Const, 0, ""}, + {"MS_RDONLY", Const, 0, ""}, + {"MS_REC", Const, 0, ""}, + {"MS_RELATIME", Const, 0, ""}, + {"MS_REMOUNT", Const, 0, ""}, + {"MS_RMT_MASK", Const, 0, ""}, + {"MS_SHARED", Const, 0, ""}, + {"MS_SILENT", Const, 0, ""}, + {"MS_SLAVE", Const, 0, ""}, + {"MS_STRICTATIME", Const, 0, ""}, + {"MS_SYNC", Const, 0, ""}, + {"MS_SYNCHRONOUS", Const, 0, ""}, + {"MS_UNBINDABLE", Const, 0, ""}, + {"Madvise", Func, 0, "func(b []byte, advice int) (err error)"}, + {"MapViewOfFile", Func, 0, ""}, + {"MaxTokenInfoClass", Const, 0, ""}, + {"Mclpool", Type, 2, ""}, + {"Mclpool.Alive", Field, 2, ""}, + {"Mclpool.Cwm", Field, 2, ""}, + {"Mclpool.Grown", Field, 2, ""}, + {"Mclpool.Hwm", Field, 2, ""}, + {"Mclpool.Lwm", Field, 2, ""}, + {"MibIfRow", Type, 0, ""}, + {"MibIfRow.AdminStatus", Field, 0, ""}, + {"MibIfRow.Descr", Field, 0, ""}, + {"MibIfRow.DescrLen", Field, 0, ""}, + {"MibIfRow.InDiscards", Field, 0, ""}, + {"MibIfRow.InErrors", Field, 0, ""}, + {"MibIfRow.InNUcastPkts", Field, 0, ""}, + {"MibIfRow.InOctets", Field, 0, ""}, + {"MibIfRow.InUcastPkts", Field, 0, ""}, + {"MibIfRow.InUnknownProtos", Field, 0, ""}, + {"MibIfRow.Index", Field, 0, ""}, + {"MibIfRow.LastChange", Field, 0, ""}, + {"MibIfRow.Mtu", Field, 0, ""}, + {"MibIfRow.Name", Field, 0, ""}, + {"MibIfRow.OperStatus", Field, 0, ""}, + {"MibIfRow.OutDiscards", Field, 0, ""}, + {"MibIfRow.OutErrors", Field, 0, ""}, + {"MibIfRow.OutNUcastPkts", Field, 0, ""}, + {"MibIfRow.OutOctets", Field, 0, ""}, + {"MibIfRow.OutQLen", Field, 0, ""}, + {"MibIfRow.OutUcastPkts", Field, 0, ""}, + {"MibIfRow.PhysAddr", Field, 0, ""}, + {"MibIfRow.PhysAddrLen", Field, 0, ""}, + {"MibIfRow.Speed", Field, 0, ""}, + {"MibIfRow.Type", Field, 0, ""}, + {"Mkdir", Func, 0, "func(path string, mode uint32) (err error)"}, + {"Mkdirat", Func, 0, "func(dirfd int, path string, mode uint32) (err error)"}, + {"Mkfifo", Func, 0, "func(path string, mode uint32) (err error)"}, + {"Mknod", Func, 0, "func(path string, mode uint32, dev int) (err error)"}, + {"Mknodat", Func, 0, "func(dirfd int, path string, mode uint32, dev int) (err error)"}, + {"Mlock", Func, 0, "func(b []byte) (err error)"}, + {"Mlockall", Func, 0, "func(flags int) (err error)"}, + {"Mmap", Func, 0, "func(fd int, offset int64, length int, prot int, flags int) (data []byte, err error)"}, + {"Mount", Func, 0, "func(source string, target string, fstype string, flags uintptr, data string) (err error)"}, + {"MoveFile", Func, 0, ""}, + {"Mprotect", Func, 0, "func(b []byte, prot int) (err error)"}, + {"Msghdr", Type, 0, ""}, + {"Msghdr.Control", Field, 0, ""}, + {"Msghdr.Controllen", Field, 0, ""}, + {"Msghdr.Flags", Field, 0, ""}, + {"Msghdr.Iov", Field, 0, ""}, + {"Msghdr.Iovlen", Field, 0, ""}, + {"Msghdr.Name", Field, 0, ""}, + {"Msghdr.Namelen", Field, 0, ""}, + {"Msghdr.Pad_cgo_0", Field, 0, ""}, + {"Msghdr.Pad_cgo_1", Field, 0, ""}, + {"Munlock", Func, 0, "func(b []byte) (err error)"}, + {"Munlockall", Func, 0, "func() (err error)"}, + {"Munmap", Func, 0, "func(b []byte) (err error)"}, + {"MustLoadDLL", Func, 0, ""}, + {"NAME_MAX", Const, 0, ""}, + {"NETLINK_ADD_MEMBERSHIP", Const, 0, ""}, + {"NETLINK_AUDIT", Const, 0, ""}, + {"NETLINK_BROADCAST_ERROR", Const, 0, ""}, + {"NETLINK_CONNECTOR", Const, 0, ""}, + {"NETLINK_DNRTMSG", Const, 0, ""}, + {"NETLINK_DROP_MEMBERSHIP", Const, 0, ""}, + {"NETLINK_ECRYPTFS", Const, 0, ""}, + {"NETLINK_FIB_LOOKUP", Const, 0, ""}, + {"NETLINK_FIREWALL", Const, 0, ""}, + {"NETLINK_GENERIC", Const, 0, ""}, + {"NETLINK_INET_DIAG", Const, 0, ""}, + {"NETLINK_IP6_FW", Const, 0, ""}, + {"NETLINK_ISCSI", Const, 0, ""}, + {"NETLINK_KOBJECT_UEVENT", Const, 0, ""}, + {"NETLINK_NETFILTER", Const, 0, ""}, + {"NETLINK_NFLOG", Const, 0, ""}, + {"NETLINK_NO_ENOBUFS", Const, 0, ""}, + {"NETLINK_PKTINFO", Const, 0, ""}, + {"NETLINK_RDMA", Const, 0, ""}, + {"NETLINK_ROUTE", Const, 0, ""}, + {"NETLINK_SCSITRANSPORT", Const, 0, ""}, + {"NETLINK_SELINUX", Const, 0, ""}, + {"NETLINK_UNUSED", Const, 0, ""}, + {"NETLINK_USERSOCK", Const, 0, ""}, + {"NETLINK_XFRM", Const, 0, ""}, + {"NET_RT_DUMP", Const, 0, ""}, + {"NET_RT_DUMP2", Const, 0, ""}, + {"NET_RT_FLAGS", Const, 0, ""}, + {"NET_RT_IFLIST", Const, 0, ""}, + {"NET_RT_IFLIST2", Const, 0, ""}, + {"NET_RT_IFLISTL", Const, 1, ""}, + {"NET_RT_IFMALIST", Const, 0, ""}, + {"NET_RT_MAXID", Const, 0, ""}, + {"NET_RT_OIFLIST", Const, 1, ""}, + {"NET_RT_OOIFLIST", Const, 1, ""}, + {"NET_RT_STAT", Const, 0, ""}, + {"NET_RT_STATS", Const, 1, ""}, + {"NET_RT_TABLE", Const, 1, ""}, + {"NET_RT_TRASH", Const, 0, ""}, + {"NLA_ALIGNTO", Const, 0, ""}, + {"NLA_F_NESTED", Const, 0, ""}, + {"NLA_F_NET_BYTEORDER", Const, 0, ""}, + {"NLA_HDRLEN", Const, 0, ""}, + {"NLMSG_ALIGNTO", Const, 0, ""}, + {"NLMSG_DONE", Const, 0, ""}, + {"NLMSG_ERROR", Const, 0, ""}, + {"NLMSG_HDRLEN", Const, 0, ""}, + {"NLMSG_MIN_TYPE", Const, 0, ""}, + {"NLMSG_NOOP", Const, 0, ""}, + {"NLMSG_OVERRUN", Const, 0, ""}, + {"NLM_F_ACK", Const, 0, ""}, + {"NLM_F_APPEND", Const, 0, ""}, + {"NLM_F_ATOMIC", Const, 0, ""}, + {"NLM_F_CREATE", Const, 0, ""}, + {"NLM_F_DUMP", Const, 0, ""}, + {"NLM_F_ECHO", Const, 0, ""}, + {"NLM_F_EXCL", Const, 0, ""}, + {"NLM_F_MATCH", Const, 0, ""}, + {"NLM_F_MULTI", Const, 0, ""}, + {"NLM_F_REPLACE", Const, 0, ""}, + {"NLM_F_REQUEST", Const, 0, ""}, + {"NLM_F_ROOT", Const, 0, ""}, + {"NOFLSH", Const, 0, ""}, + {"NOTE_ABSOLUTE", Const, 0, ""}, + {"NOTE_ATTRIB", Const, 0, ""}, + {"NOTE_BACKGROUND", Const, 16, ""}, + {"NOTE_CHILD", Const, 0, ""}, + {"NOTE_CRITICAL", Const, 16, ""}, + {"NOTE_DELETE", Const, 0, ""}, + {"NOTE_EOF", Const, 1, ""}, + {"NOTE_EXEC", Const, 0, ""}, + {"NOTE_EXIT", Const, 0, ""}, + {"NOTE_EXITSTATUS", Const, 0, ""}, + {"NOTE_EXIT_CSERROR", Const, 16, ""}, + {"NOTE_EXIT_DECRYPTFAIL", Const, 16, ""}, + {"NOTE_EXIT_DETAIL", Const, 16, ""}, + {"NOTE_EXIT_DETAIL_MASK", Const, 16, ""}, + {"NOTE_EXIT_MEMORY", Const, 16, ""}, + {"NOTE_EXIT_REPARENTED", Const, 16, ""}, + {"NOTE_EXTEND", Const, 0, ""}, + {"NOTE_FFAND", Const, 0, ""}, + {"NOTE_FFCOPY", Const, 0, ""}, + {"NOTE_FFCTRLMASK", Const, 0, ""}, + {"NOTE_FFLAGSMASK", Const, 0, ""}, + {"NOTE_FFNOP", Const, 0, ""}, + {"NOTE_FFOR", Const, 0, ""}, + {"NOTE_FORK", Const, 0, ""}, + {"NOTE_LEEWAY", Const, 16, ""}, + {"NOTE_LINK", Const, 0, ""}, + {"NOTE_LOWAT", Const, 0, ""}, + {"NOTE_NONE", Const, 0, ""}, + {"NOTE_NSECONDS", Const, 0, ""}, + {"NOTE_PCTRLMASK", Const, 0, ""}, + {"NOTE_PDATAMASK", Const, 0, ""}, + {"NOTE_REAP", Const, 0, ""}, + {"NOTE_RENAME", Const, 0, ""}, + {"NOTE_RESOURCEEND", Const, 0, ""}, + {"NOTE_REVOKE", Const, 0, ""}, + {"NOTE_SECONDS", Const, 0, ""}, + {"NOTE_SIGNAL", Const, 0, ""}, + {"NOTE_TRACK", Const, 0, ""}, + {"NOTE_TRACKERR", Const, 0, ""}, + {"NOTE_TRIGGER", Const, 0, ""}, + {"NOTE_TRUNCATE", Const, 1, ""}, + {"NOTE_USECONDS", Const, 0, ""}, + {"NOTE_VM_ERROR", Const, 0, ""}, + {"NOTE_VM_PRESSURE", Const, 0, ""}, + {"NOTE_VM_PRESSURE_SUDDEN_TERMINATE", Const, 0, ""}, + {"NOTE_VM_PRESSURE_TERMINATE", Const, 0, ""}, + {"NOTE_WRITE", Const, 0, ""}, + {"NameCanonical", Const, 0, ""}, + {"NameCanonicalEx", Const, 0, ""}, + {"NameDisplay", Const, 0, ""}, + {"NameDnsDomain", Const, 0, ""}, + {"NameFullyQualifiedDN", Const, 0, ""}, + {"NameSamCompatible", Const, 0, ""}, + {"NameServicePrincipal", Const, 0, ""}, + {"NameUniqueId", Const, 0, ""}, + {"NameUnknown", Const, 0, ""}, + {"NameUserPrincipal", Const, 0, ""}, + {"Nanosleep", Func, 0, "func(time *Timespec, leftover *Timespec) (err error)"}, + {"NetApiBufferFree", Func, 0, ""}, + {"NetGetJoinInformation", Func, 2, ""}, + {"NetSetupDomainName", Const, 2, ""}, + {"NetSetupUnjoined", Const, 2, ""}, + {"NetSetupUnknownStatus", Const, 2, ""}, + {"NetSetupWorkgroupName", Const, 2, ""}, + {"NetUserGetInfo", Func, 0, ""}, + {"NetlinkMessage", Type, 0, ""}, + {"NetlinkMessage.Data", Field, 0, ""}, + {"NetlinkMessage.Header", Field, 0, ""}, + {"NetlinkRIB", Func, 0, "func(proto int, family int) ([]byte, error)"}, + {"NetlinkRouteAttr", Type, 0, ""}, + {"NetlinkRouteAttr.Attr", Field, 0, ""}, + {"NetlinkRouteAttr.Value", Field, 0, ""}, + {"NetlinkRouteRequest", Type, 0, ""}, + {"NetlinkRouteRequest.Data", Field, 0, ""}, + {"NetlinkRouteRequest.Header", Field, 0, ""}, + {"NewCallback", Func, 0, ""}, + {"NewCallbackCDecl", Func, 3, ""}, + {"NewLazyDLL", Func, 0, ""}, + {"NlAttr", Type, 0, ""}, + {"NlAttr.Len", Field, 0, ""}, + {"NlAttr.Type", Field, 0, ""}, + {"NlMsgerr", Type, 0, ""}, + {"NlMsgerr.Error", Field, 0, ""}, + {"NlMsgerr.Msg", Field, 0, ""}, + {"NlMsghdr", Type, 0, ""}, + {"NlMsghdr.Flags", Field, 0, ""}, + {"NlMsghdr.Len", Field, 0, ""}, + {"NlMsghdr.Pid", Field, 0, ""}, + {"NlMsghdr.Seq", Field, 0, ""}, + {"NlMsghdr.Type", Field, 0, ""}, + {"NsecToFiletime", Func, 0, ""}, + {"NsecToTimespec", Func, 0, "func(nsec int64) Timespec"}, + {"NsecToTimeval", Func, 0, "func(nsec int64) Timeval"}, + {"Ntohs", Func, 0, ""}, + {"OCRNL", Const, 0, ""}, + {"OFDEL", Const, 0, ""}, + {"OFILL", Const, 0, ""}, + {"OFIOGETBMAP", Const, 1, ""}, + {"OID_PKIX_KP_SERVER_AUTH", Var, 0, ""}, + {"OID_SERVER_GATED_CRYPTO", Var, 0, ""}, + {"OID_SGC_NETSCAPE", Var, 0, ""}, + {"OLCUC", Const, 0, ""}, + {"ONLCR", Const, 0, ""}, + {"ONLRET", Const, 0, ""}, + {"ONOCR", Const, 0, ""}, + {"ONOEOT", Const, 1, ""}, + {"OPEN_ALWAYS", Const, 0, ""}, + {"OPEN_EXISTING", Const, 0, ""}, + {"OPOST", Const, 0, ""}, + {"O_ACCMODE", Const, 0, ""}, + {"O_ALERT", Const, 0, ""}, + {"O_ALT_IO", Const, 1, ""}, + {"O_APPEND", Const, 0, ""}, + {"O_ASYNC", Const, 0, ""}, + {"O_CLOEXEC", Const, 0, ""}, + {"O_CREAT", Const, 0, ""}, + {"O_DIRECT", Const, 0, ""}, + {"O_DIRECTORY", Const, 0, ""}, + {"O_DP_GETRAWENCRYPTED", Const, 16, ""}, + {"O_DSYNC", Const, 0, ""}, + {"O_EVTONLY", Const, 0, ""}, + {"O_EXCL", Const, 0, ""}, + {"O_EXEC", Const, 0, ""}, + {"O_EXLOCK", Const, 0, ""}, + {"O_FSYNC", Const, 0, ""}, + {"O_LARGEFILE", Const, 0, ""}, + {"O_NDELAY", Const, 0, ""}, + {"O_NOATIME", Const, 0, ""}, + {"O_NOCTTY", Const, 0, ""}, + {"O_NOFOLLOW", Const, 0, ""}, + {"O_NONBLOCK", Const, 0, ""}, + {"O_NOSIGPIPE", Const, 1, ""}, + {"O_POPUP", Const, 0, ""}, + {"O_RDONLY", Const, 0, ""}, + {"O_RDWR", Const, 0, ""}, + {"O_RSYNC", Const, 0, ""}, + {"O_SHLOCK", Const, 0, ""}, + {"O_SYMLINK", Const, 0, ""}, + {"O_SYNC", Const, 0, ""}, + {"O_TRUNC", Const, 0, ""}, + {"O_TTY_INIT", Const, 0, ""}, + {"O_WRONLY", Const, 0, ""}, + {"Open", Func, 0, "func(path string, mode int, perm uint32) (fd int, err error)"}, + {"OpenCurrentProcessToken", Func, 0, ""}, + {"OpenProcess", Func, 0, ""}, + {"OpenProcessToken", Func, 0, ""}, + {"Openat", Func, 0, "func(dirfd int, path string, flags int, mode uint32) (fd int, err error)"}, + {"Overlapped", Type, 0, ""}, + {"Overlapped.HEvent", Field, 0, ""}, + {"Overlapped.Internal", Field, 0, ""}, + {"Overlapped.InternalHigh", Field, 0, ""}, + {"Overlapped.Offset", Field, 0, ""}, + {"Overlapped.OffsetHigh", Field, 0, ""}, + {"PACKET_ADD_MEMBERSHIP", Const, 0, ""}, + {"PACKET_BROADCAST", Const, 0, ""}, + {"PACKET_DROP_MEMBERSHIP", Const, 0, ""}, + {"PACKET_FASTROUTE", Const, 0, ""}, + {"PACKET_HOST", Const, 0, ""}, + {"PACKET_LOOPBACK", Const, 0, ""}, + {"PACKET_MR_ALLMULTI", Const, 0, ""}, + {"PACKET_MR_MULTICAST", Const, 0, ""}, + {"PACKET_MR_PROMISC", Const, 0, ""}, + {"PACKET_MULTICAST", Const, 0, ""}, + {"PACKET_OTHERHOST", Const, 0, ""}, + {"PACKET_OUTGOING", Const, 0, ""}, + {"PACKET_RECV_OUTPUT", Const, 0, ""}, + {"PACKET_RX_RING", Const, 0, ""}, + {"PACKET_STATISTICS", Const, 0, ""}, + {"PAGE_EXECUTE_READ", Const, 0, ""}, + {"PAGE_EXECUTE_READWRITE", Const, 0, ""}, + {"PAGE_EXECUTE_WRITECOPY", Const, 0, ""}, + {"PAGE_READONLY", Const, 0, ""}, + {"PAGE_READWRITE", Const, 0, ""}, + {"PAGE_WRITECOPY", Const, 0, ""}, + {"PARENB", Const, 0, ""}, + {"PARMRK", Const, 0, ""}, + {"PARODD", Const, 0, ""}, + {"PENDIN", Const, 0, ""}, + {"PFL_HIDDEN", Const, 2, ""}, + {"PFL_MATCHES_PROTOCOL_ZERO", Const, 2, ""}, + {"PFL_MULTIPLE_PROTO_ENTRIES", Const, 2, ""}, + {"PFL_NETWORKDIRECT_PROVIDER", Const, 2, ""}, + {"PFL_RECOMMENDED_PROTO_ENTRY", Const, 2, ""}, + {"PF_FLUSH", Const, 1, ""}, + {"PKCS_7_ASN_ENCODING", Const, 0, ""}, + {"PMC5_PIPELINE_FLUSH", Const, 1, ""}, + {"PRIO_PGRP", Const, 2, ""}, + {"PRIO_PROCESS", Const, 2, ""}, + {"PRIO_USER", Const, 2, ""}, + {"PRI_IOFLUSH", Const, 1, ""}, + {"PROCESS_QUERY_INFORMATION", Const, 0, ""}, + {"PROCESS_TERMINATE", Const, 2, ""}, + {"PROT_EXEC", Const, 0, ""}, + {"PROT_GROWSDOWN", Const, 0, ""}, + {"PROT_GROWSUP", Const, 0, ""}, + {"PROT_NONE", Const, 0, ""}, + {"PROT_READ", Const, 0, ""}, + {"PROT_WRITE", Const, 0, ""}, + {"PROV_DH_SCHANNEL", Const, 0, ""}, + {"PROV_DSS", Const, 0, ""}, + {"PROV_DSS_DH", Const, 0, ""}, + {"PROV_EC_ECDSA_FULL", Const, 0, ""}, + {"PROV_EC_ECDSA_SIG", Const, 0, ""}, + {"PROV_EC_ECNRA_FULL", Const, 0, ""}, + {"PROV_EC_ECNRA_SIG", Const, 0, ""}, + {"PROV_FORTEZZA", Const, 0, ""}, + {"PROV_INTEL_SEC", Const, 0, ""}, + {"PROV_MS_EXCHANGE", Const, 0, ""}, + {"PROV_REPLACE_OWF", Const, 0, ""}, + {"PROV_RNG", Const, 0, ""}, + {"PROV_RSA_AES", Const, 0, ""}, + {"PROV_RSA_FULL", Const, 0, ""}, + {"PROV_RSA_SCHANNEL", Const, 0, ""}, + {"PROV_RSA_SIG", Const, 0, ""}, + {"PROV_SPYRUS_LYNKS", Const, 0, ""}, + {"PROV_SSL", Const, 0, ""}, + {"PR_CAPBSET_DROP", Const, 0, ""}, + {"PR_CAPBSET_READ", Const, 0, ""}, + {"PR_CLEAR_SECCOMP_FILTER", Const, 0, ""}, + {"PR_ENDIAN_BIG", Const, 0, ""}, + {"PR_ENDIAN_LITTLE", Const, 0, ""}, + {"PR_ENDIAN_PPC_LITTLE", Const, 0, ""}, + {"PR_FPEMU_NOPRINT", Const, 0, ""}, + {"PR_FPEMU_SIGFPE", Const, 0, ""}, + {"PR_FP_EXC_ASYNC", Const, 0, ""}, + {"PR_FP_EXC_DISABLED", Const, 0, ""}, + {"PR_FP_EXC_DIV", Const, 0, ""}, + {"PR_FP_EXC_INV", Const, 0, ""}, + {"PR_FP_EXC_NONRECOV", Const, 0, ""}, + {"PR_FP_EXC_OVF", Const, 0, ""}, + {"PR_FP_EXC_PRECISE", Const, 0, ""}, + {"PR_FP_EXC_RES", Const, 0, ""}, + {"PR_FP_EXC_SW_ENABLE", Const, 0, ""}, + {"PR_FP_EXC_UND", Const, 0, ""}, + {"PR_GET_DUMPABLE", Const, 0, ""}, + {"PR_GET_ENDIAN", Const, 0, ""}, + {"PR_GET_FPEMU", Const, 0, ""}, + {"PR_GET_FPEXC", Const, 0, ""}, + {"PR_GET_KEEPCAPS", Const, 0, ""}, + {"PR_GET_NAME", Const, 0, ""}, + {"PR_GET_PDEATHSIG", Const, 0, ""}, + {"PR_GET_SECCOMP", Const, 0, ""}, + {"PR_GET_SECCOMP_FILTER", Const, 0, ""}, + {"PR_GET_SECUREBITS", Const, 0, ""}, + {"PR_GET_TIMERSLACK", Const, 0, ""}, + {"PR_GET_TIMING", Const, 0, ""}, + {"PR_GET_TSC", Const, 0, ""}, + {"PR_GET_UNALIGN", Const, 0, ""}, + {"PR_MCE_KILL", Const, 0, ""}, + {"PR_MCE_KILL_CLEAR", Const, 0, ""}, + {"PR_MCE_KILL_DEFAULT", Const, 0, ""}, + {"PR_MCE_KILL_EARLY", Const, 0, ""}, + {"PR_MCE_KILL_GET", Const, 0, ""}, + {"PR_MCE_KILL_LATE", Const, 0, ""}, + {"PR_MCE_KILL_SET", Const, 0, ""}, + {"PR_SECCOMP_FILTER_EVENT", Const, 0, ""}, + {"PR_SECCOMP_FILTER_SYSCALL", Const, 0, ""}, + {"PR_SET_DUMPABLE", Const, 0, ""}, + {"PR_SET_ENDIAN", Const, 0, ""}, + {"PR_SET_FPEMU", Const, 0, ""}, + {"PR_SET_FPEXC", Const, 0, ""}, + {"PR_SET_KEEPCAPS", Const, 0, ""}, + {"PR_SET_NAME", Const, 0, ""}, + {"PR_SET_PDEATHSIG", Const, 0, ""}, + {"PR_SET_PTRACER", Const, 0, ""}, + {"PR_SET_SECCOMP", Const, 0, ""}, + {"PR_SET_SECCOMP_FILTER", Const, 0, ""}, + {"PR_SET_SECUREBITS", Const, 0, ""}, + {"PR_SET_TIMERSLACK", Const, 0, ""}, + {"PR_SET_TIMING", Const, 0, ""}, + {"PR_SET_TSC", Const, 0, ""}, + {"PR_SET_UNALIGN", Const, 0, ""}, + {"PR_TASK_PERF_EVENTS_DISABLE", Const, 0, ""}, + {"PR_TASK_PERF_EVENTS_ENABLE", Const, 0, ""}, + {"PR_TIMING_STATISTICAL", Const, 0, ""}, + {"PR_TIMING_TIMESTAMP", Const, 0, ""}, + {"PR_TSC_ENABLE", Const, 0, ""}, + {"PR_TSC_SIGSEGV", Const, 0, ""}, + {"PR_UNALIGN_NOPRINT", Const, 0, ""}, + {"PR_UNALIGN_SIGBUS", Const, 0, ""}, + {"PTRACE_ARCH_PRCTL", Const, 0, ""}, + {"PTRACE_ATTACH", Const, 0, ""}, + {"PTRACE_CONT", Const, 0, ""}, + {"PTRACE_DETACH", Const, 0, ""}, + {"PTRACE_EVENT_CLONE", Const, 0, ""}, + {"PTRACE_EVENT_EXEC", Const, 0, ""}, + {"PTRACE_EVENT_EXIT", Const, 0, ""}, + {"PTRACE_EVENT_FORK", Const, 0, ""}, + {"PTRACE_EVENT_VFORK", Const, 0, ""}, + {"PTRACE_EVENT_VFORK_DONE", Const, 0, ""}, + {"PTRACE_GETCRUNCHREGS", Const, 0, ""}, + {"PTRACE_GETEVENTMSG", Const, 0, ""}, + {"PTRACE_GETFPREGS", Const, 0, ""}, + {"PTRACE_GETFPXREGS", Const, 0, ""}, + {"PTRACE_GETHBPREGS", Const, 0, ""}, + {"PTRACE_GETREGS", Const, 0, ""}, + {"PTRACE_GETREGSET", Const, 0, ""}, + {"PTRACE_GETSIGINFO", Const, 0, ""}, + {"PTRACE_GETVFPREGS", Const, 0, ""}, + {"PTRACE_GETWMMXREGS", Const, 0, ""}, + {"PTRACE_GET_THREAD_AREA", Const, 0, ""}, + {"PTRACE_KILL", Const, 0, ""}, + {"PTRACE_OLDSETOPTIONS", Const, 0, ""}, + {"PTRACE_O_MASK", Const, 0, ""}, + {"PTRACE_O_TRACECLONE", Const, 0, ""}, + {"PTRACE_O_TRACEEXEC", Const, 0, ""}, + {"PTRACE_O_TRACEEXIT", Const, 0, ""}, + {"PTRACE_O_TRACEFORK", Const, 0, ""}, + {"PTRACE_O_TRACESYSGOOD", Const, 0, ""}, + {"PTRACE_O_TRACEVFORK", Const, 0, ""}, + {"PTRACE_O_TRACEVFORKDONE", Const, 0, ""}, + {"PTRACE_PEEKDATA", Const, 0, ""}, + {"PTRACE_PEEKTEXT", Const, 0, ""}, + {"PTRACE_PEEKUSR", Const, 0, ""}, + {"PTRACE_POKEDATA", Const, 0, ""}, + {"PTRACE_POKETEXT", Const, 0, ""}, + {"PTRACE_POKEUSR", Const, 0, ""}, + {"PTRACE_SETCRUNCHREGS", Const, 0, ""}, + {"PTRACE_SETFPREGS", Const, 0, ""}, + {"PTRACE_SETFPXREGS", Const, 0, ""}, + {"PTRACE_SETHBPREGS", Const, 0, ""}, + {"PTRACE_SETOPTIONS", Const, 0, ""}, + {"PTRACE_SETREGS", Const, 0, ""}, + {"PTRACE_SETREGSET", Const, 0, ""}, + {"PTRACE_SETSIGINFO", Const, 0, ""}, + {"PTRACE_SETVFPREGS", Const, 0, ""}, + {"PTRACE_SETWMMXREGS", Const, 0, ""}, + {"PTRACE_SET_SYSCALL", Const, 0, ""}, + {"PTRACE_SET_THREAD_AREA", Const, 0, ""}, + {"PTRACE_SINGLEBLOCK", Const, 0, ""}, + {"PTRACE_SINGLESTEP", Const, 0, ""}, + {"PTRACE_SYSCALL", Const, 0, ""}, + {"PTRACE_SYSEMU", Const, 0, ""}, + {"PTRACE_SYSEMU_SINGLESTEP", Const, 0, ""}, + {"PTRACE_TRACEME", Const, 0, ""}, + {"PT_ATTACH", Const, 0, ""}, + {"PT_ATTACHEXC", Const, 0, ""}, + {"PT_CONTINUE", Const, 0, ""}, + {"PT_DATA_ADDR", Const, 0, ""}, + {"PT_DENY_ATTACH", Const, 0, ""}, + {"PT_DETACH", Const, 0, ""}, + {"PT_FIRSTMACH", Const, 0, ""}, + {"PT_FORCEQUOTA", Const, 0, ""}, + {"PT_KILL", Const, 0, ""}, + {"PT_MASK", Const, 1, ""}, + {"PT_READ_D", Const, 0, ""}, + {"PT_READ_I", Const, 0, ""}, + {"PT_READ_U", Const, 0, ""}, + {"PT_SIGEXC", Const, 0, ""}, + {"PT_STEP", Const, 0, ""}, + {"PT_TEXT_ADDR", Const, 0, ""}, + {"PT_TEXT_END_ADDR", Const, 0, ""}, + {"PT_THUPDATE", Const, 0, ""}, + {"PT_TRACE_ME", Const, 0, ""}, + {"PT_WRITE_D", Const, 0, ""}, + {"PT_WRITE_I", Const, 0, ""}, + {"PT_WRITE_U", Const, 0, ""}, + {"ParseDirent", Func, 0, "func(buf []byte, max int, names []string) (consumed int, count int, newnames []string)"}, + {"ParseNetlinkMessage", Func, 0, "func(b []byte) ([]NetlinkMessage, error)"}, + {"ParseNetlinkRouteAttr", Func, 0, "func(m *NetlinkMessage) ([]NetlinkRouteAttr, error)"}, + {"ParseRoutingMessage", Func, 0, ""}, + {"ParseRoutingSockaddr", Func, 0, ""}, + {"ParseSocketControlMessage", Func, 0, "func(b []byte) ([]SocketControlMessage, error)"}, + {"ParseUnixCredentials", Func, 0, "func(m *SocketControlMessage) (*Ucred, error)"}, + {"ParseUnixRights", Func, 0, "func(m *SocketControlMessage) ([]int, error)"}, + {"PathMax", Const, 0, ""}, + {"Pathconf", Func, 0, ""}, + {"Pause", Func, 0, "func() (err error)"}, + {"Pipe", Func, 0, "func(p []int) error"}, + {"Pipe2", Func, 1, "func(p []int, flags int) error"}, + {"PivotRoot", Func, 0, "func(newroot string, putold string) (err error)"}, + {"Pointer", Type, 11, ""}, + {"PostQueuedCompletionStatus", Func, 0, ""}, + {"Pread", Func, 0, "func(fd int, p []byte, offset int64) (n int, err error)"}, + {"Proc", Type, 0, ""}, + {"Proc.Dll", Field, 0, ""}, + {"Proc.Name", Field, 0, ""}, + {"ProcAttr", Type, 0, ""}, + {"ProcAttr.Dir", Field, 0, ""}, + {"ProcAttr.Env", Field, 0, ""}, + {"ProcAttr.Files", Field, 0, ""}, + {"ProcAttr.Sys", Field, 0, ""}, + {"Process32First", Func, 4, ""}, + {"Process32Next", Func, 4, ""}, + {"ProcessEntry32", Type, 4, ""}, + {"ProcessEntry32.DefaultHeapID", Field, 4, ""}, + {"ProcessEntry32.ExeFile", Field, 4, ""}, + {"ProcessEntry32.Flags", Field, 4, ""}, + {"ProcessEntry32.ModuleID", Field, 4, ""}, + {"ProcessEntry32.ParentProcessID", Field, 4, ""}, + {"ProcessEntry32.PriClassBase", Field, 4, ""}, + {"ProcessEntry32.ProcessID", Field, 4, ""}, + {"ProcessEntry32.Size", Field, 4, ""}, + {"ProcessEntry32.Threads", Field, 4, ""}, + {"ProcessEntry32.Usage", Field, 4, ""}, + {"ProcessInformation", Type, 0, ""}, + {"ProcessInformation.Process", Field, 0, ""}, + {"ProcessInformation.ProcessId", Field, 0, ""}, + {"ProcessInformation.Thread", Field, 0, ""}, + {"ProcessInformation.ThreadId", Field, 0, ""}, + {"Protoent", Type, 0, ""}, + {"Protoent.Aliases", Field, 0, ""}, + {"Protoent.Name", Field, 0, ""}, + {"Protoent.Proto", Field, 0, ""}, + {"PtraceAttach", Func, 0, "func(pid int) (err error)"}, + {"PtraceCont", Func, 0, "func(pid int, signal int) (err error)"}, + {"PtraceDetach", Func, 0, "func(pid int) (err error)"}, + {"PtraceGetEventMsg", Func, 0, "func(pid int) (msg uint, err error)"}, + {"PtraceGetRegs", Func, 0, "func(pid int, regsout *PtraceRegs) (err error)"}, + {"PtracePeekData", Func, 0, "func(pid int, addr uintptr, out []byte) (count int, err error)"}, + {"PtracePeekText", Func, 0, "func(pid int, addr uintptr, out []byte) (count int, err error)"}, + {"PtracePokeData", Func, 0, "func(pid int, addr uintptr, data []byte) (count int, err error)"}, + {"PtracePokeText", Func, 0, "func(pid int, addr uintptr, data []byte) (count int, err error)"}, + {"PtraceRegs", Type, 0, ""}, + {"PtraceRegs.Cs", Field, 0, ""}, + {"PtraceRegs.Ds", Field, 0, ""}, + {"PtraceRegs.Eax", Field, 0, ""}, + {"PtraceRegs.Ebp", Field, 0, ""}, + {"PtraceRegs.Ebx", Field, 0, ""}, + {"PtraceRegs.Ecx", Field, 0, ""}, + {"PtraceRegs.Edi", Field, 0, ""}, + {"PtraceRegs.Edx", Field, 0, ""}, + {"PtraceRegs.Eflags", Field, 0, ""}, + {"PtraceRegs.Eip", Field, 0, ""}, + {"PtraceRegs.Es", Field, 0, ""}, + {"PtraceRegs.Esi", Field, 0, ""}, + {"PtraceRegs.Esp", Field, 0, ""}, + {"PtraceRegs.Fs", Field, 0, ""}, + {"PtraceRegs.Fs_base", Field, 0, ""}, + {"PtraceRegs.Gs", Field, 0, ""}, + {"PtraceRegs.Gs_base", Field, 0, ""}, + {"PtraceRegs.Orig_eax", Field, 0, ""}, + {"PtraceRegs.Orig_rax", Field, 0, ""}, + {"PtraceRegs.R10", Field, 0, ""}, + {"PtraceRegs.R11", Field, 0, ""}, + {"PtraceRegs.R12", Field, 0, ""}, + {"PtraceRegs.R13", Field, 0, ""}, + {"PtraceRegs.R14", Field, 0, ""}, + {"PtraceRegs.R15", Field, 0, ""}, + {"PtraceRegs.R8", Field, 0, ""}, + {"PtraceRegs.R9", Field, 0, ""}, + {"PtraceRegs.Rax", Field, 0, ""}, + {"PtraceRegs.Rbp", Field, 0, ""}, + {"PtraceRegs.Rbx", Field, 0, ""}, + {"PtraceRegs.Rcx", Field, 0, ""}, + {"PtraceRegs.Rdi", Field, 0, ""}, + {"PtraceRegs.Rdx", Field, 0, ""}, + {"PtraceRegs.Rip", Field, 0, ""}, + {"PtraceRegs.Rsi", Field, 0, ""}, + {"PtraceRegs.Rsp", Field, 0, ""}, + {"PtraceRegs.Ss", Field, 0, ""}, + {"PtraceRegs.Uregs", Field, 0, ""}, + {"PtraceRegs.Xcs", Field, 0, ""}, + {"PtraceRegs.Xds", Field, 0, ""}, + {"PtraceRegs.Xes", Field, 0, ""}, + {"PtraceRegs.Xfs", Field, 0, ""}, + {"PtraceRegs.Xgs", Field, 0, ""}, + {"PtraceRegs.Xss", Field, 0, ""}, + {"PtraceSetOptions", Func, 0, "func(pid int, options int) (err error)"}, + {"PtraceSetRegs", Func, 0, "func(pid int, regs *PtraceRegs) (err error)"}, + {"PtraceSingleStep", Func, 0, "func(pid int) (err error)"}, + {"PtraceSyscall", Func, 1, "func(pid int, signal int) (err error)"}, + {"Pwrite", Func, 0, "func(fd int, p []byte, offset int64) (n int, err error)"}, + {"REG_BINARY", Const, 0, ""}, + {"REG_DWORD", Const, 0, ""}, + {"REG_DWORD_BIG_ENDIAN", Const, 0, ""}, + {"REG_DWORD_LITTLE_ENDIAN", Const, 0, ""}, + {"REG_EXPAND_SZ", Const, 0, ""}, + {"REG_FULL_RESOURCE_DESCRIPTOR", Const, 0, ""}, + {"REG_LINK", Const, 0, ""}, + {"REG_MULTI_SZ", Const, 0, ""}, + {"REG_NONE", Const, 0, ""}, + {"REG_QWORD", Const, 0, ""}, + {"REG_QWORD_LITTLE_ENDIAN", Const, 0, ""}, + {"REG_RESOURCE_LIST", Const, 0, ""}, + {"REG_RESOURCE_REQUIREMENTS_LIST", Const, 0, ""}, + {"REG_SZ", Const, 0, ""}, + {"RLIMIT_AS", Const, 0, ""}, + {"RLIMIT_CORE", Const, 0, ""}, + {"RLIMIT_CPU", Const, 0, ""}, + {"RLIMIT_CPU_USAGE_MONITOR", Const, 16, ""}, + {"RLIMIT_DATA", Const, 0, ""}, + {"RLIMIT_FSIZE", Const, 0, ""}, + {"RLIMIT_NOFILE", Const, 0, ""}, + {"RLIMIT_STACK", Const, 0, ""}, + {"RLIM_INFINITY", Const, 0, ""}, + {"RTAX_ADVMSS", Const, 0, ""}, + {"RTAX_AUTHOR", Const, 0, ""}, + {"RTAX_BRD", Const, 0, ""}, + {"RTAX_CWND", Const, 0, ""}, + {"RTAX_DST", Const, 0, ""}, + {"RTAX_FEATURES", Const, 0, ""}, + {"RTAX_FEATURE_ALLFRAG", Const, 0, ""}, + {"RTAX_FEATURE_ECN", Const, 0, ""}, + {"RTAX_FEATURE_SACK", Const, 0, ""}, + {"RTAX_FEATURE_TIMESTAMP", Const, 0, ""}, + {"RTAX_GATEWAY", Const, 0, ""}, + {"RTAX_GENMASK", Const, 0, ""}, + {"RTAX_HOPLIMIT", Const, 0, ""}, + {"RTAX_IFA", Const, 0, ""}, + {"RTAX_IFP", Const, 0, ""}, + {"RTAX_INITCWND", Const, 0, ""}, + {"RTAX_INITRWND", Const, 0, ""}, + {"RTAX_LABEL", Const, 1, ""}, + {"RTAX_LOCK", Const, 0, ""}, + {"RTAX_MAX", Const, 0, ""}, + {"RTAX_MTU", Const, 0, ""}, + {"RTAX_NETMASK", Const, 0, ""}, + {"RTAX_REORDERING", Const, 0, ""}, + {"RTAX_RTO_MIN", Const, 0, ""}, + {"RTAX_RTT", Const, 0, ""}, + {"RTAX_RTTVAR", Const, 0, ""}, + {"RTAX_SRC", Const, 1, ""}, + {"RTAX_SRCMASK", Const, 1, ""}, + {"RTAX_SSTHRESH", Const, 0, ""}, + {"RTAX_TAG", Const, 1, ""}, + {"RTAX_UNSPEC", Const, 0, ""}, + {"RTAX_WINDOW", Const, 0, ""}, + {"RTA_ALIGNTO", Const, 0, ""}, + {"RTA_AUTHOR", Const, 0, ""}, + {"RTA_BRD", Const, 0, ""}, + {"RTA_CACHEINFO", Const, 0, ""}, + {"RTA_DST", Const, 0, ""}, + {"RTA_FLOW", Const, 0, ""}, + {"RTA_GATEWAY", Const, 0, ""}, + {"RTA_GENMASK", Const, 0, ""}, + {"RTA_IFA", Const, 0, ""}, + {"RTA_IFP", Const, 0, ""}, + {"RTA_IIF", Const, 0, ""}, + {"RTA_LABEL", Const, 1, ""}, + {"RTA_MAX", Const, 0, ""}, + {"RTA_METRICS", Const, 0, ""}, + {"RTA_MULTIPATH", Const, 0, ""}, + {"RTA_NETMASK", Const, 0, ""}, + {"RTA_OIF", Const, 0, ""}, + {"RTA_PREFSRC", Const, 0, ""}, + {"RTA_PRIORITY", Const, 0, ""}, + {"RTA_SRC", Const, 0, ""}, + {"RTA_SRCMASK", Const, 1, ""}, + {"RTA_TABLE", Const, 0, ""}, + {"RTA_TAG", Const, 1, ""}, + {"RTA_UNSPEC", Const, 0, ""}, + {"RTCF_DIRECTSRC", Const, 0, ""}, + {"RTCF_DOREDIRECT", Const, 0, ""}, + {"RTCF_LOG", Const, 0, ""}, + {"RTCF_MASQ", Const, 0, ""}, + {"RTCF_NAT", Const, 0, ""}, + {"RTCF_VALVE", Const, 0, ""}, + {"RTF_ADDRCLASSMASK", Const, 0, ""}, + {"RTF_ADDRCONF", Const, 0, ""}, + {"RTF_ALLONLINK", Const, 0, ""}, + {"RTF_ANNOUNCE", Const, 1, ""}, + {"RTF_BLACKHOLE", Const, 0, ""}, + {"RTF_BROADCAST", Const, 0, ""}, + {"RTF_CACHE", Const, 0, ""}, + {"RTF_CLONED", Const, 1, ""}, + {"RTF_CLONING", Const, 0, ""}, + {"RTF_CONDEMNED", Const, 0, ""}, + {"RTF_DEFAULT", Const, 0, ""}, + {"RTF_DELCLONE", Const, 0, ""}, + {"RTF_DONE", Const, 0, ""}, + {"RTF_DYNAMIC", Const, 0, ""}, + {"RTF_FLOW", Const, 0, ""}, + {"RTF_FMASK", Const, 0, ""}, + {"RTF_GATEWAY", Const, 0, ""}, + {"RTF_GWFLAG_COMPAT", Const, 3, ""}, + {"RTF_HOST", Const, 0, ""}, + {"RTF_IFREF", Const, 0, ""}, + {"RTF_IFSCOPE", Const, 0, ""}, + {"RTF_INTERFACE", Const, 0, ""}, + {"RTF_IRTT", Const, 0, ""}, + {"RTF_LINKRT", Const, 0, ""}, + {"RTF_LLDATA", Const, 0, ""}, + {"RTF_LLINFO", Const, 0, ""}, + {"RTF_LOCAL", Const, 0, ""}, + {"RTF_MASK", Const, 1, ""}, + {"RTF_MODIFIED", Const, 0, ""}, + {"RTF_MPATH", Const, 1, ""}, + {"RTF_MPLS", Const, 1, ""}, + {"RTF_MSS", Const, 0, ""}, + {"RTF_MTU", Const, 0, ""}, + {"RTF_MULTICAST", Const, 0, ""}, + {"RTF_NAT", Const, 0, ""}, + {"RTF_NOFORWARD", Const, 0, ""}, + {"RTF_NONEXTHOP", Const, 0, ""}, + {"RTF_NOPMTUDISC", Const, 0, ""}, + {"RTF_PERMANENT_ARP", Const, 1, ""}, + {"RTF_PINNED", Const, 0, ""}, + {"RTF_POLICY", Const, 0, ""}, + {"RTF_PRCLONING", Const, 0, ""}, + {"RTF_PROTO1", Const, 0, ""}, + {"RTF_PROTO2", Const, 0, ""}, + {"RTF_PROTO3", Const, 0, ""}, + {"RTF_PROXY", Const, 16, ""}, + {"RTF_REINSTATE", Const, 0, ""}, + {"RTF_REJECT", Const, 0, ""}, + {"RTF_RNH_LOCKED", Const, 0, ""}, + {"RTF_ROUTER", Const, 16, ""}, + {"RTF_SOURCE", Const, 1, ""}, + {"RTF_SRC", Const, 1, ""}, + {"RTF_STATIC", Const, 0, ""}, + {"RTF_STICKY", Const, 0, ""}, + {"RTF_THROW", Const, 0, ""}, + {"RTF_TUNNEL", Const, 1, ""}, + {"RTF_UP", Const, 0, ""}, + {"RTF_USETRAILERS", Const, 1, ""}, + {"RTF_WASCLONED", Const, 0, ""}, + {"RTF_WINDOW", Const, 0, ""}, + {"RTF_XRESOLVE", Const, 0, ""}, + {"RTM_ADD", Const, 0, ""}, + {"RTM_BASE", Const, 0, ""}, + {"RTM_CHANGE", Const, 0, ""}, + {"RTM_CHGADDR", Const, 1, ""}, + {"RTM_DELACTION", Const, 0, ""}, + {"RTM_DELADDR", Const, 0, ""}, + {"RTM_DELADDRLABEL", Const, 0, ""}, + {"RTM_DELETE", Const, 0, ""}, + {"RTM_DELLINK", Const, 0, ""}, + {"RTM_DELMADDR", Const, 0, ""}, + {"RTM_DELNEIGH", Const, 0, ""}, + {"RTM_DELQDISC", Const, 0, ""}, + {"RTM_DELROUTE", Const, 0, ""}, + {"RTM_DELRULE", Const, 0, ""}, + {"RTM_DELTCLASS", Const, 0, ""}, + {"RTM_DELTFILTER", Const, 0, ""}, + {"RTM_DESYNC", Const, 1, ""}, + {"RTM_F_CLONED", Const, 0, ""}, + {"RTM_F_EQUALIZE", Const, 0, ""}, + {"RTM_F_NOTIFY", Const, 0, ""}, + {"RTM_F_PREFIX", Const, 0, ""}, + {"RTM_GET", Const, 0, ""}, + {"RTM_GET2", Const, 0, ""}, + {"RTM_GETACTION", Const, 0, ""}, + {"RTM_GETADDR", Const, 0, ""}, + {"RTM_GETADDRLABEL", Const, 0, ""}, + {"RTM_GETANYCAST", Const, 0, ""}, + {"RTM_GETDCB", Const, 0, ""}, + {"RTM_GETLINK", Const, 0, ""}, + {"RTM_GETMULTICAST", Const, 0, ""}, + {"RTM_GETNEIGH", Const, 0, ""}, + {"RTM_GETNEIGHTBL", Const, 0, ""}, + {"RTM_GETQDISC", Const, 0, ""}, + {"RTM_GETROUTE", Const, 0, ""}, + {"RTM_GETRULE", Const, 0, ""}, + {"RTM_GETTCLASS", Const, 0, ""}, + {"RTM_GETTFILTER", Const, 0, ""}, + {"RTM_IEEE80211", Const, 0, ""}, + {"RTM_IFANNOUNCE", Const, 0, ""}, + {"RTM_IFINFO", Const, 0, ""}, + {"RTM_IFINFO2", Const, 0, ""}, + {"RTM_LLINFO_UPD", Const, 1, ""}, + {"RTM_LOCK", Const, 0, ""}, + {"RTM_LOSING", Const, 0, ""}, + {"RTM_MAX", Const, 0, ""}, + {"RTM_MAXSIZE", Const, 1, ""}, + {"RTM_MISS", Const, 0, ""}, + {"RTM_NEWACTION", Const, 0, ""}, + {"RTM_NEWADDR", Const, 0, ""}, + {"RTM_NEWADDRLABEL", Const, 0, ""}, + {"RTM_NEWLINK", Const, 0, ""}, + {"RTM_NEWMADDR", Const, 0, ""}, + {"RTM_NEWMADDR2", Const, 0, ""}, + {"RTM_NEWNDUSEROPT", Const, 0, ""}, + {"RTM_NEWNEIGH", Const, 0, ""}, + {"RTM_NEWNEIGHTBL", Const, 0, ""}, + {"RTM_NEWPREFIX", Const, 0, ""}, + {"RTM_NEWQDISC", Const, 0, ""}, + {"RTM_NEWROUTE", Const, 0, ""}, + {"RTM_NEWRULE", Const, 0, ""}, + {"RTM_NEWTCLASS", Const, 0, ""}, + {"RTM_NEWTFILTER", Const, 0, ""}, + {"RTM_NR_FAMILIES", Const, 0, ""}, + {"RTM_NR_MSGTYPES", Const, 0, ""}, + {"RTM_OIFINFO", Const, 1, ""}, + {"RTM_OLDADD", Const, 0, ""}, + {"RTM_OLDDEL", Const, 0, ""}, + {"RTM_OOIFINFO", Const, 1, ""}, + {"RTM_REDIRECT", Const, 0, ""}, + {"RTM_RESOLVE", Const, 0, ""}, + {"RTM_RTTUNIT", Const, 0, ""}, + {"RTM_SETDCB", Const, 0, ""}, + {"RTM_SETGATE", Const, 1, ""}, + {"RTM_SETLINK", Const, 0, ""}, + {"RTM_SETNEIGHTBL", Const, 0, ""}, + {"RTM_VERSION", Const, 0, ""}, + {"RTNH_ALIGNTO", Const, 0, ""}, + {"RTNH_F_DEAD", Const, 0, ""}, + {"RTNH_F_ONLINK", Const, 0, ""}, + {"RTNH_F_PERVASIVE", Const, 0, ""}, + {"RTNLGRP_IPV4_IFADDR", Const, 1, ""}, + {"RTNLGRP_IPV4_MROUTE", Const, 1, ""}, + {"RTNLGRP_IPV4_ROUTE", Const, 1, ""}, + {"RTNLGRP_IPV4_RULE", Const, 1, ""}, + {"RTNLGRP_IPV6_IFADDR", Const, 1, ""}, + {"RTNLGRP_IPV6_IFINFO", Const, 1, ""}, + {"RTNLGRP_IPV6_MROUTE", Const, 1, ""}, + {"RTNLGRP_IPV6_PREFIX", Const, 1, ""}, + {"RTNLGRP_IPV6_ROUTE", Const, 1, ""}, + {"RTNLGRP_IPV6_RULE", Const, 1, ""}, + {"RTNLGRP_LINK", Const, 1, ""}, + {"RTNLGRP_ND_USEROPT", Const, 1, ""}, + {"RTNLGRP_NEIGH", Const, 1, ""}, + {"RTNLGRP_NONE", Const, 1, ""}, + {"RTNLGRP_NOTIFY", Const, 1, ""}, + {"RTNLGRP_TC", Const, 1, ""}, + {"RTN_ANYCAST", Const, 0, ""}, + {"RTN_BLACKHOLE", Const, 0, ""}, + {"RTN_BROADCAST", Const, 0, ""}, + {"RTN_LOCAL", Const, 0, ""}, + {"RTN_MAX", Const, 0, ""}, + {"RTN_MULTICAST", Const, 0, ""}, + {"RTN_NAT", Const, 0, ""}, + {"RTN_PROHIBIT", Const, 0, ""}, + {"RTN_THROW", Const, 0, ""}, + {"RTN_UNICAST", Const, 0, ""}, + {"RTN_UNREACHABLE", Const, 0, ""}, + {"RTN_UNSPEC", Const, 0, ""}, + {"RTN_XRESOLVE", Const, 0, ""}, + {"RTPROT_BIRD", Const, 0, ""}, + {"RTPROT_BOOT", Const, 0, ""}, + {"RTPROT_DHCP", Const, 0, ""}, + {"RTPROT_DNROUTED", Const, 0, ""}, + {"RTPROT_GATED", Const, 0, ""}, + {"RTPROT_KERNEL", Const, 0, ""}, + {"RTPROT_MRT", Const, 0, ""}, + {"RTPROT_NTK", Const, 0, ""}, + {"RTPROT_RA", Const, 0, ""}, + {"RTPROT_REDIRECT", Const, 0, ""}, + {"RTPROT_STATIC", Const, 0, ""}, + {"RTPROT_UNSPEC", Const, 0, ""}, + {"RTPROT_XORP", Const, 0, ""}, + {"RTPROT_ZEBRA", Const, 0, ""}, + {"RTV_EXPIRE", Const, 0, ""}, + {"RTV_HOPCOUNT", Const, 0, ""}, + {"RTV_MTU", Const, 0, ""}, + {"RTV_RPIPE", Const, 0, ""}, + {"RTV_RTT", Const, 0, ""}, + {"RTV_RTTVAR", Const, 0, ""}, + {"RTV_SPIPE", Const, 0, ""}, + {"RTV_SSTHRESH", Const, 0, ""}, + {"RTV_WEIGHT", Const, 0, ""}, + {"RT_CACHING_CONTEXT", Const, 1, ""}, + {"RT_CLASS_DEFAULT", Const, 0, ""}, + {"RT_CLASS_LOCAL", Const, 0, ""}, + {"RT_CLASS_MAIN", Const, 0, ""}, + {"RT_CLASS_MAX", Const, 0, ""}, + {"RT_CLASS_UNSPEC", Const, 0, ""}, + {"RT_DEFAULT_FIB", Const, 1, ""}, + {"RT_NORTREF", Const, 1, ""}, + {"RT_SCOPE_HOST", Const, 0, ""}, + {"RT_SCOPE_LINK", Const, 0, ""}, + {"RT_SCOPE_NOWHERE", Const, 0, ""}, + {"RT_SCOPE_SITE", Const, 0, ""}, + {"RT_SCOPE_UNIVERSE", Const, 0, ""}, + {"RT_TABLEID_MAX", Const, 1, ""}, + {"RT_TABLE_COMPAT", Const, 0, ""}, + {"RT_TABLE_DEFAULT", Const, 0, ""}, + {"RT_TABLE_LOCAL", Const, 0, ""}, + {"RT_TABLE_MAIN", Const, 0, ""}, + {"RT_TABLE_MAX", Const, 0, ""}, + {"RT_TABLE_UNSPEC", Const, 0, ""}, + {"RUSAGE_CHILDREN", Const, 0, ""}, + {"RUSAGE_SELF", Const, 0, ""}, + {"RUSAGE_THREAD", Const, 0, ""}, + {"Radvisory_t", Type, 0, ""}, + {"Radvisory_t.Count", Field, 0, ""}, + {"Radvisory_t.Offset", Field, 0, ""}, + {"Radvisory_t.Pad_cgo_0", Field, 0, ""}, + {"RawConn", Type, 9, ""}, + {"RawSockaddr", Type, 0, ""}, + {"RawSockaddr.Data", Field, 0, ""}, + {"RawSockaddr.Family", Field, 0, ""}, + {"RawSockaddr.Len", Field, 0, ""}, + {"RawSockaddrAny", Type, 0, ""}, + {"RawSockaddrAny.Addr", Field, 0, ""}, + {"RawSockaddrAny.Pad", Field, 0, ""}, + {"RawSockaddrDatalink", Type, 0, ""}, + {"RawSockaddrDatalink.Alen", Field, 0, ""}, + {"RawSockaddrDatalink.Data", Field, 0, ""}, + {"RawSockaddrDatalink.Family", Field, 0, ""}, + {"RawSockaddrDatalink.Index", Field, 0, ""}, + {"RawSockaddrDatalink.Len", Field, 0, ""}, + {"RawSockaddrDatalink.Nlen", Field, 0, ""}, + {"RawSockaddrDatalink.Pad_cgo_0", Field, 2, ""}, + {"RawSockaddrDatalink.Slen", Field, 0, ""}, + {"RawSockaddrDatalink.Type", Field, 0, ""}, + {"RawSockaddrInet4", Type, 0, ""}, + {"RawSockaddrInet4.Addr", Field, 0, ""}, + {"RawSockaddrInet4.Family", Field, 0, ""}, + {"RawSockaddrInet4.Len", Field, 0, ""}, + {"RawSockaddrInet4.Port", Field, 0, ""}, + {"RawSockaddrInet4.Zero", Field, 0, ""}, + {"RawSockaddrInet6", Type, 0, ""}, + {"RawSockaddrInet6.Addr", Field, 0, ""}, + {"RawSockaddrInet6.Family", Field, 0, ""}, + {"RawSockaddrInet6.Flowinfo", Field, 0, ""}, + {"RawSockaddrInet6.Len", Field, 0, ""}, + {"RawSockaddrInet6.Port", Field, 0, ""}, + {"RawSockaddrInet6.Scope_id", Field, 0, ""}, + {"RawSockaddrLinklayer", Type, 0, ""}, + {"RawSockaddrLinklayer.Addr", Field, 0, ""}, + {"RawSockaddrLinklayer.Family", Field, 0, ""}, + {"RawSockaddrLinklayer.Halen", Field, 0, ""}, + {"RawSockaddrLinklayer.Hatype", Field, 0, ""}, + {"RawSockaddrLinklayer.Ifindex", Field, 0, ""}, + {"RawSockaddrLinklayer.Pkttype", Field, 0, ""}, + {"RawSockaddrLinklayer.Protocol", Field, 0, ""}, + {"RawSockaddrNetlink", Type, 0, ""}, + {"RawSockaddrNetlink.Family", Field, 0, ""}, + {"RawSockaddrNetlink.Groups", Field, 0, ""}, + {"RawSockaddrNetlink.Pad", Field, 0, ""}, + {"RawSockaddrNetlink.Pid", Field, 0, ""}, + {"RawSockaddrUnix", Type, 0, ""}, + {"RawSockaddrUnix.Family", Field, 0, ""}, + {"RawSockaddrUnix.Len", Field, 0, ""}, + {"RawSockaddrUnix.Pad_cgo_0", Field, 2, ""}, + {"RawSockaddrUnix.Path", Field, 0, ""}, + {"RawSyscall", Func, 0, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, + {"RawSyscall6", Func, 0, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr, a4 uintptr, a5 uintptr, a6 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, + {"Read", Func, 0, "func(fd int, p []byte) (n int, err error)"}, + {"ReadConsole", Func, 1, ""}, + {"ReadDirectoryChanges", Func, 0, ""}, + {"ReadDirent", Func, 0, "func(fd int, buf []byte) (n int, err error)"}, + {"ReadFile", Func, 0, ""}, + {"Readlink", Func, 0, "func(path string, buf []byte) (n int, err error)"}, + {"Reboot", Func, 0, "func(cmd int) (err error)"}, + {"Recvfrom", Func, 0, "func(fd int, p []byte, flags int) (n int, from Sockaddr, err error)"}, + {"Recvmsg", Func, 0, "func(fd int, p []byte, oob []byte, flags int) (n int, oobn int, recvflags int, from Sockaddr, err error)"}, + {"RegCloseKey", Func, 0, ""}, + {"RegEnumKeyEx", Func, 0, ""}, + {"RegOpenKeyEx", Func, 0, ""}, + {"RegQueryInfoKey", Func, 0, ""}, + {"RegQueryValueEx", Func, 0, ""}, + {"RemoveDirectory", Func, 0, ""}, + {"Removexattr", Func, 1, "func(path string, attr string) (err error)"}, + {"Rename", Func, 0, "func(oldpath string, newpath string) (err error)"}, + {"Renameat", Func, 0, "func(olddirfd int, oldpath string, newdirfd int, newpath string) (err error)"}, + {"Revoke", Func, 0, ""}, + {"Rlimit", Type, 0, ""}, + {"Rlimit.Cur", Field, 0, ""}, + {"Rlimit.Max", Field, 0, ""}, + {"Rmdir", Func, 0, "func(path string) error"}, + {"RouteMessage", Type, 0, ""}, + {"RouteMessage.Data", Field, 0, ""}, + {"RouteMessage.Header", Field, 0, ""}, + {"RouteRIB", Func, 0, ""}, + {"RoutingMessage", Type, 0, ""}, + {"RtAttr", Type, 0, ""}, + {"RtAttr.Len", Field, 0, ""}, + {"RtAttr.Type", Field, 0, ""}, + {"RtGenmsg", Type, 0, ""}, + {"RtGenmsg.Family", Field, 0, ""}, + {"RtMetrics", Type, 0, ""}, + {"RtMetrics.Expire", Field, 0, ""}, + {"RtMetrics.Filler", Field, 0, ""}, + {"RtMetrics.Hopcount", Field, 0, ""}, + {"RtMetrics.Locks", Field, 0, ""}, + {"RtMetrics.Mtu", Field, 0, ""}, + {"RtMetrics.Pad", Field, 3, ""}, + {"RtMetrics.Pksent", Field, 0, ""}, + {"RtMetrics.Recvpipe", Field, 0, ""}, + {"RtMetrics.Refcnt", Field, 2, ""}, + {"RtMetrics.Rtt", Field, 0, ""}, + {"RtMetrics.Rttvar", Field, 0, ""}, + {"RtMetrics.Sendpipe", Field, 0, ""}, + {"RtMetrics.Ssthresh", Field, 0, ""}, + {"RtMetrics.Weight", Field, 0, ""}, + {"RtMsg", Type, 0, ""}, + {"RtMsg.Dst_len", Field, 0, ""}, + {"RtMsg.Family", Field, 0, ""}, + {"RtMsg.Flags", Field, 0, ""}, + {"RtMsg.Protocol", Field, 0, ""}, + {"RtMsg.Scope", Field, 0, ""}, + {"RtMsg.Src_len", Field, 0, ""}, + {"RtMsg.Table", Field, 0, ""}, + {"RtMsg.Tos", Field, 0, ""}, + {"RtMsg.Type", Field, 0, ""}, + {"RtMsghdr", Type, 0, ""}, + {"RtMsghdr.Addrs", Field, 0, ""}, + {"RtMsghdr.Errno", Field, 0, ""}, + {"RtMsghdr.Flags", Field, 0, ""}, + {"RtMsghdr.Fmask", Field, 0, ""}, + {"RtMsghdr.Hdrlen", Field, 2, ""}, + {"RtMsghdr.Index", Field, 0, ""}, + {"RtMsghdr.Inits", Field, 0, ""}, + {"RtMsghdr.Mpls", Field, 2, ""}, + {"RtMsghdr.Msglen", Field, 0, ""}, + {"RtMsghdr.Pad_cgo_0", Field, 0, ""}, + {"RtMsghdr.Pad_cgo_1", Field, 2, ""}, + {"RtMsghdr.Pid", Field, 0, ""}, + {"RtMsghdr.Priority", Field, 2, ""}, + {"RtMsghdr.Rmx", Field, 0, ""}, + {"RtMsghdr.Seq", Field, 0, ""}, + {"RtMsghdr.Tableid", Field, 2, ""}, + {"RtMsghdr.Type", Field, 0, ""}, + {"RtMsghdr.Use", Field, 0, ""}, + {"RtMsghdr.Version", Field, 0, ""}, + {"RtNexthop", Type, 0, ""}, + {"RtNexthop.Flags", Field, 0, ""}, + {"RtNexthop.Hops", Field, 0, ""}, + {"RtNexthop.Ifindex", Field, 0, ""}, + {"RtNexthop.Len", Field, 0, ""}, + {"Rusage", Type, 0, ""}, + {"Rusage.CreationTime", Field, 0, ""}, + {"Rusage.ExitTime", Field, 0, ""}, + {"Rusage.Idrss", Field, 0, ""}, + {"Rusage.Inblock", Field, 0, ""}, + {"Rusage.Isrss", Field, 0, ""}, + {"Rusage.Ixrss", Field, 0, ""}, + {"Rusage.KernelTime", Field, 0, ""}, + {"Rusage.Majflt", Field, 0, ""}, + {"Rusage.Maxrss", Field, 0, ""}, + {"Rusage.Minflt", Field, 0, ""}, + {"Rusage.Msgrcv", Field, 0, ""}, + {"Rusage.Msgsnd", Field, 0, ""}, + {"Rusage.Nivcsw", Field, 0, ""}, + {"Rusage.Nsignals", Field, 0, ""}, + {"Rusage.Nswap", Field, 0, ""}, + {"Rusage.Nvcsw", Field, 0, ""}, + {"Rusage.Oublock", Field, 0, ""}, + {"Rusage.Stime", Field, 0, ""}, + {"Rusage.UserTime", Field, 0, ""}, + {"Rusage.Utime", Field, 0, ""}, + {"SCM_BINTIME", Const, 0, ""}, + {"SCM_CREDENTIALS", Const, 0, ""}, + {"SCM_CREDS", Const, 0, ""}, + {"SCM_RIGHTS", Const, 0, ""}, + {"SCM_TIMESTAMP", Const, 0, ""}, + {"SCM_TIMESTAMPING", Const, 0, ""}, + {"SCM_TIMESTAMPNS", Const, 0, ""}, + {"SCM_TIMESTAMP_MONOTONIC", Const, 0, ""}, + {"SHUT_RD", Const, 0, ""}, + {"SHUT_RDWR", Const, 0, ""}, + {"SHUT_WR", Const, 0, ""}, + {"SID", Type, 0, ""}, + {"SIDAndAttributes", Type, 0, ""}, + {"SIDAndAttributes.Attributes", Field, 0, ""}, + {"SIDAndAttributes.Sid", Field, 0, ""}, + {"SIGABRT", Const, 0, ""}, + {"SIGALRM", Const, 0, ""}, + {"SIGBUS", Const, 0, ""}, + {"SIGCHLD", Const, 0, ""}, + {"SIGCLD", Const, 0, ""}, + {"SIGCONT", Const, 0, ""}, + {"SIGEMT", Const, 0, ""}, + {"SIGFPE", Const, 0, ""}, + {"SIGHUP", Const, 0, ""}, + {"SIGILL", Const, 0, ""}, + {"SIGINFO", Const, 0, ""}, + {"SIGINT", Const, 0, ""}, + {"SIGIO", Const, 0, ""}, + {"SIGIOT", Const, 0, ""}, + {"SIGKILL", Const, 0, ""}, + {"SIGLIBRT", Const, 1, ""}, + {"SIGLWP", Const, 0, ""}, + {"SIGPIPE", Const, 0, ""}, + {"SIGPOLL", Const, 0, ""}, + {"SIGPROF", Const, 0, ""}, + {"SIGPWR", Const, 0, ""}, + {"SIGQUIT", Const, 0, ""}, + {"SIGSEGV", Const, 0, ""}, + {"SIGSTKFLT", Const, 0, ""}, + {"SIGSTOP", Const, 0, ""}, + {"SIGSYS", Const, 0, ""}, + {"SIGTERM", Const, 0, ""}, + {"SIGTHR", Const, 0, ""}, + {"SIGTRAP", Const, 0, ""}, + {"SIGTSTP", Const, 0, ""}, + {"SIGTTIN", Const, 0, ""}, + {"SIGTTOU", Const, 0, ""}, + {"SIGUNUSED", Const, 0, ""}, + {"SIGURG", Const, 0, ""}, + {"SIGUSR1", Const, 0, ""}, + {"SIGUSR2", Const, 0, ""}, + {"SIGVTALRM", Const, 0, ""}, + {"SIGWINCH", Const, 0, ""}, + {"SIGXCPU", Const, 0, ""}, + {"SIGXFSZ", Const, 0, ""}, + {"SIOCADDDLCI", Const, 0, ""}, + {"SIOCADDMULTI", Const, 0, ""}, + {"SIOCADDRT", Const, 0, ""}, + {"SIOCAIFADDR", Const, 0, ""}, + {"SIOCAIFGROUP", Const, 0, ""}, + {"SIOCALIFADDR", Const, 0, ""}, + {"SIOCARPIPLL", Const, 0, ""}, + {"SIOCATMARK", Const, 0, ""}, + {"SIOCAUTOADDR", Const, 0, ""}, + {"SIOCAUTONETMASK", Const, 0, ""}, + {"SIOCBRDGADD", Const, 1, ""}, + {"SIOCBRDGADDS", Const, 1, ""}, + {"SIOCBRDGARL", Const, 1, ""}, + {"SIOCBRDGDADDR", Const, 1, ""}, + {"SIOCBRDGDEL", Const, 1, ""}, + {"SIOCBRDGDELS", Const, 1, ""}, + {"SIOCBRDGFLUSH", Const, 1, ""}, + {"SIOCBRDGFRL", Const, 1, ""}, + {"SIOCBRDGGCACHE", Const, 1, ""}, + {"SIOCBRDGGFD", Const, 1, ""}, + {"SIOCBRDGGHT", Const, 1, ""}, + {"SIOCBRDGGIFFLGS", Const, 1, ""}, + {"SIOCBRDGGMA", Const, 1, ""}, + {"SIOCBRDGGPARAM", Const, 1, ""}, + {"SIOCBRDGGPRI", Const, 1, ""}, + {"SIOCBRDGGRL", Const, 1, ""}, + {"SIOCBRDGGSIFS", Const, 1, ""}, + {"SIOCBRDGGTO", Const, 1, ""}, + {"SIOCBRDGIFS", Const, 1, ""}, + {"SIOCBRDGRTS", Const, 1, ""}, + {"SIOCBRDGSADDR", Const, 1, ""}, + {"SIOCBRDGSCACHE", Const, 1, ""}, + {"SIOCBRDGSFD", Const, 1, ""}, + {"SIOCBRDGSHT", Const, 1, ""}, + {"SIOCBRDGSIFCOST", Const, 1, ""}, + {"SIOCBRDGSIFFLGS", Const, 1, ""}, + {"SIOCBRDGSIFPRIO", Const, 1, ""}, + {"SIOCBRDGSMA", Const, 1, ""}, + {"SIOCBRDGSPRI", Const, 1, ""}, + {"SIOCBRDGSPROTO", Const, 1, ""}, + {"SIOCBRDGSTO", Const, 1, ""}, + {"SIOCBRDGSTXHC", Const, 1, ""}, + {"SIOCDARP", Const, 0, ""}, + {"SIOCDELDLCI", Const, 0, ""}, + {"SIOCDELMULTI", Const, 0, ""}, + {"SIOCDELRT", Const, 0, ""}, + {"SIOCDEVPRIVATE", Const, 0, ""}, + {"SIOCDIFADDR", Const, 0, ""}, + {"SIOCDIFGROUP", Const, 0, ""}, + {"SIOCDIFPHYADDR", Const, 0, ""}, + {"SIOCDLIFADDR", Const, 0, ""}, + {"SIOCDRARP", Const, 0, ""}, + {"SIOCGARP", Const, 0, ""}, + {"SIOCGDRVSPEC", Const, 0, ""}, + {"SIOCGETKALIVE", Const, 1, ""}, + {"SIOCGETLABEL", Const, 1, ""}, + {"SIOCGETPFLOW", Const, 1, ""}, + {"SIOCGETPFSYNC", Const, 1, ""}, + {"SIOCGETSGCNT", Const, 0, ""}, + {"SIOCGETVIFCNT", Const, 0, ""}, + {"SIOCGETVLAN", Const, 0, ""}, + {"SIOCGHIWAT", Const, 0, ""}, + {"SIOCGIFADDR", Const, 0, ""}, + {"SIOCGIFADDRPREF", Const, 1, ""}, + {"SIOCGIFALIAS", Const, 1, ""}, + {"SIOCGIFALTMTU", Const, 0, ""}, + {"SIOCGIFASYNCMAP", Const, 0, ""}, + {"SIOCGIFBOND", Const, 0, ""}, + {"SIOCGIFBR", Const, 0, ""}, + {"SIOCGIFBRDADDR", Const, 0, ""}, + {"SIOCGIFCAP", Const, 0, ""}, + {"SIOCGIFCONF", Const, 0, ""}, + {"SIOCGIFCOUNT", Const, 0, ""}, + {"SIOCGIFDATA", Const, 1, ""}, + {"SIOCGIFDESCR", Const, 0, ""}, + {"SIOCGIFDEVMTU", Const, 0, ""}, + {"SIOCGIFDLT", Const, 1, ""}, + {"SIOCGIFDSTADDR", Const, 0, ""}, + {"SIOCGIFENCAP", Const, 0, ""}, + {"SIOCGIFFIB", Const, 1, ""}, + {"SIOCGIFFLAGS", Const, 0, ""}, + {"SIOCGIFGATTR", Const, 1, ""}, + {"SIOCGIFGENERIC", Const, 0, ""}, + {"SIOCGIFGMEMB", Const, 0, ""}, + {"SIOCGIFGROUP", Const, 0, ""}, + {"SIOCGIFHARDMTU", Const, 3, ""}, + {"SIOCGIFHWADDR", Const, 0, ""}, + {"SIOCGIFINDEX", Const, 0, ""}, + {"SIOCGIFKPI", Const, 0, ""}, + {"SIOCGIFMAC", Const, 0, ""}, + {"SIOCGIFMAP", Const, 0, ""}, + {"SIOCGIFMEDIA", Const, 0, ""}, + {"SIOCGIFMEM", Const, 0, ""}, + {"SIOCGIFMETRIC", Const, 0, ""}, + {"SIOCGIFMTU", Const, 0, ""}, + {"SIOCGIFNAME", Const, 0, ""}, + {"SIOCGIFNETMASK", Const, 0, ""}, + {"SIOCGIFPDSTADDR", Const, 0, ""}, + {"SIOCGIFPFLAGS", Const, 0, ""}, + {"SIOCGIFPHYS", Const, 0, ""}, + {"SIOCGIFPRIORITY", Const, 1, ""}, + {"SIOCGIFPSRCADDR", Const, 0, ""}, + {"SIOCGIFRDOMAIN", Const, 1, ""}, + {"SIOCGIFRTLABEL", Const, 1, ""}, + {"SIOCGIFSLAVE", Const, 0, ""}, + {"SIOCGIFSTATUS", Const, 0, ""}, + {"SIOCGIFTIMESLOT", Const, 1, ""}, + {"SIOCGIFTXQLEN", Const, 0, ""}, + {"SIOCGIFVLAN", Const, 0, ""}, + {"SIOCGIFWAKEFLAGS", Const, 0, ""}, + {"SIOCGIFXFLAGS", Const, 1, ""}, + {"SIOCGLIFADDR", Const, 0, ""}, + {"SIOCGLIFPHYADDR", Const, 0, ""}, + {"SIOCGLIFPHYRTABLE", Const, 1, ""}, + {"SIOCGLIFPHYTTL", Const, 3, ""}, + {"SIOCGLINKSTR", Const, 1, ""}, + {"SIOCGLOWAT", Const, 0, ""}, + {"SIOCGPGRP", Const, 0, ""}, + {"SIOCGPRIVATE_0", Const, 0, ""}, + {"SIOCGPRIVATE_1", Const, 0, ""}, + {"SIOCGRARP", Const, 0, ""}, + {"SIOCGSPPPPARAMS", Const, 3, ""}, + {"SIOCGSTAMP", Const, 0, ""}, + {"SIOCGSTAMPNS", Const, 0, ""}, + {"SIOCGVH", Const, 1, ""}, + {"SIOCGVNETID", Const, 3, ""}, + {"SIOCIFCREATE", Const, 0, ""}, + {"SIOCIFCREATE2", Const, 0, ""}, + {"SIOCIFDESTROY", Const, 0, ""}, + {"SIOCIFGCLONERS", Const, 0, ""}, + {"SIOCINITIFADDR", Const, 1, ""}, + {"SIOCPROTOPRIVATE", Const, 0, ""}, + {"SIOCRSLVMULTI", Const, 0, ""}, + {"SIOCRTMSG", Const, 0, ""}, + {"SIOCSARP", Const, 0, ""}, + {"SIOCSDRVSPEC", Const, 0, ""}, + {"SIOCSETKALIVE", Const, 1, ""}, + {"SIOCSETLABEL", Const, 1, ""}, + {"SIOCSETPFLOW", Const, 1, ""}, + {"SIOCSETPFSYNC", Const, 1, ""}, + {"SIOCSETVLAN", Const, 0, ""}, + {"SIOCSHIWAT", Const, 0, ""}, + {"SIOCSIFADDR", Const, 0, ""}, + {"SIOCSIFADDRPREF", Const, 1, ""}, + {"SIOCSIFALTMTU", Const, 0, ""}, + {"SIOCSIFASYNCMAP", Const, 0, ""}, + {"SIOCSIFBOND", Const, 0, ""}, + {"SIOCSIFBR", Const, 0, ""}, + {"SIOCSIFBRDADDR", Const, 0, ""}, + {"SIOCSIFCAP", Const, 0, ""}, + {"SIOCSIFDESCR", Const, 0, ""}, + {"SIOCSIFDSTADDR", Const, 0, ""}, + {"SIOCSIFENCAP", Const, 0, ""}, + {"SIOCSIFFIB", Const, 1, ""}, + {"SIOCSIFFLAGS", Const, 0, ""}, + {"SIOCSIFGATTR", Const, 1, ""}, + {"SIOCSIFGENERIC", Const, 0, ""}, + {"SIOCSIFHWADDR", Const, 0, ""}, + {"SIOCSIFHWBROADCAST", Const, 0, ""}, + {"SIOCSIFKPI", Const, 0, ""}, + {"SIOCSIFLINK", Const, 0, ""}, + {"SIOCSIFLLADDR", Const, 0, ""}, + {"SIOCSIFMAC", Const, 0, ""}, + {"SIOCSIFMAP", Const, 0, ""}, + {"SIOCSIFMEDIA", Const, 0, ""}, + {"SIOCSIFMEM", Const, 0, ""}, + {"SIOCSIFMETRIC", Const, 0, ""}, + {"SIOCSIFMTU", Const, 0, ""}, + {"SIOCSIFNAME", Const, 0, ""}, + {"SIOCSIFNETMASK", Const, 0, ""}, + {"SIOCSIFPFLAGS", Const, 0, ""}, + {"SIOCSIFPHYADDR", Const, 0, ""}, + {"SIOCSIFPHYS", Const, 0, ""}, + {"SIOCSIFPRIORITY", Const, 1, ""}, + {"SIOCSIFRDOMAIN", Const, 1, ""}, + {"SIOCSIFRTLABEL", Const, 1, ""}, + {"SIOCSIFRVNET", Const, 0, ""}, + {"SIOCSIFSLAVE", Const, 0, ""}, + {"SIOCSIFTIMESLOT", Const, 1, ""}, + {"SIOCSIFTXQLEN", Const, 0, ""}, + {"SIOCSIFVLAN", Const, 0, ""}, + {"SIOCSIFVNET", Const, 0, ""}, + {"SIOCSIFXFLAGS", Const, 1, ""}, + {"SIOCSLIFPHYADDR", Const, 0, ""}, + {"SIOCSLIFPHYRTABLE", Const, 1, ""}, + {"SIOCSLIFPHYTTL", Const, 3, ""}, + {"SIOCSLINKSTR", Const, 1, ""}, + {"SIOCSLOWAT", Const, 0, ""}, + {"SIOCSPGRP", Const, 0, ""}, + {"SIOCSRARP", Const, 0, ""}, + {"SIOCSSPPPPARAMS", Const, 3, ""}, + {"SIOCSVH", Const, 1, ""}, + {"SIOCSVNETID", Const, 3, ""}, + {"SIOCZIFDATA", Const, 1, ""}, + {"SIO_GET_EXTENSION_FUNCTION_POINTER", Const, 1, ""}, + {"SIO_GET_INTERFACE_LIST", Const, 0, ""}, + {"SIO_KEEPALIVE_VALS", Const, 3, ""}, + {"SIO_UDP_CONNRESET", Const, 4, ""}, + {"SOCK_CLOEXEC", Const, 0, ""}, + {"SOCK_DCCP", Const, 0, ""}, + {"SOCK_DGRAM", Const, 0, ""}, + {"SOCK_FLAGS_MASK", Const, 1, ""}, + {"SOCK_MAXADDRLEN", Const, 0, ""}, + {"SOCK_NONBLOCK", Const, 0, ""}, + {"SOCK_NOSIGPIPE", Const, 1, ""}, + {"SOCK_PACKET", Const, 0, ""}, + {"SOCK_RAW", Const, 0, ""}, + {"SOCK_RDM", Const, 0, ""}, + {"SOCK_SEQPACKET", Const, 0, ""}, + {"SOCK_STREAM", Const, 0, ""}, + {"SOL_AAL", Const, 0, ""}, + {"SOL_ATM", Const, 0, ""}, + {"SOL_DECNET", Const, 0, ""}, + {"SOL_ICMPV6", Const, 0, ""}, + {"SOL_IP", Const, 0, ""}, + {"SOL_IPV6", Const, 0, ""}, + {"SOL_IRDA", Const, 0, ""}, + {"SOL_PACKET", Const, 0, ""}, + {"SOL_RAW", Const, 0, ""}, + {"SOL_SOCKET", Const, 0, ""}, + {"SOL_TCP", Const, 0, ""}, + {"SOL_X25", Const, 0, ""}, + {"SOMAXCONN", Const, 0, ""}, + {"SO_ACCEPTCONN", Const, 0, ""}, + {"SO_ACCEPTFILTER", Const, 0, ""}, + {"SO_ATTACH_FILTER", Const, 0, ""}, + {"SO_BINDANY", Const, 1, ""}, + {"SO_BINDTODEVICE", Const, 0, ""}, + {"SO_BINTIME", Const, 0, ""}, + {"SO_BROADCAST", Const, 0, ""}, + {"SO_BSDCOMPAT", Const, 0, ""}, + {"SO_DEBUG", Const, 0, ""}, + {"SO_DETACH_FILTER", Const, 0, ""}, + {"SO_DOMAIN", Const, 0, ""}, + {"SO_DONTROUTE", Const, 0, ""}, + {"SO_DONTTRUNC", Const, 0, ""}, + {"SO_ERROR", Const, 0, ""}, + {"SO_KEEPALIVE", Const, 0, ""}, + {"SO_LABEL", Const, 0, ""}, + {"SO_LINGER", Const, 0, ""}, + {"SO_LINGER_SEC", Const, 0, ""}, + {"SO_LISTENINCQLEN", Const, 0, ""}, + {"SO_LISTENQLEN", Const, 0, ""}, + {"SO_LISTENQLIMIT", Const, 0, ""}, + {"SO_MARK", Const, 0, ""}, + {"SO_NETPROC", Const, 1, ""}, + {"SO_NKE", Const, 0, ""}, + {"SO_NOADDRERR", Const, 0, ""}, + {"SO_NOHEADER", Const, 1, ""}, + {"SO_NOSIGPIPE", Const, 0, ""}, + {"SO_NOTIFYCONFLICT", Const, 0, ""}, + {"SO_NO_CHECK", Const, 0, ""}, + {"SO_NO_DDP", Const, 0, ""}, + {"SO_NO_OFFLOAD", Const, 0, ""}, + {"SO_NP_EXTENSIONS", Const, 0, ""}, + {"SO_NREAD", Const, 0, ""}, + {"SO_NUMRCVPKT", Const, 16, ""}, + {"SO_NWRITE", Const, 0, ""}, + {"SO_OOBINLINE", Const, 0, ""}, + {"SO_OVERFLOWED", Const, 1, ""}, + {"SO_PASSCRED", Const, 0, ""}, + {"SO_PASSSEC", Const, 0, ""}, + {"SO_PEERCRED", Const, 0, ""}, + {"SO_PEERLABEL", Const, 0, ""}, + {"SO_PEERNAME", Const, 0, ""}, + {"SO_PEERSEC", Const, 0, ""}, + {"SO_PRIORITY", Const, 0, ""}, + {"SO_PROTOCOL", Const, 0, ""}, + {"SO_PROTOTYPE", Const, 1, ""}, + {"SO_RANDOMPORT", Const, 0, ""}, + {"SO_RCVBUF", Const, 0, ""}, + {"SO_RCVBUFFORCE", Const, 0, ""}, + {"SO_RCVLOWAT", Const, 0, ""}, + {"SO_RCVTIMEO", Const, 0, ""}, + {"SO_RESTRICTIONS", Const, 0, ""}, + {"SO_RESTRICT_DENYIN", Const, 0, ""}, + {"SO_RESTRICT_DENYOUT", Const, 0, ""}, + {"SO_RESTRICT_DENYSET", Const, 0, ""}, + {"SO_REUSEADDR", Const, 0, ""}, + {"SO_REUSEPORT", Const, 0, ""}, + {"SO_REUSESHAREUID", Const, 0, ""}, + {"SO_RTABLE", Const, 1, ""}, + {"SO_RXQ_OVFL", Const, 0, ""}, + {"SO_SECURITY_AUTHENTICATION", Const, 0, ""}, + {"SO_SECURITY_ENCRYPTION_NETWORK", Const, 0, ""}, + {"SO_SECURITY_ENCRYPTION_TRANSPORT", Const, 0, ""}, + {"SO_SETFIB", Const, 0, ""}, + {"SO_SNDBUF", Const, 0, ""}, + {"SO_SNDBUFFORCE", Const, 0, ""}, + {"SO_SNDLOWAT", Const, 0, ""}, + {"SO_SNDTIMEO", Const, 0, ""}, + {"SO_SPLICE", Const, 1, ""}, + {"SO_TIMESTAMP", Const, 0, ""}, + {"SO_TIMESTAMPING", Const, 0, ""}, + {"SO_TIMESTAMPNS", Const, 0, ""}, + {"SO_TIMESTAMP_MONOTONIC", Const, 0, ""}, + {"SO_TYPE", Const, 0, ""}, + {"SO_UPCALLCLOSEWAIT", Const, 0, ""}, + {"SO_UPDATE_ACCEPT_CONTEXT", Const, 0, ""}, + {"SO_UPDATE_CONNECT_CONTEXT", Const, 1, ""}, + {"SO_USELOOPBACK", Const, 0, ""}, + {"SO_USER_COOKIE", Const, 1, ""}, + {"SO_VENDOR", Const, 3, ""}, + {"SO_WANTMORE", Const, 0, ""}, + {"SO_WANTOOBFLAG", Const, 0, ""}, + {"SSLExtraCertChainPolicyPara", Type, 0, ""}, + {"SSLExtraCertChainPolicyPara.AuthType", Field, 0, ""}, + {"SSLExtraCertChainPolicyPara.Checks", Field, 0, ""}, + {"SSLExtraCertChainPolicyPara.ServerName", Field, 0, ""}, + {"SSLExtraCertChainPolicyPara.Size", Field, 0, ""}, + {"STANDARD_RIGHTS_ALL", Const, 0, ""}, + {"STANDARD_RIGHTS_EXECUTE", Const, 0, ""}, + {"STANDARD_RIGHTS_READ", Const, 0, ""}, + {"STANDARD_RIGHTS_REQUIRED", Const, 0, ""}, + {"STANDARD_RIGHTS_WRITE", Const, 0, ""}, + {"STARTF_USESHOWWINDOW", Const, 0, ""}, + {"STARTF_USESTDHANDLES", Const, 0, ""}, + {"STD_ERROR_HANDLE", Const, 0, ""}, + {"STD_INPUT_HANDLE", Const, 0, ""}, + {"STD_OUTPUT_HANDLE", Const, 0, ""}, + {"SUBLANG_ENGLISH_US", Const, 0, ""}, + {"SW_FORCEMINIMIZE", Const, 0, ""}, + {"SW_HIDE", Const, 0, ""}, + {"SW_MAXIMIZE", Const, 0, ""}, + {"SW_MINIMIZE", Const, 0, ""}, + {"SW_NORMAL", Const, 0, ""}, + {"SW_RESTORE", Const, 0, ""}, + {"SW_SHOW", Const, 0, ""}, + {"SW_SHOWDEFAULT", Const, 0, ""}, + {"SW_SHOWMAXIMIZED", Const, 0, ""}, + {"SW_SHOWMINIMIZED", Const, 0, ""}, + {"SW_SHOWMINNOACTIVE", Const, 0, ""}, + {"SW_SHOWNA", Const, 0, ""}, + {"SW_SHOWNOACTIVATE", Const, 0, ""}, + {"SW_SHOWNORMAL", Const, 0, ""}, + {"SYMBOLIC_LINK_FLAG_DIRECTORY", Const, 4, ""}, + {"SYNCHRONIZE", Const, 0, ""}, + {"SYSCTL_VERSION", Const, 1, ""}, + {"SYSCTL_VERS_0", Const, 1, ""}, + {"SYSCTL_VERS_1", Const, 1, ""}, + {"SYSCTL_VERS_MASK", Const, 1, ""}, + {"SYS_ABORT2", Const, 0, ""}, + {"SYS_ACCEPT", Const, 0, ""}, + {"SYS_ACCEPT4", Const, 0, ""}, + {"SYS_ACCEPT_NOCANCEL", Const, 0, ""}, + {"SYS_ACCESS", Const, 0, ""}, + {"SYS_ACCESS_EXTENDED", Const, 0, ""}, + {"SYS_ACCT", Const, 0, ""}, + {"SYS_ADD_KEY", Const, 0, ""}, + {"SYS_ADD_PROFIL", Const, 0, ""}, + {"SYS_ADJFREQ", Const, 1, ""}, + {"SYS_ADJTIME", Const, 0, ""}, + {"SYS_ADJTIMEX", Const, 0, ""}, + {"SYS_AFS_SYSCALL", Const, 0, ""}, + {"SYS_AIO_CANCEL", Const, 0, ""}, + {"SYS_AIO_ERROR", Const, 0, ""}, + {"SYS_AIO_FSYNC", Const, 0, ""}, + {"SYS_AIO_MLOCK", Const, 14, ""}, + {"SYS_AIO_READ", Const, 0, ""}, + {"SYS_AIO_RETURN", Const, 0, ""}, + {"SYS_AIO_SUSPEND", Const, 0, ""}, + {"SYS_AIO_SUSPEND_NOCANCEL", Const, 0, ""}, + {"SYS_AIO_WAITCOMPLETE", Const, 14, ""}, + {"SYS_AIO_WRITE", Const, 0, ""}, + {"SYS_ALARM", Const, 0, ""}, + {"SYS_ARCH_PRCTL", Const, 0, ""}, + {"SYS_ARM_FADVISE64_64", Const, 0, ""}, + {"SYS_ARM_SYNC_FILE_RANGE", Const, 0, ""}, + {"SYS_ATGETMSG", Const, 0, ""}, + {"SYS_ATPGETREQ", Const, 0, ""}, + {"SYS_ATPGETRSP", Const, 0, ""}, + {"SYS_ATPSNDREQ", Const, 0, ""}, + {"SYS_ATPSNDRSP", Const, 0, ""}, + {"SYS_ATPUTMSG", Const, 0, ""}, + {"SYS_ATSOCKET", Const, 0, ""}, + {"SYS_AUDIT", Const, 0, ""}, + {"SYS_AUDITCTL", Const, 0, ""}, + {"SYS_AUDITON", Const, 0, ""}, + {"SYS_AUDIT_SESSION_JOIN", Const, 0, ""}, + {"SYS_AUDIT_SESSION_PORT", Const, 0, ""}, + {"SYS_AUDIT_SESSION_SELF", Const, 0, ""}, + {"SYS_BDFLUSH", Const, 0, ""}, + {"SYS_BIND", Const, 0, ""}, + {"SYS_BINDAT", Const, 3, ""}, + {"SYS_BREAK", Const, 0, ""}, + {"SYS_BRK", Const, 0, ""}, + {"SYS_BSDTHREAD_CREATE", Const, 0, ""}, + {"SYS_BSDTHREAD_REGISTER", Const, 0, ""}, + {"SYS_BSDTHREAD_TERMINATE", Const, 0, ""}, + {"SYS_CAPGET", Const, 0, ""}, + {"SYS_CAPSET", Const, 0, ""}, + {"SYS_CAP_ENTER", Const, 0, ""}, + {"SYS_CAP_FCNTLS_GET", Const, 1, ""}, + {"SYS_CAP_FCNTLS_LIMIT", Const, 1, ""}, + {"SYS_CAP_GETMODE", Const, 0, ""}, + {"SYS_CAP_GETRIGHTS", Const, 0, ""}, + {"SYS_CAP_IOCTLS_GET", Const, 1, ""}, + {"SYS_CAP_IOCTLS_LIMIT", Const, 1, ""}, + {"SYS_CAP_NEW", Const, 0, ""}, + {"SYS_CAP_RIGHTS_GET", Const, 1, ""}, + {"SYS_CAP_RIGHTS_LIMIT", Const, 1, ""}, + {"SYS_CHDIR", Const, 0, ""}, + {"SYS_CHFLAGS", Const, 0, ""}, + {"SYS_CHFLAGSAT", Const, 3, ""}, + {"SYS_CHMOD", Const, 0, ""}, + {"SYS_CHMOD_EXTENDED", Const, 0, ""}, + {"SYS_CHOWN", Const, 0, ""}, + {"SYS_CHOWN32", Const, 0, ""}, + {"SYS_CHROOT", Const, 0, ""}, + {"SYS_CHUD", Const, 0, ""}, + {"SYS_CLOCK_ADJTIME", Const, 0, ""}, + {"SYS_CLOCK_GETCPUCLOCKID2", Const, 1, ""}, + {"SYS_CLOCK_GETRES", Const, 0, ""}, + {"SYS_CLOCK_GETTIME", Const, 0, ""}, + {"SYS_CLOCK_NANOSLEEP", Const, 0, ""}, + {"SYS_CLOCK_SETTIME", Const, 0, ""}, + {"SYS_CLONE", Const, 0, ""}, + {"SYS_CLOSE", Const, 0, ""}, + {"SYS_CLOSEFROM", Const, 0, ""}, + {"SYS_CLOSE_NOCANCEL", Const, 0, ""}, + {"SYS_CONNECT", Const, 0, ""}, + {"SYS_CONNECTAT", Const, 3, ""}, + {"SYS_CONNECT_NOCANCEL", Const, 0, ""}, + {"SYS_COPYFILE", Const, 0, ""}, + {"SYS_CPUSET", Const, 0, ""}, + {"SYS_CPUSET_GETAFFINITY", Const, 0, ""}, + {"SYS_CPUSET_GETID", Const, 0, ""}, + {"SYS_CPUSET_SETAFFINITY", Const, 0, ""}, + {"SYS_CPUSET_SETID", Const, 0, ""}, + {"SYS_CREAT", Const, 0, ""}, + {"SYS_CREATE_MODULE", Const, 0, ""}, + {"SYS_CSOPS", Const, 0, ""}, + {"SYS_CSOPS_AUDITTOKEN", Const, 16, ""}, + {"SYS_DELETE", Const, 0, ""}, + {"SYS_DELETE_MODULE", Const, 0, ""}, + {"SYS_DUP", Const, 0, ""}, + {"SYS_DUP2", Const, 0, ""}, + {"SYS_DUP3", Const, 0, ""}, + {"SYS_EACCESS", Const, 0, ""}, + {"SYS_EPOLL_CREATE", Const, 0, ""}, + {"SYS_EPOLL_CREATE1", Const, 0, ""}, + {"SYS_EPOLL_CTL", Const, 0, ""}, + {"SYS_EPOLL_CTL_OLD", Const, 0, ""}, + {"SYS_EPOLL_PWAIT", Const, 0, ""}, + {"SYS_EPOLL_WAIT", Const, 0, ""}, + {"SYS_EPOLL_WAIT_OLD", Const, 0, ""}, + {"SYS_EVENTFD", Const, 0, ""}, + {"SYS_EVENTFD2", Const, 0, ""}, + {"SYS_EXCHANGEDATA", Const, 0, ""}, + {"SYS_EXECVE", Const, 0, ""}, + {"SYS_EXIT", Const, 0, ""}, + {"SYS_EXIT_GROUP", Const, 0, ""}, + {"SYS_EXTATTRCTL", Const, 0, ""}, + {"SYS_EXTATTR_DELETE_FD", Const, 0, ""}, + {"SYS_EXTATTR_DELETE_FILE", Const, 0, ""}, + {"SYS_EXTATTR_DELETE_LINK", Const, 0, ""}, + {"SYS_EXTATTR_GET_FD", Const, 0, ""}, + {"SYS_EXTATTR_GET_FILE", Const, 0, ""}, + {"SYS_EXTATTR_GET_LINK", Const, 0, ""}, + {"SYS_EXTATTR_LIST_FD", Const, 0, ""}, + {"SYS_EXTATTR_LIST_FILE", Const, 0, ""}, + {"SYS_EXTATTR_LIST_LINK", Const, 0, ""}, + {"SYS_EXTATTR_SET_FD", Const, 0, ""}, + {"SYS_EXTATTR_SET_FILE", Const, 0, ""}, + {"SYS_EXTATTR_SET_LINK", Const, 0, ""}, + {"SYS_FACCESSAT", Const, 0, ""}, + {"SYS_FADVISE64", Const, 0, ""}, + {"SYS_FADVISE64_64", Const, 0, ""}, + {"SYS_FALLOCATE", Const, 0, ""}, + {"SYS_FANOTIFY_INIT", Const, 0, ""}, + {"SYS_FANOTIFY_MARK", Const, 0, ""}, + {"SYS_FCHDIR", Const, 0, ""}, + {"SYS_FCHFLAGS", Const, 0, ""}, + {"SYS_FCHMOD", Const, 0, ""}, + {"SYS_FCHMODAT", Const, 0, ""}, + {"SYS_FCHMOD_EXTENDED", Const, 0, ""}, + {"SYS_FCHOWN", Const, 0, ""}, + {"SYS_FCHOWN32", Const, 0, ""}, + {"SYS_FCHOWNAT", Const, 0, ""}, + {"SYS_FCHROOT", Const, 1, ""}, + {"SYS_FCNTL", Const, 0, ""}, + {"SYS_FCNTL64", Const, 0, ""}, + {"SYS_FCNTL_NOCANCEL", Const, 0, ""}, + {"SYS_FDATASYNC", Const, 0, ""}, + {"SYS_FEXECVE", Const, 0, ""}, + {"SYS_FFCLOCK_GETCOUNTER", Const, 0, ""}, + {"SYS_FFCLOCK_GETESTIMATE", Const, 0, ""}, + {"SYS_FFCLOCK_SETESTIMATE", Const, 0, ""}, + {"SYS_FFSCTL", Const, 0, ""}, + {"SYS_FGETATTRLIST", Const, 0, ""}, + {"SYS_FGETXATTR", Const, 0, ""}, + {"SYS_FHOPEN", Const, 0, ""}, + {"SYS_FHSTAT", Const, 0, ""}, + {"SYS_FHSTATFS", Const, 0, ""}, + {"SYS_FILEPORT_MAKEFD", Const, 0, ""}, + {"SYS_FILEPORT_MAKEPORT", Const, 0, ""}, + {"SYS_FKTRACE", Const, 1, ""}, + {"SYS_FLISTXATTR", Const, 0, ""}, + {"SYS_FLOCK", Const, 0, ""}, + {"SYS_FORK", Const, 0, ""}, + {"SYS_FPATHCONF", Const, 0, ""}, + {"SYS_FREEBSD6_FTRUNCATE", Const, 0, ""}, + {"SYS_FREEBSD6_LSEEK", Const, 0, ""}, + {"SYS_FREEBSD6_MMAP", Const, 0, ""}, + {"SYS_FREEBSD6_PREAD", Const, 0, ""}, + {"SYS_FREEBSD6_PWRITE", Const, 0, ""}, + {"SYS_FREEBSD6_TRUNCATE", Const, 0, ""}, + {"SYS_FREMOVEXATTR", Const, 0, ""}, + {"SYS_FSCTL", Const, 0, ""}, + {"SYS_FSETATTRLIST", Const, 0, ""}, + {"SYS_FSETXATTR", Const, 0, ""}, + {"SYS_FSGETPATH", Const, 0, ""}, + {"SYS_FSTAT", Const, 0, ""}, + {"SYS_FSTAT64", Const, 0, ""}, + {"SYS_FSTAT64_EXTENDED", Const, 0, ""}, + {"SYS_FSTATAT", Const, 0, ""}, + {"SYS_FSTATAT64", Const, 0, ""}, + {"SYS_FSTATFS", Const, 0, ""}, + {"SYS_FSTATFS64", Const, 0, ""}, + {"SYS_FSTATV", Const, 0, ""}, + {"SYS_FSTATVFS1", Const, 1, ""}, + {"SYS_FSTAT_EXTENDED", Const, 0, ""}, + {"SYS_FSYNC", Const, 0, ""}, + {"SYS_FSYNC_NOCANCEL", Const, 0, ""}, + {"SYS_FSYNC_RANGE", Const, 1, ""}, + {"SYS_FTIME", Const, 0, ""}, + {"SYS_FTRUNCATE", Const, 0, ""}, + {"SYS_FTRUNCATE64", Const, 0, ""}, + {"SYS_FUTEX", Const, 0, ""}, + {"SYS_FUTIMENS", Const, 1, ""}, + {"SYS_FUTIMES", Const, 0, ""}, + {"SYS_FUTIMESAT", Const, 0, ""}, + {"SYS_GETATTRLIST", Const, 0, ""}, + {"SYS_GETAUDIT", Const, 0, ""}, + {"SYS_GETAUDIT_ADDR", Const, 0, ""}, + {"SYS_GETAUID", Const, 0, ""}, + {"SYS_GETCONTEXT", Const, 0, ""}, + {"SYS_GETCPU", Const, 0, ""}, + {"SYS_GETCWD", Const, 0, ""}, + {"SYS_GETDENTS", Const, 0, ""}, + {"SYS_GETDENTS64", Const, 0, ""}, + {"SYS_GETDIRENTRIES", Const, 0, ""}, + {"SYS_GETDIRENTRIES64", Const, 0, ""}, + {"SYS_GETDIRENTRIESATTR", Const, 0, ""}, + {"SYS_GETDTABLECOUNT", Const, 1, ""}, + {"SYS_GETDTABLESIZE", Const, 0, ""}, + {"SYS_GETEGID", Const, 0, ""}, + {"SYS_GETEGID32", Const, 0, ""}, + {"SYS_GETEUID", Const, 0, ""}, + {"SYS_GETEUID32", Const, 0, ""}, + {"SYS_GETFH", Const, 0, ""}, + {"SYS_GETFSSTAT", Const, 0, ""}, + {"SYS_GETFSSTAT64", Const, 0, ""}, + {"SYS_GETGID", Const, 0, ""}, + {"SYS_GETGID32", Const, 0, ""}, + {"SYS_GETGROUPS", Const, 0, ""}, + {"SYS_GETGROUPS32", Const, 0, ""}, + {"SYS_GETHOSTUUID", Const, 0, ""}, + {"SYS_GETITIMER", Const, 0, ""}, + {"SYS_GETLCID", Const, 0, ""}, + {"SYS_GETLOGIN", Const, 0, ""}, + {"SYS_GETLOGINCLASS", Const, 0, ""}, + {"SYS_GETPEERNAME", Const, 0, ""}, + {"SYS_GETPGID", Const, 0, ""}, + {"SYS_GETPGRP", Const, 0, ""}, + {"SYS_GETPID", Const, 0, ""}, + {"SYS_GETPMSG", Const, 0, ""}, + {"SYS_GETPPID", Const, 0, ""}, + {"SYS_GETPRIORITY", Const, 0, ""}, + {"SYS_GETRESGID", Const, 0, ""}, + {"SYS_GETRESGID32", Const, 0, ""}, + {"SYS_GETRESUID", Const, 0, ""}, + {"SYS_GETRESUID32", Const, 0, ""}, + {"SYS_GETRLIMIT", Const, 0, ""}, + {"SYS_GETRTABLE", Const, 1, ""}, + {"SYS_GETRUSAGE", Const, 0, ""}, + {"SYS_GETSGROUPS", Const, 0, ""}, + {"SYS_GETSID", Const, 0, ""}, + {"SYS_GETSOCKNAME", Const, 0, ""}, + {"SYS_GETSOCKOPT", Const, 0, ""}, + {"SYS_GETTHRID", Const, 1, ""}, + {"SYS_GETTID", Const, 0, ""}, + {"SYS_GETTIMEOFDAY", Const, 0, ""}, + {"SYS_GETUID", Const, 0, ""}, + {"SYS_GETUID32", Const, 0, ""}, + {"SYS_GETVFSSTAT", Const, 1, ""}, + {"SYS_GETWGROUPS", Const, 0, ""}, + {"SYS_GETXATTR", Const, 0, ""}, + {"SYS_GET_KERNEL_SYMS", Const, 0, ""}, + {"SYS_GET_MEMPOLICY", Const, 0, ""}, + {"SYS_GET_ROBUST_LIST", Const, 0, ""}, + {"SYS_GET_THREAD_AREA", Const, 0, ""}, + {"SYS_GSSD_SYSCALL", Const, 14, ""}, + {"SYS_GTTY", Const, 0, ""}, + {"SYS_IDENTITYSVC", Const, 0, ""}, + {"SYS_IDLE", Const, 0, ""}, + {"SYS_INITGROUPS", Const, 0, ""}, + {"SYS_INIT_MODULE", Const, 0, ""}, + {"SYS_INOTIFY_ADD_WATCH", Const, 0, ""}, + {"SYS_INOTIFY_INIT", Const, 0, ""}, + {"SYS_INOTIFY_INIT1", Const, 0, ""}, + {"SYS_INOTIFY_RM_WATCH", Const, 0, ""}, + {"SYS_IOCTL", Const, 0, ""}, + {"SYS_IOPERM", Const, 0, ""}, + {"SYS_IOPL", Const, 0, ""}, + {"SYS_IOPOLICYSYS", Const, 0, ""}, + {"SYS_IOPRIO_GET", Const, 0, ""}, + {"SYS_IOPRIO_SET", Const, 0, ""}, + {"SYS_IO_CANCEL", Const, 0, ""}, + {"SYS_IO_DESTROY", Const, 0, ""}, + {"SYS_IO_GETEVENTS", Const, 0, ""}, + {"SYS_IO_SETUP", Const, 0, ""}, + {"SYS_IO_SUBMIT", Const, 0, ""}, + {"SYS_IPC", Const, 0, ""}, + {"SYS_ISSETUGID", Const, 0, ""}, + {"SYS_JAIL", Const, 0, ""}, + {"SYS_JAIL_ATTACH", Const, 0, ""}, + {"SYS_JAIL_GET", Const, 0, ""}, + {"SYS_JAIL_REMOVE", Const, 0, ""}, + {"SYS_JAIL_SET", Const, 0, ""}, + {"SYS_KAS_INFO", Const, 16, ""}, + {"SYS_KDEBUG_TRACE", Const, 0, ""}, + {"SYS_KENV", Const, 0, ""}, + {"SYS_KEVENT", Const, 0, ""}, + {"SYS_KEVENT64", Const, 0, ""}, + {"SYS_KEXEC_LOAD", Const, 0, ""}, + {"SYS_KEYCTL", Const, 0, ""}, + {"SYS_KILL", Const, 0, ""}, + {"SYS_KLDFIND", Const, 0, ""}, + {"SYS_KLDFIRSTMOD", Const, 0, ""}, + {"SYS_KLDLOAD", Const, 0, ""}, + {"SYS_KLDNEXT", Const, 0, ""}, + {"SYS_KLDSTAT", Const, 0, ""}, + {"SYS_KLDSYM", Const, 0, ""}, + {"SYS_KLDUNLOAD", Const, 0, ""}, + {"SYS_KLDUNLOADF", Const, 0, ""}, + {"SYS_KMQ_NOTIFY", Const, 14, ""}, + {"SYS_KMQ_OPEN", Const, 14, ""}, + {"SYS_KMQ_SETATTR", Const, 14, ""}, + {"SYS_KMQ_TIMEDRECEIVE", Const, 14, ""}, + {"SYS_KMQ_TIMEDSEND", Const, 14, ""}, + {"SYS_KMQ_UNLINK", Const, 14, ""}, + {"SYS_KQUEUE", Const, 0, ""}, + {"SYS_KQUEUE1", Const, 1, ""}, + {"SYS_KSEM_CLOSE", Const, 14, ""}, + {"SYS_KSEM_DESTROY", Const, 14, ""}, + {"SYS_KSEM_GETVALUE", Const, 14, ""}, + {"SYS_KSEM_INIT", Const, 14, ""}, + {"SYS_KSEM_OPEN", Const, 14, ""}, + {"SYS_KSEM_POST", Const, 14, ""}, + {"SYS_KSEM_TIMEDWAIT", Const, 14, ""}, + {"SYS_KSEM_TRYWAIT", Const, 14, ""}, + {"SYS_KSEM_UNLINK", Const, 14, ""}, + {"SYS_KSEM_WAIT", Const, 14, ""}, + {"SYS_KTIMER_CREATE", Const, 0, ""}, + {"SYS_KTIMER_DELETE", Const, 0, ""}, + {"SYS_KTIMER_GETOVERRUN", Const, 0, ""}, + {"SYS_KTIMER_GETTIME", Const, 0, ""}, + {"SYS_KTIMER_SETTIME", Const, 0, ""}, + {"SYS_KTRACE", Const, 0, ""}, + {"SYS_LCHFLAGS", Const, 0, ""}, + {"SYS_LCHMOD", Const, 0, ""}, + {"SYS_LCHOWN", Const, 0, ""}, + {"SYS_LCHOWN32", Const, 0, ""}, + {"SYS_LEDGER", Const, 16, ""}, + {"SYS_LGETFH", Const, 0, ""}, + {"SYS_LGETXATTR", Const, 0, ""}, + {"SYS_LINK", Const, 0, ""}, + {"SYS_LINKAT", Const, 0, ""}, + {"SYS_LIO_LISTIO", Const, 0, ""}, + {"SYS_LISTEN", Const, 0, ""}, + {"SYS_LISTXATTR", Const, 0, ""}, + {"SYS_LLISTXATTR", Const, 0, ""}, + {"SYS_LOCK", Const, 0, ""}, + {"SYS_LOOKUP_DCOOKIE", Const, 0, ""}, + {"SYS_LPATHCONF", Const, 0, ""}, + {"SYS_LREMOVEXATTR", Const, 0, ""}, + {"SYS_LSEEK", Const, 0, ""}, + {"SYS_LSETXATTR", Const, 0, ""}, + {"SYS_LSTAT", Const, 0, ""}, + {"SYS_LSTAT64", Const, 0, ""}, + {"SYS_LSTAT64_EXTENDED", Const, 0, ""}, + {"SYS_LSTATV", Const, 0, ""}, + {"SYS_LSTAT_EXTENDED", Const, 0, ""}, + {"SYS_LUTIMES", Const, 0, ""}, + {"SYS_MAC_SYSCALL", Const, 0, ""}, + {"SYS_MADVISE", Const, 0, ""}, + {"SYS_MADVISE1", Const, 0, ""}, + {"SYS_MAXSYSCALL", Const, 0, ""}, + {"SYS_MBIND", Const, 0, ""}, + {"SYS_MIGRATE_PAGES", Const, 0, ""}, + {"SYS_MINCORE", Const, 0, ""}, + {"SYS_MINHERIT", Const, 0, ""}, + {"SYS_MKCOMPLEX", Const, 0, ""}, + {"SYS_MKDIR", Const, 0, ""}, + {"SYS_MKDIRAT", Const, 0, ""}, + {"SYS_MKDIR_EXTENDED", Const, 0, ""}, + {"SYS_MKFIFO", Const, 0, ""}, + {"SYS_MKFIFOAT", Const, 0, ""}, + {"SYS_MKFIFO_EXTENDED", Const, 0, ""}, + {"SYS_MKNOD", Const, 0, ""}, + {"SYS_MKNODAT", Const, 0, ""}, + {"SYS_MLOCK", Const, 0, ""}, + {"SYS_MLOCKALL", Const, 0, ""}, + {"SYS_MMAP", Const, 0, ""}, + {"SYS_MMAP2", Const, 0, ""}, + {"SYS_MODCTL", Const, 1, ""}, + {"SYS_MODFIND", Const, 0, ""}, + {"SYS_MODFNEXT", Const, 0, ""}, + {"SYS_MODIFY_LDT", Const, 0, ""}, + {"SYS_MODNEXT", Const, 0, ""}, + {"SYS_MODSTAT", Const, 0, ""}, + {"SYS_MODWATCH", Const, 0, ""}, + {"SYS_MOUNT", Const, 0, ""}, + {"SYS_MOVE_PAGES", Const, 0, ""}, + {"SYS_MPROTECT", Const, 0, ""}, + {"SYS_MPX", Const, 0, ""}, + {"SYS_MQUERY", Const, 1, ""}, + {"SYS_MQ_GETSETATTR", Const, 0, ""}, + {"SYS_MQ_NOTIFY", Const, 0, ""}, + {"SYS_MQ_OPEN", Const, 0, ""}, + {"SYS_MQ_TIMEDRECEIVE", Const, 0, ""}, + {"SYS_MQ_TIMEDSEND", Const, 0, ""}, + {"SYS_MQ_UNLINK", Const, 0, ""}, + {"SYS_MREMAP", Const, 0, ""}, + {"SYS_MSGCTL", Const, 0, ""}, + {"SYS_MSGGET", Const, 0, ""}, + {"SYS_MSGRCV", Const, 0, ""}, + {"SYS_MSGRCV_NOCANCEL", Const, 0, ""}, + {"SYS_MSGSND", Const, 0, ""}, + {"SYS_MSGSND_NOCANCEL", Const, 0, ""}, + {"SYS_MSGSYS", Const, 0, ""}, + {"SYS_MSYNC", Const, 0, ""}, + {"SYS_MSYNC_NOCANCEL", Const, 0, ""}, + {"SYS_MUNLOCK", Const, 0, ""}, + {"SYS_MUNLOCKALL", Const, 0, ""}, + {"SYS_MUNMAP", Const, 0, ""}, + {"SYS_NAME_TO_HANDLE_AT", Const, 0, ""}, + {"SYS_NANOSLEEP", Const, 0, ""}, + {"SYS_NEWFSTATAT", Const, 0, ""}, + {"SYS_NFSCLNT", Const, 0, ""}, + {"SYS_NFSSERVCTL", Const, 0, ""}, + {"SYS_NFSSVC", Const, 0, ""}, + {"SYS_NFSTAT", Const, 0, ""}, + {"SYS_NICE", Const, 0, ""}, + {"SYS_NLM_SYSCALL", Const, 14, ""}, + {"SYS_NLSTAT", Const, 0, ""}, + {"SYS_NMOUNT", Const, 0, ""}, + {"SYS_NSTAT", Const, 0, ""}, + {"SYS_NTP_ADJTIME", Const, 0, ""}, + {"SYS_NTP_GETTIME", Const, 0, ""}, + {"SYS_NUMA_GETAFFINITY", Const, 14, ""}, + {"SYS_NUMA_SETAFFINITY", Const, 14, ""}, + {"SYS_OABI_SYSCALL_BASE", Const, 0, ""}, + {"SYS_OBREAK", Const, 0, ""}, + {"SYS_OLDFSTAT", Const, 0, ""}, + {"SYS_OLDLSTAT", Const, 0, ""}, + {"SYS_OLDOLDUNAME", Const, 0, ""}, + {"SYS_OLDSTAT", Const, 0, ""}, + {"SYS_OLDUNAME", Const, 0, ""}, + {"SYS_OPEN", Const, 0, ""}, + {"SYS_OPENAT", Const, 0, ""}, + {"SYS_OPENBSD_POLL", Const, 0, ""}, + {"SYS_OPEN_BY_HANDLE_AT", Const, 0, ""}, + {"SYS_OPEN_DPROTECTED_NP", Const, 16, ""}, + {"SYS_OPEN_EXTENDED", Const, 0, ""}, + {"SYS_OPEN_NOCANCEL", Const, 0, ""}, + {"SYS_OVADVISE", Const, 0, ""}, + {"SYS_PACCEPT", Const, 1, ""}, + {"SYS_PATHCONF", Const, 0, ""}, + {"SYS_PAUSE", Const, 0, ""}, + {"SYS_PCICONFIG_IOBASE", Const, 0, ""}, + {"SYS_PCICONFIG_READ", Const, 0, ""}, + {"SYS_PCICONFIG_WRITE", Const, 0, ""}, + {"SYS_PDFORK", Const, 0, ""}, + {"SYS_PDGETPID", Const, 0, ""}, + {"SYS_PDKILL", Const, 0, ""}, + {"SYS_PERF_EVENT_OPEN", Const, 0, ""}, + {"SYS_PERSONALITY", Const, 0, ""}, + {"SYS_PID_HIBERNATE", Const, 0, ""}, + {"SYS_PID_RESUME", Const, 0, ""}, + {"SYS_PID_SHUTDOWN_SOCKETS", Const, 0, ""}, + {"SYS_PID_SUSPEND", Const, 0, ""}, + {"SYS_PIPE", Const, 0, ""}, + {"SYS_PIPE2", Const, 0, ""}, + {"SYS_PIVOT_ROOT", Const, 0, ""}, + {"SYS_PMC_CONTROL", Const, 1, ""}, + {"SYS_PMC_GET_INFO", Const, 1, ""}, + {"SYS_POLL", Const, 0, ""}, + {"SYS_POLLTS", Const, 1, ""}, + {"SYS_POLL_NOCANCEL", Const, 0, ""}, + {"SYS_POSIX_FADVISE", Const, 0, ""}, + {"SYS_POSIX_FALLOCATE", Const, 0, ""}, + {"SYS_POSIX_OPENPT", Const, 0, ""}, + {"SYS_POSIX_SPAWN", Const, 0, ""}, + {"SYS_PPOLL", Const, 0, ""}, + {"SYS_PRCTL", Const, 0, ""}, + {"SYS_PREAD", Const, 0, ""}, + {"SYS_PREAD64", Const, 0, ""}, + {"SYS_PREADV", Const, 0, ""}, + {"SYS_PREAD_NOCANCEL", Const, 0, ""}, + {"SYS_PRLIMIT64", Const, 0, ""}, + {"SYS_PROCCTL", Const, 3, ""}, + {"SYS_PROCESS_POLICY", Const, 0, ""}, + {"SYS_PROCESS_VM_READV", Const, 0, ""}, + {"SYS_PROCESS_VM_WRITEV", Const, 0, ""}, + {"SYS_PROC_INFO", Const, 0, ""}, + {"SYS_PROF", Const, 0, ""}, + {"SYS_PROFIL", Const, 0, ""}, + {"SYS_PSELECT", Const, 0, ""}, + {"SYS_PSELECT6", Const, 0, ""}, + {"SYS_PSET_ASSIGN", Const, 1, ""}, + {"SYS_PSET_CREATE", Const, 1, ""}, + {"SYS_PSET_DESTROY", Const, 1, ""}, + {"SYS_PSYNCH_CVBROAD", Const, 0, ""}, + {"SYS_PSYNCH_CVCLRPREPOST", Const, 0, ""}, + {"SYS_PSYNCH_CVSIGNAL", Const, 0, ""}, + {"SYS_PSYNCH_CVWAIT", Const, 0, ""}, + {"SYS_PSYNCH_MUTEXDROP", Const, 0, ""}, + {"SYS_PSYNCH_MUTEXWAIT", Const, 0, ""}, + {"SYS_PSYNCH_RW_DOWNGRADE", Const, 0, ""}, + {"SYS_PSYNCH_RW_LONGRDLOCK", Const, 0, ""}, + {"SYS_PSYNCH_RW_RDLOCK", Const, 0, ""}, + {"SYS_PSYNCH_RW_UNLOCK", Const, 0, ""}, + {"SYS_PSYNCH_RW_UNLOCK2", Const, 0, ""}, + {"SYS_PSYNCH_RW_UPGRADE", Const, 0, ""}, + {"SYS_PSYNCH_RW_WRLOCK", Const, 0, ""}, + {"SYS_PSYNCH_RW_YIELDWRLOCK", Const, 0, ""}, + {"SYS_PTRACE", Const, 0, ""}, + {"SYS_PUTPMSG", Const, 0, ""}, + {"SYS_PWRITE", Const, 0, ""}, + {"SYS_PWRITE64", Const, 0, ""}, + {"SYS_PWRITEV", Const, 0, ""}, + {"SYS_PWRITE_NOCANCEL", Const, 0, ""}, + {"SYS_QUERY_MODULE", Const, 0, ""}, + {"SYS_QUOTACTL", Const, 0, ""}, + {"SYS_RASCTL", Const, 1, ""}, + {"SYS_RCTL_ADD_RULE", Const, 0, ""}, + {"SYS_RCTL_GET_LIMITS", Const, 0, ""}, + {"SYS_RCTL_GET_RACCT", Const, 0, ""}, + {"SYS_RCTL_GET_RULES", Const, 0, ""}, + {"SYS_RCTL_REMOVE_RULE", Const, 0, ""}, + {"SYS_READ", Const, 0, ""}, + {"SYS_READAHEAD", Const, 0, ""}, + {"SYS_READDIR", Const, 0, ""}, + {"SYS_READLINK", Const, 0, ""}, + {"SYS_READLINKAT", Const, 0, ""}, + {"SYS_READV", Const, 0, ""}, + {"SYS_READV_NOCANCEL", Const, 0, ""}, + {"SYS_READ_NOCANCEL", Const, 0, ""}, + {"SYS_REBOOT", Const, 0, ""}, + {"SYS_RECV", Const, 0, ""}, + {"SYS_RECVFROM", Const, 0, ""}, + {"SYS_RECVFROM_NOCANCEL", Const, 0, ""}, + {"SYS_RECVMMSG", Const, 0, ""}, + {"SYS_RECVMSG", Const, 0, ""}, + {"SYS_RECVMSG_NOCANCEL", Const, 0, ""}, + {"SYS_REMAP_FILE_PAGES", Const, 0, ""}, + {"SYS_REMOVEXATTR", Const, 0, ""}, + {"SYS_RENAME", Const, 0, ""}, + {"SYS_RENAMEAT", Const, 0, ""}, + {"SYS_REQUEST_KEY", Const, 0, ""}, + {"SYS_RESTART_SYSCALL", Const, 0, ""}, + {"SYS_REVOKE", Const, 0, ""}, + {"SYS_RFORK", Const, 0, ""}, + {"SYS_RMDIR", Const, 0, ""}, + {"SYS_RTPRIO", Const, 0, ""}, + {"SYS_RTPRIO_THREAD", Const, 0, ""}, + {"SYS_RT_SIGACTION", Const, 0, ""}, + {"SYS_RT_SIGPENDING", Const, 0, ""}, + {"SYS_RT_SIGPROCMASK", Const, 0, ""}, + {"SYS_RT_SIGQUEUEINFO", Const, 0, ""}, + {"SYS_RT_SIGRETURN", Const, 0, ""}, + {"SYS_RT_SIGSUSPEND", Const, 0, ""}, + {"SYS_RT_SIGTIMEDWAIT", Const, 0, ""}, + {"SYS_RT_TGSIGQUEUEINFO", Const, 0, ""}, + {"SYS_SBRK", Const, 0, ""}, + {"SYS_SCHED_GETAFFINITY", Const, 0, ""}, + {"SYS_SCHED_GETPARAM", Const, 0, ""}, + {"SYS_SCHED_GETSCHEDULER", Const, 0, ""}, + {"SYS_SCHED_GET_PRIORITY_MAX", Const, 0, ""}, + {"SYS_SCHED_GET_PRIORITY_MIN", Const, 0, ""}, + {"SYS_SCHED_RR_GET_INTERVAL", Const, 0, ""}, + {"SYS_SCHED_SETAFFINITY", Const, 0, ""}, + {"SYS_SCHED_SETPARAM", Const, 0, ""}, + {"SYS_SCHED_SETSCHEDULER", Const, 0, ""}, + {"SYS_SCHED_YIELD", Const, 0, ""}, + {"SYS_SCTP_GENERIC_RECVMSG", Const, 0, ""}, + {"SYS_SCTP_GENERIC_SENDMSG", Const, 0, ""}, + {"SYS_SCTP_GENERIC_SENDMSG_IOV", Const, 0, ""}, + {"SYS_SCTP_PEELOFF", Const, 0, ""}, + {"SYS_SEARCHFS", Const, 0, ""}, + {"SYS_SECURITY", Const, 0, ""}, + {"SYS_SELECT", Const, 0, ""}, + {"SYS_SELECT_NOCANCEL", Const, 0, ""}, + {"SYS_SEMCONFIG", Const, 1, ""}, + {"SYS_SEMCTL", Const, 0, ""}, + {"SYS_SEMGET", Const, 0, ""}, + {"SYS_SEMOP", Const, 0, ""}, + {"SYS_SEMSYS", Const, 0, ""}, + {"SYS_SEMTIMEDOP", Const, 0, ""}, + {"SYS_SEM_CLOSE", Const, 0, ""}, + {"SYS_SEM_DESTROY", Const, 0, ""}, + {"SYS_SEM_GETVALUE", Const, 0, ""}, + {"SYS_SEM_INIT", Const, 0, ""}, + {"SYS_SEM_OPEN", Const, 0, ""}, + {"SYS_SEM_POST", Const, 0, ""}, + {"SYS_SEM_TRYWAIT", Const, 0, ""}, + {"SYS_SEM_UNLINK", Const, 0, ""}, + {"SYS_SEM_WAIT", Const, 0, ""}, + {"SYS_SEM_WAIT_NOCANCEL", Const, 0, ""}, + {"SYS_SEND", Const, 0, ""}, + {"SYS_SENDFILE", Const, 0, ""}, + {"SYS_SENDFILE64", Const, 0, ""}, + {"SYS_SENDMMSG", Const, 0, ""}, + {"SYS_SENDMSG", Const, 0, ""}, + {"SYS_SENDMSG_NOCANCEL", Const, 0, ""}, + {"SYS_SENDTO", Const, 0, ""}, + {"SYS_SENDTO_NOCANCEL", Const, 0, ""}, + {"SYS_SETATTRLIST", Const, 0, ""}, + {"SYS_SETAUDIT", Const, 0, ""}, + {"SYS_SETAUDIT_ADDR", Const, 0, ""}, + {"SYS_SETAUID", Const, 0, ""}, + {"SYS_SETCONTEXT", Const, 0, ""}, + {"SYS_SETDOMAINNAME", Const, 0, ""}, + {"SYS_SETEGID", Const, 0, ""}, + {"SYS_SETEUID", Const, 0, ""}, + {"SYS_SETFIB", Const, 0, ""}, + {"SYS_SETFSGID", Const, 0, ""}, + {"SYS_SETFSGID32", Const, 0, ""}, + {"SYS_SETFSUID", Const, 0, ""}, + {"SYS_SETFSUID32", Const, 0, ""}, + {"SYS_SETGID", Const, 0, ""}, + {"SYS_SETGID32", Const, 0, ""}, + {"SYS_SETGROUPS", Const, 0, ""}, + {"SYS_SETGROUPS32", Const, 0, ""}, + {"SYS_SETHOSTNAME", Const, 0, ""}, + {"SYS_SETITIMER", Const, 0, ""}, + {"SYS_SETLCID", Const, 0, ""}, + {"SYS_SETLOGIN", Const, 0, ""}, + {"SYS_SETLOGINCLASS", Const, 0, ""}, + {"SYS_SETNS", Const, 0, ""}, + {"SYS_SETPGID", Const, 0, ""}, + {"SYS_SETPRIORITY", Const, 0, ""}, + {"SYS_SETPRIVEXEC", Const, 0, ""}, + {"SYS_SETREGID", Const, 0, ""}, + {"SYS_SETREGID32", Const, 0, ""}, + {"SYS_SETRESGID", Const, 0, ""}, + {"SYS_SETRESGID32", Const, 0, ""}, + {"SYS_SETRESUID", Const, 0, ""}, + {"SYS_SETRESUID32", Const, 0, ""}, + {"SYS_SETREUID", Const, 0, ""}, + {"SYS_SETREUID32", Const, 0, ""}, + {"SYS_SETRLIMIT", Const, 0, ""}, + {"SYS_SETRTABLE", Const, 1, ""}, + {"SYS_SETSGROUPS", Const, 0, ""}, + {"SYS_SETSID", Const, 0, ""}, + {"SYS_SETSOCKOPT", Const, 0, ""}, + {"SYS_SETTID", Const, 0, ""}, + {"SYS_SETTID_WITH_PID", Const, 0, ""}, + {"SYS_SETTIMEOFDAY", Const, 0, ""}, + {"SYS_SETUID", Const, 0, ""}, + {"SYS_SETUID32", Const, 0, ""}, + {"SYS_SETWGROUPS", Const, 0, ""}, + {"SYS_SETXATTR", Const, 0, ""}, + {"SYS_SET_MEMPOLICY", Const, 0, ""}, + {"SYS_SET_ROBUST_LIST", Const, 0, ""}, + {"SYS_SET_THREAD_AREA", Const, 0, ""}, + {"SYS_SET_TID_ADDRESS", Const, 0, ""}, + {"SYS_SGETMASK", Const, 0, ""}, + {"SYS_SHARED_REGION_CHECK_NP", Const, 0, ""}, + {"SYS_SHARED_REGION_MAP_AND_SLIDE_NP", Const, 0, ""}, + {"SYS_SHMAT", Const, 0, ""}, + {"SYS_SHMCTL", Const, 0, ""}, + {"SYS_SHMDT", Const, 0, ""}, + {"SYS_SHMGET", Const, 0, ""}, + {"SYS_SHMSYS", Const, 0, ""}, + {"SYS_SHM_OPEN", Const, 0, ""}, + {"SYS_SHM_UNLINK", Const, 0, ""}, + {"SYS_SHUTDOWN", Const, 0, ""}, + {"SYS_SIGACTION", Const, 0, ""}, + {"SYS_SIGALTSTACK", Const, 0, ""}, + {"SYS_SIGNAL", Const, 0, ""}, + {"SYS_SIGNALFD", Const, 0, ""}, + {"SYS_SIGNALFD4", Const, 0, ""}, + {"SYS_SIGPENDING", Const, 0, ""}, + {"SYS_SIGPROCMASK", Const, 0, ""}, + {"SYS_SIGQUEUE", Const, 0, ""}, + {"SYS_SIGQUEUEINFO", Const, 1, ""}, + {"SYS_SIGRETURN", Const, 0, ""}, + {"SYS_SIGSUSPEND", Const, 0, ""}, + {"SYS_SIGSUSPEND_NOCANCEL", Const, 0, ""}, + {"SYS_SIGTIMEDWAIT", Const, 0, ""}, + {"SYS_SIGWAIT", Const, 0, ""}, + {"SYS_SIGWAITINFO", Const, 0, ""}, + {"SYS_SOCKET", Const, 0, ""}, + {"SYS_SOCKETCALL", Const, 0, ""}, + {"SYS_SOCKETPAIR", Const, 0, ""}, + {"SYS_SPLICE", Const, 0, ""}, + {"SYS_SSETMASK", Const, 0, ""}, + {"SYS_SSTK", Const, 0, ""}, + {"SYS_STACK_SNAPSHOT", Const, 0, ""}, + {"SYS_STAT", Const, 0, ""}, + {"SYS_STAT64", Const, 0, ""}, + {"SYS_STAT64_EXTENDED", Const, 0, ""}, + {"SYS_STATFS", Const, 0, ""}, + {"SYS_STATFS64", Const, 0, ""}, + {"SYS_STATV", Const, 0, ""}, + {"SYS_STATVFS1", Const, 1, ""}, + {"SYS_STAT_EXTENDED", Const, 0, ""}, + {"SYS_STIME", Const, 0, ""}, + {"SYS_STTY", Const, 0, ""}, + {"SYS_SWAPCONTEXT", Const, 0, ""}, + {"SYS_SWAPCTL", Const, 1, ""}, + {"SYS_SWAPOFF", Const, 0, ""}, + {"SYS_SWAPON", Const, 0, ""}, + {"SYS_SYMLINK", Const, 0, ""}, + {"SYS_SYMLINKAT", Const, 0, ""}, + {"SYS_SYNC", Const, 0, ""}, + {"SYS_SYNCFS", Const, 0, ""}, + {"SYS_SYNC_FILE_RANGE", Const, 0, ""}, + {"SYS_SYSARCH", Const, 0, ""}, + {"SYS_SYSCALL", Const, 0, ""}, + {"SYS_SYSCALL_BASE", Const, 0, ""}, + {"SYS_SYSFS", Const, 0, ""}, + {"SYS_SYSINFO", Const, 0, ""}, + {"SYS_SYSLOG", Const, 0, ""}, + {"SYS_TEE", Const, 0, ""}, + {"SYS_TGKILL", Const, 0, ""}, + {"SYS_THREAD_SELFID", Const, 0, ""}, + {"SYS_THR_CREATE", Const, 0, ""}, + {"SYS_THR_EXIT", Const, 0, ""}, + {"SYS_THR_KILL", Const, 0, ""}, + {"SYS_THR_KILL2", Const, 0, ""}, + {"SYS_THR_NEW", Const, 0, ""}, + {"SYS_THR_SELF", Const, 0, ""}, + {"SYS_THR_SET_NAME", Const, 0, ""}, + {"SYS_THR_SUSPEND", Const, 0, ""}, + {"SYS_THR_WAKE", Const, 0, ""}, + {"SYS_TIME", Const, 0, ""}, + {"SYS_TIMERFD_CREATE", Const, 0, ""}, + {"SYS_TIMERFD_GETTIME", Const, 0, ""}, + {"SYS_TIMERFD_SETTIME", Const, 0, ""}, + {"SYS_TIMER_CREATE", Const, 0, ""}, + {"SYS_TIMER_DELETE", Const, 0, ""}, + {"SYS_TIMER_GETOVERRUN", Const, 0, ""}, + {"SYS_TIMER_GETTIME", Const, 0, ""}, + {"SYS_TIMER_SETTIME", Const, 0, ""}, + {"SYS_TIMES", Const, 0, ""}, + {"SYS_TKILL", Const, 0, ""}, + {"SYS_TRUNCATE", Const, 0, ""}, + {"SYS_TRUNCATE64", Const, 0, ""}, + {"SYS_TUXCALL", Const, 0, ""}, + {"SYS_UGETRLIMIT", Const, 0, ""}, + {"SYS_ULIMIT", Const, 0, ""}, + {"SYS_UMASK", Const, 0, ""}, + {"SYS_UMASK_EXTENDED", Const, 0, ""}, + {"SYS_UMOUNT", Const, 0, ""}, + {"SYS_UMOUNT2", Const, 0, ""}, + {"SYS_UNAME", Const, 0, ""}, + {"SYS_UNDELETE", Const, 0, ""}, + {"SYS_UNLINK", Const, 0, ""}, + {"SYS_UNLINKAT", Const, 0, ""}, + {"SYS_UNMOUNT", Const, 0, ""}, + {"SYS_UNSHARE", Const, 0, ""}, + {"SYS_USELIB", Const, 0, ""}, + {"SYS_USTAT", Const, 0, ""}, + {"SYS_UTIME", Const, 0, ""}, + {"SYS_UTIMENSAT", Const, 0, ""}, + {"SYS_UTIMES", Const, 0, ""}, + {"SYS_UTRACE", Const, 0, ""}, + {"SYS_UUIDGEN", Const, 0, ""}, + {"SYS_VADVISE", Const, 1, ""}, + {"SYS_VFORK", Const, 0, ""}, + {"SYS_VHANGUP", Const, 0, ""}, + {"SYS_VM86", Const, 0, ""}, + {"SYS_VM86OLD", Const, 0, ""}, + {"SYS_VMSPLICE", Const, 0, ""}, + {"SYS_VM_PRESSURE_MONITOR", Const, 0, ""}, + {"SYS_VSERVER", Const, 0, ""}, + {"SYS_WAIT4", Const, 0, ""}, + {"SYS_WAIT4_NOCANCEL", Const, 0, ""}, + {"SYS_WAIT6", Const, 1, ""}, + {"SYS_WAITEVENT", Const, 0, ""}, + {"SYS_WAITID", Const, 0, ""}, + {"SYS_WAITID_NOCANCEL", Const, 0, ""}, + {"SYS_WAITPID", Const, 0, ""}, + {"SYS_WATCHEVENT", Const, 0, ""}, + {"SYS_WORKQ_KERNRETURN", Const, 0, ""}, + {"SYS_WORKQ_OPEN", Const, 0, ""}, + {"SYS_WRITE", Const, 0, ""}, + {"SYS_WRITEV", Const, 0, ""}, + {"SYS_WRITEV_NOCANCEL", Const, 0, ""}, + {"SYS_WRITE_NOCANCEL", Const, 0, ""}, + {"SYS_YIELD", Const, 0, ""}, + {"SYS__LLSEEK", Const, 0, ""}, + {"SYS__LWP_CONTINUE", Const, 1, ""}, + {"SYS__LWP_CREATE", Const, 1, ""}, + {"SYS__LWP_CTL", Const, 1, ""}, + {"SYS__LWP_DETACH", Const, 1, ""}, + {"SYS__LWP_EXIT", Const, 1, ""}, + {"SYS__LWP_GETNAME", Const, 1, ""}, + {"SYS__LWP_GETPRIVATE", Const, 1, ""}, + {"SYS__LWP_KILL", Const, 1, ""}, + {"SYS__LWP_PARK", Const, 1, ""}, + {"SYS__LWP_SELF", Const, 1, ""}, + {"SYS__LWP_SETNAME", Const, 1, ""}, + {"SYS__LWP_SETPRIVATE", Const, 1, ""}, + {"SYS__LWP_SUSPEND", Const, 1, ""}, + {"SYS__LWP_UNPARK", Const, 1, ""}, + {"SYS__LWP_UNPARK_ALL", Const, 1, ""}, + {"SYS__LWP_WAIT", Const, 1, ""}, + {"SYS__LWP_WAKEUP", Const, 1, ""}, + {"SYS__NEWSELECT", Const, 0, ""}, + {"SYS__PSET_BIND", Const, 1, ""}, + {"SYS__SCHED_GETAFFINITY", Const, 1, ""}, + {"SYS__SCHED_GETPARAM", Const, 1, ""}, + {"SYS__SCHED_SETAFFINITY", Const, 1, ""}, + {"SYS__SCHED_SETPARAM", Const, 1, ""}, + {"SYS__SYSCTL", Const, 0, ""}, + {"SYS__UMTX_LOCK", Const, 0, ""}, + {"SYS__UMTX_OP", Const, 0, ""}, + {"SYS__UMTX_UNLOCK", Const, 0, ""}, + {"SYS___ACL_ACLCHECK_FD", Const, 0, ""}, + {"SYS___ACL_ACLCHECK_FILE", Const, 0, ""}, + {"SYS___ACL_ACLCHECK_LINK", Const, 0, ""}, + {"SYS___ACL_DELETE_FD", Const, 0, ""}, + {"SYS___ACL_DELETE_FILE", Const, 0, ""}, + {"SYS___ACL_DELETE_LINK", Const, 0, ""}, + {"SYS___ACL_GET_FD", Const, 0, ""}, + {"SYS___ACL_GET_FILE", Const, 0, ""}, + {"SYS___ACL_GET_LINK", Const, 0, ""}, + {"SYS___ACL_SET_FD", Const, 0, ""}, + {"SYS___ACL_SET_FILE", Const, 0, ""}, + {"SYS___ACL_SET_LINK", Const, 0, ""}, + {"SYS___CAP_RIGHTS_GET", Const, 14, ""}, + {"SYS___CLONE", Const, 1, ""}, + {"SYS___DISABLE_THREADSIGNAL", Const, 0, ""}, + {"SYS___GETCWD", Const, 0, ""}, + {"SYS___GETLOGIN", Const, 1, ""}, + {"SYS___GET_TCB", Const, 1, ""}, + {"SYS___MAC_EXECVE", Const, 0, ""}, + {"SYS___MAC_GETFSSTAT", Const, 0, ""}, + {"SYS___MAC_GET_FD", Const, 0, ""}, + {"SYS___MAC_GET_FILE", Const, 0, ""}, + {"SYS___MAC_GET_LCID", Const, 0, ""}, + {"SYS___MAC_GET_LCTX", Const, 0, ""}, + {"SYS___MAC_GET_LINK", Const, 0, ""}, + {"SYS___MAC_GET_MOUNT", Const, 0, ""}, + {"SYS___MAC_GET_PID", Const, 0, ""}, + {"SYS___MAC_GET_PROC", Const, 0, ""}, + {"SYS___MAC_MOUNT", Const, 0, ""}, + {"SYS___MAC_SET_FD", Const, 0, ""}, + {"SYS___MAC_SET_FILE", Const, 0, ""}, + {"SYS___MAC_SET_LCTX", Const, 0, ""}, + {"SYS___MAC_SET_LINK", Const, 0, ""}, + {"SYS___MAC_SET_PROC", Const, 0, ""}, + {"SYS___MAC_SYSCALL", Const, 0, ""}, + {"SYS___OLD_SEMWAIT_SIGNAL", Const, 0, ""}, + {"SYS___OLD_SEMWAIT_SIGNAL_NOCANCEL", Const, 0, ""}, + {"SYS___POSIX_CHOWN", Const, 1, ""}, + {"SYS___POSIX_FCHOWN", Const, 1, ""}, + {"SYS___POSIX_LCHOWN", Const, 1, ""}, + {"SYS___POSIX_RENAME", Const, 1, ""}, + {"SYS___PTHREAD_CANCELED", Const, 0, ""}, + {"SYS___PTHREAD_CHDIR", Const, 0, ""}, + {"SYS___PTHREAD_FCHDIR", Const, 0, ""}, + {"SYS___PTHREAD_KILL", Const, 0, ""}, + {"SYS___PTHREAD_MARKCANCEL", Const, 0, ""}, + {"SYS___PTHREAD_SIGMASK", Const, 0, ""}, + {"SYS___QUOTACTL", Const, 1, ""}, + {"SYS___SEMCTL", Const, 1, ""}, + {"SYS___SEMWAIT_SIGNAL", Const, 0, ""}, + {"SYS___SEMWAIT_SIGNAL_NOCANCEL", Const, 0, ""}, + {"SYS___SETLOGIN", Const, 1, ""}, + {"SYS___SETUGID", Const, 0, ""}, + {"SYS___SET_TCB", Const, 1, ""}, + {"SYS___SIGACTION_SIGTRAMP", Const, 1, ""}, + {"SYS___SIGTIMEDWAIT", Const, 1, ""}, + {"SYS___SIGWAIT", Const, 0, ""}, + {"SYS___SIGWAIT_NOCANCEL", Const, 0, ""}, + {"SYS___SYSCTL", Const, 0, ""}, + {"SYS___TFORK", Const, 1, ""}, + {"SYS___THREXIT", Const, 1, ""}, + {"SYS___THRSIGDIVERT", Const, 1, ""}, + {"SYS___THRSLEEP", Const, 1, ""}, + {"SYS___THRWAKEUP", Const, 1, ""}, + {"S_ARCH1", Const, 1, ""}, + {"S_ARCH2", Const, 1, ""}, + {"S_BLKSIZE", Const, 0, ""}, + {"S_IEXEC", Const, 0, ""}, + {"S_IFBLK", Const, 0, ""}, + {"S_IFCHR", Const, 0, ""}, + {"S_IFDIR", Const, 0, ""}, + {"S_IFIFO", Const, 0, ""}, + {"S_IFLNK", Const, 0, ""}, + {"S_IFMT", Const, 0, ""}, + {"S_IFREG", Const, 0, ""}, + {"S_IFSOCK", Const, 0, ""}, + {"S_IFWHT", Const, 0, ""}, + {"S_IREAD", Const, 0, ""}, + {"S_IRGRP", Const, 0, ""}, + {"S_IROTH", Const, 0, ""}, + {"S_IRUSR", Const, 0, ""}, + {"S_IRWXG", Const, 0, ""}, + {"S_IRWXO", Const, 0, ""}, + {"S_IRWXU", Const, 0, ""}, + {"S_ISGID", Const, 0, ""}, + {"S_ISTXT", Const, 0, ""}, + {"S_ISUID", Const, 0, ""}, + {"S_ISVTX", Const, 0, ""}, + {"S_IWGRP", Const, 0, ""}, + {"S_IWOTH", Const, 0, ""}, + {"S_IWRITE", Const, 0, ""}, + {"S_IWUSR", Const, 0, ""}, + {"S_IXGRP", Const, 0, ""}, + {"S_IXOTH", Const, 0, ""}, + {"S_IXUSR", Const, 0, ""}, + {"S_LOGIN_SET", Const, 1, ""}, + {"SecurityAttributes", Type, 0, ""}, + {"SecurityAttributes.InheritHandle", Field, 0, ""}, + {"SecurityAttributes.Length", Field, 0, ""}, + {"SecurityAttributes.SecurityDescriptor", Field, 0, ""}, + {"Seek", Func, 0, "func(fd int, offset int64, whence int) (off int64, err error)"}, + {"Select", Func, 0, "func(nfd int, r *FdSet, w *FdSet, e *FdSet, timeout *Timeval) (n int, err error)"}, + {"Sendfile", Func, 0, "func(outfd int, infd int, offset *int64, count int) (written int, err error)"}, + {"Sendmsg", Func, 0, "func(fd int, p []byte, oob []byte, to Sockaddr, flags int) (err error)"}, + {"SendmsgN", Func, 3, "func(fd int, p []byte, oob []byte, to Sockaddr, flags int) (n int, err error)"}, + {"Sendto", Func, 0, "func(fd int, p []byte, flags int, to Sockaddr) (err error)"}, + {"Servent", Type, 0, ""}, + {"Servent.Aliases", Field, 0, ""}, + {"Servent.Name", Field, 0, ""}, + {"Servent.Port", Field, 0, ""}, + {"Servent.Proto", Field, 0, ""}, + {"SetBpf", Func, 0, ""}, + {"SetBpfBuflen", Func, 0, ""}, + {"SetBpfDatalink", Func, 0, ""}, + {"SetBpfHeadercmpl", Func, 0, ""}, + {"SetBpfImmediate", Func, 0, ""}, + {"SetBpfInterface", Func, 0, ""}, + {"SetBpfPromisc", Func, 0, ""}, + {"SetBpfTimeout", Func, 0, ""}, + {"SetCurrentDirectory", Func, 0, ""}, + {"SetEndOfFile", Func, 0, ""}, + {"SetEnvironmentVariable", Func, 0, ""}, + {"SetFileAttributes", Func, 0, ""}, + {"SetFileCompletionNotificationModes", Func, 2, ""}, + {"SetFilePointer", Func, 0, ""}, + {"SetFileTime", Func, 0, ""}, + {"SetHandleInformation", Func, 0, ""}, + {"SetKevent", Func, 0, ""}, + {"SetLsfPromisc", Func, 0, "func(name string, m bool) error"}, + {"SetNonblock", Func, 0, "func(fd int, nonblocking bool) (err error)"}, + {"Setdomainname", Func, 0, "func(p []byte) (err error)"}, + {"Setegid", Func, 0, "func(egid int) (err error)"}, + {"Setenv", Func, 0, "func(key string, value string) error"}, + {"Seteuid", Func, 0, "func(euid int) (err error)"}, + {"Setfsgid", Func, 0, "func(gid int) (err error)"}, + {"Setfsuid", Func, 0, "func(uid int) (err error)"}, + {"Setgid", Func, 0, "func(gid int) (err error)"}, + {"Setgroups", Func, 0, "func(gids []int) (err error)"}, + {"Sethostname", Func, 0, "func(p []byte) (err error)"}, + {"Setlogin", Func, 0, ""}, + {"Setpgid", Func, 0, "func(pid int, pgid int) (err error)"}, + {"Setpriority", Func, 0, "func(which int, who int, prio int) (err error)"}, + {"Setprivexec", Func, 0, ""}, + {"Setregid", Func, 0, "func(rgid int, egid int) (err error)"}, + {"Setresgid", Func, 0, "func(rgid int, egid int, sgid int) (err error)"}, + {"Setresuid", Func, 0, "func(ruid int, euid int, suid int) (err error)"}, + {"Setreuid", Func, 0, "func(ruid int, euid int) (err error)"}, + {"Setrlimit", Func, 0, "func(resource int, rlim *Rlimit) error"}, + {"Setsid", Func, 0, "func() (pid int, err error)"}, + {"Setsockopt", Func, 0, ""}, + {"SetsockoptByte", Func, 0, "func(fd int, level int, opt int, value byte) (err error)"}, + {"SetsockoptICMPv6Filter", Func, 2, "func(fd int, level int, opt int, filter *ICMPv6Filter) error"}, + {"SetsockoptIPMreq", Func, 0, "func(fd int, level int, opt int, mreq *IPMreq) (err error)"}, + {"SetsockoptIPMreqn", Func, 0, "func(fd int, level int, opt int, mreq *IPMreqn) (err error)"}, + {"SetsockoptIPv6Mreq", Func, 0, "func(fd int, level int, opt int, mreq *IPv6Mreq) (err error)"}, + {"SetsockoptInet4Addr", Func, 0, "func(fd int, level int, opt int, value [4]byte) (err error)"}, + {"SetsockoptInt", Func, 0, "func(fd int, level int, opt int, value int) (err error)"}, + {"SetsockoptLinger", Func, 0, "func(fd int, level int, opt int, l *Linger) (err error)"}, + {"SetsockoptString", Func, 0, "func(fd int, level int, opt int, s string) (err error)"}, + {"SetsockoptTimeval", Func, 0, "func(fd int, level int, opt int, tv *Timeval) (err error)"}, + {"Settimeofday", Func, 0, "func(tv *Timeval) (err error)"}, + {"Setuid", Func, 0, "func(uid int) (err error)"}, + {"Setxattr", Func, 1, "func(path string, attr string, data []byte, flags int) (err error)"}, + {"Shutdown", Func, 0, "func(fd int, how int) (err error)"}, + {"SidTypeAlias", Const, 0, ""}, + {"SidTypeComputer", Const, 0, ""}, + {"SidTypeDeletedAccount", Const, 0, ""}, + {"SidTypeDomain", Const, 0, ""}, + {"SidTypeGroup", Const, 0, ""}, + {"SidTypeInvalid", Const, 0, ""}, + {"SidTypeLabel", Const, 0, ""}, + {"SidTypeUnknown", Const, 0, ""}, + {"SidTypeUser", Const, 0, ""}, + {"SidTypeWellKnownGroup", Const, 0, ""}, + {"Signal", Type, 0, ""}, + {"SizeofBpfHdr", Const, 0, ""}, + {"SizeofBpfInsn", Const, 0, ""}, + {"SizeofBpfProgram", Const, 0, ""}, + {"SizeofBpfStat", Const, 0, ""}, + {"SizeofBpfVersion", Const, 0, ""}, + {"SizeofBpfZbuf", Const, 0, ""}, + {"SizeofBpfZbufHeader", Const, 0, ""}, + {"SizeofCmsghdr", Const, 0, ""}, + {"SizeofICMPv6Filter", Const, 2, ""}, + {"SizeofIPMreq", Const, 0, ""}, + {"SizeofIPMreqn", Const, 0, ""}, + {"SizeofIPv6MTUInfo", Const, 2, ""}, + {"SizeofIPv6Mreq", Const, 0, ""}, + {"SizeofIfAddrmsg", Const, 0, ""}, + {"SizeofIfAnnounceMsghdr", Const, 1, ""}, + {"SizeofIfData", Const, 0, ""}, + {"SizeofIfInfomsg", Const, 0, ""}, + {"SizeofIfMsghdr", Const, 0, ""}, + {"SizeofIfaMsghdr", Const, 0, ""}, + {"SizeofIfmaMsghdr", Const, 0, ""}, + {"SizeofIfmaMsghdr2", Const, 0, ""}, + {"SizeofInet4Pktinfo", Const, 0, ""}, + {"SizeofInet6Pktinfo", Const, 0, ""}, + {"SizeofInotifyEvent", Const, 0, ""}, + {"SizeofLinger", Const, 0, ""}, + {"SizeofMsghdr", Const, 0, ""}, + {"SizeofNlAttr", Const, 0, ""}, + {"SizeofNlMsgerr", Const, 0, ""}, + {"SizeofNlMsghdr", Const, 0, ""}, + {"SizeofRtAttr", Const, 0, ""}, + {"SizeofRtGenmsg", Const, 0, ""}, + {"SizeofRtMetrics", Const, 0, ""}, + {"SizeofRtMsg", Const, 0, ""}, + {"SizeofRtMsghdr", Const, 0, ""}, + {"SizeofRtNexthop", Const, 0, ""}, + {"SizeofSockFilter", Const, 0, ""}, + {"SizeofSockFprog", Const, 0, ""}, + {"SizeofSockaddrAny", Const, 0, ""}, + {"SizeofSockaddrDatalink", Const, 0, ""}, + {"SizeofSockaddrInet4", Const, 0, ""}, + {"SizeofSockaddrInet6", Const, 0, ""}, + {"SizeofSockaddrLinklayer", Const, 0, ""}, + {"SizeofSockaddrNetlink", Const, 0, ""}, + {"SizeofSockaddrUnix", Const, 0, ""}, + {"SizeofTCPInfo", Const, 1, ""}, + {"SizeofUcred", Const, 0, ""}, + {"SlicePtrFromStrings", Func, 1, "func(ss []string) ([]*byte, error)"}, + {"SockFilter", Type, 0, ""}, + {"SockFilter.Code", Field, 0, ""}, + {"SockFilter.Jf", Field, 0, ""}, + {"SockFilter.Jt", Field, 0, ""}, + {"SockFilter.K", Field, 0, ""}, + {"SockFprog", Type, 0, ""}, + {"SockFprog.Filter", Field, 0, ""}, + {"SockFprog.Len", Field, 0, ""}, + {"SockFprog.Pad_cgo_0", Field, 0, ""}, + {"Sockaddr", Type, 0, ""}, + {"SockaddrDatalink", Type, 0, ""}, + {"SockaddrDatalink.Alen", Field, 0, ""}, + {"SockaddrDatalink.Data", Field, 0, ""}, + {"SockaddrDatalink.Family", Field, 0, ""}, + {"SockaddrDatalink.Index", Field, 0, ""}, + {"SockaddrDatalink.Len", Field, 0, ""}, + {"SockaddrDatalink.Nlen", Field, 0, ""}, + {"SockaddrDatalink.Slen", Field, 0, ""}, + {"SockaddrDatalink.Type", Field, 0, ""}, + {"SockaddrGen", Type, 0, ""}, + {"SockaddrInet4", Type, 0, ""}, + {"SockaddrInet4.Addr", Field, 0, ""}, + {"SockaddrInet4.Port", Field, 0, ""}, + {"SockaddrInet6", Type, 0, ""}, + {"SockaddrInet6.Addr", Field, 0, ""}, + {"SockaddrInet6.Port", Field, 0, ""}, + {"SockaddrInet6.ZoneId", Field, 0, ""}, + {"SockaddrLinklayer", Type, 0, ""}, + {"SockaddrLinklayer.Addr", Field, 0, ""}, + {"SockaddrLinklayer.Halen", Field, 0, ""}, + {"SockaddrLinklayer.Hatype", Field, 0, ""}, + {"SockaddrLinklayer.Ifindex", Field, 0, ""}, + {"SockaddrLinklayer.Pkttype", Field, 0, ""}, + {"SockaddrLinklayer.Protocol", Field, 0, ""}, + {"SockaddrNetlink", Type, 0, ""}, + {"SockaddrNetlink.Family", Field, 0, ""}, + {"SockaddrNetlink.Groups", Field, 0, ""}, + {"SockaddrNetlink.Pad", Field, 0, ""}, + {"SockaddrNetlink.Pid", Field, 0, ""}, + {"SockaddrUnix", Type, 0, ""}, + {"SockaddrUnix.Name", Field, 0, ""}, + {"Socket", Func, 0, "func(domain int, typ int, proto int) (fd int, err error)"}, + {"SocketControlMessage", Type, 0, ""}, + {"SocketControlMessage.Data", Field, 0, ""}, + {"SocketControlMessage.Header", Field, 0, ""}, + {"SocketDisableIPv6", Var, 0, ""}, + {"Socketpair", Func, 0, "func(domain int, typ int, proto int) (fd [2]int, err error)"}, + {"Splice", Func, 0, "func(rfd int, roff *int64, wfd int, woff *int64, len int, flags int) (n int64, err error)"}, + {"StartProcess", Func, 0, "func(argv0 string, argv []string, attr *ProcAttr) (pid int, handle uintptr, err error)"}, + {"StartupInfo", Type, 0, ""}, + {"StartupInfo.Cb", Field, 0, ""}, + {"StartupInfo.Desktop", Field, 0, ""}, + {"StartupInfo.FillAttribute", Field, 0, ""}, + {"StartupInfo.Flags", Field, 0, ""}, + {"StartupInfo.ShowWindow", Field, 0, ""}, + {"StartupInfo.StdErr", Field, 0, ""}, + {"StartupInfo.StdInput", Field, 0, ""}, + {"StartupInfo.StdOutput", Field, 0, ""}, + {"StartupInfo.Title", Field, 0, ""}, + {"StartupInfo.X", Field, 0, ""}, + {"StartupInfo.XCountChars", Field, 0, ""}, + {"StartupInfo.XSize", Field, 0, ""}, + {"StartupInfo.Y", Field, 0, ""}, + {"StartupInfo.YCountChars", Field, 0, ""}, + {"StartupInfo.YSize", Field, 0, ""}, + {"Stat", Func, 0, "func(path string, stat *Stat_t) (err error)"}, + {"Stat_t", Type, 0, ""}, + {"Stat_t.Atim", Field, 0, ""}, + {"Stat_t.Atim_ext", Field, 12, ""}, + {"Stat_t.Atimespec", Field, 0, ""}, + {"Stat_t.Birthtimespec", Field, 0, ""}, + {"Stat_t.Blksize", Field, 0, ""}, + {"Stat_t.Blocks", Field, 0, ""}, + {"Stat_t.Btim_ext", Field, 12, ""}, + {"Stat_t.Ctim", Field, 0, ""}, + {"Stat_t.Ctim_ext", Field, 12, ""}, + {"Stat_t.Ctimespec", Field, 0, ""}, + {"Stat_t.Dev", Field, 0, ""}, + {"Stat_t.Flags", Field, 0, ""}, + {"Stat_t.Gen", Field, 0, ""}, + {"Stat_t.Gid", Field, 0, ""}, + {"Stat_t.Ino", Field, 0, ""}, + {"Stat_t.Lspare", Field, 0, ""}, + {"Stat_t.Lspare0", Field, 2, ""}, + {"Stat_t.Lspare1", Field, 2, ""}, + {"Stat_t.Mode", Field, 0, ""}, + {"Stat_t.Mtim", Field, 0, ""}, + {"Stat_t.Mtim_ext", Field, 12, ""}, + {"Stat_t.Mtimespec", Field, 0, ""}, + {"Stat_t.Nlink", Field, 0, ""}, + {"Stat_t.Pad_cgo_0", Field, 0, ""}, + {"Stat_t.Pad_cgo_1", Field, 0, ""}, + {"Stat_t.Pad_cgo_2", Field, 0, ""}, + {"Stat_t.Padding0", Field, 12, ""}, + {"Stat_t.Padding1", Field, 12, ""}, + {"Stat_t.Qspare", Field, 0, ""}, + {"Stat_t.Rdev", Field, 0, ""}, + {"Stat_t.Size", Field, 0, ""}, + {"Stat_t.Spare", Field, 2, ""}, + {"Stat_t.Uid", Field, 0, ""}, + {"Stat_t.X__pad0", Field, 0, ""}, + {"Stat_t.X__pad1", Field, 0, ""}, + {"Stat_t.X__pad2", Field, 0, ""}, + {"Stat_t.X__st_birthtim", Field, 2, ""}, + {"Stat_t.X__st_ino", Field, 0, ""}, + {"Stat_t.X__unused", Field, 0, ""}, + {"Statfs", Func, 0, "func(path string, buf *Statfs_t) (err error)"}, + {"Statfs_t", Type, 0, ""}, + {"Statfs_t.Asyncreads", Field, 0, ""}, + {"Statfs_t.Asyncwrites", Field, 0, ""}, + {"Statfs_t.Bavail", Field, 0, ""}, + {"Statfs_t.Bfree", Field, 0, ""}, + {"Statfs_t.Blocks", Field, 0, ""}, + {"Statfs_t.Bsize", Field, 0, ""}, + {"Statfs_t.Charspare", Field, 0, ""}, + {"Statfs_t.F_asyncreads", Field, 2, ""}, + {"Statfs_t.F_asyncwrites", Field, 2, ""}, + {"Statfs_t.F_bavail", Field, 2, ""}, + {"Statfs_t.F_bfree", Field, 2, ""}, + {"Statfs_t.F_blocks", Field, 2, ""}, + {"Statfs_t.F_bsize", Field, 2, ""}, + {"Statfs_t.F_ctime", Field, 2, ""}, + {"Statfs_t.F_favail", Field, 2, ""}, + {"Statfs_t.F_ffree", Field, 2, ""}, + {"Statfs_t.F_files", Field, 2, ""}, + {"Statfs_t.F_flags", Field, 2, ""}, + {"Statfs_t.F_fsid", Field, 2, ""}, + {"Statfs_t.F_fstypename", Field, 2, ""}, + {"Statfs_t.F_iosize", Field, 2, ""}, + {"Statfs_t.F_mntfromname", Field, 2, ""}, + {"Statfs_t.F_mntfromspec", Field, 3, ""}, + {"Statfs_t.F_mntonname", Field, 2, ""}, + {"Statfs_t.F_namemax", Field, 2, ""}, + {"Statfs_t.F_owner", Field, 2, ""}, + {"Statfs_t.F_spare", Field, 2, ""}, + {"Statfs_t.F_syncreads", Field, 2, ""}, + {"Statfs_t.F_syncwrites", Field, 2, ""}, + {"Statfs_t.Ffree", Field, 0, ""}, + {"Statfs_t.Files", Field, 0, ""}, + {"Statfs_t.Flags", Field, 0, ""}, + {"Statfs_t.Frsize", Field, 0, ""}, + {"Statfs_t.Fsid", Field, 0, ""}, + {"Statfs_t.Fssubtype", Field, 0, ""}, + {"Statfs_t.Fstypename", Field, 0, ""}, + {"Statfs_t.Iosize", Field, 0, ""}, + {"Statfs_t.Mntfromname", Field, 0, ""}, + {"Statfs_t.Mntonname", Field, 0, ""}, + {"Statfs_t.Mount_info", Field, 2, ""}, + {"Statfs_t.Namelen", Field, 0, ""}, + {"Statfs_t.Namemax", Field, 0, ""}, + {"Statfs_t.Owner", Field, 0, ""}, + {"Statfs_t.Pad_cgo_0", Field, 0, ""}, + {"Statfs_t.Pad_cgo_1", Field, 2, ""}, + {"Statfs_t.Reserved", Field, 0, ""}, + {"Statfs_t.Spare", Field, 0, ""}, + {"Statfs_t.Syncreads", Field, 0, ""}, + {"Statfs_t.Syncwrites", Field, 0, ""}, + {"Statfs_t.Type", Field, 0, ""}, + {"Statfs_t.Version", Field, 0, ""}, + {"Stderr", Var, 0, ""}, + {"Stdin", Var, 0, ""}, + {"Stdout", Var, 0, ""}, + {"StringBytePtr", Func, 0, "func(s string) *byte"}, + {"StringByteSlice", Func, 0, "func(s string) []byte"}, + {"StringSlicePtr", Func, 0, "func(ss []string) []*byte"}, + {"StringToSid", Func, 0, ""}, + {"StringToUTF16", Func, 0, ""}, + {"StringToUTF16Ptr", Func, 0, ""}, + {"Symlink", Func, 0, "func(oldpath string, newpath string) (err error)"}, + {"Sync", Func, 0, "func()"}, + {"SyncFileRange", Func, 0, "func(fd int, off int64, n int64, flags int) (err error)"}, + {"SysProcAttr", Type, 0, ""}, + {"SysProcAttr.AdditionalInheritedHandles", Field, 17, ""}, + {"SysProcAttr.AmbientCaps", Field, 9, ""}, + {"SysProcAttr.CgroupFD", Field, 20, ""}, + {"SysProcAttr.Chroot", Field, 0, ""}, + {"SysProcAttr.Cloneflags", Field, 2, ""}, + {"SysProcAttr.CmdLine", Field, 0, ""}, + {"SysProcAttr.CreationFlags", Field, 1, ""}, + {"SysProcAttr.Credential", Field, 0, ""}, + {"SysProcAttr.Ctty", Field, 1, ""}, + {"SysProcAttr.Foreground", Field, 5, ""}, + {"SysProcAttr.GidMappings", Field, 4, ""}, + {"SysProcAttr.GidMappingsEnableSetgroups", Field, 5, ""}, + {"SysProcAttr.HideWindow", Field, 0, ""}, + {"SysProcAttr.Jail", Field, 21, ""}, + {"SysProcAttr.NoInheritHandles", Field, 16, ""}, + {"SysProcAttr.Noctty", Field, 0, ""}, + {"SysProcAttr.ParentProcess", Field, 17, ""}, + {"SysProcAttr.Pdeathsig", Field, 0, ""}, + {"SysProcAttr.Pgid", Field, 5, ""}, + {"SysProcAttr.PidFD", Field, 22, ""}, + {"SysProcAttr.ProcessAttributes", Field, 13, ""}, + {"SysProcAttr.Ptrace", Field, 0, ""}, + {"SysProcAttr.Setctty", Field, 0, ""}, + {"SysProcAttr.Setpgid", Field, 0, ""}, + {"SysProcAttr.Setsid", Field, 0, ""}, + {"SysProcAttr.ThreadAttributes", Field, 13, ""}, + {"SysProcAttr.Token", Field, 10, ""}, + {"SysProcAttr.UidMappings", Field, 4, ""}, + {"SysProcAttr.Unshareflags", Field, 7, ""}, + {"SysProcAttr.UseCgroupFD", Field, 20, ""}, + {"SysProcIDMap", Type, 4, ""}, + {"SysProcIDMap.ContainerID", Field, 4, ""}, + {"SysProcIDMap.HostID", Field, 4, ""}, + {"SysProcIDMap.Size", Field, 4, ""}, + {"Syscall", Func, 0, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, + {"Syscall12", Func, 0, ""}, + {"Syscall15", Func, 0, ""}, + {"Syscall18", Func, 12, ""}, + {"Syscall6", Func, 0, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr, a4 uintptr, a5 uintptr, a6 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, + {"Syscall9", Func, 0, ""}, + {"SyscallN", Func, 18, ""}, + {"Sysctl", Func, 0, ""}, + {"SysctlUint32", Func, 0, ""}, + {"Sysctlnode", Type, 2, ""}, + {"Sysctlnode.Flags", Field, 2, ""}, + {"Sysctlnode.Name", Field, 2, ""}, + {"Sysctlnode.Num", Field, 2, ""}, + {"Sysctlnode.Un", Field, 2, ""}, + {"Sysctlnode.Ver", Field, 2, ""}, + {"Sysctlnode.X__rsvd", Field, 2, ""}, + {"Sysctlnode.X_sysctl_desc", Field, 2, ""}, + {"Sysctlnode.X_sysctl_func", Field, 2, ""}, + {"Sysctlnode.X_sysctl_parent", Field, 2, ""}, + {"Sysctlnode.X_sysctl_size", Field, 2, ""}, + {"Sysinfo", Func, 0, "func(info *Sysinfo_t) (err error)"}, + {"Sysinfo_t", Type, 0, ""}, + {"Sysinfo_t.Bufferram", Field, 0, ""}, + {"Sysinfo_t.Freehigh", Field, 0, ""}, + {"Sysinfo_t.Freeram", Field, 0, ""}, + {"Sysinfo_t.Freeswap", Field, 0, ""}, + {"Sysinfo_t.Loads", Field, 0, ""}, + {"Sysinfo_t.Pad", Field, 0, ""}, + {"Sysinfo_t.Pad_cgo_0", Field, 0, ""}, + {"Sysinfo_t.Pad_cgo_1", Field, 0, ""}, + {"Sysinfo_t.Procs", Field, 0, ""}, + {"Sysinfo_t.Sharedram", Field, 0, ""}, + {"Sysinfo_t.Totalhigh", Field, 0, ""}, + {"Sysinfo_t.Totalram", Field, 0, ""}, + {"Sysinfo_t.Totalswap", Field, 0, ""}, + {"Sysinfo_t.Unit", Field, 0, ""}, + {"Sysinfo_t.Uptime", Field, 0, ""}, + {"Sysinfo_t.X_f", Field, 0, ""}, + {"Systemtime", Type, 0, ""}, + {"Systemtime.Day", Field, 0, ""}, + {"Systemtime.DayOfWeek", Field, 0, ""}, + {"Systemtime.Hour", Field, 0, ""}, + {"Systemtime.Milliseconds", Field, 0, ""}, + {"Systemtime.Minute", Field, 0, ""}, + {"Systemtime.Month", Field, 0, ""}, + {"Systemtime.Second", Field, 0, ""}, + {"Systemtime.Year", Field, 0, ""}, + {"TCGETS", Const, 0, ""}, + {"TCIFLUSH", Const, 1, ""}, + {"TCIOFLUSH", Const, 1, ""}, + {"TCOFLUSH", Const, 1, ""}, + {"TCPInfo", Type, 1, ""}, + {"TCPInfo.Advmss", Field, 1, ""}, + {"TCPInfo.Ato", Field, 1, ""}, + {"TCPInfo.Backoff", Field, 1, ""}, + {"TCPInfo.Ca_state", Field, 1, ""}, + {"TCPInfo.Fackets", Field, 1, ""}, + {"TCPInfo.Last_ack_recv", Field, 1, ""}, + {"TCPInfo.Last_ack_sent", Field, 1, ""}, + {"TCPInfo.Last_data_recv", Field, 1, ""}, + {"TCPInfo.Last_data_sent", Field, 1, ""}, + {"TCPInfo.Lost", Field, 1, ""}, + {"TCPInfo.Options", Field, 1, ""}, + {"TCPInfo.Pad_cgo_0", Field, 1, ""}, + {"TCPInfo.Pmtu", Field, 1, ""}, + {"TCPInfo.Probes", Field, 1, ""}, + {"TCPInfo.Rcv_mss", Field, 1, ""}, + {"TCPInfo.Rcv_rtt", Field, 1, ""}, + {"TCPInfo.Rcv_space", Field, 1, ""}, + {"TCPInfo.Rcv_ssthresh", Field, 1, ""}, + {"TCPInfo.Reordering", Field, 1, ""}, + {"TCPInfo.Retrans", Field, 1, ""}, + {"TCPInfo.Retransmits", Field, 1, ""}, + {"TCPInfo.Rto", Field, 1, ""}, + {"TCPInfo.Rtt", Field, 1, ""}, + {"TCPInfo.Rttvar", Field, 1, ""}, + {"TCPInfo.Sacked", Field, 1, ""}, + {"TCPInfo.Snd_cwnd", Field, 1, ""}, + {"TCPInfo.Snd_mss", Field, 1, ""}, + {"TCPInfo.Snd_ssthresh", Field, 1, ""}, + {"TCPInfo.State", Field, 1, ""}, + {"TCPInfo.Total_retrans", Field, 1, ""}, + {"TCPInfo.Unacked", Field, 1, ""}, + {"TCPKeepalive", Type, 3, ""}, + {"TCPKeepalive.Interval", Field, 3, ""}, + {"TCPKeepalive.OnOff", Field, 3, ""}, + {"TCPKeepalive.Time", Field, 3, ""}, + {"TCP_CA_NAME_MAX", Const, 0, ""}, + {"TCP_CONGCTL", Const, 1, ""}, + {"TCP_CONGESTION", Const, 0, ""}, + {"TCP_CONNECTIONTIMEOUT", Const, 0, ""}, + {"TCP_CORK", Const, 0, ""}, + {"TCP_DEFER_ACCEPT", Const, 0, ""}, + {"TCP_ENABLE_ECN", Const, 16, ""}, + {"TCP_INFO", Const, 0, ""}, + {"TCP_KEEPALIVE", Const, 0, ""}, + {"TCP_KEEPCNT", Const, 0, ""}, + {"TCP_KEEPIDLE", Const, 0, ""}, + {"TCP_KEEPINIT", Const, 1, ""}, + {"TCP_KEEPINTVL", Const, 0, ""}, + {"TCP_LINGER2", Const, 0, ""}, + {"TCP_MAXBURST", Const, 0, ""}, + {"TCP_MAXHLEN", Const, 0, ""}, + {"TCP_MAXOLEN", Const, 0, ""}, + {"TCP_MAXSEG", Const, 0, ""}, + {"TCP_MAXWIN", Const, 0, ""}, + {"TCP_MAX_SACK", Const, 0, ""}, + {"TCP_MAX_WINSHIFT", Const, 0, ""}, + {"TCP_MD5SIG", Const, 0, ""}, + {"TCP_MD5SIG_MAXKEYLEN", Const, 0, ""}, + {"TCP_MINMSS", Const, 0, ""}, + {"TCP_MINMSSOVERLOAD", Const, 0, ""}, + {"TCP_MSS", Const, 0, ""}, + {"TCP_NODELAY", Const, 0, ""}, + {"TCP_NOOPT", Const, 0, ""}, + {"TCP_NOPUSH", Const, 0, ""}, + {"TCP_NOTSENT_LOWAT", Const, 16, ""}, + {"TCP_NSTATES", Const, 1, ""}, + {"TCP_QUICKACK", Const, 0, ""}, + {"TCP_RXT_CONNDROPTIME", Const, 0, ""}, + {"TCP_RXT_FINDROP", Const, 0, ""}, + {"TCP_SACK_ENABLE", Const, 1, ""}, + {"TCP_SENDMOREACKS", Const, 16, ""}, + {"TCP_SYNCNT", Const, 0, ""}, + {"TCP_VENDOR", Const, 3, ""}, + {"TCP_WINDOW_CLAMP", Const, 0, ""}, + {"TCSAFLUSH", Const, 1, ""}, + {"TCSETS", Const, 0, ""}, + {"TF_DISCONNECT", Const, 0, ""}, + {"TF_REUSE_SOCKET", Const, 0, ""}, + {"TF_USE_DEFAULT_WORKER", Const, 0, ""}, + {"TF_USE_KERNEL_APC", Const, 0, ""}, + {"TF_USE_SYSTEM_THREAD", Const, 0, ""}, + {"TF_WRITE_BEHIND", Const, 0, ""}, + {"TH32CS_INHERIT", Const, 4, ""}, + {"TH32CS_SNAPALL", Const, 4, ""}, + {"TH32CS_SNAPHEAPLIST", Const, 4, ""}, + {"TH32CS_SNAPMODULE", Const, 4, ""}, + {"TH32CS_SNAPMODULE32", Const, 4, ""}, + {"TH32CS_SNAPPROCESS", Const, 4, ""}, + {"TH32CS_SNAPTHREAD", Const, 4, ""}, + {"TIME_ZONE_ID_DAYLIGHT", Const, 0, ""}, + {"TIME_ZONE_ID_STANDARD", Const, 0, ""}, + {"TIME_ZONE_ID_UNKNOWN", Const, 0, ""}, + {"TIOCCBRK", Const, 0, ""}, + {"TIOCCDTR", Const, 0, ""}, + {"TIOCCONS", Const, 0, ""}, + {"TIOCDCDTIMESTAMP", Const, 0, ""}, + {"TIOCDRAIN", Const, 0, ""}, + {"TIOCDSIMICROCODE", Const, 0, ""}, + {"TIOCEXCL", Const, 0, ""}, + {"TIOCEXT", Const, 0, ""}, + {"TIOCFLAG_CDTRCTS", Const, 1, ""}, + {"TIOCFLAG_CLOCAL", Const, 1, ""}, + {"TIOCFLAG_CRTSCTS", Const, 1, ""}, + {"TIOCFLAG_MDMBUF", Const, 1, ""}, + {"TIOCFLAG_PPS", Const, 1, ""}, + {"TIOCFLAG_SOFTCAR", Const, 1, ""}, + {"TIOCFLUSH", Const, 0, ""}, + {"TIOCGDEV", Const, 0, ""}, + {"TIOCGDRAINWAIT", Const, 0, ""}, + {"TIOCGETA", Const, 0, ""}, + {"TIOCGETD", Const, 0, ""}, + {"TIOCGFLAGS", Const, 1, ""}, + {"TIOCGICOUNT", Const, 0, ""}, + {"TIOCGLCKTRMIOS", Const, 0, ""}, + {"TIOCGLINED", Const, 1, ""}, + {"TIOCGPGRP", Const, 0, ""}, + {"TIOCGPTN", Const, 0, ""}, + {"TIOCGQSIZE", Const, 1, ""}, + {"TIOCGRANTPT", Const, 1, ""}, + {"TIOCGRS485", Const, 0, ""}, + {"TIOCGSERIAL", Const, 0, ""}, + {"TIOCGSID", Const, 0, ""}, + {"TIOCGSIZE", Const, 1, ""}, + {"TIOCGSOFTCAR", Const, 0, ""}, + {"TIOCGTSTAMP", Const, 1, ""}, + {"TIOCGWINSZ", Const, 0, ""}, + {"TIOCINQ", Const, 0, ""}, + {"TIOCIXOFF", Const, 0, ""}, + {"TIOCIXON", Const, 0, ""}, + {"TIOCLINUX", Const, 0, ""}, + {"TIOCMBIC", Const, 0, ""}, + {"TIOCMBIS", Const, 0, ""}, + {"TIOCMGDTRWAIT", Const, 0, ""}, + {"TIOCMGET", Const, 0, ""}, + {"TIOCMIWAIT", Const, 0, ""}, + {"TIOCMODG", Const, 0, ""}, + {"TIOCMODS", Const, 0, ""}, + {"TIOCMSDTRWAIT", Const, 0, ""}, + {"TIOCMSET", Const, 0, ""}, + {"TIOCM_CAR", Const, 0, ""}, + {"TIOCM_CD", Const, 0, ""}, + {"TIOCM_CTS", Const, 0, ""}, + {"TIOCM_DCD", Const, 0, ""}, + {"TIOCM_DSR", Const, 0, ""}, + {"TIOCM_DTR", Const, 0, ""}, + {"TIOCM_LE", Const, 0, ""}, + {"TIOCM_RI", Const, 0, ""}, + {"TIOCM_RNG", Const, 0, ""}, + {"TIOCM_RTS", Const, 0, ""}, + {"TIOCM_SR", Const, 0, ""}, + {"TIOCM_ST", Const, 0, ""}, + {"TIOCNOTTY", Const, 0, ""}, + {"TIOCNXCL", Const, 0, ""}, + {"TIOCOUTQ", Const, 0, ""}, + {"TIOCPKT", Const, 0, ""}, + {"TIOCPKT_DATA", Const, 0, ""}, + {"TIOCPKT_DOSTOP", Const, 0, ""}, + {"TIOCPKT_FLUSHREAD", Const, 0, ""}, + {"TIOCPKT_FLUSHWRITE", Const, 0, ""}, + {"TIOCPKT_IOCTL", Const, 0, ""}, + {"TIOCPKT_NOSTOP", Const, 0, ""}, + {"TIOCPKT_START", Const, 0, ""}, + {"TIOCPKT_STOP", Const, 0, ""}, + {"TIOCPTMASTER", Const, 0, ""}, + {"TIOCPTMGET", Const, 1, ""}, + {"TIOCPTSNAME", Const, 1, ""}, + {"TIOCPTYGNAME", Const, 0, ""}, + {"TIOCPTYGRANT", Const, 0, ""}, + {"TIOCPTYUNLK", Const, 0, ""}, + {"TIOCRCVFRAME", Const, 1, ""}, + {"TIOCREMOTE", Const, 0, ""}, + {"TIOCSBRK", Const, 0, ""}, + {"TIOCSCONS", Const, 0, ""}, + {"TIOCSCTTY", Const, 0, ""}, + {"TIOCSDRAINWAIT", Const, 0, ""}, + {"TIOCSDTR", Const, 0, ""}, + {"TIOCSERCONFIG", Const, 0, ""}, + {"TIOCSERGETLSR", Const, 0, ""}, + {"TIOCSERGETMULTI", Const, 0, ""}, + {"TIOCSERGSTRUCT", Const, 0, ""}, + {"TIOCSERGWILD", Const, 0, ""}, + {"TIOCSERSETMULTI", Const, 0, ""}, + {"TIOCSERSWILD", Const, 0, ""}, + {"TIOCSER_TEMT", Const, 0, ""}, + {"TIOCSETA", Const, 0, ""}, + {"TIOCSETAF", Const, 0, ""}, + {"TIOCSETAW", Const, 0, ""}, + {"TIOCSETD", Const, 0, ""}, + {"TIOCSFLAGS", Const, 1, ""}, + {"TIOCSIG", Const, 0, ""}, + {"TIOCSLCKTRMIOS", Const, 0, ""}, + {"TIOCSLINED", Const, 1, ""}, + {"TIOCSPGRP", Const, 0, ""}, + {"TIOCSPTLCK", Const, 0, ""}, + {"TIOCSQSIZE", Const, 1, ""}, + {"TIOCSRS485", Const, 0, ""}, + {"TIOCSSERIAL", Const, 0, ""}, + {"TIOCSSIZE", Const, 1, ""}, + {"TIOCSSOFTCAR", Const, 0, ""}, + {"TIOCSTART", Const, 0, ""}, + {"TIOCSTAT", Const, 0, ""}, + {"TIOCSTI", Const, 0, ""}, + {"TIOCSTOP", Const, 0, ""}, + {"TIOCSTSTAMP", Const, 1, ""}, + {"TIOCSWINSZ", Const, 0, ""}, + {"TIOCTIMESTAMP", Const, 0, ""}, + {"TIOCUCNTL", Const, 0, ""}, + {"TIOCVHANGUP", Const, 0, ""}, + {"TIOCXMTFRAME", Const, 1, ""}, + {"TOKEN_ADJUST_DEFAULT", Const, 0, ""}, + {"TOKEN_ADJUST_GROUPS", Const, 0, ""}, + {"TOKEN_ADJUST_PRIVILEGES", Const, 0, ""}, + {"TOKEN_ADJUST_SESSIONID", Const, 11, ""}, + {"TOKEN_ALL_ACCESS", Const, 0, ""}, + {"TOKEN_ASSIGN_PRIMARY", Const, 0, ""}, + {"TOKEN_DUPLICATE", Const, 0, ""}, + {"TOKEN_EXECUTE", Const, 0, ""}, + {"TOKEN_IMPERSONATE", Const, 0, ""}, + {"TOKEN_QUERY", Const, 0, ""}, + {"TOKEN_QUERY_SOURCE", Const, 0, ""}, + {"TOKEN_READ", Const, 0, ""}, + {"TOKEN_WRITE", Const, 0, ""}, + {"TOSTOP", Const, 0, ""}, + {"TRUNCATE_EXISTING", Const, 0, ""}, + {"TUNATTACHFILTER", Const, 0, ""}, + {"TUNDETACHFILTER", Const, 0, ""}, + {"TUNGETFEATURES", Const, 0, ""}, + {"TUNGETIFF", Const, 0, ""}, + {"TUNGETSNDBUF", Const, 0, ""}, + {"TUNGETVNETHDRSZ", Const, 0, ""}, + {"TUNSETDEBUG", Const, 0, ""}, + {"TUNSETGROUP", Const, 0, ""}, + {"TUNSETIFF", Const, 0, ""}, + {"TUNSETLINK", Const, 0, ""}, + {"TUNSETNOCSUM", Const, 0, ""}, + {"TUNSETOFFLOAD", Const, 0, ""}, + {"TUNSETOWNER", Const, 0, ""}, + {"TUNSETPERSIST", Const, 0, ""}, + {"TUNSETSNDBUF", Const, 0, ""}, + {"TUNSETTXFILTER", Const, 0, ""}, + {"TUNSETVNETHDRSZ", Const, 0, ""}, + {"Tee", Func, 0, "func(rfd int, wfd int, len int, flags int) (n int64, err error)"}, + {"TerminateProcess", Func, 0, ""}, + {"Termios", Type, 0, ""}, + {"Termios.Cc", Field, 0, ""}, + {"Termios.Cflag", Field, 0, ""}, + {"Termios.Iflag", Field, 0, ""}, + {"Termios.Ispeed", Field, 0, ""}, + {"Termios.Lflag", Field, 0, ""}, + {"Termios.Line", Field, 0, ""}, + {"Termios.Oflag", Field, 0, ""}, + {"Termios.Ospeed", Field, 0, ""}, + {"Termios.Pad_cgo_0", Field, 0, ""}, + {"Tgkill", Func, 0, "func(tgid int, tid int, sig Signal) (err error)"}, + {"Time", Func, 0, "func(t *Time_t) (tt Time_t, err error)"}, + {"Time_t", Type, 0, ""}, + {"Times", Func, 0, "func(tms *Tms) (ticks uintptr, err error)"}, + {"Timespec", Type, 0, ""}, + {"Timespec.Nsec", Field, 0, ""}, + {"Timespec.Pad_cgo_0", Field, 2, ""}, + {"Timespec.Sec", Field, 0, ""}, + {"TimespecToNsec", Func, 0, "func(ts Timespec) int64"}, + {"Timeval", Type, 0, ""}, + {"Timeval.Pad_cgo_0", Field, 0, ""}, + {"Timeval.Sec", Field, 0, ""}, + {"Timeval.Usec", Field, 0, ""}, + {"Timeval32", Type, 0, ""}, + {"Timeval32.Sec", Field, 0, ""}, + {"Timeval32.Usec", Field, 0, ""}, + {"TimevalToNsec", Func, 0, "func(tv Timeval) int64"}, + {"Timex", Type, 0, ""}, + {"Timex.Calcnt", Field, 0, ""}, + {"Timex.Constant", Field, 0, ""}, + {"Timex.Errcnt", Field, 0, ""}, + {"Timex.Esterror", Field, 0, ""}, + {"Timex.Freq", Field, 0, ""}, + {"Timex.Jitcnt", Field, 0, ""}, + {"Timex.Jitter", Field, 0, ""}, + {"Timex.Maxerror", Field, 0, ""}, + {"Timex.Modes", Field, 0, ""}, + {"Timex.Offset", Field, 0, ""}, + {"Timex.Pad_cgo_0", Field, 0, ""}, + {"Timex.Pad_cgo_1", Field, 0, ""}, + {"Timex.Pad_cgo_2", Field, 0, ""}, + {"Timex.Pad_cgo_3", Field, 0, ""}, + {"Timex.Ppsfreq", Field, 0, ""}, + {"Timex.Precision", Field, 0, ""}, + {"Timex.Shift", Field, 0, ""}, + {"Timex.Stabil", Field, 0, ""}, + {"Timex.Status", Field, 0, ""}, + {"Timex.Stbcnt", Field, 0, ""}, + {"Timex.Tai", Field, 0, ""}, + {"Timex.Tick", Field, 0, ""}, + {"Timex.Time", Field, 0, ""}, + {"Timex.Tolerance", Field, 0, ""}, + {"Timezoneinformation", Type, 0, ""}, + {"Timezoneinformation.Bias", Field, 0, ""}, + {"Timezoneinformation.DaylightBias", Field, 0, ""}, + {"Timezoneinformation.DaylightDate", Field, 0, ""}, + {"Timezoneinformation.DaylightName", Field, 0, ""}, + {"Timezoneinformation.StandardBias", Field, 0, ""}, + {"Timezoneinformation.StandardDate", Field, 0, ""}, + {"Timezoneinformation.StandardName", Field, 0, ""}, + {"Tms", Type, 0, ""}, + {"Tms.Cstime", Field, 0, ""}, + {"Tms.Cutime", Field, 0, ""}, + {"Tms.Stime", Field, 0, ""}, + {"Tms.Utime", Field, 0, ""}, + {"Token", Type, 0, ""}, + {"TokenAccessInformation", Const, 0, ""}, + {"TokenAuditPolicy", Const, 0, ""}, + {"TokenDefaultDacl", Const, 0, ""}, + {"TokenElevation", Const, 0, ""}, + {"TokenElevationType", Const, 0, ""}, + {"TokenGroups", Const, 0, ""}, + {"TokenGroupsAndPrivileges", Const, 0, ""}, + {"TokenHasRestrictions", Const, 0, ""}, + {"TokenImpersonationLevel", Const, 0, ""}, + {"TokenIntegrityLevel", Const, 0, ""}, + {"TokenLinkedToken", Const, 0, ""}, + {"TokenLogonSid", Const, 0, ""}, + {"TokenMandatoryPolicy", Const, 0, ""}, + {"TokenOrigin", Const, 0, ""}, + {"TokenOwner", Const, 0, ""}, + {"TokenPrimaryGroup", Const, 0, ""}, + {"TokenPrivileges", Const, 0, ""}, + {"TokenRestrictedSids", Const, 0, ""}, + {"TokenSandBoxInert", Const, 0, ""}, + {"TokenSessionId", Const, 0, ""}, + {"TokenSessionReference", Const, 0, ""}, + {"TokenSource", Const, 0, ""}, + {"TokenStatistics", Const, 0, ""}, + {"TokenType", Const, 0, ""}, + {"TokenUIAccess", Const, 0, ""}, + {"TokenUser", Const, 0, ""}, + {"TokenVirtualizationAllowed", Const, 0, ""}, + {"TokenVirtualizationEnabled", Const, 0, ""}, + {"Tokenprimarygroup", Type, 0, ""}, + {"Tokenprimarygroup.PrimaryGroup", Field, 0, ""}, + {"Tokenuser", Type, 0, ""}, + {"Tokenuser.User", Field, 0, ""}, + {"TranslateAccountName", Func, 0, ""}, + {"TranslateName", Func, 0, ""}, + {"TransmitFile", Func, 0, ""}, + {"TransmitFileBuffers", Type, 0, ""}, + {"TransmitFileBuffers.Head", Field, 0, ""}, + {"TransmitFileBuffers.HeadLength", Field, 0, ""}, + {"TransmitFileBuffers.Tail", Field, 0, ""}, + {"TransmitFileBuffers.TailLength", Field, 0, ""}, + {"Truncate", Func, 0, "func(path string, length int64) (err error)"}, + {"UNIX_PATH_MAX", Const, 12, ""}, + {"USAGE_MATCH_TYPE_AND", Const, 0, ""}, + {"USAGE_MATCH_TYPE_OR", Const, 0, ""}, + {"UTF16FromString", Func, 1, ""}, + {"UTF16PtrFromString", Func, 1, ""}, + {"UTF16ToString", Func, 0, ""}, + {"Ucred", Type, 0, ""}, + {"Ucred.Gid", Field, 0, ""}, + {"Ucred.Pid", Field, 0, ""}, + {"Ucred.Uid", Field, 0, ""}, + {"Umask", Func, 0, "func(mask int) (oldmask int)"}, + {"Uname", Func, 0, "func(buf *Utsname) (err error)"}, + {"Undelete", Func, 0, ""}, + {"UnixCredentials", Func, 0, "func(ucred *Ucred) []byte"}, + {"UnixRights", Func, 0, "func(fds ...int) []byte"}, + {"Unlink", Func, 0, "func(path string) error"}, + {"Unlinkat", Func, 0, "func(dirfd int, path string) error"}, + {"UnmapViewOfFile", Func, 0, ""}, + {"Unmount", Func, 0, "func(target string, flags int) (err error)"}, + {"Unsetenv", Func, 4, "func(key string) error"}, + {"Unshare", Func, 0, "func(flags int) (err error)"}, + {"UserInfo10", Type, 0, ""}, + {"UserInfo10.Comment", Field, 0, ""}, + {"UserInfo10.FullName", Field, 0, ""}, + {"UserInfo10.Name", Field, 0, ""}, + {"UserInfo10.UsrComment", Field, 0, ""}, + {"Ustat", Func, 0, "func(dev int, ubuf *Ustat_t) (err error)"}, + {"Ustat_t", Type, 0, ""}, + {"Ustat_t.Fname", Field, 0, ""}, + {"Ustat_t.Fpack", Field, 0, ""}, + {"Ustat_t.Pad_cgo_0", Field, 0, ""}, + {"Ustat_t.Pad_cgo_1", Field, 0, ""}, + {"Ustat_t.Tfree", Field, 0, ""}, + {"Ustat_t.Tinode", Field, 0, ""}, + {"Utimbuf", Type, 0, ""}, + {"Utimbuf.Actime", Field, 0, ""}, + {"Utimbuf.Modtime", Field, 0, ""}, + {"Utime", Func, 0, "func(path string, buf *Utimbuf) (err error)"}, + {"Utimes", Func, 0, "func(path string, tv []Timeval) (err error)"}, + {"UtimesNano", Func, 1, "func(path string, ts []Timespec) (err error)"}, + {"Utsname", Type, 0, ""}, + {"Utsname.Domainname", Field, 0, ""}, + {"Utsname.Machine", Field, 0, ""}, + {"Utsname.Nodename", Field, 0, ""}, + {"Utsname.Release", Field, 0, ""}, + {"Utsname.Sysname", Field, 0, ""}, + {"Utsname.Version", Field, 0, ""}, + {"VDISCARD", Const, 0, ""}, + {"VDSUSP", Const, 1, ""}, + {"VEOF", Const, 0, ""}, + {"VEOL", Const, 0, ""}, + {"VEOL2", Const, 0, ""}, + {"VERASE", Const, 0, ""}, + {"VERASE2", Const, 1, ""}, + {"VINTR", Const, 0, ""}, + {"VKILL", Const, 0, ""}, + {"VLNEXT", Const, 0, ""}, + {"VMIN", Const, 0, ""}, + {"VQUIT", Const, 0, ""}, + {"VREPRINT", Const, 0, ""}, + {"VSTART", Const, 0, ""}, + {"VSTATUS", Const, 1, ""}, + {"VSTOP", Const, 0, ""}, + {"VSUSP", Const, 0, ""}, + {"VSWTC", Const, 0, ""}, + {"VT0", Const, 1, ""}, + {"VT1", Const, 1, ""}, + {"VTDLY", Const, 1, ""}, + {"VTIME", Const, 0, ""}, + {"VWERASE", Const, 0, ""}, + {"VirtualLock", Func, 0, ""}, + {"VirtualUnlock", Func, 0, ""}, + {"WAIT_ABANDONED", Const, 0, ""}, + {"WAIT_FAILED", Const, 0, ""}, + {"WAIT_OBJECT_0", Const, 0, ""}, + {"WAIT_TIMEOUT", Const, 0, ""}, + {"WALL", Const, 0, ""}, + {"WALLSIG", Const, 1, ""}, + {"WALTSIG", Const, 1, ""}, + {"WCLONE", Const, 0, ""}, + {"WCONTINUED", Const, 0, ""}, + {"WCOREFLAG", Const, 0, ""}, + {"WEXITED", Const, 0, ""}, + {"WLINUXCLONE", Const, 0, ""}, + {"WNOHANG", Const, 0, ""}, + {"WNOTHREAD", Const, 0, ""}, + {"WNOWAIT", Const, 0, ""}, + {"WNOZOMBIE", Const, 1, ""}, + {"WOPTSCHECKED", Const, 1, ""}, + {"WORDSIZE", Const, 0, ""}, + {"WSABuf", Type, 0, ""}, + {"WSABuf.Buf", Field, 0, ""}, + {"WSABuf.Len", Field, 0, ""}, + {"WSACleanup", Func, 0, ""}, + {"WSADESCRIPTION_LEN", Const, 0, ""}, + {"WSAData", Type, 0, ""}, + {"WSAData.Description", Field, 0, ""}, + {"WSAData.HighVersion", Field, 0, ""}, + {"WSAData.MaxSockets", Field, 0, ""}, + {"WSAData.MaxUdpDg", Field, 0, ""}, + {"WSAData.SystemStatus", Field, 0, ""}, + {"WSAData.VendorInfo", Field, 0, ""}, + {"WSAData.Version", Field, 0, ""}, + {"WSAEACCES", Const, 2, ""}, + {"WSAECONNABORTED", Const, 9, ""}, + {"WSAECONNRESET", Const, 3, ""}, + {"WSAENOPROTOOPT", Const, 23, ""}, + {"WSAEnumProtocols", Func, 2, ""}, + {"WSAID_CONNECTEX", Var, 1, ""}, + {"WSAIoctl", Func, 0, ""}, + {"WSAPROTOCOL_LEN", Const, 2, ""}, + {"WSAProtocolChain", Type, 2, ""}, + {"WSAProtocolChain.ChainEntries", Field, 2, ""}, + {"WSAProtocolChain.ChainLen", Field, 2, ""}, + {"WSAProtocolInfo", Type, 2, ""}, + {"WSAProtocolInfo.AddressFamily", Field, 2, ""}, + {"WSAProtocolInfo.CatalogEntryId", Field, 2, ""}, + {"WSAProtocolInfo.MaxSockAddr", Field, 2, ""}, + {"WSAProtocolInfo.MessageSize", Field, 2, ""}, + {"WSAProtocolInfo.MinSockAddr", Field, 2, ""}, + {"WSAProtocolInfo.NetworkByteOrder", Field, 2, ""}, + {"WSAProtocolInfo.Protocol", Field, 2, ""}, + {"WSAProtocolInfo.ProtocolChain", Field, 2, ""}, + {"WSAProtocolInfo.ProtocolMaxOffset", Field, 2, ""}, + {"WSAProtocolInfo.ProtocolName", Field, 2, ""}, + {"WSAProtocolInfo.ProviderFlags", Field, 2, ""}, + {"WSAProtocolInfo.ProviderId", Field, 2, ""}, + {"WSAProtocolInfo.ProviderReserved", Field, 2, ""}, + {"WSAProtocolInfo.SecurityScheme", Field, 2, ""}, + {"WSAProtocolInfo.ServiceFlags1", Field, 2, ""}, + {"WSAProtocolInfo.ServiceFlags2", Field, 2, ""}, + {"WSAProtocolInfo.ServiceFlags3", Field, 2, ""}, + {"WSAProtocolInfo.ServiceFlags4", Field, 2, ""}, + {"WSAProtocolInfo.SocketType", Field, 2, ""}, + {"WSAProtocolInfo.Version", Field, 2, ""}, + {"WSARecv", Func, 0, ""}, + {"WSARecvFrom", Func, 0, ""}, + {"WSASYS_STATUS_LEN", Const, 0, ""}, + {"WSASend", Func, 0, ""}, + {"WSASendTo", Func, 0, ""}, + {"WSASendto", Func, 0, ""}, + {"WSAStartup", Func, 0, ""}, + {"WSTOPPED", Const, 0, ""}, + {"WTRAPPED", Const, 1, ""}, + {"WUNTRACED", Const, 0, ""}, + {"Wait4", Func, 0, "func(pid int, wstatus *WaitStatus, options int, rusage *Rusage) (wpid int, err error)"}, + {"WaitForSingleObject", Func, 0, ""}, + {"WaitStatus", Type, 0, ""}, + {"WaitStatus.ExitCode", Field, 0, ""}, + {"Win32FileAttributeData", Type, 0, ""}, + {"Win32FileAttributeData.CreationTime", Field, 0, ""}, + {"Win32FileAttributeData.FileAttributes", Field, 0, ""}, + {"Win32FileAttributeData.FileSizeHigh", Field, 0, ""}, + {"Win32FileAttributeData.FileSizeLow", Field, 0, ""}, + {"Win32FileAttributeData.LastAccessTime", Field, 0, ""}, + {"Win32FileAttributeData.LastWriteTime", Field, 0, ""}, + {"Win32finddata", Type, 0, ""}, + {"Win32finddata.AlternateFileName", Field, 0, ""}, + {"Win32finddata.CreationTime", Field, 0, ""}, + {"Win32finddata.FileAttributes", Field, 0, ""}, + {"Win32finddata.FileName", Field, 0, ""}, + {"Win32finddata.FileSizeHigh", Field, 0, ""}, + {"Win32finddata.FileSizeLow", Field, 0, ""}, + {"Win32finddata.LastAccessTime", Field, 0, ""}, + {"Win32finddata.LastWriteTime", Field, 0, ""}, + {"Win32finddata.Reserved0", Field, 0, ""}, + {"Win32finddata.Reserved1", Field, 0, ""}, + {"Write", Func, 0, "func(fd int, p []byte) (n int, err error)"}, + {"WriteConsole", Func, 1, ""}, + {"WriteFile", Func, 0, ""}, + {"X509_ASN_ENCODING", Const, 0, ""}, + {"XCASE", Const, 0, ""}, + {"XP1_CONNECTIONLESS", Const, 2, ""}, + {"XP1_CONNECT_DATA", Const, 2, ""}, + {"XP1_DISCONNECT_DATA", Const, 2, ""}, + {"XP1_EXPEDITED_DATA", Const, 2, ""}, + {"XP1_GRACEFUL_CLOSE", Const, 2, ""}, + {"XP1_GUARANTEED_DELIVERY", Const, 2, ""}, + {"XP1_GUARANTEED_ORDER", Const, 2, ""}, + {"XP1_IFS_HANDLES", Const, 2, ""}, + {"XP1_MESSAGE_ORIENTED", Const, 2, ""}, + {"XP1_MULTIPOINT_CONTROL_PLANE", Const, 2, ""}, + {"XP1_MULTIPOINT_DATA_PLANE", Const, 2, ""}, + {"XP1_PARTIAL_MESSAGE", Const, 2, ""}, + {"XP1_PSEUDO_STREAM", Const, 2, ""}, + {"XP1_QOS_SUPPORTED", Const, 2, ""}, + {"XP1_SAN_SUPPORT_SDP", Const, 2, ""}, + {"XP1_SUPPORT_BROADCAST", Const, 2, ""}, + {"XP1_SUPPORT_MULTIPOINT", Const, 2, ""}, + {"XP1_UNI_RECV", Const, 2, ""}, + {"XP1_UNI_SEND", Const, 2, ""}, }, "syscall/js": { - {"CopyBytesToGo", Func, 0}, - {"CopyBytesToJS", Func, 0}, - {"Error", Type, 0}, - {"Func", Type, 0}, - {"FuncOf", Func, 0}, - {"Global", Func, 0}, - {"Null", Func, 0}, - {"Type", Type, 0}, - {"TypeBoolean", Const, 0}, - {"TypeFunction", Const, 0}, - {"TypeNull", Const, 0}, - {"TypeNumber", Const, 0}, - {"TypeObject", Const, 0}, - {"TypeString", Const, 0}, - {"TypeSymbol", Const, 0}, - {"TypeUndefined", Const, 0}, - {"Undefined", Func, 0}, - {"Value", Type, 0}, - {"ValueError", Type, 0}, - {"ValueOf", Func, 0}, + {"CopyBytesToGo", Func, 0, ""}, + {"CopyBytesToJS", Func, 0, ""}, + {"Error", Type, 0, ""}, + {"Func", Type, 0, ""}, + {"FuncOf", Func, 0, ""}, + {"Global", Func, 0, ""}, + {"Null", Func, 0, ""}, + {"Type", Type, 0, ""}, + {"TypeBoolean", Const, 0, ""}, + {"TypeFunction", Const, 0, ""}, + {"TypeNull", Const, 0, ""}, + {"TypeNumber", Const, 0, ""}, + {"TypeObject", Const, 0, ""}, + {"TypeString", Const, 0, ""}, + {"TypeSymbol", Const, 0, ""}, + {"TypeUndefined", Const, 0, ""}, + {"Undefined", Func, 0, ""}, + {"Value", Type, 0, ""}, + {"ValueError", Type, 0, ""}, + {"ValueOf", Func, 0, ""}, }, "testing": { - {"(*B).Chdir", Method, 24}, - {"(*B).Cleanup", Method, 14}, - {"(*B).Context", Method, 24}, - {"(*B).Elapsed", Method, 20}, - {"(*B).Error", Method, 0}, - {"(*B).Errorf", Method, 0}, - {"(*B).Fail", Method, 0}, - {"(*B).FailNow", Method, 0}, - {"(*B).Failed", Method, 0}, - {"(*B).Fatal", Method, 0}, - {"(*B).Fatalf", Method, 0}, - {"(*B).Helper", Method, 9}, - {"(*B).Log", Method, 0}, - {"(*B).Logf", Method, 0}, - {"(*B).Loop", Method, 24}, - {"(*B).Name", Method, 8}, - {"(*B).ReportAllocs", Method, 1}, - {"(*B).ReportMetric", Method, 13}, - {"(*B).ResetTimer", Method, 0}, - {"(*B).Run", Method, 7}, - {"(*B).RunParallel", Method, 3}, - {"(*B).SetBytes", Method, 0}, - {"(*B).SetParallelism", Method, 3}, - {"(*B).Setenv", Method, 17}, - {"(*B).Skip", Method, 1}, - {"(*B).SkipNow", Method, 1}, - {"(*B).Skipf", Method, 1}, - {"(*B).Skipped", Method, 1}, - {"(*B).StartTimer", Method, 0}, - {"(*B).StopTimer", Method, 0}, - {"(*B).TempDir", Method, 15}, - {"(*F).Add", Method, 18}, - {"(*F).Chdir", Method, 24}, - {"(*F).Cleanup", Method, 18}, - {"(*F).Context", Method, 24}, - {"(*F).Error", Method, 18}, - {"(*F).Errorf", Method, 18}, - {"(*F).Fail", Method, 18}, - {"(*F).FailNow", Method, 18}, - {"(*F).Failed", Method, 18}, - {"(*F).Fatal", Method, 18}, - {"(*F).Fatalf", Method, 18}, - {"(*F).Fuzz", Method, 18}, - {"(*F).Helper", Method, 18}, - {"(*F).Log", Method, 18}, - {"(*F).Logf", Method, 18}, - {"(*F).Name", Method, 18}, - {"(*F).Setenv", Method, 18}, - {"(*F).Skip", Method, 18}, - {"(*F).SkipNow", Method, 18}, - {"(*F).Skipf", Method, 18}, - {"(*F).Skipped", Method, 18}, - {"(*F).TempDir", Method, 18}, - {"(*M).Run", Method, 4}, - {"(*PB).Next", Method, 3}, - {"(*T).Chdir", Method, 24}, - {"(*T).Cleanup", Method, 14}, - {"(*T).Context", Method, 24}, - {"(*T).Deadline", Method, 15}, - {"(*T).Error", Method, 0}, - {"(*T).Errorf", Method, 0}, - {"(*T).Fail", Method, 0}, - {"(*T).FailNow", Method, 0}, - {"(*T).Failed", Method, 0}, - {"(*T).Fatal", Method, 0}, - {"(*T).Fatalf", Method, 0}, - {"(*T).Helper", Method, 9}, - {"(*T).Log", Method, 0}, - {"(*T).Logf", Method, 0}, - {"(*T).Name", Method, 8}, - {"(*T).Parallel", Method, 0}, - {"(*T).Run", Method, 7}, - {"(*T).Setenv", Method, 17}, - {"(*T).Skip", Method, 1}, - {"(*T).SkipNow", Method, 1}, - {"(*T).Skipf", Method, 1}, - {"(*T).Skipped", Method, 1}, - {"(*T).TempDir", Method, 15}, - {"(BenchmarkResult).AllocedBytesPerOp", Method, 1}, - {"(BenchmarkResult).AllocsPerOp", Method, 1}, - {"(BenchmarkResult).MemString", Method, 1}, - {"(BenchmarkResult).NsPerOp", Method, 0}, - {"(BenchmarkResult).String", Method, 0}, - {"AllocsPerRun", Func, 1}, - {"B", Type, 0}, - {"B.N", Field, 0}, - {"Benchmark", Func, 0}, - {"BenchmarkResult", Type, 0}, - {"BenchmarkResult.Bytes", Field, 0}, - {"BenchmarkResult.Extra", Field, 13}, - {"BenchmarkResult.MemAllocs", Field, 1}, - {"BenchmarkResult.MemBytes", Field, 1}, - {"BenchmarkResult.N", Field, 0}, - {"BenchmarkResult.T", Field, 0}, - {"Cover", Type, 2}, - {"Cover.Blocks", Field, 2}, - {"Cover.Counters", Field, 2}, - {"Cover.CoveredPackages", Field, 2}, - {"Cover.Mode", Field, 2}, - {"CoverBlock", Type, 2}, - {"CoverBlock.Col0", Field, 2}, - {"CoverBlock.Col1", Field, 2}, - {"CoverBlock.Line0", Field, 2}, - {"CoverBlock.Line1", Field, 2}, - {"CoverBlock.Stmts", Field, 2}, - {"CoverMode", Func, 8}, - {"Coverage", Func, 4}, - {"F", Type, 18}, - {"Init", Func, 13}, - {"InternalBenchmark", Type, 0}, - {"InternalBenchmark.F", Field, 0}, - {"InternalBenchmark.Name", Field, 0}, - {"InternalExample", Type, 0}, - {"InternalExample.F", Field, 0}, - {"InternalExample.Name", Field, 0}, - {"InternalExample.Output", Field, 0}, - {"InternalExample.Unordered", Field, 7}, - {"InternalFuzzTarget", Type, 18}, - {"InternalFuzzTarget.Fn", Field, 18}, - {"InternalFuzzTarget.Name", Field, 18}, - {"InternalTest", Type, 0}, - {"InternalTest.F", Field, 0}, - {"InternalTest.Name", Field, 0}, - {"M", Type, 4}, - {"Main", Func, 0}, - {"MainStart", Func, 4}, - {"PB", Type, 3}, - {"RegisterCover", Func, 2}, - {"RunBenchmarks", Func, 0}, - {"RunExamples", Func, 0}, - {"RunTests", Func, 0}, - {"Short", Func, 0}, - {"T", Type, 0}, - {"TB", Type, 2}, - {"Testing", Func, 21}, - {"Verbose", Func, 1}, + {"(*B).Chdir", Method, 24, ""}, + {"(*B).Cleanup", Method, 14, ""}, + {"(*B).Context", Method, 24, ""}, + {"(*B).Elapsed", Method, 20, ""}, + {"(*B).Error", Method, 0, ""}, + {"(*B).Errorf", Method, 0, ""}, + {"(*B).Fail", Method, 0, ""}, + {"(*B).FailNow", Method, 0, ""}, + {"(*B).Failed", Method, 0, ""}, + {"(*B).Fatal", Method, 0, ""}, + {"(*B).Fatalf", Method, 0, ""}, + {"(*B).Helper", Method, 9, ""}, + {"(*B).Log", Method, 0, ""}, + {"(*B).Logf", Method, 0, ""}, + {"(*B).Loop", Method, 24, ""}, + {"(*B).Name", Method, 8, ""}, + {"(*B).ReportAllocs", Method, 1, ""}, + {"(*B).ReportMetric", Method, 13, ""}, + {"(*B).ResetTimer", Method, 0, ""}, + {"(*B).Run", Method, 7, ""}, + {"(*B).RunParallel", Method, 3, ""}, + {"(*B).SetBytes", Method, 0, ""}, + {"(*B).SetParallelism", Method, 3, ""}, + {"(*B).Setenv", Method, 17, ""}, + {"(*B).Skip", Method, 1, ""}, + {"(*B).SkipNow", Method, 1, ""}, + {"(*B).Skipf", Method, 1, ""}, + {"(*B).Skipped", Method, 1, ""}, + {"(*B).StartTimer", Method, 0, ""}, + {"(*B).StopTimer", Method, 0, ""}, + {"(*B).TempDir", Method, 15, ""}, + {"(*F).Add", Method, 18, ""}, + {"(*F).Chdir", Method, 24, ""}, + {"(*F).Cleanup", Method, 18, ""}, + {"(*F).Context", Method, 24, ""}, + {"(*F).Error", Method, 18, ""}, + {"(*F).Errorf", Method, 18, ""}, + {"(*F).Fail", Method, 18, ""}, + {"(*F).FailNow", Method, 18, ""}, + {"(*F).Failed", Method, 18, ""}, + {"(*F).Fatal", Method, 18, ""}, + {"(*F).Fatalf", Method, 18, ""}, + {"(*F).Fuzz", Method, 18, ""}, + {"(*F).Helper", Method, 18, ""}, + {"(*F).Log", Method, 18, ""}, + {"(*F).Logf", Method, 18, ""}, + {"(*F).Name", Method, 18, ""}, + {"(*F).Setenv", Method, 18, ""}, + {"(*F).Skip", Method, 18, ""}, + {"(*F).SkipNow", Method, 18, ""}, + {"(*F).Skipf", Method, 18, ""}, + {"(*F).Skipped", Method, 18, ""}, + {"(*F).TempDir", Method, 18, ""}, + {"(*M).Run", Method, 4, ""}, + {"(*PB).Next", Method, 3, ""}, + {"(*T).Chdir", Method, 24, ""}, + {"(*T).Cleanup", Method, 14, ""}, + {"(*T).Context", Method, 24, ""}, + {"(*T).Deadline", Method, 15, ""}, + {"(*T).Error", Method, 0, ""}, + {"(*T).Errorf", Method, 0, ""}, + {"(*T).Fail", Method, 0, ""}, + {"(*T).FailNow", Method, 0, ""}, + {"(*T).Failed", Method, 0, ""}, + {"(*T).Fatal", Method, 0, ""}, + {"(*T).Fatalf", Method, 0, ""}, + {"(*T).Helper", Method, 9, ""}, + {"(*T).Log", Method, 0, ""}, + {"(*T).Logf", Method, 0, ""}, + {"(*T).Name", Method, 8, ""}, + {"(*T).Parallel", Method, 0, ""}, + {"(*T).Run", Method, 7, ""}, + {"(*T).Setenv", Method, 17, ""}, + {"(*T).Skip", Method, 1, ""}, + {"(*T).SkipNow", Method, 1, ""}, + {"(*T).Skipf", Method, 1, ""}, + {"(*T).Skipped", Method, 1, ""}, + {"(*T).TempDir", Method, 15, ""}, + {"(BenchmarkResult).AllocedBytesPerOp", Method, 1, ""}, + {"(BenchmarkResult).AllocsPerOp", Method, 1, ""}, + {"(BenchmarkResult).MemString", Method, 1, ""}, + {"(BenchmarkResult).NsPerOp", Method, 0, ""}, + {"(BenchmarkResult).String", Method, 0, ""}, + {"AllocsPerRun", Func, 1, "func(runs int, f func()) (avg float64)"}, + {"B", Type, 0, ""}, + {"B.N", Field, 0, ""}, + {"Benchmark", Func, 0, "func(f func(b *B)) BenchmarkResult"}, + {"BenchmarkResult", Type, 0, ""}, + {"BenchmarkResult.Bytes", Field, 0, ""}, + {"BenchmarkResult.Extra", Field, 13, ""}, + {"BenchmarkResult.MemAllocs", Field, 1, ""}, + {"BenchmarkResult.MemBytes", Field, 1, ""}, + {"BenchmarkResult.N", Field, 0, ""}, + {"BenchmarkResult.T", Field, 0, ""}, + {"Cover", Type, 2, ""}, + {"Cover.Blocks", Field, 2, ""}, + {"Cover.Counters", Field, 2, ""}, + {"Cover.CoveredPackages", Field, 2, ""}, + {"Cover.Mode", Field, 2, ""}, + {"CoverBlock", Type, 2, ""}, + {"CoverBlock.Col0", Field, 2, ""}, + {"CoverBlock.Col1", Field, 2, ""}, + {"CoverBlock.Line0", Field, 2, ""}, + {"CoverBlock.Line1", Field, 2, ""}, + {"CoverBlock.Stmts", Field, 2, ""}, + {"CoverMode", Func, 8, "func() string"}, + {"Coverage", Func, 4, "func() float64"}, + {"F", Type, 18, ""}, + {"Init", Func, 13, "func()"}, + {"InternalBenchmark", Type, 0, ""}, + {"InternalBenchmark.F", Field, 0, ""}, + {"InternalBenchmark.Name", Field, 0, ""}, + {"InternalExample", Type, 0, ""}, + {"InternalExample.F", Field, 0, ""}, + {"InternalExample.Name", Field, 0, ""}, + {"InternalExample.Output", Field, 0, ""}, + {"InternalExample.Unordered", Field, 7, ""}, + {"InternalFuzzTarget", Type, 18, ""}, + {"InternalFuzzTarget.Fn", Field, 18, ""}, + {"InternalFuzzTarget.Name", Field, 18, ""}, + {"InternalTest", Type, 0, ""}, + {"InternalTest.F", Field, 0, ""}, + {"InternalTest.Name", Field, 0, ""}, + {"M", Type, 4, ""}, + {"Main", Func, 0, "func(matchString func(pat string, str string) (bool, error), tests []InternalTest, benchmarks []InternalBenchmark, examples []InternalExample)"}, + {"MainStart", Func, 4, "func(deps testDeps, tests []InternalTest, benchmarks []InternalBenchmark, fuzzTargets []InternalFuzzTarget, examples []InternalExample) *M"}, + {"PB", Type, 3, ""}, + {"RegisterCover", Func, 2, "func(c Cover)"}, + {"RunBenchmarks", Func, 0, "func(matchString func(pat string, str string) (bool, error), benchmarks []InternalBenchmark)"}, + {"RunExamples", Func, 0, "func(matchString func(pat string, str string) (bool, error), examples []InternalExample) (ok bool)"}, + {"RunTests", Func, 0, "func(matchString func(pat string, str string) (bool, error), tests []InternalTest) (ok bool)"}, + {"Short", Func, 0, "func() bool"}, + {"T", Type, 0, ""}, + {"TB", Type, 2, ""}, + {"Testing", Func, 21, "func() bool"}, + {"Verbose", Func, 1, "func() bool"}, }, "testing/fstest": { - {"(MapFS).Glob", Method, 16}, - {"(MapFS).Lstat", Method, 25}, - {"(MapFS).Open", Method, 16}, - {"(MapFS).ReadDir", Method, 16}, - {"(MapFS).ReadFile", Method, 16}, - {"(MapFS).ReadLink", Method, 25}, - {"(MapFS).Stat", Method, 16}, - {"(MapFS).Sub", Method, 16}, - {"MapFS", Type, 16}, - {"MapFile", Type, 16}, - {"MapFile.Data", Field, 16}, - {"MapFile.ModTime", Field, 16}, - {"MapFile.Mode", Field, 16}, - {"MapFile.Sys", Field, 16}, - {"TestFS", Func, 16}, + {"(MapFS).Glob", Method, 16, ""}, + {"(MapFS).Lstat", Method, 25, ""}, + {"(MapFS).Open", Method, 16, ""}, + {"(MapFS).ReadDir", Method, 16, ""}, + {"(MapFS).ReadFile", Method, 16, ""}, + {"(MapFS).ReadLink", Method, 25, ""}, + {"(MapFS).Stat", Method, 16, ""}, + {"(MapFS).Sub", Method, 16, ""}, + {"MapFS", Type, 16, ""}, + {"MapFile", Type, 16, ""}, + {"MapFile.Data", Field, 16, ""}, + {"MapFile.ModTime", Field, 16, ""}, + {"MapFile.Mode", Field, 16, ""}, + {"MapFile.Sys", Field, 16, ""}, + {"TestFS", Func, 16, "func(fsys fs.FS, expected ...string) error"}, }, "testing/iotest": { - {"DataErrReader", Func, 0}, - {"ErrReader", Func, 16}, - {"ErrTimeout", Var, 0}, - {"HalfReader", Func, 0}, - {"NewReadLogger", Func, 0}, - {"NewWriteLogger", Func, 0}, - {"OneByteReader", Func, 0}, - {"TestReader", Func, 16}, - {"TimeoutReader", Func, 0}, - {"TruncateWriter", Func, 0}, + {"DataErrReader", Func, 0, "func(r io.Reader) io.Reader"}, + {"ErrReader", Func, 16, "func(err error) io.Reader"}, + {"ErrTimeout", Var, 0, ""}, + {"HalfReader", Func, 0, "func(r io.Reader) io.Reader"}, + {"NewReadLogger", Func, 0, "func(prefix string, r io.Reader) io.Reader"}, + {"NewWriteLogger", Func, 0, "func(prefix string, w io.Writer) io.Writer"}, + {"OneByteReader", Func, 0, "func(r io.Reader) io.Reader"}, + {"TestReader", Func, 16, "func(r io.Reader, content []byte) error"}, + {"TimeoutReader", Func, 0, "func(r io.Reader) io.Reader"}, + {"TruncateWriter", Func, 0, "func(w io.Writer, n int64) io.Writer"}, }, "testing/quick": { - {"(*CheckEqualError).Error", Method, 0}, - {"(*CheckError).Error", Method, 0}, - {"(SetupError).Error", Method, 0}, - {"Check", Func, 0}, - {"CheckEqual", Func, 0}, - {"CheckEqualError", Type, 0}, - {"CheckEqualError.CheckError", Field, 0}, - {"CheckEqualError.Out1", Field, 0}, - {"CheckEqualError.Out2", Field, 0}, - {"CheckError", Type, 0}, - {"CheckError.Count", Field, 0}, - {"CheckError.In", Field, 0}, - {"Config", Type, 0}, - {"Config.MaxCount", Field, 0}, - {"Config.MaxCountScale", Field, 0}, - {"Config.Rand", Field, 0}, - {"Config.Values", Field, 0}, - {"Generator", Type, 0}, - {"SetupError", Type, 0}, - {"Value", Func, 0}, + {"(*CheckEqualError).Error", Method, 0, ""}, + {"(*CheckError).Error", Method, 0, ""}, + {"(SetupError).Error", Method, 0, ""}, + {"Check", Func, 0, "func(f any, config *Config) error"}, + {"CheckEqual", Func, 0, "func(f any, g any, config *Config) error"}, + {"CheckEqualError", Type, 0, ""}, + {"CheckEqualError.CheckError", Field, 0, ""}, + {"CheckEqualError.Out1", Field, 0, ""}, + {"CheckEqualError.Out2", Field, 0, ""}, + {"CheckError", Type, 0, ""}, + {"CheckError.Count", Field, 0, ""}, + {"CheckError.In", Field, 0, ""}, + {"Config", Type, 0, ""}, + {"Config.MaxCount", Field, 0, ""}, + {"Config.MaxCountScale", Field, 0, ""}, + {"Config.Rand", Field, 0, ""}, + {"Config.Values", Field, 0, ""}, + {"Generator", Type, 0, ""}, + {"SetupError", Type, 0, ""}, + {"Value", Func, 0, "func(t reflect.Type, rand *rand.Rand) (value reflect.Value, ok bool)"}, }, "testing/slogtest": { - {"Run", Func, 22}, - {"TestHandler", Func, 21}, + {"Run", Func, 22, "func(t *testing.T, newHandler func(*testing.T) slog.Handler, result func(*testing.T) map[string]any)"}, + {"TestHandler", Func, 21, "func(h slog.Handler, results func() []map[string]any) error"}, }, "text/scanner": { - {"(*Position).IsValid", Method, 0}, - {"(*Scanner).Init", Method, 0}, - {"(*Scanner).IsValid", Method, 0}, - {"(*Scanner).Next", Method, 0}, - {"(*Scanner).Peek", Method, 0}, - {"(*Scanner).Pos", Method, 0}, - {"(*Scanner).Scan", Method, 0}, - {"(*Scanner).TokenText", Method, 0}, - {"(Position).String", Method, 0}, - {"(Scanner).String", Method, 0}, - {"Char", Const, 0}, - {"Comment", Const, 0}, - {"EOF", Const, 0}, - {"Float", Const, 0}, - {"GoTokens", Const, 0}, - {"GoWhitespace", Const, 0}, - {"Ident", Const, 0}, - {"Int", Const, 0}, - {"Position", Type, 0}, - {"Position.Column", Field, 0}, - {"Position.Filename", Field, 0}, - {"Position.Line", Field, 0}, - {"Position.Offset", Field, 0}, - {"RawString", Const, 0}, - {"ScanChars", Const, 0}, - {"ScanComments", Const, 0}, - {"ScanFloats", Const, 0}, - {"ScanIdents", Const, 0}, - {"ScanInts", Const, 0}, - {"ScanRawStrings", Const, 0}, - {"ScanStrings", Const, 0}, - {"Scanner", Type, 0}, - {"Scanner.Error", Field, 0}, - {"Scanner.ErrorCount", Field, 0}, - {"Scanner.IsIdentRune", Field, 4}, - {"Scanner.Mode", Field, 0}, - {"Scanner.Position", Field, 0}, - {"Scanner.Whitespace", Field, 0}, - {"SkipComments", Const, 0}, - {"String", Const, 0}, - {"TokenString", Func, 0}, + {"(*Position).IsValid", Method, 0, ""}, + {"(*Scanner).Init", Method, 0, ""}, + {"(*Scanner).IsValid", Method, 0, ""}, + {"(*Scanner).Next", Method, 0, ""}, + {"(*Scanner).Peek", Method, 0, ""}, + {"(*Scanner).Pos", Method, 0, ""}, + {"(*Scanner).Scan", Method, 0, ""}, + {"(*Scanner).TokenText", Method, 0, ""}, + {"(Position).String", Method, 0, ""}, + {"(Scanner).String", Method, 0, ""}, + {"Char", Const, 0, ""}, + {"Comment", Const, 0, ""}, + {"EOF", Const, 0, ""}, + {"Float", Const, 0, ""}, + {"GoTokens", Const, 0, ""}, + {"GoWhitespace", Const, 0, ""}, + {"Ident", Const, 0, ""}, + {"Int", Const, 0, ""}, + {"Position", Type, 0, ""}, + {"Position.Column", Field, 0, ""}, + {"Position.Filename", Field, 0, ""}, + {"Position.Line", Field, 0, ""}, + {"Position.Offset", Field, 0, ""}, + {"RawString", Const, 0, ""}, + {"ScanChars", Const, 0, ""}, + {"ScanComments", Const, 0, ""}, + {"ScanFloats", Const, 0, ""}, + {"ScanIdents", Const, 0, ""}, + {"ScanInts", Const, 0, ""}, + {"ScanRawStrings", Const, 0, ""}, + {"ScanStrings", Const, 0, ""}, + {"Scanner", Type, 0, ""}, + {"Scanner.Error", Field, 0, ""}, + {"Scanner.ErrorCount", Field, 0, ""}, + {"Scanner.IsIdentRune", Field, 4, ""}, + {"Scanner.Mode", Field, 0, ""}, + {"Scanner.Position", Field, 0, ""}, + {"Scanner.Whitespace", Field, 0, ""}, + {"SkipComments", Const, 0, ""}, + {"String", Const, 0, ""}, + {"TokenString", Func, 0, "func(tok rune) string"}, }, "text/tabwriter": { - {"(*Writer).Flush", Method, 0}, - {"(*Writer).Init", Method, 0}, - {"(*Writer).Write", Method, 0}, - {"AlignRight", Const, 0}, - {"Debug", Const, 0}, - {"DiscardEmptyColumns", Const, 0}, - {"Escape", Const, 0}, - {"FilterHTML", Const, 0}, - {"NewWriter", Func, 0}, - {"StripEscape", Const, 0}, - {"TabIndent", Const, 0}, - {"Writer", Type, 0}, + {"(*Writer).Flush", Method, 0, ""}, + {"(*Writer).Init", Method, 0, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"AlignRight", Const, 0, ""}, + {"Debug", Const, 0, ""}, + {"DiscardEmptyColumns", Const, 0, ""}, + {"Escape", Const, 0, ""}, + {"FilterHTML", Const, 0, ""}, + {"NewWriter", Func, 0, "func(output io.Writer, minwidth int, tabwidth int, padding int, padchar byte, flags uint) *Writer"}, + {"StripEscape", Const, 0, ""}, + {"TabIndent", Const, 0, ""}, + {"Writer", Type, 0, ""}, }, "text/template": { - {"(*Template).AddParseTree", Method, 0}, - {"(*Template).Clone", Method, 0}, - {"(*Template).DefinedTemplates", Method, 5}, - {"(*Template).Delims", Method, 0}, - {"(*Template).Execute", Method, 0}, - {"(*Template).ExecuteTemplate", Method, 0}, - {"(*Template).Funcs", Method, 0}, - {"(*Template).Lookup", Method, 0}, - {"(*Template).Name", Method, 0}, - {"(*Template).New", Method, 0}, - {"(*Template).Option", Method, 5}, - {"(*Template).Parse", Method, 0}, - {"(*Template).ParseFS", Method, 16}, - {"(*Template).ParseFiles", Method, 0}, - {"(*Template).ParseGlob", Method, 0}, - {"(*Template).Templates", Method, 0}, - {"(ExecError).Error", Method, 6}, - {"(ExecError).Unwrap", Method, 13}, - {"(Template).Copy", Method, 2}, - {"(Template).ErrorContext", Method, 1}, - {"ExecError", Type, 6}, - {"ExecError.Err", Field, 6}, - {"ExecError.Name", Field, 6}, - {"FuncMap", Type, 0}, - {"HTMLEscape", Func, 0}, - {"HTMLEscapeString", Func, 0}, - {"HTMLEscaper", Func, 0}, - {"IsTrue", Func, 6}, - {"JSEscape", Func, 0}, - {"JSEscapeString", Func, 0}, - {"JSEscaper", Func, 0}, - {"Must", Func, 0}, - {"New", Func, 0}, - {"ParseFS", Func, 16}, - {"ParseFiles", Func, 0}, - {"ParseGlob", Func, 0}, - {"Template", Type, 0}, - {"Template.Tree", Field, 0}, - {"URLQueryEscaper", Func, 0}, + {"(*Template).AddParseTree", Method, 0, ""}, + {"(*Template).Clone", Method, 0, ""}, + {"(*Template).DefinedTemplates", Method, 5, ""}, + {"(*Template).Delims", Method, 0, ""}, + {"(*Template).Execute", Method, 0, ""}, + {"(*Template).ExecuteTemplate", Method, 0, ""}, + {"(*Template).Funcs", Method, 0, ""}, + {"(*Template).Lookup", Method, 0, ""}, + {"(*Template).Name", Method, 0, ""}, + {"(*Template).New", Method, 0, ""}, + {"(*Template).Option", Method, 5, ""}, + {"(*Template).Parse", Method, 0, ""}, + {"(*Template).ParseFS", Method, 16, ""}, + {"(*Template).ParseFiles", Method, 0, ""}, + {"(*Template).ParseGlob", Method, 0, ""}, + {"(*Template).Templates", Method, 0, ""}, + {"(ExecError).Error", Method, 6, ""}, + {"(ExecError).Unwrap", Method, 13, ""}, + {"(Template).Copy", Method, 2, ""}, + {"(Template).ErrorContext", Method, 1, ""}, + {"ExecError", Type, 6, ""}, + {"ExecError.Err", Field, 6, ""}, + {"ExecError.Name", Field, 6, ""}, + {"FuncMap", Type, 0, ""}, + {"HTMLEscape", Func, 0, "func(w io.Writer, b []byte)"}, + {"HTMLEscapeString", Func, 0, "func(s string) string"}, + {"HTMLEscaper", Func, 0, "func(args ...any) string"}, + {"IsTrue", Func, 6, "func(val any) (truth bool, ok bool)"}, + {"JSEscape", Func, 0, "func(w io.Writer, b []byte)"}, + {"JSEscapeString", Func, 0, "func(s string) string"}, + {"JSEscaper", Func, 0, "func(args ...any) string"}, + {"Must", Func, 0, "func(t *Template, err error) *Template"}, + {"New", Func, 0, "func(name string) *Template"}, + {"ParseFS", Func, 16, "func(fsys fs.FS, patterns ...string) (*Template, error)"}, + {"ParseFiles", Func, 0, "func(filenames ...string) (*Template, error)"}, + {"ParseGlob", Func, 0, "func(pattern string) (*Template, error)"}, + {"Template", Type, 0, ""}, + {"Template.Tree", Field, 0, ""}, + {"URLQueryEscaper", Func, 0, "func(args ...any) string"}, }, "text/template/parse": { - {"(*ActionNode).Copy", Method, 0}, - {"(*ActionNode).String", Method, 0}, - {"(*BoolNode).Copy", Method, 0}, - {"(*BoolNode).String", Method, 0}, - {"(*BranchNode).Copy", Method, 4}, - {"(*BranchNode).String", Method, 0}, - {"(*BreakNode).Copy", Method, 18}, - {"(*BreakNode).String", Method, 18}, - {"(*ChainNode).Add", Method, 1}, - {"(*ChainNode).Copy", Method, 1}, - {"(*ChainNode).String", Method, 1}, - {"(*CommandNode).Copy", Method, 0}, - {"(*CommandNode).String", Method, 0}, - {"(*CommentNode).Copy", Method, 16}, - {"(*CommentNode).String", Method, 16}, - {"(*ContinueNode).Copy", Method, 18}, - {"(*ContinueNode).String", Method, 18}, - {"(*DotNode).Copy", Method, 0}, - {"(*DotNode).String", Method, 0}, - {"(*DotNode).Type", Method, 0}, - {"(*FieldNode).Copy", Method, 0}, - {"(*FieldNode).String", Method, 0}, - {"(*IdentifierNode).Copy", Method, 0}, - {"(*IdentifierNode).SetPos", Method, 1}, - {"(*IdentifierNode).SetTree", Method, 4}, - {"(*IdentifierNode).String", Method, 0}, - {"(*IfNode).Copy", Method, 0}, - {"(*IfNode).String", Method, 0}, - {"(*ListNode).Copy", Method, 0}, - {"(*ListNode).CopyList", Method, 0}, - {"(*ListNode).String", Method, 0}, - {"(*NilNode).Copy", Method, 1}, - {"(*NilNode).String", Method, 1}, - {"(*NilNode).Type", Method, 1}, - {"(*NumberNode).Copy", Method, 0}, - {"(*NumberNode).String", Method, 0}, - {"(*PipeNode).Copy", Method, 0}, - {"(*PipeNode).CopyPipe", Method, 0}, - {"(*PipeNode).String", Method, 0}, - {"(*RangeNode).Copy", Method, 0}, - {"(*RangeNode).String", Method, 0}, - {"(*StringNode).Copy", Method, 0}, - {"(*StringNode).String", Method, 0}, - {"(*TemplateNode).Copy", Method, 0}, - {"(*TemplateNode).String", Method, 0}, - {"(*TextNode).Copy", Method, 0}, - {"(*TextNode).String", Method, 0}, - {"(*Tree).Copy", Method, 2}, - {"(*Tree).ErrorContext", Method, 1}, - {"(*Tree).Parse", Method, 0}, - {"(*VariableNode).Copy", Method, 0}, - {"(*VariableNode).String", Method, 0}, - {"(*WithNode).Copy", Method, 0}, - {"(*WithNode).String", Method, 0}, - {"(ActionNode).Position", Method, 1}, - {"(ActionNode).Type", Method, 0}, - {"(BoolNode).Position", Method, 1}, - {"(BoolNode).Type", Method, 0}, - {"(BranchNode).Position", Method, 1}, - {"(BranchNode).Type", Method, 0}, - {"(BreakNode).Position", Method, 18}, - {"(BreakNode).Type", Method, 18}, - {"(ChainNode).Position", Method, 1}, - {"(ChainNode).Type", Method, 1}, - {"(CommandNode).Position", Method, 1}, - {"(CommandNode).Type", Method, 0}, - {"(CommentNode).Position", Method, 16}, - {"(CommentNode).Type", Method, 16}, - {"(ContinueNode).Position", Method, 18}, - {"(ContinueNode).Type", Method, 18}, - {"(DotNode).Position", Method, 1}, - {"(FieldNode).Position", Method, 1}, - {"(FieldNode).Type", Method, 0}, - {"(IdentifierNode).Position", Method, 1}, - {"(IdentifierNode).Type", Method, 0}, - {"(IfNode).Position", Method, 1}, - {"(IfNode).Type", Method, 0}, - {"(ListNode).Position", Method, 1}, - {"(ListNode).Type", Method, 0}, - {"(NilNode).Position", Method, 1}, - {"(NodeType).Type", Method, 0}, - {"(NumberNode).Position", Method, 1}, - {"(NumberNode).Type", Method, 0}, - {"(PipeNode).Position", Method, 1}, - {"(PipeNode).Type", Method, 0}, - {"(Pos).Position", Method, 1}, - {"(RangeNode).Position", Method, 1}, - {"(RangeNode).Type", Method, 0}, - {"(StringNode).Position", Method, 1}, - {"(StringNode).Type", Method, 0}, - {"(TemplateNode).Position", Method, 1}, - {"(TemplateNode).Type", Method, 0}, - {"(TextNode).Position", Method, 1}, - {"(TextNode).Type", Method, 0}, - {"(VariableNode).Position", Method, 1}, - {"(VariableNode).Type", Method, 0}, - {"(WithNode).Position", Method, 1}, - {"(WithNode).Type", Method, 0}, - {"ActionNode", Type, 0}, - {"ActionNode.Line", Field, 0}, - {"ActionNode.NodeType", Field, 0}, - {"ActionNode.Pipe", Field, 0}, - {"ActionNode.Pos", Field, 1}, - {"BoolNode", Type, 0}, - {"BoolNode.NodeType", Field, 0}, - {"BoolNode.Pos", Field, 1}, - {"BoolNode.True", Field, 0}, - {"BranchNode", Type, 0}, - {"BranchNode.ElseList", Field, 0}, - {"BranchNode.Line", Field, 0}, - {"BranchNode.List", Field, 0}, - {"BranchNode.NodeType", Field, 0}, - {"BranchNode.Pipe", Field, 0}, - {"BranchNode.Pos", Field, 1}, - {"BreakNode", Type, 18}, - {"BreakNode.Line", Field, 18}, - {"BreakNode.NodeType", Field, 18}, - {"BreakNode.Pos", Field, 18}, - {"ChainNode", Type, 1}, - {"ChainNode.Field", Field, 1}, - {"ChainNode.Node", Field, 1}, - {"ChainNode.NodeType", Field, 1}, - {"ChainNode.Pos", Field, 1}, - {"CommandNode", Type, 0}, - {"CommandNode.Args", Field, 0}, - {"CommandNode.NodeType", Field, 0}, - {"CommandNode.Pos", Field, 1}, - {"CommentNode", Type, 16}, - {"CommentNode.NodeType", Field, 16}, - {"CommentNode.Pos", Field, 16}, - {"CommentNode.Text", Field, 16}, - {"ContinueNode", Type, 18}, - {"ContinueNode.Line", Field, 18}, - {"ContinueNode.NodeType", Field, 18}, - {"ContinueNode.Pos", Field, 18}, - {"DotNode", Type, 0}, - {"DotNode.NodeType", Field, 4}, - {"DotNode.Pos", Field, 1}, - {"FieldNode", Type, 0}, - {"FieldNode.Ident", Field, 0}, - {"FieldNode.NodeType", Field, 0}, - {"FieldNode.Pos", Field, 1}, - {"IdentifierNode", Type, 0}, - {"IdentifierNode.Ident", Field, 0}, - {"IdentifierNode.NodeType", Field, 0}, - {"IdentifierNode.Pos", Field, 1}, - {"IfNode", Type, 0}, - {"IfNode.BranchNode", Field, 0}, - {"IsEmptyTree", Func, 0}, - {"ListNode", Type, 0}, - {"ListNode.NodeType", Field, 0}, - {"ListNode.Nodes", Field, 0}, - {"ListNode.Pos", Field, 1}, - {"Mode", Type, 16}, - {"New", Func, 0}, - {"NewIdentifier", Func, 0}, - {"NilNode", Type, 1}, - {"NilNode.NodeType", Field, 4}, - {"NilNode.Pos", Field, 1}, - {"Node", Type, 0}, - {"NodeAction", Const, 0}, - {"NodeBool", Const, 0}, - {"NodeBreak", Const, 18}, - {"NodeChain", Const, 1}, - {"NodeCommand", Const, 0}, - {"NodeComment", Const, 16}, - {"NodeContinue", Const, 18}, - {"NodeDot", Const, 0}, - {"NodeField", Const, 0}, - {"NodeIdentifier", Const, 0}, - {"NodeIf", Const, 0}, - {"NodeList", Const, 0}, - {"NodeNil", Const, 1}, - {"NodeNumber", Const, 0}, - {"NodePipe", Const, 0}, - {"NodeRange", Const, 0}, - {"NodeString", Const, 0}, - {"NodeTemplate", Const, 0}, - {"NodeText", Const, 0}, - {"NodeType", Type, 0}, - {"NodeVariable", Const, 0}, - {"NodeWith", Const, 0}, - {"NumberNode", Type, 0}, - {"NumberNode.Complex128", Field, 0}, - {"NumberNode.Float64", Field, 0}, - {"NumberNode.Int64", Field, 0}, - {"NumberNode.IsComplex", Field, 0}, - {"NumberNode.IsFloat", Field, 0}, - {"NumberNode.IsInt", Field, 0}, - {"NumberNode.IsUint", Field, 0}, - {"NumberNode.NodeType", Field, 0}, - {"NumberNode.Pos", Field, 1}, - {"NumberNode.Text", Field, 0}, - {"NumberNode.Uint64", Field, 0}, - {"Parse", Func, 0}, - {"ParseComments", Const, 16}, - {"PipeNode", Type, 0}, - {"PipeNode.Cmds", Field, 0}, - {"PipeNode.Decl", Field, 0}, - {"PipeNode.IsAssign", Field, 11}, - {"PipeNode.Line", Field, 0}, - {"PipeNode.NodeType", Field, 0}, - {"PipeNode.Pos", Field, 1}, - {"Pos", Type, 1}, - {"RangeNode", Type, 0}, - {"RangeNode.BranchNode", Field, 0}, - {"SkipFuncCheck", Const, 17}, - {"StringNode", Type, 0}, - {"StringNode.NodeType", Field, 0}, - {"StringNode.Pos", Field, 1}, - {"StringNode.Quoted", Field, 0}, - {"StringNode.Text", Field, 0}, - {"TemplateNode", Type, 0}, - {"TemplateNode.Line", Field, 0}, - {"TemplateNode.Name", Field, 0}, - {"TemplateNode.NodeType", Field, 0}, - {"TemplateNode.Pipe", Field, 0}, - {"TemplateNode.Pos", Field, 1}, - {"TextNode", Type, 0}, - {"TextNode.NodeType", Field, 0}, - {"TextNode.Pos", Field, 1}, - {"TextNode.Text", Field, 0}, - {"Tree", Type, 0}, - {"Tree.Mode", Field, 16}, - {"Tree.Name", Field, 0}, - {"Tree.ParseName", Field, 1}, - {"Tree.Root", Field, 0}, - {"VariableNode", Type, 0}, - {"VariableNode.Ident", Field, 0}, - {"VariableNode.NodeType", Field, 0}, - {"VariableNode.Pos", Field, 1}, - {"WithNode", Type, 0}, - {"WithNode.BranchNode", Field, 0}, + {"(*ActionNode).Copy", Method, 0, ""}, + {"(*ActionNode).String", Method, 0, ""}, + {"(*BoolNode).Copy", Method, 0, ""}, + {"(*BoolNode).String", Method, 0, ""}, + {"(*BranchNode).Copy", Method, 4, ""}, + {"(*BranchNode).String", Method, 0, ""}, + {"(*BreakNode).Copy", Method, 18, ""}, + {"(*BreakNode).String", Method, 18, ""}, + {"(*ChainNode).Add", Method, 1, ""}, + {"(*ChainNode).Copy", Method, 1, ""}, + {"(*ChainNode).String", Method, 1, ""}, + {"(*CommandNode).Copy", Method, 0, ""}, + {"(*CommandNode).String", Method, 0, ""}, + {"(*CommentNode).Copy", Method, 16, ""}, + {"(*CommentNode).String", Method, 16, ""}, + {"(*ContinueNode).Copy", Method, 18, ""}, + {"(*ContinueNode).String", Method, 18, ""}, + {"(*DotNode).Copy", Method, 0, ""}, + {"(*DotNode).String", Method, 0, ""}, + {"(*DotNode).Type", Method, 0, ""}, + {"(*FieldNode).Copy", Method, 0, ""}, + {"(*FieldNode).String", Method, 0, ""}, + {"(*IdentifierNode).Copy", Method, 0, ""}, + {"(*IdentifierNode).SetPos", Method, 1, ""}, + {"(*IdentifierNode).SetTree", Method, 4, ""}, + {"(*IdentifierNode).String", Method, 0, ""}, + {"(*IfNode).Copy", Method, 0, ""}, + {"(*IfNode).String", Method, 0, ""}, + {"(*ListNode).Copy", Method, 0, ""}, + {"(*ListNode).CopyList", Method, 0, ""}, + {"(*ListNode).String", Method, 0, ""}, + {"(*NilNode).Copy", Method, 1, ""}, + {"(*NilNode).String", Method, 1, ""}, + {"(*NilNode).Type", Method, 1, ""}, + {"(*NumberNode).Copy", Method, 0, ""}, + {"(*NumberNode).String", Method, 0, ""}, + {"(*PipeNode).Copy", Method, 0, ""}, + {"(*PipeNode).CopyPipe", Method, 0, ""}, + {"(*PipeNode).String", Method, 0, ""}, + {"(*RangeNode).Copy", Method, 0, ""}, + {"(*RangeNode).String", Method, 0, ""}, + {"(*StringNode).Copy", Method, 0, ""}, + {"(*StringNode).String", Method, 0, ""}, + {"(*TemplateNode).Copy", Method, 0, ""}, + {"(*TemplateNode).String", Method, 0, ""}, + {"(*TextNode).Copy", Method, 0, ""}, + {"(*TextNode).String", Method, 0, ""}, + {"(*Tree).Copy", Method, 2, ""}, + {"(*Tree).ErrorContext", Method, 1, ""}, + {"(*Tree).Parse", Method, 0, ""}, + {"(*VariableNode).Copy", Method, 0, ""}, + {"(*VariableNode).String", Method, 0, ""}, + {"(*WithNode).Copy", Method, 0, ""}, + {"(*WithNode).String", Method, 0, ""}, + {"(ActionNode).Position", Method, 1, ""}, + {"(ActionNode).Type", Method, 0, ""}, + {"(BoolNode).Position", Method, 1, ""}, + {"(BoolNode).Type", Method, 0, ""}, + {"(BranchNode).Position", Method, 1, ""}, + {"(BranchNode).Type", Method, 0, ""}, + {"(BreakNode).Position", Method, 18, ""}, + {"(BreakNode).Type", Method, 18, ""}, + {"(ChainNode).Position", Method, 1, ""}, + {"(ChainNode).Type", Method, 1, ""}, + {"(CommandNode).Position", Method, 1, ""}, + {"(CommandNode).Type", Method, 0, ""}, + {"(CommentNode).Position", Method, 16, ""}, + {"(CommentNode).Type", Method, 16, ""}, + {"(ContinueNode).Position", Method, 18, ""}, + {"(ContinueNode).Type", Method, 18, ""}, + {"(DotNode).Position", Method, 1, ""}, + {"(FieldNode).Position", Method, 1, ""}, + {"(FieldNode).Type", Method, 0, ""}, + {"(IdentifierNode).Position", Method, 1, ""}, + {"(IdentifierNode).Type", Method, 0, ""}, + {"(IfNode).Position", Method, 1, ""}, + {"(IfNode).Type", Method, 0, ""}, + {"(ListNode).Position", Method, 1, ""}, + {"(ListNode).Type", Method, 0, ""}, + {"(NilNode).Position", Method, 1, ""}, + {"(NodeType).Type", Method, 0, ""}, + {"(NumberNode).Position", Method, 1, ""}, + {"(NumberNode).Type", Method, 0, ""}, + {"(PipeNode).Position", Method, 1, ""}, + {"(PipeNode).Type", Method, 0, ""}, + {"(Pos).Position", Method, 1, ""}, + {"(RangeNode).Position", Method, 1, ""}, + {"(RangeNode).Type", Method, 0, ""}, + {"(StringNode).Position", Method, 1, ""}, + {"(StringNode).Type", Method, 0, ""}, + {"(TemplateNode).Position", Method, 1, ""}, + {"(TemplateNode).Type", Method, 0, ""}, + {"(TextNode).Position", Method, 1, ""}, + {"(TextNode).Type", Method, 0, ""}, + {"(VariableNode).Position", Method, 1, ""}, + {"(VariableNode).Type", Method, 0, ""}, + {"(WithNode).Position", Method, 1, ""}, + {"(WithNode).Type", Method, 0, ""}, + {"ActionNode", Type, 0, ""}, + {"ActionNode.Line", Field, 0, ""}, + {"ActionNode.NodeType", Field, 0, ""}, + {"ActionNode.Pipe", Field, 0, ""}, + {"ActionNode.Pos", Field, 1, ""}, + {"BoolNode", Type, 0, ""}, + {"BoolNode.NodeType", Field, 0, ""}, + {"BoolNode.Pos", Field, 1, ""}, + {"BoolNode.True", Field, 0, ""}, + {"BranchNode", Type, 0, ""}, + {"BranchNode.ElseList", Field, 0, ""}, + {"BranchNode.Line", Field, 0, ""}, + {"BranchNode.List", Field, 0, ""}, + {"BranchNode.NodeType", Field, 0, ""}, + {"BranchNode.Pipe", Field, 0, ""}, + {"BranchNode.Pos", Field, 1, ""}, + {"BreakNode", Type, 18, ""}, + {"BreakNode.Line", Field, 18, ""}, + {"BreakNode.NodeType", Field, 18, ""}, + {"BreakNode.Pos", Field, 18, ""}, + {"ChainNode", Type, 1, ""}, + {"ChainNode.Field", Field, 1, ""}, + {"ChainNode.Node", Field, 1, ""}, + {"ChainNode.NodeType", Field, 1, ""}, + {"ChainNode.Pos", Field, 1, ""}, + {"CommandNode", Type, 0, ""}, + {"CommandNode.Args", Field, 0, ""}, + {"CommandNode.NodeType", Field, 0, ""}, + {"CommandNode.Pos", Field, 1, ""}, + {"CommentNode", Type, 16, ""}, + {"CommentNode.NodeType", Field, 16, ""}, + {"CommentNode.Pos", Field, 16, ""}, + {"CommentNode.Text", Field, 16, ""}, + {"ContinueNode", Type, 18, ""}, + {"ContinueNode.Line", Field, 18, ""}, + {"ContinueNode.NodeType", Field, 18, ""}, + {"ContinueNode.Pos", Field, 18, ""}, + {"DotNode", Type, 0, ""}, + {"DotNode.NodeType", Field, 4, ""}, + {"DotNode.Pos", Field, 1, ""}, + {"FieldNode", Type, 0, ""}, + {"FieldNode.Ident", Field, 0, ""}, + {"FieldNode.NodeType", Field, 0, ""}, + {"FieldNode.Pos", Field, 1, ""}, + {"IdentifierNode", Type, 0, ""}, + {"IdentifierNode.Ident", Field, 0, ""}, + {"IdentifierNode.NodeType", Field, 0, ""}, + {"IdentifierNode.Pos", Field, 1, ""}, + {"IfNode", Type, 0, ""}, + {"IfNode.BranchNode", Field, 0, ""}, + {"IsEmptyTree", Func, 0, "func(n Node) bool"}, + {"ListNode", Type, 0, ""}, + {"ListNode.NodeType", Field, 0, ""}, + {"ListNode.Nodes", Field, 0, ""}, + {"ListNode.Pos", Field, 1, ""}, + {"Mode", Type, 16, ""}, + {"New", Func, 0, "func(name string, funcs ...map[string]any) *Tree"}, + {"NewIdentifier", Func, 0, "func(ident string) *IdentifierNode"}, + {"NilNode", Type, 1, ""}, + {"NilNode.NodeType", Field, 4, ""}, + {"NilNode.Pos", Field, 1, ""}, + {"Node", Type, 0, ""}, + {"NodeAction", Const, 0, ""}, + {"NodeBool", Const, 0, ""}, + {"NodeBreak", Const, 18, ""}, + {"NodeChain", Const, 1, ""}, + {"NodeCommand", Const, 0, ""}, + {"NodeComment", Const, 16, ""}, + {"NodeContinue", Const, 18, ""}, + {"NodeDot", Const, 0, ""}, + {"NodeField", Const, 0, ""}, + {"NodeIdentifier", Const, 0, ""}, + {"NodeIf", Const, 0, ""}, + {"NodeList", Const, 0, ""}, + {"NodeNil", Const, 1, ""}, + {"NodeNumber", Const, 0, ""}, + {"NodePipe", Const, 0, ""}, + {"NodeRange", Const, 0, ""}, + {"NodeString", Const, 0, ""}, + {"NodeTemplate", Const, 0, ""}, + {"NodeText", Const, 0, ""}, + {"NodeType", Type, 0, ""}, + {"NodeVariable", Const, 0, ""}, + {"NodeWith", Const, 0, ""}, + {"NumberNode", Type, 0, ""}, + {"NumberNode.Complex128", Field, 0, ""}, + {"NumberNode.Float64", Field, 0, ""}, + {"NumberNode.Int64", Field, 0, ""}, + {"NumberNode.IsComplex", Field, 0, ""}, + {"NumberNode.IsFloat", Field, 0, ""}, + {"NumberNode.IsInt", Field, 0, ""}, + {"NumberNode.IsUint", Field, 0, ""}, + {"NumberNode.NodeType", Field, 0, ""}, + {"NumberNode.Pos", Field, 1, ""}, + {"NumberNode.Text", Field, 0, ""}, + {"NumberNode.Uint64", Field, 0, ""}, + {"Parse", Func, 0, "func(name string, text string, leftDelim string, rightDelim string, funcs ...map[string]any) (map[string]*Tree, error)"}, + {"ParseComments", Const, 16, ""}, + {"PipeNode", Type, 0, ""}, + {"PipeNode.Cmds", Field, 0, ""}, + {"PipeNode.Decl", Field, 0, ""}, + {"PipeNode.IsAssign", Field, 11, ""}, + {"PipeNode.Line", Field, 0, ""}, + {"PipeNode.NodeType", Field, 0, ""}, + {"PipeNode.Pos", Field, 1, ""}, + {"Pos", Type, 1, ""}, + {"RangeNode", Type, 0, ""}, + {"RangeNode.BranchNode", Field, 0, ""}, + {"SkipFuncCheck", Const, 17, ""}, + {"StringNode", Type, 0, ""}, + {"StringNode.NodeType", Field, 0, ""}, + {"StringNode.Pos", Field, 1, ""}, + {"StringNode.Quoted", Field, 0, ""}, + {"StringNode.Text", Field, 0, ""}, + {"TemplateNode", Type, 0, ""}, + {"TemplateNode.Line", Field, 0, ""}, + {"TemplateNode.Name", Field, 0, ""}, + {"TemplateNode.NodeType", Field, 0, ""}, + {"TemplateNode.Pipe", Field, 0, ""}, + {"TemplateNode.Pos", Field, 1, ""}, + {"TextNode", Type, 0, ""}, + {"TextNode.NodeType", Field, 0, ""}, + {"TextNode.Pos", Field, 1, ""}, + {"TextNode.Text", Field, 0, ""}, + {"Tree", Type, 0, ""}, + {"Tree.Mode", Field, 16, ""}, + {"Tree.Name", Field, 0, ""}, + {"Tree.ParseName", Field, 1, ""}, + {"Tree.Root", Field, 0, ""}, + {"VariableNode", Type, 0, ""}, + {"VariableNode.Ident", Field, 0, ""}, + {"VariableNode.NodeType", Field, 0, ""}, + {"VariableNode.Pos", Field, 1, ""}, + {"WithNode", Type, 0, ""}, + {"WithNode.BranchNode", Field, 0, ""}, }, "time": { - {"(*Location).String", Method, 0}, - {"(*ParseError).Error", Method, 0}, - {"(*Ticker).Reset", Method, 15}, - {"(*Ticker).Stop", Method, 0}, - {"(*Time).GobDecode", Method, 0}, - {"(*Time).UnmarshalBinary", Method, 2}, - {"(*Time).UnmarshalJSON", Method, 0}, - {"(*Time).UnmarshalText", Method, 2}, - {"(*Timer).Reset", Method, 1}, - {"(*Timer).Stop", Method, 0}, - {"(Duration).Abs", Method, 19}, - {"(Duration).Hours", Method, 0}, - {"(Duration).Microseconds", Method, 13}, - {"(Duration).Milliseconds", Method, 13}, - {"(Duration).Minutes", Method, 0}, - {"(Duration).Nanoseconds", Method, 0}, - {"(Duration).Round", Method, 9}, - {"(Duration).Seconds", Method, 0}, - {"(Duration).String", Method, 0}, - {"(Duration).Truncate", Method, 9}, - {"(Month).String", Method, 0}, - {"(Time).Add", Method, 0}, - {"(Time).AddDate", Method, 0}, - {"(Time).After", Method, 0}, - {"(Time).AppendBinary", Method, 24}, - {"(Time).AppendFormat", Method, 5}, - {"(Time).AppendText", Method, 24}, - {"(Time).Before", Method, 0}, - {"(Time).Clock", Method, 0}, - {"(Time).Compare", Method, 20}, - {"(Time).Date", Method, 0}, - {"(Time).Day", Method, 0}, - {"(Time).Equal", Method, 0}, - {"(Time).Format", Method, 0}, - {"(Time).GoString", Method, 17}, - {"(Time).GobEncode", Method, 0}, - {"(Time).Hour", Method, 0}, - {"(Time).ISOWeek", Method, 0}, - {"(Time).In", Method, 0}, - {"(Time).IsDST", Method, 17}, - {"(Time).IsZero", Method, 0}, - {"(Time).Local", Method, 0}, - {"(Time).Location", Method, 0}, - {"(Time).MarshalBinary", Method, 2}, - {"(Time).MarshalJSON", Method, 0}, - {"(Time).MarshalText", Method, 2}, - {"(Time).Minute", Method, 0}, - {"(Time).Month", Method, 0}, - {"(Time).Nanosecond", Method, 0}, - {"(Time).Round", Method, 1}, - {"(Time).Second", Method, 0}, - {"(Time).String", Method, 0}, - {"(Time).Sub", Method, 0}, - {"(Time).Truncate", Method, 1}, - {"(Time).UTC", Method, 0}, - {"(Time).Unix", Method, 0}, - {"(Time).UnixMicro", Method, 17}, - {"(Time).UnixMilli", Method, 17}, - {"(Time).UnixNano", Method, 0}, - {"(Time).Weekday", Method, 0}, - {"(Time).Year", Method, 0}, - {"(Time).YearDay", Method, 1}, - {"(Time).Zone", Method, 0}, - {"(Time).ZoneBounds", Method, 19}, - {"(Weekday).String", Method, 0}, - {"ANSIC", Const, 0}, - {"After", Func, 0}, - {"AfterFunc", Func, 0}, - {"April", Const, 0}, - {"August", Const, 0}, - {"Date", Func, 0}, - {"DateOnly", Const, 20}, - {"DateTime", Const, 20}, - {"December", Const, 0}, - {"Duration", Type, 0}, - {"February", Const, 0}, - {"FixedZone", Func, 0}, - {"Friday", Const, 0}, - {"Hour", Const, 0}, - {"January", Const, 0}, - {"July", Const, 0}, - {"June", Const, 0}, - {"Kitchen", Const, 0}, - {"Layout", Const, 17}, - {"LoadLocation", Func, 0}, - {"LoadLocationFromTZData", Func, 10}, - {"Local", Var, 0}, - {"Location", Type, 0}, - {"March", Const, 0}, - {"May", Const, 0}, - {"Microsecond", Const, 0}, - {"Millisecond", Const, 0}, - {"Minute", Const, 0}, - {"Monday", Const, 0}, - {"Month", Type, 0}, - {"Nanosecond", Const, 0}, - {"NewTicker", Func, 0}, - {"NewTimer", Func, 0}, - {"November", Const, 0}, - {"Now", Func, 0}, - {"October", Const, 0}, - {"Parse", Func, 0}, - {"ParseDuration", Func, 0}, - {"ParseError", Type, 0}, - {"ParseError.Layout", Field, 0}, - {"ParseError.LayoutElem", Field, 0}, - {"ParseError.Message", Field, 0}, - {"ParseError.Value", Field, 0}, - {"ParseError.ValueElem", Field, 0}, - {"ParseInLocation", Func, 1}, - {"RFC1123", Const, 0}, - {"RFC1123Z", Const, 0}, - {"RFC3339", Const, 0}, - {"RFC3339Nano", Const, 0}, - {"RFC822", Const, 0}, - {"RFC822Z", Const, 0}, - {"RFC850", Const, 0}, - {"RubyDate", Const, 0}, - {"Saturday", Const, 0}, - {"Second", Const, 0}, - {"September", Const, 0}, - {"Since", Func, 0}, - {"Sleep", Func, 0}, - {"Stamp", Const, 0}, - {"StampMicro", Const, 0}, - {"StampMilli", Const, 0}, - {"StampNano", Const, 0}, - {"Sunday", Const, 0}, - {"Thursday", Const, 0}, - {"Tick", Func, 0}, - {"Ticker", Type, 0}, - {"Ticker.C", Field, 0}, - {"Time", Type, 0}, - {"TimeOnly", Const, 20}, - {"Timer", Type, 0}, - {"Timer.C", Field, 0}, - {"Tuesday", Const, 0}, - {"UTC", Var, 0}, - {"Unix", Func, 0}, - {"UnixDate", Const, 0}, - {"UnixMicro", Func, 17}, - {"UnixMilli", Func, 17}, - {"Until", Func, 8}, - {"Wednesday", Const, 0}, - {"Weekday", Type, 0}, + {"(*Location).String", Method, 0, ""}, + {"(*ParseError).Error", Method, 0, ""}, + {"(*Ticker).Reset", Method, 15, ""}, + {"(*Ticker).Stop", Method, 0, ""}, + {"(*Time).GobDecode", Method, 0, ""}, + {"(*Time).UnmarshalBinary", Method, 2, ""}, + {"(*Time).UnmarshalJSON", Method, 0, ""}, + {"(*Time).UnmarshalText", Method, 2, ""}, + {"(*Timer).Reset", Method, 1, ""}, + {"(*Timer).Stop", Method, 0, ""}, + {"(Duration).Abs", Method, 19, ""}, + {"(Duration).Hours", Method, 0, ""}, + {"(Duration).Microseconds", Method, 13, ""}, + {"(Duration).Milliseconds", Method, 13, ""}, + {"(Duration).Minutes", Method, 0, ""}, + {"(Duration).Nanoseconds", Method, 0, ""}, + {"(Duration).Round", Method, 9, ""}, + {"(Duration).Seconds", Method, 0, ""}, + {"(Duration).String", Method, 0, ""}, + {"(Duration).Truncate", Method, 9, ""}, + {"(Month).String", Method, 0, ""}, + {"(Time).Add", Method, 0, ""}, + {"(Time).AddDate", Method, 0, ""}, + {"(Time).After", Method, 0, ""}, + {"(Time).AppendBinary", Method, 24, ""}, + {"(Time).AppendFormat", Method, 5, ""}, + {"(Time).AppendText", Method, 24, ""}, + {"(Time).Before", Method, 0, ""}, + {"(Time).Clock", Method, 0, ""}, + {"(Time).Compare", Method, 20, ""}, + {"(Time).Date", Method, 0, ""}, + {"(Time).Day", Method, 0, ""}, + {"(Time).Equal", Method, 0, ""}, + {"(Time).Format", Method, 0, ""}, + {"(Time).GoString", Method, 17, ""}, + {"(Time).GobEncode", Method, 0, ""}, + {"(Time).Hour", Method, 0, ""}, + {"(Time).ISOWeek", Method, 0, ""}, + {"(Time).In", Method, 0, ""}, + {"(Time).IsDST", Method, 17, ""}, + {"(Time).IsZero", Method, 0, ""}, + {"(Time).Local", Method, 0, ""}, + {"(Time).Location", Method, 0, ""}, + {"(Time).MarshalBinary", Method, 2, ""}, + {"(Time).MarshalJSON", Method, 0, ""}, + {"(Time).MarshalText", Method, 2, ""}, + {"(Time).Minute", Method, 0, ""}, + {"(Time).Month", Method, 0, ""}, + {"(Time).Nanosecond", Method, 0, ""}, + {"(Time).Round", Method, 1, ""}, + {"(Time).Second", Method, 0, ""}, + {"(Time).String", Method, 0, ""}, + {"(Time).Sub", Method, 0, ""}, + {"(Time).Truncate", Method, 1, ""}, + {"(Time).UTC", Method, 0, ""}, + {"(Time).Unix", Method, 0, ""}, + {"(Time).UnixMicro", Method, 17, ""}, + {"(Time).UnixMilli", Method, 17, ""}, + {"(Time).UnixNano", Method, 0, ""}, + {"(Time).Weekday", Method, 0, ""}, + {"(Time).Year", Method, 0, ""}, + {"(Time).YearDay", Method, 1, ""}, + {"(Time).Zone", Method, 0, ""}, + {"(Time).ZoneBounds", Method, 19, ""}, + {"(Weekday).String", Method, 0, ""}, + {"ANSIC", Const, 0, ""}, + {"After", Func, 0, "func(d Duration) <-chan Time"}, + {"AfterFunc", Func, 0, "func(d Duration, f func()) *Timer"}, + {"April", Const, 0, ""}, + {"August", Const, 0, ""}, + {"Date", Func, 0, "func(year int, month Month, day int, hour int, min int, sec int, nsec int, loc *Location) Time"}, + {"DateOnly", Const, 20, ""}, + {"DateTime", Const, 20, ""}, + {"December", Const, 0, ""}, + {"Duration", Type, 0, ""}, + {"February", Const, 0, ""}, + {"FixedZone", Func, 0, "func(name string, offset int) *Location"}, + {"Friday", Const, 0, ""}, + {"Hour", Const, 0, ""}, + {"January", Const, 0, ""}, + {"July", Const, 0, ""}, + {"June", Const, 0, ""}, + {"Kitchen", Const, 0, ""}, + {"Layout", Const, 17, ""}, + {"LoadLocation", Func, 0, "func(name string) (*Location, error)"}, + {"LoadLocationFromTZData", Func, 10, "func(name string, data []byte) (*Location, error)"}, + {"Local", Var, 0, ""}, + {"Location", Type, 0, ""}, + {"March", Const, 0, ""}, + {"May", Const, 0, ""}, + {"Microsecond", Const, 0, ""}, + {"Millisecond", Const, 0, ""}, + {"Minute", Const, 0, ""}, + {"Monday", Const, 0, ""}, + {"Month", Type, 0, ""}, + {"Nanosecond", Const, 0, ""}, + {"NewTicker", Func, 0, "func(d Duration) *Ticker"}, + {"NewTimer", Func, 0, "func(d Duration) *Timer"}, + {"November", Const, 0, ""}, + {"Now", Func, 0, "func() Time"}, + {"October", Const, 0, ""}, + {"Parse", Func, 0, "func(layout string, value string) (Time, error)"}, + {"ParseDuration", Func, 0, "func(s string) (Duration, error)"}, + {"ParseError", Type, 0, ""}, + {"ParseError.Layout", Field, 0, ""}, + {"ParseError.LayoutElem", Field, 0, ""}, + {"ParseError.Message", Field, 0, ""}, + {"ParseError.Value", Field, 0, ""}, + {"ParseError.ValueElem", Field, 0, ""}, + {"ParseInLocation", Func, 1, "func(layout string, value string, loc *Location) (Time, error)"}, + {"RFC1123", Const, 0, ""}, + {"RFC1123Z", Const, 0, ""}, + {"RFC3339", Const, 0, ""}, + {"RFC3339Nano", Const, 0, ""}, + {"RFC822", Const, 0, ""}, + {"RFC822Z", Const, 0, ""}, + {"RFC850", Const, 0, ""}, + {"RubyDate", Const, 0, ""}, + {"Saturday", Const, 0, ""}, + {"Second", Const, 0, ""}, + {"September", Const, 0, ""}, + {"Since", Func, 0, "func(t Time) Duration"}, + {"Sleep", Func, 0, "func(d Duration)"}, + {"Stamp", Const, 0, ""}, + {"StampMicro", Const, 0, ""}, + {"StampMilli", Const, 0, ""}, + {"StampNano", Const, 0, ""}, + {"Sunday", Const, 0, ""}, + {"Thursday", Const, 0, ""}, + {"Tick", Func, 0, "func(d Duration) <-chan Time"}, + {"Ticker", Type, 0, ""}, + {"Ticker.C", Field, 0, ""}, + {"Time", Type, 0, ""}, + {"TimeOnly", Const, 20, ""}, + {"Timer", Type, 0, ""}, + {"Timer.C", Field, 0, ""}, + {"Tuesday", Const, 0, ""}, + {"UTC", Var, 0, ""}, + {"Unix", Func, 0, "func(sec int64, nsec int64) Time"}, + {"UnixDate", Const, 0, ""}, + {"UnixMicro", Func, 17, "func(usec int64) Time"}, + {"UnixMilli", Func, 17, "func(msec int64) Time"}, + {"Until", Func, 8, "func(t Time) Duration"}, + {"Wednesday", Const, 0, ""}, + {"Weekday", Type, 0, ""}, }, "unicode": { - {"(SpecialCase).ToLower", Method, 0}, - {"(SpecialCase).ToTitle", Method, 0}, - {"(SpecialCase).ToUpper", Method, 0}, - {"ASCII_Hex_Digit", Var, 0}, - {"Adlam", Var, 7}, - {"Ahom", Var, 5}, - {"Anatolian_Hieroglyphs", Var, 5}, - {"Arabic", Var, 0}, - {"Armenian", Var, 0}, - {"Avestan", Var, 0}, - {"AzeriCase", Var, 0}, - {"Balinese", Var, 0}, - {"Bamum", Var, 0}, - {"Bassa_Vah", Var, 4}, - {"Batak", Var, 0}, - {"Bengali", Var, 0}, - {"Bhaiksuki", Var, 7}, - {"Bidi_Control", Var, 0}, - {"Bopomofo", Var, 0}, - {"Brahmi", Var, 0}, - {"Braille", Var, 0}, - {"Buginese", Var, 0}, - {"Buhid", Var, 0}, - {"C", Var, 0}, - {"Canadian_Aboriginal", Var, 0}, - {"Carian", Var, 0}, - {"CaseRange", Type, 0}, - {"CaseRange.Delta", Field, 0}, - {"CaseRange.Hi", Field, 0}, - {"CaseRange.Lo", Field, 0}, - {"CaseRanges", Var, 0}, - {"Categories", Var, 0}, - {"Caucasian_Albanian", Var, 4}, - {"Cc", Var, 0}, - {"Cf", Var, 0}, - {"Chakma", Var, 1}, - {"Cham", Var, 0}, - {"Cherokee", Var, 0}, - {"Chorasmian", Var, 16}, - {"Co", Var, 0}, - {"Common", Var, 0}, - {"Coptic", Var, 0}, - {"Cs", Var, 0}, - {"Cuneiform", Var, 0}, - {"Cypriot", Var, 0}, - {"Cypro_Minoan", Var, 21}, - {"Cyrillic", Var, 0}, - {"Dash", Var, 0}, - {"Deprecated", Var, 0}, - {"Deseret", Var, 0}, - {"Devanagari", Var, 0}, - {"Diacritic", Var, 0}, - {"Digit", Var, 0}, - {"Dives_Akuru", Var, 16}, - {"Dogra", Var, 13}, - {"Duployan", Var, 4}, - {"Egyptian_Hieroglyphs", Var, 0}, - {"Elbasan", Var, 4}, - {"Elymaic", Var, 14}, - {"Ethiopic", Var, 0}, - {"Extender", Var, 0}, - {"FoldCategory", Var, 0}, - {"FoldScript", Var, 0}, - {"Georgian", Var, 0}, - {"Glagolitic", Var, 0}, - {"Gothic", Var, 0}, - {"Grantha", Var, 4}, - {"GraphicRanges", Var, 0}, - {"Greek", Var, 0}, - {"Gujarati", Var, 0}, - {"Gunjala_Gondi", Var, 13}, - {"Gurmukhi", Var, 0}, - {"Han", Var, 0}, - {"Hangul", Var, 0}, - {"Hanifi_Rohingya", Var, 13}, - {"Hanunoo", Var, 0}, - {"Hatran", Var, 5}, - {"Hebrew", Var, 0}, - {"Hex_Digit", Var, 0}, - {"Hiragana", Var, 0}, - {"Hyphen", Var, 0}, - {"IDS_Binary_Operator", Var, 0}, - {"IDS_Trinary_Operator", Var, 0}, - {"Ideographic", Var, 0}, - {"Imperial_Aramaic", Var, 0}, - {"In", Func, 2}, - {"Inherited", Var, 0}, - {"Inscriptional_Pahlavi", Var, 0}, - {"Inscriptional_Parthian", Var, 0}, - {"Is", Func, 0}, - {"IsControl", Func, 0}, - {"IsDigit", Func, 0}, - {"IsGraphic", Func, 0}, - {"IsLetter", Func, 0}, - {"IsLower", Func, 0}, - {"IsMark", Func, 0}, - {"IsNumber", Func, 0}, - {"IsOneOf", Func, 0}, - {"IsPrint", Func, 0}, - {"IsPunct", Func, 0}, - {"IsSpace", Func, 0}, - {"IsSymbol", Func, 0}, - {"IsTitle", Func, 0}, - {"IsUpper", Func, 0}, - {"Javanese", Var, 0}, - {"Join_Control", Var, 0}, - {"Kaithi", Var, 0}, - {"Kannada", Var, 0}, - {"Katakana", Var, 0}, - {"Kawi", Var, 21}, - {"Kayah_Li", Var, 0}, - {"Kharoshthi", Var, 0}, - {"Khitan_Small_Script", Var, 16}, - {"Khmer", Var, 0}, - {"Khojki", Var, 4}, - {"Khudawadi", Var, 4}, - {"L", Var, 0}, - {"Lao", Var, 0}, - {"Latin", Var, 0}, - {"Lepcha", Var, 0}, - {"Letter", Var, 0}, - {"Limbu", Var, 0}, - {"Linear_A", Var, 4}, - {"Linear_B", Var, 0}, - {"Lisu", Var, 0}, - {"Ll", Var, 0}, - {"Lm", Var, 0}, - {"Lo", Var, 0}, - {"Logical_Order_Exception", Var, 0}, - {"Lower", Var, 0}, - {"LowerCase", Const, 0}, - {"Lt", Var, 0}, - {"Lu", Var, 0}, - {"Lycian", Var, 0}, - {"Lydian", Var, 0}, - {"M", Var, 0}, - {"Mahajani", Var, 4}, - {"Makasar", Var, 13}, - {"Malayalam", Var, 0}, - {"Mandaic", Var, 0}, - {"Manichaean", Var, 4}, - {"Marchen", Var, 7}, - {"Mark", Var, 0}, - {"Masaram_Gondi", Var, 10}, - {"MaxASCII", Const, 0}, - {"MaxCase", Const, 0}, - {"MaxLatin1", Const, 0}, - {"MaxRune", Const, 0}, - {"Mc", Var, 0}, - {"Me", Var, 0}, - {"Medefaidrin", Var, 13}, - {"Meetei_Mayek", Var, 0}, - {"Mende_Kikakui", Var, 4}, - {"Meroitic_Cursive", Var, 1}, - {"Meroitic_Hieroglyphs", Var, 1}, - {"Miao", Var, 1}, - {"Mn", Var, 0}, - {"Modi", Var, 4}, - {"Mongolian", Var, 0}, - {"Mro", Var, 4}, - {"Multani", Var, 5}, - {"Myanmar", Var, 0}, - {"N", Var, 0}, - {"Nabataean", Var, 4}, - {"Nag_Mundari", Var, 21}, - {"Nandinagari", Var, 14}, - {"Nd", Var, 0}, - {"New_Tai_Lue", Var, 0}, - {"Newa", Var, 7}, - {"Nko", Var, 0}, - {"Nl", Var, 0}, - {"No", Var, 0}, - {"Noncharacter_Code_Point", Var, 0}, - {"Number", Var, 0}, - {"Nushu", Var, 10}, - {"Nyiakeng_Puachue_Hmong", Var, 14}, - {"Ogham", Var, 0}, - {"Ol_Chiki", Var, 0}, - {"Old_Hungarian", Var, 5}, - {"Old_Italic", Var, 0}, - {"Old_North_Arabian", Var, 4}, - {"Old_Permic", Var, 4}, - {"Old_Persian", Var, 0}, - {"Old_Sogdian", Var, 13}, - {"Old_South_Arabian", Var, 0}, - {"Old_Turkic", Var, 0}, - {"Old_Uyghur", Var, 21}, - {"Oriya", Var, 0}, - {"Osage", Var, 7}, - {"Osmanya", Var, 0}, - {"Other", Var, 0}, - {"Other_Alphabetic", Var, 0}, - {"Other_Default_Ignorable_Code_Point", Var, 0}, - {"Other_Grapheme_Extend", Var, 0}, - {"Other_ID_Continue", Var, 0}, - {"Other_ID_Start", Var, 0}, - {"Other_Lowercase", Var, 0}, - {"Other_Math", Var, 0}, - {"Other_Uppercase", Var, 0}, - {"P", Var, 0}, - {"Pahawh_Hmong", Var, 4}, - {"Palmyrene", Var, 4}, - {"Pattern_Syntax", Var, 0}, - {"Pattern_White_Space", Var, 0}, - {"Pau_Cin_Hau", Var, 4}, - {"Pc", Var, 0}, - {"Pd", Var, 0}, - {"Pe", Var, 0}, - {"Pf", Var, 0}, - {"Phags_Pa", Var, 0}, - {"Phoenician", Var, 0}, - {"Pi", Var, 0}, - {"Po", Var, 0}, - {"Prepended_Concatenation_Mark", Var, 7}, - {"PrintRanges", Var, 0}, - {"Properties", Var, 0}, - {"Ps", Var, 0}, - {"Psalter_Pahlavi", Var, 4}, - {"Punct", Var, 0}, - {"Quotation_Mark", Var, 0}, - {"Radical", Var, 0}, - {"Range16", Type, 0}, - {"Range16.Hi", Field, 0}, - {"Range16.Lo", Field, 0}, - {"Range16.Stride", Field, 0}, - {"Range32", Type, 0}, - {"Range32.Hi", Field, 0}, - {"Range32.Lo", Field, 0}, - {"Range32.Stride", Field, 0}, - {"RangeTable", Type, 0}, - {"RangeTable.LatinOffset", Field, 1}, - {"RangeTable.R16", Field, 0}, - {"RangeTable.R32", Field, 0}, - {"Regional_Indicator", Var, 10}, - {"Rejang", Var, 0}, - {"ReplacementChar", Const, 0}, - {"Runic", Var, 0}, - {"S", Var, 0}, - {"STerm", Var, 0}, - {"Samaritan", Var, 0}, - {"Saurashtra", Var, 0}, - {"Sc", Var, 0}, - {"Scripts", Var, 0}, - {"Sentence_Terminal", Var, 7}, - {"Sharada", Var, 1}, - {"Shavian", Var, 0}, - {"Siddham", Var, 4}, - {"SignWriting", Var, 5}, - {"SimpleFold", Func, 0}, - {"Sinhala", Var, 0}, - {"Sk", Var, 0}, - {"Sm", Var, 0}, - {"So", Var, 0}, - {"Soft_Dotted", Var, 0}, - {"Sogdian", Var, 13}, - {"Sora_Sompeng", Var, 1}, - {"Soyombo", Var, 10}, - {"Space", Var, 0}, - {"SpecialCase", Type, 0}, - {"Sundanese", Var, 0}, - {"Syloti_Nagri", Var, 0}, - {"Symbol", Var, 0}, - {"Syriac", Var, 0}, - {"Tagalog", Var, 0}, - {"Tagbanwa", Var, 0}, - {"Tai_Le", Var, 0}, - {"Tai_Tham", Var, 0}, - {"Tai_Viet", Var, 0}, - {"Takri", Var, 1}, - {"Tamil", Var, 0}, - {"Tangsa", Var, 21}, - {"Tangut", Var, 7}, - {"Telugu", Var, 0}, - {"Terminal_Punctuation", Var, 0}, - {"Thaana", Var, 0}, - {"Thai", Var, 0}, - {"Tibetan", Var, 0}, - {"Tifinagh", Var, 0}, - {"Tirhuta", Var, 4}, - {"Title", Var, 0}, - {"TitleCase", Const, 0}, - {"To", Func, 0}, - {"ToLower", Func, 0}, - {"ToTitle", Func, 0}, - {"ToUpper", Func, 0}, - {"Toto", Var, 21}, - {"TurkishCase", Var, 0}, - {"Ugaritic", Var, 0}, - {"Unified_Ideograph", Var, 0}, - {"Upper", Var, 0}, - {"UpperCase", Const, 0}, - {"UpperLower", Const, 0}, - {"Vai", Var, 0}, - {"Variation_Selector", Var, 0}, - {"Version", Const, 0}, - {"Vithkuqi", Var, 21}, - {"Wancho", Var, 14}, - {"Warang_Citi", Var, 4}, - {"White_Space", Var, 0}, - {"Yezidi", Var, 16}, - {"Yi", Var, 0}, - {"Z", Var, 0}, - {"Zanabazar_Square", Var, 10}, - {"Zl", Var, 0}, - {"Zp", Var, 0}, - {"Zs", Var, 0}, + {"(SpecialCase).ToLower", Method, 0, ""}, + {"(SpecialCase).ToTitle", Method, 0, ""}, + {"(SpecialCase).ToUpper", Method, 0, ""}, + {"ASCII_Hex_Digit", Var, 0, ""}, + {"Adlam", Var, 7, ""}, + {"Ahom", Var, 5, ""}, + {"Anatolian_Hieroglyphs", Var, 5, ""}, + {"Arabic", Var, 0, ""}, + {"Armenian", Var, 0, ""}, + {"Avestan", Var, 0, ""}, + {"AzeriCase", Var, 0, ""}, + {"Balinese", Var, 0, ""}, + {"Bamum", Var, 0, ""}, + {"Bassa_Vah", Var, 4, ""}, + {"Batak", Var, 0, ""}, + {"Bengali", Var, 0, ""}, + {"Bhaiksuki", Var, 7, ""}, + {"Bidi_Control", Var, 0, ""}, + {"Bopomofo", Var, 0, ""}, + {"Brahmi", Var, 0, ""}, + {"Braille", Var, 0, ""}, + {"Buginese", Var, 0, ""}, + {"Buhid", Var, 0, ""}, + {"C", Var, 0, ""}, + {"Canadian_Aboriginal", Var, 0, ""}, + {"Carian", Var, 0, ""}, + {"CaseRange", Type, 0, ""}, + {"CaseRange.Delta", Field, 0, ""}, + {"CaseRange.Hi", Field, 0, ""}, + {"CaseRange.Lo", Field, 0, ""}, + {"CaseRanges", Var, 0, ""}, + {"Categories", Var, 0, ""}, + {"Caucasian_Albanian", Var, 4, ""}, + {"Cc", Var, 0, ""}, + {"Cf", Var, 0, ""}, + {"Chakma", Var, 1, ""}, + {"Cham", Var, 0, ""}, + {"Cherokee", Var, 0, ""}, + {"Chorasmian", Var, 16, ""}, + {"Co", Var, 0, ""}, + {"Common", Var, 0, ""}, + {"Coptic", Var, 0, ""}, + {"Cs", Var, 0, ""}, + {"Cuneiform", Var, 0, ""}, + {"Cypriot", Var, 0, ""}, + {"Cypro_Minoan", Var, 21, ""}, + {"Cyrillic", Var, 0, ""}, + {"Dash", Var, 0, ""}, + {"Deprecated", Var, 0, ""}, + {"Deseret", Var, 0, ""}, + {"Devanagari", Var, 0, ""}, + {"Diacritic", Var, 0, ""}, + {"Digit", Var, 0, ""}, + {"Dives_Akuru", Var, 16, ""}, + {"Dogra", Var, 13, ""}, + {"Duployan", Var, 4, ""}, + {"Egyptian_Hieroglyphs", Var, 0, ""}, + {"Elbasan", Var, 4, ""}, + {"Elymaic", Var, 14, ""}, + {"Ethiopic", Var, 0, ""}, + {"Extender", Var, 0, ""}, + {"FoldCategory", Var, 0, ""}, + {"FoldScript", Var, 0, ""}, + {"Georgian", Var, 0, ""}, + {"Glagolitic", Var, 0, ""}, + {"Gothic", Var, 0, ""}, + {"Grantha", Var, 4, ""}, + {"GraphicRanges", Var, 0, ""}, + {"Greek", Var, 0, ""}, + {"Gujarati", Var, 0, ""}, + {"Gunjala_Gondi", Var, 13, ""}, + {"Gurmukhi", Var, 0, ""}, + {"Han", Var, 0, ""}, + {"Hangul", Var, 0, ""}, + {"Hanifi_Rohingya", Var, 13, ""}, + {"Hanunoo", Var, 0, ""}, + {"Hatran", Var, 5, ""}, + {"Hebrew", Var, 0, ""}, + {"Hex_Digit", Var, 0, ""}, + {"Hiragana", Var, 0, ""}, + {"Hyphen", Var, 0, ""}, + {"IDS_Binary_Operator", Var, 0, ""}, + {"IDS_Trinary_Operator", Var, 0, ""}, + {"Ideographic", Var, 0, ""}, + {"Imperial_Aramaic", Var, 0, ""}, + {"In", Func, 2, "func(r rune, ranges ...*RangeTable) bool"}, + {"Inherited", Var, 0, ""}, + {"Inscriptional_Pahlavi", Var, 0, ""}, + {"Inscriptional_Parthian", Var, 0, ""}, + {"Is", Func, 0, "func(rangeTab *RangeTable, r rune) bool"}, + {"IsControl", Func, 0, "func(r rune) bool"}, + {"IsDigit", Func, 0, "func(r rune) bool"}, + {"IsGraphic", Func, 0, "func(r rune) bool"}, + {"IsLetter", Func, 0, "func(r rune) bool"}, + {"IsLower", Func, 0, "func(r rune) bool"}, + {"IsMark", Func, 0, "func(r rune) bool"}, + {"IsNumber", Func, 0, "func(r rune) bool"}, + {"IsOneOf", Func, 0, "func(ranges []*RangeTable, r rune) bool"}, + {"IsPrint", Func, 0, "func(r rune) bool"}, + {"IsPunct", Func, 0, "func(r rune) bool"}, + {"IsSpace", Func, 0, "func(r rune) bool"}, + {"IsSymbol", Func, 0, "func(r rune) bool"}, + {"IsTitle", Func, 0, "func(r rune) bool"}, + {"IsUpper", Func, 0, "func(r rune) bool"}, + {"Javanese", Var, 0, ""}, + {"Join_Control", Var, 0, ""}, + {"Kaithi", Var, 0, ""}, + {"Kannada", Var, 0, ""}, + {"Katakana", Var, 0, ""}, + {"Kawi", Var, 21, ""}, + {"Kayah_Li", Var, 0, ""}, + {"Kharoshthi", Var, 0, ""}, + {"Khitan_Small_Script", Var, 16, ""}, + {"Khmer", Var, 0, ""}, + {"Khojki", Var, 4, ""}, + {"Khudawadi", Var, 4, ""}, + {"L", Var, 0, ""}, + {"Lao", Var, 0, ""}, + {"Latin", Var, 0, ""}, + {"Lepcha", Var, 0, ""}, + {"Letter", Var, 0, ""}, + {"Limbu", Var, 0, ""}, + {"Linear_A", Var, 4, ""}, + {"Linear_B", Var, 0, ""}, + {"Lisu", Var, 0, ""}, + {"Ll", Var, 0, ""}, + {"Lm", Var, 0, ""}, + {"Lo", Var, 0, ""}, + {"Logical_Order_Exception", Var, 0, ""}, + {"Lower", Var, 0, ""}, + {"LowerCase", Const, 0, ""}, + {"Lt", Var, 0, ""}, + {"Lu", Var, 0, ""}, + {"Lycian", Var, 0, ""}, + {"Lydian", Var, 0, ""}, + {"M", Var, 0, ""}, + {"Mahajani", Var, 4, ""}, + {"Makasar", Var, 13, ""}, + {"Malayalam", Var, 0, ""}, + {"Mandaic", Var, 0, ""}, + {"Manichaean", Var, 4, ""}, + {"Marchen", Var, 7, ""}, + {"Mark", Var, 0, ""}, + {"Masaram_Gondi", Var, 10, ""}, + {"MaxASCII", Const, 0, ""}, + {"MaxCase", Const, 0, ""}, + {"MaxLatin1", Const, 0, ""}, + {"MaxRune", Const, 0, ""}, + {"Mc", Var, 0, ""}, + {"Me", Var, 0, ""}, + {"Medefaidrin", Var, 13, ""}, + {"Meetei_Mayek", Var, 0, ""}, + {"Mende_Kikakui", Var, 4, ""}, + {"Meroitic_Cursive", Var, 1, ""}, + {"Meroitic_Hieroglyphs", Var, 1, ""}, + {"Miao", Var, 1, ""}, + {"Mn", Var, 0, ""}, + {"Modi", Var, 4, ""}, + {"Mongolian", Var, 0, ""}, + {"Mro", Var, 4, ""}, + {"Multani", Var, 5, ""}, + {"Myanmar", Var, 0, ""}, + {"N", Var, 0, ""}, + {"Nabataean", Var, 4, ""}, + {"Nag_Mundari", Var, 21, ""}, + {"Nandinagari", Var, 14, ""}, + {"Nd", Var, 0, ""}, + {"New_Tai_Lue", Var, 0, ""}, + {"Newa", Var, 7, ""}, + {"Nko", Var, 0, ""}, + {"Nl", Var, 0, ""}, + {"No", Var, 0, ""}, + {"Noncharacter_Code_Point", Var, 0, ""}, + {"Number", Var, 0, ""}, + {"Nushu", Var, 10, ""}, + {"Nyiakeng_Puachue_Hmong", Var, 14, ""}, + {"Ogham", Var, 0, ""}, + {"Ol_Chiki", Var, 0, ""}, + {"Old_Hungarian", Var, 5, ""}, + {"Old_Italic", Var, 0, ""}, + {"Old_North_Arabian", Var, 4, ""}, + {"Old_Permic", Var, 4, ""}, + {"Old_Persian", Var, 0, ""}, + {"Old_Sogdian", Var, 13, ""}, + {"Old_South_Arabian", Var, 0, ""}, + {"Old_Turkic", Var, 0, ""}, + {"Old_Uyghur", Var, 21, ""}, + {"Oriya", Var, 0, ""}, + {"Osage", Var, 7, ""}, + {"Osmanya", Var, 0, ""}, + {"Other", Var, 0, ""}, + {"Other_Alphabetic", Var, 0, ""}, + {"Other_Default_Ignorable_Code_Point", Var, 0, ""}, + {"Other_Grapheme_Extend", Var, 0, ""}, + {"Other_ID_Continue", Var, 0, ""}, + {"Other_ID_Start", Var, 0, ""}, + {"Other_Lowercase", Var, 0, ""}, + {"Other_Math", Var, 0, ""}, + {"Other_Uppercase", Var, 0, ""}, + {"P", Var, 0, ""}, + {"Pahawh_Hmong", Var, 4, ""}, + {"Palmyrene", Var, 4, ""}, + {"Pattern_Syntax", Var, 0, ""}, + {"Pattern_White_Space", Var, 0, ""}, + {"Pau_Cin_Hau", Var, 4, ""}, + {"Pc", Var, 0, ""}, + {"Pd", Var, 0, ""}, + {"Pe", Var, 0, ""}, + {"Pf", Var, 0, ""}, + {"Phags_Pa", Var, 0, ""}, + {"Phoenician", Var, 0, ""}, + {"Pi", Var, 0, ""}, + {"Po", Var, 0, ""}, + {"Prepended_Concatenation_Mark", Var, 7, ""}, + {"PrintRanges", Var, 0, ""}, + {"Properties", Var, 0, ""}, + {"Ps", Var, 0, ""}, + {"Psalter_Pahlavi", Var, 4, ""}, + {"Punct", Var, 0, ""}, + {"Quotation_Mark", Var, 0, ""}, + {"Radical", Var, 0, ""}, + {"Range16", Type, 0, ""}, + {"Range16.Hi", Field, 0, ""}, + {"Range16.Lo", Field, 0, ""}, + {"Range16.Stride", Field, 0, ""}, + {"Range32", Type, 0, ""}, + {"Range32.Hi", Field, 0, ""}, + {"Range32.Lo", Field, 0, ""}, + {"Range32.Stride", Field, 0, ""}, + {"RangeTable", Type, 0, ""}, + {"RangeTable.LatinOffset", Field, 1, ""}, + {"RangeTable.R16", Field, 0, ""}, + {"RangeTable.R32", Field, 0, ""}, + {"Regional_Indicator", Var, 10, ""}, + {"Rejang", Var, 0, ""}, + {"ReplacementChar", Const, 0, ""}, + {"Runic", Var, 0, ""}, + {"S", Var, 0, ""}, + {"STerm", Var, 0, ""}, + {"Samaritan", Var, 0, ""}, + {"Saurashtra", Var, 0, ""}, + {"Sc", Var, 0, ""}, + {"Scripts", Var, 0, ""}, + {"Sentence_Terminal", Var, 7, ""}, + {"Sharada", Var, 1, ""}, + {"Shavian", Var, 0, ""}, + {"Siddham", Var, 4, ""}, + {"SignWriting", Var, 5, ""}, + {"SimpleFold", Func, 0, "func(r rune) rune"}, + {"Sinhala", Var, 0, ""}, + {"Sk", Var, 0, ""}, + {"Sm", Var, 0, ""}, + {"So", Var, 0, ""}, + {"Soft_Dotted", Var, 0, ""}, + {"Sogdian", Var, 13, ""}, + {"Sora_Sompeng", Var, 1, ""}, + {"Soyombo", Var, 10, ""}, + {"Space", Var, 0, ""}, + {"SpecialCase", Type, 0, ""}, + {"Sundanese", Var, 0, ""}, + {"Syloti_Nagri", Var, 0, ""}, + {"Symbol", Var, 0, ""}, + {"Syriac", Var, 0, ""}, + {"Tagalog", Var, 0, ""}, + {"Tagbanwa", Var, 0, ""}, + {"Tai_Le", Var, 0, ""}, + {"Tai_Tham", Var, 0, ""}, + {"Tai_Viet", Var, 0, ""}, + {"Takri", Var, 1, ""}, + {"Tamil", Var, 0, ""}, + {"Tangsa", Var, 21, ""}, + {"Tangut", Var, 7, ""}, + {"Telugu", Var, 0, ""}, + {"Terminal_Punctuation", Var, 0, ""}, + {"Thaana", Var, 0, ""}, + {"Thai", Var, 0, ""}, + {"Tibetan", Var, 0, ""}, + {"Tifinagh", Var, 0, ""}, + {"Tirhuta", Var, 4, ""}, + {"Title", Var, 0, ""}, + {"TitleCase", Const, 0, ""}, + {"To", Func, 0, "func(_case int, r rune) rune"}, + {"ToLower", Func, 0, "func(r rune) rune"}, + {"ToTitle", Func, 0, "func(r rune) rune"}, + {"ToUpper", Func, 0, "func(r rune) rune"}, + {"Toto", Var, 21, ""}, + {"TurkishCase", Var, 0, ""}, + {"Ugaritic", Var, 0, ""}, + {"Unified_Ideograph", Var, 0, ""}, + {"Upper", Var, 0, ""}, + {"UpperCase", Const, 0, ""}, + {"UpperLower", Const, 0, ""}, + {"Vai", Var, 0, ""}, + {"Variation_Selector", Var, 0, ""}, + {"Version", Const, 0, ""}, + {"Vithkuqi", Var, 21, ""}, + {"Wancho", Var, 14, ""}, + {"Warang_Citi", Var, 4, ""}, + {"White_Space", Var, 0, ""}, + {"Yezidi", Var, 16, ""}, + {"Yi", Var, 0, ""}, + {"Z", Var, 0, ""}, + {"Zanabazar_Square", Var, 10, ""}, + {"Zl", Var, 0, ""}, + {"Zp", Var, 0, ""}, + {"Zs", Var, 0, ""}, }, "unicode/utf16": { - {"AppendRune", Func, 20}, - {"Decode", Func, 0}, - {"DecodeRune", Func, 0}, - {"Encode", Func, 0}, - {"EncodeRune", Func, 0}, - {"IsSurrogate", Func, 0}, - {"RuneLen", Func, 23}, + {"AppendRune", Func, 20, "func(a []uint16, r rune) []uint16"}, + {"Decode", Func, 0, "func(s []uint16) []rune"}, + {"DecodeRune", Func, 0, "func(r1 rune, r2 rune) rune"}, + {"Encode", Func, 0, "func(s []rune) []uint16"}, + {"EncodeRune", Func, 0, "func(r rune) (r1 rune, r2 rune)"}, + {"IsSurrogate", Func, 0, "func(r rune) bool"}, + {"RuneLen", Func, 23, "func(r rune) int"}, }, "unicode/utf8": { - {"AppendRune", Func, 18}, - {"DecodeLastRune", Func, 0}, - {"DecodeLastRuneInString", Func, 0}, - {"DecodeRune", Func, 0}, - {"DecodeRuneInString", Func, 0}, - {"EncodeRune", Func, 0}, - {"FullRune", Func, 0}, - {"FullRuneInString", Func, 0}, - {"MaxRune", Const, 0}, - {"RuneCount", Func, 0}, - {"RuneCountInString", Func, 0}, - {"RuneError", Const, 0}, - {"RuneLen", Func, 0}, - {"RuneSelf", Const, 0}, - {"RuneStart", Func, 0}, - {"UTFMax", Const, 0}, - {"Valid", Func, 0}, - {"ValidRune", Func, 1}, - {"ValidString", Func, 0}, + {"AppendRune", Func, 18, "func(p []byte, r rune) []byte"}, + {"DecodeLastRune", Func, 0, "func(p []byte) (r rune, size int)"}, + {"DecodeLastRuneInString", Func, 0, "func(s string) (r rune, size int)"}, + {"DecodeRune", Func, 0, "func(p []byte) (r rune, size int)"}, + {"DecodeRuneInString", Func, 0, "func(s string) (r rune, size int)"}, + {"EncodeRune", Func, 0, "func(p []byte, r rune) int"}, + {"FullRune", Func, 0, "func(p []byte) bool"}, + {"FullRuneInString", Func, 0, "func(s string) bool"}, + {"MaxRune", Const, 0, ""}, + {"RuneCount", Func, 0, "func(p []byte) int"}, + {"RuneCountInString", Func, 0, "func(s string) (n int)"}, + {"RuneError", Const, 0, ""}, + {"RuneLen", Func, 0, "func(r rune) int"}, + {"RuneSelf", Const, 0, ""}, + {"RuneStart", Func, 0, "func(b byte) bool"}, + {"UTFMax", Const, 0, ""}, + {"Valid", Func, 0, "func(p []byte) bool"}, + {"ValidRune", Func, 1, "func(r rune) bool"}, + {"ValidString", Func, 0, "func(s string) bool"}, }, "unique": { - {"(Handle).Value", Method, 23}, - {"Handle", Type, 23}, - {"Make", Func, 23}, + {"(Handle).Value", Method, 23, ""}, + {"Handle", Type, 23, ""}, + {"Make", Func, 23, "func[T comparable](value T) Handle[T]"}, }, "unsafe": { - {"Add", Func, 0}, - {"Alignof", Func, 0}, - {"Offsetof", Func, 0}, - {"Pointer", Type, 0}, - {"Sizeof", Func, 0}, - {"Slice", Func, 0}, - {"SliceData", Func, 0}, - {"String", Func, 0}, - {"StringData", Func, 0}, + {"Add", Func, 0, ""}, + {"Alignof", Func, 0, ""}, + {"Offsetof", Func, 0, ""}, + {"Pointer", Type, 0, ""}, + {"Sizeof", Func, 0, ""}, + {"Slice", Func, 0, ""}, + {"SliceData", Func, 0, ""}, + {"String", Func, 0, ""}, + {"StringData", Func, 0, ""}, }, "weak": { - {"(Pointer).Value", Method, 24}, - {"Make", Func, 24}, - {"Pointer", Type, 24}, + {"(Pointer).Value", Method, 24, ""}, + {"Make", Func, 24, "func[T any](ptr *T) Pointer[T]"}, + {"Pointer", Type, 24, ""}, }, } -- diff -- # indent-heuristic: true @@ -8,17669 +8,17669 @@ var PackageSymbols = map[string][]Symbol{ "archive/tar": { - {"(*Header).FileInfo", Method, 1}, - {"(*Reader).Next", Method, 0}, - {"(*Reader).Read", Method, 0}, - {"(*Writer).AddFS", Method, 22}, - {"(*Writer).Close", Method, 0}, - {"(*Writer).Flush", Method, 0}, - {"(*Writer).Write", Method, 0}, - {"(*Writer).WriteHeader", Method, 0}, - {"(Format).String", Method, 10}, - {"ErrFieldTooLong", Var, 0}, - {"ErrHeader", Var, 0}, - {"ErrInsecurePath", Var, 20}, - {"ErrWriteAfterClose", Var, 0}, - {"ErrWriteTooLong", Var, 0}, - {"FileInfoHeader", Func, 1}, - {"FileInfoNames", Type, 23}, - {"Format", Type, 10}, - {"FormatGNU", Const, 10}, - {"FormatPAX", Const, 10}, - {"FormatUSTAR", Const, 10}, - {"FormatUnknown", Const, 10}, - {"Header", Type, 0}, - {"Header.AccessTime", Field, 0}, - {"Header.ChangeTime", Field, 0}, - {"Header.Devmajor", Field, 0}, - {"Header.Devminor", Field, 0}, - {"Header.Format", Field, 10}, - {"Header.Gid", Field, 0}, - {"Header.Gname", Field, 0}, - {"Header.Linkname", Field, 0}, - {"Header.ModTime", Field, 0}, - {"Header.Mode", Field, 0}, - {"Header.Name", Field, 0}, - {"Header.PAXRecords", Field, 10}, - {"Header.Size", Field, 0}, - {"Header.Typeflag", Field, 0}, - {"Header.Uid", Field, 0}, - {"Header.Uname", Field, 0}, - {"Header.Xattrs", Field, 3}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"Reader", Type, 0}, - {"TypeBlock", Const, 0}, - {"TypeChar", Const, 0}, - {"TypeCont", Const, 0}, - {"TypeDir", Const, 0}, - {"TypeFifo", Const, 0}, - {"TypeGNULongLink", Const, 1}, - {"TypeGNULongName", Const, 1}, - {"TypeGNUSparse", Const, 3}, - {"TypeLink", Const, 0}, - {"TypeReg", Const, 0}, - {"TypeRegA", Const, 0}, - {"TypeSymlink", Const, 0}, - {"TypeXGlobalHeader", Const, 0}, - {"TypeXHeader", Const, 0}, - {"Writer", Type, 0}, + {"(*Header).FileInfo", Method, 1, ""}, + {"(*Reader).Next", Method, 0, ""}, + {"(*Reader).Read", Method, 0, ""}, + {"(*Writer).AddFS", Method, 22, ""}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).Flush", Method, 0, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"(*Writer).WriteHeader", Method, 0, ""}, + {"(Format).String", Method, 10, ""}, + {"ErrFieldTooLong", Var, 0, ""}, + {"ErrHeader", Var, 0, ""}, + {"ErrInsecurePath", Var, 20, ""}, + {"ErrWriteAfterClose", Var, 0, ""}, + {"ErrWriteTooLong", Var, 0, ""}, + {"FileInfoHeader", Func, 1, "func(fi fs.FileInfo, link string) (*Header, error)"}, + {"FileInfoNames", Type, 23, ""}, + {"Format", Type, 10, ""}, + {"FormatGNU", Const, 10, ""}, + {"FormatPAX", Const, 10, ""}, + {"FormatUSTAR", Const, 10, ""}, + {"FormatUnknown", Const, 10, ""}, + {"Header", Type, 0, ""}, + {"Header.AccessTime", Field, 0, ""}, + {"Header.ChangeTime", Field, 0, ""}, + {"Header.Devmajor", Field, 0, ""}, + {"Header.Devminor", Field, 0, ""}, + {"Header.Format", Field, 10, ""}, + {"Header.Gid", Field, 0, ""}, + {"Header.Gname", Field, 0, ""}, + {"Header.Linkname", Field, 0, ""}, + {"Header.ModTime", Field, 0, ""}, + {"Header.Mode", Field, 0, ""}, + {"Header.Name", Field, 0, ""}, + {"Header.PAXRecords", Field, 10, ""}, + {"Header.Size", Field, 0, ""}, + {"Header.Typeflag", Field, 0, ""}, + {"Header.Uid", Field, 0, ""}, + {"Header.Uname", Field, 0, ""}, + {"Header.Xattrs", Field, 3, ""}, + {"NewReader", Func, 0, "func(r io.Reader) *Reader"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"Reader", Type, 0, ""}, + {"TypeBlock", Const, 0, ""}, + {"TypeChar", Const, 0, ""}, + {"TypeCont", Const, 0, ""}, + {"TypeDir", Const, 0, ""}, + {"TypeFifo", Const, 0, ""}, + {"TypeGNULongLink", Const, 1, ""}, + {"TypeGNULongName", Const, 1, ""}, + {"TypeGNUSparse", Const, 3, ""}, + {"TypeLink", Const, 0, ""}, + {"TypeReg", Const, 0, ""}, + {"TypeRegA", Const, 0, ""}, + {"TypeSymlink", Const, 0, ""}, + {"TypeXGlobalHeader", Const, 0, ""}, + {"TypeXHeader", Const, 0, ""}, + {"Writer", Type, 0, ""}, }, "archive/zip": { - {"(*File).DataOffset", Method, 2}, - {"(*File).FileInfo", Method, 0}, - {"(*File).ModTime", Method, 0}, - {"(*File).Mode", Method, 0}, - {"(*File).Open", Method, 0}, - {"(*File).OpenRaw", Method, 17}, - {"(*File).SetModTime", Method, 0}, - {"(*File).SetMode", Method, 0}, - {"(*FileHeader).FileInfo", Method, 0}, - {"(*FileHeader).ModTime", Method, 0}, - {"(*FileHeader).Mode", Method, 0}, - {"(*FileHeader).SetModTime", Method, 0}, - {"(*FileHeader).SetMode", Method, 0}, - {"(*ReadCloser).Close", Method, 0}, - {"(*ReadCloser).Open", Method, 16}, - {"(*ReadCloser).RegisterDecompressor", Method, 6}, - {"(*Reader).Open", Method, 16}, - {"(*Reader).RegisterDecompressor", Method, 6}, - {"(*Writer).AddFS", Method, 22}, - {"(*Writer).Close", Method, 0}, - {"(*Writer).Copy", Method, 17}, - {"(*Writer).Create", Method, 0}, - {"(*Writer).CreateHeader", Method, 0}, - {"(*Writer).CreateRaw", Method, 17}, - {"(*Writer).Flush", Method, 4}, - {"(*Writer).RegisterCompressor", Method, 6}, - {"(*Writer).SetComment", Method, 10}, - {"(*Writer).SetOffset", Method, 5}, - {"Compressor", Type, 2}, - {"Decompressor", Type, 2}, - {"Deflate", Const, 0}, - {"ErrAlgorithm", Var, 0}, - {"ErrChecksum", Var, 0}, - {"ErrFormat", Var, 0}, - {"ErrInsecurePath", Var, 20}, - {"File", Type, 0}, - {"File.FileHeader", Field, 0}, - {"FileHeader", Type, 0}, - {"FileHeader.CRC32", Field, 0}, - {"FileHeader.Comment", Field, 0}, - {"FileHeader.CompressedSize", Field, 0}, - {"FileHeader.CompressedSize64", Field, 1}, - {"FileHeader.CreatorVersion", Field, 0}, - {"FileHeader.ExternalAttrs", Field, 0}, - {"FileHeader.Extra", Field, 0}, - {"FileHeader.Flags", Field, 0}, - {"FileHeader.Method", Field, 0}, - {"FileHeader.Modified", Field, 10}, - {"FileHeader.ModifiedDate", Field, 0}, - {"FileHeader.ModifiedTime", Field, 0}, - {"FileHeader.Name", Field, 0}, - {"FileHeader.NonUTF8", Field, 10}, - {"FileHeader.ReaderVersion", Field, 0}, - {"FileHeader.UncompressedSize", Field, 0}, - {"FileHeader.UncompressedSize64", Field, 1}, - {"FileInfoHeader", Func, 0}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"OpenReader", Func, 0}, - {"ReadCloser", Type, 0}, - {"ReadCloser.Reader", Field, 0}, - {"Reader", Type, 0}, - {"Reader.Comment", Field, 0}, - {"Reader.File", Field, 0}, - {"RegisterCompressor", Func, 2}, - {"RegisterDecompressor", Func, 2}, - {"Store", Const, 0}, - {"Writer", Type, 0}, + {"(*File).DataOffset", Method, 2, ""}, + {"(*File).FileInfo", Method, 0, ""}, + {"(*File).ModTime", Method, 0, ""}, + {"(*File).Mode", Method, 0, ""}, + {"(*File).Open", Method, 0, ""}, + {"(*File).OpenRaw", Method, 17, ""}, + {"(*File).SetModTime", Method, 0, ""}, + {"(*File).SetMode", Method, 0, ""}, + {"(*FileHeader).FileInfo", Method, 0, ""}, + {"(*FileHeader).ModTime", Method, 0, ""}, + {"(*FileHeader).Mode", Method, 0, ""}, + {"(*FileHeader).SetModTime", Method, 0, ""}, + {"(*FileHeader).SetMode", Method, 0, ""}, + {"(*ReadCloser).Close", Method, 0, ""}, + {"(*ReadCloser).Open", Method, 16, ""}, + {"(*ReadCloser).RegisterDecompressor", Method, 6, ""}, + {"(*Reader).Open", Method, 16, ""}, + {"(*Reader).RegisterDecompressor", Method, 6, ""}, + {"(*Writer).AddFS", Method, 22, ""}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).Copy", Method, 17, ""}, + {"(*Writer).Create", Method, 0, ""}, + {"(*Writer).CreateHeader", Method, 0, ""}, + {"(*Writer).CreateRaw", Method, 17, ""}, + {"(*Writer).Flush", Method, 4, ""}, + {"(*Writer).RegisterCompressor", Method, 6, ""}, + {"(*Writer).SetComment", Method, 10, ""}, + {"(*Writer).SetOffset", Method, 5, ""}, + {"Compressor", Type, 2, ""}, + {"Decompressor", Type, 2, ""}, + {"Deflate", Const, 0, ""}, + {"ErrAlgorithm", Var, 0, ""}, + {"ErrChecksum", Var, 0, ""}, + {"ErrFormat", Var, 0, ""}, + {"ErrInsecurePath", Var, 20, ""}, + {"File", Type, 0, ""}, + {"File.FileHeader", Field, 0, ""}, + {"FileHeader", Type, 0, ""}, + {"FileHeader.CRC32", Field, 0, ""}, + {"FileHeader.Comment", Field, 0, ""}, + {"FileHeader.CompressedSize", Field, 0, ""}, + {"FileHeader.CompressedSize64", Field, 1, ""}, + {"FileHeader.CreatorVersion", Field, 0, ""}, + {"FileHeader.ExternalAttrs", Field, 0, ""}, + {"FileHeader.Extra", Field, 0, ""}, + {"FileHeader.Flags", Field, 0, ""}, + {"FileHeader.Method", Field, 0, ""}, + {"FileHeader.Modified", Field, 10, ""}, + {"FileHeader.ModifiedDate", Field, 0, ""}, + {"FileHeader.ModifiedTime", Field, 0, ""}, + {"FileHeader.Name", Field, 0, ""}, + {"FileHeader.NonUTF8", Field, 10, ""}, + {"FileHeader.ReaderVersion", Field, 0, ""}, + {"FileHeader.UncompressedSize", Field, 0, ""}, + {"FileHeader.UncompressedSize64", Field, 1, ""}, + {"FileInfoHeader", Func, 0, "func(fi fs.FileInfo) (*FileHeader, error)"}, + {"NewReader", Func, 0, "func(r io.ReaderAt, size int64) (*Reader, error)"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"OpenReader", Func, 0, "func(name string) (*ReadCloser, error)"}, + {"ReadCloser", Type, 0, ""}, + {"ReadCloser.Reader", Field, 0, ""}, + {"Reader", Type, 0, ""}, + {"Reader.Comment", Field, 0, ""}, + {"Reader.File", Field, 0, ""}, + {"RegisterCompressor", Func, 2, "func(method uint16, comp Compressor)"}, + {"RegisterDecompressor", Func, 2, "func(method uint16, dcomp Decompressor)"}, + {"Store", Const, 0, ""}, + {"Writer", Type, 0, ""}, }, "bufio": { - {"(*Reader).Buffered", Method, 0}, - {"(*Reader).Discard", Method, 5}, - {"(*Reader).Peek", Method, 0}, - {"(*Reader).Read", Method, 0}, - {"(*Reader).ReadByte", Method, 0}, - {"(*Reader).ReadBytes", Method, 0}, - {"(*Reader).ReadLine", Method, 0}, - {"(*Reader).ReadRune", Method, 0}, - {"(*Reader).ReadSlice", Method, 0}, - {"(*Reader).ReadString", Method, 0}, - {"(*Reader).Reset", Method, 2}, - {"(*Reader).Size", Method, 10}, - {"(*Reader).UnreadByte", Method, 0}, - {"(*Reader).UnreadRune", Method, 0}, - {"(*Reader).WriteTo", Method, 1}, - {"(*Scanner).Buffer", Method, 6}, - {"(*Scanner).Bytes", Method, 1}, - {"(*Scanner).Err", Method, 1}, - {"(*Scanner).Scan", Method, 1}, - {"(*Scanner).Split", Method, 1}, - {"(*Scanner).Text", Method, 1}, - {"(*Writer).Available", Method, 0}, - {"(*Writer).AvailableBuffer", Method, 18}, - {"(*Writer).Buffered", Method, 0}, - {"(*Writer).Flush", Method, 0}, - {"(*Writer).ReadFrom", Method, 1}, - {"(*Writer).Reset", Method, 2}, - {"(*Writer).Size", Method, 10}, - {"(*Writer).Write", Method, 0}, - {"(*Writer).WriteByte", Method, 0}, - {"(*Writer).WriteRune", Method, 0}, - {"(*Writer).WriteString", Method, 0}, - {"(ReadWriter).Available", Method, 0}, - {"(ReadWriter).AvailableBuffer", Method, 18}, - {"(ReadWriter).Discard", Method, 5}, - {"(ReadWriter).Flush", Method, 0}, - {"(ReadWriter).Peek", Method, 0}, - {"(ReadWriter).Read", Method, 0}, - {"(ReadWriter).ReadByte", Method, 0}, - {"(ReadWriter).ReadBytes", Method, 0}, - {"(ReadWriter).ReadFrom", Method, 1}, - {"(ReadWriter).ReadLine", Method, 0}, - {"(ReadWriter).ReadRune", Method, 0}, - {"(ReadWriter).ReadSlice", Method, 0}, - {"(ReadWriter).ReadString", Method, 0}, - {"(ReadWriter).UnreadByte", Method, 0}, - {"(ReadWriter).UnreadRune", Method, 0}, - {"(ReadWriter).Write", Method, 0}, - {"(ReadWriter).WriteByte", Method, 0}, - {"(ReadWriter).WriteRune", Method, 0}, - {"(ReadWriter).WriteString", Method, 0}, - {"(ReadWriter).WriteTo", Method, 1}, - {"ErrAdvanceTooFar", Var, 1}, - {"ErrBadReadCount", Var, 15}, - {"ErrBufferFull", Var, 0}, - {"ErrFinalToken", Var, 6}, - {"ErrInvalidUnreadByte", Var, 0}, - {"ErrInvalidUnreadRune", Var, 0}, - {"ErrNegativeAdvance", Var, 1}, - {"ErrNegativeCount", Var, 0}, - {"ErrTooLong", Var, 1}, - {"MaxScanTokenSize", Const, 1}, - {"NewReadWriter", Func, 0}, - {"NewReader", Func, 0}, - {"NewReaderSize", Func, 0}, - {"NewScanner", Func, 1}, - {"NewWriter", Func, 0}, - {"NewWriterSize", Func, 0}, - {"ReadWriter", Type, 0}, - {"ReadWriter.Reader", Field, 0}, - {"ReadWriter.Writer", Field, 0}, - {"Reader", Type, 0}, - {"ScanBytes", Func, 1}, - {"ScanLines", Func, 1}, - {"ScanRunes", Func, 1}, - {"ScanWords", Func, 1}, - {"Scanner", Type, 1}, - {"SplitFunc", Type, 1}, - {"Writer", Type, 0}, + {"(*Reader).Buffered", Method, 0, ""}, + {"(*Reader).Discard", Method, 5, ""}, + {"(*Reader).Peek", Method, 0, ""}, + {"(*Reader).Read", Method, 0, ""}, + {"(*Reader).ReadByte", Method, 0, ""}, + {"(*Reader).ReadBytes", Method, 0, ""}, + {"(*Reader).ReadLine", Method, 0, ""}, + {"(*Reader).ReadRune", Method, 0, ""}, + {"(*Reader).ReadSlice", Method, 0, ""}, + {"(*Reader).ReadString", Method, 0, ""}, + {"(*Reader).Reset", Method, 2, ""}, + {"(*Reader).Size", Method, 10, ""}, + {"(*Reader).UnreadByte", Method, 0, ""}, + {"(*Reader).UnreadRune", Method, 0, ""}, + {"(*Reader).WriteTo", Method, 1, ""}, + {"(*Scanner).Buffer", Method, 6, ""}, + {"(*Scanner).Bytes", Method, 1, ""}, + {"(*Scanner).Err", Method, 1, ""}, + {"(*Scanner).Scan", Method, 1, ""}, + {"(*Scanner).Split", Method, 1, ""}, + {"(*Scanner).Text", Method, 1, ""}, + {"(*Writer).Available", Method, 0, ""}, + {"(*Writer).AvailableBuffer", Method, 18, ""}, + {"(*Writer).Buffered", Method, 0, ""}, + {"(*Writer).Flush", Method, 0, ""}, + {"(*Writer).ReadFrom", Method, 1, ""}, + {"(*Writer).Reset", Method, 2, ""}, + {"(*Writer).Size", Method, 10, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"(*Writer).WriteByte", Method, 0, ""}, + {"(*Writer).WriteRune", Method, 0, ""}, + {"(*Writer).WriteString", Method, 0, ""}, + {"(ReadWriter).Available", Method, 0, ""}, + {"(ReadWriter).AvailableBuffer", Method, 18, ""}, + {"(ReadWriter).Discard", Method, 5, ""}, + {"(ReadWriter).Flush", Method, 0, ""}, + {"(ReadWriter).Peek", Method, 0, ""}, + {"(ReadWriter).Read", Method, 0, ""}, + {"(ReadWriter).ReadByte", Method, 0, ""}, + {"(ReadWriter).ReadBytes", Method, 0, ""}, + {"(ReadWriter).ReadFrom", Method, 1, ""}, + {"(ReadWriter).ReadLine", Method, 0, ""}, + {"(ReadWriter).ReadRune", Method, 0, ""}, + {"(ReadWriter).ReadSlice", Method, 0, ""}, + {"(ReadWriter).ReadString", Method, 0, ""}, + {"(ReadWriter).UnreadByte", Method, 0, ""}, + {"(ReadWriter).UnreadRune", Method, 0, ""}, + {"(ReadWriter).Write", Method, 0, ""}, + {"(ReadWriter).WriteByte", Method, 0, ""}, + {"(ReadWriter).WriteRune", Method, 0, ""}, + {"(ReadWriter).WriteString", Method, 0, ""}, + {"(ReadWriter).WriteTo", Method, 1, ""}, + {"ErrAdvanceTooFar", Var, 1, ""}, + {"ErrBadReadCount", Var, 15, ""}, + {"ErrBufferFull", Var, 0, ""}, + {"ErrFinalToken", Var, 6, ""}, + {"ErrInvalidUnreadByte", Var, 0, ""}, + {"ErrInvalidUnreadRune", Var, 0, ""}, + {"ErrNegativeAdvance", Var, 1, ""}, + {"ErrNegativeCount", Var, 0, ""}, + {"ErrTooLong", Var, 1, ""}, + {"MaxScanTokenSize", Const, 1, ""}, + {"NewReadWriter", Func, 0, "func(r *Reader, w *Writer) *ReadWriter"}, + {"NewReader", Func, 0, "func(rd io.Reader) *Reader"}, + {"NewReaderSize", Func, 0, "func(rd io.Reader, size int) *Reader"}, + {"NewScanner", Func, 1, "func(r io.Reader) *Scanner"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"NewWriterSize", Func, 0, "func(w io.Writer, size int) *Writer"}, + {"ReadWriter", Type, 0, ""}, + {"ReadWriter.Reader", Field, 0, ""}, + {"ReadWriter.Writer", Field, 0, ""}, + {"Reader", Type, 0, ""}, + {"ScanBytes", Func, 1, "func(data []byte, atEOF bool) (advance int, token []byte, err error)"}, + {"ScanLines", Func, 1, "func(data []byte, atEOF bool) (advance int, token []byte, err error)"}, + {"ScanRunes", Func, 1, "func(data []byte, atEOF bool) (advance int, token []byte, err error)"}, + {"ScanWords", Func, 1, "func(data []byte, atEOF bool) (advance int, token []byte, err error)"}, + {"Scanner", Type, 1, ""}, + {"SplitFunc", Type, 1, ""}, + {"Writer", Type, 0, ""}, }, "bytes": { - {"(*Buffer).Available", Method, 21}, - {"(*Buffer).AvailableBuffer", Method, 21}, - {"(*Buffer).Bytes", Method, 0}, - {"(*Buffer).Cap", Method, 5}, - {"(*Buffer).Grow", Method, 1}, - {"(*Buffer).Len", Method, 0}, - {"(*Buffer).Next", Method, 0}, - {"(*Buffer).Read", Method, 0}, - {"(*Buffer).ReadByte", Method, 0}, - {"(*Buffer).ReadBytes", Method, 0}, - {"(*Buffer).ReadFrom", Method, 0}, - {"(*Buffer).ReadRune", Method, 0}, - {"(*Buffer).ReadString", Method, 0}, - {"(*Buffer).Reset", Method, 0}, - {"(*Buffer).String", Method, 0}, - {"(*Buffer).Truncate", Method, 0}, - {"(*Buffer).UnreadByte", Method, 0}, - {"(*Buffer).UnreadRune", Method, 0}, - {"(*Buffer).Write", Method, 0}, - {"(*Buffer).WriteByte", Method, 0}, - {"(*Buffer).WriteRune", Method, 0}, - {"(*Buffer).WriteString", Method, 0}, - {"(*Buffer).WriteTo", Method, 0}, - {"(*Reader).Len", Method, 0}, - {"(*Reader).Read", Method, 0}, - {"(*Reader).ReadAt", Method, 0}, - {"(*Reader).ReadByte", Method, 0}, - {"(*Reader).ReadRune", Method, 0}, - {"(*Reader).Reset", Method, 7}, - {"(*Reader).Seek", Method, 0}, - {"(*Reader).Size", Method, 5}, - {"(*Reader).UnreadByte", Method, 0}, - {"(*Reader).UnreadRune", Method, 0}, - {"(*Reader).WriteTo", Method, 1}, - {"Buffer", Type, 0}, - {"Clone", Func, 20}, - {"Compare", Func, 0}, - {"Contains", Func, 0}, - {"ContainsAny", Func, 7}, - {"ContainsFunc", Func, 21}, - {"ContainsRune", Func, 7}, - {"Count", Func, 0}, - {"Cut", Func, 18}, - {"CutPrefix", Func, 20}, - {"CutSuffix", Func, 20}, - {"Equal", Func, 0}, - {"EqualFold", Func, 0}, - {"ErrTooLarge", Var, 0}, - {"Fields", Func, 0}, - {"FieldsFunc", Func, 0}, - {"FieldsFuncSeq", Func, 24}, - {"FieldsSeq", Func, 24}, - {"HasPrefix", Func, 0}, - {"HasSuffix", Func, 0}, - {"Index", Func, 0}, - {"IndexAny", Func, 0}, - {"IndexByte", Func, 0}, - {"IndexFunc", Func, 0}, - {"IndexRune", Func, 0}, - {"Join", Func, 0}, - {"LastIndex", Func, 0}, - {"LastIndexAny", Func, 0}, - {"LastIndexByte", Func, 5}, - {"LastIndexFunc", Func, 0}, - {"Lines", Func, 24}, - {"Map", Func, 0}, - {"MinRead", Const, 0}, - {"NewBuffer", Func, 0}, - {"NewBufferString", Func, 0}, - {"NewReader", Func, 0}, - {"Reader", Type, 0}, - {"Repeat", Func, 0}, - {"Replace", Func, 0}, - {"ReplaceAll", Func, 12}, - {"Runes", Func, 0}, - {"Split", Func, 0}, - {"SplitAfter", Func, 0}, - {"SplitAfterN", Func, 0}, - {"SplitAfterSeq", Func, 24}, - {"SplitN", Func, 0}, - {"SplitSeq", Func, 24}, - {"Title", Func, 0}, - {"ToLower", Func, 0}, - {"ToLowerSpecial", Func, 0}, - {"ToTitle", Func, 0}, - {"ToTitleSpecial", Func, 0}, - {"ToUpper", Func, 0}, - {"ToUpperSpecial", Func, 0}, - {"ToValidUTF8", Func, 13}, - {"Trim", Func, 0}, - {"TrimFunc", Func, 0}, - {"TrimLeft", Func, 0}, - {"TrimLeftFunc", Func, 0}, - {"TrimPrefix", Func, 1}, - {"TrimRight", Func, 0}, - {"TrimRightFunc", Func, 0}, - {"TrimSpace", Func, 0}, - {"TrimSuffix", Func, 1}, + {"(*Buffer).Available", Method, 21, ""}, + {"(*Buffer).AvailableBuffer", Method, 21, ""}, + {"(*Buffer).Bytes", Method, 0, ""}, + {"(*Buffer).Cap", Method, 5, ""}, + {"(*Buffer).Grow", Method, 1, ""}, + {"(*Buffer).Len", Method, 0, ""}, + {"(*Buffer).Next", Method, 0, ""}, + {"(*Buffer).Read", Method, 0, ""}, + {"(*Buffer).ReadByte", Method, 0, ""}, + {"(*Buffer).ReadBytes", Method, 0, ""}, + {"(*Buffer).ReadFrom", Method, 0, ""}, + {"(*Buffer).ReadRune", Method, 0, ""}, + {"(*Buffer).ReadString", Method, 0, ""}, + {"(*Buffer).Reset", Method, 0, ""}, + {"(*Buffer).String", Method, 0, ""}, + {"(*Buffer).Truncate", Method, 0, ""}, + {"(*Buffer).UnreadByte", Method, 0, ""}, + {"(*Buffer).UnreadRune", Method, 0, ""}, + {"(*Buffer).Write", Method, 0, ""}, + {"(*Buffer).WriteByte", Method, 0, ""}, + {"(*Buffer).WriteRune", Method, 0, ""}, + {"(*Buffer).WriteString", Method, 0, ""}, + {"(*Buffer).WriteTo", Method, 0, ""}, + {"(*Reader).Len", Method, 0, ""}, + {"(*Reader).Read", Method, 0, ""}, + {"(*Reader).ReadAt", Method, 0, ""}, + {"(*Reader).ReadByte", Method, 0, ""}, + {"(*Reader).ReadRune", Method, 0, ""}, + {"(*Reader).Reset", Method, 7, ""}, + {"(*Reader).Seek", Method, 0, ""}, + {"(*Reader).Size", Method, 5, ""}, + {"(*Reader).UnreadByte", Method, 0, ""}, + {"(*Reader).UnreadRune", Method, 0, ""}, + {"(*Reader).WriteTo", Method, 1, ""}, + {"Buffer", Type, 0, ""}, + {"Clone", Func, 20, "func(b []byte) []byte"}, + {"Compare", Func, 0, "func(a []byte, b []byte) int"}, + {"Contains", Func, 0, "func(b []byte, subslice []byte) bool"}, + {"ContainsAny", Func, 7, "func(b []byte, chars string) bool"}, + {"ContainsFunc", Func, 21, "func(b []byte, f func(rune) bool) bool"}, + {"ContainsRune", Func, 7, "func(b []byte, r rune) bool"}, + {"Count", Func, 0, "func(s []byte, sep []byte) int"}, + {"Cut", Func, 18, "func(s []byte, sep []byte) (before []byte, after []byte, found bool)"}, + {"CutPrefix", Func, 20, "func(s []byte, prefix []byte) (after []byte, found bool)"}, + {"CutSuffix", Func, 20, "func(s []byte, suffix []byte) (before []byte, found bool)"}, + {"Equal", Func, 0, "func(a []byte, b []byte) bool"}, + {"EqualFold", Func, 0, "func(s []byte, t []byte) bool"}, + {"ErrTooLarge", Var, 0, ""}, + {"Fields", Func, 0, "func(s []byte) [][]byte"}, + {"FieldsFunc", Func, 0, "func(s []byte, f func(rune) bool) [][]byte"}, + {"FieldsFuncSeq", Func, 24, "func(s []byte, f func(rune) bool) iter.Seq[[]byte]"}, + {"FieldsSeq", Func, 24, "func(s []byte) iter.Seq[[]byte]"}, + {"HasPrefix", Func, 0, "func(s []byte, prefix []byte) bool"}, + {"HasSuffix", Func, 0, "func(s []byte, suffix []byte) bool"}, + {"Index", Func, 0, "func(s []byte, sep []byte) int"}, + {"IndexAny", Func, 0, "func(s []byte, chars string) int"}, + {"IndexByte", Func, 0, "func(b []byte, c byte) int"}, + {"IndexFunc", Func, 0, "func(s []byte, f func(r rune) bool) int"}, + {"IndexRune", Func, 0, "func(s []byte, r rune) int"}, + {"Join", Func, 0, "func(s [][]byte, sep []byte) []byte"}, + {"LastIndex", Func, 0, "func(s []byte, sep []byte) int"}, + {"LastIndexAny", Func, 0, "func(s []byte, chars string) int"}, + {"LastIndexByte", Func, 5, "func(s []byte, c byte) int"}, + {"LastIndexFunc", Func, 0, "func(s []byte, f func(r rune) bool) int"}, + {"Lines", Func, 24, "func(s []byte) iter.Seq[[]byte]"}, + {"Map", Func, 0, "func(mapping func(r rune) rune, s []byte) []byte"}, + {"MinRead", Const, 0, ""}, + {"NewBuffer", Func, 0, "func(buf []byte) *Buffer"}, + {"NewBufferString", Func, 0, "func(s string) *Buffer"}, + {"NewReader", Func, 0, "func(b []byte) *Reader"}, + {"Reader", Type, 0, ""}, + {"Repeat", Func, 0, "func(b []byte, count int) []byte"}, + {"Replace", Func, 0, "func(s []byte, old []byte, new []byte, n int) []byte"}, + {"ReplaceAll", Func, 12, "func(s []byte, old []byte, new []byte) []byte"}, + {"Runes", Func, 0, "func(s []byte) []rune"}, + {"Split", Func, 0, "func(s []byte, sep []byte) [][]byte"}, + {"SplitAfter", Func, 0, "func(s []byte, sep []byte) [][]byte"}, + {"SplitAfterN", Func, 0, "func(s []byte, sep []byte, n int) [][]byte"}, + {"SplitAfterSeq", Func, 24, "func(s []byte, sep []byte) iter.Seq[[]byte]"}, + {"SplitN", Func, 0, "func(s []byte, sep []byte, n int) [][]byte"}, + {"SplitSeq", Func, 24, "func(s []byte, sep []byte) iter.Seq[[]byte]"}, + {"Title", Func, 0, "func(s []byte) []byte"}, + {"ToLower", Func, 0, "func(s []byte) []byte"}, + {"ToLowerSpecial", Func, 0, "func(c unicode.SpecialCase, s []byte) []byte"}, + {"ToTitle", Func, 0, "func(s []byte) []byte"}, + {"ToTitleSpecial", Func, 0, "func(c unicode.SpecialCase, s []byte) []byte"}, + {"ToUpper", Func, 0, "func(s []byte) []byte"}, + {"ToUpperSpecial", Func, 0, "func(c unicode.SpecialCase, s []byte) []byte"}, + {"ToValidUTF8", Func, 13, "func(s []byte, replacement []byte) []byte"}, + {"Trim", Func, 0, "func(s []byte, cutset string) []byte"}, + {"TrimFunc", Func, 0, "func(s []byte, f func(r rune) bool) []byte"}, + {"TrimLeft", Func, 0, "func(s []byte, cutset string) []byte"}, + {"TrimLeftFunc", Func, 0, "func(s []byte, f func(r rune) bool) []byte"}, + {"TrimPrefix", Func, 1, "func(s []byte, prefix []byte) []byte"}, + {"TrimRight", Func, 0, "func(s []byte, cutset string) []byte"}, + {"TrimRightFunc", Func, 0, "func(s []byte, f func(r rune) bool) []byte"}, + {"TrimSpace", Func, 0, "func(s []byte) []byte"}, + {"TrimSuffix", Func, 1, "func(s []byte, suffix []byte) []byte"}, }, "cmp": { - {"Compare", Func, 21}, - {"Less", Func, 21}, - {"Or", Func, 22}, - {"Ordered", Type, 21}, + {"Compare", Func, 21, "func[T Ordered](x T, y T) int"}, + {"Less", Func, 21, "func[T Ordered](x T, y T) bool"}, + {"Or", Func, 22, "func[T comparable](vals ...T) T"}, + {"Ordered", Type, 21, ""}, }, "compress/bzip2": { - {"(StructuralError).Error", Method, 0}, - {"NewReader", Func, 0}, - {"StructuralError", Type, 0}, + {"(StructuralError).Error", Method, 0, ""}, + {"NewReader", Func, 0, "func(r io.Reader) io.Reader"}, + {"StructuralError", Type, 0, ""}, }, "compress/flate": { - {"(*ReadError).Error", Method, 0}, - {"(*WriteError).Error", Method, 0}, - {"(*Writer).Close", Method, 0}, - {"(*Writer).Flush", Method, 0}, - {"(*Writer).Reset", Method, 2}, - {"(*Writer).Write", Method, 0}, - {"(CorruptInputError).Error", Method, 0}, - {"(InternalError).Error", Method, 0}, - {"BestCompression", Const, 0}, - {"BestSpeed", Const, 0}, - {"CorruptInputError", Type, 0}, - {"DefaultCompression", Const, 0}, - {"HuffmanOnly", Const, 7}, - {"InternalError", Type, 0}, - {"NewReader", Func, 0}, - {"NewReaderDict", Func, 0}, - {"NewWriter", Func, 0}, - {"NewWriterDict", Func, 0}, - {"NoCompression", Const, 0}, - {"ReadError", Type, 0}, - {"ReadError.Err", Field, 0}, - {"ReadError.Offset", Field, 0}, - {"Reader", Type, 0}, - {"Resetter", Type, 4}, - {"WriteError", Type, 0}, - {"WriteError.Err", Field, 0}, - {"WriteError.Offset", Field, 0}, - {"Writer", Type, 0}, + {"(*ReadError).Error", Method, 0, ""}, + {"(*WriteError).Error", Method, 0, ""}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).Flush", Method, 0, ""}, + {"(*Writer).Reset", Method, 2, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"(CorruptInputError).Error", Method, 0, ""}, + {"(InternalError).Error", Method, 0, ""}, + {"BestCompression", Const, 0, ""}, + {"BestSpeed", Const, 0, ""}, + {"CorruptInputError", Type, 0, ""}, + {"DefaultCompression", Const, 0, ""}, + {"HuffmanOnly", Const, 7, ""}, + {"InternalError", Type, 0, ""}, + {"NewReader", Func, 0, "func(r io.Reader) io.ReadCloser"}, + {"NewReaderDict", Func, 0, "func(r io.Reader, dict []byte) io.ReadCloser"}, + {"NewWriter", Func, 0, "func(w io.Writer, level int) (*Writer, error)"}, + {"NewWriterDict", Func, 0, "func(w io.Writer, level int, dict []byte) (*Writer, error)"}, + {"NoCompression", Const, 0, ""}, + {"ReadError", Type, 0, ""}, + {"ReadError.Err", Field, 0, ""}, + {"ReadError.Offset", Field, 0, ""}, + {"Reader", Type, 0, ""}, + {"Resetter", Type, 4, ""}, + {"WriteError", Type, 0, ""}, + {"WriteError.Err", Field, 0, ""}, + {"WriteError.Offset", Field, 0, ""}, + {"Writer", Type, 0, ""}, }, "compress/gzip": { - {"(*Reader).Close", Method, 0}, - {"(*Reader).Multistream", Method, 4}, - {"(*Reader).Read", Method, 0}, - {"(*Reader).Reset", Method, 3}, - {"(*Writer).Close", Method, 0}, - {"(*Writer).Flush", Method, 1}, - {"(*Writer).Reset", Method, 2}, - {"(*Writer).Write", Method, 0}, - {"BestCompression", Const, 0}, - {"BestSpeed", Const, 0}, - {"DefaultCompression", Const, 0}, - {"ErrChecksum", Var, 0}, - {"ErrHeader", Var, 0}, - {"Header", Type, 0}, - {"Header.Comment", Field, 0}, - {"Header.Extra", Field, 0}, - {"Header.ModTime", Field, 0}, - {"Header.Name", Field, 0}, - {"Header.OS", Field, 0}, - {"HuffmanOnly", Const, 8}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"NewWriterLevel", Func, 0}, - {"NoCompression", Const, 0}, - {"Reader", Type, 0}, - {"Reader.Header", Field, 0}, - {"Writer", Type, 0}, - {"Writer.Header", Field, 0}, + {"(*Reader).Close", Method, 0, ""}, + {"(*Reader).Multistream", Method, 4, ""}, + {"(*Reader).Read", Method, 0, ""}, + {"(*Reader).Reset", Method, 3, ""}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).Flush", Method, 1, ""}, + {"(*Writer).Reset", Method, 2, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"BestCompression", Const, 0, ""}, + {"BestSpeed", Const, 0, ""}, + {"DefaultCompression", Const, 0, ""}, + {"ErrChecksum", Var, 0, ""}, + {"ErrHeader", Var, 0, ""}, + {"Header", Type, 0, ""}, + {"Header.Comment", Field, 0, ""}, + {"Header.Extra", Field, 0, ""}, + {"Header.ModTime", Field, 0, ""}, + {"Header.Name", Field, 0, ""}, + {"Header.OS", Field, 0, ""}, + {"HuffmanOnly", Const, 8, ""}, + {"NewReader", Func, 0, "func(r io.Reader) (*Reader, error)"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"NewWriterLevel", Func, 0, "func(w io.Writer, level int) (*Writer, error)"}, + {"NoCompression", Const, 0, ""}, + {"Reader", Type, 0, ""}, + {"Reader.Header", Field, 0, ""}, + {"Writer", Type, 0, ""}, + {"Writer.Header", Field, 0, ""}, }, "compress/lzw": { - {"(*Reader).Close", Method, 17}, - {"(*Reader).Read", Method, 17}, - {"(*Reader).Reset", Method, 17}, - {"(*Writer).Close", Method, 17}, - {"(*Writer).Reset", Method, 17}, - {"(*Writer).Write", Method, 17}, - {"LSB", Const, 0}, - {"MSB", Const, 0}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"Order", Type, 0}, - {"Reader", Type, 17}, - {"Writer", Type, 17}, + {"(*Reader).Close", Method, 17, ""}, + {"(*Reader).Read", Method, 17, ""}, + {"(*Reader).Reset", Method, 17, ""}, + {"(*Writer).Close", Method, 17, ""}, + {"(*Writer).Reset", Method, 17, ""}, + {"(*Writer).Write", Method, 17, ""}, + {"LSB", Const, 0, ""}, + {"MSB", Const, 0, ""}, + {"NewReader", Func, 0, "func(r io.Reader, order Order, litWidth int) io.ReadCloser"}, + {"NewWriter", Func, 0, "func(w io.Writer, order Order, litWidth int) io.WriteCloser"}, + {"Order", Type, 0, ""}, + {"Reader", Type, 17, ""}, + {"Writer", Type, 17, ""}, }, "compress/zlib": { - {"(*Writer).Close", Method, 0}, - {"(*Writer).Flush", Method, 0}, - {"(*Writer).Reset", Method, 2}, - {"(*Writer).Write", Method, 0}, - {"BestCompression", Const, 0}, - {"BestSpeed", Const, 0}, - {"DefaultCompression", Const, 0}, - {"ErrChecksum", Var, 0}, - {"ErrDictionary", Var, 0}, - {"ErrHeader", Var, 0}, - {"HuffmanOnly", Const, 8}, - {"NewReader", Func, 0}, - {"NewReaderDict", Func, 0}, - {"NewWriter", Func, 0}, - {"NewWriterLevel", Func, 0}, - {"NewWriterLevelDict", Func, 0}, - {"NoCompression", Const, 0}, - {"Resetter", Type, 4}, - {"Writer", Type, 0}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).Flush", Method, 0, ""}, + {"(*Writer).Reset", Method, 2, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"BestCompression", Const, 0, ""}, + {"BestSpeed", Const, 0, ""}, + {"DefaultCompression", Const, 0, ""}, + {"ErrChecksum", Var, 0, ""}, + {"ErrDictionary", Var, 0, ""}, + {"ErrHeader", Var, 0, ""}, + {"HuffmanOnly", Const, 8, ""}, + {"NewReader", Func, 0, "func(r io.Reader) (io.ReadCloser, error)"}, + {"NewReaderDict", Func, 0, "func(r io.Reader, dict []byte) (io.ReadCloser, error)"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"NewWriterLevel", Func, 0, "func(w io.Writer, level int) (*Writer, error)"}, + {"NewWriterLevelDict", Func, 0, "func(w io.Writer, level int, dict []byte) (*Writer, error)"}, + {"NoCompression", Const, 0, ""}, + {"Resetter", Type, 4, ""}, + {"Writer", Type, 0, ""}, }, "container/heap": { - {"Fix", Func, 2}, - {"Init", Func, 0}, - {"Interface", Type, 0}, - {"Pop", Func, 0}, - {"Push", Func, 0}, - {"Remove", Func, 0}, + {"Fix", Func, 2, "func(h Interface, i int)"}, + {"Init", Func, 0, "func(h Interface)"}, + {"Interface", Type, 0, ""}, + {"Pop", Func, 0, "func(h Interface) any"}, + {"Push", Func, 0, "func(h Interface, x any)"}, + {"Remove", Func, 0, "func(h Interface, i int) any"}, }, "container/list": { - {"(*Element).Next", Method, 0}, - {"(*Element).Prev", Method, 0}, - {"(*List).Back", Method, 0}, - {"(*List).Front", Method, 0}, - {"(*List).Init", Method, 0}, - {"(*List).InsertAfter", Method, 0}, - {"(*List).InsertBefore", Method, 0}, - {"(*List).Len", Method, 0}, - {"(*List).MoveAfter", Method, 2}, - {"(*List).MoveBefore", Method, 2}, - {"(*List).MoveToBack", Method, 0}, - {"(*List).MoveToFront", Method, 0}, - {"(*List).PushBack", Method, 0}, - {"(*List).PushBackList", Method, 0}, - {"(*List).PushFront", Method, 0}, - {"(*List).PushFrontList", Method, 0}, - {"(*List).Remove", Method, 0}, - {"Element", Type, 0}, - {"Element.Value", Field, 0}, - {"List", Type, 0}, - {"New", Func, 0}, + {"(*Element).Next", Method, 0, ""}, + {"(*Element).Prev", Method, 0, ""}, + {"(*List).Back", Method, 0, ""}, + {"(*List).Front", Method, 0, ""}, + {"(*List).Init", Method, 0, ""}, + {"(*List).InsertAfter", Method, 0, ""}, + {"(*List).InsertBefore", Method, 0, ""}, + {"(*List).Len", Method, 0, ""}, + {"(*List).MoveAfter", Method, 2, ""}, + {"(*List).MoveBefore", Method, 2, ""}, + {"(*List).MoveToBack", Method, 0, ""}, + {"(*List).MoveToFront", Method, 0, ""}, + {"(*List).PushBack", Method, 0, ""}, + {"(*List).PushBackList", Method, 0, ""}, + {"(*List).PushFront", Method, 0, ""}, + {"(*List).PushFrontList", Method, 0, ""}, + {"(*List).Remove", Method, 0, ""}, + {"Element", Type, 0, ""}, + {"Element.Value", Field, 0, ""}, + {"List", Type, 0, ""}, + {"New", Func, 0, "func() *List"}, }, "container/ring": { - {"(*Ring).Do", Method, 0}, - {"(*Ring).Len", Method, 0}, - {"(*Ring).Link", Method, 0}, - {"(*Ring).Move", Method, 0}, - {"(*Ring).Next", Method, 0}, - {"(*Ring).Prev", Method, 0}, - {"(*Ring).Unlink", Method, 0}, - {"New", Func, 0}, - {"Ring", Type, 0}, - {"Ring.Value", Field, 0}, + {"(*Ring).Do", Method, 0, ""}, + {"(*Ring).Len", Method, 0, ""}, + {"(*Ring).Link", Method, 0, ""}, + {"(*Ring).Move", Method, 0, ""}, + {"(*Ring).Next", Method, 0, ""}, + {"(*Ring).Prev", Method, 0, ""}, + {"(*Ring).Unlink", Method, 0, ""}, + {"New", Func, 0, "func(n int) *Ring"}, + {"Ring", Type, 0, ""}, + {"Ring.Value", Field, 0, ""}, }, "context": { - {"AfterFunc", Func, 21}, - {"Background", Func, 7}, - {"CancelCauseFunc", Type, 20}, - {"CancelFunc", Type, 7}, - {"Canceled", Var, 7}, - {"Cause", Func, 20}, - {"Context", Type, 7}, - {"DeadlineExceeded", Var, 7}, - {"TODO", Func, 7}, - {"WithCancel", Func, 7}, - {"WithCancelCause", Func, 20}, - {"WithDeadline", Func, 7}, - {"WithDeadlineCause", Func, 21}, - {"WithTimeout", Func, 7}, - {"WithTimeoutCause", Func, 21}, - {"WithValue", Func, 7}, - {"WithoutCancel", Func, 21}, + {"AfterFunc", Func, 21, "func(ctx Context, f func()) (stop func() bool)"}, + {"Background", Func, 7, "func() Context"}, + {"CancelCauseFunc", Type, 20, ""}, + {"CancelFunc", Type, 7, ""}, + {"Canceled", Var, 7, ""}, + {"Cause", Func, 20, "func(c Context) error"}, + {"Context", Type, 7, ""}, + {"DeadlineExceeded", Var, 7, ""}, + {"TODO", Func, 7, "func() Context"}, + {"WithCancel", Func, 7, "func(parent Context) (ctx Context, cancel CancelFunc)"}, + {"WithCancelCause", Func, 20, "func(parent Context) (ctx Context, cancel CancelCauseFunc)"}, + {"WithDeadline", Func, 7, "func(parent Context, d time.Time) (Context, CancelFunc)"}, + {"WithDeadlineCause", Func, 21, "func(parent Context, d time.Time, cause error) (Context, CancelFunc)"}, + {"WithTimeout", Func, 7, "func(parent Context, timeout time.Duration) (Context, CancelFunc)"}, + {"WithTimeoutCause", Func, 21, "func(parent Context, timeout time.Duration, cause error) (Context, CancelFunc)"}, + {"WithValue", Func, 7, "func(parent Context, key any, val any) Context"}, + {"WithoutCancel", Func, 21, "func(parent Context) Context"}, }, "crypto": { - {"(Hash).Available", Method, 0}, - {"(Hash).HashFunc", Method, 4}, - {"(Hash).New", Method, 0}, - {"(Hash).Size", Method, 0}, - {"(Hash).String", Method, 15}, - {"BLAKE2b_256", Const, 9}, - {"BLAKE2b_384", Const, 9}, - {"BLAKE2b_512", Const, 9}, - {"BLAKE2s_256", Const, 9}, - {"Decrypter", Type, 5}, - {"DecrypterOpts", Type, 5}, - {"Hash", Type, 0}, - {"MD4", Const, 0}, - {"MD5", Const, 0}, - {"MD5SHA1", Const, 0}, - {"PrivateKey", Type, 0}, - {"PublicKey", Type, 2}, - {"RIPEMD160", Const, 0}, - {"RegisterHash", Func, 0}, - {"SHA1", Const, 0}, - {"SHA224", Const, 0}, - {"SHA256", Const, 0}, - {"SHA384", Const, 0}, - {"SHA3_224", Const, 4}, - {"SHA3_256", Const, 4}, - {"SHA3_384", Const, 4}, - {"SHA3_512", Const, 4}, - {"SHA512", Const, 0}, - {"SHA512_224", Const, 5}, - {"SHA512_256", Const, 5}, - {"Signer", Type, 4}, - {"SignerOpts", Type, 4}, + {"(Hash).Available", Method, 0, ""}, + {"(Hash).HashFunc", Method, 4, ""}, + {"(Hash).New", Method, 0, ""}, + {"(Hash).Size", Method, 0, ""}, + {"(Hash).String", Method, 15, ""}, + {"BLAKE2b_256", Const, 9, ""}, + {"BLAKE2b_384", Const, 9, ""}, + {"BLAKE2b_512", Const, 9, ""}, + {"BLAKE2s_256", Const, 9, ""}, + {"Decrypter", Type, 5, ""}, + {"DecrypterOpts", Type, 5, ""}, + {"Hash", Type, 0, ""}, + {"MD4", Const, 0, ""}, + {"MD5", Const, 0, ""}, + {"MD5SHA1", Const, 0, ""}, + {"PrivateKey", Type, 0, ""}, + {"PublicKey", Type, 2, ""}, + {"RIPEMD160", Const, 0, ""}, + {"RegisterHash", Func, 0, "func(h Hash, f func() hash.Hash)"}, + {"SHA1", Const, 0, ""}, + {"SHA224", Const, 0, ""}, + {"SHA256", Const, 0, ""}, + {"SHA384", Const, 0, ""}, + {"SHA3_224", Const, 4, ""}, + {"SHA3_256", Const, 4, ""}, + {"SHA3_384", Const, 4, ""}, + {"SHA3_512", Const, 4, ""}, + {"SHA512", Const, 0, ""}, + {"SHA512_224", Const, 5, ""}, + {"SHA512_256", Const, 5, ""}, + {"Signer", Type, 4, ""}, + {"SignerOpts", Type, 4, ""}, }, "crypto/aes": { - {"(KeySizeError).Error", Method, 0}, - {"BlockSize", Const, 0}, - {"KeySizeError", Type, 0}, - {"NewCipher", Func, 0}, + {"(KeySizeError).Error", Method, 0, ""}, + {"BlockSize", Const, 0, ""}, + {"KeySizeError", Type, 0, ""}, + {"NewCipher", Func, 0, "func(key []byte) (cipher.Block, error)"}, }, "crypto/cipher": { - {"(StreamReader).Read", Method, 0}, - {"(StreamWriter).Close", Method, 0}, - {"(StreamWriter).Write", Method, 0}, - {"AEAD", Type, 2}, - {"Block", Type, 0}, - {"BlockMode", Type, 0}, - {"NewCBCDecrypter", Func, 0}, - {"NewCBCEncrypter", Func, 0}, - {"NewCFBDecrypter", Func, 0}, - {"NewCFBEncrypter", Func, 0}, - {"NewCTR", Func, 0}, - {"NewGCM", Func, 2}, - {"NewGCMWithNonceSize", Func, 5}, - {"NewGCMWithRandomNonce", Func, 24}, - {"NewGCMWithTagSize", Func, 11}, - {"NewOFB", Func, 0}, - {"Stream", Type, 0}, - {"StreamReader", Type, 0}, - {"StreamReader.R", Field, 0}, - {"StreamReader.S", Field, 0}, - {"StreamWriter", Type, 0}, - {"StreamWriter.Err", Field, 0}, - {"StreamWriter.S", Field, 0}, - {"StreamWriter.W", Field, 0}, + {"(StreamReader).Read", Method, 0, ""}, + {"(StreamWriter).Close", Method, 0, ""}, + {"(StreamWriter).Write", Method, 0, ""}, + {"AEAD", Type, 2, ""}, + {"Block", Type, 0, ""}, + {"BlockMode", Type, 0, ""}, + {"NewCBCDecrypter", Func, 0, "func(b Block, iv []byte) BlockMode"}, + {"NewCBCEncrypter", Func, 0, "func(b Block, iv []byte) BlockMode"}, + {"NewCFBDecrypter", Func, 0, "func(block Block, iv []byte) Stream"}, + {"NewCFBEncrypter", Func, 0, "func(block Block, iv []byte) Stream"}, + {"NewCTR", Func, 0, "func(block Block, iv []byte) Stream"}, + {"NewGCM", Func, 2, "func(cipher Block) (AEAD, error)"}, + {"NewGCMWithNonceSize", Func, 5, "func(cipher Block, size int) (AEAD, error)"}, + {"NewGCMWithRandomNonce", Func, 24, "func(cipher Block) (AEAD, error)"}, + {"NewGCMWithTagSize", Func, 11, "func(cipher Block, tagSize int) (AEAD, error)"}, + {"NewOFB", Func, 0, "func(b Block, iv []byte) Stream"}, + {"Stream", Type, 0, ""}, + {"StreamReader", Type, 0, ""}, + {"StreamReader.R", Field, 0, ""}, + {"StreamReader.S", Field, 0, ""}, + {"StreamWriter", Type, 0, ""}, + {"StreamWriter.Err", Field, 0, ""}, + {"StreamWriter.S", Field, 0, ""}, + {"StreamWriter.W", Field, 0, ""}, }, "crypto/des": { - {"(KeySizeError).Error", Method, 0}, - {"BlockSize", Const, 0}, - {"KeySizeError", Type, 0}, - {"NewCipher", Func, 0}, - {"NewTripleDESCipher", Func, 0}, + {"(KeySizeError).Error", Method, 0, ""}, + {"BlockSize", Const, 0, ""}, + {"KeySizeError", Type, 0, ""}, + {"NewCipher", Func, 0, "func(key []byte) (cipher.Block, error)"}, + {"NewTripleDESCipher", Func, 0, "func(key []byte) (cipher.Block, error)"}, }, "crypto/dsa": { - {"ErrInvalidPublicKey", Var, 0}, - {"GenerateKey", Func, 0}, - {"GenerateParameters", Func, 0}, - {"L1024N160", Const, 0}, - {"L2048N224", Const, 0}, - {"L2048N256", Const, 0}, - {"L3072N256", Const, 0}, - {"ParameterSizes", Type, 0}, - {"Parameters", Type, 0}, - {"Parameters.G", Field, 0}, - {"Parameters.P", Field, 0}, - {"Parameters.Q", Field, 0}, - {"PrivateKey", Type, 0}, - {"PrivateKey.PublicKey", Field, 0}, - {"PrivateKey.X", Field, 0}, - {"PublicKey", Type, 0}, - {"PublicKey.Parameters", Field, 0}, - {"PublicKey.Y", Field, 0}, - {"Sign", Func, 0}, - {"Verify", Func, 0}, + {"ErrInvalidPublicKey", Var, 0, ""}, + {"GenerateKey", Func, 0, "func(priv *PrivateKey, rand io.Reader) error"}, + {"GenerateParameters", Func, 0, "func(params *Parameters, rand io.Reader, sizes ParameterSizes) error"}, + {"L1024N160", Const, 0, ""}, + {"L2048N224", Const, 0, ""}, + {"L2048N256", Const, 0, ""}, + {"L3072N256", Const, 0, ""}, + {"ParameterSizes", Type, 0, ""}, + {"Parameters", Type, 0, ""}, + {"Parameters.G", Field, 0, ""}, + {"Parameters.P", Field, 0, ""}, + {"Parameters.Q", Field, 0, ""}, + {"PrivateKey", Type, 0, ""}, + {"PrivateKey.PublicKey", Field, 0, ""}, + {"PrivateKey.X", Field, 0, ""}, + {"PublicKey", Type, 0, ""}, + {"PublicKey.Parameters", Field, 0, ""}, + {"PublicKey.Y", Field, 0, ""}, + {"Sign", Func, 0, "func(rand io.Reader, priv *PrivateKey, hash []byte) (r *big.Int, s *big.Int, err error)"}, + {"Verify", Func, 0, "func(pub *PublicKey, hash []byte, r *big.Int, s *big.Int) bool"}, }, "crypto/ecdh": { - {"(*PrivateKey).Bytes", Method, 20}, - {"(*PrivateKey).Curve", Method, 20}, - {"(*PrivateKey).ECDH", Method, 20}, - {"(*PrivateKey).Equal", Method, 20}, - {"(*PrivateKey).Public", Method, 20}, - {"(*PrivateKey).PublicKey", Method, 20}, - {"(*PublicKey).Bytes", Method, 20}, - {"(*PublicKey).Curve", Method, 20}, - {"(*PublicKey).Equal", Method, 20}, - {"Curve", Type, 20}, - {"P256", Func, 20}, - {"P384", Func, 20}, - {"P521", Func, 20}, - {"PrivateKey", Type, 20}, - {"PublicKey", Type, 20}, - {"X25519", Func, 20}, + {"(*PrivateKey).Bytes", Method, 20, ""}, + {"(*PrivateKey).Curve", Method, 20, ""}, + {"(*PrivateKey).ECDH", Method, 20, ""}, + {"(*PrivateKey).Equal", Method, 20, ""}, + {"(*PrivateKey).Public", Method, 20, ""}, + {"(*PrivateKey).PublicKey", Method, 20, ""}, + {"(*PublicKey).Bytes", Method, 20, ""}, + {"(*PublicKey).Curve", Method, 20, ""}, + {"(*PublicKey).Equal", Method, 20, ""}, + {"Curve", Type, 20, ""}, + {"P256", Func, 20, "func() Curve"}, + {"P384", Func, 20, "func() Curve"}, + {"P521", Func, 20, "func() Curve"}, + {"PrivateKey", Type, 20, ""}, + {"PublicKey", Type, 20, ""}, + {"X25519", Func, 20, "func() Curve"}, }, "crypto/ecdsa": { - {"(*PrivateKey).ECDH", Method, 20}, - {"(*PrivateKey).Equal", Method, 15}, - {"(*PrivateKey).Public", Method, 4}, - {"(*PrivateKey).Sign", Method, 4}, - {"(*PublicKey).ECDH", Method, 20}, - {"(*PublicKey).Equal", Method, 15}, - {"(PrivateKey).Add", Method, 0}, - {"(PrivateKey).Double", Method, 0}, - {"(PrivateKey).IsOnCurve", Method, 0}, - {"(PrivateKey).Params", Method, 0}, - {"(PrivateKey).ScalarBaseMult", Method, 0}, - {"(PrivateKey).ScalarMult", Method, 0}, - {"(PublicKey).Add", Method, 0}, - {"(PublicKey).Double", Method, 0}, - {"(PublicKey).IsOnCurve", Method, 0}, - {"(PublicKey).Params", Method, 0}, - {"(PublicKey).ScalarBaseMult", Method, 0}, - {"(PublicKey).ScalarMult", Method, 0}, - {"GenerateKey", Func, 0}, - {"PrivateKey", Type, 0}, - {"PrivateKey.D", Field, 0}, - {"PrivateKey.PublicKey", Field, 0}, - {"PublicKey", Type, 0}, - {"PublicKey.Curve", Field, 0}, - {"PublicKey.X", Field, 0}, - {"PublicKey.Y", Field, 0}, - {"Sign", Func, 0}, - {"SignASN1", Func, 15}, - {"Verify", Func, 0}, - {"VerifyASN1", Func, 15}, + {"(*PrivateKey).ECDH", Method, 20, ""}, + {"(*PrivateKey).Equal", Method, 15, ""}, + {"(*PrivateKey).Public", Method, 4, ""}, + {"(*PrivateKey).Sign", Method, 4, ""}, + {"(*PublicKey).ECDH", Method, 20, ""}, + {"(*PublicKey).Equal", Method, 15, ""}, + {"(PrivateKey).Add", Method, 0, ""}, + {"(PrivateKey).Double", Method, 0, ""}, + {"(PrivateKey).IsOnCurve", Method, 0, ""}, + {"(PrivateKey).Params", Method, 0, ""}, + {"(PrivateKey).ScalarBaseMult", Method, 0, ""}, + {"(PrivateKey).ScalarMult", Method, 0, ""}, + {"(PublicKey).Add", Method, 0, ""}, + {"(PublicKey).Double", Method, 0, ""}, + {"(PublicKey).IsOnCurve", Method, 0, ""}, + {"(PublicKey).Params", Method, 0, ""}, + {"(PublicKey).ScalarBaseMult", Method, 0, ""}, + {"(PublicKey).ScalarMult", Method, 0, ""}, + {"GenerateKey", Func, 0, "func(c elliptic.Curve, rand io.Reader) (*PrivateKey, error)"}, + {"PrivateKey", Type, 0, ""}, + {"PrivateKey.D", Field, 0, ""}, + {"PrivateKey.PublicKey", Field, 0, ""}, + {"PublicKey", Type, 0, ""}, + {"PublicKey.Curve", Field, 0, ""}, + {"PublicKey.X", Field, 0, ""}, + {"PublicKey.Y", Field, 0, ""}, + {"Sign", Func, 0, "func(rand io.Reader, priv *PrivateKey, hash []byte) (r *big.Int, s *big.Int, err error)"}, + {"SignASN1", Func, 15, "func(rand io.Reader, priv *PrivateKey, hash []byte) ([]byte, error)"}, + {"Verify", Func, 0, "func(pub *PublicKey, hash []byte, r *big.Int, s *big.Int) bool"}, + {"VerifyASN1", Func, 15, "func(pub *PublicKey, hash []byte, sig []byte) bool"}, }, "crypto/ed25519": { - {"(*Options).HashFunc", Method, 20}, - {"(PrivateKey).Equal", Method, 15}, - {"(PrivateKey).Public", Method, 13}, - {"(PrivateKey).Seed", Method, 13}, - {"(PrivateKey).Sign", Method, 13}, - {"(PublicKey).Equal", Method, 15}, - {"GenerateKey", Func, 13}, - {"NewKeyFromSeed", Func, 13}, - {"Options", Type, 20}, - {"Options.Context", Field, 20}, - {"Options.Hash", Field, 20}, - {"PrivateKey", Type, 13}, - {"PrivateKeySize", Const, 13}, - {"PublicKey", Type, 13}, - {"PublicKeySize", Const, 13}, - {"SeedSize", Const, 13}, - {"Sign", Func, 13}, - {"SignatureSize", Const, 13}, - {"Verify", Func, 13}, - {"VerifyWithOptions", Func, 20}, + {"(*Options).HashFunc", Method, 20, ""}, + {"(PrivateKey).Equal", Method, 15, ""}, + {"(PrivateKey).Public", Method, 13, ""}, + {"(PrivateKey).Seed", Method, 13, ""}, + {"(PrivateKey).Sign", Method, 13, ""}, + {"(PublicKey).Equal", Method, 15, ""}, + {"GenerateKey", Func, 13, "func(rand io.Reader) (PublicKey, PrivateKey, error)"}, + {"NewKeyFromSeed", Func, 13, "func(seed []byte) PrivateKey"}, + {"Options", Type, 20, ""}, + {"Options.Context", Field, 20, ""}, + {"Options.Hash", Field, 20, ""}, + {"PrivateKey", Type, 13, ""}, + {"PrivateKeySize", Const, 13, ""}, + {"PublicKey", Type, 13, ""}, + {"PublicKeySize", Const, 13, ""}, + {"SeedSize", Const, 13, ""}, + {"Sign", Func, 13, "func(privateKey PrivateKey, message []byte) []byte"}, + {"SignatureSize", Const, 13, ""}, + {"Verify", Func, 13, "func(publicKey PublicKey, message []byte, sig []byte) bool"}, + {"VerifyWithOptions", Func, 20, "func(publicKey PublicKey, message []byte, sig []byte, opts *Options) error"}, }, "crypto/elliptic": { - {"(*CurveParams).Add", Method, 0}, - {"(*CurveParams).Double", Method, 0}, - {"(*CurveParams).IsOnCurve", Method, 0}, - {"(*CurveParams).Params", Method, 0}, - {"(*CurveParams).ScalarBaseMult", Method, 0}, - {"(*CurveParams).ScalarMult", Method, 0}, - {"Curve", Type, 0}, - {"CurveParams", Type, 0}, - {"CurveParams.B", Field, 0}, - {"CurveParams.BitSize", Field, 0}, - {"CurveParams.Gx", Field, 0}, - {"CurveParams.Gy", Field, 0}, - {"CurveParams.N", Field, 0}, - {"CurveParams.Name", Field, 5}, - {"CurveParams.P", Field, 0}, - {"GenerateKey", Func, 0}, - {"Marshal", Func, 0}, - {"MarshalCompressed", Func, 15}, - {"P224", Func, 0}, - {"P256", Func, 0}, - {"P384", Func, 0}, - {"P521", Func, 0}, - {"Unmarshal", Func, 0}, - {"UnmarshalCompressed", Func, 15}, + {"(*CurveParams).Add", Method, 0, ""}, + {"(*CurveParams).Double", Method, 0, ""}, + {"(*CurveParams).IsOnCurve", Method, 0, ""}, + {"(*CurveParams).Params", Method, 0, ""}, + {"(*CurveParams).ScalarBaseMult", Method, 0, ""}, + {"(*CurveParams).ScalarMult", Method, 0, ""}, + {"Curve", Type, 0, ""}, + {"CurveParams", Type, 0, ""}, + {"CurveParams.B", Field, 0, ""}, + {"CurveParams.BitSize", Field, 0, ""}, + {"CurveParams.Gx", Field, 0, ""}, + {"CurveParams.Gy", Field, 0, ""}, + {"CurveParams.N", Field, 0, ""}, + {"CurveParams.Name", Field, 5, ""}, + {"CurveParams.P", Field, 0, ""}, + {"GenerateKey", Func, 0, "func(curve Curve, rand io.Reader) (priv []byte, x *big.Int, y *big.Int, err error)"}, + {"Marshal", Func, 0, "func(curve Curve, x *big.Int, y *big.Int) []byte"}, + {"MarshalCompressed", Func, 15, "func(curve Curve, x *big.Int, y *big.Int) []byte"}, + {"P224", Func, 0, "func() Curve"}, + {"P256", Func, 0, "func() Curve"}, + {"P384", Func, 0, "func() Curve"}, + {"P521", Func, 0, "func() Curve"}, + {"Unmarshal", Func, 0, "func(curve Curve, data []byte) (x *big.Int, y *big.Int)"}, + {"UnmarshalCompressed", Func, 15, "func(curve Curve, data []byte) (x *big.Int, y *big.Int)"}, }, "crypto/fips140": { - {"Enabled", Func, 24}, + {"Enabled", Func, 24, "func() bool"}, }, "crypto/hkdf": { - {"Expand", Func, 24}, - {"Extract", Func, 24}, - {"Key", Func, 24}, + {"Expand", Func, 24, "func[H hash.Hash](h func() H, pseudorandomKey []byte, info string, keyLength int) ([]byte, error)"}, + {"Extract", Func, 24, "func[H hash.Hash](h func() H, secret []byte, salt []byte) ([]byte, error)"}, + {"Key", Func, 24, "func[Hash hash.Hash](h func() Hash, secret []byte, salt []byte, info string, keyLength int) ([]byte, error)"}, }, "crypto/hmac": { - {"Equal", Func, 1}, - {"New", Func, 0}, + {"Equal", Func, 1, "func(mac1 []byte, mac2 []byte) bool"}, + {"New", Func, 0, "func(h func() hash.Hash, key []byte) hash.Hash"}, }, "crypto/md5": { - {"BlockSize", Const, 0}, - {"New", Func, 0}, - {"Size", Const, 0}, - {"Sum", Func, 2}, + {"BlockSize", Const, 0, ""}, + {"New", Func, 0, "func() hash.Hash"}, + {"Size", Const, 0, ""}, + {"Sum", Func, 2, "func(data []byte) [16]byte"}, }, "crypto/mlkem": { - {"(*DecapsulationKey1024).Bytes", Method, 24}, - {"(*DecapsulationKey1024).Decapsulate", Method, 24}, - {"(*DecapsulationKey1024).EncapsulationKey", Method, 24}, - {"(*DecapsulationKey768).Bytes", Method, 24}, - {"(*DecapsulationKey768).Decapsulate", Method, 24}, - {"(*DecapsulationKey768).EncapsulationKey", Method, 24}, - {"(*EncapsulationKey1024).Bytes", Method, 24}, - {"(*EncapsulationKey1024).Encapsulate", Method, 24}, - {"(*EncapsulationKey768).Bytes", Method, 24}, - {"(*EncapsulationKey768).Encapsulate", Method, 24}, - {"CiphertextSize1024", Const, 24}, - {"CiphertextSize768", Const, 24}, - {"DecapsulationKey1024", Type, 24}, - {"DecapsulationKey768", Type, 24}, - {"EncapsulationKey1024", Type, 24}, - {"EncapsulationKey768", Type, 24}, - {"EncapsulationKeySize1024", Const, 24}, - {"EncapsulationKeySize768", Const, 24}, - {"GenerateKey1024", Func, 24}, - {"GenerateKey768", Func, 24}, - {"NewDecapsulationKey1024", Func, 24}, - {"NewDecapsulationKey768", Func, 24}, - {"NewEncapsulationKey1024", Func, 24}, - {"NewEncapsulationKey768", Func, 24}, - {"SeedSize", Const, 24}, - {"SharedKeySize", Const, 24}, + {"(*DecapsulationKey1024).Bytes", Method, 24, ""}, + {"(*DecapsulationKey1024).Decapsulate", Method, 24, ""}, + {"(*DecapsulationKey1024).EncapsulationKey", Method, 24, ""}, + {"(*DecapsulationKey768).Bytes", Method, 24, ""}, + {"(*DecapsulationKey768).Decapsulate", Method, 24, ""}, + {"(*DecapsulationKey768).EncapsulationKey", Method, 24, ""}, + {"(*EncapsulationKey1024).Bytes", Method, 24, ""}, + {"(*EncapsulationKey1024).Encapsulate", Method, 24, ""}, + {"(*EncapsulationKey768).Bytes", Method, 24, ""}, + {"(*EncapsulationKey768).Encapsulate", Method, 24, ""}, + {"CiphertextSize1024", Const, 24, ""}, + {"CiphertextSize768", Const, 24, ""}, + {"DecapsulationKey1024", Type, 24, ""}, + {"DecapsulationKey768", Type, 24, ""}, + {"EncapsulationKey1024", Type, 24, ""}, + {"EncapsulationKey768", Type, 24, ""}, + {"EncapsulationKeySize1024", Const, 24, ""}, + {"EncapsulationKeySize768", Const, 24, ""}, + {"GenerateKey1024", Func, 24, "func() (*DecapsulationKey1024, error)"}, + {"GenerateKey768", Func, 24, "func() (*DecapsulationKey768, error)"}, + {"NewDecapsulationKey1024", Func, 24, "func(seed []byte) (*DecapsulationKey1024, error)"}, + {"NewDecapsulationKey768", Func, 24, "func(seed []byte) (*DecapsulationKey768, error)"}, + {"NewEncapsulationKey1024", Func, 24, "func(encapsulationKey []byte) (*EncapsulationKey1024, error)"}, + {"NewEncapsulationKey768", Func, 24, "func(encapsulationKey []byte) (*EncapsulationKey768, error)"}, + {"SeedSize", Const, 24, ""}, + {"SharedKeySize", Const, 24, ""}, }, "crypto/pbkdf2": { - {"Key", Func, 24}, + {"Key", Func, 24, "func[Hash hash.Hash](h func() Hash, password string, salt []byte, iter int, keyLength int) ([]byte, error)"}, }, "crypto/rand": { - {"Int", Func, 0}, - {"Prime", Func, 0}, - {"Read", Func, 0}, - {"Reader", Var, 0}, - {"Text", Func, 24}, + {"Int", Func, 0, "func(rand io.Reader, max *big.Int) (n *big.Int, err error)"}, + {"Prime", Func, 0, "func(rand io.Reader, bits int) (*big.Int, error)"}, + {"Read", Func, 0, "func(b []byte) (n int, err error)"}, + {"Reader", Var, 0, ""}, + {"Text", Func, 24, "func() string"}, }, "crypto/rc4": { - {"(*Cipher).Reset", Method, 0}, - {"(*Cipher).XORKeyStream", Method, 0}, - {"(KeySizeError).Error", Method, 0}, - {"Cipher", Type, 0}, - {"KeySizeError", Type, 0}, - {"NewCipher", Func, 0}, + {"(*Cipher).Reset", Method, 0, ""}, + {"(*Cipher).XORKeyStream", Method, 0, ""}, + {"(KeySizeError).Error", Method, 0, ""}, + {"Cipher", Type, 0, ""}, + {"KeySizeError", Type, 0, ""}, + {"NewCipher", Func, 0, "func(key []byte) (*Cipher, error)"}, }, "crypto/rsa": { - {"(*PSSOptions).HashFunc", Method, 4}, - {"(*PrivateKey).Decrypt", Method, 5}, - {"(*PrivateKey).Equal", Method, 15}, - {"(*PrivateKey).Precompute", Method, 0}, - {"(*PrivateKey).Public", Method, 4}, - {"(*PrivateKey).Sign", Method, 4}, - {"(*PrivateKey).Size", Method, 11}, - {"(*PrivateKey).Validate", Method, 0}, - {"(*PublicKey).Equal", Method, 15}, - {"(*PublicKey).Size", Method, 11}, - {"CRTValue", Type, 0}, - {"CRTValue.Coeff", Field, 0}, - {"CRTValue.Exp", Field, 0}, - {"CRTValue.R", Field, 0}, - {"DecryptOAEP", Func, 0}, - {"DecryptPKCS1v15", Func, 0}, - {"DecryptPKCS1v15SessionKey", Func, 0}, - {"EncryptOAEP", Func, 0}, - {"EncryptPKCS1v15", Func, 0}, - {"ErrDecryption", Var, 0}, - {"ErrMessageTooLong", Var, 0}, - {"ErrVerification", Var, 0}, - {"GenerateKey", Func, 0}, - {"GenerateMultiPrimeKey", Func, 0}, - {"OAEPOptions", Type, 5}, - {"OAEPOptions.Hash", Field, 5}, - {"OAEPOptions.Label", Field, 5}, - {"OAEPOptions.MGFHash", Field, 20}, - {"PKCS1v15DecryptOptions", Type, 5}, - {"PKCS1v15DecryptOptions.SessionKeyLen", Field, 5}, - {"PSSOptions", Type, 2}, - {"PSSOptions.Hash", Field, 4}, - {"PSSOptions.SaltLength", Field, 2}, - {"PSSSaltLengthAuto", Const, 2}, - {"PSSSaltLengthEqualsHash", Const, 2}, - {"PrecomputedValues", Type, 0}, - {"PrecomputedValues.CRTValues", Field, 0}, - {"PrecomputedValues.Dp", Field, 0}, - {"PrecomputedValues.Dq", Field, 0}, - {"PrecomputedValues.Qinv", Field, 0}, - {"PrivateKey", Type, 0}, - {"PrivateKey.D", Field, 0}, - {"PrivateKey.Precomputed", Field, 0}, - {"PrivateKey.Primes", Field, 0}, - {"PrivateKey.PublicKey", Field, 0}, - {"PublicKey", Type, 0}, - {"PublicKey.E", Field, 0}, - {"PublicKey.N", Field, 0}, - {"SignPKCS1v15", Func, 0}, - {"SignPSS", Func, 2}, - {"VerifyPKCS1v15", Func, 0}, - {"VerifyPSS", Func, 2}, + {"(*PSSOptions).HashFunc", Method, 4, ""}, + {"(*PrivateKey).Decrypt", Method, 5, ""}, + {"(*PrivateKey).Equal", Method, 15, ""}, + {"(*PrivateKey).Precompute", Method, 0, ""}, + {"(*PrivateKey).Public", Method, 4, ""}, + {"(*PrivateKey).Sign", Method, 4, ""}, + {"(*PrivateKey).Size", Method, 11, ""}, + {"(*PrivateKey).Validate", Method, 0, ""}, + {"(*PublicKey).Equal", Method, 15, ""}, + {"(*PublicKey).Size", Method, 11, ""}, + {"CRTValue", Type, 0, ""}, + {"CRTValue.Coeff", Field, 0, ""}, + {"CRTValue.Exp", Field, 0, ""}, + {"CRTValue.R", Field, 0, ""}, + {"DecryptOAEP", Func, 0, "func(hash hash.Hash, random io.Reader, priv *PrivateKey, ciphertext []byte, label []byte) ([]byte, error)"}, + {"DecryptPKCS1v15", Func, 0, "func(random io.Reader, priv *PrivateKey, ciphertext []byte) ([]byte, error)"}, + {"DecryptPKCS1v15SessionKey", Func, 0, "func(random io.Reader, priv *PrivateKey, ciphertext []byte, key []byte) error"}, + {"EncryptOAEP", Func, 0, "func(hash hash.Hash, random io.Reader, pub *PublicKey, msg []byte, label []byte) ([]byte, error)"}, + {"EncryptPKCS1v15", Func, 0, "func(random io.Reader, pub *PublicKey, msg []byte) ([]byte, error)"}, + {"ErrDecryption", Var, 0, ""}, + {"ErrMessageTooLong", Var, 0, ""}, + {"ErrVerification", Var, 0, ""}, + {"GenerateKey", Func, 0, "func(random io.Reader, bits int) (*PrivateKey, error)"}, + {"GenerateMultiPrimeKey", Func, 0, "func(random io.Reader, nprimes int, bits int) (*PrivateKey, error)"}, + {"OAEPOptions", Type, 5, ""}, + {"OAEPOptions.Hash", Field, 5, ""}, + {"OAEPOptions.Label", Field, 5, ""}, + {"OAEPOptions.MGFHash", Field, 20, ""}, + {"PKCS1v15DecryptOptions", Type, 5, ""}, + {"PKCS1v15DecryptOptions.SessionKeyLen", Field, 5, ""}, + {"PSSOptions", Type, 2, ""}, + {"PSSOptions.Hash", Field, 4, ""}, + {"PSSOptions.SaltLength", Field, 2, ""}, + {"PSSSaltLengthAuto", Const, 2, ""}, + {"PSSSaltLengthEqualsHash", Const, 2, ""}, + {"PrecomputedValues", Type, 0, ""}, + {"PrecomputedValues.CRTValues", Field, 0, ""}, + {"PrecomputedValues.Dp", Field, 0, ""}, + {"PrecomputedValues.Dq", Field, 0, ""}, + {"PrecomputedValues.Qinv", Field, 0, ""}, + {"PrivateKey", Type, 0, ""}, + {"PrivateKey.D", Field, 0, ""}, + {"PrivateKey.Precomputed", Field, 0, ""}, + {"PrivateKey.Primes", Field, 0, ""}, + {"PrivateKey.PublicKey", Field, 0, ""}, + {"PublicKey", Type, 0, ""}, + {"PublicKey.E", Field, 0, ""}, + {"PublicKey.N", Field, 0, ""}, + {"SignPKCS1v15", Func, 0, "func(random io.Reader, priv *PrivateKey, hash crypto.Hash, hashed []byte) ([]byte, error)"}, + {"SignPSS", Func, 2, "func(rand io.Reader, priv *PrivateKey, hash crypto.Hash, digest []byte, opts *PSSOptions) ([]byte, error)"}, + {"VerifyPKCS1v15", Func, 0, "func(pub *PublicKey, hash crypto.Hash, hashed []byte, sig []byte) error"}, + {"VerifyPSS", Func, 2, "func(pub *PublicKey, hash crypto.Hash, digest []byte, sig []byte, opts *PSSOptions) error"}, }, "crypto/sha1": { - {"BlockSize", Const, 0}, - {"New", Func, 0}, - {"Size", Const, 0}, - {"Sum", Func, 2}, + {"BlockSize", Const, 0, ""}, + {"New", Func, 0, "func() hash.Hash"}, + {"Size", Const, 0, ""}, + {"Sum", Func, 2, "func(data []byte) [20]byte"}, }, "crypto/sha256": { - {"BlockSize", Const, 0}, - {"New", Func, 0}, - {"New224", Func, 0}, - {"Size", Const, 0}, - {"Size224", Const, 0}, - {"Sum224", Func, 2}, - {"Sum256", Func, 2}, + {"BlockSize", Const, 0, ""}, + {"New", Func, 0, "func() hash.Hash"}, + {"New224", Func, 0, "func() hash.Hash"}, + {"Size", Const, 0, ""}, + {"Size224", Const, 0, ""}, + {"Sum224", Func, 2, "func(data []byte) [28]byte"}, + {"Sum256", Func, 2, "func(data []byte) [32]byte"}, }, "crypto/sha3": { - {"(*SHA3).AppendBinary", Method, 24}, - {"(*SHA3).BlockSize", Method, 24}, - {"(*SHA3).MarshalBinary", Method, 24}, - {"(*SHA3).Reset", Method, 24}, - {"(*SHA3).Size", Method, 24}, - {"(*SHA3).Sum", Method, 24}, - {"(*SHA3).UnmarshalBinary", Method, 24}, - {"(*SHA3).Write", Method, 24}, - {"(*SHAKE).AppendBinary", Method, 24}, - {"(*SHAKE).BlockSize", Method, 24}, - {"(*SHAKE).MarshalBinary", Method, 24}, - {"(*SHAKE).Read", Method, 24}, - {"(*SHAKE).Reset", Method, 24}, - {"(*SHAKE).UnmarshalBinary", Method, 24}, - {"(*SHAKE).Write", Method, 24}, - {"New224", Func, 24}, - {"New256", Func, 24}, - {"New384", Func, 24}, - {"New512", Func, 24}, - {"NewCSHAKE128", Func, 24}, - {"NewCSHAKE256", Func, 24}, - {"NewSHAKE128", Func, 24}, - {"NewSHAKE256", Func, 24}, - {"SHA3", Type, 24}, - {"SHAKE", Type, 24}, - {"Sum224", Func, 24}, - {"Sum256", Func, 24}, - {"Sum384", Func, 24}, - {"Sum512", Func, 24}, - {"SumSHAKE128", Func, 24}, - {"SumSHAKE256", Func, 24}, + {"(*SHA3).AppendBinary", Method, 24, ""}, + {"(*SHA3).BlockSize", Method, 24, ""}, + {"(*SHA3).MarshalBinary", Method, 24, ""}, + {"(*SHA3).Reset", Method, 24, ""}, + {"(*SHA3).Size", Method, 24, ""}, + {"(*SHA3).Sum", Method, 24, ""}, + {"(*SHA3).UnmarshalBinary", Method, 24, ""}, + {"(*SHA3).Write", Method, 24, ""}, + {"(*SHAKE).AppendBinary", Method, 24, ""}, + {"(*SHAKE).BlockSize", Method, 24, ""}, + {"(*SHAKE).MarshalBinary", Method, 24, ""}, + {"(*SHAKE).Read", Method, 24, ""}, + {"(*SHAKE).Reset", Method, 24, ""}, + {"(*SHAKE).UnmarshalBinary", Method, 24, ""}, + {"(*SHAKE).Write", Method, 24, ""}, + {"New224", Func, 24, "func() *SHA3"}, + {"New256", Func, 24, "func() *SHA3"}, + {"New384", Func, 24, "func() *SHA3"}, + {"New512", Func, 24, "func() *SHA3"}, + {"NewCSHAKE128", Func, 24, "func(N []byte, S []byte) *SHAKE"}, + {"NewCSHAKE256", Func, 24, "func(N []byte, S []byte) *SHAKE"}, + {"NewSHAKE128", Func, 24, "func() *SHAKE"}, + {"NewSHAKE256", Func, 24, "func() *SHAKE"}, + {"SHA3", Type, 24, ""}, + {"SHAKE", Type, 24, ""}, + {"Sum224", Func, 24, "func(data []byte) [28]byte"}, + {"Sum256", Func, 24, "func(data []byte) [32]byte"}, + {"Sum384", Func, 24, "func(data []byte) [48]byte"}, + {"Sum512", Func, 24, "func(data []byte) [64]byte"}, + {"SumSHAKE128", Func, 24, "func(data []byte, length int) []byte"}, + {"SumSHAKE256", Func, 24, "func(data []byte, length int) []byte"}, }, "crypto/sha512": { - {"BlockSize", Const, 0}, - {"New", Func, 0}, - {"New384", Func, 0}, - {"New512_224", Func, 5}, - {"New512_256", Func, 5}, - {"Size", Const, 0}, - {"Size224", Const, 5}, - {"Size256", Const, 5}, - {"Size384", Const, 0}, - {"Sum384", Func, 2}, - {"Sum512", Func, 2}, - {"Sum512_224", Func, 5}, - {"Sum512_256", Func, 5}, + {"BlockSize", Const, 0, ""}, + {"New", Func, 0, "func() hash.Hash"}, + {"New384", Func, 0, "func() hash.Hash"}, + {"New512_224", Func, 5, "func() hash.Hash"}, + {"New512_256", Func, 5, "func() hash.Hash"}, + {"Size", Const, 0, ""}, + {"Size224", Const, 5, ""}, + {"Size256", Const, 5, ""}, + {"Size384", Const, 0, ""}, + {"Sum384", Func, 2, "func(data []byte) [48]byte"}, + {"Sum512", Func, 2, "func(data []byte) [64]byte"}, + {"Sum512_224", Func, 5, "func(data []byte) [28]byte"}, + {"Sum512_256", Func, 5, "func(data []byte) [32]byte"}, }, "crypto/subtle": { - {"ConstantTimeByteEq", Func, 0}, - {"ConstantTimeCompare", Func, 0}, - {"ConstantTimeCopy", Func, 0}, - {"ConstantTimeEq", Func, 0}, - {"ConstantTimeLessOrEq", Func, 2}, - {"ConstantTimeSelect", Func, 0}, - {"WithDataIndependentTiming", Func, 24}, - {"XORBytes", Func, 20}, + {"ConstantTimeByteEq", Func, 0, "func(x uint8, y uint8) int"}, + {"ConstantTimeCompare", Func, 0, "func(x []byte, y []byte) int"}, + {"ConstantTimeCopy", Func, 0, "func(v int, x []byte, y []byte)"}, + {"ConstantTimeEq", Func, 0, "func(x int32, y int32) int"}, + {"ConstantTimeLessOrEq", Func, 2, "func(x int, y int) int"}, + {"ConstantTimeSelect", Func, 0, "func(v int, x int, y int) int"}, + {"WithDataIndependentTiming", Func, 24, "func(f func())"}, + {"XORBytes", Func, 20, "func(dst []byte, x []byte, y []byte) int"}, }, "crypto/tls": { - {"(*CertificateRequestInfo).Context", Method, 17}, - {"(*CertificateRequestInfo).SupportsCertificate", Method, 14}, - {"(*CertificateVerificationError).Error", Method, 20}, - {"(*CertificateVerificationError).Unwrap", Method, 20}, - {"(*ClientHelloInfo).Context", Method, 17}, - {"(*ClientHelloInfo).SupportsCertificate", Method, 14}, - {"(*ClientSessionState).ResumptionState", Method, 21}, - {"(*Config).BuildNameToCertificate", Method, 0}, - {"(*Config).Clone", Method, 8}, - {"(*Config).DecryptTicket", Method, 21}, - {"(*Config).EncryptTicket", Method, 21}, - {"(*Config).SetSessionTicketKeys", Method, 5}, - {"(*Conn).Close", Method, 0}, - {"(*Conn).CloseWrite", Method, 8}, - {"(*Conn).ConnectionState", Method, 0}, - {"(*Conn).Handshake", Method, 0}, - {"(*Conn).HandshakeContext", Method, 17}, - {"(*Conn).LocalAddr", Method, 0}, - {"(*Conn).NetConn", Method, 18}, - {"(*Conn).OCSPResponse", Method, 0}, - {"(*Conn).Read", Method, 0}, - {"(*Conn).RemoteAddr", Method, 0}, - {"(*Conn).SetDeadline", Method, 0}, - {"(*Conn).SetReadDeadline", Method, 0}, - {"(*Conn).SetWriteDeadline", Method, 0}, - {"(*Conn).VerifyHostname", Method, 0}, - {"(*Conn).Write", Method, 0}, - {"(*ConnectionState).ExportKeyingMaterial", Method, 11}, - {"(*Dialer).Dial", Method, 15}, - {"(*Dialer).DialContext", Method, 15}, - {"(*ECHRejectionError).Error", Method, 23}, - {"(*QUICConn).Close", Method, 21}, - {"(*QUICConn).ConnectionState", Method, 21}, - {"(*QUICConn).HandleData", Method, 21}, - {"(*QUICConn).NextEvent", Method, 21}, - {"(*QUICConn).SendSessionTicket", Method, 21}, - {"(*QUICConn).SetTransportParameters", Method, 21}, - {"(*QUICConn).Start", Method, 21}, - {"(*QUICConn).StoreSession", Method, 23}, - {"(*SessionState).Bytes", Method, 21}, - {"(AlertError).Error", Method, 21}, - {"(ClientAuthType).String", Method, 15}, - {"(CurveID).String", Method, 15}, - {"(QUICEncryptionLevel).String", Method, 21}, - {"(RecordHeaderError).Error", Method, 6}, - {"(SignatureScheme).String", Method, 15}, - {"AlertError", Type, 21}, - {"Certificate", Type, 0}, - {"Certificate.Certificate", Field, 0}, - {"Certificate.Leaf", Field, 0}, - {"Certificate.OCSPStaple", Field, 0}, - {"Certificate.PrivateKey", Field, 0}, - {"Certificate.SignedCertificateTimestamps", Field, 5}, - {"Certificate.SupportedSignatureAlgorithms", Field, 14}, - {"CertificateRequestInfo", Type, 8}, - {"CertificateRequestInfo.AcceptableCAs", Field, 8}, - {"CertificateRequestInfo.SignatureSchemes", Field, 8}, - {"CertificateRequestInfo.Version", Field, 14}, - {"CertificateVerificationError", Type, 20}, - {"CertificateVerificationError.Err", Field, 20}, - {"CertificateVerificationError.UnverifiedCertificates", Field, 20}, - {"CipherSuite", Type, 14}, - {"CipherSuite.ID", Field, 14}, - {"CipherSuite.Insecure", Field, 14}, - {"CipherSuite.Name", Field, 14}, - {"CipherSuite.SupportedVersions", Field, 14}, - {"CipherSuiteName", Func, 14}, - {"CipherSuites", Func, 14}, - {"Client", Func, 0}, - {"ClientAuthType", Type, 0}, - {"ClientHelloInfo", Type, 4}, - {"ClientHelloInfo.CipherSuites", Field, 4}, - {"ClientHelloInfo.Conn", Field, 8}, - {"ClientHelloInfo.Extensions", Field, 24}, - {"ClientHelloInfo.ServerName", Field, 4}, - {"ClientHelloInfo.SignatureSchemes", Field, 8}, - {"ClientHelloInfo.SupportedCurves", Field, 4}, - {"ClientHelloInfo.SupportedPoints", Field, 4}, - {"ClientHelloInfo.SupportedProtos", Field, 8}, - {"ClientHelloInfo.SupportedVersions", Field, 8}, - {"ClientSessionCache", Type, 3}, - {"ClientSessionState", Type, 3}, - {"Config", Type, 0}, - {"Config.Certificates", Field, 0}, - {"Config.CipherSuites", Field, 0}, - {"Config.ClientAuth", Field, 0}, - {"Config.ClientCAs", Field, 0}, - {"Config.ClientSessionCache", Field, 3}, - {"Config.CurvePreferences", Field, 3}, - {"Config.DynamicRecordSizingDisabled", Field, 7}, - {"Config.EncryptedClientHelloConfigList", Field, 23}, - {"Config.EncryptedClientHelloKeys", Field, 24}, - {"Config.EncryptedClientHelloRejectionVerify", Field, 23}, - {"Config.GetCertificate", Field, 4}, - {"Config.GetClientCertificate", Field, 8}, - {"Config.GetConfigForClient", Field, 8}, - {"Config.InsecureSkipVerify", Field, 0}, - {"Config.KeyLogWriter", Field, 8}, - {"Config.MaxVersion", Field, 2}, - {"Config.MinVersion", Field, 2}, - {"Config.NameToCertificate", Field, 0}, - {"Config.NextProtos", Field, 0}, - {"Config.PreferServerCipherSuites", Field, 1}, - {"Config.Rand", Field, 0}, - {"Config.Renegotiation", Field, 7}, - {"Config.RootCAs", Field, 0}, - {"Config.ServerName", Field, 0}, - {"Config.SessionTicketKey", Field, 1}, - {"Config.SessionTicketsDisabled", Field, 1}, - {"Config.Time", Field, 0}, - {"Config.UnwrapSession", Field, 21}, - {"Config.VerifyConnection", Field, 15}, - {"Config.VerifyPeerCertificate", Field, 8}, - {"Config.WrapSession", Field, 21}, - {"Conn", Type, 0}, - {"ConnectionState", Type, 0}, - {"ConnectionState.CipherSuite", Field, 0}, - {"ConnectionState.CurveID", Field, 25}, - {"ConnectionState.DidResume", Field, 1}, - {"ConnectionState.ECHAccepted", Field, 23}, - {"ConnectionState.HandshakeComplete", Field, 0}, - {"ConnectionState.NegotiatedProtocol", Field, 0}, - {"ConnectionState.NegotiatedProtocolIsMutual", Field, 0}, - {"ConnectionState.OCSPResponse", Field, 5}, - {"ConnectionState.PeerCertificates", Field, 0}, - {"ConnectionState.ServerName", Field, 0}, - {"ConnectionState.SignedCertificateTimestamps", Field, 5}, - {"ConnectionState.TLSUnique", Field, 4}, - {"ConnectionState.VerifiedChains", Field, 0}, - {"ConnectionState.Version", Field, 3}, - {"CurveID", Type, 3}, - {"CurveP256", Const, 3}, - {"CurveP384", Const, 3}, - {"CurveP521", Const, 3}, - {"Dial", Func, 0}, - {"DialWithDialer", Func, 3}, - {"Dialer", Type, 15}, - {"Dialer.Config", Field, 15}, - {"Dialer.NetDialer", Field, 15}, - {"ECDSAWithP256AndSHA256", Const, 8}, - {"ECDSAWithP384AndSHA384", Const, 8}, - {"ECDSAWithP521AndSHA512", Const, 8}, - {"ECDSAWithSHA1", Const, 10}, - {"ECHRejectionError", Type, 23}, - {"ECHRejectionError.RetryConfigList", Field, 23}, - {"Ed25519", Const, 13}, - {"EncryptedClientHelloKey", Type, 24}, - {"EncryptedClientHelloKey.Config", Field, 24}, - {"EncryptedClientHelloKey.PrivateKey", Field, 24}, - {"EncryptedClientHelloKey.SendAsRetry", Field, 24}, - {"InsecureCipherSuites", Func, 14}, - {"Listen", Func, 0}, - {"LoadX509KeyPair", Func, 0}, - {"NewLRUClientSessionCache", Func, 3}, - {"NewListener", Func, 0}, - {"NewResumptionState", Func, 21}, - {"NoClientCert", Const, 0}, - {"PKCS1WithSHA1", Const, 8}, - {"PKCS1WithSHA256", Const, 8}, - {"PKCS1WithSHA384", Const, 8}, - {"PKCS1WithSHA512", Const, 8}, - {"PSSWithSHA256", Const, 8}, - {"PSSWithSHA384", Const, 8}, - {"PSSWithSHA512", Const, 8}, - {"ParseSessionState", Func, 21}, - {"QUICClient", Func, 21}, - {"QUICConfig", Type, 21}, - {"QUICConfig.EnableSessionEvents", Field, 23}, - {"QUICConfig.TLSConfig", Field, 21}, - {"QUICConn", Type, 21}, - {"QUICEncryptionLevel", Type, 21}, - {"QUICEncryptionLevelApplication", Const, 21}, - {"QUICEncryptionLevelEarly", Const, 21}, - {"QUICEncryptionLevelHandshake", Const, 21}, - {"QUICEncryptionLevelInitial", Const, 21}, - {"QUICEvent", Type, 21}, - {"QUICEvent.Data", Field, 21}, - {"QUICEvent.Kind", Field, 21}, - {"QUICEvent.Level", Field, 21}, - {"QUICEvent.SessionState", Field, 23}, - {"QUICEvent.Suite", Field, 21}, - {"QUICEventKind", Type, 21}, - {"QUICHandshakeDone", Const, 21}, - {"QUICNoEvent", Const, 21}, - {"QUICRejectedEarlyData", Const, 21}, - {"QUICResumeSession", Const, 23}, - {"QUICServer", Func, 21}, - {"QUICSessionTicketOptions", Type, 21}, - {"QUICSessionTicketOptions.EarlyData", Field, 21}, - {"QUICSessionTicketOptions.Extra", Field, 23}, - {"QUICSetReadSecret", Const, 21}, - {"QUICSetWriteSecret", Const, 21}, - {"QUICStoreSession", Const, 23}, - {"QUICTransportParameters", Const, 21}, - {"QUICTransportParametersRequired", Const, 21}, - {"QUICWriteData", Const, 21}, - {"RecordHeaderError", Type, 6}, - {"RecordHeaderError.Conn", Field, 12}, - {"RecordHeaderError.Msg", Field, 6}, - {"RecordHeaderError.RecordHeader", Field, 6}, - {"RenegotiateFreelyAsClient", Const, 7}, - {"RenegotiateNever", Const, 7}, - {"RenegotiateOnceAsClient", Const, 7}, - {"RenegotiationSupport", Type, 7}, - {"RequestClientCert", Const, 0}, - {"RequireAndVerifyClientCert", Const, 0}, - {"RequireAnyClientCert", Const, 0}, - {"Server", Func, 0}, - {"SessionState", Type, 21}, - {"SessionState.EarlyData", Field, 21}, - {"SessionState.Extra", Field, 21}, - {"SignatureScheme", Type, 8}, - {"TLS_AES_128_GCM_SHA256", Const, 12}, - {"TLS_AES_256_GCM_SHA384", Const, 12}, - {"TLS_CHACHA20_POLY1305_SHA256", Const, 12}, - {"TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA", Const, 2}, - {"TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256", Const, 8}, - {"TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256", Const, 2}, - {"TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA", Const, 2}, - {"TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384", Const, 5}, - {"TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305", Const, 8}, - {"TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256", Const, 14}, - {"TLS_ECDHE_ECDSA_WITH_RC4_128_SHA", Const, 2}, - {"TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA", Const, 0}, - {"TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA", Const, 0}, - {"TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256", Const, 8}, - {"TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256", Const, 2}, - {"TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA", Const, 1}, - {"TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384", Const, 5}, - {"TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305", Const, 8}, - {"TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256", Const, 14}, - {"TLS_ECDHE_RSA_WITH_RC4_128_SHA", Const, 0}, - {"TLS_FALLBACK_SCSV", Const, 4}, - {"TLS_RSA_WITH_3DES_EDE_CBC_SHA", Const, 0}, - {"TLS_RSA_WITH_AES_128_CBC_SHA", Const, 0}, - {"TLS_RSA_WITH_AES_128_CBC_SHA256", Const, 8}, - {"TLS_RSA_WITH_AES_128_GCM_SHA256", Const, 6}, - {"TLS_RSA_WITH_AES_256_CBC_SHA", Const, 1}, - {"TLS_RSA_WITH_AES_256_GCM_SHA384", Const, 6}, - {"TLS_RSA_WITH_RC4_128_SHA", Const, 0}, - {"VerifyClientCertIfGiven", Const, 0}, - {"VersionName", Func, 21}, - {"VersionSSL30", Const, 2}, - {"VersionTLS10", Const, 2}, - {"VersionTLS11", Const, 2}, - {"VersionTLS12", Const, 2}, - {"VersionTLS13", Const, 12}, - {"X25519", Const, 8}, - {"X25519MLKEM768", Const, 24}, - {"X509KeyPair", Func, 0}, + {"(*CertificateRequestInfo).Context", Method, 17, ""}, + {"(*CertificateRequestInfo).SupportsCertificate", Method, 14, ""}, + {"(*CertificateVerificationError).Error", Method, 20, ""}, + {"(*CertificateVerificationError).Unwrap", Method, 20, ""}, + {"(*ClientHelloInfo).Context", Method, 17, ""}, + {"(*ClientHelloInfo).SupportsCertificate", Method, 14, ""}, + {"(*ClientSessionState).ResumptionState", Method, 21, ""}, + {"(*Config).BuildNameToCertificate", Method, 0, ""}, + {"(*Config).Clone", Method, 8, ""}, + {"(*Config).DecryptTicket", Method, 21, ""}, + {"(*Config).EncryptTicket", Method, 21, ""}, + {"(*Config).SetSessionTicketKeys", Method, 5, ""}, + {"(*Conn).Close", Method, 0, ""}, + {"(*Conn).CloseWrite", Method, 8, ""}, + {"(*Conn).ConnectionState", Method, 0, ""}, + {"(*Conn).Handshake", Method, 0, ""}, + {"(*Conn).HandshakeContext", Method, 17, ""}, + {"(*Conn).LocalAddr", Method, 0, ""}, + {"(*Conn).NetConn", Method, 18, ""}, + {"(*Conn).OCSPResponse", Method, 0, ""}, + {"(*Conn).Read", Method, 0, ""}, + {"(*Conn).RemoteAddr", Method, 0, ""}, + {"(*Conn).SetDeadline", Method, 0, ""}, + {"(*Conn).SetReadDeadline", Method, 0, ""}, + {"(*Conn).SetWriteDeadline", Method, 0, ""}, + {"(*Conn).VerifyHostname", Method, 0, ""}, + {"(*Conn).Write", Method, 0, ""}, + {"(*ConnectionState).ExportKeyingMaterial", Method, 11, ""}, + {"(*Dialer).Dial", Method, 15, ""}, + {"(*Dialer).DialContext", Method, 15, ""}, + {"(*ECHRejectionError).Error", Method, 23, ""}, + {"(*QUICConn).Close", Method, 21, ""}, + {"(*QUICConn).ConnectionState", Method, 21, ""}, + {"(*QUICConn).HandleData", Method, 21, ""}, + {"(*QUICConn).NextEvent", Method, 21, ""}, + {"(*QUICConn).SendSessionTicket", Method, 21, ""}, + {"(*QUICConn).SetTransportParameters", Method, 21, ""}, + {"(*QUICConn).Start", Method, 21, ""}, + {"(*QUICConn).StoreSession", Method, 23, ""}, + {"(*SessionState).Bytes", Method, 21, ""}, + {"(AlertError).Error", Method, 21, ""}, + {"(ClientAuthType).String", Method, 15, ""}, + {"(CurveID).String", Method, 15, ""}, + {"(QUICEncryptionLevel).String", Method, 21, ""}, + {"(RecordHeaderError).Error", Method, 6, ""}, + {"(SignatureScheme).String", Method, 15, ""}, + {"AlertError", Type, 21, ""}, + {"Certificate", Type, 0, ""}, + {"Certificate.Certificate", Field, 0, ""}, + {"Certificate.Leaf", Field, 0, ""}, + {"Certificate.OCSPStaple", Field, 0, ""}, + {"Certificate.PrivateKey", Field, 0, ""}, + {"Certificate.SignedCertificateTimestamps", Field, 5, ""}, + {"Certificate.SupportedSignatureAlgorithms", Field, 14, ""}, + {"CertificateRequestInfo", Type, 8, ""}, + {"CertificateRequestInfo.AcceptableCAs", Field, 8, ""}, + {"CertificateRequestInfo.SignatureSchemes", Field, 8, ""}, + {"CertificateRequestInfo.Version", Field, 14, ""}, + {"CertificateVerificationError", Type, 20, ""}, + {"CertificateVerificationError.Err", Field, 20, ""}, + {"CertificateVerificationError.UnverifiedCertificates", Field, 20, ""}, + {"CipherSuite", Type, 14, ""}, + {"CipherSuite.ID", Field, 14, ""}, + {"CipherSuite.Insecure", Field, 14, ""}, + {"CipherSuite.Name", Field, 14, ""}, + {"CipherSuite.SupportedVersions", Field, 14, ""}, + {"CipherSuiteName", Func, 14, "func(id uint16) string"}, + {"CipherSuites", Func, 14, "func() []*CipherSuite"}, + {"Client", Func, 0, "func(conn net.Conn, config *Config) *Conn"}, + {"ClientAuthType", Type, 0, ""}, + {"ClientHelloInfo", Type, 4, ""}, + {"ClientHelloInfo.CipherSuites", Field, 4, ""}, + {"ClientHelloInfo.Conn", Field, 8, ""}, + {"ClientHelloInfo.Extensions", Field, 24, ""}, + {"ClientHelloInfo.ServerName", Field, 4, ""}, + {"ClientHelloInfo.SignatureSchemes", Field, 8, ""}, + {"ClientHelloInfo.SupportedCurves", Field, 4, ""}, + {"ClientHelloInfo.SupportedPoints", Field, 4, ""}, + {"ClientHelloInfo.SupportedProtos", Field, 8, ""}, + {"ClientHelloInfo.SupportedVersions", Field, 8, ""}, + {"ClientSessionCache", Type, 3, ""}, + {"ClientSessionState", Type, 3, ""}, + {"Config", Type, 0, ""}, + {"Config.Certificates", Field, 0, ""}, + {"Config.CipherSuites", Field, 0, ""}, + {"Config.ClientAuth", Field, 0, ""}, + {"Config.ClientCAs", Field, 0, ""}, + {"Config.ClientSessionCache", Field, 3, ""}, + {"Config.CurvePreferences", Field, 3, ""}, + {"Config.DynamicRecordSizingDisabled", Field, 7, ""}, + {"Config.EncryptedClientHelloConfigList", Field, 23, ""}, + {"Config.EncryptedClientHelloKeys", Field, 24, ""}, + {"Config.EncryptedClientHelloRejectionVerify", Field, 23, ""}, + {"Config.GetCertificate", Field, 4, ""}, + {"Config.GetClientCertificate", Field, 8, ""}, + {"Config.GetConfigForClient", Field, 8, ""}, + {"Config.InsecureSkipVerify", Field, 0, ""}, + {"Config.KeyLogWriter", Field, 8, ""}, + {"Config.MaxVersion", Field, 2, ""}, + {"Config.MinVersion", Field, 2, ""}, + {"Config.NameToCertificate", Field, 0, ""}, + {"Config.NextProtos", Field, 0, ""}, + {"Config.PreferServerCipherSuites", Field, 1, ""}, + {"Config.Rand", Field, 0, ""}, + {"Config.Renegotiation", Field, 7, ""}, + {"Config.RootCAs", Field, 0, ""}, + {"Config.ServerName", Field, 0, ""}, + {"Config.SessionTicketKey", Field, 1, ""}, + {"Config.SessionTicketsDisabled", Field, 1, ""}, + {"Config.Time", Field, 0, ""}, + {"Config.UnwrapSession", Field, 21, ""}, + {"Config.VerifyConnection", Field, 15, ""}, + {"Config.VerifyPeerCertificate", Field, 8, ""}, + {"Config.WrapSession", Field, 21, ""}, + {"Conn", Type, 0, ""}, + {"ConnectionState", Type, 0, ""}, + {"ConnectionState.CipherSuite", Field, 0, ""}, + {"ConnectionState.CurveID", Field, 25, ""}, + {"ConnectionState.DidResume", Field, 1, ""}, + {"ConnectionState.ECHAccepted", Field, 23, ""}, + {"ConnectionState.HandshakeComplete", Field, 0, ""}, + {"ConnectionState.NegotiatedProtocol", Field, 0, ""}, + {"ConnectionState.NegotiatedProtocolIsMutual", Field, 0, ""}, + {"ConnectionState.OCSPResponse", Field, 5, ""}, + {"ConnectionState.PeerCertificates", Field, 0, ""}, + {"ConnectionState.ServerName", Field, 0, ""}, + {"ConnectionState.SignedCertificateTimestamps", Field, 5, ""}, + {"ConnectionState.TLSUnique", Field, 4, ""}, + {"ConnectionState.VerifiedChains", Field, 0, ""}, + {"ConnectionState.Version", Field, 3, ""}, + {"CurveID", Type, 3, ""}, + {"CurveP256", Const, 3, ""}, + {"CurveP384", Const, 3, ""}, + {"CurveP521", Const, 3, ""}, + {"Dial", Func, 0, "func(network string, addr string, config *Config) (*Conn, error)"}, + {"DialWithDialer", Func, 3, "func(dialer *net.Dialer, network string, addr string, config *Config) (*Conn, error)"}, + {"Dialer", Type, 15, ""}, + {"Dialer.Config", Field, 15, ""}, + {"Dialer.NetDialer", Field, 15, ""}, + {"ECDSAWithP256AndSHA256", Const, 8, ""}, + {"ECDSAWithP384AndSHA384", Const, 8, ""}, + {"ECDSAWithP521AndSHA512", Const, 8, ""}, + {"ECDSAWithSHA1", Const, 10, ""}, + {"ECHRejectionError", Type, 23, ""}, + {"ECHRejectionError.RetryConfigList", Field, 23, ""}, + {"Ed25519", Const, 13, ""}, + {"EncryptedClientHelloKey", Type, 24, ""}, + {"EncryptedClientHelloKey.Config", Field, 24, ""}, + {"EncryptedClientHelloKey.PrivateKey", Field, 24, ""}, + {"EncryptedClientHelloKey.SendAsRetry", Field, 24, ""}, + {"InsecureCipherSuites", Func, 14, "func() []*CipherSuite"}, + {"Listen", Func, 0, "func(network string, laddr string, config *Config) (net.Listener, error)"}, + {"LoadX509KeyPair", Func, 0, "func(certFile string, keyFile string) (Certificate, error)"}, + {"NewLRUClientSessionCache", Func, 3, "func(capacity int) ClientSessionCache"}, + {"NewListener", Func, 0, "func(inner net.Listener, config *Config) net.Listener"}, + {"NewResumptionState", Func, 21, "func(ticket []byte, state *SessionState) (*ClientSessionState, error)"}, + {"NoClientCert", Const, 0, ""}, + {"PKCS1WithSHA1", Const, 8, ""}, + {"PKCS1WithSHA256", Const, 8, ""}, + {"PKCS1WithSHA384", Const, 8, ""}, + {"PKCS1WithSHA512", Const, 8, ""}, + {"PSSWithSHA256", Const, 8, ""}, + {"PSSWithSHA384", Const, 8, ""}, + {"PSSWithSHA512", Const, 8, ""}, + {"ParseSessionState", Func, 21, "func(data []byte) (*SessionState, error)"}, + {"QUICClient", Func, 21, "func(config *QUICConfig) *QUICConn"}, + {"QUICConfig", Type, 21, ""}, + {"QUICConfig.EnableSessionEvents", Field, 23, ""}, + {"QUICConfig.TLSConfig", Field, 21, ""}, + {"QUICConn", Type, 21, ""}, + {"QUICEncryptionLevel", Type, 21, ""}, + {"QUICEncryptionLevelApplication", Const, 21, ""}, + {"QUICEncryptionLevelEarly", Const, 21, ""}, + {"QUICEncryptionLevelHandshake", Const, 21, ""}, + {"QUICEncryptionLevelInitial", Const, 21, ""}, + {"QUICEvent", Type, 21, ""}, + {"QUICEvent.Data", Field, 21, ""}, + {"QUICEvent.Kind", Field, 21, ""}, + {"QUICEvent.Level", Field, 21, ""}, + {"QUICEvent.SessionState", Field, 23, ""}, + {"QUICEvent.Suite", Field, 21, ""}, + {"QUICEventKind", Type, 21, ""}, + {"QUICHandshakeDone", Const, 21, ""}, + {"QUICNoEvent", Const, 21, ""}, + {"QUICRejectedEarlyData", Const, 21, ""}, + {"QUICResumeSession", Const, 23, ""}, + {"QUICServer", Func, 21, "func(config *QUICConfig) *QUICConn"}, + {"QUICSessionTicketOptions", Type, 21, ""}, + {"QUICSessionTicketOptions.EarlyData", Field, 21, ""}, + {"QUICSessionTicketOptions.Extra", Field, 23, ""}, + {"QUICSetReadSecret", Const, 21, ""}, + {"QUICSetWriteSecret", Const, 21, ""}, + {"QUICStoreSession", Const, 23, ""}, + {"QUICTransportParameters", Const, 21, ""}, + {"QUICTransportParametersRequired", Const, 21, ""}, + {"QUICWriteData", Const, 21, ""}, + {"RecordHeaderError", Type, 6, ""}, + {"RecordHeaderError.Conn", Field, 12, ""}, + {"RecordHeaderError.Msg", Field, 6, ""}, + {"RecordHeaderError.RecordHeader", Field, 6, ""}, + {"RenegotiateFreelyAsClient", Const, 7, ""}, + {"RenegotiateNever", Const, 7, ""}, + {"RenegotiateOnceAsClient", Const, 7, ""}, + {"RenegotiationSupport", Type, 7, ""}, + {"RequestClientCert", Const, 0, ""}, + {"RequireAndVerifyClientCert", Const, 0, ""}, + {"RequireAnyClientCert", Const, 0, ""}, + {"Server", Func, 0, "func(conn net.Conn, config *Config) *Conn"}, + {"SessionState", Type, 21, ""}, + {"SessionState.EarlyData", Field, 21, ""}, + {"SessionState.Extra", Field, 21, ""}, + {"SignatureScheme", Type, 8, ""}, + {"TLS_AES_128_GCM_SHA256", Const, 12, ""}, + {"TLS_AES_256_GCM_SHA384", Const, 12, ""}, + {"TLS_CHACHA20_POLY1305_SHA256", Const, 12, ""}, + {"TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA", Const, 2, ""}, + {"TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256", Const, 8, ""}, + {"TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256", Const, 2, ""}, + {"TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA", Const, 2, ""}, + {"TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384", Const, 5, ""}, + {"TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305", Const, 8, ""}, + {"TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256", Const, 14, ""}, + {"TLS_ECDHE_ECDSA_WITH_RC4_128_SHA", Const, 2, ""}, + {"TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA", Const, 0, ""}, + {"TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA", Const, 0, ""}, + {"TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256", Const, 8, ""}, + {"TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256", Const, 2, ""}, + {"TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA", Const, 1, ""}, + {"TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384", Const, 5, ""}, + {"TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305", Const, 8, ""}, + {"TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256", Const, 14, ""}, + {"TLS_ECDHE_RSA_WITH_RC4_128_SHA", Const, 0, ""}, + {"TLS_FALLBACK_SCSV", Const, 4, ""}, + {"TLS_RSA_WITH_3DES_EDE_CBC_SHA", Const, 0, ""}, + {"TLS_RSA_WITH_AES_128_CBC_SHA", Const, 0, ""}, + {"TLS_RSA_WITH_AES_128_CBC_SHA256", Const, 8, ""}, + {"TLS_RSA_WITH_AES_128_GCM_SHA256", Const, 6, ""}, + {"TLS_RSA_WITH_AES_256_CBC_SHA", Const, 1, ""}, + {"TLS_RSA_WITH_AES_256_GCM_SHA384", Const, 6, ""}, + {"TLS_RSA_WITH_RC4_128_SHA", Const, 0, ""}, + {"VerifyClientCertIfGiven", Const, 0, ""}, + {"VersionName", Func, 21, "func(version uint16) string"}, + {"VersionSSL30", Const, 2, ""}, + {"VersionTLS10", Const, 2, ""}, + {"VersionTLS11", Const, 2, ""}, + {"VersionTLS12", Const, 2, ""}, + {"VersionTLS13", Const, 12, ""}, + {"X25519", Const, 8, ""}, + {"X25519MLKEM768", Const, 24, ""}, + {"X509KeyPair", Func, 0, "func(certPEMBlock []byte, keyPEMBlock []byte) (Certificate, error)"}, }, "crypto/x509": { - {"(*CertPool).AddCert", Method, 0}, - {"(*CertPool).AddCertWithConstraint", Method, 22}, - {"(*CertPool).AppendCertsFromPEM", Method, 0}, - {"(*CertPool).Clone", Method, 19}, - {"(*CertPool).Equal", Method, 19}, - {"(*CertPool).Subjects", Method, 0}, - {"(*Certificate).CheckCRLSignature", Method, 0}, - {"(*Certificate).CheckSignature", Method, 0}, - {"(*Certificate).CheckSignatureFrom", Method, 0}, - {"(*Certificate).CreateCRL", Method, 0}, - {"(*Certificate).Equal", Method, 0}, - {"(*Certificate).Verify", Method, 0}, - {"(*Certificate).VerifyHostname", Method, 0}, - {"(*CertificateRequest).CheckSignature", Method, 5}, - {"(*OID).UnmarshalBinary", Method, 23}, - {"(*OID).UnmarshalText", Method, 23}, - {"(*RevocationList).CheckSignatureFrom", Method, 19}, - {"(CertificateInvalidError).Error", Method, 0}, - {"(ConstraintViolationError).Error", Method, 0}, - {"(HostnameError).Error", Method, 0}, - {"(InsecureAlgorithmError).Error", Method, 6}, - {"(OID).AppendBinary", Method, 24}, - {"(OID).AppendText", Method, 24}, - {"(OID).Equal", Method, 22}, - {"(OID).EqualASN1OID", Method, 22}, - {"(OID).MarshalBinary", Method, 23}, - {"(OID).MarshalText", Method, 23}, - {"(OID).String", Method, 22}, - {"(PublicKeyAlgorithm).String", Method, 10}, - {"(SignatureAlgorithm).String", Method, 6}, - {"(SystemRootsError).Error", Method, 1}, - {"(SystemRootsError).Unwrap", Method, 16}, - {"(UnhandledCriticalExtension).Error", Method, 0}, - {"(UnknownAuthorityError).Error", Method, 0}, - {"CANotAuthorizedForExtKeyUsage", Const, 10}, - {"CANotAuthorizedForThisName", Const, 0}, - {"CertPool", Type, 0}, - {"Certificate", Type, 0}, - {"Certificate.AuthorityKeyId", Field, 0}, - {"Certificate.BasicConstraintsValid", Field, 0}, - {"Certificate.CRLDistributionPoints", Field, 2}, - {"Certificate.DNSNames", Field, 0}, - {"Certificate.EmailAddresses", Field, 0}, - {"Certificate.ExcludedDNSDomains", Field, 9}, - {"Certificate.ExcludedEmailAddresses", Field, 10}, - {"Certificate.ExcludedIPRanges", Field, 10}, - {"Certificate.ExcludedURIDomains", Field, 10}, - {"Certificate.ExtKeyUsage", Field, 0}, - {"Certificate.Extensions", Field, 2}, - {"Certificate.ExtraExtensions", Field, 2}, - {"Certificate.IPAddresses", Field, 1}, - {"Certificate.InhibitAnyPolicy", Field, 24}, - {"Certificate.InhibitAnyPolicyZero", Field, 24}, - {"Certificate.InhibitPolicyMapping", Field, 24}, - {"Certificate.InhibitPolicyMappingZero", Field, 24}, - {"Certificate.IsCA", Field, 0}, - {"Certificate.Issuer", Field, 0}, - {"Certificate.IssuingCertificateURL", Field, 2}, - {"Certificate.KeyUsage", Field, 0}, - {"Certificate.MaxPathLen", Field, 0}, - {"Certificate.MaxPathLenZero", Field, 4}, - {"Certificate.NotAfter", Field, 0}, - {"Certificate.NotBefore", Field, 0}, - {"Certificate.OCSPServer", Field, 2}, - {"Certificate.PermittedDNSDomains", Field, 0}, - {"Certificate.PermittedDNSDomainsCritical", Field, 0}, - {"Certificate.PermittedEmailAddresses", Field, 10}, - {"Certificate.PermittedIPRanges", Field, 10}, - {"Certificate.PermittedURIDomains", Field, 10}, - {"Certificate.Policies", Field, 22}, - {"Certificate.PolicyIdentifiers", Field, 0}, - {"Certificate.PolicyMappings", Field, 24}, - {"Certificate.PublicKey", Field, 0}, - {"Certificate.PublicKeyAlgorithm", Field, 0}, - {"Certificate.Raw", Field, 0}, - {"Certificate.RawIssuer", Field, 0}, - {"Certificate.RawSubject", Field, 0}, - {"Certificate.RawSubjectPublicKeyInfo", Field, 0}, - {"Certificate.RawTBSCertificate", Field, 0}, - {"Certificate.RequireExplicitPolicy", Field, 24}, - {"Certificate.RequireExplicitPolicyZero", Field, 24}, - {"Certificate.SerialNumber", Field, 0}, - {"Certificate.Signature", Field, 0}, - {"Certificate.SignatureAlgorithm", Field, 0}, - {"Certificate.Subject", Field, 0}, - {"Certificate.SubjectKeyId", Field, 0}, - {"Certificate.URIs", Field, 10}, - {"Certificate.UnhandledCriticalExtensions", Field, 5}, - {"Certificate.UnknownExtKeyUsage", Field, 0}, - {"Certificate.Version", Field, 0}, - {"CertificateInvalidError", Type, 0}, - {"CertificateInvalidError.Cert", Field, 0}, - {"CertificateInvalidError.Detail", Field, 10}, - {"CertificateInvalidError.Reason", Field, 0}, - {"CertificateRequest", Type, 3}, - {"CertificateRequest.Attributes", Field, 3}, - {"CertificateRequest.DNSNames", Field, 3}, - {"CertificateRequest.EmailAddresses", Field, 3}, - {"CertificateRequest.Extensions", Field, 3}, - {"CertificateRequest.ExtraExtensions", Field, 3}, - {"CertificateRequest.IPAddresses", Field, 3}, - {"CertificateRequest.PublicKey", Field, 3}, - {"CertificateRequest.PublicKeyAlgorithm", Field, 3}, - {"CertificateRequest.Raw", Field, 3}, - {"CertificateRequest.RawSubject", Field, 3}, - {"CertificateRequest.RawSubjectPublicKeyInfo", Field, 3}, - {"CertificateRequest.RawTBSCertificateRequest", Field, 3}, - {"CertificateRequest.Signature", Field, 3}, - {"CertificateRequest.SignatureAlgorithm", Field, 3}, - {"CertificateRequest.Subject", Field, 3}, - {"CertificateRequest.URIs", Field, 10}, - {"CertificateRequest.Version", Field, 3}, - {"ConstraintViolationError", Type, 0}, - {"CreateCertificate", Func, 0}, - {"CreateCertificateRequest", Func, 3}, - {"CreateRevocationList", Func, 15}, - {"DSA", Const, 0}, - {"DSAWithSHA1", Const, 0}, - {"DSAWithSHA256", Const, 0}, - {"DecryptPEMBlock", Func, 1}, - {"ECDSA", Const, 1}, - {"ECDSAWithSHA1", Const, 1}, - {"ECDSAWithSHA256", Const, 1}, - {"ECDSAWithSHA384", Const, 1}, - {"ECDSAWithSHA512", Const, 1}, - {"Ed25519", Const, 13}, - {"EncryptPEMBlock", Func, 1}, - {"ErrUnsupportedAlgorithm", Var, 0}, - {"Expired", Const, 0}, - {"ExtKeyUsage", Type, 0}, - {"ExtKeyUsageAny", Const, 0}, - {"ExtKeyUsageClientAuth", Const, 0}, - {"ExtKeyUsageCodeSigning", Const, 0}, - {"ExtKeyUsageEmailProtection", Const, 0}, - {"ExtKeyUsageIPSECEndSystem", Const, 1}, - {"ExtKeyUsageIPSECTunnel", Const, 1}, - {"ExtKeyUsageIPSECUser", Const, 1}, - {"ExtKeyUsageMicrosoftCommercialCodeSigning", Const, 10}, - {"ExtKeyUsageMicrosoftKernelCodeSigning", Const, 10}, - {"ExtKeyUsageMicrosoftServerGatedCrypto", Const, 1}, - {"ExtKeyUsageNetscapeServerGatedCrypto", Const, 1}, - {"ExtKeyUsageOCSPSigning", Const, 0}, - {"ExtKeyUsageServerAuth", Const, 0}, - {"ExtKeyUsageTimeStamping", Const, 0}, - {"HostnameError", Type, 0}, - {"HostnameError.Certificate", Field, 0}, - {"HostnameError.Host", Field, 0}, - {"IncompatibleUsage", Const, 1}, - {"IncorrectPasswordError", Var, 1}, - {"InsecureAlgorithmError", Type, 6}, - {"InvalidReason", Type, 0}, - {"IsEncryptedPEMBlock", Func, 1}, - {"KeyUsage", Type, 0}, - {"KeyUsageCRLSign", Const, 0}, - {"KeyUsageCertSign", Const, 0}, - {"KeyUsageContentCommitment", Const, 0}, - {"KeyUsageDataEncipherment", Const, 0}, - {"KeyUsageDecipherOnly", Const, 0}, - {"KeyUsageDigitalSignature", Const, 0}, - {"KeyUsageEncipherOnly", Const, 0}, - {"KeyUsageKeyAgreement", Const, 0}, - {"KeyUsageKeyEncipherment", Const, 0}, - {"MD2WithRSA", Const, 0}, - {"MD5WithRSA", Const, 0}, - {"MarshalECPrivateKey", Func, 2}, - {"MarshalPKCS1PrivateKey", Func, 0}, - {"MarshalPKCS1PublicKey", Func, 10}, - {"MarshalPKCS8PrivateKey", Func, 10}, - {"MarshalPKIXPublicKey", Func, 0}, - {"NameConstraintsWithoutSANs", Const, 10}, - {"NameMismatch", Const, 8}, - {"NewCertPool", Func, 0}, - {"NoValidChains", Const, 24}, - {"NotAuthorizedToSign", Const, 0}, - {"OID", Type, 22}, - {"OIDFromInts", Func, 22}, - {"PEMCipher", Type, 1}, - {"PEMCipher3DES", Const, 1}, - {"PEMCipherAES128", Const, 1}, - {"PEMCipherAES192", Const, 1}, - {"PEMCipherAES256", Const, 1}, - {"PEMCipherDES", Const, 1}, - {"ParseCRL", Func, 0}, - {"ParseCertificate", Func, 0}, - {"ParseCertificateRequest", Func, 3}, - {"ParseCertificates", Func, 0}, - {"ParseDERCRL", Func, 0}, - {"ParseECPrivateKey", Func, 1}, - {"ParseOID", Func, 23}, - {"ParsePKCS1PrivateKey", Func, 0}, - {"ParsePKCS1PublicKey", Func, 10}, - {"ParsePKCS8PrivateKey", Func, 0}, - {"ParsePKIXPublicKey", Func, 0}, - {"ParseRevocationList", Func, 19}, - {"PolicyMapping", Type, 24}, - {"PolicyMapping.IssuerDomainPolicy", Field, 24}, - {"PolicyMapping.SubjectDomainPolicy", Field, 24}, - {"PublicKeyAlgorithm", Type, 0}, - {"PureEd25519", Const, 13}, - {"RSA", Const, 0}, - {"RevocationList", Type, 15}, - {"RevocationList.AuthorityKeyId", Field, 19}, - {"RevocationList.Extensions", Field, 19}, - {"RevocationList.ExtraExtensions", Field, 15}, - {"RevocationList.Issuer", Field, 19}, - {"RevocationList.NextUpdate", Field, 15}, - {"RevocationList.Number", Field, 15}, - {"RevocationList.Raw", Field, 19}, - {"RevocationList.RawIssuer", Field, 19}, - {"RevocationList.RawTBSRevocationList", Field, 19}, - {"RevocationList.RevokedCertificateEntries", Field, 21}, - {"RevocationList.RevokedCertificates", Field, 15}, - {"RevocationList.Signature", Field, 19}, - {"RevocationList.SignatureAlgorithm", Field, 15}, - {"RevocationList.ThisUpdate", Field, 15}, - {"RevocationListEntry", Type, 21}, - {"RevocationListEntry.Extensions", Field, 21}, - {"RevocationListEntry.ExtraExtensions", Field, 21}, - {"RevocationListEntry.Raw", Field, 21}, - {"RevocationListEntry.ReasonCode", Field, 21}, - {"RevocationListEntry.RevocationTime", Field, 21}, - {"RevocationListEntry.SerialNumber", Field, 21}, - {"SHA1WithRSA", Const, 0}, - {"SHA256WithRSA", Const, 0}, - {"SHA256WithRSAPSS", Const, 8}, - {"SHA384WithRSA", Const, 0}, - {"SHA384WithRSAPSS", Const, 8}, - {"SHA512WithRSA", Const, 0}, - {"SHA512WithRSAPSS", Const, 8}, - {"SetFallbackRoots", Func, 20}, - {"SignatureAlgorithm", Type, 0}, - {"SystemCertPool", Func, 7}, - {"SystemRootsError", Type, 1}, - {"SystemRootsError.Err", Field, 7}, - {"TooManyConstraints", Const, 10}, - {"TooManyIntermediates", Const, 0}, - {"UnconstrainedName", Const, 10}, - {"UnhandledCriticalExtension", Type, 0}, - {"UnknownAuthorityError", Type, 0}, - {"UnknownAuthorityError.Cert", Field, 8}, - {"UnknownPublicKeyAlgorithm", Const, 0}, - {"UnknownSignatureAlgorithm", Const, 0}, - {"VerifyOptions", Type, 0}, - {"VerifyOptions.CertificatePolicies", Field, 24}, - {"VerifyOptions.CurrentTime", Field, 0}, - {"VerifyOptions.DNSName", Field, 0}, - {"VerifyOptions.Intermediates", Field, 0}, - {"VerifyOptions.KeyUsages", Field, 1}, - {"VerifyOptions.MaxConstraintComparisions", Field, 10}, - {"VerifyOptions.Roots", Field, 0}, + {"(*CertPool).AddCert", Method, 0, ""}, + {"(*CertPool).AddCertWithConstraint", Method, 22, ""}, + {"(*CertPool).AppendCertsFromPEM", Method, 0, ""}, + {"(*CertPool).Clone", Method, 19, ""}, + {"(*CertPool).Equal", Method, 19, ""}, + {"(*CertPool).Subjects", Method, 0, ""}, + {"(*Certificate).CheckCRLSignature", Method, 0, ""}, + {"(*Certificate).CheckSignature", Method, 0, ""}, + {"(*Certificate).CheckSignatureFrom", Method, 0, ""}, + {"(*Certificate).CreateCRL", Method, 0, ""}, + {"(*Certificate).Equal", Method, 0, ""}, + {"(*Certificate).Verify", Method, 0, ""}, + {"(*Certificate).VerifyHostname", Method, 0, ""}, + {"(*CertificateRequest).CheckSignature", Method, 5, ""}, + {"(*OID).UnmarshalBinary", Method, 23, ""}, + {"(*OID).UnmarshalText", Method, 23, ""}, + {"(*RevocationList).CheckSignatureFrom", Method, 19, ""}, + {"(CertificateInvalidError).Error", Method, 0, ""}, + {"(ConstraintViolationError).Error", Method, 0, ""}, + {"(HostnameError).Error", Method, 0, ""}, + {"(InsecureAlgorithmError).Error", Method, 6, ""}, + {"(OID).AppendBinary", Method, 24, ""}, + {"(OID).AppendText", Method, 24, ""}, + {"(OID).Equal", Method, 22, ""}, + {"(OID).EqualASN1OID", Method, 22, ""}, + {"(OID).MarshalBinary", Method, 23, ""}, + {"(OID).MarshalText", Method, 23, ""}, + {"(OID).String", Method, 22, ""}, + {"(PublicKeyAlgorithm).String", Method, 10, ""}, + {"(SignatureAlgorithm).String", Method, 6, ""}, + {"(SystemRootsError).Error", Method, 1, ""}, + {"(SystemRootsError).Unwrap", Method, 16, ""}, + {"(UnhandledCriticalExtension).Error", Method, 0, ""}, + {"(UnknownAuthorityError).Error", Method, 0, ""}, + {"CANotAuthorizedForExtKeyUsage", Const, 10, ""}, + {"CANotAuthorizedForThisName", Const, 0, ""}, + {"CertPool", Type, 0, ""}, + {"Certificate", Type, 0, ""}, + {"Certificate.AuthorityKeyId", Field, 0, ""}, + {"Certificate.BasicConstraintsValid", Field, 0, ""}, + {"Certificate.CRLDistributionPoints", Field, 2, ""}, + {"Certificate.DNSNames", Field, 0, ""}, + {"Certificate.EmailAddresses", Field, 0, ""}, + {"Certificate.ExcludedDNSDomains", Field, 9, ""}, + {"Certificate.ExcludedEmailAddresses", Field, 10, ""}, + {"Certificate.ExcludedIPRanges", Field, 10, ""}, + {"Certificate.ExcludedURIDomains", Field, 10, ""}, + {"Certificate.ExtKeyUsage", Field, 0, ""}, + {"Certificate.Extensions", Field, 2, ""}, + {"Certificate.ExtraExtensions", Field, 2, ""}, + {"Certificate.IPAddresses", Field, 1, ""}, + {"Certificate.InhibitAnyPolicy", Field, 24, ""}, + {"Certificate.InhibitAnyPolicyZero", Field, 24, ""}, + {"Certificate.InhibitPolicyMapping", Field, 24, ""}, + {"Certificate.InhibitPolicyMappingZero", Field, 24, ""}, + {"Certificate.IsCA", Field, 0, ""}, + {"Certificate.Issuer", Field, 0, ""}, + {"Certificate.IssuingCertificateURL", Field, 2, ""}, + {"Certificate.KeyUsage", Field, 0, ""}, + {"Certificate.MaxPathLen", Field, 0, ""}, + {"Certificate.MaxPathLenZero", Field, 4, ""}, + {"Certificate.NotAfter", Field, 0, ""}, + {"Certificate.NotBefore", Field, 0, ""}, + {"Certificate.OCSPServer", Field, 2, ""}, + {"Certificate.PermittedDNSDomains", Field, 0, ""}, + {"Certificate.PermittedDNSDomainsCritical", Field, 0, ""}, + {"Certificate.PermittedEmailAddresses", Field, 10, ""}, + {"Certificate.PermittedIPRanges", Field, 10, ""}, + {"Certificate.PermittedURIDomains", Field, 10, ""}, + {"Certificate.Policies", Field, 22, ""}, + {"Certificate.PolicyIdentifiers", Field, 0, ""}, + {"Certificate.PolicyMappings", Field, 24, ""}, + {"Certificate.PublicKey", Field, 0, ""}, + {"Certificate.PublicKeyAlgorithm", Field, 0, ""}, + {"Certificate.Raw", Field, 0, ""}, + {"Certificate.RawIssuer", Field, 0, ""}, + {"Certificate.RawSubject", Field, 0, ""}, + {"Certificate.RawSubjectPublicKeyInfo", Field, 0, ""}, + {"Certificate.RawTBSCertificate", Field, 0, ""}, + {"Certificate.RequireExplicitPolicy", Field, 24, ""}, + {"Certificate.RequireExplicitPolicyZero", Field, 24, ""}, + {"Certificate.SerialNumber", Field, 0, ""}, + {"Certificate.Signature", Field, 0, ""}, + {"Certificate.SignatureAlgorithm", Field, 0, ""}, + {"Certificate.Subject", Field, 0, ""}, + {"Certificate.SubjectKeyId", Field, 0, ""}, + {"Certificate.URIs", Field, 10, ""}, + {"Certificate.UnhandledCriticalExtensions", Field, 5, ""}, + {"Certificate.UnknownExtKeyUsage", Field, 0, ""}, + {"Certificate.Version", Field, 0, ""}, + {"CertificateInvalidError", Type, 0, ""}, + {"CertificateInvalidError.Cert", Field, 0, ""}, + {"CertificateInvalidError.Detail", Field, 10, ""}, + {"CertificateInvalidError.Reason", Field, 0, ""}, + {"CertificateRequest", Type, 3, ""}, + {"CertificateRequest.Attributes", Field, 3, ""}, + {"CertificateRequest.DNSNames", Field, 3, ""}, + {"CertificateRequest.EmailAddresses", Field, 3, ""}, + {"CertificateRequest.Extensions", Field, 3, ""}, + {"CertificateRequest.ExtraExtensions", Field, 3, ""}, + {"CertificateRequest.IPAddresses", Field, 3, ""}, + {"CertificateRequest.PublicKey", Field, 3, ""}, + {"CertificateRequest.PublicKeyAlgorithm", Field, 3, ""}, + {"CertificateRequest.Raw", Field, 3, ""}, + {"CertificateRequest.RawSubject", Field, 3, ""}, + {"CertificateRequest.RawSubjectPublicKeyInfo", Field, 3, ""}, + {"CertificateRequest.RawTBSCertificateRequest", Field, 3, ""}, + {"CertificateRequest.Signature", Field, 3, ""}, + {"CertificateRequest.SignatureAlgorithm", Field, 3, ""}, + {"CertificateRequest.Subject", Field, 3, ""}, + {"CertificateRequest.URIs", Field, 10, ""}, + {"CertificateRequest.Version", Field, 3, ""}, + {"ConstraintViolationError", Type, 0, ""}, + {"CreateCertificate", Func, 0, "func(rand io.Reader, template *Certificate, parent *Certificate, pub any, priv any) ([]byte, error)"}, + {"CreateCertificateRequest", Func, 3, "func(rand io.Reader, template *CertificateRequest, priv any) (csr []byte, err error)"}, + {"CreateRevocationList", Func, 15, "func(rand io.Reader, template *RevocationList, issuer *Certificate, priv crypto.Signer) ([]byte, error)"}, + {"DSA", Const, 0, ""}, + {"DSAWithSHA1", Const, 0, ""}, + {"DSAWithSHA256", Const, 0, ""}, + {"DecryptPEMBlock", Func, 1, "func(b *pem.Block, password []byte) ([]byte, error)"}, + {"ECDSA", Const, 1, ""}, + {"ECDSAWithSHA1", Const, 1, ""}, + {"ECDSAWithSHA256", Const, 1, ""}, + {"ECDSAWithSHA384", Const, 1, ""}, + {"ECDSAWithSHA512", Const, 1, ""}, + {"Ed25519", Const, 13, ""}, + {"EncryptPEMBlock", Func, 1, "func(rand io.Reader, blockType string, data []byte, password []byte, alg PEMCipher) (*pem.Block, error)"}, + {"ErrUnsupportedAlgorithm", Var, 0, ""}, + {"Expired", Const, 0, ""}, + {"ExtKeyUsage", Type, 0, ""}, + {"ExtKeyUsageAny", Const, 0, ""}, + {"ExtKeyUsageClientAuth", Const, 0, ""}, + {"ExtKeyUsageCodeSigning", Const, 0, ""}, + {"ExtKeyUsageEmailProtection", Const, 0, ""}, + {"ExtKeyUsageIPSECEndSystem", Const, 1, ""}, + {"ExtKeyUsageIPSECTunnel", Const, 1, ""}, + {"ExtKeyUsageIPSECUser", Const, 1, ""}, + {"ExtKeyUsageMicrosoftCommercialCodeSigning", Const, 10, ""}, + {"ExtKeyUsageMicrosoftKernelCodeSigning", Const, 10, ""}, + {"ExtKeyUsageMicrosoftServerGatedCrypto", Const, 1, ""}, + {"ExtKeyUsageNetscapeServerGatedCrypto", Const, 1, ""}, + {"ExtKeyUsageOCSPSigning", Const, 0, ""}, + {"ExtKeyUsageServerAuth", Const, 0, ""}, + {"ExtKeyUsageTimeStamping", Const, 0, ""}, + {"HostnameError", Type, 0, ""}, + {"HostnameError.Certificate", Field, 0, ""}, + {"HostnameError.Host", Field, 0, ""}, + {"IncompatibleUsage", Const, 1, ""}, + {"IncorrectPasswordError", Var, 1, ""}, + {"InsecureAlgorithmError", Type, 6, ""}, + {"InvalidReason", Type, 0, ""}, + {"IsEncryptedPEMBlock", Func, 1, "func(b *pem.Block) bool"}, + {"KeyUsage", Type, 0, ""}, + {"KeyUsageCRLSign", Const, 0, ""}, + {"KeyUsageCertSign", Const, 0, ""}, + {"KeyUsageContentCommitment", Const, 0, ""}, + {"KeyUsageDataEncipherment", Const, 0, ""}, + {"KeyUsageDecipherOnly", Const, 0, ""}, + {"KeyUsageDigitalSignature", Const, 0, ""}, + {"KeyUsageEncipherOnly", Const, 0, ""}, + {"KeyUsageKeyAgreement", Const, 0, ""}, + {"KeyUsageKeyEncipherment", Const, 0, ""}, + {"MD2WithRSA", Const, 0, ""}, + {"MD5WithRSA", Const, 0, ""}, + {"MarshalECPrivateKey", Func, 2, "func(key *ecdsa.PrivateKey) ([]byte, error)"}, + {"MarshalPKCS1PrivateKey", Func, 0, "func(key *rsa.PrivateKey) []byte"}, + {"MarshalPKCS1PublicKey", Func, 10, "func(key *rsa.PublicKey) []byte"}, + {"MarshalPKCS8PrivateKey", Func, 10, "func(key any) ([]byte, error)"}, + {"MarshalPKIXPublicKey", Func, 0, "func(pub any) ([]byte, error)"}, + {"NameConstraintsWithoutSANs", Const, 10, ""}, + {"NameMismatch", Const, 8, ""}, + {"NewCertPool", Func, 0, "func() *CertPool"}, + {"NoValidChains", Const, 24, ""}, + {"NotAuthorizedToSign", Const, 0, ""}, + {"OID", Type, 22, ""}, + {"OIDFromInts", Func, 22, "func(oid []uint64) (OID, error)"}, + {"PEMCipher", Type, 1, ""}, + {"PEMCipher3DES", Const, 1, ""}, + {"PEMCipherAES128", Const, 1, ""}, + {"PEMCipherAES192", Const, 1, ""}, + {"PEMCipherAES256", Const, 1, ""}, + {"PEMCipherDES", Const, 1, ""}, + {"ParseCRL", Func, 0, "func(crlBytes []byte) (*pkix.CertificateList, error)"}, + {"ParseCertificate", Func, 0, "func(der []byte) (*Certificate, error)"}, + {"ParseCertificateRequest", Func, 3, "func(asn1Data []byte) (*CertificateRequest, error)"}, + {"ParseCertificates", Func, 0, "func(der []byte) ([]*Certificate, error)"}, + {"ParseDERCRL", Func, 0, "func(derBytes []byte) (*pkix.CertificateList, error)"}, + {"ParseECPrivateKey", Func, 1, "func(der []byte) (*ecdsa.PrivateKey, error)"}, + {"ParseOID", Func, 23, "func(oid string) (OID, error)"}, + {"ParsePKCS1PrivateKey", Func, 0, "func(der []byte) (*rsa.PrivateKey, error)"}, + {"ParsePKCS1PublicKey", Func, 10, "func(der []byte) (*rsa.PublicKey, error)"}, + {"ParsePKCS8PrivateKey", Func, 0, "func(der []byte) (key any, err error)"}, + {"ParsePKIXPublicKey", Func, 0, "func(derBytes []byte) (pub any, err error)"}, + {"ParseRevocationList", Func, 19, "func(der []byte) (*RevocationList, error)"}, + {"PolicyMapping", Type, 24, ""}, + {"PolicyMapping.IssuerDomainPolicy", Field, 24, ""}, + {"PolicyMapping.SubjectDomainPolicy", Field, 24, ""}, + {"PublicKeyAlgorithm", Type, 0, ""}, + {"PureEd25519", Const, 13, ""}, + {"RSA", Const, 0, ""}, + {"RevocationList", Type, 15, ""}, + {"RevocationList.AuthorityKeyId", Field, 19, ""}, + {"RevocationList.Extensions", Field, 19, ""}, + {"RevocationList.ExtraExtensions", Field, 15, ""}, + {"RevocationList.Issuer", Field, 19, ""}, + {"RevocationList.NextUpdate", Field, 15, ""}, + {"RevocationList.Number", Field, 15, ""}, + {"RevocationList.Raw", Field, 19, ""}, + {"RevocationList.RawIssuer", Field, 19, ""}, + {"RevocationList.RawTBSRevocationList", Field, 19, ""}, + {"RevocationList.RevokedCertificateEntries", Field, 21, ""}, + {"RevocationList.RevokedCertificates", Field, 15, ""}, + {"RevocationList.Signature", Field, 19, ""}, + {"RevocationList.SignatureAlgorithm", Field, 15, ""}, + {"RevocationList.ThisUpdate", Field, 15, ""}, + {"RevocationListEntry", Type, 21, ""}, + {"RevocationListEntry.Extensions", Field, 21, ""}, + {"RevocationListEntry.ExtraExtensions", Field, 21, ""}, + {"RevocationListEntry.Raw", Field, 21, ""}, + {"RevocationListEntry.ReasonCode", Field, 21, ""}, + {"RevocationListEntry.RevocationTime", Field, 21, ""}, + {"RevocationListEntry.SerialNumber", Field, 21, ""}, + {"SHA1WithRSA", Const, 0, ""}, + {"SHA256WithRSA", Const, 0, ""}, + {"SHA256WithRSAPSS", Const, 8, ""}, + {"SHA384WithRSA", Const, 0, ""}, + {"SHA384WithRSAPSS", Const, 8, ""}, + {"SHA512WithRSA", Const, 0, ""}, + {"SHA512WithRSAPSS", Const, 8, ""}, + {"SetFallbackRoots", Func, 20, "func(roots *CertPool)"}, + {"SignatureAlgorithm", Type, 0, ""}, + {"SystemCertPool", Func, 7, "func() (*CertPool, error)"}, + {"SystemRootsError", Type, 1, ""}, + {"SystemRootsError.Err", Field, 7, ""}, + {"TooManyConstraints", Const, 10, ""}, + {"TooManyIntermediates", Const, 0, ""}, + {"UnconstrainedName", Const, 10, ""}, + {"UnhandledCriticalExtension", Type, 0, ""}, + {"UnknownAuthorityError", Type, 0, ""}, + {"UnknownAuthorityError.Cert", Field, 8, ""}, + {"UnknownPublicKeyAlgorithm", Const, 0, ""}, + {"UnknownSignatureAlgorithm", Const, 0, ""}, + {"VerifyOptions", Type, 0, ""}, + {"VerifyOptions.CertificatePolicies", Field, 24, ""}, + {"VerifyOptions.CurrentTime", Field, 0, ""}, + {"VerifyOptions.DNSName", Field, 0, ""}, + {"VerifyOptions.Intermediates", Field, 0, ""}, + {"VerifyOptions.KeyUsages", Field, 1, ""}, + {"VerifyOptions.MaxConstraintComparisions", Field, 10, ""}, + {"VerifyOptions.Roots", Field, 0, ""}, }, "crypto/x509/pkix": { - {"(*CertificateList).HasExpired", Method, 0}, - {"(*Name).FillFromRDNSequence", Method, 0}, - {"(Name).String", Method, 10}, - {"(Name).ToRDNSequence", Method, 0}, - {"(RDNSequence).String", Method, 10}, - {"AlgorithmIdentifier", Type, 0}, - {"AlgorithmIdentifier.Algorithm", Field, 0}, - {"AlgorithmIdentifier.Parameters", Field, 0}, - {"AttributeTypeAndValue", Type, 0}, - {"AttributeTypeAndValue.Type", Field, 0}, - {"AttributeTypeAndValue.Value", Field, 0}, - {"AttributeTypeAndValueSET", Type, 3}, - {"AttributeTypeAndValueSET.Type", Field, 3}, - {"AttributeTypeAndValueSET.Value", Field, 3}, - {"CertificateList", Type, 0}, - {"CertificateList.SignatureAlgorithm", Field, 0}, - {"CertificateList.SignatureValue", Field, 0}, - {"CertificateList.TBSCertList", Field, 0}, - {"Extension", Type, 0}, - {"Extension.Critical", Field, 0}, - {"Extension.Id", Field, 0}, - {"Extension.Value", Field, 0}, - {"Name", Type, 0}, - {"Name.CommonName", Field, 0}, - {"Name.Country", Field, 0}, - {"Name.ExtraNames", Field, 5}, - {"Name.Locality", Field, 0}, - {"Name.Names", Field, 0}, - {"Name.Organization", Field, 0}, - {"Name.OrganizationalUnit", Field, 0}, - {"Name.PostalCode", Field, 0}, - {"Name.Province", Field, 0}, - {"Name.SerialNumber", Field, 0}, - {"Name.StreetAddress", Field, 0}, - {"RDNSequence", Type, 0}, - {"RelativeDistinguishedNameSET", Type, 0}, - {"RevokedCertificate", Type, 0}, - {"RevokedCertificate.Extensions", Field, 0}, - {"RevokedCertificate.RevocationTime", Field, 0}, - {"RevokedCertificate.SerialNumber", Field, 0}, - {"TBSCertificateList", Type, 0}, - {"TBSCertificateList.Extensions", Field, 0}, - {"TBSCertificateList.Issuer", Field, 0}, - {"TBSCertificateList.NextUpdate", Field, 0}, - {"TBSCertificateList.Raw", Field, 0}, - {"TBSCertificateList.RevokedCertificates", Field, 0}, - {"TBSCertificateList.Signature", Field, 0}, - {"TBSCertificateList.ThisUpdate", Field, 0}, - {"TBSCertificateList.Version", Field, 0}, + {"(*CertificateList).HasExpired", Method, 0, ""}, + {"(*Name).FillFromRDNSequence", Method, 0, ""}, + {"(Name).String", Method, 10, ""}, + {"(Name).ToRDNSequence", Method, 0, ""}, + {"(RDNSequence).String", Method, 10, ""}, + {"AlgorithmIdentifier", Type, 0, ""}, + {"AlgorithmIdentifier.Algorithm", Field, 0, ""}, + {"AlgorithmIdentifier.Parameters", Field, 0, ""}, + {"AttributeTypeAndValue", Type, 0, ""}, + {"AttributeTypeAndValue.Type", Field, 0, ""}, + {"AttributeTypeAndValue.Value", Field, 0, ""}, + {"AttributeTypeAndValueSET", Type, 3, ""}, + {"AttributeTypeAndValueSET.Type", Field, 3, ""}, + {"AttributeTypeAndValueSET.Value", Field, 3, ""}, + {"CertificateList", Type, 0, ""}, + {"CertificateList.SignatureAlgorithm", Field, 0, ""}, + {"CertificateList.SignatureValue", Field, 0, ""}, + {"CertificateList.TBSCertList", Field, 0, ""}, + {"Extension", Type, 0, ""}, + {"Extension.Critical", Field, 0, ""}, + {"Extension.Id", Field, 0, ""}, + {"Extension.Value", Field, 0, ""}, + {"Name", Type, 0, ""}, + {"Name.CommonName", Field, 0, ""}, + {"Name.Country", Field, 0, ""}, + {"Name.ExtraNames", Field, 5, ""}, + {"Name.Locality", Field, 0, ""}, + {"Name.Names", Field, 0, ""}, + {"Name.Organization", Field, 0, ""}, + {"Name.OrganizationalUnit", Field, 0, ""}, + {"Name.PostalCode", Field, 0, ""}, + {"Name.Province", Field, 0, ""}, + {"Name.SerialNumber", Field, 0, ""}, + {"Name.StreetAddress", Field, 0, ""}, + {"RDNSequence", Type, 0, ""}, + {"RelativeDistinguishedNameSET", Type, 0, ""}, + {"RevokedCertificate", Type, 0, ""}, + {"RevokedCertificate.Extensions", Field, 0, ""}, + {"RevokedCertificate.RevocationTime", Field, 0, ""}, + {"RevokedCertificate.SerialNumber", Field, 0, ""}, + {"TBSCertificateList", Type, 0, ""}, + {"TBSCertificateList.Extensions", Field, 0, ""}, + {"TBSCertificateList.Issuer", Field, 0, ""}, + {"TBSCertificateList.NextUpdate", Field, 0, ""}, + {"TBSCertificateList.Raw", Field, 0, ""}, + {"TBSCertificateList.RevokedCertificates", Field, 0, ""}, + {"TBSCertificateList.Signature", Field, 0, ""}, + {"TBSCertificateList.ThisUpdate", Field, 0, ""}, + {"TBSCertificateList.Version", Field, 0, ""}, }, "database/sql": { - {"(*ColumnType).DatabaseTypeName", Method, 8}, - {"(*ColumnType).DecimalSize", Method, 8}, - {"(*ColumnType).Length", Method, 8}, - {"(*ColumnType).Name", Method, 8}, - {"(*ColumnType).Nullable", Method, 8}, - {"(*ColumnType).ScanType", Method, 8}, - {"(*Conn).BeginTx", Method, 9}, - {"(*Conn).Close", Method, 9}, - {"(*Conn).ExecContext", Method, 9}, - {"(*Conn).PingContext", Method, 9}, - {"(*Conn).PrepareContext", Method, 9}, - {"(*Conn).QueryContext", Method, 9}, - {"(*Conn).QueryRowContext", Method, 9}, - {"(*Conn).Raw", Method, 13}, - {"(*DB).Begin", Method, 0}, - {"(*DB).BeginTx", Method, 8}, - {"(*DB).Close", Method, 0}, - {"(*DB).Conn", Method, 9}, - {"(*DB).Driver", Method, 0}, - {"(*DB).Exec", Method, 0}, - {"(*DB).ExecContext", Method, 8}, - {"(*DB).Ping", Method, 1}, - {"(*DB).PingContext", Method, 8}, - {"(*DB).Prepare", Method, 0}, - {"(*DB).PrepareContext", Method, 8}, - {"(*DB).Query", Method, 0}, - {"(*DB).QueryContext", Method, 8}, - {"(*DB).QueryRow", Method, 0}, - {"(*DB).QueryRowContext", Method, 8}, - {"(*DB).SetConnMaxIdleTime", Method, 15}, - {"(*DB).SetConnMaxLifetime", Method, 6}, - {"(*DB).SetMaxIdleConns", Method, 1}, - {"(*DB).SetMaxOpenConns", Method, 2}, - {"(*DB).Stats", Method, 5}, - {"(*Null).Scan", Method, 22}, - {"(*NullBool).Scan", Method, 0}, - {"(*NullByte).Scan", Method, 17}, - {"(*NullFloat64).Scan", Method, 0}, - {"(*NullInt16).Scan", Method, 17}, - {"(*NullInt32).Scan", Method, 13}, - {"(*NullInt64).Scan", Method, 0}, - {"(*NullString).Scan", Method, 0}, - {"(*NullTime).Scan", Method, 13}, - {"(*Row).Err", Method, 15}, - {"(*Row).Scan", Method, 0}, - {"(*Rows).Close", Method, 0}, - {"(*Rows).ColumnTypes", Method, 8}, - {"(*Rows).Columns", Method, 0}, - {"(*Rows).Err", Method, 0}, - {"(*Rows).Next", Method, 0}, - {"(*Rows).NextResultSet", Method, 8}, - {"(*Rows).Scan", Method, 0}, - {"(*Stmt).Close", Method, 0}, - {"(*Stmt).Exec", Method, 0}, - {"(*Stmt).ExecContext", Method, 8}, - {"(*Stmt).Query", Method, 0}, - {"(*Stmt).QueryContext", Method, 8}, - {"(*Stmt).QueryRow", Method, 0}, - {"(*Stmt).QueryRowContext", Method, 8}, - {"(*Tx).Commit", Method, 0}, - {"(*Tx).Exec", Method, 0}, - {"(*Tx).ExecContext", Method, 8}, - {"(*Tx).Prepare", Method, 0}, - {"(*Tx).PrepareContext", Method, 8}, - {"(*Tx).Query", Method, 0}, - {"(*Tx).QueryContext", Method, 8}, - {"(*Tx).QueryRow", Method, 0}, - {"(*Tx).QueryRowContext", Method, 8}, - {"(*Tx).Rollback", Method, 0}, - {"(*Tx).Stmt", Method, 0}, - {"(*Tx).StmtContext", Method, 8}, - {"(IsolationLevel).String", Method, 11}, - {"(Null).Value", Method, 22}, - {"(NullBool).Value", Method, 0}, - {"(NullByte).Value", Method, 17}, - {"(NullFloat64).Value", Method, 0}, - {"(NullInt16).Value", Method, 17}, - {"(NullInt32).Value", Method, 13}, - {"(NullInt64).Value", Method, 0}, - {"(NullString).Value", Method, 0}, - {"(NullTime).Value", Method, 13}, - {"ColumnType", Type, 8}, - {"Conn", Type, 9}, - {"DB", Type, 0}, - {"DBStats", Type, 5}, - {"DBStats.Idle", Field, 11}, - {"DBStats.InUse", Field, 11}, - {"DBStats.MaxIdleClosed", Field, 11}, - {"DBStats.MaxIdleTimeClosed", Field, 15}, - {"DBStats.MaxLifetimeClosed", Field, 11}, - {"DBStats.MaxOpenConnections", Field, 11}, - {"DBStats.OpenConnections", Field, 5}, - {"DBStats.WaitCount", Field, 11}, - {"DBStats.WaitDuration", Field, 11}, - {"Drivers", Func, 4}, - {"ErrConnDone", Var, 9}, - {"ErrNoRows", Var, 0}, - {"ErrTxDone", Var, 0}, - {"IsolationLevel", Type, 8}, - {"LevelDefault", Const, 8}, - {"LevelLinearizable", Const, 8}, - {"LevelReadCommitted", Const, 8}, - {"LevelReadUncommitted", Const, 8}, - {"LevelRepeatableRead", Const, 8}, - {"LevelSerializable", Const, 8}, - {"LevelSnapshot", Const, 8}, - {"LevelWriteCommitted", Const, 8}, - {"Named", Func, 8}, - {"NamedArg", Type, 8}, - {"NamedArg.Name", Field, 8}, - {"NamedArg.Value", Field, 8}, - {"Null", Type, 22}, - {"Null.V", Field, 22}, - {"Null.Valid", Field, 22}, - {"NullBool", Type, 0}, - {"NullBool.Bool", Field, 0}, - {"NullBool.Valid", Field, 0}, - {"NullByte", Type, 17}, - {"NullByte.Byte", Field, 17}, - {"NullByte.Valid", Field, 17}, - {"NullFloat64", Type, 0}, - {"NullFloat64.Float64", Field, 0}, - {"NullFloat64.Valid", Field, 0}, - {"NullInt16", Type, 17}, - {"NullInt16.Int16", Field, 17}, - {"NullInt16.Valid", Field, 17}, - {"NullInt32", Type, 13}, - {"NullInt32.Int32", Field, 13}, - {"NullInt32.Valid", Field, 13}, - {"NullInt64", Type, 0}, - {"NullInt64.Int64", Field, 0}, - {"NullInt64.Valid", Field, 0}, - {"NullString", Type, 0}, - {"NullString.String", Field, 0}, - {"NullString.Valid", Field, 0}, - {"NullTime", Type, 13}, - {"NullTime.Time", Field, 13}, - {"NullTime.Valid", Field, 13}, - {"Open", Func, 0}, - {"OpenDB", Func, 10}, - {"Out", Type, 9}, - {"Out.Dest", Field, 9}, - {"Out.In", Field, 9}, - {"RawBytes", Type, 0}, - {"Register", Func, 0}, - {"Result", Type, 0}, - {"Row", Type, 0}, - {"Rows", Type, 0}, - {"Scanner", Type, 0}, - {"Stmt", Type, 0}, - {"Tx", Type, 0}, - {"TxOptions", Type, 8}, - {"TxOptions.Isolation", Field, 8}, - {"TxOptions.ReadOnly", Field, 8}, + {"(*ColumnType).DatabaseTypeName", Method, 8, ""}, + {"(*ColumnType).DecimalSize", Method, 8, ""}, + {"(*ColumnType).Length", Method, 8, ""}, + {"(*ColumnType).Name", Method, 8, ""}, + {"(*ColumnType).Nullable", Method, 8, ""}, + {"(*ColumnType).ScanType", Method, 8, ""}, + {"(*Conn).BeginTx", Method, 9, ""}, + {"(*Conn).Close", Method, 9, ""}, + {"(*Conn).ExecContext", Method, 9, ""}, + {"(*Conn).PingContext", Method, 9, ""}, + {"(*Conn).PrepareContext", Method, 9, ""}, + {"(*Conn).QueryContext", Method, 9, ""}, + {"(*Conn).QueryRowContext", Method, 9, ""}, + {"(*Conn).Raw", Method, 13, ""}, + {"(*DB).Begin", Method, 0, ""}, + {"(*DB).BeginTx", Method, 8, ""}, + {"(*DB).Close", Method, 0, ""}, + {"(*DB).Conn", Method, 9, ""}, + {"(*DB).Driver", Method, 0, ""}, + {"(*DB).Exec", Method, 0, ""}, + {"(*DB).ExecContext", Method, 8, ""}, + {"(*DB).Ping", Method, 1, ""}, + {"(*DB).PingContext", Method, 8, ""}, + {"(*DB).Prepare", Method, 0, ""}, + {"(*DB).PrepareContext", Method, 8, ""}, + {"(*DB).Query", Method, 0, ""}, + {"(*DB).QueryContext", Method, 8, ""}, + {"(*DB).QueryRow", Method, 0, ""}, + {"(*DB).QueryRowContext", Method, 8, ""}, + {"(*DB).SetConnMaxIdleTime", Method, 15, ""}, + {"(*DB).SetConnMaxLifetime", Method, 6, ""}, + {"(*DB).SetMaxIdleConns", Method, 1, ""}, + {"(*DB).SetMaxOpenConns", Method, 2, ""}, + {"(*DB).Stats", Method, 5, ""}, + {"(*Null).Scan", Method, 22, ""}, + {"(*NullBool).Scan", Method, 0, ""}, + {"(*NullByte).Scan", Method, 17, ""}, + {"(*NullFloat64).Scan", Method, 0, ""}, + {"(*NullInt16).Scan", Method, 17, ""}, + {"(*NullInt32).Scan", Method, 13, ""}, + {"(*NullInt64).Scan", Method, 0, ""}, + {"(*NullString).Scan", Method, 0, ""}, + {"(*NullTime).Scan", Method, 13, ""}, + {"(*Row).Err", Method, 15, ""}, + {"(*Row).Scan", Method, 0, ""}, + {"(*Rows).Close", Method, 0, ""}, + {"(*Rows).ColumnTypes", Method, 8, ""}, + {"(*Rows).Columns", Method, 0, ""}, + {"(*Rows).Err", Method, 0, ""}, + {"(*Rows).Next", Method, 0, ""}, + {"(*Rows).NextResultSet", Method, 8, ""}, + {"(*Rows).Scan", Method, 0, ""}, + {"(*Stmt).Close", Method, 0, ""}, + {"(*Stmt).Exec", Method, 0, ""}, + {"(*Stmt).ExecContext", Method, 8, ""}, + {"(*Stmt).Query", Method, 0, ""}, + {"(*Stmt).QueryContext", Method, 8, ""}, + {"(*Stmt).QueryRow", Method, 0, ""}, + {"(*Stmt).QueryRowContext", Method, 8, ""}, + {"(*Tx).Commit", Method, 0, ""}, + {"(*Tx).Exec", Method, 0, ""}, + {"(*Tx).ExecContext", Method, 8, ""}, + {"(*Tx).Prepare", Method, 0, ""}, + {"(*Tx).PrepareContext", Method, 8, ""}, + {"(*Tx).Query", Method, 0, ""}, + {"(*Tx).QueryContext", Method, 8, ""}, + {"(*Tx).QueryRow", Method, 0, ""}, + {"(*Tx).QueryRowContext", Method, 8, ""}, + {"(*Tx).Rollback", Method, 0, ""}, + {"(*Tx).Stmt", Method, 0, ""}, + {"(*Tx).StmtContext", Method, 8, ""}, + {"(IsolationLevel).String", Method, 11, ""}, + {"(Null).Value", Method, 22, ""}, + {"(NullBool).Value", Method, 0, ""}, + {"(NullByte).Value", Method, 17, ""}, + {"(NullFloat64).Value", Method, 0, ""}, + {"(NullInt16).Value", Method, 17, ""}, + {"(NullInt32).Value", Method, 13, ""}, + {"(NullInt64).Value", Method, 0, ""}, + {"(NullString).Value", Method, 0, ""}, + {"(NullTime).Value", Method, 13, ""}, + {"ColumnType", Type, 8, ""}, + {"Conn", Type, 9, ""}, + {"DB", Type, 0, ""}, + {"DBStats", Type, 5, ""}, + {"DBStats.Idle", Field, 11, ""}, + {"DBStats.InUse", Field, 11, ""}, + {"DBStats.MaxIdleClosed", Field, 11, ""}, + {"DBStats.MaxIdleTimeClosed", Field, 15, ""}, + {"DBStats.MaxLifetimeClosed", Field, 11, ""}, + {"DBStats.MaxOpenConnections", Field, 11, ""}, + {"DBStats.OpenConnections", Field, 5, ""}, + {"DBStats.WaitCount", Field, 11, ""}, + {"DBStats.WaitDuration", Field, 11, ""}, + {"Drivers", Func, 4, "func() []string"}, + {"ErrConnDone", Var, 9, ""}, + {"ErrNoRows", Var, 0, ""}, + {"ErrTxDone", Var, 0, ""}, + {"IsolationLevel", Type, 8, ""}, + {"LevelDefault", Const, 8, ""}, + {"LevelLinearizable", Const, 8, ""}, + {"LevelReadCommitted", Const, 8, ""}, + {"LevelReadUncommitted", Const, 8, ""}, + {"LevelRepeatableRead", Const, 8, ""}, + {"LevelSerializable", Const, 8, ""}, + {"LevelSnapshot", Const, 8, ""}, + {"LevelWriteCommitted", Const, 8, ""}, + {"Named", Func, 8, "func(name string, value any) NamedArg"}, + {"NamedArg", Type, 8, ""}, + {"NamedArg.Name", Field, 8, ""}, + {"NamedArg.Value", Field, 8, ""}, + {"Null", Type, 22, ""}, + {"Null.V", Field, 22, ""}, + {"Null.Valid", Field, 22, ""}, + {"NullBool", Type, 0, ""}, + {"NullBool.Bool", Field, 0, ""}, + {"NullBool.Valid", Field, 0, ""}, + {"NullByte", Type, 17, ""}, + {"NullByte.Byte", Field, 17, ""}, + {"NullByte.Valid", Field, 17, ""}, + {"NullFloat64", Type, 0, ""}, + {"NullFloat64.Float64", Field, 0, ""}, + {"NullFloat64.Valid", Field, 0, ""}, + {"NullInt16", Type, 17, ""}, + {"NullInt16.Int16", Field, 17, ""}, + {"NullInt16.Valid", Field, 17, ""}, + {"NullInt32", Type, 13, ""}, + {"NullInt32.Int32", Field, 13, ""}, + {"NullInt32.Valid", Field, 13, ""}, + {"NullInt64", Type, 0, ""}, + {"NullInt64.Int64", Field, 0, ""}, + {"NullInt64.Valid", Field, 0, ""}, + {"NullString", Type, 0, ""}, + {"NullString.String", Field, 0, ""}, + {"NullString.Valid", Field, 0, ""}, + {"NullTime", Type, 13, ""}, + {"NullTime.Time", Field, 13, ""}, + {"NullTime.Valid", Field, 13, ""}, + {"Open", Func, 0, "func(driverName string, dataSourceName string) (*DB, error)"}, + {"OpenDB", Func, 10, "func(c driver.Connector) *DB"}, + {"Out", Type, 9, ""}, + {"Out.Dest", Field, 9, ""}, + {"Out.In", Field, 9, ""}, + {"RawBytes", Type, 0, ""}, + {"Register", Func, 0, "func(name string, driver driver.Driver)"}, + {"Result", Type, 0, ""}, + {"Row", Type, 0, ""}, + {"Rows", Type, 0, ""}, + {"Scanner", Type, 0, ""}, + {"Stmt", Type, 0, ""}, + {"Tx", Type, 0, ""}, + {"TxOptions", Type, 8, ""}, + {"TxOptions.Isolation", Field, 8, ""}, + {"TxOptions.ReadOnly", Field, 8, ""}, }, "database/sql/driver": { - {"(NotNull).ConvertValue", Method, 0}, - {"(Null).ConvertValue", Method, 0}, - {"(RowsAffected).LastInsertId", Method, 0}, - {"(RowsAffected).RowsAffected", Method, 0}, - {"Bool", Var, 0}, - {"ColumnConverter", Type, 0}, - {"Conn", Type, 0}, - {"ConnBeginTx", Type, 8}, - {"ConnPrepareContext", Type, 8}, - {"Connector", Type, 10}, - {"DefaultParameterConverter", Var, 0}, - {"Driver", Type, 0}, - {"DriverContext", Type, 10}, - {"ErrBadConn", Var, 0}, - {"ErrRemoveArgument", Var, 9}, - {"ErrSkip", Var, 0}, - {"Execer", Type, 0}, - {"ExecerContext", Type, 8}, - {"Int32", Var, 0}, - {"IsScanValue", Func, 0}, - {"IsValue", Func, 0}, - {"IsolationLevel", Type, 8}, - {"NamedValue", Type, 8}, - {"NamedValue.Name", Field, 8}, - {"NamedValue.Ordinal", Field, 8}, - {"NamedValue.Value", Field, 8}, - {"NamedValueChecker", Type, 9}, - {"NotNull", Type, 0}, - {"NotNull.Converter", Field, 0}, - {"Null", Type, 0}, - {"Null.Converter", Field, 0}, - {"Pinger", Type, 8}, - {"Queryer", Type, 1}, - {"QueryerContext", Type, 8}, - {"Result", Type, 0}, - {"ResultNoRows", Var, 0}, - {"Rows", Type, 0}, - {"RowsAffected", Type, 0}, - {"RowsColumnTypeDatabaseTypeName", Type, 8}, - {"RowsColumnTypeLength", Type, 8}, - {"RowsColumnTypeNullable", Type, 8}, - {"RowsColumnTypePrecisionScale", Type, 8}, - {"RowsColumnTypeScanType", Type, 8}, - {"RowsNextResultSet", Type, 8}, - {"SessionResetter", Type, 10}, - {"Stmt", Type, 0}, - {"StmtExecContext", Type, 8}, - {"StmtQueryContext", Type, 8}, - {"String", Var, 0}, - {"Tx", Type, 0}, - {"TxOptions", Type, 8}, - {"TxOptions.Isolation", Field, 8}, - {"TxOptions.ReadOnly", Field, 8}, - {"Validator", Type, 15}, - {"Value", Type, 0}, - {"ValueConverter", Type, 0}, - {"Valuer", Type, 0}, + {"(NotNull).ConvertValue", Method, 0, ""}, + {"(Null).ConvertValue", Method, 0, ""}, + {"(RowsAffected).LastInsertId", Method, 0, ""}, + {"(RowsAffected).RowsAffected", Method, 0, ""}, + {"Bool", Var, 0, ""}, + {"ColumnConverter", Type, 0, ""}, + {"Conn", Type, 0, ""}, + {"ConnBeginTx", Type, 8, ""}, + {"ConnPrepareContext", Type, 8, ""}, + {"Connector", Type, 10, ""}, + {"DefaultParameterConverter", Var, 0, ""}, + {"Driver", Type, 0, ""}, + {"DriverContext", Type, 10, ""}, + {"ErrBadConn", Var, 0, ""}, + {"ErrRemoveArgument", Var, 9, ""}, + {"ErrSkip", Var, 0, ""}, + {"Execer", Type, 0, ""}, + {"ExecerContext", Type, 8, ""}, + {"Int32", Var, 0, ""}, + {"IsScanValue", Func, 0, "func(v any) bool"}, + {"IsValue", Func, 0, "func(v any) bool"}, + {"IsolationLevel", Type, 8, ""}, + {"NamedValue", Type, 8, ""}, + {"NamedValue.Name", Field, 8, ""}, + {"NamedValue.Ordinal", Field, 8, ""}, + {"NamedValue.Value", Field, 8, ""}, + {"NamedValueChecker", Type, 9, ""}, + {"NotNull", Type, 0, ""}, + {"NotNull.Converter", Field, 0, ""}, + {"Null", Type, 0, ""}, + {"Null.Converter", Field, 0, ""}, + {"Pinger", Type, 8, ""}, + {"Queryer", Type, 1, ""}, + {"QueryerContext", Type, 8, ""}, + {"Result", Type, 0, ""}, + {"ResultNoRows", Var, 0, ""}, + {"Rows", Type, 0, ""}, + {"RowsAffected", Type, 0, ""}, + {"RowsColumnTypeDatabaseTypeName", Type, 8, ""}, + {"RowsColumnTypeLength", Type, 8, ""}, + {"RowsColumnTypeNullable", Type, 8, ""}, + {"RowsColumnTypePrecisionScale", Type, 8, ""}, + {"RowsColumnTypeScanType", Type, 8, ""}, + {"RowsNextResultSet", Type, 8, ""}, + {"SessionResetter", Type, 10, ""}, + {"Stmt", Type, 0, ""}, + {"StmtExecContext", Type, 8, ""}, + {"StmtQueryContext", Type, 8, ""}, + {"String", Var, 0, ""}, + {"Tx", Type, 0, ""}, + {"TxOptions", Type, 8, ""}, + {"TxOptions.Isolation", Field, 8, ""}, + {"TxOptions.ReadOnly", Field, 8, ""}, + {"Validator", Type, 15, ""}, + {"Value", Type, 0, ""}, + {"ValueConverter", Type, 0, ""}, + {"Valuer", Type, 0, ""}, }, "debug/buildinfo": { - {"BuildInfo", Type, 18}, - {"Read", Func, 18}, - {"ReadFile", Func, 18}, + {"BuildInfo", Type, 18, ""}, + {"Read", Func, 18, "func(r io.ReaderAt) (*BuildInfo, error)"}, + {"ReadFile", Func, 18, "func(name string) (info *BuildInfo, err error)"}, }, "debug/dwarf": { - {"(*AddrType).Basic", Method, 0}, - {"(*AddrType).Common", Method, 0}, - {"(*AddrType).Size", Method, 0}, - {"(*AddrType).String", Method, 0}, - {"(*ArrayType).Common", Method, 0}, - {"(*ArrayType).Size", Method, 0}, - {"(*ArrayType).String", Method, 0}, - {"(*BasicType).Basic", Method, 0}, - {"(*BasicType).Common", Method, 0}, - {"(*BasicType).Size", Method, 0}, - {"(*BasicType).String", Method, 0}, - {"(*BoolType).Basic", Method, 0}, - {"(*BoolType).Common", Method, 0}, - {"(*BoolType).Size", Method, 0}, - {"(*BoolType).String", Method, 0}, - {"(*CharType).Basic", Method, 0}, - {"(*CharType).Common", Method, 0}, - {"(*CharType).Size", Method, 0}, - {"(*CharType).String", Method, 0}, - {"(*CommonType).Common", Method, 0}, - {"(*CommonType).Size", Method, 0}, - {"(*ComplexType).Basic", Method, 0}, - {"(*ComplexType).Common", Method, 0}, - {"(*ComplexType).Size", Method, 0}, - {"(*ComplexType).String", Method, 0}, - {"(*Data).AddSection", Method, 14}, - {"(*Data).AddTypes", Method, 3}, - {"(*Data).LineReader", Method, 5}, - {"(*Data).Ranges", Method, 7}, - {"(*Data).Reader", Method, 0}, - {"(*Data).Type", Method, 0}, - {"(*DotDotDotType).Common", Method, 0}, - {"(*DotDotDotType).Size", Method, 0}, - {"(*DotDotDotType).String", Method, 0}, - {"(*Entry).AttrField", Method, 5}, - {"(*Entry).Val", Method, 0}, - {"(*EnumType).Common", Method, 0}, - {"(*EnumType).Size", Method, 0}, - {"(*EnumType).String", Method, 0}, - {"(*FloatType).Basic", Method, 0}, - {"(*FloatType).Common", Method, 0}, - {"(*FloatType).Size", Method, 0}, - {"(*FloatType).String", Method, 0}, - {"(*FuncType).Common", Method, 0}, - {"(*FuncType).Size", Method, 0}, - {"(*FuncType).String", Method, 0}, - {"(*IntType).Basic", Method, 0}, - {"(*IntType).Common", Method, 0}, - {"(*IntType).Size", Method, 0}, - {"(*IntType).String", Method, 0}, - {"(*LineReader).Files", Method, 14}, - {"(*LineReader).Next", Method, 5}, - {"(*LineReader).Reset", Method, 5}, - {"(*LineReader).Seek", Method, 5}, - {"(*LineReader).SeekPC", Method, 5}, - {"(*LineReader).Tell", Method, 5}, - {"(*PtrType).Common", Method, 0}, - {"(*PtrType).Size", Method, 0}, - {"(*PtrType).String", Method, 0}, - {"(*QualType).Common", Method, 0}, - {"(*QualType).Size", Method, 0}, - {"(*QualType).String", Method, 0}, - {"(*Reader).AddressSize", Method, 5}, - {"(*Reader).ByteOrder", Method, 14}, - {"(*Reader).Next", Method, 0}, - {"(*Reader).Seek", Method, 0}, - {"(*Reader).SeekPC", Method, 7}, - {"(*Reader).SkipChildren", Method, 0}, - {"(*StructType).Common", Method, 0}, - {"(*StructType).Defn", Method, 0}, - {"(*StructType).Size", Method, 0}, - {"(*StructType).String", Method, 0}, - {"(*TypedefType).Common", Method, 0}, - {"(*TypedefType).Size", Method, 0}, - {"(*TypedefType).String", Method, 0}, - {"(*UcharType).Basic", Method, 0}, - {"(*UcharType).Common", Method, 0}, - {"(*UcharType).Size", Method, 0}, - {"(*UcharType).String", Method, 0}, - {"(*UintType).Basic", Method, 0}, - {"(*UintType).Common", Method, 0}, - {"(*UintType).Size", Method, 0}, - {"(*UintType).String", Method, 0}, - {"(*UnspecifiedType).Basic", Method, 4}, - {"(*UnspecifiedType).Common", Method, 4}, - {"(*UnspecifiedType).Size", Method, 4}, - {"(*UnspecifiedType).String", Method, 4}, - {"(*UnsupportedType).Common", Method, 13}, - {"(*UnsupportedType).Size", Method, 13}, - {"(*UnsupportedType).String", Method, 13}, - {"(*VoidType).Common", Method, 0}, - {"(*VoidType).Size", Method, 0}, - {"(*VoidType).String", Method, 0}, - {"(Attr).GoString", Method, 0}, - {"(Attr).String", Method, 0}, - {"(Class).GoString", Method, 5}, - {"(Class).String", Method, 5}, - {"(DecodeError).Error", Method, 0}, - {"(Tag).GoString", Method, 0}, - {"(Tag).String", Method, 0}, - {"AddrType", Type, 0}, - {"AddrType.BasicType", Field, 0}, - {"ArrayType", Type, 0}, - {"ArrayType.CommonType", Field, 0}, - {"ArrayType.Count", Field, 0}, - {"ArrayType.StrideBitSize", Field, 0}, - {"ArrayType.Type", Field, 0}, - {"Attr", Type, 0}, - {"AttrAbstractOrigin", Const, 0}, - {"AttrAccessibility", Const, 0}, - {"AttrAddrBase", Const, 14}, - {"AttrAddrClass", Const, 0}, - {"AttrAlignment", Const, 14}, - {"AttrAllocated", Const, 0}, - {"AttrArtificial", Const, 0}, - {"AttrAssociated", Const, 0}, - {"AttrBaseTypes", Const, 0}, - {"AttrBinaryScale", Const, 14}, - {"AttrBitOffset", Const, 0}, - {"AttrBitSize", Const, 0}, - {"AttrByteSize", Const, 0}, - {"AttrCallAllCalls", Const, 14}, - {"AttrCallAllSourceCalls", Const, 14}, - {"AttrCallAllTailCalls", Const, 14}, - {"AttrCallColumn", Const, 0}, - {"AttrCallDataLocation", Const, 14}, - {"AttrCallDataValue", Const, 14}, - {"AttrCallFile", Const, 0}, - {"AttrCallLine", Const, 0}, - {"AttrCallOrigin", Const, 14}, - {"AttrCallPC", Const, 14}, - {"AttrCallParameter", Const, 14}, - {"AttrCallReturnPC", Const, 14}, - {"AttrCallTailCall", Const, 14}, - {"AttrCallTarget", Const, 14}, - {"AttrCallTargetClobbered", Const, 14}, - {"AttrCallValue", Const, 14}, - {"AttrCalling", Const, 0}, - {"AttrCommonRef", Const, 0}, - {"AttrCompDir", Const, 0}, - {"AttrConstExpr", Const, 14}, - {"AttrConstValue", Const, 0}, - {"AttrContainingType", Const, 0}, - {"AttrCount", Const, 0}, - {"AttrDataBitOffset", Const, 14}, - {"AttrDataLocation", Const, 0}, - {"AttrDataMemberLoc", Const, 0}, - {"AttrDecimalScale", Const, 14}, - {"AttrDecimalSign", Const, 14}, - {"AttrDeclColumn", Const, 0}, - {"AttrDeclFile", Const, 0}, - {"AttrDeclLine", Const, 0}, - {"AttrDeclaration", Const, 0}, - {"AttrDefaultValue", Const, 0}, - {"AttrDefaulted", Const, 14}, - {"AttrDeleted", Const, 14}, - {"AttrDescription", Const, 0}, - {"AttrDigitCount", Const, 14}, - {"AttrDiscr", Const, 0}, - {"AttrDiscrList", Const, 0}, - {"AttrDiscrValue", Const, 0}, - {"AttrDwoName", Const, 14}, - {"AttrElemental", Const, 14}, - {"AttrEncoding", Const, 0}, - {"AttrEndianity", Const, 14}, - {"AttrEntrypc", Const, 0}, - {"AttrEnumClass", Const, 14}, - {"AttrExplicit", Const, 14}, - {"AttrExportSymbols", Const, 14}, - {"AttrExtension", Const, 0}, - {"AttrExternal", Const, 0}, - {"AttrFrameBase", Const, 0}, - {"AttrFriend", Const, 0}, - {"AttrHighpc", Const, 0}, - {"AttrIdentifierCase", Const, 0}, - {"AttrImport", Const, 0}, - {"AttrInline", Const, 0}, - {"AttrIsOptional", Const, 0}, - {"AttrLanguage", Const, 0}, - {"AttrLinkageName", Const, 14}, - {"AttrLocation", Const, 0}, - {"AttrLoclistsBase", Const, 14}, - {"AttrLowerBound", Const, 0}, - {"AttrLowpc", Const, 0}, - {"AttrMacroInfo", Const, 0}, - {"AttrMacros", Const, 14}, - {"AttrMainSubprogram", Const, 14}, - {"AttrMutable", Const, 14}, - {"AttrName", Const, 0}, - {"AttrNamelistItem", Const, 0}, - {"AttrNoreturn", Const, 14}, - {"AttrObjectPointer", Const, 14}, - {"AttrOrdering", Const, 0}, - {"AttrPictureString", Const, 14}, - {"AttrPriority", Const, 0}, - {"AttrProducer", Const, 0}, - {"AttrPrototyped", Const, 0}, - {"AttrPure", Const, 14}, - {"AttrRanges", Const, 0}, - {"AttrRank", Const, 14}, - {"AttrRecursive", Const, 14}, - {"AttrReference", Const, 14}, - {"AttrReturnAddr", Const, 0}, - {"AttrRnglistsBase", Const, 14}, - {"AttrRvalueReference", Const, 14}, - {"AttrSegment", Const, 0}, - {"AttrSibling", Const, 0}, - {"AttrSignature", Const, 14}, - {"AttrSmall", Const, 14}, - {"AttrSpecification", Const, 0}, - {"AttrStartScope", Const, 0}, - {"AttrStaticLink", Const, 0}, - {"AttrStmtList", Const, 0}, - {"AttrStrOffsetsBase", Const, 14}, - {"AttrStride", Const, 0}, - {"AttrStrideSize", Const, 0}, - {"AttrStringLength", Const, 0}, - {"AttrStringLengthBitSize", Const, 14}, - {"AttrStringLengthByteSize", Const, 14}, - {"AttrThreadsScaled", Const, 14}, - {"AttrTrampoline", Const, 0}, - {"AttrType", Const, 0}, - {"AttrUpperBound", Const, 0}, - {"AttrUseLocation", Const, 0}, - {"AttrUseUTF8", Const, 0}, - {"AttrVarParam", Const, 0}, - {"AttrVirtuality", Const, 0}, - {"AttrVisibility", Const, 0}, - {"AttrVtableElemLoc", Const, 0}, - {"BasicType", Type, 0}, - {"BasicType.BitOffset", Field, 0}, - {"BasicType.BitSize", Field, 0}, - {"BasicType.CommonType", Field, 0}, - {"BasicType.DataBitOffset", Field, 18}, - {"BoolType", Type, 0}, - {"BoolType.BasicType", Field, 0}, - {"CharType", Type, 0}, - {"CharType.BasicType", Field, 0}, - {"Class", Type, 5}, - {"ClassAddrPtr", Const, 14}, - {"ClassAddress", Const, 5}, - {"ClassBlock", Const, 5}, - {"ClassConstant", Const, 5}, - {"ClassExprLoc", Const, 5}, - {"ClassFlag", Const, 5}, - {"ClassLinePtr", Const, 5}, - {"ClassLocList", Const, 14}, - {"ClassLocListPtr", Const, 5}, - {"ClassMacPtr", Const, 5}, - {"ClassRangeListPtr", Const, 5}, - {"ClassReference", Const, 5}, - {"ClassReferenceAlt", Const, 5}, - {"ClassReferenceSig", Const, 5}, - {"ClassRngList", Const, 14}, - {"ClassRngListsPtr", Const, 14}, - {"ClassStrOffsetsPtr", Const, 14}, - {"ClassString", Const, 5}, - {"ClassStringAlt", Const, 5}, - {"ClassUnknown", Const, 6}, - {"CommonType", Type, 0}, - {"CommonType.ByteSize", Field, 0}, - {"CommonType.Name", Field, 0}, - {"ComplexType", Type, 0}, - {"ComplexType.BasicType", Field, 0}, - {"Data", Type, 0}, - {"DecodeError", Type, 0}, - {"DecodeError.Err", Field, 0}, - {"DecodeError.Name", Field, 0}, - {"DecodeError.Offset", Field, 0}, - {"DotDotDotType", Type, 0}, - {"DotDotDotType.CommonType", Field, 0}, - {"Entry", Type, 0}, - {"Entry.Children", Field, 0}, - {"Entry.Field", Field, 0}, - {"Entry.Offset", Field, 0}, - {"Entry.Tag", Field, 0}, - {"EnumType", Type, 0}, - {"EnumType.CommonType", Field, 0}, - {"EnumType.EnumName", Field, 0}, - {"EnumType.Val", Field, 0}, - {"EnumValue", Type, 0}, - {"EnumValue.Name", Field, 0}, - {"EnumValue.Val", Field, 0}, - {"ErrUnknownPC", Var, 5}, - {"Field", Type, 0}, - {"Field.Attr", Field, 0}, - {"Field.Class", Field, 5}, - {"Field.Val", Field, 0}, - {"FloatType", Type, 0}, - {"FloatType.BasicType", Field, 0}, - {"FuncType", Type, 0}, - {"FuncType.CommonType", Field, 0}, - {"FuncType.ParamType", Field, 0}, - {"FuncType.ReturnType", Field, 0}, - {"IntType", Type, 0}, - {"IntType.BasicType", Field, 0}, - {"LineEntry", Type, 5}, - {"LineEntry.Address", Field, 5}, - {"LineEntry.BasicBlock", Field, 5}, - {"LineEntry.Column", Field, 5}, - {"LineEntry.Discriminator", Field, 5}, - {"LineEntry.EndSequence", Field, 5}, - {"LineEntry.EpilogueBegin", Field, 5}, - {"LineEntry.File", Field, 5}, - {"LineEntry.ISA", Field, 5}, - {"LineEntry.IsStmt", Field, 5}, - {"LineEntry.Line", Field, 5}, - {"LineEntry.OpIndex", Field, 5}, - {"LineEntry.PrologueEnd", Field, 5}, - {"LineFile", Type, 5}, - {"LineFile.Length", Field, 5}, - {"LineFile.Mtime", Field, 5}, - {"LineFile.Name", Field, 5}, - {"LineReader", Type, 5}, - {"LineReaderPos", Type, 5}, - {"New", Func, 0}, - {"Offset", Type, 0}, - {"PtrType", Type, 0}, - {"PtrType.CommonType", Field, 0}, - {"PtrType.Type", Field, 0}, - {"QualType", Type, 0}, - {"QualType.CommonType", Field, 0}, - {"QualType.Qual", Field, 0}, - {"QualType.Type", Field, 0}, - {"Reader", Type, 0}, - {"StructField", Type, 0}, - {"StructField.BitOffset", Field, 0}, - {"StructField.BitSize", Field, 0}, - {"StructField.ByteOffset", Field, 0}, - {"StructField.ByteSize", Field, 0}, - {"StructField.DataBitOffset", Field, 18}, - {"StructField.Name", Field, 0}, - {"StructField.Type", Field, 0}, - {"StructType", Type, 0}, - {"StructType.CommonType", Field, 0}, - {"StructType.Field", Field, 0}, - {"StructType.Incomplete", Field, 0}, - {"StructType.Kind", Field, 0}, - {"StructType.StructName", Field, 0}, - {"Tag", Type, 0}, - {"TagAccessDeclaration", Const, 0}, - {"TagArrayType", Const, 0}, - {"TagAtomicType", Const, 14}, - {"TagBaseType", Const, 0}, - {"TagCallSite", Const, 14}, - {"TagCallSiteParameter", Const, 14}, - {"TagCatchDwarfBlock", Const, 0}, - {"TagClassType", Const, 0}, - {"TagCoarrayType", Const, 14}, - {"TagCommonDwarfBlock", Const, 0}, - {"TagCommonInclusion", Const, 0}, - {"TagCompileUnit", Const, 0}, - {"TagCondition", Const, 3}, - {"TagConstType", Const, 0}, - {"TagConstant", Const, 0}, - {"TagDwarfProcedure", Const, 0}, - {"TagDynamicType", Const, 14}, - {"TagEntryPoint", Const, 0}, - {"TagEnumerationType", Const, 0}, - {"TagEnumerator", Const, 0}, - {"TagFileType", Const, 0}, - {"TagFormalParameter", Const, 0}, - {"TagFriend", Const, 0}, - {"TagGenericSubrange", Const, 14}, - {"TagImmutableType", Const, 14}, - {"TagImportedDeclaration", Const, 0}, - {"TagImportedModule", Const, 0}, - {"TagImportedUnit", Const, 0}, - {"TagInheritance", Const, 0}, - {"TagInlinedSubroutine", Const, 0}, - {"TagInterfaceType", Const, 0}, - {"TagLabel", Const, 0}, - {"TagLexDwarfBlock", Const, 0}, - {"TagMember", Const, 0}, - {"TagModule", Const, 0}, - {"TagMutableType", Const, 0}, - {"TagNamelist", Const, 0}, - {"TagNamelistItem", Const, 0}, - {"TagNamespace", Const, 0}, - {"TagPackedType", Const, 0}, - {"TagPartialUnit", Const, 0}, - {"TagPointerType", Const, 0}, - {"TagPtrToMemberType", Const, 0}, - {"TagReferenceType", Const, 0}, - {"TagRestrictType", Const, 0}, - {"TagRvalueReferenceType", Const, 3}, - {"TagSetType", Const, 0}, - {"TagSharedType", Const, 3}, - {"TagSkeletonUnit", Const, 14}, - {"TagStringType", Const, 0}, - {"TagStructType", Const, 0}, - {"TagSubprogram", Const, 0}, - {"TagSubrangeType", Const, 0}, - {"TagSubroutineType", Const, 0}, - {"TagTemplateAlias", Const, 3}, - {"TagTemplateTypeParameter", Const, 0}, - {"TagTemplateValueParameter", Const, 0}, - {"TagThrownType", Const, 0}, - {"TagTryDwarfBlock", Const, 0}, - {"TagTypeUnit", Const, 3}, - {"TagTypedef", Const, 0}, - {"TagUnionType", Const, 0}, - {"TagUnspecifiedParameters", Const, 0}, - {"TagUnspecifiedType", Const, 0}, - {"TagVariable", Const, 0}, - {"TagVariant", Const, 0}, - {"TagVariantPart", Const, 0}, - {"TagVolatileType", Const, 0}, - {"TagWithStmt", Const, 0}, - {"Type", Type, 0}, - {"TypedefType", Type, 0}, - {"TypedefType.CommonType", Field, 0}, - {"TypedefType.Type", Field, 0}, - {"UcharType", Type, 0}, - {"UcharType.BasicType", Field, 0}, - {"UintType", Type, 0}, - {"UintType.BasicType", Field, 0}, - {"UnspecifiedType", Type, 4}, - {"UnspecifiedType.BasicType", Field, 4}, - {"UnsupportedType", Type, 13}, - {"UnsupportedType.CommonType", Field, 13}, - {"UnsupportedType.Tag", Field, 13}, - {"VoidType", Type, 0}, - {"VoidType.CommonType", Field, 0}, + {"(*AddrType).Basic", Method, 0, ""}, + {"(*AddrType).Common", Method, 0, ""}, + {"(*AddrType).Size", Method, 0, ""}, + {"(*AddrType).String", Method, 0, ""}, + {"(*ArrayType).Common", Method, 0, ""}, + {"(*ArrayType).Size", Method, 0, ""}, + {"(*ArrayType).String", Method, 0, ""}, + {"(*BasicType).Basic", Method, 0, ""}, + {"(*BasicType).Common", Method, 0, ""}, + {"(*BasicType).Size", Method, 0, ""}, + {"(*BasicType).String", Method, 0, ""}, + {"(*BoolType).Basic", Method, 0, ""}, + {"(*BoolType).Common", Method, 0, ""}, + {"(*BoolType).Size", Method, 0, ""}, + {"(*BoolType).String", Method, 0, ""}, + {"(*CharType).Basic", Method, 0, ""}, + {"(*CharType).Common", Method, 0, ""}, + {"(*CharType).Size", Method, 0, ""}, + {"(*CharType).String", Method, 0, ""}, + {"(*CommonType).Common", Method, 0, ""}, + {"(*CommonType).Size", Method, 0, ""}, + {"(*ComplexType).Basic", Method, 0, ""}, + {"(*ComplexType).Common", Method, 0, ""}, + {"(*ComplexType).Size", Method, 0, ""}, + {"(*ComplexType).String", Method, 0, ""}, + {"(*Data).AddSection", Method, 14, ""}, + {"(*Data).AddTypes", Method, 3, ""}, + {"(*Data).LineReader", Method, 5, ""}, + {"(*Data).Ranges", Method, 7, ""}, + {"(*Data).Reader", Method, 0, ""}, + {"(*Data).Type", Method, 0, ""}, + {"(*DotDotDotType).Common", Method, 0, ""}, + {"(*DotDotDotType).Size", Method, 0, ""}, + {"(*DotDotDotType).String", Method, 0, ""}, + {"(*Entry).AttrField", Method, 5, ""}, + {"(*Entry).Val", Method, 0, ""}, + {"(*EnumType).Common", Method, 0, ""}, + {"(*EnumType).Size", Method, 0, ""}, + {"(*EnumType).String", Method, 0, ""}, + {"(*FloatType).Basic", Method, 0, ""}, + {"(*FloatType).Common", Method, 0, ""}, + {"(*FloatType).Size", Method, 0, ""}, + {"(*FloatType).String", Method, 0, ""}, + {"(*FuncType).Common", Method, 0, ""}, + {"(*FuncType).Size", Method, 0, ""}, + {"(*FuncType).String", Method, 0, ""}, + {"(*IntType).Basic", Method, 0, ""}, + {"(*IntType).Common", Method, 0, ""}, + {"(*IntType).Size", Method, 0, ""}, + {"(*IntType).String", Method, 0, ""}, + {"(*LineReader).Files", Method, 14, ""}, + {"(*LineReader).Next", Method, 5, ""}, + {"(*LineReader).Reset", Method, 5, ""}, + {"(*LineReader).Seek", Method, 5, ""}, + {"(*LineReader).SeekPC", Method, 5, ""}, + {"(*LineReader).Tell", Method, 5, ""}, + {"(*PtrType).Common", Method, 0, ""}, + {"(*PtrType).Size", Method, 0, ""}, + {"(*PtrType).String", Method, 0, ""}, + {"(*QualType).Common", Method, 0, ""}, + {"(*QualType).Size", Method, 0, ""}, + {"(*QualType).String", Method, 0, ""}, + {"(*Reader).AddressSize", Method, 5, ""}, + {"(*Reader).ByteOrder", Method, 14, ""}, + {"(*Reader).Next", Method, 0, ""}, + {"(*Reader).Seek", Method, 0, ""}, + {"(*Reader).SeekPC", Method, 7, ""}, + {"(*Reader).SkipChildren", Method, 0, ""}, + {"(*StructType).Common", Method, 0, ""}, + {"(*StructType).Defn", Method, 0, ""}, + {"(*StructType).Size", Method, 0, ""}, + {"(*StructType).String", Method, 0, ""}, + {"(*TypedefType).Common", Method, 0, ""}, + {"(*TypedefType).Size", Method, 0, ""}, + {"(*TypedefType).String", Method, 0, ""}, + {"(*UcharType).Basic", Method, 0, ""}, + {"(*UcharType).Common", Method, 0, ""}, + {"(*UcharType).Size", Method, 0, ""}, + {"(*UcharType).String", Method, 0, ""}, + {"(*UintType).Basic", Method, 0, ""}, + {"(*UintType).Common", Method, 0, ""}, + {"(*UintType).Size", Method, 0, ""}, + {"(*UintType).String", Method, 0, ""}, + {"(*UnspecifiedType).Basic", Method, 4, ""}, + {"(*UnspecifiedType).Common", Method, 4, ""}, + {"(*UnspecifiedType).Size", Method, 4, ""}, + {"(*UnspecifiedType).String", Method, 4, ""}, + {"(*UnsupportedType).Common", Method, 13, ""}, + {"(*UnsupportedType).Size", Method, 13, ""}, + {"(*UnsupportedType).String", Method, 13, ""}, + {"(*VoidType).Common", Method, 0, ""}, + {"(*VoidType).Size", Method, 0, ""}, + {"(*VoidType).String", Method, 0, ""}, + {"(Attr).GoString", Method, 0, ""}, + {"(Attr).String", Method, 0, ""}, + {"(Class).GoString", Method, 5, ""}, + {"(Class).String", Method, 5, ""}, + {"(DecodeError).Error", Method, 0, ""}, + {"(Tag).GoString", Method, 0, ""}, + {"(Tag).String", Method, 0, ""}, + {"AddrType", Type, 0, ""}, + {"AddrType.BasicType", Field, 0, ""}, + {"ArrayType", Type, 0, ""}, + {"ArrayType.CommonType", Field, 0, ""}, + {"ArrayType.Count", Field, 0, ""}, + {"ArrayType.StrideBitSize", Field, 0, ""}, + {"ArrayType.Type", Field, 0, ""}, + {"Attr", Type, 0, ""}, + {"AttrAbstractOrigin", Const, 0, ""}, + {"AttrAccessibility", Const, 0, ""}, + {"AttrAddrBase", Const, 14, ""}, + {"AttrAddrClass", Const, 0, ""}, + {"AttrAlignment", Const, 14, ""}, + {"AttrAllocated", Const, 0, ""}, + {"AttrArtificial", Const, 0, ""}, + {"AttrAssociated", Const, 0, ""}, + {"AttrBaseTypes", Const, 0, ""}, + {"AttrBinaryScale", Const, 14, ""}, + {"AttrBitOffset", Const, 0, ""}, + {"AttrBitSize", Const, 0, ""}, + {"AttrByteSize", Const, 0, ""}, + {"AttrCallAllCalls", Const, 14, ""}, + {"AttrCallAllSourceCalls", Const, 14, ""}, + {"AttrCallAllTailCalls", Const, 14, ""}, + {"AttrCallColumn", Const, 0, ""}, + {"AttrCallDataLocation", Const, 14, ""}, + {"AttrCallDataValue", Const, 14, ""}, + {"AttrCallFile", Const, 0, ""}, + {"AttrCallLine", Const, 0, ""}, + {"AttrCallOrigin", Const, 14, ""}, + {"AttrCallPC", Const, 14, ""}, + {"AttrCallParameter", Const, 14, ""}, + {"AttrCallReturnPC", Const, 14, ""}, + {"AttrCallTailCall", Const, 14, ""}, + {"AttrCallTarget", Const, 14, ""}, + {"AttrCallTargetClobbered", Const, 14, ""}, + {"AttrCallValue", Const, 14, ""}, + {"AttrCalling", Const, 0, ""}, + {"AttrCommonRef", Const, 0, ""}, + {"AttrCompDir", Const, 0, ""}, + {"AttrConstExpr", Const, 14, ""}, + {"AttrConstValue", Const, 0, ""}, + {"AttrContainingType", Const, 0, ""}, + {"AttrCount", Const, 0, ""}, + {"AttrDataBitOffset", Const, 14, ""}, + {"AttrDataLocation", Const, 0, ""}, + {"AttrDataMemberLoc", Const, 0, ""}, + {"AttrDecimalScale", Const, 14, ""}, + {"AttrDecimalSign", Const, 14, ""}, + {"AttrDeclColumn", Const, 0, ""}, + {"AttrDeclFile", Const, 0, ""}, + {"AttrDeclLine", Const, 0, ""}, + {"AttrDeclaration", Const, 0, ""}, + {"AttrDefaultValue", Const, 0, ""}, + {"AttrDefaulted", Const, 14, ""}, + {"AttrDeleted", Const, 14, ""}, + {"AttrDescription", Const, 0, ""}, + {"AttrDigitCount", Const, 14, ""}, + {"AttrDiscr", Const, 0, ""}, + {"AttrDiscrList", Const, 0, ""}, + {"AttrDiscrValue", Const, 0, ""}, + {"AttrDwoName", Const, 14, ""}, + {"AttrElemental", Const, 14, ""}, + {"AttrEncoding", Const, 0, ""}, + {"AttrEndianity", Const, 14, ""}, + {"AttrEntrypc", Const, 0, ""}, + {"AttrEnumClass", Const, 14, ""}, + {"AttrExplicit", Const, 14, ""}, + {"AttrExportSymbols", Const, 14, ""}, + {"AttrExtension", Const, 0, ""}, + {"AttrExternal", Const, 0, ""}, + {"AttrFrameBase", Const, 0, ""}, + {"AttrFriend", Const, 0, ""}, + {"AttrHighpc", Const, 0, ""}, + {"AttrIdentifierCase", Const, 0, ""}, + {"AttrImport", Const, 0, ""}, + {"AttrInline", Const, 0, ""}, + {"AttrIsOptional", Const, 0, ""}, + {"AttrLanguage", Const, 0, ""}, + {"AttrLinkageName", Const, 14, ""}, + {"AttrLocation", Const, 0, ""}, + {"AttrLoclistsBase", Const, 14, ""}, + {"AttrLowerBound", Const, 0, ""}, + {"AttrLowpc", Const, 0, ""}, + {"AttrMacroInfo", Const, 0, ""}, + {"AttrMacros", Const, 14, ""}, + {"AttrMainSubprogram", Const, 14, ""}, + {"AttrMutable", Const, 14, ""}, + {"AttrName", Const, 0, ""}, + {"AttrNamelistItem", Const, 0, ""}, + {"AttrNoreturn", Const, 14, ""}, + {"AttrObjectPointer", Const, 14, ""}, + {"AttrOrdering", Const, 0, ""}, + {"AttrPictureString", Const, 14, ""}, + {"AttrPriority", Const, 0, ""}, + {"AttrProducer", Const, 0, ""}, + {"AttrPrototyped", Const, 0, ""}, + {"AttrPure", Const, 14, ""}, + {"AttrRanges", Const, 0, ""}, + {"AttrRank", Const, 14, ""}, + {"AttrRecursive", Const, 14, ""}, + {"AttrReference", Const, 14, ""}, + {"AttrReturnAddr", Const, 0, ""}, + {"AttrRnglistsBase", Const, 14, ""}, + {"AttrRvalueReference", Const, 14, ""}, + {"AttrSegment", Const, 0, ""}, + {"AttrSibling", Const, 0, ""}, + {"AttrSignature", Const, 14, ""}, + {"AttrSmall", Const, 14, ""}, + {"AttrSpecification", Const, 0, ""}, + {"AttrStartScope", Const, 0, ""}, + {"AttrStaticLink", Const, 0, ""}, + {"AttrStmtList", Const, 0, ""}, + {"AttrStrOffsetsBase", Const, 14, ""}, + {"AttrStride", Const, 0, ""}, + {"AttrStrideSize", Const, 0, ""}, + {"AttrStringLength", Const, 0, ""}, + {"AttrStringLengthBitSize", Const, 14, ""}, + {"AttrStringLengthByteSize", Const, 14, ""}, + {"AttrThreadsScaled", Const, 14, ""}, + {"AttrTrampoline", Const, 0, ""}, + {"AttrType", Const, 0, ""}, + {"AttrUpperBound", Const, 0, ""}, + {"AttrUseLocation", Const, 0, ""}, + {"AttrUseUTF8", Const, 0, ""}, + {"AttrVarParam", Const, 0, ""}, + {"AttrVirtuality", Const, 0, ""}, + {"AttrVisibility", Const, 0, ""}, + {"AttrVtableElemLoc", Const, 0, ""}, + {"BasicType", Type, 0, ""}, + {"BasicType.BitOffset", Field, 0, ""}, + {"BasicType.BitSize", Field, 0, ""}, + {"BasicType.CommonType", Field, 0, ""}, + {"BasicType.DataBitOffset", Field, 18, ""}, + {"BoolType", Type, 0, ""}, + {"BoolType.BasicType", Field, 0, ""}, + {"CharType", Type, 0, ""}, + {"CharType.BasicType", Field, 0, ""}, + {"Class", Type, 5, ""}, + {"ClassAddrPtr", Const, 14, ""}, + {"ClassAddress", Const, 5, ""}, + {"ClassBlock", Const, 5, ""}, + {"ClassConstant", Const, 5, ""}, + {"ClassExprLoc", Const, 5, ""}, + {"ClassFlag", Const, 5, ""}, + {"ClassLinePtr", Const, 5, ""}, + {"ClassLocList", Const, 14, ""}, + {"ClassLocListPtr", Const, 5, ""}, + {"ClassMacPtr", Const, 5, ""}, + {"ClassRangeListPtr", Const, 5, ""}, + {"ClassReference", Const, 5, ""}, + {"ClassReferenceAlt", Const, 5, ""}, + {"ClassReferenceSig", Const, 5, ""}, + {"ClassRngList", Const, 14, ""}, + {"ClassRngListsPtr", Const, 14, ""}, + {"ClassStrOffsetsPtr", Const, 14, ""}, + {"ClassString", Const, 5, ""}, + {"ClassStringAlt", Const, 5, ""}, + {"ClassUnknown", Const, 6, ""}, + {"CommonType", Type, 0, ""}, + {"CommonType.ByteSize", Field, 0, ""}, + {"CommonType.Name", Field, 0, ""}, + {"ComplexType", Type, 0, ""}, + {"ComplexType.BasicType", Field, 0, ""}, + {"Data", Type, 0, ""}, + {"DecodeError", Type, 0, ""}, + {"DecodeError.Err", Field, 0, ""}, + {"DecodeError.Name", Field, 0, ""}, + {"DecodeError.Offset", Field, 0, ""}, + {"DotDotDotType", Type, 0, ""}, + {"DotDotDotType.CommonType", Field, 0, ""}, + {"Entry", Type, 0, ""}, + {"Entry.Children", Field, 0, ""}, + {"Entry.Field", Field, 0, ""}, + {"Entry.Offset", Field, 0, ""}, + {"Entry.Tag", Field, 0, ""}, + {"EnumType", Type, 0, ""}, + {"EnumType.CommonType", Field, 0, ""}, + {"EnumType.EnumName", Field, 0, ""}, + {"EnumType.Val", Field, 0, ""}, + {"EnumValue", Type, 0, ""}, + {"EnumValue.Name", Field, 0, ""}, + {"EnumValue.Val", Field, 0, ""}, + {"ErrUnknownPC", Var, 5, ""}, + {"Field", Type, 0, ""}, + {"Field.Attr", Field, 0, ""}, + {"Field.Class", Field, 5, ""}, + {"Field.Val", Field, 0, ""}, + {"FloatType", Type, 0, ""}, + {"FloatType.BasicType", Field, 0, ""}, + {"FuncType", Type, 0, ""}, + {"FuncType.CommonType", Field, 0, ""}, + {"FuncType.ParamType", Field, 0, ""}, + {"FuncType.ReturnType", Field, 0, ""}, + {"IntType", Type, 0, ""}, + {"IntType.BasicType", Field, 0, ""}, + {"LineEntry", Type, 5, ""}, + {"LineEntry.Address", Field, 5, ""}, + {"LineEntry.BasicBlock", Field, 5, ""}, + {"LineEntry.Column", Field, 5, ""}, + {"LineEntry.Discriminator", Field, 5, ""}, + {"LineEntry.EndSequence", Field, 5, ""}, + {"LineEntry.EpilogueBegin", Field, 5, ""}, + {"LineEntry.File", Field, 5, ""}, + {"LineEntry.ISA", Field, 5, ""}, + {"LineEntry.IsStmt", Field, 5, ""}, + {"LineEntry.Line", Field, 5, ""}, + {"LineEntry.OpIndex", Field, 5, ""}, + {"LineEntry.PrologueEnd", Field, 5, ""}, + {"LineFile", Type, 5, ""}, + {"LineFile.Length", Field, 5, ""}, + {"LineFile.Mtime", Field, 5, ""}, + {"LineFile.Name", Field, 5, ""}, + {"LineReader", Type, 5, ""}, + {"LineReaderPos", Type, 5, ""}, + {"New", Func, 0, "func(abbrev []byte, aranges []byte, frame []byte, info []byte, line []byte, pubnames []byte, ranges []byte, str []byte) (*Data, error)"}, + {"Offset", Type, 0, ""}, + {"PtrType", Type, 0, ""}, + {"PtrType.CommonType", Field, 0, ""}, + {"PtrType.Type", Field, 0, ""}, + {"QualType", Type, 0, ""}, + {"QualType.CommonType", Field, 0, ""}, + {"QualType.Qual", Field, 0, ""}, + {"QualType.Type", Field, 0, ""}, + {"Reader", Type, 0, ""}, + {"StructField", Type, 0, ""}, + {"StructField.BitOffset", Field, 0, ""}, + {"StructField.BitSize", Field, 0, ""}, + {"StructField.ByteOffset", Field, 0, ""}, + {"StructField.ByteSize", Field, 0, ""}, + {"StructField.DataBitOffset", Field, 18, ""}, + {"StructField.Name", Field, 0, ""}, + {"StructField.Type", Field, 0, ""}, + {"StructType", Type, 0, ""}, + {"StructType.CommonType", Field, 0, ""}, + {"StructType.Field", Field, 0, ""}, + {"StructType.Incomplete", Field, 0, ""}, + {"StructType.Kind", Field, 0, ""}, + {"StructType.StructName", Field, 0, ""}, + {"Tag", Type, 0, ""}, + {"TagAccessDeclaration", Const, 0, ""}, + {"TagArrayType", Const, 0, ""}, + {"TagAtomicType", Const, 14, ""}, + {"TagBaseType", Const, 0, ""}, + {"TagCallSite", Const, 14, ""}, + {"TagCallSiteParameter", Const, 14, ""}, + {"TagCatchDwarfBlock", Const, 0, ""}, + {"TagClassType", Const, 0, ""}, + {"TagCoarrayType", Const, 14, ""}, + {"TagCommonDwarfBlock", Const, 0, ""}, + {"TagCommonInclusion", Const, 0, ""}, + {"TagCompileUnit", Const, 0, ""}, + {"TagCondition", Const, 3, ""}, + {"TagConstType", Const, 0, ""}, + {"TagConstant", Const, 0, ""}, + {"TagDwarfProcedure", Const, 0, ""}, + {"TagDynamicType", Const, 14, ""}, + {"TagEntryPoint", Const, 0, ""}, + {"TagEnumerationType", Const, 0, ""}, + {"TagEnumerator", Const, 0, ""}, + {"TagFileType", Const, 0, ""}, + {"TagFormalParameter", Const, 0, ""}, + {"TagFriend", Const, 0, ""}, + {"TagGenericSubrange", Const, 14, ""}, + {"TagImmutableType", Const, 14, ""}, + {"TagImportedDeclaration", Const, 0, ""}, + {"TagImportedModule", Const, 0, ""}, + {"TagImportedUnit", Const, 0, ""}, + {"TagInheritance", Const, 0, ""}, + {"TagInlinedSubroutine", Const, 0, ""}, + {"TagInterfaceType", Const, 0, ""}, + {"TagLabel", Const, 0, ""}, + {"TagLexDwarfBlock", Const, 0, ""}, + {"TagMember", Const, 0, ""}, + {"TagModule", Const, 0, ""}, + {"TagMutableType", Const, 0, ""}, + {"TagNamelist", Const, 0, ""}, + {"TagNamelistItem", Const, 0, ""}, + {"TagNamespace", Const, 0, ""}, + {"TagPackedType", Const, 0, ""}, + {"TagPartialUnit", Const, 0, ""}, + {"TagPointerType", Const, 0, ""}, + {"TagPtrToMemberType", Const, 0, ""}, + {"TagReferenceType", Const, 0, ""}, + {"TagRestrictType", Const, 0, ""}, + {"TagRvalueReferenceType", Const, 3, ""}, + {"TagSetType", Const, 0, ""}, + {"TagSharedType", Const, 3, ""}, + {"TagSkeletonUnit", Const, 14, ""}, + {"TagStringType", Const, 0, ""}, + {"TagStructType", Const, 0, ""}, + {"TagSubprogram", Const, 0, ""}, + {"TagSubrangeType", Const, 0, ""}, + {"TagSubroutineType", Const, 0, ""}, + {"TagTemplateAlias", Const, 3, ""}, + {"TagTemplateTypeParameter", Const, 0, ""}, + {"TagTemplateValueParameter", Const, 0, ""}, + {"TagThrownType", Const, 0, ""}, + {"TagTryDwarfBlock", Const, 0, ""}, + {"TagTypeUnit", Const, 3, ""}, + {"TagTypedef", Const, 0, ""}, + {"TagUnionType", Const, 0, ""}, + {"TagUnspecifiedParameters", Const, 0, ""}, + {"TagUnspecifiedType", Const, 0, ""}, + {"TagVariable", Const, 0, ""}, + {"TagVariant", Const, 0, ""}, + {"TagVariantPart", Const, 0, ""}, + {"TagVolatileType", Const, 0, ""}, + {"TagWithStmt", Const, 0, ""}, + {"Type", Type, 0, ""}, + {"TypedefType", Type, 0, ""}, + {"TypedefType.CommonType", Field, 0, ""}, + {"TypedefType.Type", Field, 0, ""}, + {"UcharType", Type, 0, ""}, + {"UcharType.BasicType", Field, 0, ""}, + {"UintType", Type, 0, ""}, + {"UintType.BasicType", Field, 0, ""}, + {"UnspecifiedType", Type, 4, ""}, + {"UnspecifiedType.BasicType", Field, 4, ""}, + {"UnsupportedType", Type, 13, ""}, + {"UnsupportedType.CommonType", Field, 13, ""}, + {"UnsupportedType.Tag", Field, 13, ""}, + {"VoidType", Type, 0, ""}, + {"VoidType.CommonType", Field, 0, ""}, }, "debug/elf": { - {"(*File).Close", Method, 0}, - {"(*File).DWARF", Method, 0}, - {"(*File).DynString", Method, 1}, - {"(*File).DynValue", Method, 21}, - {"(*File).DynamicSymbols", Method, 4}, - {"(*File).DynamicVersionNeeds", Method, 24}, - {"(*File).DynamicVersions", Method, 24}, - {"(*File).ImportedLibraries", Method, 0}, - {"(*File).ImportedSymbols", Method, 0}, - {"(*File).Section", Method, 0}, - {"(*File).SectionByType", Method, 0}, - {"(*File).Symbols", Method, 0}, - {"(*FormatError).Error", Method, 0}, - {"(*Prog).Open", Method, 0}, - {"(*Section).Data", Method, 0}, - {"(*Section).Open", Method, 0}, - {"(Class).GoString", Method, 0}, - {"(Class).String", Method, 0}, - {"(CompressionType).GoString", Method, 6}, - {"(CompressionType).String", Method, 6}, - {"(Data).GoString", Method, 0}, - {"(Data).String", Method, 0}, - {"(DynFlag).GoString", Method, 0}, - {"(DynFlag).String", Method, 0}, - {"(DynFlag1).GoString", Method, 21}, - {"(DynFlag1).String", Method, 21}, - {"(DynTag).GoString", Method, 0}, - {"(DynTag).String", Method, 0}, - {"(Machine).GoString", Method, 0}, - {"(Machine).String", Method, 0}, - {"(NType).GoString", Method, 0}, - {"(NType).String", Method, 0}, - {"(OSABI).GoString", Method, 0}, - {"(OSABI).String", Method, 0}, - {"(Prog).ReadAt", Method, 0}, - {"(ProgFlag).GoString", Method, 0}, - {"(ProgFlag).String", Method, 0}, - {"(ProgType).GoString", Method, 0}, - {"(ProgType).String", Method, 0}, - {"(R_386).GoString", Method, 0}, - {"(R_386).String", Method, 0}, - {"(R_390).GoString", Method, 7}, - {"(R_390).String", Method, 7}, - {"(R_AARCH64).GoString", Method, 4}, - {"(R_AARCH64).String", Method, 4}, - {"(R_ALPHA).GoString", Method, 0}, - {"(R_ALPHA).String", Method, 0}, - {"(R_ARM).GoString", Method, 0}, - {"(R_ARM).String", Method, 0}, - {"(R_LARCH).GoString", Method, 19}, - {"(R_LARCH).String", Method, 19}, - {"(R_MIPS).GoString", Method, 6}, - {"(R_MIPS).String", Method, 6}, - {"(R_PPC).GoString", Method, 0}, - {"(R_PPC).String", Method, 0}, - {"(R_PPC64).GoString", Method, 5}, - {"(R_PPC64).String", Method, 5}, - {"(R_RISCV).GoString", Method, 11}, - {"(R_RISCV).String", Method, 11}, - {"(R_SPARC).GoString", Method, 0}, - {"(R_SPARC).String", Method, 0}, - {"(R_X86_64).GoString", Method, 0}, - {"(R_X86_64).String", Method, 0}, - {"(Section).ReadAt", Method, 0}, - {"(SectionFlag).GoString", Method, 0}, - {"(SectionFlag).String", Method, 0}, - {"(SectionIndex).GoString", Method, 0}, - {"(SectionIndex).String", Method, 0}, - {"(SectionType).GoString", Method, 0}, - {"(SectionType).String", Method, 0}, - {"(SymBind).GoString", Method, 0}, - {"(SymBind).String", Method, 0}, - {"(SymType).GoString", Method, 0}, - {"(SymType).String", Method, 0}, - {"(SymVis).GoString", Method, 0}, - {"(SymVis).String", Method, 0}, - {"(Type).GoString", Method, 0}, - {"(Type).String", Method, 0}, - {"(Version).GoString", Method, 0}, - {"(Version).String", Method, 0}, - {"(VersionIndex).Index", Method, 24}, - {"(VersionIndex).IsHidden", Method, 24}, - {"ARM_MAGIC_TRAMP_NUMBER", Const, 0}, - {"COMPRESS_HIOS", Const, 6}, - {"COMPRESS_HIPROC", Const, 6}, - {"COMPRESS_LOOS", Const, 6}, - {"COMPRESS_LOPROC", Const, 6}, - {"COMPRESS_ZLIB", Const, 6}, - {"COMPRESS_ZSTD", Const, 21}, - {"Chdr32", Type, 6}, - {"Chdr32.Addralign", Field, 6}, - {"Chdr32.Size", Field, 6}, - {"Chdr32.Type", Field, 6}, - {"Chdr64", Type, 6}, - {"Chdr64.Addralign", Field, 6}, - {"Chdr64.Size", Field, 6}, - {"Chdr64.Type", Field, 6}, - {"Class", Type, 0}, - {"CompressionType", Type, 6}, - {"DF_1_CONFALT", Const, 21}, - {"DF_1_DIRECT", Const, 21}, - {"DF_1_DISPRELDNE", Const, 21}, - {"DF_1_DISPRELPND", Const, 21}, - {"DF_1_EDITED", Const, 21}, - {"DF_1_ENDFILTEE", Const, 21}, - {"DF_1_GLOBAL", Const, 21}, - {"DF_1_GLOBAUDIT", Const, 21}, - {"DF_1_GROUP", Const, 21}, - {"DF_1_IGNMULDEF", Const, 21}, - {"DF_1_INITFIRST", Const, 21}, - {"DF_1_INTERPOSE", Const, 21}, - {"DF_1_KMOD", Const, 21}, - {"DF_1_LOADFLTR", Const, 21}, - {"DF_1_NOCOMMON", Const, 21}, - {"DF_1_NODEFLIB", Const, 21}, - {"DF_1_NODELETE", Const, 21}, - {"DF_1_NODIRECT", Const, 21}, - {"DF_1_NODUMP", Const, 21}, - {"DF_1_NOHDR", Const, 21}, - {"DF_1_NOKSYMS", Const, 21}, - {"DF_1_NOOPEN", Const, 21}, - {"DF_1_NORELOC", Const, 21}, - {"DF_1_NOW", Const, 21}, - {"DF_1_ORIGIN", Const, 21}, - {"DF_1_PIE", Const, 21}, - {"DF_1_SINGLETON", Const, 21}, - {"DF_1_STUB", Const, 21}, - {"DF_1_SYMINTPOSE", Const, 21}, - {"DF_1_TRANS", Const, 21}, - {"DF_1_WEAKFILTER", Const, 21}, - {"DF_BIND_NOW", Const, 0}, - {"DF_ORIGIN", Const, 0}, - {"DF_STATIC_TLS", Const, 0}, - {"DF_SYMBOLIC", Const, 0}, - {"DF_TEXTREL", Const, 0}, - {"DT_ADDRRNGHI", Const, 16}, - {"DT_ADDRRNGLO", Const, 16}, - {"DT_AUDIT", Const, 16}, - {"DT_AUXILIARY", Const, 16}, - {"DT_BIND_NOW", Const, 0}, - {"DT_CHECKSUM", Const, 16}, - {"DT_CONFIG", Const, 16}, - {"DT_DEBUG", Const, 0}, - {"DT_DEPAUDIT", Const, 16}, - {"DT_ENCODING", Const, 0}, - {"DT_FEATURE", Const, 16}, - {"DT_FILTER", Const, 16}, - {"DT_FINI", Const, 0}, - {"DT_FINI_ARRAY", Const, 0}, - {"DT_FINI_ARRAYSZ", Const, 0}, - {"DT_FLAGS", Const, 0}, - {"DT_FLAGS_1", Const, 16}, - {"DT_GNU_CONFLICT", Const, 16}, - {"DT_GNU_CONFLICTSZ", Const, 16}, - {"DT_GNU_HASH", Const, 16}, - {"DT_GNU_LIBLIST", Const, 16}, - {"DT_GNU_LIBLISTSZ", Const, 16}, - {"DT_GNU_PRELINKED", Const, 16}, - {"DT_HASH", Const, 0}, - {"DT_HIOS", Const, 0}, - {"DT_HIPROC", Const, 0}, - {"DT_INIT", Const, 0}, - {"DT_INIT_ARRAY", Const, 0}, - {"DT_INIT_ARRAYSZ", Const, 0}, - {"DT_JMPREL", Const, 0}, - {"DT_LOOS", Const, 0}, - {"DT_LOPROC", Const, 0}, - {"DT_MIPS_AUX_DYNAMIC", Const, 16}, - {"DT_MIPS_BASE_ADDRESS", Const, 16}, - {"DT_MIPS_COMPACT_SIZE", Const, 16}, - {"DT_MIPS_CONFLICT", Const, 16}, - {"DT_MIPS_CONFLICTNO", Const, 16}, - {"DT_MIPS_CXX_FLAGS", Const, 16}, - {"DT_MIPS_DELTA_CLASS", Const, 16}, - {"DT_MIPS_DELTA_CLASSSYM", Const, 16}, - {"DT_MIPS_DELTA_CLASSSYM_NO", Const, 16}, - {"DT_MIPS_DELTA_CLASS_NO", Const, 16}, - {"DT_MIPS_DELTA_INSTANCE", Const, 16}, - {"DT_MIPS_DELTA_INSTANCE_NO", Const, 16}, - {"DT_MIPS_DELTA_RELOC", Const, 16}, - {"DT_MIPS_DELTA_RELOC_NO", Const, 16}, - {"DT_MIPS_DELTA_SYM", Const, 16}, - {"DT_MIPS_DELTA_SYM_NO", Const, 16}, - {"DT_MIPS_DYNSTR_ALIGN", Const, 16}, - {"DT_MIPS_FLAGS", Const, 16}, - {"DT_MIPS_GOTSYM", Const, 16}, - {"DT_MIPS_GP_VALUE", Const, 16}, - {"DT_MIPS_HIDDEN_GOTIDX", Const, 16}, - {"DT_MIPS_HIPAGENO", Const, 16}, - {"DT_MIPS_ICHECKSUM", Const, 16}, - {"DT_MIPS_INTERFACE", Const, 16}, - {"DT_MIPS_INTERFACE_SIZE", Const, 16}, - {"DT_MIPS_IVERSION", Const, 16}, - {"DT_MIPS_LIBLIST", Const, 16}, - {"DT_MIPS_LIBLISTNO", Const, 16}, - {"DT_MIPS_LOCALPAGE_GOTIDX", Const, 16}, - {"DT_MIPS_LOCAL_GOTIDX", Const, 16}, - {"DT_MIPS_LOCAL_GOTNO", Const, 16}, - {"DT_MIPS_MSYM", Const, 16}, - {"DT_MIPS_OPTIONS", Const, 16}, - {"DT_MIPS_PERF_SUFFIX", Const, 16}, - {"DT_MIPS_PIXIE_INIT", Const, 16}, - {"DT_MIPS_PLTGOT", Const, 16}, - {"DT_MIPS_PROTECTED_GOTIDX", Const, 16}, - {"DT_MIPS_RLD_MAP", Const, 16}, - {"DT_MIPS_RLD_MAP_REL", Const, 16}, - {"DT_MIPS_RLD_TEXT_RESOLVE_ADDR", Const, 16}, - {"DT_MIPS_RLD_VERSION", Const, 16}, - {"DT_MIPS_RWPLT", Const, 16}, - {"DT_MIPS_SYMBOL_LIB", Const, 16}, - {"DT_MIPS_SYMTABNO", Const, 16}, - {"DT_MIPS_TIME_STAMP", Const, 16}, - {"DT_MIPS_UNREFEXTNO", Const, 16}, - {"DT_MOVEENT", Const, 16}, - {"DT_MOVESZ", Const, 16}, - {"DT_MOVETAB", Const, 16}, - {"DT_NEEDED", Const, 0}, - {"DT_NULL", Const, 0}, - {"DT_PLTGOT", Const, 0}, - {"DT_PLTPAD", Const, 16}, - {"DT_PLTPADSZ", Const, 16}, - {"DT_PLTREL", Const, 0}, - {"DT_PLTRELSZ", Const, 0}, - {"DT_POSFLAG_1", Const, 16}, - {"DT_PPC64_GLINK", Const, 16}, - {"DT_PPC64_OPD", Const, 16}, - {"DT_PPC64_OPDSZ", Const, 16}, - {"DT_PPC64_OPT", Const, 16}, - {"DT_PPC_GOT", Const, 16}, - {"DT_PPC_OPT", Const, 16}, - {"DT_PREINIT_ARRAY", Const, 0}, - {"DT_PREINIT_ARRAYSZ", Const, 0}, - {"DT_REL", Const, 0}, - {"DT_RELA", Const, 0}, - {"DT_RELACOUNT", Const, 16}, - {"DT_RELAENT", Const, 0}, - {"DT_RELASZ", Const, 0}, - {"DT_RELCOUNT", Const, 16}, - {"DT_RELENT", Const, 0}, - {"DT_RELSZ", Const, 0}, - {"DT_RPATH", Const, 0}, - {"DT_RUNPATH", Const, 0}, - {"DT_SONAME", Const, 0}, - {"DT_SPARC_REGISTER", Const, 16}, - {"DT_STRSZ", Const, 0}, - {"DT_STRTAB", Const, 0}, - {"DT_SYMBOLIC", Const, 0}, - {"DT_SYMENT", Const, 0}, - {"DT_SYMINENT", Const, 16}, - {"DT_SYMINFO", Const, 16}, - {"DT_SYMINSZ", Const, 16}, - {"DT_SYMTAB", Const, 0}, - {"DT_SYMTAB_SHNDX", Const, 16}, - {"DT_TEXTREL", Const, 0}, - {"DT_TLSDESC_GOT", Const, 16}, - {"DT_TLSDESC_PLT", Const, 16}, - {"DT_USED", Const, 16}, - {"DT_VALRNGHI", Const, 16}, - {"DT_VALRNGLO", Const, 16}, - {"DT_VERDEF", Const, 16}, - {"DT_VERDEFNUM", Const, 16}, - {"DT_VERNEED", Const, 0}, - {"DT_VERNEEDNUM", Const, 0}, - {"DT_VERSYM", Const, 0}, - {"Data", Type, 0}, - {"Dyn32", Type, 0}, - {"Dyn32.Tag", Field, 0}, - {"Dyn32.Val", Field, 0}, - {"Dyn64", Type, 0}, - {"Dyn64.Tag", Field, 0}, - {"Dyn64.Val", Field, 0}, - {"DynFlag", Type, 0}, - {"DynFlag1", Type, 21}, - {"DynTag", Type, 0}, - {"DynamicVersion", Type, 24}, - {"DynamicVersion.Deps", Field, 24}, - {"DynamicVersion.Flags", Field, 24}, - {"DynamicVersion.Index", Field, 24}, - {"DynamicVersion.Name", Field, 24}, - {"DynamicVersionDep", Type, 24}, - {"DynamicVersionDep.Dep", Field, 24}, - {"DynamicVersionDep.Flags", Field, 24}, - {"DynamicVersionDep.Index", Field, 24}, - {"DynamicVersionFlag", Type, 24}, - {"DynamicVersionNeed", Type, 24}, - {"DynamicVersionNeed.Name", Field, 24}, - {"DynamicVersionNeed.Needs", Field, 24}, - {"EI_ABIVERSION", Const, 0}, - {"EI_CLASS", Const, 0}, - {"EI_DATA", Const, 0}, - {"EI_NIDENT", Const, 0}, - {"EI_OSABI", Const, 0}, - {"EI_PAD", Const, 0}, - {"EI_VERSION", Const, 0}, - {"ELFCLASS32", Const, 0}, - {"ELFCLASS64", Const, 0}, - {"ELFCLASSNONE", Const, 0}, - {"ELFDATA2LSB", Const, 0}, - {"ELFDATA2MSB", Const, 0}, - {"ELFDATANONE", Const, 0}, - {"ELFMAG", Const, 0}, - {"ELFOSABI_86OPEN", Const, 0}, - {"ELFOSABI_AIX", Const, 0}, - {"ELFOSABI_ARM", Const, 0}, - {"ELFOSABI_AROS", Const, 11}, - {"ELFOSABI_CLOUDABI", Const, 11}, - {"ELFOSABI_FENIXOS", Const, 11}, - {"ELFOSABI_FREEBSD", Const, 0}, - {"ELFOSABI_HPUX", Const, 0}, - {"ELFOSABI_HURD", Const, 0}, - {"ELFOSABI_IRIX", Const, 0}, - {"ELFOSABI_LINUX", Const, 0}, - {"ELFOSABI_MODESTO", Const, 0}, - {"ELFOSABI_NETBSD", Const, 0}, - {"ELFOSABI_NONE", Const, 0}, - {"ELFOSABI_NSK", Const, 0}, - {"ELFOSABI_OPENBSD", Const, 0}, - {"ELFOSABI_OPENVMS", Const, 0}, - {"ELFOSABI_SOLARIS", Const, 0}, - {"ELFOSABI_STANDALONE", Const, 0}, - {"ELFOSABI_TRU64", Const, 0}, - {"EM_386", Const, 0}, - {"EM_486", Const, 0}, - {"EM_56800EX", Const, 11}, - {"EM_68HC05", Const, 11}, - {"EM_68HC08", Const, 11}, - {"EM_68HC11", Const, 11}, - {"EM_68HC12", Const, 0}, - {"EM_68HC16", Const, 11}, - {"EM_68K", Const, 0}, - {"EM_78KOR", Const, 11}, - {"EM_8051", Const, 11}, - {"EM_860", Const, 0}, - {"EM_88K", Const, 0}, - {"EM_960", Const, 0}, - {"EM_AARCH64", Const, 4}, - {"EM_ALPHA", Const, 0}, - {"EM_ALPHA_STD", Const, 0}, - {"EM_ALTERA_NIOS2", Const, 11}, - {"EM_AMDGPU", Const, 11}, - {"EM_ARC", Const, 0}, - {"EM_ARCA", Const, 11}, - {"EM_ARC_COMPACT", Const, 11}, - {"EM_ARC_COMPACT2", Const, 11}, - {"EM_ARM", Const, 0}, - {"EM_AVR", Const, 11}, - {"EM_AVR32", Const, 11}, - {"EM_BA1", Const, 11}, - {"EM_BA2", Const, 11}, - {"EM_BLACKFIN", Const, 11}, - {"EM_BPF", Const, 11}, - {"EM_C166", Const, 11}, - {"EM_CDP", Const, 11}, - {"EM_CE", Const, 11}, - {"EM_CLOUDSHIELD", Const, 11}, - {"EM_COGE", Const, 11}, - {"EM_COLDFIRE", Const, 0}, - {"EM_COOL", Const, 11}, - {"EM_COREA_1ST", Const, 11}, - {"EM_COREA_2ND", Const, 11}, - {"EM_CR", Const, 11}, - {"EM_CR16", Const, 11}, - {"EM_CRAYNV2", Const, 11}, - {"EM_CRIS", Const, 11}, - {"EM_CRX", Const, 11}, - {"EM_CSR_KALIMBA", Const, 11}, - {"EM_CUDA", Const, 11}, - {"EM_CYPRESS_M8C", Const, 11}, - {"EM_D10V", Const, 11}, - {"EM_D30V", Const, 11}, - {"EM_DSP24", Const, 11}, - {"EM_DSPIC30F", Const, 11}, - {"EM_DXP", Const, 11}, - {"EM_ECOG1", Const, 11}, - {"EM_ECOG16", Const, 11}, - {"EM_ECOG1X", Const, 11}, - {"EM_ECOG2", Const, 11}, - {"EM_ETPU", Const, 11}, - {"EM_EXCESS", Const, 11}, - {"EM_F2MC16", Const, 11}, - {"EM_FIREPATH", Const, 11}, - {"EM_FR20", Const, 0}, - {"EM_FR30", Const, 11}, - {"EM_FT32", Const, 11}, - {"EM_FX66", Const, 11}, - {"EM_H8S", Const, 0}, - {"EM_H8_300", Const, 0}, - {"EM_H8_300H", Const, 0}, - {"EM_H8_500", Const, 0}, - {"EM_HUANY", Const, 11}, - {"EM_IA_64", Const, 0}, - {"EM_INTEL205", Const, 11}, - {"EM_INTEL206", Const, 11}, - {"EM_INTEL207", Const, 11}, - {"EM_INTEL208", Const, 11}, - {"EM_INTEL209", Const, 11}, - {"EM_IP2K", Const, 11}, - {"EM_JAVELIN", Const, 11}, - {"EM_K10M", Const, 11}, - {"EM_KM32", Const, 11}, - {"EM_KMX16", Const, 11}, - {"EM_KMX32", Const, 11}, - {"EM_KMX8", Const, 11}, - {"EM_KVARC", Const, 11}, - {"EM_L10M", Const, 11}, - {"EM_LANAI", Const, 11}, - {"EM_LATTICEMICO32", Const, 11}, - {"EM_LOONGARCH", Const, 19}, - {"EM_M16C", Const, 11}, - {"EM_M32", Const, 0}, - {"EM_M32C", Const, 11}, - {"EM_M32R", Const, 11}, - {"EM_MANIK", Const, 11}, - {"EM_MAX", Const, 11}, - {"EM_MAXQ30", Const, 11}, - {"EM_MCHP_PIC", Const, 11}, - {"EM_MCST_ELBRUS", Const, 11}, - {"EM_ME16", Const, 0}, - {"EM_METAG", Const, 11}, - {"EM_MICROBLAZE", Const, 11}, - {"EM_MIPS", Const, 0}, - {"EM_MIPS_RS3_LE", Const, 0}, - {"EM_MIPS_RS4_BE", Const, 0}, - {"EM_MIPS_X", Const, 0}, - {"EM_MMA", Const, 0}, - {"EM_MMDSP_PLUS", Const, 11}, - {"EM_MMIX", Const, 11}, - {"EM_MN10200", Const, 11}, - {"EM_MN10300", Const, 11}, - {"EM_MOXIE", Const, 11}, - {"EM_MSP430", Const, 11}, - {"EM_NCPU", Const, 0}, - {"EM_NDR1", Const, 0}, - {"EM_NDS32", Const, 11}, - {"EM_NONE", Const, 0}, - {"EM_NORC", Const, 11}, - {"EM_NS32K", Const, 11}, - {"EM_OPEN8", Const, 11}, - {"EM_OPENRISC", Const, 11}, - {"EM_PARISC", Const, 0}, - {"EM_PCP", Const, 0}, - {"EM_PDP10", Const, 11}, - {"EM_PDP11", Const, 11}, - {"EM_PDSP", Const, 11}, - {"EM_PJ", Const, 11}, - {"EM_PPC", Const, 0}, - {"EM_PPC64", Const, 0}, - {"EM_PRISM", Const, 11}, - {"EM_QDSP6", Const, 11}, - {"EM_R32C", Const, 11}, - {"EM_RCE", Const, 0}, - {"EM_RH32", Const, 0}, - {"EM_RISCV", Const, 11}, - {"EM_RL78", Const, 11}, - {"EM_RS08", Const, 11}, - {"EM_RX", Const, 11}, - {"EM_S370", Const, 0}, - {"EM_S390", Const, 0}, - {"EM_SCORE7", Const, 11}, - {"EM_SEP", Const, 11}, - {"EM_SE_C17", Const, 11}, - {"EM_SE_C33", Const, 11}, - {"EM_SH", Const, 0}, - {"EM_SHARC", Const, 11}, - {"EM_SLE9X", Const, 11}, - {"EM_SNP1K", Const, 11}, - {"EM_SPARC", Const, 0}, - {"EM_SPARC32PLUS", Const, 0}, - {"EM_SPARCV9", Const, 0}, - {"EM_ST100", Const, 0}, - {"EM_ST19", Const, 11}, - {"EM_ST200", Const, 11}, - {"EM_ST7", Const, 11}, - {"EM_ST9PLUS", Const, 11}, - {"EM_STARCORE", Const, 0}, - {"EM_STM8", Const, 11}, - {"EM_STXP7X", Const, 11}, - {"EM_SVX", Const, 11}, - {"EM_TILE64", Const, 11}, - {"EM_TILEGX", Const, 11}, - {"EM_TILEPRO", Const, 11}, - {"EM_TINYJ", Const, 0}, - {"EM_TI_ARP32", Const, 11}, - {"EM_TI_C2000", Const, 11}, - {"EM_TI_C5500", Const, 11}, - {"EM_TI_C6000", Const, 11}, - {"EM_TI_PRU", Const, 11}, - {"EM_TMM_GPP", Const, 11}, - {"EM_TPC", Const, 11}, - {"EM_TRICORE", Const, 0}, - {"EM_TRIMEDIA", Const, 11}, - {"EM_TSK3000", Const, 11}, - {"EM_UNICORE", Const, 11}, - {"EM_V800", Const, 0}, - {"EM_V850", Const, 11}, - {"EM_VAX", Const, 11}, - {"EM_VIDEOCORE", Const, 11}, - {"EM_VIDEOCORE3", Const, 11}, - {"EM_VIDEOCORE5", Const, 11}, - {"EM_VISIUM", Const, 11}, - {"EM_VPP500", Const, 0}, - {"EM_X86_64", Const, 0}, - {"EM_XCORE", Const, 11}, - {"EM_XGATE", Const, 11}, - {"EM_XIMO16", Const, 11}, - {"EM_XTENSA", Const, 11}, - {"EM_Z80", Const, 11}, - {"EM_ZSP", Const, 11}, - {"ET_CORE", Const, 0}, - {"ET_DYN", Const, 0}, - {"ET_EXEC", Const, 0}, - {"ET_HIOS", Const, 0}, - {"ET_HIPROC", Const, 0}, - {"ET_LOOS", Const, 0}, - {"ET_LOPROC", Const, 0}, - {"ET_NONE", Const, 0}, - {"ET_REL", Const, 0}, - {"EV_CURRENT", Const, 0}, - {"EV_NONE", Const, 0}, - {"ErrNoSymbols", Var, 4}, - {"File", Type, 0}, - {"File.FileHeader", Field, 0}, - {"File.Progs", Field, 0}, - {"File.Sections", Field, 0}, - {"FileHeader", Type, 0}, - {"FileHeader.ABIVersion", Field, 0}, - {"FileHeader.ByteOrder", Field, 0}, - {"FileHeader.Class", Field, 0}, - {"FileHeader.Data", Field, 0}, - {"FileHeader.Entry", Field, 1}, - {"FileHeader.Machine", Field, 0}, - {"FileHeader.OSABI", Field, 0}, - {"FileHeader.Type", Field, 0}, - {"FileHeader.Version", Field, 0}, - {"FormatError", Type, 0}, - {"Header32", Type, 0}, - {"Header32.Ehsize", Field, 0}, - {"Header32.Entry", Field, 0}, - {"Header32.Flags", Field, 0}, - {"Header32.Ident", Field, 0}, - {"Header32.Machine", Field, 0}, - {"Header32.Phentsize", Field, 0}, - {"Header32.Phnum", Field, 0}, - {"Header32.Phoff", Field, 0}, - {"Header32.Shentsize", Field, 0}, - {"Header32.Shnum", Field, 0}, - {"Header32.Shoff", Field, 0}, - {"Header32.Shstrndx", Field, 0}, - {"Header32.Type", Field, 0}, - {"Header32.Version", Field, 0}, - {"Header64", Type, 0}, - {"Header64.Ehsize", Field, 0}, - {"Header64.Entry", Field, 0}, - {"Header64.Flags", Field, 0}, - {"Header64.Ident", Field, 0}, - {"Header64.Machine", Field, 0}, - {"Header64.Phentsize", Field, 0}, - {"Header64.Phnum", Field, 0}, - {"Header64.Phoff", Field, 0}, - {"Header64.Shentsize", Field, 0}, - {"Header64.Shnum", Field, 0}, - {"Header64.Shoff", Field, 0}, - {"Header64.Shstrndx", Field, 0}, - {"Header64.Type", Field, 0}, - {"Header64.Version", Field, 0}, - {"ImportedSymbol", Type, 0}, - {"ImportedSymbol.Library", Field, 0}, - {"ImportedSymbol.Name", Field, 0}, - {"ImportedSymbol.Version", Field, 0}, - {"Machine", Type, 0}, - {"NT_FPREGSET", Const, 0}, - {"NT_PRPSINFO", Const, 0}, - {"NT_PRSTATUS", Const, 0}, - {"NType", Type, 0}, - {"NewFile", Func, 0}, - {"OSABI", Type, 0}, - {"Open", Func, 0}, - {"PF_MASKOS", Const, 0}, - {"PF_MASKPROC", Const, 0}, - {"PF_R", Const, 0}, - {"PF_W", Const, 0}, - {"PF_X", Const, 0}, - {"PT_AARCH64_ARCHEXT", Const, 16}, - {"PT_AARCH64_UNWIND", Const, 16}, - {"PT_ARM_ARCHEXT", Const, 16}, - {"PT_ARM_EXIDX", Const, 16}, - {"PT_DYNAMIC", Const, 0}, - {"PT_GNU_EH_FRAME", Const, 16}, - {"PT_GNU_MBIND_HI", Const, 16}, - {"PT_GNU_MBIND_LO", Const, 16}, - {"PT_GNU_PROPERTY", Const, 16}, - {"PT_GNU_RELRO", Const, 16}, - {"PT_GNU_STACK", Const, 16}, - {"PT_HIOS", Const, 0}, - {"PT_HIPROC", Const, 0}, - {"PT_INTERP", Const, 0}, - {"PT_LOAD", Const, 0}, - {"PT_LOOS", Const, 0}, - {"PT_LOPROC", Const, 0}, - {"PT_MIPS_ABIFLAGS", Const, 16}, - {"PT_MIPS_OPTIONS", Const, 16}, - {"PT_MIPS_REGINFO", Const, 16}, - {"PT_MIPS_RTPROC", Const, 16}, - {"PT_NOTE", Const, 0}, - {"PT_NULL", Const, 0}, - {"PT_OPENBSD_BOOTDATA", Const, 16}, - {"PT_OPENBSD_NOBTCFI", Const, 23}, - {"PT_OPENBSD_RANDOMIZE", Const, 16}, - {"PT_OPENBSD_WXNEEDED", Const, 16}, - {"PT_PAX_FLAGS", Const, 16}, - {"PT_PHDR", Const, 0}, - {"PT_RISCV_ATTRIBUTES", Const, 25}, - {"PT_S390_PGSTE", Const, 16}, - {"PT_SHLIB", Const, 0}, - {"PT_SUNWSTACK", Const, 16}, - {"PT_SUNW_EH_FRAME", Const, 16}, - {"PT_TLS", Const, 0}, - {"Prog", Type, 0}, - {"Prog.ProgHeader", Field, 0}, - {"Prog.ReaderAt", Field, 0}, - {"Prog32", Type, 0}, - {"Prog32.Align", Field, 0}, - {"Prog32.Filesz", Field, 0}, - {"Prog32.Flags", Field, 0}, - {"Prog32.Memsz", Field, 0}, - {"Prog32.Off", Field, 0}, - {"Prog32.Paddr", Field, 0}, - {"Prog32.Type", Field, 0}, - {"Prog32.Vaddr", Field, 0}, - {"Prog64", Type, 0}, - {"Prog64.Align", Field, 0}, - {"Prog64.Filesz", Field, 0}, - {"Prog64.Flags", Field, 0}, - {"Prog64.Memsz", Field, 0}, - {"Prog64.Off", Field, 0}, - {"Prog64.Paddr", Field, 0}, - {"Prog64.Type", Field, 0}, - {"Prog64.Vaddr", Field, 0}, - {"ProgFlag", Type, 0}, - {"ProgHeader", Type, 0}, - {"ProgHeader.Align", Field, 0}, - {"ProgHeader.Filesz", Field, 0}, - {"ProgHeader.Flags", Field, 0}, - {"ProgHeader.Memsz", Field, 0}, - {"ProgHeader.Off", Field, 0}, - {"ProgHeader.Paddr", Field, 0}, - {"ProgHeader.Type", Field, 0}, - {"ProgHeader.Vaddr", Field, 0}, - {"ProgType", Type, 0}, - {"R_386", Type, 0}, - {"R_386_16", Const, 10}, - {"R_386_32", Const, 0}, - {"R_386_32PLT", Const, 10}, - {"R_386_8", Const, 10}, - {"R_386_COPY", Const, 0}, - {"R_386_GLOB_DAT", Const, 0}, - {"R_386_GOT32", Const, 0}, - {"R_386_GOT32X", Const, 10}, - {"R_386_GOTOFF", Const, 0}, - {"R_386_GOTPC", Const, 0}, - {"R_386_IRELATIVE", Const, 10}, - {"R_386_JMP_SLOT", Const, 0}, - {"R_386_NONE", Const, 0}, - {"R_386_PC16", Const, 10}, - {"R_386_PC32", Const, 0}, - {"R_386_PC8", Const, 10}, - {"R_386_PLT32", Const, 0}, - {"R_386_RELATIVE", Const, 0}, - {"R_386_SIZE32", Const, 10}, - {"R_386_TLS_DESC", Const, 10}, - {"R_386_TLS_DESC_CALL", Const, 10}, - {"R_386_TLS_DTPMOD32", Const, 0}, - {"R_386_TLS_DTPOFF32", Const, 0}, - {"R_386_TLS_GD", Const, 0}, - {"R_386_TLS_GD_32", Const, 0}, - {"R_386_TLS_GD_CALL", Const, 0}, - {"R_386_TLS_GD_POP", Const, 0}, - {"R_386_TLS_GD_PUSH", Const, 0}, - {"R_386_TLS_GOTDESC", Const, 10}, - {"R_386_TLS_GOTIE", Const, 0}, - {"R_386_TLS_IE", Const, 0}, - {"R_386_TLS_IE_32", Const, 0}, - {"R_386_TLS_LDM", Const, 0}, - {"R_386_TLS_LDM_32", Const, 0}, - {"R_386_TLS_LDM_CALL", Const, 0}, - {"R_386_TLS_LDM_POP", Const, 0}, - {"R_386_TLS_LDM_PUSH", Const, 0}, - {"R_386_TLS_LDO_32", Const, 0}, - {"R_386_TLS_LE", Const, 0}, - {"R_386_TLS_LE_32", Const, 0}, - {"R_386_TLS_TPOFF", Const, 0}, - {"R_386_TLS_TPOFF32", Const, 0}, - {"R_390", Type, 7}, - {"R_390_12", Const, 7}, - {"R_390_16", Const, 7}, - {"R_390_20", Const, 7}, - {"R_390_32", Const, 7}, - {"R_390_64", Const, 7}, - {"R_390_8", Const, 7}, - {"R_390_COPY", Const, 7}, - {"R_390_GLOB_DAT", Const, 7}, - {"R_390_GOT12", Const, 7}, - {"R_390_GOT16", Const, 7}, - {"R_390_GOT20", Const, 7}, - {"R_390_GOT32", Const, 7}, - {"R_390_GOT64", Const, 7}, - {"R_390_GOTENT", Const, 7}, - {"R_390_GOTOFF", Const, 7}, - {"R_390_GOTOFF16", Const, 7}, - {"R_390_GOTOFF64", Const, 7}, - {"R_390_GOTPC", Const, 7}, - {"R_390_GOTPCDBL", Const, 7}, - {"R_390_GOTPLT12", Const, 7}, - {"R_390_GOTPLT16", Const, 7}, - {"R_390_GOTPLT20", Const, 7}, - {"R_390_GOTPLT32", Const, 7}, - {"R_390_GOTPLT64", Const, 7}, - {"R_390_GOTPLTENT", Const, 7}, - {"R_390_GOTPLTOFF16", Const, 7}, - {"R_390_GOTPLTOFF32", Const, 7}, - {"R_390_GOTPLTOFF64", Const, 7}, - {"R_390_JMP_SLOT", Const, 7}, - {"R_390_NONE", Const, 7}, - {"R_390_PC16", Const, 7}, - {"R_390_PC16DBL", Const, 7}, - {"R_390_PC32", Const, 7}, - {"R_390_PC32DBL", Const, 7}, - {"R_390_PC64", Const, 7}, - {"R_390_PLT16DBL", Const, 7}, - {"R_390_PLT32", Const, 7}, - {"R_390_PLT32DBL", Const, 7}, - {"R_390_PLT64", Const, 7}, - {"R_390_RELATIVE", Const, 7}, - {"R_390_TLS_DTPMOD", Const, 7}, - {"R_390_TLS_DTPOFF", Const, 7}, - {"R_390_TLS_GD32", Const, 7}, - {"R_390_TLS_GD64", Const, 7}, - {"R_390_TLS_GDCALL", Const, 7}, - {"R_390_TLS_GOTIE12", Const, 7}, - {"R_390_TLS_GOTIE20", Const, 7}, - {"R_390_TLS_GOTIE32", Const, 7}, - {"R_390_TLS_GOTIE64", Const, 7}, - {"R_390_TLS_IE32", Const, 7}, - {"R_390_TLS_IE64", Const, 7}, - {"R_390_TLS_IEENT", Const, 7}, - {"R_390_TLS_LDCALL", Const, 7}, - {"R_390_TLS_LDM32", Const, 7}, - {"R_390_TLS_LDM64", Const, 7}, - {"R_390_TLS_LDO32", Const, 7}, - {"R_390_TLS_LDO64", Const, 7}, - {"R_390_TLS_LE32", Const, 7}, - {"R_390_TLS_LE64", Const, 7}, - {"R_390_TLS_LOAD", Const, 7}, - {"R_390_TLS_TPOFF", Const, 7}, - {"R_AARCH64", Type, 4}, - {"R_AARCH64_ABS16", Const, 4}, - {"R_AARCH64_ABS32", Const, 4}, - {"R_AARCH64_ABS64", Const, 4}, - {"R_AARCH64_ADD_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_ADR_GOT_PAGE", Const, 4}, - {"R_AARCH64_ADR_PREL_LO21", Const, 4}, - {"R_AARCH64_ADR_PREL_PG_HI21", Const, 4}, - {"R_AARCH64_ADR_PREL_PG_HI21_NC", Const, 4}, - {"R_AARCH64_CALL26", Const, 4}, - {"R_AARCH64_CONDBR19", Const, 4}, - {"R_AARCH64_COPY", Const, 4}, - {"R_AARCH64_GLOB_DAT", Const, 4}, - {"R_AARCH64_GOT_LD_PREL19", Const, 4}, - {"R_AARCH64_IRELATIVE", Const, 4}, - {"R_AARCH64_JUMP26", Const, 4}, - {"R_AARCH64_JUMP_SLOT", Const, 4}, - {"R_AARCH64_LD64_GOTOFF_LO15", Const, 10}, - {"R_AARCH64_LD64_GOTPAGE_LO15", Const, 10}, - {"R_AARCH64_LD64_GOT_LO12_NC", Const, 4}, - {"R_AARCH64_LDST128_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_LDST16_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_LDST32_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_LDST64_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_LDST8_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_LD_PREL_LO19", Const, 4}, - {"R_AARCH64_MOVW_SABS_G0", Const, 4}, - {"R_AARCH64_MOVW_SABS_G1", Const, 4}, - {"R_AARCH64_MOVW_SABS_G2", Const, 4}, - {"R_AARCH64_MOVW_UABS_G0", Const, 4}, - {"R_AARCH64_MOVW_UABS_G0_NC", Const, 4}, - {"R_AARCH64_MOVW_UABS_G1", Const, 4}, - {"R_AARCH64_MOVW_UABS_G1_NC", Const, 4}, - {"R_AARCH64_MOVW_UABS_G2", Const, 4}, - {"R_AARCH64_MOVW_UABS_G2_NC", Const, 4}, - {"R_AARCH64_MOVW_UABS_G3", Const, 4}, - {"R_AARCH64_NONE", Const, 4}, - {"R_AARCH64_NULL", Const, 4}, - {"R_AARCH64_P32_ABS16", Const, 4}, - {"R_AARCH64_P32_ABS32", Const, 4}, - {"R_AARCH64_P32_ADD_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_P32_ADR_GOT_PAGE", Const, 4}, - {"R_AARCH64_P32_ADR_PREL_LO21", Const, 4}, - {"R_AARCH64_P32_ADR_PREL_PG_HI21", Const, 4}, - {"R_AARCH64_P32_CALL26", Const, 4}, - {"R_AARCH64_P32_CONDBR19", Const, 4}, - {"R_AARCH64_P32_COPY", Const, 4}, - {"R_AARCH64_P32_GLOB_DAT", Const, 4}, - {"R_AARCH64_P32_GOT_LD_PREL19", Const, 4}, - {"R_AARCH64_P32_IRELATIVE", Const, 4}, - {"R_AARCH64_P32_JUMP26", Const, 4}, - {"R_AARCH64_P32_JUMP_SLOT", Const, 4}, - {"R_AARCH64_P32_LD32_GOT_LO12_NC", Const, 4}, - {"R_AARCH64_P32_LDST128_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_P32_LDST16_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_P32_LDST32_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_P32_LDST64_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_P32_LDST8_ABS_LO12_NC", Const, 4}, - {"R_AARCH64_P32_LD_PREL_LO19", Const, 4}, - {"R_AARCH64_P32_MOVW_SABS_G0", Const, 4}, - {"R_AARCH64_P32_MOVW_UABS_G0", Const, 4}, - {"R_AARCH64_P32_MOVW_UABS_G0_NC", Const, 4}, - {"R_AARCH64_P32_MOVW_UABS_G1", Const, 4}, - {"R_AARCH64_P32_PREL16", Const, 4}, - {"R_AARCH64_P32_PREL32", Const, 4}, - {"R_AARCH64_P32_RELATIVE", Const, 4}, - {"R_AARCH64_P32_TLSDESC", Const, 4}, - {"R_AARCH64_P32_TLSDESC_ADD_LO12_NC", Const, 4}, - {"R_AARCH64_P32_TLSDESC_ADR_PAGE21", Const, 4}, - {"R_AARCH64_P32_TLSDESC_ADR_PREL21", Const, 4}, - {"R_AARCH64_P32_TLSDESC_CALL", Const, 4}, - {"R_AARCH64_P32_TLSDESC_LD32_LO12_NC", Const, 4}, - {"R_AARCH64_P32_TLSDESC_LD_PREL19", Const, 4}, - {"R_AARCH64_P32_TLSGD_ADD_LO12_NC", Const, 4}, - {"R_AARCH64_P32_TLSGD_ADR_PAGE21", Const, 4}, - {"R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21", Const, 4}, - {"R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC", Const, 4}, - {"R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19", Const, 4}, - {"R_AARCH64_P32_TLSLE_ADD_TPREL_HI12", Const, 4}, - {"R_AARCH64_P32_TLSLE_ADD_TPREL_LO12", Const, 4}, - {"R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC", Const, 4}, - {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G0", Const, 4}, - {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC", Const, 4}, - {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G1", Const, 4}, - {"R_AARCH64_P32_TLS_DTPMOD", Const, 4}, - {"R_AARCH64_P32_TLS_DTPREL", Const, 4}, - {"R_AARCH64_P32_TLS_TPREL", Const, 4}, - {"R_AARCH64_P32_TSTBR14", Const, 4}, - {"R_AARCH64_PREL16", Const, 4}, - {"R_AARCH64_PREL32", Const, 4}, - {"R_AARCH64_PREL64", Const, 4}, - {"R_AARCH64_RELATIVE", Const, 4}, - {"R_AARCH64_TLSDESC", Const, 4}, - {"R_AARCH64_TLSDESC_ADD", Const, 4}, - {"R_AARCH64_TLSDESC_ADD_LO12_NC", Const, 4}, - {"R_AARCH64_TLSDESC_ADR_PAGE21", Const, 4}, - {"R_AARCH64_TLSDESC_ADR_PREL21", Const, 4}, - {"R_AARCH64_TLSDESC_CALL", Const, 4}, - {"R_AARCH64_TLSDESC_LD64_LO12_NC", Const, 4}, - {"R_AARCH64_TLSDESC_LDR", Const, 4}, - {"R_AARCH64_TLSDESC_LD_PREL19", Const, 4}, - {"R_AARCH64_TLSDESC_OFF_G0_NC", Const, 4}, - {"R_AARCH64_TLSDESC_OFF_G1", Const, 4}, - {"R_AARCH64_TLSGD_ADD_LO12_NC", Const, 4}, - {"R_AARCH64_TLSGD_ADR_PAGE21", Const, 4}, - {"R_AARCH64_TLSGD_ADR_PREL21", Const, 10}, - {"R_AARCH64_TLSGD_MOVW_G0_NC", Const, 10}, - {"R_AARCH64_TLSGD_MOVW_G1", Const, 10}, - {"R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21", Const, 4}, - {"R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC", Const, 4}, - {"R_AARCH64_TLSIE_LD_GOTTPREL_PREL19", Const, 4}, - {"R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC", Const, 4}, - {"R_AARCH64_TLSIE_MOVW_GOTTPREL_G1", Const, 4}, - {"R_AARCH64_TLSLD_ADR_PAGE21", Const, 10}, - {"R_AARCH64_TLSLD_ADR_PREL21", Const, 10}, - {"R_AARCH64_TLSLD_LDST128_DTPREL_LO12", Const, 10}, - {"R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC", Const, 10}, - {"R_AARCH64_TLSLE_ADD_TPREL_HI12", Const, 4}, - {"R_AARCH64_TLSLE_ADD_TPREL_LO12", Const, 4}, - {"R_AARCH64_TLSLE_ADD_TPREL_LO12_NC", Const, 4}, - {"R_AARCH64_TLSLE_LDST128_TPREL_LO12", Const, 10}, - {"R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC", Const, 10}, - {"R_AARCH64_TLSLE_MOVW_TPREL_G0", Const, 4}, - {"R_AARCH64_TLSLE_MOVW_TPREL_G0_NC", Const, 4}, - {"R_AARCH64_TLSLE_MOVW_TPREL_G1", Const, 4}, - {"R_AARCH64_TLSLE_MOVW_TPREL_G1_NC", Const, 4}, - {"R_AARCH64_TLSLE_MOVW_TPREL_G2", Const, 4}, - {"R_AARCH64_TLS_DTPMOD64", Const, 4}, - {"R_AARCH64_TLS_DTPREL64", Const, 4}, - {"R_AARCH64_TLS_TPREL64", Const, 4}, - {"R_AARCH64_TSTBR14", Const, 4}, - {"R_ALPHA", Type, 0}, - {"R_ALPHA_BRADDR", Const, 0}, - {"R_ALPHA_COPY", Const, 0}, - {"R_ALPHA_GLOB_DAT", Const, 0}, - {"R_ALPHA_GPDISP", Const, 0}, - {"R_ALPHA_GPREL32", Const, 0}, - {"R_ALPHA_GPRELHIGH", Const, 0}, - {"R_ALPHA_GPRELLOW", Const, 0}, - {"R_ALPHA_GPVALUE", Const, 0}, - {"R_ALPHA_HINT", Const, 0}, - {"R_ALPHA_IMMED_BR_HI32", Const, 0}, - {"R_ALPHA_IMMED_GP_16", Const, 0}, - {"R_ALPHA_IMMED_GP_HI32", Const, 0}, - {"R_ALPHA_IMMED_LO32", Const, 0}, - {"R_ALPHA_IMMED_SCN_HI32", Const, 0}, - {"R_ALPHA_JMP_SLOT", Const, 0}, - {"R_ALPHA_LITERAL", Const, 0}, - {"R_ALPHA_LITUSE", Const, 0}, - {"R_ALPHA_NONE", Const, 0}, - {"R_ALPHA_OP_PRSHIFT", Const, 0}, - {"R_ALPHA_OP_PSUB", Const, 0}, - {"R_ALPHA_OP_PUSH", Const, 0}, - {"R_ALPHA_OP_STORE", Const, 0}, - {"R_ALPHA_REFLONG", Const, 0}, - {"R_ALPHA_REFQUAD", Const, 0}, - {"R_ALPHA_RELATIVE", Const, 0}, - {"R_ALPHA_SREL16", Const, 0}, - {"R_ALPHA_SREL32", Const, 0}, - {"R_ALPHA_SREL64", Const, 0}, - {"R_ARM", Type, 0}, - {"R_ARM_ABS12", Const, 0}, - {"R_ARM_ABS16", Const, 0}, - {"R_ARM_ABS32", Const, 0}, - {"R_ARM_ABS32_NOI", Const, 10}, - {"R_ARM_ABS8", Const, 0}, - {"R_ARM_ALU_PCREL_15_8", Const, 10}, - {"R_ARM_ALU_PCREL_23_15", Const, 10}, - {"R_ARM_ALU_PCREL_7_0", Const, 10}, - {"R_ARM_ALU_PC_G0", Const, 10}, - {"R_ARM_ALU_PC_G0_NC", Const, 10}, - {"R_ARM_ALU_PC_G1", Const, 10}, - {"R_ARM_ALU_PC_G1_NC", Const, 10}, - {"R_ARM_ALU_PC_G2", Const, 10}, - {"R_ARM_ALU_SBREL_19_12_NC", Const, 10}, - {"R_ARM_ALU_SBREL_27_20_CK", Const, 10}, - {"R_ARM_ALU_SB_G0", Const, 10}, - {"R_ARM_ALU_SB_G0_NC", Const, 10}, - {"R_ARM_ALU_SB_G1", Const, 10}, - {"R_ARM_ALU_SB_G1_NC", Const, 10}, - {"R_ARM_ALU_SB_G2", Const, 10}, - {"R_ARM_AMP_VCALL9", Const, 0}, - {"R_ARM_BASE_ABS", Const, 10}, - {"R_ARM_CALL", Const, 10}, - {"R_ARM_COPY", Const, 0}, - {"R_ARM_GLOB_DAT", Const, 0}, - {"R_ARM_GNU_VTENTRY", Const, 0}, - {"R_ARM_GNU_VTINHERIT", Const, 0}, - {"R_ARM_GOT32", Const, 0}, - {"R_ARM_GOTOFF", Const, 0}, - {"R_ARM_GOTOFF12", Const, 10}, - {"R_ARM_GOTPC", Const, 0}, - {"R_ARM_GOTRELAX", Const, 10}, - {"R_ARM_GOT_ABS", Const, 10}, - {"R_ARM_GOT_BREL12", Const, 10}, - {"R_ARM_GOT_PREL", Const, 10}, - {"R_ARM_IRELATIVE", Const, 10}, - {"R_ARM_JUMP24", Const, 10}, - {"R_ARM_JUMP_SLOT", Const, 0}, - {"R_ARM_LDC_PC_G0", Const, 10}, - {"R_ARM_LDC_PC_G1", Const, 10}, - {"R_ARM_LDC_PC_G2", Const, 10}, - {"R_ARM_LDC_SB_G0", Const, 10}, - {"R_ARM_LDC_SB_G1", Const, 10}, - {"R_ARM_LDC_SB_G2", Const, 10}, - {"R_ARM_LDRS_PC_G0", Const, 10}, - {"R_ARM_LDRS_PC_G1", Const, 10}, - {"R_ARM_LDRS_PC_G2", Const, 10}, - {"R_ARM_LDRS_SB_G0", Const, 10}, - {"R_ARM_LDRS_SB_G1", Const, 10}, - {"R_ARM_LDRS_SB_G2", Const, 10}, - {"R_ARM_LDR_PC_G1", Const, 10}, - {"R_ARM_LDR_PC_G2", Const, 10}, - {"R_ARM_LDR_SBREL_11_10_NC", Const, 10}, - {"R_ARM_LDR_SB_G0", Const, 10}, - {"R_ARM_LDR_SB_G1", Const, 10}, - {"R_ARM_LDR_SB_G2", Const, 10}, - {"R_ARM_ME_TOO", Const, 10}, - {"R_ARM_MOVT_ABS", Const, 10}, - {"R_ARM_MOVT_BREL", Const, 10}, - {"R_ARM_MOVT_PREL", Const, 10}, - {"R_ARM_MOVW_ABS_NC", Const, 10}, - {"R_ARM_MOVW_BREL", Const, 10}, - {"R_ARM_MOVW_BREL_NC", Const, 10}, - {"R_ARM_MOVW_PREL_NC", Const, 10}, - {"R_ARM_NONE", Const, 0}, - {"R_ARM_PC13", Const, 0}, - {"R_ARM_PC24", Const, 0}, - {"R_ARM_PLT32", Const, 0}, - {"R_ARM_PLT32_ABS", Const, 10}, - {"R_ARM_PREL31", Const, 10}, - {"R_ARM_PRIVATE_0", Const, 10}, - {"R_ARM_PRIVATE_1", Const, 10}, - {"R_ARM_PRIVATE_10", Const, 10}, - {"R_ARM_PRIVATE_11", Const, 10}, - {"R_ARM_PRIVATE_12", Const, 10}, - {"R_ARM_PRIVATE_13", Const, 10}, - {"R_ARM_PRIVATE_14", Const, 10}, - {"R_ARM_PRIVATE_15", Const, 10}, - {"R_ARM_PRIVATE_2", Const, 10}, - {"R_ARM_PRIVATE_3", Const, 10}, - {"R_ARM_PRIVATE_4", Const, 10}, - {"R_ARM_PRIVATE_5", Const, 10}, - {"R_ARM_PRIVATE_6", Const, 10}, - {"R_ARM_PRIVATE_7", Const, 10}, - {"R_ARM_PRIVATE_8", Const, 10}, - {"R_ARM_PRIVATE_9", Const, 10}, - {"R_ARM_RABS32", Const, 0}, - {"R_ARM_RBASE", Const, 0}, - {"R_ARM_REL32", Const, 0}, - {"R_ARM_REL32_NOI", Const, 10}, - {"R_ARM_RELATIVE", Const, 0}, - {"R_ARM_RPC24", Const, 0}, - {"R_ARM_RREL32", Const, 0}, - {"R_ARM_RSBREL32", Const, 0}, - {"R_ARM_RXPC25", Const, 10}, - {"R_ARM_SBREL31", Const, 10}, - {"R_ARM_SBREL32", Const, 0}, - {"R_ARM_SWI24", Const, 0}, - {"R_ARM_TARGET1", Const, 10}, - {"R_ARM_TARGET2", Const, 10}, - {"R_ARM_THM_ABS5", Const, 0}, - {"R_ARM_THM_ALU_ABS_G0_NC", Const, 10}, - {"R_ARM_THM_ALU_ABS_G1_NC", Const, 10}, - {"R_ARM_THM_ALU_ABS_G2_NC", Const, 10}, - {"R_ARM_THM_ALU_ABS_G3", Const, 10}, - {"R_ARM_THM_ALU_PREL_11_0", Const, 10}, - {"R_ARM_THM_GOT_BREL12", Const, 10}, - {"R_ARM_THM_JUMP11", Const, 10}, - {"R_ARM_THM_JUMP19", Const, 10}, - {"R_ARM_THM_JUMP24", Const, 10}, - {"R_ARM_THM_JUMP6", Const, 10}, - {"R_ARM_THM_JUMP8", Const, 10}, - {"R_ARM_THM_MOVT_ABS", Const, 10}, - {"R_ARM_THM_MOVT_BREL", Const, 10}, - {"R_ARM_THM_MOVT_PREL", Const, 10}, - {"R_ARM_THM_MOVW_ABS_NC", Const, 10}, - {"R_ARM_THM_MOVW_BREL", Const, 10}, - {"R_ARM_THM_MOVW_BREL_NC", Const, 10}, - {"R_ARM_THM_MOVW_PREL_NC", Const, 10}, - {"R_ARM_THM_PC12", Const, 10}, - {"R_ARM_THM_PC22", Const, 0}, - {"R_ARM_THM_PC8", Const, 0}, - {"R_ARM_THM_RPC22", Const, 0}, - {"R_ARM_THM_SWI8", Const, 0}, - {"R_ARM_THM_TLS_CALL", Const, 10}, - {"R_ARM_THM_TLS_DESCSEQ16", Const, 10}, - {"R_ARM_THM_TLS_DESCSEQ32", Const, 10}, - {"R_ARM_THM_XPC22", Const, 0}, - {"R_ARM_TLS_CALL", Const, 10}, - {"R_ARM_TLS_DESCSEQ", Const, 10}, - {"R_ARM_TLS_DTPMOD32", Const, 10}, - {"R_ARM_TLS_DTPOFF32", Const, 10}, - {"R_ARM_TLS_GD32", Const, 10}, - {"R_ARM_TLS_GOTDESC", Const, 10}, - {"R_ARM_TLS_IE12GP", Const, 10}, - {"R_ARM_TLS_IE32", Const, 10}, - {"R_ARM_TLS_LDM32", Const, 10}, - {"R_ARM_TLS_LDO12", Const, 10}, - {"R_ARM_TLS_LDO32", Const, 10}, - {"R_ARM_TLS_LE12", Const, 10}, - {"R_ARM_TLS_LE32", Const, 10}, - {"R_ARM_TLS_TPOFF32", Const, 10}, - {"R_ARM_V4BX", Const, 10}, - {"R_ARM_XPC25", Const, 0}, - {"R_INFO", Func, 0}, - {"R_INFO32", Func, 0}, - {"R_LARCH", Type, 19}, - {"R_LARCH_32", Const, 19}, - {"R_LARCH_32_PCREL", Const, 20}, - {"R_LARCH_64", Const, 19}, - {"R_LARCH_64_PCREL", Const, 22}, - {"R_LARCH_ABS64_HI12", Const, 20}, - {"R_LARCH_ABS64_LO20", Const, 20}, - {"R_LARCH_ABS_HI20", Const, 20}, - {"R_LARCH_ABS_LO12", Const, 20}, - {"R_LARCH_ADD16", Const, 19}, - {"R_LARCH_ADD24", Const, 19}, - {"R_LARCH_ADD32", Const, 19}, - {"R_LARCH_ADD6", Const, 22}, - {"R_LARCH_ADD64", Const, 19}, - {"R_LARCH_ADD8", Const, 19}, - {"R_LARCH_ADD_ULEB128", Const, 22}, - {"R_LARCH_ALIGN", Const, 22}, - {"R_LARCH_B16", Const, 20}, - {"R_LARCH_B21", Const, 20}, - {"R_LARCH_B26", Const, 20}, - {"R_LARCH_CFA", Const, 22}, - {"R_LARCH_COPY", Const, 19}, - {"R_LARCH_DELETE", Const, 22}, - {"R_LARCH_GNU_VTENTRY", Const, 20}, - {"R_LARCH_GNU_VTINHERIT", Const, 20}, - {"R_LARCH_GOT64_HI12", Const, 20}, - {"R_LARCH_GOT64_LO20", Const, 20}, - {"R_LARCH_GOT64_PC_HI12", Const, 20}, - {"R_LARCH_GOT64_PC_LO20", Const, 20}, - {"R_LARCH_GOT_HI20", Const, 20}, - {"R_LARCH_GOT_LO12", Const, 20}, - {"R_LARCH_GOT_PC_HI20", Const, 20}, - {"R_LARCH_GOT_PC_LO12", Const, 20}, - {"R_LARCH_IRELATIVE", Const, 19}, - {"R_LARCH_JUMP_SLOT", Const, 19}, - {"R_LARCH_MARK_LA", Const, 19}, - {"R_LARCH_MARK_PCREL", Const, 19}, - {"R_LARCH_NONE", Const, 19}, - {"R_LARCH_PCALA64_HI12", Const, 20}, - {"R_LARCH_PCALA64_LO20", Const, 20}, - {"R_LARCH_PCALA_HI20", Const, 20}, - {"R_LARCH_PCALA_LO12", Const, 20}, - {"R_LARCH_PCREL20_S2", Const, 22}, - {"R_LARCH_RELATIVE", Const, 19}, - {"R_LARCH_RELAX", Const, 20}, - {"R_LARCH_SOP_ADD", Const, 19}, - {"R_LARCH_SOP_AND", Const, 19}, - {"R_LARCH_SOP_ASSERT", Const, 19}, - {"R_LARCH_SOP_IF_ELSE", Const, 19}, - {"R_LARCH_SOP_NOT", Const, 19}, - {"R_LARCH_SOP_POP_32_S_0_10_10_16_S2", Const, 19}, - {"R_LARCH_SOP_POP_32_S_0_5_10_16_S2", Const, 19}, - {"R_LARCH_SOP_POP_32_S_10_12", Const, 19}, - {"R_LARCH_SOP_POP_32_S_10_16", Const, 19}, - {"R_LARCH_SOP_POP_32_S_10_16_S2", Const, 19}, - {"R_LARCH_SOP_POP_32_S_10_5", Const, 19}, - {"R_LARCH_SOP_POP_32_S_5_20", Const, 19}, - {"R_LARCH_SOP_POP_32_U", Const, 19}, - {"R_LARCH_SOP_POP_32_U_10_12", Const, 19}, - {"R_LARCH_SOP_PUSH_ABSOLUTE", Const, 19}, - {"R_LARCH_SOP_PUSH_DUP", Const, 19}, - {"R_LARCH_SOP_PUSH_GPREL", Const, 19}, - {"R_LARCH_SOP_PUSH_PCREL", Const, 19}, - {"R_LARCH_SOP_PUSH_PLT_PCREL", Const, 19}, - {"R_LARCH_SOP_PUSH_TLS_GD", Const, 19}, - {"R_LARCH_SOP_PUSH_TLS_GOT", Const, 19}, - {"R_LARCH_SOP_PUSH_TLS_TPREL", Const, 19}, - {"R_LARCH_SOP_SL", Const, 19}, - {"R_LARCH_SOP_SR", Const, 19}, - {"R_LARCH_SOP_SUB", Const, 19}, - {"R_LARCH_SUB16", Const, 19}, - {"R_LARCH_SUB24", Const, 19}, - {"R_LARCH_SUB32", Const, 19}, - {"R_LARCH_SUB6", Const, 22}, - {"R_LARCH_SUB64", Const, 19}, - {"R_LARCH_SUB8", Const, 19}, - {"R_LARCH_SUB_ULEB128", Const, 22}, - {"R_LARCH_TLS_DTPMOD32", Const, 19}, - {"R_LARCH_TLS_DTPMOD64", Const, 19}, - {"R_LARCH_TLS_DTPREL32", Const, 19}, - {"R_LARCH_TLS_DTPREL64", Const, 19}, - {"R_LARCH_TLS_GD_HI20", Const, 20}, - {"R_LARCH_TLS_GD_PC_HI20", Const, 20}, - {"R_LARCH_TLS_IE64_HI12", Const, 20}, - {"R_LARCH_TLS_IE64_LO20", Const, 20}, - {"R_LARCH_TLS_IE64_PC_HI12", Const, 20}, - {"R_LARCH_TLS_IE64_PC_LO20", Const, 20}, - {"R_LARCH_TLS_IE_HI20", Const, 20}, - {"R_LARCH_TLS_IE_LO12", Const, 20}, - {"R_LARCH_TLS_IE_PC_HI20", Const, 20}, - {"R_LARCH_TLS_IE_PC_LO12", Const, 20}, - {"R_LARCH_TLS_LD_HI20", Const, 20}, - {"R_LARCH_TLS_LD_PC_HI20", Const, 20}, - {"R_LARCH_TLS_LE64_HI12", Const, 20}, - {"R_LARCH_TLS_LE64_LO20", Const, 20}, - {"R_LARCH_TLS_LE_HI20", Const, 20}, - {"R_LARCH_TLS_LE_LO12", Const, 20}, - {"R_LARCH_TLS_TPREL32", Const, 19}, - {"R_LARCH_TLS_TPREL64", Const, 19}, - {"R_MIPS", Type, 6}, - {"R_MIPS_16", Const, 6}, - {"R_MIPS_26", Const, 6}, - {"R_MIPS_32", Const, 6}, - {"R_MIPS_64", Const, 6}, - {"R_MIPS_ADD_IMMEDIATE", Const, 6}, - {"R_MIPS_CALL16", Const, 6}, - {"R_MIPS_CALL_HI16", Const, 6}, - {"R_MIPS_CALL_LO16", Const, 6}, - {"R_MIPS_DELETE", Const, 6}, - {"R_MIPS_GOT16", Const, 6}, - {"R_MIPS_GOT_DISP", Const, 6}, - {"R_MIPS_GOT_HI16", Const, 6}, - {"R_MIPS_GOT_LO16", Const, 6}, - {"R_MIPS_GOT_OFST", Const, 6}, - {"R_MIPS_GOT_PAGE", Const, 6}, - {"R_MIPS_GPREL16", Const, 6}, - {"R_MIPS_GPREL32", Const, 6}, - {"R_MIPS_HI16", Const, 6}, - {"R_MIPS_HIGHER", Const, 6}, - {"R_MIPS_HIGHEST", Const, 6}, - {"R_MIPS_INSERT_A", Const, 6}, - {"R_MIPS_INSERT_B", Const, 6}, - {"R_MIPS_JALR", Const, 6}, - {"R_MIPS_LITERAL", Const, 6}, - {"R_MIPS_LO16", Const, 6}, - {"R_MIPS_NONE", Const, 6}, - {"R_MIPS_PC16", Const, 6}, - {"R_MIPS_PC32", Const, 22}, - {"R_MIPS_PJUMP", Const, 6}, - {"R_MIPS_REL16", Const, 6}, - {"R_MIPS_REL32", Const, 6}, - {"R_MIPS_RELGOT", Const, 6}, - {"R_MIPS_SCN_DISP", Const, 6}, - {"R_MIPS_SHIFT5", Const, 6}, - {"R_MIPS_SHIFT6", Const, 6}, - {"R_MIPS_SUB", Const, 6}, - {"R_MIPS_TLS_DTPMOD32", Const, 6}, - {"R_MIPS_TLS_DTPMOD64", Const, 6}, - {"R_MIPS_TLS_DTPREL32", Const, 6}, - {"R_MIPS_TLS_DTPREL64", Const, 6}, - {"R_MIPS_TLS_DTPREL_HI16", Const, 6}, - {"R_MIPS_TLS_DTPREL_LO16", Const, 6}, - {"R_MIPS_TLS_GD", Const, 6}, - {"R_MIPS_TLS_GOTTPREL", Const, 6}, - {"R_MIPS_TLS_LDM", Const, 6}, - {"R_MIPS_TLS_TPREL32", Const, 6}, - {"R_MIPS_TLS_TPREL64", Const, 6}, - {"R_MIPS_TLS_TPREL_HI16", Const, 6}, - {"R_MIPS_TLS_TPREL_LO16", Const, 6}, - {"R_PPC", Type, 0}, - {"R_PPC64", Type, 5}, - {"R_PPC64_ADDR14", Const, 5}, - {"R_PPC64_ADDR14_BRNTAKEN", Const, 5}, - {"R_PPC64_ADDR14_BRTAKEN", Const, 5}, - {"R_PPC64_ADDR16", Const, 5}, - {"R_PPC64_ADDR16_DS", Const, 5}, - {"R_PPC64_ADDR16_HA", Const, 5}, - {"R_PPC64_ADDR16_HI", Const, 5}, - {"R_PPC64_ADDR16_HIGH", Const, 10}, - {"R_PPC64_ADDR16_HIGHA", Const, 10}, - {"R_PPC64_ADDR16_HIGHER", Const, 5}, - {"R_PPC64_ADDR16_HIGHER34", Const, 20}, - {"R_PPC64_ADDR16_HIGHERA", Const, 5}, - {"R_PPC64_ADDR16_HIGHERA34", Const, 20}, - {"R_PPC64_ADDR16_HIGHEST", Const, 5}, - {"R_PPC64_ADDR16_HIGHEST34", Const, 20}, - {"R_PPC64_ADDR16_HIGHESTA", Const, 5}, - {"R_PPC64_ADDR16_HIGHESTA34", Const, 20}, - {"R_PPC64_ADDR16_LO", Const, 5}, - {"R_PPC64_ADDR16_LO_DS", Const, 5}, - {"R_PPC64_ADDR24", Const, 5}, - {"R_PPC64_ADDR32", Const, 5}, - {"R_PPC64_ADDR64", Const, 5}, - {"R_PPC64_ADDR64_LOCAL", Const, 10}, - {"R_PPC64_COPY", Const, 20}, - {"R_PPC64_D28", Const, 20}, - {"R_PPC64_D34", Const, 20}, - {"R_PPC64_D34_HA30", Const, 20}, - {"R_PPC64_D34_HI30", Const, 20}, - {"R_PPC64_D34_LO", Const, 20}, - {"R_PPC64_DTPMOD64", Const, 5}, - {"R_PPC64_DTPREL16", Const, 5}, - {"R_PPC64_DTPREL16_DS", Const, 5}, - {"R_PPC64_DTPREL16_HA", Const, 5}, - {"R_PPC64_DTPREL16_HI", Const, 5}, - {"R_PPC64_DTPREL16_HIGH", Const, 10}, - {"R_PPC64_DTPREL16_HIGHA", Const, 10}, - {"R_PPC64_DTPREL16_HIGHER", Const, 5}, - {"R_PPC64_DTPREL16_HIGHERA", Const, 5}, - {"R_PPC64_DTPREL16_HIGHEST", Const, 5}, - {"R_PPC64_DTPREL16_HIGHESTA", Const, 5}, - {"R_PPC64_DTPREL16_LO", Const, 5}, - {"R_PPC64_DTPREL16_LO_DS", Const, 5}, - {"R_PPC64_DTPREL34", Const, 20}, - {"R_PPC64_DTPREL64", Const, 5}, - {"R_PPC64_ENTRY", Const, 10}, - {"R_PPC64_GLOB_DAT", Const, 20}, - {"R_PPC64_GNU_VTENTRY", Const, 20}, - {"R_PPC64_GNU_VTINHERIT", Const, 20}, - {"R_PPC64_GOT16", Const, 5}, - {"R_PPC64_GOT16_DS", Const, 5}, - {"R_PPC64_GOT16_HA", Const, 5}, - {"R_PPC64_GOT16_HI", Const, 5}, - {"R_PPC64_GOT16_LO", Const, 5}, - {"R_PPC64_GOT16_LO_DS", Const, 5}, - {"R_PPC64_GOT_DTPREL16_DS", Const, 5}, - {"R_PPC64_GOT_DTPREL16_HA", Const, 5}, - {"R_PPC64_GOT_DTPREL16_HI", Const, 5}, - {"R_PPC64_GOT_DTPREL16_LO_DS", Const, 5}, - {"R_PPC64_GOT_DTPREL_PCREL34", Const, 20}, - {"R_PPC64_GOT_PCREL34", Const, 20}, - {"R_PPC64_GOT_TLSGD16", Const, 5}, - {"R_PPC64_GOT_TLSGD16_HA", Const, 5}, - {"R_PPC64_GOT_TLSGD16_HI", Const, 5}, - {"R_PPC64_GOT_TLSGD16_LO", Const, 5}, - {"R_PPC64_GOT_TLSGD_PCREL34", Const, 20}, - {"R_PPC64_GOT_TLSLD16", Const, 5}, - {"R_PPC64_GOT_TLSLD16_HA", Const, 5}, - {"R_PPC64_GOT_TLSLD16_HI", Const, 5}, - {"R_PPC64_GOT_TLSLD16_LO", Const, 5}, - {"R_PPC64_GOT_TLSLD_PCREL34", Const, 20}, - {"R_PPC64_GOT_TPREL16_DS", Const, 5}, - {"R_PPC64_GOT_TPREL16_HA", Const, 5}, - {"R_PPC64_GOT_TPREL16_HI", Const, 5}, - {"R_PPC64_GOT_TPREL16_LO_DS", Const, 5}, - {"R_PPC64_GOT_TPREL_PCREL34", Const, 20}, - {"R_PPC64_IRELATIVE", Const, 10}, - {"R_PPC64_JMP_IREL", Const, 10}, - {"R_PPC64_JMP_SLOT", Const, 5}, - {"R_PPC64_NONE", Const, 5}, - {"R_PPC64_PCREL28", Const, 20}, - {"R_PPC64_PCREL34", Const, 20}, - {"R_PPC64_PCREL_OPT", Const, 20}, - {"R_PPC64_PLT16_HA", Const, 20}, - {"R_PPC64_PLT16_HI", Const, 20}, - {"R_PPC64_PLT16_LO", Const, 20}, - {"R_PPC64_PLT16_LO_DS", Const, 10}, - {"R_PPC64_PLT32", Const, 20}, - {"R_PPC64_PLT64", Const, 20}, - {"R_PPC64_PLTCALL", Const, 20}, - {"R_PPC64_PLTCALL_NOTOC", Const, 20}, - {"R_PPC64_PLTGOT16", Const, 10}, - {"R_PPC64_PLTGOT16_DS", Const, 10}, - {"R_PPC64_PLTGOT16_HA", Const, 10}, - {"R_PPC64_PLTGOT16_HI", Const, 10}, - {"R_PPC64_PLTGOT16_LO", Const, 10}, - {"R_PPC64_PLTGOT_LO_DS", Const, 10}, - {"R_PPC64_PLTREL32", Const, 20}, - {"R_PPC64_PLTREL64", Const, 20}, - {"R_PPC64_PLTSEQ", Const, 20}, - {"R_PPC64_PLTSEQ_NOTOC", Const, 20}, - {"R_PPC64_PLT_PCREL34", Const, 20}, - {"R_PPC64_PLT_PCREL34_NOTOC", Const, 20}, - {"R_PPC64_REL14", Const, 5}, - {"R_PPC64_REL14_BRNTAKEN", Const, 5}, - {"R_PPC64_REL14_BRTAKEN", Const, 5}, - {"R_PPC64_REL16", Const, 5}, - {"R_PPC64_REL16DX_HA", Const, 10}, - {"R_PPC64_REL16_HA", Const, 5}, - {"R_PPC64_REL16_HI", Const, 5}, - {"R_PPC64_REL16_HIGH", Const, 20}, - {"R_PPC64_REL16_HIGHA", Const, 20}, - {"R_PPC64_REL16_HIGHER", Const, 20}, - {"R_PPC64_REL16_HIGHER34", Const, 20}, - {"R_PPC64_REL16_HIGHERA", Const, 20}, - {"R_PPC64_REL16_HIGHERA34", Const, 20}, - {"R_PPC64_REL16_HIGHEST", Const, 20}, - {"R_PPC64_REL16_HIGHEST34", Const, 20}, - {"R_PPC64_REL16_HIGHESTA", Const, 20}, - {"R_PPC64_REL16_HIGHESTA34", Const, 20}, - {"R_PPC64_REL16_LO", Const, 5}, - {"R_PPC64_REL24", Const, 5}, - {"R_PPC64_REL24_NOTOC", Const, 10}, - {"R_PPC64_REL24_P9NOTOC", Const, 21}, - {"R_PPC64_REL30", Const, 20}, - {"R_PPC64_REL32", Const, 5}, - {"R_PPC64_REL64", Const, 5}, - {"R_PPC64_RELATIVE", Const, 18}, - {"R_PPC64_SECTOFF", Const, 20}, - {"R_PPC64_SECTOFF_DS", Const, 10}, - {"R_PPC64_SECTOFF_HA", Const, 20}, - {"R_PPC64_SECTOFF_HI", Const, 20}, - {"R_PPC64_SECTOFF_LO", Const, 20}, - {"R_PPC64_SECTOFF_LO_DS", Const, 10}, - {"R_PPC64_TLS", Const, 5}, - {"R_PPC64_TLSGD", Const, 5}, - {"R_PPC64_TLSLD", Const, 5}, - {"R_PPC64_TOC", Const, 5}, - {"R_PPC64_TOC16", Const, 5}, - {"R_PPC64_TOC16_DS", Const, 5}, - {"R_PPC64_TOC16_HA", Const, 5}, - {"R_PPC64_TOC16_HI", Const, 5}, - {"R_PPC64_TOC16_LO", Const, 5}, - {"R_PPC64_TOC16_LO_DS", Const, 5}, - {"R_PPC64_TOCSAVE", Const, 10}, - {"R_PPC64_TPREL16", Const, 5}, - {"R_PPC64_TPREL16_DS", Const, 5}, - {"R_PPC64_TPREL16_HA", Const, 5}, - {"R_PPC64_TPREL16_HI", Const, 5}, - {"R_PPC64_TPREL16_HIGH", Const, 10}, - {"R_PPC64_TPREL16_HIGHA", Const, 10}, - {"R_PPC64_TPREL16_HIGHER", Const, 5}, - {"R_PPC64_TPREL16_HIGHERA", Const, 5}, - {"R_PPC64_TPREL16_HIGHEST", Const, 5}, - {"R_PPC64_TPREL16_HIGHESTA", Const, 5}, - {"R_PPC64_TPREL16_LO", Const, 5}, - {"R_PPC64_TPREL16_LO_DS", Const, 5}, - {"R_PPC64_TPREL34", Const, 20}, - {"R_PPC64_TPREL64", Const, 5}, - {"R_PPC64_UADDR16", Const, 20}, - {"R_PPC64_UADDR32", Const, 20}, - {"R_PPC64_UADDR64", Const, 20}, - {"R_PPC_ADDR14", Const, 0}, - {"R_PPC_ADDR14_BRNTAKEN", Const, 0}, - {"R_PPC_ADDR14_BRTAKEN", Const, 0}, - {"R_PPC_ADDR16", Const, 0}, - {"R_PPC_ADDR16_HA", Const, 0}, - {"R_PPC_ADDR16_HI", Const, 0}, - {"R_PPC_ADDR16_LO", Const, 0}, - {"R_PPC_ADDR24", Const, 0}, - {"R_PPC_ADDR32", Const, 0}, - {"R_PPC_COPY", Const, 0}, - {"R_PPC_DTPMOD32", Const, 0}, - {"R_PPC_DTPREL16", Const, 0}, - {"R_PPC_DTPREL16_HA", Const, 0}, - {"R_PPC_DTPREL16_HI", Const, 0}, - {"R_PPC_DTPREL16_LO", Const, 0}, - {"R_PPC_DTPREL32", Const, 0}, - {"R_PPC_EMB_BIT_FLD", Const, 0}, - {"R_PPC_EMB_MRKREF", Const, 0}, - {"R_PPC_EMB_NADDR16", Const, 0}, - {"R_PPC_EMB_NADDR16_HA", Const, 0}, - {"R_PPC_EMB_NADDR16_HI", Const, 0}, - {"R_PPC_EMB_NADDR16_LO", Const, 0}, - {"R_PPC_EMB_NADDR32", Const, 0}, - {"R_PPC_EMB_RELSDA", Const, 0}, - {"R_PPC_EMB_RELSEC16", Const, 0}, - {"R_PPC_EMB_RELST_HA", Const, 0}, - {"R_PPC_EMB_RELST_HI", Const, 0}, - {"R_PPC_EMB_RELST_LO", Const, 0}, - {"R_PPC_EMB_SDA21", Const, 0}, - {"R_PPC_EMB_SDA2I16", Const, 0}, - {"R_PPC_EMB_SDA2REL", Const, 0}, - {"R_PPC_EMB_SDAI16", Const, 0}, - {"R_PPC_GLOB_DAT", Const, 0}, - {"R_PPC_GOT16", Const, 0}, - {"R_PPC_GOT16_HA", Const, 0}, - {"R_PPC_GOT16_HI", Const, 0}, - {"R_PPC_GOT16_LO", Const, 0}, - {"R_PPC_GOT_TLSGD16", Const, 0}, - {"R_PPC_GOT_TLSGD16_HA", Const, 0}, - {"R_PPC_GOT_TLSGD16_HI", Const, 0}, - {"R_PPC_GOT_TLSGD16_LO", Const, 0}, - {"R_PPC_GOT_TLSLD16", Const, 0}, - {"R_PPC_GOT_TLSLD16_HA", Const, 0}, - {"R_PPC_GOT_TLSLD16_HI", Const, 0}, - {"R_PPC_GOT_TLSLD16_LO", Const, 0}, - {"R_PPC_GOT_TPREL16", Const, 0}, - {"R_PPC_GOT_TPREL16_HA", Const, 0}, - {"R_PPC_GOT_TPREL16_HI", Const, 0}, - {"R_PPC_GOT_TPREL16_LO", Const, 0}, - {"R_PPC_JMP_SLOT", Const, 0}, - {"R_PPC_LOCAL24PC", Const, 0}, - {"R_PPC_NONE", Const, 0}, - {"R_PPC_PLT16_HA", Const, 0}, - {"R_PPC_PLT16_HI", Const, 0}, - {"R_PPC_PLT16_LO", Const, 0}, - {"R_PPC_PLT32", Const, 0}, - {"R_PPC_PLTREL24", Const, 0}, - {"R_PPC_PLTREL32", Const, 0}, - {"R_PPC_REL14", Const, 0}, - {"R_PPC_REL14_BRNTAKEN", Const, 0}, - {"R_PPC_REL14_BRTAKEN", Const, 0}, - {"R_PPC_REL24", Const, 0}, - {"R_PPC_REL32", Const, 0}, - {"R_PPC_RELATIVE", Const, 0}, - {"R_PPC_SDAREL16", Const, 0}, - {"R_PPC_SECTOFF", Const, 0}, - {"R_PPC_SECTOFF_HA", Const, 0}, - {"R_PPC_SECTOFF_HI", Const, 0}, - {"R_PPC_SECTOFF_LO", Const, 0}, - {"R_PPC_TLS", Const, 0}, - {"R_PPC_TPREL16", Const, 0}, - {"R_PPC_TPREL16_HA", Const, 0}, - {"R_PPC_TPREL16_HI", Const, 0}, - {"R_PPC_TPREL16_LO", Const, 0}, - {"R_PPC_TPREL32", Const, 0}, - {"R_PPC_UADDR16", Const, 0}, - {"R_PPC_UADDR32", Const, 0}, - {"R_RISCV", Type, 11}, - {"R_RISCV_32", Const, 11}, - {"R_RISCV_32_PCREL", Const, 12}, - {"R_RISCV_64", Const, 11}, - {"R_RISCV_ADD16", Const, 11}, - {"R_RISCV_ADD32", Const, 11}, - {"R_RISCV_ADD64", Const, 11}, - {"R_RISCV_ADD8", Const, 11}, - {"R_RISCV_ALIGN", Const, 11}, - {"R_RISCV_BRANCH", Const, 11}, - {"R_RISCV_CALL", Const, 11}, - {"R_RISCV_CALL_PLT", Const, 11}, - {"R_RISCV_COPY", Const, 11}, - {"R_RISCV_GNU_VTENTRY", Const, 11}, - {"R_RISCV_GNU_VTINHERIT", Const, 11}, - {"R_RISCV_GOT_HI20", Const, 11}, - {"R_RISCV_GPREL_I", Const, 11}, - {"R_RISCV_GPREL_S", Const, 11}, - {"R_RISCV_HI20", Const, 11}, - {"R_RISCV_JAL", Const, 11}, - {"R_RISCV_JUMP_SLOT", Const, 11}, - {"R_RISCV_LO12_I", Const, 11}, - {"R_RISCV_LO12_S", Const, 11}, - {"R_RISCV_NONE", Const, 11}, - {"R_RISCV_PCREL_HI20", Const, 11}, - {"R_RISCV_PCREL_LO12_I", Const, 11}, - {"R_RISCV_PCREL_LO12_S", Const, 11}, - {"R_RISCV_RELATIVE", Const, 11}, - {"R_RISCV_RELAX", Const, 11}, - {"R_RISCV_RVC_BRANCH", Const, 11}, - {"R_RISCV_RVC_JUMP", Const, 11}, - {"R_RISCV_RVC_LUI", Const, 11}, - {"R_RISCV_SET16", Const, 11}, - {"R_RISCV_SET32", Const, 11}, - {"R_RISCV_SET6", Const, 11}, - {"R_RISCV_SET8", Const, 11}, - {"R_RISCV_SUB16", Const, 11}, - {"R_RISCV_SUB32", Const, 11}, - {"R_RISCV_SUB6", Const, 11}, - {"R_RISCV_SUB64", Const, 11}, - {"R_RISCV_SUB8", Const, 11}, - {"R_RISCV_TLS_DTPMOD32", Const, 11}, - {"R_RISCV_TLS_DTPMOD64", Const, 11}, - {"R_RISCV_TLS_DTPREL32", Const, 11}, - {"R_RISCV_TLS_DTPREL64", Const, 11}, - {"R_RISCV_TLS_GD_HI20", Const, 11}, - {"R_RISCV_TLS_GOT_HI20", Const, 11}, - {"R_RISCV_TLS_TPREL32", Const, 11}, - {"R_RISCV_TLS_TPREL64", Const, 11}, - {"R_RISCV_TPREL_ADD", Const, 11}, - {"R_RISCV_TPREL_HI20", Const, 11}, - {"R_RISCV_TPREL_I", Const, 11}, - {"R_RISCV_TPREL_LO12_I", Const, 11}, - {"R_RISCV_TPREL_LO12_S", Const, 11}, - {"R_RISCV_TPREL_S", Const, 11}, - {"R_SPARC", Type, 0}, - {"R_SPARC_10", Const, 0}, - {"R_SPARC_11", Const, 0}, - {"R_SPARC_13", Const, 0}, - {"R_SPARC_16", Const, 0}, - {"R_SPARC_22", Const, 0}, - {"R_SPARC_32", Const, 0}, - {"R_SPARC_5", Const, 0}, - {"R_SPARC_6", Const, 0}, - {"R_SPARC_64", Const, 0}, - {"R_SPARC_7", Const, 0}, - {"R_SPARC_8", Const, 0}, - {"R_SPARC_COPY", Const, 0}, - {"R_SPARC_DISP16", Const, 0}, - {"R_SPARC_DISP32", Const, 0}, - {"R_SPARC_DISP64", Const, 0}, - {"R_SPARC_DISP8", Const, 0}, - {"R_SPARC_GLOB_DAT", Const, 0}, - {"R_SPARC_GLOB_JMP", Const, 0}, - {"R_SPARC_GOT10", Const, 0}, - {"R_SPARC_GOT13", Const, 0}, - {"R_SPARC_GOT22", Const, 0}, - {"R_SPARC_H44", Const, 0}, - {"R_SPARC_HH22", Const, 0}, - {"R_SPARC_HI22", Const, 0}, - {"R_SPARC_HIPLT22", Const, 0}, - {"R_SPARC_HIX22", Const, 0}, - {"R_SPARC_HM10", Const, 0}, - {"R_SPARC_JMP_SLOT", Const, 0}, - {"R_SPARC_L44", Const, 0}, - {"R_SPARC_LM22", Const, 0}, - {"R_SPARC_LO10", Const, 0}, - {"R_SPARC_LOPLT10", Const, 0}, - {"R_SPARC_LOX10", Const, 0}, - {"R_SPARC_M44", Const, 0}, - {"R_SPARC_NONE", Const, 0}, - {"R_SPARC_OLO10", Const, 0}, - {"R_SPARC_PC10", Const, 0}, - {"R_SPARC_PC22", Const, 0}, - {"R_SPARC_PCPLT10", Const, 0}, - {"R_SPARC_PCPLT22", Const, 0}, - {"R_SPARC_PCPLT32", Const, 0}, - {"R_SPARC_PC_HH22", Const, 0}, - {"R_SPARC_PC_HM10", Const, 0}, - {"R_SPARC_PC_LM22", Const, 0}, - {"R_SPARC_PLT32", Const, 0}, - {"R_SPARC_PLT64", Const, 0}, - {"R_SPARC_REGISTER", Const, 0}, - {"R_SPARC_RELATIVE", Const, 0}, - {"R_SPARC_UA16", Const, 0}, - {"R_SPARC_UA32", Const, 0}, - {"R_SPARC_UA64", Const, 0}, - {"R_SPARC_WDISP16", Const, 0}, - {"R_SPARC_WDISP19", Const, 0}, - {"R_SPARC_WDISP22", Const, 0}, - {"R_SPARC_WDISP30", Const, 0}, - {"R_SPARC_WPLT30", Const, 0}, - {"R_SYM32", Func, 0}, - {"R_SYM64", Func, 0}, - {"R_TYPE32", Func, 0}, - {"R_TYPE64", Func, 0}, - {"R_X86_64", Type, 0}, - {"R_X86_64_16", Const, 0}, - {"R_X86_64_32", Const, 0}, - {"R_X86_64_32S", Const, 0}, - {"R_X86_64_64", Const, 0}, - {"R_X86_64_8", Const, 0}, - {"R_X86_64_COPY", Const, 0}, - {"R_X86_64_DTPMOD64", Const, 0}, - {"R_X86_64_DTPOFF32", Const, 0}, - {"R_X86_64_DTPOFF64", Const, 0}, - {"R_X86_64_GLOB_DAT", Const, 0}, - {"R_X86_64_GOT32", Const, 0}, - {"R_X86_64_GOT64", Const, 10}, - {"R_X86_64_GOTOFF64", Const, 10}, - {"R_X86_64_GOTPC32", Const, 10}, - {"R_X86_64_GOTPC32_TLSDESC", Const, 10}, - {"R_X86_64_GOTPC64", Const, 10}, - {"R_X86_64_GOTPCREL", Const, 0}, - {"R_X86_64_GOTPCREL64", Const, 10}, - {"R_X86_64_GOTPCRELX", Const, 10}, - {"R_X86_64_GOTPLT64", Const, 10}, - {"R_X86_64_GOTTPOFF", Const, 0}, - {"R_X86_64_IRELATIVE", Const, 10}, - {"R_X86_64_JMP_SLOT", Const, 0}, - {"R_X86_64_NONE", Const, 0}, - {"R_X86_64_PC16", Const, 0}, - {"R_X86_64_PC32", Const, 0}, - {"R_X86_64_PC32_BND", Const, 10}, - {"R_X86_64_PC64", Const, 10}, - {"R_X86_64_PC8", Const, 0}, - {"R_X86_64_PLT32", Const, 0}, - {"R_X86_64_PLT32_BND", Const, 10}, - {"R_X86_64_PLTOFF64", Const, 10}, - {"R_X86_64_RELATIVE", Const, 0}, - {"R_X86_64_RELATIVE64", Const, 10}, - {"R_X86_64_REX_GOTPCRELX", Const, 10}, - {"R_X86_64_SIZE32", Const, 10}, - {"R_X86_64_SIZE64", Const, 10}, - {"R_X86_64_TLSDESC", Const, 10}, - {"R_X86_64_TLSDESC_CALL", Const, 10}, - {"R_X86_64_TLSGD", Const, 0}, - {"R_X86_64_TLSLD", Const, 0}, - {"R_X86_64_TPOFF32", Const, 0}, - {"R_X86_64_TPOFF64", Const, 0}, - {"Rel32", Type, 0}, - {"Rel32.Info", Field, 0}, - {"Rel32.Off", Field, 0}, - {"Rel64", Type, 0}, - {"Rel64.Info", Field, 0}, - {"Rel64.Off", Field, 0}, - {"Rela32", Type, 0}, - {"Rela32.Addend", Field, 0}, - {"Rela32.Info", Field, 0}, - {"Rela32.Off", Field, 0}, - {"Rela64", Type, 0}, - {"Rela64.Addend", Field, 0}, - {"Rela64.Info", Field, 0}, - {"Rela64.Off", Field, 0}, - {"SHF_ALLOC", Const, 0}, - {"SHF_COMPRESSED", Const, 6}, - {"SHF_EXECINSTR", Const, 0}, - {"SHF_GROUP", Const, 0}, - {"SHF_INFO_LINK", Const, 0}, - {"SHF_LINK_ORDER", Const, 0}, - {"SHF_MASKOS", Const, 0}, - {"SHF_MASKPROC", Const, 0}, - {"SHF_MERGE", Const, 0}, - {"SHF_OS_NONCONFORMING", Const, 0}, - {"SHF_STRINGS", Const, 0}, - {"SHF_TLS", Const, 0}, - {"SHF_WRITE", Const, 0}, - {"SHN_ABS", Const, 0}, - {"SHN_COMMON", Const, 0}, - {"SHN_HIOS", Const, 0}, - {"SHN_HIPROC", Const, 0}, - {"SHN_HIRESERVE", Const, 0}, - {"SHN_LOOS", Const, 0}, - {"SHN_LOPROC", Const, 0}, - {"SHN_LORESERVE", Const, 0}, - {"SHN_UNDEF", Const, 0}, - {"SHN_XINDEX", Const, 0}, - {"SHT_DYNAMIC", Const, 0}, - {"SHT_DYNSYM", Const, 0}, - {"SHT_FINI_ARRAY", Const, 0}, - {"SHT_GNU_ATTRIBUTES", Const, 0}, - {"SHT_GNU_HASH", Const, 0}, - {"SHT_GNU_LIBLIST", Const, 0}, - {"SHT_GNU_VERDEF", Const, 0}, - {"SHT_GNU_VERNEED", Const, 0}, - {"SHT_GNU_VERSYM", Const, 0}, - {"SHT_GROUP", Const, 0}, - {"SHT_HASH", Const, 0}, - {"SHT_HIOS", Const, 0}, - {"SHT_HIPROC", Const, 0}, - {"SHT_HIUSER", Const, 0}, - {"SHT_INIT_ARRAY", Const, 0}, - {"SHT_LOOS", Const, 0}, - {"SHT_LOPROC", Const, 0}, - {"SHT_LOUSER", Const, 0}, - {"SHT_MIPS_ABIFLAGS", Const, 17}, - {"SHT_NOBITS", Const, 0}, - {"SHT_NOTE", Const, 0}, - {"SHT_NULL", Const, 0}, - {"SHT_PREINIT_ARRAY", Const, 0}, - {"SHT_PROGBITS", Const, 0}, - {"SHT_REL", Const, 0}, - {"SHT_RELA", Const, 0}, - {"SHT_RISCV_ATTRIBUTES", Const, 25}, - {"SHT_SHLIB", Const, 0}, - {"SHT_STRTAB", Const, 0}, - {"SHT_SYMTAB", Const, 0}, - {"SHT_SYMTAB_SHNDX", Const, 0}, - {"STB_GLOBAL", Const, 0}, - {"STB_HIOS", Const, 0}, - {"STB_HIPROC", Const, 0}, - {"STB_LOCAL", Const, 0}, - {"STB_LOOS", Const, 0}, - {"STB_LOPROC", Const, 0}, - {"STB_WEAK", Const, 0}, - {"STT_COMMON", Const, 0}, - {"STT_FILE", Const, 0}, - {"STT_FUNC", Const, 0}, - {"STT_GNU_IFUNC", Const, 23}, - {"STT_HIOS", Const, 0}, - {"STT_HIPROC", Const, 0}, - {"STT_LOOS", Const, 0}, - {"STT_LOPROC", Const, 0}, - {"STT_NOTYPE", Const, 0}, - {"STT_OBJECT", Const, 0}, - {"STT_RELC", Const, 23}, - {"STT_SECTION", Const, 0}, - {"STT_SRELC", Const, 23}, - {"STT_TLS", Const, 0}, - {"STV_DEFAULT", Const, 0}, - {"STV_HIDDEN", Const, 0}, - {"STV_INTERNAL", Const, 0}, - {"STV_PROTECTED", Const, 0}, - {"ST_BIND", Func, 0}, - {"ST_INFO", Func, 0}, - {"ST_TYPE", Func, 0}, - {"ST_VISIBILITY", Func, 0}, - {"Section", Type, 0}, - {"Section.ReaderAt", Field, 0}, - {"Section.SectionHeader", Field, 0}, - {"Section32", Type, 0}, - {"Section32.Addr", Field, 0}, - {"Section32.Addralign", Field, 0}, - {"Section32.Entsize", Field, 0}, - {"Section32.Flags", Field, 0}, - {"Section32.Info", Field, 0}, - {"Section32.Link", Field, 0}, - {"Section32.Name", Field, 0}, - {"Section32.Off", Field, 0}, - {"Section32.Size", Field, 0}, - {"Section32.Type", Field, 0}, - {"Section64", Type, 0}, - {"Section64.Addr", Field, 0}, - {"Section64.Addralign", Field, 0}, - {"Section64.Entsize", Field, 0}, - {"Section64.Flags", Field, 0}, - {"Section64.Info", Field, 0}, - {"Section64.Link", Field, 0}, - {"Section64.Name", Field, 0}, - {"Section64.Off", Field, 0}, - {"Section64.Size", Field, 0}, - {"Section64.Type", Field, 0}, - {"SectionFlag", Type, 0}, - {"SectionHeader", Type, 0}, - {"SectionHeader.Addr", Field, 0}, - {"SectionHeader.Addralign", Field, 0}, - {"SectionHeader.Entsize", Field, 0}, - {"SectionHeader.FileSize", Field, 6}, - {"SectionHeader.Flags", Field, 0}, - {"SectionHeader.Info", Field, 0}, - {"SectionHeader.Link", Field, 0}, - {"SectionHeader.Name", Field, 0}, - {"SectionHeader.Offset", Field, 0}, - {"SectionHeader.Size", Field, 0}, - {"SectionHeader.Type", Field, 0}, - {"SectionIndex", Type, 0}, - {"SectionType", Type, 0}, - {"Sym32", Type, 0}, - {"Sym32.Info", Field, 0}, - {"Sym32.Name", Field, 0}, - {"Sym32.Other", Field, 0}, - {"Sym32.Shndx", Field, 0}, - {"Sym32.Size", Field, 0}, - {"Sym32.Value", Field, 0}, - {"Sym32Size", Const, 0}, - {"Sym64", Type, 0}, - {"Sym64.Info", Field, 0}, - {"Sym64.Name", Field, 0}, - {"Sym64.Other", Field, 0}, - {"Sym64.Shndx", Field, 0}, - {"Sym64.Size", Field, 0}, - {"Sym64.Value", Field, 0}, - {"Sym64Size", Const, 0}, - {"SymBind", Type, 0}, - {"SymType", Type, 0}, - {"SymVis", Type, 0}, - {"Symbol", Type, 0}, - {"Symbol.HasVersion", Field, 24}, - {"Symbol.Info", Field, 0}, - {"Symbol.Library", Field, 13}, - {"Symbol.Name", Field, 0}, - {"Symbol.Other", Field, 0}, - {"Symbol.Section", Field, 0}, - {"Symbol.Size", Field, 0}, - {"Symbol.Value", Field, 0}, - {"Symbol.Version", Field, 13}, - {"Symbol.VersionIndex", Field, 24}, - {"Type", Type, 0}, - {"VER_FLG_BASE", Const, 24}, - {"VER_FLG_INFO", Const, 24}, - {"VER_FLG_WEAK", Const, 24}, - {"Version", Type, 0}, - {"VersionIndex", Type, 24}, + {"(*File).Close", Method, 0, ""}, + {"(*File).DWARF", Method, 0, ""}, + {"(*File).DynString", Method, 1, ""}, + {"(*File).DynValue", Method, 21, ""}, + {"(*File).DynamicSymbols", Method, 4, ""}, + {"(*File).DynamicVersionNeeds", Method, 24, ""}, + {"(*File).DynamicVersions", Method, 24, ""}, + {"(*File).ImportedLibraries", Method, 0, ""}, + {"(*File).ImportedSymbols", Method, 0, ""}, + {"(*File).Section", Method, 0, ""}, + {"(*File).SectionByType", Method, 0, ""}, + {"(*File).Symbols", Method, 0, ""}, + {"(*FormatError).Error", Method, 0, ""}, + {"(*Prog).Open", Method, 0, ""}, + {"(*Section).Data", Method, 0, ""}, + {"(*Section).Open", Method, 0, ""}, + {"(Class).GoString", Method, 0, ""}, + {"(Class).String", Method, 0, ""}, + {"(CompressionType).GoString", Method, 6, ""}, + {"(CompressionType).String", Method, 6, ""}, + {"(Data).GoString", Method, 0, ""}, + {"(Data).String", Method, 0, ""}, + {"(DynFlag).GoString", Method, 0, ""}, + {"(DynFlag).String", Method, 0, ""}, + {"(DynFlag1).GoString", Method, 21, ""}, + {"(DynFlag1).String", Method, 21, ""}, + {"(DynTag).GoString", Method, 0, ""}, + {"(DynTag).String", Method, 0, ""}, + {"(Machine).GoString", Method, 0, ""}, + {"(Machine).String", Method, 0, ""}, + {"(NType).GoString", Method, 0, ""}, + {"(NType).String", Method, 0, ""}, + {"(OSABI).GoString", Method, 0, ""}, + {"(OSABI).String", Method, 0, ""}, + {"(Prog).ReadAt", Method, 0, ""}, + {"(ProgFlag).GoString", Method, 0, ""}, + {"(ProgFlag).String", Method, 0, ""}, + {"(ProgType).GoString", Method, 0, ""}, + {"(ProgType).String", Method, 0, ""}, + {"(R_386).GoString", Method, 0, ""}, + {"(R_386).String", Method, 0, ""}, + {"(R_390).GoString", Method, 7, ""}, + {"(R_390).String", Method, 7, ""}, + {"(R_AARCH64).GoString", Method, 4, ""}, + {"(R_AARCH64).String", Method, 4, ""}, + {"(R_ALPHA).GoString", Method, 0, ""}, + {"(R_ALPHA).String", Method, 0, ""}, + {"(R_ARM).GoString", Method, 0, ""}, + {"(R_ARM).String", Method, 0, ""}, + {"(R_LARCH).GoString", Method, 19, ""}, + {"(R_LARCH).String", Method, 19, ""}, + {"(R_MIPS).GoString", Method, 6, ""}, + {"(R_MIPS).String", Method, 6, ""}, + {"(R_PPC).GoString", Method, 0, ""}, + {"(R_PPC).String", Method, 0, ""}, + {"(R_PPC64).GoString", Method, 5, ""}, + {"(R_PPC64).String", Method, 5, ""}, + {"(R_RISCV).GoString", Method, 11, ""}, + {"(R_RISCV).String", Method, 11, ""}, + {"(R_SPARC).GoString", Method, 0, ""}, + {"(R_SPARC).String", Method, 0, ""}, + {"(R_X86_64).GoString", Method, 0, ""}, + {"(R_X86_64).String", Method, 0, ""}, + {"(Section).ReadAt", Method, 0, ""}, + {"(SectionFlag).GoString", Method, 0, ""}, + {"(SectionFlag).String", Method, 0, ""}, + {"(SectionIndex).GoString", Method, 0, ""}, + {"(SectionIndex).String", Method, 0, ""}, + {"(SectionType).GoString", Method, 0, ""}, + {"(SectionType).String", Method, 0, ""}, + {"(SymBind).GoString", Method, 0, ""}, + {"(SymBind).String", Method, 0, ""}, + {"(SymType).GoString", Method, 0, ""}, + {"(SymType).String", Method, 0, ""}, + {"(SymVis).GoString", Method, 0, ""}, + {"(SymVis).String", Method, 0, ""}, + {"(Type).GoString", Method, 0, ""}, + {"(Type).String", Method, 0, ""}, + {"(Version).GoString", Method, 0, ""}, + {"(Version).String", Method, 0, ""}, + {"(VersionIndex).Index", Method, 24, ""}, + {"(VersionIndex).IsHidden", Method, 24, ""}, + {"ARM_MAGIC_TRAMP_NUMBER", Const, 0, ""}, + {"COMPRESS_HIOS", Const, 6, ""}, + {"COMPRESS_HIPROC", Const, 6, ""}, + {"COMPRESS_LOOS", Const, 6, ""}, + {"COMPRESS_LOPROC", Const, 6, ""}, + {"COMPRESS_ZLIB", Const, 6, ""}, + {"COMPRESS_ZSTD", Const, 21, ""}, + {"Chdr32", Type, 6, ""}, + {"Chdr32.Addralign", Field, 6, ""}, + {"Chdr32.Size", Field, 6, ""}, + {"Chdr32.Type", Field, 6, ""}, + {"Chdr64", Type, 6, ""}, + {"Chdr64.Addralign", Field, 6, ""}, + {"Chdr64.Size", Field, 6, ""}, + {"Chdr64.Type", Field, 6, ""}, + {"Class", Type, 0, ""}, + {"CompressionType", Type, 6, ""}, + {"DF_1_CONFALT", Const, 21, ""}, + {"DF_1_DIRECT", Const, 21, ""}, + {"DF_1_DISPRELDNE", Const, 21, ""}, + {"DF_1_DISPRELPND", Const, 21, ""}, + {"DF_1_EDITED", Const, 21, ""}, + {"DF_1_ENDFILTEE", Const, 21, ""}, + {"DF_1_GLOBAL", Const, 21, ""}, + {"DF_1_GLOBAUDIT", Const, 21, ""}, + {"DF_1_GROUP", Const, 21, ""}, + {"DF_1_IGNMULDEF", Const, 21, ""}, + {"DF_1_INITFIRST", Const, 21, ""}, + {"DF_1_INTERPOSE", Const, 21, ""}, + {"DF_1_KMOD", Const, 21, ""}, + {"DF_1_LOADFLTR", Const, 21, ""}, + {"DF_1_NOCOMMON", Const, 21, ""}, + {"DF_1_NODEFLIB", Const, 21, ""}, + {"DF_1_NODELETE", Const, 21, ""}, + {"DF_1_NODIRECT", Const, 21, ""}, + {"DF_1_NODUMP", Const, 21, ""}, + {"DF_1_NOHDR", Const, 21, ""}, + {"DF_1_NOKSYMS", Const, 21, ""}, + {"DF_1_NOOPEN", Const, 21, ""}, + {"DF_1_NORELOC", Const, 21, ""}, + {"DF_1_NOW", Const, 21, ""}, + {"DF_1_ORIGIN", Const, 21, ""}, + {"DF_1_PIE", Const, 21, ""}, + {"DF_1_SINGLETON", Const, 21, ""}, + {"DF_1_STUB", Const, 21, ""}, + {"DF_1_SYMINTPOSE", Const, 21, ""}, + {"DF_1_TRANS", Const, 21, ""}, + {"DF_1_WEAKFILTER", Const, 21, ""}, + {"DF_BIND_NOW", Const, 0, ""}, + {"DF_ORIGIN", Const, 0, ""}, + {"DF_STATIC_TLS", Const, 0, ""}, + {"DF_SYMBOLIC", Const, 0, ""}, + {"DF_TEXTREL", Const, 0, ""}, + {"DT_ADDRRNGHI", Const, 16, ""}, + {"DT_ADDRRNGLO", Const, 16, ""}, + {"DT_AUDIT", Const, 16, ""}, + {"DT_AUXILIARY", Const, 16, ""}, + {"DT_BIND_NOW", Const, 0, ""}, + {"DT_CHECKSUM", Const, 16, ""}, + {"DT_CONFIG", Const, 16, ""}, + {"DT_DEBUG", Const, 0, ""}, + {"DT_DEPAUDIT", Const, 16, ""}, + {"DT_ENCODING", Const, 0, ""}, + {"DT_FEATURE", Const, 16, ""}, + {"DT_FILTER", Const, 16, ""}, + {"DT_FINI", Const, 0, ""}, + {"DT_FINI_ARRAY", Const, 0, ""}, + {"DT_FINI_ARRAYSZ", Const, 0, ""}, + {"DT_FLAGS", Const, 0, ""}, + {"DT_FLAGS_1", Const, 16, ""}, + {"DT_GNU_CONFLICT", Const, 16, ""}, + {"DT_GNU_CONFLICTSZ", Const, 16, ""}, + {"DT_GNU_HASH", Const, 16, ""}, + {"DT_GNU_LIBLIST", Const, 16, ""}, + {"DT_GNU_LIBLISTSZ", Const, 16, ""}, + {"DT_GNU_PRELINKED", Const, 16, ""}, + {"DT_HASH", Const, 0, ""}, + {"DT_HIOS", Const, 0, ""}, + {"DT_HIPROC", Const, 0, ""}, + {"DT_INIT", Const, 0, ""}, + {"DT_INIT_ARRAY", Const, 0, ""}, + {"DT_INIT_ARRAYSZ", Const, 0, ""}, + {"DT_JMPREL", Const, 0, ""}, + {"DT_LOOS", Const, 0, ""}, + {"DT_LOPROC", Const, 0, ""}, + {"DT_MIPS_AUX_DYNAMIC", Const, 16, ""}, + {"DT_MIPS_BASE_ADDRESS", Const, 16, ""}, + {"DT_MIPS_COMPACT_SIZE", Const, 16, ""}, + {"DT_MIPS_CONFLICT", Const, 16, ""}, + {"DT_MIPS_CONFLICTNO", Const, 16, ""}, + {"DT_MIPS_CXX_FLAGS", Const, 16, ""}, + {"DT_MIPS_DELTA_CLASS", Const, 16, ""}, + {"DT_MIPS_DELTA_CLASSSYM", Const, 16, ""}, + {"DT_MIPS_DELTA_CLASSSYM_NO", Const, 16, ""}, + {"DT_MIPS_DELTA_CLASS_NO", Const, 16, ""}, + {"DT_MIPS_DELTA_INSTANCE", Const, 16, ""}, + {"DT_MIPS_DELTA_INSTANCE_NO", Const, 16, ""}, + {"DT_MIPS_DELTA_RELOC", Const, 16, ""}, + {"DT_MIPS_DELTA_RELOC_NO", Const, 16, ""}, + {"DT_MIPS_DELTA_SYM", Const, 16, ""}, + {"DT_MIPS_DELTA_SYM_NO", Const, 16, ""}, + {"DT_MIPS_DYNSTR_ALIGN", Const, 16, ""}, + {"DT_MIPS_FLAGS", Const, 16, ""}, + {"DT_MIPS_GOTSYM", Const, 16, ""}, + {"DT_MIPS_GP_VALUE", Const, 16, ""}, + {"DT_MIPS_HIDDEN_GOTIDX", Const, 16, ""}, + {"DT_MIPS_HIPAGENO", Const, 16, ""}, + {"DT_MIPS_ICHECKSUM", Const, 16, ""}, + {"DT_MIPS_INTERFACE", Const, 16, ""}, + {"DT_MIPS_INTERFACE_SIZE", Const, 16, ""}, + {"DT_MIPS_IVERSION", Const, 16, ""}, + {"DT_MIPS_LIBLIST", Const, 16, ""}, + {"DT_MIPS_LIBLISTNO", Const, 16, ""}, + {"DT_MIPS_LOCALPAGE_GOTIDX", Const, 16, ""}, + {"DT_MIPS_LOCAL_GOTIDX", Const, 16, ""}, + {"DT_MIPS_LOCAL_GOTNO", Const, 16, ""}, + {"DT_MIPS_MSYM", Const, 16, ""}, + {"DT_MIPS_OPTIONS", Const, 16, ""}, + {"DT_MIPS_PERF_SUFFIX", Const, 16, ""}, + {"DT_MIPS_PIXIE_INIT", Const, 16, ""}, + {"DT_MIPS_PLTGOT", Const, 16, ""}, + {"DT_MIPS_PROTECTED_GOTIDX", Const, 16, ""}, + {"DT_MIPS_RLD_MAP", Const, 16, ""}, + {"DT_MIPS_RLD_MAP_REL", Const, 16, ""}, + {"DT_MIPS_RLD_TEXT_RESOLVE_ADDR", Const, 16, ""}, + {"DT_MIPS_RLD_VERSION", Const, 16, ""}, + {"DT_MIPS_RWPLT", Const, 16, ""}, + {"DT_MIPS_SYMBOL_LIB", Const, 16, ""}, + {"DT_MIPS_SYMTABNO", Const, 16, ""}, + {"DT_MIPS_TIME_STAMP", Const, 16, ""}, + {"DT_MIPS_UNREFEXTNO", Const, 16, ""}, + {"DT_MOVEENT", Const, 16, ""}, + {"DT_MOVESZ", Const, 16, ""}, + {"DT_MOVETAB", Const, 16, ""}, + {"DT_NEEDED", Const, 0, ""}, + {"DT_NULL", Const, 0, ""}, + {"DT_PLTGOT", Const, 0, ""}, + {"DT_PLTPAD", Const, 16, ""}, + {"DT_PLTPADSZ", Const, 16, ""}, + {"DT_PLTREL", Const, 0, ""}, + {"DT_PLTRELSZ", Const, 0, ""}, + {"DT_POSFLAG_1", Const, 16, ""}, + {"DT_PPC64_GLINK", Const, 16, ""}, + {"DT_PPC64_OPD", Const, 16, ""}, + {"DT_PPC64_OPDSZ", Const, 16, ""}, + {"DT_PPC64_OPT", Const, 16, ""}, + {"DT_PPC_GOT", Const, 16, ""}, + {"DT_PPC_OPT", Const, 16, ""}, + {"DT_PREINIT_ARRAY", Const, 0, ""}, + {"DT_PREINIT_ARRAYSZ", Const, 0, ""}, + {"DT_REL", Const, 0, ""}, + {"DT_RELA", Const, 0, ""}, + {"DT_RELACOUNT", Const, 16, ""}, + {"DT_RELAENT", Const, 0, ""}, + {"DT_RELASZ", Const, 0, ""}, + {"DT_RELCOUNT", Const, 16, ""}, + {"DT_RELENT", Const, 0, ""}, + {"DT_RELSZ", Const, 0, ""}, + {"DT_RPATH", Const, 0, ""}, + {"DT_RUNPATH", Const, 0, ""}, + {"DT_SONAME", Const, 0, ""}, + {"DT_SPARC_REGISTER", Const, 16, ""}, + {"DT_STRSZ", Const, 0, ""}, + {"DT_STRTAB", Const, 0, ""}, + {"DT_SYMBOLIC", Const, 0, ""}, + {"DT_SYMENT", Const, 0, ""}, + {"DT_SYMINENT", Const, 16, ""}, + {"DT_SYMINFO", Const, 16, ""}, + {"DT_SYMINSZ", Const, 16, ""}, + {"DT_SYMTAB", Const, 0, ""}, + {"DT_SYMTAB_SHNDX", Const, 16, ""}, + {"DT_TEXTREL", Const, 0, ""}, + {"DT_TLSDESC_GOT", Const, 16, ""}, + {"DT_TLSDESC_PLT", Const, 16, ""}, + {"DT_USED", Const, 16, ""}, + {"DT_VALRNGHI", Const, 16, ""}, + {"DT_VALRNGLO", Const, 16, ""}, + {"DT_VERDEF", Const, 16, ""}, + {"DT_VERDEFNUM", Const, 16, ""}, + {"DT_VERNEED", Const, 0, ""}, + {"DT_VERNEEDNUM", Const, 0, ""}, + {"DT_VERSYM", Const, 0, ""}, + {"Data", Type, 0, ""}, + {"Dyn32", Type, 0, ""}, + {"Dyn32.Tag", Field, 0, ""}, + {"Dyn32.Val", Field, 0, ""}, + {"Dyn64", Type, 0, ""}, + {"Dyn64.Tag", Field, 0, ""}, + {"Dyn64.Val", Field, 0, ""}, + {"DynFlag", Type, 0, ""}, + {"DynFlag1", Type, 21, ""}, + {"DynTag", Type, 0, ""}, + {"DynamicVersion", Type, 24, ""}, + {"DynamicVersion.Deps", Field, 24, ""}, + {"DynamicVersion.Flags", Field, 24, ""}, + {"DynamicVersion.Index", Field, 24, ""}, + {"DynamicVersion.Name", Field, 24, ""}, + {"DynamicVersionDep", Type, 24, ""}, + {"DynamicVersionDep.Dep", Field, 24, ""}, + {"DynamicVersionDep.Flags", Field, 24, ""}, + {"DynamicVersionDep.Index", Field, 24, ""}, + {"DynamicVersionFlag", Type, 24, ""}, + {"DynamicVersionNeed", Type, 24, ""}, + {"DynamicVersionNeed.Name", Field, 24, ""}, + {"DynamicVersionNeed.Needs", Field, 24, ""}, + {"EI_ABIVERSION", Const, 0, ""}, + {"EI_CLASS", Const, 0, ""}, + {"EI_DATA", Const, 0, ""}, + {"EI_NIDENT", Const, 0, ""}, + {"EI_OSABI", Const, 0, ""}, + {"EI_PAD", Const, 0, ""}, + {"EI_VERSION", Const, 0, ""}, + {"ELFCLASS32", Const, 0, ""}, + {"ELFCLASS64", Const, 0, ""}, + {"ELFCLASSNONE", Const, 0, ""}, + {"ELFDATA2LSB", Const, 0, ""}, + {"ELFDATA2MSB", Const, 0, ""}, + {"ELFDATANONE", Const, 0, ""}, + {"ELFMAG", Const, 0, ""}, + {"ELFOSABI_86OPEN", Const, 0, ""}, + {"ELFOSABI_AIX", Const, 0, ""}, + {"ELFOSABI_ARM", Const, 0, ""}, + {"ELFOSABI_AROS", Const, 11, ""}, + {"ELFOSABI_CLOUDABI", Const, 11, ""}, + {"ELFOSABI_FENIXOS", Const, 11, ""}, + {"ELFOSABI_FREEBSD", Const, 0, ""}, + {"ELFOSABI_HPUX", Const, 0, ""}, + {"ELFOSABI_HURD", Const, 0, ""}, + {"ELFOSABI_IRIX", Const, 0, ""}, + {"ELFOSABI_LINUX", Const, 0, ""}, + {"ELFOSABI_MODESTO", Const, 0, ""}, + {"ELFOSABI_NETBSD", Const, 0, ""}, + {"ELFOSABI_NONE", Const, 0, ""}, + {"ELFOSABI_NSK", Const, 0, ""}, + {"ELFOSABI_OPENBSD", Const, 0, ""}, + {"ELFOSABI_OPENVMS", Const, 0, ""}, + {"ELFOSABI_SOLARIS", Const, 0, ""}, + {"ELFOSABI_STANDALONE", Const, 0, ""}, + {"ELFOSABI_TRU64", Const, 0, ""}, + {"EM_386", Const, 0, ""}, + {"EM_486", Const, 0, ""}, + {"EM_56800EX", Const, 11, ""}, + {"EM_68HC05", Const, 11, ""}, + {"EM_68HC08", Const, 11, ""}, + {"EM_68HC11", Const, 11, ""}, + {"EM_68HC12", Const, 0, ""}, + {"EM_68HC16", Const, 11, ""}, + {"EM_68K", Const, 0, ""}, + {"EM_78KOR", Const, 11, ""}, + {"EM_8051", Const, 11, ""}, + {"EM_860", Const, 0, ""}, + {"EM_88K", Const, 0, ""}, + {"EM_960", Const, 0, ""}, + {"EM_AARCH64", Const, 4, ""}, + {"EM_ALPHA", Const, 0, ""}, + {"EM_ALPHA_STD", Const, 0, ""}, + {"EM_ALTERA_NIOS2", Const, 11, ""}, + {"EM_AMDGPU", Const, 11, ""}, + {"EM_ARC", Const, 0, ""}, + {"EM_ARCA", Const, 11, ""}, + {"EM_ARC_COMPACT", Const, 11, ""}, + {"EM_ARC_COMPACT2", Const, 11, ""}, + {"EM_ARM", Const, 0, ""}, + {"EM_AVR", Const, 11, ""}, + {"EM_AVR32", Const, 11, ""}, + {"EM_BA1", Const, 11, ""}, + {"EM_BA2", Const, 11, ""}, + {"EM_BLACKFIN", Const, 11, ""}, + {"EM_BPF", Const, 11, ""}, + {"EM_C166", Const, 11, ""}, + {"EM_CDP", Const, 11, ""}, + {"EM_CE", Const, 11, ""}, + {"EM_CLOUDSHIELD", Const, 11, ""}, + {"EM_COGE", Const, 11, ""}, + {"EM_COLDFIRE", Const, 0, ""}, + {"EM_COOL", Const, 11, ""}, + {"EM_COREA_1ST", Const, 11, ""}, + {"EM_COREA_2ND", Const, 11, ""}, + {"EM_CR", Const, 11, ""}, + {"EM_CR16", Const, 11, ""}, + {"EM_CRAYNV2", Const, 11, ""}, + {"EM_CRIS", Const, 11, ""}, + {"EM_CRX", Const, 11, ""}, + {"EM_CSR_KALIMBA", Const, 11, ""}, + {"EM_CUDA", Const, 11, ""}, + {"EM_CYPRESS_M8C", Const, 11, ""}, + {"EM_D10V", Const, 11, ""}, + {"EM_D30V", Const, 11, ""}, + {"EM_DSP24", Const, 11, ""}, + {"EM_DSPIC30F", Const, 11, ""}, + {"EM_DXP", Const, 11, ""}, + {"EM_ECOG1", Const, 11, ""}, + {"EM_ECOG16", Const, 11, ""}, + {"EM_ECOG1X", Const, 11, ""}, + {"EM_ECOG2", Const, 11, ""}, + {"EM_ETPU", Const, 11, ""}, + {"EM_EXCESS", Const, 11, ""}, + {"EM_F2MC16", Const, 11, ""}, + {"EM_FIREPATH", Const, 11, ""}, + {"EM_FR20", Const, 0, ""}, + {"EM_FR30", Const, 11, ""}, + {"EM_FT32", Const, 11, ""}, + {"EM_FX66", Const, 11, ""}, + {"EM_H8S", Const, 0, ""}, + {"EM_H8_300", Const, 0, ""}, + {"EM_H8_300H", Const, 0, ""}, + {"EM_H8_500", Const, 0, ""}, + {"EM_HUANY", Const, 11, ""}, + {"EM_IA_64", Const, 0, ""}, + {"EM_INTEL205", Const, 11, ""}, + {"EM_INTEL206", Const, 11, ""}, + {"EM_INTEL207", Const, 11, ""}, + {"EM_INTEL208", Const, 11, ""}, + {"EM_INTEL209", Const, 11, ""}, + {"EM_IP2K", Const, 11, ""}, + {"EM_JAVELIN", Const, 11, ""}, + {"EM_K10M", Const, 11, ""}, + {"EM_KM32", Const, 11, ""}, + {"EM_KMX16", Const, 11, ""}, + {"EM_KMX32", Const, 11, ""}, + {"EM_KMX8", Const, 11, ""}, + {"EM_KVARC", Const, 11, ""}, + {"EM_L10M", Const, 11, ""}, + {"EM_LANAI", Const, 11, ""}, + {"EM_LATTICEMICO32", Const, 11, ""}, + {"EM_LOONGARCH", Const, 19, ""}, + {"EM_M16C", Const, 11, ""}, + {"EM_M32", Const, 0, ""}, + {"EM_M32C", Const, 11, ""}, + {"EM_M32R", Const, 11, ""}, + {"EM_MANIK", Const, 11, ""}, + {"EM_MAX", Const, 11, ""}, + {"EM_MAXQ30", Const, 11, ""}, + {"EM_MCHP_PIC", Const, 11, ""}, + {"EM_MCST_ELBRUS", Const, 11, ""}, + {"EM_ME16", Const, 0, ""}, + {"EM_METAG", Const, 11, ""}, + {"EM_MICROBLAZE", Const, 11, ""}, + {"EM_MIPS", Const, 0, ""}, + {"EM_MIPS_RS3_LE", Const, 0, ""}, + {"EM_MIPS_RS4_BE", Const, 0, ""}, + {"EM_MIPS_X", Const, 0, ""}, + {"EM_MMA", Const, 0, ""}, + {"EM_MMDSP_PLUS", Const, 11, ""}, + {"EM_MMIX", Const, 11, ""}, + {"EM_MN10200", Const, 11, ""}, + {"EM_MN10300", Const, 11, ""}, + {"EM_MOXIE", Const, 11, ""}, + {"EM_MSP430", Const, 11, ""}, + {"EM_NCPU", Const, 0, ""}, + {"EM_NDR1", Const, 0, ""}, + {"EM_NDS32", Const, 11, ""}, + {"EM_NONE", Const, 0, ""}, + {"EM_NORC", Const, 11, ""}, + {"EM_NS32K", Const, 11, ""}, + {"EM_OPEN8", Const, 11, ""}, + {"EM_OPENRISC", Const, 11, ""}, + {"EM_PARISC", Const, 0, ""}, + {"EM_PCP", Const, 0, ""}, + {"EM_PDP10", Const, 11, ""}, + {"EM_PDP11", Const, 11, ""}, + {"EM_PDSP", Const, 11, ""}, + {"EM_PJ", Const, 11, ""}, + {"EM_PPC", Const, 0, ""}, + {"EM_PPC64", Const, 0, ""}, + {"EM_PRISM", Const, 11, ""}, + {"EM_QDSP6", Const, 11, ""}, + {"EM_R32C", Const, 11, ""}, + {"EM_RCE", Const, 0, ""}, + {"EM_RH32", Const, 0, ""}, + {"EM_RISCV", Const, 11, ""}, + {"EM_RL78", Const, 11, ""}, + {"EM_RS08", Const, 11, ""}, + {"EM_RX", Const, 11, ""}, + {"EM_S370", Const, 0, ""}, + {"EM_S390", Const, 0, ""}, + {"EM_SCORE7", Const, 11, ""}, + {"EM_SEP", Const, 11, ""}, + {"EM_SE_C17", Const, 11, ""}, + {"EM_SE_C33", Const, 11, ""}, + {"EM_SH", Const, 0, ""}, + {"EM_SHARC", Const, 11, ""}, + {"EM_SLE9X", Const, 11, ""}, + {"EM_SNP1K", Const, 11, ""}, + {"EM_SPARC", Const, 0, ""}, + {"EM_SPARC32PLUS", Const, 0, ""}, + {"EM_SPARCV9", Const, 0, ""}, + {"EM_ST100", Const, 0, ""}, + {"EM_ST19", Const, 11, ""}, + {"EM_ST200", Const, 11, ""}, + {"EM_ST7", Const, 11, ""}, + {"EM_ST9PLUS", Const, 11, ""}, + {"EM_STARCORE", Const, 0, ""}, + {"EM_STM8", Const, 11, ""}, + {"EM_STXP7X", Const, 11, ""}, + {"EM_SVX", Const, 11, ""}, + {"EM_TILE64", Const, 11, ""}, + {"EM_TILEGX", Const, 11, ""}, + {"EM_TILEPRO", Const, 11, ""}, + {"EM_TINYJ", Const, 0, ""}, + {"EM_TI_ARP32", Const, 11, ""}, + {"EM_TI_C2000", Const, 11, ""}, + {"EM_TI_C5500", Const, 11, ""}, + {"EM_TI_C6000", Const, 11, ""}, + {"EM_TI_PRU", Const, 11, ""}, + {"EM_TMM_GPP", Const, 11, ""}, + {"EM_TPC", Const, 11, ""}, + {"EM_TRICORE", Const, 0, ""}, + {"EM_TRIMEDIA", Const, 11, ""}, + {"EM_TSK3000", Const, 11, ""}, + {"EM_UNICORE", Const, 11, ""}, + {"EM_V800", Const, 0, ""}, + {"EM_V850", Const, 11, ""}, + {"EM_VAX", Const, 11, ""}, + {"EM_VIDEOCORE", Const, 11, ""}, + {"EM_VIDEOCORE3", Const, 11, ""}, + {"EM_VIDEOCORE5", Const, 11, ""}, + {"EM_VISIUM", Const, 11, ""}, + {"EM_VPP500", Const, 0, ""}, + {"EM_X86_64", Const, 0, ""}, + {"EM_XCORE", Const, 11, ""}, + {"EM_XGATE", Const, 11, ""}, + {"EM_XIMO16", Const, 11, ""}, + {"EM_XTENSA", Const, 11, ""}, + {"EM_Z80", Const, 11, ""}, + {"EM_ZSP", Const, 11, ""}, + {"ET_CORE", Const, 0, ""}, + {"ET_DYN", Const, 0, ""}, + {"ET_EXEC", Const, 0, ""}, + {"ET_HIOS", Const, 0, ""}, + {"ET_HIPROC", Const, 0, ""}, + {"ET_LOOS", Const, 0, ""}, + {"ET_LOPROC", Const, 0, ""}, + {"ET_NONE", Const, 0, ""}, + {"ET_REL", Const, 0, ""}, + {"EV_CURRENT", Const, 0, ""}, + {"EV_NONE", Const, 0, ""}, + {"ErrNoSymbols", Var, 4, ""}, + {"File", Type, 0, ""}, + {"File.FileHeader", Field, 0, ""}, + {"File.Progs", Field, 0, ""}, + {"File.Sections", Field, 0, ""}, + {"FileHeader", Type, 0, ""}, + {"FileHeader.ABIVersion", Field, 0, ""}, + {"FileHeader.ByteOrder", Field, 0, ""}, + {"FileHeader.Class", Field, 0, ""}, + {"FileHeader.Data", Field, 0, ""}, + {"FileHeader.Entry", Field, 1, ""}, + {"FileHeader.Machine", Field, 0, ""}, + {"FileHeader.OSABI", Field, 0, ""}, + {"FileHeader.Type", Field, 0, ""}, + {"FileHeader.Version", Field, 0, ""}, + {"FormatError", Type, 0, ""}, + {"Header32", Type, 0, ""}, + {"Header32.Ehsize", Field, 0, ""}, + {"Header32.Entry", Field, 0, ""}, + {"Header32.Flags", Field, 0, ""}, + {"Header32.Ident", Field, 0, ""}, + {"Header32.Machine", Field, 0, ""}, + {"Header32.Phentsize", Field, 0, ""}, + {"Header32.Phnum", Field, 0, ""}, + {"Header32.Phoff", Field, 0, ""}, + {"Header32.Shentsize", Field, 0, ""}, + {"Header32.Shnum", Field, 0, ""}, + {"Header32.Shoff", Field, 0, ""}, + {"Header32.Shstrndx", Field, 0, ""}, + {"Header32.Type", Field, 0, ""}, + {"Header32.Version", Field, 0, ""}, + {"Header64", Type, 0, ""}, + {"Header64.Ehsize", Field, 0, ""}, + {"Header64.Entry", Field, 0, ""}, + {"Header64.Flags", Field, 0, ""}, + {"Header64.Ident", Field, 0, ""}, + {"Header64.Machine", Field, 0, ""}, + {"Header64.Phentsize", Field, 0, ""}, + {"Header64.Phnum", Field, 0, ""}, + {"Header64.Phoff", Field, 0, ""}, + {"Header64.Shentsize", Field, 0, ""}, + {"Header64.Shnum", Field, 0, ""}, + {"Header64.Shoff", Field, 0, ""}, + {"Header64.Shstrndx", Field, 0, ""}, + {"Header64.Type", Field, 0, ""}, + {"Header64.Version", Field, 0, ""}, + {"ImportedSymbol", Type, 0, ""}, + {"ImportedSymbol.Library", Field, 0, ""}, + {"ImportedSymbol.Name", Field, 0, ""}, + {"ImportedSymbol.Version", Field, 0, ""}, + {"Machine", Type, 0, ""}, + {"NT_FPREGSET", Const, 0, ""}, + {"NT_PRPSINFO", Const, 0, ""}, + {"NT_PRSTATUS", Const, 0, ""}, + {"NType", Type, 0, ""}, + {"NewFile", Func, 0, "func(r io.ReaderAt) (*File, error)"}, + {"OSABI", Type, 0, ""}, + {"Open", Func, 0, "func(name string) (*File, error)"}, + {"PF_MASKOS", Const, 0, ""}, + {"PF_MASKPROC", Const, 0, ""}, + {"PF_R", Const, 0, ""}, + {"PF_W", Const, 0, ""}, + {"PF_X", Const, 0, ""}, + {"PT_AARCH64_ARCHEXT", Const, 16, ""}, + {"PT_AARCH64_UNWIND", Const, 16, ""}, + {"PT_ARM_ARCHEXT", Const, 16, ""}, + {"PT_ARM_EXIDX", Const, 16, ""}, + {"PT_DYNAMIC", Const, 0, ""}, + {"PT_GNU_EH_FRAME", Const, 16, ""}, + {"PT_GNU_MBIND_HI", Const, 16, ""}, + {"PT_GNU_MBIND_LO", Const, 16, ""}, + {"PT_GNU_PROPERTY", Const, 16, ""}, + {"PT_GNU_RELRO", Const, 16, ""}, + {"PT_GNU_STACK", Const, 16, ""}, + {"PT_HIOS", Const, 0, ""}, + {"PT_HIPROC", Const, 0, ""}, + {"PT_INTERP", Const, 0, ""}, + {"PT_LOAD", Const, 0, ""}, + {"PT_LOOS", Const, 0, ""}, + {"PT_LOPROC", Const, 0, ""}, + {"PT_MIPS_ABIFLAGS", Const, 16, ""}, + {"PT_MIPS_OPTIONS", Const, 16, ""}, + {"PT_MIPS_REGINFO", Const, 16, ""}, + {"PT_MIPS_RTPROC", Const, 16, ""}, + {"PT_NOTE", Const, 0, ""}, + {"PT_NULL", Const, 0, ""}, + {"PT_OPENBSD_BOOTDATA", Const, 16, ""}, + {"PT_OPENBSD_NOBTCFI", Const, 23, ""}, + {"PT_OPENBSD_RANDOMIZE", Const, 16, ""}, + {"PT_OPENBSD_WXNEEDED", Const, 16, ""}, + {"PT_PAX_FLAGS", Const, 16, ""}, + {"PT_PHDR", Const, 0, ""}, + {"PT_RISCV_ATTRIBUTES", Const, 25, ""}, + {"PT_S390_PGSTE", Const, 16, ""}, + {"PT_SHLIB", Const, 0, ""}, + {"PT_SUNWSTACK", Const, 16, ""}, + {"PT_SUNW_EH_FRAME", Const, 16, ""}, + {"PT_TLS", Const, 0, ""}, + {"Prog", Type, 0, ""}, + {"Prog.ProgHeader", Field, 0, ""}, + {"Prog.ReaderAt", Field, 0, ""}, + {"Prog32", Type, 0, ""}, + {"Prog32.Align", Field, 0, ""}, + {"Prog32.Filesz", Field, 0, ""}, + {"Prog32.Flags", Field, 0, ""}, + {"Prog32.Memsz", Field, 0, ""}, + {"Prog32.Off", Field, 0, ""}, + {"Prog32.Paddr", Field, 0, ""}, + {"Prog32.Type", Field, 0, ""}, + {"Prog32.Vaddr", Field, 0, ""}, + {"Prog64", Type, 0, ""}, + {"Prog64.Align", Field, 0, ""}, + {"Prog64.Filesz", Field, 0, ""}, + {"Prog64.Flags", Field, 0, ""}, + {"Prog64.Memsz", Field, 0, ""}, + {"Prog64.Off", Field, 0, ""}, + {"Prog64.Paddr", Field, 0, ""}, + {"Prog64.Type", Field, 0, ""}, + {"Prog64.Vaddr", Field, 0, ""}, + {"ProgFlag", Type, 0, ""}, + {"ProgHeader", Type, 0, ""}, + {"ProgHeader.Align", Field, 0, ""}, + {"ProgHeader.Filesz", Field, 0, ""}, + {"ProgHeader.Flags", Field, 0, ""}, + {"ProgHeader.Memsz", Field, 0, ""}, + {"ProgHeader.Off", Field, 0, ""}, + {"ProgHeader.Paddr", Field, 0, ""}, + {"ProgHeader.Type", Field, 0, ""}, + {"ProgHeader.Vaddr", Field, 0, ""}, + {"ProgType", Type, 0, ""}, + {"R_386", Type, 0, ""}, + {"R_386_16", Const, 10, ""}, + {"R_386_32", Const, 0, ""}, + {"R_386_32PLT", Const, 10, ""}, + {"R_386_8", Const, 10, ""}, + {"R_386_COPY", Const, 0, ""}, + {"R_386_GLOB_DAT", Const, 0, ""}, + {"R_386_GOT32", Const, 0, ""}, + {"R_386_GOT32X", Const, 10, ""}, + {"R_386_GOTOFF", Const, 0, ""}, + {"R_386_GOTPC", Const, 0, ""}, + {"R_386_IRELATIVE", Const, 10, ""}, + {"R_386_JMP_SLOT", Const, 0, ""}, + {"R_386_NONE", Const, 0, ""}, + {"R_386_PC16", Const, 10, ""}, + {"R_386_PC32", Const, 0, ""}, + {"R_386_PC8", Const, 10, ""}, + {"R_386_PLT32", Const, 0, ""}, + {"R_386_RELATIVE", Const, 0, ""}, + {"R_386_SIZE32", Const, 10, ""}, + {"R_386_TLS_DESC", Const, 10, ""}, + {"R_386_TLS_DESC_CALL", Const, 10, ""}, + {"R_386_TLS_DTPMOD32", Const, 0, ""}, + {"R_386_TLS_DTPOFF32", Const, 0, ""}, + {"R_386_TLS_GD", Const, 0, ""}, + {"R_386_TLS_GD_32", Const, 0, ""}, + {"R_386_TLS_GD_CALL", Const, 0, ""}, + {"R_386_TLS_GD_POP", Const, 0, ""}, + {"R_386_TLS_GD_PUSH", Const, 0, ""}, + {"R_386_TLS_GOTDESC", Const, 10, ""}, + {"R_386_TLS_GOTIE", Const, 0, ""}, + {"R_386_TLS_IE", Const, 0, ""}, + {"R_386_TLS_IE_32", Const, 0, ""}, + {"R_386_TLS_LDM", Const, 0, ""}, + {"R_386_TLS_LDM_32", Const, 0, ""}, + {"R_386_TLS_LDM_CALL", Const, 0, ""}, + {"R_386_TLS_LDM_POP", Const, 0, ""}, + {"R_386_TLS_LDM_PUSH", Const, 0, ""}, + {"R_386_TLS_LDO_32", Const, 0, ""}, + {"R_386_TLS_LE", Const, 0, ""}, + {"R_386_TLS_LE_32", Const, 0, ""}, + {"R_386_TLS_TPOFF", Const, 0, ""}, + {"R_386_TLS_TPOFF32", Const, 0, ""}, + {"R_390", Type, 7, ""}, + {"R_390_12", Const, 7, ""}, + {"R_390_16", Const, 7, ""}, + {"R_390_20", Const, 7, ""}, + {"R_390_32", Const, 7, ""}, + {"R_390_64", Const, 7, ""}, + {"R_390_8", Const, 7, ""}, + {"R_390_COPY", Const, 7, ""}, + {"R_390_GLOB_DAT", Const, 7, ""}, + {"R_390_GOT12", Const, 7, ""}, + {"R_390_GOT16", Const, 7, ""}, + {"R_390_GOT20", Const, 7, ""}, + {"R_390_GOT32", Const, 7, ""}, + {"R_390_GOT64", Const, 7, ""}, + {"R_390_GOTENT", Const, 7, ""}, + {"R_390_GOTOFF", Const, 7, ""}, + {"R_390_GOTOFF16", Const, 7, ""}, + {"R_390_GOTOFF64", Const, 7, ""}, + {"R_390_GOTPC", Const, 7, ""}, + {"R_390_GOTPCDBL", Const, 7, ""}, + {"R_390_GOTPLT12", Const, 7, ""}, + {"R_390_GOTPLT16", Const, 7, ""}, + {"R_390_GOTPLT20", Const, 7, ""}, + {"R_390_GOTPLT32", Const, 7, ""}, + {"R_390_GOTPLT64", Const, 7, ""}, + {"R_390_GOTPLTENT", Const, 7, ""}, + {"R_390_GOTPLTOFF16", Const, 7, ""}, + {"R_390_GOTPLTOFF32", Const, 7, ""}, + {"R_390_GOTPLTOFF64", Const, 7, ""}, + {"R_390_JMP_SLOT", Const, 7, ""}, + {"R_390_NONE", Const, 7, ""}, + {"R_390_PC16", Const, 7, ""}, + {"R_390_PC16DBL", Const, 7, ""}, + {"R_390_PC32", Const, 7, ""}, + {"R_390_PC32DBL", Const, 7, ""}, + {"R_390_PC64", Const, 7, ""}, + {"R_390_PLT16DBL", Const, 7, ""}, + {"R_390_PLT32", Const, 7, ""}, + {"R_390_PLT32DBL", Const, 7, ""}, + {"R_390_PLT64", Const, 7, ""}, + {"R_390_RELATIVE", Const, 7, ""}, + {"R_390_TLS_DTPMOD", Const, 7, ""}, + {"R_390_TLS_DTPOFF", Const, 7, ""}, + {"R_390_TLS_GD32", Const, 7, ""}, + {"R_390_TLS_GD64", Const, 7, ""}, + {"R_390_TLS_GDCALL", Const, 7, ""}, + {"R_390_TLS_GOTIE12", Const, 7, ""}, + {"R_390_TLS_GOTIE20", Const, 7, ""}, + {"R_390_TLS_GOTIE32", Const, 7, ""}, + {"R_390_TLS_GOTIE64", Const, 7, ""}, + {"R_390_TLS_IE32", Const, 7, ""}, + {"R_390_TLS_IE64", Const, 7, ""}, + {"R_390_TLS_IEENT", Const, 7, ""}, + {"R_390_TLS_LDCALL", Const, 7, ""}, + {"R_390_TLS_LDM32", Const, 7, ""}, + {"R_390_TLS_LDM64", Const, 7, ""}, + {"R_390_TLS_LDO32", Const, 7, ""}, + {"R_390_TLS_LDO64", Const, 7, ""}, + {"R_390_TLS_LE32", Const, 7, ""}, + {"R_390_TLS_LE64", Const, 7, ""}, + {"R_390_TLS_LOAD", Const, 7, ""}, + {"R_390_TLS_TPOFF", Const, 7, ""}, + {"R_AARCH64", Type, 4, ""}, + {"R_AARCH64_ABS16", Const, 4, ""}, + {"R_AARCH64_ABS32", Const, 4, ""}, + {"R_AARCH64_ABS64", Const, 4, ""}, + {"R_AARCH64_ADD_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_ADR_GOT_PAGE", Const, 4, ""}, + {"R_AARCH64_ADR_PREL_LO21", Const, 4, ""}, + {"R_AARCH64_ADR_PREL_PG_HI21", Const, 4, ""}, + {"R_AARCH64_ADR_PREL_PG_HI21_NC", Const, 4, ""}, + {"R_AARCH64_CALL26", Const, 4, ""}, + {"R_AARCH64_CONDBR19", Const, 4, ""}, + {"R_AARCH64_COPY", Const, 4, ""}, + {"R_AARCH64_GLOB_DAT", Const, 4, ""}, + {"R_AARCH64_GOT_LD_PREL19", Const, 4, ""}, + {"R_AARCH64_IRELATIVE", Const, 4, ""}, + {"R_AARCH64_JUMP26", Const, 4, ""}, + {"R_AARCH64_JUMP_SLOT", Const, 4, ""}, + {"R_AARCH64_LD64_GOTOFF_LO15", Const, 10, ""}, + {"R_AARCH64_LD64_GOTPAGE_LO15", Const, 10, ""}, + {"R_AARCH64_LD64_GOT_LO12_NC", Const, 4, ""}, + {"R_AARCH64_LDST128_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_LDST16_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_LDST32_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_LDST64_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_LDST8_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_LD_PREL_LO19", Const, 4, ""}, + {"R_AARCH64_MOVW_SABS_G0", Const, 4, ""}, + {"R_AARCH64_MOVW_SABS_G1", Const, 4, ""}, + {"R_AARCH64_MOVW_SABS_G2", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G0", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G0_NC", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G1", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G1_NC", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G2", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G2_NC", Const, 4, ""}, + {"R_AARCH64_MOVW_UABS_G3", Const, 4, ""}, + {"R_AARCH64_NONE", Const, 4, ""}, + {"R_AARCH64_NULL", Const, 4, ""}, + {"R_AARCH64_P32_ABS16", Const, 4, ""}, + {"R_AARCH64_P32_ABS32", Const, 4, ""}, + {"R_AARCH64_P32_ADD_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_ADR_GOT_PAGE", Const, 4, ""}, + {"R_AARCH64_P32_ADR_PREL_LO21", Const, 4, ""}, + {"R_AARCH64_P32_ADR_PREL_PG_HI21", Const, 4, ""}, + {"R_AARCH64_P32_CALL26", Const, 4, ""}, + {"R_AARCH64_P32_CONDBR19", Const, 4, ""}, + {"R_AARCH64_P32_COPY", Const, 4, ""}, + {"R_AARCH64_P32_GLOB_DAT", Const, 4, ""}, + {"R_AARCH64_P32_GOT_LD_PREL19", Const, 4, ""}, + {"R_AARCH64_P32_IRELATIVE", Const, 4, ""}, + {"R_AARCH64_P32_JUMP26", Const, 4, ""}, + {"R_AARCH64_P32_JUMP_SLOT", Const, 4, ""}, + {"R_AARCH64_P32_LD32_GOT_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_LDST128_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_LDST16_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_LDST32_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_LDST64_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_LDST8_ABS_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_LD_PREL_LO19", Const, 4, ""}, + {"R_AARCH64_P32_MOVW_SABS_G0", Const, 4, ""}, + {"R_AARCH64_P32_MOVW_UABS_G0", Const, 4, ""}, + {"R_AARCH64_P32_MOVW_UABS_G0_NC", Const, 4, ""}, + {"R_AARCH64_P32_MOVW_UABS_G1", Const, 4, ""}, + {"R_AARCH64_P32_PREL16", Const, 4, ""}, + {"R_AARCH64_P32_PREL32", Const, 4, ""}, + {"R_AARCH64_P32_RELATIVE", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC_ADD_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC_ADR_PAGE21", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC_ADR_PREL21", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC_CALL", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC_LD32_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_TLSDESC_LD_PREL19", Const, 4, ""}, + {"R_AARCH64_P32_TLSGD_ADD_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_TLSGD_ADR_PAGE21", Const, 4, ""}, + {"R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21", Const, 4, ""}, + {"R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19", Const, 4, ""}, + {"R_AARCH64_P32_TLSLE_ADD_TPREL_HI12", Const, 4, ""}, + {"R_AARCH64_P32_TLSLE_ADD_TPREL_LO12", Const, 4, ""}, + {"R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC", Const, 4, ""}, + {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G0", Const, 4, ""}, + {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC", Const, 4, ""}, + {"R_AARCH64_P32_TLSLE_MOVW_TPREL_G1", Const, 4, ""}, + {"R_AARCH64_P32_TLS_DTPMOD", Const, 4, ""}, + {"R_AARCH64_P32_TLS_DTPREL", Const, 4, ""}, + {"R_AARCH64_P32_TLS_TPREL", Const, 4, ""}, + {"R_AARCH64_P32_TSTBR14", Const, 4, ""}, + {"R_AARCH64_PREL16", Const, 4, ""}, + {"R_AARCH64_PREL32", Const, 4, ""}, + {"R_AARCH64_PREL64", Const, 4, ""}, + {"R_AARCH64_RELATIVE", Const, 4, ""}, + {"R_AARCH64_TLSDESC", Const, 4, ""}, + {"R_AARCH64_TLSDESC_ADD", Const, 4, ""}, + {"R_AARCH64_TLSDESC_ADD_LO12_NC", Const, 4, ""}, + {"R_AARCH64_TLSDESC_ADR_PAGE21", Const, 4, ""}, + {"R_AARCH64_TLSDESC_ADR_PREL21", Const, 4, ""}, + {"R_AARCH64_TLSDESC_CALL", Const, 4, ""}, + {"R_AARCH64_TLSDESC_LD64_LO12_NC", Const, 4, ""}, + {"R_AARCH64_TLSDESC_LDR", Const, 4, ""}, + {"R_AARCH64_TLSDESC_LD_PREL19", Const, 4, ""}, + {"R_AARCH64_TLSDESC_OFF_G0_NC", Const, 4, ""}, + {"R_AARCH64_TLSDESC_OFF_G1", Const, 4, ""}, + {"R_AARCH64_TLSGD_ADD_LO12_NC", Const, 4, ""}, + {"R_AARCH64_TLSGD_ADR_PAGE21", Const, 4, ""}, + {"R_AARCH64_TLSGD_ADR_PREL21", Const, 10, ""}, + {"R_AARCH64_TLSGD_MOVW_G0_NC", Const, 10, ""}, + {"R_AARCH64_TLSGD_MOVW_G1", Const, 10, ""}, + {"R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21", Const, 4, ""}, + {"R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC", Const, 4, ""}, + {"R_AARCH64_TLSIE_LD_GOTTPREL_PREL19", Const, 4, ""}, + {"R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC", Const, 4, ""}, + {"R_AARCH64_TLSIE_MOVW_GOTTPREL_G1", Const, 4, ""}, + {"R_AARCH64_TLSLD_ADR_PAGE21", Const, 10, ""}, + {"R_AARCH64_TLSLD_ADR_PREL21", Const, 10, ""}, + {"R_AARCH64_TLSLD_LDST128_DTPREL_LO12", Const, 10, ""}, + {"R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC", Const, 10, ""}, + {"R_AARCH64_TLSLE_ADD_TPREL_HI12", Const, 4, ""}, + {"R_AARCH64_TLSLE_ADD_TPREL_LO12", Const, 4, ""}, + {"R_AARCH64_TLSLE_ADD_TPREL_LO12_NC", Const, 4, ""}, + {"R_AARCH64_TLSLE_LDST128_TPREL_LO12", Const, 10, ""}, + {"R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC", Const, 10, ""}, + {"R_AARCH64_TLSLE_MOVW_TPREL_G0", Const, 4, ""}, + {"R_AARCH64_TLSLE_MOVW_TPREL_G0_NC", Const, 4, ""}, + {"R_AARCH64_TLSLE_MOVW_TPREL_G1", Const, 4, ""}, + {"R_AARCH64_TLSLE_MOVW_TPREL_G1_NC", Const, 4, ""}, + {"R_AARCH64_TLSLE_MOVW_TPREL_G2", Const, 4, ""}, + {"R_AARCH64_TLS_DTPMOD64", Const, 4, ""}, + {"R_AARCH64_TLS_DTPREL64", Const, 4, ""}, + {"R_AARCH64_TLS_TPREL64", Const, 4, ""}, + {"R_AARCH64_TSTBR14", Const, 4, ""}, + {"R_ALPHA", Type, 0, ""}, + {"R_ALPHA_BRADDR", Const, 0, ""}, + {"R_ALPHA_COPY", Const, 0, ""}, + {"R_ALPHA_GLOB_DAT", Const, 0, ""}, + {"R_ALPHA_GPDISP", Const, 0, ""}, + {"R_ALPHA_GPREL32", Const, 0, ""}, + {"R_ALPHA_GPRELHIGH", Const, 0, ""}, + {"R_ALPHA_GPRELLOW", Const, 0, ""}, + {"R_ALPHA_GPVALUE", Const, 0, ""}, + {"R_ALPHA_HINT", Const, 0, ""}, + {"R_ALPHA_IMMED_BR_HI32", Const, 0, ""}, + {"R_ALPHA_IMMED_GP_16", Const, 0, ""}, + {"R_ALPHA_IMMED_GP_HI32", Const, 0, ""}, + {"R_ALPHA_IMMED_LO32", Const, 0, ""}, + {"R_ALPHA_IMMED_SCN_HI32", Const, 0, ""}, + {"R_ALPHA_JMP_SLOT", Const, 0, ""}, + {"R_ALPHA_LITERAL", Const, 0, ""}, + {"R_ALPHA_LITUSE", Const, 0, ""}, + {"R_ALPHA_NONE", Const, 0, ""}, + {"R_ALPHA_OP_PRSHIFT", Const, 0, ""}, + {"R_ALPHA_OP_PSUB", Const, 0, ""}, + {"R_ALPHA_OP_PUSH", Const, 0, ""}, + {"R_ALPHA_OP_STORE", Const, 0, ""}, + {"R_ALPHA_REFLONG", Const, 0, ""}, + {"R_ALPHA_REFQUAD", Const, 0, ""}, + {"R_ALPHA_RELATIVE", Const, 0, ""}, + {"R_ALPHA_SREL16", Const, 0, ""}, + {"R_ALPHA_SREL32", Const, 0, ""}, + {"R_ALPHA_SREL64", Const, 0, ""}, + {"R_ARM", Type, 0, ""}, + {"R_ARM_ABS12", Const, 0, ""}, + {"R_ARM_ABS16", Const, 0, ""}, + {"R_ARM_ABS32", Const, 0, ""}, + {"R_ARM_ABS32_NOI", Const, 10, ""}, + {"R_ARM_ABS8", Const, 0, ""}, + {"R_ARM_ALU_PCREL_15_8", Const, 10, ""}, + {"R_ARM_ALU_PCREL_23_15", Const, 10, ""}, + {"R_ARM_ALU_PCREL_7_0", Const, 10, ""}, + {"R_ARM_ALU_PC_G0", Const, 10, ""}, + {"R_ARM_ALU_PC_G0_NC", Const, 10, ""}, + {"R_ARM_ALU_PC_G1", Const, 10, ""}, + {"R_ARM_ALU_PC_G1_NC", Const, 10, ""}, + {"R_ARM_ALU_PC_G2", Const, 10, ""}, + {"R_ARM_ALU_SBREL_19_12_NC", Const, 10, ""}, + {"R_ARM_ALU_SBREL_27_20_CK", Const, 10, ""}, + {"R_ARM_ALU_SB_G0", Const, 10, ""}, + {"R_ARM_ALU_SB_G0_NC", Const, 10, ""}, + {"R_ARM_ALU_SB_G1", Const, 10, ""}, + {"R_ARM_ALU_SB_G1_NC", Const, 10, ""}, + {"R_ARM_ALU_SB_G2", Const, 10, ""}, + {"R_ARM_AMP_VCALL9", Const, 0, ""}, + {"R_ARM_BASE_ABS", Const, 10, ""}, + {"R_ARM_CALL", Const, 10, ""}, + {"R_ARM_COPY", Const, 0, ""}, + {"R_ARM_GLOB_DAT", Const, 0, ""}, + {"R_ARM_GNU_VTENTRY", Const, 0, ""}, + {"R_ARM_GNU_VTINHERIT", Const, 0, ""}, + {"R_ARM_GOT32", Const, 0, ""}, + {"R_ARM_GOTOFF", Const, 0, ""}, + {"R_ARM_GOTOFF12", Const, 10, ""}, + {"R_ARM_GOTPC", Const, 0, ""}, + {"R_ARM_GOTRELAX", Const, 10, ""}, + {"R_ARM_GOT_ABS", Const, 10, ""}, + {"R_ARM_GOT_BREL12", Const, 10, ""}, + {"R_ARM_GOT_PREL", Const, 10, ""}, + {"R_ARM_IRELATIVE", Const, 10, ""}, + {"R_ARM_JUMP24", Const, 10, ""}, + {"R_ARM_JUMP_SLOT", Const, 0, ""}, + {"R_ARM_LDC_PC_G0", Const, 10, ""}, + {"R_ARM_LDC_PC_G1", Const, 10, ""}, + {"R_ARM_LDC_PC_G2", Const, 10, ""}, + {"R_ARM_LDC_SB_G0", Const, 10, ""}, + {"R_ARM_LDC_SB_G1", Const, 10, ""}, + {"R_ARM_LDC_SB_G2", Const, 10, ""}, + {"R_ARM_LDRS_PC_G0", Const, 10, ""}, + {"R_ARM_LDRS_PC_G1", Const, 10, ""}, + {"R_ARM_LDRS_PC_G2", Const, 10, ""}, + {"R_ARM_LDRS_SB_G0", Const, 10, ""}, + {"R_ARM_LDRS_SB_G1", Const, 10, ""}, + {"R_ARM_LDRS_SB_G2", Const, 10, ""}, + {"R_ARM_LDR_PC_G1", Const, 10, ""}, + {"R_ARM_LDR_PC_G2", Const, 10, ""}, + {"R_ARM_LDR_SBREL_11_10_NC", Const, 10, ""}, + {"R_ARM_LDR_SB_G0", Const, 10, ""}, + {"R_ARM_LDR_SB_G1", Const, 10, ""}, + {"R_ARM_LDR_SB_G2", Const, 10, ""}, + {"R_ARM_ME_TOO", Const, 10, ""}, + {"R_ARM_MOVT_ABS", Const, 10, ""}, + {"R_ARM_MOVT_BREL", Const, 10, ""}, + {"R_ARM_MOVT_PREL", Const, 10, ""}, + {"R_ARM_MOVW_ABS_NC", Const, 10, ""}, + {"R_ARM_MOVW_BREL", Const, 10, ""}, + {"R_ARM_MOVW_BREL_NC", Const, 10, ""}, + {"R_ARM_MOVW_PREL_NC", Const, 10, ""}, + {"R_ARM_NONE", Const, 0, ""}, + {"R_ARM_PC13", Const, 0, ""}, + {"R_ARM_PC24", Const, 0, ""}, + {"R_ARM_PLT32", Const, 0, ""}, + {"R_ARM_PLT32_ABS", Const, 10, ""}, + {"R_ARM_PREL31", Const, 10, ""}, + {"R_ARM_PRIVATE_0", Const, 10, ""}, + {"R_ARM_PRIVATE_1", Const, 10, ""}, + {"R_ARM_PRIVATE_10", Const, 10, ""}, + {"R_ARM_PRIVATE_11", Const, 10, ""}, + {"R_ARM_PRIVATE_12", Const, 10, ""}, + {"R_ARM_PRIVATE_13", Const, 10, ""}, + {"R_ARM_PRIVATE_14", Const, 10, ""}, + {"R_ARM_PRIVATE_15", Const, 10, ""}, + {"R_ARM_PRIVATE_2", Const, 10, ""}, + {"R_ARM_PRIVATE_3", Const, 10, ""}, + {"R_ARM_PRIVATE_4", Const, 10, ""}, + {"R_ARM_PRIVATE_5", Const, 10, ""}, + {"R_ARM_PRIVATE_6", Const, 10, ""}, + {"R_ARM_PRIVATE_7", Const, 10, ""}, + {"R_ARM_PRIVATE_8", Const, 10, ""}, + {"R_ARM_PRIVATE_9", Const, 10, ""}, + {"R_ARM_RABS32", Const, 0, ""}, + {"R_ARM_RBASE", Const, 0, ""}, + {"R_ARM_REL32", Const, 0, ""}, + {"R_ARM_REL32_NOI", Const, 10, ""}, + {"R_ARM_RELATIVE", Const, 0, ""}, + {"R_ARM_RPC24", Const, 0, ""}, + {"R_ARM_RREL32", Const, 0, ""}, + {"R_ARM_RSBREL32", Const, 0, ""}, + {"R_ARM_RXPC25", Const, 10, ""}, + {"R_ARM_SBREL31", Const, 10, ""}, + {"R_ARM_SBREL32", Const, 0, ""}, + {"R_ARM_SWI24", Const, 0, ""}, + {"R_ARM_TARGET1", Const, 10, ""}, + {"R_ARM_TARGET2", Const, 10, ""}, + {"R_ARM_THM_ABS5", Const, 0, ""}, + {"R_ARM_THM_ALU_ABS_G0_NC", Const, 10, ""}, + {"R_ARM_THM_ALU_ABS_G1_NC", Const, 10, ""}, + {"R_ARM_THM_ALU_ABS_G2_NC", Const, 10, ""}, + {"R_ARM_THM_ALU_ABS_G3", Const, 10, ""}, + {"R_ARM_THM_ALU_PREL_11_0", Const, 10, ""}, + {"R_ARM_THM_GOT_BREL12", Const, 10, ""}, + {"R_ARM_THM_JUMP11", Const, 10, ""}, + {"R_ARM_THM_JUMP19", Const, 10, ""}, + {"R_ARM_THM_JUMP24", Const, 10, ""}, + {"R_ARM_THM_JUMP6", Const, 10, ""}, + {"R_ARM_THM_JUMP8", Const, 10, ""}, + {"R_ARM_THM_MOVT_ABS", Const, 10, ""}, + {"R_ARM_THM_MOVT_BREL", Const, 10, ""}, + {"R_ARM_THM_MOVT_PREL", Const, 10, ""}, + {"R_ARM_THM_MOVW_ABS_NC", Const, 10, ""}, + {"R_ARM_THM_MOVW_BREL", Const, 10, ""}, + {"R_ARM_THM_MOVW_BREL_NC", Const, 10, ""}, + {"R_ARM_THM_MOVW_PREL_NC", Const, 10, ""}, + {"R_ARM_THM_PC12", Const, 10, ""}, + {"R_ARM_THM_PC22", Const, 0, ""}, + {"R_ARM_THM_PC8", Const, 0, ""}, + {"R_ARM_THM_RPC22", Const, 0, ""}, + {"R_ARM_THM_SWI8", Const, 0, ""}, + {"R_ARM_THM_TLS_CALL", Const, 10, ""}, + {"R_ARM_THM_TLS_DESCSEQ16", Const, 10, ""}, + {"R_ARM_THM_TLS_DESCSEQ32", Const, 10, ""}, + {"R_ARM_THM_XPC22", Const, 0, ""}, + {"R_ARM_TLS_CALL", Const, 10, ""}, + {"R_ARM_TLS_DESCSEQ", Const, 10, ""}, + {"R_ARM_TLS_DTPMOD32", Const, 10, ""}, + {"R_ARM_TLS_DTPOFF32", Const, 10, ""}, + {"R_ARM_TLS_GD32", Const, 10, ""}, + {"R_ARM_TLS_GOTDESC", Const, 10, ""}, + {"R_ARM_TLS_IE12GP", Const, 10, ""}, + {"R_ARM_TLS_IE32", Const, 10, ""}, + {"R_ARM_TLS_LDM32", Const, 10, ""}, + {"R_ARM_TLS_LDO12", Const, 10, ""}, + {"R_ARM_TLS_LDO32", Const, 10, ""}, + {"R_ARM_TLS_LE12", Const, 10, ""}, + {"R_ARM_TLS_LE32", Const, 10, ""}, + {"R_ARM_TLS_TPOFF32", Const, 10, ""}, + {"R_ARM_V4BX", Const, 10, ""}, + {"R_ARM_XPC25", Const, 0, ""}, + {"R_INFO", Func, 0, "func(sym uint32, typ uint32) uint64"}, + {"R_INFO32", Func, 0, "func(sym uint32, typ uint32) uint32"}, + {"R_LARCH", Type, 19, ""}, + {"R_LARCH_32", Const, 19, ""}, + {"R_LARCH_32_PCREL", Const, 20, ""}, + {"R_LARCH_64", Const, 19, ""}, + {"R_LARCH_64_PCREL", Const, 22, ""}, + {"R_LARCH_ABS64_HI12", Const, 20, ""}, + {"R_LARCH_ABS64_LO20", Const, 20, ""}, + {"R_LARCH_ABS_HI20", Const, 20, ""}, + {"R_LARCH_ABS_LO12", Const, 20, ""}, + {"R_LARCH_ADD16", Const, 19, ""}, + {"R_LARCH_ADD24", Const, 19, ""}, + {"R_LARCH_ADD32", Const, 19, ""}, + {"R_LARCH_ADD6", Const, 22, ""}, + {"R_LARCH_ADD64", Const, 19, ""}, + {"R_LARCH_ADD8", Const, 19, ""}, + {"R_LARCH_ADD_ULEB128", Const, 22, ""}, + {"R_LARCH_ALIGN", Const, 22, ""}, + {"R_LARCH_B16", Const, 20, ""}, + {"R_LARCH_B21", Const, 20, ""}, + {"R_LARCH_B26", Const, 20, ""}, + {"R_LARCH_CFA", Const, 22, ""}, + {"R_LARCH_COPY", Const, 19, ""}, + {"R_LARCH_DELETE", Const, 22, ""}, + {"R_LARCH_GNU_VTENTRY", Const, 20, ""}, + {"R_LARCH_GNU_VTINHERIT", Const, 20, ""}, + {"R_LARCH_GOT64_HI12", Const, 20, ""}, + {"R_LARCH_GOT64_LO20", Const, 20, ""}, + {"R_LARCH_GOT64_PC_HI12", Const, 20, ""}, + {"R_LARCH_GOT64_PC_LO20", Const, 20, ""}, + {"R_LARCH_GOT_HI20", Const, 20, ""}, + {"R_LARCH_GOT_LO12", Const, 20, ""}, + {"R_LARCH_GOT_PC_HI20", Const, 20, ""}, + {"R_LARCH_GOT_PC_LO12", Const, 20, ""}, + {"R_LARCH_IRELATIVE", Const, 19, ""}, + {"R_LARCH_JUMP_SLOT", Const, 19, ""}, + {"R_LARCH_MARK_LA", Const, 19, ""}, + {"R_LARCH_MARK_PCREL", Const, 19, ""}, + {"R_LARCH_NONE", Const, 19, ""}, + {"R_LARCH_PCALA64_HI12", Const, 20, ""}, + {"R_LARCH_PCALA64_LO20", Const, 20, ""}, + {"R_LARCH_PCALA_HI20", Const, 20, ""}, + {"R_LARCH_PCALA_LO12", Const, 20, ""}, + {"R_LARCH_PCREL20_S2", Const, 22, ""}, + {"R_LARCH_RELATIVE", Const, 19, ""}, + {"R_LARCH_RELAX", Const, 20, ""}, + {"R_LARCH_SOP_ADD", Const, 19, ""}, + {"R_LARCH_SOP_AND", Const, 19, ""}, + {"R_LARCH_SOP_ASSERT", Const, 19, ""}, + {"R_LARCH_SOP_IF_ELSE", Const, 19, ""}, + {"R_LARCH_SOP_NOT", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_0_10_10_16_S2", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_0_5_10_16_S2", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_10_12", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_10_16", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_10_16_S2", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_10_5", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_S_5_20", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_U", Const, 19, ""}, + {"R_LARCH_SOP_POP_32_U_10_12", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_ABSOLUTE", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_DUP", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_GPREL", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_PCREL", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_PLT_PCREL", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_TLS_GD", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_TLS_GOT", Const, 19, ""}, + {"R_LARCH_SOP_PUSH_TLS_TPREL", Const, 19, ""}, + {"R_LARCH_SOP_SL", Const, 19, ""}, + {"R_LARCH_SOP_SR", Const, 19, ""}, + {"R_LARCH_SOP_SUB", Const, 19, ""}, + {"R_LARCH_SUB16", Const, 19, ""}, + {"R_LARCH_SUB24", Const, 19, ""}, + {"R_LARCH_SUB32", Const, 19, ""}, + {"R_LARCH_SUB6", Const, 22, ""}, + {"R_LARCH_SUB64", Const, 19, ""}, + {"R_LARCH_SUB8", Const, 19, ""}, + {"R_LARCH_SUB_ULEB128", Const, 22, ""}, + {"R_LARCH_TLS_DTPMOD32", Const, 19, ""}, + {"R_LARCH_TLS_DTPMOD64", Const, 19, ""}, + {"R_LARCH_TLS_DTPREL32", Const, 19, ""}, + {"R_LARCH_TLS_DTPREL64", Const, 19, ""}, + {"R_LARCH_TLS_GD_HI20", Const, 20, ""}, + {"R_LARCH_TLS_GD_PC_HI20", Const, 20, ""}, + {"R_LARCH_TLS_IE64_HI12", Const, 20, ""}, + {"R_LARCH_TLS_IE64_LO20", Const, 20, ""}, + {"R_LARCH_TLS_IE64_PC_HI12", Const, 20, ""}, + {"R_LARCH_TLS_IE64_PC_LO20", Const, 20, ""}, + {"R_LARCH_TLS_IE_HI20", Const, 20, ""}, + {"R_LARCH_TLS_IE_LO12", Const, 20, ""}, + {"R_LARCH_TLS_IE_PC_HI20", Const, 20, ""}, + {"R_LARCH_TLS_IE_PC_LO12", Const, 20, ""}, + {"R_LARCH_TLS_LD_HI20", Const, 20, ""}, + {"R_LARCH_TLS_LD_PC_HI20", Const, 20, ""}, + {"R_LARCH_TLS_LE64_HI12", Const, 20, ""}, + {"R_LARCH_TLS_LE64_LO20", Const, 20, ""}, + {"R_LARCH_TLS_LE_HI20", Const, 20, ""}, + {"R_LARCH_TLS_LE_LO12", Const, 20, ""}, + {"R_LARCH_TLS_TPREL32", Const, 19, ""}, + {"R_LARCH_TLS_TPREL64", Const, 19, ""}, + {"R_MIPS", Type, 6, ""}, + {"R_MIPS_16", Const, 6, ""}, + {"R_MIPS_26", Const, 6, ""}, + {"R_MIPS_32", Const, 6, ""}, + {"R_MIPS_64", Const, 6, ""}, + {"R_MIPS_ADD_IMMEDIATE", Const, 6, ""}, + {"R_MIPS_CALL16", Const, 6, ""}, + {"R_MIPS_CALL_HI16", Const, 6, ""}, + {"R_MIPS_CALL_LO16", Const, 6, ""}, + {"R_MIPS_DELETE", Const, 6, ""}, + {"R_MIPS_GOT16", Const, 6, ""}, + {"R_MIPS_GOT_DISP", Const, 6, ""}, + {"R_MIPS_GOT_HI16", Const, 6, ""}, + {"R_MIPS_GOT_LO16", Const, 6, ""}, + {"R_MIPS_GOT_OFST", Const, 6, ""}, + {"R_MIPS_GOT_PAGE", Const, 6, ""}, + {"R_MIPS_GPREL16", Const, 6, ""}, + {"R_MIPS_GPREL32", Const, 6, ""}, + {"R_MIPS_HI16", Const, 6, ""}, + {"R_MIPS_HIGHER", Const, 6, ""}, + {"R_MIPS_HIGHEST", Const, 6, ""}, + {"R_MIPS_INSERT_A", Const, 6, ""}, + {"R_MIPS_INSERT_B", Const, 6, ""}, + {"R_MIPS_JALR", Const, 6, ""}, + {"R_MIPS_LITERAL", Const, 6, ""}, + {"R_MIPS_LO16", Const, 6, ""}, + {"R_MIPS_NONE", Const, 6, ""}, + {"R_MIPS_PC16", Const, 6, ""}, + {"R_MIPS_PC32", Const, 22, ""}, + {"R_MIPS_PJUMP", Const, 6, ""}, + {"R_MIPS_REL16", Const, 6, ""}, + {"R_MIPS_REL32", Const, 6, ""}, + {"R_MIPS_RELGOT", Const, 6, ""}, + {"R_MIPS_SCN_DISP", Const, 6, ""}, + {"R_MIPS_SHIFT5", Const, 6, ""}, + {"R_MIPS_SHIFT6", Const, 6, ""}, + {"R_MIPS_SUB", Const, 6, ""}, + {"R_MIPS_TLS_DTPMOD32", Const, 6, ""}, + {"R_MIPS_TLS_DTPMOD64", Const, 6, ""}, + {"R_MIPS_TLS_DTPREL32", Const, 6, ""}, + {"R_MIPS_TLS_DTPREL64", Const, 6, ""}, + {"R_MIPS_TLS_DTPREL_HI16", Const, 6, ""}, + {"R_MIPS_TLS_DTPREL_LO16", Const, 6, ""}, + {"R_MIPS_TLS_GD", Const, 6, ""}, + {"R_MIPS_TLS_GOTTPREL", Const, 6, ""}, + {"R_MIPS_TLS_LDM", Const, 6, ""}, + {"R_MIPS_TLS_TPREL32", Const, 6, ""}, + {"R_MIPS_TLS_TPREL64", Const, 6, ""}, + {"R_MIPS_TLS_TPREL_HI16", Const, 6, ""}, + {"R_MIPS_TLS_TPREL_LO16", Const, 6, ""}, + {"R_PPC", Type, 0, ""}, + {"R_PPC64", Type, 5, ""}, + {"R_PPC64_ADDR14", Const, 5, ""}, + {"R_PPC64_ADDR14_BRNTAKEN", Const, 5, ""}, + {"R_PPC64_ADDR14_BRTAKEN", Const, 5, ""}, + {"R_PPC64_ADDR16", Const, 5, ""}, + {"R_PPC64_ADDR16_DS", Const, 5, ""}, + {"R_PPC64_ADDR16_HA", Const, 5, ""}, + {"R_PPC64_ADDR16_HI", Const, 5, ""}, + {"R_PPC64_ADDR16_HIGH", Const, 10, ""}, + {"R_PPC64_ADDR16_HIGHA", Const, 10, ""}, + {"R_PPC64_ADDR16_HIGHER", Const, 5, ""}, + {"R_PPC64_ADDR16_HIGHER34", Const, 20, ""}, + {"R_PPC64_ADDR16_HIGHERA", Const, 5, ""}, + {"R_PPC64_ADDR16_HIGHERA34", Const, 20, ""}, + {"R_PPC64_ADDR16_HIGHEST", Const, 5, ""}, + {"R_PPC64_ADDR16_HIGHEST34", Const, 20, ""}, + {"R_PPC64_ADDR16_HIGHESTA", Const, 5, ""}, + {"R_PPC64_ADDR16_HIGHESTA34", Const, 20, ""}, + {"R_PPC64_ADDR16_LO", Const, 5, ""}, + {"R_PPC64_ADDR16_LO_DS", Const, 5, ""}, + {"R_PPC64_ADDR24", Const, 5, ""}, + {"R_PPC64_ADDR32", Const, 5, ""}, + {"R_PPC64_ADDR64", Const, 5, ""}, + {"R_PPC64_ADDR64_LOCAL", Const, 10, ""}, + {"R_PPC64_COPY", Const, 20, ""}, + {"R_PPC64_D28", Const, 20, ""}, + {"R_PPC64_D34", Const, 20, ""}, + {"R_PPC64_D34_HA30", Const, 20, ""}, + {"R_PPC64_D34_HI30", Const, 20, ""}, + {"R_PPC64_D34_LO", Const, 20, ""}, + {"R_PPC64_DTPMOD64", Const, 5, ""}, + {"R_PPC64_DTPREL16", Const, 5, ""}, + {"R_PPC64_DTPREL16_DS", Const, 5, ""}, + {"R_PPC64_DTPREL16_HA", Const, 5, ""}, + {"R_PPC64_DTPREL16_HI", Const, 5, ""}, + {"R_PPC64_DTPREL16_HIGH", Const, 10, ""}, + {"R_PPC64_DTPREL16_HIGHA", Const, 10, ""}, + {"R_PPC64_DTPREL16_HIGHER", Const, 5, ""}, + {"R_PPC64_DTPREL16_HIGHERA", Const, 5, ""}, + {"R_PPC64_DTPREL16_HIGHEST", Const, 5, ""}, + {"R_PPC64_DTPREL16_HIGHESTA", Const, 5, ""}, + {"R_PPC64_DTPREL16_LO", Const, 5, ""}, + {"R_PPC64_DTPREL16_LO_DS", Const, 5, ""}, + {"R_PPC64_DTPREL34", Const, 20, ""}, + {"R_PPC64_DTPREL64", Const, 5, ""}, + {"R_PPC64_ENTRY", Const, 10, ""}, + {"R_PPC64_GLOB_DAT", Const, 20, ""}, + {"R_PPC64_GNU_VTENTRY", Const, 20, ""}, + {"R_PPC64_GNU_VTINHERIT", Const, 20, ""}, + {"R_PPC64_GOT16", Const, 5, ""}, + {"R_PPC64_GOT16_DS", Const, 5, ""}, + {"R_PPC64_GOT16_HA", Const, 5, ""}, + {"R_PPC64_GOT16_HI", Const, 5, ""}, + {"R_PPC64_GOT16_LO", Const, 5, ""}, + {"R_PPC64_GOT16_LO_DS", Const, 5, ""}, + {"R_PPC64_GOT_DTPREL16_DS", Const, 5, ""}, + {"R_PPC64_GOT_DTPREL16_HA", Const, 5, ""}, + {"R_PPC64_GOT_DTPREL16_HI", Const, 5, ""}, + {"R_PPC64_GOT_DTPREL16_LO_DS", Const, 5, ""}, + {"R_PPC64_GOT_DTPREL_PCREL34", Const, 20, ""}, + {"R_PPC64_GOT_PCREL34", Const, 20, ""}, + {"R_PPC64_GOT_TLSGD16", Const, 5, ""}, + {"R_PPC64_GOT_TLSGD16_HA", Const, 5, ""}, + {"R_PPC64_GOT_TLSGD16_HI", Const, 5, ""}, + {"R_PPC64_GOT_TLSGD16_LO", Const, 5, ""}, + {"R_PPC64_GOT_TLSGD_PCREL34", Const, 20, ""}, + {"R_PPC64_GOT_TLSLD16", Const, 5, ""}, + {"R_PPC64_GOT_TLSLD16_HA", Const, 5, ""}, + {"R_PPC64_GOT_TLSLD16_HI", Const, 5, ""}, + {"R_PPC64_GOT_TLSLD16_LO", Const, 5, ""}, + {"R_PPC64_GOT_TLSLD_PCREL34", Const, 20, ""}, + {"R_PPC64_GOT_TPREL16_DS", Const, 5, ""}, + {"R_PPC64_GOT_TPREL16_HA", Const, 5, ""}, + {"R_PPC64_GOT_TPREL16_HI", Const, 5, ""}, + {"R_PPC64_GOT_TPREL16_LO_DS", Const, 5, ""}, + {"R_PPC64_GOT_TPREL_PCREL34", Const, 20, ""}, + {"R_PPC64_IRELATIVE", Const, 10, ""}, + {"R_PPC64_JMP_IREL", Const, 10, ""}, + {"R_PPC64_JMP_SLOT", Const, 5, ""}, + {"R_PPC64_NONE", Const, 5, ""}, + {"R_PPC64_PCREL28", Const, 20, ""}, + {"R_PPC64_PCREL34", Const, 20, ""}, + {"R_PPC64_PCREL_OPT", Const, 20, ""}, + {"R_PPC64_PLT16_HA", Const, 20, ""}, + {"R_PPC64_PLT16_HI", Const, 20, ""}, + {"R_PPC64_PLT16_LO", Const, 20, ""}, + {"R_PPC64_PLT16_LO_DS", Const, 10, ""}, + {"R_PPC64_PLT32", Const, 20, ""}, + {"R_PPC64_PLT64", Const, 20, ""}, + {"R_PPC64_PLTCALL", Const, 20, ""}, + {"R_PPC64_PLTCALL_NOTOC", Const, 20, ""}, + {"R_PPC64_PLTGOT16", Const, 10, ""}, + {"R_PPC64_PLTGOT16_DS", Const, 10, ""}, + {"R_PPC64_PLTGOT16_HA", Const, 10, ""}, + {"R_PPC64_PLTGOT16_HI", Const, 10, ""}, + {"R_PPC64_PLTGOT16_LO", Const, 10, ""}, + {"R_PPC64_PLTGOT_LO_DS", Const, 10, ""}, + {"R_PPC64_PLTREL32", Const, 20, ""}, + {"R_PPC64_PLTREL64", Const, 20, ""}, + {"R_PPC64_PLTSEQ", Const, 20, ""}, + {"R_PPC64_PLTSEQ_NOTOC", Const, 20, ""}, + {"R_PPC64_PLT_PCREL34", Const, 20, ""}, + {"R_PPC64_PLT_PCREL34_NOTOC", Const, 20, ""}, + {"R_PPC64_REL14", Const, 5, ""}, + {"R_PPC64_REL14_BRNTAKEN", Const, 5, ""}, + {"R_PPC64_REL14_BRTAKEN", Const, 5, ""}, + {"R_PPC64_REL16", Const, 5, ""}, + {"R_PPC64_REL16DX_HA", Const, 10, ""}, + {"R_PPC64_REL16_HA", Const, 5, ""}, + {"R_PPC64_REL16_HI", Const, 5, ""}, + {"R_PPC64_REL16_HIGH", Const, 20, ""}, + {"R_PPC64_REL16_HIGHA", Const, 20, ""}, + {"R_PPC64_REL16_HIGHER", Const, 20, ""}, + {"R_PPC64_REL16_HIGHER34", Const, 20, ""}, + {"R_PPC64_REL16_HIGHERA", Const, 20, ""}, + {"R_PPC64_REL16_HIGHERA34", Const, 20, ""}, + {"R_PPC64_REL16_HIGHEST", Const, 20, ""}, + {"R_PPC64_REL16_HIGHEST34", Const, 20, ""}, + {"R_PPC64_REL16_HIGHESTA", Const, 20, ""}, + {"R_PPC64_REL16_HIGHESTA34", Const, 20, ""}, + {"R_PPC64_REL16_LO", Const, 5, ""}, + {"R_PPC64_REL24", Const, 5, ""}, + {"R_PPC64_REL24_NOTOC", Const, 10, ""}, + {"R_PPC64_REL24_P9NOTOC", Const, 21, ""}, + {"R_PPC64_REL30", Const, 20, ""}, + {"R_PPC64_REL32", Const, 5, ""}, + {"R_PPC64_REL64", Const, 5, ""}, + {"R_PPC64_RELATIVE", Const, 18, ""}, + {"R_PPC64_SECTOFF", Const, 20, ""}, + {"R_PPC64_SECTOFF_DS", Const, 10, ""}, + {"R_PPC64_SECTOFF_HA", Const, 20, ""}, + {"R_PPC64_SECTOFF_HI", Const, 20, ""}, + {"R_PPC64_SECTOFF_LO", Const, 20, ""}, + {"R_PPC64_SECTOFF_LO_DS", Const, 10, ""}, + {"R_PPC64_TLS", Const, 5, ""}, + {"R_PPC64_TLSGD", Const, 5, ""}, + {"R_PPC64_TLSLD", Const, 5, ""}, + {"R_PPC64_TOC", Const, 5, ""}, + {"R_PPC64_TOC16", Const, 5, ""}, + {"R_PPC64_TOC16_DS", Const, 5, ""}, + {"R_PPC64_TOC16_HA", Const, 5, ""}, + {"R_PPC64_TOC16_HI", Const, 5, ""}, + {"R_PPC64_TOC16_LO", Const, 5, ""}, + {"R_PPC64_TOC16_LO_DS", Const, 5, ""}, + {"R_PPC64_TOCSAVE", Const, 10, ""}, + {"R_PPC64_TPREL16", Const, 5, ""}, + {"R_PPC64_TPREL16_DS", Const, 5, ""}, + {"R_PPC64_TPREL16_HA", Const, 5, ""}, + {"R_PPC64_TPREL16_HI", Const, 5, ""}, + {"R_PPC64_TPREL16_HIGH", Const, 10, ""}, + {"R_PPC64_TPREL16_HIGHA", Const, 10, ""}, + {"R_PPC64_TPREL16_HIGHER", Const, 5, ""}, + {"R_PPC64_TPREL16_HIGHERA", Const, 5, ""}, + {"R_PPC64_TPREL16_HIGHEST", Const, 5, ""}, + {"R_PPC64_TPREL16_HIGHESTA", Const, 5, ""}, + {"R_PPC64_TPREL16_LO", Const, 5, ""}, + {"R_PPC64_TPREL16_LO_DS", Const, 5, ""}, + {"R_PPC64_TPREL34", Const, 20, ""}, + {"R_PPC64_TPREL64", Const, 5, ""}, + {"R_PPC64_UADDR16", Const, 20, ""}, + {"R_PPC64_UADDR32", Const, 20, ""}, + {"R_PPC64_UADDR64", Const, 20, ""}, + {"R_PPC_ADDR14", Const, 0, ""}, + {"R_PPC_ADDR14_BRNTAKEN", Const, 0, ""}, + {"R_PPC_ADDR14_BRTAKEN", Const, 0, ""}, + {"R_PPC_ADDR16", Const, 0, ""}, + {"R_PPC_ADDR16_HA", Const, 0, ""}, + {"R_PPC_ADDR16_HI", Const, 0, ""}, + {"R_PPC_ADDR16_LO", Const, 0, ""}, + {"R_PPC_ADDR24", Const, 0, ""}, + {"R_PPC_ADDR32", Const, 0, ""}, + {"R_PPC_COPY", Const, 0, ""}, + {"R_PPC_DTPMOD32", Const, 0, ""}, + {"R_PPC_DTPREL16", Const, 0, ""}, + {"R_PPC_DTPREL16_HA", Const, 0, ""}, + {"R_PPC_DTPREL16_HI", Const, 0, ""}, + {"R_PPC_DTPREL16_LO", Const, 0, ""}, + {"R_PPC_DTPREL32", Const, 0, ""}, + {"R_PPC_EMB_BIT_FLD", Const, 0, ""}, + {"R_PPC_EMB_MRKREF", Const, 0, ""}, + {"R_PPC_EMB_NADDR16", Const, 0, ""}, + {"R_PPC_EMB_NADDR16_HA", Const, 0, ""}, + {"R_PPC_EMB_NADDR16_HI", Const, 0, ""}, + {"R_PPC_EMB_NADDR16_LO", Const, 0, ""}, + {"R_PPC_EMB_NADDR32", Const, 0, ""}, + {"R_PPC_EMB_RELSDA", Const, 0, ""}, + {"R_PPC_EMB_RELSEC16", Const, 0, ""}, + {"R_PPC_EMB_RELST_HA", Const, 0, ""}, + {"R_PPC_EMB_RELST_HI", Const, 0, ""}, + {"R_PPC_EMB_RELST_LO", Const, 0, ""}, + {"R_PPC_EMB_SDA21", Const, 0, ""}, + {"R_PPC_EMB_SDA2I16", Const, 0, ""}, + {"R_PPC_EMB_SDA2REL", Const, 0, ""}, + {"R_PPC_EMB_SDAI16", Const, 0, ""}, + {"R_PPC_GLOB_DAT", Const, 0, ""}, + {"R_PPC_GOT16", Const, 0, ""}, + {"R_PPC_GOT16_HA", Const, 0, ""}, + {"R_PPC_GOT16_HI", Const, 0, ""}, + {"R_PPC_GOT16_LO", Const, 0, ""}, + {"R_PPC_GOT_TLSGD16", Const, 0, ""}, + {"R_PPC_GOT_TLSGD16_HA", Const, 0, ""}, + {"R_PPC_GOT_TLSGD16_HI", Const, 0, ""}, + {"R_PPC_GOT_TLSGD16_LO", Const, 0, ""}, + {"R_PPC_GOT_TLSLD16", Const, 0, ""}, + {"R_PPC_GOT_TLSLD16_HA", Const, 0, ""}, + {"R_PPC_GOT_TLSLD16_HI", Const, 0, ""}, + {"R_PPC_GOT_TLSLD16_LO", Const, 0, ""}, + {"R_PPC_GOT_TPREL16", Const, 0, ""}, + {"R_PPC_GOT_TPREL16_HA", Const, 0, ""}, + {"R_PPC_GOT_TPREL16_HI", Const, 0, ""}, + {"R_PPC_GOT_TPREL16_LO", Const, 0, ""}, + {"R_PPC_JMP_SLOT", Const, 0, ""}, + {"R_PPC_LOCAL24PC", Const, 0, ""}, + {"R_PPC_NONE", Const, 0, ""}, + {"R_PPC_PLT16_HA", Const, 0, ""}, + {"R_PPC_PLT16_HI", Const, 0, ""}, + {"R_PPC_PLT16_LO", Const, 0, ""}, + {"R_PPC_PLT32", Const, 0, ""}, + {"R_PPC_PLTREL24", Const, 0, ""}, + {"R_PPC_PLTREL32", Const, 0, ""}, + {"R_PPC_REL14", Const, 0, ""}, + {"R_PPC_REL14_BRNTAKEN", Const, 0, ""}, + {"R_PPC_REL14_BRTAKEN", Const, 0, ""}, + {"R_PPC_REL24", Const, 0, ""}, + {"R_PPC_REL32", Const, 0, ""}, + {"R_PPC_RELATIVE", Const, 0, ""}, + {"R_PPC_SDAREL16", Const, 0, ""}, + {"R_PPC_SECTOFF", Const, 0, ""}, + {"R_PPC_SECTOFF_HA", Const, 0, ""}, + {"R_PPC_SECTOFF_HI", Const, 0, ""}, + {"R_PPC_SECTOFF_LO", Const, 0, ""}, + {"R_PPC_TLS", Const, 0, ""}, + {"R_PPC_TPREL16", Const, 0, ""}, + {"R_PPC_TPREL16_HA", Const, 0, ""}, + {"R_PPC_TPREL16_HI", Const, 0, ""}, + {"R_PPC_TPREL16_LO", Const, 0, ""}, + {"R_PPC_TPREL32", Const, 0, ""}, + {"R_PPC_UADDR16", Const, 0, ""}, + {"R_PPC_UADDR32", Const, 0, ""}, + {"R_RISCV", Type, 11, ""}, + {"R_RISCV_32", Const, 11, ""}, + {"R_RISCV_32_PCREL", Const, 12, ""}, + {"R_RISCV_64", Const, 11, ""}, + {"R_RISCV_ADD16", Const, 11, ""}, + {"R_RISCV_ADD32", Const, 11, ""}, + {"R_RISCV_ADD64", Const, 11, ""}, + {"R_RISCV_ADD8", Const, 11, ""}, + {"R_RISCV_ALIGN", Const, 11, ""}, + {"R_RISCV_BRANCH", Const, 11, ""}, + {"R_RISCV_CALL", Const, 11, ""}, + {"R_RISCV_CALL_PLT", Const, 11, ""}, + {"R_RISCV_COPY", Const, 11, ""}, + {"R_RISCV_GNU_VTENTRY", Const, 11, ""}, + {"R_RISCV_GNU_VTINHERIT", Const, 11, ""}, + {"R_RISCV_GOT_HI20", Const, 11, ""}, + {"R_RISCV_GPREL_I", Const, 11, ""}, + {"R_RISCV_GPREL_S", Const, 11, ""}, + {"R_RISCV_HI20", Const, 11, ""}, + {"R_RISCV_JAL", Const, 11, ""}, + {"R_RISCV_JUMP_SLOT", Const, 11, ""}, + {"R_RISCV_LO12_I", Const, 11, ""}, + {"R_RISCV_LO12_S", Const, 11, ""}, + {"R_RISCV_NONE", Const, 11, ""}, + {"R_RISCV_PCREL_HI20", Const, 11, ""}, + {"R_RISCV_PCREL_LO12_I", Const, 11, ""}, + {"R_RISCV_PCREL_LO12_S", Const, 11, ""}, + {"R_RISCV_RELATIVE", Const, 11, ""}, + {"R_RISCV_RELAX", Const, 11, ""}, + {"R_RISCV_RVC_BRANCH", Const, 11, ""}, + {"R_RISCV_RVC_JUMP", Const, 11, ""}, + {"R_RISCV_RVC_LUI", Const, 11, ""}, + {"R_RISCV_SET16", Const, 11, ""}, + {"R_RISCV_SET32", Const, 11, ""}, + {"R_RISCV_SET6", Const, 11, ""}, + {"R_RISCV_SET8", Const, 11, ""}, + {"R_RISCV_SUB16", Const, 11, ""}, + {"R_RISCV_SUB32", Const, 11, ""}, + {"R_RISCV_SUB6", Const, 11, ""}, + {"R_RISCV_SUB64", Const, 11, ""}, + {"R_RISCV_SUB8", Const, 11, ""}, + {"R_RISCV_TLS_DTPMOD32", Const, 11, ""}, + {"R_RISCV_TLS_DTPMOD64", Const, 11, ""}, + {"R_RISCV_TLS_DTPREL32", Const, 11, ""}, + {"R_RISCV_TLS_DTPREL64", Const, 11, ""}, + {"R_RISCV_TLS_GD_HI20", Const, 11, ""}, + {"R_RISCV_TLS_GOT_HI20", Const, 11, ""}, + {"R_RISCV_TLS_TPREL32", Const, 11, ""}, + {"R_RISCV_TLS_TPREL64", Const, 11, ""}, + {"R_RISCV_TPREL_ADD", Const, 11, ""}, + {"R_RISCV_TPREL_HI20", Const, 11, ""}, + {"R_RISCV_TPREL_I", Const, 11, ""}, + {"R_RISCV_TPREL_LO12_I", Const, 11, ""}, + {"R_RISCV_TPREL_LO12_S", Const, 11, ""}, + {"R_RISCV_TPREL_S", Const, 11, ""}, + {"R_SPARC", Type, 0, ""}, + {"R_SPARC_10", Const, 0, ""}, + {"R_SPARC_11", Const, 0, ""}, + {"R_SPARC_13", Const, 0, ""}, + {"R_SPARC_16", Const, 0, ""}, + {"R_SPARC_22", Const, 0, ""}, + {"R_SPARC_32", Const, 0, ""}, + {"R_SPARC_5", Const, 0, ""}, + {"R_SPARC_6", Const, 0, ""}, + {"R_SPARC_64", Const, 0, ""}, + {"R_SPARC_7", Const, 0, ""}, + {"R_SPARC_8", Const, 0, ""}, + {"R_SPARC_COPY", Const, 0, ""}, + {"R_SPARC_DISP16", Const, 0, ""}, + {"R_SPARC_DISP32", Const, 0, ""}, + {"R_SPARC_DISP64", Const, 0, ""}, + {"R_SPARC_DISP8", Const, 0, ""}, + {"R_SPARC_GLOB_DAT", Const, 0, ""}, + {"R_SPARC_GLOB_JMP", Const, 0, ""}, + {"R_SPARC_GOT10", Const, 0, ""}, + {"R_SPARC_GOT13", Const, 0, ""}, + {"R_SPARC_GOT22", Const, 0, ""}, + {"R_SPARC_H44", Const, 0, ""}, + {"R_SPARC_HH22", Const, 0, ""}, + {"R_SPARC_HI22", Const, 0, ""}, + {"R_SPARC_HIPLT22", Const, 0, ""}, + {"R_SPARC_HIX22", Const, 0, ""}, + {"R_SPARC_HM10", Const, 0, ""}, + {"R_SPARC_JMP_SLOT", Const, 0, ""}, + {"R_SPARC_L44", Const, 0, ""}, + {"R_SPARC_LM22", Const, 0, ""}, + {"R_SPARC_LO10", Const, 0, ""}, + {"R_SPARC_LOPLT10", Const, 0, ""}, + {"R_SPARC_LOX10", Const, 0, ""}, + {"R_SPARC_M44", Const, 0, ""}, + {"R_SPARC_NONE", Const, 0, ""}, + {"R_SPARC_OLO10", Const, 0, ""}, + {"R_SPARC_PC10", Const, 0, ""}, + {"R_SPARC_PC22", Const, 0, ""}, + {"R_SPARC_PCPLT10", Const, 0, ""}, + {"R_SPARC_PCPLT22", Const, 0, ""}, + {"R_SPARC_PCPLT32", Const, 0, ""}, + {"R_SPARC_PC_HH22", Const, 0, ""}, + {"R_SPARC_PC_HM10", Const, 0, ""}, + {"R_SPARC_PC_LM22", Const, 0, ""}, + {"R_SPARC_PLT32", Const, 0, ""}, + {"R_SPARC_PLT64", Const, 0, ""}, + {"R_SPARC_REGISTER", Const, 0, ""}, + {"R_SPARC_RELATIVE", Const, 0, ""}, + {"R_SPARC_UA16", Const, 0, ""}, + {"R_SPARC_UA32", Const, 0, ""}, + {"R_SPARC_UA64", Const, 0, ""}, + {"R_SPARC_WDISP16", Const, 0, ""}, + {"R_SPARC_WDISP19", Const, 0, ""}, + {"R_SPARC_WDISP22", Const, 0, ""}, + {"R_SPARC_WDISP30", Const, 0, ""}, + {"R_SPARC_WPLT30", Const, 0, ""}, + {"R_SYM32", Func, 0, "func(info uint32) uint32"}, + {"R_SYM64", Func, 0, "func(info uint64) uint32"}, + {"R_TYPE32", Func, 0, "func(info uint32) uint32"}, + {"R_TYPE64", Func, 0, "func(info uint64) uint32"}, + {"R_X86_64", Type, 0, ""}, + {"R_X86_64_16", Const, 0, ""}, + {"R_X86_64_32", Const, 0, ""}, + {"R_X86_64_32S", Const, 0, ""}, + {"R_X86_64_64", Const, 0, ""}, + {"R_X86_64_8", Const, 0, ""}, + {"R_X86_64_COPY", Const, 0, ""}, + {"R_X86_64_DTPMOD64", Const, 0, ""}, + {"R_X86_64_DTPOFF32", Const, 0, ""}, + {"R_X86_64_DTPOFF64", Const, 0, ""}, + {"R_X86_64_GLOB_DAT", Const, 0, ""}, + {"R_X86_64_GOT32", Const, 0, ""}, + {"R_X86_64_GOT64", Const, 10, ""}, + {"R_X86_64_GOTOFF64", Const, 10, ""}, + {"R_X86_64_GOTPC32", Const, 10, ""}, + {"R_X86_64_GOTPC32_TLSDESC", Const, 10, ""}, + {"R_X86_64_GOTPC64", Const, 10, ""}, + {"R_X86_64_GOTPCREL", Const, 0, ""}, + {"R_X86_64_GOTPCREL64", Const, 10, ""}, + {"R_X86_64_GOTPCRELX", Const, 10, ""}, + {"R_X86_64_GOTPLT64", Const, 10, ""}, + {"R_X86_64_GOTTPOFF", Const, 0, ""}, + {"R_X86_64_IRELATIVE", Const, 10, ""}, + {"R_X86_64_JMP_SLOT", Const, 0, ""}, + {"R_X86_64_NONE", Const, 0, ""}, + {"R_X86_64_PC16", Const, 0, ""}, + {"R_X86_64_PC32", Const, 0, ""}, + {"R_X86_64_PC32_BND", Const, 10, ""}, + {"R_X86_64_PC64", Const, 10, ""}, + {"R_X86_64_PC8", Const, 0, ""}, + {"R_X86_64_PLT32", Const, 0, ""}, + {"R_X86_64_PLT32_BND", Const, 10, ""}, + {"R_X86_64_PLTOFF64", Const, 10, ""}, + {"R_X86_64_RELATIVE", Const, 0, ""}, + {"R_X86_64_RELATIVE64", Const, 10, ""}, + {"R_X86_64_REX_GOTPCRELX", Const, 10, ""}, + {"R_X86_64_SIZE32", Const, 10, ""}, + {"R_X86_64_SIZE64", Const, 10, ""}, + {"R_X86_64_TLSDESC", Const, 10, ""}, + {"R_X86_64_TLSDESC_CALL", Const, 10, ""}, + {"R_X86_64_TLSGD", Const, 0, ""}, + {"R_X86_64_TLSLD", Const, 0, ""}, + {"R_X86_64_TPOFF32", Const, 0, ""}, + {"R_X86_64_TPOFF64", Const, 0, ""}, + {"Rel32", Type, 0, ""}, + {"Rel32.Info", Field, 0, ""}, + {"Rel32.Off", Field, 0, ""}, + {"Rel64", Type, 0, ""}, + {"Rel64.Info", Field, 0, ""}, + {"Rel64.Off", Field, 0, ""}, + {"Rela32", Type, 0, ""}, + {"Rela32.Addend", Field, 0, ""}, + {"Rela32.Info", Field, 0, ""}, + {"Rela32.Off", Field, 0, ""}, + {"Rela64", Type, 0, ""}, + {"Rela64.Addend", Field, 0, ""}, + {"Rela64.Info", Field, 0, ""}, + {"Rela64.Off", Field, 0, ""}, + {"SHF_ALLOC", Const, 0, ""}, + {"SHF_COMPRESSED", Const, 6, ""}, + {"SHF_EXECINSTR", Const, 0, ""}, + {"SHF_GROUP", Const, 0, ""}, + {"SHF_INFO_LINK", Const, 0, ""}, + {"SHF_LINK_ORDER", Const, 0, ""}, + {"SHF_MASKOS", Const, 0, ""}, + {"SHF_MASKPROC", Const, 0, ""}, + {"SHF_MERGE", Const, 0, ""}, + {"SHF_OS_NONCONFORMING", Const, 0, ""}, + {"SHF_STRINGS", Const, 0, ""}, + {"SHF_TLS", Const, 0, ""}, + {"SHF_WRITE", Const, 0, ""}, + {"SHN_ABS", Const, 0, ""}, + {"SHN_COMMON", Const, 0, ""}, + {"SHN_HIOS", Const, 0, ""}, + {"SHN_HIPROC", Const, 0, ""}, + {"SHN_HIRESERVE", Const, 0, ""}, + {"SHN_LOOS", Const, 0, ""}, + {"SHN_LOPROC", Const, 0, ""}, + {"SHN_LORESERVE", Const, 0, ""}, + {"SHN_UNDEF", Const, 0, ""}, + {"SHN_XINDEX", Const, 0, ""}, + {"SHT_DYNAMIC", Const, 0, ""}, + {"SHT_DYNSYM", Const, 0, ""}, + {"SHT_FINI_ARRAY", Const, 0, ""}, + {"SHT_GNU_ATTRIBUTES", Const, 0, ""}, + {"SHT_GNU_HASH", Const, 0, ""}, + {"SHT_GNU_LIBLIST", Const, 0, ""}, + {"SHT_GNU_VERDEF", Const, 0, ""}, + {"SHT_GNU_VERNEED", Const, 0, ""}, + {"SHT_GNU_VERSYM", Const, 0, ""}, + {"SHT_GROUP", Const, 0, ""}, + {"SHT_HASH", Const, 0, ""}, + {"SHT_HIOS", Const, 0, ""}, + {"SHT_HIPROC", Const, 0, ""}, + {"SHT_HIUSER", Const, 0, ""}, + {"SHT_INIT_ARRAY", Const, 0, ""}, + {"SHT_LOOS", Const, 0, ""}, + {"SHT_LOPROC", Const, 0, ""}, + {"SHT_LOUSER", Const, 0, ""}, + {"SHT_MIPS_ABIFLAGS", Const, 17, ""}, + {"SHT_NOBITS", Const, 0, ""}, + {"SHT_NOTE", Const, 0, ""}, + {"SHT_NULL", Const, 0, ""}, + {"SHT_PREINIT_ARRAY", Const, 0, ""}, + {"SHT_PROGBITS", Const, 0, ""}, + {"SHT_REL", Const, 0, ""}, + {"SHT_RELA", Const, 0, ""}, + {"SHT_RISCV_ATTRIBUTES", Const, 25, ""}, + {"SHT_SHLIB", Const, 0, ""}, + {"SHT_STRTAB", Const, 0, ""}, + {"SHT_SYMTAB", Const, 0, ""}, + {"SHT_SYMTAB_SHNDX", Const, 0, ""}, + {"STB_GLOBAL", Const, 0, ""}, + {"STB_HIOS", Const, 0, ""}, + {"STB_HIPROC", Const, 0, ""}, + {"STB_LOCAL", Const, 0, ""}, + {"STB_LOOS", Const, 0, ""}, + {"STB_LOPROC", Const, 0, ""}, + {"STB_WEAK", Const, 0, ""}, + {"STT_COMMON", Const, 0, ""}, + {"STT_FILE", Const, 0, ""}, + {"STT_FUNC", Const, 0, ""}, + {"STT_GNU_IFUNC", Const, 23, ""}, + {"STT_HIOS", Const, 0, ""}, + {"STT_HIPROC", Const, 0, ""}, + {"STT_LOOS", Const, 0, ""}, + {"STT_LOPROC", Const, 0, ""}, + {"STT_NOTYPE", Const, 0, ""}, + {"STT_OBJECT", Const, 0, ""}, + {"STT_RELC", Const, 23, ""}, + {"STT_SECTION", Const, 0, ""}, + {"STT_SRELC", Const, 23, ""}, + {"STT_TLS", Const, 0, ""}, + {"STV_DEFAULT", Const, 0, ""}, + {"STV_HIDDEN", Const, 0, ""}, + {"STV_INTERNAL", Const, 0, ""}, + {"STV_PROTECTED", Const, 0, ""}, + {"ST_BIND", Func, 0, "func(info uint8) SymBind"}, + {"ST_INFO", Func, 0, "func(bind SymBind, typ SymType) uint8"}, + {"ST_TYPE", Func, 0, "func(info uint8) SymType"}, + {"ST_VISIBILITY", Func, 0, "func(other uint8) SymVis"}, + {"Section", Type, 0, ""}, + {"Section.ReaderAt", Field, 0, ""}, + {"Section.SectionHeader", Field, 0, ""}, + {"Section32", Type, 0, ""}, + {"Section32.Addr", Field, 0, ""}, + {"Section32.Addralign", Field, 0, ""}, + {"Section32.Entsize", Field, 0, ""}, + {"Section32.Flags", Field, 0, ""}, + {"Section32.Info", Field, 0, ""}, + {"Section32.Link", Field, 0, ""}, + {"Section32.Name", Field, 0, ""}, + {"Section32.Off", Field, 0, ""}, + {"Section32.Size", Field, 0, ""}, + {"Section32.Type", Field, 0, ""}, + {"Section64", Type, 0, ""}, + {"Section64.Addr", Field, 0, ""}, + {"Section64.Addralign", Field, 0, ""}, + {"Section64.Entsize", Field, 0, ""}, + {"Section64.Flags", Field, 0, ""}, + {"Section64.Info", Field, 0, ""}, + {"Section64.Link", Field, 0, ""}, + {"Section64.Name", Field, 0, ""}, + {"Section64.Off", Field, 0, ""}, + {"Section64.Size", Field, 0, ""}, + {"Section64.Type", Field, 0, ""}, + {"SectionFlag", Type, 0, ""}, + {"SectionHeader", Type, 0, ""}, + {"SectionHeader.Addr", Field, 0, ""}, + {"SectionHeader.Addralign", Field, 0, ""}, + {"SectionHeader.Entsize", Field, 0, ""}, + {"SectionHeader.FileSize", Field, 6, ""}, + {"SectionHeader.Flags", Field, 0, ""}, + {"SectionHeader.Info", Field, 0, ""}, + {"SectionHeader.Link", Field, 0, ""}, + {"SectionHeader.Name", Field, 0, ""}, + {"SectionHeader.Offset", Field, 0, ""}, + {"SectionHeader.Size", Field, 0, ""}, + {"SectionHeader.Type", Field, 0, ""}, + {"SectionIndex", Type, 0, ""}, + {"SectionType", Type, 0, ""}, + {"Sym32", Type, 0, ""}, + {"Sym32.Info", Field, 0, ""}, + {"Sym32.Name", Field, 0, ""}, + {"Sym32.Other", Field, 0, ""}, + {"Sym32.Shndx", Field, 0, ""}, + {"Sym32.Size", Field, 0, ""}, + {"Sym32.Value", Field, 0, ""}, + {"Sym32Size", Const, 0, ""}, + {"Sym64", Type, 0, ""}, + {"Sym64.Info", Field, 0, ""}, + {"Sym64.Name", Field, 0, ""}, + {"Sym64.Other", Field, 0, ""}, + {"Sym64.Shndx", Field, 0, ""}, + {"Sym64.Size", Field, 0, ""}, + {"Sym64.Value", Field, 0, ""}, + {"Sym64Size", Const, 0, ""}, + {"SymBind", Type, 0, ""}, + {"SymType", Type, 0, ""}, + {"SymVis", Type, 0, ""}, + {"Symbol", Type, 0, ""}, + {"Symbol.HasVersion", Field, 24, ""}, + {"Symbol.Info", Field, 0, ""}, + {"Symbol.Library", Field, 13, ""}, + {"Symbol.Name", Field, 0, ""}, + {"Symbol.Other", Field, 0, ""}, + {"Symbol.Section", Field, 0, ""}, + {"Symbol.Size", Field, 0, ""}, + {"Symbol.Value", Field, 0, ""}, + {"Symbol.Version", Field, 13, ""}, + {"Symbol.VersionIndex", Field, 24, ""}, + {"Type", Type, 0, ""}, + {"VER_FLG_BASE", Const, 24, ""}, + {"VER_FLG_INFO", Const, 24, ""}, + {"VER_FLG_WEAK", Const, 24, ""}, + {"Version", Type, 0, ""}, + {"VersionIndex", Type, 24, ""}, }, "debug/gosym": { - {"(*DecodingError).Error", Method, 0}, - {"(*LineTable).LineToPC", Method, 0}, - {"(*LineTable).PCToLine", Method, 0}, - {"(*Sym).BaseName", Method, 0}, - {"(*Sym).PackageName", Method, 0}, - {"(*Sym).ReceiverName", Method, 0}, - {"(*Sym).Static", Method, 0}, - {"(*Table).LineToPC", Method, 0}, - {"(*Table).LookupFunc", Method, 0}, - {"(*Table).LookupSym", Method, 0}, - {"(*Table).PCToFunc", Method, 0}, - {"(*Table).PCToLine", Method, 0}, - {"(*Table).SymByAddr", Method, 0}, - {"(*UnknownLineError).Error", Method, 0}, - {"(Func).BaseName", Method, 0}, - {"(Func).PackageName", Method, 0}, - {"(Func).ReceiverName", Method, 0}, - {"(Func).Static", Method, 0}, - {"(UnknownFileError).Error", Method, 0}, - {"DecodingError", Type, 0}, - {"Func", Type, 0}, - {"Func.End", Field, 0}, - {"Func.Entry", Field, 0}, - {"Func.FrameSize", Field, 0}, - {"Func.LineTable", Field, 0}, - {"Func.Locals", Field, 0}, - {"Func.Obj", Field, 0}, - {"Func.Params", Field, 0}, - {"Func.Sym", Field, 0}, - {"LineTable", Type, 0}, - {"LineTable.Data", Field, 0}, - {"LineTable.Line", Field, 0}, - {"LineTable.PC", Field, 0}, - {"NewLineTable", Func, 0}, - {"NewTable", Func, 0}, - {"Obj", Type, 0}, - {"Obj.Funcs", Field, 0}, - {"Obj.Paths", Field, 0}, - {"Sym", Type, 0}, - {"Sym.Func", Field, 0}, - {"Sym.GoType", Field, 0}, - {"Sym.Name", Field, 0}, - {"Sym.Type", Field, 0}, - {"Sym.Value", Field, 0}, - {"Table", Type, 0}, - {"Table.Files", Field, 0}, - {"Table.Funcs", Field, 0}, - {"Table.Objs", Field, 0}, - {"Table.Syms", Field, 0}, - {"UnknownFileError", Type, 0}, - {"UnknownLineError", Type, 0}, - {"UnknownLineError.File", Field, 0}, - {"UnknownLineError.Line", Field, 0}, + {"(*DecodingError).Error", Method, 0, ""}, + {"(*LineTable).LineToPC", Method, 0, ""}, + {"(*LineTable).PCToLine", Method, 0, ""}, + {"(*Sym).BaseName", Method, 0, ""}, + {"(*Sym).PackageName", Method, 0, ""}, + {"(*Sym).ReceiverName", Method, 0, ""}, + {"(*Sym).Static", Method, 0, ""}, + {"(*Table).LineToPC", Method, 0, ""}, + {"(*Table).LookupFunc", Method, 0, ""}, + {"(*Table).LookupSym", Method, 0, ""}, + {"(*Table).PCToFunc", Method, 0, ""}, + {"(*Table).PCToLine", Method, 0, ""}, + {"(*Table).SymByAddr", Method, 0, ""}, + {"(*UnknownLineError).Error", Method, 0, ""}, + {"(Func).BaseName", Method, 0, ""}, + {"(Func).PackageName", Method, 0, ""}, + {"(Func).ReceiverName", Method, 0, ""}, + {"(Func).Static", Method, 0, ""}, + {"(UnknownFileError).Error", Method, 0, ""}, + {"DecodingError", Type, 0, ""}, + {"Func", Type, 0, ""}, + {"Func.End", Field, 0, ""}, + {"Func.Entry", Field, 0, ""}, + {"Func.FrameSize", Field, 0, ""}, + {"Func.LineTable", Field, 0, ""}, + {"Func.Locals", Field, 0, ""}, + {"Func.Obj", Field, 0, ""}, + {"Func.Params", Field, 0, ""}, + {"Func.Sym", Field, 0, ""}, + {"LineTable", Type, 0, ""}, + {"LineTable.Data", Field, 0, ""}, + {"LineTable.Line", Field, 0, ""}, + {"LineTable.PC", Field, 0, ""}, + {"NewLineTable", Func, 0, "func(data []byte, text uint64) *LineTable"}, + {"NewTable", Func, 0, "func(symtab []byte, pcln *LineTable) (*Table, error)"}, + {"Obj", Type, 0, ""}, + {"Obj.Funcs", Field, 0, ""}, + {"Obj.Paths", Field, 0, ""}, + {"Sym", Type, 0, ""}, + {"Sym.Func", Field, 0, ""}, + {"Sym.GoType", Field, 0, ""}, + {"Sym.Name", Field, 0, ""}, + {"Sym.Type", Field, 0, ""}, + {"Sym.Value", Field, 0, ""}, + {"Table", Type, 0, ""}, + {"Table.Files", Field, 0, ""}, + {"Table.Funcs", Field, 0, ""}, + {"Table.Objs", Field, 0, ""}, + {"Table.Syms", Field, 0, ""}, + {"UnknownFileError", Type, 0, ""}, + {"UnknownLineError", Type, 0, ""}, + {"UnknownLineError.File", Field, 0, ""}, + {"UnknownLineError.Line", Field, 0, ""}, }, "debug/macho": { - {"(*FatFile).Close", Method, 3}, - {"(*File).Close", Method, 0}, - {"(*File).DWARF", Method, 0}, - {"(*File).ImportedLibraries", Method, 0}, - {"(*File).ImportedSymbols", Method, 0}, - {"(*File).Section", Method, 0}, - {"(*File).Segment", Method, 0}, - {"(*FormatError).Error", Method, 0}, - {"(*Section).Data", Method, 0}, - {"(*Section).Open", Method, 0}, - {"(*Segment).Data", Method, 0}, - {"(*Segment).Open", Method, 0}, - {"(Cpu).GoString", Method, 0}, - {"(Cpu).String", Method, 0}, - {"(Dylib).Raw", Method, 0}, - {"(Dysymtab).Raw", Method, 0}, - {"(FatArch).Close", Method, 3}, - {"(FatArch).DWARF", Method, 3}, - {"(FatArch).ImportedLibraries", Method, 3}, - {"(FatArch).ImportedSymbols", Method, 3}, - {"(FatArch).Section", Method, 3}, - {"(FatArch).Segment", Method, 3}, - {"(LoadBytes).Raw", Method, 0}, - {"(LoadCmd).GoString", Method, 0}, - {"(LoadCmd).String", Method, 0}, - {"(RelocTypeARM).GoString", Method, 10}, - {"(RelocTypeARM).String", Method, 10}, - {"(RelocTypeARM64).GoString", Method, 10}, - {"(RelocTypeARM64).String", Method, 10}, - {"(RelocTypeGeneric).GoString", Method, 10}, - {"(RelocTypeGeneric).String", Method, 10}, - {"(RelocTypeX86_64).GoString", Method, 10}, - {"(RelocTypeX86_64).String", Method, 10}, - {"(Rpath).Raw", Method, 10}, - {"(Section).ReadAt", Method, 0}, - {"(Segment).Raw", Method, 0}, - {"(Segment).ReadAt", Method, 0}, - {"(Symtab).Raw", Method, 0}, - {"(Type).GoString", Method, 10}, - {"(Type).String", Method, 10}, - {"ARM64_RELOC_ADDEND", Const, 10}, - {"ARM64_RELOC_BRANCH26", Const, 10}, - {"ARM64_RELOC_GOT_LOAD_PAGE21", Const, 10}, - {"ARM64_RELOC_GOT_LOAD_PAGEOFF12", Const, 10}, - {"ARM64_RELOC_PAGE21", Const, 10}, - {"ARM64_RELOC_PAGEOFF12", Const, 10}, - {"ARM64_RELOC_POINTER_TO_GOT", Const, 10}, - {"ARM64_RELOC_SUBTRACTOR", Const, 10}, - {"ARM64_RELOC_TLVP_LOAD_PAGE21", Const, 10}, - {"ARM64_RELOC_TLVP_LOAD_PAGEOFF12", Const, 10}, - {"ARM64_RELOC_UNSIGNED", Const, 10}, - {"ARM_RELOC_BR24", Const, 10}, - {"ARM_RELOC_HALF", Const, 10}, - {"ARM_RELOC_HALF_SECTDIFF", Const, 10}, - {"ARM_RELOC_LOCAL_SECTDIFF", Const, 10}, - {"ARM_RELOC_PAIR", Const, 10}, - {"ARM_RELOC_PB_LA_PTR", Const, 10}, - {"ARM_RELOC_SECTDIFF", Const, 10}, - {"ARM_RELOC_VANILLA", Const, 10}, - {"ARM_THUMB_32BIT_BRANCH", Const, 10}, - {"ARM_THUMB_RELOC_BR22", Const, 10}, - {"Cpu", Type, 0}, - {"Cpu386", Const, 0}, - {"CpuAmd64", Const, 0}, - {"CpuArm", Const, 3}, - {"CpuArm64", Const, 11}, - {"CpuPpc", Const, 3}, - {"CpuPpc64", Const, 3}, - {"Dylib", Type, 0}, - {"Dylib.CompatVersion", Field, 0}, - {"Dylib.CurrentVersion", Field, 0}, - {"Dylib.LoadBytes", Field, 0}, - {"Dylib.Name", Field, 0}, - {"Dylib.Time", Field, 0}, - {"DylibCmd", Type, 0}, - {"DylibCmd.Cmd", Field, 0}, - {"DylibCmd.CompatVersion", Field, 0}, - {"DylibCmd.CurrentVersion", Field, 0}, - {"DylibCmd.Len", Field, 0}, - {"DylibCmd.Name", Field, 0}, - {"DylibCmd.Time", Field, 0}, - {"Dysymtab", Type, 0}, - {"Dysymtab.DysymtabCmd", Field, 0}, - {"Dysymtab.IndirectSyms", Field, 0}, - {"Dysymtab.LoadBytes", Field, 0}, - {"DysymtabCmd", Type, 0}, - {"DysymtabCmd.Cmd", Field, 0}, - {"DysymtabCmd.Extrefsymoff", Field, 0}, - {"DysymtabCmd.Extreloff", Field, 0}, - {"DysymtabCmd.Iextdefsym", Field, 0}, - {"DysymtabCmd.Ilocalsym", Field, 0}, - {"DysymtabCmd.Indirectsymoff", Field, 0}, - {"DysymtabCmd.Iundefsym", Field, 0}, - {"DysymtabCmd.Len", Field, 0}, - {"DysymtabCmd.Locreloff", Field, 0}, - {"DysymtabCmd.Modtaboff", Field, 0}, - {"DysymtabCmd.Nextdefsym", Field, 0}, - {"DysymtabCmd.Nextrefsyms", Field, 0}, - {"DysymtabCmd.Nextrel", Field, 0}, - {"DysymtabCmd.Nindirectsyms", Field, 0}, - {"DysymtabCmd.Nlocalsym", Field, 0}, - {"DysymtabCmd.Nlocrel", Field, 0}, - {"DysymtabCmd.Nmodtab", Field, 0}, - {"DysymtabCmd.Ntoc", Field, 0}, - {"DysymtabCmd.Nundefsym", Field, 0}, - {"DysymtabCmd.Tocoffset", Field, 0}, - {"ErrNotFat", Var, 3}, - {"FatArch", Type, 3}, - {"FatArch.FatArchHeader", Field, 3}, - {"FatArch.File", Field, 3}, - {"FatArchHeader", Type, 3}, - {"FatArchHeader.Align", Field, 3}, - {"FatArchHeader.Cpu", Field, 3}, - {"FatArchHeader.Offset", Field, 3}, - {"FatArchHeader.Size", Field, 3}, - {"FatArchHeader.SubCpu", Field, 3}, - {"FatFile", Type, 3}, - {"FatFile.Arches", Field, 3}, - {"FatFile.Magic", Field, 3}, - {"File", Type, 0}, - {"File.ByteOrder", Field, 0}, - {"File.Dysymtab", Field, 0}, - {"File.FileHeader", Field, 0}, - {"File.Loads", Field, 0}, - {"File.Sections", Field, 0}, - {"File.Symtab", Field, 0}, - {"FileHeader", Type, 0}, - {"FileHeader.Cmdsz", Field, 0}, - {"FileHeader.Cpu", Field, 0}, - {"FileHeader.Flags", Field, 0}, - {"FileHeader.Magic", Field, 0}, - {"FileHeader.Ncmd", Field, 0}, - {"FileHeader.SubCpu", Field, 0}, - {"FileHeader.Type", Field, 0}, - {"FlagAllModsBound", Const, 10}, - {"FlagAllowStackExecution", Const, 10}, - {"FlagAppExtensionSafe", Const, 10}, - {"FlagBindAtLoad", Const, 10}, - {"FlagBindsToWeak", Const, 10}, - {"FlagCanonical", Const, 10}, - {"FlagDeadStrippableDylib", Const, 10}, - {"FlagDyldLink", Const, 10}, - {"FlagForceFlat", Const, 10}, - {"FlagHasTLVDescriptors", Const, 10}, - {"FlagIncrLink", Const, 10}, - {"FlagLazyInit", Const, 10}, - {"FlagNoFixPrebinding", Const, 10}, - {"FlagNoHeapExecution", Const, 10}, - {"FlagNoMultiDefs", Const, 10}, - {"FlagNoReexportedDylibs", Const, 10}, - {"FlagNoUndefs", Const, 10}, - {"FlagPIE", Const, 10}, - {"FlagPrebindable", Const, 10}, - {"FlagPrebound", Const, 10}, - {"FlagRootSafe", Const, 10}, - {"FlagSetuidSafe", Const, 10}, - {"FlagSplitSegs", Const, 10}, - {"FlagSubsectionsViaSymbols", Const, 10}, - {"FlagTwoLevel", Const, 10}, - {"FlagWeakDefines", Const, 10}, - {"FormatError", Type, 0}, - {"GENERIC_RELOC_LOCAL_SECTDIFF", Const, 10}, - {"GENERIC_RELOC_PAIR", Const, 10}, - {"GENERIC_RELOC_PB_LA_PTR", Const, 10}, - {"GENERIC_RELOC_SECTDIFF", Const, 10}, - {"GENERIC_RELOC_TLV", Const, 10}, - {"GENERIC_RELOC_VANILLA", Const, 10}, - {"Load", Type, 0}, - {"LoadBytes", Type, 0}, - {"LoadCmd", Type, 0}, - {"LoadCmdDylib", Const, 0}, - {"LoadCmdDylinker", Const, 0}, - {"LoadCmdDysymtab", Const, 0}, - {"LoadCmdRpath", Const, 10}, - {"LoadCmdSegment", Const, 0}, - {"LoadCmdSegment64", Const, 0}, - {"LoadCmdSymtab", Const, 0}, - {"LoadCmdThread", Const, 0}, - {"LoadCmdUnixThread", Const, 0}, - {"Magic32", Const, 0}, - {"Magic64", Const, 0}, - {"MagicFat", Const, 3}, - {"NewFatFile", Func, 3}, - {"NewFile", Func, 0}, - {"Nlist32", Type, 0}, - {"Nlist32.Desc", Field, 0}, - {"Nlist32.Name", Field, 0}, - {"Nlist32.Sect", Field, 0}, - {"Nlist32.Type", Field, 0}, - {"Nlist32.Value", Field, 0}, - {"Nlist64", Type, 0}, - {"Nlist64.Desc", Field, 0}, - {"Nlist64.Name", Field, 0}, - {"Nlist64.Sect", Field, 0}, - {"Nlist64.Type", Field, 0}, - {"Nlist64.Value", Field, 0}, - {"Open", Func, 0}, - {"OpenFat", Func, 3}, - {"Regs386", Type, 0}, - {"Regs386.AX", Field, 0}, - {"Regs386.BP", Field, 0}, - {"Regs386.BX", Field, 0}, - {"Regs386.CS", Field, 0}, - {"Regs386.CX", Field, 0}, - {"Regs386.DI", Field, 0}, - {"Regs386.DS", Field, 0}, - {"Regs386.DX", Field, 0}, - {"Regs386.ES", Field, 0}, - {"Regs386.FLAGS", Field, 0}, - {"Regs386.FS", Field, 0}, - {"Regs386.GS", Field, 0}, - {"Regs386.IP", Field, 0}, - {"Regs386.SI", Field, 0}, - {"Regs386.SP", Field, 0}, - {"Regs386.SS", Field, 0}, - {"RegsAMD64", Type, 0}, - {"RegsAMD64.AX", Field, 0}, - {"RegsAMD64.BP", Field, 0}, - {"RegsAMD64.BX", Field, 0}, - {"RegsAMD64.CS", Field, 0}, - {"RegsAMD64.CX", Field, 0}, - {"RegsAMD64.DI", Field, 0}, - {"RegsAMD64.DX", Field, 0}, - {"RegsAMD64.FLAGS", Field, 0}, - {"RegsAMD64.FS", Field, 0}, - {"RegsAMD64.GS", Field, 0}, - {"RegsAMD64.IP", Field, 0}, - {"RegsAMD64.R10", Field, 0}, - {"RegsAMD64.R11", Field, 0}, - {"RegsAMD64.R12", Field, 0}, - {"RegsAMD64.R13", Field, 0}, - {"RegsAMD64.R14", Field, 0}, - {"RegsAMD64.R15", Field, 0}, - {"RegsAMD64.R8", Field, 0}, - {"RegsAMD64.R9", Field, 0}, - {"RegsAMD64.SI", Field, 0}, - {"RegsAMD64.SP", Field, 0}, - {"Reloc", Type, 10}, - {"Reloc.Addr", Field, 10}, - {"Reloc.Extern", Field, 10}, - {"Reloc.Len", Field, 10}, - {"Reloc.Pcrel", Field, 10}, - {"Reloc.Scattered", Field, 10}, - {"Reloc.Type", Field, 10}, - {"Reloc.Value", Field, 10}, - {"RelocTypeARM", Type, 10}, - {"RelocTypeARM64", Type, 10}, - {"RelocTypeGeneric", Type, 10}, - {"RelocTypeX86_64", Type, 10}, - {"Rpath", Type, 10}, - {"Rpath.LoadBytes", Field, 10}, - {"Rpath.Path", Field, 10}, - {"RpathCmd", Type, 10}, - {"RpathCmd.Cmd", Field, 10}, - {"RpathCmd.Len", Field, 10}, - {"RpathCmd.Path", Field, 10}, - {"Section", Type, 0}, - {"Section.ReaderAt", Field, 0}, - {"Section.Relocs", Field, 10}, - {"Section.SectionHeader", Field, 0}, - {"Section32", Type, 0}, - {"Section32.Addr", Field, 0}, - {"Section32.Align", Field, 0}, - {"Section32.Flags", Field, 0}, - {"Section32.Name", Field, 0}, - {"Section32.Nreloc", Field, 0}, - {"Section32.Offset", Field, 0}, - {"Section32.Reloff", Field, 0}, - {"Section32.Reserve1", Field, 0}, - {"Section32.Reserve2", Field, 0}, - {"Section32.Seg", Field, 0}, - {"Section32.Size", Field, 0}, - {"Section64", Type, 0}, - {"Section64.Addr", Field, 0}, - {"Section64.Align", Field, 0}, - {"Section64.Flags", Field, 0}, - {"Section64.Name", Field, 0}, - {"Section64.Nreloc", Field, 0}, - {"Section64.Offset", Field, 0}, - {"Section64.Reloff", Field, 0}, - {"Section64.Reserve1", Field, 0}, - {"Section64.Reserve2", Field, 0}, - {"Section64.Reserve3", Field, 0}, - {"Section64.Seg", Field, 0}, - {"Section64.Size", Field, 0}, - {"SectionHeader", Type, 0}, - {"SectionHeader.Addr", Field, 0}, - {"SectionHeader.Align", Field, 0}, - {"SectionHeader.Flags", Field, 0}, - {"SectionHeader.Name", Field, 0}, - {"SectionHeader.Nreloc", Field, 0}, - {"SectionHeader.Offset", Field, 0}, - {"SectionHeader.Reloff", Field, 0}, - {"SectionHeader.Seg", Field, 0}, - {"SectionHeader.Size", Field, 0}, - {"Segment", Type, 0}, - {"Segment.LoadBytes", Field, 0}, - {"Segment.ReaderAt", Field, 0}, - {"Segment.SegmentHeader", Field, 0}, - {"Segment32", Type, 0}, - {"Segment32.Addr", Field, 0}, - {"Segment32.Cmd", Field, 0}, - {"Segment32.Filesz", Field, 0}, - {"Segment32.Flag", Field, 0}, - {"Segment32.Len", Field, 0}, - {"Segment32.Maxprot", Field, 0}, - {"Segment32.Memsz", Field, 0}, - {"Segment32.Name", Field, 0}, - {"Segment32.Nsect", Field, 0}, - {"Segment32.Offset", Field, 0}, - {"Segment32.Prot", Field, 0}, - {"Segment64", Type, 0}, - {"Segment64.Addr", Field, 0}, - {"Segment64.Cmd", Field, 0}, - {"Segment64.Filesz", Field, 0}, - {"Segment64.Flag", Field, 0}, - {"Segment64.Len", Field, 0}, - {"Segment64.Maxprot", Field, 0}, - {"Segment64.Memsz", Field, 0}, - {"Segment64.Name", Field, 0}, - {"Segment64.Nsect", Field, 0}, - {"Segment64.Offset", Field, 0}, - {"Segment64.Prot", Field, 0}, - {"SegmentHeader", Type, 0}, - {"SegmentHeader.Addr", Field, 0}, - {"SegmentHeader.Cmd", Field, 0}, - {"SegmentHeader.Filesz", Field, 0}, - {"SegmentHeader.Flag", Field, 0}, - {"SegmentHeader.Len", Field, 0}, - {"SegmentHeader.Maxprot", Field, 0}, - {"SegmentHeader.Memsz", Field, 0}, - {"SegmentHeader.Name", Field, 0}, - {"SegmentHeader.Nsect", Field, 0}, - {"SegmentHeader.Offset", Field, 0}, - {"SegmentHeader.Prot", Field, 0}, - {"Symbol", Type, 0}, - {"Symbol.Desc", Field, 0}, - {"Symbol.Name", Field, 0}, - {"Symbol.Sect", Field, 0}, - {"Symbol.Type", Field, 0}, - {"Symbol.Value", Field, 0}, - {"Symtab", Type, 0}, - {"Symtab.LoadBytes", Field, 0}, - {"Symtab.Syms", Field, 0}, - {"Symtab.SymtabCmd", Field, 0}, - {"SymtabCmd", Type, 0}, - {"SymtabCmd.Cmd", Field, 0}, - {"SymtabCmd.Len", Field, 0}, - {"SymtabCmd.Nsyms", Field, 0}, - {"SymtabCmd.Stroff", Field, 0}, - {"SymtabCmd.Strsize", Field, 0}, - {"SymtabCmd.Symoff", Field, 0}, - {"Thread", Type, 0}, - {"Thread.Cmd", Field, 0}, - {"Thread.Data", Field, 0}, - {"Thread.Len", Field, 0}, - {"Thread.Type", Field, 0}, - {"Type", Type, 0}, - {"TypeBundle", Const, 3}, - {"TypeDylib", Const, 3}, - {"TypeExec", Const, 0}, - {"TypeObj", Const, 0}, - {"X86_64_RELOC_BRANCH", Const, 10}, - {"X86_64_RELOC_GOT", Const, 10}, - {"X86_64_RELOC_GOT_LOAD", Const, 10}, - {"X86_64_RELOC_SIGNED", Const, 10}, - {"X86_64_RELOC_SIGNED_1", Const, 10}, - {"X86_64_RELOC_SIGNED_2", Const, 10}, - {"X86_64_RELOC_SIGNED_4", Const, 10}, - {"X86_64_RELOC_SUBTRACTOR", Const, 10}, - {"X86_64_RELOC_TLV", Const, 10}, - {"X86_64_RELOC_UNSIGNED", Const, 10}, + {"(*FatFile).Close", Method, 3, ""}, + {"(*File).Close", Method, 0, ""}, + {"(*File).DWARF", Method, 0, ""}, + {"(*File).ImportedLibraries", Method, 0, ""}, + {"(*File).ImportedSymbols", Method, 0, ""}, + {"(*File).Section", Method, 0, ""}, + {"(*File).Segment", Method, 0, ""}, + {"(*FormatError).Error", Method, 0, ""}, + {"(*Section).Data", Method, 0, ""}, + {"(*Section).Open", Method, 0, ""}, + {"(*Segment).Data", Method, 0, ""}, + {"(*Segment).Open", Method, 0, ""}, + {"(Cpu).GoString", Method, 0, ""}, + {"(Cpu).String", Method, 0, ""}, + {"(Dylib).Raw", Method, 0, ""}, + {"(Dysymtab).Raw", Method, 0, ""}, + {"(FatArch).Close", Method, 3, ""}, + {"(FatArch).DWARF", Method, 3, ""}, + {"(FatArch).ImportedLibraries", Method, 3, ""}, + {"(FatArch).ImportedSymbols", Method, 3, ""}, + {"(FatArch).Section", Method, 3, ""}, + {"(FatArch).Segment", Method, 3, ""}, + {"(LoadBytes).Raw", Method, 0, ""}, + {"(LoadCmd).GoString", Method, 0, ""}, + {"(LoadCmd).String", Method, 0, ""}, + {"(RelocTypeARM).GoString", Method, 10, ""}, + {"(RelocTypeARM).String", Method, 10, ""}, + {"(RelocTypeARM64).GoString", Method, 10, ""}, + {"(RelocTypeARM64).String", Method, 10, ""}, + {"(RelocTypeGeneric).GoString", Method, 10, ""}, + {"(RelocTypeGeneric).String", Method, 10, ""}, + {"(RelocTypeX86_64).GoString", Method, 10, ""}, + {"(RelocTypeX86_64).String", Method, 10, ""}, + {"(Rpath).Raw", Method, 10, ""}, + {"(Section).ReadAt", Method, 0, ""}, + {"(Segment).Raw", Method, 0, ""}, + {"(Segment).ReadAt", Method, 0, ""}, + {"(Symtab).Raw", Method, 0, ""}, + {"(Type).GoString", Method, 10, ""}, + {"(Type).String", Method, 10, ""}, + {"ARM64_RELOC_ADDEND", Const, 10, ""}, + {"ARM64_RELOC_BRANCH26", Const, 10, ""}, + {"ARM64_RELOC_GOT_LOAD_PAGE21", Const, 10, ""}, + {"ARM64_RELOC_GOT_LOAD_PAGEOFF12", Const, 10, ""}, + {"ARM64_RELOC_PAGE21", Const, 10, ""}, + {"ARM64_RELOC_PAGEOFF12", Const, 10, ""}, + {"ARM64_RELOC_POINTER_TO_GOT", Const, 10, ""}, + {"ARM64_RELOC_SUBTRACTOR", Const, 10, ""}, + {"ARM64_RELOC_TLVP_LOAD_PAGE21", Const, 10, ""}, + {"ARM64_RELOC_TLVP_LOAD_PAGEOFF12", Const, 10, ""}, + {"ARM64_RELOC_UNSIGNED", Const, 10, ""}, + {"ARM_RELOC_BR24", Const, 10, ""}, + {"ARM_RELOC_HALF", Const, 10, ""}, + {"ARM_RELOC_HALF_SECTDIFF", Const, 10, ""}, + {"ARM_RELOC_LOCAL_SECTDIFF", Const, 10, ""}, + {"ARM_RELOC_PAIR", Const, 10, ""}, + {"ARM_RELOC_PB_LA_PTR", Const, 10, ""}, + {"ARM_RELOC_SECTDIFF", Const, 10, ""}, + {"ARM_RELOC_VANILLA", Const, 10, ""}, + {"ARM_THUMB_32BIT_BRANCH", Const, 10, ""}, + {"ARM_THUMB_RELOC_BR22", Const, 10, ""}, + {"Cpu", Type, 0, ""}, + {"Cpu386", Const, 0, ""}, + {"CpuAmd64", Const, 0, ""}, + {"CpuArm", Const, 3, ""}, + {"CpuArm64", Const, 11, ""}, + {"CpuPpc", Const, 3, ""}, + {"CpuPpc64", Const, 3, ""}, + {"Dylib", Type, 0, ""}, + {"Dylib.CompatVersion", Field, 0, ""}, + {"Dylib.CurrentVersion", Field, 0, ""}, + {"Dylib.LoadBytes", Field, 0, ""}, + {"Dylib.Name", Field, 0, ""}, + {"Dylib.Time", Field, 0, ""}, + {"DylibCmd", Type, 0, ""}, + {"DylibCmd.Cmd", Field, 0, ""}, + {"DylibCmd.CompatVersion", Field, 0, ""}, + {"DylibCmd.CurrentVersion", Field, 0, ""}, + {"DylibCmd.Len", Field, 0, ""}, + {"DylibCmd.Name", Field, 0, ""}, + {"DylibCmd.Time", Field, 0, ""}, + {"Dysymtab", Type, 0, ""}, + {"Dysymtab.DysymtabCmd", Field, 0, ""}, + {"Dysymtab.IndirectSyms", Field, 0, ""}, + {"Dysymtab.LoadBytes", Field, 0, ""}, + {"DysymtabCmd", Type, 0, ""}, + {"DysymtabCmd.Cmd", Field, 0, ""}, + {"DysymtabCmd.Extrefsymoff", Field, 0, ""}, + {"DysymtabCmd.Extreloff", Field, 0, ""}, + {"DysymtabCmd.Iextdefsym", Field, 0, ""}, + {"DysymtabCmd.Ilocalsym", Field, 0, ""}, + {"DysymtabCmd.Indirectsymoff", Field, 0, ""}, + {"DysymtabCmd.Iundefsym", Field, 0, ""}, + {"DysymtabCmd.Len", Field, 0, ""}, + {"DysymtabCmd.Locreloff", Field, 0, ""}, + {"DysymtabCmd.Modtaboff", Field, 0, ""}, + {"DysymtabCmd.Nextdefsym", Field, 0, ""}, + {"DysymtabCmd.Nextrefsyms", Field, 0, ""}, + {"DysymtabCmd.Nextrel", Field, 0, ""}, + {"DysymtabCmd.Nindirectsyms", Field, 0, ""}, + {"DysymtabCmd.Nlocalsym", Field, 0, ""}, + {"DysymtabCmd.Nlocrel", Field, 0, ""}, + {"DysymtabCmd.Nmodtab", Field, 0, ""}, + {"DysymtabCmd.Ntoc", Field, 0, ""}, + {"DysymtabCmd.Nundefsym", Field, 0, ""}, + {"DysymtabCmd.Tocoffset", Field, 0, ""}, + {"ErrNotFat", Var, 3, ""}, + {"FatArch", Type, 3, ""}, + {"FatArch.FatArchHeader", Field, 3, ""}, + {"FatArch.File", Field, 3, ""}, + {"FatArchHeader", Type, 3, ""}, + {"FatArchHeader.Align", Field, 3, ""}, + {"FatArchHeader.Cpu", Field, 3, ""}, + {"FatArchHeader.Offset", Field, 3, ""}, + {"FatArchHeader.Size", Field, 3, ""}, + {"FatArchHeader.SubCpu", Field, 3, ""}, + {"FatFile", Type, 3, ""}, + {"FatFile.Arches", Field, 3, ""}, + {"FatFile.Magic", Field, 3, ""}, + {"File", Type, 0, ""}, + {"File.ByteOrder", Field, 0, ""}, + {"File.Dysymtab", Field, 0, ""}, + {"File.FileHeader", Field, 0, ""}, + {"File.Loads", Field, 0, ""}, + {"File.Sections", Field, 0, ""}, + {"File.Symtab", Field, 0, ""}, + {"FileHeader", Type, 0, ""}, + {"FileHeader.Cmdsz", Field, 0, ""}, + {"FileHeader.Cpu", Field, 0, ""}, + {"FileHeader.Flags", Field, 0, ""}, + {"FileHeader.Magic", Field, 0, ""}, + {"FileHeader.Ncmd", Field, 0, ""}, + {"FileHeader.SubCpu", Field, 0, ""}, + {"FileHeader.Type", Field, 0, ""}, + {"FlagAllModsBound", Const, 10, ""}, + {"FlagAllowStackExecution", Const, 10, ""}, + {"FlagAppExtensionSafe", Const, 10, ""}, + {"FlagBindAtLoad", Const, 10, ""}, + {"FlagBindsToWeak", Const, 10, ""}, + {"FlagCanonical", Const, 10, ""}, + {"FlagDeadStrippableDylib", Const, 10, ""}, + {"FlagDyldLink", Const, 10, ""}, + {"FlagForceFlat", Const, 10, ""}, + {"FlagHasTLVDescriptors", Const, 10, ""}, + {"FlagIncrLink", Const, 10, ""}, + {"FlagLazyInit", Const, 10, ""}, + {"FlagNoFixPrebinding", Const, 10, ""}, + {"FlagNoHeapExecution", Const, 10, ""}, + {"FlagNoMultiDefs", Const, 10, ""}, + {"FlagNoReexportedDylibs", Const, 10, ""}, + {"FlagNoUndefs", Const, 10, ""}, + {"FlagPIE", Const, 10, ""}, + {"FlagPrebindable", Const, 10, ""}, + {"FlagPrebound", Const, 10, ""}, + {"FlagRootSafe", Const, 10, ""}, + {"FlagSetuidSafe", Const, 10, ""}, + {"FlagSplitSegs", Const, 10, ""}, + {"FlagSubsectionsViaSymbols", Const, 10, ""}, + {"FlagTwoLevel", Const, 10, ""}, + {"FlagWeakDefines", Const, 10, ""}, + {"FormatError", Type, 0, ""}, + {"GENERIC_RELOC_LOCAL_SECTDIFF", Const, 10, ""}, + {"GENERIC_RELOC_PAIR", Const, 10, ""}, + {"GENERIC_RELOC_PB_LA_PTR", Const, 10, ""}, + {"GENERIC_RELOC_SECTDIFF", Const, 10, ""}, + {"GENERIC_RELOC_TLV", Const, 10, ""}, + {"GENERIC_RELOC_VANILLA", Const, 10, ""}, + {"Load", Type, 0, ""}, + {"LoadBytes", Type, 0, ""}, + {"LoadCmd", Type, 0, ""}, + {"LoadCmdDylib", Const, 0, ""}, + {"LoadCmdDylinker", Const, 0, ""}, + {"LoadCmdDysymtab", Const, 0, ""}, + {"LoadCmdRpath", Const, 10, ""}, + {"LoadCmdSegment", Const, 0, ""}, + {"LoadCmdSegment64", Const, 0, ""}, + {"LoadCmdSymtab", Const, 0, ""}, + {"LoadCmdThread", Const, 0, ""}, + {"LoadCmdUnixThread", Const, 0, ""}, + {"Magic32", Const, 0, ""}, + {"Magic64", Const, 0, ""}, + {"MagicFat", Const, 3, ""}, + {"NewFatFile", Func, 3, "func(r io.ReaderAt) (*FatFile, error)"}, + {"NewFile", Func, 0, "func(r io.ReaderAt) (*File, error)"}, + {"Nlist32", Type, 0, ""}, + {"Nlist32.Desc", Field, 0, ""}, + {"Nlist32.Name", Field, 0, ""}, + {"Nlist32.Sect", Field, 0, ""}, + {"Nlist32.Type", Field, 0, ""}, + {"Nlist32.Value", Field, 0, ""}, + {"Nlist64", Type, 0, ""}, + {"Nlist64.Desc", Field, 0, ""}, + {"Nlist64.Name", Field, 0, ""}, + {"Nlist64.Sect", Field, 0, ""}, + {"Nlist64.Type", Field, 0, ""}, + {"Nlist64.Value", Field, 0, ""}, + {"Open", Func, 0, "func(name string) (*File, error)"}, + {"OpenFat", Func, 3, "func(name string) (*FatFile, error)"}, + {"Regs386", Type, 0, ""}, + {"Regs386.AX", Field, 0, ""}, + {"Regs386.BP", Field, 0, ""}, + {"Regs386.BX", Field, 0, ""}, + {"Regs386.CS", Field, 0, ""}, + {"Regs386.CX", Field, 0, ""}, + {"Regs386.DI", Field, 0, ""}, + {"Regs386.DS", Field, 0, ""}, + {"Regs386.DX", Field, 0, ""}, + {"Regs386.ES", Field, 0, ""}, + {"Regs386.FLAGS", Field, 0, ""}, + {"Regs386.FS", Field, 0, ""}, + {"Regs386.GS", Field, 0, ""}, + {"Regs386.IP", Field, 0, ""}, + {"Regs386.SI", Field, 0, ""}, + {"Regs386.SP", Field, 0, ""}, + {"Regs386.SS", Field, 0, ""}, + {"RegsAMD64", Type, 0, ""}, + {"RegsAMD64.AX", Field, 0, ""}, + {"RegsAMD64.BP", Field, 0, ""}, + {"RegsAMD64.BX", Field, 0, ""}, + {"RegsAMD64.CS", Field, 0, ""}, + {"RegsAMD64.CX", Field, 0, ""}, + {"RegsAMD64.DI", Field, 0, ""}, + {"RegsAMD64.DX", Field, 0, ""}, + {"RegsAMD64.FLAGS", Field, 0, ""}, + {"RegsAMD64.FS", Field, 0, ""}, + {"RegsAMD64.GS", Field, 0, ""}, + {"RegsAMD64.IP", Field, 0, ""}, + {"RegsAMD64.R10", Field, 0, ""}, + {"RegsAMD64.R11", Field, 0, ""}, + {"RegsAMD64.R12", Field, 0, ""}, + {"RegsAMD64.R13", Field, 0, ""}, + {"RegsAMD64.R14", Field, 0, ""}, + {"RegsAMD64.R15", Field, 0, ""}, + {"RegsAMD64.R8", Field, 0, ""}, + {"RegsAMD64.R9", Field, 0, ""}, + {"RegsAMD64.SI", Field, 0, ""}, + {"RegsAMD64.SP", Field, 0, ""}, + {"Reloc", Type, 10, ""}, + {"Reloc.Addr", Field, 10, ""}, + {"Reloc.Extern", Field, 10, ""}, + {"Reloc.Len", Field, 10, ""}, + {"Reloc.Pcrel", Field, 10, ""}, + {"Reloc.Scattered", Field, 10, ""}, + {"Reloc.Type", Field, 10, ""}, + {"Reloc.Value", Field, 10, ""}, + {"RelocTypeARM", Type, 10, ""}, + {"RelocTypeARM64", Type, 10, ""}, + {"RelocTypeGeneric", Type, 10, ""}, + {"RelocTypeX86_64", Type, 10, ""}, + {"Rpath", Type, 10, ""}, + {"Rpath.LoadBytes", Field, 10, ""}, + {"Rpath.Path", Field, 10, ""}, + {"RpathCmd", Type, 10, ""}, + {"RpathCmd.Cmd", Field, 10, ""}, + {"RpathCmd.Len", Field, 10, ""}, + {"RpathCmd.Path", Field, 10, ""}, + {"Section", Type, 0, ""}, + {"Section.ReaderAt", Field, 0, ""}, + {"Section.Relocs", Field, 10, ""}, + {"Section.SectionHeader", Field, 0, ""}, + {"Section32", Type, 0, ""}, + {"Section32.Addr", Field, 0, ""}, + {"Section32.Align", Field, 0, ""}, + {"Section32.Flags", Field, 0, ""}, + {"Section32.Name", Field, 0, ""}, + {"Section32.Nreloc", Field, 0, ""}, + {"Section32.Offset", Field, 0, ""}, + {"Section32.Reloff", Field, 0, ""}, + {"Section32.Reserve1", Field, 0, ""}, + {"Section32.Reserve2", Field, 0, ""}, + {"Section32.Seg", Field, 0, ""}, + {"Section32.Size", Field, 0, ""}, + {"Section64", Type, 0, ""}, + {"Section64.Addr", Field, 0, ""}, + {"Section64.Align", Field, 0, ""}, + {"Section64.Flags", Field, 0, ""}, + {"Section64.Name", Field, 0, ""}, + {"Section64.Nreloc", Field, 0, ""}, + {"Section64.Offset", Field, 0, ""}, + {"Section64.Reloff", Field, 0, ""}, + {"Section64.Reserve1", Field, 0, ""}, + {"Section64.Reserve2", Field, 0, ""}, + {"Section64.Reserve3", Field, 0, ""}, + {"Section64.Seg", Field, 0, ""}, + {"Section64.Size", Field, 0, ""}, + {"SectionHeader", Type, 0, ""}, + {"SectionHeader.Addr", Field, 0, ""}, + {"SectionHeader.Align", Field, 0, ""}, + {"SectionHeader.Flags", Field, 0, ""}, + {"SectionHeader.Name", Field, 0, ""}, + {"SectionHeader.Nreloc", Field, 0, ""}, + {"SectionHeader.Offset", Field, 0, ""}, + {"SectionHeader.Reloff", Field, 0, ""}, + {"SectionHeader.Seg", Field, 0, ""}, + {"SectionHeader.Size", Field, 0, ""}, + {"Segment", Type, 0, ""}, + {"Segment.LoadBytes", Field, 0, ""}, + {"Segment.ReaderAt", Field, 0, ""}, + {"Segment.SegmentHeader", Field, 0, ""}, + {"Segment32", Type, 0, ""}, + {"Segment32.Addr", Field, 0, ""}, + {"Segment32.Cmd", Field, 0, ""}, + {"Segment32.Filesz", Field, 0, ""}, + {"Segment32.Flag", Field, 0, ""}, + {"Segment32.Len", Field, 0, ""}, + {"Segment32.Maxprot", Field, 0, ""}, + {"Segment32.Memsz", Field, 0, ""}, + {"Segment32.Name", Field, 0, ""}, + {"Segment32.Nsect", Field, 0, ""}, + {"Segment32.Offset", Field, 0, ""}, + {"Segment32.Prot", Field, 0, ""}, + {"Segment64", Type, 0, ""}, + {"Segment64.Addr", Field, 0, ""}, + {"Segment64.Cmd", Field, 0, ""}, + {"Segment64.Filesz", Field, 0, ""}, + {"Segment64.Flag", Field, 0, ""}, + {"Segment64.Len", Field, 0, ""}, + {"Segment64.Maxprot", Field, 0, ""}, + {"Segment64.Memsz", Field, 0, ""}, + {"Segment64.Name", Field, 0, ""}, + {"Segment64.Nsect", Field, 0, ""}, + {"Segment64.Offset", Field, 0, ""}, + {"Segment64.Prot", Field, 0, ""}, + {"SegmentHeader", Type, 0, ""}, + {"SegmentHeader.Addr", Field, 0, ""}, + {"SegmentHeader.Cmd", Field, 0, ""}, + {"SegmentHeader.Filesz", Field, 0, ""}, + {"SegmentHeader.Flag", Field, 0, ""}, + {"SegmentHeader.Len", Field, 0, ""}, + {"SegmentHeader.Maxprot", Field, 0, ""}, + {"SegmentHeader.Memsz", Field, 0, ""}, + {"SegmentHeader.Name", Field, 0, ""}, + {"SegmentHeader.Nsect", Field, 0, ""}, + {"SegmentHeader.Offset", Field, 0, ""}, + {"SegmentHeader.Prot", Field, 0, ""}, + {"Symbol", Type, 0, ""}, + {"Symbol.Desc", Field, 0, ""}, + {"Symbol.Name", Field, 0, ""}, + {"Symbol.Sect", Field, 0, ""}, + {"Symbol.Type", Field, 0, ""}, + {"Symbol.Value", Field, 0, ""}, + {"Symtab", Type, 0, ""}, + {"Symtab.LoadBytes", Field, 0, ""}, + {"Symtab.Syms", Field, 0, ""}, + {"Symtab.SymtabCmd", Field, 0, ""}, + {"SymtabCmd", Type, 0, ""}, + {"SymtabCmd.Cmd", Field, 0, ""}, + {"SymtabCmd.Len", Field, 0, ""}, + {"SymtabCmd.Nsyms", Field, 0, ""}, + {"SymtabCmd.Stroff", Field, 0, ""}, + {"SymtabCmd.Strsize", Field, 0, ""}, + {"SymtabCmd.Symoff", Field, 0, ""}, + {"Thread", Type, 0, ""}, + {"Thread.Cmd", Field, 0, ""}, + {"Thread.Data", Field, 0, ""}, + {"Thread.Len", Field, 0, ""}, + {"Thread.Type", Field, 0, ""}, + {"Type", Type, 0, ""}, + {"TypeBundle", Const, 3, ""}, + {"TypeDylib", Const, 3, ""}, + {"TypeExec", Const, 0, ""}, + {"TypeObj", Const, 0, ""}, + {"X86_64_RELOC_BRANCH", Const, 10, ""}, + {"X86_64_RELOC_GOT", Const, 10, ""}, + {"X86_64_RELOC_GOT_LOAD", Const, 10, ""}, + {"X86_64_RELOC_SIGNED", Const, 10, ""}, + {"X86_64_RELOC_SIGNED_1", Const, 10, ""}, + {"X86_64_RELOC_SIGNED_2", Const, 10, ""}, + {"X86_64_RELOC_SIGNED_4", Const, 10, ""}, + {"X86_64_RELOC_SUBTRACTOR", Const, 10, ""}, + {"X86_64_RELOC_TLV", Const, 10, ""}, + {"X86_64_RELOC_UNSIGNED", Const, 10, ""}, }, "debug/pe": { - {"(*COFFSymbol).FullName", Method, 8}, - {"(*File).COFFSymbolReadSectionDefAux", Method, 19}, - {"(*File).Close", Method, 0}, - {"(*File).DWARF", Method, 0}, - {"(*File).ImportedLibraries", Method, 0}, - {"(*File).ImportedSymbols", Method, 0}, - {"(*File).Section", Method, 0}, - {"(*FormatError).Error", Method, 0}, - {"(*Section).Data", Method, 0}, - {"(*Section).Open", Method, 0}, - {"(Section).ReadAt", Method, 0}, - {"(StringTable).String", Method, 8}, - {"COFFSymbol", Type, 1}, - {"COFFSymbol.Name", Field, 1}, - {"COFFSymbol.NumberOfAuxSymbols", Field, 1}, - {"COFFSymbol.SectionNumber", Field, 1}, - {"COFFSymbol.StorageClass", Field, 1}, - {"COFFSymbol.Type", Field, 1}, - {"COFFSymbol.Value", Field, 1}, - {"COFFSymbolAuxFormat5", Type, 19}, - {"COFFSymbolAuxFormat5.Checksum", Field, 19}, - {"COFFSymbolAuxFormat5.NumLineNumbers", Field, 19}, - {"COFFSymbolAuxFormat5.NumRelocs", Field, 19}, - {"COFFSymbolAuxFormat5.SecNum", Field, 19}, - {"COFFSymbolAuxFormat5.Selection", Field, 19}, - {"COFFSymbolAuxFormat5.Size", Field, 19}, - {"COFFSymbolSize", Const, 1}, - {"DataDirectory", Type, 3}, - {"DataDirectory.Size", Field, 3}, - {"DataDirectory.VirtualAddress", Field, 3}, - {"File", Type, 0}, - {"File.COFFSymbols", Field, 8}, - {"File.FileHeader", Field, 0}, - {"File.OptionalHeader", Field, 3}, - {"File.Sections", Field, 0}, - {"File.StringTable", Field, 8}, - {"File.Symbols", Field, 1}, - {"FileHeader", Type, 0}, - {"FileHeader.Characteristics", Field, 0}, - {"FileHeader.Machine", Field, 0}, - {"FileHeader.NumberOfSections", Field, 0}, - {"FileHeader.NumberOfSymbols", Field, 0}, - {"FileHeader.PointerToSymbolTable", Field, 0}, - {"FileHeader.SizeOfOptionalHeader", Field, 0}, - {"FileHeader.TimeDateStamp", Field, 0}, - {"FormatError", Type, 0}, - {"IMAGE_COMDAT_SELECT_ANY", Const, 19}, - {"IMAGE_COMDAT_SELECT_ASSOCIATIVE", Const, 19}, - {"IMAGE_COMDAT_SELECT_EXACT_MATCH", Const, 19}, - {"IMAGE_COMDAT_SELECT_LARGEST", Const, 19}, - {"IMAGE_COMDAT_SELECT_NODUPLICATES", Const, 19}, - {"IMAGE_COMDAT_SELECT_SAME_SIZE", Const, 19}, - {"IMAGE_DIRECTORY_ENTRY_ARCHITECTURE", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_BASERELOC", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_BOUND_IMPORT", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_COM_DESCRIPTOR", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_DEBUG", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_DELAY_IMPORT", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_EXCEPTION", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_EXPORT", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_GLOBALPTR", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_IAT", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_IMPORT", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_RESOURCE", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_SECURITY", Const, 11}, - {"IMAGE_DIRECTORY_ENTRY_TLS", Const, 11}, - {"IMAGE_DLLCHARACTERISTICS_APPCONTAINER", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_DYNAMIC_BASE", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_FORCE_INTEGRITY", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_GUARD_CF", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_HIGH_ENTROPY_VA", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_NO_BIND", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_NO_ISOLATION", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_NO_SEH", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_NX_COMPAT", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE", Const, 15}, - {"IMAGE_DLLCHARACTERISTICS_WDM_DRIVER", Const, 15}, - {"IMAGE_FILE_32BIT_MACHINE", Const, 15}, - {"IMAGE_FILE_AGGRESIVE_WS_TRIM", Const, 15}, - {"IMAGE_FILE_BYTES_REVERSED_HI", Const, 15}, - {"IMAGE_FILE_BYTES_REVERSED_LO", Const, 15}, - {"IMAGE_FILE_DEBUG_STRIPPED", Const, 15}, - {"IMAGE_FILE_DLL", Const, 15}, - {"IMAGE_FILE_EXECUTABLE_IMAGE", Const, 15}, - {"IMAGE_FILE_LARGE_ADDRESS_AWARE", Const, 15}, - {"IMAGE_FILE_LINE_NUMS_STRIPPED", Const, 15}, - {"IMAGE_FILE_LOCAL_SYMS_STRIPPED", Const, 15}, - {"IMAGE_FILE_MACHINE_AM33", Const, 0}, - {"IMAGE_FILE_MACHINE_AMD64", Const, 0}, - {"IMAGE_FILE_MACHINE_ARM", Const, 0}, - {"IMAGE_FILE_MACHINE_ARM64", Const, 11}, - {"IMAGE_FILE_MACHINE_ARMNT", Const, 12}, - {"IMAGE_FILE_MACHINE_EBC", Const, 0}, - {"IMAGE_FILE_MACHINE_I386", Const, 0}, - {"IMAGE_FILE_MACHINE_IA64", Const, 0}, - {"IMAGE_FILE_MACHINE_LOONGARCH32", Const, 19}, - {"IMAGE_FILE_MACHINE_LOONGARCH64", Const, 19}, - {"IMAGE_FILE_MACHINE_M32R", Const, 0}, - {"IMAGE_FILE_MACHINE_MIPS16", Const, 0}, - {"IMAGE_FILE_MACHINE_MIPSFPU", Const, 0}, - {"IMAGE_FILE_MACHINE_MIPSFPU16", Const, 0}, - {"IMAGE_FILE_MACHINE_POWERPC", Const, 0}, - {"IMAGE_FILE_MACHINE_POWERPCFP", Const, 0}, - {"IMAGE_FILE_MACHINE_R4000", Const, 0}, - {"IMAGE_FILE_MACHINE_RISCV128", Const, 20}, - {"IMAGE_FILE_MACHINE_RISCV32", Const, 20}, - {"IMAGE_FILE_MACHINE_RISCV64", Const, 20}, - {"IMAGE_FILE_MACHINE_SH3", Const, 0}, - {"IMAGE_FILE_MACHINE_SH3DSP", Const, 0}, - {"IMAGE_FILE_MACHINE_SH4", Const, 0}, - {"IMAGE_FILE_MACHINE_SH5", Const, 0}, - {"IMAGE_FILE_MACHINE_THUMB", Const, 0}, - {"IMAGE_FILE_MACHINE_UNKNOWN", Const, 0}, - {"IMAGE_FILE_MACHINE_WCEMIPSV2", Const, 0}, - {"IMAGE_FILE_NET_RUN_FROM_SWAP", Const, 15}, - {"IMAGE_FILE_RELOCS_STRIPPED", Const, 15}, - {"IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP", Const, 15}, - {"IMAGE_FILE_SYSTEM", Const, 15}, - {"IMAGE_FILE_UP_SYSTEM_ONLY", Const, 15}, - {"IMAGE_SCN_CNT_CODE", Const, 19}, - {"IMAGE_SCN_CNT_INITIALIZED_DATA", Const, 19}, - {"IMAGE_SCN_CNT_UNINITIALIZED_DATA", Const, 19}, - {"IMAGE_SCN_LNK_COMDAT", Const, 19}, - {"IMAGE_SCN_MEM_DISCARDABLE", Const, 19}, - {"IMAGE_SCN_MEM_EXECUTE", Const, 19}, - {"IMAGE_SCN_MEM_READ", Const, 19}, - {"IMAGE_SCN_MEM_WRITE", Const, 19}, - {"IMAGE_SUBSYSTEM_EFI_APPLICATION", Const, 15}, - {"IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER", Const, 15}, - {"IMAGE_SUBSYSTEM_EFI_ROM", Const, 15}, - {"IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER", Const, 15}, - {"IMAGE_SUBSYSTEM_NATIVE", Const, 15}, - {"IMAGE_SUBSYSTEM_NATIVE_WINDOWS", Const, 15}, - {"IMAGE_SUBSYSTEM_OS2_CUI", Const, 15}, - {"IMAGE_SUBSYSTEM_POSIX_CUI", Const, 15}, - {"IMAGE_SUBSYSTEM_UNKNOWN", Const, 15}, - {"IMAGE_SUBSYSTEM_WINDOWS_BOOT_APPLICATION", Const, 15}, - {"IMAGE_SUBSYSTEM_WINDOWS_CE_GUI", Const, 15}, - {"IMAGE_SUBSYSTEM_WINDOWS_CUI", Const, 15}, - {"IMAGE_SUBSYSTEM_WINDOWS_GUI", Const, 15}, - {"IMAGE_SUBSYSTEM_XBOX", Const, 15}, - {"ImportDirectory", Type, 0}, - {"ImportDirectory.FirstThunk", Field, 0}, - {"ImportDirectory.ForwarderChain", Field, 0}, - {"ImportDirectory.Name", Field, 0}, - {"ImportDirectory.OriginalFirstThunk", Field, 0}, - {"ImportDirectory.TimeDateStamp", Field, 0}, - {"NewFile", Func, 0}, - {"Open", Func, 0}, - {"OptionalHeader32", Type, 3}, - {"OptionalHeader32.AddressOfEntryPoint", Field, 3}, - {"OptionalHeader32.BaseOfCode", Field, 3}, - {"OptionalHeader32.BaseOfData", Field, 3}, - {"OptionalHeader32.CheckSum", Field, 3}, - {"OptionalHeader32.DataDirectory", Field, 3}, - {"OptionalHeader32.DllCharacteristics", Field, 3}, - {"OptionalHeader32.FileAlignment", Field, 3}, - {"OptionalHeader32.ImageBase", Field, 3}, - {"OptionalHeader32.LoaderFlags", Field, 3}, - {"OptionalHeader32.Magic", Field, 3}, - {"OptionalHeader32.MajorImageVersion", Field, 3}, - {"OptionalHeader32.MajorLinkerVersion", Field, 3}, - {"OptionalHeader32.MajorOperatingSystemVersion", Field, 3}, - {"OptionalHeader32.MajorSubsystemVersion", Field, 3}, - {"OptionalHeader32.MinorImageVersion", Field, 3}, - {"OptionalHeader32.MinorLinkerVersion", Field, 3}, - {"OptionalHeader32.MinorOperatingSystemVersion", Field, 3}, - {"OptionalHeader32.MinorSubsystemVersion", Field, 3}, - {"OptionalHeader32.NumberOfRvaAndSizes", Field, 3}, - {"OptionalHeader32.SectionAlignment", Field, 3}, - {"OptionalHeader32.SizeOfCode", Field, 3}, - {"OptionalHeader32.SizeOfHeaders", Field, 3}, - {"OptionalHeader32.SizeOfHeapCommit", Field, 3}, - {"OptionalHeader32.SizeOfHeapReserve", Field, 3}, - {"OptionalHeader32.SizeOfImage", Field, 3}, - {"OptionalHeader32.SizeOfInitializedData", Field, 3}, - {"OptionalHeader32.SizeOfStackCommit", Field, 3}, - {"OptionalHeader32.SizeOfStackReserve", Field, 3}, - {"OptionalHeader32.SizeOfUninitializedData", Field, 3}, - {"OptionalHeader32.Subsystem", Field, 3}, - {"OptionalHeader32.Win32VersionValue", Field, 3}, - {"OptionalHeader64", Type, 3}, - {"OptionalHeader64.AddressOfEntryPoint", Field, 3}, - {"OptionalHeader64.BaseOfCode", Field, 3}, - {"OptionalHeader64.CheckSum", Field, 3}, - {"OptionalHeader64.DataDirectory", Field, 3}, - {"OptionalHeader64.DllCharacteristics", Field, 3}, - {"OptionalHeader64.FileAlignment", Field, 3}, - {"OptionalHeader64.ImageBase", Field, 3}, - {"OptionalHeader64.LoaderFlags", Field, 3}, - {"OptionalHeader64.Magic", Field, 3}, - {"OptionalHeader64.MajorImageVersion", Field, 3}, - {"OptionalHeader64.MajorLinkerVersion", Field, 3}, - {"OptionalHeader64.MajorOperatingSystemVersion", Field, 3}, - {"OptionalHeader64.MajorSubsystemVersion", Field, 3}, - {"OptionalHeader64.MinorImageVersion", Field, 3}, - {"OptionalHeader64.MinorLinkerVersion", Field, 3}, - {"OptionalHeader64.MinorOperatingSystemVersion", Field, 3}, - {"OptionalHeader64.MinorSubsystemVersion", Field, 3}, - {"OptionalHeader64.NumberOfRvaAndSizes", Field, 3}, - {"OptionalHeader64.SectionAlignment", Field, 3}, - {"OptionalHeader64.SizeOfCode", Field, 3}, - {"OptionalHeader64.SizeOfHeaders", Field, 3}, - {"OptionalHeader64.SizeOfHeapCommit", Field, 3}, - {"OptionalHeader64.SizeOfHeapReserve", Field, 3}, - {"OptionalHeader64.SizeOfImage", Field, 3}, - {"OptionalHeader64.SizeOfInitializedData", Field, 3}, - {"OptionalHeader64.SizeOfStackCommit", Field, 3}, - {"OptionalHeader64.SizeOfStackReserve", Field, 3}, - {"OptionalHeader64.SizeOfUninitializedData", Field, 3}, - {"OptionalHeader64.Subsystem", Field, 3}, - {"OptionalHeader64.Win32VersionValue", Field, 3}, - {"Reloc", Type, 8}, - {"Reloc.SymbolTableIndex", Field, 8}, - {"Reloc.Type", Field, 8}, - {"Reloc.VirtualAddress", Field, 8}, - {"Section", Type, 0}, - {"Section.ReaderAt", Field, 0}, - {"Section.Relocs", Field, 8}, - {"Section.SectionHeader", Field, 0}, - {"SectionHeader", Type, 0}, - {"SectionHeader.Characteristics", Field, 0}, - {"SectionHeader.Name", Field, 0}, - {"SectionHeader.NumberOfLineNumbers", Field, 0}, - {"SectionHeader.NumberOfRelocations", Field, 0}, - {"SectionHeader.Offset", Field, 0}, - {"SectionHeader.PointerToLineNumbers", Field, 0}, - {"SectionHeader.PointerToRelocations", Field, 0}, - {"SectionHeader.Size", Field, 0}, - {"SectionHeader.VirtualAddress", Field, 0}, - {"SectionHeader.VirtualSize", Field, 0}, - {"SectionHeader32", Type, 0}, - {"SectionHeader32.Characteristics", Field, 0}, - {"SectionHeader32.Name", Field, 0}, - {"SectionHeader32.NumberOfLineNumbers", Field, 0}, - {"SectionHeader32.NumberOfRelocations", Field, 0}, - {"SectionHeader32.PointerToLineNumbers", Field, 0}, - {"SectionHeader32.PointerToRawData", Field, 0}, - {"SectionHeader32.PointerToRelocations", Field, 0}, - {"SectionHeader32.SizeOfRawData", Field, 0}, - {"SectionHeader32.VirtualAddress", Field, 0}, - {"SectionHeader32.VirtualSize", Field, 0}, - {"StringTable", Type, 8}, - {"Symbol", Type, 1}, - {"Symbol.Name", Field, 1}, - {"Symbol.SectionNumber", Field, 1}, - {"Symbol.StorageClass", Field, 1}, - {"Symbol.Type", Field, 1}, - {"Symbol.Value", Field, 1}, + {"(*COFFSymbol).FullName", Method, 8, ""}, + {"(*File).COFFSymbolReadSectionDefAux", Method, 19, ""}, + {"(*File).Close", Method, 0, ""}, + {"(*File).DWARF", Method, 0, ""}, + {"(*File).ImportedLibraries", Method, 0, ""}, + {"(*File).ImportedSymbols", Method, 0, ""}, + {"(*File).Section", Method, 0, ""}, + {"(*FormatError).Error", Method, 0, ""}, + {"(*Section).Data", Method, 0, ""}, + {"(*Section).Open", Method, 0, ""}, + {"(Section).ReadAt", Method, 0, ""}, + {"(StringTable).String", Method, 8, ""}, + {"COFFSymbol", Type, 1, ""}, + {"COFFSymbol.Name", Field, 1, ""}, + {"COFFSymbol.NumberOfAuxSymbols", Field, 1, ""}, + {"COFFSymbol.SectionNumber", Field, 1, ""}, + {"COFFSymbol.StorageClass", Field, 1, ""}, + {"COFFSymbol.Type", Field, 1, ""}, + {"COFFSymbol.Value", Field, 1, ""}, + {"COFFSymbolAuxFormat5", Type, 19, ""}, + {"COFFSymbolAuxFormat5.Checksum", Field, 19, ""}, + {"COFFSymbolAuxFormat5.NumLineNumbers", Field, 19, ""}, + {"COFFSymbolAuxFormat5.NumRelocs", Field, 19, ""}, + {"COFFSymbolAuxFormat5.SecNum", Field, 19, ""}, + {"COFFSymbolAuxFormat5.Selection", Field, 19, ""}, + {"COFFSymbolAuxFormat5.Size", Field, 19, ""}, + {"COFFSymbolSize", Const, 1, ""}, + {"DataDirectory", Type, 3, ""}, + {"DataDirectory.Size", Field, 3, ""}, + {"DataDirectory.VirtualAddress", Field, 3, ""}, + {"File", Type, 0, ""}, + {"File.COFFSymbols", Field, 8, ""}, + {"File.FileHeader", Field, 0, ""}, + {"File.OptionalHeader", Field, 3, ""}, + {"File.Sections", Field, 0, ""}, + {"File.StringTable", Field, 8, ""}, + {"File.Symbols", Field, 1, ""}, + {"FileHeader", Type, 0, ""}, + {"FileHeader.Characteristics", Field, 0, ""}, + {"FileHeader.Machine", Field, 0, ""}, + {"FileHeader.NumberOfSections", Field, 0, ""}, + {"FileHeader.NumberOfSymbols", Field, 0, ""}, + {"FileHeader.PointerToSymbolTable", Field, 0, ""}, + {"FileHeader.SizeOfOptionalHeader", Field, 0, ""}, + {"FileHeader.TimeDateStamp", Field, 0, ""}, + {"FormatError", Type, 0, ""}, + {"IMAGE_COMDAT_SELECT_ANY", Const, 19, ""}, + {"IMAGE_COMDAT_SELECT_ASSOCIATIVE", Const, 19, ""}, + {"IMAGE_COMDAT_SELECT_EXACT_MATCH", Const, 19, ""}, + {"IMAGE_COMDAT_SELECT_LARGEST", Const, 19, ""}, + {"IMAGE_COMDAT_SELECT_NODUPLICATES", Const, 19, ""}, + {"IMAGE_COMDAT_SELECT_SAME_SIZE", Const, 19, ""}, + {"IMAGE_DIRECTORY_ENTRY_ARCHITECTURE", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_BASERELOC", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_BOUND_IMPORT", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_COM_DESCRIPTOR", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_DEBUG", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_DELAY_IMPORT", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_EXCEPTION", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_EXPORT", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_GLOBALPTR", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_IAT", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_IMPORT", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_RESOURCE", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_SECURITY", Const, 11, ""}, + {"IMAGE_DIRECTORY_ENTRY_TLS", Const, 11, ""}, + {"IMAGE_DLLCHARACTERISTICS_APPCONTAINER", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_DYNAMIC_BASE", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_FORCE_INTEGRITY", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_GUARD_CF", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_HIGH_ENTROPY_VA", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_NO_BIND", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_NO_ISOLATION", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_NO_SEH", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_NX_COMPAT", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE", Const, 15, ""}, + {"IMAGE_DLLCHARACTERISTICS_WDM_DRIVER", Const, 15, ""}, + {"IMAGE_FILE_32BIT_MACHINE", Const, 15, ""}, + {"IMAGE_FILE_AGGRESIVE_WS_TRIM", Const, 15, ""}, + {"IMAGE_FILE_BYTES_REVERSED_HI", Const, 15, ""}, + {"IMAGE_FILE_BYTES_REVERSED_LO", Const, 15, ""}, + {"IMAGE_FILE_DEBUG_STRIPPED", Const, 15, ""}, + {"IMAGE_FILE_DLL", Const, 15, ""}, + {"IMAGE_FILE_EXECUTABLE_IMAGE", Const, 15, ""}, + {"IMAGE_FILE_LARGE_ADDRESS_AWARE", Const, 15, ""}, + {"IMAGE_FILE_LINE_NUMS_STRIPPED", Const, 15, ""}, + {"IMAGE_FILE_LOCAL_SYMS_STRIPPED", Const, 15, ""}, + {"IMAGE_FILE_MACHINE_AM33", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_AMD64", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_ARM", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_ARM64", Const, 11, ""}, + {"IMAGE_FILE_MACHINE_ARMNT", Const, 12, ""}, + {"IMAGE_FILE_MACHINE_EBC", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_I386", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_IA64", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_LOONGARCH32", Const, 19, ""}, + {"IMAGE_FILE_MACHINE_LOONGARCH64", Const, 19, ""}, + {"IMAGE_FILE_MACHINE_M32R", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_MIPS16", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_MIPSFPU", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_MIPSFPU16", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_POWERPC", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_POWERPCFP", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_R4000", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_RISCV128", Const, 20, ""}, + {"IMAGE_FILE_MACHINE_RISCV32", Const, 20, ""}, + {"IMAGE_FILE_MACHINE_RISCV64", Const, 20, ""}, + {"IMAGE_FILE_MACHINE_SH3", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_SH3DSP", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_SH4", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_SH5", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_THUMB", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_UNKNOWN", Const, 0, ""}, + {"IMAGE_FILE_MACHINE_WCEMIPSV2", Const, 0, ""}, + {"IMAGE_FILE_NET_RUN_FROM_SWAP", Const, 15, ""}, + {"IMAGE_FILE_RELOCS_STRIPPED", Const, 15, ""}, + {"IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP", Const, 15, ""}, + {"IMAGE_FILE_SYSTEM", Const, 15, ""}, + {"IMAGE_FILE_UP_SYSTEM_ONLY", Const, 15, ""}, + {"IMAGE_SCN_CNT_CODE", Const, 19, ""}, + {"IMAGE_SCN_CNT_INITIALIZED_DATA", Const, 19, ""}, + {"IMAGE_SCN_CNT_UNINITIALIZED_DATA", Const, 19, ""}, + {"IMAGE_SCN_LNK_COMDAT", Const, 19, ""}, + {"IMAGE_SCN_MEM_DISCARDABLE", Const, 19, ""}, + {"IMAGE_SCN_MEM_EXECUTE", Const, 19, ""}, + {"IMAGE_SCN_MEM_READ", Const, 19, ""}, + {"IMAGE_SCN_MEM_WRITE", Const, 19, ""}, + {"IMAGE_SUBSYSTEM_EFI_APPLICATION", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_EFI_ROM", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_NATIVE", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_NATIVE_WINDOWS", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_OS2_CUI", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_POSIX_CUI", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_UNKNOWN", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_WINDOWS_BOOT_APPLICATION", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_WINDOWS_CE_GUI", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_WINDOWS_CUI", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_WINDOWS_GUI", Const, 15, ""}, + {"IMAGE_SUBSYSTEM_XBOX", Const, 15, ""}, + {"ImportDirectory", Type, 0, ""}, + {"ImportDirectory.FirstThunk", Field, 0, ""}, + {"ImportDirectory.ForwarderChain", Field, 0, ""}, + {"ImportDirectory.Name", Field, 0, ""}, + {"ImportDirectory.OriginalFirstThunk", Field, 0, ""}, + {"ImportDirectory.TimeDateStamp", Field, 0, ""}, + {"NewFile", Func, 0, "func(r io.ReaderAt) (*File, error)"}, + {"Open", Func, 0, "func(name string) (*File, error)"}, + {"OptionalHeader32", Type, 3, ""}, + {"OptionalHeader32.AddressOfEntryPoint", Field, 3, ""}, + {"OptionalHeader32.BaseOfCode", Field, 3, ""}, + {"OptionalHeader32.BaseOfData", Field, 3, ""}, + {"OptionalHeader32.CheckSum", Field, 3, ""}, + {"OptionalHeader32.DataDirectory", Field, 3, ""}, + {"OptionalHeader32.DllCharacteristics", Field, 3, ""}, + {"OptionalHeader32.FileAlignment", Field, 3, ""}, + {"OptionalHeader32.ImageBase", Field, 3, ""}, + {"OptionalHeader32.LoaderFlags", Field, 3, ""}, + {"OptionalHeader32.Magic", Field, 3, ""}, + {"OptionalHeader32.MajorImageVersion", Field, 3, ""}, + {"OptionalHeader32.MajorLinkerVersion", Field, 3, ""}, + {"OptionalHeader32.MajorOperatingSystemVersion", Field, 3, ""}, + {"OptionalHeader32.MajorSubsystemVersion", Field, 3, ""}, + {"OptionalHeader32.MinorImageVersion", Field, 3, ""}, + {"OptionalHeader32.MinorLinkerVersion", Field, 3, ""}, + {"OptionalHeader32.MinorOperatingSystemVersion", Field, 3, ""}, + {"OptionalHeader32.MinorSubsystemVersion", Field, 3, ""}, + {"OptionalHeader32.NumberOfRvaAndSizes", Field, 3, ""}, + {"OptionalHeader32.SectionAlignment", Field, 3, ""}, + {"OptionalHeader32.SizeOfCode", Field, 3, ""}, + {"OptionalHeader32.SizeOfHeaders", Field, 3, ""}, + {"OptionalHeader32.SizeOfHeapCommit", Field, 3, ""}, + {"OptionalHeader32.SizeOfHeapReserve", Field, 3, ""}, + {"OptionalHeader32.SizeOfImage", Field, 3, ""}, + {"OptionalHeader32.SizeOfInitializedData", Field, 3, ""}, + {"OptionalHeader32.SizeOfStackCommit", Field, 3, ""}, + {"OptionalHeader32.SizeOfStackReserve", Field, 3, ""}, + {"OptionalHeader32.SizeOfUninitializedData", Field, 3, ""}, + {"OptionalHeader32.Subsystem", Field, 3, ""}, + {"OptionalHeader32.Win32VersionValue", Field, 3, ""}, + {"OptionalHeader64", Type, 3, ""}, + {"OptionalHeader64.AddressOfEntryPoint", Field, 3, ""}, + {"OptionalHeader64.BaseOfCode", Field, 3, ""}, + {"OptionalHeader64.CheckSum", Field, 3, ""}, + {"OptionalHeader64.DataDirectory", Field, 3, ""}, + {"OptionalHeader64.DllCharacteristics", Field, 3, ""}, + {"OptionalHeader64.FileAlignment", Field, 3, ""}, + {"OptionalHeader64.ImageBase", Field, 3, ""}, + {"OptionalHeader64.LoaderFlags", Field, 3, ""}, + {"OptionalHeader64.Magic", Field, 3, ""}, + {"OptionalHeader64.MajorImageVersion", Field, 3, ""}, + {"OptionalHeader64.MajorLinkerVersion", Field, 3, ""}, + {"OptionalHeader64.MajorOperatingSystemVersion", Field, 3, ""}, + {"OptionalHeader64.MajorSubsystemVersion", Field, 3, ""}, + {"OptionalHeader64.MinorImageVersion", Field, 3, ""}, + {"OptionalHeader64.MinorLinkerVersion", Field, 3, ""}, + {"OptionalHeader64.MinorOperatingSystemVersion", Field, 3, ""}, + {"OptionalHeader64.MinorSubsystemVersion", Field, 3, ""}, + {"OptionalHeader64.NumberOfRvaAndSizes", Field, 3, ""}, + {"OptionalHeader64.SectionAlignment", Field, 3, ""}, + {"OptionalHeader64.SizeOfCode", Field, 3, ""}, + {"OptionalHeader64.SizeOfHeaders", Field, 3, ""}, + {"OptionalHeader64.SizeOfHeapCommit", Field, 3, ""}, + {"OptionalHeader64.SizeOfHeapReserve", Field, 3, ""}, + {"OptionalHeader64.SizeOfImage", Field, 3, ""}, + {"OptionalHeader64.SizeOfInitializedData", Field, 3, ""}, + {"OptionalHeader64.SizeOfStackCommit", Field, 3, ""}, + {"OptionalHeader64.SizeOfStackReserve", Field, 3, ""}, + {"OptionalHeader64.SizeOfUninitializedData", Field, 3, ""}, + {"OptionalHeader64.Subsystem", Field, 3, ""}, + {"OptionalHeader64.Win32VersionValue", Field, 3, ""}, + {"Reloc", Type, 8, ""}, + {"Reloc.SymbolTableIndex", Field, 8, ""}, + {"Reloc.Type", Field, 8, ""}, + {"Reloc.VirtualAddress", Field, 8, ""}, + {"Section", Type, 0, ""}, + {"Section.ReaderAt", Field, 0, ""}, + {"Section.Relocs", Field, 8, ""}, + {"Section.SectionHeader", Field, 0, ""}, + {"SectionHeader", Type, 0, ""}, + {"SectionHeader.Characteristics", Field, 0, ""}, + {"SectionHeader.Name", Field, 0, ""}, + {"SectionHeader.NumberOfLineNumbers", Field, 0, ""}, + {"SectionHeader.NumberOfRelocations", Field, 0, ""}, + {"SectionHeader.Offset", Field, 0, ""}, + {"SectionHeader.PointerToLineNumbers", Field, 0, ""}, + {"SectionHeader.PointerToRelocations", Field, 0, ""}, + {"SectionHeader.Size", Field, 0, ""}, + {"SectionHeader.VirtualAddress", Field, 0, ""}, + {"SectionHeader.VirtualSize", Field, 0, ""}, + {"SectionHeader32", Type, 0, ""}, + {"SectionHeader32.Characteristics", Field, 0, ""}, + {"SectionHeader32.Name", Field, 0, ""}, + {"SectionHeader32.NumberOfLineNumbers", Field, 0, ""}, + {"SectionHeader32.NumberOfRelocations", Field, 0, ""}, + {"SectionHeader32.PointerToLineNumbers", Field, 0, ""}, + {"SectionHeader32.PointerToRawData", Field, 0, ""}, + {"SectionHeader32.PointerToRelocations", Field, 0, ""}, + {"SectionHeader32.SizeOfRawData", Field, 0, ""}, + {"SectionHeader32.VirtualAddress", Field, 0, ""}, + {"SectionHeader32.VirtualSize", Field, 0, ""}, + {"StringTable", Type, 8, ""}, + {"Symbol", Type, 1, ""}, + {"Symbol.Name", Field, 1, ""}, + {"Symbol.SectionNumber", Field, 1, ""}, + {"Symbol.StorageClass", Field, 1, ""}, + {"Symbol.Type", Field, 1, ""}, + {"Symbol.Value", Field, 1, ""}, }, "debug/plan9obj": { - {"(*File).Close", Method, 3}, - {"(*File).Section", Method, 3}, - {"(*File).Symbols", Method, 3}, - {"(*Section).Data", Method, 3}, - {"(*Section).Open", Method, 3}, - {"(Section).ReadAt", Method, 3}, - {"ErrNoSymbols", Var, 18}, - {"File", Type, 3}, - {"File.FileHeader", Field, 3}, - {"File.Sections", Field, 3}, - {"FileHeader", Type, 3}, - {"FileHeader.Bss", Field, 3}, - {"FileHeader.Entry", Field, 3}, - {"FileHeader.HdrSize", Field, 4}, - {"FileHeader.LoadAddress", Field, 4}, - {"FileHeader.Magic", Field, 3}, - {"FileHeader.PtrSize", Field, 3}, - {"Magic386", Const, 3}, - {"Magic64", Const, 3}, - {"MagicAMD64", Const, 3}, - {"MagicARM", Const, 3}, - {"NewFile", Func, 3}, - {"Open", Func, 3}, - {"Section", Type, 3}, - {"Section.ReaderAt", Field, 3}, - {"Section.SectionHeader", Field, 3}, - {"SectionHeader", Type, 3}, - {"SectionHeader.Name", Field, 3}, - {"SectionHeader.Offset", Field, 3}, - {"SectionHeader.Size", Field, 3}, - {"Sym", Type, 3}, - {"Sym.Name", Field, 3}, - {"Sym.Type", Field, 3}, - {"Sym.Value", Field, 3}, + {"(*File).Close", Method, 3, ""}, + {"(*File).Section", Method, 3, ""}, + {"(*File).Symbols", Method, 3, ""}, + {"(*Section).Data", Method, 3, ""}, + {"(*Section).Open", Method, 3, ""}, + {"(Section).ReadAt", Method, 3, ""}, + {"ErrNoSymbols", Var, 18, ""}, + {"File", Type, 3, ""}, + {"File.FileHeader", Field, 3, ""}, + {"File.Sections", Field, 3, ""}, + {"FileHeader", Type, 3, ""}, + {"FileHeader.Bss", Field, 3, ""}, + {"FileHeader.Entry", Field, 3, ""}, + {"FileHeader.HdrSize", Field, 4, ""}, + {"FileHeader.LoadAddress", Field, 4, ""}, + {"FileHeader.Magic", Field, 3, ""}, + {"FileHeader.PtrSize", Field, 3, ""}, + {"Magic386", Const, 3, ""}, + {"Magic64", Const, 3, ""}, + {"MagicAMD64", Const, 3, ""}, + {"MagicARM", Const, 3, ""}, + {"NewFile", Func, 3, "func(r io.ReaderAt) (*File, error)"}, + {"Open", Func, 3, "func(name string) (*File, error)"}, + {"Section", Type, 3, ""}, + {"Section.ReaderAt", Field, 3, ""}, + {"Section.SectionHeader", Field, 3, ""}, + {"SectionHeader", Type, 3, ""}, + {"SectionHeader.Name", Field, 3, ""}, + {"SectionHeader.Offset", Field, 3, ""}, + {"SectionHeader.Size", Field, 3, ""}, + {"Sym", Type, 3, ""}, + {"Sym.Name", Field, 3, ""}, + {"Sym.Type", Field, 3, ""}, + {"Sym.Value", Field, 3, ""}, }, "embed": { - {"(FS).Open", Method, 16}, - {"(FS).ReadDir", Method, 16}, - {"(FS).ReadFile", Method, 16}, - {"FS", Type, 16}, + {"(FS).Open", Method, 16, ""}, + {"(FS).ReadDir", Method, 16, ""}, + {"(FS).ReadFile", Method, 16, ""}, + {"FS", Type, 16, ""}, }, "encoding": { - {"BinaryAppender", Type, 24}, - {"BinaryMarshaler", Type, 2}, - {"BinaryUnmarshaler", Type, 2}, - {"TextAppender", Type, 24}, - {"TextMarshaler", Type, 2}, - {"TextUnmarshaler", Type, 2}, + {"BinaryAppender", Type, 24, ""}, + {"BinaryMarshaler", Type, 2, ""}, + {"BinaryUnmarshaler", Type, 2, ""}, + {"TextAppender", Type, 24, ""}, + {"TextMarshaler", Type, 2, ""}, + {"TextUnmarshaler", Type, 2, ""}, }, "encoding/ascii85": { - {"(CorruptInputError).Error", Method, 0}, - {"CorruptInputError", Type, 0}, - {"Decode", Func, 0}, - {"Encode", Func, 0}, - {"MaxEncodedLen", Func, 0}, - {"NewDecoder", Func, 0}, - {"NewEncoder", Func, 0}, + {"(CorruptInputError).Error", Method, 0, ""}, + {"CorruptInputError", Type, 0, ""}, + {"Decode", Func, 0, "func(dst []byte, src []byte, flush bool) (ndst int, nsrc int, err error)"}, + {"Encode", Func, 0, "func(dst []byte, src []byte) int"}, + {"MaxEncodedLen", Func, 0, "func(n int) int"}, + {"NewDecoder", Func, 0, "func(r io.Reader) io.Reader"}, + {"NewEncoder", Func, 0, "func(w io.Writer) io.WriteCloser"}, }, "encoding/asn1": { - {"(BitString).At", Method, 0}, - {"(BitString).RightAlign", Method, 0}, - {"(ObjectIdentifier).Equal", Method, 0}, - {"(ObjectIdentifier).String", Method, 3}, - {"(StructuralError).Error", Method, 0}, - {"(SyntaxError).Error", Method, 0}, - {"BitString", Type, 0}, - {"BitString.BitLength", Field, 0}, - {"BitString.Bytes", Field, 0}, - {"ClassApplication", Const, 6}, - {"ClassContextSpecific", Const, 6}, - {"ClassPrivate", Const, 6}, - {"ClassUniversal", Const, 6}, - {"Enumerated", Type, 0}, - {"Flag", Type, 0}, - {"Marshal", Func, 0}, - {"MarshalWithParams", Func, 10}, - {"NullBytes", Var, 9}, - {"NullRawValue", Var, 9}, - {"ObjectIdentifier", Type, 0}, - {"RawContent", Type, 0}, - {"RawValue", Type, 0}, - {"RawValue.Bytes", Field, 0}, - {"RawValue.Class", Field, 0}, - {"RawValue.FullBytes", Field, 0}, - {"RawValue.IsCompound", Field, 0}, - {"RawValue.Tag", Field, 0}, - {"StructuralError", Type, 0}, - {"StructuralError.Msg", Field, 0}, - {"SyntaxError", Type, 0}, - {"SyntaxError.Msg", Field, 0}, - {"TagBMPString", Const, 14}, - {"TagBitString", Const, 6}, - {"TagBoolean", Const, 6}, - {"TagEnum", Const, 6}, - {"TagGeneralString", Const, 6}, - {"TagGeneralizedTime", Const, 6}, - {"TagIA5String", Const, 6}, - {"TagInteger", Const, 6}, - {"TagNull", Const, 9}, - {"TagNumericString", Const, 10}, - {"TagOID", Const, 6}, - {"TagOctetString", Const, 6}, - {"TagPrintableString", Const, 6}, - {"TagSequence", Const, 6}, - {"TagSet", Const, 6}, - {"TagT61String", Const, 6}, - {"TagUTCTime", Const, 6}, - {"TagUTF8String", Const, 6}, - {"Unmarshal", Func, 0}, - {"UnmarshalWithParams", Func, 0}, + {"(BitString).At", Method, 0, ""}, + {"(BitString).RightAlign", Method, 0, ""}, + {"(ObjectIdentifier).Equal", Method, 0, ""}, + {"(ObjectIdentifier).String", Method, 3, ""}, + {"(StructuralError).Error", Method, 0, ""}, + {"(SyntaxError).Error", Method, 0, ""}, + {"BitString", Type, 0, ""}, + {"BitString.BitLength", Field, 0, ""}, + {"BitString.Bytes", Field, 0, ""}, + {"ClassApplication", Const, 6, ""}, + {"ClassContextSpecific", Const, 6, ""}, + {"ClassPrivate", Const, 6, ""}, + {"ClassUniversal", Const, 6, ""}, + {"Enumerated", Type, 0, ""}, + {"Flag", Type, 0, ""}, + {"Marshal", Func, 0, "func(val any) ([]byte, error)"}, + {"MarshalWithParams", Func, 10, "func(val any, params string) ([]byte, error)"}, + {"NullBytes", Var, 9, ""}, + {"NullRawValue", Var, 9, ""}, + {"ObjectIdentifier", Type, 0, ""}, + {"RawContent", Type, 0, ""}, + {"RawValue", Type, 0, ""}, + {"RawValue.Bytes", Field, 0, ""}, + {"RawValue.Class", Field, 0, ""}, + {"RawValue.FullBytes", Field, 0, ""}, + {"RawValue.IsCompound", Field, 0, ""}, + {"RawValue.Tag", Field, 0, ""}, + {"StructuralError", Type, 0, ""}, + {"StructuralError.Msg", Field, 0, ""}, + {"SyntaxError", Type, 0, ""}, + {"SyntaxError.Msg", Field, 0, ""}, + {"TagBMPString", Const, 14, ""}, + {"TagBitString", Const, 6, ""}, + {"TagBoolean", Const, 6, ""}, + {"TagEnum", Const, 6, ""}, + {"TagGeneralString", Const, 6, ""}, + {"TagGeneralizedTime", Const, 6, ""}, + {"TagIA5String", Const, 6, ""}, + {"TagInteger", Const, 6, ""}, + {"TagNull", Const, 9, ""}, + {"TagNumericString", Const, 10, ""}, + {"TagOID", Const, 6, ""}, + {"TagOctetString", Const, 6, ""}, + {"TagPrintableString", Const, 6, ""}, + {"TagSequence", Const, 6, ""}, + {"TagSet", Const, 6, ""}, + {"TagT61String", Const, 6, ""}, + {"TagUTCTime", Const, 6, ""}, + {"TagUTF8String", Const, 6, ""}, + {"Unmarshal", Func, 0, "func(b []byte, val any) (rest []byte, err error)"}, + {"UnmarshalWithParams", Func, 0, "func(b []byte, val any, params string) (rest []byte, err error)"}, }, "encoding/base32": { - {"(*Encoding).AppendDecode", Method, 22}, - {"(*Encoding).AppendEncode", Method, 22}, - {"(*Encoding).Decode", Method, 0}, - {"(*Encoding).DecodeString", Method, 0}, - {"(*Encoding).DecodedLen", Method, 0}, - {"(*Encoding).Encode", Method, 0}, - {"(*Encoding).EncodeToString", Method, 0}, - {"(*Encoding).EncodedLen", Method, 0}, - {"(CorruptInputError).Error", Method, 0}, - {"(Encoding).WithPadding", Method, 9}, - {"CorruptInputError", Type, 0}, - {"Encoding", Type, 0}, - {"HexEncoding", Var, 0}, - {"NewDecoder", Func, 0}, - {"NewEncoder", Func, 0}, - {"NewEncoding", Func, 0}, - {"NoPadding", Const, 9}, - {"StdEncoding", Var, 0}, - {"StdPadding", Const, 9}, + {"(*Encoding).AppendDecode", Method, 22, ""}, + {"(*Encoding).AppendEncode", Method, 22, ""}, + {"(*Encoding).Decode", Method, 0, ""}, + {"(*Encoding).DecodeString", Method, 0, ""}, + {"(*Encoding).DecodedLen", Method, 0, ""}, + {"(*Encoding).Encode", Method, 0, ""}, + {"(*Encoding).EncodeToString", Method, 0, ""}, + {"(*Encoding).EncodedLen", Method, 0, ""}, + {"(CorruptInputError).Error", Method, 0, ""}, + {"(Encoding).WithPadding", Method, 9, ""}, + {"CorruptInputError", Type, 0, ""}, + {"Encoding", Type, 0, ""}, + {"HexEncoding", Var, 0, ""}, + {"NewDecoder", Func, 0, "func(enc *Encoding, r io.Reader) io.Reader"}, + {"NewEncoder", Func, 0, "func(enc *Encoding, w io.Writer) io.WriteCloser"}, + {"NewEncoding", Func, 0, "func(encoder string) *Encoding"}, + {"NoPadding", Const, 9, ""}, + {"StdEncoding", Var, 0, ""}, + {"StdPadding", Const, 9, ""}, }, "encoding/base64": { - {"(*Encoding).AppendDecode", Method, 22}, - {"(*Encoding).AppendEncode", Method, 22}, - {"(*Encoding).Decode", Method, 0}, - {"(*Encoding).DecodeString", Method, 0}, - {"(*Encoding).DecodedLen", Method, 0}, - {"(*Encoding).Encode", Method, 0}, - {"(*Encoding).EncodeToString", Method, 0}, - {"(*Encoding).EncodedLen", Method, 0}, - {"(CorruptInputError).Error", Method, 0}, - {"(Encoding).Strict", Method, 8}, - {"(Encoding).WithPadding", Method, 5}, - {"CorruptInputError", Type, 0}, - {"Encoding", Type, 0}, - {"NewDecoder", Func, 0}, - {"NewEncoder", Func, 0}, - {"NewEncoding", Func, 0}, - {"NoPadding", Const, 5}, - {"RawStdEncoding", Var, 5}, - {"RawURLEncoding", Var, 5}, - {"StdEncoding", Var, 0}, - {"StdPadding", Const, 5}, - {"URLEncoding", Var, 0}, + {"(*Encoding).AppendDecode", Method, 22, ""}, + {"(*Encoding).AppendEncode", Method, 22, ""}, + {"(*Encoding).Decode", Method, 0, ""}, + {"(*Encoding).DecodeString", Method, 0, ""}, + {"(*Encoding).DecodedLen", Method, 0, ""}, + {"(*Encoding).Encode", Method, 0, ""}, + {"(*Encoding).EncodeToString", Method, 0, ""}, + {"(*Encoding).EncodedLen", Method, 0, ""}, + {"(CorruptInputError).Error", Method, 0, ""}, + {"(Encoding).Strict", Method, 8, ""}, + {"(Encoding).WithPadding", Method, 5, ""}, + {"CorruptInputError", Type, 0, ""}, + {"Encoding", Type, 0, ""}, + {"NewDecoder", Func, 0, "func(enc *Encoding, r io.Reader) io.Reader"}, + {"NewEncoder", Func, 0, "func(enc *Encoding, w io.Writer) io.WriteCloser"}, + {"NewEncoding", Func, 0, "func(encoder string) *Encoding"}, + {"NoPadding", Const, 5, ""}, + {"RawStdEncoding", Var, 5, ""}, + {"RawURLEncoding", Var, 5, ""}, + {"StdEncoding", Var, 0, ""}, + {"StdPadding", Const, 5, ""}, + {"URLEncoding", Var, 0, ""}, }, "encoding/binary": { - {"Append", Func, 23}, - {"AppendByteOrder", Type, 19}, - {"AppendUvarint", Func, 19}, - {"AppendVarint", Func, 19}, - {"BigEndian", Var, 0}, - {"ByteOrder", Type, 0}, - {"Decode", Func, 23}, - {"Encode", Func, 23}, - {"LittleEndian", Var, 0}, - {"MaxVarintLen16", Const, 0}, - {"MaxVarintLen32", Const, 0}, - {"MaxVarintLen64", Const, 0}, - {"NativeEndian", Var, 21}, - {"PutUvarint", Func, 0}, - {"PutVarint", Func, 0}, - {"Read", Func, 0}, - {"ReadUvarint", Func, 0}, - {"ReadVarint", Func, 0}, - {"Size", Func, 0}, - {"Uvarint", Func, 0}, - {"Varint", Func, 0}, - {"Write", Func, 0}, + {"Append", Func, 23, "func(buf []byte, order ByteOrder, data any) ([]byte, error)"}, + {"AppendByteOrder", Type, 19, ""}, + {"AppendUvarint", Func, 19, "func(buf []byte, x uint64) []byte"}, + {"AppendVarint", Func, 19, "func(buf []byte, x int64) []byte"}, + {"BigEndian", Var, 0, ""}, + {"ByteOrder", Type, 0, ""}, + {"Decode", Func, 23, "func(buf []byte, order ByteOrder, data any) (int, error)"}, + {"Encode", Func, 23, "func(buf []byte, order ByteOrder, data any) (int, error)"}, + {"LittleEndian", Var, 0, ""}, + {"MaxVarintLen16", Const, 0, ""}, + {"MaxVarintLen32", Const, 0, ""}, + {"MaxVarintLen64", Const, 0, ""}, + {"NativeEndian", Var, 21, ""}, + {"PutUvarint", Func, 0, "func(buf []byte, x uint64) int"}, + {"PutVarint", Func, 0, "func(buf []byte, x int64) int"}, + {"Read", Func, 0, "func(r io.Reader, order ByteOrder, data any) error"}, + {"ReadUvarint", Func, 0, "func(r io.ByteReader) (uint64, error)"}, + {"ReadVarint", Func, 0, "func(r io.ByteReader) (int64, error)"}, + {"Size", Func, 0, "func(v any) int"}, + {"Uvarint", Func, 0, "func(buf []byte) (uint64, int)"}, + {"Varint", Func, 0, "func(buf []byte) (int64, int)"}, + {"Write", Func, 0, "func(w io.Writer, order ByteOrder, data any) error"}, }, "encoding/csv": { - {"(*ParseError).Error", Method, 0}, - {"(*ParseError).Unwrap", Method, 13}, - {"(*Reader).FieldPos", Method, 17}, - {"(*Reader).InputOffset", Method, 19}, - {"(*Reader).Read", Method, 0}, - {"(*Reader).ReadAll", Method, 0}, - {"(*Writer).Error", Method, 1}, - {"(*Writer).Flush", Method, 0}, - {"(*Writer).Write", Method, 0}, - {"(*Writer).WriteAll", Method, 0}, - {"ErrBareQuote", Var, 0}, - {"ErrFieldCount", Var, 0}, - {"ErrQuote", Var, 0}, - {"ErrTrailingComma", Var, 0}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"ParseError", Type, 0}, - {"ParseError.Column", Field, 0}, - {"ParseError.Err", Field, 0}, - {"ParseError.Line", Field, 0}, - {"ParseError.StartLine", Field, 10}, - {"Reader", Type, 0}, - {"Reader.Comma", Field, 0}, - {"Reader.Comment", Field, 0}, - {"Reader.FieldsPerRecord", Field, 0}, - {"Reader.LazyQuotes", Field, 0}, - {"Reader.ReuseRecord", Field, 9}, - {"Reader.TrailingComma", Field, 0}, - {"Reader.TrimLeadingSpace", Field, 0}, - {"Writer", Type, 0}, - {"Writer.Comma", Field, 0}, - {"Writer.UseCRLF", Field, 0}, + {"(*ParseError).Error", Method, 0, ""}, + {"(*ParseError).Unwrap", Method, 13, ""}, + {"(*Reader).FieldPos", Method, 17, ""}, + {"(*Reader).InputOffset", Method, 19, ""}, + {"(*Reader).Read", Method, 0, ""}, + {"(*Reader).ReadAll", Method, 0, ""}, + {"(*Writer).Error", Method, 1, ""}, + {"(*Writer).Flush", Method, 0, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"(*Writer).WriteAll", Method, 0, ""}, + {"ErrBareQuote", Var, 0, ""}, + {"ErrFieldCount", Var, 0, ""}, + {"ErrQuote", Var, 0, ""}, + {"ErrTrailingComma", Var, 0, ""}, + {"NewReader", Func, 0, "func(r io.Reader) *Reader"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"ParseError", Type, 0, ""}, + {"ParseError.Column", Field, 0, ""}, + {"ParseError.Err", Field, 0, ""}, + {"ParseError.Line", Field, 0, ""}, + {"ParseError.StartLine", Field, 10, ""}, + {"Reader", Type, 0, ""}, + {"Reader.Comma", Field, 0, ""}, + {"Reader.Comment", Field, 0, ""}, + {"Reader.FieldsPerRecord", Field, 0, ""}, + {"Reader.LazyQuotes", Field, 0, ""}, + {"Reader.ReuseRecord", Field, 9, ""}, + {"Reader.TrailingComma", Field, 0, ""}, + {"Reader.TrimLeadingSpace", Field, 0, ""}, + {"Writer", Type, 0, ""}, + {"Writer.Comma", Field, 0, ""}, + {"Writer.UseCRLF", Field, 0, ""}, }, "encoding/gob": { - {"(*Decoder).Decode", Method, 0}, - {"(*Decoder).DecodeValue", Method, 0}, - {"(*Encoder).Encode", Method, 0}, - {"(*Encoder).EncodeValue", Method, 0}, - {"CommonType", Type, 0}, - {"CommonType.Id", Field, 0}, - {"CommonType.Name", Field, 0}, - {"Decoder", Type, 0}, - {"Encoder", Type, 0}, - {"GobDecoder", Type, 0}, - {"GobEncoder", Type, 0}, - {"NewDecoder", Func, 0}, - {"NewEncoder", Func, 0}, - {"Register", Func, 0}, - {"RegisterName", Func, 0}, + {"(*Decoder).Decode", Method, 0, ""}, + {"(*Decoder).DecodeValue", Method, 0, ""}, + {"(*Encoder).Encode", Method, 0, ""}, + {"(*Encoder).EncodeValue", Method, 0, ""}, + {"CommonType", Type, 0, ""}, + {"CommonType.Id", Field, 0, ""}, + {"CommonType.Name", Field, 0, ""}, + {"Decoder", Type, 0, ""}, + {"Encoder", Type, 0, ""}, + {"GobDecoder", Type, 0, ""}, + {"GobEncoder", Type, 0, ""}, + {"NewDecoder", Func, 0, "func(r io.Reader) *Decoder"}, + {"NewEncoder", Func, 0, "func(w io.Writer) *Encoder"}, + {"Register", Func, 0, "func(value any)"}, + {"RegisterName", Func, 0, "func(name string, value any)"}, }, "encoding/hex": { - {"(InvalidByteError).Error", Method, 0}, - {"AppendDecode", Func, 22}, - {"AppendEncode", Func, 22}, - {"Decode", Func, 0}, - {"DecodeString", Func, 0}, - {"DecodedLen", Func, 0}, - {"Dump", Func, 0}, - {"Dumper", Func, 0}, - {"Encode", Func, 0}, - {"EncodeToString", Func, 0}, - {"EncodedLen", Func, 0}, - {"ErrLength", Var, 0}, - {"InvalidByteError", Type, 0}, - {"NewDecoder", Func, 10}, - {"NewEncoder", Func, 10}, + {"(InvalidByteError).Error", Method, 0, ""}, + {"AppendDecode", Func, 22, "func(dst []byte, src []byte) ([]byte, error)"}, + {"AppendEncode", Func, 22, "func(dst []byte, src []byte) []byte"}, + {"Decode", Func, 0, "func(dst []byte, src []byte) (int, error)"}, + {"DecodeString", Func, 0, "func(s string) ([]byte, error)"}, + {"DecodedLen", Func, 0, "func(x int) int"}, + {"Dump", Func, 0, "func(data []byte) string"}, + {"Dumper", Func, 0, "func(w io.Writer) io.WriteCloser"}, + {"Encode", Func, 0, "func(dst []byte, src []byte) int"}, + {"EncodeToString", Func, 0, "func(src []byte) string"}, + {"EncodedLen", Func, 0, "func(n int) int"}, + {"ErrLength", Var, 0, ""}, + {"InvalidByteError", Type, 0, ""}, + {"NewDecoder", Func, 10, "func(r io.Reader) io.Reader"}, + {"NewEncoder", Func, 10, "func(w io.Writer) io.Writer"}, }, "encoding/json": { - {"(*Decoder).Buffered", Method, 1}, - {"(*Decoder).Decode", Method, 0}, - {"(*Decoder).DisallowUnknownFields", Method, 10}, - {"(*Decoder).InputOffset", Method, 14}, - {"(*Decoder).More", Method, 5}, - {"(*Decoder).Token", Method, 5}, - {"(*Decoder).UseNumber", Method, 1}, - {"(*Encoder).Encode", Method, 0}, - {"(*Encoder).SetEscapeHTML", Method, 7}, - {"(*Encoder).SetIndent", Method, 7}, - {"(*InvalidUTF8Error).Error", Method, 0}, - {"(*InvalidUnmarshalError).Error", Method, 0}, - {"(*MarshalerError).Error", Method, 0}, - {"(*MarshalerError).Unwrap", Method, 13}, - {"(*RawMessage).MarshalJSON", Method, 0}, - {"(*RawMessage).UnmarshalJSON", Method, 0}, - {"(*SyntaxError).Error", Method, 0}, - {"(*UnmarshalFieldError).Error", Method, 0}, - {"(*UnmarshalTypeError).Error", Method, 0}, - {"(*UnsupportedTypeError).Error", Method, 0}, - {"(*UnsupportedValueError).Error", Method, 0}, - {"(Delim).String", Method, 5}, - {"(Number).Float64", Method, 1}, - {"(Number).Int64", Method, 1}, - {"(Number).String", Method, 1}, - {"(RawMessage).MarshalJSON", Method, 8}, - {"Compact", Func, 0}, - {"Decoder", Type, 0}, - {"Delim", Type, 5}, - {"Encoder", Type, 0}, - {"HTMLEscape", Func, 0}, - {"Indent", Func, 0}, - {"InvalidUTF8Error", Type, 0}, - {"InvalidUTF8Error.S", Field, 0}, - {"InvalidUnmarshalError", Type, 0}, - {"InvalidUnmarshalError.Type", Field, 0}, - {"Marshal", Func, 0}, - {"MarshalIndent", Func, 0}, - {"Marshaler", Type, 0}, - {"MarshalerError", Type, 0}, - {"MarshalerError.Err", Field, 0}, - {"MarshalerError.Type", Field, 0}, - {"NewDecoder", Func, 0}, - {"NewEncoder", Func, 0}, - {"Number", Type, 1}, - {"RawMessage", Type, 0}, - {"SyntaxError", Type, 0}, - {"SyntaxError.Offset", Field, 0}, - {"Token", Type, 5}, - {"Unmarshal", Func, 0}, - {"UnmarshalFieldError", Type, 0}, - {"UnmarshalFieldError.Field", Field, 0}, - {"UnmarshalFieldError.Key", Field, 0}, - {"UnmarshalFieldError.Type", Field, 0}, - {"UnmarshalTypeError", Type, 0}, - {"UnmarshalTypeError.Field", Field, 8}, - {"UnmarshalTypeError.Offset", Field, 5}, - {"UnmarshalTypeError.Struct", Field, 8}, - {"UnmarshalTypeError.Type", Field, 0}, - {"UnmarshalTypeError.Value", Field, 0}, - {"Unmarshaler", Type, 0}, - {"UnsupportedTypeError", Type, 0}, - {"UnsupportedTypeError.Type", Field, 0}, - {"UnsupportedValueError", Type, 0}, - {"UnsupportedValueError.Str", Field, 0}, - {"UnsupportedValueError.Value", Field, 0}, - {"Valid", Func, 9}, + {"(*Decoder).Buffered", Method, 1, ""}, + {"(*Decoder).Decode", Method, 0, ""}, + {"(*Decoder).DisallowUnknownFields", Method, 10, ""}, + {"(*Decoder).InputOffset", Method, 14, ""}, + {"(*Decoder).More", Method, 5, ""}, + {"(*Decoder).Token", Method, 5, ""}, + {"(*Decoder).UseNumber", Method, 1, ""}, + {"(*Encoder).Encode", Method, 0, ""}, + {"(*Encoder).SetEscapeHTML", Method, 7, ""}, + {"(*Encoder).SetIndent", Method, 7, ""}, + {"(*InvalidUTF8Error).Error", Method, 0, ""}, + {"(*InvalidUnmarshalError).Error", Method, 0, ""}, + {"(*MarshalerError).Error", Method, 0, ""}, + {"(*MarshalerError).Unwrap", Method, 13, ""}, + {"(*RawMessage).MarshalJSON", Method, 0, ""}, + {"(*RawMessage).UnmarshalJSON", Method, 0, ""}, + {"(*SyntaxError).Error", Method, 0, ""}, + {"(*UnmarshalFieldError).Error", Method, 0, ""}, + {"(*UnmarshalTypeError).Error", Method, 0, ""}, + {"(*UnsupportedTypeError).Error", Method, 0, ""}, + {"(*UnsupportedValueError).Error", Method, 0, ""}, + {"(Delim).String", Method, 5, ""}, + {"(Number).Float64", Method, 1, ""}, + {"(Number).Int64", Method, 1, ""}, + {"(Number).String", Method, 1, ""}, + {"(RawMessage).MarshalJSON", Method, 8, ""}, + {"Compact", Func, 0, "func(dst *bytes.Buffer, src []byte) error"}, + {"Decoder", Type, 0, ""}, + {"Delim", Type, 5, ""}, + {"Encoder", Type, 0, ""}, + {"HTMLEscape", Func, 0, "func(dst *bytes.Buffer, src []byte)"}, + {"Indent", Func, 0, "func(dst *bytes.Buffer, src []byte, prefix string, indent string) error"}, + {"InvalidUTF8Error", Type, 0, ""}, + {"InvalidUTF8Error.S", Field, 0, ""}, + {"InvalidUnmarshalError", Type, 0, ""}, + {"InvalidUnmarshalError.Type", Field, 0, ""}, + {"Marshal", Func, 0, "func(v any) ([]byte, error)"}, + {"MarshalIndent", Func, 0, "func(v any, prefix string, indent string) ([]byte, error)"}, + {"Marshaler", Type, 0, ""}, + {"MarshalerError", Type, 0, ""}, + {"MarshalerError.Err", Field, 0, ""}, + {"MarshalerError.Type", Field, 0, ""}, + {"NewDecoder", Func, 0, "func(r io.Reader) *Decoder"}, + {"NewEncoder", Func, 0, "func(w io.Writer) *Encoder"}, + {"Number", Type, 1, ""}, + {"RawMessage", Type, 0, ""}, + {"SyntaxError", Type, 0, ""}, + {"SyntaxError.Offset", Field, 0, ""}, + {"Token", Type, 5, ""}, + {"Unmarshal", Func, 0, "func(data []byte, v any) error"}, + {"UnmarshalFieldError", Type, 0, ""}, + {"UnmarshalFieldError.Field", Field, 0, ""}, + {"UnmarshalFieldError.Key", Field, 0, ""}, + {"UnmarshalFieldError.Type", Field, 0, ""}, + {"UnmarshalTypeError", Type, 0, ""}, + {"UnmarshalTypeError.Field", Field, 8, ""}, + {"UnmarshalTypeError.Offset", Field, 5, ""}, + {"UnmarshalTypeError.Struct", Field, 8, ""}, + {"UnmarshalTypeError.Type", Field, 0, ""}, + {"UnmarshalTypeError.Value", Field, 0, ""}, + {"Unmarshaler", Type, 0, ""}, + {"UnsupportedTypeError", Type, 0, ""}, + {"UnsupportedTypeError.Type", Field, 0, ""}, + {"UnsupportedValueError", Type, 0, ""}, + {"UnsupportedValueError.Str", Field, 0, ""}, + {"UnsupportedValueError.Value", Field, 0, ""}, + {"Valid", Func, 9, "func(data []byte) bool"}, }, "encoding/pem": { - {"Block", Type, 0}, - {"Block.Bytes", Field, 0}, - {"Block.Headers", Field, 0}, - {"Block.Type", Field, 0}, - {"Decode", Func, 0}, - {"Encode", Func, 0}, - {"EncodeToMemory", Func, 0}, + {"Block", Type, 0, ""}, + {"Block.Bytes", Field, 0, ""}, + {"Block.Headers", Field, 0, ""}, + {"Block.Type", Field, 0, ""}, + {"Decode", Func, 0, "func(data []byte) (p *Block, rest []byte)"}, + {"Encode", Func, 0, "func(out io.Writer, b *Block) error"}, + {"EncodeToMemory", Func, 0, "func(b *Block) []byte"}, }, "encoding/xml": { - {"(*Decoder).Decode", Method, 0}, - {"(*Decoder).DecodeElement", Method, 0}, - {"(*Decoder).InputOffset", Method, 4}, - {"(*Decoder).InputPos", Method, 19}, - {"(*Decoder).RawToken", Method, 0}, - {"(*Decoder).Skip", Method, 0}, - {"(*Decoder).Token", Method, 0}, - {"(*Encoder).Close", Method, 20}, - {"(*Encoder).Encode", Method, 0}, - {"(*Encoder).EncodeElement", Method, 2}, - {"(*Encoder).EncodeToken", Method, 2}, - {"(*Encoder).Flush", Method, 2}, - {"(*Encoder).Indent", Method, 1}, - {"(*SyntaxError).Error", Method, 0}, - {"(*TagPathError).Error", Method, 0}, - {"(*UnsupportedTypeError).Error", Method, 0}, - {"(CharData).Copy", Method, 0}, - {"(Comment).Copy", Method, 0}, - {"(Directive).Copy", Method, 0}, - {"(ProcInst).Copy", Method, 0}, - {"(StartElement).Copy", Method, 0}, - {"(StartElement).End", Method, 2}, - {"(UnmarshalError).Error", Method, 0}, - {"Attr", Type, 0}, - {"Attr.Name", Field, 0}, - {"Attr.Value", Field, 0}, - {"CharData", Type, 0}, - {"Comment", Type, 0}, - {"CopyToken", Func, 0}, - {"Decoder", Type, 0}, - {"Decoder.AutoClose", Field, 0}, - {"Decoder.CharsetReader", Field, 0}, - {"Decoder.DefaultSpace", Field, 1}, - {"Decoder.Entity", Field, 0}, - {"Decoder.Strict", Field, 0}, - {"Directive", Type, 0}, - {"Encoder", Type, 0}, - {"EndElement", Type, 0}, - {"EndElement.Name", Field, 0}, - {"Escape", Func, 0}, - {"EscapeText", Func, 1}, - {"HTMLAutoClose", Var, 0}, - {"HTMLEntity", Var, 0}, - {"Header", Const, 0}, - {"Marshal", Func, 0}, - {"MarshalIndent", Func, 0}, - {"Marshaler", Type, 2}, - {"MarshalerAttr", Type, 2}, - {"Name", Type, 0}, - {"Name.Local", Field, 0}, - {"Name.Space", Field, 0}, - {"NewDecoder", Func, 0}, - {"NewEncoder", Func, 0}, - {"NewTokenDecoder", Func, 10}, - {"ProcInst", Type, 0}, - {"ProcInst.Inst", Field, 0}, - {"ProcInst.Target", Field, 0}, - {"StartElement", Type, 0}, - {"StartElement.Attr", Field, 0}, - {"StartElement.Name", Field, 0}, - {"SyntaxError", Type, 0}, - {"SyntaxError.Line", Field, 0}, - {"SyntaxError.Msg", Field, 0}, - {"TagPathError", Type, 0}, - {"TagPathError.Field1", Field, 0}, - {"TagPathError.Field2", Field, 0}, - {"TagPathError.Struct", Field, 0}, - {"TagPathError.Tag1", Field, 0}, - {"TagPathError.Tag2", Field, 0}, - {"Token", Type, 0}, - {"TokenReader", Type, 10}, - {"Unmarshal", Func, 0}, - {"UnmarshalError", Type, 0}, - {"Unmarshaler", Type, 2}, - {"UnmarshalerAttr", Type, 2}, - {"UnsupportedTypeError", Type, 0}, - {"UnsupportedTypeError.Type", Field, 0}, + {"(*Decoder).Decode", Method, 0, ""}, + {"(*Decoder).DecodeElement", Method, 0, ""}, + {"(*Decoder).InputOffset", Method, 4, ""}, + {"(*Decoder).InputPos", Method, 19, ""}, + {"(*Decoder).RawToken", Method, 0, ""}, + {"(*Decoder).Skip", Method, 0, ""}, + {"(*Decoder).Token", Method, 0, ""}, + {"(*Encoder).Close", Method, 20, ""}, + {"(*Encoder).Encode", Method, 0, ""}, + {"(*Encoder).EncodeElement", Method, 2, ""}, + {"(*Encoder).EncodeToken", Method, 2, ""}, + {"(*Encoder).Flush", Method, 2, ""}, + {"(*Encoder).Indent", Method, 1, ""}, + {"(*SyntaxError).Error", Method, 0, ""}, + {"(*TagPathError).Error", Method, 0, ""}, + {"(*UnsupportedTypeError).Error", Method, 0, ""}, + {"(CharData).Copy", Method, 0, ""}, + {"(Comment).Copy", Method, 0, ""}, + {"(Directive).Copy", Method, 0, ""}, + {"(ProcInst).Copy", Method, 0, ""}, + {"(StartElement).Copy", Method, 0, ""}, + {"(StartElement).End", Method, 2, ""}, + {"(UnmarshalError).Error", Method, 0, ""}, + {"Attr", Type, 0, ""}, + {"Attr.Name", Field, 0, ""}, + {"Attr.Value", Field, 0, ""}, + {"CharData", Type, 0, ""}, + {"Comment", Type, 0, ""}, + {"CopyToken", Func, 0, "func(t Token) Token"}, + {"Decoder", Type, 0, ""}, + {"Decoder.AutoClose", Field, 0, ""}, + {"Decoder.CharsetReader", Field, 0, ""}, + {"Decoder.DefaultSpace", Field, 1, ""}, + {"Decoder.Entity", Field, 0, ""}, + {"Decoder.Strict", Field, 0, ""}, + {"Directive", Type, 0, ""}, + {"Encoder", Type, 0, ""}, + {"EndElement", Type, 0, ""}, + {"EndElement.Name", Field, 0, ""}, + {"Escape", Func, 0, "func(w io.Writer, s []byte)"}, + {"EscapeText", Func, 1, "func(w io.Writer, s []byte) error"}, + {"HTMLAutoClose", Var, 0, ""}, + {"HTMLEntity", Var, 0, ""}, + {"Header", Const, 0, ""}, + {"Marshal", Func, 0, "func(v any) ([]byte, error)"}, + {"MarshalIndent", Func, 0, "func(v any, prefix string, indent string) ([]byte, error)"}, + {"Marshaler", Type, 2, ""}, + {"MarshalerAttr", Type, 2, ""}, + {"Name", Type, 0, ""}, + {"Name.Local", Field, 0, ""}, + {"Name.Space", Field, 0, ""}, + {"NewDecoder", Func, 0, "func(r io.Reader) *Decoder"}, + {"NewEncoder", Func, 0, "func(w io.Writer) *Encoder"}, + {"NewTokenDecoder", Func, 10, "func(t TokenReader) *Decoder"}, + {"ProcInst", Type, 0, ""}, + {"ProcInst.Inst", Field, 0, ""}, + {"ProcInst.Target", Field, 0, ""}, + {"StartElement", Type, 0, ""}, + {"StartElement.Attr", Field, 0, ""}, + {"StartElement.Name", Field, 0, ""}, + {"SyntaxError", Type, 0, ""}, + {"SyntaxError.Line", Field, 0, ""}, + {"SyntaxError.Msg", Field, 0, ""}, + {"TagPathError", Type, 0, ""}, + {"TagPathError.Field1", Field, 0, ""}, + {"TagPathError.Field2", Field, 0, ""}, + {"TagPathError.Struct", Field, 0, ""}, + {"TagPathError.Tag1", Field, 0, ""}, + {"TagPathError.Tag2", Field, 0, ""}, + {"Token", Type, 0, ""}, + {"TokenReader", Type, 10, ""}, + {"Unmarshal", Func, 0, "func(data []byte, v any) error"}, + {"UnmarshalError", Type, 0, ""}, + {"Unmarshaler", Type, 2, ""}, + {"UnmarshalerAttr", Type, 2, ""}, + {"UnsupportedTypeError", Type, 0, ""}, + {"UnsupportedTypeError.Type", Field, 0, ""}, }, "errors": { - {"As", Func, 13}, - {"ErrUnsupported", Var, 21}, - {"Is", Func, 13}, - {"Join", Func, 20}, - {"New", Func, 0}, - {"Unwrap", Func, 13}, + {"As", Func, 13, "func(err error, target any) bool"}, + {"ErrUnsupported", Var, 21, ""}, + {"Is", Func, 13, "func(err error, target error) bool"}, + {"Join", Func, 20, "func(errs ...error) error"}, + {"New", Func, 0, "func(text string) error"}, + {"Unwrap", Func, 13, "func(err error) error"}, }, "expvar": { - {"(*Float).Add", Method, 0}, - {"(*Float).Set", Method, 0}, - {"(*Float).String", Method, 0}, - {"(*Float).Value", Method, 8}, - {"(*Int).Add", Method, 0}, - {"(*Int).Set", Method, 0}, - {"(*Int).String", Method, 0}, - {"(*Int).Value", Method, 8}, - {"(*Map).Add", Method, 0}, - {"(*Map).AddFloat", Method, 0}, - {"(*Map).Delete", Method, 12}, - {"(*Map).Do", Method, 0}, - {"(*Map).Get", Method, 0}, - {"(*Map).Init", Method, 0}, - {"(*Map).Set", Method, 0}, - {"(*Map).String", Method, 0}, - {"(*String).Set", Method, 0}, - {"(*String).String", Method, 0}, - {"(*String).Value", Method, 8}, - {"(Func).String", Method, 0}, - {"(Func).Value", Method, 8}, - {"Do", Func, 0}, - {"Float", Type, 0}, - {"Func", Type, 0}, - {"Get", Func, 0}, - {"Handler", Func, 8}, - {"Int", Type, 0}, - {"KeyValue", Type, 0}, - {"KeyValue.Key", Field, 0}, - {"KeyValue.Value", Field, 0}, - {"Map", Type, 0}, - {"NewFloat", Func, 0}, - {"NewInt", Func, 0}, - {"NewMap", Func, 0}, - {"NewString", Func, 0}, - {"Publish", Func, 0}, - {"String", Type, 0}, - {"Var", Type, 0}, + {"(*Float).Add", Method, 0, ""}, + {"(*Float).Set", Method, 0, ""}, + {"(*Float).String", Method, 0, ""}, + {"(*Float).Value", Method, 8, ""}, + {"(*Int).Add", Method, 0, ""}, + {"(*Int).Set", Method, 0, ""}, + {"(*Int).String", Method, 0, ""}, + {"(*Int).Value", Method, 8, ""}, + {"(*Map).Add", Method, 0, ""}, + {"(*Map).AddFloat", Method, 0, ""}, + {"(*Map).Delete", Method, 12, ""}, + {"(*Map).Do", Method, 0, ""}, + {"(*Map).Get", Method, 0, ""}, + {"(*Map).Init", Method, 0, ""}, + {"(*Map).Set", Method, 0, ""}, + {"(*Map).String", Method, 0, ""}, + {"(*String).Set", Method, 0, ""}, + {"(*String).String", Method, 0, ""}, + {"(*String).Value", Method, 8, ""}, + {"(Func).String", Method, 0, ""}, + {"(Func).Value", Method, 8, ""}, + {"Do", Func, 0, "func(f func(KeyValue))"}, + {"Float", Type, 0, ""}, + {"Func", Type, 0, ""}, + {"Get", Func, 0, "func(name string) Var"}, + {"Handler", Func, 8, "func() http.Handler"}, + {"Int", Type, 0, ""}, + {"KeyValue", Type, 0, ""}, + {"KeyValue.Key", Field, 0, ""}, + {"KeyValue.Value", Field, 0, ""}, + {"Map", Type, 0, ""}, + {"NewFloat", Func, 0, "func(name string) *Float"}, + {"NewInt", Func, 0, "func(name string) *Int"}, + {"NewMap", Func, 0, "func(name string) *Map"}, + {"NewString", Func, 0, "func(name string) *String"}, + {"Publish", Func, 0, "func(name string, v Var)"}, + {"String", Type, 0, ""}, + {"Var", Type, 0, ""}, }, "flag": { - {"(*FlagSet).Arg", Method, 0}, - {"(*FlagSet).Args", Method, 0}, - {"(*FlagSet).Bool", Method, 0}, - {"(*FlagSet).BoolFunc", Method, 21}, - {"(*FlagSet).BoolVar", Method, 0}, - {"(*FlagSet).Duration", Method, 0}, - {"(*FlagSet).DurationVar", Method, 0}, - {"(*FlagSet).ErrorHandling", Method, 10}, - {"(*FlagSet).Float64", Method, 0}, - {"(*FlagSet).Float64Var", Method, 0}, - {"(*FlagSet).Func", Method, 16}, - {"(*FlagSet).Init", Method, 0}, - {"(*FlagSet).Int", Method, 0}, - {"(*FlagSet).Int64", Method, 0}, - {"(*FlagSet).Int64Var", Method, 0}, - {"(*FlagSet).IntVar", Method, 0}, - {"(*FlagSet).Lookup", Method, 0}, - {"(*FlagSet).NArg", Method, 0}, - {"(*FlagSet).NFlag", Method, 0}, - {"(*FlagSet).Name", Method, 10}, - {"(*FlagSet).Output", Method, 10}, - {"(*FlagSet).Parse", Method, 0}, - {"(*FlagSet).Parsed", Method, 0}, - {"(*FlagSet).PrintDefaults", Method, 0}, - {"(*FlagSet).Set", Method, 0}, - {"(*FlagSet).SetOutput", Method, 0}, - {"(*FlagSet).String", Method, 0}, - {"(*FlagSet).StringVar", Method, 0}, - {"(*FlagSet).TextVar", Method, 19}, - {"(*FlagSet).Uint", Method, 0}, - {"(*FlagSet).Uint64", Method, 0}, - {"(*FlagSet).Uint64Var", Method, 0}, - {"(*FlagSet).UintVar", Method, 0}, - {"(*FlagSet).Var", Method, 0}, - {"(*FlagSet).Visit", Method, 0}, - {"(*FlagSet).VisitAll", Method, 0}, - {"Arg", Func, 0}, - {"Args", Func, 0}, - {"Bool", Func, 0}, - {"BoolFunc", Func, 21}, - {"BoolVar", Func, 0}, - {"CommandLine", Var, 2}, - {"ContinueOnError", Const, 0}, - {"Duration", Func, 0}, - {"DurationVar", Func, 0}, - {"ErrHelp", Var, 0}, - {"ErrorHandling", Type, 0}, - {"ExitOnError", Const, 0}, - {"Flag", Type, 0}, - {"Flag.DefValue", Field, 0}, - {"Flag.Name", Field, 0}, - {"Flag.Usage", Field, 0}, - {"Flag.Value", Field, 0}, - {"FlagSet", Type, 0}, - {"FlagSet.Usage", Field, 0}, - {"Float64", Func, 0}, - {"Float64Var", Func, 0}, - {"Func", Func, 16}, - {"Getter", Type, 2}, - {"Int", Func, 0}, - {"Int64", Func, 0}, - {"Int64Var", Func, 0}, - {"IntVar", Func, 0}, - {"Lookup", Func, 0}, - {"NArg", Func, 0}, - {"NFlag", Func, 0}, - {"NewFlagSet", Func, 0}, - {"PanicOnError", Const, 0}, - {"Parse", Func, 0}, - {"Parsed", Func, 0}, - {"PrintDefaults", Func, 0}, - {"Set", Func, 0}, - {"String", Func, 0}, - {"StringVar", Func, 0}, - {"TextVar", Func, 19}, - {"Uint", Func, 0}, - {"Uint64", Func, 0}, - {"Uint64Var", Func, 0}, - {"UintVar", Func, 0}, - {"UnquoteUsage", Func, 5}, - {"Usage", Var, 0}, - {"Value", Type, 0}, - {"Var", Func, 0}, - {"Visit", Func, 0}, - {"VisitAll", Func, 0}, + {"(*FlagSet).Arg", Method, 0, ""}, + {"(*FlagSet).Args", Method, 0, ""}, + {"(*FlagSet).Bool", Method, 0, ""}, + {"(*FlagSet).BoolFunc", Method, 21, ""}, + {"(*FlagSet).BoolVar", Method, 0, ""}, + {"(*FlagSet).Duration", Method, 0, ""}, + {"(*FlagSet).DurationVar", Method, 0, ""}, + {"(*FlagSet).ErrorHandling", Method, 10, ""}, + {"(*FlagSet).Float64", Method, 0, ""}, + {"(*FlagSet).Float64Var", Method, 0, ""}, + {"(*FlagSet).Func", Method, 16, ""}, + {"(*FlagSet).Init", Method, 0, ""}, + {"(*FlagSet).Int", Method, 0, ""}, + {"(*FlagSet).Int64", Method, 0, ""}, + {"(*FlagSet).Int64Var", Method, 0, ""}, + {"(*FlagSet).IntVar", Method, 0, ""}, + {"(*FlagSet).Lookup", Method, 0, ""}, + {"(*FlagSet).NArg", Method, 0, ""}, + {"(*FlagSet).NFlag", Method, 0, ""}, + {"(*FlagSet).Name", Method, 10, ""}, + {"(*FlagSet).Output", Method, 10, ""}, + {"(*FlagSet).Parse", Method, 0, ""}, + {"(*FlagSet).Parsed", Method, 0, ""}, + {"(*FlagSet).PrintDefaults", Method, 0, ""}, + {"(*FlagSet).Set", Method, 0, ""}, + {"(*FlagSet).SetOutput", Method, 0, ""}, + {"(*FlagSet).String", Method, 0, ""}, + {"(*FlagSet).StringVar", Method, 0, ""}, + {"(*FlagSet).TextVar", Method, 19, ""}, + {"(*FlagSet).Uint", Method, 0, ""}, + {"(*FlagSet).Uint64", Method, 0, ""}, + {"(*FlagSet).Uint64Var", Method, 0, ""}, + {"(*FlagSet).UintVar", Method, 0, ""}, + {"(*FlagSet).Var", Method, 0, ""}, + {"(*FlagSet).Visit", Method, 0, ""}, + {"(*FlagSet).VisitAll", Method, 0, ""}, + {"Arg", Func, 0, "func(i int) string"}, + {"Args", Func, 0, "func() []string"}, + {"Bool", Func, 0, "func(name string, value bool, usage string) *bool"}, + {"BoolFunc", Func, 21, "func(name string, usage string, fn func(string) error)"}, + {"BoolVar", Func, 0, "func(p *bool, name string, value bool, usage string)"}, + {"CommandLine", Var, 2, ""}, + {"ContinueOnError", Const, 0, ""}, + {"Duration", Func, 0, "func(name string, value time.Duration, usage string) *time.Duration"}, + {"DurationVar", Func, 0, "func(p *time.Duration, name string, value time.Duration, usage string)"}, + {"ErrHelp", Var, 0, ""}, + {"ErrorHandling", Type, 0, ""}, + {"ExitOnError", Const, 0, ""}, + {"Flag", Type, 0, ""}, + {"Flag.DefValue", Field, 0, ""}, + {"Flag.Name", Field, 0, ""}, + {"Flag.Usage", Field, 0, ""}, + {"Flag.Value", Field, 0, ""}, + {"FlagSet", Type, 0, ""}, + {"FlagSet.Usage", Field, 0, ""}, + {"Float64", Func, 0, "func(name string, value float64, usage string) *float64"}, + {"Float64Var", Func, 0, "func(p *float64, name string, value float64, usage string)"}, + {"Func", Func, 16, "func(name string, usage string, fn func(string) error)"}, + {"Getter", Type, 2, ""}, + {"Int", Func, 0, "func(name string, value int, usage string) *int"}, + {"Int64", Func, 0, "func(name string, value int64, usage string) *int64"}, + {"Int64Var", Func, 0, "func(p *int64, name string, value int64, usage string)"}, + {"IntVar", Func, 0, "func(p *int, name string, value int, usage string)"}, + {"Lookup", Func, 0, "func(name string) *Flag"}, + {"NArg", Func, 0, "func() int"}, + {"NFlag", Func, 0, "func() int"}, + {"NewFlagSet", Func, 0, "func(name string, errorHandling ErrorHandling) *FlagSet"}, + {"PanicOnError", Const, 0, ""}, + {"Parse", Func, 0, "func()"}, + {"Parsed", Func, 0, "func() bool"}, + {"PrintDefaults", Func, 0, "func()"}, + {"Set", Func, 0, "func(name string, value string) error"}, + {"String", Func, 0, "func(name string, value string, usage string) *string"}, + {"StringVar", Func, 0, "func(p *string, name string, value string, usage string)"}, + {"TextVar", Func, 19, "func(p encoding.TextUnmarshaler, name string, value encoding.TextMarshaler, usage string)"}, + {"Uint", Func, 0, "func(name string, value uint, usage string) *uint"}, + {"Uint64", Func, 0, "func(name string, value uint64, usage string) *uint64"}, + {"Uint64Var", Func, 0, "func(p *uint64, name string, value uint64, usage string)"}, + {"UintVar", Func, 0, "func(p *uint, name string, value uint, usage string)"}, + {"UnquoteUsage", Func, 5, "func(flag *Flag) (name string, usage string)"}, + {"Usage", Var, 0, ""}, + {"Value", Type, 0, ""}, + {"Var", Func, 0, "func(value Value, name string, usage string)"}, + {"Visit", Func, 0, "func(fn func(*Flag))"}, + {"VisitAll", Func, 0, "func(fn func(*Flag))"}, }, "fmt": { - {"Append", Func, 19}, - {"Appendf", Func, 19}, - {"Appendln", Func, 19}, - {"Errorf", Func, 0}, - {"FormatString", Func, 20}, - {"Formatter", Type, 0}, - {"Fprint", Func, 0}, - {"Fprintf", Func, 0}, - {"Fprintln", Func, 0}, - {"Fscan", Func, 0}, - {"Fscanf", Func, 0}, - {"Fscanln", Func, 0}, - {"GoStringer", Type, 0}, - {"Print", Func, 0}, - {"Printf", Func, 0}, - {"Println", Func, 0}, - {"Scan", Func, 0}, - {"ScanState", Type, 0}, - {"Scanf", Func, 0}, - {"Scanln", Func, 0}, - {"Scanner", Type, 0}, - {"Sprint", Func, 0}, - {"Sprintf", Func, 0}, - {"Sprintln", Func, 0}, - {"Sscan", Func, 0}, - {"Sscanf", Func, 0}, - {"Sscanln", Func, 0}, - {"State", Type, 0}, - {"Stringer", Type, 0}, + {"Append", Func, 19, "func(b []byte, a ...any) []byte"}, + {"Appendf", Func, 19, "func(b []byte, format string, a ...any) []byte"}, + {"Appendln", Func, 19, "func(b []byte, a ...any) []byte"}, + {"Errorf", Func, 0, "func(format string, a ...any) error"}, + {"FormatString", Func, 20, "func(state State, verb rune) string"}, + {"Formatter", Type, 0, ""}, + {"Fprint", Func, 0, "func(w io.Writer, a ...any) (n int, err error)"}, + {"Fprintf", Func, 0, "func(w io.Writer, format string, a ...any) (n int, err error)"}, + {"Fprintln", Func, 0, "func(w io.Writer, a ...any) (n int, err error)"}, + {"Fscan", Func, 0, "func(r io.Reader, a ...any) (n int, err error)"}, + {"Fscanf", Func, 0, "func(r io.Reader, format string, a ...any) (n int, err error)"}, + {"Fscanln", Func, 0, "func(r io.Reader, a ...any) (n int, err error)"}, + {"GoStringer", Type, 0, ""}, + {"Print", Func, 0, "func(a ...any) (n int, err error)"}, + {"Printf", Func, 0, "func(format string, a ...any) (n int, err error)"}, + {"Println", Func, 0, "func(a ...any) (n int, err error)"}, + {"Scan", Func, 0, "func(a ...any) (n int, err error)"}, + {"ScanState", Type, 0, ""}, + {"Scanf", Func, 0, "func(format string, a ...any) (n int, err error)"}, + {"Scanln", Func, 0, "func(a ...any) (n int, err error)"}, + {"Scanner", Type, 0, ""}, + {"Sprint", Func, 0, "func(a ...any) string"}, + {"Sprintf", Func, 0, "func(format string, a ...any) string"}, + {"Sprintln", Func, 0, "func(a ...any) string"}, + {"Sscan", Func, 0, "func(str string, a ...any) (n int, err error)"}, + {"Sscanf", Func, 0, "func(str string, format string, a ...any) (n int, err error)"}, + {"Sscanln", Func, 0, "func(str string, a ...any) (n int, err error)"}, + {"State", Type, 0, ""}, + {"Stringer", Type, 0, ""}, }, "go/ast": { - {"(*ArrayType).End", Method, 0}, - {"(*ArrayType).Pos", Method, 0}, - {"(*AssignStmt).End", Method, 0}, - {"(*AssignStmt).Pos", Method, 0}, - {"(*BadDecl).End", Method, 0}, - {"(*BadDecl).Pos", Method, 0}, - {"(*BadExpr).End", Method, 0}, - {"(*BadExpr).Pos", Method, 0}, - {"(*BadStmt).End", Method, 0}, - {"(*BadStmt).Pos", Method, 0}, - {"(*BasicLit).End", Method, 0}, - {"(*BasicLit).Pos", Method, 0}, - {"(*BinaryExpr).End", Method, 0}, - {"(*BinaryExpr).Pos", Method, 0}, - {"(*BlockStmt).End", Method, 0}, - {"(*BlockStmt).Pos", Method, 0}, - {"(*BranchStmt).End", Method, 0}, - {"(*BranchStmt).Pos", Method, 0}, - {"(*CallExpr).End", Method, 0}, - {"(*CallExpr).Pos", Method, 0}, - {"(*CaseClause).End", Method, 0}, - {"(*CaseClause).Pos", Method, 0}, - {"(*ChanType).End", Method, 0}, - {"(*ChanType).Pos", Method, 0}, - {"(*CommClause).End", Method, 0}, - {"(*CommClause).Pos", Method, 0}, - {"(*Comment).End", Method, 0}, - {"(*Comment).Pos", Method, 0}, - {"(*CommentGroup).End", Method, 0}, - {"(*CommentGroup).Pos", Method, 0}, - {"(*CommentGroup).Text", Method, 0}, - {"(*CompositeLit).End", Method, 0}, - {"(*CompositeLit).Pos", Method, 0}, - {"(*DeclStmt).End", Method, 0}, - {"(*DeclStmt).Pos", Method, 0}, - {"(*DeferStmt).End", Method, 0}, - {"(*DeferStmt).Pos", Method, 0}, - {"(*Ellipsis).End", Method, 0}, - {"(*Ellipsis).Pos", Method, 0}, - {"(*EmptyStmt).End", Method, 0}, - {"(*EmptyStmt).Pos", Method, 0}, - {"(*ExprStmt).End", Method, 0}, - {"(*ExprStmt).Pos", Method, 0}, - {"(*Field).End", Method, 0}, - {"(*Field).Pos", Method, 0}, - {"(*FieldList).End", Method, 0}, - {"(*FieldList).NumFields", Method, 0}, - {"(*FieldList).Pos", Method, 0}, - {"(*File).End", Method, 0}, - {"(*File).Pos", Method, 0}, - {"(*ForStmt).End", Method, 0}, - {"(*ForStmt).Pos", Method, 0}, - {"(*FuncDecl).End", Method, 0}, - {"(*FuncDecl).Pos", Method, 0}, - {"(*FuncLit).End", Method, 0}, - {"(*FuncLit).Pos", Method, 0}, - {"(*FuncType).End", Method, 0}, - {"(*FuncType).Pos", Method, 0}, - {"(*GenDecl).End", Method, 0}, - {"(*GenDecl).Pos", Method, 0}, - {"(*GoStmt).End", Method, 0}, - {"(*GoStmt).Pos", Method, 0}, - {"(*Ident).End", Method, 0}, - {"(*Ident).IsExported", Method, 0}, - {"(*Ident).Pos", Method, 0}, - {"(*Ident).String", Method, 0}, - {"(*IfStmt).End", Method, 0}, - {"(*IfStmt).Pos", Method, 0}, - {"(*ImportSpec).End", Method, 0}, - {"(*ImportSpec).Pos", Method, 0}, - {"(*IncDecStmt).End", Method, 0}, - {"(*IncDecStmt).Pos", Method, 0}, - {"(*IndexExpr).End", Method, 0}, - {"(*IndexExpr).Pos", Method, 0}, - {"(*IndexListExpr).End", Method, 18}, - {"(*IndexListExpr).Pos", Method, 18}, - {"(*InterfaceType).End", Method, 0}, - {"(*InterfaceType).Pos", Method, 0}, - {"(*KeyValueExpr).End", Method, 0}, - {"(*KeyValueExpr).Pos", Method, 0}, - {"(*LabeledStmt).End", Method, 0}, - {"(*LabeledStmt).Pos", Method, 0}, - {"(*MapType).End", Method, 0}, - {"(*MapType).Pos", Method, 0}, - {"(*Object).Pos", Method, 0}, - {"(*Package).End", Method, 0}, - {"(*Package).Pos", Method, 0}, - {"(*ParenExpr).End", Method, 0}, - {"(*ParenExpr).Pos", Method, 0}, - {"(*RangeStmt).End", Method, 0}, - {"(*RangeStmt).Pos", Method, 0}, - {"(*ReturnStmt).End", Method, 0}, - {"(*ReturnStmt).Pos", Method, 0}, - {"(*Scope).Insert", Method, 0}, - {"(*Scope).Lookup", Method, 0}, - {"(*Scope).String", Method, 0}, - {"(*SelectStmt).End", Method, 0}, - {"(*SelectStmt).Pos", Method, 0}, - {"(*SelectorExpr).End", Method, 0}, - {"(*SelectorExpr).Pos", Method, 0}, - {"(*SendStmt).End", Method, 0}, - {"(*SendStmt).Pos", Method, 0}, - {"(*SliceExpr).End", Method, 0}, - {"(*SliceExpr).Pos", Method, 0}, - {"(*StarExpr).End", Method, 0}, - {"(*StarExpr).Pos", Method, 0}, - {"(*StructType).End", Method, 0}, - {"(*StructType).Pos", Method, 0}, - {"(*SwitchStmt).End", Method, 0}, - {"(*SwitchStmt).Pos", Method, 0}, - {"(*TypeAssertExpr).End", Method, 0}, - {"(*TypeAssertExpr).Pos", Method, 0}, - {"(*TypeSpec).End", Method, 0}, - {"(*TypeSpec).Pos", Method, 0}, - {"(*TypeSwitchStmt).End", Method, 0}, - {"(*TypeSwitchStmt).Pos", Method, 0}, - {"(*UnaryExpr).End", Method, 0}, - {"(*UnaryExpr).Pos", Method, 0}, - {"(*ValueSpec).End", Method, 0}, - {"(*ValueSpec).Pos", Method, 0}, - {"(CommentMap).Comments", Method, 1}, - {"(CommentMap).Filter", Method, 1}, - {"(CommentMap).String", Method, 1}, - {"(CommentMap).Update", Method, 1}, - {"(ObjKind).String", Method, 0}, - {"ArrayType", Type, 0}, - {"ArrayType.Elt", Field, 0}, - {"ArrayType.Lbrack", Field, 0}, - {"ArrayType.Len", Field, 0}, - {"AssignStmt", Type, 0}, - {"AssignStmt.Lhs", Field, 0}, - {"AssignStmt.Rhs", Field, 0}, - {"AssignStmt.Tok", Field, 0}, - {"AssignStmt.TokPos", Field, 0}, - {"Bad", Const, 0}, - {"BadDecl", Type, 0}, - {"BadDecl.From", Field, 0}, - {"BadDecl.To", Field, 0}, - {"BadExpr", Type, 0}, - {"BadExpr.From", Field, 0}, - {"BadExpr.To", Field, 0}, - {"BadStmt", Type, 0}, - {"BadStmt.From", Field, 0}, - {"BadStmt.To", Field, 0}, - {"BasicLit", Type, 0}, - {"BasicLit.Kind", Field, 0}, - {"BasicLit.Value", Field, 0}, - {"BasicLit.ValuePos", Field, 0}, - {"BinaryExpr", Type, 0}, - {"BinaryExpr.Op", Field, 0}, - {"BinaryExpr.OpPos", Field, 0}, - {"BinaryExpr.X", Field, 0}, - {"BinaryExpr.Y", Field, 0}, - {"BlockStmt", Type, 0}, - {"BlockStmt.Lbrace", Field, 0}, - {"BlockStmt.List", Field, 0}, - {"BlockStmt.Rbrace", Field, 0}, - {"BranchStmt", Type, 0}, - {"BranchStmt.Label", Field, 0}, - {"BranchStmt.Tok", Field, 0}, - {"BranchStmt.TokPos", Field, 0}, - {"CallExpr", Type, 0}, - {"CallExpr.Args", Field, 0}, - {"CallExpr.Ellipsis", Field, 0}, - {"CallExpr.Fun", Field, 0}, - {"CallExpr.Lparen", Field, 0}, - {"CallExpr.Rparen", Field, 0}, - {"CaseClause", Type, 0}, - {"CaseClause.Body", Field, 0}, - {"CaseClause.Case", Field, 0}, - {"CaseClause.Colon", Field, 0}, - {"CaseClause.List", Field, 0}, - {"ChanDir", Type, 0}, - {"ChanType", Type, 0}, - {"ChanType.Arrow", Field, 1}, - {"ChanType.Begin", Field, 0}, - {"ChanType.Dir", Field, 0}, - {"ChanType.Value", Field, 0}, - {"CommClause", Type, 0}, - {"CommClause.Body", Field, 0}, - {"CommClause.Case", Field, 0}, - {"CommClause.Colon", Field, 0}, - {"CommClause.Comm", Field, 0}, - {"Comment", Type, 0}, - {"Comment.Slash", Field, 0}, - {"Comment.Text", Field, 0}, - {"CommentGroup", Type, 0}, - {"CommentGroup.List", Field, 0}, - {"CommentMap", Type, 1}, - {"CompositeLit", Type, 0}, - {"CompositeLit.Elts", Field, 0}, - {"CompositeLit.Incomplete", Field, 11}, - {"CompositeLit.Lbrace", Field, 0}, - {"CompositeLit.Rbrace", Field, 0}, - {"CompositeLit.Type", Field, 0}, - {"Con", Const, 0}, - {"Decl", Type, 0}, - {"DeclStmt", Type, 0}, - {"DeclStmt.Decl", Field, 0}, - {"DeferStmt", Type, 0}, - {"DeferStmt.Call", Field, 0}, - {"DeferStmt.Defer", Field, 0}, - {"Ellipsis", Type, 0}, - {"Ellipsis.Ellipsis", Field, 0}, - {"Ellipsis.Elt", Field, 0}, - {"EmptyStmt", Type, 0}, - {"EmptyStmt.Implicit", Field, 5}, - {"EmptyStmt.Semicolon", Field, 0}, - {"Expr", Type, 0}, - {"ExprStmt", Type, 0}, - {"ExprStmt.X", Field, 0}, - {"Field", Type, 0}, - {"Field.Comment", Field, 0}, - {"Field.Doc", Field, 0}, - {"Field.Names", Field, 0}, - {"Field.Tag", Field, 0}, - {"Field.Type", Field, 0}, - {"FieldFilter", Type, 0}, - {"FieldList", Type, 0}, - {"FieldList.Closing", Field, 0}, - {"FieldList.List", Field, 0}, - {"FieldList.Opening", Field, 0}, - {"File", Type, 0}, - {"File.Comments", Field, 0}, - {"File.Decls", Field, 0}, - {"File.Doc", Field, 0}, - {"File.FileEnd", Field, 20}, - {"File.FileStart", Field, 20}, - {"File.GoVersion", Field, 21}, - {"File.Imports", Field, 0}, - {"File.Name", Field, 0}, - {"File.Package", Field, 0}, - {"File.Scope", Field, 0}, - {"File.Unresolved", Field, 0}, - {"FileExports", Func, 0}, - {"Filter", Type, 0}, - {"FilterDecl", Func, 0}, - {"FilterFile", Func, 0}, - {"FilterFuncDuplicates", Const, 0}, - {"FilterImportDuplicates", Const, 0}, - {"FilterPackage", Func, 0}, - {"FilterUnassociatedComments", Const, 0}, - {"ForStmt", Type, 0}, - {"ForStmt.Body", Field, 0}, - {"ForStmt.Cond", Field, 0}, - {"ForStmt.For", Field, 0}, - {"ForStmt.Init", Field, 0}, - {"ForStmt.Post", Field, 0}, - {"Fprint", Func, 0}, - {"Fun", Const, 0}, - {"FuncDecl", Type, 0}, - {"FuncDecl.Body", Field, 0}, - {"FuncDecl.Doc", Field, 0}, - {"FuncDecl.Name", Field, 0}, - {"FuncDecl.Recv", Field, 0}, - {"FuncDecl.Type", Field, 0}, - {"FuncLit", Type, 0}, - {"FuncLit.Body", Field, 0}, - {"FuncLit.Type", Field, 0}, - {"FuncType", Type, 0}, - {"FuncType.Func", Field, 0}, - {"FuncType.Params", Field, 0}, - {"FuncType.Results", Field, 0}, - {"FuncType.TypeParams", Field, 18}, - {"GenDecl", Type, 0}, - {"GenDecl.Doc", Field, 0}, - {"GenDecl.Lparen", Field, 0}, - {"GenDecl.Rparen", Field, 0}, - {"GenDecl.Specs", Field, 0}, - {"GenDecl.Tok", Field, 0}, - {"GenDecl.TokPos", Field, 0}, - {"GoStmt", Type, 0}, - {"GoStmt.Call", Field, 0}, - {"GoStmt.Go", Field, 0}, - {"Ident", Type, 0}, - {"Ident.Name", Field, 0}, - {"Ident.NamePos", Field, 0}, - {"Ident.Obj", Field, 0}, - {"IfStmt", Type, 0}, - {"IfStmt.Body", Field, 0}, - {"IfStmt.Cond", Field, 0}, - {"IfStmt.Else", Field, 0}, - {"IfStmt.If", Field, 0}, - {"IfStmt.Init", Field, 0}, - {"ImportSpec", Type, 0}, - {"ImportSpec.Comment", Field, 0}, - {"ImportSpec.Doc", Field, 0}, - {"ImportSpec.EndPos", Field, 0}, - {"ImportSpec.Name", Field, 0}, - {"ImportSpec.Path", Field, 0}, - {"Importer", Type, 0}, - {"IncDecStmt", Type, 0}, - {"IncDecStmt.Tok", Field, 0}, - {"IncDecStmt.TokPos", Field, 0}, - {"IncDecStmt.X", Field, 0}, - {"IndexExpr", Type, 0}, - {"IndexExpr.Index", Field, 0}, - {"IndexExpr.Lbrack", Field, 0}, - {"IndexExpr.Rbrack", Field, 0}, - {"IndexExpr.X", Field, 0}, - {"IndexListExpr", Type, 18}, - {"IndexListExpr.Indices", Field, 18}, - {"IndexListExpr.Lbrack", Field, 18}, - {"IndexListExpr.Rbrack", Field, 18}, - {"IndexListExpr.X", Field, 18}, - {"Inspect", Func, 0}, - {"InterfaceType", Type, 0}, - {"InterfaceType.Incomplete", Field, 0}, - {"InterfaceType.Interface", Field, 0}, - {"InterfaceType.Methods", Field, 0}, - {"IsExported", Func, 0}, - {"IsGenerated", Func, 21}, - {"KeyValueExpr", Type, 0}, - {"KeyValueExpr.Colon", Field, 0}, - {"KeyValueExpr.Key", Field, 0}, - {"KeyValueExpr.Value", Field, 0}, - {"LabeledStmt", Type, 0}, - {"LabeledStmt.Colon", Field, 0}, - {"LabeledStmt.Label", Field, 0}, - {"LabeledStmt.Stmt", Field, 0}, - {"Lbl", Const, 0}, - {"MapType", Type, 0}, - {"MapType.Key", Field, 0}, - {"MapType.Map", Field, 0}, - {"MapType.Value", Field, 0}, - {"MergeMode", Type, 0}, - {"MergePackageFiles", Func, 0}, - {"NewCommentMap", Func, 1}, - {"NewIdent", Func, 0}, - {"NewObj", Func, 0}, - {"NewPackage", Func, 0}, - {"NewScope", Func, 0}, - {"Node", Type, 0}, - {"NotNilFilter", Func, 0}, - {"ObjKind", Type, 0}, - {"Object", Type, 0}, - {"Object.Data", Field, 0}, - {"Object.Decl", Field, 0}, - {"Object.Kind", Field, 0}, - {"Object.Name", Field, 0}, - {"Object.Type", Field, 0}, - {"Package", Type, 0}, - {"Package.Files", Field, 0}, - {"Package.Imports", Field, 0}, - {"Package.Name", Field, 0}, - {"Package.Scope", Field, 0}, - {"PackageExports", Func, 0}, - {"ParenExpr", Type, 0}, - {"ParenExpr.Lparen", Field, 0}, - {"ParenExpr.Rparen", Field, 0}, - {"ParenExpr.X", Field, 0}, - {"Pkg", Const, 0}, - {"Preorder", Func, 23}, - {"Print", Func, 0}, - {"RECV", Const, 0}, - {"RangeStmt", Type, 0}, - {"RangeStmt.Body", Field, 0}, - {"RangeStmt.For", Field, 0}, - {"RangeStmt.Key", Field, 0}, - {"RangeStmt.Range", Field, 20}, - {"RangeStmt.Tok", Field, 0}, - {"RangeStmt.TokPos", Field, 0}, - {"RangeStmt.Value", Field, 0}, - {"RangeStmt.X", Field, 0}, - {"ReturnStmt", Type, 0}, - {"ReturnStmt.Results", Field, 0}, - {"ReturnStmt.Return", Field, 0}, - {"SEND", Const, 0}, - {"Scope", Type, 0}, - {"Scope.Objects", Field, 0}, - {"Scope.Outer", Field, 0}, - {"SelectStmt", Type, 0}, - {"SelectStmt.Body", Field, 0}, - {"SelectStmt.Select", Field, 0}, - {"SelectorExpr", Type, 0}, - {"SelectorExpr.Sel", Field, 0}, - {"SelectorExpr.X", Field, 0}, - {"SendStmt", Type, 0}, - {"SendStmt.Arrow", Field, 0}, - {"SendStmt.Chan", Field, 0}, - {"SendStmt.Value", Field, 0}, - {"SliceExpr", Type, 0}, - {"SliceExpr.High", Field, 0}, - {"SliceExpr.Lbrack", Field, 0}, - {"SliceExpr.Low", Field, 0}, - {"SliceExpr.Max", Field, 2}, - {"SliceExpr.Rbrack", Field, 0}, - {"SliceExpr.Slice3", Field, 2}, - {"SliceExpr.X", Field, 0}, - {"SortImports", Func, 0}, - {"Spec", Type, 0}, - {"StarExpr", Type, 0}, - {"StarExpr.Star", Field, 0}, - {"StarExpr.X", Field, 0}, - {"Stmt", Type, 0}, - {"StructType", Type, 0}, - {"StructType.Fields", Field, 0}, - {"StructType.Incomplete", Field, 0}, - {"StructType.Struct", Field, 0}, - {"SwitchStmt", Type, 0}, - {"SwitchStmt.Body", Field, 0}, - {"SwitchStmt.Init", Field, 0}, - {"SwitchStmt.Switch", Field, 0}, - {"SwitchStmt.Tag", Field, 0}, - {"Typ", Const, 0}, - {"TypeAssertExpr", Type, 0}, - {"TypeAssertExpr.Lparen", Field, 2}, - {"TypeAssertExpr.Rparen", Field, 2}, - {"TypeAssertExpr.Type", Field, 0}, - {"TypeAssertExpr.X", Field, 0}, - {"TypeSpec", Type, 0}, - {"TypeSpec.Assign", Field, 9}, - {"TypeSpec.Comment", Field, 0}, - {"TypeSpec.Doc", Field, 0}, - {"TypeSpec.Name", Field, 0}, - {"TypeSpec.Type", Field, 0}, - {"TypeSpec.TypeParams", Field, 18}, - {"TypeSwitchStmt", Type, 0}, - {"TypeSwitchStmt.Assign", Field, 0}, - {"TypeSwitchStmt.Body", Field, 0}, - {"TypeSwitchStmt.Init", Field, 0}, - {"TypeSwitchStmt.Switch", Field, 0}, - {"UnaryExpr", Type, 0}, - {"UnaryExpr.Op", Field, 0}, - {"UnaryExpr.OpPos", Field, 0}, - {"UnaryExpr.X", Field, 0}, - {"Unparen", Func, 22}, - {"ValueSpec", Type, 0}, - {"ValueSpec.Comment", Field, 0}, - {"ValueSpec.Doc", Field, 0}, - {"ValueSpec.Names", Field, 0}, - {"ValueSpec.Type", Field, 0}, - {"ValueSpec.Values", Field, 0}, - {"Var", Const, 0}, - {"Visitor", Type, 0}, - {"Walk", Func, 0}, + {"(*ArrayType).End", Method, 0, ""}, + {"(*ArrayType).Pos", Method, 0, ""}, + {"(*AssignStmt).End", Method, 0, ""}, + {"(*AssignStmt).Pos", Method, 0, ""}, + {"(*BadDecl).End", Method, 0, ""}, + {"(*BadDecl).Pos", Method, 0, ""}, + {"(*BadExpr).End", Method, 0, ""}, + {"(*BadExpr).Pos", Method, 0, ""}, + {"(*BadStmt).End", Method, 0, ""}, + {"(*BadStmt).Pos", Method, 0, ""}, + {"(*BasicLit).End", Method, 0, ""}, + {"(*BasicLit).Pos", Method, 0, ""}, + {"(*BinaryExpr).End", Method, 0, ""}, + {"(*BinaryExpr).Pos", Method, 0, ""}, + {"(*BlockStmt).End", Method, 0, ""}, + {"(*BlockStmt).Pos", Method, 0, ""}, + {"(*BranchStmt).End", Method, 0, ""}, + {"(*BranchStmt).Pos", Method, 0, ""}, + {"(*CallExpr).End", Method, 0, ""}, + {"(*CallExpr).Pos", Method, 0, ""}, + {"(*CaseClause).End", Method, 0, ""}, + {"(*CaseClause).Pos", Method, 0, ""}, + {"(*ChanType).End", Method, 0, ""}, + {"(*ChanType).Pos", Method, 0, ""}, + {"(*CommClause).End", Method, 0, ""}, + {"(*CommClause).Pos", Method, 0, ""}, + {"(*Comment).End", Method, 0, ""}, + {"(*Comment).Pos", Method, 0, ""}, + {"(*CommentGroup).End", Method, 0, ""}, + {"(*CommentGroup).Pos", Method, 0, ""}, + {"(*CommentGroup).Text", Method, 0, ""}, + {"(*CompositeLit).End", Method, 0, ""}, + {"(*CompositeLit).Pos", Method, 0, ""}, + {"(*DeclStmt).End", Method, 0, ""}, + {"(*DeclStmt).Pos", Method, 0, ""}, + {"(*DeferStmt).End", Method, 0, ""}, + {"(*DeferStmt).Pos", Method, 0, ""}, + {"(*Ellipsis).End", Method, 0, ""}, + {"(*Ellipsis).Pos", Method, 0, ""}, + {"(*EmptyStmt).End", Method, 0, ""}, + {"(*EmptyStmt).Pos", Method, 0, ""}, + {"(*ExprStmt).End", Method, 0, ""}, + {"(*ExprStmt).Pos", Method, 0, ""}, + {"(*Field).End", Method, 0, ""}, + {"(*Field).Pos", Method, 0, ""}, + {"(*FieldList).End", Method, 0, ""}, + {"(*FieldList).NumFields", Method, 0, ""}, + {"(*FieldList).Pos", Method, 0, ""}, + {"(*File).End", Method, 0, ""}, + {"(*File).Pos", Method, 0, ""}, + {"(*ForStmt).End", Method, 0, ""}, + {"(*ForStmt).Pos", Method, 0, ""}, + {"(*FuncDecl).End", Method, 0, ""}, + {"(*FuncDecl).Pos", Method, 0, ""}, + {"(*FuncLit).End", Method, 0, ""}, + {"(*FuncLit).Pos", Method, 0, ""}, + {"(*FuncType).End", Method, 0, ""}, + {"(*FuncType).Pos", Method, 0, ""}, + {"(*GenDecl).End", Method, 0, ""}, + {"(*GenDecl).Pos", Method, 0, ""}, + {"(*GoStmt).End", Method, 0, ""}, + {"(*GoStmt).Pos", Method, 0, ""}, + {"(*Ident).End", Method, 0, ""}, + {"(*Ident).IsExported", Method, 0, ""}, + {"(*Ident).Pos", Method, 0, ""}, + {"(*Ident).String", Method, 0, ""}, + {"(*IfStmt).End", Method, 0, ""}, + {"(*IfStmt).Pos", Method, 0, ""}, + {"(*ImportSpec).End", Method, 0, ""}, + {"(*ImportSpec).Pos", Method, 0, ""}, + {"(*IncDecStmt).End", Method, 0, ""}, + {"(*IncDecStmt).Pos", Method, 0, ""}, + {"(*IndexExpr).End", Method, 0, ""}, + {"(*IndexExpr).Pos", Method, 0, ""}, + {"(*IndexListExpr).End", Method, 18, ""}, + {"(*IndexListExpr).Pos", Method, 18, ""}, + {"(*InterfaceType).End", Method, 0, ""}, + {"(*InterfaceType).Pos", Method, 0, ""}, + {"(*KeyValueExpr).End", Method, 0, ""}, + {"(*KeyValueExpr).Pos", Method, 0, ""}, + {"(*LabeledStmt).End", Method, 0, ""}, + {"(*LabeledStmt).Pos", Method, 0, ""}, + {"(*MapType).End", Method, 0, ""}, + {"(*MapType).Pos", Method, 0, ""}, + {"(*Object).Pos", Method, 0, ""}, + {"(*Package).End", Method, 0, ""}, + {"(*Package).Pos", Method, 0, ""}, + {"(*ParenExpr).End", Method, 0, ""}, + {"(*ParenExpr).Pos", Method, 0, ""}, + {"(*RangeStmt).End", Method, 0, ""}, + {"(*RangeStmt).Pos", Method, 0, ""}, + {"(*ReturnStmt).End", Method, 0, ""}, + {"(*ReturnStmt).Pos", Method, 0, ""}, + {"(*Scope).Insert", Method, 0, ""}, + {"(*Scope).Lookup", Method, 0, ""}, + {"(*Scope).String", Method, 0, ""}, + {"(*SelectStmt).End", Method, 0, ""}, + {"(*SelectStmt).Pos", Method, 0, ""}, + {"(*SelectorExpr).End", Method, 0, ""}, + {"(*SelectorExpr).Pos", Method, 0, ""}, + {"(*SendStmt).End", Method, 0, ""}, + {"(*SendStmt).Pos", Method, 0, ""}, + {"(*SliceExpr).End", Method, 0, ""}, + {"(*SliceExpr).Pos", Method, 0, ""}, + {"(*StarExpr).End", Method, 0, ""}, + {"(*StarExpr).Pos", Method, 0, ""}, + {"(*StructType).End", Method, 0, ""}, + {"(*StructType).Pos", Method, 0, ""}, + {"(*SwitchStmt).End", Method, 0, ""}, + {"(*SwitchStmt).Pos", Method, 0, ""}, + {"(*TypeAssertExpr).End", Method, 0, ""}, + {"(*TypeAssertExpr).Pos", Method, 0, ""}, + {"(*TypeSpec).End", Method, 0, ""}, + {"(*TypeSpec).Pos", Method, 0, ""}, + {"(*TypeSwitchStmt).End", Method, 0, ""}, + {"(*TypeSwitchStmt).Pos", Method, 0, ""}, + {"(*UnaryExpr).End", Method, 0, ""}, + {"(*UnaryExpr).Pos", Method, 0, ""}, + {"(*ValueSpec).End", Method, 0, ""}, + {"(*ValueSpec).Pos", Method, 0, ""}, + {"(CommentMap).Comments", Method, 1, ""}, + {"(CommentMap).Filter", Method, 1, ""}, + {"(CommentMap).String", Method, 1, ""}, + {"(CommentMap).Update", Method, 1, ""}, + {"(ObjKind).String", Method, 0, ""}, + {"ArrayType", Type, 0, ""}, + {"ArrayType.Elt", Field, 0, ""}, + {"ArrayType.Lbrack", Field, 0, ""}, + {"ArrayType.Len", Field, 0, ""}, + {"AssignStmt", Type, 0, ""}, + {"AssignStmt.Lhs", Field, 0, ""}, + {"AssignStmt.Rhs", Field, 0, ""}, + {"AssignStmt.Tok", Field, 0, ""}, + {"AssignStmt.TokPos", Field, 0, ""}, + {"Bad", Const, 0, ""}, + {"BadDecl", Type, 0, ""}, + {"BadDecl.From", Field, 0, ""}, + {"BadDecl.To", Field, 0, ""}, + {"BadExpr", Type, 0, ""}, + {"BadExpr.From", Field, 0, ""}, + {"BadExpr.To", Field, 0, ""}, + {"BadStmt", Type, 0, ""}, + {"BadStmt.From", Field, 0, ""}, + {"BadStmt.To", Field, 0, ""}, + {"BasicLit", Type, 0, ""}, + {"BasicLit.Kind", Field, 0, ""}, + {"BasicLit.Value", Field, 0, ""}, + {"BasicLit.ValuePos", Field, 0, ""}, + {"BinaryExpr", Type, 0, ""}, + {"BinaryExpr.Op", Field, 0, ""}, + {"BinaryExpr.OpPos", Field, 0, ""}, + {"BinaryExpr.X", Field, 0, ""}, + {"BinaryExpr.Y", Field, 0, ""}, + {"BlockStmt", Type, 0, ""}, + {"BlockStmt.Lbrace", Field, 0, ""}, + {"BlockStmt.List", Field, 0, ""}, + {"BlockStmt.Rbrace", Field, 0, ""}, + {"BranchStmt", Type, 0, ""}, + {"BranchStmt.Label", Field, 0, ""}, + {"BranchStmt.Tok", Field, 0, ""}, + {"BranchStmt.TokPos", Field, 0, ""}, + {"CallExpr", Type, 0, ""}, + {"CallExpr.Args", Field, 0, ""}, + {"CallExpr.Ellipsis", Field, 0, ""}, + {"CallExpr.Fun", Field, 0, ""}, + {"CallExpr.Lparen", Field, 0, ""}, + {"CallExpr.Rparen", Field, 0, ""}, + {"CaseClause", Type, 0, ""}, + {"CaseClause.Body", Field, 0, ""}, + {"CaseClause.Case", Field, 0, ""}, + {"CaseClause.Colon", Field, 0, ""}, + {"CaseClause.List", Field, 0, ""}, + {"ChanDir", Type, 0, ""}, + {"ChanType", Type, 0, ""}, + {"ChanType.Arrow", Field, 1, ""}, + {"ChanType.Begin", Field, 0, ""}, + {"ChanType.Dir", Field, 0, ""}, + {"ChanType.Value", Field, 0, ""}, + {"CommClause", Type, 0, ""}, + {"CommClause.Body", Field, 0, ""}, + {"CommClause.Case", Field, 0, ""}, + {"CommClause.Colon", Field, 0, ""}, + {"CommClause.Comm", Field, 0, ""}, + {"Comment", Type, 0, ""}, + {"Comment.Slash", Field, 0, ""}, + {"Comment.Text", Field, 0, ""}, + {"CommentGroup", Type, 0, ""}, + {"CommentGroup.List", Field, 0, ""}, + {"CommentMap", Type, 1, ""}, + {"CompositeLit", Type, 0, ""}, + {"CompositeLit.Elts", Field, 0, ""}, + {"CompositeLit.Incomplete", Field, 11, ""}, + {"CompositeLit.Lbrace", Field, 0, ""}, + {"CompositeLit.Rbrace", Field, 0, ""}, + {"CompositeLit.Type", Field, 0, ""}, + {"Con", Const, 0, ""}, + {"Decl", Type, 0, ""}, + {"DeclStmt", Type, 0, ""}, + {"DeclStmt.Decl", Field, 0, ""}, + {"DeferStmt", Type, 0, ""}, + {"DeferStmt.Call", Field, 0, ""}, + {"DeferStmt.Defer", Field, 0, ""}, + {"Ellipsis", Type, 0, ""}, + {"Ellipsis.Ellipsis", Field, 0, ""}, + {"Ellipsis.Elt", Field, 0, ""}, + {"EmptyStmt", Type, 0, ""}, + {"EmptyStmt.Implicit", Field, 5, ""}, + {"EmptyStmt.Semicolon", Field, 0, ""}, + {"Expr", Type, 0, ""}, + {"ExprStmt", Type, 0, ""}, + {"ExprStmt.X", Field, 0, ""}, + {"Field", Type, 0, ""}, + {"Field.Comment", Field, 0, ""}, + {"Field.Doc", Field, 0, ""}, + {"Field.Names", Field, 0, ""}, + {"Field.Tag", Field, 0, ""}, + {"Field.Type", Field, 0, ""}, + {"FieldFilter", Type, 0, ""}, + {"FieldList", Type, 0, ""}, + {"FieldList.Closing", Field, 0, ""}, + {"FieldList.List", Field, 0, ""}, + {"FieldList.Opening", Field, 0, ""}, + {"File", Type, 0, ""}, + {"File.Comments", Field, 0, ""}, + {"File.Decls", Field, 0, ""}, + {"File.Doc", Field, 0, ""}, + {"File.FileEnd", Field, 20, ""}, + {"File.FileStart", Field, 20, ""}, + {"File.GoVersion", Field, 21, ""}, + {"File.Imports", Field, 0, ""}, + {"File.Name", Field, 0, ""}, + {"File.Package", Field, 0, ""}, + {"File.Scope", Field, 0, ""}, + {"File.Unresolved", Field, 0, ""}, + {"FileExports", Func, 0, "func(src *File) bool"}, + {"Filter", Type, 0, ""}, + {"FilterDecl", Func, 0, "func(decl Decl, f Filter) bool"}, + {"FilterFile", Func, 0, "func(src *File, f Filter) bool"}, + {"FilterFuncDuplicates", Const, 0, ""}, + {"FilterImportDuplicates", Const, 0, ""}, + {"FilterPackage", Func, 0, "func(pkg *Package, f Filter) bool"}, + {"FilterUnassociatedComments", Const, 0, ""}, + {"ForStmt", Type, 0, ""}, + {"ForStmt.Body", Field, 0, ""}, + {"ForStmt.Cond", Field, 0, ""}, + {"ForStmt.For", Field, 0, ""}, + {"ForStmt.Init", Field, 0, ""}, + {"ForStmt.Post", Field, 0, ""}, + {"Fprint", Func, 0, "func(w io.Writer, fset *token.FileSet, x any, f FieldFilter) error"}, + {"Fun", Const, 0, ""}, + {"FuncDecl", Type, 0, ""}, + {"FuncDecl.Body", Field, 0, ""}, + {"FuncDecl.Doc", Field, 0, ""}, + {"FuncDecl.Name", Field, 0, ""}, + {"FuncDecl.Recv", Field, 0, ""}, + {"FuncDecl.Type", Field, 0, ""}, + {"FuncLit", Type, 0, ""}, + {"FuncLit.Body", Field, 0, ""}, + {"FuncLit.Type", Field, 0, ""}, + {"FuncType", Type, 0, ""}, + {"FuncType.Func", Field, 0, ""}, + {"FuncType.Params", Field, 0, ""}, + {"FuncType.Results", Field, 0, ""}, + {"FuncType.TypeParams", Field, 18, ""}, + {"GenDecl", Type, 0, ""}, + {"GenDecl.Doc", Field, 0, ""}, + {"GenDecl.Lparen", Field, 0, ""}, + {"GenDecl.Rparen", Field, 0, ""}, + {"GenDecl.Specs", Field, 0, ""}, + {"GenDecl.Tok", Field, 0, ""}, + {"GenDecl.TokPos", Field, 0, ""}, + {"GoStmt", Type, 0, ""}, + {"GoStmt.Call", Field, 0, ""}, + {"GoStmt.Go", Field, 0, ""}, + {"Ident", Type, 0, ""}, + {"Ident.Name", Field, 0, ""}, + {"Ident.NamePos", Field, 0, ""}, + {"Ident.Obj", Field, 0, ""}, + {"IfStmt", Type, 0, ""}, + {"IfStmt.Body", Field, 0, ""}, + {"IfStmt.Cond", Field, 0, ""}, + {"IfStmt.Else", Field, 0, ""}, + {"IfStmt.If", Field, 0, ""}, + {"IfStmt.Init", Field, 0, ""}, + {"ImportSpec", Type, 0, ""}, + {"ImportSpec.Comment", Field, 0, ""}, + {"ImportSpec.Doc", Field, 0, ""}, + {"ImportSpec.EndPos", Field, 0, ""}, + {"ImportSpec.Name", Field, 0, ""}, + {"ImportSpec.Path", Field, 0, ""}, + {"Importer", Type, 0, ""}, + {"IncDecStmt", Type, 0, ""}, + {"IncDecStmt.Tok", Field, 0, ""}, + {"IncDecStmt.TokPos", Field, 0, ""}, + {"IncDecStmt.X", Field, 0, ""}, + {"IndexExpr", Type, 0, ""}, + {"IndexExpr.Index", Field, 0, ""}, + {"IndexExpr.Lbrack", Field, 0, ""}, + {"IndexExpr.Rbrack", Field, 0, ""}, + {"IndexExpr.X", Field, 0, ""}, + {"IndexListExpr", Type, 18, ""}, + {"IndexListExpr.Indices", Field, 18, ""}, + {"IndexListExpr.Lbrack", Field, 18, ""}, + {"IndexListExpr.Rbrack", Field, 18, ""}, + {"IndexListExpr.X", Field, 18, ""}, + {"Inspect", Func, 0, "func(node Node, f func(Node) bool)"}, + {"InterfaceType", Type, 0, ""}, + {"InterfaceType.Incomplete", Field, 0, ""}, + {"InterfaceType.Interface", Field, 0, ""}, + {"InterfaceType.Methods", Field, 0, ""}, + {"IsExported", Func, 0, "func(name string) bool"}, + {"IsGenerated", Func, 21, "func(file *File) bool"}, + {"KeyValueExpr", Type, 0, ""}, + {"KeyValueExpr.Colon", Field, 0, ""}, + {"KeyValueExpr.Key", Field, 0, ""}, + {"KeyValueExpr.Value", Field, 0, ""}, + {"LabeledStmt", Type, 0, ""}, + {"LabeledStmt.Colon", Field, 0, ""}, + {"LabeledStmt.Label", Field, 0, ""}, + {"LabeledStmt.Stmt", Field, 0, ""}, + {"Lbl", Const, 0, ""}, + {"MapType", Type, 0, ""}, + {"MapType.Key", Field, 0, ""}, + {"MapType.Map", Field, 0, ""}, + {"MapType.Value", Field, 0, ""}, + {"MergeMode", Type, 0, ""}, + {"MergePackageFiles", Func, 0, "func(pkg *Package, mode MergeMode) *File"}, + {"NewCommentMap", Func, 1, "func(fset *token.FileSet, node Node, comments []*CommentGroup) CommentMap"}, + {"NewIdent", Func, 0, "func(name string) *Ident"}, + {"NewObj", Func, 0, "func(kind ObjKind, name string) *Object"}, + {"NewPackage", Func, 0, "func(fset *token.FileSet, files map[string]*File, importer Importer, universe *Scope) (*Package, error)"}, + {"NewScope", Func, 0, "func(outer *Scope) *Scope"}, + {"Node", Type, 0, ""}, + {"NotNilFilter", Func, 0, "func(_ string, v reflect.Value) bool"}, + {"ObjKind", Type, 0, ""}, + {"Object", Type, 0, ""}, + {"Object.Data", Field, 0, ""}, + {"Object.Decl", Field, 0, ""}, + {"Object.Kind", Field, 0, ""}, + {"Object.Name", Field, 0, ""}, + {"Object.Type", Field, 0, ""}, + {"Package", Type, 0, ""}, + {"Package.Files", Field, 0, ""}, + {"Package.Imports", Field, 0, ""}, + {"Package.Name", Field, 0, ""}, + {"Package.Scope", Field, 0, ""}, + {"PackageExports", Func, 0, "func(pkg *Package) bool"}, + {"ParenExpr", Type, 0, ""}, + {"ParenExpr.Lparen", Field, 0, ""}, + {"ParenExpr.Rparen", Field, 0, ""}, + {"ParenExpr.X", Field, 0, ""}, + {"Pkg", Const, 0, ""}, + {"Preorder", Func, 23, "func(root Node) iter.Seq[Node]"}, + {"Print", Func, 0, "func(fset *token.FileSet, x any) error"}, + {"RECV", Const, 0, ""}, + {"RangeStmt", Type, 0, ""}, + {"RangeStmt.Body", Field, 0, ""}, + {"RangeStmt.For", Field, 0, ""}, + {"RangeStmt.Key", Field, 0, ""}, + {"RangeStmt.Range", Field, 20, ""}, + {"RangeStmt.Tok", Field, 0, ""}, + {"RangeStmt.TokPos", Field, 0, ""}, + {"RangeStmt.Value", Field, 0, ""}, + {"RangeStmt.X", Field, 0, ""}, + {"ReturnStmt", Type, 0, ""}, + {"ReturnStmt.Results", Field, 0, ""}, + {"ReturnStmt.Return", Field, 0, ""}, + {"SEND", Const, 0, ""}, + {"Scope", Type, 0, ""}, + {"Scope.Objects", Field, 0, ""}, + {"Scope.Outer", Field, 0, ""}, + {"SelectStmt", Type, 0, ""}, + {"SelectStmt.Body", Field, 0, ""}, + {"SelectStmt.Select", Field, 0, ""}, + {"SelectorExpr", Type, 0, ""}, + {"SelectorExpr.Sel", Field, 0, ""}, + {"SelectorExpr.X", Field, 0, ""}, + {"SendStmt", Type, 0, ""}, + {"SendStmt.Arrow", Field, 0, ""}, + {"SendStmt.Chan", Field, 0, ""}, + {"SendStmt.Value", Field, 0, ""}, + {"SliceExpr", Type, 0, ""}, + {"SliceExpr.High", Field, 0, ""}, + {"SliceExpr.Lbrack", Field, 0, ""}, + {"SliceExpr.Low", Field, 0, ""}, + {"SliceExpr.Max", Field, 2, ""}, + {"SliceExpr.Rbrack", Field, 0, ""}, + {"SliceExpr.Slice3", Field, 2, ""}, + {"SliceExpr.X", Field, 0, ""}, + {"SortImports", Func, 0, "func(fset *token.FileSet, f *File)"}, + {"Spec", Type, 0, ""}, + {"StarExpr", Type, 0, ""}, + {"StarExpr.Star", Field, 0, ""}, + {"StarExpr.X", Field, 0, ""}, + {"Stmt", Type, 0, ""}, + {"StructType", Type, 0, ""}, + {"StructType.Fields", Field, 0, ""}, + {"StructType.Incomplete", Field, 0, ""}, + {"StructType.Struct", Field, 0, ""}, + {"SwitchStmt", Type, 0, ""}, + {"SwitchStmt.Body", Field, 0, ""}, + {"SwitchStmt.Init", Field, 0, ""}, + {"SwitchStmt.Switch", Field, 0, ""}, + {"SwitchStmt.Tag", Field, 0, ""}, + {"Typ", Const, 0, ""}, + {"TypeAssertExpr", Type, 0, ""}, + {"TypeAssertExpr.Lparen", Field, 2, ""}, + {"TypeAssertExpr.Rparen", Field, 2, ""}, + {"TypeAssertExpr.Type", Field, 0, ""}, + {"TypeAssertExpr.X", Field, 0, ""}, + {"TypeSpec", Type, 0, ""}, + {"TypeSpec.Assign", Field, 9, ""}, + {"TypeSpec.Comment", Field, 0, ""}, + {"TypeSpec.Doc", Field, 0, ""}, + {"TypeSpec.Name", Field, 0, ""}, + {"TypeSpec.Type", Field, 0, ""}, + {"TypeSpec.TypeParams", Field, 18, ""}, + {"TypeSwitchStmt", Type, 0, ""}, + {"TypeSwitchStmt.Assign", Field, 0, ""}, + {"TypeSwitchStmt.Body", Field, 0, ""}, + {"TypeSwitchStmt.Init", Field, 0, ""}, + {"TypeSwitchStmt.Switch", Field, 0, ""}, + {"UnaryExpr", Type, 0, ""}, + {"UnaryExpr.Op", Field, 0, ""}, + {"UnaryExpr.OpPos", Field, 0, ""}, + {"UnaryExpr.X", Field, 0, ""}, + {"Unparen", Func, 22, "func(e Expr) Expr"}, + {"ValueSpec", Type, 0, ""}, + {"ValueSpec.Comment", Field, 0, ""}, + {"ValueSpec.Doc", Field, 0, ""}, + {"ValueSpec.Names", Field, 0, ""}, + {"ValueSpec.Type", Field, 0, ""}, + {"ValueSpec.Values", Field, 0, ""}, + {"Var", Const, 0, ""}, + {"Visitor", Type, 0, ""}, + {"Walk", Func, 0, "func(v Visitor, node Node)"}, }, "go/build": { - {"(*Context).Import", Method, 0}, - {"(*Context).ImportDir", Method, 0}, - {"(*Context).MatchFile", Method, 2}, - {"(*Context).SrcDirs", Method, 0}, - {"(*MultiplePackageError).Error", Method, 4}, - {"(*NoGoError).Error", Method, 0}, - {"(*Package).IsCommand", Method, 0}, - {"AllowBinary", Const, 0}, - {"ArchChar", Func, 0}, - {"Context", Type, 0}, - {"Context.BuildTags", Field, 0}, - {"Context.CgoEnabled", Field, 0}, - {"Context.Compiler", Field, 0}, - {"Context.Dir", Field, 14}, - {"Context.GOARCH", Field, 0}, - {"Context.GOOS", Field, 0}, - {"Context.GOPATH", Field, 0}, - {"Context.GOROOT", Field, 0}, - {"Context.HasSubdir", Field, 0}, - {"Context.InstallSuffix", Field, 1}, - {"Context.IsAbsPath", Field, 0}, - {"Context.IsDir", Field, 0}, - {"Context.JoinPath", Field, 0}, - {"Context.OpenFile", Field, 0}, - {"Context.ReadDir", Field, 0}, - {"Context.ReleaseTags", Field, 1}, - {"Context.SplitPathList", Field, 0}, - {"Context.ToolTags", Field, 17}, - {"Context.UseAllFiles", Field, 0}, - {"Default", Var, 0}, - {"Directive", Type, 21}, - {"Directive.Pos", Field, 21}, - {"Directive.Text", Field, 21}, - {"FindOnly", Const, 0}, - {"IgnoreVendor", Const, 6}, - {"Import", Func, 0}, - {"ImportComment", Const, 4}, - {"ImportDir", Func, 0}, - {"ImportMode", Type, 0}, - {"IsLocalImport", Func, 0}, - {"MultiplePackageError", Type, 4}, - {"MultiplePackageError.Dir", Field, 4}, - {"MultiplePackageError.Files", Field, 4}, - {"MultiplePackageError.Packages", Field, 4}, - {"NoGoError", Type, 0}, - {"NoGoError.Dir", Field, 0}, - {"Package", Type, 0}, - {"Package.AllTags", Field, 2}, - {"Package.BinDir", Field, 0}, - {"Package.BinaryOnly", Field, 7}, - {"Package.CFiles", Field, 0}, - {"Package.CXXFiles", Field, 2}, - {"Package.CgoCFLAGS", Field, 0}, - {"Package.CgoCPPFLAGS", Field, 2}, - {"Package.CgoCXXFLAGS", Field, 2}, - {"Package.CgoFFLAGS", Field, 7}, - {"Package.CgoFiles", Field, 0}, - {"Package.CgoLDFLAGS", Field, 0}, - {"Package.CgoPkgConfig", Field, 0}, - {"Package.ConflictDir", Field, 2}, - {"Package.Dir", Field, 0}, - {"Package.Directives", Field, 21}, - {"Package.Doc", Field, 0}, - {"Package.EmbedPatternPos", Field, 16}, - {"Package.EmbedPatterns", Field, 16}, - {"Package.FFiles", Field, 7}, - {"Package.GoFiles", Field, 0}, - {"Package.Goroot", Field, 0}, - {"Package.HFiles", Field, 0}, - {"Package.IgnoredGoFiles", Field, 1}, - {"Package.IgnoredOtherFiles", Field, 16}, - {"Package.ImportComment", Field, 4}, - {"Package.ImportPath", Field, 0}, - {"Package.ImportPos", Field, 0}, - {"Package.Imports", Field, 0}, - {"Package.InvalidGoFiles", Field, 6}, - {"Package.MFiles", Field, 3}, - {"Package.Name", Field, 0}, - {"Package.PkgObj", Field, 0}, - {"Package.PkgRoot", Field, 0}, - {"Package.PkgTargetRoot", Field, 5}, - {"Package.Root", Field, 0}, - {"Package.SFiles", Field, 0}, - {"Package.SrcRoot", Field, 0}, - {"Package.SwigCXXFiles", Field, 1}, - {"Package.SwigFiles", Field, 1}, - {"Package.SysoFiles", Field, 0}, - {"Package.TestDirectives", Field, 21}, - {"Package.TestEmbedPatternPos", Field, 16}, - {"Package.TestEmbedPatterns", Field, 16}, - {"Package.TestGoFiles", Field, 0}, - {"Package.TestImportPos", Field, 0}, - {"Package.TestImports", Field, 0}, - {"Package.XTestDirectives", Field, 21}, - {"Package.XTestEmbedPatternPos", Field, 16}, - {"Package.XTestEmbedPatterns", Field, 16}, - {"Package.XTestGoFiles", Field, 0}, - {"Package.XTestImportPos", Field, 0}, - {"Package.XTestImports", Field, 0}, - {"ToolDir", Var, 0}, + {"(*Context).Import", Method, 0, ""}, + {"(*Context).ImportDir", Method, 0, ""}, + {"(*Context).MatchFile", Method, 2, ""}, + {"(*Context).SrcDirs", Method, 0, ""}, + {"(*MultiplePackageError).Error", Method, 4, ""}, + {"(*NoGoError).Error", Method, 0, ""}, + {"(*Package).IsCommand", Method, 0, ""}, + {"AllowBinary", Const, 0, ""}, + {"ArchChar", Func, 0, "func(goarch string) (string, error)"}, + {"Context", Type, 0, ""}, + {"Context.BuildTags", Field, 0, ""}, + {"Context.CgoEnabled", Field, 0, ""}, + {"Context.Compiler", Field, 0, ""}, + {"Context.Dir", Field, 14, ""}, + {"Context.GOARCH", Field, 0, ""}, + {"Context.GOOS", Field, 0, ""}, + {"Context.GOPATH", Field, 0, ""}, + {"Context.GOROOT", Field, 0, ""}, + {"Context.HasSubdir", Field, 0, ""}, + {"Context.InstallSuffix", Field, 1, ""}, + {"Context.IsAbsPath", Field, 0, ""}, + {"Context.IsDir", Field, 0, ""}, + {"Context.JoinPath", Field, 0, ""}, + {"Context.OpenFile", Field, 0, ""}, + {"Context.ReadDir", Field, 0, ""}, + {"Context.ReleaseTags", Field, 1, ""}, + {"Context.SplitPathList", Field, 0, ""}, + {"Context.ToolTags", Field, 17, ""}, + {"Context.UseAllFiles", Field, 0, ""}, + {"Default", Var, 0, ""}, + {"Directive", Type, 21, ""}, + {"Directive.Pos", Field, 21, ""}, + {"Directive.Text", Field, 21, ""}, + {"FindOnly", Const, 0, ""}, + {"IgnoreVendor", Const, 6, ""}, + {"Import", Func, 0, "func(path string, srcDir string, mode ImportMode) (*Package, error)"}, + {"ImportComment", Const, 4, ""}, + {"ImportDir", Func, 0, "func(dir string, mode ImportMode) (*Package, error)"}, + {"ImportMode", Type, 0, ""}, + {"IsLocalImport", Func, 0, "func(path string) bool"}, + {"MultiplePackageError", Type, 4, ""}, + {"MultiplePackageError.Dir", Field, 4, ""}, + {"MultiplePackageError.Files", Field, 4, ""}, + {"MultiplePackageError.Packages", Field, 4, ""}, + {"NoGoError", Type, 0, ""}, + {"NoGoError.Dir", Field, 0, ""}, + {"Package", Type, 0, ""}, + {"Package.AllTags", Field, 2, ""}, + {"Package.BinDir", Field, 0, ""}, + {"Package.BinaryOnly", Field, 7, ""}, + {"Package.CFiles", Field, 0, ""}, + {"Package.CXXFiles", Field, 2, ""}, + {"Package.CgoCFLAGS", Field, 0, ""}, + {"Package.CgoCPPFLAGS", Field, 2, ""}, + {"Package.CgoCXXFLAGS", Field, 2, ""}, + {"Package.CgoFFLAGS", Field, 7, ""}, + {"Package.CgoFiles", Field, 0, ""}, + {"Package.CgoLDFLAGS", Field, 0, ""}, + {"Package.CgoPkgConfig", Field, 0, ""}, + {"Package.ConflictDir", Field, 2, ""}, + {"Package.Dir", Field, 0, ""}, + {"Package.Directives", Field, 21, ""}, + {"Package.Doc", Field, 0, ""}, + {"Package.EmbedPatternPos", Field, 16, ""}, + {"Package.EmbedPatterns", Field, 16, ""}, + {"Package.FFiles", Field, 7, ""}, + {"Package.GoFiles", Field, 0, ""}, + {"Package.Goroot", Field, 0, ""}, + {"Package.HFiles", Field, 0, ""}, + {"Package.IgnoredGoFiles", Field, 1, ""}, + {"Package.IgnoredOtherFiles", Field, 16, ""}, + {"Package.ImportComment", Field, 4, ""}, + {"Package.ImportPath", Field, 0, ""}, + {"Package.ImportPos", Field, 0, ""}, + {"Package.Imports", Field, 0, ""}, + {"Package.InvalidGoFiles", Field, 6, ""}, + {"Package.MFiles", Field, 3, ""}, + {"Package.Name", Field, 0, ""}, + {"Package.PkgObj", Field, 0, ""}, + {"Package.PkgRoot", Field, 0, ""}, + {"Package.PkgTargetRoot", Field, 5, ""}, + {"Package.Root", Field, 0, ""}, + {"Package.SFiles", Field, 0, ""}, + {"Package.SrcRoot", Field, 0, ""}, + {"Package.SwigCXXFiles", Field, 1, ""}, + {"Package.SwigFiles", Field, 1, ""}, + {"Package.SysoFiles", Field, 0, ""}, + {"Package.TestDirectives", Field, 21, ""}, + {"Package.TestEmbedPatternPos", Field, 16, ""}, + {"Package.TestEmbedPatterns", Field, 16, ""}, + {"Package.TestGoFiles", Field, 0, ""}, + {"Package.TestImportPos", Field, 0, ""}, + {"Package.TestImports", Field, 0, ""}, + {"Package.XTestDirectives", Field, 21, ""}, + {"Package.XTestEmbedPatternPos", Field, 16, ""}, + {"Package.XTestEmbedPatterns", Field, 16, ""}, + {"Package.XTestGoFiles", Field, 0, ""}, + {"Package.XTestImportPos", Field, 0, ""}, + {"Package.XTestImports", Field, 0, ""}, + {"ToolDir", Var, 0, ""}, }, "go/build/constraint": { - {"(*AndExpr).Eval", Method, 16}, - {"(*AndExpr).String", Method, 16}, - {"(*NotExpr).Eval", Method, 16}, - {"(*NotExpr).String", Method, 16}, - {"(*OrExpr).Eval", Method, 16}, - {"(*OrExpr).String", Method, 16}, - {"(*SyntaxError).Error", Method, 16}, - {"(*TagExpr).Eval", Method, 16}, - {"(*TagExpr).String", Method, 16}, - {"AndExpr", Type, 16}, - {"AndExpr.X", Field, 16}, - {"AndExpr.Y", Field, 16}, - {"Expr", Type, 16}, - {"GoVersion", Func, 21}, - {"IsGoBuild", Func, 16}, - {"IsPlusBuild", Func, 16}, - {"NotExpr", Type, 16}, - {"NotExpr.X", Field, 16}, - {"OrExpr", Type, 16}, - {"OrExpr.X", Field, 16}, - {"OrExpr.Y", Field, 16}, - {"Parse", Func, 16}, - {"PlusBuildLines", Func, 16}, - {"SyntaxError", Type, 16}, - {"SyntaxError.Err", Field, 16}, - {"SyntaxError.Offset", Field, 16}, - {"TagExpr", Type, 16}, - {"TagExpr.Tag", Field, 16}, + {"(*AndExpr).Eval", Method, 16, ""}, + {"(*AndExpr).String", Method, 16, ""}, + {"(*NotExpr).Eval", Method, 16, ""}, + {"(*NotExpr).String", Method, 16, ""}, + {"(*OrExpr).Eval", Method, 16, ""}, + {"(*OrExpr).String", Method, 16, ""}, + {"(*SyntaxError).Error", Method, 16, ""}, + {"(*TagExpr).Eval", Method, 16, ""}, + {"(*TagExpr).String", Method, 16, ""}, + {"AndExpr", Type, 16, ""}, + {"AndExpr.X", Field, 16, ""}, + {"AndExpr.Y", Field, 16, ""}, + {"Expr", Type, 16, ""}, + {"GoVersion", Func, 21, "func(x Expr) string"}, + {"IsGoBuild", Func, 16, "func(line string) bool"}, + {"IsPlusBuild", Func, 16, "func(line string) bool"}, + {"NotExpr", Type, 16, ""}, + {"NotExpr.X", Field, 16, ""}, + {"OrExpr", Type, 16, ""}, + {"OrExpr.X", Field, 16, ""}, + {"OrExpr.Y", Field, 16, ""}, + {"Parse", Func, 16, "func(line string) (Expr, error)"}, + {"PlusBuildLines", Func, 16, "func(x Expr) ([]string, error)"}, + {"SyntaxError", Type, 16, ""}, + {"SyntaxError.Err", Field, 16, ""}, + {"SyntaxError.Offset", Field, 16, ""}, + {"TagExpr", Type, 16, ""}, + {"TagExpr.Tag", Field, 16, ""}, }, "go/constant": { - {"(Kind).String", Method, 18}, - {"BinaryOp", Func, 5}, - {"BitLen", Func, 5}, - {"Bool", Const, 5}, - {"BoolVal", Func, 5}, - {"Bytes", Func, 5}, - {"Compare", Func, 5}, - {"Complex", Const, 5}, - {"Denom", Func, 5}, - {"Float", Const, 5}, - {"Float32Val", Func, 5}, - {"Float64Val", Func, 5}, - {"Imag", Func, 5}, - {"Int", Const, 5}, - {"Int64Val", Func, 5}, - {"Kind", Type, 5}, - {"Make", Func, 13}, - {"MakeBool", Func, 5}, - {"MakeFloat64", Func, 5}, - {"MakeFromBytes", Func, 5}, - {"MakeFromLiteral", Func, 5}, - {"MakeImag", Func, 5}, - {"MakeInt64", Func, 5}, - {"MakeString", Func, 5}, - {"MakeUint64", Func, 5}, - {"MakeUnknown", Func, 5}, - {"Num", Func, 5}, - {"Real", Func, 5}, - {"Shift", Func, 5}, - {"Sign", Func, 5}, - {"String", Const, 5}, - {"StringVal", Func, 5}, - {"ToComplex", Func, 6}, - {"ToFloat", Func, 6}, - {"ToInt", Func, 6}, - {"Uint64Val", Func, 5}, - {"UnaryOp", Func, 5}, - {"Unknown", Const, 5}, - {"Val", Func, 13}, - {"Value", Type, 5}, + {"(Kind).String", Method, 18, ""}, + {"BinaryOp", Func, 5, "func(x_ Value, op token.Token, y_ Value) Value"}, + {"BitLen", Func, 5, "func(x Value) int"}, + {"Bool", Const, 5, ""}, + {"BoolVal", Func, 5, "func(x Value) bool"}, + {"Bytes", Func, 5, "func(x Value) []byte"}, + {"Compare", Func, 5, "func(x_ Value, op token.Token, y_ Value) bool"}, + {"Complex", Const, 5, ""}, + {"Denom", Func, 5, "func(x Value) Value"}, + {"Float", Const, 5, ""}, + {"Float32Val", Func, 5, "func(x Value) (float32, bool)"}, + {"Float64Val", Func, 5, "func(x Value) (float64, bool)"}, + {"Imag", Func, 5, "func(x Value) Value"}, + {"Int", Const, 5, ""}, + {"Int64Val", Func, 5, "func(x Value) (int64, bool)"}, + {"Kind", Type, 5, ""}, + {"Make", Func, 13, "func(x any) Value"}, + {"MakeBool", Func, 5, "func(b bool) Value"}, + {"MakeFloat64", Func, 5, "func(x float64) Value"}, + {"MakeFromBytes", Func, 5, "func(bytes []byte) Value"}, + {"MakeFromLiteral", Func, 5, "func(lit string, tok token.Token, zero uint) Value"}, + {"MakeImag", Func, 5, "func(x Value) Value"}, + {"MakeInt64", Func, 5, "func(x int64) Value"}, + {"MakeString", Func, 5, "func(s string) Value"}, + {"MakeUint64", Func, 5, "func(x uint64) Value"}, + {"MakeUnknown", Func, 5, "func() Value"}, + {"Num", Func, 5, "func(x Value) Value"}, + {"Real", Func, 5, "func(x Value) Value"}, + {"Shift", Func, 5, "func(x Value, op token.Token, s uint) Value"}, + {"Sign", Func, 5, "func(x Value) int"}, + {"String", Const, 5, ""}, + {"StringVal", Func, 5, "func(x Value) string"}, + {"ToComplex", Func, 6, "func(x Value) Value"}, + {"ToFloat", Func, 6, "func(x Value) Value"}, + {"ToInt", Func, 6, "func(x Value) Value"}, + {"Uint64Val", Func, 5, "func(x Value) (uint64, bool)"}, + {"UnaryOp", Func, 5, "func(op token.Token, y Value, prec uint) Value"}, + {"Unknown", Const, 5, ""}, + {"Val", Func, 13, "func(x Value) any"}, + {"Value", Type, 5, ""}, }, "go/doc": { - {"(*Package).Filter", Method, 0}, - {"(*Package).HTML", Method, 19}, - {"(*Package).Markdown", Method, 19}, - {"(*Package).Parser", Method, 19}, - {"(*Package).Printer", Method, 19}, - {"(*Package).Synopsis", Method, 19}, - {"(*Package).Text", Method, 19}, - {"AllDecls", Const, 0}, - {"AllMethods", Const, 0}, - {"Example", Type, 0}, - {"Example.Code", Field, 0}, - {"Example.Comments", Field, 0}, - {"Example.Doc", Field, 0}, - {"Example.EmptyOutput", Field, 1}, - {"Example.Name", Field, 0}, - {"Example.Order", Field, 1}, - {"Example.Output", Field, 0}, - {"Example.Play", Field, 1}, - {"Example.Suffix", Field, 14}, - {"Example.Unordered", Field, 7}, - {"Examples", Func, 0}, - {"Filter", Type, 0}, - {"Func", Type, 0}, - {"Func.Decl", Field, 0}, - {"Func.Doc", Field, 0}, - {"Func.Examples", Field, 14}, - {"Func.Level", Field, 0}, - {"Func.Name", Field, 0}, - {"Func.Orig", Field, 0}, - {"Func.Recv", Field, 0}, - {"IllegalPrefixes", Var, 1}, - {"IsPredeclared", Func, 8}, - {"Mode", Type, 0}, - {"New", Func, 0}, - {"NewFromFiles", Func, 14}, - {"Note", Type, 1}, - {"Note.Body", Field, 1}, - {"Note.End", Field, 1}, - {"Note.Pos", Field, 1}, - {"Note.UID", Field, 1}, - {"Package", Type, 0}, - {"Package.Bugs", Field, 0}, - {"Package.Consts", Field, 0}, - {"Package.Doc", Field, 0}, - {"Package.Examples", Field, 14}, - {"Package.Filenames", Field, 0}, - {"Package.Funcs", Field, 0}, - {"Package.ImportPath", Field, 0}, - {"Package.Imports", Field, 0}, - {"Package.Name", Field, 0}, - {"Package.Notes", Field, 1}, - {"Package.Types", Field, 0}, - {"Package.Vars", Field, 0}, - {"PreserveAST", Const, 12}, - {"Synopsis", Func, 0}, - {"ToHTML", Func, 0}, - {"ToText", Func, 0}, - {"Type", Type, 0}, - {"Type.Consts", Field, 0}, - {"Type.Decl", Field, 0}, - {"Type.Doc", Field, 0}, - {"Type.Examples", Field, 14}, - {"Type.Funcs", Field, 0}, - {"Type.Methods", Field, 0}, - {"Type.Name", Field, 0}, - {"Type.Vars", Field, 0}, - {"Value", Type, 0}, - {"Value.Decl", Field, 0}, - {"Value.Doc", Field, 0}, - {"Value.Names", Field, 0}, + {"(*Package).Filter", Method, 0, ""}, + {"(*Package).HTML", Method, 19, ""}, + {"(*Package).Markdown", Method, 19, ""}, + {"(*Package).Parser", Method, 19, ""}, + {"(*Package).Printer", Method, 19, ""}, + {"(*Package).Synopsis", Method, 19, ""}, + {"(*Package).Text", Method, 19, ""}, + {"AllDecls", Const, 0, ""}, + {"AllMethods", Const, 0, ""}, + {"Example", Type, 0, ""}, + {"Example.Code", Field, 0, ""}, + {"Example.Comments", Field, 0, ""}, + {"Example.Doc", Field, 0, ""}, + {"Example.EmptyOutput", Field, 1, ""}, + {"Example.Name", Field, 0, ""}, + {"Example.Order", Field, 1, ""}, + {"Example.Output", Field, 0, ""}, + {"Example.Play", Field, 1, ""}, + {"Example.Suffix", Field, 14, ""}, + {"Example.Unordered", Field, 7, ""}, + {"Examples", Func, 0, "func(testFiles ...*ast.File) []*Example"}, + {"Filter", Type, 0, ""}, + {"Func", Type, 0, ""}, + {"Func.Decl", Field, 0, ""}, + {"Func.Doc", Field, 0, ""}, + {"Func.Examples", Field, 14, ""}, + {"Func.Level", Field, 0, ""}, + {"Func.Name", Field, 0, ""}, + {"Func.Orig", Field, 0, ""}, + {"Func.Recv", Field, 0, ""}, + {"IllegalPrefixes", Var, 1, ""}, + {"IsPredeclared", Func, 8, "func(s string) bool"}, + {"Mode", Type, 0, ""}, + {"New", Func, 0, "func(pkg *ast.Package, importPath string, mode Mode) *Package"}, + {"NewFromFiles", Func, 14, "func(fset *token.FileSet, files []*ast.File, importPath string, opts ...any) (*Package, error)"}, + {"Note", Type, 1, ""}, + {"Note.Body", Field, 1, ""}, + {"Note.End", Field, 1, ""}, + {"Note.Pos", Field, 1, ""}, + {"Note.UID", Field, 1, ""}, + {"Package", Type, 0, ""}, + {"Package.Bugs", Field, 0, ""}, + {"Package.Consts", Field, 0, ""}, + {"Package.Doc", Field, 0, ""}, + {"Package.Examples", Field, 14, ""}, + {"Package.Filenames", Field, 0, ""}, + {"Package.Funcs", Field, 0, ""}, + {"Package.ImportPath", Field, 0, ""}, + {"Package.Imports", Field, 0, ""}, + {"Package.Name", Field, 0, ""}, + {"Package.Notes", Field, 1, ""}, + {"Package.Types", Field, 0, ""}, + {"Package.Vars", Field, 0, ""}, + {"PreserveAST", Const, 12, ""}, + {"Synopsis", Func, 0, "func(text string) string"}, + {"ToHTML", Func, 0, "func(w io.Writer, text string, words map[string]string)"}, + {"ToText", Func, 0, "func(w io.Writer, text string, prefix string, codePrefix string, width int)"}, + {"Type", Type, 0, ""}, + {"Type.Consts", Field, 0, ""}, + {"Type.Decl", Field, 0, ""}, + {"Type.Doc", Field, 0, ""}, + {"Type.Examples", Field, 14, ""}, + {"Type.Funcs", Field, 0, ""}, + {"Type.Methods", Field, 0, ""}, + {"Type.Name", Field, 0, ""}, + {"Type.Vars", Field, 0, ""}, + {"Value", Type, 0, ""}, + {"Value.Decl", Field, 0, ""}, + {"Value.Doc", Field, 0, ""}, + {"Value.Names", Field, 0, ""}, }, "go/doc/comment": { - {"(*DocLink).DefaultURL", Method, 19}, - {"(*Heading).DefaultID", Method, 19}, - {"(*List).BlankBefore", Method, 19}, - {"(*List).BlankBetween", Method, 19}, - {"(*Parser).Parse", Method, 19}, - {"(*Printer).Comment", Method, 19}, - {"(*Printer).HTML", Method, 19}, - {"(*Printer).Markdown", Method, 19}, - {"(*Printer).Text", Method, 19}, - {"Block", Type, 19}, - {"Code", Type, 19}, - {"Code.Text", Field, 19}, - {"DefaultLookupPackage", Func, 19}, - {"Doc", Type, 19}, - {"Doc.Content", Field, 19}, - {"Doc.Links", Field, 19}, - {"DocLink", Type, 19}, - {"DocLink.ImportPath", Field, 19}, - {"DocLink.Name", Field, 19}, - {"DocLink.Recv", Field, 19}, - {"DocLink.Text", Field, 19}, - {"Heading", Type, 19}, - {"Heading.Text", Field, 19}, - {"Italic", Type, 19}, - {"Link", Type, 19}, - {"Link.Auto", Field, 19}, - {"Link.Text", Field, 19}, - {"Link.URL", Field, 19}, - {"LinkDef", Type, 19}, - {"LinkDef.Text", Field, 19}, - {"LinkDef.URL", Field, 19}, - {"LinkDef.Used", Field, 19}, - {"List", Type, 19}, - {"List.ForceBlankBefore", Field, 19}, - {"List.ForceBlankBetween", Field, 19}, - {"List.Items", Field, 19}, - {"ListItem", Type, 19}, - {"ListItem.Content", Field, 19}, - {"ListItem.Number", Field, 19}, - {"Paragraph", Type, 19}, - {"Paragraph.Text", Field, 19}, - {"Parser", Type, 19}, - {"Parser.LookupPackage", Field, 19}, - {"Parser.LookupSym", Field, 19}, - {"Parser.Words", Field, 19}, - {"Plain", Type, 19}, - {"Printer", Type, 19}, - {"Printer.DocLinkBaseURL", Field, 19}, - {"Printer.DocLinkURL", Field, 19}, - {"Printer.HeadingID", Field, 19}, - {"Printer.HeadingLevel", Field, 19}, - {"Printer.TextCodePrefix", Field, 19}, - {"Printer.TextPrefix", Field, 19}, - {"Printer.TextWidth", Field, 19}, - {"Text", Type, 19}, + {"(*DocLink).DefaultURL", Method, 19, ""}, + {"(*Heading).DefaultID", Method, 19, ""}, + {"(*List).BlankBefore", Method, 19, ""}, + {"(*List).BlankBetween", Method, 19, ""}, + {"(*Parser).Parse", Method, 19, ""}, + {"(*Printer).Comment", Method, 19, ""}, + {"(*Printer).HTML", Method, 19, ""}, + {"(*Printer).Markdown", Method, 19, ""}, + {"(*Printer).Text", Method, 19, ""}, + {"Block", Type, 19, ""}, + {"Code", Type, 19, ""}, + {"Code.Text", Field, 19, ""}, + {"DefaultLookupPackage", Func, 19, "func(name string) (importPath string, ok bool)"}, + {"Doc", Type, 19, ""}, + {"Doc.Content", Field, 19, ""}, + {"Doc.Links", Field, 19, ""}, + {"DocLink", Type, 19, ""}, + {"DocLink.ImportPath", Field, 19, ""}, + {"DocLink.Name", Field, 19, ""}, + {"DocLink.Recv", Field, 19, ""}, + {"DocLink.Text", Field, 19, ""}, + {"Heading", Type, 19, ""}, + {"Heading.Text", Field, 19, ""}, + {"Italic", Type, 19, ""}, + {"Link", Type, 19, ""}, + {"Link.Auto", Field, 19, ""}, + {"Link.Text", Field, 19, ""}, + {"Link.URL", Field, 19, ""}, + {"LinkDef", Type, 19, ""}, + {"LinkDef.Text", Field, 19, ""}, + {"LinkDef.URL", Field, 19, ""}, + {"LinkDef.Used", Field, 19, ""}, + {"List", Type, 19, ""}, + {"List.ForceBlankBefore", Field, 19, ""}, + {"List.ForceBlankBetween", Field, 19, ""}, + {"List.Items", Field, 19, ""}, + {"ListItem", Type, 19, ""}, + {"ListItem.Content", Field, 19, ""}, + {"ListItem.Number", Field, 19, ""}, + {"Paragraph", Type, 19, ""}, + {"Paragraph.Text", Field, 19, ""}, + {"Parser", Type, 19, ""}, + {"Parser.LookupPackage", Field, 19, ""}, + {"Parser.LookupSym", Field, 19, ""}, + {"Parser.Words", Field, 19, ""}, + {"Plain", Type, 19, ""}, + {"Printer", Type, 19, ""}, + {"Printer.DocLinkBaseURL", Field, 19, ""}, + {"Printer.DocLinkURL", Field, 19, ""}, + {"Printer.HeadingID", Field, 19, ""}, + {"Printer.HeadingLevel", Field, 19, ""}, + {"Printer.TextCodePrefix", Field, 19, ""}, + {"Printer.TextPrefix", Field, 19, ""}, + {"Printer.TextWidth", Field, 19, ""}, + {"Text", Type, 19, ""}, }, "go/format": { - {"Node", Func, 1}, - {"Source", Func, 1}, + {"Node", Func, 1, "func(dst io.Writer, fset *token.FileSet, node any) error"}, + {"Source", Func, 1, "func(src []byte) ([]byte, error)"}, }, "go/importer": { - {"Default", Func, 5}, - {"For", Func, 5}, - {"ForCompiler", Func, 12}, - {"Lookup", Type, 5}, + {"Default", Func, 5, "func() types.Importer"}, + {"For", Func, 5, "func(compiler string, lookup Lookup) types.Importer"}, + {"ForCompiler", Func, 12, "func(fset *token.FileSet, compiler string, lookup Lookup) types.Importer"}, + {"Lookup", Type, 5, ""}, }, "go/parser": { - {"AllErrors", Const, 1}, - {"DeclarationErrors", Const, 0}, - {"ImportsOnly", Const, 0}, - {"Mode", Type, 0}, - {"PackageClauseOnly", Const, 0}, - {"ParseComments", Const, 0}, - {"ParseDir", Func, 0}, - {"ParseExpr", Func, 0}, - {"ParseExprFrom", Func, 5}, - {"ParseFile", Func, 0}, - {"SkipObjectResolution", Const, 17}, - {"SpuriousErrors", Const, 0}, - {"Trace", Const, 0}, + {"AllErrors", Const, 1, ""}, + {"DeclarationErrors", Const, 0, ""}, + {"ImportsOnly", Const, 0, ""}, + {"Mode", Type, 0, ""}, + {"PackageClauseOnly", Const, 0, ""}, + {"ParseComments", Const, 0, ""}, + {"ParseDir", Func, 0, "func(fset *token.FileSet, path string, filter func(fs.FileInfo) bool, mode Mode) (pkgs map[string]*ast.Package, first error)"}, + {"ParseExpr", Func, 0, "func(x string) (ast.Expr, error)"}, + {"ParseExprFrom", Func, 5, "func(fset *token.FileSet, filename string, src any, mode Mode) (expr ast.Expr, err error)"}, + {"ParseFile", Func, 0, "func(fset *token.FileSet, filename string, src any, mode Mode) (f *ast.File, err error)"}, + {"SkipObjectResolution", Const, 17, ""}, + {"SpuriousErrors", Const, 0, ""}, + {"Trace", Const, 0, ""}, }, "go/printer": { - {"(*Config).Fprint", Method, 0}, - {"CommentedNode", Type, 0}, - {"CommentedNode.Comments", Field, 0}, - {"CommentedNode.Node", Field, 0}, - {"Config", Type, 0}, - {"Config.Indent", Field, 1}, - {"Config.Mode", Field, 0}, - {"Config.Tabwidth", Field, 0}, - {"Fprint", Func, 0}, - {"Mode", Type, 0}, - {"RawFormat", Const, 0}, - {"SourcePos", Const, 0}, - {"TabIndent", Const, 0}, - {"UseSpaces", Const, 0}, + {"(*Config).Fprint", Method, 0, ""}, + {"CommentedNode", Type, 0, ""}, + {"CommentedNode.Comments", Field, 0, ""}, + {"CommentedNode.Node", Field, 0, ""}, + {"Config", Type, 0, ""}, + {"Config.Indent", Field, 1, ""}, + {"Config.Mode", Field, 0, ""}, + {"Config.Tabwidth", Field, 0, ""}, + {"Fprint", Func, 0, "func(output io.Writer, fset *token.FileSet, node any) error"}, + {"Mode", Type, 0, ""}, + {"RawFormat", Const, 0, ""}, + {"SourcePos", Const, 0, ""}, + {"TabIndent", Const, 0, ""}, + {"UseSpaces", Const, 0, ""}, }, "go/scanner": { - {"(*ErrorList).Add", Method, 0}, - {"(*ErrorList).RemoveMultiples", Method, 0}, - {"(*ErrorList).Reset", Method, 0}, - {"(*Scanner).Init", Method, 0}, - {"(*Scanner).Scan", Method, 0}, - {"(Error).Error", Method, 0}, - {"(ErrorList).Err", Method, 0}, - {"(ErrorList).Error", Method, 0}, - {"(ErrorList).Len", Method, 0}, - {"(ErrorList).Less", Method, 0}, - {"(ErrorList).Sort", Method, 0}, - {"(ErrorList).Swap", Method, 0}, - {"Error", Type, 0}, - {"Error.Msg", Field, 0}, - {"Error.Pos", Field, 0}, - {"ErrorHandler", Type, 0}, - {"ErrorList", Type, 0}, - {"Mode", Type, 0}, - {"PrintError", Func, 0}, - {"ScanComments", Const, 0}, - {"Scanner", Type, 0}, - {"Scanner.ErrorCount", Field, 0}, + {"(*ErrorList).Add", Method, 0, ""}, + {"(*ErrorList).RemoveMultiples", Method, 0, ""}, + {"(*ErrorList).Reset", Method, 0, ""}, + {"(*Scanner).Init", Method, 0, ""}, + {"(*Scanner).Scan", Method, 0, ""}, + {"(Error).Error", Method, 0, ""}, + {"(ErrorList).Err", Method, 0, ""}, + {"(ErrorList).Error", Method, 0, ""}, + {"(ErrorList).Len", Method, 0, ""}, + {"(ErrorList).Less", Method, 0, ""}, + {"(ErrorList).Sort", Method, 0, ""}, + {"(ErrorList).Swap", Method, 0, ""}, + {"Error", Type, 0, ""}, + {"Error.Msg", Field, 0, ""}, + {"Error.Pos", Field, 0, ""}, + {"ErrorHandler", Type, 0, ""}, + {"ErrorList", Type, 0, ""}, + {"Mode", Type, 0, ""}, + {"PrintError", Func, 0, "func(w io.Writer, err error)"}, + {"ScanComments", Const, 0, ""}, + {"Scanner", Type, 0, ""}, + {"Scanner.ErrorCount", Field, 0, ""}, }, "go/token": { - {"(*File).AddLine", Method, 0}, - {"(*File).AddLineColumnInfo", Method, 11}, - {"(*File).AddLineInfo", Method, 0}, - {"(*File).Base", Method, 0}, - {"(*File).Line", Method, 0}, - {"(*File).LineCount", Method, 0}, - {"(*File).LineStart", Method, 12}, - {"(*File).Lines", Method, 21}, - {"(*File).MergeLine", Method, 2}, - {"(*File).Name", Method, 0}, - {"(*File).Offset", Method, 0}, - {"(*File).Pos", Method, 0}, - {"(*File).Position", Method, 0}, - {"(*File).PositionFor", Method, 4}, - {"(*File).SetLines", Method, 0}, - {"(*File).SetLinesForContent", Method, 0}, - {"(*File).Size", Method, 0}, - {"(*FileSet).AddFile", Method, 0}, - {"(*FileSet).Base", Method, 0}, - {"(*FileSet).File", Method, 0}, - {"(*FileSet).Iterate", Method, 0}, - {"(*FileSet).Position", Method, 0}, - {"(*FileSet).PositionFor", Method, 4}, - {"(*FileSet).Read", Method, 0}, - {"(*FileSet).RemoveFile", Method, 20}, - {"(*FileSet).Write", Method, 0}, - {"(*Position).IsValid", Method, 0}, - {"(Pos).IsValid", Method, 0}, - {"(Position).String", Method, 0}, - {"(Token).IsKeyword", Method, 0}, - {"(Token).IsLiteral", Method, 0}, - {"(Token).IsOperator", Method, 0}, - {"(Token).Precedence", Method, 0}, - {"(Token).String", Method, 0}, - {"ADD", Const, 0}, - {"ADD_ASSIGN", Const, 0}, - {"AND", Const, 0}, - {"AND_ASSIGN", Const, 0}, - {"AND_NOT", Const, 0}, - {"AND_NOT_ASSIGN", Const, 0}, - {"ARROW", Const, 0}, - {"ASSIGN", Const, 0}, - {"BREAK", Const, 0}, - {"CASE", Const, 0}, - {"CHAN", Const, 0}, - {"CHAR", Const, 0}, - {"COLON", Const, 0}, - {"COMMA", Const, 0}, - {"COMMENT", Const, 0}, - {"CONST", Const, 0}, - {"CONTINUE", Const, 0}, - {"DEC", Const, 0}, - {"DEFAULT", Const, 0}, - {"DEFER", Const, 0}, - {"DEFINE", Const, 0}, - {"ELLIPSIS", Const, 0}, - {"ELSE", Const, 0}, - {"EOF", Const, 0}, - {"EQL", Const, 0}, - {"FALLTHROUGH", Const, 0}, - {"FLOAT", Const, 0}, - {"FOR", Const, 0}, - {"FUNC", Const, 0}, - {"File", Type, 0}, - {"FileSet", Type, 0}, - {"GEQ", Const, 0}, - {"GO", Const, 0}, - {"GOTO", Const, 0}, - {"GTR", Const, 0}, - {"HighestPrec", Const, 0}, - {"IDENT", Const, 0}, - {"IF", Const, 0}, - {"ILLEGAL", Const, 0}, - {"IMAG", Const, 0}, - {"IMPORT", Const, 0}, - {"INC", Const, 0}, - {"INT", Const, 0}, - {"INTERFACE", Const, 0}, - {"IsExported", Func, 13}, - {"IsIdentifier", Func, 13}, - {"IsKeyword", Func, 13}, - {"LAND", Const, 0}, - {"LBRACE", Const, 0}, - {"LBRACK", Const, 0}, - {"LEQ", Const, 0}, - {"LOR", Const, 0}, - {"LPAREN", Const, 0}, - {"LSS", Const, 0}, - {"Lookup", Func, 0}, - {"LowestPrec", Const, 0}, - {"MAP", Const, 0}, - {"MUL", Const, 0}, - {"MUL_ASSIGN", Const, 0}, - {"NEQ", Const, 0}, - {"NOT", Const, 0}, - {"NewFileSet", Func, 0}, - {"NoPos", Const, 0}, - {"OR", Const, 0}, - {"OR_ASSIGN", Const, 0}, - {"PACKAGE", Const, 0}, - {"PERIOD", Const, 0}, - {"Pos", Type, 0}, - {"Position", Type, 0}, - {"Position.Column", Field, 0}, - {"Position.Filename", Field, 0}, - {"Position.Line", Field, 0}, - {"Position.Offset", Field, 0}, - {"QUO", Const, 0}, - {"QUO_ASSIGN", Const, 0}, - {"RANGE", Const, 0}, - {"RBRACE", Const, 0}, - {"RBRACK", Const, 0}, - {"REM", Const, 0}, - {"REM_ASSIGN", Const, 0}, - {"RETURN", Const, 0}, - {"RPAREN", Const, 0}, - {"SELECT", Const, 0}, - {"SEMICOLON", Const, 0}, - {"SHL", Const, 0}, - {"SHL_ASSIGN", Const, 0}, - {"SHR", Const, 0}, - {"SHR_ASSIGN", Const, 0}, - {"STRING", Const, 0}, - {"STRUCT", Const, 0}, - {"SUB", Const, 0}, - {"SUB_ASSIGN", Const, 0}, - {"SWITCH", Const, 0}, - {"TILDE", Const, 18}, - {"TYPE", Const, 0}, - {"Token", Type, 0}, - {"UnaryPrec", Const, 0}, - {"VAR", Const, 0}, - {"XOR", Const, 0}, - {"XOR_ASSIGN", Const, 0}, + {"(*File).AddLine", Method, 0, ""}, + {"(*File).AddLineColumnInfo", Method, 11, ""}, + {"(*File).AddLineInfo", Method, 0, ""}, + {"(*File).Base", Method, 0, ""}, + {"(*File).Line", Method, 0, ""}, + {"(*File).LineCount", Method, 0, ""}, + {"(*File).LineStart", Method, 12, ""}, + {"(*File).Lines", Method, 21, ""}, + {"(*File).MergeLine", Method, 2, ""}, + {"(*File).Name", Method, 0, ""}, + {"(*File).Offset", Method, 0, ""}, + {"(*File).Pos", Method, 0, ""}, + {"(*File).Position", Method, 0, ""}, + {"(*File).PositionFor", Method, 4, ""}, + {"(*File).SetLines", Method, 0, ""}, + {"(*File).SetLinesForContent", Method, 0, ""}, + {"(*File).Size", Method, 0, ""}, + {"(*FileSet).AddFile", Method, 0, ""}, + {"(*FileSet).Base", Method, 0, ""}, + {"(*FileSet).File", Method, 0, ""}, + {"(*FileSet).Iterate", Method, 0, ""}, + {"(*FileSet).Position", Method, 0, ""}, + {"(*FileSet).PositionFor", Method, 4, ""}, + {"(*FileSet).Read", Method, 0, ""}, + {"(*FileSet).RemoveFile", Method, 20, ""}, + {"(*FileSet).Write", Method, 0, ""}, + {"(*Position).IsValid", Method, 0, ""}, + {"(Pos).IsValid", Method, 0, ""}, + {"(Position).String", Method, 0, ""}, + {"(Token).IsKeyword", Method, 0, ""}, + {"(Token).IsLiteral", Method, 0, ""}, + {"(Token).IsOperator", Method, 0, ""}, + {"(Token).Precedence", Method, 0, ""}, + {"(Token).String", Method, 0, ""}, + {"ADD", Const, 0, ""}, + {"ADD_ASSIGN", Const, 0, ""}, + {"AND", Const, 0, ""}, + {"AND_ASSIGN", Const, 0, ""}, + {"AND_NOT", Const, 0, ""}, + {"AND_NOT_ASSIGN", Const, 0, ""}, + {"ARROW", Const, 0, ""}, + {"ASSIGN", Const, 0, ""}, + {"BREAK", Const, 0, ""}, + {"CASE", Const, 0, ""}, + {"CHAN", Const, 0, ""}, + {"CHAR", Const, 0, ""}, + {"COLON", Const, 0, ""}, + {"COMMA", Const, 0, ""}, + {"COMMENT", Const, 0, ""}, + {"CONST", Const, 0, ""}, + {"CONTINUE", Const, 0, ""}, + {"DEC", Const, 0, ""}, + {"DEFAULT", Const, 0, ""}, + {"DEFER", Const, 0, ""}, + {"DEFINE", Const, 0, ""}, + {"ELLIPSIS", Const, 0, ""}, + {"ELSE", Const, 0, ""}, + {"EOF", Const, 0, ""}, + {"EQL", Const, 0, ""}, + {"FALLTHROUGH", Const, 0, ""}, + {"FLOAT", Const, 0, ""}, + {"FOR", Const, 0, ""}, + {"FUNC", Const, 0, ""}, + {"File", Type, 0, ""}, + {"FileSet", Type, 0, ""}, + {"GEQ", Const, 0, ""}, + {"GO", Const, 0, ""}, + {"GOTO", Const, 0, ""}, + {"GTR", Const, 0, ""}, + {"HighestPrec", Const, 0, ""}, + {"IDENT", Const, 0, ""}, + {"IF", Const, 0, ""}, + {"ILLEGAL", Const, 0, ""}, + {"IMAG", Const, 0, ""}, + {"IMPORT", Const, 0, ""}, + {"INC", Const, 0, ""}, + {"INT", Const, 0, ""}, + {"INTERFACE", Const, 0, ""}, + {"IsExported", Func, 13, "func(name string) bool"}, + {"IsIdentifier", Func, 13, "func(name string) bool"}, + {"IsKeyword", Func, 13, "func(name string) bool"}, + {"LAND", Const, 0, ""}, + {"LBRACE", Const, 0, ""}, + {"LBRACK", Const, 0, ""}, + {"LEQ", Const, 0, ""}, + {"LOR", Const, 0, ""}, + {"LPAREN", Const, 0, ""}, + {"LSS", Const, 0, ""}, + {"Lookup", Func, 0, "func(ident string) Token"}, + {"LowestPrec", Const, 0, ""}, + {"MAP", Const, 0, ""}, + {"MUL", Const, 0, ""}, + {"MUL_ASSIGN", Const, 0, ""}, + {"NEQ", Const, 0, ""}, + {"NOT", Const, 0, ""}, + {"NewFileSet", Func, 0, "func() *FileSet"}, + {"NoPos", Const, 0, ""}, + {"OR", Const, 0, ""}, + {"OR_ASSIGN", Const, 0, ""}, + {"PACKAGE", Const, 0, ""}, + {"PERIOD", Const, 0, ""}, + {"Pos", Type, 0, ""}, + {"Position", Type, 0, ""}, + {"Position.Column", Field, 0, ""}, + {"Position.Filename", Field, 0, ""}, + {"Position.Line", Field, 0, ""}, + {"Position.Offset", Field, 0, ""}, + {"QUO", Const, 0, ""}, + {"QUO_ASSIGN", Const, 0, ""}, + {"RANGE", Const, 0, ""}, + {"RBRACE", Const, 0, ""}, + {"RBRACK", Const, 0, ""}, + {"REM", Const, 0, ""}, + {"REM_ASSIGN", Const, 0, ""}, + {"RETURN", Const, 0, ""}, + {"RPAREN", Const, 0, ""}, + {"SELECT", Const, 0, ""}, + {"SEMICOLON", Const, 0, ""}, + {"SHL", Const, 0, ""}, + {"SHL_ASSIGN", Const, 0, ""}, + {"SHR", Const, 0, ""}, + {"SHR_ASSIGN", Const, 0, ""}, + {"STRING", Const, 0, ""}, + {"STRUCT", Const, 0, ""}, + {"SUB", Const, 0, ""}, + {"SUB_ASSIGN", Const, 0, ""}, + {"SWITCH", Const, 0, ""}, + {"TILDE", Const, 18, ""}, + {"TYPE", Const, 0, ""}, + {"Token", Type, 0, ""}, + {"UnaryPrec", Const, 0, ""}, + {"VAR", Const, 0, ""}, + {"XOR", Const, 0, ""}, + {"XOR_ASSIGN", Const, 0, ""}, }, "go/types": { - {"(*Alias).Obj", Method, 22}, - {"(*Alias).Origin", Method, 23}, - {"(*Alias).Rhs", Method, 23}, - {"(*Alias).SetTypeParams", Method, 23}, - {"(*Alias).String", Method, 22}, - {"(*Alias).TypeArgs", Method, 23}, - {"(*Alias).TypeParams", Method, 23}, - {"(*Alias).Underlying", Method, 22}, - {"(*ArgumentError).Error", Method, 18}, - {"(*ArgumentError).Unwrap", Method, 18}, - {"(*Array).Elem", Method, 5}, - {"(*Array).Len", Method, 5}, - {"(*Array).String", Method, 5}, - {"(*Array).Underlying", Method, 5}, - {"(*Basic).Info", Method, 5}, - {"(*Basic).Kind", Method, 5}, - {"(*Basic).Name", Method, 5}, - {"(*Basic).String", Method, 5}, - {"(*Basic).Underlying", Method, 5}, - {"(*Builtin).Exported", Method, 5}, - {"(*Builtin).Id", Method, 5}, - {"(*Builtin).Name", Method, 5}, - {"(*Builtin).Parent", Method, 5}, - {"(*Builtin).Pkg", Method, 5}, - {"(*Builtin).Pos", Method, 5}, - {"(*Builtin).String", Method, 5}, - {"(*Builtin).Type", Method, 5}, - {"(*Chan).Dir", Method, 5}, - {"(*Chan).Elem", Method, 5}, - {"(*Chan).String", Method, 5}, - {"(*Chan).Underlying", Method, 5}, - {"(*Checker).Files", Method, 5}, - {"(*Config).Check", Method, 5}, - {"(*Const).Exported", Method, 5}, - {"(*Const).Id", Method, 5}, - {"(*Const).Name", Method, 5}, - {"(*Const).Parent", Method, 5}, - {"(*Const).Pkg", Method, 5}, - {"(*Const).Pos", Method, 5}, - {"(*Const).String", Method, 5}, - {"(*Const).Type", Method, 5}, - {"(*Const).Val", Method, 5}, - {"(*Func).Exported", Method, 5}, - {"(*Func).FullName", Method, 5}, - {"(*Func).Id", Method, 5}, - {"(*Func).Name", Method, 5}, - {"(*Func).Origin", Method, 19}, - {"(*Func).Parent", Method, 5}, - {"(*Func).Pkg", Method, 5}, - {"(*Func).Pos", Method, 5}, - {"(*Func).Scope", Method, 5}, - {"(*Func).Signature", Method, 23}, - {"(*Func).String", Method, 5}, - {"(*Func).Type", Method, 5}, - {"(*Info).ObjectOf", Method, 5}, - {"(*Info).PkgNameOf", Method, 22}, - {"(*Info).TypeOf", Method, 5}, - {"(*Initializer).String", Method, 5}, - {"(*Interface).Complete", Method, 5}, - {"(*Interface).Embedded", Method, 5}, - {"(*Interface).EmbeddedType", Method, 11}, - {"(*Interface).EmbeddedTypes", Method, 24}, - {"(*Interface).Empty", Method, 5}, - {"(*Interface).ExplicitMethod", Method, 5}, - {"(*Interface).ExplicitMethods", Method, 24}, - {"(*Interface).IsComparable", Method, 18}, - {"(*Interface).IsImplicit", Method, 18}, - {"(*Interface).IsMethodSet", Method, 18}, - {"(*Interface).MarkImplicit", Method, 18}, - {"(*Interface).Method", Method, 5}, - {"(*Interface).Methods", Method, 24}, - {"(*Interface).NumEmbeddeds", Method, 5}, - {"(*Interface).NumExplicitMethods", Method, 5}, - {"(*Interface).NumMethods", Method, 5}, - {"(*Interface).String", Method, 5}, - {"(*Interface).Underlying", Method, 5}, - {"(*Label).Exported", Method, 5}, - {"(*Label).Id", Method, 5}, - {"(*Label).Name", Method, 5}, - {"(*Label).Parent", Method, 5}, - {"(*Label).Pkg", Method, 5}, - {"(*Label).Pos", Method, 5}, - {"(*Label).String", Method, 5}, - {"(*Label).Type", Method, 5}, - {"(*Map).Elem", Method, 5}, - {"(*Map).Key", Method, 5}, - {"(*Map).String", Method, 5}, - {"(*Map).Underlying", Method, 5}, - {"(*MethodSet).At", Method, 5}, - {"(*MethodSet).Len", Method, 5}, - {"(*MethodSet).Lookup", Method, 5}, - {"(*MethodSet).Methods", Method, 24}, - {"(*MethodSet).String", Method, 5}, - {"(*Named).AddMethod", Method, 5}, - {"(*Named).Method", Method, 5}, - {"(*Named).Methods", Method, 24}, - {"(*Named).NumMethods", Method, 5}, - {"(*Named).Obj", Method, 5}, - {"(*Named).Origin", Method, 18}, - {"(*Named).SetTypeParams", Method, 18}, - {"(*Named).SetUnderlying", Method, 5}, - {"(*Named).String", Method, 5}, - {"(*Named).TypeArgs", Method, 18}, - {"(*Named).TypeParams", Method, 18}, - {"(*Named).Underlying", Method, 5}, - {"(*Nil).Exported", Method, 5}, - {"(*Nil).Id", Method, 5}, - {"(*Nil).Name", Method, 5}, - {"(*Nil).Parent", Method, 5}, - {"(*Nil).Pkg", Method, 5}, - {"(*Nil).Pos", Method, 5}, - {"(*Nil).String", Method, 5}, - {"(*Nil).Type", Method, 5}, - {"(*Package).Complete", Method, 5}, - {"(*Package).GoVersion", Method, 21}, - {"(*Package).Imports", Method, 5}, - {"(*Package).MarkComplete", Method, 5}, - {"(*Package).Name", Method, 5}, - {"(*Package).Path", Method, 5}, - {"(*Package).Scope", Method, 5}, - {"(*Package).SetImports", Method, 5}, - {"(*Package).SetName", Method, 6}, - {"(*Package).String", Method, 5}, - {"(*PkgName).Exported", Method, 5}, - {"(*PkgName).Id", Method, 5}, - {"(*PkgName).Imported", Method, 5}, - {"(*PkgName).Name", Method, 5}, - {"(*PkgName).Parent", Method, 5}, - {"(*PkgName).Pkg", Method, 5}, - {"(*PkgName).Pos", Method, 5}, - {"(*PkgName).String", Method, 5}, - {"(*PkgName).Type", Method, 5}, - {"(*Pointer).Elem", Method, 5}, - {"(*Pointer).String", Method, 5}, - {"(*Pointer).Underlying", Method, 5}, - {"(*Scope).Child", Method, 5}, - {"(*Scope).Children", Method, 24}, - {"(*Scope).Contains", Method, 5}, - {"(*Scope).End", Method, 5}, - {"(*Scope).Innermost", Method, 5}, - {"(*Scope).Insert", Method, 5}, - {"(*Scope).Len", Method, 5}, - {"(*Scope).Lookup", Method, 5}, - {"(*Scope).LookupParent", Method, 5}, - {"(*Scope).Names", Method, 5}, - {"(*Scope).NumChildren", Method, 5}, - {"(*Scope).Parent", Method, 5}, - {"(*Scope).Pos", Method, 5}, - {"(*Scope).String", Method, 5}, - {"(*Scope).WriteTo", Method, 5}, - {"(*Selection).Index", Method, 5}, - {"(*Selection).Indirect", Method, 5}, - {"(*Selection).Kind", Method, 5}, - {"(*Selection).Obj", Method, 5}, - {"(*Selection).Recv", Method, 5}, - {"(*Selection).String", Method, 5}, - {"(*Selection).Type", Method, 5}, - {"(*Signature).Params", Method, 5}, - {"(*Signature).Recv", Method, 5}, - {"(*Signature).RecvTypeParams", Method, 18}, - {"(*Signature).Results", Method, 5}, - {"(*Signature).String", Method, 5}, - {"(*Signature).TypeParams", Method, 18}, - {"(*Signature).Underlying", Method, 5}, - {"(*Signature).Variadic", Method, 5}, - {"(*Slice).Elem", Method, 5}, - {"(*Slice).String", Method, 5}, - {"(*Slice).Underlying", Method, 5}, - {"(*StdSizes).Alignof", Method, 5}, - {"(*StdSizes).Offsetsof", Method, 5}, - {"(*StdSizes).Sizeof", Method, 5}, - {"(*Struct).Field", Method, 5}, - {"(*Struct).Fields", Method, 24}, - {"(*Struct).NumFields", Method, 5}, - {"(*Struct).String", Method, 5}, - {"(*Struct).Tag", Method, 5}, - {"(*Struct).Underlying", Method, 5}, - {"(*Term).String", Method, 18}, - {"(*Term).Tilde", Method, 18}, - {"(*Term).Type", Method, 18}, - {"(*Tuple).At", Method, 5}, - {"(*Tuple).Len", Method, 5}, - {"(*Tuple).String", Method, 5}, - {"(*Tuple).Underlying", Method, 5}, - {"(*Tuple).Variables", Method, 24}, - {"(*TypeList).At", Method, 18}, - {"(*TypeList).Len", Method, 18}, - {"(*TypeList).Types", Method, 24}, - {"(*TypeName).Exported", Method, 5}, - {"(*TypeName).Id", Method, 5}, - {"(*TypeName).IsAlias", Method, 9}, - {"(*TypeName).Name", Method, 5}, - {"(*TypeName).Parent", Method, 5}, - {"(*TypeName).Pkg", Method, 5}, - {"(*TypeName).Pos", Method, 5}, - {"(*TypeName).String", Method, 5}, - {"(*TypeName).Type", Method, 5}, - {"(*TypeParam).Constraint", Method, 18}, - {"(*TypeParam).Index", Method, 18}, - {"(*TypeParam).Obj", Method, 18}, - {"(*TypeParam).SetConstraint", Method, 18}, - {"(*TypeParam).String", Method, 18}, - {"(*TypeParam).Underlying", Method, 18}, - {"(*TypeParamList).At", Method, 18}, - {"(*TypeParamList).Len", Method, 18}, - {"(*TypeParamList).TypeParams", Method, 24}, - {"(*Union).Len", Method, 18}, - {"(*Union).String", Method, 18}, - {"(*Union).Term", Method, 18}, - {"(*Union).Terms", Method, 24}, - {"(*Union).Underlying", Method, 18}, - {"(*Var).Anonymous", Method, 5}, - {"(*Var).Embedded", Method, 11}, - {"(*Var).Exported", Method, 5}, - {"(*Var).Id", Method, 5}, - {"(*Var).IsField", Method, 5}, - {"(*Var).Kind", Method, 25}, - {"(*Var).Name", Method, 5}, - {"(*Var).Origin", Method, 19}, - {"(*Var).Parent", Method, 5}, - {"(*Var).Pkg", Method, 5}, - {"(*Var).Pos", Method, 5}, - {"(*Var).SetKind", Method, 25}, - {"(*Var).String", Method, 5}, - {"(*Var).Type", Method, 5}, - {"(Checker).ObjectOf", Method, 5}, - {"(Checker).PkgNameOf", Method, 22}, - {"(Checker).TypeOf", Method, 5}, - {"(Error).Error", Method, 5}, - {"(TypeAndValue).Addressable", Method, 5}, - {"(TypeAndValue).Assignable", Method, 5}, - {"(TypeAndValue).HasOk", Method, 5}, - {"(TypeAndValue).IsBuiltin", Method, 5}, - {"(TypeAndValue).IsNil", Method, 5}, - {"(TypeAndValue).IsType", Method, 5}, - {"(TypeAndValue).IsValue", Method, 5}, - {"(TypeAndValue).IsVoid", Method, 5}, - {"(VarKind).String", Method, 25}, - {"Alias", Type, 22}, - {"ArgumentError", Type, 18}, - {"ArgumentError.Err", Field, 18}, - {"ArgumentError.Index", Field, 18}, - {"Array", Type, 5}, - {"AssertableTo", Func, 5}, - {"AssignableTo", Func, 5}, - {"Basic", Type, 5}, - {"BasicInfo", Type, 5}, - {"BasicKind", Type, 5}, - {"Bool", Const, 5}, - {"Builtin", Type, 5}, - {"Byte", Const, 5}, - {"Chan", Type, 5}, - {"ChanDir", Type, 5}, - {"CheckExpr", Func, 13}, - {"Checker", Type, 5}, - {"Checker.Info", Field, 5}, - {"Comparable", Func, 5}, - {"Complex128", Const, 5}, - {"Complex64", Const, 5}, - {"Config", Type, 5}, - {"Config.Context", Field, 18}, - {"Config.DisableUnusedImportCheck", Field, 5}, - {"Config.Error", Field, 5}, - {"Config.FakeImportC", Field, 5}, - {"Config.GoVersion", Field, 18}, - {"Config.IgnoreFuncBodies", Field, 5}, - {"Config.Importer", Field, 5}, - {"Config.Sizes", Field, 5}, - {"Const", Type, 5}, - {"Context", Type, 18}, - {"ConvertibleTo", Func, 5}, - {"DefPredeclaredTestFuncs", Func, 5}, - {"Default", Func, 8}, - {"Error", Type, 5}, - {"Error.Fset", Field, 5}, - {"Error.Msg", Field, 5}, - {"Error.Pos", Field, 5}, - {"Error.Soft", Field, 5}, - {"Eval", Func, 5}, - {"ExprString", Func, 5}, - {"FieldVal", Const, 5}, - {"FieldVar", Const, 25}, - {"Float32", Const, 5}, - {"Float64", Const, 5}, - {"Func", Type, 5}, - {"Id", Func, 5}, - {"Identical", Func, 5}, - {"IdenticalIgnoreTags", Func, 8}, - {"Implements", Func, 5}, - {"ImportMode", Type, 6}, - {"Importer", Type, 5}, - {"ImporterFrom", Type, 6}, - {"Info", Type, 5}, - {"Info.Defs", Field, 5}, - {"Info.FileVersions", Field, 22}, - {"Info.Implicits", Field, 5}, - {"Info.InitOrder", Field, 5}, - {"Info.Instances", Field, 18}, - {"Info.Scopes", Field, 5}, - {"Info.Selections", Field, 5}, - {"Info.Types", Field, 5}, - {"Info.Uses", Field, 5}, - {"Initializer", Type, 5}, - {"Initializer.Lhs", Field, 5}, - {"Initializer.Rhs", Field, 5}, - {"Instance", Type, 18}, - {"Instance.Type", Field, 18}, - {"Instance.TypeArgs", Field, 18}, - {"Instantiate", Func, 18}, - {"Int", Const, 5}, - {"Int16", Const, 5}, - {"Int32", Const, 5}, - {"Int64", Const, 5}, - {"Int8", Const, 5}, - {"Interface", Type, 5}, - {"Invalid", Const, 5}, - {"IsBoolean", Const, 5}, - {"IsComplex", Const, 5}, - {"IsConstType", Const, 5}, - {"IsFloat", Const, 5}, - {"IsInteger", Const, 5}, - {"IsInterface", Func, 5}, - {"IsNumeric", Const, 5}, - {"IsOrdered", Const, 5}, - {"IsString", Const, 5}, - {"IsUnsigned", Const, 5}, - {"IsUntyped", Const, 5}, - {"Label", Type, 5}, - {"LocalVar", Const, 25}, - {"LookupFieldOrMethod", Func, 5}, - {"LookupSelection", Func, 25}, - {"Map", Type, 5}, - {"MethodExpr", Const, 5}, - {"MethodSet", Type, 5}, - {"MethodVal", Const, 5}, - {"MissingMethod", Func, 5}, - {"Named", Type, 5}, - {"NewAlias", Func, 22}, - {"NewArray", Func, 5}, - {"NewChan", Func, 5}, - {"NewChecker", Func, 5}, - {"NewConst", Func, 5}, - {"NewContext", Func, 18}, - {"NewField", Func, 5}, - {"NewFunc", Func, 5}, - {"NewInterface", Func, 5}, - {"NewInterfaceType", Func, 11}, - {"NewLabel", Func, 5}, - {"NewMap", Func, 5}, - {"NewMethodSet", Func, 5}, - {"NewNamed", Func, 5}, - {"NewPackage", Func, 5}, - {"NewParam", Func, 5}, - {"NewPkgName", Func, 5}, - {"NewPointer", Func, 5}, - {"NewScope", Func, 5}, - {"NewSignature", Func, 5}, - {"NewSignatureType", Func, 18}, - {"NewSlice", Func, 5}, - {"NewStruct", Func, 5}, - {"NewTerm", Func, 18}, - {"NewTuple", Func, 5}, - {"NewTypeName", Func, 5}, - {"NewTypeParam", Func, 18}, - {"NewUnion", Func, 18}, - {"NewVar", Func, 5}, - {"Nil", Type, 5}, - {"Object", Type, 5}, - {"ObjectString", Func, 5}, - {"Package", Type, 5}, - {"PackageVar", Const, 25}, - {"ParamVar", Const, 25}, - {"PkgName", Type, 5}, - {"Pointer", Type, 5}, - {"Qualifier", Type, 5}, - {"RecvOnly", Const, 5}, - {"RecvVar", Const, 25}, - {"RelativeTo", Func, 5}, - {"ResultVar", Const, 25}, - {"Rune", Const, 5}, - {"Satisfies", Func, 20}, - {"Scope", Type, 5}, - {"Selection", Type, 5}, - {"SelectionKind", Type, 5}, - {"SelectionString", Func, 5}, - {"SendOnly", Const, 5}, - {"SendRecv", Const, 5}, - {"Signature", Type, 5}, - {"Sizes", Type, 5}, - {"SizesFor", Func, 9}, - {"Slice", Type, 5}, - {"StdSizes", Type, 5}, - {"StdSizes.MaxAlign", Field, 5}, - {"StdSizes.WordSize", Field, 5}, - {"String", Const, 5}, - {"Struct", Type, 5}, - {"Term", Type, 18}, - {"Tuple", Type, 5}, - {"Typ", Var, 5}, - {"Type", Type, 5}, - {"TypeAndValue", Type, 5}, - {"TypeAndValue.Type", Field, 5}, - {"TypeAndValue.Value", Field, 5}, - {"TypeList", Type, 18}, - {"TypeName", Type, 5}, - {"TypeParam", Type, 18}, - {"TypeParamList", Type, 18}, - {"TypeString", Func, 5}, - {"Uint", Const, 5}, - {"Uint16", Const, 5}, - {"Uint32", Const, 5}, - {"Uint64", Const, 5}, - {"Uint8", Const, 5}, - {"Uintptr", Const, 5}, - {"Unalias", Func, 22}, - {"Union", Type, 18}, - {"Universe", Var, 5}, - {"Unsafe", Var, 5}, - {"UnsafePointer", Const, 5}, - {"UntypedBool", Const, 5}, - {"UntypedComplex", Const, 5}, - {"UntypedFloat", Const, 5}, - {"UntypedInt", Const, 5}, - {"UntypedNil", Const, 5}, - {"UntypedRune", Const, 5}, - {"UntypedString", Const, 5}, - {"Var", Type, 5}, - {"VarKind", Type, 25}, - {"WriteExpr", Func, 5}, - {"WriteSignature", Func, 5}, - {"WriteType", Func, 5}, + {"(*Alias).Obj", Method, 22, ""}, + {"(*Alias).Origin", Method, 23, ""}, + {"(*Alias).Rhs", Method, 23, ""}, + {"(*Alias).SetTypeParams", Method, 23, ""}, + {"(*Alias).String", Method, 22, ""}, + {"(*Alias).TypeArgs", Method, 23, ""}, + {"(*Alias).TypeParams", Method, 23, ""}, + {"(*Alias).Underlying", Method, 22, ""}, + {"(*ArgumentError).Error", Method, 18, ""}, + {"(*ArgumentError).Unwrap", Method, 18, ""}, + {"(*Array).Elem", Method, 5, ""}, + {"(*Array).Len", Method, 5, ""}, + {"(*Array).String", Method, 5, ""}, + {"(*Array).Underlying", Method, 5, ""}, + {"(*Basic).Info", Method, 5, ""}, + {"(*Basic).Kind", Method, 5, ""}, + {"(*Basic).Name", Method, 5, ""}, + {"(*Basic).String", Method, 5, ""}, + {"(*Basic).Underlying", Method, 5, ""}, + {"(*Builtin).Exported", Method, 5, ""}, + {"(*Builtin).Id", Method, 5, ""}, + {"(*Builtin).Name", Method, 5, ""}, + {"(*Builtin).Parent", Method, 5, ""}, + {"(*Builtin).Pkg", Method, 5, ""}, + {"(*Builtin).Pos", Method, 5, ""}, + {"(*Builtin).String", Method, 5, ""}, + {"(*Builtin).Type", Method, 5, ""}, + {"(*Chan).Dir", Method, 5, ""}, + {"(*Chan).Elem", Method, 5, ""}, + {"(*Chan).String", Method, 5, ""}, + {"(*Chan).Underlying", Method, 5, ""}, + {"(*Checker).Files", Method, 5, ""}, + {"(*Config).Check", Method, 5, ""}, + {"(*Const).Exported", Method, 5, ""}, + {"(*Const).Id", Method, 5, ""}, + {"(*Const).Name", Method, 5, ""}, + {"(*Const).Parent", Method, 5, ""}, + {"(*Const).Pkg", Method, 5, ""}, + {"(*Const).Pos", Method, 5, ""}, + {"(*Const).String", Method, 5, ""}, + {"(*Const).Type", Method, 5, ""}, + {"(*Const).Val", Method, 5, ""}, + {"(*Func).Exported", Method, 5, ""}, + {"(*Func).FullName", Method, 5, ""}, + {"(*Func).Id", Method, 5, ""}, + {"(*Func).Name", Method, 5, ""}, + {"(*Func).Origin", Method, 19, ""}, + {"(*Func).Parent", Method, 5, ""}, + {"(*Func).Pkg", Method, 5, ""}, + {"(*Func).Pos", Method, 5, ""}, + {"(*Func).Scope", Method, 5, ""}, + {"(*Func).Signature", Method, 23, ""}, + {"(*Func).String", Method, 5, ""}, + {"(*Func).Type", Method, 5, ""}, + {"(*Info).ObjectOf", Method, 5, ""}, + {"(*Info).PkgNameOf", Method, 22, ""}, + {"(*Info).TypeOf", Method, 5, ""}, + {"(*Initializer).String", Method, 5, ""}, + {"(*Interface).Complete", Method, 5, ""}, + {"(*Interface).Embedded", Method, 5, ""}, + {"(*Interface).EmbeddedType", Method, 11, ""}, + {"(*Interface).EmbeddedTypes", Method, 24, ""}, + {"(*Interface).Empty", Method, 5, ""}, + {"(*Interface).ExplicitMethod", Method, 5, ""}, + {"(*Interface).ExplicitMethods", Method, 24, ""}, + {"(*Interface).IsComparable", Method, 18, ""}, + {"(*Interface).IsImplicit", Method, 18, ""}, + {"(*Interface).IsMethodSet", Method, 18, ""}, + {"(*Interface).MarkImplicit", Method, 18, ""}, + {"(*Interface).Method", Method, 5, ""}, + {"(*Interface).Methods", Method, 24, ""}, + {"(*Interface).NumEmbeddeds", Method, 5, ""}, + {"(*Interface).NumExplicitMethods", Method, 5, ""}, + {"(*Interface).NumMethods", Method, 5, ""}, + {"(*Interface).String", Method, 5, ""}, + {"(*Interface).Underlying", Method, 5, ""}, + {"(*Label).Exported", Method, 5, ""}, + {"(*Label).Id", Method, 5, ""}, + {"(*Label).Name", Method, 5, ""}, + {"(*Label).Parent", Method, 5, ""}, + {"(*Label).Pkg", Method, 5, ""}, + {"(*Label).Pos", Method, 5, ""}, + {"(*Label).String", Method, 5, ""}, + {"(*Label).Type", Method, 5, ""}, + {"(*Map).Elem", Method, 5, ""}, + {"(*Map).Key", Method, 5, ""}, + {"(*Map).String", Method, 5, ""}, + {"(*Map).Underlying", Method, 5, ""}, + {"(*MethodSet).At", Method, 5, ""}, + {"(*MethodSet).Len", Method, 5, ""}, + {"(*MethodSet).Lookup", Method, 5, ""}, + {"(*MethodSet).Methods", Method, 24, ""}, + {"(*MethodSet).String", Method, 5, ""}, + {"(*Named).AddMethod", Method, 5, ""}, + {"(*Named).Method", Method, 5, ""}, + {"(*Named).Methods", Method, 24, ""}, + {"(*Named).NumMethods", Method, 5, ""}, + {"(*Named).Obj", Method, 5, ""}, + {"(*Named).Origin", Method, 18, ""}, + {"(*Named).SetTypeParams", Method, 18, ""}, + {"(*Named).SetUnderlying", Method, 5, ""}, + {"(*Named).String", Method, 5, ""}, + {"(*Named).TypeArgs", Method, 18, ""}, + {"(*Named).TypeParams", Method, 18, ""}, + {"(*Named).Underlying", Method, 5, ""}, + {"(*Nil).Exported", Method, 5, ""}, + {"(*Nil).Id", Method, 5, ""}, + {"(*Nil).Name", Method, 5, ""}, + {"(*Nil).Parent", Method, 5, ""}, + {"(*Nil).Pkg", Method, 5, ""}, + {"(*Nil).Pos", Method, 5, ""}, + {"(*Nil).String", Method, 5, ""}, + {"(*Nil).Type", Method, 5, ""}, + {"(*Package).Complete", Method, 5, ""}, + {"(*Package).GoVersion", Method, 21, ""}, + {"(*Package).Imports", Method, 5, ""}, + {"(*Package).MarkComplete", Method, 5, ""}, + {"(*Package).Name", Method, 5, ""}, + {"(*Package).Path", Method, 5, ""}, + {"(*Package).Scope", Method, 5, ""}, + {"(*Package).SetImports", Method, 5, ""}, + {"(*Package).SetName", Method, 6, ""}, + {"(*Package).String", Method, 5, ""}, + {"(*PkgName).Exported", Method, 5, ""}, + {"(*PkgName).Id", Method, 5, ""}, + {"(*PkgName).Imported", Method, 5, ""}, + {"(*PkgName).Name", Method, 5, ""}, + {"(*PkgName).Parent", Method, 5, ""}, + {"(*PkgName).Pkg", Method, 5, ""}, + {"(*PkgName).Pos", Method, 5, ""}, + {"(*PkgName).String", Method, 5, ""}, + {"(*PkgName).Type", Method, 5, ""}, + {"(*Pointer).Elem", Method, 5, ""}, + {"(*Pointer).String", Method, 5, ""}, + {"(*Pointer).Underlying", Method, 5, ""}, + {"(*Scope).Child", Method, 5, ""}, + {"(*Scope).Children", Method, 24, ""}, + {"(*Scope).Contains", Method, 5, ""}, + {"(*Scope).End", Method, 5, ""}, + {"(*Scope).Innermost", Method, 5, ""}, + {"(*Scope).Insert", Method, 5, ""}, + {"(*Scope).Len", Method, 5, ""}, + {"(*Scope).Lookup", Method, 5, ""}, + {"(*Scope).LookupParent", Method, 5, ""}, + {"(*Scope).Names", Method, 5, ""}, + {"(*Scope).NumChildren", Method, 5, ""}, + {"(*Scope).Parent", Method, 5, ""}, + {"(*Scope).Pos", Method, 5, ""}, + {"(*Scope).String", Method, 5, ""}, + {"(*Scope).WriteTo", Method, 5, ""}, + {"(*Selection).Index", Method, 5, ""}, + {"(*Selection).Indirect", Method, 5, ""}, + {"(*Selection).Kind", Method, 5, ""}, + {"(*Selection).Obj", Method, 5, ""}, + {"(*Selection).Recv", Method, 5, ""}, + {"(*Selection).String", Method, 5, ""}, + {"(*Selection).Type", Method, 5, ""}, + {"(*Signature).Params", Method, 5, ""}, + {"(*Signature).Recv", Method, 5, ""}, + {"(*Signature).RecvTypeParams", Method, 18, ""}, + {"(*Signature).Results", Method, 5, ""}, + {"(*Signature).String", Method, 5, ""}, + {"(*Signature).TypeParams", Method, 18, ""}, + {"(*Signature).Underlying", Method, 5, ""}, + {"(*Signature).Variadic", Method, 5, ""}, + {"(*Slice).Elem", Method, 5, ""}, + {"(*Slice).String", Method, 5, ""}, + {"(*Slice).Underlying", Method, 5, ""}, + {"(*StdSizes).Alignof", Method, 5, ""}, + {"(*StdSizes).Offsetsof", Method, 5, ""}, + {"(*StdSizes).Sizeof", Method, 5, ""}, + {"(*Struct).Field", Method, 5, ""}, + {"(*Struct).Fields", Method, 24, ""}, + {"(*Struct).NumFields", Method, 5, ""}, + {"(*Struct).String", Method, 5, ""}, + {"(*Struct).Tag", Method, 5, ""}, + {"(*Struct).Underlying", Method, 5, ""}, + {"(*Term).String", Method, 18, ""}, + {"(*Term).Tilde", Method, 18, ""}, + {"(*Term).Type", Method, 18, ""}, + {"(*Tuple).At", Method, 5, ""}, + {"(*Tuple).Len", Method, 5, ""}, + {"(*Tuple).String", Method, 5, ""}, + {"(*Tuple).Underlying", Method, 5, ""}, + {"(*Tuple).Variables", Method, 24, ""}, + {"(*TypeList).At", Method, 18, ""}, + {"(*TypeList).Len", Method, 18, ""}, + {"(*TypeList).Types", Method, 24, ""}, + {"(*TypeName).Exported", Method, 5, ""}, + {"(*TypeName).Id", Method, 5, ""}, + {"(*TypeName).IsAlias", Method, 9, ""}, + {"(*TypeName).Name", Method, 5, ""}, + {"(*TypeName).Parent", Method, 5, ""}, + {"(*TypeName).Pkg", Method, 5, ""}, + {"(*TypeName).Pos", Method, 5, ""}, + {"(*TypeName).String", Method, 5, ""}, + {"(*TypeName).Type", Method, 5, ""}, + {"(*TypeParam).Constraint", Method, 18, ""}, + {"(*TypeParam).Index", Method, 18, ""}, + {"(*TypeParam).Obj", Method, 18, ""}, + {"(*TypeParam).SetConstraint", Method, 18, ""}, + {"(*TypeParam).String", Method, 18, ""}, + {"(*TypeParam).Underlying", Method, 18, ""}, + {"(*TypeParamList).At", Method, 18, ""}, + {"(*TypeParamList).Len", Method, 18, ""}, + {"(*TypeParamList).TypeParams", Method, 24, ""}, + {"(*Union).Len", Method, 18, ""}, + {"(*Union).String", Method, 18, ""}, + {"(*Union).Term", Method, 18, ""}, + {"(*Union).Terms", Method, 24, ""}, + {"(*Union).Underlying", Method, 18, ""}, + {"(*Var).Anonymous", Method, 5, ""}, + {"(*Var).Embedded", Method, 11, ""}, + {"(*Var).Exported", Method, 5, ""}, + {"(*Var).Id", Method, 5, ""}, + {"(*Var).IsField", Method, 5, ""}, + {"(*Var).Kind", Method, 25, ""}, + {"(*Var).Name", Method, 5, ""}, + {"(*Var).Origin", Method, 19, ""}, + {"(*Var).Parent", Method, 5, ""}, + {"(*Var).Pkg", Method, 5, ""}, + {"(*Var).Pos", Method, 5, ""}, + {"(*Var).SetKind", Method, 25, ""}, + {"(*Var).String", Method, 5, ""}, + {"(*Var).Type", Method, 5, ""}, + {"(Checker).ObjectOf", Method, 5, ""}, + {"(Checker).PkgNameOf", Method, 22, ""}, + {"(Checker).TypeOf", Method, 5, ""}, + {"(Error).Error", Method, 5, ""}, + {"(TypeAndValue).Addressable", Method, 5, ""}, + {"(TypeAndValue).Assignable", Method, 5, ""}, + {"(TypeAndValue).HasOk", Method, 5, ""}, + {"(TypeAndValue).IsBuiltin", Method, 5, ""}, + {"(TypeAndValue).IsNil", Method, 5, ""}, + {"(TypeAndValue).IsType", Method, 5, ""}, + {"(TypeAndValue).IsValue", Method, 5, ""}, + {"(TypeAndValue).IsVoid", Method, 5, ""}, + {"(VarKind).String", Method, 25, ""}, + {"Alias", Type, 22, ""}, + {"ArgumentError", Type, 18, ""}, + {"ArgumentError.Err", Field, 18, ""}, + {"ArgumentError.Index", Field, 18, ""}, + {"Array", Type, 5, ""}, + {"AssertableTo", Func, 5, "func(V *Interface, T Type) bool"}, + {"AssignableTo", Func, 5, "func(V Type, T Type) bool"}, + {"Basic", Type, 5, ""}, + {"BasicInfo", Type, 5, ""}, + {"BasicKind", Type, 5, ""}, + {"Bool", Const, 5, ""}, + {"Builtin", Type, 5, ""}, + {"Byte", Const, 5, ""}, + {"Chan", Type, 5, ""}, + {"ChanDir", Type, 5, ""}, + {"CheckExpr", Func, 13, "func(fset *token.FileSet, pkg *Package, pos token.Pos, expr ast.Expr, info *Info) (err error)"}, + {"Checker", Type, 5, ""}, + {"Checker.Info", Field, 5, ""}, + {"Comparable", Func, 5, "func(T Type) bool"}, + {"Complex128", Const, 5, ""}, + {"Complex64", Const, 5, ""}, + {"Config", Type, 5, ""}, + {"Config.Context", Field, 18, ""}, + {"Config.DisableUnusedImportCheck", Field, 5, ""}, + {"Config.Error", Field, 5, ""}, + {"Config.FakeImportC", Field, 5, ""}, + {"Config.GoVersion", Field, 18, ""}, + {"Config.IgnoreFuncBodies", Field, 5, ""}, + {"Config.Importer", Field, 5, ""}, + {"Config.Sizes", Field, 5, ""}, + {"Const", Type, 5, ""}, + {"Context", Type, 18, ""}, + {"ConvertibleTo", Func, 5, "func(V Type, T Type) bool"}, + {"DefPredeclaredTestFuncs", Func, 5, "func()"}, + {"Default", Func, 8, "func(t Type) Type"}, + {"Error", Type, 5, ""}, + {"Error.Fset", Field, 5, ""}, + {"Error.Msg", Field, 5, ""}, + {"Error.Pos", Field, 5, ""}, + {"Error.Soft", Field, 5, ""}, + {"Eval", Func, 5, "func(fset *token.FileSet, pkg *Package, pos token.Pos, expr string) (_ TypeAndValue, err error)"}, + {"ExprString", Func, 5, "func(x ast.Expr) string"}, + {"FieldVal", Const, 5, ""}, + {"FieldVar", Const, 25, ""}, + {"Float32", Const, 5, ""}, + {"Float64", Const, 5, ""}, + {"Func", Type, 5, ""}, + {"Id", Func, 5, "func(pkg *Package, name string) string"}, + {"Identical", Func, 5, "func(x Type, y Type) bool"}, + {"IdenticalIgnoreTags", Func, 8, "func(x Type, y Type) bool"}, + {"Implements", Func, 5, "func(V Type, T *Interface) bool"}, + {"ImportMode", Type, 6, ""}, + {"Importer", Type, 5, ""}, + {"ImporterFrom", Type, 6, ""}, + {"Info", Type, 5, ""}, + {"Info.Defs", Field, 5, ""}, + {"Info.FileVersions", Field, 22, ""}, + {"Info.Implicits", Field, 5, ""}, + {"Info.InitOrder", Field, 5, ""}, + {"Info.Instances", Field, 18, ""}, + {"Info.Scopes", Field, 5, ""}, + {"Info.Selections", Field, 5, ""}, + {"Info.Types", Field, 5, ""}, + {"Info.Uses", Field, 5, ""}, + {"Initializer", Type, 5, ""}, + {"Initializer.Lhs", Field, 5, ""}, + {"Initializer.Rhs", Field, 5, ""}, + {"Instance", Type, 18, ""}, + {"Instance.Type", Field, 18, ""}, + {"Instance.TypeArgs", Field, 18, ""}, + {"Instantiate", Func, 18, "func(ctxt *Context, orig Type, targs []Type, validate bool) (Type, error)"}, + {"Int", Const, 5, ""}, + {"Int16", Const, 5, ""}, + {"Int32", Const, 5, ""}, + {"Int64", Const, 5, ""}, + {"Int8", Const, 5, ""}, + {"Interface", Type, 5, ""}, + {"Invalid", Const, 5, ""}, + {"IsBoolean", Const, 5, ""}, + {"IsComplex", Const, 5, ""}, + {"IsConstType", Const, 5, ""}, + {"IsFloat", Const, 5, ""}, + {"IsInteger", Const, 5, ""}, + {"IsInterface", Func, 5, "func(t Type) bool"}, + {"IsNumeric", Const, 5, ""}, + {"IsOrdered", Const, 5, ""}, + {"IsString", Const, 5, ""}, + {"IsUnsigned", Const, 5, ""}, + {"IsUntyped", Const, 5, ""}, + {"Label", Type, 5, ""}, + {"LocalVar", Const, 25, ""}, + {"LookupFieldOrMethod", Func, 5, "func(T Type, addressable bool, pkg *Package, name string) (obj Object, index []int, indirect bool)"}, + {"LookupSelection", Func, 25, ""}, + {"Map", Type, 5, ""}, + {"MethodExpr", Const, 5, ""}, + {"MethodSet", Type, 5, ""}, + {"MethodVal", Const, 5, ""}, + {"MissingMethod", Func, 5, "func(V Type, T *Interface, static bool) (method *Func, wrongType bool)"}, + {"Named", Type, 5, ""}, + {"NewAlias", Func, 22, "func(obj *TypeName, rhs Type) *Alias"}, + {"NewArray", Func, 5, "func(elem Type, len int64) *Array"}, + {"NewChan", Func, 5, "func(dir ChanDir, elem Type) *Chan"}, + {"NewChecker", Func, 5, "func(conf *Config, fset *token.FileSet, pkg *Package, info *Info) *Checker"}, + {"NewConst", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type, val constant.Value) *Const"}, + {"NewContext", Func, 18, "func() *Context"}, + {"NewField", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type, embedded bool) *Var"}, + {"NewFunc", Func, 5, "func(pos token.Pos, pkg *Package, name string, sig *Signature) *Func"}, + {"NewInterface", Func, 5, "func(methods []*Func, embeddeds []*Named) *Interface"}, + {"NewInterfaceType", Func, 11, "func(methods []*Func, embeddeds []Type) *Interface"}, + {"NewLabel", Func, 5, "func(pos token.Pos, pkg *Package, name string) *Label"}, + {"NewMap", Func, 5, "func(key Type, elem Type) *Map"}, + {"NewMethodSet", Func, 5, "func(T Type) *MethodSet"}, + {"NewNamed", Func, 5, "func(obj *TypeName, underlying Type, methods []*Func) *Named"}, + {"NewPackage", Func, 5, "func(path string, name string) *Package"}, + {"NewParam", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type) *Var"}, + {"NewPkgName", Func, 5, "func(pos token.Pos, pkg *Package, name string, imported *Package) *PkgName"}, + {"NewPointer", Func, 5, "func(elem Type) *Pointer"}, + {"NewScope", Func, 5, "func(parent *Scope, pos token.Pos, end token.Pos, comment string) *Scope"}, + {"NewSignature", Func, 5, "func(recv *Var, params *Tuple, results *Tuple, variadic bool) *Signature"}, + {"NewSignatureType", Func, 18, "func(recv *Var, recvTypeParams []*TypeParam, typeParams []*TypeParam, params *Tuple, results *Tuple, variadic bool) *Signature"}, + {"NewSlice", Func, 5, "func(elem Type) *Slice"}, + {"NewStruct", Func, 5, "func(fields []*Var, tags []string) *Struct"}, + {"NewTerm", Func, 18, "func(tilde bool, typ Type) *Term"}, + {"NewTuple", Func, 5, "func(x ...*Var) *Tuple"}, + {"NewTypeName", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type) *TypeName"}, + {"NewTypeParam", Func, 18, "func(obj *TypeName, constraint Type) *TypeParam"}, + {"NewUnion", Func, 18, "func(terms []*Term) *Union"}, + {"NewVar", Func, 5, "func(pos token.Pos, pkg *Package, name string, typ Type) *Var"}, + {"Nil", Type, 5, ""}, + {"Object", Type, 5, ""}, + {"ObjectString", Func, 5, "func(obj Object, qf Qualifier) string"}, + {"Package", Type, 5, ""}, + {"PackageVar", Const, 25, ""}, + {"ParamVar", Const, 25, ""}, + {"PkgName", Type, 5, ""}, + {"Pointer", Type, 5, ""}, + {"Qualifier", Type, 5, ""}, + {"RecvOnly", Const, 5, ""}, + {"RecvVar", Const, 25, ""}, + {"RelativeTo", Func, 5, "func(pkg *Package) Qualifier"}, + {"ResultVar", Const, 25, ""}, + {"Rune", Const, 5, ""}, + {"Satisfies", Func, 20, "func(V Type, T *Interface) bool"}, + {"Scope", Type, 5, ""}, + {"Selection", Type, 5, ""}, + {"SelectionKind", Type, 5, ""}, + {"SelectionString", Func, 5, "func(s *Selection, qf Qualifier) string"}, + {"SendOnly", Const, 5, ""}, + {"SendRecv", Const, 5, ""}, + {"Signature", Type, 5, ""}, + {"Sizes", Type, 5, ""}, + {"SizesFor", Func, 9, "func(compiler string, arch string) Sizes"}, + {"Slice", Type, 5, ""}, + {"StdSizes", Type, 5, ""}, + {"StdSizes.MaxAlign", Field, 5, ""}, + {"StdSizes.WordSize", Field, 5, ""}, + {"String", Const, 5, ""}, + {"Struct", Type, 5, ""}, + {"Term", Type, 18, ""}, + {"Tuple", Type, 5, ""}, + {"Typ", Var, 5, ""}, + {"Type", Type, 5, ""}, + {"TypeAndValue", Type, 5, ""}, + {"TypeAndValue.Type", Field, 5, ""}, + {"TypeAndValue.Value", Field, 5, ""}, + {"TypeList", Type, 18, ""}, + {"TypeName", Type, 5, ""}, + {"TypeParam", Type, 18, ""}, + {"TypeParamList", Type, 18, ""}, + {"TypeString", Func, 5, "func(typ Type, qf Qualifier) string"}, + {"Uint", Const, 5, ""}, + {"Uint16", Const, 5, ""}, + {"Uint32", Const, 5, ""}, + {"Uint64", Const, 5, ""}, + {"Uint8", Const, 5, ""}, + {"Uintptr", Const, 5, ""}, + {"Unalias", Func, 22, "func(t Type) Type"}, + {"Union", Type, 18, ""}, + {"Universe", Var, 5, ""}, + {"Unsafe", Var, 5, ""}, + {"UnsafePointer", Const, 5, ""}, + {"UntypedBool", Const, 5, ""}, + {"UntypedComplex", Const, 5, ""}, + {"UntypedFloat", Const, 5, ""}, + {"UntypedInt", Const, 5, ""}, + {"UntypedNil", Const, 5, ""}, + {"UntypedRune", Const, 5, ""}, + {"UntypedString", Const, 5, ""}, + {"Var", Type, 5, ""}, + {"VarKind", Type, 25, ""}, + {"WriteExpr", Func, 5, "func(buf *bytes.Buffer, x ast.Expr)"}, + {"WriteSignature", Func, 5, "func(buf *bytes.Buffer, sig *Signature, qf Qualifier)"}, + {"WriteType", Func, 5, "func(buf *bytes.Buffer, typ Type, qf Qualifier)"}, }, "go/version": { - {"Compare", Func, 22}, - {"IsValid", Func, 22}, - {"Lang", Func, 22}, + {"Compare", Func, 22, "func(x string, y string) int"}, + {"IsValid", Func, 22, "func(x string) bool"}, + {"Lang", Func, 22, "func(x string) string"}, }, "hash": { - {"Hash", Type, 0}, - {"Hash32", Type, 0}, - {"Hash64", Type, 0}, + {"Hash", Type, 0, ""}, + {"Hash32", Type, 0, ""}, + {"Hash64", Type, 0, ""}, }, "hash/adler32": { - {"Checksum", Func, 0}, - {"New", Func, 0}, - {"Size", Const, 0}, + {"Checksum", Func, 0, "func(data []byte) uint32"}, + {"New", Func, 0, "func() hash.Hash32"}, + {"Size", Const, 0, ""}, }, "hash/crc32": { - {"Castagnoli", Const, 0}, - {"Checksum", Func, 0}, - {"ChecksumIEEE", Func, 0}, - {"IEEE", Const, 0}, - {"IEEETable", Var, 0}, - {"Koopman", Const, 0}, - {"MakeTable", Func, 0}, - {"New", Func, 0}, - {"NewIEEE", Func, 0}, - {"Size", Const, 0}, - {"Table", Type, 0}, - {"Update", Func, 0}, + {"Castagnoli", Const, 0, ""}, + {"Checksum", Func, 0, "func(data []byte, tab *Table) uint32"}, + {"ChecksumIEEE", Func, 0, "func(data []byte) uint32"}, + {"IEEE", Const, 0, ""}, + {"IEEETable", Var, 0, ""}, + {"Koopman", Const, 0, ""}, + {"MakeTable", Func, 0, "func(poly uint32) *Table"}, + {"New", Func, 0, "func(tab *Table) hash.Hash32"}, + {"NewIEEE", Func, 0, "func() hash.Hash32"}, + {"Size", Const, 0, ""}, + {"Table", Type, 0, ""}, + {"Update", Func, 0, "func(crc uint32, tab *Table, p []byte) uint32"}, }, "hash/crc64": { - {"Checksum", Func, 0}, - {"ECMA", Const, 0}, - {"ISO", Const, 0}, - {"MakeTable", Func, 0}, - {"New", Func, 0}, - {"Size", Const, 0}, - {"Table", Type, 0}, - {"Update", Func, 0}, + {"Checksum", Func, 0, "func(data []byte, tab *Table) uint64"}, + {"ECMA", Const, 0, ""}, + {"ISO", Const, 0, ""}, + {"MakeTable", Func, 0, "func(poly uint64) *Table"}, + {"New", Func, 0, "func(tab *Table) hash.Hash64"}, + {"Size", Const, 0, ""}, + {"Table", Type, 0, ""}, + {"Update", Func, 0, "func(crc uint64, tab *Table, p []byte) uint64"}, }, "hash/fnv": { - {"New128", Func, 9}, - {"New128a", Func, 9}, - {"New32", Func, 0}, - {"New32a", Func, 0}, - {"New64", Func, 0}, - {"New64a", Func, 0}, + {"New128", Func, 9, "func() hash.Hash"}, + {"New128a", Func, 9, "func() hash.Hash"}, + {"New32", Func, 0, "func() hash.Hash32"}, + {"New32a", Func, 0, "func() hash.Hash32"}, + {"New64", Func, 0, "func() hash.Hash64"}, + {"New64a", Func, 0, "func() hash.Hash64"}, }, "hash/maphash": { - {"(*Hash).BlockSize", Method, 14}, - {"(*Hash).Reset", Method, 14}, - {"(*Hash).Seed", Method, 14}, - {"(*Hash).SetSeed", Method, 14}, - {"(*Hash).Size", Method, 14}, - {"(*Hash).Sum", Method, 14}, - {"(*Hash).Sum64", Method, 14}, - {"(*Hash).Write", Method, 14}, - {"(*Hash).WriteByte", Method, 14}, - {"(*Hash).WriteString", Method, 14}, - {"Bytes", Func, 19}, - {"Comparable", Func, 24}, - {"Hash", Type, 14}, - {"MakeSeed", Func, 14}, - {"Seed", Type, 14}, - {"String", Func, 19}, - {"WriteComparable", Func, 24}, + {"(*Hash).BlockSize", Method, 14, ""}, + {"(*Hash).Reset", Method, 14, ""}, + {"(*Hash).Seed", Method, 14, ""}, + {"(*Hash).SetSeed", Method, 14, ""}, + {"(*Hash).Size", Method, 14, ""}, + {"(*Hash).Sum", Method, 14, ""}, + {"(*Hash).Sum64", Method, 14, ""}, + {"(*Hash).Write", Method, 14, ""}, + {"(*Hash).WriteByte", Method, 14, ""}, + {"(*Hash).WriteString", Method, 14, ""}, + {"Bytes", Func, 19, "func(seed Seed, b []byte) uint64"}, + {"Comparable", Func, 24, "func[T comparable](seed Seed, v T) uint64"}, + {"Hash", Type, 14, ""}, + {"MakeSeed", Func, 14, "func() Seed"}, + {"Seed", Type, 14, ""}, + {"String", Func, 19, "func(seed Seed, s string) uint64"}, + {"WriteComparable", Func, 24, "func[T comparable](h *Hash, x T)"}, }, "html": { - {"EscapeString", Func, 0}, - {"UnescapeString", Func, 0}, + {"EscapeString", Func, 0, "func(s string) string"}, + {"UnescapeString", Func, 0, "func(s string) string"}, }, "html/template": { - {"(*Error).Error", Method, 0}, - {"(*Template).AddParseTree", Method, 0}, - {"(*Template).Clone", Method, 0}, - {"(*Template).DefinedTemplates", Method, 6}, - {"(*Template).Delims", Method, 0}, - {"(*Template).Execute", Method, 0}, - {"(*Template).ExecuteTemplate", Method, 0}, - {"(*Template).Funcs", Method, 0}, - {"(*Template).Lookup", Method, 0}, - {"(*Template).Name", Method, 0}, - {"(*Template).New", Method, 0}, - {"(*Template).Option", Method, 5}, - {"(*Template).Parse", Method, 0}, - {"(*Template).ParseFS", Method, 16}, - {"(*Template).ParseFiles", Method, 0}, - {"(*Template).ParseGlob", Method, 0}, - {"(*Template).Templates", Method, 0}, - {"CSS", Type, 0}, - {"ErrAmbigContext", Const, 0}, - {"ErrBadHTML", Const, 0}, - {"ErrBranchEnd", Const, 0}, - {"ErrEndContext", Const, 0}, - {"ErrJSTemplate", Const, 21}, - {"ErrNoSuchTemplate", Const, 0}, - {"ErrOutputContext", Const, 0}, - {"ErrPartialCharset", Const, 0}, - {"ErrPartialEscape", Const, 0}, - {"ErrPredefinedEscaper", Const, 9}, - {"ErrRangeLoopReentry", Const, 0}, - {"ErrSlashAmbig", Const, 0}, - {"Error", Type, 0}, - {"Error.Description", Field, 0}, - {"Error.ErrorCode", Field, 0}, - {"Error.Line", Field, 0}, - {"Error.Name", Field, 0}, - {"Error.Node", Field, 4}, - {"ErrorCode", Type, 0}, - {"FuncMap", Type, 0}, - {"HTML", Type, 0}, - {"HTMLAttr", Type, 0}, - {"HTMLEscape", Func, 0}, - {"HTMLEscapeString", Func, 0}, - {"HTMLEscaper", Func, 0}, - {"IsTrue", Func, 6}, - {"JS", Type, 0}, - {"JSEscape", Func, 0}, - {"JSEscapeString", Func, 0}, - {"JSEscaper", Func, 0}, - {"JSStr", Type, 0}, - {"Must", Func, 0}, - {"New", Func, 0}, - {"OK", Const, 0}, - {"ParseFS", Func, 16}, - {"ParseFiles", Func, 0}, - {"ParseGlob", Func, 0}, - {"Srcset", Type, 10}, - {"Template", Type, 0}, - {"Template.Tree", Field, 2}, - {"URL", Type, 0}, - {"URLQueryEscaper", Func, 0}, + {"(*Error).Error", Method, 0, ""}, + {"(*Template).AddParseTree", Method, 0, ""}, + {"(*Template).Clone", Method, 0, ""}, + {"(*Template).DefinedTemplates", Method, 6, ""}, + {"(*Template).Delims", Method, 0, ""}, + {"(*Template).Execute", Method, 0, ""}, + {"(*Template).ExecuteTemplate", Method, 0, ""}, + {"(*Template).Funcs", Method, 0, ""}, + {"(*Template).Lookup", Method, 0, ""}, + {"(*Template).Name", Method, 0, ""}, + {"(*Template).New", Method, 0, ""}, + {"(*Template).Option", Method, 5, ""}, + {"(*Template).Parse", Method, 0, ""}, + {"(*Template).ParseFS", Method, 16, ""}, + {"(*Template).ParseFiles", Method, 0, ""}, + {"(*Template).ParseGlob", Method, 0, ""}, + {"(*Template).Templates", Method, 0, ""}, + {"CSS", Type, 0, ""}, + {"ErrAmbigContext", Const, 0, ""}, + {"ErrBadHTML", Const, 0, ""}, + {"ErrBranchEnd", Const, 0, ""}, + {"ErrEndContext", Const, 0, ""}, + {"ErrJSTemplate", Const, 21, ""}, + {"ErrNoSuchTemplate", Const, 0, ""}, + {"ErrOutputContext", Const, 0, ""}, + {"ErrPartialCharset", Const, 0, ""}, + {"ErrPartialEscape", Const, 0, ""}, + {"ErrPredefinedEscaper", Const, 9, ""}, + {"ErrRangeLoopReentry", Const, 0, ""}, + {"ErrSlashAmbig", Const, 0, ""}, + {"Error", Type, 0, ""}, + {"Error.Description", Field, 0, ""}, + {"Error.ErrorCode", Field, 0, ""}, + {"Error.Line", Field, 0, ""}, + {"Error.Name", Field, 0, ""}, + {"Error.Node", Field, 4, ""}, + {"ErrorCode", Type, 0, ""}, + {"FuncMap", Type, 0, ""}, + {"HTML", Type, 0, ""}, + {"HTMLAttr", Type, 0, ""}, + {"HTMLEscape", Func, 0, "func(w io.Writer, b []byte)"}, + {"HTMLEscapeString", Func, 0, "func(s string) string"}, + {"HTMLEscaper", Func, 0, "func(args ...any) string"}, + {"IsTrue", Func, 6, "func(val any) (truth bool, ok bool)"}, + {"JS", Type, 0, ""}, + {"JSEscape", Func, 0, "func(w io.Writer, b []byte)"}, + {"JSEscapeString", Func, 0, "func(s string) string"}, + {"JSEscaper", Func, 0, "func(args ...any) string"}, + {"JSStr", Type, 0, ""}, + {"Must", Func, 0, "func(t *Template, err error) *Template"}, + {"New", Func, 0, "func(name string) *Template"}, + {"OK", Const, 0, ""}, + {"ParseFS", Func, 16, "func(fs fs.FS, patterns ...string) (*Template, error)"}, + {"ParseFiles", Func, 0, "func(filenames ...string) (*Template, error)"}, + {"ParseGlob", Func, 0, "func(pattern string) (*Template, error)"}, + {"Srcset", Type, 10, ""}, + {"Template", Type, 0, ""}, + {"Template.Tree", Field, 2, ""}, + {"URL", Type, 0, ""}, + {"URLQueryEscaper", Func, 0, "func(args ...any) string"}, }, "image": { - {"(*Alpha).AlphaAt", Method, 4}, - {"(*Alpha).At", Method, 0}, - {"(*Alpha).Bounds", Method, 0}, - {"(*Alpha).ColorModel", Method, 0}, - {"(*Alpha).Opaque", Method, 0}, - {"(*Alpha).PixOffset", Method, 0}, - {"(*Alpha).RGBA64At", Method, 17}, - {"(*Alpha).Set", Method, 0}, - {"(*Alpha).SetAlpha", Method, 0}, - {"(*Alpha).SetRGBA64", Method, 17}, - {"(*Alpha).SubImage", Method, 0}, - {"(*Alpha16).Alpha16At", Method, 4}, - {"(*Alpha16).At", Method, 0}, - {"(*Alpha16).Bounds", Method, 0}, - {"(*Alpha16).ColorModel", Method, 0}, - {"(*Alpha16).Opaque", Method, 0}, - {"(*Alpha16).PixOffset", Method, 0}, - {"(*Alpha16).RGBA64At", Method, 17}, - {"(*Alpha16).Set", Method, 0}, - {"(*Alpha16).SetAlpha16", Method, 0}, - {"(*Alpha16).SetRGBA64", Method, 17}, - {"(*Alpha16).SubImage", Method, 0}, - {"(*CMYK).At", Method, 5}, - {"(*CMYK).Bounds", Method, 5}, - {"(*CMYK).CMYKAt", Method, 5}, - {"(*CMYK).ColorModel", Method, 5}, - {"(*CMYK).Opaque", Method, 5}, - {"(*CMYK).PixOffset", Method, 5}, - {"(*CMYK).RGBA64At", Method, 17}, - {"(*CMYK).Set", Method, 5}, - {"(*CMYK).SetCMYK", Method, 5}, - {"(*CMYK).SetRGBA64", Method, 17}, - {"(*CMYK).SubImage", Method, 5}, - {"(*Gray).At", Method, 0}, - {"(*Gray).Bounds", Method, 0}, - {"(*Gray).ColorModel", Method, 0}, - {"(*Gray).GrayAt", Method, 4}, - {"(*Gray).Opaque", Method, 0}, - {"(*Gray).PixOffset", Method, 0}, - {"(*Gray).RGBA64At", Method, 17}, - {"(*Gray).Set", Method, 0}, - {"(*Gray).SetGray", Method, 0}, - {"(*Gray).SetRGBA64", Method, 17}, - {"(*Gray).SubImage", Method, 0}, - {"(*Gray16).At", Method, 0}, - {"(*Gray16).Bounds", Method, 0}, - {"(*Gray16).ColorModel", Method, 0}, - {"(*Gray16).Gray16At", Method, 4}, - {"(*Gray16).Opaque", Method, 0}, - {"(*Gray16).PixOffset", Method, 0}, - {"(*Gray16).RGBA64At", Method, 17}, - {"(*Gray16).Set", Method, 0}, - {"(*Gray16).SetGray16", Method, 0}, - {"(*Gray16).SetRGBA64", Method, 17}, - {"(*Gray16).SubImage", Method, 0}, - {"(*NRGBA).At", Method, 0}, - {"(*NRGBA).Bounds", Method, 0}, - {"(*NRGBA).ColorModel", Method, 0}, - {"(*NRGBA).NRGBAAt", Method, 4}, - {"(*NRGBA).Opaque", Method, 0}, - {"(*NRGBA).PixOffset", Method, 0}, - {"(*NRGBA).RGBA64At", Method, 17}, - {"(*NRGBA).Set", Method, 0}, - {"(*NRGBA).SetNRGBA", Method, 0}, - {"(*NRGBA).SetRGBA64", Method, 17}, - {"(*NRGBA).SubImage", Method, 0}, - {"(*NRGBA64).At", Method, 0}, - {"(*NRGBA64).Bounds", Method, 0}, - {"(*NRGBA64).ColorModel", Method, 0}, - {"(*NRGBA64).NRGBA64At", Method, 4}, - {"(*NRGBA64).Opaque", Method, 0}, - {"(*NRGBA64).PixOffset", Method, 0}, - {"(*NRGBA64).RGBA64At", Method, 17}, - {"(*NRGBA64).Set", Method, 0}, - {"(*NRGBA64).SetNRGBA64", Method, 0}, - {"(*NRGBA64).SetRGBA64", Method, 17}, - {"(*NRGBA64).SubImage", Method, 0}, - {"(*NYCbCrA).AOffset", Method, 6}, - {"(*NYCbCrA).At", Method, 6}, - {"(*NYCbCrA).Bounds", Method, 6}, - {"(*NYCbCrA).COffset", Method, 6}, - {"(*NYCbCrA).ColorModel", Method, 6}, - {"(*NYCbCrA).NYCbCrAAt", Method, 6}, - {"(*NYCbCrA).Opaque", Method, 6}, - {"(*NYCbCrA).RGBA64At", Method, 17}, - {"(*NYCbCrA).SubImage", Method, 6}, - {"(*NYCbCrA).YCbCrAt", Method, 6}, - {"(*NYCbCrA).YOffset", Method, 6}, - {"(*Paletted).At", Method, 0}, - {"(*Paletted).Bounds", Method, 0}, - {"(*Paletted).ColorIndexAt", Method, 0}, - {"(*Paletted).ColorModel", Method, 0}, - {"(*Paletted).Opaque", Method, 0}, - {"(*Paletted).PixOffset", Method, 0}, - {"(*Paletted).RGBA64At", Method, 17}, - {"(*Paletted).Set", Method, 0}, - {"(*Paletted).SetColorIndex", Method, 0}, - {"(*Paletted).SetRGBA64", Method, 17}, - {"(*Paletted).SubImage", Method, 0}, - {"(*RGBA).At", Method, 0}, - {"(*RGBA).Bounds", Method, 0}, - {"(*RGBA).ColorModel", Method, 0}, - {"(*RGBA).Opaque", Method, 0}, - {"(*RGBA).PixOffset", Method, 0}, - {"(*RGBA).RGBA64At", Method, 17}, - {"(*RGBA).RGBAAt", Method, 4}, - {"(*RGBA).Set", Method, 0}, - {"(*RGBA).SetRGBA", Method, 0}, - {"(*RGBA).SetRGBA64", Method, 17}, - {"(*RGBA).SubImage", Method, 0}, - {"(*RGBA64).At", Method, 0}, - {"(*RGBA64).Bounds", Method, 0}, - {"(*RGBA64).ColorModel", Method, 0}, - {"(*RGBA64).Opaque", Method, 0}, - {"(*RGBA64).PixOffset", Method, 0}, - {"(*RGBA64).RGBA64At", Method, 4}, - {"(*RGBA64).Set", Method, 0}, - {"(*RGBA64).SetRGBA64", Method, 0}, - {"(*RGBA64).SubImage", Method, 0}, - {"(*Uniform).At", Method, 0}, - {"(*Uniform).Bounds", Method, 0}, - {"(*Uniform).ColorModel", Method, 0}, - {"(*Uniform).Convert", Method, 0}, - {"(*Uniform).Opaque", Method, 0}, - {"(*Uniform).RGBA", Method, 0}, - {"(*Uniform).RGBA64At", Method, 17}, - {"(*YCbCr).At", Method, 0}, - {"(*YCbCr).Bounds", Method, 0}, - {"(*YCbCr).COffset", Method, 0}, - {"(*YCbCr).ColorModel", Method, 0}, - {"(*YCbCr).Opaque", Method, 0}, - {"(*YCbCr).RGBA64At", Method, 17}, - {"(*YCbCr).SubImage", Method, 0}, - {"(*YCbCr).YCbCrAt", Method, 4}, - {"(*YCbCr).YOffset", Method, 0}, - {"(Point).Add", Method, 0}, - {"(Point).Div", Method, 0}, - {"(Point).Eq", Method, 0}, - {"(Point).In", Method, 0}, - {"(Point).Mod", Method, 0}, - {"(Point).Mul", Method, 0}, - {"(Point).String", Method, 0}, - {"(Point).Sub", Method, 0}, - {"(Rectangle).Add", Method, 0}, - {"(Rectangle).At", Method, 5}, - {"(Rectangle).Bounds", Method, 5}, - {"(Rectangle).Canon", Method, 0}, - {"(Rectangle).ColorModel", Method, 5}, - {"(Rectangle).Dx", Method, 0}, - {"(Rectangle).Dy", Method, 0}, - {"(Rectangle).Empty", Method, 0}, - {"(Rectangle).Eq", Method, 0}, - {"(Rectangle).In", Method, 0}, - {"(Rectangle).Inset", Method, 0}, - {"(Rectangle).Intersect", Method, 0}, - {"(Rectangle).Overlaps", Method, 0}, - {"(Rectangle).RGBA64At", Method, 17}, - {"(Rectangle).Size", Method, 0}, - {"(Rectangle).String", Method, 0}, - {"(Rectangle).Sub", Method, 0}, - {"(Rectangle).Union", Method, 0}, - {"(YCbCrSubsampleRatio).String", Method, 0}, - {"Alpha", Type, 0}, - {"Alpha.Pix", Field, 0}, - {"Alpha.Rect", Field, 0}, - {"Alpha.Stride", Field, 0}, - {"Alpha16", Type, 0}, - {"Alpha16.Pix", Field, 0}, - {"Alpha16.Rect", Field, 0}, - {"Alpha16.Stride", Field, 0}, - {"Black", Var, 0}, - {"CMYK", Type, 5}, - {"CMYK.Pix", Field, 5}, - {"CMYK.Rect", Field, 5}, - {"CMYK.Stride", Field, 5}, - {"Config", Type, 0}, - {"Config.ColorModel", Field, 0}, - {"Config.Height", Field, 0}, - {"Config.Width", Field, 0}, - {"Decode", Func, 0}, - {"DecodeConfig", Func, 0}, - {"ErrFormat", Var, 0}, - {"Gray", Type, 0}, - {"Gray.Pix", Field, 0}, - {"Gray.Rect", Field, 0}, - {"Gray.Stride", Field, 0}, - {"Gray16", Type, 0}, - {"Gray16.Pix", Field, 0}, - {"Gray16.Rect", Field, 0}, - {"Gray16.Stride", Field, 0}, - {"Image", Type, 0}, - {"NRGBA", Type, 0}, - {"NRGBA.Pix", Field, 0}, - {"NRGBA.Rect", Field, 0}, - {"NRGBA.Stride", Field, 0}, - {"NRGBA64", Type, 0}, - {"NRGBA64.Pix", Field, 0}, - {"NRGBA64.Rect", Field, 0}, - {"NRGBA64.Stride", Field, 0}, - {"NYCbCrA", Type, 6}, - {"NYCbCrA.A", Field, 6}, - {"NYCbCrA.AStride", Field, 6}, - {"NYCbCrA.YCbCr", Field, 6}, - {"NewAlpha", Func, 0}, - {"NewAlpha16", Func, 0}, - {"NewCMYK", Func, 5}, - {"NewGray", Func, 0}, - {"NewGray16", Func, 0}, - {"NewNRGBA", Func, 0}, - {"NewNRGBA64", Func, 0}, - {"NewNYCbCrA", Func, 6}, - {"NewPaletted", Func, 0}, - {"NewRGBA", Func, 0}, - {"NewRGBA64", Func, 0}, - {"NewUniform", Func, 0}, - {"NewYCbCr", Func, 0}, - {"Opaque", Var, 0}, - {"Paletted", Type, 0}, - {"Paletted.Palette", Field, 0}, - {"Paletted.Pix", Field, 0}, - {"Paletted.Rect", Field, 0}, - {"Paletted.Stride", Field, 0}, - {"PalettedImage", Type, 0}, - {"Point", Type, 0}, - {"Point.X", Field, 0}, - {"Point.Y", Field, 0}, - {"Pt", Func, 0}, - {"RGBA", Type, 0}, - {"RGBA.Pix", Field, 0}, - {"RGBA.Rect", Field, 0}, - {"RGBA.Stride", Field, 0}, - {"RGBA64", Type, 0}, - {"RGBA64.Pix", Field, 0}, - {"RGBA64.Rect", Field, 0}, - {"RGBA64.Stride", Field, 0}, - {"RGBA64Image", Type, 17}, - {"Rect", Func, 0}, - {"Rectangle", Type, 0}, - {"Rectangle.Max", Field, 0}, - {"Rectangle.Min", Field, 0}, - {"RegisterFormat", Func, 0}, - {"Transparent", Var, 0}, - {"Uniform", Type, 0}, - {"Uniform.C", Field, 0}, - {"White", Var, 0}, - {"YCbCr", Type, 0}, - {"YCbCr.CStride", Field, 0}, - {"YCbCr.Cb", Field, 0}, - {"YCbCr.Cr", Field, 0}, - {"YCbCr.Rect", Field, 0}, - {"YCbCr.SubsampleRatio", Field, 0}, - {"YCbCr.Y", Field, 0}, - {"YCbCr.YStride", Field, 0}, - {"YCbCrSubsampleRatio", Type, 0}, - {"YCbCrSubsampleRatio410", Const, 5}, - {"YCbCrSubsampleRatio411", Const, 5}, - {"YCbCrSubsampleRatio420", Const, 0}, - {"YCbCrSubsampleRatio422", Const, 0}, - {"YCbCrSubsampleRatio440", Const, 1}, - {"YCbCrSubsampleRatio444", Const, 0}, - {"ZP", Var, 0}, - {"ZR", Var, 0}, + {"(*Alpha).AlphaAt", Method, 4, ""}, + {"(*Alpha).At", Method, 0, ""}, + {"(*Alpha).Bounds", Method, 0, ""}, + {"(*Alpha).ColorModel", Method, 0, ""}, + {"(*Alpha).Opaque", Method, 0, ""}, + {"(*Alpha).PixOffset", Method, 0, ""}, + {"(*Alpha).RGBA64At", Method, 17, ""}, + {"(*Alpha).Set", Method, 0, ""}, + {"(*Alpha).SetAlpha", Method, 0, ""}, + {"(*Alpha).SetRGBA64", Method, 17, ""}, + {"(*Alpha).SubImage", Method, 0, ""}, + {"(*Alpha16).Alpha16At", Method, 4, ""}, + {"(*Alpha16).At", Method, 0, ""}, + {"(*Alpha16).Bounds", Method, 0, ""}, + {"(*Alpha16).ColorModel", Method, 0, ""}, + {"(*Alpha16).Opaque", Method, 0, ""}, + {"(*Alpha16).PixOffset", Method, 0, ""}, + {"(*Alpha16).RGBA64At", Method, 17, ""}, + {"(*Alpha16).Set", Method, 0, ""}, + {"(*Alpha16).SetAlpha16", Method, 0, ""}, + {"(*Alpha16).SetRGBA64", Method, 17, ""}, + {"(*Alpha16).SubImage", Method, 0, ""}, + {"(*CMYK).At", Method, 5, ""}, + {"(*CMYK).Bounds", Method, 5, ""}, + {"(*CMYK).CMYKAt", Method, 5, ""}, + {"(*CMYK).ColorModel", Method, 5, ""}, + {"(*CMYK).Opaque", Method, 5, ""}, + {"(*CMYK).PixOffset", Method, 5, ""}, + {"(*CMYK).RGBA64At", Method, 17, ""}, + {"(*CMYK).Set", Method, 5, ""}, + {"(*CMYK).SetCMYK", Method, 5, ""}, + {"(*CMYK).SetRGBA64", Method, 17, ""}, + {"(*CMYK).SubImage", Method, 5, ""}, + {"(*Gray).At", Method, 0, ""}, + {"(*Gray).Bounds", Method, 0, ""}, + {"(*Gray).ColorModel", Method, 0, ""}, + {"(*Gray).GrayAt", Method, 4, ""}, + {"(*Gray).Opaque", Method, 0, ""}, + {"(*Gray).PixOffset", Method, 0, ""}, + {"(*Gray).RGBA64At", Method, 17, ""}, + {"(*Gray).Set", Method, 0, ""}, + {"(*Gray).SetGray", Method, 0, ""}, + {"(*Gray).SetRGBA64", Method, 17, ""}, + {"(*Gray).SubImage", Method, 0, ""}, + {"(*Gray16).At", Method, 0, ""}, + {"(*Gray16).Bounds", Method, 0, ""}, + {"(*Gray16).ColorModel", Method, 0, ""}, + {"(*Gray16).Gray16At", Method, 4, ""}, + {"(*Gray16).Opaque", Method, 0, ""}, + {"(*Gray16).PixOffset", Method, 0, ""}, + {"(*Gray16).RGBA64At", Method, 17, ""}, + {"(*Gray16).Set", Method, 0, ""}, + {"(*Gray16).SetGray16", Method, 0, ""}, + {"(*Gray16).SetRGBA64", Method, 17, ""}, + {"(*Gray16).SubImage", Method, 0, ""}, + {"(*NRGBA).At", Method, 0, ""}, + {"(*NRGBA).Bounds", Method, 0, ""}, + {"(*NRGBA).ColorModel", Method, 0, ""}, + {"(*NRGBA).NRGBAAt", Method, 4, ""}, + {"(*NRGBA).Opaque", Method, 0, ""}, + {"(*NRGBA).PixOffset", Method, 0, ""}, + {"(*NRGBA).RGBA64At", Method, 17, ""}, + {"(*NRGBA).Set", Method, 0, ""}, + {"(*NRGBA).SetNRGBA", Method, 0, ""}, + {"(*NRGBA).SetRGBA64", Method, 17, ""}, + {"(*NRGBA).SubImage", Method, 0, ""}, + {"(*NRGBA64).At", Method, 0, ""}, + {"(*NRGBA64).Bounds", Method, 0, ""}, + {"(*NRGBA64).ColorModel", Method, 0, ""}, + {"(*NRGBA64).NRGBA64At", Method, 4, ""}, + {"(*NRGBA64).Opaque", Method, 0, ""}, + {"(*NRGBA64).PixOffset", Method, 0, ""}, + {"(*NRGBA64).RGBA64At", Method, 17, ""}, + {"(*NRGBA64).Set", Method, 0, ""}, + {"(*NRGBA64).SetNRGBA64", Method, 0, ""}, + {"(*NRGBA64).SetRGBA64", Method, 17, ""}, + {"(*NRGBA64).SubImage", Method, 0, ""}, + {"(*NYCbCrA).AOffset", Method, 6, ""}, + {"(*NYCbCrA).At", Method, 6, ""}, + {"(*NYCbCrA).Bounds", Method, 6, ""}, + {"(*NYCbCrA).COffset", Method, 6, ""}, + {"(*NYCbCrA).ColorModel", Method, 6, ""}, + {"(*NYCbCrA).NYCbCrAAt", Method, 6, ""}, + {"(*NYCbCrA).Opaque", Method, 6, ""}, + {"(*NYCbCrA).RGBA64At", Method, 17, ""}, + {"(*NYCbCrA).SubImage", Method, 6, ""}, + {"(*NYCbCrA).YCbCrAt", Method, 6, ""}, + {"(*NYCbCrA).YOffset", Method, 6, ""}, + {"(*Paletted).At", Method, 0, ""}, + {"(*Paletted).Bounds", Method, 0, ""}, + {"(*Paletted).ColorIndexAt", Method, 0, ""}, + {"(*Paletted).ColorModel", Method, 0, ""}, + {"(*Paletted).Opaque", Method, 0, ""}, + {"(*Paletted).PixOffset", Method, 0, ""}, + {"(*Paletted).RGBA64At", Method, 17, ""}, + {"(*Paletted).Set", Method, 0, ""}, + {"(*Paletted).SetColorIndex", Method, 0, ""}, + {"(*Paletted).SetRGBA64", Method, 17, ""}, + {"(*Paletted).SubImage", Method, 0, ""}, + {"(*RGBA).At", Method, 0, ""}, + {"(*RGBA).Bounds", Method, 0, ""}, + {"(*RGBA).ColorModel", Method, 0, ""}, + {"(*RGBA).Opaque", Method, 0, ""}, + {"(*RGBA).PixOffset", Method, 0, ""}, + {"(*RGBA).RGBA64At", Method, 17, ""}, + {"(*RGBA).RGBAAt", Method, 4, ""}, + {"(*RGBA).Set", Method, 0, ""}, + {"(*RGBA).SetRGBA", Method, 0, ""}, + {"(*RGBA).SetRGBA64", Method, 17, ""}, + {"(*RGBA).SubImage", Method, 0, ""}, + {"(*RGBA64).At", Method, 0, ""}, + {"(*RGBA64).Bounds", Method, 0, ""}, + {"(*RGBA64).ColorModel", Method, 0, ""}, + {"(*RGBA64).Opaque", Method, 0, ""}, + {"(*RGBA64).PixOffset", Method, 0, ""}, + {"(*RGBA64).RGBA64At", Method, 4, ""}, + {"(*RGBA64).Set", Method, 0, ""}, + {"(*RGBA64).SetRGBA64", Method, 0, ""}, + {"(*RGBA64).SubImage", Method, 0, ""}, + {"(*Uniform).At", Method, 0, ""}, + {"(*Uniform).Bounds", Method, 0, ""}, + {"(*Uniform).ColorModel", Method, 0, ""}, + {"(*Uniform).Convert", Method, 0, ""}, + {"(*Uniform).Opaque", Method, 0, ""}, + {"(*Uniform).RGBA", Method, 0, ""}, + {"(*Uniform).RGBA64At", Method, 17, ""}, + {"(*YCbCr).At", Method, 0, ""}, + {"(*YCbCr).Bounds", Method, 0, ""}, + {"(*YCbCr).COffset", Method, 0, ""}, + {"(*YCbCr).ColorModel", Method, 0, ""}, + {"(*YCbCr).Opaque", Method, 0, ""}, + {"(*YCbCr).RGBA64At", Method, 17, ""}, + {"(*YCbCr).SubImage", Method, 0, ""}, + {"(*YCbCr).YCbCrAt", Method, 4, ""}, + {"(*YCbCr).YOffset", Method, 0, ""}, + {"(Point).Add", Method, 0, ""}, + {"(Point).Div", Method, 0, ""}, + {"(Point).Eq", Method, 0, ""}, + {"(Point).In", Method, 0, ""}, + {"(Point).Mod", Method, 0, ""}, + {"(Point).Mul", Method, 0, ""}, + {"(Point).String", Method, 0, ""}, + {"(Point).Sub", Method, 0, ""}, + {"(Rectangle).Add", Method, 0, ""}, + {"(Rectangle).At", Method, 5, ""}, + {"(Rectangle).Bounds", Method, 5, ""}, + {"(Rectangle).Canon", Method, 0, ""}, + {"(Rectangle).ColorModel", Method, 5, ""}, + {"(Rectangle).Dx", Method, 0, ""}, + {"(Rectangle).Dy", Method, 0, ""}, + {"(Rectangle).Empty", Method, 0, ""}, + {"(Rectangle).Eq", Method, 0, ""}, + {"(Rectangle).In", Method, 0, ""}, + {"(Rectangle).Inset", Method, 0, ""}, + {"(Rectangle).Intersect", Method, 0, ""}, + {"(Rectangle).Overlaps", Method, 0, ""}, + {"(Rectangle).RGBA64At", Method, 17, ""}, + {"(Rectangle).Size", Method, 0, ""}, + {"(Rectangle).String", Method, 0, ""}, + {"(Rectangle).Sub", Method, 0, ""}, + {"(Rectangle).Union", Method, 0, ""}, + {"(YCbCrSubsampleRatio).String", Method, 0, ""}, + {"Alpha", Type, 0, ""}, + {"Alpha.Pix", Field, 0, ""}, + {"Alpha.Rect", Field, 0, ""}, + {"Alpha.Stride", Field, 0, ""}, + {"Alpha16", Type, 0, ""}, + {"Alpha16.Pix", Field, 0, ""}, + {"Alpha16.Rect", Field, 0, ""}, + {"Alpha16.Stride", Field, 0, ""}, + {"Black", Var, 0, ""}, + {"CMYK", Type, 5, ""}, + {"CMYK.Pix", Field, 5, ""}, + {"CMYK.Rect", Field, 5, ""}, + {"CMYK.Stride", Field, 5, ""}, + {"Config", Type, 0, ""}, + {"Config.ColorModel", Field, 0, ""}, + {"Config.Height", Field, 0, ""}, + {"Config.Width", Field, 0, ""}, + {"Decode", Func, 0, "func(r io.Reader) (Image, string, error)"}, + {"DecodeConfig", Func, 0, "func(r io.Reader) (Config, string, error)"}, + {"ErrFormat", Var, 0, ""}, + {"Gray", Type, 0, ""}, + {"Gray.Pix", Field, 0, ""}, + {"Gray.Rect", Field, 0, ""}, + {"Gray.Stride", Field, 0, ""}, + {"Gray16", Type, 0, ""}, + {"Gray16.Pix", Field, 0, ""}, + {"Gray16.Rect", Field, 0, ""}, + {"Gray16.Stride", Field, 0, ""}, + {"Image", Type, 0, ""}, + {"NRGBA", Type, 0, ""}, + {"NRGBA.Pix", Field, 0, ""}, + {"NRGBA.Rect", Field, 0, ""}, + {"NRGBA.Stride", Field, 0, ""}, + {"NRGBA64", Type, 0, ""}, + {"NRGBA64.Pix", Field, 0, ""}, + {"NRGBA64.Rect", Field, 0, ""}, + {"NRGBA64.Stride", Field, 0, ""}, + {"NYCbCrA", Type, 6, ""}, + {"NYCbCrA.A", Field, 6, ""}, + {"NYCbCrA.AStride", Field, 6, ""}, + {"NYCbCrA.YCbCr", Field, 6, ""}, + {"NewAlpha", Func, 0, "func(r Rectangle) *Alpha"}, + {"NewAlpha16", Func, 0, "func(r Rectangle) *Alpha16"}, + {"NewCMYK", Func, 5, "func(r Rectangle) *CMYK"}, + {"NewGray", Func, 0, "func(r Rectangle) *Gray"}, + {"NewGray16", Func, 0, "func(r Rectangle) *Gray16"}, + {"NewNRGBA", Func, 0, "func(r Rectangle) *NRGBA"}, + {"NewNRGBA64", Func, 0, "func(r Rectangle) *NRGBA64"}, + {"NewNYCbCrA", Func, 6, "func(r Rectangle, subsampleRatio YCbCrSubsampleRatio) *NYCbCrA"}, + {"NewPaletted", Func, 0, "func(r Rectangle, p color.Palette) *Paletted"}, + {"NewRGBA", Func, 0, "func(r Rectangle) *RGBA"}, + {"NewRGBA64", Func, 0, "func(r Rectangle) *RGBA64"}, + {"NewUniform", Func, 0, "func(c color.Color) *Uniform"}, + {"NewYCbCr", Func, 0, "func(r Rectangle, subsampleRatio YCbCrSubsampleRatio) *YCbCr"}, + {"Opaque", Var, 0, ""}, + {"Paletted", Type, 0, ""}, + {"Paletted.Palette", Field, 0, ""}, + {"Paletted.Pix", Field, 0, ""}, + {"Paletted.Rect", Field, 0, ""}, + {"Paletted.Stride", Field, 0, ""}, + {"PalettedImage", Type, 0, ""}, + {"Point", Type, 0, ""}, + {"Point.X", Field, 0, ""}, + {"Point.Y", Field, 0, ""}, + {"Pt", Func, 0, "func(X int, Y int) Point"}, + {"RGBA", Type, 0, ""}, + {"RGBA.Pix", Field, 0, ""}, + {"RGBA.Rect", Field, 0, ""}, + {"RGBA.Stride", Field, 0, ""}, + {"RGBA64", Type, 0, ""}, + {"RGBA64.Pix", Field, 0, ""}, + {"RGBA64.Rect", Field, 0, ""}, + {"RGBA64.Stride", Field, 0, ""}, + {"RGBA64Image", Type, 17, ""}, + {"Rect", Func, 0, "func(x0 int, y0 int, x1 int, y1 int) Rectangle"}, + {"Rectangle", Type, 0, ""}, + {"Rectangle.Max", Field, 0, ""}, + {"Rectangle.Min", Field, 0, ""}, + {"RegisterFormat", Func, 0, "func(name string, magic string, decode func(io.Reader) (Image, error), decodeConfig func(io.Reader) (Config, error))"}, + {"Transparent", Var, 0, ""}, + {"Uniform", Type, 0, ""}, + {"Uniform.C", Field, 0, ""}, + {"White", Var, 0, ""}, + {"YCbCr", Type, 0, ""}, + {"YCbCr.CStride", Field, 0, ""}, + {"YCbCr.Cb", Field, 0, ""}, + {"YCbCr.Cr", Field, 0, ""}, + {"YCbCr.Rect", Field, 0, ""}, + {"YCbCr.SubsampleRatio", Field, 0, ""}, + {"YCbCr.Y", Field, 0, ""}, + {"YCbCr.YStride", Field, 0, ""}, + {"YCbCrSubsampleRatio", Type, 0, ""}, + {"YCbCrSubsampleRatio410", Const, 5, ""}, + {"YCbCrSubsampleRatio411", Const, 5, ""}, + {"YCbCrSubsampleRatio420", Const, 0, ""}, + {"YCbCrSubsampleRatio422", Const, 0, ""}, + {"YCbCrSubsampleRatio440", Const, 1, ""}, + {"YCbCrSubsampleRatio444", Const, 0, ""}, + {"ZP", Var, 0, ""}, + {"ZR", Var, 0, ""}, }, "image/color": { - {"(Alpha).RGBA", Method, 0}, - {"(Alpha16).RGBA", Method, 0}, - {"(CMYK).RGBA", Method, 5}, - {"(Gray).RGBA", Method, 0}, - {"(Gray16).RGBA", Method, 0}, - {"(NRGBA).RGBA", Method, 0}, - {"(NRGBA64).RGBA", Method, 0}, - {"(NYCbCrA).RGBA", Method, 6}, - {"(Palette).Convert", Method, 0}, - {"(Palette).Index", Method, 0}, - {"(RGBA).RGBA", Method, 0}, - {"(RGBA64).RGBA", Method, 0}, - {"(YCbCr).RGBA", Method, 0}, - {"Alpha", Type, 0}, - {"Alpha.A", Field, 0}, - {"Alpha16", Type, 0}, - {"Alpha16.A", Field, 0}, - {"Alpha16Model", Var, 0}, - {"AlphaModel", Var, 0}, - {"Black", Var, 0}, - {"CMYK", Type, 5}, - {"CMYK.C", Field, 5}, - {"CMYK.K", Field, 5}, - {"CMYK.M", Field, 5}, - {"CMYK.Y", Field, 5}, - {"CMYKModel", Var, 5}, - {"CMYKToRGB", Func, 5}, - {"Color", Type, 0}, - {"Gray", Type, 0}, - {"Gray.Y", Field, 0}, - {"Gray16", Type, 0}, - {"Gray16.Y", Field, 0}, - {"Gray16Model", Var, 0}, - {"GrayModel", Var, 0}, - {"Model", Type, 0}, - {"ModelFunc", Func, 0}, - {"NRGBA", Type, 0}, - {"NRGBA.A", Field, 0}, - {"NRGBA.B", Field, 0}, - {"NRGBA.G", Field, 0}, - {"NRGBA.R", Field, 0}, - {"NRGBA64", Type, 0}, - {"NRGBA64.A", Field, 0}, - {"NRGBA64.B", Field, 0}, - {"NRGBA64.G", Field, 0}, - {"NRGBA64.R", Field, 0}, - {"NRGBA64Model", Var, 0}, - {"NRGBAModel", Var, 0}, - {"NYCbCrA", Type, 6}, - {"NYCbCrA.A", Field, 6}, - {"NYCbCrA.YCbCr", Field, 6}, - {"NYCbCrAModel", Var, 6}, - {"Opaque", Var, 0}, - {"Palette", Type, 0}, - {"RGBA", Type, 0}, - {"RGBA.A", Field, 0}, - {"RGBA.B", Field, 0}, - {"RGBA.G", Field, 0}, - {"RGBA.R", Field, 0}, - {"RGBA64", Type, 0}, - {"RGBA64.A", Field, 0}, - {"RGBA64.B", Field, 0}, - {"RGBA64.G", Field, 0}, - {"RGBA64.R", Field, 0}, - {"RGBA64Model", Var, 0}, - {"RGBAModel", Var, 0}, - {"RGBToCMYK", Func, 5}, - {"RGBToYCbCr", Func, 0}, - {"Transparent", Var, 0}, - {"White", Var, 0}, - {"YCbCr", Type, 0}, - {"YCbCr.Cb", Field, 0}, - {"YCbCr.Cr", Field, 0}, - {"YCbCr.Y", Field, 0}, - {"YCbCrModel", Var, 0}, - {"YCbCrToRGB", Func, 0}, + {"(Alpha).RGBA", Method, 0, ""}, + {"(Alpha16).RGBA", Method, 0, ""}, + {"(CMYK).RGBA", Method, 5, ""}, + {"(Gray).RGBA", Method, 0, ""}, + {"(Gray16).RGBA", Method, 0, ""}, + {"(NRGBA).RGBA", Method, 0, ""}, + {"(NRGBA64).RGBA", Method, 0, ""}, + {"(NYCbCrA).RGBA", Method, 6, ""}, + {"(Palette).Convert", Method, 0, ""}, + {"(Palette).Index", Method, 0, ""}, + {"(RGBA).RGBA", Method, 0, ""}, + {"(RGBA64).RGBA", Method, 0, ""}, + {"(YCbCr).RGBA", Method, 0, ""}, + {"Alpha", Type, 0, ""}, + {"Alpha.A", Field, 0, ""}, + {"Alpha16", Type, 0, ""}, + {"Alpha16.A", Field, 0, ""}, + {"Alpha16Model", Var, 0, ""}, + {"AlphaModel", Var, 0, ""}, + {"Black", Var, 0, ""}, + {"CMYK", Type, 5, ""}, + {"CMYK.C", Field, 5, ""}, + {"CMYK.K", Field, 5, ""}, + {"CMYK.M", Field, 5, ""}, + {"CMYK.Y", Field, 5, ""}, + {"CMYKModel", Var, 5, ""}, + {"CMYKToRGB", Func, 5, "func(c uint8, m uint8, y uint8, k uint8) (uint8, uint8, uint8)"}, + {"Color", Type, 0, ""}, + {"Gray", Type, 0, ""}, + {"Gray.Y", Field, 0, ""}, + {"Gray16", Type, 0, ""}, + {"Gray16.Y", Field, 0, ""}, + {"Gray16Model", Var, 0, ""}, + {"GrayModel", Var, 0, ""}, + {"Model", Type, 0, ""}, + {"ModelFunc", Func, 0, "func(f func(Color) Color) Model"}, + {"NRGBA", Type, 0, ""}, + {"NRGBA.A", Field, 0, ""}, + {"NRGBA.B", Field, 0, ""}, + {"NRGBA.G", Field, 0, ""}, + {"NRGBA.R", Field, 0, ""}, + {"NRGBA64", Type, 0, ""}, + {"NRGBA64.A", Field, 0, ""}, + {"NRGBA64.B", Field, 0, ""}, + {"NRGBA64.G", Field, 0, ""}, + {"NRGBA64.R", Field, 0, ""}, + {"NRGBA64Model", Var, 0, ""}, + {"NRGBAModel", Var, 0, ""}, + {"NYCbCrA", Type, 6, ""}, + {"NYCbCrA.A", Field, 6, ""}, + {"NYCbCrA.YCbCr", Field, 6, ""}, + {"NYCbCrAModel", Var, 6, ""}, + {"Opaque", Var, 0, ""}, + {"Palette", Type, 0, ""}, + {"RGBA", Type, 0, ""}, + {"RGBA.A", Field, 0, ""}, + {"RGBA.B", Field, 0, ""}, + {"RGBA.G", Field, 0, ""}, + {"RGBA.R", Field, 0, ""}, + {"RGBA64", Type, 0, ""}, + {"RGBA64.A", Field, 0, ""}, + {"RGBA64.B", Field, 0, ""}, + {"RGBA64.G", Field, 0, ""}, + {"RGBA64.R", Field, 0, ""}, + {"RGBA64Model", Var, 0, ""}, + {"RGBAModel", Var, 0, ""}, + {"RGBToCMYK", Func, 5, "func(r uint8, g uint8, b uint8) (uint8, uint8, uint8, uint8)"}, + {"RGBToYCbCr", Func, 0, "func(r uint8, g uint8, b uint8) (uint8, uint8, uint8)"}, + {"Transparent", Var, 0, ""}, + {"White", Var, 0, ""}, + {"YCbCr", Type, 0, ""}, + {"YCbCr.Cb", Field, 0, ""}, + {"YCbCr.Cr", Field, 0, ""}, + {"YCbCr.Y", Field, 0, ""}, + {"YCbCrModel", Var, 0, ""}, + {"YCbCrToRGB", Func, 0, "func(y uint8, cb uint8, cr uint8) (uint8, uint8, uint8)"}, }, "image/color/palette": { - {"Plan9", Var, 2}, - {"WebSafe", Var, 2}, + {"Plan9", Var, 2, ""}, + {"WebSafe", Var, 2, ""}, }, "image/draw": { - {"(Op).Draw", Method, 2}, - {"Draw", Func, 0}, - {"DrawMask", Func, 0}, - {"Drawer", Type, 2}, - {"FloydSteinberg", Var, 2}, - {"Image", Type, 0}, - {"Op", Type, 0}, - {"Over", Const, 0}, - {"Quantizer", Type, 2}, - {"RGBA64Image", Type, 17}, - {"Src", Const, 0}, + {"(Op).Draw", Method, 2, ""}, + {"Draw", Func, 0, "func(dst Image, r image.Rectangle, src image.Image, sp image.Point, op Op)"}, + {"DrawMask", Func, 0, "func(dst Image, r image.Rectangle, src image.Image, sp image.Point, mask image.Image, mp image.Point, op Op)"}, + {"Drawer", Type, 2, ""}, + {"FloydSteinberg", Var, 2, ""}, + {"Image", Type, 0, ""}, + {"Op", Type, 0, ""}, + {"Over", Const, 0, ""}, + {"Quantizer", Type, 2, ""}, + {"RGBA64Image", Type, 17, ""}, + {"Src", Const, 0, ""}, }, "image/gif": { - {"Decode", Func, 0}, - {"DecodeAll", Func, 0}, - {"DecodeConfig", Func, 0}, - {"DisposalBackground", Const, 5}, - {"DisposalNone", Const, 5}, - {"DisposalPrevious", Const, 5}, - {"Encode", Func, 2}, - {"EncodeAll", Func, 2}, - {"GIF", Type, 0}, - {"GIF.BackgroundIndex", Field, 5}, - {"GIF.Config", Field, 5}, - {"GIF.Delay", Field, 0}, - {"GIF.Disposal", Field, 5}, - {"GIF.Image", Field, 0}, - {"GIF.LoopCount", Field, 0}, - {"Options", Type, 2}, - {"Options.Drawer", Field, 2}, - {"Options.NumColors", Field, 2}, - {"Options.Quantizer", Field, 2}, + {"Decode", Func, 0, "func(r io.Reader) (image.Image, error)"}, + {"DecodeAll", Func, 0, "func(r io.Reader) (*GIF, error)"}, + {"DecodeConfig", Func, 0, "func(r io.Reader) (image.Config, error)"}, + {"DisposalBackground", Const, 5, ""}, + {"DisposalNone", Const, 5, ""}, + {"DisposalPrevious", Const, 5, ""}, + {"Encode", Func, 2, "func(w io.Writer, m image.Image, o *Options) error"}, + {"EncodeAll", Func, 2, "func(w io.Writer, g *GIF) error"}, + {"GIF", Type, 0, ""}, + {"GIF.BackgroundIndex", Field, 5, ""}, + {"GIF.Config", Field, 5, ""}, + {"GIF.Delay", Field, 0, ""}, + {"GIF.Disposal", Field, 5, ""}, + {"GIF.Image", Field, 0, ""}, + {"GIF.LoopCount", Field, 0, ""}, + {"Options", Type, 2, ""}, + {"Options.Drawer", Field, 2, ""}, + {"Options.NumColors", Field, 2, ""}, + {"Options.Quantizer", Field, 2, ""}, }, "image/jpeg": { - {"(FormatError).Error", Method, 0}, - {"(UnsupportedError).Error", Method, 0}, - {"Decode", Func, 0}, - {"DecodeConfig", Func, 0}, - {"DefaultQuality", Const, 0}, - {"Encode", Func, 0}, - {"FormatError", Type, 0}, - {"Options", Type, 0}, - {"Options.Quality", Field, 0}, - {"Reader", Type, 0}, - {"UnsupportedError", Type, 0}, + {"(FormatError).Error", Method, 0, ""}, + {"(UnsupportedError).Error", Method, 0, ""}, + {"Decode", Func, 0, "func(r io.Reader) (image.Image, error)"}, + {"DecodeConfig", Func, 0, "func(r io.Reader) (image.Config, error)"}, + {"DefaultQuality", Const, 0, ""}, + {"Encode", Func, 0, "func(w io.Writer, m image.Image, o *Options) error"}, + {"FormatError", Type, 0, ""}, + {"Options", Type, 0, ""}, + {"Options.Quality", Field, 0, ""}, + {"Reader", Type, 0, ""}, + {"UnsupportedError", Type, 0, ""}, }, "image/png": { - {"(*Encoder).Encode", Method, 4}, - {"(FormatError).Error", Method, 0}, - {"(UnsupportedError).Error", Method, 0}, - {"BestCompression", Const, 4}, - {"BestSpeed", Const, 4}, - {"CompressionLevel", Type, 4}, - {"Decode", Func, 0}, - {"DecodeConfig", Func, 0}, - {"DefaultCompression", Const, 4}, - {"Encode", Func, 0}, - {"Encoder", Type, 4}, - {"Encoder.BufferPool", Field, 9}, - {"Encoder.CompressionLevel", Field, 4}, - {"EncoderBuffer", Type, 9}, - {"EncoderBufferPool", Type, 9}, - {"FormatError", Type, 0}, - {"NoCompression", Const, 4}, - {"UnsupportedError", Type, 0}, + {"(*Encoder).Encode", Method, 4, ""}, + {"(FormatError).Error", Method, 0, ""}, + {"(UnsupportedError).Error", Method, 0, ""}, + {"BestCompression", Const, 4, ""}, + {"BestSpeed", Const, 4, ""}, + {"CompressionLevel", Type, 4, ""}, + {"Decode", Func, 0, "func(r io.Reader) (image.Image, error)"}, + {"DecodeConfig", Func, 0, "func(r io.Reader) (image.Config, error)"}, + {"DefaultCompression", Const, 4, ""}, + {"Encode", Func, 0, "func(w io.Writer, m image.Image) error"}, + {"Encoder", Type, 4, ""}, + {"Encoder.BufferPool", Field, 9, ""}, + {"Encoder.CompressionLevel", Field, 4, ""}, + {"EncoderBuffer", Type, 9, ""}, + {"EncoderBufferPool", Type, 9, ""}, + {"FormatError", Type, 0, ""}, + {"NoCompression", Const, 4, ""}, + {"UnsupportedError", Type, 0, ""}, }, "index/suffixarray": { - {"(*Index).Bytes", Method, 0}, - {"(*Index).FindAllIndex", Method, 0}, - {"(*Index).Lookup", Method, 0}, - {"(*Index).Read", Method, 0}, - {"(*Index).Write", Method, 0}, - {"Index", Type, 0}, - {"New", Func, 0}, + {"(*Index).Bytes", Method, 0, ""}, + {"(*Index).FindAllIndex", Method, 0, ""}, + {"(*Index).Lookup", Method, 0, ""}, + {"(*Index).Read", Method, 0, ""}, + {"(*Index).Write", Method, 0, ""}, + {"Index", Type, 0, ""}, + {"New", Func, 0, "func(data []byte) *Index"}, }, "io": { - {"(*LimitedReader).Read", Method, 0}, - {"(*OffsetWriter).Seek", Method, 20}, - {"(*OffsetWriter).Write", Method, 20}, - {"(*OffsetWriter).WriteAt", Method, 20}, - {"(*PipeReader).Close", Method, 0}, - {"(*PipeReader).CloseWithError", Method, 0}, - {"(*PipeReader).Read", Method, 0}, - {"(*PipeWriter).Close", Method, 0}, - {"(*PipeWriter).CloseWithError", Method, 0}, - {"(*PipeWriter).Write", Method, 0}, - {"(*SectionReader).Outer", Method, 22}, - {"(*SectionReader).Read", Method, 0}, - {"(*SectionReader).ReadAt", Method, 0}, - {"(*SectionReader).Seek", Method, 0}, - {"(*SectionReader).Size", Method, 0}, - {"ByteReader", Type, 0}, - {"ByteScanner", Type, 0}, - {"ByteWriter", Type, 1}, - {"Closer", Type, 0}, - {"Copy", Func, 0}, - {"CopyBuffer", Func, 5}, - {"CopyN", Func, 0}, - {"Discard", Var, 16}, - {"EOF", Var, 0}, - {"ErrClosedPipe", Var, 0}, - {"ErrNoProgress", Var, 1}, - {"ErrShortBuffer", Var, 0}, - {"ErrShortWrite", Var, 0}, - {"ErrUnexpectedEOF", Var, 0}, - {"LimitReader", Func, 0}, - {"LimitedReader", Type, 0}, - {"LimitedReader.N", Field, 0}, - {"LimitedReader.R", Field, 0}, - {"MultiReader", Func, 0}, - {"MultiWriter", Func, 0}, - {"NewOffsetWriter", Func, 20}, - {"NewSectionReader", Func, 0}, - {"NopCloser", Func, 16}, - {"OffsetWriter", Type, 20}, - {"Pipe", Func, 0}, - {"PipeReader", Type, 0}, - {"PipeWriter", Type, 0}, - {"ReadAll", Func, 16}, - {"ReadAtLeast", Func, 0}, - {"ReadCloser", Type, 0}, - {"ReadFull", Func, 0}, - {"ReadSeekCloser", Type, 16}, - {"ReadSeeker", Type, 0}, - {"ReadWriteCloser", Type, 0}, - {"ReadWriteSeeker", Type, 0}, - {"ReadWriter", Type, 0}, - {"Reader", Type, 0}, - {"ReaderAt", Type, 0}, - {"ReaderFrom", Type, 0}, - {"RuneReader", Type, 0}, - {"RuneScanner", Type, 0}, - {"SectionReader", Type, 0}, - {"SeekCurrent", Const, 7}, - {"SeekEnd", Const, 7}, - {"SeekStart", Const, 7}, - {"Seeker", Type, 0}, - {"StringWriter", Type, 12}, - {"TeeReader", Func, 0}, - {"WriteCloser", Type, 0}, - {"WriteSeeker", Type, 0}, - {"WriteString", Func, 0}, - {"Writer", Type, 0}, - {"WriterAt", Type, 0}, - {"WriterTo", Type, 0}, + {"(*LimitedReader).Read", Method, 0, ""}, + {"(*OffsetWriter).Seek", Method, 20, ""}, + {"(*OffsetWriter).Write", Method, 20, ""}, + {"(*OffsetWriter).WriteAt", Method, 20, ""}, + {"(*PipeReader).Close", Method, 0, ""}, + {"(*PipeReader).CloseWithError", Method, 0, ""}, + {"(*PipeReader).Read", Method, 0, ""}, + {"(*PipeWriter).Close", Method, 0, ""}, + {"(*PipeWriter).CloseWithError", Method, 0, ""}, + {"(*PipeWriter).Write", Method, 0, ""}, + {"(*SectionReader).Outer", Method, 22, ""}, + {"(*SectionReader).Read", Method, 0, ""}, + {"(*SectionReader).ReadAt", Method, 0, ""}, + {"(*SectionReader).Seek", Method, 0, ""}, + {"(*SectionReader).Size", Method, 0, ""}, + {"ByteReader", Type, 0, ""}, + {"ByteScanner", Type, 0, ""}, + {"ByteWriter", Type, 1, ""}, + {"Closer", Type, 0, ""}, + {"Copy", Func, 0, "func(dst Writer, src Reader) (written int64, err error)"}, + {"CopyBuffer", Func, 5, "func(dst Writer, src Reader, buf []byte) (written int64, err error)"}, + {"CopyN", Func, 0, "func(dst Writer, src Reader, n int64) (written int64, err error)"}, + {"Discard", Var, 16, ""}, + {"EOF", Var, 0, ""}, + {"ErrClosedPipe", Var, 0, ""}, + {"ErrNoProgress", Var, 1, ""}, + {"ErrShortBuffer", Var, 0, ""}, + {"ErrShortWrite", Var, 0, ""}, + {"ErrUnexpectedEOF", Var, 0, ""}, + {"LimitReader", Func, 0, "func(r Reader, n int64) Reader"}, + {"LimitedReader", Type, 0, ""}, + {"LimitedReader.N", Field, 0, ""}, + {"LimitedReader.R", Field, 0, ""}, + {"MultiReader", Func, 0, "func(readers ...Reader) Reader"}, + {"MultiWriter", Func, 0, "func(writers ...Writer) Writer"}, + {"NewOffsetWriter", Func, 20, "func(w WriterAt, off int64) *OffsetWriter"}, + {"NewSectionReader", Func, 0, "func(r ReaderAt, off int64, n int64) *SectionReader"}, + {"NopCloser", Func, 16, "func(r Reader) ReadCloser"}, + {"OffsetWriter", Type, 20, ""}, + {"Pipe", Func, 0, "func() (*PipeReader, *PipeWriter)"}, + {"PipeReader", Type, 0, ""}, + {"PipeWriter", Type, 0, ""}, + {"ReadAll", Func, 16, "func(r Reader) ([]byte, error)"}, + {"ReadAtLeast", Func, 0, "func(r Reader, buf []byte, min int) (n int, err error)"}, + {"ReadCloser", Type, 0, ""}, + {"ReadFull", Func, 0, "func(r Reader, buf []byte) (n int, err error)"}, + {"ReadSeekCloser", Type, 16, ""}, + {"ReadSeeker", Type, 0, ""}, + {"ReadWriteCloser", Type, 0, ""}, + {"ReadWriteSeeker", Type, 0, ""}, + {"ReadWriter", Type, 0, ""}, + {"Reader", Type, 0, ""}, + {"ReaderAt", Type, 0, ""}, + {"ReaderFrom", Type, 0, ""}, + {"RuneReader", Type, 0, ""}, + {"RuneScanner", Type, 0, ""}, + {"SectionReader", Type, 0, ""}, + {"SeekCurrent", Const, 7, ""}, + {"SeekEnd", Const, 7, ""}, + {"SeekStart", Const, 7, ""}, + {"Seeker", Type, 0, ""}, + {"StringWriter", Type, 12, ""}, + {"TeeReader", Func, 0, "func(r Reader, w Writer) Reader"}, + {"WriteCloser", Type, 0, ""}, + {"WriteSeeker", Type, 0, ""}, + {"WriteString", Func, 0, "func(w Writer, s string) (n int, err error)"}, + {"Writer", Type, 0, ""}, + {"WriterAt", Type, 0, ""}, + {"WriterTo", Type, 0, ""}, }, "io/fs": { - {"(*PathError).Error", Method, 16}, - {"(*PathError).Timeout", Method, 16}, - {"(*PathError).Unwrap", Method, 16}, - {"(FileMode).IsDir", Method, 16}, - {"(FileMode).IsRegular", Method, 16}, - {"(FileMode).Perm", Method, 16}, - {"(FileMode).String", Method, 16}, - {"(FileMode).Type", Method, 16}, - {"DirEntry", Type, 16}, - {"ErrClosed", Var, 16}, - {"ErrExist", Var, 16}, - {"ErrInvalid", Var, 16}, - {"ErrNotExist", Var, 16}, - {"ErrPermission", Var, 16}, - {"FS", Type, 16}, - {"File", Type, 16}, - {"FileInfo", Type, 16}, - {"FileInfoToDirEntry", Func, 17}, - {"FileMode", Type, 16}, - {"FormatDirEntry", Func, 21}, - {"FormatFileInfo", Func, 21}, - {"Glob", Func, 16}, - {"GlobFS", Type, 16}, - {"Lstat", Func, 25}, - {"ModeAppend", Const, 16}, - {"ModeCharDevice", Const, 16}, - {"ModeDevice", Const, 16}, - {"ModeDir", Const, 16}, - {"ModeExclusive", Const, 16}, - {"ModeIrregular", Const, 16}, - {"ModeNamedPipe", Const, 16}, - {"ModePerm", Const, 16}, - {"ModeSetgid", Const, 16}, - {"ModeSetuid", Const, 16}, - {"ModeSocket", Const, 16}, - {"ModeSticky", Const, 16}, - {"ModeSymlink", Const, 16}, - {"ModeTemporary", Const, 16}, - {"ModeType", Const, 16}, - {"PathError", Type, 16}, - {"PathError.Err", Field, 16}, - {"PathError.Op", Field, 16}, - {"PathError.Path", Field, 16}, - {"ReadDir", Func, 16}, - {"ReadDirFS", Type, 16}, - {"ReadDirFile", Type, 16}, - {"ReadFile", Func, 16}, - {"ReadFileFS", Type, 16}, - {"ReadLink", Func, 25}, - {"ReadLinkFS", Type, 25}, - {"SkipAll", Var, 20}, - {"SkipDir", Var, 16}, - {"Stat", Func, 16}, - {"StatFS", Type, 16}, - {"Sub", Func, 16}, - {"SubFS", Type, 16}, - {"ValidPath", Func, 16}, - {"WalkDir", Func, 16}, - {"WalkDirFunc", Type, 16}, + {"(*PathError).Error", Method, 16, ""}, + {"(*PathError).Timeout", Method, 16, ""}, + {"(*PathError).Unwrap", Method, 16, ""}, + {"(FileMode).IsDir", Method, 16, ""}, + {"(FileMode).IsRegular", Method, 16, ""}, + {"(FileMode).Perm", Method, 16, ""}, + {"(FileMode).String", Method, 16, ""}, + {"(FileMode).Type", Method, 16, ""}, + {"DirEntry", Type, 16, ""}, + {"ErrClosed", Var, 16, ""}, + {"ErrExist", Var, 16, ""}, + {"ErrInvalid", Var, 16, ""}, + {"ErrNotExist", Var, 16, ""}, + {"ErrPermission", Var, 16, ""}, + {"FS", Type, 16, ""}, + {"File", Type, 16, ""}, + {"FileInfo", Type, 16, ""}, + {"FileInfoToDirEntry", Func, 17, "func(info FileInfo) DirEntry"}, + {"FileMode", Type, 16, ""}, + {"FormatDirEntry", Func, 21, "func(dir DirEntry) string"}, + {"FormatFileInfo", Func, 21, "func(info FileInfo) string"}, + {"Glob", Func, 16, "func(fsys FS, pattern string) (matches []string, err error)"}, + {"GlobFS", Type, 16, ""}, + {"Lstat", Func, 25, ""}, + {"ModeAppend", Const, 16, ""}, + {"ModeCharDevice", Const, 16, ""}, + {"ModeDevice", Const, 16, ""}, + {"ModeDir", Const, 16, ""}, + {"ModeExclusive", Const, 16, ""}, + {"ModeIrregular", Const, 16, ""}, + {"ModeNamedPipe", Const, 16, ""}, + {"ModePerm", Const, 16, ""}, + {"ModeSetgid", Const, 16, ""}, + {"ModeSetuid", Const, 16, ""}, + {"ModeSocket", Const, 16, ""}, + {"ModeSticky", Const, 16, ""}, + {"ModeSymlink", Const, 16, ""}, + {"ModeTemporary", Const, 16, ""}, + {"ModeType", Const, 16, ""}, + {"PathError", Type, 16, ""}, + {"PathError.Err", Field, 16, ""}, + {"PathError.Op", Field, 16, ""}, + {"PathError.Path", Field, 16, ""}, + {"ReadDir", Func, 16, "func(fsys FS, name string) ([]DirEntry, error)"}, + {"ReadDirFS", Type, 16, ""}, + {"ReadDirFile", Type, 16, ""}, + {"ReadFile", Func, 16, "func(fsys FS, name string) ([]byte, error)"}, + {"ReadFileFS", Type, 16, ""}, + {"ReadLink", Func, 25, ""}, + {"ReadLinkFS", Type, 25, ""}, + {"SkipAll", Var, 20, ""}, + {"SkipDir", Var, 16, ""}, + {"Stat", Func, 16, "func(fsys FS, name string) (FileInfo, error)"}, + {"StatFS", Type, 16, ""}, + {"Sub", Func, 16, "func(fsys FS, dir string) (FS, error)"}, + {"SubFS", Type, 16, ""}, + {"ValidPath", Func, 16, "func(name string) bool"}, + {"WalkDir", Func, 16, "func(fsys FS, root string, fn WalkDirFunc) error"}, + {"WalkDirFunc", Type, 16, ""}, }, "io/ioutil": { - {"Discard", Var, 0}, - {"NopCloser", Func, 0}, - {"ReadAll", Func, 0}, - {"ReadDir", Func, 0}, - {"ReadFile", Func, 0}, - {"TempDir", Func, 0}, - {"TempFile", Func, 0}, - {"WriteFile", Func, 0}, + {"Discard", Var, 0, ""}, + {"NopCloser", Func, 0, "func(r io.Reader) io.ReadCloser"}, + {"ReadAll", Func, 0, "func(r io.Reader) ([]byte, error)"}, + {"ReadDir", Func, 0, "func(dirname string) ([]fs.FileInfo, error)"}, + {"ReadFile", Func, 0, "func(filename string) ([]byte, error)"}, + {"TempDir", Func, 0, "func(dir string, pattern string) (name string, err error)"}, + {"TempFile", Func, 0, "func(dir string, pattern string) (f *os.File, err error)"}, + {"WriteFile", Func, 0, "func(filename string, data []byte, perm fs.FileMode) error"}, }, "iter": { - {"Pull", Func, 23}, - {"Pull2", Func, 23}, - {"Seq", Type, 23}, - {"Seq2", Type, 23}, + {"Pull", Func, 23, "func[V any](seq Seq[V]) (next func() (V, bool), stop func())"}, + {"Pull2", Func, 23, "func[K, V any](seq Seq2[K, V]) (next func() (K, V, bool), stop func())"}, + {"Seq", Type, 23, ""}, + {"Seq2", Type, 23, ""}, }, "log": { - {"(*Logger).Fatal", Method, 0}, - {"(*Logger).Fatalf", Method, 0}, - {"(*Logger).Fatalln", Method, 0}, - {"(*Logger).Flags", Method, 0}, - {"(*Logger).Output", Method, 0}, - {"(*Logger).Panic", Method, 0}, - {"(*Logger).Panicf", Method, 0}, - {"(*Logger).Panicln", Method, 0}, - {"(*Logger).Prefix", Method, 0}, - {"(*Logger).Print", Method, 0}, - {"(*Logger).Printf", Method, 0}, - {"(*Logger).Println", Method, 0}, - {"(*Logger).SetFlags", Method, 0}, - {"(*Logger).SetOutput", Method, 5}, - {"(*Logger).SetPrefix", Method, 0}, - {"(*Logger).Writer", Method, 12}, - {"Default", Func, 16}, - {"Fatal", Func, 0}, - {"Fatalf", Func, 0}, - {"Fatalln", Func, 0}, - {"Flags", Func, 0}, - {"LUTC", Const, 5}, - {"Ldate", Const, 0}, - {"Llongfile", Const, 0}, - {"Lmicroseconds", Const, 0}, - {"Lmsgprefix", Const, 14}, - {"Logger", Type, 0}, - {"Lshortfile", Const, 0}, - {"LstdFlags", Const, 0}, - {"Ltime", Const, 0}, - {"New", Func, 0}, - {"Output", Func, 5}, - {"Panic", Func, 0}, - {"Panicf", Func, 0}, - {"Panicln", Func, 0}, - {"Prefix", Func, 0}, - {"Print", Func, 0}, - {"Printf", Func, 0}, - {"Println", Func, 0}, - {"SetFlags", Func, 0}, - {"SetOutput", Func, 0}, - {"SetPrefix", Func, 0}, - {"Writer", Func, 13}, + {"(*Logger).Fatal", Method, 0, ""}, + {"(*Logger).Fatalf", Method, 0, ""}, + {"(*Logger).Fatalln", Method, 0, ""}, + {"(*Logger).Flags", Method, 0, ""}, + {"(*Logger).Output", Method, 0, ""}, + {"(*Logger).Panic", Method, 0, ""}, + {"(*Logger).Panicf", Method, 0, ""}, + {"(*Logger).Panicln", Method, 0, ""}, + {"(*Logger).Prefix", Method, 0, ""}, + {"(*Logger).Print", Method, 0, ""}, + {"(*Logger).Printf", Method, 0, ""}, + {"(*Logger).Println", Method, 0, ""}, + {"(*Logger).SetFlags", Method, 0, ""}, + {"(*Logger).SetOutput", Method, 5, ""}, + {"(*Logger).SetPrefix", Method, 0, ""}, + {"(*Logger).Writer", Method, 12, ""}, + {"Default", Func, 16, "func() *Logger"}, + {"Fatal", Func, 0, "func(v ...any)"}, + {"Fatalf", Func, 0, "func(format string, v ...any)"}, + {"Fatalln", Func, 0, "func(v ...any)"}, + {"Flags", Func, 0, "func() int"}, + {"LUTC", Const, 5, ""}, + {"Ldate", Const, 0, ""}, + {"Llongfile", Const, 0, ""}, + {"Lmicroseconds", Const, 0, ""}, + {"Lmsgprefix", Const, 14, ""}, + {"Logger", Type, 0, ""}, + {"Lshortfile", Const, 0, ""}, + {"LstdFlags", Const, 0, ""}, + {"Ltime", Const, 0, ""}, + {"New", Func, 0, "func(out io.Writer, prefix string, flag int) *Logger"}, + {"Output", Func, 5, "func(calldepth int, s string) error"}, + {"Panic", Func, 0, "func(v ...any)"}, + {"Panicf", Func, 0, "func(format string, v ...any)"}, + {"Panicln", Func, 0, "func(v ...any)"}, + {"Prefix", Func, 0, "func() string"}, + {"Print", Func, 0, "func(v ...any)"}, + {"Printf", Func, 0, "func(format string, v ...any)"}, + {"Println", Func, 0, "func(v ...any)"}, + {"SetFlags", Func, 0, "func(flag int)"}, + {"SetOutput", Func, 0, "func(w io.Writer)"}, + {"SetPrefix", Func, 0, "func(prefix string)"}, + {"Writer", Func, 13, "func() io.Writer"}, }, "log/slog": { - {"(*JSONHandler).Enabled", Method, 21}, - {"(*JSONHandler).Handle", Method, 21}, - {"(*JSONHandler).WithAttrs", Method, 21}, - {"(*JSONHandler).WithGroup", Method, 21}, - {"(*Level).UnmarshalJSON", Method, 21}, - {"(*Level).UnmarshalText", Method, 21}, - {"(*LevelVar).AppendText", Method, 24}, - {"(*LevelVar).Level", Method, 21}, - {"(*LevelVar).MarshalText", Method, 21}, - {"(*LevelVar).Set", Method, 21}, - {"(*LevelVar).String", Method, 21}, - {"(*LevelVar).UnmarshalText", Method, 21}, - {"(*Logger).Debug", Method, 21}, - {"(*Logger).DebugContext", Method, 21}, - {"(*Logger).Enabled", Method, 21}, - {"(*Logger).Error", Method, 21}, - {"(*Logger).ErrorContext", Method, 21}, - {"(*Logger).Handler", Method, 21}, - {"(*Logger).Info", Method, 21}, - {"(*Logger).InfoContext", Method, 21}, - {"(*Logger).Log", Method, 21}, - {"(*Logger).LogAttrs", Method, 21}, - {"(*Logger).Warn", Method, 21}, - {"(*Logger).WarnContext", Method, 21}, - {"(*Logger).With", Method, 21}, - {"(*Logger).WithGroup", Method, 21}, - {"(*Record).Add", Method, 21}, - {"(*Record).AddAttrs", Method, 21}, - {"(*TextHandler).Enabled", Method, 21}, - {"(*TextHandler).Handle", Method, 21}, - {"(*TextHandler).WithAttrs", Method, 21}, - {"(*TextHandler).WithGroup", Method, 21}, - {"(Attr).Equal", Method, 21}, - {"(Attr).String", Method, 21}, - {"(Kind).String", Method, 21}, - {"(Level).AppendText", Method, 24}, - {"(Level).Level", Method, 21}, - {"(Level).MarshalJSON", Method, 21}, - {"(Level).MarshalText", Method, 21}, - {"(Level).String", Method, 21}, - {"(Record).Attrs", Method, 21}, - {"(Record).Clone", Method, 21}, - {"(Record).NumAttrs", Method, 21}, - {"(Value).Any", Method, 21}, - {"(Value).Bool", Method, 21}, - {"(Value).Duration", Method, 21}, - {"(Value).Equal", Method, 21}, - {"(Value).Float64", Method, 21}, - {"(Value).Group", Method, 21}, - {"(Value).Int64", Method, 21}, - {"(Value).Kind", Method, 21}, - {"(Value).LogValuer", Method, 21}, - {"(Value).Resolve", Method, 21}, - {"(Value).String", Method, 21}, - {"(Value).Time", Method, 21}, - {"(Value).Uint64", Method, 21}, - {"Any", Func, 21}, - {"AnyValue", Func, 21}, - {"Attr", Type, 21}, - {"Attr.Key", Field, 21}, - {"Attr.Value", Field, 21}, - {"Bool", Func, 21}, - {"BoolValue", Func, 21}, - {"Debug", Func, 21}, - {"DebugContext", Func, 21}, - {"Default", Func, 21}, - {"DiscardHandler", Var, 24}, - {"Duration", Func, 21}, - {"DurationValue", Func, 21}, - {"Error", Func, 21}, - {"ErrorContext", Func, 21}, - {"Float64", Func, 21}, - {"Float64Value", Func, 21}, - {"Group", Func, 21}, - {"GroupValue", Func, 21}, - {"Handler", Type, 21}, - {"HandlerOptions", Type, 21}, - {"HandlerOptions.AddSource", Field, 21}, - {"HandlerOptions.Level", Field, 21}, - {"HandlerOptions.ReplaceAttr", Field, 21}, - {"Info", Func, 21}, - {"InfoContext", Func, 21}, - {"Int", Func, 21}, - {"Int64", Func, 21}, - {"Int64Value", Func, 21}, - {"IntValue", Func, 21}, - {"JSONHandler", Type, 21}, - {"Kind", Type, 21}, - {"KindAny", Const, 21}, - {"KindBool", Const, 21}, - {"KindDuration", Const, 21}, - {"KindFloat64", Const, 21}, - {"KindGroup", Const, 21}, - {"KindInt64", Const, 21}, - {"KindLogValuer", Const, 21}, - {"KindString", Const, 21}, - {"KindTime", Const, 21}, - {"KindUint64", Const, 21}, - {"Level", Type, 21}, - {"LevelDebug", Const, 21}, - {"LevelError", Const, 21}, - {"LevelInfo", Const, 21}, - {"LevelKey", Const, 21}, - {"LevelVar", Type, 21}, - {"LevelWarn", Const, 21}, - {"Leveler", Type, 21}, - {"Log", Func, 21}, - {"LogAttrs", Func, 21}, - {"LogValuer", Type, 21}, - {"Logger", Type, 21}, - {"MessageKey", Const, 21}, - {"New", Func, 21}, - {"NewJSONHandler", Func, 21}, - {"NewLogLogger", Func, 21}, - {"NewRecord", Func, 21}, - {"NewTextHandler", Func, 21}, - {"Record", Type, 21}, - {"Record.Level", Field, 21}, - {"Record.Message", Field, 21}, - {"Record.PC", Field, 21}, - {"Record.Time", Field, 21}, - {"SetDefault", Func, 21}, - {"SetLogLoggerLevel", Func, 22}, - {"Source", Type, 21}, - {"Source.File", Field, 21}, - {"Source.Function", Field, 21}, - {"Source.Line", Field, 21}, - {"SourceKey", Const, 21}, - {"String", Func, 21}, - {"StringValue", Func, 21}, - {"TextHandler", Type, 21}, - {"Time", Func, 21}, - {"TimeKey", Const, 21}, - {"TimeValue", Func, 21}, - {"Uint64", Func, 21}, - {"Uint64Value", Func, 21}, - {"Value", Type, 21}, - {"Warn", Func, 21}, - {"WarnContext", Func, 21}, - {"With", Func, 21}, + {"(*JSONHandler).Enabled", Method, 21, ""}, + {"(*JSONHandler).Handle", Method, 21, ""}, + {"(*JSONHandler).WithAttrs", Method, 21, ""}, + {"(*JSONHandler).WithGroup", Method, 21, ""}, + {"(*Level).UnmarshalJSON", Method, 21, ""}, + {"(*Level).UnmarshalText", Method, 21, ""}, + {"(*LevelVar).AppendText", Method, 24, ""}, + {"(*LevelVar).Level", Method, 21, ""}, + {"(*LevelVar).MarshalText", Method, 21, ""}, + {"(*LevelVar).Set", Method, 21, ""}, + {"(*LevelVar).String", Method, 21, ""}, + {"(*LevelVar).UnmarshalText", Method, 21, ""}, + {"(*Logger).Debug", Method, 21, ""}, + {"(*Logger).DebugContext", Method, 21, ""}, + {"(*Logger).Enabled", Method, 21, ""}, + {"(*Logger).Error", Method, 21, ""}, + {"(*Logger).ErrorContext", Method, 21, ""}, + {"(*Logger).Handler", Method, 21, ""}, + {"(*Logger).Info", Method, 21, ""}, + {"(*Logger).InfoContext", Method, 21, ""}, + {"(*Logger).Log", Method, 21, ""}, + {"(*Logger).LogAttrs", Method, 21, ""}, + {"(*Logger).Warn", Method, 21, ""}, + {"(*Logger).WarnContext", Method, 21, ""}, + {"(*Logger).With", Method, 21, ""}, + {"(*Logger).WithGroup", Method, 21, ""}, + {"(*Record).Add", Method, 21, ""}, + {"(*Record).AddAttrs", Method, 21, ""}, + {"(*TextHandler).Enabled", Method, 21, ""}, + {"(*TextHandler).Handle", Method, 21, ""}, + {"(*TextHandler).WithAttrs", Method, 21, ""}, + {"(*TextHandler).WithGroup", Method, 21, ""}, + {"(Attr).Equal", Method, 21, ""}, + {"(Attr).String", Method, 21, ""}, + {"(Kind).String", Method, 21, ""}, + {"(Level).AppendText", Method, 24, ""}, + {"(Level).Level", Method, 21, ""}, + {"(Level).MarshalJSON", Method, 21, ""}, + {"(Level).MarshalText", Method, 21, ""}, + {"(Level).String", Method, 21, ""}, + {"(Record).Attrs", Method, 21, ""}, + {"(Record).Clone", Method, 21, ""}, + {"(Record).NumAttrs", Method, 21, ""}, + {"(Value).Any", Method, 21, ""}, + {"(Value).Bool", Method, 21, ""}, + {"(Value).Duration", Method, 21, ""}, + {"(Value).Equal", Method, 21, ""}, + {"(Value).Float64", Method, 21, ""}, + {"(Value).Group", Method, 21, ""}, + {"(Value).Int64", Method, 21, ""}, + {"(Value).Kind", Method, 21, ""}, + {"(Value).LogValuer", Method, 21, ""}, + {"(Value).Resolve", Method, 21, ""}, + {"(Value).String", Method, 21, ""}, + {"(Value).Time", Method, 21, ""}, + {"(Value).Uint64", Method, 21, ""}, + {"Any", Func, 21, "func(key string, value any) Attr"}, + {"AnyValue", Func, 21, "func(v any) Value"}, + {"Attr", Type, 21, ""}, + {"Attr.Key", Field, 21, ""}, + {"Attr.Value", Field, 21, ""}, + {"Bool", Func, 21, "func(key string, v bool) Attr"}, + {"BoolValue", Func, 21, "func(v bool) Value"}, + {"Debug", Func, 21, "func(msg string, args ...any)"}, + {"DebugContext", Func, 21, "func(ctx context.Context, msg string, args ...any)"}, + {"Default", Func, 21, "func() *Logger"}, + {"DiscardHandler", Var, 24, ""}, + {"Duration", Func, 21, "func(key string, v time.Duration) Attr"}, + {"DurationValue", Func, 21, "func(v time.Duration) Value"}, + {"Error", Func, 21, "func(msg string, args ...any)"}, + {"ErrorContext", Func, 21, "func(ctx context.Context, msg string, args ...any)"}, + {"Float64", Func, 21, "func(key string, v float64) Attr"}, + {"Float64Value", Func, 21, "func(v float64) Value"}, + {"Group", Func, 21, "func(key string, args ...any) Attr"}, + {"GroupValue", Func, 21, "func(as ...Attr) Value"}, + {"Handler", Type, 21, ""}, + {"HandlerOptions", Type, 21, ""}, + {"HandlerOptions.AddSource", Field, 21, ""}, + {"HandlerOptions.Level", Field, 21, ""}, + {"HandlerOptions.ReplaceAttr", Field, 21, ""}, + {"Info", Func, 21, "func(msg string, args ...any)"}, + {"InfoContext", Func, 21, "func(ctx context.Context, msg string, args ...any)"}, + {"Int", Func, 21, "func(key string, value int) Attr"}, + {"Int64", Func, 21, "func(key string, value int64) Attr"}, + {"Int64Value", Func, 21, "func(v int64) Value"}, + {"IntValue", Func, 21, "func(v int) Value"}, + {"JSONHandler", Type, 21, ""}, + {"Kind", Type, 21, ""}, + {"KindAny", Const, 21, ""}, + {"KindBool", Const, 21, ""}, + {"KindDuration", Const, 21, ""}, + {"KindFloat64", Const, 21, ""}, + {"KindGroup", Const, 21, ""}, + {"KindInt64", Const, 21, ""}, + {"KindLogValuer", Const, 21, ""}, + {"KindString", Const, 21, ""}, + {"KindTime", Const, 21, ""}, + {"KindUint64", Const, 21, ""}, + {"Level", Type, 21, ""}, + {"LevelDebug", Const, 21, ""}, + {"LevelError", Const, 21, ""}, + {"LevelInfo", Const, 21, ""}, + {"LevelKey", Const, 21, ""}, + {"LevelVar", Type, 21, ""}, + {"LevelWarn", Const, 21, ""}, + {"Leveler", Type, 21, ""}, + {"Log", Func, 21, "func(ctx context.Context, level Level, msg string, args ...any)"}, + {"LogAttrs", Func, 21, "func(ctx context.Context, level Level, msg string, attrs ...Attr)"}, + {"LogValuer", Type, 21, ""}, + {"Logger", Type, 21, ""}, + {"MessageKey", Const, 21, ""}, + {"New", Func, 21, "func(h Handler) *Logger"}, + {"NewJSONHandler", Func, 21, "func(w io.Writer, opts *HandlerOptions) *JSONHandler"}, + {"NewLogLogger", Func, 21, "func(h Handler, level Level) *log.Logger"}, + {"NewRecord", Func, 21, "func(t time.Time, level Level, msg string, pc uintptr) Record"}, + {"NewTextHandler", Func, 21, "func(w io.Writer, opts *HandlerOptions) *TextHandler"}, + {"Record", Type, 21, ""}, + {"Record.Level", Field, 21, ""}, + {"Record.Message", Field, 21, ""}, + {"Record.PC", Field, 21, ""}, + {"Record.Time", Field, 21, ""}, + {"SetDefault", Func, 21, "func(l *Logger)"}, + {"SetLogLoggerLevel", Func, 22, "func(level Level) (oldLevel Level)"}, + {"Source", Type, 21, ""}, + {"Source.File", Field, 21, ""}, + {"Source.Function", Field, 21, ""}, + {"Source.Line", Field, 21, ""}, + {"SourceKey", Const, 21, ""}, + {"String", Func, 21, "func(key string, value string) Attr"}, + {"StringValue", Func, 21, "func(value string) Value"}, + {"TextHandler", Type, 21, ""}, + {"Time", Func, 21, "func(key string, v time.Time) Attr"}, + {"TimeKey", Const, 21, ""}, + {"TimeValue", Func, 21, "func(v time.Time) Value"}, + {"Uint64", Func, 21, "func(key string, v uint64) Attr"}, + {"Uint64Value", Func, 21, "func(v uint64) Value"}, + {"Value", Type, 21, ""}, + {"Warn", Func, 21, "func(msg string, args ...any)"}, + {"WarnContext", Func, 21, "func(ctx context.Context, msg string, args ...any)"}, + {"With", Func, 21, "func(args ...any) *Logger"}, }, "log/syslog": { - {"(*Writer).Alert", Method, 0}, - {"(*Writer).Close", Method, 0}, - {"(*Writer).Crit", Method, 0}, - {"(*Writer).Debug", Method, 0}, - {"(*Writer).Emerg", Method, 0}, - {"(*Writer).Err", Method, 0}, - {"(*Writer).Info", Method, 0}, - {"(*Writer).Notice", Method, 0}, - {"(*Writer).Warning", Method, 0}, - {"(*Writer).Write", Method, 0}, - {"Dial", Func, 0}, - {"LOG_ALERT", Const, 0}, - {"LOG_AUTH", Const, 1}, - {"LOG_AUTHPRIV", Const, 1}, - {"LOG_CRIT", Const, 0}, - {"LOG_CRON", Const, 1}, - {"LOG_DAEMON", Const, 1}, - {"LOG_DEBUG", Const, 0}, - {"LOG_EMERG", Const, 0}, - {"LOG_ERR", Const, 0}, - {"LOG_FTP", Const, 1}, - {"LOG_INFO", Const, 0}, - {"LOG_KERN", Const, 1}, - {"LOG_LOCAL0", Const, 1}, - {"LOG_LOCAL1", Const, 1}, - {"LOG_LOCAL2", Const, 1}, - {"LOG_LOCAL3", Const, 1}, - {"LOG_LOCAL4", Const, 1}, - {"LOG_LOCAL5", Const, 1}, - {"LOG_LOCAL6", Const, 1}, - {"LOG_LOCAL7", Const, 1}, - {"LOG_LPR", Const, 1}, - {"LOG_MAIL", Const, 1}, - {"LOG_NEWS", Const, 1}, - {"LOG_NOTICE", Const, 0}, - {"LOG_SYSLOG", Const, 1}, - {"LOG_USER", Const, 1}, - {"LOG_UUCP", Const, 1}, - {"LOG_WARNING", Const, 0}, - {"New", Func, 0}, - {"NewLogger", Func, 0}, - {"Priority", Type, 0}, - {"Writer", Type, 0}, + {"(*Writer).Alert", Method, 0, ""}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).Crit", Method, 0, ""}, + {"(*Writer).Debug", Method, 0, ""}, + {"(*Writer).Emerg", Method, 0, ""}, + {"(*Writer).Err", Method, 0, ""}, + {"(*Writer).Info", Method, 0, ""}, + {"(*Writer).Notice", Method, 0, ""}, + {"(*Writer).Warning", Method, 0, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"Dial", Func, 0, "func(network string, raddr string, priority Priority, tag string) (*Writer, error)"}, + {"LOG_ALERT", Const, 0, ""}, + {"LOG_AUTH", Const, 1, ""}, + {"LOG_AUTHPRIV", Const, 1, ""}, + {"LOG_CRIT", Const, 0, ""}, + {"LOG_CRON", Const, 1, ""}, + {"LOG_DAEMON", Const, 1, ""}, + {"LOG_DEBUG", Const, 0, ""}, + {"LOG_EMERG", Const, 0, ""}, + {"LOG_ERR", Const, 0, ""}, + {"LOG_FTP", Const, 1, ""}, + {"LOG_INFO", Const, 0, ""}, + {"LOG_KERN", Const, 1, ""}, + {"LOG_LOCAL0", Const, 1, ""}, + {"LOG_LOCAL1", Const, 1, ""}, + {"LOG_LOCAL2", Const, 1, ""}, + {"LOG_LOCAL3", Const, 1, ""}, + {"LOG_LOCAL4", Const, 1, ""}, + {"LOG_LOCAL5", Const, 1, ""}, + {"LOG_LOCAL6", Const, 1, ""}, + {"LOG_LOCAL7", Const, 1, ""}, + {"LOG_LPR", Const, 1, ""}, + {"LOG_MAIL", Const, 1, ""}, + {"LOG_NEWS", Const, 1, ""}, + {"LOG_NOTICE", Const, 0, ""}, + {"LOG_SYSLOG", Const, 1, ""}, + {"LOG_USER", Const, 1, ""}, + {"LOG_UUCP", Const, 1, ""}, + {"LOG_WARNING", Const, 0, ""}, + {"New", Func, 0, "func(priority Priority, tag string) (*Writer, error)"}, + {"NewLogger", Func, 0, "func(p Priority, logFlag int) (*log.Logger, error)"}, + {"Priority", Type, 0, ""}, + {"Writer", Type, 0, ""}, }, "maps": { - {"All", Func, 23}, - {"Clone", Func, 21}, - {"Collect", Func, 23}, - {"Copy", Func, 21}, - {"DeleteFunc", Func, 21}, - {"Equal", Func, 21}, - {"EqualFunc", Func, 21}, - {"Insert", Func, 23}, - {"Keys", Func, 23}, - {"Values", Func, 23}, + {"All", Func, 23, "func[Map ~map[K]V, K comparable, V any](m Map) iter.Seq2[K, V]"}, + {"Clone", Func, 21, "func[M ~map[K]V, K comparable, V any](m M) M"}, + {"Collect", Func, 23, "func[K comparable, V any](seq iter.Seq2[K, V]) map[K]V"}, + {"Copy", Func, 21, "func[M1 ~map[K]V, M2 ~map[K]V, K comparable, V any](dst M1, src M2)"}, + {"DeleteFunc", Func, 21, "func[M ~map[K]V, K comparable, V any](m M, del func(K, V) bool)"}, + {"Equal", Func, 21, "func[M1, M2 ~map[K]V, K, V comparable](m1 M1, m2 M2) bool"}, + {"EqualFunc", Func, 21, "func[M1 ~map[K]V1, M2 ~map[K]V2, K comparable, V1, V2 any](m1 M1, m2 M2, eq func(V1, V2) bool) bool"}, + {"Insert", Func, 23, "func[Map ~map[K]V, K comparable, V any](m Map, seq iter.Seq2[K, V])"}, + {"Keys", Func, 23, "func[Map ~map[K]V, K comparable, V any](m Map) iter.Seq[K]"}, + {"Values", Func, 23, "func[Map ~map[K]V, K comparable, V any](m Map) iter.Seq[V]"}, }, "math": { - {"Abs", Func, 0}, - {"Acos", Func, 0}, - {"Acosh", Func, 0}, - {"Asin", Func, 0}, - {"Asinh", Func, 0}, - {"Atan", Func, 0}, - {"Atan2", Func, 0}, - {"Atanh", Func, 0}, - {"Cbrt", Func, 0}, - {"Ceil", Func, 0}, - {"Copysign", Func, 0}, - {"Cos", Func, 0}, - {"Cosh", Func, 0}, - {"Dim", Func, 0}, - {"E", Const, 0}, - {"Erf", Func, 0}, - {"Erfc", Func, 0}, - {"Erfcinv", Func, 10}, - {"Erfinv", Func, 10}, - {"Exp", Func, 0}, - {"Exp2", Func, 0}, - {"Expm1", Func, 0}, - {"FMA", Func, 14}, - {"Float32bits", Func, 0}, - {"Float32frombits", Func, 0}, - {"Float64bits", Func, 0}, - {"Float64frombits", Func, 0}, - {"Floor", Func, 0}, - {"Frexp", Func, 0}, - {"Gamma", Func, 0}, - {"Hypot", Func, 0}, - {"Ilogb", Func, 0}, - {"Inf", Func, 0}, - {"IsInf", Func, 0}, - {"IsNaN", Func, 0}, - {"J0", Func, 0}, - {"J1", Func, 0}, - {"Jn", Func, 0}, - {"Ldexp", Func, 0}, - {"Lgamma", Func, 0}, - {"Ln10", Const, 0}, - {"Ln2", Const, 0}, - {"Log", Func, 0}, - {"Log10", Func, 0}, - {"Log10E", Const, 0}, - {"Log1p", Func, 0}, - {"Log2", Func, 0}, - {"Log2E", Const, 0}, - {"Logb", Func, 0}, - {"Max", Func, 0}, - {"MaxFloat32", Const, 0}, - {"MaxFloat64", Const, 0}, - {"MaxInt", Const, 17}, - {"MaxInt16", Const, 0}, - {"MaxInt32", Const, 0}, - {"MaxInt64", Const, 0}, - {"MaxInt8", Const, 0}, - {"MaxUint", Const, 17}, - {"MaxUint16", Const, 0}, - {"MaxUint32", Const, 0}, - {"MaxUint64", Const, 0}, - {"MaxUint8", Const, 0}, - {"Min", Func, 0}, - {"MinInt", Const, 17}, - {"MinInt16", Const, 0}, - {"MinInt32", Const, 0}, - {"MinInt64", Const, 0}, - {"MinInt8", Const, 0}, - {"Mod", Func, 0}, - {"Modf", Func, 0}, - {"NaN", Func, 0}, - {"Nextafter", Func, 0}, - {"Nextafter32", Func, 4}, - {"Phi", Const, 0}, - {"Pi", Const, 0}, - {"Pow", Func, 0}, - {"Pow10", Func, 0}, - {"Remainder", Func, 0}, - {"Round", Func, 10}, - {"RoundToEven", Func, 10}, - {"Signbit", Func, 0}, - {"Sin", Func, 0}, - {"Sincos", Func, 0}, - {"Sinh", Func, 0}, - {"SmallestNonzeroFloat32", Const, 0}, - {"SmallestNonzeroFloat64", Const, 0}, - {"Sqrt", Func, 0}, - {"Sqrt2", Const, 0}, - {"SqrtE", Const, 0}, - {"SqrtPhi", Const, 0}, - {"SqrtPi", Const, 0}, - {"Tan", Func, 0}, - {"Tanh", Func, 0}, - {"Trunc", Func, 0}, - {"Y0", Func, 0}, - {"Y1", Func, 0}, - {"Yn", Func, 0}, + {"Abs", Func, 0, "func(x float64) float64"}, + {"Acos", Func, 0, "func(x float64) float64"}, + {"Acosh", Func, 0, "func(x float64) float64"}, + {"Asin", Func, 0, "func(x float64) float64"}, + {"Asinh", Func, 0, "func(x float64) float64"}, + {"Atan", Func, 0, "func(x float64) float64"}, + {"Atan2", Func, 0, "func(y float64, x float64) float64"}, + {"Atanh", Func, 0, "func(x float64) float64"}, + {"Cbrt", Func, 0, "func(x float64) float64"}, + {"Ceil", Func, 0, "func(x float64) float64"}, + {"Copysign", Func, 0, "func(f float64, sign float64) float64"}, + {"Cos", Func, 0, "func(x float64) float64"}, + {"Cosh", Func, 0, "func(x float64) float64"}, + {"Dim", Func, 0, "func(x float64, y float64) float64"}, + {"E", Const, 0, ""}, + {"Erf", Func, 0, "func(x float64) float64"}, + {"Erfc", Func, 0, "func(x float64) float64"}, + {"Erfcinv", Func, 10, "func(x float64) float64"}, + {"Erfinv", Func, 10, "func(x float64) float64"}, + {"Exp", Func, 0, "func(x float64) float64"}, + {"Exp2", Func, 0, "func(x float64) float64"}, + {"Expm1", Func, 0, "func(x float64) float64"}, + {"FMA", Func, 14, "func(x float64, y float64, z float64) float64"}, + {"Float32bits", Func, 0, "func(f float32) uint32"}, + {"Float32frombits", Func, 0, "func(b uint32) float32"}, + {"Float64bits", Func, 0, "func(f float64) uint64"}, + {"Float64frombits", Func, 0, "func(b uint64) float64"}, + {"Floor", Func, 0, "func(x float64) float64"}, + {"Frexp", Func, 0, "func(f float64) (frac float64, exp int)"}, + {"Gamma", Func, 0, "func(x float64) float64"}, + {"Hypot", Func, 0, "func(p float64, q float64) float64"}, + {"Ilogb", Func, 0, "func(x float64) int"}, + {"Inf", Func, 0, "func(sign int) float64"}, + {"IsInf", Func, 0, "func(f float64, sign int) bool"}, + {"IsNaN", Func, 0, "func(f float64) (is bool)"}, + {"J0", Func, 0, "func(x float64) float64"}, + {"J1", Func, 0, "func(x float64) float64"}, + {"Jn", Func, 0, "func(n int, x float64) float64"}, + {"Ldexp", Func, 0, "func(frac float64, exp int) float64"}, + {"Lgamma", Func, 0, "func(x float64) (lgamma float64, sign int)"}, + {"Ln10", Const, 0, ""}, + {"Ln2", Const, 0, ""}, + {"Log", Func, 0, "func(x float64) float64"}, + {"Log10", Func, 0, "func(x float64) float64"}, + {"Log10E", Const, 0, ""}, + {"Log1p", Func, 0, "func(x float64) float64"}, + {"Log2", Func, 0, "func(x float64) float64"}, + {"Log2E", Const, 0, ""}, + {"Logb", Func, 0, "func(x float64) float64"}, + {"Max", Func, 0, "func(x float64, y float64) float64"}, + {"MaxFloat32", Const, 0, ""}, + {"MaxFloat64", Const, 0, ""}, + {"MaxInt", Const, 17, ""}, + {"MaxInt16", Const, 0, ""}, + {"MaxInt32", Const, 0, ""}, + {"MaxInt64", Const, 0, ""}, + {"MaxInt8", Const, 0, ""}, + {"MaxUint", Const, 17, ""}, + {"MaxUint16", Const, 0, ""}, + {"MaxUint32", Const, 0, ""}, + {"MaxUint64", Const, 0, ""}, + {"MaxUint8", Const, 0, ""}, + {"Min", Func, 0, "func(x float64, y float64) float64"}, + {"MinInt", Const, 17, ""}, + {"MinInt16", Const, 0, ""}, + {"MinInt32", Const, 0, ""}, + {"MinInt64", Const, 0, ""}, + {"MinInt8", Const, 0, ""}, + {"Mod", Func, 0, "func(x float64, y float64) float64"}, + {"Modf", Func, 0, "func(f float64) (int float64, frac float64)"}, + {"NaN", Func, 0, "func() float64"}, + {"Nextafter", Func, 0, "func(x float64, y float64) (r float64)"}, + {"Nextafter32", Func, 4, "func(x float32, y float32) (r float32)"}, + {"Phi", Const, 0, ""}, + {"Pi", Const, 0, ""}, + {"Pow", Func, 0, "func(x float64, y float64) float64"}, + {"Pow10", Func, 0, "func(n int) float64"}, + {"Remainder", Func, 0, "func(x float64, y float64) float64"}, + {"Round", Func, 10, "func(x float64) float64"}, + {"RoundToEven", Func, 10, "func(x float64) float64"}, + {"Signbit", Func, 0, "func(x float64) bool"}, + {"Sin", Func, 0, "func(x float64) float64"}, + {"Sincos", Func, 0, "func(x float64) (sin float64, cos float64)"}, + {"Sinh", Func, 0, "func(x float64) float64"}, + {"SmallestNonzeroFloat32", Const, 0, ""}, + {"SmallestNonzeroFloat64", Const, 0, ""}, + {"Sqrt", Func, 0, "func(x float64) float64"}, + {"Sqrt2", Const, 0, ""}, + {"SqrtE", Const, 0, ""}, + {"SqrtPhi", Const, 0, ""}, + {"SqrtPi", Const, 0, ""}, + {"Tan", Func, 0, "func(x float64) float64"}, + {"Tanh", Func, 0, "func(x float64) float64"}, + {"Trunc", Func, 0, "func(x float64) float64"}, + {"Y0", Func, 0, "func(x float64) float64"}, + {"Y1", Func, 0, "func(x float64) float64"}, + {"Yn", Func, 0, "func(n int, x float64) float64"}, }, "math/big": { - {"(*Float).Abs", Method, 5}, - {"(*Float).Acc", Method, 5}, - {"(*Float).Add", Method, 5}, - {"(*Float).Append", Method, 5}, - {"(*Float).AppendText", Method, 24}, - {"(*Float).Cmp", Method, 5}, - {"(*Float).Copy", Method, 5}, - {"(*Float).Float32", Method, 5}, - {"(*Float).Float64", Method, 5}, - {"(*Float).Format", Method, 5}, - {"(*Float).GobDecode", Method, 7}, - {"(*Float).GobEncode", Method, 7}, - {"(*Float).Int", Method, 5}, - {"(*Float).Int64", Method, 5}, - {"(*Float).IsInf", Method, 5}, - {"(*Float).IsInt", Method, 5}, - {"(*Float).MantExp", Method, 5}, - {"(*Float).MarshalText", Method, 6}, - {"(*Float).MinPrec", Method, 5}, - {"(*Float).Mode", Method, 5}, - {"(*Float).Mul", Method, 5}, - {"(*Float).Neg", Method, 5}, - {"(*Float).Parse", Method, 5}, - {"(*Float).Prec", Method, 5}, - {"(*Float).Quo", Method, 5}, - {"(*Float).Rat", Method, 5}, - {"(*Float).Scan", Method, 8}, - {"(*Float).Set", Method, 5}, - {"(*Float).SetFloat64", Method, 5}, - {"(*Float).SetInf", Method, 5}, - {"(*Float).SetInt", Method, 5}, - {"(*Float).SetInt64", Method, 5}, - {"(*Float).SetMantExp", Method, 5}, - {"(*Float).SetMode", Method, 5}, - {"(*Float).SetPrec", Method, 5}, - {"(*Float).SetRat", Method, 5}, - {"(*Float).SetString", Method, 5}, - {"(*Float).SetUint64", Method, 5}, - {"(*Float).Sign", Method, 5}, - {"(*Float).Signbit", Method, 5}, - {"(*Float).Sqrt", Method, 10}, - {"(*Float).String", Method, 5}, - {"(*Float).Sub", Method, 5}, - {"(*Float).Text", Method, 5}, - {"(*Float).Uint64", Method, 5}, - {"(*Float).UnmarshalText", Method, 6}, - {"(*Int).Abs", Method, 0}, - {"(*Int).Add", Method, 0}, - {"(*Int).And", Method, 0}, - {"(*Int).AndNot", Method, 0}, - {"(*Int).Append", Method, 6}, - {"(*Int).AppendText", Method, 24}, - {"(*Int).Binomial", Method, 0}, - {"(*Int).Bit", Method, 0}, - {"(*Int).BitLen", Method, 0}, - {"(*Int).Bits", Method, 0}, - {"(*Int).Bytes", Method, 0}, - {"(*Int).Cmp", Method, 0}, - {"(*Int).CmpAbs", Method, 10}, - {"(*Int).Div", Method, 0}, - {"(*Int).DivMod", Method, 0}, - {"(*Int).Exp", Method, 0}, - {"(*Int).FillBytes", Method, 15}, - {"(*Int).Float64", Method, 21}, - {"(*Int).Format", Method, 0}, - {"(*Int).GCD", Method, 0}, - {"(*Int).GobDecode", Method, 0}, - {"(*Int).GobEncode", Method, 0}, - {"(*Int).Int64", Method, 0}, - {"(*Int).IsInt64", Method, 9}, - {"(*Int).IsUint64", Method, 9}, - {"(*Int).Lsh", Method, 0}, - {"(*Int).MarshalJSON", Method, 1}, - {"(*Int).MarshalText", Method, 3}, - {"(*Int).Mod", Method, 0}, - {"(*Int).ModInverse", Method, 0}, - {"(*Int).ModSqrt", Method, 5}, - {"(*Int).Mul", Method, 0}, - {"(*Int).MulRange", Method, 0}, - {"(*Int).Neg", Method, 0}, - {"(*Int).Not", Method, 0}, - {"(*Int).Or", Method, 0}, - {"(*Int).ProbablyPrime", Method, 0}, - {"(*Int).Quo", Method, 0}, - {"(*Int).QuoRem", Method, 0}, - {"(*Int).Rand", Method, 0}, - {"(*Int).Rem", Method, 0}, - {"(*Int).Rsh", Method, 0}, - {"(*Int).Scan", Method, 0}, - {"(*Int).Set", Method, 0}, - {"(*Int).SetBit", Method, 0}, - {"(*Int).SetBits", Method, 0}, - {"(*Int).SetBytes", Method, 0}, - {"(*Int).SetInt64", Method, 0}, - {"(*Int).SetString", Method, 0}, - {"(*Int).SetUint64", Method, 1}, - {"(*Int).Sign", Method, 0}, - {"(*Int).Sqrt", Method, 8}, - {"(*Int).String", Method, 0}, - {"(*Int).Sub", Method, 0}, - {"(*Int).Text", Method, 6}, - {"(*Int).TrailingZeroBits", Method, 13}, - {"(*Int).Uint64", Method, 1}, - {"(*Int).UnmarshalJSON", Method, 1}, - {"(*Int).UnmarshalText", Method, 3}, - {"(*Int).Xor", Method, 0}, - {"(*Rat).Abs", Method, 0}, - {"(*Rat).Add", Method, 0}, - {"(*Rat).AppendText", Method, 24}, - {"(*Rat).Cmp", Method, 0}, - {"(*Rat).Denom", Method, 0}, - {"(*Rat).Float32", Method, 4}, - {"(*Rat).Float64", Method, 1}, - {"(*Rat).FloatPrec", Method, 22}, - {"(*Rat).FloatString", Method, 0}, - {"(*Rat).GobDecode", Method, 0}, - {"(*Rat).GobEncode", Method, 0}, - {"(*Rat).Inv", Method, 0}, - {"(*Rat).IsInt", Method, 0}, - {"(*Rat).MarshalText", Method, 3}, - {"(*Rat).Mul", Method, 0}, - {"(*Rat).Neg", Method, 0}, - {"(*Rat).Num", Method, 0}, - {"(*Rat).Quo", Method, 0}, - {"(*Rat).RatString", Method, 0}, - {"(*Rat).Scan", Method, 0}, - {"(*Rat).Set", Method, 0}, - {"(*Rat).SetFloat64", Method, 1}, - {"(*Rat).SetFrac", Method, 0}, - {"(*Rat).SetFrac64", Method, 0}, - {"(*Rat).SetInt", Method, 0}, - {"(*Rat).SetInt64", Method, 0}, - {"(*Rat).SetString", Method, 0}, - {"(*Rat).SetUint64", Method, 13}, - {"(*Rat).Sign", Method, 0}, - {"(*Rat).String", Method, 0}, - {"(*Rat).Sub", Method, 0}, - {"(*Rat).UnmarshalText", Method, 3}, - {"(Accuracy).String", Method, 5}, - {"(ErrNaN).Error", Method, 5}, - {"(RoundingMode).String", Method, 5}, - {"Above", Const, 5}, - {"Accuracy", Type, 5}, - {"AwayFromZero", Const, 5}, - {"Below", Const, 5}, - {"ErrNaN", Type, 5}, - {"Exact", Const, 5}, - {"Float", Type, 5}, - {"Int", Type, 0}, - {"Jacobi", Func, 5}, - {"MaxBase", Const, 0}, - {"MaxExp", Const, 5}, - {"MaxPrec", Const, 5}, - {"MinExp", Const, 5}, - {"NewFloat", Func, 5}, - {"NewInt", Func, 0}, - {"NewRat", Func, 0}, - {"ParseFloat", Func, 5}, - {"Rat", Type, 0}, - {"RoundingMode", Type, 5}, - {"ToNearestAway", Const, 5}, - {"ToNearestEven", Const, 5}, - {"ToNegativeInf", Const, 5}, - {"ToPositiveInf", Const, 5}, - {"ToZero", Const, 5}, - {"Word", Type, 0}, + {"(*Float).Abs", Method, 5, ""}, + {"(*Float).Acc", Method, 5, ""}, + {"(*Float).Add", Method, 5, ""}, + {"(*Float).Append", Method, 5, ""}, + {"(*Float).AppendText", Method, 24, ""}, + {"(*Float).Cmp", Method, 5, ""}, + {"(*Float).Copy", Method, 5, ""}, + {"(*Float).Float32", Method, 5, ""}, + {"(*Float).Float64", Method, 5, ""}, + {"(*Float).Format", Method, 5, ""}, + {"(*Float).GobDecode", Method, 7, ""}, + {"(*Float).GobEncode", Method, 7, ""}, + {"(*Float).Int", Method, 5, ""}, + {"(*Float).Int64", Method, 5, ""}, + {"(*Float).IsInf", Method, 5, ""}, + {"(*Float).IsInt", Method, 5, ""}, + {"(*Float).MantExp", Method, 5, ""}, + {"(*Float).MarshalText", Method, 6, ""}, + {"(*Float).MinPrec", Method, 5, ""}, + {"(*Float).Mode", Method, 5, ""}, + {"(*Float).Mul", Method, 5, ""}, + {"(*Float).Neg", Method, 5, ""}, + {"(*Float).Parse", Method, 5, ""}, + {"(*Float).Prec", Method, 5, ""}, + {"(*Float).Quo", Method, 5, ""}, + {"(*Float).Rat", Method, 5, ""}, + {"(*Float).Scan", Method, 8, ""}, + {"(*Float).Set", Method, 5, ""}, + {"(*Float).SetFloat64", Method, 5, ""}, + {"(*Float).SetInf", Method, 5, ""}, + {"(*Float).SetInt", Method, 5, ""}, + {"(*Float).SetInt64", Method, 5, ""}, + {"(*Float).SetMantExp", Method, 5, ""}, + {"(*Float).SetMode", Method, 5, ""}, + {"(*Float).SetPrec", Method, 5, ""}, + {"(*Float).SetRat", Method, 5, ""}, + {"(*Float).SetString", Method, 5, ""}, + {"(*Float).SetUint64", Method, 5, ""}, + {"(*Float).Sign", Method, 5, ""}, + {"(*Float).Signbit", Method, 5, ""}, + {"(*Float).Sqrt", Method, 10, ""}, + {"(*Float).String", Method, 5, ""}, + {"(*Float).Sub", Method, 5, ""}, + {"(*Float).Text", Method, 5, ""}, + {"(*Float).Uint64", Method, 5, ""}, + {"(*Float).UnmarshalText", Method, 6, ""}, + {"(*Int).Abs", Method, 0, ""}, + {"(*Int).Add", Method, 0, ""}, + {"(*Int).And", Method, 0, ""}, + {"(*Int).AndNot", Method, 0, ""}, + {"(*Int).Append", Method, 6, ""}, + {"(*Int).AppendText", Method, 24, ""}, + {"(*Int).Binomial", Method, 0, ""}, + {"(*Int).Bit", Method, 0, ""}, + {"(*Int).BitLen", Method, 0, ""}, + {"(*Int).Bits", Method, 0, ""}, + {"(*Int).Bytes", Method, 0, ""}, + {"(*Int).Cmp", Method, 0, ""}, + {"(*Int).CmpAbs", Method, 10, ""}, + {"(*Int).Div", Method, 0, ""}, + {"(*Int).DivMod", Method, 0, ""}, + {"(*Int).Exp", Method, 0, ""}, + {"(*Int).FillBytes", Method, 15, ""}, + {"(*Int).Float64", Method, 21, ""}, + {"(*Int).Format", Method, 0, ""}, + {"(*Int).GCD", Method, 0, ""}, + {"(*Int).GobDecode", Method, 0, ""}, + {"(*Int).GobEncode", Method, 0, ""}, + {"(*Int).Int64", Method, 0, ""}, + {"(*Int).IsInt64", Method, 9, ""}, + {"(*Int).IsUint64", Method, 9, ""}, + {"(*Int).Lsh", Method, 0, ""}, + {"(*Int).MarshalJSON", Method, 1, ""}, + {"(*Int).MarshalText", Method, 3, ""}, + {"(*Int).Mod", Method, 0, ""}, + {"(*Int).ModInverse", Method, 0, ""}, + {"(*Int).ModSqrt", Method, 5, ""}, + {"(*Int).Mul", Method, 0, ""}, + {"(*Int).MulRange", Method, 0, ""}, + {"(*Int).Neg", Method, 0, ""}, + {"(*Int).Not", Method, 0, ""}, + {"(*Int).Or", Method, 0, ""}, + {"(*Int).ProbablyPrime", Method, 0, ""}, + {"(*Int).Quo", Method, 0, ""}, + {"(*Int).QuoRem", Method, 0, ""}, + {"(*Int).Rand", Method, 0, ""}, + {"(*Int).Rem", Method, 0, ""}, + {"(*Int).Rsh", Method, 0, ""}, + {"(*Int).Scan", Method, 0, ""}, + {"(*Int).Set", Method, 0, ""}, + {"(*Int).SetBit", Method, 0, ""}, + {"(*Int).SetBits", Method, 0, ""}, + {"(*Int).SetBytes", Method, 0, ""}, + {"(*Int).SetInt64", Method, 0, ""}, + {"(*Int).SetString", Method, 0, ""}, + {"(*Int).SetUint64", Method, 1, ""}, + {"(*Int).Sign", Method, 0, ""}, + {"(*Int).Sqrt", Method, 8, ""}, + {"(*Int).String", Method, 0, ""}, + {"(*Int).Sub", Method, 0, ""}, + {"(*Int).Text", Method, 6, ""}, + {"(*Int).TrailingZeroBits", Method, 13, ""}, + {"(*Int).Uint64", Method, 1, ""}, + {"(*Int).UnmarshalJSON", Method, 1, ""}, + {"(*Int).UnmarshalText", Method, 3, ""}, + {"(*Int).Xor", Method, 0, ""}, + {"(*Rat).Abs", Method, 0, ""}, + {"(*Rat).Add", Method, 0, ""}, + {"(*Rat).AppendText", Method, 24, ""}, + {"(*Rat).Cmp", Method, 0, ""}, + {"(*Rat).Denom", Method, 0, ""}, + {"(*Rat).Float32", Method, 4, ""}, + {"(*Rat).Float64", Method, 1, ""}, + {"(*Rat).FloatPrec", Method, 22, ""}, + {"(*Rat).FloatString", Method, 0, ""}, + {"(*Rat).GobDecode", Method, 0, ""}, + {"(*Rat).GobEncode", Method, 0, ""}, + {"(*Rat).Inv", Method, 0, ""}, + {"(*Rat).IsInt", Method, 0, ""}, + {"(*Rat).MarshalText", Method, 3, ""}, + {"(*Rat).Mul", Method, 0, ""}, + {"(*Rat).Neg", Method, 0, ""}, + {"(*Rat).Num", Method, 0, ""}, + {"(*Rat).Quo", Method, 0, ""}, + {"(*Rat).RatString", Method, 0, ""}, + {"(*Rat).Scan", Method, 0, ""}, + {"(*Rat).Set", Method, 0, ""}, + {"(*Rat).SetFloat64", Method, 1, ""}, + {"(*Rat).SetFrac", Method, 0, ""}, + {"(*Rat).SetFrac64", Method, 0, ""}, + {"(*Rat).SetInt", Method, 0, ""}, + {"(*Rat).SetInt64", Method, 0, ""}, + {"(*Rat).SetString", Method, 0, ""}, + {"(*Rat).SetUint64", Method, 13, ""}, + {"(*Rat).Sign", Method, 0, ""}, + {"(*Rat).String", Method, 0, ""}, + {"(*Rat).Sub", Method, 0, ""}, + {"(*Rat).UnmarshalText", Method, 3, ""}, + {"(Accuracy).String", Method, 5, ""}, + {"(ErrNaN).Error", Method, 5, ""}, + {"(RoundingMode).String", Method, 5, ""}, + {"Above", Const, 5, ""}, + {"Accuracy", Type, 5, ""}, + {"AwayFromZero", Const, 5, ""}, + {"Below", Const, 5, ""}, + {"ErrNaN", Type, 5, ""}, + {"Exact", Const, 5, ""}, + {"Float", Type, 5, ""}, + {"Int", Type, 0, ""}, + {"Jacobi", Func, 5, "func(x *Int, y *Int) int"}, + {"MaxBase", Const, 0, ""}, + {"MaxExp", Const, 5, ""}, + {"MaxPrec", Const, 5, ""}, + {"MinExp", Const, 5, ""}, + {"NewFloat", Func, 5, "func(x float64) *Float"}, + {"NewInt", Func, 0, "func(x int64) *Int"}, + {"NewRat", Func, 0, "func(a int64, b int64) *Rat"}, + {"ParseFloat", Func, 5, "func(s string, base int, prec uint, mode RoundingMode) (f *Float, b int, err error)"}, + {"Rat", Type, 0, ""}, + {"RoundingMode", Type, 5, ""}, + {"ToNearestAway", Const, 5, ""}, + {"ToNearestEven", Const, 5, ""}, + {"ToNegativeInf", Const, 5, ""}, + {"ToPositiveInf", Const, 5, ""}, + {"ToZero", Const, 5, ""}, + {"Word", Type, 0, ""}, }, "math/bits": { - {"Add", Func, 12}, - {"Add32", Func, 12}, - {"Add64", Func, 12}, - {"Div", Func, 12}, - {"Div32", Func, 12}, - {"Div64", Func, 12}, - {"LeadingZeros", Func, 9}, - {"LeadingZeros16", Func, 9}, - {"LeadingZeros32", Func, 9}, - {"LeadingZeros64", Func, 9}, - {"LeadingZeros8", Func, 9}, - {"Len", Func, 9}, - {"Len16", Func, 9}, - {"Len32", Func, 9}, - {"Len64", Func, 9}, - {"Len8", Func, 9}, - {"Mul", Func, 12}, - {"Mul32", Func, 12}, - {"Mul64", Func, 12}, - {"OnesCount", Func, 9}, - {"OnesCount16", Func, 9}, - {"OnesCount32", Func, 9}, - {"OnesCount64", Func, 9}, - {"OnesCount8", Func, 9}, - {"Rem", Func, 14}, - {"Rem32", Func, 14}, - {"Rem64", Func, 14}, - {"Reverse", Func, 9}, - {"Reverse16", Func, 9}, - {"Reverse32", Func, 9}, - {"Reverse64", Func, 9}, - {"Reverse8", Func, 9}, - {"ReverseBytes", Func, 9}, - {"ReverseBytes16", Func, 9}, - {"ReverseBytes32", Func, 9}, - {"ReverseBytes64", Func, 9}, - {"RotateLeft", Func, 9}, - {"RotateLeft16", Func, 9}, - {"RotateLeft32", Func, 9}, - {"RotateLeft64", Func, 9}, - {"RotateLeft8", Func, 9}, - {"Sub", Func, 12}, - {"Sub32", Func, 12}, - {"Sub64", Func, 12}, - {"TrailingZeros", Func, 9}, - {"TrailingZeros16", Func, 9}, - {"TrailingZeros32", Func, 9}, - {"TrailingZeros64", Func, 9}, - {"TrailingZeros8", Func, 9}, - {"UintSize", Const, 9}, + {"Add", Func, 12, "func(x uint, y uint, carry uint) (sum uint, carryOut uint)"}, + {"Add32", Func, 12, "func(x uint32, y uint32, carry uint32) (sum uint32, carryOut uint32)"}, + {"Add64", Func, 12, "func(x uint64, y uint64, carry uint64) (sum uint64, carryOut uint64)"}, + {"Div", Func, 12, "func(hi uint, lo uint, y uint) (quo uint, rem uint)"}, + {"Div32", Func, 12, "func(hi uint32, lo uint32, y uint32) (quo uint32, rem uint32)"}, + {"Div64", Func, 12, "func(hi uint64, lo uint64, y uint64) (quo uint64, rem uint64)"}, + {"LeadingZeros", Func, 9, "func(x uint) int"}, + {"LeadingZeros16", Func, 9, "func(x uint16) int"}, + {"LeadingZeros32", Func, 9, "func(x uint32) int"}, + {"LeadingZeros64", Func, 9, "func(x uint64) int"}, + {"LeadingZeros8", Func, 9, "func(x uint8) int"}, + {"Len", Func, 9, "func(x uint) int"}, + {"Len16", Func, 9, "func(x uint16) (n int)"}, + {"Len32", Func, 9, "func(x uint32) (n int)"}, + {"Len64", Func, 9, "func(x uint64) (n int)"}, + {"Len8", Func, 9, "func(x uint8) int"}, + {"Mul", Func, 12, "func(x uint, y uint) (hi uint, lo uint)"}, + {"Mul32", Func, 12, "func(x uint32, y uint32) (hi uint32, lo uint32)"}, + {"Mul64", Func, 12, "func(x uint64, y uint64) (hi uint64, lo uint64)"}, + {"OnesCount", Func, 9, "func(x uint) int"}, + {"OnesCount16", Func, 9, "func(x uint16) int"}, + {"OnesCount32", Func, 9, "func(x uint32) int"}, + {"OnesCount64", Func, 9, "func(x uint64) int"}, + {"OnesCount8", Func, 9, "func(x uint8) int"}, + {"Rem", Func, 14, "func(hi uint, lo uint, y uint) uint"}, + {"Rem32", Func, 14, "func(hi uint32, lo uint32, y uint32) uint32"}, + {"Rem64", Func, 14, "func(hi uint64, lo uint64, y uint64) uint64"}, + {"Reverse", Func, 9, "func(x uint) uint"}, + {"Reverse16", Func, 9, "func(x uint16) uint16"}, + {"Reverse32", Func, 9, "func(x uint32) uint32"}, + {"Reverse64", Func, 9, "func(x uint64) uint64"}, + {"Reverse8", Func, 9, "func(x uint8) uint8"}, + {"ReverseBytes", Func, 9, "func(x uint) uint"}, + {"ReverseBytes16", Func, 9, "func(x uint16) uint16"}, + {"ReverseBytes32", Func, 9, "func(x uint32) uint32"}, + {"ReverseBytes64", Func, 9, "func(x uint64) uint64"}, + {"RotateLeft", Func, 9, "func(x uint, k int) uint"}, + {"RotateLeft16", Func, 9, "func(x uint16, k int) uint16"}, + {"RotateLeft32", Func, 9, "func(x uint32, k int) uint32"}, + {"RotateLeft64", Func, 9, "func(x uint64, k int) uint64"}, + {"RotateLeft8", Func, 9, "func(x uint8, k int) uint8"}, + {"Sub", Func, 12, "func(x uint, y uint, borrow uint) (diff uint, borrowOut uint)"}, + {"Sub32", Func, 12, "func(x uint32, y uint32, borrow uint32) (diff uint32, borrowOut uint32)"}, + {"Sub64", Func, 12, "func(x uint64, y uint64, borrow uint64) (diff uint64, borrowOut uint64)"}, + {"TrailingZeros", Func, 9, "func(x uint) int"}, + {"TrailingZeros16", Func, 9, "func(x uint16) int"}, + {"TrailingZeros32", Func, 9, "func(x uint32) int"}, + {"TrailingZeros64", Func, 9, "func(x uint64) int"}, + {"TrailingZeros8", Func, 9, "func(x uint8) int"}, + {"UintSize", Const, 9, ""}, }, "math/cmplx": { - {"Abs", Func, 0}, - {"Acos", Func, 0}, - {"Acosh", Func, 0}, - {"Asin", Func, 0}, - {"Asinh", Func, 0}, - {"Atan", Func, 0}, - {"Atanh", Func, 0}, - {"Conj", Func, 0}, - {"Cos", Func, 0}, - {"Cosh", Func, 0}, - {"Cot", Func, 0}, - {"Exp", Func, 0}, - {"Inf", Func, 0}, - {"IsInf", Func, 0}, - {"IsNaN", Func, 0}, - {"Log", Func, 0}, - {"Log10", Func, 0}, - {"NaN", Func, 0}, - {"Phase", Func, 0}, - {"Polar", Func, 0}, - {"Pow", Func, 0}, - {"Rect", Func, 0}, - {"Sin", Func, 0}, - {"Sinh", Func, 0}, - {"Sqrt", Func, 0}, - {"Tan", Func, 0}, - {"Tanh", Func, 0}, + {"Abs", Func, 0, "func(x complex128) float64"}, + {"Acos", Func, 0, "func(x complex128) complex128"}, + {"Acosh", Func, 0, "func(x complex128) complex128"}, + {"Asin", Func, 0, "func(x complex128) complex128"}, + {"Asinh", Func, 0, "func(x complex128) complex128"}, + {"Atan", Func, 0, "func(x complex128) complex128"}, + {"Atanh", Func, 0, "func(x complex128) complex128"}, + {"Conj", Func, 0, "func(x complex128) complex128"}, + {"Cos", Func, 0, "func(x complex128) complex128"}, + {"Cosh", Func, 0, "func(x complex128) complex128"}, + {"Cot", Func, 0, "func(x complex128) complex128"}, + {"Exp", Func, 0, "func(x complex128) complex128"}, + {"Inf", Func, 0, "func() complex128"}, + {"IsInf", Func, 0, "func(x complex128) bool"}, + {"IsNaN", Func, 0, "func(x complex128) bool"}, + {"Log", Func, 0, "func(x complex128) complex128"}, + {"Log10", Func, 0, "func(x complex128) complex128"}, + {"NaN", Func, 0, "func() complex128"}, + {"Phase", Func, 0, "func(x complex128) float64"}, + {"Polar", Func, 0, "func(x complex128) (r float64, θ float64)"}, + {"Pow", Func, 0, "func(x complex128, y complex128) complex128"}, + {"Rect", Func, 0, "func(r float64, θ float64) complex128"}, + {"Sin", Func, 0, "func(x complex128) complex128"}, + {"Sinh", Func, 0, "func(x complex128) complex128"}, + {"Sqrt", Func, 0, "func(x complex128) complex128"}, + {"Tan", Func, 0, "func(x complex128) complex128"}, + {"Tanh", Func, 0, "func(x complex128) complex128"}, }, "math/rand": { - {"(*Rand).ExpFloat64", Method, 0}, - {"(*Rand).Float32", Method, 0}, - {"(*Rand).Float64", Method, 0}, - {"(*Rand).Int", Method, 0}, - {"(*Rand).Int31", Method, 0}, - {"(*Rand).Int31n", Method, 0}, - {"(*Rand).Int63", Method, 0}, - {"(*Rand).Int63n", Method, 0}, - {"(*Rand).Intn", Method, 0}, - {"(*Rand).NormFloat64", Method, 0}, - {"(*Rand).Perm", Method, 0}, - {"(*Rand).Read", Method, 6}, - {"(*Rand).Seed", Method, 0}, - {"(*Rand).Shuffle", Method, 10}, - {"(*Rand).Uint32", Method, 0}, - {"(*Rand).Uint64", Method, 8}, - {"(*Zipf).Uint64", Method, 0}, - {"ExpFloat64", Func, 0}, - {"Float32", Func, 0}, - {"Float64", Func, 0}, - {"Int", Func, 0}, - {"Int31", Func, 0}, - {"Int31n", Func, 0}, - {"Int63", Func, 0}, - {"Int63n", Func, 0}, - {"Intn", Func, 0}, - {"New", Func, 0}, - {"NewSource", Func, 0}, - {"NewZipf", Func, 0}, - {"NormFloat64", Func, 0}, - {"Perm", Func, 0}, - {"Rand", Type, 0}, - {"Read", Func, 6}, - {"Seed", Func, 0}, - {"Shuffle", Func, 10}, - {"Source", Type, 0}, - {"Source64", Type, 8}, - {"Uint32", Func, 0}, - {"Uint64", Func, 8}, - {"Zipf", Type, 0}, + {"(*Rand).ExpFloat64", Method, 0, ""}, + {"(*Rand).Float32", Method, 0, ""}, + {"(*Rand).Float64", Method, 0, ""}, + {"(*Rand).Int", Method, 0, ""}, + {"(*Rand).Int31", Method, 0, ""}, + {"(*Rand).Int31n", Method, 0, ""}, + {"(*Rand).Int63", Method, 0, ""}, + {"(*Rand).Int63n", Method, 0, ""}, + {"(*Rand).Intn", Method, 0, ""}, + {"(*Rand).NormFloat64", Method, 0, ""}, + {"(*Rand).Perm", Method, 0, ""}, + {"(*Rand).Read", Method, 6, ""}, + {"(*Rand).Seed", Method, 0, ""}, + {"(*Rand).Shuffle", Method, 10, ""}, + {"(*Rand).Uint32", Method, 0, ""}, + {"(*Rand).Uint64", Method, 8, ""}, + {"(*Zipf).Uint64", Method, 0, ""}, + {"ExpFloat64", Func, 0, "func() float64"}, + {"Float32", Func, 0, "func() float32"}, + {"Float64", Func, 0, "func() float64"}, + {"Int", Func, 0, "func() int"}, + {"Int31", Func, 0, "func() int32"}, + {"Int31n", Func, 0, "func(n int32) int32"}, + {"Int63", Func, 0, "func() int64"}, + {"Int63n", Func, 0, "func(n int64) int64"}, + {"Intn", Func, 0, "func(n int) int"}, + {"New", Func, 0, "func(src Source) *Rand"}, + {"NewSource", Func, 0, "func(seed int64) Source"}, + {"NewZipf", Func, 0, "func(r *Rand, s float64, v float64, imax uint64) *Zipf"}, + {"NormFloat64", Func, 0, "func() float64"}, + {"Perm", Func, 0, "func(n int) []int"}, + {"Rand", Type, 0, ""}, + {"Read", Func, 6, "func(p []byte) (n int, err error)"}, + {"Seed", Func, 0, "func(seed int64)"}, + {"Shuffle", Func, 10, "func(n int, swap func(i int, j int))"}, + {"Source", Type, 0, ""}, + {"Source64", Type, 8, ""}, + {"Uint32", Func, 0, "func() uint32"}, + {"Uint64", Func, 8, "func() uint64"}, + {"Zipf", Type, 0, ""}, }, "math/rand/v2": { - {"(*ChaCha8).AppendBinary", Method, 24}, - {"(*ChaCha8).MarshalBinary", Method, 22}, - {"(*ChaCha8).Read", Method, 23}, - {"(*ChaCha8).Seed", Method, 22}, - {"(*ChaCha8).Uint64", Method, 22}, - {"(*ChaCha8).UnmarshalBinary", Method, 22}, - {"(*PCG).AppendBinary", Method, 24}, - {"(*PCG).MarshalBinary", Method, 22}, - {"(*PCG).Seed", Method, 22}, - {"(*PCG).Uint64", Method, 22}, - {"(*PCG).UnmarshalBinary", Method, 22}, - {"(*Rand).ExpFloat64", Method, 22}, - {"(*Rand).Float32", Method, 22}, - {"(*Rand).Float64", Method, 22}, - {"(*Rand).Int", Method, 22}, - {"(*Rand).Int32", Method, 22}, - {"(*Rand).Int32N", Method, 22}, - {"(*Rand).Int64", Method, 22}, - {"(*Rand).Int64N", Method, 22}, - {"(*Rand).IntN", Method, 22}, - {"(*Rand).NormFloat64", Method, 22}, - {"(*Rand).Perm", Method, 22}, - {"(*Rand).Shuffle", Method, 22}, - {"(*Rand).Uint", Method, 23}, - {"(*Rand).Uint32", Method, 22}, - {"(*Rand).Uint32N", Method, 22}, - {"(*Rand).Uint64", Method, 22}, - {"(*Rand).Uint64N", Method, 22}, - {"(*Rand).UintN", Method, 22}, - {"(*Zipf).Uint64", Method, 22}, - {"ChaCha8", Type, 22}, - {"ExpFloat64", Func, 22}, - {"Float32", Func, 22}, - {"Float64", Func, 22}, - {"Int", Func, 22}, - {"Int32", Func, 22}, - {"Int32N", Func, 22}, - {"Int64", Func, 22}, - {"Int64N", Func, 22}, - {"IntN", Func, 22}, - {"N", Func, 22}, - {"New", Func, 22}, - {"NewChaCha8", Func, 22}, - {"NewPCG", Func, 22}, - {"NewZipf", Func, 22}, - {"NormFloat64", Func, 22}, - {"PCG", Type, 22}, - {"Perm", Func, 22}, - {"Rand", Type, 22}, - {"Shuffle", Func, 22}, - {"Source", Type, 22}, - {"Uint", Func, 23}, - {"Uint32", Func, 22}, - {"Uint32N", Func, 22}, - {"Uint64", Func, 22}, - {"Uint64N", Func, 22}, - {"UintN", Func, 22}, - {"Zipf", Type, 22}, + {"(*ChaCha8).AppendBinary", Method, 24, ""}, + {"(*ChaCha8).MarshalBinary", Method, 22, ""}, + {"(*ChaCha8).Read", Method, 23, ""}, + {"(*ChaCha8).Seed", Method, 22, ""}, + {"(*ChaCha8).Uint64", Method, 22, ""}, + {"(*ChaCha8).UnmarshalBinary", Method, 22, ""}, + {"(*PCG).AppendBinary", Method, 24, ""}, + {"(*PCG).MarshalBinary", Method, 22, ""}, + {"(*PCG).Seed", Method, 22, ""}, + {"(*PCG).Uint64", Method, 22, ""}, + {"(*PCG).UnmarshalBinary", Method, 22, ""}, + {"(*Rand).ExpFloat64", Method, 22, ""}, + {"(*Rand).Float32", Method, 22, ""}, + {"(*Rand).Float64", Method, 22, ""}, + {"(*Rand).Int", Method, 22, ""}, + {"(*Rand).Int32", Method, 22, ""}, + {"(*Rand).Int32N", Method, 22, ""}, + {"(*Rand).Int64", Method, 22, ""}, + {"(*Rand).Int64N", Method, 22, ""}, + {"(*Rand).IntN", Method, 22, ""}, + {"(*Rand).NormFloat64", Method, 22, ""}, + {"(*Rand).Perm", Method, 22, ""}, + {"(*Rand).Shuffle", Method, 22, ""}, + {"(*Rand).Uint", Method, 23, ""}, + {"(*Rand).Uint32", Method, 22, ""}, + {"(*Rand).Uint32N", Method, 22, ""}, + {"(*Rand).Uint64", Method, 22, ""}, + {"(*Rand).Uint64N", Method, 22, ""}, + {"(*Rand).UintN", Method, 22, ""}, + {"(*Zipf).Uint64", Method, 22, ""}, + {"ChaCha8", Type, 22, ""}, + {"ExpFloat64", Func, 22, "func() float64"}, + {"Float32", Func, 22, "func() float32"}, + {"Float64", Func, 22, "func() float64"}, + {"Int", Func, 22, "func() int"}, + {"Int32", Func, 22, "func() int32"}, + {"Int32N", Func, 22, "func(n int32) int32"}, + {"Int64", Func, 22, "func() int64"}, + {"Int64N", Func, 22, "func(n int64) int64"}, + {"IntN", Func, 22, "func(n int) int"}, + {"N", Func, 22, "func[Int intType](n Int) Int"}, + {"New", Func, 22, "func(src Source) *Rand"}, + {"NewChaCha8", Func, 22, "func(seed [32]byte) *ChaCha8"}, + {"NewPCG", Func, 22, "func(seed1 uint64, seed2 uint64) *PCG"}, + {"NewZipf", Func, 22, "func(r *Rand, s float64, v float64, imax uint64) *Zipf"}, + {"NormFloat64", Func, 22, "func() float64"}, + {"PCG", Type, 22, ""}, + {"Perm", Func, 22, "func(n int) []int"}, + {"Rand", Type, 22, ""}, + {"Shuffle", Func, 22, "func(n int, swap func(i int, j int))"}, + {"Source", Type, 22, ""}, + {"Uint", Func, 23, "func() uint"}, + {"Uint32", Func, 22, "func() uint32"}, + {"Uint32N", Func, 22, "func(n uint32) uint32"}, + {"Uint64", Func, 22, "func() uint64"}, + {"Uint64N", Func, 22, "func(n uint64) uint64"}, + {"UintN", Func, 22, "func(n uint) uint"}, + {"Zipf", Type, 22, ""}, }, "mime": { - {"(*WordDecoder).Decode", Method, 5}, - {"(*WordDecoder).DecodeHeader", Method, 5}, - {"(WordEncoder).Encode", Method, 5}, - {"AddExtensionType", Func, 0}, - {"BEncoding", Const, 5}, - {"ErrInvalidMediaParameter", Var, 9}, - {"ExtensionsByType", Func, 5}, - {"FormatMediaType", Func, 0}, - {"ParseMediaType", Func, 0}, - {"QEncoding", Const, 5}, - {"TypeByExtension", Func, 0}, - {"WordDecoder", Type, 5}, - {"WordDecoder.CharsetReader", Field, 5}, - {"WordEncoder", Type, 5}, + {"(*WordDecoder).Decode", Method, 5, ""}, + {"(*WordDecoder).DecodeHeader", Method, 5, ""}, + {"(WordEncoder).Encode", Method, 5, ""}, + {"AddExtensionType", Func, 0, "func(ext string, typ string) error"}, + {"BEncoding", Const, 5, ""}, + {"ErrInvalidMediaParameter", Var, 9, ""}, + {"ExtensionsByType", Func, 5, "func(typ string) ([]string, error)"}, + {"FormatMediaType", Func, 0, "func(t string, param map[string]string) string"}, + {"ParseMediaType", Func, 0, "func(v string) (mediatype string, params map[string]string, err error)"}, + {"QEncoding", Const, 5, ""}, + {"TypeByExtension", Func, 0, "func(ext string) string"}, + {"WordDecoder", Type, 5, ""}, + {"WordDecoder.CharsetReader", Field, 5, ""}, + {"WordEncoder", Type, 5, ""}, }, "mime/multipart": { - {"(*FileHeader).Open", Method, 0}, - {"(*Form).RemoveAll", Method, 0}, - {"(*Part).Close", Method, 0}, - {"(*Part).FileName", Method, 0}, - {"(*Part).FormName", Method, 0}, - {"(*Part).Read", Method, 0}, - {"(*Reader).NextPart", Method, 0}, - {"(*Reader).NextRawPart", Method, 14}, - {"(*Reader).ReadForm", Method, 0}, - {"(*Writer).Boundary", Method, 0}, - {"(*Writer).Close", Method, 0}, - {"(*Writer).CreateFormField", Method, 0}, - {"(*Writer).CreateFormFile", Method, 0}, - {"(*Writer).CreatePart", Method, 0}, - {"(*Writer).FormDataContentType", Method, 0}, - {"(*Writer).SetBoundary", Method, 1}, - {"(*Writer).WriteField", Method, 0}, - {"ErrMessageTooLarge", Var, 9}, - {"File", Type, 0}, - {"FileContentDisposition", Func, 25}, - {"FileHeader", Type, 0}, - {"FileHeader.Filename", Field, 0}, - {"FileHeader.Header", Field, 0}, - {"FileHeader.Size", Field, 9}, - {"Form", Type, 0}, - {"Form.File", Field, 0}, - {"Form.Value", Field, 0}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"Part", Type, 0}, - {"Part.Header", Field, 0}, - {"Reader", Type, 0}, - {"Writer", Type, 0}, + {"(*FileHeader).Open", Method, 0, ""}, + {"(*Form).RemoveAll", Method, 0, ""}, + {"(*Part).Close", Method, 0, ""}, + {"(*Part).FileName", Method, 0, ""}, + {"(*Part).FormName", Method, 0, ""}, + {"(*Part).Read", Method, 0, ""}, + {"(*Reader).NextPart", Method, 0, ""}, + {"(*Reader).NextRawPart", Method, 14, ""}, + {"(*Reader).ReadForm", Method, 0, ""}, + {"(*Writer).Boundary", Method, 0, ""}, + {"(*Writer).Close", Method, 0, ""}, + {"(*Writer).CreateFormField", Method, 0, ""}, + {"(*Writer).CreateFormFile", Method, 0, ""}, + {"(*Writer).CreatePart", Method, 0, ""}, + {"(*Writer).FormDataContentType", Method, 0, ""}, + {"(*Writer).SetBoundary", Method, 1, ""}, + {"(*Writer).WriteField", Method, 0, ""}, + {"ErrMessageTooLarge", Var, 9, ""}, + {"File", Type, 0, ""}, + {"FileContentDisposition", Func, 25, ""}, + {"FileHeader", Type, 0, ""}, + {"FileHeader.Filename", Field, 0, ""}, + {"FileHeader.Header", Field, 0, ""}, + {"FileHeader.Size", Field, 9, ""}, + {"Form", Type, 0, ""}, + {"Form.File", Field, 0, ""}, + {"Form.Value", Field, 0, ""}, + {"NewReader", Func, 0, "func(r io.Reader, boundary string) *Reader"}, + {"NewWriter", Func, 0, "func(w io.Writer) *Writer"}, + {"Part", Type, 0, ""}, + {"Part.Header", Field, 0, ""}, + {"Reader", Type, 0, ""}, + {"Writer", Type, 0, ""}, }, "mime/quotedprintable": { - {"(*Reader).Read", Method, 5}, - {"(*Writer).Close", Method, 5}, - {"(*Writer).Write", Method, 5}, - {"NewReader", Func, 5}, - {"NewWriter", Func, 5}, - {"Reader", Type, 5}, - {"Writer", Type, 5}, - {"Writer.Binary", Field, 5}, + {"(*Reader).Read", Method, 5, ""}, + {"(*Writer).Close", Method, 5, ""}, + {"(*Writer).Write", Method, 5, ""}, + {"NewReader", Func, 5, "func(r io.Reader) *Reader"}, + {"NewWriter", Func, 5, "func(w io.Writer) *Writer"}, + {"Reader", Type, 5, ""}, + {"Writer", Type, 5, ""}, + {"Writer.Binary", Field, 5, ""}, }, "net": { - {"(*AddrError).Error", Method, 0}, - {"(*AddrError).Temporary", Method, 0}, - {"(*AddrError).Timeout", Method, 0}, - {"(*Buffers).Read", Method, 8}, - {"(*Buffers).WriteTo", Method, 8}, - {"(*DNSConfigError).Error", Method, 0}, - {"(*DNSConfigError).Temporary", Method, 0}, - {"(*DNSConfigError).Timeout", Method, 0}, - {"(*DNSConfigError).Unwrap", Method, 13}, - {"(*DNSError).Error", Method, 0}, - {"(*DNSError).Temporary", Method, 0}, - {"(*DNSError).Timeout", Method, 0}, - {"(*DNSError).Unwrap", Method, 23}, - {"(*Dialer).Dial", Method, 1}, - {"(*Dialer).DialContext", Method, 7}, - {"(*Dialer).MultipathTCP", Method, 21}, - {"(*Dialer).SetMultipathTCP", Method, 21}, - {"(*IP).UnmarshalText", Method, 2}, - {"(*IPAddr).Network", Method, 0}, - {"(*IPAddr).String", Method, 0}, - {"(*IPConn).Close", Method, 0}, - {"(*IPConn).File", Method, 0}, - {"(*IPConn).LocalAddr", Method, 0}, - {"(*IPConn).Read", Method, 0}, - {"(*IPConn).ReadFrom", Method, 0}, - {"(*IPConn).ReadFromIP", Method, 0}, - {"(*IPConn).ReadMsgIP", Method, 1}, - {"(*IPConn).RemoteAddr", Method, 0}, - {"(*IPConn).SetDeadline", Method, 0}, - {"(*IPConn).SetReadBuffer", Method, 0}, - {"(*IPConn).SetReadDeadline", Method, 0}, - {"(*IPConn).SetWriteBuffer", Method, 0}, - {"(*IPConn).SetWriteDeadline", Method, 0}, - {"(*IPConn).SyscallConn", Method, 9}, - {"(*IPConn).Write", Method, 0}, - {"(*IPConn).WriteMsgIP", Method, 1}, - {"(*IPConn).WriteTo", Method, 0}, - {"(*IPConn).WriteToIP", Method, 0}, - {"(*IPNet).Contains", Method, 0}, - {"(*IPNet).Network", Method, 0}, - {"(*IPNet).String", Method, 0}, - {"(*Interface).Addrs", Method, 0}, - {"(*Interface).MulticastAddrs", Method, 0}, - {"(*ListenConfig).Listen", Method, 11}, - {"(*ListenConfig).ListenPacket", Method, 11}, - {"(*ListenConfig).MultipathTCP", Method, 21}, - {"(*ListenConfig).SetMultipathTCP", Method, 21}, - {"(*OpError).Error", Method, 0}, - {"(*OpError).Temporary", Method, 0}, - {"(*OpError).Timeout", Method, 0}, - {"(*OpError).Unwrap", Method, 13}, - {"(*ParseError).Error", Method, 0}, - {"(*ParseError).Temporary", Method, 17}, - {"(*ParseError).Timeout", Method, 17}, - {"(*Resolver).LookupAddr", Method, 8}, - {"(*Resolver).LookupCNAME", Method, 8}, - {"(*Resolver).LookupHost", Method, 8}, - {"(*Resolver).LookupIP", Method, 15}, - {"(*Resolver).LookupIPAddr", Method, 8}, - {"(*Resolver).LookupMX", Method, 8}, - {"(*Resolver).LookupNS", Method, 8}, - {"(*Resolver).LookupNetIP", Method, 18}, - {"(*Resolver).LookupPort", Method, 8}, - {"(*Resolver).LookupSRV", Method, 8}, - {"(*Resolver).LookupTXT", Method, 8}, - {"(*TCPAddr).AddrPort", Method, 18}, - {"(*TCPAddr).Network", Method, 0}, - {"(*TCPAddr).String", Method, 0}, - {"(*TCPConn).Close", Method, 0}, - {"(*TCPConn).CloseRead", Method, 0}, - {"(*TCPConn).CloseWrite", Method, 0}, - {"(*TCPConn).File", Method, 0}, - {"(*TCPConn).LocalAddr", Method, 0}, - {"(*TCPConn).MultipathTCP", Method, 21}, - {"(*TCPConn).Read", Method, 0}, - {"(*TCPConn).ReadFrom", Method, 0}, - {"(*TCPConn).RemoteAddr", Method, 0}, - {"(*TCPConn).SetDeadline", Method, 0}, - {"(*TCPConn).SetKeepAlive", Method, 0}, - {"(*TCPConn).SetKeepAliveConfig", Method, 23}, - {"(*TCPConn).SetKeepAlivePeriod", Method, 2}, - {"(*TCPConn).SetLinger", Method, 0}, - {"(*TCPConn).SetNoDelay", Method, 0}, - {"(*TCPConn).SetReadBuffer", Method, 0}, - {"(*TCPConn).SetReadDeadline", Method, 0}, - {"(*TCPConn).SetWriteBuffer", Method, 0}, - {"(*TCPConn).SetWriteDeadline", Method, 0}, - {"(*TCPConn).SyscallConn", Method, 9}, - {"(*TCPConn).Write", Method, 0}, - {"(*TCPConn).WriteTo", Method, 22}, - {"(*TCPListener).Accept", Method, 0}, - {"(*TCPListener).AcceptTCP", Method, 0}, - {"(*TCPListener).Addr", Method, 0}, - {"(*TCPListener).Close", Method, 0}, - {"(*TCPListener).File", Method, 0}, - {"(*TCPListener).SetDeadline", Method, 0}, - {"(*TCPListener).SyscallConn", Method, 10}, - {"(*UDPAddr).AddrPort", Method, 18}, - {"(*UDPAddr).Network", Method, 0}, - {"(*UDPAddr).String", Method, 0}, - {"(*UDPConn).Close", Method, 0}, - {"(*UDPConn).File", Method, 0}, - {"(*UDPConn).LocalAddr", Method, 0}, - {"(*UDPConn).Read", Method, 0}, - {"(*UDPConn).ReadFrom", Method, 0}, - {"(*UDPConn).ReadFromUDP", Method, 0}, - {"(*UDPConn).ReadFromUDPAddrPort", Method, 18}, - {"(*UDPConn).ReadMsgUDP", Method, 1}, - {"(*UDPConn).ReadMsgUDPAddrPort", Method, 18}, - {"(*UDPConn).RemoteAddr", Method, 0}, - {"(*UDPConn).SetDeadline", Method, 0}, - {"(*UDPConn).SetReadBuffer", Method, 0}, - {"(*UDPConn).SetReadDeadline", Method, 0}, - {"(*UDPConn).SetWriteBuffer", Method, 0}, - {"(*UDPConn).SetWriteDeadline", Method, 0}, - {"(*UDPConn).SyscallConn", Method, 9}, - {"(*UDPConn).Write", Method, 0}, - {"(*UDPConn).WriteMsgUDP", Method, 1}, - {"(*UDPConn).WriteMsgUDPAddrPort", Method, 18}, - {"(*UDPConn).WriteTo", Method, 0}, - {"(*UDPConn).WriteToUDP", Method, 0}, - {"(*UDPConn).WriteToUDPAddrPort", Method, 18}, - {"(*UnixAddr).Network", Method, 0}, - {"(*UnixAddr).String", Method, 0}, - {"(*UnixConn).Close", Method, 0}, - {"(*UnixConn).CloseRead", Method, 1}, - {"(*UnixConn).CloseWrite", Method, 1}, - {"(*UnixConn).File", Method, 0}, - {"(*UnixConn).LocalAddr", Method, 0}, - {"(*UnixConn).Read", Method, 0}, - {"(*UnixConn).ReadFrom", Method, 0}, - {"(*UnixConn).ReadFromUnix", Method, 0}, - {"(*UnixConn).ReadMsgUnix", Method, 0}, - {"(*UnixConn).RemoteAddr", Method, 0}, - {"(*UnixConn).SetDeadline", Method, 0}, - {"(*UnixConn).SetReadBuffer", Method, 0}, - {"(*UnixConn).SetReadDeadline", Method, 0}, - {"(*UnixConn).SetWriteBuffer", Method, 0}, - {"(*UnixConn).SetWriteDeadline", Method, 0}, - {"(*UnixConn).SyscallConn", Method, 9}, - {"(*UnixConn).Write", Method, 0}, - {"(*UnixConn).WriteMsgUnix", Method, 0}, - {"(*UnixConn).WriteTo", Method, 0}, - {"(*UnixConn).WriteToUnix", Method, 0}, - {"(*UnixListener).Accept", Method, 0}, - {"(*UnixListener).AcceptUnix", Method, 0}, - {"(*UnixListener).Addr", Method, 0}, - {"(*UnixListener).Close", Method, 0}, - {"(*UnixListener).File", Method, 0}, - {"(*UnixListener).SetDeadline", Method, 0}, - {"(*UnixListener).SetUnlinkOnClose", Method, 8}, - {"(*UnixListener).SyscallConn", Method, 10}, - {"(Flags).String", Method, 0}, - {"(HardwareAddr).String", Method, 0}, - {"(IP).AppendText", Method, 24}, - {"(IP).DefaultMask", Method, 0}, - {"(IP).Equal", Method, 0}, - {"(IP).IsGlobalUnicast", Method, 0}, - {"(IP).IsInterfaceLocalMulticast", Method, 0}, - {"(IP).IsLinkLocalMulticast", Method, 0}, - {"(IP).IsLinkLocalUnicast", Method, 0}, - {"(IP).IsLoopback", Method, 0}, - {"(IP).IsMulticast", Method, 0}, - {"(IP).IsPrivate", Method, 17}, - {"(IP).IsUnspecified", Method, 0}, - {"(IP).MarshalText", Method, 2}, - {"(IP).Mask", Method, 0}, - {"(IP).String", Method, 0}, - {"(IP).To16", Method, 0}, - {"(IP).To4", Method, 0}, - {"(IPMask).Size", Method, 0}, - {"(IPMask).String", Method, 0}, - {"(InvalidAddrError).Error", Method, 0}, - {"(InvalidAddrError).Temporary", Method, 0}, - {"(InvalidAddrError).Timeout", Method, 0}, - {"(UnknownNetworkError).Error", Method, 0}, - {"(UnknownNetworkError).Temporary", Method, 0}, - {"(UnknownNetworkError).Timeout", Method, 0}, - {"Addr", Type, 0}, - {"AddrError", Type, 0}, - {"AddrError.Addr", Field, 0}, - {"AddrError.Err", Field, 0}, - {"Buffers", Type, 8}, - {"CIDRMask", Func, 0}, - {"Conn", Type, 0}, - {"DNSConfigError", Type, 0}, - {"DNSConfigError.Err", Field, 0}, - {"DNSError", Type, 0}, - {"DNSError.Err", Field, 0}, - {"DNSError.IsNotFound", Field, 13}, - {"DNSError.IsTemporary", Field, 6}, - {"DNSError.IsTimeout", Field, 0}, - {"DNSError.Name", Field, 0}, - {"DNSError.Server", Field, 0}, - {"DNSError.UnwrapErr", Field, 23}, - {"DefaultResolver", Var, 8}, - {"Dial", Func, 0}, - {"DialIP", Func, 0}, - {"DialTCP", Func, 0}, - {"DialTimeout", Func, 0}, - {"DialUDP", Func, 0}, - {"DialUnix", Func, 0}, - {"Dialer", Type, 1}, - {"Dialer.Cancel", Field, 6}, - {"Dialer.Control", Field, 11}, - {"Dialer.ControlContext", Field, 20}, - {"Dialer.Deadline", Field, 1}, - {"Dialer.DualStack", Field, 2}, - {"Dialer.FallbackDelay", Field, 5}, - {"Dialer.KeepAlive", Field, 3}, - {"Dialer.KeepAliveConfig", Field, 23}, - {"Dialer.LocalAddr", Field, 1}, - {"Dialer.Resolver", Field, 8}, - {"Dialer.Timeout", Field, 1}, - {"ErrClosed", Var, 16}, - {"ErrWriteToConnected", Var, 0}, - {"Error", Type, 0}, - {"FileConn", Func, 0}, - {"FileListener", Func, 0}, - {"FilePacketConn", Func, 0}, - {"FlagBroadcast", Const, 0}, - {"FlagLoopback", Const, 0}, - {"FlagMulticast", Const, 0}, - {"FlagPointToPoint", Const, 0}, - {"FlagRunning", Const, 20}, - {"FlagUp", Const, 0}, - {"Flags", Type, 0}, - {"HardwareAddr", Type, 0}, - {"IP", Type, 0}, - {"IPAddr", Type, 0}, - {"IPAddr.IP", Field, 0}, - {"IPAddr.Zone", Field, 1}, - {"IPConn", Type, 0}, - {"IPMask", Type, 0}, - {"IPNet", Type, 0}, - {"IPNet.IP", Field, 0}, - {"IPNet.Mask", Field, 0}, - {"IPv4", Func, 0}, - {"IPv4Mask", Func, 0}, - {"IPv4allrouter", Var, 0}, - {"IPv4allsys", Var, 0}, - {"IPv4bcast", Var, 0}, - {"IPv4len", Const, 0}, - {"IPv4zero", Var, 0}, - {"IPv6interfacelocalallnodes", Var, 0}, - {"IPv6len", Const, 0}, - {"IPv6linklocalallnodes", Var, 0}, - {"IPv6linklocalallrouters", Var, 0}, - {"IPv6loopback", Var, 0}, - {"IPv6unspecified", Var, 0}, - {"IPv6zero", Var, 0}, - {"Interface", Type, 0}, - {"Interface.Flags", Field, 0}, - {"Interface.HardwareAddr", Field, 0}, - {"Interface.Index", Field, 0}, - {"Interface.MTU", Field, 0}, - {"Interface.Name", Field, 0}, - {"InterfaceAddrs", Func, 0}, - {"InterfaceByIndex", Func, 0}, - {"InterfaceByName", Func, 0}, - {"Interfaces", Func, 0}, - {"InvalidAddrError", Type, 0}, - {"JoinHostPort", Func, 0}, - {"KeepAliveConfig", Type, 23}, - {"KeepAliveConfig.Count", Field, 23}, - {"KeepAliveConfig.Enable", Field, 23}, - {"KeepAliveConfig.Idle", Field, 23}, - {"KeepAliveConfig.Interval", Field, 23}, - {"Listen", Func, 0}, - {"ListenConfig", Type, 11}, - {"ListenConfig.Control", Field, 11}, - {"ListenConfig.KeepAlive", Field, 13}, - {"ListenConfig.KeepAliveConfig", Field, 23}, - {"ListenIP", Func, 0}, - {"ListenMulticastUDP", Func, 0}, - {"ListenPacket", Func, 0}, - {"ListenTCP", Func, 0}, - {"ListenUDP", Func, 0}, - {"ListenUnix", Func, 0}, - {"ListenUnixgram", Func, 0}, - {"Listener", Type, 0}, - {"LookupAddr", Func, 0}, - {"LookupCNAME", Func, 0}, - {"LookupHost", Func, 0}, - {"LookupIP", Func, 0}, - {"LookupMX", Func, 0}, - {"LookupNS", Func, 1}, - {"LookupPort", Func, 0}, - {"LookupSRV", Func, 0}, - {"LookupTXT", Func, 0}, - {"MX", Type, 0}, - {"MX.Host", Field, 0}, - {"MX.Pref", Field, 0}, - {"NS", Type, 1}, - {"NS.Host", Field, 1}, - {"OpError", Type, 0}, - {"OpError.Addr", Field, 0}, - {"OpError.Err", Field, 0}, - {"OpError.Net", Field, 0}, - {"OpError.Op", Field, 0}, - {"OpError.Source", Field, 5}, - {"PacketConn", Type, 0}, - {"ParseCIDR", Func, 0}, - {"ParseError", Type, 0}, - {"ParseError.Text", Field, 0}, - {"ParseError.Type", Field, 0}, - {"ParseIP", Func, 0}, - {"ParseMAC", Func, 0}, - {"Pipe", Func, 0}, - {"ResolveIPAddr", Func, 0}, - {"ResolveTCPAddr", Func, 0}, - {"ResolveUDPAddr", Func, 0}, - {"ResolveUnixAddr", Func, 0}, - {"Resolver", Type, 8}, - {"Resolver.Dial", Field, 9}, - {"Resolver.PreferGo", Field, 8}, - {"Resolver.StrictErrors", Field, 9}, - {"SRV", Type, 0}, - {"SRV.Port", Field, 0}, - {"SRV.Priority", Field, 0}, - {"SRV.Target", Field, 0}, - {"SRV.Weight", Field, 0}, - {"SplitHostPort", Func, 0}, - {"TCPAddr", Type, 0}, - {"TCPAddr.IP", Field, 0}, - {"TCPAddr.Port", Field, 0}, - {"TCPAddr.Zone", Field, 1}, - {"TCPAddrFromAddrPort", Func, 18}, - {"TCPConn", Type, 0}, - {"TCPListener", Type, 0}, - {"UDPAddr", Type, 0}, - {"UDPAddr.IP", Field, 0}, - {"UDPAddr.Port", Field, 0}, - {"UDPAddr.Zone", Field, 1}, - {"UDPAddrFromAddrPort", Func, 18}, - {"UDPConn", Type, 0}, - {"UnixAddr", Type, 0}, - {"UnixAddr.Name", Field, 0}, - {"UnixAddr.Net", Field, 0}, - {"UnixConn", Type, 0}, - {"UnixListener", Type, 0}, - {"UnknownNetworkError", Type, 0}, + {"(*AddrError).Error", Method, 0, ""}, + {"(*AddrError).Temporary", Method, 0, ""}, + {"(*AddrError).Timeout", Method, 0, ""}, + {"(*Buffers).Read", Method, 8, ""}, + {"(*Buffers).WriteTo", Method, 8, ""}, + {"(*DNSConfigError).Error", Method, 0, ""}, + {"(*DNSConfigError).Temporary", Method, 0, ""}, + {"(*DNSConfigError).Timeout", Method, 0, ""}, + {"(*DNSConfigError).Unwrap", Method, 13, ""}, + {"(*DNSError).Error", Method, 0, ""}, + {"(*DNSError).Temporary", Method, 0, ""}, + {"(*DNSError).Timeout", Method, 0, ""}, + {"(*DNSError).Unwrap", Method, 23, ""}, + {"(*Dialer).Dial", Method, 1, ""}, + {"(*Dialer).DialContext", Method, 7, ""}, + {"(*Dialer).MultipathTCP", Method, 21, ""}, + {"(*Dialer).SetMultipathTCP", Method, 21, ""}, + {"(*IP).UnmarshalText", Method, 2, ""}, + {"(*IPAddr).Network", Method, 0, ""}, + {"(*IPAddr).String", Method, 0, ""}, + {"(*IPConn).Close", Method, 0, ""}, + {"(*IPConn).File", Method, 0, ""}, + {"(*IPConn).LocalAddr", Method, 0, ""}, + {"(*IPConn).Read", Method, 0, ""}, + {"(*IPConn).ReadFrom", Method, 0, ""}, + {"(*IPConn).ReadFromIP", Method, 0, ""}, + {"(*IPConn).ReadMsgIP", Method, 1, ""}, + {"(*IPConn).RemoteAddr", Method, 0, ""}, + {"(*IPConn).SetDeadline", Method, 0, ""}, + {"(*IPConn).SetReadBuffer", Method, 0, ""}, + {"(*IPConn).SetReadDeadline", Method, 0, ""}, + {"(*IPConn).SetWriteBuffer", Method, 0, ""}, + {"(*IPConn).SetWriteDeadline", Method, 0, ""}, + {"(*IPConn).SyscallConn", Method, 9, ""}, + {"(*IPConn).Write", Method, 0, ""}, + {"(*IPConn).WriteMsgIP", Method, 1, ""}, + {"(*IPConn).WriteTo", Method, 0, ""}, + {"(*IPConn).WriteToIP", Method, 0, ""}, + {"(*IPNet).Contains", Method, 0, ""}, + {"(*IPNet).Network", Method, 0, ""}, + {"(*IPNet).String", Method, 0, ""}, + {"(*Interface).Addrs", Method, 0, ""}, + {"(*Interface).MulticastAddrs", Method, 0, ""}, + {"(*ListenConfig).Listen", Method, 11, ""}, + {"(*ListenConfig).ListenPacket", Method, 11, ""}, + {"(*ListenConfig).MultipathTCP", Method, 21, ""}, + {"(*ListenConfig).SetMultipathTCP", Method, 21, ""}, + {"(*OpError).Error", Method, 0, ""}, + {"(*OpError).Temporary", Method, 0, ""}, + {"(*OpError).Timeout", Method, 0, ""}, + {"(*OpError).Unwrap", Method, 13, ""}, + {"(*ParseError).Error", Method, 0, ""}, + {"(*ParseError).Temporary", Method, 17, ""}, + {"(*ParseError).Timeout", Method, 17, ""}, + {"(*Resolver).LookupAddr", Method, 8, ""}, + {"(*Resolver).LookupCNAME", Method, 8, ""}, + {"(*Resolver).LookupHost", Method, 8, ""}, + {"(*Resolver).LookupIP", Method, 15, ""}, + {"(*Resolver).LookupIPAddr", Method, 8, ""}, + {"(*Resolver).LookupMX", Method, 8, ""}, + {"(*Resolver).LookupNS", Method, 8, ""}, + {"(*Resolver).LookupNetIP", Method, 18, ""}, + {"(*Resolver).LookupPort", Method, 8, ""}, + {"(*Resolver).LookupSRV", Method, 8, ""}, + {"(*Resolver).LookupTXT", Method, 8, ""}, + {"(*TCPAddr).AddrPort", Method, 18, ""}, + {"(*TCPAddr).Network", Method, 0, ""}, + {"(*TCPAddr).String", Method, 0, ""}, + {"(*TCPConn).Close", Method, 0, ""}, + {"(*TCPConn).CloseRead", Method, 0, ""}, + {"(*TCPConn).CloseWrite", Method, 0, ""}, + {"(*TCPConn).File", Method, 0, ""}, + {"(*TCPConn).LocalAddr", Method, 0, ""}, + {"(*TCPConn).MultipathTCP", Method, 21, ""}, + {"(*TCPConn).Read", Method, 0, ""}, + {"(*TCPConn).ReadFrom", Method, 0, ""}, + {"(*TCPConn).RemoteAddr", Method, 0, ""}, + {"(*TCPConn).SetDeadline", Method, 0, ""}, + {"(*TCPConn).SetKeepAlive", Method, 0, ""}, + {"(*TCPConn).SetKeepAliveConfig", Method, 23, ""}, + {"(*TCPConn).SetKeepAlivePeriod", Method, 2, ""}, + {"(*TCPConn).SetLinger", Method, 0, ""}, + {"(*TCPConn).SetNoDelay", Method, 0, ""}, + {"(*TCPConn).SetReadBuffer", Method, 0, ""}, + {"(*TCPConn).SetReadDeadline", Method, 0, ""}, + {"(*TCPConn).SetWriteBuffer", Method, 0, ""}, + {"(*TCPConn).SetWriteDeadline", Method, 0, ""}, + {"(*TCPConn).SyscallConn", Method, 9, ""}, + {"(*TCPConn).Write", Method, 0, ""}, + {"(*TCPConn).WriteTo", Method, 22, ""}, + {"(*TCPListener).Accept", Method, 0, ""}, + {"(*TCPListener).AcceptTCP", Method, 0, ""}, + {"(*TCPListener).Addr", Method, 0, ""}, + {"(*TCPListener).Close", Method, 0, ""}, + {"(*TCPListener).File", Method, 0, ""}, + {"(*TCPListener).SetDeadline", Method, 0, ""}, + {"(*TCPListener).SyscallConn", Method, 10, ""}, + {"(*UDPAddr).AddrPort", Method, 18, ""}, + {"(*UDPAddr).Network", Method, 0, ""}, + {"(*UDPAddr).String", Method, 0, ""}, + {"(*UDPConn).Close", Method, 0, ""}, + {"(*UDPConn).File", Method, 0, ""}, + {"(*UDPConn).LocalAddr", Method, 0, ""}, + {"(*UDPConn).Read", Method, 0, ""}, + {"(*UDPConn).ReadFrom", Method, 0, ""}, + {"(*UDPConn).ReadFromUDP", Method, 0, ""}, + {"(*UDPConn).ReadFromUDPAddrPort", Method, 18, ""}, + {"(*UDPConn).ReadMsgUDP", Method, 1, ""}, + {"(*UDPConn).ReadMsgUDPAddrPort", Method, 18, ""}, + {"(*UDPConn).RemoteAddr", Method, 0, ""}, + {"(*UDPConn).SetDeadline", Method, 0, ""}, + {"(*UDPConn).SetReadBuffer", Method, 0, ""}, + {"(*UDPConn).SetReadDeadline", Method, 0, ""}, + {"(*UDPConn).SetWriteBuffer", Method, 0, ""}, + {"(*UDPConn).SetWriteDeadline", Method, 0, ""}, + {"(*UDPConn).SyscallConn", Method, 9, ""}, + {"(*UDPConn).Write", Method, 0, ""}, + {"(*UDPConn).WriteMsgUDP", Method, 1, ""}, + {"(*UDPConn).WriteMsgUDPAddrPort", Method, 18, ""}, + {"(*UDPConn).WriteTo", Method, 0, ""}, + {"(*UDPConn).WriteToUDP", Method, 0, ""}, + {"(*UDPConn).WriteToUDPAddrPort", Method, 18, ""}, + {"(*UnixAddr).Network", Method, 0, ""}, + {"(*UnixAddr).String", Method, 0, ""}, + {"(*UnixConn).Close", Method, 0, ""}, + {"(*UnixConn).CloseRead", Method, 1, ""}, + {"(*UnixConn).CloseWrite", Method, 1, ""}, + {"(*UnixConn).File", Method, 0, ""}, + {"(*UnixConn).LocalAddr", Method, 0, ""}, + {"(*UnixConn).Read", Method, 0, ""}, + {"(*UnixConn).ReadFrom", Method, 0, ""}, + {"(*UnixConn).ReadFromUnix", Method, 0, ""}, + {"(*UnixConn).ReadMsgUnix", Method, 0, ""}, + {"(*UnixConn).RemoteAddr", Method, 0, ""}, + {"(*UnixConn).SetDeadline", Method, 0, ""}, + {"(*UnixConn).SetReadBuffer", Method, 0, ""}, + {"(*UnixConn).SetReadDeadline", Method, 0, ""}, + {"(*UnixConn).SetWriteBuffer", Method, 0, ""}, + {"(*UnixConn).SetWriteDeadline", Method, 0, ""}, + {"(*UnixConn).SyscallConn", Method, 9, ""}, + {"(*UnixConn).Write", Method, 0, ""}, + {"(*UnixConn).WriteMsgUnix", Method, 0, ""}, + {"(*UnixConn).WriteTo", Method, 0, ""}, + {"(*UnixConn).WriteToUnix", Method, 0, ""}, + {"(*UnixListener).Accept", Method, 0, ""}, + {"(*UnixListener).AcceptUnix", Method, 0, ""}, + {"(*UnixListener).Addr", Method, 0, ""}, + {"(*UnixListener).Close", Method, 0, ""}, + {"(*UnixListener).File", Method, 0, ""}, + {"(*UnixListener).SetDeadline", Method, 0, ""}, + {"(*UnixListener).SetUnlinkOnClose", Method, 8, ""}, + {"(*UnixListener).SyscallConn", Method, 10, ""}, + {"(Flags).String", Method, 0, ""}, + {"(HardwareAddr).String", Method, 0, ""}, + {"(IP).AppendText", Method, 24, ""}, + {"(IP).DefaultMask", Method, 0, ""}, + {"(IP).Equal", Method, 0, ""}, + {"(IP).IsGlobalUnicast", Method, 0, ""}, + {"(IP).IsInterfaceLocalMulticast", Method, 0, ""}, + {"(IP).IsLinkLocalMulticast", Method, 0, ""}, + {"(IP).IsLinkLocalUnicast", Method, 0, ""}, + {"(IP).IsLoopback", Method, 0, ""}, + {"(IP).IsMulticast", Method, 0, ""}, + {"(IP).IsPrivate", Method, 17, ""}, + {"(IP).IsUnspecified", Method, 0, ""}, + {"(IP).MarshalText", Method, 2, ""}, + {"(IP).Mask", Method, 0, ""}, + {"(IP).String", Method, 0, ""}, + {"(IP).To16", Method, 0, ""}, + {"(IP).To4", Method, 0, ""}, + {"(IPMask).Size", Method, 0, ""}, + {"(IPMask).String", Method, 0, ""}, + {"(InvalidAddrError).Error", Method, 0, ""}, + {"(InvalidAddrError).Temporary", Method, 0, ""}, + {"(InvalidAddrError).Timeout", Method, 0, ""}, + {"(UnknownNetworkError).Error", Method, 0, ""}, + {"(UnknownNetworkError).Temporary", Method, 0, ""}, + {"(UnknownNetworkError).Timeout", Method, 0, ""}, + {"Addr", Type, 0, ""}, + {"AddrError", Type, 0, ""}, + {"AddrError.Addr", Field, 0, ""}, + {"AddrError.Err", Field, 0, ""}, + {"Buffers", Type, 8, ""}, + {"CIDRMask", Func, 0, "func(ones int, bits int) IPMask"}, + {"Conn", Type, 0, ""}, + {"DNSConfigError", Type, 0, ""}, + {"DNSConfigError.Err", Field, 0, ""}, + {"DNSError", Type, 0, ""}, + {"DNSError.Err", Field, 0, ""}, + {"DNSError.IsNotFound", Field, 13, ""}, + {"DNSError.IsTemporary", Field, 6, ""}, + {"DNSError.IsTimeout", Field, 0, ""}, + {"DNSError.Name", Field, 0, ""}, + {"DNSError.Server", Field, 0, ""}, + {"DNSError.UnwrapErr", Field, 23, ""}, + {"DefaultResolver", Var, 8, ""}, + {"Dial", Func, 0, "func(network string, address string) (Conn, error)"}, + {"DialIP", Func, 0, "func(network string, laddr *IPAddr, raddr *IPAddr) (*IPConn, error)"}, + {"DialTCP", Func, 0, "func(network string, laddr *TCPAddr, raddr *TCPAddr) (*TCPConn, error)"}, + {"DialTimeout", Func, 0, "func(network string, address string, timeout time.Duration) (Conn, error)"}, + {"DialUDP", Func, 0, "func(network string, laddr *UDPAddr, raddr *UDPAddr) (*UDPConn, error)"}, + {"DialUnix", Func, 0, "func(network string, laddr *UnixAddr, raddr *UnixAddr) (*UnixConn, error)"}, + {"Dialer", Type, 1, ""}, + {"Dialer.Cancel", Field, 6, ""}, + {"Dialer.Control", Field, 11, ""}, + {"Dialer.ControlContext", Field, 20, ""}, + {"Dialer.Deadline", Field, 1, ""}, + {"Dialer.DualStack", Field, 2, ""}, + {"Dialer.FallbackDelay", Field, 5, ""}, + {"Dialer.KeepAlive", Field, 3, ""}, + {"Dialer.KeepAliveConfig", Field, 23, ""}, + {"Dialer.LocalAddr", Field, 1, ""}, + {"Dialer.Resolver", Field, 8, ""}, + {"Dialer.Timeout", Field, 1, ""}, + {"ErrClosed", Var, 16, ""}, + {"ErrWriteToConnected", Var, 0, ""}, + {"Error", Type, 0, ""}, + {"FileConn", Func, 0, "func(f *os.File) (c Conn, err error)"}, + {"FileListener", Func, 0, "func(f *os.File) (ln Listener, err error)"}, + {"FilePacketConn", Func, 0, "func(f *os.File) (c PacketConn, err error)"}, + {"FlagBroadcast", Const, 0, ""}, + {"FlagLoopback", Const, 0, ""}, + {"FlagMulticast", Const, 0, ""}, + {"FlagPointToPoint", Const, 0, ""}, + {"FlagRunning", Const, 20, ""}, + {"FlagUp", Const, 0, ""}, + {"Flags", Type, 0, ""}, + {"HardwareAddr", Type, 0, ""}, + {"IP", Type, 0, ""}, + {"IPAddr", Type, 0, ""}, + {"IPAddr.IP", Field, 0, ""}, + {"IPAddr.Zone", Field, 1, ""}, + {"IPConn", Type, 0, ""}, + {"IPMask", Type, 0, ""}, + {"IPNet", Type, 0, ""}, + {"IPNet.IP", Field, 0, ""}, + {"IPNet.Mask", Field, 0, ""}, + {"IPv4", Func, 0, "func(a byte, b byte, c byte, d byte) IP"}, + {"IPv4Mask", Func, 0, "func(a byte, b byte, c byte, d byte) IPMask"}, + {"IPv4allrouter", Var, 0, ""}, + {"IPv4allsys", Var, 0, ""}, + {"IPv4bcast", Var, 0, ""}, + {"IPv4len", Const, 0, ""}, + {"IPv4zero", Var, 0, ""}, + {"IPv6interfacelocalallnodes", Var, 0, ""}, + {"IPv6len", Const, 0, ""}, + {"IPv6linklocalallnodes", Var, 0, ""}, + {"IPv6linklocalallrouters", Var, 0, ""}, + {"IPv6loopback", Var, 0, ""}, + {"IPv6unspecified", Var, 0, ""}, + {"IPv6zero", Var, 0, ""}, + {"Interface", Type, 0, ""}, + {"Interface.Flags", Field, 0, ""}, + {"Interface.HardwareAddr", Field, 0, ""}, + {"Interface.Index", Field, 0, ""}, + {"Interface.MTU", Field, 0, ""}, + {"Interface.Name", Field, 0, ""}, + {"InterfaceAddrs", Func, 0, "func() ([]Addr, error)"}, + {"InterfaceByIndex", Func, 0, "func(index int) (*Interface, error)"}, + {"InterfaceByName", Func, 0, "func(name string) (*Interface, error)"}, + {"Interfaces", Func, 0, "func() ([]Interface, error)"}, + {"InvalidAddrError", Type, 0, ""}, + {"JoinHostPort", Func, 0, "func(host string, port string) string"}, + {"KeepAliveConfig", Type, 23, ""}, + {"KeepAliveConfig.Count", Field, 23, ""}, + {"KeepAliveConfig.Enable", Field, 23, ""}, + {"KeepAliveConfig.Idle", Field, 23, ""}, + {"KeepAliveConfig.Interval", Field, 23, ""}, + {"Listen", Func, 0, "func(network string, address string) (Listener, error)"}, + {"ListenConfig", Type, 11, ""}, + {"ListenConfig.Control", Field, 11, ""}, + {"ListenConfig.KeepAlive", Field, 13, ""}, + {"ListenConfig.KeepAliveConfig", Field, 23, ""}, + {"ListenIP", Func, 0, "func(network string, laddr *IPAddr) (*IPConn, error)"}, + {"ListenMulticastUDP", Func, 0, "func(network string, ifi *Interface, gaddr *UDPAddr) (*UDPConn, error)"}, + {"ListenPacket", Func, 0, "func(network string, address string) (PacketConn, error)"}, + {"ListenTCP", Func, 0, "func(network string, laddr *TCPAddr) (*TCPListener, error)"}, + {"ListenUDP", Func, 0, "func(network string, laddr *UDPAddr) (*UDPConn, error)"}, + {"ListenUnix", Func, 0, "func(network string, laddr *UnixAddr) (*UnixListener, error)"}, + {"ListenUnixgram", Func, 0, "func(network string, laddr *UnixAddr) (*UnixConn, error)"}, + {"Listener", Type, 0, ""}, + {"LookupAddr", Func, 0, "func(addr string) (names []string, err error)"}, + {"LookupCNAME", Func, 0, "func(host string) (cname string, err error)"}, + {"LookupHost", Func, 0, "func(host string) (addrs []string, err error)"}, + {"LookupIP", Func, 0, "func(host string) ([]IP, error)"}, + {"LookupMX", Func, 0, "func(name string) ([]*MX, error)"}, + {"LookupNS", Func, 1, "func(name string) ([]*NS, error)"}, + {"LookupPort", Func, 0, "func(network string, service string) (port int, err error)"}, + {"LookupSRV", Func, 0, "func(service string, proto string, name string) (cname string, addrs []*SRV, err error)"}, + {"LookupTXT", Func, 0, "func(name string) ([]string, error)"}, + {"MX", Type, 0, ""}, + {"MX.Host", Field, 0, ""}, + {"MX.Pref", Field, 0, ""}, + {"NS", Type, 1, ""}, + {"NS.Host", Field, 1, ""}, + {"OpError", Type, 0, ""}, + {"OpError.Addr", Field, 0, ""}, + {"OpError.Err", Field, 0, ""}, + {"OpError.Net", Field, 0, ""}, + {"OpError.Op", Field, 0, ""}, + {"OpError.Source", Field, 5, ""}, + {"PacketConn", Type, 0, ""}, + {"ParseCIDR", Func, 0, "func(s string) (IP, *IPNet, error)"}, + {"ParseError", Type, 0, ""}, + {"ParseError.Text", Field, 0, ""}, + {"ParseError.Type", Field, 0, ""}, + {"ParseIP", Func, 0, "func(s string) IP"}, + {"ParseMAC", Func, 0, "func(s string) (hw HardwareAddr, err error)"}, + {"Pipe", Func, 0, "func() (Conn, Conn)"}, + {"ResolveIPAddr", Func, 0, "func(network string, address string) (*IPAddr, error)"}, + {"ResolveTCPAddr", Func, 0, "func(network string, address string) (*TCPAddr, error)"}, + {"ResolveUDPAddr", Func, 0, "func(network string, address string) (*UDPAddr, error)"}, + {"ResolveUnixAddr", Func, 0, "func(network string, address string) (*UnixAddr, error)"}, + {"Resolver", Type, 8, ""}, + {"Resolver.Dial", Field, 9, ""}, + {"Resolver.PreferGo", Field, 8, ""}, + {"Resolver.StrictErrors", Field, 9, ""}, + {"SRV", Type, 0, ""}, + {"SRV.Port", Field, 0, ""}, + {"SRV.Priority", Field, 0, ""}, + {"SRV.Target", Field, 0, ""}, + {"SRV.Weight", Field, 0, ""}, + {"SplitHostPort", Func, 0, "func(hostport string) (host string, port string, err error)"}, + {"TCPAddr", Type, 0, ""}, + {"TCPAddr.IP", Field, 0, ""}, + {"TCPAddr.Port", Field, 0, ""}, + {"TCPAddr.Zone", Field, 1, ""}, + {"TCPAddrFromAddrPort", Func, 18, "func(addr netip.AddrPort) *TCPAddr"}, + {"TCPConn", Type, 0, ""}, + {"TCPListener", Type, 0, ""}, + {"UDPAddr", Type, 0, ""}, + {"UDPAddr.IP", Field, 0, ""}, + {"UDPAddr.Port", Field, 0, ""}, + {"UDPAddr.Zone", Field, 1, ""}, + {"UDPAddrFromAddrPort", Func, 18, "func(addr netip.AddrPort) *UDPAddr"}, + {"UDPConn", Type, 0, ""}, + {"UnixAddr", Type, 0, ""}, + {"UnixAddr.Name", Field, 0, ""}, + {"UnixAddr.Net", Field, 0, ""}, + {"UnixConn", Type, 0, ""}, + {"UnixListener", Type, 0, ""}, + {"UnknownNetworkError", Type, 0, ""}, }, "net/http": { - {"(*Client).CloseIdleConnections", Method, 12}, - {"(*Client).Do", Method, 0}, - {"(*Client).Get", Method, 0}, - {"(*Client).Head", Method, 0}, - {"(*Client).Post", Method, 0}, - {"(*Client).PostForm", Method, 0}, - {"(*Cookie).String", Method, 0}, - {"(*Cookie).Valid", Method, 18}, - {"(*MaxBytesError).Error", Method, 19}, - {"(*ProtocolError).Error", Method, 0}, - {"(*ProtocolError).Is", Method, 21}, - {"(*Protocols).SetHTTP1", Method, 24}, - {"(*Protocols).SetHTTP2", Method, 24}, - {"(*Protocols).SetUnencryptedHTTP2", Method, 24}, - {"(*Request).AddCookie", Method, 0}, - {"(*Request).BasicAuth", Method, 4}, - {"(*Request).Clone", Method, 13}, - {"(*Request).Context", Method, 7}, - {"(*Request).Cookie", Method, 0}, - {"(*Request).Cookies", Method, 0}, - {"(*Request).CookiesNamed", Method, 23}, - {"(*Request).FormFile", Method, 0}, - {"(*Request).FormValue", Method, 0}, - {"(*Request).MultipartReader", Method, 0}, - {"(*Request).ParseForm", Method, 0}, - {"(*Request).ParseMultipartForm", Method, 0}, - {"(*Request).PathValue", Method, 22}, - {"(*Request).PostFormValue", Method, 1}, - {"(*Request).ProtoAtLeast", Method, 0}, - {"(*Request).Referer", Method, 0}, - {"(*Request).SetBasicAuth", Method, 0}, - {"(*Request).SetPathValue", Method, 22}, - {"(*Request).UserAgent", Method, 0}, - {"(*Request).WithContext", Method, 7}, - {"(*Request).Write", Method, 0}, - {"(*Request).WriteProxy", Method, 0}, - {"(*Response).Cookies", Method, 0}, - {"(*Response).Location", Method, 0}, - {"(*Response).ProtoAtLeast", Method, 0}, - {"(*Response).Write", Method, 0}, - {"(*ResponseController).EnableFullDuplex", Method, 21}, - {"(*ResponseController).Flush", Method, 20}, - {"(*ResponseController).Hijack", Method, 20}, - {"(*ResponseController).SetReadDeadline", Method, 20}, - {"(*ResponseController).SetWriteDeadline", Method, 20}, - {"(*ServeMux).Handle", Method, 0}, - {"(*ServeMux).HandleFunc", Method, 0}, - {"(*ServeMux).Handler", Method, 1}, - {"(*ServeMux).ServeHTTP", Method, 0}, - {"(*Server).Close", Method, 8}, - {"(*Server).ListenAndServe", Method, 0}, - {"(*Server).ListenAndServeTLS", Method, 0}, - {"(*Server).RegisterOnShutdown", Method, 9}, - {"(*Server).Serve", Method, 0}, - {"(*Server).ServeTLS", Method, 9}, - {"(*Server).SetKeepAlivesEnabled", Method, 3}, - {"(*Server).Shutdown", Method, 8}, - {"(*Transport).CancelRequest", Method, 1}, - {"(*Transport).Clone", Method, 13}, - {"(*Transport).CloseIdleConnections", Method, 0}, - {"(*Transport).RegisterProtocol", Method, 0}, - {"(*Transport).RoundTrip", Method, 0}, - {"(ConnState).String", Method, 3}, - {"(Dir).Open", Method, 0}, - {"(HandlerFunc).ServeHTTP", Method, 0}, - {"(Header).Add", Method, 0}, - {"(Header).Clone", Method, 13}, - {"(Header).Del", Method, 0}, - {"(Header).Get", Method, 0}, - {"(Header).Set", Method, 0}, - {"(Header).Values", Method, 14}, - {"(Header).Write", Method, 0}, - {"(Header).WriteSubset", Method, 0}, - {"(Protocols).HTTP1", Method, 24}, - {"(Protocols).HTTP2", Method, 24}, - {"(Protocols).String", Method, 24}, - {"(Protocols).UnencryptedHTTP2", Method, 24}, - {"AllowQuerySemicolons", Func, 17}, - {"CanonicalHeaderKey", Func, 0}, - {"Client", Type, 0}, - {"Client.CheckRedirect", Field, 0}, - {"Client.Jar", Field, 0}, - {"Client.Timeout", Field, 3}, - {"Client.Transport", Field, 0}, - {"CloseNotifier", Type, 1}, - {"ConnState", Type, 3}, - {"Cookie", Type, 0}, - {"Cookie.Domain", Field, 0}, - {"Cookie.Expires", Field, 0}, - {"Cookie.HttpOnly", Field, 0}, - {"Cookie.MaxAge", Field, 0}, - {"Cookie.Name", Field, 0}, - {"Cookie.Partitioned", Field, 23}, - {"Cookie.Path", Field, 0}, - {"Cookie.Quoted", Field, 23}, - {"Cookie.Raw", Field, 0}, - {"Cookie.RawExpires", Field, 0}, - {"Cookie.SameSite", Field, 11}, - {"Cookie.Secure", Field, 0}, - {"Cookie.Unparsed", Field, 0}, - {"Cookie.Value", Field, 0}, - {"CookieJar", Type, 0}, - {"DefaultClient", Var, 0}, - {"DefaultMaxHeaderBytes", Const, 0}, - {"DefaultMaxIdleConnsPerHost", Const, 0}, - {"DefaultServeMux", Var, 0}, - {"DefaultTransport", Var, 0}, - {"DetectContentType", Func, 0}, - {"Dir", Type, 0}, - {"ErrAbortHandler", Var, 8}, - {"ErrBodyNotAllowed", Var, 0}, - {"ErrBodyReadAfterClose", Var, 0}, - {"ErrContentLength", Var, 0}, - {"ErrHandlerTimeout", Var, 0}, - {"ErrHeaderTooLong", Var, 0}, - {"ErrHijacked", Var, 0}, - {"ErrLineTooLong", Var, 0}, - {"ErrMissingBoundary", Var, 0}, - {"ErrMissingContentLength", Var, 0}, - {"ErrMissingFile", Var, 0}, - {"ErrNoCookie", Var, 0}, - {"ErrNoLocation", Var, 0}, - {"ErrNotMultipart", Var, 0}, - {"ErrNotSupported", Var, 0}, - {"ErrSchemeMismatch", Var, 21}, - {"ErrServerClosed", Var, 8}, - {"ErrShortBody", Var, 0}, - {"ErrSkipAltProtocol", Var, 6}, - {"ErrUnexpectedTrailer", Var, 0}, - {"ErrUseLastResponse", Var, 7}, - {"ErrWriteAfterFlush", Var, 0}, - {"Error", Func, 0}, - {"FS", Func, 16}, - {"File", Type, 0}, - {"FileServer", Func, 0}, - {"FileServerFS", Func, 22}, - {"FileSystem", Type, 0}, - {"Flusher", Type, 0}, - {"Get", Func, 0}, - {"HTTP2Config", Type, 24}, - {"HTTP2Config.CountError", Field, 24}, - {"HTTP2Config.MaxConcurrentStreams", Field, 24}, - {"HTTP2Config.MaxDecoderHeaderTableSize", Field, 24}, - {"HTTP2Config.MaxEncoderHeaderTableSize", Field, 24}, - {"HTTP2Config.MaxReadFrameSize", Field, 24}, - {"HTTP2Config.MaxReceiveBufferPerConnection", Field, 24}, - {"HTTP2Config.MaxReceiveBufferPerStream", Field, 24}, - {"HTTP2Config.PermitProhibitedCipherSuites", Field, 24}, - {"HTTP2Config.PingTimeout", Field, 24}, - {"HTTP2Config.SendPingTimeout", Field, 24}, - {"HTTP2Config.WriteByteTimeout", Field, 24}, - {"Handle", Func, 0}, - {"HandleFunc", Func, 0}, - {"Handler", Type, 0}, - {"HandlerFunc", Type, 0}, - {"Head", Func, 0}, - {"Header", Type, 0}, - {"Hijacker", Type, 0}, - {"ListenAndServe", Func, 0}, - {"ListenAndServeTLS", Func, 0}, - {"LocalAddrContextKey", Var, 7}, - {"MaxBytesError", Type, 19}, - {"MaxBytesError.Limit", Field, 19}, - {"MaxBytesHandler", Func, 18}, - {"MaxBytesReader", Func, 0}, - {"MethodConnect", Const, 6}, - {"MethodDelete", Const, 6}, - {"MethodGet", Const, 6}, - {"MethodHead", Const, 6}, - {"MethodOptions", Const, 6}, - {"MethodPatch", Const, 6}, - {"MethodPost", Const, 6}, - {"MethodPut", Const, 6}, - {"MethodTrace", Const, 6}, - {"NewFileTransport", Func, 0}, - {"NewFileTransportFS", Func, 22}, - {"NewRequest", Func, 0}, - {"NewRequestWithContext", Func, 13}, - {"NewResponseController", Func, 20}, - {"NewServeMux", Func, 0}, - {"NoBody", Var, 8}, - {"NotFound", Func, 0}, - {"NotFoundHandler", Func, 0}, - {"ParseCookie", Func, 23}, - {"ParseHTTPVersion", Func, 0}, - {"ParseSetCookie", Func, 23}, - {"ParseTime", Func, 1}, - {"Post", Func, 0}, - {"PostForm", Func, 0}, - {"ProtocolError", Type, 0}, - {"ProtocolError.ErrorString", Field, 0}, - {"Protocols", Type, 24}, - {"ProxyFromEnvironment", Func, 0}, - {"ProxyURL", Func, 0}, - {"PushOptions", Type, 8}, - {"PushOptions.Header", Field, 8}, - {"PushOptions.Method", Field, 8}, - {"Pusher", Type, 8}, - {"ReadRequest", Func, 0}, - {"ReadResponse", Func, 0}, - {"Redirect", Func, 0}, - {"RedirectHandler", Func, 0}, - {"Request", Type, 0}, - {"Request.Body", Field, 0}, - {"Request.Cancel", Field, 5}, - {"Request.Close", Field, 0}, - {"Request.ContentLength", Field, 0}, - {"Request.Form", Field, 0}, - {"Request.GetBody", Field, 8}, - {"Request.Header", Field, 0}, - {"Request.Host", Field, 0}, - {"Request.Method", Field, 0}, - {"Request.MultipartForm", Field, 0}, - {"Request.Pattern", Field, 23}, - {"Request.PostForm", Field, 1}, - {"Request.Proto", Field, 0}, - {"Request.ProtoMajor", Field, 0}, - {"Request.ProtoMinor", Field, 0}, - {"Request.RemoteAddr", Field, 0}, - {"Request.RequestURI", Field, 0}, - {"Request.Response", Field, 7}, - {"Request.TLS", Field, 0}, - {"Request.Trailer", Field, 0}, - {"Request.TransferEncoding", Field, 0}, - {"Request.URL", Field, 0}, - {"Response", Type, 0}, - {"Response.Body", Field, 0}, - {"Response.Close", Field, 0}, - {"Response.ContentLength", Field, 0}, - {"Response.Header", Field, 0}, - {"Response.Proto", Field, 0}, - {"Response.ProtoMajor", Field, 0}, - {"Response.ProtoMinor", Field, 0}, - {"Response.Request", Field, 0}, - {"Response.Status", Field, 0}, - {"Response.StatusCode", Field, 0}, - {"Response.TLS", Field, 3}, - {"Response.Trailer", Field, 0}, - {"Response.TransferEncoding", Field, 0}, - {"Response.Uncompressed", Field, 7}, - {"ResponseController", Type, 20}, - {"ResponseWriter", Type, 0}, - {"RoundTripper", Type, 0}, - {"SameSite", Type, 11}, - {"SameSiteDefaultMode", Const, 11}, - {"SameSiteLaxMode", Const, 11}, - {"SameSiteNoneMode", Const, 13}, - {"SameSiteStrictMode", Const, 11}, - {"Serve", Func, 0}, - {"ServeContent", Func, 0}, - {"ServeFile", Func, 0}, - {"ServeFileFS", Func, 22}, - {"ServeMux", Type, 0}, - {"ServeTLS", Func, 9}, - {"Server", Type, 0}, - {"Server.Addr", Field, 0}, - {"Server.BaseContext", Field, 13}, - {"Server.ConnContext", Field, 13}, - {"Server.ConnState", Field, 3}, - {"Server.DisableGeneralOptionsHandler", Field, 20}, - {"Server.ErrorLog", Field, 3}, - {"Server.HTTP2", Field, 24}, - {"Server.Handler", Field, 0}, - {"Server.IdleTimeout", Field, 8}, - {"Server.MaxHeaderBytes", Field, 0}, - {"Server.Protocols", Field, 24}, - {"Server.ReadHeaderTimeout", Field, 8}, - {"Server.ReadTimeout", Field, 0}, - {"Server.TLSConfig", Field, 0}, - {"Server.TLSNextProto", Field, 1}, - {"Server.WriteTimeout", Field, 0}, - {"ServerContextKey", Var, 7}, - {"SetCookie", Func, 0}, - {"StateActive", Const, 3}, - {"StateClosed", Const, 3}, - {"StateHijacked", Const, 3}, - {"StateIdle", Const, 3}, - {"StateNew", Const, 3}, - {"StatusAccepted", Const, 0}, - {"StatusAlreadyReported", Const, 7}, - {"StatusBadGateway", Const, 0}, - {"StatusBadRequest", Const, 0}, - {"StatusConflict", Const, 0}, - {"StatusContinue", Const, 0}, - {"StatusCreated", Const, 0}, - {"StatusEarlyHints", Const, 13}, - {"StatusExpectationFailed", Const, 0}, - {"StatusFailedDependency", Const, 7}, - {"StatusForbidden", Const, 0}, - {"StatusFound", Const, 0}, - {"StatusGatewayTimeout", Const, 0}, - {"StatusGone", Const, 0}, - {"StatusHTTPVersionNotSupported", Const, 0}, - {"StatusIMUsed", Const, 7}, - {"StatusInsufficientStorage", Const, 7}, - {"StatusInternalServerError", Const, 0}, - {"StatusLengthRequired", Const, 0}, - {"StatusLocked", Const, 7}, - {"StatusLoopDetected", Const, 7}, - {"StatusMethodNotAllowed", Const, 0}, - {"StatusMisdirectedRequest", Const, 11}, - {"StatusMovedPermanently", Const, 0}, - {"StatusMultiStatus", Const, 7}, - {"StatusMultipleChoices", Const, 0}, - {"StatusNetworkAuthenticationRequired", Const, 6}, - {"StatusNoContent", Const, 0}, - {"StatusNonAuthoritativeInfo", Const, 0}, - {"StatusNotAcceptable", Const, 0}, - {"StatusNotExtended", Const, 7}, - {"StatusNotFound", Const, 0}, - {"StatusNotImplemented", Const, 0}, - {"StatusNotModified", Const, 0}, - {"StatusOK", Const, 0}, - {"StatusPartialContent", Const, 0}, - {"StatusPaymentRequired", Const, 0}, - {"StatusPermanentRedirect", Const, 7}, - {"StatusPreconditionFailed", Const, 0}, - {"StatusPreconditionRequired", Const, 6}, - {"StatusProcessing", Const, 7}, - {"StatusProxyAuthRequired", Const, 0}, - {"StatusRequestEntityTooLarge", Const, 0}, - {"StatusRequestHeaderFieldsTooLarge", Const, 6}, - {"StatusRequestTimeout", Const, 0}, - {"StatusRequestURITooLong", Const, 0}, - {"StatusRequestedRangeNotSatisfiable", Const, 0}, - {"StatusResetContent", Const, 0}, - {"StatusSeeOther", Const, 0}, - {"StatusServiceUnavailable", Const, 0}, - {"StatusSwitchingProtocols", Const, 0}, - {"StatusTeapot", Const, 0}, - {"StatusTemporaryRedirect", Const, 0}, - {"StatusText", Func, 0}, - {"StatusTooEarly", Const, 12}, - {"StatusTooManyRequests", Const, 6}, - {"StatusUnauthorized", Const, 0}, - {"StatusUnavailableForLegalReasons", Const, 6}, - {"StatusUnprocessableEntity", Const, 7}, - {"StatusUnsupportedMediaType", Const, 0}, - {"StatusUpgradeRequired", Const, 7}, - {"StatusUseProxy", Const, 0}, - {"StatusVariantAlsoNegotiates", Const, 7}, - {"StripPrefix", Func, 0}, - {"TimeFormat", Const, 0}, - {"TimeoutHandler", Func, 0}, - {"TrailerPrefix", Const, 8}, - {"Transport", Type, 0}, - {"Transport.Dial", Field, 0}, - {"Transport.DialContext", Field, 7}, - {"Transport.DialTLS", Field, 4}, - {"Transport.DialTLSContext", Field, 14}, - {"Transport.DisableCompression", Field, 0}, - {"Transport.DisableKeepAlives", Field, 0}, - {"Transport.ExpectContinueTimeout", Field, 6}, - {"Transport.ForceAttemptHTTP2", Field, 13}, - {"Transport.GetProxyConnectHeader", Field, 16}, - {"Transport.HTTP2", Field, 24}, - {"Transport.IdleConnTimeout", Field, 7}, - {"Transport.MaxConnsPerHost", Field, 11}, - {"Transport.MaxIdleConns", Field, 7}, - {"Transport.MaxIdleConnsPerHost", Field, 0}, - {"Transport.MaxResponseHeaderBytes", Field, 7}, - {"Transport.OnProxyConnectResponse", Field, 20}, - {"Transport.Protocols", Field, 24}, - {"Transport.Proxy", Field, 0}, - {"Transport.ProxyConnectHeader", Field, 8}, - {"Transport.ReadBufferSize", Field, 13}, - {"Transport.ResponseHeaderTimeout", Field, 1}, - {"Transport.TLSClientConfig", Field, 0}, - {"Transport.TLSHandshakeTimeout", Field, 3}, - {"Transport.TLSNextProto", Field, 6}, - {"Transport.WriteBufferSize", Field, 13}, + {"(*Client).CloseIdleConnections", Method, 12, ""}, + {"(*Client).Do", Method, 0, ""}, + {"(*Client).Get", Method, 0, ""}, + {"(*Client).Head", Method, 0, ""}, + {"(*Client).Post", Method, 0, ""}, + {"(*Client).PostForm", Method, 0, ""}, + {"(*Cookie).String", Method, 0, ""}, + {"(*Cookie).Valid", Method, 18, ""}, + {"(*MaxBytesError).Error", Method, 19, ""}, + {"(*ProtocolError).Error", Method, 0, ""}, + {"(*ProtocolError).Is", Method, 21, ""}, + {"(*Protocols).SetHTTP1", Method, 24, ""}, + {"(*Protocols).SetHTTP2", Method, 24, ""}, + {"(*Protocols).SetUnencryptedHTTP2", Method, 24, ""}, + {"(*Request).AddCookie", Method, 0, ""}, + {"(*Request).BasicAuth", Method, 4, ""}, + {"(*Request).Clone", Method, 13, ""}, + {"(*Request).Context", Method, 7, ""}, + {"(*Request).Cookie", Method, 0, ""}, + {"(*Request).Cookies", Method, 0, ""}, + {"(*Request).CookiesNamed", Method, 23, ""}, + {"(*Request).FormFile", Method, 0, ""}, + {"(*Request).FormValue", Method, 0, ""}, + {"(*Request).MultipartReader", Method, 0, ""}, + {"(*Request).ParseForm", Method, 0, ""}, + {"(*Request).ParseMultipartForm", Method, 0, ""}, + {"(*Request).PathValue", Method, 22, ""}, + {"(*Request).PostFormValue", Method, 1, ""}, + {"(*Request).ProtoAtLeast", Method, 0, ""}, + {"(*Request).Referer", Method, 0, ""}, + {"(*Request).SetBasicAuth", Method, 0, ""}, + {"(*Request).SetPathValue", Method, 22, ""}, + {"(*Request).UserAgent", Method, 0, ""}, + {"(*Request).WithContext", Method, 7, ""}, + {"(*Request).Write", Method, 0, ""}, + {"(*Request).WriteProxy", Method, 0, ""}, + {"(*Response).Cookies", Method, 0, ""}, + {"(*Response).Location", Method, 0, ""}, + {"(*Response).ProtoAtLeast", Method, 0, ""}, + {"(*Response).Write", Method, 0, ""}, + {"(*ResponseController).EnableFullDuplex", Method, 21, ""}, + {"(*ResponseController).Flush", Method, 20, ""}, + {"(*ResponseController).Hijack", Method, 20, ""}, + {"(*ResponseController).SetReadDeadline", Method, 20, ""}, + {"(*ResponseController).SetWriteDeadline", Method, 20, ""}, + {"(*ServeMux).Handle", Method, 0, ""}, + {"(*ServeMux).HandleFunc", Method, 0, ""}, + {"(*ServeMux).Handler", Method, 1, ""}, + {"(*ServeMux).ServeHTTP", Method, 0, ""}, + {"(*Server).Close", Method, 8, ""}, + {"(*Server).ListenAndServe", Method, 0, ""}, + {"(*Server).ListenAndServeTLS", Method, 0, ""}, + {"(*Server).RegisterOnShutdown", Method, 9, ""}, + {"(*Server).Serve", Method, 0, ""}, + {"(*Server).ServeTLS", Method, 9, ""}, + {"(*Server).SetKeepAlivesEnabled", Method, 3, ""}, + {"(*Server).Shutdown", Method, 8, ""}, + {"(*Transport).CancelRequest", Method, 1, ""}, + {"(*Transport).Clone", Method, 13, ""}, + {"(*Transport).CloseIdleConnections", Method, 0, ""}, + {"(*Transport).RegisterProtocol", Method, 0, ""}, + {"(*Transport).RoundTrip", Method, 0, ""}, + {"(ConnState).String", Method, 3, ""}, + {"(Dir).Open", Method, 0, ""}, + {"(HandlerFunc).ServeHTTP", Method, 0, ""}, + {"(Header).Add", Method, 0, ""}, + {"(Header).Clone", Method, 13, ""}, + {"(Header).Del", Method, 0, ""}, + {"(Header).Get", Method, 0, ""}, + {"(Header).Set", Method, 0, ""}, + {"(Header).Values", Method, 14, ""}, + {"(Header).Write", Method, 0, ""}, + {"(Header).WriteSubset", Method, 0, ""}, + {"(Protocols).HTTP1", Method, 24, ""}, + {"(Protocols).HTTP2", Method, 24, ""}, + {"(Protocols).String", Method, 24, ""}, + {"(Protocols).UnencryptedHTTP2", Method, 24, ""}, + {"AllowQuerySemicolons", Func, 17, "func(h Handler) Handler"}, + {"CanonicalHeaderKey", Func, 0, "func(s string) string"}, + {"Client", Type, 0, ""}, + {"Client.CheckRedirect", Field, 0, ""}, + {"Client.Jar", Field, 0, ""}, + {"Client.Timeout", Field, 3, ""}, + {"Client.Transport", Field, 0, ""}, + {"CloseNotifier", Type, 1, ""}, + {"ConnState", Type, 3, ""}, + {"Cookie", Type, 0, ""}, + {"Cookie.Domain", Field, 0, ""}, + {"Cookie.Expires", Field, 0, ""}, + {"Cookie.HttpOnly", Field, 0, ""}, + {"Cookie.MaxAge", Field, 0, ""}, + {"Cookie.Name", Field, 0, ""}, + {"Cookie.Partitioned", Field, 23, ""}, + {"Cookie.Path", Field, 0, ""}, + {"Cookie.Quoted", Field, 23, ""}, + {"Cookie.Raw", Field, 0, ""}, + {"Cookie.RawExpires", Field, 0, ""}, + {"Cookie.SameSite", Field, 11, ""}, + {"Cookie.Secure", Field, 0, ""}, + {"Cookie.Unparsed", Field, 0, ""}, + {"Cookie.Value", Field, 0, ""}, + {"CookieJar", Type, 0, ""}, + {"DefaultClient", Var, 0, ""}, + {"DefaultMaxHeaderBytes", Const, 0, ""}, + {"DefaultMaxIdleConnsPerHost", Const, 0, ""}, + {"DefaultServeMux", Var, 0, ""}, + {"DefaultTransport", Var, 0, ""}, + {"DetectContentType", Func, 0, "func(data []byte) string"}, + {"Dir", Type, 0, ""}, + {"ErrAbortHandler", Var, 8, ""}, + {"ErrBodyNotAllowed", Var, 0, ""}, + {"ErrBodyReadAfterClose", Var, 0, ""}, + {"ErrContentLength", Var, 0, ""}, + {"ErrHandlerTimeout", Var, 0, ""}, + {"ErrHeaderTooLong", Var, 0, ""}, + {"ErrHijacked", Var, 0, ""}, + {"ErrLineTooLong", Var, 0, ""}, + {"ErrMissingBoundary", Var, 0, ""}, + {"ErrMissingContentLength", Var, 0, ""}, + {"ErrMissingFile", Var, 0, ""}, + {"ErrNoCookie", Var, 0, ""}, + {"ErrNoLocation", Var, 0, ""}, + {"ErrNotMultipart", Var, 0, ""}, + {"ErrNotSupported", Var, 0, ""}, + {"ErrSchemeMismatch", Var, 21, ""}, + {"ErrServerClosed", Var, 8, ""}, + {"ErrShortBody", Var, 0, ""}, + {"ErrSkipAltProtocol", Var, 6, ""}, + {"ErrUnexpectedTrailer", Var, 0, ""}, + {"ErrUseLastResponse", Var, 7, ""}, + {"ErrWriteAfterFlush", Var, 0, ""}, + {"Error", Func, 0, "func(w ResponseWriter, error string, code int)"}, + {"FS", Func, 16, "func(fsys fs.FS) FileSystem"}, + {"File", Type, 0, ""}, + {"FileServer", Func, 0, "func(root FileSystem) Handler"}, + {"FileServerFS", Func, 22, "func(root fs.FS) Handler"}, + {"FileSystem", Type, 0, ""}, + {"Flusher", Type, 0, ""}, + {"Get", Func, 0, "func(url string) (resp *Response, err error)"}, + {"HTTP2Config", Type, 24, ""}, + {"HTTP2Config.CountError", Field, 24, ""}, + {"HTTP2Config.MaxConcurrentStreams", Field, 24, ""}, + {"HTTP2Config.MaxDecoderHeaderTableSize", Field, 24, ""}, + {"HTTP2Config.MaxEncoderHeaderTableSize", Field, 24, ""}, + {"HTTP2Config.MaxReadFrameSize", Field, 24, ""}, + {"HTTP2Config.MaxReceiveBufferPerConnection", Field, 24, ""}, + {"HTTP2Config.MaxReceiveBufferPerStream", Field, 24, ""}, + {"HTTP2Config.PermitProhibitedCipherSuites", Field, 24, ""}, + {"HTTP2Config.PingTimeout", Field, 24, ""}, + {"HTTP2Config.SendPingTimeout", Field, 24, ""}, + {"HTTP2Config.WriteByteTimeout", Field, 24, ""}, + {"Handle", Func, 0, "func(pattern string, handler Handler)"}, + {"HandleFunc", Func, 0, "func(pattern string, handler func(ResponseWriter, *Request))"}, + {"Handler", Type, 0, ""}, + {"HandlerFunc", Type, 0, ""}, + {"Head", Func, 0, "func(url string) (resp *Response, err error)"}, + {"Header", Type, 0, ""}, + {"Hijacker", Type, 0, ""}, + {"ListenAndServe", Func, 0, "func(addr string, handler Handler) error"}, + {"ListenAndServeTLS", Func, 0, "func(addr string, certFile string, keyFile string, handler Handler) error"}, + {"LocalAddrContextKey", Var, 7, ""}, + {"MaxBytesError", Type, 19, ""}, + {"MaxBytesError.Limit", Field, 19, ""}, + {"MaxBytesHandler", Func, 18, "func(h Handler, n int64) Handler"}, + {"MaxBytesReader", Func, 0, "func(w ResponseWriter, r io.ReadCloser, n int64) io.ReadCloser"}, + {"MethodConnect", Const, 6, ""}, + {"MethodDelete", Const, 6, ""}, + {"MethodGet", Const, 6, ""}, + {"MethodHead", Const, 6, ""}, + {"MethodOptions", Const, 6, ""}, + {"MethodPatch", Const, 6, ""}, + {"MethodPost", Const, 6, ""}, + {"MethodPut", Const, 6, ""}, + {"MethodTrace", Const, 6, ""}, + {"NewFileTransport", Func, 0, "func(fs FileSystem) RoundTripper"}, + {"NewFileTransportFS", Func, 22, "func(fsys fs.FS) RoundTripper"}, + {"NewRequest", Func, 0, "func(method string, url string, body io.Reader) (*Request, error)"}, + {"NewRequestWithContext", Func, 13, "func(ctx context.Context, method string, url string, body io.Reader) (*Request, error)"}, + {"NewResponseController", Func, 20, "func(rw ResponseWriter) *ResponseController"}, + {"NewServeMux", Func, 0, "func() *ServeMux"}, + {"NoBody", Var, 8, ""}, + {"NotFound", Func, 0, "func(w ResponseWriter, r *Request)"}, + {"NotFoundHandler", Func, 0, "func() Handler"}, + {"ParseCookie", Func, 23, "func(line string) ([]*Cookie, error)"}, + {"ParseHTTPVersion", Func, 0, "func(vers string) (major int, minor int, ok bool)"}, + {"ParseSetCookie", Func, 23, "func(line string) (*Cookie, error)"}, + {"ParseTime", Func, 1, "func(text string) (t time.Time, err error)"}, + {"Post", Func, 0, "func(url string, contentType string, body io.Reader) (resp *Response, err error)"}, + {"PostForm", Func, 0, "func(url string, data url.Values) (resp *Response, err error)"}, + {"ProtocolError", Type, 0, ""}, + {"ProtocolError.ErrorString", Field, 0, ""}, + {"Protocols", Type, 24, ""}, + {"ProxyFromEnvironment", Func, 0, "func(req *Request) (*url.URL, error)"}, + {"ProxyURL", Func, 0, "func(fixedURL *url.URL) func(*Request) (*url.URL, error)"}, + {"PushOptions", Type, 8, ""}, + {"PushOptions.Header", Field, 8, ""}, + {"PushOptions.Method", Field, 8, ""}, + {"Pusher", Type, 8, ""}, + {"ReadRequest", Func, 0, "func(b *bufio.Reader) (*Request, error)"}, + {"ReadResponse", Func, 0, "func(r *bufio.Reader, req *Request) (*Response, error)"}, + {"Redirect", Func, 0, "func(w ResponseWriter, r *Request, url string, code int)"}, + {"RedirectHandler", Func, 0, "func(url string, code int) Handler"}, + {"Request", Type, 0, ""}, + {"Request.Body", Field, 0, ""}, + {"Request.Cancel", Field, 5, ""}, + {"Request.Close", Field, 0, ""}, + {"Request.ContentLength", Field, 0, ""}, + {"Request.Form", Field, 0, ""}, + {"Request.GetBody", Field, 8, ""}, + {"Request.Header", Field, 0, ""}, + {"Request.Host", Field, 0, ""}, + {"Request.Method", Field, 0, ""}, + {"Request.MultipartForm", Field, 0, ""}, + {"Request.Pattern", Field, 23, ""}, + {"Request.PostForm", Field, 1, ""}, + {"Request.Proto", Field, 0, ""}, + {"Request.ProtoMajor", Field, 0, ""}, + {"Request.ProtoMinor", Field, 0, ""}, + {"Request.RemoteAddr", Field, 0, ""}, + {"Request.RequestURI", Field, 0, ""}, + {"Request.Response", Field, 7, ""}, + {"Request.TLS", Field, 0, ""}, + {"Request.Trailer", Field, 0, ""}, + {"Request.TransferEncoding", Field, 0, ""}, + {"Request.URL", Field, 0, ""}, + {"Response", Type, 0, ""}, + {"Response.Body", Field, 0, ""}, + {"Response.Close", Field, 0, ""}, + {"Response.ContentLength", Field, 0, ""}, + {"Response.Header", Field, 0, ""}, + {"Response.Proto", Field, 0, ""}, + {"Response.ProtoMajor", Field, 0, ""}, + {"Response.ProtoMinor", Field, 0, ""}, + {"Response.Request", Field, 0, ""}, + {"Response.Status", Field, 0, ""}, + {"Response.StatusCode", Field, 0, ""}, + {"Response.TLS", Field, 3, ""}, + {"Response.Trailer", Field, 0, ""}, + {"Response.TransferEncoding", Field, 0, ""}, + {"Response.Uncompressed", Field, 7, ""}, + {"ResponseController", Type, 20, ""}, + {"ResponseWriter", Type, 0, ""}, + {"RoundTripper", Type, 0, ""}, + {"SameSite", Type, 11, ""}, + {"SameSiteDefaultMode", Const, 11, ""}, + {"SameSiteLaxMode", Const, 11, ""}, + {"SameSiteNoneMode", Const, 13, ""}, + {"SameSiteStrictMode", Const, 11, ""}, + {"Serve", Func, 0, "func(l net.Listener, handler Handler) error"}, + {"ServeContent", Func, 0, "func(w ResponseWriter, req *Request, name string, modtime time.Time, content io.ReadSeeker)"}, + {"ServeFile", Func, 0, "func(w ResponseWriter, r *Request, name string)"}, + {"ServeFileFS", Func, 22, "func(w ResponseWriter, r *Request, fsys fs.FS, name string)"}, + {"ServeMux", Type, 0, ""}, + {"ServeTLS", Func, 9, "func(l net.Listener, handler Handler, certFile string, keyFile string) error"}, + {"Server", Type, 0, ""}, + {"Server.Addr", Field, 0, ""}, + {"Server.BaseContext", Field, 13, ""}, + {"Server.ConnContext", Field, 13, ""}, + {"Server.ConnState", Field, 3, ""}, + {"Server.DisableGeneralOptionsHandler", Field, 20, ""}, + {"Server.ErrorLog", Field, 3, ""}, + {"Server.HTTP2", Field, 24, ""}, + {"Server.Handler", Field, 0, ""}, + {"Server.IdleTimeout", Field, 8, ""}, + {"Server.MaxHeaderBytes", Field, 0, ""}, + {"Server.Protocols", Field, 24, ""}, + {"Server.ReadHeaderTimeout", Field, 8, ""}, + {"Server.ReadTimeout", Field, 0, ""}, + {"Server.TLSConfig", Field, 0, ""}, + {"Server.TLSNextProto", Field, 1, ""}, + {"Server.WriteTimeout", Field, 0, ""}, + {"ServerContextKey", Var, 7, ""}, + {"SetCookie", Func, 0, "func(w ResponseWriter, cookie *Cookie)"}, + {"StateActive", Const, 3, ""}, + {"StateClosed", Const, 3, ""}, + {"StateHijacked", Const, 3, ""}, + {"StateIdle", Const, 3, ""}, + {"StateNew", Const, 3, ""}, + {"StatusAccepted", Const, 0, ""}, + {"StatusAlreadyReported", Const, 7, ""}, + {"StatusBadGateway", Const, 0, ""}, + {"StatusBadRequest", Const, 0, ""}, + {"StatusConflict", Const, 0, ""}, + {"StatusContinue", Const, 0, ""}, + {"StatusCreated", Const, 0, ""}, + {"StatusEarlyHints", Const, 13, ""}, + {"StatusExpectationFailed", Const, 0, ""}, + {"StatusFailedDependency", Const, 7, ""}, + {"StatusForbidden", Const, 0, ""}, + {"StatusFound", Const, 0, ""}, + {"StatusGatewayTimeout", Const, 0, ""}, + {"StatusGone", Const, 0, ""}, + {"StatusHTTPVersionNotSupported", Const, 0, ""}, + {"StatusIMUsed", Const, 7, ""}, + {"StatusInsufficientStorage", Const, 7, ""}, + {"StatusInternalServerError", Const, 0, ""}, + {"StatusLengthRequired", Const, 0, ""}, + {"StatusLocked", Const, 7, ""}, + {"StatusLoopDetected", Const, 7, ""}, + {"StatusMethodNotAllowed", Const, 0, ""}, + {"StatusMisdirectedRequest", Const, 11, ""}, + {"StatusMovedPermanently", Const, 0, ""}, + {"StatusMultiStatus", Const, 7, ""}, + {"StatusMultipleChoices", Const, 0, ""}, + {"StatusNetworkAuthenticationRequired", Const, 6, ""}, + {"StatusNoContent", Const, 0, ""}, + {"StatusNonAuthoritativeInfo", Const, 0, ""}, + {"StatusNotAcceptable", Const, 0, ""}, + {"StatusNotExtended", Const, 7, ""}, + {"StatusNotFound", Const, 0, ""}, + {"StatusNotImplemented", Const, 0, ""}, + {"StatusNotModified", Const, 0, ""}, + {"StatusOK", Const, 0, ""}, + {"StatusPartialContent", Const, 0, ""}, + {"StatusPaymentRequired", Const, 0, ""}, + {"StatusPermanentRedirect", Const, 7, ""}, + {"StatusPreconditionFailed", Const, 0, ""}, + {"StatusPreconditionRequired", Const, 6, ""}, + {"StatusProcessing", Const, 7, ""}, + {"StatusProxyAuthRequired", Const, 0, ""}, + {"StatusRequestEntityTooLarge", Const, 0, ""}, + {"StatusRequestHeaderFieldsTooLarge", Const, 6, ""}, + {"StatusRequestTimeout", Const, 0, ""}, + {"StatusRequestURITooLong", Const, 0, ""}, + {"StatusRequestedRangeNotSatisfiable", Const, 0, ""}, + {"StatusResetContent", Const, 0, ""}, + {"StatusSeeOther", Const, 0, ""}, + {"StatusServiceUnavailable", Const, 0, ""}, + {"StatusSwitchingProtocols", Const, 0, ""}, + {"StatusTeapot", Const, 0, ""}, + {"StatusTemporaryRedirect", Const, 0, ""}, + {"StatusText", Func, 0, "func(code int) string"}, + {"StatusTooEarly", Const, 12, ""}, + {"StatusTooManyRequests", Const, 6, ""}, + {"StatusUnauthorized", Const, 0, ""}, + {"StatusUnavailableForLegalReasons", Const, 6, ""}, + {"StatusUnprocessableEntity", Const, 7, ""}, + {"StatusUnsupportedMediaType", Const, 0, ""}, + {"StatusUpgradeRequired", Const, 7, ""}, + {"StatusUseProxy", Const, 0, ""}, + {"StatusVariantAlsoNegotiates", Const, 7, ""}, + {"StripPrefix", Func, 0, "func(prefix string, h Handler) Handler"}, + {"TimeFormat", Const, 0, ""}, + {"TimeoutHandler", Func, 0, "func(h Handler, dt time.Duration, msg string) Handler"}, + {"TrailerPrefix", Const, 8, ""}, + {"Transport", Type, 0, ""}, + {"Transport.Dial", Field, 0, ""}, + {"Transport.DialContext", Field, 7, ""}, + {"Transport.DialTLS", Field, 4, ""}, + {"Transport.DialTLSContext", Field, 14, ""}, + {"Transport.DisableCompression", Field, 0, ""}, + {"Transport.DisableKeepAlives", Field, 0, ""}, + {"Transport.ExpectContinueTimeout", Field, 6, ""}, + {"Transport.ForceAttemptHTTP2", Field, 13, ""}, + {"Transport.GetProxyConnectHeader", Field, 16, ""}, + {"Transport.HTTP2", Field, 24, ""}, + {"Transport.IdleConnTimeout", Field, 7, ""}, + {"Transport.MaxConnsPerHost", Field, 11, ""}, + {"Transport.MaxIdleConns", Field, 7, ""}, + {"Transport.MaxIdleConnsPerHost", Field, 0, ""}, + {"Transport.MaxResponseHeaderBytes", Field, 7, ""}, + {"Transport.OnProxyConnectResponse", Field, 20, ""}, + {"Transport.Protocols", Field, 24, ""}, + {"Transport.Proxy", Field, 0, ""}, + {"Transport.ProxyConnectHeader", Field, 8, ""}, + {"Transport.ReadBufferSize", Field, 13, ""}, + {"Transport.ResponseHeaderTimeout", Field, 1, ""}, + {"Transport.TLSClientConfig", Field, 0, ""}, + {"Transport.TLSHandshakeTimeout", Field, 3, ""}, + {"Transport.TLSNextProto", Field, 6, ""}, + {"Transport.WriteBufferSize", Field, 13, ""}, }, "net/http/cgi": { - {"(*Handler).ServeHTTP", Method, 0}, - {"Handler", Type, 0}, - {"Handler.Args", Field, 0}, - {"Handler.Dir", Field, 0}, - {"Handler.Env", Field, 0}, - {"Handler.InheritEnv", Field, 0}, - {"Handler.Logger", Field, 0}, - {"Handler.Path", Field, 0}, - {"Handler.PathLocationHandler", Field, 0}, - {"Handler.Root", Field, 0}, - {"Handler.Stderr", Field, 7}, - {"Request", Func, 0}, - {"RequestFromMap", Func, 0}, - {"Serve", Func, 0}, + {"(*Handler).ServeHTTP", Method, 0, ""}, + {"Handler", Type, 0, ""}, + {"Handler.Args", Field, 0, ""}, + {"Handler.Dir", Field, 0, ""}, + {"Handler.Env", Field, 0, ""}, + {"Handler.InheritEnv", Field, 0, ""}, + {"Handler.Logger", Field, 0, ""}, + {"Handler.Path", Field, 0, ""}, + {"Handler.PathLocationHandler", Field, 0, ""}, + {"Handler.Root", Field, 0, ""}, + {"Handler.Stderr", Field, 7, ""}, + {"Request", Func, 0, "func() (*http.Request, error)"}, + {"RequestFromMap", Func, 0, "func(params map[string]string) (*http.Request, error)"}, + {"Serve", Func, 0, "func(handler http.Handler) error"}, }, "net/http/cookiejar": { - {"(*Jar).Cookies", Method, 1}, - {"(*Jar).SetCookies", Method, 1}, - {"Jar", Type, 1}, - {"New", Func, 1}, - {"Options", Type, 1}, - {"Options.PublicSuffixList", Field, 1}, - {"PublicSuffixList", Type, 1}, + {"(*Jar).Cookies", Method, 1, ""}, + {"(*Jar).SetCookies", Method, 1, ""}, + {"Jar", Type, 1, ""}, + {"New", Func, 1, "func(o *Options) (*Jar, error)"}, + {"Options", Type, 1, ""}, + {"Options.PublicSuffixList", Field, 1, ""}, + {"PublicSuffixList", Type, 1, ""}, }, "net/http/fcgi": { - {"ErrConnClosed", Var, 5}, - {"ErrRequestAborted", Var, 5}, - {"ProcessEnv", Func, 9}, - {"Serve", Func, 0}, + {"ErrConnClosed", Var, 5, ""}, + {"ErrRequestAborted", Var, 5, ""}, + {"ProcessEnv", Func, 9, "func(r *http.Request) map[string]string"}, + {"Serve", Func, 0, "func(l net.Listener, handler http.Handler) error"}, }, "net/http/httptest": { - {"(*ResponseRecorder).Flush", Method, 0}, - {"(*ResponseRecorder).Header", Method, 0}, - {"(*ResponseRecorder).Result", Method, 7}, - {"(*ResponseRecorder).Write", Method, 0}, - {"(*ResponseRecorder).WriteHeader", Method, 0}, - {"(*ResponseRecorder).WriteString", Method, 6}, - {"(*Server).Certificate", Method, 9}, - {"(*Server).Client", Method, 9}, - {"(*Server).Close", Method, 0}, - {"(*Server).CloseClientConnections", Method, 0}, - {"(*Server).Start", Method, 0}, - {"(*Server).StartTLS", Method, 0}, - {"DefaultRemoteAddr", Const, 0}, - {"NewRecorder", Func, 0}, - {"NewRequest", Func, 7}, - {"NewRequestWithContext", Func, 23}, - {"NewServer", Func, 0}, - {"NewTLSServer", Func, 0}, - {"NewUnstartedServer", Func, 0}, - {"ResponseRecorder", Type, 0}, - {"ResponseRecorder.Body", Field, 0}, - {"ResponseRecorder.Code", Field, 0}, - {"ResponseRecorder.Flushed", Field, 0}, - {"ResponseRecorder.HeaderMap", Field, 0}, - {"Server", Type, 0}, - {"Server.Config", Field, 0}, - {"Server.EnableHTTP2", Field, 14}, - {"Server.Listener", Field, 0}, - {"Server.TLS", Field, 0}, - {"Server.URL", Field, 0}, + {"(*ResponseRecorder).Flush", Method, 0, ""}, + {"(*ResponseRecorder).Header", Method, 0, ""}, + {"(*ResponseRecorder).Result", Method, 7, ""}, + {"(*ResponseRecorder).Write", Method, 0, ""}, + {"(*ResponseRecorder).WriteHeader", Method, 0, ""}, + {"(*ResponseRecorder).WriteString", Method, 6, ""}, + {"(*Server).Certificate", Method, 9, ""}, + {"(*Server).Client", Method, 9, ""}, + {"(*Server).Close", Method, 0, ""}, + {"(*Server).CloseClientConnections", Method, 0, ""}, + {"(*Server).Start", Method, 0, ""}, + {"(*Server).StartTLS", Method, 0, ""}, + {"DefaultRemoteAddr", Const, 0, ""}, + {"NewRecorder", Func, 0, "func() *ResponseRecorder"}, + {"NewRequest", Func, 7, "func(method string, target string, body io.Reader) *http.Request"}, + {"NewRequestWithContext", Func, 23, "func(ctx context.Context, method string, target string, body io.Reader) *http.Request"}, + {"NewServer", Func, 0, "func(handler http.Handler) *Server"}, + {"NewTLSServer", Func, 0, "func(handler http.Handler) *Server"}, + {"NewUnstartedServer", Func, 0, "func(handler http.Handler) *Server"}, + {"ResponseRecorder", Type, 0, ""}, + {"ResponseRecorder.Body", Field, 0, ""}, + {"ResponseRecorder.Code", Field, 0, ""}, + {"ResponseRecorder.Flushed", Field, 0, ""}, + {"ResponseRecorder.HeaderMap", Field, 0, ""}, + {"Server", Type, 0, ""}, + {"Server.Config", Field, 0, ""}, + {"Server.EnableHTTP2", Field, 14, ""}, + {"Server.Listener", Field, 0, ""}, + {"Server.TLS", Field, 0, ""}, + {"Server.URL", Field, 0, ""}, }, "net/http/httptrace": { - {"ClientTrace", Type, 7}, - {"ClientTrace.ConnectDone", Field, 7}, - {"ClientTrace.ConnectStart", Field, 7}, - {"ClientTrace.DNSDone", Field, 7}, - {"ClientTrace.DNSStart", Field, 7}, - {"ClientTrace.GetConn", Field, 7}, - {"ClientTrace.Got100Continue", Field, 7}, - {"ClientTrace.Got1xxResponse", Field, 11}, - {"ClientTrace.GotConn", Field, 7}, - {"ClientTrace.GotFirstResponseByte", Field, 7}, - {"ClientTrace.PutIdleConn", Field, 7}, - {"ClientTrace.TLSHandshakeDone", Field, 8}, - {"ClientTrace.TLSHandshakeStart", Field, 8}, - {"ClientTrace.Wait100Continue", Field, 7}, - {"ClientTrace.WroteHeaderField", Field, 11}, - {"ClientTrace.WroteHeaders", Field, 7}, - {"ClientTrace.WroteRequest", Field, 7}, - {"ContextClientTrace", Func, 7}, - {"DNSDoneInfo", Type, 7}, - {"DNSDoneInfo.Addrs", Field, 7}, - {"DNSDoneInfo.Coalesced", Field, 7}, - {"DNSDoneInfo.Err", Field, 7}, - {"DNSStartInfo", Type, 7}, - {"DNSStartInfo.Host", Field, 7}, - {"GotConnInfo", Type, 7}, - {"GotConnInfo.Conn", Field, 7}, - {"GotConnInfo.IdleTime", Field, 7}, - {"GotConnInfo.Reused", Field, 7}, - {"GotConnInfo.WasIdle", Field, 7}, - {"WithClientTrace", Func, 7}, - {"WroteRequestInfo", Type, 7}, - {"WroteRequestInfo.Err", Field, 7}, + {"ClientTrace", Type, 7, ""}, + {"ClientTrace.ConnectDone", Field, 7, ""}, + {"ClientTrace.ConnectStart", Field, 7, ""}, + {"ClientTrace.DNSDone", Field, 7, ""}, + {"ClientTrace.DNSStart", Field, 7, ""}, + {"ClientTrace.GetConn", Field, 7, ""}, + {"ClientTrace.Got100Continue", Field, 7, ""}, + {"ClientTrace.Got1xxResponse", Field, 11, ""}, + {"ClientTrace.GotConn", Field, 7, ""}, + {"ClientTrace.GotFirstResponseByte", Field, 7, ""}, + {"ClientTrace.PutIdleConn", Field, 7, ""}, + {"ClientTrace.TLSHandshakeDone", Field, 8, ""}, + {"ClientTrace.TLSHandshakeStart", Field, 8, ""}, + {"ClientTrace.Wait100Continue", Field, 7, ""}, + {"ClientTrace.WroteHeaderField", Field, 11, ""}, + {"ClientTrace.WroteHeaders", Field, 7, ""}, + {"ClientTrace.WroteRequest", Field, 7, ""}, + {"ContextClientTrace", Func, 7, "func(ctx context.Context) *ClientTrace"}, + {"DNSDoneInfo", Type, 7, ""}, + {"DNSDoneInfo.Addrs", Field, 7, ""}, + {"DNSDoneInfo.Coalesced", Field, 7, ""}, + {"DNSDoneInfo.Err", Field, 7, ""}, + {"DNSStartInfo", Type, 7, ""}, + {"DNSStartInfo.Host", Field, 7, ""}, + {"GotConnInfo", Type, 7, ""}, + {"GotConnInfo.Conn", Field, 7, ""}, + {"GotConnInfo.IdleTime", Field, 7, ""}, + {"GotConnInfo.Reused", Field, 7, ""}, + {"GotConnInfo.WasIdle", Field, 7, ""}, + {"WithClientTrace", Func, 7, "func(ctx context.Context, trace *ClientTrace) context.Context"}, + {"WroteRequestInfo", Type, 7, ""}, + {"WroteRequestInfo.Err", Field, 7, ""}, }, "net/http/httputil": { - {"(*ClientConn).Close", Method, 0}, - {"(*ClientConn).Do", Method, 0}, - {"(*ClientConn).Hijack", Method, 0}, - {"(*ClientConn).Pending", Method, 0}, - {"(*ClientConn).Read", Method, 0}, - {"(*ClientConn).Write", Method, 0}, - {"(*ProxyRequest).SetURL", Method, 20}, - {"(*ProxyRequest).SetXForwarded", Method, 20}, - {"(*ReverseProxy).ServeHTTP", Method, 0}, - {"(*ServerConn).Close", Method, 0}, - {"(*ServerConn).Hijack", Method, 0}, - {"(*ServerConn).Pending", Method, 0}, - {"(*ServerConn).Read", Method, 0}, - {"(*ServerConn).Write", Method, 0}, - {"BufferPool", Type, 6}, - {"ClientConn", Type, 0}, - {"DumpRequest", Func, 0}, - {"DumpRequestOut", Func, 0}, - {"DumpResponse", Func, 0}, - {"ErrClosed", Var, 0}, - {"ErrLineTooLong", Var, 0}, - {"ErrPersistEOF", Var, 0}, - {"ErrPipeline", Var, 0}, - {"NewChunkedReader", Func, 0}, - {"NewChunkedWriter", Func, 0}, - {"NewClientConn", Func, 0}, - {"NewProxyClientConn", Func, 0}, - {"NewServerConn", Func, 0}, - {"NewSingleHostReverseProxy", Func, 0}, - {"ProxyRequest", Type, 20}, - {"ProxyRequest.In", Field, 20}, - {"ProxyRequest.Out", Field, 20}, - {"ReverseProxy", Type, 0}, - {"ReverseProxy.BufferPool", Field, 6}, - {"ReverseProxy.Director", Field, 0}, - {"ReverseProxy.ErrorHandler", Field, 11}, - {"ReverseProxy.ErrorLog", Field, 4}, - {"ReverseProxy.FlushInterval", Field, 0}, - {"ReverseProxy.ModifyResponse", Field, 8}, - {"ReverseProxy.Rewrite", Field, 20}, - {"ReverseProxy.Transport", Field, 0}, - {"ServerConn", Type, 0}, + {"(*ClientConn).Close", Method, 0, ""}, + {"(*ClientConn).Do", Method, 0, ""}, + {"(*ClientConn).Hijack", Method, 0, ""}, + {"(*ClientConn).Pending", Method, 0, ""}, + {"(*ClientConn).Read", Method, 0, ""}, + {"(*ClientConn).Write", Method, 0, ""}, + {"(*ProxyRequest).SetURL", Method, 20, ""}, + {"(*ProxyRequest).SetXForwarded", Method, 20, ""}, + {"(*ReverseProxy).ServeHTTP", Method, 0, ""}, + {"(*ServerConn).Close", Method, 0, ""}, + {"(*ServerConn).Hijack", Method, 0, ""}, + {"(*ServerConn).Pending", Method, 0, ""}, + {"(*ServerConn).Read", Method, 0, ""}, + {"(*ServerConn).Write", Method, 0, ""}, + {"BufferPool", Type, 6, ""}, + {"ClientConn", Type, 0, ""}, + {"DumpRequest", Func, 0, "func(req *http.Request, body bool) ([]byte, error)"}, + {"DumpRequestOut", Func, 0, "func(req *http.Request, body bool) ([]byte, error)"}, + {"DumpResponse", Func, 0, "func(resp *http.Response, body bool) ([]byte, error)"}, + {"ErrClosed", Var, 0, ""}, + {"ErrLineTooLong", Var, 0, ""}, + {"ErrPersistEOF", Var, 0, ""}, + {"ErrPipeline", Var, 0, ""}, + {"NewChunkedReader", Func, 0, "func(r io.Reader) io.Reader"}, + {"NewChunkedWriter", Func, 0, "func(w io.Writer) io.WriteCloser"}, + {"NewClientConn", Func, 0, "func(c net.Conn, r *bufio.Reader) *ClientConn"}, + {"NewProxyClientConn", Func, 0, "func(c net.Conn, r *bufio.Reader) *ClientConn"}, + {"NewServerConn", Func, 0, "func(c net.Conn, r *bufio.Reader) *ServerConn"}, + {"NewSingleHostReverseProxy", Func, 0, "func(target *url.URL) *ReverseProxy"}, + {"ProxyRequest", Type, 20, ""}, + {"ProxyRequest.In", Field, 20, ""}, + {"ProxyRequest.Out", Field, 20, ""}, + {"ReverseProxy", Type, 0, ""}, + {"ReverseProxy.BufferPool", Field, 6, ""}, + {"ReverseProxy.Director", Field, 0, ""}, + {"ReverseProxy.ErrorHandler", Field, 11, ""}, + {"ReverseProxy.ErrorLog", Field, 4, ""}, + {"ReverseProxy.FlushInterval", Field, 0, ""}, + {"ReverseProxy.ModifyResponse", Field, 8, ""}, + {"ReverseProxy.Rewrite", Field, 20, ""}, + {"ReverseProxy.Transport", Field, 0, ""}, + {"ServerConn", Type, 0, ""}, }, "net/http/pprof": { - {"Cmdline", Func, 0}, - {"Handler", Func, 0}, - {"Index", Func, 0}, - {"Profile", Func, 0}, - {"Symbol", Func, 0}, - {"Trace", Func, 5}, + {"Cmdline", Func, 0, "func(w http.ResponseWriter, r *http.Request)"}, + {"Handler", Func, 0, "func(name string) http.Handler"}, + {"Index", Func, 0, "func(w http.ResponseWriter, r *http.Request)"}, + {"Profile", Func, 0, "func(w http.ResponseWriter, r *http.Request)"}, + {"Symbol", Func, 0, "func(w http.ResponseWriter, r *http.Request)"}, + {"Trace", Func, 5, "func(w http.ResponseWriter, r *http.Request)"}, }, "net/mail": { - {"(*Address).String", Method, 0}, - {"(*AddressParser).Parse", Method, 5}, - {"(*AddressParser).ParseList", Method, 5}, - {"(Header).AddressList", Method, 0}, - {"(Header).Date", Method, 0}, - {"(Header).Get", Method, 0}, - {"Address", Type, 0}, - {"Address.Address", Field, 0}, - {"Address.Name", Field, 0}, - {"AddressParser", Type, 5}, - {"AddressParser.WordDecoder", Field, 5}, - {"ErrHeaderNotPresent", Var, 0}, - {"Header", Type, 0}, - {"Message", Type, 0}, - {"Message.Body", Field, 0}, - {"Message.Header", Field, 0}, - {"ParseAddress", Func, 1}, - {"ParseAddressList", Func, 1}, - {"ParseDate", Func, 8}, - {"ReadMessage", Func, 0}, + {"(*Address).String", Method, 0, ""}, + {"(*AddressParser).Parse", Method, 5, ""}, + {"(*AddressParser).ParseList", Method, 5, ""}, + {"(Header).AddressList", Method, 0, ""}, + {"(Header).Date", Method, 0, ""}, + {"(Header).Get", Method, 0, ""}, + {"Address", Type, 0, ""}, + {"Address.Address", Field, 0, ""}, + {"Address.Name", Field, 0, ""}, + {"AddressParser", Type, 5, ""}, + {"AddressParser.WordDecoder", Field, 5, ""}, + {"ErrHeaderNotPresent", Var, 0, ""}, + {"Header", Type, 0, ""}, + {"Message", Type, 0, ""}, + {"Message.Body", Field, 0, ""}, + {"Message.Header", Field, 0, ""}, + {"ParseAddress", Func, 1, "func(address string) (*Address, error)"}, + {"ParseAddressList", Func, 1, "func(list string) ([]*Address, error)"}, + {"ParseDate", Func, 8, "func(date string) (time.Time, error)"}, + {"ReadMessage", Func, 0, "func(r io.Reader) (msg *Message, err error)"}, }, "net/netip": { - {"(*Addr).UnmarshalBinary", Method, 18}, - {"(*Addr).UnmarshalText", Method, 18}, - {"(*AddrPort).UnmarshalBinary", Method, 18}, - {"(*AddrPort).UnmarshalText", Method, 18}, - {"(*Prefix).UnmarshalBinary", Method, 18}, - {"(*Prefix).UnmarshalText", Method, 18}, - {"(Addr).AppendBinary", Method, 24}, - {"(Addr).AppendText", Method, 24}, - {"(Addr).AppendTo", Method, 18}, - {"(Addr).As16", Method, 18}, - {"(Addr).As4", Method, 18}, - {"(Addr).AsSlice", Method, 18}, - {"(Addr).BitLen", Method, 18}, - {"(Addr).Compare", Method, 18}, - {"(Addr).Is4", Method, 18}, - {"(Addr).Is4In6", Method, 18}, - {"(Addr).Is6", Method, 18}, - {"(Addr).IsGlobalUnicast", Method, 18}, - {"(Addr).IsInterfaceLocalMulticast", Method, 18}, - {"(Addr).IsLinkLocalMulticast", Method, 18}, - {"(Addr).IsLinkLocalUnicast", Method, 18}, - {"(Addr).IsLoopback", Method, 18}, - {"(Addr).IsMulticast", Method, 18}, - {"(Addr).IsPrivate", Method, 18}, - {"(Addr).IsUnspecified", Method, 18}, - {"(Addr).IsValid", Method, 18}, - {"(Addr).Less", Method, 18}, - {"(Addr).MarshalBinary", Method, 18}, - {"(Addr).MarshalText", Method, 18}, - {"(Addr).Next", Method, 18}, - {"(Addr).Prefix", Method, 18}, - {"(Addr).Prev", Method, 18}, - {"(Addr).String", Method, 18}, - {"(Addr).StringExpanded", Method, 18}, - {"(Addr).Unmap", Method, 18}, - {"(Addr).WithZone", Method, 18}, - {"(Addr).Zone", Method, 18}, - {"(AddrPort).Addr", Method, 18}, - {"(AddrPort).AppendBinary", Method, 24}, - {"(AddrPort).AppendText", Method, 24}, - {"(AddrPort).AppendTo", Method, 18}, - {"(AddrPort).Compare", Method, 22}, - {"(AddrPort).IsValid", Method, 18}, - {"(AddrPort).MarshalBinary", Method, 18}, - {"(AddrPort).MarshalText", Method, 18}, - {"(AddrPort).Port", Method, 18}, - {"(AddrPort).String", Method, 18}, - {"(Prefix).Addr", Method, 18}, - {"(Prefix).AppendBinary", Method, 24}, - {"(Prefix).AppendText", Method, 24}, - {"(Prefix).AppendTo", Method, 18}, - {"(Prefix).Bits", Method, 18}, - {"(Prefix).Contains", Method, 18}, - {"(Prefix).IsSingleIP", Method, 18}, - {"(Prefix).IsValid", Method, 18}, - {"(Prefix).MarshalBinary", Method, 18}, - {"(Prefix).MarshalText", Method, 18}, - {"(Prefix).Masked", Method, 18}, - {"(Prefix).Overlaps", Method, 18}, - {"(Prefix).String", Method, 18}, - {"Addr", Type, 18}, - {"AddrFrom16", Func, 18}, - {"AddrFrom4", Func, 18}, - {"AddrFromSlice", Func, 18}, - {"AddrPort", Type, 18}, - {"AddrPortFrom", Func, 18}, - {"IPv4Unspecified", Func, 18}, - {"IPv6LinkLocalAllNodes", Func, 18}, - {"IPv6LinkLocalAllRouters", Func, 20}, - {"IPv6Loopback", Func, 20}, - {"IPv6Unspecified", Func, 18}, - {"MustParseAddr", Func, 18}, - {"MustParseAddrPort", Func, 18}, - {"MustParsePrefix", Func, 18}, - {"ParseAddr", Func, 18}, - {"ParseAddrPort", Func, 18}, - {"ParsePrefix", Func, 18}, - {"Prefix", Type, 18}, - {"PrefixFrom", Func, 18}, + {"(*Addr).UnmarshalBinary", Method, 18, ""}, + {"(*Addr).UnmarshalText", Method, 18, ""}, + {"(*AddrPort).UnmarshalBinary", Method, 18, ""}, + {"(*AddrPort).UnmarshalText", Method, 18, ""}, + {"(*Prefix).UnmarshalBinary", Method, 18, ""}, + {"(*Prefix).UnmarshalText", Method, 18, ""}, + {"(Addr).AppendBinary", Method, 24, ""}, + {"(Addr).AppendText", Method, 24, ""}, + {"(Addr).AppendTo", Method, 18, ""}, + {"(Addr).As16", Method, 18, ""}, + {"(Addr).As4", Method, 18, ""}, + {"(Addr).AsSlice", Method, 18, ""}, + {"(Addr).BitLen", Method, 18, ""}, + {"(Addr).Compare", Method, 18, ""}, + {"(Addr).Is4", Method, 18, ""}, + {"(Addr).Is4In6", Method, 18, ""}, + {"(Addr).Is6", Method, 18, ""}, + {"(Addr).IsGlobalUnicast", Method, 18, ""}, + {"(Addr).IsInterfaceLocalMulticast", Method, 18, ""}, + {"(Addr).IsLinkLocalMulticast", Method, 18, ""}, + {"(Addr).IsLinkLocalUnicast", Method, 18, ""}, + {"(Addr).IsLoopback", Method, 18, ""}, + {"(Addr).IsMulticast", Method, 18, ""}, + {"(Addr).IsPrivate", Method, 18, ""}, + {"(Addr).IsUnspecified", Method, 18, ""}, + {"(Addr).IsValid", Method, 18, ""}, + {"(Addr).Less", Method, 18, ""}, + {"(Addr).MarshalBinary", Method, 18, ""}, + {"(Addr).MarshalText", Method, 18, ""}, + {"(Addr).Next", Method, 18, ""}, + {"(Addr).Prefix", Method, 18, ""}, + {"(Addr).Prev", Method, 18, ""}, + {"(Addr).String", Method, 18, ""}, + {"(Addr).StringExpanded", Method, 18, ""}, + {"(Addr).Unmap", Method, 18, ""}, + {"(Addr).WithZone", Method, 18, ""}, + {"(Addr).Zone", Method, 18, ""}, + {"(AddrPort).Addr", Method, 18, ""}, + {"(AddrPort).AppendBinary", Method, 24, ""}, + {"(AddrPort).AppendText", Method, 24, ""}, + {"(AddrPort).AppendTo", Method, 18, ""}, + {"(AddrPort).Compare", Method, 22, ""}, + {"(AddrPort).IsValid", Method, 18, ""}, + {"(AddrPort).MarshalBinary", Method, 18, ""}, + {"(AddrPort).MarshalText", Method, 18, ""}, + {"(AddrPort).Port", Method, 18, ""}, + {"(AddrPort).String", Method, 18, ""}, + {"(Prefix).Addr", Method, 18, ""}, + {"(Prefix).AppendBinary", Method, 24, ""}, + {"(Prefix).AppendText", Method, 24, ""}, + {"(Prefix).AppendTo", Method, 18, ""}, + {"(Prefix).Bits", Method, 18, ""}, + {"(Prefix).Contains", Method, 18, ""}, + {"(Prefix).IsSingleIP", Method, 18, ""}, + {"(Prefix).IsValid", Method, 18, ""}, + {"(Prefix).MarshalBinary", Method, 18, ""}, + {"(Prefix).MarshalText", Method, 18, ""}, + {"(Prefix).Masked", Method, 18, ""}, + {"(Prefix).Overlaps", Method, 18, ""}, + {"(Prefix).String", Method, 18, ""}, + {"Addr", Type, 18, ""}, + {"AddrFrom16", Func, 18, "func(addr [16]byte) Addr"}, + {"AddrFrom4", Func, 18, "func(addr [4]byte) Addr"}, + {"AddrFromSlice", Func, 18, "func(slice []byte) (ip Addr, ok bool)"}, + {"AddrPort", Type, 18, ""}, + {"AddrPortFrom", Func, 18, "func(ip Addr, port uint16) AddrPort"}, + {"IPv4Unspecified", Func, 18, "func() Addr"}, + {"IPv6LinkLocalAllNodes", Func, 18, "func() Addr"}, + {"IPv6LinkLocalAllRouters", Func, 20, "func() Addr"}, + {"IPv6Loopback", Func, 20, "func() Addr"}, + {"IPv6Unspecified", Func, 18, "func() Addr"}, + {"MustParseAddr", Func, 18, "func(s string) Addr"}, + {"MustParseAddrPort", Func, 18, "func(s string) AddrPort"}, + {"MustParsePrefix", Func, 18, "func(s string) Prefix"}, + {"ParseAddr", Func, 18, "func(s string) (Addr, error)"}, + {"ParseAddrPort", Func, 18, "func(s string) (AddrPort, error)"}, + {"ParsePrefix", Func, 18, "func(s string) (Prefix, error)"}, + {"Prefix", Type, 18, ""}, + {"PrefixFrom", Func, 18, "func(ip Addr, bits int) Prefix"}, }, "net/rpc": { - {"(*Client).Call", Method, 0}, - {"(*Client).Close", Method, 0}, - {"(*Client).Go", Method, 0}, - {"(*Server).Accept", Method, 0}, - {"(*Server).HandleHTTP", Method, 0}, - {"(*Server).Register", Method, 0}, - {"(*Server).RegisterName", Method, 0}, - {"(*Server).ServeCodec", Method, 0}, - {"(*Server).ServeConn", Method, 0}, - {"(*Server).ServeHTTP", Method, 0}, - {"(*Server).ServeRequest", Method, 0}, - {"(ServerError).Error", Method, 0}, - {"Accept", Func, 0}, - {"Call", Type, 0}, - {"Call.Args", Field, 0}, - {"Call.Done", Field, 0}, - {"Call.Error", Field, 0}, - {"Call.Reply", Field, 0}, - {"Call.ServiceMethod", Field, 0}, - {"Client", Type, 0}, - {"ClientCodec", Type, 0}, - {"DefaultDebugPath", Const, 0}, - {"DefaultRPCPath", Const, 0}, - {"DefaultServer", Var, 0}, - {"Dial", Func, 0}, - {"DialHTTP", Func, 0}, - {"DialHTTPPath", Func, 0}, - {"ErrShutdown", Var, 0}, - {"HandleHTTP", Func, 0}, - {"NewClient", Func, 0}, - {"NewClientWithCodec", Func, 0}, - {"NewServer", Func, 0}, - {"Register", Func, 0}, - {"RegisterName", Func, 0}, - {"Request", Type, 0}, - {"Request.Seq", Field, 0}, - {"Request.ServiceMethod", Field, 0}, - {"Response", Type, 0}, - {"Response.Error", Field, 0}, - {"Response.Seq", Field, 0}, - {"Response.ServiceMethod", Field, 0}, - {"ServeCodec", Func, 0}, - {"ServeConn", Func, 0}, - {"ServeRequest", Func, 0}, - {"Server", Type, 0}, - {"ServerCodec", Type, 0}, - {"ServerError", Type, 0}, + {"(*Client).Call", Method, 0, ""}, + {"(*Client).Close", Method, 0, ""}, + {"(*Client).Go", Method, 0, ""}, + {"(*Server).Accept", Method, 0, ""}, + {"(*Server).HandleHTTP", Method, 0, ""}, + {"(*Server).Register", Method, 0, ""}, + {"(*Server).RegisterName", Method, 0, ""}, + {"(*Server).ServeCodec", Method, 0, ""}, + {"(*Server).ServeConn", Method, 0, ""}, + {"(*Server).ServeHTTP", Method, 0, ""}, + {"(*Server).ServeRequest", Method, 0, ""}, + {"(ServerError).Error", Method, 0, ""}, + {"Accept", Func, 0, "func(lis net.Listener)"}, + {"Call", Type, 0, ""}, + {"Call.Args", Field, 0, ""}, + {"Call.Done", Field, 0, ""}, + {"Call.Error", Field, 0, ""}, + {"Call.Reply", Field, 0, ""}, + {"Call.ServiceMethod", Field, 0, ""}, + {"Client", Type, 0, ""}, + {"ClientCodec", Type, 0, ""}, + {"DefaultDebugPath", Const, 0, ""}, + {"DefaultRPCPath", Const, 0, ""}, + {"DefaultServer", Var, 0, ""}, + {"Dial", Func, 0, "func(network string, address string) (*Client, error)"}, + {"DialHTTP", Func, 0, "func(network string, address string) (*Client, error)"}, + {"DialHTTPPath", Func, 0, "func(network string, address string, path string) (*Client, error)"}, + {"ErrShutdown", Var, 0, ""}, + {"HandleHTTP", Func, 0, "func()"}, + {"NewClient", Func, 0, "func(conn io.ReadWriteCloser) *Client"}, + {"NewClientWithCodec", Func, 0, "func(codec ClientCodec) *Client"}, + {"NewServer", Func, 0, "func() *Server"}, + {"Register", Func, 0, "func(rcvr any) error"}, + {"RegisterName", Func, 0, "func(name string, rcvr any) error"}, + {"Request", Type, 0, ""}, + {"Request.Seq", Field, 0, ""}, + {"Request.ServiceMethod", Field, 0, ""}, + {"Response", Type, 0, ""}, + {"Response.Error", Field, 0, ""}, + {"Response.Seq", Field, 0, ""}, + {"Response.ServiceMethod", Field, 0, ""}, + {"ServeCodec", Func, 0, "func(codec ServerCodec)"}, + {"ServeConn", Func, 0, "func(conn io.ReadWriteCloser)"}, + {"ServeRequest", Func, 0, "func(codec ServerCodec) error"}, + {"Server", Type, 0, ""}, + {"ServerCodec", Type, 0, ""}, + {"ServerError", Type, 0, ""}, }, "net/rpc/jsonrpc": { - {"Dial", Func, 0}, - {"NewClient", Func, 0}, - {"NewClientCodec", Func, 0}, - {"NewServerCodec", Func, 0}, - {"ServeConn", Func, 0}, + {"Dial", Func, 0, "func(network string, address string) (*rpc.Client, error)"}, + {"NewClient", Func, 0, "func(conn io.ReadWriteCloser) *rpc.Client"}, + {"NewClientCodec", Func, 0, "func(conn io.ReadWriteCloser) rpc.ClientCodec"}, + {"NewServerCodec", Func, 0, "func(conn io.ReadWriteCloser) rpc.ServerCodec"}, + {"ServeConn", Func, 0, "func(conn io.ReadWriteCloser)"}, }, "net/smtp": { - {"(*Client).Auth", Method, 0}, - {"(*Client).Close", Method, 2}, - {"(*Client).Data", Method, 0}, - {"(*Client).Extension", Method, 0}, - {"(*Client).Hello", Method, 1}, - {"(*Client).Mail", Method, 0}, - {"(*Client).Noop", Method, 10}, - {"(*Client).Quit", Method, 0}, - {"(*Client).Rcpt", Method, 0}, - {"(*Client).Reset", Method, 0}, - {"(*Client).StartTLS", Method, 0}, - {"(*Client).TLSConnectionState", Method, 5}, - {"(*Client).Verify", Method, 0}, - {"Auth", Type, 0}, - {"CRAMMD5Auth", Func, 0}, - {"Client", Type, 0}, - {"Client.Text", Field, 0}, - {"Dial", Func, 0}, - {"NewClient", Func, 0}, - {"PlainAuth", Func, 0}, - {"SendMail", Func, 0}, - {"ServerInfo", Type, 0}, - {"ServerInfo.Auth", Field, 0}, - {"ServerInfo.Name", Field, 0}, - {"ServerInfo.TLS", Field, 0}, + {"(*Client).Auth", Method, 0, ""}, + {"(*Client).Close", Method, 2, ""}, + {"(*Client).Data", Method, 0, ""}, + {"(*Client).Extension", Method, 0, ""}, + {"(*Client).Hello", Method, 1, ""}, + {"(*Client).Mail", Method, 0, ""}, + {"(*Client).Noop", Method, 10, ""}, + {"(*Client).Quit", Method, 0, ""}, + {"(*Client).Rcpt", Method, 0, ""}, + {"(*Client).Reset", Method, 0, ""}, + {"(*Client).StartTLS", Method, 0, ""}, + {"(*Client).TLSConnectionState", Method, 5, ""}, + {"(*Client).Verify", Method, 0, ""}, + {"Auth", Type, 0, ""}, + {"CRAMMD5Auth", Func, 0, "func(username string, secret string) Auth"}, + {"Client", Type, 0, ""}, + {"Client.Text", Field, 0, ""}, + {"Dial", Func, 0, "func(addr string) (*Client, error)"}, + {"NewClient", Func, 0, "func(conn net.Conn, host string) (*Client, error)"}, + {"PlainAuth", Func, 0, "func(identity string, username string, password string, host string) Auth"}, + {"SendMail", Func, 0, "func(addr string, a Auth, from string, to []string, msg []byte) error"}, + {"ServerInfo", Type, 0, ""}, + {"ServerInfo.Auth", Field, 0, ""}, + {"ServerInfo.Name", Field, 0, ""}, + {"ServerInfo.TLS", Field, 0, ""}, }, "net/textproto": { - {"(*Conn).Close", Method, 0}, - {"(*Conn).Cmd", Method, 0}, - {"(*Conn).DotReader", Method, 0}, - {"(*Conn).DotWriter", Method, 0}, - {"(*Conn).EndRequest", Method, 0}, - {"(*Conn).EndResponse", Method, 0}, - {"(*Conn).Next", Method, 0}, - {"(*Conn).PrintfLine", Method, 0}, - {"(*Conn).ReadCodeLine", Method, 0}, - {"(*Conn).ReadContinuedLine", Method, 0}, - {"(*Conn).ReadContinuedLineBytes", Method, 0}, - {"(*Conn).ReadDotBytes", Method, 0}, - {"(*Conn).ReadDotLines", Method, 0}, - {"(*Conn).ReadLine", Method, 0}, - {"(*Conn).ReadLineBytes", Method, 0}, - {"(*Conn).ReadMIMEHeader", Method, 0}, - {"(*Conn).ReadResponse", Method, 0}, - {"(*Conn).StartRequest", Method, 0}, - {"(*Conn).StartResponse", Method, 0}, - {"(*Error).Error", Method, 0}, - {"(*Pipeline).EndRequest", Method, 0}, - {"(*Pipeline).EndResponse", Method, 0}, - {"(*Pipeline).Next", Method, 0}, - {"(*Pipeline).StartRequest", Method, 0}, - {"(*Pipeline).StartResponse", Method, 0}, - {"(*Reader).DotReader", Method, 0}, - {"(*Reader).ReadCodeLine", Method, 0}, - {"(*Reader).ReadContinuedLine", Method, 0}, - {"(*Reader).ReadContinuedLineBytes", Method, 0}, - {"(*Reader).ReadDotBytes", Method, 0}, - {"(*Reader).ReadDotLines", Method, 0}, - {"(*Reader).ReadLine", Method, 0}, - {"(*Reader).ReadLineBytes", Method, 0}, - {"(*Reader).ReadMIMEHeader", Method, 0}, - {"(*Reader).ReadResponse", Method, 0}, - {"(*Writer).DotWriter", Method, 0}, - {"(*Writer).PrintfLine", Method, 0}, - {"(MIMEHeader).Add", Method, 0}, - {"(MIMEHeader).Del", Method, 0}, - {"(MIMEHeader).Get", Method, 0}, - {"(MIMEHeader).Set", Method, 0}, - {"(MIMEHeader).Values", Method, 14}, - {"(ProtocolError).Error", Method, 0}, - {"CanonicalMIMEHeaderKey", Func, 0}, - {"Conn", Type, 0}, - {"Conn.Pipeline", Field, 0}, - {"Conn.Reader", Field, 0}, - {"Conn.Writer", Field, 0}, - {"Dial", Func, 0}, - {"Error", Type, 0}, - {"Error.Code", Field, 0}, - {"Error.Msg", Field, 0}, - {"MIMEHeader", Type, 0}, - {"NewConn", Func, 0}, - {"NewReader", Func, 0}, - {"NewWriter", Func, 0}, - {"Pipeline", Type, 0}, - {"ProtocolError", Type, 0}, - {"Reader", Type, 0}, - {"Reader.R", Field, 0}, - {"TrimBytes", Func, 1}, - {"TrimString", Func, 1}, - {"Writer", Type, 0}, - {"Writer.W", Field, 0}, + {"(*Conn).Close", Method, 0, ""}, + {"(*Conn).Cmd", Method, 0, ""}, + {"(*Conn).DotReader", Method, 0, ""}, + {"(*Conn).DotWriter", Method, 0, ""}, + {"(*Conn).EndRequest", Method, 0, ""}, + {"(*Conn).EndResponse", Method, 0, ""}, + {"(*Conn).Next", Method, 0, ""}, + {"(*Conn).PrintfLine", Method, 0, ""}, + {"(*Conn).ReadCodeLine", Method, 0, ""}, + {"(*Conn).ReadContinuedLine", Method, 0, ""}, + {"(*Conn).ReadContinuedLineBytes", Method, 0, ""}, + {"(*Conn).ReadDotBytes", Method, 0, ""}, + {"(*Conn).ReadDotLines", Method, 0, ""}, + {"(*Conn).ReadLine", Method, 0, ""}, + {"(*Conn).ReadLineBytes", Method, 0, ""}, + {"(*Conn).ReadMIMEHeader", Method, 0, ""}, + {"(*Conn).ReadResponse", Method, 0, ""}, + {"(*Conn).StartRequest", Method, 0, ""}, + {"(*Conn).StartResponse", Method, 0, ""}, + {"(*Error).Error", Method, 0, ""}, + {"(*Pipeline).EndRequest", Method, 0, ""}, + {"(*Pipeline).EndResponse", Method, 0, ""}, + {"(*Pipeline).Next", Method, 0, ""}, + {"(*Pipeline).StartRequest", Method, 0, ""}, + {"(*Pipeline).StartResponse", Method, 0, ""}, + {"(*Reader).DotReader", Method, 0, ""}, + {"(*Reader).ReadCodeLine", Method, 0, ""}, + {"(*Reader).ReadContinuedLine", Method, 0, ""}, + {"(*Reader).ReadContinuedLineBytes", Method, 0, ""}, + {"(*Reader).ReadDotBytes", Method, 0, ""}, + {"(*Reader).ReadDotLines", Method, 0, ""}, + {"(*Reader).ReadLine", Method, 0, ""}, + {"(*Reader).ReadLineBytes", Method, 0, ""}, + {"(*Reader).ReadMIMEHeader", Method, 0, ""}, + {"(*Reader).ReadResponse", Method, 0, ""}, + {"(*Writer).DotWriter", Method, 0, ""}, + {"(*Writer).PrintfLine", Method, 0, ""}, + {"(MIMEHeader).Add", Method, 0, ""}, + {"(MIMEHeader).Del", Method, 0, ""}, + {"(MIMEHeader).Get", Method, 0, ""}, + {"(MIMEHeader).Set", Method, 0, ""}, + {"(MIMEHeader).Values", Method, 14, ""}, + {"(ProtocolError).Error", Method, 0, ""}, + {"CanonicalMIMEHeaderKey", Func, 0, "func(s string) string"}, + {"Conn", Type, 0, ""}, + {"Conn.Pipeline", Field, 0, ""}, + {"Conn.Reader", Field, 0, ""}, + {"Conn.Writer", Field, 0, ""}, + {"Dial", Func, 0, "func(network string, addr string) (*Conn, error)"}, + {"Error", Type, 0, ""}, + {"Error.Code", Field, 0, ""}, + {"Error.Msg", Field, 0, ""}, + {"MIMEHeader", Type, 0, ""}, + {"NewConn", Func, 0, "func(conn io.ReadWriteCloser) *Conn"}, + {"NewReader", Func, 0, "func(r *bufio.Reader) *Reader"}, + {"NewWriter", Func, 0, "func(w *bufio.Writer) *Writer"}, + {"Pipeline", Type, 0, ""}, + {"ProtocolError", Type, 0, ""}, + {"Reader", Type, 0, ""}, + {"Reader.R", Field, 0, ""}, + {"TrimBytes", Func, 1, "func(b []byte) []byte"}, + {"TrimString", Func, 1, "func(s string) string"}, + {"Writer", Type, 0, ""}, + {"Writer.W", Field, 0, ""}, }, "net/url": { - {"(*Error).Error", Method, 0}, - {"(*Error).Temporary", Method, 6}, - {"(*Error).Timeout", Method, 6}, - {"(*Error).Unwrap", Method, 13}, - {"(*URL).AppendBinary", Method, 24}, - {"(*URL).EscapedFragment", Method, 15}, - {"(*URL).EscapedPath", Method, 5}, - {"(*URL).Hostname", Method, 8}, - {"(*URL).IsAbs", Method, 0}, - {"(*URL).JoinPath", Method, 19}, - {"(*URL).MarshalBinary", Method, 8}, - {"(*URL).Parse", Method, 0}, - {"(*URL).Port", Method, 8}, - {"(*URL).Query", Method, 0}, - {"(*URL).Redacted", Method, 15}, - {"(*URL).RequestURI", Method, 0}, - {"(*URL).ResolveReference", Method, 0}, - {"(*URL).String", Method, 0}, - {"(*URL).UnmarshalBinary", Method, 8}, - {"(*Userinfo).Password", Method, 0}, - {"(*Userinfo).String", Method, 0}, - {"(*Userinfo).Username", Method, 0}, - {"(EscapeError).Error", Method, 0}, - {"(InvalidHostError).Error", Method, 6}, - {"(Values).Add", Method, 0}, - {"(Values).Del", Method, 0}, - {"(Values).Encode", Method, 0}, - {"(Values).Get", Method, 0}, - {"(Values).Has", Method, 17}, - {"(Values).Set", Method, 0}, - {"Error", Type, 0}, - {"Error.Err", Field, 0}, - {"Error.Op", Field, 0}, - {"Error.URL", Field, 0}, - {"EscapeError", Type, 0}, - {"InvalidHostError", Type, 6}, - {"JoinPath", Func, 19}, - {"Parse", Func, 0}, - {"ParseQuery", Func, 0}, - {"ParseRequestURI", Func, 0}, - {"PathEscape", Func, 8}, - {"PathUnescape", Func, 8}, - {"QueryEscape", Func, 0}, - {"QueryUnescape", Func, 0}, - {"URL", Type, 0}, - {"URL.ForceQuery", Field, 7}, - {"URL.Fragment", Field, 0}, - {"URL.Host", Field, 0}, - {"URL.OmitHost", Field, 19}, - {"URL.Opaque", Field, 0}, - {"URL.Path", Field, 0}, - {"URL.RawFragment", Field, 15}, - {"URL.RawPath", Field, 5}, - {"URL.RawQuery", Field, 0}, - {"URL.Scheme", Field, 0}, - {"URL.User", Field, 0}, - {"User", Func, 0}, - {"UserPassword", Func, 0}, - {"Userinfo", Type, 0}, - {"Values", Type, 0}, + {"(*Error).Error", Method, 0, ""}, + {"(*Error).Temporary", Method, 6, ""}, + {"(*Error).Timeout", Method, 6, ""}, + {"(*Error).Unwrap", Method, 13, ""}, + {"(*URL).AppendBinary", Method, 24, ""}, + {"(*URL).EscapedFragment", Method, 15, ""}, + {"(*URL).EscapedPath", Method, 5, ""}, + {"(*URL).Hostname", Method, 8, ""}, + {"(*URL).IsAbs", Method, 0, ""}, + {"(*URL).JoinPath", Method, 19, ""}, + {"(*URL).MarshalBinary", Method, 8, ""}, + {"(*URL).Parse", Method, 0, ""}, + {"(*URL).Port", Method, 8, ""}, + {"(*URL).Query", Method, 0, ""}, + {"(*URL).Redacted", Method, 15, ""}, + {"(*URL).RequestURI", Method, 0, ""}, + {"(*URL).ResolveReference", Method, 0, ""}, + {"(*URL).String", Method, 0, ""}, + {"(*URL).UnmarshalBinary", Method, 8, ""}, + {"(*Userinfo).Password", Method, 0, ""}, + {"(*Userinfo).String", Method, 0, ""}, + {"(*Userinfo).Username", Method, 0, ""}, + {"(EscapeError).Error", Method, 0, ""}, + {"(InvalidHostError).Error", Method, 6, ""}, + {"(Values).Add", Method, 0, ""}, + {"(Values).Del", Method, 0, ""}, + {"(Values).Encode", Method, 0, ""}, + {"(Values).Get", Method, 0, ""}, + {"(Values).Has", Method, 17, ""}, + {"(Values).Set", Method, 0, ""}, + {"Error", Type, 0, ""}, + {"Error.Err", Field, 0, ""}, + {"Error.Op", Field, 0, ""}, + {"Error.URL", Field, 0, ""}, + {"EscapeError", Type, 0, ""}, + {"InvalidHostError", Type, 6, ""}, + {"JoinPath", Func, 19, "func(base string, elem ...string) (result string, err error)"}, + {"Parse", Func, 0, "func(rawURL string) (*URL, error)"}, + {"ParseQuery", Func, 0, "func(query string) (Values, error)"}, + {"ParseRequestURI", Func, 0, "func(rawURL string) (*URL, error)"}, + {"PathEscape", Func, 8, "func(s string) string"}, + {"PathUnescape", Func, 8, "func(s string) (string, error)"}, + {"QueryEscape", Func, 0, "func(s string) string"}, + {"QueryUnescape", Func, 0, "func(s string) (string, error)"}, + {"URL", Type, 0, ""}, + {"URL.ForceQuery", Field, 7, ""}, + {"URL.Fragment", Field, 0, ""}, + {"URL.Host", Field, 0, ""}, + {"URL.OmitHost", Field, 19, ""}, + {"URL.Opaque", Field, 0, ""}, + {"URL.Path", Field, 0, ""}, + {"URL.RawFragment", Field, 15, ""}, + {"URL.RawPath", Field, 5, ""}, + {"URL.RawQuery", Field, 0, ""}, + {"URL.Scheme", Field, 0, ""}, + {"URL.User", Field, 0, ""}, + {"User", Func, 0, "func(username string) *Userinfo"}, + {"UserPassword", Func, 0, "func(username string, password string) *Userinfo"}, + {"Userinfo", Type, 0, ""}, + {"Values", Type, 0, ""}, }, "os": { - {"(*File).Chdir", Method, 0}, - {"(*File).Chmod", Method, 0}, - {"(*File).Chown", Method, 0}, - {"(*File).Close", Method, 0}, - {"(*File).Fd", Method, 0}, - {"(*File).Name", Method, 0}, - {"(*File).Read", Method, 0}, - {"(*File).ReadAt", Method, 0}, - {"(*File).ReadDir", Method, 16}, - {"(*File).ReadFrom", Method, 15}, - {"(*File).Readdir", Method, 0}, - {"(*File).Readdirnames", Method, 0}, - {"(*File).Seek", Method, 0}, - {"(*File).SetDeadline", Method, 10}, - {"(*File).SetReadDeadline", Method, 10}, - {"(*File).SetWriteDeadline", Method, 10}, - {"(*File).Stat", Method, 0}, - {"(*File).Sync", Method, 0}, - {"(*File).SyscallConn", Method, 12}, - {"(*File).Truncate", Method, 0}, - {"(*File).Write", Method, 0}, - {"(*File).WriteAt", Method, 0}, - {"(*File).WriteString", Method, 0}, - {"(*File).WriteTo", Method, 22}, - {"(*LinkError).Error", Method, 0}, - {"(*LinkError).Unwrap", Method, 13}, - {"(*PathError).Error", Method, 0}, - {"(*PathError).Timeout", Method, 10}, - {"(*PathError).Unwrap", Method, 13}, - {"(*Process).Kill", Method, 0}, - {"(*Process).Release", Method, 0}, - {"(*Process).Signal", Method, 0}, - {"(*Process).Wait", Method, 0}, - {"(*ProcessState).ExitCode", Method, 12}, - {"(*ProcessState).Exited", Method, 0}, - {"(*ProcessState).Pid", Method, 0}, - {"(*ProcessState).String", Method, 0}, - {"(*ProcessState).Success", Method, 0}, - {"(*ProcessState).Sys", Method, 0}, - {"(*ProcessState).SysUsage", Method, 0}, - {"(*ProcessState).SystemTime", Method, 0}, - {"(*ProcessState).UserTime", Method, 0}, - {"(*Root).Chmod", Method, 25}, - {"(*Root).Chown", Method, 25}, - {"(*Root).Chtimes", Method, 25}, - {"(*Root).Close", Method, 24}, - {"(*Root).Create", Method, 24}, - {"(*Root).FS", Method, 24}, - {"(*Root).Lchown", Method, 25}, - {"(*Root).Link", Method, 25}, - {"(*Root).Lstat", Method, 24}, - {"(*Root).Mkdir", Method, 24}, - {"(*Root).Name", Method, 24}, - {"(*Root).Open", Method, 24}, - {"(*Root).OpenFile", Method, 24}, - {"(*Root).OpenRoot", Method, 24}, - {"(*Root).Readlink", Method, 25}, - {"(*Root).Remove", Method, 24}, - {"(*Root).Rename", Method, 25}, - {"(*Root).Stat", Method, 24}, - {"(*Root).Symlink", Method, 25}, - {"(*SyscallError).Error", Method, 0}, - {"(*SyscallError).Timeout", Method, 10}, - {"(*SyscallError).Unwrap", Method, 13}, - {"(FileMode).IsDir", Method, 0}, - {"(FileMode).IsRegular", Method, 1}, - {"(FileMode).Perm", Method, 0}, - {"(FileMode).String", Method, 0}, - {"Args", Var, 0}, - {"Chdir", Func, 0}, - {"Chmod", Func, 0}, - {"Chown", Func, 0}, - {"Chtimes", Func, 0}, - {"Clearenv", Func, 0}, - {"CopyFS", Func, 23}, - {"Create", Func, 0}, - {"CreateTemp", Func, 16}, - {"DevNull", Const, 0}, - {"DirEntry", Type, 16}, - {"DirFS", Func, 16}, - {"Environ", Func, 0}, - {"ErrClosed", Var, 8}, - {"ErrDeadlineExceeded", Var, 15}, - {"ErrExist", Var, 0}, - {"ErrInvalid", Var, 0}, - {"ErrNoDeadline", Var, 10}, - {"ErrNotExist", Var, 0}, - {"ErrPermission", Var, 0}, - {"ErrProcessDone", Var, 16}, - {"Executable", Func, 8}, - {"Exit", Func, 0}, - {"Expand", Func, 0}, - {"ExpandEnv", Func, 0}, - {"File", Type, 0}, - {"FileInfo", Type, 0}, - {"FileMode", Type, 0}, - {"FindProcess", Func, 0}, - {"Getegid", Func, 0}, - {"Getenv", Func, 0}, - {"Geteuid", Func, 0}, - {"Getgid", Func, 0}, - {"Getgroups", Func, 0}, - {"Getpagesize", Func, 0}, - {"Getpid", Func, 0}, - {"Getppid", Func, 0}, - {"Getuid", Func, 0}, - {"Getwd", Func, 0}, - {"Hostname", Func, 0}, - {"Interrupt", Var, 0}, - {"IsExist", Func, 0}, - {"IsNotExist", Func, 0}, - {"IsPathSeparator", Func, 0}, - {"IsPermission", Func, 0}, - {"IsTimeout", Func, 10}, - {"Kill", Var, 0}, - {"Lchown", Func, 0}, - {"Link", Func, 0}, - {"LinkError", Type, 0}, - {"LinkError.Err", Field, 0}, - {"LinkError.New", Field, 0}, - {"LinkError.Old", Field, 0}, - {"LinkError.Op", Field, 0}, - {"LookupEnv", Func, 5}, - {"Lstat", Func, 0}, - {"Mkdir", Func, 0}, - {"MkdirAll", Func, 0}, - {"MkdirTemp", Func, 16}, - {"ModeAppend", Const, 0}, - {"ModeCharDevice", Const, 0}, - {"ModeDevice", Const, 0}, - {"ModeDir", Const, 0}, - {"ModeExclusive", Const, 0}, - {"ModeIrregular", Const, 11}, - {"ModeNamedPipe", Const, 0}, - {"ModePerm", Const, 0}, - {"ModeSetgid", Const, 0}, - {"ModeSetuid", Const, 0}, - {"ModeSocket", Const, 0}, - {"ModeSticky", Const, 0}, - {"ModeSymlink", Const, 0}, - {"ModeTemporary", Const, 0}, - {"ModeType", Const, 0}, - {"NewFile", Func, 0}, - {"NewSyscallError", Func, 0}, - {"O_APPEND", Const, 0}, - {"O_CREATE", Const, 0}, - {"O_EXCL", Const, 0}, - {"O_RDONLY", Const, 0}, - {"O_RDWR", Const, 0}, - {"O_SYNC", Const, 0}, - {"O_TRUNC", Const, 0}, - {"O_WRONLY", Const, 0}, - {"Open", Func, 0}, - {"OpenFile", Func, 0}, - {"OpenInRoot", Func, 24}, - {"OpenRoot", Func, 24}, - {"PathError", Type, 0}, - {"PathError.Err", Field, 0}, - {"PathError.Op", Field, 0}, - {"PathError.Path", Field, 0}, - {"PathListSeparator", Const, 0}, - {"PathSeparator", Const, 0}, - {"Pipe", Func, 0}, - {"ProcAttr", Type, 0}, - {"ProcAttr.Dir", Field, 0}, - {"ProcAttr.Env", Field, 0}, - {"ProcAttr.Files", Field, 0}, - {"ProcAttr.Sys", Field, 0}, - {"Process", Type, 0}, - {"Process.Pid", Field, 0}, - {"ProcessState", Type, 0}, - {"ReadDir", Func, 16}, - {"ReadFile", Func, 16}, - {"Readlink", Func, 0}, - {"Remove", Func, 0}, - {"RemoveAll", Func, 0}, - {"Rename", Func, 0}, - {"Root", Type, 24}, - {"SEEK_CUR", Const, 0}, - {"SEEK_END", Const, 0}, - {"SEEK_SET", Const, 0}, - {"SameFile", Func, 0}, - {"Setenv", Func, 0}, - {"Signal", Type, 0}, - {"StartProcess", Func, 0}, - {"Stat", Func, 0}, - {"Stderr", Var, 0}, - {"Stdin", Var, 0}, - {"Stdout", Var, 0}, - {"Symlink", Func, 0}, - {"SyscallError", Type, 0}, - {"SyscallError.Err", Field, 0}, - {"SyscallError.Syscall", Field, 0}, - {"TempDir", Func, 0}, - {"Truncate", Func, 0}, - {"Unsetenv", Func, 4}, - {"UserCacheDir", Func, 11}, - {"UserConfigDir", Func, 13}, - {"UserHomeDir", Func, 12}, - {"WriteFile", Func, 16}, + {"(*File).Chdir", Method, 0, ""}, + {"(*File).Chmod", Method, 0, ""}, + {"(*File).Chown", Method, 0, ""}, + {"(*File).Close", Method, 0, ""}, + {"(*File).Fd", Method, 0, ""}, + {"(*File).Name", Method, 0, ""}, + {"(*File).Read", Method, 0, ""}, + {"(*File).ReadAt", Method, 0, ""}, + {"(*File).ReadDir", Method, 16, ""}, + {"(*File).ReadFrom", Method, 15, ""}, + {"(*File).Readdir", Method, 0, ""}, + {"(*File).Readdirnames", Method, 0, ""}, + {"(*File).Seek", Method, 0, ""}, + {"(*File).SetDeadline", Method, 10, ""}, + {"(*File).SetReadDeadline", Method, 10, ""}, + {"(*File).SetWriteDeadline", Method, 10, ""}, + {"(*File).Stat", Method, 0, ""}, + {"(*File).Sync", Method, 0, ""}, + {"(*File).SyscallConn", Method, 12, ""}, + {"(*File).Truncate", Method, 0, ""}, + {"(*File).Write", Method, 0, ""}, + {"(*File).WriteAt", Method, 0, ""}, + {"(*File).WriteString", Method, 0, ""}, + {"(*File).WriteTo", Method, 22, ""}, + {"(*LinkError).Error", Method, 0, ""}, + {"(*LinkError).Unwrap", Method, 13, ""}, + {"(*PathError).Error", Method, 0, ""}, + {"(*PathError).Timeout", Method, 10, ""}, + {"(*PathError).Unwrap", Method, 13, ""}, + {"(*Process).Kill", Method, 0, ""}, + {"(*Process).Release", Method, 0, ""}, + {"(*Process).Signal", Method, 0, ""}, + {"(*Process).Wait", Method, 0, ""}, + {"(*ProcessState).ExitCode", Method, 12, ""}, + {"(*ProcessState).Exited", Method, 0, ""}, + {"(*ProcessState).Pid", Method, 0, ""}, + {"(*ProcessState).String", Method, 0, ""}, + {"(*ProcessState).Success", Method, 0, ""}, + {"(*ProcessState).Sys", Method, 0, ""}, + {"(*ProcessState).SysUsage", Method, 0, ""}, + {"(*ProcessState).SystemTime", Method, 0, ""}, + {"(*ProcessState).UserTime", Method, 0, ""}, + {"(*Root).Chmod", Method, 25, ""}, + {"(*Root).Chown", Method, 25, ""}, + {"(*Root).Chtimes", Method, 25, ""}, + {"(*Root).Close", Method, 24, ""}, + {"(*Root).Create", Method, 24, ""}, + {"(*Root).FS", Method, 24, ""}, + {"(*Root).Lchown", Method, 25, ""}, + {"(*Root).Link", Method, 25, ""}, + {"(*Root).Lstat", Method, 24, ""}, + {"(*Root).Mkdir", Method, 24, ""}, + {"(*Root).Name", Method, 24, ""}, + {"(*Root).Open", Method, 24, ""}, + {"(*Root).OpenFile", Method, 24, ""}, + {"(*Root).OpenRoot", Method, 24, ""}, + {"(*Root).Readlink", Method, 25, ""}, + {"(*Root).Remove", Method, 24, ""}, + {"(*Root).Rename", Method, 25, ""}, + {"(*Root).Stat", Method, 24, ""}, + {"(*Root).Symlink", Method, 25, ""}, + {"(*SyscallError).Error", Method, 0, ""}, + {"(*SyscallError).Timeout", Method, 10, ""}, + {"(*SyscallError).Unwrap", Method, 13, ""}, + {"(FileMode).IsDir", Method, 0, ""}, + {"(FileMode).IsRegular", Method, 1, ""}, + {"(FileMode).Perm", Method, 0, ""}, + {"(FileMode).String", Method, 0, ""}, + {"Args", Var, 0, ""}, + {"Chdir", Func, 0, "func(dir string) error"}, + {"Chmod", Func, 0, "func(name string, mode FileMode) error"}, + {"Chown", Func, 0, "func(name string, uid int, gid int) error"}, + {"Chtimes", Func, 0, "func(name string, atime time.Time, mtime time.Time) error"}, + {"Clearenv", Func, 0, "func()"}, + {"CopyFS", Func, 23, "func(dir string, fsys fs.FS) error"}, + {"Create", Func, 0, "func(name string) (*File, error)"}, + {"CreateTemp", Func, 16, "func(dir string, pattern string) (*File, error)"}, + {"DevNull", Const, 0, ""}, + {"DirEntry", Type, 16, ""}, + {"DirFS", Func, 16, "func(dir string) fs.FS"}, + {"Environ", Func, 0, "func() []string"}, + {"ErrClosed", Var, 8, ""}, + {"ErrDeadlineExceeded", Var, 15, ""}, + {"ErrExist", Var, 0, ""}, + {"ErrInvalid", Var, 0, ""}, + {"ErrNoDeadline", Var, 10, ""}, + {"ErrNotExist", Var, 0, ""}, + {"ErrPermission", Var, 0, ""}, + {"ErrProcessDone", Var, 16, ""}, + {"Executable", Func, 8, "func() (string, error)"}, + {"Exit", Func, 0, "func(code int)"}, + {"Expand", Func, 0, "func(s string, mapping func(string) string) string"}, + {"ExpandEnv", Func, 0, "func(s string) string"}, + {"File", Type, 0, ""}, + {"FileInfo", Type, 0, ""}, + {"FileMode", Type, 0, ""}, + {"FindProcess", Func, 0, "func(pid int) (*Process, error)"}, + {"Getegid", Func, 0, "func() int"}, + {"Getenv", Func, 0, "func(key string) string"}, + {"Geteuid", Func, 0, "func() int"}, + {"Getgid", Func, 0, "func() int"}, + {"Getgroups", Func, 0, "func() ([]int, error)"}, + {"Getpagesize", Func, 0, "func() int"}, + {"Getpid", Func, 0, "func() int"}, + {"Getppid", Func, 0, "func() int"}, + {"Getuid", Func, 0, "func() int"}, + {"Getwd", Func, 0, "func() (dir string, err error)"}, + {"Hostname", Func, 0, "func() (name string, err error)"}, + {"Interrupt", Var, 0, ""}, + {"IsExist", Func, 0, "func(err error) bool"}, + {"IsNotExist", Func, 0, "func(err error) bool"}, + {"IsPathSeparator", Func, 0, "func(c uint8) bool"}, + {"IsPermission", Func, 0, "func(err error) bool"}, + {"IsTimeout", Func, 10, "func(err error) bool"}, + {"Kill", Var, 0, ""}, + {"Lchown", Func, 0, "func(name string, uid int, gid int) error"}, + {"Link", Func, 0, "func(oldname string, newname string) error"}, + {"LinkError", Type, 0, ""}, + {"LinkError.Err", Field, 0, ""}, + {"LinkError.New", Field, 0, ""}, + {"LinkError.Old", Field, 0, ""}, + {"LinkError.Op", Field, 0, ""}, + {"LookupEnv", Func, 5, "func(key string) (string, bool)"}, + {"Lstat", Func, 0, "func(name string) (FileInfo, error)"}, + {"Mkdir", Func, 0, "func(name string, perm FileMode) error"}, + {"MkdirAll", Func, 0, "func(path string, perm FileMode) error"}, + {"MkdirTemp", Func, 16, "func(dir string, pattern string) (string, error)"}, + {"ModeAppend", Const, 0, ""}, + {"ModeCharDevice", Const, 0, ""}, + {"ModeDevice", Const, 0, ""}, + {"ModeDir", Const, 0, ""}, + {"ModeExclusive", Const, 0, ""}, + {"ModeIrregular", Const, 11, ""}, + {"ModeNamedPipe", Const, 0, ""}, + {"ModePerm", Const, 0, ""}, + {"ModeSetgid", Const, 0, ""}, + {"ModeSetuid", Const, 0, ""}, + {"ModeSocket", Const, 0, ""}, + {"ModeSticky", Const, 0, ""}, + {"ModeSymlink", Const, 0, ""}, + {"ModeTemporary", Const, 0, ""}, + {"ModeType", Const, 0, ""}, + {"NewFile", Func, 0, "func(fd uintptr, name string) *File"}, + {"NewSyscallError", Func, 0, "func(syscall string, err error) error"}, + {"O_APPEND", Const, 0, ""}, + {"O_CREATE", Const, 0, ""}, + {"O_EXCL", Const, 0, ""}, + {"O_RDONLY", Const, 0, ""}, + {"O_RDWR", Const, 0, ""}, + {"O_SYNC", Const, 0, ""}, + {"O_TRUNC", Const, 0, ""}, + {"O_WRONLY", Const, 0, ""}, + {"Open", Func, 0, "func(name string) (*File, error)"}, + {"OpenFile", Func, 0, "func(name string, flag int, perm FileMode) (*File, error)"}, + {"OpenInRoot", Func, 24, "func(dir string, name string) (*File, error)"}, + {"OpenRoot", Func, 24, "func(name string) (*Root, error)"}, + {"PathError", Type, 0, ""}, + {"PathError.Err", Field, 0, ""}, + {"PathError.Op", Field, 0, ""}, + {"PathError.Path", Field, 0, ""}, + {"PathListSeparator", Const, 0, ""}, + {"PathSeparator", Const, 0, ""}, + {"Pipe", Func, 0, "func() (r *File, w *File, err error)"}, + {"ProcAttr", Type, 0, ""}, + {"ProcAttr.Dir", Field, 0, ""}, + {"ProcAttr.Env", Field, 0, ""}, + {"ProcAttr.Files", Field, 0, ""}, + {"ProcAttr.Sys", Field, 0, ""}, + {"Process", Type, 0, ""}, + {"Process.Pid", Field, 0, ""}, + {"ProcessState", Type, 0, ""}, + {"ReadDir", Func, 16, "func(name string) ([]DirEntry, error)"}, + {"ReadFile", Func, 16, "func(name string) ([]byte, error)"}, + {"Readlink", Func, 0, "func(name string) (string, error)"}, + {"Remove", Func, 0, "func(name string) error"}, + {"RemoveAll", Func, 0, "func(path string) error"}, + {"Rename", Func, 0, "func(oldpath string, newpath string) error"}, + {"Root", Type, 24, ""}, + {"SEEK_CUR", Const, 0, ""}, + {"SEEK_END", Const, 0, ""}, + {"SEEK_SET", Const, 0, ""}, + {"SameFile", Func, 0, "func(fi1 FileInfo, fi2 FileInfo) bool"}, + {"Setenv", Func, 0, "func(key string, value string) error"}, + {"Signal", Type, 0, ""}, + {"StartProcess", Func, 0, "func(name string, argv []string, attr *ProcAttr) (*Process, error)"}, + {"Stat", Func, 0, "func(name string) (FileInfo, error)"}, + {"Stderr", Var, 0, ""}, + {"Stdin", Var, 0, ""}, + {"Stdout", Var, 0, ""}, + {"Symlink", Func, 0, "func(oldname string, newname string) error"}, + {"SyscallError", Type, 0, ""}, + {"SyscallError.Err", Field, 0, ""}, + {"SyscallError.Syscall", Field, 0, ""}, + {"TempDir", Func, 0, "func() string"}, + {"Truncate", Func, 0, "func(name string, size int64) error"}, + {"Unsetenv", Func, 4, "func(key string) error"}, + {"UserCacheDir", Func, 11, "func() (string, error)"}, + {"UserConfigDir", Func, 13, "func() (string, error)"}, + {"UserHomeDir", Func, 12, "func() (string, error)"}, + {"WriteFile", Func, 16, "func(name string, data []byte, perm FileMode) error"}, }, "os/exec": { - {"(*Cmd).CombinedOutput", Method, 0}, - {"(*Cmd).Environ", Method, 19}, - {"(*Cmd).Output", Method, 0}, - {"(*Cmd).Run", Method, 0}, - {"(*Cmd).Start", Method, 0}, - {"(*Cmd).StderrPipe", Method, 0}, - {"(*Cmd).StdinPipe", Method, 0}, - {"(*Cmd).StdoutPipe", Method, 0}, - {"(*Cmd).String", Method, 13}, - {"(*Cmd).Wait", Method, 0}, - {"(*Error).Error", Method, 0}, - {"(*Error).Unwrap", Method, 13}, - {"(*ExitError).Error", Method, 0}, - {"(ExitError).ExitCode", Method, 12}, - {"(ExitError).Exited", Method, 0}, - {"(ExitError).Pid", Method, 0}, - {"(ExitError).String", Method, 0}, - {"(ExitError).Success", Method, 0}, - {"(ExitError).Sys", Method, 0}, - {"(ExitError).SysUsage", Method, 0}, - {"(ExitError).SystemTime", Method, 0}, - {"(ExitError).UserTime", Method, 0}, - {"Cmd", Type, 0}, - {"Cmd.Args", Field, 0}, - {"Cmd.Cancel", Field, 20}, - {"Cmd.Dir", Field, 0}, - {"Cmd.Env", Field, 0}, - {"Cmd.Err", Field, 19}, - {"Cmd.ExtraFiles", Field, 0}, - {"Cmd.Path", Field, 0}, - {"Cmd.Process", Field, 0}, - {"Cmd.ProcessState", Field, 0}, - {"Cmd.Stderr", Field, 0}, - {"Cmd.Stdin", Field, 0}, - {"Cmd.Stdout", Field, 0}, - {"Cmd.SysProcAttr", Field, 0}, - {"Cmd.WaitDelay", Field, 20}, - {"Command", Func, 0}, - {"CommandContext", Func, 7}, - {"ErrDot", Var, 19}, - {"ErrNotFound", Var, 0}, - {"ErrWaitDelay", Var, 20}, - {"Error", Type, 0}, - {"Error.Err", Field, 0}, - {"Error.Name", Field, 0}, - {"ExitError", Type, 0}, - {"ExitError.ProcessState", Field, 0}, - {"ExitError.Stderr", Field, 6}, - {"LookPath", Func, 0}, + {"(*Cmd).CombinedOutput", Method, 0, ""}, + {"(*Cmd).Environ", Method, 19, ""}, + {"(*Cmd).Output", Method, 0, ""}, + {"(*Cmd).Run", Method, 0, ""}, + {"(*Cmd).Start", Method, 0, ""}, + {"(*Cmd).StderrPipe", Method, 0, ""}, + {"(*Cmd).StdinPipe", Method, 0, ""}, + {"(*Cmd).StdoutPipe", Method, 0, ""}, + {"(*Cmd).String", Method, 13, ""}, + {"(*Cmd).Wait", Method, 0, ""}, + {"(*Error).Error", Method, 0, ""}, + {"(*Error).Unwrap", Method, 13, ""}, + {"(*ExitError).Error", Method, 0, ""}, + {"(ExitError).ExitCode", Method, 12, ""}, + {"(ExitError).Exited", Method, 0, ""}, + {"(ExitError).Pid", Method, 0, ""}, + {"(ExitError).String", Method, 0, ""}, + {"(ExitError).Success", Method, 0, ""}, + {"(ExitError).Sys", Method, 0, ""}, + {"(ExitError).SysUsage", Method, 0, ""}, + {"(ExitError).SystemTime", Method, 0, ""}, + {"(ExitError).UserTime", Method, 0, ""}, + {"Cmd", Type, 0, ""}, + {"Cmd.Args", Field, 0, ""}, + {"Cmd.Cancel", Field, 20, ""}, + {"Cmd.Dir", Field, 0, ""}, + {"Cmd.Env", Field, 0, ""}, + {"Cmd.Err", Field, 19, ""}, + {"Cmd.ExtraFiles", Field, 0, ""}, + {"Cmd.Path", Field, 0, ""}, + {"Cmd.Process", Field, 0, ""}, + {"Cmd.ProcessState", Field, 0, ""}, + {"Cmd.Stderr", Field, 0, ""}, + {"Cmd.Stdin", Field, 0, ""}, + {"Cmd.Stdout", Field, 0, ""}, + {"Cmd.SysProcAttr", Field, 0, ""}, + {"Cmd.WaitDelay", Field, 20, ""}, + {"Command", Func, 0, "func(name string, arg ...string) *Cmd"}, + {"CommandContext", Func, 7, "func(ctx context.Context, name string, arg ...string) *Cmd"}, + {"ErrDot", Var, 19, ""}, + {"ErrNotFound", Var, 0, ""}, + {"ErrWaitDelay", Var, 20, ""}, + {"Error", Type, 0, ""}, + {"Error.Err", Field, 0, ""}, + {"Error.Name", Field, 0, ""}, + {"ExitError", Type, 0, ""}, + {"ExitError.ProcessState", Field, 0, ""}, + {"ExitError.Stderr", Field, 6, ""}, + {"LookPath", Func, 0, "func(file string) (string, error)"}, }, "os/signal": { - {"Ignore", Func, 5}, - {"Ignored", Func, 11}, - {"Notify", Func, 0}, - {"NotifyContext", Func, 16}, - {"Reset", Func, 5}, - {"Stop", Func, 1}, + {"Ignore", Func, 5, "func(sig ...os.Signal)"}, + {"Ignored", Func, 11, "func(sig os.Signal) bool"}, + {"Notify", Func, 0, "func(c chan<- os.Signal, sig ...os.Signal)"}, + {"NotifyContext", Func, 16, "func(parent context.Context, signals ...os.Signal) (ctx context.Context, stop context.CancelFunc)"}, + {"Reset", Func, 5, "func(sig ...os.Signal)"}, + {"Stop", Func, 1, "func(c chan<- os.Signal)"}, }, "os/user": { - {"(*User).GroupIds", Method, 7}, - {"(UnknownGroupError).Error", Method, 7}, - {"(UnknownGroupIdError).Error", Method, 7}, - {"(UnknownUserError).Error", Method, 0}, - {"(UnknownUserIdError).Error", Method, 0}, - {"Current", Func, 0}, - {"Group", Type, 7}, - {"Group.Gid", Field, 7}, - {"Group.Name", Field, 7}, - {"Lookup", Func, 0}, - {"LookupGroup", Func, 7}, - {"LookupGroupId", Func, 7}, - {"LookupId", Func, 0}, - {"UnknownGroupError", Type, 7}, - {"UnknownGroupIdError", Type, 7}, - {"UnknownUserError", Type, 0}, - {"UnknownUserIdError", Type, 0}, - {"User", Type, 0}, - {"User.Gid", Field, 0}, - {"User.HomeDir", Field, 0}, - {"User.Name", Field, 0}, - {"User.Uid", Field, 0}, - {"User.Username", Field, 0}, + {"(*User).GroupIds", Method, 7, ""}, + {"(UnknownGroupError).Error", Method, 7, ""}, + {"(UnknownGroupIdError).Error", Method, 7, ""}, + {"(UnknownUserError).Error", Method, 0, ""}, + {"(UnknownUserIdError).Error", Method, 0, ""}, + {"Current", Func, 0, "func() (*User, error)"}, + {"Group", Type, 7, ""}, + {"Group.Gid", Field, 7, ""}, + {"Group.Name", Field, 7, ""}, + {"Lookup", Func, 0, "func(username string) (*User, error)"}, + {"LookupGroup", Func, 7, "func(name string) (*Group, error)"}, + {"LookupGroupId", Func, 7, "func(gid string) (*Group, error)"}, + {"LookupId", Func, 0, "func(uid string) (*User, error)"}, + {"UnknownGroupError", Type, 7, ""}, + {"UnknownGroupIdError", Type, 7, ""}, + {"UnknownUserError", Type, 0, ""}, + {"UnknownUserIdError", Type, 0, ""}, + {"User", Type, 0, ""}, + {"User.Gid", Field, 0, ""}, + {"User.HomeDir", Field, 0, ""}, + {"User.Name", Field, 0, ""}, + {"User.Uid", Field, 0, ""}, + {"User.Username", Field, 0, ""}, }, "path": { - {"Base", Func, 0}, - {"Clean", Func, 0}, - {"Dir", Func, 0}, - {"ErrBadPattern", Var, 0}, - {"Ext", Func, 0}, - {"IsAbs", Func, 0}, - {"Join", Func, 0}, - {"Match", Func, 0}, - {"Split", Func, 0}, + {"Base", Func, 0, "func(path string) string"}, + {"Clean", Func, 0, "func(path string) string"}, + {"Dir", Func, 0, "func(path string) string"}, + {"ErrBadPattern", Var, 0, ""}, + {"Ext", Func, 0, "func(path string) string"}, + {"IsAbs", Func, 0, "func(path string) bool"}, + {"Join", Func, 0, "func(elem ...string) string"}, + {"Match", Func, 0, "func(pattern string, name string) (matched bool, err error)"}, + {"Split", Func, 0, "func(path string) (dir string, file string)"}, }, "path/filepath": { - {"Abs", Func, 0}, - {"Base", Func, 0}, - {"Clean", Func, 0}, - {"Dir", Func, 0}, - {"ErrBadPattern", Var, 0}, - {"EvalSymlinks", Func, 0}, - {"Ext", Func, 0}, - {"FromSlash", Func, 0}, - {"Glob", Func, 0}, - {"HasPrefix", Func, 0}, - {"IsAbs", Func, 0}, - {"IsLocal", Func, 20}, - {"Join", Func, 0}, - {"ListSeparator", Const, 0}, - {"Localize", Func, 23}, - {"Match", Func, 0}, - {"Rel", Func, 0}, - {"Separator", Const, 0}, - {"SkipAll", Var, 20}, - {"SkipDir", Var, 0}, - {"Split", Func, 0}, - {"SplitList", Func, 0}, - {"ToSlash", Func, 0}, - {"VolumeName", Func, 0}, - {"Walk", Func, 0}, - {"WalkDir", Func, 16}, - {"WalkFunc", Type, 0}, + {"Abs", Func, 0, "func(path string) (string, error)"}, + {"Base", Func, 0, "func(path string) string"}, + {"Clean", Func, 0, "func(path string) string"}, + {"Dir", Func, 0, "func(path string) string"}, + {"ErrBadPattern", Var, 0, ""}, + {"EvalSymlinks", Func, 0, "func(path string) (string, error)"}, + {"Ext", Func, 0, "func(path string) string"}, + {"FromSlash", Func, 0, "func(path string) string"}, + {"Glob", Func, 0, "func(pattern string) (matches []string, err error)"}, + {"HasPrefix", Func, 0, "func(p string, prefix string) bool"}, + {"IsAbs", Func, 0, "func(path string) bool"}, + {"IsLocal", Func, 20, "func(path string) bool"}, + {"Join", Func, 0, "func(elem ...string) string"}, + {"ListSeparator", Const, 0, ""}, + {"Localize", Func, 23, "func(path string) (string, error)"}, + {"Match", Func, 0, "func(pattern string, name string) (matched bool, err error)"}, + {"Rel", Func, 0, "func(basepath string, targpath string) (string, error)"}, + {"Separator", Const, 0, ""}, + {"SkipAll", Var, 20, ""}, + {"SkipDir", Var, 0, ""}, + {"Split", Func, 0, "func(path string) (dir string, file string)"}, + {"SplitList", Func, 0, "func(path string) []string"}, + {"ToSlash", Func, 0, "func(path string) string"}, + {"VolumeName", Func, 0, "func(path string) string"}, + {"Walk", Func, 0, "func(root string, fn WalkFunc) error"}, + {"WalkDir", Func, 16, "func(root string, fn fs.WalkDirFunc) error"}, + {"WalkFunc", Type, 0, ""}, }, "plugin": { - {"(*Plugin).Lookup", Method, 8}, - {"Open", Func, 8}, - {"Plugin", Type, 8}, - {"Symbol", Type, 8}, + {"(*Plugin).Lookup", Method, 8, ""}, + {"Open", Func, 8, "func(path string) (*Plugin, error)"}, + {"Plugin", Type, 8, ""}, + {"Symbol", Type, 8, ""}, }, "reflect": { - {"(*MapIter).Key", Method, 12}, - {"(*MapIter).Next", Method, 12}, - {"(*MapIter).Reset", Method, 18}, - {"(*MapIter).Value", Method, 12}, - {"(*ValueError).Error", Method, 0}, - {"(ChanDir).String", Method, 0}, - {"(Kind).String", Method, 0}, - {"(Method).IsExported", Method, 17}, - {"(StructField).IsExported", Method, 17}, - {"(StructTag).Get", Method, 0}, - {"(StructTag).Lookup", Method, 7}, - {"(Value).Addr", Method, 0}, - {"(Value).Bool", Method, 0}, - {"(Value).Bytes", Method, 0}, - {"(Value).Call", Method, 0}, - {"(Value).CallSlice", Method, 0}, - {"(Value).CanAddr", Method, 0}, - {"(Value).CanComplex", Method, 18}, - {"(Value).CanConvert", Method, 17}, - {"(Value).CanFloat", Method, 18}, - {"(Value).CanInt", Method, 18}, - {"(Value).CanInterface", Method, 0}, - {"(Value).CanSet", Method, 0}, - {"(Value).CanUint", Method, 18}, - {"(Value).Cap", Method, 0}, - {"(Value).Clear", Method, 21}, - {"(Value).Close", Method, 0}, - {"(Value).Comparable", Method, 20}, - {"(Value).Complex", Method, 0}, - {"(Value).Convert", Method, 1}, - {"(Value).Elem", Method, 0}, - {"(Value).Equal", Method, 20}, - {"(Value).Field", Method, 0}, - {"(Value).FieldByIndex", Method, 0}, - {"(Value).FieldByIndexErr", Method, 18}, - {"(Value).FieldByName", Method, 0}, - {"(Value).FieldByNameFunc", Method, 0}, - {"(Value).Float", Method, 0}, - {"(Value).Grow", Method, 20}, - {"(Value).Index", Method, 0}, - {"(Value).Int", Method, 0}, - {"(Value).Interface", Method, 0}, - {"(Value).InterfaceData", Method, 0}, - {"(Value).IsNil", Method, 0}, - {"(Value).IsValid", Method, 0}, - {"(Value).IsZero", Method, 13}, - {"(Value).Kind", Method, 0}, - {"(Value).Len", Method, 0}, - {"(Value).MapIndex", Method, 0}, - {"(Value).MapKeys", Method, 0}, - {"(Value).MapRange", Method, 12}, - {"(Value).Method", Method, 0}, - {"(Value).MethodByName", Method, 0}, - {"(Value).NumField", Method, 0}, - {"(Value).NumMethod", Method, 0}, - {"(Value).OverflowComplex", Method, 0}, - {"(Value).OverflowFloat", Method, 0}, - {"(Value).OverflowInt", Method, 0}, - {"(Value).OverflowUint", Method, 0}, - {"(Value).Pointer", Method, 0}, - {"(Value).Recv", Method, 0}, - {"(Value).Send", Method, 0}, - {"(Value).Seq", Method, 23}, - {"(Value).Seq2", Method, 23}, - {"(Value).Set", Method, 0}, - {"(Value).SetBool", Method, 0}, - {"(Value).SetBytes", Method, 0}, - {"(Value).SetCap", Method, 2}, - {"(Value).SetComplex", Method, 0}, - {"(Value).SetFloat", Method, 0}, - {"(Value).SetInt", Method, 0}, - {"(Value).SetIterKey", Method, 18}, - {"(Value).SetIterValue", Method, 18}, - {"(Value).SetLen", Method, 0}, - {"(Value).SetMapIndex", Method, 0}, - {"(Value).SetPointer", Method, 0}, - {"(Value).SetString", Method, 0}, - {"(Value).SetUint", Method, 0}, - {"(Value).SetZero", Method, 20}, - {"(Value).Slice", Method, 0}, - {"(Value).Slice3", Method, 2}, - {"(Value).String", Method, 0}, - {"(Value).TryRecv", Method, 0}, - {"(Value).TrySend", Method, 0}, - {"(Value).Type", Method, 0}, - {"(Value).Uint", Method, 0}, - {"(Value).UnsafeAddr", Method, 0}, - {"(Value).UnsafePointer", Method, 18}, - {"Append", Func, 0}, - {"AppendSlice", Func, 0}, - {"Array", Const, 0}, - {"ArrayOf", Func, 5}, - {"Bool", Const, 0}, - {"BothDir", Const, 0}, - {"Chan", Const, 0}, - {"ChanDir", Type, 0}, - {"ChanOf", Func, 1}, - {"Complex128", Const, 0}, - {"Complex64", Const, 0}, - {"Copy", Func, 0}, - {"DeepEqual", Func, 0}, - {"Float32", Const, 0}, - {"Float64", Const, 0}, - {"Func", Const, 0}, - {"FuncOf", Func, 5}, - {"Indirect", Func, 0}, - {"Int", Const, 0}, - {"Int16", Const, 0}, - {"Int32", Const, 0}, - {"Int64", Const, 0}, - {"Int8", Const, 0}, - {"Interface", Const, 0}, - {"Invalid", Const, 0}, - {"Kind", Type, 0}, - {"MakeChan", Func, 0}, - {"MakeFunc", Func, 1}, - {"MakeMap", Func, 0}, - {"MakeMapWithSize", Func, 9}, - {"MakeSlice", Func, 0}, - {"Map", Const, 0}, - {"MapIter", Type, 12}, - {"MapOf", Func, 1}, - {"Method", Type, 0}, - {"Method.Func", Field, 0}, - {"Method.Index", Field, 0}, - {"Method.Name", Field, 0}, - {"Method.PkgPath", Field, 0}, - {"Method.Type", Field, 0}, - {"New", Func, 0}, - {"NewAt", Func, 0}, - {"Pointer", Const, 18}, - {"PointerTo", Func, 18}, - {"Ptr", Const, 0}, - {"PtrTo", Func, 0}, - {"RecvDir", Const, 0}, - {"Select", Func, 1}, - {"SelectCase", Type, 1}, - {"SelectCase.Chan", Field, 1}, - {"SelectCase.Dir", Field, 1}, - {"SelectCase.Send", Field, 1}, - {"SelectDefault", Const, 1}, - {"SelectDir", Type, 1}, - {"SelectRecv", Const, 1}, - {"SelectSend", Const, 1}, - {"SendDir", Const, 0}, - {"Slice", Const, 0}, - {"SliceAt", Func, 23}, - {"SliceHeader", Type, 0}, - {"SliceHeader.Cap", Field, 0}, - {"SliceHeader.Data", Field, 0}, - {"SliceHeader.Len", Field, 0}, - {"SliceOf", Func, 1}, - {"String", Const, 0}, - {"StringHeader", Type, 0}, - {"StringHeader.Data", Field, 0}, - {"StringHeader.Len", Field, 0}, - {"Struct", Const, 0}, - {"StructField", Type, 0}, - {"StructField.Anonymous", Field, 0}, - {"StructField.Index", Field, 0}, - {"StructField.Name", Field, 0}, - {"StructField.Offset", Field, 0}, - {"StructField.PkgPath", Field, 0}, - {"StructField.Tag", Field, 0}, - {"StructField.Type", Field, 0}, - {"StructOf", Func, 7}, - {"StructTag", Type, 0}, - {"Swapper", Func, 8}, - {"Type", Type, 0}, - {"TypeFor", Func, 22}, - {"TypeOf", Func, 0}, - {"Uint", Const, 0}, - {"Uint16", Const, 0}, - {"Uint32", Const, 0}, - {"Uint64", Const, 0}, - {"Uint8", Const, 0}, - {"Uintptr", Const, 0}, - {"UnsafePointer", Const, 0}, - {"Value", Type, 0}, - {"ValueError", Type, 0}, - {"ValueError.Kind", Field, 0}, - {"ValueError.Method", Field, 0}, - {"ValueOf", Func, 0}, - {"VisibleFields", Func, 17}, - {"Zero", Func, 0}, + {"(*MapIter).Key", Method, 12, ""}, + {"(*MapIter).Next", Method, 12, ""}, + {"(*MapIter).Reset", Method, 18, ""}, + {"(*MapIter).Value", Method, 12, ""}, + {"(*ValueError).Error", Method, 0, ""}, + {"(ChanDir).String", Method, 0, ""}, + {"(Kind).String", Method, 0, ""}, + {"(Method).IsExported", Method, 17, ""}, + {"(StructField).IsExported", Method, 17, ""}, + {"(StructTag).Get", Method, 0, ""}, + {"(StructTag).Lookup", Method, 7, ""}, + {"(Value).Addr", Method, 0, ""}, + {"(Value).Bool", Method, 0, ""}, + {"(Value).Bytes", Method, 0, ""}, + {"(Value).Call", Method, 0, ""}, + {"(Value).CallSlice", Method, 0, ""}, + {"(Value).CanAddr", Method, 0, ""}, + {"(Value).CanComplex", Method, 18, ""}, + {"(Value).CanConvert", Method, 17, ""}, + {"(Value).CanFloat", Method, 18, ""}, + {"(Value).CanInt", Method, 18, ""}, + {"(Value).CanInterface", Method, 0, ""}, + {"(Value).CanSet", Method, 0, ""}, + {"(Value).CanUint", Method, 18, ""}, + {"(Value).Cap", Method, 0, ""}, + {"(Value).Clear", Method, 21, ""}, + {"(Value).Close", Method, 0, ""}, + {"(Value).Comparable", Method, 20, ""}, + {"(Value).Complex", Method, 0, ""}, + {"(Value).Convert", Method, 1, ""}, + {"(Value).Elem", Method, 0, ""}, + {"(Value).Equal", Method, 20, ""}, + {"(Value).Field", Method, 0, ""}, + {"(Value).FieldByIndex", Method, 0, ""}, + {"(Value).FieldByIndexErr", Method, 18, ""}, + {"(Value).FieldByName", Method, 0, ""}, + {"(Value).FieldByNameFunc", Method, 0, ""}, + {"(Value).Float", Method, 0, ""}, + {"(Value).Grow", Method, 20, ""}, + {"(Value).Index", Method, 0, ""}, + {"(Value).Int", Method, 0, ""}, + {"(Value).Interface", Method, 0, ""}, + {"(Value).InterfaceData", Method, 0, ""}, + {"(Value).IsNil", Method, 0, ""}, + {"(Value).IsValid", Method, 0, ""}, + {"(Value).IsZero", Method, 13, ""}, + {"(Value).Kind", Method, 0, ""}, + {"(Value).Len", Method, 0, ""}, + {"(Value).MapIndex", Method, 0, ""}, + {"(Value).MapKeys", Method, 0, ""}, + {"(Value).MapRange", Method, 12, ""}, + {"(Value).Method", Method, 0, ""}, + {"(Value).MethodByName", Method, 0, ""}, + {"(Value).NumField", Method, 0, ""}, + {"(Value).NumMethod", Method, 0, ""}, + {"(Value).OverflowComplex", Method, 0, ""}, + {"(Value).OverflowFloat", Method, 0, ""}, + {"(Value).OverflowInt", Method, 0, ""}, + {"(Value).OverflowUint", Method, 0, ""}, + {"(Value).Pointer", Method, 0, ""}, + {"(Value).Recv", Method, 0, ""}, + {"(Value).Send", Method, 0, ""}, + {"(Value).Seq", Method, 23, ""}, + {"(Value).Seq2", Method, 23, ""}, + {"(Value).Set", Method, 0, ""}, + {"(Value).SetBool", Method, 0, ""}, + {"(Value).SetBytes", Method, 0, ""}, + {"(Value).SetCap", Method, 2, ""}, + {"(Value).SetComplex", Method, 0, ""}, + {"(Value).SetFloat", Method, 0, ""}, + {"(Value).SetInt", Method, 0, ""}, + {"(Value).SetIterKey", Method, 18, ""}, + {"(Value).SetIterValue", Method, 18, ""}, + {"(Value).SetLen", Method, 0, ""}, + {"(Value).SetMapIndex", Method, 0, ""}, + {"(Value).SetPointer", Method, 0, ""}, + {"(Value).SetString", Method, 0, ""}, + {"(Value).SetUint", Method, 0, ""}, + {"(Value).SetZero", Method, 20, ""}, + {"(Value).Slice", Method, 0, ""}, + {"(Value).Slice3", Method, 2, ""}, + {"(Value).String", Method, 0, ""}, + {"(Value).TryRecv", Method, 0, ""}, + {"(Value).TrySend", Method, 0, ""}, + {"(Value).Type", Method, 0, ""}, + {"(Value).Uint", Method, 0, ""}, + {"(Value).UnsafeAddr", Method, 0, ""}, + {"(Value).UnsafePointer", Method, 18, ""}, + {"Append", Func, 0, "func(s Value, x ...Value) Value"}, + {"AppendSlice", Func, 0, "func(s Value, t Value) Value"}, + {"Array", Const, 0, ""}, + {"ArrayOf", Func, 5, "func(length int, elem Type) Type"}, + {"Bool", Const, 0, ""}, + {"BothDir", Const, 0, ""}, + {"Chan", Const, 0, ""}, + {"ChanDir", Type, 0, ""}, + {"ChanOf", Func, 1, "func(dir ChanDir, t Type) Type"}, + {"Complex128", Const, 0, ""}, + {"Complex64", Const, 0, ""}, + {"Copy", Func, 0, "func(dst Value, src Value) int"}, + {"DeepEqual", Func, 0, "func(x any, y any) bool"}, + {"Float32", Const, 0, ""}, + {"Float64", Const, 0, ""}, + {"Func", Const, 0, ""}, + {"FuncOf", Func, 5, "func(in []Type, out []Type, variadic bool) Type"}, + {"Indirect", Func, 0, "func(v Value) Value"}, + {"Int", Const, 0, ""}, + {"Int16", Const, 0, ""}, + {"Int32", Const, 0, ""}, + {"Int64", Const, 0, ""}, + {"Int8", Const, 0, ""}, + {"Interface", Const, 0, ""}, + {"Invalid", Const, 0, ""}, + {"Kind", Type, 0, ""}, + {"MakeChan", Func, 0, "func(typ Type, buffer int) Value"}, + {"MakeFunc", Func, 1, "func(typ Type, fn func(args []Value) (results []Value)) Value"}, + {"MakeMap", Func, 0, "func(typ Type) Value"}, + {"MakeMapWithSize", Func, 9, "func(typ Type, n int) Value"}, + {"MakeSlice", Func, 0, "func(typ Type, len int, cap int) Value"}, + {"Map", Const, 0, ""}, + {"MapIter", Type, 12, ""}, + {"MapOf", Func, 1, "func(key Type, elem Type) Type"}, + {"Method", Type, 0, ""}, + {"Method.Func", Field, 0, ""}, + {"Method.Index", Field, 0, ""}, + {"Method.Name", Field, 0, ""}, + {"Method.PkgPath", Field, 0, ""}, + {"Method.Type", Field, 0, ""}, + {"New", Func, 0, "func(typ Type) Value"}, + {"NewAt", Func, 0, "func(typ Type, p unsafe.Pointer) Value"}, + {"Pointer", Const, 18, ""}, + {"PointerTo", Func, 18, "func(t Type) Type"}, + {"Ptr", Const, 0, ""}, + {"PtrTo", Func, 0, "func(t Type) Type"}, + {"RecvDir", Const, 0, ""}, + {"Select", Func, 1, "func(cases []SelectCase) (chosen int, recv Value, recvOK bool)"}, + {"SelectCase", Type, 1, ""}, + {"SelectCase.Chan", Field, 1, ""}, + {"SelectCase.Dir", Field, 1, ""}, + {"SelectCase.Send", Field, 1, ""}, + {"SelectDefault", Const, 1, ""}, + {"SelectDir", Type, 1, ""}, + {"SelectRecv", Const, 1, ""}, + {"SelectSend", Const, 1, ""}, + {"SendDir", Const, 0, ""}, + {"Slice", Const, 0, ""}, + {"SliceAt", Func, 23, "func(typ Type, p unsafe.Pointer, n int) Value"}, + {"SliceHeader", Type, 0, ""}, + {"SliceHeader.Cap", Field, 0, ""}, + {"SliceHeader.Data", Field, 0, ""}, + {"SliceHeader.Len", Field, 0, ""}, + {"SliceOf", Func, 1, "func(t Type) Type"}, + {"String", Const, 0, ""}, + {"StringHeader", Type, 0, ""}, + {"StringHeader.Data", Field, 0, ""}, + {"StringHeader.Len", Field, 0, ""}, + {"Struct", Const, 0, ""}, + {"StructField", Type, 0, ""}, + {"StructField.Anonymous", Field, 0, ""}, + {"StructField.Index", Field, 0, ""}, + {"StructField.Name", Field, 0, ""}, + {"StructField.Offset", Field, 0, ""}, + {"StructField.PkgPath", Field, 0, ""}, + {"StructField.Tag", Field, 0, ""}, + {"StructField.Type", Field, 0, ""}, + {"StructOf", Func, 7, "func(fields []StructField) Type"}, + {"StructTag", Type, 0, ""}, + {"Swapper", Func, 8, "func(slice any) func(i int, j int)"}, + {"Type", Type, 0, ""}, + {"TypeFor", Func, 22, "func[T any]() Type"}, + {"TypeOf", Func, 0, "func(i any) Type"}, + {"Uint", Const, 0, ""}, + {"Uint16", Const, 0, ""}, + {"Uint32", Const, 0, ""}, + {"Uint64", Const, 0, ""}, + {"Uint8", Const, 0, ""}, + {"Uintptr", Const, 0, ""}, + {"UnsafePointer", Const, 0, ""}, + {"Value", Type, 0, ""}, + {"ValueError", Type, 0, ""}, + {"ValueError.Kind", Field, 0, ""}, + {"ValueError.Method", Field, 0, ""}, + {"ValueOf", Func, 0, "func(i any) Value"}, + {"VisibleFields", Func, 17, "func(t Type) []StructField"}, + {"Zero", Func, 0, "func(typ Type) Value"}, }, "regexp": { - {"(*Regexp).AppendText", Method, 24}, - {"(*Regexp).Copy", Method, 6}, - {"(*Regexp).Expand", Method, 0}, - {"(*Regexp).ExpandString", Method, 0}, - {"(*Regexp).Find", Method, 0}, - {"(*Regexp).FindAll", Method, 0}, - {"(*Regexp).FindAllIndex", Method, 0}, - {"(*Regexp).FindAllString", Method, 0}, - {"(*Regexp).FindAllStringIndex", Method, 0}, - {"(*Regexp).FindAllStringSubmatch", Method, 0}, - {"(*Regexp).FindAllStringSubmatchIndex", Method, 0}, - {"(*Regexp).FindAllSubmatch", Method, 0}, - {"(*Regexp).FindAllSubmatchIndex", Method, 0}, - {"(*Regexp).FindIndex", Method, 0}, - {"(*Regexp).FindReaderIndex", Method, 0}, - {"(*Regexp).FindReaderSubmatchIndex", Method, 0}, - {"(*Regexp).FindString", Method, 0}, - {"(*Regexp).FindStringIndex", Method, 0}, - {"(*Regexp).FindStringSubmatch", Method, 0}, - {"(*Regexp).FindStringSubmatchIndex", Method, 0}, - {"(*Regexp).FindSubmatch", Method, 0}, - {"(*Regexp).FindSubmatchIndex", Method, 0}, - {"(*Regexp).LiteralPrefix", Method, 0}, - {"(*Regexp).Longest", Method, 1}, - {"(*Regexp).MarshalText", Method, 21}, - {"(*Regexp).Match", Method, 0}, - {"(*Regexp).MatchReader", Method, 0}, - {"(*Regexp).MatchString", Method, 0}, - {"(*Regexp).NumSubexp", Method, 0}, - {"(*Regexp).ReplaceAll", Method, 0}, - {"(*Regexp).ReplaceAllFunc", Method, 0}, - {"(*Regexp).ReplaceAllLiteral", Method, 0}, - {"(*Regexp).ReplaceAllLiteralString", Method, 0}, - {"(*Regexp).ReplaceAllString", Method, 0}, - {"(*Regexp).ReplaceAllStringFunc", Method, 0}, - {"(*Regexp).Split", Method, 1}, - {"(*Regexp).String", Method, 0}, - {"(*Regexp).SubexpIndex", Method, 15}, - {"(*Regexp).SubexpNames", Method, 0}, - {"(*Regexp).UnmarshalText", Method, 21}, - {"Compile", Func, 0}, - {"CompilePOSIX", Func, 0}, - {"Match", Func, 0}, - {"MatchReader", Func, 0}, - {"MatchString", Func, 0}, - {"MustCompile", Func, 0}, - {"MustCompilePOSIX", Func, 0}, - {"QuoteMeta", Func, 0}, - {"Regexp", Type, 0}, + {"(*Regexp).AppendText", Method, 24, ""}, + {"(*Regexp).Copy", Method, 6, ""}, + {"(*Regexp).Expand", Method, 0, ""}, + {"(*Regexp).ExpandString", Method, 0, ""}, + {"(*Regexp).Find", Method, 0, ""}, + {"(*Regexp).FindAll", Method, 0, ""}, + {"(*Regexp).FindAllIndex", Method, 0, ""}, + {"(*Regexp).FindAllString", Method, 0, ""}, + {"(*Regexp).FindAllStringIndex", Method, 0, ""}, + {"(*Regexp).FindAllStringSubmatch", Method, 0, ""}, + {"(*Regexp).FindAllStringSubmatchIndex", Method, 0, ""}, + {"(*Regexp).FindAllSubmatch", Method, 0, ""}, + {"(*Regexp).FindAllSubmatchIndex", Method, 0, ""}, + {"(*Regexp).FindIndex", Method, 0, ""}, + {"(*Regexp).FindReaderIndex", Method, 0, ""}, + {"(*Regexp).FindReaderSubmatchIndex", Method, 0, ""}, + {"(*Regexp).FindString", Method, 0, ""}, + {"(*Regexp).FindStringIndex", Method, 0, ""}, + {"(*Regexp).FindStringSubmatch", Method, 0, ""}, + {"(*Regexp).FindStringSubmatchIndex", Method, 0, ""}, + {"(*Regexp).FindSubmatch", Method, 0, ""}, + {"(*Regexp).FindSubmatchIndex", Method, 0, ""}, + {"(*Regexp).LiteralPrefix", Method, 0, ""}, + {"(*Regexp).Longest", Method, 1, ""}, + {"(*Regexp).MarshalText", Method, 21, ""}, + {"(*Regexp).Match", Method, 0, ""}, + {"(*Regexp).MatchReader", Method, 0, ""}, + {"(*Regexp).MatchString", Method, 0, ""}, + {"(*Regexp).NumSubexp", Method, 0, ""}, + {"(*Regexp).ReplaceAll", Method, 0, ""}, + {"(*Regexp).ReplaceAllFunc", Method, 0, ""}, + {"(*Regexp).ReplaceAllLiteral", Method, 0, ""}, + {"(*Regexp).ReplaceAllLiteralString", Method, 0, ""}, + {"(*Regexp).ReplaceAllString", Method, 0, ""}, + {"(*Regexp).ReplaceAllStringFunc", Method, 0, ""}, + {"(*Regexp).Split", Method, 1, ""}, + {"(*Regexp).String", Method, 0, ""}, + {"(*Regexp).SubexpIndex", Method, 15, ""}, + {"(*Regexp).SubexpNames", Method, 0, ""}, + {"(*Regexp).UnmarshalText", Method, 21, ""}, + {"Compile", Func, 0, "func(expr string) (*Regexp, error)"}, + {"CompilePOSIX", Func, 0, "func(expr string) (*Regexp, error)"}, + {"Match", Func, 0, "func(pattern string, b []byte) (matched bool, err error)"}, + {"MatchReader", Func, 0, "func(pattern string, r io.RuneReader) (matched bool, err error)"}, + {"MatchString", Func, 0, "func(pattern string, s string) (matched bool, err error)"}, + {"MustCompile", Func, 0, "func(str string) *Regexp"}, + {"MustCompilePOSIX", Func, 0, "func(str string) *Regexp"}, + {"QuoteMeta", Func, 0, "func(s string) string"}, + {"Regexp", Type, 0, ""}, }, "regexp/syntax": { - {"(*Error).Error", Method, 0}, - {"(*Inst).MatchEmptyWidth", Method, 0}, - {"(*Inst).MatchRune", Method, 0}, - {"(*Inst).MatchRunePos", Method, 3}, - {"(*Inst).String", Method, 0}, - {"(*Prog).Prefix", Method, 0}, - {"(*Prog).StartCond", Method, 0}, - {"(*Prog).String", Method, 0}, - {"(*Regexp).CapNames", Method, 0}, - {"(*Regexp).Equal", Method, 0}, - {"(*Regexp).MaxCap", Method, 0}, - {"(*Regexp).Simplify", Method, 0}, - {"(*Regexp).String", Method, 0}, - {"(ErrorCode).String", Method, 0}, - {"(InstOp).String", Method, 3}, - {"(Op).String", Method, 11}, - {"ClassNL", Const, 0}, - {"Compile", Func, 0}, - {"DotNL", Const, 0}, - {"EmptyBeginLine", Const, 0}, - {"EmptyBeginText", Const, 0}, - {"EmptyEndLine", Const, 0}, - {"EmptyEndText", Const, 0}, - {"EmptyNoWordBoundary", Const, 0}, - {"EmptyOp", Type, 0}, - {"EmptyOpContext", Func, 0}, - {"EmptyWordBoundary", Const, 0}, - {"ErrInternalError", Const, 0}, - {"ErrInvalidCharClass", Const, 0}, - {"ErrInvalidCharRange", Const, 0}, - {"ErrInvalidEscape", Const, 0}, - {"ErrInvalidNamedCapture", Const, 0}, - {"ErrInvalidPerlOp", Const, 0}, - {"ErrInvalidRepeatOp", Const, 0}, - {"ErrInvalidRepeatSize", Const, 0}, - {"ErrInvalidUTF8", Const, 0}, - {"ErrLarge", Const, 20}, - {"ErrMissingBracket", Const, 0}, - {"ErrMissingParen", Const, 0}, - {"ErrMissingRepeatArgument", Const, 0}, - {"ErrNestingDepth", Const, 19}, - {"ErrTrailingBackslash", Const, 0}, - {"ErrUnexpectedParen", Const, 1}, - {"Error", Type, 0}, - {"Error.Code", Field, 0}, - {"Error.Expr", Field, 0}, - {"ErrorCode", Type, 0}, - {"Flags", Type, 0}, - {"FoldCase", Const, 0}, - {"Inst", Type, 0}, - {"Inst.Arg", Field, 0}, - {"Inst.Op", Field, 0}, - {"Inst.Out", Field, 0}, - {"Inst.Rune", Field, 0}, - {"InstAlt", Const, 0}, - {"InstAltMatch", Const, 0}, - {"InstCapture", Const, 0}, - {"InstEmptyWidth", Const, 0}, - {"InstFail", Const, 0}, - {"InstMatch", Const, 0}, - {"InstNop", Const, 0}, - {"InstOp", Type, 0}, - {"InstRune", Const, 0}, - {"InstRune1", Const, 0}, - {"InstRuneAny", Const, 0}, - {"InstRuneAnyNotNL", Const, 0}, - {"IsWordChar", Func, 0}, - {"Literal", Const, 0}, - {"MatchNL", Const, 0}, - {"NonGreedy", Const, 0}, - {"OneLine", Const, 0}, - {"Op", Type, 0}, - {"OpAlternate", Const, 0}, - {"OpAnyChar", Const, 0}, - {"OpAnyCharNotNL", Const, 0}, - {"OpBeginLine", Const, 0}, - {"OpBeginText", Const, 0}, - {"OpCapture", Const, 0}, - {"OpCharClass", Const, 0}, - {"OpConcat", Const, 0}, - {"OpEmptyMatch", Const, 0}, - {"OpEndLine", Const, 0}, - {"OpEndText", Const, 0}, - {"OpLiteral", Const, 0}, - {"OpNoMatch", Const, 0}, - {"OpNoWordBoundary", Const, 0}, - {"OpPlus", Const, 0}, - {"OpQuest", Const, 0}, - {"OpRepeat", Const, 0}, - {"OpStar", Const, 0}, - {"OpWordBoundary", Const, 0}, - {"POSIX", Const, 0}, - {"Parse", Func, 0}, - {"Perl", Const, 0}, - {"PerlX", Const, 0}, - {"Prog", Type, 0}, - {"Prog.Inst", Field, 0}, - {"Prog.NumCap", Field, 0}, - {"Prog.Start", Field, 0}, - {"Regexp", Type, 0}, - {"Regexp.Cap", Field, 0}, - {"Regexp.Flags", Field, 0}, - {"Regexp.Max", Field, 0}, - {"Regexp.Min", Field, 0}, - {"Regexp.Name", Field, 0}, - {"Regexp.Op", Field, 0}, - {"Regexp.Rune", Field, 0}, - {"Regexp.Rune0", Field, 0}, - {"Regexp.Sub", Field, 0}, - {"Regexp.Sub0", Field, 0}, - {"Simple", Const, 0}, - {"UnicodeGroups", Const, 0}, - {"WasDollar", Const, 0}, + {"(*Error).Error", Method, 0, ""}, + {"(*Inst).MatchEmptyWidth", Method, 0, ""}, + {"(*Inst).MatchRune", Method, 0, ""}, + {"(*Inst).MatchRunePos", Method, 3, ""}, + {"(*Inst).String", Method, 0, ""}, + {"(*Prog).Prefix", Method, 0, ""}, + {"(*Prog).StartCond", Method, 0, ""}, + {"(*Prog).String", Method, 0, ""}, + {"(*Regexp).CapNames", Method, 0, ""}, + {"(*Regexp).Equal", Method, 0, ""}, + {"(*Regexp).MaxCap", Method, 0, ""}, + {"(*Regexp).Simplify", Method, 0, ""}, + {"(*Regexp).String", Method, 0, ""}, + {"(ErrorCode).String", Method, 0, ""}, + {"(InstOp).String", Method, 3, ""}, + {"(Op).String", Method, 11, ""}, + {"ClassNL", Const, 0, ""}, + {"Compile", Func, 0, "func(re *Regexp) (*Prog, error)"}, + {"DotNL", Const, 0, ""}, + {"EmptyBeginLine", Const, 0, ""}, + {"EmptyBeginText", Const, 0, ""}, + {"EmptyEndLine", Const, 0, ""}, + {"EmptyEndText", Const, 0, ""}, + {"EmptyNoWordBoundary", Const, 0, ""}, + {"EmptyOp", Type, 0, ""}, + {"EmptyOpContext", Func, 0, "func(r1 rune, r2 rune) EmptyOp"}, + {"EmptyWordBoundary", Const, 0, ""}, + {"ErrInternalError", Const, 0, ""}, + {"ErrInvalidCharClass", Const, 0, ""}, + {"ErrInvalidCharRange", Const, 0, ""}, + {"ErrInvalidEscape", Const, 0, ""}, + {"ErrInvalidNamedCapture", Const, 0, ""}, + {"ErrInvalidPerlOp", Const, 0, ""}, + {"ErrInvalidRepeatOp", Const, 0, ""}, + {"ErrInvalidRepeatSize", Const, 0, ""}, + {"ErrInvalidUTF8", Const, 0, ""}, + {"ErrLarge", Const, 20, ""}, + {"ErrMissingBracket", Const, 0, ""}, + {"ErrMissingParen", Const, 0, ""}, + {"ErrMissingRepeatArgument", Const, 0, ""}, + {"ErrNestingDepth", Const, 19, ""}, + {"ErrTrailingBackslash", Const, 0, ""}, + {"ErrUnexpectedParen", Const, 1, ""}, + {"Error", Type, 0, ""}, + {"Error.Code", Field, 0, ""}, + {"Error.Expr", Field, 0, ""}, + {"ErrorCode", Type, 0, ""}, + {"Flags", Type, 0, ""}, + {"FoldCase", Const, 0, ""}, + {"Inst", Type, 0, ""}, + {"Inst.Arg", Field, 0, ""}, + {"Inst.Op", Field, 0, ""}, + {"Inst.Out", Field, 0, ""}, + {"Inst.Rune", Field, 0, ""}, + {"InstAlt", Const, 0, ""}, + {"InstAltMatch", Const, 0, ""}, + {"InstCapture", Const, 0, ""}, + {"InstEmptyWidth", Const, 0, ""}, + {"InstFail", Const, 0, ""}, + {"InstMatch", Const, 0, ""}, + {"InstNop", Const, 0, ""}, + {"InstOp", Type, 0, ""}, + {"InstRune", Const, 0, ""}, + {"InstRune1", Const, 0, ""}, + {"InstRuneAny", Const, 0, ""}, + {"InstRuneAnyNotNL", Const, 0, ""}, + {"IsWordChar", Func, 0, "func(r rune) bool"}, + {"Literal", Const, 0, ""}, + {"MatchNL", Const, 0, ""}, + {"NonGreedy", Const, 0, ""}, + {"OneLine", Const, 0, ""}, + {"Op", Type, 0, ""}, + {"OpAlternate", Const, 0, ""}, + {"OpAnyChar", Const, 0, ""}, + {"OpAnyCharNotNL", Const, 0, ""}, + {"OpBeginLine", Const, 0, ""}, + {"OpBeginText", Const, 0, ""}, + {"OpCapture", Const, 0, ""}, + {"OpCharClass", Const, 0, ""}, + {"OpConcat", Const, 0, ""}, + {"OpEmptyMatch", Const, 0, ""}, + {"OpEndLine", Const, 0, ""}, + {"OpEndText", Const, 0, ""}, + {"OpLiteral", Const, 0, ""}, + {"OpNoMatch", Const, 0, ""}, + {"OpNoWordBoundary", Const, 0, ""}, + {"OpPlus", Const, 0, ""}, + {"OpQuest", Const, 0, ""}, + {"OpRepeat", Const, 0, ""}, + {"OpStar", Const, 0, ""}, + {"OpWordBoundary", Const, 0, ""}, + {"POSIX", Const, 0, ""}, + {"Parse", Func, 0, "func(s string, flags Flags) (*Regexp, error)"}, + {"Perl", Const, 0, ""}, + {"PerlX", Const, 0, ""}, + {"Prog", Type, 0, ""}, + {"Prog.Inst", Field, 0, ""}, + {"Prog.NumCap", Field, 0, ""}, + {"Prog.Start", Field, 0, ""}, + {"Regexp", Type, 0, ""}, + {"Regexp.Cap", Field, 0, ""}, + {"Regexp.Flags", Field, 0, ""}, + {"Regexp.Max", Field, 0, ""}, + {"Regexp.Min", Field, 0, ""}, + {"Regexp.Name", Field, 0, ""}, + {"Regexp.Op", Field, 0, ""}, + {"Regexp.Rune", Field, 0, ""}, + {"Regexp.Rune0", Field, 0, ""}, + {"Regexp.Sub", Field, 0, ""}, + {"Regexp.Sub0", Field, 0, ""}, + {"Simple", Const, 0, ""}, + {"UnicodeGroups", Const, 0, ""}, + {"WasDollar", Const, 0, ""}, }, "runtime": { - {"(*BlockProfileRecord).Stack", Method, 1}, - {"(*Frames).Next", Method, 7}, - {"(*Func).Entry", Method, 0}, - {"(*Func).FileLine", Method, 0}, - {"(*Func).Name", Method, 0}, - {"(*MemProfileRecord).InUseBytes", Method, 0}, - {"(*MemProfileRecord).InUseObjects", Method, 0}, - {"(*MemProfileRecord).Stack", Method, 0}, - {"(*PanicNilError).Error", Method, 21}, - {"(*PanicNilError).RuntimeError", Method, 21}, - {"(*Pinner).Pin", Method, 21}, - {"(*Pinner).Unpin", Method, 21}, - {"(*StackRecord).Stack", Method, 0}, - {"(*TypeAssertionError).Error", Method, 0}, - {"(*TypeAssertionError).RuntimeError", Method, 0}, - {"(Cleanup).Stop", Method, 24}, - {"AddCleanup", Func, 24}, - {"BlockProfile", Func, 1}, - {"BlockProfileRecord", Type, 1}, - {"BlockProfileRecord.Count", Field, 1}, - {"BlockProfileRecord.Cycles", Field, 1}, - {"BlockProfileRecord.StackRecord", Field, 1}, - {"Breakpoint", Func, 0}, - {"CPUProfile", Func, 0}, - {"Caller", Func, 0}, - {"Callers", Func, 0}, - {"CallersFrames", Func, 7}, - {"Cleanup", Type, 24}, - {"Compiler", Const, 0}, - {"Error", Type, 0}, - {"Frame", Type, 7}, - {"Frame.Entry", Field, 7}, - {"Frame.File", Field, 7}, - {"Frame.Func", Field, 7}, - {"Frame.Function", Field, 7}, - {"Frame.Line", Field, 7}, - {"Frame.PC", Field, 7}, - {"Frames", Type, 7}, - {"Func", Type, 0}, - {"FuncForPC", Func, 0}, - {"GC", Func, 0}, - {"GOARCH", Const, 0}, - {"GOMAXPROCS", Func, 0}, - {"GOOS", Const, 0}, - {"GOROOT", Func, 0}, - {"Goexit", Func, 0}, - {"GoroutineProfile", Func, 0}, - {"Gosched", Func, 0}, - {"KeepAlive", Func, 7}, - {"LockOSThread", Func, 0}, - {"MemProfile", Func, 0}, - {"MemProfileRate", Var, 0}, - {"MemProfileRecord", Type, 0}, - {"MemProfileRecord.AllocBytes", Field, 0}, - {"MemProfileRecord.AllocObjects", Field, 0}, - {"MemProfileRecord.FreeBytes", Field, 0}, - {"MemProfileRecord.FreeObjects", Field, 0}, - {"MemProfileRecord.Stack0", Field, 0}, - {"MemStats", Type, 0}, - {"MemStats.Alloc", Field, 0}, - {"MemStats.BuckHashSys", Field, 0}, - {"MemStats.BySize", Field, 0}, - {"MemStats.DebugGC", Field, 0}, - {"MemStats.EnableGC", Field, 0}, - {"MemStats.Frees", Field, 0}, - {"MemStats.GCCPUFraction", Field, 5}, - {"MemStats.GCSys", Field, 2}, - {"MemStats.HeapAlloc", Field, 0}, - {"MemStats.HeapIdle", Field, 0}, - {"MemStats.HeapInuse", Field, 0}, - {"MemStats.HeapObjects", Field, 0}, - {"MemStats.HeapReleased", Field, 0}, - {"MemStats.HeapSys", Field, 0}, - {"MemStats.LastGC", Field, 0}, - {"MemStats.Lookups", Field, 0}, - {"MemStats.MCacheInuse", Field, 0}, - {"MemStats.MCacheSys", Field, 0}, - {"MemStats.MSpanInuse", Field, 0}, - {"MemStats.MSpanSys", Field, 0}, - {"MemStats.Mallocs", Field, 0}, - {"MemStats.NextGC", Field, 0}, - {"MemStats.NumForcedGC", Field, 8}, - {"MemStats.NumGC", Field, 0}, - {"MemStats.OtherSys", Field, 2}, - {"MemStats.PauseEnd", Field, 4}, - {"MemStats.PauseNs", Field, 0}, - {"MemStats.PauseTotalNs", Field, 0}, - {"MemStats.StackInuse", Field, 0}, - {"MemStats.StackSys", Field, 0}, - {"MemStats.Sys", Field, 0}, - {"MemStats.TotalAlloc", Field, 0}, - {"MutexProfile", Func, 8}, - {"NumCPU", Func, 0}, - {"NumCgoCall", Func, 0}, - {"NumGoroutine", Func, 0}, - {"PanicNilError", Type, 21}, - {"Pinner", Type, 21}, - {"ReadMemStats", Func, 0}, - {"ReadTrace", Func, 5}, - {"SetBlockProfileRate", Func, 1}, - {"SetCPUProfileRate", Func, 0}, - {"SetCgoTraceback", Func, 7}, - {"SetFinalizer", Func, 0}, - {"SetMutexProfileFraction", Func, 8}, - {"Stack", Func, 0}, - {"StackRecord", Type, 0}, - {"StackRecord.Stack0", Field, 0}, - {"StartTrace", Func, 5}, - {"StopTrace", Func, 5}, - {"ThreadCreateProfile", Func, 0}, - {"TypeAssertionError", Type, 0}, - {"UnlockOSThread", Func, 0}, - {"Version", Func, 0}, + {"(*BlockProfileRecord).Stack", Method, 1, ""}, + {"(*Frames).Next", Method, 7, ""}, + {"(*Func).Entry", Method, 0, ""}, + {"(*Func).FileLine", Method, 0, ""}, + {"(*Func).Name", Method, 0, ""}, + {"(*MemProfileRecord).InUseBytes", Method, 0, ""}, + {"(*MemProfileRecord).InUseObjects", Method, 0, ""}, + {"(*MemProfileRecord).Stack", Method, 0, ""}, + {"(*PanicNilError).Error", Method, 21, ""}, + {"(*PanicNilError).RuntimeError", Method, 21, ""}, + {"(*Pinner).Pin", Method, 21, ""}, + {"(*Pinner).Unpin", Method, 21, ""}, + {"(*StackRecord).Stack", Method, 0, ""}, + {"(*TypeAssertionError).Error", Method, 0, ""}, + {"(*TypeAssertionError).RuntimeError", Method, 0, ""}, + {"(Cleanup).Stop", Method, 24, ""}, + {"AddCleanup", Func, 24, "func[T, S any](ptr *T, cleanup func(S), arg S) Cleanup"}, + {"BlockProfile", Func, 1, "func(p []BlockProfileRecord) (n int, ok bool)"}, + {"BlockProfileRecord", Type, 1, ""}, + {"BlockProfileRecord.Count", Field, 1, ""}, + {"BlockProfileRecord.Cycles", Field, 1, ""}, + {"BlockProfileRecord.StackRecord", Field, 1, ""}, + {"Breakpoint", Func, 0, "func()"}, + {"CPUProfile", Func, 0, "func() []byte"}, + {"Caller", Func, 0, "func(skip int) (pc uintptr, file string, line int, ok bool)"}, + {"Callers", Func, 0, "func(skip int, pc []uintptr) int"}, + {"CallersFrames", Func, 7, "func(callers []uintptr) *Frames"}, + {"Cleanup", Type, 24, ""}, + {"Compiler", Const, 0, ""}, + {"Error", Type, 0, ""}, + {"Frame", Type, 7, ""}, + {"Frame.Entry", Field, 7, ""}, + {"Frame.File", Field, 7, ""}, + {"Frame.Func", Field, 7, ""}, + {"Frame.Function", Field, 7, ""}, + {"Frame.Line", Field, 7, ""}, + {"Frame.PC", Field, 7, ""}, + {"Frames", Type, 7, ""}, + {"Func", Type, 0, ""}, + {"FuncForPC", Func, 0, "func(pc uintptr) *Func"}, + {"GC", Func, 0, "func()"}, + {"GOARCH", Const, 0, ""}, + {"GOMAXPROCS", Func, 0, "func(n int) int"}, + {"GOOS", Const, 0, ""}, + {"GOROOT", Func, 0, "func() string"}, + {"Goexit", Func, 0, "func()"}, + {"GoroutineProfile", Func, 0, "func(p []StackRecord) (n int, ok bool)"}, + {"Gosched", Func, 0, "func()"}, + {"KeepAlive", Func, 7, "func(x any)"}, + {"LockOSThread", Func, 0, "func()"}, + {"MemProfile", Func, 0, "func(p []MemProfileRecord, inuseZero bool) (n int, ok bool)"}, + {"MemProfileRate", Var, 0, ""}, + {"MemProfileRecord", Type, 0, ""}, + {"MemProfileRecord.AllocBytes", Field, 0, ""}, + {"MemProfileRecord.AllocObjects", Field, 0, ""}, + {"MemProfileRecord.FreeBytes", Field, 0, ""}, + {"MemProfileRecord.FreeObjects", Field, 0, ""}, + {"MemProfileRecord.Stack0", Field, 0, ""}, + {"MemStats", Type, 0, ""}, + {"MemStats.Alloc", Field, 0, ""}, + {"MemStats.BuckHashSys", Field, 0, ""}, + {"MemStats.BySize", Field, 0, ""}, + {"MemStats.DebugGC", Field, 0, ""}, + {"MemStats.EnableGC", Field, 0, ""}, + {"MemStats.Frees", Field, 0, ""}, + {"MemStats.GCCPUFraction", Field, 5, ""}, + {"MemStats.GCSys", Field, 2, ""}, + {"MemStats.HeapAlloc", Field, 0, ""}, + {"MemStats.HeapIdle", Field, 0, ""}, + {"MemStats.HeapInuse", Field, 0, ""}, + {"MemStats.HeapObjects", Field, 0, ""}, + {"MemStats.HeapReleased", Field, 0, ""}, + {"MemStats.HeapSys", Field, 0, ""}, + {"MemStats.LastGC", Field, 0, ""}, + {"MemStats.Lookups", Field, 0, ""}, + {"MemStats.MCacheInuse", Field, 0, ""}, + {"MemStats.MCacheSys", Field, 0, ""}, + {"MemStats.MSpanInuse", Field, 0, ""}, + {"MemStats.MSpanSys", Field, 0, ""}, + {"MemStats.Mallocs", Field, 0, ""}, + {"MemStats.NextGC", Field, 0, ""}, + {"MemStats.NumForcedGC", Field, 8, ""}, + {"MemStats.NumGC", Field, 0, ""}, + {"MemStats.OtherSys", Field, 2, ""}, + {"MemStats.PauseEnd", Field, 4, ""}, + {"MemStats.PauseNs", Field, 0, ""}, + {"MemStats.PauseTotalNs", Field, 0, ""}, + {"MemStats.StackInuse", Field, 0, ""}, + {"MemStats.StackSys", Field, 0, ""}, + {"MemStats.Sys", Field, 0, ""}, + {"MemStats.TotalAlloc", Field, 0, ""}, + {"MutexProfile", Func, 8, "func(p []BlockProfileRecord) (n int, ok bool)"}, + {"NumCPU", Func, 0, "func() int"}, + {"NumCgoCall", Func, 0, "func() int64"}, + {"NumGoroutine", Func, 0, "func() int"}, + {"PanicNilError", Type, 21, ""}, + {"Pinner", Type, 21, ""}, + {"ReadMemStats", Func, 0, "func(m *MemStats)"}, + {"ReadTrace", Func, 5, "func() []byte"}, + {"SetBlockProfileRate", Func, 1, "func(rate int)"}, + {"SetCPUProfileRate", Func, 0, "func(hz int)"}, + {"SetCgoTraceback", Func, 7, "func(version int, traceback unsafe.Pointer, context unsafe.Pointer, symbolizer unsafe.Pointer)"}, + {"SetFinalizer", Func, 0, "func(obj any, finalizer any)"}, + {"SetMutexProfileFraction", Func, 8, "func(rate int) int"}, + {"Stack", Func, 0, "func(buf []byte, all bool) int"}, + {"StackRecord", Type, 0, ""}, + {"StackRecord.Stack0", Field, 0, ""}, + {"StartTrace", Func, 5, "func() error"}, + {"StopTrace", Func, 5, "func()"}, + {"ThreadCreateProfile", Func, 0, "func(p []StackRecord) (n int, ok bool)"}, + {"TypeAssertionError", Type, 0, ""}, + {"UnlockOSThread", Func, 0, "func()"}, + {"Version", Func, 0, "func() string"}, }, "runtime/cgo": { - {"(Handle).Delete", Method, 17}, - {"(Handle).Value", Method, 17}, - {"Handle", Type, 17}, - {"Incomplete", Type, 20}, - {"NewHandle", Func, 17}, + {"(Handle).Delete", Method, 17, ""}, + {"(Handle).Value", Method, 17, ""}, + {"Handle", Type, 17, ""}, + {"Incomplete", Type, 20, ""}, + {"NewHandle", Func, 17, ""}, }, "runtime/coverage": { - {"ClearCounters", Func, 20}, - {"WriteCounters", Func, 20}, - {"WriteCountersDir", Func, 20}, - {"WriteMeta", Func, 20}, - {"WriteMetaDir", Func, 20}, + {"ClearCounters", Func, 20, "func() error"}, + {"WriteCounters", Func, 20, "func(w io.Writer) error"}, + {"WriteCountersDir", Func, 20, "func(dir string) error"}, + {"WriteMeta", Func, 20, "func(w io.Writer) error"}, + {"WriteMetaDir", Func, 20, "func(dir string) error"}, }, "runtime/debug": { - {"(*BuildInfo).String", Method, 18}, - {"BuildInfo", Type, 12}, - {"BuildInfo.Deps", Field, 12}, - {"BuildInfo.GoVersion", Field, 18}, - {"BuildInfo.Main", Field, 12}, - {"BuildInfo.Path", Field, 12}, - {"BuildInfo.Settings", Field, 18}, - {"BuildSetting", Type, 18}, - {"BuildSetting.Key", Field, 18}, - {"BuildSetting.Value", Field, 18}, - {"CrashOptions", Type, 23}, - {"FreeOSMemory", Func, 1}, - {"GCStats", Type, 1}, - {"GCStats.LastGC", Field, 1}, - {"GCStats.NumGC", Field, 1}, - {"GCStats.Pause", Field, 1}, - {"GCStats.PauseEnd", Field, 4}, - {"GCStats.PauseQuantiles", Field, 1}, - {"GCStats.PauseTotal", Field, 1}, - {"Module", Type, 12}, - {"Module.Path", Field, 12}, - {"Module.Replace", Field, 12}, - {"Module.Sum", Field, 12}, - {"Module.Version", Field, 12}, - {"ParseBuildInfo", Func, 18}, - {"PrintStack", Func, 0}, - {"ReadBuildInfo", Func, 12}, - {"ReadGCStats", Func, 1}, - {"SetCrashOutput", Func, 23}, - {"SetGCPercent", Func, 1}, - {"SetMaxStack", Func, 2}, - {"SetMaxThreads", Func, 2}, - {"SetMemoryLimit", Func, 19}, - {"SetPanicOnFault", Func, 3}, - {"SetTraceback", Func, 6}, - {"Stack", Func, 0}, - {"WriteHeapDump", Func, 3}, + {"(*BuildInfo).String", Method, 18, ""}, + {"BuildInfo", Type, 12, ""}, + {"BuildInfo.Deps", Field, 12, ""}, + {"BuildInfo.GoVersion", Field, 18, ""}, + {"BuildInfo.Main", Field, 12, ""}, + {"BuildInfo.Path", Field, 12, ""}, + {"BuildInfo.Settings", Field, 18, ""}, + {"BuildSetting", Type, 18, ""}, + {"BuildSetting.Key", Field, 18, ""}, + {"BuildSetting.Value", Field, 18, ""}, + {"CrashOptions", Type, 23, ""}, + {"FreeOSMemory", Func, 1, "func()"}, + {"GCStats", Type, 1, ""}, + {"GCStats.LastGC", Field, 1, ""}, + {"GCStats.NumGC", Field, 1, ""}, + {"GCStats.Pause", Field, 1, ""}, + {"GCStats.PauseEnd", Field, 4, ""}, + {"GCStats.PauseQuantiles", Field, 1, ""}, + {"GCStats.PauseTotal", Field, 1, ""}, + {"Module", Type, 12, ""}, + {"Module.Path", Field, 12, ""}, + {"Module.Replace", Field, 12, ""}, + {"Module.Sum", Field, 12, ""}, + {"Module.Version", Field, 12, ""}, + {"ParseBuildInfo", Func, 18, "func(data string) (bi *BuildInfo, err error)"}, + {"PrintStack", Func, 0, "func()"}, + {"ReadBuildInfo", Func, 12, "func() (info *BuildInfo, ok bool)"}, + {"ReadGCStats", Func, 1, "func(stats *GCStats)"}, + {"SetCrashOutput", Func, 23, "func(f *os.File, opts CrashOptions) error"}, + {"SetGCPercent", Func, 1, "func(percent int) int"}, + {"SetMaxStack", Func, 2, "func(bytes int) int"}, + {"SetMaxThreads", Func, 2, "func(threads int) int"}, + {"SetMemoryLimit", Func, 19, "func(limit int64) int64"}, + {"SetPanicOnFault", Func, 3, "func(enabled bool) bool"}, + {"SetTraceback", Func, 6, "func(level string)"}, + {"Stack", Func, 0, "func() []byte"}, + {"WriteHeapDump", Func, 3, "func(fd uintptr)"}, }, "runtime/metrics": { - {"(Value).Float64", Method, 16}, - {"(Value).Float64Histogram", Method, 16}, - {"(Value).Kind", Method, 16}, - {"(Value).Uint64", Method, 16}, - {"All", Func, 16}, - {"Description", Type, 16}, - {"Description.Cumulative", Field, 16}, - {"Description.Description", Field, 16}, - {"Description.Kind", Field, 16}, - {"Description.Name", Field, 16}, - {"Float64Histogram", Type, 16}, - {"Float64Histogram.Buckets", Field, 16}, - {"Float64Histogram.Counts", Field, 16}, - {"KindBad", Const, 16}, - {"KindFloat64", Const, 16}, - {"KindFloat64Histogram", Const, 16}, - {"KindUint64", Const, 16}, - {"Read", Func, 16}, - {"Sample", Type, 16}, - {"Sample.Name", Field, 16}, - {"Sample.Value", Field, 16}, - {"Value", Type, 16}, - {"ValueKind", Type, 16}, + {"(Value).Float64", Method, 16, ""}, + {"(Value).Float64Histogram", Method, 16, ""}, + {"(Value).Kind", Method, 16, ""}, + {"(Value).Uint64", Method, 16, ""}, + {"All", Func, 16, "func() []Description"}, + {"Description", Type, 16, ""}, + {"Description.Cumulative", Field, 16, ""}, + {"Description.Description", Field, 16, ""}, + {"Description.Kind", Field, 16, ""}, + {"Description.Name", Field, 16, ""}, + {"Float64Histogram", Type, 16, ""}, + {"Float64Histogram.Buckets", Field, 16, ""}, + {"Float64Histogram.Counts", Field, 16, ""}, + {"KindBad", Const, 16, ""}, + {"KindFloat64", Const, 16, ""}, + {"KindFloat64Histogram", Const, 16, ""}, + {"KindUint64", Const, 16, ""}, + {"Read", Func, 16, "func(m []Sample)"}, + {"Sample", Type, 16, ""}, + {"Sample.Name", Field, 16, ""}, + {"Sample.Value", Field, 16, ""}, + {"Value", Type, 16, ""}, + {"ValueKind", Type, 16, ""}, }, "runtime/pprof": { - {"(*Profile).Add", Method, 0}, - {"(*Profile).Count", Method, 0}, - {"(*Profile).Name", Method, 0}, - {"(*Profile).Remove", Method, 0}, - {"(*Profile).WriteTo", Method, 0}, - {"Do", Func, 9}, - {"ForLabels", Func, 9}, - {"Label", Func, 9}, - {"LabelSet", Type, 9}, - {"Labels", Func, 9}, - {"Lookup", Func, 0}, - {"NewProfile", Func, 0}, - {"Profile", Type, 0}, - {"Profiles", Func, 0}, - {"SetGoroutineLabels", Func, 9}, - {"StartCPUProfile", Func, 0}, - {"StopCPUProfile", Func, 0}, - {"WithLabels", Func, 9}, - {"WriteHeapProfile", Func, 0}, + {"(*Profile).Add", Method, 0, ""}, + {"(*Profile).Count", Method, 0, ""}, + {"(*Profile).Name", Method, 0, ""}, + {"(*Profile).Remove", Method, 0, ""}, + {"(*Profile).WriteTo", Method, 0, ""}, + {"Do", Func, 9, "func(ctx context.Context, labels LabelSet, f func(context.Context))"}, + {"ForLabels", Func, 9, "func(ctx context.Context, f func(key string, value string) bool)"}, + {"Label", Func, 9, "func(ctx context.Context, key string) (string, bool)"}, + {"LabelSet", Type, 9, ""}, + {"Labels", Func, 9, "func(args ...string) LabelSet"}, + {"Lookup", Func, 0, "func(name string) *Profile"}, + {"NewProfile", Func, 0, "func(name string) *Profile"}, + {"Profile", Type, 0, ""}, + {"Profiles", Func, 0, "func() []*Profile"}, + {"SetGoroutineLabels", Func, 9, "func(ctx context.Context)"}, + {"StartCPUProfile", Func, 0, "func(w io.Writer) error"}, + {"StopCPUProfile", Func, 0, "func()"}, + {"WithLabels", Func, 9, "func(ctx context.Context, labels LabelSet) context.Context"}, + {"WriteHeapProfile", Func, 0, "func(w io.Writer) error"}, }, "runtime/trace": { - {"(*Region).End", Method, 11}, - {"(*Task).End", Method, 11}, - {"IsEnabled", Func, 11}, - {"Log", Func, 11}, - {"Logf", Func, 11}, - {"NewTask", Func, 11}, - {"Region", Type, 11}, - {"Start", Func, 5}, - {"StartRegion", Func, 11}, - {"Stop", Func, 5}, - {"Task", Type, 11}, - {"WithRegion", Func, 11}, + {"(*Region).End", Method, 11, ""}, + {"(*Task).End", Method, 11, ""}, + {"IsEnabled", Func, 11, "func() bool"}, + {"Log", Func, 11, "func(ctx context.Context, category string, message string)"}, + {"Logf", Func, 11, "func(ctx context.Context, category string, format string, args ...any)"}, + {"NewTask", Func, 11, "func(pctx context.Context, taskType string) (ctx context.Context, task *Task)"}, + {"Region", Type, 11, ""}, + {"Start", Func, 5, "func(w io.Writer) error"}, + {"StartRegion", Func, 11, "func(ctx context.Context, regionType string) *Region"}, + {"Stop", Func, 5, "func()"}, + {"Task", Type, 11, ""}, + {"WithRegion", Func, 11, "func(ctx context.Context, regionType string, fn func())"}, }, "slices": { - {"All", Func, 23}, - {"AppendSeq", Func, 23}, - {"Backward", Func, 23}, - {"BinarySearch", Func, 21}, - {"BinarySearchFunc", Func, 21}, - {"Chunk", Func, 23}, - {"Clip", Func, 21}, - {"Clone", Func, 21}, - {"Collect", Func, 23}, - {"Compact", Func, 21}, - {"CompactFunc", Func, 21}, - {"Compare", Func, 21}, - {"CompareFunc", Func, 21}, - {"Concat", Func, 22}, - {"Contains", Func, 21}, - {"ContainsFunc", Func, 21}, - {"Delete", Func, 21}, - {"DeleteFunc", Func, 21}, - {"Equal", Func, 21}, - {"EqualFunc", Func, 21}, - {"Grow", Func, 21}, - {"Index", Func, 21}, - {"IndexFunc", Func, 21}, - {"Insert", Func, 21}, - {"IsSorted", Func, 21}, - {"IsSortedFunc", Func, 21}, - {"Max", Func, 21}, - {"MaxFunc", Func, 21}, - {"Min", Func, 21}, - {"MinFunc", Func, 21}, - {"Repeat", Func, 23}, - {"Replace", Func, 21}, - {"Reverse", Func, 21}, - {"Sort", Func, 21}, - {"SortFunc", Func, 21}, - {"SortStableFunc", Func, 21}, - {"Sorted", Func, 23}, - {"SortedFunc", Func, 23}, - {"SortedStableFunc", Func, 23}, - {"Values", Func, 23}, + {"All", Func, 23, "func[Slice ~[]E, E any](s Slice) iter.Seq2[int, E]"}, + {"AppendSeq", Func, 23, "func[Slice ~[]E, E any](s Slice, seq iter.Seq[E]) Slice"}, + {"Backward", Func, 23, "func[Slice ~[]E, E any](s Slice) iter.Seq2[int, E]"}, + {"BinarySearch", Func, 21, "func[S ~[]E, E cmp.Ordered](x S, target E) (int, bool)"}, + {"BinarySearchFunc", Func, 21, "func[S ~[]E, E, T any](x S, target T, cmp func(E, T) int) (int, bool)"}, + {"Chunk", Func, 23, "func[Slice ~[]E, E any](s Slice, n int) iter.Seq[Slice]"}, + {"Clip", Func, 21, "func[S ~[]E, E any](s S) S"}, + {"Clone", Func, 21, "func[S ~[]E, E any](s S) S"}, + {"Collect", Func, 23, "func[E any](seq iter.Seq[E]) []E"}, + {"Compact", Func, 21, "func[S ~[]E, E comparable](s S) S"}, + {"CompactFunc", Func, 21, "func[S ~[]E, E any](s S, eq func(E, E) bool) S"}, + {"Compare", Func, 21, "func[S ~[]E, E cmp.Ordered](s1 S, s2 S) int"}, + {"CompareFunc", Func, 21, "func[S1 ~[]E1, S2 ~[]E2, E1, E2 any](s1 S1, s2 S2, cmp func(E1, E2) int) int"}, + {"Concat", Func, 22, "func[S ~[]E, E any](slices ...S) S"}, + {"Contains", Func, 21, "func[S ~[]E, E comparable](s S, v E) bool"}, + {"ContainsFunc", Func, 21, "func[S ~[]E, E any](s S, f func(E) bool) bool"}, + {"Delete", Func, 21, "func[S ~[]E, E any](s S, i int, j int) S"}, + {"DeleteFunc", Func, 21, "func[S ~[]E, E any](s S, del func(E) bool) S"}, + {"Equal", Func, 21, "func[S ~[]E, E comparable](s1 S, s2 S) bool"}, + {"EqualFunc", Func, 21, "func[S1 ~[]E1, S2 ~[]E2, E1, E2 any](s1 S1, s2 S2, eq func(E1, E2) bool) bool"}, + {"Grow", Func, 21, "func[S ~[]E, E any](s S, n int) S"}, + {"Index", Func, 21, "func[S ~[]E, E comparable](s S, v E) int"}, + {"IndexFunc", Func, 21, "func[S ~[]E, E any](s S, f func(E) bool) int"}, + {"Insert", Func, 21, "func[S ~[]E, E any](s S, i int, v ...E) S"}, + {"IsSorted", Func, 21, "func[S ~[]E, E cmp.Ordered](x S) bool"}, + {"IsSortedFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int) bool"}, + {"Max", Func, 21, "func[S ~[]E, E cmp.Ordered](x S) E"}, + {"MaxFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int) E"}, + {"Min", Func, 21, "func[S ~[]E, E cmp.Ordered](x S) E"}, + {"MinFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int) E"}, + {"Repeat", Func, 23, "func[S ~[]E, E any](x S, count int) S"}, + {"Replace", Func, 21, "func[S ~[]E, E any](s S, i int, j int, v ...E) S"}, + {"Reverse", Func, 21, "func[S ~[]E, E any](s S)"}, + {"Sort", Func, 21, "func[S ~[]E, E cmp.Ordered](x S)"}, + {"SortFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int)"}, + {"SortStableFunc", Func, 21, "func[S ~[]E, E any](x S, cmp func(a E, b E) int)"}, + {"Sorted", Func, 23, "func[E cmp.Ordered](seq iter.Seq[E]) []E"}, + {"SortedFunc", Func, 23, "func[E any](seq iter.Seq[E], cmp func(E, E) int) []E"}, + {"SortedStableFunc", Func, 23, "func[E any](seq iter.Seq[E], cmp func(E, E) int) []E"}, + {"Values", Func, 23, "func[Slice ~[]E, E any](s Slice) iter.Seq[E]"}, }, "sort": { - {"(Float64Slice).Len", Method, 0}, - {"(Float64Slice).Less", Method, 0}, - {"(Float64Slice).Search", Method, 0}, - {"(Float64Slice).Sort", Method, 0}, - {"(Float64Slice).Swap", Method, 0}, - {"(IntSlice).Len", Method, 0}, - {"(IntSlice).Less", Method, 0}, - {"(IntSlice).Search", Method, 0}, - {"(IntSlice).Sort", Method, 0}, - {"(IntSlice).Swap", Method, 0}, - {"(StringSlice).Len", Method, 0}, - {"(StringSlice).Less", Method, 0}, - {"(StringSlice).Search", Method, 0}, - {"(StringSlice).Sort", Method, 0}, - {"(StringSlice).Swap", Method, 0}, - {"Find", Func, 19}, - {"Float64Slice", Type, 0}, - {"Float64s", Func, 0}, - {"Float64sAreSorted", Func, 0}, - {"IntSlice", Type, 0}, - {"Interface", Type, 0}, - {"Ints", Func, 0}, - {"IntsAreSorted", Func, 0}, - {"IsSorted", Func, 0}, - {"Reverse", Func, 1}, - {"Search", Func, 0}, - {"SearchFloat64s", Func, 0}, - {"SearchInts", Func, 0}, - {"SearchStrings", Func, 0}, - {"Slice", Func, 8}, - {"SliceIsSorted", Func, 8}, - {"SliceStable", Func, 8}, - {"Sort", Func, 0}, - {"Stable", Func, 2}, - {"StringSlice", Type, 0}, - {"Strings", Func, 0}, - {"StringsAreSorted", Func, 0}, + {"(Float64Slice).Len", Method, 0, ""}, + {"(Float64Slice).Less", Method, 0, ""}, + {"(Float64Slice).Search", Method, 0, ""}, + {"(Float64Slice).Sort", Method, 0, ""}, + {"(Float64Slice).Swap", Method, 0, ""}, + {"(IntSlice).Len", Method, 0, ""}, + {"(IntSlice).Less", Method, 0, ""}, + {"(IntSlice).Search", Method, 0, ""}, + {"(IntSlice).Sort", Method, 0, ""}, + {"(IntSlice).Swap", Method, 0, ""}, + {"(StringSlice).Len", Method, 0, ""}, + {"(StringSlice).Less", Method, 0, ""}, + {"(StringSlice).Search", Method, 0, ""}, + {"(StringSlice).Sort", Method, 0, ""}, + {"(StringSlice).Swap", Method, 0, ""}, + {"Find", Func, 19, "func(n int, cmp func(int) int) (i int, found bool)"}, + {"Float64Slice", Type, 0, ""}, + {"Float64s", Func, 0, "func(x []float64)"}, + {"Float64sAreSorted", Func, 0, "func(x []float64) bool"}, + {"IntSlice", Type, 0, ""}, + {"Interface", Type, 0, ""}, + {"Ints", Func, 0, "func(x []int)"}, + {"IntsAreSorted", Func, 0, "func(x []int) bool"}, + {"IsSorted", Func, 0, "func(data Interface) bool"}, + {"Reverse", Func, 1, "func(data Interface) Interface"}, + {"Search", Func, 0, "func(n int, f func(int) bool) int"}, + {"SearchFloat64s", Func, 0, "func(a []float64, x float64) int"}, + {"SearchInts", Func, 0, "func(a []int, x int) int"}, + {"SearchStrings", Func, 0, "func(a []string, x string) int"}, + {"Slice", Func, 8, "func(x any, less func(i int, j int) bool)"}, + {"SliceIsSorted", Func, 8, "func(x any, less func(i int, j int) bool) bool"}, + {"SliceStable", Func, 8, "func(x any, less func(i int, j int) bool)"}, + {"Sort", Func, 0, "func(data Interface)"}, + {"Stable", Func, 2, "func(data Interface)"}, + {"StringSlice", Type, 0, ""}, + {"Strings", Func, 0, "func(x []string)"}, + {"StringsAreSorted", Func, 0, "func(x []string) bool"}, }, "strconv": { - {"(*NumError).Error", Method, 0}, - {"(*NumError).Unwrap", Method, 14}, - {"AppendBool", Func, 0}, - {"AppendFloat", Func, 0}, - {"AppendInt", Func, 0}, - {"AppendQuote", Func, 0}, - {"AppendQuoteRune", Func, 0}, - {"AppendQuoteRuneToASCII", Func, 0}, - {"AppendQuoteRuneToGraphic", Func, 6}, - {"AppendQuoteToASCII", Func, 0}, - {"AppendQuoteToGraphic", Func, 6}, - {"AppendUint", Func, 0}, - {"Atoi", Func, 0}, - {"CanBackquote", Func, 0}, - {"ErrRange", Var, 0}, - {"ErrSyntax", Var, 0}, - {"FormatBool", Func, 0}, - {"FormatComplex", Func, 15}, - {"FormatFloat", Func, 0}, - {"FormatInt", Func, 0}, - {"FormatUint", Func, 0}, - {"IntSize", Const, 0}, - {"IsGraphic", Func, 6}, - {"IsPrint", Func, 0}, - {"Itoa", Func, 0}, - {"NumError", Type, 0}, - {"NumError.Err", Field, 0}, - {"NumError.Func", Field, 0}, - {"NumError.Num", Field, 0}, - {"ParseBool", Func, 0}, - {"ParseComplex", Func, 15}, - {"ParseFloat", Func, 0}, - {"ParseInt", Func, 0}, - {"ParseUint", Func, 0}, - {"Quote", Func, 0}, - {"QuoteRune", Func, 0}, - {"QuoteRuneToASCII", Func, 0}, - {"QuoteRuneToGraphic", Func, 6}, - {"QuoteToASCII", Func, 0}, - {"QuoteToGraphic", Func, 6}, - {"QuotedPrefix", Func, 17}, - {"Unquote", Func, 0}, - {"UnquoteChar", Func, 0}, + {"(*NumError).Error", Method, 0, ""}, + {"(*NumError).Unwrap", Method, 14, ""}, + {"AppendBool", Func, 0, "func(dst []byte, b bool) []byte"}, + {"AppendFloat", Func, 0, "func(dst []byte, f float64, fmt byte, prec int, bitSize int) []byte"}, + {"AppendInt", Func, 0, "func(dst []byte, i int64, base int) []byte"}, + {"AppendQuote", Func, 0, "func(dst []byte, s string) []byte"}, + {"AppendQuoteRune", Func, 0, "func(dst []byte, r rune) []byte"}, + {"AppendQuoteRuneToASCII", Func, 0, "func(dst []byte, r rune) []byte"}, + {"AppendQuoteRuneToGraphic", Func, 6, "func(dst []byte, r rune) []byte"}, + {"AppendQuoteToASCII", Func, 0, "func(dst []byte, s string) []byte"}, + {"AppendQuoteToGraphic", Func, 6, "func(dst []byte, s string) []byte"}, + {"AppendUint", Func, 0, "func(dst []byte, i uint64, base int) []byte"}, + {"Atoi", Func, 0, "func(s string) (int, error)"}, + {"CanBackquote", Func, 0, "func(s string) bool"}, + {"ErrRange", Var, 0, ""}, + {"ErrSyntax", Var, 0, ""}, + {"FormatBool", Func, 0, "func(b bool) string"}, + {"FormatComplex", Func, 15, "func(c complex128, fmt byte, prec int, bitSize int) string"}, + {"FormatFloat", Func, 0, "func(f float64, fmt byte, prec int, bitSize int) string"}, + {"FormatInt", Func, 0, "func(i int64, base int) string"}, + {"FormatUint", Func, 0, "func(i uint64, base int) string"}, + {"IntSize", Const, 0, ""}, + {"IsGraphic", Func, 6, "func(r rune) bool"}, + {"IsPrint", Func, 0, "func(r rune) bool"}, + {"Itoa", Func, 0, "func(i int) string"}, + {"NumError", Type, 0, ""}, + {"NumError.Err", Field, 0, ""}, + {"NumError.Func", Field, 0, ""}, + {"NumError.Num", Field, 0, ""}, + {"ParseBool", Func, 0, "func(str string) (bool, error)"}, + {"ParseComplex", Func, 15, "func(s string, bitSize int) (complex128, error)"}, + {"ParseFloat", Func, 0, "func(s string, bitSize int) (float64, error)"}, + {"ParseInt", Func, 0, "func(s string, base int, bitSize int) (i int64, err error)"}, + {"ParseUint", Func, 0, "func(s string, base int, bitSize int) (uint64, error)"}, + {"Quote", Func, 0, "func(s string) string"}, + {"QuoteRune", Func, 0, "func(r rune) string"}, + {"QuoteRuneToASCII", Func, 0, "func(r rune) string"}, + {"QuoteRuneToGraphic", Func, 6, "func(r rune) string"}, + {"QuoteToASCII", Func, 0, "func(s string) string"}, + {"QuoteToGraphic", Func, 6, "func(s string) string"}, + {"QuotedPrefix", Func, 17, "func(s string) (string, error)"}, + {"Unquote", Func, 0, "func(s string) (string, error)"}, + {"UnquoteChar", Func, 0, "func(s string, quote byte) (value rune, multibyte bool, tail string, err error)"}, }, "strings": { - {"(*Builder).Cap", Method, 12}, - {"(*Builder).Grow", Method, 10}, - {"(*Builder).Len", Method, 10}, - {"(*Builder).Reset", Method, 10}, - {"(*Builder).String", Method, 10}, - {"(*Builder).Write", Method, 10}, - {"(*Builder).WriteByte", Method, 10}, - {"(*Builder).WriteRune", Method, 10}, - {"(*Builder).WriteString", Method, 10}, - {"(*Reader).Len", Method, 0}, - {"(*Reader).Read", Method, 0}, - {"(*Reader).ReadAt", Method, 0}, - {"(*Reader).ReadByte", Method, 0}, - {"(*Reader).ReadRune", Method, 0}, - {"(*Reader).Reset", Method, 7}, - {"(*Reader).Seek", Method, 0}, - {"(*Reader).Size", Method, 5}, - {"(*Reader).UnreadByte", Method, 0}, - {"(*Reader).UnreadRune", Method, 0}, - {"(*Reader).WriteTo", Method, 1}, - {"(*Replacer).Replace", Method, 0}, - {"(*Replacer).WriteString", Method, 0}, - {"Builder", Type, 10}, - {"Clone", Func, 18}, - {"Compare", Func, 5}, - {"Contains", Func, 0}, - {"ContainsAny", Func, 0}, - {"ContainsFunc", Func, 21}, - {"ContainsRune", Func, 0}, - {"Count", Func, 0}, - {"Cut", Func, 18}, - {"CutPrefix", Func, 20}, - {"CutSuffix", Func, 20}, - {"EqualFold", Func, 0}, - {"Fields", Func, 0}, - {"FieldsFunc", Func, 0}, - {"FieldsFuncSeq", Func, 24}, - {"FieldsSeq", Func, 24}, - {"HasPrefix", Func, 0}, - {"HasSuffix", Func, 0}, - {"Index", Func, 0}, - {"IndexAny", Func, 0}, - {"IndexByte", Func, 2}, - {"IndexFunc", Func, 0}, - {"IndexRune", Func, 0}, - {"Join", Func, 0}, - {"LastIndex", Func, 0}, - {"LastIndexAny", Func, 0}, - {"LastIndexByte", Func, 5}, - {"LastIndexFunc", Func, 0}, - {"Lines", Func, 24}, - {"Map", Func, 0}, - {"NewReader", Func, 0}, - {"NewReplacer", Func, 0}, - {"Reader", Type, 0}, - {"Repeat", Func, 0}, - {"Replace", Func, 0}, - {"ReplaceAll", Func, 12}, - {"Replacer", Type, 0}, - {"Split", Func, 0}, - {"SplitAfter", Func, 0}, - {"SplitAfterN", Func, 0}, - {"SplitAfterSeq", Func, 24}, - {"SplitN", Func, 0}, - {"SplitSeq", Func, 24}, - {"Title", Func, 0}, - {"ToLower", Func, 0}, - {"ToLowerSpecial", Func, 0}, - {"ToTitle", Func, 0}, - {"ToTitleSpecial", Func, 0}, - {"ToUpper", Func, 0}, - {"ToUpperSpecial", Func, 0}, - {"ToValidUTF8", Func, 13}, - {"Trim", Func, 0}, - {"TrimFunc", Func, 0}, - {"TrimLeft", Func, 0}, - {"TrimLeftFunc", Func, 0}, - {"TrimPrefix", Func, 1}, - {"TrimRight", Func, 0}, - {"TrimRightFunc", Func, 0}, - {"TrimSpace", Func, 0}, - {"TrimSuffix", Func, 1}, + {"(*Builder).Cap", Method, 12, ""}, + {"(*Builder).Grow", Method, 10, ""}, + {"(*Builder).Len", Method, 10, ""}, + {"(*Builder).Reset", Method, 10, ""}, + {"(*Builder).String", Method, 10, ""}, + {"(*Builder).Write", Method, 10, ""}, + {"(*Builder).WriteByte", Method, 10, ""}, + {"(*Builder).WriteRune", Method, 10, ""}, + {"(*Builder).WriteString", Method, 10, ""}, + {"(*Reader).Len", Method, 0, ""}, + {"(*Reader).Read", Method, 0, ""}, + {"(*Reader).ReadAt", Method, 0, ""}, + {"(*Reader).ReadByte", Method, 0, ""}, + {"(*Reader).ReadRune", Method, 0, ""}, + {"(*Reader).Reset", Method, 7, ""}, + {"(*Reader).Seek", Method, 0, ""}, + {"(*Reader).Size", Method, 5, ""}, + {"(*Reader).UnreadByte", Method, 0, ""}, + {"(*Reader).UnreadRune", Method, 0, ""}, + {"(*Reader).WriteTo", Method, 1, ""}, + {"(*Replacer).Replace", Method, 0, ""}, + {"(*Replacer).WriteString", Method, 0, ""}, + {"Builder", Type, 10, ""}, + {"Clone", Func, 18, "func(s string) string"}, + {"Compare", Func, 5, "func(a string, b string) int"}, + {"Contains", Func, 0, "func(s string, substr string) bool"}, + {"ContainsAny", Func, 0, "func(s string, chars string) bool"}, + {"ContainsFunc", Func, 21, "func(s string, f func(rune) bool) bool"}, + {"ContainsRune", Func, 0, "func(s string, r rune) bool"}, + {"Count", Func, 0, "func(s string, substr string) int"}, + {"Cut", Func, 18, "func(s string, sep string) (before string, after string, found bool)"}, + {"CutPrefix", Func, 20, "func(s string, prefix string) (after string, found bool)"}, + {"CutSuffix", Func, 20, "func(s string, suffix string) (before string, found bool)"}, + {"EqualFold", Func, 0, "func(s string, t string) bool"}, + {"Fields", Func, 0, "func(s string) []string"}, + {"FieldsFunc", Func, 0, "func(s string, f func(rune) bool) []string"}, + {"FieldsFuncSeq", Func, 24, "func(s string, f func(rune) bool) iter.Seq[string]"}, + {"FieldsSeq", Func, 24, "func(s string) iter.Seq[string]"}, + {"HasPrefix", Func, 0, "func(s string, prefix string) bool"}, + {"HasSuffix", Func, 0, "func(s string, suffix string) bool"}, + {"Index", Func, 0, "func(s string, substr string) int"}, + {"IndexAny", Func, 0, "func(s string, chars string) int"}, + {"IndexByte", Func, 2, "func(s string, c byte) int"}, + {"IndexFunc", Func, 0, "func(s string, f func(rune) bool) int"}, + {"IndexRune", Func, 0, "func(s string, r rune) int"}, + {"Join", Func, 0, "func(elems []string, sep string) string"}, + {"LastIndex", Func, 0, "func(s string, substr string) int"}, + {"LastIndexAny", Func, 0, "func(s string, chars string) int"}, + {"LastIndexByte", Func, 5, "func(s string, c byte) int"}, + {"LastIndexFunc", Func, 0, "func(s string, f func(rune) bool) int"}, + {"Lines", Func, 24, "func(s string) iter.Seq[string]"}, + {"Map", Func, 0, "func(mapping func(rune) rune, s string) string"}, + {"NewReader", Func, 0, "func(s string) *Reader"}, + {"NewReplacer", Func, 0, "func(oldnew ...string) *Replacer"}, + {"Reader", Type, 0, ""}, + {"Repeat", Func, 0, "func(s string, count int) string"}, + {"Replace", Func, 0, "func(s string, old string, new string, n int) string"}, + {"ReplaceAll", Func, 12, "func(s string, old string, new string) string"}, + {"Replacer", Type, 0, ""}, + {"Split", Func, 0, "func(s string, sep string) []string"}, + {"SplitAfter", Func, 0, "func(s string, sep string) []string"}, + {"SplitAfterN", Func, 0, "func(s string, sep string, n int) []string"}, + {"SplitAfterSeq", Func, 24, "func(s string, sep string) iter.Seq[string]"}, + {"SplitN", Func, 0, "func(s string, sep string, n int) []string"}, + {"SplitSeq", Func, 24, "func(s string, sep string) iter.Seq[string]"}, + {"Title", Func, 0, "func(s string) string"}, + {"ToLower", Func, 0, "func(s string) string"}, + {"ToLowerSpecial", Func, 0, "func(c unicode.SpecialCase, s string) string"}, + {"ToTitle", Func, 0, "func(s string) string"}, + {"ToTitleSpecial", Func, 0, "func(c unicode.SpecialCase, s string) string"}, + {"ToUpper", Func, 0, "func(s string) string"}, + {"ToUpperSpecial", Func, 0, "func(c unicode.SpecialCase, s string) string"}, + {"ToValidUTF8", Func, 13, "func(s string, replacement string) string"}, + {"Trim", Func, 0, "func(s string, cutset string) string"}, + {"TrimFunc", Func, 0, "func(s string, f func(rune) bool) string"}, + {"TrimLeft", Func, 0, "func(s string, cutset string) string"}, + {"TrimLeftFunc", Func, 0, "func(s string, f func(rune) bool) string"}, + {"TrimPrefix", Func, 1, "func(s string, prefix string) string"}, + {"TrimRight", Func, 0, "func(s string, cutset string) string"}, + {"TrimRightFunc", Func, 0, "func(s string, f func(rune) bool) string"}, + {"TrimSpace", Func, 0, "func(s string) string"}, + {"TrimSuffix", Func, 1, "func(s string, suffix string) string"}, }, "structs": { - {"HostLayout", Type, 23}, + {"HostLayout", Type, 23, ""}, }, "sync": { - {"(*Cond).Broadcast", Method, 0}, - {"(*Cond).Signal", Method, 0}, - {"(*Cond).Wait", Method, 0}, - {"(*Map).Clear", Method, 23}, - {"(*Map).CompareAndDelete", Method, 20}, - {"(*Map).CompareAndSwap", Method, 20}, - {"(*Map).Delete", Method, 9}, - {"(*Map).Load", Method, 9}, - {"(*Map).LoadAndDelete", Method, 15}, - {"(*Map).LoadOrStore", Method, 9}, - {"(*Map).Range", Method, 9}, - {"(*Map).Store", Method, 9}, - {"(*Map).Swap", Method, 20}, - {"(*Mutex).Lock", Method, 0}, - {"(*Mutex).TryLock", Method, 18}, - {"(*Mutex).Unlock", Method, 0}, - {"(*Once).Do", Method, 0}, - {"(*Pool).Get", Method, 3}, - {"(*Pool).Put", Method, 3}, - {"(*RWMutex).Lock", Method, 0}, - {"(*RWMutex).RLock", Method, 0}, - {"(*RWMutex).RLocker", Method, 0}, - {"(*RWMutex).RUnlock", Method, 0}, - {"(*RWMutex).TryLock", Method, 18}, - {"(*RWMutex).TryRLock", Method, 18}, - {"(*RWMutex).Unlock", Method, 0}, - {"(*WaitGroup).Add", Method, 0}, - {"(*WaitGroup).Done", Method, 0}, - {"(*WaitGroup).Go", Method, 25}, - {"(*WaitGroup).Wait", Method, 0}, - {"Cond", Type, 0}, - {"Cond.L", Field, 0}, - {"Locker", Type, 0}, - {"Map", Type, 9}, - {"Mutex", Type, 0}, - {"NewCond", Func, 0}, - {"Once", Type, 0}, - {"OnceFunc", Func, 21}, - {"OnceValue", Func, 21}, - {"OnceValues", Func, 21}, - {"Pool", Type, 3}, - {"Pool.New", Field, 3}, - {"RWMutex", Type, 0}, - {"WaitGroup", Type, 0}, + {"(*Cond).Broadcast", Method, 0, ""}, + {"(*Cond).Signal", Method, 0, ""}, + {"(*Cond).Wait", Method, 0, ""}, + {"(*Map).Clear", Method, 23, ""}, + {"(*Map).CompareAndDelete", Method, 20, ""}, + {"(*Map).CompareAndSwap", Method, 20, ""}, + {"(*Map).Delete", Method, 9, ""}, + {"(*Map).Load", Method, 9, ""}, + {"(*Map).LoadAndDelete", Method, 15, ""}, + {"(*Map).LoadOrStore", Method, 9, ""}, + {"(*Map).Range", Method, 9, ""}, + {"(*Map).Store", Method, 9, ""}, + {"(*Map).Swap", Method, 20, ""}, + {"(*Mutex).Lock", Method, 0, ""}, + {"(*Mutex).TryLock", Method, 18, ""}, + {"(*Mutex).Unlock", Method, 0, ""}, + {"(*Once).Do", Method, 0, ""}, + {"(*Pool).Get", Method, 3, ""}, + {"(*Pool).Put", Method, 3, ""}, + {"(*RWMutex).Lock", Method, 0, ""}, + {"(*RWMutex).RLock", Method, 0, ""}, + {"(*RWMutex).RLocker", Method, 0, ""}, + {"(*RWMutex).RUnlock", Method, 0, ""}, + {"(*RWMutex).TryLock", Method, 18, ""}, + {"(*RWMutex).TryRLock", Method, 18, ""}, + {"(*RWMutex).Unlock", Method, 0, ""}, + {"(*WaitGroup).Add", Method, 0, ""}, + {"(*WaitGroup).Done", Method, 0, ""}, + {"(*WaitGroup).Go", Method, 25, ""}, + {"(*WaitGroup).Wait", Method, 0, ""}, + {"Cond", Type, 0, ""}, + {"Cond.L", Field, 0, ""}, + {"Locker", Type, 0, ""}, + {"Map", Type, 9, ""}, + {"Mutex", Type, 0, ""}, + {"NewCond", Func, 0, "func(l Locker) *Cond"}, + {"Once", Type, 0, ""}, + {"OnceFunc", Func, 21, "func(f func()) func()"}, + {"OnceValue", Func, 21, "func[T any](f func() T) func() T"}, + {"OnceValues", Func, 21, "func[T1, T2 any](f func() (T1, T2)) func() (T1, T2)"}, + {"Pool", Type, 3, ""}, + {"Pool.New", Field, 3, ""}, + {"RWMutex", Type, 0, ""}, + {"WaitGroup", Type, 0, ""}, }, "sync/atomic": { - {"(*Bool).CompareAndSwap", Method, 19}, - {"(*Bool).Load", Method, 19}, - {"(*Bool).Store", Method, 19}, - {"(*Bool).Swap", Method, 19}, - {"(*Int32).Add", Method, 19}, - {"(*Int32).And", Method, 23}, - {"(*Int32).CompareAndSwap", Method, 19}, - {"(*Int32).Load", Method, 19}, - {"(*Int32).Or", Method, 23}, - {"(*Int32).Store", Method, 19}, - {"(*Int32).Swap", Method, 19}, - {"(*Int64).Add", Method, 19}, - {"(*Int64).And", Method, 23}, - {"(*Int64).CompareAndSwap", Method, 19}, - {"(*Int64).Load", Method, 19}, - {"(*Int64).Or", Method, 23}, - {"(*Int64).Store", Method, 19}, - {"(*Int64).Swap", Method, 19}, - {"(*Pointer).CompareAndSwap", Method, 19}, - {"(*Pointer).Load", Method, 19}, - {"(*Pointer).Store", Method, 19}, - {"(*Pointer).Swap", Method, 19}, - {"(*Uint32).Add", Method, 19}, - {"(*Uint32).And", Method, 23}, - {"(*Uint32).CompareAndSwap", Method, 19}, - {"(*Uint32).Load", Method, 19}, - {"(*Uint32).Or", Method, 23}, - {"(*Uint32).Store", Method, 19}, - {"(*Uint32).Swap", Method, 19}, - {"(*Uint64).Add", Method, 19}, - {"(*Uint64).And", Method, 23}, - {"(*Uint64).CompareAndSwap", Method, 19}, - {"(*Uint64).Load", Method, 19}, - {"(*Uint64).Or", Method, 23}, - {"(*Uint64).Store", Method, 19}, - {"(*Uint64).Swap", Method, 19}, - {"(*Uintptr).Add", Method, 19}, - {"(*Uintptr).And", Method, 23}, - {"(*Uintptr).CompareAndSwap", Method, 19}, - {"(*Uintptr).Load", Method, 19}, - {"(*Uintptr).Or", Method, 23}, - {"(*Uintptr).Store", Method, 19}, - {"(*Uintptr).Swap", Method, 19}, - {"(*Value).CompareAndSwap", Method, 17}, - {"(*Value).Load", Method, 4}, - {"(*Value).Store", Method, 4}, - {"(*Value).Swap", Method, 17}, - {"AddInt32", Func, 0}, - {"AddInt64", Func, 0}, - {"AddUint32", Func, 0}, - {"AddUint64", Func, 0}, - {"AddUintptr", Func, 0}, - {"AndInt32", Func, 23}, - {"AndInt64", Func, 23}, - {"AndUint32", Func, 23}, - {"AndUint64", Func, 23}, - {"AndUintptr", Func, 23}, - {"Bool", Type, 19}, - {"CompareAndSwapInt32", Func, 0}, - {"CompareAndSwapInt64", Func, 0}, - {"CompareAndSwapPointer", Func, 0}, - {"CompareAndSwapUint32", Func, 0}, - {"CompareAndSwapUint64", Func, 0}, - {"CompareAndSwapUintptr", Func, 0}, - {"Int32", Type, 19}, - {"Int64", Type, 19}, - {"LoadInt32", Func, 0}, - {"LoadInt64", Func, 0}, - {"LoadPointer", Func, 0}, - {"LoadUint32", Func, 0}, - {"LoadUint64", Func, 0}, - {"LoadUintptr", Func, 0}, - {"OrInt32", Func, 23}, - {"OrInt64", Func, 23}, - {"OrUint32", Func, 23}, - {"OrUint64", Func, 23}, - {"OrUintptr", Func, 23}, - {"Pointer", Type, 19}, - {"StoreInt32", Func, 0}, - {"StoreInt64", Func, 0}, - {"StorePointer", Func, 0}, - {"StoreUint32", Func, 0}, - {"StoreUint64", Func, 0}, - {"StoreUintptr", Func, 0}, - {"SwapInt32", Func, 2}, - {"SwapInt64", Func, 2}, - {"SwapPointer", Func, 2}, - {"SwapUint32", Func, 2}, - {"SwapUint64", Func, 2}, - {"SwapUintptr", Func, 2}, - {"Uint32", Type, 19}, - {"Uint64", Type, 19}, - {"Uintptr", Type, 19}, - {"Value", Type, 4}, + {"(*Bool).CompareAndSwap", Method, 19, ""}, + {"(*Bool).Load", Method, 19, ""}, + {"(*Bool).Store", Method, 19, ""}, + {"(*Bool).Swap", Method, 19, ""}, + {"(*Int32).Add", Method, 19, ""}, + {"(*Int32).And", Method, 23, ""}, + {"(*Int32).CompareAndSwap", Method, 19, ""}, + {"(*Int32).Load", Method, 19, ""}, + {"(*Int32).Or", Method, 23, ""}, + {"(*Int32).Store", Method, 19, ""}, + {"(*Int32).Swap", Method, 19, ""}, + {"(*Int64).Add", Method, 19, ""}, + {"(*Int64).And", Method, 23, ""}, + {"(*Int64).CompareAndSwap", Method, 19, ""}, + {"(*Int64).Load", Method, 19, ""}, + {"(*Int64).Or", Method, 23, ""}, + {"(*Int64).Store", Method, 19, ""}, + {"(*Int64).Swap", Method, 19, ""}, + {"(*Pointer).CompareAndSwap", Method, 19, ""}, + {"(*Pointer).Load", Method, 19, ""}, + {"(*Pointer).Store", Method, 19, ""}, + {"(*Pointer).Swap", Method, 19, ""}, + {"(*Uint32).Add", Method, 19, ""}, + {"(*Uint32).And", Method, 23, ""}, + {"(*Uint32).CompareAndSwap", Method, 19, ""}, + {"(*Uint32).Load", Method, 19, ""}, + {"(*Uint32).Or", Method, 23, ""}, + {"(*Uint32).Store", Method, 19, ""}, + {"(*Uint32).Swap", Method, 19, ""}, + {"(*Uint64).Add", Method, 19, ""}, + {"(*Uint64).And", Method, 23, ""}, + {"(*Uint64).CompareAndSwap", Method, 19, ""}, + {"(*Uint64).Load", Method, 19, ""}, + {"(*Uint64).Or", Method, 23, ""}, + {"(*Uint64).Store", Method, 19, ""}, + {"(*Uint64).Swap", Method, 19, ""}, + {"(*Uintptr).Add", Method, 19, ""}, + {"(*Uintptr).And", Method, 23, ""}, + {"(*Uintptr).CompareAndSwap", Method, 19, ""}, + {"(*Uintptr).Load", Method, 19, ""}, + {"(*Uintptr).Or", Method, 23, ""}, + {"(*Uintptr).Store", Method, 19, ""}, + {"(*Uintptr).Swap", Method, 19, ""}, + {"(*Value).CompareAndSwap", Method, 17, ""}, + {"(*Value).Load", Method, 4, ""}, + {"(*Value).Store", Method, 4, ""}, + {"(*Value).Swap", Method, 17, ""}, + {"AddInt32", Func, 0, "func(addr *int32, delta int32) (new int32)"}, + {"AddInt64", Func, 0, "func(addr *int64, delta int64) (new int64)"}, + {"AddUint32", Func, 0, "func(addr *uint32, delta uint32) (new uint32)"}, + {"AddUint64", Func, 0, "func(addr *uint64, delta uint64) (new uint64)"}, + {"AddUintptr", Func, 0, "func(addr *uintptr, delta uintptr) (new uintptr)"}, + {"AndInt32", Func, 23, "func(addr *int32, mask int32) (old int32)"}, + {"AndInt64", Func, 23, "func(addr *int64, mask int64) (old int64)"}, + {"AndUint32", Func, 23, "func(addr *uint32, mask uint32) (old uint32)"}, + {"AndUint64", Func, 23, "func(addr *uint64, mask uint64) (old uint64)"}, + {"AndUintptr", Func, 23, "func(addr *uintptr, mask uintptr) (old uintptr)"}, + {"Bool", Type, 19, ""}, + {"CompareAndSwapInt32", Func, 0, "func(addr *int32, old int32, new int32) (swapped bool)"}, + {"CompareAndSwapInt64", Func, 0, "func(addr *int64, old int64, new int64) (swapped bool)"}, + {"CompareAndSwapPointer", Func, 0, "func(addr *unsafe.Pointer, old unsafe.Pointer, new unsafe.Pointer) (swapped bool)"}, + {"CompareAndSwapUint32", Func, 0, "func(addr *uint32, old uint32, new uint32) (swapped bool)"}, + {"CompareAndSwapUint64", Func, 0, "func(addr *uint64, old uint64, new uint64) (swapped bool)"}, + {"CompareAndSwapUintptr", Func, 0, "func(addr *uintptr, old uintptr, new uintptr) (swapped bool)"}, + {"Int32", Type, 19, ""}, + {"Int64", Type, 19, ""}, + {"LoadInt32", Func, 0, "func(addr *int32) (val int32)"}, + {"LoadInt64", Func, 0, "func(addr *int64) (val int64)"}, + {"LoadPointer", Func, 0, "func(addr *unsafe.Pointer) (val unsafe.Pointer)"}, + {"LoadUint32", Func, 0, "func(addr *uint32) (val uint32)"}, + {"LoadUint64", Func, 0, "func(addr *uint64) (val uint64)"}, + {"LoadUintptr", Func, 0, "func(addr *uintptr) (val uintptr)"}, + {"OrInt32", Func, 23, "func(addr *int32, mask int32) (old int32)"}, + {"OrInt64", Func, 23, "func(addr *int64, mask int64) (old int64)"}, + {"OrUint32", Func, 23, "func(addr *uint32, mask uint32) (old uint32)"}, + {"OrUint64", Func, 23, "func(addr *uint64, mask uint64) (old uint64)"}, + {"OrUintptr", Func, 23, "func(addr *uintptr, mask uintptr) (old uintptr)"}, + {"Pointer", Type, 19, ""}, + {"StoreInt32", Func, 0, "func(addr *int32, val int32)"}, + {"StoreInt64", Func, 0, "func(addr *int64, val int64)"}, + {"StorePointer", Func, 0, "func(addr *unsafe.Pointer, val unsafe.Pointer)"}, + {"StoreUint32", Func, 0, "func(addr *uint32, val uint32)"}, + {"StoreUint64", Func, 0, "func(addr *uint64, val uint64)"}, + {"StoreUintptr", Func, 0, "func(addr *uintptr, val uintptr)"}, + {"SwapInt32", Func, 2, "func(addr *int32, new int32) (old int32)"}, + {"SwapInt64", Func, 2, "func(addr *int64, new int64) (old int64)"}, + {"SwapPointer", Func, 2, "func(addr *unsafe.Pointer, new unsafe.Pointer) (old unsafe.Pointer)"}, + {"SwapUint32", Func, 2, "func(addr *uint32, new uint32) (old uint32)"}, + {"SwapUint64", Func, 2, "func(addr *uint64, new uint64) (old uint64)"}, + {"SwapUintptr", Func, 2, "func(addr *uintptr, new uintptr) (old uintptr)"}, + {"Uint32", Type, 19, ""}, + {"Uint64", Type, 19, ""}, + {"Uintptr", Type, 19, ""}, + {"Value", Type, 4, ""}, }, "syscall": { - {"(*Cmsghdr).SetLen", Method, 0}, - {"(*DLL).FindProc", Method, 0}, - {"(*DLL).MustFindProc", Method, 0}, - {"(*DLL).Release", Method, 0}, - {"(*DLLError).Error", Method, 0}, - {"(*DLLError).Unwrap", Method, 16}, - {"(*Filetime).Nanoseconds", Method, 0}, - {"(*Iovec).SetLen", Method, 0}, - {"(*LazyDLL).Handle", Method, 0}, - {"(*LazyDLL).Load", Method, 0}, - {"(*LazyDLL).NewProc", Method, 0}, - {"(*LazyProc).Addr", Method, 0}, - {"(*LazyProc).Call", Method, 0}, - {"(*LazyProc).Find", Method, 0}, - {"(*Msghdr).SetControllen", Method, 0}, - {"(*Proc).Addr", Method, 0}, - {"(*Proc).Call", Method, 0}, - {"(*PtraceRegs).PC", Method, 0}, - {"(*PtraceRegs).SetPC", Method, 0}, - {"(*RawSockaddrAny).Sockaddr", Method, 0}, - {"(*SID).Copy", Method, 0}, - {"(*SID).Len", Method, 0}, - {"(*SID).LookupAccount", Method, 0}, - {"(*SID).String", Method, 0}, - {"(*Timespec).Nano", Method, 0}, - {"(*Timespec).Unix", Method, 0}, - {"(*Timeval).Nano", Method, 0}, - {"(*Timeval).Nanoseconds", Method, 0}, - {"(*Timeval).Unix", Method, 0}, - {"(Errno).Error", Method, 0}, - {"(Errno).Is", Method, 13}, - {"(Errno).Temporary", Method, 0}, - {"(Errno).Timeout", Method, 0}, - {"(Signal).Signal", Method, 0}, - {"(Signal).String", Method, 0}, - {"(Token).Close", Method, 0}, - {"(Token).GetTokenPrimaryGroup", Method, 0}, - {"(Token).GetTokenUser", Method, 0}, - {"(Token).GetUserProfileDirectory", Method, 0}, - {"(WaitStatus).Continued", Method, 0}, - {"(WaitStatus).CoreDump", Method, 0}, - {"(WaitStatus).ExitStatus", Method, 0}, - {"(WaitStatus).Exited", Method, 0}, - {"(WaitStatus).Signal", Method, 0}, - {"(WaitStatus).Signaled", Method, 0}, - {"(WaitStatus).StopSignal", Method, 0}, - {"(WaitStatus).Stopped", Method, 0}, - {"(WaitStatus).TrapCause", Method, 0}, - {"AF_ALG", Const, 0}, - {"AF_APPLETALK", Const, 0}, - {"AF_ARP", Const, 0}, - {"AF_ASH", Const, 0}, - {"AF_ATM", Const, 0}, - {"AF_ATMPVC", Const, 0}, - {"AF_ATMSVC", Const, 0}, - {"AF_AX25", Const, 0}, - {"AF_BLUETOOTH", Const, 0}, - {"AF_BRIDGE", Const, 0}, - {"AF_CAIF", Const, 0}, - {"AF_CAN", Const, 0}, - {"AF_CCITT", Const, 0}, - {"AF_CHAOS", Const, 0}, - {"AF_CNT", Const, 0}, - {"AF_COIP", Const, 0}, - {"AF_DATAKIT", Const, 0}, - {"AF_DECnet", Const, 0}, - {"AF_DLI", Const, 0}, - {"AF_E164", Const, 0}, - {"AF_ECMA", Const, 0}, - {"AF_ECONET", Const, 0}, - {"AF_ENCAP", Const, 1}, - {"AF_FILE", Const, 0}, - {"AF_HYLINK", Const, 0}, - {"AF_IEEE80211", Const, 0}, - {"AF_IEEE802154", Const, 0}, - {"AF_IMPLINK", Const, 0}, - {"AF_INET", Const, 0}, - {"AF_INET6", Const, 0}, - {"AF_INET6_SDP", Const, 3}, - {"AF_INET_SDP", Const, 3}, - {"AF_IPX", Const, 0}, - {"AF_IRDA", Const, 0}, - {"AF_ISDN", Const, 0}, - {"AF_ISO", Const, 0}, - {"AF_IUCV", Const, 0}, - {"AF_KEY", Const, 0}, - {"AF_LAT", Const, 0}, - {"AF_LINK", Const, 0}, - {"AF_LLC", Const, 0}, - {"AF_LOCAL", Const, 0}, - {"AF_MAX", Const, 0}, - {"AF_MPLS", Const, 1}, - {"AF_NATM", Const, 0}, - {"AF_NDRV", Const, 0}, - {"AF_NETBEUI", Const, 0}, - {"AF_NETBIOS", Const, 0}, - {"AF_NETGRAPH", Const, 0}, - {"AF_NETLINK", Const, 0}, - {"AF_NETROM", Const, 0}, - {"AF_NS", Const, 0}, - {"AF_OROUTE", Const, 1}, - {"AF_OSI", Const, 0}, - {"AF_PACKET", Const, 0}, - {"AF_PHONET", Const, 0}, - {"AF_PPP", Const, 0}, - {"AF_PPPOX", Const, 0}, - {"AF_PUP", Const, 0}, - {"AF_RDS", Const, 0}, - {"AF_RESERVED_36", Const, 0}, - {"AF_ROSE", Const, 0}, - {"AF_ROUTE", Const, 0}, - {"AF_RXRPC", Const, 0}, - {"AF_SCLUSTER", Const, 0}, - {"AF_SECURITY", Const, 0}, - {"AF_SIP", Const, 0}, - {"AF_SLOW", Const, 0}, - {"AF_SNA", Const, 0}, - {"AF_SYSTEM", Const, 0}, - {"AF_TIPC", Const, 0}, - {"AF_UNIX", Const, 0}, - {"AF_UNSPEC", Const, 0}, - {"AF_UTUN", Const, 16}, - {"AF_VENDOR00", Const, 0}, - {"AF_VENDOR01", Const, 0}, - {"AF_VENDOR02", Const, 0}, - {"AF_VENDOR03", Const, 0}, - {"AF_VENDOR04", Const, 0}, - {"AF_VENDOR05", Const, 0}, - {"AF_VENDOR06", Const, 0}, - {"AF_VENDOR07", Const, 0}, - {"AF_VENDOR08", Const, 0}, - {"AF_VENDOR09", Const, 0}, - {"AF_VENDOR10", Const, 0}, - {"AF_VENDOR11", Const, 0}, - {"AF_VENDOR12", Const, 0}, - {"AF_VENDOR13", Const, 0}, - {"AF_VENDOR14", Const, 0}, - {"AF_VENDOR15", Const, 0}, - {"AF_VENDOR16", Const, 0}, - {"AF_VENDOR17", Const, 0}, - {"AF_VENDOR18", Const, 0}, - {"AF_VENDOR19", Const, 0}, - {"AF_VENDOR20", Const, 0}, - {"AF_VENDOR21", Const, 0}, - {"AF_VENDOR22", Const, 0}, - {"AF_VENDOR23", Const, 0}, - {"AF_VENDOR24", Const, 0}, - {"AF_VENDOR25", Const, 0}, - {"AF_VENDOR26", Const, 0}, - {"AF_VENDOR27", Const, 0}, - {"AF_VENDOR28", Const, 0}, - {"AF_VENDOR29", Const, 0}, - {"AF_VENDOR30", Const, 0}, - {"AF_VENDOR31", Const, 0}, - {"AF_VENDOR32", Const, 0}, - {"AF_VENDOR33", Const, 0}, - {"AF_VENDOR34", Const, 0}, - {"AF_VENDOR35", Const, 0}, - {"AF_VENDOR36", Const, 0}, - {"AF_VENDOR37", Const, 0}, - {"AF_VENDOR38", Const, 0}, - {"AF_VENDOR39", Const, 0}, - {"AF_VENDOR40", Const, 0}, - {"AF_VENDOR41", Const, 0}, - {"AF_VENDOR42", Const, 0}, - {"AF_VENDOR43", Const, 0}, - {"AF_VENDOR44", Const, 0}, - {"AF_VENDOR45", Const, 0}, - {"AF_VENDOR46", Const, 0}, - {"AF_VENDOR47", Const, 0}, - {"AF_WANPIPE", Const, 0}, - {"AF_X25", Const, 0}, - {"AI_CANONNAME", Const, 1}, - {"AI_NUMERICHOST", Const, 1}, - {"AI_PASSIVE", Const, 1}, - {"APPLICATION_ERROR", Const, 0}, - {"ARPHRD_ADAPT", Const, 0}, - {"ARPHRD_APPLETLK", Const, 0}, - {"ARPHRD_ARCNET", Const, 0}, - {"ARPHRD_ASH", Const, 0}, - {"ARPHRD_ATM", Const, 0}, - {"ARPHRD_AX25", Const, 0}, - {"ARPHRD_BIF", Const, 0}, - {"ARPHRD_CHAOS", Const, 0}, - {"ARPHRD_CISCO", Const, 0}, - {"ARPHRD_CSLIP", Const, 0}, - {"ARPHRD_CSLIP6", Const, 0}, - {"ARPHRD_DDCMP", Const, 0}, - {"ARPHRD_DLCI", Const, 0}, - {"ARPHRD_ECONET", Const, 0}, - {"ARPHRD_EETHER", Const, 0}, - {"ARPHRD_ETHER", Const, 0}, - {"ARPHRD_EUI64", Const, 0}, - {"ARPHRD_FCAL", Const, 0}, - {"ARPHRD_FCFABRIC", Const, 0}, - {"ARPHRD_FCPL", Const, 0}, - {"ARPHRD_FCPP", Const, 0}, - {"ARPHRD_FDDI", Const, 0}, - {"ARPHRD_FRAD", Const, 0}, - {"ARPHRD_FRELAY", Const, 1}, - {"ARPHRD_HDLC", Const, 0}, - {"ARPHRD_HIPPI", Const, 0}, - {"ARPHRD_HWX25", Const, 0}, - {"ARPHRD_IEEE1394", Const, 0}, - {"ARPHRD_IEEE802", Const, 0}, - {"ARPHRD_IEEE80211", Const, 0}, - {"ARPHRD_IEEE80211_PRISM", Const, 0}, - {"ARPHRD_IEEE80211_RADIOTAP", Const, 0}, - {"ARPHRD_IEEE802154", Const, 0}, - {"ARPHRD_IEEE802154_PHY", Const, 0}, - {"ARPHRD_IEEE802_TR", Const, 0}, - {"ARPHRD_INFINIBAND", Const, 0}, - {"ARPHRD_IPDDP", Const, 0}, - {"ARPHRD_IPGRE", Const, 0}, - {"ARPHRD_IRDA", Const, 0}, - {"ARPHRD_LAPB", Const, 0}, - {"ARPHRD_LOCALTLK", Const, 0}, - {"ARPHRD_LOOPBACK", Const, 0}, - {"ARPHRD_METRICOM", Const, 0}, - {"ARPHRD_NETROM", Const, 0}, - {"ARPHRD_NONE", Const, 0}, - {"ARPHRD_PIMREG", Const, 0}, - {"ARPHRD_PPP", Const, 0}, - {"ARPHRD_PRONET", Const, 0}, - {"ARPHRD_RAWHDLC", Const, 0}, - {"ARPHRD_ROSE", Const, 0}, - {"ARPHRD_RSRVD", Const, 0}, - {"ARPHRD_SIT", Const, 0}, - {"ARPHRD_SKIP", Const, 0}, - {"ARPHRD_SLIP", Const, 0}, - {"ARPHRD_SLIP6", Const, 0}, - {"ARPHRD_STRIP", Const, 1}, - {"ARPHRD_TUNNEL", Const, 0}, - {"ARPHRD_TUNNEL6", Const, 0}, - {"ARPHRD_VOID", Const, 0}, - {"ARPHRD_X25", Const, 0}, - {"AUTHTYPE_CLIENT", Const, 0}, - {"AUTHTYPE_SERVER", Const, 0}, - {"Accept", Func, 0}, - {"Accept4", Func, 1}, - {"AcceptEx", Func, 0}, - {"Access", Func, 0}, - {"Acct", Func, 0}, - {"AddrinfoW", Type, 1}, - {"AddrinfoW.Addr", Field, 1}, - {"AddrinfoW.Addrlen", Field, 1}, - {"AddrinfoW.Canonname", Field, 1}, - {"AddrinfoW.Family", Field, 1}, - {"AddrinfoW.Flags", Field, 1}, - {"AddrinfoW.Next", Field, 1}, - {"AddrinfoW.Protocol", Field, 1}, - {"AddrinfoW.Socktype", Field, 1}, - {"Adjtime", Func, 0}, - {"Adjtimex", Func, 0}, - {"AllThreadsSyscall", Func, 16}, - {"AllThreadsSyscall6", Func, 16}, - {"AttachLsf", Func, 0}, - {"B0", Const, 0}, - {"B1000000", Const, 0}, - {"B110", Const, 0}, - {"B115200", Const, 0}, - {"B1152000", Const, 0}, - {"B1200", Const, 0}, - {"B134", Const, 0}, - {"B14400", Const, 1}, - {"B150", Const, 0}, - {"B1500000", Const, 0}, - {"B1800", Const, 0}, - {"B19200", Const, 0}, - {"B200", Const, 0}, - {"B2000000", Const, 0}, - {"B230400", Const, 0}, - {"B2400", Const, 0}, - {"B2500000", Const, 0}, - {"B28800", Const, 1}, - {"B300", Const, 0}, - {"B3000000", Const, 0}, - {"B3500000", Const, 0}, - {"B38400", Const, 0}, - {"B4000000", Const, 0}, - {"B460800", Const, 0}, - {"B4800", Const, 0}, - {"B50", Const, 0}, - {"B500000", Const, 0}, - {"B57600", Const, 0}, - {"B576000", Const, 0}, - {"B600", Const, 0}, - {"B7200", Const, 1}, - {"B75", Const, 0}, - {"B76800", Const, 1}, - {"B921600", Const, 0}, - {"B9600", Const, 0}, - {"BASE_PROTOCOL", Const, 2}, - {"BIOCFEEDBACK", Const, 0}, - {"BIOCFLUSH", Const, 0}, - {"BIOCGBLEN", Const, 0}, - {"BIOCGDIRECTION", Const, 0}, - {"BIOCGDIRFILT", Const, 1}, - {"BIOCGDLT", Const, 0}, - {"BIOCGDLTLIST", Const, 0}, - {"BIOCGETBUFMODE", Const, 0}, - {"BIOCGETIF", Const, 0}, - {"BIOCGETZMAX", Const, 0}, - {"BIOCGFEEDBACK", Const, 1}, - {"BIOCGFILDROP", Const, 1}, - {"BIOCGHDRCMPLT", Const, 0}, - {"BIOCGRSIG", Const, 0}, - {"BIOCGRTIMEOUT", Const, 0}, - {"BIOCGSEESENT", Const, 0}, - {"BIOCGSTATS", Const, 0}, - {"BIOCGSTATSOLD", Const, 1}, - {"BIOCGTSTAMP", Const, 1}, - {"BIOCIMMEDIATE", Const, 0}, - {"BIOCLOCK", Const, 0}, - {"BIOCPROMISC", Const, 0}, - {"BIOCROTZBUF", Const, 0}, - {"BIOCSBLEN", Const, 0}, - {"BIOCSDIRECTION", Const, 0}, - {"BIOCSDIRFILT", Const, 1}, - {"BIOCSDLT", Const, 0}, - {"BIOCSETBUFMODE", Const, 0}, - {"BIOCSETF", Const, 0}, - {"BIOCSETFNR", Const, 0}, - {"BIOCSETIF", Const, 0}, - {"BIOCSETWF", Const, 0}, - {"BIOCSETZBUF", Const, 0}, - {"BIOCSFEEDBACK", Const, 1}, - {"BIOCSFILDROP", Const, 1}, - {"BIOCSHDRCMPLT", Const, 0}, - {"BIOCSRSIG", Const, 0}, - {"BIOCSRTIMEOUT", Const, 0}, - {"BIOCSSEESENT", Const, 0}, - {"BIOCSTCPF", Const, 1}, - {"BIOCSTSTAMP", Const, 1}, - {"BIOCSUDPF", Const, 1}, - {"BIOCVERSION", Const, 0}, - {"BPF_A", Const, 0}, - {"BPF_ABS", Const, 0}, - {"BPF_ADD", Const, 0}, - {"BPF_ALIGNMENT", Const, 0}, - {"BPF_ALIGNMENT32", Const, 1}, - {"BPF_ALU", Const, 0}, - {"BPF_AND", Const, 0}, - {"BPF_B", Const, 0}, - {"BPF_BUFMODE_BUFFER", Const, 0}, - {"BPF_BUFMODE_ZBUF", Const, 0}, - {"BPF_DFLTBUFSIZE", Const, 1}, - {"BPF_DIRECTION_IN", Const, 1}, - {"BPF_DIRECTION_OUT", Const, 1}, - {"BPF_DIV", Const, 0}, - {"BPF_H", Const, 0}, - {"BPF_IMM", Const, 0}, - {"BPF_IND", Const, 0}, - {"BPF_JA", Const, 0}, - {"BPF_JEQ", Const, 0}, - {"BPF_JGE", Const, 0}, - {"BPF_JGT", Const, 0}, - {"BPF_JMP", Const, 0}, - {"BPF_JSET", Const, 0}, - {"BPF_K", Const, 0}, - {"BPF_LD", Const, 0}, - {"BPF_LDX", Const, 0}, - {"BPF_LEN", Const, 0}, - {"BPF_LSH", Const, 0}, - {"BPF_MAJOR_VERSION", Const, 0}, - {"BPF_MAXBUFSIZE", Const, 0}, - {"BPF_MAXINSNS", Const, 0}, - {"BPF_MEM", Const, 0}, - {"BPF_MEMWORDS", Const, 0}, - {"BPF_MINBUFSIZE", Const, 0}, - {"BPF_MINOR_VERSION", Const, 0}, - {"BPF_MISC", Const, 0}, - {"BPF_MSH", Const, 0}, - {"BPF_MUL", Const, 0}, - {"BPF_NEG", Const, 0}, - {"BPF_OR", Const, 0}, - {"BPF_RELEASE", Const, 0}, - {"BPF_RET", Const, 0}, - {"BPF_RSH", Const, 0}, - {"BPF_ST", Const, 0}, - {"BPF_STX", Const, 0}, - {"BPF_SUB", Const, 0}, - {"BPF_TAX", Const, 0}, - {"BPF_TXA", Const, 0}, - {"BPF_T_BINTIME", Const, 1}, - {"BPF_T_BINTIME_FAST", Const, 1}, - {"BPF_T_BINTIME_MONOTONIC", Const, 1}, - {"BPF_T_BINTIME_MONOTONIC_FAST", Const, 1}, - {"BPF_T_FAST", Const, 1}, - {"BPF_T_FLAG_MASK", Const, 1}, - {"BPF_T_FORMAT_MASK", Const, 1}, - {"BPF_T_MICROTIME", Const, 1}, - {"BPF_T_MICROTIME_FAST", Const, 1}, - {"BPF_T_MICROTIME_MONOTONIC", Const, 1}, - {"BPF_T_MICROTIME_MONOTONIC_FAST", Const, 1}, - {"BPF_T_MONOTONIC", Const, 1}, - {"BPF_T_MONOTONIC_FAST", Const, 1}, - {"BPF_T_NANOTIME", Const, 1}, - {"BPF_T_NANOTIME_FAST", Const, 1}, - {"BPF_T_NANOTIME_MONOTONIC", Const, 1}, - {"BPF_T_NANOTIME_MONOTONIC_FAST", Const, 1}, - {"BPF_T_NONE", Const, 1}, - {"BPF_T_NORMAL", Const, 1}, - {"BPF_W", Const, 0}, - {"BPF_X", Const, 0}, - {"BRKINT", Const, 0}, - {"Bind", Func, 0}, - {"BindToDevice", Func, 0}, - {"BpfBuflen", Func, 0}, - {"BpfDatalink", Func, 0}, - {"BpfHdr", Type, 0}, - {"BpfHdr.Caplen", Field, 0}, - {"BpfHdr.Datalen", Field, 0}, - {"BpfHdr.Hdrlen", Field, 0}, - {"BpfHdr.Pad_cgo_0", Field, 0}, - {"BpfHdr.Tstamp", Field, 0}, - {"BpfHeadercmpl", Func, 0}, - {"BpfInsn", Type, 0}, - {"BpfInsn.Code", Field, 0}, - {"BpfInsn.Jf", Field, 0}, - {"BpfInsn.Jt", Field, 0}, - {"BpfInsn.K", Field, 0}, - {"BpfInterface", Func, 0}, - {"BpfJump", Func, 0}, - {"BpfProgram", Type, 0}, - {"BpfProgram.Insns", Field, 0}, - {"BpfProgram.Len", Field, 0}, - {"BpfProgram.Pad_cgo_0", Field, 0}, - {"BpfStat", Type, 0}, - {"BpfStat.Capt", Field, 2}, - {"BpfStat.Drop", Field, 0}, - {"BpfStat.Padding", Field, 2}, - {"BpfStat.Recv", Field, 0}, - {"BpfStats", Func, 0}, - {"BpfStmt", Func, 0}, - {"BpfTimeout", Func, 0}, - {"BpfTimeval", Type, 2}, - {"BpfTimeval.Sec", Field, 2}, - {"BpfTimeval.Usec", Field, 2}, - {"BpfVersion", Type, 0}, - {"BpfVersion.Major", Field, 0}, - {"BpfVersion.Minor", Field, 0}, - {"BpfZbuf", Type, 0}, - {"BpfZbuf.Bufa", Field, 0}, - {"BpfZbuf.Bufb", Field, 0}, - {"BpfZbuf.Buflen", Field, 0}, - {"BpfZbufHeader", Type, 0}, - {"BpfZbufHeader.Kernel_gen", Field, 0}, - {"BpfZbufHeader.Kernel_len", Field, 0}, - {"BpfZbufHeader.User_gen", Field, 0}, - {"BpfZbufHeader.X_bzh_pad", Field, 0}, - {"ByHandleFileInformation", Type, 0}, - {"ByHandleFileInformation.CreationTime", Field, 0}, - {"ByHandleFileInformation.FileAttributes", Field, 0}, - {"ByHandleFileInformation.FileIndexHigh", Field, 0}, - {"ByHandleFileInformation.FileIndexLow", Field, 0}, - {"ByHandleFileInformation.FileSizeHigh", Field, 0}, - {"ByHandleFileInformation.FileSizeLow", Field, 0}, - {"ByHandleFileInformation.LastAccessTime", Field, 0}, - {"ByHandleFileInformation.LastWriteTime", Field, 0}, - {"ByHandleFileInformation.NumberOfLinks", Field, 0}, - {"ByHandleFileInformation.VolumeSerialNumber", Field, 0}, - {"BytePtrFromString", Func, 1}, - {"ByteSliceFromString", Func, 1}, - {"CCR0_FLUSH", Const, 1}, - {"CERT_CHAIN_POLICY_AUTHENTICODE", Const, 0}, - {"CERT_CHAIN_POLICY_AUTHENTICODE_TS", Const, 0}, - {"CERT_CHAIN_POLICY_BASE", Const, 0}, - {"CERT_CHAIN_POLICY_BASIC_CONSTRAINTS", Const, 0}, - {"CERT_CHAIN_POLICY_EV", Const, 0}, - {"CERT_CHAIN_POLICY_MICROSOFT_ROOT", Const, 0}, - {"CERT_CHAIN_POLICY_NT_AUTH", Const, 0}, - {"CERT_CHAIN_POLICY_SSL", Const, 0}, - {"CERT_E_CN_NO_MATCH", Const, 0}, - {"CERT_E_EXPIRED", Const, 0}, - {"CERT_E_PURPOSE", Const, 0}, - {"CERT_E_ROLE", Const, 0}, - {"CERT_E_UNTRUSTEDROOT", Const, 0}, - {"CERT_STORE_ADD_ALWAYS", Const, 0}, - {"CERT_STORE_DEFER_CLOSE_UNTIL_LAST_FREE_FLAG", Const, 0}, - {"CERT_STORE_PROV_MEMORY", Const, 0}, - {"CERT_TRUST_HAS_EXCLUDED_NAME_CONSTRAINT", Const, 0}, - {"CERT_TRUST_HAS_NOT_DEFINED_NAME_CONSTRAINT", Const, 0}, - {"CERT_TRUST_HAS_NOT_PERMITTED_NAME_CONSTRAINT", Const, 0}, - {"CERT_TRUST_HAS_NOT_SUPPORTED_CRITICAL_EXT", Const, 0}, - {"CERT_TRUST_HAS_NOT_SUPPORTED_NAME_CONSTRAINT", Const, 0}, - {"CERT_TRUST_INVALID_BASIC_CONSTRAINTS", Const, 0}, - {"CERT_TRUST_INVALID_EXTENSION", Const, 0}, - {"CERT_TRUST_INVALID_NAME_CONSTRAINTS", Const, 0}, - {"CERT_TRUST_INVALID_POLICY_CONSTRAINTS", Const, 0}, - {"CERT_TRUST_IS_CYCLIC", Const, 0}, - {"CERT_TRUST_IS_EXPLICIT_DISTRUST", Const, 0}, - {"CERT_TRUST_IS_NOT_SIGNATURE_VALID", Const, 0}, - {"CERT_TRUST_IS_NOT_TIME_VALID", Const, 0}, - {"CERT_TRUST_IS_NOT_VALID_FOR_USAGE", Const, 0}, - {"CERT_TRUST_IS_OFFLINE_REVOCATION", Const, 0}, - {"CERT_TRUST_IS_REVOKED", Const, 0}, - {"CERT_TRUST_IS_UNTRUSTED_ROOT", Const, 0}, - {"CERT_TRUST_NO_ERROR", Const, 0}, - {"CERT_TRUST_NO_ISSUANCE_CHAIN_POLICY", Const, 0}, - {"CERT_TRUST_REVOCATION_STATUS_UNKNOWN", Const, 0}, - {"CFLUSH", Const, 1}, - {"CLOCAL", Const, 0}, - {"CLONE_CHILD_CLEARTID", Const, 2}, - {"CLONE_CHILD_SETTID", Const, 2}, - {"CLONE_CLEAR_SIGHAND", Const, 20}, - {"CLONE_CSIGNAL", Const, 3}, - {"CLONE_DETACHED", Const, 2}, - {"CLONE_FILES", Const, 2}, - {"CLONE_FS", Const, 2}, - {"CLONE_INTO_CGROUP", Const, 20}, - {"CLONE_IO", Const, 2}, - {"CLONE_NEWCGROUP", Const, 20}, - {"CLONE_NEWIPC", Const, 2}, - {"CLONE_NEWNET", Const, 2}, - {"CLONE_NEWNS", Const, 2}, - {"CLONE_NEWPID", Const, 2}, - {"CLONE_NEWTIME", Const, 20}, - {"CLONE_NEWUSER", Const, 2}, - {"CLONE_NEWUTS", Const, 2}, - {"CLONE_PARENT", Const, 2}, - {"CLONE_PARENT_SETTID", Const, 2}, - {"CLONE_PID", Const, 3}, - {"CLONE_PIDFD", Const, 20}, - {"CLONE_PTRACE", Const, 2}, - {"CLONE_SETTLS", Const, 2}, - {"CLONE_SIGHAND", Const, 2}, - {"CLONE_SYSVSEM", Const, 2}, - {"CLONE_THREAD", Const, 2}, - {"CLONE_UNTRACED", Const, 2}, - {"CLONE_VFORK", Const, 2}, - {"CLONE_VM", Const, 2}, - {"CPUID_CFLUSH", Const, 1}, - {"CREAD", Const, 0}, - {"CREATE_ALWAYS", Const, 0}, - {"CREATE_NEW", Const, 0}, - {"CREATE_NEW_PROCESS_GROUP", Const, 1}, - {"CREATE_UNICODE_ENVIRONMENT", Const, 0}, - {"CRYPT_DEFAULT_CONTAINER_OPTIONAL", Const, 0}, - {"CRYPT_DELETEKEYSET", Const, 0}, - {"CRYPT_MACHINE_KEYSET", Const, 0}, - {"CRYPT_NEWKEYSET", Const, 0}, - {"CRYPT_SILENT", Const, 0}, - {"CRYPT_VERIFYCONTEXT", Const, 0}, - {"CS5", Const, 0}, - {"CS6", Const, 0}, - {"CS7", Const, 0}, - {"CS8", Const, 0}, - {"CSIZE", Const, 0}, - {"CSTART", Const, 1}, - {"CSTATUS", Const, 1}, - {"CSTOP", Const, 1}, - {"CSTOPB", Const, 0}, - {"CSUSP", Const, 1}, - {"CTL_MAXNAME", Const, 0}, - {"CTL_NET", Const, 0}, - {"CTL_QUERY", Const, 1}, - {"CTRL_BREAK_EVENT", Const, 1}, - {"CTRL_CLOSE_EVENT", Const, 14}, - {"CTRL_C_EVENT", Const, 1}, - {"CTRL_LOGOFF_EVENT", Const, 14}, - {"CTRL_SHUTDOWN_EVENT", Const, 14}, - {"CancelIo", Func, 0}, - {"CancelIoEx", Func, 1}, - {"CertAddCertificateContextToStore", Func, 0}, - {"CertChainContext", Type, 0}, - {"CertChainContext.ChainCount", Field, 0}, - {"CertChainContext.Chains", Field, 0}, - {"CertChainContext.HasRevocationFreshnessTime", Field, 0}, - {"CertChainContext.LowerQualityChainCount", Field, 0}, - {"CertChainContext.LowerQualityChains", Field, 0}, - {"CertChainContext.RevocationFreshnessTime", Field, 0}, - {"CertChainContext.Size", Field, 0}, - {"CertChainContext.TrustStatus", Field, 0}, - {"CertChainElement", Type, 0}, - {"CertChainElement.ApplicationUsage", Field, 0}, - {"CertChainElement.CertContext", Field, 0}, - {"CertChainElement.ExtendedErrorInfo", Field, 0}, - {"CertChainElement.IssuanceUsage", Field, 0}, - {"CertChainElement.RevocationInfo", Field, 0}, - {"CertChainElement.Size", Field, 0}, - {"CertChainElement.TrustStatus", Field, 0}, - {"CertChainPara", Type, 0}, - {"CertChainPara.CacheResync", Field, 0}, - {"CertChainPara.CheckRevocationFreshnessTime", Field, 0}, - {"CertChainPara.RequestedUsage", Field, 0}, - {"CertChainPara.RequstedIssuancePolicy", Field, 0}, - {"CertChainPara.RevocationFreshnessTime", Field, 0}, - {"CertChainPara.Size", Field, 0}, - {"CertChainPara.URLRetrievalTimeout", Field, 0}, - {"CertChainPolicyPara", Type, 0}, - {"CertChainPolicyPara.ExtraPolicyPara", Field, 0}, - {"CertChainPolicyPara.Flags", Field, 0}, - {"CertChainPolicyPara.Size", Field, 0}, - {"CertChainPolicyStatus", Type, 0}, - {"CertChainPolicyStatus.ChainIndex", Field, 0}, - {"CertChainPolicyStatus.ElementIndex", Field, 0}, - {"CertChainPolicyStatus.Error", Field, 0}, - {"CertChainPolicyStatus.ExtraPolicyStatus", Field, 0}, - {"CertChainPolicyStatus.Size", Field, 0}, - {"CertCloseStore", Func, 0}, - {"CertContext", Type, 0}, - {"CertContext.CertInfo", Field, 0}, - {"CertContext.EncodedCert", Field, 0}, - {"CertContext.EncodingType", Field, 0}, - {"CertContext.Length", Field, 0}, - {"CertContext.Store", Field, 0}, - {"CertCreateCertificateContext", Func, 0}, - {"CertEnhKeyUsage", Type, 0}, - {"CertEnhKeyUsage.Length", Field, 0}, - {"CertEnhKeyUsage.UsageIdentifiers", Field, 0}, - {"CertEnumCertificatesInStore", Func, 0}, - {"CertFreeCertificateChain", Func, 0}, - {"CertFreeCertificateContext", Func, 0}, - {"CertGetCertificateChain", Func, 0}, - {"CertInfo", Type, 11}, - {"CertOpenStore", Func, 0}, - {"CertOpenSystemStore", Func, 0}, - {"CertRevocationCrlInfo", Type, 11}, - {"CertRevocationInfo", Type, 0}, - {"CertRevocationInfo.CrlInfo", Field, 0}, - {"CertRevocationInfo.FreshnessTime", Field, 0}, - {"CertRevocationInfo.HasFreshnessTime", Field, 0}, - {"CertRevocationInfo.OidSpecificInfo", Field, 0}, - {"CertRevocationInfo.RevocationOid", Field, 0}, - {"CertRevocationInfo.RevocationResult", Field, 0}, - {"CertRevocationInfo.Size", Field, 0}, - {"CertSimpleChain", Type, 0}, - {"CertSimpleChain.Elements", Field, 0}, - {"CertSimpleChain.HasRevocationFreshnessTime", Field, 0}, - {"CertSimpleChain.NumElements", Field, 0}, - {"CertSimpleChain.RevocationFreshnessTime", Field, 0}, - {"CertSimpleChain.Size", Field, 0}, - {"CertSimpleChain.TrustListInfo", Field, 0}, - {"CertSimpleChain.TrustStatus", Field, 0}, - {"CertTrustListInfo", Type, 11}, - {"CertTrustStatus", Type, 0}, - {"CertTrustStatus.ErrorStatus", Field, 0}, - {"CertTrustStatus.InfoStatus", Field, 0}, - {"CertUsageMatch", Type, 0}, - {"CertUsageMatch.Type", Field, 0}, - {"CertUsageMatch.Usage", Field, 0}, - {"CertVerifyCertificateChainPolicy", Func, 0}, - {"Chdir", Func, 0}, - {"CheckBpfVersion", Func, 0}, - {"Chflags", Func, 0}, - {"Chmod", Func, 0}, - {"Chown", Func, 0}, - {"Chroot", Func, 0}, - {"Clearenv", Func, 0}, - {"Close", Func, 0}, - {"CloseHandle", Func, 0}, - {"CloseOnExec", Func, 0}, - {"Closesocket", Func, 0}, - {"CmsgLen", Func, 0}, - {"CmsgSpace", Func, 0}, - {"Cmsghdr", Type, 0}, - {"Cmsghdr.Len", Field, 0}, - {"Cmsghdr.Level", Field, 0}, - {"Cmsghdr.Type", Field, 0}, - {"Cmsghdr.X__cmsg_data", Field, 0}, - {"CommandLineToArgv", Func, 0}, - {"ComputerName", Func, 0}, - {"Conn", Type, 9}, - {"Connect", Func, 0}, - {"ConnectEx", Func, 1}, - {"ConvertSidToStringSid", Func, 0}, - {"ConvertStringSidToSid", Func, 0}, - {"CopySid", Func, 0}, - {"Creat", Func, 0}, - {"CreateDirectory", Func, 0}, - {"CreateFile", Func, 0}, - {"CreateFileMapping", Func, 0}, - {"CreateHardLink", Func, 4}, - {"CreateIoCompletionPort", Func, 0}, - {"CreatePipe", Func, 0}, - {"CreateProcess", Func, 0}, - {"CreateProcessAsUser", Func, 10}, - {"CreateSymbolicLink", Func, 4}, - {"CreateToolhelp32Snapshot", Func, 4}, - {"Credential", Type, 0}, - {"Credential.Gid", Field, 0}, - {"Credential.Groups", Field, 0}, - {"Credential.NoSetGroups", Field, 9}, - {"Credential.Uid", Field, 0}, - {"CryptAcquireContext", Func, 0}, - {"CryptGenRandom", Func, 0}, - {"CryptReleaseContext", Func, 0}, - {"DIOCBSFLUSH", Const, 1}, - {"DIOCOSFPFLUSH", Const, 1}, - {"DLL", Type, 0}, - {"DLL.Handle", Field, 0}, - {"DLL.Name", Field, 0}, - {"DLLError", Type, 0}, - {"DLLError.Err", Field, 0}, - {"DLLError.Msg", Field, 0}, - {"DLLError.ObjName", Field, 0}, - {"DLT_A429", Const, 0}, - {"DLT_A653_ICM", Const, 0}, - {"DLT_AIRONET_HEADER", Const, 0}, - {"DLT_AOS", Const, 1}, - {"DLT_APPLE_IP_OVER_IEEE1394", Const, 0}, - {"DLT_ARCNET", Const, 0}, - {"DLT_ARCNET_LINUX", Const, 0}, - {"DLT_ATM_CLIP", Const, 0}, - {"DLT_ATM_RFC1483", Const, 0}, - {"DLT_AURORA", Const, 0}, - {"DLT_AX25", Const, 0}, - {"DLT_AX25_KISS", Const, 0}, - {"DLT_BACNET_MS_TP", Const, 0}, - {"DLT_BLUETOOTH_HCI_H4", Const, 0}, - {"DLT_BLUETOOTH_HCI_H4_WITH_PHDR", Const, 0}, - {"DLT_CAN20B", Const, 0}, - {"DLT_CAN_SOCKETCAN", Const, 1}, - {"DLT_CHAOS", Const, 0}, - {"DLT_CHDLC", Const, 0}, - {"DLT_CISCO_IOS", Const, 0}, - {"DLT_C_HDLC", Const, 0}, - {"DLT_C_HDLC_WITH_DIR", Const, 0}, - {"DLT_DBUS", Const, 1}, - {"DLT_DECT", Const, 1}, - {"DLT_DOCSIS", Const, 0}, - {"DLT_DVB_CI", Const, 1}, - {"DLT_ECONET", Const, 0}, - {"DLT_EN10MB", Const, 0}, - {"DLT_EN3MB", Const, 0}, - {"DLT_ENC", Const, 0}, - {"DLT_ERF", Const, 0}, - {"DLT_ERF_ETH", Const, 0}, - {"DLT_ERF_POS", Const, 0}, - {"DLT_FC_2", Const, 1}, - {"DLT_FC_2_WITH_FRAME_DELIMS", Const, 1}, - {"DLT_FDDI", Const, 0}, - {"DLT_FLEXRAY", Const, 0}, - {"DLT_FRELAY", Const, 0}, - {"DLT_FRELAY_WITH_DIR", Const, 0}, - {"DLT_GCOM_SERIAL", Const, 0}, - {"DLT_GCOM_T1E1", Const, 0}, - {"DLT_GPF_F", Const, 0}, - {"DLT_GPF_T", Const, 0}, - {"DLT_GPRS_LLC", Const, 0}, - {"DLT_GSMTAP_ABIS", Const, 1}, - {"DLT_GSMTAP_UM", Const, 1}, - {"DLT_HDLC", Const, 1}, - {"DLT_HHDLC", Const, 0}, - {"DLT_HIPPI", Const, 1}, - {"DLT_IBM_SN", Const, 0}, - {"DLT_IBM_SP", Const, 0}, - {"DLT_IEEE802", Const, 0}, - {"DLT_IEEE802_11", Const, 0}, - {"DLT_IEEE802_11_RADIO", Const, 0}, - {"DLT_IEEE802_11_RADIO_AVS", Const, 0}, - {"DLT_IEEE802_15_4", Const, 0}, - {"DLT_IEEE802_15_4_LINUX", Const, 0}, - {"DLT_IEEE802_15_4_NOFCS", Const, 1}, - {"DLT_IEEE802_15_4_NONASK_PHY", Const, 0}, - {"DLT_IEEE802_16_MAC_CPS", Const, 0}, - {"DLT_IEEE802_16_MAC_CPS_RADIO", Const, 0}, - {"DLT_IPFILTER", Const, 0}, - {"DLT_IPMB", Const, 0}, - {"DLT_IPMB_LINUX", Const, 0}, - {"DLT_IPNET", Const, 1}, - {"DLT_IPOIB", Const, 1}, - {"DLT_IPV4", Const, 1}, - {"DLT_IPV6", Const, 1}, - {"DLT_IP_OVER_FC", Const, 0}, - {"DLT_JUNIPER_ATM1", Const, 0}, - {"DLT_JUNIPER_ATM2", Const, 0}, - {"DLT_JUNIPER_ATM_CEMIC", Const, 1}, - {"DLT_JUNIPER_CHDLC", Const, 0}, - {"DLT_JUNIPER_ES", Const, 0}, - {"DLT_JUNIPER_ETHER", Const, 0}, - {"DLT_JUNIPER_FIBRECHANNEL", Const, 1}, - {"DLT_JUNIPER_FRELAY", Const, 0}, - {"DLT_JUNIPER_GGSN", Const, 0}, - {"DLT_JUNIPER_ISM", Const, 0}, - {"DLT_JUNIPER_MFR", Const, 0}, - {"DLT_JUNIPER_MLFR", Const, 0}, - {"DLT_JUNIPER_MLPPP", Const, 0}, - {"DLT_JUNIPER_MONITOR", Const, 0}, - {"DLT_JUNIPER_PIC_PEER", Const, 0}, - {"DLT_JUNIPER_PPP", Const, 0}, - {"DLT_JUNIPER_PPPOE", Const, 0}, - {"DLT_JUNIPER_PPPOE_ATM", Const, 0}, - {"DLT_JUNIPER_SERVICES", Const, 0}, - {"DLT_JUNIPER_SRX_E2E", Const, 1}, - {"DLT_JUNIPER_ST", Const, 0}, - {"DLT_JUNIPER_VP", Const, 0}, - {"DLT_JUNIPER_VS", Const, 1}, - {"DLT_LAPB_WITH_DIR", Const, 0}, - {"DLT_LAPD", Const, 0}, - {"DLT_LIN", Const, 0}, - {"DLT_LINUX_EVDEV", Const, 1}, - {"DLT_LINUX_IRDA", Const, 0}, - {"DLT_LINUX_LAPD", Const, 0}, - {"DLT_LINUX_PPP_WITHDIRECTION", Const, 0}, - {"DLT_LINUX_SLL", Const, 0}, - {"DLT_LOOP", Const, 0}, - {"DLT_LTALK", Const, 0}, - {"DLT_MATCHING_MAX", Const, 1}, - {"DLT_MATCHING_MIN", Const, 1}, - {"DLT_MFR", Const, 0}, - {"DLT_MOST", Const, 0}, - {"DLT_MPEG_2_TS", Const, 1}, - {"DLT_MPLS", Const, 1}, - {"DLT_MTP2", Const, 0}, - {"DLT_MTP2_WITH_PHDR", Const, 0}, - {"DLT_MTP3", Const, 0}, - {"DLT_MUX27010", Const, 1}, - {"DLT_NETANALYZER", Const, 1}, - {"DLT_NETANALYZER_TRANSPARENT", Const, 1}, - {"DLT_NFC_LLCP", Const, 1}, - {"DLT_NFLOG", Const, 1}, - {"DLT_NG40", Const, 1}, - {"DLT_NULL", Const, 0}, - {"DLT_PCI_EXP", Const, 0}, - {"DLT_PFLOG", Const, 0}, - {"DLT_PFSYNC", Const, 0}, - {"DLT_PPI", Const, 0}, - {"DLT_PPP", Const, 0}, - {"DLT_PPP_BSDOS", Const, 0}, - {"DLT_PPP_ETHER", Const, 0}, - {"DLT_PPP_PPPD", Const, 0}, - {"DLT_PPP_SERIAL", Const, 0}, - {"DLT_PPP_WITH_DIR", Const, 0}, - {"DLT_PPP_WITH_DIRECTION", Const, 0}, - {"DLT_PRISM_HEADER", Const, 0}, - {"DLT_PRONET", Const, 0}, - {"DLT_RAIF1", Const, 0}, - {"DLT_RAW", Const, 0}, - {"DLT_RAWAF_MASK", Const, 1}, - {"DLT_RIO", Const, 0}, - {"DLT_SCCP", Const, 0}, - {"DLT_SITA", Const, 0}, - {"DLT_SLIP", Const, 0}, - {"DLT_SLIP_BSDOS", Const, 0}, - {"DLT_STANAG_5066_D_PDU", Const, 1}, - {"DLT_SUNATM", Const, 0}, - {"DLT_SYMANTEC_FIREWALL", Const, 0}, - {"DLT_TZSP", Const, 0}, - {"DLT_USB", Const, 0}, - {"DLT_USB_LINUX", Const, 0}, - {"DLT_USB_LINUX_MMAPPED", Const, 1}, - {"DLT_USER0", Const, 0}, - {"DLT_USER1", Const, 0}, - {"DLT_USER10", Const, 0}, - {"DLT_USER11", Const, 0}, - {"DLT_USER12", Const, 0}, - {"DLT_USER13", Const, 0}, - {"DLT_USER14", Const, 0}, - {"DLT_USER15", Const, 0}, - {"DLT_USER2", Const, 0}, - {"DLT_USER3", Const, 0}, - {"DLT_USER4", Const, 0}, - {"DLT_USER5", Const, 0}, - {"DLT_USER6", Const, 0}, - {"DLT_USER7", Const, 0}, - {"DLT_USER8", Const, 0}, - {"DLT_USER9", Const, 0}, - {"DLT_WIHART", Const, 1}, - {"DLT_X2E_SERIAL", Const, 0}, - {"DLT_X2E_XORAYA", Const, 0}, - {"DNSMXData", Type, 0}, - {"DNSMXData.NameExchange", Field, 0}, - {"DNSMXData.Pad", Field, 0}, - {"DNSMXData.Preference", Field, 0}, - {"DNSPTRData", Type, 0}, - {"DNSPTRData.Host", Field, 0}, - {"DNSRecord", Type, 0}, - {"DNSRecord.Data", Field, 0}, - {"DNSRecord.Dw", Field, 0}, - {"DNSRecord.Length", Field, 0}, - {"DNSRecord.Name", Field, 0}, - {"DNSRecord.Next", Field, 0}, - {"DNSRecord.Reserved", Field, 0}, - {"DNSRecord.Ttl", Field, 0}, - {"DNSRecord.Type", Field, 0}, - {"DNSSRVData", Type, 0}, - {"DNSSRVData.Pad", Field, 0}, - {"DNSSRVData.Port", Field, 0}, - {"DNSSRVData.Priority", Field, 0}, - {"DNSSRVData.Target", Field, 0}, - {"DNSSRVData.Weight", Field, 0}, - {"DNSTXTData", Type, 0}, - {"DNSTXTData.StringArray", Field, 0}, - {"DNSTXTData.StringCount", Field, 0}, - {"DNS_INFO_NO_RECORDS", Const, 4}, - {"DNS_TYPE_A", Const, 0}, - {"DNS_TYPE_A6", Const, 0}, - {"DNS_TYPE_AAAA", Const, 0}, - {"DNS_TYPE_ADDRS", Const, 0}, - {"DNS_TYPE_AFSDB", Const, 0}, - {"DNS_TYPE_ALL", Const, 0}, - {"DNS_TYPE_ANY", Const, 0}, - {"DNS_TYPE_ATMA", Const, 0}, - {"DNS_TYPE_AXFR", Const, 0}, - {"DNS_TYPE_CERT", Const, 0}, - {"DNS_TYPE_CNAME", Const, 0}, - {"DNS_TYPE_DHCID", Const, 0}, - {"DNS_TYPE_DNAME", Const, 0}, - {"DNS_TYPE_DNSKEY", Const, 0}, - {"DNS_TYPE_DS", Const, 0}, - {"DNS_TYPE_EID", Const, 0}, - {"DNS_TYPE_GID", Const, 0}, - {"DNS_TYPE_GPOS", Const, 0}, - {"DNS_TYPE_HINFO", Const, 0}, - {"DNS_TYPE_ISDN", Const, 0}, - {"DNS_TYPE_IXFR", Const, 0}, - {"DNS_TYPE_KEY", Const, 0}, - {"DNS_TYPE_KX", Const, 0}, - {"DNS_TYPE_LOC", Const, 0}, - {"DNS_TYPE_MAILA", Const, 0}, - {"DNS_TYPE_MAILB", Const, 0}, - {"DNS_TYPE_MB", Const, 0}, - {"DNS_TYPE_MD", Const, 0}, - {"DNS_TYPE_MF", Const, 0}, - {"DNS_TYPE_MG", Const, 0}, - {"DNS_TYPE_MINFO", Const, 0}, - {"DNS_TYPE_MR", Const, 0}, - {"DNS_TYPE_MX", Const, 0}, - {"DNS_TYPE_NAPTR", Const, 0}, - {"DNS_TYPE_NBSTAT", Const, 0}, - {"DNS_TYPE_NIMLOC", Const, 0}, - {"DNS_TYPE_NS", Const, 0}, - {"DNS_TYPE_NSAP", Const, 0}, - {"DNS_TYPE_NSAPPTR", Const, 0}, - {"DNS_TYPE_NSEC", Const, 0}, - {"DNS_TYPE_NULL", Const, 0}, - {"DNS_TYPE_NXT", Const, 0}, - {"DNS_TYPE_OPT", Const, 0}, - {"DNS_TYPE_PTR", Const, 0}, - {"DNS_TYPE_PX", Const, 0}, - {"DNS_TYPE_RP", Const, 0}, - {"DNS_TYPE_RRSIG", Const, 0}, - {"DNS_TYPE_RT", Const, 0}, - {"DNS_TYPE_SIG", Const, 0}, - {"DNS_TYPE_SINK", Const, 0}, - {"DNS_TYPE_SOA", Const, 0}, - {"DNS_TYPE_SRV", Const, 0}, - {"DNS_TYPE_TEXT", Const, 0}, - {"DNS_TYPE_TKEY", Const, 0}, - {"DNS_TYPE_TSIG", Const, 0}, - {"DNS_TYPE_UID", Const, 0}, - {"DNS_TYPE_UINFO", Const, 0}, - {"DNS_TYPE_UNSPEC", Const, 0}, - {"DNS_TYPE_WINS", Const, 0}, - {"DNS_TYPE_WINSR", Const, 0}, - {"DNS_TYPE_WKS", Const, 0}, - {"DNS_TYPE_X25", Const, 0}, - {"DT_BLK", Const, 0}, - {"DT_CHR", Const, 0}, - {"DT_DIR", Const, 0}, - {"DT_FIFO", Const, 0}, - {"DT_LNK", Const, 0}, - {"DT_REG", Const, 0}, - {"DT_SOCK", Const, 0}, - {"DT_UNKNOWN", Const, 0}, - {"DT_WHT", Const, 0}, - {"DUPLICATE_CLOSE_SOURCE", Const, 0}, - {"DUPLICATE_SAME_ACCESS", Const, 0}, - {"DeleteFile", Func, 0}, - {"DetachLsf", Func, 0}, - {"DeviceIoControl", Func, 4}, - {"Dirent", Type, 0}, - {"Dirent.Fileno", Field, 0}, - {"Dirent.Ino", Field, 0}, - {"Dirent.Name", Field, 0}, - {"Dirent.Namlen", Field, 0}, - {"Dirent.Off", Field, 0}, - {"Dirent.Pad0", Field, 12}, - {"Dirent.Pad1", Field, 12}, - {"Dirent.Pad_cgo_0", Field, 0}, - {"Dirent.Reclen", Field, 0}, - {"Dirent.Seekoff", Field, 0}, - {"Dirent.Type", Field, 0}, - {"Dirent.X__d_padding", Field, 3}, - {"DnsNameCompare", Func, 4}, - {"DnsQuery", Func, 0}, - {"DnsRecordListFree", Func, 0}, - {"DnsSectionAdditional", Const, 4}, - {"DnsSectionAnswer", Const, 4}, - {"DnsSectionAuthority", Const, 4}, - {"DnsSectionQuestion", Const, 4}, - {"Dup", Func, 0}, - {"Dup2", Func, 0}, - {"Dup3", Func, 2}, - {"DuplicateHandle", Func, 0}, - {"E2BIG", Const, 0}, - {"EACCES", Const, 0}, - {"EADDRINUSE", Const, 0}, - {"EADDRNOTAVAIL", Const, 0}, - {"EADV", Const, 0}, - {"EAFNOSUPPORT", Const, 0}, - {"EAGAIN", Const, 0}, - {"EALREADY", Const, 0}, - {"EAUTH", Const, 0}, - {"EBADARCH", Const, 0}, - {"EBADE", Const, 0}, - {"EBADEXEC", Const, 0}, - {"EBADF", Const, 0}, - {"EBADFD", Const, 0}, - {"EBADMACHO", Const, 0}, - {"EBADMSG", Const, 0}, - {"EBADR", Const, 0}, - {"EBADRPC", Const, 0}, - {"EBADRQC", Const, 0}, - {"EBADSLT", Const, 0}, - {"EBFONT", Const, 0}, - {"EBUSY", Const, 0}, - {"ECANCELED", Const, 0}, - {"ECAPMODE", Const, 1}, - {"ECHILD", Const, 0}, - {"ECHO", Const, 0}, - {"ECHOCTL", Const, 0}, - {"ECHOE", Const, 0}, - {"ECHOK", Const, 0}, - {"ECHOKE", Const, 0}, - {"ECHONL", Const, 0}, - {"ECHOPRT", Const, 0}, - {"ECHRNG", Const, 0}, - {"ECOMM", Const, 0}, - {"ECONNABORTED", Const, 0}, - {"ECONNREFUSED", Const, 0}, - {"ECONNRESET", Const, 0}, - {"EDEADLK", Const, 0}, - {"EDEADLOCK", Const, 0}, - {"EDESTADDRREQ", Const, 0}, - {"EDEVERR", Const, 0}, - {"EDOM", Const, 0}, - {"EDOOFUS", Const, 0}, - {"EDOTDOT", Const, 0}, - {"EDQUOT", Const, 0}, - {"EEXIST", Const, 0}, - {"EFAULT", Const, 0}, - {"EFBIG", Const, 0}, - {"EFER_LMA", Const, 1}, - {"EFER_LME", Const, 1}, - {"EFER_NXE", Const, 1}, - {"EFER_SCE", Const, 1}, - {"EFTYPE", Const, 0}, - {"EHOSTDOWN", Const, 0}, - {"EHOSTUNREACH", Const, 0}, - {"EHWPOISON", Const, 0}, - {"EIDRM", Const, 0}, - {"EILSEQ", Const, 0}, - {"EINPROGRESS", Const, 0}, - {"EINTR", Const, 0}, - {"EINVAL", Const, 0}, - {"EIO", Const, 0}, - {"EIPSEC", Const, 1}, - {"EISCONN", Const, 0}, - {"EISDIR", Const, 0}, - {"EISNAM", Const, 0}, - {"EKEYEXPIRED", Const, 0}, - {"EKEYREJECTED", Const, 0}, - {"EKEYREVOKED", Const, 0}, - {"EL2HLT", Const, 0}, - {"EL2NSYNC", Const, 0}, - {"EL3HLT", Const, 0}, - {"EL3RST", Const, 0}, - {"ELAST", Const, 0}, - {"ELF_NGREG", Const, 0}, - {"ELF_PRARGSZ", Const, 0}, - {"ELIBACC", Const, 0}, - {"ELIBBAD", Const, 0}, - {"ELIBEXEC", Const, 0}, - {"ELIBMAX", Const, 0}, - {"ELIBSCN", Const, 0}, - {"ELNRNG", Const, 0}, - {"ELOOP", Const, 0}, - {"EMEDIUMTYPE", Const, 0}, - {"EMFILE", Const, 0}, - {"EMLINK", Const, 0}, - {"EMSGSIZE", Const, 0}, - {"EMT_TAGOVF", Const, 1}, - {"EMULTIHOP", Const, 0}, - {"EMUL_ENABLED", Const, 1}, - {"EMUL_LINUX", Const, 1}, - {"EMUL_LINUX32", Const, 1}, - {"EMUL_MAXID", Const, 1}, - {"EMUL_NATIVE", Const, 1}, - {"ENAMETOOLONG", Const, 0}, - {"ENAVAIL", Const, 0}, - {"ENDRUNDISC", Const, 1}, - {"ENEEDAUTH", Const, 0}, - {"ENETDOWN", Const, 0}, - {"ENETRESET", Const, 0}, - {"ENETUNREACH", Const, 0}, - {"ENFILE", Const, 0}, - {"ENOANO", Const, 0}, - {"ENOATTR", Const, 0}, - {"ENOBUFS", Const, 0}, - {"ENOCSI", Const, 0}, - {"ENODATA", Const, 0}, - {"ENODEV", Const, 0}, - {"ENOENT", Const, 0}, - {"ENOEXEC", Const, 0}, - {"ENOKEY", Const, 0}, - {"ENOLCK", Const, 0}, - {"ENOLINK", Const, 0}, - {"ENOMEDIUM", Const, 0}, - {"ENOMEM", Const, 0}, - {"ENOMSG", Const, 0}, - {"ENONET", Const, 0}, - {"ENOPKG", Const, 0}, - {"ENOPOLICY", Const, 0}, - {"ENOPROTOOPT", Const, 0}, - {"ENOSPC", Const, 0}, - {"ENOSR", Const, 0}, - {"ENOSTR", Const, 0}, - {"ENOSYS", Const, 0}, - {"ENOTBLK", Const, 0}, - {"ENOTCAPABLE", Const, 0}, - {"ENOTCONN", Const, 0}, - {"ENOTDIR", Const, 0}, - {"ENOTEMPTY", Const, 0}, - {"ENOTNAM", Const, 0}, - {"ENOTRECOVERABLE", Const, 0}, - {"ENOTSOCK", Const, 0}, - {"ENOTSUP", Const, 0}, - {"ENOTTY", Const, 0}, - {"ENOTUNIQ", Const, 0}, - {"ENXIO", Const, 0}, - {"EN_SW_CTL_INF", Const, 1}, - {"EN_SW_CTL_PREC", Const, 1}, - {"EN_SW_CTL_ROUND", Const, 1}, - {"EN_SW_DATACHAIN", Const, 1}, - {"EN_SW_DENORM", Const, 1}, - {"EN_SW_INVOP", Const, 1}, - {"EN_SW_OVERFLOW", Const, 1}, - {"EN_SW_PRECLOSS", Const, 1}, - {"EN_SW_UNDERFLOW", Const, 1}, - {"EN_SW_ZERODIV", Const, 1}, - {"EOPNOTSUPP", Const, 0}, - {"EOVERFLOW", Const, 0}, - {"EOWNERDEAD", Const, 0}, - {"EPERM", Const, 0}, - {"EPFNOSUPPORT", Const, 0}, - {"EPIPE", Const, 0}, - {"EPOLLERR", Const, 0}, - {"EPOLLET", Const, 0}, - {"EPOLLHUP", Const, 0}, - {"EPOLLIN", Const, 0}, - {"EPOLLMSG", Const, 0}, - {"EPOLLONESHOT", Const, 0}, - {"EPOLLOUT", Const, 0}, - {"EPOLLPRI", Const, 0}, - {"EPOLLRDBAND", Const, 0}, - {"EPOLLRDHUP", Const, 0}, - {"EPOLLRDNORM", Const, 0}, - {"EPOLLWRBAND", Const, 0}, - {"EPOLLWRNORM", Const, 0}, - {"EPOLL_CLOEXEC", Const, 0}, - {"EPOLL_CTL_ADD", Const, 0}, - {"EPOLL_CTL_DEL", Const, 0}, - {"EPOLL_CTL_MOD", Const, 0}, - {"EPOLL_NONBLOCK", Const, 0}, - {"EPROCLIM", Const, 0}, - {"EPROCUNAVAIL", Const, 0}, - {"EPROGMISMATCH", Const, 0}, - {"EPROGUNAVAIL", Const, 0}, - {"EPROTO", Const, 0}, - {"EPROTONOSUPPORT", Const, 0}, - {"EPROTOTYPE", Const, 0}, - {"EPWROFF", Const, 0}, - {"EQFULL", Const, 16}, - {"ERANGE", Const, 0}, - {"EREMCHG", Const, 0}, - {"EREMOTE", Const, 0}, - {"EREMOTEIO", Const, 0}, - {"ERESTART", Const, 0}, - {"ERFKILL", Const, 0}, - {"EROFS", Const, 0}, - {"ERPCMISMATCH", Const, 0}, - {"ERROR_ACCESS_DENIED", Const, 0}, - {"ERROR_ALREADY_EXISTS", Const, 0}, - {"ERROR_BROKEN_PIPE", Const, 0}, - {"ERROR_BUFFER_OVERFLOW", Const, 0}, - {"ERROR_DIR_NOT_EMPTY", Const, 8}, - {"ERROR_ENVVAR_NOT_FOUND", Const, 0}, - {"ERROR_FILE_EXISTS", Const, 0}, - {"ERROR_FILE_NOT_FOUND", Const, 0}, - {"ERROR_HANDLE_EOF", Const, 2}, - {"ERROR_INSUFFICIENT_BUFFER", Const, 0}, - {"ERROR_IO_PENDING", Const, 0}, - {"ERROR_MOD_NOT_FOUND", Const, 0}, - {"ERROR_MORE_DATA", Const, 3}, - {"ERROR_NETNAME_DELETED", Const, 3}, - {"ERROR_NOT_FOUND", Const, 1}, - {"ERROR_NO_MORE_FILES", Const, 0}, - {"ERROR_OPERATION_ABORTED", Const, 0}, - {"ERROR_PATH_NOT_FOUND", Const, 0}, - {"ERROR_PRIVILEGE_NOT_HELD", Const, 4}, - {"ERROR_PROC_NOT_FOUND", Const, 0}, - {"ESHLIBVERS", Const, 0}, - {"ESHUTDOWN", Const, 0}, - {"ESOCKTNOSUPPORT", Const, 0}, - {"ESPIPE", Const, 0}, - {"ESRCH", Const, 0}, - {"ESRMNT", Const, 0}, - {"ESTALE", Const, 0}, - {"ESTRPIPE", Const, 0}, - {"ETHERCAP_JUMBO_MTU", Const, 1}, - {"ETHERCAP_VLAN_HWTAGGING", Const, 1}, - {"ETHERCAP_VLAN_MTU", Const, 1}, - {"ETHERMIN", Const, 1}, - {"ETHERMTU", Const, 1}, - {"ETHERMTU_JUMBO", Const, 1}, - {"ETHERTYPE_8023", Const, 1}, - {"ETHERTYPE_AARP", Const, 1}, - {"ETHERTYPE_ACCTON", Const, 1}, - {"ETHERTYPE_AEONIC", Const, 1}, - {"ETHERTYPE_ALPHA", Const, 1}, - {"ETHERTYPE_AMBER", Const, 1}, - {"ETHERTYPE_AMOEBA", Const, 1}, - {"ETHERTYPE_AOE", Const, 1}, - {"ETHERTYPE_APOLLO", Const, 1}, - {"ETHERTYPE_APOLLODOMAIN", Const, 1}, - {"ETHERTYPE_APPLETALK", Const, 1}, - {"ETHERTYPE_APPLITEK", Const, 1}, - {"ETHERTYPE_ARGONAUT", Const, 1}, - {"ETHERTYPE_ARP", Const, 1}, - {"ETHERTYPE_AT", Const, 1}, - {"ETHERTYPE_ATALK", Const, 1}, - {"ETHERTYPE_ATOMIC", Const, 1}, - {"ETHERTYPE_ATT", Const, 1}, - {"ETHERTYPE_ATTSTANFORD", Const, 1}, - {"ETHERTYPE_AUTOPHON", Const, 1}, - {"ETHERTYPE_AXIS", Const, 1}, - {"ETHERTYPE_BCLOOP", Const, 1}, - {"ETHERTYPE_BOFL", Const, 1}, - {"ETHERTYPE_CABLETRON", Const, 1}, - {"ETHERTYPE_CHAOS", Const, 1}, - {"ETHERTYPE_COMDESIGN", Const, 1}, - {"ETHERTYPE_COMPUGRAPHIC", Const, 1}, - {"ETHERTYPE_COUNTERPOINT", Const, 1}, - {"ETHERTYPE_CRONUS", Const, 1}, - {"ETHERTYPE_CRONUSVLN", Const, 1}, - {"ETHERTYPE_DCA", Const, 1}, - {"ETHERTYPE_DDE", Const, 1}, - {"ETHERTYPE_DEBNI", Const, 1}, - {"ETHERTYPE_DECAM", Const, 1}, - {"ETHERTYPE_DECCUST", Const, 1}, - {"ETHERTYPE_DECDIAG", Const, 1}, - {"ETHERTYPE_DECDNS", Const, 1}, - {"ETHERTYPE_DECDTS", Const, 1}, - {"ETHERTYPE_DECEXPER", Const, 1}, - {"ETHERTYPE_DECLAST", Const, 1}, - {"ETHERTYPE_DECLTM", Const, 1}, - {"ETHERTYPE_DECMUMPS", Const, 1}, - {"ETHERTYPE_DECNETBIOS", Const, 1}, - {"ETHERTYPE_DELTACON", Const, 1}, - {"ETHERTYPE_DIDDLE", Const, 1}, - {"ETHERTYPE_DLOG1", Const, 1}, - {"ETHERTYPE_DLOG2", Const, 1}, - {"ETHERTYPE_DN", Const, 1}, - {"ETHERTYPE_DOGFIGHT", Const, 1}, - {"ETHERTYPE_DSMD", Const, 1}, - {"ETHERTYPE_ECMA", Const, 1}, - {"ETHERTYPE_ENCRYPT", Const, 1}, - {"ETHERTYPE_ES", Const, 1}, - {"ETHERTYPE_EXCELAN", Const, 1}, - {"ETHERTYPE_EXPERDATA", Const, 1}, - {"ETHERTYPE_FLIP", Const, 1}, - {"ETHERTYPE_FLOWCONTROL", Const, 1}, - {"ETHERTYPE_FRARP", Const, 1}, - {"ETHERTYPE_GENDYN", Const, 1}, - {"ETHERTYPE_HAYES", Const, 1}, - {"ETHERTYPE_HIPPI_FP", Const, 1}, - {"ETHERTYPE_HITACHI", Const, 1}, - {"ETHERTYPE_HP", Const, 1}, - {"ETHERTYPE_IEEEPUP", Const, 1}, - {"ETHERTYPE_IEEEPUPAT", Const, 1}, - {"ETHERTYPE_IMLBL", Const, 1}, - {"ETHERTYPE_IMLBLDIAG", Const, 1}, - {"ETHERTYPE_IP", Const, 1}, - {"ETHERTYPE_IPAS", Const, 1}, - {"ETHERTYPE_IPV6", Const, 1}, - {"ETHERTYPE_IPX", Const, 1}, - {"ETHERTYPE_IPXNEW", Const, 1}, - {"ETHERTYPE_KALPANA", Const, 1}, - {"ETHERTYPE_LANBRIDGE", Const, 1}, - {"ETHERTYPE_LANPROBE", Const, 1}, - {"ETHERTYPE_LAT", Const, 1}, - {"ETHERTYPE_LBACK", Const, 1}, - {"ETHERTYPE_LITTLE", Const, 1}, - {"ETHERTYPE_LLDP", Const, 1}, - {"ETHERTYPE_LOGICRAFT", Const, 1}, - {"ETHERTYPE_LOOPBACK", Const, 1}, - {"ETHERTYPE_MATRA", Const, 1}, - {"ETHERTYPE_MAX", Const, 1}, - {"ETHERTYPE_MERIT", Const, 1}, - {"ETHERTYPE_MICP", Const, 1}, - {"ETHERTYPE_MOPDL", Const, 1}, - {"ETHERTYPE_MOPRC", Const, 1}, - {"ETHERTYPE_MOTOROLA", Const, 1}, - {"ETHERTYPE_MPLS", Const, 1}, - {"ETHERTYPE_MPLS_MCAST", Const, 1}, - {"ETHERTYPE_MUMPS", Const, 1}, - {"ETHERTYPE_NBPCC", Const, 1}, - {"ETHERTYPE_NBPCLAIM", Const, 1}, - {"ETHERTYPE_NBPCLREQ", Const, 1}, - {"ETHERTYPE_NBPCLRSP", Const, 1}, - {"ETHERTYPE_NBPCREQ", Const, 1}, - {"ETHERTYPE_NBPCRSP", Const, 1}, - {"ETHERTYPE_NBPDG", Const, 1}, - {"ETHERTYPE_NBPDGB", Const, 1}, - {"ETHERTYPE_NBPDLTE", Const, 1}, - {"ETHERTYPE_NBPRAR", Const, 1}, - {"ETHERTYPE_NBPRAS", Const, 1}, - {"ETHERTYPE_NBPRST", Const, 1}, - {"ETHERTYPE_NBPSCD", Const, 1}, - {"ETHERTYPE_NBPVCD", Const, 1}, - {"ETHERTYPE_NBS", Const, 1}, - {"ETHERTYPE_NCD", Const, 1}, - {"ETHERTYPE_NESTAR", Const, 1}, - {"ETHERTYPE_NETBEUI", Const, 1}, - {"ETHERTYPE_NOVELL", Const, 1}, - {"ETHERTYPE_NS", Const, 1}, - {"ETHERTYPE_NSAT", Const, 1}, - {"ETHERTYPE_NSCOMPAT", Const, 1}, - {"ETHERTYPE_NTRAILER", Const, 1}, - {"ETHERTYPE_OS9", Const, 1}, - {"ETHERTYPE_OS9NET", Const, 1}, - {"ETHERTYPE_PACER", Const, 1}, - {"ETHERTYPE_PAE", Const, 1}, - {"ETHERTYPE_PCS", Const, 1}, - {"ETHERTYPE_PLANNING", Const, 1}, - {"ETHERTYPE_PPP", Const, 1}, - {"ETHERTYPE_PPPOE", Const, 1}, - {"ETHERTYPE_PPPOEDISC", Const, 1}, - {"ETHERTYPE_PRIMENTS", Const, 1}, - {"ETHERTYPE_PUP", Const, 1}, - {"ETHERTYPE_PUPAT", Const, 1}, - {"ETHERTYPE_QINQ", Const, 1}, - {"ETHERTYPE_RACAL", Const, 1}, - {"ETHERTYPE_RATIONAL", Const, 1}, - {"ETHERTYPE_RAWFR", Const, 1}, - {"ETHERTYPE_RCL", Const, 1}, - {"ETHERTYPE_RDP", Const, 1}, - {"ETHERTYPE_RETIX", Const, 1}, - {"ETHERTYPE_REVARP", Const, 1}, - {"ETHERTYPE_SCA", Const, 1}, - {"ETHERTYPE_SECTRA", Const, 1}, - {"ETHERTYPE_SECUREDATA", Const, 1}, - {"ETHERTYPE_SGITW", Const, 1}, - {"ETHERTYPE_SG_BOUNCE", Const, 1}, - {"ETHERTYPE_SG_DIAG", Const, 1}, - {"ETHERTYPE_SG_NETGAMES", Const, 1}, - {"ETHERTYPE_SG_RESV", Const, 1}, - {"ETHERTYPE_SIMNET", Const, 1}, - {"ETHERTYPE_SLOW", Const, 1}, - {"ETHERTYPE_SLOWPROTOCOLS", Const, 1}, - {"ETHERTYPE_SNA", Const, 1}, - {"ETHERTYPE_SNMP", Const, 1}, - {"ETHERTYPE_SONIX", Const, 1}, - {"ETHERTYPE_SPIDER", Const, 1}, - {"ETHERTYPE_SPRITE", Const, 1}, - {"ETHERTYPE_STP", Const, 1}, - {"ETHERTYPE_TALARIS", Const, 1}, - {"ETHERTYPE_TALARISMC", Const, 1}, - {"ETHERTYPE_TCPCOMP", Const, 1}, - {"ETHERTYPE_TCPSM", Const, 1}, - {"ETHERTYPE_TEC", Const, 1}, - {"ETHERTYPE_TIGAN", Const, 1}, - {"ETHERTYPE_TRAIL", Const, 1}, - {"ETHERTYPE_TRANSETHER", Const, 1}, - {"ETHERTYPE_TYMSHARE", Const, 1}, - {"ETHERTYPE_UBBST", Const, 1}, - {"ETHERTYPE_UBDEBUG", Const, 1}, - {"ETHERTYPE_UBDIAGLOOP", Const, 1}, - {"ETHERTYPE_UBDL", Const, 1}, - {"ETHERTYPE_UBNIU", Const, 1}, - {"ETHERTYPE_UBNMC", Const, 1}, - {"ETHERTYPE_VALID", Const, 1}, - {"ETHERTYPE_VARIAN", Const, 1}, - {"ETHERTYPE_VAXELN", Const, 1}, - {"ETHERTYPE_VEECO", Const, 1}, - {"ETHERTYPE_VEXP", Const, 1}, - {"ETHERTYPE_VGLAB", Const, 1}, - {"ETHERTYPE_VINES", Const, 1}, - {"ETHERTYPE_VINESECHO", Const, 1}, - {"ETHERTYPE_VINESLOOP", Const, 1}, - {"ETHERTYPE_VITAL", Const, 1}, - {"ETHERTYPE_VLAN", Const, 1}, - {"ETHERTYPE_VLTLMAN", Const, 1}, - {"ETHERTYPE_VPROD", Const, 1}, - {"ETHERTYPE_VURESERVED", Const, 1}, - {"ETHERTYPE_WATERLOO", Const, 1}, - {"ETHERTYPE_WELLFLEET", Const, 1}, - {"ETHERTYPE_X25", Const, 1}, - {"ETHERTYPE_X75", Const, 1}, - {"ETHERTYPE_XNSSM", Const, 1}, - {"ETHERTYPE_XTP", Const, 1}, - {"ETHER_ADDR_LEN", Const, 1}, - {"ETHER_ALIGN", Const, 1}, - {"ETHER_CRC_LEN", Const, 1}, - {"ETHER_CRC_POLY_BE", Const, 1}, - {"ETHER_CRC_POLY_LE", Const, 1}, - {"ETHER_HDR_LEN", Const, 1}, - {"ETHER_MAX_DIX_LEN", Const, 1}, - {"ETHER_MAX_LEN", Const, 1}, - {"ETHER_MAX_LEN_JUMBO", Const, 1}, - {"ETHER_MIN_LEN", Const, 1}, - {"ETHER_PPPOE_ENCAP_LEN", Const, 1}, - {"ETHER_TYPE_LEN", Const, 1}, - {"ETHER_VLAN_ENCAP_LEN", Const, 1}, - {"ETH_P_1588", Const, 0}, - {"ETH_P_8021Q", Const, 0}, - {"ETH_P_802_2", Const, 0}, - {"ETH_P_802_3", Const, 0}, - {"ETH_P_AARP", Const, 0}, - {"ETH_P_ALL", Const, 0}, - {"ETH_P_AOE", Const, 0}, - {"ETH_P_ARCNET", Const, 0}, - {"ETH_P_ARP", Const, 0}, - {"ETH_P_ATALK", Const, 0}, - {"ETH_P_ATMFATE", Const, 0}, - {"ETH_P_ATMMPOA", Const, 0}, - {"ETH_P_AX25", Const, 0}, - {"ETH_P_BPQ", Const, 0}, - {"ETH_P_CAIF", Const, 0}, - {"ETH_P_CAN", Const, 0}, - {"ETH_P_CONTROL", Const, 0}, - {"ETH_P_CUST", Const, 0}, - {"ETH_P_DDCMP", Const, 0}, - {"ETH_P_DEC", Const, 0}, - {"ETH_P_DIAG", Const, 0}, - {"ETH_P_DNA_DL", Const, 0}, - {"ETH_P_DNA_RC", Const, 0}, - {"ETH_P_DNA_RT", Const, 0}, - {"ETH_P_DSA", Const, 0}, - {"ETH_P_ECONET", Const, 0}, - {"ETH_P_EDSA", Const, 0}, - {"ETH_P_FCOE", Const, 0}, - {"ETH_P_FIP", Const, 0}, - {"ETH_P_HDLC", Const, 0}, - {"ETH_P_IEEE802154", Const, 0}, - {"ETH_P_IEEEPUP", Const, 0}, - {"ETH_P_IEEEPUPAT", Const, 0}, - {"ETH_P_IP", Const, 0}, - {"ETH_P_IPV6", Const, 0}, - {"ETH_P_IPX", Const, 0}, - {"ETH_P_IRDA", Const, 0}, - {"ETH_P_LAT", Const, 0}, - {"ETH_P_LINK_CTL", Const, 0}, - {"ETH_P_LOCALTALK", Const, 0}, - {"ETH_P_LOOP", Const, 0}, - {"ETH_P_MOBITEX", Const, 0}, - {"ETH_P_MPLS_MC", Const, 0}, - {"ETH_P_MPLS_UC", Const, 0}, - {"ETH_P_PAE", Const, 0}, - {"ETH_P_PAUSE", Const, 0}, - {"ETH_P_PHONET", Const, 0}, - {"ETH_P_PPPTALK", Const, 0}, - {"ETH_P_PPP_DISC", Const, 0}, - {"ETH_P_PPP_MP", Const, 0}, - {"ETH_P_PPP_SES", Const, 0}, - {"ETH_P_PUP", Const, 0}, - {"ETH_P_PUPAT", Const, 0}, - {"ETH_P_RARP", Const, 0}, - {"ETH_P_SCA", Const, 0}, - {"ETH_P_SLOW", Const, 0}, - {"ETH_P_SNAP", Const, 0}, - {"ETH_P_TEB", Const, 0}, - {"ETH_P_TIPC", Const, 0}, - {"ETH_P_TRAILER", Const, 0}, - {"ETH_P_TR_802_2", Const, 0}, - {"ETH_P_WAN_PPP", Const, 0}, - {"ETH_P_WCCP", Const, 0}, - {"ETH_P_X25", Const, 0}, - {"ETIME", Const, 0}, - {"ETIMEDOUT", Const, 0}, - {"ETOOMANYREFS", Const, 0}, - {"ETXTBSY", Const, 0}, - {"EUCLEAN", Const, 0}, - {"EUNATCH", Const, 0}, - {"EUSERS", Const, 0}, - {"EVFILT_AIO", Const, 0}, - {"EVFILT_FS", Const, 0}, - {"EVFILT_LIO", Const, 0}, - {"EVFILT_MACHPORT", Const, 0}, - {"EVFILT_PROC", Const, 0}, - {"EVFILT_READ", Const, 0}, - {"EVFILT_SIGNAL", Const, 0}, - {"EVFILT_SYSCOUNT", Const, 0}, - {"EVFILT_THREADMARKER", Const, 0}, - {"EVFILT_TIMER", Const, 0}, - {"EVFILT_USER", Const, 0}, - {"EVFILT_VM", Const, 0}, - {"EVFILT_VNODE", Const, 0}, - {"EVFILT_WRITE", Const, 0}, - {"EV_ADD", Const, 0}, - {"EV_CLEAR", Const, 0}, - {"EV_DELETE", Const, 0}, - {"EV_DISABLE", Const, 0}, - {"EV_DISPATCH", Const, 0}, - {"EV_DROP", Const, 3}, - {"EV_ENABLE", Const, 0}, - {"EV_EOF", Const, 0}, - {"EV_ERROR", Const, 0}, - {"EV_FLAG0", Const, 0}, - {"EV_FLAG1", Const, 0}, - {"EV_ONESHOT", Const, 0}, - {"EV_OOBAND", Const, 0}, - {"EV_POLL", Const, 0}, - {"EV_RECEIPT", Const, 0}, - {"EV_SYSFLAGS", Const, 0}, - {"EWINDOWS", Const, 0}, - {"EWOULDBLOCK", Const, 0}, - {"EXDEV", Const, 0}, - {"EXFULL", Const, 0}, - {"EXTA", Const, 0}, - {"EXTB", Const, 0}, - {"EXTPROC", Const, 0}, - {"Environ", Func, 0}, - {"EpollCreate", Func, 0}, - {"EpollCreate1", Func, 0}, - {"EpollCtl", Func, 0}, - {"EpollEvent", Type, 0}, - {"EpollEvent.Events", Field, 0}, - {"EpollEvent.Fd", Field, 0}, - {"EpollEvent.Pad", Field, 0}, - {"EpollEvent.PadFd", Field, 0}, - {"EpollWait", Func, 0}, - {"Errno", Type, 0}, - {"EscapeArg", Func, 0}, - {"Exchangedata", Func, 0}, - {"Exec", Func, 0}, - {"Exit", Func, 0}, - {"ExitProcess", Func, 0}, - {"FD_CLOEXEC", Const, 0}, - {"FD_SETSIZE", Const, 0}, - {"FILE_ACTION_ADDED", Const, 0}, - {"FILE_ACTION_MODIFIED", Const, 0}, - {"FILE_ACTION_REMOVED", Const, 0}, - {"FILE_ACTION_RENAMED_NEW_NAME", Const, 0}, - {"FILE_ACTION_RENAMED_OLD_NAME", Const, 0}, - {"FILE_APPEND_DATA", Const, 0}, - {"FILE_ATTRIBUTE_ARCHIVE", Const, 0}, - {"FILE_ATTRIBUTE_DIRECTORY", Const, 0}, - {"FILE_ATTRIBUTE_HIDDEN", Const, 0}, - {"FILE_ATTRIBUTE_NORMAL", Const, 0}, - {"FILE_ATTRIBUTE_READONLY", Const, 0}, - {"FILE_ATTRIBUTE_REPARSE_POINT", Const, 4}, - {"FILE_ATTRIBUTE_SYSTEM", Const, 0}, - {"FILE_BEGIN", Const, 0}, - {"FILE_CURRENT", Const, 0}, - {"FILE_END", Const, 0}, - {"FILE_FLAG_BACKUP_SEMANTICS", Const, 0}, - {"FILE_FLAG_OPEN_REPARSE_POINT", Const, 4}, - {"FILE_FLAG_OVERLAPPED", Const, 0}, - {"FILE_LIST_DIRECTORY", Const, 0}, - {"FILE_MAP_COPY", Const, 0}, - {"FILE_MAP_EXECUTE", Const, 0}, - {"FILE_MAP_READ", Const, 0}, - {"FILE_MAP_WRITE", Const, 0}, - {"FILE_NOTIFY_CHANGE_ATTRIBUTES", Const, 0}, - {"FILE_NOTIFY_CHANGE_CREATION", Const, 0}, - {"FILE_NOTIFY_CHANGE_DIR_NAME", Const, 0}, - {"FILE_NOTIFY_CHANGE_FILE_NAME", Const, 0}, - {"FILE_NOTIFY_CHANGE_LAST_ACCESS", Const, 0}, - {"FILE_NOTIFY_CHANGE_LAST_WRITE", Const, 0}, - {"FILE_NOTIFY_CHANGE_SIZE", Const, 0}, - {"FILE_SHARE_DELETE", Const, 0}, - {"FILE_SHARE_READ", Const, 0}, - {"FILE_SHARE_WRITE", Const, 0}, - {"FILE_SKIP_COMPLETION_PORT_ON_SUCCESS", Const, 2}, - {"FILE_SKIP_SET_EVENT_ON_HANDLE", Const, 2}, - {"FILE_TYPE_CHAR", Const, 0}, - {"FILE_TYPE_DISK", Const, 0}, - {"FILE_TYPE_PIPE", Const, 0}, - {"FILE_TYPE_REMOTE", Const, 0}, - {"FILE_TYPE_UNKNOWN", Const, 0}, - {"FILE_WRITE_ATTRIBUTES", Const, 0}, - {"FLUSHO", Const, 0}, - {"FORMAT_MESSAGE_ALLOCATE_BUFFER", Const, 0}, - {"FORMAT_MESSAGE_ARGUMENT_ARRAY", Const, 0}, - {"FORMAT_MESSAGE_FROM_HMODULE", Const, 0}, - {"FORMAT_MESSAGE_FROM_STRING", Const, 0}, - {"FORMAT_MESSAGE_FROM_SYSTEM", Const, 0}, - {"FORMAT_MESSAGE_IGNORE_INSERTS", Const, 0}, - {"FORMAT_MESSAGE_MAX_WIDTH_MASK", Const, 0}, - {"FSCTL_GET_REPARSE_POINT", Const, 4}, - {"F_ADDFILESIGS", Const, 0}, - {"F_ADDSIGS", Const, 0}, - {"F_ALLOCATEALL", Const, 0}, - {"F_ALLOCATECONTIG", Const, 0}, - {"F_CANCEL", Const, 0}, - {"F_CHKCLEAN", Const, 0}, - {"F_CLOSEM", Const, 1}, - {"F_DUP2FD", Const, 0}, - {"F_DUP2FD_CLOEXEC", Const, 1}, - {"F_DUPFD", Const, 0}, - {"F_DUPFD_CLOEXEC", Const, 0}, - {"F_EXLCK", Const, 0}, - {"F_FINDSIGS", Const, 16}, - {"F_FLUSH_DATA", Const, 0}, - {"F_FREEZE_FS", Const, 0}, - {"F_FSCTL", Const, 1}, - {"F_FSDIRMASK", Const, 1}, - {"F_FSIN", Const, 1}, - {"F_FSINOUT", Const, 1}, - {"F_FSOUT", Const, 1}, - {"F_FSPRIV", Const, 1}, - {"F_FSVOID", Const, 1}, - {"F_FULLFSYNC", Const, 0}, - {"F_GETCODEDIR", Const, 16}, - {"F_GETFD", Const, 0}, - {"F_GETFL", Const, 0}, - {"F_GETLEASE", Const, 0}, - {"F_GETLK", Const, 0}, - {"F_GETLK64", Const, 0}, - {"F_GETLKPID", Const, 0}, - {"F_GETNOSIGPIPE", Const, 0}, - {"F_GETOWN", Const, 0}, - {"F_GETOWN_EX", Const, 0}, - {"F_GETPATH", Const, 0}, - {"F_GETPATH_MTMINFO", Const, 0}, - {"F_GETPIPE_SZ", Const, 0}, - {"F_GETPROTECTIONCLASS", Const, 0}, - {"F_GETPROTECTIONLEVEL", Const, 16}, - {"F_GETSIG", Const, 0}, - {"F_GLOBAL_NOCACHE", Const, 0}, - {"F_LOCK", Const, 0}, - {"F_LOG2PHYS", Const, 0}, - {"F_LOG2PHYS_EXT", Const, 0}, - {"F_MARKDEPENDENCY", Const, 0}, - {"F_MAXFD", Const, 1}, - {"F_NOCACHE", Const, 0}, - {"F_NODIRECT", Const, 0}, - {"F_NOTIFY", Const, 0}, - {"F_OGETLK", Const, 0}, - {"F_OK", Const, 0}, - {"F_OSETLK", Const, 0}, - {"F_OSETLKW", Const, 0}, - {"F_PARAM_MASK", Const, 1}, - {"F_PARAM_MAX", Const, 1}, - {"F_PATHPKG_CHECK", Const, 0}, - {"F_PEOFPOSMODE", Const, 0}, - {"F_PREALLOCATE", Const, 0}, - {"F_RDADVISE", Const, 0}, - {"F_RDAHEAD", Const, 0}, - {"F_RDLCK", Const, 0}, - {"F_READAHEAD", Const, 0}, - {"F_READBOOTSTRAP", Const, 0}, - {"F_SETBACKINGSTORE", Const, 0}, - {"F_SETFD", Const, 0}, - {"F_SETFL", Const, 0}, - {"F_SETLEASE", Const, 0}, - {"F_SETLK", Const, 0}, - {"F_SETLK64", Const, 0}, - {"F_SETLKW", Const, 0}, - {"F_SETLKW64", Const, 0}, - {"F_SETLKWTIMEOUT", Const, 16}, - {"F_SETLK_REMOTE", Const, 0}, - {"F_SETNOSIGPIPE", Const, 0}, - {"F_SETOWN", Const, 0}, - {"F_SETOWN_EX", Const, 0}, - {"F_SETPIPE_SZ", Const, 0}, - {"F_SETPROTECTIONCLASS", Const, 0}, - {"F_SETSIG", Const, 0}, - {"F_SETSIZE", Const, 0}, - {"F_SHLCK", Const, 0}, - {"F_SINGLE_WRITER", Const, 16}, - {"F_TEST", Const, 0}, - {"F_THAW_FS", Const, 0}, - {"F_TLOCK", Const, 0}, - {"F_TRANSCODEKEY", Const, 16}, - {"F_ULOCK", Const, 0}, - {"F_UNLCK", Const, 0}, - {"F_UNLCKSYS", Const, 0}, - {"F_VOLPOSMODE", Const, 0}, - {"F_WRITEBOOTSTRAP", Const, 0}, - {"F_WRLCK", Const, 0}, - {"Faccessat", Func, 0}, - {"Fallocate", Func, 0}, - {"Fbootstraptransfer_t", Type, 0}, - {"Fbootstraptransfer_t.Buffer", Field, 0}, - {"Fbootstraptransfer_t.Length", Field, 0}, - {"Fbootstraptransfer_t.Offset", Field, 0}, - {"Fchdir", Func, 0}, - {"Fchflags", Func, 0}, - {"Fchmod", Func, 0}, - {"Fchmodat", Func, 0}, - {"Fchown", Func, 0}, - {"Fchownat", Func, 0}, - {"FcntlFlock", Func, 3}, - {"FdSet", Type, 0}, - {"FdSet.Bits", Field, 0}, - {"FdSet.X__fds_bits", Field, 0}, - {"Fdatasync", Func, 0}, - {"FileNotifyInformation", Type, 0}, - {"FileNotifyInformation.Action", Field, 0}, - {"FileNotifyInformation.FileName", Field, 0}, - {"FileNotifyInformation.FileNameLength", Field, 0}, - {"FileNotifyInformation.NextEntryOffset", Field, 0}, - {"Filetime", Type, 0}, - {"Filetime.HighDateTime", Field, 0}, - {"Filetime.LowDateTime", Field, 0}, - {"FindClose", Func, 0}, - {"FindFirstFile", Func, 0}, - {"FindNextFile", Func, 0}, - {"Flock", Func, 0}, - {"Flock_t", Type, 0}, - {"Flock_t.Len", Field, 0}, - {"Flock_t.Pad_cgo_0", Field, 0}, - {"Flock_t.Pad_cgo_1", Field, 3}, - {"Flock_t.Pid", Field, 0}, - {"Flock_t.Start", Field, 0}, - {"Flock_t.Sysid", Field, 0}, - {"Flock_t.Type", Field, 0}, - {"Flock_t.Whence", Field, 0}, - {"FlushBpf", Func, 0}, - {"FlushFileBuffers", Func, 0}, - {"FlushViewOfFile", Func, 0}, - {"ForkExec", Func, 0}, - {"ForkLock", Var, 0}, - {"FormatMessage", Func, 0}, - {"Fpathconf", Func, 0}, - {"FreeAddrInfoW", Func, 1}, - {"FreeEnvironmentStrings", Func, 0}, - {"FreeLibrary", Func, 0}, - {"Fsid", Type, 0}, - {"Fsid.Val", Field, 0}, - {"Fsid.X__fsid_val", Field, 2}, - {"Fsid.X__val", Field, 0}, - {"Fstat", Func, 0}, - {"Fstatat", Func, 12}, - {"Fstatfs", Func, 0}, - {"Fstore_t", Type, 0}, - {"Fstore_t.Bytesalloc", Field, 0}, - {"Fstore_t.Flags", Field, 0}, - {"Fstore_t.Length", Field, 0}, - {"Fstore_t.Offset", Field, 0}, - {"Fstore_t.Posmode", Field, 0}, - {"Fsync", Func, 0}, - {"Ftruncate", Func, 0}, - {"FullPath", Func, 4}, - {"Futimes", Func, 0}, - {"Futimesat", Func, 0}, - {"GENERIC_ALL", Const, 0}, - {"GENERIC_EXECUTE", Const, 0}, - {"GENERIC_READ", Const, 0}, - {"GENERIC_WRITE", Const, 0}, - {"GUID", Type, 1}, - {"GUID.Data1", Field, 1}, - {"GUID.Data2", Field, 1}, - {"GUID.Data3", Field, 1}, - {"GUID.Data4", Field, 1}, - {"GetAcceptExSockaddrs", Func, 0}, - {"GetAdaptersInfo", Func, 0}, - {"GetAddrInfoW", Func, 1}, - {"GetCommandLine", Func, 0}, - {"GetComputerName", Func, 0}, - {"GetConsoleMode", Func, 1}, - {"GetCurrentDirectory", Func, 0}, - {"GetCurrentProcess", Func, 0}, - {"GetEnvironmentStrings", Func, 0}, - {"GetEnvironmentVariable", Func, 0}, - {"GetExitCodeProcess", Func, 0}, - {"GetFileAttributes", Func, 0}, - {"GetFileAttributesEx", Func, 0}, - {"GetFileExInfoStandard", Const, 0}, - {"GetFileExMaxInfoLevel", Const, 0}, - {"GetFileInformationByHandle", Func, 0}, - {"GetFileType", Func, 0}, - {"GetFullPathName", Func, 0}, - {"GetHostByName", Func, 0}, - {"GetIfEntry", Func, 0}, - {"GetLastError", Func, 0}, - {"GetLengthSid", Func, 0}, - {"GetLongPathName", Func, 0}, - {"GetProcAddress", Func, 0}, - {"GetProcessTimes", Func, 0}, - {"GetProtoByName", Func, 0}, - {"GetQueuedCompletionStatus", Func, 0}, - {"GetServByName", Func, 0}, - {"GetShortPathName", Func, 0}, - {"GetStartupInfo", Func, 0}, - {"GetStdHandle", Func, 0}, - {"GetSystemTimeAsFileTime", Func, 0}, - {"GetTempPath", Func, 0}, - {"GetTimeZoneInformation", Func, 0}, - {"GetTokenInformation", Func, 0}, - {"GetUserNameEx", Func, 0}, - {"GetUserProfileDirectory", Func, 0}, - {"GetVersion", Func, 0}, - {"Getcwd", Func, 0}, - {"Getdents", Func, 0}, - {"Getdirentries", Func, 0}, - {"Getdtablesize", Func, 0}, - {"Getegid", Func, 0}, - {"Getenv", Func, 0}, - {"Geteuid", Func, 0}, - {"Getfsstat", Func, 0}, - {"Getgid", Func, 0}, - {"Getgroups", Func, 0}, - {"Getpagesize", Func, 0}, - {"Getpeername", Func, 0}, - {"Getpgid", Func, 0}, - {"Getpgrp", Func, 0}, - {"Getpid", Func, 0}, - {"Getppid", Func, 0}, - {"Getpriority", Func, 0}, - {"Getrlimit", Func, 0}, - {"Getrusage", Func, 0}, - {"Getsid", Func, 0}, - {"Getsockname", Func, 0}, - {"Getsockopt", Func, 1}, - {"GetsockoptByte", Func, 0}, - {"GetsockoptICMPv6Filter", Func, 2}, - {"GetsockoptIPMreq", Func, 0}, - {"GetsockoptIPMreqn", Func, 0}, - {"GetsockoptIPv6MTUInfo", Func, 2}, - {"GetsockoptIPv6Mreq", Func, 0}, - {"GetsockoptInet4Addr", Func, 0}, - {"GetsockoptInt", Func, 0}, - {"GetsockoptUcred", Func, 1}, - {"Gettid", Func, 0}, - {"Gettimeofday", Func, 0}, - {"Getuid", Func, 0}, - {"Getwd", Func, 0}, - {"Getxattr", Func, 1}, - {"HANDLE_FLAG_INHERIT", Const, 0}, - {"HKEY_CLASSES_ROOT", Const, 0}, - {"HKEY_CURRENT_CONFIG", Const, 0}, - {"HKEY_CURRENT_USER", Const, 0}, - {"HKEY_DYN_DATA", Const, 0}, - {"HKEY_LOCAL_MACHINE", Const, 0}, - {"HKEY_PERFORMANCE_DATA", Const, 0}, - {"HKEY_USERS", Const, 0}, - {"HUPCL", Const, 0}, - {"Handle", Type, 0}, - {"Hostent", Type, 0}, - {"Hostent.AddrList", Field, 0}, - {"Hostent.AddrType", Field, 0}, - {"Hostent.Aliases", Field, 0}, - {"Hostent.Length", Field, 0}, - {"Hostent.Name", Field, 0}, - {"ICANON", Const, 0}, - {"ICMP6_FILTER", Const, 2}, - {"ICMPV6_FILTER", Const, 2}, - {"ICMPv6Filter", Type, 2}, - {"ICMPv6Filter.Data", Field, 2}, - {"ICMPv6Filter.Filt", Field, 2}, - {"ICRNL", Const, 0}, - {"IEXTEN", Const, 0}, - {"IFAN_ARRIVAL", Const, 1}, - {"IFAN_DEPARTURE", Const, 1}, - {"IFA_ADDRESS", Const, 0}, - {"IFA_ANYCAST", Const, 0}, - {"IFA_BROADCAST", Const, 0}, - {"IFA_CACHEINFO", Const, 0}, - {"IFA_F_DADFAILED", Const, 0}, - {"IFA_F_DEPRECATED", Const, 0}, - {"IFA_F_HOMEADDRESS", Const, 0}, - {"IFA_F_NODAD", Const, 0}, - {"IFA_F_OPTIMISTIC", Const, 0}, - {"IFA_F_PERMANENT", Const, 0}, - {"IFA_F_SECONDARY", Const, 0}, - {"IFA_F_TEMPORARY", Const, 0}, - {"IFA_F_TENTATIVE", Const, 0}, - {"IFA_LABEL", Const, 0}, - {"IFA_LOCAL", Const, 0}, - {"IFA_MAX", Const, 0}, - {"IFA_MULTICAST", Const, 0}, - {"IFA_ROUTE", Const, 1}, - {"IFA_UNSPEC", Const, 0}, - {"IFF_ALLMULTI", Const, 0}, - {"IFF_ALTPHYS", Const, 0}, - {"IFF_AUTOMEDIA", Const, 0}, - {"IFF_BROADCAST", Const, 0}, - {"IFF_CANTCHANGE", Const, 0}, - {"IFF_CANTCONFIG", Const, 1}, - {"IFF_DEBUG", Const, 0}, - {"IFF_DRV_OACTIVE", Const, 0}, - {"IFF_DRV_RUNNING", Const, 0}, - {"IFF_DYING", Const, 0}, - {"IFF_DYNAMIC", Const, 0}, - {"IFF_LINK0", Const, 0}, - {"IFF_LINK1", Const, 0}, - {"IFF_LINK2", Const, 0}, - {"IFF_LOOPBACK", Const, 0}, - {"IFF_MASTER", Const, 0}, - {"IFF_MONITOR", Const, 0}, - {"IFF_MULTICAST", Const, 0}, - {"IFF_NOARP", Const, 0}, - {"IFF_NOTRAILERS", Const, 0}, - {"IFF_NO_PI", Const, 0}, - {"IFF_OACTIVE", Const, 0}, - {"IFF_ONE_QUEUE", Const, 0}, - {"IFF_POINTOPOINT", Const, 0}, - {"IFF_POINTTOPOINT", Const, 0}, - {"IFF_PORTSEL", Const, 0}, - {"IFF_PPROMISC", Const, 0}, - {"IFF_PROMISC", Const, 0}, - {"IFF_RENAMING", Const, 0}, - {"IFF_RUNNING", Const, 0}, - {"IFF_SIMPLEX", Const, 0}, - {"IFF_SLAVE", Const, 0}, - {"IFF_SMART", Const, 0}, - {"IFF_STATICARP", Const, 0}, - {"IFF_TAP", Const, 0}, - {"IFF_TUN", Const, 0}, - {"IFF_TUN_EXCL", Const, 0}, - {"IFF_UP", Const, 0}, - {"IFF_VNET_HDR", Const, 0}, - {"IFLA_ADDRESS", Const, 0}, - {"IFLA_BROADCAST", Const, 0}, - {"IFLA_COST", Const, 0}, - {"IFLA_IFALIAS", Const, 0}, - {"IFLA_IFNAME", Const, 0}, - {"IFLA_LINK", Const, 0}, - {"IFLA_LINKINFO", Const, 0}, - {"IFLA_LINKMODE", Const, 0}, - {"IFLA_MAP", Const, 0}, - {"IFLA_MASTER", Const, 0}, - {"IFLA_MAX", Const, 0}, - {"IFLA_MTU", Const, 0}, - {"IFLA_NET_NS_PID", Const, 0}, - {"IFLA_OPERSTATE", Const, 0}, - {"IFLA_PRIORITY", Const, 0}, - {"IFLA_PROTINFO", Const, 0}, - {"IFLA_QDISC", Const, 0}, - {"IFLA_STATS", Const, 0}, - {"IFLA_TXQLEN", Const, 0}, - {"IFLA_UNSPEC", Const, 0}, - {"IFLA_WEIGHT", Const, 0}, - {"IFLA_WIRELESS", Const, 0}, - {"IFNAMSIZ", Const, 0}, - {"IFT_1822", Const, 0}, - {"IFT_A12MPPSWITCH", Const, 0}, - {"IFT_AAL2", Const, 0}, - {"IFT_AAL5", Const, 0}, - {"IFT_ADSL", Const, 0}, - {"IFT_AFLANE8023", Const, 0}, - {"IFT_AFLANE8025", Const, 0}, - {"IFT_ARAP", Const, 0}, - {"IFT_ARCNET", Const, 0}, - {"IFT_ARCNETPLUS", Const, 0}, - {"IFT_ASYNC", Const, 0}, - {"IFT_ATM", Const, 0}, - {"IFT_ATMDXI", Const, 0}, - {"IFT_ATMFUNI", Const, 0}, - {"IFT_ATMIMA", Const, 0}, - {"IFT_ATMLOGICAL", Const, 0}, - {"IFT_ATMRADIO", Const, 0}, - {"IFT_ATMSUBINTERFACE", Const, 0}, - {"IFT_ATMVCIENDPT", Const, 0}, - {"IFT_ATMVIRTUAL", Const, 0}, - {"IFT_BGPPOLICYACCOUNTING", Const, 0}, - {"IFT_BLUETOOTH", Const, 1}, - {"IFT_BRIDGE", Const, 0}, - {"IFT_BSC", Const, 0}, - {"IFT_CARP", Const, 0}, - {"IFT_CCTEMUL", Const, 0}, - {"IFT_CELLULAR", Const, 0}, - {"IFT_CEPT", Const, 0}, - {"IFT_CES", Const, 0}, - {"IFT_CHANNEL", Const, 0}, - {"IFT_CNR", Const, 0}, - {"IFT_COFFEE", Const, 0}, - {"IFT_COMPOSITELINK", Const, 0}, - {"IFT_DCN", Const, 0}, - {"IFT_DIGITALPOWERLINE", Const, 0}, - {"IFT_DIGITALWRAPPEROVERHEADCHANNEL", Const, 0}, - {"IFT_DLSW", Const, 0}, - {"IFT_DOCSCABLEDOWNSTREAM", Const, 0}, - {"IFT_DOCSCABLEMACLAYER", Const, 0}, - {"IFT_DOCSCABLEUPSTREAM", Const, 0}, - {"IFT_DOCSCABLEUPSTREAMCHANNEL", Const, 1}, - {"IFT_DS0", Const, 0}, - {"IFT_DS0BUNDLE", Const, 0}, - {"IFT_DS1FDL", Const, 0}, - {"IFT_DS3", Const, 0}, - {"IFT_DTM", Const, 0}, - {"IFT_DUMMY", Const, 1}, - {"IFT_DVBASILN", Const, 0}, - {"IFT_DVBASIOUT", Const, 0}, - {"IFT_DVBRCCDOWNSTREAM", Const, 0}, - {"IFT_DVBRCCMACLAYER", Const, 0}, - {"IFT_DVBRCCUPSTREAM", Const, 0}, - {"IFT_ECONET", Const, 1}, - {"IFT_ENC", Const, 0}, - {"IFT_EON", Const, 0}, - {"IFT_EPLRS", Const, 0}, - {"IFT_ESCON", Const, 0}, - {"IFT_ETHER", Const, 0}, - {"IFT_FAITH", Const, 0}, - {"IFT_FAST", Const, 0}, - {"IFT_FASTETHER", Const, 0}, - {"IFT_FASTETHERFX", Const, 0}, - {"IFT_FDDI", Const, 0}, - {"IFT_FIBRECHANNEL", Const, 0}, - {"IFT_FRAMERELAYINTERCONNECT", Const, 0}, - {"IFT_FRAMERELAYMPI", Const, 0}, - {"IFT_FRDLCIENDPT", Const, 0}, - {"IFT_FRELAY", Const, 0}, - {"IFT_FRELAYDCE", Const, 0}, - {"IFT_FRF16MFRBUNDLE", Const, 0}, - {"IFT_FRFORWARD", Const, 0}, - {"IFT_G703AT2MB", Const, 0}, - {"IFT_G703AT64K", Const, 0}, - {"IFT_GIF", Const, 0}, - {"IFT_GIGABITETHERNET", Const, 0}, - {"IFT_GR303IDT", Const, 0}, - {"IFT_GR303RDT", Const, 0}, - {"IFT_H323GATEKEEPER", Const, 0}, - {"IFT_H323PROXY", Const, 0}, - {"IFT_HDH1822", Const, 0}, - {"IFT_HDLC", Const, 0}, - {"IFT_HDSL2", Const, 0}, - {"IFT_HIPERLAN2", Const, 0}, - {"IFT_HIPPI", Const, 0}, - {"IFT_HIPPIINTERFACE", Const, 0}, - {"IFT_HOSTPAD", Const, 0}, - {"IFT_HSSI", Const, 0}, - {"IFT_HY", Const, 0}, - {"IFT_IBM370PARCHAN", Const, 0}, - {"IFT_IDSL", Const, 0}, - {"IFT_IEEE1394", Const, 0}, - {"IFT_IEEE80211", Const, 0}, - {"IFT_IEEE80212", Const, 0}, - {"IFT_IEEE8023ADLAG", Const, 0}, - {"IFT_IFGSN", Const, 0}, - {"IFT_IMT", Const, 0}, - {"IFT_INFINIBAND", Const, 1}, - {"IFT_INTERLEAVE", Const, 0}, - {"IFT_IP", Const, 0}, - {"IFT_IPFORWARD", Const, 0}, - {"IFT_IPOVERATM", Const, 0}, - {"IFT_IPOVERCDLC", Const, 0}, - {"IFT_IPOVERCLAW", Const, 0}, - {"IFT_IPSWITCH", Const, 0}, - {"IFT_IPXIP", Const, 0}, - {"IFT_ISDN", Const, 0}, - {"IFT_ISDNBASIC", Const, 0}, - {"IFT_ISDNPRIMARY", Const, 0}, - {"IFT_ISDNS", Const, 0}, - {"IFT_ISDNU", Const, 0}, - {"IFT_ISO88022LLC", Const, 0}, - {"IFT_ISO88023", Const, 0}, - {"IFT_ISO88024", Const, 0}, - {"IFT_ISO88025", Const, 0}, - {"IFT_ISO88025CRFPINT", Const, 0}, - {"IFT_ISO88025DTR", Const, 0}, - {"IFT_ISO88025FIBER", Const, 0}, - {"IFT_ISO88026", Const, 0}, - {"IFT_ISUP", Const, 0}, - {"IFT_L2VLAN", Const, 0}, - {"IFT_L3IPVLAN", Const, 0}, - {"IFT_L3IPXVLAN", Const, 0}, - {"IFT_LAPB", Const, 0}, - {"IFT_LAPD", Const, 0}, - {"IFT_LAPF", Const, 0}, - {"IFT_LINEGROUP", Const, 1}, - {"IFT_LOCALTALK", Const, 0}, - {"IFT_LOOP", Const, 0}, - {"IFT_MEDIAMAILOVERIP", Const, 0}, - {"IFT_MFSIGLINK", Const, 0}, - {"IFT_MIOX25", Const, 0}, - {"IFT_MODEM", Const, 0}, - {"IFT_MPC", Const, 0}, - {"IFT_MPLS", Const, 0}, - {"IFT_MPLSTUNNEL", Const, 0}, - {"IFT_MSDSL", Const, 0}, - {"IFT_MVL", Const, 0}, - {"IFT_MYRINET", Const, 0}, - {"IFT_NFAS", Const, 0}, - {"IFT_NSIP", Const, 0}, - {"IFT_OPTICALCHANNEL", Const, 0}, - {"IFT_OPTICALTRANSPORT", Const, 0}, - {"IFT_OTHER", Const, 0}, - {"IFT_P10", Const, 0}, - {"IFT_P80", Const, 0}, - {"IFT_PARA", Const, 0}, - {"IFT_PDP", Const, 0}, - {"IFT_PFLOG", Const, 0}, - {"IFT_PFLOW", Const, 1}, - {"IFT_PFSYNC", Const, 0}, - {"IFT_PLC", Const, 0}, - {"IFT_PON155", Const, 1}, - {"IFT_PON622", Const, 1}, - {"IFT_POS", Const, 0}, - {"IFT_PPP", Const, 0}, - {"IFT_PPPMULTILINKBUNDLE", Const, 0}, - {"IFT_PROPATM", Const, 1}, - {"IFT_PROPBWAP2MP", Const, 0}, - {"IFT_PROPCNLS", Const, 0}, - {"IFT_PROPDOCSWIRELESSDOWNSTREAM", Const, 0}, - {"IFT_PROPDOCSWIRELESSMACLAYER", Const, 0}, - {"IFT_PROPDOCSWIRELESSUPSTREAM", Const, 0}, - {"IFT_PROPMUX", Const, 0}, - {"IFT_PROPVIRTUAL", Const, 0}, - {"IFT_PROPWIRELESSP2P", Const, 0}, - {"IFT_PTPSERIAL", Const, 0}, - {"IFT_PVC", Const, 0}, - {"IFT_Q2931", Const, 1}, - {"IFT_QLLC", Const, 0}, - {"IFT_RADIOMAC", Const, 0}, - {"IFT_RADSL", Const, 0}, - {"IFT_REACHDSL", Const, 0}, - {"IFT_RFC1483", Const, 0}, - {"IFT_RS232", Const, 0}, - {"IFT_RSRB", Const, 0}, - {"IFT_SDLC", Const, 0}, - {"IFT_SDSL", Const, 0}, - {"IFT_SHDSL", Const, 0}, - {"IFT_SIP", Const, 0}, - {"IFT_SIPSIG", Const, 1}, - {"IFT_SIPTG", Const, 1}, - {"IFT_SLIP", Const, 0}, - {"IFT_SMDSDXI", Const, 0}, - {"IFT_SMDSICIP", Const, 0}, - {"IFT_SONET", Const, 0}, - {"IFT_SONETOVERHEADCHANNEL", Const, 0}, - {"IFT_SONETPATH", Const, 0}, - {"IFT_SONETVT", Const, 0}, - {"IFT_SRP", Const, 0}, - {"IFT_SS7SIGLINK", Const, 0}, - {"IFT_STACKTOSTACK", Const, 0}, - {"IFT_STARLAN", Const, 0}, - {"IFT_STF", Const, 0}, - {"IFT_T1", Const, 0}, - {"IFT_TDLC", Const, 0}, - {"IFT_TELINK", Const, 1}, - {"IFT_TERMPAD", Const, 0}, - {"IFT_TR008", Const, 0}, - {"IFT_TRANSPHDLC", Const, 0}, - {"IFT_TUNNEL", Const, 0}, - {"IFT_ULTRA", Const, 0}, - {"IFT_USB", Const, 0}, - {"IFT_V11", Const, 0}, - {"IFT_V35", Const, 0}, - {"IFT_V36", Const, 0}, - {"IFT_V37", Const, 0}, - {"IFT_VDSL", Const, 0}, - {"IFT_VIRTUALIPADDRESS", Const, 0}, - {"IFT_VIRTUALTG", Const, 1}, - {"IFT_VOICEDID", Const, 1}, - {"IFT_VOICEEM", Const, 0}, - {"IFT_VOICEEMFGD", Const, 1}, - {"IFT_VOICEENCAP", Const, 0}, - {"IFT_VOICEFGDEANA", Const, 1}, - {"IFT_VOICEFXO", Const, 0}, - {"IFT_VOICEFXS", Const, 0}, - {"IFT_VOICEOVERATM", Const, 0}, - {"IFT_VOICEOVERCABLE", Const, 1}, - {"IFT_VOICEOVERFRAMERELAY", Const, 0}, - {"IFT_VOICEOVERIP", Const, 0}, - {"IFT_X213", Const, 0}, - {"IFT_X25", Const, 0}, - {"IFT_X25DDN", Const, 0}, - {"IFT_X25HUNTGROUP", Const, 0}, - {"IFT_X25MLP", Const, 0}, - {"IFT_X25PLE", Const, 0}, - {"IFT_XETHER", Const, 0}, - {"IGNBRK", Const, 0}, - {"IGNCR", Const, 0}, - {"IGNORE", Const, 0}, - {"IGNPAR", Const, 0}, - {"IMAXBEL", Const, 0}, - {"INFINITE", Const, 0}, - {"INLCR", Const, 0}, - {"INPCK", Const, 0}, - {"INVALID_FILE_ATTRIBUTES", Const, 0}, - {"IN_ACCESS", Const, 0}, - {"IN_ALL_EVENTS", Const, 0}, - {"IN_ATTRIB", Const, 0}, - {"IN_CLASSA_HOST", Const, 0}, - {"IN_CLASSA_MAX", Const, 0}, - {"IN_CLASSA_NET", Const, 0}, - {"IN_CLASSA_NSHIFT", Const, 0}, - {"IN_CLASSB_HOST", Const, 0}, - {"IN_CLASSB_MAX", Const, 0}, - {"IN_CLASSB_NET", Const, 0}, - {"IN_CLASSB_NSHIFT", Const, 0}, - {"IN_CLASSC_HOST", Const, 0}, - {"IN_CLASSC_NET", Const, 0}, - {"IN_CLASSC_NSHIFT", Const, 0}, - {"IN_CLASSD_HOST", Const, 0}, - {"IN_CLASSD_NET", Const, 0}, - {"IN_CLASSD_NSHIFT", Const, 0}, - {"IN_CLOEXEC", Const, 0}, - {"IN_CLOSE", Const, 0}, - {"IN_CLOSE_NOWRITE", Const, 0}, - {"IN_CLOSE_WRITE", Const, 0}, - {"IN_CREATE", Const, 0}, - {"IN_DELETE", Const, 0}, - {"IN_DELETE_SELF", Const, 0}, - {"IN_DONT_FOLLOW", Const, 0}, - {"IN_EXCL_UNLINK", Const, 0}, - {"IN_IGNORED", Const, 0}, - {"IN_ISDIR", Const, 0}, - {"IN_LINKLOCALNETNUM", Const, 0}, - {"IN_LOOPBACKNET", Const, 0}, - {"IN_MASK_ADD", Const, 0}, - {"IN_MODIFY", Const, 0}, - {"IN_MOVE", Const, 0}, - {"IN_MOVED_FROM", Const, 0}, - {"IN_MOVED_TO", Const, 0}, - {"IN_MOVE_SELF", Const, 0}, - {"IN_NONBLOCK", Const, 0}, - {"IN_ONESHOT", Const, 0}, - {"IN_ONLYDIR", Const, 0}, - {"IN_OPEN", Const, 0}, - {"IN_Q_OVERFLOW", Const, 0}, - {"IN_RFC3021_HOST", Const, 1}, - {"IN_RFC3021_MASK", Const, 1}, - {"IN_RFC3021_NET", Const, 1}, - {"IN_RFC3021_NSHIFT", Const, 1}, - {"IN_UNMOUNT", Const, 0}, - {"IOC_IN", Const, 1}, - {"IOC_INOUT", Const, 1}, - {"IOC_OUT", Const, 1}, - {"IOC_VENDOR", Const, 3}, - {"IOC_WS2", Const, 1}, - {"IO_REPARSE_TAG_SYMLINK", Const, 4}, - {"IPMreq", Type, 0}, - {"IPMreq.Interface", Field, 0}, - {"IPMreq.Multiaddr", Field, 0}, - {"IPMreqn", Type, 0}, - {"IPMreqn.Address", Field, 0}, - {"IPMreqn.Ifindex", Field, 0}, - {"IPMreqn.Multiaddr", Field, 0}, - {"IPPROTO_3PC", Const, 0}, - {"IPPROTO_ADFS", Const, 0}, - {"IPPROTO_AH", Const, 0}, - {"IPPROTO_AHIP", Const, 0}, - {"IPPROTO_APES", Const, 0}, - {"IPPROTO_ARGUS", Const, 0}, - {"IPPROTO_AX25", Const, 0}, - {"IPPROTO_BHA", Const, 0}, - {"IPPROTO_BLT", Const, 0}, - {"IPPROTO_BRSATMON", Const, 0}, - {"IPPROTO_CARP", Const, 0}, - {"IPPROTO_CFTP", Const, 0}, - {"IPPROTO_CHAOS", Const, 0}, - {"IPPROTO_CMTP", Const, 0}, - {"IPPROTO_COMP", Const, 0}, - {"IPPROTO_CPHB", Const, 0}, - {"IPPROTO_CPNX", Const, 0}, - {"IPPROTO_DCCP", Const, 0}, - {"IPPROTO_DDP", Const, 0}, - {"IPPROTO_DGP", Const, 0}, - {"IPPROTO_DIVERT", Const, 0}, - {"IPPROTO_DIVERT_INIT", Const, 3}, - {"IPPROTO_DIVERT_RESP", Const, 3}, - {"IPPROTO_DONE", Const, 0}, - {"IPPROTO_DSTOPTS", Const, 0}, - {"IPPROTO_EGP", Const, 0}, - {"IPPROTO_EMCON", Const, 0}, - {"IPPROTO_ENCAP", Const, 0}, - {"IPPROTO_EON", Const, 0}, - {"IPPROTO_ESP", Const, 0}, - {"IPPROTO_ETHERIP", Const, 0}, - {"IPPROTO_FRAGMENT", Const, 0}, - {"IPPROTO_GGP", Const, 0}, - {"IPPROTO_GMTP", Const, 0}, - {"IPPROTO_GRE", Const, 0}, - {"IPPROTO_HELLO", Const, 0}, - {"IPPROTO_HMP", Const, 0}, - {"IPPROTO_HOPOPTS", Const, 0}, - {"IPPROTO_ICMP", Const, 0}, - {"IPPROTO_ICMPV6", Const, 0}, - {"IPPROTO_IDP", Const, 0}, - {"IPPROTO_IDPR", Const, 0}, - {"IPPROTO_IDRP", Const, 0}, - {"IPPROTO_IGMP", Const, 0}, - {"IPPROTO_IGP", Const, 0}, - {"IPPROTO_IGRP", Const, 0}, - {"IPPROTO_IL", Const, 0}, - {"IPPROTO_INLSP", Const, 0}, - {"IPPROTO_INP", Const, 0}, - {"IPPROTO_IP", Const, 0}, - {"IPPROTO_IPCOMP", Const, 0}, - {"IPPROTO_IPCV", Const, 0}, - {"IPPROTO_IPEIP", Const, 0}, - {"IPPROTO_IPIP", Const, 0}, - {"IPPROTO_IPPC", Const, 0}, - {"IPPROTO_IPV4", Const, 0}, - {"IPPROTO_IPV6", Const, 0}, - {"IPPROTO_IPV6_ICMP", Const, 1}, - {"IPPROTO_IRTP", Const, 0}, - {"IPPROTO_KRYPTOLAN", Const, 0}, - {"IPPROTO_LARP", Const, 0}, - {"IPPROTO_LEAF1", Const, 0}, - {"IPPROTO_LEAF2", Const, 0}, - {"IPPROTO_MAX", Const, 0}, - {"IPPROTO_MAXID", Const, 0}, - {"IPPROTO_MEAS", Const, 0}, - {"IPPROTO_MH", Const, 1}, - {"IPPROTO_MHRP", Const, 0}, - {"IPPROTO_MICP", Const, 0}, - {"IPPROTO_MOBILE", Const, 0}, - {"IPPROTO_MPLS", Const, 1}, - {"IPPROTO_MTP", Const, 0}, - {"IPPROTO_MUX", Const, 0}, - {"IPPROTO_ND", Const, 0}, - {"IPPROTO_NHRP", Const, 0}, - {"IPPROTO_NONE", Const, 0}, - {"IPPROTO_NSP", Const, 0}, - {"IPPROTO_NVPII", Const, 0}, - {"IPPROTO_OLD_DIVERT", Const, 0}, - {"IPPROTO_OSPFIGP", Const, 0}, - {"IPPROTO_PFSYNC", Const, 0}, - {"IPPROTO_PGM", Const, 0}, - {"IPPROTO_PIGP", Const, 0}, - {"IPPROTO_PIM", Const, 0}, - {"IPPROTO_PRM", Const, 0}, - {"IPPROTO_PUP", Const, 0}, - {"IPPROTO_PVP", Const, 0}, - {"IPPROTO_RAW", Const, 0}, - {"IPPROTO_RCCMON", Const, 0}, - {"IPPROTO_RDP", Const, 0}, - {"IPPROTO_ROUTING", Const, 0}, - {"IPPROTO_RSVP", Const, 0}, - {"IPPROTO_RVD", Const, 0}, - {"IPPROTO_SATEXPAK", Const, 0}, - {"IPPROTO_SATMON", Const, 0}, - {"IPPROTO_SCCSP", Const, 0}, - {"IPPROTO_SCTP", Const, 0}, - {"IPPROTO_SDRP", Const, 0}, - {"IPPROTO_SEND", Const, 1}, - {"IPPROTO_SEP", Const, 0}, - {"IPPROTO_SKIP", Const, 0}, - {"IPPROTO_SPACER", Const, 0}, - {"IPPROTO_SRPC", Const, 0}, - {"IPPROTO_ST", Const, 0}, - {"IPPROTO_SVMTP", Const, 0}, - {"IPPROTO_SWIPE", Const, 0}, - {"IPPROTO_TCF", Const, 0}, - {"IPPROTO_TCP", Const, 0}, - {"IPPROTO_TLSP", Const, 0}, - {"IPPROTO_TP", Const, 0}, - {"IPPROTO_TPXX", Const, 0}, - {"IPPROTO_TRUNK1", Const, 0}, - {"IPPROTO_TRUNK2", Const, 0}, - {"IPPROTO_TTP", Const, 0}, - {"IPPROTO_UDP", Const, 0}, - {"IPPROTO_UDPLITE", Const, 0}, - {"IPPROTO_VINES", Const, 0}, - {"IPPROTO_VISA", Const, 0}, - {"IPPROTO_VMTP", Const, 0}, - {"IPPROTO_VRRP", Const, 1}, - {"IPPROTO_WBEXPAK", Const, 0}, - {"IPPROTO_WBMON", Const, 0}, - {"IPPROTO_WSN", Const, 0}, - {"IPPROTO_XNET", Const, 0}, - {"IPPROTO_XTP", Const, 0}, - {"IPV6_2292DSTOPTS", Const, 0}, - {"IPV6_2292HOPLIMIT", Const, 0}, - {"IPV6_2292HOPOPTS", Const, 0}, - {"IPV6_2292NEXTHOP", Const, 0}, - {"IPV6_2292PKTINFO", Const, 0}, - {"IPV6_2292PKTOPTIONS", Const, 0}, - {"IPV6_2292RTHDR", Const, 0}, - {"IPV6_ADDRFORM", Const, 0}, - {"IPV6_ADD_MEMBERSHIP", Const, 0}, - {"IPV6_AUTHHDR", Const, 0}, - {"IPV6_AUTH_LEVEL", Const, 1}, - {"IPV6_AUTOFLOWLABEL", Const, 0}, - {"IPV6_BINDANY", Const, 0}, - {"IPV6_BINDV6ONLY", Const, 0}, - {"IPV6_BOUND_IF", Const, 0}, - {"IPV6_CHECKSUM", Const, 0}, - {"IPV6_DEFAULT_MULTICAST_HOPS", Const, 0}, - {"IPV6_DEFAULT_MULTICAST_LOOP", Const, 0}, - {"IPV6_DEFHLIM", Const, 0}, - {"IPV6_DONTFRAG", Const, 0}, - {"IPV6_DROP_MEMBERSHIP", Const, 0}, - {"IPV6_DSTOPTS", Const, 0}, - {"IPV6_ESP_NETWORK_LEVEL", Const, 1}, - {"IPV6_ESP_TRANS_LEVEL", Const, 1}, - {"IPV6_FAITH", Const, 0}, - {"IPV6_FLOWINFO_MASK", Const, 0}, - {"IPV6_FLOWLABEL_MASK", Const, 0}, - {"IPV6_FRAGTTL", Const, 0}, - {"IPV6_FW_ADD", Const, 0}, - {"IPV6_FW_DEL", Const, 0}, - {"IPV6_FW_FLUSH", Const, 0}, - {"IPV6_FW_GET", Const, 0}, - {"IPV6_FW_ZERO", Const, 0}, - {"IPV6_HLIMDEC", Const, 0}, - {"IPV6_HOPLIMIT", Const, 0}, - {"IPV6_HOPOPTS", Const, 0}, - {"IPV6_IPCOMP_LEVEL", Const, 1}, - {"IPV6_IPSEC_POLICY", Const, 0}, - {"IPV6_JOIN_ANYCAST", Const, 0}, - {"IPV6_JOIN_GROUP", Const, 0}, - {"IPV6_LEAVE_ANYCAST", Const, 0}, - {"IPV6_LEAVE_GROUP", Const, 0}, - {"IPV6_MAXHLIM", Const, 0}, - {"IPV6_MAXOPTHDR", Const, 0}, - {"IPV6_MAXPACKET", Const, 0}, - {"IPV6_MAX_GROUP_SRC_FILTER", Const, 0}, - {"IPV6_MAX_MEMBERSHIPS", Const, 0}, - {"IPV6_MAX_SOCK_SRC_FILTER", Const, 0}, - {"IPV6_MIN_MEMBERSHIPS", Const, 0}, - {"IPV6_MMTU", Const, 0}, - {"IPV6_MSFILTER", Const, 0}, - {"IPV6_MTU", Const, 0}, - {"IPV6_MTU_DISCOVER", Const, 0}, - {"IPV6_MULTICAST_HOPS", Const, 0}, - {"IPV6_MULTICAST_IF", Const, 0}, - {"IPV6_MULTICAST_LOOP", Const, 0}, - {"IPV6_NEXTHOP", Const, 0}, - {"IPV6_OPTIONS", Const, 1}, - {"IPV6_PATHMTU", Const, 0}, - {"IPV6_PIPEX", Const, 1}, - {"IPV6_PKTINFO", Const, 0}, - {"IPV6_PMTUDISC_DO", Const, 0}, - {"IPV6_PMTUDISC_DONT", Const, 0}, - {"IPV6_PMTUDISC_PROBE", Const, 0}, - {"IPV6_PMTUDISC_WANT", Const, 0}, - {"IPV6_PORTRANGE", Const, 0}, - {"IPV6_PORTRANGE_DEFAULT", Const, 0}, - {"IPV6_PORTRANGE_HIGH", Const, 0}, - {"IPV6_PORTRANGE_LOW", Const, 0}, - {"IPV6_PREFER_TEMPADDR", Const, 0}, - {"IPV6_RECVDSTOPTS", Const, 0}, - {"IPV6_RECVDSTPORT", Const, 3}, - {"IPV6_RECVERR", Const, 0}, - {"IPV6_RECVHOPLIMIT", Const, 0}, - {"IPV6_RECVHOPOPTS", Const, 0}, - {"IPV6_RECVPATHMTU", Const, 0}, - {"IPV6_RECVPKTINFO", Const, 0}, - {"IPV6_RECVRTHDR", Const, 0}, - {"IPV6_RECVTCLASS", Const, 0}, - {"IPV6_ROUTER_ALERT", Const, 0}, - {"IPV6_RTABLE", Const, 1}, - {"IPV6_RTHDR", Const, 0}, - {"IPV6_RTHDRDSTOPTS", Const, 0}, - {"IPV6_RTHDR_LOOSE", Const, 0}, - {"IPV6_RTHDR_STRICT", Const, 0}, - {"IPV6_RTHDR_TYPE_0", Const, 0}, - {"IPV6_RXDSTOPTS", Const, 0}, - {"IPV6_RXHOPOPTS", Const, 0}, - {"IPV6_SOCKOPT_RESERVED1", Const, 0}, - {"IPV6_TCLASS", Const, 0}, - {"IPV6_UNICAST_HOPS", Const, 0}, - {"IPV6_USE_MIN_MTU", Const, 0}, - {"IPV6_V6ONLY", Const, 0}, - {"IPV6_VERSION", Const, 0}, - {"IPV6_VERSION_MASK", Const, 0}, - {"IPV6_XFRM_POLICY", Const, 0}, - {"IP_ADD_MEMBERSHIP", Const, 0}, - {"IP_ADD_SOURCE_MEMBERSHIP", Const, 0}, - {"IP_AUTH_LEVEL", Const, 1}, - {"IP_BINDANY", Const, 0}, - {"IP_BLOCK_SOURCE", Const, 0}, - {"IP_BOUND_IF", Const, 0}, - {"IP_DEFAULT_MULTICAST_LOOP", Const, 0}, - {"IP_DEFAULT_MULTICAST_TTL", Const, 0}, - {"IP_DF", Const, 0}, - {"IP_DIVERTFL", Const, 3}, - {"IP_DONTFRAG", Const, 0}, - {"IP_DROP_MEMBERSHIP", Const, 0}, - {"IP_DROP_SOURCE_MEMBERSHIP", Const, 0}, - {"IP_DUMMYNET3", Const, 0}, - {"IP_DUMMYNET_CONFIGURE", Const, 0}, - {"IP_DUMMYNET_DEL", Const, 0}, - {"IP_DUMMYNET_FLUSH", Const, 0}, - {"IP_DUMMYNET_GET", Const, 0}, - {"IP_EF", Const, 1}, - {"IP_ERRORMTU", Const, 1}, - {"IP_ESP_NETWORK_LEVEL", Const, 1}, - {"IP_ESP_TRANS_LEVEL", Const, 1}, - {"IP_FAITH", Const, 0}, - {"IP_FREEBIND", Const, 0}, - {"IP_FW3", Const, 0}, - {"IP_FW_ADD", Const, 0}, - {"IP_FW_DEL", Const, 0}, - {"IP_FW_FLUSH", Const, 0}, - {"IP_FW_GET", Const, 0}, - {"IP_FW_NAT_CFG", Const, 0}, - {"IP_FW_NAT_DEL", Const, 0}, - {"IP_FW_NAT_GET_CONFIG", Const, 0}, - {"IP_FW_NAT_GET_LOG", Const, 0}, - {"IP_FW_RESETLOG", Const, 0}, - {"IP_FW_TABLE_ADD", Const, 0}, - {"IP_FW_TABLE_DEL", Const, 0}, - {"IP_FW_TABLE_FLUSH", Const, 0}, - {"IP_FW_TABLE_GETSIZE", Const, 0}, - {"IP_FW_TABLE_LIST", Const, 0}, - {"IP_FW_ZERO", Const, 0}, - {"IP_HDRINCL", Const, 0}, - {"IP_IPCOMP_LEVEL", Const, 1}, - {"IP_IPSECFLOWINFO", Const, 1}, - {"IP_IPSEC_LOCAL_AUTH", Const, 1}, - {"IP_IPSEC_LOCAL_CRED", Const, 1}, - {"IP_IPSEC_LOCAL_ID", Const, 1}, - {"IP_IPSEC_POLICY", Const, 0}, - {"IP_IPSEC_REMOTE_AUTH", Const, 1}, - {"IP_IPSEC_REMOTE_CRED", Const, 1}, - {"IP_IPSEC_REMOTE_ID", Const, 1}, - {"IP_MAXPACKET", Const, 0}, - {"IP_MAX_GROUP_SRC_FILTER", Const, 0}, - {"IP_MAX_MEMBERSHIPS", Const, 0}, - {"IP_MAX_SOCK_MUTE_FILTER", Const, 0}, - {"IP_MAX_SOCK_SRC_FILTER", Const, 0}, - {"IP_MAX_SOURCE_FILTER", Const, 0}, - {"IP_MF", Const, 0}, - {"IP_MINFRAGSIZE", Const, 1}, - {"IP_MINTTL", Const, 0}, - {"IP_MIN_MEMBERSHIPS", Const, 0}, - {"IP_MSFILTER", Const, 0}, - {"IP_MSS", Const, 0}, - {"IP_MTU", Const, 0}, - {"IP_MTU_DISCOVER", Const, 0}, - {"IP_MULTICAST_IF", Const, 0}, - {"IP_MULTICAST_IFINDEX", Const, 0}, - {"IP_MULTICAST_LOOP", Const, 0}, - {"IP_MULTICAST_TTL", Const, 0}, - {"IP_MULTICAST_VIF", Const, 0}, - {"IP_NAT__XXX", Const, 0}, - {"IP_OFFMASK", Const, 0}, - {"IP_OLD_FW_ADD", Const, 0}, - {"IP_OLD_FW_DEL", Const, 0}, - {"IP_OLD_FW_FLUSH", Const, 0}, - {"IP_OLD_FW_GET", Const, 0}, - {"IP_OLD_FW_RESETLOG", Const, 0}, - {"IP_OLD_FW_ZERO", Const, 0}, - {"IP_ONESBCAST", Const, 0}, - {"IP_OPTIONS", Const, 0}, - {"IP_ORIGDSTADDR", Const, 0}, - {"IP_PASSSEC", Const, 0}, - {"IP_PIPEX", Const, 1}, - {"IP_PKTINFO", Const, 0}, - {"IP_PKTOPTIONS", Const, 0}, - {"IP_PMTUDISC", Const, 0}, - {"IP_PMTUDISC_DO", Const, 0}, - {"IP_PMTUDISC_DONT", Const, 0}, - {"IP_PMTUDISC_PROBE", Const, 0}, - {"IP_PMTUDISC_WANT", Const, 0}, - {"IP_PORTRANGE", Const, 0}, - {"IP_PORTRANGE_DEFAULT", Const, 0}, - {"IP_PORTRANGE_HIGH", Const, 0}, - {"IP_PORTRANGE_LOW", Const, 0}, - {"IP_RECVDSTADDR", Const, 0}, - {"IP_RECVDSTPORT", Const, 1}, - {"IP_RECVERR", Const, 0}, - {"IP_RECVIF", Const, 0}, - {"IP_RECVOPTS", Const, 0}, - {"IP_RECVORIGDSTADDR", Const, 0}, - {"IP_RECVPKTINFO", Const, 0}, - {"IP_RECVRETOPTS", Const, 0}, - {"IP_RECVRTABLE", Const, 1}, - {"IP_RECVTOS", Const, 0}, - {"IP_RECVTTL", Const, 0}, - {"IP_RETOPTS", Const, 0}, - {"IP_RF", Const, 0}, - {"IP_ROUTER_ALERT", Const, 0}, - {"IP_RSVP_OFF", Const, 0}, - {"IP_RSVP_ON", Const, 0}, - {"IP_RSVP_VIF_OFF", Const, 0}, - {"IP_RSVP_VIF_ON", Const, 0}, - {"IP_RTABLE", Const, 1}, - {"IP_SENDSRCADDR", Const, 0}, - {"IP_STRIPHDR", Const, 0}, - {"IP_TOS", Const, 0}, - {"IP_TRAFFIC_MGT_BACKGROUND", Const, 0}, - {"IP_TRANSPARENT", Const, 0}, - {"IP_TTL", Const, 0}, - {"IP_UNBLOCK_SOURCE", Const, 0}, - {"IP_XFRM_POLICY", Const, 0}, - {"IPv6MTUInfo", Type, 2}, - {"IPv6MTUInfo.Addr", Field, 2}, - {"IPv6MTUInfo.Mtu", Field, 2}, - {"IPv6Mreq", Type, 0}, - {"IPv6Mreq.Interface", Field, 0}, - {"IPv6Mreq.Multiaddr", Field, 0}, - {"ISIG", Const, 0}, - {"ISTRIP", Const, 0}, - {"IUCLC", Const, 0}, - {"IUTF8", Const, 0}, - {"IXANY", Const, 0}, - {"IXOFF", Const, 0}, - {"IXON", Const, 0}, - {"IfAddrmsg", Type, 0}, - {"IfAddrmsg.Family", Field, 0}, - {"IfAddrmsg.Flags", Field, 0}, - {"IfAddrmsg.Index", Field, 0}, - {"IfAddrmsg.Prefixlen", Field, 0}, - {"IfAddrmsg.Scope", Field, 0}, - {"IfAnnounceMsghdr", Type, 1}, - {"IfAnnounceMsghdr.Hdrlen", Field, 2}, - {"IfAnnounceMsghdr.Index", Field, 1}, - {"IfAnnounceMsghdr.Msglen", Field, 1}, - {"IfAnnounceMsghdr.Name", Field, 1}, - {"IfAnnounceMsghdr.Type", Field, 1}, - {"IfAnnounceMsghdr.Version", Field, 1}, - {"IfAnnounceMsghdr.What", Field, 1}, - {"IfData", Type, 0}, - {"IfData.Addrlen", Field, 0}, - {"IfData.Baudrate", Field, 0}, - {"IfData.Capabilities", Field, 2}, - {"IfData.Collisions", Field, 0}, - {"IfData.Datalen", Field, 0}, - {"IfData.Epoch", Field, 0}, - {"IfData.Hdrlen", Field, 0}, - {"IfData.Hwassist", Field, 0}, - {"IfData.Ibytes", Field, 0}, - {"IfData.Ierrors", Field, 0}, - {"IfData.Imcasts", Field, 0}, - {"IfData.Ipackets", Field, 0}, - {"IfData.Iqdrops", Field, 0}, - {"IfData.Lastchange", Field, 0}, - {"IfData.Link_state", Field, 0}, - {"IfData.Mclpool", Field, 2}, - {"IfData.Metric", Field, 0}, - {"IfData.Mtu", Field, 0}, - {"IfData.Noproto", Field, 0}, - {"IfData.Obytes", Field, 0}, - {"IfData.Oerrors", Field, 0}, - {"IfData.Omcasts", Field, 0}, - {"IfData.Opackets", Field, 0}, - {"IfData.Pad", Field, 2}, - {"IfData.Pad_cgo_0", Field, 2}, - {"IfData.Pad_cgo_1", Field, 2}, - {"IfData.Physical", Field, 0}, - {"IfData.Recvquota", Field, 0}, - {"IfData.Recvtiming", Field, 0}, - {"IfData.Reserved1", Field, 0}, - {"IfData.Reserved2", Field, 0}, - {"IfData.Spare_char1", Field, 0}, - {"IfData.Spare_char2", Field, 0}, - {"IfData.Type", Field, 0}, - {"IfData.Typelen", Field, 0}, - {"IfData.Unused1", Field, 0}, - {"IfData.Unused2", Field, 0}, - {"IfData.Xmitquota", Field, 0}, - {"IfData.Xmittiming", Field, 0}, - {"IfInfomsg", Type, 0}, - {"IfInfomsg.Change", Field, 0}, - {"IfInfomsg.Family", Field, 0}, - {"IfInfomsg.Flags", Field, 0}, - {"IfInfomsg.Index", Field, 0}, - {"IfInfomsg.Type", Field, 0}, - {"IfInfomsg.X__ifi_pad", Field, 0}, - {"IfMsghdr", Type, 0}, - {"IfMsghdr.Addrs", Field, 0}, - {"IfMsghdr.Data", Field, 0}, - {"IfMsghdr.Flags", Field, 0}, - {"IfMsghdr.Hdrlen", Field, 2}, - {"IfMsghdr.Index", Field, 0}, - {"IfMsghdr.Msglen", Field, 0}, - {"IfMsghdr.Pad1", Field, 2}, - {"IfMsghdr.Pad2", Field, 2}, - {"IfMsghdr.Pad_cgo_0", Field, 0}, - {"IfMsghdr.Pad_cgo_1", Field, 2}, - {"IfMsghdr.Tableid", Field, 2}, - {"IfMsghdr.Type", Field, 0}, - {"IfMsghdr.Version", Field, 0}, - {"IfMsghdr.Xflags", Field, 2}, - {"IfaMsghdr", Type, 0}, - {"IfaMsghdr.Addrs", Field, 0}, - {"IfaMsghdr.Flags", Field, 0}, - {"IfaMsghdr.Hdrlen", Field, 2}, - {"IfaMsghdr.Index", Field, 0}, - {"IfaMsghdr.Metric", Field, 0}, - {"IfaMsghdr.Msglen", Field, 0}, - {"IfaMsghdr.Pad1", Field, 2}, - {"IfaMsghdr.Pad2", Field, 2}, - {"IfaMsghdr.Pad_cgo_0", Field, 0}, - {"IfaMsghdr.Tableid", Field, 2}, - {"IfaMsghdr.Type", Field, 0}, - {"IfaMsghdr.Version", Field, 0}, - {"IfmaMsghdr", Type, 0}, - {"IfmaMsghdr.Addrs", Field, 0}, - {"IfmaMsghdr.Flags", Field, 0}, - {"IfmaMsghdr.Index", Field, 0}, - {"IfmaMsghdr.Msglen", Field, 0}, - {"IfmaMsghdr.Pad_cgo_0", Field, 0}, - {"IfmaMsghdr.Type", Field, 0}, - {"IfmaMsghdr.Version", Field, 0}, - {"IfmaMsghdr2", Type, 0}, - {"IfmaMsghdr2.Addrs", Field, 0}, - {"IfmaMsghdr2.Flags", Field, 0}, - {"IfmaMsghdr2.Index", Field, 0}, - {"IfmaMsghdr2.Msglen", Field, 0}, - {"IfmaMsghdr2.Pad_cgo_0", Field, 0}, - {"IfmaMsghdr2.Refcount", Field, 0}, - {"IfmaMsghdr2.Type", Field, 0}, - {"IfmaMsghdr2.Version", Field, 0}, - {"ImplementsGetwd", Const, 0}, - {"Inet4Pktinfo", Type, 0}, - {"Inet4Pktinfo.Addr", Field, 0}, - {"Inet4Pktinfo.Ifindex", Field, 0}, - {"Inet4Pktinfo.Spec_dst", Field, 0}, - {"Inet6Pktinfo", Type, 0}, - {"Inet6Pktinfo.Addr", Field, 0}, - {"Inet6Pktinfo.Ifindex", Field, 0}, - {"InotifyAddWatch", Func, 0}, - {"InotifyEvent", Type, 0}, - {"InotifyEvent.Cookie", Field, 0}, - {"InotifyEvent.Len", Field, 0}, - {"InotifyEvent.Mask", Field, 0}, - {"InotifyEvent.Name", Field, 0}, - {"InotifyEvent.Wd", Field, 0}, - {"InotifyInit", Func, 0}, - {"InotifyInit1", Func, 0}, - {"InotifyRmWatch", Func, 0}, - {"InterfaceAddrMessage", Type, 0}, - {"InterfaceAddrMessage.Data", Field, 0}, - {"InterfaceAddrMessage.Header", Field, 0}, - {"InterfaceAnnounceMessage", Type, 1}, - {"InterfaceAnnounceMessage.Header", Field, 1}, - {"InterfaceInfo", Type, 0}, - {"InterfaceInfo.Address", Field, 0}, - {"InterfaceInfo.BroadcastAddress", Field, 0}, - {"InterfaceInfo.Flags", Field, 0}, - {"InterfaceInfo.Netmask", Field, 0}, - {"InterfaceMessage", Type, 0}, - {"InterfaceMessage.Data", Field, 0}, - {"InterfaceMessage.Header", Field, 0}, - {"InterfaceMulticastAddrMessage", Type, 0}, - {"InterfaceMulticastAddrMessage.Data", Field, 0}, - {"InterfaceMulticastAddrMessage.Header", Field, 0}, - {"InvalidHandle", Const, 0}, - {"Ioperm", Func, 0}, - {"Iopl", Func, 0}, - {"Iovec", Type, 0}, - {"Iovec.Base", Field, 0}, - {"Iovec.Len", Field, 0}, - {"IpAdapterInfo", Type, 0}, - {"IpAdapterInfo.AdapterName", Field, 0}, - {"IpAdapterInfo.Address", Field, 0}, - {"IpAdapterInfo.AddressLength", Field, 0}, - {"IpAdapterInfo.ComboIndex", Field, 0}, - {"IpAdapterInfo.CurrentIpAddress", Field, 0}, - {"IpAdapterInfo.Description", Field, 0}, - {"IpAdapterInfo.DhcpEnabled", Field, 0}, - {"IpAdapterInfo.DhcpServer", Field, 0}, - {"IpAdapterInfo.GatewayList", Field, 0}, - {"IpAdapterInfo.HaveWins", Field, 0}, - {"IpAdapterInfo.Index", Field, 0}, - {"IpAdapterInfo.IpAddressList", Field, 0}, - {"IpAdapterInfo.LeaseExpires", Field, 0}, - {"IpAdapterInfo.LeaseObtained", Field, 0}, - {"IpAdapterInfo.Next", Field, 0}, - {"IpAdapterInfo.PrimaryWinsServer", Field, 0}, - {"IpAdapterInfo.SecondaryWinsServer", Field, 0}, - {"IpAdapterInfo.Type", Field, 0}, - {"IpAddrString", Type, 0}, - {"IpAddrString.Context", Field, 0}, - {"IpAddrString.IpAddress", Field, 0}, - {"IpAddrString.IpMask", Field, 0}, - {"IpAddrString.Next", Field, 0}, - {"IpAddressString", Type, 0}, - {"IpAddressString.String", Field, 0}, - {"IpMaskString", Type, 0}, - {"IpMaskString.String", Field, 2}, - {"Issetugid", Func, 0}, - {"KEY_ALL_ACCESS", Const, 0}, - {"KEY_CREATE_LINK", Const, 0}, - {"KEY_CREATE_SUB_KEY", Const, 0}, - {"KEY_ENUMERATE_SUB_KEYS", Const, 0}, - {"KEY_EXECUTE", Const, 0}, - {"KEY_NOTIFY", Const, 0}, - {"KEY_QUERY_VALUE", Const, 0}, - {"KEY_READ", Const, 0}, - {"KEY_SET_VALUE", Const, 0}, - {"KEY_WOW64_32KEY", Const, 0}, - {"KEY_WOW64_64KEY", Const, 0}, - {"KEY_WRITE", Const, 0}, - {"Kevent", Func, 0}, - {"Kevent_t", Type, 0}, - {"Kevent_t.Data", Field, 0}, - {"Kevent_t.Fflags", Field, 0}, - {"Kevent_t.Filter", Field, 0}, - {"Kevent_t.Flags", Field, 0}, - {"Kevent_t.Ident", Field, 0}, - {"Kevent_t.Pad_cgo_0", Field, 2}, - {"Kevent_t.Udata", Field, 0}, - {"Kill", Func, 0}, - {"Klogctl", Func, 0}, - {"Kqueue", Func, 0}, - {"LANG_ENGLISH", Const, 0}, - {"LAYERED_PROTOCOL", Const, 2}, - {"LCNT_OVERLOAD_FLUSH", Const, 1}, - {"LINUX_REBOOT_CMD_CAD_OFF", Const, 0}, - {"LINUX_REBOOT_CMD_CAD_ON", Const, 0}, - {"LINUX_REBOOT_CMD_HALT", Const, 0}, - {"LINUX_REBOOT_CMD_KEXEC", Const, 0}, - {"LINUX_REBOOT_CMD_POWER_OFF", Const, 0}, - {"LINUX_REBOOT_CMD_RESTART", Const, 0}, - {"LINUX_REBOOT_CMD_RESTART2", Const, 0}, - {"LINUX_REBOOT_CMD_SW_SUSPEND", Const, 0}, - {"LINUX_REBOOT_MAGIC1", Const, 0}, - {"LINUX_REBOOT_MAGIC2", Const, 0}, - {"LOCK_EX", Const, 0}, - {"LOCK_NB", Const, 0}, - {"LOCK_SH", Const, 0}, - {"LOCK_UN", Const, 0}, - {"LazyDLL", Type, 0}, - {"LazyDLL.Name", Field, 0}, - {"LazyProc", Type, 0}, - {"LazyProc.Name", Field, 0}, - {"Lchown", Func, 0}, - {"Linger", Type, 0}, - {"Linger.Linger", Field, 0}, - {"Linger.Onoff", Field, 0}, - {"Link", Func, 0}, - {"Listen", Func, 0}, - {"Listxattr", Func, 1}, - {"LoadCancelIoEx", Func, 1}, - {"LoadConnectEx", Func, 1}, - {"LoadCreateSymbolicLink", Func, 4}, - {"LoadDLL", Func, 0}, - {"LoadGetAddrInfo", Func, 1}, - {"LoadLibrary", Func, 0}, - {"LoadSetFileCompletionNotificationModes", Func, 2}, - {"LocalFree", Func, 0}, - {"Log2phys_t", Type, 0}, - {"Log2phys_t.Contigbytes", Field, 0}, - {"Log2phys_t.Devoffset", Field, 0}, - {"Log2phys_t.Flags", Field, 0}, - {"LookupAccountName", Func, 0}, - {"LookupAccountSid", Func, 0}, - {"LookupSID", Func, 0}, - {"LsfJump", Func, 0}, - {"LsfSocket", Func, 0}, - {"LsfStmt", Func, 0}, - {"Lstat", Func, 0}, - {"MADV_AUTOSYNC", Const, 1}, - {"MADV_CAN_REUSE", Const, 0}, - {"MADV_CORE", Const, 1}, - {"MADV_DOFORK", Const, 0}, - {"MADV_DONTFORK", Const, 0}, - {"MADV_DONTNEED", Const, 0}, - {"MADV_FREE", Const, 0}, - {"MADV_FREE_REUSABLE", Const, 0}, - {"MADV_FREE_REUSE", Const, 0}, - {"MADV_HUGEPAGE", Const, 0}, - {"MADV_HWPOISON", Const, 0}, - {"MADV_MERGEABLE", Const, 0}, - {"MADV_NOCORE", Const, 1}, - {"MADV_NOHUGEPAGE", Const, 0}, - {"MADV_NORMAL", Const, 0}, - {"MADV_NOSYNC", Const, 1}, - {"MADV_PROTECT", Const, 1}, - {"MADV_RANDOM", Const, 0}, - {"MADV_REMOVE", Const, 0}, - {"MADV_SEQUENTIAL", Const, 0}, - {"MADV_SPACEAVAIL", Const, 3}, - {"MADV_UNMERGEABLE", Const, 0}, - {"MADV_WILLNEED", Const, 0}, - {"MADV_ZERO_WIRED_PAGES", Const, 0}, - {"MAP_32BIT", Const, 0}, - {"MAP_ALIGNED_SUPER", Const, 3}, - {"MAP_ALIGNMENT_16MB", Const, 3}, - {"MAP_ALIGNMENT_1TB", Const, 3}, - {"MAP_ALIGNMENT_256TB", Const, 3}, - {"MAP_ALIGNMENT_4GB", Const, 3}, - {"MAP_ALIGNMENT_64KB", Const, 3}, - {"MAP_ALIGNMENT_64PB", Const, 3}, - {"MAP_ALIGNMENT_MASK", Const, 3}, - {"MAP_ALIGNMENT_SHIFT", Const, 3}, - {"MAP_ANON", Const, 0}, - {"MAP_ANONYMOUS", Const, 0}, - {"MAP_COPY", Const, 0}, - {"MAP_DENYWRITE", Const, 0}, - {"MAP_EXECUTABLE", Const, 0}, - {"MAP_FILE", Const, 0}, - {"MAP_FIXED", Const, 0}, - {"MAP_FLAGMASK", Const, 3}, - {"MAP_GROWSDOWN", Const, 0}, - {"MAP_HASSEMAPHORE", Const, 0}, - {"MAP_HUGETLB", Const, 0}, - {"MAP_INHERIT", Const, 3}, - {"MAP_INHERIT_COPY", Const, 3}, - {"MAP_INHERIT_DEFAULT", Const, 3}, - {"MAP_INHERIT_DONATE_COPY", Const, 3}, - {"MAP_INHERIT_NONE", Const, 3}, - {"MAP_INHERIT_SHARE", Const, 3}, - {"MAP_JIT", Const, 0}, - {"MAP_LOCKED", Const, 0}, - {"MAP_NOCACHE", Const, 0}, - {"MAP_NOCORE", Const, 1}, - {"MAP_NOEXTEND", Const, 0}, - {"MAP_NONBLOCK", Const, 0}, - {"MAP_NORESERVE", Const, 0}, - {"MAP_NOSYNC", Const, 1}, - {"MAP_POPULATE", Const, 0}, - {"MAP_PREFAULT_READ", Const, 1}, - {"MAP_PRIVATE", Const, 0}, - {"MAP_RENAME", Const, 0}, - {"MAP_RESERVED0080", Const, 0}, - {"MAP_RESERVED0100", Const, 1}, - {"MAP_SHARED", Const, 0}, - {"MAP_STACK", Const, 0}, - {"MAP_TRYFIXED", Const, 3}, - {"MAP_TYPE", Const, 0}, - {"MAP_WIRED", Const, 3}, - {"MAXIMUM_REPARSE_DATA_BUFFER_SIZE", Const, 4}, - {"MAXLEN_IFDESCR", Const, 0}, - {"MAXLEN_PHYSADDR", Const, 0}, - {"MAX_ADAPTER_ADDRESS_LENGTH", Const, 0}, - {"MAX_ADAPTER_DESCRIPTION_LENGTH", Const, 0}, - {"MAX_ADAPTER_NAME_LENGTH", Const, 0}, - {"MAX_COMPUTERNAME_LENGTH", Const, 0}, - {"MAX_INTERFACE_NAME_LEN", Const, 0}, - {"MAX_LONG_PATH", Const, 0}, - {"MAX_PATH", Const, 0}, - {"MAX_PROTOCOL_CHAIN", Const, 2}, - {"MCL_CURRENT", Const, 0}, - {"MCL_FUTURE", Const, 0}, - {"MNT_DETACH", Const, 0}, - {"MNT_EXPIRE", Const, 0}, - {"MNT_FORCE", Const, 0}, - {"MSG_BCAST", Const, 1}, - {"MSG_CMSG_CLOEXEC", Const, 0}, - {"MSG_COMPAT", Const, 0}, - {"MSG_CONFIRM", Const, 0}, - {"MSG_CONTROLMBUF", Const, 1}, - {"MSG_CTRUNC", Const, 0}, - {"MSG_DONTROUTE", Const, 0}, - {"MSG_DONTWAIT", Const, 0}, - {"MSG_EOF", Const, 0}, - {"MSG_EOR", Const, 0}, - {"MSG_ERRQUEUE", Const, 0}, - {"MSG_FASTOPEN", Const, 1}, - {"MSG_FIN", Const, 0}, - {"MSG_FLUSH", Const, 0}, - {"MSG_HAVEMORE", Const, 0}, - {"MSG_HOLD", Const, 0}, - {"MSG_IOVUSRSPACE", Const, 1}, - {"MSG_LENUSRSPACE", Const, 1}, - {"MSG_MCAST", Const, 1}, - {"MSG_MORE", Const, 0}, - {"MSG_NAMEMBUF", Const, 1}, - {"MSG_NBIO", Const, 0}, - {"MSG_NEEDSA", Const, 0}, - {"MSG_NOSIGNAL", Const, 0}, - {"MSG_NOTIFICATION", Const, 0}, - {"MSG_OOB", Const, 0}, - {"MSG_PEEK", Const, 0}, - {"MSG_PROXY", Const, 0}, - {"MSG_RCVMORE", Const, 0}, - {"MSG_RST", Const, 0}, - {"MSG_SEND", Const, 0}, - {"MSG_SYN", Const, 0}, - {"MSG_TRUNC", Const, 0}, - {"MSG_TRYHARD", Const, 0}, - {"MSG_USERFLAGS", Const, 1}, - {"MSG_WAITALL", Const, 0}, - {"MSG_WAITFORONE", Const, 0}, - {"MSG_WAITSTREAM", Const, 0}, - {"MS_ACTIVE", Const, 0}, - {"MS_ASYNC", Const, 0}, - {"MS_BIND", Const, 0}, - {"MS_DEACTIVATE", Const, 0}, - {"MS_DIRSYNC", Const, 0}, - {"MS_INVALIDATE", Const, 0}, - {"MS_I_VERSION", Const, 0}, - {"MS_KERNMOUNT", Const, 0}, - {"MS_KILLPAGES", Const, 0}, - {"MS_MANDLOCK", Const, 0}, - {"MS_MGC_MSK", Const, 0}, - {"MS_MGC_VAL", Const, 0}, - {"MS_MOVE", Const, 0}, - {"MS_NOATIME", Const, 0}, - {"MS_NODEV", Const, 0}, - {"MS_NODIRATIME", Const, 0}, - {"MS_NOEXEC", Const, 0}, - {"MS_NOSUID", Const, 0}, - {"MS_NOUSER", Const, 0}, - {"MS_POSIXACL", Const, 0}, - {"MS_PRIVATE", Const, 0}, - {"MS_RDONLY", Const, 0}, - {"MS_REC", Const, 0}, - {"MS_RELATIME", Const, 0}, - {"MS_REMOUNT", Const, 0}, - {"MS_RMT_MASK", Const, 0}, - {"MS_SHARED", Const, 0}, - {"MS_SILENT", Const, 0}, - {"MS_SLAVE", Const, 0}, - {"MS_STRICTATIME", Const, 0}, - {"MS_SYNC", Const, 0}, - {"MS_SYNCHRONOUS", Const, 0}, - {"MS_UNBINDABLE", Const, 0}, - {"Madvise", Func, 0}, - {"MapViewOfFile", Func, 0}, - {"MaxTokenInfoClass", Const, 0}, - {"Mclpool", Type, 2}, - {"Mclpool.Alive", Field, 2}, - {"Mclpool.Cwm", Field, 2}, - {"Mclpool.Grown", Field, 2}, - {"Mclpool.Hwm", Field, 2}, - {"Mclpool.Lwm", Field, 2}, - {"MibIfRow", Type, 0}, - {"MibIfRow.AdminStatus", Field, 0}, - {"MibIfRow.Descr", Field, 0}, - {"MibIfRow.DescrLen", Field, 0}, - {"MibIfRow.InDiscards", Field, 0}, - {"MibIfRow.InErrors", Field, 0}, - {"MibIfRow.InNUcastPkts", Field, 0}, - {"MibIfRow.InOctets", Field, 0}, - {"MibIfRow.InUcastPkts", Field, 0}, - {"MibIfRow.InUnknownProtos", Field, 0}, - {"MibIfRow.Index", Field, 0}, - {"MibIfRow.LastChange", Field, 0}, - {"MibIfRow.Mtu", Field, 0}, - {"MibIfRow.Name", Field, 0}, - {"MibIfRow.OperStatus", Field, 0}, - {"MibIfRow.OutDiscards", Field, 0}, - {"MibIfRow.OutErrors", Field, 0}, - {"MibIfRow.OutNUcastPkts", Field, 0}, - {"MibIfRow.OutOctets", Field, 0}, - {"MibIfRow.OutQLen", Field, 0}, - {"MibIfRow.OutUcastPkts", Field, 0}, - {"MibIfRow.PhysAddr", Field, 0}, - {"MibIfRow.PhysAddrLen", Field, 0}, - {"MibIfRow.Speed", Field, 0}, - {"MibIfRow.Type", Field, 0}, - {"Mkdir", Func, 0}, - {"Mkdirat", Func, 0}, - {"Mkfifo", Func, 0}, - {"Mknod", Func, 0}, - {"Mknodat", Func, 0}, - {"Mlock", Func, 0}, - {"Mlockall", Func, 0}, - {"Mmap", Func, 0}, - {"Mount", Func, 0}, - {"MoveFile", Func, 0}, - {"Mprotect", Func, 0}, - {"Msghdr", Type, 0}, - {"Msghdr.Control", Field, 0}, - {"Msghdr.Controllen", Field, 0}, - {"Msghdr.Flags", Field, 0}, - {"Msghdr.Iov", Field, 0}, - {"Msghdr.Iovlen", Field, 0}, - {"Msghdr.Name", Field, 0}, - {"Msghdr.Namelen", Field, 0}, - {"Msghdr.Pad_cgo_0", Field, 0}, - {"Msghdr.Pad_cgo_1", Field, 0}, - {"Munlock", Func, 0}, - {"Munlockall", Func, 0}, - {"Munmap", Func, 0}, - {"MustLoadDLL", Func, 0}, - {"NAME_MAX", Const, 0}, - {"NETLINK_ADD_MEMBERSHIP", Const, 0}, - {"NETLINK_AUDIT", Const, 0}, - {"NETLINK_BROADCAST_ERROR", Const, 0}, - {"NETLINK_CONNECTOR", Const, 0}, - {"NETLINK_DNRTMSG", Const, 0}, - {"NETLINK_DROP_MEMBERSHIP", Const, 0}, - {"NETLINK_ECRYPTFS", Const, 0}, - {"NETLINK_FIB_LOOKUP", Const, 0}, - {"NETLINK_FIREWALL", Const, 0}, - {"NETLINK_GENERIC", Const, 0}, - {"NETLINK_INET_DIAG", Const, 0}, - {"NETLINK_IP6_FW", Const, 0}, - {"NETLINK_ISCSI", Const, 0}, - {"NETLINK_KOBJECT_UEVENT", Const, 0}, - {"NETLINK_NETFILTER", Const, 0}, - {"NETLINK_NFLOG", Const, 0}, - {"NETLINK_NO_ENOBUFS", Const, 0}, - {"NETLINK_PKTINFO", Const, 0}, - {"NETLINK_RDMA", Const, 0}, - {"NETLINK_ROUTE", Const, 0}, - {"NETLINK_SCSITRANSPORT", Const, 0}, - {"NETLINK_SELINUX", Const, 0}, - {"NETLINK_UNUSED", Const, 0}, - {"NETLINK_USERSOCK", Const, 0}, - {"NETLINK_XFRM", Const, 0}, - {"NET_RT_DUMP", Const, 0}, - {"NET_RT_DUMP2", Const, 0}, - {"NET_RT_FLAGS", Const, 0}, - {"NET_RT_IFLIST", Const, 0}, - {"NET_RT_IFLIST2", Const, 0}, - {"NET_RT_IFLISTL", Const, 1}, - {"NET_RT_IFMALIST", Const, 0}, - {"NET_RT_MAXID", Const, 0}, - {"NET_RT_OIFLIST", Const, 1}, - {"NET_RT_OOIFLIST", Const, 1}, - {"NET_RT_STAT", Const, 0}, - {"NET_RT_STATS", Const, 1}, - {"NET_RT_TABLE", Const, 1}, - {"NET_RT_TRASH", Const, 0}, - {"NLA_ALIGNTO", Const, 0}, - {"NLA_F_NESTED", Const, 0}, - {"NLA_F_NET_BYTEORDER", Const, 0}, - {"NLA_HDRLEN", Const, 0}, - {"NLMSG_ALIGNTO", Const, 0}, - {"NLMSG_DONE", Const, 0}, - {"NLMSG_ERROR", Const, 0}, - {"NLMSG_HDRLEN", Const, 0}, - {"NLMSG_MIN_TYPE", Const, 0}, - {"NLMSG_NOOP", Const, 0}, - {"NLMSG_OVERRUN", Const, 0}, - {"NLM_F_ACK", Const, 0}, - {"NLM_F_APPEND", Const, 0}, - {"NLM_F_ATOMIC", Const, 0}, - {"NLM_F_CREATE", Const, 0}, - {"NLM_F_DUMP", Const, 0}, - {"NLM_F_ECHO", Const, 0}, - {"NLM_F_EXCL", Const, 0}, - {"NLM_F_MATCH", Const, 0}, - {"NLM_F_MULTI", Const, 0}, - {"NLM_F_REPLACE", Const, 0}, - {"NLM_F_REQUEST", Const, 0}, - {"NLM_F_ROOT", Const, 0}, - {"NOFLSH", Const, 0}, - {"NOTE_ABSOLUTE", Const, 0}, - {"NOTE_ATTRIB", Const, 0}, - {"NOTE_BACKGROUND", Const, 16}, - {"NOTE_CHILD", Const, 0}, - {"NOTE_CRITICAL", Const, 16}, - {"NOTE_DELETE", Const, 0}, - {"NOTE_EOF", Const, 1}, - {"NOTE_EXEC", Const, 0}, - {"NOTE_EXIT", Const, 0}, - {"NOTE_EXITSTATUS", Const, 0}, - {"NOTE_EXIT_CSERROR", Const, 16}, - {"NOTE_EXIT_DECRYPTFAIL", Const, 16}, - {"NOTE_EXIT_DETAIL", Const, 16}, - {"NOTE_EXIT_DETAIL_MASK", Const, 16}, - {"NOTE_EXIT_MEMORY", Const, 16}, - {"NOTE_EXIT_REPARENTED", Const, 16}, - {"NOTE_EXTEND", Const, 0}, - {"NOTE_FFAND", Const, 0}, - {"NOTE_FFCOPY", Const, 0}, - {"NOTE_FFCTRLMASK", Const, 0}, - {"NOTE_FFLAGSMASK", Const, 0}, - {"NOTE_FFNOP", Const, 0}, - {"NOTE_FFOR", Const, 0}, - {"NOTE_FORK", Const, 0}, - {"NOTE_LEEWAY", Const, 16}, - {"NOTE_LINK", Const, 0}, - {"NOTE_LOWAT", Const, 0}, - {"NOTE_NONE", Const, 0}, - {"NOTE_NSECONDS", Const, 0}, - {"NOTE_PCTRLMASK", Const, 0}, - {"NOTE_PDATAMASK", Const, 0}, - {"NOTE_REAP", Const, 0}, - {"NOTE_RENAME", Const, 0}, - {"NOTE_RESOURCEEND", Const, 0}, - {"NOTE_REVOKE", Const, 0}, - {"NOTE_SECONDS", Const, 0}, - {"NOTE_SIGNAL", Const, 0}, - {"NOTE_TRACK", Const, 0}, - {"NOTE_TRACKERR", Const, 0}, - {"NOTE_TRIGGER", Const, 0}, - {"NOTE_TRUNCATE", Const, 1}, - {"NOTE_USECONDS", Const, 0}, - {"NOTE_VM_ERROR", Const, 0}, - {"NOTE_VM_PRESSURE", Const, 0}, - {"NOTE_VM_PRESSURE_SUDDEN_TERMINATE", Const, 0}, - {"NOTE_VM_PRESSURE_TERMINATE", Const, 0}, - {"NOTE_WRITE", Const, 0}, - {"NameCanonical", Const, 0}, - {"NameCanonicalEx", Const, 0}, - {"NameDisplay", Const, 0}, - {"NameDnsDomain", Const, 0}, - {"NameFullyQualifiedDN", Const, 0}, - {"NameSamCompatible", Const, 0}, - {"NameServicePrincipal", Const, 0}, - {"NameUniqueId", Const, 0}, - {"NameUnknown", Const, 0}, - {"NameUserPrincipal", Const, 0}, - {"Nanosleep", Func, 0}, - {"NetApiBufferFree", Func, 0}, - {"NetGetJoinInformation", Func, 2}, - {"NetSetupDomainName", Const, 2}, - {"NetSetupUnjoined", Const, 2}, - {"NetSetupUnknownStatus", Const, 2}, - {"NetSetupWorkgroupName", Const, 2}, - {"NetUserGetInfo", Func, 0}, - {"NetlinkMessage", Type, 0}, - {"NetlinkMessage.Data", Field, 0}, - {"NetlinkMessage.Header", Field, 0}, - {"NetlinkRIB", Func, 0}, - {"NetlinkRouteAttr", Type, 0}, - {"NetlinkRouteAttr.Attr", Field, 0}, - {"NetlinkRouteAttr.Value", Field, 0}, - {"NetlinkRouteRequest", Type, 0}, - {"NetlinkRouteRequest.Data", Field, 0}, - {"NetlinkRouteRequest.Header", Field, 0}, - {"NewCallback", Func, 0}, - {"NewCallbackCDecl", Func, 3}, - {"NewLazyDLL", Func, 0}, - {"NlAttr", Type, 0}, - {"NlAttr.Len", Field, 0}, - {"NlAttr.Type", Field, 0}, - {"NlMsgerr", Type, 0}, - {"NlMsgerr.Error", Field, 0}, - {"NlMsgerr.Msg", Field, 0}, - {"NlMsghdr", Type, 0}, - {"NlMsghdr.Flags", Field, 0}, - {"NlMsghdr.Len", Field, 0}, - {"NlMsghdr.Pid", Field, 0}, - {"NlMsghdr.Seq", Field, 0}, - {"NlMsghdr.Type", Field, 0}, - {"NsecToFiletime", Func, 0}, - {"NsecToTimespec", Func, 0}, - {"NsecToTimeval", Func, 0}, - {"Ntohs", Func, 0}, - {"OCRNL", Const, 0}, - {"OFDEL", Const, 0}, - {"OFILL", Const, 0}, - {"OFIOGETBMAP", Const, 1}, - {"OID_PKIX_KP_SERVER_AUTH", Var, 0}, - {"OID_SERVER_GATED_CRYPTO", Var, 0}, - {"OID_SGC_NETSCAPE", Var, 0}, - {"OLCUC", Const, 0}, - {"ONLCR", Const, 0}, - {"ONLRET", Const, 0}, - {"ONOCR", Const, 0}, - {"ONOEOT", Const, 1}, - {"OPEN_ALWAYS", Const, 0}, - {"OPEN_EXISTING", Const, 0}, - {"OPOST", Const, 0}, - {"O_ACCMODE", Const, 0}, - {"O_ALERT", Const, 0}, - {"O_ALT_IO", Const, 1}, - {"O_APPEND", Const, 0}, - {"O_ASYNC", Const, 0}, - {"O_CLOEXEC", Const, 0}, - {"O_CREAT", Const, 0}, - {"O_DIRECT", Const, 0}, - {"O_DIRECTORY", Const, 0}, - {"O_DP_GETRAWENCRYPTED", Const, 16}, - {"O_DSYNC", Const, 0}, - {"O_EVTONLY", Const, 0}, - {"O_EXCL", Const, 0}, - {"O_EXEC", Const, 0}, - {"O_EXLOCK", Const, 0}, - {"O_FSYNC", Const, 0}, - {"O_LARGEFILE", Const, 0}, - {"O_NDELAY", Const, 0}, - {"O_NOATIME", Const, 0}, - {"O_NOCTTY", Const, 0}, - {"O_NOFOLLOW", Const, 0}, - {"O_NONBLOCK", Const, 0}, - {"O_NOSIGPIPE", Const, 1}, - {"O_POPUP", Const, 0}, - {"O_RDONLY", Const, 0}, - {"O_RDWR", Const, 0}, - {"O_RSYNC", Const, 0}, - {"O_SHLOCK", Const, 0}, - {"O_SYMLINK", Const, 0}, - {"O_SYNC", Const, 0}, - {"O_TRUNC", Const, 0}, - {"O_TTY_INIT", Const, 0}, - {"O_WRONLY", Const, 0}, - {"Open", Func, 0}, - {"OpenCurrentProcessToken", Func, 0}, - {"OpenProcess", Func, 0}, - {"OpenProcessToken", Func, 0}, - {"Openat", Func, 0}, - {"Overlapped", Type, 0}, - {"Overlapped.HEvent", Field, 0}, - {"Overlapped.Internal", Field, 0}, - {"Overlapped.InternalHigh", Field, 0}, - {"Overlapped.Offset", Field, 0}, - {"Overlapped.OffsetHigh", Field, 0}, - {"PACKET_ADD_MEMBERSHIP", Const, 0}, - {"PACKET_BROADCAST", Const, 0}, - {"PACKET_DROP_MEMBERSHIP", Const, 0}, - {"PACKET_FASTROUTE", Const, 0}, - {"PACKET_HOST", Const, 0}, - {"PACKET_LOOPBACK", Const, 0}, - {"PACKET_MR_ALLMULTI", Const, 0}, - {"PACKET_MR_MULTICAST", Const, 0}, - {"PACKET_MR_PROMISC", Const, 0}, - {"PACKET_MULTICAST", Const, 0}, - {"PACKET_OTHERHOST", Const, 0}, - {"PACKET_OUTGOING", Const, 0}, - {"PACKET_RECV_OUTPUT", Const, 0}, - {"PACKET_RX_RING", Const, 0}, - {"PACKET_STATISTICS", Const, 0}, - {"PAGE_EXECUTE_READ", Const, 0}, - {"PAGE_EXECUTE_READWRITE", Const, 0}, - {"PAGE_EXECUTE_WRITECOPY", Const, 0}, - {"PAGE_READONLY", Const, 0}, - {"PAGE_READWRITE", Const, 0}, - {"PAGE_WRITECOPY", Const, 0}, - {"PARENB", Const, 0}, - {"PARMRK", Const, 0}, - {"PARODD", Const, 0}, - {"PENDIN", Const, 0}, - {"PFL_HIDDEN", Const, 2}, - {"PFL_MATCHES_PROTOCOL_ZERO", Const, 2}, - {"PFL_MULTIPLE_PROTO_ENTRIES", Const, 2}, - {"PFL_NETWORKDIRECT_PROVIDER", Const, 2}, - {"PFL_RECOMMENDED_PROTO_ENTRY", Const, 2}, - {"PF_FLUSH", Const, 1}, - {"PKCS_7_ASN_ENCODING", Const, 0}, - {"PMC5_PIPELINE_FLUSH", Const, 1}, - {"PRIO_PGRP", Const, 2}, - {"PRIO_PROCESS", Const, 2}, - {"PRIO_USER", Const, 2}, - {"PRI_IOFLUSH", Const, 1}, - {"PROCESS_QUERY_INFORMATION", Const, 0}, - {"PROCESS_TERMINATE", Const, 2}, - {"PROT_EXEC", Const, 0}, - {"PROT_GROWSDOWN", Const, 0}, - {"PROT_GROWSUP", Const, 0}, - {"PROT_NONE", Const, 0}, - {"PROT_READ", Const, 0}, - {"PROT_WRITE", Const, 0}, - {"PROV_DH_SCHANNEL", Const, 0}, - {"PROV_DSS", Const, 0}, - {"PROV_DSS_DH", Const, 0}, - {"PROV_EC_ECDSA_FULL", Const, 0}, - {"PROV_EC_ECDSA_SIG", Const, 0}, - {"PROV_EC_ECNRA_FULL", Const, 0}, - {"PROV_EC_ECNRA_SIG", Const, 0}, - {"PROV_FORTEZZA", Const, 0}, - {"PROV_INTEL_SEC", Const, 0}, - {"PROV_MS_EXCHANGE", Const, 0}, - {"PROV_REPLACE_OWF", Const, 0}, - {"PROV_RNG", Const, 0}, - {"PROV_RSA_AES", Const, 0}, - {"PROV_RSA_FULL", Const, 0}, - {"PROV_RSA_SCHANNEL", Const, 0}, - {"PROV_RSA_SIG", Const, 0}, - {"PROV_SPYRUS_LYNKS", Const, 0}, - {"PROV_SSL", Const, 0}, - {"PR_CAPBSET_DROP", Const, 0}, - {"PR_CAPBSET_READ", Const, 0}, - {"PR_CLEAR_SECCOMP_FILTER", Const, 0}, - {"PR_ENDIAN_BIG", Const, 0}, - {"PR_ENDIAN_LITTLE", Const, 0}, - {"PR_ENDIAN_PPC_LITTLE", Const, 0}, - {"PR_FPEMU_NOPRINT", Const, 0}, - {"PR_FPEMU_SIGFPE", Const, 0}, - {"PR_FP_EXC_ASYNC", Const, 0}, - {"PR_FP_EXC_DISABLED", Const, 0}, - {"PR_FP_EXC_DIV", Const, 0}, - {"PR_FP_EXC_INV", Const, 0}, - {"PR_FP_EXC_NONRECOV", Const, 0}, - {"PR_FP_EXC_OVF", Const, 0}, - {"PR_FP_EXC_PRECISE", Const, 0}, - {"PR_FP_EXC_RES", Const, 0}, - {"PR_FP_EXC_SW_ENABLE", Const, 0}, - {"PR_FP_EXC_UND", Const, 0}, - {"PR_GET_DUMPABLE", Const, 0}, - {"PR_GET_ENDIAN", Const, 0}, - {"PR_GET_FPEMU", Const, 0}, - {"PR_GET_FPEXC", Const, 0}, - {"PR_GET_KEEPCAPS", Const, 0}, - {"PR_GET_NAME", Const, 0}, - {"PR_GET_PDEATHSIG", Const, 0}, - {"PR_GET_SECCOMP", Const, 0}, - {"PR_GET_SECCOMP_FILTER", Const, 0}, - {"PR_GET_SECUREBITS", Const, 0}, - {"PR_GET_TIMERSLACK", Const, 0}, - {"PR_GET_TIMING", Const, 0}, - {"PR_GET_TSC", Const, 0}, - {"PR_GET_UNALIGN", Const, 0}, - {"PR_MCE_KILL", Const, 0}, - {"PR_MCE_KILL_CLEAR", Const, 0}, - {"PR_MCE_KILL_DEFAULT", Const, 0}, - {"PR_MCE_KILL_EARLY", Const, 0}, - {"PR_MCE_KILL_GET", Const, 0}, - {"PR_MCE_KILL_LATE", Const, 0}, - {"PR_MCE_KILL_SET", Const, 0}, - {"PR_SECCOMP_FILTER_EVENT", Const, 0}, - {"PR_SECCOMP_FILTER_SYSCALL", Const, 0}, - {"PR_SET_DUMPABLE", Const, 0}, - {"PR_SET_ENDIAN", Const, 0}, - {"PR_SET_FPEMU", Const, 0}, - {"PR_SET_FPEXC", Const, 0}, - {"PR_SET_KEEPCAPS", Const, 0}, - {"PR_SET_NAME", Const, 0}, - {"PR_SET_PDEATHSIG", Const, 0}, - {"PR_SET_PTRACER", Const, 0}, - {"PR_SET_SECCOMP", Const, 0}, - {"PR_SET_SECCOMP_FILTER", Const, 0}, - {"PR_SET_SECUREBITS", Const, 0}, - {"PR_SET_TIMERSLACK", Const, 0}, - {"PR_SET_TIMING", Const, 0}, - {"PR_SET_TSC", Const, 0}, - {"PR_SET_UNALIGN", Const, 0}, - {"PR_TASK_PERF_EVENTS_DISABLE", Const, 0}, - {"PR_TASK_PERF_EVENTS_ENABLE", Const, 0}, - {"PR_TIMING_STATISTICAL", Const, 0}, - {"PR_TIMING_TIMESTAMP", Const, 0}, - {"PR_TSC_ENABLE", Const, 0}, - {"PR_TSC_SIGSEGV", Const, 0}, - {"PR_UNALIGN_NOPRINT", Const, 0}, - {"PR_UNALIGN_SIGBUS", Const, 0}, - {"PTRACE_ARCH_PRCTL", Const, 0}, - {"PTRACE_ATTACH", Const, 0}, - {"PTRACE_CONT", Const, 0}, - {"PTRACE_DETACH", Const, 0}, - {"PTRACE_EVENT_CLONE", Const, 0}, - {"PTRACE_EVENT_EXEC", Const, 0}, - {"PTRACE_EVENT_EXIT", Const, 0}, - {"PTRACE_EVENT_FORK", Const, 0}, - {"PTRACE_EVENT_VFORK", Const, 0}, - {"PTRACE_EVENT_VFORK_DONE", Const, 0}, - {"PTRACE_GETCRUNCHREGS", Const, 0}, - {"PTRACE_GETEVENTMSG", Const, 0}, - {"PTRACE_GETFPREGS", Const, 0}, - {"PTRACE_GETFPXREGS", Const, 0}, - {"PTRACE_GETHBPREGS", Const, 0}, - {"PTRACE_GETREGS", Const, 0}, - {"PTRACE_GETREGSET", Const, 0}, - {"PTRACE_GETSIGINFO", Const, 0}, - {"PTRACE_GETVFPREGS", Const, 0}, - {"PTRACE_GETWMMXREGS", Const, 0}, - {"PTRACE_GET_THREAD_AREA", Const, 0}, - {"PTRACE_KILL", Const, 0}, - {"PTRACE_OLDSETOPTIONS", Const, 0}, - {"PTRACE_O_MASK", Const, 0}, - {"PTRACE_O_TRACECLONE", Const, 0}, - {"PTRACE_O_TRACEEXEC", Const, 0}, - {"PTRACE_O_TRACEEXIT", Const, 0}, - {"PTRACE_O_TRACEFORK", Const, 0}, - {"PTRACE_O_TRACESYSGOOD", Const, 0}, - {"PTRACE_O_TRACEVFORK", Const, 0}, - {"PTRACE_O_TRACEVFORKDONE", Const, 0}, - {"PTRACE_PEEKDATA", Const, 0}, - {"PTRACE_PEEKTEXT", Const, 0}, - {"PTRACE_PEEKUSR", Const, 0}, - {"PTRACE_POKEDATA", Const, 0}, - {"PTRACE_POKETEXT", Const, 0}, - {"PTRACE_POKEUSR", Const, 0}, - {"PTRACE_SETCRUNCHREGS", Const, 0}, - {"PTRACE_SETFPREGS", Const, 0}, - {"PTRACE_SETFPXREGS", Const, 0}, - {"PTRACE_SETHBPREGS", Const, 0}, - {"PTRACE_SETOPTIONS", Const, 0}, - {"PTRACE_SETREGS", Const, 0}, - {"PTRACE_SETREGSET", Const, 0}, - {"PTRACE_SETSIGINFO", Const, 0}, - {"PTRACE_SETVFPREGS", Const, 0}, - {"PTRACE_SETWMMXREGS", Const, 0}, - {"PTRACE_SET_SYSCALL", Const, 0}, - {"PTRACE_SET_THREAD_AREA", Const, 0}, - {"PTRACE_SINGLEBLOCK", Const, 0}, - {"PTRACE_SINGLESTEP", Const, 0}, - {"PTRACE_SYSCALL", Const, 0}, - {"PTRACE_SYSEMU", Const, 0}, - {"PTRACE_SYSEMU_SINGLESTEP", Const, 0}, - {"PTRACE_TRACEME", Const, 0}, - {"PT_ATTACH", Const, 0}, - {"PT_ATTACHEXC", Const, 0}, - {"PT_CONTINUE", Const, 0}, - {"PT_DATA_ADDR", Const, 0}, - {"PT_DENY_ATTACH", Const, 0}, - {"PT_DETACH", Const, 0}, - {"PT_FIRSTMACH", Const, 0}, - {"PT_FORCEQUOTA", Const, 0}, - {"PT_KILL", Const, 0}, - {"PT_MASK", Const, 1}, - {"PT_READ_D", Const, 0}, - {"PT_READ_I", Const, 0}, - {"PT_READ_U", Const, 0}, - {"PT_SIGEXC", Const, 0}, - {"PT_STEP", Const, 0}, - {"PT_TEXT_ADDR", Const, 0}, - {"PT_TEXT_END_ADDR", Const, 0}, - {"PT_THUPDATE", Const, 0}, - {"PT_TRACE_ME", Const, 0}, - {"PT_WRITE_D", Const, 0}, - {"PT_WRITE_I", Const, 0}, - {"PT_WRITE_U", Const, 0}, - {"ParseDirent", Func, 0}, - {"ParseNetlinkMessage", Func, 0}, - {"ParseNetlinkRouteAttr", Func, 0}, - {"ParseRoutingMessage", Func, 0}, - {"ParseRoutingSockaddr", Func, 0}, - {"ParseSocketControlMessage", Func, 0}, - {"ParseUnixCredentials", Func, 0}, - {"ParseUnixRights", Func, 0}, - {"PathMax", Const, 0}, - {"Pathconf", Func, 0}, - {"Pause", Func, 0}, - {"Pipe", Func, 0}, - {"Pipe2", Func, 1}, - {"PivotRoot", Func, 0}, - {"Pointer", Type, 11}, - {"PostQueuedCompletionStatus", Func, 0}, - {"Pread", Func, 0}, - {"Proc", Type, 0}, - {"Proc.Dll", Field, 0}, - {"Proc.Name", Field, 0}, - {"ProcAttr", Type, 0}, - {"ProcAttr.Dir", Field, 0}, - {"ProcAttr.Env", Field, 0}, - {"ProcAttr.Files", Field, 0}, - {"ProcAttr.Sys", Field, 0}, - {"Process32First", Func, 4}, - {"Process32Next", Func, 4}, - {"ProcessEntry32", Type, 4}, - {"ProcessEntry32.DefaultHeapID", Field, 4}, - {"ProcessEntry32.ExeFile", Field, 4}, - {"ProcessEntry32.Flags", Field, 4}, - {"ProcessEntry32.ModuleID", Field, 4}, - {"ProcessEntry32.ParentProcessID", Field, 4}, - {"ProcessEntry32.PriClassBase", Field, 4}, - {"ProcessEntry32.ProcessID", Field, 4}, - {"ProcessEntry32.Size", Field, 4}, - {"ProcessEntry32.Threads", Field, 4}, - {"ProcessEntry32.Usage", Field, 4}, - {"ProcessInformation", Type, 0}, - {"ProcessInformation.Process", Field, 0}, - {"ProcessInformation.ProcessId", Field, 0}, - {"ProcessInformation.Thread", Field, 0}, - {"ProcessInformation.ThreadId", Field, 0}, - {"Protoent", Type, 0}, - {"Protoent.Aliases", Field, 0}, - {"Protoent.Name", Field, 0}, - {"Protoent.Proto", Field, 0}, - {"PtraceAttach", Func, 0}, - {"PtraceCont", Func, 0}, - {"PtraceDetach", Func, 0}, - {"PtraceGetEventMsg", Func, 0}, - {"PtraceGetRegs", Func, 0}, - {"PtracePeekData", Func, 0}, - {"PtracePeekText", Func, 0}, - {"PtracePokeData", Func, 0}, - {"PtracePokeText", Func, 0}, - {"PtraceRegs", Type, 0}, - {"PtraceRegs.Cs", Field, 0}, - {"PtraceRegs.Ds", Field, 0}, - {"PtraceRegs.Eax", Field, 0}, - {"PtraceRegs.Ebp", Field, 0}, - {"PtraceRegs.Ebx", Field, 0}, - {"PtraceRegs.Ecx", Field, 0}, - {"PtraceRegs.Edi", Field, 0}, - {"PtraceRegs.Edx", Field, 0}, - {"PtraceRegs.Eflags", Field, 0}, - {"PtraceRegs.Eip", Field, 0}, - {"PtraceRegs.Es", Field, 0}, - {"PtraceRegs.Esi", Field, 0}, - {"PtraceRegs.Esp", Field, 0}, - {"PtraceRegs.Fs", Field, 0}, - {"PtraceRegs.Fs_base", Field, 0}, - {"PtraceRegs.Gs", Field, 0}, - {"PtraceRegs.Gs_base", Field, 0}, - {"PtraceRegs.Orig_eax", Field, 0}, - {"PtraceRegs.Orig_rax", Field, 0}, - {"PtraceRegs.R10", Field, 0}, - {"PtraceRegs.R11", Field, 0}, - {"PtraceRegs.R12", Field, 0}, - {"PtraceRegs.R13", Field, 0}, - {"PtraceRegs.R14", Field, 0}, - {"PtraceRegs.R15", Field, 0}, - {"PtraceRegs.R8", Field, 0}, - {"PtraceRegs.R9", Field, 0}, - {"PtraceRegs.Rax", Field, 0}, - {"PtraceRegs.Rbp", Field, 0}, - {"PtraceRegs.Rbx", Field, 0}, - {"PtraceRegs.Rcx", Field, 0}, - {"PtraceRegs.Rdi", Field, 0}, - {"PtraceRegs.Rdx", Field, 0}, - {"PtraceRegs.Rip", Field, 0}, - {"PtraceRegs.Rsi", Field, 0}, - {"PtraceRegs.Rsp", Field, 0}, - {"PtraceRegs.Ss", Field, 0}, - {"PtraceRegs.Uregs", Field, 0}, - {"PtraceRegs.Xcs", Field, 0}, - {"PtraceRegs.Xds", Field, 0}, - {"PtraceRegs.Xes", Field, 0}, - {"PtraceRegs.Xfs", Field, 0}, - {"PtraceRegs.Xgs", Field, 0}, - {"PtraceRegs.Xss", Field, 0}, - {"PtraceSetOptions", Func, 0}, - {"PtraceSetRegs", Func, 0}, - {"PtraceSingleStep", Func, 0}, - {"PtraceSyscall", Func, 1}, - {"Pwrite", Func, 0}, - {"REG_BINARY", Const, 0}, - {"REG_DWORD", Const, 0}, - {"REG_DWORD_BIG_ENDIAN", Const, 0}, - {"REG_DWORD_LITTLE_ENDIAN", Const, 0}, - {"REG_EXPAND_SZ", Const, 0}, - {"REG_FULL_RESOURCE_DESCRIPTOR", Const, 0}, - {"REG_LINK", Const, 0}, - {"REG_MULTI_SZ", Const, 0}, - {"REG_NONE", Const, 0}, - {"REG_QWORD", Const, 0}, - {"REG_QWORD_LITTLE_ENDIAN", Const, 0}, - {"REG_RESOURCE_LIST", Const, 0}, - {"REG_RESOURCE_REQUIREMENTS_LIST", Const, 0}, - {"REG_SZ", Const, 0}, - {"RLIMIT_AS", Const, 0}, - {"RLIMIT_CORE", Const, 0}, - {"RLIMIT_CPU", Const, 0}, - {"RLIMIT_CPU_USAGE_MONITOR", Const, 16}, - {"RLIMIT_DATA", Const, 0}, - {"RLIMIT_FSIZE", Const, 0}, - {"RLIMIT_NOFILE", Const, 0}, - {"RLIMIT_STACK", Const, 0}, - {"RLIM_INFINITY", Const, 0}, - {"RTAX_ADVMSS", Const, 0}, - {"RTAX_AUTHOR", Const, 0}, - {"RTAX_BRD", Const, 0}, - {"RTAX_CWND", Const, 0}, - {"RTAX_DST", Const, 0}, - {"RTAX_FEATURES", Const, 0}, - {"RTAX_FEATURE_ALLFRAG", Const, 0}, - {"RTAX_FEATURE_ECN", Const, 0}, - {"RTAX_FEATURE_SACK", Const, 0}, - {"RTAX_FEATURE_TIMESTAMP", Const, 0}, - {"RTAX_GATEWAY", Const, 0}, - {"RTAX_GENMASK", Const, 0}, - {"RTAX_HOPLIMIT", Const, 0}, - {"RTAX_IFA", Const, 0}, - {"RTAX_IFP", Const, 0}, - {"RTAX_INITCWND", Const, 0}, - {"RTAX_INITRWND", Const, 0}, - {"RTAX_LABEL", Const, 1}, - {"RTAX_LOCK", Const, 0}, - {"RTAX_MAX", Const, 0}, - {"RTAX_MTU", Const, 0}, - {"RTAX_NETMASK", Const, 0}, - {"RTAX_REORDERING", Const, 0}, - {"RTAX_RTO_MIN", Const, 0}, - {"RTAX_RTT", Const, 0}, - {"RTAX_RTTVAR", Const, 0}, - {"RTAX_SRC", Const, 1}, - {"RTAX_SRCMASK", Const, 1}, - {"RTAX_SSTHRESH", Const, 0}, - {"RTAX_TAG", Const, 1}, - {"RTAX_UNSPEC", Const, 0}, - {"RTAX_WINDOW", Const, 0}, - {"RTA_ALIGNTO", Const, 0}, - {"RTA_AUTHOR", Const, 0}, - {"RTA_BRD", Const, 0}, - {"RTA_CACHEINFO", Const, 0}, - {"RTA_DST", Const, 0}, - {"RTA_FLOW", Const, 0}, - {"RTA_GATEWAY", Const, 0}, - {"RTA_GENMASK", Const, 0}, - {"RTA_IFA", Const, 0}, - {"RTA_IFP", Const, 0}, - {"RTA_IIF", Const, 0}, - {"RTA_LABEL", Const, 1}, - {"RTA_MAX", Const, 0}, - {"RTA_METRICS", Const, 0}, - {"RTA_MULTIPATH", Const, 0}, - {"RTA_NETMASK", Const, 0}, - {"RTA_OIF", Const, 0}, - {"RTA_PREFSRC", Const, 0}, - {"RTA_PRIORITY", Const, 0}, - {"RTA_SRC", Const, 0}, - {"RTA_SRCMASK", Const, 1}, - {"RTA_TABLE", Const, 0}, - {"RTA_TAG", Const, 1}, - {"RTA_UNSPEC", Const, 0}, - {"RTCF_DIRECTSRC", Const, 0}, - {"RTCF_DOREDIRECT", Const, 0}, - {"RTCF_LOG", Const, 0}, - {"RTCF_MASQ", Const, 0}, - {"RTCF_NAT", Const, 0}, - {"RTCF_VALVE", Const, 0}, - {"RTF_ADDRCLASSMASK", Const, 0}, - {"RTF_ADDRCONF", Const, 0}, - {"RTF_ALLONLINK", Const, 0}, - {"RTF_ANNOUNCE", Const, 1}, - {"RTF_BLACKHOLE", Const, 0}, - {"RTF_BROADCAST", Const, 0}, - {"RTF_CACHE", Const, 0}, - {"RTF_CLONED", Const, 1}, - {"RTF_CLONING", Const, 0}, - {"RTF_CONDEMNED", Const, 0}, - {"RTF_DEFAULT", Const, 0}, - {"RTF_DELCLONE", Const, 0}, - {"RTF_DONE", Const, 0}, - {"RTF_DYNAMIC", Const, 0}, - {"RTF_FLOW", Const, 0}, - {"RTF_FMASK", Const, 0}, - {"RTF_GATEWAY", Const, 0}, - {"RTF_GWFLAG_COMPAT", Const, 3}, - {"RTF_HOST", Const, 0}, - {"RTF_IFREF", Const, 0}, - {"RTF_IFSCOPE", Const, 0}, - {"RTF_INTERFACE", Const, 0}, - {"RTF_IRTT", Const, 0}, - {"RTF_LINKRT", Const, 0}, - {"RTF_LLDATA", Const, 0}, - {"RTF_LLINFO", Const, 0}, - {"RTF_LOCAL", Const, 0}, - {"RTF_MASK", Const, 1}, - {"RTF_MODIFIED", Const, 0}, - {"RTF_MPATH", Const, 1}, - {"RTF_MPLS", Const, 1}, - {"RTF_MSS", Const, 0}, - {"RTF_MTU", Const, 0}, - {"RTF_MULTICAST", Const, 0}, - {"RTF_NAT", Const, 0}, - {"RTF_NOFORWARD", Const, 0}, - {"RTF_NONEXTHOP", Const, 0}, - {"RTF_NOPMTUDISC", Const, 0}, - {"RTF_PERMANENT_ARP", Const, 1}, - {"RTF_PINNED", Const, 0}, - {"RTF_POLICY", Const, 0}, - {"RTF_PRCLONING", Const, 0}, - {"RTF_PROTO1", Const, 0}, - {"RTF_PROTO2", Const, 0}, - {"RTF_PROTO3", Const, 0}, - {"RTF_PROXY", Const, 16}, - {"RTF_REINSTATE", Const, 0}, - {"RTF_REJECT", Const, 0}, - {"RTF_RNH_LOCKED", Const, 0}, - {"RTF_ROUTER", Const, 16}, - {"RTF_SOURCE", Const, 1}, - {"RTF_SRC", Const, 1}, - {"RTF_STATIC", Const, 0}, - {"RTF_STICKY", Const, 0}, - {"RTF_THROW", Const, 0}, - {"RTF_TUNNEL", Const, 1}, - {"RTF_UP", Const, 0}, - {"RTF_USETRAILERS", Const, 1}, - {"RTF_WASCLONED", Const, 0}, - {"RTF_WINDOW", Const, 0}, - {"RTF_XRESOLVE", Const, 0}, - {"RTM_ADD", Const, 0}, - {"RTM_BASE", Const, 0}, - {"RTM_CHANGE", Const, 0}, - {"RTM_CHGADDR", Const, 1}, - {"RTM_DELACTION", Const, 0}, - {"RTM_DELADDR", Const, 0}, - {"RTM_DELADDRLABEL", Const, 0}, - {"RTM_DELETE", Const, 0}, - {"RTM_DELLINK", Const, 0}, - {"RTM_DELMADDR", Const, 0}, - {"RTM_DELNEIGH", Const, 0}, - {"RTM_DELQDISC", Const, 0}, - {"RTM_DELROUTE", Const, 0}, - {"RTM_DELRULE", Const, 0}, - {"RTM_DELTCLASS", Const, 0}, - {"RTM_DELTFILTER", Const, 0}, - {"RTM_DESYNC", Const, 1}, - {"RTM_F_CLONED", Const, 0}, - {"RTM_F_EQUALIZE", Const, 0}, - {"RTM_F_NOTIFY", Const, 0}, - {"RTM_F_PREFIX", Const, 0}, - {"RTM_GET", Const, 0}, - {"RTM_GET2", Const, 0}, - {"RTM_GETACTION", Const, 0}, - {"RTM_GETADDR", Const, 0}, - {"RTM_GETADDRLABEL", Const, 0}, - {"RTM_GETANYCAST", Const, 0}, - {"RTM_GETDCB", Const, 0}, - {"RTM_GETLINK", Const, 0}, - {"RTM_GETMULTICAST", Const, 0}, - {"RTM_GETNEIGH", Const, 0}, - {"RTM_GETNEIGHTBL", Const, 0}, - {"RTM_GETQDISC", Const, 0}, - {"RTM_GETROUTE", Const, 0}, - {"RTM_GETRULE", Const, 0}, - {"RTM_GETTCLASS", Const, 0}, - {"RTM_GETTFILTER", Const, 0}, - {"RTM_IEEE80211", Const, 0}, - {"RTM_IFANNOUNCE", Const, 0}, - {"RTM_IFINFO", Const, 0}, - {"RTM_IFINFO2", Const, 0}, - {"RTM_LLINFO_UPD", Const, 1}, - {"RTM_LOCK", Const, 0}, - {"RTM_LOSING", Const, 0}, - {"RTM_MAX", Const, 0}, - {"RTM_MAXSIZE", Const, 1}, - {"RTM_MISS", Const, 0}, - {"RTM_NEWACTION", Const, 0}, - {"RTM_NEWADDR", Const, 0}, - {"RTM_NEWADDRLABEL", Const, 0}, - {"RTM_NEWLINK", Const, 0}, - {"RTM_NEWMADDR", Const, 0}, - {"RTM_NEWMADDR2", Const, 0}, - {"RTM_NEWNDUSEROPT", Const, 0}, - {"RTM_NEWNEIGH", Const, 0}, - {"RTM_NEWNEIGHTBL", Const, 0}, - {"RTM_NEWPREFIX", Const, 0}, - {"RTM_NEWQDISC", Const, 0}, - {"RTM_NEWROUTE", Const, 0}, - {"RTM_NEWRULE", Const, 0}, - {"RTM_NEWTCLASS", Const, 0}, - {"RTM_NEWTFILTER", Const, 0}, - {"RTM_NR_FAMILIES", Const, 0}, - {"RTM_NR_MSGTYPES", Const, 0}, - {"RTM_OIFINFO", Const, 1}, - {"RTM_OLDADD", Const, 0}, - {"RTM_OLDDEL", Const, 0}, - {"RTM_OOIFINFO", Const, 1}, - {"RTM_REDIRECT", Const, 0}, - {"RTM_RESOLVE", Const, 0}, - {"RTM_RTTUNIT", Const, 0}, - {"RTM_SETDCB", Const, 0}, - {"RTM_SETGATE", Const, 1}, - {"RTM_SETLINK", Const, 0}, - {"RTM_SETNEIGHTBL", Const, 0}, - {"RTM_VERSION", Const, 0}, - {"RTNH_ALIGNTO", Const, 0}, - {"RTNH_F_DEAD", Const, 0}, - {"RTNH_F_ONLINK", Const, 0}, - {"RTNH_F_PERVASIVE", Const, 0}, - {"RTNLGRP_IPV4_IFADDR", Const, 1}, - {"RTNLGRP_IPV4_MROUTE", Const, 1}, - {"RTNLGRP_IPV4_ROUTE", Const, 1}, - {"RTNLGRP_IPV4_RULE", Const, 1}, - {"RTNLGRP_IPV6_IFADDR", Const, 1}, - {"RTNLGRP_IPV6_IFINFO", Const, 1}, - {"RTNLGRP_IPV6_MROUTE", Const, 1}, - {"RTNLGRP_IPV6_PREFIX", Const, 1}, - {"RTNLGRP_IPV6_ROUTE", Const, 1}, - {"RTNLGRP_IPV6_RULE", Const, 1}, - {"RTNLGRP_LINK", Const, 1}, - {"RTNLGRP_ND_USEROPT", Const, 1}, - {"RTNLGRP_NEIGH", Const, 1}, - {"RTNLGRP_NONE", Const, 1}, - {"RTNLGRP_NOTIFY", Const, 1}, - {"RTNLGRP_TC", Const, 1}, - {"RTN_ANYCAST", Const, 0}, - {"RTN_BLACKHOLE", Const, 0}, - {"RTN_BROADCAST", Const, 0}, - {"RTN_LOCAL", Const, 0}, - {"RTN_MAX", Const, 0}, - {"RTN_MULTICAST", Const, 0}, - {"RTN_NAT", Const, 0}, - {"RTN_PROHIBIT", Const, 0}, - {"RTN_THROW", Const, 0}, - {"RTN_UNICAST", Const, 0}, - {"RTN_UNREACHABLE", Const, 0}, - {"RTN_UNSPEC", Const, 0}, - {"RTN_XRESOLVE", Const, 0}, - {"RTPROT_BIRD", Const, 0}, - {"RTPROT_BOOT", Const, 0}, - {"RTPROT_DHCP", Const, 0}, - {"RTPROT_DNROUTED", Const, 0}, - {"RTPROT_GATED", Const, 0}, - {"RTPROT_KERNEL", Const, 0}, - {"RTPROT_MRT", Const, 0}, - {"RTPROT_NTK", Const, 0}, - {"RTPROT_RA", Const, 0}, - {"RTPROT_REDIRECT", Const, 0}, - {"RTPROT_STATIC", Const, 0}, - {"RTPROT_UNSPEC", Const, 0}, - {"RTPROT_XORP", Const, 0}, - {"RTPROT_ZEBRA", Const, 0}, - {"RTV_EXPIRE", Const, 0}, - {"RTV_HOPCOUNT", Const, 0}, - {"RTV_MTU", Const, 0}, - {"RTV_RPIPE", Const, 0}, - {"RTV_RTT", Const, 0}, - {"RTV_RTTVAR", Const, 0}, - {"RTV_SPIPE", Const, 0}, - {"RTV_SSTHRESH", Const, 0}, - {"RTV_WEIGHT", Const, 0}, - {"RT_CACHING_CONTEXT", Const, 1}, - {"RT_CLASS_DEFAULT", Const, 0}, - {"RT_CLASS_LOCAL", Const, 0}, - {"RT_CLASS_MAIN", Const, 0}, - {"RT_CLASS_MAX", Const, 0}, - {"RT_CLASS_UNSPEC", Const, 0}, - {"RT_DEFAULT_FIB", Const, 1}, - {"RT_NORTREF", Const, 1}, - {"RT_SCOPE_HOST", Const, 0}, - {"RT_SCOPE_LINK", Const, 0}, - {"RT_SCOPE_NOWHERE", Const, 0}, - {"RT_SCOPE_SITE", Const, 0}, - {"RT_SCOPE_UNIVERSE", Const, 0}, - {"RT_TABLEID_MAX", Const, 1}, - {"RT_TABLE_COMPAT", Const, 0}, - {"RT_TABLE_DEFAULT", Const, 0}, - {"RT_TABLE_LOCAL", Const, 0}, - {"RT_TABLE_MAIN", Const, 0}, - {"RT_TABLE_MAX", Const, 0}, - {"RT_TABLE_UNSPEC", Const, 0}, - {"RUSAGE_CHILDREN", Const, 0}, - {"RUSAGE_SELF", Const, 0}, - {"RUSAGE_THREAD", Const, 0}, - {"Radvisory_t", Type, 0}, - {"Radvisory_t.Count", Field, 0}, - {"Radvisory_t.Offset", Field, 0}, - {"Radvisory_t.Pad_cgo_0", Field, 0}, - {"RawConn", Type, 9}, - {"RawSockaddr", Type, 0}, - {"RawSockaddr.Data", Field, 0}, - {"RawSockaddr.Family", Field, 0}, - {"RawSockaddr.Len", Field, 0}, - {"RawSockaddrAny", Type, 0}, - {"RawSockaddrAny.Addr", Field, 0}, - {"RawSockaddrAny.Pad", Field, 0}, - {"RawSockaddrDatalink", Type, 0}, - {"RawSockaddrDatalink.Alen", Field, 0}, - {"RawSockaddrDatalink.Data", Field, 0}, - {"RawSockaddrDatalink.Family", Field, 0}, - {"RawSockaddrDatalink.Index", Field, 0}, - {"RawSockaddrDatalink.Len", Field, 0}, - {"RawSockaddrDatalink.Nlen", Field, 0}, - {"RawSockaddrDatalink.Pad_cgo_0", Field, 2}, - {"RawSockaddrDatalink.Slen", Field, 0}, - {"RawSockaddrDatalink.Type", Field, 0}, - {"RawSockaddrInet4", Type, 0}, - {"RawSockaddrInet4.Addr", Field, 0}, - {"RawSockaddrInet4.Family", Field, 0}, - {"RawSockaddrInet4.Len", Field, 0}, - {"RawSockaddrInet4.Port", Field, 0}, - {"RawSockaddrInet4.Zero", Field, 0}, - {"RawSockaddrInet6", Type, 0}, - {"RawSockaddrInet6.Addr", Field, 0}, - {"RawSockaddrInet6.Family", Field, 0}, - {"RawSockaddrInet6.Flowinfo", Field, 0}, - {"RawSockaddrInet6.Len", Field, 0}, - {"RawSockaddrInet6.Port", Field, 0}, - {"RawSockaddrInet6.Scope_id", Field, 0}, - {"RawSockaddrLinklayer", Type, 0}, - {"RawSockaddrLinklayer.Addr", Field, 0}, - {"RawSockaddrLinklayer.Family", Field, 0}, - {"RawSockaddrLinklayer.Halen", Field, 0}, - {"RawSockaddrLinklayer.Hatype", Field, 0}, - {"RawSockaddrLinklayer.Ifindex", Field, 0}, - {"RawSockaddrLinklayer.Pkttype", Field, 0}, - {"RawSockaddrLinklayer.Protocol", Field, 0}, - {"RawSockaddrNetlink", Type, 0}, - {"RawSockaddrNetlink.Family", Field, 0}, - {"RawSockaddrNetlink.Groups", Field, 0}, - {"RawSockaddrNetlink.Pad", Field, 0}, - {"RawSockaddrNetlink.Pid", Field, 0}, - {"RawSockaddrUnix", Type, 0}, - {"RawSockaddrUnix.Family", Field, 0}, - {"RawSockaddrUnix.Len", Field, 0}, - {"RawSockaddrUnix.Pad_cgo_0", Field, 2}, - {"RawSockaddrUnix.Path", Field, 0}, - {"RawSyscall", Func, 0}, - {"RawSyscall6", Func, 0}, - {"Read", Func, 0}, - {"ReadConsole", Func, 1}, - {"ReadDirectoryChanges", Func, 0}, - {"ReadDirent", Func, 0}, - {"ReadFile", Func, 0}, - {"Readlink", Func, 0}, - {"Reboot", Func, 0}, - {"Recvfrom", Func, 0}, - {"Recvmsg", Func, 0}, - {"RegCloseKey", Func, 0}, - {"RegEnumKeyEx", Func, 0}, - {"RegOpenKeyEx", Func, 0}, - {"RegQueryInfoKey", Func, 0}, - {"RegQueryValueEx", Func, 0}, - {"RemoveDirectory", Func, 0}, - {"Removexattr", Func, 1}, - {"Rename", Func, 0}, - {"Renameat", Func, 0}, - {"Revoke", Func, 0}, - {"Rlimit", Type, 0}, - {"Rlimit.Cur", Field, 0}, - {"Rlimit.Max", Field, 0}, - {"Rmdir", Func, 0}, - {"RouteMessage", Type, 0}, - {"RouteMessage.Data", Field, 0}, - {"RouteMessage.Header", Field, 0}, - {"RouteRIB", Func, 0}, - {"RoutingMessage", Type, 0}, - {"RtAttr", Type, 0}, - {"RtAttr.Len", Field, 0}, - {"RtAttr.Type", Field, 0}, - {"RtGenmsg", Type, 0}, - {"RtGenmsg.Family", Field, 0}, - {"RtMetrics", Type, 0}, - {"RtMetrics.Expire", Field, 0}, - {"RtMetrics.Filler", Field, 0}, - {"RtMetrics.Hopcount", Field, 0}, - {"RtMetrics.Locks", Field, 0}, - {"RtMetrics.Mtu", Field, 0}, - {"RtMetrics.Pad", Field, 3}, - {"RtMetrics.Pksent", Field, 0}, - {"RtMetrics.Recvpipe", Field, 0}, - {"RtMetrics.Refcnt", Field, 2}, - {"RtMetrics.Rtt", Field, 0}, - {"RtMetrics.Rttvar", Field, 0}, - {"RtMetrics.Sendpipe", Field, 0}, - {"RtMetrics.Ssthresh", Field, 0}, - {"RtMetrics.Weight", Field, 0}, - {"RtMsg", Type, 0}, - {"RtMsg.Dst_len", Field, 0}, - {"RtMsg.Family", Field, 0}, - {"RtMsg.Flags", Field, 0}, - {"RtMsg.Protocol", Field, 0}, - {"RtMsg.Scope", Field, 0}, - {"RtMsg.Src_len", Field, 0}, - {"RtMsg.Table", Field, 0}, - {"RtMsg.Tos", Field, 0}, - {"RtMsg.Type", Field, 0}, - {"RtMsghdr", Type, 0}, - {"RtMsghdr.Addrs", Field, 0}, - {"RtMsghdr.Errno", Field, 0}, - {"RtMsghdr.Flags", Field, 0}, - {"RtMsghdr.Fmask", Field, 0}, - {"RtMsghdr.Hdrlen", Field, 2}, - {"RtMsghdr.Index", Field, 0}, - {"RtMsghdr.Inits", Field, 0}, - {"RtMsghdr.Mpls", Field, 2}, - {"RtMsghdr.Msglen", Field, 0}, - {"RtMsghdr.Pad_cgo_0", Field, 0}, - {"RtMsghdr.Pad_cgo_1", Field, 2}, - {"RtMsghdr.Pid", Field, 0}, - {"RtMsghdr.Priority", Field, 2}, - {"RtMsghdr.Rmx", Field, 0}, - {"RtMsghdr.Seq", Field, 0}, - {"RtMsghdr.Tableid", Field, 2}, - {"RtMsghdr.Type", Field, 0}, - {"RtMsghdr.Use", Field, 0}, - {"RtMsghdr.Version", Field, 0}, - {"RtNexthop", Type, 0}, - {"RtNexthop.Flags", Field, 0}, - {"RtNexthop.Hops", Field, 0}, - {"RtNexthop.Ifindex", Field, 0}, - {"RtNexthop.Len", Field, 0}, - {"Rusage", Type, 0}, - {"Rusage.CreationTime", Field, 0}, - {"Rusage.ExitTime", Field, 0}, - {"Rusage.Idrss", Field, 0}, - {"Rusage.Inblock", Field, 0}, - {"Rusage.Isrss", Field, 0}, - {"Rusage.Ixrss", Field, 0}, - {"Rusage.KernelTime", Field, 0}, - {"Rusage.Majflt", Field, 0}, - {"Rusage.Maxrss", Field, 0}, - {"Rusage.Minflt", Field, 0}, - {"Rusage.Msgrcv", Field, 0}, - {"Rusage.Msgsnd", Field, 0}, - {"Rusage.Nivcsw", Field, 0}, - {"Rusage.Nsignals", Field, 0}, - {"Rusage.Nswap", Field, 0}, - {"Rusage.Nvcsw", Field, 0}, - {"Rusage.Oublock", Field, 0}, - {"Rusage.Stime", Field, 0}, - {"Rusage.UserTime", Field, 0}, - {"Rusage.Utime", Field, 0}, - {"SCM_BINTIME", Const, 0}, - {"SCM_CREDENTIALS", Const, 0}, - {"SCM_CREDS", Const, 0}, - {"SCM_RIGHTS", Const, 0}, - {"SCM_TIMESTAMP", Const, 0}, - {"SCM_TIMESTAMPING", Const, 0}, - {"SCM_TIMESTAMPNS", Const, 0}, - {"SCM_TIMESTAMP_MONOTONIC", Const, 0}, - {"SHUT_RD", Const, 0}, - {"SHUT_RDWR", Const, 0}, - {"SHUT_WR", Const, 0}, - {"SID", Type, 0}, - {"SIDAndAttributes", Type, 0}, - {"SIDAndAttributes.Attributes", Field, 0}, - {"SIDAndAttributes.Sid", Field, 0}, - {"SIGABRT", Const, 0}, - {"SIGALRM", Const, 0}, - {"SIGBUS", Const, 0}, - {"SIGCHLD", Const, 0}, - {"SIGCLD", Const, 0}, - {"SIGCONT", Const, 0}, - {"SIGEMT", Const, 0}, - {"SIGFPE", Const, 0}, - {"SIGHUP", Const, 0}, - {"SIGILL", Const, 0}, - {"SIGINFO", Const, 0}, - {"SIGINT", Const, 0}, - {"SIGIO", Const, 0}, - {"SIGIOT", Const, 0}, - {"SIGKILL", Const, 0}, - {"SIGLIBRT", Const, 1}, - {"SIGLWP", Const, 0}, - {"SIGPIPE", Const, 0}, - {"SIGPOLL", Const, 0}, - {"SIGPROF", Const, 0}, - {"SIGPWR", Const, 0}, - {"SIGQUIT", Const, 0}, - {"SIGSEGV", Const, 0}, - {"SIGSTKFLT", Const, 0}, - {"SIGSTOP", Const, 0}, - {"SIGSYS", Const, 0}, - {"SIGTERM", Const, 0}, - {"SIGTHR", Const, 0}, - {"SIGTRAP", Const, 0}, - {"SIGTSTP", Const, 0}, - {"SIGTTIN", Const, 0}, - {"SIGTTOU", Const, 0}, - {"SIGUNUSED", Const, 0}, - {"SIGURG", Const, 0}, - {"SIGUSR1", Const, 0}, - {"SIGUSR2", Const, 0}, - {"SIGVTALRM", Const, 0}, - {"SIGWINCH", Const, 0}, - {"SIGXCPU", Const, 0}, - {"SIGXFSZ", Const, 0}, - {"SIOCADDDLCI", Const, 0}, - {"SIOCADDMULTI", Const, 0}, - {"SIOCADDRT", Const, 0}, - {"SIOCAIFADDR", Const, 0}, - {"SIOCAIFGROUP", Const, 0}, - {"SIOCALIFADDR", Const, 0}, - {"SIOCARPIPLL", Const, 0}, - {"SIOCATMARK", Const, 0}, - {"SIOCAUTOADDR", Const, 0}, - {"SIOCAUTONETMASK", Const, 0}, - {"SIOCBRDGADD", Const, 1}, - {"SIOCBRDGADDS", Const, 1}, - {"SIOCBRDGARL", Const, 1}, - {"SIOCBRDGDADDR", Const, 1}, - {"SIOCBRDGDEL", Const, 1}, - {"SIOCBRDGDELS", Const, 1}, - {"SIOCBRDGFLUSH", Const, 1}, - {"SIOCBRDGFRL", Const, 1}, - {"SIOCBRDGGCACHE", Const, 1}, - {"SIOCBRDGGFD", Const, 1}, - {"SIOCBRDGGHT", Const, 1}, - {"SIOCBRDGGIFFLGS", Const, 1}, - {"SIOCBRDGGMA", Const, 1}, - {"SIOCBRDGGPARAM", Const, 1}, - {"SIOCBRDGGPRI", Const, 1}, - {"SIOCBRDGGRL", Const, 1}, - {"SIOCBRDGGSIFS", Const, 1}, - {"SIOCBRDGGTO", Const, 1}, - {"SIOCBRDGIFS", Const, 1}, - {"SIOCBRDGRTS", Const, 1}, - {"SIOCBRDGSADDR", Const, 1}, - {"SIOCBRDGSCACHE", Const, 1}, - {"SIOCBRDGSFD", Const, 1}, - {"SIOCBRDGSHT", Const, 1}, - {"SIOCBRDGSIFCOST", Const, 1}, - {"SIOCBRDGSIFFLGS", Const, 1}, - {"SIOCBRDGSIFPRIO", Const, 1}, - {"SIOCBRDGSMA", Const, 1}, - {"SIOCBRDGSPRI", Const, 1}, - {"SIOCBRDGSPROTO", Const, 1}, - {"SIOCBRDGSTO", Const, 1}, - {"SIOCBRDGSTXHC", Const, 1}, - {"SIOCDARP", Const, 0}, - {"SIOCDELDLCI", Const, 0}, - {"SIOCDELMULTI", Const, 0}, - {"SIOCDELRT", Const, 0}, - {"SIOCDEVPRIVATE", Const, 0}, - {"SIOCDIFADDR", Const, 0}, - {"SIOCDIFGROUP", Const, 0}, - {"SIOCDIFPHYADDR", Const, 0}, - {"SIOCDLIFADDR", Const, 0}, - {"SIOCDRARP", Const, 0}, - {"SIOCGARP", Const, 0}, - {"SIOCGDRVSPEC", Const, 0}, - {"SIOCGETKALIVE", Const, 1}, - {"SIOCGETLABEL", Const, 1}, - {"SIOCGETPFLOW", Const, 1}, - {"SIOCGETPFSYNC", Const, 1}, - {"SIOCGETSGCNT", Const, 0}, - {"SIOCGETVIFCNT", Const, 0}, - {"SIOCGETVLAN", Const, 0}, - {"SIOCGHIWAT", Const, 0}, - {"SIOCGIFADDR", Const, 0}, - {"SIOCGIFADDRPREF", Const, 1}, - {"SIOCGIFALIAS", Const, 1}, - {"SIOCGIFALTMTU", Const, 0}, - {"SIOCGIFASYNCMAP", Const, 0}, - {"SIOCGIFBOND", Const, 0}, - {"SIOCGIFBR", Const, 0}, - {"SIOCGIFBRDADDR", Const, 0}, - {"SIOCGIFCAP", Const, 0}, - {"SIOCGIFCONF", Const, 0}, - {"SIOCGIFCOUNT", Const, 0}, - {"SIOCGIFDATA", Const, 1}, - {"SIOCGIFDESCR", Const, 0}, - {"SIOCGIFDEVMTU", Const, 0}, - {"SIOCGIFDLT", Const, 1}, - {"SIOCGIFDSTADDR", Const, 0}, - {"SIOCGIFENCAP", Const, 0}, - {"SIOCGIFFIB", Const, 1}, - {"SIOCGIFFLAGS", Const, 0}, - {"SIOCGIFGATTR", Const, 1}, - {"SIOCGIFGENERIC", Const, 0}, - {"SIOCGIFGMEMB", Const, 0}, - {"SIOCGIFGROUP", Const, 0}, - {"SIOCGIFHARDMTU", Const, 3}, - {"SIOCGIFHWADDR", Const, 0}, - {"SIOCGIFINDEX", Const, 0}, - {"SIOCGIFKPI", Const, 0}, - {"SIOCGIFMAC", Const, 0}, - {"SIOCGIFMAP", Const, 0}, - {"SIOCGIFMEDIA", Const, 0}, - {"SIOCGIFMEM", Const, 0}, - {"SIOCGIFMETRIC", Const, 0}, - {"SIOCGIFMTU", Const, 0}, - {"SIOCGIFNAME", Const, 0}, - {"SIOCGIFNETMASK", Const, 0}, - {"SIOCGIFPDSTADDR", Const, 0}, - {"SIOCGIFPFLAGS", Const, 0}, - {"SIOCGIFPHYS", Const, 0}, - {"SIOCGIFPRIORITY", Const, 1}, - {"SIOCGIFPSRCADDR", Const, 0}, - {"SIOCGIFRDOMAIN", Const, 1}, - {"SIOCGIFRTLABEL", Const, 1}, - {"SIOCGIFSLAVE", Const, 0}, - {"SIOCGIFSTATUS", Const, 0}, - {"SIOCGIFTIMESLOT", Const, 1}, - {"SIOCGIFTXQLEN", Const, 0}, - {"SIOCGIFVLAN", Const, 0}, - {"SIOCGIFWAKEFLAGS", Const, 0}, - {"SIOCGIFXFLAGS", Const, 1}, - {"SIOCGLIFADDR", Const, 0}, - {"SIOCGLIFPHYADDR", Const, 0}, - {"SIOCGLIFPHYRTABLE", Const, 1}, - {"SIOCGLIFPHYTTL", Const, 3}, - {"SIOCGLINKSTR", Const, 1}, - {"SIOCGLOWAT", Const, 0}, - {"SIOCGPGRP", Const, 0}, - {"SIOCGPRIVATE_0", Const, 0}, - {"SIOCGPRIVATE_1", Const, 0}, - {"SIOCGRARP", Const, 0}, - {"SIOCGSPPPPARAMS", Const, 3}, - {"SIOCGSTAMP", Const, 0}, - {"SIOCGSTAMPNS", Const, 0}, - {"SIOCGVH", Const, 1}, - {"SIOCGVNETID", Const, 3}, - {"SIOCIFCREATE", Const, 0}, - {"SIOCIFCREATE2", Const, 0}, - {"SIOCIFDESTROY", Const, 0}, - {"SIOCIFGCLONERS", Const, 0}, - {"SIOCINITIFADDR", Const, 1}, - {"SIOCPROTOPRIVATE", Const, 0}, - {"SIOCRSLVMULTI", Const, 0}, - {"SIOCRTMSG", Const, 0}, - {"SIOCSARP", Const, 0}, - {"SIOCSDRVSPEC", Const, 0}, - {"SIOCSETKALIVE", Const, 1}, - {"SIOCSETLABEL", Const, 1}, - {"SIOCSETPFLOW", Const, 1}, - {"SIOCSETPFSYNC", Const, 1}, - {"SIOCSETVLAN", Const, 0}, - {"SIOCSHIWAT", Const, 0}, - {"SIOCSIFADDR", Const, 0}, - {"SIOCSIFADDRPREF", Const, 1}, - {"SIOCSIFALTMTU", Const, 0}, - {"SIOCSIFASYNCMAP", Const, 0}, - {"SIOCSIFBOND", Const, 0}, - {"SIOCSIFBR", Const, 0}, - {"SIOCSIFBRDADDR", Const, 0}, - {"SIOCSIFCAP", Const, 0}, - {"SIOCSIFDESCR", Const, 0}, - {"SIOCSIFDSTADDR", Const, 0}, - {"SIOCSIFENCAP", Const, 0}, - {"SIOCSIFFIB", Const, 1}, - {"SIOCSIFFLAGS", Const, 0}, - {"SIOCSIFGATTR", Const, 1}, - {"SIOCSIFGENERIC", Const, 0}, - {"SIOCSIFHWADDR", Const, 0}, - {"SIOCSIFHWBROADCAST", Const, 0}, - {"SIOCSIFKPI", Const, 0}, - {"SIOCSIFLINK", Const, 0}, - {"SIOCSIFLLADDR", Const, 0}, - {"SIOCSIFMAC", Const, 0}, - {"SIOCSIFMAP", Const, 0}, - {"SIOCSIFMEDIA", Const, 0}, - {"SIOCSIFMEM", Const, 0}, - {"SIOCSIFMETRIC", Const, 0}, - {"SIOCSIFMTU", Const, 0}, - {"SIOCSIFNAME", Const, 0}, - {"SIOCSIFNETMASK", Const, 0}, - {"SIOCSIFPFLAGS", Const, 0}, - {"SIOCSIFPHYADDR", Const, 0}, - {"SIOCSIFPHYS", Const, 0}, - {"SIOCSIFPRIORITY", Const, 1}, - {"SIOCSIFRDOMAIN", Const, 1}, - {"SIOCSIFRTLABEL", Const, 1}, - {"SIOCSIFRVNET", Const, 0}, - {"SIOCSIFSLAVE", Const, 0}, - {"SIOCSIFTIMESLOT", Const, 1}, - {"SIOCSIFTXQLEN", Const, 0}, - {"SIOCSIFVLAN", Const, 0}, - {"SIOCSIFVNET", Const, 0}, - {"SIOCSIFXFLAGS", Const, 1}, - {"SIOCSLIFPHYADDR", Const, 0}, - {"SIOCSLIFPHYRTABLE", Const, 1}, - {"SIOCSLIFPHYTTL", Const, 3}, - {"SIOCSLINKSTR", Const, 1}, - {"SIOCSLOWAT", Const, 0}, - {"SIOCSPGRP", Const, 0}, - {"SIOCSRARP", Const, 0}, - {"SIOCSSPPPPARAMS", Const, 3}, - {"SIOCSVH", Const, 1}, - {"SIOCSVNETID", Const, 3}, - {"SIOCZIFDATA", Const, 1}, - {"SIO_GET_EXTENSION_FUNCTION_POINTER", Const, 1}, - {"SIO_GET_INTERFACE_LIST", Const, 0}, - {"SIO_KEEPALIVE_VALS", Const, 3}, - {"SIO_UDP_CONNRESET", Const, 4}, - {"SOCK_CLOEXEC", Const, 0}, - {"SOCK_DCCP", Const, 0}, - {"SOCK_DGRAM", Const, 0}, - {"SOCK_FLAGS_MASK", Const, 1}, - {"SOCK_MAXADDRLEN", Const, 0}, - {"SOCK_NONBLOCK", Const, 0}, - {"SOCK_NOSIGPIPE", Const, 1}, - {"SOCK_PACKET", Const, 0}, - {"SOCK_RAW", Const, 0}, - {"SOCK_RDM", Const, 0}, - {"SOCK_SEQPACKET", Const, 0}, - {"SOCK_STREAM", Const, 0}, - {"SOL_AAL", Const, 0}, - {"SOL_ATM", Const, 0}, - {"SOL_DECNET", Const, 0}, - {"SOL_ICMPV6", Const, 0}, - {"SOL_IP", Const, 0}, - {"SOL_IPV6", Const, 0}, - {"SOL_IRDA", Const, 0}, - {"SOL_PACKET", Const, 0}, - {"SOL_RAW", Const, 0}, - {"SOL_SOCKET", Const, 0}, - {"SOL_TCP", Const, 0}, - {"SOL_X25", Const, 0}, - {"SOMAXCONN", Const, 0}, - {"SO_ACCEPTCONN", Const, 0}, - {"SO_ACCEPTFILTER", Const, 0}, - {"SO_ATTACH_FILTER", Const, 0}, - {"SO_BINDANY", Const, 1}, - {"SO_BINDTODEVICE", Const, 0}, - {"SO_BINTIME", Const, 0}, - {"SO_BROADCAST", Const, 0}, - {"SO_BSDCOMPAT", Const, 0}, - {"SO_DEBUG", Const, 0}, - {"SO_DETACH_FILTER", Const, 0}, - {"SO_DOMAIN", Const, 0}, - {"SO_DONTROUTE", Const, 0}, - {"SO_DONTTRUNC", Const, 0}, - {"SO_ERROR", Const, 0}, - {"SO_KEEPALIVE", Const, 0}, - {"SO_LABEL", Const, 0}, - {"SO_LINGER", Const, 0}, - {"SO_LINGER_SEC", Const, 0}, - {"SO_LISTENINCQLEN", Const, 0}, - {"SO_LISTENQLEN", Const, 0}, - {"SO_LISTENQLIMIT", Const, 0}, - {"SO_MARK", Const, 0}, - {"SO_NETPROC", Const, 1}, - {"SO_NKE", Const, 0}, - {"SO_NOADDRERR", Const, 0}, - {"SO_NOHEADER", Const, 1}, - {"SO_NOSIGPIPE", Const, 0}, - {"SO_NOTIFYCONFLICT", Const, 0}, - {"SO_NO_CHECK", Const, 0}, - {"SO_NO_DDP", Const, 0}, - {"SO_NO_OFFLOAD", Const, 0}, - {"SO_NP_EXTENSIONS", Const, 0}, - {"SO_NREAD", Const, 0}, - {"SO_NUMRCVPKT", Const, 16}, - {"SO_NWRITE", Const, 0}, - {"SO_OOBINLINE", Const, 0}, - {"SO_OVERFLOWED", Const, 1}, - {"SO_PASSCRED", Const, 0}, - {"SO_PASSSEC", Const, 0}, - {"SO_PEERCRED", Const, 0}, - {"SO_PEERLABEL", Const, 0}, - {"SO_PEERNAME", Const, 0}, - {"SO_PEERSEC", Const, 0}, - {"SO_PRIORITY", Const, 0}, - {"SO_PROTOCOL", Const, 0}, - {"SO_PROTOTYPE", Const, 1}, - {"SO_RANDOMPORT", Const, 0}, - {"SO_RCVBUF", Const, 0}, - {"SO_RCVBUFFORCE", Const, 0}, - {"SO_RCVLOWAT", Const, 0}, - {"SO_RCVTIMEO", Const, 0}, - {"SO_RESTRICTIONS", Const, 0}, - {"SO_RESTRICT_DENYIN", Const, 0}, - {"SO_RESTRICT_DENYOUT", Const, 0}, - {"SO_RESTRICT_DENYSET", Const, 0}, - {"SO_REUSEADDR", Const, 0}, - {"SO_REUSEPORT", Const, 0}, - {"SO_REUSESHAREUID", Const, 0}, - {"SO_RTABLE", Const, 1}, - {"SO_RXQ_OVFL", Const, 0}, - {"SO_SECURITY_AUTHENTICATION", Const, 0}, - {"SO_SECURITY_ENCRYPTION_NETWORK", Const, 0}, - {"SO_SECURITY_ENCRYPTION_TRANSPORT", Const, 0}, - {"SO_SETFIB", Const, 0}, - {"SO_SNDBUF", Const, 0}, - {"SO_SNDBUFFORCE", Const, 0}, - {"SO_SNDLOWAT", Const, 0}, - {"SO_SNDTIMEO", Const, 0}, - {"SO_SPLICE", Const, 1}, - {"SO_TIMESTAMP", Const, 0}, - {"SO_TIMESTAMPING", Const, 0}, - {"SO_TIMESTAMPNS", Const, 0}, - {"SO_TIMESTAMP_MONOTONIC", Const, 0}, - {"SO_TYPE", Const, 0}, - {"SO_UPCALLCLOSEWAIT", Const, 0}, - {"SO_UPDATE_ACCEPT_CONTEXT", Const, 0}, - {"SO_UPDATE_CONNECT_CONTEXT", Const, 1}, - {"SO_USELOOPBACK", Const, 0}, - {"SO_USER_COOKIE", Const, 1}, - {"SO_VENDOR", Const, 3}, - {"SO_WANTMORE", Const, 0}, - {"SO_WANTOOBFLAG", Const, 0}, - {"SSLExtraCertChainPolicyPara", Type, 0}, - {"SSLExtraCertChainPolicyPara.AuthType", Field, 0}, - {"SSLExtraCertChainPolicyPara.Checks", Field, 0}, - {"SSLExtraCertChainPolicyPara.ServerName", Field, 0}, - {"SSLExtraCertChainPolicyPara.Size", Field, 0}, - {"STANDARD_RIGHTS_ALL", Const, 0}, - {"STANDARD_RIGHTS_EXECUTE", Const, 0}, - {"STANDARD_RIGHTS_READ", Const, 0}, - {"STANDARD_RIGHTS_REQUIRED", Const, 0}, - {"STANDARD_RIGHTS_WRITE", Const, 0}, - {"STARTF_USESHOWWINDOW", Const, 0}, - {"STARTF_USESTDHANDLES", Const, 0}, - {"STD_ERROR_HANDLE", Const, 0}, - {"STD_INPUT_HANDLE", Const, 0}, - {"STD_OUTPUT_HANDLE", Const, 0}, - {"SUBLANG_ENGLISH_US", Const, 0}, - {"SW_FORCEMINIMIZE", Const, 0}, - {"SW_HIDE", Const, 0}, - {"SW_MAXIMIZE", Const, 0}, - {"SW_MINIMIZE", Const, 0}, - {"SW_NORMAL", Const, 0}, - {"SW_RESTORE", Const, 0}, - {"SW_SHOW", Const, 0}, - {"SW_SHOWDEFAULT", Const, 0}, - {"SW_SHOWMAXIMIZED", Const, 0}, - {"SW_SHOWMINIMIZED", Const, 0}, - {"SW_SHOWMINNOACTIVE", Const, 0}, - {"SW_SHOWNA", Const, 0}, - {"SW_SHOWNOACTIVATE", Const, 0}, - {"SW_SHOWNORMAL", Const, 0}, - {"SYMBOLIC_LINK_FLAG_DIRECTORY", Const, 4}, - {"SYNCHRONIZE", Const, 0}, - {"SYSCTL_VERSION", Const, 1}, - {"SYSCTL_VERS_0", Const, 1}, - {"SYSCTL_VERS_1", Const, 1}, - {"SYSCTL_VERS_MASK", Const, 1}, - {"SYS_ABORT2", Const, 0}, - {"SYS_ACCEPT", Const, 0}, - {"SYS_ACCEPT4", Const, 0}, - {"SYS_ACCEPT_NOCANCEL", Const, 0}, - {"SYS_ACCESS", Const, 0}, - {"SYS_ACCESS_EXTENDED", Const, 0}, - {"SYS_ACCT", Const, 0}, - {"SYS_ADD_KEY", Const, 0}, - {"SYS_ADD_PROFIL", Const, 0}, - {"SYS_ADJFREQ", Const, 1}, - {"SYS_ADJTIME", Const, 0}, - {"SYS_ADJTIMEX", Const, 0}, - {"SYS_AFS_SYSCALL", Const, 0}, - {"SYS_AIO_CANCEL", Const, 0}, - {"SYS_AIO_ERROR", Const, 0}, - {"SYS_AIO_FSYNC", Const, 0}, - {"SYS_AIO_MLOCK", Const, 14}, - {"SYS_AIO_READ", Const, 0}, - {"SYS_AIO_RETURN", Const, 0}, - {"SYS_AIO_SUSPEND", Const, 0}, - {"SYS_AIO_SUSPEND_NOCANCEL", Const, 0}, - {"SYS_AIO_WAITCOMPLETE", Const, 14}, - {"SYS_AIO_WRITE", Const, 0}, - {"SYS_ALARM", Const, 0}, - {"SYS_ARCH_PRCTL", Const, 0}, - {"SYS_ARM_FADVISE64_64", Const, 0}, - {"SYS_ARM_SYNC_FILE_RANGE", Const, 0}, - {"SYS_ATGETMSG", Const, 0}, - {"SYS_ATPGETREQ", Const, 0}, - {"SYS_ATPGETRSP", Const, 0}, - {"SYS_ATPSNDREQ", Const, 0}, - {"SYS_ATPSNDRSP", Const, 0}, - {"SYS_ATPUTMSG", Const, 0}, - {"SYS_ATSOCKET", Const, 0}, - {"SYS_AUDIT", Const, 0}, - {"SYS_AUDITCTL", Const, 0}, - {"SYS_AUDITON", Const, 0}, - {"SYS_AUDIT_SESSION_JOIN", Const, 0}, - {"SYS_AUDIT_SESSION_PORT", Const, 0}, - {"SYS_AUDIT_SESSION_SELF", Const, 0}, - {"SYS_BDFLUSH", Const, 0}, - {"SYS_BIND", Const, 0}, - {"SYS_BINDAT", Const, 3}, - {"SYS_BREAK", Const, 0}, - {"SYS_BRK", Const, 0}, - {"SYS_BSDTHREAD_CREATE", Const, 0}, - {"SYS_BSDTHREAD_REGISTER", Const, 0}, - {"SYS_BSDTHREAD_TERMINATE", Const, 0}, - {"SYS_CAPGET", Const, 0}, - {"SYS_CAPSET", Const, 0}, - {"SYS_CAP_ENTER", Const, 0}, - {"SYS_CAP_FCNTLS_GET", Const, 1}, - {"SYS_CAP_FCNTLS_LIMIT", Const, 1}, - {"SYS_CAP_GETMODE", Const, 0}, - {"SYS_CAP_GETRIGHTS", Const, 0}, - {"SYS_CAP_IOCTLS_GET", Const, 1}, - {"SYS_CAP_IOCTLS_LIMIT", Const, 1}, - {"SYS_CAP_NEW", Const, 0}, - {"SYS_CAP_RIGHTS_GET", Const, 1}, - {"SYS_CAP_RIGHTS_LIMIT", Const, 1}, - {"SYS_CHDIR", Const, 0}, - {"SYS_CHFLAGS", Const, 0}, - {"SYS_CHFLAGSAT", Const, 3}, - {"SYS_CHMOD", Const, 0}, - {"SYS_CHMOD_EXTENDED", Const, 0}, - {"SYS_CHOWN", Const, 0}, - {"SYS_CHOWN32", Const, 0}, - {"SYS_CHROOT", Const, 0}, - {"SYS_CHUD", Const, 0}, - {"SYS_CLOCK_ADJTIME", Const, 0}, - {"SYS_CLOCK_GETCPUCLOCKID2", Const, 1}, - {"SYS_CLOCK_GETRES", Const, 0}, - {"SYS_CLOCK_GETTIME", Const, 0}, - {"SYS_CLOCK_NANOSLEEP", Const, 0}, - {"SYS_CLOCK_SETTIME", Const, 0}, - {"SYS_CLONE", Const, 0}, - {"SYS_CLOSE", Const, 0}, - {"SYS_CLOSEFROM", Const, 0}, - {"SYS_CLOSE_NOCANCEL", Const, 0}, - {"SYS_CONNECT", Const, 0}, - {"SYS_CONNECTAT", Const, 3}, - {"SYS_CONNECT_NOCANCEL", Const, 0}, - {"SYS_COPYFILE", Const, 0}, - {"SYS_CPUSET", Const, 0}, - {"SYS_CPUSET_GETAFFINITY", Const, 0}, - {"SYS_CPUSET_GETID", Const, 0}, - {"SYS_CPUSET_SETAFFINITY", Const, 0}, - {"SYS_CPUSET_SETID", Const, 0}, - {"SYS_CREAT", Const, 0}, - {"SYS_CREATE_MODULE", Const, 0}, - {"SYS_CSOPS", Const, 0}, - {"SYS_CSOPS_AUDITTOKEN", Const, 16}, - {"SYS_DELETE", Const, 0}, - {"SYS_DELETE_MODULE", Const, 0}, - {"SYS_DUP", Const, 0}, - {"SYS_DUP2", Const, 0}, - {"SYS_DUP3", Const, 0}, - {"SYS_EACCESS", Const, 0}, - {"SYS_EPOLL_CREATE", Const, 0}, - {"SYS_EPOLL_CREATE1", Const, 0}, - {"SYS_EPOLL_CTL", Const, 0}, - {"SYS_EPOLL_CTL_OLD", Const, 0}, - {"SYS_EPOLL_PWAIT", Const, 0}, - {"SYS_EPOLL_WAIT", Const, 0}, - {"SYS_EPOLL_WAIT_OLD", Const, 0}, - {"SYS_EVENTFD", Const, 0}, - {"SYS_EVENTFD2", Const, 0}, - {"SYS_EXCHANGEDATA", Const, 0}, - {"SYS_EXECVE", Const, 0}, - {"SYS_EXIT", Const, 0}, - {"SYS_EXIT_GROUP", Const, 0}, - {"SYS_EXTATTRCTL", Const, 0}, - {"SYS_EXTATTR_DELETE_FD", Const, 0}, - {"SYS_EXTATTR_DELETE_FILE", Const, 0}, - {"SYS_EXTATTR_DELETE_LINK", Const, 0}, - {"SYS_EXTATTR_GET_FD", Const, 0}, - {"SYS_EXTATTR_GET_FILE", Const, 0}, - {"SYS_EXTATTR_GET_LINK", Const, 0}, - {"SYS_EXTATTR_LIST_FD", Const, 0}, - {"SYS_EXTATTR_LIST_FILE", Const, 0}, - {"SYS_EXTATTR_LIST_LINK", Const, 0}, - {"SYS_EXTATTR_SET_FD", Const, 0}, - {"SYS_EXTATTR_SET_FILE", Const, 0}, - {"SYS_EXTATTR_SET_LINK", Const, 0}, - {"SYS_FACCESSAT", Const, 0}, - {"SYS_FADVISE64", Const, 0}, - {"SYS_FADVISE64_64", Const, 0}, - {"SYS_FALLOCATE", Const, 0}, - {"SYS_FANOTIFY_INIT", Const, 0}, - {"SYS_FANOTIFY_MARK", Const, 0}, - {"SYS_FCHDIR", Const, 0}, - {"SYS_FCHFLAGS", Const, 0}, - {"SYS_FCHMOD", Const, 0}, - {"SYS_FCHMODAT", Const, 0}, - {"SYS_FCHMOD_EXTENDED", Const, 0}, - {"SYS_FCHOWN", Const, 0}, - {"SYS_FCHOWN32", Const, 0}, - {"SYS_FCHOWNAT", Const, 0}, - {"SYS_FCHROOT", Const, 1}, - {"SYS_FCNTL", Const, 0}, - {"SYS_FCNTL64", Const, 0}, - {"SYS_FCNTL_NOCANCEL", Const, 0}, - {"SYS_FDATASYNC", Const, 0}, - {"SYS_FEXECVE", Const, 0}, - {"SYS_FFCLOCK_GETCOUNTER", Const, 0}, - {"SYS_FFCLOCK_GETESTIMATE", Const, 0}, - {"SYS_FFCLOCK_SETESTIMATE", Const, 0}, - {"SYS_FFSCTL", Const, 0}, - {"SYS_FGETATTRLIST", Const, 0}, - {"SYS_FGETXATTR", Const, 0}, - {"SYS_FHOPEN", Const, 0}, - {"SYS_FHSTAT", Const, 0}, - {"SYS_FHSTATFS", Const, 0}, - {"SYS_FILEPORT_MAKEFD", Const, 0}, - {"SYS_FILEPORT_MAKEPORT", Const, 0}, - {"SYS_FKTRACE", Const, 1}, - {"SYS_FLISTXATTR", Const, 0}, - {"SYS_FLOCK", Const, 0}, - {"SYS_FORK", Const, 0}, - {"SYS_FPATHCONF", Const, 0}, - {"SYS_FREEBSD6_FTRUNCATE", Const, 0}, - {"SYS_FREEBSD6_LSEEK", Const, 0}, - {"SYS_FREEBSD6_MMAP", Const, 0}, - {"SYS_FREEBSD6_PREAD", Const, 0}, - {"SYS_FREEBSD6_PWRITE", Const, 0}, - {"SYS_FREEBSD6_TRUNCATE", Const, 0}, - {"SYS_FREMOVEXATTR", Const, 0}, - {"SYS_FSCTL", Const, 0}, - {"SYS_FSETATTRLIST", Const, 0}, - {"SYS_FSETXATTR", Const, 0}, - {"SYS_FSGETPATH", Const, 0}, - {"SYS_FSTAT", Const, 0}, - {"SYS_FSTAT64", Const, 0}, - {"SYS_FSTAT64_EXTENDED", Const, 0}, - {"SYS_FSTATAT", Const, 0}, - {"SYS_FSTATAT64", Const, 0}, - {"SYS_FSTATFS", Const, 0}, - {"SYS_FSTATFS64", Const, 0}, - {"SYS_FSTATV", Const, 0}, - {"SYS_FSTATVFS1", Const, 1}, - {"SYS_FSTAT_EXTENDED", Const, 0}, - {"SYS_FSYNC", Const, 0}, - {"SYS_FSYNC_NOCANCEL", Const, 0}, - {"SYS_FSYNC_RANGE", Const, 1}, - {"SYS_FTIME", Const, 0}, - {"SYS_FTRUNCATE", Const, 0}, - {"SYS_FTRUNCATE64", Const, 0}, - {"SYS_FUTEX", Const, 0}, - {"SYS_FUTIMENS", Const, 1}, - {"SYS_FUTIMES", Const, 0}, - {"SYS_FUTIMESAT", Const, 0}, - {"SYS_GETATTRLIST", Const, 0}, - {"SYS_GETAUDIT", Const, 0}, - {"SYS_GETAUDIT_ADDR", Const, 0}, - {"SYS_GETAUID", Const, 0}, - {"SYS_GETCONTEXT", Const, 0}, - {"SYS_GETCPU", Const, 0}, - {"SYS_GETCWD", Const, 0}, - {"SYS_GETDENTS", Const, 0}, - {"SYS_GETDENTS64", Const, 0}, - {"SYS_GETDIRENTRIES", Const, 0}, - {"SYS_GETDIRENTRIES64", Const, 0}, - {"SYS_GETDIRENTRIESATTR", Const, 0}, - {"SYS_GETDTABLECOUNT", Const, 1}, - {"SYS_GETDTABLESIZE", Const, 0}, - {"SYS_GETEGID", Const, 0}, - {"SYS_GETEGID32", Const, 0}, - {"SYS_GETEUID", Const, 0}, - {"SYS_GETEUID32", Const, 0}, - {"SYS_GETFH", Const, 0}, - {"SYS_GETFSSTAT", Const, 0}, - {"SYS_GETFSSTAT64", Const, 0}, - {"SYS_GETGID", Const, 0}, - {"SYS_GETGID32", Const, 0}, - {"SYS_GETGROUPS", Const, 0}, - {"SYS_GETGROUPS32", Const, 0}, - {"SYS_GETHOSTUUID", Const, 0}, - {"SYS_GETITIMER", Const, 0}, - {"SYS_GETLCID", Const, 0}, - {"SYS_GETLOGIN", Const, 0}, - {"SYS_GETLOGINCLASS", Const, 0}, - {"SYS_GETPEERNAME", Const, 0}, - {"SYS_GETPGID", Const, 0}, - {"SYS_GETPGRP", Const, 0}, - {"SYS_GETPID", Const, 0}, - {"SYS_GETPMSG", Const, 0}, - {"SYS_GETPPID", Const, 0}, - {"SYS_GETPRIORITY", Const, 0}, - {"SYS_GETRESGID", Const, 0}, - {"SYS_GETRESGID32", Const, 0}, - {"SYS_GETRESUID", Const, 0}, - {"SYS_GETRESUID32", Const, 0}, - {"SYS_GETRLIMIT", Const, 0}, - {"SYS_GETRTABLE", Const, 1}, - {"SYS_GETRUSAGE", Const, 0}, - {"SYS_GETSGROUPS", Const, 0}, - {"SYS_GETSID", Const, 0}, - {"SYS_GETSOCKNAME", Const, 0}, - {"SYS_GETSOCKOPT", Const, 0}, - {"SYS_GETTHRID", Const, 1}, - {"SYS_GETTID", Const, 0}, - {"SYS_GETTIMEOFDAY", Const, 0}, - {"SYS_GETUID", Const, 0}, - {"SYS_GETUID32", Const, 0}, - {"SYS_GETVFSSTAT", Const, 1}, - {"SYS_GETWGROUPS", Const, 0}, - {"SYS_GETXATTR", Const, 0}, - {"SYS_GET_KERNEL_SYMS", Const, 0}, - {"SYS_GET_MEMPOLICY", Const, 0}, - {"SYS_GET_ROBUST_LIST", Const, 0}, - {"SYS_GET_THREAD_AREA", Const, 0}, - {"SYS_GSSD_SYSCALL", Const, 14}, - {"SYS_GTTY", Const, 0}, - {"SYS_IDENTITYSVC", Const, 0}, - {"SYS_IDLE", Const, 0}, - {"SYS_INITGROUPS", Const, 0}, - {"SYS_INIT_MODULE", Const, 0}, - {"SYS_INOTIFY_ADD_WATCH", Const, 0}, - {"SYS_INOTIFY_INIT", Const, 0}, - {"SYS_INOTIFY_INIT1", Const, 0}, - {"SYS_INOTIFY_RM_WATCH", Const, 0}, - {"SYS_IOCTL", Const, 0}, - {"SYS_IOPERM", Const, 0}, - {"SYS_IOPL", Const, 0}, - {"SYS_IOPOLICYSYS", Const, 0}, - {"SYS_IOPRIO_GET", Const, 0}, - {"SYS_IOPRIO_SET", Const, 0}, - {"SYS_IO_CANCEL", Const, 0}, - {"SYS_IO_DESTROY", Const, 0}, - {"SYS_IO_GETEVENTS", Const, 0}, - {"SYS_IO_SETUP", Const, 0}, - {"SYS_IO_SUBMIT", Const, 0}, - {"SYS_IPC", Const, 0}, - {"SYS_ISSETUGID", Const, 0}, - {"SYS_JAIL", Const, 0}, - {"SYS_JAIL_ATTACH", Const, 0}, - {"SYS_JAIL_GET", Const, 0}, - {"SYS_JAIL_REMOVE", Const, 0}, - {"SYS_JAIL_SET", Const, 0}, - {"SYS_KAS_INFO", Const, 16}, - {"SYS_KDEBUG_TRACE", Const, 0}, - {"SYS_KENV", Const, 0}, - {"SYS_KEVENT", Const, 0}, - {"SYS_KEVENT64", Const, 0}, - {"SYS_KEXEC_LOAD", Const, 0}, - {"SYS_KEYCTL", Const, 0}, - {"SYS_KILL", Const, 0}, - {"SYS_KLDFIND", Const, 0}, - {"SYS_KLDFIRSTMOD", Const, 0}, - {"SYS_KLDLOAD", Const, 0}, - {"SYS_KLDNEXT", Const, 0}, - {"SYS_KLDSTAT", Const, 0}, - {"SYS_KLDSYM", Const, 0}, - {"SYS_KLDUNLOAD", Const, 0}, - {"SYS_KLDUNLOADF", Const, 0}, - {"SYS_KMQ_NOTIFY", Const, 14}, - {"SYS_KMQ_OPEN", Const, 14}, - {"SYS_KMQ_SETATTR", Const, 14}, - {"SYS_KMQ_TIMEDRECEIVE", Const, 14}, - {"SYS_KMQ_TIMEDSEND", Const, 14}, - {"SYS_KMQ_UNLINK", Const, 14}, - {"SYS_KQUEUE", Const, 0}, - {"SYS_KQUEUE1", Const, 1}, - {"SYS_KSEM_CLOSE", Const, 14}, - {"SYS_KSEM_DESTROY", Const, 14}, - {"SYS_KSEM_GETVALUE", Const, 14}, - {"SYS_KSEM_INIT", Const, 14}, - {"SYS_KSEM_OPEN", Const, 14}, - {"SYS_KSEM_POST", Const, 14}, - {"SYS_KSEM_TIMEDWAIT", Const, 14}, - {"SYS_KSEM_TRYWAIT", Const, 14}, - {"SYS_KSEM_UNLINK", Const, 14}, - {"SYS_KSEM_WAIT", Const, 14}, - {"SYS_KTIMER_CREATE", Const, 0}, - {"SYS_KTIMER_DELETE", Const, 0}, - {"SYS_KTIMER_GETOVERRUN", Const, 0}, - {"SYS_KTIMER_GETTIME", Const, 0}, - {"SYS_KTIMER_SETTIME", Const, 0}, - {"SYS_KTRACE", Const, 0}, - {"SYS_LCHFLAGS", Const, 0}, - {"SYS_LCHMOD", Const, 0}, - {"SYS_LCHOWN", Const, 0}, - {"SYS_LCHOWN32", Const, 0}, - {"SYS_LEDGER", Const, 16}, - {"SYS_LGETFH", Const, 0}, - {"SYS_LGETXATTR", Const, 0}, - {"SYS_LINK", Const, 0}, - {"SYS_LINKAT", Const, 0}, - {"SYS_LIO_LISTIO", Const, 0}, - {"SYS_LISTEN", Const, 0}, - {"SYS_LISTXATTR", Const, 0}, - {"SYS_LLISTXATTR", Const, 0}, - {"SYS_LOCK", Const, 0}, - {"SYS_LOOKUP_DCOOKIE", Const, 0}, - {"SYS_LPATHCONF", Const, 0}, - {"SYS_LREMOVEXATTR", Const, 0}, - {"SYS_LSEEK", Const, 0}, - {"SYS_LSETXATTR", Const, 0}, - {"SYS_LSTAT", Const, 0}, - {"SYS_LSTAT64", Const, 0}, - {"SYS_LSTAT64_EXTENDED", Const, 0}, - {"SYS_LSTATV", Const, 0}, - {"SYS_LSTAT_EXTENDED", Const, 0}, - {"SYS_LUTIMES", Const, 0}, - {"SYS_MAC_SYSCALL", Const, 0}, - {"SYS_MADVISE", Const, 0}, - {"SYS_MADVISE1", Const, 0}, - {"SYS_MAXSYSCALL", Const, 0}, - {"SYS_MBIND", Const, 0}, - {"SYS_MIGRATE_PAGES", Const, 0}, - {"SYS_MINCORE", Const, 0}, - {"SYS_MINHERIT", Const, 0}, - {"SYS_MKCOMPLEX", Const, 0}, - {"SYS_MKDIR", Const, 0}, - {"SYS_MKDIRAT", Const, 0}, - {"SYS_MKDIR_EXTENDED", Const, 0}, - {"SYS_MKFIFO", Const, 0}, - {"SYS_MKFIFOAT", Const, 0}, - {"SYS_MKFIFO_EXTENDED", Const, 0}, - {"SYS_MKNOD", Const, 0}, - {"SYS_MKNODAT", Const, 0}, - {"SYS_MLOCK", Const, 0}, - {"SYS_MLOCKALL", Const, 0}, - {"SYS_MMAP", Const, 0}, - {"SYS_MMAP2", Const, 0}, - {"SYS_MODCTL", Const, 1}, - {"SYS_MODFIND", Const, 0}, - {"SYS_MODFNEXT", Const, 0}, - {"SYS_MODIFY_LDT", Const, 0}, - {"SYS_MODNEXT", Const, 0}, - {"SYS_MODSTAT", Const, 0}, - {"SYS_MODWATCH", Const, 0}, - {"SYS_MOUNT", Const, 0}, - {"SYS_MOVE_PAGES", Const, 0}, - {"SYS_MPROTECT", Const, 0}, - {"SYS_MPX", Const, 0}, - {"SYS_MQUERY", Const, 1}, - {"SYS_MQ_GETSETATTR", Const, 0}, - {"SYS_MQ_NOTIFY", Const, 0}, - {"SYS_MQ_OPEN", Const, 0}, - {"SYS_MQ_TIMEDRECEIVE", Const, 0}, - {"SYS_MQ_TIMEDSEND", Const, 0}, - {"SYS_MQ_UNLINK", Const, 0}, - {"SYS_MREMAP", Const, 0}, - {"SYS_MSGCTL", Const, 0}, - {"SYS_MSGGET", Const, 0}, - {"SYS_MSGRCV", Const, 0}, - {"SYS_MSGRCV_NOCANCEL", Const, 0}, - {"SYS_MSGSND", Const, 0}, - {"SYS_MSGSND_NOCANCEL", Const, 0}, - {"SYS_MSGSYS", Const, 0}, - {"SYS_MSYNC", Const, 0}, - {"SYS_MSYNC_NOCANCEL", Const, 0}, - {"SYS_MUNLOCK", Const, 0}, - {"SYS_MUNLOCKALL", Const, 0}, - {"SYS_MUNMAP", Const, 0}, - {"SYS_NAME_TO_HANDLE_AT", Const, 0}, - {"SYS_NANOSLEEP", Const, 0}, - {"SYS_NEWFSTATAT", Const, 0}, - {"SYS_NFSCLNT", Const, 0}, - {"SYS_NFSSERVCTL", Const, 0}, - {"SYS_NFSSVC", Const, 0}, - {"SYS_NFSTAT", Const, 0}, - {"SYS_NICE", Const, 0}, - {"SYS_NLM_SYSCALL", Const, 14}, - {"SYS_NLSTAT", Const, 0}, - {"SYS_NMOUNT", Const, 0}, - {"SYS_NSTAT", Const, 0}, - {"SYS_NTP_ADJTIME", Const, 0}, - {"SYS_NTP_GETTIME", Const, 0}, - {"SYS_NUMA_GETAFFINITY", Const, 14}, - {"SYS_NUMA_SETAFFINITY", Const, 14}, - {"SYS_OABI_SYSCALL_BASE", Const, 0}, - {"SYS_OBREAK", Const, 0}, - {"SYS_OLDFSTAT", Const, 0}, - {"SYS_OLDLSTAT", Const, 0}, - {"SYS_OLDOLDUNAME", Const, 0}, - {"SYS_OLDSTAT", Const, 0}, - {"SYS_OLDUNAME", Const, 0}, - {"SYS_OPEN", Const, 0}, - {"SYS_OPENAT", Const, 0}, - {"SYS_OPENBSD_POLL", Const, 0}, - {"SYS_OPEN_BY_HANDLE_AT", Const, 0}, - {"SYS_OPEN_DPROTECTED_NP", Const, 16}, - {"SYS_OPEN_EXTENDED", Const, 0}, - {"SYS_OPEN_NOCANCEL", Const, 0}, - {"SYS_OVADVISE", Const, 0}, - {"SYS_PACCEPT", Const, 1}, - {"SYS_PATHCONF", Const, 0}, - {"SYS_PAUSE", Const, 0}, - {"SYS_PCICONFIG_IOBASE", Const, 0}, - {"SYS_PCICONFIG_READ", Const, 0}, - {"SYS_PCICONFIG_WRITE", Const, 0}, - {"SYS_PDFORK", Const, 0}, - {"SYS_PDGETPID", Const, 0}, - {"SYS_PDKILL", Const, 0}, - {"SYS_PERF_EVENT_OPEN", Const, 0}, - {"SYS_PERSONALITY", Const, 0}, - {"SYS_PID_HIBERNATE", Const, 0}, - {"SYS_PID_RESUME", Const, 0}, - {"SYS_PID_SHUTDOWN_SOCKETS", Const, 0}, - {"SYS_PID_SUSPEND", Const, 0}, - {"SYS_PIPE", Const, 0}, - {"SYS_PIPE2", Const, 0}, - {"SYS_PIVOT_ROOT", Const, 0}, - {"SYS_PMC_CONTROL", Const, 1}, - {"SYS_PMC_GET_INFO", Const, 1}, - {"SYS_POLL", Const, 0}, - {"SYS_POLLTS", Const, 1}, - {"SYS_POLL_NOCANCEL", Const, 0}, - {"SYS_POSIX_FADVISE", Const, 0}, - {"SYS_POSIX_FALLOCATE", Const, 0}, - {"SYS_POSIX_OPENPT", Const, 0}, - {"SYS_POSIX_SPAWN", Const, 0}, - {"SYS_PPOLL", Const, 0}, - {"SYS_PRCTL", Const, 0}, - {"SYS_PREAD", Const, 0}, - {"SYS_PREAD64", Const, 0}, - {"SYS_PREADV", Const, 0}, - {"SYS_PREAD_NOCANCEL", Const, 0}, - {"SYS_PRLIMIT64", Const, 0}, - {"SYS_PROCCTL", Const, 3}, - {"SYS_PROCESS_POLICY", Const, 0}, - {"SYS_PROCESS_VM_READV", Const, 0}, - {"SYS_PROCESS_VM_WRITEV", Const, 0}, - {"SYS_PROC_INFO", Const, 0}, - {"SYS_PROF", Const, 0}, - {"SYS_PROFIL", Const, 0}, - {"SYS_PSELECT", Const, 0}, - {"SYS_PSELECT6", Const, 0}, - {"SYS_PSET_ASSIGN", Const, 1}, - {"SYS_PSET_CREATE", Const, 1}, - {"SYS_PSET_DESTROY", Const, 1}, - {"SYS_PSYNCH_CVBROAD", Const, 0}, - {"SYS_PSYNCH_CVCLRPREPOST", Const, 0}, - {"SYS_PSYNCH_CVSIGNAL", Const, 0}, - {"SYS_PSYNCH_CVWAIT", Const, 0}, - {"SYS_PSYNCH_MUTEXDROP", Const, 0}, - {"SYS_PSYNCH_MUTEXWAIT", Const, 0}, - {"SYS_PSYNCH_RW_DOWNGRADE", Const, 0}, - {"SYS_PSYNCH_RW_LONGRDLOCK", Const, 0}, - {"SYS_PSYNCH_RW_RDLOCK", Const, 0}, - {"SYS_PSYNCH_RW_UNLOCK", Const, 0}, - {"SYS_PSYNCH_RW_UNLOCK2", Const, 0}, - {"SYS_PSYNCH_RW_UPGRADE", Const, 0}, - {"SYS_PSYNCH_RW_WRLOCK", Const, 0}, - {"SYS_PSYNCH_RW_YIELDWRLOCK", Const, 0}, - {"SYS_PTRACE", Const, 0}, - {"SYS_PUTPMSG", Const, 0}, - {"SYS_PWRITE", Const, 0}, - {"SYS_PWRITE64", Const, 0}, - {"SYS_PWRITEV", Const, 0}, - {"SYS_PWRITE_NOCANCEL", Const, 0}, - {"SYS_QUERY_MODULE", Const, 0}, - {"SYS_QUOTACTL", Const, 0}, - {"SYS_RASCTL", Const, 1}, - {"SYS_RCTL_ADD_RULE", Const, 0}, - {"SYS_RCTL_GET_LIMITS", Const, 0}, - {"SYS_RCTL_GET_RACCT", Const, 0}, - {"SYS_RCTL_GET_RULES", Const, 0}, - {"SYS_RCTL_REMOVE_RULE", Const, 0}, - {"SYS_READ", Const, 0}, - {"SYS_READAHEAD", Const, 0}, - {"SYS_READDIR", Const, 0}, - {"SYS_READLINK", Const, 0}, - {"SYS_READLINKAT", Const, 0}, - {"SYS_READV", Const, 0}, - {"SYS_READV_NOCANCEL", Const, 0}, - {"SYS_READ_NOCANCEL", Const, 0}, - {"SYS_REBOOT", Const, 0}, - {"SYS_RECV", Const, 0}, - {"SYS_RECVFROM", Const, 0}, - {"SYS_RECVFROM_NOCANCEL", Const, 0}, - {"SYS_RECVMMSG", Const, 0}, - {"SYS_RECVMSG", Const, 0}, - {"SYS_RECVMSG_NOCANCEL", Const, 0}, - {"SYS_REMAP_FILE_PAGES", Const, 0}, - {"SYS_REMOVEXATTR", Const, 0}, - {"SYS_RENAME", Const, 0}, - {"SYS_RENAMEAT", Const, 0}, - {"SYS_REQUEST_KEY", Const, 0}, - {"SYS_RESTART_SYSCALL", Const, 0}, - {"SYS_REVOKE", Const, 0}, - {"SYS_RFORK", Const, 0}, - {"SYS_RMDIR", Const, 0}, - {"SYS_RTPRIO", Const, 0}, - {"SYS_RTPRIO_THREAD", Const, 0}, - {"SYS_RT_SIGACTION", Const, 0}, - {"SYS_RT_SIGPENDING", Const, 0}, - {"SYS_RT_SIGPROCMASK", Const, 0}, - {"SYS_RT_SIGQUEUEINFO", Const, 0}, - {"SYS_RT_SIGRETURN", Const, 0}, - {"SYS_RT_SIGSUSPEND", Const, 0}, - {"SYS_RT_SIGTIMEDWAIT", Const, 0}, - {"SYS_RT_TGSIGQUEUEINFO", Const, 0}, - {"SYS_SBRK", Const, 0}, - {"SYS_SCHED_GETAFFINITY", Const, 0}, - {"SYS_SCHED_GETPARAM", Const, 0}, - {"SYS_SCHED_GETSCHEDULER", Const, 0}, - {"SYS_SCHED_GET_PRIORITY_MAX", Const, 0}, - {"SYS_SCHED_GET_PRIORITY_MIN", Const, 0}, - {"SYS_SCHED_RR_GET_INTERVAL", Const, 0}, - {"SYS_SCHED_SETAFFINITY", Const, 0}, - {"SYS_SCHED_SETPARAM", Const, 0}, - {"SYS_SCHED_SETSCHEDULER", Const, 0}, - {"SYS_SCHED_YIELD", Const, 0}, - {"SYS_SCTP_GENERIC_RECVMSG", Const, 0}, - {"SYS_SCTP_GENERIC_SENDMSG", Const, 0}, - {"SYS_SCTP_GENERIC_SENDMSG_IOV", Const, 0}, - {"SYS_SCTP_PEELOFF", Const, 0}, - {"SYS_SEARCHFS", Const, 0}, - {"SYS_SECURITY", Const, 0}, - {"SYS_SELECT", Const, 0}, - {"SYS_SELECT_NOCANCEL", Const, 0}, - {"SYS_SEMCONFIG", Const, 1}, - {"SYS_SEMCTL", Const, 0}, - {"SYS_SEMGET", Const, 0}, - {"SYS_SEMOP", Const, 0}, - {"SYS_SEMSYS", Const, 0}, - {"SYS_SEMTIMEDOP", Const, 0}, - {"SYS_SEM_CLOSE", Const, 0}, - {"SYS_SEM_DESTROY", Const, 0}, - {"SYS_SEM_GETVALUE", Const, 0}, - {"SYS_SEM_INIT", Const, 0}, - {"SYS_SEM_OPEN", Const, 0}, - {"SYS_SEM_POST", Const, 0}, - {"SYS_SEM_TRYWAIT", Const, 0}, - {"SYS_SEM_UNLINK", Const, 0}, - {"SYS_SEM_WAIT", Const, 0}, - {"SYS_SEM_WAIT_NOCANCEL", Const, 0}, - {"SYS_SEND", Const, 0}, - {"SYS_SENDFILE", Const, 0}, - {"SYS_SENDFILE64", Const, 0}, - {"SYS_SENDMMSG", Const, 0}, - {"SYS_SENDMSG", Const, 0}, - {"SYS_SENDMSG_NOCANCEL", Const, 0}, - {"SYS_SENDTO", Const, 0}, - {"SYS_SENDTO_NOCANCEL", Const, 0}, - {"SYS_SETATTRLIST", Const, 0}, - {"SYS_SETAUDIT", Const, 0}, - {"SYS_SETAUDIT_ADDR", Const, 0}, - {"SYS_SETAUID", Const, 0}, - {"SYS_SETCONTEXT", Const, 0}, - {"SYS_SETDOMAINNAME", Const, 0}, - {"SYS_SETEGID", Const, 0}, - {"SYS_SETEUID", Const, 0}, - {"SYS_SETFIB", Const, 0}, - {"SYS_SETFSGID", Const, 0}, - {"SYS_SETFSGID32", Const, 0}, - {"SYS_SETFSUID", Const, 0}, - {"SYS_SETFSUID32", Const, 0}, - {"SYS_SETGID", Const, 0}, - {"SYS_SETGID32", Const, 0}, - {"SYS_SETGROUPS", Const, 0}, - {"SYS_SETGROUPS32", Const, 0}, - {"SYS_SETHOSTNAME", Const, 0}, - {"SYS_SETITIMER", Const, 0}, - {"SYS_SETLCID", Const, 0}, - {"SYS_SETLOGIN", Const, 0}, - {"SYS_SETLOGINCLASS", Const, 0}, - {"SYS_SETNS", Const, 0}, - {"SYS_SETPGID", Const, 0}, - {"SYS_SETPRIORITY", Const, 0}, - {"SYS_SETPRIVEXEC", Const, 0}, - {"SYS_SETREGID", Const, 0}, - {"SYS_SETREGID32", Const, 0}, - {"SYS_SETRESGID", Const, 0}, - {"SYS_SETRESGID32", Const, 0}, - {"SYS_SETRESUID", Const, 0}, - {"SYS_SETRESUID32", Const, 0}, - {"SYS_SETREUID", Const, 0}, - {"SYS_SETREUID32", Const, 0}, - {"SYS_SETRLIMIT", Const, 0}, - {"SYS_SETRTABLE", Const, 1}, - {"SYS_SETSGROUPS", Const, 0}, - {"SYS_SETSID", Const, 0}, - {"SYS_SETSOCKOPT", Const, 0}, - {"SYS_SETTID", Const, 0}, - {"SYS_SETTID_WITH_PID", Const, 0}, - {"SYS_SETTIMEOFDAY", Const, 0}, - {"SYS_SETUID", Const, 0}, - {"SYS_SETUID32", Const, 0}, - {"SYS_SETWGROUPS", Const, 0}, - {"SYS_SETXATTR", Const, 0}, - {"SYS_SET_MEMPOLICY", Const, 0}, - {"SYS_SET_ROBUST_LIST", Const, 0}, - {"SYS_SET_THREAD_AREA", Const, 0}, - {"SYS_SET_TID_ADDRESS", Const, 0}, - {"SYS_SGETMASK", Const, 0}, - {"SYS_SHARED_REGION_CHECK_NP", Const, 0}, - {"SYS_SHARED_REGION_MAP_AND_SLIDE_NP", Const, 0}, - {"SYS_SHMAT", Const, 0}, - {"SYS_SHMCTL", Const, 0}, - {"SYS_SHMDT", Const, 0}, - {"SYS_SHMGET", Const, 0}, - {"SYS_SHMSYS", Const, 0}, - {"SYS_SHM_OPEN", Const, 0}, - {"SYS_SHM_UNLINK", Const, 0}, - {"SYS_SHUTDOWN", Const, 0}, - {"SYS_SIGACTION", Const, 0}, - {"SYS_SIGALTSTACK", Const, 0}, - {"SYS_SIGNAL", Const, 0}, - {"SYS_SIGNALFD", Const, 0}, - {"SYS_SIGNALFD4", Const, 0}, - {"SYS_SIGPENDING", Const, 0}, - {"SYS_SIGPROCMASK", Const, 0}, - {"SYS_SIGQUEUE", Const, 0}, - {"SYS_SIGQUEUEINFO", Const, 1}, - {"SYS_SIGRETURN", Const, 0}, - {"SYS_SIGSUSPEND", Const, 0}, - {"SYS_SIGSUSPEND_NOCANCEL", Const, 0}, - {"SYS_SIGTIMEDWAIT", Const, 0}, - {"SYS_SIGWAIT", Const, 0}, - {"SYS_SIGWAITINFO", Const, 0}, - {"SYS_SOCKET", Const, 0}, - {"SYS_SOCKETCALL", Const, 0}, - {"SYS_SOCKETPAIR", Const, 0}, - {"SYS_SPLICE", Const, 0}, - {"SYS_SSETMASK", Const, 0}, - {"SYS_SSTK", Const, 0}, - {"SYS_STACK_SNAPSHOT", Const, 0}, - {"SYS_STAT", Const, 0}, - {"SYS_STAT64", Const, 0}, - {"SYS_STAT64_EXTENDED", Const, 0}, - {"SYS_STATFS", Const, 0}, - {"SYS_STATFS64", Const, 0}, - {"SYS_STATV", Const, 0}, - {"SYS_STATVFS1", Const, 1}, - {"SYS_STAT_EXTENDED", Const, 0}, - {"SYS_STIME", Const, 0}, - {"SYS_STTY", Const, 0}, - {"SYS_SWAPCONTEXT", Const, 0}, - {"SYS_SWAPCTL", Const, 1}, - {"SYS_SWAPOFF", Const, 0}, - {"SYS_SWAPON", Const, 0}, - {"SYS_SYMLINK", Const, 0}, - {"SYS_SYMLINKAT", Const, 0}, - {"SYS_SYNC", Const, 0}, - {"SYS_SYNCFS", Const, 0}, - {"SYS_SYNC_FILE_RANGE", Const, 0}, - {"SYS_SYSARCH", Const, 0}, - {"SYS_SYSCALL", Const, 0}, - {"SYS_SYSCALL_BASE", Const, 0}, - {"SYS_SYSFS", Const, 0}, - {"SYS_SYSINFO", Const, 0}, - {"SYS_SYSLOG", Const, 0}, - {"SYS_TEE", Const, 0}, - {"SYS_TGKILL", Const, 0}, - {"SYS_THREAD_SELFID", Const, 0}, - {"SYS_THR_CREATE", Const, 0}, - {"SYS_THR_EXIT", Const, 0}, - {"SYS_THR_KILL", Const, 0}, - {"SYS_THR_KILL2", Const, 0}, - {"SYS_THR_NEW", Const, 0}, - {"SYS_THR_SELF", Const, 0}, - {"SYS_THR_SET_NAME", Const, 0}, - {"SYS_THR_SUSPEND", Const, 0}, - {"SYS_THR_WAKE", Const, 0}, - {"SYS_TIME", Const, 0}, - {"SYS_TIMERFD_CREATE", Const, 0}, - {"SYS_TIMERFD_GETTIME", Const, 0}, - {"SYS_TIMERFD_SETTIME", Const, 0}, - {"SYS_TIMER_CREATE", Const, 0}, - {"SYS_TIMER_DELETE", Const, 0}, - {"SYS_TIMER_GETOVERRUN", Const, 0}, - {"SYS_TIMER_GETTIME", Const, 0}, - {"SYS_TIMER_SETTIME", Const, 0}, - {"SYS_TIMES", Const, 0}, - {"SYS_TKILL", Const, 0}, - {"SYS_TRUNCATE", Const, 0}, - {"SYS_TRUNCATE64", Const, 0}, - {"SYS_TUXCALL", Const, 0}, - {"SYS_UGETRLIMIT", Const, 0}, - {"SYS_ULIMIT", Const, 0}, - {"SYS_UMASK", Const, 0}, - {"SYS_UMASK_EXTENDED", Const, 0}, - {"SYS_UMOUNT", Const, 0}, - {"SYS_UMOUNT2", Const, 0}, - {"SYS_UNAME", Const, 0}, - {"SYS_UNDELETE", Const, 0}, - {"SYS_UNLINK", Const, 0}, - {"SYS_UNLINKAT", Const, 0}, - {"SYS_UNMOUNT", Const, 0}, - {"SYS_UNSHARE", Const, 0}, - {"SYS_USELIB", Const, 0}, - {"SYS_USTAT", Const, 0}, - {"SYS_UTIME", Const, 0}, - {"SYS_UTIMENSAT", Const, 0}, - {"SYS_UTIMES", Const, 0}, - {"SYS_UTRACE", Const, 0}, - {"SYS_UUIDGEN", Const, 0}, - {"SYS_VADVISE", Const, 1}, - {"SYS_VFORK", Const, 0}, - {"SYS_VHANGUP", Const, 0}, - {"SYS_VM86", Const, 0}, - {"SYS_VM86OLD", Const, 0}, - {"SYS_VMSPLICE", Const, 0}, - {"SYS_VM_PRESSURE_MONITOR", Const, 0}, - {"SYS_VSERVER", Const, 0}, - {"SYS_WAIT4", Const, 0}, - {"SYS_WAIT4_NOCANCEL", Const, 0}, - {"SYS_WAIT6", Const, 1}, - {"SYS_WAITEVENT", Const, 0}, - {"SYS_WAITID", Const, 0}, - {"SYS_WAITID_NOCANCEL", Const, 0}, - {"SYS_WAITPID", Const, 0}, - {"SYS_WATCHEVENT", Const, 0}, - {"SYS_WORKQ_KERNRETURN", Const, 0}, - {"SYS_WORKQ_OPEN", Const, 0}, - {"SYS_WRITE", Const, 0}, - {"SYS_WRITEV", Const, 0}, - {"SYS_WRITEV_NOCANCEL", Const, 0}, - {"SYS_WRITE_NOCANCEL", Const, 0}, - {"SYS_YIELD", Const, 0}, - {"SYS__LLSEEK", Const, 0}, - {"SYS__LWP_CONTINUE", Const, 1}, - {"SYS__LWP_CREATE", Const, 1}, - {"SYS__LWP_CTL", Const, 1}, - {"SYS__LWP_DETACH", Const, 1}, - {"SYS__LWP_EXIT", Const, 1}, - {"SYS__LWP_GETNAME", Const, 1}, - {"SYS__LWP_GETPRIVATE", Const, 1}, - {"SYS__LWP_KILL", Const, 1}, - {"SYS__LWP_PARK", Const, 1}, - {"SYS__LWP_SELF", Const, 1}, - {"SYS__LWP_SETNAME", Const, 1}, - {"SYS__LWP_SETPRIVATE", Const, 1}, - {"SYS__LWP_SUSPEND", Const, 1}, - {"SYS__LWP_UNPARK", Const, 1}, - {"SYS__LWP_UNPARK_ALL", Const, 1}, - {"SYS__LWP_WAIT", Const, 1}, - {"SYS__LWP_WAKEUP", Const, 1}, - {"SYS__NEWSELECT", Const, 0}, - {"SYS__PSET_BIND", Const, 1}, - {"SYS__SCHED_GETAFFINITY", Const, 1}, - {"SYS__SCHED_GETPARAM", Const, 1}, - {"SYS__SCHED_SETAFFINITY", Const, 1}, - {"SYS__SCHED_SETPARAM", Const, 1}, - {"SYS__SYSCTL", Const, 0}, - {"SYS__UMTX_LOCK", Const, 0}, - {"SYS__UMTX_OP", Const, 0}, - {"SYS__UMTX_UNLOCK", Const, 0}, - {"SYS___ACL_ACLCHECK_FD", Const, 0}, - {"SYS___ACL_ACLCHECK_FILE", Const, 0}, - {"SYS___ACL_ACLCHECK_LINK", Const, 0}, - {"SYS___ACL_DELETE_FD", Const, 0}, - {"SYS___ACL_DELETE_FILE", Const, 0}, - {"SYS___ACL_DELETE_LINK", Const, 0}, - {"SYS___ACL_GET_FD", Const, 0}, - {"SYS___ACL_GET_FILE", Const, 0}, - {"SYS___ACL_GET_LINK", Const, 0}, - {"SYS___ACL_SET_FD", Const, 0}, - {"SYS___ACL_SET_FILE", Const, 0}, - {"SYS___ACL_SET_LINK", Const, 0}, - {"SYS___CAP_RIGHTS_GET", Const, 14}, - {"SYS___CLONE", Const, 1}, - {"SYS___DISABLE_THREADSIGNAL", Const, 0}, - {"SYS___GETCWD", Const, 0}, - {"SYS___GETLOGIN", Const, 1}, - {"SYS___GET_TCB", Const, 1}, - {"SYS___MAC_EXECVE", Const, 0}, - {"SYS___MAC_GETFSSTAT", Const, 0}, - {"SYS___MAC_GET_FD", Const, 0}, - {"SYS___MAC_GET_FILE", Const, 0}, - {"SYS___MAC_GET_LCID", Const, 0}, - {"SYS___MAC_GET_LCTX", Const, 0}, - {"SYS___MAC_GET_LINK", Const, 0}, - {"SYS___MAC_GET_MOUNT", Const, 0}, - {"SYS___MAC_GET_PID", Const, 0}, - {"SYS___MAC_GET_PROC", Const, 0}, - {"SYS___MAC_MOUNT", Const, 0}, - {"SYS___MAC_SET_FD", Const, 0}, - {"SYS___MAC_SET_FILE", Const, 0}, - {"SYS___MAC_SET_LCTX", Const, 0}, - {"SYS___MAC_SET_LINK", Const, 0}, - {"SYS___MAC_SET_PROC", Const, 0}, - {"SYS___MAC_SYSCALL", Const, 0}, - {"SYS___OLD_SEMWAIT_SIGNAL", Const, 0}, - {"SYS___OLD_SEMWAIT_SIGNAL_NOCANCEL", Const, 0}, - {"SYS___POSIX_CHOWN", Const, 1}, - {"SYS___POSIX_FCHOWN", Const, 1}, - {"SYS___POSIX_LCHOWN", Const, 1}, - {"SYS___POSIX_RENAME", Const, 1}, - {"SYS___PTHREAD_CANCELED", Const, 0}, - {"SYS___PTHREAD_CHDIR", Const, 0}, - {"SYS___PTHREAD_FCHDIR", Const, 0}, - {"SYS___PTHREAD_KILL", Const, 0}, - {"SYS___PTHREAD_MARKCANCEL", Const, 0}, - {"SYS___PTHREAD_SIGMASK", Const, 0}, - {"SYS___QUOTACTL", Const, 1}, - {"SYS___SEMCTL", Const, 1}, - {"SYS___SEMWAIT_SIGNAL", Const, 0}, - {"SYS___SEMWAIT_SIGNAL_NOCANCEL", Const, 0}, - {"SYS___SETLOGIN", Const, 1}, - {"SYS___SETUGID", Const, 0}, - {"SYS___SET_TCB", Const, 1}, - {"SYS___SIGACTION_SIGTRAMP", Const, 1}, - {"SYS___SIGTIMEDWAIT", Const, 1}, - {"SYS___SIGWAIT", Const, 0}, - {"SYS___SIGWAIT_NOCANCEL", Const, 0}, - {"SYS___SYSCTL", Const, 0}, - {"SYS___TFORK", Const, 1}, - {"SYS___THREXIT", Const, 1}, - {"SYS___THRSIGDIVERT", Const, 1}, - {"SYS___THRSLEEP", Const, 1}, - {"SYS___THRWAKEUP", Const, 1}, - {"S_ARCH1", Const, 1}, - {"S_ARCH2", Const, 1}, - {"S_BLKSIZE", Const, 0}, - {"S_IEXEC", Const, 0}, - {"S_IFBLK", Const, 0}, - {"S_IFCHR", Const, 0}, - {"S_IFDIR", Const, 0}, - {"S_IFIFO", Const, 0}, - {"S_IFLNK", Const, 0}, - {"S_IFMT", Const, 0}, - {"S_IFREG", Const, 0}, - {"S_IFSOCK", Const, 0}, - {"S_IFWHT", Const, 0}, - {"S_IREAD", Const, 0}, - {"S_IRGRP", Const, 0}, - {"S_IROTH", Const, 0}, - {"S_IRUSR", Const, 0}, - {"S_IRWXG", Const, 0}, - {"S_IRWXO", Const, 0}, - {"S_IRWXU", Const, 0}, - {"S_ISGID", Const, 0}, - {"S_ISTXT", Const, 0}, - {"S_ISUID", Const, 0}, - {"S_ISVTX", Const, 0}, - {"S_IWGRP", Const, 0}, - {"S_IWOTH", Const, 0}, - {"S_IWRITE", Const, 0}, - {"S_IWUSR", Const, 0}, - {"S_IXGRP", Const, 0}, - {"S_IXOTH", Const, 0}, - {"S_IXUSR", Const, 0}, - {"S_LOGIN_SET", Const, 1}, - {"SecurityAttributes", Type, 0}, - {"SecurityAttributes.InheritHandle", Field, 0}, - {"SecurityAttributes.Length", Field, 0}, - {"SecurityAttributes.SecurityDescriptor", Field, 0}, - {"Seek", Func, 0}, - {"Select", Func, 0}, - {"Sendfile", Func, 0}, - {"Sendmsg", Func, 0}, - {"SendmsgN", Func, 3}, - {"Sendto", Func, 0}, - {"Servent", Type, 0}, - {"Servent.Aliases", Field, 0}, - {"Servent.Name", Field, 0}, - {"Servent.Port", Field, 0}, - {"Servent.Proto", Field, 0}, - {"SetBpf", Func, 0}, - {"SetBpfBuflen", Func, 0}, - {"SetBpfDatalink", Func, 0}, - {"SetBpfHeadercmpl", Func, 0}, - {"SetBpfImmediate", Func, 0}, - {"SetBpfInterface", Func, 0}, - {"SetBpfPromisc", Func, 0}, - {"SetBpfTimeout", Func, 0}, - {"SetCurrentDirectory", Func, 0}, - {"SetEndOfFile", Func, 0}, - {"SetEnvironmentVariable", Func, 0}, - {"SetFileAttributes", Func, 0}, - {"SetFileCompletionNotificationModes", Func, 2}, - {"SetFilePointer", Func, 0}, - {"SetFileTime", Func, 0}, - {"SetHandleInformation", Func, 0}, - {"SetKevent", Func, 0}, - {"SetLsfPromisc", Func, 0}, - {"SetNonblock", Func, 0}, - {"Setdomainname", Func, 0}, - {"Setegid", Func, 0}, - {"Setenv", Func, 0}, - {"Seteuid", Func, 0}, - {"Setfsgid", Func, 0}, - {"Setfsuid", Func, 0}, - {"Setgid", Func, 0}, - {"Setgroups", Func, 0}, - {"Sethostname", Func, 0}, - {"Setlogin", Func, 0}, - {"Setpgid", Func, 0}, - {"Setpriority", Func, 0}, - {"Setprivexec", Func, 0}, - {"Setregid", Func, 0}, - {"Setresgid", Func, 0}, - {"Setresuid", Func, 0}, - {"Setreuid", Func, 0}, - {"Setrlimit", Func, 0}, - {"Setsid", Func, 0}, - {"Setsockopt", Func, 0}, - {"SetsockoptByte", Func, 0}, - {"SetsockoptICMPv6Filter", Func, 2}, - {"SetsockoptIPMreq", Func, 0}, - {"SetsockoptIPMreqn", Func, 0}, - {"SetsockoptIPv6Mreq", Func, 0}, - {"SetsockoptInet4Addr", Func, 0}, - {"SetsockoptInt", Func, 0}, - {"SetsockoptLinger", Func, 0}, - {"SetsockoptString", Func, 0}, - {"SetsockoptTimeval", Func, 0}, - {"Settimeofday", Func, 0}, - {"Setuid", Func, 0}, - {"Setxattr", Func, 1}, - {"Shutdown", Func, 0}, - {"SidTypeAlias", Const, 0}, - {"SidTypeComputer", Const, 0}, - {"SidTypeDeletedAccount", Const, 0}, - {"SidTypeDomain", Const, 0}, - {"SidTypeGroup", Const, 0}, - {"SidTypeInvalid", Const, 0}, - {"SidTypeLabel", Const, 0}, - {"SidTypeUnknown", Const, 0}, - {"SidTypeUser", Const, 0}, - {"SidTypeWellKnownGroup", Const, 0}, - {"Signal", Type, 0}, - {"SizeofBpfHdr", Const, 0}, - {"SizeofBpfInsn", Const, 0}, - {"SizeofBpfProgram", Const, 0}, - {"SizeofBpfStat", Const, 0}, - {"SizeofBpfVersion", Const, 0}, - {"SizeofBpfZbuf", Const, 0}, - {"SizeofBpfZbufHeader", Const, 0}, - {"SizeofCmsghdr", Const, 0}, - {"SizeofICMPv6Filter", Const, 2}, - {"SizeofIPMreq", Const, 0}, - {"SizeofIPMreqn", Const, 0}, - {"SizeofIPv6MTUInfo", Const, 2}, - {"SizeofIPv6Mreq", Const, 0}, - {"SizeofIfAddrmsg", Const, 0}, - {"SizeofIfAnnounceMsghdr", Const, 1}, - {"SizeofIfData", Const, 0}, - {"SizeofIfInfomsg", Const, 0}, - {"SizeofIfMsghdr", Const, 0}, - {"SizeofIfaMsghdr", Const, 0}, - {"SizeofIfmaMsghdr", Const, 0}, - {"SizeofIfmaMsghdr2", Const, 0}, - {"SizeofInet4Pktinfo", Const, 0}, - {"SizeofInet6Pktinfo", Const, 0}, - {"SizeofInotifyEvent", Const, 0}, - {"SizeofLinger", Const, 0}, - {"SizeofMsghdr", Const, 0}, - {"SizeofNlAttr", Const, 0}, - {"SizeofNlMsgerr", Const, 0}, - {"SizeofNlMsghdr", Const, 0}, - {"SizeofRtAttr", Const, 0}, - {"SizeofRtGenmsg", Const, 0}, - {"SizeofRtMetrics", Const, 0}, - {"SizeofRtMsg", Const, 0}, - {"SizeofRtMsghdr", Const, 0}, - {"SizeofRtNexthop", Const, 0}, - {"SizeofSockFilter", Const, 0}, - {"SizeofSockFprog", Const, 0}, - {"SizeofSockaddrAny", Const, 0}, - {"SizeofSockaddrDatalink", Const, 0}, - {"SizeofSockaddrInet4", Const, 0}, - {"SizeofSockaddrInet6", Const, 0}, - {"SizeofSockaddrLinklayer", Const, 0}, - {"SizeofSockaddrNetlink", Const, 0}, - {"SizeofSockaddrUnix", Const, 0}, - {"SizeofTCPInfo", Const, 1}, - {"SizeofUcred", Const, 0}, - {"SlicePtrFromStrings", Func, 1}, - {"SockFilter", Type, 0}, - {"SockFilter.Code", Field, 0}, - {"SockFilter.Jf", Field, 0}, - {"SockFilter.Jt", Field, 0}, - {"SockFilter.K", Field, 0}, - {"SockFprog", Type, 0}, - {"SockFprog.Filter", Field, 0}, - {"SockFprog.Len", Field, 0}, - {"SockFprog.Pad_cgo_0", Field, 0}, - {"Sockaddr", Type, 0}, - {"SockaddrDatalink", Type, 0}, - {"SockaddrDatalink.Alen", Field, 0}, - {"SockaddrDatalink.Data", Field, 0}, - {"SockaddrDatalink.Family", Field, 0}, - {"SockaddrDatalink.Index", Field, 0}, - {"SockaddrDatalink.Len", Field, 0}, - {"SockaddrDatalink.Nlen", Field, 0}, - {"SockaddrDatalink.Slen", Field, 0}, - {"SockaddrDatalink.Type", Field, 0}, - {"SockaddrGen", Type, 0}, - {"SockaddrInet4", Type, 0}, - {"SockaddrInet4.Addr", Field, 0}, - {"SockaddrInet4.Port", Field, 0}, - {"SockaddrInet6", Type, 0}, - {"SockaddrInet6.Addr", Field, 0}, - {"SockaddrInet6.Port", Field, 0}, - {"SockaddrInet6.ZoneId", Field, 0}, - {"SockaddrLinklayer", Type, 0}, - {"SockaddrLinklayer.Addr", Field, 0}, - {"SockaddrLinklayer.Halen", Field, 0}, - {"SockaddrLinklayer.Hatype", Field, 0}, - {"SockaddrLinklayer.Ifindex", Field, 0}, - {"SockaddrLinklayer.Pkttype", Field, 0}, - {"SockaddrLinklayer.Protocol", Field, 0}, - {"SockaddrNetlink", Type, 0}, - {"SockaddrNetlink.Family", Field, 0}, - {"SockaddrNetlink.Groups", Field, 0}, - {"SockaddrNetlink.Pad", Field, 0}, - {"SockaddrNetlink.Pid", Field, 0}, - {"SockaddrUnix", Type, 0}, - {"SockaddrUnix.Name", Field, 0}, - {"Socket", Func, 0}, - {"SocketControlMessage", Type, 0}, - {"SocketControlMessage.Data", Field, 0}, - {"SocketControlMessage.Header", Field, 0}, - {"SocketDisableIPv6", Var, 0}, - {"Socketpair", Func, 0}, - {"Splice", Func, 0}, - {"StartProcess", Func, 0}, - {"StartupInfo", Type, 0}, - {"StartupInfo.Cb", Field, 0}, - {"StartupInfo.Desktop", Field, 0}, - {"StartupInfo.FillAttribute", Field, 0}, - {"StartupInfo.Flags", Field, 0}, - {"StartupInfo.ShowWindow", Field, 0}, - {"StartupInfo.StdErr", Field, 0}, - {"StartupInfo.StdInput", Field, 0}, - {"StartupInfo.StdOutput", Field, 0}, - {"StartupInfo.Title", Field, 0}, - {"StartupInfo.X", Field, 0}, - {"StartupInfo.XCountChars", Field, 0}, - {"StartupInfo.XSize", Field, 0}, - {"StartupInfo.Y", Field, 0}, - {"StartupInfo.YCountChars", Field, 0}, - {"StartupInfo.YSize", Field, 0}, - {"Stat", Func, 0}, - {"Stat_t", Type, 0}, - {"Stat_t.Atim", Field, 0}, - {"Stat_t.Atim_ext", Field, 12}, - {"Stat_t.Atimespec", Field, 0}, - {"Stat_t.Birthtimespec", Field, 0}, - {"Stat_t.Blksize", Field, 0}, - {"Stat_t.Blocks", Field, 0}, - {"Stat_t.Btim_ext", Field, 12}, - {"Stat_t.Ctim", Field, 0}, - {"Stat_t.Ctim_ext", Field, 12}, - {"Stat_t.Ctimespec", Field, 0}, - {"Stat_t.Dev", Field, 0}, - {"Stat_t.Flags", Field, 0}, - {"Stat_t.Gen", Field, 0}, - {"Stat_t.Gid", Field, 0}, - {"Stat_t.Ino", Field, 0}, - {"Stat_t.Lspare", Field, 0}, - {"Stat_t.Lspare0", Field, 2}, - {"Stat_t.Lspare1", Field, 2}, - {"Stat_t.Mode", Field, 0}, - {"Stat_t.Mtim", Field, 0}, - {"Stat_t.Mtim_ext", Field, 12}, - {"Stat_t.Mtimespec", Field, 0}, - {"Stat_t.Nlink", Field, 0}, - {"Stat_t.Pad_cgo_0", Field, 0}, - {"Stat_t.Pad_cgo_1", Field, 0}, - {"Stat_t.Pad_cgo_2", Field, 0}, - {"Stat_t.Padding0", Field, 12}, - {"Stat_t.Padding1", Field, 12}, - {"Stat_t.Qspare", Field, 0}, - {"Stat_t.Rdev", Field, 0}, - {"Stat_t.Size", Field, 0}, - {"Stat_t.Spare", Field, 2}, - {"Stat_t.Uid", Field, 0}, - {"Stat_t.X__pad0", Field, 0}, - {"Stat_t.X__pad1", Field, 0}, - {"Stat_t.X__pad2", Field, 0}, - {"Stat_t.X__st_birthtim", Field, 2}, - {"Stat_t.X__st_ino", Field, 0}, - {"Stat_t.X__unused", Field, 0}, - {"Statfs", Func, 0}, - {"Statfs_t", Type, 0}, - {"Statfs_t.Asyncreads", Field, 0}, - {"Statfs_t.Asyncwrites", Field, 0}, - {"Statfs_t.Bavail", Field, 0}, - {"Statfs_t.Bfree", Field, 0}, - {"Statfs_t.Blocks", Field, 0}, - {"Statfs_t.Bsize", Field, 0}, - {"Statfs_t.Charspare", Field, 0}, - {"Statfs_t.F_asyncreads", Field, 2}, - {"Statfs_t.F_asyncwrites", Field, 2}, - {"Statfs_t.F_bavail", Field, 2}, - {"Statfs_t.F_bfree", Field, 2}, - {"Statfs_t.F_blocks", Field, 2}, - {"Statfs_t.F_bsize", Field, 2}, - {"Statfs_t.F_ctime", Field, 2}, - {"Statfs_t.F_favail", Field, 2}, - {"Statfs_t.F_ffree", Field, 2}, - {"Statfs_t.F_files", Field, 2}, - {"Statfs_t.F_flags", Field, 2}, - {"Statfs_t.F_fsid", Field, 2}, - {"Statfs_t.F_fstypename", Field, 2}, - {"Statfs_t.F_iosize", Field, 2}, - {"Statfs_t.F_mntfromname", Field, 2}, - {"Statfs_t.F_mntfromspec", Field, 3}, - {"Statfs_t.F_mntonname", Field, 2}, - {"Statfs_t.F_namemax", Field, 2}, - {"Statfs_t.F_owner", Field, 2}, - {"Statfs_t.F_spare", Field, 2}, - {"Statfs_t.F_syncreads", Field, 2}, - {"Statfs_t.F_syncwrites", Field, 2}, - {"Statfs_t.Ffree", Field, 0}, - {"Statfs_t.Files", Field, 0}, - {"Statfs_t.Flags", Field, 0}, - {"Statfs_t.Frsize", Field, 0}, - {"Statfs_t.Fsid", Field, 0}, - {"Statfs_t.Fssubtype", Field, 0}, - {"Statfs_t.Fstypename", Field, 0}, - {"Statfs_t.Iosize", Field, 0}, - {"Statfs_t.Mntfromname", Field, 0}, - {"Statfs_t.Mntonname", Field, 0}, - {"Statfs_t.Mount_info", Field, 2}, - {"Statfs_t.Namelen", Field, 0}, - {"Statfs_t.Namemax", Field, 0}, - {"Statfs_t.Owner", Field, 0}, - {"Statfs_t.Pad_cgo_0", Field, 0}, - {"Statfs_t.Pad_cgo_1", Field, 2}, - {"Statfs_t.Reserved", Field, 0}, - {"Statfs_t.Spare", Field, 0}, - {"Statfs_t.Syncreads", Field, 0}, - {"Statfs_t.Syncwrites", Field, 0}, - {"Statfs_t.Type", Field, 0}, - {"Statfs_t.Version", Field, 0}, - {"Stderr", Var, 0}, - {"Stdin", Var, 0}, - {"Stdout", Var, 0}, - {"StringBytePtr", Func, 0}, - {"StringByteSlice", Func, 0}, - {"StringSlicePtr", Func, 0}, - {"StringToSid", Func, 0}, - {"StringToUTF16", Func, 0}, - {"StringToUTF16Ptr", Func, 0}, - {"Symlink", Func, 0}, - {"Sync", Func, 0}, - {"SyncFileRange", Func, 0}, - {"SysProcAttr", Type, 0}, - {"SysProcAttr.AdditionalInheritedHandles", Field, 17}, - {"SysProcAttr.AmbientCaps", Field, 9}, - {"SysProcAttr.CgroupFD", Field, 20}, - {"SysProcAttr.Chroot", Field, 0}, - {"SysProcAttr.Cloneflags", Field, 2}, - {"SysProcAttr.CmdLine", Field, 0}, - {"SysProcAttr.CreationFlags", Field, 1}, - {"SysProcAttr.Credential", Field, 0}, - {"SysProcAttr.Ctty", Field, 1}, - {"SysProcAttr.Foreground", Field, 5}, - {"SysProcAttr.GidMappings", Field, 4}, - {"SysProcAttr.GidMappingsEnableSetgroups", Field, 5}, - {"SysProcAttr.HideWindow", Field, 0}, - {"SysProcAttr.Jail", Field, 21}, - {"SysProcAttr.NoInheritHandles", Field, 16}, - {"SysProcAttr.Noctty", Field, 0}, - {"SysProcAttr.ParentProcess", Field, 17}, - {"SysProcAttr.Pdeathsig", Field, 0}, - {"SysProcAttr.Pgid", Field, 5}, - {"SysProcAttr.PidFD", Field, 22}, - {"SysProcAttr.ProcessAttributes", Field, 13}, - {"SysProcAttr.Ptrace", Field, 0}, - {"SysProcAttr.Setctty", Field, 0}, - {"SysProcAttr.Setpgid", Field, 0}, - {"SysProcAttr.Setsid", Field, 0}, - {"SysProcAttr.ThreadAttributes", Field, 13}, - {"SysProcAttr.Token", Field, 10}, - {"SysProcAttr.UidMappings", Field, 4}, - {"SysProcAttr.Unshareflags", Field, 7}, - {"SysProcAttr.UseCgroupFD", Field, 20}, - {"SysProcIDMap", Type, 4}, - {"SysProcIDMap.ContainerID", Field, 4}, - {"SysProcIDMap.HostID", Field, 4}, - {"SysProcIDMap.Size", Field, 4}, - {"Syscall", Func, 0}, - {"Syscall12", Func, 0}, - {"Syscall15", Func, 0}, - {"Syscall18", Func, 12}, - {"Syscall6", Func, 0}, - {"Syscall9", Func, 0}, - {"SyscallN", Func, 18}, - {"Sysctl", Func, 0}, - {"SysctlUint32", Func, 0}, - {"Sysctlnode", Type, 2}, - {"Sysctlnode.Flags", Field, 2}, - {"Sysctlnode.Name", Field, 2}, - {"Sysctlnode.Num", Field, 2}, - {"Sysctlnode.Un", Field, 2}, - {"Sysctlnode.Ver", Field, 2}, - {"Sysctlnode.X__rsvd", Field, 2}, - {"Sysctlnode.X_sysctl_desc", Field, 2}, - {"Sysctlnode.X_sysctl_func", Field, 2}, - {"Sysctlnode.X_sysctl_parent", Field, 2}, - {"Sysctlnode.X_sysctl_size", Field, 2}, - {"Sysinfo", Func, 0}, - {"Sysinfo_t", Type, 0}, - {"Sysinfo_t.Bufferram", Field, 0}, - {"Sysinfo_t.Freehigh", Field, 0}, - {"Sysinfo_t.Freeram", Field, 0}, - {"Sysinfo_t.Freeswap", Field, 0}, - {"Sysinfo_t.Loads", Field, 0}, - {"Sysinfo_t.Pad", Field, 0}, - {"Sysinfo_t.Pad_cgo_0", Field, 0}, - {"Sysinfo_t.Pad_cgo_1", Field, 0}, - {"Sysinfo_t.Procs", Field, 0}, - {"Sysinfo_t.Sharedram", Field, 0}, - {"Sysinfo_t.Totalhigh", Field, 0}, - {"Sysinfo_t.Totalram", Field, 0}, - {"Sysinfo_t.Totalswap", Field, 0}, - {"Sysinfo_t.Unit", Field, 0}, - {"Sysinfo_t.Uptime", Field, 0}, - {"Sysinfo_t.X_f", Field, 0}, - {"Systemtime", Type, 0}, - {"Systemtime.Day", Field, 0}, - {"Systemtime.DayOfWeek", Field, 0}, - {"Systemtime.Hour", Field, 0}, - {"Systemtime.Milliseconds", Field, 0}, - {"Systemtime.Minute", Field, 0}, - {"Systemtime.Month", Field, 0}, - {"Systemtime.Second", Field, 0}, - {"Systemtime.Year", Field, 0}, - {"TCGETS", Const, 0}, - {"TCIFLUSH", Const, 1}, - {"TCIOFLUSH", Const, 1}, - {"TCOFLUSH", Const, 1}, - {"TCPInfo", Type, 1}, - {"TCPInfo.Advmss", Field, 1}, - {"TCPInfo.Ato", Field, 1}, - {"TCPInfo.Backoff", Field, 1}, - {"TCPInfo.Ca_state", Field, 1}, - {"TCPInfo.Fackets", Field, 1}, - {"TCPInfo.Last_ack_recv", Field, 1}, - {"TCPInfo.Last_ack_sent", Field, 1}, - {"TCPInfo.Last_data_recv", Field, 1}, - {"TCPInfo.Last_data_sent", Field, 1}, - {"TCPInfo.Lost", Field, 1}, - {"TCPInfo.Options", Field, 1}, - {"TCPInfo.Pad_cgo_0", Field, 1}, - {"TCPInfo.Pmtu", Field, 1}, - {"TCPInfo.Probes", Field, 1}, - {"TCPInfo.Rcv_mss", Field, 1}, - {"TCPInfo.Rcv_rtt", Field, 1}, - {"TCPInfo.Rcv_space", Field, 1}, - {"TCPInfo.Rcv_ssthresh", Field, 1}, - {"TCPInfo.Reordering", Field, 1}, - {"TCPInfo.Retrans", Field, 1}, - {"TCPInfo.Retransmits", Field, 1}, - {"TCPInfo.Rto", Field, 1}, - {"TCPInfo.Rtt", Field, 1}, - {"TCPInfo.Rttvar", Field, 1}, - {"TCPInfo.Sacked", Field, 1}, - {"TCPInfo.Snd_cwnd", Field, 1}, - {"TCPInfo.Snd_mss", Field, 1}, - {"TCPInfo.Snd_ssthresh", Field, 1}, - {"TCPInfo.State", Field, 1}, - {"TCPInfo.Total_retrans", Field, 1}, - {"TCPInfo.Unacked", Field, 1}, - {"TCPKeepalive", Type, 3}, - {"TCPKeepalive.Interval", Field, 3}, - {"TCPKeepalive.OnOff", Field, 3}, - {"TCPKeepalive.Time", Field, 3}, - {"TCP_CA_NAME_MAX", Const, 0}, - {"TCP_CONGCTL", Const, 1}, - {"TCP_CONGESTION", Const, 0}, - {"TCP_CONNECTIONTIMEOUT", Const, 0}, - {"TCP_CORK", Const, 0}, - {"TCP_DEFER_ACCEPT", Const, 0}, - {"TCP_ENABLE_ECN", Const, 16}, - {"TCP_INFO", Const, 0}, - {"TCP_KEEPALIVE", Const, 0}, - {"TCP_KEEPCNT", Const, 0}, - {"TCP_KEEPIDLE", Const, 0}, - {"TCP_KEEPINIT", Const, 1}, - {"TCP_KEEPINTVL", Const, 0}, - {"TCP_LINGER2", Const, 0}, - {"TCP_MAXBURST", Const, 0}, - {"TCP_MAXHLEN", Const, 0}, - {"TCP_MAXOLEN", Const, 0}, - {"TCP_MAXSEG", Const, 0}, - {"TCP_MAXWIN", Const, 0}, - {"TCP_MAX_SACK", Const, 0}, - {"TCP_MAX_WINSHIFT", Const, 0}, - {"TCP_MD5SIG", Const, 0}, - {"TCP_MD5SIG_MAXKEYLEN", Const, 0}, - {"TCP_MINMSS", Const, 0}, - {"TCP_MINMSSOVERLOAD", Const, 0}, - {"TCP_MSS", Const, 0}, - {"TCP_NODELAY", Const, 0}, - {"TCP_NOOPT", Const, 0}, - {"TCP_NOPUSH", Const, 0}, - {"TCP_NOTSENT_LOWAT", Const, 16}, - {"TCP_NSTATES", Const, 1}, - {"TCP_QUICKACK", Const, 0}, - {"TCP_RXT_CONNDROPTIME", Const, 0}, - {"TCP_RXT_FINDROP", Const, 0}, - {"TCP_SACK_ENABLE", Const, 1}, - {"TCP_SENDMOREACKS", Const, 16}, - {"TCP_SYNCNT", Const, 0}, - {"TCP_VENDOR", Const, 3}, - {"TCP_WINDOW_CLAMP", Const, 0}, - {"TCSAFLUSH", Const, 1}, - {"TCSETS", Const, 0}, - {"TF_DISCONNECT", Const, 0}, - {"TF_REUSE_SOCKET", Const, 0}, - {"TF_USE_DEFAULT_WORKER", Const, 0}, - {"TF_USE_KERNEL_APC", Const, 0}, - {"TF_USE_SYSTEM_THREAD", Const, 0}, - {"TF_WRITE_BEHIND", Const, 0}, - {"TH32CS_INHERIT", Const, 4}, - {"TH32CS_SNAPALL", Const, 4}, - {"TH32CS_SNAPHEAPLIST", Const, 4}, - {"TH32CS_SNAPMODULE", Const, 4}, - {"TH32CS_SNAPMODULE32", Const, 4}, - {"TH32CS_SNAPPROCESS", Const, 4}, - {"TH32CS_SNAPTHREAD", Const, 4}, - {"TIME_ZONE_ID_DAYLIGHT", Const, 0}, - {"TIME_ZONE_ID_STANDARD", Const, 0}, - {"TIME_ZONE_ID_UNKNOWN", Const, 0}, - {"TIOCCBRK", Const, 0}, - {"TIOCCDTR", Const, 0}, - {"TIOCCONS", Const, 0}, - {"TIOCDCDTIMESTAMP", Const, 0}, - {"TIOCDRAIN", Const, 0}, - {"TIOCDSIMICROCODE", Const, 0}, - {"TIOCEXCL", Const, 0}, - {"TIOCEXT", Const, 0}, - {"TIOCFLAG_CDTRCTS", Const, 1}, - {"TIOCFLAG_CLOCAL", Const, 1}, - {"TIOCFLAG_CRTSCTS", Const, 1}, - {"TIOCFLAG_MDMBUF", Const, 1}, - {"TIOCFLAG_PPS", Const, 1}, - {"TIOCFLAG_SOFTCAR", Const, 1}, - {"TIOCFLUSH", Const, 0}, - {"TIOCGDEV", Const, 0}, - {"TIOCGDRAINWAIT", Const, 0}, - {"TIOCGETA", Const, 0}, - {"TIOCGETD", Const, 0}, - {"TIOCGFLAGS", Const, 1}, - {"TIOCGICOUNT", Const, 0}, - {"TIOCGLCKTRMIOS", Const, 0}, - {"TIOCGLINED", Const, 1}, - {"TIOCGPGRP", Const, 0}, - {"TIOCGPTN", Const, 0}, - {"TIOCGQSIZE", Const, 1}, - {"TIOCGRANTPT", Const, 1}, - {"TIOCGRS485", Const, 0}, - {"TIOCGSERIAL", Const, 0}, - {"TIOCGSID", Const, 0}, - {"TIOCGSIZE", Const, 1}, - {"TIOCGSOFTCAR", Const, 0}, - {"TIOCGTSTAMP", Const, 1}, - {"TIOCGWINSZ", Const, 0}, - {"TIOCINQ", Const, 0}, - {"TIOCIXOFF", Const, 0}, - {"TIOCIXON", Const, 0}, - {"TIOCLINUX", Const, 0}, - {"TIOCMBIC", Const, 0}, - {"TIOCMBIS", Const, 0}, - {"TIOCMGDTRWAIT", Const, 0}, - {"TIOCMGET", Const, 0}, - {"TIOCMIWAIT", Const, 0}, - {"TIOCMODG", Const, 0}, - {"TIOCMODS", Const, 0}, - {"TIOCMSDTRWAIT", Const, 0}, - {"TIOCMSET", Const, 0}, - {"TIOCM_CAR", Const, 0}, - {"TIOCM_CD", Const, 0}, - {"TIOCM_CTS", Const, 0}, - {"TIOCM_DCD", Const, 0}, - {"TIOCM_DSR", Const, 0}, - {"TIOCM_DTR", Const, 0}, - {"TIOCM_LE", Const, 0}, - {"TIOCM_RI", Const, 0}, - {"TIOCM_RNG", Const, 0}, - {"TIOCM_RTS", Const, 0}, - {"TIOCM_SR", Const, 0}, - {"TIOCM_ST", Const, 0}, - {"TIOCNOTTY", Const, 0}, - {"TIOCNXCL", Const, 0}, - {"TIOCOUTQ", Const, 0}, - {"TIOCPKT", Const, 0}, - {"TIOCPKT_DATA", Const, 0}, - {"TIOCPKT_DOSTOP", Const, 0}, - {"TIOCPKT_FLUSHREAD", Const, 0}, - {"TIOCPKT_FLUSHWRITE", Const, 0}, - {"TIOCPKT_IOCTL", Const, 0}, - {"TIOCPKT_NOSTOP", Const, 0}, - {"TIOCPKT_START", Const, 0}, - {"TIOCPKT_STOP", Const, 0}, - {"TIOCPTMASTER", Const, 0}, - {"TIOCPTMGET", Const, 1}, - {"TIOCPTSNAME", Const, 1}, - {"TIOCPTYGNAME", Const, 0}, - {"TIOCPTYGRANT", Const, 0}, - {"TIOCPTYUNLK", Const, 0}, - {"TIOCRCVFRAME", Const, 1}, - {"TIOCREMOTE", Const, 0}, - {"TIOCSBRK", Const, 0}, - {"TIOCSCONS", Const, 0}, - {"TIOCSCTTY", Const, 0}, - {"TIOCSDRAINWAIT", Const, 0}, - {"TIOCSDTR", Const, 0}, - {"TIOCSERCONFIG", Const, 0}, - {"TIOCSERGETLSR", Const, 0}, - {"TIOCSERGETMULTI", Const, 0}, - {"TIOCSERGSTRUCT", Const, 0}, - {"TIOCSERGWILD", Const, 0}, - {"TIOCSERSETMULTI", Const, 0}, - {"TIOCSERSWILD", Const, 0}, - {"TIOCSER_TEMT", Const, 0}, - {"TIOCSETA", Const, 0}, - {"TIOCSETAF", Const, 0}, - {"TIOCSETAW", Const, 0}, - {"TIOCSETD", Const, 0}, - {"TIOCSFLAGS", Const, 1}, - {"TIOCSIG", Const, 0}, - {"TIOCSLCKTRMIOS", Const, 0}, - {"TIOCSLINED", Const, 1}, - {"TIOCSPGRP", Const, 0}, - {"TIOCSPTLCK", Const, 0}, - {"TIOCSQSIZE", Const, 1}, - {"TIOCSRS485", Const, 0}, - {"TIOCSSERIAL", Const, 0}, - {"TIOCSSIZE", Const, 1}, - {"TIOCSSOFTCAR", Const, 0}, - {"TIOCSTART", Const, 0}, - {"TIOCSTAT", Const, 0}, - {"TIOCSTI", Const, 0}, - {"TIOCSTOP", Const, 0}, - {"TIOCSTSTAMP", Const, 1}, - {"TIOCSWINSZ", Const, 0}, - {"TIOCTIMESTAMP", Const, 0}, - {"TIOCUCNTL", Const, 0}, - {"TIOCVHANGUP", Const, 0}, - {"TIOCXMTFRAME", Const, 1}, - {"TOKEN_ADJUST_DEFAULT", Const, 0}, - {"TOKEN_ADJUST_GROUPS", Const, 0}, - {"TOKEN_ADJUST_PRIVILEGES", Const, 0}, - {"TOKEN_ADJUST_SESSIONID", Const, 11}, - {"TOKEN_ALL_ACCESS", Const, 0}, - {"TOKEN_ASSIGN_PRIMARY", Const, 0}, - {"TOKEN_DUPLICATE", Const, 0}, - {"TOKEN_EXECUTE", Const, 0}, - {"TOKEN_IMPERSONATE", Const, 0}, - {"TOKEN_QUERY", Const, 0}, - {"TOKEN_QUERY_SOURCE", Const, 0}, - {"TOKEN_READ", Const, 0}, - {"TOKEN_WRITE", Const, 0}, - {"TOSTOP", Const, 0}, - {"TRUNCATE_EXISTING", Const, 0}, - {"TUNATTACHFILTER", Const, 0}, - {"TUNDETACHFILTER", Const, 0}, - {"TUNGETFEATURES", Const, 0}, - {"TUNGETIFF", Const, 0}, - {"TUNGETSNDBUF", Const, 0}, - {"TUNGETVNETHDRSZ", Const, 0}, - {"TUNSETDEBUG", Const, 0}, - {"TUNSETGROUP", Const, 0}, - {"TUNSETIFF", Const, 0}, - {"TUNSETLINK", Const, 0}, - {"TUNSETNOCSUM", Const, 0}, - {"TUNSETOFFLOAD", Const, 0}, - {"TUNSETOWNER", Const, 0}, - {"TUNSETPERSIST", Const, 0}, - {"TUNSETSNDBUF", Const, 0}, - {"TUNSETTXFILTER", Const, 0}, - {"TUNSETVNETHDRSZ", Const, 0}, - {"Tee", Func, 0}, - {"TerminateProcess", Func, 0}, - {"Termios", Type, 0}, - {"Termios.Cc", Field, 0}, - {"Termios.Cflag", Field, 0}, - {"Termios.Iflag", Field, 0}, - {"Termios.Ispeed", Field, 0}, - {"Termios.Lflag", Field, 0}, - {"Termios.Line", Field, 0}, - {"Termios.Oflag", Field, 0}, - {"Termios.Ospeed", Field, 0}, - {"Termios.Pad_cgo_0", Field, 0}, - {"Tgkill", Func, 0}, - {"Time", Func, 0}, - {"Time_t", Type, 0}, - {"Times", Func, 0}, - {"Timespec", Type, 0}, - {"Timespec.Nsec", Field, 0}, - {"Timespec.Pad_cgo_0", Field, 2}, - {"Timespec.Sec", Field, 0}, - {"TimespecToNsec", Func, 0}, - {"Timeval", Type, 0}, - {"Timeval.Pad_cgo_0", Field, 0}, - {"Timeval.Sec", Field, 0}, - {"Timeval.Usec", Field, 0}, - {"Timeval32", Type, 0}, - {"Timeval32.Sec", Field, 0}, - {"Timeval32.Usec", Field, 0}, - {"TimevalToNsec", Func, 0}, - {"Timex", Type, 0}, - {"Timex.Calcnt", Field, 0}, - {"Timex.Constant", Field, 0}, - {"Timex.Errcnt", Field, 0}, - {"Timex.Esterror", Field, 0}, - {"Timex.Freq", Field, 0}, - {"Timex.Jitcnt", Field, 0}, - {"Timex.Jitter", Field, 0}, - {"Timex.Maxerror", Field, 0}, - {"Timex.Modes", Field, 0}, - {"Timex.Offset", Field, 0}, - {"Timex.Pad_cgo_0", Field, 0}, - {"Timex.Pad_cgo_1", Field, 0}, - {"Timex.Pad_cgo_2", Field, 0}, - {"Timex.Pad_cgo_3", Field, 0}, - {"Timex.Ppsfreq", Field, 0}, - {"Timex.Precision", Field, 0}, - {"Timex.Shift", Field, 0}, - {"Timex.Stabil", Field, 0}, - {"Timex.Status", Field, 0}, - {"Timex.Stbcnt", Field, 0}, - {"Timex.Tai", Field, 0}, - {"Timex.Tick", Field, 0}, - {"Timex.Time", Field, 0}, - {"Timex.Tolerance", Field, 0}, - {"Timezoneinformation", Type, 0}, - {"Timezoneinformation.Bias", Field, 0}, - {"Timezoneinformation.DaylightBias", Field, 0}, - {"Timezoneinformation.DaylightDate", Field, 0}, - {"Timezoneinformation.DaylightName", Field, 0}, - {"Timezoneinformation.StandardBias", Field, 0}, - {"Timezoneinformation.StandardDate", Field, 0}, - {"Timezoneinformation.StandardName", Field, 0}, - {"Tms", Type, 0}, - {"Tms.Cstime", Field, 0}, - {"Tms.Cutime", Field, 0}, - {"Tms.Stime", Field, 0}, - {"Tms.Utime", Field, 0}, - {"Token", Type, 0}, - {"TokenAccessInformation", Const, 0}, - {"TokenAuditPolicy", Const, 0}, - {"TokenDefaultDacl", Const, 0}, - {"TokenElevation", Const, 0}, - {"TokenElevationType", Const, 0}, - {"TokenGroups", Const, 0}, - {"TokenGroupsAndPrivileges", Const, 0}, - {"TokenHasRestrictions", Const, 0}, - {"TokenImpersonationLevel", Const, 0}, - {"TokenIntegrityLevel", Const, 0}, - {"TokenLinkedToken", Const, 0}, - {"TokenLogonSid", Const, 0}, - {"TokenMandatoryPolicy", Const, 0}, - {"TokenOrigin", Const, 0}, - {"TokenOwner", Const, 0}, - {"TokenPrimaryGroup", Const, 0}, - {"TokenPrivileges", Const, 0}, - {"TokenRestrictedSids", Const, 0}, - {"TokenSandBoxInert", Const, 0}, - {"TokenSessionId", Const, 0}, - {"TokenSessionReference", Const, 0}, - {"TokenSource", Const, 0}, - {"TokenStatistics", Const, 0}, - {"TokenType", Const, 0}, - {"TokenUIAccess", Const, 0}, - {"TokenUser", Const, 0}, - {"TokenVirtualizationAllowed", Const, 0}, - {"TokenVirtualizationEnabled", Const, 0}, - {"Tokenprimarygroup", Type, 0}, - {"Tokenprimarygroup.PrimaryGroup", Field, 0}, - {"Tokenuser", Type, 0}, - {"Tokenuser.User", Field, 0}, - {"TranslateAccountName", Func, 0}, - {"TranslateName", Func, 0}, - {"TransmitFile", Func, 0}, - {"TransmitFileBuffers", Type, 0}, - {"TransmitFileBuffers.Head", Field, 0}, - {"TransmitFileBuffers.HeadLength", Field, 0}, - {"TransmitFileBuffers.Tail", Field, 0}, - {"TransmitFileBuffers.TailLength", Field, 0}, - {"Truncate", Func, 0}, - {"UNIX_PATH_MAX", Const, 12}, - {"USAGE_MATCH_TYPE_AND", Const, 0}, - {"USAGE_MATCH_TYPE_OR", Const, 0}, - {"UTF16FromString", Func, 1}, - {"UTF16PtrFromString", Func, 1}, - {"UTF16ToString", Func, 0}, - {"Ucred", Type, 0}, - {"Ucred.Gid", Field, 0}, - {"Ucred.Pid", Field, 0}, - {"Ucred.Uid", Field, 0}, - {"Umask", Func, 0}, - {"Uname", Func, 0}, - {"Undelete", Func, 0}, - {"UnixCredentials", Func, 0}, - {"UnixRights", Func, 0}, - {"Unlink", Func, 0}, - {"Unlinkat", Func, 0}, - {"UnmapViewOfFile", Func, 0}, - {"Unmount", Func, 0}, - {"Unsetenv", Func, 4}, - {"Unshare", Func, 0}, - {"UserInfo10", Type, 0}, - {"UserInfo10.Comment", Field, 0}, - {"UserInfo10.FullName", Field, 0}, - {"UserInfo10.Name", Field, 0}, - {"UserInfo10.UsrComment", Field, 0}, - {"Ustat", Func, 0}, - {"Ustat_t", Type, 0}, - {"Ustat_t.Fname", Field, 0}, - {"Ustat_t.Fpack", Field, 0}, - {"Ustat_t.Pad_cgo_0", Field, 0}, - {"Ustat_t.Pad_cgo_1", Field, 0}, - {"Ustat_t.Tfree", Field, 0}, - {"Ustat_t.Tinode", Field, 0}, - {"Utimbuf", Type, 0}, - {"Utimbuf.Actime", Field, 0}, - {"Utimbuf.Modtime", Field, 0}, - {"Utime", Func, 0}, - {"Utimes", Func, 0}, - {"UtimesNano", Func, 1}, - {"Utsname", Type, 0}, - {"Utsname.Domainname", Field, 0}, - {"Utsname.Machine", Field, 0}, - {"Utsname.Nodename", Field, 0}, - {"Utsname.Release", Field, 0}, - {"Utsname.Sysname", Field, 0}, - {"Utsname.Version", Field, 0}, - {"VDISCARD", Const, 0}, - {"VDSUSP", Const, 1}, - {"VEOF", Const, 0}, - {"VEOL", Const, 0}, - {"VEOL2", Const, 0}, - {"VERASE", Const, 0}, - {"VERASE2", Const, 1}, - {"VINTR", Const, 0}, - {"VKILL", Const, 0}, - {"VLNEXT", Const, 0}, - {"VMIN", Const, 0}, - {"VQUIT", Const, 0}, - {"VREPRINT", Const, 0}, - {"VSTART", Const, 0}, - {"VSTATUS", Const, 1}, - {"VSTOP", Const, 0}, - {"VSUSP", Const, 0}, - {"VSWTC", Const, 0}, - {"VT0", Const, 1}, - {"VT1", Const, 1}, - {"VTDLY", Const, 1}, - {"VTIME", Const, 0}, - {"VWERASE", Const, 0}, - {"VirtualLock", Func, 0}, - {"VirtualUnlock", Func, 0}, - {"WAIT_ABANDONED", Const, 0}, - {"WAIT_FAILED", Const, 0}, - {"WAIT_OBJECT_0", Const, 0}, - {"WAIT_TIMEOUT", Const, 0}, - {"WALL", Const, 0}, - {"WALLSIG", Const, 1}, - {"WALTSIG", Const, 1}, - {"WCLONE", Const, 0}, - {"WCONTINUED", Const, 0}, - {"WCOREFLAG", Const, 0}, - {"WEXITED", Const, 0}, - {"WLINUXCLONE", Const, 0}, - {"WNOHANG", Const, 0}, - {"WNOTHREAD", Const, 0}, - {"WNOWAIT", Const, 0}, - {"WNOZOMBIE", Const, 1}, - {"WOPTSCHECKED", Const, 1}, - {"WORDSIZE", Const, 0}, - {"WSABuf", Type, 0}, - {"WSABuf.Buf", Field, 0}, - {"WSABuf.Len", Field, 0}, - {"WSACleanup", Func, 0}, - {"WSADESCRIPTION_LEN", Const, 0}, - {"WSAData", Type, 0}, - {"WSAData.Description", Field, 0}, - {"WSAData.HighVersion", Field, 0}, - {"WSAData.MaxSockets", Field, 0}, - {"WSAData.MaxUdpDg", Field, 0}, - {"WSAData.SystemStatus", Field, 0}, - {"WSAData.VendorInfo", Field, 0}, - {"WSAData.Version", Field, 0}, - {"WSAEACCES", Const, 2}, - {"WSAECONNABORTED", Const, 9}, - {"WSAECONNRESET", Const, 3}, - {"WSAENOPROTOOPT", Const, 23}, - {"WSAEnumProtocols", Func, 2}, - {"WSAID_CONNECTEX", Var, 1}, - {"WSAIoctl", Func, 0}, - {"WSAPROTOCOL_LEN", Const, 2}, - {"WSAProtocolChain", Type, 2}, - {"WSAProtocolChain.ChainEntries", Field, 2}, - {"WSAProtocolChain.ChainLen", Field, 2}, - {"WSAProtocolInfo", Type, 2}, - {"WSAProtocolInfo.AddressFamily", Field, 2}, - {"WSAProtocolInfo.CatalogEntryId", Field, 2}, - {"WSAProtocolInfo.MaxSockAddr", Field, 2}, - {"WSAProtocolInfo.MessageSize", Field, 2}, - {"WSAProtocolInfo.MinSockAddr", Field, 2}, - {"WSAProtocolInfo.NetworkByteOrder", Field, 2}, - {"WSAProtocolInfo.Protocol", Field, 2}, - {"WSAProtocolInfo.ProtocolChain", Field, 2}, - {"WSAProtocolInfo.ProtocolMaxOffset", Field, 2}, - {"WSAProtocolInfo.ProtocolName", Field, 2}, - {"WSAProtocolInfo.ProviderFlags", Field, 2}, - {"WSAProtocolInfo.ProviderId", Field, 2}, - {"WSAProtocolInfo.ProviderReserved", Field, 2}, - {"WSAProtocolInfo.SecurityScheme", Field, 2}, - {"WSAProtocolInfo.ServiceFlags1", Field, 2}, - {"WSAProtocolInfo.ServiceFlags2", Field, 2}, - {"WSAProtocolInfo.ServiceFlags3", Field, 2}, - {"WSAProtocolInfo.ServiceFlags4", Field, 2}, - {"WSAProtocolInfo.SocketType", Field, 2}, - {"WSAProtocolInfo.Version", Field, 2}, - {"WSARecv", Func, 0}, - {"WSARecvFrom", Func, 0}, - {"WSASYS_STATUS_LEN", Const, 0}, - {"WSASend", Func, 0}, - {"WSASendTo", Func, 0}, - {"WSASendto", Func, 0}, - {"WSAStartup", Func, 0}, - {"WSTOPPED", Const, 0}, - {"WTRAPPED", Const, 1}, - {"WUNTRACED", Const, 0}, - {"Wait4", Func, 0}, - {"WaitForSingleObject", Func, 0}, - {"WaitStatus", Type, 0}, - {"WaitStatus.ExitCode", Field, 0}, - {"Win32FileAttributeData", Type, 0}, - {"Win32FileAttributeData.CreationTime", Field, 0}, - {"Win32FileAttributeData.FileAttributes", Field, 0}, - {"Win32FileAttributeData.FileSizeHigh", Field, 0}, - {"Win32FileAttributeData.FileSizeLow", Field, 0}, - {"Win32FileAttributeData.LastAccessTime", Field, 0}, - {"Win32FileAttributeData.LastWriteTime", Field, 0}, - {"Win32finddata", Type, 0}, - {"Win32finddata.AlternateFileName", Field, 0}, - {"Win32finddata.CreationTime", Field, 0}, - {"Win32finddata.FileAttributes", Field, 0}, - {"Win32finddata.FileName", Field, 0}, - {"Win32finddata.FileSizeHigh", Field, 0}, - {"Win32finddata.FileSizeLow", Field, 0}, - {"Win32finddata.LastAccessTime", Field, 0}, - {"Win32finddata.LastWriteTime", Field, 0}, - {"Win32finddata.Reserved0", Field, 0}, - {"Win32finddata.Reserved1", Field, 0}, - {"Write", Func, 0}, - {"WriteConsole", Func, 1}, - {"WriteFile", Func, 0}, - {"X509_ASN_ENCODING", Const, 0}, - {"XCASE", Const, 0}, - {"XP1_CONNECTIONLESS", Const, 2}, - {"XP1_CONNECT_DATA", Const, 2}, - {"XP1_DISCONNECT_DATA", Const, 2}, - {"XP1_EXPEDITED_DATA", Const, 2}, - {"XP1_GRACEFUL_CLOSE", Const, 2}, - {"XP1_GUARANTEED_DELIVERY", Const, 2}, - {"XP1_GUARANTEED_ORDER", Const, 2}, - {"XP1_IFS_HANDLES", Const, 2}, - {"XP1_MESSAGE_ORIENTED", Const, 2}, - {"XP1_MULTIPOINT_CONTROL_PLANE", Const, 2}, - {"XP1_MULTIPOINT_DATA_PLANE", Const, 2}, - {"XP1_PARTIAL_MESSAGE", Const, 2}, - {"XP1_PSEUDO_STREAM", Const, 2}, - {"XP1_QOS_SUPPORTED", Const, 2}, - {"XP1_SAN_SUPPORT_SDP", Const, 2}, - {"XP1_SUPPORT_BROADCAST", Const, 2}, - {"XP1_SUPPORT_MULTIPOINT", Const, 2}, - {"XP1_UNI_RECV", Const, 2}, - {"XP1_UNI_SEND", Const, 2}, + {"(*Cmsghdr).SetLen", Method, 0, ""}, + {"(*DLL).FindProc", Method, 0, ""}, + {"(*DLL).MustFindProc", Method, 0, ""}, + {"(*DLL).Release", Method, 0, ""}, + {"(*DLLError).Error", Method, 0, ""}, + {"(*DLLError).Unwrap", Method, 16, ""}, + {"(*Filetime).Nanoseconds", Method, 0, ""}, + {"(*Iovec).SetLen", Method, 0, ""}, + {"(*LazyDLL).Handle", Method, 0, ""}, + {"(*LazyDLL).Load", Method, 0, ""}, + {"(*LazyDLL).NewProc", Method, 0, ""}, + {"(*LazyProc).Addr", Method, 0, ""}, + {"(*LazyProc).Call", Method, 0, ""}, + {"(*LazyProc).Find", Method, 0, ""}, + {"(*Msghdr).SetControllen", Method, 0, ""}, + {"(*Proc).Addr", Method, 0, ""}, + {"(*Proc).Call", Method, 0, ""}, + {"(*PtraceRegs).PC", Method, 0, ""}, + {"(*PtraceRegs).SetPC", Method, 0, ""}, + {"(*RawSockaddrAny).Sockaddr", Method, 0, ""}, + {"(*SID).Copy", Method, 0, ""}, + {"(*SID).Len", Method, 0, ""}, + {"(*SID).LookupAccount", Method, 0, ""}, + {"(*SID).String", Method, 0, ""}, + {"(*Timespec).Nano", Method, 0, ""}, + {"(*Timespec).Unix", Method, 0, ""}, + {"(*Timeval).Nano", Method, 0, ""}, + {"(*Timeval).Nanoseconds", Method, 0, ""}, + {"(*Timeval).Unix", Method, 0, ""}, + {"(Errno).Error", Method, 0, ""}, + {"(Errno).Is", Method, 13, ""}, + {"(Errno).Temporary", Method, 0, ""}, + {"(Errno).Timeout", Method, 0, ""}, + {"(Signal).Signal", Method, 0, ""}, + {"(Signal).String", Method, 0, ""}, + {"(Token).Close", Method, 0, ""}, + {"(Token).GetTokenPrimaryGroup", Method, 0, ""}, + {"(Token).GetTokenUser", Method, 0, ""}, + {"(Token).GetUserProfileDirectory", Method, 0, ""}, + {"(WaitStatus).Continued", Method, 0, ""}, + {"(WaitStatus).CoreDump", Method, 0, ""}, + {"(WaitStatus).ExitStatus", Method, 0, ""}, + {"(WaitStatus).Exited", Method, 0, ""}, + {"(WaitStatus).Signal", Method, 0, ""}, + {"(WaitStatus).Signaled", Method, 0, ""}, + {"(WaitStatus).StopSignal", Method, 0, ""}, + {"(WaitStatus).Stopped", Method, 0, ""}, + {"(WaitStatus).TrapCause", Method, 0, ""}, + {"AF_ALG", Const, 0, ""}, + {"AF_APPLETALK", Const, 0, ""}, + {"AF_ARP", Const, 0, ""}, + {"AF_ASH", Const, 0, ""}, + {"AF_ATM", Const, 0, ""}, + {"AF_ATMPVC", Const, 0, ""}, + {"AF_ATMSVC", Const, 0, ""}, + {"AF_AX25", Const, 0, ""}, + {"AF_BLUETOOTH", Const, 0, ""}, + {"AF_BRIDGE", Const, 0, ""}, + {"AF_CAIF", Const, 0, ""}, + {"AF_CAN", Const, 0, ""}, + {"AF_CCITT", Const, 0, ""}, + {"AF_CHAOS", Const, 0, ""}, + {"AF_CNT", Const, 0, ""}, + {"AF_COIP", Const, 0, ""}, + {"AF_DATAKIT", Const, 0, ""}, + {"AF_DECnet", Const, 0, ""}, + {"AF_DLI", Const, 0, ""}, + {"AF_E164", Const, 0, ""}, + {"AF_ECMA", Const, 0, ""}, + {"AF_ECONET", Const, 0, ""}, + {"AF_ENCAP", Const, 1, ""}, + {"AF_FILE", Const, 0, ""}, + {"AF_HYLINK", Const, 0, ""}, + {"AF_IEEE80211", Const, 0, ""}, + {"AF_IEEE802154", Const, 0, ""}, + {"AF_IMPLINK", Const, 0, ""}, + {"AF_INET", Const, 0, ""}, + {"AF_INET6", Const, 0, ""}, + {"AF_INET6_SDP", Const, 3, ""}, + {"AF_INET_SDP", Const, 3, ""}, + {"AF_IPX", Const, 0, ""}, + {"AF_IRDA", Const, 0, ""}, + {"AF_ISDN", Const, 0, ""}, + {"AF_ISO", Const, 0, ""}, + {"AF_IUCV", Const, 0, ""}, + {"AF_KEY", Const, 0, ""}, + {"AF_LAT", Const, 0, ""}, + {"AF_LINK", Const, 0, ""}, + {"AF_LLC", Const, 0, ""}, + {"AF_LOCAL", Const, 0, ""}, + {"AF_MAX", Const, 0, ""}, + {"AF_MPLS", Const, 1, ""}, + {"AF_NATM", Const, 0, ""}, + {"AF_NDRV", Const, 0, ""}, + {"AF_NETBEUI", Const, 0, ""}, + {"AF_NETBIOS", Const, 0, ""}, + {"AF_NETGRAPH", Const, 0, ""}, + {"AF_NETLINK", Const, 0, ""}, + {"AF_NETROM", Const, 0, ""}, + {"AF_NS", Const, 0, ""}, + {"AF_OROUTE", Const, 1, ""}, + {"AF_OSI", Const, 0, ""}, + {"AF_PACKET", Const, 0, ""}, + {"AF_PHONET", Const, 0, ""}, + {"AF_PPP", Const, 0, ""}, + {"AF_PPPOX", Const, 0, ""}, + {"AF_PUP", Const, 0, ""}, + {"AF_RDS", Const, 0, ""}, + {"AF_RESERVED_36", Const, 0, ""}, + {"AF_ROSE", Const, 0, ""}, + {"AF_ROUTE", Const, 0, ""}, + {"AF_RXRPC", Const, 0, ""}, + {"AF_SCLUSTER", Const, 0, ""}, + {"AF_SECURITY", Const, 0, ""}, + {"AF_SIP", Const, 0, ""}, + {"AF_SLOW", Const, 0, ""}, + {"AF_SNA", Const, 0, ""}, + {"AF_SYSTEM", Const, 0, ""}, + {"AF_TIPC", Const, 0, ""}, + {"AF_UNIX", Const, 0, ""}, + {"AF_UNSPEC", Const, 0, ""}, + {"AF_UTUN", Const, 16, ""}, + {"AF_VENDOR00", Const, 0, ""}, + {"AF_VENDOR01", Const, 0, ""}, + {"AF_VENDOR02", Const, 0, ""}, + {"AF_VENDOR03", Const, 0, ""}, + {"AF_VENDOR04", Const, 0, ""}, + {"AF_VENDOR05", Const, 0, ""}, + {"AF_VENDOR06", Const, 0, ""}, + {"AF_VENDOR07", Const, 0, ""}, + {"AF_VENDOR08", Const, 0, ""}, + {"AF_VENDOR09", Const, 0, ""}, + {"AF_VENDOR10", Const, 0, ""}, + {"AF_VENDOR11", Const, 0, ""}, + {"AF_VENDOR12", Const, 0, ""}, + {"AF_VENDOR13", Const, 0, ""}, + {"AF_VENDOR14", Const, 0, ""}, + {"AF_VENDOR15", Const, 0, ""}, + {"AF_VENDOR16", Const, 0, ""}, + {"AF_VENDOR17", Const, 0, ""}, + {"AF_VENDOR18", Const, 0, ""}, + {"AF_VENDOR19", Const, 0, ""}, + {"AF_VENDOR20", Const, 0, ""}, + {"AF_VENDOR21", Const, 0, ""}, + {"AF_VENDOR22", Const, 0, ""}, + {"AF_VENDOR23", Const, 0, ""}, + {"AF_VENDOR24", Const, 0, ""}, + {"AF_VENDOR25", Const, 0, ""}, + {"AF_VENDOR26", Const, 0, ""}, + {"AF_VENDOR27", Const, 0, ""}, + {"AF_VENDOR28", Const, 0, ""}, + {"AF_VENDOR29", Const, 0, ""}, + {"AF_VENDOR30", Const, 0, ""}, + {"AF_VENDOR31", Const, 0, ""}, + {"AF_VENDOR32", Const, 0, ""}, + {"AF_VENDOR33", Const, 0, ""}, + {"AF_VENDOR34", Const, 0, ""}, + {"AF_VENDOR35", Const, 0, ""}, + {"AF_VENDOR36", Const, 0, ""}, + {"AF_VENDOR37", Const, 0, ""}, + {"AF_VENDOR38", Const, 0, ""}, + {"AF_VENDOR39", Const, 0, ""}, + {"AF_VENDOR40", Const, 0, ""}, + {"AF_VENDOR41", Const, 0, ""}, + {"AF_VENDOR42", Const, 0, ""}, + {"AF_VENDOR43", Const, 0, ""}, + {"AF_VENDOR44", Const, 0, ""}, + {"AF_VENDOR45", Const, 0, ""}, + {"AF_VENDOR46", Const, 0, ""}, + {"AF_VENDOR47", Const, 0, ""}, + {"AF_WANPIPE", Const, 0, ""}, + {"AF_X25", Const, 0, ""}, + {"AI_CANONNAME", Const, 1, ""}, + {"AI_NUMERICHOST", Const, 1, ""}, + {"AI_PASSIVE", Const, 1, ""}, + {"APPLICATION_ERROR", Const, 0, ""}, + {"ARPHRD_ADAPT", Const, 0, ""}, + {"ARPHRD_APPLETLK", Const, 0, ""}, + {"ARPHRD_ARCNET", Const, 0, ""}, + {"ARPHRD_ASH", Const, 0, ""}, + {"ARPHRD_ATM", Const, 0, ""}, + {"ARPHRD_AX25", Const, 0, ""}, + {"ARPHRD_BIF", Const, 0, ""}, + {"ARPHRD_CHAOS", Const, 0, ""}, + {"ARPHRD_CISCO", Const, 0, ""}, + {"ARPHRD_CSLIP", Const, 0, ""}, + {"ARPHRD_CSLIP6", Const, 0, ""}, + {"ARPHRD_DDCMP", Const, 0, ""}, + {"ARPHRD_DLCI", Const, 0, ""}, + {"ARPHRD_ECONET", Const, 0, ""}, + {"ARPHRD_EETHER", Const, 0, ""}, + {"ARPHRD_ETHER", Const, 0, ""}, + {"ARPHRD_EUI64", Const, 0, ""}, + {"ARPHRD_FCAL", Const, 0, ""}, + {"ARPHRD_FCFABRIC", Const, 0, ""}, + {"ARPHRD_FCPL", Const, 0, ""}, + {"ARPHRD_FCPP", Const, 0, ""}, + {"ARPHRD_FDDI", Const, 0, ""}, + {"ARPHRD_FRAD", Const, 0, ""}, + {"ARPHRD_FRELAY", Const, 1, ""}, + {"ARPHRD_HDLC", Const, 0, ""}, + {"ARPHRD_HIPPI", Const, 0, ""}, + {"ARPHRD_HWX25", Const, 0, ""}, + {"ARPHRD_IEEE1394", Const, 0, ""}, + {"ARPHRD_IEEE802", Const, 0, ""}, + {"ARPHRD_IEEE80211", Const, 0, ""}, + {"ARPHRD_IEEE80211_PRISM", Const, 0, ""}, + {"ARPHRD_IEEE80211_RADIOTAP", Const, 0, ""}, + {"ARPHRD_IEEE802154", Const, 0, ""}, + {"ARPHRD_IEEE802154_PHY", Const, 0, ""}, + {"ARPHRD_IEEE802_TR", Const, 0, ""}, + {"ARPHRD_INFINIBAND", Const, 0, ""}, + {"ARPHRD_IPDDP", Const, 0, ""}, + {"ARPHRD_IPGRE", Const, 0, ""}, + {"ARPHRD_IRDA", Const, 0, ""}, + {"ARPHRD_LAPB", Const, 0, ""}, + {"ARPHRD_LOCALTLK", Const, 0, ""}, + {"ARPHRD_LOOPBACK", Const, 0, ""}, + {"ARPHRD_METRICOM", Const, 0, ""}, + {"ARPHRD_NETROM", Const, 0, ""}, + {"ARPHRD_NONE", Const, 0, ""}, + {"ARPHRD_PIMREG", Const, 0, ""}, + {"ARPHRD_PPP", Const, 0, ""}, + {"ARPHRD_PRONET", Const, 0, ""}, + {"ARPHRD_RAWHDLC", Const, 0, ""}, + {"ARPHRD_ROSE", Const, 0, ""}, + {"ARPHRD_RSRVD", Const, 0, ""}, + {"ARPHRD_SIT", Const, 0, ""}, + {"ARPHRD_SKIP", Const, 0, ""}, + {"ARPHRD_SLIP", Const, 0, ""}, + {"ARPHRD_SLIP6", Const, 0, ""}, + {"ARPHRD_STRIP", Const, 1, ""}, + {"ARPHRD_TUNNEL", Const, 0, ""}, + {"ARPHRD_TUNNEL6", Const, 0, ""}, + {"ARPHRD_VOID", Const, 0, ""}, + {"ARPHRD_X25", Const, 0, ""}, + {"AUTHTYPE_CLIENT", Const, 0, ""}, + {"AUTHTYPE_SERVER", Const, 0, ""}, + {"Accept", Func, 0, "func(fd int) (nfd int, sa Sockaddr, err error)"}, + {"Accept4", Func, 1, "func(fd int, flags int) (nfd int, sa Sockaddr, err error)"}, + {"AcceptEx", Func, 0, ""}, + {"Access", Func, 0, "func(path string, mode uint32) (err error)"}, + {"Acct", Func, 0, "func(path string) (err error)"}, + {"AddrinfoW", Type, 1, ""}, + {"AddrinfoW.Addr", Field, 1, ""}, + {"AddrinfoW.Addrlen", Field, 1, ""}, + {"AddrinfoW.Canonname", Field, 1, ""}, + {"AddrinfoW.Family", Field, 1, ""}, + {"AddrinfoW.Flags", Field, 1, ""}, + {"AddrinfoW.Next", Field, 1, ""}, + {"AddrinfoW.Protocol", Field, 1, ""}, + {"AddrinfoW.Socktype", Field, 1, ""}, + {"Adjtime", Func, 0, ""}, + {"Adjtimex", Func, 0, "func(buf *Timex) (state int, err error)"}, + {"AllThreadsSyscall", Func, 16, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, + {"AllThreadsSyscall6", Func, 16, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr, a4 uintptr, a5 uintptr, a6 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, + {"AttachLsf", Func, 0, "func(fd int, i []SockFilter) error"}, + {"B0", Const, 0, ""}, + {"B1000000", Const, 0, ""}, + {"B110", Const, 0, ""}, + {"B115200", Const, 0, ""}, + {"B1152000", Const, 0, ""}, + {"B1200", Const, 0, ""}, + {"B134", Const, 0, ""}, + {"B14400", Const, 1, ""}, + {"B150", Const, 0, ""}, + {"B1500000", Const, 0, ""}, + {"B1800", Const, 0, ""}, + {"B19200", Const, 0, ""}, + {"B200", Const, 0, ""}, + {"B2000000", Const, 0, ""}, + {"B230400", Const, 0, ""}, + {"B2400", Const, 0, ""}, + {"B2500000", Const, 0, ""}, + {"B28800", Const, 1, ""}, + {"B300", Const, 0, ""}, + {"B3000000", Const, 0, ""}, + {"B3500000", Const, 0, ""}, + {"B38400", Const, 0, ""}, + {"B4000000", Const, 0, ""}, + {"B460800", Const, 0, ""}, + {"B4800", Const, 0, ""}, + {"B50", Const, 0, ""}, + {"B500000", Const, 0, ""}, + {"B57600", Const, 0, ""}, + {"B576000", Const, 0, ""}, + {"B600", Const, 0, ""}, + {"B7200", Const, 1, ""}, + {"B75", Const, 0, ""}, + {"B76800", Const, 1, ""}, + {"B921600", Const, 0, ""}, + {"B9600", Const, 0, ""}, + {"BASE_PROTOCOL", Const, 2, ""}, + {"BIOCFEEDBACK", Const, 0, ""}, + {"BIOCFLUSH", Const, 0, ""}, + {"BIOCGBLEN", Const, 0, ""}, + {"BIOCGDIRECTION", Const, 0, ""}, + {"BIOCGDIRFILT", Const, 1, ""}, + {"BIOCGDLT", Const, 0, ""}, + {"BIOCGDLTLIST", Const, 0, ""}, + {"BIOCGETBUFMODE", Const, 0, ""}, + {"BIOCGETIF", Const, 0, ""}, + {"BIOCGETZMAX", Const, 0, ""}, + {"BIOCGFEEDBACK", Const, 1, ""}, + {"BIOCGFILDROP", Const, 1, ""}, + {"BIOCGHDRCMPLT", Const, 0, ""}, + {"BIOCGRSIG", Const, 0, ""}, + {"BIOCGRTIMEOUT", Const, 0, ""}, + {"BIOCGSEESENT", Const, 0, ""}, + {"BIOCGSTATS", Const, 0, ""}, + {"BIOCGSTATSOLD", Const, 1, ""}, + {"BIOCGTSTAMP", Const, 1, ""}, + {"BIOCIMMEDIATE", Const, 0, ""}, + {"BIOCLOCK", Const, 0, ""}, + {"BIOCPROMISC", Const, 0, ""}, + {"BIOCROTZBUF", Const, 0, ""}, + {"BIOCSBLEN", Const, 0, ""}, + {"BIOCSDIRECTION", Const, 0, ""}, + {"BIOCSDIRFILT", Const, 1, ""}, + {"BIOCSDLT", Const, 0, ""}, + {"BIOCSETBUFMODE", Const, 0, ""}, + {"BIOCSETF", Const, 0, ""}, + {"BIOCSETFNR", Const, 0, ""}, + {"BIOCSETIF", Const, 0, ""}, + {"BIOCSETWF", Const, 0, ""}, + {"BIOCSETZBUF", Const, 0, ""}, + {"BIOCSFEEDBACK", Const, 1, ""}, + {"BIOCSFILDROP", Const, 1, ""}, + {"BIOCSHDRCMPLT", Const, 0, ""}, + {"BIOCSRSIG", Const, 0, ""}, + {"BIOCSRTIMEOUT", Const, 0, ""}, + {"BIOCSSEESENT", Const, 0, ""}, + {"BIOCSTCPF", Const, 1, ""}, + {"BIOCSTSTAMP", Const, 1, ""}, + {"BIOCSUDPF", Const, 1, ""}, + {"BIOCVERSION", Const, 0, ""}, + {"BPF_A", Const, 0, ""}, + {"BPF_ABS", Const, 0, ""}, + {"BPF_ADD", Const, 0, ""}, + {"BPF_ALIGNMENT", Const, 0, ""}, + {"BPF_ALIGNMENT32", Const, 1, ""}, + {"BPF_ALU", Const, 0, ""}, + {"BPF_AND", Const, 0, ""}, + {"BPF_B", Const, 0, ""}, + {"BPF_BUFMODE_BUFFER", Const, 0, ""}, + {"BPF_BUFMODE_ZBUF", Const, 0, ""}, + {"BPF_DFLTBUFSIZE", Const, 1, ""}, + {"BPF_DIRECTION_IN", Const, 1, ""}, + {"BPF_DIRECTION_OUT", Const, 1, ""}, + {"BPF_DIV", Const, 0, ""}, + {"BPF_H", Const, 0, ""}, + {"BPF_IMM", Const, 0, ""}, + {"BPF_IND", Const, 0, ""}, + {"BPF_JA", Const, 0, ""}, + {"BPF_JEQ", Const, 0, ""}, + {"BPF_JGE", Const, 0, ""}, + {"BPF_JGT", Const, 0, ""}, + {"BPF_JMP", Const, 0, ""}, + {"BPF_JSET", Const, 0, ""}, + {"BPF_K", Const, 0, ""}, + {"BPF_LD", Const, 0, ""}, + {"BPF_LDX", Const, 0, ""}, + {"BPF_LEN", Const, 0, ""}, + {"BPF_LSH", Const, 0, ""}, + {"BPF_MAJOR_VERSION", Const, 0, ""}, + {"BPF_MAXBUFSIZE", Const, 0, ""}, + {"BPF_MAXINSNS", Const, 0, ""}, + {"BPF_MEM", Const, 0, ""}, + {"BPF_MEMWORDS", Const, 0, ""}, + {"BPF_MINBUFSIZE", Const, 0, ""}, + {"BPF_MINOR_VERSION", Const, 0, ""}, + {"BPF_MISC", Const, 0, ""}, + {"BPF_MSH", Const, 0, ""}, + {"BPF_MUL", Const, 0, ""}, + {"BPF_NEG", Const, 0, ""}, + {"BPF_OR", Const, 0, ""}, + {"BPF_RELEASE", Const, 0, ""}, + {"BPF_RET", Const, 0, ""}, + {"BPF_RSH", Const, 0, ""}, + {"BPF_ST", Const, 0, ""}, + {"BPF_STX", Const, 0, ""}, + {"BPF_SUB", Const, 0, ""}, + {"BPF_TAX", Const, 0, ""}, + {"BPF_TXA", Const, 0, ""}, + {"BPF_T_BINTIME", Const, 1, ""}, + {"BPF_T_BINTIME_FAST", Const, 1, ""}, + {"BPF_T_BINTIME_MONOTONIC", Const, 1, ""}, + {"BPF_T_BINTIME_MONOTONIC_FAST", Const, 1, ""}, + {"BPF_T_FAST", Const, 1, ""}, + {"BPF_T_FLAG_MASK", Const, 1, ""}, + {"BPF_T_FORMAT_MASK", Const, 1, ""}, + {"BPF_T_MICROTIME", Const, 1, ""}, + {"BPF_T_MICROTIME_FAST", Const, 1, ""}, + {"BPF_T_MICROTIME_MONOTONIC", Const, 1, ""}, + {"BPF_T_MICROTIME_MONOTONIC_FAST", Const, 1, ""}, + {"BPF_T_MONOTONIC", Const, 1, ""}, + {"BPF_T_MONOTONIC_FAST", Const, 1, ""}, + {"BPF_T_NANOTIME", Const, 1, ""}, + {"BPF_T_NANOTIME_FAST", Const, 1, ""}, + {"BPF_T_NANOTIME_MONOTONIC", Const, 1, ""}, + {"BPF_T_NANOTIME_MONOTONIC_FAST", Const, 1, ""}, + {"BPF_T_NONE", Const, 1, ""}, + {"BPF_T_NORMAL", Const, 1, ""}, + {"BPF_W", Const, 0, ""}, + {"BPF_X", Const, 0, ""}, + {"BRKINT", Const, 0, ""}, + {"Bind", Func, 0, "func(fd int, sa Sockaddr) (err error)"}, + {"BindToDevice", Func, 0, "func(fd int, device string) (err error)"}, + {"BpfBuflen", Func, 0, ""}, + {"BpfDatalink", Func, 0, ""}, + {"BpfHdr", Type, 0, ""}, + {"BpfHdr.Caplen", Field, 0, ""}, + {"BpfHdr.Datalen", Field, 0, ""}, + {"BpfHdr.Hdrlen", Field, 0, ""}, + {"BpfHdr.Pad_cgo_0", Field, 0, ""}, + {"BpfHdr.Tstamp", Field, 0, ""}, + {"BpfHeadercmpl", Func, 0, ""}, + {"BpfInsn", Type, 0, ""}, + {"BpfInsn.Code", Field, 0, ""}, + {"BpfInsn.Jf", Field, 0, ""}, + {"BpfInsn.Jt", Field, 0, ""}, + {"BpfInsn.K", Field, 0, ""}, + {"BpfInterface", Func, 0, ""}, + {"BpfJump", Func, 0, ""}, + {"BpfProgram", Type, 0, ""}, + {"BpfProgram.Insns", Field, 0, ""}, + {"BpfProgram.Len", Field, 0, ""}, + {"BpfProgram.Pad_cgo_0", Field, 0, ""}, + {"BpfStat", Type, 0, ""}, + {"BpfStat.Capt", Field, 2, ""}, + {"BpfStat.Drop", Field, 0, ""}, + {"BpfStat.Padding", Field, 2, ""}, + {"BpfStat.Recv", Field, 0, ""}, + {"BpfStats", Func, 0, ""}, + {"BpfStmt", Func, 0, ""}, + {"BpfTimeout", Func, 0, ""}, + {"BpfTimeval", Type, 2, ""}, + {"BpfTimeval.Sec", Field, 2, ""}, + {"BpfTimeval.Usec", Field, 2, ""}, + {"BpfVersion", Type, 0, ""}, + {"BpfVersion.Major", Field, 0, ""}, + {"BpfVersion.Minor", Field, 0, ""}, + {"BpfZbuf", Type, 0, ""}, + {"BpfZbuf.Bufa", Field, 0, ""}, + {"BpfZbuf.Bufb", Field, 0, ""}, + {"BpfZbuf.Buflen", Field, 0, ""}, + {"BpfZbufHeader", Type, 0, ""}, + {"BpfZbufHeader.Kernel_gen", Field, 0, ""}, + {"BpfZbufHeader.Kernel_len", Field, 0, ""}, + {"BpfZbufHeader.User_gen", Field, 0, ""}, + {"BpfZbufHeader.X_bzh_pad", Field, 0, ""}, + {"ByHandleFileInformation", Type, 0, ""}, + {"ByHandleFileInformation.CreationTime", Field, 0, ""}, + {"ByHandleFileInformation.FileAttributes", Field, 0, ""}, + {"ByHandleFileInformation.FileIndexHigh", Field, 0, ""}, + {"ByHandleFileInformation.FileIndexLow", Field, 0, ""}, + {"ByHandleFileInformation.FileSizeHigh", Field, 0, ""}, + {"ByHandleFileInformation.FileSizeLow", Field, 0, ""}, + {"ByHandleFileInformation.LastAccessTime", Field, 0, ""}, + {"ByHandleFileInformation.LastWriteTime", Field, 0, ""}, + {"ByHandleFileInformation.NumberOfLinks", Field, 0, ""}, + {"ByHandleFileInformation.VolumeSerialNumber", Field, 0, ""}, + {"BytePtrFromString", Func, 1, "func(s string) (*byte, error)"}, + {"ByteSliceFromString", Func, 1, "func(s string) ([]byte, error)"}, + {"CCR0_FLUSH", Const, 1, ""}, + {"CERT_CHAIN_POLICY_AUTHENTICODE", Const, 0, ""}, + {"CERT_CHAIN_POLICY_AUTHENTICODE_TS", Const, 0, ""}, + {"CERT_CHAIN_POLICY_BASE", Const, 0, ""}, + {"CERT_CHAIN_POLICY_BASIC_CONSTRAINTS", Const, 0, ""}, + {"CERT_CHAIN_POLICY_EV", Const, 0, ""}, + {"CERT_CHAIN_POLICY_MICROSOFT_ROOT", Const, 0, ""}, + {"CERT_CHAIN_POLICY_NT_AUTH", Const, 0, ""}, + {"CERT_CHAIN_POLICY_SSL", Const, 0, ""}, + {"CERT_E_CN_NO_MATCH", Const, 0, ""}, + {"CERT_E_EXPIRED", Const, 0, ""}, + {"CERT_E_PURPOSE", Const, 0, ""}, + {"CERT_E_ROLE", Const, 0, ""}, + {"CERT_E_UNTRUSTEDROOT", Const, 0, ""}, + {"CERT_STORE_ADD_ALWAYS", Const, 0, ""}, + {"CERT_STORE_DEFER_CLOSE_UNTIL_LAST_FREE_FLAG", Const, 0, ""}, + {"CERT_STORE_PROV_MEMORY", Const, 0, ""}, + {"CERT_TRUST_HAS_EXCLUDED_NAME_CONSTRAINT", Const, 0, ""}, + {"CERT_TRUST_HAS_NOT_DEFINED_NAME_CONSTRAINT", Const, 0, ""}, + {"CERT_TRUST_HAS_NOT_PERMITTED_NAME_CONSTRAINT", Const, 0, ""}, + {"CERT_TRUST_HAS_NOT_SUPPORTED_CRITICAL_EXT", Const, 0, ""}, + {"CERT_TRUST_HAS_NOT_SUPPORTED_NAME_CONSTRAINT", Const, 0, ""}, + {"CERT_TRUST_INVALID_BASIC_CONSTRAINTS", Const, 0, ""}, + {"CERT_TRUST_INVALID_EXTENSION", Const, 0, ""}, + {"CERT_TRUST_INVALID_NAME_CONSTRAINTS", Const, 0, ""}, + {"CERT_TRUST_INVALID_POLICY_CONSTRAINTS", Const, 0, ""}, + {"CERT_TRUST_IS_CYCLIC", Const, 0, ""}, + {"CERT_TRUST_IS_EXPLICIT_DISTRUST", Const, 0, ""}, + {"CERT_TRUST_IS_NOT_SIGNATURE_VALID", Const, 0, ""}, + {"CERT_TRUST_IS_NOT_TIME_VALID", Const, 0, ""}, + {"CERT_TRUST_IS_NOT_VALID_FOR_USAGE", Const, 0, ""}, + {"CERT_TRUST_IS_OFFLINE_REVOCATION", Const, 0, ""}, + {"CERT_TRUST_IS_REVOKED", Const, 0, ""}, + {"CERT_TRUST_IS_UNTRUSTED_ROOT", Const, 0, ""}, + {"CERT_TRUST_NO_ERROR", Const, 0, ""}, + {"CERT_TRUST_NO_ISSUANCE_CHAIN_POLICY", Const, 0, ""}, + {"CERT_TRUST_REVOCATION_STATUS_UNKNOWN", Const, 0, ""}, + {"CFLUSH", Const, 1, ""}, + {"CLOCAL", Const, 0, ""}, + {"CLONE_CHILD_CLEARTID", Const, 2, ""}, + {"CLONE_CHILD_SETTID", Const, 2, ""}, + {"CLONE_CLEAR_SIGHAND", Const, 20, ""}, + {"CLONE_CSIGNAL", Const, 3, ""}, + {"CLONE_DETACHED", Const, 2, ""}, + {"CLONE_FILES", Const, 2, ""}, + {"CLONE_FS", Const, 2, ""}, + {"CLONE_INTO_CGROUP", Const, 20, ""}, + {"CLONE_IO", Const, 2, ""}, + {"CLONE_NEWCGROUP", Const, 20, ""}, + {"CLONE_NEWIPC", Const, 2, ""}, + {"CLONE_NEWNET", Const, 2, ""}, + {"CLONE_NEWNS", Const, 2, ""}, + {"CLONE_NEWPID", Const, 2, ""}, + {"CLONE_NEWTIME", Const, 20, ""}, + {"CLONE_NEWUSER", Const, 2, ""}, + {"CLONE_NEWUTS", Const, 2, ""}, + {"CLONE_PARENT", Const, 2, ""}, + {"CLONE_PARENT_SETTID", Const, 2, ""}, + {"CLONE_PID", Const, 3, ""}, + {"CLONE_PIDFD", Const, 20, ""}, + {"CLONE_PTRACE", Const, 2, ""}, + {"CLONE_SETTLS", Const, 2, ""}, + {"CLONE_SIGHAND", Const, 2, ""}, + {"CLONE_SYSVSEM", Const, 2, ""}, + {"CLONE_THREAD", Const, 2, ""}, + {"CLONE_UNTRACED", Const, 2, ""}, + {"CLONE_VFORK", Const, 2, ""}, + {"CLONE_VM", Const, 2, ""}, + {"CPUID_CFLUSH", Const, 1, ""}, + {"CREAD", Const, 0, ""}, + {"CREATE_ALWAYS", Const, 0, ""}, + {"CREATE_NEW", Const, 0, ""}, + {"CREATE_NEW_PROCESS_GROUP", Const, 1, ""}, + {"CREATE_UNICODE_ENVIRONMENT", Const, 0, ""}, + {"CRYPT_DEFAULT_CONTAINER_OPTIONAL", Const, 0, ""}, + {"CRYPT_DELETEKEYSET", Const, 0, ""}, + {"CRYPT_MACHINE_KEYSET", Const, 0, ""}, + {"CRYPT_NEWKEYSET", Const, 0, ""}, + {"CRYPT_SILENT", Const, 0, ""}, + {"CRYPT_VERIFYCONTEXT", Const, 0, ""}, + {"CS5", Const, 0, ""}, + {"CS6", Const, 0, ""}, + {"CS7", Const, 0, ""}, + {"CS8", Const, 0, ""}, + {"CSIZE", Const, 0, ""}, + {"CSTART", Const, 1, ""}, + {"CSTATUS", Const, 1, ""}, + {"CSTOP", Const, 1, ""}, + {"CSTOPB", Const, 0, ""}, + {"CSUSP", Const, 1, ""}, + {"CTL_MAXNAME", Const, 0, ""}, + {"CTL_NET", Const, 0, ""}, + {"CTL_QUERY", Const, 1, ""}, + {"CTRL_BREAK_EVENT", Const, 1, ""}, + {"CTRL_CLOSE_EVENT", Const, 14, ""}, + {"CTRL_C_EVENT", Const, 1, ""}, + {"CTRL_LOGOFF_EVENT", Const, 14, ""}, + {"CTRL_SHUTDOWN_EVENT", Const, 14, ""}, + {"CancelIo", Func, 0, ""}, + {"CancelIoEx", Func, 1, ""}, + {"CertAddCertificateContextToStore", Func, 0, ""}, + {"CertChainContext", Type, 0, ""}, + {"CertChainContext.ChainCount", Field, 0, ""}, + {"CertChainContext.Chains", Field, 0, ""}, + {"CertChainContext.HasRevocationFreshnessTime", Field, 0, ""}, + {"CertChainContext.LowerQualityChainCount", Field, 0, ""}, + {"CertChainContext.LowerQualityChains", Field, 0, ""}, + {"CertChainContext.RevocationFreshnessTime", Field, 0, ""}, + {"CertChainContext.Size", Field, 0, ""}, + {"CertChainContext.TrustStatus", Field, 0, ""}, + {"CertChainElement", Type, 0, ""}, + {"CertChainElement.ApplicationUsage", Field, 0, ""}, + {"CertChainElement.CertContext", Field, 0, ""}, + {"CertChainElement.ExtendedErrorInfo", Field, 0, ""}, + {"CertChainElement.IssuanceUsage", Field, 0, ""}, + {"CertChainElement.RevocationInfo", Field, 0, ""}, + {"CertChainElement.Size", Field, 0, ""}, + {"CertChainElement.TrustStatus", Field, 0, ""}, + {"CertChainPara", Type, 0, ""}, + {"CertChainPara.CacheResync", Field, 0, ""}, + {"CertChainPara.CheckRevocationFreshnessTime", Field, 0, ""}, + {"CertChainPara.RequestedUsage", Field, 0, ""}, + {"CertChainPara.RequstedIssuancePolicy", Field, 0, ""}, + {"CertChainPara.RevocationFreshnessTime", Field, 0, ""}, + {"CertChainPara.Size", Field, 0, ""}, + {"CertChainPara.URLRetrievalTimeout", Field, 0, ""}, + {"CertChainPolicyPara", Type, 0, ""}, + {"CertChainPolicyPara.ExtraPolicyPara", Field, 0, ""}, + {"CertChainPolicyPara.Flags", Field, 0, ""}, + {"CertChainPolicyPara.Size", Field, 0, ""}, + {"CertChainPolicyStatus", Type, 0, ""}, + {"CertChainPolicyStatus.ChainIndex", Field, 0, ""}, + {"CertChainPolicyStatus.ElementIndex", Field, 0, ""}, + {"CertChainPolicyStatus.Error", Field, 0, ""}, + {"CertChainPolicyStatus.ExtraPolicyStatus", Field, 0, ""}, + {"CertChainPolicyStatus.Size", Field, 0, ""}, + {"CertCloseStore", Func, 0, ""}, + {"CertContext", Type, 0, ""}, + {"CertContext.CertInfo", Field, 0, ""}, + {"CertContext.EncodedCert", Field, 0, ""}, + {"CertContext.EncodingType", Field, 0, ""}, + {"CertContext.Length", Field, 0, ""}, + {"CertContext.Store", Field, 0, ""}, + {"CertCreateCertificateContext", Func, 0, ""}, + {"CertEnhKeyUsage", Type, 0, ""}, + {"CertEnhKeyUsage.Length", Field, 0, ""}, + {"CertEnhKeyUsage.UsageIdentifiers", Field, 0, ""}, + {"CertEnumCertificatesInStore", Func, 0, ""}, + {"CertFreeCertificateChain", Func, 0, ""}, + {"CertFreeCertificateContext", Func, 0, ""}, + {"CertGetCertificateChain", Func, 0, ""}, + {"CertInfo", Type, 11, ""}, + {"CertOpenStore", Func, 0, ""}, + {"CertOpenSystemStore", Func, 0, ""}, + {"CertRevocationCrlInfo", Type, 11, ""}, + {"CertRevocationInfo", Type, 0, ""}, + {"CertRevocationInfo.CrlInfo", Field, 0, ""}, + {"CertRevocationInfo.FreshnessTime", Field, 0, ""}, + {"CertRevocationInfo.HasFreshnessTime", Field, 0, ""}, + {"CertRevocationInfo.OidSpecificInfo", Field, 0, ""}, + {"CertRevocationInfo.RevocationOid", Field, 0, ""}, + {"CertRevocationInfo.RevocationResult", Field, 0, ""}, + {"CertRevocationInfo.Size", Field, 0, ""}, + {"CertSimpleChain", Type, 0, ""}, + {"CertSimpleChain.Elements", Field, 0, ""}, + {"CertSimpleChain.HasRevocationFreshnessTime", Field, 0, ""}, + {"CertSimpleChain.NumElements", Field, 0, ""}, + {"CertSimpleChain.RevocationFreshnessTime", Field, 0, ""}, + {"CertSimpleChain.Size", Field, 0, ""}, + {"CertSimpleChain.TrustListInfo", Field, 0, ""}, + {"CertSimpleChain.TrustStatus", Field, 0, ""}, + {"CertTrustListInfo", Type, 11, ""}, + {"CertTrustStatus", Type, 0, ""}, + {"CertTrustStatus.ErrorStatus", Field, 0, ""}, + {"CertTrustStatus.InfoStatus", Field, 0, ""}, + {"CertUsageMatch", Type, 0, ""}, + {"CertUsageMatch.Type", Field, 0, ""}, + {"CertUsageMatch.Usage", Field, 0, ""}, + {"CertVerifyCertificateChainPolicy", Func, 0, ""}, + {"Chdir", Func, 0, "func(path string) (err error)"}, + {"CheckBpfVersion", Func, 0, ""}, + {"Chflags", Func, 0, ""}, + {"Chmod", Func, 0, "func(path string, mode uint32) (err error)"}, + {"Chown", Func, 0, "func(path string, uid int, gid int) (err error)"}, + {"Chroot", Func, 0, "func(path string) (err error)"}, + {"Clearenv", Func, 0, "func()"}, + {"Close", Func, 0, "func(fd int) (err error)"}, + {"CloseHandle", Func, 0, ""}, + {"CloseOnExec", Func, 0, "func(fd int)"}, + {"Closesocket", Func, 0, ""}, + {"CmsgLen", Func, 0, "func(datalen int) int"}, + {"CmsgSpace", Func, 0, "func(datalen int) int"}, + {"Cmsghdr", Type, 0, ""}, + {"Cmsghdr.Len", Field, 0, ""}, + {"Cmsghdr.Level", Field, 0, ""}, + {"Cmsghdr.Type", Field, 0, ""}, + {"Cmsghdr.X__cmsg_data", Field, 0, ""}, + {"CommandLineToArgv", Func, 0, ""}, + {"ComputerName", Func, 0, ""}, + {"Conn", Type, 9, ""}, + {"Connect", Func, 0, "func(fd int, sa Sockaddr) (err error)"}, + {"ConnectEx", Func, 1, ""}, + {"ConvertSidToStringSid", Func, 0, ""}, + {"ConvertStringSidToSid", Func, 0, ""}, + {"CopySid", Func, 0, ""}, + {"Creat", Func, 0, "func(path string, mode uint32) (fd int, err error)"}, + {"CreateDirectory", Func, 0, ""}, + {"CreateFile", Func, 0, ""}, + {"CreateFileMapping", Func, 0, ""}, + {"CreateHardLink", Func, 4, ""}, + {"CreateIoCompletionPort", Func, 0, ""}, + {"CreatePipe", Func, 0, ""}, + {"CreateProcess", Func, 0, ""}, + {"CreateProcessAsUser", Func, 10, ""}, + {"CreateSymbolicLink", Func, 4, ""}, + {"CreateToolhelp32Snapshot", Func, 4, ""}, + {"Credential", Type, 0, ""}, + {"Credential.Gid", Field, 0, ""}, + {"Credential.Groups", Field, 0, ""}, + {"Credential.NoSetGroups", Field, 9, ""}, + {"Credential.Uid", Field, 0, ""}, + {"CryptAcquireContext", Func, 0, ""}, + {"CryptGenRandom", Func, 0, ""}, + {"CryptReleaseContext", Func, 0, ""}, + {"DIOCBSFLUSH", Const, 1, ""}, + {"DIOCOSFPFLUSH", Const, 1, ""}, + {"DLL", Type, 0, ""}, + {"DLL.Handle", Field, 0, ""}, + {"DLL.Name", Field, 0, ""}, + {"DLLError", Type, 0, ""}, + {"DLLError.Err", Field, 0, ""}, + {"DLLError.Msg", Field, 0, ""}, + {"DLLError.ObjName", Field, 0, ""}, + {"DLT_A429", Const, 0, ""}, + {"DLT_A653_ICM", Const, 0, ""}, + {"DLT_AIRONET_HEADER", Const, 0, ""}, + {"DLT_AOS", Const, 1, ""}, + {"DLT_APPLE_IP_OVER_IEEE1394", Const, 0, ""}, + {"DLT_ARCNET", Const, 0, ""}, + {"DLT_ARCNET_LINUX", Const, 0, ""}, + {"DLT_ATM_CLIP", Const, 0, ""}, + {"DLT_ATM_RFC1483", Const, 0, ""}, + {"DLT_AURORA", Const, 0, ""}, + {"DLT_AX25", Const, 0, ""}, + {"DLT_AX25_KISS", Const, 0, ""}, + {"DLT_BACNET_MS_TP", Const, 0, ""}, + {"DLT_BLUETOOTH_HCI_H4", Const, 0, ""}, + {"DLT_BLUETOOTH_HCI_H4_WITH_PHDR", Const, 0, ""}, + {"DLT_CAN20B", Const, 0, ""}, + {"DLT_CAN_SOCKETCAN", Const, 1, ""}, + {"DLT_CHAOS", Const, 0, ""}, + {"DLT_CHDLC", Const, 0, ""}, + {"DLT_CISCO_IOS", Const, 0, ""}, + {"DLT_C_HDLC", Const, 0, ""}, + {"DLT_C_HDLC_WITH_DIR", Const, 0, ""}, + {"DLT_DBUS", Const, 1, ""}, + {"DLT_DECT", Const, 1, ""}, + {"DLT_DOCSIS", Const, 0, ""}, + {"DLT_DVB_CI", Const, 1, ""}, + {"DLT_ECONET", Const, 0, ""}, + {"DLT_EN10MB", Const, 0, ""}, + {"DLT_EN3MB", Const, 0, ""}, + {"DLT_ENC", Const, 0, ""}, + {"DLT_ERF", Const, 0, ""}, + {"DLT_ERF_ETH", Const, 0, ""}, + {"DLT_ERF_POS", Const, 0, ""}, + {"DLT_FC_2", Const, 1, ""}, + {"DLT_FC_2_WITH_FRAME_DELIMS", Const, 1, ""}, + {"DLT_FDDI", Const, 0, ""}, + {"DLT_FLEXRAY", Const, 0, ""}, + {"DLT_FRELAY", Const, 0, ""}, + {"DLT_FRELAY_WITH_DIR", Const, 0, ""}, + {"DLT_GCOM_SERIAL", Const, 0, ""}, + {"DLT_GCOM_T1E1", Const, 0, ""}, + {"DLT_GPF_F", Const, 0, ""}, + {"DLT_GPF_T", Const, 0, ""}, + {"DLT_GPRS_LLC", Const, 0, ""}, + {"DLT_GSMTAP_ABIS", Const, 1, ""}, + {"DLT_GSMTAP_UM", Const, 1, ""}, + {"DLT_HDLC", Const, 1, ""}, + {"DLT_HHDLC", Const, 0, ""}, + {"DLT_HIPPI", Const, 1, ""}, + {"DLT_IBM_SN", Const, 0, ""}, + {"DLT_IBM_SP", Const, 0, ""}, + {"DLT_IEEE802", Const, 0, ""}, + {"DLT_IEEE802_11", Const, 0, ""}, + {"DLT_IEEE802_11_RADIO", Const, 0, ""}, + {"DLT_IEEE802_11_RADIO_AVS", Const, 0, ""}, + {"DLT_IEEE802_15_4", Const, 0, ""}, + {"DLT_IEEE802_15_4_LINUX", Const, 0, ""}, + {"DLT_IEEE802_15_4_NOFCS", Const, 1, ""}, + {"DLT_IEEE802_15_4_NONASK_PHY", Const, 0, ""}, + {"DLT_IEEE802_16_MAC_CPS", Const, 0, ""}, + {"DLT_IEEE802_16_MAC_CPS_RADIO", Const, 0, ""}, + {"DLT_IPFILTER", Const, 0, ""}, + {"DLT_IPMB", Const, 0, ""}, + {"DLT_IPMB_LINUX", Const, 0, ""}, + {"DLT_IPNET", Const, 1, ""}, + {"DLT_IPOIB", Const, 1, ""}, + {"DLT_IPV4", Const, 1, ""}, + {"DLT_IPV6", Const, 1, ""}, + {"DLT_IP_OVER_FC", Const, 0, ""}, + {"DLT_JUNIPER_ATM1", Const, 0, ""}, + {"DLT_JUNIPER_ATM2", Const, 0, ""}, + {"DLT_JUNIPER_ATM_CEMIC", Const, 1, ""}, + {"DLT_JUNIPER_CHDLC", Const, 0, ""}, + {"DLT_JUNIPER_ES", Const, 0, ""}, + {"DLT_JUNIPER_ETHER", Const, 0, ""}, + {"DLT_JUNIPER_FIBRECHANNEL", Const, 1, ""}, + {"DLT_JUNIPER_FRELAY", Const, 0, ""}, + {"DLT_JUNIPER_GGSN", Const, 0, ""}, + {"DLT_JUNIPER_ISM", Const, 0, ""}, + {"DLT_JUNIPER_MFR", Const, 0, ""}, + {"DLT_JUNIPER_MLFR", Const, 0, ""}, + {"DLT_JUNIPER_MLPPP", Const, 0, ""}, + {"DLT_JUNIPER_MONITOR", Const, 0, ""}, + {"DLT_JUNIPER_PIC_PEER", Const, 0, ""}, + {"DLT_JUNIPER_PPP", Const, 0, ""}, + {"DLT_JUNIPER_PPPOE", Const, 0, ""}, + {"DLT_JUNIPER_PPPOE_ATM", Const, 0, ""}, + {"DLT_JUNIPER_SERVICES", Const, 0, ""}, + {"DLT_JUNIPER_SRX_E2E", Const, 1, ""}, + {"DLT_JUNIPER_ST", Const, 0, ""}, + {"DLT_JUNIPER_VP", Const, 0, ""}, + {"DLT_JUNIPER_VS", Const, 1, ""}, + {"DLT_LAPB_WITH_DIR", Const, 0, ""}, + {"DLT_LAPD", Const, 0, ""}, + {"DLT_LIN", Const, 0, ""}, + {"DLT_LINUX_EVDEV", Const, 1, ""}, + {"DLT_LINUX_IRDA", Const, 0, ""}, + {"DLT_LINUX_LAPD", Const, 0, ""}, + {"DLT_LINUX_PPP_WITHDIRECTION", Const, 0, ""}, + {"DLT_LINUX_SLL", Const, 0, ""}, + {"DLT_LOOP", Const, 0, ""}, + {"DLT_LTALK", Const, 0, ""}, + {"DLT_MATCHING_MAX", Const, 1, ""}, + {"DLT_MATCHING_MIN", Const, 1, ""}, + {"DLT_MFR", Const, 0, ""}, + {"DLT_MOST", Const, 0, ""}, + {"DLT_MPEG_2_TS", Const, 1, ""}, + {"DLT_MPLS", Const, 1, ""}, + {"DLT_MTP2", Const, 0, ""}, + {"DLT_MTP2_WITH_PHDR", Const, 0, ""}, + {"DLT_MTP3", Const, 0, ""}, + {"DLT_MUX27010", Const, 1, ""}, + {"DLT_NETANALYZER", Const, 1, ""}, + {"DLT_NETANALYZER_TRANSPARENT", Const, 1, ""}, + {"DLT_NFC_LLCP", Const, 1, ""}, + {"DLT_NFLOG", Const, 1, ""}, + {"DLT_NG40", Const, 1, ""}, + {"DLT_NULL", Const, 0, ""}, + {"DLT_PCI_EXP", Const, 0, ""}, + {"DLT_PFLOG", Const, 0, ""}, + {"DLT_PFSYNC", Const, 0, ""}, + {"DLT_PPI", Const, 0, ""}, + {"DLT_PPP", Const, 0, ""}, + {"DLT_PPP_BSDOS", Const, 0, ""}, + {"DLT_PPP_ETHER", Const, 0, ""}, + {"DLT_PPP_PPPD", Const, 0, ""}, + {"DLT_PPP_SERIAL", Const, 0, ""}, + {"DLT_PPP_WITH_DIR", Const, 0, ""}, + {"DLT_PPP_WITH_DIRECTION", Const, 0, ""}, + {"DLT_PRISM_HEADER", Const, 0, ""}, + {"DLT_PRONET", Const, 0, ""}, + {"DLT_RAIF1", Const, 0, ""}, + {"DLT_RAW", Const, 0, ""}, + {"DLT_RAWAF_MASK", Const, 1, ""}, + {"DLT_RIO", Const, 0, ""}, + {"DLT_SCCP", Const, 0, ""}, + {"DLT_SITA", Const, 0, ""}, + {"DLT_SLIP", Const, 0, ""}, + {"DLT_SLIP_BSDOS", Const, 0, ""}, + {"DLT_STANAG_5066_D_PDU", Const, 1, ""}, + {"DLT_SUNATM", Const, 0, ""}, + {"DLT_SYMANTEC_FIREWALL", Const, 0, ""}, + {"DLT_TZSP", Const, 0, ""}, + {"DLT_USB", Const, 0, ""}, + {"DLT_USB_LINUX", Const, 0, ""}, + {"DLT_USB_LINUX_MMAPPED", Const, 1, ""}, + {"DLT_USER0", Const, 0, ""}, + {"DLT_USER1", Const, 0, ""}, + {"DLT_USER10", Const, 0, ""}, + {"DLT_USER11", Const, 0, ""}, + {"DLT_USER12", Const, 0, ""}, + {"DLT_USER13", Const, 0, ""}, + {"DLT_USER14", Const, 0, ""}, + {"DLT_USER15", Const, 0, ""}, + {"DLT_USER2", Const, 0, ""}, + {"DLT_USER3", Const, 0, ""}, + {"DLT_USER4", Const, 0, ""}, + {"DLT_USER5", Const, 0, ""}, + {"DLT_USER6", Const, 0, ""}, + {"DLT_USER7", Const, 0, ""}, + {"DLT_USER8", Const, 0, ""}, + {"DLT_USER9", Const, 0, ""}, + {"DLT_WIHART", Const, 1, ""}, + {"DLT_X2E_SERIAL", Const, 0, ""}, + {"DLT_X2E_XORAYA", Const, 0, ""}, + {"DNSMXData", Type, 0, ""}, + {"DNSMXData.NameExchange", Field, 0, ""}, + {"DNSMXData.Pad", Field, 0, ""}, + {"DNSMXData.Preference", Field, 0, ""}, + {"DNSPTRData", Type, 0, ""}, + {"DNSPTRData.Host", Field, 0, ""}, + {"DNSRecord", Type, 0, ""}, + {"DNSRecord.Data", Field, 0, ""}, + {"DNSRecord.Dw", Field, 0, ""}, + {"DNSRecord.Length", Field, 0, ""}, + {"DNSRecord.Name", Field, 0, ""}, + {"DNSRecord.Next", Field, 0, ""}, + {"DNSRecord.Reserved", Field, 0, ""}, + {"DNSRecord.Ttl", Field, 0, ""}, + {"DNSRecord.Type", Field, 0, ""}, + {"DNSSRVData", Type, 0, ""}, + {"DNSSRVData.Pad", Field, 0, ""}, + {"DNSSRVData.Port", Field, 0, ""}, + {"DNSSRVData.Priority", Field, 0, ""}, + {"DNSSRVData.Target", Field, 0, ""}, + {"DNSSRVData.Weight", Field, 0, ""}, + {"DNSTXTData", Type, 0, ""}, + {"DNSTXTData.StringArray", Field, 0, ""}, + {"DNSTXTData.StringCount", Field, 0, ""}, + {"DNS_INFO_NO_RECORDS", Const, 4, ""}, + {"DNS_TYPE_A", Const, 0, ""}, + {"DNS_TYPE_A6", Const, 0, ""}, + {"DNS_TYPE_AAAA", Const, 0, ""}, + {"DNS_TYPE_ADDRS", Const, 0, ""}, + {"DNS_TYPE_AFSDB", Const, 0, ""}, + {"DNS_TYPE_ALL", Const, 0, ""}, + {"DNS_TYPE_ANY", Const, 0, ""}, + {"DNS_TYPE_ATMA", Const, 0, ""}, + {"DNS_TYPE_AXFR", Const, 0, ""}, + {"DNS_TYPE_CERT", Const, 0, ""}, + {"DNS_TYPE_CNAME", Const, 0, ""}, + {"DNS_TYPE_DHCID", Const, 0, ""}, + {"DNS_TYPE_DNAME", Const, 0, ""}, + {"DNS_TYPE_DNSKEY", Const, 0, ""}, + {"DNS_TYPE_DS", Const, 0, ""}, + {"DNS_TYPE_EID", Const, 0, ""}, + {"DNS_TYPE_GID", Const, 0, ""}, + {"DNS_TYPE_GPOS", Const, 0, ""}, + {"DNS_TYPE_HINFO", Const, 0, ""}, + {"DNS_TYPE_ISDN", Const, 0, ""}, + {"DNS_TYPE_IXFR", Const, 0, ""}, + {"DNS_TYPE_KEY", Const, 0, ""}, + {"DNS_TYPE_KX", Const, 0, ""}, + {"DNS_TYPE_LOC", Const, 0, ""}, + {"DNS_TYPE_MAILA", Const, 0, ""}, + {"DNS_TYPE_MAILB", Const, 0, ""}, + {"DNS_TYPE_MB", Const, 0, ""}, + {"DNS_TYPE_MD", Const, 0, ""}, + {"DNS_TYPE_MF", Const, 0, ""}, + {"DNS_TYPE_MG", Const, 0, ""}, + {"DNS_TYPE_MINFO", Const, 0, ""}, + {"DNS_TYPE_MR", Const, 0, ""}, + {"DNS_TYPE_MX", Const, 0, ""}, + {"DNS_TYPE_NAPTR", Const, 0, ""}, + {"DNS_TYPE_NBSTAT", Const, 0, ""}, + {"DNS_TYPE_NIMLOC", Const, 0, ""}, + {"DNS_TYPE_NS", Const, 0, ""}, + {"DNS_TYPE_NSAP", Const, 0, ""}, + {"DNS_TYPE_NSAPPTR", Const, 0, ""}, + {"DNS_TYPE_NSEC", Const, 0, ""}, + {"DNS_TYPE_NULL", Const, 0, ""}, + {"DNS_TYPE_NXT", Const, 0, ""}, + {"DNS_TYPE_OPT", Const, 0, ""}, + {"DNS_TYPE_PTR", Const, 0, ""}, + {"DNS_TYPE_PX", Const, 0, ""}, + {"DNS_TYPE_RP", Const, 0, ""}, + {"DNS_TYPE_RRSIG", Const, 0, ""}, + {"DNS_TYPE_RT", Const, 0, ""}, + {"DNS_TYPE_SIG", Const, 0, ""}, + {"DNS_TYPE_SINK", Const, 0, ""}, + {"DNS_TYPE_SOA", Const, 0, ""}, + {"DNS_TYPE_SRV", Const, 0, ""}, + {"DNS_TYPE_TEXT", Const, 0, ""}, + {"DNS_TYPE_TKEY", Const, 0, ""}, + {"DNS_TYPE_TSIG", Const, 0, ""}, + {"DNS_TYPE_UID", Const, 0, ""}, + {"DNS_TYPE_UINFO", Const, 0, ""}, + {"DNS_TYPE_UNSPEC", Const, 0, ""}, + {"DNS_TYPE_WINS", Const, 0, ""}, + {"DNS_TYPE_WINSR", Const, 0, ""}, + {"DNS_TYPE_WKS", Const, 0, ""}, + {"DNS_TYPE_X25", Const, 0, ""}, + {"DT_BLK", Const, 0, ""}, + {"DT_CHR", Const, 0, ""}, + {"DT_DIR", Const, 0, ""}, + {"DT_FIFO", Const, 0, ""}, + {"DT_LNK", Const, 0, ""}, + {"DT_REG", Const, 0, ""}, + {"DT_SOCK", Const, 0, ""}, + {"DT_UNKNOWN", Const, 0, ""}, + {"DT_WHT", Const, 0, ""}, + {"DUPLICATE_CLOSE_SOURCE", Const, 0, ""}, + {"DUPLICATE_SAME_ACCESS", Const, 0, ""}, + {"DeleteFile", Func, 0, ""}, + {"DetachLsf", Func, 0, "func(fd int) error"}, + {"DeviceIoControl", Func, 4, ""}, + {"Dirent", Type, 0, ""}, + {"Dirent.Fileno", Field, 0, ""}, + {"Dirent.Ino", Field, 0, ""}, + {"Dirent.Name", Field, 0, ""}, + {"Dirent.Namlen", Field, 0, ""}, + {"Dirent.Off", Field, 0, ""}, + {"Dirent.Pad0", Field, 12, ""}, + {"Dirent.Pad1", Field, 12, ""}, + {"Dirent.Pad_cgo_0", Field, 0, ""}, + {"Dirent.Reclen", Field, 0, ""}, + {"Dirent.Seekoff", Field, 0, ""}, + {"Dirent.Type", Field, 0, ""}, + {"Dirent.X__d_padding", Field, 3, ""}, + {"DnsNameCompare", Func, 4, ""}, + {"DnsQuery", Func, 0, ""}, + {"DnsRecordListFree", Func, 0, ""}, + {"DnsSectionAdditional", Const, 4, ""}, + {"DnsSectionAnswer", Const, 4, ""}, + {"DnsSectionAuthority", Const, 4, ""}, + {"DnsSectionQuestion", Const, 4, ""}, + {"Dup", Func, 0, "func(oldfd int) (fd int, err error)"}, + {"Dup2", Func, 0, "func(oldfd int, newfd int) (err error)"}, + {"Dup3", Func, 2, "func(oldfd int, newfd int, flags int) (err error)"}, + {"DuplicateHandle", Func, 0, ""}, + {"E2BIG", Const, 0, ""}, + {"EACCES", Const, 0, ""}, + {"EADDRINUSE", Const, 0, ""}, + {"EADDRNOTAVAIL", Const, 0, ""}, + {"EADV", Const, 0, ""}, + {"EAFNOSUPPORT", Const, 0, ""}, + {"EAGAIN", Const, 0, ""}, + {"EALREADY", Const, 0, ""}, + {"EAUTH", Const, 0, ""}, + {"EBADARCH", Const, 0, ""}, + {"EBADE", Const, 0, ""}, + {"EBADEXEC", Const, 0, ""}, + {"EBADF", Const, 0, ""}, + {"EBADFD", Const, 0, ""}, + {"EBADMACHO", Const, 0, ""}, + {"EBADMSG", Const, 0, ""}, + {"EBADR", Const, 0, ""}, + {"EBADRPC", Const, 0, ""}, + {"EBADRQC", Const, 0, ""}, + {"EBADSLT", Const, 0, ""}, + {"EBFONT", Const, 0, ""}, + {"EBUSY", Const, 0, ""}, + {"ECANCELED", Const, 0, ""}, + {"ECAPMODE", Const, 1, ""}, + {"ECHILD", Const, 0, ""}, + {"ECHO", Const, 0, ""}, + {"ECHOCTL", Const, 0, ""}, + {"ECHOE", Const, 0, ""}, + {"ECHOK", Const, 0, ""}, + {"ECHOKE", Const, 0, ""}, + {"ECHONL", Const, 0, ""}, + {"ECHOPRT", Const, 0, ""}, + {"ECHRNG", Const, 0, ""}, + {"ECOMM", Const, 0, ""}, + {"ECONNABORTED", Const, 0, ""}, + {"ECONNREFUSED", Const, 0, ""}, + {"ECONNRESET", Const, 0, ""}, + {"EDEADLK", Const, 0, ""}, + {"EDEADLOCK", Const, 0, ""}, + {"EDESTADDRREQ", Const, 0, ""}, + {"EDEVERR", Const, 0, ""}, + {"EDOM", Const, 0, ""}, + {"EDOOFUS", Const, 0, ""}, + {"EDOTDOT", Const, 0, ""}, + {"EDQUOT", Const, 0, ""}, + {"EEXIST", Const, 0, ""}, + {"EFAULT", Const, 0, ""}, + {"EFBIG", Const, 0, ""}, + {"EFER_LMA", Const, 1, ""}, + {"EFER_LME", Const, 1, ""}, + {"EFER_NXE", Const, 1, ""}, + {"EFER_SCE", Const, 1, ""}, + {"EFTYPE", Const, 0, ""}, + {"EHOSTDOWN", Const, 0, ""}, + {"EHOSTUNREACH", Const, 0, ""}, + {"EHWPOISON", Const, 0, ""}, + {"EIDRM", Const, 0, ""}, + {"EILSEQ", Const, 0, ""}, + {"EINPROGRESS", Const, 0, ""}, + {"EINTR", Const, 0, ""}, + {"EINVAL", Const, 0, ""}, + {"EIO", Const, 0, ""}, + {"EIPSEC", Const, 1, ""}, + {"EISCONN", Const, 0, ""}, + {"EISDIR", Const, 0, ""}, + {"EISNAM", Const, 0, ""}, + {"EKEYEXPIRED", Const, 0, ""}, + {"EKEYREJECTED", Const, 0, ""}, + {"EKEYREVOKED", Const, 0, ""}, + {"EL2HLT", Const, 0, ""}, + {"EL2NSYNC", Const, 0, ""}, + {"EL3HLT", Const, 0, ""}, + {"EL3RST", Const, 0, ""}, + {"ELAST", Const, 0, ""}, + {"ELF_NGREG", Const, 0, ""}, + {"ELF_PRARGSZ", Const, 0, ""}, + {"ELIBACC", Const, 0, ""}, + {"ELIBBAD", Const, 0, ""}, + {"ELIBEXEC", Const, 0, ""}, + {"ELIBMAX", Const, 0, ""}, + {"ELIBSCN", Const, 0, ""}, + {"ELNRNG", Const, 0, ""}, + {"ELOOP", Const, 0, ""}, + {"EMEDIUMTYPE", Const, 0, ""}, + {"EMFILE", Const, 0, ""}, + {"EMLINK", Const, 0, ""}, + {"EMSGSIZE", Const, 0, ""}, + {"EMT_TAGOVF", Const, 1, ""}, + {"EMULTIHOP", Const, 0, ""}, + {"EMUL_ENABLED", Const, 1, ""}, + {"EMUL_LINUX", Const, 1, ""}, + {"EMUL_LINUX32", Const, 1, ""}, + {"EMUL_MAXID", Const, 1, ""}, + {"EMUL_NATIVE", Const, 1, ""}, + {"ENAMETOOLONG", Const, 0, ""}, + {"ENAVAIL", Const, 0, ""}, + {"ENDRUNDISC", Const, 1, ""}, + {"ENEEDAUTH", Const, 0, ""}, + {"ENETDOWN", Const, 0, ""}, + {"ENETRESET", Const, 0, ""}, + {"ENETUNREACH", Const, 0, ""}, + {"ENFILE", Const, 0, ""}, + {"ENOANO", Const, 0, ""}, + {"ENOATTR", Const, 0, ""}, + {"ENOBUFS", Const, 0, ""}, + {"ENOCSI", Const, 0, ""}, + {"ENODATA", Const, 0, ""}, + {"ENODEV", Const, 0, ""}, + {"ENOENT", Const, 0, ""}, + {"ENOEXEC", Const, 0, ""}, + {"ENOKEY", Const, 0, ""}, + {"ENOLCK", Const, 0, ""}, + {"ENOLINK", Const, 0, ""}, + {"ENOMEDIUM", Const, 0, ""}, + {"ENOMEM", Const, 0, ""}, + {"ENOMSG", Const, 0, ""}, + {"ENONET", Const, 0, ""}, + {"ENOPKG", Const, 0, ""}, + {"ENOPOLICY", Const, 0, ""}, + {"ENOPROTOOPT", Const, 0, ""}, + {"ENOSPC", Const, 0, ""}, + {"ENOSR", Const, 0, ""}, + {"ENOSTR", Const, 0, ""}, + {"ENOSYS", Const, 0, ""}, + {"ENOTBLK", Const, 0, ""}, + {"ENOTCAPABLE", Const, 0, ""}, + {"ENOTCONN", Const, 0, ""}, + {"ENOTDIR", Const, 0, ""}, + {"ENOTEMPTY", Const, 0, ""}, + {"ENOTNAM", Const, 0, ""}, + {"ENOTRECOVERABLE", Const, 0, ""}, + {"ENOTSOCK", Const, 0, ""}, + {"ENOTSUP", Const, 0, ""}, + {"ENOTTY", Const, 0, ""}, + {"ENOTUNIQ", Const, 0, ""}, + {"ENXIO", Const, 0, ""}, + {"EN_SW_CTL_INF", Const, 1, ""}, + {"EN_SW_CTL_PREC", Const, 1, ""}, + {"EN_SW_CTL_ROUND", Const, 1, ""}, + {"EN_SW_DATACHAIN", Const, 1, ""}, + {"EN_SW_DENORM", Const, 1, ""}, + {"EN_SW_INVOP", Const, 1, ""}, + {"EN_SW_OVERFLOW", Const, 1, ""}, + {"EN_SW_PRECLOSS", Const, 1, ""}, + {"EN_SW_UNDERFLOW", Const, 1, ""}, + {"EN_SW_ZERODIV", Const, 1, ""}, + {"EOPNOTSUPP", Const, 0, ""}, + {"EOVERFLOW", Const, 0, ""}, + {"EOWNERDEAD", Const, 0, ""}, + {"EPERM", Const, 0, ""}, + {"EPFNOSUPPORT", Const, 0, ""}, + {"EPIPE", Const, 0, ""}, + {"EPOLLERR", Const, 0, ""}, + {"EPOLLET", Const, 0, ""}, + {"EPOLLHUP", Const, 0, ""}, + {"EPOLLIN", Const, 0, ""}, + {"EPOLLMSG", Const, 0, ""}, + {"EPOLLONESHOT", Const, 0, ""}, + {"EPOLLOUT", Const, 0, ""}, + {"EPOLLPRI", Const, 0, ""}, + {"EPOLLRDBAND", Const, 0, ""}, + {"EPOLLRDHUP", Const, 0, ""}, + {"EPOLLRDNORM", Const, 0, ""}, + {"EPOLLWRBAND", Const, 0, ""}, + {"EPOLLWRNORM", Const, 0, ""}, + {"EPOLL_CLOEXEC", Const, 0, ""}, + {"EPOLL_CTL_ADD", Const, 0, ""}, + {"EPOLL_CTL_DEL", Const, 0, ""}, + {"EPOLL_CTL_MOD", Const, 0, ""}, + {"EPOLL_NONBLOCK", Const, 0, ""}, + {"EPROCLIM", Const, 0, ""}, + {"EPROCUNAVAIL", Const, 0, ""}, + {"EPROGMISMATCH", Const, 0, ""}, + {"EPROGUNAVAIL", Const, 0, ""}, + {"EPROTO", Const, 0, ""}, + {"EPROTONOSUPPORT", Const, 0, ""}, + {"EPROTOTYPE", Const, 0, ""}, + {"EPWROFF", Const, 0, ""}, + {"EQFULL", Const, 16, ""}, + {"ERANGE", Const, 0, ""}, + {"EREMCHG", Const, 0, ""}, + {"EREMOTE", Const, 0, ""}, + {"EREMOTEIO", Const, 0, ""}, + {"ERESTART", Const, 0, ""}, + {"ERFKILL", Const, 0, ""}, + {"EROFS", Const, 0, ""}, + {"ERPCMISMATCH", Const, 0, ""}, + {"ERROR_ACCESS_DENIED", Const, 0, ""}, + {"ERROR_ALREADY_EXISTS", Const, 0, ""}, + {"ERROR_BROKEN_PIPE", Const, 0, ""}, + {"ERROR_BUFFER_OVERFLOW", Const, 0, ""}, + {"ERROR_DIR_NOT_EMPTY", Const, 8, ""}, + {"ERROR_ENVVAR_NOT_FOUND", Const, 0, ""}, + {"ERROR_FILE_EXISTS", Const, 0, ""}, + {"ERROR_FILE_NOT_FOUND", Const, 0, ""}, + {"ERROR_HANDLE_EOF", Const, 2, ""}, + {"ERROR_INSUFFICIENT_BUFFER", Const, 0, ""}, + {"ERROR_IO_PENDING", Const, 0, ""}, + {"ERROR_MOD_NOT_FOUND", Const, 0, ""}, + {"ERROR_MORE_DATA", Const, 3, ""}, + {"ERROR_NETNAME_DELETED", Const, 3, ""}, + {"ERROR_NOT_FOUND", Const, 1, ""}, + {"ERROR_NO_MORE_FILES", Const, 0, ""}, + {"ERROR_OPERATION_ABORTED", Const, 0, ""}, + {"ERROR_PATH_NOT_FOUND", Const, 0, ""}, + {"ERROR_PRIVILEGE_NOT_HELD", Const, 4, ""}, + {"ERROR_PROC_NOT_FOUND", Const, 0, ""}, + {"ESHLIBVERS", Const, 0, ""}, + {"ESHUTDOWN", Const, 0, ""}, + {"ESOCKTNOSUPPORT", Const, 0, ""}, + {"ESPIPE", Const, 0, ""}, + {"ESRCH", Const, 0, ""}, + {"ESRMNT", Const, 0, ""}, + {"ESTALE", Const, 0, ""}, + {"ESTRPIPE", Const, 0, ""}, + {"ETHERCAP_JUMBO_MTU", Const, 1, ""}, + {"ETHERCAP_VLAN_HWTAGGING", Const, 1, ""}, + {"ETHERCAP_VLAN_MTU", Const, 1, ""}, + {"ETHERMIN", Const, 1, ""}, + {"ETHERMTU", Const, 1, ""}, + {"ETHERMTU_JUMBO", Const, 1, ""}, + {"ETHERTYPE_8023", Const, 1, ""}, + {"ETHERTYPE_AARP", Const, 1, ""}, + {"ETHERTYPE_ACCTON", Const, 1, ""}, + {"ETHERTYPE_AEONIC", Const, 1, ""}, + {"ETHERTYPE_ALPHA", Const, 1, ""}, + {"ETHERTYPE_AMBER", Const, 1, ""}, + {"ETHERTYPE_AMOEBA", Const, 1, ""}, + {"ETHERTYPE_AOE", Const, 1, ""}, + {"ETHERTYPE_APOLLO", Const, 1, ""}, + {"ETHERTYPE_APOLLODOMAIN", Const, 1, ""}, + {"ETHERTYPE_APPLETALK", Const, 1, ""}, + {"ETHERTYPE_APPLITEK", Const, 1, ""}, + {"ETHERTYPE_ARGONAUT", Const, 1, ""}, + {"ETHERTYPE_ARP", Const, 1, ""}, + {"ETHERTYPE_AT", Const, 1, ""}, + {"ETHERTYPE_ATALK", Const, 1, ""}, + {"ETHERTYPE_ATOMIC", Const, 1, ""}, + {"ETHERTYPE_ATT", Const, 1, ""}, + {"ETHERTYPE_ATTSTANFORD", Const, 1, ""}, + {"ETHERTYPE_AUTOPHON", Const, 1, ""}, + {"ETHERTYPE_AXIS", Const, 1, ""}, + {"ETHERTYPE_BCLOOP", Const, 1, ""}, + {"ETHERTYPE_BOFL", Const, 1, ""}, + {"ETHERTYPE_CABLETRON", Const, 1, ""}, + {"ETHERTYPE_CHAOS", Const, 1, ""}, + {"ETHERTYPE_COMDESIGN", Const, 1, ""}, + {"ETHERTYPE_COMPUGRAPHIC", Const, 1, ""}, + {"ETHERTYPE_COUNTERPOINT", Const, 1, ""}, + {"ETHERTYPE_CRONUS", Const, 1, ""}, + {"ETHERTYPE_CRONUSVLN", Const, 1, ""}, + {"ETHERTYPE_DCA", Const, 1, ""}, + {"ETHERTYPE_DDE", Const, 1, ""}, + {"ETHERTYPE_DEBNI", Const, 1, ""}, + {"ETHERTYPE_DECAM", Const, 1, ""}, + {"ETHERTYPE_DECCUST", Const, 1, ""}, + {"ETHERTYPE_DECDIAG", Const, 1, ""}, + {"ETHERTYPE_DECDNS", Const, 1, ""}, + {"ETHERTYPE_DECDTS", Const, 1, ""}, + {"ETHERTYPE_DECEXPER", Const, 1, ""}, + {"ETHERTYPE_DECLAST", Const, 1, ""}, + {"ETHERTYPE_DECLTM", Const, 1, ""}, + {"ETHERTYPE_DECMUMPS", Const, 1, ""}, + {"ETHERTYPE_DECNETBIOS", Const, 1, ""}, + {"ETHERTYPE_DELTACON", Const, 1, ""}, + {"ETHERTYPE_DIDDLE", Const, 1, ""}, + {"ETHERTYPE_DLOG1", Const, 1, ""}, + {"ETHERTYPE_DLOG2", Const, 1, ""}, + {"ETHERTYPE_DN", Const, 1, ""}, + {"ETHERTYPE_DOGFIGHT", Const, 1, ""}, + {"ETHERTYPE_DSMD", Const, 1, ""}, + {"ETHERTYPE_ECMA", Const, 1, ""}, + {"ETHERTYPE_ENCRYPT", Const, 1, ""}, + {"ETHERTYPE_ES", Const, 1, ""}, + {"ETHERTYPE_EXCELAN", Const, 1, ""}, + {"ETHERTYPE_EXPERDATA", Const, 1, ""}, + {"ETHERTYPE_FLIP", Const, 1, ""}, + {"ETHERTYPE_FLOWCONTROL", Const, 1, ""}, + {"ETHERTYPE_FRARP", Const, 1, ""}, + {"ETHERTYPE_GENDYN", Const, 1, ""}, + {"ETHERTYPE_HAYES", Const, 1, ""}, + {"ETHERTYPE_HIPPI_FP", Const, 1, ""}, + {"ETHERTYPE_HITACHI", Const, 1, ""}, + {"ETHERTYPE_HP", Const, 1, ""}, + {"ETHERTYPE_IEEEPUP", Const, 1, ""}, + {"ETHERTYPE_IEEEPUPAT", Const, 1, ""}, + {"ETHERTYPE_IMLBL", Const, 1, ""}, + {"ETHERTYPE_IMLBLDIAG", Const, 1, ""}, + {"ETHERTYPE_IP", Const, 1, ""}, + {"ETHERTYPE_IPAS", Const, 1, ""}, + {"ETHERTYPE_IPV6", Const, 1, ""}, + {"ETHERTYPE_IPX", Const, 1, ""}, + {"ETHERTYPE_IPXNEW", Const, 1, ""}, + {"ETHERTYPE_KALPANA", Const, 1, ""}, + {"ETHERTYPE_LANBRIDGE", Const, 1, ""}, + {"ETHERTYPE_LANPROBE", Const, 1, ""}, + {"ETHERTYPE_LAT", Const, 1, ""}, + {"ETHERTYPE_LBACK", Const, 1, ""}, + {"ETHERTYPE_LITTLE", Const, 1, ""}, + {"ETHERTYPE_LLDP", Const, 1, ""}, + {"ETHERTYPE_LOGICRAFT", Const, 1, ""}, + {"ETHERTYPE_LOOPBACK", Const, 1, ""}, + {"ETHERTYPE_MATRA", Const, 1, ""}, + {"ETHERTYPE_MAX", Const, 1, ""}, + {"ETHERTYPE_MERIT", Const, 1, ""}, + {"ETHERTYPE_MICP", Const, 1, ""}, + {"ETHERTYPE_MOPDL", Const, 1, ""}, + {"ETHERTYPE_MOPRC", Const, 1, ""}, + {"ETHERTYPE_MOTOROLA", Const, 1, ""}, + {"ETHERTYPE_MPLS", Const, 1, ""}, + {"ETHERTYPE_MPLS_MCAST", Const, 1, ""}, + {"ETHERTYPE_MUMPS", Const, 1, ""}, + {"ETHERTYPE_NBPCC", Const, 1, ""}, + {"ETHERTYPE_NBPCLAIM", Const, 1, ""}, + {"ETHERTYPE_NBPCLREQ", Const, 1, ""}, + {"ETHERTYPE_NBPCLRSP", Const, 1, ""}, + {"ETHERTYPE_NBPCREQ", Const, 1, ""}, + {"ETHERTYPE_NBPCRSP", Const, 1, ""}, + {"ETHERTYPE_NBPDG", Const, 1, ""}, + {"ETHERTYPE_NBPDGB", Const, 1, ""}, + {"ETHERTYPE_NBPDLTE", Const, 1, ""}, + {"ETHERTYPE_NBPRAR", Const, 1, ""}, + {"ETHERTYPE_NBPRAS", Const, 1, ""}, + {"ETHERTYPE_NBPRST", Const, 1, ""}, + {"ETHERTYPE_NBPSCD", Const, 1, ""}, + {"ETHERTYPE_NBPVCD", Const, 1, ""}, + {"ETHERTYPE_NBS", Const, 1, ""}, + {"ETHERTYPE_NCD", Const, 1, ""}, + {"ETHERTYPE_NESTAR", Const, 1, ""}, + {"ETHERTYPE_NETBEUI", Const, 1, ""}, + {"ETHERTYPE_NOVELL", Const, 1, ""}, + {"ETHERTYPE_NS", Const, 1, ""}, + {"ETHERTYPE_NSAT", Const, 1, ""}, + {"ETHERTYPE_NSCOMPAT", Const, 1, ""}, + {"ETHERTYPE_NTRAILER", Const, 1, ""}, + {"ETHERTYPE_OS9", Const, 1, ""}, + {"ETHERTYPE_OS9NET", Const, 1, ""}, + {"ETHERTYPE_PACER", Const, 1, ""}, + {"ETHERTYPE_PAE", Const, 1, ""}, + {"ETHERTYPE_PCS", Const, 1, ""}, + {"ETHERTYPE_PLANNING", Const, 1, ""}, + {"ETHERTYPE_PPP", Const, 1, ""}, + {"ETHERTYPE_PPPOE", Const, 1, ""}, + {"ETHERTYPE_PPPOEDISC", Const, 1, ""}, + {"ETHERTYPE_PRIMENTS", Const, 1, ""}, + {"ETHERTYPE_PUP", Const, 1, ""}, + {"ETHERTYPE_PUPAT", Const, 1, ""}, + {"ETHERTYPE_QINQ", Const, 1, ""}, + {"ETHERTYPE_RACAL", Const, 1, ""}, + {"ETHERTYPE_RATIONAL", Const, 1, ""}, + {"ETHERTYPE_RAWFR", Const, 1, ""}, + {"ETHERTYPE_RCL", Const, 1, ""}, + {"ETHERTYPE_RDP", Const, 1, ""}, + {"ETHERTYPE_RETIX", Const, 1, ""}, + {"ETHERTYPE_REVARP", Const, 1, ""}, + {"ETHERTYPE_SCA", Const, 1, ""}, + {"ETHERTYPE_SECTRA", Const, 1, ""}, + {"ETHERTYPE_SECUREDATA", Const, 1, ""}, + {"ETHERTYPE_SGITW", Const, 1, ""}, + {"ETHERTYPE_SG_BOUNCE", Const, 1, ""}, + {"ETHERTYPE_SG_DIAG", Const, 1, ""}, + {"ETHERTYPE_SG_NETGAMES", Const, 1, ""}, + {"ETHERTYPE_SG_RESV", Const, 1, ""}, + {"ETHERTYPE_SIMNET", Const, 1, ""}, + {"ETHERTYPE_SLOW", Const, 1, ""}, + {"ETHERTYPE_SLOWPROTOCOLS", Const, 1, ""}, + {"ETHERTYPE_SNA", Const, 1, ""}, + {"ETHERTYPE_SNMP", Const, 1, ""}, + {"ETHERTYPE_SONIX", Const, 1, ""}, + {"ETHERTYPE_SPIDER", Const, 1, ""}, + {"ETHERTYPE_SPRITE", Const, 1, ""}, + {"ETHERTYPE_STP", Const, 1, ""}, + {"ETHERTYPE_TALARIS", Const, 1, ""}, + {"ETHERTYPE_TALARISMC", Const, 1, ""}, + {"ETHERTYPE_TCPCOMP", Const, 1, ""}, + {"ETHERTYPE_TCPSM", Const, 1, ""}, + {"ETHERTYPE_TEC", Const, 1, ""}, + {"ETHERTYPE_TIGAN", Const, 1, ""}, + {"ETHERTYPE_TRAIL", Const, 1, ""}, + {"ETHERTYPE_TRANSETHER", Const, 1, ""}, + {"ETHERTYPE_TYMSHARE", Const, 1, ""}, + {"ETHERTYPE_UBBST", Const, 1, ""}, + {"ETHERTYPE_UBDEBUG", Const, 1, ""}, + {"ETHERTYPE_UBDIAGLOOP", Const, 1, ""}, + {"ETHERTYPE_UBDL", Const, 1, ""}, + {"ETHERTYPE_UBNIU", Const, 1, ""}, + {"ETHERTYPE_UBNMC", Const, 1, ""}, + {"ETHERTYPE_VALID", Const, 1, ""}, + {"ETHERTYPE_VARIAN", Const, 1, ""}, + {"ETHERTYPE_VAXELN", Const, 1, ""}, + {"ETHERTYPE_VEECO", Const, 1, ""}, + {"ETHERTYPE_VEXP", Const, 1, ""}, + {"ETHERTYPE_VGLAB", Const, 1, ""}, + {"ETHERTYPE_VINES", Const, 1, ""}, + {"ETHERTYPE_VINESECHO", Const, 1, ""}, + {"ETHERTYPE_VINESLOOP", Const, 1, ""}, + {"ETHERTYPE_VITAL", Const, 1, ""}, + {"ETHERTYPE_VLAN", Const, 1, ""}, + {"ETHERTYPE_VLTLMAN", Const, 1, ""}, + {"ETHERTYPE_VPROD", Const, 1, ""}, + {"ETHERTYPE_VURESERVED", Const, 1, ""}, + {"ETHERTYPE_WATERLOO", Const, 1, ""}, + {"ETHERTYPE_WELLFLEET", Const, 1, ""}, + {"ETHERTYPE_X25", Const, 1, ""}, + {"ETHERTYPE_X75", Const, 1, ""}, + {"ETHERTYPE_XNSSM", Const, 1, ""}, + {"ETHERTYPE_XTP", Const, 1, ""}, + {"ETHER_ADDR_LEN", Const, 1, ""}, + {"ETHER_ALIGN", Const, 1, ""}, + {"ETHER_CRC_LEN", Const, 1, ""}, + {"ETHER_CRC_POLY_BE", Const, 1, ""}, + {"ETHER_CRC_POLY_LE", Const, 1, ""}, + {"ETHER_HDR_LEN", Const, 1, ""}, + {"ETHER_MAX_DIX_LEN", Const, 1, ""}, + {"ETHER_MAX_LEN", Const, 1, ""}, + {"ETHER_MAX_LEN_JUMBO", Const, 1, ""}, + {"ETHER_MIN_LEN", Const, 1, ""}, + {"ETHER_PPPOE_ENCAP_LEN", Const, 1, ""}, + {"ETHER_TYPE_LEN", Const, 1, ""}, + {"ETHER_VLAN_ENCAP_LEN", Const, 1, ""}, + {"ETH_P_1588", Const, 0, ""}, + {"ETH_P_8021Q", Const, 0, ""}, + {"ETH_P_802_2", Const, 0, ""}, + {"ETH_P_802_3", Const, 0, ""}, + {"ETH_P_AARP", Const, 0, ""}, + {"ETH_P_ALL", Const, 0, ""}, + {"ETH_P_AOE", Const, 0, ""}, + {"ETH_P_ARCNET", Const, 0, ""}, + {"ETH_P_ARP", Const, 0, ""}, + {"ETH_P_ATALK", Const, 0, ""}, + {"ETH_P_ATMFATE", Const, 0, ""}, + {"ETH_P_ATMMPOA", Const, 0, ""}, + {"ETH_P_AX25", Const, 0, ""}, + {"ETH_P_BPQ", Const, 0, ""}, + {"ETH_P_CAIF", Const, 0, ""}, + {"ETH_P_CAN", Const, 0, ""}, + {"ETH_P_CONTROL", Const, 0, ""}, + {"ETH_P_CUST", Const, 0, ""}, + {"ETH_P_DDCMP", Const, 0, ""}, + {"ETH_P_DEC", Const, 0, ""}, + {"ETH_P_DIAG", Const, 0, ""}, + {"ETH_P_DNA_DL", Const, 0, ""}, + {"ETH_P_DNA_RC", Const, 0, ""}, + {"ETH_P_DNA_RT", Const, 0, ""}, + {"ETH_P_DSA", Const, 0, ""}, + {"ETH_P_ECONET", Const, 0, ""}, + {"ETH_P_EDSA", Const, 0, ""}, + {"ETH_P_FCOE", Const, 0, ""}, + {"ETH_P_FIP", Const, 0, ""}, + {"ETH_P_HDLC", Const, 0, ""}, + {"ETH_P_IEEE802154", Const, 0, ""}, + {"ETH_P_IEEEPUP", Const, 0, ""}, + {"ETH_P_IEEEPUPAT", Const, 0, ""}, + {"ETH_P_IP", Const, 0, ""}, + {"ETH_P_IPV6", Const, 0, ""}, + {"ETH_P_IPX", Const, 0, ""}, + {"ETH_P_IRDA", Const, 0, ""}, + {"ETH_P_LAT", Const, 0, ""}, + {"ETH_P_LINK_CTL", Const, 0, ""}, + {"ETH_P_LOCALTALK", Const, 0, ""}, + {"ETH_P_LOOP", Const, 0, ""}, + {"ETH_P_MOBITEX", Const, 0, ""}, + {"ETH_P_MPLS_MC", Const, 0, ""}, + {"ETH_P_MPLS_UC", Const, 0, ""}, + {"ETH_P_PAE", Const, 0, ""}, + {"ETH_P_PAUSE", Const, 0, ""}, + {"ETH_P_PHONET", Const, 0, ""}, + {"ETH_P_PPPTALK", Const, 0, ""}, + {"ETH_P_PPP_DISC", Const, 0, ""}, + {"ETH_P_PPP_MP", Const, 0, ""}, + {"ETH_P_PPP_SES", Const, 0, ""}, + {"ETH_P_PUP", Const, 0, ""}, + {"ETH_P_PUPAT", Const, 0, ""}, + {"ETH_P_RARP", Const, 0, ""}, + {"ETH_P_SCA", Const, 0, ""}, + {"ETH_P_SLOW", Const, 0, ""}, + {"ETH_P_SNAP", Const, 0, ""}, + {"ETH_P_TEB", Const, 0, ""}, + {"ETH_P_TIPC", Const, 0, ""}, + {"ETH_P_TRAILER", Const, 0, ""}, + {"ETH_P_TR_802_2", Const, 0, ""}, + {"ETH_P_WAN_PPP", Const, 0, ""}, + {"ETH_P_WCCP", Const, 0, ""}, + {"ETH_P_X25", Const, 0, ""}, + {"ETIME", Const, 0, ""}, + {"ETIMEDOUT", Const, 0, ""}, + {"ETOOMANYREFS", Const, 0, ""}, + {"ETXTBSY", Const, 0, ""}, + {"EUCLEAN", Const, 0, ""}, + {"EUNATCH", Const, 0, ""}, + {"EUSERS", Const, 0, ""}, + {"EVFILT_AIO", Const, 0, ""}, + {"EVFILT_FS", Const, 0, ""}, + {"EVFILT_LIO", Const, 0, ""}, + {"EVFILT_MACHPORT", Const, 0, ""}, + {"EVFILT_PROC", Const, 0, ""}, + {"EVFILT_READ", Const, 0, ""}, + {"EVFILT_SIGNAL", Const, 0, ""}, + {"EVFILT_SYSCOUNT", Const, 0, ""}, + {"EVFILT_THREADMARKER", Const, 0, ""}, + {"EVFILT_TIMER", Const, 0, ""}, + {"EVFILT_USER", Const, 0, ""}, + {"EVFILT_VM", Const, 0, ""}, + {"EVFILT_VNODE", Const, 0, ""}, + {"EVFILT_WRITE", Const, 0, ""}, + {"EV_ADD", Const, 0, ""}, + {"EV_CLEAR", Const, 0, ""}, + {"EV_DELETE", Const, 0, ""}, + {"EV_DISABLE", Const, 0, ""}, + {"EV_DISPATCH", Const, 0, ""}, + {"EV_DROP", Const, 3, ""}, + {"EV_ENABLE", Const, 0, ""}, + {"EV_EOF", Const, 0, ""}, + {"EV_ERROR", Const, 0, ""}, + {"EV_FLAG0", Const, 0, ""}, + {"EV_FLAG1", Const, 0, ""}, + {"EV_ONESHOT", Const, 0, ""}, + {"EV_OOBAND", Const, 0, ""}, + {"EV_POLL", Const, 0, ""}, + {"EV_RECEIPT", Const, 0, ""}, + {"EV_SYSFLAGS", Const, 0, ""}, + {"EWINDOWS", Const, 0, ""}, + {"EWOULDBLOCK", Const, 0, ""}, + {"EXDEV", Const, 0, ""}, + {"EXFULL", Const, 0, ""}, + {"EXTA", Const, 0, ""}, + {"EXTB", Const, 0, ""}, + {"EXTPROC", Const, 0, ""}, + {"Environ", Func, 0, "func() []string"}, + {"EpollCreate", Func, 0, "func(size int) (fd int, err error)"}, + {"EpollCreate1", Func, 0, "func(flag int) (fd int, err error)"}, + {"EpollCtl", Func, 0, "func(epfd int, op int, fd int, event *EpollEvent) (err error)"}, + {"EpollEvent", Type, 0, ""}, + {"EpollEvent.Events", Field, 0, ""}, + {"EpollEvent.Fd", Field, 0, ""}, + {"EpollEvent.Pad", Field, 0, ""}, + {"EpollEvent.PadFd", Field, 0, ""}, + {"EpollWait", Func, 0, "func(epfd int, events []EpollEvent, msec int) (n int, err error)"}, + {"Errno", Type, 0, ""}, + {"EscapeArg", Func, 0, ""}, + {"Exchangedata", Func, 0, ""}, + {"Exec", Func, 0, "func(argv0 string, argv []string, envv []string) (err error)"}, + {"Exit", Func, 0, "func(code int)"}, + {"ExitProcess", Func, 0, ""}, + {"FD_CLOEXEC", Const, 0, ""}, + {"FD_SETSIZE", Const, 0, ""}, + {"FILE_ACTION_ADDED", Const, 0, ""}, + {"FILE_ACTION_MODIFIED", Const, 0, ""}, + {"FILE_ACTION_REMOVED", Const, 0, ""}, + {"FILE_ACTION_RENAMED_NEW_NAME", Const, 0, ""}, + {"FILE_ACTION_RENAMED_OLD_NAME", Const, 0, ""}, + {"FILE_APPEND_DATA", Const, 0, ""}, + {"FILE_ATTRIBUTE_ARCHIVE", Const, 0, ""}, + {"FILE_ATTRIBUTE_DIRECTORY", Const, 0, ""}, + {"FILE_ATTRIBUTE_HIDDEN", Const, 0, ""}, + {"FILE_ATTRIBUTE_NORMAL", Const, 0, ""}, + {"FILE_ATTRIBUTE_READONLY", Const, 0, ""}, + {"FILE_ATTRIBUTE_REPARSE_POINT", Const, 4, ""}, + {"FILE_ATTRIBUTE_SYSTEM", Const, 0, ""}, + {"FILE_BEGIN", Const, 0, ""}, + {"FILE_CURRENT", Const, 0, ""}, + {"FILE_END", Const, 0, ""}, + {"FILE_FLAG_BACKUP_SEMANTICS", Const, 0, ""}, + {"FILE_FLAG_OPEN_REPARSE_POINT", Const, 4, ""}, + {"FILE_FLAG_OVERLAPPED", Const, 0, ""}, + {"FILE_LIST_DIRECTORY", Const, 0, ""}, + {"FILE_MAP_COPY", Const, 0, ""}, + {"FILE_MAP_EXECUTE", Const, 0, ""}, + {"FILE_MAP_READ", Const, 0, ""}, + {"FILE_MAP_WRITE", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_ATTRIBUTES", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_CREATION", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_DIR_NAME", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_FILE_NAME", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_LAST_ACCESS", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_LAST_WRITE", Const, 0, ""}, + {"FILE_NOTIFY_CHANGE_SIZE", Const, 0, ""}, + {"FILE_SHARE_DELETE", Const, 0, ""}, + {"FILE_SHARE_READ", Const, 0, ""}, + {"FILE_SHARE_WRITE", Const, 0, ""}, + {"FILE_SKIP_COMPLETION_PORT_ON_SUCCESS", Const, 2, ""}, + {"FILE_SKIP_SET_EVENT_ON_HANDLE", Const, 2, ""}, + {"FILE_TYPE_CHAR", Const, 0, ""}, + {"FILE_TYPE_DISK", Const, 0, ""}, + {"FILE_TYPE_PIPE", Const, 0, ""}, + {"FILE_TYPE_REMOTE", Const, 0, ""}, + {"FILE_TYPE_UNKNOWN", Const, 0, ""}, + {"FILE_WRITE_ATTRIBUTES", Const, 0, ""}, + {"FLUSHO", Const, 0, ""}, + {"FORMAT_MESSAGE_ALLOCATE_BUFFER", Const, 0, ""}, + {"FORMAT_MESSAGE_ARGUMENT_ARRAY", Const, 0, ""}, + {"FORMAT_MESSAGE_FROM_HMODULE", Const, 0, ""}, + {"FORMAT_MESSAGE_FROM_STRING", Const, 0, ""}, + {"FORMAT_MESSAGE_FROM_SYSTEM", Const, 0, ""}, + {"FORMAT_MESSAGE_IGNORE_INSERTS", Const, 0, ""}, + {"FORMAT_MESSAGE_MAX_WIDTH_MASK", Const, 0, ""}, + {"FSCTL_GET_REPARSE_POINT", Const, 4, ""}, + {"F_ADDFILESIGS", Const, 0, ""}, + {"F_ADDSIGS", Const, 0, ""}, + {"F_ALLOCATEALL", Const, 0, ""}, + {"F_ALLOCATECONTIG", Const, 0, ""}, + {"F_CANCEL", Const, 0, ""}, + {"F_CHKCLEAN", Const, 0, ""}, + {"F_CLOSEM", Const, 1, ""}, + {"F_DUP2FD", Const, 0, ""}, + {"F_DUP2FD_CLOEXEC", Const, 1, ""}, + {"F_DUPFD", Const, 0, ""}, + {"F_DUPFD_CLOEXEC", Const, 0, ""}, + {"F_EXLCK", Const, 0, ""}, + {"F_FINDSIGS", Const, 16, ""}, + {"F_FLUSH_DATA", Const, 0, ""}, + {"F_FREEZE_FS", Const, 0, ""}, + {"F_FSCTL", Const, 1, ""}, + {"F_FSDIRMASK", Const, 1, ""}, + {"F_FSIN", Const, 1, ""}, + {"F_FSINOUT", Const, 1, ""}, + {"F_FSOUT", Const, 1, ""}, + {"F_FSPRIV", Const, 1, ""}, + {"F_FSVOID", Const, 1, ""}, + {"F_FULLFSYNC", Const, 0, ""}, + {"F_GETCODEDIR", Const, 16, ""}, + {"F_GETFD", Const, 0, ""}, + {"F_GETFL", Const, 0, ""}, + {"F_GETLEASE", Const, 0, ""}, + {"F_GETLK", Const, 0, ""}, + {"F_GETLK64", Const, 0, ""}, + {"F_GETLKPID", Const, 0, ""}, + {"F_GETNOSIGPIPE", Const, 0, ""}, + {"F_GETOWN", Const, 0, ""}, + {"F_GETOWN_EX", Const, 0, ""}, + {"F_GETPATH", Const, 0, ""}, + {"F_GETPATH_MTMINFO", Const, 0, ""}, + {"F_GETPIPE_SZ", Const, 0, ""}, + {"F_GETPROTECTIONCLASS", Const, 0, ""}, + {"F_GETPROTECTIONLEVEL", Const, 16, ""}, + {"F_GETSIG", Const, 0, ""}, + {"F_GLOBAL_NOCACHE", Const, 0, ""}, + {"F_LOCK", Const, 0, ""}, + {"F_LOG2PHYS", Const, 0, ""}, + {"F_LOG2PHYS_EXT", Const, 0, ""}, + {"F_MARKDEPENDENCY", Const, 0, ""}, + {"F_MAXFD", Const, 1, ""}, + {"F_NOCACHE", Const, 0, ""}, + {"F_NODIRECT", Const, 0, ""}, + {"F_NOTIFY", Const, 0, ""}, + {"F_OGETLK", Const, 0, ""}, + {"F_OK", Const, 0, ""}, + {"F_OSETLK", Const, 0, ""}, + {"F_OSETLKW", Const, 0, ""}, + {"F_PARAM_MASK", Const, 1, ""}, + {"F_PARAM_MAX", Const, 1, ""}, + {"F_PATHPKG_CHECK", Const, 0, ""}, + {"F_PEOFPOSMODE", Const, 0, ""}, + {"F_PREALLOCATE", Const, 0, ""}, + {"F_RDADVISE", Const, 0, ""}, + {"F_RDAHEAD", Const, 0, ""}, + {"F_RDLCK", Const, 0, ""}, + {"F_READAHEAD", Const, 0, ""}, + {"F_READBOOTSTRAP", Const, 0, ""}, + {"F_SETBACKINGSTORE", Const, 0, ""}, + {"F_SETFD", Const, 0, ""}, + {"F_SETFL", Const, 0, ""}, + {"F_SETLEASE", Const, 0, ""}, + {"F_SETLK", Const, 0, ""}, + {"F_SETLK64", Const, 0, ""}, + {"F_SETLKW", Const, 0, ""}, + {"F_SETLKW64", Const, 0, ""}, + {"F_SETLKWTIMEOUT", Const, 16, ""}, + {"F_SETLK_REMOTE", Const, 0, ""}, + {"F_SETNOSIGPIPE", Const, 0, ""}, + {"F_SETOWN", Const, 0, ""}, + {"F_SETOWN_EX", Const, 0, ""}, + {"F_SETPIPE_SZ", Const, 0, ""}, + {"F_SETPROTECTIONCLASS", Const, 0, ""}, + {"F_SETSIG", Const, 0, ""}, + {"F_SETSIZE", Const, 0, ""}, + {"F_SHLCK", Const, 0, ""}, + {"F_SINGLE_WRITER", Const, 16, ""}, + {"F_TEST", Const, 0, ""}, + {"F_THAW_FS", Const, 0, ""}, + {"F_TLOCK", Const, 0, ""}, + {"F_TRANSCODEKEY", Const, 16, ""}, + {"F_ULOCK", Const, 0, ""}, + {"F_UNLCK", Const, 0, ""}, + {"F_UNLCKSYS", Const, 0, ""}, + {"F_VOLPOSMODE", Const, 0, ""}, + {"F_WRITEBOOTSTRAP", Const, 0, ""}, + {"F_WRLCK", Const, 0, ""}, + {"Faccessat", Func, 0, "func(dirfd int, path string, mode uint32, flags int) (err error)"}, + {"Fallocate", Func, 0, "func(fd int, mode uint32, off int64, len int64) (err error)"}, + {"Fbootstraptransfer_t", Type, 0, ""}, + {"Fbootstraptransfer_t.Buffer", Field, 0, ""}, + {"Fbootstraptransfer_t.Length", Field, 0, ""}, + {"Fbootstraptransfer_t.Offset", Field, 0, ""}, + {"Fchdir", Func, 0, "func(fd int) (err error)"}, + {"Fchflags", Func, 0, ""}, + {"Fchmod", Func, 0, "func(fd int, mode uint32) (err error)"}, + {"Fchmodat", Func, 0, "func(dirfd int, path string, mode uint32, flags int) error"}, + {"Fchown", Func, 0, "func(fd int, uid int, gid int) (err error)"}, + {"Fchownat", Func, 0, "func(dirfd int, path string, uid int, gid int, flags int) (err error)"}, + {"FcntlFlock", Func, 3, "func(fd uintptr, cmd int, lk *Flock_t) error"}, + {"FdSet", Type, 0, ""}, + {"FdSet.Bits", Field, 0, ""}, + {"FdSet.X__fds_bits", Field, 0, ""}, + {"Fdatasync", Func, 0, "func(fd int) (err error)"}, + {"FileNotifyInformation", Type, 0, ""}, + {"FileNotifyInformation.Action", Field, 0, ""}, + {"FileNotifyInformation.FileName", Field, 0, ""}, + {"FileNotifyInformation.FileNameLength", Field, 0, ""}, + {"FileNotifyInformation.NextEntryOffset", Field, 0, ""}, + {"Filetime", Type, 0, ""}, + {"Filetime.HighDateTime", Field, 0, ""}, + {"Filetime.LowDateTime", Field, 0, ""}, + {"FindClose", Func, 0, ""}, + {"FindFirstFile", Func, 0, ""}, + {"FindNextFile", Func, 0, ""}, + {"Flock", Func, 0, "func(fd int, how int) (err error)"}, + {"Flock_t", Type, 0, ""}, + {"Flock_t.Len", Field, 0, ""}, + {"Flock_t.Pad_cgo_0", Field, 0, ""}, + {"Flock_t.Pad_cgo_1", Field, 3, ""}, + {"Flock_t.Pid", Field, 0, ""}, + {"Flock_t.Start", Field, 0, ""}, + {"Flock_t.Sysid", Field, 0, ""}, + {"Flock_t.Type", Field, 0, ""}, + {"Flock_t.Whence", Field, 0, ""}, + {"FlushBpf", Func, 0, ""}, + {"FlushFileBuffers", Func, 0, ""}, + {"FlushViewOfFile", Func, 0, ""}, + {"ForkExec", Func, 0, "func(argv0 string, argv []string, attr *ProcAttr) (pid int, err error)"}, + {"ForkLock", Var, 0, ""}, + {"FormatMessage", Func, 0, ""}, + {"Fpathconf", Func, 0, ""}, + {"FreeAddrInfoW", Func, 1, ""}, + {"FreeEnvironmentStrings", Func, 0, ""}, + {"FreeLibrary", Func, 0, ""}, + {"Fsid", Type, 0, ""}, + {"Fsid.Val", Field, 0, ""}, + {"Fsid.X__fsid_val", Field, 2, ""}, + {"Fsid.X__val", Field, 0, ""}, + {"Fstat", Func, 0, "func(fd int, stat *Stat_t) (err error)"}, + {"Fstatat", Func, 12, ""}, + {"Fstatfs", Func, 0, "func(fd int, buf *Statfs_t) (err error)"}, + {"Fstore_t", Type, 0, ""}, + {"Fstore_t.Bytesalloc", Field, 0, ""}, + {"Fstore_t.Flags", Field, 0, ""}, + {"Fstore_t.Length", Field, 0, ""}, + {"Fstore_t.Offset", Field, 0, ""}, + {"Fstore_t.Posmode", Field, 0, ""}, + {"Fsync", Func, 0, "func(fd int) (err error)"}, + {"Ftruncate", Func, 0, "func(fd int, length int64) (err error)"}, + {"FullPath", Func, 4, ""}, + {"Futimes", Func, 0, "func(fd int, tv []Timeval) (err error)"}, + {"Futimesat", Func, 0, "func(dirfd int, path string, tv []Timeval) (err error)"}, + {"GENERIC_ALL", Const, 0, ""}, + {"GENERIC_EXECUTE", Const, 0, ""}, + {"GENERIC_READ", Const, 0, ""}, + {"GENERIC_WRITE", Const, 0, ""}, + {"GUID", Type, 1, ""}, + {"GUID.Data1", Field, 1, ""}, + {"GUID.Data2", Field, 1, ""}, + {"GUID.Data3", Field, 1, ""}, + {"GUID.Data4", Field, 1, ""}, + {"GetAcceptExSockaddrs", Func, 0, ""}, + {"GetAdaptersInfo", Func, 0, ""}, + {"GetAddrInfoW", Func, 1, ""}, + {"GetCommandLine", Func, 0, ""}, + {"GetComputerName", Func, 0, ""}, + {"GetConsoleMode", Func, 1, ""}, + {"GetCurrentDirectory", Func, 0, ""}, + {"GetCurrentProcess", Func, 0, ""}, + {"GetEnvironmentStrings", Func, 0, ""}, + {"GetEnvironmentVariable", Func, 0, ""}, + {"GetExitCodeProcess", Func, 0, ""}, + {"GetFileAttributes", Func, 0, ""}, + {"GetFileAttributesEx", Func, 0, ""}, + {"GetFileExInfoStandard", Const, 0, ""}, + {"GetFileExMaxInfoLevel", Const, 0, ""}, + {"GetFileInformationByHandle", Func, 0, ""}, + {"GetFileType", Func, 0, ""}, + {"GetFullPathName", Func, 0, ""}, + {"GetHostByName", Func, 0, ""}, + {"GetIfEntry", Func, 0, ""}, + {"GetLastError", Func, 0, ""}, + {"GetLengthSid", Func, 0, ""}, + {"GetLongPathName", Func, 0, ""}, + {"GetProcAddress", Func, 0, ""}, + {"GetProcessTimes", Func, 0, ""}, + {"GetProtoByName", Func, 0, ""}, + {"GetQueuedCompletionStatus", Func, 0, ""}, + {"GetServByName", Func, 0, ""}, + {"GetShortPathName", Func, 0, ""}, + {"GetStartupInfo", Func, 0, ""}, + {"GetStdHandle", Func, 0, ""}, + {"GetSystemTimeAsFileTime", Func, 0, ""}, + {"GetTempPath", Func, 0, ""}, + {"GetTimeZoneInformation", Func, 0, ""}, + {"GetTokenInformation", Func, 0, ""}, + {"GetUserNameEx", Func, 0, ""}, + {"GetUserProfileDirectory", Func, 0, ""}, + {"GetVersion", Func, 0, ""}, + {"Getcwd", Func, 0, "func(buf []byte) (n int, err error)"}, + {"Getdents", Func, 0, "func(fd int, buf []byte) (n int, err error)"}, + {"Getdirentries", Func, 0, ""}, + {"Getdtablesize", Func, 0, ""}, + {"Getegid", Func, 0, "func() (egid int)"}, + {"Getenv", Func, 0, "func(key string) (value string, found bool)"}, + {"Geteuid", Func, 0, "func() (euid int)"}, + {"Getfsstat", Func, 0, ""}, + {"Getgid", Func, 0, "func() (gid int)"}, + {"Getgroups", Func, 0, "func() (gids []int, err error)"}, + {"Getpagesize", Func, 0, "func() int"}, + {"Getpeername", Func, 0, "func(fd int) (sa Sockaddr, err error)"}, + {"Getpgid", Func, 0, "func(pid int) (pgid int, err error)"}, + {"Getpgrp", Func, 0, "func() (pid int)"}, + {"Getpid", Func, 0, "func() (pid int)"}, + {"Getppid", Func, 0, "func() (ppid int)"}, + {"Getpriority", Func, 0, "func(which int, who int) (prio int, err error)"}, + {"Getrlimit", Func, 0, "func(resource int, rlim *Rlimit) (err error)"}, + {"Getrusage", Func, 0, "func(who int, rusage *Rusage) (err error)"}, + {"Getsid", Func, 0, ""}, + {"Getsockname", Func, 0, "func(fd int) (sa Sockaddr, err error)"}, + {"Getsockopt", Func, 1, ""}, + {"GetsockoptByte", Func, 0, ""}, + {"GetsockoptICMPv6Filter", Func, 2, "func(fd int, level int, opt int) (*ICMPv6Filter, error)"}, + {"GetsockoptIPMreq", Func, 0, "func(fd int, level int, opt int) (*IPMreq, error)"}, + {"GetsockoptIPMreqn", Func, 0, "func(fd int, level int, opt int) (*IPMreqn, error)"}, + {"GetsockoptIPv6MTUInfo", Func, 2, "func(fd int, level int, opt int) (*IPv6MTUInfo, error)"}, + {"GetsockoptIPv6Mreq", Func, 0, "func(fd int, level int, opt int) (*IPv6Mreq, error)"}, + {"GetsockoptInet4Addr", Func, 0, "func(fd int, level int, opt int) (value [4]byte, err error)"}, + {"GetsockoptInt", Func, 0, "func(fd int, level int, opt int) (value int, err error)"}, + {"GetsockoptUcred", Func, 1, "func(fd int, level int, opt int) (*Ucred, error)"}, + {"Gettid", Func, 0, "func() (tid int)"}, + {"Gettimeofday", Func, 0, "func(tv *Timeval) (err error)"}, + {"Getuid", Func, 0, "func() (uid int)"}, + {"Getwd", Func, 0, "func() (wd string, err error)"}, + {"Getxattr", Func, 1, "func(path string, attr string, dest []byte) (sz int, err error)"}, + {"HANDLE_FLAG_INHERIT", Const, 0, ""}, + {"HKEY_CLASSES_ROOT", Const, 0, ""}, + {"HKEY_CURRENT_CONFIG", Const, 0, ""}, + {"HKEY_CURRENT_USER", Const, 0, ""}, + {"HKEY_DYN_DATA", Const, 0, ""}, + {"HKEY_LOCAL_MACHINE", Const, 0, ""}, + {"HKEY_PERFORMANCE_DATA", Const, 0, ""}, + {"HKEY_USERS", Const, 0, ""}, + {"HUPCL", Const, 0, ""}, + {"Handle", Type, 0, ""}, + {"Hostent", Type, 0, ""}, + {"Hostent.AddrList", Field, 0, ""}, + {"Hostent.AddrType", Field, 0, ""}, + {"Hostent.Aliases", Field, 0, ""}, + {"Hostent.Length", Field, 0, ""}, + {"Hostent.Name", Field, 0, ""}, + {"ICANON", Const, 0, ""}, + {"ICMP6_FILTER", Const, 2, ""}, + {"ICMPV6_FILTER", Const, 2, ""}, + {"ICMPv6Filter", Type, 2, ""}, + {"ICMPv6Filter.Data", Field, 2, ""}, + {"ICMPv6Filter.Filt", Field, 2, ""}, + {"ICRNL", Const, 0, ""}, + {"IEXTEN", Const, 0, ""}, + {"IFAN_ARRIVAL", Const, 1, ""}, + {"IFAN_DEPARTURE", Const, 1, ""}, + {"IFA_ADDRESS", Const, 0, ""}, + {"IFA_ANYCAST", Const, 0, ""}, + {"IFA_BROADCAST", Const, 0, ""}, + {"IFA_CACHEINFO", Const, 0, ""}, + {"IFA_F_DADFAILED", Const, 0, ""}, + {"IFA_F_DEPRECATED", Const, 0, ""}, + {"IFA_F_HOMEADDRESS", Const, 0, ""}, + {"IFA_F_NODAD", Const, 0, ""}, + {"IFA_F_OPTIMISTIC", Const, 0, ""}, + {"IFA_F_PERMANENT", Const, 0, ""}, + {"IFA_F_SECONDARY", Const, 0, ""}, + {"IFA_F_TEMPORARY", Const, 0, ""}, + {"IFA_F_TENTATIVE", Const, 0, ""}, + {"IFA_LABEL", Const, 0, ""}, + {"IFA_LOCAL", Const, 0, ""}, + {"IFA_MAX", Const, 0, ""}, + {"IFA_MULTICAST", Const, 0, ""}, + {"IFA_ROUTE", Const, 1, ""}, + {"IFA_UNSPEC", Const, 0, ""}, + {"IFF_ALLMULTI", Const, 0, ""}, + {"IFF_ALTPHYS", Const, 0, ""}, + {"IFF_AUTOMEDIA", Const, 0, ""}, + {"IFF_BROADCAST", Const, 0, ""}, + {"IFF_CANTCHANGE", Const, 0, ""}, + {"IFF_CANTCONFIG", Const, 1, ""}, + {"IFF_DEBUG", Const, 0, ""}, + {"IFF_DRV_OACTIVE", Const, 0, ""}, + {"IFF_DRV_RUNNING", Const, 0, ""}, + {"IFF_DYING", Const, 0, ""}, + {"IFF_DYNAMIC", Const, 0, ""}, + {"IFF_LINK0", Const, 0, ""}, + {"IFF_LINK1", Const, 0, ""}, + {"IFF_LINK2", Const, 0, ""}, + {"IFF_LOOPBACK", Const, 0, ""}, + {"IFF_MASTER", Const, 0, ""}, + {"IFF_MONITOR", Const, 0, ""}, + {"IFF_MULTICAST", Const, 0, ""}, + {"IFF_NOARP", Const, 0, ""}, + {"IFF_NOTRAILERS", Const, 0, ""}, + {"IFF_NO_PI", Const, 0, ""}, + {"IFF_OACTIVE", Const, 0, ""}, + {"IFF_ONE_QUEUE", Const, 0, ""}, + {"IFF_POINTOPOINT", Const, 0, ""}, + {"IFF_POINTTOPOINT", Const, 0, ""}, + {"IFF_PORTSEL", Const, 0, ""}, + {"IFF_PPROMISC", Const, 0, ""}, + {"IFF_PROMISC", Const, 0, ""}, + {"IFF_RENAMING", Const, 0, ""}, + {"IFF_RUNNING", Const, 0, ""}, + {"IFF_SIMPLEX", Const, 0, ""}, + {"IFF_SLAVE", Const, 0, ""}, + {"IFF_SMART", Const, 0, ""}, + {"IFF_STATICARP", Const, 0, ""}, + {"IFF_TAP", Const, 0, ""}, + {"IFF_TUN", Const, 0, ""}, + {"IFF_TUN_EXCL", Const, 0, ""}, + {"IFF_UP", Const, 0, ""}, + {"IFF_VNET_HDR", Const, 0, ""}, + {"IFLA_ADDRESS", Const, 0, ""}, + {"IFLA_BROADCAST", Const, 0, ""}, + {"IFLA_COST", Const, 0, ""}, + {"IFLA_IFALIAS", Const, 0, ""}, + {"IFLA_IFNAME", Const, 0, ""}, + {"IFLA_LINK", Const, 0, ""}, + {"IFLA_LINKINFO", Const, 0, ""}, + {"IFLA_LINKMODE", Const, 0, ""}, + {"IFLA_MAP", Const, 0, ""}, + {"IFLA_MASTER", Const, 0, ""}, + {"IFLA_MAX", Const, 0, ""}, + {"IFLA_MTU", Const, 0, ""}, + {"IFLA_NET_NS_PID", Const, 0, ""}, + {"IFLA_OPERSTATE", Const, 0, ""}, + {"IFLA_PRIORITY", Const, 0, ""}, + {"IFLA_PROTINFO", Const, 0, ""}, + {"IFLA_QDISC", Const, 0, ""}, + {"IFLA_STATS", Const, 0, ""}, + {"IFLA_TXQLEN", Const, 0, ""}, + {"IFLA_UNSPEC", Const, 0, ""}, + {"IFLA_WEIGHT", Const, 0, ""}, + {"IFLA_WIRELESS", Const, 0, ""}, + {"IFNAMSIZ", Const, 0, ""}, + {"IFT_1822", Const, 0, ""}, + {"IFT_A12MPPSWITCH", Const, 0, ""}, + {"IFT_AAL2", Const, 0, ""}, + {"IFT_AAL5", Const, 0, ""}, + {"IFT_ADSL", Const, 0, ""}, + {"IFT_AFLANE8023", Const, 0, ""}, + {"IFT_AFLANE8025", Const, 0, ""}, + {"IFT_ARAP", Const, 0, ""}, + {"IFT_ARCNET", Const, 0, ""}, + {"IFT_ARCNETPLUS", Const, 0, ""}, + {"IFT_ASYNC", Const, 0, ""}, + {"IFT_ATM", Const, 0, ""}, + {"IFT_ATMDXI", Const, 0, ""}, + {"IFT_ATMFUNI", Const, 0, ""}, + {"IFT_ATMIMA", Const, 0, ""}, + {"IFT_ATMLOGICAL", Const, 0, ""}, + {"IFT_ATMRADIO", Const, 0, ""}, + {"IFT_ATMSUBINTERFACE", Const, 0, ""}, + {"IFT_ATMVCIENDPT", Const, 0, ""}, + {"IFT_ATMVIRTUAL", Const, 0, ""}, + {"IFT_BGPPOLICYACCOUNTING", Const, 0, ""}, + {"IFT_BLUETOOTH", Const, 1, ""}, + {"IFT_BRIDGE", Const, 0, ""}, + {"IFT_BSC", Const, 0, ""}, + {"IFT_CARP", Const, 0, ""}, + {"IFT_CCTEMUL", Const, 0, ""}, + {"IFT_CELLULAR", Const, 0, ""}, + {"IFT_CEPT", Const, 0, ""}, + {"IFT_CES", Const, 0, ""}, + {"IFT_CHANNEL", Const, 0, ""}, + {"IFT_CNR", Const, 0, ""}, + {"IFT_COFFEE", Const, 0, ""}, + {"IFT_COMPOSITELINK", Const, 0, ""}, + {"IFT_DCN", Const, 0, ""}, + {"IFT_DIGITALPOWERLINE", Const, 0, ""}, + {"IFT_DIGITALWRAPPEROVERHEADCHANNEL", Const, 0, ""}, + {"IFT_DLSW", Const, 0, ""}, + {"IFT_DOCSCABLEDOWNSTREAM", Const, 0, ""}, + {"IFT_DOCSCABLEMACLAYER", Const, 0, ""}, + {"IFT_DOCSCABLEUPSTREAM", Const, 0, ""}, + {"IFT_DOCSCABLEUPSTREAMCHANNEL", Const, 1, ""}, + {"IFT_DS0", Const, 0, ""}, + {"IFT_DS0BUNDLE", Const, 0, ""}, + {"IFT_DS1FDL", Const, 0, ""}, + {"IFT_DS3", Const, 0, ""}, + {"IFT_DTM", Const, 0, ""}, + {"IFT_DUMMY", Const, 1, ""}, + {"IFT_DVBASILN", Const, 0, ""}, + {"IFT_DVBASIOUT", Const, 0, ""}, + {"IFT_DVBRCCDOWNSTREAM", Const, 0, ""}, + {"IFT_DVBRCCMACLAYER", Const, 0, ""}, + {"IFT_DVBRCCUPSTREAM", Const, 0, ""}, + {"IFT_ECONET", Const, 1, ""}, + {"IFT_ENC", Const, 0, ""}, + {"IFT_EON", Const, 0, ""}, + {"IFT_EPLRS", Const, 0, ""}, + {"IFT_ESCON", Const, 0, ""}, + {"IFT_ETHER", Const, 0, ""}, + {"IFT_FAITH", Const, 0, ""}, + {"IFT_FAST", Const, 0, ""}, + {"IFT_FASTETHER", Const, 0, ""}, + {"IFT_FASTETHERFX", Const, 0, ""}, + {"IFT_FDDI", Const, 0, ""}, + {"IFT_FIBRECHANNEL", Const, 0, ""}, + {"IFT_FRAMERELAYINTERCONNECT", Const, 0, ""}, + {"IFT_FRAMERELAYMPI", Const, 0, ""}, + {"IFT_FRDLCIENDPT", Const, 0, ""}, + {"IFT_FRELAY", Const, 0, ""}, + {"IFT_FRELAYDCE", Const, 0, ""}, + {"IFT_FRF16MFRBUNDLE", Const, 0, ""}, + {"IFT_FRFORWARD", Const, 0, ""}, + {"IFT_G703AT2MB", Const, 0, ""}, + {"IFT_G703AT64K", Const, 0, ""}, + {"IFT_GIF", Const, 0, ""}, + {"IFT_GIGABITETHERNET", Const, 0, ""}, + {"IFT_GR303IDT", Const, 0, ""}, + {"IFT_GR303RDT", Const, 0, ""}, + {"IFT_H323GATEKEEPER", Const, 0, ""}, + {"IFT_H323PROXY", Const, 0, ""}, + {"IFT_HDH1822", Const, 0, ""}, + {"IFT_HDLC", Const, 0, ""}, + {"IFT_HDSL2", Const, 0, ""}, + {"IFT_HIPERLAN2", Const, 0, ""}, + {"IFT_HIPPI", Const, 0, ""}, + {"IFT_HIPPIINTERFACE", Const, 0, ""}, + {"IFT_HOSTPAD", Const, 0, ""}, + {"IFT_HSSI", Const, 0, ""}, + {"IFT_HY", Const, 0, ""}, + {"IFT_IBM370PARCHAN", Const, 0, ""}, + {"IFT_IDSL", Const, 0, ""}, + {"IFT_IEEE1394", Const, 0, ""}, + {"IFT_IEEE80211", Const, 0, ""}, + {"IFT_IEEE80212", Const, 0, ""}, + {"IFT_IEEE8023ADLAG", Const, 0, ""}, + {"IFT_IFGSN", Const, 0, ""}, + {"IFT_IMT", Const, 0, ""}, + {"IFT_INFINIBAND", Const, 1, ""}, + {"IFT_INTERLEAVE", Const, 0, ""}, + {"IFT_IP", Const, 0, ""}, + {"IFT_IPFORWARD", Const, 0, ""}, + {"IFT_IPOVERATM", Const, 0, ""}, + {"IFT_IPOVERCDLC", Const, 0, ""}, + {"IFT_IPOVERCLAW", Const, 0, ""}, + {"IFT_IPSWITCH", Const, 0, ""}, + {"IFT_IPXIP", Const, 0, ""}, + {"IFT_ISDN", Const, 0, ""}, + {"IFT_ISDNBASIC", Const, 0, ""}, + {"IFT_ISDNPRIMARY", Const, 0, ""}, + {"IFT_ISDNS", Const, 0, ""}, + {"IFT_ISDNU", Const, 0, ""}, + {"IFT_ISO88022LLC", Const, 0, ""}, + {"IFT_ISO88023", Const, 0, ""}, + {"IFT_ISO88024", Const, 0, ""}, + {"IFT_ISO88025", Const, 0, ""}, + {"IFT_ISO88025CRFPINT", Const, 0, ""}, + {"IFT_ISO88025DTR", Const, 0, ""}, + {"IFT_ISO88025FIBER", Const, 0, ""}, + {"IFT_ISO88026", Const, 0, ""}, + {"IFT_ISUP", Const, 0, ""}, + {"IFT_L2VLAN", Const, 0, ""}, + {"IFT_L3IPVLAN", Const, 0, ""}, + {"IFT_L3IPXVLAN", Const, 0, ""}, + {"IFT_LAPB", Const, 0, ""}, + {"IFT_LAPD", Const, 0, ""}, + {"IFT_LAPF", Const, 0, ""}, + {"IFT_LINEGROUP", Const, 1, ""}, + {"IFT_LOCALTALK", Const, 0, ""}, + {"IFT_LOOP", Const, 0, ""}, + {"IFT_MEDIAMAILOVERIP", Const, 0, ""}, + {"IFT_MFSIGLINK", Const, 0, ""}, + {"IFT_MIOX25", Const, 0, ""}, + {"IFT_MODEM", Const, 0, ""}, + {"IFT_MPC", Const, 0, ""}, + {"IFT_MPLS", Const, 0, ""}, + {"IFT_MPLSTUNNEL", Const, 0, ""}, + {"IFT_MSDSL", Const, 0, ""}, + {"IFT_MVL", Const, 0, ""}, + {"IFT_MYRINET", Const, 0, ""}, + {"IFT_NFAS", Const, 0, ""}, + {"IFT_NSIP", Const, 0, ""}, + {"IFT_OPTICALCHANNEL", Const, 0, ""}, + {"IFT_OPTICALTRANSPORT", Const, 0, ""}, + {"IFT_OTHER", Const, 0, ""}, + {"IFT_P10", Const, 0, ""}, + {"IFT_P80", Const, 0, ""}, + {"IFT_PARA", Const, 0, ""}, + {"IFT_PDP", Const, 0, ""}, + {"IFT_PFLOG", Const, 0, ""}, + {"IFT_PFLOW", Const, 1, ""}, + {"IFT_PFSYNC", Const, 0, ""}, + {"IFT_PLC", Const, 0, ""}, + {"IFT_PON155", Const, 1, ""}, + {"IFT_PON622", Const, 1, ""}, + {"IFT_POS", Const, 0, ""}, + {"IFT_PPP", Const, 0, ""}, + {"IFT_PPPMULTILINKBUNDLE", Const, 0, ""}, + {"IFT_PROPATM", Const, 1, ""}, + {"IFT_PROPBWAP2MP", Const, 0, ""}, + {"IFT_PROPCNLS", Const, 0, ""}, + {"IFT_PROPDOCSWIRELESSDOWNSTREAM", Const, 0, ""}, + {"IFT_PROPDOCSWIRELESSMACLAYER", Const, 0, ""}, + {"IFT_PROPDOCSWIRELESSUPSTREAM", Const, 0, ""}, + {"IFT_PROPMUX", Const, 0, ""}, + {"IFT_PROPVIRTUAL", Const, 0, ""}, + {"IFT_PROPWIRELESSP2P", Const, 0, ""}, + {"IFT_PTPSERIAL", Const, 0, ""}, + {"IFT_PVC", Const, 0, ""}, + {"IFT_Q2931", Const, 1, ""}, + {"IFT_QLLC", Const, 0, ""}, + {"IFT_RADIOMAC", Const, 0, ""}, + {"IFT_RADSL", Const, 0, ""}, + {"IFT_REACHDSL", Const, 0, ""}, + {"IFT_RFC1483", Const, 0, ""}, + {"IFT_RS232", Const, 0, ""}, + {"IFT_RSRB", Const, 0, ""}, + {"IFT_SDLC", Const, 0, ""}, + {"IFT_SDSL", Const, 0, ""}, + {"IFT_SHDSL", Const, 0, ""}, + {"IFT_SIP", Const, 0, ""}, + {"IFT_SIPSIG", Const, 1, ""}, + {"IFT_SIPTG", Const, 1, ""}, + {"IFT_SLIP", Const, 0, ""}, + {"IFT_SMDSDXI", Const, 0, ""}, + {"IFT_SMDSICIP", Const, 0, ""}, + {"IFT_SONET", Const, 0, ""}, + {"IFT_SONETOVERHEADCHANNEL", Const, 0, ""}, + {"IFT_SONETPATH", Const, 0, ""}, + {"IFT_SONETVT", Const, 0, ""}, + {"IFT_SRP", Const, 0, ""}, + {"IFT_SS7SIGLINK", Const, 0, ""}, + {"IFT_STACKTOSTACK", Const, 0, ""}, + {"IFT_STARLAN", Const, 0, ""}, + {"IFT_STF", Const, 0, ""}, + {"IFT_T1", Const, 0, ""}, + {"IFT_TDLC", Const, 0, ""}, + {"IFT_TELINK", Const, 1, ""}, + {"IFT_TERMPAD", Const, 0, ""}, + {"IFT_TR008", Const, 0, ""}, + {"IFT_TRANSPHDLC", Const, 0, ""}, + {"IFT_TUNNEL", Const, 0, ""}, + {"IFT_ULTRA", Const, 0, ""}, + {"IFT_USB", Const, 0, ""}, + {"IFT_V11", Const, 0, ""}, + {"IFT_V35", Const, 0, ""}, + {"IFT_V36", Const, 0, ""}, + {"IFT_V37", Const, 0, ""}, + {"IFT_VDSL", Const, 0, ""}, + {"IFT_VIRTUALIPADDRESS", Const, 0, ""}, + {"IFT_VIRTUALTG", Const, 1, ""}, + {"IFT_VOICEDID", Const, 1, ""}, + {"IFT_VOICEEM", Const, 0, ""}, + {"IFT_VOICEEMFGD", Const, 1, ""}, + {"IFT_VOICEENCAP", Const, 0, ""}, + {"IFT_VOICEFGDEANA", Const, 1, ""}, + {"IFT_VOICEFXO", Const, 0, ""}, + {"IFT_VOICEFXS", Const, 0, ""}, + {"IFT_VOICEOVERATM", Const, 0, ""}, + {"IFT_VOICEOVERCABLE", Const, 1, ""}, + {"IFT_VOICEOVERFRAMERELAY", Const, 0, ""}, + {"IFT_VOICEOVERIP", Const, 0, ""}, + {"IFT_X213", Const, 0, ""}, + {"IFT_X25", Const, 0, ""}, + {"IFT_X25DDN", Const, 0, ""}, + {"IFT_X25HUNTGROUP", Const, 0, ""}, + {"IFT_X25MLP", Const, 0, ""}, + {"IFT_X25PLE", Const, 0, ""}, + {"IFT_XETHER", Const, 0, ""}, + {"IGNBRK", Const, 0, ""}, + {"IGNCR", Const, 0, ""}, + {"IGNORE", Const, 0, ""}, + {"IGNPAR", Const, 0, ""}, + {"IMAXBEL", Const, 0, ""}, + {"INFINITE", Const, 0, ""}, + {"INLCR", Const, 0, ""}, + {"INPCK", Const, 0, ""}, + {"INVALID_FILE_ATTRIBUTES", Const, 0, ""}, + {"IN_ACCESS", Const, 0, ""}, + {"IN_ALL_EVENTS", Const, 0, ""}, + {"IN_ATTRIB", Const, 0, ""}, + {"IN_CLASSA_HOST", Const, 0, ""}, + {"IN_CLASSA_MAX", Const, 0, ""}, + {"IN_CLASSA_NET", Const, 0, ""}, + {"IN_CLASSA_NSHIFT", Const, 0, ""}, + {"IN_CLASSB_HOST", Const, 0, ""}, + {"IN_CLASSB_MAX", Const, 0, ""}, + {"IN_CLASSB_NET", Const, 0, ""}, + {"IN_CLASSB_NSHIFT", Const, 0, ""}, + {"IN_CLASSC_HOST", Const, 0, ""}, + {"IN_CLASSC_NET", Const, 0, ""}, + {"IN_CLASSC_NSHIFT", Const, 0, ""}, + {"IN_CLASSD_HOST", Const, 0, ""}, + {"IN_CLASSD_NET", Const, 0, ""}, + {"IN_CLASSD_NSHIFT", Const, 0, ""}, + {"IN_CLOEXEC", Const, 0, ""}, + {"IN_CLOSE", Const, 0, ""}, + {"IN_CLOSE_NOWRITE", Const, 0, ""}, + {"IN_CLOSE_WRITE", Const, 0, ""}, + {"IN_CREATE", Const, 0, ""}, + {"IN_DELETE", Const, 0, ""}, + {"IN_DELETE_SELF", Const, 0, ""}, + {"IN_DONT_FOLLOW", Const, 0, ""}, + {"IN_EXCL_UNLINK", Const, 0, ""}, + {"IN_IGNORED", Const, 0, ""}, + {"IN_ISDIR", Const, 0, ""}, + {"IN_LINKLOCALNETNUM", Const, 0, ""}, + {"IN_LOOPBACKNET", Const, 0, ""}, + {"IN_MASK_ADD", Const, 0, ""}, + {"IN_MODIFY", Const, 0, ""}, + {"IN_MOVE", Const, 0, ""}, + {"IN_MOVED_FROM", Const, 0, ""}, + {"IN_MOVED_TO", Const, 0, ""}, + {"IN_MOVE_SELF", Const, 0, ""}, + {"IN_NONBLOCK", Const, 0, ""}, + {"IN_ONESHOT", Const, 0, ""}, + {"IN_ONLYDIR", Const, 0, ""}, + {"IN_OPEN", Const, 0, ""}, + {"IN_Q_OVERFLOW", Const, 0, ""}, + {"IN_RFC3021_HOST", Const, 1, ""}, + {"IN_RFC3021_MASK", Const, 1, ""}, + {"IN_RFC3021_NET", Const, 1, ""}, + {"IN_RFC3021_NSHIFT", Const, 1, ""}, + {"IN_UNMOUNT", Const, 0, ""}, + {"IOC_IN", Const, 1, ""}, + {"IOC_INOUT", Const, 1, ""}, + {"IOC_OUT", Const, 1, ""}, + {"IOC_VENDOR", Const, 3, ""}, + {"IOC_WS2", Const, 1, ""}, + {"IO_REPARSE_TAG_SYMLINK", Const, 4, ""}, + {"IPMreq", Type, 0, ""}, + {"IPMreq.Interface", Field, 0, ""}, + {"IPMreq.Multiaddr", Field, 0, ""}, + {"IPMreqn", Type, 0, ""}, + {"IPMreqn.Address", Field, 0, ""}, + {"IPMreqn.Ifindex", Field, 0, ""}, + {"IPMreqn.Multiaddr", Field, 0, ""}, + {"IPPROTO_3PC", Const, 0, ""}, + {"IPPROTO_ADFS", Const, 0, ""}, + {"IPPROTO_AH", Const, 0, ""}, + {"IPPROTO_AHIP", Const, 0, ""}, + {"IPPROTO_APES", Const, 0, ""}, + {"IPPROTO_ARGUS", Const, 0, ""}, + {"IPPROTO_AX25", Const, 0, ""}, + {"IPPROTO_BHA", Const, 0, ""}, + {"IPPROTO_BLT", Const, 0, ""}, + {"IPPROTO_BRSATMON", Const, 0, ""}, + {"IPPROTO_CARP", Const, 0, ""}, + {"IPPROTO_CFTP", Const, 0, ""}, + {"IPPROTO_CHAOS", Const, 0, ""}, + {"IPPROTO_CMTP", Const, 0, ""}, + {"IPPROTO_COMP", Const, 0, ""}, + {"IPPROTO_CPHB", Const, 0, ""}, + {"IPPROTO_CPNX", Const, 0, ""}, + {"IPPROTO_DCCP", Const, 0, ""}, + {"IPPROTO_DDP", Const, 0, ""}, + {"IPPROTO_DGP", Const, 0, ""}, + {"IPPROTO_DIVERT", Const, 0, ""}, + {"IPPROTO_DIVERT_INIT", Const, 3, ""}, + {"IPPROTO_DIVERT_RESP", Const, 3, ""}, + {"IPPROTO_DONE", Const, 0, ""}, + {"IPPROTO_DSTOPTS", Const, 0, ""}, + {"IPPROTO_EGP", Const, 0, ""}, + {"IPPROTO_EMCON", Const, 0, ""}, + {"IPPROTO_ENCAP", Const, 0, ""}, + {"IPPROTO_EON", Const, 0, ""}, + {"IPPROTO_ESP", Const, 0, ""}, + {"IPPROTO_ETHERIP", Const, 0, ""}, + {"IPPROTO_FRAGMENT", Const, 0, ""}, + {"IPPROTO_GGP", Const, 0, ""}, + {"IPPROTO_GMTP", Const, 0, ""}, + {"IPPROTO_GRE", Const, 0, ""}, + {"IPPROTO_HELLO", Const, 0, ""}, + {"IPPROTO_HMP", Const, 0, ""}, + {"IPPROTO_HOPOPTS", Const, 0, ""}, + {"IPPROTO_ICMP", Const, 0, ""}, + {"IPPROTO_ICMPV6", Const, 0, ""}, + {"IPPROTO_IDP", Const, 0, ""}, + {"IPPROTO_IDPR", Const, 0, ""}, + {"IPPROTO_IDRP", Const, 0, ""}, + {"IPPROTO_IGMP", Const, 0, ""}, + {"IPPROTO_IGP", Const, 0, ""}, + {"IPPROTO_IGRP", Const, 0, ""}, + {"IPPROTO_IL", Const, 0, ""}, + {"IPPROTO_INLSP", Const, 0, ""}, + {"IPPROTO_INP", Const, 0, ""}, + {"IPPROTO_IP", Const, 0, ""}, + {"IPPROTO_IPCOMP", Const, 0, ""}, + {"IPPROTO_IPCV", Const, 0, ""}, + {"IPPROTO_IPEIP", Const, 0, ""}, + {"IPPROTO_IPIP", Const, 0, ""}, + {"IPPROTO_IPPC", Const, 0, ""}, + {"IPPROTO_IPV4", Const, 0, ""}, + {"IPPROTO_IPV6", Const, 0, ""}, + {"IPPROTO_IPV6_ICMP", Const, 1, ""}, + {"IPPROTO_IRTP", Const, 0, ""}, + {"IPPROTO_KRYPTOLAN", Const, 0, ""}, + {"IPPROTO_LARP", Const, 0, ""}, + {"IPPROTO_LEAF1", Const, 0, ""}, + {"IPPROTO_LEAF2", Const, 0, ""}, + {"IPPROTO_MAX", Const, 0, ""}, + {"IPPROTO_MAXID", Const, 0, ""}, + {"IPPROTO_MEAS", Const, 0, ""}, + {"IPPROTO_MH", Const, 1, ""}, + {"IPPROTO_MHRP", Const, 0, ""}, + {"IPPROTO_MICP", Const, 0, ""}, + {"IPPROTO_MOBILE", Const, 0, ""}, + {"IPPROTO_MPLS", Const, 1, ""}, + {"IPPROTO_MTP", Const, 0, ""}, + {"IPPROTO_MUX", Const, 0, ""}, + {"IPPROTO_ND", Const, 0, ""}, + {"IPPROTO_NHRP", Const, 0, ""}, + {"IPPROTO_NONE", Const, 0, ""}, + {"IPPROTO_NSP", Const, 0, ""}, + {"IPPROTO_NVPII", Const, 0, ""}, + {"IPPROTO_OLD_DIVERT", Const, 0, ""}, + {"IPPROTO_OSPFIGP", Const, 0, ""}, + {"IPPROTO_PFSYNC", Const, 0, ""}, + {"IPPROTO_PGM", Const, 0, ""}, + {"IPPROTO_PIGP", Const, 0, ""}, + {"IPPROTO_PIM", Const, 0, ""}, + {"IPPROTO_PRM", Const, 0, ""}, + {"IPPROTO_PUP", Const, 0, ""}, + {"IPPROTO_PVP", Const, 0, ""}, + {"IPPROTO_RAW", Const, 0, ""}, + {"IPPROTO_RCCMON", Const, 0, ""}, + {"IPPROTO_RDP", Const, 0, ""}, + {"IPPROTO_ROUTING", Const, 0, ""}, + {"IPPROTO_RSVP", Const, 0, ""}, + {"IPPROTO_RVD", Const, 0, ""}, + {"IPPROTO_SATEXPAK", Const, 0, ""}, + {"IPPROTO_SATMON", Const, 0, ""}, + {"IPPROTO_SCCSP", Const, 0, ""}, + {"IPPROTO_SCTP", Const, 0, ""}, + {"IPPROTO_SDRP", Const, 0, ""}, + {"IPPROTO_SEND", Const, 1, ""}, + {"IPPROTO_SEP", Const, 0, ""}, + {"IPPROTO_SKIP", Const, 0, ""}, + {"IPPROTO_SPACER", Const, 0, ""}, + {"IPPROTO_SRPC", Const, 0, ""}, + {"IPPROTO_ST", Const, 0, ""}, + {"IPPROTO_SVMTP", Const, 0, ""}, + {"IPPROTO_SWIPE", Const, 0, ""}, + {"IPPROTO_TCF", Const, 0, ""}, + {"IPPROTO_TCP", Const, 0, ""}, + {"IPPROTO_TLSP", Const, 0, ""}, + {"IPPROTO_TP", Const, 0, ""}, + {"IPPROTO_TPXX", Const, 0, ""}, + {"IPPROTO_TRUNK1", Const, 0, ""}, + {"IPPROTO_TRUNK2", Const, 0, ""}, + {"IPPROTO_TTP", Const, 0, ""}, + {"IPPROTO_UDP", Const, 0, ""}, + {"IPPROTO_UDPLITE", Const, 0, ""}, + {"IPPROTO_VINES", Const, 0, ""}, + {"IPPROTO_VISA", Const, 0, ""}, + {"IPPROTO_VMTP", Const, 0, ""}, + {"IPPROTO_VRRP", Const, 1, ""}, + {"IPPROTO_WBEXPAK", Const, 0, ""}, + {"IPPROTO_WBMON", Const, 0, ""}, + {"IPPROTO_WSN", Const, 0, ""}, + {"IPPROTO_XNET", Const, 0, ""}, + {"IPPROTO_XTP", Const, 0, ""}, + {"IPV6_2292DSTOPTS", Const, 0, ""}, + {"IPV6_2292HOPLIMIT", Const, 0, ""}, + {"IPV6_2292HOPOPTS", Const, 0, ""}, + {"IPV6_2292NEXTHOP", Const, 0, ""}, + {"IPV6_2292PKTINFO", Const, 0, ""}, + {"IPV6_2292PKTOPTIONS", Const, 0, ""}, + {"IPV6_2292RTHDR", Const, 0, ""}, + {"IPV6_ADDRFORM", Const, 0, ""}, + {"IPV6_ADD_MEMBERSHIP", Const, 0, ""}, + {"IPV6_AUTHHDR", Const, 0, ""}, + {"IPV6_AUTH_LEVEL", Const, 1, ""}, + {"IPV6_AUTOFLOWLABEL", Const, 0, ""}, + {"IPV6_BINDANY", Const, 0, ""}, + {"IPV6_BINDV6ONLY", Const, 0, ""}, + {"IPV6_BOUND_IF", Const, 0, ""}, + {"IPV6_CHECKSUM", Const, 0, ""}, + {"IPV6_DEFAULT_MULTICAST_HOPS", Const, 0, ""}, + {"IPV6_DEFAULT_MULTICAST_LOOP", Const, 0, ""}, + {"IPV6_DEFHLIM", Const, 0, ""}, + {"IPV6_DONTFRAG", Const, 0, ""}, + {"IPV6_DROP_MEMBERSHIP", Const, 0, ""}, + {"IPV6_DSTOPTS", Const, 0, ""}, + {"IPV6_ESP_NETWORK_LEVEL", Const, 1, ""}, + {"IPV6_ESP_TRANS_LEVEL", Const, 1, ""}, + {"IPV6_FAITH", Const, 0, ""}, + {"IPV6_FLOWINFO_MASK", Const, 0, ""}, + {"IPV6_FLOWLABEL_MASK", Const, 0, ""}, + {"IPV6_FRAGTTL", Const, 0, ""}, + {"IPV6_FW_ADD", Const, 0, ""}, + {"IPV6_FW_DEL", Const, 0, ""}, + {"IPV6_FW_FLUSH", Const, 0, ""}, + {"IPV6_FW_GET", Const, 0, ""}, + {"IPV6_FW_ZERO", Const, 0, ""}, + {"IPV6_HLIMDEC", Const, 0, ""}, + {"IPV6_HOPLIMIT", Const, 0, ""}, + {"IPV6_HOPOPTS", Const, 0, ""}, + {"IPV6_IPCOMP_LEVEL", Const, 1, ""}, + {"IPV6_IPSEC_POLICY", Const, 0, ""}, + {"IPV6_JOIN_ANYCAST", Const, 0, ""}, + {"IPV6_JOIN_GROUP", Const, 0, ""}, + {"IPV6_LEAVE_ANYCAST", Const, 0, ""}, + {"IPV6_LEAVE_GROUP", Const, 0, ""}, + {"IPV6_MAXHLIM", Const, 0, ""}, + {"IPV6_MAXOPTHDR", Const, 0, ""}, + {"IPV6_MAXPACKET", Const, 0, ""}, + {"IPV6_MAX_GROUP_SRC_FILTER", Const, 0, ""}, + {"IPV6_MAX_MEMBERSHIPS", Const, 0, ""}, + {"IPV6_MAX_SOCK_SRC_FILTER", Const, 0, ""}, + {"IPV6_MIN_MEMBERSHIPS", Const, 0, ""}, + {"IPV6_MMTU", Const, 0, ""}, + {"IPV6_MSFILTER", Const, 0, ""}, + {"IPV6_MTU", Const, 0, ""}, + {"IPV6_MTU_DISCOVER", Const, 0, ""}, + {"IPV6_MULTICAST_HOPS", Const, 0, ""}, + {"IPV6_MULTICAST_IF", Const, 0, ""}, + {"IPV6_MULTICAST_LOOP", Const, 0, ""}, + {"IPV6_NEXTHOP", Const, 0, ""}, + {"IPV6_OPTIONS", Const, 1, ""}, + {"IPV6_PATHMTU", Const, 0, ""}, + {"IPV6_PIPEX", Const, 1, ""}, + {"IPV6_PKTINFO", Const, 0, ""}, + {"IPV6_PMTUDISC_DO", Const, 0, ""}, + {"IPV6_PMTUDISC_DONT", Const, 0, ""}, + {"IPV6_PMTUDISC_PROBE", Const, 0, ""}, + {"IPV6_PMTUDISC_WANT", Const, 0, ""}, + {"IPV6_PORTRANGE", Const, 0, ""}, + {"IPV6_PORTRANGE_DEFAULT", Const, 0, ""}, + {"IPV6_PORTRANGE_HIGH", Const, 0, ""}, + {"IPV6_PORTRANGE_LOW", Const, 0, ""}, + {"IPV6_PREFER_TEMPADDR", Const, 0, ""}, + {"IPV6_RECVDSTOPTS", Const, 0, ""}, + {"IPV6_RECVDSTPORT", Const, 3, ""}, + {"IPV6_RECVERR", Const, 0, ""}, + {"IPV6_RECVHOPLIMIT", Const, 0, ""}, + {"IPV6_RECVHOPOPTS", Const, 0, ""}, + {"IPV6_RECVPATHMTU", Const, 0, ""}, + {"IPV6_RECVPKTINFO", Const, 0, ""}, + {"IPV6_RECVRTHDR", Const, 0, ""}, + {"IPV6_RECVTCLASS", Const, 0, ""}, + {"IPV6_ROUTER_ALERT", Const, 0, ""}, + {"IPV6_RTABLE", Const, 1, ""}, + {"IPV6_RTHDR", Const, 0, ""}, + {"IPV6_RTHDRDSTOPTS", Const, 0, ""}, + {"IPV6_RTHDR_LOOSE", Const, 0, ""}, + {"IPV6_RTHDR_STRICT", Const, 0, ""}, + {"IPV6_RTHDR_TYPE_0", Const, 0, ""}, + {"IPV6_RXDSTOPTS", Const, 0, ""}, + {"IPV6_RXHOPOPTS", Const, 0, ""}, + {"IPV6_SOCKOPT_RESERVED1", Const, 0, ""}, + {"IPV6_TCLASS", Const, 0, ""}, + {"IPV6_UNICAST_HOPS", Const, 0, ""}, + {"IPV6_USE_MIN_MTU", Const, 0, ""}, + {"IPV6_V6ONLY", Const, 0, ""}, + {"IPV6_VERSION", Const, 0, ""}, + {"IPV6_VERSION_MASK", Const, 0, ""}, + {"IPV6_XFRM_POLICY", Const, 0, ""}, + {"IP_ADD_MEMBERSHIP", Const, 0, ""}, + {"IP_ADD_SOURCE_MEMBERSHIP", Const, 0, ""}, + {"IP_AUTH_LEVEL", Const, 1, ""}, + {"IP_BINDANY", Const, 0, ""}, + {"IP_BLOCK_SOURCE", Const, 0, ""}, + {"IP_BOUND_IF", Const, 0, ""}, + {"IP_DEFAULT_MULTICAST_LOOP", Const, 0, ""}, + {"IP_DEFAULT_MULTICAST_TTL", Const, 0, ""}, + {"IP_DF", Const, 0, ""}, + {"IP_DIVERTFL", Const, 3, ""}, + {"IP_DONTFRAG", Const, 0, ""}, + {"IP_DROP_MEMBERSHIP", Const, 0, ""}, + {"IP_DROP_SOURCE_MEMBERSHIP", Const, 0, ""}, + {"IP_DUMMYNET3", Const, 0, ""}, + {"IP_DUMMYNET_CONFIGURE", Const, 0, ""}, + {"IP_DUMMYNET_DEL", Const, 0, ""}, + {"IP_DUMMYNET_FLUSH", Const, 0, ""}, + {"IP_DUMMYNET_GET", Const, 0, ""}, + {"IP_EF", Const, 1, ""}, + {"IP_ERRORMTU", Const, 1, ""}, + {"IP_ESP_NETWORK_LEVEL", Const, 1, ""}, + {"IP_ESP_TRANS_LEVEL", Const, 1, ""}, + {"IP_FAITH", Const, 0, ""}, + {"IP_FREEBIND", Const, 0, ""}, + {"IP_FW3", Const, 0, ""}, + {"IP_FW_ADD", Const, 0, ""}, + {"IP_FW_DEL", Const, 0, ""}, + {"IP_FW_FLUSH", Const, 0, ""}, + {"IP_FW_GET", Const, 0, ""}, + {"IP_FW_NAT_CFG", Const, 0, ""}, + {"IP_FW_NAT_DEL", Const, 0, ""}, + {"IP_FW_NAT_GET_CONFIG", Const, 0, ""}, + {"IP_FW_NAT_GET_LOG", Const, 0, ""}, + {"IP_FW_RESETLOG", Const, 0, ""}, + {"IP_FW_TABLE_ADD", Const, 0, ""}, + {"IP_FW_TABLE_DEL", Const, 0, ""}, + {"IP_FW_TABLE_FLUSH", Const, 0, ""}, + {"IP_FW_TABLE_GETSIZE", Const, 0, ""}, + {"IP_FW_TABLE_LIST", Const, 0, ""}, + {"IP_FW_ZERO", Const, 0, ""}, + {"IP_HDRINCL", Const, 0, ""}, + {"IP_IPCOMP_LEVEL", Const, 1, ""}, + {"IP_IPSECFLOWINFO", Const, 1, ""}, + {"IP_IPSEC_LOCAL_AUTH", Const, 1, ""}, + {"IP_IPSEC_LOCAL_CRED", Const, 1, ""}, + {"IP_IPSEC_LOCAL_ID", Const, 1, ""}, + {"IP_IPSEC_POLICY", Const, 0, ""}, + {"IP_IPSEC_REMOTE_AUTH", Const, 1, ""}, + {"IP_IPSEC_REMOTE_CRED", Const, 1, ""}, + {"IP_IPSEC_REMOTE_ID", Const, 1, ""}, + {"IP_MAXPACKET", Const, 0, ""}, + {"IP_MAX_GROUP_SRC_FILTER", Const, 0, ""}, + {"IP_MAX_MEMBERSHIPS", Const, 0, ""}, + {"IP_MAX_SOCK_MUTE_FILTER", Const, 0, ""}, + {"IP_MAX_SOCK_SRC_FILTER", Const, 0, ""}, + {"IP_MAX_SOURCE_FILTER", Const, 0, ""}, + {"IP_MF", Const, 0, ""}, + {"IP_MINFRAGSIZE", Const, 1, ""}, + {"IP_MINTTL", Const, 0, ""}, + {"IP_MIN_MEMBERSHIPS", Const, 0, ""}, + {"IP_MSFILTER", Const, 0, ""}, + {"IP_MSS", Const, 0, ""}, + {"IP_MTU", Const, 0, ""}, + {"IP_MTU_DISCOVER", Const, 0, ""}, + {"IP_MULTICAST_IF", Const, 0, ""}, + {"IP_MULTICAST_IFINDEX", Const, 0, ""}, + {"IP_MULTICAST_LOOP", Const, 0, ""}, + {"IP_MULTICAST_TTL", Const, 0, ""}, + {"IP_MULTICAST_VIF", Const, 0, ""}, + {"IP_NAT__XXX", Const, 0, ""}, + {"IP_OFFMASK", Const, 0, ""}, + {"IP_OLD_FW_ADD", Const, 0, ""}, + {"IP_OLD_FW_DEL", Const, 0, ""}, + {"IP_OLD_FW_FLUSH", Const, 0, ""}, + {"IP_OLD_FW_GET", Const, 0, ""}, + {"IP_OLD_FW_RESETLOG", Const, 0, ""}, + {"IP_OLD_FW_ZERO", Const, 0, ""}, + {"IP_ONESBCAST", Const, 0, ""}, + {"IP_OPTIONS", Const, 0, ""}, + {"IP_ORIGDSTADDR", Const, 0, ""}, + {"IP_PASSSEC", Const, 0, ""}, + {"IP_PIPEX", Const, 1, ""}, + {"IP_PKTINFO", Const, 0, ""}, + {"IP_PKTOPTIONS", Const, 0, ""}, + {"IP_PMTUDISC", Const, 0, ""}, + {"IP_PMTUDISC_DO", Const, 0, ""}, + {"IP_PMTUDISC_DONT", Const, 0, ""}, + {"IP_PMTUDISC_PROBE", Const, 0, ""}, + {"IP_PMTUDISC_WANT", Const, 0, ""}, + {"IP_PORTRANGE", Const, 0, ""}, + {"IP_PORTRANGE_DEFAULT", Const, 0, ""}, + {"IP_PORTRANGE_HIGH", Const, 0, ""}, + {"IP_PORTRANGE_LOW", Const, 0, ""}, + {"IP_RECVDSTADDR", Const, 0, ""}, + {"IP_RECVDSTPORT", Const, 1, ""}, + {"IP_RECVERR", Const, 0, ""}, + {"IP_RECVIF", Const, 0, ""}, + {"IP_RECVOPTS", Const, 0, ""}, + {"IP_RECVORIGDSTADDR", Const, 0, ""}, + {"IP_RECVPKTINFO", Const, 0, ""}, + {"IP_RECVRETOPTS", Const, 0, ""}, + {"IP_RECVRTABLE", Const, 1, ""}, + {"IP_RECVTOS", Const, 0, ""}, + {"IP_RECVTTL", Const, 0, ""}, + {"IP_RETOPTS", Const, 0, ""}, + {"IP_RF", Const, 0, ""}, + {"IP_ROUTER_ALERT", Const, 0, ""}, + {"IP_RSVP_OFF", Const, 0, ""}, + {"IP_RSVP_ON", Const, 0, ""}, + {"IP_RSVP_VIF_OFF", Const, 0, ""}, + {"IP_RSVP_VIF_ON", Const, 0, ""}, + {"IP_RTABLE", Const, 1, ""}, + {"IP_SENDSRCADDR", Const, 0, ""}, + {"IP_STRIPHDR", Const, 0, ""}, + {"IP_TOS", Const, 0, ""}, + {"IP_TRAFFIC_MGT_BACKGROUND", Const, 0, ""}, + {"IP_TRANSPARENT", Const, 0, ""}, + {"IP_TTL", Const, 0, ""}, + {"IP_UNBLOCK_SOURCE", Const, 0, ""}, + {"IP_XFRM_POLICY", Const, 0, ""}, + {"IPv6MTUInfo", Type, 2, ""}, + {"IPv6MTUInfo.Addr", Field, 2, ""}, + {"IPv6MTUInfo.Mtu", Field, 2, ""}, + {"IPv6Mreq", Type, 0, ""}, + {"IPv6Mreq.Interface", Field, 0, ""}, + {"IPv6Mreq.Multiaddr", Field, 0, ""}, + {"ISIG", Const, 0, ""}, + {"ISTRIP", Const, 0, ""}, + {"IUCLC", Const, 0, ""}, + {"IUTF8", Const, 0, ""}, + {"IXANY", Const, 0, ""}, + {"IXOFF", Const, 0, ""}, + {"IXON", Const, 0, ""}, + {"IfAddrmsg", Type, 0, ""}, + {"IfAddrmsg.Family", Field, 0, ""}, + {"IfAddrmsg.Flags", Field, 0, ""}, + {"IfAddrmsg.Index", Field, 0, ""}, + {"IfAddrmsg.Prefixlen", Field, 0, ""}, + {"IfAddrmsg.Scope", Field, 0, ""}, + {"IfAnnounceMsghdr", Type, 1, ""}, + {"IfAnnounceMsghdr.Hdrlen", Field, 2, ""}, + {"IfAnnounceMsghdr.Index", Field, 1, ""}, + {"IfAnnounceMsghdr.Msglen", Field, 1, ""}, + {"IfAnnounceMsghdr.Name", Field, 1, ""}, + {"IfAnnounceMsghdr.Type", Field, 1, ""}, + {"IfAnnounceMsghdr.Version", Field, 1, ""}, + {"IfAnnounceMsghdr.What", Field, 1, ""}, + {"IfData", Type, 0, ""}, + {"IfData.Addrlen", Field, 0, ""}, + {"IfData.Baudrate", Field, 0, ""}, + {"IfData.Capabilities", Field, 2, ""}, + {"IfData.Collisions", Field, 0, ""}, + {"IfData.Datalen", Field, 0, ""}, + {"IfData.Epoch", Field, 0, ""}, + {"IfData.Hdrlen", Field, 0, ""}, + {"IfData.Hwassist", Field, 0, ""}, + {"IfData.Ibytes", Field, 0, ""}, + {"IfData.Ierrors", Field, 0, ""}, + {"IfData.Imcasts", Field, 0, ""}, + {"IfData.Ipackets", Field, 0, ""}, + {"IfData.Iqdrops", Field, 0, ""}, + {"IfData.Lastchange", Field, 0, ""}, + {"IfData.Link_state", Field, 0, ""}, + {"IfData.Mclpool", Field, 2, ""}, + {"IfData.Metric", Field, 0, ""}, + {"IfData.Mtu", Field, 0, ""}, + {"IfData.Noproto", Field, 0, ""}, + {"IfData.Obytes", Field, 0, ""}, + {"IfData.Oerrors", Field, 0, ""}, + {"IfData.Omcasts", Field, 0, ""}, + {"IfData.Opackets", Field, 0, ""}, + {"IfData.Pad", Field, 2, ""}, + {"IfData.Pad_cgo_0", Field, 2, ""}, + {"IfData.Pad_cgo_1", Field, 2, ""}, + {"IfData.Physical", Field, 0, ""}, + {"IfData.Recvquota", Field, 0, ""}, + {"IfData.Recvtiming", Field, 0, ""}, + {"IfData.Reserved1", Field, 0, ""}, + {"IfData.Reserved2", Field, 0, ""}, + {"IfData.Spare_char1", Field, 0, ""}, + {"IfData.Spare_char2", Field, 0, ""}, + {"IfData.Type", Field, 0, ""}, + {"IfData.Typelen", Field, 0, ""}, + {"IfData.Unused1", Field, 0, ""}, + {"IfData.Unused2", Field, 0, ""}, + {"IfData.Xmitquota", Field, 0, ""}, + {"IfData.Xmittiming", Field, 0, ""}, + {"IfInfomsg", Type, 0, ""}, + {"IfInfomsg.Change", Field, 0, ""}, + {"IfInfomsg.Family", Field, 0, ""}, + {"IfInfomsg.Flags", Field, 0, ""}, + {"IfInfomsg.Index", Field, 0, ""}, + {"IfInfomsg.Type", Field, 0, ""}, + {"IfInfomsg.X__ifi_pad", Field, 0, ""}, + {"IfMsghdr", Type, 0, ""}, + {"IfMsghdr.Addrs", Field, 0, ""}, + {"IfMsghdr.Data", Field, 0, ""}, + {"IfMsghdr.Flags", Field, 0, ""}, + {"IfMsghdr.Hdrlen", Field, 2, ""}, + {"IfMsghdr.Index", Field, 0, ""}, + {"IfMsghdr.Msglen", Field, 0, ""}, + {"IfMsghdr.Pad1", Field, 2, ""}, + {"IfMsghdr.Pad2", Field, 2, ""}, + {"IfMsghdr.Pad_cgo_0", Field, 0, ""}, + {"IfMsghdr.Pad_cgo_1", Field, 2, ""}, + {"IfMsghdr.Tableid", Field, 2, ""}, + {"IfMsghdr.Type", Field, 0, ""}, + {"IfMsghdr.Version", Field, 0, ""}, + {"IfMsghdr.Xflags", Field, 2, ""}, + {"IfaMsghdr", Type, 0, ""}, + {"IfaMsghdr.Addrs", Field, 0, ""}, + {"IfaMsghdr.Flags", Field, 0, ""}, + {"IfaMsghdr.Hdrlen", Field, 2, ""}, + {"IfaMsghdr.Index", Field, 0, ""}, + {"IfaMsghdr.Metric", Field, 0, ""}, + {"IfaMsghdr.Msglen", Field, 0, ""}, + {"IfaMsghdr.Pad1", Field, 2, ""}, + {"IfaMsghdr.Pad2", Field, 2, ""}, + {"IfaMsghdr.Pad_cgo_0", Field, 0, ""}, + {"IfaMsghdr.Tableid", Field, 2, ""}, + {"IfaMsghdr.Type", Field, 0, ""}, + {"IfaMsghdr.Version", Field, 0, ""}, + {"IfmaMsghdr", Type, 0, ""}, + {"IfmaMsghdr.Addrs", Field, 0, ""}, + {"IfmaMsghdr.Flags", Field, 0, ""}, + {"IfmaMsghdr.Index", Field, 0, ""}, + {"IfmaMsghdr.Msglen", Field, 0, ""}, + {"IfmaMsghdr.Pad_cgo_0", Field, 0, ""}, + {"IfmaMsghdr.Type", Field, 0, ""}, + {"IfmaMsghdr.Version", Field, 0, ""}, + {"IfmaMsghdr2", Type, 0, ""}, + {"IfmaMsghdr2.Addrs", Field, 0, ""}, + {"IfmaMsghdr2.Flags", Field, 0, ""}, + {"IfmaMsghdr2.Index", Field, 0, ""}, + {"IfmaMsghdr2.Msglen", Field, 0, ""}, + {"IfmaMsghdr2.Pad_cgo_0", Field, 0, ""}, + {"IfmaMsghdr2.Refcount", Field, 0, ""}, + {"IfmaMsghdr2.Type", Field, 0, ""}, + {"IfmaMsghdr2.Version", Field, 0, ""}, + {"ImplementsGetwd", Const, 0, ""}, + {"Inet4Pktinfo", Type, 0, ""}, + {"Inet4Pktinfo.Addr", Field, 0, ""}, + {"Inet4Pktinfo.Ifindex", Field, 0, ""}, + {"Inet4Pktinfo.Spec_dst", Field, 0, ""}, + {"Inet6Pktinfo", Type, 0, ""}, + {"Inet6Pktinfo.Addr", Field, 0, ""}, + {"Inet6Pktinfo.Ifindex", Field, 0, ""}, + {"InotifyAddWatch", Func, 0, "func(fd int, pathname string, mask uint32) (watchdesc int, err error)"}, + {"InotifyEvent", Type, 0, ""}, + {"InotifyEvent.Cookie", Field, 0, ""}, + {"InotifyEvent.Len", Field, 0, ""}, + {"InotifyEvent.Mask", Field, 0, ""}, + {"InotifyEvent.Name", Field, 0, ""}, + {"InotifyEvent.Wd", Field, 0, ""}, + {"InotifyInit", Func, 0, "func() (fd int, err error)"}, + {"InotifyInit1", Func, 0, "func(flags int) (fd int, err error)"}, + {"InotifyRmWatch", Func, 0, "func(fd int, watchdesc uint32) (success int, err error)"}, + {"InterfaceAddrMessage", Type, 0, ""}, + {"InterfaceAddrMessage.Data", Field, 0, ""}, + {"InterfaceAddrMessage.Header", Field, 0, ""}, + {"InterfaceAnnounceMessage", Type, 1, ""}, + {"InterfaceAnnounceMessage.Header", Field, 1, ""}, + {"InterfaceInfo", Type, 0, ""}, + {"InterfaceInfo.Address", Field, 0, ""}, + {"InterfaceInfo.BroadcastAddress", Field, 0, ""}, + {"InterfaceInfo.Flags", Field, 0, ""}, + {"InterfaceInfo.Netmask", Field, 0, ""}, + {"InterfaceMessage", Type, 0, ""}, + {"InterfaceMessage.Data", Field, 0, ""}, + {"InterfaceMessage.Header", Field, 0, ""}, + {"InterfaceMulticastAddrMessage", Type, 0, ""}, + {"InterfaceMulticastAddrMessage.Data", Field, 0, ""}, + {"InterfaceMulticastAddrMessage.Header", Field, 0, ""}, + {"InvalidHandle", Const, 0, ""}, + {"Ioperm", Func, 0, "func(from int, num int, on int) (err error)"}, + {"Iopl", Func, 0, "func(level int) (err error)"}, + {"Iovec", Type, 0, ""}, + {"Iovec.Base", Field, 0, ""}, + {"Iovec.Len", Field, 0, ""}, + {"IpAdapterInfo", Type, 0, ""}, + {"IpAdapterInfo.AdapterName", Field, 0, ""}, + {"IpAdapterInfo.Address", Field, 0, ""}, + {"IpAdapterInfo.AddressLength", Field, 0, ""}, + {"IpAdapterInfo.ComboIndex", Field, 0, ""}, + {"IpAdapterInfo.CurrentIpAddress", Field, 0, ""}, + {"IpAdapterInfo.Description", Field, 0, ""}, + {"IpAdapterInfo.DhcpEnabled", Field, 0, ""}, + {"IpAdapterInfo.DhcpServer", Field, 0, ""}, + {"IpAdapterInfo.GatewayList", Field, 0, ""}, + {"IpAdapterInfo.HaveWins", Field, 0, ""}, + {"IpAdapterInfo.Index", Field, 0, ""}, + {"IpAdapterInfo.IpAddressList", Field, 0, ""}, + {"IpAdapterInfo.LeaseExpires", Field, 0, ""}, + {"IpAdapterInfo.LeaseObtained", Field, 0, ""}, + {"IpAdapterInfo.Next", Field, 0, ""}, + {"IpAdapterInfo.PrimaryWinsServer", Field, 0, ""}, + {"IpAdapterInfo.SecondaryWinsServer", Field, 0, ""}, + {"IpAdapterInfo.Type", Field, 0, ""}, + {"IpAddrString", Type, 0, ""}, + {"IpAddrString.Context", Field, 0, ""}, + {"IpAddrString.IpAddress", Field, 0, ""}, + {"IpAddrString.IpMask", Field, 0, ""}, + {"IpAddrString.Next", Field, 0, ""}, + {"IpAddressString", Type, 0, ""}, + {"IpAddressString.String", Field, 0, ""}, + {"IpMaskString", Type, 0, ""}, + {"IpMaskString.String", Field, 2, ""}, + {"Issetugid", Func, 0, ""}, + {"KEY_ALL_ACCESS", Const, 0, ""}, + {"KEY_CREATE_LINK", Const, 0, ""}, + {"KEY_CREATE_SUB_KEY", Const, 0, ""}, + {"KEY_ENUMERATE_SUB_KEYS", Const, 0, ""}, + {"KEY_EXECUTE", Const, 0, ""}, + {"KEY_NOTIFY", Const, 0, ""}, + {"KEY_QUERY_VALUE", Const, 0, ""}, + {"KEY_READ", Const, 0, ""}, + {"KEY_SET_VALUE", Const, 0, ""}, + {"KEY_WOW64_32KEY", Const, 0, ""}, + {"KEY_WOW64_64KEY", Const, 0, ""}, + {"KEY_WRITE", Const, 0, ""}, + {"Kevent", Func, 0, ""}, + {"Kevent_t", Type, 0, ""}, + {"Kevent_t.Data", Field, 0, ""}, + {"Kevent_t.Fflags", Field, 0, ""}, + {"Kevent_t.Filter", Field, 0, ""}, + {"Kevent_t.Flags", Field, 0, ""}, + {"Kevent_t.Ident", Field, 0, ""}, + {"Kevent_t.Pad_cgo_0", Field, 2, ""}, + {"Kevent_t.Udata", Field, 0, ""}, + {"Kill", Func, 0, "func(pid int, sig Signal) (err error)"}, + {"Klogctl", Func, 0, "func(typ int, buf []byte) (n int, err error)"}, + {"Kqueue", Func, 0, ""}, + {"LANG_ENGLISH", Const, 0, ""}, + {"LAYERED_PROTOCOL", Const, 2, ""}, + {"LCNT_OVERLOAD_FLUSH", Const, 1, ""}, + {"LINUX_REBOOT_CMD_CAD_OFF", Const, 0, ""}, + {"LINUX_REBOOT_CMD_CAD_ON", Const, 0, ""}, + {"LINUX_REBOOT_CMD_HALT", Const, 0, ""}, + {"LINUX_REBOOT_CMD_KEXEC", Const, 0, ""}, + {"LINUX_REBOOT_CMD_POWER_OFF", Const, 0, ""}, + {"LINUX_REBOOT_CMD_RESTART", Const, 0, ""}, + {"LINUX_REBOOT_CMD_RESTART2", Const, 0, ""}, + {"LINUX_REBOOT_CMD_SW_SUSPEND", Const, 0, ""}, + {"LINUX_REBOOT_MAGIC1", Const, 0, ""}, + {"LINUX_REBOOT_MAGIC2", Const, 0, ""}, + {"LOCK_EX", Const, 0, ""}, + {"LOCK_NB", Const, 0, ""}, + {"LOCK_SH", Const, 0, ""}, + {"LOCK_UN", Const, 0, ""}, + {"LazyDLL", Type, 0, ""}, + {"LazyDLL.Name", Field, 0, ""}, + {"LazyProc", Type, 0, ""}, + {"LazyProc.Name", Field, 0, ""}, + {"Lchown", Func, 0, "func(path string, uid int, gid int) (err error)"}, + {"Linger", Type, 0, ""}, + {"Linger.Linger", Field, 0, ""}, + {"Linger.Onoff", Field, 0, ""}, + {"Link", Func, 0, "func(oldpath string, newpath string) (err error)"}, + {"Listen", Func, 0, "func(s int, n int) (err error)"}, + {"Listxattr", Func, 1, "func(path string, dest []byte) (sz int, err error)"}, + {"LoadCancelIoEx", Func, 1, ""}, + {"LoadConnectEx", Func, 1, ""}, + {"LoadCreateSymbolicLink", Func, 4, ""}, + {"LoadDLL", Func, 0, ""}, + {"LoadGetAddrInfo", Func, 1, ""}, + {"LoadLibrary", Func, 0, ""}, + {"LoadSetFileCompletionNotificationModes", Func, 2, ""}, + {"LocalFree", Func, 0, ""}, + {"Log2phys_t", Type, 0, ""}, + {"Log2phys_t.Contigbytes", Field, 0, ""}, + {"Log2phys_t.Devoffset", Field, 0, ""}, + {"Log2phys_t.Flags", Field, 0, ""}, + {"LookupAccountName", Func, 0, ""}, + {"LookupAccountSid", Func, 0, ""}, + {"LookupSID", Func, 0, ""}, + {"LsfJump", Func, 0, "func(code int, k int, jt int, jf int) *SockFilter"}, + {"LsfSocket", Func, 0, "func(ifindex int, proto int) (int, error)"}, + {"LsfStmt", Func, 0, "func(code int, k int) *SockFilter"}, + {"Lstat", Func, 0, "func(path string, stat *Stat_t) (err error)"}, + {"MADV_AUTOSYNC", Const, 1, ""}, + {"MADV_CAN_REUSE", Const, 0, ""}, + {"MADV_CORE", Const, 1, ""}, + {"MADV_DOFORK", Const, 0, ""}, + {"MADV_DONTFORK", Const, 0, ""}, + {"MADV_DONTNEED", Const, 0, ""}, + {"MADV_FREE", Const, 0, ""}, + {"MADV_FREE_REUSABLE", Const, 0, ""}, + {"MADV_FREE_REUSE", Const, 0, ""}, + {"MADV_HUGEPAGE", Const, 0, ""}, + {"MADV_HWPOISON", Const, 0, ""}, + {"MADV_MERGEABLE", Const, 0, ""}, + {"MADV_NOCORE", Const, 1, ""}, + {"MADV_NOHUGEPAGE", Const, 0, ""}, + {"MADV_NORMAL", Const, 0, ""}, + {"MADV_NOSYNC", Const, 1, ""}, + {"MADV_PROTECT", Const, 1, ""}, + {"MADV_RANDOM", Const, 0, ""}, + {"MADV_REMOVE", Const, 0, ""}, + {"MADV_SEQUENTIAL", Const, 0, ""}, + {"MADV_SPACEAVAIL", Const, 3, ""}, + {"MADV_UNMERGEABLE", Const, 0, ""}, + {"MADV_WILLNEED", Const, 0, ""}, + {"MADV_ZERO_WIRED_PAGES", Const, 0, ""}, + {"MAP_32BIT", Const, 0, ""}, + {"MAP_ALIGNED_SUPER", Const, 3, ""}, + {"MAP_ALIGNMENT_16MB", Const, 3, ""}, + {"MAP_ALIGNMENT_1TB", Const, 3, ""}, + {"MAP_ALIGNMENT_256TB", Const, 3, ""}, + {"MAP_ALIGNMENT_4GB", Const, 3, ""}, + {"MAP_ALIGNMENT_64KB", Const, 3, ""}, + {"MAP_ALIGNMENT_64PB", Const, 3, ""}, + {"MAP_ALIGNMENT_MASK", Const, 3, ""}, + {"MAP_ALIGNMENT_SHIFT", Const, 3, ""}, + {"MAP_ANON", Const, 0, ""}, + {"MAP_ANONYMOUS", Const, 0, ""}, + {"MAP_COPY", Const, 0, ""}, + {"MAP_DENYWRITE", Const, 0, ""}, + {"MAP_EXECUTABLE", Const, 0, ""}, + {"MAP_FILE", Const, 0, ""}, + {"MAP_FIXED", Const, 0, ""}, + {"MAP_FLAGMASK", Const, 3, ""}, + {"MAP_GROWSDOWN", Const, 0, ""}, + {"MAP_HASSEMAPHORE", Const, 0, ""}, + {"MAP_HUGETLB", Const, 0, ""}, + {"MAP_INHERIT", Const, 3, ""}, + {"MAP_INHERIT_COPY", Const, 3, ""}, + {"MAP_INHERIT_DEFAULT", Const, 3, ""}, + {"MAP_INHERIT_DONATE_COPY", Const, 3, ""}, + {"MAP_INHERIT_NONE", Const, 3, ""}, + {"MAP_INHERIT_SHARE", Const, 3, ""}, + {"MAP_JIT", Const, 0, ""}, + {"MAP_LOCKED", Const, 0, ""}, + {"MAP_NOCACHE", Const, 0, ""}, + {"MAP_NOCORE", Const, 1, ""}, + {"MAP_NOEXTEND", Const, 0, ""}, + {"MAP_NONBLOCK", Const, 0, ""}, + {"MAP_NORESERVE", Const, 0, ""}, + {"MAP_NOSYNC", Const, 1, ""}, + {"MAP_POPULATE", Const, 0, ""}, + {"MAP_PREFAULT_READ", Const, 1, ""}, + {"MAP_PRIVATE", Const, 0, ""}, + {"MAP_RENAME", Const, 0, ""}, + {"MAP_RESERVED0080", Const, 0, ""}, + {"MAP_RESERVED0100", Const, 1, ""}, + {"MAP_SHARED", Const, 0, ""}, + {"MAP_STACK", Const, 0, ""}, + {"MAP_TRYFIXED", Const, 3, ""}, + {"MAP_TYPE", Const, 0, ""}, + {"MAP_WIRED", Const, 3, ""}, + {"MAXIMUM_REPARSE_DATA_BUFFER_SIZE", Const, 4, ""}, + {"MAXLEN_IFDESCR", Const, 0, ""}, + {"MAXLEN_PHYSADDR", Const, 0, ""}, + {"MAX_ADAPTER_ADDRESS_LENGTH", Const, 0, ""}, + {"MAX_ADAPTER_DESCRIPTION_LENGTH", Const, 0, ""}, + {"MAX_ADAPTER_NAME_LENGTH", Const, 0, ""}, + {"MAX_COMPUTERNAME_LENGTH", Const, 0, ""}, + {"MAX_INTERFACE_NAME_LEN", Const, 0, ""}, + {"MAX_LONG_PATH", Const, 0, ""}, + {"MAX_PATH", Const, 0, ""}, + {"MAX_PROTOCOL_CHAIN", Const, 2, ""}, + {"MCL_CURRENT", Const, 0, ""}, + {"MCL_FUTURE", Const, 0, ""}, + {"MNT_DETACH", Const, 0, ""}, + {"MNT_EXPIRE", Const, 0, ""}, + {"MNT_FORCE", Const, 0, ""}, + {"MSG_BCAST", Const, 1, ""}, + {"MSG_CMSG_CLOEXEC", Const, 0, ""}, + {"MSG_COMPAT", Const, 0, ""}, + {"MSG_CONFIRM", Const, 0, ""}, + {"MSG_CONTROLMBUF", Const, 1, ""}, + {"MSG_CTRUNC", Const, 0, ""}, + {"MSG_DONTROUTE", Const, 0, ""}, + {"MSG_DONTWAIT", Const, 0, ""}, + {"MSG_EOF", Const, 0, ""}, + {"MSG_EOR", Const, 0, ""}, + {"MSG_ERRQUEUE", Const, 0, ""}, + {"MSG_FASTOPEN", Const, 1, ""}, + {"MSG_FIN", Const, 0, ""}, + {"MSG_FLUSH", Const, 0, ""}, + {"MSG_HAVEMORE", Const, 0, ""}, + {"MSG_HOLD", Const, 0, ""}, + {"MSG_IOVUSRSPACE", Const, 1, ""}, + {"MSG_LENUSRSPACE", Const, 1, ""}, + {"MSG_MCAST", Const, 1, ""}, + {"MSG_MORE", Const, 0, ""}, + {"MSG_NAMEMBUF", Const, 1, ""}, + {"MSG_NBIO", Const, 0, ""}, + {"MSG_NEEDSA", Const, 0, ""}, + {"MSG_NOSIGNAL", Const, 0, ""}, + {"MSG_NOTIFICATION", Const, 0, ""}, + {"MSG_OOB", Const, 0, ""}, + {"MSG_PEEK", Const, 0, ""}, + {"MSG_PROXY", Const, 0, ""}, + {"MSG_RCVMORE", Const, 0, ""}, + {"MSG_RST", Const, 0, ""}, + {"MSG_SEND", Const, 0, ""}, + {"MSG_SYN", Const, 0, ""}, + {"MSG_TRUNC", Const, 0, ""}, + {"MSG_TRYHARD", Const, 0, ""}, + {"MSG_USERFLAGS", Const, 1, ""}, + {"MSG_WAITALL", Const, 0, ""}, + {"MSG_WAITFORONE", Const, 0, ""}, + {"MSG_WAITSTREAM", Const, 0, ""}, + {"MS_ACTIVE", Const, 0, ""}, + {"MS_ASYNC", Const, 0, ""}, + {"MS_BIND", Const, 0, ""}, + {"MS_DEACTIVATE", Const, 0, ""}, + {"MS_DIRSYNC", Const, 0, ""}, + {"MS_INVALIDATE", Const, 0, ""}, + {"MS_I_VERSION", Const, 0, ""}, + {"MS_KERNMOUNT", Const, 0, ""}, + {"MS_KILLPAGES", Const, 0, ""}, + {"MS_MANDLOCK", Const, 0, ""}, + {"MS_MGC_MSK", Const, 0, ""}, + {"MS_MGC_VAL", Const, 0, ""}, + {"MS_MOVE", Const, 0, ""}, + {"MS_NOATIME", Const, 0, ""}, + {"MS_NODEV", Const, 0, ""}, + {"MS_NODIRATIME", Const, 0, ""}, + {"MS_NOEXEC", Const, 0, ""}, + {"MS_NOSUID", Const, 0, ""}, + {"MS_NOUSER", Const, 0, ""}, + {"MS_POSIXACL", Const, 0, ""}, + {"MS_PRIVATE", Const, 0, ""}, + {"MS_RDONLY", Const, 0, ""}, + {"MS_REC", Const, 0, ""}, + {"MS_RELATIME", Const, 0, ""}, + {"MS_REMOUNT", Const, 0, ""}, + {"MS_RMT_MASK", Const, 0, ""}, + {"MS_SHARED", Const, 0, ""}, + {"MS_SILENT", Const, 0, ""}, + {"MS_SLAVE", Const, 0, ""}, + {"MS_STRICTATIME", Const, 0, ""}, + {"MS_SYNC", Const, 0, ""}, + {"MS_SYNCHRONOUS", Const, 0, ""}, + {"MS_UNBINDABLE", Const, 0, ""}, + {"Madvise", Func, 0, "func(b []byte, advice int) (err error)"}, + {"MapViewOfFile", Func, 0, ""}, + {"MaxTokenInfoClass", Const, 0, ""}, + {"Mclpool", Type, 2, ""}, + {"Mclpool.Alive", Field, 2, ""}, + {"Mclpool.Cwm", Field, 2, ""}, + {"Mclpool.Grown", Field, 2, ""}, + {"Mclpool.Hwm", Field, 2, ""}, + {"Mclpool.Lwm", Field, 2, ""}, + {"MibIfRow", Type, 0, ""}, + {"MibIfRow.AdminStatus", Field, 0, ""}, + {"MibIfRow.Descr", Field, 0, ""}, + {"MibIfRow.DescrLen", Field, 0, ""}, + {"MibIfRow.InDiscards", Field, 0, ""}, + {"MibIfRow.InErrors", Field, 0, ""}, + {"MibIfRow.InNUcastPkts", Field, 0, ""}, + {"MibIfRow.InOctets", Field, 0, ""}, + {"MibIfRow.InUcastPkts", Field, 0, ""}, + {"MibIfRow.InUnknownProtos", Field, 0, ""}, + {"MibIfRow.Index", Field, 0, ""}, + {"MibIfRow.LastChange", Field, 0, ""}, + {"MibIfRow.Mtu", Field, 0, ""}, + {"MibIfRow.Name", Field, 0, ""}, + {"MibIfRow.OperStatus", Field, 0, ""}, + {"MibIfRow.OutDiscards", Field, 0, ""}, + {"MibIfRow.OutErrors", Field, 0, ""}, + {"MibIfRow.OutNUcastPkts", Field, 0, ""}, + {"MibIfRow.OutOctets", Field, 0, ""}, + {"MibIfRow.OutQLen", Field, 0, ""}, + {"MibIfRow.OutUcastPkts", Field, 0, ""}, + {"MibIfRow.PhysAddr", Field, 0, ""}, + {"MibIfRow.PhysAddrLen", Field, 0, ""}, + {"MibIfRow.Speed", Field, 0, ""}, + {"MibIfRow.Type", Field, 0, ""}, + {"Mkdir", Func, 0, "func(path string, mode uint32) (err error)"}, + {"Mkdirat", Func, 0, "func(dirfd int, path string, mode uint32) (err error)"}, + {"Mkfifo", Func, 0, "func(path string, mode uint32) (err error)"}, + {"Mknod", Func, 0, "func(path string, mode uint32, dev int) (err error)"}, + {"Mknodat", Func, 0, "func(dirfd int, path string, mode uint32, dev int) (err error)"}, + {"Mlock", Func, 0, "func(b []byte) (err error)"}, + {"Mlockall", Func, 0, "func(flags int) (err error)"}, + {"Mmap", Func, 0, "func(fd int, offset int64, length int, prot int, flags int) (data []byte, err error)"}, + {"Mount", Func, 0, "func(source string, target string, fstype string, flags uintptr, data string) (err error)"}, + {"MoveFile", Func, 0, ""}, + {"Mprotect", Func, 0, "func(b []byte, prot int) (err error)"}, + {"Msghdr", Type, 0, ""}, + {"Msghdr.Control", Field, 0, ""}, + {"Msghdr.Controllen", Field, 0, ""}, + {"Msghdr.Flags", Field, 0, ""}, + {"Msghdr.Iov", Field, 0, ""}, + {"Msghdr.Iovlen", Field, 0, ""}, + {"Msghdr.Name", Field, 0, ""}, + {"Msghdr.Namelen", Field, 0, ""}, + {"Msghdr.Pad_cgo_0", Field, 0, ""}, + {"Msghdr.Pad_cgo_1", Field, 0, ""}, + {"Munlock", Func, 0, "func(b []byte) (err error)"}, + {"Munlockall", Func, 0, "func() (err error)"}, + {"Munmap", Func, 0, "func(b []byte) (err error)"}, + {"MustLoadDLL", Func, 0, ""}, + {"NAME_MAX", Const, 0, ""}, + {"NETLINK_ADD_MEMBERSHIP", Const, 0, ""}, + {"NETLINK_AUDIT", Const, 0, ""}, + {"NETLINK_BROADCAST_ERROR", Const, 0, ""}, + {"NETLINK_CONNECTOR", Const, 0, ""}, + {"NETLINK_DNRTMSG", Const, 0, ""}, + {"NETLINK_DROP_MEMBERSHIP", Const, 0, ""}, + {"NETLINK_ECRYPTFS", Const, 0, ""}, + {"NETLINK_FIB_LOOKUP", Const, 0, ""}, + {"NETLINK_FIREWALL", Const, 0, ""}, + {"NETLINK_GENERIC", Const, 0, ""}, + {"NETLINK_INET_DIAG", Const, 0, ""}, + {"NETLINK_IP6_FW", Const, 0, ""}, + {"NETLINK_ISCSI", Const, 0, ""}, + {"NETLINK_KOBJECT_UEVENT", Const, 0, ""}, + {"NETLINK_NETFILTER", Const, 0, ""}, + {"NETLINK_NFLOG", Const, 0, ""}, + {"NETLINK_NO_ENOBUFS", Const, 0, ""}, + {"NETLINK_PKTINFO", Const, 0, ""}, + {"NETLINK_RDMA", Const, 0, ""}, + {"NETLINK_ROUTE", Const, 0, ""}, + {"NETLINK_SCSITRANSPORT", Const, 0, ""}, + {"NETLINK_SELINUX", Const, 0, ""}, + {"NETLINK_UNUSED", Const, 0, ""}, + {"NETLINK_USERSOCK", Const, 0, ""}, + {"NETLINK_XFRM", Const, 0, ""}, + {"NET_RT_DUMP", Const, 0, ""}, + {"NET_RT_DUMP2", Const, 0, ""}, + {"NET_RT_FLAGS", Const, 0, ""}, + {"NET_RT_IFLIST", Const, 0, ""}, + {"NET_RT_IFLIST2", Const, 0, ""}, + {"NET_RT_IFLISTL", Const, 1, ""}, + {"NET_RT_IFMALIST", Const, 0, ""}, + {"NET_RT_MAXID", Const, 0, ""}, + {"NET_RT_OIFLIST", Const, 1, ""}, + {"NET_RT_OOIFLIST", Const, 1, ""}, + {"NET_RT_STAT", Const, 0, ""}, + {"NET_RT_STATS", Const, 1, ""}, + {"NET_RT_TABLE", Const, 1, ""}, + {"NET_RT_TRASH", Const, 0, ""}, + {"NLA_ALIGNTO", Const, 0, ""}, + {"NLA_F_NESTED", Const, 0, ""}, + {"NLA_F_NET_BYTEORDER", Const, 0, ""}, + {"NLA_HDRLEN", Const, 0, ""}, + {"NLMSG_ALIGNTO", Const, 0, ""}, + {"NLMSG_DONE", Const, 0, ""}, + {"NLMSG_ERROR", Const, 0, ""}, + {"NLMSG_HDRLEN", Const, 0, ""}, + {"NLMSG_MIN_TYPE", Const, 0, ""}, + {"NLMSG_NOOP", Const, 0, ""}, + {"NLMSG_OVERRUN", Const, 0, ""}, + {"NLM_F_ACK", Const, 0, ""}, + {"NLM_F_APPEND", Const, 0, ""}, + {"NLM_F_ATOMIC", Const, 0, ""}, + {"NLM_F_CREATE", Const, 0, ""}, + {"NLM_F_DUMP", Const, 0, ""}, + {"NLM_F_ECHO", Const, 0, ""}, + {"NLM_F_EXCL", Const, 0, ""}, + {"NLM_F_MATCH", Const, 0, ""}, + {"NLM_F_MULTI", Const, 0, ""}, + {"NLM_F_REPLACE", Const, 0, ""}, + {"NLM_F_REQUEST", Const, 0, ""}, + {"NLM_F_ROOT", Const, 0, ""}, + {"NOFLSH", Const, 0, ""}, + {"NOTE_ABSOLUTE", Const, 0, ""}, + {"NOTE_ATTRIB", Const, 0, ""}, + {"NOTE_BACKGROUND", Const, 16, ""}, + {"NOTE_CHILD", Const, 0, ""}, + {"NOTE_CRITICAL", Const, 16, ""}, + {"NOTE_DELETE", Const, 0, ""}, + {"NOTE_EOF", Const, 1, ""}, + {"NOTE_EXEC", Const, 0, ""}, + {"NOTE_EXIT", Const, 0, ""}, + {"NOTE_EXITSTATUS", Const, 0, ""}, + {"NOTE_EXIT_CSERROR", Const, 16, ""}, + {"NOTE_EXIT_DECRYPTFAIL", Const, 16, ""}, + {"NOTE_EXIT_DETAIL", Const, 16, ""}, + {"NOTE_EXIT_DETAIL_MASK", Const, 16, ""}, + {"NOTE_EXIT_MEMORY", Const, 16, ""}, + {"NOTE_EXIT_REPARENTED", Const, 16, ""}, + {"NOTE_EXTEND", Const, 0, ""}, + {"NOTE_FFAND", Const, 0, ""}, + {"NOTE_FFCOPY", Const, 0, ""}, + {"NOTE_FFCTRLMASK", Const, 0, ""}, + {"NOTE_FFLAGSMASK", Const, 0, ""}, + {"NOTE_FFNOP", Const, 0, ""}, + {"NOTE_FFOR", Const, 0, ""}, + {"NOTE_FORK", Const, 0, ""}, + {"NOTE_LEEWAY", Const, 16, ""}, + {"NOTE_LINK", Const, 0, ""}, + {"NOTE_LOWAT", Const, 0, ""}, + {"NOTE_NONE", Const, 0, ""}, + {"NOTE_NSECONDS", Const, 0, ""}, + {"NOTE_PCTRLMASK", Const, 0, ""}, + {"NOTE_PDATAMASK", Const, 0, ""}, + {"NOTE_REAP", Const, 0, ""}, + {"NOTE_RENAME", Const, 0, ""}, + {"NOTE_RESOURCEEND", Const, 0, ""}, + {"NOTE_REVOKE", Const, 0, ""}, + {"NOTE_SECONDS", Const, 0, ""}, + {"NOTE_SIGNAL", Const, 0, ""}, + {"NOTE_TRACK", Const, 0, ""}, + {"NOTE_TRACKERR", Const, 0, ""}, + {"NOTE_TRIGGER", Const, 0, ""}, + {"NOTE_TRUNCATE", Const, 1, ""}, + {"NOTE_USECONDS", Const, 0, ""}, + {"NOTE_VM_ERROR", Const, 0, ""}, + {"NOTE_VM_PRESSURE", Const, 0, ""}, + {"NOTE_VM_PRESSURE_SUDDEN_TERMINATE", Const, 0, ""}, + {"NOTE_VM_PRESSURE_TERMINATE", Const, 0, ""}, + {"NOTE_WRITE", Const, 0, ""}, + {"NameCanonical", Const, 0, ""}, + {"NameCanonicalEx", Const, 0, ""}, + {"NameDisplay", Const, 0, ""}, + {"NameDnsDomain", Const, 0, ""}, + {"NameFullyQualifiedDN", Const, 0, ""}, + {"NameSamCompatible", Const, 0, ""}, + {"NameServicePrincipal", Const, 0, ""}, + {"NameUniqueId", Const, 0, ""}, + {"NameUnknown", Const, 0, ""}, + {"NameUserPrincipal", Const, 0, ""}, + {"Nanosleep", Func, 0, "func(time *Timespec, leftover *Timespec) (err error)"}, + {"NetApiBufferFree", Func, 0, ""}, + {"NetGetJoinInformation", Func, 2, ""}, + {"NetSetupDomainName", Const, 2, ""}, + {"NetSetupUnjoined", Const, 2, ""}, + {"NetSetupUnknownStatus", Const, 2, ""}, + {"NetSetupWorkgroupName", Const, 2, ""}, + {"NetUserGetInfo", Func, 0, ""}, + {"NetlinkMessage", Type, 0, ""}, + {"NetlinkMessage.Data", Field, 0, ""}, + {"NetlinkMessage.Header", Field, 0, ""}, + {"NetlinkRIB", Func, 0, "func(proto int, family int) ([]byte, error)"}, + {"NetlinkRouteAttr", Type, 0, ""}, + {"NetlinkRouteAttr.Attr", Field, 0, ""}, + {"NetlinkRouteAttr.Value", Field, 0, ""}, + {"NetlinkRouteRequest", Type, 0, ""}, + {"NetlinkRouteRequest.Data", Field, 0, ""}, + {"NetlinkRouteRequest.Header", Field, 0, ""}, + {"NewCallback", Func, 0, ""}, + {"NewCallbackCDecl", Func, 3, ""}, + {"NewLazyDLL", Func, 0, ""}, + {"NlAttr", Type, 0, ""}, + {"NlAttr.Len", Field, 0, ""}, + {"NlAttr.Type", Field, 0, ""}, + {"NlMsgerr", Type, 0, ""}, + {"NlMsgerr.Error", Field, 0, ""}, + {"NlMsgerr.Msg", Field, 0, ""}, + {"NlMsghdr", Type, 0, ""}, + {"NlMsghdr.Flags", Field, 0, ""}, + {"NlMsghdr.Len", Field, 0, ""}, + {"NlMsghdr.Pid", Field, 0, ""}, + {"NlMsghdr.Seq", Field, 0, ""}, + {"NlMsghdr.Type", Field, 0, ""}, + {"NsecToFiletime", Func, 0, ""}, + {"NsecToTimespec", Func, 0, "func(nsec int64) Timespec"}, + {"NsecToTimeval", Func, 0, "func(nsec int64) Timeval"}, + {"Ntohs", Func, 0, ""}, + {"OCRNL", Const, 0, ""}, + {"OFDEL", Const, 0, ""}, + {"OFILL", Const, 0, ""}, + {"OFIOGETBMAP", Const, 1, ""}, + {"OID_PKIX_KP_SERVER_AUTH", Var, 0, ""}, + {"OID_SERVER_GATED_CRYPTO", Var, 0, ""}, + {"OID_SGC_NETSCAPE", Var, 0, ""}, + {"OLCUC", Const, 0, ""}, + {"ONLCR", Const, 0, ""}, + {"ONLRET", Const, 0, ""}, + {"ONOCR", Const, 0, ""}, + {"ONOEOT", Const, 1, ""}, + {"OPEN_ALWAYS", Const, 0, ""}, + {"OPEN_EXISTING", Const, 0, ""}, + {"OPOST", Const, 0, ""}, + {"O_ACCMODE", Const, 0, ""}, + {"O_ALERT", Const, 0, ""}, + {"O_ALT_IO", Const, 1, ""}, + {"O_APPEND", Const, 0, ""}, + {"O_ASYNC", Const, 0, ""}, + {"O_CLOEXEC", Const, 0, ""}, + {"O_CREAT", Const, 0, ""}, + {"O_DIRECT", Const, 0, ""}, + {"O_DIRECTORY", Const, 0, ""}, + {"O_DP_GETRAWENCRYPTED", Const, 16, ""}, + {"O_DSYNC", Const, 0, ""}, + {"O_EVTONLY", Const, 0, ""}, + {"O_EXCL", Const, 0, ""}, + {"O_EXEC", Const, 0, ""}, + {"O_EXLOCK", Const, 0, ""}, + {"O_FSYNC", Const, 0, ""}, + {"O_LARGEFILE", Const, 0, ""}, + {"O_NDELAY", Const, 0, ""}, + {"O_NOATIME", Const, 0, ""}, + {"O_NOCTTY", Const, 0, ""}, + {"O_NOFOLLOW", Const, 0, ""}, + {"O_NONBLOCK", Const, 0, ""}, + {"O_NOSIGPIPE", Const, 1, ""}, + {"O_POPUP", Const, 0, ""}, + {"O_RDONLY", Const, 0, ""}, + {"O_RDWR", Const, 0, ""}, + {"O_RSYNC", Const, 0, ""}, + {"O_SHLOCK", Const, 0, ""}, + {"O_SYMLINK", Const, 0, ""}, + {"O_SYNC", Const, 0, ""}, + {"O_TRUNC", Const, 0, ""}, + {"O_TTY_INIT", Const, 0, ""}, + {"O_WRONLY", Const, 0, ""}, + {"Open", Func, 0, "func(path string, mode int, perm uint32) (fd int, err error)"}, + {"OpenCurrentProcessToken", Func, 0, ""}, + {"OpenProcess", Func, 0, ""}, + {"OpenProcessToken", Func, 0, ""}, + {"Openat", Func, 0, "func(dirfd int, path string, flags int, mode uint32) (fd int, err error)"}, + {"Overlapped", Type, 0, ""}, + {"Overlapped.HEvent", Field, 0, ""}, + {"Overlapped.Internal", Field, 0, ""}, + {"Overlapped.InternalHigh", Field, 0, ""}, + {"Overlapped.Offset", Field, 0, ""}, + {"Overlapped.OffsetHigh", Field, 0, ""}, + {"PACKET_ADD_MEMBERSHIP", Const, 0, ""}, + {"PACKET_BROADCAST", Const, 0, ""}, + {"PACKET_DROP_MEMBERSHIP", Const, 0, ""}, + {"PACKET_FASTROUTE", Const, 0, ""}, + {"PACKET_HOST", Const, 0, ""}, + {"PACKET_LOOPBACK", Const, 0, ""}, + {"PACKET_MR_ALLMULTI", Const, 0, ""}, + {"PACKET_MR_MULTICAST", Const, 0, ""}, + {"PACKET_MR_PROMISC", Const, 0, ""}, + {"PACKET_MULTICAST", Const, 0, ""}, + {"PACKET_OTHERHOST", Const, 0, ""}, + {"PACKET_OUTGOING", Const, 0, ""}, + {"PACKET_RECV_OUTPUT", Const, 0, ""}, + {"PACKET_RX_RING", Const, 0, ""}, + {"PACKET_STATISTICS", Const, 0, ""}, + {"PAGE_EXECUTE_READ", Const, 0, ""}, + {"PAGE_EXECUTE_READWRITE", Const, 0, ""}, + {"PAGE_EXECUTE_WRITECOPY", Const, 0, ""}, + {"PAGE_READONLY", Const, 0, ""}, + {"PAGE_READWRITE", Const, 0, ""}, + {"PAGE_WRITECOPY", Const, 0, ""}, + {"PARENB", Const, 0, ""}, + {"PARMRK", Const, 0, ""}, + {"PARODD", Const, 0, ""}, + {"PENDIN", Const, 0, ""}, + {"PFL_HIDDEN", Const, 2, ""}, + {"PFL_MATCHES_PROTOCOL_ZERO", Const, 2, ""}, + {"PFL_MULTIPLE_PROTO_ENTRIES", Const, 2, ""}, + {"PFL_NETWORKDIRECT_PROVIDER", Const, 2, ""}, + {"PFL_RECOMMENDED_PROTO_ENTRY", Const, 2, ""}, + {"PF_FLUSH", Const, 1, ""}, + {"PKCS_7_ASN_ENCODING", Const, 0, ""}, + {"PMC5_PIPELINE_FLUSH", Const, 1, ""}, + {"PRIO_PGRP", Const, 2, ""}, + {"PRIO_PROCESS", Const, 2, ""}, + {"PRIO_USER", Const, 2, ""}, + {"PRI_IOFLUSH", Const, 1, ""}, + {"PROCESS_QUERY_INFORMATION", Const, 0, ""}, + {"PROCESS_TERMINATE", Const, 2, ""}, + {"PROT_EXEC", Const, 0, ""}, + {"PROT_GROWSDOWN", Const, 0, ""}, + {"PROT_GROWSUP", Const, 0, ""}, + {"PROT_NONE", Const, 0, ""}, + {"PROT_READ", Const, 0, ""}, + {"PROT_WRITE", Const, 0, ""}, + {"PROV_DH_SCHANNEL", Const, 0, ""}, + {"PROV_DSS", Const, 0, ""}, + {"PROV_DSS_DH", Const, 0, ""}, + {"PROV_EC_ECDSA_FULL", Const, 0, ""}, + {"PROV_EC_ECDSA_SIG", Const, 0, ""}, + {"PROV_EC_ECNRA_FULL", Const, 0, ""}, + {"PROV_EC_ECNRA_SIG", Const, 0, ""}, + {"PROV_FORTEZZA", Const, 0, ""}, + {"PROV_INTEL_SEC", Const, 0, ""}, + {"PROV_MS_EXCHANGE", Const, 0, ""}, + {"PROV_REPLACE_OWF", Const, 0, ""}, + {"PROV_RNG", Const, 0, ""}, + {"PROV_RSA_AES", Const, 0, ""}, + {"PROV_RSA_FULL", Const, 0, ""}, + {"PROV_RSA_SCHANNEL", Const, 0, ""}, + {"PROV_RSA_SIG", Const, 0, ""}, + {"PROV_SPYRUS_LYNKS", Const, 0, ""}, + {"PROV_SSL", Const, 0, ""}, + {"PR_CAPBSET_DROP", Const, 0, ""}, + {"PR_CAPBSET_READ", Const, 0, ""}, + {"PR_CLEAR_SECCOMP_FILTER", Const, 0, ""}, + {"PR_ENDIAN_BIG", Const, 0, ""}, + {"PR_ENDIAN_LITTLE", Const, 0, ""}, + {"PR_ENDIAN_PPC_LITTLE", Const, 0, ""}, + {"PR_FPEMU_NOPRINT", Const, 0, ""}, + {"PR_FPEMU_SIGFPE", Const, 0, ""}, + {"PR_FP_EXC_ASYNC", Const, 0, ""}, + {"PR_FP_EXC_DISABLED", Const, 0, ""}, + {"PR_FP_EXC_DIV", Const, 0, ""}, + {"PR_FP_EXC_INV", Const, 0, ""}, + {"PR_FP_EXC_NONRECOV", Const, 0, ""}, + {"PR_FP_EXC_OVF", Const, 0, ""}, + {"PR_FP_EXC_PRECISE", Const, 0, ""}, + {"PR_FP_EXC_RES", Const, 0, ""}, + {"PR_FP_EXC_SW_ENABLE", Const, 0, ""}, + {"PR_FP_EXC_UND", Const, 0, ""}, + {"PR_GET_DUMPABLE", Const, 0, ""}, + {"PR_GET_ENDIAN", Const, 0, ""}, + {"PR_GET_FPEMU", Const, 0, ""}, + {"PR_GET_FPEXC", Const, 0, ""}, + {"PR_GET_KEEPCAPS", Const, 0, ""}, + {"PR_GET_NAME", Const, 0, ""}, + {"PR_GET_PDEATHSIG", Const, 0, ""}, + {"PR_GET_SECCOMP", Const, 0, ""}, + {"PR_GET_SECCOMP_FILTER", Const, 0, ""}, + {"PR_GET_SECUREBITS", Const, 0, ""}, + {"PR_GET_TIMERSLACK", Const, 0, ""}, + {"PR_GET_TIMING", Const, 0, ""}, + {"PR_GET_TSC", Const, 0, ""}, + {"PR_GET_UNALIGN", Const, 0, ""}, + {"PR_MCE_KILL", Const, 0, ""}, + {"PR_MCE_KILL_CLEAR", Const, 0, ""}, + {"PR_MCE_KILL_DEFAULT", Const, 0, ""}, + {"PR_MCE_KILL_EARLY", Const, 0, ""}, + {"PR_MCE_KILL_GET", Const, 0, ""}, + {"PR_MCE_KILL_LATE", Const, 0, ""}, + {"PR_MCE_KILL_SET", Const, 0, ""}, + {"PR_SECCOMP_FILTER_EVENT", Const, 0, ""}, + {"PR_SECCOMP_FILTER_SYSCALL", Const, 0, ""}, + {"PR_SET_DUMPABLE", Const, 0, ""}, + {"PR_SET_ENDIAN", Const, 0, ""}, + {"PR_SET_FPEMU", Const, 0, ""}, + {"PR_SET_FPEXC", Const, 0, ""}, + {"PR_SET_KEEPCAPS", Const, 0, ""}, + {"PR_SET_NAME", Const, 0, ""}, + {"PR_SET_PDEATHSIG", Const, 0, ""}, + {"PR_SET_PTRACER", Const, 0, ""}, + {"PR_SET_SECCOMP", Const, 0, ""}, + {"PR_SET_SECCOMP_FILTER", Const, 0, ""}, + {"PR_SET_SECUREBITS", Const, 0, ""}, + {"PR_SET_TIMERSLACK", Const, 0, ""}, + {"PR_SET_TIMING", Const, 0, ""}, + {"PR_SET_TSC", Const, 0, ""}, + {"PR_SET_UNALIGN", Const, 0, ""}, + {"PR_TASK_PERF_EVENTS_DISABLE", Const, 0, ""}, + {"PR_TASK_PERF_EVENTS_ENABLE", Const, 0, ""}, + {"PR_TIMING_STATISTICAL", Const, 0, ""}, + {"PR_TIMING_TIMESTAMP", Const, 0, ""}, + {"PR_TSC_ENABLE", Const, 0, ""}, + {"PR_TSC_SIGSEGV", Const, 0, ""}, + {"PR_UNALIGN_NOPRINT", Const, 0, ""}, + {"PR_UNALIGN_SIGBUS", Const, 0, ""}, + {"PTRACE_ARCH_PRCTL", Const, 0, ""}, + {"PTRACE_ATTACH", Const, 0, ""}, + {"PTRACE_CONT", Const, 0, ""}, + {"PTRACE_DETACH", Const, 0, ""}, + {"PTRACE_EVENT_CLONE", Const, 0, ""}, + {"PTRACE_EVENT_EXEC", Const, 0, ""}, + {"PTRACE_EVENT_EXIT", Const, 0, ""}, + {"PTRACE_EVENT_FORK", Const, 0, ""}, + {"PTRACE_EVENT_VFORK", Const, 0, ""}, + {"PTRACE_EVENT_VFORK_DONE", Const, 0, ""}, + {"PTRACE_GETCRUNCHREGS", Const, 0, ""}, + {"PTRACE_GETEVENTMSG", Const, 0, ""}, + {"PTRACE_GETFPREGS", Const, 0, ""}, + {"PTRACE_GETFPXREGS", Const, 0, ""}, + {"PTRACE_GETHBPREGS", Const, 0, ""}, + {"PTRACE_GETREGS", Const, 0, ""}, + {"PTRACE_GETREGSET", Const, 0, ""}, + {"PTRACE_GETSIGINFO", Const, 0, ""}, + {"PTRACE_GETVFPREGS", Const, 0, ""}, + {"PTRACE_GETWMMXREGS", Const, 0, ""}, + {"PTRACE_GET_THREAD_AREA", Const, 0, ""}, + {"PTRACE_KILL", Const, 0, ""}, + {"PTRACE_OLDSETOPTIONS", Const, 0, ""}, + {"PTRACE_O_MASK", Const, 0, ""}, + {"PTRACE_O_TRACECLONE", Const, 0, ""}, + {"PTRACE_O_TRACEEXEC", Const, 0, ""}, + {"PTRACE_O_TRACEEXIT", Const, 0, ""}, + {"PTRACE_O_TRACEFORK", Const, 0, ""}, + {"PTRACE_O_TRACESYSGOOD", Const, 0, ""}, + {"PTRACE_O_TRACEVFORK", Const, 0, ""}, + {"PTRACE_O_TRACEVFORKDONE", Const, 0, ""}, + {"PTRACE_PEEKDATA", Const, 0, ""}, + {"PTRACE_PEEKTEXT", Const, 0, ""}, + {"PTRACE_PEEKUSR", Const, 0, ""}, + {"PTRACE_POKEDATA", Const, 0, ""}, + {"PTRACE_POKETEXT", Const, 0, ""}, + {"PTRACE_POKEUSR", Const, 0, ""}, + {"PTRACE_SETCRUNCHREGS", Const, 0, ""}, + {"PTRACE_SETFPREGS", Const, 0, ""}, + {"PTRACE_SETFPXREGS", Const, 0, ""}, + {"PTRACE_SETHBPREGS", Const, 0, ""}, + {"PTRACE_SETOPTIONS", Const, 0, ""}, + {"PTRACE_SETREGS", Const, 0, ""}, + {"PTRACE_SETREGSET", Const, 0, ""}, + {"PTRACE_SETSIGINFO", Const, 0, ""}, + {"PTRACE_SETVFPREGS", Const, 0, ""}, + {"PTRACE_SETWMMXREGS", Const, 0, ""}, + {"PTRACE_SET_SYSCALL", Const, 0, ""}, + {"PTRACE_SET_THREAD_AREA", Const, 0, ""}, + {"PTRACE_SINGLEBLOCK", Const, 0, ""}, + {"PTRACE_SINGLESTEP", Const, 0, ""}, + {"PTRACE_SYSCALL", Const, 0, ""}, + {"PTRACE_SYSEMU", Const, 0, ""}, + {"PTRACE_SYSEMU_SINGLESTEP", Const, 0, ""}, + {"PTRACE_TRACEME", Const, 0, ""}, + {"PT_ATTACH", Const, 0, ""}, + {"PT_ATTACHEXC", Const, 0, ""}, + {"PT_CONTINUE", Const, 0, ""}, + {"PT_DATA_ADDR", Const, 0, ""}, + {"PT_DENY_ATTACH", Const, 0, ""}, + {"PT_DETACH", Const, 0, ""}, + {"PT_FIRSTMACH", Const, 0, ""}, + {"PT_FORCEQUOTA", Const, 0, ""}, + {"PT_KILL", Const, 0, ""}, + {"PT_MASK", Const, 1, ""}, + {"PT_READ_D", Const, 0, ""}, + {"PT_READ_I", Const, 0, ""}, + {"PT_READ_U", Const, 0, ""}, + {"PT_SIGEXC", Const, 0, ""}, + {"PT_STEP", Const, 0, ""}, + {"PT_TEXT_ADDR", Const, 0, ""}, + {"PT_TEXT_END_ADDR", Const, 0, ""}, + {"PT_THUPDATE", Const, 0, ""}, + {"PT_TRACE_ME", Const, 0, ""}, + {"PT_WRITE_D", Const, 0, ""}, + {"PT_WRITE_I", Const, 0, ""}, + {"PT_WRITE_U", Const, 0, ""}, + {"ParseDirent", Func, 0, "func(buf []byte, max int, names []string) (consumed int, count int, newnames []string)"}, + {"ParseNetlinkMessage", Func, 0, "func(b []byte) ([]NetlinkMessage, error)"}, + {"ParseNetlinkRouteAttr", Func, 0, "func(m *NetlinkMessage) ([]NetlinkRouteAttr, error)"}, + {"ParseRoutingMessage", Func, 0, ""}, + {"ParseRoutingSockaddr", Func, 0, ""}, + {"ParseSocketControlMessage", Func, 0, "func(b []byte) ([]SocketControlMessage, error)"}, + {"ParseUnixCredentials", Func, 0, "func(m *SocketControlMessage) (*Ucred, error)"}, + {"ParseUnixRights", Func, 0, "func(m *SocketControlMessage) ([]int, error)"}, + {"PathMax", Const, 0, ""}, + {"Pathconf", Func, 0, ""}, + {"Pause", Func, 0, "func() (err error)"}, + {"Pipe", Func, 0, "func(p []int) error"}, + {"Pipe2", Func, 1, "func(p []int, flags int) error"}, + {"PivotRoot", Func, 0, "func(newroot string, putold string) (err error)"}, + {"Pointer", Type, 11, ""}, + {"PostQueuedCompletionStatus", Func, 0, ""}, + {"Pread", Func, 0, "func(fd int, p []byte, offset int64) (n int, err error)"}, + {"Proc", Type, 0, ""}, + {"Proc.Dll", Field, 0, ""}, + {"Proc.Name", Field, 0, ""}, + {"ProcAttr", Type, 0, ""}, + {"ProcAttr.Dir", Field, 0, ""}, + {"ProcAttr.Env", Field, 0, ""}, + {"ProcAttr.Files", Field, 0, ""}, + {"ProcAttr.Sys", Field, 0, ""}, + {"Process32First", Func, 4, ""}, + {"Process32Next", Func, 4, ""}, + {"ProcessEntry32", Type, 4, ""}, + {"ProcessEntry32.DefaultHeapID", Field, 4, ""}, + {"ProcessEntry32.ExeFile", Field, 4, ""}, + {"ProcessEntry32.Flags", Field, 4, ""}, + {"ProcessEntry32.ModuleID", Field, 4, ""}, + {"ProcessEntry32.ParentProcessID", Field, 4, ""}, + {"ProcessEntry32.PriClassBase", Field, 4, ""}, + {"ProcessEntry32.ProcessID", Field, 4, ""}, + {"ProcessEntry32.Size", Field, 4, ""}, + {"ProcessEntry32.Threads", Field, 4, ""}, + {"ProcessEntry32.Usage", Field, 4, ""}, + {"ProcessInformation", Type, 0, ""}, + {"ProcessInformation.Process", Field, 0, ""}, + {"ProcessInformation.ProcessId", Field, 0, ""}, + {"ProcessInformation.Thread", Field, 0, ""}, + {"ProcessInformation.ThreadId", Field, 0, ""}, + {"Protoent", Type, 0, ""}, + {"Protoent.Aliases", Field, 0, ""}, + {"Protoent.Name", Field, 0, ""}, + {"Protoent.Proto", Field, 0, ""}, + {"PtraceAttach", Func, 0, "func(pid int) (err error)"}, + {"PtraceCont", Func, 0, "func(pid int, signal int) (err error)"}, + {"PtraceDetach", Func, 0, "func(pid int) (err error)"}, + {"PtraceGetEventMsg", Func, 0, "func(pid int) (msg uint, err error)"}, + {"PtraceGetRegs", Func, 0, "func(pid int, regsout *PtraceRegs) (err error)"}, + {"PtracePeekData", Func, 0, "func(pid int, addr uintptr, out []byte) (count int, err error)"}, + {"PtracePeekText", Func, 0, "func(pid int, addr uintptr, out []byte) (count int, err error)"}, + {"PtracePokeData", Func, 0, "func(pid int, addr uintptr, data []byte) (count int, err error)"}, + {"PtracePokeText", Func, 0, "func(pid int, addr uintptr, data []byte) (count int, err error)"}, + {"PtraceRegs", Type, 0, ""}, + {"PtraceRegs.Cs", Field, 0, ""}, + {"PtraceRegs.Ds", Field, 0, ""}, + {"PtraceRegs.Eax", Field, 0, ""}, + {"PtraceRegs.Ebp", Field, 0, ""}, + {"PtraceRegs.Ebx", Field, 0, ""}, + {"PtraceRegs.Ecx", Field, 0, ""}, + {"PtraceRegs.Edi", Field, 0, ""}, + {"PtraceRegs.Edx", Field, 0, ""}, + {"PtraceRegs.Eflags", Field, 0, ""}, + {"PtraceRegs.Eip", Field, 0, ""}, + {"PtraceRegs.Es", Field, 0, ""}, + {"PtraceRegs.Esi", Field, 0, ""}, + {"PtraceRegs.Esp", Field, 0, ""}, + {"PtraceRegs.Fs", Field, 0, ""}, + {"PtraceRegs.Fs_base", Field, 0, ""}, + {"PtraceRegs.Gs", Field, 0, ""}, + {"PtraceRegs.Gs_base", Field, 0, ""}, + {"PtraceRegs.Orig_eax", Field, 0, ""}, + {"PtraceRegs.Orig_rax", Field, 0, ""}, + {"PtraceRegs.R10", Field, 0, ""}, + {"PtraceRegs.R11", Field, 0, ""}, + {"PtraceRegs.R12", Field, 0, ""}, + {"PtraceRegs.R13", Field, 0, ""}, + {"PtraceRegs.R14", Field, 0, ""}, + {"PtraceRegs.R15", Field, 0, ""}, + {"PtraceRegs.R8", Field, 0, ""}, + {"PtraceRegs.R9", Field, 0, ""}, + {"PtraceRegs.Rax", Field, 0, ""}, + {"PtraceRegs.Rbp", Field, 0, ""}, + {"PtraceRegs.Rbx", Field, 0, ""}, + {"PtraceRegs.Rcx", Field, 0, ""}, + {"PtraceRegs.Rdi", Field, 0, ""}, + {"PtraceRegs.Rdx", Field, 0, ""}, + {"PtraceRegs.Rip", Field, 0, ""}, + {"PtraceRegs.Rsi", Field, 0, ""}, + {"PtraceRegs.Rsp", Field, 0, ""}, + {"PtraceRegs.Ss", Field, 0, ""}, + {"PtraceRegs.Uregs", Field, 0, ""}, + {"PtraceRegs.Xcs", Field, 0, ""}, + {"PtraceRegs.Xds", Field, 0, ""}, + {"PtraceRegs.Xes", Field, 0, ""}, + {"PtraceRegs.Xfs", Field, 0, ""}, + {"PtraceRegs.Xgs", Field, 0, ""}, + {"PtraceRegs.Xss", Field, 0, ""}, + {"PtraceSetOptions", Func, 0, "func(pid int, options int) (err error)"}, + {"PtraceSetRegs", Func, 0, "func(pid int, regs *PtraceRegs) (err error)"}, + {"PtraceSingleStep", Func, 0, "func(pid int) (err error)"}, + {"PtraceSyscall", Func, 1, "func(pid int, signal int) (err error)"}, + {"Pwrite", Func, 0, "func(fd int, p []byte, offset int64) (n int, err error)"}, + {"REG_BINARY", Const, 0, ""}, + {"REG_DWORD", Const, 0, ""}, + {"REG_DWORD_BIG_ENDIAN", Const, 0, ""}, + {"REG_DWORD_LITTLE_ENDIAN", Const, 0, ""}, + {"REG_EXPAND_SZ", Const, 0, ""}, + {"REG_FULL_RESOURCE_DESCRIPTOR", Const, 0, ""}, + {"REG_LINK", Const, 0, ""}, + {"REG_MULTI_SZ", Const, 0, ""}, + {"REG_NONE", Const, 0, ""}, + {"REG_QWORD", Const, 0, ""}, + {"REG_QWORD_LITTLE_ENDIAN", Const, 0, ""}, + {"REG_RESOURCE_LIST", Const, 0, ""}, + {"REG_RESOURCE_REQUIREMENTS_LIST", Const, 0, ""}, + {"REG_SZ", Const, 0, ""}, + {"RLIMIT_AS", Const, 0, ""}, + {"RLIMIT_CORE", Const, 0, ""}, + {"RLIMIT_CPU", Const, 0, ""}, + {"RLIMIT_CPU_USAGE_MONITOR", Const, 16, ""}, + {"RLIMIT_DATA", Const, 0, ""}, + {"RLIMIT_FSIZE", Const, 0, ""}, + {"RLIMIT_NOFILE", Const, 0, ""}, + {"RLIMIT_STACK", Const, 0, ""}, + {"RLIM_INFINITY", Const, 0, ""}, + {"RTAX_ADVMSS", Const, 0, ""}, + {"RTAX_AUTHOR", Const, 0, ""}, + {"RTAX_BRD", Const, 0, ""}, + {"RTAX_CWND", Const, 0, ""}, + {"RTAX_DST", Const, 0, ""}, + {"RTAX_FEATURES", Const, 0, ""}, + {"RTAX_FEATURE_ALLFRAG", Const, 0, ""}, + {"RTAX_FEATURE_ECN", Const, 0, ""}, + {"RTAX_FEATURE_SACK", Const, 0, ""}, + {"RTAX_FEATURE_TIMESTAMP", Const, 0, ""}, + {"RTAX_GATEWAY", Const, 0, ""}, + {"RTAX_GENMASK", Const, 0, ""}, + {"RTAX_HOPLIMIT", Const, 0, ""}, + {"RTAX_IFA", Const, 0, ""}, + {"RTAX_IFP", Const, 0, ""}, + {"RTAX_INITCWND", Const, 0, ""}, + {"RTAX_INITRWND", Const, 0, ""}, + {"RTAX_LABEL", Const, 1, ""}, + {"RTAX_LOCK", Const, 0, ""}, + {"RTAX_MAX", Const, 0, ""}, + {"RTAX_MTU", Const, 0, ""}, + {"RTAX_NETMASK", Const, 0, ""}, + {"RTAX_REORDERING", Const, 0, ""}, + {"RTAX_RTO_MIN", Const, 0, ""}, + {"RTAX_RTT", Const, 0, ""}, + {"RTAX_RTTVAR", Const, 0, ""}, + {"RTAX_SRC", Const, 1, ""}, + {"RTAX_SRCMASK", Const, 1, ""}, + {"RTAX_SSTHRESH", Const, 0, ""}, + {"RTAX_TAG", Const, 1, ""}, + {"RTAX_UNSPEC", Const, 0, ""}, + {"RTAX_WINDOW", Const, 0, ""}, + {"RTA_ALIGNTO", Const, 0, ""}, + {"RTA_AUTHOR", Const, 0, ""}, + {"RTA_BRD", Const, 0, ""}, + {"RTA_CACHEINFO", Const, 0, ""}, + {"RTA_DST", Const, 0, ""}, + {"RTA_FLOW", Const, 0, ""}, + {"RTA_GATEWAY", Const, 0, ""}, + {"RTA_GENMASK", Const, 0, ""}, + {"RTA_IFA", Const, 0, ""}, + {"RTA_IFP", Const, 0, ""}, + {"RTA_IIF", Const, 0, ""}, + {"RTA_LABEL", Const, 1, ""}, + {"RTA_MAX", Const, 0, ""}, + {"RTA_METRICS", Const, 0, ""}, + {"RTA_MULTIPATH", Const, 0, ""}, + {"RTA_NETMASK", Const, 0, ""}, + {"RTA_OIF", Const, 0, ""}, + {"RTA_PREFSRC", Const, 0, ""}, + {"RTA_PRIORITY", Const, 0, ""}, + {"RTA_SRC", Const, 0, ""}, + {"RTA_SRCMASK", Const, 1, ""}, + {"RTA_TABLE", Const, 0, ""}, + {"RTA_TAG", Const, 1, ""}, + {"RTA_UNSPEC", Const, 0, ""}, + {"RTCF_DIRECTSRC", Const, 0, ""}, + {"RTCF_DOREDIRECT", Const, 0, ""}, + {"RTCF_LOG", Const, 0, ""}, + {"RTCF_MASQ", Const, 0, ""}, + {"RTCF_NAT", Const, 0, ""}, + {"RTCF_VALVE", Const, 0, ""}, + {"RTF_ADDRCLASSMASK", Const, 0, ""}, + {"RTF_ADDRCONF", Const, 0, ""}, + {"RTF_ALLONLINK", Const, 0, ""}, + {"RTF_ANNOUNCE", Const, 1, ""}, + {"RTF_BLACKHOLE", Const, 0, ""}, + {"RTF_BROADCAST", Const, 0, ""}, + {"RTF_CACHE", Const, 0, ""}, + {"RTF_CLONED", Const, 1, ""}, + {"RTF_CLONING", Const, 0, ""}, + {"RTF_CONDEMNED", Const, 0, ""}, + {"RTF_DEFAULT", Const, 0, ""}, + {"RTF_DELCLONE", Const, 0, ""}, + {"RTF_DONE", Const, 0, ""}, + {"RTF_DYNAMIC", Const, 0, ""}, + {"RTF_FLOW", Const, 0, ""}, + {"RTF_FMASK", Const, 0, ""}, + {"RTF_GATEWAY", Const, 0, ""}, + {"RTF_GWFLAG_COMPAT", Const, 3, ""}, + {"RTF_HOST", Const, 0, ""}, + {"RTF_IFREF", Const, 0, ""}, + {"RTF_IFSCOPE", Const, 0, ""}, + {"RTF_INTERFACE", Const, 0, ""}, + {"RTF_IRTT", Const, 0, ""}, + {"RTF_LINKRT", Const, 0, ""}, + {"RTF_LLDATA", Const, 0, ""}, + {"RTF_LLINFO", Const, 0, ""}, + {"RTF_LOCAL", Const, 0, ""}, + {"RTF_MASK", Const, 1, ""}, + {"RTF_MODIFIED", Const, 0, ""}, + {"RTF_MPATH", Const, 1, ""}, + {"RTF_MPLS", Const, 1, ""}, + {"RTF_MSS", Const, 0, ""}, + {"RTF_MTU", Const, 0, ""}, + {"RTF_MULTICAST", Const, 0, ""}, + {"RTF_NAT", Const, 0, ""}, + {"RTF_NOFORWARD", Const, 0, ""}, + {"RTF_NONEXTHOP", Const, 0, ""}, + {"RTF_NOPMTUDISC", Const, 0, ""}, + {"RTF_PERMANENT_ARP", Const, 1, ""}, + {"RTF_PINNED", Const, 0, ""}, + {"RTF_POLICY", Const, 0, ""}, + {"RTF_PRCLONING", Const, 0, ""}, + {"RTF_PROTO1", Const, 0, ""}, + {"RTF_PROTO2", Const, 0, ""}, + {"RTF_PROTO3", Const, 0, ""}, + {"RTF_PROXY", Const, 16, ""}, + {"RTF_REINSTATE", Const, 0, ""}, + {"RTF_REJECT", Const, 0, ""}, + {"RTF_RNH_LOCKED", Const, 0, ""}, + {"RTF_ROUTER", Const, 16, ""}, + {"RTF_SOURCE", Const, 1, ""}, + {"RTF_SRC", Const, 1, ""}, + {"RTF_STATIC", Const, 0, ""}, + {"RTF_STICKY", Const, 0, ""}, + {"RTF_THROW", Const, 0, ""}, + {"RTF_TUNNEL", Const, 1, ""}, + {"RTF_UP", Const, 0, ""}, + {"RTF_USETRAILERS", Const, 1, ""}, + {"RTF_WASCLONED", Const, 0, ""}, + {"RTF_WINDOW", Const, 0, ""}, + {"RTF_XRESOLVE", Const, 0, ""}, + {"RTM_ADD", Const, 0, ""}, + {"RTM_BASE", Const, 0, ""}, + {"RTM_CHANGE", Const, 0, ""}, + {"RTM_CHGADDR", Const, 1, ""}, + {"RTM_DELACTION", Const, 0, ""}, + {"RTM_DELADDR", Const, 0, ""}, + {"RTM_DELADDRLABEL", Const, 0, ""}, + {"RTM_DELETE", Const, 0, ""}, + {"RTM_DELLINK", Const, 0, ""}, + {"RTM_DELMADDR", Const, 0, ""}, + {"RTM_DELNEIGH", Const, 0, ""}, + {"RTM_DELQDISC", Const, 0, ""}, + {"RTM_DELROUTE", Const, 0, ""}, + {"RTM_DELRULE", Const, 0, ""}, + {"RTM_DELTCLASS", Const, 0, ""}, + {"RTM_DELTFILTER", Const, 0, ""}, + {"RTM_DESYNC", Const, 1, ""}, + {"RTM_F_CLONED", Const, 0, ""}, + {"RTM_F_EQUALIZE", Const, 0, ""}, + {"RTM_F_NOTIFY", Const, 0, ""}, + {"RTM_F_PREFIX", Const, 0, ""}, + {"RTM_GET", Const, 0, ""}, + {"RTM_GET2", Const, 0, ""}, + {"RTM_GETACTION", Const, 0, ""}, + {"RTM_GETADDR", Const, 0, ""}, + {"RTM_GETADDRLABEL", Const, 0, ""}, + {"RTM_GETANYCAST", Const, 0, ""}, + {"RTM_GETDCB", Const, 0, ""}, + {"RTM_GETLINK", Const, 0, ""}, + {"RTM_GETMULTICAST", Const, 0, ""}, + {"RTM_GETNEIGH", Const, 0, ""}, + {"RTM_GETNEIGHTBL", Const, 0, ""}, + {"RTM_GETQDISC", Const, 0, ""}, + {"RTM_GETROUTE", Const, 0, ""}, + {"RTM_GETRULE", Const, 0, ""}, + {"RTM_GETTCLASS", Const, 0, ""}, + {"RTM_GETTFILTER", Const, 0, ""}, + {"RTM_IEEE80211", Const, 0, ""}, + {"RTM_IFANNOUNCE", Const, 0, ""}, + {"RTM_IFINFO", Const, 0, ""}, + {"RTM_IFINFO2", Const, 0, ""}, + {"RTM_LLINFO_UPD", Const, 1, ""}, + {"RTM_LOCK", Const, 0, ""}, + {"RTM_LOSING", Const, 0, ""}, + {"RTM_MAX", Const, 0, ""}, + {"RTM_MAXSIZE", Const, 1, ""}, + {"RTM_MISS", Const, 0, ""}, + {"RTM_NEWACTION", Const, 0, ""}, + {"RTM_NEWADDR", Const, 0, ""}, + {"RTM_NEWADDRLABEL", Const, 0, ""}, + {"RTM_NEWLINK", Const, 0, ""}, + {"RTM_NEWMADDR", Const, 0, ""}, + {"RTM_NEWMADDR2", Const, 0, ""}, + {"RTM_NEWNDUSEROPT", Const, 0, ""}, + {"RTM_NEWNEIGH", Const, 0, ""}, + {"RTM_NEWNEIGHTBL", Const, 0, ""}, + {"RTM_NEWPREFIX", Const, 0, ""}, + {"RTM_NEWQDISC", Const, 0, ""}, + {"RTM_NEWROUTE", Const, 0, ""}, + {"RTM_NEWRULE", Const, 0, ""}, + {"RTM_NEWTCLASS", Const, 0, ""}, + {"RTM_NEWTFILTER", Const, 0, ""}, + {"RTM_NR_FAMILIES", Const, 0, ""}, + {"RTM_NR_MSGTYPES", Const, 0, ""}, + {"RTM_OIFINFO", Const, 1, ""}, + {"RTM_OLDADD", Const, 0, ""}, + {"RTM_OLDDEL", Const, 0, ""}, + {"RTM_OOIFINFO", Const, 1, ""}, + {"RTM_REDIRECT", Const, 0, ""}, + {"RTM_RESOLVE", Const, 0, ""}, + {"RTM_RTTUNIT", Const, 0, ""}, + {"RTM_SETDCB", Const, 0, ""}, + {"RTM_SETGATE", Const, 1, ""}, + {"RTM_SETLINK", Const, 0, ""}, + {"RTM_SETNEIGHTBL", Const, 0, ""}, + {"RTM_VERSION", Const, 0, ""}, + {"RTNH_ALIGNTO", Const, 0, ""}, + {"RTNH_F_DEAD", Const, 0, ""}, + {"RTNH_F_ONLINK", Const, 0, ""}, + {"RTNH_F_PERVASIVE", Const, 0, ""}, + {"RTNLGRP_IPV4_IFADDR", Const, 1, ""}, + {"RTNLGRP_IPV4_MROUTE", Const, 1, ""}, + {"RTNLGRP_IPV4_ROUTE", Const, 1, ""}, + {"RTNLGRP_IPV4_RULE", Const, 1, ""}, + {"RTNLGRP_IPV6_IFADDR", Const, 1, ""}, + {"RTNLGRP_IPV6_IFINFO", Const, 1, ""}, + {"RTNLGRP_IPV6_MROUTE", Const, 1, ""}, + {"RTNLGRP_IPV6_PREFIX", Const, 1, ""}, + {"RTNLGRP_IPV6_ROUTE", Const, 1, ""}, + {"RTNLGRP_IPV6_RULE", Const, 1, ""}, + {"RTNLGRP_LINK", Const, 1, ""}, + {"RTNLGRP_ND_USEROPT", Const, 1, ""}, + {"RTNLGRP_NEIGH", Const, 1, ""}, + {"RTNLGRP_NONE", Const, 1, ""}, + {"RTNLGRP_NOTIFY", Const, 1, ""}, + {"RTNLGRP_TC", Const, 1, ""}, + {"RTN_ANYCAST", Const, 0, ""}, + {"RTN_BLACKHOLE", Const, 0, ""}, + {"RTN_BROADCAST", Const, 0, ""}, + {"RTN_LOCAL", Const, 0, ""}, + {"RTN_MAX", Const, 0, ""}, + {"RTN_MULTICAST", Const, 0, ""}, + {"RTN_NAT", Const, 0, ""}, + {"RTN_PROHIBIT", Const, 0, ""}, + {"RTN_THROW", Const, 0, ""}, + {"RTN_UNICAST", Const, 0, ""}, + {"RTN_UNREACHABLE", Const, 0, ""}, + {"RTN_UNSPEC", Const, 0, ""}, + {"RTN_XRESOLVE", Const, 0, ""}, + {"RTPROT_BIRD", Const, 0, ""}, + {"RTPROT_BOOT", Const, 0, ""}, + {"RTPROT_DHCP", Const, 0, ""}, + {"RTPROT_DNROUTED", Const, 0, ""}, + {"RTPROT_GATED", Const, 0, ""}, + {"RTPROT_KERNEL", Const, 0, ""}, + {"RTPROT_MRT", Const, 0, ""}, + {"RTPROT_NTK", Const, 0, ""}, + {"RTPROT_RA", Const, 0, ""}, + {"RTPROT_REDIRECT", Const, 0, ""}, + {"RTPROT_STATIC", Const, 0, ""}, + {"RTPROT_UNSPEC", Const, 0, ""}, + {"RTPROT_XORP", Const, 0, ""}, + {"RTPROT_ZEBRA", Const, 0, ""}, + {"RTV_EXPIRE", Const, 0, ""}, + {"RTV_HOPCOUNT", Const, 0, ""}, + {"RTV_MTU", Const, 0, ""}, + {"RTV_RPIPE", Const, 0, ""}, + {"RTV_RTT", Const, 0, ""}, + {"RTV_RTTVAR", Const, 0, ""}, + {"RTV_SPIPE", Const, 0, ""}, + {"RTV_SSTHRESH", Const, 0, ""}, + {"RTV_WEIGHT", Const, 0, ""}, + {"RT_CACHING_CONTEXT", Const, 1, ""}, + {"RT_CLASS_DEFAULT", Const, 0, ""}, + {"RT_CLASS_LOCAL", Const, 0, ""}, + {"RT_CLASS_MAIN", Const, 0, ""}, + {"RT_CLASS_MAX", Const, 0, ""}, + {"RT_CLASS_UNSPEC", Const, 0, ""}, + {"RT_DEFAULT_FIB", Const, 1, ""}, + {"RT_NORTREF", Const, 1, ""}, + {"RT_SCOPE_HOST", Const, 0, ""}, + {"RT_SCOPE_LINK", Const, 0, ""}, + {"RT_SCOPE_NOWHERE", Const, 0, ""}, + {"RT_SCOPE_SITE", Const, 0, ""}, + {"RT_SCOPE_UNIVERSE", Const, 0, ""}, + {"RT_TABLEID_MAX", Const, 1, ""}, + {"RT_TABLE_COMPAT", Const, 0, ""}, + {"RT_TABLE_DEFAULT", Const, 0, ""}, + {"RT_TABLE_LOCAL", Const, 0, ""}, + {"RT_TABLE_MAIN", Const, 0, ""}, + {"RT_TABLE_MAX", Const, 0, ""}, + {"RT_TABLE_UNSPEC", Const, 0, ""}, + {"RUSAGE_CHILDREN", Const, 0, ""}, + {"RUSAGE_SELF", Const, 0, ""}, + {"RUSAGE_THREAD", Const, 0, ""}, + {"Radvisory_t", Type, 0, ""}, + {"Radvisory_t.Count", Field, 0, ""}, + {"Radvisory_t.Offset", Field, 0, ""}, + {"Radvisory_t.Pad_cgo_0", Field, 0, ""}, + {"RawConn", Type, 9, ""}, + {"RawSockaddr", Type, 0, ""}, + {"RawSockaddr.Data", Field, 0, ""}, + {"RawSockaddr.Family", Field, 0, ""}, + {"RawSockaddr.Len", Field, 0, ""}, + {"RawSockaddrAny", Type, 0, ""}, + {"RawSockaddrAny.Addr", Field, 0, ""}, + {"RawSockaddrAny.Pad", Field, 0, ""}, + {"RawSockaddrDatalink", Type, 0, ""}, + {"RawSockaddrDatalink.Alen", Field, 0, ""}, + {"RawSockaddrDatalink.Data", Field, 0, ""}, + {"RawSockaddrDatalink.Family", Field, 0, ""}, + {"RawSockaddrDatalink.Index", Field, 0, ""}, + {"RawSockaddrDatalink.Len", Field, 0, ""}, + {"RawSockaddrDatalink.Nlen", Field, 0, ""}, + {"RawSockaddrDatalink.Pad_cgo_0", Field, 2, ""}, + {"RawSockaddrDatalink.Slen", Field, 0, ""}, + {"RawSockaddrDatalink.Type", Field, 0, ""}, + {"RawSockaddrInet4", Type, 0, ""}, + {"RawSockaddrInet4.Addr", Field, 0, ""}, + {"RawSockaddrInet4.Family", Field, 0, ""}, + {"RawSockaddrInet4.Len", Field, 0, ""}, + {"RawSockaddrInet4.Port", Field, 0, ""}, + {"RawSockaddrInet4.Zero", Field, 0, ""}, + {"RawSockaddrInet6", Type, 0, ""}, + {"RawSockaddrInet6.Addr", Field, 0, ""}, + {"RawSockaddrInet6.Family", Field, 0, ""}, + {"RawSockaddrInet6.Flowinfo", Field, 0, ""}, + {"RawSockaddrInet6.Len", Field, 0, ""}, + {"RawSockaddrInet6.Port", Field, 0, ""}, + {"RawSockaddrInet6.Scope_id", Field, 0, ""}, + {"RawSockaddrLinklayer", Type, 0, ""}, + {"RawSockaddrLinklayer.Addr", Field, 0, ""}, + {"RawSockaddrLinklayer.Family", Field, 0, ""}, + {"RawSockaddrLinklayer.Halen", Field, 0, ""}, + {"RawSockaddrLinklayer.Hatype", Field, 0, ""}, + {"RawSockaddrLinklayer.Ifindex", Field, 0, ""}, + {"RawSockaddrLinklayer.Pkttype", Field, 0, ""}, + {"RawSockaddrLinklayer.Protocol", Field, 0, ""}, + {"RawSockaddrNetlink", Type, 0, ""}, + {"RawSockaddrNetlink.Family", Field, 0, ""}, + {"RawSockaddrNetlink.Groups", Field, 0, ""}, + {"RawSockaddrNetlink.Pad", Field, 0, ""}, + {"RawSockaddrNetlink.Pid", Field, 0, ""}, + {"RawSockaddrUnix", Type, 0, ""}, + {"RawSockaddrUnix.Family", Field, 0, ""}, + {"RawSockaddrUnix.Len", Field, 0, ""}, + {"RawSockaddrUnix.Pad_cgo_0", Field, 2, ""}, + {"RawSockaddrUnix.Path", Field, 0, ""}, + {"RawSyscall", Func, 0, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, + {"RawSyscall6", Func, 0, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr, a4 uintptr, a5 uintptr, a6 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, + {"Read", Func, 0, "func(fd int, p []byte) (n int, err error)"}, + {"ReadConsole", Func, 1, ""}, + {"ReadDirectoryChanges", Func, 0, ""}, + {"ReadDirent", Func, 0, "func(fd int, buf []byte) (n int, err error)"}, + {"ReadFile", Func, 0, ""}, + {"Readlink", Func, 0, "func(path string, buf []byte) (n int, err error)"}, + {"Reboot", Func, 0, "func(cmd int) (err error)"}, + {"Recvfrom", Func, 0, "func(fd int, p []byte, flags int) (n int, from Sockaddr, err error)"}, + {"Recvmsg", Func, 0, "func(fd int, p []byte, oob []byte, flags int) (n int, oobn int, recvflags int, from Sockaddr, err error)"}, + {"RegCloseKey", Func, 0, ""}, + {"RegEnumKeyEx", Func, 0, ""}, + {"RegOpenKeyEx", Func, 0, ""}, + {"RegQueryInfoKey", Func, 0, ""}, + {"RegQueryValueEx", Func, 0, ""}, + {"RemoveDirectory", Func, 0, ""}, + {"Removexattr", Func, 1, "func(path string, attr string) (err error)"}, + {"Rename", Func, 0, "func(oldpath string, newpath string) (err error)"}, + {"Renameat", Func, 0, "func(olddirfd int, oldpath string, newdirfd int, newpath string) (err error)"}, + {"Revoke", Func, 0, ""}, + {"Rlimit", Type, 0, ""}, + {"Rlimit.Cur", Field, 0, ""}, + {"Rlimit.Max", Field, 0, ""}, + {"Rmdir", Func, 0, "func(path string) error"}, + {"RouteMessage", Type, 0, ""}, + {"RouteMessage.Data", Field, 0, ""}, + {"RouteMessage.Header", Field, 0, ""}, + {"RouteRIB", Func, 0, ""}, + {"RoutingMessage", Type, 0, ""}, + {"RtAttr", Type, 0, ""}, + {"RtAttr.Len", Field, 0, ""}, + {"RtAttr.Type", Field, 0, ""}, + {"RtGenmsg", Type, 0, ""}, + {"RtGenmsg.Family", Field, 0, ""}, + {"RtMetrics", Type, 0, ""}, + {"RtMetrics.Expire", Field, 0, ""}, + {"RtMetrics.Filler", Field, 0, ""}, + {"RtMetrics.Hopcount", Field, 0, ""}, + {"RtMetrics.Locks", Field, 0, ""}, + {"RtMetrics.Mtu", Field, 0, ""}, + {"RtMetrics.Pad", Field, 3, ""}, + {"RtMetrics.Pksent", Field, 0, ""}, + {"RtMetrics.Recvpipe", Field, 0, ""}, + {"RtMetrics.Refcnt", Field, 2, ""}, + {"RtMetrics.Rtt", Field, 0, ""}, + {"RtMetrics.Rttvar", Field, 0, ""}, + {"RtMetrics.Sendpipe", Field, 0, ""}, + {"RtMetrics.Ssthresh", Field, 0, ""}, + {"RtMetrics.Weight", Field, 0, ""}, + {"RtMsg", Type, 0, ""}, + {"RtMsg.Dst_len", Field, 0, ""}, + {"RtMsg.Family", Field, 0, ""}, + {"RtMsg.Flags", Field, 0, ""}, + {"RtMsg.Protocol", Field, 0, ""}, + {"RtMsg.Scope", Field, 0, ""}, + {"RtMsg.Src_len", Field, 0, ""}, + {"RtMsg.Table", Field, 0, ""}, + {"RtMsg.Tos", Field, 0, ""}, + {"RtMsg.Type", Field, 0, ""}, + {"RtMsghdr", Type, 0, ""}, + {"RtMsghdr.Addrs", Field, 0, ""}, + {"RtMsghdr.Errno", Field, 0, ""}, + {"RtMsghdr.Flags", Field, 0, ""}, + {"RtMsghdr.Fmask", Field, 0, ""}, + {"RtMsghdr.Hdrlen", Field, 2, ""}, + {"RtMsghdr.Index", Field, 0, ""}, + {"RtMsghdr.Inits", Field, 0, ""}, + {"RtMsghdr.Mpls", Field, 2, ""}, + {"RtMsghdr.Msglen", Field, 0, ""}, + {"RtMsghdr.Pad_cgo_0", Field, 0, ""}, + {"RtMsghdr.Pad_cgo_1", Field, 2, ""}, + {"RtMsghdr.Pid", Field, 0, ""}, + {"RtMsghdr.Priority", Field, 2, ""}, + {"RtMsghdr.Rmx", Field, 0, ""}, + {"RtMsghdr.Seq", Field, 0, ""}, + {"RtMsghdr.Tableid", Field, 2, ""}, + {"RtMsghdr.Type", Field, 0, ""}, + {"RtMsghdr.Use", Field, 0, ""}, + {"RtMsghdr.Version", Field, 0, ""}, + {"RtNexthop", Type, 0, ""}, + {"RtNexthop.Flags", Field, 0, ""}, + {"RtNexthop.Hops", Field, 0, ""}, + {"RtNexthop.Ifindex", Field, 0, ""}, + {"RtNexthop.Len", Field, 0, ""}, + {"Rusage", Type, 0, ""}, + {"Rusage.CreationTime", Field, 0, ""}, + {"Rusage.ExitTime", Field, 0, ""}, + {"Rusage.Idrss", Field, 0, ""}, + {"Rusage.Inblock", Field, 0, ""}, + {"Rusage.Isrss", Field, 0, ""}, + {"Rusage.Ixrss", Field, 0, ""}, + {"Rusage.KernelTime", Field, 0, ""}, + {"Rusage.Majflt", Field, 0, ""}, + {"Rusage.Maxrss", Field, 0, ""}, + {"Rusage.Minflt", Field, 0, ""}, + {"Rusage.Msgrcv", Field, 0, ""}, + {"Rusage.Msgsnd", Field, 0, ""}, + {"Rusage.Nivcsw", Field, 0, ""}, + {"Rusage.Nsignals", Field, 0, ""}, + {"Rusage.Nswap", Field, 0, ""}, + {"Rusage.Nvcsw", Field, 0, ""}, + {"Rusage.Oublock", Field, 0, ""}, + {"Rusage.Stime", Field, 0, ""}, + {"Rusage.UserTime", Field, 0, ""}, + {"Rusage.Utime", Field, 0, ""}, + {"SCM_BINTIME", Const, 0, ""}, + {"SCM_CREDENTIALS", Const, 0, ""}, + {"SCM_CREDS", Const, 0, ""}, + {"SCM_RIGHTS", Const, 0, ""}, + {"SCM_TIMESTAMP", Const, 0, ""}, + {"SCM_TIMESTAMPING", Const, 0, ""}, + {"SCM_TIMESTAMPNS", Const, 0, ""}, + {"SCM_TIMESTAMP_MONOTONIC", Const, 0, ""}, + {"SHUT_RD", Const, 0, ""}, + {"SHUT_RDWR", Const, 0, ""}, + {"SHUT_WR", Const, 0, ""}, + {"SID", Type, 0, ""}, + {"SIDAndAttributes", Type, 0, ""}, + {"SIDAndAttributes.Attributes", Field, 0, ""}, + {"SIDAndAttributes.Sid", Field, 0, ""}, + {"SIGABRT", Const, 0, ""}, + {"SIGALRM", Const, 0, ""}, + {"SIGBUS", Const, 0, ""}, + {"SIGCHLD", Const, 0, ""}, + {"SIGCLD", Const, 0, ""}, + {"SIGCONT", Const, 0, ""}, + {"SIGEMT", Const, 0, ""}, + {"SIGFPE", Const, 0, ""}, + {"SIGHUP", Const, 0, ""}, + {"SIGILL", Const, 0, ""}, + {"SIGINFO", Const, 0, ""}, + {"SIGINT", Const, 0, ""}, + {"SIGIO", Const, 0, ""}, + {"SIGIOT", Const, 0, ""}, + {"SIGKILL", Const, 0, ""}, + {"SIGLIBRT", Const, 1, ""}, + {"SIGLWP", Const, 0, ""}, + {"SIGPIPE", Const, 0, ""}, + {"SIGPOLL", Const, 0, ""}, + {"SIGPROF", Const, 0, ""}, + {"SIGPWR", Const, 0, ""}, + {"SIGQUIT", Const, 0, ""}, + {"SIGSEGV", Const, 0, ""}, + {"SIGSTKFLT", Const, 0, ""}, + {"SIGSTOP", Const, 0, ""}, + {"SIGSYS", Const, 0, ""}, + {"SIGTERM", Const, 0, ""}, + {"SIGTHR", Const, 0, ""}, + {"SIGTRAP", Const, 0, ""}, + {"SIGTSTP", Const, 0, ""}, + {"SIGTTIN", Const, 0, ""}, + {"SIGTTOU", Const, 0, ""}, + {"SIGUNUSED", Const, 0, ""}, + {"SIGURG", Const, 0, ""}, + {"SIGUSR1", Const, 0, ""}, + {"SIGUSR2", Const, 0, ""}, + {"SIGVTALRM", Const, 0, ""}, + {"SIGWINCH", Const, 0, ""}, + {"SIGXCPU", Const, 0, ""}, + {"SIGXFSZ", Const, 0, ""}, + {"SIOCADDDLCI", Const, 0, ""}, + {"SIOCADDMULTI", Const, 0, ""}, + {"SIOCADDRT", Const, 0, ""}, + {"SIOCAIFADDR", Const, 0, ""}, + {"SIOCAIFGROUP", Const, 0, ""}, + {"SIOCALIFADDR", Const, 0, ""}, + {"SIOCARPIPLL", Const, 0, ""}, + {"SIOCATMARK", Const, 0, ""}, + {"SIOCAUTOADDR", Const, 0, ""}, + {"SIOCAUTONETMASK", Const, 0, ""}, + {"SIOCBRDGADD", Const, 1, ""}, + {"SIOCBRDGADDS", Const, 1, ""}, + {"SIOCBRDGARL", Const, 1, ""}, + {"SIOCBRDGDADDR", Const, 1, ""}, + {"SIOCBRDGDEL", Const, 1, ""}, + {"SIOCBRDGDELS", Const, 1, ""}, + {"SIOCBRDGFLUSH", Const, 1, ""}, + {"SIOCBRDGFRL", Const, 1, ""}, + {"SIOCBRDGGCACHE", Const, 1, ""}, + {"SIOCBRDGGFD", Const, 1, ""}, + {"SIOCBRDGGHT", Const, 1, ""}, + {"SIOCBRDGGIFFLGS", Const, 1, ""}, + {"SIOCBRDGGMA", Const, 1, ""}, + {"SIOCBRDGGPARAM", Const, 1, ""}, + {"SIOCBRDGGPRI", Const, 1, ""}, + {"SIOCBRDGGRL", Const, 1, ""}, + {"SIOCBRDGGSIFS", Const, 1, ""}, + {"SIOCBRDGGTO", Const, 1, ""}, + {"SIOCBRDGIFS", Const, 1, ""}, + {"SIOCBRDGRTS", Const, 1, ""}, + {"SIOCBRDGSADDR", Const, 1, ""}, + {"SIOCBRDGSCACHE", Const, 1, ""}, + {"SIOCBRDGSFD", Const, 1, ""}, + {"SIOCBRDGSHT", Const, 1, ""}, + {"SIOCBRDGSIFCOST", Const, 1, ""}, + {"SIOCBRDGSIFFLGS", Const, 1, ""}, + {"SIOCBRDGSIFPRIO", Const, 1, ""}, + {"SIOCBRDGSMA", Const, 1, ""}, + {"SIOCBRDGSPRI", Const, 1, ""}, + {"SIOCBRDGSPROTO", Const, 1, ""}, + {"SIOCBRDGSTO", Const, 1, ""}, + {"SIOCBRDGSTXHC", Const, 1, ""}, + {"SIOCDARP", Const, 0, ""}, + {"SIOCDELDLCI", Const, 0, ""}, + {"SIOCDELMULTI", Const, 0, ""}, + {"SIOCDELRT", Const, 0, ""}, + {"SIOCDEVPRIVATE", Const, 0, ""}, + {"SIOCDIFADDR", Const, 0, ""}, + {"SIOCDIFGROUP", Const, 0, ""}, + {"SIOCDIFPHYADDR", Const, 0, ""}, + {"SIOCDLIFADDR", Const, 0, ""}, + {"SIOCDRARP", Const, 0, ""}, + {"SIOCGARP", Const, 0, ""}, + {"SIOCGDRVSPEC", Const, 0, ""}, + {"SIOCGETKALIVE", Const, 1, ""}, + {"SIOCGETLABEL", Const, 1, ""}, + {"SIOCGETPFLOW", Const, 1, ""}, + {"SIOCGETPFSYNC", Const, 1, ""}, + {"SIOCGETSGCNT", Const, 0, ""}, + {"SIOCGETVIFCNT", Const, 0, ""}, + {"SIOCGETVLAN", Const, 0, ""}, + {"SIOCGHIWAT", Const, 0, ""}, + {"SIOCGIFADDR", Const, 0, ""}, + {"SIOCGIFADDRPREF", Const, 1, ""}, + {"SIOCGIFALIAS", Const, 1, ""}, + {"SIOCGIFALTMTU", Const, 0, ""}, + {"SIOCGIFASYNCMAP", Const, 0, ""}, + {"SIOCGIFBOND", Const, 0, ""}, + {"SIOCGIFBR", Const, 0, ""}, + {"SIOCGIFBRDADDR", Const, 0, ""}, + {"SIOCGIFCAP", Const, 0, ""}, + {"SIOCGIFCONF", Const, 0, ""}, + {"SIOCGIFCOUNT", Const, 0, ""}, + {"SIOCGIFDATA", Const, 1, ""}, + {"SIOCGIFDESCR", Const, 0, ""}, + {"SIOCGIFDEVMTU", Const, 0, ""}, + {"SIOCGIFDLT", Const, 1, ""}, + {"SIOCGIFDSTADDR", Const, 0, ""}, + {"SIOCGIFENCAP", Const, 0, ""}, + {"SIOCGIFFIB", Const, 1, ""}, + {"SIOCGIFFLAGS", Const, 0, ""}, + {"SIOCGIFGATTR", Const, 1, ""}, + {"SIOCGIFGENERIC", Const, 0, ""}, + {"SIOCGIFGMEMB", Const, 0, ""}, + {"SIOCGIFGROUP", Const, 0, ""}, + {"SIOCGIFHARDMTU", Const, 3, ""}, + {"SIOCGIFHWADDR", Const, 0, ""}, + {"SIOCGIFINDEX", Const, 0, ""}, + {"SIOCGIFKPI", Const, 0, ""}, + {"SIOCGIFMAC", Const, 0, ""}, + {"SIOCGIFMAP", Const, 0, ""}, + {"SIOCGIFMEDIA", Const, 0, ""}, + {"SIOCGIFMEM", Const, 0, ""}, + {"SIOCGIFMETRIC", Const, 0, ""}, + {"SIOCGIFMTU", Const, 0, ""}, + {"SIOCGIFNAME", Const, 0, ""}, + {"SIOCGIFNETMASK", Const, 0, ""}, + {"SIOCGIFPDSTADDR", Const, 0, ""}, + {"SIOCGIFPFLAGS", Const, 0, ""}, + {"SIOCGIFPHYS", Const, 0, ""}, + {"SIOCGIFPRIORITY", Const, 1, ""}, + {"SIOCGIFPSRCADDR", Const, 0, ""}, + {"SIOCGIFRDOMAIN", Const, 1, ""}, + {"SIOCGIFRTLABEL", Const, 1, ""}, + {"SIOCGIFSLAVE", Const, 0, ""}, + {"SIOCGIFSTATUS", Const, 0, ""}, + {"SIOCGIFTIMESLOT", Const, 1, ""}, + {"SIOCGIFTXQLEN", Const, 0, ""}, + {"SIOCGIFVLAN", Const, 0, ""}, + {"SIOCGIFWAKEFLAGS", Const, 0, ""}, + {"SIOCGIFXFLAGS", Const, 1, ""}, + {"SIOCGLIFADDR", Const, 0, ""}, + {"SIOCGLIFPHYADDR", Const, 0, ""}, + {"SIOCGLIFPHYRTABLE", Const, 1, ""}, + {"SIOCGLIFPHYTTL", Const, 3, ""}, + {"SIOCGLINKSTR", Const, 1, ""}, + {"SIOCGLOWAT", Const, 0, ""}, + {"SIOCGPGRP", Const, 0, ""}, + {"SIOCGPRIVATE_0", Const, 0, ""}, + {"SIOCGPRIVATE_1", Const, 0, ""}, + {"SIOCGRARP", Const, 0, ""}, + {"SIOCGSPPPPARAMS", Const, 3, ""}, + {"SIOCGSTAMP", Const, 0, ""}, + {"SIOCGSTAMPNS", Const, 0, ""}, + {"SIOCGVH", Const, 1, ""}, + {"SIOCGVNETID", Const, 3, ""}, + {"SIOCIFCREATE", Const, 0, ""}, + {"SIOCIFCREATE2", Const, 0, ""}, + {"SIOCIFDESTROY", Const, 0, ""}, + {"SIOCIFGCLONERS", Const, 0, ""}, + {"SIOCINITIFADDR", Const, 1, ""}, + {"SIOCPROTOPRIVATE", Const, 0, ""}, + {"SIOCRSLVMULTI", Const, 0, ""}, + {"SIOCRTMSG", Const, 0, ""}, + {"SIOCSARP", Const, 0, ""}, + {"SIOCSDRVSPEC", Const, 0, ""}, + {"SIOCSETKALIVE", Const, 1, ""}, + {"SIOCSETLABEL", Const, 1, ""}, + {"SIOCSETPFLOW", Const, 1, ""}, + {"SIOCSETPFSYNC", Const, 1, ""}, + {"SIOCSETVLAN", Const, 0, ""}, + {"SIOCSHIWAT", Const, 0, ""}, + {"SIOCSIFADDR", Const, 0, ""}, + {"SIOCSIFADDRPREF", Const, 1, ""}, + {"SIOCSIFALTMTU", Const, 0, ""}, + {"SIOCSIFASYNCMAP", Const, 0, ""}, + {"SIOCSIFBOND", Const, 0, ""}, + {"SIOCSIFBR", Const, 0, ""}, + {"SIOCSIFBRDADDR", Const, 0, ""}, + {"SIOCSIFCAP", Const, 0, ""}, + {"SIOCSIFDESCR", Const, 0, ""}, + {"SIOCSIFDSTADDR", Const, 0, ""}, + {"SIOCSIFENCAP", Const, 0, ""}, + {"SIOCSIFFIB", Const, 1, ""}, + {"SIOCSIFFLAGS", Const, 0, ""}, + {"SIOCSIFGATTR", Const, 1, ""}, + {"SIOCSIFGENERIC", Const, 0, ""}, + {"SIOCSIFHWADDR", Const, 0, ""}, + {"SIOCSIFHWBROADCAST", Const, 0, ""}, + {"SIOCSIFKPI", Const, 0, ""}, + {"SIOCSIFLINK", Const, 0, ""}, + {"SIOCSIFLLADDR", Const, 0, ""}, + {"SIOCSIFMAC", Const, 0, ""}, + {"SIOCSIFMAP", Const, 0, ""}, + {"SIOCSIFMEDIA", Const, 0, ""}, + {"SIOCSIFMEM", Const, 0, ""}, + {"SIOCSIFMETRIC", Const, 0, ""}, + {"SIOCSIFMTU", Const, 0, ""}, + {"SIOCSIFNAME", Const, 0, ""}, + {"SIOCSIFNETMASK", Const, 0, ""}, + {"SIOCSIFPFLAGS", Const, 0, ""}, + {"SIOCSIFPHYADDR", Const, 0, ""}, + {"SIOCSIFPHYS", Const, 0, ""}, + {"SIOCSIFPRIORITY", Const, 1, ""}, + {"SIOCSIFRDOMAIN", Const, 1, ""}, + {"SIOCSIFRTLABEL", Const, 1, ""}, + {"SIOCSIFRVNET", Const, 0, ""}, + {"SIOCSIFSLAVE", Const, 0, ""}, + {"SIOCSIFTIMESLOT", Const, 1, ""}, + {"SIOCSIFTXQLEN", Const, 0, ""}, + {"SIOCSIFVLAN", Const, 0, ""}, + {"SIOCSIFVNET", Const, 0, ""}, + {"SIOCSIFXFLAGS", Const, 1, ""}, + {"SIOCSLIFPHYADDR", Const, 0, ""}, + {"SIOCSLIFPHYRTABLE", Const, 1, ""}, + {"SIOCSLIFPHYTTL", Const, 3, ""}, + {"SIOCSLINKSTR", Const, 1, ""}, + {"SIOCSLOWAT", Const, 0, ""}, + {"SIOCSPGRP", Const, 0, ""}, + {"SIOCSRARP", Const, 0, ""}, + {"SIOCSSPPPPARAMS", Const, 3, ""}, + {"SIOCSVH", Const, 1, ""}, + {"SIOCSVNETID", Const, 3, ""}, + {"SIOCZIFDATA", Const, 1, ""}, + {"SIO_GET_EXTENSION_FUNCTION_POINTER", Const, 1, ""}, + {"SIO_GET_INTERFACE_LIST", Const, 0, ""}, + {"SIO_KEEPALIVE_VALS", Const, 3, ""}, + {"SIO_UDP_CONNRESET", Const, 4, ""}, + {"SOCK_CLOEXEC", Const, 0, ""}, + {"SOCK_DCCP", Const, 0, ""}, + {"SOCK_DGRAM", Const, 0, ""}, + {"SOCK_FLAGS_MASK", Const, 1, ""}, + {"SOCK_MAXADDRLEN", Const, 0, ""}, + {"SOCK_NONBLOCK", Const, 0, ""}, + {"SOCK_NOSIGPIPE", Const, 1, ""}, + {"SOCK_PACKET", Const, 0, ""}, + {"SOCK_RAW", Const, 0, ""}, + {"SOCK_RDM", Const, 0, ""}, + {"SOCK_SEQPACKET", Const, 0, ""}, + {"SOCK_STREAM", Const, 0, ""}, + {"SOL_AAL", Const, 0, ""}, + {"SOL_ATM", Const, 0, ""}, + {"SOL_DECNET", Const, 0, ""}, + {"SOL_ICMPV6", Const, 0, ""}, + {"SOL_IP", Const, 0, ""}, + {"SOL_IPV6", Const, 0, ""}, + {"SOL_IRDA", Const, 0, ""}, + {"SOL_PACKET", Const, 0, ""}, + {"SOL_RAW", Const, 0, ""}, + {"SOL_SOCKET", Const, 0, ""}, + {"SOL_TCP", Const, 0, ""}, + {"SOL_X25", Const, 0, ""}, + {"SOMAXCONN", Const, 0, ""}, + {"SO_ACCEPTCONN", Const, 0, ""}, + {"SO_ACCEPTFILTER", Const, 0, ""}, + {"SO_ATTACH_FILTER", Const, 0, ""}, + {"SO_BINDANY", Const, 1, ""}, + {"SO_BINDTODEVICE", Const, 0, ""}, + {"SO_BINTIME", Const, 0, ""}, + {"SO_BROADCAST", Const, 0, ""}, + {"SO_BSDCOMPAT", Const, 0, ""}, + {"SO_DEBUG", Const, 0, ""}, + {"SO_DETACH_FILTER", Const, 0, ""}, + {"SO_DOMAIN", Const, 0, ""}, + {"SO_DONTROUTE", Const, 0, ""}, + {"SO_DONTTRUNC", Const, 0, ""}, + {"SO_ERROR", Const, 0, ""}, + {"SO_KEEPALIVE", Const, 0, ""}, + {"SO_LABEL", Const, 0, ""}, + {"SO_LINGER", Const, 0, ""}, + {"SO_LINGER_SEC", Const, 0, ""}, + {"SO_LISTENINCQLEN", Const, 0, ""}, + {"SO_LISTENQLEN", Const, 0, ""}, + {"SO_LISTENQLIMIT", Const, 0, ""}, + {"SO_MARK", Const, 0, ""}, + {"SO_NETPROC", Const, 1, ""}, + {"SO_NKE", Const, 0, ""}, + {"SO_NOADDRERR", Const, 0, ""}, + {"SO_NOHEADER", Const, 1, ""}, + {"SO_NOSIGPIPE", Const, 0, ""}, + {"SO_NOTIFYCONFLICT", Const, 0, ""}, + {"SO_NO_CHECK", Const, 0, ""}, + {"SO_NO_DDP", Const, 0, ""}, + {"SO_NO_OFFLOAD", Const, 0, ""}, + {"SO_NP_EXTENSIONS", Const, 0, ""}, + {"SO_NREAD", Const, 0, ""}, + {"SO_NUMRCVPKT", Const, 16, ""}, + {"SO_NWRITE", Const, 0, ""}, + {"SO_OOBINLINE", Const, 0, ""}, + {"SO_OVERFLOWED", Const, 1, ""}, + {"SO_PASSCRED", Const, 0, ""}, + {"SO_PASSSEC", Const, 0, ""}, + {"SO_PEERCRED", Const, 0, ""}, + {"SO_PEERLABEL", Const, 0, ""}, + {"SO_PEERNAME", Const, 0, ""}, + {"SO_PEERSEC", Const, 0, ""}, + {"SO_PRIORITY", Const, 0, ""}, + {"SO_PROTOCOL", Const, 0, ""}, + {"SO_PROTOTYPE", Const, 1, ""}, + {"SO_RANDOMPORT", Const, 0, ""}, + {"SO_RCVBUF", Const, 0, ""}, + {"SO_RCVBUFFORCE", Const, 0, ""}, + {"SO_RCVLOWAT", Const, 0, ""}, + {"SO_RCVTIMEO", Const, 0, ""}, + {"SO_RESTRICTIONS", Const, 0, ""}, + {"SO_RESTRICT_DENYIN", Const, 0, ""}, + {"SO_RESTRICT_DENYOUT", Const, 0, ""}, + {"SO_RESTRICT_DENYSET", Const, 0, ""}, + {"SO_REUSEADDR", Const, 0, ""}, + {"SO_REUSEPORT", Const, 0, ""}, + {"SO_REUSESHAREUID", Const, 0, ""}, + {"SO_RTABLE", Const, 1, ""}, + {"SO_RXQ_OVFL", Const, 0, ""}, + {"SO_SECURITY_AUTHENTICATION", Const, 0, ""}, + {"SO_SECURITY_ENCRYPTION_NETWORK", Const, 0, ""}, + {"SO_SECURITY_ENCRYPTION_TRANSPORT", Const, 0, ""}, + {"SO_SETFIB", Const, 0, ""}, + {"SO_SNDBUF", Const, 0, ""}, + {"SO_SNDBUFFORCE", Const, 0, ""}, + {"SO_SNDLOWAT", Const, 0, ""}, + {"SO_SNDTIMEO", Const, 0, ""}, + {"SO_SPLICE", Const, 1, ""}, + {"SO_TIMESTAMP", Const, 0, ""}, + {"SO_TIMESTAMPING", Const, 0, ""}, + {"SO_TIMESTAMPNS", Const, 0, ""}, + {"SO_TIMESTAMP_MONOTONIC", Const, 0, ""}, + {"SO_TYPE", Const, 0, ""}, + {"SO_UPCALLCLOSEWAIT", Const, 0, ""}, + {"SO_UPDATE_ACCEPT_CONTEXT", Const, 0, ""}, + {"SO_UPDATE_CONNECT_CONTEXT", Const, 1, ""}, + {"SO_USELOOPBACK", Const, 0, ""}, + {"SO_USER_COOKIE", Const, 1, ""}, + {"SO_VENDOR", Const, 3, ""}, + {"SO_WANTMORE", Const, 0, ""}, + {"SO_WANTOOBFLAG", Const, 0, ""}, + {"SSLExtraCertChainPolicyPara", Type, 0, ""}, + {"SSLExtraCertChainPolicyPara.AuthType", Field, 0, ""}, + {"SSLExtraCertChainPolicyPara.Checks", Field, 0, ""}, + {"SSLExtraCertChainPolicyPara.ServerName", Field, 0, ""}, + {"SSLExtraCertChainPolicyPara.Size", Field, 0, ""}, + {"STANDARD_RIGHTS_ALL", Const, 0, ""}, + {"STANDARD_RIGHTS_EXECUTE", Const, 0, ""}, + {"STANDARD_RIGHTS_READ", Const, 0, ""}, + {"STANDARD_RIGHTS_REQUIRED", Const, 0, ""}, + {"STANDARD_RIGHTS_WRITE", Const, 0, ""}, + {"STARTF_USESHOWWINDOW", Const, 0, ""}, + {"STARTF_USESTDHANDLES", Const, 0, ""}, + {"STD_ERROR_HANDLE", Const, 0, ""}, + {"STD_INPUT_HANDLE", Const, 0, ""}, + {"STD_OUTPUT_HANDLE", Const, 0, ""}, + {"SUBLANG_ENGLISH_US", Const, 0, ""}, + {"SW_FORCEMINIMIZE", Const, 0, ""}, + {"SW_HIDE", Const, 0, ""}, + {"SW_MAXIMIZE", Const, 0, ""}, + {"SW_MINIMIZE", Const, 0, ""}, + {"SW_NORMAL", Const, 0, ""}, + {"SW_RESTORE", Const, 0, ""}, + {"SW_SHOW", Const, 0, ""}, + {"SW_SHOWDEFAULT", Const, 0, ""}, + {"SW_SHOWMAXIMIZED", Const, 0, ""}, + {"SW_SHOWMINIMIZED", Const, 0, ""}, + {"SW_SHOWMINNOACTIVE", Const, 0, ""}, + {"SW_SHOWNA", Const, 0, ""}, + {"SW_SHOWNOACTIVATE", Const, 0, ""}, + {"SW_SHOWNORMAL", Const, 0, ""}, + {"SYMBOLIC_LINK_FLAG_DIRECTORY", Const, 4, ""}, + {"SYNCHRONIZE", Const, 0, ""}, + {"SYSCTL_VERSION", Const, 1, ""}, + {"SYSCTL_VERS_0", Const, 1, ""}, + {"SYSCTL_VERS_1", Const, 1, ""}, + {"SYSCTL_VERS_MASK", Const, 1, ""}, + {"SYS_ABORT2", Const, 0, ""}, + {"SYS_ACCEPT", Const, 0, ""}, + {"SYS_ACCEPT4", Const, 0, ""}, + {"SYS_ACCEPT_NOCANCEL", Const, 0, ""}, + {"SYS_ACCESS", Const, 0, ""}, + {"SYS_ACCESS_EXTENDED", Const, 0, ""}, + {"SYS_ACCT", Const, 0, ""}, + {"SYS_ADD_KEY", Const, 0, ""}, + {"SYS_ADD_PROFIL", Const, 0, ""}, + {"SYS_ADJFREQ", Const, 1, ""}, + {"SYS_ADJTIME", Const, 0, ""}, + {"SYS_ADJTIMEX", Const, 0, ""}, + {"SYS_AFS_SYSCALL", Const, 0, ""}, + {"SYS_AIO_CANCEL", Const, 0, ""}, + {"SYS_AIO_ERROR", Const, 0, ""}, + {"SYS_AIO_FSYNC", Const, 0, ""}, + {"SYS_AIO_MLOCK", Const, 14, ""}, + {"SYS_AIO_READ", Const, 0, ""}, + {"SYS_AIO_RETURN", Const, 0, ""}, + {"SYS_AIO_SUSPEND", Const, 0, ""}, + {"SYS_AIO_SUSPEND_NOCANCEL", Const, 0, ""}, + {"SYS_AIO_WAITCOMPLETE", Const, 14, ""}, + {"SYS_AIO_WRITE", Const, 0, ""}, + {"SYS_ALARM", Const, 0, ""}, + {"SYS_ARCH_PRCTL", Const, 0, ""}, + {"SYS_ARM_FADVISE64_64", Const, 0, ""}, + {"SYS_ARM_SYNC_FILE_RANGE", Const, 0, ""}, + {"SYS_ATGETMSG", Const, 0, ""}, + {"SYS_ATPGETREQ", Const, 0, ""}, + {"SYS_ATPGETRSP", Const, 0, ""}, + {"SYS_ATPSNDREQ", Const, 0, ""}, + {"SYS_ATPSNDRSP", Const, 0, ""}, + {"SYS_ATPUTMSG", Const, 0, ""}, + {"SYS_ATSOCKET", Const, 0, ""}, + {"SYS_AUDIT", Const, 0, ""}, + {"SYS_AUDITCTL", Const, 0, ""}, + {"SYS_AUDITON", Const, 0, ""}, + {"SYS_AUDIT_SESSION_JOIN", Const, 0, ""}, + {"SYS_AUDIT_SESSION_PORT", Const, 0, ""}, + {"SYS_AUDIT_SESSION_SELF", Const, 0, ""}, + {"SYS_BDFLUSH", Const, 0, ""}, + {"SYS_BIND", Const, 0, ""}, + {"SYS_BINDAT", Const, 3, ""}, + {"SYS_BREAK", Const, 0, ""}, + {"SYS_BRK", Const, 0, ""}, + {"SYS_BSDTHREAD_CREATE", Const, 0, ""}, + {"SYS_BSDTHREAD_REGISTER", Const, 0, ""}, + {"SYS_BSDTHREAD_TERMINATE", Const, 0, ""}, + {"SYS_CAPGET", Const, 0, ""}, + {"SYS_CAPSET", Const, 0, ""}, + {"SYS_CAP_ENTER", Const, 0, ""}, + {"SYS_CAP_FCNTLS_GET", Const, 1, ""}, + {"SYS_CAP_FCNTLS_LIMIT", Const, 1, ""}, + {"SYS_CAP_GETMODE", Const, 0, ""}, + {"SYS_CAP_GETRIGHTS", Const, 0, ""}, + {"SYS_CAP_IOCTLS_GET", Const, 1, ""}, + {"SYS_CAP_IOCTLS_LIMIT", Const, 1, ""}, + {"SYS_CAP_NEW", Const, 0, ""}, + {"SYS_CAP_RIGHTS_GET", Const, 1, ""}, + {"SYS_CAP_RIGHTS_LIMIT", Const, 1, ""}, + {"SYS_CHDIR", Const, 0, ""}, + {"SYS_CHFLAGS", Const, 0, ""}, + {"SYS_CHFLAGSAT", Const, 3, ""}, + {"SYS_CHMOD", Const, 0, ""}, + {"SYS_CHMOD_EXTENDED", Const, 0, ""}, + {"SYS_CHOWN", Const, 0, ""}, + {"SYS_CHOWN32", Const, 0, ""}, + {"SYS_CHROOT", Const, 0, ""}, + {"SYS_CHUD", Const, 0, ""}, + {"SYS_CLOCK_ADJTIME", Const, 0, ""}, + {"SYS_CLOCK_GETCPUCLOCKID2", Const, 1, ""}, + {"SYS_CLOCK_GETRES", Const, 0, ""}, + {"SYS_CLOCK_GETTIME", Const, 0, ""}, + {"SYS_CLOCK_NANOSLEEP", Const, 0, ""}, + {"SYS_CLOCK_SETTIME", Const, 0, ""}, + {"SYS_CLONE", Const, 0, ""}, + {"SYS_CLOSE", Const, 0, ""}, + {"SYS_CLOSEFROM", Const, 0, ""}, + {"SYS_CLOSE_NOCANCEL", Const, 0, ""}, + {"SYS_CONNECT", Const, 0, ""}, + {"SYS_CONNECTAT", Const, 3, ""}, + {"SYS_CONNECT_NOCANCEL", Const, 0, ""}, + {"SYS_COPYFILE", Const, 0, ""}, + {"SYS_CPUSET", Const, 0, ""}, + {"SYS_CPUSET_GETAFFINITY", Const, 0, ""}, + {"SYS_CPUSET_GETID", Const, 0, ""}, + {"SYS_CPUSET_SETAFFINITY", Const, 0, ""}, + {"SYS_CPUSET_SETID", Const, 0, ""}, + {"SYS_CREAT", Const, 0, ""}, + {"SYS_CREATE_MODULE", Const, 0, ""}, + {"SYS_CSOPS", Const, 0, ""}, + {"SYS_CSOPS_AUDITTOKEN", Const, 16, ""}, + {"SYS_DELETE", Const, 0, ""}, + {"SYS_DELETE_MODULE", Const, 0, ""}, + {"SYS_DUP", Const, 0, ""}, + {"SYS_DUP2", Const, 0, ""}, + {"SYS_DUP3", Const, 0, ""}, + {"SYS_EACCESS", Const, 0, ""}, + {"SYS_EPOLL_CREATE", Const, 0, ""}, + {"SYS_EPOLL_CREATE1", Const, 0, ""}, + {"SYS_EPOLL_CTL", Const, 0, ""}, + {"SYS_EPOLL_CTL_OLD", Const, 0, ""}, + {"SYS_EPOLL_PWAIT", Const, 0, ""}, + {"SYS_EPOLL_WAIT", Const, 0, ""}, + {"SYS_EPOLL_WAIT_OLD", Const, 0, ""}, + {"SYS_EVENTFD", Const, 0, ""}, + {"SYS_EVENTFD2", Const, 0, ""}, + {"SYS_EXCHANGEDATA", Const, 0, ""}, + {"SYS_EXECVE", Const, 0, ""}, + {"SYS_EXIT", Const, 0, ""}, + {"SYS_EXIT_GROUP", Const, 0, ""}, + {"SYS_EXTATTRCTL", Const, 0, ""}, + {"SYS_EXTATTR_DELETE_FD", Const, 0, ""}, + {"SYS_EXTATTR_DELETE_FILE", Const, 0, ""}, + {"SYS_EXTATTR_DELETE_LINK", Const, 0, ""}, + {"SYS_EXTATTR_GET_FD", Const, 0, ""}, + {"SYS_EXTATTR_GET_FILE", Const, 0, ""}, + {"SYS_EXTATTR_GET_LINK", Const, 0, ""}, + {"SYS_EXTATTR_LIST_FD", Const, 0, ""}, + {"SYS_EXTATTR_LIST_FILE", Const, 0, ""}, + {"SYS_EXTATTR_LIST_LINK", Const, 0, ""}, + {"SYS_EXTATTR_SET_FD", Const, 0, ""}, + {"SYS_EXTATTR_SET_FILE", Const, 0, ""}, + {"SYS_EXTATTR_SET_LINK", Const, 0, ""}, + {"SYS_FACCESSAT", Const, 0, ""}, + {"SYS_FADVISE64", Const, 0, ""}, + {"SYS_FADVISE64_64", Const, 0, ""}, + {"SYS_FALLOCATE", Const, 0, ""}, + {"SYS_FANOTIFY_INIT", Const, 0, ""}, + {"SYS_FANOTIFY_MARK", Const, 0, ""}, + {"SYS_FCHDIR", Const, 0, ""}, + {"SYS_FCHFLAGS", Const, 0, ""}, + {"SYS_FCHMOD", Const, 0, ""}, + {"SYS_FCHMODAT", Const, 0, ""}, + {"SYS_FCHMOD_EXTENDED", Const, 0, ""}, + {"SYS_FCHOWN", Const, 0, ""}, + {"SYS_FCHOWN32", Const, 0, ""}, + {"SYS_FCHOWNAT", Const, 0, ""}, + {"SYS_FCHROOT", Const, 1, ""}, + {"SYS_FCNTL", Const, 0, ""}, + {"SYS_FCNTL64", Const, 0, ""}, + {"SYS_FCNTL_NOCANCEL", Const, 0, ""}, + {"SYS_FDATASYNC", Const, 0, ""}, + {"SYS_FEXECVE", Const, 0, ""}, + {"SYS_FFCLOCK_GETCOUNTER", Const, 0, ""}, + {"SYS_FFCLOCK_GETESTIMATE", Const, 0, ""}, + {"SYS_FFCLOCK_SETESTIMATE", Const, 0, ""}, + {"SYS_FFSCTL", Const, 0, ""}, + {"SYS_FGETATTRLIST", Const, 0, ""}, + {"SYS_FGETXATTR", Const, 0, ""}, + {"SYS_FHOPEN", Const, 0, ""}, + {"SYS_FHSTAT", Const, 0, ""}, + {"SYS_FHSTATFS", Const, 0, ""}, + {"SYS_FILEPORT_MAKEFD", Const, 0, ""}, + {"SYS_FILEPORT_MAKEPORT", Const, 0, ""}, + {"SYS_FKTRACE", Const, 1, ""}, + {"SYS_FLISTXATTR", Const, 0, ""}, + {"SYS_FLOCK", Const, 0, ""}, + {"SYS_FORK", Const, 0, ""}, + {"SYS_FPATHCONF", Const, 0, ""}, + {"SYS_FREEBSD6_FTRUNCATE", Const, 0, ""}, + {"SYS_FREEBSD6_LSEEK", Const, 0, ""}, + {"SYS_FREEBSD6_MMAP", Const, 0, ""}, + {"SYS_FREEBSD6_PREAD", Const, 0, ""}, + {"SYS_FREEBSD6_PWRITE", Const, 0, ""}, + {"SYS_FREEBSD6_TRUNCATE", Const, 0, ""}, + {"SYS_FREMOVEXATTR", Const, 0, ""}, + {"SYS_FSCTL", Const, 0, ""}, + {"SYS_FSETATTRLIST", Const, 0, ""}, + {"SYS_FSETXATTR", Const, 0, ""}, + {"SYS_FSGETPATH", Const, 0, ""}, + {"SYS_FSTAT", Const, 0, ""}, + {"SYS_FSTAT64", Const, 0, ""}, + {"SYS_FSTAT64_EXTENDED", Const, 0, ""}, + {"SYS_FSTATAT", Const, 0, ""}, + {"SYS_FSTATAT64", Const, 0, ""}, + {"SYS_FSTATFS", Const, 0, ""}, + {"SYS_FSTATFS64", Const, 0, ""}, + {"SYS_FSTATV", Const, 0, ""}, + {"SYS_FSTATVFS1", Const, 1, ""}, + {"SYS_FSTAT_EXTENDED", Const, 0, ""}, + {"SYS_FSYNC", Const, 0, ""}, + {"SYS_FSYNC_NOCANCEL", Const, 0, ""}, + {"SYS_FSYNC_RANGE", Const, 1, ""}, + {"SYS_FTIME", Const, 0, ""}, + {"SYS_FTRUNCATE", Const, 0, ""}, + {"SYS_FTRUNCATE64", Const, 0, ""}, + {"SYS_FUTEX", Const, 0, ""}, + {"SYS_FUTIMENS", Const, 1, ""}, + {"SYS_FUTIMES", Const, 0, ""}, + {"SYS_FUTIMESAT", Const, 0, ""}, + {"SYS_GETATTRLIST", Const, 0, ""}, + {"SYS_GETAUDIT", Const, 0, ""}, + {"SYS_GETAUDIT_ADDR", Const, 0, ""}, + {"SYS_GETAUID", Const, 0, ""}, + {"SYS_GETCONTEXT", Const, 0, ""}, + {"SYS_GETCPU", Const, 0, ""}, + {"SYS_GETCWD", Const, 0, ""}, + {"SYS_GETDENTS", Const, 0, ""}, + {"SYS_GETDENTS64", Const, 0, ""}, + {"SYS_GETDIRENTRIES", Const, 0, ""}, + {"SYS_GETDIRENTRIES64", Const, 0, ""}, + {"SYS_GETDIRENTRIESATTR", Const, 0, ""}, + {"SYS_GETDTABLECOUNT", Const, 1, ""}, + {"SYS_GETDTABLESIZE", Const, 0, ""}, + {"SYS_GETEGID", Const, 0, ""}, + {"SYS_GETEGID32", Const, 0, ""}, + {"SYS_GETEUID", Const, 0, ""}, + {"SYS_GETEUID32", Const, 0, ""}, + {"SYS_GETFH", Const, 0, ""}, + {"SYS_GETFSSTAT", Const, 0, ""}, + {"SYS_GETFSSTAT64", Const, 0, ""}, + {"SYS_GETGID", Const, 0, ""}, + {"SYS_GETGID32", Const, 0, ""}, + {"SYS_GETGROUPS", Const, 0, ""}, + {"SYS_GETGROUPS32", Const, 0, ""}, + {"SYS_GETHOSTUUID", Const, 0, ""}, + {"SYS_GETITIMER", Const, 0, ""}, + {"SYS_GETLCID", Const, 0, ""}, + {"SYS_GETLOGIN", Const, 0, ""}, + {"SYS_GETLOGINCLASS", Const, 0, ""}, + {"SYS_GETPEERNAME", Const, 0, ""}, + {"SYS_GETPGID", Const, 0, ""}, + {"SYS_GETPGRP", Const, 0, ""}, + {"SYS_GETPID", Const, 0, ""}, + {"SYS_GETPMSG", Const, 0, ""}, + {"SYS_GETPPID", Const, 0, ""}, + {"SYS_GETPRIORITY", Const, 0, ""}, + {"SYS_GETRESGID", Const, 0, ""}, + {"SYS_GETRESGID32", Const, 0, ""}, + {"SYS_GETRESUID", Const, 0, ""}, + {"SYS_GETRESUID32", Const, 0, ""}, + {"SYS_GETRLIMIT", Const, 0, ""}, + {"SYS_GETRTABLE", Const, 1, ""}, + {"SYS_GETRUSAGE", Const, 0, ""}, + {"SYS_GETSGROUPS", Const, 0, ""}, + {"SYS_GETSID", Const, 0, ""}, + {"SYS_GETSOCKNAME", Const, 0, ""}, + {"SYS_GETSOCKOPT", Const, 0, ""}, + {"SYS_GETTHRID", Const, 1, ""}, + {"SYS_GETTID", Const, 0, ""}, + {"SYS_GETTIMEOFDAY", Const, 0, ""}, + {"SYS_GETUID", Const, 0, ""}, + {"SYS_GETUID32", Const, 0, ""}, + {"SYS_GETVFSSTAT", Const, 1, ""}, + {"SYS_GETWGROUPS", Const, 0, ""}, + {"SYS_GETXATTR", Const, 0, ""}, + {"SYS_GET_KERNEL_SYMS", Const, 0, ""}, + {"SYS_GET_MEMPOLICY", Const, 0, ""}, + {"SYS_GET_ROBUST_LIST", Const, 0, ""}, + {"SYS_GET_THREAD_AREA", Const, 0, ""}, + {"SYS_GSSD_SYSCALL", Const, 14, ""}, + {"SYS_GTTY", Const, 0, ""}, + {"SYS_IDENTITYSVC", Const, 0, ""}, + {"SYS_IDLE", Const, 0, ""}, + {"SYS_INITGROUPS", Const, 0, ""}, + {"SYS_INIT_MODULE", Const, 0, ""}, + {"SYS_INOTIFY_ADD_WATCH", Const, 0, ""}, + {"SYS_INOTIFY_INIT", Const, 0, ""}, + {"SYS_INOTIFY_INIT1", Const, 0, ""}, + {"SYS_INOTIFY_RM_WATCH", Const, 0, ""}, + {"SYS_IOCTL", Const, 0, ""}, + {"SYS_IOPERM", Const, 0, ""}, + {"SYS_IOPL", Const, 0, ""}, + {"SYS_IOPOLICYSYS", Const, 0, ""}, + {"SYS_IOPRIO_GET", Const, 0, ""}, + {"SYS_IOPRIO_SET", Const, 0, ""}, + {"SYS_IO_CANCEL", Const, 0, ""}, + {"SYS_IO_DESTROY", Const, 0, ""}, + {"SYS_IO_GETEVENTS", Const, 0, ""}, + {"SYS_IO_SETUP", Const, 0, ""}, + {"SYS_IO_SUBMIT", Const, 0, ""}, + {"SYS_IPC", Const, 0, ""}, + {"SYS_ISSETUGID", Const, 0, ""}, + {"SYS_JAIL", Const, 0, ""}, + {"SYS_JAIL_ATTACH", Const, 0, ""}, + {"SYS_JAIL_GET", Const, 0, ""}, + {"SYS_JAIL_REMOVE", Const, 0, ""}, + {"SYS_JAIL_SET", Const, 0, ""}, + {"SYS_KAS_INFO", Const, 16, ""}, + {"SYS_KDEBUG_TRACE", Const, 0, ""}, + {"SYS_KENV", Const, 0, ""}, + {"SYS_KEVENT", Const, 0, ""}, + {"SYS_KEVENT64", Const, 0, ""}, + {"SYS_KEXEC_LOAD", Const, 0, ""}, + {"SYS_KEYCTL", Const, 0, ""}, + {"SYS_KILL", Const, 0, ""}, + {"SYS_KLDFIND", Const, 0, ""}, + {"SYS_KLDFIRSTMOD", Const, 0, ""}, + {"SYS_KLDLOAD", Const, 0, ""}, + {"SYS_KLDNEXT", Const, 0, ""}, + {"SYS_KLDSTAT", Const, 0, ""}, + {"SYS_KLDSYM", Const, 0, ""}, + {"SYS_KLDUNLOAD", Const, 0, ""}, + {"SYS_KLDUNLOADF", Const, 0, ""}, + {"SYS_KMQ_NOTIFY", Const, 14, ""}, + {"SYS_KMQ_OPEN", Const, 14, ""}, + {"SYS_KMQ_SETATTR", Const, 14, ""}, + {"SYS_KMQ_TIMEDRECEIVE", Const, 14, ""}, + {"SYS_KMQ_TIMEDSEND", Const, 14, ""}, + {"SYS_KMQ_UNLINK", Const, 14, ""}, + {"SYS_KQUEUE", Const, 0, ""}, + {"SYS_KQUEUE1", Const, 1, ""}, + {"SYS_KSEM_CLOSE", Const, 14, ""}, + {"SYS_KSEM_DESTROY", Const, 14, ""}, + {"SYS_KSEM_GETVALUE", Const, 14, ""}, + {"SYS_KSEM_INIT", Const, 14, ""}, + {"SYS_KSEM_OPEN", Const, 14, ""}, + {"SYS_KSEM_POST", Const, 14, ""}, + {"SYS_KSEM_TIMEDWAIT", Const, 14, ""}, + {"SYS_KSEM_TRYWAIT", Const, 14, ""}, + {"SYS_KSEM_UNLINK", Const, 14, ""}, + {"SYS_KSEM_WAIT", Const, 14, ""}, + {"SYS_KTIMER_CREATE", Const, 0, ""}, + {"SYS_KTIMER_DELETE", Const, 0, ""}, + {"SYS_KTIMER_GETOVERRUN", Const, 0, ""}, + {"SYS_KTIMER_GETTIME", Const, 0, ""}, + {"SYS_KTIMER_SETTIME", Const, 0, ""}, + {"SYS_KTRACE", Const, 0, ""}, + {"SYS_LCHFLAGS", Const, 0, ""}, + {"SYS_LCHMOD", Const, 0, ""}, + {"SYS_LCHOWN", Const, 0, ""}, + {"SYS_LCHOWN32", Const, 0, ""}, + {"SYS_LEDGER", Const, 16, ""}, + {"SYS_LGETFH", Const, 0, ""}, + {"SYS_LGETXATTR", Const, 0, ""}, + {"SYS_LINK", Const, 0, ""}, + {"SYS_LINKAT", Const, 0, ""}, + {"SYS_LIO_LISTIO", Const, 0, ""}, + {"SYS_LISTEN", Const, 0, ""}, + {"SYS_LISTXATTR", Const, 0, ""}, + {"SYS_LLISTXATTR", Const, 0, ""}, + {"SYS_LOCK", Const, 0, ""}, + {"SYS_LOOKUP_DCOOKIE", Const, 0, ""}, + {"SYS_LPATHCONF", Const, 0, ""}, + {"SYS_LREMOVEXATTR", Const, 0, ""}, + {"SYS_LSEEK", Const, 0, ""}, + {"SYS_LSETXATTR", Const, 0, ""}, + {"SYS_LSTAT", Const, 0, ""}, + {"SYS_LSTAT64", Const, 0, ""}, + {"SYS_LSTAT64_EXTENDED", Const, 0, ""}, + {"SYS_LSTATV", Const, 0, ""}, + {"SYS_LSTAT_EXTENDED", Const, 0, ""}, + {"SYS_LUTIMES", Const, 0, ""}, + {"SYS_MAC_SYSCALL", Const, 0, ""}, + {"SYS_MADVISE", Const, 0, ""}, + {"SYS_MADVISE1", Const, 0, ""}, + {"SYS_MAXSYSCALL", Const, 0, ""}, + {"SYS_MBIND", Const, 0, ""}, + {"SYS_MIGRATE_PAGES", Const, 0, ""}, + {"SYS_MINCORE", Const, 0, ""}, + {"SYS_MINHERIT", Const, 0, ""}, + {"SYS_MKCOMPLEX", Const, 0, ""}, + {"SYS_MKDIR", Const, 0, ""}, + {"SYS_MKDIRAT", Const, 0, ""}, + {"SYS_MKDIR_EXTENDED", Const, 0, ""}, + {"SYS_MKFIFO", Const, 0, ""}, + {"SYS_MKFIFOAT", Const, 0, ""}, + {"SYS_MKFIFO_EXTENDED", Const, 0, ""}, + {"SYS_MKNOD", Const, 0, ""}, + {"SYS_MKNODAT", Const, 0, ""}, + {"SYS_MLOCK", Const, 0, ""}, + {"SYS_MLOCKALL", Const, 0, ""}, + {"SYS_MMAP", Const, 0, ""}, + {"SYS_MMAP2", Const, 0, ""}, + {"SYS_MODCTL", Const, 1, ""}, + {"SYS_MODFIND", Const, 0, ""}, + {"SYS_MODFNEXT", Const, 0, ""}, + {"SYS_MODIFY_LDT", Const, 0, ""}, + {"SYS_MODNEXT", Const, 0, ""}, + {"SYS_MODSTAT", Const, 0, ""}, + {"SYS_MODWATCH", Const, 0, ""}, + {"SYS_MOUNT", Const, 0, ""}, + {"SYS_MOVE_PAGES", Const, 0, ""}, + {"SYS_MPROTECT", Const, 0, ""}, + {"SYS_MPX", Const, 0, ""}, + {"SYS_MQUERY", Const, 1, ""}, + {"SYS_MQ_GETSETATTR", Const, 0, ""}, + {"SYS_MQ_NOTIFY", Const, 0, ""}, + {"SYS_MQ_OPEN", Const, 0, ""}, + {"SYS_MQ_TIMEDRECEIVE", Const, 0, ""}, + {"SYS_MQ_TIMEDSEND", Const, 0, ""}, + {"SYS_MQ_UNLINK", Const, 0, ""}, + {"SYS_MREMAP", Const, 0, ""}, + {"SYS_MSGCTL", Const, 0, ""}, + {"SYS_MSGGET", Const, 0, ""}, + {"SYS_MSGRCV", Const, 0, ""}, + {"SYS_MSGRCV_NOCANCEL", Const, 0, ""}, + {"SYS_MSGSND", Const, 0, ""}, + {"SYS_MSGSND_NOCANCEL", Const, 0, ""}, + {"SYS_MSGSYS", Const, 0, ""}, + {"SYS_MSYNC", Const, 0, ""}, + {"SYS_MSYNC_NOCANCEL", Const, 0, ""}, + {"SYS_MUNLOCK", Const, 0, ""}, + {"SYS_MUNLOCKALL", Const, 0, ""}, + {"SYS_MUNMAP", Const, 0, ""}, + {"SYS_NAME_TO_HANDLE_AT", Const, 0, ""}, + {"SYS_NANOSLEEP", Const, 0, ""}, + {"SYS_NEWFSTATAT", Const, 0, ""}, + {"SYS_NFSCLNT", Const, 0, ""}, + {"SYS_NFSSERVCTL", Const, 0, ""}, + {"SYS_NFSSVC", Const, 0, ""}, + {"SYS_NFSTAT", Const, 0, ""}, + {"SYS_NICE", Const, 0, ""}, + {"SYS_NLM_SYSCALL", Const, 14, ""}, + {"SYS_NLSTAT", Const, 0, ""}, + {"SYS_NMOUNT", Const, 0, ""}, + {"SYS_NSTAT", Const, 0, ""}, + {"SYS_NTP_ADJTIME", Const, 0, ""}, + {"SYS_NTP_GETTIME", Const, 0, ""}, + {"SYS_NUMA_GETAFFINITY", Const, 14, ""}, + {"SYS_NUMA_SETAFFINITY", Const, 14, ""}, + {"SYS_OABI_SYSCALL_BASE", Const, 0, ""}, + {"SYS_OBREAK", Const, 0, ""}, + {"SYS_OLDFSTAT", Const, 0, ""}, + {"SYS_OLDLSTAT", Const, 0, ""}, + {"SYS_OLDOLDUNAME", Const, 0, ""}, + {"SYS_OLDSTAT", Const, 0, ""}, + {"SYS_OLDUNAME", Const, 0, ""}, + {"SYS_OPEN", Const, 0, ""}, + {"SYS_OPENAT", Const, 0, ""}, + {"SYS_OPENBSD_POLL", Const, 0, ""}, + {"SYS_OPEN_BY_HANDLE_AT", Const, 0, ""}, + {"SYS_OPEN_DPROTECTED_NP", Const, 16, ""}, + {"SYS_OPEN_EXTENDED", Const, 0, ""}, + {"SYS_OPEN_NOCANCEL", Const, 0, ""}, + {"SYS_OVADVISE", Const, 0, ""}, + {"SYS_PACCEPT", Const, 1, ""}, + {"SYS_PATHCONF", Const, 0, ""}, + {"SYS_PAUSE", Const, 0, ""}, + {"SYS_PCICONFIG_IOBASE", Const, 0, ""}, + {"SYS_PCICONFIG_READ", Const, 0, ""}, + {"SYS_PCICONFIG_WRITE", Const, 0, ""}, + {"SYS_PDFORK", Const, 0, ""}, + {"SYS_PDGETPID", Const, 0, ""}, + {"SYS_PDKILL", Const, 0, ""}, + {"SYS_PERF_EVENT_OPEN", Const, 0, ""}, + {"SYS_PERSONALITY", Const, 0, ""}, + {"SYS_PID_HIBERNATE", Const, 0, ""}, + {"SYS_PID_RESUME", Const, 0, ""}, + {"SYS_PID_SHUTDOWN_SOCKETS", Const, 0, ""}, + {"SYS_PID_SUSPEND", Const, 0, ""}, + {"SYS_PIPE", Const, 0, ""}, + {"SYS_PIPE2", Const, 0, ""}, + {"SYS_PIVOT_ROOT", Const, 0, ""}, + {"SYS_PMC_CONTROL", Const, 1, ""}, + {"SYS_PMC_GET_INFO", Const, 1, ""}, + {"SYS_POLL", Const, 0, ""}, + {"SYS_POLLTS", Const, 1, ""}, + {"SYS_POLL_NOCANCEL", Const, 0, ""}, + {"SYS_POSIX_FADVISE", Const, 0, ""}, + {"SYS_POSIX_FALLOCATE", Const, 0, ""}, + {"SYS_POSIX_OPENPT", Const, 0, ""}, + {"SYS_POSIX_SPAWN", Const, 0, ""}, + {"SYS_PPOLL", Const, 0, ""}, + {"SYS_PRCTL", Const, 0, ""}, + {"SYS_PREAD", Const, 0, ""}, + {"SYS_PREAD64", Const, 0, ""}, + {"SYS_PREADV", Const, 0, ""}, + {"SYS_PREAD_NOCANCEL", Const, 0, ""}, + {"SYS_PRLIMIT64", Const, 0, ""}, + {"SYS_PROCCTL", Const, 3, ""}, + {"SYS_PROCESS_POLICY", Const, 0, ""}, + {"SYS_PROCESS_VM_READV", Const, 0, ""}, + {"SYS_PROCESS_VM_WRITEV", Const, 0, ""}, + {"SYS_PROC_INFO", Const, 0, ""}, + {"SYS_PROF", Const, 0, ""}, + {"SYS_PROFIL", Const, 0, ""}, + {"SYS_PSELECT", Const, 0, ""}, + {"SYS_PSELECT6", Const, 0, ""}, + {"SYS_PSET_ASSIGN", Const, 1, ""}, + {"SYS_PSET_CREATE", Const, 1, ""}, + {"SYS_PSET_DESTROY", Const, 1, ""}, + {"SYS_PSYNCH_CVBROAD", Const, 0, ""}, + {"SYS_PSYNCH_CVCLRPREPOST", Const, 0, ""}, + {"SYS_PSYNCH_CVSIGNAL", Const, 0, ""}, + {"SYS_PSYNCH_CVWAIT", Const, 0, ""}, + {"SYS_PSYNCH_MUTEXDROP", Const, 0, ""}, + {"SYS_PSYNCH_MUTEXWAIT", Const, 0, ""}, + {"SYS_PSYNCH_RW_DOWNGRADE", Const, 0, ""}, + {"SYS_PSYNCH_RW_LONGRDLOCK", Const, 0, ""}, + {"SYS_PSYNCH_RW_RDLOCK", Const, 0, ""}, + {"SYS_PSYNCH_RW_UNLOCK", Const, 0, ""}, + {"SYS_PSYNCH_RW_UNLOCK2", Const, 0, ""}, + {"SYS_PSYNCH_RW_UPGRADE", Const, 0, ""}, + {"SYS_PSYNCH_RW_WRLOCK", Const, 0, ""}, + {"SYS_PSYNCH_RW_YIELDWRLOCK", Const, 0, ""}, + {"SYS_PTRACE", Const, 0, ""}, + {"SYS_PUTPMSG", Const, 0, ""}, + {"SYS_PWRITE", Const, 0, ""}, + {"SYS_PWRITE64", Const, 0, ""}, + {"SYS_PWRITEV", Const, 0, ""}, + {"SYS_PWRITE_NOCANCEL", Const, 0, ""}, + {"SYS_QUERY_MODULE", Const, 0, ""}, + {"SYS_QUOTACTL", Const, 0, ""}, + {"SYS_RASCTL", Const, 1, ""}, + {"SYS_RCTL_ADD_RULE", Const, 0, ""}, + {"SYS_RCTL_GET_LIMITS", Const, 0, ""}, + {"SYS_RCTL_GET_RACCT", Const, 0, ""}, + {"SYS_RCTL_GET_RULES", Const, 0, ""}, + {"SYS_RCTL_REMOVE_RULE", Const, 0, ""}, + {"SYS_READ", Const, 0, ""}, + {"SYS_READAHEAD", Const, 0, ""}, + {"SYS_READDIR", Const, 0, ""}, + {"SYS_READLINK", Const, 0, ""}, + {"SYS_READLINKAT", Const, 0, ""}, + {"SYS_READV", Const, 0, ""}, + {"SYS_READV_NOCANCEL", Const, 0, ""}, + {"SYS_READ_NOCANCEL", Const, 0, ""}, + {"SYS_REBOOT", Const, 0, ""}, + {"SYS_RECV", Const, 0, ""}, + {"SYS_RECVFROM", Const, 0, ""}, + {"SYS_RECVFROM_NOCANCEL", Const, 0, ""}, + {"SYS_RECVMMSG", Const, 0, ""}, + {"SYS_RECVMSG", Const, 0, ""}, + {"SYS_RECVMSG_NOCANCEL", Const, 0, ""}, + {"SYS_REMAP_FILE_PAGES", Const, 0, ""}, + {"SYS_REMOVEXATTR", Const, 0, ""}, + {"SYS_RENAME", Const, 0, ""}, + {"SYS_RENAMEAT", Const, 0, ""}, + {"SYS_REQUEST_KEY", Const, 0, ""}, + {"SYS_RESTART_SYSCALL", Const, 0, ""}, + {"SYS_REVOKE", Const, 0, ""}, + {"SYS_RFORK", Const, 0, ""}, + {"SYS_RMDIR", Const, 0, ""}, + {"SYS_RTPRIO", Const, 0, ""}, + {"SYS_RTPRIO_THREAD", Const, 0, ""}, + {"SYS_RT_SIGACTION", Const, 0, ""}, + {"SYS_RT_SIGPENDING", Const, 0, ""}, + {"SYS_RT_SIGPROCMASK", Const, 0, ""}, + {"SYS_RT_SIGQUEUEINFO", Const, 0, ""}, + {"SYS_RT_SIGRETURN", Const, 0, ""}, + {"SYS_RT_SIGSUSPEND", Const, 0, ""}, + {"SYS_RT_SIGTIMEDWAIT", Const, 0, ""}, + {"SYS_RT_TGSIGQUEUEINFO", Const, 0, ""}, + {"SYS_SBRK", Const, 0, ""}, + {"SYS_SCHED_GETAFFINITY", Const, 0, ""}, + {"SYS_SCHED_GETPARAM", Const, 0, ""}, + {"SYS_SCHED_GETSCHEDULER", Const, 0, ""}, + {"SYS_SCHED_GET_PRIORITY_MAX", Const, 0, ""}, + {"SYS_SCHED_GET_PRIORITY_MIN", Const, 0, ""}, + {"SYS_SCHED_RR_GET_INTERVAL", Const, 0, ""}, + {"SYS_SCHED_SETAFFINITY", Const, 0, ""}, + {"SYS_SCHED_SETPARAM", Const, 0, ""}, + {"SYS_SCHED_SETSCHEDULER", Const, 0, ""}, + {"SYS_SCHED_YIELD", Const, 0, ""}, + {"SYS_SCTP_GENERIC_RECVMSG", Const, 0, ""}, + {"SYS_SCTP_GENERIC_SENDMSG", Const, 0, ""}, + {"SYS_SCTP_GENERIC_SENDMSG_IOV", Const, 0, ""}, + {"SYS_SCTP_PEELOFF", Const, 0, ""}, + {"SYS_SEARCHFS", Const, 0, ""}, + {"SYS_SECURITY", Const, 0, ""}, + {"SYS_SELECT", Const, 0, ""}, + {"SYS_SELECT_NOCANCEL", Const, 0, ""}, + {"SYS_SEMCONFIG", Const, 1, ""}, + {"SYS_SEMCTL", Const, 0, ""}, + {"SYS_SEMGET", Const, 0, ""}, + {"SYS_SEMOP", Const, 0, ""}, + {"SYS_SEMSYS", Const, 0, ""}, + {"SYS_SEMTIMEDOP", Const, 0, ""}, + {"SYS_SEM_CLOSE", Const, 0, ""}, + {"SYS_SEM_DESTROY", Const, 0, ""}, + {"SYS_SEM_GETVALUE", Const, 0, ""}, + {"SYS_SEM_INIT", Const, 0, ""}, + {"SYS_SEM_OPEN", Const, 0, ""}, + {"SYS_SEM_POST", Const, 0, ""}, + {"SYS_SEM_TRYWAIT", Const, 0, ""}, + {"SYS_SEM_UNLINK", Const, 0, ""}, + {"SYS_SEM_WAIT", Const, 0, ""}, + {"SYS_SEM_WAIT_NOCANCEL", Const, 0, ""}, + {"SYS_SEND", Const, 0, ""}, + {"SYS_SENDFILE", Const, 0, ""}, + {"SYS_SENDFILE64", Const, 0, ""}, + {"SYS_SENDMMSG", Const, 0, ""}, + {"SYS_SENDMSG", Const, 0, ""}, + {"SYS_SENDMSG_NOCANCEL", Const, 0, ""}, + {"SYS_SENDTO", Const, 0, ""}, + {"SYS_SENDTO_NOCANCEL", Const, 0, ""}, + {"SYS_SETATTRLIST", Const, 0, ""}, + {"SYS_SETAUDIT", Const, 0, ""}, + {"SYS_SETAUDIT_ADDR", Const, 0, ""}, + {"SYS_SETAUID", Const, 0, ""}, + {"SYS_SETCONTEXT", Const, 0, ""}, + {"SYS_SETDOMAINNAME", Const, 0, ""}, + {"SYS_SETEGID", Const, 0, ""}, + {"SYS_SETEUID", Const, 0, ""}, + {"SYS_SETFIB", Const, 0, ""}, + {"SYS_SETFSGID", Const, 0, ""}, + {"SYS_SETFSGID32", Const, 0, ""}, + {"SYS_SETFSUID", Const, 0, ""}, + {"SYS_SETFSUID32", Const, 0, ""}, + {"SYS_SETGID", Const, 0, ""}, + {"SYS_SETGID32", Const, 0, ""}, + {"SYS_SETGROUPS", Const, 0, ""}, + {"SYS_SETGROUPS32", Const, 0, ""}, + {"SYS_SETHOSTNAME", Const, 0, ""}, + {"SYS_SETITIMER", Const, 0, ""}, + {"SYS_SETLCID", Const, 0, ""}, + {"SYS_SETLOGIN", Const, 0, ""}, + {"SYS_SETLOGINCLASS", Const, 0, ""}, + {"SYS_SETNS", Const, 0, ""}, + {"SYS_SETPGID", Const, 0, ""}, + {"SYS_SETPRIORITY", Const, 0, ""}, + {"SYS_SETPRIVEXEC", Const, 0, ""}, + {"SYS_SETREGID", Const, 0, ""}, + {"SYS_SETREGID32", Const, 0, ""}, + {"SYS_SETRESGID", Const, 0, ""}, + {"SYS_SETRESGID32", Const, 0, ""}, + {"SYS_SETRESUID", Const, 0, ""}, + {"SYS_SETRESUID32", Const, 0, ""}, + {"SYS_SETREUID", Const, 0, ""}, + {"SYS_SETREUID32", Const, 0, ""}, + {"SYS_SETRLIMIT", Const, 0, ""}, + {"SYS_SETRTABLE", Const, 1, ""}, + {"SYS_SETSGROUPS", Const, 0, ""}, + {"SYS_SETSID", Const, 0, ""}, + {"SYS_SETSOCKOPT", Const, 0, ""}, + {"SYS_SETTID", Const, 0, ""}, + {"SYS_SETTID_WITH_PID", Const, 0, ""}, + {"SYS_SETTIMEOFDAY", Const, 0, ""}, + {"SYS_SETUID", Const, 0, ""}, + {"SYS_SETUID32", Const, 0, ""}, + {"SYS_SETWGROUPS", Const, 0, ""}, + {"SYS_SETXATTR", Const, 0, ""}, + {"SYS_SET_MEMPOLICY", Const, 0, ""}, + {"SYS_SET_ROBUST_LIST", Const, 0, ""}, + {"SYS_SET_THREAD_AREA", Const, 0, ""}, + {"SYS_SET_TID_ADDRESS", Const, 0, ""}, + {"SYS_SGETMASK", Const, 0, ""}, + {"SYS_SHARED_REGION_CHECK_NP", Const, 0, ""}, + {"SYS_SHARED_REGION_MAP_AND_SLIDE_NP", Const, 0, ""}, + {"SYS_SHMAT", Const, 0, ""}, + {"SYS_SHMCTL", Const, 0, ""}, + {"SYS_SHMDT", Const, 0, ""}, + {"SYS_SHMGET", Const, 0, ""}, + {"SYS_SHMSYS", Const, 0, ""}, + {"SYS_SHM_OPEN", Const, 0, ""}, + {"SYS_SHM_UNLINK", Const, 0, ""}, + {"SYS_SHUTDOWN", Const, 0, ""}, + {"SYS_SIGACTION", Const, 0, ""}, + {"SYS_SIGALTSTACK", Const, 0, ""}, + {"SYS_SIGNAL", Const, 0, ""}, + {"SYS_SIGNALFD", Const, 0, ""}, + {"SYS_SIGNALFD4", Const, 0, ""}, + {"SYS_SIGPENDING", Const, 0, ""}, + {"SYS_SIGPROCMASK", Const, 0, ""}, + {"SYS_SIGQUEUE", Const, 0, ""}, + {"SYS_SIGQUEUEINFO", Const, 1, ""}, + {"SYS_SIGRETURN", Const, 0, ""}, + {"SYS_SIGSUSPEND", Const, 0, ""}, + {"SYS_SIGSUSPEND_NOCANCEL", Const, 0, ""}, + {"SYS_SIGTIMEDWAIT", Const, 0, ""}, + {"SYS_SIGWAIT", Const, 0, ""}, + {"SYS_SIGWAITINFO", Const, 0, ""}, + {"SYS_SOCKET", Const, 0, ""}, + {"SYS_SOCKETCALL", Const, 0, ""}, + {"SYS_SOCKETPAIR", Const, 0, ""}, + {"SYS_SPLICE", Const, 0, ""}, + {"SYS_SSETMASK", Const, 0, ""}, + {"SYS_SSTK", Const, 0, ""}, + {"SYS_STACK_SNAPSHOT", Const, 0, ""}, + {"SYS_STAT", Const, 0, ""}, + {"SYS_STAT64", Const, 0, ""}, + {"SYS_STAT64_EXTENDED", Const, 0, ""}, + {"SYS_STATFS", Const, 0, ""}, + {"SYS_STATFS64", Const, 0, ""}, + {"SYS_STATV", Const, 0, ""}, + {"SYS_STATVFS1", Const, 1, ""}, + {"SYS_STAT_EXTENDED", Const, 0, ""}, + {"SYS_STIME", Const, 0, ""}, + {"SYS_STTY", Const, 0, ""}, + {"SYS_SWAPCONTEXT", Const, 0, ""}, + {"SYS_SWAPCTL", Const, 1, ""}, + {"SYS_SWAPOFF", Const, 0, ""}, + {"SYS_SWAPON", Const, 0, ""}, + {"SYS_SYMLINK", Const, 0, ""}, + {"SYS_SYMLINKAT", Const, 0, ""}, + {"SYS_SYNC", Const, 0, ""}, + {"SYS_SYNCFS", Const, 0, ""}, + {"SYS_SYNC_FILE_RANGE", Const, 0, ""}, + {"SYS_SYSARCH", Const, 0, ""}, + {"SYS_SYSCALL", Const, 0, ""}, + {"SYS_SYSCALL_BASE", Const, 0, ""}, + {"SYS_SYSFS", Const, 0, ""}, + {"SYS_SYSINFO", Const, 0, ""}, + {"SYS_SYSLOG", Const, 0, ""}, + {"SYS_TEE", Const, 0, ""}, + {"SYS_TGKILL", Const, 0, ""}, + {"SYS_THREAD_SELFID", Const, 0, ""}, + {"SYS_THR_CREATE", Const, 0, ""}, + {"SYS_THR_EXIT", Const, 0, ""}, + {"SYS_THR_KILL", Const, 0, ""}, + {"SYS_THR_KILL2", Const, 0, ""}, + {"SYS_THR_NEW", Const, 0, ""}, + {"SYS_THR_SELF", Const, 0, ""}, + {"SYS_THR_SET_NAME", Const, 0, ""}, + {"SYS_THR_SUSPEND", Const, 0, ""}, + {"SYS_THR_WAKE", Const, 0, ""}, + {"SYS_TIME", Const, 0, ""}, + {"SYS_TIMERFD_CREATE", Const, 0, ""}, + {"SYS_TIMERFD_GETTIME", Const, 0, ""}, + {"SYS_TIMERFD_SETTIME", Const, 0, ""}, + {"SYS_TIMER_CREATE", Const, 0, ""}, + {"SYS_TIMER_DELETE", Const, 0, ""}, + {"SYS_TIMER_GETOVERRUN", Const, 0, ""}, + {"SYS_TIMER_GETTIME", Const, 0, ""}, + {"SYS_TIMER_SETTIME", Const, 0, ""}, + {"SYS_TIMES", Const, 0, ""}, + {"SYS_TKILL", Const, 0, ""}, + {"SYS_TRUNCATE", Const, 0, ""}, + {"SYS_TRUNCATE64", Const, 0, ""}, + {"SYS_TUXCALL", Const, 0, ""}, + {"SYS_UGETRLIMIT", Const, 0, ""}, + {"SYS_ULIMIT", Const, 0, ""}, + {"SYS_UMASK", Const, 0, ""}, + {"SYS_UMASK_EXTENDED", Const, 0, ""}, + {"SYS_UMOUNT", Const, 0, ""}, + {"SYS_UMOUNT2", Const, 0, ""}, + {"SYS_UNAME", Const, 0, ""}, + {"SYS_UNDELETE", Const, 0, ""}, + {"SYS_UNLINK", Const, 0, ""}, + {"SYS_UNLINKAT", Const, 0, ""}, + {"SYS_UNMOUNT", Const, 0, ""}, + {"SYS_UNSHARE", Const, 0, ""}, + {"SYS_USELIB", Const, 0, ""}, + {"SYS_USTAT", Const, 0, ""}, + {"SYS_UTIME", Const, 0, ""}, + {"SYS_UTIMENSAT", Const, 0, ""}, + {"SYS_UTIMES", Const, 0, ""}, + {"SYS_UTRACE", Const, 0, ""}, + {"SYS_UUIDGEN", Const, 0, ""}, + {"SYS_VADVISE", Const, 1, ""}, + {"SYS_VFORK", Const, 0, ""}, + {"SYS_VHANGUP", Const, 0, ""}, + {"SYS_VM86", Const, 0, ""}, + {"SYS_VM86OLD", Const, 0, ""}, + {"SYS_VMSPLICE", Const, 0, ""}, + {"SYS_VM_PRESSURE_MONITOR", Const, 0, ""}, + {"SYS_VSERVER", Const, 0, ""}, + {"SYS_WAIT4", Const, 0, ""}, + {"SYS_WAIT4_NOCANCEL", Const, 0, ""}, + {"SYS_WAIT6", Const, 1, ""}, + {"SYS_WAITEVENT", Const, 0, ""}, + {"SYS_WAITID", Const, 0, ""}, + {"SYS_WAITID_NOCANCEL", Const, 0, ""}, + {"SYS_WAITPID", Const, 0, ""}, + {"SYS_WATCHEVENT", Const, 0, ""}, + {"SYS_WORKQ_KERNRETURN", Const, 0, ""}, + {"SYS_WORKQ_OPEN", Const, 0, ""}, + {"SYS_WRITE", Const, 0, ""}, + {"SYS_WRITEV", Const, 0, ""}, + {"SYS_WRITEV_NOCANCEL", Const, 0, ""}, + {"SYS_WRITE_NOCANCEL", Const, 0, ""}, + {"SYS_YIELD", Const, 0, ""}, + {"SYS__LLSEEK", Const, 0, ""}, + {"SYS__LWP_CONTINUE", Const, 1, ""}, + {"SYS__LWP_CREATE", Const, 1, ""}, + {"SYS__LWP_CTL", Const, 1, ""}, + {"SYS__LWP_DETACH", Const, 1, ""}, + {"SYS__LWP_EXIT", Const, 1, ""}, + {"SYS__LWP_GETNAME", Const, 1, ""}, + {"SYS__LWP_GETPRIVATE", Const, 1, ""}, + {"SYS__LWP_KILL", Const, 1, ""}, + {"SYS__LWP_PARK", Const, 1, ""}, + {"SYS__LWP_SELF", Const, 1, ""}, + {"SYS__LWP_SETNAME", Const, 1, ""}, + {"SYS__LWP_SETPRIVATE", Const, 1, ""}, + {"SYS__LWP_SUSPEND", Const, 1, ""}, + {"SYS__LWP_UNPARK", Const, 1, ""}, + {"SYS__LWP_UNPARK_ALL", Const, 1, ""}, + {"SYS__LWP_WAIT", Const, 1, ""}, + {"SYS__LWP_WAKEUP", Const, 1, ""}, + {"SYS__NEWSELECT", Const, 0, ""}, + {"SYS__PSET_BIND", Const, 1, ""}, + {"SYS__SCHED_GETAFFINITY", Const, 1, ""}, + {"SYS__SCHED_GETPARAM", Const, 1, ""}, + {"SYS__SCHED_SETAFFINITY", Const, 1, ""}, + {"SYS__SCHED_SETPARAM", Const, 1, ""}, + {"SYS__SYSCTL", Const, 0, ""}, + {"SYS__UMTX_LOCK", Const, 0, ""}, + {"SYS__UMTX_OP", Const, 0, ""}, + {"SYS__UMTX_UNLOCK", Const, 0, ""}, + {"SYS___ACL_ACLCHECK_FD", Const, 0, ""}, + {"SYS___ACL_ACLCHECK_FILE", Const, 0, ""}, + {"SYS___ACL_ACLCHECK_LINK", Const, 0, ""}, + {"SYS___ACL_DELETE_FD", Const, 0, ""}, + {"SYS___ACL_DELETE_FILE", Const, 0, ""}, + {"SYS___ACL_DELETE_LINK", Const, 0, ""}, + {"SYS___ACL_GET_FD", Const, 0, ""}, + {"SYS___ACL_GET_FILE", Const, 0, ""}, + {"SYS___ACL_GET_LINK", Const, 0, ""}, + {"SYS___ACL_SET_FD", Const, 0, ""}, + {"SYS___ACL_SET_FILE", Const, 0, ""}, + {"SYS___ACL_SET_LINK", Const, 0, ""}, + {"SYS___CAP_RIGHTS_GET", Const, 14, ""}, + {"SYS___CLONE", Const, 1, ""}, + {"SYS___DISABLE_THREADSIGNAL", Const, 0, ""}, + {"SYS___GETCWD", Const, 0, ""}, + {"SYS___GETLOGIN", Const, 1, ""}, + {"SYS___GET_TCB", Const, 1, ""}, + {"SYS___MAC_EXECVE", Const, 0, ""}, + {"SYS___MAC_GETFSSTAT", Const, 0, ""}, + {"SYS___MAC_GET_FD", Const, 0, ""}, + {"SYS___MAC_GET_FILE", Const, 0, ""}, + {"SYS___MAC_GET_LCID", Const, 0, ""}, + {"SYS___MAC_GET_LCTX", Const, 0, ""}, + {"SYS___MAC_GET_LINK", Const, 0, ""}, + {"SYS___MAC_GET_MOUNT", Const, 0, ""}, + {"SYS___MAC_GET_PID", Const, 0, ""}, + {"SYS___MAC_GET_PROC", Const, 0, ""}, + {"SYS___MAC_MOUNT", Const, 0, ""}, + {"SYS___MAC_SET_FD", Const, 0, ""}, + {"SYS___MAC_SET_FILE", Const, 0, ""}, + {"SYS___MAC_SET_LCTX", Const, 0, ""}, + {"SYS___MAC_SET_LINK", Const, 0, ""}, + {"SYS___MAC_SET_PROC", Const, 0, ""}, + {"SYS___MAC_SYSCALL", Const, 0, ""}, + {"SYS___OLD_SEMWAIT_SIGNAL", Const, 0, ""}, + {"SYS___OLD_SEMWAIT_SIGNAL_NOCANCEL", Const, 0, ""}, + {"SYS___POSIX_CHOWN", Const, 1, ""}, + {"SYS___POSIX_FCHOWN", Const, 1, ""}, + {"SYS___POSIX_LCHOWN", Const, 1, ""}, + {"SYS___POSIX_RENAME", Const, 1, ""}, + {"SYS___PTHREAD_CANCELED", Const, 0, ""}, + {"SYS___PTHREAD_CHDIR", Const, 0, ""}, + {"SYS___PTHREAD_FCHDIR", Const, 0, ""}, + {"SYS___PTHREAD_KILL", Const, 0, ""}, + {"SYS___PTHREAD_MARKCANCEL", Const, 0, ""}, + {"SYS___PTHREAD_SIGMASK", Const, 0, ""}, + {"SYS___QUOTACTL", Const, 1, ""}, + {"SYS___SEMCTL", Const, 1, ""}, + {"SYS___SEMWAIT_SIGNAL", Const, 0, ""}, + {"SYS___SEMWAIT_SIGNAL_NOCANCEL", Const, 0, ""}, + {"SYS___SETLOGIN", Const, 1, ""}, + {"SYS___SETUGID", Const, 0, ""}, + {"SYS___SET_TCB", Const, 1, ""}, + {"SYS___SIGACTION_SIGTRAMP", Const, 1, ""}, + {"SYS___SIGTIMEDWAIT", Const, 1, ""}, + {"SYS___SIGWAIT", Const, 0, ""}, + {"SYS___SIGWAIT_NOCANCEL", Const, 0, ""}, + {"SYS___SYSCTL", Const, 0, ""}, + {"SYS___TFORK", Const, 1, ""}, + {"SYS___THREXIT", Const, 1, ""}, + {"SYS___THRSIGDIVERT", Const, 1, ""}, + {"SYS___THRSLEEP", Const, 1, ""}, + {"SYS___THRWAKEUP", Const, 1, ""}, + {"S_ARCH1", Const, 1, ""}, + {"S_ARCH2", Const, 1, ""}, + {"S_BLKSIZE", Const, 0, ""}, + {"S_IEXEC", Const, 0, ""}, + {"S_IFBLK", Const, 0, ""}, + {"S_IFCHR", Const, 0, ""}, + {"S_IFDIR", Const, 0, ""}, + {"S_IFIFO", Const, 0, ""}, + {"S_IFLNK", Const, 0, ""}, + {"S_IFMT", Const, 0, ""}, + {"S_IFREG", Const, 0, ""}, + {"S_IFSOCK", Const, 0, ""}, + {"S_IFWHT", Const, 0, ""}, + {"S_IREAD", Const, 0, ""}, + {"S_IRGRP", Const, 0, ""}, + {"S_IROTH", Const, 0, ""}, + {"S_IRUSR", Const, 0, ""}, + {"S_IRWXG", Const, 0, ""}, + {"S_IRWXO", Const, 0, ""}, + {"S_IRWXU", Const, 0, ""}, + {"S_ISGID", Const, 0, ""}, + {"S_ISTXT", Const, 0, ""}, + {"S_ISUID", Const, 0, ""}, + {"S_ISVTX", Const, 0, ""}, + {"S_IWGRP", Const, 0, ""}, + {"S_IWOTH", Const, 0, ""}, + {"S_IWRITE", Const, 0, ""}, + {"S_IWUSR", Const, 0, ""}, + {"S_IXGRP", Const, 0, ""}, + {"S_IXOTH", Const, 0, ""}, + {"S_IXUSR", Const, 0, ""}, + {"S_LOGIN_SET", Const, 1, ""}, + {"SecurityAttributes", Type, 0, ""}, + {"SecurityAttributes.InheritHandle", Field, 0, ""}, + {"SecurityAttributes.Length", Field, 0, ""}, + {"SecurityAttributes.SecurityDescriptor", Field, 0, ""}, + {"Seek", Func, 0, "func(fd int, offset int64, whence int) (off int64, err error)"}, + {"Select", Func, 0, "func(nfd int, r *FdSet, w *FdSet, e *FdSet, timeout *Timeval) (n int, err error)"}, + {"Sendfile", Func, 0, "func(outfd int, infd int, offset *int64, count int) (written int, err error)"}, + {"Sendmsg", Func, 0, "func(fd int, p []byte, oob []byte, to Sockaddr, flags int) (err error)"}, + {"SendmsgN", Func, 3, "func(fd int, p []byte, oob []byte, to Sockaddr, flags int) (n int, err error)"}, + {"Sendto", Func, 0, "func(fd int, p []byte, flags int, to Sockaddr) (err error)"}, + {"Servent", Type, 0, ""}, + {"Servent.Aliases", Field, 0, ""}, + {"Servent.Name", Field, 0, ""}, + {"Servent.Port", Field, 0, ""}, + {"Servent.Proto", Field, 0, ""}, + {"SetBpf", Func, 0, ""}, + {"SetBpfBuflen", Func, 0, ""}, + {"SetBpfDatalink", Func, 0, ""}, + {"SetBpfHeadercmpl", Func, 0, ""}, + {"SetBpfImmediate", Func, 0, ""}, + {"SetBpfInterface", Func, 0, ""}, + {"SetBpfPromisc", Func, 0, ""}, + {"SetBpfTimeout", Func, 0, ""}, + {"SetCurrentDirectory", Func, 0, ""}, + {"SetEndOfFile", Func, 0, ""}, + {"SetEnvironmentVariable", Func, 0, ""}, + {"SetFileAttributes", Func, 0, ""}, + {"SetFileCompletionNotificationModes", Func, 2, ""}, + {"SetFilePointer", Func, 0, ""}, + {"SetFileTime", Func, 0, ""}, + {"SetHandleInformation", Func, 0, ""}, + {"SetKevent", Func, 0, ""}, + {"SetLsfPromisc", Func, 0, "func(name string, m bool) error"}, + {"SetNonblock", Func, 0, "func(fd int, nonblocking bool) (err error)"}, + {"Setdomainname", Func, 0, "func(p []byte) (err error)"}, + {"Setegid", Func, 0, "func(egid int) (err error)"}, + {"Setenv", Func, 0, "func(key string, value string) error"}, + {"Seteuid", Func, 0, "func(euid int) (err error)"}, + {"Setfsgid", Func, 0, "func(gid int) (err error)"}, + {"Setfsuid", Func, 0, "func(uid int) (err error)"}, + {"Setgid", Func, 0, "func(gid int) (err error)"}, + {"Setgroups", Func, 0, "func(gids []int) (err error)"}, + {"Sethostname", Func, 0, "func(p []byte) (err error)"}, + {"Setlogin", Func, 0, ""}, + {"Setpgid", Func, 0, "func(pid int, pgid int) (err error)"}, + {"Setpriority", Func, 0, "func(which int, who int, prio int) (err error)"}, + {"Setprivexec", Func, 0, ""}, + {"Setregid", Func, 0, "func(rgid int, egid int) (err error)"}, + {"Setresgid", Func, 0, "func(rgid int, egid int, sgid int) (err error)"}, + {"Setresuid", Func, 0, "func(ruid int, euid int, suid int) (err error)"}, + {"Setreuid", Func, 0, "func(ruid int, euid int) (err error)"}, + {"Setrlimit", Func, 0, "func(resource int, rlim *Rlimit) error"}, + {"Setsid", Func, 0, "func() (pid int, err error)"}, + {"Setsockopt", Func, 0, ""}, + {"SetsockoptByte", Func, 0, "func(fd int, level int, opt int, value byte) (err error)"}, + {"SetsockoptICMPv6Filter", Func, 2, "func(fd int, level int, opt int, filter *ICMPv6Filter) error"}, + {"SetsockoptIPMreq", Func, 0, "func(fd int, level int, opt int, mreq *IPMreq) (err error)"}, + {"SetsockoptIPMreqn", Func, 0, "func(fd int, level int, opt int, mreq *IPMreqn) (err error)"}, + {"SetsockoptIPv6Mreq", Func, 0, "func(fd int, level int, opt int, mreq *IPv6Mreq) (err error)"}, + {"SetsockoptInet4Addr", Func, 0, "func(fd int, level int, opt int, value [4]byte) (err error)"}, + {"SetsockoptInt", Func, 0, "func(fd int, level int, opt int, value int) (err error)"}, + {"SetsockoptLinger", Func, 0, "func(fd int, level int, opt int, l *Linger) (err error)"}, + {"SetsockoptString", Func, 0, "func(fd int, level int, opt int, s string) (err error)"}, + {"SetsockoptTimeval", Func, 0, "func(fd int, level int, opt int, tv *Timeval) (err error)"}, + {"Settimeofday", Func, 0, "func(tv *Timeval) (err error)"}, + {"Setuid", Func, 0, "func(uid int) (err error)"}, + {"Setxattr", Func, 1, "func(path string, attr string, data []byte, flags int) (err error)"}, + {"Shutdown", Func, 0, "func(fd int, how int) (err error)"}, + {"SidTypeAlias", Const, 0, ""}, + {"SidTypeComputer", Const, 0, ""}, + {"SidTypeDeletedAccount", Const, 0, ""}, + {"SidTypeDomain", Const, 0, ""}, + {"SidTypeGroup", Const, 0, ""}, + {"SidTypeInvalid", Const, 0, ""}, + {"SidTypeLabel", Const, 0, ""}, + {"SidTypeUnknown", Const, 0, ""}, + {"SidTypeUser", Const, 0, ""}, + {"SidTypeWellKnownGroup", Const, 0, ""}, + {"Signal", Type, 0, ""}, + {"SizeofBpfHdr", Const, 0, ""}, + {"SizeofBpfInsn", Const, 0, ""}, + {"SizeofBpfProgram", Const, 0, ""}, + {"SizeofBpfStat", Const, 0, ""}, + {"SizeofBpfVersion", Const, 0, ""}, + {"SizeofBpfZbuf", Const, 0, ""}, + {"SizeofBpfZbufHeader", Const, 0, ""}, + {"SizeofCmsghdr", Const, 0, ""}, + {"SizeofICMPv6Filter", Const, 2, ""}, + {"SizeofIPMreq", Const, 0, ""}, + {"SizeofIPMreqn", Const, 0, ""}, + {"SizeofIPv6MTUInfo", Const, 2, ""}, + {"SizeofIPv6Mreq", Const, 0, ""}, + {"SizeofIfAddrmsg", Const, 0, ""}, + {"SizeofIfAnnounceMsghdr", Const, 1, ""}, + {"SizeofIfData", Const, 0, ""}, + {"SizeofIfInfomsg", Const, 0, ""}, + {"SizeofIfMsghdr", Const, 0, ""}, + {"SizeofIfaMsghdr", Const, 0, ""}, + {"SizeofIfmaMsghdr", Const, 0, ""}, + {"SizeofIfmaMsghdr2", Const, 0, ""}, + {"SizeofInet4Pktinfo", Const, 0, ""}, + {"SizeofInet6Pktinfo", Const, 0, ""}, + {"SizeofInotifyEvent", Const, 0, ""}, + {"SizeofLinger", Const, 0, ""}, + {"SizeofMsghdr", Const, 0, ""}, + {"SizeofNlAttr", Const, 0, ""}, + {"SizeofNlMsgerr", Const, 0, ""}, + {"SizeofNlMsghdr", Const, 0, ""}, + {"SizeofRtAttr", Const, 0, ""}, + {"SizeofRtGenmsg", Const, 0, ""}, + {"SizeofRtMetrics", Const, 0, ""}, + {"SizeofRtMsg", Const, 0, ""}, + {"SizeofRtMsghdr", Const, 0, ""}, + {"SizeofRtNexthop", Const, 0, ""}, + {"SizeofSockFilter", Const, 0, ""}, + {"SizeofSockFprog", Const, 0, ""}, + {"SizeofSockaddrAny", Const, 0, ""}, + {"SizeofSockaddrDatalink", Const, 0, ""}, + {"SizeofSockaddrInet4", Const, 0, ""}, + {"SizeofSockaddrInet6", Const, 0, ""}, + {"SizeofSockaddrLinklayer", Const, 0, ""}, + {"SizeofSockaddrNetlink", Const, 0, ""}, + {"SizeofSockaddrUnix", Const, 0, ""}, + {"SizeofTCPInfo", Const, 1, ""}, + {"SizeofUcred", Const, 0, ""}, + {"SlicePtrFromStrings", Func, 1, "func(ss []string) ([]*byte, error)"}, + {"SockFilter", Type, 0, ""}, + {"SockFilter.Code", Field, 0, ""}, + {"SockFilter.Jf", Field, 0, ""}, + {"SockFilter.Jt", Field, 0, ""}, + {"SockFilter.K", Field, 0, ""}, + {"SockFprog", Type, 0, ""}, + {"SockFprog.Filter", Field, 0, ""}, + {"SockFprog.Len", Field, 0, ""}, + {"SockFprog.Pad_cgo_0", Field, 0, ""}, + {"Sockaddr", Type, 0, ""}, + {"SockaddrDatalink", Type, 0, ""}, + {"SockaddrDatalink.Alen", Field, 0, ""}, + {"SockaddrDatalink.Data", Field, 0, ""}, + {"SockaddrDatalink.Family", Field, 0, ""}, + {"SockaddrDatalink.Index", Field, 0, ""}, + {"SockaddrDatalink.Len", Field, 0, ""}, + {"SockaddrDatalink.Nlen", Field, 0, ""}, + {"SockaddrDatalink.Slen", Field, 0, ""}, + {"SockaddrDatalink.Type", Field, 0, ""}, + {"SockaddrGen", Type, 0, ""}, + {"SockaddrInet4", Type, 0, ""}, + {"SockaddrInet4.Addr", Field, 0, ""}, + {"SockaddrInet4.Port", Field, 0, ""}, + {"SockaddrInet6", Type, 0, ""}, + {"SockaddrInet6.Addr", Field, 0, ""}, + {"SockaddrInet6.Port", Field, 0, ""}, + {"SockaddrInet6.ZoneId", Field, 0, ""}, + {"SockaddrLinklayer", Type, 0, ""}, + {"SockaddrLinklayer.Addr", Field, 0, ""}, + {"SockaddrLinklayer.Halen", Field, 0, ""}, + {"SockaddrLinklayer.Hatype", Field, 0, ""}, + {"SockaddrLinklayer.Ifindex", Field, 0, ""}, + {"SockaddrLinklayer.Pkttype", Field, 0, ""}, + {"SockaddrLinklayer.Protocol", Field, 0, ""}, + {"SockaddrNetlink", Type, 0, ""}, + {"SockaddrNetlink.Family", Field, 0, ""}, + {"SockaddrNetlink.Groups", Field, 0, ""}, + {"SockaddrNetlink.Pad", Field, 0, ""}, + {"SockaddrNetlink.Pid", Field, 0, ""}, + {"SockaddrUnix", Type, 0, ""}, + {"SockaddrUnix.Name", Field, 0, ""}, + {"Socket", Func, 0, "func(domain int, typ int, proto int) (fd int, err error)"}, + {"SocketControlMessage", Type, 0, ""}, + {"SocketControlMessage.Data", Field, 0, ""}, + {"SocketControlMessage.Header", Field, 0, ""}, + {"SocketDisableIPv6", Var, 0, ""}, + {"Socketpair", Func, 0, "func(domain int, typ int, proto int) (fd [2]int, err error)"}, + {"Splice", Func, 0, "func(rfd int, roff *int64, wfd int, woff *int64, len int, flags int) (n int64, err error)"}, + {"StartProcess", Func, 0, "func(argv0 string, argv []string, attr *ProcAttr) (pid int, handle uintptr, err error)"}, + {"StartupInfo", Type, 0, ""}, + {"StartupInfo.Cb", Field, 0, ""}, + {"StartupInfo.Desktop", Field, 0, ""}, + {"StartupInfo.FillAttribute", Field, 0, ""}, + {"StartupInfo.Flags", Field, 0, ""}, + {"StartupInfo.ShowWindow", Field, 0, ""}, + {"StartupInfo.StdErr", Field, 0, ""}, + {"StartupInfo.StdInput", Field, 0, ""}, + {"StartupInfo.StdOutput", Field, 0, ""}, + {"StartupInfo.Title", Field, 0, ""}, + {"StartupInfo.X", Field, 0, ""}, + {"StartupInfo.XCountChars", Field, 0, ""}, + {"StartupInfo.XSize", Field, 0, ""}, + {"StartupInfo.Y", Field, 0, ""}, + {"StartupInfo.YCountChars", Field, 0, ""}, + {"StartupInfo.YSize", Field, 0, ""}, + {"Stat", Func, 0, "func(path string, stat *Stat_t) (err error)"}, + {"Stat_t", Type, 0, ""}, + {"Stat_t.Atim", Field, 0, ""}, + {"Stat_t.Atim_ext", Field, 12, ""}, + {"Stat_t.Atimespec", Field, 0, ""}, + {"Stat_t.Birthtimespec", Field, 0, ""}, + {"Stat_t.Blksize", Field, 0, ""}, + {"Stat_t.Blocks", Field, 0, ""}, + {"Stat_t.Btim_ext", Field, 12, ""}, + {"Stat_t.Ctim", Field, 0, ""}, + {"Stat_t.Ctim_ext", Field, 12, ""}, + {"Stat_t.Ctimespec", Field, 0, ""}, + {"Stat_t.Dev", Field, 0, ""}, + {"Stat_t.Flags", Field, 0, ""}, + {"Stat_t.Gen", Field, 0, ""}, + {"Stat_t.Gid", Field, 0, ""}, + {"Stat_t.Ino", Field, 0, ""}, + {"Stat_t.Lspare", Field, 0, ""}, + {"Stat_t.Lspare0", Field, 2, ""}, + {"Stat_t.Lspare1", Field, 2, ""}, + {"Stat_t.Mode", Field, 0, ""}, + {"Stat_t.Mtim", Field, 0, ""}, + {"Stat_t.Mtim_ext", Field, 12, ""}, + {"Stat_t.Mtimespec", Field, 0, ""}, + {"Stat_t.Nlink", Field, 0, ""}, + {"Stat_t.Pad_cgo_0", Field, 0, ""}, + {"Stat_t.Pad_cgo_1", Field, 0, ""}, + {"Stat_t.Pad_cgo_2", Field, 0, ""}, + {"Stat_t.Padding0", Field, 12, ""}, + {"Stat_t.Padding1", Field, 12, ""}, + {"Stat_t.Qspare", Field, 0, ""}, + {"Stat_t.Rdev", Field, 0, ""}, + {"Stat_t.Size", Field, 0, ""}, + {"Stat_t.Spare", Field, 2, ""}, + {"Stat_t.Uid", Field, 0, ""}, + {"Stat_t.X__pad0", Field, 0, ""}, + {"Stat_t.X__pad1", Field, 0, ""}, + {"Stat_t.X__pad2", Field, 0, ""}, + {"Stat_t.X__st_birthtim", Field, 2, ""}, + {"Stat_t.X__st_ino", Field, 0, ""}, + {"Stat_t.X__unused", Field, 0, ""}, + {"Statfs", Func, 0, "func(path string, buf *Statfs_t) (err error)"}, + {"Statfs_t", Type, 0, ""}, + {"Statfs_t.Asyncreads", Field, 0, ""}, + {"Statfs_t.Asyncwrites", Field, 0, ""}, + {"Statfs_t.Bavail", Field, 0, ""}, + {"Statfs_t.Bfree", Field, 0, ""}, + {"Statfs_t.Blocks", Field, 0, ""}, + {"Statfs_t.Bsize", Field, 0, ""}, + {"Statfs_t.Charspare", Field, 0, ""}, + {"Statfs_t.F_asyncreads", Field, 2, ""}, + {"Statfs_t.F_asyncwrites", Field, 2, ""}, + {"Statfs_t.F_bavail", Field, 2, ""}, + {"Statfs_t.F_bfree", Field, 2, ""}, + {"Statfs_t.F_blocks", Field, 2, ""}, + {"Statfs_t.F_bsize", Field, 2, ""}, + {"Statfs_t.F_ctime", Field, 2, ""}, + {"Statfs_t.F_favail", Field, 2, ""}, + {"Statfs_t.F_ffree", Field, 2, ""}, + {"Statfs_t.F_files", Field, 2, ""}, + {"Statfs_t.F_flags", Field, 2, ""}, + {"Statfs_t.F_fsid", Field, 2, ""}, + {"Statfs_t.F_fstypename", Field, 2, ""}, + {"Statfs_t.F_iosize", Field, 2, ""}, + {"Statfs_t.F_mntfromname", Field, 2, ""}, + {"Statfs_t.F_mntfromspec", Field, 3, ""}, + {"Statfs_t.F_mntonname", Field, 2, ""}, + {"Statfs_t.F_namemax", Field, 2, ""}, + {"Statfs_t.F_owner", Field, 2, ""}, + {"Statfs_t.F_spare", Field, 2, ""}, + {"Statfs_t.F_syncreads", Field, 2, ""}, + {"Statfs_t.F_syncwrites", Field, 2, ""}, + {"Statfs_t.Ffree", Field, 0, ""}, + {"Statfs_t.Files", Field, 0, ""}, + {"Statfs_t.Flags", Field, 0, ""}, + {"Statfs_t.Frsize", Field, 0, ""}, + {"Statfs_t.Fsid", Field, 0, ""}, + {"Statfs_t.Fssubtype", Field, 0, ""}, + {"Statfs_t.Fstypename", Field, 0, ""}, + {"Statfs_t.Iosize", Field, 0, ""}, + {"Statfs_t.Mntfromname", Field, 0, ""}, + {"Statfs_t.Mntonname", Field, 0, ""}, + {"Statfs_t.Mount_info", Field, 2, ""}, + {"Statfs_t.Namelen", Field, 0, ""}, + {"Statfs_t.Namemax", Field, 0, ""}, + {"Statfs_t.Owner", Field, 0, ""}, + {"Statfs_t.Pad_cgo_0", Field, 0, ""}, + {"Statfs_t.Pad_cgo_1", Field, 2, ""}, + {"Statfs_t.Reserved", Field, 0, ""}, + {"Statfs_t.Spare", Field, 0, ""}, + {"Statfs_t.Syncreads", Field, 0, ""}, + {"Statfs_t.Syncwrites", Field, 0, ""}, + {"Statfs_t.Type", Field, 0, ""}, + {"Statfs_t.Version", Field, 0, ""}, + {"Stderr", Var, 0, ""}, + {"Stdin", Var, 0, ""}, + {"Stdout", Var, 0, ""}, + {"StringBytePtr", Func, 0, "func(s string) *byte"}, + {"StringByteSlice", Func, 0, "func(s string) []byte"}, + {"StringSlicePtr", Func, 0, "func(ss []string) []*byte"}, + {"StringToSid", Func, 0, ""}, + {"StringToUTF16", Func, 0, ""}, + {"StringToUTF16Ptr", Func, 0, ""}, + {"Symlink", Func, 0, "func(oldpath string, newpath string) (err error)"}, + {"Sync", Func, 0, "func()"}, + {"SyncFileRange", Func, 0, "func(fd int, off int64, n int64, flags int) (err error)"}, + {"SysProcAttr", Type, 0, ""}, + {"SysProcAttr.AdditionalInheritedHandles", Field, 17, ""}, + {"SysProcAttr.AmbientCaps", Field, 9, ""}, + {"SysProcAttr.CgroupFD", Field, 20, ""}, + {"SysProcAttr.Chroot", Field, 0, ""}, + {"SysProcAttr.Cloneflags", Field, 2, ""}, + {"SysProcAttr.CmdLine", Field, 0, ""}, + {"SysProcAttr.CreationFlags", Field, 1, ""}, + {"SysProcAttr.Credential", Field, 0, ""}, + {"SysProcAttr.Ctty", Field, 1, ""}, + {"SysProcAttr.Foreground", Field, 5, ""}, + {"SysProcAttr.GidMappings", Field, 4, ""}, + {"SysProcAttr.GidMappingsEnableSetgroups", Field, 5, ""}, + {"SysProcAttr.HideWindow", Field, 0, ""}, + {"SysProcAttr.Jail", Field, 21, ""}, + {"SysProcAttr.NoInheritHandles", Field, 16, ""}, + {"SysProcAttr.Noctty", Field, 0, ""}, + {"SysProcAttr.ParentProcess", Field, 17, ""}, + {"SysProcAttr.Pdeathsig", Field, 0, ""}, + {"SysProcAttr.Pgid", Field, 5, ""}, + {"SysProcAttr.PidFD", Field, 22, ""}, + {"SysProcAttr.ProcessAttributes", Field, 13, ""}, + {"SysProcAttr.Ptrace", Field, 0, ""}, + {"SysProcAttr.Setctty", Field, 0, ""}, + {"SysProcAttr.Setpgid", Field, 0, ""}, + {"SysProcAttr.Setsid", Field, 0, ""}, + {"SysProcAttr.ThreadAttributes", Field, 13, ""}, + {"SysProcAttr.Token", Field, 10, ""}, + {"SysProcAttr.UidMappings", Field, 4, ""}, + {"SysProcAttr.Unshareflags", Field, 7, ""}, + {"SysProcAttr.UseCgroupFD", Field, 20, ""}, + {"SysProcIDMap", Type, 4, ""}, + {"SysProcIDMap.ContainerID", Field, 4, ""}, + {"SysProcIDMap.HostID", Field, 4, ""}, + {"SysProcIDMap.Size", Field, 4, ""}, + {"Syscall", Func, 0, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, + {"Syscall12", Func, 0, ""}, + {"Syscall15", Func, 0, ""}, + {"Syscall18", Func, 12, ""}, + {"Syscall6", Func, 0, "func(trap uintptr, a1 uintptr, a2 uintptr, a3 uintptr, a4 uintptr, a5 uintptr, a6 uintptr) (r1 uintptr, r2 uintptr, err Errno)"}, + {"Syscall9", Func, 0, ""}, + {"SyscallN", Func, 18, ""}, + {"Sysctl", Func, 0, ""}, + {"SysctlUint32", Func, 0, ""}, + {"Sysctlnode", Type, 2, ""}, + {"Sysctlnode.Flags", Field, 2, ""}, + {"Sysctlnode.Name", Field, 2, ""}, + {"Sysctlnode.Num", Field, 2, ""}, + {"Sysctlnode.Un", Field, 2, ""}, + {"Sysctlnode.Ver", Field, 2, ""}, + {"Sysctlnode.X__rsvd", Field, 2, ""}, + {"Sysctlnode.X_sysctl_desc", Field, 2, ""}, + {"Sysctlnode.X_sysctl_func", Field, 2, ""}, + {"Sysctlnode.X_sysctl_parent", Field, 2, ""}, + {"Sysctlnode.X_sysctl_size", Field, 2, ""}, + {"Sysinfo", Func, 0, "func(info *Sysinfo_t) (err error)"}, + {"Sysinfo_t", Type, 0, ""}, + {"Sysinfo_t.Bufferram", Field, 0, ""}, + {"Sysinfo_t.Freehigh", Field, 0, ""}, + {"Sysinfo_t.Freeram", Field, 0, ""}, + {"Sysinfo_t.Freeswap", Field, 0, ""}, + {"Sysinfo_t.Loads", Field, 0, ""}, + {"Sysinfo_t.Pad", Field, 0, ""}, + {"Sysinfo_t.Pad_cgo_0", Field, 0, ""}, + {"Sysinfo_t.Pad_cgo_1", Field, 0, ""}, + {"Sysinfo_t.Procs", Field, 0, ""}, + {"Sysinfo_t.Sharedram", Field, 0, ""}, + {"Sysinfo_t.Totalhigh", Field, 0, ""}, + {"Sysinfo_t.Totalram", Field, 0, ""}, + {"Sysinfo_t.Totalswap", Field, 0, ""}, + {"Sysinfo_t.Unit", Field, 0, ""}, + {"Sysinfo_t.Uptime", Field, 0, ""}, + {"Sysinfo_t.X_f", Field, 0, ""}, + {"Systemtime", Type, 0, ""}, + {"Systemtime.Day", Field, 0, ""}, + {"Systemtime.DayOfWeek", Field, 0, ""}, + {"Systemtime.Hour", Field, 0, ""}, + {"Systemtime.Milliseconds", Field, 0, ""}, + {"Systemtime.Minute", Field, 0, ""}, + {"Systemtime.Month", Field, 0, ""}, + {"Systemtime.Second", Field, 0, ""}, + {"Systemtime.Year", Field, 0, ""}, + {"TCGETS", Const, 0, ""}, + {"TCIFLUSH", Const, 1, ""}, + {"TCIOFLUSH", Const, 1, ""}, + {"TCOFLUSH", Const, 1, ""}, + {"TCPInfo", Type, 1, ""}, + {"TCPInfo.Advmss", Field, 1, ""}, + {"TCPInfo.Ato", Field, 1, ""}, + {"TCPInfo.Backoff", Field, 1, ""}, + {"TCPInfo.Ca_state", Field, 1, ""}, + {"TCPInfo.Fackets", Field, 1, ""}, + {"TCPInfo.Last_ack_recv", Field, 1, ""}, + {"TCPInfo.Last_ack_sent", Field, 1, ""}, + {"TCPInfo.Last_data_recv", Field, 1, ""}, + {"TCPInfo.Last_data_sent", Field, 1, ""}, + {"TCPInfo.Lost", Field, 1, ""}, + {"TCPInfo.Options", Field, 1, ""}, + {"TCPInfo.Pad_cgo_0", Field, 1, ""}, + {"TCPInfo.Pmtu", Field, 1, ""}, + {"TCPInfo.Probes", Field, 1, ""}, + {"TCPInfo.Rcv_mss", Field, 1, ""}, + {"TCPInfo.Rcv_rtt", Field, 1, ""}, + {"TCPInfo.Rcv_space", Field, 1, ""}, + {"TCPInfo.Rcv_ssthresh", Field, 1, ""}, + {"TCPInfo.Reordering", Field, 1, ""}, + {"TCPInfo.Retrans", Field, 1, ""}, + {"TCPInfo.Retransmits", Field, 1, ""}, + {"TCPInfo.Rto", Field, 1, ""}, + {"TCPInfo.Rtt", Field, 1, ""}, + {"TCPInfo.Rttvar", Field, 1, ""}, + {"TCPInfo.Sacked", Field, 1, ""}, + {"TCPInfo.Snd_cwnd", Field, 1, ""}, + {"TCPInfo.Snd_mss", Field, 1, ""}, + {"TCPInfo.Snd_ssthresh", Field, 1, ""}, + {"TCPInfo.State", Field, 1, ""}, + {"TCPInfo.Total_retrans", Field, 1, ""}, + {"TCPInfo.Unacked", Field, 1, ""}, + {"TCPKeepalive", Type, 3, ""}, + {"TCPKeepalive.Interval", Field, 3, ""}, + {"TCPKeepalive.OnOff", Field, 3, ""}, + {"TCPKeepalive.Time", Field, 3, ""}, + {"TCP_CA_NAME_MAX", Const, 0, ""}, + {"TCP_CONGCTL", Const, 1, ""}, + {"TCP_CONGESTION", Const, 0, ""}, + {"TCP_CONNECTIONTIMEOUT", Const, 0, ""}, + {"TCP_CORK", Const, 0, ""}, + {"TCP_DEFER_ACCEPT", Const, 0, ""}, + {"TCP_ENABLE_ECN", Const, 16, ""}, + {"TCP_INFO", Const, 0, ""}, + {"TCP_KEEPALIVE", Const, 0, ""}, + {"TCP_KEEPCNT", Const, 0, ""}, + {"TCP_KEEPIDLE", Const, 0, ""}, + {"TCP_KEEPINIT", Const, 1, ""}, + {"TCP_KEEPINTVL", Const, 0, ""}, + {"TCP_LINGER2", Const, 0, ""}, + {"TCP_MAXBURST", Const, 0, ""}, + {"TCP_MAXHLEN", Const, 0, ""}, + {"TCP_MAXOLEN", Const, 0, ""}, + {"TCP_MAXSEG", Const, 0, ""}, + {"TCP_MAXWIN", Const, 0, ""}, + {"TCP_MAX_SACK", Const, 0, ""}, + {"TCP_MAX_WINSHIFT", Const, 0, ""}, + {"TCP_MD5SIG", Const, 0, ""}, + {"TCP_MD5SIG_MAXKEYLEN", Const, 0, ""}, + {"TCP_MINMSS", Const, 0, ""}, + {"TCP_MINMSSOVERLOAD", Const, 0, ""}, + {"TCP_MSS", Const, 0, ""}, + {"TCP_NODELAY", Const, 0, ""}, + {"TCP_NOOPT", Const, 0, ""}, + {"TCP_NOPUSH", Const, 0, ""}, + {"TCP_NOTSENT_LOWAT", Const, 16, ""}, + {"TCP_NSTATES", Const, 1, ""}, + {"TCP_QUICKACK", Const, 0, ""}, + {"TCP_RXT_CONNDROPTIME", Const, 0, ""}, + {"TCP_RXT_FINDROP", Const, 0, ""}, + {"TCP_SACK_ENABLE", Const, 1, ""}, + {"TCP_SENDMOREACKS", Const, 16, ""}, + {"TCP_SYNCNT", Const, 0, ""}, + {"TCP_VENDOR", Const, 3, ""}, + {"TCP_WINDOW_CLAMP", Const, 0, ""}, + {"TCSAFLUSH", Const, 1, ""}, + {"TCSETS", Const, 0, ""}, + {"TF_DISCONNECT", Const, 0, ""}, + {"TF_REUSE_SOCKET", Const, 0, ""}, + {"TF_USE_DEFAULT_WORKER", Const, 0, ""}, + {"TF_USE_KERNEL_APC", Const, 0, ""}, + {"TF_USE_SYSTEM_THREAD", Const, 0, ""}, + {"TF_WRITE_BEHIND", Const, 0, ""}, + {"TH32CS_INHERIT", Const, 4, ""}, + {"TH32CS_SNAPALL", Const, 4, ""}, + {"TH32CS_SNAPHEAPLIST", Const, 4, ""}, + {"TH32CS_SNAPMODULE", Const, 4, ""}, + {"TH32CS_SNAPMODULE32", Const, 4, ""}, + {"TH32CS_SNAPPROCESS", Const, 4, ""}, + {"TH32CS_SNAPTHREAD", Const, 4, ""}, + {"TIME_ZONE_ID_DAYLIGHT", Const, 0, ""}, + {"TIME_ZONE_ID_STANDARD", Const, 0, ""}, + {"TIME_ZONE_ID_UNKNOWN", Const, 0, ""}, + {"TIOCCBRK", Const, 0, ""}, + {"TIOCCDTR", Const, 0, ""}, + {"TIOCCONS", Const, 0, ""}, + {"TIOCDCDTIMESTAMP", Const, 0, ""}, + {"TIOCDRAIN", Const, 0, ""}, + {"TIOCDSIMICROCODE", Const, 0, ""}, + {"TIOCEXCL", Const, 0, ""}, + {"TIOCEXT", Const, 0, ""}, + {"TIOCFLAG_CDTRCTS", Const, 1, ""}, + {"TIOCFLAG_CLOCAL", Const, 1, ""}, + {"TIOCFLAG_CRTSCTS", Const, 1, ""}, + {"TIOCFLAG_MDMBUF", Const, 1, ""}, + {"TIOCFLAG_PPS", Const, 1, ""}, + {"TIOCFLAG_SOFTCAR", Const, 1, ""}, + {"TIOCFLUSH", Const, 0, ""}, + {"TIOCGDEV", Const, 0, ""}, + {"TIOCGDRAINWAIT", Const, 0, ""}, + {"TIOCGETA", Const, 0, ""}, + {"TIOCGETD", Const, 0, ""}, + {"TIOCGFLAGS", Const, 1, ""}, + {"TIOCGICOUNT", Const, 0, ""}, + {"TIOCGLCKTRMIOS", Const, 0, ""}, + {"TIOCGLINED", Const, 1, ""}, + {"TIOCGPGRP", Const, 0, ""}, + {"TIOCGPTN", Const, 0, ""}, + {"TIOCGQSIZE", Const, 1, ""}, + {"TIOCGRANTPT", Const, 1, ""}, + {"TIOCGRS485", Const, 0, ""}, + {"TIOCGSERIAL", Const, 0, ""}, + {"TIOCGSID", Const, 0, ""}, + {"TIOCGSIZE", Const, 1, ""}, + {"TIOCGSOFTCAR", Const, 0, ""}, + {"TIOCGTSTAMP", Const, 1, ""}, + {"TIOCGWINSZ", Const, 0, ""}, + {"TIOCINQ", Const, 0, ""}, + {"TIOCIXOFF", Const, 0, ""}, + {"TIOCIXON", Const, 0, ""}, + {"TIOCLINUX", Const, 0, ""}, + {"TIOCMBIC", Const, 0, ""}, + {"TIOCMBIS", Const, 0, ""}, + {"TIOCMGDTRWAIT", Const, 0, ""}, + {"TIOCMGET", Const, 0, ""}, + {"TIOCMIWAIT", Const, 0, ""}, + {"TIOCMODG", Const, 0, ""}, + {"TIOCMODS", Const, 0, ""}, + {"TIOCMSDTRWAIT", Const, 0, ""}, + {"TIOCMSET", Const, 0, ""}, + {"TIOCM_CAR", Const, 0, ""}, + {"TIOCM_CD", Const, 0, ""}, + {"TIOCM_CTS", Const, 0, ""}, + {"TIOCM_DCD", Const, 0, ""}, + {"TIOCM_DSR", Const, 0, ""}, + {"TIOCM_DTR", Const, 0, ""}, + {"TIOCM_LE", Const, 0, ""}, + {"TIOCM_RI", Const, 0, ""}, + {"TIOCM_RNG", Const, 0, ""}, + {"TIOCM_RTS", Const, 0, ""}, + {"TIOCM_SR", Const, 0, ""}, + {"TIOCM_ST", Const, 0, ""}, + {"TIOCNOTTY", Const, 0, ""}, + {"TIOCNXCL", Const, 0, ""}, + {"TIOCOUTQ", Const, 0, ""}, + {"TIOCPKT", Const, 0, ""}, + {"TIOCPKT_DATA", Const, 0, ""}, + {"TIOCPKT_DOSTOP", Const, 0, ""}, + {"TIOCPKT_FLUSHREAD", Const, 0, ""}, + {"TIOCPKT_FLUSHWRITE", Const, 0, ""}, + {"TIOCPKT_IOCTL", Const, 0, ""}, + {"TIOCPKT_NOSTOP", Const, 0, ""}, + {"TIOCPKT_START", Const, 0, ""}, + {"TIOCPKT_STOP", Const, 0, ""}, + {"TIOCPTMASTER", Const, 0, ""}, + {"TIOCPTMGET", Const, 1, ""}, + {"TIOCPTSNAME", Const, 1, ""}, + {"TIOCPTYGNAME", Const, 0, ""}, + {"TIOCPTYGRANT", Const, 0, ""}, + {"TIOCPTYUNLK", Const, 0, ""}, + {"TIOCRCVFRAME", Const, 1, ""}, + {"TIOCREMOTE", Const, 0, ""}, + {"TIOCSBRK", Const, 0, ""}, + {"TIOCSCONS", Const, 0, ""}, + {"TIOCSCTTY", Const, 0, ""}, + {"TIOCSDRAINWAIT", Const, 0, ""}, + {"TIOCSDTR", Const, 0, ""}, + {"TIOCSERCONFIG", Const, 0, ""}, + {"TIOCSERGETLSR", Const, 0, ""}, + {"TIOCSERGETMULTI", Const, 0, ""}, + {"TIOCSERGSTRUCT", Const, 0, ""}, + {"TIOCSERGWILD", Const, 0, ""}, + {"TIOCSERSETMULTI", Const, 0, ""}, + {"TIOCSERSWILD", Const, 0, ""}, + {"TIOCSER_TEMT", Const, 0, ""}, + {"TIOCSETA", Const, 0, ""}, + {"TIOCSETAF", Const, 0, ""}, + {"TIOCSETAW", Const, 0, ""}, + {"TIOCSETD", Const, 0, ""}, + {"TIOCSFLAGS", Const, 1, ""}, + {"TIOCSIG", Const, 0, ""}, + {"TIOCSLCKTRMIOS", Const, 0, ""}, + {"TIOCSLINED", Const, 1, ""}, + {"TIOCSPGRP", Const, 0, ""}, + {"TIOCSPTLCK", Const, 0, ""}, + {"TIOCSQSIZE", Const, 1, ""}, + {"TIOCSRS485", Const, 0, ""}, + {"TIOCSSERIAL", Const, 0, ""}, + {"TIOCSSIZE", Const, 1, ""}, + {"TIOCSSOFTCAR", Const, 0, ""}, + {"TIOCSTART", Const, 0, ""}, + {"TIOCSTAT", Const, 0, ""}, + {"TIOCSTI", Const, 0, ""}, + {"TIOCSTOP", Const, 0, ""}, + {"TIOCSTSTAMP", Const, 1, ""}, + {"TIOCSWINSZ", Const, 0, ""}, + {"TIOCTIMESTAMP", Const, 0, ""}, + {"TIOCUCNTL", Const, 0, ""}, + {"TIOCVHANGUP", Const, 0, ""}, + {"TIOCXMTFRAME", Const, 1, ""}, + {"TOKEN_ADJUST_DEFAULT", Const, 0, ""}, + {"TOKEN_ADJUST_GROUPS", Const, 0, ""}, + {"TOKEN_ADJUST_PRIVILEGES", Const, 0, ""}, + {"TOKEN_ADJUST_SESSIONID", Const, 11, ""}, + {"TOKEN_ALL_ACCESS", Const, 0, ""}, + {"TOKEN_ASSIGN_PRIMARY", Const, 0, ""}, + {"TOKEN_DUPLICATE", Const, 0, ""}, + {"TOKEN_EXECUTE", Const, 0, ""}, + {"TOKEN_IMPERSONATE", Const, 0, ""}, + {"TOKEN_QUERY", Const, 0, ""}, + {"TOKEN_QUERY_SOURCE", Const, 0, ""}, + {"TOKEN_READ", Const, 0, ""}, + {"TOKEN_WRITE", Const, 0, ""}, + {"TOSTOP", Const, 0, ""}, + {"TRUNCATE_EXISTING", Const, 0, ""}, + {"TUNATTACHFILTER", Const, 0, ""}, + {"TUNDETACHFILTER", Const, 0, ""}, + {"TUNGETFEATURES", Const, 0, ""}, + {"TUNGETIFF", Const, 0, ""}, + {"TUNGETSNDBUF", Const, 0, ""}, + {"TUNGETVNETHDRSZ", Const, 0, ""}, + {"TUNSETDEBUG", Const, 0, ""}, + {"TUNSETGROUP", Const, 0, ""}, + {"TUNSETIFF", Const, 0, ""}, + {"TUNSETLINK", Const, 0, ""}, + {"TUNSETNOCSUM", Const, 0, ""}, + {"TUNSETOFFLOAD", Const, 0, ""}, + {"TUNSETOWNER", Const, 0, ""}, + {"TUNSETPERSIST", Const, 0, ""}, + {"TUNSETSNDBUF", Const, 0, ""}, + {"TUNSETTXFILTER", Const, 0, ""}, + {"TUNSETVNETHDRSZ", Const, 0, ""}, + {"Tee", Func, 0, "func(rfd int, wfd int, len int, flags int) (n int64, err error)"}, + {"TerminateProcess", Func, 0, ""}, + {"Termios", Type, 0, ""}, + {"Termios.Cc", Field, 0, ""}, + {"Termios.Cflag", Field, 0, ""}, + {"Termios.Iflag", Field, 0, ""}, + {"Termios.Ispeed", Field, 0, ""}, + {"Termios.Lflag", Field, 0, ""}, + {"Termios.Line", Field, 0, ""}, + {"Termios.Oflag", Field, 0, ""}, + {"Termios.Ospeed", Field, 0, ""}, + {"Termios.Pad_cgo_0", Field, 0, ""}, + {"Tgkill", Func, 0, "func(tgid int, tid int, sig Signal) (err error)"}, + {"Time", Func, 0, "func(t *Time_t) (tt Time_t, err error)"}, + {"Time_t", Type, 0, ""}, + {"Times", Func, 0, "func(tms *Tms) (ticks uintptr, err error)"}, + {"Timespec", Type, 0, ""}, + {"Timespec.Nsec", Field, 0, ""}, + {"Timespec.Pad_cgo_0", Field, 2, ""}, + {"Timespec.Sec", Field, 0, ""}, + {"TimespecToNsec", Func, 0, "func(ts Timespec) int64"}, + {"Timeval", Type, 0, ""}, + {"Timeval.Pad_cgo_0", Field, 0, ""}, + {"Timeval.Sec", Field, 0, ""}, + {"Timeval.Usec", Field, 0, ""}, + {"Timeval32", Type, 0, ""}, + {"Timeval32.Sec", Field, 0, ""}, + {"Timeval32.Usec", Field, 0, ""}, + {"TimevalToNsec", Func, 0, "func(tv Timeval) int64"}, + {"Timex", Type, 0, ""}, + {"Timex.Calcnt", Field, 0, ""}, + {"Timex.Constant", Field, 0, ""}, + {"Timex.Errcnt", Field, 0, ""}, + {"Timex.Esterror", Field, 0, ""}, + {"Timex.Freq", Field, 0, ""}, + {"Timex.Jitcnt", Field, 0, ""}, + {"Timex.Jitter", Field, 0, ""}, + {"Timex.Maxerror", Field, 0, ""}, + {"Timex.Modes", Field, 0, ""}, + {"Timex.Offset", Field, 0, ""}, + {"Timex.Pad_cgo_0", Field, 0, ""}, + {"Timex.Pad_cgo_1", Field, 0, ""}, + {"Timex.Pad_cgo_2", Field, 0, ""}, + {"Timex.Pad_cgo_3", Field, 0, ""}, + {"Timex.Ppsfreq", Field, 0, ""}, + {"Timex.Precision", Field, 0, ""}, + {"Timex.Shift", Field, 0, ""}, + {"Timex.Stabil", Field, 0, ""}, + {"Timex.Status", Field, 0, ""}, + {"Timex.Stbcnt", Field, 0, ""}, + {"Timex.Tai", Field, 0, ""}, + {"Timex.Tick", Field, 0, ""}, + {"Timex.Time", Field, 0, ""}, + {"Timex.Tolerance", Field, 0, ""}, + {"Timezoneinformation", Type, 0, ""}, + {"Timezoneinformation.Bias", Field, 0, ""}, + {"Timezoneinformation.DaylightBias", Field, 0, ""}, + {"Timezoneinformation.DaylightDate", Field, 0, ""}, + {"Timezoneinformation.DaylightName", Field, 0, ""}, + {"Timezoneinformation.StandardBias", Field, 0, ""}, + {"Timezoneinformation.StandardDate", Field, 0, ""}, + {"Timezoneinformation.StandardName", Field, 0, ""}, + {"Tms", Type, 0, ""}, + {"Tms.Cstime", Field, 0, ""}, + {"Tms.Cutime", Field, 0, ""}, + {"Tms.Stime", Field, 0, ""}, + {"Tms.Utime", Field, 0, ""}, + {"Token", Type, 0, ""}, + {"TokenAccessInformation", Const, 0, ""}, + {"TokenAuditPolicy", Const, 0, ""}, + {"TokenDefaultDacl", Const, 0, ""}, + {"TokenElevation", Const, 0, ""}, + {"TokenElevationType", Const, 0, ""}, + {"TokenGroups", Const, 0, ""}, + {"TokenGroupsAndPrivileges", Const, 0, ""}, + {"TokenHasRestrictions", Const, 0, ""}, + {"TokenImpersonationLevel", Const, 0, ""}, + {"TokenIntegrityLevel", Const, 0, ""}, + {"TokenLinkedToken", Const, 0, ""}, + {"TokenLogonSid", Const, 0, ""}, + {"TokenMandatoryPolicy", Const, 0, ""}, + {"TokenOrigin", Const, 0, ""}, + {"TokenOwner", Const, 0, ""}, + {"TokenPrimaryGroup", Const, 0, ""}, + {"TokenPrivileges", Const, 0, ""}, + {"TokenRestrictedSids", Const, 0, ""}, + {"TokenSandBoxInert", Const, 0, ""}, + {"TokenSessionId", Const, 0, ""}, + {"TokenSessionReference", Const, 0, ""}, + {"TokenSource", Const, 0, ""}, + {"TokenStatistics", Const, 0, ""}, + {"TokenType", Const, 0, ""}, + {"TokenUIAccess", Const, 0, ""}, + {"TokenUser", Const, 0, ""}, + {"TokenVirtualizationAllowed", Const, 0, ""}, + {"TokenVirtualizationEnabled", Const, 0, ""}, + {"Tokenprimarygroup", Type, 0, ""}, + {"Tokenprimarygroup.PrimaryGroup", Field, 0, ""}, + {"Tokenuser", Type, 0, ""}, + {"Tokenuser.User", Field, 0, ""}, + {"TranslateAccountName", Func, 0, ""}, + {"TranslateName", Func, 0, ""}, + {"TransmitFile", Func, 0, ""}, + {"TransmitFileBuffers", Type, 0, ""}, + {"TransmitFileBuffers.Head", Field, 0, ""}, + {"TransmitFileBuffers.HeadLength", Field, 0, ""}, + {"TransmitFileBuffers.Tail", Field, 0, ""}, + {"TransmitFileBuffers.TailLength", Field, 0, ""}, + {"Truncate", Func, 0, "func(path string, length int64) (err error)"}, + {"UNIX_PATH_MAX", Const, 12, ""}, + {"USAGE_MATCH_TYPE_AND", Const, 0, ""}, + {"USAGE_MATCH_TYPE_OR", Const, 0, ""}, + {"UTF16FromString", Func, 1, ""}, + {"UTF16PtrFromString", Func, 1, ""}, + {"UTF16ToString", Func, 0, ""}, + {"Ucred", Type, 0, ""}, + {"Ucred.Gid", Field, 0, ""}, + {"Ucred.Pid", Field, 0, ""}, + {"Ucred.Uid", Field, 0, ""}, + {"Umask", Func, 0, "func(mask int) (oldmask int)"}, + {"Uname", Func, 0, "func(buf *Utsname) (err error)"}, + {"Undelete", Func, 0, ""}, + {"UnixCredentials", Func, 0, "func(ucred *Ucred) []byte"}, + {"UnixRights", Func, 0, "func(fds ...int) []byte"}, + {"Unlink", Func, 0, "func(path string) error"}, + {"Unlinkat", Func, 0, "func(dirfd int, path string) error"}, + {"UnmapViewOfFile", Func, 0, ""}, + {"Unmount", Func, 0, "func(target string, flags int) (err error)"}, + {"Unsetenv", Func, 4, "func(key string) error"}, + {"Unshare", Func, 0, "func(flags int) (err error)"}, + {"UserInfo10", Type, 0, ""}, + {"UserInfo10.Comment", Field, 0, ""}, + {"UserInfo10.FullName", Field, 0, ""}, + {"UserInfo10.Name", Field, 0, ""}, + {"UserInfo10.UsrComment", Field, 0, ""}, + {"Ustat", Func, 0, "func(dev int, ubuf *Ustat_t) (err error)"}, + {"Ustat_t", Type, 0, ""}, + {"Ustat_t.Fname", Field, 0, ""}, + {"Ustat_t.Fpack", Field, 0, ""}, + {"Ustat_t.Pad_cgo_0", Field, 0, ""}, + {"Ustat_t.Pad_cgo_1", Field, 0, ""}, + {"Ustat_t.Tfree", Field, 0, ""}, + {"Ustat_t.Tinode", Field, 0, ""}, + {"Utimbuf", Type, 0, ""}, + {"Utimbuf.Actime", Field, 0, ""}, + {"Utimbuf.Modtime", Field, 0, ""}, + {"Utime", Func, 0, "func(path string, buf *Utimbuf) (err error)"}, + {"Utimes", Func, 0, "func(path string, tv []Timeval) (err error)"}, + {"UtimesNano", Func, 1, "func(path string, ts []Timespec) (err error)"}, + {"Utsname", Type, 0, ""}, + {"Utsname.Domainname", Field, 0, ""}, + {"Utsname.Machine", Field, 0, ""}, + {"Utsname.Nodename", Field, 0, ""}, + {"Utsname.Release", Field, 0, ""}, + {"Utsname.Sysname", Field, 0, ""}, + {"Utsname.Version", Field, 0, ""}, + {"VDISCARD", Const, 0, ""}, + {"VDSUSP", Const, 1, ""}, + {"VEOF", Const, 0, ""}, + {"VEOL", Const, 0, ""}, + {"VEOL2", Const, 0, ""}, + {"VERASE", Const, 0, ""}, + {"VERASE2", Const, 1, ""}, + {"VINTR", Const, 0, ""}, + {"VKILL", Const, 0, ""}, + {"VLNEXT", Const, 0, ""}, + {"VMIN", Const, 0, ""}, + {"VQUIT", Const, 0, ""}, + {"VREPRINT", Const, 0, ""}, + {"VSTART", Const, 0, ""}, + {"VSTATUS", Const, 1, ""}, + {"VSTOP", Const, 0, ""}, + {"VSUSP", Const, 0, ""}, + {"VSWTC", Const, 0, ""}, + {"VT0", Const, 1, ""}, + {"VT1", Const, 1, ""}, + {"VTDLY", Const, 1, ""}, + {"VTIME", Const, 0, ""}, + {"VWERASE", Const, 0, ""}, + {"VirtualLock", Func, 0, ""}, + {"VirtualUnlock", Func, 0, ""}, + {"WAIT_ABANDONED", Const, 0, ""}, + {"WAIT_FAILED", Const, 0, ""}, + {"WAIT_OBJECT_0", Const, 0, ""}, + {"WAIT_TIMEOUT", Const, 0, ""}, + {"WALL", Const, 0, ""}, + {"WALLSIG", Const, 1, ""}, + {"WALTSIG", Const, 1, ""}, + {"WCLONE", Const, 0, ""}, + {"WCONTINUED", Const, 0, ""}, + {"WCOREFLAG", Const, 0, ""}, + {"WEXITED", Const, 0, ""}, + {"WLINUXCLONE", Const, 0, ""}, + {"WNOHANG", Const, 0, ""}, + {"WNOTHREAD", Const, 0, ""}, + {"WNOWAIT", Const, 0, ""}, + {"WNOZOMBIE", Const, 1, ""}, + {"WOPTSCHECKED", Const, 1, ""}, + {"WORDSIZE", Const, 0, ""}, + {"WSABuf", Type, 0, ""}, + {"WSABuf.Buf", Field, 0, ""}, + {"WSABuf.Len", Field, 0, ""}, + {"WSACleanup", Func, 0, ""}, + {"WSADESCRIPTION_LEN", Const, 0, ""}, + {"WSAData", Type, 0, ""}, + {"WSAData.Description", Field, 0, ""}, + {"WSAData.HighVersion", Field, 0, ""}, + {"WSAData.MaxSockets", Field, 0, ""}, + {"WSAData.MaxUdpDg", Field, 0, ""}, + {"WSAData.SystemStatus", Field, 0, ""}, + {"WSAData.VendorInfo", Field, 0, ""}, + {"WSAData.Version", Field, 0, ""}, + {"WSAEACCES", Const, 2, ""}, + {"WSAECONNABORTED", Const, 9, ""}, + {"WSAECONNRESET", Const, 3, ""}, + {"WSAENOPROTOOPT", Const, 23, ""}, + {"WSAEnumProtocols", Func, 2, ""}, + {"WSAID_CONNECTEX", Var, 1, ""}, + {"WSAIoctl", Func, 0, ""}, + {"WSAPROTOCOL_LEN", Const, 2, ""}, + {"WSAProtocolChain", Type, 2, ""}, + {"WSAProtocolChain.ChainEntries", Field, 2, ""}, + {"WSAProtocolChain.ChainLen", Field, 2, ""}, + {"WSAProtocolInfo", Type, 2, ""}, + {"WSAProtocolInfo.AddressFamily", Field, 2, ""}, + {"WSAProtocolInfo.CatalogEntryId", Field, 2, ""}, + {"WSAProtocolInfo.MaxSockAddr", Field, 2, ""}, + {"WSAProtocolInfo.MessageSize", Field, 2, ""}, + {"WSAProtocolInfo.MinSockAddr", Field, 2, ""}, + {"WSAProtocolInfo.NetworkByteOrder", Field, 2, ""}, + {"WSAProtocolInfo.Protocol", Field, 2, ""}, + {"WSAProtocolInfo.ProtocolChain", Field, 2, ""}, + {"WSAProtocolInfo.ProtocolMaxOffset", Field, 2, ""}, + {"WSAProtocolInfo.ProtocolName", Field, 2, ""}, + {"WSAProtocolInfo.ProviderFlags", Field, 2, ""}, + {"WSAProtocolInfo.ProviderId", Field, 2, ""}, + {"WSAProtocolInfo.ProviderReserved", Field, 2, ""}, + {"WSAProtocolInfo.SecurityScheme", Field, 2, ""}, + {"WSAProtocolInfo.ServiceFlags1", Field, 2, ""}, + {"WSAProtocolInfo.ServiceFlags2", Field, 2, ""}, + {"WSAProtocolInfo.ServiceFlags3", Field, 2, ""}, + {"WSAProtocolInfo.ServiceFlags4", Field, 2, ""}, + {"WSAProtocolInfo.SocketType", Field, 2, ""}, + {"WSAProtocolInfo.Version", Field, 2, ""}, + {"WSARecv", Func, 0, ""}, + {"WSARecvFrom", Func, 0, ""}, + {"WSASYS_STATUS_LEN", Const, 0, ""}, + {"WSASend", Func, 0, ""}, + {"WSASendTo", Func, 0, ""}, + {"WSASendto", Func, 0, ""}, + {"WSAStartup", Func, 0, ""}, + {"WSTOPPED", Const, 0, ""}, + {"WTRAPPED", Const, 1, ""}, + {"WUNTRACED", Const, 0, ""}, + {"Wait4", Func, 0, "func(pid int, wstatus *WaitStatus, options int, rusage *Rusage) (wpid int, err error)"}, + {"WaitForSingleObject", Func, 0, ""}, + {"WaitStatus", Type, 0, ""}, + {"WaitStatus.ExitCode", Field, 0, ""}, + {"Win32FileAttributeData", Type, 0, ""}, + {"Win32FileAttributeData.CreationTime", Field, 0, ""}, + {"Win32FileAttributeData.FileAttributes", Field, 0, ""}, + {"Win32FileAttributeData.FileSizeHigh", Field, 0, ""}, + {"Win32FileAttributeData.FileSizeLow", Field, 0, ""}, + {"Win32FileAttributeData.LastAccessTime", Field, 0, ""}, + {"Win32FileAttributeData.LastWriteTime", Field, 0, ""}, + {"Win32finddata", Type, 0, ""}, + {"Win32finddata.AlternateFileName", Field, 0, ""}, + {"Win32finddata.CreationTime", Field, 0, ""}, + {"Win32finddata.FileAttributes", Field, 0, ""}, + {"Win32finddata.FileName", Field, 0, ""}, + {"Win32finddata.FileSizeHigh", Field, 0, ""}, + {"Win32finddata.FileSizeLow", Field, 0, ""}, + {"Win32finddata.LastAccessTime", Field, 0, ""}, + {"Win32finddata.LastWriteTime", Field, 0, ""}, + {"Win32finddata.Reserved0", Field, 0, ""}, + {"Win32finddata.Reserved1", Field, 0, ""}, + {"Write", Func, 0, "func(fd int, p []byte) (n int, err error)"}, + {"WriteConsole", Func, 1, ""}, + {"WriteFile", Func, 0, ""}, + {"X509_ASN_ENCODING", Const, 0, ""}, + {"XCASE", Const, 0, ""}, + {"XP1_CONNECTIONLESS", Const, 2, ""}, + {"XP1_CONNECT_DATA", Const, 2, ""}, + {"XP1_DISCONNECT_DATA", Const, 2, ""}, + {"XP1_EXPEDITED_DATA", Const, 2, ""}, + {"XP1_GRACEFUL_CLOSE", Const, 2, ""}, + {"XP1_GUARANTEED_DELIVERY", Const, 2, ""}, + {"XP1_GUARANTEED_ORDER", Const, 2, ""}, + {"XP1_IFS_HANDLES", Const, 2, ""}, + {"XP1_MESSAGE_ORIENTED", Const, 2, ""}, + {"XP1_MULTIPOINT_CONTROL_PLANE", Const, 2, ""}, + {"XP1_MULTIPOINT_DATA_PLANE", Const, 2, ""}, + {"XP1_PARTIAL_MESSAGE", Const, 2, ""}, + {"XP1_PSEUDO_STREAM", Const, 2, ""}, + {"XP1_QOS_SUPPORTED", Const, 2, ""}, + {"XP1_SAN_SUPPORT_SDP", Const, 2, ""}, + {"XP1_SUPPORT_BROADCAST", Const, 2, ""}, + {"XP1_SUPPORT_MULTIPOINT", Const, 2, ""}, + {"XP1_UNI_RECV", Const, 2, ""}, + {"XP1_UNI_SEND", Const, 2, ""}, }, "syscall/js": { - {"CopyBytesToGo", Func, 0}, - {"CopyBytesToJS", Func, 0}, - {"Error", Type, 0}, - {"Func", Type, 0}, - {"FuncOf", Func, 0}, - {"Global", Func, 0}, - {"Null", Func, 0}, - {"Type", Type, 0}, - {"TypeBoolean", Const, 0}, - {"TypeFunction", Const, 0}, - {"TypeNull", Const, 0}, - {"TypeNumber", Const, 0}, - {"TypeObject", Const, 0}, - {"TypeString", Const, 0}, - {"TypeSymbol", Const, 0}, - {"TypeUndefined", Const, 0}, - {"Undefined", Func, 0}, - {"Value", Type, 0}, - {"ValueError", Type, 0}, - {"ValueOf", Func, 0}, + {"CopyBytesToGo", Func, 0, ""}, + {"CopyBytesToJS", Func, 0, ""}, + {"Error", Type, 0, ""}, + {"Func", Type, 0, ""}, + {"FuncOf", Func, 0, ""}, + {"Global", Func, 0, ""}, + {"Null", Func, 0, ""}, + {"Type", Type, 0, ""}, + {"TypeBoolean", Const, 0, ""}, + {"TypeFunction", Const, 0, ""}, + {"TypeNull", Const, 0, ""}, + {"TypeNumber", Const, 0, ""}, + {"TypeObject", Const, 0, ""}, + {"TypeString", Const, 0, ""}, + {"TypeSymbol", Const, 0, ""}, + {"TypeUndefined", Const, 0, ""}, + {"Undefined", Func, 0, ""}, + {"Value", Type, 0, ""}, + {"ValueError", Type, 0, ""}, + {"ValueOf", Func, 0, ""}, }, "testing": { - {"(*B).Chdir", Method, 24}, - {"(*B).Cleanup", Method, 14}, - {"(*B).Context", Method, 24}, - {"(*B).Elapsed", Method, 20}, - {"(*B).Error", Method, 0}, - {"(*B).Errorf", Method, 0}, - {"(*B).Fail", Method, 0}, - {"(*B).FailNow", Method, 0}, - {"(*B).Failed", Method, 0}, - {"(*B).Fatal", Method, 0}, - {"(*B).Fatalf", Method, 0}, - {"(*B).Helper", Method, 9}, - {"(*B).Log", Method, 0}, - {"(*B).Logf", Method, 0}, - {"(*B).Loop", Method, 24}, - {"(*B).Name", Method, 8}, - {"(*B).ReportAllocs", Method, 1}, - {"(*B).ReportMetric", Method, 13}, - {"(*B).ResetTimer", Method, 0}, - {"(*B).Run", Method, 7}, - {"(*B).RunParallel", Method, 3}, - {"(*B).SetBytes", Method, 0}, - {"(*B).SetParallelism", Method, 3}, - {"(*B).Setenv", Method, 17}, - {"(*B).Skip", Method, 1}, - {"(*B).SkipNow", Method, 1}, - {"(*B).Skipf", Method, 1}, - {"(*B).Skipped", Method, 1}, - {"(*B).StartTimer", Method, 0}, - {"(*B).StopTimer", Method, 0}, - {"(*B).TempDir", Method, 15}, - {"(*F).Add", Method, 18}, - {"(*F).Chdir", Method, 24}, - {"(*F).Cleanup", Method, 18}, - {"(*F).Context", Method, 24}, - {"(*F).Error", Method, 18}, - {"(*F).Errorf", Method, 18}, - {"(*F).Fail", Method, 18}, - {"(*F).FailNow", Method, 18}, - {"(*F).Failed", Method, 18}, - {"(*F).Fatal", Method, 18}, - {"(*F).Fatalf", Method, 18}, - {"(*F).Fuzz", Method, 18}, - {"(*F).Helper", Method, 18}, - {"(*F).Log", Method, 18}, - {"(*F).Logf", Method, 18}, - {"(*F).Name", Method, 18}, - {"(*F).Setenv", Method, 18}, - {"(*F).Skip", Method, 18}, - {"(*F).SkipNow", Method, 18}, - {"(*F).Skipf", Method, 18}, - {"(*F).Skipped", Method, 18}, - {"(*F).TempDir", Method, 18}, - {"(*M).Run", Method, 4}, - {"(*PB).Next", Method, 3}, - {"(*T).Chdir", Method, 24}, - {"(*T).Cleanup", Method, 14}, - {"(*T).Context", Method, 24}, - {"(*T).Deadline", Method, 15}, - {"(*T).Error", Method, 0}, - {"(*T).Errorf", Method, 0}, - {"(*T).Fail", Method, 0}, - {"(*T).FailNow", Method, 0}, - {"(*T).Failed", Method, 0}, - {"(*T).Fatal", Method, 0}, - {"(*T).Fatalf", Method, 0}, - {"(*T).Helper", Method, 9}, - {"(*T).Log", Method, 0}, - {"(*T).Logf", Method, 0}, - {"(*T).Name", Method, 8}, - {"(*T).Parallel", Method, 0}, - {"(*T).Run", Method, 7}, - {"(*T).Setenv", Method, 17}, - {"(*T).Skip", Method, 1}, - {"(*T).SkipNow", Method, 1}, - {"(*T).Skipf", Method, 1}, - {"(*T).Skipped", Method, 1}, - {"(*T).TempDir", Method, 15}, - {"(BenchmarkResult).AllocedBytesPerOp", Method, 1}, - {"(BenchmarkResult).AllocsPerOp", Method, 1}, - {"(BenchmarkResult).MemString", Method, 1}, - {"(BenchmarkResult).NsPerOp", Method, 0}, - {"(BenchmarkResult).String", Method, 0}, - {"AllocsPerRun", Func, 1}, - {"B", Type, 0}, - {"B.N", Field, 0}, - {"Benchmark", Func, 0}, - {"BenchmarkResult", Type, 0}, - {"BenchmarkResult.Bytes", Field, 0}, - {"BenchmarkResult.Extra", Field, 13}, - {"BenchmarkResult.MemAllocs", Field, 1}, - {"BenchmarkResult.MemBytes", Field, 1}, - {"BenchmarkResult.N", Field, 0}, - {"BenchmarkResult.T", Field, 0}, - {"Cover", Type, 2}, - {"Cover.Blocks", Field, 2}, - {"Cover.Counters", Field, 2}, - {"Cover.CoveredPackages", Field, 2}, - {"Cover.Mode", Field, 2}, - {"CoverBlock", Type, 2}, - {"CoverBlock.Col0", Field, 2}, - {"CoverBlock.Col1", Field, 2}, - {"CoverBlock.Line0", Field, 2}, - {"CoverBlock.Line1", Field, 2}, - {"CoverBlock.Stmts", Field, 2}, - {"CoverMode", Func, 8}, - {"Coverage", Func, 4}, - {"F", Type, 18}, - {"Init", Func, 13}, - {"InternalBenchmark", Type, 0}, - {"InternalBenchmark.F", Field, 0}, - {"InternalBenchmark.Name", Field, 0}, - {"InternalExample", Type, 0}, - {"InternalExample.F", Field, 0}, - {"InternalExample.Name", Field, 0}, - {"InternalExample.Output", Field, 0}, - {"InternalExample.Unordered", Field, 7}, - {"InternalFuzzTarget", Type, 18}, - {"InternalFuzzTarget.Fn", Field, 18}, - {"InternalFuzzTarget.Name", Field, 18}, - {"InternalTest", Type, 0}, - {"InternalTest.F", Field, 0}, - {"InternalTest.Name", Field, 0}, - {"M", Type, 4}, - {"Main", Func, 0}, - {"MainStart", Func, 4}, - {"PB", Type, 3}, - {"RegisterCover", Func, 2}, - {"RunBenchmarks", Func, 0}, - {"RunExamples", Func, 0}, - {"RunTests", Func, 0}, - {"Short", Func, 0}, - {"T", Type, 0}, - {"TB", Type, 2}, - {"Testing", Func, 21}, - {"Verbose", Func, 1}, + {"(*B).Chdir", Method, 24, ""}, + {"(*B).Cleanup", Method, 14, ""}, + {"(*B).Context", Method, 24, ""}, + {"(*B).Elapsed", Method, 20, ""}, + {"(*B).Error", Method, 0, ""}, + {"(*B).Errorf", Method, 0, ""}, + {"(*B).Fail", Method, 0, ""}, + {"(*B).FailNow", Method, 0, ""}, + {"(*B).Failed", Method, 0, ""}, + {"(*B).Fatal", Method, 0, ""}, + {"(*B).Fatalf", Method, 0, ""}, + {"(*B).Helper", Method, 9, ""}, + {"(*B).Log", Method, 0, ""}, + {"(*B).Logf", Method, 0, ""}, + {"(*B).Loop", Method, 24, ""}, + {"(*B).Name", Method, 8, ""}, + {"(*B).ReportAllocs", Method, 1, ""}, + {"(*B).ReportMetric", Method, 13, ""}, + {"(*B).ResetTimer", Method, 0, ""}, + {"(*B).Run", Method, 7, ""}, + {"(*B).RunParallel", Method, 3, ""}, + {"(*B).SetBytes", Method, 0, ""}, + {"(*B).SetParallelism", Method, 3, ""}, + {"(*B).Setenv", Method, 17, ""}, + {"(*B).Skip", Method, 1, ""}, + {"(*B).SkipNow", Method, 1, ""}, + {"(*B).Skipf", Method, 1, ""}, + {"(*B).Skipped", Method, 1, ""}, + {"(*B).StartTimer", Method, 0, ""}, + {"(*B).StopTimer", Method, 0, ""}, + {"(*B).TempDir", Method, 15, ""}, + {"(*F).Add", Method, 18, ""}, + {"(*F).Chdir", Method, 24, ""}, + {"(*F).Cleanup", Method, 18, ""}, + {"(*F).Context", Method, 24, ""}, + {"(*F).Error", Method, 18, ""}, + {"(*F).Errorf", Method, 18, ""}, + {"(*F).Fail", Method, 18, ""}, + {"(*F).FailNow", Method, 18, ""}, + {"(*F).Failed", Method, 18, ""}, + {"(*F).Fatal", Method, 18, ""}, + {"(*F).Fatalf", Method, 18, ""}, + {"(*F).Fuzz", Method, 18, ""}, + {"(*F).Helper", Method, 18, ""}, + {"(*F).Log", Method, 18, ""}, + {"(*F).Logf", Method, 18, ""}, + {"(*F).Name", Method, 18, ""}, + {"(*F).Setenv", Method, 18, ""}, + {"(*F).Skip", Method, 18, ""}, + {"(*F).SkipNow", Method, 18, ""}, + {"(*F).Skipf", Method, 18, ""}, + {"(*F).Skipped", Method, 18, ""}, + {"(*F).TempDir", Method, 18, ""}, + {"(*M).Run", Method, 4, ""}, + {"(*PB).Next", Method, 3, ""}, + {"(*T).Chdir", Method, 24, ""}, + {"(*T).Cleanup", Method, 14, ""}, + {"(*T).Context", Method, 24, ""}, + {"(*T).Deadline", Method, 15, ""}, + {"(*T).Error", Method, 0, ""}, + {"(*T).Errorf", Method, 0, ""}, + {"(*T).Fail", Method, 0, ""}, + {"(*T).FailNow", Method, 0, ""}, + {"(*T).Failed", Method, 0, ""}, + {"(*T).Fatal", Method, 0, ""}, + {"(*T).Fatalf", Method, 0, ""}, + {"(*T).Helper", Method, 9, ""}, + {"(*T).Log", Method, 0, ""}, + {"(*T).Logf", Method, 0, ""}, + {"(*T).Name", Method, 8, ""}, + {"(*T).Parallel", Method, 0, ""}, + {"(*T).Run", Method, 7, ""}, + {"(*T).Setenv", Method, 17, ""}, + {"(*T).Skip", Method, 1, ""}, + {"(*T).SkipNow", Method, 1, ""}, + {"(*T).Skipf", Method, 1, ""}, + {"(*T).Skipped", Method, 1, ""}, + {"(*T).TempDir", Method, 15, ""}, + {"(BenchmarkResult).AllocedBytesPerOp", Method, 1, ""}, + {"(BenchmarkResult).AllocsPerOp", Method, 1, ""}, + {"(BenchmarkResult).MemString", Method, 1, ""}, + {"(BenchmarkResult).NsPerOp", Method, 0, ""}, + {"(BenchmarkResult).String", Method, 0, ""}, + {"AllocsPerRun", Func, 1, "func(runs int, f func()) (avg float64)"}, + {"B", Type, 0, ""}, + {"B.N", Field, 0, ""}, + {"Benchmark", Func, 0, "func(f func(b *B)) BenchmarkResult"}, + {"BenchmarkResult", Type, 0, ""}, + {"BenchmarkResult.Bytes", Field, 0, ""}, + {"BenchmarkResult.Extra", Field, 13, ""}, + {"BenchmarkResult.MemAllocs", Field, 1, ""}, + {"BenchmarkResult.MemBytes", Field, 1, ""}, + {"BenchmarkResult.N", Field, 0, ""}, + {"BenchmarkResult.T", Field, 0, ""}, + {"Cover", Type, 2, ""}, + {"Cover.Blocks", Field, 2, ""}, + {"Cover.Counters", Field, 2, ""}, + {"Cover.CoveredPackages", Field, 2, ""}, + {"Cover.Mode", Field, 2, ""}, + {"CoverBlock", Type, 2, ""}, + {"CoverBlock.Col0", Field, 2, ""}, + {"CoverBlock.Col1", Field, 2, ""}, + {"CoverBlock.Line0", Field, 2, ""}, + {"CoverBlock.Line1", Field, 2, ""}, + {"CoverBlock.Stmts", Field, 2, ""}, + {"CoverMode", Func, 8, "func() string"}, + {"Coverage", Func, 4, "func() float64"}, + {"F", Type, 18, ""}, + {"Init", Func, 13, "func()"}, + {"InternalBenchmark", Type, 0, ""}, + {"InternalBenchmark.F", Field, 0, ""}, + {"InternalBenchmark.Name", Field, 0, ""}, + {"InternalExample", Type, 0, ""}, + {"InternalExample.F", Field, 0, ""}, + {"InternalExample.Name", Field, 0, ""}, + {"InternalExample.Output", Field, 0, ""}, + {"InternalExample.Unordered", Field, 7, ""}, + {"InternalFuzzTarget", Type, 18, ""}, + {"InternalFuzzTarget.Fn", Field, 18, ""}, + {"InternalFuzzTarget.Name", Field, 18, ""}, + {"InternalTest", Type, 0, ""}, + {"InternalTest.F", Field, 0, ""}, + {"InternalTest.Name", Field, 0, ""}, + {"M", Type, 4, ""}, + {"Main", Func, 0, "func(matchString func(pat string, str string) (bool, error), tests []InternalTest, benchmarks []InternalBenchmark, examples []InternalExample)"}, + {"MainStart", Func, 4, "func(deps testDeps, tests []InternalTest, benchmarks []InternalBenchmark, fuzzTargets []InternalFuzzTarget, examples []InternalExample) *M"}, + {"PB", Type, 3, ""}, + {"RegisterCover", Func, 2, "func(c Cover)"}, + {"RunBenchmarks", Func, 0, "func(matchString func(pat string, str string) (bool, error), benchmarks []InternalBenchmark)"}, + {"RunExamples", Func, 0, "func(matchString func(pat string, str string) (bool, error), examples []InternalExample) (ok bool)"}, + {"RunTests", Func, 0, "func(matchString func(pat string, str string) (bool, error), tests []InternalTest) (ok bool)"}, + {"Short", Func, 0, "func() bool"}, + {"T", Type, 0, ""}, + {"TB", Type, 2, ""}, + {"Testing", Func, 21, "func() bool"}, + {"Verbose", Func, 1, "func() bool"}, }, "testing/fstest": { - {"(MapFS).Glob", Method, 16}, - {"(MapFS).Lstat", Method, 25}, - {"(MapFS).Open", Method, 16}, - {"(MapFS).ReadDir", Method, 16}, - {"(MapFS).ReadFile", Method, 16}, - {"(MapFS).ReadLink", Method, 25}, - {"(MapFS).Stat", Method, 16}, - {"(MapFS).Sub", Method, 16}, - {"MapFS", Type, 16}, - {"MapFile", Type, 16}, - {"MapFile.Data", Field, 16}, - {"MapFile.ModTime", Field, 16}, - {"MapFile.Mode", Field, 16}, - {"MapFile.Sys", Field, 16}, - {"TestFS", Func, 16}, + {"(MapFS).Glob", Method, 16, ""}, + {"(MapFS).Lstat", Method, 25, ""}, + {"(MapFS).Open", Method, 16, ""}, + {"(MapFS).ReadDir", Method, 16, ""}, + {"(MapFS).ReadFile", Method, 16, ""}, + {"(MapFS).ReadLink", Method, 25, ""}, + {"(MapFS).Stat", Method, 16, ""}, + {"(MapFS).Sub", Method, 16, ""}, + {"MapFS", Type, 16, ""}, + {"MapFile", Type, 16, ""}, + {"MapFile.Data", Field, 16, ""}, + {"MapFile.ModTime", Field, 16, ""}, + {"MapFile.Mode", Field, 16, ""}, + {"MapFile.Sys", Field, 16, ""}, + {"TestFS", Func, 16, "func(fsys fs.FS, expected ...string) error"}, }, "testing/iotest": { - {"DataErrReader", Func, 0}, - {"ErrReader", Func, 16}, - {"ErrTimeout", Var, 0}, - {"HalfReader", Func, 0}, - {"NewReadLogger", Func, 0}, - {"NewWriteLogger", Func, 0}, - {"OneByteReader", Func, 0}, - {"TestReader", Func, 16}, - {"TimeoutReader", Func, 0}, - {"TruncateWriter", Func, 0}, + {"DataErrReader", Func, 0, "func(r io.Reader) io.Reader"}, + {"ErrReader", Func, 16, "func(err error) io.Reader"}, + {"ErrTimeout", Var, 0, ""}, + {"HalfReader", Func, 0, "func(r io.Reader) io.Reader"}, + {"NewReadLogger", Func, 0, "func(prefix string, r io.Reader) io.Reader"}, + {"NewWriteLogger", Func, 0, "func(prefix string, w io.Writer) io.Writer"}, + {"OneByteReader", Func, 0, "func(r io.Reader) io.Reader"}, + {"TestReader", Func, 16, "func(r io.Reader, content []byte) error"}, + {"TimeoutReader", Func, 0, "func(r io.Reader) io.Reader"}, + {"TruncateWriter", Func, 0, "func(w io.Writer, n int64) io.Writer"}, }, "testing/quick": { - {"(*CheckEqualError).Error", Method, 0}, - {"(*CheckError).Error", Method, 0}, - {"(SetupError).Error", Method, 0}, - {"Check", Func, 0}, - {"CheckEqual", Func, 0}, - {"CheckEqualError", Type, 0}, - {"CheckEqualError.CheckError", Field, 0}, - {"CheckEqualError.Out1", Field, 0}, - {"CheckEqualError.Out2", Field, 0}, - {"CheckError", Type, 0}, - {"CheckError.Count", Field, 0}, - {"CheckError.In", Field, 0}, - {"Config", Type, 0}, - {"Config.MaxCount", Field, 0}, - {"Config.MaxCountScale", Field, 0}, - {"Config.Rand", Field, 0}, - {"Config.Values", Field, 0}, - {"Generator", Type, 0}, - {"SetupError", Type, 0}, - {"Value", Func, 0}, + {"(*CheckEqualError).Error", Method, 0, ""}, + {"(*CheckError).Error", Method, 0, ""}, + {"(SetupError).Error", Method, 0, ""}, + {"Check", Func, 0, "func(f any, config *Config) error"}, + {"CheckEqual", Func, 0, "func(f any, g any, config *Config) error"}, + {"CheckEqualError", Type, 0, ""}, + {"CheckEqualError.CheckError", Field, 0, ""}, + {"CheckEqualError.Out1", Field, 0, ""}, + {"CheckEqualError.Out2", Field, 0, ""}, + {"CheckError", Type, 0, ""}, + {"CheckError.Count", Field, 0, ""}, + {"CheckError.In", Field, 0, ""}, + {"Config", Type, 0, ""}, + {"Config.MaxCount", Field, 0, ""}, + {"Config.MaxCountScale", Field, 0, ""}, + {"Config.Rand", Field, 0, ""}, + {"Config.Values", Field, 0, ""}, + {"Generator", Type, 0, ""}, + {"SetupError", Type, 0, ""}, + {"Value", Func, 0, "func(t reflect.Type, rand *rand.Rand) (value reflect.Value, ok bool)"}, }, "testing/slogtest": { - {"Run", Func, 22}, - {"TestHandler", Func, 21}, + {"Run", Func, 22, "func(t *testing.T, newHandler func(*testing.T) slog.Handler, result func(*testing.T) map[string]any)"}, + {"TestHandler", Func, 21, "func(h slog.Handler, results func() []map[string]any) error"}, }, "text/scanner": { - {"(*Position).IsValid", Method, 0}, - {"(*Scanner).Init", Method, 0}, - {"(*Scanner).IsValid", Method, 0}, - {"(*Scanner).Next", Method, 0}, - {"(*Scanner).Peek", Method, 0}, - {"(*Scanner).Pos", Method, 0}, - {"(*Scanner).Scan", Method, 0}, - {"(*Scanner).TokenText", Method, 0}, - {"(Position).String", Method, 0}, - {"(Scanner).String", Method, 0}, - {"Char", Const, 0}, - {"Comment", Const, 0}, - {"EOF", Const, 0}, - {"Float", Const, 0}, - {"GoTokens", Const, 0}, - {"GoWhitespace", Const, 0}, - {"Ident", Const, 0}, - {"Int", Const, 0}, - {"Position", Type, 0}, - {"Position.Column", Field, 0}, - {"Position.Filename", Field, 0}, - {"Position.Line", Field, 0}, - {"Position.Offset", Field, 0}, - {"RawString", Const, 0}, - {"ScanChars", Const, 0}, - {"ScanComments", Const, 0}, - {"ScanFloats", Const, 0}, - {"ScanIdents", Const, 0}, - {"ScanInts", Const, 0}, - {"ScanRawStrings", Const, 0}, - {"ScanStrings", Const, 0}, - {"Scanner", Type, 0}, - {"Scanner.Error", Field, 0}, - {"Scanner.ErrorCount", Field, 0}, - {"Scanner.IsIdentRune", Field, 4}, - {"Scanner.Mode", Field, 0}, - {"Scanner.Position", Field, 0}, - {"Scanner.Whitespace", Field, 0}, - {"SkipComments", Const, 0}, - {"String", Const, 0}, - {"TokenString", Func, 0}, + {"(*Position).IsValid", Method, 0, ""}, + {"(*Scanner).Init", Method, 0, ""}, + {"(*Scanner).IsValid", Method, 0, ""}, + {"(*Scanner).Next", Method, 0, ""}, + {"(*Scanner).Peek", Method, 0, ""}, + {"(*Scanner).Pos", Method, 0, ""}, + {"(*Scanner).Scan", Method, 0, ""}, + {"(*Scanner).TokenText", Method, 0, ""}, + {"(Position).String", Method, 0, ""}, + {"(Scanner).String", Method, 0, ""}, + {"Char", Const, 0, ""}, + {"Comment", Const, 0, ""}, + {"EOF", Const, 0, ""}, + {"Float", Const, 0, ""}, + {"GoTokens", Const, 0, ""}, + {"GoWhitespace", Const, 0, ""}, + {"Ident", Const, 0, ""}, + {"Int", Const, 0, ""}, + {"Position", Type, 0, ""}, + {"Position.Column", Field, 0, ""}, + {"Position.Filename", Field, 0, ""}, + {"Position.Line", Field, 0, ""}, + {"Position.Offset", Field, 0, ""}, + {"RawString", Const, 0, ""}, + {"ScanChars", Const, 0, ""}, + {"ScanComments", Const, 0, ""}, + {"ScanFloats", Const, 0, ""}, + {"ScanIdents", Const, 0, ""}, + {"ScanInts", Const, 0, ""}, + {"ScanRawStrings", Const, 0, ""}, + {"ScanStrings", Const, 0, ""}, + {"Scanner", Type, 0, ""}, + {"Scanner.Error", Field, 0, ""}, + {"Scanner.ErrorCount", Field, 0, ""}, + {"Scanner.IsIdentRune", Field, 4, ""}, + {"Scanner.Mode", Field, 0, ""}, + {"Scanner.Position", Field, 0, ""}, + {"Scanner.Whitespace", Field, 0, ""}, + {"SkipComments", Const, 0, ""}, + {"String", Const, 0, ""}, + {"TokenString", Func, 0, "func(tok rune) string"}, }, "text/tabwriter": { - {"(*Writer).Flush", Method, 0}, - {"(*Writer).Init", Method, 0}, - {"(*Writer).Write", Method, 0}, - {"AlignRight", Const, 0}, - {"Debug", Const, 0}, - {"DiscardEmptyColumns", Const, 0}, - {"Escape", Const, 0}, - {"FilterHTML", Const, 0}, - {"NewWriter", Func, 0}, - {"StripEscape", Const, 0}, - {"TabIndent", Const, 0}, - {"Writer", Type, 0}, + {"(*Writer).Flush", Method, 0, ""}, + {"(*Writer).Init", Method, 0, ""}, + {"(*Writer).Write", Method, 0, ""}, + {"AlignRight", Const, 0, ""}, + {"Debug", Const, 0, ""}, + {"DiscardEmptyColumns", Const, 0, ""}, + {"Escape", Const, 0, ""}, + {"FilterHTML", Const, 0, ""}, + {"NewWriter", Func, 0, "func(output io.Writer, minwidth int, tabwidth int, padding int, padchar byte, flags uint) *Writer"}, + {"StripEscape", Const, 0, ""}, + {"TabIndent", Const, 0, ""}, + {"Writer", Type, 0, ""}, }, "text/template": { - {"(*Template).AddParseTree", Method, 0}, - {"(*Template).Clone", Method, 0}, - {"(*Template).DefinedTemplates", Method, 5}, - {"(*Template).Delims", Method, 0}, - {"(*Template).Execute", Method, 0}, - {"(*Template).ExecuteTemplate", Method, 0}, - {"(*Template).Funcs", Method, 0}, - {"(*Template).Lookup", Method, 0}, - {"(*Template).Name", Method, 0}, - {"(*Template).New", Method, 0}, - {"(*Template).Option", Method, 5}, - {"(*Template).Parse", Method, 0}, - {"(*Template).ParseFS", Method, 16}, - {"(*Template).ParseFiles", Method, 0}, - {"(*Template).ParseGlob", Method, 0}, - {"(*Template).Templates", Method, 0}, - {"(ExecError).Error", Method, 6}, - {"(ExecError).Unwrap", Method, 13}, - {"(Template).Copy", Method, 2}, - {"(Template).ErrorContext", Method, 1}, - {"ExecError", Type, 6}, - {"ExecError.Err", Field, 6}, - {"ExecError.Name", Field, 6}, - {"FuncMap", Type, 0}, - {"HTMLEscape", Func, 0}, - {"HTMLEscapeString", Func, 0}, - {"HTMLEscaper", Func, 0}, - {"IsTrue", Func, 6}, - {"JSEscape", Func, 0}, - {"JSEscapeString", Func, 0}, - {"JSEscaper", Func, 0}, - {"Must", Func, 0}, - {"New", Func, 0}, - {"ParseFS", Func, 16}, - {"ParseFiles", Func, 0}, - {"ParseGlob", Func, 0}, - {"Template", Type, 0}, - {"Template.Tree", Field, 0}, - {"URLQueryEscaper", Func, 0}, + {"(*Template).AddParseTree", Method, 0, ""}, + {"(*Template).Clone", Method, 0, ""}, + {"(*Template).DefinedTemplates", Method, 5, ""}, + {"(*Template).Delims", Method, 0, ""}, + {"(*Template).Execute", Method, 0, ""}, + {"(*Template).ExecuteTemplate", Method, 0, ""}, + {"(*Template).Funcs", Method, 0, ""}, + {"(*Template).Lookup", Method, 0, ""}, + {"(*Template).Name", Method, 0, ""}, + {"(*Template).New", Method, 0, ""}, + {"(*Template).Option", Method, 5, ""}, + {"(*Template).Parse", Method, 0, ""}, + {"(*Template).ParseFS", Method, 16, ""}, + {"(*Template).ParseFiles", Method, 0, ""}, + {"(*Template).ParseGlob", Method, 0, ""}, + {"(*Template).Templates", Method, 0, ""}, + {"(ExecError).Error", Method, 6, ""}, + {"(ExecError).Unwrap", Method, 13, ""}, + {"(Template).Copy", Method, 2, ""}, + {"(Template).ErrorContext", Method, 1, ""}, + {"ExecError", Type, 6, ""}, + {"ExecError.Err", Field, 6, ""}, + {"ExecError.Name", Field, 6, ""}, + {"FuncMap", Type, 0, ""}, + {"HTMLEscape", Func, 0, "func(w io.Writer, b []byte)"}, + {"HTMLEscapeString", Func, 0, "func(s string) string"}, + {"HTMLEscaper", Func, 0, "func(args ...any) string"}, + {"IsTrue", Func, 6, "func(val any) (truth bool, ok bool)"}, + {"JSEscape", Func, 0, "func(w io.Writer, b []byte)"}, + {"JSEscapeString", Func, 0, "func(s string) string"}, + {"JSEscaper", Func, 0, "func(args ...any) string"}, + {"Must", Func, 0, "func(t *Template, err error) *Template"}, + {"New", Func, 0, "func(name string) *Template"}, + {"ParseFS", Func, 16, "func(fsys fs.FS, patterns ...string) (*Template, error)"}, + {"ParseFiles", Func, 0, "func(filenames ...string) (*Template, error)"}, + {"ParseGlob", Func, 0, "func(pattern string) (*Template, error)"}, + {"Template", Type, 0, ""}, + {"Template.Tree", Field, 0, ""}, + {"URLQueryEscaper", Func, 0, "func(args ...any) string"}, }, "text/template/parse": { - {"(*ActionNode).Copy", Method, 0}, - {"(*ActionNode).String", Method, 0}, - {"(*BoolNode).Copy", Method, 0}, - {"(*BoolNode).String", Method, 0}, - {"(*BranchNode).Copy", Method, 4}, - {"(*BranchNode).String", Method, 0}, - {"(*BreakNode).Copy", Method, 18}, - {"(*BreakNode).String", Method, 18}, - {"(*ChainNode).Add", Method, 1}, - {"(*ChainNode).Copy", Method, 1}, - {"(*ChainNode).String", Method, 1}, - {"(*CommandNode).Copy", Method, 0}, - {"(*CommandNode).String", Method, 0}, - {"(*CommentNode).Copy", Method, 16}, - {"(*CommentNode).String", Method, 16}, - {"(*ContinueNode).Copy", Method, 18}, - {"(*ContinueNode).String", Method, 18}, - {"(*DotNode).Copy", Method, 0}, - {"(*DotNode).String", Method, 0}, - {"(*DotNode).Type", Method, 0}, - {"(*FieldNode).Copy", Method, 0}, - {"(*FieldNode).String", Method, 0}, - {"(*IdentifierNode).Copy", Method, 0}, - {"(*IdentifierNode).SetPos", Method, 1}, - {"(*IdentifierNode).SetTree", Method, 4}, - {"(*IdentifierNode).String", Method, 0}, - {"(*IfNode).Copy", Method, 0}, - {"(*IfNode).String", Method, 0}, - {"(*ListNode).Copy", Method, 0}, - {"(*ListNode).CopyList", Method, 0}, - {"(*ListNode).String", Method, 0}, - {"(*NilNode).Copy", Method, 1}, - {"(*NilNode).String", Method, 1}, - {"(*NilNode).Type", Method, 1}, - {"(*NumberNode).Copy", Method, 0}, - {"(*NumberNode).String", Method, 0}, - {"(*PipeNode).Copy", Method, 0}, - {"(*PipeNode).CopyPipe", Method, 0}, - {"(*PipeNode).String", Method, 0}, - {"(*RangeNode).Copy", Method, 0}, - {"(*RangeNode).String", Method, 0}, - {"(*StringNode).Copy", Method, 0}, - {"(*StringNode).String", Method, 0}, - {"(*TemplateNode).Copy", Method, 0}, - {"(*TemplateNode).String", Method, 0}, - {"(*TextNode).Copy", Method, 0}, - {"(*TextNode).String", Method, 0}, - {"(*Tree).Copy", Method, 2}, - {"(*Tree).ErrorContext", Method, 1}, - {"(*Tree).Parse", Method, 0}, - {"(*VariableNode).Copy", Method, 0}, - {"(*VariableNode).String", Method, 0}, - {"(*WithNode).Copy", Method, 0}, - {"(*WithNode).String", Method, 0}, - {"(ActionNode).Position", Method, 1}, - {"(ActionNode).Type", Method, 0}, - {"(BoolNode).Position", Method, 1}, - {"(BoolNode).Type", Method, 0}, - {"(BranchNode).Position", Method, 1}, - {"(BranchNode).Type", Method, 0}, - {"(BreakNode).Position", Method, 18}, - {"(BreakNode).Type", Method, 18}, - {"(ChainNode).Position", Method, 1}, - {"(ChainNode).Type", Method, 1}, - {"(CommandNode).Position", Method, 1}, - {"(CommandNode).Type", Method, 0}, - {"(CommentNode).Position", Method, 16}, - {"(CommentNode).Type", Method, 16}, - {"(ContinueNode).Position", Method, 18}, - {"(ContinueNode).Type", Method, 18}, - {"(DotNode).Position", Method, 1}, - {"(FieldNode).Position", Method, 1}, - {"(FieldNode).Type", Method, 0}, - {"(IdentifierNode).Position", Method, 1}, - {"(IdentifierNode).Type", Method, 0}, - {"(IfNode).Position", Method, 1}, - {"(IfNode).Type", Method, 0}, - {"(ListNode).Position", Method, 1}, - {"(ListNode).Type", Method, 0}, - {"(NilNode).Position", Method, 1}, - {"(NodeType).Type", Method, 0}, - {"(NumberNode).Position", Method, 1}, - {"(NumberNode).Type", Method, 0}, - {"(PipeNode).Position", Method, 1}, - {"(PipeNode).Type", Method, 0}, - {"(Pos).Position", Method, 1}, - {"(RangeNode).Position", Method, 1}, - {"(RangeNode).Type", Method, 0}, - {"(StringNode).Position", Method, 1}, - {"(StringNode).Type", Method, 0}, - {"(TemplateNode).Position", Method, 1}, - {"(TemplateNode).Type", Method, 0}, - {"(TextNode).Position", Method, 1}, - {"(TextNode).Type", Method, 0}, - {"(VariableNode).Position", Method, 1}, - {"(VariableNode).Type", Method, 0}, - {"(WithNode).Position", Method, 1}, - {"(WithNode).Type", Method, 0}, - {"ActionNode", Type, 0}, - {"ActionNode.Line", Field, 0}, - {"ActionNode.NodeType", Field, 0}, - {"ActionNode.Pipe", Field, 0}, - {"ActionNode.Pos", Field, 1}, - {"BoolNode", Type, 0}, - {"BoolNode.NodeType", Field, 0}, - {"BoolNode.Pos", Field, 1}, - {"BoolNode.True", Field, 0}, - {"BranchNode", Type, 0}, - {"BranchNode.ElseList", Field, 0}, - {"BranchNode.Line", Field, 0}, - {"BranchNode.List", Field, 0}, - {"BranchNode.NodeType", Field, 0}, - {"BranchNode.Pipe", Field, 0}, - {"BranchNode.Pos", Field, 1}, - {"BreakNode", Type, 18}, - {"BreakNode.Line", Field, 18}, - {"BreakNode.NodeType", Field, 18}, - {"BreakNode.Pos", Field, 18}, - {"ChainNode", Type, 1}, - {"ChainNode.Field", Field, 1}, - {"ChainNode.Node", Field, 1}, - {"ChainNode.NodeType", Field, 1}, - {"ChainNode.Pos", Field, 1}, - {"CommandNode", Type, 0}, - {"CommandNode.Args", Field, 0}, - {"CommandNode.NodeType", Field, 0}, - {"CommandNode.Pos", Field, 1}, - {"CommentNode", Type, 16}, - {"CommentNode.NodeType", Field, 16}, - {"CommentNode.Pos", Field, 16}, - {"CommentNode.Text", Field, 16}, - {"ContinueNode", Type, 18}, - {"ContinueNode.Line", Field, 18}, - {"ContinueNode.NodeType", Field, 18}, - {"ContinueNode.Pos", Field, 18}, - {"DotNode", Type, 0}, - {"DotNode.NodeType", Field, 4}, - {"DotNode.Pos", Field, 1}, - {"FieldNode", Type, 0}, - {"FieldNode.Ident", Field, 0}, - {"FieldNode.NodeType", Field, 0}, - {"FieldNode.Pos", Field, 1}, - {"IdentifierNode", Type, 0}, - {"IdentifierNode.Ident", Field, 0}, - {"IdentifierNode.NodeType", Field, 0}, - {"IdentifierNode.Pos", Field, 1}, - {"IfNode", Type, 0}, - {"IfNode.BranchNode", Field, 0}, - {"IsEmptyTree", Func, 0}, - {"ListNode", Type, 0}, - {"ListNode.NodeType", Field, 0}, - {"ListNode.Nodes", Field, 0}, - {"ListNode.Pos", Field, 1}, - {"Mode", Type, 16}, - {"New", Func, 0}, - {"NewIdentifier", Func, 0}, - {"NilNode", Type, 1}, - {"NilNode.NodeType", Field, 4}, - {"NilNode.Pos", Field, 1}, - {"Node", Type, 0}, - {"NodeAction", Const, 0}, - {"NodeBool", Const, 0}, - {"NodeBreak", Const, 18}, - {"NodeChain", Const, 1}, - {"NodeCommand", Const, 0}, - {"NodeComment", Const, 16}, - {"NodeContinue", Const, 18}, - {"NodeDot", Const, 0}, - {"NodeField", Const, 0}, - {"NodeIdentifier", Const, 0}, - {"NodeIf", Const, 0}, - {"NodeList", Const, 0}, - {"NodeNil", Const, 1}, - {"NodeNumber", Const, 0}, - {"NodePipe", Const, 0}, - {"NodeRange", Const, 0}, - {"NodeString", Const, 0}, - {"NodeTemplate", Const, 0}, - {"NodeText", Const, 0}, - {"NodeType", Type, 0}, - {"NodeVariable", Const, 0}, - {"NodeWith", Const, 0}, - {"NumberNode", Type, 0}, - {"NumberNode.Complex128", Field, 0}, - {"NumberNode.Float64", Field, 0}, - {"NumberNode.Int64", Field, 0}, - {"NumberNode.IsComplex", Field, 0}, - {"NumberNode.IsFloat", Field, 0}, - {"NumberNode.IsInt", Field, 0}, - {"NumberNode.IsUint", Field, 0}, - {"NumberNode.NodeType", Field, 0}, - {"NumberNode.Pos", Field, 1}, - {"NumberNode.Text", Field, 0}, - {"NumberNode.Uint64", Field, 0}, - {"Parse", Func, 0}, - {"ParseComments", Const, 16}, - {"PipeNode", Type, 0}, - {"PipeNode.Cmds", Field, 0}, - {"PipeNode.Decl", Field, 0}, - {"PipeNode.IsAssign", Field, 11}, - {"PipeNode.Line", Field, 0}, - {"PipeNode.NodeType", Field, 0}, - {"PipeNode.Pos", Field, 1}, - {"Pos", Type, 1}, - {"RangeNode", Type, 0}, - {"RangeNode.BranchNode", Field, 0}, - {"SkipFuncCheck", Const, 17}, - {"StringNode", Type, 0}, - {"StringNode.NodeType", Field, 0}, - {"StringNode.Pos", Field, 1}, - {"StringNode.Quoted", Field, 0}, - {"StringNode.Text", Field, 0}, - {"TemplateNode", Type, 0}, - {"TemplateNode.Line", Field, 0}, - {"TemplateNode.Name", Field, 0}, - {"TemplateNode.NodeType", Field, 0}, - {"TemplateNode.Pipe", Field, 0}, - {"TemplateNode.Pos", Field, 1}, - {"TextNode", Type, 0}, - {"TextNode.NodeType", Field, 0}, - {"TextNode.Pos", Field, 1}, - {"TextNode.Text", Field, 0}, - {"Tree", Type, 0}, - {"Tree.Mode", Field, 16}, - {"Tree.Name", Field, 0}, - {"Tree.ParseName", Field, 1}, - {"Tree.Root", Field, 0}, - {"VariableNode", Type, 0}, - {"VariableNode.Ident", Field, 0}, - {"VariableNode.NodeType", Field, 0}, - {"VariableNode.Pos", Field, 1}, - {"WithNode", Type, 0}, - {"WithNode.BranchNode", Field, 0}, + {"(*ActionNode).Copy", Method, 0, ""}, + {"(*ActionNode).String", Method, 0, ""}, + {"(*BoolNode).Copy", Method, 0, ""}, + {"(*BoolNode).String", Method, 0, ""}, + {"(*BranchNode).Copy", Method, 4, ""}, + {"(*BranchNode).String", Method, 0, ""}, + {"(*BreakNode).Copy", Method, 18, ""}, + {"(*BreakNode).String", Method, 18, ""}, + {"(*ChainNode).Add", Method, 1, ""}, + {"(*ChainNode).Copy", Method, 1, ""}, + {"(*ChainNode).String", Method, 1, ""}, + {"(*CommandNode).Copy", Method, 0, ""}, + {"(*CommandNode).String", Method, 0, ""}, + {"(*CommentNode).Copy", Method, 16, ""}, + {"(*CommentNode).String", Method, 16, ""}, + {"(*ContinueNode).Copy", Method, 18, ""}, + {"(*ContinueNode).String", Method, 18, ""}, + {"(*DotNode).Copy", Method, 0, ""}, + {"(*DotNode).String", Method, 0, ""}, + {"(*DotNode).Type", Method, 0, ""}, + {"(*FieldNode).Copy", Method, 0, ""}, + {"(*FieldNode).String", Method, 0, ""}, + {"(*IdentifierNode).Copy", Method, 0, ""}, + {"(*IdentifierNode).SetPos", Method, 1, ""}, + {"(*IdentifierNode).SetTree", Method, 4, ""}, + {"(*IdentifierNode).String", Method, 0, ""}, + {"(*IfNode).Copy", Method, 0, ""}, + {"(*IfNode).String", Method, 0, ""}, + {"(*ListNode).Copy", Method, 0, ""}, + {"(*ListNode).CopyList", Method, 0, ""}, + {"(*ListNode).String", Method, 0, ""}, + {"(*NilNode).Copy", Method, 1, ""}, + {"(*NilNode).String", Method, 1, ""}, + {"(*NilNode).Type", Method, 1, ""}, + {"(*NumberNode).Copy", Method, 0, ""}, + {"(*NumberNode).String", Method, 0, ""}, + {"(*PipeNode).Copy", Method, 0, ""}, + {"(*PipeNode).CopyPipe", Method, 0, ""}, + {"(*PipeNode).String", Method, 0, ""}, + {"(*RangeNode).Copy", Method, 0, ""}, + {"(*RangeNode).String", Method, 0, ""}, + {"(*StringNode).Copy", Method, 0, ""}, + {"(*StringNode).String", Method, 0, ""}, + {"(*TemplateNode).Copy", Method, 0, ""}, + {"(*TemplateNode).String", Method, 0, ""}, + {"(*TextNode).Copy", Method, 0, ""}, + {"(*TextNode).String", Method, 0, ""}, + {"(*Tree).Copy", Method, 2, ""}, + {"(*Tree).ErrorContext", Method, 1, ""}, + {"(*Tree).Parse", Method, 0, ""}, + {"(*VariableNode).Copy", Method, 0, ""}, + {"(*VariableNode).String", Method, 0, ""}, + {"(*WithNode).Copy", Method, 0, ""}, + {"(*WithNode).String", Method, 0, ""}, + {"(ActionNode).Position", Method, 1, ""}, + {"(ActionNode).Type", Method, 0, ""}, + {"(BoolNode).Position", Method, 1, ""}, + {"(BoolNode).Type", Method, 0, ""}, + {"(BranchNode).Position", Method, 1, ""}, + {"(BranchNode).Type", Method, 0, ""}, + {"(BreakNode).Position", Method, 18, ""}, + {"(BreakNode).Type", Method, 18, ""}, + {"(ChainNode).Position", Method, 1, ""}, + {"(ChainNode).Type", Method, 1, ""}, + {"(CommandNode).Position", Method, 1, ""}, + {"(CommandNode).Type", Method, 0, ""}, + {"(CommentNode).Position", Method, 16, ""}, + {"(CommentNode).Type", Method, 16, ""}, + {"(ContinueNode).Position", Method, 18, ""}, + {"(ContinueNode).Type", Method, 18, ""}, + {"(DotNode).Position", Method, 1, ""}, + {"(FieldNode).Position", Method, 1, ""}, + {"(FieldNode).Type", Method, 0, ""}, + {"(IdentifierNode).Position", Method, 1, ""}, + {"(IdentifierNode).Type", Method, 0, ""}, + {"(IfNode).Position", Method, 1, ""}, + {"(IfNode).Type", Method, 0, ""}, + {"(ListNode).Position", Method, 1, ""}, + {"(ListNode).Type", Method, 0, ""}, + {"(NilNode).Position", Method, 1, ""}, + {"(NodeType).Type", Method, 0, ""}, + {"(NumberNode).Position", Method, 1, ""}, + {"(NumberNode).Type", Method, 0, ""}, + {"(PipeNode).Position", Method, 1, ""}, + {"(PipeNode).Type", Method, 0, ""}, + {"(Pos).Position", Method, 1, ""}, + {"(RangeNode).Position", Method, 1, ""}, + {"(RangeNode).Type", Method, 0, ""}, + {"(StringNode).Position", Method, 1, ""}, + {"(StringNode).Type", Method, 0, ""}, + {"(TemplateNode).Position", Method, 1, ""}, + {"(TemplateNode).Type", Method, 0, ""}, + {"(TextNode).Position", Method, 1, ""}, + {"(TextNode).Type", Method, 0, ""}, + {"(VariableNode).Position", Method, 1, ""}, + {"(VariableNode).Type", Method, 0, ""}, + {"(WithNode).Position", Method, 1, ""}, + {"(WithNode).Type", Method, 0, ""}, + {"ActionNode", Type, 0, ""}, + {"ActionNode.Line", Field, 0, ""}, + {"ActionNode.NodeType", Field, 0, ""}, + {"ActionNode.Pipe", Field, 0, ""}, + {"ActionNode.Pos", Field, 1, ""}, + {"BoolNode", Type, 0, ""}, + {"BoolNode.NodeType", Field, 0, ""}, + {"BoolNode.Pos", Field, 1, ""}, + {"BoolNode.True", Field, 0, ""}, + {"BranchNode", Type, 0, ""}, + {"BranchNode.ElseList", Field, 0, ""}, + {"BranchNode.Line", Field, 0, ""}, + {"BranchNode.List", Field, 0, ""}, + {"BranchNode.NodeType", Field, 0, ""}, + {"BranchNode.Pipe", Field, 0, ""}, + {"BranchNode.Pos", Field, 1, ""}, + {"BreakNode", Type, 18, ""}, + {"BreakNode.Line", Field, 18, ""}, + {"BreakNode.NodeType", Field, 18, ""}, + {"BreakNode.Pos", Field, 18, ""}, + {"ChainNode", Type, 1, ""}, + {"ChainNode.Field", Field, 1, ""}, + {"ChainNode.Node", Field, 1, ""}, + {"ChainNode.NodeType", Field, 1, ""}, + {"ChainNode.Pos", Field, 1, ""}, + {"CommandNode", Type, 0, ""}, + {"CommandNode.Args", Field, 0, ""}, + {"CommandNode.NodeType", Field, 0, ""}, + {"CommandNode.Pos", Field, 1, ""}, + {"CommentNode", Type, 16, ""}, + {"CommentNode.NodeType", Field, 16, ""}, + {"CommentNode.Pos", Field, 16, ""}, + {"CommentNode.Text", Field, 16, ""}, + {"ContinueNode", Type, 18, ""}, + {"ContinueNode.Line", Field, 18, ""}, + {"ContinueNode.NodeType", Field, 18, ""}, + {"ContinueNode.Pos", Field, 18, ""}, + {"DotNode", Type, 0, ""}, + {"DotNode.NodeType", Field, 4, ""}, + {"DotNode.Pos", Field, 1, ""}, + {"FieldNode", Type, 0, ""}, + {"FieldNode.Ident", Field, 0, ""}, + {"FieldNode.NodeType", Field, 0, ""}, + {"FieldNode.Pos", Field, 1, ""}, + {"IdentifierNode", Type, 0, ""}, + {"IdentifierNode.Ident", Field, 0, ""}, + {"IdentifierNode.NodeType", Field, 0, ""}, + {"IdentifierNode.Pos", Field, 1, ""}, + {"IfNode", Type, 0, ""}, + {"IfNode.BranchNode", Field, 0, ""}, + {"IsEmptyTree", Func, 0, "func(n Node) bool"}, + {"ListNode", Type, 0, ""}, + {"ListNode.NodeType", Field, 0, ""}, + {"ListNode.Nodes", Field, 0, ""}, + {"ListNode.Pos", Field, 1, ""}, + {"Mode", Type, 16, ""}, + {"New", Func, 0, "func(name string, funcs ...map[string]any) *Tree"}, + {"NewIdentifier", Func, 0, "func(ident string) *IdentifierNode"}, + {"NilNode", Type, 1, ""}, + {"NilNode.NodeType", Field, 4, ""}, + {"NilNode.Pos", Field, 1, ""}, + {"Node", Type, 0, ""}, + {"NodeAction", Const, 0, ""}, + {"NodeBool", Const, 0, ""}, + {"NodeBreak", Const, 18, ""}, + {"NodeChain", Const, 1, ""}, + {"NodeCommand", Const, 0, ""}, + {"NodeComment", Const, 16, ""}, + {"NodeContinue", Const, 18, ""}, + {"NodeDot", Const, 0, ""}, + {"NodeField", Const, 0, ""}, + {"NodeIdentifier", Const, 0, ""}, + {"NodeIf", Const, 0, ""}, + {"NodeList", Const, 0, ""}, + {"NodeNil", Const, 1, ""}, + {"NodeNumber", Const, 0, ""}, + {"NodePipe", Const, 0, ""}, + {"NodeRange", Const, 0, ""}, + {"NodeString", Const, 0, ""}, + {"NodeTemplate", Const, 0, ""}, + {"NodeText", Const, 0, ""}, + {"NodeType", Type, 0, ""}, + {"NodeVariable", Const, 0, ""}, + {"NodeWith", Const, 0, ""}, + {"NumberNode", Type, 0, ""}, + {"NumberNode.Complex128", Field, 0, ""}, + {"NumberNode.Float64", Field, 0, ""}, + {"NumberNode.Int64", Field, 0, ""}, + {"NumberNode.IsComplex", Field, 0, ""}, + {"NumberNode.IsFloat", Field, 0, ""}, + {"NumberNode.IsInt", Field, 0, ""}, + {"NumberNode.IsUint", Field, 0, ""}, + {"NumberNode.NodeType", Field, 0, ""}, + {"NumberNode.Pos", Field, 1, ""}, + {"NumberNode.Text", Field, 0, ""}, + {"NumberNode.Uint64", Field, 0, ""}, + {"Parse", Func, 0, "func(name string, text string, leftDelim string, rightDelim string, funcs ...map[string]any) (map[string]*Tree, error)"}, + {"ParseComments", Const, 16, ""}, + {"PipeNode", Type, 0, ""}, + {"PipeNode.Cmds", Field, 0, ""}, + {"PipeNode.Decl", Field, 0, ""}, + {"PipeNode.IsAssign", Field, 11, ""}, + {"PipeNode.Line", Field, 0, ""}, + {"PipeNode.NodeType", Field, 0, ""}, + {"PipeNode.Pos", Field, 1, ""}, + {"Pos", Type, 1, ""}, + {"RangeNode", Type, 0, ""}, + {"RangeNode.BranchNode", Field, 0, ""}, + {"SkipFuncCheck", Const, 17, ""}, + {"StringNode", Type, 0, ""}, + {"StringNode.NodeType", Field, 0, ""}, + {"StringNode.Pos", Field, 1, ""}, + {"StringNode.Quoted", Field, 0, ""}, + {"StringNode.Text", Field, 0, ""}, + {"TemplateNode", Type, 0, ""}, + {"TemplateNode.Line", Field, 0, ""}, + {"TemplateNode.Name", Field, 0, ""}, + {"TemplateNode.NodeType", Field, 0, ""}, + {"TemplateNode.Pipe", Field, 0, ""}, + {"TemplateNode.Pos", Field, 1, ""}, + {"TextNode", Type, 0, ""}, + {"TextNode.NodeType", Field, 0, ""}, + {"TextNode.Pos", Field, 1, ""}, + {"TextNode.Text", Field, 0, ""}, + {"Tree", Type, 0, ""}, + {"Tree.Mode", Field, 16, ""}, + {"Tree.Name", Field, 0, ""}, + {"Tree.ParseName", Field, 1, ""}, + {"Tree.Root", Field, 0, ""}, + {"VariableNode", Type, 0, ""}, + {"VariableNode.Ident", Field, 0, ""}, + {"VariableNode.NodeType", Field, 0, ""}, + {"VariableNode.Pos", Field, 1, ""}, + {"WithNode", Type, 0, ""}, + {"WithNode.BranchNode", Field, 0, ""}, }, "time": { - {"(*Location).String", Method, 0}, - {"(*ParseError).Error", Method, 0}, - {"(*Ticker).Reset", Method, 15}, - {"(*Ticker).Stop", Method, 0}, - {"(*Time).GobDecode", Method, 0}, - {"(*Time).UnmarshalBinary", Method, 2}, - {"(*Time).UnmarshalJSON", Method, 0}, - {"(*Time).UnmarshalText", Method, 2}, - {"(*Timer).Reset", Method, 1}, - {"(*Timer).Stop", Method, 0}, - {"(Duration).Abs", Method, 19}, - {"(Duration).Hours", Method, 0}, - {"(Duration).Microseconds", Method, 13}, - {"(Duration).Milliseconds", Method, 13}, - {"(Duration).Minutes", Method, 0}, - {"(Duration).Nanoseconds", Method, 0}, - {"(Duration).Round", Method, 9}, - {"(Duration).Seconds", Method, 0}, - {"(Duration).String", Method, 0}, - {"(Duration).Truncate", Method, 9}, - {"(Month).String", Method, 0}, - {"(Time).Add", Method, 0}, - {"(Time).AddDate", Method, 0}, - {"(Time).After", Method, 0}, - {"(Time).AppendBinary", Method, 24}, - {"(Time).AppendFormat", Method, 5}, - {"(Time).AppendText", Method, 24}, - {"(Time).Before", Method, 0}, - {"(Time).Clock", Method, 0}, - {"(Time).Compare", Method, 20}, - {"(Time).Date", Method, 0}, - {"(Time).Day", Method, 0}, - {"(Time).Equal", Method, 0}, - {"(Time).Format", Method, 0}, - {"(Time).GoString", Method, 17}, - {"(Time).GobEncode", Method, 0}, - {"(Time).Hour", Method, 0}, - {"(Time).ISOWeek", Method, 0}, - {"(Time).In", Method, 0}, - {"(Time).IsDST", Method, 17}, - {"(Time).IsZero", Method, 0}, - {"(Time).Local", Method, 0}, - {"(Time).Location", Method, 0}, - {"(Time).MarshalBinary", Method, 2}, - {"(Time).MarshalJSON", Method, 0}, - {"(Time).MarshalText", Method, 2}, - {"(Time).Minute", Method, 0}, - {"(Time).Month", Method, 0}, - {"(Time).Nanosecond", Method, 0}, - {"(Time).Round", Method, 1}, - {"(Time).Second", Method, 0}, - {"(Time).String", Method, 0}, - {"(Time).Sub", Method, 0}, - {"(Time).Truncate", Method, 1}, - {"(Time).UTC", Method, 0}, - {"(Time).Unix", Method, 0}, - {"(Time).UnixMicro", Method, 17}, - {"(Time).UnixMilli", Method, 17}, - {"(Time).UnixNano", Method, 0}, - {"(Time).Weekday", Method, 0}, - {"(Time).Year", Method, 0}, - {"(Time).YearDay", Method, 1}, - {"(Time).Zone", Method, 0}, - {"(Time).ZoneBounds", Method, 19}, - {"(Weekday).String", Method, 0}, - {"ANSIC", Const, 0}, - {"After", Func, 0}, - {"AfterFunc", Func, 0}, - {"April", Const, 0}, - {"August", Const, 0}, - {"Date", Func, 0}, - {"DateOnly", Const, 20}, - {"DateTime", Const, 20}, - {"December", Const, 0}, - {"Duration", Type, 0}, - {"February", Const, 0}, - {"FixedZone", Func, 0}, - {"Friday", Const, 0}, - {"Hour", Const, 0}, - {"January", Const, 0}, - {"July", Const, 0}, - {"June", Const, 0}, - {"Kitchen", Const, 0}, - {"Layout", Const, 17}, - {"LoadLocation", Func, 0}, - {"LoadLocationFromTZData", Func, 10}, - {"Local", Var, 0}, - {"Location", Type, 0}, - {"March", Const, 0}, - {"May", Const, 0}, - {"Microsecond", Const, 0}, - {"Millisecond", Const, 0}, - {"Minute", Const, 0}, - {"Monday", Const, 0}, - {"Month", Type, 0}, - {"Nanosecond", Const, 0}, - {"NewTicker", Func, 0}, - {"NewTimer", Func, 0}, - {"November", Const, 0}, - {"Now", Func, 0}, - {"October", Const, 0}, - {"Parse", Func, 0}, - {"ParseDuration", Func, 0}, - {"ParseError", Type, 0}, - {"ParseError.Layout", Field, 0}, - {"ParseError.LayoutElem", Field, 0}, - {"ParseError.Message", Field, 0}, - {"ParseError.Value", Field, 0}, - {"ParseError.ValueElem", Field, 0}, - {"ParseInLocation", Func, 1}, - {"RFC1123", Const, 0}, - {"RFC1123Z", Const, 0}, - {"RFC3339", Const, 0}, - {"RFC3339Nano", Const, 0}, - {"RFC822", Const, 0}, - {"RFC822Z", Const, 0}, - {"RFC850", Const, 0}, - {"RubyDate", Const, 0}, - {"Saturday", Const, 0}, - {"Second", Const, 0}, - {"September", Const, 0}, - {"Since", Func, 0}, - {"Sleep", Func, 0}, - {"Stamp", Const, 0}, - {"StampMicro", Const, 0}, - {"StampMilli", Const, 0}, - {"StampNano", Const, 0}, - {"Sunday", Const, 0}, - {"Thursday", Const, 0}, - {"Tick", Func, 0}, - {"Ticker", Type, 0}, - {"Ticker.C", Field, 0}, - {"Time", Type, 0}, - {"TimeOnly", Const, 20}, - {"Timer", Type, 0}, - {"Timer.C", Field, 0}, - {"Tuesday", Const, 0}, - {"UTC", Var, 0}, - {"Unix", Func, 0}, - {"UnixDate", Const, 0}, - {"UnixMicro", Func, 17}, - {"UnixMilli", Func, 17}, - {"Until", Func, 8}, - {"Wednesday", Const, 0}, - {"Weekday", Type, 0}, + {"(*Location).String", Method, 0, ""}, + {"(*ParseError).Error", Method, 0, ""}, + {"(*Ticker).Reset", Method, 15, ""}, + {"(*Ticker).Stop", Method, 0, ""}, + {"(*Time).GobDecode", Method, 0, ""}, + {"(*Time).UnmarshalBinary", Method, 2, ""}, + {"(*Time).UnmarshalJSON", Method, 0, ""}, + {"(*Time).UnmarshalText", Method, 2, ""}, + {"(*Timer).Reset", Method, 1, ""}, + {"(*Timer).Stop", Method, 0, ""}, + {"(Duration).Abs", Method, 19, ""}, + {"(Duration).Hours", Method, 0, ""}, + {"(Duration).Microseconds", Method, 13, ""}, + {"(Duration).Milliseconds", Method, 13, ""}, + {"(Duration).Minutes", Method, 0, ""}, + {"(Duration).Nanoseconds", Method, 0, ""}, + {"(Duration).Round", Method, 9, ""}, + {"(Duration).Seconds", Method, 0, ""}, + {"(Duration).String", Method, 0, ""}, + {"(Duration).Truncate", Method, 9, ""}, + {"(Month).String", Method, 0, ""}, + {"(Time).Add", Method, 0, ""}, + {"(Time).AddDate", Method, 0, ""}, + {"(Time).After", Method, 0, ""}, + {"(Time).AppendBinary", Method, 24, ""}, + {"(Time).AppendFormat", Method, 5, ""}, + {"(Time).AppendText", Method, 24, ""}, + {"(Time).Before", Method, 0, ""}, + {"(Time).Clock", Method, 0, ""}, + {"(Time).Compare", Method, 20, ""}, + {"(Time).Date", Method, 0, ""}, + {"(Time).Day", Method, 0, ""}, + {"(Time).Equal", Method, 0, ""}, + {"(Time).Format", Method, 0, ""}, + {"(Time).GoString", Method, 17, ""}, + {"(Time).GobEncode", Method, 0, ""}, + {"(Time).Hour", Method, 0, ""}, + {"(Time).ISOWeek", Method, 0, ""}, + {"(Time).In", Method, 0, ""}, + {"(Time).IsDST", Method, 17, ""}, + {"(Time).IsZero", Method, 0, ""}, + {"(Time).Local", Method, 0, ""}, + {"(Time).Location", Method, 0, ""}, + {"(Time).MarshalBinary", Method, 2, ""}, + {"(Time).MarshalJSON", Method, 0, ""}, + {"(Time).MarshalText", Method, 2, ""}, + {"(Time).Minute", Method, 0, ""}, + {"(Time).Month", Method, 0, ""}, + {"(Time).Nanosecond", Method, 0, ""}, + {"(Time).Round", Method, 1, ""}, + {"(Time).Second", Method, 0, ""}, + {"(Time).String", Method, 0, ""}, + {"(Time).Sub", Method, 0, ""}, + {"(Time).Truncate", Method, 1, ""}, + {"(Time).UTC", Method, 0, ""}, + {"(Time).Unix", Method, 0, ""}, + {"(Time).UnixMicro", Method, 17, ""}, + {"(Time).UnixMilli", Method, 17, ""}, + {"(Time).UnixNano", Method, 0, ""}, + {"(Time).Weekday", Method, 0, ""}, + {"(Time).Year", Method, 0, ""}, + {"(Time).YearDay", Method, 1, ""}, + {"(Time).Zone", Method, 0, ""}, + {"(Time).ZoneBounds", Method, 19, ""}, + {"(Weekday).String", Method, 0, ""}, + {"ANSIC", Const, 0, ""}, + {"After", Func, 0, "func(d Duration) <-chan Time"}, + {"AfterFunc", Func, 0, "func(d Duration, f func()) *Timer"}, + {"April", Const, 0, ""}, + {"August", Const, 0, ""}, + {"Date", Func, 0, "func(year int, month Month, day int, hour int, min int, sec int, nsec int, loc *Location) Time"}, + {"DateOnly", Const, 20, ""}, + {"DateTime", Const, 20, ""}, + {"December", Const, 0, ""}, + {"Duration", Type, 0, ""}, + {"February", Const, 0, ""}, + {"FixedZone", Func, 0, "func(name string, offset int) *Location"}, + {"Friday", Const, 0, ""}, + {"Hour", Const, 0, ""}, + {"January", Const, 0, ""}, + {"July", Const, 0, ""}, + {"June", Const, 0, ""}, + {"Kitchen", Const, 0, ""}, + {"Layout", Const, 17, ""}, + {"LoadLocation", Func, 0, "func(name string) (*Location, error)"}, + {"LoadLocationFromTZData", Func, 10, "func(name string, data []byte) (*Location, error)"}, + {"Local", Var, 0, ""}, + {"Location", Type, 0, ""}, + {"March", Const, 0, ""}, + {"May", Const, 0, ""}, + {"Microsecond", Const, 0, ""}, + {"Millisecond", Const, 0, ""}, + {"Minute", Const, 0, ""}, + {"Monday", Const, 0, ""}, + {"Month", Type, 0, ""}, + {"Nanosecond", Const, 0, ""}, + {"NewTicker", Func, 0, "func(d Duration) *Ticker"}, + {"NewTimer", Func, 0, "func(d Duration) *Timer"}, + {"November", Const, 0, ""}, + {"Now", Func, 0, "func() Time"}, + {"October", Const, 0, ""}, + {"Parse", Func, 0, "func(layout string, value string) (Time, error)"}, + {"ParseDuration", Func, 0, "func(s string) (Duration, error)"}, + {"ParseError", Type, 0, ""}, + {"ParseError.Layout", Field, 0, ""}, + {"ParseError.LayoutElem", Field, 0, ""}, + {"ParseError.Message", Field, 0, ""}, + {"ParseError.Value", Field, 0, ""}, + {"ParseError.ValueElem", Field, 0, ""}, + {"ParseInLocation", Func, 1, "func(layout string, value string, loc *Location) (Time, error)"}, + {"RFC1123", Const, 0, ""}, + {"RFC1123Z", Const, 0, ""}, + {"RFC3339", Const, 0, ""}, + {"RFC3339Nano", Const, 0, ""}, + {"RFC822", Const, 0, ""}, + {"RFC822Z", Const, 0, ""}, + {"RFC850", Const, 0, ""}, + {"RubyDate", Const, 0, ""}, + {"Saturday", Const, 0, ""}, + {"Second", Const, 0, ""}, + {"September", Const, 0, ""}, + {"Since", Func, 0, "func(t Time) Duration"}, + {"Sleep", Func, 0, "func(d Duration)"}, + {"Stamp", Const, 0, ""}, + {"StampMicro", Const, 0, ""}, + {"StampMilli", Const, 0, ""}, + {"StampNano", Const, 0, ""}, + {"Sunday", Const, 0, ""}, + {"Thursday", Const, 0, ""}, + {"Tick", Func, 0, "func(d Duration) <-chan Time"}, + {"Ticker", Type, 0, ""}, + {"Ticker.C", Field, 0, ""}, + {"Time", Type, 0, ""}, + {"TimeOnly", Const, 20, ""}, + {"Timer", Type, 0, ""}, + {"Timer.C", Field, 0, ""}, + {"Tuesday", Const, 0, ""}, + {"UTC", Var, 0, ""}, + {"Unix", Func, 0, "func(sec int64, nsec int64) Time"}, + {"UnixDate", Const, 0, ""}, + {"UnixMicro", Func, 17, "func(usec int64) Time"}, + {"UnixMilli", Func, 17, "func(msec int64) Time"}, + {"Until", Func, 8, "func(t Time) Duration"}, + {"Wednesday", Const, 0, ""}, + {"Weekday", Type, 0, ""}, }, "unicode": { - {"(SpecialCase).ToLower", Method, 0}, - {"(SpecialCase).ToTitle", Method, 0}, - {"(SpecialCase).ToUpper", Method, 0}, - {"ASCII_Hex_Digit", Var, 0}, - {"Adlam", Var, 7}, - {"Ahom", Var, 5}, - {"Anatolian_Hieroglyphs", Var, 5}, - {"Arabic", Var, 0}, - {"Armenian", Var, 0}, - {"Avestan", Var, 0}, - {"AzeriCase", Var, 0}, - {"Balinese", Var, 0}, - {"Bamum", Var, 0}, - {"Bassa_Vah", Var, 4}, - {"Batak", Var, 0}, - {"Bengali", Var, 0}, - {"Bhaiksuki", Var, 7}, - {"Bidi_Control", Var, 0}, - {"Bopomofo", Var, 0}, - {"Brahmi", Var, 0}, - {"Braille", Var, 0}, - {"Buginese", Var, 0}, - {"Buhid", Var, 0}, - {"C", Var, 0}, - {"Canadian_Aboriginal", Var, 0}, - {"Carian", Var, 0}, - {"CaseRange", Type, 0}, - {"CaseRange.Delta", Field, 0}, - {"CaseRange.Hi", Field, 0}, - {"CaseRange.Lo", Field, 0}, - {"CaseRanges", Var, 0}, - {"Categories", Var, 0}, - {"Caucasian_Albanian", Var, 4}, - {"Cc", Var, 0}, - {"Cf", Var, 0}, - {"Chakma", Var, 1}, - {"Cham", Var, 0}, - {"Cherokee", Var, 0}, - {"Chorasmian", Var, 16}, - {"Co", Var, 0}, - {"Common", Var, 0}, - {"Coptic", Var, 0}, - {"Cs", Var, 0}, - {"Cuneiform", Var, 0}, - {"Cypriot", Var, 0}, - {"Cypro_Minoan", Var, 21}, - {"Cyrillic", Var, 0}, - {"Dash", Var, 0}, - {"Deprecated", Var, 0}, - {"Deseret", Var, 0}, - {"Devanagari", Var, 0}, - {"Diacritic", Var, 0}, - {"Digit", Var, 0}, - {"Dives_Akuru", Var, 16}, - {"Dogra", Var, 13}, - {"Duployan", Var, 4}, - {"Egyptian_Hieroglyphs", Var, 0}, - {"Elbasan", Var, 4}, - {"Elymaic", Var, 14}, - {"Ethiopic", Var, 0}, - {"Extender", Var, 0}, - {"FoldCategory", Var, 0}, - {"FoldScript", Var, 0}, - {"Georgian", Var, 0}, - {"Glagolitic", Var, 0}, - {"Gothic", Var, 0}, - {"Grantha", Var, 4}, - {"GraphicRanges", Var, 0}, - {"Greek", Var, 0}, - {"Gujarati", Var, 0}, - {"Gunjala_Gondi", Var, 13}, - {"Gurmukhi", Var, 0}, - {"Han", Var, 0}, - {"Hangul", Var, 0}, - {"Hanifi_Rohingya", Var, 13}, - {"Hanunoo", Var, 0}, - {"Hatran", Var, 5}, - {"Hebrew", Var, 0}, - {"Hex_Digit", Var, 0}, - {"Hiragana", Var, 0}, - {"Hyphen", Var, 0}, - {"IDS_Binary_Operator", Var, 0}, - {"IDS_Trinary_Operator", Var, 0}, - {"Ideographic", Var, 0}, - {"Imperial_Aramaic", Var, 0}, - {"In", Func, 2}, - {"Inherited", Var, 0}, - {"Inscriptional_Pahlavi", Var, 0}, - {"Inscriptional_Parthian", Var, 0}, - {"Is", Func, 0}, - {"IsControl", Func, 0}, - {"IsDigit", Func, 0}, - {"IsGraphic", Func, 0}, - {"IsLetter", Func, 0}, - {"IsLower", Func, 0}, - {"IsMark", Func, 0}, - {"IsNumber", Func, 0}, - {"IsOneOf", Func, 0}, - {"IsPrint", Func, 0}, - {"IsPunct", Func, 0}, - {"IsSpace", Func, 0}, - {"IsSymbol", Func, 0}, - {"IsTitle", Func, 0}, - {"IsUpper", Func, 0}, - {"Javanese", Var, 0}, - {"Join_Control", Var, 0}, - {"Kaithi", Var, 0}, - {"Kannada", Var, 0}, - {"Katakana", Var, 0}, - {"Kawi", Var, 21}, - {"Kayah_Li", Var, 0}, - {"Kharoshthi", Var, 0}, - {"Khitan_Small_Script", Var, 16}, - {"Khmer", Var, 0}, - {"Khojki", Var, 4}, - {"Khudawadi", Var, 4}, - {"L", Var, 0}, - {"Lao", Var, 0}, - {"Latin", Var, 0}, - {"Lepcha", Var, 0}, - {"Letter", Var, 0}, - {"Limbu", Var, 0}, - {"Linear_A", Var, 4}, - {"Linear_B", Var, 0}, - {"Lisu", Var, 0}, - {"Ll", Var, 0}, - {"Lm", Var, 0}, - {"Lo", Var, 0}, - {"Logical_Order_Exception", Var, 0}, - {"Lower", Var, 0}, - {"LowerCase", Const, 0}, - {"Lt", Var, 0}, - {"Lu", Var, 0}, - {"Lycian", Var, 0}, - {"Lydian", Var, 0}, - {"M", Var, 0}, - {"Mahajani", Var, 4}, - {"Makasar", Var, 13}, - {"Malayalam", Var, 0}, - {"Mandaic", Var, 0}, - {"Manichaean", Var, 4}, - {"Marchen", Var, 7}, - {"Mark", Var, 0}, - {"Masaram_Gondi", Var, 10}, - {"MaxASCII", Const, 0}, - {"MaxCase", Const, 0}, - {"MaxLatin1", Const, 0}, - {"MaxRune", Const, 0}, - {"Mc", Var, 0}, - {"Me", Var, 0}, - {"Medefaidrin", Var, 13}, - {"Meetei_Mayek", Var, 0}, - {"Mende_Kikakui", Var, 4}, - {"Meroitic_Cursive", Var, 1}, - {"Meroitic_Hieroglyphs", Var, 1}, - {"Miao", Var, 1}, - {"Mn", Var, 0}, - {"Modi", Var, 4}, - {"Mongolian", Var, 0}, - {"Mro", Var, 4}, - {"Multani", Var, 5}, - {"Myanmar", Var, 0}, - {"N", Var, 0}, - {"Nabataean", Var, 4}, - {"Nag_Mundari", Var, 21}, - {"Nandinagari", Var, 14}, - {"Nd", Var, 0}, - {"New_Tai_Lue", Var, 0}, - {"Newa", Var, 7}, - {"Nko", Var, 0}, - {"Nl", Var, 0}, - {"No", Var, 0}, - {"Noncharacter_Code_Point", Var, 0}, - {"Number", Var, 0}, - {"Nushu", Var, 10}, - {"Nyiakeng_Puachue_Hmong", Var, 14}, - {"Ogham", Var, 0}, - {"Ol_Chiki", Var, 0}, - {"Old_Hungarian", Var, 5}, - {"Old_Italic", Var, 0}, - {"Old_North_Arabian", Var, 4}, - {"Old_Permic", Var, 4}, - {"Old_Persian", Var, 0}, - {"Old_Sogdian", Var, 13}, - {"Old_South_Arabian", Var, 0}, - {"Old_Turkic", Var, 0}, - {"Old_Uyghur", Var, 21}, - {"Oriya", Var, 0}, - {"Osage", Var, 7}, - {"Osmanya", Var, 0}, - {"Other", Var, 0}, - {"Other_Alphabetic", Var, 0}, - {"Other_Default_Ignorable_Code_Point", Var, 0}, - {"Other_Grapheme_Extend", Var, 0}, - {"Other_ID_Continue", Var, 0}, - {"Other_ID_Start", Var, 0}, - {"Other_Lowercase", Var, 0}, - {"Other_Math", Var, 0}, - {"Other_Uppercase", Var, 0}, - {"P", Var, 0}, - {"Pahawh_Hmong", Var, 4}, - {"Palmyrene", Var, 4}, - {"Pattern_Syntax", Var, 0}, - {"Pattern_White_Space", Var, 0}, - {"Pau_Cin_Hau", Var, 4}, - {"Pc", Var, 0}, - {"Pd", Var, 0}, - {"Pe", Var, 0}, - {"Pf", Var, 0}, - {"Phags_Pa", Var, 0}, - {"Phoenician", Var, 0}, - {"Pi", Var, 0}, - {"Po", Var, 0}, - {"Prepended_Concatenation_Mark", Var, 7}, - {"PrintRanges", Var, 0}, - {"Properties", Var, 0}, - {"Ps", Var, 0}, - {"Psalter_Pahlavi", Var, 4}, - {"Punct", Var, 0}, - {"Quotation_Mark", Var, 0}, - {"Radical", Var, 0}, - {"Range16", Type, 0}, - {"Range16.Hi", Field, 0}, - {"Range16.Lo", Field, 0}, - {"Range16.Stride", Field, 0}, - {"Range32", Type, 0}, - {"Range32.Hi", Field, 0}, - {"Range32.Lo", Field, 0}, - {"Range32.Stride", Field, 0}, - {"RangeTable", Type, 0}, - {"RangeTable.LatinOffset", Field, 1}, - {"RangeTable.R16", Field, 0}, - {"RangeTable.R32", Field, 0}, - {"Regional_Indicator", Var, 10}, - {"Rejang", Var, 0}, - {"ReplacementChar", Const, 0}, - {"Runic", Var, 0}, - {"S", Var, 0}, - {"STerm", Var, 0}, - {"Samaritan", Var, 0}, - {"Saurashtra", Var, 0}, - {"Sc", Var, 0}, - {"Scripts", Var, 0}, - {"Sentence_Terminal", Var, 7}, - {"Sharada", Var, 1}, - {"Shavian", Var, 0}, - {"Siddham", Var, 4}, - {"SignWriting", Var, 5}, - {"SimpleFold", Func, 0}, - {"Sinhala", Var, 0}, - {"Sk", Var, 0}, - {"Sm", Var, 0}, - {"So", Var, 0}, - {"Soft_Dotted", Var, 0}, - {"Sogdian", Var, 13}, - {"Sora_Sompeng", Var, 1}, - {"Soyombo", Var, 10}, - {"Space", Var, 0}, - {"SpecialCase", Type, 0}, - {"Sundanese", Var, 0}, - {"Syloti_Nagri", Var, 0}, - {"Symbol", Var, 0}, - {"Syriac", Var, 0}, - {"Tagalog", Var, 0}, - {"Tagbanwa", Var, 0}, - {"Tai_Le", Var, 0}, - {"Tai_Tham", Var, 0}, - {"Tai_Viet", Var, 0}, - {"Takri", Var, 1}, - {"Tamil", Var, 0}, - {"Tangsa", Var, 21}, - {"Tangut", Var, 7}, - {"Telugu", Var, 0}, - {"Terminal_Punctuation", Var, 0}, - {"Thaana", Var, 0}, - {"Thai", Var, 0}, - {"Tibetan", Var, 0}, - {"Tifinagh", Var, 0}, - {"Tirhuta", Var, 4}, - {"Title", Var, 0}, - {"TitleCase", Const, 0}, - {"To", Func, 0}, - {"ToLower", Func, 0}, - {"ToTitle", Func, 0}, - {"ToUpper", Func, 0}, - {"Toto", Var, 21}, - {"TurkishCase", Var, 0}, - {"Ugaritic", Var, 0}, - {"Unified_Ideograph", Var, 0}, - {"Upper", Var, 0}, - {"UpperCase", Const, 0}, - {"UpperLower", Const, 0}, - {"Vai", Var, 0}, - {"Variation_Selector", Var, 0}, - {"Version", Const, 0}, - {"Vithkuqi", Var, 21}, - {"Wancho", Var, 14}, - {"Warang_Citi", Var, 4}, - {"White_Space", Var, 0}, - {"Yezidi", Var, 16}, - {"Yi", Var, 0}, - {"Z", Var, 0}, - {"Zanabazar_Square", Var, 10}, - {"Zl", Var, 0}, - {"Zp", Var, 0}, - {"Zs", Var, 0}, + {"(SpecialCase).ToLower", Method, 0, ""}, + {"(SpecialCase).ToTitle", Method, 0, ""}, + {"(SpecialCase).ToUpper", Method, 0, ""}, + {"ASCII_Hex_Digit", Var, 0, ""}, + {"Adlam", Var, 7, ""}, + {"Ahom", Var, 5, ""}, + {"Anatolian_Hieroglyphs", Var, 5, ""}, + {"Arabic", Var, 0, ""}, + {"Armenian", Var, 0, ""}, + {"Avestan", Var, 0, ""}, + {"AzeriCase", Var, 0, ""}, + {"Balinese", Var, 0, ""}, + {"Bamum", Var, 0, ""}, + {"Bassa_Vah", Var, 4, ""}, + {"Batak", Var, 0, ""}, + {"Bengali", Var, 0, ""}, + {"Bhaiksuki", Var, 7, ""}, + {"Bidi_Control", Var, 0, ""}, + {"Bopomofo", Var, 0, ""}, + {"Brahmi", Var, 0, ""}, + {"Braille", Var, 0, ""}, + {"Buginese", Var, 0, ""}, + {"Buhid", Var, 0, ""}, + {"C", Var, 0, ""}, + {"Canadian_Aboriginal", Var, 0, ""}, + {"Carian", Var, 0, ""}, + {"CaseRange", Type, 0, ""}, + {"CaseRange.Delta", Field, 0, ""}, + {"CaseRange.Hi", Field, 0, ""}, + {"CaseRange.Lo", Field, 0, ""}, + {"CaseRanges", Var, 0, ""}, + {"Categories", Var, 0, ""}, + {"Caucasian_Albanian", Var, 4, ""}, + {"Cc", Var, 0, ""}, + {"Cf", Var, 0, ""}, + {"Chakma", Var, 1, ""}, + {"Cham", Var, 0, ""}, + {"Cherokee", Var, 0, ""}, + {"Chorasmian", Var, 16, ""}, + {"Co", Var, 0, ""}, + {"Common", Var, 0, ""}, + {"Coptic", Var, 0, ""}, + {"Cs", Var, 0, ""}, + {"Cuneiform", Var, 0, ""}, + {"Cypriot", Var, 0, ""}, + {"Cypro_Minoan", Var, 21, ""}, + {"Cyrillic", Var, 0, ""}, + {"Dash", Var, 0, ""}, + {"Deprecated", Var, 0, ""}, + {"Deseret", Var, 0, ""}, + {"Devanagari", Var, 0, ""}, + {"Diacritic", Var, 0, ""}, + {"Digit", Var, 0, ""}, + {"Dives_Akuru", Var, 16, ""}, + {"Dogra", Var, 13, ""}, + {"Duployan", Var, 4, ""}, + {"Egyptian_Hieroglyphs", Var, 0, ""}, + {"Elbasan", Var, 4, ""}, + {"Elymaic", Var, 14, ""}, + {"Ethiopic", Var, 0, ""}, + {"Extender", Var, 0, ""}, + {"FoldCategory", Var, 0, ""}, + {"FoldScript", Var, 0, ""}, + {"Georgian", Var, 0, ""}, + {"Glagolitic", Var, 0, ""}, + {"Gothic", Var, 0, ""}, + {"Grantha", Var, 4, ""}, + {"GraphicRanges", Var, 0, ""}, + {"Greek", Var, 0, ""}, + {"Gujarati", Var, 0, ""}, + {"Gunjala_Gondi", Var, 13, ""}, + {"Gurmukhi", Var, 0, ""}, + {"Han", Var, 0, ""}, + {"Hangul", Var, 0, ""}, + {"Hanifi_Rohingya", Var, 13, ""}, + {"Hanunoo", Var, 0, ""}, + {"Hatran", Var, 5, ""}, + {"Hebrew", Var, 0, ""}, + {"Hex_Digit", Var, 0, ""}, + {"Hiragana", Var, 0, ""}, + {"Hyphen", Var, 0, ""}, + {"IDS_Binary_Operator", Var, 0, ""}, + {"IDS_Trinary_Operator", Var, 0, ""}, + {"Ideographic", Var, 0, ""}, + {"Imperial_Aramaic", Var, 0, ""}, + {"In", Func, 2, "func(r rune, ranges ...*RangeTable) bool"}, + {"Inherited", Var, 0, ""}, + {"Inscriptional_Pahlavi", Var, 0, ""}, + {"Inscriptional_Parthian", Var, 0, ""}, + {"Is", Func, 0, "func(rangeTab *RangeTable, r rune) bool"}, + {"IsControl", Func, 0, "func(r rune) bool"}, + {"IsDigit", Func, 0, "func(r rune) bool"}, + {"IsGraphic", Func, 0, "func(r rune) bool"}, + {"IsLetter", Func, 0, "func(r rune) bool"}, + {"IsLower", Func, 0, "func(r rune) bool"}, + {"IsMark", Func, 0, "func(r rune) bool"}, + {"IsNumber", Func, 0, "func(r rune) bool"}, + {"IsOneOf", Func, 0, "func(ranges []*RangeTable, r rune) bool"}, + {"IsPrint", Func, 0, "func(r rune) bool"}, + {"IsPunct", Func, 0, "func(r rune) bool"}, + {"IsSpace", Func, 0, "func(r rune) bool"}, + {"IsSymbol", Func, 0, "func(r rune) bool"}, + {"IsTitle", Func, 0, "func(r rune) bool"}, + {"IsUpper", Func, 0, "func(r rune) bool"}, + {"Javanese", Var, 0, ""}, + {"Join_Control", Var, 0, ""}, + {"Kaithi", Var, 0, ""}, + {"Kannada", Var, 0, ""}, + {"Katakana", Var, 0, ""}, + {"Kawi", Var, 21, ""}, + {"Kayah_Li", Var, 0, ""}, + {"Kharoshthi", Var, 0, ""}, + {"Khitan_Small_Script", Var, 16, ""}, + {"Khmer", Var, 0, ""}, + {"Khojki", Var, 4, ""}, + {"Khudawadi", Var, 4, ""}, + {"L", Var, 0, ""}, + {"Lao", Var, 0, ""}, + {"Latin", Var, 0, ""}, + {"Lepcha", Var, 0, ""}, + {"Letter", Var, 0, ""}, + {"Limbu", Var, 0, ""}, + {"Linear_A", Var, 4, ""}, + {"Linear_B", Var, 0, ""}, + {"Lisu", Var, 0, ""}, + {"Ll", Var, 0, ""}, + {"Lm", Var, 0, ""}, + {"Lo", Var, 0, ""}, + {"Logical_Order_Exception", Var, 0, ""}, + {"Lower", Var, 0, ""}, + {"LowerCase", Const, 0, ""}, + {"Lt", Var, 0, ""}, + {"Lu", Var, 0, ""}, + {"Lycian", Var, 0, ""}, + {"Lydian", Var, 0, ""}, + {"M", Var, 0, ""}, + {"Mahajani", Var, 4, ""}, + {"Makasar", Var, 13, ""}, + {"Malayalam", Var, 0, ""}, + {"Mandaic", Var, 0, ""}, + {"Manichaean", Var, 4, ""}, + {"Marchen", Var, 7, ""}, + {"Mark", Var, 0, ""}, + {"Masaram_Gondi", Var, 10, ""}, + {"MaxASCII", Const, 0, ""}, + {"MaxCase", Const, 0, ""}, + {"MaxLatin1", Const, 0, ""}, + {"MaxRune", Const, 0, ""}, + {"Mc", Var, 0, ""}, + {"Me", Var, 0, ""}, + {"Medefaidrin", Var, 13, ""}, + {"Meetei_Mayek", Var, 0, ""}, + {"Mende_Kikakui", Var, 4, ""}, + {"Meroitic_Cursive", Var, 1, ""}, + {"Meroitic_Hieroglyphs", Var, 1, ""}, + {"Miao", Var, 1, ""}, + {"Mn", Var, 0, ""}, + {"Modi", Var, 4, ""}, + {"Mongolian", Var, 0, ""}, + {"Mro", Var, 4, ""}, + {"Multani", Var, 5, ""}, + {"Myanmar", Var, 0, ""}, + {"N", Var, 0, ""}, + {"Nabataean", Var, 4, ""}, + {"Nag_Mundari", Var, 21, ""}, + {"Nandinagari", Var, 14, ""}, + {"Nd", Var, 0, ""}, + {"New_Tai_Lue", Var, 0, ""}, + {"Newa", Var, 7, ""}, + {"Nko", Var, 0, ""}, + {"Nl", Var, 0, ""}, + {"No", Var, 0, ""}, + {"Noncharacter_Code_Point", Var, 0, ""}, + {"Number", Var, 0, ""}, + {"Nushu", Var, 10, ""}, + {"Nyiakeng_Puachue_Hmong", Var, 14, ""}, + {"Ogham", Var, 0, ""}, + {"Ol_Chiki", Var, 0, ""}, + {"Old_Hungarian", Var, 5, ""}, + {"Old_Italic", Var, 0, ""}, + {"Old_North_Arabian", Var, 4, ""}, + {"Old_Permic", Var, 4, ""}, + {"Old_Persian", Var, 0, ""}, + {"Old_Sogdian", Var, 13, ""}, + {"Old_South_Arabian", Var, 0, ""}, + {"Old_Turkic", Var, 0, ""}, + {"Old_Uyghur", Var, 21, ""}, + {"Oriya", Var, 0, ""}, + {"Osage", Var, 7, ""}, + {"Osmanya", Var, 0, ""}, + {"Other", Var, 0, ""}, + {"Other_Alphabetic", Var, 0, ""}, + {"Other_Default_Ignorable_Code_Point", Var, 0, ""}, + {"Other_Grapheme_Extend", Var, 0, ""}, + {"Other_ID_Continue", Var, 0, ""}, + {"Other_ID_Start", Var, 0, ""}, + {"Other_Lowercase", Var, 0, ""}, + {"Other_Math", Var, 0, ""}, + {"Other_Uppercase", Var, 0, ""}, + {"P", Var, 0, ""}, + {"Pahawh_Hmong", Var, 4, ""}, + {"Palmyrene", Var, 4, ""}, + {"Pattern_Syntax", Var, 0, ""}, + {"Pattern_White_Space", Var, 0, ""}, + {"Pau_Cin_Hau", Var, 4, ""}, + {"Pc", Var, 0, ""}, + {"Pd", Var, 0, ""}, + {"Pe", Var, 0, ""}, + {"Pf", Var, 0, ""}, + {"Phags_Pa", Var, 0, ""}, + {"Phoenician", Var, 0, ""}, + {"Pi", Var, 0, ""}, + {"Po", Var, 0, ""}, + {"Prepended_Concatenation_Mark", Var, 7, ""}, + {"PrintRanges", Var, 0, ""}, + {"Properties", Var, 0, ""}, + {"Ps", Var, 0, ""}, + {"Psalter_Pahlavi", Var, 4, ""}, + {"Punct", Var, 0, ""}, + {"Quotation_Mark", Var, 0, ""}, + {"Radical", Var, 0, ""}, + {"Range16", Type, 0, ""}, + {"Range16.Hi", Field, 0, ""}, + {"Range16.Lo", Field, 0, ""}, + {"Range16.Stride", Field, 0, ""}, + {"Range32", Type, 0, ""}, + {"Range32.Hi", Field, 0, ""}, + {"Range32.Lo", Field, 0, ""}, + {"Range32.Stride", Field, 0, ""}, + {"RangeTable", Type, 0, ""}, + {"RangeTable.LatinOffset", Field, 1, ""}, + {"RangeTable.R16", Field, 0, ""}, + {"RangeTable.R32", Field, 0, ""}, + {"Regional_Indicator", Var, 10, ""}, + {"Rejang", Var, 0, ""}, + {"ReplacementChar", Const, 0, ""}, + {"Runic", Var, 0, ""}, + {"S", Var, 0, ""}, + {"STerm", Var, 0, ""}, + {"Samaritan", Var, 0, ""}, + {"Saurashtra", Var, 0, ""}, + {"Sc", Var, 0, ""}, + {"Scripts", Var, 0, ""}, + {"Sentence_Terminal", Var, 7, ""}, + {"Sharada", Var, 1, ""}, + {"Shavian", Var, 0, ""}, + {"Siddham", Var, 4, ""}, + {"SignWriting", Var, 5, ""}, + {"SimpleFold", Func, 0, "func(r rune) rune"}, + {"Sinhala", Var, 0, ""}, + {"Sk", Var, 0, ""}, + {"Sm", Var, 0, ""}, + {"So", Var, 0, ""}, + {"Soft_Dotted", Var, 0, ""}, + {"Sogdian", Var, 13, ""}, + {"Sora_Sompeng", Var, 1, ""}, + {"Soyombo", Var, 10, ""}, + {"Space", Var, 0, ""}, + {"SpecialCase", Type, 0, ""}, + {"Sundanese", Var, 0, ""}, + {"Syloti_Nagri", Var, 0, ""}, + {"Symbol", Var, 0, ""}, + {"Syriac", Var, 0, ""}, + {"Tagalog", Var, 0, ""}, + {"Tagbanwa", Var, 0, ""}, + {"Tai_Le", Var, 0, ""}, + {"Tai_Tham", Var, 0, ""}, + {"Tai_Viet", Var, 0, ""}, + {"Takri", Var, 1, ""}, + {"Tamil", Var, 0, ""}, + {"Tangsa", Var, 21, ""}, + {"Tangut", Var, 7, ""}, + {"Telugu", Var, 0, ""}, + {"Terminal_Punctuation", Var, 0, ""}, + {"Thaana", Var, 0, ""}, + {"Thai", Var, 0, ""}, + {"Tibetan", Var, 0, ""}, + {"Tifinagh", Var, 0, ""}, + {"Tirhuta", Var, 4, ""}, + {"Title", Var, 0, ""}, + {"TitleCase", Const, 0, ""}, + {"To", Func, 0, "func(_case int, r rune) rune"}, + {"ToLower", Func, 0, "func(r rune) rune"}, + {"ToTitle", Func, 0, "func(r rune) rune"}, + {"ToUpper", Func, 0, "func(r rune) rune"}, + {"Toto", Var, 21, ""}, + {"TurkishCase", Var, 0, ""}, + {"Ugaritic", Var, 0, ""}, + {"Unified_Ideograph", Var, 0, ""}, + {"Upper", Var, 0, ""}, + {"UpperCase", Const, 0, ""}, + {"UpperLower", Const, 0, ""}, + {"Vai", Var, 0, ""}, + {"Variation_Selector", Var, 0, ""}, + {"Version", Const, 0, ""}, + {"Vithkuqi", Var, 21, ""}, + {"Wancho", Var, 14, ""}, + {"Warang_Citi", Var, 4, ""}, + {"White_Space", Var, 0, ""}, + {"Yezidi", Var, 16, ""}, + {"Yi", Var, 0, ""}, + {"Z", Var, 0, ""}, + {"Zanabazar_Square", Var, 10, ""}, + {"Zl", Var, 0, ""}, + {"Zp", Var, 0, ""}, + {"Zs", Var, 0, ""}, }, "unicode/utf16": { - {"AppendRune", Func, 20}, - {"Decode", Func, 0}, - {"DecodeRune", Func, 0}, - {"Encode", Func, 0}, - {"EncodeRune", Func, 0}, - {"IsSurrogate", Func, 0}, - {"RuneLen", Func, 23}, + {"AppendRune", Func, 20, "func(a []uint16, r rune) []uint16"}, + {"Decode", Func, 0, "func(s []uint16) []rune"}, + {"DecodeRune", Func, 0, "func(r1 rune, r2 rune) rune"}, + {"Encode", Func, 0, "func(s []rune) []uint16"}, + {"EncodeRune", Func, 0, "func(r rune) (r1 rune, r2 rune)"}, + {"IsSurrogate", Func, 0, "func(r rune) bool"}, + {"RuneLen", Func, 23, "func(r rune) int"}, }, "unicode/utf8": { - {"AppendRune", Func, 18}, - {"DecodeLastRune", Func, 0}, - {"DecodeLastRuneInString", Func, 0}, - {"DecodeRune", Func, 0}, - {"DecodeRuneInString", Func, 0}, - {"EncodeRune", Func, 0}, - {"FullRune", Func, 0}, - {"FullRuneInString", Func, 0}, - {"MaxRune", Const, 0}, - {"RuneCount", Func, 0}, - {"RuneCountInString", Func, 0}, - {"RuneError", Const, 0}, - {"RuneLen", Func, 0}, - {"RuneSelf", Const, 0}, - {"RuneStart", Func, 0}, - {"UTFMax", Const, 0}, - {"Valid", Func, 0}, - {"ValidRune", Func, 1}, - {"ValidString", Func, 0}, + {"AppendRune", Func, 18, "func(p []byte, r rune) []byte"}, + {"DecodeLastRune", Func, 0, "func(p []byte) (r rune, size int)"}, + {"DecodeLastRuneInString", Func, 0, "func(s string) (r rune, size int)"}, + {"DecodeRune", Func, 0, "func(p []byte) (r rune, size int)"}, + {"DecodeRuneInString", Func, 0, "func(s string) (r rune, size int)"}, + {"EncodeRune", Func, 0, "func(p []byte, r rune) int"}, + {"FullRune", Func, 0, "func(p []byte) bool"}, + {"FullRuneInString", Func, 0, "func(s string) bool"}, + {"MaxRune", Const, 0, ""}, + {"RuneCount", Func, 0, "func(p []byte) int"}, + {"RuneCountInString", Func, 0, "func(s string) (n int)"}, + {"RuneError", Const, 0, ""}, + {"RuneLen", Func, 0, "func(r rune) int"}, + {"RuneSelf", Const, 0, ""}, + {"RuneStart", Func, 0, "func(b byte) bool"}, + {"UTFMax", Const, 0, ""}, + {"Valid", Func, 0, "func(p []byte) bool"}, + {"ValidRune", Func, 1, "func(r rune) bool"}, + {"ValidString", Func, 0, "func(s string) bool"}, }, "unique": { - {"(Handle).Value", Method, 23}, - {"Handle", Type, 23}, - {"Make", Func, 23}, + {"(Handle).Value", Method, 23, ""}, + {"Handle", Type, 23, ""}, + {"Make", Func, 23, "func[T comparable](value T) Handle[T]"}, }, "unsafe": { - {"Add", Func, 0}, - {"Alignof", Func, 0}, - {"Offsetof", Func, 0}, - {"Pointer", Type, 0}, - {"Sizeof", Func, 0}, - {"Slice", Func, 0}, - {"SliceData", Func, 0}, - {"String", Func, 0}, - {"StringData", Func, 0}, + {"Add", Func, 0, ""}, + {"Alignof", Func, 0, ""}, + {"Offsetof", Func, 0, ""}, + {"Pointer", Type, 0, ""}, + {"Sizeof", Func, 0, ""}, + {"Slice", Func, 0, ""}, + {"SliceData", Func, 0, ""}, + {"String", Func, 0, ""}, + {"StringData", Func, 0, ""}, }, "weak": { - {"(Pointer).Value", Method, 24}, - {"Make", Func, 24}, - {"Pointer", Type, 24}, + {"(Pointer).Value", Method, 24, ""}, + {"Make", Func, 24, "func[T any](ptr *T) Pointer[T]"}, + {"Pointer", Type, 24, ""}, }, } go_8623503fe54642a21854c551129d550139f3bbac_src_cmd_compile_internal_gc_testdata_arithConst.go.test000066400000000000000000107725061516001707200367060ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit 8623503fe54642a21854c551129d550139f3bbac file src/cmd/compile/internal/gc/testdata/arithConst.go -- x -- // run // Code generated by gen/arithConstGen.go. DO NOT EDIT. package main import "fmt" //go:noinline func add_uint64_0_ssa(a uint64) uint64 { return a + 0 } //go:noinline func add_0_uint64_ssa(a uint64) uint64 { return 0 + a } //go:noinline func add_uint64_1_ssa(a uint64) uint64 { return a + 1 } //go:noinline func add_1_uint64_ssa(a uint64) uint64 { return 1 + a } //go:noinline func add_uint64_4294967296_ssa(a uint64) uint64 { return a + 4294967296 } //go:noinline func add_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 + a } //go:noinline func add_uint64_9223372036854775808_ssa(a uint64) uint64 { return a + 9223372036854775808 } //go:noinline func add_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 + a } //go:noinline func add_uint64_18446744073709551615_ssa(a uint64) uint64 { return a + 18446744073709551615 } //go:noinline func add_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 + a } //go:noinline func sub_uint64_0_ssa(a uint64) uint64 { return a - 0 } //go:noinline func sub_0_uint64_ssa(a uint64) uint64 { return 0 - a } //go:noinline func sub_uint64_1_ssa(a uint64) uint64 { return a - 1 } //go:noinline func sub_1_uint64_ssa(a uint64) uint64 { return 1 - a } //go:noinline func sub_uint64_4294967296_ssa(a uint64) uint64 { return a - 4294967296 } //go:noinline func sub_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 - a } //go:noinline func sub_uint64_9223372036854775808_ssa(a uint64) uint64 { return a - 9223372036854775808 } //go:noinline func sub_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 - a } //go:noinline func sub_uint64_18446744073709551615_ssa(a uint64) uint64 { return a - 18446744073709551615 } //go:noinline func sub_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 - a } //go:noinline func div_0_uint64_ssa(a uint64) uint64 { return 0 / a } //go:noinline func div_uint64_1_ssa(a uint64) uint64 { return a / 1 } //go:noinline func div_1_uint64_ssa(a uint64) uint64 { return 1 / a } //go:noinline func div_uint64_4294967296_ssa(a uint64) uint64 { return a / 4294967296 } //go:noinline func div_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 / a } //go:noinline func div_uint64_9223372036854775808_ssa(a uint64) uint64 { return a / 9223372036854775808 } //go:noinline func div_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 / a } //go:noinline func div_uint64_18446744073709551615_ssa(a uint64) uint64 { return a / 18446744073709551615 } //go:noinline func div_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 / a } //go:noinline func mul_uint64_0_ssa(a uint64) uint64 { return a * 0 } //go:noinline func mul_0_uint64_ssa(a uint64) uint64 { return 0 * a } //go:noinline func mul_uint64_1_ssa(a uint64) uint64 { return a * 1 } //go:noinline func mul_1_uint64_ssa(a uint64) uint64 { return 1 * a } //go:noinline func mul_uint64_4294967296_ssa(a uint64) uint64 { return a * 4294967296 } //go:noinline func mul_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 * a } //go:noinline func mul_uint64_9223372036854775808_ssa(a uint64) uint64 { return a * 9223372036854775808 } //go:noinline func mul_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 * a } //go:noinline func mul_uint64_18446744073709551615_ssa(a uint64) uint64 { return a * 18446744073709551615 } //go:noinline func mul_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 * a } //go:noinline func lsh_uint64_0_ssa(a uint64) uint64 { return a << 0 } //go:noinline func lsh_0_uint64_ssa(a uint64) uint64 { return 0 << a } //go:noinline func lsh_uint64_1_ssa(a uint64) uint64 { return a << 1 } //go:noinline func lsh_1_uint64_ssa(a uint64) uint64 { return 1 << a } //go:noinline func lsh_uint64_4294967296_ssa(a uint64) uint64 { return a << uint64(4294967296) } //go:noinline func lsh_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 << a } //go:noinline func lsh_uint64_9223372036854775808_ssa(a uint64) uint64 { return a << uint64(9223372036854775808) } //go:noinline func lsh_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 << a } //go:noinline func lsh_uint64_18446744073709551615_ssa(a uint64) uint64 { return a << uint64(18446744073709551615) } //go:noinline func lsh_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 << a } //go:noinline func rsh_uint64_0_ssa(a uint64) uint64 { return a >> 0 } //go:noinline func rsh_0_uint64_ssa(a uint64) uint64 { return 0 >> a } //go:noinline func rsh_uint64_1_ssa(a uint64) uint64 { return a >> 1 } //go:noinline func rsh_1_uint64_ssa(a uint64) uint64 { return 1 >> a } //go:noinline func rsh_uint64_4294967296_ssa(a uint64) uint64 { return a >> uint64(4294967296) } //go:noinline func rsh_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 >> a } //go:noinline func rsh_uint64_9223372036854775808_ssa(a uint64) uint64 { return a >> uint64(9223372036854775808) } //go:noinline func rsh_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 >> a } //go:noinline func rsh_uint64_18446744073709551615_ssa(a uint64) uint64 { return a >> uint64(18446744073709551615) } //go:noinline func rsh_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 >> a } //go:noinline func mod_0_uint64_ssa(a uint64) uint64 { return 0 % a } //go:noinline func mod_uint64_1_ssa(a uint64) uint64 { return a % 1 } //go:noinline func mod_1_uint64_ssa(a uint64) uint64 { return 1 % a } //go:noinline func mod_uint64_4294967296_ssa(a uint64) uint64 { return a % 4294967296 } //go:noinline func mod_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 % a } //go:noinline func mod_uint64_9223372036854775808_ssa(a uint64) uint64 { return a % 9223372036854775808 } //go:noinline func mod_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 % a } //go:noinline func mod_uint64_18446744073709551615_ssa(a uint64) uint64 { return a % 18446744073709551615 } //go:noinline func mod_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 % a } //go:noinline func and_uint64_0_ssa(a uint64) uint64 { return a & 0 } //go:noinline func and_0_uint64_ssa(a uint64) uint64 { return 0 & a } //go:noinline func and_uint64_1_ssa(a uint64) uint64 { return a & 1 } //go:noinline func and_1_uint64_ssa(a uint64) uint64 { return 1 & a } //go:noinline func and_uint64_4294967296_ssa(a uint64) uint64 { return a & 4294967296 } //go:noinline func and_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 & a } //go:noinline func and_uint64_9223372036854775808_ssa(a uint64) uint64 { return a & 9223372036854775808 } //go:noinline func and_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 & a } //go:noinline func and_uint64_18446744073709551615_ssa(a uint64) uint64 { return a & 18446744073709551615 } //go:noinline func and_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 & a } //go:noinline func or_uint64_0_ssa(a uint64) uint64 { return a | 0 } //go:noinline func or_0_uint64_ssa(a uint64) uint64 { return 0 | a } //go:noinline func or_uint64_1_ssa(a uint64) uint64 { return a | 1 } //go:noinline func or_1_uint64_ssa(a uint64) uint64 { return 1 | a } //go:noinline func or_uint64_4294967296_ssa(a uint64) uint64 { return a | 4294967296 } //go:noinline func or_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 | a } //go:noinline func or_uint64_9223372036854775808_ssa(a uint64) uint64 { return a | 9223372036854775808 } //go:noinline func or_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 | a } //go:noinline func or_uint64_18446744073709551615_ssa(a uint64) uint64 { return a | 18446744073709551615 } //go:noinline func or_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 | a } //go:noinline func xor_uint64_0_ssa(a uint64) uint64 { return a ^ 0 } //go:noinline func xor_0_uint64_ssa(a uint64) uint64 { return 0 ^ a } //go:noinline func xor_uint64_1_ssa(a uint64) uint64 { return a ^ 1 } //go:noinline func xor_1_uint64_ssa(a uint64) uint64 { return 1 ^ a } //go:noinline func xor_uint64_4294967296_ssa(a uint64) uint64 { return a ^ 4294967296 } //go:noinline func xor_4294967296_uint64_ssa(a uint64) uint64 { return 4294967296 ^ a } //go:noinline func xor_uint64_9223372036854775808_ssa(a uint64) uint64 { return a ^ 9223372036854775808 } //go:noinline func xor_9223372036854775808_uint64_ssa(a uint64) uint64 { return 9223372036854775808 ^ a } //go:noinline func xor_uint64_18446744073709551615_ssa(a uint64) uint64 { return a ^ 18446744073709551615 } //go:noinline func xor_18446744073709551615_uint64_ssa(a uint64) uint64 { return 18446744073709551615 ^ a } //go:noinline func add_int64_Neg9223372036854775808_ssa(a int64) int64 { return a + -9223372036854775808 } //go:noinline func add_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 + a } //go:noinline func add_int64_Neg9223372036854775807_ssa(a int64) int64 { return a + -9223372036854775807 } //go:noinline func add_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 + a } //go:noinline func add_int64_Neg4294967296_ssa(a int64) int64 { return a + -4294967296 } //go:noinline func add_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 + a } //go:noinline func add_int64_Neg1_ssa(a int64) int64 { return a + -1 } //go:noinline func add_Neg1_int64_ssa(a int64) int64 { return -1 + a } //go:noinline func add_int64_0_ssa(a int64) int64 { return a + 0 } //go:noinline func add_0_int64_ssa(a int64) int64 { return 0 + a } //go:noinline func add_int64_1_ssa(a int64) int64 { return a + 1 } //go:noinline func add_1_int64_ssa(a int64) int64 { return 1 + a } //go:noinline func add_int64_4294967296_ssa(a int64) int64 { return a + 4294967296 } //go:noinline func add_4294967296_int64_ssa(a int64) int64 { return 4294967296 + a } //go:noinline func add_int64_9223372036854775806_ssa(a int64) int64 { return a + 9223372036854775806 } //go:noinline func add_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 + a } //go:noinline func add_int64_9223372036854775807_ssa(a int64) int64 { return a + 9223372036854775807 } //go:noinline func add_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 + a } //go:noinline func sub_int64_Neg9223372036854775808_ssa(a int64) int64 { return a - -9223372036854775808 } //go:noinline func sub_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 - a } //go:noinline func sub_int64_Neg9223372036854775807_ssa(a int64) int64 { return a - -9223372036854775807 } //go:noinline func sub_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 - a } //go:noinline func sub_int64_Neg4294967296_ssa(a int64) int64 { return a - -4294967296 } //go:noinline func sub_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 - a } //go:noinline func sub_int64_Neg1_ssa(a int64) int64 { return a - -1 } //go:noinline func sub_Neg1_int64_ssa(a int64) int64 { return -1 - a } //go:noinline func sub_int64_0_ssa(a int64) int64 { return a - 0 } //go:noinline func sub_0_int64_ssa(a int64) int64 { return 0 - a } //go:noinline func sub_int64_1_ssa(a int64) int64 { return a - 1 } //go:noinline func sub_1_int64_ssa(a int64) int64 { return 1 - a } //go:noinline func sub_int64_4294967296_ssa(a int64) int64 { return a - 4294967296 } //go:noinline func sub_4294967296_int64_ssa(a int64) int64 { return 4294967296 - a } //go:noinline func sub_int64_9223372036854775806_ssa(a int64) int64 { return a - 9223372036854775806 } //go:noinline func sub_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 - a } //go:noinline func sub_int64_9223372036854775807_ssa(a int64) int64 { return a - 9223372036854775807 } //go:noinline func sub_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 - a } //go:noinline func div_int64_Neg9223372036854775808_ssa(a int64) int64 { return a / -9223372036854775808 } //go:noinline func div_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 / a } //go:noinline func div_int64_Neg9223372036854775807_ssa(a int64) int64 { return a / -9223372036854775807 } //go:noinline func div_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 / a } //go:noinline func div_int64_Neg4294967296_ssa(a int64) int64 { return a / -4294967296 } //go:noinline func div_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 / a } //go:noinline func div_int64_Neg1_ssa(a int64) int64 { return a / -1 } //go:noinline func div_Neg1_int64_ssa(a int64) int64 { return -1 / a } //go:noinline func div_0_int64_ssa(a int64) int64 { return 0 / a } //go:noinline func div_int64_1_ssa(a int64) int64 { return a / 1 } //go:noinline func div_1_int64_ssa(a int64) int64 { return 1 / a } //go:noinline func div_int64_4294967296_ssa(a int64) int64 { return a / 4294967296 } //go:noinline func div_4294967296_int64_ssa(a int64) int64 { return 4294967296 / a } //go:noinline func div_int64_9223372036854775806_ssa(a int64) int64 { return a / 9223372036854775806 } //go:noinline func div_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 / a } //go:noinline func div_int64_9223372036854775807_ssa(a int64) int64 { return a / 9223372036854775807 } //go:noinline func div_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 / a } //go:noinline func mul_int64_Neg9223372036854775808_ssa(a int64) int64 { return a * -9223372036854775808 } //go:noinline func mul_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 * a } //go:noinline func mul_int64_Neg9223372036854775807_ssa(a int64) int64 { return a * -9223372036854775807 } //go:noinline func mul_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 * a } //go:noinline func mul_int64_Neg4294967296_ssa(a int64) int64 { return a * -4294967296 } //go:noinline func mul_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 * a } //go:noinline func mul_int64_Neg1_ssa(a int64) int64 { return a * -1 } //go:noinline func mul_Neg1_int64_ssa(a int64) int64 { return -1 * a } //go:noinline func mul_int64_0_ssa(a int64) int64 { return a * 0 } //go:noinline func mul_0_int64_ssa(a int64) int64 { return 0 * a } //go:noinline func mul_int64_1_ssa(a int64) int64 { return a * 1 } //go:noinline func mul_1_int64_ssa(a int64) int64 { return 1 * a } //go:noinline func mul_int64_4294967296_ssa(a int64) int64 { return a * 4294967296 } //go:noinline func mul_4294967296_int64_ssa(a int64) int64 { return 4294967296 * a } //go:noinline func mul_int64_9223372036854775806_ssa(a int64) int64 { return a * 9223372036854775806 } //go:noinline func mul_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 * a } //go:noinline func mul_int64_9223372036854775807_ssa(a int64) int64 { return a * 9223372036854775807 } //go:noinline func mul_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 * a } //go:noinline func mod_int64_Neg9223372036854775808_ssa(a int64) int64 { return a % -9223372036854775808 } //go:noinline func mod_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 % a } //go:noinline func mod_int64_Neg9223372036854775807_ssa(a int64) int64 { return a % -9223372036854775807 } //go:noinline func mod_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 % a } //go:noinline func mod_int64_Neg4294967296_ssa(a int64) int64 { return a % -4294967296 } //go:noinline func mod_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 % a } //go:noinline func mod_int64_Neg1_ssa(a int64) int64 { return a % -1 } //go:noinline func mod_Neg1_int64_ssa(a int64) int64 { return -1 % a } //go:noinline func mod_0_int64_ssa(a int64) int64 { return 0 % a } //go:noinline func mod_int64_1_ssa(a int64) int64 { return a % 1 } //go:noinline func mod_1_int64_ssa(a int64) int64 { return 1 % a } //go:noinline func mod_int64_4294967296_ssa(a int64) int64 { return a % 4294967296 } //go:noinline func mod_4294967296_int64_ssa(a int64) int64 { return 4294967296 % a } //go:noinline func mod_int64_9223372036854775806_ssa(a int64) int64 { return a % 9223372036854775806 } //go:noinline func mod_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 % a } //go:noinline func mod_int64_9223372036854775807_ssa(a int64) int64 { return a % 9223372036854775807 } //go:noinline func mod_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 % a } //go:noinline func and_int64_Neg9223372036854775808_ssa(a int64) int64 { return a & -9223372036854775808 } //go:noinline func and_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 & a } //go:noinline func and_int64_Neg9223372036854775807_ssa(a int64) int64 { return a & -9223372036854775807 } //go:noinline func and_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 & a } //go:noinline func and_int64_Neg4294967296_ssa(a int64) int64 { return a & -4294967296 } //go:noinline func and_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 & a } //go:noinline func and_int64_Neg1_ssa(a int64) int64 { return a & -1 } //go:noinline func and_Neg1_int64_ssa(a int64) int64 { return -1 & a } //go:noinline func and_int64_0_ssa(a int64) int64 { return a & 0 } //go:noinline func and_0_int64_ssa(a int64) int64 { return 0 & a } //go:noinline func and_int64_1_ssa(a int64) int64 { return a & 1 } //go:noinline func and_1_int64_ssa(a int64) int64 { return 1 & a } //go:noinline func and_int64_4294967296_ssa(a int64) int64 { return a & 4294967296 } //go:noinline func and_4294967296_int64_ssa(a int64) int64 { return 4294967296 & a } //go:noinline func and_int64_9223372036854775806_ssa(a int64) int64 { return a & 9223372036854775806 } //go:noinline func and_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 & a } //go:noinline func and_int64_9223372036854775807_ssa(a int64) int64 { return a & 9223372036854775807 } //go:noinline func and_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 & a } //go:noinline func or_int64_Neg9223372036854775808_ssa(a int64) int64 { return a | -9223372036854775808 } //go:noinline func or_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 | a } //go:noinline func or_int64_Neg9223372036854775807_ssa(a int64) int64 { return a | -9223372036854775807 } //go:noinline func or_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 | a } //go:noinline func or_int64_Neg4294967296_ssa(a int64) int64 { return a | -4294967296 } //go:noinline func or_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 | a } //go:noinline func or_int64_Neg1_ssa(a int64) int64 { return a | -1 } //go:noinline func or_Neg1_int64_ssa(a int64) int64 { return -1 | a } //go:noinline func or_int64_0_ssa(a int64) int64 { return a | 0 } //go:noinline func or_0_int64_ssa(a int64) int64 { return 0 | a } //go:noinline func or_int64_1_ssa(a int64) int64 { return a | 1 } //go:noinline func or_1_int64_ssa(a int64) int64 { return 1 | a } //go:noinline func or_int64_4294967296_ssa(a int64) int64 { return a | 4294967296 } //go:noinline func or_4294967296_int64_ssa(a int64) int64 { return 4294967296 | a } //go:noinline func or_int64_9223372036854775806_ssa(a int64) int64 { return a | 9223372036854775806 } //go:noinline func or_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 | a } //go:noinline func or_int64_9223372036854775807_ssa(a int64) int64 { return a | 9223372036854775807 } //go:noinline func or_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 | a } //go:noinline func xor_int64_Neg9223372036854775808_ssa(a int64) int64 { return a ^ -9223372036854775808 } //go:noinline func xor_Neg9223372036854775808_int64_ssa(a int64) int64 { return -9223372036854775808 ^ a } //go:noinline func xor_int64_Neg9223372036854775807_ssa(a int64) int64 { return a ^ -9223372036854775807 } //go:noinline func xor_Neg9223372036854775807_int64_ssa(a int64) int64 { return -9223372036854775807 ^ a } //go:noinline func xor_int64_Neg4294967296_ssa(a int64) int64 { return a ^ -4294967296 } //go:noinline func xor_Neg4294967296_int64_ssa(a int64) int64 { return -4294967296 ^ a } //go:noinline func xor_int64_Neg1_ssa(a int64) int64 { return a ^ -1 } //go:noinline func xor_Neg1_int64_ssa(a int64) int64 { return -1 ^ a } //go:noinline func xor_int64_0_ssa(a int64) int64 { return a ^ 0 } //go:noinline func xor_0_int64_ssa(a int64) int64 { return 0 ^ a } //go:noinline func xor_int64_1_ssa(a int64) int64 { return a ^ 1 } //go:noinline func xor_1_int64_ssa(a int64) int64 { return 1 ^ a } //go:noinline func xor_int64_4294967296_ssa(a int64) int64 { return a ^ 4294967296 } //go:noinline func xor_4294967296_int64_ssa(a int64) int64 { return 4294967296 ^ a } //go:noinline func xor_int64_9223372036854775806_ssa(a int64) int64 { return a ^ 9223372036854775806 } //go:noinline func xor_9223372036854775806_int64_ssa(a int64) int64 { return 9223372036854775806 ^ a } //go:noinline func xor_int64_9223372036854775807_ssa(a int64) int64 { return a ^ 9223372036854775807 } //go:noinline func xor_9223372036854775807_int64_ssa(a int64) int64 { return 9223372036854775807 ^ a } //go:noinline func add_uint32_0_ssa(a uint32) uint32 { return a + 0 } //go:noinline func add_0_uint32_ssa(a uint32) uint32 { return 0 + a } //go:noinline func add_uint32_1_ssa(a uint32) uint32 { return a + 1 } //go:noinline func add_1_uint32_ssa(a uint32) uint32 { return 1 + a } //go:noinline func add_uint32_4294967295_ssa(a uint32) uint32 { return a + 4294967295 } //go:noinline func add_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 + a } //go:noinline func sub_uint32_0_ssa(a uint32) uint32 { return a - 0 } //go:noinline func sub_0_uint32_ssa(a uint32) uint32 { return 0 - a } //go:noinline func sub_uint32_1_ssa(a uint32) uint32 { return a - 1 } //go:noinline func sub_1_uint32_ssa(a uint32) uint32 { return 1 - a } //go:noinline func sub_uint32_4294967295_ssa(a uint32) uint32 { return a - 4294967295 } //go:noinline func sub_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 - a } //go:noinline func div_0_uint32_ssa(a uint32) uint32 { return 0 / a } //go:noinline func div_uint32_1_ssa(a uint32) uint32 { return a / 1 } //go:noinline func div_1_uint32_ssa(a uint32) uint32 { return 1 / a } //go:noinline func div_uint32_4294967295_ssa(a uint32) uint32 { return a / 4294967295 } //go:noinline func div_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 / a } //go:noinline func mul_uint32_0_ssa(a uint32) uint32 { return a * 0 } //go:noinline func mul_0_uint32_ssa(a uint32) uint32 { return 0 * a } //go:noinline func mul_uint32_1_ssa(a uint32) uint32 { return a * 1 } //go:noinline func mul_1_uint32_ssa(a uint32) uint32 { return 1 * a } //go:noinline func mul_uint32_4294967295_ssa(a uint32) uint32 { return a * 4294967295 } //go:noinline func mul_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 * a } //go:noinline func lsh_uint32_0_ssa(a uint32) uint32 { return a << 0 } //go:noinline func lsh_0_uint32_ssa(a uint32) uint32 { return 0 << a } //go:noinline func lsh_uint32_1_ssa(a uint32) uint32 { return a << 1 } //go:noinline func lsh_1_uint32_ssa(a uint32) uint32 { return 1 << a } //go:noinline func lsh_uint32_4294967295_ssa(a uint32) uint32 { return a << 4294967295 } //go:noinline func lsh_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 << a } //go:noinline func rsh_uint32_0_ssa(a uint32) uint32 { return a >> 0 } //go:noinline func rsh_0_uint32_ssa(a uint32) uint32 { return 0 >> a } //go:noinline func rsh_uint32_1_ssa(a uint32) uint32 { return a >> 1 } //go:noinline func rsh_1_uint32_ssa(a uint32) uint32 { return 1 >> a } //go:noinline func rsh_uint32_4294967295_ssa(a uint32) uint32 { return a >> 4294967295 } //go:noinline func rsh_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 >> a } //go:noinline func mod_0_uint32_ssa(a uint32) uint32 { return 0 % a } //go:noinline func mod_uint32_1_ssa(a uint32) uint32 { return a % 1 } //go:noinline func mod_1_uint32_ssa(a uint32) uint32 { return 1 % a } //go:noinline func mod_uint32_4294967295_ssa(a uint32) uint32 { return a % 4294967295 } //go:noinline func mod_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 % a } //go:noinline func and_uint32_0_ssa(a uint32) uint32 { return a & 0 } //go:noinline func and_0_uint32_ssa(a uint32) uint32 { return 0 & a } //go:noinline func and_uint32_1_ssa(a uint32) uint32 { return a & 1 } //go:noinline func and_1_uint32_ssa(a uint32) uint32 { return 1 & a } //go:noinline func and_uint32_4294967295_ssa(a uint32) uint32 { return a & 4294967295 } //go:noinline func and_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 & a } //go:noinline func or_uint32_0_ssa(a uint32) uint32 { return a | 0 } //go:noinline func or_0_uint32_ssa(a uint32) uint32 { return 0 | a } //go:noinline func or_uint32_1_ssa(a uint32) uint32 { return a | 1 } //go:noinline func or_1_uint32_ssa(a uint32) uint32 { return 1 | a } //go:noinline func or_uint32_4294967295_ssa(a uint32) uint32 { return a | 4294967295 } //go:noinline func or_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 | a } //go:noinline func xor_uint32_0_ssa(a uint32) uint32 { return a ^ 0 } //go:noinline func xor_0_uint32_ssa(a uint32) uint32 { return 0 ^ a } //go:noinline func xor_uint32_1_ssa(a uint32) uint32 { return a ^ 1 } //go:noinline func xor_1_uint32_ssa(a uint32) uint32 { return 1 ^ a } //go:noinline func xor_uint32_4294967295_ssa(a uint32) uint32 { return a ^ 4294967295 } //go:noinline func xor_4294967295_uint32_ssa(a uint32) uint32 { return 4294967295 ^ a } //go:noinline func add_int32_Neg2147483648_ssa(a int32) int32 { return a + -2147483648 } //go:noinline func add_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 + a } //go:noinline func add_int32_Neg2147483647_ssa(a int32) int32 { return a + -2147483647 } //go:noinline func add_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 + a } //go:noinline func add_int32_Neg1_ssa(a int32) int32 { return a + -1 } //go:noinline func add_Neg1_int32_ssa(a int32) int32 { return -1 + a } //go:noinline func add_int32_0_ssa(a int32) int32 { return a + 0 } //go:noinline func add_0_int32_ssa(a int32) int32 { return 0 + a } //go:noinline func add_int32_1_ssa(a int32) int32 { return a + 1 } //go:noinline func add_1_int32_ssa(a int32) int32 { return 1 + a } //go:noinline func add_int32_2147483647_ssa(a int32) int32 { return a + 2147483647 } //go:noinline func add_2147483647_int32_ssa(a int32) int32 { return 2147483647 + a } //go:noinline func sub_int32_Neg2147483648_ssa(a int32) int32 { return a - -2147483648 } //go:noinline func sub_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 - a } //go:noinline func sub_int32_Neg2147483647_ssa(a int32) int32 { return a - -2147483647 } //go:noinline func sub_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 - a } //go:noinline func sub_int32_Neg1_ssa(a int32) int32 { return a - -1 } //go:noinline func sub_Neg1_int32_ssa(a int32) int32 { return -1 - a } //go:noinline func sub_int32_0_ssa(a int32) int32 { return a - 0 } //go:noinline func sub_0_int32_ssa(a int32) int32 { return 0 - a } //go:noinline func sub_int32_1_ssa(a int32) int32 { return a - 1 } //go:noinline func sub_1_int32_ssa(a int32) int32 { return 1 - a } //go:noinline func sub_int32_2147483647_ssa(a int32) int32 { return a - 2147483647 } //go:noinline func sub_2147483647_int32_ssa(a int32) int32 { return 2147483647 - a } //go:noinline func div_int32_Neg2147483648_ssa(a int32) int32 { return a / -2147483648 } //go:noinline func div_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 / a } //go:noinline func div_int32_Neg2147483647_ssa(a int32) int32 { return a / -2147483647 } //go:noinline func div_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 / a } //go:noinline func div_int32_Neg1_ssa(a int32) int32 { return a / -1 } //go:noinline func div_Neg1_int32_ssa(a int32) int32 { return -1 / a } //go:noinline func div_0_int32_ssa(a int32) int32 { return 0 / a } //go:noinline func div_int32_1_ssa(a int32) int32 { return a / 1 } //go:noinline func div_1_int32_ssa(a int32) int32 { return 1 / a } //go:noinline func div_int32_2147483647_ssa(a int32) int32 { return a / 2147483647 } //go:noinline func div_2147483647_int32_ssa(a int32) int32 { return 2147483647 / a } //go:noinline func mul_int32_Neg2147483648_ssa(a int32) int32 { return a * -2147483648 } //go:noinline func mul_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 * a } //go:noinline func mul_int32_Neg2147483647_ssa(a int32) int32 { return a * -2147483647 } //go:noinline func mul_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 * a } //go:noinline func mul_int32_Neg1_ssa(a int32) int32 { return a * -1 } //go:noinline func mul_Neg1_int32_ssa(a int32) int32 { return -1 * a } //go:noinline func mul_int32_0_ssa(a int32) int32 { return a * 0 } //go:noinline func mul_0_int32_ssa(a int32) int32 { return 0 * a } //go:noinline func mul_int32_1_ssa(a int32) int32 { return a * 1 } //go:noinline func mul_1_int32_ssa(a int32) int32 { return 1 * a } //go:noinline func mul_int32_2147483647_ssa(a int32) int32 { return a * 2147483647 } //go:noinline func mul_2147483647_int32_ssa(a int32) int32 { return 2147483647 * a } //go:noinline func mod_int32_Neg2147483648_ssa(a int32) int32 { return a % -2147483648 } //go:noinline func mod_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 % a } //go:noinline func mod_int32_Neg2147483647_ssa(a int32) int32 { return a % -2147483647 } //go:noinline func mod_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 % a } //go:noinline func mod_int32_Neg1_ssa(a int32) int32 { return a % -1 } //go:noinline func mod_Neg1_int32_ssa(a int32) int32 { return -1 % a } //go:noinline func mod_0_int32_ssa(a int32) int32 { return 0 % a } //go:noinline func mod_int32_1_ssa(a int32) int32 { return a % 1 } //go:noinline func mod_1_int32_ssa(a int32) int32 { return 1 % a } //go:noinline func mod_int32_2147483647_ssa(a int32) int32 { return a % 2147483647 } //go:noinline func mod_2147483647_int32_ssa(a int32) int32 { return 2147483647 % a } //go:noinline func and_int32_Neg2147483648_ssa(a int32) int32 { return a & -2147483648 } //go:noinline func and_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 & a } //go:noinline func and_int32_Neg2147483647_ssa(a int32) int32 { return a & -2147483647 } //go:noinline func and_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 & a } //go:noinline func and_int32_Neg1_ssa(a int32) int32 { return a & -1 } //go:noinline func and_Neg1_int32_ssa(a int32) int32 { return -1 & a } //go:noinline func and_int32_0_ssa(a int32) int32 { return a & 0 } //go:noinline func and_0_int32_ssa(a int32) int32 { return 0 & a } //go:noinline func and_int32_1_ssa(a int32) int32 { return a & 1 } //go:noinline func and_1_int32_ssa(a int32) int32 { return 1 & a } //go:noinline func and_int32_2147483647_ssa(a int32) int32 { return a & 2147483647 } //go:noinline func and_2147483647_int32_ssa(a int32) int32 { return 2147483647 & a } //go:noinline func or_int32_Neg2147483648_ssa(a int32) int32 { return a | -2147483648 } //go:noinline func or_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 | a } //go:noinline func or_int32_Neg2147483647_ssa(a int32) int32 { return a | -2147483647 } //go:noinline func or_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 | a } //go:noinline func or_int32_Neg1_ssa(a int32) int32 { return a | -1 } //go:noinline func or_Neg1_int32_ssa(a int32) int32 { return -1 | a } //go:noinline func or_int32_0_ssa(a int32) int32 { return a | 0 } //go:noinline func or_0_int32_ssa(a int32) int32 { return 0 | a } //go:noinline func or_int32_1_ssa(a int32) int32 { return a | 1 } //go:noinline func or_1_int32_ssa(a int32) int32 { return 1 | a } //go:noinline func or_int32_2147483647_ssa(a int32) int32 { return a | 2147483647 } //go:noinline func or_2147483647_int32_ssa(a int32) int32 { return 2147483647 | a } //go:noinline func xor_int32_Neg2147483648_ssa(a int32) int32 { return a ^ -2147483648 } //go:noinline func xor_Neg2147483648_int32_ssa(a int32) int32 { return -2147483648 ^ a } //go:noinline func xor_int32_Neg2147483647_ssa(a int32) int32 { return a ^ -2147483647 } //go:noinline func xor_Neg2147483647_int32_ssa(a int32) int32 { return -2147483647 ^ a } //go:noinline func xor_int32_Neg1_ssa(a int32) int32 { return a ^ -1 } //go:noinline func xor_Neg1_int32_ssa(a int32) int32 { return -1 ^ a } //go:noinline func xor_int32_0_ssa(a int32) int32 { return a ^ 0 } //go:noinline func xor_0_int32_ssa(a int32) int32 { return 0 ^ a } //go:noinline func xor_int32_1_ssa(a int32) int32 { return a ^ 1 } //go:noinline func xor_1_int32_ssa(a int32) int32 { return 1 ^ a } //go:noinline func xor_int32_2147483647_ssa(a int32) int32 { return a ^ 2147483647 } //go:noinline func xor_2147483647_int32_ssa(a int32) int32 { return 2147483647 ^ a } //go:noinline func add_uint16_0_ssa(a uint16) uint16 { return a + 0 } //go:noinline func add_0_uint16_ssa(a uint16) uint16 { return 0 + a } //go:noinline func add_uint16_1_ssa(a uint16) uint16 { return a + 1 } //go:noinline func add_1_uint16_ssa(a uint16) uint16 { return 1 + a } //go:noinline func add_uint16_65535_ssa(a uint16) uint16 { return a + 65535 } //go:noinline func add_65535_uint16_ssa(a uint16) uint16 { return 65535 + a } //go:noinline func sub_uint16_0_ssa(a uint16) uint16 { return a - 0 } //go:noinline func sub_0_uint16_ssa(a uint16) uint16 { return 0 - a } //go:noinline func sub_uint16_1_ssa(a uint16) uint16 { return a - 1 } //go:noinline func sub_1_uint16_ssa(a uint16) uint16 { return 1 - a } //go:noinline func sub_uint16_65535_ssa(a uint16) uint16 { return a - 65535 } //go:noinline func sub_65535_uint16_ssa(a uint16) uint16 { return 65535 - a } //go:noinline func div_0_uint16_ssa(a uint16) uint16 { return 0 / a } //go:noinline func div_uint16_1_ssa(a uint16) uint16 { return a / 1 } //go:noinline func div_1_uint16_ssa(a uint16) uint16 { return 1 / a } //go:noinline func div_uint16_65535_ssa(a uint16) uint16 { return a / 65535 } //go:noinline func div_65535_uint16_ssa(a uint16) uint16 { return 65535 / a } //go:noinline func mul_uint16_0_ssa(a uint16) uint16 { return a * 0 } //go:noinline func mul_0_uint16_ssa(a uint16) uint16 { return 0 * a } //go:noinline func mul_uint16_1_ssa(a uint16) uint16 { return a * 1 } //go:noinline func mul_1_uint16_ssa(a uint16) uint16 { return 1 * a } //go:noinline func mul_uint16_65535_ssa(a uint16) uint16 { return a * 65535 } //go:noinline func mul_65535_uint16_ssa(a uint16) uint16 { return 65535 * a } //go:noinline func lsh_uint16_0_ssa(a uint16) uint16 { return a << 0 } //go:noinline func lsh_0_uint16_ssa(a uint16) uint16 { return 0 << a } //go:noinline func lsh_uint16_1_ssa(a uint16) uint16 { return a << 1 } //go:noinline func lsh_1_uint16_ssa(a uint16) uint16 { return 1 << a } //go:noinline func lsh_uint16_65535_ssa(a uint16) uint16 { return a << 65535 } //go:noinline func lsh_65535_uint16_ssa(a uint16) uint16 { return 65535 << a } //go:noinline func rsh_uint16_0_ssa(a uint16) uint16 { return a >> 0 } //go:noinline func rsh_0_uint16_ssa(a uint16) uint16 { return 0 >> a } //go:noinline func rsh_uint16_1_ssa(a uint16) uint16 { return a >> 1 } //go:noinline func rsh_1_uint16_ssa(a uint16) uint16 { return 1 >> a } //go:noinline func rsh_uint16_65535_ssa(a uint16) uint16 { return a >> 65535 } //go:noinline func rsh_65535_uint16_ssa(a uint16) uint16 { return 65535 >> a } //go:noinline func mod_0_uint16_ssa(a uint16) uint16 { return 0 % a } //go:noinline func mod_uint16_1_ssa(a uint16) uint16 { return a % 1 } //go:noinline func mod_1_uint16_ssa(a uint16) uint16 { return 1 % a } //go:noinline func mod_uint16_65535_ssa(a uint16) uint16 { return a % 65535 } //go:noinline func mod_65535_uint16_ssa(a uint16) uint16 { return 65535 % a } //go:noinline func and_uint16_0_ssa(a uint16) uint16 { return a & 0 } //go:noinline func and_0_uint16_ssa(a uint16) uint16 { return 0 & a } //go:noinline func and_uint16_1_ssa(a uint16) uint16 { return a & 1 } //go:noinline func and_1_uint16_ssa(a uint16) uint16 { return 1 & a } //go:noinline func and_uint16_65535_ssa(a uint16) uint16 { return a & 65535 } //go:noinline func and_65535_uint16_ssa(a uint16) uint16 { return 65535 & a } //go:noinline func or_uint16_0_ssa(a uint16) uint16 { return a | 0 } //go:noinline func or_0_uint16_ssa(a uint16) uint16 { return 0 | a } //go:noinline func or_uint16_1_ssa(a uint16) uint16 { return a | 1 } //go:noinline func or_1_uint16_ssa(a uint16) uint16 { return 1 | a } //go:noinline func or_uint16_65535_ssa(a uint16) uint16 { return a | 65535 } //go:noinline func or_65535_uint16_ssa(a uint16) uint16 { return 65535 | a } //go:noinline func xor_uint16_0_ssa(a uint16) uint16 { return a ^ 0 } //go:noinline func xor_0_uint16_ssa(a uint16) uint16 { return 0 ^ a } //go:noinline func xor_uint16_1_ssa(a uint16) uint16 { return a ^ 1 } //go:noinline func xor_1_uint16_ssa(a uint16) uint16 { return 1 ^ a } //go:noinline func xor_uint16_65535_ssa(a uint16) uint16 { return a ^ 65535 } //go:noinline func xor_65535_uint16_ssa(a uint16) uint16 { return 65535 ^ a } //go:noinline func add_int16_Neg32768_ssa(a int16) int16 { return a + -32768 } //go:noinline func add_Neg32768_int16_ssa(a int16) int16 { return -32768 + a } //go:noinline func add_int16_Neg32767_ssa(a int16) int16 { return a + -32767 } //go:noinline func add_Neg32767_int16_ssa(a int16) int16 { return -32767 + a } //go:noinline func add_int16_Neg1_ssa(a int16) int16 { return a + -1 } //go:noinline func add_Neg1_int16_ssa(a int16) int16 { return -1 + a } //go:noinline func add_int16_0_ssa(a int16) int16 { return a + 0 } //go:noinline func add_0_int16_ssa(a int16) int16 { return 0 + a } //go:noinline func add_int16_1_ssa(a int16) int16 { return a + 1 } //go:noinline func add_1_int16_ssa(a int16) int16 { return 1 + a } //go:noinline func add_int16_32766_ssa(a int16) int16 { return a + 32766 } //go:noinline func add_32766_int16_ssa(a int16) int16 { return 32766 + a } //go:noinline func add_int16_32767_ssa(a int16) int16 { return a + 32767 } //go:noinline func add_32767_int16_ssa(a int16) int16 { return 32767 + a } //go:noinline func sub_int16_Neg32768_ssa(a int16) int16 { return a - -32768 } //go:noinline func sub_Neg32768_int16_ssa(a int16) int16 { return -32768 - a } //go:noinline func sub_int16_Neg32767_ssa(a int16) int16 { return a - -32767 } //go:noinline func sub_Neg32767_int16_ssa(a int16) int16 { return -32767 - a } //go:noinline func sub_int16_Neg1_ssa(a int16) int16 { return a - -1 } //go:noinline func sub_Neg1_int16_ssa(a int16) int16 { return -1 - a } //go:noinline func sub_int16_0_ssa(a int16) int16 { return a - 0 } //go:noinline func sub_0_int16_ssa(a int16) int16 { return 0 - a } //go:noinline func sub_int16_1_ssa(a int16) int16 { return a - 1 } //go:noinline func sub_1_int16_ssa(a int16) int16 { return 1 - a } //go:noinline func sub_int16_32766_ssa(a int16) int16 { return a - 32766 } //go:noinline func sub_32766_int16_ssa(a int16) int16 { return 32766 - a } //go:noinline func sub_int16_32767_ssa(a int16) int16 { return a - 32767 } //go:noinline func sub_32767_int16_ssa(a int16) int16 { return 32767 - a } //go:noinline func div_int16_Neg32768_ssa(a int16) int16 { return a / -32768 } //go:noinline func div_Neg32768_int16_ssa(a int16) int16 { return -32768 / a } //go:noinline func div_int16_Neg32767_ssa(a int16) int16 { return a / -32767 } //go:noinline func div_Neg32767_int16_ssa(a int16) int16 { return -32767 / a } //go:noinline func div_int16_Neg1_ssa(a int16) int16 { return a / -1 } //go:noinline func div_Neg1_int16_ssa(a int16) int16 { return -1 / a } //go:noinline func div_0_int16_ssa(a int16) int16 { return 0 / a } //go:noinline func div_int16_1_ssa(a int16) int16 { return a / 1 } //go:noinline func div_1_int16_ssa(a int16) int16 { return 1 / a } //go:noinline func div_int16_32766_ssa(a int16) int16 { return a / 32766 } //go:noinline func div_32766_int16_ssa(a int16) int16 { return 32766 / a } //go:noinline func div_int16_32767_ssa(a int16) int16 { return a / 32767 } //go:noinline func div_32767_int16_ssa(a int16) int16 { return 32767 / a } //go:noinline func mul_int16_Neg32768_ssa(a int16) int16 { return a * -32768 } //go:noinline func mul_Neg32768_int16_ssa(a int16) int16 { return -32768 * a } //go:noinline func mul_int16_Neg32767_ssa(a int16) int16 { return a * -32767 } //go:noinline func mul_Neg32767_int16_ssa(a int16) int16 { return -32767 * a } //go:noinline func mul_int16_Neg1_ssa(a int16) int16 { return a * -1 } //go:noinline func mul_Neg1_int16_ssa(a int16) int16 { return -1 * a } //go:noinline func mul_int16_0_ssa(a int16) int16 { return a * 0 } //go:noinline func mul_0_int16_ssa(a int16) int16 { return 0 * a } //go:noinline func mul_int16_1_ssa(a int16) int16 { return a * 1 } //go:noinline func mul_1_int16_ssa(a int16) int16 { return 1 * a } //go:noinline func mul_int16_32766_ssa(a int16) int16 { return a * 32766 } //go:noinline func mul_32766_int16_ssa(a int16) int16 { return 32766 * a } //go:noinline func mul_int16_32767_ssa(a int16) int16 { return a * 32767 } //go:noinline func mul_32767_int16_ssa(a int16) int16 { return 32767 * a } //go:noinline func mod_int16_Neg32768_ssa(a int16) int16 { return a % -32768 } //go:noinline func mod_Neg32768_int16_ssa(a int16) int16 { return -32768 % a } //go:noinline func mod_int16_Neg32767_ssa(a int16) int16 { return a % -32767 } //go:noinline func mod_Neg32767_int16_ssa(a int16) int16 { return -32767 % a } //go:noinline func mod_int16_Neg1_ssa(a int16) int16 { return a % -1 } //go:noinline func mod_Neg1_int16_ssa(a int16) int16 { return -1 % a } //go:noinline func mod_0_int16_ssa(a int16) int16 { return 0 % a } //go:noinline func mod_int16_1_ssa(a int16) int16 { return a % 1 } //go:noinline func mod_1_int16_ssa(a int16) int16 { return 1 % a } //go:noinline func mod_int16_32766_ssa(a int16) int16 { return a % 32766 } //go:noinline func mod_32766_int16_ssa(a int16) int16 { return 32766 % a } //go:noinline func mod_int16_32767_ssa(a int16) int16 { return a % 32767 } //go:noinline func mod_32767_int16_ssa(a int16) int16 { return 32767 % a } //go:noinline func and_int16_Neg32768_ssa(a int16) int16 { return a & -32768 } //go:noinline func and_Neg32768_int16_ssa(a int16) int16 { return -32768 & a } //go:noinline func and_int16_Neg32767_ssa(a int16) int16 { return a & -32767 } //go:noinline func and_Neg32767_int16_ssa(a int16) int16 { return -32767 & a } //go:noinline func and_int16_Neg1_ssa(a int16) int16 { return a & -1 } //go:noinline func and_Neg1_int16_ssa(a int16) int16 { return -1 & a } //go:noinline func and_int16_0_ssa(a int16) int16 { return a & 0 } //go:noinline func and_0_int16_ssa(a int16) int16 { return 0 & a } //go:noinline func and_int16_1_ssa(a int16) int16 { return a & 1 } //go:noinline func and_1_int16_ssa(a int16) int16 { return 1 & a } //go:noinline func and_int16_32766_ssa(a int16) int16 { return a & 32766 } //go:noinline func and_32766_int16_ssa(a int16) int16 { return 32766 & a } //go:noinline func and_int16_32767_ssa(a int16) int16 { return a & 32767 } //go:noinline func and_32767_int16_ssa(a int16) int16 { return 32767 & a } //go:noinline func or_int16_Neg32768_ssa(a int16) int16 { return a | -32768 } //go:noinline func or_Neg32768_int16_ssa(a int16) int16 { return -32768 | a } //go:noinline func or_int16_Neg32767_ssa(a int16) int16 { return a | -32767 } //go:noinline func or_Neg32767_int16_ssa(a int16) int16 { return -32767 | a } //go:noinline func or_int16_Neg1_ssa(a int16) int16 { return a | -1 } //go:noinline func or_Neg1_int16_ssa(a int16) int16 { return -1 | a } //go:noinline func or_int16_0_ssa(a int16) int16 { return a | 0 } //go:noinline func or_0_int16_ssa(a int16) int16 { return 0 | a } //go:noinline func or_int16_1_ssa(a int16) int16 { return a | 1 } //go:noinline func or_1_int16_ssa(a int16) int16 { return 1 | a } //go:noinline func or_int16_32766_ssa(a int16) int16 { return a | 32766 } //go:noinline func or_32766_int16_ssa(a int16) int16 { return 32766 | a } //go:noinline func or_int16_32767_ssa(a int16) int16 { return a | 32767 } //go:noinline func or_32767_int16_ssa(a int16) int16 { return 32767 | a } //go:noinline func xor_int16_Neg32768_ssa(a int16) int16 { return a ^ -32768 } //go:noinline func xor_Neg32768_int16_ssa(a int16) int16 { return -32768 ^ a } //go:noinline func xor_int16_Neg32767_ssa(a int16) int16 { return a ^ -32767 } //go:noinline func xor_Neg32767_int16_ssa(a int16) int16 { return -32767 ^ a } //go:noinline func xor_int16_Neg1_ssa(a int16) int16 { return a ^ -1 } //go:noinline func xor_Neg1_int16_ssa(a int16) int16 { return -1 ^ a } //go:noinline func xor_int16_0_ssa(a int16) int16 { return a ^ 0 } //go:noinline func xor_0_int16_ssa(a int16) int16 { return 0 ^ a } //go:noinline func xor_int16_1_ssa(a int16) int16 { return a ^ 1 } //go:noinline func xor_1_int16_ssa(a int16) int16 { return 1 ^ a } //go:noinline func xor_int16_32766_ssa(a int16) int16 { return a ^ 32766 } //go:noinline func xor_32766_int16_ssa(a int16) int16 { return 32766 ^ a } //go:noinline func xor_int16_32767_ssa(a int16) int16 { return a ^ 32767 } //go:noinline func xor_32767_int16_ssa(a int16) int16 { return 32767 ^ a } //go:noinline func add_uint8_0_ssa(a uint8) uint8 { return a + 0 } //go:noinline func add_0_uint8_ssa(a uint8) uint8 { return 0 + a } //go:noinline func add_uint8_1_ssa(a uint8) uint8 { return a + 1 } //go:noinline func add_1_uint8_ssa(a uint8) uint8 { return 1 + a } //go:noinline func add_uint8_255_ssa(a uint8) uint8 { return a + 255 } //go:noinline func add_255_uint8_ssa(a uint8) uint8 { return 255 + a } //go:noinline func sub_uint8_0_ssa(a uint8) uint8 { return a - 0 } //go:noinline func sub_0_uint8_ssa(a uint8) uint8 { return 0 - a } //go:noinline func sub_uint8_1_ssa(a uint8) uint8 { return a - 1 } //go:noinline func sub_1_uint8_ssa(a uint8) uint8 { return 1 - a } //go:noinline func sub_uint8_255_ssa(a uint8) uint8 { return a - 255 } //go:noinline func sub_255_uint8_ssa(a uint8) uint8 { return 255 - a } //go:noinline func div_0_uint8_ssa(a uint8) uint8 { return 0 / a } //go:noinline func div_uint8_1_ssa(a uint8) uint8 { return a / 1 } //go:noinline func div_1_uint8_ssa(a uint8) uint8 { return 1 / a } //go:noinline func div_uint8_255_ssa(a uint8) uint8 { return a / 255 } //go:noinline func div_255_uint8_ssa(a uint8) uint8 { return 255 / a } //go:noinline func mul_uint8_0_ssa(a uint8) uint8 { return a * 0 } //go:noinline func mul_0_uint8_ssa(a uint8) uint8 { return 0 * a } //go:noinline func mul_uint8_1_ssa(a uint8) uint8 { return a * 1 } //go:noinline func mul_1_uint8_ssa(a uint8) uint8 { return 1 * a } //go:noinline func mul_uint8_255_ssa(a uint8) uint8 { return a * 255 } //go:noinline func mul_255_uint8_ssa(a uint8) uint8 { return 255 * a } //go:noinline func lsh_uint8_0_ssa(a uint8) uint8 { return a << 0 } //go:noinline func lsh_0_uint8_ssa(a uint8) uint8 { return 0 << a } //go:noinline func lsh_uint8_1_ssa(a uint8) uint8 { return a << 1 } //go:noinline func lsh_1_uint8_ssa(a uint8) uint8 { return 1 << a } //go:noinline func lsh_uint8_255_ssa(a uint8) uint8 { return a << 255 } //go:noinline func lsh_255_uint8_ssa(a uint8) uint8 { return 255 << a } //go:noinline func rsh_uint8_0_ssa(a uint8) uint8 { return a >> 0 } //go:noinline func rsh_0_uint8_ssa(a uint8) uint8 { return 0 >> a } //go:noinline func rsh_uint8_1_ssa(a uint8) uint8 { return a >> 1 } //go:noinline func rsh_1_uint8_ssa(a uint8) uint8 { return 1 >> a } //go:noinline func rsh_uint8_255_ssa(a uint8) uint8 { return a >> 255 } //go:noinline func rsh_255_uint8_ssa(a uint8) uint8 { return 255 >> a } //go:noinline func mod_0_uint8_ssa(a uint8) uint8 { return 0 % a } //go:noinline func mod_uint8_1_ssa(a uint8) uint8 { return a % 1 } //go:noinline func mod_1_uint8_ssa(a uint8) uint8 { return 1 % a } //go:noinline func mod_uint8_255_ssa(a uint8) uint8 { return a % 255 } //go:noinline func mod_255_uint8_ssa(a uint8) uint8 { return 255 % a } //go:noinline func and_uint8_0_ssa(a uint8) uint8 { return a & 0 } //go:noinline func and_0_uint8_ssa(a uint8) uint8 { return 0 & a } //go:noinline func and_uint8_1_ssa(a uint8) uint8 { return a & 1 } //go:noinline func and_1_uint8_ssa(a uint8) uint8 { return 1 & a } //go:noinline func and_uint8_255_ssa(a uint8) uint8 { return a & 255 } //go:noinline func and_255_uint8_ssa(a uint8) uint8 { return 255 & a } //go:noinline func or_uint8_0_ssa(a uint8) uint8 { return a | 0 } //go:noinline func or_0_uint8_ssa(a uint8) uint8 { return 0 | a } //go:noinline func or_uint8_1_ssa(a uint8) uint8 { return a | 1 } //go:noinline func or_1_uint8_ssa(a uint8) uint8 { return 1 | a } //go:noinline func or_uint8_255_ssa(a uint8) uint8 { return a | 255 } //go:noinline func or_255_uint8_ssa(a uint8) uint8 { return 255 | a } //go:noinline func xor_uint8_0_ssa(a uint8) uint8 { return a ^ 0 } //go:noinline func xor_0_uint8_ssa(a uint8) uint8 { return 0 ^ a } //go:noinline func xor_uint8_1_ssa(a uint8) uint8 { return a ^ 1 } //go:noinline func xor_1_uint8_ssa(a uint8) uint8 { return 1 ^ a } //go:noinline func xor_uint8_255_ssa(a uint8) uint8 { return a ^ 255 } //go:noinline func xor_255_uint8_ssa(a uint8) uint8 { return 255 ^ a } //go:noinline func add_int8_Neg128_ssa(a int8) int8 { return a + -128 } //go:noinline func add_Neg128_int8_ssa(a int8) int8 { return -128 + a } //go:noinline func add_int8_Neg127_ssa(a int8) int8 { return a + -127 } //go:noinline func add_Neg127_int8_ssa(a int8) int8 { return -127 + a } //go:noinline func add_int8_Neg1_ssa(a int8) int8 { return a + -1 } //go:noinline func add_Neg1_int8_ssa(a int8) int8 { return -1 + a } //go:noinline func add_int8_0_ssa(a int8) int8 { return a + 0 } //go:noinline func add_0_int8_ssa(a int8) int8 { return 0 + a } //go:noinline func add_int8_1_ssa(a int8) int8 { return a + 1 } //go:noinline func add_1_int8_ssa(a int8) int8 { return 1 + a } //go:noinline func add_int8_126_ssa(a int8) int8 { return a + 126 } //go:noinline func add_126_int8_ssa(a int8) int8 { return 126 + a } //go:noinline func add_int8_127_ssa(a int8) int8 { return a + 127 } //go:noinline func add_127_int8_ssa(a int8) int8 { return 127 + a } //go:noinline func sub_int8_Neg128_ssa(a int8) int8 { return a - -128 } //go:noinline func sub_Neg128_int8_ssa(a int8) int8 { return -128 - a } //go:noinline func sub_int8_Neg127_ssa(a int8) int8 { return a - -127 } //go:noinline func sub_Neg127_int8_ssa(a int8) int8 { return -127 - a } //go:noinline func sub_int8_Neg1_ssa(a int8) int8 { return a - -1 } //go:noinline func sub_Neg1_int8_ssa(a int8) int8 { return -1 - a } //go:noinline func sub_int8_0_ssa(a int8) int8 { return a - 0 } //go:noinline func sub_0_int8_ssa(a int8) int8 { return 0 - a } //go:noinline func sub_int8_1_ssa(a int8) int8 { return a - 1 } //go:noinline func sub_1_int8_ssa(a int8) int8 { return 1 - a } //go:noinline func sub_int8_126_ssa(a int8) int8 { return a - 126 } //go:noinline func sub_126_int8_ssa(a int8) int8 { return 126 - a } //go:noinline func sub_int8_127_ssa(a int8) int8 { return a - 127 } //go:noinline func sub_127_int8_ssa(a int8) int8 { return 127 - a } //go:noinline func div_int8_Neg128_ssa(a int8) int8 { return a / -128 } //go:noinline func div_Neg128_int8_ssa(a int8) int8 { return -128 / a } //go:noinline func div_int8_Neg127_ssa(a int8) int8 { return a / -127 } //go:noinline func div_Neg127_int8_ssa(a int8) int8 { return -127 / a } //go:noinline func div_int8_Neg1_ssa(a int8) int8 { return a / -1 } //go:noinline func div_Neg1_int8_ssa(a int8) int8 { return -1 / a } //go:noinline func div_0_int8_ssa(a int8) int8 { return 0 / a } //go:noinline func div_int8_1_ssa(a int8) int8 { return a / 1 } //go:noinline func div_1_int8_ssa(a int8) int8 { return 1 / a } //go:noinline func div_int8_126_ssa(a int8) int8 { return a / 126 } //go:noinline func div_126_int8_ssa(a int8) int8 { return 126 / a } //go:noinline func div_int8_127_ssa(a int8) int8 { return a / 127 } //go:noinline func div_127_int8_ssa(a int8) int8 { return 127 / a } //go:noinline func mul_int8_Neg128_ssa(a int8) int8 { return a * -128 } //go:noinline func mul_Neg128_int8_ssa(a int8) int8 { return -128 * a } //go:noinline func mul_int8_Neg127_ssa(a int8) int8 { return a * -127 } //go:noinline func mul_Neg127_int8_ssa(a int8) int8 { return -127 * a } //go:noinline func mul_int8_Neg1_ssa(a int8) int8 { return a * -1 } //go:noinline func mul_Neg1_int8_ssa(a int8) int8 { return -1 * a } //go:noinline func mul_int8_0_ssa(a int8) int8 { return a * 0 } //go:noinline func mul_0_int8_ssa(a int8) int8 { return 0 * a } //go:noinline func mul_int8_1_ssa(a int8) int8 { return a * 1 } //go:noinline func mul_1_int8_ssa(a int8) int8 { return 1 * a } //go:noinline func mul_int8_126_ssa(a int8) int8 { return a * 126 } //go:noinline func mul_126_int8_ssa(a int8) int8 { return 126 * a } //go:noinline func mul_int8_127_ssa(a int8) int8 { return a * 127 } //go:noinline func mul_127_int8_ssa(a int8) int8 { return 127 * a } //go:noinline func mod_int8_Neg128_ssa(a int8) int8 { return a % -128 } //go:noinline func mod_Neg128_int8_ssa(a int8) int8 { return -128 % a } //go:noinline func mod_int8_Neg127_ssa(a int8) int8 { return a % -127 } //go:noinline func mod_Neg127_int8_ssa(a int8) int8 { return -127 % a } //go:noinline func mod_int8_Neg1_ssa(a int8) int8 { return a % -1 } //go:noinline func mod_Neg1_int8_ssa(a int8) int8 { return -1 % a } //go:noinline func mod_0_int8_ssa(a int8) int8 { return 0 % a } //go:noinline func mod_int8_1_ssa(a int8) int8 { return a % 1 } //go:noinline func mod_1_int8_ssa(a int8) int8 { return 1 % a } //go:noinline func mod_int8_126_ssa(a int8) int8 { return a % 126 } //go:noinline func mod_126_int8_ssa(a int8) int8 { return 126 % a } //go:noinline func mod_int8_127_ssa(a int8) int8 { return a % 127 } //go:noinline func mod_127_int8_ssa(a int8) int8 { return 127 % a } //go:noinline func and_int8_Neg128_ssa(a int8) int8 { return a & -128 } //go:noinline func and_Neg128_int8_ssa(a int8) int8 { return -128 & a } //go:noinline func and_int8_Neg127_ssa(a int8) int8 { return a & -127 } //go:noinline func and_Neg127_int8_ssa(a int8) int8 { return -127 & a } //go:noinline func and_int8_Neg1_ssa(a int8) int8 { return a & -1 } //go:noinline func and_Neg1_int8_ssa(a int8) int8 { return -1 & a } //go:noinline func and_int8_0_ssa(a int8) int8 { return a & 0 } //go:noinline func and_0_int8_ssa(a int8) int8 { return 0 & a } //go:noinline func and_int8_1_ssa(a int8) int8 { return a & 1 } //go:noinline func and_1_int8_ssa(a int8) int8 { return 1 & a } //go:noinline func and_int8_126_ssa(a int8) int8 { return a & 126 } //go:noinline func and_126_int8_ssa(a int8) int8 { return 126 & a } //go:noinline func and_int8_127_ssa(a int8) int8 { return a & 127 } //go:noinline func and_127_int8_ssa(a int8) int8 { return 127 & a } //go:noinline func or_int8_Neg128_ssa(a int8) int8 { return a | -128 } //go:noinline func or_Neg128_int8_ssa(a int8) int8 { return -128 | a } //go:noinline func or_int8_Neg127_ssa(a int8) int8 { return a | -127 } //go:noinline func or_Neg127_int8_ssa(a int8) int8 { return -127 | a } //go:noinline func or_int8_Neg1_ssa(a int8) int8 { return a | -1 } //go:noinline func or_Neg1_int8_ssa(a int8) int8 { return -1 | a } //go:noinline func or_int8_0_ssa(a int8) int8 { return a | 0 } //go:noinline func or_0_int8_ssa(a int8) int8 { return 0 | a } //go:noinline func or_int8_1_ssa(a int8) int8 { return a | 1 } //go:noinline func or_1_int8_ssa(a int8) int8 { return 1 | a } //go:noinline func or_int8_126_ssa(a int8) int8 { return a | 126 } //go:noinline func or_126_int8_ssa(a int8) int8 { return 126 | a } //go:noinline func or_int8_127_ssa(a int8) int8 { return a | 127 } //go:noinline func or_127_int8_ssa(a int8) int8 { return 127 | a } //go:noinline func xor_int8_Neg128_ssa(a int8) int8 { return a ^ -128 } //go:noinline func xor_Neg128_int8_ssa(a int8) int8 { return -128 ^ a } //go:noinline func xor_int8_Neg127_ssa(a int8) int8 { return a ^ -127 } //go:noinline func xor_Neg127_int8_ssa(a int8) int8 { return -127 ^ a } //go:noinline func xor_int8_Neg1_ssa(a int8) int8 { return a ^ -1 } //go:noinline func xor_Neg1_int8_ssa(a int8) int8 { return -1 ^ a } //go:noinline func xor_int8_0_ssa(a int8) int8 { return a ^ 0 } //go:noinline func xor_0_int8_ssa(a int8) int8 { return 0 ^ a } //go:noinline func xor_int8_1_ssa(a int8) int8 { return a ^ 1 } //go:noinline func xor_1_int8_ssa(a int8) int8 { return 1 ^ a } //go:noinline func xor_int8_126_ssa(a int8) int8 { return a ^ 126 } //go:noinline func xor_126_int8_ssa(a int8) int8 { return 126 ^ a } //go:noinline func xor_int8_127_ssa(a int8) int8 { return a ^ 127 } //go:noinline func xor_127_int8_ssa(a int8) int8 { return 127 ^ a } var failed bool func main() { if got := add_0_uint64_ssa(0); got != 0 { fmt.Printf("add_uint64 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint64_0_ssa(0); got != 0 { fmt.Printf("add_uint64 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_uint64_ssa(1); got != 1 { fmt.Printf("add_uint64 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint64_0_ssa(1); got != 1 { fmt.Printf("add_uint64 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("add_uint64 0%s4294967296 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_uint64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("add_uint64 4294967296%s0 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_0_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("add_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `+`, got) failed = true } if got := add_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("add_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `+`, got) failed = true } if got := add_0_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("add_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `+`, got) failed = true } if got := add_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("add_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `+`, got) failed = true } if got := add_1_uint64_ssa(0); got != 1 { fmt.Printf("add_uint64 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint64_1_ssa(0); got != 1 { fmt.Printf("add_uint64 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_uint64_ssa(1); got != 2 { fmt.Printf("add_uint64 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_uint64_1_ssa(1); got != 2 { fmt.Printf("add_uint64 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_uint64_ssa(4294967296); got != 4294967297 { fmt.Printf("add_uint64 1%s4294967296 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_uint64_1_ssa(4294967296); got != 4294967297 { fmt.Printf("add_uint64 4294967296%s1 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_1_uint64_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("add_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `+`, got) failed = true } if got := add_uint64_1_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("add_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `+`, got) failed = true } if got := add_1_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("add_uint64 1%s18446744073709551615 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint64_1_ssa(18446744073709551615); got != 0 { fmt.Printf("add_uint64 18446744073709551615%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_4294967296_uint64_ssa(0); got != 4294967296 { fmt.Printf("add_uint64 4294967296%s0 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_uint64_4294967296_ssa(0); got != 4294967296 { fmt.Printf("add_uint64 0%s4294967296 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_4294967296_uint64_ssa(1); got != 4294967297 { fmt.Printf("add_uint64 4294967296%s1 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_uint64_4294967296_ssa(1); got != 4294967297 { fmt.Printf("add_uint64 1%s4294967296 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_4294967296_uint64_ssa(4294967296); got != 8589934592 { fmt.Printf("add_uint64 4294967296%s4294967296 = %d, wanted 8589934592\n", `+`, got) failed = true } if got := add_uint64_4294967296_ssa(4294967296); got != 8589934592 { fmt.Printf("add_uint64 4294967296%s4294967296 = %d, wanted 8589934592\n", `+`, got) failed = true } if got := add_4294967296_uint64_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("add_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `+`, got) failed = true } if got := add_uint64_4294967296_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("add_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `+`, got) failed = true } if got := add_4294967296_uint64_ssa(18446744073709551615); got != 4294967295 { fmt.Printf("add_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_uint64_4294967296_ssa(18446744073709551615); got != 4294967295 { fmt.Printf("add_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { fmt.Printf("add_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `+`, got) failed = true } if got := add_uint64_9223372036854775808_ssa(0); got != 9223372036854775808 { fmt.Printf("add_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `+`, got) failed = true } if got := add_9223372036854775808_uint64_ssa(1); got != 9223372036854775809 { fmt.Printf("add_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `+`, got) failed = true } if got := add_uint64_9223372036854775808_ssa(1); got != 9223372036854775809 { fmt.Printf("add_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `+`, got) failed = true } if got := add_9223372036854775808_uint64_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("add_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `+`, got) failed = true } if got := add_uint64_9223372036854775808_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("add_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `+`, got) failed = true } if got := add_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("add_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("add_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `+`, got) failed = true } if got := add_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("add_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("add_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { fmt.Printf("add_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `+`, got) failed = true } if got := add_uint64_18446744073709551615_ssa(0); got != 18446744073709551615 { fmt.Printf("add_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `+`, got) failed = true } if got := add_18446744073709551615_uint64_ssa(1); got != 0 { fmt.Printf("add_uint64 18446744073709551615%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint64_18446744073709551615_ssa(1); got != 0 { fmt.Printf("add_uint64 1%s18446744073709551615 = %d, wanted 0\n", `+`, got) failed = true } if got := add_18446744073709551615_uint64_ssa(4294967296); got != 4294967295 { fmt.Printf("add_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_uint64_18446744073709551615_ssa(4294967296); got != 4294967295 { fmt.Printf("add_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("add_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("add_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_18446744073709551615_uint64_ssa(18446744073709551615); got != 18446744073709551614 { fmt.Printf("add_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551614\n", `+`, got) failed = true } if got := add_uint64_18446744073709551615_ssa(18446744073709551615); got != 18446744073709551614 { fmt.Printf("add_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551614\n", `+`, got) failed = true } if got := sub_0_uint64_ssa(0); got != 0 { fmt.Printf("sub_uint64 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint64_0_ssa(0); got != 0 { fmt.Printf("sub_uint64 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_uint64_ssa(1); got != 18446744073709551615 { fmt.Printf("sub_uint64 0%s1 = %d, wanted 18446744073709551615\n", `-`, got) failed = true } if got := sub_uint64_0_ssa(1); got != 1 { fmt.Printf("sub_uint64 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_uint64_ssa(4294967296); got != 18446744069414584320 { fmt.Printf("sub_uint64 0%s4294967296 = %d, wanted 18446744069414584320\n", `-`, got) failed = true } if got := sub_uint64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("sub_uint64 4294967296%s0 = %d, wanted 4294967296\n", `-`, got) failed = true } if got := sub_0_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("sub_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `-`, got) failed = true } if got := sub_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("sub_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `-`, got) failed = true } if got := sub_0_uint64_ssa(18446744073709551615); got != 1 { fmt.Printf("sub_uint64 0%s18446744073709551615 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("sub_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `-`, got) failed = true } if got := sub_1_uint64_ssa(0); got != 1 { fmt.Printf("sub_uint64 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint64_1_ssa(0); got != 18446744073709551615 { fmt.Printf("sub_uint64 0%s1 = %d, wanted 18446744073709551615\n", `-`, got) failed = true } if got := sub_1_uint64_ssa(1); got != 0 { fmt.Printf("sub_uint64 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint64_1_ssa(1); got != 0 { fmt.Printf("sub_uint64 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_uint64_ssa(4294967296); got != 18446744069414584321 { fmt.Printf("sub_uint64 1%s4294967296 = %d, wanted 18446744069414584321\n", `-`, got) failed = true } if got := sub_uint64_1_ssa(4294967296); got != 4294967295 { fmt.Printf("sub_uint64 4294967296%s1 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_1_uint64_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("sub_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `-`, got) failed = true } if got := sub_uint64_1_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("sub_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_1_uint64_ssa(18446744073709551615); got != 2 { fmt.Printf("sub_uint64 1%s18446744073709551615 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_uint64_1_ssa(18446744073709551615); got != 18446744073709551614 { fmt.Printf("sub_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `-`, got) failed = true } if got := sub_4294967296_uint64_ssa(0); got != 4294967296 { fmt.Printf("sub_uint64 4294967296%s0 = %d, wanted 4294967296\n", `-`, got) failed = true } if got := sub_uint64_4294967296_ssa(0); got != 18446744069414584320 { fmt.Printf("sub_uint64 0%s4294967296 = %d, wanted 18446744069414584320\n", `-`, got) failed = true } if got := sub_4294967296_uint64_ssa(1); got != 4294967295 { fmt.Printf("sub_uint64 4294967296%s1 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_uint64_4294967296_ssa(1); got != 18446744069414584321 { fmt.Printf("sub_uint64 1%s4294967296 = %d, wanted 18446744069414584321\n", `-`, got) failed = true } if got := sub_4294967296_uint64_ssa(4294967296); got != 0 { fmt.Printf("sub_uint64 4294967296%s4294967296 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("sub_uint64 4294967296%s4294967296 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_4294967296_uint64_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("sub_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `-`, got) failed = true } if got := sub_uint64_4294967296_ssa(9223372036854775808); got != 9223372032559808512 { fmt.Printf("sub_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372032559808512\n", `-`, got) failed = true } if got := sub_4294967296_uint64_ssa(18446744073709551615); got != 4294967297 { fmt.Printf("sub_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967297\n", `-`, got) failed = true } if got := sub_uint64_4294967296_ssa(18446744073709551615); got != 18446744069414584319 { fmt.Printf("sub_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584319\n", `-`, got) failed = true } if got := sub_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { fmt.Printf("sub_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `-`, got) failed = true } if got := sub_uint64_9223372036854775808_ssa(0); got != 9223372036854775808 { fmt.Printf("sub_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `-`, got) failed = true } if got := sub_9223372036854775808_uint64_ssa(1); got != 9223372036854775807 { fmt.Printf("sub_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_uint64_9223372036854775808_ssa(1); got != 9223372036854775809 { fmt.Printf("sub_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `-`, got) failed = true } if got := sub_9223372036854775808_uint64_ssa(4294967296); got != 9223372032559808512 { fmt.Printf("sub_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372032559808512\n", `-`, got) failed = true } if got := sub_uint64_9223372036854775808_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("sub_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `-`, got) failed = true } if got := sub_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("sub_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("sub_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775809 { fmt.Printf("sub_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775809\n", `-`, got) failed = true } if got := sub_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("sub_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { fmt.Printf("sub_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `-`, got) failed = true } if got := sub_uint64_18446744073709551615_ssa(0); got != 1 { fmt.Printf("sub_uint64 0%s18446744073709551615 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_18446744073709551615_uint64_ssa(1); got != 18446744073709551614 { fmt.Printf("sub_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `-`, got) failed = true } if got := sub_uint64_18446744073709551615_ssa(1); got != 2 { fmt.Printf("sub_uint64 1%s18446744073709551615 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_18446744073709551615_uint64_ssa(4294967296); got != 18446744069414584319 { fmt.Printf("sub_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584319\n", `-`, got) failed = true } if got := sub_uint64_18446744073709551615_ssa(4294967296); got != 4294967297 { fmt.Printf("sub_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967297\n", `-`, got) failed = true } if got := sub_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("sub_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("sub_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775809\n", `-`, got) failed = true } if got := sub_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("sub_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { fmt.Printf("sub_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `-`, got) failed = true } if got := div_0_uint64_ssa(1); got != 0 { fmt.Printf("div_uint64 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_uint64_ssa(4294967296); got != 0 { fmt.Printf("div_uint64 0%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("div_uint64 0%s9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("div_uint64 0%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_1_ssa(0); got != 0 { fmt.Printf("div_uint64 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_uint64_ssa(1); got != 1 { fmt.Printf("div_uint64 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint64_1_ssa(1); got != 1 { fmt.Printf("div_uint64 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_uint64_ssa(4294967296); got != 0 { fmt.Printf("div_uint64 1%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_1_ssa(4294967296); got != 4294967296 { fmt.Printf("div_uint64 4294967296%s1 = %d, wanted 4294967296\n", `/`, got) failed = true } if got := div_1_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("div_uint64 1%s9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_1_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("div_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775808\n", `/`, got) failed = true } if got := div_1_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("div_uint64 1%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_1_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("div_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `/`, got) failed = true } if got := div_uint64_4294967296_ssa(0); got != 0 { fmt.Printf("div_uint64 0%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_4294967296_uint64_ssa(1); got != 4294967296 { fmt.Printf("div_uint64 4294967296%s1 = %d, wanted 4294967296\n", `/`, got) failed = true } if got := div_uint64_4294967296_ssa(1); got != 0 { fmt.Printf("div_uint64 1%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_4294967296_uint64_ssa(4294967296); got != 1 { fmt.Printf("div_uint64 4294967296%s4294967296 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint64_4294967296_ssa(4294967296); got != 1 { fmt.Printf("div_uint64 4294967296%s4294967296 = %d, wanted 1\n", `/`, got) failed = true } if got := div_4294967296_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("div_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_4294967296_ssa(9223372036854775808); got != 2147483648 { fmt.Printf("div_uint64 9223372036854775808%s4294967296 = %d, wanted 2147483648\n", `/`, got) failed = true } if got := div_4294967296_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("div_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_4294967296_ssa(18446744073709551615); got != 4294967295 { fmt.Printf("div_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `/`, got) failed = true } if got := div_uint64_9223372036854775808_ssa(0); got != 0 { fmt.Printf("div_uint64 0%s9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775808_uint64_ssa(1); got != 9223372036854775808 { fmt.Printf("div_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775808\n", `/`, got) failed = true } if got := div_uint64_9223372036854775808_ssa(1); got != 0 { fmt.Printf("div_uint64 1%s9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775808_uint64_ssa(4294967296); got != 2147483648 { fmt.Printf("div_uint64 9223372036854775808%s4294967296 = %d, wanted 2147483648\n", `/`, got) failed = true } if got := div_uint64_9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("div_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775808_uint64_ssa(9223372036854775808); got != 1 { fmt.Printf("div_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint64_9223372036854775808_ssa(9223372036854775808); got != 1 { fmt.Printf("div_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 1\n", `/`, got) failed = true } if got := div_9223372036854775808_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("div_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint64_9223372036854775808_ssa(18446744073709551615); got != 1 { fmt.Printf("div_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint64_18446744073709551615_ssa(0); got != 0 { fmt.Printf("div_uint64 0%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_18446744073709551615_uint64_ssa(1); got != 18446744073709551615 { fmt.Printf("div_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `/`, got) failed = true } if got := div_uint64_18446744073709551615_ssa(1); got != 0 { fmt.Printf("div_uint64 1%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_18446744073709551615_uint64_ssa(4294967296); got != 4294967295 { fmt.Printf("div_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `/`, got) failed = true } if got := div_uint64_18446744073709551615_ssa(4294967296); got != 0 { fmt.Printf("div_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_18446744073709551615_uint64_ssa(9223372036854775808); got != 1 { fmt.Printf("div_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint64_18446744073709551615_ssa(9223372036854775808); got != 0 { fmt.Printf("div_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `/`, got) failed = true } if got := div_18446744073709551615_uint64_ssa(18446744073709551615); got != 1 { fmt.Printf("div_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint64_18446744073709551615_ssa(18446744073709551615); got != 1 { fmt.Printf("div_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_0_uint64_ssa(0); got != 0 { fmt.Printf("mul_uint64 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_0_ssa(0); got != 0 { fmt.Printf("mul_uint64 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint64_ssa(1); got != 0 { fmt.Printf("mul_uint64 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_0_ssa(1); got != 0 { fmt.Printf("mul_uint64 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint64_ssa(4294967296); got != 0 { fmt.Printf("mul_uint64 0%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_0_ssa(4294967296); got != 0 { fmt.Printf("mul_uint64 4294967296%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("mul_uint64 0%s9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_0_ssa(9223372036854775808); got != 0 { fmt.Printf("mul_uint64 9223372036854775808%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("mul_uint64 0%s18446744073709551615 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_0_ssa(18446744073709551615); got != 0 { fmt.Printf("mul_uint64 18446744073709551615%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint64_ssa(0); got != 0 { fmt.Printf("mul_uint64 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_1_ssa(0); got != 0 { fmt.Printf("mul_uint64 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint64_ssa(1); got != 1 { fmt.Printf("mul_uint64 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint64_1_ssa(1); got != 1 { fmt.Printf("mul_uint64 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("mul_uint64 1%s4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_uint64_1_ssa(4294967296); got != 4294967296 { fmt.Printf("mul_uint64 4294967296%s1 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_1_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("mul_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_uint64_1_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("mul_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_1_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("mul_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551615\n", `*`, got) failed = true } if got := mul_uint64_1_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("mul_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `*`, got) failed = true } if got := mul_4294967296_uint64_ssa(0); got != 0 { fmt.Printf("mul_uint64 4294967296%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_4294967296_ssa(0); got != 0 { fmt.Printf("mul_uint64 0%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_uint64_ssa(1); got != 4294967296 { fmt.Printf("mul_uint64 4294967296%s1 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_uint64_4294967296_ssa(1); got != 4294967296 { fmt.Printf("mul_uint64 1%s4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_4294967296_uint64_ssa(4294967296); got != 0 { fmt.Printf("mul_uint64 4294967296%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("mul_uint64 4294967296%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("mul_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_4294967296_ssa(9223372036854775808); got != 0 { fmt.Printf("mul_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_uint64_ssa(18446744073709551615); got != 18446744069414584320 { fmt.Printf("mul_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744069414584320\n", `*`, got) failed = true } if got := mul_uint64_4294967296_ssa(18446744073709551615); got != 18446744069414584320 { fmt.Printf("mul_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584320\n", `*`, got) failed = true } if got := mul_9223372036854775808_uint64_ssa(0); got != 0 { fmt.Printf("mul_uint64 9223372036854775808%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_9223372036854775808_ssa(0); got != 0 { fmt.Printf("mul_uint64 0%s9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_9223372036854775808_uint64_ssa(1); got != 9223372036854775808 { fmt.Printf("mul_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_uint64_9223372036854775808_ssa(1); got != 9223372036854775808 { fmt.Printf("mul_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_9223372036854775808_uint64_ssa(4294967296); got != 0 { fmt.Printf("mul_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("mul_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("mul_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("mul_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775808 { fmt.Printf("mul_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775808 { fmt.Printf("mul_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_18446744073709551615_uint64_ssa(0); got != 0 { fmt.Printf("mul_uint64 18446744073709551615%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint64_18446744073709551615_ssa(0); got != 0 { fmt.Printf("mul_uint64 0%s18446744073709551615 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_18446744073709551615_uint64_ssa(1); got != 18446744073709551615 { fmt.Printf("mul_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `*`, got) failed = true } if got := mul_uint64_18446744073709551615_ssa(1); got != 18446744073709551615 { fmt.Printf("mul_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551615\n", `*`, got) failed = true } if got := mul_18446744073709551615_uint64_ssa(4294967296); got != 18446744069414584320 { fmt.Printf("mul_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584320\n", `*`, got) failed = true } if got := mul_uint64_18446744073709551615_ssa(4294967296); got != 18446744069414584320 { fmt.Printf("mul_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744069414584320\n", `*`, got) failed = true } if got := mul_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("mul_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("mul_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `*`, got) failed = true } if got := mul_18446744073709551615_uint64_ssa(18446744073709551615); got != 1 { fmt.Printf("mul_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint64_18446744073709551615_ssa(18446744073709551615); got != 1 { fmt.Printf("mul_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 1\n", `*`, got) failed = true } if got := lsh_0_uint64_ssa(0); got != 0 { fmt.Printf("lsh_uint64 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_0_ssa(0); got != 0 { fmt.Printf("lsh_uint64 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_0_uint64_ssa(1); got != 0 { fmt.Printf("lsh_uint64 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_0_ssa(1); got != 1 { fmt.Printf("lsh_uint64 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_0_uint64_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 0%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("lsh_uint64 4294967296%s0 = %d, wanted 4294967296\n", `<<`, got) failed = true } if got := lsh_0_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 0%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("lsh_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `<<`, got) failed = true } if got := lsh_0_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 0%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("lsh_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `<<`, got) failed = true } if got := lsh_1_uint64_ssa(0); got != 1 { fmt.Printf("lsh_uint64 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_uint64_1_ssa(0); got != 0 { fmt.Printf("lsh_uint64 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_1_uint64_ssa(1); got != 2 { fmt.Printf("lsh_uint64 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_uint64_1_ssa(1); got != 2 { fmt.Printf("lsh_uint64 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_1_uint64_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 1%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_1_ssa(4294967296); got != 8589934592 { fmt.Printf("lsh_uint64 4294967296%s1 = %d, wanted 8589934592\n", `<<`, got) failed = true } if got := lsh_1_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 1%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_1_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_1_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 1%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_1_ssa(18446744073709551615); got != 18446744073709551614 { fmt.Printf("lsh_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `<<`, got) failed = true } if got := lsh_4294967296_uint64_ssa(0); got != 4294967296 { fmt.Printf("lsh_uint64 4294967296%s0 = %d, wanted 4294967296\n", `<<`, got) failed = true } if got := lsh_uint64_4294967296_ssa(0); got != 0 { fmt.Printf("lsh_uint64 0%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_4294967296_uint64_ssa(1); got != 8589934592 { fmt.Printf("lsh_uint64 4294967296%s1 = %d, wanted 8589934592\n", `<<`, got) failed = true } if got := lsh_uint64_4294967296_ssa(1); got != 0 { fmt.Printf("lsh_uint64 1%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_4294967296_uint64_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 4294967296%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 4294967296%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_4294967296_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_4294967296_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_4294967296_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_4294967296_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 18446744073709551615%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { fmt.Printf("lsh_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `<<`, got) failed = true } if got := lsh_uint64_9223372036854775808_ssa(0); got != 0 { fmt.Printf("lsh_uint64 0%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_9223372036854775808_uint64_ssa(1); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_9223372036854775808_ssa(1); got != 0 { fmt.Printf("lsh_uint64 1%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_9223372036854775808_uint64_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_9223372036854775808_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_9223372036854775808_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { fmt.Printf("lsh_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `<<`, got) failed = true } if got := lsh_uint64_18446744073709551615_ssa(0); got != 0 { fmt.Printf("lsh_uint64 0%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_18446744073709551615_uint64_ssa(1); got != 18446744073709551614 { fmt.Printf("lsh_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `<<`, got) failed = true } if got := lsh_uint64_18446744073709551615_ssa(1); got != 0 { fmt.Printf("lsh_uint64 1%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_18446744073709551615_uint64_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 18446744073709551615%s4294967296 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_18446744073709551615_ssa(4294967296); got != 0 { fmt.Printf("lsh_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_18446744073709551615_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_18446744073709551615_ssa(9223372036854775808); got != 0 { fmt.Printf("lsh_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { fmt.Printf("lsh_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `<<`, got) failed = true } if got := rsh_0_uint64_ssa(0); got != 0 { fmt.Printf("rsh_uint64 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_0_ssa(0); got != 0 { fmt.Printf("rsh_uint64 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_0_uint64_ssa(1); got != 0 { fmt.Printf("rsh_uint64 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_0_ssa(1); got != 1 { fmt.Printf("rsh_uint64 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_0_uint64_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 0%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("rsh_uint64 4294967296%s0 = %d, wanted 4294967296\n", `>>`, got) failed = true } if got := rsh_0_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 0%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("rsh_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `>>`, got) failed = true } if got := rsh_0_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 0%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("rsh_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `>>`, got) failed = true } if got := rsh_1_uint64_ssa(0); got != 1 { fmt.Printf("rsh_uint64 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_uint64_1_ssa(0); got != 0 { fmt.Printf("rsh_uint64 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint64_ssa(1); got != 0 { fmt.Printf("rsh_uint64 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_1_ssa(1); got != 0 { fmt.Printf("rsh_uint64 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint64_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 1%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_1_ssa(4294967296); got != 2147483648 { fmt.Printf("rsh_uint64 4294967296%s1 = %d, wanted 2147483648\n", `>>`, got) failed = true } if got := rsh_1_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 1%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_1_ssa(9223372036854775808); got != 4611686018427387904 { fmt.Printf("rsh_uint64 9223372036854775808%s1 = %d, wanted 4611686018427387904\n", `>>`, got) failed = true } if got := rsh_1_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 1%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_1_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("rsh_uint64 18446744073709551615%s1 = %d, wanted 9223372036854775807\n", `>>`, got) failed = true } if got := rsh_4294967296_uint64_ssa(0); got != 4294967296 { fmt.Printf("rsh_uint64 4294967296%s0 = %d, wanted 4294967296\n", `>>`, got) failed = true } if got := rsh_uint64_4294967296_ssa(0); got != 0 { fmt.Printf("rsh_uint64 0%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_4294967296_uint64_ssa(1); got != 2147483648 { fmt.Printf("rsh_uint64 4294967296%s1 = %d, wanted 2147483648\n", `>>`, got) failed = true } if got := rsh_uint64_4294967296_ssa(1); got != 0 { fmt.Printf("rsh_uint64 1%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_4294967296_uint64_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 4294967296%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 4294967296%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_4294967296_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_4294967296_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_4294967296_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_4294967296_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 18446744073709551615%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { fmt.Printf("rsh_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `>>`, got) failed = true } if got := rsh_uint64_9223372036854775808_ssa(0); got != 0 { fmt.Printf("rsh_uint64 0%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_9223372036854775808_uint64_ssa(1); got != 4611686018427387904 { fmt.Printf("rsh_uint64 9223372036854775808%s1 = %d, wanted 4611686018427387904\n", `>>`, got) failed = true } if got := rsh_uint64_9223372036854775808_ssa(1); got != 0 { fmt.Printf("rsh_uint64 1%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_9223372036854775808_uint64_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_9223372036854775808_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_9223372036854775808_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { fmt.Printf("rsh_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `>>`, got) failed = true } if got := rsh_uint64_18446744073709551615_ssa(0); got != 0 { fmt.Printf("rsh_uint64 0%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_18446744073709551615_uint64_ssa(1); got != 9223372036854775807 { fmt.Printf("rsh_uint64 18446744073709551615%s1 = %d, wanted 9223372036854775807\n", `>>`, got) failed = true } if got := rsh_uint64_18446744073709551615_ssa(1); got != 0 { fmt.Printf("rsh_uint64 1%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_18446744073709551615_uint64_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 18446744073709551615%s4294967296 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_18446744073709551615_ssa(4294967296); got != 0 { fmt.Printf("rsh_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_18446744073709551615_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_18446744073709551615_ssa(9223372036854775808); got != 0 { fmt.Printf("rsh_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { fmt.Printf("rsh_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `>>`, got) failed = true } if got := mod_0_uint64_ssa(1); got != 0 { fmt.Printf("mod_uint64 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_uint64_ssa(4294967296); got != 0 { fmt.Printf("mod_uint64 0%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("mod_uint64 0%s9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("mod_uint64 0%s18446744073709551615 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_1_ssa(0); got != 0 { fmt.Printf("mod_uint64 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint64_ssa(1); got != 0 { fmt.Printf("mod_uint64 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_1_ssa(1); got != 0 { fmt.Printf("mod_uint64 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint64_ssa(4294967296); got != 1 { fmt.Printf("mod_uint64 1%s4294967296 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_uint64_1_ssa(4294967296); got != 0 { fmt.Printf("mod_uint64 4294967296%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint64_ssa(9223372036854775808); got != 1 { fmt.Printf("mod_uint64 1%s9223372036854775808 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_uint64_1_ssa(9223372036854775808); got != 0 { fmt.Printf("mod_uint64 9223372036854775808%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint64_ssa(18446744073709551615); got != 1 { fmt.Printf("mod_uint64 1%s18446744073709551615 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_uint64_1_ssa(18446744073709551615); got != 0 { fmt.Printf("mod_uint64 18446744073709551615%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_4294967296_ssa(0); got != 0 { fmt.Printf("mod_uint64 0%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_uint64_ssa(1); got != 0 { fmt.Printf("mod_uint64 4294967296%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_4294967296_ssa(1); got != 1 { fmt.Printf("mod_uint64 1%s4294967296 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_4294967296_uint64_ssa(4294967296); got != 0 { fmt.Printf("mod_uint64 4294967296%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("mod_uint64 4294967296%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_uint64_ssa(9223372036854775808); got != 4294967296 { fmt.Printf("mod_uint64 4294967296%s9223372036854775808 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_uint64_4294967296_ssa(9223372036854775808); got != 0 { fmt.Printf("mod_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_uint64_ssa(18446744073709551615); got != 4294967296 { fmt.Printf("mod_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_uint64_4294967296_ssa(18446744073709551615); got != 4294967295 { fmt.Printf("mod_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `%`, got) failed = true } if got := mod_uint64_9223372036854775808_ssa(0); got != 0 { fmt.Printf("mod_uint64 0%s9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_9223372036854775808_uint64_ssa(1); got != 0 { fmt.Printf("mod_uint64 9223372036854775808%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_9223372036854775808_ssa(1); got != 1 { fmt.Printf("mod_uint64 1%s9223372036854775808 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_9223372036854775808_uint64_ssa(4294967296); got != 0 { fmt.Printf("mod_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_9223372036854775808_ssa(4294967296); got != 4294967296 { fmt.Printf("mod_uint64 4294967296%s9223372036854775808 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("mod_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("mod_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775808 { fmt.Printf("mod_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `%`, got) failed = true } if got := mod_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("mod_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `%`, got) failed = true } if got := mod_uint64_18446744073709551615_ssa(0); got != 0 { fmt.Printf("mod_uint64 0%s18446744073709551615 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_18446744073709551615_uint64_ssa(1); got != 0 { fmt.Printf("mod_uint64 18446744073709551615%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_18446744073709551615_ssa(1); got != 1 { fmt.Printf("mod_uint64 1%s18446744073709551615 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_18446744073709551615_uint64_ssa(4294967296); got != 4294967295 { fmt.Printf("mod_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `%`, got) failed = true } if got := mod_uint64_18446744073709551615_ssa(4294967296); got != 4294967296 { fmt.Printf("mod_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("mod_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `%`, got) failed = true } if got := mod_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("mod_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `%`, got) failed = true } if got := mod_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("mod_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { fmt.Printf("mod_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `%`, got) failed = true } if got := and_0_uint64_ssa(0); got != 0 { fmt.Printf("and_uint64 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_0_ssa(0); got != 0 { fmt.Printf("and_uint64 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint64_ssa(1); got != 0 { fmt.Printf("and_uint64 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_0_ssa(1); got != 0 { fmt.Printf("and_uint64 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint64_ssa(4294967296); got != 0 { fmt.Printf("and_uint64 0%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_0_ssa(4294967296); got != 0 { fmt.Printf("and_uint64 4294967296%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("and_uint64 0%s9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_0_ssa(9223372036854775808); got != 0 { fmt.Printf("and_uint64 9223372036854775808%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("and_uint64 0%s18446744073709551615 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_0_ssa(18446744073709551615); got != 0 { fmt.Printf("and_uint64 18446744073709551615%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint64_ssa(0); got != 0 { fmt.Printf("and_uint64 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_1_ssa(0); got != 0 { fmt.Printf("and_uint64 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint64_ssa(1); got != 1 { fmt.Printf("and_uint64 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint64_1_ssa(1); got != 1 { fmt.Printf("and_uint64 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_uint64_ssa(4294967296); got != 0 { fmt.Printf("and_uint64 1%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_1_ssa(4294967296); got != 0 { fmt.Printf("and_uint64 4294967296%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("and_uint64 1%s9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_1_ssa(9223372036854775808); got != 0 { fmt.Printf("and_uint64 9223372036854775808%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint64_ssa(18446744073709551615); got != 1 { fmt.Printf("and_uint64 1%s18446744073709551615 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint64_1_ssa(18446744073709551615); got != 1 { fmt.Printf("and_uint64 18446744073709551615%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_4294967296_uint64_ssa(0); got != 0 { fmt.Printf("and_uint64 4294967296%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_4294967296_ssa(0); got != 0 { fmt.Printf("and_uint64 0%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_uint64_ssa(1); got != 0 { fmt.Printf("and_uint64 4294967296%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_4294967296_ssa(1); got != 0 { fmt.Printf("and_uint64 1%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_uint64 4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_uint64_4294967296_ssa(4294967296); got != 4294967296 { fmt.Printf("and_uint64 4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_4294967296_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("and_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_4294967296_ssa(9223372036854775808); got != 0 { fmt.Printf("and_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_uint64_ssa(18446744073709551615); got != 4294967296 { fmt.Printf("and_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_uint64_4294967296_ssa(18446744073709551615); got != 4294967296 { fmt.Printf("and_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_9223372036854775808_uint64_ssa(0); got != 0 { fmt.Printf("and_uint64 9223372036854775808%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_9223372036854775808_ssa(0); got != 0 { fmt.Printf("and_uint64 0%s9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775808_uint64_ssa(1); got != 0 { fmt.Printf("and_uint64 9223372036854775808%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_9223372036854775808_ssa(1); got != 0 { fmt.Printf("and_uint64 1%s9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775808_uint64_ssa(4294967296); got != 0 { fmt.Printf("and_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("and_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775808_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("and_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 9223372036854775808\n", `&`, got) failed = true } if got := and_uint64_9223372036854775808_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("and_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 9223372036854775808\n", `&`, got) failed = true } if got := and_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775808 { fmt.Printf("and_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `&`, got) failed = true } if got := and_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775808 { fmt.Printf("and_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775808\n", `&`, got) failed = true } if got := and_18446744073709551615_uint64_ssa(0); got != 0 { fmt.Printf("and_uint64 18446744073709551615%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint64_18446744073709551615_ssa(0); got != 0 { fmt.Printf("and_uint64 0%s18446744073709551615 = %d, wanted 0\n", `&`, got) failed = true } if got := and_18446744073709551615_uint64_ssa(1); got != 1 { fmt.Printf("and_uint64 18446744073709551615%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint64_18446744073709551615_ssa(1); got != 1 { fmt.Printf("and_uint64 1%s18446744073709551615 = %d, wanted 1\n", `&`, got) failed = true } if got := and_18446744073709551615_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_uint64_18446744073709551615_ssa(4294967296); got != 4294967296 { fmt.Printf("and_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("and_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775808\n", `&`, got) failed = true } if got := and_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("and_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `&`, got) failed = true } if got := and_18446744073709551615_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("and_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551615\n", `&`, got) failed = true } if got := and_uint64_18446744073709551615_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("and_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551615\n", `&`, got) failed = true } if got := or_0_uint64_ssa(0); got != 0 { fmt.Printf("or_uint64 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_uint64_0_ssa(0); got != 0 { fmt.Printf("or_uint64 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_uint64_ssa(1); got != 1 { fmt.Printf("or_uint64 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint64_0_ssa(1); got != 1 { fmt.Printf("or_uint64 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("or_uint64 0%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_uint64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("or_uint64 4294967296%s0 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_0_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("or_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `|`, got) failed = true } if got := or_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("or_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `|`, got) failed = true } if got := or_0_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_1_uint64_ssa(0); got != 1 { fmt.Printf("or_uint64 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint64_1_ssa(0); got != 1 { fmt.Printf("or_uint64 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint64_ssa(1); got != 1 { fmt.Printf("or_uint64 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint64_1_ssa(1); got != 1 { fmt.Printf("or_uint64 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint64_ssa(4294967296); got != 4294967297 { fmt.Printf("or_uint64 1%s4294967296 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_uint64_1_ssa(4294967296); got != 4294967297 { fmt.Printf("or_uint64 4294967296%s1 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_1_uint64_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("or_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `|`, got) failed = true } if got := or_uint64_1_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("or_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `|`, got) failed = true } if got := or_1_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_1_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_4294967296_uint64_ssa(0); got != 4294967296 { fmt.Printf("or_uint64 4294967296%s0 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_uint64_4294967296_ssa(0); got != 4294967296 { fmt.Printf("or_uint64 0%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_4294967296_uint64_ssa(1); got != 4294967297 { fmt.Printf("or_uint64 4294967296%s1 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_uint64_4294967296_ssa(1); got != 4294967297 { fmt.Printf("or_uint64 1%s4294967296 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_4294967296_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("or_uint64 4294967296%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_uint64_4294967296_ssa(4294967296); got != 4294967296 { fmt.Printf("or_uint64 4294967296%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_4294967296_uint64_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("or_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `|`, got) failed = true } if got := or_uint64_4294967296_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("or_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `|`, got) failed = true } if got := or_4294967296_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_4294967296_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { fmt.Printf("or_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `|`, got) failed = true } if got := or_uint64_9223372036854775808_ssa(0); got != 9223372036854775808 { fmt.Printf("or_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `|`, got) failed = true } if got := or_9223372036854775808_uint64_ssa(1); got != 9223372036854775809 { fmt.Printf("or_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `|`, got) failed = true } if got := or_uint64_9223372036854775808_ssa(1); got != 9223372036854775809 { fmt.Printf("or_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `|`, got) failed = true } if got := or_9223372036854775808_uint64_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("or_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `|`, got) failed = true } if got := or_uint64_9223372036854775808_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("or_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `|`, got) failed = true } if got := or_9223372036854775808_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("or_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 9223372036854775808\n", `|`, got) failed = true } if got := or_uint64_9223372036854775808_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("or_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 9223372036854775808\n", `|`, got) failed = true } if got := or_9223372036854775808_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_9223372036854775808_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_18446744073709551615_ssa(0); got != 18446744073709551615 { fmt.Printf("or_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_18446744073709551615_uint64_ssa(1); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_18446744073709551615_ssa(1); got != 18446744073709551615 { fmt.Printf("or_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_18446744073709551615_uint64_ssa(4294967296); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_18446744073709551615_ssa(4294967296); got != 18446744073709551615 { fmt.Printf("or_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_18446744073709551615_uint64_ssa(9223372036854775808); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_18446744073709551615_ssa(9223372036854775808); got != 18446744073709551615 { fmt.Printf("or_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_18446744073709551615_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := or_uint64_18446744073709551615_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("or_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) failed = true } if got := xor_0_uint64_ssa(0); got != 0 { fmt.Printf("xor_uint64 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint64_0_ssa(0); got != 0 { fmt.Printf("xor_uint64 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_uint64_ssa(1); got != 1 { fmt.Printf("xor_uint64 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint64_0_ssa(1); got != 1 { fmt.Printf("xor_uint64 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_uint64_ssa(4294967296); got != 4294967296 { fmt.Printf("xor_uint64 0%s4294967296 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_uint64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("xor_uint64 4294967296%s0 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_0_uint64_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("xor_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `^`, got) failed = true } if got := xor_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { fmt.Printf("xor_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `^`, got) failed = true } if got := xor_0_uint64_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("xor_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `^`, got) failed = true } if got := xor_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { fmt.Printf("xor_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `^`, got) failed = true } if got := xor_1_uint64_ssa(0); got != 1 { fmt.Printf("xor_uint64 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint64_1_ssa(0); got != 1 { fmt.Printf("xor_uint64 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_uint64_ssa(1); got != 0 { fmt.Printf("xor_uint64 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint64_1_ssa(1); got != 0 { fmt.Printf("xor_uint64 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_uint64_ssa(4294967296); got != 4294967297 { fmt.Printf("xor_uint64 1%s4294967296 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_uint64_1_ssa(4294967296); got != 4294967297 { fmt.Printf("xor_uint64 4294967296%s1 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_1_uint64_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("xor_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `^`, got) failed = true } if got := xor_uint64_1_ssa(9223372036854775808); got != 9223372036854775809 { fmt.Printf("xor_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `^`, got) failed = true } if got := xor_1_uint64_ssa(18446744073709551615); got != 18446744073709551614 { fmt.Printf("xor_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551614\n", `^`, got) failed = true } if got := xor_uint64_1_ssa(18446744073709551615); got != 18446744073709551614 { fmt.Printf("xor_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `^`, got) failed = true } if got := xor_4294967296_uint64_ssa(0); got != 4294967296 { fmt.Printf("xor_uint64 4294967296%s0 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_uint64_4294967296_ssa(0); got != 4294967296 { fmt.Printf("xor_uint64 0%s4294967296 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_4294967296_uint64_ssa(1); got != 4294967297 { fmt.Printf("xor_uint64 4294967296%s1 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_uint64_4294967296_ssa(1); got != 4294967297 { fmt.Printf("xor_uint64 1%s4294967296 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_4294967296_uint64_ssa(4294967296); got != 0 { fmt.Printf("xor_uint64 4294967296%s4294967296 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("xor_uint64 4294967296%s4294967296 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_4294967296_uint64_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("xor_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `^`, got) failed = true } if got := xor_uint64_4294967296_ssa(9223372036854775808); got != 9223372041149743104 { fmt.Printf("xor_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `^`, got) failed = true } if got := xor_4294967296_uint64_ssa(18446744073709551615); got != 18446744069414584319 { fmt.Printf("xor_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744069414584319\n", `^`, got) failed = true } if got := xor_uint64_4294967296_ssa(18446744073709551615); got != 18446744069414584319 { fmt.Printf("xor_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584319\n", `^`, got) failed = true } if got := xor_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { fmt.Printf("xor_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `^`, got) failed = true } if got := xor_uint64_9223372036854775808_ssa(0); got != 9223372036854775808 { fmt.Printf("xor_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `^`, got) failed = true } if got := xor_9223372036854775808_uint64_ssa(1); got != 9223372036854775809 { fmt.Printf("xor_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `^`, got) failed = true } if got := xor_uint64_9223372036854775808_ssa(1); got != 9223372036854775809 { fmt.Printf("xor_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `^`, got) failed = true } if got := xor_9223372036854775808_uint64_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("xor_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `^`, got) failed = true } if got := xor_uint64_9223372036854775808_ssa(4294967296); got != 9223372041149743104 { fmt.Printf("xor_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `^`, got) failed = true } if got := xor_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { fmt.Printf("xor_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { fmt.Printf("xor_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("xor_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775807 { fmt.Printf("xor_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { fmt.Printf("xor_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `^`, got) failed = true } if got := xor_uint64_18446744073709551615_ssa(0); got != 18446744073709551615 { fmt.Printf("xor_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `^`, got) failed = true } if got := xor_18446744073709551615_uint64_ssa(1); got != 18446744073709551614 { fmt.Printf("xor_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `^`, got) failed = true } if got := xor_uint64_18446744073709551615_ssa(1); got != 18446744073709551614 { fmt.Printf("xor_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551614\n", `^`, got) failed = true } if got := xor_18446744073709551615_uint64_ssa(4294967296); got != 18446744069414584319 { fmt.Printf("xor_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584319\n", `^`, got) failed = true } if got := xor_uint64_18446744073709551615_ssa(4294967296); got != 18446744069414584319 { fmt.Printf("xor_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744069414584319\n", `^`, got) failed = true } if got := xor_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("xor_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775807 { fmt.Printf("xor_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { fmt.Printf("xor_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { fmt.Printf("xor_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `^`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("add_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { fmt.Printf("add_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("add_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != 1 { fmt.Printf("add_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("add_int64 -9223372036854775808%s-4294967296 = %d, wanted 9223372032559808512\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("add_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(-1); got != 9223372036854775807 { fmt.Printf("add_int64 -9223372036854775808%s-1 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(-1); got != 9223372036854775807 { fmt.Printf("add_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(0); got != -9223372036854775808 { fmt.Printf("add_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(0); got != -9223372036854775808 { fmt.Printf("add_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775807 { fmt.Printf("add_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775807 { fmt.Printf("add_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("add_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("add_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -2 { fmt.Printf("add_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(9223372036854775806); got != -2 { fmt.Printf("add_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("add_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -1 { fmt.Printf("add_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != 1 { fmt.Printf("add_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != 1 { fmt.Printf("add_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 2 { fmt.Printf("add_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 2 { fmt.Printf("add_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 2\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(-4294967296); got != 9223372032559808513 { fmt.Printf("add_int64 -9223372036854775807%s-4294967296 = %d, wanted 9223372032559808513\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(-4294967296); got != 9223372032559808513 { fmt.Printf("add_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808513\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(-1); got != -9223372036854775808 { fmt.Printf("add_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(-1); got != -9223372036854775808 { fmt.Printf("add_int64 -1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(0); got != -9223372036854775807 { fmt.Printf("add_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(0); got != -9223372036854775807 { fmt.Printf("add_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775806 { fmt.Printf("add_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775806\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775806 { fmt.Printf("add_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775806\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("add_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("add_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("add_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(9223372036854775806); got != -1 { fmt.Printf("add_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg9223372036854775807_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("add_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_Neg9223372036854775807_ssa(9223372036854775807); got != 0 { fmt.Printf("add_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(-9223372036854775808); got != 9223372032559808512 { fmt.Printf("add_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(-9223372036854775808); got != 9223372032559808512 { fmt.Printf("add_int64 -9223372036854775808%s-4294967296 = %d, wanted 9223372032559808512\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(-9223372036854775807); got != 9223372032559808513 { fmt.Printf("add_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808513\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(-9223372036854775807); got != 9223372032559808513 { fmt.Printf("add_int64 -9223372036854775807%s-4294967296 = %d, wanted 9223372032559808513\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(-4294967296); got != -8589934592 { fmt.Printf("add_int64 -4294967296%s-4294967296 = %d, wanted -8589934592\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(-4294967296); got != -8589934592 { fmt.Printf("add_int64 -4294967296%s-4294967296 = %d, wanted -8589934592\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(-1); got != -4294967297 { fmt.Printf("add_int64 -4294967296%s-1 = %d, wanted -4294967297\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(-1); got != -4294967297 { fmt.Printf("add_int64 -1%s-4294967296 = %d, wanted -4294967297\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(0); got != -4294967296 { fmt.Printf("add_int64 -4294967296%s0 = %d, wanted -4294967296\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(0); got != -4294967296 { fmt.Printf("add_int64 0%s-4294967296 = %d, wanted -4294967296\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(1); got != -4294967295 { fmt.Printf("add_int64 -4294967296%s1 = %d, wanted -4294967295\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(1); got != -4294967295 { fmt.Printf("add_int64 1%s-4294967296 = %d, wanted -4294967295\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("add_int64 -4294967296%s4294967296 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(4294967296); got != 0 { fmt.Printf("add_int64 4294967296%s-4294967296 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(9223372036854775806); got != 9223372032559808510 { fmt.Printf("add_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808510\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(9223372036854775806); got != 9223372032559808510 { fmt.Printf("add_int64 9223372036854775806%s-4294967296 = %d, wanted 9223372032559808510\n", `+`, got) failed = true } if got := add_Neg4294967296_int64_ssa(9223372036854775807); got != 9223372032559808511 { fmt.Printf("add_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808511\n", `+`, got) failed = true } if got := add_int64_Neg4294967296_ssa(9223372036854775807); got != 9223372032559808511 { fmt.Printf("add_int64 9223372036854775807%s-4294967296 = %d, wanted 9223372032559808511\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("add_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("add_int64 -9223372036854775808%s-1 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("add_int64 -1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("add_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(-4294967296); got != -4294967297 { fmt.Printf("add_int64 -1%s-4294967296 = %d, wanted -4294967297\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(-4294967296); got != -4294967297 { fmt.Printf("add_int64 -4294967296%s-1 = %d, wanted -4294967297\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(-1); got != -2 { fmt.Printf("add_int64 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(-1); got != -2 { fmt.Printf("add_int64 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(0); got != -1 { fmt.Printf("add_int64 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(0); got != -1 { fmt.Printf("add_int64 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(1); got != 0 { fmt.Printf("add_int64 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(1); got != 0 { fmt.Printf("add_int64 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(4294967296); got != 4294967295 { fmt.Printf("add_int64 -1%s4294967296 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(4294967296); got != 4294967295 { fmt.Printf("add_int64 4294967296%s-1 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(9223372036854775806); got != 9223372036854775805 { fmt.Printf("add_int64 -1%s9223372036854775806 = %d, wanted 9223372036854775805\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(9223372036854775806); got != 9223372036854775805 { fmt.Printf("add_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775805\n", `+`, got) failed = true } if got := add_Neg1_int64_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("add_int64 -1%s9223372036854775807 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_int64_Neg1_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("add_int64 9223372036854775807%s-1 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_0_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("add_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_int64_0_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("add_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_0_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("add_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_int64_0_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("add_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_0_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("add_int64 0%s-4294967296 = %d, wanted -4294967296\n", `+`, got) failed = true } if got := add_int64_0_ssa(-4294967296); got != -4294967296 { fmt.Printf("add_int64 -4294967296%s0 = %d, wanted -4294967296\n", `+`, got) failed = true } if got := add_0_int64_ssa(-1); got != -1 { fmt.Printf("add_int64 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int64_0_ssa(-1); got != -1 { fmt.Printf("add_int64 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_0_int64_ssa(0); got != 0 { fmt.Printf("add_int64 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_0_ssa(0); got != 0 { fmt.Printf("add_int64 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_int64_ssa(1); got != 1 { fmt.Printf("add_int64 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int64_0_ssa(1); got != 1 { fmt.Printf("add_int64 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("add_int64 0%s4294967296 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_int64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("add_int64 4294967296%s0 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_0_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("add_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_int64_0_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("add_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_0_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("add_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_int64_0_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("add_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_1_int64_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("add_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_int64_1_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("add_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `+`, got) failed = true } if got := add_1_int64_ssa(-9223372036854775807); got != -9223372036854775806 { fmt.Printf("add_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775806\n", `+`, got) failed = true } if got := add_int64_1_ssa(-9223372036854775807); got != -9223372036854775806 { fmt.Printf("add_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775806\n", `+`, got) failed = true } if got := add_1_int64_ssa(-4294967296); got != -4294967295 { fmt.Printf("add_int64 1%s-4294967296 = %d, wanted -4294967295\n", `+`, got) failed = true } if got := add_int64_1_ssa(-4294967296); got != -4294967295 { fmt.Printf("add_int64 -4294967296%s1 = %d, wanted -4294967295\n", `+`, got) failed = true } if got := add_1_int64_ssa(-1); got != 0 { fmt.Printf("add_int64 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_1_ssa(-1); got != 0 { fmt.Printf("add_int64 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_1_int64_ssa(0); got != 1 { fmt.Printf("add_int64 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int64_1_ssa(0); got != 1 { fmt.Printf("add_int64 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_int64_ssa(1); got != 2 { fmt.Printf("add_int64 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int64_1_ssa(1); got != 2 { fmt.Printf("add_int64 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_int64_ssa(4294967296); got != 4294967297 { fmt.Printf("add_int64 1%s4294967296 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_int64_1_ssa(4294967296); got != 4294967297 { fmt.Printf("add_int64 4294967296%s1 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_1_int64_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("add_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_int64_1_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("add_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_1_int64_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("add_int64 1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_int64_1_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("add_int64 9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("add_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("add_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("add_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("add_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("add_int64 4294967296%s-4294967296 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(-4294967296); got != 0 { fmt.Printf("add_int64 -4294967296%s4294967296 = %d, wanted 0\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(-1); got != 4294967295 { fmt.Printf("add_int64 4294967296%s-1 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(-1); got != 4294967295 { fmt.Printf("add_int64 -1%s4294967296 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(0); got != 4294967296 { fmt.Printf("add_int64 4294967296%s0 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(0); got != 4294967296 { fmt.Printf("add_int64 0%s4294967296 = %d, wanted 4294967296\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(1); got != 4294967297 { fmt.Printf("add_int64 4294967296%s1 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(1); got != 4294967297 { fmt.Printf("add_int64 1%s4294967296 = %d, wanted 4294967297\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(4294967296); got != 8589934592 { fmt.Printf("add_int64 4294967296%s4294967296 = %d, wanted 8589934592\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(4294967296); got != 8589934592 { fmt.Printf("add_int64 4294967296%s4294967296 = %d, wanted 8589934592\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(9223372036854775806); got != -9223372032559808514 { fmt.Printf("add_int64 4294967296%s9223372036854775806 = %d, wanted -9223372032559808514\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(9223372036854775806); got != -9223372032559808514 { fmt.Printf("add_int64 9223372036854775806%s4294967296 = %d, wanted -9223372032559808514\n", `+`, got) failed = true } if got := add_4294967296_int64_ssa(9223372036854775807); got != -9223372032559808513 { fmt.Printf("add_int64 4294967296%s9223372036854775807 = %d, wanted -9223372032559808513\n", `+`, got) failed = true } if got := add_int64_4294967296_ssa(9223372036854775807); got != -9223372032559808513 { fmt.Printf("add_int64 9223372036854775807%s4294967296 = %d, wanted -9223372032559808513\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(-9223372036854775808); got != -2 { fmt.Printf("add_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(-9223372036854775808); got != -2 { fmt.Printf("add_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("add_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { fmt.Printf("add_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(-4294967296); got != 9223372032559808510 { fmt.Printf("add_int64 9223372036854775806%s-4294967296 = %d, wanted 9223372032559808510\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(-4294967296); got != 9223372032559808510 { fmt.Printf("add_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808510\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(-1); got != 9223372036854775805 { fmt.Printf("add_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775805\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(-1); got != 9223372036854775805 { fmt.Printf("add_int64 -1%s9223372036854775806 = %d, wanted 9223372036854775805\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(0); got != 9223372036854775806 { fmt.Printf("add_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(0); got != 9223372036854775806 { fmt.Printf("add_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("add_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(1); got != 9223372036854775807 { fmt.Printf("add_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(4294967296); got != -9223372032559808514 { fmt.Printf("add_int64 9223372036854775806%s4294967296 = %d, wanted -9223372032559808514\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(4294967296); got != -9223372032559808514 { fmt.Printf("add_int64 4294967296%s9223372036854775806 = %d, wanted -9223372032559808514\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(9223372036854775806); got != -4 { fmt.Printf("add_int64 9223372036854775806%s9223372036854775806 = %d, wanted -4\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(9223372036854775806); got != -4 { fmt.Printf("add_int64 9223372036854775806%s9223372036854775806 = %d, wanted -4\n", `+`, got) failed = true } if got := add_9223372036854775806_int64_ssa(9223372036854775807); got != -3 { fmt.Printf("add_int64 9223372036854775806%s9223372036854775807 = %d, wanted -3\n", `+`, got) failed = true } if got := add_int64_9223372036854775806_ssa(9223372036854775807); got != -3 { fmt.Printf("add_int64 9223372036854775807%s9223372036854775806 = %d, wanted -3\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(-9223372036854775808); got != -1 { fmt.Printf("add_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("add_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("add_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(-9223372036854775807); got != 0 { fmt.Printf("add_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(-4294967296); got != 9223372032559808511 { fmt.Printf("add_int64 9223372036854775807%s-4294967296 = %d, wanted 9223372032559808511\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(-4294967296); got != 9223372032559808511 { fmt.Printf("add_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808511\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(-1); got != 9223372036854775806 { fmt.Printf("add_int64 9223372036854775807%s-1 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(-1); got != 9223372036854775806 { fmt.Printf("add_int64 -1%s9223372036854775807 = %d, wanted 9223372036854775806\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(0); got != 9223372036854775807 { fmt.Printf("add_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(0); got != 9223372036854775807 { fmt.Printf("add_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(1); got != -9223372036854775808 { fmt.Printf("add_int64 9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(1); got != -9223372036854775808 { fmt.Printf("add_int64 1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(4294967296); got != -9223372032559808513 { fmt.Printf("add_int64 9223372036854775807%s4294967296 = %d, wanted -9223372032559808513\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(4294967296); got != -9223372032559808513 { fmt.Printf("add_int64 4294967296%s9223372036854775807 = %d, wanted -9223372032559808513\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(9223372036854775806); got != -3 { fmt.Printf("add_int64 9223372036854775807%s9223372036854775806 = %d, wanted -3\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(9223372036854775806); got != -3 { fmt.Printf("add_int64 9223372036854775806%s9223372036854775807 = %d, wanted -3\n", `+`, got) failed = true } if got := add_9223372036854775807_int64_ssa(9223372036854775807); got != -2 { fmt.Printf("add_int64 9223372036854775807%s9223372036854775807 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int64_9223372036854775807_ssa(9223372036854775807); got != -2 { fmt.Printf("add_int64 9223372036854775807%s9223372036854775807 = %d, wanted -2\n", `+`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("sub_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { fmt.Printf("sub_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("sub_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != 1 { fmt.Printf("sub_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(-4294967296); got != -9223372032559808512 { fmt.Printf("sub_int64 -9223372036854775808%s-4294967296 = %d, wanted -9223372032559808512\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("sub_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(-1); got != -9223372036854775807 { fmt.Printf("sub_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(-1); got != 9223372036854775807 { fmt.Printf("sub_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(0); got != -9223372036854775808 { fmt.Printf("sub_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(0); got != -9223372036854775808 { fmt.Printf("sub_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("sub_int64 -9223372036854775808%s1 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775807 { fmt.Printf("sub_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(4294967296); got != 9223372032559808512 { fmt.Printf("sub_int64 -9223372036854775808%s4294967296 = %d, wanted 9223372032559808512\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("sub_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(9223372036854775806); got != 2 { fmt.Printf("sub_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(9223372036854775806); got != -2 { fmt.Printf("sub_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg9223372036854775808_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("sub_int64 -9223372036854775808%s9223372036854775807 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -1 { fmt.Printf("sub_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != 1 { fmt.Printf("sub_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("sub_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("sub_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 0 { fmt.Printf("sub_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(-4294967296); got != -9223372032559808511 { fmt.Printf("sub_int64 -9223372036854775807%s-4294967296 = %d, wanted -9223372032559808511\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(-4294967296); got != 9223372032559808511 { fmt.Printf("sub_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808511\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(-1); got != -9223372036854775806 { fmt.Printf("sub_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775806\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(-1); got != 9223372036854775806 { fmt.Printf("sub_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(0); got != -9223372036854775807 { fmt.Printf("sub_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(0); got != 9223372036854775807 { fmt.Printf("sub_int64 0%s-9223372036854775807 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775808 { fmt.Printf("sub_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775808 { fmt.Printf("sub_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(4294967296); got != 9223372032559808513 { fmt.Printf("sub_int64 -9223372036854775807%s4294967296 = %d, wanted 9223372032559808513\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(4294967296); got != -9223372032559808513 { fmt.Printf("sub_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808513\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(9223372036854775806); got != 3 { fmt.Printf("sub_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 3\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(9223372036854775806); got != -3 { fmt.Printf("sub_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -3\n", `-`, got) failed = true } if got := sub_Neg9223372036854775807_int64_ssa(9223372036854775807); got != 2 { fmt.Printf("sub_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -2 { fmt.Printf("sub_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(-9223372036854775808); got != 9223372032559808512 { fmt.Printf("sub_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("sub_int64 -9223372036854775808%s-4294967296 = %d, wanted -9223372032559808512\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(-9223372036854775807); got != 9223372032559808511 { fmt.Printf("sub_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808511\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("sub_int64 -9223372036854775807%s-4294967296 = %d, wanted -9223372032559808511\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("sub_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(-4294967296); got != 0 { fmt.Printf("sub_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(-1); got != -4294967295 { fmt.Printf("sub_int64 -4294967296%s-1 = %d, wanted -4294967295\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(-1); got != 4294967295 { fmt.Printf("sub_int64 -1%s-4294967296 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(0); got != -4294967296 { fmt.Printf("sub_int64 -4294967296%s0 = %d, wanted -4294967296\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(0); got != 4294967296 { fmt.Printf("sub_int64 0%s-4294967296 = %d, wanted 4294967296\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(1); got != -4294967297 { fmt.Printf("sub_int64 -4294967296%s1 = %d, wanted -4294967297\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(1); got != 4294967297 { fmt.Printf("sub_int64 1%s-4294967296 = %d, wanted 4294967297\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(4294967296); got != -8589934592 { fmt.Printf("sub_int64 -4294967296%s4294967296 = %d, wanted -8589934592\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(4294967296); got != 8589934592 { fmt.Printf("sub_int64 4294967296%s-4294967296 = %d, wanted 8589934592\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(9223372036854775806); got != 9223372032559808514 { fmt.Printf("sub_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808514\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(9223372036854775806); got != -9223372032559808514 { fmt.Printf("sub_int64 9223372036854775806%s-4294967296 = %d, wanted -9223372032559808514\n", `-`, got) failed = true } if got := sub_Neg4294967296_int64_ssa(9223372036854775807); got != 9223372032559808513 { fmt.Printf("sub_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808513\n", `-`, got) failed = true } if got := sub_int64_Neg4294967296_ssa(9223372036854775807); got != -9223372032559808513 { fmt.Printf("sub_int64 9223372036854775807%s-4294967296 = %d, wanted -9223372032559808513\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("sub_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("sub_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(-9223372036854775807); got != 9223372036854775806 { fmt.Printf("sub_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(-9223372036854775807); got != -9223372036854775806 { fmt.Printf("sub_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775806\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(-4294967296); got != 4294967295 { fmt.Printf("sub_int64 -1%s-4294967296 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(-4294967296); got != -4294967295 { fmt.Printf("sub_int64 -4294967296%s-1 = %d, wanted -4294967295\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(-1); got != 0 { fmt.Printf("sub_int64 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(-1); got != 0 { fmt.Printf("sub_int64 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(0); got != -1 { fmt.Printf("sub_int64 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(0); got != 1 { fmt.Printf("sub_int64 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(1); got != -2 { fmt.Printf("sub_int64 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(1); got != 2 { fmt.Printf("sub_int64 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(4294967296); got != -4294967297 { fmt.Printf("sub_int64 -1%s4294967296 = %d, wanted -4294967297\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(4294967296); got != 4294967297 { fmt.Printf("sub_int64 4294967296%s-1 = %d, wanted 4294967297\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(9223372036854775806); got != -9223372036854775807 { fmt.Printf("sub_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("sub_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_Neg1_int64_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("sub_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_int64_Neg1_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("sub_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_0_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("sub_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_int64_0_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("sub_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_0_int64_ssa(-9223372036854775807); got != 9223372036854775807 { fmt.Printf("sub_int64 0%s-9223372036854775807 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_0_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("sub_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_0_int64_ssa(-4294967296); got != 4294967296 { fmt.Printf("sub_int64 0%s-4294967296 = %d, wanted 4294967296\n", `-`, got) failed = true } if got := sub_int64_0_ssa(-4294967296); got != -4294967296 { fmt.Printf("sub_int64 -4294967296%s0 = %d, wanted -4294967296\n", `-`, got) failed = true } if got := sub_0_int64_ssa(-1); got != 1 { fmt.Printf("sub_int64 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int64_0_ssa(-1); got != -1 { fmt.Printf("sub_int64 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_0_int64_ssa(0); got != 0 { fmt.Printf("sub_int64 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_0_ssa(0); got != 0 { fmt.Printf("sub_int64 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_int64_ssa(1); got != -1 { fmt.Printf("sub_int64 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int64_0_ssa(1); got != 1 { fmt.Printf("sub_int64 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_int64_ssa(4294967296); got != -4294967296 { fmt.Printf("sub_int64 0%s4294967296 = %d, wanted -4294967296\n", `-`, got) failed = true } if got := sub_int64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("sub_int64 4294967296%s0 = %d, wanted 4294967296\n", `-`, got) failed = true } if got := sub_0_int64_ssa(9223372036854775806); got != -9223372036854775806 { fmt.Printf("sub_int64 0%s9223372036854775806 = %d, wanted -9223372036854775806\n", `-`, got) failed = true } if got := sub_int64_0_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("sub_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `-`, got) failed = true } if got := sub_0_int64_ssa(9223372036854775807); got != -9223372036854775807 { fmt.Printf("sub_int64 0%s9223372036854775807 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_0_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("sub_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_1_int64_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("sub_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_1_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("sub_int64 -9223372036854775808%s1 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_1_int64_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("sub_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_int64_1_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("sub_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_1_int64_ssa(-4294967296); got != 4294967297 { fmt.Printf("sub_int64 1%s-4294967296 = %d, wanted 4294967297\n", `-`, got) failed = true } if got := sub_int64_1_ssa(-4294967296); got != -4294967297 { fmt.Printf("sub_int64 -4294967296%s1 = %d, wanted -4294967297\n", `-`, got) failed = true } if got := sub_1_int64_ssa(-1); got != 2 { fmt.Printf("sub_int64 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int64_1_ssa(-1); got != -2 { fmt.Printf("sub_int64 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_1_int64_ssa(0); got != 1 { fmt.Printf("sub_int64 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int64_1_ssa(0); got != -1 { fmt.Printf("sub_int64 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_1_int64_ssa(1); got != 0 { fmt.Printf("sub_int64 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_1_ssa(1); got != 0 { fmt.Printf("sub_int64 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_int64_ssa(4294967296); got != -4294967295 { fmt.Printf("sub_int64 1%s4294967296 = %d, wanted -4294967295\n", `-`, got) failed = true } if got := sub_int64_1_ssa(4294967296); got != 4294967295 { fmt.Printf("sub_int64 4294967296%s1 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_1_int64_ssa(9223372036854775806); got != -9223372036854775805 { fmt.Printf("sub_int64 1%s9223372036854775806 = %d, wanted -9223372036854775805\n", `-`, got) failed = true } if got := sub_int64_1_ssa(9223372036854775806); got != 9223372036854775805 { fmt.Printf("sub_int64 9223372036854775806%s1 = %d, wanted 9223372036854775805\n", `-`, got) failed = true } if got := sub_1_int64_ssa(9223372036854775807); got != -9223372036854775806 { fmt.Printf("sub_int64 1%s9223372036854775807 = %d, wanted -9223372036854775806\n", `-`, got) failed = true } if got := sub_int64_1_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("sub_int64 9223372036854775807%s1 = %d, wanted 9223372036854775806\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("sub_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(-9223372036854775808); got != 9223372032559808512 { fmt.Printf("sub_int64 -9223372036854775808%s4294967296 = %d, wanted 9223372032559808512\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(-9223372036854775807); got != -9223372032559808513 { fmt.Printf("sub_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808513\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(-9223372036854775807); got != 9223372032559808513 { fmt.Printf("sub_int64 -9223372036854775807%s4294967296 = %d, wanted 9223372032559808513\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(-4294967296); got != 8589934592 { fmt.Printf("sub_int64 4294967296%s-4294967296 = %d, wanted 8589934592\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(-4294967296); got != -8589934592 { fmt.Printf("sub_int64 -4294967296%s4294967296 = %d, wanted -8589934592\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(-1); got != 4294967297 { fmt.Printf("sub_int64 4294967296%s-1 = %d, wanted 4294967297\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(-1); got != -4294967297 { fmt.Printf("sub_int64 -1%s4294967296 = %d, wanted -4294967297\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(0); got != 4294967296 { fmt.Printf("sub_int64 4294967296%s0 = %d, wanted 4294967296\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(0); got != -4294967296 { fmt.Printf("sub_int64 0%s4294967296 = %d, wanted -4294967296\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(1); got != 4294967295 { fmt.Printf("sub_int64 4294967296%s1 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(1); got != -4294967295 { fmt.Printf("sub_int64 1%s4294967296 = %d, wanted -4294967295\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("sub_int64 4294967296%s4294967296 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("sub_int64 4294967296%s4294967296 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(9223372036854775806); got != -9223372032559808510 { fmt.Printf("sub_int64 4294967296%s9223372036854775806 = %d, wanted -9223372032559808510\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(9223372036854775806); got != 9223372032559808510 { fmt.Printf("sub_int64 9223372036854775806%s4294967296 = %d, wanted 9223372032559808510\n", `-`, got) failed = true } if got := sub_4294967296_int64_ssa(9223372036854775807); got != -9223372032559808511 { fmt.Printf("sub_int64 4294967296%s9223372036854775807 = %d, wanted -9223372032559808511\n", `-`, got) failed = true } if got := sub_int64_4294967296_ssa(9223372036854775807); got != 9223372032559808511 { fmt.Printf("sub_int64 9223372036854775807%s4294967296 = %d, wanted 9223372032559808511\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(-9223372036854775808); got != -2 { fmt.Printf("sub_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(-9223372036854775808); got != 2 { fmt.Printf("sub_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(-9223372036854775807); got != -3 { fmt.Printf("sub_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -3\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(-9223372036854775807); got != 3 { fmt.Printf("sub_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 3\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(-4294967296); got != -9223372032559808514 { fmt.Printf("sub_int64 9223372036854775806%s-4294967296 = %d, wanted -9223372032559808514\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(-4294967296); got != 9223372032559808514 { fmt.Printf("sub_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808514\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(-1); got != 9223372036854775807 { fmt.Printf("sub_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(-1); got != -9223372036854775807 { fmt.Printf("sub_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(0); got != 9223372036854775806 { fmt.Printf("sub_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(0); got != -9223372036854775806 { fmt.Printf("sub_int64 0%s9223372036854775806 = %d, wanted -9223372036854775806\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(1); got != 9223372036854775805 { fmt.Printf("sub_int64 9223372036854775806%s1 = %d, wanted 9223372036854775805\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(1); got != -9223372036854775805 { fmt.Printf("sub_int64 1%s9223372036854775806 = %d, wanted -9223372036854775805\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(4294967296); got != 9223372032559808510 { fmt.Printf("sub_int64 9223372036854775806%s4294967296 = %d, wanted 9223372032559808510\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(4294967296); got != -9223372032559808510 { fmt.Printf("sub_int64 4294967296%s9223372036854775806 = %d, wanted -9223372032559808510\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("sub_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(9223372036854775806); got != 0 { fmt.Printf("sub_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_9223372036854775806_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("sub_int64 9223372036854775806%s9223372036854775807 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int64_9223372036854775806_ssa(9223372036854775807); got != 1 { fmt.Printf("sub_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(-9223372036854775808); got != -1 { fmt.Printf("sub_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(-9223372036854775808); got != 1 { fmt.Printf("sub_int64 -9223372036854775808%s9223372036854775807 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(-9223372036854775807); got != -2 { fmt.Printf("sub_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(-9223372036854775807); got != 2 { fmt.Printf("sub_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(-4294967296); got != -9223372032559808513 { fmt.Printf("sub_int64 9223372036854775807%s-4294967296 = %d, wanted -9223372032559808513\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(-4294967296); got != 9223372032559808513 { fmt.Printf("sub_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808513\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(-1); got != -9223372036854775808 { fmt.Printf("sub_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(-1); got != -9223372036854775808 { fmt.Printf("sub_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(0); got != 9223372036854775807 { fmt.Printf("sub_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(0); got != -9223372036854775807 { fmt.Printf("sub_int64 0%s9223372036854775807 = %d, wanted -9223372036854775807\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(1); got != 9223372036854775806 { fmt.Printf("sub_int64 9223372036854775807%s1 = %d, wanted 9223372036854775806\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(1); got != -9223372036854775806 { fmt.Printf("sub_int64 1%s9223372036854775807 = %d, wanted -9223372036854775806\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(4294967296); got != 9223372032559808511 { fmt.Printf("sub_int64 9223372036854775807%s4294967296 = %d, wanted 9223372032559808511\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("sub_int64 4294967296%s9223372036854775807 = %d, wanted -9223372032559808511\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(9223372036854775806); got != 1 { fmt.Printf("sub_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(9223372036854775806); got != -1 { fmt.Printf("sub_int64 9223372036854775806%s9223372036854775807 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_9223372036854775807_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("sub_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int64_9223372036854775807_ssa(9223372036854775807); got != 0 { fmt.Printf("sub_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `-`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 1 { fmt.Printf("div_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 1 { fmt.Printf("div_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("div_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(-4294967296); got != 2147483648 { fmt.Printf("div_int64 -9223372036854775808%s-4294967296 = %d, wanted 2147483648\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 -4294967296%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(-1); got != -9223372036854775808 { fmt.Printf("div_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(-1); got != 0 { fmt.Printf("div_int64 -1%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(0); got != 0 { fmt.Printf("div_int64 0%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775808 { fmt.Printf("div_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775808\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(1); got != 0 { fmt.Printf("div_int64 1%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(4294967296); got != -2147483648 { fmt.Printf("div_int64 -9223372036854775808%s4294967296 = %d, wanted -2147483648\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("div_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("div_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("div_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775808_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != 1 { fmt.Printf("div_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("div_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 1 { fmt.Printf("div_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(-4294967296); got != 2147483647 { fmt.Printf("div_int64 -9223372036854775807%s-4294967296 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 -4294967296%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(-1); got != 9223372036854775807 { fmt.Printf("div_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(-1); got != 0 { fmt.Printf("div_int64 -1%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(0); got != 0 { fmt.Printf("div_int64 0%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775807 { fmt.Printf("div_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(1); got != 0 { fmt.Printf("div_int64 1%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(4294967296); got != -2147483647 { fmt.Printf("div_int64 -9223372036854775807%s4294967296 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(4294967296); got != 0 { fmt.Printf("div_int64 4294967296%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("div_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg9223372036854775807_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("div_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -1 { fmt.Printf("div_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 -4294967296%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(-9223372036854775808); got != 2147483648 { fmt.Printf("div_int64 -9223372036854775808%s-4294967296 = %d, wanted 2147483648\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 -4294967296%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(-9223372036854775807); got != 2147483647 { fmt.Printf("div_int64 -9223372036854775807%s-4294967296 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(-4294967296); got != 1 { fmt.Printf("div_int64 -4294967296%s-4294967296 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(-4294967296); got != 1 { fmt.Printf("div_int64 -4294967296%s-4294967296 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(-1); got != 4294967296 { fmt.Printf("div_int64 -4294967296%s-1 = %d, wanted 4294967296\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(-1); got != 0 { fmt.Printf("div_int64 -1%s-4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(0); got != 0 { fmt.Printf("div_int64 0%s-4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(1); got != -4294967296 { fmt.Printf("div_int64 -4294967296%s1 = %d, wanted -4294967296\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(1); got != 0 { fmt.Printf("div_int64 1%s-4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(4294967296); got != -1 { fmt.Printf("div_int64 -4294967296%s4294967296 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(4294967296); got != -1 { fmt.Printf("div_int64 4294967296%s-4294967296 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 -4294967296%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(9223372036854775806); got != -2147483647 { fmt.Printf("div_int64 9223372036854775806%s-4294967296 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_Neg4294967296_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 -4294967296%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg4294967296_ssa(9223372036854775807); got != -2147483647 { fmt.Printf("div_int64 9223372036854775807%s-4294967296 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 -1%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("div_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 -1%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(-9223372036854775807); got != 9223372036854775807 { fmt.Printf("div_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 -1%s-4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(-4294967296); got != 4294967296 { fmt.Printf("div_int64 -4294967296%s-1 = %d, wanted 4294967296\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(-1); got != 1 { fmt.Printf("div_int64 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(-1); got != 1 { fmt.Printf("div_int64 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(0); got != 0 { fmt.Printf("div_int64 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(1); got != -1 { fmt.Printf("div_int64 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(1); got != -1 { fmt.Printf("div_int64 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(4294967296); got != 0 { fmt.Printf("div_int64 -1%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(4294967296); got != -4294967296 { fmt.Printf("div_int64 4294967296%s-1 = %d, wanted -4294967296\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 -1%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(9223372036854775806); got != -9223372036854775806 { fmt.Printf("div_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775806\n", `/`, got) failed = true } if got := div_Neg1_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 -1%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_Neg1_ssa(9223372036854775807); got != -9223372036854775807 { fmt.Printf("div_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `/`, got) failed = true } if got := div_0_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 0%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 0%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 0%s-4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(-1); got != 0 { fmt.Printf("div_int64 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(1); got != 0 { fmt.Printf("div_int64 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(4294967296); got != 0 { fmt.Printf("div_int64 0%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 0%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 0%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 1%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_1_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("div_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775808\n", `/`, got) failed = true } if got := div_1_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 1%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_1_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("div_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `/`, got) failed = true } if got := div_1_int64_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 1%s-4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_1_ssa(-4294967296); got != -4294967296 { fmt.Printf("div_int64 -4294967296%s1 = %d, wanted -4294967296\n", `/`, got) failed = true } if got := div_1_int64_ssa(-1); got != -1 { fmt.Printf("div_int64 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_1_ssa(-1); got != -1 { fmt.Printf("div_int64 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_1_ssa(0); got != 0 { fmt.Printf("div_int64 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int64_ssa(1); got != 1 { fmt.Printf("div_int64 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_1_ssa(1); got != 1 { fmt.Printf("div_int64 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_int64_ssa(4294967296); got != 0 { fmt.Printf("div_int64 1%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_1_ssa(4294967296); got != 4294967296 { fmt.Printf("div_int64 4294967296%s1 = %d, wanted 4294967296\n", `/`, got) failed = true } if got := div_1_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 1%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_1_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("div_int64 9223372036854775806%s1 = %d, wanted 9223372036854775806\n", `/`, got) failed = true } if got := div_1_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 1%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_1_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("div_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(-9223372036854775808); got != -2147483648 { fmt.Printf("div_int64 -9223372036854775808%s4294967296 = %d, wanted -2147483648\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 4294967296%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(-9223372036854775807); got != -2147483647 { fmt.Printf("div_int64 -9223372036854775807%s4294967296 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(-4294967296); got != -1 { fmt.Printf("div_int64 4294967296%s-4294967296 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(-4294967296); got != -1 { fmt.Printf("div_int64 -4294967296%s4294967296 = %d, wanted -1\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(-1); got != -4294967296 { fmt.Printf("div_int64 4294967296%s-1 = %d, wanted -4294967296\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(-1); got != 0 { fmt.Printf("div_int64 -1%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(0); got != 0 { fmt.Printf("div_int64 0%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(1); got != 4294967296 { fmt.Printf("div_int64 4294967296%s1 = %d, wanted 4294967296\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(1); got != 0 { fmt.Printf("div_int64 1%s4294967296 = %d, wanted 0\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(4294967296); got != 1 { fmt.Printf("div_int64 4294967296%s4294967296 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(4294967296); got != 1 { fmt.Printf("div_int64 4294967296%s4294967296 = %d, wanted 1\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 4294967296%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(9223372036854775806); got != 2147483647 { fmt.Printf("div_int64 9223372036854775806%s4294967296 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_4294967296_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 4294967296%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_4294967296_ssa(9223372036854775807); got != 2147483647 { fmt.Printf("div_int64 9223372036854775807%s4294967296 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(-9223372036854775808); got != -1 { fmt.Printf("div_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -1\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("div_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { fmt.Printf("div_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(-4294967296); got != -2147483647 { fmt.Printf("div_int64 9223372036854775806%s-4294967296 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 -4294967296%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(-1); got != -9223372036854775806 { fmt.Printf("div_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775806\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(-1); got != 0 { fmt.Printf("div_int64 -1%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(0); got != 0 { fmt.Printf("div_int64 0%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(1); got != 9223372036854775806 { fmt.Printf("div_int64 9223372036854775806%s1 = %d, wanted 9223372036854775806\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(1); got != 0 { fmt.Printf("div_int64 1%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(4294967296); got != 2147483647 { fmt.Printf("div_int64 9223372036854775806%s4294967296 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(4294967296); got != 0 { fmt.Printf("div_int64 4294967296%s9223372036854775806 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(9223372036854775806); got != 1 { fmt.Printf("div_int64 9223372036854775806%s9223372036854775806 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(9223372036854775806); got != 1 { fmt.Printf("div_int64 9223372036854775806%s9223372036854775806 = %d, wanted 1\n", `/`, got) failed = true } if got := div_9223372036854775806_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("div_int64 9223372036854775806%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_9223372036854775806_ssa(9223372036854775807); got != 1 { fmt.Printf("div_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("div_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("div_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("div_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(-9223372036854775807); got != -1 { fmt.Printf("div_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(-4294967296); got != -2147483647 { fmt.Printf("div_int64 9223372036854775807%s-4294967296 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(-4294967296); got != 0 { fmt.Printf("div_int64 -4294967296%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(-1); got != -9223372036854775807 { fmt.Printf("div_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(-1); got != 0 { fmt.Printf("div_int64 -1%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(0); got != 0 { fmt.Printf("div_int64 0%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("div_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(1); got != 0 { fmt.Printf("div_int64 1%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(4294967296); got != 2147483647 { fmt.Printf("div_int64 9223372036854775807%s4294967296 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(4294967296); got != 0 { fmt.Printf("div_int64 4294967296%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(9223372036854775806); got != 1 { fmt.Printf("div_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(9223372036854775806); got != 0 { fmt.Printf("div_int64 9223372036854775806%s9223372036854775807 = %d, wanted 0\n", `/`, got) failed = true } if got := div_9223372036854775807_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("div_int64 9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int64_9223372036854775807_ssa(9223372036854775807); got != 1 { fmt.Printf("div_int64 9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 -4294967296%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(-1); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(-1); got != -9223372036854775808 { fmt.Printf("mul_int64 -1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775808 { fmt.Printf("mul_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(9223372036854775806); got != 0 { fmt.Printf("mul_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("mul_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("mul_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 1 { fmt.Printf("mul_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("mul_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(-4294967296); got != -4294967296 { fmt.Printf("mul_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(-1); got != 9223372036854775807 { fmt.Printf("mul_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(-1); got != 9223372036854775807 { fmt.Printf("mul_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 -9223372036854775807%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s-9223372036854775807 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775807 { fmt.Printf("mul_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775807 { fmt.Printf("mul_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("mul_int64 -9223372036854775807%s4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(4294967296); got != 4294967296 { fmt.Printf("mul_int64 4294967296%s-9223372036854775807 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mul_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_Neg9223372036854775807_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("mul_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -1 { fmt.Printf("mul_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -4294967296%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(-9223372036854775807); got != -4294967296 { fmt.Printf("mul_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(-9223372036854775807); got != -4294967296 { fmt.Printf("mul_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(-1); got != 4294967296 { fmt.Printf("mul_int64 -4294967296%s-1 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(-1); got != 4294967296 { fmt.Printf("mul_int64 -1%s-4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 -4294967296%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(1); got != -4294967296 { fmt.Printf("mul_int64 -4294967296%s1 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(1); got != -4294967296 { fmt.Printf("mul_int64 1%s-4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 -4294967296%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 4294967296%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(9223372036854775806); got != 8589934592 { fmt.Printf("mul_int64 -4294967296%s9223372036854775806 = %d, wanted 8589934592\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(9223372036854775806); got != 8589934592 { fmt.Printf("mul_int64 9223372036854775806%s-4294967296 = %d, wanted 8589934592\n", `*`, got) failed = true } if got := mul_Neg4294967296_int64_ssa(9223372036854775807); got != 4294967296 { fmt.Printf("mul_int64 -4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg4294967296_ssa(9223372036854775807); got != 4294967296 { fmt.Printf("mul_int64 9223372036854775807%s-4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 -1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(-9223372036854775807); got != 9223372036854775807 { fmt.Printf("mul_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(-9223372036854775807); got != 9223372036854775807 { fmt.Printf("mul_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(-4294967296); got != 4294967296 { fmt.Printf("mul_int64 -1%s-4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(-4294967296); got != 4294967296 { fmt.Printf("mul_int64 -4294967296%s-1 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(-1); got != 1 { fmt.Printf("mul_int64 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(-1); got != 1 { fmt.Printf("mul_int64 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(1); got != -1 { fmt.Printf("mul_int64 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(1); got != -1 { fmt.Printf("mul_int64 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(4294967296); got != -4294967296 { fmt.Printf("mul_int64 -1%s4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(4294967296); got != -4294967296 { fmt.Printf("mul_int64 4294967296%s-1 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(9223372036854775806); got != -9223372036854775806 { fmt.Printf("mul_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(9223372036854775806); got != -9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_Neg1_int64_ssa(9223372036854775807); got != -9223372036854775807 { fmt.Printf("mul_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_Neg1_ssa(9223372036854775807); got != -9223372036854775807 { fmt.Printf("mul_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_0_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 0%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("mul_int64 0%s-9223372036854775807 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(-9223372036854775807); got != 0 { fmt.Printf("mul_int64 -9223372036854775807%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 0%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 -4294967296%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(-1); got != 0 { fmt.Printf("mul_int64 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(-1); got != 0 { fmt.Printf("mul_int64 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(1); got != 0 { fmt.Printf("mul_int64 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(1); got != 0 { fmt.Printf("mul_int64 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 0%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 4294967296%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("mul_int64 0%s9223372036854775806 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(9223372036854775806); got != 0 { fmt.Printf("mul_int64 9223372036854775806%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("mul_int64 0%s9223372036854775807 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_0_ssa(9223372036854775807); got != 0 { fmt.Printf("mul_int64 9223372036854775807%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_1_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_1_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("mul_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_1_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("mul_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_1_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("mul_int64 1%s-4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_1_ssa(-4294967296); got != -4294967296 { fmt.Printf("mul_int64 -4294967296%s1 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_1_int64_ssa(-1); got != -1 { fmt.Printf("mul_int64 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int64_1_ssa(-1); got != -1 { fmt.Printf("mul_int64 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_1_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_1_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int64_ssa(1); got != 1 { fmt.Printf("mul_int64 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int64_1_ssa(1); got != 1 { fmt.Printf("mul_int64 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("mul_int64 1%s4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_1_ssa(4294967296); got != 4294967296 { fmt.Printf("mul_int64 4294967296%s1 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_1_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mul_int64 1%s9223372036854775806 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_1_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s1 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_1_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("mul_int64 1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_1_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("mul_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(-9223372036854775807); got != 4294967296 { fmt.Printf("mul_int64 4294967296%s-9223372036854775807 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(-9223372036854775807); got != 4294967296 { fmt.Printf("mul_int64 -9223372036854775807%s4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 4294967296%s-4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(-4294967296); got != 0 { fmt.Printf("mul_int64 -4294967296%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(-1); got != -4294967296 { fmt.Printf("mul_int64 4294967296%s-1 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(-1); got != -4294967296 { fmt.Printf("mul_int64 -1%s4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 4294967296%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(1); got != 4294967296 { fmt.Printf("mul_int64 4294967296%s1 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(1); got != 4294967296 { fmt.Printf("mul_int64 1%s4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 4294967296%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("mul_int64 4294967296%s4294967296 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(9223372036854775806); got != -8589934592 { fmt.Printf("mul_int64 4294967296%s9223372036854775806 = %d, wanted -8589934592\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(9223372036854775806); got != -8589934592 { fmt.Printf("mul_int64 9223372036854775806%s4294967296 = %d, wanted -8589934592\n", `*`, got) failed = true } if got := mul_4294967296_int64_ssa(9223372036854775807); got != -4294967296 { fmt.Printf("mul_int64 4294967296%s9223372036854775807 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_4294967296_ssa(9223372036854775807); got != -4294967296 { fmt.Printf("mul_int64 9223372036854775807%s4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(-9223372036854775808); got != 0 { fmt.Printf("mul_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(-9223372036854775807); got != 9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(-9223372036854775807); got != 9223372036854775806 { fmt.Printf("mul_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(-4294967296); got != 8589934592 { fmt.Printf("mul_int64 9223372036854775806%s-4294967296 = %d, wanted 8589934592\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(-4294967296); got != 8589934592 { fmt.Printf("mul_int64 -4294967296%s9223372036854775806 = %d, wanted 8589934592\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(-1); got != -9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(-1); got != -9223372036854775806 { fmt.Printf("mul_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 9223372036854775806%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s9223372036854775806 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(1); got != 9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s1 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(1); got != 9223372036854775806 { fmt.Printf("mul_int64 1%s9223372036854775806 = %d, wanted 9223372036854775806\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(4294967296); got != -8589934592 { fmt.Printf("mul_int64 9223372036854775806%s4294967296 = %d, wanted -8589934592\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(4294967296); got != -8589934592 { fmt.Printf("mul_int64 4294967296%s9223372036854775806 = %d, wanted -8589934592\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(9223372036854775806); got != 4 { fmt.Printf("mul_int64 9223372036854775806%s9223372036854775806 = %d, wanted 4\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(9223372036854775806); got != 4 { fmt.Printf("mul_int64 9223372036854775806%s9223372036854775806 = %d, wanted 4\n", `*`, got) failed = true } if got := mul_9223372036854775806_int64_ssa(9223372036854775807); got != -9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s9223372036854775807 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_9223372036854775806_ssa(9223372036854775807); got != -9223372036854775806 { fmt.Printf("mul_int64 9223372036854775807%s9223372036854775806 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("mul_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -9223372036854775808\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("mul_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(-9223372036854775807); got != -1 { fmt.Printf("mul_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(-4294967296); got != 4294967296 { fmt.Printf("mul_int64 9223372036854775807%s-4294967296 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(-4294967296); got != 4294967296 { fmt.Printf("mul_int64 -4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(-1); got != -9223372036854775807 { fmt.Printf("mul_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(-1); got != -9223372036854775807 { fmt.Printf("mul_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775807\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(0); got != 0 { fmt.Printf("mul_int64 9223372036854775807%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(0); got != 0 { fmt.Printf("mul_int64 0%s9223372036854775807 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("mul_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(1); got != 9223372036854775807 { fmt.Printf("mul_int64 1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(4294967296); got != -4294967296 { fmt.Printf("mul_int64 9223372036854775807%s4294967296 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(4294967296); got != -4294967296 { fmt.Printf("mul_int64 4294967296%s9223372036854775807 = %d, wanted -4294967296\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(9223372036854775806); got != -9223372036854775806 { fmt.Printf("mul_int64 9223372036854775807%s9223372036854775806 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(9223372036854775806); got != -9223372036854775806 { fmt.Printf("mul_int64 9223372036854775806%s9223372036854775807 = %d, wanted -9223372036854775806\n", `*`, got) failed = true } if got := mul_9223372036854775807_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("mul_int64 9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int64_9223372036854775807_ssa(9223372036854775807); got != 1 { fmt.Printf("mul_int64 9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `*`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("mod_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("mod_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(-4294967296); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s-9223372036854775808 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(-1); got != -1 { fmt.Printf("mod_int64 -1%s-9223372036854775808 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s-9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(1); got != 1 { fmt.Printf("mod_int64 1%s-9223372036854775808 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(4294967296); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s-9223372036854775808 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -2 { fmt.Printf("mod_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mod_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 9223372036854775806\n", `%`, got) failed = true } if got := mod_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("mod_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775808_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("mod_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("mod_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("mod_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(-4294967296); got != -4294967295 { fmt.Printf("mod_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967295\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(-4294967296); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(-1); got != -1 { fmt.Printf("mod_int64 -1%s-9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s-9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(1); got != 1 { fmt.Printf("mod_int64 1%s-9223372036854775807 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(4294967296); got != -4294967295 { fmt.Printf("mod_int64 -9223372036854775807%s4294967296 = %d, wanted -4294967295\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(4294967296); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s-9223372036854775807 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("mod_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mod_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `%`, got) failed = true } if got := mod_Neg9223372036854775807_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg9223372036854775807_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(-9223372036854775808); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s-9223372036854775808 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(-9223372036854775807); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(-9223372036854775807); got != -4294967295 { fmt.Printf("mod_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967295\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 -4294967296%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(-1); got != -1 { fmt.Printf("mod_int64 -1%s-4294967296 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 -4294967296%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(1); got != 1 { fmt.Printf("mod_int64 1%s-4294967296 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 -4294967296%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 4294967296%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(9223372036854775806); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s9223372036854775806 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(9223372036854775806); got != 4294967294 { fmt.Printf("mod_int64 9223372036854775806%s-4294967296 = %d, wanted 4294967294\n", `%`, got) failed = true } if got := mod_Neg4294967296_int64_ssa(9223372036854775807); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s9223372036854775807 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_int64_Neg4294967296_ssa(9223372036854775807); got != 4294967295 { fmt.Printf("mod_int64 9223372036854775807%s-4294967296 = %d, wanted 4294967295\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(-9223372036854775808); got != -1 { fmt.Printf("mod_int64 -1%s-9223372036854775808 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("mod_int64 -1%s-9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(-4294967296); got != -1 { fmt.Printf("mod_int64 -1%s-4294967296 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 -4294967296%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(-1); got != 0 { fmt.Printf("mod_int64 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(1); got != 0 { fmt.Printf("mod_int64 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(4294967296); got != -1 { fmt.Printf("mod_int64 -1%s4294967296 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 4294967296%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("mod_int64 -1%s9223372036854775806 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(9223372036854775806); got != 0 { fmt.Printf("mod_int64 9223372036854775806%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("mod_int64 -1%s9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_Neg1_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 0%s-9223372036854775808 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 0%s-9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 0%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 0%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("mod_int64 0%s9223372036854775806 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 0%s9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(-9223372036854775808); got != 1 { fmt.Printf("mod_int64 1%s-9223372036854775808 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_1_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("mod_int64 1%s-9223372036854775807 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_1_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(-4294967296); got != 1 { fmt.Printf("mod_int64 1%s-4294967296 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_1_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 -4294967296%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_1_ssa(-1); got != 0 { fmt.Printf("mod_int64 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_1_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_1_ssa(1); got != 0 { fmt.Printf("mod_int64 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(4294967296); got != 1 { fmt.Printf("mod_int64 1%s4294967296 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_1_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 4294967296%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(9223372036854775806); got != 1 { fmt.Printf("mod_int64 1%s9223372036854775806 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_1_ssa(9223372036854775806); got != 0 { fmt.Printf("mod_int64 9223372036854775806%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("mod_int64 1%s9223372036854775807 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_1_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(-9223372036854775808); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s-9223372036854775808 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(-9223372036854775808); got != 0 { fmt.Printf("mod_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(-9223372036854775807); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s-9223372036854775807 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(-9223372036854775807); got != -4294967295 { fmt.Printf("mod_int64 -9223372036854775807%s4294967296 = %d, wanted -4294967295\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 4294967296%s-4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(-4294967296); got != 0 { fmt.Printf("mod_int64 -4294967296%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 4294967296%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(-1); got != -1 { fmt.Printf("mod_int64 -1%s4294967296 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 4294967296%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(1); got != 1 { fmt.Printf("mod_int64 1%s4294967296 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 4294967296%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("mod_int64 4294967296%s4294967296 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(9223372036854775806); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s9223372036854775806 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(9223372036854775806); got != 4294967294 { fmt.Printf("mod_int64 9223372036854775806%s4294967296 = %d, wanted 4294967294\n", `%`, got) failed = true } if got := mod_4294967296_int64_ssa(9223372036854775807); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_int64_4294967296_ssa(9223372036854775807); got != 4294967295 { fmt.Printf("mod_int64 9223372036854775807%s4294967296 = %d, wanted 4294967295\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(-9223372036854775808); got != 9223372036854775806 { fmt.Printf("mod_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 9223372036854775806\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(-9223372036854775808); got != -2 { fmt.Printf("mod_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(-9223372036854775807); got != 9223372036854775806 { fmt.Printf("mod_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { fmt.Printf("mod_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(-4294967296); got != 4294967294 { fmt.Printf("mod_int64 9223372036854775806%s-4294967296 = %d, wanted 4294967294\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(-4294967296); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s9223372036854775806 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 9223372036854775806%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(-1); got != -1 { fmt.Printf("mod_int64 -1%s9223372036854775806 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s9223372036854775806 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 9223372036854775806%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(1); got != 1 { fmt.Printf("mod_int64 1%s9223372036854775806 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(4294967296); got != 4294967294 { fmt.Printf("mod_int64 9223372036854775806%s4294967296 = %d, wanted 4294967294\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(4294967296); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s9223372036854775806 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("mod_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(9223372036854775806); got != 0 { fmt.Printf("mod_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_9223372036854775806_int64_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("mod_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775806\n", `%`, got) failed = true } if got := mod_int64_9223372036854775806_ssa(9223372036854775807); got != 1 { fmt.Printf("mod_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("mod_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("mod_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(-9223372036854775807); got != 0 { fmt.Printf("mod_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(-4294967296); got != 4294967295 { fmt.Printf("mod_int64 9223372036854775807%s-4294967296 = %d, wanted 4294967295\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(-4294967296); got != -4294967296 { fmt.Printf("mod_int64 -4294967296%s9223372036854775807 = %d, wanted -4294967296\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(-1); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(-1); got != -1 { fmt.Printf("mod_int64 -1%s9223372036854775807 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(0); got != 0 { fmt.Printf("mod_int64 0%s9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(1); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(1); got != 1 { fmt.Printf("mod_int64 1%s9223372036854775807 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(4294967296); got != 4294967295 { fmt.Printf("mod_int64 9223372036854775807%s4294967296 = %d, wanted 4294967295\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(4294967296); got != 4294967296 { fmt.Printf("mod_int64 4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(9223372036854775806); got != 1 { fmt.Printf("mod_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("mod_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775806\n", `%`, got) failed = true } if got := mod_9223372036854775807_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int64_9223372036854775807_ssa(9223372036854775807); got != 0 { fmt.Printf("mod_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `%`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(-4294967296); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-4294967296 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(-4294967296); got != -9223372036854775808 { fmt.Printf("and_int64 -4294967296%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(-1); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(-1); got != -9223372036854775808 { fmt.Printf("and_int64 -1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(0); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(0); got != 0 { fmt.Printf("and_int64 0%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(1); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(1); got != 0 { fmt.Printf("and_int64 1%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(4294967296); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(4294967296); got != 0 { fmt.Printf("and_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775808_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775808_ssa(9223372036854775807); got != 0 { fmt.Printf("and_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("and_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("and_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(-4294967296); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775807%s-4294967296 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(-4294967296); got != -9223372036854775808 { fmt.Printf("and_int64 -4294967296%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(-1); got != -9223372036854775807 { fmt.Printf("and_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(-1); got != -9223372036854775807 { fmt.Printf("and_int64 -1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(0); got != 0 { fmt.Printf("and_int64 -9223372036854775807%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(0); got != 0 { fmt.Printf("and_int64 0%s-9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(1); got != 1 { fmt.Printf("and_int64 -9223372036854775807%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(1); got != 1 { fmt.Printf("and_int64 1%s-9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(4294967296); got != 0 { fmt.Printf("and_int64 -9223372036854775807%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(4294967296); got != 0 { fmt.Printf("and_int64 4294967296%s-9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg9223372036854775807_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("and_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_Neg9223372036854775807_ssa(9223372036854775807); got != 1 { fmt.Printf("and_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -4294967296%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-4294967296 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("and_int64 -4294967296%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775807%s-4294967296 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("and_int64 -4294967296%s-4294967296 = %d, wanted -4294967296\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(-4294967296); got != -4294967296 { fmt.Printf("and_int64 -4294967296%s-4294967296 = %d, wanted -4294967296\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(-1); got != -4294967296 { fmt.Printf("and_int64 -4294967296%s-1 = %d, wanted -4294967296\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(-1); got != -4294967296 { fmt.Printf("and_int64 -1%s-4294967296 = %d, wanted -4294967296\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(0); got != 0 { fmt.Printf("and_int64 -4294967296%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(0); got != 0 { fmt.Printf("and_int64 0%s-4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(1); got != 0 { fmt.Printf("and_int64 -4294967296%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(1); got != 0 { fmt.Printf("and_int64 1%s-4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 -4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s-4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(9223372036854775806); got != 9223372032559808512 { fmt.Printf("and_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(9223372036854775806); got != 9223372032559808512 { fmt.Printf("and_int64 9223372036854775806%s-4294967296 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_Neg4294967296_int64_ssa(9223372036854775807); got != 9223372032559808512 { fmt.Printf("and_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_int64_Neg4294967296_ssa(9223372036854775807); got != 9223372032559808512 { fmt.Printf("and_int64 9223372036854775807%s-4294967296 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("and_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("and_int64 -1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("and_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("and_int64 -1%s-4294967296 = %d, wanted -4294967296\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(-4294967296); got != -4294967296 { fmt.Printf("and_int64 -4294967296%s-1 = %d, wanted -4294967296\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(-1); got != -1 { fmt.Printf("and_int64 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(-1); got != -1 { fmt.Printf("and_int64 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(0); got != 0 { fmt.Printf("and_int64 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(0); got != 0 { fmt.Printf("and_int64 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(1); got != 1 { fmt.Printf("and_int64 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(1); got != 1 { fmt.Printf("and_int64 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 -1%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s-1 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("and_int64 -1%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_Neg1_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("and_int64 -1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `&`, got) failed = true } if got := and_int64_Neg1_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("and_int64 9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `&`, got) failed = true } if got := and_0_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 0%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("and_int64 0%s-9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(-9223372036854775807); got != 0 { fmt.Printf("and_int64 -9223372036854775807%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(-4294967296); got != 0 { fmt.Printf("and_int64 0%s-4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(-4294967296); got != 0 { fmt.Printf("and_int64 -4294967296%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(-1); got != 0 { fmt.Printf("and_int64 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(-1); got != 0 { fmt.Printf("and_int64 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(0); got != 0 { fmt.Printf("and_int64 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(0); got != 0 { fmt.Printf("and_int64 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(1); got != 0 { fmt.Printf("and_int64 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(1); got != 0 { fmt.Printf("and_int64 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(4294967296); got != 0 { fmt.Printf("and_int64 0%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(4294967296); got != 0 { fmt.Printf("and_int64 4294967296%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 0%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 9223372036854775806%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("and_int64 0%s9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_0_ssa(9223372036854775807); got != 0 { fmt.Printf("and_int64 9223372036854775807%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 1%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_1_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("and_int64 1%s-9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_1_ssa(-9223372036854775807); got != 1 { fmt.Printf("and_int64 -9223372036854775807%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int64_ssa(-4294967296); got != 0 { fmt.Printf("and_int64 1%s-4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_1_ssa(-4294967296); got != 0 { fmt.Printf("and_int64 -4294967296%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int64_ssa(-1); got != 1 { fmt.Printf("and_int64 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_1_ssa(-1); got != 1 { fmt.Printf("and_int64 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int64_ssa(0); got != 0 { fmt.Printf("and_int64 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_1_ssa(0); got != 0 { fmt.Printf("and_int64 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int64_ssa(1); got != 1 { fmt.Printf("and_int64 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_1_ssa(1); got != 1 { fmt.Printf("and_int64 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int64_ssa(4294967296); got != 0 { fmt.Printf("and_int64 1%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_1_ssa(4294967296); got != 0 { fmt.Printf("and_int64 4294967296%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 1%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_1_ssa(9223372036854775806); got != 0 { fmt.Printf("and_int64 9223372036854775806%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("and_int64 1%s9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_1_ssa(9223372036854775807); got != 1 { fmt.Printf("and_int64 9223372036854775807%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("and_int64 4294967296%s-9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(-9223372036854775807); got != 0 { fmt.Printf("and_int64 -9223372036854775807%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(-4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s-4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(-4294967296); got != 4294967296 { fmt.Printf("and_int64 -4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(-1); got != 4294967296 { fmt.Printf("and_int64 4294967296%s-1 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(-1); got != 4294967296 { fmt.Printf("and_int64 -1%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(0); got != 0 { fmt.Printf("and_int64 4294967296%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(0); got != 0 { fmt.Printf("and_int64 0%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(1); got != 0 { fmt.Printf("and_int64 4294967296%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(1); got != 0 { fmt.Printf("and_int64 1%s4294967296 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(9223372036854775806); got != 4294967296 { fmt.Printf("and_int64 4294967296%s9223372036854775806 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(9223372036854775806); got != 4294967296 { fmt.Printf("and_int64 9223372036854775806%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_4294967296_int64_ssa(9223372036854775807); got != 4294967296 { fmt.Printf("and_int64 4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_4294967296_ssa(9223372036854775807); got != 4294967296 { fmt.Printf("and_int64 9223372036854775807%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("and_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(-9223372036854775807); got != 0 { fmt.Printf("and_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("and_int64 9223372036854775806%s-4294967296 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("and_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(-1); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(-1); got != 9223372036854775806 { fmt.Printf("and_int64 -1%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(0); got != 0 { fmt.Printf("and_int64 9223372036854775806%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(0); got != 0 { fmt.Printf("and_int64 0%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(1); got != 0 { fmt.Printf("and_int64 9223372036854775806%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(1); got != 0 { fmt.Printf("and_int64 1%s9223372036854775806 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 9223372036854775806%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s9223372036854775806 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775806%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775806%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_9223372036854775806_int64_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_int64_9223372036854775806_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(-9223372036854775808); got != 0 { fmt.Printf("and_int64 -9223372036854775808%s9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("and_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(-9223372036854775807); got != 1 { fmt.Printf("and_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("and_int64 9223372036854775807%s-4294967296 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("and_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808512\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(-1); got != 9223372036854775807 { fmt.Printf("and_int64 9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(-1); got != 9223372036854775807 { fmt.Printf("and_int64 -1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(0); got != 0 { fmt.Printf("and_int64 9223372036854775807%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(0); got != 0 { fmt.Printf("and_int64 0%s9223372036854775807 = %d, wanted 0\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(1); got != 1 { fmt.Printf("and_int64 9223372036854775807%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(1); got != 1 { fmt.Printf("and_int64 1%s9223372036854775807 = %d, wanted 1\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 9223372036854775807%s4294967296 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(4294967296); got != 4294967296 { fmt.Printf("and_int64 4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("and_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775806\n", `&`, got) failed = true } if got := and_9223372036854775807_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("and_int64 9223372036854775807%s9223372036854775807 = %d, wanted 9223372036854775807\n", `&`, got) failed = true } if got := and_int64_9223372036854775807_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("and_int64 9223372036854775807%s9223372036854775807 = %d, wanted 9223372036854775807\n", `&`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("or_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("or_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 -9223372036854775808%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s-9223372036854775808 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 -9223372036854775808%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s-9223372036854775808 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(0); got != -9223372036854775808 { fmt.Printf("or_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(0); got != -9223372036854775808 { fmt.Printf("or_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775807 { fmt.Printf("or_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("or_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("or_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -2 { fmt.Printf("or_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(9223372036854775806); got != -2 { fmt.Printf("or_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `|`, got) failed = true } if got := or_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(-4294967296); got != -4294967295 { fmt.Printf("or_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(-4294967296); got != -4294967295 { fmt.Printf("or_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 -9223372036854775807%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s-9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(0); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(0); got != -9223372036854775807 { fmt.Printf("or_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775807 { fmt.Printf("or_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("or_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("or_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("or_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(9223372036854775806); got != -1 { fmt.Printf("or_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg9223372036854775807_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(-9223372036854775808); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s-9223372036854775808 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(-9223372036854775808); got != -4294967296 { fmt.Printf("or_int64 -9223372036854775808%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(-9223372036854775807); got != -4294967295 { fmt.Printf("or_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(-9223372036854775807); got != -4294967295 { fmt.Printf("or_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 -4294967296%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s-4294967296 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(0); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s0 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(0); got != -4294967296 { fmt.Printf("or_int64 0%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(1); got != -4294967295 { fmt.Printf("or_int64 -4294967296%s1 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(1); got != -4294967295 { fmt.Printf("or_int64 1%s-4294967296 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(4294967296); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(4294967296); got != -4294967296 { fmt.Printf("or_int64 4294967296%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(9223372036854775806); got != -2 { fmt.Printf("or_int64 -4294967296%s9223372036854775806 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(9223372036854775806); got != -2 { fmt.Printf("or_int64 9223372036854775806%s-4294967296 = %d, wanted -2\n", `|`, got) failed = true } if got := or_Neg4294967296_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 -4294967296%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg4294967296_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-4294967296 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(-9223372036854775808); got != -1 { fmt.Printf("or_int64 -1%s-9223372036854775808 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(-9223372036854775808); got != -1 { fmt.Printf("or_int64 -9223372036854775808%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("or_int64 -1%s-9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(-9223372036854775807); got != -1 { fmt.Printf("or_int64 -9223372036854775807%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(-4294967296); got != -1 { fmt.Printf("or_int64 -1%s-4294967296 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(-4294967296); got != -1 { fmt.Printf("or_int64 -4294967296%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(0); got != -1 { fmt.Printf("or_int64 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(0); got != -1 { fmt.Printf("or_int64 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(1); got != -1 { fmt.Printf("or_int64 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(1); got != -1 { fmt.Printf("or_int64 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(4294967296); got != -1 { fmt.Printf("or_int64 -1%s4294967296 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(4294967296); got != -1 { fmt.Printf("or_int64 4294967296%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("or_int64 -1%s9223372036854775806 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(9223372036854775806); got != -1 { fmt.Printf("or_int64 9223372036854775806%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 -1%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_Neg1_ssa(9223372036854775807); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("or_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `|`, got) failed = true } if got := or_int64_0_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("or_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `|`, got) failed = true } if got := or_0_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_0_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_0_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 0%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_0_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s0 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_0_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_0_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int64_ssa(0); got != 0 { fmt.Printf("or_int64 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_int64_0_ssa(0); got != 0 { fmt.Printf("or_int64 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_int64_ssa(1); got != 1 { fmt.Printf("or_int64 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int64_0_ssa(1); got != 1 { fmt.Printf("or_int64 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("or_int64 0%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_int64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("or_int64 4294967296%s0 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_0_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("or_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_int64_0_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("or_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_0_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_0_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_1_int64_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("or_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_1_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_1_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_int64_1_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("or_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `|`, got) failed = true } if got := or_1_int64_ssa(-4294967296); got != -4294967295 { fmt.Printf("or_int64 1%s-4294967296 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_int64_1_ssa(-4294967296); got != -4294967295 { fmt.Printf("or_int64 -4294967296%s1 = %d, wanted -4294967295\n", `|`, got) failed = true } if got := or_1_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_1_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_1_int64_ssa(0); got != 1 { fmt.Printf("or_int64 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int64_1_ssa(0); got != 1 { fmt.Printf("or_int64 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int64_ssa(1); got != 1 { fmt.Printf("or_int64 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int64_1_ssa(1); got != 1 { fmt.Printf("or_int64 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int64_ssa(4294967296); got != 4294967297 { fmt.Printf("or_int64 1%s4294967296 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_int64_1_ssa(4294967296); got != 4294967297 { fmt.Printf("or_int64 4294967296%s1 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_1_int64_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("or_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_1_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_1_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_1_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("or_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("or_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("or_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("or_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 4294967296%s-4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(-4294967296); got != -4294967296 { fmt.Printf("or_int64 -4294967296%s4294967296 = %d, wanted -4294967296\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 4294967296%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s4294967296 = %d, wanted -1\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(0); got != 4294967296 { fmt.Printf("or_int64 4294967296%s0 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(0); got != 4294967296 { fmt.Printf("or_int64 0%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(1); got != 4294967297 { fmt.Printf("or_int64 4294967296%s1 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(1); got != 4294967297 { fmt.Printf("or_int64 1%s4294967296 = %d, wanted 4294967297\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("or_int64 4294967296%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(4294967296); got != 4294967296 { fmt.Printf("or_int64 4294967296%s4294967296 = %d, wanted 4294967296\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("or_int64 4294967296%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("or_int64 9223372036854775806%s4294967296 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_4294967296_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 4294967296%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_4294967296_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s4294967296 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(-9223372036854775808); got != -2 { fmt.Printf("or_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(-9223372036854775808); got != -2 { fmt.Printf("or_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("or_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { fmt.Printf("or_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(-4294967296); got != -2 { fmt.Printf("or_int64 9223372036854775806%s-4294967296 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(-4294967296); got != -2 { fmt.Printf("or_int64 -4294967296%s9223372036854775806 = %d, wanted -2\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 9223372036854775806%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s9223372036854775806 = %d, wanted -1\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(0); got != 9223372036854775806 { fmt.Printf("or_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(0); got != 9223372036854775806 { fmt.Printf("or_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(1); got != 9223372036854775807 { fmt.Printf("or_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(4294967296); got != 9223372036854775806 { fmt.Printf("or_int64 9223372036854775806%s4294967296 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(4294967296); got != 9223372036854775806 { fmt.Printf("or_int64 4294967296%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("or_int64 9223372036854775806%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("or_int64 9223372036854775806%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) failed = true } if got := or_9223372036854775806_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775806_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(-9223372036854775808); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("or_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(-9223372036854775807); got != -1 { fmt.Printf("or_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(-4294967296); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-4294967296 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(-4294967296); got != -1 { fmt.Printf("or_int64 -4294967296%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(-1); got != -1 { fmt.Printf("or_int64 9223372036854775807%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(-1); got != -1 { fmt.Printf("or_int64 -1%s9223372036854775807 = %d, wanted -1\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(0); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(0); got != 9223372036854775807 { fmt.Printf("or_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(1); got != 9223372036854775807 { fmt.Printf("or_int64 1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(4294967296); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s4294967296 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(4294967296); got != 9223372036854775807 { fmt.Printf("or_int64 4294967296%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_9223372036854775807_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := or_int64_9223372036854775807_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("or_int64 9223372036854775807%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { fmt.Printf("xor_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { fmt.Printf("xor_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != 1 { fmt.Printf("xor_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != 1 { fmt.Printf("xor_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("xor_int64 -9223372036854775808%s-4294967296 = %d, wanted 9223372032559808512\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(-4294967296); got != 9223372032559808512 { fmt.Printf("xor_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(-1); got != 9223372036854775807 { fmt.Printf("xor_int64 -9223372036854775808%s-1 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(-1); got != 9223372036854775807 { fmt.Printf("xor_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(0); got != -9223372036854775808 { fmt.Printf("xor_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(0); got != -9223372036854775808 { fmt.Printf("xor_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775807 { fmt.Printf("xor_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775807 { fmt.Printf("xor_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("xor_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(4294967296); got != -9223372032559808512 { fmt.Printf("xor_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -2 { fmt.Printf("xor_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(9223372036854775806); got != -2 { fmt.Printf("xor_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { fmt.Printf("xor_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -1 { fmt.Printf("xor_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != 1 { fmt.Printf("xor_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != 1 { fmt.Printf("xor_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { fmt.Printf("xor_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 0 { fmt.Printf("xor_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(-4294967296); got != 9223372032559808513 { fmt.Printf("xor_int64 -9223372036854775807%s-4294967296 = %d, wanted 9223372032559808513\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(-4294967296); got != 9223372032559808513 { fmt.Printf("xor_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808513\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(-1); got != 9223372036854775806 { fmt.Printf("xor_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(-1); got != 9223372036854775806 { fmt.Printf("xor_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(0); got != -9223372036854775807 { fmt.Printf("xor_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(0); got != -9223372036854775807 { fmt.Printf("xor_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775808 { fmt.Printf("xor_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775808 { fmt.Printf("xor_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("xor_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(4294967296); got != -9223372032559808511 { fmt.Printf("xor_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { fmt.Printf("xor_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(9223372036854775806); got != -1 { fmt.Printf("xor_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg9223372036854775807_int64_ssa(9223372036854775807); got != -2 { fmt.Printf("xor_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -2 { fmt.Printf("xor_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(-9223372036854775808); got != 9223372032559808512 { fmt.Printf("xor_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(-9223372036854775808); got != 9223372032559808512 { fmt.Printf("xor_int64 -9223372036854775808%s-4294967296 = %d, wanted 9223372032559808512\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(-9223372036854775807); got != 9223372032559808513 { fmt.Printf("xor_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808513\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(-9223372036854775807); got != 9223372032559808513 { fmt.Printf("xor_int64 -9223372036854775807%s-4294967296 = %d, wanted 9223372032559808513\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(-4294967296); got != 0 { fmt.Printf("xor_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(-4294967296); got != 0 { fmt.Printf("xor_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(-1); got != 4294967295 { fmt.Printf("xor_int64 -4294967296%s-1 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(-1); got != 4294967295 { fmt.Printf("xor_int64 -1%s-4294967296 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(0); got != -4294967296 { fmt.Printf("xor_int64 -4294967296%s0 = %d, wanted -4294967296\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(0); got != -4294967296 { fmt.Printf("xor_int64 0%s-4294967296 = %d, wanted -4294967296\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(1); got != -4294967295 { fmt.Printf("xor_int64 -4294967296%s1 = %d, wanted -4294967295\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(1); got != -4294967295 { fmt.Printf("xor_int64 1%s-4294967296 = %d, wanted -4294967295\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(4294967296); got != -8589934592 { fmt.Printf("xor_int64 -4294967296%s4294967296 = %d, wanted -8589934592\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(4294967296); got != -8589934592 { fmt.Printf("xor_int64 4294967296%s-4294967296 = %d, wanted -8589934592\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(9223372036854775806); got != -9223372032559808514 { fmt.Printf("xor_int64 -4294967296%s9223372036854775806 = %d, wanted -9223372032559808514\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(9223372036854775806); got != -9223372032559808514 { fmt.Printf("xor_int64 9223372036854775806%s-4294967296 = %d, wanted -9223372032559808514\n", `^`, got) failed = true } if got := xor_Neg4294967296_int64_ssa(9223372036854775807); got != -9223372032559808513 { fmt.Printf("xor_int64 -4294967296%s9223372036854775807 = %d, wanted -9223372032559808513\n", `^`, got) failed = true } if got := xor_int64_Neg4294967296_ssa(9223372036854775807); got != -9223372032559808513 { fmt.Printf("xor_int64 9223372036854775807%s-4294967296 = %d, wanted -9223372032559808513\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("xor_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(-9223372036854775808); got != 9223372036854775807 { fmt.Printf("xor_int64 -9223372036854775808%s-1 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(-9223372036854775807); got != 9223372036854775806 { fmt.Printf("xor_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(-9223372036854775807); got != 9223372036854775806 { fmt.Printf("xor_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(-4294967296); got != 4294967295 { fmt.Printf("xor_int64 -1%s-4294967296 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(-4294967296); got != 4294967295 { fmt.Printf("xor_int64 -4294967296%s-1 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(-1); got != 0 { fmt.Printf("xor_int64 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(-1); got != 0 { fmt.Printf("xor_int64 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(0); got != -1 { fmt.Printf("xor_int64 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(0); got != -1 { fmt.Printf("xor_int64 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(1); got != -2 { fmt.Printf("xor_int64 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(1); got != -2 { fmt.Printf("xor_int64 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(4294967296); got != -4294967297 { fmt.Printf("xor_int64 -1%s4294967296 = %d, wanted -4294967297\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(4294967296); got != -4294967297 { fmt.Printf("xor_int64 4294967296%s-1 = %d, wanted -4294967297\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(9223372036854775806); got != -9223372036854775807 { fmt.Printf("xor_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(9223372036854775806); got != -9223372036854775807 { fmt.Printf("xor_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_Neg1_int64_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("xor_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_int64_Neg1_ssa(9223372036854775807); got != -9223372036854775808 { fmt.Printf("xor_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_0_int64_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("xor_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_int64_0_ssa(-9223372036854775808); got != -9223372036854775808 { fmt.Printf("xor_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_0_int64_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("xor_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_0_ssa(-9223372036854775807); got != -9223372036854775807 { fmt.Printf("xor_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_0_int64_ssa(-4294967296); got != -4294967296 { fmt.Printf("xor_int64 0%s-4294967296 = %d, wanted -4294967296\n", `^`, got) failed = true } if got := xor_int64_0_ssa(-4294967296); got != -4294967296 { fmt.Printf("xor_int64 -4294967296%s0 = %d, wanted -4294967296\n", `^`, got) failed = true } if got := xor_0_int64_ssa(-1); got != -1 { fmt.Printf("xor_int64 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int64_0_ssa(-1); got != -1 { fmt.Printf("xor_int64 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_0_int64_ssa(0); got != 0 { fmt.Printf("xor_int64 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_0_ssa(0); got != 0 { fmt.Printf("xor_int64 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_int64_ssa(1); got != 1 { fmt.Printf("xor_int64 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int64_0_ssa(1); got != 1 { fmt.Printf("xor_int64 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_int64_ssa(4294967296); got != 4294967296 { fmt.Printf("xor_int64 0%s4294967296 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_int64_0_ssa(4294967296); got != 4294967296 { fmt.Printf("xor_int64 4294967296%s0 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_0_int64_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("xor_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_int64_0_ssa(9223372036854775806); got != 9223372036854775806 { fmt.Printf("xor_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_0_int64_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("xor_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_0_ssa(9223372036854775807); got != 9223372036854775807 { fmt.Printf("xor_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_1_int64_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("xor_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_1_ssa(-9223372036854775808); got != -9223372036854775807 { fmt.Printf("xor_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_1_int64_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("xor_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_int64_1_ssa(-9223372036854775807); got != -9223372036854775808 { fmt.Printf("xor_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_1_int64_ssa(-4294967296); got != -4294967295 { fmt.Printf("xor_int64 1%s-4294967296 = %d, wanted -4294967295\n", `^`, got) failed = true } if got := xor_int64_1_ssa(-4294967296); got != -4294967295 { fmt.Printf("xor_int64 -4294967296%s1 = %d, wanted -4294967295\n", `^`, got) failed = true } if got := xor_1_int64_ssa(-1); got != -2 { fmt.Printf("xor_int64 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int64_1_ssa(-1); got != -2 { fmt.Printf("xor_int64 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_1_int64_ssa(0); got != 1 { fmt.Printf("xor_int64 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int64_1_ssa(0); got != 1 { fmt.Printf("xor_int64 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_int64_ssa(1); got != 0 { fmt.Printf("xor_int64 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_1_ssa(1); got != 0 { fmt.Printf("xor_int64 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_int64_ssa(4294967296); got != 4294967297 { fmt.Printf("xor_int64 1%s4294967296 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_int64_1_ssa(4294967296); got != 4294967297 { fmt.Printf("xor_int64 4294967296%s1 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_1_int64_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("xor_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_1_ssa(9223372036854775806); got != 9223372036854775807 { fmt.Printf("xor_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_1_int64_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("xor_int64 1%s9223372036854775807 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_int64_1_ssa(9223372036854775807); got != 9223372036854775806 { fmt.Printf("xor_int64 9223372036854775807%s1 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("xor_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(-9223372036854775808); got != -9223372032559808512 { fmt.Printf("xor_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("xor_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(-9223372036854775807); got != -9223372032559808511 { fmt.Printf("xor_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(-4294967296); got != -8589934592 { fmt.Printf("xor_int64 4294967296%s-4294967296 = %d, wanted -8589934592\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(-4294967296); got != -8589934592 { fmt.Printf("xor_int64 -4294967296%s4294967296 = %d, wanted -8589934592\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(-1); got != -4294967297 { fmt.Printf("xor_int64 4294967296%s-1 = %d, wanted -4294967297\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(-1); got != -4294967297 { fmt.Printf("xor_int64 -1%s4294967296 = %d, wanted -4294967297\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(0); got != 4294967296 { fmt.Printf("xor_int64 4294967296%s0 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(0); got != 4294967296 { fmt.Printf("xor_int64 0%s4294967296 = %d, wanted 4294967296\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(1); got != 4294967297 { fmt.Printf("xor_int64 4294967296%s1 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(1); got != 4294967297 { fmt.Printf("xor_int64 1%s4294967296 = %d, wanted 4294967297\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(4294967296); got != 0 { fmt.Printf("xor_int64 4294967296%s4294967296 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(4294967296); got != 0 { fmt.Printf("xor_int64 4294967296%s4294967296 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(9223372036854775806); got != 9223372032559808510 { fmt.Printf("xor_int64 4294967296%s9223372036854775806 = %d, wanted 9223372032559808510\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(9223372036854775806); got != 9223372032559808510 { fmt.Printf("xor_int64 9223372036854775806%s4294967296 = %d, wanted 9223372032559808510\n", `^`, got) failed = true } if got := xor_4294967296_int64_ssa(9223372036854775807); got != 9223372032559808511 { fmt.Printf("xor_int64 4294967296%s9223372036854775807 = %d, wanted 9223372032559808511\n", `^`, got) failed = true } if got := xor_int64_4294967296_ssa(9223372036854775807); got != 9223372032559808511 { fmt.Printf("xor_int64 9223372036854775807%s4294967296 = %d, wanted 9223372032559808511\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(-9223372036854775808); got != -2 { fmt.Printf("xor_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(-9223372036854775808); got != -2 { fmt.Printf("xor_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(-9223372036854775807); got != -1 { fmt.Printf("xor_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { fmt.Printf("xor_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(-4294967296); got != -9223372032559808514 { fmt.Printf("xor_int64 9223372036854775806%s-4294967296 = %d, wanted -9223372032559808514\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(-4294967296); got != -9223372032559808514 { fmt.Printf("xor_int64 -4294967296%s9223372036854775806 = %d, wanted -9223372032559808514\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(-1); got != -9223372036854775807 { fmt.Printf("xor_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(-1); got != -9223372036854775807 { fmt.Printf("xor_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775807\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(0); got != 9223372036854775806 { fmt.Printf("xor_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(0); got != 9223372036854775806 { fmt.Printf("xor_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(1); got != 9223372036854775807 { fmt.Printf("xor_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(1); got != 9223372036854775807 { fmt.Printf("xor_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(4294967296); got != 9223372032559808510 { fmt.Printf("xor_int64 9223372036854775806%s4294967296 = %d, wanted 9223372032559808510\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(4294967296); got != 9223372032559808510 { fmt.Printf("xor_int64 4294967296%s9223372036854775806 = %d, wanted 9223372032559808510\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(9223372036854775806); got != 0 { fmt.Printf("xor_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(9223372036854775806); got != 0 { fmt.Printf("xor_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_9223372036854775806_int64_ssa(9223372036854775807); got != 1 { fmt.Printf("xor_int64 9223372036854775806%s9223372036854775807 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int64_9223372036854775806_ssa(9223372036854775807); got != 1 { fmt.Printf("xor_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(-9223372036854775808); got != -1 { fmt.Printf("xor_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { fmt.Printf("xor_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(-9223372036854775807); got != -2 { fmt.Printf("xor_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(-9223372036854775807); got != -2 { fmt.Printf("xor_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(-4294967296); got != -9223372032559808513 { fmt.Printf("xor_int64 9223372036854775807%s-4294967296 = %d, wanted -9223372032559808513\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(-4294967296); got != -9223372032559808513 { fmt.Printf("xor_int64 -4294967296%s9223372036854775807 = %d, wanted -9223372032559808513\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(-1); got != -9223372036854775808 { fmt.Printf("xor_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(-1); got != -9223372036854775808 { fmt.Printf("xor_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(0); got != 9223372036854775807 { fmt.Printf("xor_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(0); got != 9223372036854775807 { fmt.Printf("xor_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(1); got != 9223372036854775806 { fmt.Printf("xor_int64 9223372036854775807%s1 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(1); got != 9223372036854775806 { fmt.Printf("xor_int64 1%s9223372036854775807 = %d, wanted 9223372036854775806\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(4294967296); got != 9223372032559808511 { fmt.Printf("xor_int64 9223372036854775807%s4294967296 = %d, wanted 9223372032559808511\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(4294967296); got != 9223372032559808511 { fmt.Printf("xor_int64 4294967296%s9223372036854775807 = %d, wanted 9223372032559808511\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(9223372036854775806); got != 1 { fmt.Printf("xor_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(9223372036854775806); got != 1 { fmt.Printf("xor_int64 9223372036854775806%s9223372036854775807 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_9223372036854775807_int64_ssa(9223372036854775807); got != 0 { fmt.Printf("xor_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int64_9223372036854775807_ssa(9223372036854775807); got != 0 { fmt.Printf("xor_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `^`, got) failed = true } if got := add_0_uint32_ssa(0); got != 0 { fmt.Printf("add_uint32 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint32_0_ssa(0); got != 0 { fmt.Printf("add_uint32 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_uint32_ssa(1); got != 1 { fmt.Printf("add_uint32 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint32_0_ssa(1); got != 1 { fmt.Printf("add_uint32 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("add_uint32 0%s4294967295 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_uint32_0_ssa(4294967295); got != 4294967295 { fmt.Printf("add_uint32 4294967295%s0 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_1_uint32_ssa(0); got != 1 { fmt.Printf("add_uint32 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint32_1_ssa(0); got != 1 { fmt.Printf("add_uint32 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_uint32_ssa(1); got != 2 { fmt.Printf("add_uint32 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_uint32_1_ssa(1); got != 2 { fmt.Printf("add_uint32 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_uint32_ssa(4294967295); got != 0 { fmt.Printf("add_uint32 1%s4294967295 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint32_1_ssa(4294967295); got != 0 { fmt.Printf("add_uint32 4294967295%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_4294967295_uint32_ssa(0); got != 4294967295 { fmt.Printf("add_uint32 4294967295%s0 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_uint32_4294967295_ssa(0); got != 4294967295 { fmt.Printf("add_uint32 0%s4294967295 = %d, wanted 4294967295\n", `+`, got) failed = true } if got := add_4294967295_uint32_ssa(1); got != 0 { fmt.Printf("add_uint32 4294967295%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint32_4294967295_ssa(1); got != 0 { fmt.Printf("add_uint32 1%s4294967295 = %d, wanted 0\n", `+`, got) failed = true } if got := add_4294967295_uint32_ssa(4294967295); got != 4294967294 { fmt.Printf("add_uint32 4294967295%s4294967295 = %d, wanted 4294967294\n", `+`, got) failed = true } if got := add_uint32_4294967295_ssa(4294967295); got != 4294967294 { fmt.Printf("add_uint32 4294967295%s4294967295 = %d, wanted 4294967294\n", `+`, got) failed = true } if got := sub_0_uint32_ssa(0); got != 0 { fmt.Printf("sub_uint32 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint32_0_ssa(0); got != 0 { fmt.Printf("sub_uint32 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_uint32_ssa(1); got != 4294967295 { fmt.Printf("sub_uint32 0%s1 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_uint32_0_ssa(1); got != 1 { fmt.Printf("sub_uint32 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_uint32_ssa(4294967295); got != 1 { fmt.Printf("sub_uint32 0%s4294967295 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint32_0_ssa(4294967295); got != 4294967295 { fmt.Printf("sub_uint32 4294967295%s0 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_1_uint32_ssa(0); got != 1 { fmt.Printf("sub_uint32 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint32_1_ssa(0); got != 4294967295 { fmt.Printf("sub_uint32 0%s1 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_1_uint32_ssa(1); got != 0 { fmt.Printf("sub_uint32 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint32_1_ssa(1); got != 0 { fmt.Printf("sub_uint32 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_uint32_ssa(4294967295); got != 2 { fmt.Printf("sub_uint32 1%s4294967295 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_uint32_1_ssa(4294967295); got != 4294967294 { fmt.Printf("sub_uint32 4294967295%s1 = %d, wanted 4294967294\n", `-`, got) failed = true } if got := sub_4294967295_uint32_ssa(0); got != 4294967295 { fmt.Printf("sub_uint32 4294967295%s0 = %d, wanted 4294967295\n", `-`, got) failed = true } if got := sub_uint32_4294967295_ssa(0); got != 1 { fmt.Printf("sub_uint32 0%s4294967295 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_4294967295_uint32_ssa(1); got != 4294967294 { fmt.Printf("sub_uint32 4294967295%s1 = %d, wanted 4294967294\n", `-`, got) failed = true } if got := sub_uint32_4294967295_ssa(1); got != 2 { fmt.Printf("sub_uint32 1%s4294967295 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_4294967295_uint32_ssa(4294967295); got != 0 { fmt.Printf("sub_uint32 4294967295%s4294967295 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint32_4294967295_ssa(4294967295); got != 0 { fmt.Printf("sub_uint32 4294967295%s4294967295 = %d, wanted 0\n", `-`, got) failed = true } if got := div_0_uint32_ssa(1); got != 0 { fmt.Printf("div_uint32 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_uint32_ssa(4294967295); got != 0 { fmt.Printf("div_uint32 0%s4294967295 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint32_1_ssa(0); got != 0 { fmt.Printf("div_uint32 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_uint32_ssa(1); got != 1 { fmt.Printf("div_uint32 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint32_1_ssa(1); got != 1 { fmt.Printf("div_uint32 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_uint32_ssa(4294967295); got != 0 { fmt.Printf("div_uint32 1%s4294967295 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint32_1_ssa(4294967295); got != 4294967295 { fmt.Printf("div_uint32 4294967295%s1 = %d, wanted 4294967295\n", `/`, got) failed = true } if got := div_uint32_4294967295_ssa(0); got != 0 { fmt.Printf("div_uint32 0%s4294967295 = %d, wanted 0\n", `/`, got) failed = true } if got := div_4294967295_uint32_ssa(1); got != 4294967295 { fmt.Printf("div_uint32 4294967295%s1 = %d, wanted 4294967295\n", `/`, got) failed = true } if got := div_uint32_4294967295_ssa(1); got != 0 { fmt.Printf("div_uint32 1%s4294967295 = %d, wanted 0\n", `/`, got) failed = true } if got := div_4294967295_uint32_ssa(4294967295); got != 1 { fmt.Printf("div_uint32 4294967295%s4294967295 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint32_4294967295_ssa(4294967295); got != 1 { fmt.Printf("div_uint32 4294967295%s4294967295 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_0_uint32_ssa(0); got != 0 { fmt.Printf("mul_uint32 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint32_0_ssa(0); got != 0 { fmt.Printf("mul_uint32 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint32_ssa(1); got != 0 { fmt.Printf("mul_uint32 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint32_0_ssa(1); got != 0 { fmt.Printf("mul_uint32 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint32_ssa(4294967295); got != 0 { fmt.Printf("mul_uint32 0%s4294967295 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint32_0_ssa(4294967295); got != 0 { fmt.Printf("mul_uint32 4294967295%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint32_ssa(0); got != 0 { fmt.Printf("mul_uint32 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint32_1_ssa(0); got != 0 { fmt.Printf("mul_uint32 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint32_ssa(1); got != 1 { fmt.Printf("mul_uint32 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint32_1_ssa(1); got != 1 { fmt.Printf("mul_uint32 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("mul_uint32 1%s4294967295 = %d, wanted 4294967295\n", `*`, got) failed = true } if got := mul_uint32_1_ssa(4294967295); got != 4294967295 { fmt.Printf("mul_uint32 4294967295%s1 = %d, wanted 4294967295\n", `*`, got) failed = true } if got := mul_4294967295_uint32_ssa(0); got != 0 { fmt.Printf("mul_uint32 4294967295%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint32_4294967295_ssa(0); got != 0 { fmt.Printf("mul_uint32 0%s4294967295 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_4294967295_uint32_ssa(1); got != 4294967295 { fmt.Printf("mul_uint32 4294967295%s1 = %d, wanted 4294967295\n", `*`, got) failed = true } if got := mul_uint32_4294967295_ssa(1); got != 4294967295 { fmt.Printf("mul_uint32 1%s4294967295 = %d, wanted 4294967295\n", `*`, got) failed = true } if got := mul_4294967295_uint32_ssa(4294967295); got != 1 { fmt.Printf("mul_uint32 4294967295%s4294967295 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint32_4294967295_ssa(4294967295); got != 1 { fmt.Printf("mul_uint32 4294967295%s4294967295 = %d, wanted 1\n", `*`, got) failed = true } if got := lsh_0_uint32_ssa(0); got != 0 { fmt.Printf("lsh_uint32 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint32_0_ssa(0); got != 0 { fmt.Printf("lsh_uint32 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_0_uint32_ssa(1); got != 0 { fmt.Printf("lsh_uint32 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint32_0_ssa(1); got != 1 { fmt.Printf("lsh_uint32 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_0_uint32_ssa(4294967295); got != 0 { fmt.Printf("lsh_uint32 0%s4294967295 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint32_0_ssa(4294967295); got != 4294967295 { fmt.Printf("lsh_uint32 4294967295%s0 = %d, wanted 4294967295\n", `<<`, got) failed = true } if got := lsh_1_uint32_ssa(0); got != 1 { fmt.Printf("lsh_uint32 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_uint32_1_ssa(0); got != 0 { fmt.Printf("lsh_uint32 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_1_uint32_ssa(1); got != 2 { fmt.Printf("lsh_uint32 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_uint32_1_ssa(1); got != 2 { fmt.Printf("lsh_uint32 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_1_uint32_ssa(4294967295); got != 0 { fmt.Printf("lsh_uint32 1%s4294967295 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint32_1_ssa(4294967295); got != 4294967294 { fmt.Printf("lsh_uint32 4294967295%s1 = %d, wanted 4294967294\n", `<<`, got) failed = true } if got := lsh_4294967295_uint32_ssa(0); got != 4294967295 { fmt.Printf("lsh_uint32 4294967295%s0 = %d, wanted 4294967295\n", `<<`, got) failed = true } if got := lsh_uint32_4294967295_ssa(0); got != 0 { fmt.Printf("lsh_uint32 0%s4294967295 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_4294967295_uint32_ssa(1); got != 4294967294 { fmt.Printf("lsh_uint32 4294967295%s1 = %d, wanted 4294967294\n", `<<`, got) failed = true } if got := lsh_uint32_4294967295_ssa(1); got != 0 { fmt.Printf("lsh_uint32 1%s4294967295 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_4294967295_uint32_ssa(4294967295); got != 0 { fmt.Printf("lsh_uint32 4294967295%s4294967295 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint32_4294967295_ssa(4294967295); got != 0 { fmt.Printf("lsh_uint32 4294967295%s4294967295 = %d, wanted 0\n", `<<`, got) failed = true } if got := rsh_0_uint32_ssa(0); got != 0 { fmt.Printf("rsh_uint32 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint32_0_ssa(0); got != 0 { fmt.Printf("rsh_uint32 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_0_uint32_ssa(1); got != 0 { fmt.Printf("rsh_uint32 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint32_0_ssa(1); got != 1 { fmt.Printf("rsh_uint32 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_0_uint32_ssa(4294967295); got != 0 { fmt.Printf("rsh_uint32 0%s4294967295 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint32_0_ssa(4294967295); got != 4294967295 { fmt.Printf("rsh_uint32 4294967295%s0 = %d, wanted 4294967295\n", `>>`, got) failed = true } if got := rsh_1_uint32_ssa(0); got != 1 { fmt.Printf("rsh_uint32 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_uint32_1_ssa(0); got != 0 { fmt.Printf("rsh_uint32 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint32_ssa(1); got != 0 { fmt.Printf("rsh_uint32 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint32_1_ssa(1); got != 0 { fmt.Printf("rsh_uint32 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint32_ssa(4294967295); got != 0 { fmt.Printf("rsh_uint32 1%s4294967295 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint32_1_ssa(4294967295); got != 2147483647 { fmt.Printf("rsh_uint32 4294967295%s1 = %d, wanted 2147483647\n", `>>`, got) failed = true } if got := rsh_4294967295_uint32_ssa(0); got != 4294967295 { fmt.Printf("rsh_uint32 4294967295%s0 = %d, wanted 4294967295\n", `>>`, got) failed = true } if got := rsh_uint32_4294967295_ssa(0); got != 0 { fmt.Printf("rsh_uint32 0%s4294967295 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_4294967295_uint32_ssa(1); got != 2147483647 { fmt.Printf("rsh_uint32 4294967295%s1 = %d, wanted 2147483647\n", `>>`, got) failed = true } if got := rsh_uint32_4294967295_ssa(1); got != 0 { fmt.Printf("rsh_uint32 1%s4294967295 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_4294967295_uint32_ssa(4294967295); got != 0 { fmt.Printf("rsh_uint32 4294967295%s4294967295 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint32_4294967295_ssa(4294967295); got != 0 { fmt.Printf("rsh_uint32 4294967295%s4294967295 = %d, wanted 0\n", `>>`, got) failed = true } if got := mod_0_uint32_ssa(1); got != 0 { fmt.Printf("mod_uint32 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_uint32_ssa(4294967295); got != 0 { fmt.Printf("mod_uint32 0%s4294967295 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint32_1_ssa(0); got != 0 { fmt.Printf("mod_uint32 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint32_ssa(1); got != 0 { fmt.Printf("mod_uint32 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint32_1_ssa(1); got != 0 { fmt.Printf("mod_uint32 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint32_ssa(4294967295); got != 1 { fmt.Printf("mod_uint32 1%s4294967295 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_uint32_1_ssa(4294967295); got != 0 { fmt.Printf("mod_uint32 4294967295%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint32_4294967295_ssa(0); got != 0 { fmt.Printf("mod_uint32 0%s4294967295 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_4294967295_uint32_ssa(1); got != 0 { fmt.Printf("mod_uint32 4294967295%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint32_4294967295_ssa(1); got != 1 { fmt.Printf("mod_uint32 1%s4294967295 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_4294967295_uint32_ssa(4294967295); got != 0 { fmt.Printf("mod_uint32 4294967295%s4294967295 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint32_4294967295_ssa(4294967295); got != 0 { fmt.Printf("mod_uint32 4294967295%s4294967295 = %d, wanted 0\n", `%`, got) failed = true } if got := and_0_uint32_ssa(0); got != 0 { fmt.Printf("and_uint32 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint32_0_ssa(0); got != 0 { fmt.Printf("and_uint32 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint32_ssa(1); got != 0 { fmt.Printf("and_uint32 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint32_0_ssa(1); got != 0 { fmt.Printf("and_uint32 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint32_ssa(4294967295); got != 0 { fmt.Printf("and_uint32 0%s4294967295 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint32_0_ssa(4294967295); got != 0 { fmt.Printf("and_uint32 4294967295%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint32_ssa(0); got != 0 { fmt.Printf("and_uint32 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint32_1_ssa(0); got != 0 { fmt.Printf("and_uint32 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint32_ssa(1); got != 1 { fmt.Printf("and_uint32 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint32_1_ssa(1); got != 1 { fmt.Printf("and_uint32 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_uint32_ssa(4294967295); got != 1 { fmt.Printf("and_uint32 1%s4294967295 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint32_1_ssa(4294967295); got != 1 { fmt.Printf("and_uint32 4294967295%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_4294967295_uint32_ssa(0); got != 0 { fmt.Printf("and_uint32 4294967295%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint32_4294967295_ssa(0); got != 0 { fmt.Printf("and_uint32 0%s4294967295 = %d, wanted 0\n", `&`, got) failed = true } if got := and_4294967295_uint32_ssa(1); got != 1 { fmt.Printf("and_uint32 4294967295%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint32_4294967295_ssa(1); got != 1 { fmt.Printf("and_uint32 1%s4294967295 = %d, wanted 1\n", `&`, got) failed = true } if got := and_4294967295_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("and_uint32 4294967295%s4294967295 = %d, wanted 4294967295\n", `&`, got) failed = true } if got := and_uint32_4294967295_ssa(4294967295); got != 4294967295 { fmt.Printf("and_uint32 4294967295%s4294967295 = %d, wanted 4294967295\n", `&`, got) failed = true } if got := or_0_uint32_ssa(0); got != 0 { fmt.Printf("or_uint32 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_uint32_0_ssa(0); got != 0 { fmt.Printf("or_uint32 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_uint32_ssa(1); got != 1 { fmt.Printf("or_uint32 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint32_0_ssa(1); got != 1 { fmt.Printf("or_uint32 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("or_uint32 0%s4294967295 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_uint32_0_ssa(4294967295); got != 4294967295 { fmt.Printf("or_uint32 4294967295%s0 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_1_uint32_ssa(0); got != 1 { fmt.Printf("or_uint32 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint32_1_ssa(0); got != 1 { fmt.Printf("or_uint32 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint32_ssa(1); got != 1 { fmt.Printf("or_uint32 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint32_1_ssa(1); got != 1 { fmt.Printf("or_uint32 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("or_uint32 1%s4294967295 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_uint32_1_ssa(4294967295); got != 4294967295 { fmt.Printf("or_uint32 4294967295%s1 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_4294967295_uint32_ssa(0); got != 4294967295 { fmt.Printf("or_uint32 4294967295%s0 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_uint32_4294967295_ssa(0); got != 4294967295 { fmt.Printf("or_uint32 0%s4294967295 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_4294967295_uint32_ssa(1); got != 4294967295 { fmt.Printf("or_uint32 4294967295%s1 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_uint32_4294967295_ssa(1); got != 4294967295 { fmt.Printf("or_uint32 1%s4294967295 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_4294967295_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("or_uint32 4294967295%s4294967295 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := or_uint32_4294967295_ssa(4294967295); got != 4294967295 { fmt.Printf("or_uint32 4294967295%s4294967295 = %d, wanted 4294967295\n", `|`, got) failed = true } if got := xor_0_uint32_ssa(0); got != 0 { fmt.Printf("xor_uint32 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint32_0_ssa(0); got != 0 { fmt.Printf("xor_uint32 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_uint32_ssa(1); got != 1 { fmt.Printf("xor_uint32 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint32_0_ssa(1); got != 1 { fmt.Printf("xor_uint32 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_uint32_ssa(4294967295); got != 4294967295 { fmt.Printf("xor_uint32 0%s4294967295 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_uint32_0_ssa(4294967295); got != 4294967295 { fmt.Printf("xor_uint32 4294967295%s0 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_1_uint32_ssa(0); got != 1 { fmt.Printf("xor_uint32 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint32_1_ssa(0); got != 1 { fmt.Printf("xor_uint32 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_uint32_ssa(1); got != 0 { fmt.Printf("xor_uint32 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint32_1_ssa(1); got != 0 { fmt.Printf("xor_uint32 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_uint32_ssa(4294967295); got != 4294967294 { fmt.Printf("xor_uint32 1%s4294967295 = %d, wanted 4294967294\n", `^`, got) failed = true } if got := xor_uint32_1_ssa(4294967295); got != 4294967294 { fmt.Printf("xor_uint32 4294967295%s1 = %d, wanted 4294967294\n", `^`, got) failed = true } if got := xor_4294967295_uint32_ssa(0); got != 4294967295 { fmt.Printf("xor_uint32 4294967295%s0 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_uint32_4294967295_ssa(0); got != 4294967295 { fmt.Printf("xor_uint32 0%s4294967295 = %d, wanted 4294967295\n", `^`, got) failed = true } if got := xor_4294967295_uint32_ssa(1); got != 4294967294 { fmt.Printf("xor_uint32 4294967295%s1 = %d, wanted 4294967294\n", `^`, got) failed = true } if got := xor_uint32_4294967295_ssa(1); got != 4294967294 { fmt.Printf("xor_uint32 1%s4294967295 = %d, wanted 4294967294\n", `^`, got) failed = true } if got := xor_4294967295_uint32_ssa(4294967295); got != 0 { fmt.Printf("xor_uint32 4294967295%s4294967295 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint32_4294967295_ssa(4294967295); got != 0 { fmt.Printf("xor_uint32 4294967295%s4294967295 = %d, wanted 0\n", `^`, got) failed = true } if got := add_Neg2147483648_int32_ssa(-2147483648); got != 0 { fmt.Printf("add_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int32_Neg2147483648_ssa(-2147483648); got != 0 { fmt.Printf("add_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg2147483648_int32_ssa(-2147483647); got != 1 { fmt.Printf("add_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int32_Neg2147483648_ssa(-2147483647); got != 1 { fmt.Printf("add_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg2147483648_int32_ssa(-1); got != 2147483647 { fmt.Printf("add_int32 -2147483648%s-1 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_int32_Neg2147483648_ssa(-1); got != 2147483647 { fmt.Printf("add_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_Neg2147483648_int32_ssa(0); got != -2147483648 { fmt.Printf("add_int32 -2147483648%s0 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_int32_Neg2147483648_ssa(0); got != -2147483648 { fmt.Printf("add_int32 0%s-2147483648 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_Neg2147483648_int32_ssa(1); got != -2147483647 { fmt.Printf("add_int32 -2147483648%s1 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_int32_Neg2147483648_ssa(1); got != -2147483647 { fmt.Printf("add_int32 1%s-2147483648 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_Neg2147483648_int32_ssa(2147483647); got != -1 { fmt.Printf("add_int32 -2147483648%s2147483647 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int32_Neg2147483648_ssa(2147483647); got != -1 { fmt.Printf("add_int32 2147483647%s-2147483648 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg2147483647_int32_ssa(-2147483648); got != 1 { fmt.Printf("add_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int32_Neg2147483647_ssa(-2147483648); got != 1 { fmt.Printf("add_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg2147483647_int32_ssa(-2147483647); got != 2 { fmt.Printf("add_int32 -2147483647%s-2147483647 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int32_Neg2147483647_ssa(-2147483647); got != 2 { fmt.Printf("add_int32 -2147483647%s-2147483647 = %d, wanted 2\n", `+`, got) failed = true } if got := add_Neg2147483647_int32_ssa(-1); got != -2147483648 { fmt.Printf("add_int32 -2147483647%s-1 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_int32_Neg2147483647_ssa(-1); got != -2147483648 { fmt.Printf("add_int32 -1%s-2147483647 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_Neg2147483647_int32_ssa(0); got != -2147483647 { fmt.Printf("add_int32 -2147483647%s0 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_int32_Neg2147483647_ssa(0); got != -2147483647 { fmt.Printf("add_int32 0%s-2147483647 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_Neg2147483647_int32_ssa(1); got != -2147483646 { fmt.Printf("add_int32 -2147483647%s1 = %d, wanted -2147483646\n", `+`, got) failed = true } if got := add_int32_Neg2147483647_ssa(1); got != -2147483646 { fmt.Printf("add_int32 1%s-2147483647 = %d, wanted -2147483646\n", `+`, got) failed = true } if got := add_Neg2147483647_int32_ssa(2147483647); got != 0 { fmt.Printf("add_int32 -2147483647%s2147483647 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int32_Neg2147483647_ssa(2147483647); got != 0 { fmt.Printf("add_int32 2147483647%s-2147483647 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int32_ssa(-2147483648); got != 2147483647 { fmt.Printf("add_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_int32_Neg1_ssa(-2147483648); got != 2147483647 { fmt.Printf("add_int32 -2147483648%s-1 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_Neg1_int32_ssa(-2147483647); got != -2147483648 { fmt.Printf("add_int32 -1%s-2147483647 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_int32_Neg1_ssa(-2147483647); got != -2147483648 { fmt.Printf("add_int32 -2147483647%s-1 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_Neg1_int32_ssa(-1); got != -2 { fmt.Printf("add_int32 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int32_Neg1_ssa(-1); got != -2 { fmt.Printf("add_int32 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg1_int32_ssa(0); got != -1 { fmt.Printf("add_int32 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int32_Neg1_ssa(0); got != -1 { fmt.Printf("add_int32 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg1_int32_ssa(1); got != 0 { fmt.Printf("add_int32 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int32_Neg1_ssa(1); got != 0 { fmt.Printf("add_int32 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int32_ssa(2147483647); got != 2147483646 { fmt.Printf("add_int32 -1%s2147483647 = %d, wanted 2147483646\n", `+`, got) failed = true } if got := add_int32_Neg1_ssa(2147483647); got != 2147483646 { fmt.Printf("add_int32 2147483647%s-1 = %d, wanted 2147483646\n", `+`, got) failed = true } if got := add_0_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("add_int32 0%s-2147483648 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_int32_0_ssa(-2147483648); got != -2147483648 { fmt.Printf("add_int32 -2147483648%s0 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_0_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("add_int32 0%s-2147483647 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_int32_0_ssa(-2147483647); got != -2147483647 { fmt.Printf("add_int32 -2147483647%s0 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_0_int32_ssa(-1); got != -1 { fmt.Printf("add_int32 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int32_0_ssa(-1); got != -1 { fmt.Printf("add_int32 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_0_int32_ssa(0); got != 0 { fmt.Printf("add_int32 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int32_0_ssa(0); got != 0 { fmt.Printf("add_int32 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_int32_ssa(1); got != 1 { fmt.Printf("add_int32 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int32_0_ssa(1); got != 1 { fmt.Printf("add_int32 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("add_int32 0%s2147483647 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_int32_0_ssa(2147483647); got != 2147483647 { fmt.Printf("add_int32 2147483647%s0 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_1_int32_ssa(-2147483648); got != -2147483647 { fmt.Printf("add_int32 1%s-2147483648 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_int32_1_ssa(-2147483648); got != -2147483647 { fmt.Printf("add_int32 -2147483648%s1 = %d, wanted -2147483647\n", `+`, got) failed = true } if got := add_1_int32_ssa(-2147483647); got != -2147483646 { fmt.Printf("add_int32 1%s-2147483647 = %d, wanted -2147483646\n", `+`, got) failed = true } if got := add_int32_1_ssa(-2147483647); got != -2147483646 { fmt.Printf("add_int32 -2147483647%s1 = %d, wanted -2147483646\n", `+`, got) failed = true } if got := add_1_int32_ssa(-1); got != 0 { fmt.Printf("add_int32 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int32_1_ssa(-1); got != 0 { fmt.Printf("add_int32 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_1_int32_ssa(0); got != 1 { fmt.Printf("add_int32 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int32_1_ssa(0); got != 1 { fmt.Printf("add_int32 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_int32_ssa(1); got != 2 { fmt.Printf("add_int32 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int32_1_ssa(1); got != 2 { fmt.Printf("add_int32 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_int32_ssa(2147483647); got != -2147483648 { fmt.Printf("add_int32 1%s2147483647 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_int32_1_ssa(2147483647); got != -2147483648 { fmt.Printf("add_int32 2147483647%s1 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_2147483647_int32_ssa(-2147483648); got != -1 { fmt.Printf("add_int32 2147483647%s-2147483648 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int32_2147483647_ssa(-2147483648); got != -1 { fmt.Printf("add_int32 -2147483648%s2147483647 = %d, wanted -1\n", `+`, got) failed = true } if got := add_2147483647_int32_ssa(-2147483647); got != 0 { fmt.Printf("add_int32 2147483647%s-2147483647 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int32_2147483647_ssa(-2147483647); got != 0 { fmt.Printf("add_int32 -2147483647%s2147483647 = %d, wanted 0\n", `+`, got) failed = true } if got := add_2147483647_int32_ssa(-1); got != 2147483646 { fmt.Printf("add_int32 2147483647%s-1 = %d, wanted 2147483646\n", `+`, got) failed = true } if got := add_int32_2147483647_ssa(-1); got != 2147483646 { fmt.Printf("add_int32 -1%s2147483647 = %d, wanted 2147483646\n", `+`, got) failed = true } if got := add_2147483647_int32_ssa(0); got != 2147483647 { fmt.Printf("add_int32 2147483647%s0 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_int32_2147483647_ssa(0); got != 2147483647 { fmt.Printf("add_int32 0%s2147483647 = %d, wanted 2147483647\n", `+`, got) failed = true } if got := add_2147483647_int32_ssa(1); got != -2147483648 { fmt.Printf("add_int32 2147483647%s1 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_int32_2147483647_ssa(1); got != -2147483648 { fmt.Printf("add_int32 1%s2147483647 = %d, wanted -2147483648\n", `+`, got) failed = true } if got := add_2147483647_int32_ssa(2147483647); got != -2 { fmt.Printf("add_int32 2147483647%s2147483647 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int32_2147483647_ssa(2147483647); got != -2 { fmt.Printf("add_int32 2147483647%s2147483647 = %d, wanted -2\n", `+`, got) failed = true } if got := sub_Neg2147483648_int32_ssa(-2147483648); got != 0 { fmt.Printf("sub_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int32_Neg2147483648_ssa(-2147483648); got != 0 { fmt.Printf("sub_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg2147483648_int32_ssa(-2147483647); got != -1 { fmt.Printf("sub_int32 -2147483648%s-2147483647 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int32_Neg2147483648_ssa(-2147483647); got != 1 { fmt.Printf("sub_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg2147483648_int32_ssa(-1); got != -2147483647 { fmt.Printf("sub_int32 -2147483648%s-1 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_int32_Neg2147483648_ssa(-1); got != 2147483647 { fmt.Printf("sub_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_Neg2147483648_int32_ssa(0); got != -2147483648 { fmt.Printf("sub_int32 -2147483648%s0 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_int32_Neg2147483648_ssa(0); got != -2147483648 { fmt.Printf("sub_int32 0%s-2147483648 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_Neg2147483648_int32_ssa(1); got != 2147483647 { fmt.Printf("sub_int32 -2147483648%s1 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_int32_Neg2147483648_ssa(1); got != -2147483647 { fmt.Printf("sub_int32 1%s-2147483648 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_Neg2147483648_int32_ssa(2147483647); got != 1 { fmt.Printf("sub_int32 -2147483648%s2147483647 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int32_Neg2147483648_ssa(2147483647); got != -1 { fmt.Printf("sub_int32 2147483647%s-2147483648 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg2147483647_int32_ssa(-2147483648); got != 1 { fmt.Printf("sub_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int32_Neg2147483647_ssa(-2147483648); got != -1 { fmt.Printf("sub_int32 -2147483648%s-2147483647 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg2147483647_int32_ssa(-2147483647); got != 0 { fmt.Printf("sub_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int32_Neg2147483647_ssa(-2147483647); got != 0 { fmt.Printf("sub_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg2147483647_int32_ssa(-1); got != -2147483646 { fmt.Printf("sub_int32 -2147483647%s-1 = %d, wanted -2147483646\n", `-`, got) failed = true } if got := sub_int32_Neg2147483647_ssa(-1); got != 2147483646 { fmt.Printf("sub_int32 -1%s-2147483647 = %d, wanted 2147483646\n", `-`, got) failed = true } if got := sub_Neg2147483647_int32_ssa(0); got != -2147483647 { fmt.Printf("sub_int32 -2147483647%s0 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_int32_Neg2147483647_ssa(0); got != 2147483647 { fmt.Printf("sub_int32 0%s-2147483647 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_Neg2147483647_int32_ssa(1); got != -2147483648 { fmt.Printf("sub_int32 -2147483647%s1 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_int32_Neg2147483647_ssa(1); got != -2147483648 { fmt.Printf("sub_int32 1%s-2147483647 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_Neg2147483647_int32_ssa(2147483647); got != 2 { fmt.Printf("sub_int32 -2147483647%s2147483647 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int32_Neg2147483647_ssa(2147483647); got != -2 { fmt.Printf("sub_int32 2147483647%s-2147483647 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg1_int32_ssa(-2147483648); got != 2147483647 { fmt.Printf("sub_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_int32_Neg1_ssa(-2147483648); got != -2147483647 { fmt.Printf("sub_int32 -2147483648%s-1 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_Neg1_int32_ssa(-2147483647); got != 2147483646 { fmt.Printf("sub_int32 -1%s-2147483647 = %d, wanted 2147483646\n", `-`, got) failed = true } if got := sub_int32_Neg1_ssa(-2147483647); got != -2147483646 { fmt.Printf("sub_int32 -2147483647%s-1 = %d, wanted -2147483646\n", `-`, got) failed = true } if got := sub_Neg1_int32_ssa(-1); got != 0 { fmt.Printf("sub_int32 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int32_Neg1_ssa(-1); got != 0 { fmt.Printf("sub_int32 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg1_int32_ssa(0); got != -1 { fmt.Printf("sub_int32 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int32_Neg1_ssa(0); got != 1 { fmt.Printf("sub_int32 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg1_int32_ssa(1); got != -2 { fmt.Printf("sub_int32 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int32_Neg1_ssa(1); got != 2 { fmt.Printf("sub_int32 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_Neg1_int32_ssa(2147483647); got != -2147483648 { fmt.Printf("sub_int32 -1%s2147483647 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_int32_Neg1_ssa(2147483647); got != -2147483648 { fmt.Printf("sub_int32 2147483647%s-1 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_0_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("sub_int32 0%s-2147483648 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_int32_0_ssa(-2147483648); got != -2147483648 { fmt.Printf("sub_int32 -2147483648%s0 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_0_int32_ssa(-2147483647); got != 2147483647 { fmt.Printf("sub_int32 0%s-2147483647 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_int32_0_ssa(-2147483647); got != -2147483647 { fmt.Printf("sub_int32 -2147483647%s0 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_0_int32_ssa(-1); got != 1 { fmt.Printf("sub_int32 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int32_0_ssa(-1); got != -1 { fmt.Printf("sub_int32 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_0_int32_ssa(0); got != 0 { fmt.Printf("sub_int32 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int32_0_ssa(0); got != 0 { fmt.Printf("sub_int32 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_int32_ssa(1); got != -1 { fmt.Printf("sub_int32 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int32_0_ssa(1); got != 1 { fmt.Printf("sub_int32 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_int32_ssa(2147483647); got != -2147483647 { fmt.Printf("sub_int32 0%s2147483647 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_int32_0_ssa(2147483647); got != 2147483647 { fmt.Printf("sub_int32 2147483647%s0 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_1_int32_ssa(-2147483648); got != -2147483647 { fmt.Printf("sub_int32 1%s-2147483648 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_int32_1_ssa(-2147483648); got != 2147483647 { fmt.Printf("sub_int32 -2147483648%s1 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_1_int32_ssa(-2147483647); got != -2147483648 { fmt.Printf("sub_int32 1%s-2147483647 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_int32_1_ssa(-2147483647); got != -2147483648 { fmt.Printf("sub_int32 -2147483647%s1 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_1_int32_ssa(-1); got != 2 { fmt.Printf("sub_int32 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int32_1_ssa(-1); got != -2 { fmt.Printf("sub_int32 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_1_int32_ssa(0); got != 1 { fmt.Printf("sub_int32 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int32_1_ssa(0); got != -1 { fmt.Printf("sub_int32 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_1_int32_ssa(1); got != 0 { fmt.Printf("sub_int32 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int32_1_ssa(1); got != 0 { fmt.Printf("sub_int32 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_int32_ssa(2147483647); got != -2147483646 { fmt.Printf("sub_int32 1%s2147483647 = %d, wanted -2147483646\n", `-`, got) failed = true } if got := sub_int32_1_ssa(2147483647); got != 2147483646 { fmt.Printf("sub_int32 2147483647%s1 = %d, wanted 2147483646\n", `-`, got) failed = true } if got := sub_2147483647_int32_ssa(-2147483648); got != -1 { fmt.Printf("sub_int32 2147483647%s-2147483648 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int32_2147483647_ssa(-2147483648); got != 1 { fmt.Printf("sub_int32 -2147483648%s2147483647 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_2147483647_int32_ssa(-2147483647); got != -2 { fmt.Printf("sub_int32 2147483647%s-2147483647 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int32_2147483647_ssa(-2147483647); got != 2 { fmt.Printf("sub_int32 -2147483647%s2147483647 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_2147483647_int32_ssa(-1); got != -2147483648 { fmt.Printf("sub_int32 2147483647%s-1 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_int32_2147483647_ssa(-1); got != -2147483648 { fmt.Printf("sub_int32 -1%s2147483647 = %d, wanted -2147483648\n", `-`, got) failed = true } if got := sub_2147483647_int32_ssa(0); got != 2147483647 { fmt.Printf("sub_int32 2147483647%s0 = %d, wanted 2147483647\n", `-`, got) failed = true } if got := sub_int32_2147483647_ssa(0); got != -2147483647 { fmt.Printf("sub_int32 0%s2147483647 = %d, wanted -2147483647\n", `-`, got) failed = true } if got := sub_2147483647_int32_ssa(1); got != 2147483646 { fmt.Printf("sub_int32 2147483647%s1 = %d, wanted 2147483646\n", `-`, got) failed = true } if got := sub_int32_2147483647_ssa(1); got != -2147483646 { fmt.Printf("sub_int32 1%s2147483647 = %d, wanted -2147483646\n", `-`, got) failed = true } if got := sub_2147483647_int32_ssa(2147483647); got != 0 { fmt.Printf("sub_int32 2147483647%s2147483647 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int32_2147483647_ssa(2147483647); got != 0 { fmt.Printf("sub_int32 2147483647%s2147483647 = %d, wanted 0\n", `-`, got) failed = true } if got := div_Neg2147483648_int32_ssa(-2147483648); got != 1 { fmt.Printf("div_int32 -2147483648%s-2147483648 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_Neg2147483648_ssa(-2147483648); got != 1 { fmt.Printf("div_int32 -2147483648%s-2147483648 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg2147483648_int32_ssa(-2147483647); got != 1 { fmt.Printf("div_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_Neg2147483648_ssa(-2147483647); got != 0 { fmt.Printf("div_int32 -2147483647%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg2147483648_int32_ssa(-1); got != -2147483648 { fmt.Printf("div_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `/`, got) failed = true } if got := div_int32_Neg2147483648_ssa(-1); got != 0 { fmt.Printf("div_int32 -1%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_Neg2147483648_ssa(0); got != 0 { fmt.Printf("div_int32 0%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg2147483648_int32_ssa(1); got != -2147483648 { fmt.Printf("div_int32 -2147483648%s1 = %d, wanted -2147483648\n", `/`, got) failed = true } if got := div_int32_Neg2147483648_ssa(1); got != 0 { fmt.Printf("div_int32 1%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg2147483648_int32_ssa(2147483647); got != -1 { fmt.Printf("div_int32 -2147483648%s2147483647 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int32_Neg2147483648_ssa(2147483647); got != 0 { fmt.Printf("div_int32 2147483647%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg2147483647_int32_ssa(-2147483648); got != 0 { fmt.Printf("div_int32 -2147483647%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_Neg2147483647_ssa(-2147483648); got != 1 { fmt.Printf("div_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg2147483647_int32_ssa(-2147483647); got != 1 { fmt.Printf("div_int32 -2147483647%s-2147483647 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_Neg2147483647_ssa(-2147483647); got != 1 { fmt.Printf("div_int32 -2147483647%s-2147483647 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg2147483647_int32_ssa(-1); got != 2147483647 { fmt.Printf("div_int32 -2147483647%s-1 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_int32_Neg2147483647_ssa(-1); got != 0 { fmt.Printf("div_int32 -1%s-2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_Neg2147483647_ssa(0); got != 0 { fmt.Printf("div_int32 0%s-2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg2147483647_int32_ssa(1); got != -2147483647 { fmt.Printf("div_int32 -2147483647%s1 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_int32_Neg2147483647_ssa(1); got != 0 { fmt.Printf("div_int32 1%s-2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg2147483647_int32_ssa(2147483647); got != -1 { fmt.Printf("div_int32 -2147483647%s2147483647 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int32_Neg2147483647_ssa(2147483647); got != -1 { fmt.Printf("div_int32 2147483647%s-2147483647 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int32_ssa(-2147483648); got != 0 { fmt.Printf("div_int32 -1%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_Neg1_ssa(-2147483648); got != -2147483648 { fmt.Printf("div_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `/`, got) failed = true } if got := div_Neg1_int32_ssa(-2147483647); got != 0 { fmt.Printf("div_int32 -1%s-2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_Neg1_ssa(-2147483647); got != 2147483647 { fmt.Printf("div_int32 -2147483647%s-1 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_Neg1_int32_ssa(-1); got != 1 { fmt.Printf("div_int32 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_Neg1_ssa(-1); got != 1 { fmt.Printf("div_int32 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_Neg1_ssa(0); got != 0 { fmt.Printf("div_int32 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg1_int32_ssa(1); got != -1 { fmt.Printf("div_int32 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int32_Neg1_ssa(1); got != -1 { fmt.Printf("div_int32 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int32_ssa(2147483647); got != 0 { fmt.Printf("div_int32 -1%s2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_Neg1_ssa(2147483647); got != -2147483647 { fmt.Printf("div_int32 2147483647%s-1 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_0_int32_ssa(-2147483648); got != 0 { fmt.Printf("div_int32 0%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int32_ssa(-2147483647); got != 0 { fmt.Printf("div_int32 0%s-2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int32_ssa(-1); got != 0 { fmt.Printf("div_int32 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int32_ssa(1); got != 0 { fmt.Printf("div_int32 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int32_ssa(2147483647); got != 0 { fmt.Printf("div_int32 0%s2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int32_ssa(-2147483648); got != 0 { fmt.Printf("div_int32 1%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_1_ssa(-2147483648); got != -2147483648 { fmt.Printf("div_int32 -2147483648%s1 = %d, wanted -2147483648\n", `/`, got) failed = true } if got := div_1_int32_ssa(-2147483647); got != 0 { fmt.Printf("div_int32 1%s-2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_1_ssa(-2147483647); got != -2147483647 { fmt.Printf("div_int32 -2147483647%s1 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_1_int32_ssa(-1); got != -1 { fmt.Printf("div_int32 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int32_1_ssa(-1); got != -1 { fmt.Printf("div_int32 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int32_1_ssa(0); got != 0 { fmt.Printf("div_int32 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int32_ssa(1); got != 1 { fmt.Printf("div_int32 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_1_ssa(1); got != 1 { fmt.Printf("div_int32 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_int32_ssa(2147483647); got != 0 { fmt.Printf("div_int32 1%s2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_1_ssa(2147483647); got != 2147483647 { fmt.Printf("div_int32 2147483647%s1 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_2147483647_int32_ssa(-2147483648); got != 0 { fmt.Printf("div_int32 2147483647%s-2147483648 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_2147483647_ssa(-2147483648); got != -1 { fmt.Printf("div_int32 -2147483648%s2147483647 = %d, wanted -1\n", `/`, got) failed = true } if got := div_2147483647_int32_ssa(-2147483647); got != -1 { fmt.Printf("div_int32 2147483647%s-2147483647 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int32_2147483647_ssa(-2147483647); got != -1 { fmt.Printf("div_int32 -2147483647%s2147483647 = %d, wanted -1\n", `/`, got) failed = true } if got := div_2147483647_int32_ssa(-1); got != -2147483647 { fmt.Printf("div_int32 2147483647%s-1 = %d, wanted -2147483647\n", `/`, got) failed = true } if got := div_int32_2147483647_ssa(-1); got != 0 { fmt.Printf("div_int32 -1%s2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int32_2147483647_ssa(0); got != 0 { fmt.Printf("div_int32 0%s2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_2147483647_int32_ssa(1); got != 2147483647 { fmt.Printf("div_int32 2147483647%s1 = %d, wanted 2147483647\n", `/`, got) failed = true } if got := div_int32_2147483647_ssa(1); got != 0 { fmt.Printf("div_int32 1%s2147483647 = %d, wanted 0\n", `/`, got) failed = true } if got := div_2147483647_int32_ssa(2147483647); got != 1 { fmt.Printf("div_int32 2147483647%s2147483647 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int32_2147483647_ssa(2147483647); got != 1 { fmt.Printf("div_int32 2147483647%s2147483647 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_Neg2147483648_int32_ssa(-2147483648); got != 0 { fmt.Printf("mul_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_Neg2147483648_ssa(-2147483648); got != 0 { fmt.Printf("mul_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg2147483648_int32_ssa(-2147483647); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s-2147483647 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_Neg2147483648_ssa(-2147483647); got != -2147483648 { fmt.Printf("mul_int32 -2147483647%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_Neg2147483648_int32_ssa(-1); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_Neg2147483648_ssa(-1); got != -2147483648 { fmt.Printf("mul_int32 -1%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_Neg2147483648_int32_ssa(0); got != 0 { fmt.Printf("mul_int32 -2147483648%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_Neg2147483648_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s-2147483648 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg2147483648_int32_ssa(1); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s1 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_Neg2147483648_ssa(1); got != -2147483648 { fmt.Printf("mul_int32 1%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_Neg2147483648_int32_ssa(2147483647); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s2147483647 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_Neg2147483648_ssa(2147483647); got != -2147483648 { fmt.Printf("mul_int32 2147483647%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_Neg2147483647_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 -2147483647%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_Neg2147483647_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s-2147483647 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_Neg2147483647_int32_ssa(-2147483647); got != 1 { fmt.Printf("mul_int32 -2147483647%s-2147483647 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int32_Neg2147483647_ssa(-2147483647); got != 1 { fmt.Printf("mul_int32 -2147483647%s-2147483647 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg2147483647_int32_ssa(-1); got != 2147483647 { fmt.Printf("mul_int32 -2147483647%s-1 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_int32_Neg2147483647_ssa(-1); got != 2147483647 { fmt.Printf("mul_int32 -1%s-2147483647 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_Neg2147483647_int32_ssa(0); got != 0 { fmt.Printf("mul_int32 -2147483647%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_Neg2147483647_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s-2147483647 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg2147483647_int32_ssa(1); got != -2147483647 { fmt.Printf("mul_int32 -2147483647%s1 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_int32_Neg2147483647_ssa(1); got != -2147483647 { fmt.Printf("mul_int32 1%s-2147483647 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_Neg2147483647_int32_ssa(2147483647); got != -1 { fmt.Printf("mul_int32 -2147483647%s2147483647 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int32_Neg2147483647_ssa(2147483647); got != -1 { fmt.Printf("mul_int32 2147483647%s-2147483647 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 -1%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_Neg1_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_Neg1_int32_ssa(-2147483647); got != 2147483647 { fmt.Printf("mul_int32 -1%s-2147483647 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_int32_Neg1_ssa(-2147483647); got != 2147483647 { fmt.Printf("mul_int32 -2147483647%s-1 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_Neg1_int32_ssa(-1); got != 1 { fmt.Printf("mul_int32 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int32_Neg1_ssa(-1); got != 1 { fmt.Printf("mul_int32 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg1_int32_ssa(0); got != 0 { fmt.Printf("mul_int32 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_Neg1_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg1_int32_ssa(1); got != -1 { fmt.Printf("mul_int32 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int32_Neg1_ssa(1); got != -1 { fmt.Printf("mul_int32 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int32_ssa(2147483647); got != -2147483647 { fmt.Printf("mul_int32 -1%s2147483647 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_int32_Neg1_ssa(2147483647); got != -2147483647 { fmt.Printf("mul_int32 2147483647%s-1 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_0_int32_ssa(-2147483648); got != 0 { fmt.Printf("mul_int32 0%s-2147483648 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_0_ssa(-2147483648); got != 0 { fmt.Printf("mul_int32 -2147483648%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int32_ssa(-2147483647); got != 0 { fmt.Printf("mul_int32 0%s-2147483647 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_0_ssa(-2147483647); got != 0 { fmt.Printf("mul_int32 -2147483647%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int32_ssa(-1); got != 0 { fmt.Printf("mul_int32 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_0_ssa(-1); got != 0 { fmt.Printf("mul_int32 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int32_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_0_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int32_ssa(1); got != 0 { fmt.Printf("mul_int32 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_0_ssa(1); got != 0 { fmt.Printf("mul_int32 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int32_ssa(2147483647); got != 0 { fmt.Printf("mul_int32 0%s2147483647 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_0_ssa(2147483647); got != 0 { fmt.Printf("mul_int32 2147483647%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 1%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_1_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s1 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_1_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("mul_int32 1%s-2147483647 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_int32_1_ssa(-2147483647); got != -2147483647 { fmt.Printf("mul_int32 -2147483647%s1 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_1_int32_ssa(-1); got != -1 { fmt.Printf("mul_int32 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int32_1_ssa(-1); got != -1 { fmt.Printf("mul_int32 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_1_int32_ssa(0); got != 0 { fmt.Printf("mul_int32 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_1_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int32_ssa(1); got != 1 { fmt.Printf("mul_int32 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int32_1_ssa(1); got != 1 { fmt.Printf("mul_int32 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("mul_int32 1%s2147483647 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_int32_1_ssa(2147483647); got != 2147483647 { fmt.Printf("mul_int32 2147483647%s1 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_2147483647_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 2147483647%s-2147483648 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_int32_2147483647_ssa(-2147483648); got != -2147483648 { fmt.Printf("mul_int32 -2147483648%s2147483647 = %d, wanted -2147483648\n", `*`, got) failed = true } if got := mul_2147483647_int32_ssa(-2147483647); got != -1 { fmt.Printf("mul_int32 2147483647%s-2147483647 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int32_2147483647_ssa(-2147483647); got != -1 { fmt.Printf("mul_int32 -2147483647%s2147483647 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_2147483647_int32_ssa(-1); got != -2147483647 { fmt.Printf("mul_int32 2147483647%s-1 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_int32_2147483647_ssa(-1); got != -2147483647 { fmt.Printf("mul_int32 -1%s2147483647 = %d, wanted -2147483647\n", `*`, got) failed = true } if got := mul_2147483647_int32_ssa(0); got != 0 { fmt.Printf("mul_int32 2147483647%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int32_2147483647_ssa(0); got != 0 { fmt.Printf("mul_int32 0%s2147483647 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_2147483647_int32_ssa(1); got != 2147483647 { fmt.Printf("mul_int32 2147483647%s1 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_int32_2147483647_ssa(1); got != 2147483647 { fmt.Printf("mul_int32 1%s2147483647 = %d, wanted 2147483647\n", `*`, got) failed = true } if got := mul_2147483647_int32_ssa(2147483647); got != 1 { fmt.Printf("mul_int32 2147483647%s2147483647 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int32_2147483647_ssa(2147483647); got != 1 { fmt.Printf("mul_int32 2147483647%s2147483647 = %d, wanted 1\n", `*`, got) failed = true } if got := mod_Neg2147483648_int32_ssa(-2147483648); got != 0 { fmt.Printf("mod_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483648_ssa(-2147483648); got != 0 { fmt.Printf("mod_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg2147483648_int32_ssa(-2147483647); got != -1 { fmt.Printf("mod_int32 -2147483648%s-2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg2147483648_ssa(-2147483647); got != -2147483647 { fmt.Printf("mod_int32 -2147483647%s-2147483648 = %d, wanted -2147483647\n", `%`, got) failed = true } if got := mod_Neg2147483648_int32_ssa(-1); got != 0 { fmt.Printf("mod_int32 -2147483648%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483648_ssa(-1); got != -1 { fmt.Printf("mod_int32 -1%s-2147483648 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg2147483648_ssa(0); got != 0 { fmt.Printf("mod_int32 0%s-2147483648 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg2147483648_int32_ssa(1); got != 0 { fmt.Printf("mod_int32 -2147483648%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483648_ssa(1); got != 1 { fmt.Printf("mod_int32 1%s-2147483648 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg2147483648_int32_ssa(2147483647); got != -1 { fmt.Printf("mod_int32 -2147483648%s2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg2147483648_ssa(2147483647); got != 2147483647 { fmt.Printf("mod_int32 2147483647%s-2147483648 = %d, wanted 2147483647\n", `%`, got) failed = true } if got := mod_Neg2147483647_int32_ssa(-2147483648); got != -2147483647 { fmt.Printf("mod_int32 -2147483647%s-2147483648 = %d, wanted -2147483647\n", `%`, got) failed = true } if got := mod_int32_Neg2147483647_ssa(-2147483648); got != -1 { fmt.Printf("mod_int32 -2147483648%s-2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_Neg2147483647_int32_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483647_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg2147483647_int32_ssa(-1); got != 0 { fmt.Printf("mod_int32 -2147483647%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483647_ssa(-1); got != -1 { fmt.Printf("mod_int32 -1%s-2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg2147483647_ssa(0); got != 0 { fmt.Printf("mod_int32 0%s-2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg2147483647_int32_ssa(1); got != 0 { fmt.Printf("mod_int32 -2147483647%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483647_ssa(1); got != 1 { fmt.Printf("mod_int32 1%s-2147483647 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg2147483647_int32_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 -2147483647%s2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg2147483647_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 2147483647%s-2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int32_ssa(-2147483648); got != -1 { fmt.Printf("mod_int32 -1%s-2147483648 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg1_ssa(-2147483648); got != 0 { fmt.Printf("mod_int32 -2147483648%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int32_ssa(-2147483647); got != -1 { fmt.Printf("mod_int32 -1%s-2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg1_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 -2147483647%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int32_ssa(-1); got != 0 { fmt.Printf("mod_int32 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg1_ssa(-1); got != 0 { fmt.Printf("mod_int32 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg1_ssa(0); got != 0 { fmt.Printf("mod_int32 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int32_ssa(1); got != 0 { fmt.Printf("mod_int32 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_Neg1_ssa(1); got != 0 { fmt.Printf("mod_int32 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int32_ssa(2147483647); got != -1 { fmt.Printf("mod_int32 -1%s2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_Neg1_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 2147483647%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int32_ssa(-2147483648); got != 0 { fmt.Printf("mod_int32 0%s-2147483648 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int32_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 0%s-2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int32_ssa(-1); got != 0 { fmt.Printf("mod_int32 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int32_ssa(1); got != 0 { fmt.Printf("mod_int32 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int32_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 0%s2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int32_ssa(-2147483648); got != 1 { fmt.Printf("mod_int32 1%s-2147483648 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int32_1_ssa(-2147483648); got != 0 { fmt.Printf("mod_int32 -2147483648%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int32_ssa(-2147483647); got != 1 { fmt.Printf("mod_int32 1%s-2147483647 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int32_1_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 -2147483647%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int32_ssa(-1); got != 0 { fmt.Printf("mod_int32 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_1_ssa(-1); got != 0 { fmt.Printf("mod_int32 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_1_ssa(0); got != 0 { fmt.Printf("mod_int32 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int32_ssa(1); got != 0 { fmt.Printf("mod_int32 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_1_ssa(1); got != 0 { fmt.Printf("mod_int32 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int32_ssa(2147483647); got != 1 { fmt.Printf("mod_int32 1%s2147483647 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int32_1_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 2147483647%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_2147483647_int32_ssa(-2147483648); got != 2147483647 { fmt.Printf("mod_int32 2147483647%s-2147483648 = %d, wanted 2147483647\n", `%`, got) failed = true } if got := mod_int32_2147483647_ssa(-2147483648); got != -1 { fmt.Printf("mod_int32 -2147483648%s2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_2147483647_int32_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 2147483647%s-2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_2147483647_ssa(-2147483647); got != 0 { fmt.Printf("mod_int32 -2147483647%s2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_2147483647_int32_ssa(-1); got != 0 { fmt.Printf("mod_int32 2147483647%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_2147483647_ssa(-1); got != -1 { fmt.Printf("mod_int32 -1%s2147483647 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int32_2147483647_ssa(0); got != 0 { fmt.Printf("mod_int32 0%s2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_2147483647_int32_ssa(1); got != 0 { fmt.Printf("mod_int32 2147483647%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_2147483647_ssa(1); got != 1 { fmt.Printf("mod_int32 1%s2147483647 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_2147483647_int32_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 2147483647%s2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int32_2147483647_ssa(2147483647); got != 0 { fmt.Printf("mod_int32 2147483647%s2147483647 = %d, wanted 0\n", `%`, got) failed = true } if got := and_Neg2147483648_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("and_int32 -2147483648%s-2147483648 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_int32_Neg2147483648_ssa(-2147483648); got != -2147483648 { fmt.Printf("and_int32 -2147483648%s-2147483648 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_Neg2147483648_int32_ssa(-2147483647); got != -2147483648 { fmt.Printf("and_int32 -2147483648%s-2147483647 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_int32_Neg2147483648_ssa(-2147483647); got != -2147483648 { fmt.Printf("and_int32 -2147483647%s-2147483648 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_Neg2147483648_int32_ssa(-1); got != -2147483648 { fmt.Printf("and_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_int32_Neg2147483648_ssa(-1); got != -2147483648 { fmt.Printf("and_int32 -1%s-2147483648 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_Neg2147483648_int32_ssa(0); got != 0 { fmt.Printf("and_int32 -2147483648%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_Neg2147483648_ssa(0); got != 0 { fmt.Printf("and_int32 0%s-2147483648 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg2147483648_int32_ssa(1); got != 0 { fmt.Printf("and_int32 -2147483648%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_Neg2147483648_ssa(1); got != 0 { fmt.Printf("and_int32 1%s-2147483648 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg2147483648_int32_ssa(2147483647); got != 0 { fmt.Printf("and_int32 -2147483648%s2147483647 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_Neg2147483648_ssa(2147483647); got != 0 { fmt.Printf("and_int32 2147483647%s-2147483648 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg2147483647_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("and_int32 -2147483647%s-2147483648 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_int32_Neg2147483647_ssa(-2147483648); got != -2147483648 { fmt.Printf("and_int32 -2147483648%s-2147483647 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_Neg2147483647_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("and_int32 -2147483647%s-2147483647 = %d, wanted -2147483647\n", `&`, got) failed = true } if got := and_int32_Neg2147483647_ssa(-2147483647); got != -2147483647 { fmt.Printf("and_int32 -2147483647%s-2147483647 = %d, wanted -2147483647\n", `&`, got) failed = true } if got := and_Neg2147483647_int32_ssa(-1); got != -2147483647 { fmt.Printf("and_int32 -2147483647%s-1 = %d, wanted -2147483647\n", `&`, got) failed = true } if got := and_int32_Neg2147483647_ssa(-1); got != -2147483647 { fmt.Printf("and_int32 -1%s-2147483647 = %d, wanted -2147483647\n", `&`, got) failed = true } if got := and_Neg2147483647_int32_ssa(0); got != 0 { fmt.Printf("and_int32 -2147483647%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_Neg2147483647_ssa(0); got != 0 { fmt.Printf("and_int32 0%s-2147483647 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg2147483647_int32_ssa(1); got != 1 { fmt.Printf("and_int32 -2147483647%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_Neg2147483647_ssa(1); got != 1 { fmt.Printf("and_int32 1%s-2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg2147483647_int32_ssa(2147483647); got != 1 { fmt.Printf("and_int32 -2147483647%s2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_Neg2147483647_ssa(2147483647); got != 1 { fmt.Printf("and_int32 2147483647%s-2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("and_int32 -1%s-2147483648 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_int32_Neg1_ssa(-2147483648); got != -2147483648 { fmt.Printf("and_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `&`, got) failed = true } if got := and_Neg1_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("and_int32 -1%s-2147483647 = %d, wanted -2147483647\n", `&`, got) failed = true } if got := and_int32_Neg1_ssa(-2147483647); got != -2147483647 { fmt.Printf("and_int32 -2147483647%s-1 = %d, wanted -2147483647\n", `&`, got) failed = true } if got := and_Neg1_int32_ssa(-1); got != -1 { fmt.Printf("and_int32 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_int32_Neg1_ssa(-1); got != -1 { fmt.Printf("and_int32 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_Neg1_int32_ssa(0); got != 0 { fmt.Printf("and_int32 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_Neg1_ssa(0); got != 0 { fmt.Printf("and_int32 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg1_int32_ssa(1); got != 1 { fmt.Printf("and_int32 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_Neg1_ssa(1); got != 1 { fmt.Printf("and_int32 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("and_int32 -1%s2147483647 = %d, wanted 2147483647\n", `&`, got) failed = true } if got := and_int32_Neg1_ssa(2147483647); got != 2147483647 { fmt.Printf("and_int32 2147483647%s-1 = %d, wanted 2147483647\n", `&`, got) failed = true } if got := and_0_int32_ssa(-2147483648); got != 0 { fmt.Printf("and_int32 0%s-2147483648 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_0_ssa(-2147483648); got != 0 { fmt.Printf("and_int32 -2147483648%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int32_ssa(-2147483647); got != 0 { fmt.Printf("and_int32 0%s-2147483647 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_0_ssa(-2147483647); got != 0 { fmt.Printf("and_int32 -2147483647%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int32_ssa(-1); got != 0 { fmt.Printf("and_int32 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_0_ssa(-1); got != 0 { fmt.Printf("and_int32 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int32_ssa(0); got != 0 { fmt.Printf("and_int32 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_0_ssa(0); got != 0 { fmt.Printf("and_int32 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int32_ssa(1); got != 0 { fmt.Printf("and_int32 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_0_ssa(1); got != 0 { fmt.Printf("and_int32 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int32_ssa(2147483647); got != 0 { fmt.Printf("and_int32 0%s2147483647 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_0_ssa(2147483647); got != 0 { fmt.Printf("and_int32 2147483647%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int32_ssa(-2147483648); got != 0 { fmt.Printf("and_int32 1%s-2147483648 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_1_ssa(-2147483648); got != 0 { fmt.Printf("and_int32 -2147483648%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int32_ssa(-2147483647); got != 1 { fmt.Printf("and_int32 1%s-2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_1_ssa(-2147483647); got != 1 { fmt.Printf("and_int32 -2147483647%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int32_ssa(-1); got != 1 { fmt.Printf("and_int32 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_1_ssa(-1); got != 1 { fmt.Printf("and_int32 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int32_ssa(0); got != 0 { fmt.Printf("and_int32 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_1_ssa(0); got != 0 { fmt.Printf("and_int32 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int32_ssa(1); got != 1 { fmt.Printf("and_int32 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_1_ssa(1); got != 1 { fmt.Printf("and_int32 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int32_ssa(2147483647); got != 1 { fmt.Printf("and_int32 1%s2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_1_ssa(2147483647); got != 1 { fmt.Printf("and_int32 2147483647%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_2147483647_int32_ssa(-2147483648); got != 0 { fmt.Printf("and_int32 2147483647%s-2147483648 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_2147483647_ssa(-2147483648); got != 0 { fmt.Printf("and_int32 -2147483648%s2147483647 = %d, wanted 0\n", `&`, got) failed = true } if got := and_2147483647_int32_ssa(-2147483647); got != 1 { fmt.Printf("and_int32 2147483647%s-2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_2147483647_ssa(-2147483647); got != 1 { fmt.Printf("and_int32 -2147483647%s2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_2147483647_int32_ssa(-1); got != 2147483647 { fmt.Printf("and_int32 2147483647%s-1 = %d, wanted 2147483647\n", `&`, got) failed = true } if got := and_int32_2147483647_ssa(-1); got != 2147483647 { fmt.Printf("and_int32 -1%s2147483647 = %d, wanted 2147483647\n", `&`, got) failed = true } if got := and_2147483647_int32_ssa(0); got != 0 { fmt.Printf("and_int32 2147483647%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int32_2147483647_ssa(0); got != 0 { fmt.Printf("and_int32 0%s2147483647 = %d, wanted 0\n", `&`, got) failed = true } if got := and_2147483647_int32_ssa(1); got != 1 { fmt.Printf("and_int32 2147483647%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int32_2147483647_ssa(1); got != 1 { fmt.Printf("and_int32 1%s2147483647 = %d, wanted 1\n", `&`, got) failed = true } if got := and_2147483647_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("and_int32 2147483647%s2147483647 = %d, wanted 2147483647\n", `&`, got) failed = true } if got := and_int32_2147483647_ssa(2147483647); got != 2147483647 { fmt.Printf("and_int32 2147483647%s2147483647 = %d, wanted 2147483647\n", `&`, got) failed = true } if got := or_Neg2147483648_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("or_int32 -2147483648%s-2147483648 = %d, wanted -2147483648\n", `|`, got) failed = true } if got := or_int32_Neg2147483648_ssa(-2147483648); got != -2147483648 { fmt.Printf("or_int32 -2147483648%s-2147483648 = %d, wanted -2147483648\n", `|`, got) failed = true } if got := or_Neg2147483648_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 -2147483648%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_Neg2147483648_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s-2147483648 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_Neg2147483648_int32_ssa(-1); got != -1 { fmt.Printf("or_int32 -2147483648%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg2147483648_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s-2147483648 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg2147483648_int32_ssa(0); got != -2147483648 { fmt.Printf("or_int32 -2147483648%s0 = %d, wanted -2147483648\n", `|`, got) failed = true } if got := or_int32_Neg2147483648_ssa(0); got != -2147483648 { fmt.Printf("or_int32 0%s-2147483648 = %d, wanted -2147483648\n", `|`, got) failed = true } if got := or_Neg2147483648_int32_ssa(1); got != -2147483647 { fmt.Printf("or_int32 -2147483648%s1 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_Neg2147483648_ssa(1); got != -2147483647 { fmt.Printf("or_int32 1%s-2147483648 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_Neg2147483648_int32_ssa(2147483647); got != -1 { fmt.Printf("or_int32 -2147483648%s2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg2147483648_ssa(2147483647); got != -1 { fmt.Printf("or_int32 2147483647%s-2147483648 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg2147483647_int32_ssa(-2147483648); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s-2147483648 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_Neg2147483647_ssa(-2147483648); got != -2147483647 { fmt.Printf("or_int32 -2147483648%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_Neg2147483647_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_Neg2147483647_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_Neg2147483647_int32_ssa(-1); got != -1 { fmt.Printf("or_int32 -2147483647%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg2147483647_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s-2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg2147483647_int32_ssa(0); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s0 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_Neg2147483647_ssa(0); got != -2147483647 { fmt.Printf("or_int32 0%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_Neg2147483647_int32_ssa(1); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s1 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_Neg2147483647_ssa(1); got != -2147483647 { fmt.Printf("or_int32 1%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_Neg2147483647_int32_ssa(2147483647); got != -1 { fmt.Printf("or_int32 -2147483647%s2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg2147483647_ssa(2147483647); got != -1 { fmt.Printf("or_int32 2147483647%s-2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int32_ssa(-2147483648); got != -1 { fmt.Printf("or_int32 -1%s-2147483648 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg1_ssa(-2147483648); got != -1 { fmt.Printf("or_int32 -2147483648%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int32_ssa(-2147483647); got != -1 { fmt.Printf("or_int32 -1%s-2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg1_ssa(-2147483647); got != -1 { fmt.Printf("or_int32 -2147483647%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int32_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg1_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int32_ssa(0); got != -1 { fmt.Printf("or_int32 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg1_ssa(0); got != -1 { fmt.Printf("or_int32 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int32_ssa(1); got != -1 { fmt.Printf("or_int32 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg1_ssa(1); got != -1 { fmt.Printf("or_int32 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int32_ssa(2147483647); got != -1 { fmt.Printf("or_int32 -1%s2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_Neg1_ssa(2147483647); got != -1 { fmt.Printf("or_int32 2147483647%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("or_int32 0%s-2147483648 = %d, wanted -2147483648\n", `|`, got) failed = true } if got := or_int32_0_ssa(-2147483648); got != -2147483648 { fmt.Printf("or_int32 -2147483648%s0 = %d, wanted -2147483648\n", `|`, got) failed = true } if got := or_0_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 0%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_0_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s0 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_0_int32_ssa(-1); got != -1 { fmt.Printf("or_int32 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_0_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int32_ssa(0); got != 0 { fmt.Printf("or_int32 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_int32_0_ssa(0); got != 0 { fmt.Printf("or_int32 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_int32_ssa(1); got != 1 { fmt.Printf("or_int32 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int32_0_ssa(1); got != 1 { fmt.Printf("or_int32 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("or_int32 0%s2147483647 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_int32_0_ssa(2147483647); got != 2147483647 { fmt.Printf("or_int32 2147483647%s0 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_1_int32_ssa(-2147483648); got != -2147483647 { fmt.Printf("or_int32 1%s-2147483648 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_1_ssa(-2147483648); got != -2147483647 { fmt.Printf("or_int32 -2147483648%s1 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_1_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 1%s-2147483647 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_int32_1_ssa(-2147483647); got != -2147483647 { fmt.Printf("or_int32 -2147483647%s1 = %d, wanted -2147483647\n", `|`, got) failed = true } if got := or_1_int32_ssa(-1); got != -1 { fmt.Printf("or_int32 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_1_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_1_int32_ssa(0); got != 1 { fmt.Printf("or_int32 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int32_1_ssa(0); got != 1 { fmt.Printf("or_int32 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int32_ssa(1); got != 1 { fmt.Printf("or_int32 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int32_1_ssa(1); got != 1 { fmt.Printf("or_int32 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("or_int32 1%s2147483647 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_int32_1_ssa(2147483647); got != 2147483647 { fmt.Printf("or_int32 2147483647%s1 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_2147483647_int32_ssa(-2147483648); got != -1 { fmt.Printf("or_int32 2147483647%s-2147483648 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_2147483647_ssa(-2147483648); got != -1 { fmt.Printf("or_int32 -2147483648%s2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_2147483647_int32_ssa(-2147483647); got != -1 { fmt.Printf("or_int32 2147483647%s-2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_2147483647_ssa(-2147483647); got != -1 { fmt.Printf("or_int32 -2147483647%s2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_2147483647_int32_ssa(-1); got != -1 { fmt.Printf("or_int32 2147483647%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int32_2147483647_ssa(-1); got != -1 { fmt.Printf("or_int32 -1%s2147483647 = %d, wanted -1\n", `|`, got) failed = true } if got := or_2147483647_int32_ssa(0); got != 2147483647 { fmt.Printf("or_int32 2147483647%s0 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_int32_2147483647_ssa(0); got != 2147483647 { fmt.Printf("or_int32 0%s2147483647 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_2147483647_int32_ssa(1); got != 2147483647 { fmt.Printf("or_int32 2147483647%s1 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_int32_2147483647_ssa(1); got != 2147483647 { fmt.Printf("or_int32 1%s2147483647 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_2147483647_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("or_int32 2147483647%s2147483647 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := or_int32_2147483647_ssa(2147483647); got != 2147483647 { fmt.Printf("or_int32 2147483647%s2147483647 = %d, wanted 2147483647\n", `|`, got) failed = true } if got := xor_Neg2147483648_int32_ssa(-2147483648); got != 0 { fmt.Printf("xor_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int32_Neg2147483648_ssa(-2147483648); got != 0 { fmt.Printf("xor_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg2147483648_int32_ssa(-2147483647); got != 1 { fmt.Printf("xor_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int32_Neg2147483648_ssa(-2147483647); got != 1 { fmt.Printf("xor_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg2147483648_int32_ssa(-1); got != 2147483647 { fmt.Printf("xor_int32 -2147483648%s-1 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_int32_Neg2147483648_ssa(-1); got != 2147483647 { fmt.Printf("xor_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_Neg2147483648_int32_ssa(0); got != -2147483648 { fmt.Printf("xor_int32 -2147483648%s0 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_int32_Neg2147483648_ssa(0); got != -2147483648 { fmt.Printf("xor_int32 0%s-2147483648 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_Neg2147483648_int32_ssa(1); got != -2147483647 { fmt.Printf("xor_int32 -2147483648%s1 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_int32_Neg2147483648_ssa(1); got != -2147483647 { fmt.Printf("xor_int32 1%s-2147483648 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_Neg2147483648_int32_ssa(2147483647); got != -1 { fmt.Printf("xor_int32 -2147483648%s2147483647 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int32_Neg2147483648_ssa(2147483647); got != -1 { fmt.Printf("xor_int32 2147483647%s-2147483648 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg2147483647_int32_ssa(-2147483648); got != 1 { fmt.Printf("xor_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int32_Neg2147483647_ssa(-2147483648); got != 1 { fmt.Printf("xor_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg2147483647_int32_ssa(-2147483647); got != 0 { fmt.Printf("xor_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int32_Neg2147483647_ssa(-2147483647); got != 0 { fmt.Printf("xor_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg2147483647_int32_ssa(-1); got != 2147483646 { fmt.Printf("xor_int32 -2147483647%s-1 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_int32_Neg2147483647_ssa(-1); got != 2147483646 { fmt.Printf("xor_int32 -1%s-2147483647 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_Neg2147483647_int32_ssa(0); got != -2147483647 { fmt.Printf("xor_int32 -2147483647%s0 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_int32_Neg2147483647_ssa(0); got != -2147483647 { fmt.Printf("xor_int32 0%s-2147483647 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_Neg2147483647_int32_ssa(1); got != -2147483648 { fmt.Printf("xor_int32 -2147483647%s1 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_int32_Neg2147483647_ssa(1); got != -2147483648 { fmt.Printf("xor_int32 1%s-2147483647 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_Neg2147483647_int32_ssa(2147483647); got != -2 { fmt.Printf("xor_int32 -2147483647%s2147483647 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int32_Neg2147483647_ssa(2147483647); got != -2 { fmt.Printf("xor_int32 2147483647%s-2147483647 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int32_ssa(-2147483648); got != 2147483647 { fmt.Printf("xor_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_int32_Neg1_ssa(-2147483648); got != 2147483647 { fmt.Printf("xor_int32 -2147483648%s-1 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_Neg1_int32_ssa(-2147483647); got != 2147483646 { fmt.Printf("xor_int32 -1%s-2147483647 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_int32_Neg1_ssa(-2147483647); got != 2147483646 { fmt.Printf("xor_int32 -2147483647%s-1 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_Neg1_int32_ssa(-1); got != 0 { fmt.Printf("xor_int32 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int32_Neg1_ssa(-1); got != 0 { fmt.Printf("xor_int32 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg1_int32_ssa(0); got != -1 { fmt.Printf("xor_int32 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int32_Neg1_ssa(0); got != -1 { fmt.Printf("xor_int32 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg1_int32_ssa(1); got != -2 { fmt.Printf("xor_int32 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int32_Neg1_ssa(1); got != -2 { fmt.Printf("xor_int32 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int32_ssa(2147483647); got != -2147483648 { fmt.Printf("xor_int32 -1%s2147483647 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_int32_Neg1_ssa(2147483647); got != -2147483648 { fmt.Printf("xor_int32 2147483647%s-1 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_0_int32_ssa(-2147483648); got != -2147483648 { fmt.Printf("xor_int32 0%s-2147483648 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_int32_0_ssa(-2147483648); got != -2147483648 { fmt.Printf("xor_int32 -2147483648%s0 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_0_int32_ssa(-2147483647); got != -2147483647 { fmt.Printf("xor_int32 0%s-2147483647 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_int32_0_ssa(-2147483647); got != -2147483647 { fmt.Printf("xor_int32 -2147483647%s0 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_0_int32_ssa(-1); got != -1 { fmt.Printf("xor_int32 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int32_0_ssa(-1); got != -1 { fmt.Printf("xor_int32 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_0_int32_ssa(0); got != 0 { fmt.Printf("xor_int32 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int32_0_ssa(0); got != 0 { fmt.Printf("xor_int32 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_int32_ssa(1); got != 1 { fmt.Printf("xor_int32 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int32_0_ssa(1); got != 1 { fmt.Printf("xor_int32 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_int32_ssa(2147483647); got != 2147483647 { fmt.Printf("xor_int32 0%s2147483647 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_int32_0_ssa(2147483647); got != 2147483647 { fmt.Printf("xor_int32 2147483647%s0 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_1_int32_ssa(-2147483648); got != -2147483647 { fmt.Printf("xor_int32 1%s-2147483648 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_int32_1_ssa(-2147483648); got != -2147483647 { fmt.Printf("xor_int32 -2147483648%s1 = %d, wanted -2147483647\n", `^`, got) failed = true } if got := xor_1_int32_ssa(-2147483647); got != -2147483648 { fmt.Printf("xor_int32 1%s-2147483647 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_int32_1_ssa(-2147483647); got != -2147483648 { fmt.Printf("xor_int32 -2147483647%s1 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_1_int32_ssa(-1); got != -2 { fmt.Printf("xor_int32 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int32_1_ssa(-1); got != -2 { fmt.Printf("xor_int32 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_1_int32_ssa(0); got != 1 { fmt.Printf("xor_int32 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int32_1_ssa(0); got != 1 { fmt.Printf("xor_int32 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_int32_ssa(1); got != 0 { fmt.Printf("xor_int32 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int32_1_ssa(1); got != 0 { fmt.Printf("xor_int32 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_int32_ssa(2147483647); got != 2147483646 { fmt.Printf("xor_int32 1%s2147483647 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_int32_1_ssa(2147483647); got != 2147483646 { fmt.Printf("xor_int32 2147483647%s1 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_2147483647_int32_ssa(-2147483648); got != -1 { fmt.Printf("xor_int32 2147483647%s-2147483648 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int32_2147483647_ssa(-2147483648); got != -1 { fmt.Printf("xor_int32 -2147483648%s2147483647 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_2147483647_int32_ssa(-2147483647); got != -2 { fmt.Printf("xor_int32 2147483647%s-2147483647 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int32_2147483647_ssa(-2147483647); got != -2 { fmt.Printf("xor_int32 -2147483647%s2147483647 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_2147483647_int32_ssa(-1); got != -2147483648 { fmt.Printf("xor_int32 2147483647%s-1 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_int32_2147483647_ssa(-1); got != -2147483648 { fmt.Printf("xor_int32 -1%s2147483647 = %d, wanted -2147483648\n", `^`, got) failed = true } if got := xor_2147483647_int32_ssa(0); got != 2147483647 { fmt.Printf("xor_int32 2147483647%s0 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_int32_2147483647_ssa(0); got != 2147483647 { fmt.Printf("xor_int32 0%s2147483647 = %d, wanted 2147483647\n", `^`, got) failed = true } if got := xor_2147483647_int32_ssa(1); got != 2147483646 { fmt.Printf("xor_int32 2147483647%s1 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_int32_2147483647_ssa(1); got != 2147483646 { fmt.Printf("xor_int32 1%s2147483647 = %d, wanted 2147483646\n", `^`, got) failed = true } if got := xor_2147483647_int32_ssa(2147483647); got != 0 { fmt.Printf("xor_int32 2147483647%s2147483647 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int32_2147483647_ssa(2147483647); got != 0 { fmt.Printf("xor_int32 2147483647%s2147483647 = %d, wanted 0\n", `^`, got) failed = true } if got := add_0_uint16_ssa(0); got != 0 { fmt.Printf("add_uint16 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint16_0_ssa(0); got != 0 { fmt.Printf("add_uint16 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_uint16_ssa(1); got != 1 { fmt.Printf("add_uint16 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint16_0_ssa(1); got != 1 { fmt.Printf("add_uint16 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_uint16_ssa(65535); got != 65535 { fmt.Printf("add_uint16 0%s65535 = %d, wanted 65535\n", `+`, got) failed = true } if got := add_uint16_0_ssa(65535); got != 65535 { fmt.Printf("add_uint16 65535%s0 = %d, wanted 65535\n", `+`, got) failed = true } if got := add_1_uint16_ssa(0); got != 1 { fmt.Printf("add_uint16 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint16_1_ssa(0); got != 1 { fmt.Printf("add_uint16 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_uint16_ssa(1); got != 2 { fmt.Printf("add_uint16 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_uint16_1_ssa(1); got != 2 { fmt.Printf("add_uint16 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_uint16_ssa(65535); got != 0 { fmt.Printf("add_uint16 1%s65535 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint16_1_ssa(65535); got != 0 { fmt.Printf("add_uint16 65535%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_65535_uint16_ssa(0); got != 65535 { fmt.Printf("add_uint16 65535%s0 = %d, wanted 65535\n", `+`, got) failed = true } if got := add_uint16_65535_ssa(0); got != 65535 { fmt.Printf("add_uint16 0%s65535 = %d, wanted 65535\n", `+`, got) failed = true } if got := add_65535_uint16_ssa(1); got != 0 { fmt.Printf("add_uint16 65535%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint16_65535_ssa(1); got != 0 { fmt.Printf("add_uint16 1%s65535 = %d, wanted 0\n", `+`, got) failed = true } if got := add_65535_uint16_ssa(65535); got != 65534 { fmt.Printf("add_uint16 65535%s65535 = %d, wanted 65534\n", `+`, got) failed = true } if got := add_uint16_65535_ssa(65535); got != 65534 { fmt.Printf("add_uint16 65535%s65535 = %d, wanted 65534\n", `+`, got) failed = true } if got := sub_0_uint16_ssa(0); got != 0 { fmt.Printf("sub_uint16 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint16_0_ssa(0); got != 0 { fmt.Printf("sub_uint16 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_uint16_ssa(1); got != 65535 { fmt.Printf("sub_uint16 0%s1 = %d, wanted 65535\n", `-`, got) failed = true } if got := sub_uint16_0_ssa(1); got != 1 { fmt.Printf("sub_uint16 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_uint16_ssa(65535); got != 1 { fmt.Printf("sub_uint16 0%s65535 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint16_0_ssa(65535); got != 65535 { fmt.Printf("sub_uint16 65535%s0 = %d, wanted 65535\n", `-`, got) failed = true } if got := sub_1_uint16_ssa(0); got != 1 { fmt.Printf("sub_uint16 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint16_1_ssa(0); got != 65535 { fmt.Printf("sub_uint16 0%s1 = %d, wanted 65535\n", `-`, got) failed = true } if got := sub_1_uint16_ssa(1); got != 0 { fmt.Printf("sub_uint16 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint16_1_ssa(1); got != 0 { fmt.Printf("sub_uint16 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_uint16_ssa(65535); got != 2 { fmt.Printf("sub_uint16 1%s65535 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_uint16_1_ssa(65535); got != 65534 { fmt.Printf("sub_uint16 65535%s1 = %d, wanted 65534\n", `-`, got) failed = true } if got := sub_65535_uint16_ssa(0); got != 65535 { fmt.Printf("sub_uint16 65535%s0 = %d, wanted 65535\n", `-`, got) failed = true } if got := sub_uint16_65535_ssa(0); got != 1 { fmt.Printf("sub_uint16 0%s65535 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_65535_uint16_ssa(1); got != 65534 { fmt.Printf("sub_uint16 65535%s1 = %d, wanted 65534\n", `-`, got) failed = true } if got := sub_uint16_65535_ssa(1); got != 2 { fmt.Printf("sub_uint16 1%s65535 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_65535_uint16_ssa(65535); got != 0 { fmt.Printf("sub_uint16 65535%s65535 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint16_65535_ssa(65535); got != 0 { fmt.Printf("sub_uint16 65535%s65535 = %d, wanted 0\n", `-`, got) failed = true } if got := div_0_uint16_ssa(1); got != 0 { fmt.Printf("div_uint16 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_uint16_ssa(65535); got != 0 { fmt.Printf("div_uint16 0%s65535 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint16_1_ssa(0); got != 0 { fmt.Printf("div_uint16 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_uint16_ssa(1); got != 1 { fmt.Printf("div_uint16 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint16_1_ssa(1); got != 1 { fmt.Printf("div_uint16 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_uint16_ssa(65535); got != 0 { fmt.Printf("div_uint16 1%s65535 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint16_1_ssa(65535); got != 65535 { fmt.Printf("div_uint16 65535%s1 = %d, wanted 65535\n", `/`, got) failed = true } if got := div_uint16_65535_ssa(0); got != 0 { fmt.Printf("div_uint16 0%s65535 = %d, wanted 0\n", `/`, got) failed = true } if got := div_65535_uint16_ssa(1); got != 65535 { fmt.Printf("div_uint16 65535%s1 = %d, wanted 65535\n", `/`, got) failed = true } if got := div_uint16_65535_ssa(1); got != 0 { fmt.Printf("div_uint16 1%s65535 = %d, wanted 0\n", `/`, got) failed = true } if got := div_65535_uint16_ssa(65535); got != 1 { fmt.Printf("div_uint16 65535%s65535 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint16_65535_ssa(65535); got != 1 { fmt.Printf("div_uint16 65535%s65535 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_0_uint16_ssa(0); got != 0 { fmt.Printf("mul_uint16 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint16_0_ssa(0); got != 0 { fmt.Printf("mul_uint16 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint16_ssa(1); got != 0 { fmt.Printf("mul_uint16 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint16_0_ssa(1); got != 0 { fmt.Printf("mul_uint16 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint16_ssa(65535); got != 0 { fmt.Printf("mul_uint16 0%s65535 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint16_0_ssa(65535); got != 0 { fmt.Printf("mul_uint16 65535%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint16_ssa(0); got != 0 { fmt.Printf("mul_uint16 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint16_1_ssa(0); got != 0 { fmt.Printf("mul_uint16 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint16_ssa(1); got != 1 { fmt.Printf("mul_uint16 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint16_1_ssa(1); got != 1 { fmt.Printf("mul_uint16 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_uint16_ssa(65535); got != 65535 { fmt.Printf("mul_uint16 1%s65535 = %d, wanted 65535\n", `*`, got) failed = true } if got := mul_uint16_1_ssa(65535); got != 65535 { fmt.Printf("mul_uint16 65535%s1 = %d, wanted 65535\n", `*`, got) failed = true } if got := mul_65535_uint16_ssa(0); got != 0 { fmt.Printf("mul_uint16 65535%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint16_65535_ssa(0); got != 0 { fmt.Printf("mul_uint16 0%s65535 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_65535_uint16_ssa(1); got != 65535 { fmt.Printf("mul_uint16 65535%s1 = %d, wanted 65535\n", `*`, got) failed = true } if got := mul_uint16_65535_ssa(1); got != 65535 { fmt.Printf("mul_uint16 1%s65535 = %d, wanted 65535\n", `*`, got) failed = true } if got := mul_65535_uint16_ssa(65535); got != 1 { fmt.Printf("mul_uint16 65535%s65535 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint16_65535_ssa(65535); got != 1 { fmt.Printf("mul_uint16 65535%s65535 = %d, wanted 1\n", `*`, got) failed = true } if got := lsh_0_uint16_ssa(0); got != 0 { fmt.Printf("lsh_uint16 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint16_0_ssa(0); got != 0 { fmt.Printf("lsh_uint16 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_0_uint16_ssa(1); got != 0 { fmt.Printf("lsh_uint16 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint16_0_ssa(1); got != 1 { fmt.Printf("lsh_uint16 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_0_uint16_ssa(65535); got != 0 { fmt.Printf("lsh_uint16 0%s65535 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint16_0_ssa(65535); got != 65535 { fmt.Printf("lsh_uint16 65535%s0 = %d, wanted 65535\n", `<<`, got) failed = true } if got := lsh_1_uint16_ssa(0); got != 1 { fmt.Printf("lsh_uint16 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_uint16_1_ssa(0); got != 0 { fmt.Printf("lsh_uint16 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_1_uint16_ssa(1); got != 2 { fmt.Printf("lsh_uint16 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_uint16_1_ssa(1); got != 2 { fmt.Printf("lsh_uint16 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_1_uint16_ssa(65535); got != 0 { fmt.Printf("lsh_uint16 1%s65535 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint16_1_ssa(65535); got != 65534 { fmt.Printf("lsh_uint16 65535%s1 = %d, wanted 65534\n", `<<`, got) failed = true } if got := lsh_65535_uint16_ssa(0); got != 65535 { fmt.Printf("lsh_uint16 65535%s0 = %d, wanted 65535\n", `<<`, got) failed = true } if got := lsh_uint16_65535_ssa(0); got != 0 { fmt.Printf("lsh_uint16 0%s65535 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_65535_uint16_ssa(1); got != 65534 { fmt.Printf("lsh_uint16 65535%s1 = %d, wanted 65534\n", `<<`, got) failed = true } if got := lsh_uint16_65535_ssa(1); got != 0 { fmt.Printf("lsh_uint16 1%s65535 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_65535_uint16_ssa(65535); got != 0 { fmt.Printf("lsh_uint16 65535%s65535 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint16_65535_ssa(65535); got != 0 { fmt.Printf("lsh_uint16 65535%s65535 = %d, wanted 0\n", `<<`, got) failed = true } if got := rsh_0_uint16_ssa(0); got != 0 { fmt.Printf("rsh_uint16 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint16_0_ssa(0); got != 0 { fmt.Printf("rsh_uint16 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_0_uint16_ssa(1); got != 0 { fmt.Printf("rsh_uint16 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint16_0_ssa(1); got != 1 { fmt.Printf("rsh_uint16 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_0_uint16_ssa(65535); got != 0 { fmt.Printf("rsh_uint16 0%s65535 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint16_0_ssa(65535); got != 65535 { fmt.Printf("rsh_uint16 65535%s0 = %d, wanted 65535\n", `>>`, got) failed = true } if got := rsh_1_uint16_ssa(0); got != 1 { fmt.Printf("rsh_uint16 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_uint16_1_ssa(0); got != 0 { fmt.Printf("rsh_uint16 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint16_ssa(1); got != 0 { fmt.Printf("rsh_uint16 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint16_1_ssa(1); got != 0 { fmt.Printf("rsh_uint16 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint16_ssa(65535); got != 0 { fmt.Printf("rsh_uint16 1%s65535 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint16_1_ssa(65535); got != 32767 { fmt.Printf("rsh_uint16 65535%s1 = %d, wanted 32767\n", `>>`, got) failed = true } if got := rsh_65535_uint16_ssa(0); got != 65535 { fmt.Printf("rsh_uint16 65535%s0 = %d, wanted 65535\n", `>>`, got) failed = true } if got := rsh_uint16_65535_ssa(0); got != 0 { fmt.Printf("rsh_uint16 0%s65535 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_65535_uint16_ssa(1); got != 32767 { fmt.Printf("rsh_uint16 65535%s1 = %d, wanted 32767\n", `>>`, got) failed = true } if got := rsh_uint16_65535_ssa(1); got != 0 { fmt.Printf("rsh_uint16 1%s65535 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_65535_uint16_ssa(65535); got != 0 { fmt.Printf("rsh_uint16 65535%s65535 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint16_65535_ssa(65535); got != 0 { fmt.Printf("rsh_uint16 65535%s65535 = %d, wanted 0\n", `>>`, got) failed = true } if got := mod_0_uint16_ssa(1); got != 0 { fmt.Printf("mod_uint16 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_uint16_ssa(65535); got != 0 { fmt.Printf("mod_uint16 0%s65535 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint16_1_ssa(0); got != 0 { fmt.Printf("mod_uint16 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint16_ssa(1); got != 0 { fmt.Printf("mod_uint16 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint16_1_ssa(1); got != 0 { fmt.Printf("mod_uint16 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint16_ssa(65535); got != 1 { fmt.Printf("mod_uint16 1%s65535 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_uint16_1_ssa(65535); got != 0 { fmt.Printf("mod_uint16 65535%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint16_65535_ssa(0); got != 0 { fmt.Printf("mod_uint16 0%s65535 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_65535_uint16_ssa(1); got != 0 { fmt.Printf("mod_uint16 65535%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint16_65535_ssa(1); got != 1 { fmt.Printf("mod_uint16 1%s65535 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_65535_uint16_ssa(65535); got != 0 { fmt.Printf("mod_uint16 65535%s65535 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint16_65535_ssa(65535); got != 0 { fmt.Printf("mod_uint16 65535%s65535 = %d, wanted 0\n", `%`, got) failed = true } if got := and_0_uint16_ssa(0); got != 0 { fmt.Printf("and_uint16 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint16_0_ssa(0); got != 0 { fmt.Printf("and_uint16 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint16_ssa(1); got != 0 { fmt.Printf("and_uint16 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint16_0_ssa(1); got != 0 { fmt.Printf("and_uint16 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint16_ssa(65535); got != 0 { fmt.Printf("and_uint16 0%s65535 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint16_0_ssa(65535); got != 0 { fmt.Printf("and_uint16 65535%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint16_ssa(0); got != 0 { fmt.Printf("and_uint16 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint16_1_ssa(0); got != 0 { fmt.Printf("and_uint16 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint16_ssa(1); got != 1 { fmt.Printf("and_uint16 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint16_1_ssa(1); got != 1 { fmt.Printf("and_uint16 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_uint16_ssa(65535); got != 1 { fmt.Printf("and_uint16 1%s65535 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint16_1_ssa(65535); got != 1 { fmt.Printf("and_uint16 65535%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_65535_uint16_ssa(0); got != 0 { fmt.Printf("and_uint16 65535%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint16_65535_ssa(0); got != 0 { fmt.Printf("and_uint16 0%s65535 = %d, wanted 0\n", `&`, got) failed = true } if got := and_65535_uint16_ssa(1); got != 1 { fmt.Printf("and_uint16 65535%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint16_65535_ssa(1); got != 1 { fmt.Printf("and_uint16 1%s65535 = %d, wanted 1\n", `&`, got) failed = true } if got := and_65535_uint16_ssa(65535); got != 65535 { fmt.Printf("and_uint16 65535%s65535 = %d, wanted 65535\n", `&`, got) failed = true } if got := and_uint16_65535_ssa(65535); got != 65535 { fmt.Printf("and_uint16 65535%s65535 = %d, wanted 65535\n", `&`, got) failed = true } if got := or_0_uint16_ssa(0); got != 0 { fmt.Printf("or_uint16 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_uint16_0_ssa(0); got != 0 { fmt.Printf("or_uint16 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_uint16_ssa(1); got != 1 { fmt.Printf("or_uint16 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint16_0_ssa(1); got != 1 { fmt.Printf("or_uint16 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_uint16_ssa(65535); got != 65535 { fmt.Printf("or_uint16 0%s65535 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_uint16_0_ssa(65535); got != 65535 { fmt.Printf("or_uint16 65535%s0 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_1_uint16_ssa(0); got != 1 { fmt.Printf("or_uint16 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint16_1_ssa(0); got != 1 { fmt.Printf("or_uint16 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint16_ssa(1); got != 1 { fmt.Printf("or_uint16 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint16_1_ssa(1); got != 1 { fmt.Printf("or_uint16 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint16_ssa(65535); got != 65535 { fmt.Printf("or_uint16 1%s65535 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_uint16_1_ssa(65535); got != 65535 { fmt.Printf("or_uint16 65535%s1 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_65535_uint16_ssa(0); got != 65535 { fmt.Printf("or_uint16 65535%s0 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_uint16_65535_ssa(0); got != 65535 { fmt.Printf("or_uint16 0%s65535 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_65535_uint16_ssa(1); got != 65535 { fmt.Printf("or_uint16 65535%s1 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_uint16_65535_ssa(1); got != 65535 { fmt.Printf("or_uint16 1%s65535 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_65535_uint16_ssa(65535); got != 65535 { fmt.Printf("or_uint16 65535%s65535 = %d, wanted 65535\n", `|`, got) failed = true } if got := or_uint16_65535_ssa(65535); got != 65535 { fmt.Printf("or_uint16 65535%s65535 = %d, wanted 65535\n", `|`, got) failed = true } if got := xor_0_uint16_ssa(0); got != 0 { fmt.Printf("xor_uint16 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint16_0_ssa(0); got != 0 { fmt.Printf("xor_uint16 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_uint16_ssa(1); got != 1 { fmt.Printf("xor_uint16 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint16_0_ssa(1); got != 1 { fmt.Printf("xor_uint16 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_uint16_ssa(65535); got != 65535 { fmt.Printf("xor_uint16 0%s65535 = %d, wanted 65535\n", `^`, got) failed = true } if got := xor_uint16_0_ssa(65535); got != 65535 { fmt.Printf("xor_uint16 65535%s0 = %d, wanted 65535\n", `^`, got) failed = true } if got := xor_1_uint16_ssa(0); got != 1 { fmt.Printf("xor_uint16 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint16_1_ssa(0); got != 1 { fmt.Printf("xor_uint16 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_uint16_ssa(1); got != 0 { fmt.Printf("xor_uint16 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint16_1_ssa(1); got != 0 { fmt.Printf("xor_uint16 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_uint16_ssa(65535); got != 65534 { fmt.Printf("xor_uint16 1%s65535 = %d, wanted 65534\n", `^`, got) failed = true } if got := xor_uint16_1_ssa(65535); got != 65534 { fmt.Printf("xor_uint16 65535%s1 = %d, wanted 65534\n", `^`, got) failed = true } if got := xor_65535_uint16_ssa(0); got != 65535 { fmt.Printf("xor_uint16 65535%s0 = %d, wanted 65535\n", `^`, got) failed = true } if got := xor_uint16_65535_ssa(0); got != 65535 { fmt.Printf("xor_uint16 0%s65535 = %d, wanted 65535\n", `^`, got) failed = true } if got := xor_65535_uint16_ssa(1); got != 65534 { fmt.Printf("xor_uint16 65535%s1 = %d, wanted 65534\n", `^`, got) failed = true } if got := xor_uint16_65535_ssa(1); got != 65534 { fmt.Printf("xor_uint16 1%s65535 = %d, wanted 65534\n", `^`, got) failed = true } if got := xor_65535_uint16_ssa(65535); got != 0 { fmt.Printf("xor_uint16 65535%s65535 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint16_65535_ssa(65535); got != 0 { fmt.Printf("xor_uint16 65535%s65535 = %d, wanted 0\n", `^`, got) failed = true } if got := add_Neg32768_int16_ssa(-32768); got != 0 { fmt.Printf("add_int16 -32768%s-32768 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(-32768); got != 0 { fmt.Printf("add_int16 -32768%s-32768 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg32768_int16_ssa(-32767); got != 1 { fmt.Printf("add_int16 -32768%s-32767 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(-32767); got != 1 { fmt.Printf("add_int16 -32767%s-32768 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg32768_int16_ssa(-1); got != 32767 { fmt.Printf("add_int16 -32768%s-1 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(-1); got != 32767 { fmt.Printf("add_int16 -1%s-32768 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_Neg32768_int16_ssa(0); got != -32768 { fmt.Printf("add_int16 -32768%s0 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(0); got != -32768 { fmt.Printf("add_int16 0%s-32768 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_Neg32768_int16_ssa(1); got != -32767 { fmt.Printf("add_int16 -32768%s1 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(1); got != -32767 { fmt.Printf("add_int16 1%s-32768 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_Neg32768_int16_ssa(32766); got != -2 { fmt.Printf("add_int16 -32768%s32766 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(32766); got != -2 { fmt.Printf("add_int16 32766%s-32768 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg32768_int16_ssa(32767); got != -1 { fmt.Printf("add_int16 -32768%s32767 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int16_Neg32768_ssa(32767); got != -1 { fmt.Printf("add_int16 32767%s-32768 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(-32768); got != 1 { fmt.Printf("add_int16 -32767%s-32768 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(-32768); got != 1 { fmt.Printf("add_int16 -32768%s-32767 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(-32767); got != 2 { fmt.Printf("add_int16 -32767%s-32767 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(-32767); got != 2 { fmt.Printf("add_int16 -32767%s-32767 = %d, wanted 2\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(-1); got != -32768 { fmt.Printf("add_int16 -32767%s-1 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(-1); got != -32768 { fmt.Printf("add_int16 -1%s-32767 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(0); got != -32767 { fmt.Printf("add_int16 -32767%s0 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(0); got != -32767 { fmt.Printf("add_int16 0%s-32767 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(1); got != -32766 { fmt.Printf("add_int16 -32767%s1 = %d, wanted -32766\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(1); got != -32766 { fmt.Printf("add_int16 1%s-32767 = %d, wanted -32766\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(32766); got != -1 { fmt.Printf("add_int16 -32767%s32766 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(32766); got != -1 { fmt.Printf("add_int16 32766%s-32767 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg32767_int16_ssa(32767); got != 0 { fmt.Printf("add_int16 -32767%s32767 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int16_Neg32767_ssa(32767); got != 0 { fmt.Printf("add_int16 32767%s-32767 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(-32768); got != 32767 { fmt.Printf("add_int16 -1%s-32768 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(-32768); got != 32767 { fmt.Printf("add_int16 -32768%s-1 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(-32767); got != -32768 { fmt.Printf("add_int16 -1%s-32767 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(-32767); got != -32768 { fmt.Printf("add_int16 -32767%s-1 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(-1); got != -2 { fmt.Printf("add_int16 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(-1); got != -2 { fmt.Printf("add_int16 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(0); got != -1 { fmt.Printf("add_int16 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(0); got != -1 { fmt.Printf("add_int16 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(1); got != 0 { fmt.Printf("add_int16 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(1); got != 0 { fmt.Printf("add_int16 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(32766); got != 32765 { fmt.Printf("add_int16 -1%s32766 = %d, wanted 32765\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(32766); got != 32765 { fmt.Printf("add_int16 32766%s-1 = %d, wanted 32765\n", `+`, got) failed = true } if got := add_Neg1_int16_ssa(32767); got != 32766 { fmt.Printf("add_int16 -1%s32767 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_int16_Neg1_ssa(32767); got != 32766 { fmt.Printf("add_int16 32767%s-1 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_0_int16_ssa(-32768); got != -32768 { fmt.Printf("add_int16 0%s-32768 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_int16_0_ssa(-32768); got != -32768 { fmt.Printf("add_int16 -32768%s0 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_0_int16_ssa(-32767); got != -32767 { fmt.Printf("add_int16 0%s-32767 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_int16_0_ssa(-32767); got != -32767 { fmt.Printf("add_int16 -32767%s0 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_0_int16_ssa(-1); got != -1 { fmt.Printf("add_int16 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int16_0_ssa(-1); got != -1 { fmt.Printf("add_int16 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_0_int16_ssa(0); got != 0 { fmt.Printf("add_int16 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int16_0_ssa(0); got != 0 { fmt.Printf("add_int16 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_int16_ssa(1); got != 1 { fmt.Printf("add_int16 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int16_0_ssa(1); got != 1 { fmt.Printf("add_int16 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_int16_ssa(32766); got != 32766 { fmt.Printf("add_int16 0%s32766 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_int16_0_ssa(32766); got != 32766 { fmt.Printf("add_int16 32766%s0 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_0_int16_ssa(32767); got != 32767 { fmt.Printf("add_int16 0%s32767 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_int16_0_ssa(32767); got != 32767 { fmt.Printf("add_int16 32767%s0 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_1_int16_ssa(-32768); got != -32767 { fmt.Printf("add_int16 1%s-32768 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_int16_1_ssa(-32768); got != -32767 { fmt.Printf("add_int16 -32768%s1 = %d, wanted -32767\n", `+`, got) failed = true } if got := add_1_int16_ssa(-32767); got != -32766 { fmt.Printf("add_int16 1%s-32767 = %d, wanted -32766\n", `+`, got) failed = true } if got := add_int16_1_ssa(-32767); got != -32766 { fmt.Printf("add_int16 -32767%s1 = %d, wanted -32766\n", `+`, got) failed = true } if got := add_1_int16_ssa(-1); got != 0 { fmt.Printf("add_int16 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int16_1_ssa(-1); got != 0 { fmt.Printf("add_int16 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_1_int16_ssa(0); got != 1 { fmt.Printf("add_int16 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int16_1_ssa(0); got != 1 { fmt.Printf("add_int16 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_int16_ssa(1); got != 2 { fmt.Printf("add_int16 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int16_1_ssa(1); got != 2 { fmt.Printf("add_int16 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_int16_ssa(32766); got != 32767 { fmt.Printf("add_int16 1%s32766 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_int16_1_ssa(32766); got != 32767 { fmt.Printf("add_int16 32766%s1 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_1_int16_ssa(32767); got != -32768 { fmt.Printf("add_int16 1%s32767 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_int16_1_ssa(32767); got != -32768 { fmt.Printf("add_int16 32767%s1 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_32766_int16_ssa(-32768); got != -2 { fmt.Printf("add_int16 32766%s-32768 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int16_32766_ssa(-32768); got != -2 { fmt.Printf("add_int16 -32768%s32766 = %d, wanted -2\n", `+`, got) failed = true } if got := add_32766_int16_ssa(-32767); got != -1 { fmt.Printf("add_int16 32766%s-32767 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int16_32766_ssa(-32767); got != -1 { fmt.Printf("add_int16 -32767%s32766 = %d, wanted -1\n", `+`, got) failed = true } if got := add_32766_int16_ssa(-1); got != 32765 { fmt.Printf("add_int16 32766%s-1 = %d, wanted 32765\n", `+`, got) failed = true } if got := add_int16_32766_ssa(-1); got != 32765 { fmt.Printf("add_int16 -1%s32766 = %d, wanted 32765\n", `+`, got) failed = true } if got := add_32766_int16_ssa(0); got != 32766 { fmt.Printf("add_int16 32766%s0 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_int16_32766_ssa(0); got != 32766 { fmt.Printf("add_int16 0%s32766 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_32766_int16_ssa(1); got != 32767 { fmt.Printf("add_int16 32766%s1 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_int16_32766_ssa(1); got != 32767 { fmt.Printf("add_int16 1%s32766 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_32766_int16_ssa(32766); got != -4 { fmt.Printf("add_int16 32766%s32766 = %d, wanted -4\n", `+`, got) failed = true } if got := add_int16_32766_ssa(32766); got != -4 { fmt.Printf("add_int16 32766%s32766 = %d, wanted -4\n", `+`, got) failed = true } if got := add_32766_int16_ssa(32767); got != -3 { fmt.Printf("add_int16 32766%s32767 = %d, wanted -3\n", `+`, got) failed = true } if got := add_int16_32766_ssa(32767); got != -3 { fmt.Printf("add_int16 32767%s32766 = %d, wanted -3\n", `+`, got) failed = true } if got := add_32767_int16_ssa(-32768); got != -1 { fmt.Printf("add_int16 32767%s-32768 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int16_32767_ssa(-32768); got != -1 { fmt.Printf("add_int16 -32768%s32767 = %d, wanted -1\n", `+`, got) failed = true } if got := add_32767_int16_ssa(-32767); got != 0 { fmt.Printf("add_int16 32767%s-32767 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int16_32767_ssa(-32767); got != 0 { fmt.Printf("add_int16 -32767%s32767 = %d, wanted 0\n", `+`, got) failed = true } if got := add_32767_int16_ssa(-1); got != 32766 { fmt.Printf("add_int16 32767%s-1 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_int16_32767_ssa(-1); got != 32766 { fmt.Printf("add_int16 -1%s32767 = %d, wanted 32766\n", `+`, got) failed = true } if got := add_32767_int16_ssa(0); got != 32767 { fmt.Printf("add_int16 32767%s0 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_int16_32767_ssa(0); got != 32767 { fmt.Printf("add_int16 0%s32767 = %d, wanted 32767\n", `+`, got) failed = true } if got := add_32767_int16_ssa(1); got != -32768 { fmt.Printf("add_int16 32767%s1 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_int16_32767_ssa(1); got != -32768 { fmt.Printf("add_int16 1%s32767 = %d, wanted -32768\n", `+`, got) failed = true } if got := add_32767_int16_ssa(32766); got != -3 { fmt.Printf("add_int16 32767%s32766 = %d, wanted -3\n", `+`, got) failed = true } if got := add_int16_32767_ssa(32766); got != -3 { fmt.Printf("add_int16 32766%s32767 = %d, wanted -3\n", `+`, got) failed = true } if got := add_32767_int16_ssa(32767); got != -2 { fmt.Printf("add_int16 32767%s32767 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int16_32767_ssa(32767); got != -2 { fmt.Printf("add_int16 32767%s32767 = %d, wanted -2\n", `+`, got) failed = true } if got := sub_Neg32768_int16_ssa(-32768); got != 0 { fmt.Printf("sub_int16 -32768%s-32768 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(-32768); got != 0 { fmt.Printf("sub_int16 -32768%s-32768 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg32768_int16_ssa(-32767); got != -1 { fmt.Printf("sub_int16 -32768%s-32767 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(-32767); got != 1 { fmt.Printf("sub_int16 -32767%s-32768 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg32768_int16_ssa(-1); got != -32767 { fmt.Printf("sub_int16 -32768%s-1 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(-1); got != 32767 { fmt.Printf("sub_int16 -1%s-32768 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_Neg32768_int16_ssa(0); got != -32768 { fmt.Printf("sub_int16 -32768%s0 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(0); got != -32768 { fmt.Printf("sub_int16 0%s-32768 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_Neg32768_int16_ssa(1); got != 32767 { fmt.Printf("sub_int16 -32768%s1 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(1); got != -32767 { fmt.Printf("sub_int16 1%s-32768 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_Neg32768_int16_ssa(32766); got != 2 { fmt.Printf("sub_int16 -32768%s32766 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(32766); got != -2 { fmt.Printf("sub_int16 32766%s-32768 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg32768_int16_ssa(32767); got != 1 { fmt.Printf("sub_int16 -32768%s32767 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int16_Neg32768_ssa(32767); got != -1 { fmt.Printf("sub_int16 32767%s-32768 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(-32768); got != 1 { fmt.Printf("sub_int16 -32767%s-32768 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(-32768); got != -1 { fmt.Printf("sub_int16 -32768%s-32767 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(-32767); got != 0 { fmt.Printf("sub_int16 -32767%s-32767 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(-32767); got != 0 { fmt.Printf("sub_int16 -32767%s-32767 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(-1); got != -32766 { fmt.Printf("sub_int16 -32767%s-1 = %d, wanted -32766\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(-1); got != 32766 { fmt.Printf("sub_int16 -1%s-32767 = %d, wanted 32766\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(0); got != -32767 { fmt.Printf("sub_int16 -32767%s0 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(0); got != 32767 { fmt.Printf("sub_int16 0%s-32767 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(1); got != -32768 { fmt.Printf("sub_int16 -32767%s1 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(1); got != -32768 { fmt.Printf("sub_int16 1%s-32767 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(32766); got != 3 { fmt.Printf("sub_int16 -32767%s32766 = %d, wanted 3\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(32766); got != -3 { fmt.Printf("sub_int16 32766%s-32767 = %d, wanted -3\n", `-`, got) failed = true } if got := sub_Neg32767_int16_ssa(32767); got != 2 { fmt.Printf("sub_int16 -32767%s32767 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int16_Neg32767_ssa(32767); got != -2 { fmt.Printf("sub_int16 32767%s-32767 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(-32768); got != 32767 { fmt.Printf("sub_int16 -1%s-32768 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(-32768); got != -32767 { fmt.Printf("sub_int16 -32768%s-1 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(-32767); got != 32766 { fmt.Printf("sub_int16 -1%s-32767 = %d, wanted 32766\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(-32767); got != -32766 { fmt.Printf("sub_int16 -32767%s-1 = %d, wanted -32766\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(-1); got != 0 { fmt.Printf("sub_int16 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(-1); got != 0 { fmt.Printf("sub_int16 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(0); got != -1 { fmt.Printf("sub_int16 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(0); got != 1 { fmt.Printf("sub_int16 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(1); got != -2 { fmt.Printf("sub_int16 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(1); got != 2 { fmt.Printf("sub_int16 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(32766); got != -32767 { fmt.Printf("sub_int16 -1%s32766 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(32766); got != 32767 { fmt.Printf("sub_int16 32766%s-1 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_Neg1_int16_ssa(32767); got != -32768 { fmt.Printf("sub_int16 -1%s32767 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_int16_Neg1_ssa(32767); got != -32768 { fmt.Printf("sub_int16 32767%s-1 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_0_int16_ssa(-32768); got != -32768 { fmt.Printf("sub_int16 0%s-32768 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_int16_0_ssa(-32768); got != -32768 { fmt.Printf("sub_int16 -32768%s0 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_0_int16_ssa(-32767); got != 32767 { fmt.Printf("sub_int16 0%s-32767 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_int16_0_ssa(-32767); got != -32767 { fmt.Printf("sub_int16 -32767%s0 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_0_int16_ssa(-1); got != 1 { fmt.Printf("sub_int16 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int16_0_ssa(-1); got != -1 { fmt.Printf("sub_int16 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_0_int16_ssa(0); got != 0 { fmt.Printf("sub_int16 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_0_ssa(0); got != 0 { fmt.Printf("sub_int16 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_int16_ssa(1); got != -1 { fmt.Printf("sub_int16 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int16_0_ssa(1); got != 1 { fmt.Printf("sub_int16 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_int16_ssa(32766); got != -32766 { fmt.Printf("sub_int16 0%s32766 = %d, wanted -32766\n", `-`, got) failed = true } if got := sub_int16_0_ssa(32766); got != 32766 { fmt.Printf("sub_int16 32766%s0 = %d, wanted 32766\n", `-`, got) failed = true } if got := sub_0_int16_ssa(32767); got != -32767 { fmt.Printf("sub_int16 0%s32767 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_int16_0_ssa(32767); got != 32767 { fmt.Printf("sub_int16 32767%s0 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_1_int16_ssa(-32768); got != -32767 { fmt.Printf("sub_int16 1%s-32768 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_int16_1_ssa(-32768); got != 32767 { fmt.Printf("sub_int16 -32768%s1 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_1_int16_ssa(-32767); got != -32768 { fmt.Printf("sub_int16 1%s-32767 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_int16_1_ssa(-32767); got != -32768 { fmt.Printf("sub_int16 -32767%s1 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_1_int16_ssa(-1); got != 2 { fmt.Printf("sub_int16 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int16_1_ssa(-1); got != -2 { fmt.Printf("sub_int16 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_1_int16_ssa(0); got != 1 { fmt.Printf("sub_int16 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int16_1_ssa(0); got != -1 { fmt.Printf("sub_int16 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_1_int16_ssa(1); got != 0 { fmt.Printf("sub_int16 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_1_ssa(1); got != 0 { fmt.Printf("sub_int16 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_int16_ssa(32766); got != -32765 { fmt.Printf("sub_int16 1%s32766 = %d, wanted -32765\n", `-`, got) failed = true } if got := sub_int16_1_ssa(32766); got != 32765 { fmt.Printf("sub_int16 32766%s1 = %d, wanted 32765\n", `-`, got) failed = true } if got := sub_1_int16_ssa(32767); got != -32766 { fmt.Printf("sub_int16 1%s32767 = %d, wanted -32766\n", `-`, got) failed = true } if got := sub_int16_1_ssa(32767); got != 32766 { fmt.Printf("sub_int16 32767%s1 = %d, wanted 32766\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(-32768); got != -2 { fmt.Printf("sub_int16 32766%s-32768 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(-32768); got != 2 { fmt.Printf("sub_int16 -32768%s32766 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(-32767); got != -3 { fmt.Printf("sub_int16 32766%s-32767 = %d, wanted -3\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(-32767); got != 3 { fmt.Printf("sub_int16 -32767%s32766 = %d, wanted 3\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(-1); got != 32767 { fmt.Printf("sub_int16 32766%s-1 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(-1); got != -32767 { fmt.Printf("sub_int16 -1%s32766 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(0); got != 32766 { fmt.Printf("sub_int16 32766%s0 = %d, wanted 32766\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(0); got != -32766 { fmt.Printf("sub_int16 0%s32766 = %d, wanted -32766\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(1); got != 32765 { fmt.Printf("sub_int16 32766%s1 = %d, wanted 32765\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(1); got != -32765 { fmt.Printf("sub_int16 1%s32766 = %d, wanted -32765\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(32766); got != 0 { fmt.Printf("sub_int16 32766%s32766 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(32766); got != 0 { fmt.Printf("sub_int16 32766%s32766 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_32766_int16_ssa(32767); got != -1 { fmt.Printf("sub_int16 32766%s32767 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int16_32766_ssa(32767); got != 1 { fmt.Printf("sub_int16 32767%s32766 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(-32768); got != -1 { fmt.Printf("sub_int16 32767%s-32768 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(-32768); got != 1 { fmt.Printf("sub_int16 -32768%s32767 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(-32767); got != -2 { fmt.Printf("sub_int16 32767%s-32767 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(-32767); got != 2 { fmt.Printf("sub_int16 -32767%s32767 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(-1); got != -32768 { fmt.Printf("sub_int16 32767%s-1 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(-1); got != -32768 { fmt.Printf("sub_int16 -1%s32767 = %d, wanted -32768\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(0); got != 32767 { fmt.Printf("sub_int16 32767%s0 = %d, wanted 32767\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(0); got != -32767 { fmt.Printf("sub_int16 0%s32767 = %d, wanted -32767\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(1); got != 32766 { fmt.Printf("sub_int16 32767%s1 = %d, wanted 32766\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(1); got != -32766 { fmt.Printf("sub_int16 1%s32767 = %d, wanted -32766\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(32766); got != 1 { fmt.Printf("sub_int16 32767%s32766 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(32766); got != -1 { fmt.Printf("sub_int16 32766%s32767 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_32767_int16_ssa(32767); got != 0 { fmt.Printf("sub_int16 32767%s32767 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int16_32767_ssa(32767); got != 0 { fmt.Printf("sub_int16 32767%s32767 = %d, wanted 0\n", `-`, got) failed = true } if got := div_Neg32768_int16_ssa(-32768); got != 1 { fmt.Printf("div_int16 -32768%s-32768 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(-32768); got != 1 { fmt.Printf("div_int16 -32768%s-32768 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg32768_int16_ssa(-32767); got != 1 { fmt.Printf("div_int16 -32768%s-32767 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(-32767); got != 0 { fmt.Printf("div_int16 -32767%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32768_int16_ssa(-1); got != -32768 { fmt.Printf("div_int16 -32768%s-1 = %d, wanted -32768\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(-1); got != 0 { fmt.Printf("div_int16 -1%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(0); got != 0 { fmt.Printf("div_int16 0%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32768_int16_ssa(1); got != -32768 { fmt.Printf("div_int16 -32768%s1 = %d, wanted -32768\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(1); got != 0 { fmt.Printf("div_int16 1%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32768_int16_ssa(32766); got != -1 { fmt.Printf("div_int16 -32768%s32766 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(32766); got != 0 { fmt.Printf("div_int16 32766%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32768_int16_ssa(32767); got != -1 { fmt.Printf("div_int16 -32768%s32767 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_Neg32768_ssa(32767); got != 0 { fmt.Printf("div_int16 32767%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32767_int16_ssa(-32768); got != 0 { fmt.Printf("div_int16 -32767%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(-32768); got != 1 { fmt.Printf("div_int16 -32768%s-32767 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg32767_int16_ssa(-32767); got != 1 { fmt.Printf("div_int16 -32767%s-32767 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(-32767); got != 1 { fmt.Printf("div_int16 -32767%s-32767 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg32767_int16_ssa(-1); got != 32767 { fmt.Printf("div_int16 -32767%s-1 = %d, wanted 32767\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(-1); got != 0 { fmt.Printf("div_int16 -1%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(0); got != 0 { fmt.Printf("div_int16 0%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32767_int16_ssa(1); got != -32767 { fmt.Printf("div_int16 -32767%s1 = %d, wanted -32767\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(1); got != 0 { fmt.Printf("div_int16 1%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32767_int16_ssa(32766); got != -1 { fmt.Printf("div_int16 -32767%s32766 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(32766); got != 0 { fmt.Printf("div_int16 32766%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg32767_int16_ssa(32767); got != -1 { fmt.Printf("div_int16 -32767%s32767 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_Neg32767_ssa(32767); got != -1 { fmt.Printf("div_int16 32767%s-32767 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int16_ssa(-32768); got != 0 { fmt.Printf("div_int16 -1%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(-32768); got != -32768 { fmt.Printf("div_int16 -32768%s-1 = %d, wanted -32768\n", `/`, got) failed = true } if got := div_Neg1_int16_ssa(-32767); got != 0 { fmt.Printf("div_int16 -1%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(-32767); got != 32767 { fmt.Printf("div_int16 -32767%s-1 = %d, wanted 32767\n", `/`, got) failed = true } if got := div_Neg1_int16_ssa(-1); got != 1 { fmt.Printf("div_int16 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(-1); got != 1 { fmt.Printf("div_int16 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(0); got != 0 { fmt.Printf("div_int16 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg1_int16_ssa(1); got != -1 { fmt.Printf("div_int16 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(1); got != -1 { fmt.Printf("div_int16 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int16_ssa(32766); got != 0 { fmt.Printf("div_int16 -1%s32766 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(32766); got != -32766 { fmt.Printf("div_int16 32766%s-1 = %d, wanted -32766\n", `/`, got) failed = true } if got := div_Neg1_int16_ssa(32767); got != 0 { fmt.Printf("div_int16 -1%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_Neg1_ssa(32767); got != -32767 { fmt.Printf("div_int16 32767%s-1 = %d, wanted -32767\n", `/`, got) failed = true } if got := div_0_int16_ssa(-32768); got != 0 { fmt.Printf("div_int16 0%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int16_ssa(-32767); got != 0 { fmt.Printf("div_int16 0%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int16_ssa(-1); got != 0 { fmt.Printf("div_int16 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int16_ssa(1); got != 0 { fmt.Printf("div_int16 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int16_ssa(32766); got != 0 { fmt.Printf("div_int16 0%s32766 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int16_ssa(32767); got != 0 { fmt.Printf("div_int16 0%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int16_ssa(-32768); got != 0 { fmt.Printf("div_int16 1%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_1_ssa(-32768); got != -32768 { fmt.Printf("div_int16 -32768%s1 = %d, wanted -32768\n", `/`, got) failed = true } if got := div_1_int16_ssa(-32767); got != 0 { fmt.Printf("div_int16 1%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_1_ssa(-32767); got != -32767 { fmt.Printf("div_int16 -32767%s1 = %d, wanted -32767\n", `/`, got) failed = true } if got := div_1_int16_ssa(-1); got != -1 { fmt.Printf("div_int16 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_1_ssa(-1); got != -1 { fmt.Printf("div_int16 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_1_ssa(0); got != 0 { fmt.Printf("div_int16 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int16_ssa(1); got != 1 { fmt.Printf("div_int16 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_1_ssa(1); got != 1 { fmt.Printf("div_int16 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_int16_ssa(32766); got != 0 { fmt.Printf("div_int16 1%s32766 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_1_ssa(32766); got != 32766 { fmt.Printf("div_int16 32766%s1 = %d, wanted 32766\n", `/`, got) failed = true } if got := div_1_int16_ssa(32767); got != 0 { fmt.Printf("div_int16 1%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_1_ssa(32767); got != 32767 { fmt.Printf("div_int16 32767%s1 = %d, wanted 32767\n", `/`, got) failed = true } if got := div_32766_int16_ssa(-32768); got != 0 { fmt.Printf("div_int16 32766%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_32766_ssa(-32768); got != -1 { fmt.Printf("div_int16 -32768%s32766 = %d, wanted -1\n", `/`, got) failed = true } if got := div_32766_int16_ssa(-32767); got != 0 { fmt.Printf("div_int16 32766%s-32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_32766_ssa(-32767); got != -1 { fmt.Printf("div_int16 -32767%s32766 = %d, wanted -1\n", `/`, got) failed = true } if got := div_32766_int16_ssa(-1); got != -32766 { fmt.Printf("div_int16 32766%s-1 = %d, wanted -32766\n", `/`, got) failed = true } if got := div_int16_32766_ssa(-1); got != 0 { fmt.Printf("div_int16 -1%s32766 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_32766_ssa(0); got != 0 { fmt.Printf("div_int16 0%s32766 = %d, wanted 0\n", `/`, got) failed = true } if got := div_32766_int16_ssa(1); got != 32766 { fmt.Printf("div_int16 32766%s1 = %d, wanted 32766\n", `/`, got) failed = true } if got := div_int16_32766_ssa(1); got != 0 { fmt.Printf("div_int16 1%s32766 = %d, wanted 0\n", `/`, got) failed = true } if got := div_32766_int16_ssa(32766); got != 1 { fmt.Printf("div_int16 32766%s32766 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_32766_ssa(32766); got != 1 { fmt.Printf("div_int16 32766%s32766 = %d, wanted 1\n", `/`, got) failed = true } if got := div_32766_int16_ssa(32767); got != 0 { fmt.Printf("div_int16 32766%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_32766_ssa(32767); got != 1 { fmt.Printf("div_int16 32767%s32766 = %d, wanted 1\n", `/`, got) failed = true } if got := div_32767_int16_ssa(-32768); got != 0 { fmt.Printf("div_int16 32767%s-32768 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_32767_ssa(-32768); got != -1 { fmt.Printf("div_int16 -32768%s32767 = %d, wanted -1\n", `/`, got) failed = true } if got := div_32767_int16_ssa(-32767); got != -1 { fmt.Printf("div_int16 32767%s-32767 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int16_32767_ssa(-32767); got != -1 { fmt.Printf("div_int16 -32767%s32767 = %d, wanted -1\n", `/`, got) failed = true } if got := div_32767_int16_ssa(-1); got != -32767 { fmt.Printf("div_int16 32767%s-1 = %d, wanted -32767\n", `/`, got) failed = true } if got := div_int16_32767_ssa(-1); got != 0 { fmt.Printf("div_int16 -1%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int16_32767_ssa(0); got != 0 { fmt.Printf("div_int16 0%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_32767_int16_ssa(1); got != 32767 { fmt.Printf("div_int16 32767%s1 = %d, wanted 32767\n", `/`, got) failed = true } if got := div_int16_32767_ssa(1); got != 0 { fmt.Printf("div_int16 1%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_32767_int16_ssa(32766); got != 1 { fmt.Printf("div_int16 32767%s32766 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_32767_ssa(32766); got != 0 { fmt.Printf("div_int16 32766%s32767 = %d, wanted 0\n", `/`, got) failed = true } if got := div_32767_int16_ssa(32767); got != 1 { fmt.Printf("div_int16 32767%s32767 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int16_32767_ssa(32767); got != 1 { fmt.Printf("div_int16 32767%s32767 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_Neg32768_int16_ssa(-32768); got != 0 { fmt.Printf("mul_int16 -32768%s-32768 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(-32768); got != 0 { fmt.Printf("mul_int16 -32768%s-32768 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg32768_int16_ssa(-32767); got != -32768 { fmt.Printf("mul_int16 -32768%s-32767 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(-32767); got != -32768 { fmt.Printf("mul_int16 -32767%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_Neg32768_int16_ssa(-1); got != -32768 { fmt.Printf("mul_int16 -32768%s-1 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(-1); got != -32768 { fmt.Printf("mul_int16 -1%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_Neg32768_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 -32768%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s-32768 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg32768_int16_ssa(1); got != -32768 { fmt.Printf("mul_int16 -32768%s1 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(1); got != -32768 { fmt.Printf("mul_int16 1%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_Neg32768_int16_ssa(32766); got != 0 { fmt.Printf("mul_int16 -32768%s32766 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(32766); got != 0 { fmt.Printf("mul_int16 32766%s-32768 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg32768_int16_ssa(32767); got != -32768 { fmt.Printf("mul_int16 -32768%s32767 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_Neg32768_ssa(32767); got != -32768 { fmt.Printf("mul_int16 32767%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 -32767%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 -32768%s-32767 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(-32767); got != 1 { fmt.Printf("mul_int16 -32767%s-32767 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(-32767); got != 1 { fmt.Printf("mul_int16 -32767%s-32767 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(-1); got != 32767 { fmt.Printf("mul_int16 -32767%s-1 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(-1); got != 32767 { fmt.Printf("mul_int16 -1%s-32767 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 -32767%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s-32767 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(1); got != -32767 { fmt.Printf("mul_int16 -32767%s1 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(1); got != -32767 { fmt.Printf("mul_int16 1%s-32767 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(32766); got != 32766 { fmt.Printf("mul_int16 -32767%s32766 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(32766); got != 32766 { fmt.Printf("mul_int16 32766%s-32767 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_Neg32767_int16_ssa(32767); got != -1 { fmt.Printf("mul_int16 -32767%s32767 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int16_Neg32767_ssa(32767); got != -1 { fmt.Printf("mul_int16 32767%s-32767 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 -1%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 -32768%s-1 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(-32767); got != 32767 { fmt.Printf("mul_int16 -1%s-32767 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(-32767); got != 32767 { fmt.Printf("mul_int16 -32767%s-1 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(-1); got != 1 { fmt.Printf("mul_int16 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(-1); got != 1 { fmt.Printf("mul_int16 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(1); got != -1 { fmt.Printf("mul_int16 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(1); got != -1 { fmt.Printf("mul_int16 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(32766); got != -32766 { fmt.Printf("mul_int16 -1%s32766 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(32766); got != -32766 { fmt.Printf("mul_int16 32766%s-1 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_Neg1_int16_ssa(32767); got != -32767 { fmt.Printf("mul_int16 -1%s32767 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_int16_Neg1_ssa(32767); got != -32767 { fmt.Printf("mul_int16 32767%s-1 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_0_int16_ssa(-32768); got != 0 { fmt.Printf("mul_int16 0%s-32768 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(-32768); got != 0 { fmt.Printf("mul_int16 -32768%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int16_ssa(-32767); got != 0 { fmt.Printf("mul_int16 0%s-32767 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(-32767); got != 0 { fmt.Printf("mul_int16 -32767%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int16_ssa(-1); got != 0 { fmt.Printf("mul_int16 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(-1); got != 0 { fmt.Printf("mul_int16 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int16_ssa(1); got != 0 { fmt.Printf("mul_int16 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(1); got != 0 { fmt.Printf("mul_int16 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int16_ssa(32766); got != 0 { fmt.Printf("mul_int16 0%s32766 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(32766); got != 0 { fmt.Printf("mul_int16 32766%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int16_ssa(32767); got != 0 { fmt.Printf("mul_int16 0%s32767 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_0_ssa(32767); got != 0 { fmt.Printf("mul_int16 32767%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int16_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 1%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_1_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 -32768%s1 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_1_int16_ssa(-32767); got != -32767 { fmt.Printf("mul_int16 1%s-32767 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_int16_1_ssa(-32767); got != -32767 { fmt.Printf("mul_int16 -32767%s1 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_1_int16_ssa(-1); got != -1 { fmt.Printf("mul_int16 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int16_1_ssa(-1); got != -1 { fmt.Printf("mul_int16 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_1_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_1_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int16_ssa(1); got != 1 { fmt.Printf("mul_int16 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int16_1_ssa(1); got != 1 { fmt.Printf("mul_int16 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_int16_ssa(32766); got != 32766 { fmt.Printf("mul_int16 1%s32766 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_int16_1_ssa(32766); got != 32766 { fmt.Printf("mul_int16 32766%s1 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_1_int16_ssa(32767); got != 32767 { fmt.Printf("mul_int16 1%s32767 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_int16_1_ssa(32767); got != 32767 { fmt.Printf("mul_int16 32767%s1 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(-32768); got != 0 { fmt.Printf("mul_int16 32766%s-32768 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(-32768); got != 0 { fmt.Printf("mul_int16 -32768%s32766 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(-32767); got != 32766 { fmt.Printf("mul_int16 32766%s-32767 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(-32767); got != 32766 { fmt.Printf("mul_int16 -32767%s32766 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(-1); got != -32766 { fmt.Printf("mul_int16 32766%s-1 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(-1); got != -32766 { fmt.Printf("mul_int16 -1%s32766 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 32766%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s32766 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(1); got != 32766 { fmt.Printf("mul_int16 32766%s1 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(1); got != 32766 { fmt.Printf("mul_int16 1%s32766 = %d, wanted 32766\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(32766); got != 4 { fmt.Printf("mul_int16 32766%s32766 = %d, wanted 4\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(32766); got != 4 { fmt.Printf("mul_int16 32766%s32766 = %d, wanted 4\n", `*`, got) failed = true } if got := mul_32766_int16_ssa(32767); got != -32766 { fmt.Printf("mul_int16 32766%s32767 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_int16_32766_ssa(32767); got != -32766 { fmt.Printf("mul_int16 32767%s32766 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 32767%s-32768 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(-32768); got != -32768 { fmt.Printf("mul_int16 -32768%s32767 = %d, wanted -32768\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(-32767); got != -1 { fmt.Printf("mul_int16 32767%s-32767 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(-32767); got != -1 { fmt.Printf("mul_int16 -32767%s32767 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(-1); got != -32767 { fmt.Printf("mul_int16 32767%s-1 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(-1); got != -32767 { fmt.Printf("mul_int16 -1%s32767 = %d, wanted -32767\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(0); got != 0 { fmt.Printf("mul_int16 32767%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(0); got != 0 { fmt.Printf("mul_int16 0%s32767 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(1); got != 32767 { fmt.Printf("mul_int16 32767%s1 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(1); got != 32767 { fmt.Printf("mul_int16 1%s32767 = %d, wanted 32767\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(32766); got != -32766 { fmt.Printf("mul_int16 32767%s32766 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(32766); got != -32766 { fmt.Printf("mul_int16 32766%s32767 = %d, wanted -32766\n", `*`, got) failed = true } if got := mul_32767_int16_ssa(32767); got != 1 { fmt.Printf("mul_int16 32767%s32767 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int16_32767_ssa(32767); got != 1 { fmt.Printf("mul_int16 32767%s32767 = %d, wanted 1\n", `*`, got) failed = true } if got := mod_Neg32768_int16_ssa(-32768); got != 0 { fmt.Printf("mod_int16 -32768%s-32768 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(-32768); got != 0 { fmt.Printf("mod_int16 -32768%s-32768 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg32768_int16_ssa(-32767); got != -1 { fmt.Printf("mod_int16 -32768%s-32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(-32767); got != -32767 { fmt.Printf("mod_int16 -32767%s-32768 = %d, wanted -32767\n", `%`, got) failed = true } if got := mod_Neg32768_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 -32768%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(-1); got != -1 { fmt.Printf("mod_int16 -1%s-32768 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(0); got != 0 { fmt.Printf("mod_int16 0%s-32768 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg32768_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 -32768%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(1); got != 1 { fmt.Printf("mod_int16 1%s-32768 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg32768_int16_ssa(32766); got != -2 { fmt.Printf("mod_int16 -32768%s32766 = %d, wanted -2\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(32766); got != 32766 { fmt.Printf("mod_int16 32766%s-32768 = %d, wanted 32766\n", `%`, got) failed = true } if got := mod_Neg32768_int16_ssa(32767); got != -1 { fmt.Printf("mod_int16 -32768%s32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg32768_ssa(32767); got != 32767 { fmt.Printf("mod_int16 32767%s-32768 = %d, wanted 32767\n", `%`, got) failed = true } if got := mod_Neg32767_int16_ssa(-32768); got != -32767 { fmt.Printf("mod_int16 -32767%s-32768 = %d, wanted -32767\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(-32768); got != -1 { fmt.Printf("mod_int16 -32768%s-32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_Neg32767_int16_ssa(-32767); got != 0 { fmt.Printf("mod_int16 -32767%s-32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(-32767); got != 0 { fmt.Printf("mod_int16 -32767%s-32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg32767_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 -32767%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(-1); got != -1 { fmt.Printf("mod_int16 -1%s-32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(0); got != 0 { fmt.Printf("mod_int16 0%s-32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg32767_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 -32767%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(1); got != 1 { fmt.Printf("mod_int16 1%s-32767 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg32767_int16_ssa(32766); got != -1 { fmt.Printf("mod_int16 -32767%s32766 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(32766); got != 32766 { fmt.Printf("mod_int16 32766%s-32767 = %d, wanted 32766\n", `%`, got) failed = true } if got := mod_Neg32767_int16_ssa(32767); got != 0 { fmt.Printf("mod_int16 -32767%s32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg32767_ssa(32767); got != 0 { fmt.Printf("mod_int16 32767%s-32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int16_ssa(-32768); got != -1 { fmt.Printf("mod_int16 -1%s-32768 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(-32768); got != 0 { fmt.Printf("mod_int16 -32768%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int16_ssa(-32767); got != -1 { fmt.Printf("mod_int16 -1%s-32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(-32767); got != 0 { fmt.Printf("mod_int16 -32767%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(-1); got != 0 { fmt.Printf("mod_int16 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(0); got != 0 { fmt.Printf("mod_int16 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(1); got != 0 { fmt.Printf("mod_int16 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int16_ssa(32766); got != -1 { fmt.Printf("mod_int16 -1%s32766 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(32766); got != 0 { fmt.Printf("mod_int16 32766%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int16_ssa(32767); got != -1 { fmt.Printf("mod_int16 -1%s32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_Neg1_ssa(32767); got != 0 { fmt.Printf("mod_int16 32767%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int16_ssa(-32768); got != 0 { fmt.Printf("mod_int16 0%s-32768 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int16_ssa(-32767); got != 0 { fmt.Printf("mod_int16 0%s-32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int16_ssa(32766); got != 0 { fmt.Printf("mod_int16 0%s32766 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int16_ssa(32767); got != 0 { fmt.Printf("mod_int16 0%s32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int16_ssa(-32768); got != 1 { fmt.Printf("mod_int16 1%s-32768 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int16_1_ssa(-32768); got != 0 { fmt.Printf("mod_int16 -32768%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int16_ssa(-32767); got != 1 { fmt.Printf("mod_int16 1%s-32767 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int16_1_ssa(-32767); got != 0 { fmt.Printf("mod_int16 -32767%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_1_ssa(-1); got != 0 { fmt.Printf("mod_int16 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_1_ssa(0); got != 0 { fmt.Printf("mod_int16 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_1_ssa(1); got != 0 { fmt.Printf("mod_int16 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int16_ssa(32766); got != 1 { fmt.Printf("mod_int16 1%s32766 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int16_1_ssa(32766); got != 0 { fmt.Printf("mod_int16 32766%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int16_ssa(32767); got != 1 { fmt.Printf("mod_int16 1%s32767 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int16_1_ssa(32767); got != 0 { fmt.Printf("mod_int16 32767%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_32766_int16_ssa(-32768); got != 32766 { fmt.Printf("mod_int16 32766%s-32768 = %d, wanted 32766\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(-32768); got != -2 { fmt.Printf("mod_int16 -32768%s32766 = %d, wanted -2\n", `%`, got) failed = true } if got := mod_32766_int16_ssa(-32767); got != 32766 { fmt.Printf("mod_int16 32766%s-32767 = %d, wanted 32766\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(-32767); got != -1 { fmt.Printf("mod_int16 -32767%s32766 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_32766_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 32766%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(-1); got != -1 { fmt.Printf("mod_int16 -1%s32766 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(0); got != 0 { fmt.Printf("mod_int16 0%s32766 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_32766_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 32766%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(1); got != 1 { fmt.Printf("mod_int16 1%s32766 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_32766_int16_ssa(32766); got != 0 { fmt.Printf("mod_int16 32766%s32766 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(32766); got != 0 { fmt.Printf("mod_int16 32766%s32766 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_32766_int16_ssa(32767); got != 32766 { fmt.Printf("mod_int16 32766%s32767 = %d, wanted 32766\n", `%`, got) failed = true } if got := mod_int16_32766_ssa(32767); got != 1 { fmt.Printf("mod_int16 32767%s32766 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_32767_int16_ssa(-32768); got != 32767 { fmt.Printf("mod_int16 32767%s-32768 = %d, wanted 32767\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(-32768); got != -1 { fmt.Printf("mod_int16 -32768%s32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_32767_int16_ssa(-32767); got != 0 { fmt.Printf("mod_int16 32767%s-32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(-32767); got != 0 { fmt.Printf("mod_int16 -32767%s32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_32767_int16_ssa(-1); got != 0 { fmt.Printf("mod_int16 32767%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(-1); got != -1 { fmt.Printf("mod_int16 -1%s32767 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(0); got != 0 { fmt.Printf("mod_int16 0%s32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_32767_int16_ssa(1); got != 0 { fmt.Printf("mod_int16 32767%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(1); got != 1 { fmt.Printf("mod_int16 1%s32767 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_32767_int16_ssa(32766); got != 1 { fmt.Printf("mod_int16 32767%s32766 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(32766); got != 32766 { fmt.Printf("mod_int16 32766%s32767 = %d, wanted 32766\n", `%`, got) failed = true } if got := mod_32767_int16_ssa(32767); got != 0 { fmt.Printf("mod_int16 32767%s32767 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int16_32767_ssa(32767); got != 0 { fmt.Printf("mod_int16 32767%s32767 = %d, wanted 0\n", `%`, got) failed = true } if got := and_Neg32768_int16_ssa(-32768); got != -32768 { fmt.Printf("and_int16 -32768%s-32768 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(-32768); got != -32768 { fmt.Printf("and_int16 -32768%s-32768 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_Neg32768_int16_ssa(-32767); got != -32768 { fmt.Printf("and_int16 -32768%s-32767 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(-32767); got != -32768 { fmt.Printf("and_int16 -32767%s-32768 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_Neg32768_int16_ssa(-1); got != -32768 { fmt.Printf("and_int16 -32768%s-1 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(-1); got != -32768 { fmt.Printf("and_int16 -1%s-32768 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_Neg32768_int16_ssa(0); got != 0 { fmt.Printf("and_int16 -32768%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(0); got != 0 { fmt.Printf("and_int16 0%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg32768_int16_ssa(1); got != 0 { fmt.Printf("and_int16 -32768%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(1); got != 0 { fmt.Printf("and_int16 1%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg32768_int16_ssa(32766); got != 0 { fmt.Printf("and_int16 -32768%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(32766); got != 0 { fmt.Printf("and_int16 32766%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg32768_int16_ssa(32767); got != 0 { fmt.Printf("and_int16 -32768%s32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg32768_ssa(32767); got != 0 { fmt.Printf("and_int16 32767%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(-32768); got != -32768 { fmt.Printf("and_int16 -32767%s-32768 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(-32768); got != -32768 { fmt.Printf("and_int16 -32768%s-32767 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(-32767); got != -32767 { fmt.Printf("and_int16 -32767%s-32767 = %d, wanted -32767\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(-32767); got != -32767 { fmt.Printf("and_int16 -32767%s-32767 = %d, wanted -32767\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(-1); got != -32767 { fmt.Printf("and_int16 -32767%s-1 = %d, wanted -32767\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(-1); got != -32767 { fmt.Printf("and_int16 -1%s-32767 = %d, wanted -32767\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(0); got != 0 { fmt.Printf("and_int16 -32767%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(0); got != 0 { fmt.Printf("and_int16 0%s-32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(1); got != 1 { fmt.Printf("and_int16 -32767%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(1); got != 1 { fmt.Printf("and_int16 1%s-32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(32766); got != 0 { fmt.Printf("and_int16 -32767%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(32766); got != 0 { fmt.Printf("and_int16 32766%s-32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg32767_int16_ssa(32767); got != 1 { fmt.Printf("and_int16 -32767%s32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_Neg32767_ssa(32767); got != 1 { fmt.Printf("and_int16 32767%s-32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(-32768); got != -32768 { fmt.Printf("and_int16 -1%s-32768 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(-32768); got != -32768 { fmt.Printf("and_int16 -32768%s-1 = %d, wanted -32768\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(-32767); got != -32767 { fmt.Printf("and_int16 -1%s-32767 = %d, wanted -32767\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(-32767); got != -32767 { fmt.Printf("and_int16 -32767%s-1 = %d, wanted -32767\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(-1); got != -1 { fmt.Printf("and_int16 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(-1); got != -1 { fmt.Printf("and_int16 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(0); got != 0 { fmt.Printf("and_int16 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(0); got != 0 { fmt.Printf("and_int16 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(1); got != 1 { fmt.Printf("and_int16 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(1); got != 1 { fmt.Printf("and_int16 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(32766); got != 32766 { fmt.Printf("and_int16 -1%s32766 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(32766); got != 32766 { fmt.Printf("and_int16 32766%s-1 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_Neg1_int16_ssa(32767); got != 32767 { fmt.Printf("and_int16 -1%s32767 = %d, wanted 32767\n", `&`, got) failed = true } if got := and_int16_Neg1_ssa(32767); got != 32767 { fmt.Printf("and_int16 32767%s-1 = %d, wanted 32767\n", `&`, got) failed = true } if got := and_0_int16_ssa(-32768); got != 0 { fmt.Printf("and_int16 0%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(-32768); got != 0 { fmt.Printf("and_int16 -32768%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int16_ssa(-32767); got != 0 { fmt.Printf("and_int16 0%s-32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(-32767); got != 0 { fmt.Printf("and_int16 -32767%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int16_ssa(-1); got != 0 { fmt.Printf("and_int16 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(-1); got != 0 { fmt.Printf("and_int16 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int16_ssa(0); got != 0 { fmt.Printf("and_int16 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(0); got != 0 { fmt.Printf("and_int16 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int16_ssa(1); got != 0 { fmt.Printf("and_int16 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(1); got != 0 { fmt.Printf("and_int16 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int16_ssa(32766); got != 0 { fmt.Printf("and_int16 0%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(32766); got != 0 { fmt.Printf("and_int16 32766%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int16_ssa(32767); got != 0 { fmt.Printf("and_int16 0%s32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_0_ssa(32767); got != 0 { fmt.Printf("and_int16 32767%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int16_ssa(-32768); got != 0 { fmt.Printf("and_int16 1%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_1_ssa(-32768); got != 0 { fmt.Printf("and_int16 -32768%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int16_ssa(-32767); got != 1 { fmt.Printf("and_int16 1%s-32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_1_ssa(-32767); got != 1 { fmt.Printf("and_int16 -32767%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int16_ssa(-1); got != 1 { fmt.Printf("and_int16 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_1_ssa(-1); got != 1 { fmt.Printf("and_int16 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int16_ssa(0); got != 0 { fmt.Printf("and_int16 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_1_ssa(0); got != 0 { fmt.Printf("and_int16 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int16_ssa(1); got != 1 { fmt.Printf("and_int16 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_1_ssa(1); got != 1 { fmt.Printf("and_int16 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int16_ssa(32766); got != 0 { fmt.Printf("and_int16 1%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_1_ssa(32766); got != 0 { fmt.Printf("and_int16 32766%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int16_ssa(32767); got != 1 { fmt.Printf("and_int16 1%s32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_1_ssa(32767); got != 1 { fmt.Printf("and_int16 32767%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_32766_int16_ssa(-32768); got != 0 { fmt.Printf("and_int16 32766%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_32766_ssa(-32768); got != 0 { fmt.Printf("and_int16 -32768%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_32766_int16_ssa(-32767); got != 0 { fmt.Printf("and_int16 32766%s-32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_32766_ssa(-32767); got != 0 { fmt.Printf("and_int16 -32767%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_32766_int16_ssa(-1); got != 32766 { fmt.Printf("and_int16 32766%s-1 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_int16_32766_ssa(-1); got != 32766 { fmt.Printf("and_int16 -1%s32766 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_32766_int16_ssa(0); got != 0 { fmt.Printf("and_int16 32766%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_32766_ssa(0); got != 0 { fmt.Printf("and_int16 0%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_32766_int16_ssa(1); got != 0 { fmt.Printf("and_int16 32766%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_32766_ssa(1); got != 0 { fmt.Printf("and_int16 1%s32766 = %d, wanted 0\n", `&`, got) failed = true } if got := and_32766_int16_ssa(32766); got != 32766 { fmt.Printf("and_int16 32766%s32766 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_int16_32766_ssa(32766); got != 32766 { fmt.Printf("and_int16 32766%s32766 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_32766_int16_ssa(32767); got != 32766 { fmt.Printf("and_int16 32766%s32767 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_int16_32766_ssa(32767); got != 32766 { fmt.Printf("and_int16 32767%s32766 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_32767_int16_ssa(-32768); got != 0 { fmt.Printf("and_int16 32767%s-32768 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_32767_ssa(-32768); got != 0 { fmt.Printf("and_int16 -32768%s32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_32767_int16_ssa(-32767); got != 1 { fmt.Printf("and_int16 32767%s-32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_32767_ssa(-32767); got != 1 { fmt.Printf("and_int16 -32767%s32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_32767_int16_ssa(-1); got != 32767 { fmt.Printf("and_int16 32767%s-1 = %d, wanted 32767\n", `&`, got) failed = true } if got := and_int16_32767_ssa(-1); got != 32767 { fmt.Printf("and_int16 -1%s32767 = %d, wanted 32767\n", `&`, got) failed = true } if got := and_32767_int16_ssa(0); got != 0 { fmt.Printf("and_int16 32767%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int16_32767_ssa(0); got != 0 { fmt.Printf("and_int16 0%s32767 = %d, wanted 0\n", `&`, got) failed = true } if got := and_32767_int16_ssa(1); got != 1 { fmt.Printf("and_int16 32767%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int16_32767_ssa(1); got != 1 { fmt.Printf("and_int16 1%s32767 = %d, wanted 1\n", `&`, got) failed = true } if got := and_32767_int16_ssa(32766); got != 32766 { fmt.Printf("and_int16 32767%s32766 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_int16_32767_ssa(32766); got != 32766 { fmt.Printf("and_int16 32766%s32767 = %d, wanted 32766\n", `&`, got) failed = true } if got := and_32767_int16_ssa(32767); got != 32767 { fmt.Printf("and_int16 32767%s32767 = %d, wanted 32767\n", `&`, got) failed = true } if got := and_int16_32767_ssa(32767); got != 32767 { fmt.Printf("and_int16 32767%s32767 = %d, wanted 32767\n", `&`, got) failed = true } if got := or_Neg32768_int16_ssa(-32768); got != -32768 { fmt.Printf("or_int16 -32768%s-32768 = %d, wanted -32768\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(-32768); got != -32768 { fmt.Printf("or_int16 -32768%s-32768 = %d, wanted -32768\n", `|`, got) failed = true } if got := or_Neg32768_int16_ssa(-32767); got != -32767 { fmt.Printf("or_int16 -32768%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(-32767); got != -32767 { fmt.Printf("or_int16 -32767%s-32768 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_Neg32768_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 -32768%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s-32768 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg32768_int16_ssa(0); got != -32768 { fmt.Printf("or_int16 -32768%s0 = %d, wanted -32768\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(0); got != -32768 { fmt.Printf("or_int16 0%s-32768 = %d, wanted -32768\n", `|`, got) failed = true } if got := or_Neg32768_int16_ssa(1); got != -32767 { fmt.Printf("or_int16 -32768%s1 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(1); got != -32767 { fmt.Printf("or_int16 1%s-32768 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_Neg32768_int16_ssa(32766); got != -2 { fmt.Printf("or_int16 -32768%s32766 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(32766); got != -2 { fmt.Printf("or_int16 32766%s-32768 = %d, wanted -2\n", `|`, got) failed = true } if got := or_Neg32768_int16_ssa(32767); got != -1 { fmt.Printf("or_int16 -32768%s32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg32768_ssa(32767); got != -1 { fmt.Printf("or_int16 32767%s-32768 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(-32768); got != -32767 { fmt.Printf("or_int16 -32767%s-32768 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(-32768); got != -32767 { fmt.Printf("or_int16 -32768%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(-32767); got != -32767 { fmt.Printf("or_int16 -32767%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(-32767); got != -32767 { fmt.Printf("or_int16 -32767%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 -32767%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s-32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(0); got != -32767 { fmt.Printf("or_int16 -32767%s0 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(0); got != -32767 { fmt.Printf("or_int16 0%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(1); got != -32767 { fmt.Printf("or_int16 -32767%s1 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(1); got != -32767 { fmt.Printf("or_int16 1%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(32766); got != -1 { fmt.Printf("or_int16 -32767%s32766 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(32766); got != -1 { fmt.Printf("or_int16 32766%s-32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg32767_int16_ssa(32767); got != -1 { fmt.Printf("or_int16 -32767%s32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg32767_ssa(32767); got != -1 { fmt.Printf("or_int16 32767%s-32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(-32768); got != -1 { fmt.Printf("or_int16 -1%s-32768 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(-32768); got != -1 { fmt.Printf("or_int16 -32768%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(-32767); got != -1 { fmt.Printf("or_int16 -1%s-32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(-32767); got != -1 { fmt.Printf("or_int16 -32767%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(0); got != -1 { fmt.Printf("or_int16 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(0); got != -1 { fmt.Printf("or_int16 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(1); got != -1 { fmt.Printf("or_int16 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(1); got != -1 { fmt.Printf("or_int16 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(32766); got != -1 { fmt.Printf("or_int16 -1%s32766 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(32766); got != -1 { fmt.Printf("or_int16 32766%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int16_ssa(32767); got != -1 { fmt.Printf("or_int16 -1%s32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_Neg1_ssa(32767); got != -1 { fmt.Printf("or_int16 32767%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int16_ssa(-32768); got != -32768 { fmt.Printf("or_int16 0%s-32768 = %d, wanted -32768\n", `|`, got) failed = true } if got := or_int16_0_ssa(-32768); got != -32768 { fmt.Printf("or_int16 -32768%s0 = %d, wanted -32768\n", `|`, got) failed = true } if got := or_0_int16_ssa(-32767); got != -32767 { fmt.Printf("or_int16 0%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_0_ssa(-32767); got != -32767 { fmt.Printf("or_int16 -32767%s0 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_0_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_0_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int16_ssa(0); got != 0 { fmt.Printf("or_int16 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_int16_0_ssa(0); got != 0 { fmt.Printf("or_int16 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_int16_ssa(1); got != 1 { fmt.Printf("or_int16 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int16_0_ssa(1); got != 1 { fmt.Printf("or_int16 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_int16_ssa(32766); got != 32766 { fmt.Printf("or_int16 0%s32766 = %d, wanted 32766\n", `|`, got) failed = true } if got := or_int16_0_ssa(32766); got != 32766 { fmt.Printf("or_int16 32766%s0 = %d, wanted 32766\n", `|`, got) failed = true } if got := or_0_int16_ssa(32767); got != 32767 { fmt.Printf("or_int16 0%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_0_ssa(32767); got != 32767 { fmt.Printf("or_int16 32767%s0 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_1_int16_ssa(-32768); got != -32767 { fmt.Printf("or_int16 1%s-32768 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_1_ssa(-32768); got != -32767 { fmt.Printf("or_int16 -32768%s1 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_1_int16_ssa(-32767); got != -32767 { fmt.Printf("or_int16 1%s-32767 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_int16_1_ssa(-32767); got != -32767 { fmt.Printf("or_int16 -32767%s1 = %d, wanted -32767\n", `|`, got) failed = true } if got := or_1_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_1_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_1_int16_ssa(0); got != 1 { fmt.Printf("or_int16 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int16_1_ssa(0); got != 1 { fmt.Printf("or_int16 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int16_ssa(1); got != 1 { fmt.Printf("or_int16 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int16_1_ssa(1); got != 1 { fmt.Printf("or_int16 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int16_ssa(32766); got != 32767 { fmt.Printf("or_int16 1%s32766 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_1_ssa(32766); got != 32767 { fmt.Printf("or_int16 32766%s1 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_1_int16_ssa(32767); got != 32767 { fmt.Printf("or_int16 1%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_1_ssa(32767); got != 32767 { fmt.Printf("or_int16 32767%s1 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_32766_int16_ssa(-32768); got != -2 { fmt.Printf("or_int16 32766%s-32768 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int16_32766_ssa(-32768); got != -2 { fmt.Printf("or_int16 -32768%s32766 = %d, wanted -2\n", `|`, got) failed = true } if got := or_32766_int16_ssa(-32767); got != -1 { fmt.Printf("or_int16 32766%s-32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_32766_ssa(-32767); got != -1 { fmt.Printf("or_int16 -32767%s32766 = %d, wanted -1\n", `|`, got) failed = true } if got := or_32766_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 32766%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_32766_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s32766 = %d, wanted -1\n", `|`, got) failed = true } if got := or_32766_int16_ssa(0); got != 32766 { fmt.Printf("or_int16 32766%s0 = %d, wanted 32766\n", `|`, got) failed = true } if got := or_int16_32766_ssa(0); got != 32766 { fmt.Printf("or_int16 0%s32766 = %d, wanted 32766\n", `|`, got) failed = true } if got := or_32766_int16_ssa(1); got != 32767 { fmt.Printf("or_int16 32766%s1 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_32766_ssa(1); got != 32767 { fmt.Printf("or_int16 1%s32766 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_32766_int16_ssa(32766); got != 32766 { fmt.Printf("or_int16 32766%s32766 = %d, wanted 32766\n", `|`, got) failed = true } if got := or_int16_32766_ssa(32766); got != 32766 { fmt.Printf("or_int16 32766%s32766 = %d, wanted 32766\n", `|`, got) failed = true } if got := or_32766_int16_ssa(32767); got != 32767 { fmt.Printf("or_int16 32766%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_32766_ssa(32767); got != 32767 { fmt.Printf("or_int16 32767%s32766 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_32767_int16_ssa(-32768); got != -1 { fmt.Printf("or_int16 32767%s-32768 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_32767_ssa(-32768); got != -1 { fmt.Printf("or_int16 -32768%s32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_32767_int16_ssa(-32767); got != -1 { fmt.Printf("or_int16 32767%s-32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_32767_ssa(-32767); got != -1 { fmt.Printf("or_int16 -32767%s32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_32767_int16_ssa(-1); got != -1 { fmt.Printf("or_int16 32767%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int16_32767_ssa(-1); got != -1 { fmt.Printf("or_int16 -1%s32767 = %d, wanted -1\n", `|`, got) failed = true } if got := or_32767_int16_ssa(0); got != 32767 { fmt.Printf("or_int16 32767%s0 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_32767_ssa(0); got != 32767 { fmt.Printf("or_int16 0%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_32767_int16_ssa(1); got != 32767 { fmt.Printf("or_int16 32767%s1 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_32767_ssa(1); got != 32767 { fmt.Printf("or_int16 1%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_32767_int16_ssa(32766); got != 32767 { fmt.Printf("or_int16 32767%s32766 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_32767_ssa(32766); got != 32767 { fmt.Printf("or_int16 32766%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_32767_int16_ssa(32767); got != 32767 { fmt.Printf("or_int16 32767%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := or_int16_32767_ssa(32767); got != 32767 { fmt.Printf("or_int16 32767%s32767 = %d, wanted 32767\n", `|`, got) failed = true } if got := xor_Neg32768_int16_ssa(-32768); got != 0 { fmt.Printf("xor_int16 -32768%s-32768 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(-32768); got != 0 { fmt.Printf("xor_int16 -32768%s-32768 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg32768_int16_ssa(-32767); got != 1 { fmt.Printf("xor_int16 -32768%s-32767 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(-32767); got != 1 { fmt.Printf("xor_int16 -32767%s-32768 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg32768_int16_ssa(-1); got != 32767 { fmt.Printf("xor_int16 -32768%s-1 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(-1); got != 32767 { fmt.Printf("xor_int16 -1%s-32768 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_Neg32768_int16_ssa(0); got != -32768 { fmt.Printf("xor_int16 -32768%s0 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(0); got != -32768 { fmt.Printf("xor_int16 0%s-32768 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_Neg32768_int16_ssa(1); got != -32767 { fmt.Printf("xor_int16 -32768%s1 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(1); got != -32767 { fmt.Printf("xor_int16 1%s-32768 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_Neg32768_int16_ssa(32766); got != -2 { fmt.Printf("xor_int16 -32768%s32766 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(32766); got != -2 { fmt.Printf("xor_int16 32766%s-32768 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg32768_int16_ssa(32767); got != -1 { fmt.Printf("xor_int16 -32768%s32767 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int16_Neg32768_ssa(32767); got != -1 { fmt.Printf("xor_int16 32767%s-32768 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(-32768); got != 1 { fmt.Printf("xor_int16 -32767%s-32768 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(-32768); got != 1 { fmt.Printf("xor_int16 -32768%s-32767 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(-32767); got != 0 { fmt.Printf("xor_int16 -32767%s-32767 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(-32767); got != 0 { fmt.Printf("xor_int16 -32767%s-32767 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(-1); got != 32766 { fmt.Printf("xor_int16 -32767%s-1 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(-1); got != 32766 { fmt.Printf("xor_int16 -1%s-32767 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(0); got != -32767 { fmt.Printf("xor_int16 -32767%s0 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(0); got != -32767 { fmt.Printf("xor_int16 0%s-32767 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(1); got != -32768 { fmt.Printf("xor_int16 -32767%s1 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(1); got != -32768 { fmt.Printf("xor_int16 1%s-32767 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(32766); got != -1 { fmt.Printf("xor_int16 -32767%s32766 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(32766); got != -1 { fmt.Printf("xor_int16 32766%s-32767 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg32767_int16_ssa(32767); got != -2 { fmt.Printf("xor_int16 -32767%s32767 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int16_Neg32767_ssa(32767); got != -2 { fmt.Printf("xor_int16 32767%s-32767 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(-32768); got != 32767 { fmt.Printf("xor_int16 -1%s-32768 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(-32768); got != 32767 { fmt.Printf("xor_int16 -32768%s-1 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(-32767); got != 32766 { fmt.Printf("xor_int16 -1%s-32767 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(-32767); got != 32766 { fmt.Printf("xor_int16 -32767%s-1 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(-1); got != 0 { fmt.Printf("xor_int16 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(-1); got != 0 { fmt.Printf("xor_int16 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(0); got != -1 { fmt.Printf("xor_int16 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(0); got != -1 { fmt.Printf("xor_int16 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(1); got != -2 { fmt.Printf("xor_int16 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(1); got != -2 { fmt.Printf("xor_int16 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(32766); got != -32767 { fmt.Printf("xor_int16 -1%s32766 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(32766); got != -32767 { fmt.Printf("xor_int16 32766%s-1 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_Neg1_int16_ssa(32767); got != -32768 { fmt.Printf("xor_int16 -1%s32767 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_int16_Neg1_ssa(32767); got != -32768 { fmt.Printf("xor_int16 32767%s-1 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_0_int16_ssa(-32768); got != -32768 { fmt.Printf("xor_int16 0%s-32768 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_int16_0_ssa(-32768); got != -32768 { fmt.Printf("xor_int16 -32768%s0 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_0_int16_ssa(-32767); got != -32767 { fmt.Printf("xor_int16 0%s-32767 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_int16_0_ssa(-32767); got != -32767 { fmt.Printf("xor_int16 -32767%s0 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_0_int16_ssa(-1); got != -1 { fmt.Printf("xor_int16 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int16_0_ssa(-1); got != -1 { fmt.Printf("xor_int16 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_0_int16_ssa(0); got != 0 { fmt.Printf("xor_int16 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_0_ssa(0); got != 0 { fmt.Printf("xor_int16 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_int16_ssa(1); got != 1 { fmt.Printf("xor_int16 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int16_0_ssa(1); got != 1 { fmt.Printf("xor_int16 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_int16_ssa(32766); got != 32766 { fmt.Printf("xor_int16 0%s32766 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_int16_0_ssa(32766); got != 32766 { fmt.Printf("xor_int16 32766%s0 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_0_int16_ssa(32767); got != 32767 { fmt.Printf("xor_int16 0%s32767 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_int16_0_ssa(32767); got != 32767 { fmt.Printf("xor_int16 32767%s0 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_1_int16_ssa(-32768); got != -32767 { fmt.Printf("xor_int16 1%s-32768 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_int16_1_ssa(-32768); got != -32767 { fmt.Printf("xor_int16 -32768%s1 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_1_int16_ssa(-32767); got != -32768 { fmt.Printf("xor_int16 1%s-32767 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_int16_1_ssa(-32767); got != -32768 { fmt.Printf("xor_int16 -32767%s1 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_1_int16_ssa(-1); got != -2 { fmt.Printf("xor_int16 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int16_1_ssa(-1); got != -2 { fmt.Printf("xor_int16 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_1_int16_ssa(0); got != 1 { fmt.Printf("xor_int16 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int16_1_ssa(0); got != 1 { fmt.Printf("xor_int16 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_int16_ssa(1); got != 0 { fmt.Printf("xor_int16 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_1_ssa(1); got != 0 { fmt.Printf("xor_int16 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_int16_ssa(32766); got != 32767 { fmt.Printf("xor_int16 1%s32766 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_int16_1_ssa(32766); got != 32767 { fmt.Printf("xor_int16 32766%s1 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_1_int16_ssa(32767); got != 32766 { fmt.Printf("xor_int16 1%s32767 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_int16_1_ssa(32767); got != 32766 { fmt.Printf("xor_int16 32767%s1 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(-32768); got != -2 { fmt.Printf("xor_int16 32766%s-32768 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(-32768); got != -2 { fmt.Printf("xor_int16 -32768%s32766 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(-32767); got != -1 { fmt.Printf("xor_int16 32766%s-32767 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(-32767); got != -1 { fmt.Printf("xor_int16 -32767%s32766 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(-1); got != -32767 { fmt.Printf("xor_int16 32766%s-1 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(-1); got != -32767 { fmt.Printf("xor_int16 -1%s32766 = %d, wanted -32767\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(0); got != 32766 { fmt.Printf("xor_int16 32766%s0 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(0); got != 32766 { fmt.Printf("xor_int16 0%s32766 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(1); got != 32767 { fmt.Printf("xor_int16 32766%s1 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(1); got != 32767 { fmt.Printf("xor_int16 1%s32766 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(32766); got != 0 { fmt.Printf("xor_int16 32766%s32766 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(32766); got != 0 { fmt.Printf("xor_int16 32766%s32766 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_32766_int16_ssa(32767); got != 1 { fmt.Printf("xor_int16 32766%s32767 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int16_32766_ssa(32767); got != 1 { fmt.Printf("xor_int16 32767%s32766 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(-32768); got != -1 { fmt.Printf("xor_int16 32767%s-32768 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(-32768); got != -1 { fmt.Printf("xor_int16 -32768%s32767 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(-32767); got != -2 { fmt.Printf("xor_int16 32767%s-32767 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(-32767); got != -2 { fmt.Printf("xor_int16 -32767%s32767 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(-1); got != -32768 { fmt.Printf("xor_int16 32767%s-1 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(-1); got != -32768 { fmt.Printf("xor_int16 -1%s32767 = %d, wanted -32768\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(0); got != 32767 { fmt.Printf("xor_int16 32767%s0 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(0); got != 32767 { fmt.Printf("xor_int16 0%s32767 = %d, wanted 32767\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(1); got != 32766 { fmt.Printf("xor_int16 32767%s1 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(1); got != 32766 { fmt.Printf("xor_int16 1%s32767 = %d, wanted 32766\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(32766); got != 1 { fmt.Printf("xor_int16 32767%s32766 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(32766); got != 1 { fmt.Printf("xor_int16 32766%s32767 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_32767_int16_ssa(32767); got != 0 { fmt.Printf("xor_int16 32767%s32767 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int16_32767_ssa(32767); got != 0 { fmt.Printf("xor_int16 32767%s32767 = %d, wanted 0\n", `^`, got) failed = true } if got := add_0_uint8_ssa(0); got != 0 { fmt.Printf("add_uint8 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint8_0_ssa(0); got != 0 { fmt.Printf("add_uint8 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_uint8_ssa(1); got != 1 { fmt.Printf("add_uint8 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint8_0_ssa(1); got != 1 { fmt.Printf("add_uint8 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_uint8_ssa(255); got != 255 { fmt.Printf("add_uint8 0%s255 = %d, wanted 255\n", `+`, got) failed = true } if got := add_uint8_0_ssa(255); got != 255 { fmt.Printf("add_uint8 255%s0 = %d, wanted 255\n", `+`, got) failed = true } if got := add_1_uint8_ssa(0); got != 1 { fmt.Printf("add_uint8 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_uint8_1_ssa(0); got != 1 { fmt.Printf("add_uint8 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_uint8_ssa(1); got != 2 { fmt.Printf("add_uint8 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_uint8_1_ssa(1); got != 2 { fmt.Printf("add_uint8 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_uint8_ssa(255); got != 0 { fmt.Printf("add_uint8 1%s255 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint8_1_ssa(255); got != 0 { fmt.Printf("add_uint8 255%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_255_uint8_ssa(0); got != 255 { fmt.Printf("add_uint8 255%s0 = %d, wanted 255\n", `+`, got) failed = true } if got := add_uint8_255_ssa(0); got != 255 { fmt.Printf("add_uint8 0%s255 = %d, wanted 255\n", `+`, got) failed = true } if got := add_255_uint8_ssa(1); got != 0 { fmt.Printf("add_uint8 255%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_uint8_255_ssa(1); got != 0 { fmt.Printf("add_uint8 1%s255 = %d, wanted 0\n", `+`, got) failed = true } if got := add_255_uint8_ssa(255); got != 254 { fmt.Printf("add_uint8 255%s255 = %d, wanted 254\n", `+`, got) failed = true } if got := add_uint8_255_ssa(255); got != 254 { fmt.Printf("add_uint8 255%s255 = %d, wanted 254\n", `+`, got) failed = true } if got := sub_0_uint8_ssa(0); got != 0 { fmt.Printf("sub_uint8 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint8_0_ssa(0); got != 0 { fmt.Printf("sub_uint8 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_uint8_ssa(1); got != 255 { fmt.Printf("sub_uint8 0%s1 = %d, wanted 255\n", `-`, got) failed = true } if got := sub_uint8_0_ssa(1); got != 1 { fmt.Printf("sub_uint8 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_uint8_ssa(255); got != 1 { fmt.Printf("sub_uint8 0%s255 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint8_0_ssa(255); got != 255 { fmt.Printf("sub_uint8 255%s0 = %d, wanted 255\n", `-`, got) failed = true } if got := sub_1_uint8_ssa(0); got != 1 { fmt.Printf("sub_uint8 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_uint8_1_ssa(0); got != 255 { fmt.Printf("sub_uint8 0%s1 = %d, wanted 255\n", `-`, got) failed = true } if got := sub_1_uint8_ssa(1); got != 0 { fmt.Printf("sub_uint8 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint8_1_ssa(1); got != 0 { fmt.Printf("sub_uint8 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_uint8_ssa(255); got != 2 { fmt.Printf("sub_uint8 1%s255 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_uint8_1_ssa(255); got != 254 { fmt.Printf("sub_uint8 255%s1 = %d, wanted 254\n", `-`, got) failed = true } if got := sub_255_uint8_ssa(0); got != 255 { fmt.Printf("sub_uint8 255%s0 = %d, wanted 255\n", `-`, got) failed = true } if got := sub_uint8_255_ssa(0); got != 1 { fmt.Printf("sub_uint8 0%s255 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_255_uint8_ssa(1); got != 254 { fmt.Printf("sub_uint8 255%s1 = %d, wanted 254\n", `-`, got) failed = true } if got := sub_uint8_255_ssa(1); got != 2 { fmt.Printf("sub_uint8 1%s255 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_255_uint8_ssa(255); got != 0 { fmt.Printf("sub_uint8 255%s255 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_uint8_255_ssa(255); got != 0 { fmt.Printf("sub_uint8 255%s255 = %d, wanted 0\n", `-`, got) failed = true } if got := div_0_uint8_ssa(1); got != 0 { fmt.Printf("div_uint8 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_uint8_ssa(255); got != 0 { fmt.Printf("div_uint8 0%s255 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint8_1_ssa(0); got != 0 { fmt.Printf("div_uint8 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_uint8_ssa(1); got != 1 { fmt.Printf("div_uint8 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint8_1_ssa(1); got != 1 { fmt.Printf("div_uint8 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_uint8_ssa(255); got != 0 { fmt.Printf("div_uint8 1%s255 = %d, wanted 0\n", `/`, got) failed = true } if got := div_uint8_1_ssa(255); got != 255 { fmt.Printf("div_uint8 255%s1 = %d, wanted 255\n", `/`, got) failed = true } if got := div_uint8_255_ssa(0); got != 0 { fmt.Printf("div_uint8 0%s255 = %d, wanted 0\n", `/`, got) failed = true } if got := div_255_uint8_ssa(1); got != 255 { fmt.Printf("div_uint8 255%s1 = %d, wanted 255\n", `/`, got) failed = true } if got := div_uint8_255_ssa(1); got != 0 { fmt.Printf("div_uint8 1%s255 = %d, wanted 0\n", `/`, got) failed = true } if got := div_255_uint8_ssa(255); got != 1 { fmt.Printf("div_uint8 255%s255 = %d, wanted 1\n", `/`, got) failed = true } if got := div_uint8_255_ssa(255); got != 1 { fmt.Printf("div_uint8 255%s255 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_0_uint8_ssa(0); got != 0 { fmt.Printf("mul_uint8 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint8_0_ssa(0); got != 0 { fmt.Printf("mul_uint8 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint8_ssa(1); got != 0 { fmt.Printf("mul_uint8 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint8_0_ssa(1); got != 0 { fmt.Printf("mul_uint8 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_uint8_ssa(255); got != 0 { fmt.Printf("mul_uint8 0%s255 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint8_0_ssa(255); got != 0 { fmt.Printf("mul_uint8 255%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint8_ssa(0); got != 0 { fmt.Printf("mul_uint8 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint8_1_ssa(0); got != 0 { fmt.Printf("mul_uint8 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_uint8_ssa(1); got != 1 { fmt.Printf("mul_uint8 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint8_1_ssa(1); got != 1 { fmt.Printf("mul_uint8 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_uint8_ssa(255); got != 255 { fmt.Printf("mul_uint8 1%s255 = %d, wanted 255\n", `*`, got) failed = true } if got := mul_uint8_1_ssa(255); got != 255 { fmt.Printf("mul_uint8 255%s1 = %d, wanted 255\n", `*`, got) failed = true } if got := mul_255_uint8_ssa(0); got != 0 { fmt.Printf("mul_uint8 255%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_uint8_255_ssa(0); got != 0 { fmt.Printf("mul_uint8 0%s255 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_255_uint8_ssa(1); got != 255 { fmt.Printf("mul_uint8 255%s1 = %d, wanted 255\n", `*`, got) failed = true } if got := mul_uint8_255_ssa(1); got != 255 { fmt.Printf("mul_uint8 1%s255 = %d, wanted 255\n", `*`, got) failed = true } if got := mul_255_uint8_ssa(255); got != 1 { fmt.Printf("mul_uint8 255%s255 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_uint8_255_ssa(255); got != 1 { fmt.Printf("mul_uint8 255%s255 = %d, wanted 1\n", `*`, got) failed = true } if got := lsh_0_uint8_ssa(0); got != 0 { fmt.Printf("lsh_uint8 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint8_0_ssa(0); got != 0 { fmt.Printf("lsh_uint8 0%s0 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_0_uint8_ssa(1); got != 0 { fmt.Printf("lsh_uint8 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint8_0_ssa(1); got != 1 { fmt.Printf("lsh_uint8 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_0_uint8_ssa(255); got != 0 { fmt.Printf("lsh_uint8 0%s255 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint8_0_ssa(255); got != 255 { fmt.Printf("lsh_uint8 255%s0 = %d, wanted 255\n", `<<`, got) failed = true } if got := lsh_1_uint8_ssa(0); got != 1 { fmt.Printf("lsh_uint8 1%s0 = %d, wanted 1\n", `<<`, got) failed = true } if got := lsh_uint8_1_ssa(0); got != 0 { fmt.Printf("lsh_uint8 0%s1 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_1_uint8_ssa(1); got != 2 { fmt.Printf("lsh_uint8 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_uint8_1_ssa(1); got != 2 { fmt.Printf("lsh_uint8 1%s1 = %d, wanted 2\n", `<<`, got) failed = true } if got := lsh_1_uint8_ssa(255); got != 0 { fmt.Printf("lsh_uint8 1%s255 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint8_1_ssa(255); got != 254 { fmt.Printf("lsh_uint8 255%s1 = %d, wanted 254\n", `<<`, got) failed = true } if got := lsh_255_uint8_ssa(0); got != 255 { fmt.Printf("lsh_uint8 255%s0 = %d, wanted 255\n", `<<`, got) failed = true } if got := lsh_uint8_255_ssa(0); got != 0 { fmt.Printf("lsh_uint8 0%s255 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_255_uint8_ssa(1); got != 254 { fmt.Printf("lsh_uint8 255%s1 = %d, wanted 254\n", `<<`, got) failed = true } if got := lsh_uint8_255_ssa(1); got != 0 { fmt.Printf("lsh_uint8 1%s255 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_255_uint8_ssa(255); got != 0 { fmt.Printf("lsh_uint8 255%s255 = %d, wanted 0\n", `<<`, got) failed = true } if got := lsh_uint8_255_ssa(255); got != 0 { fmt.Printf("lsh_uint8 255%s255 = %d, wanted 0\n", `<<`, got) failed = true } if got := rsh_0_uint8_ssa(0); got != 0 { fmt.Printf("rsh_uint8 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint8_0_ssa(0); got != 0 { fmt.Printf("rsh_uint8 0%s0 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_0_uint8_ssa(1); got != 0 { fmt.Printf("rsh_uint8 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint8_0_ssa(1); got != 1 { fmt.Printf("rsh_uint8 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_0_uint8_ssa(255); got != 0 { fmt.Printf("rsh_uint8 0%s255 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint8_0_ssa(255); got != 255 { fmt.Printf("rsh_uint8 255%s0 = %d, wanted 255\n", `>>`, got) failed = true } if got := rsh_1_uint8_ssa(0); got != 1 { fmt.Printf("rsh_uint8 1%s0 = %d, wanted 1\n", `>>`, got) failed = true } if got := rsh_uint8_1_ssa(0); got != 0 { fmt.Printf("rsh_uint8 0%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint8_ssa(1); got != 0 { fmt.Printf("rsh_uint8 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint8_1_ssa(1); got != 0 { fmt.Printf("rsh_uint8 1%s1 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_1_uint8_ssa(255); got != 0 { fmt.Printf("rsh_uint8 1%s255 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint8_1_ssa(255); got != 127 { fmt.Printf("rsh_uint8 255%s1 = %d, wanted 127\n", `>>`, got) failed = true } if got := rsh_255_uint8_ssa(0); got != 255 { fmt.Printf("rsh_uint8 255%s0 = %d, wanted 255\n", `>>`, got) failed = true } if got := rsh_uint8_255_ssa(0); got != 0 { fmt.Printf("rsh_uint8 0%s255 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_255_uint8_ssa(1); got != 127 { fmt.Printf("rsh_uint8 255%s1 = %d, wanted 127\n", `>>`, got) failed = true } if got := rsh_uint8_255_ssa(1); got != 0 { fmt.Printf("rsh_uint8 1%s255 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_255_uint8_ssa(255); got != 0 { fmt.Printf("rsh_uint8 255%s255 = %d, wanted 0\n", `>>`, got) failed = true } if got := rsh_uint8_255_ssa(255); got != 0 { fmt.Printf("rsh_uint8 255%s255 = %d, wanted 0\n", `>>`, got) failed = true } if got := mod_0_uint8_ssa(1); got != 0 { fmt.Printf("mod_uint8 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_uint8_ssa(255); got != 0 { fmt.Printf("mod_uint8 0%s255 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint8_1_ssa(0); got != 0 { fmt.Printf("mod_uint8 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint8_ssa(1); got != 0 { fmt.Printf("mod_uint8 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint8_1_ssa(1); got != 0 { fmt.Printf("mod_uint8 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_uint8_ssa(255); got != 1 { fmt.Printf("mod_uint8 1%s255 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_uint8_1_ssa(255); got != 0 { fmt.Printf("mod_uint8 255%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint8_255_ssa(0); got != 0 { fmt.Printf("mod_uint8 0%s255 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_255_uint8_ssa(1); got != 0 { fmt.Printf("mod_uint8 255%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint8_255_ssa(1); got != 1 { fmt.Printf("mod_uint8 1%s255 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_255_uint8_ssa(255); got != 0 { fmt.Printf("mod_uint8 255%s255 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_uint8_255_ssa(255); got != 0 { fmt.Printf("mod_uint8 255%s255 = %d, wanted 0\n", `%`, got) failed = true } if got := and_0_uint8_ssa(0); got != 0 { fmt.Printf("and_uint8 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint8_0_ssa(0); got != 0 { fmt.Printf("and_uint8 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint8_ssa(1); got != 0 { fmt.Printf("and_uint8 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint8_0_ssa(1); got != 0 { fmt.Printf("and_uint8 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_uint8_ssa(255); got != 0 { fmt.Printf("and_uint8 0%s255 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint8_0_ssa(255); got != 0 { fmt.Printf("and_uint8 255%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint8_ssa(0); got != 0 { fmt.Printf("and_uint8 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint8_1_ssa(0); got != 0 { fmt.Printf("and_uint8 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_uint8_ssa(1); got != 1 { fmt.Printf("and_uint8 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint8_1_ssa(1); got != 1 { fmt.Printf("and_uint8 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_uint8_ssa(255); got != 1 { fmt.Printf("and_uint8 1%s255 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint8_1_ssa(255); got != 1 { fmt.Printf("and_uint8 255%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_255_uint8_ssa(0); got != 0 { fmt.Printf("and_uint8 255%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_uint8_255_ssa(0); got != 0 { fmt.Printf("and_uint8 0%s255 = %d, wanted 0\n", `&`, got) failed = true } if got := and_255_uint8_ssa(1); got != 1 { fmt.Printf("and_uint8 255%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_uint8_255_ssa(1); got != 1 { fmt.Printf("and_uint8 1%s255 = %d, wanted 1\n", `&`, got) failed = true } if got := and_255_uint8_ssa(255); got != 255 { fmt.Printf("and_uint8 255%s255 = %d, wanted 255\n", `&`, got) failed = true } if got := and_uint8_255_ssa(255); got != 255 { fmt.Printf("and_uint8 255%s255 = %d, wanted 255\n", `&`, got) failed = true } if got := or_0_uint8_ssa(0); got != 0 { fmt.Printf("or_uint8 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_uint8_0_ssa(0); got != 0 { fmt.Printf("or_uint8 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_uint8_ssa(1); got != 1 { fmt.Printf("or_uint8 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint8_0_ssa(1); got != 1 { fmt.Printf("or_uint8 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_uint8_ssa(255); got != 255 { fmt.Printf("or_uint8 0%s255 = %d, wanted 255\n", `|`, got) failed = true } if got := or_uint8_0_ssa(255); got != 255 { fmt.Printf("or_uint8 255%s0 = %d, wanted 255\n", `|`, got) failed = true } if got := or_1_uint8_ssa(0); got != 1 { fmt.Printf("or_uint8 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint8_1_ssa(0); got != 1 { fmt.Printf("or_uint8 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint8_ssa(1); got != 1 { fmt.Printf("or_uint8 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_uint8_1_ssa(1); got != 1 { fmt.Printf("or_uint8 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_uint8_ssa(255); got != 255 { fmt.Printf("or_uint8 1%s255 = %d, wanted 255\n", `|`, got) failed = true } if got := or_uint8_1_ssa(255); got != 255 { fmt.Printf("or_uint8 255%s1 = %d, wanted 255\n", `|`, got) failed = true } if got := or_255_uint8_ssa(0); got != 255 { fmt.Printf("or_uint8 255%s0 = %d, wanted 255\n", `|`, got) failed = true } if got := or_uint8_255_ssa(0); got != 255 { fmt.Printf("or_uint8 0%s255 = %d, wanted 255\n", `|`, got) failed = true } if got := or_255_uint8_ssa(1); got != 255 { fmt.Printf("or_uint8 255%s1 = %d, wanted 255\n", `|`, got) failed = true } if got := or_uint8_255_ssa(1); got != 255 { fmt.Printf("or_uint8 1%s255 = %d, wanted 255\n", `|`, got) failed = true } if got := or_255_uint8_ssa(255); got != 255 { fmt.Printf("or_uint8 255%s255 = %d, wanted 255\n", `|`, got) failed = true } if got := or_uint8_255_ssa(255); got != 255 { fmt.Printf("or_uint8 255%s255 = %d, wanted 255\n", `|`, got) failed = true } if got := xor_0_uint8_ssa(0); got != 0 { fmt.Printf("xor_uint8 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint8_0_ssa(0); got != 0 { fmt.Printf("xor_uint8 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_uint8_ssa(1); got != 1 { fmt.Printf("xor_uint8 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint8_0_ssa(1); got != 1 { fmt.Printf("xor_uint8 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_uint8_ssa(255); got != 255 { fmt.Printf("xor_uint8 0%s255 = %d, wanted 255\n", `^`, got) failed = true } if got := xor_uint8_0_ssa(255); got != 255 { fmt.Printf("xor_uint8 255%s0 = %d, wanted 255\n", `^`, got) failed = true } if got := xor_1_uint8_ssa(0); got != 1 { fmt.Printf("xor_uint8 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_uint8_1_ssa(0); got != 1 { fmt.Printf("xor_uint8 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_uint8_ssa(1); got != 0 { fmt.Printf("xor_uint8 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint8_1_ssa(1); got != 0 { fmt.Printf("xor_uint8 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_uint8_ssa(255); got != 254 { fmt.Printf("xor_uint8 1%s255 = %d, wanted 254\n", `^`, got) failed = true } if got := xor_uint8_1_ssa(255); got != 254 { fmt.Printf("xor_uint8 255%s1 = %d, wanted 254\n", `^`, got) failed = true } if got := xor_255_uint8_ssa(0); got != 255 { fmt.Printf("xor_uint8 255%s0 = %d, wanted 255\n", `^`, got) failed = true } if got := xor_uint8_255_ssa(0); got != 255 { fmt.Printf("xor_uint8 0%s255 = %d, wanted 255\n", `^`, got) failed = true } if got := xor_255_uint8_ssa(1); got != 254 { fmt.Printf("xor_uint8 255%s1 = %d, wanted 254\n", `^`, got) failed = true } if got := xor_uint8_255_ssa(1); got != 254 { fmt.Printf("xor_uint8 1%s255 = %d, wanted 254\n", `^`, got) failed = true } if got := xor_255_uint8_ssa(255); got != 0 { fmt.Printf("xor_uint8 255%s255 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_uint8_255_ssa(255); got != 0 { fmt.Printf("xor_uint8 255%s255 = %d, wanted 0\n", `^`, got) failed = true } if got := add_Neg128_int8_ssa(-128); got != 0 { fmt.Printf("add_int8 -128%s-128 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(-128); got != 0 { fmt.Printf("add_int8 -128%s-128 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg128_int8_ssa(-127); got != 1 { fmt.Printf("add_int8 -128%s-127 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(-127); got != 1 { fmt.Printf("add_int8 -127%s-128 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg128_int8_ssa(-1); got != 127 { fmt.Printf("add_int8 -128%s-1 = %d, wanted 127\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(-1); got != 127 { fmt.Printf("add_int8 -1%s-128 = %d, wanted 127\n", `+`, got) failed = true } if got := add_Neg128_int8_ssa(0); got != -128 { fmt.Printf("add_int8 -128%s0 = %d, wanted -128\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(0); got != -128 { fmt.Printf("add_int8 0%s-128 = %d, wanted -128\n", `+`, got) failed = true } if got := add_Neg128_int8_ssa(1); got != -127 { fmt.Printf("add_int8 -128%s1 = %d, wanted -127\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(1); got != -127 { fmt.Printf("add_int8 1%s-128 = %d, wanted -127\n", `+`, got) failed = true } if got := add_Neg128_int8_ssa(126); got != -2 { fmt.Printf("add_int8 -128%s126 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(126); got != -2 { fmt.Printf("add_int8 126%s-128 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg128_int8_ssa(127); got != -1 { fmt.Printf("add_int8 -128%s127 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int8_Neg128_ssa(127); got != -1 { fmt.Printf("add_int8 127%s-128 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(-128); got != 1 { fmt.Printf("add_int8 -127%s-128 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(-128); got != 1 { fmt.Printf("add_int8 -128%s-127 = %d, wanted 1\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(-127); got != 2 { fmt.Printf("add_int8 -127%s-127 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(-127); got != 2 { fmt.Printf("add_int8 -127%s-127 = %d, wanted 2\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(-1); got != -128 { fmt.Printf("add_int8 -127%s-1 = %d, wanted -128\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(-1); got != -128 { fmt.Printf("add_int8 -1%s-127 = %d, wanted -128\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(0); got != -127 { fmt.Printf("add_int8 -127%s0 = %d, wanted -127\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(0); got != -127 { fmt.Printf("add_int8 0%s-127 = %d, wanted -127\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(1); got != -126 { fmt.Printf("add_int8 -127%s1 = %d, wanted -126\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(1); got != -126 { fmt.Printf("add_int8 1%s-127 = %d, wanted -126\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(126); got != -1 { fmt.Printf("add_int8 -127%s126 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(126); got != -1 { fmt.Printf("add_int8 126%s-127 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg127_int8_ssa(127); got != 0 { fmt.Printf("add_int8 -127%s127 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int8_Neg127_ssa(127); got != 0 { fmt.Printf("add_int8 127%s-127 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(-128); got != 127 { fmt.Printf("add_int8 -1%s-128 = %d, wanted 127\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(-128); got != 127 { fmt.Printf("add_int8 -128%s-1 = %d, wanted 127\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(-127); got != -128 { fmt.Printf("add_int8 -1%s-127 = %d, wanted -128\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(-127); got != -128 { fmt.Printf("add_int8 -127%s-1 = %d, wanted -128\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(-1); got != -2 { fmt.Printf("add_int8 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(-1); got != -2 { fmt.Printf("add_int8 -1%s-1 = %d, wanted -2\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(0); got != -1 { fmt.Printf("add_int8 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(0); got != -1 { fmt.Printf("add_int8 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(1); got != 0 { fmt.Printf("add_int8 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(1); got != 0 { fmt.Printf("add_int8 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(126); got != 125 { fmt.Printf("add_int8 -1%s126 = %d, wanted 125\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(126); got != 125 { fmt.Printf("add_int8 126%s-1 = %d, wanted 125\n", `+`, got) failed = true } if got := add_Neg1_int8_ssa(127); got != 126 { fmt.Printf("add_int8 -1%s127 = %d, wanted 126\n", `+`, got) failed = true } if got := add_int8_Neg1_ssa(127); got != 126 { fmt.Printf("add_int8 127%s-1 = %d, wanted 126\n", `+`, got) failed = true } if got := add_0_int8_ssa(-128); got != -128 { fmt.Printf("add_int8 0%s-128 = %d, wanted -128\n", `+`, got) failed = true } if got := add_int8_0_ssa(-128); got != -128 { fmt.Printf("add_int8 -128%s0 = %d, wanted -128\n", `+`, got) failed = true } if got := add_0_int8_ssa(-127); got != -127 { fmt.Printf("add_int8 0%s-127 = %d, wanted -127\n", `+`, got) failed = true } if got := add_int8_0_ssa(-127); got != -127 { fmt.Printf("add_int8 -127%s0 = %d, wanted -127\n", `+`, got) failed = true } if got := add_0_int8_ssa(-1); got != -1 { fmt.Printf("add_int8 0%s-1 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int8_0_ssa(-1); got != -1 { fmt.Printf("add_int8 -1%s0 = %d, wanted -1\n", `+`, got) failed = true } if got := add_0_int8_ssa(0); got != 0 { fmt.Printf("add_int8 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int8_0_ssa(0); got != 0 { fmt.Printf("add_int8 0%s0 = %d, wanted 0\n", `+`, got) failed = true } if got := add_0_int8_ssa(1); got != 1 { fmt.Printf("add_int8 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int8_0_ssa(1); got != 1 { fmt.Printf("add_int8 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_0_int8_ssa(126); got != 126 { fmt.Printf("add_int8 0%s126 = %d, wanted 126\n", `+`, got) failed = true } if got := add_int8_0_ssa(126); got != 126 { fmt.Printf("add_int8 126%s0 = %d, wanted 126\n", `+`, got) failed = true } if got := add_0_int8_ssa(127); got != 127 { fmt.Printf("add_int8 0%s127 = %d, wanted 127\n", `+`, got) failed = true } if got := add_int8_0_ssa(127); got != 127 { fmt.Printf("add_int8 127%s0 = %d, wanted 127\n", `+`, got) failed = true } if got := add_1_int8_ssa(-128); got != -127 { fmt.Printf("add_int8 1%s-128 = %d, wanted -127\n", `+`, got) failed = true } if got := add_int8_1_ssa(-128); got != -127 { fmt.Printf("add_int8 -128%s1 = %d, wanted -127\n", `+`, got) failed = true } if got := add_1_int8_ssa(-127); got != -126 { fmt.Printf("add_int8 1%s-127 = %d, wanted -126\n", `+`, got) failed = true } if got := add_int8_1_ssa(-127); got != -126 { fmt.Printf("add_int8 -127%s1 = %d, wanted -126\n", `+`, got) failed = true } if got := add_1_int8_ssa(-1); got != 0 { fmt.Printf("add_int8 1%s-1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int8_1_ssa(-1); got != 0 { fmt.Printf("add_int8 -1%s1 = %d, wanted 0\n", `+`, got) failed = true } if got := add_1_int8_ssa(0); got != 1 { fmt.Printf("add_int8 1%s0 = %d, wanted 1\n", `+`, got) failed = true } if got := add_int8_1_ssa(0); got != 1 { fmt.Printf("add_int8 0%s1 = %d, wanted 1\n", `+`, got) failed = true } if got := add_1_int8_ssa(1); got != 2 { fmt.Printf("add_int8 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_int8_1_ssa(1); got != 2 { fmt.Printf("add_int8 1%s1 = %d, wanted 2\n", `+`, got) failed = true } if got := add_1_int8_ssa(126); got != 127 { fmt.Printf("add_int8 1%s126 = %d, wanted 127\n", `+`, got) failed = true } if got := add_int8_1_ssa(126); got != 127 { fmt.Printf("add_int8 126%s1 = %d, wanted 127\n", `+`, got) failed = true } if got := add_1_int8_ssa(127); got != -128 { fmt.Printf("add_int8 1%s127 = %d, wanted -128\n", `+`, got) failed = true } if got := add_int8_1_ssa(127); got != -128 { fmt.Printf("add_int8 127%s1 = %d, wanted -128\n", `+`, got) failed = true } if got := add_126_int8_ssa(-128); got != -2 { fmt.Printf("add_int8 126%s-128 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int8_126_ssa(-128); got != -2 { fmt.Printf("add_int8 -128%s126 = %d, wanted -2\n", `+`, got) failed = true } if got := add_126_int8_ssa(-127); got != -1 { fmt.Printf("add_int8 126%s-127 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int8_126_ssa(-127); got != -1 { fmt.Printf("add_int8 -127%s126 = %d, wanted -1\n", `+`, got) failed = true } if got := add_126_int8_ssa(-1); got != 125 { fmt.Printf("add_int8 126%s-1 = %d, wanted 125\n", `+`, got) failed = true } if got := add_int8_126_ssa(-1); got != 125 { fmt.Printf("add_int8 -1%s126 = %d, wanted 125\n", `+`, got) failed = true } if got := add_126_int8_ssa(0); got != 126 { fmt.Printf("add_int8 126%s0 = %d, wanted 126\n", `+`, got) failed = true } if got := add_int8_126_ssa(0); got != 126 { fmt.Printf("add_int8 0%s126 = %d, wanted 126\n", `+`, got) failed = true } if got := add_126_int8_ssa(1); got != 127 { fmt.Printf("add_int8 126%s1 = %d, wanted 127\n", `+`, got) failed = true } if got := add_int8_126_ssa(1); got != 127 { fmt.Printf("add_int8 1%s126 = %d, wanted 127\n", `+`, got) failed = true } if got := add_126_int8_ssa(126); got != -4 { fmt.Printf("add_int8 126%s126 = %d, wanted -4\n", `+`, got) failed = true } if got := add_int8_126_ssa(126); got != -4 { fmt.Printf("add_int8 126%s126 = %d, wanted -4\n", `+`, got) failed = true } if got := add_126_int8_ssa(127); got != -3 { fmt.Printf("add_int8 126%s127 = %d, wanted -3\n", `+`, got) failed = true } if got := add_int8_126_ssa(127); got != -3 { fmt.Printf("add_int8 127%s126 = %d, wanted -3\n", `+`, got) failed = true } if got := add_127_int8_ssa(-128); got != -1 { fmt.Printf("add_int8 127%s-128 = %d, wanted -1\n", `+`, got) failed = true } if got := add_int8_127_ssa(-128); got != -1 { fmt.Printf("add_int8 -128%s127 = %d, wanted -1\n", `+`, got) failed = true } if got := add_127_int8_ssa(-127); got != 0 { fmt.Printf("add_int8 127%s-127 = %d, wanted 0\n", `+`, got) failed = true } if got := add_int8_127_ssa(-127); got != 0 { fmt.Printf("add_int8 -127%s127 = %d, wanted 0\n", `+`, got) failed = true } if got := add_127_int8_ssa(-1); got != 126 { fmt.Printf("add_int8 127%s-1 = %d, wanted 126\n", `+`, got) failed = true } if got := add_int8_127_ssa(-1); got != 126 { fmt.Printf("add_int8 -1%s127 = %d, wanted 126\n", `+`, got) failed = true } if got := add_127_int8_ssa(0); got != 127 { fmt.Printf("add_int8 127%s0 = %d, wanted 127\n", `+`, got) failed = true } if got := add_int8_127_ssa(0); got != 127 { fmt.Printf("add_int8 0%s127 = %d, wanted 127\n", `+`, got) failed = true } if got := add_127_int8_ssa(1); got != -128 { fmt.Printf("add_int8 127%s1 = %d, wanted -128\n", `+`, got) failed = true } if got := add_int8_127_ssa(1); got != -128 { fmt.Printf("add_int8 1%s127 = %d, wanted -128\n", `+`, got) failed = true } if got := add_127_int8_ssa(126); got != -3 { fmt.Printf("add_int8 127%s126 = %d, wanted -3\n", `+`, got) failed = true } if got := add_int8_127_ssa(126); got != -3 { fmt.Printf("add_int8 126%s127 = %d, wanted -3\n", `+`, got) failed = true } if got := add_127_int8_ssa(127); got != -2 { fmt.Printf("add_int8 127%s127 = %d, wanted -2\n", `+`, got) failed = true } if got := add_int8_127_ssa(127); got != -2 { fmt.Printf("add_int8 127%s127 = %d, wanted -2\n", `+`, got) failed = true } if got := sub_Neg128_int8_ssa(-128); got != 0 { fmt.Printf("sub_int8 -128%s-128 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(-128); got != 0 { fmt.Printf("sub_int8 -128%s-128 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg128_int8_ssa(-127); got != -1 { fmt.Printf("sub_int8 -128%s-127 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(-127); got != 1 { fmt.Printf("sub_int8 -127%s-128 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg128_int8_ssa(-1); got != -127 { fmt.Printf("sub_int8 -128%s-1 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(-1); got != 127 { fmt.Printf("sub_int8 -1%s-128 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_Neg128_int8_ssa(0); got != -128 { fmt.Printf("sub_int8 -128%s0 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(0); got != -128 { fmt.Printf("sub_int8 0%s-128 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_Neg128_int8_ssa(1); got != 127 { fmt.Printf("sub_int8 -128%s1 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(1); got != -127 { fmt.Printf("sub_int8 1%s-128 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_Neg128_int8_ssa(126); got != 2 { fmt.Printf("sub_int8 -128%s126 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(126); got != -2 { fmt.Printf("sub_int8 126%s-128 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg128_int8_ssa(127); got != 1 { fmt.Printf("sub_int8 -128%s127 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int8_Neg128_ssa(127); got != -1 { fmt.Printf("sub_int8 127%s-128 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(-128); got != 1 { fmt.Printf("sub_int8 -127%s-128 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(-128); got != -1 { fmt.Printf("sub_int8 -128%s-127 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(-127); got != 0 { fmt.Printf("sub_int8 -127%s-127 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(-127); got != 0 { fmt.Printf("sub_int8 -127%s-127 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(-1); got != -126 { fmt.Printf("sub_int8 -127%s-1 = %d, wanted -126\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(-1); got != 126 { fmt.Printf("sub_int8 -1%s-127 = %d, wanted 126\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(0); got != -127 { fmt.Printf("sub_int8 -127%s0 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(0); got != 127 { fmt.Printf("sub_int8 0%s-127 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(1); got != -128 { fmt.Printf("sub_int8 -127%s1 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(1); got != -128 { fmt.Printf("sub_int8 1%s-127 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(126); got != 3 { fmt.Printf("sub_int8 -127%s126 = %d, wanted 3\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(126); got != -3 { fmt.Printf("sub_int8 126%s-127 = %d, wanted -3\n", `-`, got) failed = true } if got := sub_Neg127_int8_ssa(127); got != 2 { fmt.Printf("sub_int8 -127%s127 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int8_Neg127_ssa(127); got != -2 { fmt.Printf("sub_int8 127%s-127 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(-128); got != 127 { fmt.Printf("sub_int8 -1%s-128 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(-128); got != -127 { fmt.Printf("sub_int8 -128%s-1 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(-127); got != 126 { fmt.Printf("sub_int8 -1%s-127 = %d, wanted 126\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(-127); got != -126 { fmt.Printf("sub_int8 -127%s-1 = %d, wanted -126\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(-1); got != 0 { fmt.Printf("sub_int8 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(-1); got != 0 { fmt.Printf("sub_int8 -1%s-1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(0); got != -1 { fmt.Printf("sub_int8 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(0); got != 1 { fmt.Printf("sub_int8 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(1); got != -2 { fmt.Printf("sub_int8 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(1); got != 2 { fmt.Printf("sub_int8 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(126); got != -127 { fmt.Printf("sub_int8 -1%s126 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(126); got != 127 { fmt.Printf("sub_int8 126%s-1 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_Neg1_int8_ssa(127); got != -128 { fmt.Printf("sub_int8 -1%s127 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_int8_Neg1_ssa(127); got != -128 { fmt.Printf("sub_int8 127%s-1 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_0_int8_ssa(-128); got != -128 { fmt.Printf("sub_int8 0%s-128 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_int8_0_ssa(-128); got != -128 { fmt.Printf("sub_int8 -128%s0 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_0_int8_ssa(-127); got != 127 { fmt.Printf("sub_int8 0%s-127 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_int8_0_ssa(-127); got != -127 { fmt.Printf("sub_int8 -127%s0 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_0_int8_ssa(-1); got != 1 { fmt.Printf("sub_int8 0%s-1 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int8_0_ssa(-1); got != -1 { fmt.Printf("sub_int8 -1%s0 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_0_int8_ssa(0); got != 0 { fmt.Printf("sub_int8 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_0_ssa(0); got != 0 { fmt.Printf("sub_int8 0%s0 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_0_int8_ssa(1); got != -1 { fmt.Printf("sub_int8 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int8_0_ssa(1); got != 1 { fmt.Printf("sub_int8 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_0_int8_ssa(126); got != -126 { fmt.Printf("sub_int8 0%s126 = %d, wanted -126\n", `-`, got) failed = true } if got := sub_int8_0_ssa(126); got != 126 { fmt.Printf("sub_int8 126%s0 = %d, wanted 126\n", `-`, got) failed = true } if got := sub_0_int8_ssa(127); got != -127 { fmt.Printf("sub_int8 0%s127 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_int8_0_ssa(127); got != 127 { fmt.Printf("sub_int8 127%s0 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_1_int8_ssa(-128); got != -127 { fmt.Printf("sub_int8 1%s-128 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_int8_1_ssa(-128); got != 127 { fmt.Printf("sub_int8 -128%s1 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_1_int8_ssa(-127); got != -128 { fmt.Printf("sub_int8 1%s-127 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_int8_1_ssa(-127); got != -128 { fmt.Printf("sub_int8 -127%s1 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_1_int8_ssa(-1); got != 2 { fmt.Printf("sub_int8 1%s-1 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_int8_1_ssa(-1); got != -2 { fmt.Printf("sub_int8 -1%s1 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_1_int8_ssa(0); got != 1 { fmt.Printf("sub_int8 1%s0 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int8_1_ssa(0); got != -1 { fmt.Printf("sub_int8 0%s1 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_1_int8_ssa(1); got != 0 { fmt.Printf("sub_int8 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_1_ssa(1); got != 0 { fmt.Printf("sub_int8 1%s1 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_1_int8_ssa(126); got != -125 { fmt.Printf("sub_int8 1%s126 = %d, wanted -125\n", `-`, got) failed = true } if got := sub_int8_1_ssa(126); got != 125 { fmt.Printf("sub_int8 126%s1 = %d, wanted 125\n", `-`, got) failed = true } if got := sub_1_int8_ssa(127); got != -126 { fmt.Printf("sub_int8 1%s127 = %d, wanted -126\n", `-`, got) failed = true } if got := sub_int8_1_ssa(127); got != 126 { fmt.Printf("sub_int8 127%s1 = %d, wanted 126\n", `-`, got) failed = true } if got := sub_126_int8_ssa(-128); got != -2 { fmt.Printf("sub_int8 126%s-128 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int8_126_ssa(-128); got != 2 { fmt.Printf("sub_int8 -128%s126 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_126_int8_ssa(-127); got != -3 { fmt.Printf("sub_int8 126%s-127 = %d, wanted -3\n", `-`, got) failed = true } if got := sub_int8_126_ssa(-127); got != 3 { fmt.Printf("sub_int8 -127%s126 = %d, wanted 3\n", `-`, got) failed = true } if got := sub_126_int8_ssa(-1); got != 127 { fmt.Printf("sub_int8 126%s-1 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_int8_126_ssa(-1); got != -127 { fmt.Printf("sub_int8 -1%s126 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_126_int8_ssa(0); got != 126 { fmt.Printf("sub_int8 126%s0 = %d, wanted 126\n", `-`, got) failed = true } if got := sub_int8_126_ssa(0); got != -126 { fmt.Printf("sub_int8 0%s126 = %d, wanted -126\n", `-`, got) failed = true } if got := sub_126_int8_ssa(1); got != 125 { fmt.Printf("sub_int8 126%s1 = %d, wanted 125\n", `-`, got) failed = true } if got := sub_int8_126_ssa(1); got != -125 { fmt.Printf("sub_int8 1%s126 = %d, wanted -125\n", `-`, got) failed = true } if got := sub_126_int8_ssa(126); got != 0 { fmt.Printf("sub_int8 126%s126 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_126_ssa(126); got != 0 { fmt.Printf("sub_int8 126%s126 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_126_int8_ssa(127); got != -1 { fmt.Printf("sub_int8 126%s127 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int8_126_ssa(127); got != 1 { fmt.Printf("sub_int8 127%s126 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_127_int8_ssa(-128); got != -1 { fmt.Printf("sub_int8 127%s-128 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_int8_127_ssa(-128); got != 1 { fmt.Printf("sub_int8 -128%s127 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_127_int8_ssa(-127); got != -2 { fmt.Printf("sub_int8 127%s-127 = %d, wanted -2\n", `-`, got) failed = true } if got := sub_int8_127_ssa(-127); got != 2 { fmt.Printf("sub_int8 -127%s127 = %d, wanted 2\n", `-`, got) failed = true } if got := sub_127_int8_ssa(-1); got != -128 { fmt.Printf("sub_int8 127%s-1 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_int8_127_ssa(-1); got != -128 { fmt.Printf("sub_int8 -1%s127 = %d, wanted -128\n", `-`, got) failed = true } if got := sub_127_int8_ssa(0); got != 127 { fmt.Printf("sub_int8 127%s0 = %d, wanted 127\n", `-`, got) failed = true } if got := sub_int8_127_ssa(0); got != -127 { fmt.Printf("sub_int8 0%s127 = %d, wanted -127\n", `-`, got) failed = true } if got := sub_127_int8_ssa(1); got != 126 { fmt.Printf("sub_int8 127%s1 = %d, wanted 126\n", `-`, got) failed = true } if got := sub_int8_127_ssa(1); got != -126 { fmt.Printf("sub_int8 1%s127 = %d, wanted -126\n", `-`, got) failed = true } if got := sub_127_int8_ssa(126); got != 1 { fmt.Printf("sub_int8 127%s126 = %d, wanted 1\n", `-`, got) failed = true } if got := sub_int8_127_ssa(126); got != -1 { fmt.Printf("sub_int8 126%s127 = %d, wanted -1\n", `-`, got) failed = true } if got := sub_127_int8_ssa(127); got != 0 { fmt.Printf("sub_int8 127%s127 = %d, wanted 0\n", `-`, got) failed = true } if got := sub_int8_127_ssa(127); got != 0 { fmt.Printf("sub_int8 127%s127 = %d, wanted 0\n", `-`, got) failed = true } if got := div_Neg128_int8_ssa(-128); got != 1 { fmt.Printf("div_int8 -128%s-128 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(-128); got != 1 { fmt.Printf("div_int8 -128%s-128 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg128_int8_ssa(-127); got != 1 { fmt.Printf("div_int8 -128%s-127 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(-127); got != 0 { fmt.Printf("div_int8 -127%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg128_int8_ssa(-1); got != -128 { fmt.Printf("div_int8 -128%s-1 = %d, wanted -128\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(-1); got != 0 { fmt.Printf("div_int8 -1%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(0); got != 0 { fmt.Printf("div_int8 0%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg128_int8_ssa(1); got != -128 { fmt.Printf("div_int8 -128%s1 = %d, wanted -128\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(1); got != 0 { fmt.Printf("div_int8 1%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg128_int8_ssa(126); got != -1 { fmt.Printf("div_int8 -128%s126 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(126); got != 0 { fmt.Printf("div_int8 126%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg128_int8_ssa(127); got != -1 { fmt.Printf("div_int8 -128%s127 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_Neg128_ssa(127); got != 0 { fmt.Printf("div_int8 127%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg127_int8_ssa(-128); got != 0 { fmt.Printf("div_int8 -127%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(-128); got != 1 { fmt.Printf("div_int8 -128%s-127 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg127_int8_ssa(-127); got != 1 { fmt.Printf("div_int8 -127%s-127 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(-127); got != 1 { fmt.Printf("div_int8 -127%s-127 = %d, wanted 1\n", `/`, got) failed = true } if got := div_Neg127_int8_ssa(-1); got != 127 { fmt.Printf("div_int8 -127%s-1 = %d, wanted 127\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(-1); got != 0 { fmt.Printf("div_int8 -1%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(0); got != 0 { fmt.Printf("div_int8 0%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg127_int8_ssa(1); got != -127 { fmt.Printf("div_int8 -127%s1 = %d, wanted -127\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(1); got != 0 { fmt.Printf("div_int8 1%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg127_int8_ssa(126); got != -1 { fmt.Printf("div_int8 -127%s126 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(126); got != 0 { fmt.Printf("div_int8 126%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg127_int8_ssa(127); got != -1 { fmt.Printf("div_int8 -127%s127 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_Neg127_ssa(127); got != -1 { fmt.Printf("div_int8 127%s-127 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int8_ssa(-128); got != 0 { fmt.Printf("div_int8 -1%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(-128); got != -128 { fmt.Printf("div_int8 -128%s-1 = %d, wanted -128\n", `/`, got) failed = true } if got := div_Neg1_int8_ssa(-127); got != 0 { fmt.Printf("div_int8 -1%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(-127); got != 127 { fmt.Printf("div_int8 -127%s-1 = %d, wanted 127\n", `/`, got) failed = true } if got := div_Neg1_int8_ssa(-1); got != 1 { fmt.Printf("div_int8 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(-1); got != 1 { fmt.Printf("div_int8 -1%s-1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(0); got != 0 { fmt.Printf("div_int8 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_Neg1_int8_ssa(1); got != -1 { fmt.Printf("div_int8 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(1); got != -1 { fmt.Printf("div_int8 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_Neg1_int8_ssa(126); got != 0 { fmt.Printf("div_int8 -1%s126 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(126); got != -126 { fmt.Printf("div_int8 126%s-1 = %d, wanted -126\n", `/`, got) failed = true } if got := div_Neg1_int8_ssa(127); got != 0 { fmt.Printf("div_int8 -1%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_Neg1_ssa(127); got != -127 { fmt.Printf("div_int8 127%s-1 = %d, wanted -127\n", `/`, got) failed = true } if got := div_0_int8_ssa(-128); got != 0 { fmt.Printf("div_int8 0%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int8_ssa(-127); got != 0 { fmt.Printf("div_int8 0%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int8_ssa(-1); got != 0 { fmt.Printf("div_int8 0%s-1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int8_ssa(1); got != 0 { fmt.Printf("div_int8 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int8_ssa(126); got != 0 { fmt.Printf("div_int8 0%s126 = %d, wanted 0\n", `/`, got) failed = true } if got := div_0_int8_ssa(127); got != 0 { fmt.Printf("div_int8 0%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int8_ssa(-128); got != 0 { fmt.Printf("div_int8 1%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_1_ssa(-128); got != -128 { fmt.Printf("div_int8 -128%s1 = %d, wanted -128\n", `/`, got) failed = true } if got := div_1_int8_ssa(-127); got != 0 { fmt.Printf("div_int8 1%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_1_ssa(-127); got != -127 { fmt.Printf("div_int8 -127%s1 = %d, wanted -127\n", `/`, got) failed = true } if got := div_1_int8_ssa(-1); got != -1 { fmt.Printf("div_int8 1%s-1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_1_ssa(-1); got != -1 { fmt.Printf("div_int8 -1%s1 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_1_ssa(0); got != 0 { fmt.Printf("div_int8 0%s1 = %d, wanted 0\n", `/`, got) failed = true } if got := div_1_int8_ssa(1); got != 1 { fmt.Printf("div_int8 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_1_ssa(1); got != 1 { fmt.Printf("div_int8 1%s1 = %d, wanted 1\n", `/`, got) failed = true } if got := div_1_int8_ssa(126); got != 0 { fmt.Printf("div_int8 1%s126 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_1_ssa(126); got != 126 { fmt.Printf("div_int8 126%s1 = %d, wanted 126\n", `/`, got) failed = true } if got := div_1_int8_ssa(127); got != 0 { fmt.Printf("div_int8 1%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_1_ssa(127); got != 127 { fmt.Printf("div_int8 127%s1 = %d, wanted 127\n", `/`, got) failed = true } if got := div_126_int8_ssa(-128); got != 0 { fmt.Printf("div_int8 126%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_126_ssa(-128); got != -1 { fmt.Printf("div_int8 -128%s126 = %d, wanted -1\n", `/`, got) failed = true } if got := div_126_int8_ssa(-127); got != 0 { fmt.Printf("div_int8 126%s-127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_126_ssa(-127); got != -1 { fmt.Printf("div_int8 -127%s126 = %d, wanted -1\n", `/`, got) failed = true } if got := div_126_int8_ssa(-1); got != -126 { fmt.Printf("div_int8 126%s-1 = %d, wanted -126\n", `/`, got) failed = true } if got := div_int8_126_ssa(-1); got != 0 { fmt.Printf("div_int8 -1%s126 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_126_ssa(0); got != 0 { fmt.Printf("div_int8 0%s126 = %d, wanted 0\n", `/`, got) failed = true } if got := div_126_int8_ssa(1); got != 126 { fmt.Printf("div_int8 126%s1 = %d, wanted 126\n", `/`, got) failed = true } if got := div_int8_126_ssa(1); got != 0 { fmt.Printf("div_int8 1%s126 = %d, wanted 0\n", `/`, got) failed = true } if got := div_126_int8_ssa(126); got != 1 { fmt.Printf("div_int8 126%s126 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_126_ssa(126); got != 1 { fmt.Printf("div_int8 126%s126 = %d, wanted 1\n", `/`, got) failed = true } if got := div_126_int8_ssa(127); got != 0 { fmt.Printf("div_int8 126%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_126_ssa(127); got != 1 { fmt.Printf("div_int8 127%s126 = %d, wanted 1\n", `/`, got) failed = true } if got := div_127_int8_ssa(-128); got != 0 { fmt.Printf("div_int8 127%s-128 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_127_ssa(-128); got != -1 { fmt.Printf("div_int8 -128%s127 = %d, wanted -1\n", `/`, got) failed = true } if got := div_127_int8_ssa(-127); got != -1 { fmt.Printf("div_int8 127%s-127 = %d, wanted -1\n", `/`, got) failed = true } if got := div_int8_127_ssa(-127); got != -1 { fmt.Printf("div_int8 -127%s127 = %d, wanted -1\n", `/`, got) failed = true } if got := div_127_int8_ssa(-1); got != -127 { fmt.Printf("div_int8 127%s-1 = %d, wanted -127\n", `/`, got) failed = true } if got := div_int8_127_ssa(-1); got != 0 { fmt.Printf("div_int8 -1%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_int8_127_ssa(0); got != 0 { fmt.Printf("div_int8 0%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_127_int8_ssa(1); got != 127 { fmt.Printf("div_int8 127%s1 = %d, wanted 127\n", `/`, got) failed = true } if got := div_int8_127_ssa(1); got != 0 { fmt.Printf("div_int8 1%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_127_int8_ssa(126); got != 1 { fmt.Printf("div_int8 127%s126 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_127_ssa(126); got != 0 { fmt.Printf("div_int8 126%s127 = %d, wanted 0\n", `/`, got) failed = true } if got := div_127_int8_ssa(127); got != 1 { fmt.Printf("div_int8 127%s127 = %d, wanted 1\n", `/`, got) failed = true } if got := div_int8_127_ssa(127); got != 1 { fmt.Printf("div_int8 127%s127 = %d, wanted 1\n", `/`, got) failed = true } if got := mul_Neg128_int8_ssa(-128); got != 0 { fmt.Printf("mul_int8 -128%s-128 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(-128); got != 0 { fmt.Printf("mul_int8 -128%s-128 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg128_int8_ssa(-127); got != -128 { fmt.Printf("mul_int8 -128%s-127 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(-127); got != -128 { fmt.Printf("mul_int8 -127%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_Neg128_int8_ssa(-1); got != -128 { fmt.Printf("mul_int8 -128%s-1 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(-1); got != -128 { fmt.Printf("mul_int8 -1%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_Neg128_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 -128%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s-128 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg128_int8_ssa(1); got != -128 { fmt.Printf("mul_int8 -128%s1 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(1); got != -128 { fmt.Printf("mul_int8 1%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_Neg128_int8_ssa(126); got != 0 { fmt.Printf("mul_int8 -128%s126 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(126); got != 0 { fmt.Printf("mul_int8 126%s-128 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg128_int8_ssa(127); got != -128 { fmt.Printf("mul_int8 -128%s127 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_Neg128_ssa(127); got != -128 { fmt.Printf("mul_int8 127%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(-128); got != -128 { fmt.Printf("mul_int8 -127%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(-128); got != -128 { fmt.Printf("mul_int8 -128%s-127 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(-127); got != 1 { fmt.Printf("mul_int8 -127%s-127 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(-127); got != 1 { fmt.Printf("mul_int8 -127%s-127 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(-1); got != 127 { fmt.Printf("mul_int8 -127%s-1 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(-1); got != 127 { fmt.Printf("mul_int8 -1%s-127 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 -127%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s-127 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(1); got != -127 { fmt.Printf("mul_int8 -127%s1 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(1); got != -127 { fmt.Printf("mul_int8 1%s-127 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(126); got != 126 { fmt.Printf("mul_int8 -127%s126 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(126); got != 126 { fmt.Printf("mul_int8 126%s-127 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_Neg127_int8_ssa(127); got != -1 { fmt.Printf("mul_int8 -127%s127 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int8_Neg127_ssa(127); got != -1 { fmt.Printf("mul_int8 127%s-127 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(-128); got != -128 { fmt.Printf("mul_int8 -1%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(-128); got != -128 { fmt.Printf("mul_int8 -128%s-1 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(-127); got != 127 { fmt.Printf("mul_int8 -1%s-127 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(-127); got != 127 { fmt.Printf("mul_int8 -127%s-1 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(-1); got != 1 { fmt.Printf("mul_int8 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(-1); got != 1 { fmt.Printf("mul_int8 -1%s-1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(1); got != -1 { fmt.Printf("mul_int8 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(1); got != -1 { fmt.Printf("mul_int8 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(126); got != -126 { fmt.Printf("mul_int8 -1%s126 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(126); got != -126 { fmt.Printf("mul_int8 126%s-1 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_Neg1_int8_ssa(127); got != -127 { fmt.Printf("mul_int8 -1%s127 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_int8_Neg1_ssa(127); got != -127 { fmt.Printf("mul_int8 127%s-1 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_0_int8_ssa(-128); got != 0 { fmt.Printf("mul_int8 0%s-128 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(-128); got != 0 { fmt.Printf("mul_int8 -128%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int8_ssa(-127); got != 0 { fmt.Printf("mul_int8 0%s-127 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(-127); got != 0 { fmt.Printf("mul_int8 -127%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int8_ssa(-1); got != 0 { fmt.Printf("mul_int8 0%s-1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(-1); got != 0 { fmt.Printf("mul_int8 -1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int8_ssa(1); got != 0 { fmt.Printf("mul_int8 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(1); got != 0 { fmt.Printf("mul_int8 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int8_ssa(126); got != 0 { fmt.Printf("mul_int8 0%s126 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(126); got != 0 { fmt.Printf("mul_int8 126%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_0_int8_ssa(127); got != 0 { fmt.Printf("mul_int8 0%s127 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_0_ssa(127); got != 0 { fmt.Printf("mul_int8 127%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int8_ssa(-128); got != -128 { fmt.Printf("mul_int8 1%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_1_ssa(-128); got != -128 { fmt.Printf("mul_int8 -128%s1 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_1_int8_ssa(-127); got != -127 { fmt.Printf("mul_int8 1%s-127 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_int8_1_ssa(-127); got != -127 { fmt.Printf("mul_int8 -127%s1 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_1_int8_ssa(-1); got != -1 { fmt.Printf("mul_int8 1%s-1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int8_1_ssa(-1); got != -1 { fmt.Printf("mul_int8 -1%s1 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_1_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 1%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_1_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s1 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_1_int8_ssa(1); got != 1 { fmt.Printf("mul_int8 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int8_1_ssa(1); got != 1 { fmt.Printf("mul_int8 1%s1 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_1_int8_ssa(126); got != 126 { fmt.Printf("mul_int8 1%s126 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_int8_1_ssa(126); got != 126 { fmt.Printf("mul_int8 126%s1 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_1_int8_ssa(127); got != 127 { fmt.Printf("mul_int8 1%s127 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_int8_1_ssa(127); got != 127 { fmt.Printf("mul_int8 127%s1 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_126_int8_ssa(-128); got != 0 { fmt.Printf("mul_int8 126%s-128 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_126_ssa(-128); got != 0 { fmt.Printf("mul_int8 -128%s126 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_126_int8_ssa(-127); got != 126 { fmt.Printf("mul_int8 126%s-127 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_int8_126_ssa(-127); got != 126 { fmt.Printf("mul_int8 -127%s126 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_126_int8_ssa(-1); got != -126 { fmt.Printf("mul_int8 126%s-1 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_int8_126_ssa(-1); got != -126 { fmt.Printf("mul_int8 -1%s126 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_126_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 126%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_126_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s126 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_126_int8_ssa(1); got != 126 { fmt.Printf("mul_int8 126%s1 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_int8_126_ssa(1); got != 126 { fmt.Printf("mul_int8 1%s126 = %d, wanted 126\n", `*`, got) failed = true } if got := mul_126_int8_ssa(126); got != 4 { fmt.Printf("mul_int8 126%s126 = %d, wanted 4\n", `*`, got) failed = true } if got := mul_int8_126_ssa(126); got != 4 { fmt.Printf("mul_int8 126%s126 = %d, wanted 4\n", `*`, got) failed = true } if got := mul_126_int8_ssa(127); got != -126 { fmt.Printf("mul_int8 126%s127 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_int8_126_ssa(127); got != -126 { fmt.Printf("mul_int8 127%s126 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_127_int8_ssa(-128); got != -128 { fmt.Printf("mul_int8 127%s-128 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_int8_127_ssa(-128); got != -128 { fmt.Printf("mul_int8 -128%s127 = %d, wanted -128\n", `*`, got) failed = true } if got := mul_127_int8_ssa(-127); got != -1 { fmt.Printf("mul_int8 127%s-127 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_int8_127_ssa(-127); got != -1 { fmt.Printf("mul_int8 -127%s127 = %d, wanted -1\n", `*`, got) failed = true } if got := mul_127_int8_ssa(-1); got != -127 { fmt.Printf("mul_int8 127%s-1 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_int8_127_ssa(-1); got != -127 { fmt.Printf("mul_int8 -1%s127 = %d, wanted -127\n", `*`, got) failed = true } if got := mul_127_int8_ssa(0); got != 0 { fmt.Printf("mul_int8 127%s0 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_int8_127_ssa(0); got != 0 { fmt.Printf("mul_int8 0%s127 = %d, wanted 0\n", `*`, got) failed = true } if got := mul_127_int8_ssa(1); got != 127 { fmt.Printf("mul_int8 127%s1 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_int8_127_ssa(1); got != 127 { fmt.Printf("mul_int8 1%s127 = %d, wanted 127\n", `*`, got) failed = true } if got := mul_127_int8_ssa(126); got != -126 { fmt.Printf("mul_int8 127%s126 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_int8_127_ssa(126); got != -126 { fmt.Printf("mul_int8 126%s127 = %d, wanted -126\n", `*`, got) failed = true } if got := mul_127_int8_ssa(127); got != 1 { fmt.Printf("mul_int8 127%s127 = %d, wanted 1\n", `*`, got) failed = true } if got := mul_int8_127_ssa(127); got != 1 { fmt.Printf("mul_int8 127%s127 = %d, wanted 1\n", `*`, got) failed = true } if got := mod_Neg128_int8_ssa(-128); got != 0 { fmt.Printf("mod_int8 -128%s-128 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(-128); got != 0 { fmt.Printf("mod_int8 -128%s-128 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg128_int8_ssa(-127); got != -1 { fmt.Printf("mod_int8 -128%s-127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(-127); got != -127 { fmt.Printf("mod_int8 -127%s-128 = %d, wanted -127\n", `%`, got) failed = true } if got := mod_Neg128_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 -128%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(-1); got != -1 { fmt.Printf("mod_int8 -1%s-128 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(0); got != 0 { fmt.Printf("mod_int8 0%s-128 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg128_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 -128%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(1); got != 1 { fmt.Printf("mod_int8 1%s-128 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg128_int8_ssa(126); got != -2 { fmt.Printf("mod_int8 -128%s126 = %d, wanted -2\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(126); got != 126 { fmt.Printf("mod_int8 126%s-128 = %d, wanted 126\n", `%`, got) failed = true } if got := mod_Neg128_int8_ssa(127); got != -1 { fmt.Printf("mod_int8 -128%s127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg128_ssa(127); got != 127 { fmt.Printf("mod_int8 127%s-128 = %d, wanted 127\n", `%`, got) failed = true } if got := mod_Neg127_int8_ssa(-128); got != -127 { fmt.Printf("mod_int8 -127%s-128 = %d, wanted -127\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(-128); got != -1 { fmt.Printf("mod_int8 -128%s-127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_Neg127_int8_ssa(-127); got != 0 { fmt.Printf("mod_int8 -127%s-127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(-127); got != 0 { fmt.Printf("mod_int8 -127%s-127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg127_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 -127%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(-1); got != -1 { fmt.Printf("mod_int8 -1%s-127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(0); got != 0 { fmt.Printf("mod_int8 0%s-127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg127_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 -127%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(1); got != 1 { fmt.Printf("mod_int8 1%s-127 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_Neg127_int8_ssa(126); got != -1 { fmt.Printf("mod_int8 -127%s126 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(126); got != 126 { fmt.Printf("mod_int8 126%s-127 = %d, wanted 126\n", `%`, got) failed = true } if got := mod_Neg127_int8_ssa(127); got != 0 { fmt.Printf("mod_int8 -127%s127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg127_ssa(127); got != 0 { fmt.Printf("mod_int8 127%s-127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int8_ssa(-128); got != -1 { fmt.Printf("mod_int8 -1%s-128 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(-128); got != 0 { fmt.Printf("mod_int8 -128%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int8_ssa(-127); got != -1 { fmt.Printf("mod_int8 -1%s-127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(-127); got != 0 { fmt.Printf("mod_int8 -127%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(-1); got != 0 { fmt.Printf("mod_int8 -1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(0); got != 0 { fmt.Printf("mod_int8 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(1); got != 0 { fmt.Printf("mod_int8 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int8_ssa(126); got != -1 { fmt.Printf("mod_int8 -1%s126 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(126); got != 0 { fmt.Printf("mod_int8 126%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_Neg1_int8_ssa(127); got != -1 { fmt.Printf("mod_int8 -1%s127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_Neg1_ssa(127); got != 0 { fmt.Printf("mod_int8 127%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int8_ssa(-128); got != 0 { fmt.Printf("mod_int8 0%s-128 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int8_ssa(-127); got != 0 { fmt.Printf("mod_int8 0%s-127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 0%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int8_ssa(126); got != 0 { fmt.Printf("mod_int8 0%s126 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_0_int8_ssa(127); got != 0 { fmt.Printf("mod_int8 0%s127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int8_ssa(-128); got != 1 { fmt.Printf("mod_int8 1%s-128 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int8_1_ssa(-128); got != 0 { fmt.Printf("mod_int8 -128%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int8_ssa(-127); got != 1 { fmt.Printf("mod_int8 1%s-127 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int8_1_ssa(-127); got != 0 { fmt.Printf("mod_int8 -127%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 1%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_1_ssa(-1); got != 0 { fmt.Printf("mod_int8 -1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_1_ssa(0); got != 0 { fmt.Printf("mod_int8 0%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_1_ssa(1); got != 0 { fmt.Printf("mod_int8 1%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int8_ssa(126); got != 1 { fmt.Printf("mod_int8 1%s126 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int8_1_ssa(126); got != 0 { fmt.Printf("mod_int8 126%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_1_int8_ssa(127); got != 1 { fmt.Printf("mod_int8 1%s127 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int8_1_ssa(127); got != 0 { fmt.Printf("mod_int8 127%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_126_int8_ssa(-128); got != 126 { fmt.Printf("mod_int8 126%s-128 = %d, wanted 126\n", `%`, got) failed = true } if got := mod_int8_126_ssa(-128); got != -2 { fmt.Printf("mod_int8 -128%s126 = %d, wanted -2\n", `%`, got) failed = true } if got := mod_126_int8_ssa(-127); got != 126 { fmt.Printf("mod_int8 126%s-127 = %d, wanted 126\n", `%`, got) failed = true } if got := mod_int8_126_ssa(-127); got != -1 { fmt.Printf("mod_int8 -127%s126 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_126_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 126%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_126_ssa(-1); got != -1 { fmt.Printf("mod_int8 -1%s126 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_126_ssa(0); got != 0 { fmt.Printf("mod_int8 0%s126 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_126_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 126%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_126_ssa(1); got != 1 { fmt.Printf("mod_int8 1%s126 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_126_int8_ssa(126); got != 0 { fmt.Printf("mod_int8 126%s126 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_126_ssa(126); got != 0 { fmt.Printf("mod_int8 126%s126 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_126_int8_ssa(127); got != 126 { fmt.Printf("mod_int8 126%s127 = %d, wanted 126\n", `%`, got) failed = true } if got := mod_int8_126_ssa(127); got != 1 { fmt.Printf("mod_int8 127%s126 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_127_int8_ssa(-128); got != 127 { fmt.Printf("mod_int8 127%s-128 = %d, wanted 127\n", `%`, got) failed = true } if got := mod_int8_127_ssa(-128); got != -1 { fmt.Printf("mod_int8 -128%s127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_127_int8_ssa(-127); got != 0 { fmt.Printf("mod_int8 127%s-127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_127_ssa(-127); got != 0 { fmt.Printf("mod_int8 -127%s127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_127_int8_ssa(-1); got != 0 { fmt.Printf("mod_int8 127%s-1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_127_ssa(-1); got != -1 { fmt.Printf("mod_int8 -1%s127 = %d, wanted -1\n", `%`, got) failed = true } if got := mod_int8_127_ssa(0); got != 0 { fmt.Printf("mod_int8 0%s127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_127_int8_ssa(1); got != 0 { fmt.Printf("mod_int8 127%s1 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_127_ssa(1); got != 1 { fmt.Printf("mod_int8 1%s127 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_127_int8_ssa(126); got != 1 { fmt.Printf("mod_int8 127%s126 = %d, wanted 1\n", `%`, got) failed = true } if got := mod_int8_127_ssa(126); got != 126 { fmt.Printf("mod_int8 126%s127 = %d, wanted 126\n", `%`, got) failed = true } if got := mod_127_int8_ssa(127); got != 0 { fmt.Printf("mod_int8 127%s127 = %d, wanted 0\n", `%`, got) failed = true } if got := mod_int8_127_ssa(127); got != 0 { fmt.Printf("mod_int8 127%s127 = %d, wanted 0\n", `%`, got) failed = true } if got := and_Neg128_int8_ssa(-128); got != -128 { fmt.Printf("and_int8 -128%s-128 = %d, wanted -128\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(-128); got != -128 { fmt.Printf("and_int8 -128%s-128 = %d, wanted -128\n", `&`, got) failed = true } if got := and_Neg128_int8_ssa(-127); got != -128 { fmt.Printf("and_int8 -128%s-127 = %d, wanted -128\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(-127); got != -128 { fmt.Printf("and_int8 -127%s-128 = %d, wanted -128\n", `&`, got) failed = true } if got := and_Neg128_int8_ssa(-1); got != -128 { fmt.Printf("and_int8 -128%s-1 = %d, wanted -128\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(-1); got != -128 { fmt.Printf("and_int8 -1%s-128 = %d, wanted -128\n", `&`, got) failed = true } if got := and_Neg128_int8_ssa(0); got != 0 { fmt.Printf("and_int8 -128%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(0); got != 0 { fmt.Printf("and_int8 0%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg128_int8_ssa(1); got != 0 { fmt.Printf("and_int8 -128%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(1); got != 0 { fmt.Printf("and_int8 1%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg128_int8_ssa(126); got != 0 { fmt.Printf("and_int8 -128%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(126); got != 0 { fmt.Printf("and_int8 126%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg128_int8_ssa(127); got != 0 { fmt.Printf("and_int8 -128%s127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg128_ssa(127); got != 0 { fmt.Printf("and_int8 127%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(-128); got != -128 { fmt.Printf("and_int8 -127%s-128 = %d, wanted -128\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(-128); got != -128 { fmt.Printf("and_int8 -128%s-127 = %d, wanted -128\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(-127); got != -127 { fmt.Printf("and_int8 -127%s-127 = %d, wanted -127\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(-127); got != -127 { fmt.Printf("and_int8 -127%s-127 = %d, wanted -127\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(-1); got != -127 { fmt.Printf("and_int8 -127%s-1 = %d, wanted -127\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(-1); got != -127 { fmt.Printf("and_int8 -1%s-127 = %d, wanted -127\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(0); got != 0 { fmt.Printf("and_int8 -127%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(0); got != 0 { fmt.Printf("and_int8 0%s-127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(1); got != 1 { fmt.Printf("and_int8 -127%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(1); got != 1 { fmt.Printf("and_int8 1%s-127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(126); got != 0 { fmt.Printf("and_int8 -127%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(126); got != 0 { fmt.Printf("and_int8 126%s-127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg127_int8_ssa(127); got != 1 { fmt.Printf("and_int8 -127%s127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_Neg127_ssa(127); got != 1 { fmt.Printf("and_int8 127%s-127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(-128); got != -128 { fmt.Printf("and_int8 -1%s-128 = %d, wanted -128\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(-128); got != -128 { fmt.Printf("and_int8 -128%s-1 = %d, wanted -128\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(-127); got != -127 { fmt.Printf("and_int8 -1%s-127 = %d, wanted -127\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(-127); got != -127 { fmt.Printf("and_int8 -127%s-1 = %d, wanted -127\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(-1); got != -1 { fmt.Printf("and_int8 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(-1); got != -1 { fmt.Printf("and_int8 -1%s-1 = %d, wanted -1\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(0); got != 0 { fmt.Printf("and_int8 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(0); got != 0 { fmt.Printf("and_int8 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(1); got != 1 { fmt.Printf("and_int8 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(1); got != 1 { fmt.Printf("and_int8 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(126); got != 126 { fmt.Printf("and_int8 -1%s126 = %d, wanted 126\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(126); got != 126 { fmt.Printf("and_int8 126%s-1 = %d, wanted 126\n", `&`, got) failed = true } if got := and_Neg1_int8_ssa(127); got != 127 { fmt.Printf("and_int8 -1%s127 = %d, wanted 127\n", `&`, got) failed = true } if got := and_int8_Neg1_ssa(127); got != 127 { fmt.Printf("and_int8 127%s-1 = %d, wanted 127\n", `&`, got) failed = true } if got := and_0_int8_ssa(-128); got != 0 { fmt.Printf("and_int8 0%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(-128); got != 0 { fmt.Printf("and_int8 -128%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int8_ssa(-127); got != 0 { fmt.Printf("and_int8 0%s-127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(-127); got != 0 { fmt.Printf("and_int8 -127%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int8_ssa(-1); got != 0 { fmt.Printf("and_int8 0%s-1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(-1); got != 0 { fmt.Printf("and_int8 -1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int8_ssa(0); got != 0 { fmt.Printf("and_int8 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(0); got != 0 { fmt.Printf("and_int8 0%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int8_ssa(1); got != 0 { fmt.Printf("and_int8 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(1); got != 0 { fmt.Printf("and_int8 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int8_ssa(126); got != 0 { fmt.Printf("and_int8 0%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(126); got != 0 { fmt.Printf("and_int8 126%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_0_int8_ssa(127); got != 0 { fmt.Printf("and_int8 0%s127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_0_ssa(127); got != 0 { fmt.Printf("and_int8 127%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int8_ssa(-128); got != 0 { fmt.Printf("and_int8 1%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_1_ssa(-128); got != 0 { fmt.Printf("and_int8 -128%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int8_ssa(-127); got != 1 { fmt.Printf("and_int8 1%s-127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_1_ssa(-127); got != 1 { fmt.Printf("and_int8 -127%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int8_ssa(-1); got != 1 { fmt.Printf("and_int8 1%s-1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_1_ssa(-1); got != 1 { fmt.Printf("and_int8 -1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int8_ssa(0); got != 0 { fmt.Printf("and_int8 1%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_1_ssa(0); got != 0 { fmt.Printf("and_int8 0%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int8_ssa(1); got != 1 { fmt.Printf("and_int8 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_1_ssa(1); got != 1 { fmt.Printf("and_int8 1%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_1_int8_ssa(126); got != 0 { fmt.Printf("and_int8 1%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_1_ssa(126); got != 0 { fmt.Printf("and_int8 126%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_1_int8_ssa(127); got != 1 { fmt.Printf("and_int8 1%s127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_1_ssa(127); got != 1 { fmt.Printf("and_int8 127%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_126_int8_ssa(-128); got != 0 { fmt.Printf("and_int8 126%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_126_ssa(-128); got != 0 { fmt.Printf("and_int8 -128%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_126_int8_ssa(-127); got != 0 { fmt.Printf("and_int8 126%s-127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_126_ssa(-127); got != 0 { fmt.Printf("and_int8 -127%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_126_int8_ssa(-1); got != 126 { fmt.Printf("and_int8 126%s-1 = %d, wanted 126\n", `&`, got) failed = true } if got := and_int8_126_ssa(-1); got != 126 { fmt.Printf("and_int8 -1%s126 = %d, wanted 126\n", `&`, got) failed = true } if got := and_126_int8_ssa(0); got != 0 { fmt.Printf("and_int8 126%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_126_ssa(0); got != 0 { fmt.Printf("and_int8 0%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_126_int8_ssa(1); got != 0 { fmt.Printf("and_int8 126%s1 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_126_ssa(1); got != 0 { fmt.Printf("and_int8 1%s126 = %d, wanted 0\n", `&`, got) failed = true } if got := and_126_int8_ssa(126); got != 126 { fmt.Printf("and_int8 126%s126 = %d, wanted 126\n", `&`, got) failed = true } if got := and_int8_126_ssa(126); got != 126 { fmt.Printf("and_int8 126%s126 = %d, wanted 126\n", `&`, got) failed = true } if got := and_126_int8_ssa(127); got != 126 { fmt.Printf("and_int8 126%s127 = %d, wanted 126\n", `&`, got) failed = true } if got := and_int8_126_ssa(127); got != 126 { fmt.Printf("and_int8 127%s126 = %d, wanted 126\n", `&`, got) failed = true } if got := and_127_int8_ssa(-128); got != 0 { fmt.Printf("and_int8 127%s-128 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_127_ssa(-128); got != 0 { fmt.Printf("and_int8 -128%s127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_127_int8_ssa(-127); got != 1 { fmt.Printf("and_int8 127%s-127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_127_ssa(-127); got != 1 { fmt.Printf("and_int8 -127%s127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_127_int8_ssa(-1); got != 127 { fmt.Printf("and_int8 127%s-1 = %d, wanted 127\n", `&`, got) failed = true } if got := and_int8_127_ssa(-1); got != 127 { fmt.Printf("and_int8 -1%s127 = %d, wanted 127\n", `&`, got) failed = true } if got := and_127_int8_ssa(0); got != 0 { fmt.Printf("and_int8 127%s0 = %d, wanted 0\n", `&`, got) failed = true } if got := and_int8_127_ssa(0); got != 0 { fmt.Printf("and_int8 0%s127 = %d, wanted 0\n", `&`, got) failed = true } if got := and_127_int8_ssa(1); got != 1 { fmt.Printf("and_int8 127%s1 = %d, wanted 1\n", `&`, got) failed = true } if got := and_int8_127_ssa(1); got != 1 { fmt.Printf("and_int8 1%s127 = %d, wanted 1\n", `&`, got) failed = true } if got := and_127_int8_ssa(126); got != 126 { fmt.Printf("and_int8 127%s126 = %d, wanted 126\n", `&`, got) failed = true } if got := and_int8_127_ssa(126); got != 126 { fmt.Printf("and_int8 126%s127 = %d, wanted 126\n", `&`, got) failed = true } if got := and_127_int8_ssa(127); got != 127 { fmt.Printf("and_int8 127%s127 = %d, wanted 127\n", `&`, got) failed = true } if got := and_int8_127_ssa(127); got != 127 { fmt.Printf("and_int8 127%s127 = %d, wanted 127\n", `&`, got) failed = true } if got := or_Neg128_int8_ssa(-128); got != -128 { fmt.Printf("or_int8 -128%s-128 = %d, wanted -128\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(-128); got != -128 { fmt.Printf("or_int8 -128%s-128 = %d, wanted -128\n", `|`, got) failed = true } if got := or_Neg128_int8_ssa(-127); got != -127 { fmt.Printf("or_int8 -128%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(-127); got != -127 { fmt.Printf("or_int8 -127%s-128 = %d, wanted -127\n", `|`, got) failed = true } if got := or_Neg128_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 -128%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s-128 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg128_int8_ssa(0); got != -128 { fmt.Printf("or_int8 -128%s0 = %d, wanted -128\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(0); got != -128 { fmt.Printf("or_int8 0%s-128 = %d, wanted -128\n", `|`, got) failed = true } if got := or_Neg128_int8_ssa(1); got != -127 { fmt.Printf("or_int8 -128%s1 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(1); got != -127 { fmt.Printf("or_int8 1%s-128 = %d, wanted -127\n", `|`, got) failed = true } if got := or_Neg128_int8_ssa(126); got != -2 { fmt.Printf("or_int8 -128%s126 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(126); got != -2 { fmt.Printf("or_int8 126%s-128 = %d, wanted -2\n", `|`, got) failed = true } if got := or_Neg128_int8_ssa(127); got != -1 { fmt.Printf("or_int8 -128%s127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg128_ssa(127); got != -1 { fmt.Printf("or_int8 127%s-128 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(-128); got != -127 { fmt.Printf("or_int8 -127%s-128 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(-128); got != -127 { fmt.Printf("or_int8 -128%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(-127); got != -127 { fmt.Printf("or_int8 -127%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(-127); got != -127 { fmt.Printf("or_int8 -127%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 -127%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s-127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(0); got != -127 { fmt.Printf("or_int8 -127%s0 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(0); got != -127 { fmt.Printf("or_int8 0%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(1); got != -127 { fmt.Printf("or_int8 -127%s1 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(1); got != -127 { fmt.Printf("or_int8 1%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(126); got != -1 { fmt.Printf("or_int8 -127%s126 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(126); got != -1 { fmt.Printf("or_int8 126%s-127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg127_int8_ssa(127); got != -1 { fmt.Printf("or_int8 -127%s127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg127_ssa(127); got != -1 { fmt.Printf("or_int8 127%s-127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(-128); got != -1 { fmt.Printf("or_int8 -1%s-128 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(-128); got != -1 { fmt.Printf("or_int8 -128%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(-127); got != -1 { fmt.Printf("or_int8 -1%s-127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(-127); got != -1 { fmt.Printf("or_int8 -127%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(0); got != -1 { fmt.Printf("or_int8 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(0); got != -1 { fmt.Printf("or_int8 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(1); got != -1 { fmt.Printf("or_int8 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(1); got != -1 { fmt.Printf("or_int8 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(126); got != -1 { fmt.Printf("or_int8 -1%s126 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(126); got != -1 { fmt.Printf("or_int8 126%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_Neg1_int8_ssa(127); got != -1 { fmt.Printf("or_int8 -1%s127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_Neg1_ssa(127); got != -1 { fmt.Printf("or_int8 127%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int8_ssa(-128); got != -128 { fmt.Printf("or_int8 0%s-128 = %d, wanted -128\n", `|`, got) failed = true } if got := or_int8_0_ssa(-128); got != -128 { fmt.Printf("or_int8 -128%s0 = %d, wanted -128\n", `|`, got) failed = true } if got := or_0_int8_ssa(-127); got != -127 { fmt.Printf("or_int8 0%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_0_ssa(-127); got != -127 { fmt.Printf("or_int8 -127%s0 = %d, wanted -127\n", `|`, got) failed = true } if got := or_0_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 0%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_0_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s0 = %d, wanted -1\n", `|`, got) failed = true } if got := or_0_int8_ssa(0); got != 0 { fmt.Printf("or_int8 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_int8_0_ssa(0); got != 0 { fmt.Printf("or_int8 0%s0 = %d, wanted 0\n", `|`, got) failed = true } if got := or_0_int8_ssa(1); got != 1 { fmt.Printf("or_int8 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int8_0_ssa(1); got != 1 { fmt.Printf("or_int8 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_0_int8_ssa(126); got != 126 { fmt.Printf("or_int8 0%s126 = %d, wanted 126\n", `|`, got) failed = true } if got := or_int8_0_ssa(126); got != 126 { fmt.Printf("or_int8 126%s0 = %d, wanted 126\n", `|`, got) failed = true } if got := or_0_int8_ssa(127); got != 127 { fmt.Printf("or_int8 0%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_0_ssa(127); got != 127 { fmt.Printf("or_int8 127%s0 = %d, wanted 127\n", `|`, got) failed = true } if got := or_1_int8_ssa(-128); got != -127 { fmt.Printf("or_int8 1%s-128 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_1_ssa(-128); got != -127 { fmt.Printf("or_int8 -128%s1 = %d, wanted -127\n", `|`, got) failed = true } if got := or_1_int8_ssa(-127); got != -127 { fmt.Printf("or_int8 1%s-127 = %d, wanted -127\n", `|`, got) failed = true } if got := or_int8_1_ssa(-127); got != -127 { fmt.Printf("or_int8 -127%s1 = %d, wanted -127\n", `|`, got) failed = true } if got := or_1_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 1%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_1_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_1_int8_ssa(0); got != 1 { fmt.Printf("or_int8 1%s0 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int8_1_ssa(0); got != 1 { fmt.Printf("or_int8 0%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int8_ssa(1); got != 1 { fmt.Printf("or_int8 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_int8_1_ssa(1); got != 1 { fmt.Printf("or_int8 1%s1 = %d, wanted 1\n", `|`, got) failed = true } if got := or_1_int8_ssa(126); got != 127 { fmt.Printf("or_int8 1%s126 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_1_ssa(126); got != 127 { fmt.Printf("or_int8 126%s1 = %d, wanted 127\n", `|`, got) failed = true } if got := or_1_int8_ssa(127); got != 127 { fmt.Printf("or_int8 1%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_1_ssa(127); got != 127 { fmt.Printf("or_int8 127%s1 = %d, wanted 127\n", `|`, got) failed = true } if got := or_126_int8_ssa(-128); got != -2 { fmt.Printf("or_int8 126%s-128 = %d, wanted -2\n", `|`, got) failed = true } if got := or_int8_126_ssa(-128); got != -2 { fmt.Printf("or_int8 -128%s126 = %d, wanted -2\n", `|`, got) failed = true } if got := or_126_int8_ssa(-127); got != -1 { fmt.Printf("or_int8 126%s-127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_126_ssa(-127); got != -1 { fmt.Printf("or_int8 -127%s126 = %d, wanted -1\n", `|`, got) failed = true } if got := or_126_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 126%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_126_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s126 = %d, wanted -1\n", `|`, got) failed = true } if got := or_126_int8_ssa(0); got != 126 { fmt.Printf("or_int8 126%s0 = %d, wanted 126\n", `|`, got) failed = true } if got := or_int8_126_ssa(0); got != 126 { fmt.Printf("or_int8 0%s126 = %d, wanted 126\n", `|`, got) failed = true } if got := or_126_int8_ssa(1); got != 127 { fmt.Printf("or_int8 126%s1 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_126_ssa(1); got != 127 { fmt.Printf("or_int8 1%s126 = %d, wanted 127\n", `|`, got) failed = true } if got := or_126_int8_ssa(126); got != 126 { fmt.Printf("or_int8 126%s126 = %d, wanted 126\n", `|`, got) failed = true } if got := or_int8_126_ssa(126); got != 126 { fmt.Printf("or_int8 126%s126 = %d, wanted 126\n", `|`, got) failed = true } if got := or_126_int8_ssa(127); got != 127 { fmt.Printf("or_int8 126%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_126_ssa(127); got != 127 { fmt.Printf("or_int8 127%s126 = %d, wanted 127\n", `|`, got) failed = true } if got := or_127_int8_ssa(-128); got != -1 { fmt.Printf("or_int8 127%s-128 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_127_ssa(-128); got != -1 { fmt.Printf("or_int8 -128%s127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_127_int8_ssa(-127); got != -1 { fmt.Printf("or_int8 127%s-127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_127_ssa(-127); got != -1 { fmt.Printf("or_int8 -127%s127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_127_int8_ssa(-1); got != -1 { fmt.Printf("or_int8 127%s-1 = %d, wanted -1\n", `|`, got) failed = true } if got := or_int8_127_ssa(-1); got != -1 { fmt.Printf("or_int8 -1%s127 = %d, wanted -1\n", `|`, got) failed = true } if got := or_127_int8_ssa(0); got != 127 { fmt.Printf("or_int8 127%s0 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_127_ssa(0); got != 127 { fmt.Printf("or_int8 0%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_127_int8_ssa(1); got != 127 { fmt.Printf("or_int8 127%s1 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_127_ssa(1); got != 127 { fmt.Printf("or_int8 1%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_127_int8_ssa(126); got != 127 { fmt.Printf("or_int8 127%s126 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_127_ssa(126); got != 127 { fmt.Printf("or_int8 126%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_127_int8_ssa(127); got != 127 { fmt.Printf("or_int8 127%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := or_int8_127_ssa(127); got != 127 { fmt.Printf("or_int8 127%s127 = %d, wanted 127\n", `|`, got) failed = true } if got := xor_Neg128_int8_ssa(-128); got != 0 { fmt.Printf("xor_int8 -128%s-128 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(-128); got != 0 { fmt.Printf("xor_int8 -128%s-128 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg128_int8_ssa(-127); got != 1 { fmt.Printf("xor_int8 -128%s-127 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(-127); got != 1 { fmt.Printf("xor_int8 -127%s-128 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg128_int8_ssa(-1); got != 127 { fmt.Printf("xor_int8 -128%s-1 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(-1); got != 127 { fmt.Printf("xor_int8 -1%s-128 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_Neg128_int8_ssa(0); got != -128 { fmt.Printf("xor_int8 -128%s0 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(0); got != -128 { fmt.Printf("xor_int8 0%s-128 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_Neg128_int8_ssa(1); got != -127 { fmt.Printf("xor_int8 -128%s1 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(1); got != -127 { fmt.Printf("xor_int8 1%s-128 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_Neg128_int8_ssa(126); got != -2 { fmt.Printf("xor_int8 -128%s126 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(126); got != -2 { fmt.Printf("xor_int8 126%s-128 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg128_int8_ssa(127); got != -1 { fmt.Printf("xor_int8 -128%s127 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int8_Neg128_ssa(127); got != -1 { fmt.Printf("xor_int8 127%s-128 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(-128); got != 1 { fmt.Printf("xor_int8 -127%s-128 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(-128); got != 1 { fmt.Printf("xor_int8 -128%s-127 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(-127); got != 0 { fmt.Printf("xor_int8 -127%s-127 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(-127); got != 0 { fmt.Printf("xor_int8 -127%s-127 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(-1); got != 126 { fmt.Printf("xor_int8 -127%s-1 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(-1); got != 126 { fmt.Printf("xor_int8 -1%s-127 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(0); got != -127 { fmt.Printf("xor_int8 -127%s0 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(0); got != -127 { fmt.Printf("xor_int8 0%s-127 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(1); got != -128 { fmt.Printf("xor_int8 -127%s1 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(1); got != -128 { fmt.Printf("xor_int8 1%s-127 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(126); got != -1 { fmt.Printf("xor_int8 -127%s126 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(126); got != -1 { fmt.Printf("xor_int8 126%s-127 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg127_int8_ssa(127); got != -2 { fmt.Printf("xor_int8 -127%s127 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int8_Neg127_ssa(127); got != -2 { fmt.Printf("xor_int8 127%s-127 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(-128); got != 127 { fmt.Printf("xor_int8 -1%s-128 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(-128); got != 127 { fmt.Printf("xor_int8 -128%s-1 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(-127); got != 126 { fmt.Printf("xor_int8 -1%s-127 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(-127); got != 126 { fmt.Printf("xor_int8 -127%s-1 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(-1); got != 0 { fmt.Printf("xor_int8 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(-1); got != 0 { fmt.Printf("xor_int8 -1%s-1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(0); got != -1 { fmt.Printf("xor_int8 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(0); got != -1 { fmt.Printf("xor_int8 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(1); got != -2 { fmt.Printf("xor_int8 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(1); got != -2 { fmt.Printf("xor_int8 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(126); got != -127 { fmt.Printf("xor_int8 -1%s126 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(126); got != -127 { fmt.Printf("xor_int8 126%s-1 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_Neg1_int8_ssa(127); got != -128 { fmt.Printf("xor_int8 -1%s127 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_int8_Neg1_ssa(127); got != -128 { fmt.Printf("xor_int8 127%s-1 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_0_int8_ssa(-128); got != -128 { fmt.Printf("xor_int8 0%s-128 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_int8_0_ssa(-128); got != -128 { fmt.Printf("xor_int8 -128%s0 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_0_int8_ssa(-127); got != -127 { fmt.Printf("xor_int8 0%s-127 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_int8_0_ssa(-127); got != -127 { fmt.Printf("xor_int8 -127%s0 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_0_int8_ssa(-1); got != -1 { fmt.Printf("xor_int8 0%s-1 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int8_0_ssa(-1); got != -1 { fmt.Printf("xor_int8 -1%s0 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_0_int8_ssa(0); got != 0 { fmt.Printf("xor_int8 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_0_ssa(0); got != 0 { fmt.Printf("xor_int8 0%s0 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_0_int8_ssa(1); got != 1 { fmt.Printf("xor_int8 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int8_0_ssa(1); got != 1 { fmt.Printf("xor_int8 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_0_int8_ssa(126); got != 126 { fmt.Printf("xor_int8 0%s126 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_int8_0_ssa(126); got != 126 { fmt.Printf("xor_int8 126%s0 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_0_int8_ssa(127); got != 127 { fmt.Printf("xor_int8 0%s127 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_int8_0_ssa(127); got != 127 { fmt.Printf("xor_int8 127%s0 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_1_int8_ssa(-128); got != -127 { fmt.Printf("xor_int8 1%s-128 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_int8_1_ssa(-128); got != -127 { fmt.Printf("xor_int8 -128%s1 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_1_int8_ssa(-127); got != -128 { fmt.Printf("xor_int8 1%s-127 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_int8_1_ssa(-127); got != -128 { fmt.Printf("xor_int8 -127%s1 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_1_int8_ssa(-1); got != -2 { fmt.Printf("xor_int8 1%s-1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int8_1_ssa(-1); got != -2 { fmt.Printf("xor_int8 -1%s1 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_1_int8_ssa(0); got != 1 { fmt.Printf("xor_int8 1%s0 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int8_1_ssa(0); got != 1 { fmt.Printf("xor_int8 0%s1 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_1_int8_ssa(1); got != 0 { fmt.Printf("xor_int8 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_1_ssa(1); got != 0 { fmt.Printf("xor_int8 1%s1 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_1_int8_ssa(126); got != 127 { fmt.Printf("xor_int8 1%s126 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_int8_1_ssa(126); got != 127 { fmt.Printf("xor_int8 126%s1 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_1_int8_ssa(127); got != 126 { fmt.Printf("xor_int8 1%s127 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_int8_1_ssa(127); got != 126 { fmt.Printf("xor_int8 127%s1 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_126_int8_ssa(-128); got != -2 { fmt.Printf("xor_int8 126%s-128 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int8_126_ssa(-128); got != -2 { fmt.Printf("xor_int8 -128%s126 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_126_int8_ssa(-127); got != -1 { fmt.Printf("xor_int8 126%s-127 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int8_126_ssa(-127); got != -1 { fmt.Printf("xor_int8 -127%s126 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_126_int8_ssa(-1); got != -127 { fmt.Printf("xor_int8 126%s-1 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_int8_126_ssa(-1); got != -127 { fmt.Printf("xor_int8 -1%s126 = %d, wanted -127\n", `^`, got) failed = true } if got := xor_126_int8_ssa(0); got != 126 { fmt.Printf("xor_int8 126%s0 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_int8_126_ssa(0); got != 126 { fmt.Printf("xor_int8 0%s126 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_126_int8_ssa(1); got != 127 { fmt.Printf("xor_int8 126%s1 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_int8_126_ssa(1); got != 127 { fmt.Printf("xor_int8 1%s126 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_126_int8_ssa(126); got != 0 { fmt.Printf("xor_int8 126%s126 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_126_ssa(126); got != 0 { fmt.Printf("xor_int8 126%s126 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_126_int8_ssa(127); got != 1 { fmt.Printf("xor_int8 126%s127 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int8_126_ssa(127); got != 1 { fmt.Printf("xor_int8 127%s126 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_127_int8_ssa(-128); got != -1 { fmt.Printf("xor_int8 127%s-128 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_int8_127_ssa(-128); got != -1 { fmt.Printf("xor_int8 -128%s127 = %d, wanted -1\n", `^`, got) failed = true } if got := xor_127_int8_ssa(-127); got != -2 { fmt.Printf("xor_int8 127%s-127 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_int8_127_ssa(-127); got != -2 { fmt.Printf("xor_int8 -127%s127 = %d, wanted -2\n", `^`, got) failed = true } if got := xor_127_int8_ssa(-1); got != -128 { fmt.Printf("xor_int8 127%s-1 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_int8_127_ssa(-1); got != -128 { fmt.Printf("xor_int8 -1%s127 = %d, wanted -128\n", `^`, got) failed = true } if got := xor_127_int8_ssa(0); got != 127 { fmt.Printf("xor_int8 127%s0 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_int8_127_ssa(0); got != 127 { fmt.Printf("xor_int8 0%s127 = %d, wanted 127\n", `^`, got) failed = true } if got := xor_127_int8_ssa(1); got != 126 { fmt.Printf("xor_int8 127%s1 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_int8_127_ssa(1); got != 126 { fmt.Printf("xor_int8 1%s127 = %d, wanted 126\n", `^`, got) failed = true } if got := xor_127_int8_ssa(126); got != 1 { fmt.Printf("xor_int8 127%s126 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_int8_127_ssa(126); got != 1 { fmt.Printf("xor_int8 126%s127 = %d, wanted 1\n", `^`, got) failed = true } if got := xor_127_int8_ssa(127); got != 0 { fmt.Printf("xor_int8 127%s127 = %d, wanted 0\n", `^`, got) failed = true } if got := xor_int8_127_ssa(127); got != 0 { fmt.Printf("xor_int8 127%s127 = %d, wanted 0\n", `^`, got) failed = true } if failed { panic("tests failed") } } -- y -- // run // Code generated by gen/arithConstGen.go. DO NOT EDIT. package main import "fmt" import "os" //go:noinline func add_uint64_0(a uint64) uint64 { return a + 0 } //go:noinline func add_0_uint64(a uint64) uint64 { return 0 + a } //go:noinline func add_uint64_1(a uint64) uint64 { return a + 1 } //go:noinline func add_1_uint64(a uint64) uint64 { return 1 + a } //go:noinline func add_uint64_4294967296(a uint64) uint64 { return a + 4294967296 } //go:noinline func add_4294967296_uint64(a uint64) uint64 { return 4294967296 + a } //go:noinline func add_uint64_9223372036854775808(a uint64) uint64 { return a + 9223372036854775808 } //go:noinline func add_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 + a } //go:noinline func add_uint64_18446744073709551615(a uint64) uint64 { return a + 18446744073709551615 } //go:noinline func add_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 + a } //go:noinline func sub_uint64_0(a uint64) uint64 { return a - 0 } //go:noinline func sub_0_uint64(a uint64) uint64 { return 0 - a } //go:noinline func sub_uint64_1(a uint64) uint64 { return a - 1 } //go:noinline func sub_1_uint64(a uint64) uint64 { return 1 - a } //go:noinline func sub_uint64_4294967296(a uint64) uint64 { return a - 4294967296 } //go:noinline func sub_4294967296_uint64(a uint64) uint64 { return 4294967296 - a } //go:noinline func sub_uint64_9223372036854775808(a uint64) uint64 { return a - 9223372036854775808 } //go:noinline func sub_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 - a } //go:noinline func sub_uint64_18446744073709551615(a uint64) uint64 { return a - 18446744073709551615 } //go:noinline func sub_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 - a } //go:noinline func div_0_uint64(a uint64) uint64 { return 0 / a } //go:noinline func div_uint64_1(a uint64) uint64 { return a / 1 } //go:noinline func div_1_uint64(a uint64) uint64 { return 1 / a } //go:noinline func div_uint64_4294967296(a uint64) uint64 { return a / 4294967296 } //go:noinline func div_4294967296_uint64(a uint64) uint64 { return 4294967296 / a } //go:noinline func div_uint64_9223372036854775808(a uint64) uint64 { return a / 9223372036854775808 } //go:noinline func div_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 / a } //go:noinline func div_uint64_18446744073709551615(a uint64) uint64 { return a / 18446744073709551615 } //go:noinline func div_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 / a } //go:noinline func mul_uint64_0(a uint64) uint64 { return a * 0 } //go:noinline func mul_0_uint64(a uint64) uint64 { return 0 * a } //go:noinline func mul_uint64_1(a uint64) uint64 { return a * 1 } //go:noinline func mul_1_uint64(a uint64) uint64 { return 1 * a } //go:noinline func mul_uint64_4294967296(a uint64) uint64 { return a * 4294967296 } //go:noinline func mul_4294967296_uint64(a uint64) uint64 { return 4294967296 * a } //go:noinline func mul_uint64_9223372036854775808(a uint64) uint64 { return a * 9223372036854775808 } //go:noinline func mul_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 * a } //go:noinline func mul_uint64_18446744073709551615(a uint64) uint64 { return a * 18446744073709551615 } //go:noinline func mul_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 * a } //go:noinline func lsh_uint64_0(a uint64) uint64 { return a << 0 } //go:noinline func lsh_0_uint64(a uint64) uint64 { return 0 << a } //go:noinline func lsh_uint64_1(a uint64) uint64 { return a << 1 } //go:noinline func lsh_1_uint64(a uint64) uint64 { return 1 << a } //go:noinline func lsh_uint64_4294967296(a uint64) uint64 { return a << uint64(4294967296) } //go:noinline func lsh_4294967296_uint64(a uint64) uint64 { return 4294967296 << a } //go:noinline func lsh_uint64_9223372036854775808(a uint64) uint64 { return a << uint64(9223372036854775808) } //go:noinline func lsh_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 << a } //go:noinline func lsh_uint64_18446744073709551615(a uint64) uint64 { return a << uint64(18446744073709551615) } //go:noinline func lsh_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 << a } //go:noinline func rsh_uint64_0(a uint64) uint64 { return a >> 0 } //go:noinline func rsh_0_uint64(a uint64) uint64 { return 0 >> a } //go:noinline func rsh_uint64_1(a uint64) uint64 { return a >> 1 } //go:noinline func rsh_1_uint64(a uint64) uint64 { return 1 >> a } //go:noinline func rsh_uint64_4294967296(a uint64) uint64 { return a >> uint64(4294967296) } //go:noinline func rsh_4294967296_uint64(a uint64) uint64 { return 4294967296 >> a } //go:noinline func rsh_uint64_9223372036854775808(a uint64) uint64 { return a >> uint64(9223372036854775808) } //go:noinline func rsh_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 >> a } //go:noinline func rsh_uint64_18446744073709551615(a uint64) uint64 { return a >> uint64(18446744073709551615) } //go:noinline func rsh_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 >> a } //go:noinline func mod_0_uint64(a uint64) uint64 { return 0 % a } //go:noinline func mod_uint64_1(a uint64) uint64 { return a % 1 } //go:noinline func mod_1_uint64(a uint64) uint64 { return 1 % a } //go:noinline func mod_uint64_4294967296(a uint64) uint64 { return a % 4294967296 } //go:noinline func mod_4294967296_uint64(a uint64) uint64 { return 4294967296 % a } //go:noinline func mod_uint64_9223372036854775808(a uint64) uint64 { return a % 9223372036854775808 } //go:noinline func mod_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 % a } //go:noinline func mod_uint64_18446744073709551615(a uint64) uint64 { return a % 18446744073709551615 } //go:noinline func mod_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 % a } //go:noinline func and_uint64_0(a uint64) uint64 { return a & 0 } //go:noinline func and_0_uint64(a uint64) uint64 { return 0 & a } //go:noinline func and_uint64_1(a uint64) uint64 { return a & 1 } //go:noinline func and_1_uint64(a uint64) uint64 { return 1 & a } //go:noinline func and_uint64_4294967296(a uint64) uint64 { return a & 4294967296 } //go:noinline func and_4294967296_uint64(a uint64) uint64 { return 4294967296 & a } //go:noinline func and_uint64_9223372036854775808(a uint64) uint64 { return a & 9223372036854775808 } //go:noinline func and_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 & a } //go:noinline func and_uint64_18446744073709551615(a uint64) uint64 { return a & 18446744073709551615 } //go:noinline func and_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 & a } //go:noinline func or_uint64_0(a uint64) uint64 { return a | 0 } //go:noinline func or_0_uint64(a uint64) uint64 { return 0 | a } //go:noinline func or_uint64_1(a uint64) uint64 { return a | 1 } //go:noinline func or_1_uint64(a uint64) uint64 { return 1 | a } //go:noinline func or_uint64_4294967296(a uint64) uint64 { return a | 4294967296 } //go:noinline func or_4294967296_uint64(a uint64) uint64 { return 4294967296 | a } //go:noinline func or_uint64_9223372036854775808(a uint64) uint64 { return a | 9223372036854775808 } //go:noinline func or_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 | a } //go:noinline func or_uint64_18446744073709551615(a uint64) uint64 { return a | 18446744073709551615 } //go:noinline func or_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 | a } //go:noinline func xor_uint64_0(a uint64) uint64 { return a ^ 0 } //go:noinline func xor_0_uint64(a uint64) uint64 { return 0 ^ a } //go:noinline func xor_uint64_1(a uint64) uint64 { return a ^ 1 } //go:noinline func xor_1_uint64(a uint64) uint64 { return 1 ^ a } //go:noinline func xor_uint64_4294967296(a uint64) uint64 { return a ^ 4294967296 } //go:noinline func xor_4294967296_uint64(a uint64) uint64 { return 4294967296 ^ a } //go:noinline func xor_uint64_9223372036854775808(a uint64) uint64 { return a ^ 9223372036854775808 } //go:noinline func xor_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 ^ a } //go:noinline func xor_uint64_18446744073709551615(a uint64) uint64 { return a ^ 18446744073709551615 } //go:noinline func xor_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 ^ a } //go:noinline func add_int64_Neg9223372036854775808(a int64) int64 { return a + -9223372036854775808 } //go:noinline func add_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 + a } //go:noinline func add_int64_Neg9223372036854775807(a int64) int64 { return a + -9223372036854775807 } //go:noinline func add_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 + a } //go:noinline func add_int64_Neg4294967296(a int64) int64 { return a + -4294967296 } //go:noinline func add_Neg4294967296_int64(a int64) int64 { return -4294967296 + a } //go:noinline func add_int64_Neg1(a int64) int64 { return a + -1 } //go:noinline func add_Neg1_int64(a int64) int64 { return -1 + a } //go:noinline func add_int64_0(a int64) int64 { return a + 0 } //go:noinline func add_0_int64(a int64) int64 { return 0 + a } //go:noinline func add_int64_1(a int64) int64 { return a + 1 } //go:noinline func add_1_int64(a int64) int64 { return 1 + a } //go:noinline func add_int64_4294967296(a int64) int64 { return a + 4294967296 } //go:noinline func add_4294967296_int64(a int64) int64 { return 4294967296 + a } //go:noinline func add_int64_9223372036854775806(a int64) int64 { return a + 9223372036854775806 } //go:noinline func add_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 + a } //go:noinline func add_int64_9223372036854775807(a int64) int64 { return a + 9223372036854775807 } //go:noinline func add_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 + a } //go:noinline func sub_int64_Neg9223372036854775808(a int64) int64 { return a - -9223372036854775808 } //go:noinline func sub_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 - a } //go:noinline func sub_int64_Neg9223372036854775807(a int64) int64 { return a - -9223372036854775807 } //go:noinline func sub_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 - a } //go:noinline func sub_int64_Neg4294967296(a int64) int64 { return a - -4294967296 } //go:noinline func sub_Neg4294967296_int64(a int64) int64 { return -4294967296 - a } //go:noinline func sub_int64_Neg1(a int64) int64 { return a - -1 } //go:noinline func sub_Neg1_int64(a int64) int64 { return -1 - a } //go:noinline func sub_int64_0(a int64) int64 { return a - 0 } //go:noinline func sub_0_int64(a int64) int64 { return 0 - a } //go:noinline func sub_int64_1(a int64) int64 { return a - 1 } //go:noinline func sub_1_int64(a int64) int64 { return 1 - a } //go:noinline func sub_int64_4294967296(a int64) int64 { return a - 4294967296 } //go:noinline func sub_4294967296_int64(a int64) int64 { return 4294967296 - a } //go:noinline func sub_int64_9223372036854775806(a int64) int64 { return a - 9223372036854775806 } //go:noinline func sub_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 - a } //go:noinline func sub_int64_9223372036854775807(a int64) int64 { return a - 9223372036854775807 } //go:noinline func sub_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 - a } //go:noinline func div_int64_Neg9223372036854775808(a int64) int64 { return a / -9223372036854775808 } //go:noinline func div_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 / a } //go:noinline func div_int64_Neg9223372036854775807(a int64) int64 { return a / -9223372036854775807 } //go:noinline func div_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 / a } //go:noinline func div_int64_Neg4294967296(a int64) int64 { return a / -4294967296 } //go:noinline func div_Neg4294967296_int64(a int64) int64 { return -4294967296 / a } //go:noinline func div_int64_Neg1(a int64) int64 { return a / -1 } //go:noinline func div_Neg1_int64(a int64) int64 { return -1 / a } //go:noinline func div_0_int64(a int64) int64 { return 0 / a } //go:noinline func div_int64_1(a int64) int64 { return a / 1 } //go:noinline func div_1_int64(a int64) int64 { return 1 / a } //go:noinline func div_int64_4294967296(a int64) int64 { return a / 4294967296 } //go:noinline func div_4294967296_int64(a int64) int64 { return 4294967296 / a } //go:noinline func div_int64_9223372036854775806(a int64) int64 { return a / 9223372036854775806 } //go:noinline func div_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 / a } //go:noinline func div_int64_9223372036854775807(a int64) int64 { return a / 9223372036854775807 } //go:noinline func div_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 / a } //go:noinline func mul_int64_Neg9223372036854775808(a int64) int64 { return a * -9223372036854775808 } //go:noinline func mul_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 * a } //go:noinline func mul_int64_Neg9223372036854775807(a int64) int64 { return a * -9223372036854775807 } //go:noinline func mul_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 * a } //go:noinline func mul_int64_Neg4294967296(a int64) int64 { return a * -4294967296 } //go:noinline func mul_Neg4294967296_int64(a int64) int64 { return -4294967296 * a } //go:noinline func mul_int64_Neg1(a int64) int64 { return a * -1 } //go:noinline func mul_Neg1_int64(a int64) int64 { return -1 * a } //go:noinline func mul_int64_0(a int64) int64 { return a * 0 } //go:noinline func mul_0_int64(a int64) int64 { return 0 * a } //go:noinline func mul_int64_1(a int64) int64 { return a * 1 } //go:noinline func mul_1_int64(a int64) int64 { return 1 * a } //go:noinline func mul_int64_4294967296(a int64) int64 { return a * 4294967296 } //go:noinline func mul_4294967296_int64(a int64) int64 { return 4294967296 * a } //go:noinline func mul_int64_9223372036854775806(a int64) int64 { return a * 9223372036854775806 } //go:noinline func mul_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 * a } //go:noinline func mul_int64_9223372036854775807(a int64) int64 { return a * 9223372036854775807 } //go:noinline func mul_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 * a } //go:noinline func mod_int64_Neg9223372036854775808(a int64) int64 { return a % -9223372036854775808 } //go:noinline func mod_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 % a } //go:noinline func mod_int64_Neg9223372036854775807(a int64) int64 { return a % -9223372036854775807 } //go:noinline func mod_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 % a } //go:noinline func mod_int64_Neg4294967296(a int64) int64 { return a % -4294967296 } //go:noinline func mod_Neg4294967296_int64(a int64) int64 { return -4294967296 % a } //go:noinline func mod_int64_Neg1(a int64) int64 { return a % -1 } //go:noinline func mod_Neg1_int64(a int64) int64 { return -1 % a } //go:noinline func mod_0_int64(a int64) int64 { return 0 % a } //go:noinline func mod_int64_1(a int64) int64 { return a % 1 } //go:noinline func mod_1_int64(a int64) int64 { return 1 % a } //go:noinline func mod_int64_4294967296(a int64) int64 { return a % 4294967296 } //go:noinline func mod_4294967296_int64(a int64) int64 { return 4294967296 % a } //go:noinline func mod_int64_9223372036854775806(a int64) int64 { return a % 9223372036854775806 } //go:noinline func mod_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 % a } //go:noinline func mod_int64_9223372036854775807(a int64) int64 { return a % 9223372036854775807 } //go:noinline func mod_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 % a } //go:noinline func and_int64_Neg9223372036854775808(a int64) int64 { return a & -9223372036854775808 } //go:noinline func and_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 & a } //go:noinline func and_int64_Neg9223372036854775807(a int64) int64 { return a & -9223372036854775807 } //go:noinline func and_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 & a } //go:noinline func and_int64_Neg4294967296(a int64) int64 { return a & -4294967296 } //go:noinline func and_Neg4294967296_int64(a int64) int64 { return -4294967296 & a } //go:noinline func and_int64_Neg1(a int64) int64 { return a & -1 } //go:noinline func and_Neg1_int64(a int64) int64 { return -1 & a } //go:noinline func and_int64_0(a int64) int64 { return a & 0 } //go:noinline func and_0_int64(a int64) int64 { return 0 & a } //go:noinline func and_int64_1(a int64) int64 { return a & 1 } //go:noinline func and_1_int64(a int64) int64 { return 1 & a } //go:noinline func and_int64_4294967296(a int64) int64 { return a & 4294967296 } //go:noinline func and_4294967296_int64(a int64) int64 { return 4294967296 & a } //go:noinline func and_int64_9223372036854775806(a int64) int64 { return a & 9223372036854775806 } //go:noinline func and_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 & a } //go:noinline func and_int64_9223372036854775807(a int64) int64 { return a & 9223372036854775807 } //go:noinline func and_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 & a } //go:noinline func or_int64_Neg9223372036854775808(a int64) int64 { return a | -9223372036854775808 } //go:noinline func or_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 | a } //go:noinline func or_int64_Neg9223372036854775807(a int64) int64 { return a | -9223372036854775807 } //go:noinline func or_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 | a } //go:noinline func or_int64_Neg4294967296(a int64) int64 { return a | -4294967296 } //go:noinline func or_Neg4294967296_int64(a int64) int64 { return -4294967296 | a } //go:noinline func or_int64_Neg1(a int64) int64 { return a | -1 } //go:noinline func or_Neg1_int64(a int64) int64 { return -1 | a } //go:noinline func or_int64_0(a int64) int64 { return a | 0 } //go:noinline func or_0_int64(a int64) int64 { return 0 | a } //go:noinline func or_int64_1(a int64) int64 { return a | 1 } //go:noinline func or_1_int64(a int64) int64 { return 1 | a } //go:noinline func or_int64_4294967296(a int64) int64 { return a | 4294967296 } //go:noinline func or_4294967296_int64(a int64) int64 { return 4294967296 | a } //go:noinline func or_int64_9223372036854775806(a int64) int64 { return a | 9223372036854775806 } //go:noinline func or_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 | a } //go:noinline func or_int64_9223372036854775807(a int64) int64 { return a | 9223372036854775807 } //go:noinline func or_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 | a } //go:noinline func xor_int64_Neg9223372036854775808(a int64) int64 { return a ^ -9223372036854775808 } //go:noinline func xor_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 ^ a } //go:noinline func xor_int64_Neg9223372036854775807(a int64) int64 { return a ^ -9223372036854775807 } //go:noinline func xor_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 ^ a } //go:noinline func xor_int64_Neg4294967296(a int64) int64 { return a ^ -4294967296 } //go:noinline func xor_Neg4294967296_int64(a int64) int64 { return -4294967296 ^ a } //go:noinline func xor_int64_Neg1(a int64) int64 { return a ^ -1 } //go:noinline func xor_Neg1_int64(a int64) int64 { return -1 ^ a } //go:noinline func xor_int64_0(a int64) int64 { return a ^ 0 } //go:noinline func xor_0_int64(a int64) int64 { return 0 ^ a } //go:noinline func xor_int64_1(a int64) int64 { return a ^ 1 } //go:noinline func xor_1_int64(a int64) int64 { return 1 ^ a } //go:noinline func xor_int64_4294967296(a int64) int64 { return a ^ 4294967296 } //go:noinline func xor_4294967296_int64(a int64) int64 { return 4294967296 ^ a } //go:noinline func xor_int64_9223372036854775806(a int64) int64 { return a ^ 9223372036854775806 } //go:noinline func xor_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 ^ a } //go:noinline func xor_int64_9223372036854775807(a int64) int64 { return a ^ 9223372036854775807 } //go:noinline func xor_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 ^ a } //go:noinline func add_uint32_0(a uint32) uint32 { return a + 0 } //go:noinline func add_0_uint32(a uint32) uint32 { return 0 + a } //go:noinline func add_uint32_1(a uint32) uint32 { return a + 1 } //go:noinline func add_1_uint32(a uint32) uint32 { return 1 + a } //go:noinline func add_uint32_4294967295(a uint32) uint32 { return a + 4294967295 } //go:noinline func add_4294967295_uint32(a uint32) uint32 { return 4294967295 + a } //go:noinline func sub_uint32_0(a uint32) uint32 { return a - 0 } //go:noinline func sub_0_uint32(a uint32) uint32 { return 0 - a } //go:noinline func sub_uint32_1(a uint32) uint32 { return a - 1 } //go:noinline func sub_1_uint32(a uint32) uint32 { return 1 - a } //go:noinline func sub_uint32_4294967295(a uint32) uint32 { return a - 4294967295 } //go:noinline func sub_4294967295_uint32(a uint32) uint32 { return 4294967295 - a } //go:noinline func div_0_uint32(a uint32) uint32 { return 0 / a } //go:noinline func div_uint32_1(a uint32) uint32 { return a / 1 } //go:noinline func div_1_uint32(a uint32) uint32 { return 1 / a } //go:noinline func div_uint32_4294967295(a uint32) uint32 { return a / 4294967295 } //go:noinline func div_4294967295_uint32(a uint32) uint32 { return 4294967295 / a } //go:noinline func mul_uint32_0(a uint32) uint32 { return a * 0 } //go:noinline func mul_0_uint32(a uint32) uint32 { return 0 * a } //go:noinline func mul_uint32_1(a uint32) uint32 { return a * 1 } //go:noinline func mul_1_uint32(a uint32) uint32 { return 1 * a } //go:noinline func mul_uint32_4294967295(a uint32) uint32 { return a * 4294967295 } //go:noinline func mul_4294967295_uint32(a uint32) uint32 { return 4294967295 * a } //go:noinline func lsh_uint32_0(a uint32) uint32 { return a << 0 } //go:noinline func lsh_0_uint32(a uint32) uint32 { return 0 << a } //go:noinline func lsh_uint32_1(a uint32) uint32 { return a << 1 } //go:noinline func lsh_1_uint32(a uint32) uint32 { return 1 << a } //go:noinline func lsh_uint32_4294967295(a uint32) uint32 { return a << 4294967295 } //go:noinline func lsh_4294967295_uint32(a uint32) uint32 { return 4294967295 << a } //go:noinline func rsh_uint32_0(a uint32) uint32 { return a >> 0 } //go:noinline func rsh_0_uint32(a uint32) uint32 { return 0 >> a } //go:noinline func rsh_uint32_1(a uint32) uint32 { return a >> 1 } //go:noinline func rsh_1_uint32(a uint32) uint32 { return 1 >> a } //go:noinline func rsh_uint32_4294967295(a uint32) uint32 { return a >> 4294967295 } //go:noinline func rsh_4294967295_uint32(a uint32) uint32 { return 4294967295 >> a } //go:noinline func mod_0_uint32(a uint32) uint32 { return 0 % a } //go:noinline func mod_uint32_1(a uint32) uint32 { return a % 1 } //go:noinline func mod_1_uint32(a uint32) uint32 { return 1 % a } //go:noinline func mod_uint32_4294967295(a uint32) uint32 { return a % 4294967295 } //go:noinline func mod_4294967295_uint32(a uint32) uint32 { return 4294967295 % a } //go:noinline func and_uint32_0(a uint32) uint32 { return a & 0 } //go:noinline func and_0_uint32(a uint32) uint32 { return 0 & a } //go:noinline func and_uint32_1(a uint32) uint32 { return a & 1 } //go:noinline func and_1_uint32(a uint32) uint32 { return 1 & a } //go:noinline func and_uint32_4294967295(a uint32) uint32 { return a & 4294967295 } //go:noinline func and_4294967295_uint32(a uint32) uint32 { return 4294967295 & a } //go:noinline func or_uint32_0(a uint32) uint32 { return a | 0 } //go:noinline func or_0_uint32(a uint32) uint32 { return 0 | a } //go:noinline func or_uint32_1(a uint32) uint32 { return a | 1 } //go:noinline func or_1_uint32(a uint32) uint32 { return 1 | a } //go:noinline func or_uint32_4294967295(a uint32) uint32 { return a | 4294967295 } //go:noinline func or_4294967295_uint32(a uint32) uint32 { return 4294967295 | a } //go:noinline func xor_uint32_0(a uint32) uint32 { return a ^ 0 } //go:noinline func xor_0_uint32(a uint32) uint32 { return 0 ^ a } //go:noinline func xor_uint32_1(a uint32) uint32 { return a ^ 1 } //go:noinline func xor_1_uint32(a uint32) uint32 { return 1 ^ a } //go:noinline func xor_uint32_4294967295(a uint32) uint32 { return a ^ 4294967295 } //go:noinline func xor_4294967295_uint32(a uint32) uint32 { return 4294967295 ^ a } //go:noinline func add_int32_Neg2147483648(a int32) int32 { return a + -2147483648 } //go:noinline func add_Neg2147483648_int32(a int32) int32 { return -2147483648 + a } //go:noinline func add_int32_Neg2147483647(a int32) int32 { return a + -2147483647 } //go:noinline func add_Neg2147483647_int32(a int32) int32 { return -2147483647 + a } //go:noinline func add_int32_Neg1(a int32) int32 { return a + -1 } //go:noinline func add_Neg1_int32(a int32) int32 { return -1 + a } //go:noinline func add_int32_0(a int32) int32 { return a + 0 } //go:noinline func add_0_int32(a int32) int32 { return 0 + a } //go:noinline func add_int32_1(a int32) int32 { return a + 1 } //go:noinline func add_1_int32(a int32) int32 { return 1 + a } //go:noinline func add_int32_2147483647(a int32) int32 { return a + 2147483647 } //go:noinline func add_2147483647_int32(a int32) int32 { return 2147483647 + a } //go:noinline func sub_int32_Neg2147483648(a int32) int32 { return a - -2147483648 } //go:noinline func sub_Neg2147483648_int32(a int32) int32 { return -2147483648 - a } //go:noinline func sub_int32_Neg2147483647(a int32) int32 { return a - -2147483647 } //go:noinline func sub_Neg2147483647_int32(a int32) int32 { return -2147483647 - a } //go:noinline func sub_int32_Neg1(a int32) int32 { return a - -1 } //go:noinline func sub_Neg1_int32(a int32) int32 { return -1 - a } //go:noinline func sub_int32_0(a int32) int32 { return a - 0 } //go:noinline func sub_0_int32(a int32) int32 { return 0 - a } //go:noinline func sub_int32_1(a int32) int32 { return a - 1 } //go:noinline func sub_1_int32(a int32) int32 { return 1 - a } //go:noinline func sub_int32_2147483647(a int32) int32 { return a - 2147483647 } //go:noinline func sub_2147483647_int32(a int32) int32 { return 2147483647 - a } //go:noinline func div_int32_Neg2147483648(a int32) int32 { return a / -2147483648 } //go:noinline func div_Neg2147483648_int32(a int32) int32 { return -2147483648 / a } //go:noinline func div_int32_Neg2147483647(a int32) int32 { return a / -2147483647 } //go:noinline func div_Neg2147483647_int32(a int32) int32 { return -2147483647 / a } //go:noinline func div_int32_Neg1(a int32) int32 { return a / -1 } //go:noinline func div_Neg1_int32(a int32) int32 { return -1 / a } //go:noinline func div_0_int32(a int32) int32 { return 0 / a } //go:noinline func div_int32_1(a int32) int32 { return a / 1 } //go:noinline func div_1_int32(a int32) int32 { return 1 / a } //go:noinline func div_int32_2147483647(a int32) int32 { return a / 2147483647 } //go:noinline func div_2147483647_int32(a int32) int32 { return 2147483647 / a } //go:noinline func mul_int32_Neg2147483648(a int32) int32 { return a * -2147483648 } //go:noinline func mul_Neg2147483648_int32(a int32) int32 { return -2147483648 * a } //go:noinline func mul_int32_Neg2147483647(a int32) int32 { return a * -2147483647 } //go:noinline func mul_Neg2147483647_int32(a int32) int32 { return -2147483647 * a } //go:noinline func mul_int32_Neg1(a int32) int32 { return a * -1 } //go:noinline func mul_Neg1_int32(a int32) int32 { return -1 * a } //go:noinline func mul_int32_0(a int32) int32 { return a * 0 } //go:noinline func mul_0_int32(a int32) int32 { return 0 * a } //go:noinline func mul_int32_1(a int32) int32 { return a * 1 } //go:noinline func mul_1_int32(a int32) int32 { return 1 * a } //go:noinline func mul_int32_2147483647(a int32) int32 { return a * 2147483647 } //go:noinline func mul_2147483647_int32(a int32) int32 { return 2147483647 * a } //go:noinline func mod_int32_Neg2147483648(a int32) int32 { return a % -2147483648 } //go:noinline func mod_Neg2147483648_int32(a int32) int32 { return -2147483648 % a } //go:noinline func mod_int32_Neg2147483647(a int32) int32 { return a % -2147483647 } //go:noinline func mod_Neg2147483647_int32(a int32) int32 { return -2147483647 % a } //go:noinline func mod_int32_Neg1(a int32) int32 { return a % -1 } //go:noinline func mod_Neg1_int32(a int32) int32 { return -1 % a } //go:noinline func mod_0_int32(a int32) int32 { return 0 % a } //go:noinline func mod_int32_1(a int32) int32 { return a % 1 } //go:noinline func mod_1_int32(a int32) int32 { return 1 % a } //go:noinline func mod_int32_2147483647(a int32) int32 { return a % 2147483647 } //go:noinline func mod_2147483647_int32(a int32) int32 { return 2147483647 % a } //go:noinline func and_int32_Neg2147483648(a int32) int32 { return a & -2147483648 } //go:noinline func and_Neg2147483648_int32(a int32) int32 { return -2147483648 & a } //go:noinline func and_int32_Neg2147483647(a int32) int32 { return a & -2147483647 } //go:noinline func and_Neg2147483647_int32(a int32) int32 { return -2147483647 & a } //go:noinline func and_int32_Neg1(a int32) int32 { return a & -1 } //go:noinline func and_Neg1_int32(a int32) int32 { return -1 & a } //go:noinline func and_int32_0(a int32) int32 { return a & 0 } //go:noinline func and_0_int32(a int32) int32 { return 0 & a } //go:noinline func and_int32_1(a int32) int32 { return a & 1 } //go:noinline func and_1_int32(a int32) int32 { return 1 & a } //go:noinline func and_int32_2147483647(a int32) int32 { return a & 2147483647 } //go:noinline func and_2147483647_int32(a int32) int32 { return 2147483647 & a } //go:noinline func or_int32_Neg2147483648(a int32) int32 { return a | -2147483648 } //go:noinline func or_Neg2147483648_int32(a int32) int32 { return -2147483648 | a } //go:noinline func or_int32_Neg2147483647(a int32) int32 { return a | -2147483647 } //go:noinline func or_Neg2147483647_int32(a int32) int32 { return -2147483647 | a } //go:noinline func or_int32_Neg1(a int32) int32 { return a | -1 } //go:noinline func or_Neg1_int32(a int32) int32 { return -1 | a } //go:noinline func or_int32_0(a int32) int32 { return a | 0 } //go:noinline func or_0_int32(a int32) int32 { return 0 | a } //go:noinline func or_int32_1(a int32) int32 { return a | 1 } //go:noinline func or_1_int32(a int32) int32 { return 1 | a } //go:noinline func or_int32_2147483647(a int32) int32 { return a | 2147483647 } //go:noinline func or_2147483647_int32(a int32) int32 { return 2147483647 | a } //go:noinline func xor_int32_Neg2147483648(a int32) int32 { return a ^ -2147483648 } //go:noinline func xor_Neg2147483648_int32(a int32) int32 { return -2147483648 ^ a } //go:noinline func xor_int32_Neg2147483647(a int32) int32 { return a ^ -2147483647 } //go:noinline func xor_Neg2147483647_int32(a int32) int32 { return -2147483647 ^ a } //go:noinline func xor_int32_Neg1(a int32) int32 { return a ^ -1 } //go:noinline func xor_Neg1_int32(a int32) int32 { return -1 ^ a } //go:noinline func xor_int32_0(a int32) int32 { return a ^ 0 } //go:noinline func xor_0_int32(a int32) int32 { return 0 ^ a } //go:noinline func xor_int32_1(a int32) int32 { return a ^ 1 } //go:noinline func xor_1_int32(a int32) int32 { return 1 ^ a } //go:noinline func xor_int32_2147483647(a int32) int32 { return a ^ 2147483647 } //go:noinline func xor_2147483647_int32(a int32) int32 { return 2147483647 ^ a } //go:noinline func add_uint16_0(a uint16) uint16 { return a + 0 } //go:noinline func add_0_uint16(a uint16) uint16 { return 0 + a } //go:noinline func add_uint16_1(a uint16) uint16 { return a + 1 } //go:noinline func add_1_uint16(a uint16) uint16 { return 1 + a } //go:noinline func add_uint16_65535(a uint16) uint16 { return a + 65535 } //go:noinline func add_65535_uint16(a uint16) uint16 { return 65535 + a } //go:noinline func sub_uint16_0(a uint16) uint16 { return a - 0 } //go:noinline func sub_0_uint16(a uint16) uint16 { return 0 - a } //go:noinline func sub_uint16_1(a uint16) uint16 { return a - 1 } //go:noinline func sub_1_uint16(a uint16) uint16 { return 1 - a } //go:noinline func sub_uint16_65535(a uint16) uint16 { return a - 65535 } //go:noinline func sub_65535_uint16(a uint16) uint16 { return 65535 - a } //go:noinline func div_0_uint16(a uint16) uint16 { return 0 / a } //go:noinline func div_uint16_1(a uint16) uint16 { return a / 1 } //go:noinline func div_1_uint16(a uint16) uint16 { return 1 / a } //go:noinline func div_uint16_65535(a uint16) uint16 { return a / 65535 } //go:noinline func div_65535_uint16(a uint16) uint16 { return 65535 / a } //go:noinline func mul_uint16_0(a uint16) uint16 { return a * 0 } //go:noinline func mul_0_uint16(a uint16) uint16 { return 0 * a } //go:noinline func mul_uint16_1(a uint16) uint16 { return a * 1 } //go:noinline func mul_1_uint16(a uint16) uint16 { return 1 * a } //go:noinline func mul_uint16_65535(a uint16) uint16 { return a * 65535 } //go:noinline func mul_65535_uint16(a uint16) uint16 { return 65535 * a } //go:noinline func lsh_uint16_0(a uint16) uint16 { return a << 0 } //go:noinline func lsh_0_uint16(a uint16) uint16 { return 0 << a } //go:noinline func lsh_uint16_1(a uint16) uint16 { return a << 1 } //go:noinline func lsh_1_uint16(a uint16) uint16 { return 1 << a } //go:noinline func lsh_uint16_65535(a uint16) uint16 { return a << 65535 } //go:noinline func lsh_65535_uint16(a uint16) uint16 { return 65535 << a } //go:noinline func rsh_uint16_0(a uint16) uint16 { return a >> 0 } //go:noinline func rsh_0_uint16(a uint16) uint16 { return 0 >> a } //go:noinline func rsh_uint16_1(a uint16) uint16 { return a >> 1 } //go:noinline func rsh_1_uint16(a uint16) uint16 { return 1 >> a } //go:noinline func rsh_uint16_65535(a uint16) uint16 { return a >> 65535 } //go:noinline func rsh_65535_uint16(a uint16) uint16 { return 65535 >> a } //go:noinline func mod_0_uint16(a uint16) uint16 { return 0 % a } //go:noinline func mod_uint16_1(a uint16) uint16 { return a % 1 } //go:noinline func mod_1_uint16(a uint16) uint16 { return 1 % a } //go:noinline func mod_uint16_65535(a uint16) uint16 { return a % 65535 } //go:noinline func mod_65535_uint16(a uint16) uint16 { return 65535 % a } //go:noinline func and_uint16_0(a uint16) uint16 { return a & 0 } //go:noinline func and_0_uint16(a uint16) uint16 { return 0 & a } //go:noinline func and_uint16_1(a uint16) uint16 { return a & 1 } //go:noinline func and_1_uint16(a uint16) uint16 { return 1 & a } //go:noinline func and_uint16_65535(a uint16) uint16 { return a & 65535 } //go:noinline func and_65535_uint16(a uint16) uint16 { return 65535 & a } //go:noinline func or_uint16_0(a uint16) uint16 { return a | 0 } //go:noinline func or_0_uint16(a uint16) uint16 { return 0 | a } //go:noinline func or_uint16_1(a uint16) uint16 { return a | 1 } //go:noinline func or_1_uint16(a uint16) uint16 { return 1 | a } //go:noinline func or_uint16_65535(a uint16) uint16 { return a | 65535 } //go:noinline func or_65535_uint16(a uint16) uint16 { return 65535 | a } //go:noinline func xor_uint16_0(a uint16) uint16 { return a ^ 0 } //go:noinline func xor_0_uint16(a uint16) uint16 { return 0 ^ a } //go:noinline func xor_uint16_1(a uint16) uint16 { return a ^ 1 } //go:noinline func xor_1_uint16(a uint16) uint16 { return 1 ^ a } //go:noinline func xor_uint16_65535(a uint16) uint16 { return a ^ 65535 } //go:noinline func xor_65535_uint16(a uint16) uint16 { return 65535 ^ a } //go:noinline func add_int16_Neg32768(a int16) int16 { return a + -32768 } //go:noinline func add_Neg32768_int16(a int16) int16 { return -32768 + a } //go:noinline func add_int16_Neg32767(a int16) int16 { return a + -32767 } //go:noinline func add_Neg32767_int16(a int16) int16 { return -32767 + a } //go:noinline func add_int16_Neg1(a int16) int16 { return a + -1 } //go:noinline func add_Neg1_int16(a int16) int16 { return -1 + a } //go:noinline func add_int16_0(a int16) int16 { return a + 0 } //go:noinline func add_0_int16(a int16) int16 { return 0 + a } //go:noinline func add_int16_1(a int16) int16 { return a + 1 } //go:noinline func add_1_int16(a int16) int16 { return 1 + a } //go:noinline func add_int16_32766(a int16) int16 { return a + 32766 } //go:noinline func add_32766_int16(a int16) int16 { return 32766 + a } //go:noinline func add_int16_32767(a int16) int16 { return a + 32767 } //go:noinline func add_32767_int16(a int16) int16 { return 32767 + a } //go:noinline func sub_int16_Neg32768(a int16) int16 { return a - -32768 } //go:noinline func sub_Neg32768_int16(a int16) int16 { return -32768 - a } //go:noinline func sub_int16_Neg32767(a int16) int16 { return a - -32767 } //go:noinline func sub_Neg32767_int16(a int16) int16 { return -32767 - a } //go:noinline func sub_int16_Neg1(a int16) int16 { return a - -1 } //go:noinline func sub_Neg1_int16(a int16) int16 { return -1 - a } //go:noinline func sub_int16_0(a int16) int16 { return a - 0 } //go:noinline func sub_0_int16(a int16) int16 { return 0 - a } //go:noinline func sub_int16_1(a int16) int16 { return a - 1 } //go:noinline func sub_1_int16(a int16) int16 { return 1 - a } //go:noinline func sub_int16_32766(a int16) int16 { return a - 32766 } //go:noinline func sub_32766_int16(a int16) int16 { return 32766 - a } //go:noinline func sub_int16_32767(a int16) int16 { return a - 32767 } //go:noinline func sub_32767_int16(a int16) int16 { return 32767 - a } //go:noinline func div_int16_Neg32768(a int16) int16 { return a / -32768 } //go:noinline func div_Neg32768_int16(a int16) int16 { return -32768 / a } //go:noinline func div_int16_Neg32767(a int16) int16 { return a / -32767 } //go:noinline func div_Neg32767_int16(a int16) int16 { return -32767 / a } //go:noinline func div_int16_Neg1(a int16) int16 { return a / -1 } //go:noinline func div_Neg1_int16(a int16) int16 { return -1 / a } //go:noinline func div_0_int16(a int16) int16 { return 0 / a } //go:noinline func div_int16_1(a int16) int16 { return a / 1 } //go:noinline func div_1_int16(a int16) int16 { return 1 / a } //go:noinline func div_int16_32766(a int16) int16 { return a / 32766 } //go:noinline func div_32766_int16(a int16) int16 { return 32766 / a } //go:noinline func div_int16_32767(a int16) int16 { return a / 32767 } //go:noinline func div_32767_int16(a int16) int16 { return 32767 / a } //go:noinline func mul_int16_Neg32768(a int16) int16 { return a * -32768 } //go:noinline func mul_Neg32768_int16(a int16) int16 { return -32768 * a } //go:noinline func mul_int16_Neg32767(a int16) int16 { return a * -32767 } //go:noinline func mul_Neg32767_int16(a int16) int16 { return -32767 * a } //go:noinline func mul_int16_Neg1(a int16) int16 { return a * -1 } //go:noinline func mul_Neg1_int16(a int16) int16 { return -1 * a } //go:noinline func mul_int16_0(a int16) int16 { return a * 0 } //go:noinline func mul_0_int16(a int16) int16 { return 0 * a } //go:noinline func mul_int16_1(a int16) int16 { return a * 1 } //go:noinline func mul_1_int16(a int16) int16 { return 1 * a } //go:noinline func mul_int16_32766(a int16) int16 { return a * 32766 } //go:noinline func mul_32766_int16(a int16) int16 { return 32766 * a } //go:noinline func mul_int16_32767(a int16) int16 { return a * 32767 } //go:noinline func mul_32767_int16(a int16) int16 { return 32767 * a } //go:noinline func mod_int16_Neg32768(a int16) int16 { return a % -32768 } //go:noinline func mod_Neg32768_int16(a int16) int16 { return -32768 % a } //go:noinline func mod_int16_Neg32767(a int16) int16 { return a % -32767 } //go:noinline func mod_Neg32767_int16(a int16) int16 { return -32767 % a } //go:noinline func mod_int16_Neg1(a int16) int16 { return a % -1 } //go:noinline func mod_Neg1_int16(a int16) int16 { return -1 % a } //go:noinline func mod_0_int16(a int16) int16 { return 0 % a } //go:noinline func mod_int16_1(a int16) int16 { return a % 1 } //go:noinline func mod_1_int16(a int16) int16 { return 1 % a } //go:noinline func mod_int16_32766(a int16) int16 { return a % 32766 } //go:noinline func mod_32766_int16(a int16) int16 { return 32766 % a } //go:noinline func mod_int16_32767(a int16) int16 { return a % 32767 } //go:noinline func mod_32767_int16(a int16) int16 { return 32767 % a } //go:noinline func and_int16_Neg32768(a int16) int16 { return a & -32768 } //go:noinline func and_Neg32768_int16(a int16) int16 { return -32768 & a } //go:noinline func and_int16_Neg32767(a int16) int16 { return a & -32767 } //go:noinline func and_Neg32767_int16(a int16) int16 { return -32767 & a } //go:noinline func and_int16_Neg1(a int16) int16 { return a & -1 } //go:noinline func and_Neg1_int16(a int16) int16 { return -1 & a } //go:noinline func and_int16_0(a int16) int16 { return a & 0 } //go:noinline func and_0_int16(a int16) int16 { return 0 & a } //go:noinline func and_int16_1(a int16) int16 { return a & 1 } //go:noinline func and_1_int16(a int16) int16 { return 1 & a } //go:noinline func and_int16_32766(a int16) int16 { return a & 32766 } //go:noinline func and_32766_int16(a int16) int16 { return 32766 & a } //go:noinline func and_int16_32767(a int16) int16 { return a & 32767 } //go:noinline func and_32767_int16(a int16) int16 { return 32767 & a } //go:noinline func or_int16_Neg32768(a int16) int16 { return a | -32768 } //go:noinline func or_Neg32768_int16(a int16) int16 { return -32768 | a } //go:noinline func or_int16_Neg32767(a int16) int16 { return a | -32767 } //go:noinline func or_Neg32767_int16(a int16) int16 { return -32767 | a } //go:noinline func or_int16_Neg1(a int16) int16 { return a | -1 } //go:noinline func or_Neg1_int16(a int16) int16 { return -1 | a } //go:noinline func or_int16_0(a int16) int16 { return a | 0 } //go:noinline func or_0_int16(a int16) int16 { return 0 | a } //go:noinline func or_int16_1(a int16) int16 { return a | 1 } //go:noinline func or_1_int16(a int16) int16 { return 1 | a } //go:noinline func or_int16_32766(a int16) int16 { return a | 32766 } //go:noinline func or_32766_int16(a int16) int16 { return 32766 | a } //go:noinline func or_int16_32767(a int16) int16 { return a | 32767 } //go:noinline func or_32767_int16(a int16) int16 { return 32767 | a } //go:noinline func xor_int16_Neg32768(a int16) int16 { return a ^ -32768 } //go:noinline func xor_Neg32768_int16(a int16) int16 { return -32768 ^ a } //go:noinline func xor_int16_Neg32767(a int16) int16 { return a ^ -32767 } //go:noinline func xor_Neg32767_int16(a int16) int16 { return -32767 ^ a } //go:noinline func xor_int16_Neg1(a int16) int16 { return a ^ -1 } //go:noinline func xor_Neg1_int16(a int16) int16 { return -1 ^ a } //go:noinline func xor_int16_0(a int16) int16 { return a ^ 0 } //go:noinline func xor_0_int16(a int16) int16 { return 0 ^ a } //go:noinline func xor_int16_1(a int16) int16 { return a ^ 1 } //go:noinline func xor_1_int16(a int16) int16 { return 1 ^ a } //go:noinline func xor_int16_32766(a int16) int16 { return a ^ 32766 } //go:noinline func xor_32766_int16(a int16) int16 { return 32766 ^ a } //go:noinline func xor_int16_32767(a int16) int16 { return a ^ 32767 } //go:noinline func xor_32767_int16(a int16) int16 { return 32767 ^ a } //go:noinline func add_uint8_0(a uint8) uint8 { return a + 0 } //go:noinline func add_0_uint8(a uint8) uint8 { return 0 + a } //go:noinline func add_uint8_1(a uint8) uint8 { return a + 1 } //go:noinline func add_1_uint8(a uint8) uint8 { return 1 + a } //go:noinline func add_uint8_255(a uint8) uint8 { return a + 255 } //go:noinline func add_255_uint8(a uint8) uint8 { return 255 + a } //go:noinline func sub_uint8_0(a uint8) uint8 { return a - 0 } //go:noinline func sub_0_uint8(a uint8) uint8 { return 0 - a } //go:noinline func sub_uint8_1(a uint8) uint8 { return a - 1 } //go:noinline func sub_1_uint8(a uint8) uint8 { return 1 - a } //go:noinline func sub_uint8_255(a uint8) uint8 { return a - 255 } //go:noinline func sub_255_uint8(a uint8) uint8 { return 255 - a } //go:noinline func div_0_uint8(a uint8) uint8 { return 0 / a } //go:noinline func div_uint8_1(a uint8) uint8 { return a / 1 } //go:noinline func div_1_uint8(a uint8) uint8 { return 1 / a } //go:noinline func div_uint8_255(a uint8) uint8 { return a / 255 } //go:noinline func div_255_uint8(a uint8) uint8 { return 255 / a } //go:noinline func mul_uint8_0(a uint8) uint8 { return a * 0 } //go:noinline func mul_0_uint8(a uint8) uint8 { return 0 * a } //go:noinline func mul_uint8_1(a uint8) uint8 { return a * 1 } //go:noinline func mul_1_uint8(a uint8) uint8 { return 1 * a } //go:noinline func mul_uint8_255(a uint8) uint8 { return a * 255 } //go:noinline func mul_255_uint8(a uint8) uint8 { return 255 * a } //go:noinline func lsh_uint8_0(a uint8) uint8 { return a << 0 } //go:noinline func lsh_0_uint8(a uint8) uint8 { return 0 << a } //go:noinline func lsh_uint8_1(a uint8) uint8 { return a << 1 } //go:noinline func lsh_1_uint8(a uint8) uint8 { return 1 << a } //go:noinline func lsh_uint8_255(a uint8) uint8 { return a << 255 } //go:noinline func lsh_255_uint8(a uint8) uint8 { return 255 << a } //go:noinline func rsh_uint8_0(a uint8) uint8 { return a >> 0 } //go:noinline func rsh_0_uint8(a uint8) uint8 { return 0 >> a } //go:noinline func rsh_uint8_1(a uint8) uint8 { return a >> 1 } //go:noinline func rsh_1_uint8(a uint8) uint8 { return 1 >> a } //go:noinline func rsh_uint8_255(a uint8) uint8 { return a >> 255 } //go:noinline func rsh_255_uint8(a uint8) uint8 { return 255 >> a } //go:noinline func mod_0_uint8(a uint8) uint8 { return 0 % a } //go:noinline func mod_uint8_1(a uint8) uint8 { return a % 1 } //go:noinline func mod_1_uint8(a uint8) uint8 { return 1 % a } //go:noinline func mod_uint8_255(a uint8) uint8 { return a % 255 } //go:noinline func mod_255_uint8(a uint8) uint8 { return 255 % a } //go:noinline func and_uint8_0(a uint8) uint8 { return a & 0 } //go:noinline func and_0_uint8(a uint8) uint8 { return 0 & a } //go:noinline func and_uint8_1(a uint8) uint8 { return a & 1 } //go:noinline func and_1_uint8(a uint8) uint8 { return 1 & a } //go:noinline func and_uint8_255(a uint8) uint8 { return a & 255 } //go:noinline func and_255_uint8(a uint8) uint8 { return 255 & a } //go:noinline func or_uint8_0(a uint8) uint8 { return a | 0 } //go:noinline func or_0_uint8(a uint8) uint8 { return 0 | a } //go:noinline func or_uint8_1(a uint8) uint8 { return a | 1 } //go:noinline func or_1_uint8(a uint8) uint8 { return 1 | a } //go:noinline func or_uint8_255(a uint8) uint8 { return a | 255 } //go:noinline func or_255_uint8(a uint8) uint8 { return 255 | a } //go:noinline func xor_uint8_0(a uint8) uint8 { return a ^ 0 } //go:noinline func xor_0_uint8(a uint8) uint8 { return 0 ^ a } //go:noinline func xor_uint8_1(a uint8) uint8 { return a ^ 1 } //go:noinline func xor_1_uint8(a uint8) uint8 { return 1 ^ a } //go:noinline func xor_uint8_255(a uint8) uint8 { return a ^ 255 } //go:noinline func xor_255_uint8(a uint8) uint8 { return 255 ^ a } //go:noinline func add_int8_Neg128(a int8) int8 { return a + -128 } //go:noinline func add_Neg128_int8(a int8) int8 { return -128 + a } //go:noinline func add_int8_Neg127(a int8) int8 { return a + -127 } //go:noinline func add_Neg127_int8(a int8) int8 { return -127 + a } //go:noinline func add_int8_Neg1(a int8) int8 { return a + -1 } //go:noinline func add_Neg1_int8(a int8) int8 { return -1 + a } //go:noinline func add_int8_0(a int8) int8 { return a + 0 } //go:noinline func add_0_int8(a int8) int8 { return 0 + a } //go:noinline func add_int8_1(a int8) int8 { return a + 1 } //go:noinline func add_1_int8(a int8) int8 { return 1 + a } //go:noinline func add_int8_126(a int8) int8 { return a + 126 } //go:noinline func add_126_int8(a int8) int8 { return 126 + a } //go:noinline func add_int8_127(a int8) int8 { return a + 127 } //go:noinline func add_127_int8(a int8) int8 { return 127 + a } //go:noinline func sub_int8_Neg128(a int8) int8 { return a - -128 } //go:noinline func sub_Neg128_int8(a int8) int8 { return -128 - a } //go:noinline func sub_int8_Neg127(a int8) int8 { return a - -127 } //go:noinline func sub_Neg127_int8(a int8) int8 { return -127 - a } //go:noinline func sub_int8_Neg1(a int8) int8 { return a - -1 } //go:noinline func sub_Neg1_int8(a int8) int8 { return -1 - a } //go:noinline func sub_int8_0(a int8) int8 { return a - 0 } //go:noinline func sub_0_int8(a int8) int8 { return 0 - a } //go:noinline func sub_int8_1(a int8) int8 { return a - 1 } //go:noinline func sub_1_int8(a int8) int8 { return 1 - a } //go:noinline func sub_int8_126(a int8) int8 { return a - 126 } //go:noinline func sub_126_int8(a int8) int8 { return 126 - a } //go:noinline func sub_int8_127(a int8) int8 { return a - 127 } //go:noinline func sub_127_int8(a int8) int8 { return 127 - a } //go:noinline func div_int8_Neg128(a int8) int8 { return a / -128 } //go:noinline func div_Neg128_int8(a int8) int8 { return -128 / a } //go:noinline func div_int8_Neg127(a int8) int8 { return a / -127 } //go:noinline func div_Neg127_int8(a int8) int8 { return -127 / a } //go:noinline func div_int8_Neg1(a int8) int8 { return a / -1 } //go:noinline func div_Neg1_int8(a int8) int8 { return -1 / a } //go:noinline func div_0_int8(a int8) int8 { return 0 / a } //go:noinline func div_int8_1(a int8) int8 { return a / 1 } //go:noinline func div_1_int8(a int8) int8 { return 1 / a } //go:noinline func div_int8_126(a int8) int8 { return a / 126 } //go:noinline func div_126_int8(a int8) int8 { return 126 / a } //go:noinline func div_int8_127(a int8) int8 { return a / 127 } //go:noinline func div_127_int8(a int8) int8 { return 127 / a } //go:noinline func mul_int8_Neg128(a int8) int8 { return a * -128 } //go:noinline func mul_Neg128_int8(a int8) int8 { return -128 * a } //go:noinline func mul_int8_Neg127(a int8) int8 { return a * -127 } //go:noinline func mul_Neg127_int8(a int8) int8 { return -127 * a } //go:noinline func mul_int8_Neg1(a int8) int8 { return a * -1 } //go:noinline func mul_Neg1_int8(a int8) int8 { return -1 * a } //go:noinline func mul_int8_0(a int8) int8 { return a * 0 } //go:noinline func mul_0_int8(a int8) int8 { return 0 * a } //go:noinline func mul_int8_1(a int8) int8 { return a * 1 } //go:noinline func mul_1_int8(a int8) int8 { return 1 * a } //go:noinline func mul_int8_126(a int8) int8 { return a * 126 } //go:noinline func mul_126_int8(a int8) int8 { return 126 * a } //go:noinline func mul_int8_127(a int8) int8 { return a * 127 } //go:noinline func mul_127_int8(a int8) int8 { return 127 * a } //go:noinline func mod_int8_Neg128(a int8) int8 { return a % -128 } //go:noinline func mod_Neg128_int8(a int8) int8 { return -128 % a } //go:noinline func mod_int8_Neg127(a int8) int8 { return a % -127 } //go:noinline func mod_Neg127_int8(a int8) int8 { return -127 % a } //go:noinline func mod_int8_Neg1(a int8) int8 { return a % -1 } //go:noinline func mod_Neg1_int8(a int8) int8 { return -1 % a } //go:noinline func mod_0_int8(a int8) int8 { return 0 % a } //go:noinline func mod_int8_1(a int8) int8 { return a % 1 } //go:noinline func mod_1_int8(a int8) int8 { return 1 % a } //go:noinline func mod_int8_126(a int8) int8 { return a % 126 } //go:noinline func mod_126_int8(a int8) int8 { return 126 % a } //go:noinline func mod_int8_127(a int8) int8 { return a % 127 } //go:noinline func mod_127_int8(a int8) int8 { return 127 % a } //go:noinline func and_int8_Neg128(a int8) int8 { return a & -128 } //go:noinline func and_Neg128_int8(a int8) int8 { return -128 & a } //go:noinline func and_int8_Neg127(a int8) int8 { return a & -127 } //go:noinline func and_Neg127_int8(a int8) int8 { return -127 & a } //go:noinline func and_int8_Neg1(a int8) int8 { return a & -1 } //go:noinline func and_Neg1_int8(a int8) int8 { return -1 & a } //go:noinline func and_int8_0(a int8) int8 { return a & 0 } //go:noinline func and_0_int8(a int8) int8 { return 0 & a } //go:noinline func and_int8_1(a int8) int8 { return a & 1 } //go:noinline func and_1_int8(a int8) int8 { return 1 & a } //go:noinline func and_int8_126(a int8) int8 { return a & 126 } //go:noinline func and_126_int8(a int8) int8 { return 126 & a } //go:noinline func and_int8_127(a int8) int8 { return a & 127 } //go:noinline func and_127_int8(a int8) int8 { return 127 & a } //go:noinline func or_int8_Neg128(a int8) int8 { return a | -128 } //go:noinline func or_Neg128_int8(a int8) int8 { return -128 | a } //go:noinline func or_int8_Neg127(a int8) int8 { return a | -127 } //go:noinline func or_Neg127_int8(a int8) int8 { return -127 | a } //go:noinline func or_int8_Neg1(a int8) int8 { return a | -1 } //go:noinline func or_Neg1_int8(a int8) int8 { return -1 | a } //go:noinline func or_int8_0(a int8) int8 { return a | 0 } //go:noinline func or_0_int8(a int8) int8 { return 0 | a } //go:noinline func or_int8_1(a int8) int8 { return a | 1 } //go:noinline func or_1_int8(a int8) int8 { return 1 | a } //go:noinline func or_int8_126(a int8) int8 { return a | 126 } //go:noinline func or_126_int8(a int8) int8 { return 126 | a } //go:noinline func or_int8_127(a int8) int8 { return a | 127 } //go:noinline func or_127_int8(a int8) int8 { return 127 | a } //go:noinline func xor_int8_Neg128(a int8) int8 { return a ^ -128 } //go:noinline func xor_Neg128_int8(a int8) int8 { return -128 ^ a } //go:noinline func xor_int8_Neg127(a int8) int8 { return a ^ -127 } //go:noinline func xor_Neg127_int8(a int8) int8 { return -127 ^ a } //go:noinline func xor_int8_Neg1(a int8) int8 { return a ^ -1 } //go:noinline func xor_Neg1_int8(a int8) int8 { return -1 ^ a } //go:noinline func xor_int8_0(a int8) int8 { return a ^ 0 } //go:noinline func xor_0_int8(a int8) int8 { return 0 ^ a } //go:noinline func xor_int8_1(a int8) int8 { return a ^ 1 } //go:noinline func xor_1_int8(a int8) int8 { return 1 ^ a } //go:noinline func xor_int8_126(a int8) int8 { return a ^ 126 } //go:noinline func xor_126_int8(a int8) int8 { return 126 ^ a } //go:noinline func xor_int8_127(a int8) int8 { return a ^ 127 } //go:noinline func xor_127_int8(a int8) int8 { return 127 ^ a } type test_uint64 struct { fn func(uint64) uint64 fnname string in uint64 want uint64 } var tests_uint64 = []test_uint64{ test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 0, want: 0}, test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 0, want: 0}, test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 1, want: 1}, test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 1, want: 1}, test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 4294967296, want: 4294967296}, test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 0, want: 1}, test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 0, want: 1}, test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 1, want: 2}, test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 1, want: 2}, test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 4294967296, want: 4294967297}, test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 4294967296, want: 4294967297}, test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 18446744073709551615, want: 0}, test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 0, want: 4294967296}, test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 0, want: 4294967296}, test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 1, want: 4294967297}, test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 1, want: 4294967297}, test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 4294967296, want: 8589934592}, test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 4294967296, want: 8589934592}, test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 18446744073709551615, want: 4294967295}, test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 18446744073709551615, want: 4294967295}, test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 0, want: 9223372036854775808}, test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 1, want: 9223372036854775809}, test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 1, want: 9223372036854775809}, test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 0, want: 18446744073709551615}, test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 1, want: 0}, test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 1, want: 0}, test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 4294967296, want: 4294967295}, test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 4294967296, want: 4294967295}, test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 18446744073709551615, want: 18446744073709551614}, test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 18446744073709551615, want: 18446744073709551614}, test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 0, want: 0}, test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 0, want: 0}, test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 1, want: 18446744073709551615}, test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 1, want: 1}, test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 4294967296, want: 18446744069414584320}, test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 4294967296, want: 4294967296}, test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 18446744073709551615, want: 1}, test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 0, want: 1}, test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 0, want: 18446744073709551615}, test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 1, want: 0}, test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 1, want: 0}, test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 4294967296, want: 18446744069414584321}, test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 4294967296, want: 4294967295}, test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 18446744073709551615, want: 2}, test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 18446744073709551615, want: 18446744073709551614}, test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 0, want: 4294967296}, test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 0, want: 18446744069414584320}, test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 1, want: 4294967295}, test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 1, want: 18446744069414584321}, test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 4294967296, want: 0}, test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 4294967296, want: 0}, test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 9223372036854775808, want: 9223372032559808512}, test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 18446744073709551615, want: 4294967297}, test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 18446744073709551615, want: 18446744069414584319}, test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 0, want: 9223372036854775808}, test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 1, want: 9223372036854775807}, test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 1, want: 9223372036854775809}, test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 4294967296, want: 9223372032559808512}, test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775809}, test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 0, want: 1}, test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 1, want: 18446744073709551614}, test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 1, want: 2}, test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 4294967296, want: 18446744069414584319}, test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 4294967296, want: 4294967297}, test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 18446744073709551615, want: 0}, test_uint64{fn: div_0_uint64, fnname: "div_0_uint64", in: 1, want: 0}, test_uint64{fn: div_0_uint64, fnname: "div_0_uint64", in: 4294967296, want: 0}, test_uint64{fn: div_0_uint64, fnname: "div_0_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: div_0_uint64, fnname: "div_0_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 0, want: 0}, test_uint64{fn: div_1_uint64, fnname: "div_1_uint64", in: 1, want: 1}, test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 1, want: 1}, test_uint64{fn: div_1_uint64, fnname: "div_1_uint64", in: 4294967296, want: 0}, test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 4294967296, want: 4294967296}, test_uint64{fn: div_1_uint64, fnname: "div_1_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: div_1_uint64, fnname: "div_1_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 0, want: 0}, test_uint64{fn: div_4294967296_uint64, fnname: "div_4294967296_uint64", in: 1, want: 4294967296}, test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 1, want: 0}, test_uint64{fn: div_4294967296_uint64, fnname: "div_4294967296_uint64", in: 4294967296, want: 1}, test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 4294967296, want: 1}, test_uint64{fn: div_4294967296_uint64, fnname: "div_4294967296_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 9223372036854775808, want: 2147483648}, test_uint64{fn: div_4294967296_uint64, fnname: "div_4294967296_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 18446744073709551615, want: 4294967295}, test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 0, want: 0}, test_uint64{fn: div_9223372036854775808_uint64, fnname: "div_9223372036854775808_uint64", in: 1, want: 9223372036854775808}, test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 1, want: 0}, test_uint64{fn: div_9223372036854775808_uint64, fnname: "div_9223372036854775808_uint64", in: 4294967296, want: 2147483648}, test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 4294967296, want: 0}, test_uint64{fn: div_9223372036854775808_uint64, fnname: "div_9223372036854775808_uint64", in: 9223372036854775808, want: 1}, test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 9223372036854775808, want: 1}, test_uint64{fn: div_9223372036854775808_uint64, fnname: "div_9223372036854775808_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 18446744073709551615, want: 1}, test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 0, want: 0}, test_uint64{fn: div_18446744073709551615_uint64, fnname: "div_18446744073709551615_uint64", in: 1, want: 18446744073709551615}, test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 1, want: 0}, test_uint64{fn: div_18446744073709551615_uint64, fnname: "div_18446744073709551615_uint64", in: 4294967296, want: 4294967295}, test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 4294967296, want: 0}, test_uint64{fn: div_18446744073709551615_uint64, fnname: "div_18446744073709551615_uint64", in: 9223372036854775808, want: 1}, test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 9223372036854775808, want: 0}, test_uint64{fn: div_18446744073709551615_uint64, fnname: "div_18446744073709551615_uint64", in: 18446744073709551615, want: 1}, test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 18446744073709551615, want: 1}, test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 0, want: 0}, test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 0, want: 0}, test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 1, want: 0}, test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 1, want: 0}, test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 4294967296, want: 0}, test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 4294967296, want: 0}, test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 9223372036854775808, want: 0}, test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 18446744073709551615, want: 0}, test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 0, want: 0}, test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 0, want: 0}, test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 1, want: 1}, test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 1, want: 1}, test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 4294967296, want: 4294967296}, test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 0, want: 0}, test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 0, want: 0}, test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 1, want: 4294967296}, test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 1, want: 4294967296}, test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 4294967296, want: 0}, test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 4294967296, want: 0}, test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 9223372036854775808, want: 0}, test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 18446744073709551615, want: 18446744069414584320}, test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 18446744073709551615, want: 18446744069414584320}, test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 0, want: 0}, test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 0, want: 0}, test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 1, want: 9223372036854775808}, test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 1, want: 9223372036854775808}, test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 4294967296, want: 0}, test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 4294967296, want: 0}, test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775808}, test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775808}, test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 0, want: 0}, test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 0, want: 0}, test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 1, want: 18446744073709551615}, test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 1, want: 18446744073709551615}, test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 4294967296, want: 18446744069414584320}, test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 4294967296, want: 18446744069414584320}, test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 18446744073709551615, want: 1}, test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 18446744073709551615, want: 1}, test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 0, want: 0}, test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 0, want: 0}, test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 1, want: 0}, test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 1, want: 1}, test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 4294967296, want: 0}, test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 4294967296, want: 4294967296}, test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 0, want: 1}, test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 0, want: 0}, test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 1, want: 2}, test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 1, want: 2}, test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 4294967296, want: 0}, test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 4294967296, want: 8589934592}, test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 18446744073709551615, want: 18446744073709551614}, test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 0, want: 4294967296}, test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 0, want: 0}, test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 1, want: 8589934592}, test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 1, want: 0}, test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 4294967296, want: 0}, test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 4294967296, want: 0}, test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 0, want: 0}, test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 1, want: 0}, test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 1, want: 0}, test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 4294967296, want: 0}, test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 4294967296, want: 0}, test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 0, want: 0}, test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 1, want: 18446744073709551614}, test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 1, want: 0}, test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 4294967296, want: 0}, test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 4294967296, want: 0}, test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 9223372036854775808, want: 0}, test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 0, want: 0}, test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 0, want: 0}, test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 1, want: 0}, test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 1, want: 1}, test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 4294967296, want: 0}, test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 4294967296, want: 4294967296}, test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 0, want: 1}, test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 0, want: 0}, test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 1, want: 0}, test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 1, want: 0}, test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 4294967296, want: 0}, test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 4294967296, want: 2147483648}, test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 9223372036854775808, want: 4611686018427387904}, test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 0, want: 4294967296}, test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 0, want: 0}, test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 1, want: 2147483648}, test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 1, want: 0}, test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 4294967296, want: 0}, test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 4294967296, want: 0}, test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 0, want: 0}, test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 1, want: 4611686018427387904}, test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 1, want: 0}, test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 4294967296, want: 0}, test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 4294967296, want: 0}, test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 0, want: 0}, test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 1, want: 9223372036854775807}, test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 1, want: 0}, test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 4294967296, want: 0}, test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 4294967296, want: 0}, test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 9223372036854775808, want: 0}, test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 18446744073709551615, want: 0}, test_uint64{fn: mod_0_uint64, fnname: "mod_0_uint64", in: 1, want: 0}, test_uint64{fn: mod_0_uint64, fnname: "mod_0_uint64", in: 4294967296, want: 0}, test_uint64{fn: mod_0_uint64, fnname: "mod_0_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: mod_0_uint64, fnname: "mod_0_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 0, want: 0}, test_uint64{fn: mod_1_uint64, fnname: "mod_1_uint64", in: 1, want: 0}, test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 1, want: 0}, test_uint64{fn: mod_1_uint64, fnname: "mod_1_uint64", in: 4294967296, want: 1}, test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 4294967296, want: 0}, test_uint64{fn: mod_1_uint64, fnname: "mod_1_uint64", in: 9223372036854775808, want: 1}, test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 9223372036854775808, want: 0}, test_uint64{fn: mod_1_uint64, fnname: "mod_1_uint64", in: 18446744073709551615, want: 1}, test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 18446744073709551615, want: 0}, test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 0, want: 0}, test_uint64{fn: mod_4294967296_uint64, fnname: "mod_4294967296_uint64", in: 1, want: 0}, test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 1, want: 1}, test_uint64{fn: mod_4294967296_uint64, fnname: "mod_4294967296_uint64", in: 4294967296, want: 0}, test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 4294967296, want: 0}, test_uint64{fn: mod_4294967296_uint64, fnname: "mod_4294967296_uint64", in: 9223372036854775808, want: 4294967296}, test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 9223372036854775808, want: 0}, test_uint64{fn: mod_4294967296_uint64, fnname: "mod_4294967296_uint64", in: 18446744073709551615, want: 4294967296}, test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 18446744073709551615, want: 4294967295}, test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 0, want: 0}, test_uint64{fn: mod_9223372036854775808_uint64, fnname: "mod_9223372036854775808_uint64", in: 1, want: 0}, test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 1, want: 1}, test_uint64{fn: mod_9223372036854775808_uint64, fnname: "mod_9223372036854775808_uint64", in: 4294967296, want: 0}, test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 4294967296, want: 4294967296}, test_uint64{fn: mod_9223372036854775808_uint64, fnname: "mod_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: mod_9223372036854775808_uint64, fnname: "mod_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775808}, test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 0, want: 0}, test_uint64{fn: mod_18446744073709551615_uint64, fnname: "mod_18446744073709551615_uint64", in: 1, want: 0}, test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 1, want: 1}, test_uint64{fn: mod_18446744073709551615_uint64, fnname: "mod_18446744073709551615_uint64", in: 4294967296, want: 4294967295}, test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 4294967296, want: 4294967296}, test_uint64{fn: mod_18446744073709551615_uint64, fnname: "mod_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: mod_18446744073709551615_uint64, fnname: "mod_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 18446744073709551615, want: 0}, test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 0, want: 0}, test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 0, want: 0}, test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 1, want: 0}, test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 1, want: 0}, test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 4294967296, want: 0}, test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 4294967296, want: 0}, test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 9223372036854775808, want: 0}, test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 18446744073709551615, want: 0}, test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 0, want: 0}, test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 0, want: 0}, test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 1, want: 1}, test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 1, want: 1}, test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 4294967296, want: 0}, test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 4294967296, want: 0}, test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 9223372036854775808, want: 0}, test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 18446744073709551615, want: 1}, test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 18446744073709551615, want: 1}, test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 0, want: 0}, test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 0, want: 0}, test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 1, want: 0}, test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 1, want: 0}, test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 4294967296, want: 4294967296}, test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 9223372036854775808, want: 0}, test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 18446744073709551615, want: 4294967296}, test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 18446744073709551615, want: 4294967296}, test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 0, want: 0}, test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 0, want: 0}, test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 1, want: 0}, test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 1, want: 0}, test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 4294967296, want: 0}, test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 4294967296, want: 0}, test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775808}, test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775808}, test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 0, want: 0}, test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 0, want: 0}, test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 1, want: 1}, test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 1, want: 1}, test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 4294967296, want: 4294967296}, test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 0, want: 0}, test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 0, want: 0}, test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 1, want: 1}, test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 1, want: 1}, test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 4294967296, want: 4294967296}, test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 0, want: 1}, test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 0, want: 1}, test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 1, want: 1}, test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 1, want: 1}, test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 4294967296, want: 4294967297}, test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 4294967296, want: 4294967297}, test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 0, want: 4294967296}, test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 0, want: 4294967296}, test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 1, want: 4294967297}, test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 1, want: 4294967297}, test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 4294967296, want: 4294967296}, test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 0, want: 9223372036854775808}, test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 1, want: 9223372036854775809}, test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 1, want: 9223372036854775809}, test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 0, want: 18446744073709551615}, test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 1, want: 18446744073709551615}, test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 1, want: 18446744073709551615}, test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 4294967296, want: 18446744073709551615}, test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 4294967296, want: 18446744073709551615}, test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 9223372036854775808, want: 18446744073709551615}, test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 9223372036854775808, want: 18446744073709551615}, test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 0, want: 0}, test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 0, want: 0}, test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 1, want: 1}, test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 1, want: 1}, test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 4294967296, want: 4294967296}, test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 4294967296, want: 4294967296}, test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 0, want: 1}, test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 0, want: 1}, test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 1, want: 0}, test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 1, want: 0}, test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 4294967296, want: 4294967297}, test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 4294967296, want: 4294967297}, test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 9223372036854775808, want: 9223372036854775809}, test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 18446744073709551615, want: 18446744073709551614}, test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 18446744073709551615, want: 18446744073709551614}, test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 0, want: 4294967296}, test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 0, want: 4294967296}, test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 1, want: 4294967297}, test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 1, want: 4294967297}, test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 4294967296, want: 0}, test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 4294967296, want: 0}, test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 9223372036854775808, want: 9223372041149743104}, test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 18446744073709551615, want: 18446744069414584319}, test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 18446744073709551615, want: 18446744069414584319}, test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 0, want: 9223372036854775808}, test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 1, want: 9223372036854775809}, test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 1, want: 9223372036854775809}, test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 4294967296, want: 9223372041149743104}, test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775807}, test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 0, want: 18446744073709551615}, test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 1, want: 18446744073709551614}, test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 1, want: 18446744073709551614}, test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 4294967296, want: 18446744069414584319}, test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 4294967296, want: 18446744069414584319}, test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775807}, test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 18446744073709551615, want: 0}} type test_int64 struct { fn func(int64) int64 fnname string in int64 want int64 } var tests_int64 = []test_int64{ test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: -9223372036854775807, want: 1}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: -9223372036854775807, want: 1}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: -4294967296, want: 9223372032559808512}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: -4294967296, want: 9223372032559808512}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: -1, want: 9223372036854775807}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: -1, want: 9223372036854775807}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 0, want: -9223372036854775808}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 0, want: -9223372036854775808}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 1, want: -9223372036854775807}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 1, want: -9223372036854775807}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 4294967296, want: -9223372032559808512}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 4294967296, want: -9223372032559808512}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 9223372036854775806, want: -2}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 9223372036854775806, want: -2}, test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 9223372036854775807, want: -1}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: -9223372036854775808, want: 1}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: -9223372036854775808, want: 1}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: -9223372036854775807, want: 2}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: -9223372036854775807, want: 2}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: -4294967296, want: 9223372032559808513}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: -4294967296, want: 9223372032559808513}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: -1, want: -9223372036854775808}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: -1, want: -9223372036854775808}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 0, want: -9223372036854775807}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 0, want: -9223372036854775807}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 1, want: -9223372036854775806}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 1, want: -9223372036854775806}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 4294967296, want: -9223372032559808511}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 4294967296, want: -9223372032559808511}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 9223372036854775806, want: -1}, test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 9223372036854775807, want: 0}, test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 9223372036854775807, want: 0}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: -9223372036854775808, want: 9223372032559808512}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: -9223372036854775808, want: 9223372032559808512}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: -9223372036854775807, want: 9223372032559808513}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: -9223372036854775807, want: 9223372032559808513}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: -4294967296, want: -8589934592}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: -4294967296, want: -8589934592}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: -1, want: -4294967297}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: -1, want: -4294967297}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 0, want: -4294967296}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 0, want: -4294967296}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 1, want: -4294967295}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 1, want: -4294967295}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 4294967296, want: 0}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 9223372036854775806, want: 9223372032559808510}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 9223372036854775806, want: 9223372032559808510}, test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 9223372036854775807, want: 9223372032559808511}, test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 9223372036854775807, want: 9223372032559808511}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: -4294967296, want: -4294967297}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: -4294967296, want: -4294967297}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: -1, want: -2}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: -1, want: -2}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 0, want: -1}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 0, want: -1}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 1, want: 0}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 1, want: 0}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 4294967296, want: 4294967295}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 4294967296, want: 4294967295}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 9223372036854775806, want: 9223372036854775805}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 9223372036854775806, want: 9223372036854775805}, test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: -4294967296, want: -4294967296}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: -4294967296, want: -4294967296}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: -1, want: -1}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: -1, want: -1}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 0, want: 0}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 0, want: 0}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 1, want: 1}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 1, want: 1}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 4294967296, want: 4294967296}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 4294967296, want: 4294967296}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: -9223372036854775807, want: -9223372036854775806}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: -9223372036854775807, want: -9223372036854775806}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: -4294967296, want: -4294967295}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: -4294967296, want: -4294967295}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: -1, want: 0}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: -1, want: 0}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 0, want: 1}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 0, want: 1}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 1, want: 2}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 1, want: 2}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 4294967296, want: 4294967297}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 4294967296, want: 4294967297}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: -4294967296, want: 0}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: -1, want: 4294967295}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: -1, want: 4294967295}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 0, want: 4294967296}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 0, want: 4294967296}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 1, want: 4294967297}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 1, want: 4294967297}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 4294967296, want: 8589934592}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 4294967296, want: 8589934592}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 9223372036854775806, want: -9223372032559808514}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 9223372036854775806, want: -9223372032559808514}, test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 9223372036854775807, want: -9223372032559808513}, test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 9223372036854775807, want: -9223372032559808513}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: -9223372036854775808, want: -2}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: -9223372036854775808, want: -2}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: -9223372036854775807, want: -1}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: -9223372036854775807, want: -1}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: -4294967296, want: 9223372032559808510}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: -4294967296, want: 9223372032559808510}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: -1, want: 9223372036854775805}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: -1, want: 9223372036854775805}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 0, want: 9223372036854775806}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 0, want: 9223372036854775806}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 1, want: 9223372036854775807}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 1, want: 9223372036854775807}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 4294967296, want: -9223372032559808514}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 4294967296, want: -9223372032559808514}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 9223372036854775806, want: -4}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 9223372036854775806, want: -4}, test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 9223372036854775807, want: -3}, test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 9223372036854775807, want: -3}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: -9223372036854775808, want: -1}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: -9223372036854775807, want: 0}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: -9223372036854775807, want: 0}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: -4294967296, want: 9223372032559808511}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: -4294967296, want: 9223372032559808511}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: -1, want: 9223372036854775806}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: -1, want: 9223372036854775806}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 0, want: 9223372036854775807}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 0, want: 9223372036854775807}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 1, want: -9223372036854775808}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 1, want: -9223372036854775808}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 4294967296, want: -9223372032559808513}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 4294967296, want: -9223372032559808513}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 9223372036854775806, want: -3}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 9223372036854775806, want: -3}, test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 9223372036854775807, want: -2}, test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 9223372036854775807, want: -2}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: -9223372036854775807, want: -1}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: -9223372036854775807, want: 1}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: -4294967296, want: -9223372032559808512}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: -4294967296, want: 9223372032559808512}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: -1, want: -9223372036854775807}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: -1, want: 9223372036854775807}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 0, want: -9223372036854775808}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 0, want: -9223372036854775808}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 1, want: 9223372036854775807}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 1, want: -9223372036854775807}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 4294967296, want: 9223372032559808512}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 4294967296, want: -9223372032559808512}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 9223372036854775806, want: 2}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 9223372036854775806, want: -2}, test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 9223372036854775807, want: 1}, test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 9223372036854775807, want: -1}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: -9223372036854775808, want: 1}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: -9223372036854775807, want: 0}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: -9223372036854775807, want: 0}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: -4294967296, want: -9223372032559808511}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: -4294967296, want: 9223372032559808511}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: -1, want: -9223372036854775806}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: -1, want: 9223372036854775806}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 0, want: -9223372036854775807}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 0, want: 9223372036854775807}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 1, want: -9223372036854775808}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 1, want: -9223372036854775808}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 4294967296, want: 9223372032559808513}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 4294967296, want: -9223372032559808513}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 9223372036854775806, want: 3}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 9223372036854775806, want: -3}, test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 9223372036854775807, want: 2}, test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 9223372036854775807, want: -2}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: -9223372036854775808, want: 9223372032559808512}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: -9223372036854775807, want: 9223372032559808511}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: -4294967296, want: 0}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: -1, want: -4294967295}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: -1, want: 4294967295}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 0, want: -4294967296}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 0, want: 4294967296}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 1, want: -4294967297}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 1, want: 4294967297}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 4294967296, want: -8589934592}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 4294967296, want: 8589934592}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 9223372036854775806, want: 9223372032559808514}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 9223372036854775806, want: -9223372032559808514}, test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 9223372036854775807, want: 9223372032559808513}, test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 9223372036854775807, want: -9223372032559808513}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: -9223372036854775807, want: 9223372036854775806}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: -9223372036854775807, want: -9223372036854775806}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: -4294967296, want: 4294967295}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: -4294967296, want: -4294967295}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: -1, want: 0}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: -1, want: 0}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 0, want: -1}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 0, want: 1}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 1, want: -2}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 1, want: 2}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 4294967296, want: -4294967297}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 4294967296, want: 4294967297}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 9223372036854775806, want: -9223372036854775807}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: -9223372036854775807, want: 9223372036854775807}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: -4294967296, want: 4294967296}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: -4294967296, want: -4294967296}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: -1, want: 1}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: -1, want: -1}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 0, want: 0}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 0, want: 0}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 1, want: -1}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 1, want: 1}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 4294967296, want: -4294967296}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 4294967296, want: 4294967296}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 9223372036854775806, want: -9223372036854775806}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 9223372036854775807, want: -9223372036854775807}, test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: -4294967296, want: 4294967297}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: -4294967296, want: -4294967297}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: -1, want: 2}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: -1, want: -2}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 0, want: 1}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 0, want: -1}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 1, want: 0}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 1, want: 0}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 4294967296, want: -4294967295}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 4294967296, want: 4294967295}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 9223372036854775806, want: -9223372036854775805}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 9223372036854775806, want: 9223372036854775805}, test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 9223372036854775807, want: -9223372036854775806}, test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: -9223372036854775808, want: 9223372032559808512}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: -9223372036854775807, want: -9223372032559808513}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: -9223372036854775807, want: 9223372032559808513}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: -4294967296, want: 8589934592}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: -4294967296, want: -8589934592}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: -1, want: 4294967297}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: -1, want: -4294967297}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 0, want: 4294967296}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 0, want: -4294967296}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 1, want: 4294967295}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 1, want: -4294967295}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 4294967296, want: 0}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 9223372036854775806, want: -9223372032559808510}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 9223372036854775806, want: 9223372032559808510}, test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 9223372036854775807, want: -9223372032559808511}, test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 9223372036854775807, want: 9223372032559808511}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: -9223372036854775808, want: -2}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: -9223372036854775808, want: 2}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: -9223372036854775807, want: -3}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: -9223372036854775807, want: 3}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: -4294967296, want: -9223372032559808514}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: -4294967296, want: 9223372032559808514}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: -1, want: 9223372036854775807}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: -1, want: -9223372036854775807}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 0, want: 9223372036854775806}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 0, want: -9223372036854775806}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 1, want: 9223372036854775805}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 1, want: -9223372036854775805}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 4294967296, want: 9223372032559808510}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 4294967296, want: -9223372032559808510}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 9223372036854775806, want: 0}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 9223372036854775806, want: 0}, test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 9223372036854775807, want: -1}, test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 9223372036854775807, want: 1}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: -9223372036854775808, want: -1}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: -9223372036854775808, want: 1}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: -9223372036854775807, want: -2}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: -9223372036854775807, want: 2}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: -4294967296, want: -9223372032559808513}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: -4294967296, want: 9223372032559808513}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: -1, want: -9223372036854775808}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: -1, want: -9223372036854775808}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 0, want: 9223372036854775807}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 0, want: -9223372036854775807}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 1, want: 9223372036854775806}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 1, want: -9223372036854775806}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 4294967296, want: 9223372032559808511}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 4294967296, want: -9223372032559808511}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 9223372036854775806, want: 1}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 9223372036854775806, want: -1}, test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 9223372036854775807, want: 0}, test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 9223372036854775807, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: -9223372036854775808, want: 1}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: -9223372036854775808, want: 1}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: -9223372036854775807, want: 1}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: -9223372036854775807, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: -4294967296, want: 2147483648}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: -4294967296, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: -1, want: -9223372036854775808}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: -1, want: 0}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 0, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: 1, want: -9223372036854775808}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 1, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: 4294967296, want: -2147483648}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 4294967296, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: 9223372036854775806, want: -1}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 9223372036854775806, want: 0}, test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 9223372036854775807, want: 0}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: -9223372036854775808, want: 1}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: -9223372036854775807, want: 1}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: -9223372036854775807, want: 1}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: -4294967296, want: 2147483647}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: -4294967296, want: 0}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: -1, want: 9223372036854775807}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: -1, want: 0}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 0, want: 0}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: 1, want: -9223372036854775807}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 1, want: 0}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: 4294967296, want: -2147483647}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 4294967296, want: 0}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 9223372036854775806, want: 0}, test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: 9223372036854775807, want: -1}, test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 9223372036854775807, want: -1}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: -9223372036854775808, want: 2147483648}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: -9223372036854775807, want: 0}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: -9223372036854775807, want: 2147483647}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: -4294967296, want: 1}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: -4294967296, want: 1}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: -1, want: 4294967296}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: -1, want: 0}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 0, want: 0}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: 1, want: -4294967296}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 1, want: 0}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: 4294967296, want: -1}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 4294967296, want: -1}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: 9223372036854775806, want: 0}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 9223372036854775806, want: -2147483647}, test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: 9223372036854775807, want: 0}, test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 9223372036854775807, want: -2147483647}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: -9223372036854775807, want: 0}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: -9223372036854775807, want: 9223372036854775807}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: -4294967296, want: 0}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: -4294967296, want: 4294967296}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: -1, want: 1}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: -1, want: 1}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 0, want: 0}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: 1, want: -1}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 1, want: -1}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: 4294967296, want: 0}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 4294967296, want: -4294967296}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: 9223372036854775806, want: 0}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 9223372036854775806, want: -9223372036854775806}, test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: 9223372036854775807, want: 0}, test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 9223372036854775807, want: -9223372036854775807}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: -9223372036854775807, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: -4294967296, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: -1, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: 1, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: 4294967296, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: 9223372036854775806, want: 0}, test_int64{fn: div_0_int64, fnname: "div_0_int64", in: 9223372036854775807, want: 0}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: -9223372036854775807, want: 0}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: -4294967296, want: 0}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: -4294967296, want: -4294967296}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: -1, want: -1}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: -1, want: -1}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 0, want: 0}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: 1, want: 1}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 1, want: 1}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: 4294967296, want: 0}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 4294967296, want: 4294967296}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: 9223372036854775806, want: 0}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: div_1_int64, fnname: "div_1_int64", in: 9223372036854775807, want: 0}, test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: -9223372036854775808, want: -2147483648}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: -9223372036854775807, want: 0}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: -9223372036854775807, want: -2147483647}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: -4294967296, want: -1}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: -4294967296, want: -1}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: -1, want: -4294967296}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: -1, want: 0}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 0, want: 0}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: 1, want: 4294967296}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 1, want: 0}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: 4294967296, want: 1}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 4294967296, want: 1}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: 9223372036854775806, want: 0}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 9223372036854775806, want: 2147483647}, test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: 9223372036854775807, want: 0}, test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 9223372036854775807, want: 2147483647}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: -9223372036854775808, want: -1}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: -9223372036854775807, want: 0}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: -9223372036854775807, want: -1}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: -4294967296, want: -2147483647}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: -4294967296, want: 0}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: -1, want: -9223372036854775806}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: -1, want: 0}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 0, want: 0}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: 1, want: 9223372036854775806}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 1, want: 0}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: 4294967296, want: 2147483647}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 4294967296, want: 0}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: 9223372036854775806, want: 1}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 9223372036854775806, want: 1}, test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: 9223372036854775807, want: 0}, test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 9223372036854775807, want: 1}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: -9223372036854775808, want: 0}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: -9223372036854775807, want: -1}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: -9223372036854775807, want: -1}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: -4294967296, want: -2147483647}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: -4294967296, want: 0}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: -1, want: -9223372036854775807}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: -1, want: 0}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 0, want: 0}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: 1, want: 9223372036854775807}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 1, want: 0}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: 4294967296, want: 2147483647}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 4294967296, want: 0}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: 9223372036854775806, want: 1}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 9223372036854775806, want: 0}, test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: 9223372036854775807, want: 1}, test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 9223372036854775807, want: 1}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: -4294967296, want: 0}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: -4294967296, want: 0}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: -1, want: -9223372036854775808}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: -1, want: -9223372036854775808}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 0, want: 0}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 0, want: 0}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 1, want: -9223372036854775808}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 1, want: -9223372036854775808}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 4294967296, want: 0}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 4294967296, want: 0}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 9223372036854775806, want: 0}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 9223372036854775806, want: 0}, test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: -9223372036854775807, want: 1}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: -9223372036854775807, want: 1}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: -4294967296, want: -4294967296}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: -4294967296, want: -4294967296}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: -1, want: 9223372036854775807}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: -1, want: 9223372036854775807}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 0, want: 0}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 0, want: 0}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 1, want: -9223372036854775807}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 1, want: -9223372036854775807}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 4294967296, want: 4294967296}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 4294967296, want: 4294967296}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 9223372036854775807, want: -1}, test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 9223372036854775807, want: -1}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: -9223372036854775808, want: 0}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: -9223372036854775807, want: -4294967296}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: -9223372036854775807, want: -4294967296}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: -4294967296, want: 0}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: -1, want: 4294967296}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: -1, want: 4294967296}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 0, want: 0}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 0, want: 0}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 1, want: -4294967296}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 1, want: -4294967296}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 4294967296, want: 0}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 9223372036854775806, want: 8589934592}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 9223372036854775806, want: 8589934592}, test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 9223372036854775807, want: 4294967296}, test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 9223372036854775807, want: 4294967296}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: -9223372036854775807, want: 9223372036854775807}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: -9223372036854775807, want: 9223372036854775807}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: -4294967296, want: 4294967296}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: -4294967296, want: 4294967296}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: -1, want: 1}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: -1, want: 1}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 0, want: 0}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 0, want: 0}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 1, want: -1}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 1, want: -1}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 4294967296, want: -4294967296}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 4294967296, want: -4294967296}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 9223372036854775806, want: -9223372036854775806}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 9223372036854775806, want: -9223372036854775806}, test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 9223372036854775807, want: -9223372036854775807}, test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 9223372036854775807, want: -9223372036854775807}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: -9223372036854775808, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: -9223372036854775807, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: -9223372036854775807, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: -4294967296, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: -4294967296, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: -1, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: -1, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 0, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 0, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 1, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 1, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 4294967296, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 4294967296, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 9223372036854775806, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 9223372036854775806, want: 0}, test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 9223372036854775807, want: 0}, test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 9223372036854775807, want: 0}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: -4294967296, want: -4294967296}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: -4294967296, want: -4294967296}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: -1, want: -1}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: -1, want: -1}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 0, want: 0}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 0, want: 0}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 1, want: 1}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 1, want: 1}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 4294967296, want: 4294967296}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 4294967296, want: 4294967296}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: -9223372036854775808, want: 0}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: -9223372036854775807, want: 4294967296}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: -9223372036854775807, want: 4294967296}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: -4294967296, want: 0}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: -1, want: -4294967296}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: -1, want: -4294967296}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 0, want: 0}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 0, want: 0}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 1, want: 4294967296}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 1, want: 4294967296}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 4294967296, want: 0}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 9223372036854775806, want: -8589934592}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 9223372036854775806, want: -8589934592}, test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 9223372036854775807, want: -4294967296}, test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 9223372036854775807, want: -4294967296}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: -9223372036854775808, want: 0}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: -9223372036854775807, want: 9223372036854775806}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: -9223372036854775807, want: 9223372036854775806}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: -4294967296, want: 8589934592}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: -4294967296, want: 8589934592}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: -1, want: -9223372036854775806}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: -1, want: -9223372036854775806}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 0, want: 0}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 0, want: 0}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 1, want: 9223372036854775806}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 1, want: 9223372036854775806}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 4294967296, want: -8589934592}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 4294967296, want: -8589934592}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 9223372036854775806, want: 4}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 9223372036854775806, want: 4}, test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 9223372036854775807, want: -9223372036854775806}, test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 9223372036854775807, want: -9223372036854775806}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: -9223372036854775807, want: -1}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: -9223372036854775807, want: -1}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: -4294967296, want: 4294967296}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: -4294967296, want: 4294967296}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: -1, want: -9223372036854775807}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: -1, want: -9223372036854775807}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 0, want: 0}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 0, want: 0}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 1, want: 9223372036854775807}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 1, want: 9223372036854775807}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 4294967296, want: -4294967296}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 4294967296, want: -4294967296}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 9223372036854775806, want: -9223372036854775806}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 9223372036854775806, want: -9223372036854775806}, test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 9223372036854775807, want: 1}, test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 9223372036854775807, want: 1}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: -9223372036854775807, want: -1}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: -4294967296, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: -4294967296, want: -4294967296}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: -1, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: -1, want: -1}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 0, want: 0}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: 1, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 1, want: 1}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: 4294967296, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 4294967296, want: 4294967296}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: 9223372036854775806, want: -2}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: -9223372036854775807, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: -9223372036854775807, want: 0}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: -4294967296, want: -4294967295}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: -4294967296, want: -4294967296}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: -1, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: -1, want: -1}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 0, want: 0}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: 1, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 1, want: 1}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: 4294967296, want: -4294967295}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 4294967296, want: 4294967296}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: 9223372036854775807, want: 0}, test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 9223372036854775807, want: 0}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: -9223372036854775808, want: -4294967296}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: -9223372036854775808, want: 0}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: -9223372036854775807, want: -4294967296}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: -9223372036854775807, want: -4294967295}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: -4294967296, want: 0}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: -1, want: 0}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: -1, want: -1}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 0, want: 0}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: 1, want: 0}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 1, want: 1}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 4294967296, want: 0}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: 9223372036854775806, want: -4294967296}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 9223372036854775806, want: 4294967294}, test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: 9223372036854775807, want: -4294967296}, test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 9223372036854775807, want: 4294967295}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: -9223372036854775808, want: -1}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: -9223372036854775808, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: -9223372036854775807, want: -1}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: -9223372036854775807, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: -4294967296, want: -1}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: -4294967296, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: -1, want: 0}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: -1, want: 0}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 0, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: 1, want: 0}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 1, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: 4294967296, want: -1}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 4294967296, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: 9223372036854775806, want: -1}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 9223372036854775806, want: 0}, test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: 9223372036854775807, want: -1}, test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 9223372036854775807, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: -9223372036854775808, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: -9223372036854775807, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: -4294967296, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: -1, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: 1, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: 4294967296, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: 9223372036854775806, want: 0}, test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: 9223372036854775807, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: -9223372036854775808, want: 1}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: -9223372036854775808, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: -9223372036854775807, want: 1}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: -9223372036854775807, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: -4294967296, want: 1}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: -4294967296, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: -1, want: 0}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: -1, want: 0}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 0, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: 1, want: 0}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 1, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: 4294967296, want: 1}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 4294967296, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: 9223372036854775806, want: 1}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 9223372036854775806, want: 0}, test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: 9223372036854775807, want: 1}, test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 9223372036854775807, want: 0}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: -9223372036854775808, want: 4294967296}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: -9223372036854775808, want: 0}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: -9223372036854775807, want: 4294967296}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: -9223372036854775807, want: -4294967295}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: -4294967296, want: 0}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: -1, want: 0}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: -1, want: -1}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 0, want: 0}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: 1, want: 0}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 1, want: 1}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 4294967296, want: 0}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: 9223372036854775806, want: 4294967296}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 9223372036854775806, want: 4294967294}, test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: 9223372036854775807, want: 4294967296}, test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 9223372036854775807, want: 4294967295}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: -9223372036854775808, want: 9223372036854775806}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: -9223372036854775808, want: -2}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: -9223372036854775807, want: 9223372036854775806}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: -9223372036854775807, want: -1}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: -4294967296, want: 4294967294}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: -4294967296, want: -4294967296}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: -1, want: 0}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: -1, want: -1}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 0, want: 0}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: 1, want: 0}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 1, want: 1}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: 4294967296, want: 4294967294}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 4294967296, want: 4294967296}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: 9223372036854775806, want: 0}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 9223372036854775806, want: 0}, test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 9223372036854775807, want: 1}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: -9223372036854775807, want: 0}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: -9223372036854775807, want: 0}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: -4294967296, want: 4294967295}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: -4294967296, want: -4294967296}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: -1, want: 0}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: -1, want: -1}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 0, want: 0}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: 1, want: 0}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 1, want: 1}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: 4294967296, want: 4294967295}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 4294967296, want: 4294967296}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: 9223372036854775806, want: 1}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: 9223372036854775807, want: 0}, test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 9223372036854775807, want: 0}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: -4294967296, want: -9223372036854775808}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: -4294967296, want: -9223372036854775808}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: -1, want: -9223372036854775808}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: -1, want: -9223372036854775808}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 0, want: 0}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 0, want: 0}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 1, want: 0}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 1, want: 0}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 4294967296, want: 0}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 4294967296, want: 0}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 9223372036854775806, want: 0}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 9223372036854775806, want: 0}, test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 9223372036854775807, want: 0}, test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 9223372036854775807, want: 0}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: -4294967296, want: -9223372036854775808}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: -4294967296, want: -9223372036854775808}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: -1, want: -9223372036854775807}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: -1, want: -9223372036854775807}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 0, want: 0}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 0, want: 0}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 1, want: 1}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 1, want: 1}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 4294967296, want: 0}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 4294967296, want: 0}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 9223372036854775806, want: 0}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 9223372036854775806, want: 0}, test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 9223372036854775807, want: 1}, test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 9223372036854775807, want: 1}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: -4294967296, want: -4294967296}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: -4294967296, want: -4294967296}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: -1, want: -4294967296}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: -1, want: -4294967296}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 0, want: 0}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 0, want: 0}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 1, want: 0}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 1, want: 0}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 4294967296, want: 4294967296}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 4294967296, want: 4294967296}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 9223372036854775806, want: 9223372032559808512}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 9223372036854775806, want: 9223372032559808512}, test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 9223372036854775807, want: 9223372032559808512}, test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 9223372036854775807, want: 9223372032559808512}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: -4294967296, want: -4294967296}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: -4294967296, want: -4294967296}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: -1, want: -1}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: -1, want: -1}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 0, want: 0}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 0, want: 0}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 1, want: 1}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 1, want: 1}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 4294967296, want: 4294967296}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 4294967296, want: 4294967296}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: -9223372036854775808, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: -9223372036854775808, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: -9223372036854775807, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: -9223372036854775807, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: -4294967296, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: -4294967296, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: -1, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: -1, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 0, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 0, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 1, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 1, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 4294967296, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 4294967296, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 9223372036854775806, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 9223372036854775806, want: 0}, test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 9223372036854775807, want: 0}, test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 9223372036854775807, want: 0}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: -9223372036854775808, want: 0}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: -9223372036854775808, want: 0}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: -9223372036854775807, want: 1}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: -9223372036854775807, want: 1}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: -4294967296, want: 0}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: -4294967296, want: 0}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: -1, want: 1}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: -1, want: 1}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 0, want: 0}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 0, want: 0}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 1, want: 1}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 1, want: 1}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 4294967296, want: 0}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 4294967296, want: 0}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 9223372036854775806, want: 0}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 9223372036854775806, want: 0}, test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 9223372036854775807, want: 1}, test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 9223372036854775807, want: 1}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: -9223372036854775808, want: 0}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: -9223372036854775808, want: 0}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: -9223372036854775807, want: 0}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: -9223372036854775807, want: 0}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: -4294967296, want: 4294967296}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: -4294967296, want: 4294967296}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: -1, want: 4294967296}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: -1, want: 4294967296}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 0, want: 0}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 0, want: 0}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 1, want: 0}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 1, want: 0}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 4294967296, want: 4294967296}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 4294967296, want: 4294967296}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 9223372036854775806, want: 4294967296}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 9223372036854775806, want: 4294967296}, test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 9223372036854775807, want: 4294967296}, test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 9223372036854775807, want: 4294967296}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: -9223372036854775808, want: 0}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: -9223372036854775808, want: 0}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: -9223372036854775807, want: 0}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: -9223372036854775807, want: 0}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: -4294967296, want: 9223372032559808512}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: -4294967296, want: 9223372032559808512}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: -1, want: 9223372036854775806}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: -1, want: 9223372036854775806}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 0, want: 0}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 0, want: 0}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 1, want: 0}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 1, want: 0}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 4294967296, want: 4294967296}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 4294967296, want: 4294967296}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: -9223372036854775808, want: 0}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: -9223372036854775808, want: 0}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: -9223372036854775807, want: 1}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: -9223372036854775807, want: 1}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: -4294967296, want: 9223372032559808512}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: -4294967296, want: 9223372032559808512}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: -1, want: 9223372036854775807}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: -1, want: 9223372036854775807}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 0, want: 0}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 0, want: 0}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 1, want: 1}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 1, want: 1}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 4294967296, want: 4294967296}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 4294967296, want: 4294967296}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: -4294967296, want: -4294967296}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: -4294967296, want: -4294967296}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: -1, want: -1}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: -1, want: -1}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 0, want: -9223372036854775808}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 0, want: -9223372036854775808}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 1, want: -9223372036854775807}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 1, want: -9223372036854775807}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 4294967296, want: -9223372032559808512}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 4294967296, want: -9223372032559808512}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 9223372036854775806, want: -2}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 9223372036854775806, want: -2}, test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 9223372036854775807, want: -1}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: -4294967296, want: -4294967295}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: -4294967296, want: -4294967295}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: -1, want: -1}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: -1, want: -1}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 0, want: -9223372036854775807}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 0, want: -9223372036854775807}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 1, want: -9223372036854775807}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 1, want: -9223372036854775807}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 4294967296, want: -9223372032559808511}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 4294967296, want: -9223372032559808511}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 9223372036854775806, want: -1}, test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 9223372036854775807, want: -1}, test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 9223372036854775807, want: -1}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: -9223372036854775808, want: -4294967296}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: -9223372036854775808, want: -4294967296}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: -9223372036854775807, want: -4294967295}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: -9223372036854775807, want: -4294967295}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: -4294967296, want: -4294967296}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: -4294967296, want: -4294967296}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: -1, want: -1}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: -1, want: -1}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 0, want: -4294967296}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 0, want: -4294967296}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 1, want: -4294967295}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 1, want: -4294967295}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 4294967296, want: -4294967296}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 4294967296, want: -4294967296}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 9223372036854775806, want: -2}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 9223372036854775806, want: -2}, test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 9223372036854775807, want: -1}, test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 9223372036854775807, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: -9223372036854775808, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: -9223372036854775808, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: -9223372036854775807, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: -9223372036854775807, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: -4294967296, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: -4294967296, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: -1, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: -1, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 0, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 0, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 1, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 1, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 4294967296, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 4294967296, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 9223372036854775806, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 9223372036854775806, want: -1}, test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 9223372036854775807, want: -1}, test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 9223372036854775807, want: -1}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: -4294967296, want: -4294967296}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: -4294967296, want: -4294967296}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: -1, want: -1}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: -1, want: -1}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 0, want: 0}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 0, want: 0}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 1, want: 1}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 1, want: 1}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 4294967296, want: 4294967296}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 4294967296, want: 4294967296}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: -4294967296, want: -4294967295}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: -4294967296, want: -4294967295}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: -1, want: -1}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: -1, want: -1}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 0, want: 1}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 0, want: 1}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 1, want: 1}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 1, want: 1}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 4294967296, want: 4294967297}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 4294967296, want: 4294967297}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: -4294967296, want: -4294967296}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: -4294967296, want: -4294967296}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: -1, want: -1}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: -1, want: -1}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 0, want: 4294967296}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 0, want: 4294967296}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 1, want: 4294967297}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 1, want: 4294967297}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 4294967296, want: 4294967296}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 4294967296, want: 4294967296}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: -9223372036854775808, want: -2}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: -9223372036854775808, want: -2}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: -9223372036854775807, want: -1}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: -9223372036854775807, want: -1}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: -4294967296, want: -2}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: -4294967296, want: -2}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: -1, want: -1}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: -1, want: -1}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 0, want: 9223372036854775806}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 0, want: 9223372036854775806}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 1, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 1, want: 9223372036854775807}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 4294967296, want: 9223372036854775806}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 4294967296, want: 9223372036854775806}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: -9223372036854775808, want: -1}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: -9223372036854775807, want: -1}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: -9223372036854775807, want: -1}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: -4294967296, want: -1}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: -4294967296, want: -1}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: -1, want: -1}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: -1, want: -1}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 0, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 0, want: 9223372036854775807}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 1, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 1, want: 9223372036854775807}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 4294967296, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 4294967296, want: 9223372036854775807}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: -9223372036854775807, want: 1}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: -9223372036854775807, want: 1}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: -4294967296, want: 9223372032559808512}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: -4294967296, want: 9223372032559808512}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: -1, want: 9223372036854775807}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: -1, want: 9223372036854775807}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 0, want: -9223372036854775808}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 0, want: -9223372036854775808}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 1, want: -9223372036854775807}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 1, want: -9223372036854775807}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 4294967296, want: -9223372032559808512}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 4294967296, want: -9223372032559808512}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 9223372036854775806, want: -2}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 9223372036854775806, want: -2}, test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 9223372036854775807, want: -1}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: -9223372036854775808, want: 1}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: -9223372036854775808, want: 1}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: -9223372036854775807, want: 0}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: -9223372036854775807, want: 0}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: -4294967296, want: 9223372032559808513}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: -4294967296, want: 9223372032559808513}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: -1, want: 9223372036854775806}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: -1, want: 9223372036854775806}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 0, want: -9223372036854775807}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 0, want: -9223372036854775807}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 1, want: -9223372036854775808}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 1, want: -9223372036854775808}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 4294967296, want: -9223372032559808511}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 4294967296, want: -9223372032559808511}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 9223372036854775806, want: -1}, test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 9223372036854775807, want: -2}, test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 9223372036854775807, want: -2}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: -9223372036854775808, want: 9223372032559808512}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: -9223372036854775808, want: 9223372032559808512}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: -9223372036854775807, want: 9223372032559808513}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: -9223372036854775807, want: 9223372032559808513}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: -4294967296, want: 0}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: -4294967296, want: 0}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: -1, want: 4294967295}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: -1, want: 4294967295}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 0, want: -4294967296}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 0, want: -4294967296}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 1, want: -4294967295}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 1, want: -4294967295}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 4294967296, want: -8589934592}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 4294967296, want: -8589934592}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 9223372036854775806, want: -9223372032559808514}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 9223372036854775806, want: -9223372032559808514}, test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 9223372036854775807, want: -9223372032559808513}, test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 9223372036854775807, want: -9223372032559808513}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: -9223372036854775808, want: 9223372036854775807}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: -9223372036854775807, want: 9223372036854775806}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: -9223372036854775807, want: 9223372036854775806}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: -4294967296, want: 4294967295}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: -4294967296, want: 4294967295}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: -1, want: 0}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: -1, want: 0}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 0, want: -1}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 0, want: -1}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 1, want: -2}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 1, want: -2}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 4294967296, want: -4294967297}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 4294967296, want: -4294967297}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 9223372036854775806, want: -9223372036854775807}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 9223372036854775806, want: -9223372036854775807}, test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 9223372036854775807, want: -9223372036854775808}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: -9223372036854775808, want: -9223372036854775808}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: -9223372036854775807, want: -9223372036854775807}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: -4294967296, want: -4294967296}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: -4294967296, want: -4294967296}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: -1, want: -1}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: -1, want: -1}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 0, want: 0}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 0, want: 0}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 1, want: 1}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 1, want: 1}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 4294967296, want: 4294967296}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 4294967296, want: 4294967296}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 9223372036854775806, want: 9223372036854775806}, test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 9223372036854775807, want: 9223372036854775807}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: -9223372036854775808, want: -9223372036854775807}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: -9223372036854775807, want: -9223372036854775808}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: -4294967296, want: -4294967295}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: -4294967296, want: -4294967295}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: -1, want: -2}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: -1, want: -2}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 0, want: 1}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 0, want: 1}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 1, want: 0}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 1, want: 0}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 4294967296, want: 4294967297}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 4294967296, want: 4294967297}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 9223372036854775806, want: 9223372036854775807}, test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 9223372036854775807, want: 9223372036854775806}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: -9223372036854775808, want: -9223372032559808512}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: -9223372036854775807, want: -9223372032559808511}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: -4294967296, want: -8589934592}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: -4294967296, want: -8589934592}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: -1, want: -4294967297}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: -1, want: -4294967297}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 0, want: 4294967296}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 0, want: 4294967296}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 1, want: 4294967297}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 1, want: 4294967297}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 4294967296, want: 0}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 4294967296, want: 0}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 9223372036854775806, want: 9223372032559808510}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 9223372036854775806, want: 9223372032559808510}, test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 9223372036854775807, want: 9223372032559808511}, test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 9223372036854775807, want: 9223372032559808511}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: -9223372036854775808, want: -2}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: -9223372036854775808, want: -2}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: -9223372036854775807, want: -1}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: -9223372036854775807, want: -1}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: -4294967296, want: -9223372032559808514}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: -4294967296, want: -9223372032559808514}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: -1, want: -9223372036854775807}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: -1, want: -9223372036854775807}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 0, want: 9223372036854775806}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 0, want: 9223372036854775806}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 1, want: 9223372036854775807}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 1, want: 9223372036854775807}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 4294967296, want: 9223372032559808510}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 4294967296, want: 9223372032559808510}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 9223372036854775806, want: 0}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 9223372036854775806, want: 0}, test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 9223372036854775807, want: 1}, test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 9223372036854775807, want: 1}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: -9223372036854775808, want: -1}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: -9223372036854775808, want: -1}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: -9223372036854775807, want: -2}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: -9223372036854775807, want: -2}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: -4294967296, want: -9223372032559808513}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: -4294967296, want: -9223372032559808513}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: -1, want: -9223372036854775808}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: -1, want: -9223372036854775808}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 0, want: 9223372036854775807}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 0, want: 9223372036854775807}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 1, want: 9223372036854775806}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 1, want: 9223372036854775806}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 4294967296, want: 9223372032559808511}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 4294967296, want: 9223372032559808511}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 9223372036854775806, want: 1}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 9223372036854775806, want: 1}, test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 9223372036854775807, want: 0}, test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 9223372036854775807, want: 0}} type test_uint32 struct { fn func(uint32) uint32 fnname string in uint32 want uint32 } var tests_uint32 = []test_uint32{ test_uint32{fn: add_0_uint32, fnname: "add_0_uint32", in: 0, want: 0}, test_uint32{fn: add_uint32_0, fnname: "add_uint32_0", in: 0, want: 0}, test_uint32{fn: add_0_uint32, fnname: "add_0_uint32", in: 1, want: 1}, test_uint32{fn: add_uint32_0, fnname: "add_uint32_0", in: 1, want: 1}, test_uint32{fn: add_0_uint32, fnname: "add_0_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: add_uint32_0, fnname: "add_uint32_0", in: 4294967295, want: 4294967295}, test_uint32{fn: add_1_uint32, fnname: "add_1_uint32", in: 0, want: 1}, test_uint32{fn: add_uint32_1, fnname: "add_uint32_1", in: 0, want: 1}, test_uint32{fn: add_1_uint32, fnname: "add_1_uint32", in: 1, want: 2}, test_uint32{fn: add_uint32_1, fnname: "add_uint32_1", in: 1, want: 2}, test_uint32{fn: add_1_uint32, fnname: "add_1_uint32", in: 4294967295, want: 0}, test_uint32{fn: add_uint32_1, fnname: "add_uint32_1", in: 4294967295, want: 0}, test_uint32{fn: add_4294967295_uint32, fnname: "add_4294967295_uint32", in: 0, want: 4294967295}, test_uint32{fn: add_uint32_4294967295, fnname: "add_uint32_4294967295", in: 0, want: 4294967295}, test_uint32{fn: add_4294967295_uint32, fnname: "add_4294967295_uint32", in: 1, want: 0}, test_uint32{fn: add_uint32_4294967295, fnname: "add_uint32_4294967295", in: 1, want: 0}, test_uint32{fn: add_4294967295_uint32, fnname: "add_4294967295_uint32", in: 4294967295, want: 4294967294}, test_uint32{fn: add_uint32_4294967295, fnname: "add_uint32_4294967295", in: 4294967295, want: 4294967294}, test_uint32{fn: sub_0_uint32, fnname: "sub_0_uint32", in: 0, want: 0}, test_uint32{fn: sub_uint32_0, fnname: "sub_uint32_0", in: 0, want: 0}, test_uint32{fn: sub_0_uint32, fnname: "sub_0_uint32", in: 1, want: 4294967295}, test_uint32{fn: sub_uint32_0, fnname: "sub_uint32_0", in: 1, want: 1}, test_uint32{fn: sub_0_uint32, fnname: "sub_0_uint32", in: 4294967295, want: 1}, test_uint32{fn: sub_uint32_0, fnname: "sub_uint32_0", in: 4294967295, want: 4294967295}, test_uint32{fn: sub_1_uint32, fnname: "sub_1_uint32", in: 0, want: 1}, test_uint32{fn: sub_uint32_1, fnname: "sub_uint32_1", in: 0, want: 4294967295}, test_uint32{fn: sub_1_uint32, fnname: "sub_1_uint32", in: 1, want: 0}, test_uint32{fn: sub_uint32_1, fnname: "sub_uint32_1", in: 1, want: 0}, test_uint32{fn: sub_1_uint32, fnname: "sub_1_uint32", in: 4294967295, want: 2}, test_uint32{fn: sub_uint32_1, fnname: "sub_uint32_1", in: 4294967295, want: 4294967294}, test_uint32{fn: sub_4294967295_uint32, fnname: "sub_4294967295_uint32", in: 0, want: 4294967295}, test_uint32{fn: sub_uint32_4294967295, fnname: "sub_uint32_4294967295", in: 0, want: 1}, test_uint32{fn: sub_4294967295_uint32, fnname: "sub_4294967295_uint32", in: 1, want: 4294967294}, test_uint32{fn: sub_uint32_4294967295, fnname: "sub_uint32_4294967295", in: 1, want: 2}, test_uint32{fn: sub_4294967295_uint32, fnname: "sub_4294967295_uint32", in: 4294967295, want: 0}, test_uint32{fn: sub_uint32_4294967295, fnname: "sub_uint32_4294967295", in: 4294967295, want: 0}, test_uint32{fn: div_0_uint32, fnname: "div_0_uint32", in: 1, want: 0}, test_uint32{fn: div_0_uint32, fnname: "div_0_uint32", in: 4294967295, want: 0}, test_uint32{fn: div_uint32_1, fnname: "div_uint32_1", in: 0, want: 0}, test_uint32{fn: div_1_uint32, fnname: "div_1_uint32", in: 1, want: 1}, test_uint32{fn: div_uint32_1, fnname: "div_uint32_1", in: 1, want: 1}, test_uint32{fn: div_1_uint32, fnname: "div_1_uint32", in: 4294967295, want: 0}, test_uint32{fn: div_uint32_1, fnname: "div_uint32_1", in: 4294967295, want: 4294967295}, test_uint32{fn: div_uint32_4294967295, fnname: "div_uint32_4294967295", in: 0, want: 0}, test_uint32{fn: div_4294967295_uint32, fnname: "div_4294967295_uint32", in: 1, want: 4294967295}, test_uint32{fn: div_uint32_4294967295, fnname: "div_uint32_4294967295", in: 1, want: 0}, test_uint32{fn: div_4294967295_uint32, fnname: "div_4294967295_uint32", in: 4294967295, want: 1}, test_uint32{fn: div_uint32_4294967295, fnname: "div_uint32_4294967295", in: 4294967295, want: 1}, test_uint32{fn: mul_0_uint32, fnname: "mul_0_uint32", in: 0, want: 0}, test_uint32{fn: mul_uint32_0, fnname: "mul_uint32_0", in: 0, want: 0}, test_uint32{fn: mul_0_uint32, fnname: "mul_0_uint32", in: 1, want: 0}, test_uint32{fn: mul_uint32_0, fnname: "mul_uint32_0", in: 1, want: 0}, test_uint32{fn: mul_0_uint32, fnname: "mul_0_uint32", in: 4294967295, want: 0}, test_uint32{fn: mul_uint32_0, fnname: "mul_uint32_0", in: 4294967295, want: 0}, test_uint32{fn: mul_1_uint32, fnname: "mul_1_uint32", in: 0, want: 0}, test_uint32{fn: mul_uint32_1, fnname: "mul_uint32_1", in: 0, want: 0}, test_uint32{fn: mul_1_uint32, fnname: "mul_1_uint32", in: 1, want: 1}, test_uint32{fn: mul_uint32_1, fnname: "mul_uint32_1", in: 1, want: 1}, test_uint32{fn: mul_1_uint32, fnname: "mul_1_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: mul_uint32_1, fnname: "mul_uint32_1", in: 4294967295, want: 4294967295}, test_uint32{fn: mul_4294967295_uint32, fnname: "mul_4294967295_uint32", in: 0, want: 0}, test_uint32{fn: mul_uint32_4294967295, fnname: "mul_uint32_4294967295", in: 0, want: 0}, test_uint32{fn: mul_4294967295_uint32, fnname: "mul_4294967295_uint32", in: 1, want: 4294967295}, test_uint32{fn: mul_uint32_4294967295, fnname: "mul_uint32_4294967295", in: 1, want: 4294967295}, test_uint32{fn: mul_4294967295_uint32, fnname: "mul_4294967295_uint32", in: 4294967295, want: 1}, test_uint32{fn: mul_uint32_4294967295, fnname: "mul_uint32_4294967295", in: 4294967295, want: 1}, test_uint32{fn: lsh_0_uint32, fnname: "lsh_0_uint32", in: 0, want: 0}, test_uint32{fn: lsh_uint32_0, fnname: "lsh_uint32_0", in: 0, want: 0}, test_uint32{fn: lsh_0_uint32, fnname: "lsh_0_uint32", in: 1, want: 0}, test_uint32{fn: lsh_uint32_0, fnname: "lsh_uint32_0", in: 1, want: 1}, test_uint32{fn: lsh_0_uint32, fnname: "lsh_0_uint32", in: 4294967295, want: 0}, test_uint32{fn: lsh_uint32_0, fnname: "lsh_uint32_0", in: 4294967295, want: 4294967295}, test_uint32{fn: lsh_1_uint32, fnname: "lsh_1_uint32", in: 0, want: 1}, test_uint32{fn: lsh_uint32_1, fnname: "lsh_uint32_1", in: 0, want: 0}, test_uint32{fn: lsh_1_uint32, fnname: "lsh_1_uint32", in: 1, want: 2}, test_uint32{fn: lsh_uint32_1, fnname: "lsh_uint32_1", in: 1, want: 2}, test_uint32{fn: lsh_1_uint32, fnname: "lsh_1_uint32", in: 4294967295, want: 0}, test_uint32{fn: lsh_uint32_1, fnname: "lsh_uint32_1", in: 4294967295, want: 4294967294}, test_uint32{fn: lsh_4294967295_uint32, fnname: "lsh_4294967295_uint32", in: 0, want: 4294967295}, test_uint32{fn: lsh_uint32_4294967295, fnname: "lsh_uint32_4294967295", in: 0, want: 0}, test_uint32{fn: lsh_4294967295_uint32, fnname: "lsh_4294967295_uint32", in: 1, want: 4294967294}, test_uint32{fn: lsh_uint32_4294967295, fnname: "lsh_uint32_4294967295", in: 1, want: 0}, test_uint32{fn: lsh_4294967295_uint32, fnname: "lsh_4294967295_uint32", in: 4294967295, want: 0}, test_uint32{fn: lsh_uint32_4294967295, fnname: "lsh_uint32_4294967295", in: 4294967295, want: 0}, test_uint32{fn: rsh_0_uint32, fnname: "rsh_0_uint32", in: 0, want: 0}, test_uint32{fn: rsh_uint32_0, fnname: "rsh_uint32_0", in: 0, want: 0}, test_uint32{fn: rsh_0_uint32, fnname: "rsh_0_uint32", in: 1, want: 0}, test_uint32{fn: rsh_uint32_0, fnname: "rsh_uint32_0", in: 1, want: 1}, test_uint32{fn: rsh_0_uint32, fnname: "rsh_0_uint32", in: 4294967295, want: 0}, test_uint32{fn: rsh_uint32_0, fnname: "rsh_uint32_0", in: 4294967295, want: 4294967295}, test_uint32{fn: rsh_1_uint32, fnname: "rsh_1_uint32", in: 0, want: 1}, test_uint32{fn: rsh_uint32_1, fnname: "rsh_uint32_1", in: 0, want: 0}, test_uint32{fn: rsh_1_uint32, fnname: "rsh_1_uint32", in: 1, want: 0}, test_uint32{fn: rsh_uint32_1, fnname: "rsh_uint32_1", in: 1, want: 0}, test_uint32{fn: rsh_1_uint32, fnname: "rsh_1_uint32", in: 4294967295, want: 0}, test_uint32{fn: rsh_uint32_1, fnname: "rsh_uint32_1", in: 4294967295, want: 2147483647}, test_uint32{fn: rsh_4294967295_uint32, fnname: "rsh_4294967295_uint32", in: 0, want: 4294967295}, test_uint32{fn: rsh_uint32_4294967295, fnname: "rsh_uint32_4294967295", in: 0, want: 0}, test_uint32{fn: rsh_4294967295_uint32, fnname: "rsh_4294967295_uint32", in: 1, want: 2147483647}, test_uint32{fn: rsh_uint32_4294967295, fnname: "rsh_uint32_4294967295", in: 1, want: 0}, test_uint32{fn: rsh_4294967295_uint32, fnname: "rsh_4294967295_uint32", in: 4294967295, want: 0}, test_uint32{fn: rsh_uint32_4294967295, fnname: "rsh_uint32_4294967295", in: 4294967295, want: 0}, test_uint32{fn: mod_0_uint32, fnname: "mod_0_uint32", in: 1, want: 0}, test_uint32{fn: mod_0_uint32, fnname: "mod_0_uint32", in: 4294967295, want: 0}, test_uint32{fn: mod_uint32_1, fnname: "mod_uint32_1", in: 0, want: 0}, test_uint32{fn: mod_1_uint32, fnname: "mod_1_uint32", in: 1, want: 0}, test_uint32{fn: mod_uint32_1, fnname: "mod_uint32_1", in: 1, want: 0}, test_uint32{fn: mod_1_uint32, fnname: "mod_1_uint32", in: 4294967295, want: 1}, test_uint32{fn: mod_uint32_1, fnname: "mod_uint32_1", in: 4294967295, want: 0}, test_uint32{fn: mod_uint32_4294967295, fnname: "mod_uint32_4294967295", in: 0, want: 0}, test_uint32{fn: mod_4294967295_uint32, fnname: "mod_4294967295_uint32", in: 1, want: 0}, test_uint32{fn: mod_uint32_4294967295, fnname: "mod_uint32_4294967295", in: 1, want: 1}, test_uint32{fn: mod_4294967295_uint32, fnname: "mod_4294967295_uint32", in: 4294967295, want: 0}, test_uint32{fn: mod_uint32_4294967295, fnname: "mod_uint32_4294967295", in: 4294967295, want: 0}, test_uint32{fn: and_0_uint32, fnname: "and_0_uint32", in: 0, want: 0}, test_uint32{fn: and_uint32_0, fnname: "and_uint32_0", in: 0, want: 0}, test_uint32{fn: and_0_uint32, fnname: "and_0_uint32", in: 1, want: 0}, test_uint32{fn: and_uint32_0, fnname: "and_uint32_0", in: 1, want: 0}, test_uint32{fn: and_0_uint32, fnname: "and_0_uint32", in: 4294967295, want: 0}, test_uint32{fn: and_uint32_0, fnname: "and_uint32_0", in: 4294967295, want: 0}, test_uint32{fn: and_1_uint32, fnname: "and_1_uint32", in: 0, want: 0}, test_uint32{fn: and_uint32_1, fnname: "and_uint32_1", in: 0, want: 0}, test_uint32{fn: and_1_uint32, fnname: "and_1_uint32", in: 1, want: 1}, test_uint32{fn: and_uint32_1, fnname: "and_uint32_1", in: 1, want: 1}, test_uint32{fn: and_1_uint32, fnname: "and_1_uint32", in: 4294967295, want: 1}, test_uint32{fn: and_uint32_1, fnname: "and_uint32_1", in: 4294967295, want: 1}, test_uint32{fn: and_4294967295_uint32, fnname: "and_4294967295_uint32", in: 0, want: 0}, test_uint32{fn: and_uint32_4294967295, fnname: "and_uint32_4294967295", in: 0, want: 0}, test_uint32{fn: and_4294967295_uint32, fnname: "and_4294967295_uint32", in: 1, want: 1}, test_uint32{fn: and_uint32_4294967295, fnname: "and_uint32_4294967295", in: 1, want: 1}, test_uint32{fn: and_4294967295_uint32, fnname: "and_4294967295_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: and_uint32_4294967295, fnname: "and_uint32_4294967295", in: 4294967295, want: 4294967295}, test_uint32{fn: or_0_uint32, fnname: "or_0_uint32", in: 0, want: 0}, test_uint32{fn: or_uint32_0, fnname: "or_uint32_0", in: 0, want: 0}, test_uint32{fn: or_0_uint32, fnname: "or_0_uint32", in: 1, want: 1}, test_uint32{fn: or_uint32_0, fnname: "or_uint32_0", in: 1, want: 1}, test_uint32{fn: or_0_uint32, fnname: "or_0_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: or_uint32_0, fnname: "or_uint32_0", in: 4294967295, want: 4294967295}, test_uint32{fn: or_1_uint32, fnname: "or_1_uint32", in: 0, want: 1}, test_uint32{fn: or_uint32_1, fnname: "or_uint32_1", in: 0, want: 1}, test_uint32{fn: or_1_uint32, fnname: "or_1_uint32", in: 1, want: 1}, test_uint32{fn: or_uint32_1, fnname: "or_uint32_1", in: 1, want: 1}, test_uint32{fn: or_1_uint32, fnname: "or_1_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: or_uint32_1, fnname: "or_uint32_1", in: 4294967295, want: 4294967295}, test_uint32{fn: or_4294967295_uint32, fnname: "or_4294967295_uint32", in: 0, want: 4294967295}, test_uint32{fn: or_uint32_4294967295, fnname: "or_uint32_4294967295", in: 0, want: 4294967295}, test_uint32{fn: or_4294967295_uint32, fnname: "or_4294967295_uint32", in: 1, want: 4294967295}, test_uint32{fn: or_uint32_4294967295, fnname: "or_uint32_4294967295", in: 1, want: 4294967295}, test_uint32{fn: or_4294967295_uint32, fnname: "or_4294967295_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: or_uint32_4294967295, fnname: "or_uint32_4294967295", in: 4294967295, want: 4294967295}, test_uint32{fn: xor_0_uint32, fnname: "xor_0_uint32", in: 0, want: 0}, test_uint32{fn: xor_uint32_0, fnname: "xor_uint32_0", in: 0, want: 0}, test_uint32{fn: xor_0_uint32, fnname: "xor_0_uint32", in: 1, want: 1}, test_uint32{fn: xor_uint32_0, fnname: "xor_uint32_0", in: 1, want: 1}, test_uint32{fn: xor_0_uint32, fnname: "xor_0_uint32", in: 4294967295, want: 4294967295}, test_uint32{fn: xor_uint32_0, fnname: "xor_uint32_0", in: 4294967295, want: 4294967295}, test_uint32{fn: xor_1_uint32, fnname: "xor_1_uint32", in: 0, want: 1}, test_uint32{fn: xor_uint32_1, fnname: "xor_uint32_1", in: 0, want: 1}, test_uint32{fn: xor_1_uint32, fnname: "xor_1_uint32", in: 1, want: 0}, test_uint32{fn: xor_uint32_1, fnname: "xor_uint32_1", in: 1, want: 0}, test_uint32{fn: xor_1_uint32, fnname: "xor_1_uint32", in: 4294967295, want: 4294967294}, test_uint32{fn: xor_uint32_1, fnname: "xor_uint32_1", in: 4294967295, want: 4294967294}, test_uint32{fn: xor_4294967295_uint32, fnname: "xor_4294967295_uint32", in: 0, want: 4294967295}, test_uint32{fn: xor_uint32_4294967295, fnname: "xor_uint32_4294967295", in: 0, want: 4294967295}, test_uint32{fn: xor_4294967295_uint32, fnname: "xor_4294967295_uint32", in: 1, want: 4294967294}, test_uint32{fn: xor_uint32_4294967295, fnname: "xor_uint32_4294967295", in: 1, want: 4294967294}, test_uint32{fn: xor_4294967295_uint32, fnname: "xor_4294967295_uint32", in: 4294967295, want: 0}, test_uint32{fn: xor_uint32_4294967295, fnname: "xor_uint32_4294967295", in: 4294967295, want: 0}} type test_int32 struct { fn func(int32) int32 fnname string in int32 want int32 } var tests_int32 = []test_int32{ test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: -2147483648, want: 0}, test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: -2147483648, want: 0}, test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: -2147483647, want: 1}, test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: -2147483647, want: 1}, test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: -1, want: 2147483647}, test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: -1, want: 2147483647}, test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: 0, want: -2147483648}, test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: 0, want: -2147483648}, test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: 1, want: -2147483647}, test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: 1, want: -2147483647}, test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: 2147483647, want: -1}, test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: 2147483647, want: -1}, test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: -2147483648, want: 1}, test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: -2147483648, want: 1}, test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: -2147483647, want: 2}, test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: -2147483647, want: 2}, test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: -1, want: -2147483648}, test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: -1, want: -2147483648}, test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: 0, want: -2147483647}, test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: 0, want: -2147483647}, test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: 1, want: -2147483646}, test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: 1, want: -2147483646}, test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: 2147483647, want: 0}, test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: 2147483647, want: 0}, test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: -2147483648, want: 2147483647}, test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: -2147483648, want: 2147483647}, test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: -2147483647, want: -2147483648}, test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: -2147483647, want: -2147483648}, test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: -1, want: -2}, test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: -1, want: -2}, test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: 0, want: -1}, test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: 0, want: -1}, test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: 1, want: 0}, test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: 1, want: 0}, test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: 2147483647, want: 2147483646}, test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: 2147483647, want: 2147483646}, test_int32{fn: add_0_int32, fnname: "add_0_int32", in: -2147483648, want: -2147483648}, test_int32{fn: add_int32_0, fnname: "add_int32_0", in: -2147483648, want: -2147483648}, test_int32{fn: add_0_int32, fnname: "add_0_int32", in: -2147483647, want: -2147483647}, test_int32{fn: add_int32_0, fnname: "add_int32_0", in: -2147483647, want: -2147483647}, test_int32{fn: add_0_int32, fnname: "add_0_int32", in: -1, want: -1}, test_int32{fn: add_int32_0, fnname: "add_int32_0", in: -1, want: -1}, test_int32{fn: add_0_int32, fnname: "add_0_int32", in: 0, want: 0}, test_int32{fn: add_int32_0, fnname: "add_int32_0", in: 0, want: 0}, test_int32{fn: add_0_int32, fnname: "add_0_int32", in: 1, want: 1}, test_int32{fn: add_int32_0, fnname: "add_int32_0", in: 1, want: 1}, test_int32{fn: add_0_int32, fnname: "add_0_int32", in: 2147483647, want: 2147483647}, test_int32{fn: add_int32_0, fnname: "add_int32_0", in: 2147483647, want: 2147483647}, test_int32{fn: add_1_int32, fnname: "add_1_int32", in: -2147483648, want: -2147483647}, test_int32{fn: add_int32_1, fnname: "add_int32_1", in: -2147483648, want: -2147483647}, test_int32{fn: add_1_int32, fnname: "add_1_int32", in: -2147483647, want: -2147483646}, test_int32{fn: add_int32_1, fnname: "add_int32_1", in: -2147483647, want: -2147483646}, test_int32{fn: add_1_int32, fnname: "add_1_int32", in: -1, want: 0}, test_int32{fn: add_int32_1, fnname: "add_int32_1", in: -1, want: 0}, test_int32{fn: add_1_int32, fnname: "add_1_int32", in: 0, want: 1}, test_int32{fn: add_int32_1, fnname: "add_int32_1", in: 0, want: 1}, test_int32{fn: add_1_int32, fnname: "add_1_int32", in: 1, want: 2}, test_int32{fn: add_int32_1, fnname: "add_int32_1", in: 1, want: 2}, test_int32{fn: add_1_int32, fnname: "add_1_int32", in: 2147483647, want: -2147483648}, test_int32{fn: add_int32_1, fnname: "add_int32_1", in: 2147483647, want: -2147483648}, test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: -2147483648, want: -1}, test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: -2147483648, want: -1}, test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: -2147483647, want: 0}, test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: -2147483647, want: 0}, test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: -1, want: 2147483646}, test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: -1, want: 2147483646}, test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: 0, want: 2147483647}, test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: 0, want: 2147483647}, test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: 1, want: -2147483648}, test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: 1, want: -2147483648}, test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: 2147483647, want: -2}, test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: 2147483647, want: -2}, test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: -2147483648, want: 0}, test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: -2147483648, want: 0}, test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: -2147483647, want: -1}, test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: -2147483647, want: 1}, test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: -1, want: -2147483647}, test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: -1, want: 2147483647}, test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: 0, want: -2147483648}, test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: 0, want: -2147483648}, test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: 1, want: 2147483647}, test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: 1, want: -2147483647}, test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: 2147483647, want: 1}, test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: 2147483647, want: -1}, test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: -2147483648, want: 1}, test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: -2147483648, want: -1}, test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: -2147483647, want: 0}, test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: -2147483647, want: 0}, test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: -1, want: -2147483646}, test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: -1, want: 2147483646}, test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: 0, want: -2147483647}, test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: 0, want: 2147483647}, test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: 1, want: -2147483648}, test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: 1, want: -2147483648}, test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: 2147483647, want: 2}, test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: 2147483647, want: -2}, test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: -2147483648, want: 2147483647}, test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: -2147483648, want: -2147483647}, test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: -2147483647, want: 2147483646}, test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: -2147483647, want: -2147483646}, test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: -1, want: 0}, test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: -1, want: 0}, test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: 0, want: -1}, test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: 0, want: 1}, test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: 1, want: -2}, test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: 1, want: 2}, test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: 2147483647, want: -2147483648}, test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: 2147483647, want: -2147483648}, test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: -2147483648, want: -2147483648}, test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: -2147483648, want: -2147483648}, test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: -2147483647, want: 2147483647}, test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: -2147483647, want: -2147483647}, test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: -1, want: 1}, test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: -1, want: -1}, test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: 0, want: 0}, test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: 0, want: 0}, test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: 1, want: -1}, test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: 1, want: 1}, test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: 2147483647, want: -2147483647}, test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: 2147483647, want: 2147483647}, test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: -2147483648, want: -2147483647}, test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: -2147483648, want: 2147483647}, test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: -2147483647, want: -2147483648}, test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: -2147483647, want: -2147483648}, test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: -1, want: 2}, test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: -1, want: -2}, test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: 0, want: 1}, test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: 0, want: -1}, test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: 1, want: 0}, test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: 1, want: 0}, test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: 2147483647, want: -2147483646}, test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: 2147483647, want: 2147483646}, test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: -2147483648, want: -1}, test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: -2147483648, want: 1}, test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: -2147483647, want: -2}, test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: -2147483647, want: 2}, test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: -1, want: -2147483648}, test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: -1, want: -2147483648}, test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: 0, want: 2147483647}, test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: 0, want: -2147483647}, test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: 1, want: 2147483646}, test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: 1, want: -2147483646}, test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: 2147483647, want: 0}, test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: 2147483647, want: 0}, test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: -2147483648, want: 1}, test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: -2147483648, want: 1}, test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: -2147483647, want: 1}, test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: -2147483647, want: 0}, test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: -1, want: -2147483648}, test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: -1, want: 0}, test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: 0, want: 0}, test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: 1, want: -2147483648}, test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: 1, want: 0}, test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: 2147483647, want: -1}, test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: 2147483647, want: 0}, test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: -2147483648, want: 0}, test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: -2147483648, want: 1}, test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: -2147483647, want: 1}, test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: -2147483647, want: 1}, test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: -1, want: 2147483647}, test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: -1, want: 0}, test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: 0, want: 0}, test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: 1, want: -2147483647}, test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: 1, want: 0}, test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: 2147483647, want: -1}, test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: 2147483647, want: -1}, test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: -2147483648, want: 0}, test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: -2147483648, want: -2147483648}, test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: -2147483647, want: 0}, test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: -2147483647, want: 2147483647}, test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: -1, want: 1}, test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: -1, want: 1}, test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: 0, want: 0}, test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: 1, want: -1}, test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: 1, want: -1}, test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: 2147483647, want: 0}, test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: 2147483647, want: -2147483647}, test_int32{fn: div_0_int32, fnname: "div_0_int32", in: -2147483648, want: 0}, test_int32{fn: div_0_int32, fnname: "div_0_int32", in: -2147483647, want: 0}, test_int32{fn: div_0_int32, fnname: "div_0_int32", in: -1, want: 0}, test_int32{fn: div_0_int32, fnname: "div_0_int32", in: 1, want: 0}, test_int32{fn: div_0_int32, fnname: "div_0_int32", in: 2147483647, want: 0}, test_int32{fn: div_1_int32, fnname: "div_1_int32", in: -2147483648, want: 0}, test_int32{fn: div_int32_1, fnname: "div_int32_1", in: -2147483648, want: -2147483648}, test_int32{fn: div_1_int32, fnname: "div_1_int32", in: -2147483647, want: 0}, test_int32{fn: div_int32_1, fnname: "div_int32_1", in: -2147483647, want: -2147483647}, test_int32{fn: div_1_int32, fnname: "div_1_int32", in: -1, want: -1}, test_int32{fn: div_int32_1, fnname: "div_int32_1", in: -1, want: -1}, test_int32{fn: div_int32_1, fnname: "div_int32_1", in: 0, want: 0}, test_int32{fn: div_1_int32, fnname: "div_1_int32", in: 1, want: 1}, test_int32{fn: div_int32_1, fnname: "div_int32_1", in: 1, want: 1}, test_int32{fn: div_1_int32, fnname: "div_1_int32", in: 2147483647, want: 0}, test_int32{fn: div_int32_1, fnname: "div_int32_1", in: 2147483647, want: 2147483647}, test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: -2147483648, want: 0}, test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: -2147483648, want: -1}, test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: -2147483647, want: -1}, test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: -2147483647, want: -1}, test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: -1, want: -2147483647}, test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: -1, want: 0}, test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: 0, want: 0}, test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: 1, want: 2147483647}, test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: 1, want: 0}, test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: 2147483647, want: 1}, test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: 2147483647, want: 1}, test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: -2147483648, want: 0}, test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: -2147483648, want: 0}, test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: -2147483647, want: -2147483648}, test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: -2147483647, want: -2147483648}, test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: -1, want: -2147483648}, test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: -1, want: -2147483648}, test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: 0, want: 0}, test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: 0, want: 0}, test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: 1, want: -2147483648}, test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: 1, want: -2147483648}, test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: 2147483647, want: -2147483648}, test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: 2147483647, want: -2147483648}, test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: -2147483648, want: -2147483648}, test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: -2147483648, want: -2147483648}, test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: -2147483647, want: 1}, test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: -2147483647, want: 1}, test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: -1, want: 2147483647}, test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: -1, want: 2147483647}, test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: 0, want: 0}, test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: 0, want: 0}, test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: 1, want: -2147483647}, test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: 1, want: -2147483647}, test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: 2147483647, want: -1}, test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: 2147483647, want: -1}, test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: -2147483648, want: -2147483648}, test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: -2147483648, want: -2147483648}, test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: -2147483647, want: 2147483647}, test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: -2147483647, want: 2147483647}, test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: -1, want: 1}, test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: -1, want: 1}, test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: 0, want: 0}, test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: 0, want: 0}, test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: 1, want: -1}, test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: 1, want: -1}, test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: 2147483647, want: -2147483647}, test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: 2147483647, want: -2147483647}, test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: -2147483648, want: 0}, test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: -2147483648, want: 0}, test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: -2147483647, want: 0}, test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: -2147483647, want: 0}, test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: -1, want: 0}, test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: -1, want: 0}, test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: 0, want: 0}, test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: 0, want: 0}, test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: 1, want: 0}, test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: 1, want: 0}, test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: 2147483647, want: 0}, test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: 2147483647, want: 0}, test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: -2147483648, want: -2147483648}, test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: -2147483648, want: -2147483648}, test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: -2147483647, want: -2147483647}, test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: -2147483647, want: -2147483647}, test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: -1, want: -1}, test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: -1, want: -1}, test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: 0, want: 0}, test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: 0, want: 0}, test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: 1, want: 1}, test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: 1, want: 1}, test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: 2147483647, want: 2147483647}, test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: 2147483647, want: 2147483647}, test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: -2147483648, want: -2147483648}, test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: -2147483648, want: -2147483648}, test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: -2147483647, want: -1}, test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: -2147483647, want: -1}, test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: -1, want: -2147483647}, test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: -1, want: -2147483647}, test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: 0, want: 0}, test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: 0, want: 0}, test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: 1, want: 2147483647}, test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: 1, want: 2147483647}, test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: 2147483647, want: 1}, test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: 2147483647, want: 1}, test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: -2147483648, want: 0}, test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: -2147483648, want: 0}, test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: -2147483647, want: -1}, test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: -2147483647, want: -2147483647}, test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: -1, want: 0}, test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: -1, want: -1}, test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: 0, want: 0}, test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: 1, want: 0}, test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: 1, want: 1}, test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: 2147483647, want: -1}, test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: 2147483647, want: 2147483647}, test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: -2147483648, want: -2147483647}, test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: -2147483648, want: -1}, test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: -2147483647, want: 0}, test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: -2147483647, want: 0}, test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: -1, want: 0}, test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: -1, want: -1}, test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: 0, want: 0}, test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: 1, want: 0}, test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: 1, want: 1}, test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: 2147483647, want: 0}, test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: 2147483647, want: 0}, test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: -2147483648, want: -1}, test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: -2147483648, want: 0}, test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: -2147483647, want: -1}, test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: -2147483647, want: 0}, test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: -1, want: 0}, test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: -1, want: 0}, test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: 0, want: 0}, test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: 1, want: 0}, test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: 1, want: 0}, test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: 2147483647, want: -1}, test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: 2147483647, want: 0}, test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: -2147483648, want: 0}, test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: -2147483647, want: 0}, test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: -1, want: 0}, test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: 1, want: 0}, test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: 2147483647, want: 0}, test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: -2147483648, want: 1}, test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: -2147483648, want: 0}, test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: -2147483647, want: 1}, test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: -2147483647, want: 0}, test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: -1, want: 0}, test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: -1, want: 0}, test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: 0, want: 0}, test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: 1, want: 0}, test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: 1, want: 0}, test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: 2147483647, want: 1}, test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: 2147483647, want: 0}, test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: -2147483648, want: 2147483647}, test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: -2147483648, want: -1}, test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: -2147483647, want: 0}, test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: -2147483647, want: 0}, test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: -1, want: 0}, test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: -1, want: -1}, test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: 0, want: 0}, test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: 1, want: 0}, test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: 1, want: 1}, test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: 2147483647, want: 0}, test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: 2147483647, want: 0}, test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: -2147483648, want: -2147483648}, test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: -2147483648, want: -2147483648}, test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: -2147483647, want: -2147483648}, test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: -2147483647, want: -2147483648}, test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: -1, want: -2147483648}, test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: -1, want: -2147483648}, test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: 0, want: 0}, test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: 0, want: 0}, test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: 1, want: 0}, test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: 1, want: 0}, test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: 2147483647, want: 0}, test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: 2147483647, want: 0}, test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: -2147483648, want: -2147483648}, test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: -2147483648, want: -2147483648}, test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: -2147483647, want: -2147483647}, test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: -2147483647, want: -2147483647}, test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: -1, want: -2147483647}, test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: -1, want: -2147483647}, test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: 0, want: 0}, test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: 0, want: 0}, test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: 1, want: 1}, test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: 1, want: 1}, test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: 2147483647, want: 1}, test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: 2147483647, want: 1}, test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: -2147483648, want: -2147483648}, test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: -2147483648, want: -2147483648}, test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: -2147483647, want: -2147483647}, test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: -2147483647, want: -2147483647}, test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: -1, want: -1}, test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: -1, want: -1}, test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: 0, want: 0}, test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: 0, want: 0}, test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: 1, want: 1}, test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: 1, want: 1}, test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: 2147483647, want: 2147483647}, test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: 2147483647, want: 2147483647}, test_int32{fn: and_0_int32, fnname: "and_0_int32", in: -2147483648, want: 0}, test_int32{fn: and_int32_0, fnname: "and_int32_0", in: -2147483648, want: 0}, test_int32{fn: and_0_int32, fnname: "and_0_int32", in: -2147483647, want: 0}, test_int32{fn: and_int32_0, fnname: "and_int32_0", in: -2147483647, want: 0}, test_int32{fn: and_0_int32, fnname: "and_0_int32", in: -1, want: 0}, test_int32{fn: and_int32_0, fnname: "and_int32_0", in: -1, want: 0}, test_int32{fn: and_0_int32, fnname: "and_0_int32", in: 0, want: 0}, test_int32{fn: and_int32_0, fnname: "and_int32_0", in: 0, want: 0}, test_int32{fn: and_0_int32, fnname: "and_0_int32", in: 1, want: 0}, test_int32{fn: and_int32_0, fnname: "and_int32_0", in: 1, want: 0}, test_int32{fn: and_0_int32, fnname: "and_0_int32", in: 2147483647, want: 0}, test_int32{fn: and_int32_0, fnname: "and_int32_0", in: 2147483647, want: 0}, test_int32{fn: and_1_int32, fnname: "and_1_int32", in: -2147483648, want: 0}, test_int32{fn: and_int32_1, fnname: "and_int32_1", in: -2147483648, want: 0}, test_int32{fn: and_1_int32, fnname: "and_1_int32", in: -2147483647, want: 1}, test_int32{fn: and_int32_1, fnname: "and_int32_1", in: -2147483647, want: 1}, test_int32{fn: and_1_int32, fnname: "and_1_int32", in: -1, want: 1}, test_int32{fn: and_int32_1, fnname: "and_int32_1", in: -1, want: 1}, test_int32{fn: and_1_int32, fnname: "and_1_int32", in: 0, want: 0}, test_int32{fn: and_int32_1, fnname: "and_int32_1", in: 0, want: 0}, test_int32{fn: and_1_int32, fnname: "and_1_int32", in: 1, want: 1}, test_int32{fn: and_int32_1, fnname: "and_int32_1", in: 1, want: 1}, test_int32{fn: and_1_int32, fnname: "and_1_int32", in: 2147483647, want: 1}, test_int32{fn: and_int32_1, fnname: "and_int32_1", in: 2147483647, want: 1}, test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: -2147483648, want: 0}, test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: -2147483648, want: 0}, test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: -2147483647, want: 1}, test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: -2147483647, want: 1}, test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: -1, want: 2147483647}, test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: -1, want: 2147483647}, test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: 0, want: 0}, test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: 0, want: 0}, test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: 1, want: 1}, test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: 1, want: 1}, test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: 2147483647, want: 2147483647}, test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: 2147483647, want: 2147483647}, test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: -2147483648, want: -2147483648}, test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: -2147483648, want: -2147483648}, test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: -2147483647, want: -2147483647}, test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: -2147483647, want: -2147483647}, test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: -1, want: -1}, test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: -1, want: -1}, test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: 0, want: -2147483648}, test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: 0, want: -2147483648}, test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: 1, want: -2147483647}, test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: 1, want: -2147483647}, test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: 2147483647, want: -1}, test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: 2147483647, want: -1}, test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: -2147483648, want: -2147483647}, test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: -2147483648, want: -2147483647}, test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: -2147483647, want: -2147483647}, test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: -2147483647, want: -2147483647}, test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: -1, want: -1}, test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: -1, want: -1}, test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: 0, want: -2147483647}, test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: 0, want: -2147483647}, test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: 1, want: -2147483647}, test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: 1, want: -2147483647}, test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: 2147483647, want: -1}, test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: 2147483647, want: -1}, test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: -2147483648, want: -1}, test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: -2147483648, want: -1}, test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: -2147483647, want: -1}, test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: -2147483647, want: -1}, test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: -1, want: -1}, test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: -1, want: -1}, test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: 0, want: -1}, test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: 0, want: -1}, test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: 1, want: -1}, test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: 1, want: -1}, test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: 2147483647, want: -1}, test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: 2147483647, want: -1}, test_int32{fn: or_0_int32, fnname: "or_0_int32", in: -2147483648, want: -2147483648}, test_int32{fn: or_int32_0, fnname: "or_int32_0", in: -2147483648, want: -2147483648}, test_int32{fn: or_0_int32, fnname: "or_0_int32", in: -2147483647, want: -2147483647}, test_int32{fn: or_int32_0, fnname: "or_int32_0", in: -2147483647, want: -2147483647}, test_int32{fn: or_0_int32, fnname: "or_0_int32", in: -1, want: -1}, test_int32{fn: or_int32_0, fnname: "or_int32_0", in: -1, want: -1}, test_int32{fn: or_0_int32, fnname: "or_0_int32", in: 0, want: 0}, test_int32{fn: or_int32_0, fnname: "or_int32_0", in: 0, want: 0}, test_int32{fn: or_0_int32, fnname: "or_0_int32", in: 1, want: 1}, test_int32{fn: or_int32_0, fnname: "or_int32_0", in: 1, want: 1}, test_int32{fn: or_0_int32, fnname: "or_0_int32", in: 2147483647, want: 2147483647}, test_int32{fn: or_int32_0, fnname: "or_int32_0", in: 2147483647, want: 2147483647}, test_int32{fn: or_1_int32, fnname: "or_1_int32", in: -2147483648, want: -2147483647}, test_int32{fn: or_int32_1, fnname: "or_int32_1", in: -2147483648, want: -2147483647}, test_int32{fn: or_1_int32, fnname: "or_1_int32", in: -2147483647, want: -2147483647}, test_int32{fn: or_int32_1, fnname: "or_int32_1", in: -2147483647, want: -2147483647}, test_int32{fn: or_1_int32, fnname: "or_1_int32", in: -1, want: -1}, test_int32{fn: or_int32_1, fnname: "or_int32_1", in: -1, want: -1}, test_int32{fn: or_1_int32, fnname: "or_1_int32", in: 0, want: 1}, test_int32{fn: or_int32_1, fnname: "or_int32_1", in: 0, want: 1}, test_int32{fn: or_1_int32, fnname: "or_1_int32", in: 1, want: 1}, test_int32{fn: or_int32_1, fnname: "or_int32_1", in: 1, want: 1}, test_int32{fn: or_1_int32, fnname: "or_1_int32", in: 2147483647, want: 2147483647}, test_int32{fn: or_int32_1, fnname: "or_int32_1", in: 2147483647, want: 2147483647}, test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: -2147483648, want: -1}, test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: -2147483648, want: -1}, test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: -2147483647, want: -1}, test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: -2147483647, want: -1}, test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: -1, want: -1}, test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: -1, want: -1}, test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: 0, want: 2147483647}, test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: 0, want: 2147483647}, test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: 1, want: 2147483647}, test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: 1, want: 2147483647}, test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: 2147483647, want: 2147483647}, test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: 2147483647, want: 2147483647}, test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: -2147483648, want: 0}, test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: -2147483648, want: 0}, test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: -2147483647, want: 1}, test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: -2147483647, want: 1}, test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: -1, want: 2147483647}, test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: -1, want: 2147483647}, test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: 0, want: -2147483648}, test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: 0, want: -2147483648}, test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: 1, want: -2147483647}, test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: 1, want: -2147483647}, test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: 2147483647, want: -1}, test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: 2147483647, want: -1}, test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: -2147483648, want: 1}, test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: -2147483648, want: 1}, test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: -2147483647, want: 0}, test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: -2147483647, want: 0}, test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: -1, want: 2147483646}, test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: -1, want: 2147483646}, test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: 0, want: -2147483647}, test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: 0, want: -2147483647}, test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: 1, want: -2147483648}, test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: 1, want: -2147483648}, test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: 2147483647, want: -2}, test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: 2147483647, want: -2}, test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: -2147483648, want: 2147483647}, test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: -2147483648, want: 2147483647}, test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: -2147483647, want: 2147483646}, test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: -2147483647, want: 2147483646}, test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: -1, want: 0}, test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: -1, want: 0}, test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: 0, want: -1}, test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: 0, want: -1}, test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: 1, want: -2}, test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: 1, want: -2}, test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: 2147483647, want: -2147483648}, test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: 2147483647, want: -2147483648}, test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: -2147483648, want: -2147483648}, test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: -2147483648, want: -2147483648}, test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: -2147483647, want: -2147483647}, test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: -2147483647, want: -2147483647}, test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: -1, want: -1}, test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: -1, want: -1}, test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: 0, want: 0}, test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: 0, want: 0}, test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: 1, want: 1}, test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: 1, want: 1}, test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: 2147483647, want: 2147483647}, test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: 2147483647, want: 2147483647}, test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: -2147483648, want: -2147483647}, test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: -2147483648, want: -2147483647}, test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: -2147483647, want: -2147483648}, test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: -2147483647, want: -2147483648}, test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: -1, want: -2}, test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: -1, want: -2}, test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: 0, want: 1}, test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: 0, want: 1}, test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: 1, want: 0}, test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: 1, want: 0}, test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: 2147483647, want: 2147483646}, test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: 2147483647, want: 2147483646}, test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: -2147483648, want: -1}, test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: -2147483648, want: -1}, test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: -2147483647, want: -2}, test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: -2147483647, want: -2}, test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: -1, want: -2147483648}, test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: -1, want: -2147483648}, test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: 0, want: 2147483647}, test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: 0, want: 2147483647}, test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: 1, want: 2147483646}, test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: 1, want: 2147483646}, test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: 2147483647, want: 0}, test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: 2147483647, want: 0}} type test_uint16 struct { fn func(uint16) uint16 fnname string in uint16 want uint16 } var tests_uint16 = []test_uint16{ test_uint16{fn: add_0_uint16, fnname: "add_0_uint16", in: 0, want: 0}, test_uint16{fn: add_uint16_0, fnname: "add_uint16_0", in: 0, want: 0}, test_uint16{fn: add_0_uint16, fnname: "add_0_uint16", in: 1, want: 1}, test_uint16{fn: add_uint16_0, fnname: "add_uint16_0", in: 1, want: 1}, test_uint16{fn: add_0_uint16, fnname: "add_0_uint16", in: 65535, want: 65535}, test_uint16{fn: add_uint16_0, fnname: "add_uint16_0", in: 65535, want: 65535}, test_uint16{fn: add_1_uint16, fnname: "add_1_uint16", in: 0, want: 1}, test_uint16{fn: add_uint16_1, fnname: "add_uint16_1", in: 0, want: 1}, test_uint16{fn: add_1_uint16, fnname: "add_1_uint16", in: 1, want: 2}, test_uint16{fn: add_uint16_1, fnname: "add_uint16_1", in: 1, want: 2}, test_uint16{fn: add_1_uint16, fnname: "add_1_uint16", in: 65535, want: 0}, test_uint16{fn: add_uint16_1, fnname: "add_uint16_1", in: 65535, want: 0}, test_uint16{fn: add_65535_uint16, fnname: "add_65535_uint16", in: 0, want: 65535}, test_uint16{fn: add_uint16_65535, fnname: "add_uint16_65535", in: 0, want: 65535}, test_uint16{fn: add_65535_uint16, fnname: "add_65535_uint16", in: 1, want: 0}, test_uint16{fn: add_uint16_65535, fnname: "add_uint16_65535", in: 1, want: 0}, test_uint16{fn: add_65535_uint16, fnname: "add_65535_uint16", in: 65535, want: 65534}, test_uint16{fn: add_uint16_65535, fnname: "add_uint16_65535", in: 65535, want: 65534}, test_uint16{fn: sub_0_uint16, fnname: "sub_0_uint16", in: 0, want: 0}, test_uint16{fn: sub_uint16_0, fnname: "sub_uint16_0", in: 0, want: 0}, test_uint16{fn: sub_0_uint16, fnname: "sub_0_uint16", in: 1, want: 65535}, test_uint16{fn: sub_uint16_0, fnname: "sub_uint16_0", in: 1, want: 1}, test_uint16{fn: sub_0_uint16, fnname: "sub_0_uint16", in: 65535, want: 1}, test_uint16{fn: sub_uint16_0, fnname: "sub_uint16_0", in: 65535, want: 65535}, test_uint16{fn: sub_1_uint16, fnname: "sub_1_uint16", in: 0, want: 1}, test_uint16{fn: sub_uint16_1, fnname: "sub_uint16_1", in: 0, want: 65535}, test_uint16{fn: sub_1_uint16, fnname: "sub_1_uint16", in: 1, want: 0}, test_uint16{fn: sub_uint16_1, fnname: "sub_uint16_1", in: 1, want: 0}, test_uint16{fn: sub_1_uint16, fnname: "sub_1_uint16", in: 65535, want: 2}, test_uint16{fn: sub_uint16_1, fnname: "sub_uint16_1", in: 65535, want: 65534}, test_uint16{fn: sub_65535_uint16, fnname: "sub_65535_uint16", in: 0, want: 65535}, test_uint16{fn: sub_uint16_65535, fnname: "sub_uint16_65535", in: 0, want: 1}, test_uint16{fn: sub_65535_uint16, fnname: "sub_65535_uint16", in: 1, want: 65534}, test_uint16{fn: sub_uint16_65535, fnname: "sub_uint16_65535", in: 1, want: 2}, test_uint16{fn: sub_65535_uint16, fnname: "sub_65535_uint16", in: 65535, want: 0}, test_uint16{fn: sub_uint16_65535, fnname: "sub_uint16_65535", in: 65535, want: 0}, test_uint16{fn: div_0_uint16, fnname: "div_0_uint16", in: 1, want: 0}, test_uint16{fn: div_0_uint16, fnname: "div_0_uint16", in: 65535, want: 0}, test_uint16{fn: div_uint16_1, fnname: "div_uint16_1", in: 0, want: 0}, test_uint16{fn: div_1_uint16, fnname: "div_1_uint16", in: 1, want: 1}, test_uint16{fn: div_uint16_1, fnname: "div_uint16_1", in: 1, want: 1}, test_uint16{fn: div_1_uint16, fnname: "div_1_uint16", in: 65535, want: 0}, test_uint16{fn: div_uint16_1, fnname: "div_uint16_1", in: 65535, want: 65535}, test_uint16{fn: div_uint16_65535, fnname: "div_uint16_65535", in: 0, want: 0}, test_uint16{fn: div_65535_uint16, fnname: "div_65535_uint16", in: 1, want: 65535}, test_uint16{fn: div_uint16_65535, fnname: "div_uint16_65535", in: 1, want: 0}, test_uint16{fn: div_65535_uint16, fnname: "div_65535_uint16", in: 65535, want: 1}, test_uint16{fn: div_uint16_65535, fnname: "div_uint16_65535", in: 65535, want: 1}, test_uint16{fn: mul_0_uint16, fnname: "mul_0_uint16", in: 0, want: 0}, test_uint16{fn: mul_uint16_0, fnname: "mul_uint16_0", in: 0, want: 0}, test_uint16{fn: mul_0_uint16, fnname: "mul_0_uint16", in: 1, want: 0}, test_uint16{fn: mul_uint16_0, fnname: "mul_uint16_0", in: 1, want: 0}, test_uint16{fn: mul_0_uint16, fnname: "mul_0_uint16", in: 65535, want: 0}, test_uint16{fn: mul_uint16_0, fnname: "mul_uint16_0", in: 65535, want: 0}, test_uint16{fn: mul_1_uint16, fnname: "mul_1_uint16", in: 0, want: 0}, test_uint16{fn: mul_uint16_1, fnname: "mul_uint16_1", in: 0, want: 0}, test_uint16{fn: mul_1_uint16, fnname: "mul_1_uint16", in: 1, want: 1}, test_uint16{fn: mul_uint16_1, fnname: "mul_uint16_1", in: 1, want: 1}, test_uint16{fn: mul_1_uint16, fnname: "mul_1_uint16", in: 65535, want: 65535}, test_uint16{fn: mul_uint16_1, fnname: "mul_uint16_1", in: 65535, want: 65535}, test_uint16{fn: mul_65535_uint16, fnname: "mul_65535_uint16", in: 0, want: 0}, test_uint16{fn: mul_uint16_65535, fnname: "mul_uint16_65535", in: 0, want: 0}, test_uint16{fn: mul_65535_uint16, fnname: "mul_65535_uint16", in: 1, want: 65535}, test_uint16{fn: mul_uint16_65535, fnname: "mul_uint16_65535", in: 1, want: 65535}, test_uint16{fn: mul_65535_uint16, fnname: "mul_65535_uint16", in: 65535, want: 1}, test_uint16{fn: mul_uint16_65535, fnname: "mul_uint16_65535", in: 65535, want: 1}, test_uint16{fn: lsh_0_uint16, fnname: "lsh_0_uint16", in: 0, want: 0}, test_uint16{fn: lsh_uint16_0, fnname: "lsh_uint16_0", in: 0, want: 0}, test_uint16{fn: lsh_0_uint16, fnname: "lsh_0_uint16", in: 1, want: 0}, test_uint16{fn: lsh_uint16_0, fnname: "lsh_uint16_0", in: 1, want: 1}, test_uint16{fn: lsh_0_uint16, fnname: "lsh_0_uint16", in: 65535, want: 0}, test_uint16{fn: lsh_uint16_0, fnname: "lsh_uint16_0", in: 65535, want: 65535}, test_uint16{fn: lsh_1_uint16, fnname: "lsh_1_uint16", in: 0, want: 1}, test_uint16{fn: lsh_uint16_1, fnname: "lsh_uint16_1", in: 0, want: 0}, test_uint16{fn: lsh_1_uint16, fnname: "lsh_1_uint16", in: 1, want: 2}, test_uint16{fn: lsh_uint16_1, fnname: "lsh_uint16_1", in: 1, want: 2}, test_uint16{fn: lsh_1_uint16, fnname: "lsh_1_uint16", in: 65535, want: 0}, test_uint16{fn: lsh_uint16_1, fnname: "lsh_uint16_1", in: 65535, want: 65534}, test_uint16{fn: lsh_65535_uint16, fnname: "lsh_65535_uint16", in: 0, want: 65535}, test_uint16{fn: lsh_uint16_65535, fnname: "lsh_uint16_65535", in: 0, want: 0}, test_uint16{fn: lsh_65535_uint16, fnname: "lsh_65535_uint16", in: 1, want: 65534}, test_uint16{fn: lsh_uint16_65535, fnname: "lsh_uint16_65535", in: 1, want: 0}, test_uint16{fn: lsh_65535_uint16, fnname: "lsh_65535_uint16", in: 65535, want: 0}, test_uint16{fn: lsh_uint16_65535, fnname: "lsh_uint16_65535", in: 65535, want: 0}, test_uint16{fn: rsh_0_uint16, fnname: "rsh_0_uint16", in: 0, want: 0}, test_uint16{fn: rsh_uint16_0, fnname: "rsh_uint16_0", in: 0, want: 0}, test_uint16{fn: rsh_0_uint16, fnname: "rsh_0_uint16", in: 1, want: 0}, test_uint16{fn: rsh_uint16_0, fnname: "rsh_uint16_0", in: 1, want: 1}, test_uint16{fn: rsh_0_uint16, fnname: "rsh_0_uint16", in: 65535, want: 0}, test_uint16{fn: rsh_uint16_0, fnname: "rsh_uint16_0", in: 65535, want: 65535}, test_uint16{fn: rsh_1_uint16, fnname: "rsh_1_uint16", in: 0, want: 1}, test_uint16{fn: rsh_uint16_1, fnname: "rsh_uint16_1", in: 0, want: 0}, test_uint16{fn: rsh_1_uint16, fnname: "rsh_1_uint16", in: 1, want: 0}, test_uint16{fn: rsh_uint16_1, fnname: "rsh_uint16_1", in: 1, want: 0}, test_uint16{fn: rsh_1_uint16, fnname: "rsh_1_uint16", in: 65535, want: 0}, test_uint16{fn: rsh_uint16_1, fnname: "rsh_uint16_1", in: 65535, want: 32767}, test_uint16{fn: rsh_65535_uint16, fnname: "rsh_65535_uint16", in: 0, want: 65535}, test_uint16{fn: rsh_uint16_65535, fnname: "rsh_uint16_65535", in: 0, want: 0}, test_uint16{fn: rsh_65535_uint16, fnname: "rsh_65535_uint16", in: 1, want: 32767}, test_uint16{fn: rsh_uint16_65535, fnname: "rsh_uint16_65535", in: 1, want: 0}, test_uint16{fn: rsh_65535_uint16, fnname: "rsh_65535_uint16", in: 65535, want: 0}, test_uint16{fn: rsh_uint16_65535, fnname: "rsh_uint16_65535", in: 65535, want: 0}, test_uint16{fn: mod_0_uint16, fnname: "mod_0_uint16", in: 1, want: 0}, test_uint16{fn: mod_0_uint16, fnname: "mod_0_uint16", in: 65535, want: 0}, test_uint16{fn: mod_uint16_1, fnname: "mod_uint16_1", in: 0, want: 0}, test_uint16{fn: mod_1_uint16, fnname: "mod_1_uint16", in: 1, want: 0}, test_uint16{fn: mod_uint16_1, fnname: "mod_uint16_1", in: 1, want: 0}, test_uint16{fn: mod_1_uint16, fnname: "mod_1_uint16", in: 65535, want: 1}, test_uint16{fn: mod_uint16_1, fnname: "mod_uint16_1", in: 65535, want: 0}, test_uint16{fn: mod_uint16_65535, fnname: "mod_uint16_65535", in: 0, want: 0}, test_uint16{fn: mod_65535_uint16, fnname: "mod_65535_uint16", in: 1, want: 0}, test_uint16{fn: mod_uint16_65535, fnname: "mod_uint16_65535", in: 1, want: 1}, test_uint16{fn: mod_65535_uint16, fnname: "mod_65535_uint16", in: 65535, want: 0}, test_uint16{fn: mod_uint16_65535, fnname: "mod_uint16_65535", in: 65535, want: 0}, test_uint16{fn: and_0_uint16, fnname: "and_0_uint16", in: 0, want: 0}, test_uint16{fn: and_uint16_0, fnname: "and_uint16_0", in: 0, want: 0}, test_uint16{fn: and_0_uint16, fnname: "and_0_uint16", in: 1, want: 0}, test_uint16{fn: and_uint16_0, fnname: "and_uint16_0", in: 1, want: 0}, test_uint16{fn: and_0_uint16, fnname: "and_0_uint16", in: 65535, want: 0}, test_uint16{fn: and_uint16_0, fnname: "and_uint16_0", in: 65535, want: 0}, test_uint16{fn: and_1_uint16, fnname: "and_1_uint16", in: 0, want: 0}, test_uint16{fn: and_uint16_1, fnname: "and_uint16_1", in: 0, want: 0}, test_uint16{fn: and_1_uint16, fnname: "and_1_uint16", in: 1, want: 1}, test_uint16{fn: and_uint16_1, fnname: "and_uint16_1", in: 1, want: 1}, test_uint16{fn: and_1_uint16, fnname: "and_1_uint16", in: 65535, want: 1}, test_uint16{fn: and_uint16_1, fnname: "and_uint16_1", in: 65535, want: 1}, test_uint16{fn: and_65535_uint16, fnname: "and_65535_uint16", in: 0, want: 0}, test_uint16{fn: and_uint16_65535, fnname: "and_uint16_65535", in: 0, want: 0}, test_uint16{fn: and_65535_uint16, fnname: "and_65535_uint16", in: 1, want: 1}, test_uint16{fn: and_uint16_65535, fnname: "and_uint16_65535", in: 1, want: 1}, test_uint16{fn: and_65535_uint16, fnname: "and_65535_uint16", in: 65535, want: 65535}, test_uint16{fn: and_uint16_65535, fnname: "and_uint16_65535", in: 65535, want: 65535}, test_uint16{fn: or_0_uint16, fnname: "or_0_uint16", in: 0, want: 0}, test_uint16{fn: or_uint16_0, fnname: "or_uint16_0", in: 0, want: 0}, test_uint16{fn: or_0_uint16, fnname: "or_0_uint16", in: 1, want: 1}, test_uint16{fn: or_uint16_0, fnname: "or_uint16_0", in: 1, want: 1}, test_uint16{fn: or_0_uint16, fnname: "or_0_uint16", in: 65535, want: 65535}, test_uint16{fn: or_uint16_0, fnname: "or_uint16_0", in: 65535, want: 65535}, test_uint16{fn: or_1_uint16, fnname: "or_1_uint16", in: 0, want: 1}, test_uint16{fn: or_uint16_1, fnname: "or_uint16_1", in: 0, want: 1}, test_uint16{fn: or_1_uint16, fnname: "or_1_uint16", in: 1, want: 1}, test_uint16{fn: or_uint16_1, fnname: "or_uint16_1", in: 1, want: 1}, test_uint16{fn: or_1_uint16, fnname: "or_1_uint16", in: 65535, want: 65535}, test_uint16{fn: or_uint16_1, fnname: "or_uint16_1", in: 65535, want: 65535}, test_uint16{fn: or_65535_uint16, fnname: "or_65535_uint16", in: 0, want: 65535}, test_uint16{fn: or_uint16_65535, fnname: "or_uint16_65535", in: 0, want: 65535}, test_uint16{fn: or_65535_uint16, fnname: "or_65535_uint16", in: 1, want: 65535}, test_uint16{fn: or_uint16_65535, fnname: "or_uint16_65535", in: 1, want: 65535}, test_uint16{fn: or_65535_uint16, fnname: "or_65535_uint16", in: 65535, want: 65535}, test_uint16{fn: or_uint16_65535, fnname: "or_uint16_65535", in: 65535, want: 65535}, test_uint16{fn: xor_0_uint16, fnname: "xor_0_uint16", in: 0, want: 0}, test_uint16{fn: xor_uint16_0, fnname: "xor_uint16_0", in: 0, want: 0}, test_uint16{fn: xor_0_uint16, fnname: "xor_0_uint16", in: 1, want: 1}, test_uint16{fn: xor_uint16_0, fnname: "xor_uint16_0", in: 1, want: 1}, test_uint16{fn: xor_0_uint16, fnname: "xor_0_uint16", in: 65535, want: 65535}, test_uint16{fn: xor_uint16_0, fnname: "xor_uint16_0", in: 65535, want: 65535}, test_uint16{fn: xor_1_uint16, fnname: "xor_1_uint16", in: 0, want: 1}, test_uint16{fn: xor_uint16_1, fnname: "xor_uint16_1", in: 0, want: 1}, test_uint16{fn: xor_1_uint16, fnname: "xor_1_uint16", in: 1, want: 0}, test_uint16{fn: xor_uint16_1, fnname: "xor_uint16_1", in: 1, want: 0}, test_uint16{fn: xor_1_uint16, fnname: "xor_1_uint16", in: 65535, want: 65534}, test_uint16{fn: xor_uint16_1, fnname: "xor_uint16_1", in: 65535, want: 65534}, test_uint16{fn: xor_65535_uint16, fnname: "xor_65535_uint16", in: 0, want: 65535}, test_uint16{fn: xor_uint16_65535, fnname: "xor_uint16_65535", in: 0, want: 65535}, test_uint16{fn: xor_65535_uint16, fnname: "xor_65535_uint16", in: 1, want: 65534}, test_uint16{fn: xor_uint16_65535, fnname: "xor_uint16_65535", in: 1, want: 65534}, test_uint16{fn: xor_65535_uint16, fnname: "xor_65535_uint16", in: 65535, want: 0}, test_uint16{fn: xor_uint16_65535, fnname: "xor_uint16_65535", in: 65535, want: 0}} type test_int16 struct { fn func(int16) int16 fnname string in int16 want int16 } var tests_int16 = []test_int16{ test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: -32768, want: 0}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: -32768, want: 0}, test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: -32767, want: 1}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: -32767, want: 1}, test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: -1, want: 32767}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: -1, want: 32767}, test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: 0, want: -32768}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: 0, want: -32768}, test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: 1, want: -32767}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: 1, want: -32767}, test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: 32766, want: -2}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: 32766, want: -2}, test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: 32767, want: -1}, test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: 32767, want: -1}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: -32768, want: 1}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: -32768, want: 1}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: -32767, want: 2}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: -32767, want: 2}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: -1, want: -32768}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: -1, want: -32768}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: 0, want: -32767}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: 0, want: -32767}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: 1, want: -32766}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: 1, want: -32766}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: 32766, want: -1}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: 32766, want: -1}, test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: 32767, want: 0}, test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: 32767, want: 0}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: -32768, want: 32767}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: -32768, want: 32767}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: -32767, want: -32768}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: -32767, want: -32768}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: -1, want: -2}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: -1, want: -2}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: 0, want: -1}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: 0, want: -1}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: 1, want: 0}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: 1, want: 0}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: 32766, want: 32765}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: 32766, want: 32765}, test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: 32767, want: 32766}, test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: 32767, want: 32766}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: -32768, want: -32768}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: -32768, want: -32768}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: -32767, want: -32767}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: -32767, want: -32767}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: -1, want: -1}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: -1, want: -1}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: 0, want: 0}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: 0, want: 0}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: 1, want: 1}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: 1, want: 1}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: 32766, want: 32766}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: 32766, want: 32766}, test_int16{fn: add_0_int16, fnname: "add_0_int16", in: 32767, want: 32767}, test_int16{fn: add_int16_0, fnname: "add_int16_0", in: 32767, want: 32767}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: -32768, want: -32767}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: -32768, want: -32767}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: -32767, want: -32766}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: -32767, want: -32766}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: -1, want: 0}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: -1, want: 0}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: 0, want: 1}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: 0, want: 1}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: 1, want: 2}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: 1, want: 2}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: 32766, want: 32767}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: 32766, want: 32767}, test_int16{fn: add_1_int16, fnname: "add_1_int16", in: 32767, want: -32768}, test_int16{fn: add_int16_1, fnname: "add_int16_1", in: 32767, want: -32768}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: -32768, want: -2}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: -32768, want: -2}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: -32767, want: -1}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: -32767, want: -1}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: -1, want: 32765}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: -1, want: 32765}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: 0, want: 32766}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: 0, want: 32766}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: 1, want: 32767}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: 1, want: 32767}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: 32766, want: -4}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: 32766, want: -4}, test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: 32767, want: -3}, test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: 32767, want: -3}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: -32768, want: -1}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: -32768, want: -1}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: -32767, want: 0}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: -32767, want: 0}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: -1, want: 32766}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: -1, want: 32766}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: 0, want: 32767}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: 0, want: 32767}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: 1, want: -32768}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: 1, want: -32768}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: 32766, want: -3}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: 32766, want: -3}, test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: 32767, want: -2}, test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: 32767, want: -2}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: -32768, want: 0}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: -32768, want: 0}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: -32767, want: -1}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: -32767, want: 1}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: -1, want: -32767}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: -1, want: 32767}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: 0, want: -32768}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: 0, want: -32768}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: 1, want: 32767}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: 1, want: -32767}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: 32766, want: 2}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: 32766, want: -2}, test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: 32767, want: 1}, test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: 32767, want: -1}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: -32768, want: 1}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: -32768, want: -1}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: -32767, want: 0}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: -32767, want: 0}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: -1, want: -32766}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: -1, want: 32766}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: 0, want: -32767}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: 0, want: 32767}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: 1, want: -32768}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: 1, want: -32768}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: 32766, want: 3}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: 32766, want: -3}, test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: 32767, want: 2}, test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: 32767, want: -2}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: -32768, want: 32767}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: -32768, want: -32767}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: -32767, want: 32766}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: -32767, want: -32766}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: -1, want: 0}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: -1, want: 0}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: 0, want: -1}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: 0, want: 1}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: 1, want: -2}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: 1, want: 2}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: 32766, want: -32767}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: 32766, want: 32767}, test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: 32767, want: -32768}, test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: 32767, want: -32768}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: -32768, want: -32768}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: -32768, want: -32768}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: -32767, want: 32767}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: -32767, want: -32767}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: -1, want: 1}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: -1, want: -1}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: 0, want: 0}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: 0, want: 0}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: 1, want: -1}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: 1, want: 1}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: 32766, want: -32766}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: 32766, want: 32766}, test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: 32767, want: -32767}, test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: 32767, want: 32767}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: -32768, want: -32767}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: -32768, want: 32767}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: -32767, want: -32768}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: -32767, want: -32768}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: -1, want: 2}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: -1, want: -2}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: 0, want: 1}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: 0, want: -1}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: 1, want: 0}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: 1, want: 0}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: 32766, want: -32765}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: 32766, want: 32765}, test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: 32767, want: -32766}, test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: 32767, want: 32766}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: -32768, want: -2}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: -32768, want: 2}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: -32767, want: -3}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: -32767, want: 3}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: -1, want: 32767}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: -1, want: -32767}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: 0, want: 32766}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: 0, want: -32766}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: 1, want: 32765}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: 1, want: -32765}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: 32766, want: 0}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: 32766, want: 0}, test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: 32767, want: -1}, test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: 32767, want: 1}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: -32768, want: -1}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: -32768, want: 1}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: -32767, want: -2}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: -32767, want: 2}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: -1, want: -32768}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: -1, want: -32768}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: 0, want: 32767}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: 0, want: -32767}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: 1, want: 32766}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: 1, want: -32766}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: 32766, want: 1}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: 32766, want: -1}, test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: 32767, want: 0}, test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: 32767, want: 0}, test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: -32768, want: 1}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: -32768, want: 1}, test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: -32767, want: 1}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: -32767, want: 0}, test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: -1, want: -32768}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: -1, want: 0}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: 0, want: 0}, test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: 1, want: -32768}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: 1, want: 0}, test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: 32766, want: -1}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: 32766, want: 0}, test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: 32767, want: -1}, test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: 32767, want: 0}, test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: -32768, want: 0}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: -32768, want: 1}, test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: -32767, want: 1}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: -32767, want: 1}, test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: -1, want: 32767}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: -1, want: 0}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: 0, want: 0}, test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: 1, want: -32767}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: 1, want: 0}, test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: 32766, want: -1}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: 32766, want: 0}, test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: 32767, want: -1}, test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: 32767, want: -1}, test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: -32768, want: 0}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: -32768, want: -32768}, test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: -32767, want: 0}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: -32767, want: 32767}, test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: -1, want: 1}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: -1, want: 1}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: 0, want: 0}, test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: 1, want: -1}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: 1, want: -1}, test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: 32766, want: 0}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: 32766, want: -32766}, test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: 32767, want: 0}, test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: 32767, want: -32767}, test_int16{fn: div_0_int16, fnname: "div_0_int16", in: -32768, want: 0}, test_int16{fn: div_0_int16, fnname: "div_0_int16", in: -32767, want: 0}, test_int16{fn: div_0_int16, fnname: "div_0_int16", in: -1, want: 0}, test_int16{fn: div_0_int16, fnname: "div_0_int16", in: 1, want: 0}, test_int16{fn: div_0_int16, fnname: "div_0_int16", in: 32766, want: 0}, test_int16{fn: div_0_int16, fnname: "div_0_int16", in: 32767, want: 0}, test_int16{fn: div_1_int16, fnname: "div_1_int16", in: -32768, want: 0}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: -32768, want: -32768}, test_int16{fn: div_1_int16, fnname: "div_1_int16", in: -32767, want: 0}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: -32767, want: -32767}, test_int16{fn: div_1_int16, fnname: "div_1_int16", in: -1, want: -1}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: -1, want: -1}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: 0, want: 0}, test_int16{fn: div_1_int16, fnname: "div_1_int16", in: 1, want: 1}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: 1, want: 1}, test_int16{fn: div_1_int16, fnname: "div_1_int16", in: 32766, want: 0}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: 32766, want: 32766}, test_int16{fn: div_1_int16, fnname: "div_1_int16", in: 32767, want: 0}, test_int16{fn: div_int16_1, fnname: "div_int16_1", in: 32767, want: 32767}, test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: -32768, want: 0}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: -32768, want: -1}, test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: -32767, want: 0}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: -32767, want: -1}, test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: -1, want: -32766}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: -1, want: 0}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: 0, want: 0}, test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: 1, want: 32766}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: 1, want: 0}, test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: 32766, want: 1}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: 32766, want: 1}, test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: 32767, want: 0}, test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: 32767, want: 1}, test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: -32768, want: 0}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: -32768, want: -1}, test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: -32767, want: -1}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: -32767, want: -1}, test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: -1, want: -32767}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: -1, want: 0}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: 0, want: 0}, test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: 1, want: 32767}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: 1, want: 0}, test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: 32766, want: 1}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: 32766, want: 0}, test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: 32767, want: 1}, test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: 32767, want: 1}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: -32768, want: 0}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: -32768, want: 0}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: -32767, want: -32768}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: -32767, want: -32768}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: -1, want: -32768}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: -1, want: -32768}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: 0, want: 0}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: 0, want: 0}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: 1, want: -32768}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: 1, want: -32768}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: 32766, want: 0}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: 32766, want: 0}, test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: 32767, want: -32768}, test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: 32767, want: -32768}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: -32768, want: -32768}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: -32768, want: -32768}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: -32767, want: 1}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: -32767, want: 1}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: -1, want: 32767}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: -1, want: 32767}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: 0, want: 0}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: 0, want: 0}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: 1, want: -32767}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: 1, want: -32767}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: 32766, want: 32766}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: 32766, want: 32766}, test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: 32767, want: -1}, test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: 32767, want: -1}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: -32768, want: -32768}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: -32768, want: -32768}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: -32767, want: 32767}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: -32767, want: 32767}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: -1, want: 1}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: -1, want: 1}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: 0, want: 0}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: 0, want: 0}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: 1, want: -1}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: 1, want: -1}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: 32766, want: -32766}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: 32766, want: -32766}, test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: 32767, want: -32767}, test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: 32767, want: -32767}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: -32768, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: -32768, want: 0}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: -32767, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: -32767, want: 0}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: -1, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: -1, want: 0}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: 0, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: 0, want: 0}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: 1, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: 1, want: 0}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: 32766, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: 32766, want: 0}, test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: 32767, want: 0}, test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: 32767, want: 0}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: -32768, want: -32768}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: -32768, want: -32768}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: -32767, want: -32767}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: -32767, want: -32767}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: -1, want: -1}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: -1, want: -1}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: 0, want: 0}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: 0, want: 0}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: 1, want: 1}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: 1, want: 1}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: 32766, want: 32766}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: 32766, want: 32766}, test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: 32767, want: 32767}, test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: 32767, want: 32767}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: -32768, want: 0}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: -32768, want: 0}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: -32767, want: 32766}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: -32767, want: 32766}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: -1, want: -32766}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: -1, want: -32766}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: 0, want: 0}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: 0, want: 0}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: 1, want: 32766}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: 1, want: 32766}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: 32766, want: 4}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: 32766, want: 4}, test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: 32767, want: -32766}, test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: 32767, want: -32766}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: -32768, want: -32768}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: -32768, want: -32768}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: -32767, want: -1}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: -32767, want: -1}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: -1, want: -32767}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: -1, want: -32767}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: 0, want: 0}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: 0, want: 0}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: 1, want: 32767}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: 1, want: 32767}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: 32766, want: -32766}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: 32766, want: -32766}, test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: 32767, want: 1}, test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: 32767, want: 1}, test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: -32768, want: 0}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: -32768, want: 0}, test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: -32767, want: -1}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: -32767, want: -32767}, test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: -1, want: 0}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: -1, want: -1}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: 0, want: 0}, test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: 1, want: 0}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: 1, want: 1}, test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: 32766, want: -2}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: 32766, want: 32766}, test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: 32767, want: -1}, test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: 32767, want: 32767}, test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: -32768, want: -32767}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: -32768, want: -1}, test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: -32767, want: 0}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: -32767, want: 0}, test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: -1, want: 0}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: -1, want: -1}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: 0, want: 0}, test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: 1, want: 0}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: 1, want: 1}, test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: 32766, want: -1}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: 32766, want: 32766}, test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: 32767, want: 0}, test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: 32767, want: 0}, test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: -32768, want: -1}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: -32768, want: 0}, test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: -32767, want: -1}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: -32767, want: 0}, test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: -1, want: 0}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: -1, want: 0}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: 0, want: 0}, test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: 1, want: 0}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: 1, want: 0}, test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: 32766, want: -1}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: 32766, want: 0}, test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: 32767, want: -1}, test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: 32767, want: 0}, test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: -32768, want: 0}, test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: -32767, want: 0}, test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: -1, want: 0}, test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: 1, want: 0}, test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: 32766, want: 0}, test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: 32767, want: 0}, test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: -32768, want: 1}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: -32768, want: 0}, test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: -32767, want: 1}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: -32767, want: 0}, test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: -1, want: 0}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: -1, want: 0}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: 0, want: 0}, test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: 1, want: 0}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: 1, want: 0}, test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: 32766, want: 1}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: 32766, want: 0}, test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: 32767, want: 1}, test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: 32767, want: 0}, test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: -32768, want: 32766}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: -32768, want: -2}, test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: -32767, want: 32766}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: -32767, want: -1}, test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: -1, want: 0}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: -1, want: -1}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: 0, want: 0}, test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: 1, want: 0}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: 1, want: 1}, test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: 32766, want: 0}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: 32766, want: 0}, test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: 32767, want: 32766}, test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: 32767, want: 1}, test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: -32768, want: 32767}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: -32768, want: -1}, test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: -32767, want: 0}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: -32767, want: 0}, test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: -1, want: 0}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: -1, want: -1}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: 0, want: 0}, test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: 1, want: 0}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: 1, want: 1}, test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: 32766, want: 1}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: 32766, want: 32766}, test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: 32767, want: 0}, test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: 32767, want: 0}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: -32768, want: -32768}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: -32768, want: -32768}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: -32767, want: -32768}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: -32767, want: -32768}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: -1, want: -32768}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: -1, want: -32768}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: 0, want: 0}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: 0, want: 0}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: 1, want: 0}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: 1, want: 0}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: 32766, want: 0}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: 32766, want: 0}, test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: 32767, want: 0}, test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: 32767, want: 0}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: -32768, want: -32768}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: -32768, want: -32768}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: -32767, want: -32767}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: -32767, want: -32767}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: -1, want: -32767}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: -1, want: -32767}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: 0, want: 0}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: 0, want: 0}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: 1, want: 1}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: 1, want: 1}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: 32766, want: 0}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: 32766, want: 0}, test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: 32767, want: 1}, test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: 32767, want: 1}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: -32768, want: -32768}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: -32768, want: -32768}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: -32767, want: -32767}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: -32767, want: -32767}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: -1, want: -1}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: -1, want: -1}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: 0, want: 0}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: 0, want: 0}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: 1, want: 1}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: 1, want: 1}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: 32766, want: 32766}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: 32766, want: 32766}, test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: 32767, want: 32767}, test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: 32767, want: 32767}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: -32768, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: -32768, want: 0}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: -32767, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: -32767, want: 0}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: -1, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: -1, want: 0}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: 0, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: 0, want: 0}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: 1, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: 1, want: 0}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: 32766, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: 32766, want: 0}, test_int16{fn: and_0_int16, fnname: "and_0_int16", in: 32767, want: 0}, test_int16{fn: and_int16_0, fnname: "and_int16_0", in: 32767, want: 0}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: -32768, want: 0}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: -32768, want: 0}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: -32767, want: 1}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: -32767, want: 1}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: -1, want: 1}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: -1, want: 1}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: 0, want: 0}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: 0, want: 0}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: 1, want: 1}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: 1, want: 1}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: 32766, want: 0}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: 32766, want: 0}, test_int16{fn: and_1_int16, fnname: "and_1_int16", in: 32767, want: 1}, test_int16{fn: and_int16_1, fnname: "and_int16_1", in: 32767, want: 1}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: -32768, want: 0}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: -32768, want: 0}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: -32767, want: 0}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: -32767, want: 0}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: -1, want: 32766}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: -1, want: 32766}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: 0, want: 0}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: 0, want: 0}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: 1, want: 0}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: 1, want: 0}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: 32766, want: 32766}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: 32766, want: 32766}, test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: 32767, want: 32766}, test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: 32767, want: 32766}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: -32768, want: 0}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: -32768, want: 0}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: -32767, want: 1}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: -32767, want: 1}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: -1, want: 32767}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: -1, want: 32767}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: 0, want: 0}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: 0, want: 0}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: 1, want: 1}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: 1, want: 1}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: 32766, want: 32766}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: 32766, want: 32766}, test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: 32767, want: 32767}, test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: 32767, want: 32767}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: -32768, want: -32768}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: -32768, want: -32768}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: -32767, want: -32767}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: -32767, want: -32767}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: -1, want: -1}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: -1, want: -1}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: 0, want: -32768}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: 0, want: -32768}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: 1, want: -32767}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: 1, want: -32767}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: 32766, want: -2}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: 32766, want: -2}, test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: 32767, want: -1}, test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: 32767, want: -1}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: -32768, want: -32767}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: -32768, want: -32767}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: -32767, want: -32767}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: -32767, want: -32767}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: -1, want: -1}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: -1, want: -1}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: 0, want: -32767}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: 0, want: -32767}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: 1, want: -32767}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: 1, want: -32767}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: 32766, want: -1}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: 32766, want: -1}, test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: 32767, want: -1}, test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: 32767, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: -32768, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: -32768, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: -32767, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: -32767, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: -1, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: -1, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: 0, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: 0, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: 1, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: 1, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: 32766, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: 32766, want: -1}, test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: 32767, want: -1}, test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: 32767, want: -1}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: -32768, want: -32768}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: -32768, want: -32768}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: -32767, want: -32767}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: -32767, want: -32767}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: -1, want: -1}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: -1, want: -1}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: 0, want: 0}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: 0, want: 0}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: 1, want: 1}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: 1, want: 1}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: 32766, want: 32766}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: 32766, want: 32766}, test_int16{fn: or_0_int16, fnname: "or_0_int16", in: 32767, want: 32767}, test_int16{fn: or_int16_0, fnname: "or_int16_0", in: 32767, want: 32767}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: -32768, want: -32767}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: -32768, want: -32767}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: -32767, want: -32767}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: -32767, want: -32767}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: -1, want: -1}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: -1, want: -1}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: 0, want: 1}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: 0, want: 1}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: 1, want: 1}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: 1, want: 1}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: 32766, want: 32767}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: 32766, want: 32767}, test_int16{fn: or_1_int16, fnname: "or_1_int16", in: 32767, want: 32767}, test_int16{fn: or_int16_1, fnname: "or_int16_1", in: 32767, want: 32767}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: -32768, want: -2}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: -32768, want: -2}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: -32767, want: -1}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: -32767, want: -1}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: -1, want: -1}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: -1, want: -1}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: 0, want: 32766}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: 0, want: 32766}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: 1, want: 32767}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: 1, want: 32767}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: 32766, want: 32766}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: 32766, want: 32766}, test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: 32767, want: 32767}, test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: 32767, want: 32767}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: -32768, want: -1}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: -32768, want: -1}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: -32767, want: -1}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: -32767, want: -1}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: -1, want: -1}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: -1, want: -1}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: 0, want: 32767}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: 0, want: 32767}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: 1, want: 32767}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: 1, want: 32767}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: 32766, want: 32767}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: 32766, want: 32767}, test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: 32767, want: 32767}, test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: 32767, want: 32767}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: -32768, want: 0}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: -32768, want: 0}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: -32767, want: 1}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: -32767, want: 1}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: -1, want: 32767}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: -1, want: 32767}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: 0, want: -32768}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: 0, want: -32768}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: 1, want: -32767}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: 1, want: -32767}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: 32766, want: -2}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: 32766, want: -2}, test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: 32767, want: -1}, test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: 32767, want: -1}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: -32768, want: 1}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: -32768, want: 1}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: -32767, want: 0}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: -32767, want: 0}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: -1, want: 32766}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: -1, want: 32766}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: 0, want: -32767}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: 0, want: -32767}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: 1, want: -32768}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: 1, want: -32768}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: 32766, want: -1}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: 32766, want: -1}, test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: 32767, want: -2}, test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: 32767, want: -2}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: -32768, want: 32767}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: -32768, want: 32767}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: -32767, want: 32766}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: -32767, want: 32766}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: -1, want: 0}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: -1, want: 0}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: 0, want: -1}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: 0, want: -1}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: 1, want: -2}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: 1, want: -2}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: 32766, want: -32767}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: 32766, want: -32767}, test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: 32767, want: -32768}, test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: 32767, want: -32768}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: -32768, want: -32768}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: -32768, want: -32768}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: -32767, want: -32767}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: -32767, want: -32767}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: -1, want: -1}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: -1, want: -1}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: 0, want: 0}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: 0, want: 0}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: 1, want: 1}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: 1, want: 1}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: 32766, want: 32766}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: 32766, want: 32766}, test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: 32767, want: 32767}, test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: 32767, want: 32767}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: -32768, want: -32767}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: -32768, want: -32767}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: -32767, want: -32768}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: -32767, want: -32768}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: -1, want: -2}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: -1, want: -2}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: 0, want: 1}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: 0, want: 1}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: 1, want: 0}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: 1, want: 0}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: 32766, want: 32767}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: 32766, want: 32767}, test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: 32767, want: 32766}, test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: 32767, want: 32766}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: -32768, want: -2}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: -32768, want: -2}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: -32767, want: -1}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: -32767, want: -1}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: -1, want: -32767}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: -1, want: -32767}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: 0, want: 32766}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: 0, want: 32766}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: 1, want: 32767}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: 1, want: 32767}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: 32766, want: 0}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: 32766, want: 0}, test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: 32767, want: 1}, test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: 32767, want: 1}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: -32768, want: -1}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: -32768, want: -1}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: -32767, want: -2}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: -32767, want: -2}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: -1, want: -32768}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: -1, want: -32768}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: 0, want: 32767}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: 0, want: 32767}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: 1, want: 32766}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: 1, want: 32766}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: 32766, want: 1}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: 32766, want: 1}, test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: 32767, want: 0}, test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: 32767, want: 0}} type test_uint8 struct { fn func(uint8) uint8 fnname string in uint8 want uint8 } var tests_uint8 = []test_uint8{ test_uint8{fn: add_0_uint8, fnname: "add_0_uint8", in: 0, want: 0}, test_uint8{fn: add_uint8_0, fnname: "add_uint8_0", in: 0, want: 0}, test_uint8{fn: add_0_uint8, fnname: "add_0_uint8", in: 1, want: 1}, test_uint8{fn: add_uint8_0, fnname: "add_uint8_0", in: 1, want: 1}, test_uint8{fn: add_0_uint8, fnname: "add_0_uint8", in: 255, want: 255}, test_uint8{fn: add_uint8_0, fnname: "add_uint8_0", in: 255, want: 255}, test_uint8{fn: add_1_uint8, fnname: "add_1_uint8", in: 0, want: 1}, test_uint8{fn: add_uint8_1, fnname: "add_uint8_1", in: 0, want: 1}, test_uint8{fn: add_1_uint8, fnname: "add_1_uint8", in: 1, want: 2}, test_uint8{fn: add_uint8_1, fnname: "add_uint8_1", in: 1, want: 2}, test_uint8{fn: add_1_uint8, fnname: "add_1_uint8", in: 255, want: 0}, test_uint8{fn: add_uint8_1, fnname: "add_uint8_1", in: 255, want: 0}, test_uint8{fn: add_255_uint8, fnname: "add_255_uint8", in: 0, want: 255}, test_uint8{fn: add_uint8_255, fnname: "add_uint8_255", in: 0, want: 255}, test_uint8{fn: add_255_uint8, fnname: "add_255_uint8", in: 1, want: 0}, test_uint8{fn: add_uint8_255, fnname: "add_uint8_255", in: 1, want: 0}, test_uint8{fn: add_255_uint8, fnname: "add_255_uint8", in: 255, want: 254}, test_uint8{fn: add_uint8_255, fnname: "add_uint8_255", in: 255, want: 254}, test_uint8{fn: sub_0_uint8, fnname: "sub_0_uint8", in: 0, want: 0}, test_uint8{fn: sub_uint8_0, fnname: "sub_uint8_0", in: 0, want: 0}, test_uint8{fn: sub_0_uint8, fnname: "sub_0_uint8", in: 1, want: 255}, test_uint8{fn: sub_uint8_0, fnname: "sub_uint8_0", in: 1, want: 1}, test_uint8{fn: sub_0_uint8, fnname: "sub_0_uint8", in: 255, want: 1}, test_uint8{fn: sub_uint8_0, fnname: "sub_uint8_0", in: 255, want: 255}, test_uint8{fn: sub_1_uint8, fnname: "sub_1_uint8", in: 0, want: 1}, test_uint8{fn: sub_uint8_1, fnname: "sub_uint8_1", in: 0, want: 255}, test_uint8{fn: sub_1_uint8, fnname: "sub_1_uint8", in: 1, want: 0}, test_uint8{fn: sub_uint8_1, fnname: "sub_uint8_1", in: 1, want: 0}, test_uint8{fn: sub_1_uint8, fnname: "sub_1_uint8", in: 255, want: 2}, test_uint8{fn: sub_uint8_1, fnname: "sub_uint8_1", in: 255, want: 254}, test_uint8{fn: sub_255_uint8, fnname: "sub_255_uint8", in: 0, want: 255}, test_uint8{fn: sub_uint8_255, fnname: "sub_uint8_255", in: 0, want: 1}, test_uint8{fn: sub_255_uint8, fnname: "sub_255_uint8", in: 1, want: 254}, test_uint8{fn: sub_uint8_255, fnname: "sub_uint8_255", in: 1, want: 2}, test_uint8{fn: sub_255_uint8, fnname: "sub_255_uint8", in: 255, want: 0}, test_uint8{fn: sub_uint8_255, fnname: "sub_uint8_255", in: 255, want: 0}, test_uint8{fn: div_0_uint8, fnname: "div_0_uint8", in: 1, want: 0}, test_uint8{fn: div_0_uint8, fnname: "div_0_uint8", in: 255, want: 0}, test_uint8{fn: div_uint8_1, fnname: "div_uint8_1", in: 0, want: 0}, test_uint8{fn: div_1_uint8, fnname: "div_1_uint8", in: 1, want: 1}, test_uint8{fn: div_uint8_1, fnname: "div_uint8_1", in: 1, want: 1}, test_uint8{fn: div_1_uint8, fnname: "div_1_uint8", in: 255, want: 0}, test_uint8{fn: div_uint8_1, fnname: "div_uint8_1", in: 255, want: 255}, test_uint8{fn: div_uint8_255, fnname: "div_uint8_255", in: 0, want: 0}, test_uint8{fn: div_255_uint8, fnname: "div_255_uint8", in: 1, want: 255}, test_uint8{fn: div_uint8_255, fnname: "div_uint8_255", in: 1, want: 0}, test_uint8{fn: div_255_uint8, fnname: "div_255_uint8", in: 255, want: 1}, test_uint8{fn: div_uint8_255, fnname: "div_uint8_255", in: 255, want: 1}, test_uint8{fn: mul_0_uint8, fnname: "mul_0_uint8", in: 0, want: 0}, test_uint8{fn: mul_uint8_0, fnname: "mul_uint8_0", in: 0, want: 0}, test_uint8{fn: mul_0_uint8, fnname: "mul_0_uint8", in: 1, want: 0}, test_uint8{fn: mul_uint8_0, fnname: "mul_uint8_0", in: 1, want: 0}, test_uint8{fn: mul_0_uint8, fnname: "mul_0_uint8", in: 255, want: 0}, test_uint8{fn: mul_uint8_0, fnname: "mul_uint8_0", in: 255, want: 0}, test_uint8{fn: mul_1_uint8, fnname: "mul_1_uint8", in: 0, want: 0}, test_uint8{fn: mul_uint8_1, fnname: "mul_uint8_1", in: 0, want: 0}, test_uint8{fn: mul_1_uint8, fnname: "mul_1_uint8", in: 1, want: 1}, test_uint8{fn: mul_uint8_1, fnname: "mul_uint8_1", in: 1, want: 1}, test_uint8{fn: mul_1_uint8, fnname: "mul_1_uint8", in: 255, want: 255}, test_uint8{fn: mul_uint8_1, fnname: "mul_uint8_1", in: 255, want: 255}, test_uint8{fn: mul_255_uint8, fnname: "mul_255_uint8", in: 0, want: 0}, test_uint8{fn: mul_uint8_255, fnname: "mul_uint8_255", in: 0, want: 0}, test_uint8{fn: mul_255_uint8, fnname: "mul_255_uint8", in: 1, want: 255}, test_uint8{fn: mul_uint8_255, fnname: "mul_uint8_255", in: 1, want: 255}, test_uint8{fn: mul_255_uint8, fnname: "mul_255_uint8", in: 255, want: 1}, test_uint8{fn: mul_uint8_255, fnname: "mul_uint8_255", in: 255, want: 1}, test_uint8{fn: lsh_0_uint8, fnname: "lsh_0_uint8", in: 0, want: 0}, test_uint8{fn: lsh_uint8_0, fnname: "lsh_uint8_0", in: 0, want: 0}, test_uint8{fn: lsh_0_uint8, fnname: "lsh_0_uint8", in: 1, want: 0}, test_uint8{fn: lsh_uint8_0, fnname: "lsh_uint8_0", in: 1, want: 1}, test_uint8{fn: lsh_0_uint8, fnname: "lsh_0_uint8", in: 255, want: 0}, test_uint8{fn: lsh_uint8_0, fnname: "lsh_uint8_0", in: 255, want: 255}, test_uint8{fn: lsh_1_uint8, fnname: "lsh_1_uint8", in: 0, want: 1}, test_uint8{fn: lsh_uint8_1, fnname: "lsh_uint8_1", in: 0, want: 0}, test_uint8{fn: lsh_1_uint8, fnname: "lsh_1_uint8", in: 1, want: 2}, test_uint8{fn: lsh_uint8_1, fnname: "lsh_uint8_1", in: 1, want: 2}, test_uint8{fn: lsh_1_uint8, fnname: "lsh_1_uint8", in: 255, want: 0}, test_uint8{fn: lsh_uint8_1, fnname: "lsh_uint8_1", in: 255, want: 254}, test_uint8{fn: lsh_255_uint8, fnname: "lsh_255_uint8", in: 0, want: 255}, test_uint8{fn: lsh_uint8_255, fnname: "lsh_uint8_255", in: 0, want: 0}, test_uint8{fn: lsh_255_uint8, fnname: "lsh_255_uint8", in: 1, want: 254}, test_uint8{fn: lsh_uint8_255, fnname: "lsh_uint8_255", in: 1, want: 0}, test_uint8{fn: lsh_255_uint8, fnname: "lsh_255_uint8", in: 255, want: 0}, test_uint8{fn: lsh_uint8_255, fnname: "lsh_uint8_255", in: 255, want: 0}, test_uint8{fn: rsh_0_uint8, fnname: "rsh_0_uint8", in: 0, want: 0}, test_uint8{fn: rsh_uint8_0, fnname: "rsh_uint8_0", in: 0, want: 0}, test_uint8{fn: rsh_0_uint8, fnname: "rsh_0_uint8", in: 1, want: 0}, test_uint8{fn: rsh_uint8_0, fnname: "rsh_uint8_0", in: 1, want: 1}, test_uint8{fn: rsh_0_uint8, fnname: "rsh_0_uint8", in: 255, want: 0}, test_uint8{fn: rsh_uint8_0, fnname: "rsh_uint8_0", in: 255, want: 255}, test_uint8{fn: rsh_1_uint8, fnname: "rsh_1_uint8", in: 0, want: 1}, test_uint8{fn: rsh_uint8_1, fnname: "rsh_uint8_1", in: 0, want: 0}, test_uint8{fn: rsh_1_uint8, fnname: "rsh_1_uint8", in: 1, want: 0}, test_uint8{fn: rsh_uint8_1, fnname: "rsh_uint8_1", in: 1, want: 0}, test_uint8{fn: rsh_1_uint8, fnname: "rsh_1_uint8", in: 255, want: 0}, test_uint8{fn: rsh_uint8_1, fnname: "rsh_uint8_1", in: 255, want: 127}, test_uint8{fn: rsh_255_uint8, fnname: "rsh_255_uint8", in: 0, want: 255}, test_uint8{fn: rsh_uint8_255, fnname: "rsh_uint8_255", in: 0, want: 0}, test_uint8{fn: rsh_255_uint8, fnname: "rsh_255_uint8", in: 1, want: 127}, test_uint8{fn: rsh_uint8_255, fnname: "rsh_uint8_255", in: 1, want: 0}, test_uint8{fn: rsh_255_uint8, fnname: "rsh_255_uint8", in: 255, want: 0}, test_uint8{fn: rsh_uint8_255, fnname: "rsh_uint8_255", in: 255, want: 0}, test_uint8{fn: mod_0_uint8, fnname: "mod_0_uint8", in: 1, want: 0}, test_uint8{fn: mod_0_uint8, fnname: "mod_0_uint8", in: 255, want: 0}, test_uint8{fn: mod_uint8_1, fnname: "mod_uint8_1", in: 0, want: 0}, test_uint8{fn: mod_1_uint8, fnname: "mod_1_uint8", in: 1, want: 0}, test_uint8{fn: mod_uint8_1, fnname: "mod_uint8_1", in: 1, want: 0}, test_uint8{fn: mod_1_uint8, fnname: "mod_1_uint8", in: 255, want: 1}, test_uint8{fn: mod_uint8_1, fnname: "mod_uint8_1", in: 255, want: 0}, test_uint8{fn: mod_uint8_255, fnname: "mod_uint8_255", in: 0, want: 0}, test_uint8{fn: mod_255_uint8, fnname: "mod_255_uint8", in: 1, want: 0}, test_uint8{fn: mod_uint8_255, fnname: "mod_uint8_255", in: 1, want: 1}, test_uint8{fn: mod_255_uint8, fnname: "mod_255_uint8", in: 255, want: 0}, test_uint8{fn: mod_uint8_255, fnname: "mod_uint8_255", in: 255, want: 0}, test_uint8{fn: and_0_uint8, fnname: "and_0_uint8", in: 0, want: 0}, test_uint8{fn: and_uint8_0, fnname: "and_uint8_0", in: 0, want: 0}, test_uint8{fn: and_0_uint8, fnname: "and_0_uint8", in: 1, want: 0}, test_uint8{fn: and_uint8_0, fnname: "and_uint8_0", in: 1, want: 0}, test_uint8{fn: and_0_uint8, fnname: "and_0_uint8", in: 255, want: 0}, test_uint8{fn: and_uint8_0, fnname: "and_uint8_0", in: 255, want: 0}, test_uint8{fn: and_1_uint8, fnname: "and_1_uint8", in: 0, want: 0}, test_uint8{fn: and_uint8_1, fnname: "and_uint8_1", in: 0, want: 0}, test_uint8{fn: and_1_uint8, fnname: "and_1_uint8", in: 1, want: 1}, test_uint8{fn: and_uint8_1, fnname: "and_uint8_1", in: 1, want: 1}, test_uint8{fn: and_1_uint8, fnname: "and_1_uint8", in: 255, want: 1}, test_uint8{fn: and_uint8_1, fnname: "and_uint8_1", in: 255, want: 1}, test_uint8{fn: and_255_uint8, fnname: "and_255_uint8", in: 0, want: 0}, test_uint8{fn: and_uint8_255, fnname: "and_uint8_255", in: 0, want: 0}, test_uint8{fn: and_255_uint8, fnname: "and_255_uint8", in: 1, want: 1}, test_uint8{fn: and_uint8_255, fnname: "and_uint8_255", in: 1, want: 1}, test_uint8{fn: and_255_uint8, fnname: "and_255_uint8", in: 255, want: 255}, test_uint8{fn: and_uint8_255, fnname: "and_uint8_255", in: 255, want: 255}, test_uint8{fn: or_0_uint8, fnname: "or_0_uint8", in: 0, want: 0}, test_uint8{fn: or_uint8_0, fnname: "or_uint8_0", in: 0, want: 0}, test_uint8{fn: or_0_uint8, fnname: "or_0_uint8", in: 1, want: 1}, test_uint8{fn: or_uint8_0, fnname: "or_uint8_0", in: 1, want: 1}, test_uint8{fn: or_0_uint8, fnname: "or_0_uint8", in: 255, want: 255}, test_uint8{fn: or_uint8_0, fnname: "or_uint8_0", in: 255, want: 255}, test_uint8{fn: or_1_uint8, fnname: "or_1_uint8", in: 0, want: 1}, test_uint8{fn: or_uint8_1, fnname: "or_uint8_1", in: 0, want: 1}, test_uint8{fn: or_1_uint8, fnname: "or_1_uint8", in: 1, want: 1}, test_uint8{fn: or_uint8_1, fnname: "or_uint8_1", in: 1, want: 1}, test_uint8{fn: or_1_uint8, fnname: "or_1_uint8", in: 255, want: 255}, test_uint8{fn: or_uint8_1, fnname: "or_uint8_1", in: 255, want: 255}, test_uint8{fn: or_255_uint8, fnname: "or_255_uint8", in: 0, want: 255}, test_uint8{fn: or_uint8_255, fnname: "or_uint8_255", in: 0, want: 255}, test_uint8{fn: or_255_uint8, fnname: "or_255_uint8", in: 1, want: 255}, test_uint8{fn: or_uint8_255, fnname: "or_uint8_255", in: 1, want: 255}, test_uint8{fn: or_255_uint8, fnname: "or_255_uint8", in: 255, want: 255}, test_uint8{fn: or_uint8_255, fnname: "or_uint8_255", in: 255, want: 255}, test_uint8{fn: xor_0_uint8, fnname: "xor_0_uint8", in: 0, want: 0}, test_uint8{fn: xor_uint8_0, fnname: "xor_uint8_0", in: 0, want: 0}, test_uint8{fn: xor_0_uint8, fnname: "xor_0_uint8", in: 1, want: 1}, test_uint8{fn: xor_uint8_0, fnname: "xor_uint8_0", in: 1, want: 1}, test_uint8{fn: xor_0_uint8, fnname: "xor_0_uint8", in: 255, want: 255}, test_uint8{fn: xor_uint8_0, fnname: "xor_uint8_0", in: 255, want: 255}, test_uint8{fn: xor_1_uint8, fnname: "xor_1_uint8", in: 0, want: 1}, test_uint8{fn: xor_uint8_1, fnname: "xor_uint8_1", in: 0, want: 1}, test_uint8{fn: xor_1_uint8, fnname: "xor_1_uint8", in: 1, want: 0}, test_uint8{fn: xor_uint8_1, fnname: "xor_uint8_1", in: 1, want: 0}, test_uint8{fn: xor_1_uint8, fnname: "xor_1_uint8", in: 255, want: 254}, test_uint8{fn: xor_uint8_1, fnname: "xor_uint8_1", in: 255, want: 254}, test_uint8{fn: xor_255_uint8, fnname: "xor_255_uint8", in: 0, want: 255}, test_uint8{fn: xor_uint8_255, fnname: "xor_uint8_255", in: 0, want: 255}, test_uint8{fn: xor_255_uint8, fnname: "xor_255_uint8", in: 1, want: 254}, test_uint8{fn: xor_uint8_255, fnname: "xor_uint8_255", in: 1, want: 254}, test_uint8{fn: xor_255_uint8, fnname: "xor_255_uint8", in: 255, want: 0}, test_uint8{fn: xor_uint8_255, fnname: "xor_uint8_255", in: 255, want: 0}} type test_int8 struct { fn func(int8) int8 fnname string in int8 want int8 } var tests_int8 = []test_int8{ test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: -128, want: 0}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: -128, want: 0}, test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: -127, want: 1}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: -127, want: 1}, test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: -1, want: 127}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: -1, want: 127}, test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: 0, want: -128}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: 0, want: -128}, test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: 1, want: -127}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: 1, want: -127}, test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: 126, want: -2}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: 126, want: -2}, test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: 127, want: -1}, test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: 127, want: -1}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: -128, want: 1}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: -128, want: 1}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: -127, want: 2}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: -127, want: 2}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: -1, want: -128}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: -1, want: -128}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: 0, want: -127}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: 0, want: -127}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: 1, want: -126}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: 1, want: -126}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: 126, want: -1}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: 126, want: -1}, test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: 127, want: 0}, test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: 127, want: 0}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: -128, want: 127}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: -128, want: 127}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: -127, want: -128}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: -127, want: -128}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: -1, want: -2}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: -1, want: -2}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: 0, want: -1}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: 0, want: -1}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: 1, want: 0}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: 1, want: 0}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: 126, want: 125}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: 126, want: 125}, test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: 127, want: 126}, test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: 127, want: 126}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: -128, want: -128}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: -128, want: -128}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: -127, want: -127}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: -127, want: -127}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: -1, want: -1}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: -1, want: -1}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: 0, want: 0}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: 0, want: 0}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: 1, want: 1}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: 1, want: 1}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: 126, want: 126}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: 126, want: 126}, test_int8{fn: add_0_int8, fnname: "add_0_int8", in: 127, want: 127}, test_int8{fn: add_int8_0, fnname: "add_int8_0", in: 127, want: 127}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: -128, want: -127}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: -128, want: -127}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: -127, want: -126}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: -127, want: -126}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: -1, want: 0}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: -1, want: 0}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: 0, want: 1}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: 0, want: 1}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: 1, want: 2}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: 1, want: 2}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: 126, want: 127}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: 126, want: 127}, test_int8{fn: add_1_int8, fnname: "add_1_int8", in: 127, want: -128}, test_int8{fn: add_int8_1, fnname: "add_int8_1", in: 127, want: -128}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: -128, want: -2}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: -128, want: -2}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: -127, want: -1}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: -127, want: -1}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: -1, want: 125}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: -1, want: 125}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: 0, want: 126}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: 0, want: 126}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: 1, want: 127}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: 1, want: 127}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: 126, want: -4}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: 126, want: -4}, test_int8{fn: add_126_int8, fnname: "add_126_int8", in: 127, want: -3}, test_int8{fn: add_int8_126, fnname: "add_int8_126", in: 127, want: -3}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: -128, want: -1}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: -128, want: -1}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: -127, want: 0}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: -127, want: 0}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: -1, want: 126}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: -1, want: 126}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: 0, want: 127}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: 0, want: 127}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: 1, want: -128}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: 1, want: -128}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: 126, want: -3}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: 126, want: -3}, test_int8{fn: add_127_int8, fnname: "add_127_int8", in: 127, want: -2}, test_int8{fn: add_int8_127, fnname: "add_int8_127", in: 127, want: -2}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: -128, want: 0}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: -128, want: 0}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: -127, want: -1}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: -127, want: 1}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: -1, want: -127}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: -1, want: 127}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: 0, want: -128}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: 0, want: -128}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: 1, want: 127}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: 1, want: -127}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: 126, want: 2}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: 126, want: -2}, test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: 127, want: 1}, test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: 127, want: -1}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: -128, want: 1}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: -128, want: -1}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: -127, want: 0}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: -127, want: 0}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: -1, want: -126}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: -1, want: 126}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: 0, want: -127}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: 0, want: 127}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: 1, want: -128}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: 1, want: -128}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: 126, want: 3}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: 126, want: -3}, test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: 127, want: 2}, test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: 127, want: -2}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: -128, want: 127}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: -128, want: -127}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: -127, want: 126}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: -127, want: -126}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: -1, want: 0}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: -1, want: 0}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: 0, want: -1}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: 0, want: 1}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: 1, want: -2}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: 1, want: 2}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: 126, want: -127}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: 126, want: 127}, test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: 127, want: -128}, test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: 127, want: -128}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: -128, want: -128}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: -128, want: -128}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: -127, want: 127}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: -127, want: -127}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: -1, want: 1}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: -1, want: -1}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: 0, want: 0}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: 0, want: 0}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: 1, want: -1}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: 1, want: 1}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: 126, want: -126}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: 126, want: 126}, test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: 127, want: -127}, test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: 127, want: 127}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: -128, want: -127}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: -128, want: 127}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: -127, want: -128}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: -127, want: -128}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: -1, want: 2}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: -1, want: -2}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: 0, want: 1}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: 0, want: -1}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: 1, want: 0}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: 1, want: 0}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: 126, want: -125}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: 126, want: 125}, test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: 127, want: -126}, test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: 127, want: 126}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: -128, want: -2}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: -128, want: 2}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: -127, want: -3}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: -127, want: 3}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: -1, want: 127}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: -1, want: -127}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: 0, want: 126}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: 0, want: -126}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: 1, want: 125}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: 1, want: -125}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: 126, want: 0}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: 126, want: 0}, test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: 127, want: -1}, test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: 127, want: 1}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: -128, want: -1}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: -128, want: 1}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: -127, want: -2}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: -127, want: 2}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: -1, want: -128}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: -1, want: -128}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: 0, want: 127}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: 0, want: -127}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: 1, want: 126}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: 1, want: -126}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: 126, want: 1}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: 126, want: -1}, test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: 127, want: 0}, test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: 127, want: 0}, test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: -128, want: 1}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: -128, want: 1}, test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: -127, want: 1}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: -127, want: 0}, test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: -1, want: -128}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: -1, want: 0}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: 0, want: 0}, test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: 1, want: -128}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: 1, want: 0}, test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: 126, want: -1}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: 126, want: 0}, test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: 127, want: -1}, test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: 127, want: 0}, test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: -128, want: 0}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: -128, want: 1}, test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: -127, want: 1}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: -127, want: 1}, test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: -1, want: 127}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: -1, want: 0}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: 0, want: 0}, test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: 1, want: -127}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: 1, want: 0}, test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: 126, want: -1}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: 126, want: 0}, test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: 127, want: -1}, test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: 127, want: -1}, test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: -128, want: 0}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: -128, want: -128}, test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: -127, want: 0}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: -127, want: 127}, test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: -1, want: 1}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: -1, want: 1}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: 0, want: 0}, test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: 1, want: -1}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: 1, want: -1}, test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: 126, want: 0}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: 126, want: -126}, test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: 127, want: 0}, test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: 127, want: -127}, test_int8{fn: div_0_int8, fnname: "div_0_int8", in: -128, want: 0}, test_int8{fn: div_0_int8, fnname: "div_0_int8", in: -127, want: 0}, test_int8{fn: div_0_int8, fnname: "div_0_int8", in: -1, want: 0}, test_int8{fn: div_0_int8, fnname: "div_0_int8", in: 1, want: 0}, test_int8{fn: div_0_int8, fnname: "div_0_int8", in: 126, want: 0}, test_int8{fn: div_0_int8, fnname: "div_0_int8", in: 127, want: 0}, test_int8{fn: div_1_int8, fnname: "div_1_int8", in: -128, want: 0}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: -128, want: -128}, test_int8{fn: div_1_int8, fnname: "div_1_int8", in: -127, want: 0}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: -127, want: -127}, test_int8{fn: div_1_int8, fnname: "div_1_int8", in: -1, want: -1}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: -1, want: -1}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: 0, want: 0}, test_int8{fn: div_1_int8, fnname: "div_1_int8", in: 1, want: 1}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: 1, want: 1}, test_int8{fn: div_1_int8, fnname: "div_1_int8", in: 126, want: 0}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: 126, want: 126}, test_int8{fn: div_1_int8, fnname: "div_1_int8", in: 127, want: 0}, test_int8{fn: div_int8_1, fnname: "div_int8_1", in: 127, want: 127}, test_int8{fn: div_126_int8, fnname: "div_126_int8", in: -128, want: 0}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: -128, want: -1}, test_int8{fn: div_126_int8, fnname: "div_126_int8", in: -127, want: 0}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: -127, want: -1}, test_int8{fn: div_126_int8, fnname: "div_126_int8", in: -1, want: -126}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: -1, want: 0}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: 0, want: 0}, test_int8{fn: div_126_int8, fnname: "div_126_int8", in: 1, want: 126}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: 1, want: 0}, test_int8{fn: div_126_int8, fnname: "div_126_int8", in: 126, want: 1}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: 126, want: 1}, test_int8{fn: div_126_int8, fnname: "div_126_int8", in: 127, want: 0}, test_int8{fn: div_int8_126, fnname: "div_int8_126", in: 127, want: 1}, test_int8{fn: div_127_int8, fnname: "div_127_int8", in: -128, want: 0}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: -128, want: -1}, test_int8{fn: div_127_int8, fnname: "div_127_int8", in: -127, want: -1}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: -127, want: -1}, test_int8{fn: div_127_int8, fnname: "div_127_int8", in: -1, want: -127}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: -1, want: 0}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: 0, want: 0}, test_int8{fn: div_127_int8, fnname: "div_127_int8", in: 1, want: 127}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: 1, want: 0}, test_int8{fn: div_127_int8, fnname: "div_127_int8", in: 126, want: 1}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: 126, want: 0}, test_int8{fn: div_127_int8, fnname: "div_127_int8", in: 127, want: 1}, test_int8{fn: div_int8_127, fnname: "div_int8_127", in: 127, want: 1}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: -128, want: 0}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: -128, want: 0}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: -127, want: -128}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: -127, want: -128}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: -1, want: -128}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: -1, want: -128}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: 0, want: 0}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: 0, want: 0}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: 1, want: -128}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: 1, want: -128}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: 126, want: 0}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: 126, want: 0}, test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: 127, want: -128}, test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: 127, want: -128}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: -128, want: -128}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: -128, want: -128}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: -127, want: 1}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: -127, want: 1}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: -1, want: 127}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: -1, want: 127}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: 0, want: 0}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: 0, want: 0}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: 1, want: -127}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: 1, want: -127}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: 126, want: 126}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: 126, want: 126}, test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: 127, want: -1}, test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: 127, want: -1}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: -128, want: -128}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: -128, want: -128}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: -127, want: 127}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: -127, want: 127}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: -1, want: 1}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: -1, want: 1}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: 0, want: 0}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: 0, want: 0}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: 1, want: -1}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: 1, want: -1}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: 126, want: -126}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: 126, want: -126}, test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: 127, want: -127}, test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: 127, want: -127}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: -128, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: -128, want: 0}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: -127, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: -127, want: 0}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: -1, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: -1, want: 0}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: 0, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: 0, want: 0}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: 1, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: 1, want: 0}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: 126, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: 126, want: 0}, test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: 127, want: 0}, test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: 127, want: 0}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: -128, want: -128}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: -128, want: -128}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: -127, want: -127}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: -127, want: -127}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: -1, want: -1}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: -1, want: -1}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: 0, want: 0}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: 0, want: 0}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: 1, want: 1}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: 1, want: 1}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: 126, want: 126}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: 126, want: 126}, test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: 127, want: 127}, test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: 127, want: 127}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: -128, want: 0}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: -128, want: 0}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: -127, want: 126}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: -127, want: 126}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: -1, want: -126}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: -1, want: -126}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: 0, want: 0}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: 0, want: 0}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: 1, want: 126}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: 1, want: 126}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: 126, want: 4}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: 126, want: 4}, test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: 127, want: -126}, test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: 127, want: -126}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: -128, want: -128}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: -128, want: -128}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: -127, want: -1}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: -127, want: -1}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: -1, want: -127}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: -1, want: -127}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: 0, want: 0}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: 0, want: 0}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: 1, want: 127}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: 1, want: 127}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: 126, want: -126}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: 126, want: -126}, test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: 127, want: 1}, test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: 127, want: 1}, test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: -128, want: 0}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: -128, want: 0}, test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: -127, want: -1}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: -127, want: -127}, test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: -1, want: 0}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: -1, want: -1}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: 0, want: 0}, test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: 1, want: 0}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: 1, want: 1}, test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: 126, want: -2}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: 126, want: 126}, test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: 127, want: -1}, test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: 127, want: 127}, test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: -128, want: -127}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: -128, want: -1}, test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: -127, want: 0}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: -127, want: 0}, test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: -1, want: 0}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: -1, want: -1}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: 0, want: 0}, test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: 1, want: 0}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: 1, want: 1}, test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: 126, want: -1}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: 126, want: 126}, test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: 127, want: 0}, test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: 127, want: 0}, test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: -128, want: -1}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: -128, want: 0}, test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: -127, want: -1}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: -127, want: 0}, test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: -1, want: 0}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: -1, want: 0}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: 0, want: 0}, test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: 1, want: 0}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: 1, want: 0}, test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: 126, want: -1}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: 126, want: 0}, test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: 127, want: -1}, test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: 127, want: 0}, test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: -128, want: 0}, test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: -127, want: 0}, test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: -1, want: 0}, test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: 1, want: 0}, test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: 126, want: 0}, test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: 127, want: 0}, test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: -128, want: 1}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: -128, want: 0}, test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: -127, want: 1}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: -127, want: 0}, test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: -1, want: 0}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: -1, want: 0}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: 0, want: 0}, test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: 1, want: 0}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: 1, want: 0}, test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: 126, want: 1}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: 126, want: 0}, test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: 127, want: 1}, test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: 127, want: 0}, test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: -128, want: 126}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: -128, want: -2}, test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: -127, want: 126}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: -127, want: -1}, test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: -1, want: 0}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: -1, want: -1}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: 0, want: 0}, test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: 1, want: 0}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: 1, want: 1}, test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: 126, want: 0}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: 126, want: 0}, test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: 127, want: 126}, test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: 127, want: 1}, test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: -128, want: 127}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: -128, want: -1}, test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: -127, want: 0}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: -127, want: 0}, test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: -1, want: 0}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: -1, want: -1}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: 0, want: 0}, test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: 1, want: 0}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: 1, want: 1}, test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: 126, want: 1}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: 126, want: 126}, test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: 127, want: 0}, test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: 127, want: 0}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: -128, want: -128}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: -128, want: -128}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: -127, want: -128}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: -127, want: -128}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: -1, want: -128}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: -1, want: -128}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: 0, want: 0}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: 0, want: 0}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: 1, want: 0}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: 1, want: 0}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: 126, want: 0}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: 126, want: 0}, test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: 127, want: 0}, test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: 127, want: 0}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: -128, want: -128}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: -128, want: -128}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: -127, want: -127}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: -127, want: -127}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: -1, want: -127}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: -1, want: -127}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: 0, want: 0}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: 0, want: 0}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: 1, want: 1}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: 1, want: 1}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: 126, want: 0}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: 126, want: 0}, test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: 127, want: 1}, test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: 127, want: 1}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: -128, want: -128}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: -128, want: -128}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: -127, want: -127}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: -127, want: -127}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: -1, want: -1}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: -1, want: -1}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: 0, want: 0}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: 0, want: 0}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: 1, want: 1}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: 1, want: 1}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: 126, want: 126}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: 126, want: 126}, test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: 127, want: 127}, test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: 127, want: 127}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: -128, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: -128, want: 0}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: -127, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: -127, want: 0}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: -1, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: -1, want: 0}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: 0, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: 0, want: 0}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: 1, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: 1, want: 0}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: 126, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: 126, want: 0}, test_int8{fn: and_0_int8, fnname: "and_0_int8", in: 127, want: 0}, test_int8{fn: and_int8_0, fnname: "and_int8_0", in: 127, want: 0}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: -128, want: 0}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: -128, want: 0}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: -127, want: 1}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: -127, want: 1}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: -1, want: 1}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: -1, want: 1}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: 0, want: 0}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: 0, want: 0}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: 1, want: 1}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: 1, want: 1}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: 126, want: 0}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: 126, want: 0}, test_int8{fn: and_1_int8, fnname: "and_1_int8", in: 127, want: 1}, test_int8{fn: and_int8_1, fnname: "and_int8_1", in: 127, want: 1}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: -128, want: 0}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: -128, want: 0}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: -127, want: 0}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: -127, want: 0}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: -1, want: 126}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: -1, want: 126}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: 0, want: 0}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: 0, want: 0}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: 1, want: 0}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: 1, want: 0}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: 126, want: 126}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: 126, want: 126}, test_int8{fn: and_126_int8, fnname: "and_126_int8", in: 127, want: 126}, test_int8{fn: and_int8_126, fnname: "and_int8_126", in: 127, want: 126}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: -128, want: 0}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: -128, want: 0}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: -127, want: 1}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: -127, want: 1}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: -1, want: 127}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: -1, want: 127}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: 0, want: 0}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: 0, want: 0}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: 1, want: 1}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: 1, want: 1}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: 126, want: 126}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: 126, want: 126}, test_int8{fn: and_127_int8, fnname: "and_127_int8", in: 127, want: 127}, test_int8{fn: and_int8_127, fnname: "and_int8_127", in: 127, want: 127}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: -128, want: -128}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: -128, want: -128}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: -127, want: -127}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: -127, want: -127}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: -1, want: -1}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: -1, want: -1}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: 0, want: -128}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: 0, want: -128}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: 1, want: -127}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: 1, want: -127}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: 126, want: -2}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: 126, want: -2}, test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: 127, want: -1}, test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: 127, want: -1}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: -128, want: -127}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: -128, want: -127}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: -127, want: -127}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: -127, want: -127}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: -1, want: -1}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: -1, want: -1}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: 0, want: -127}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: 0, want: -127}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: 1, want: -127}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: 1, want: -127}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: 126, want: -1}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: 126, want: -1}, test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: 127, want: -1}, test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: 127, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: -128, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: -128, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: -127, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: -127, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: -1, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: -1, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: 0, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: 0, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: 1, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: 1, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: 126, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: 126, want: -1}, test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: 127, want: -1}, test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: 127, want: -1}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: -128, want: -128}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: -128, want: -128}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: -127, want: -127}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: -127, want: -127}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: -1, want: -1}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: -1, want: -1}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: 0, want: 0}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: 0, want: 0}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: 1, want: 1}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: 1, want: 1}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: 126, want: 126}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: 126, want: 126}, test_int8{fn: or_0_int8, fnname: "or_0_int8", in: 127, want: 127}, test_int8{fn: or_int8_0, fnname: "or_int8_0", in: 127, want: 127}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: -128, want: -127}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: -128, want: -127}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: -127, want: -127}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: -127, want: -127}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: -1, want: -1}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: -1, want: -1}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: 0, want: 1}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: 0, want: 1}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: 1, want: 1}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: 1, want: 1}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: 126, want: 127}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: 126, want: 127}, test_int8{fn: or_1_int8, fnname: "or_1_int8", in: 127, want: 127}, test_int8{fn: or_int8_1, fnname: "or_int8_1", in: 127, want: 127}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: -128, want: -2}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: -128, want: -2}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: -127, want: -1}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: -127, want: -1}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: -1, want: -1}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: -1, want: -1}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: 0, want: 126}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: 0, want: 126}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: 1, want: 127}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: 1, want: 127}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: 126, want: 126}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: 126, want: 126}, test_int8{fn: or_126_int8, fnname: "or_126_int8", in: 127, want: 127}, test_int8{fn: or_int8_126, fnname: "or_int8_126", in: 127, want: 127}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: -128, want: -1}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: -128, want: -1}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: -127, want: -1}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: -127, want: -1}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: -1, want: -1}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: -1, want: -1}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: 0, want: 127}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: 0, want: 127}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: 1, want: 127}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: 1, want: 127}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: 126, want: 127}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: 126, want: 127}, test_int8{fn: or_127_int8, fnname: "or_127_int8", in: 127, want: 127}, test_int8{fn: or_int8_127, fnname: "or_int8_127", in: 127, want: 127}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: -128, want: 0}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: -128, want: 0}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: -127, want: 1}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: -127, want: 1}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: -1, want: 127}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: -1, want: 127}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: 0, want: -128}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: 0, want: -128}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: 1, want: -127}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: 1, want: -127}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: 126, want: -2}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: 126, want: -2}, test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: 127, want: -1}, test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: 127, want: -1}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: -128, want: 1}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: -128, want: 1}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: -127, want: 0}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: -127, want: 0}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: -1, want: 126}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: -1, want: 126}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: 0, want: -127}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: 0, want: -127}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: 1, want: -128}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: 1, want: -128}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: 126, want: -1}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: 126, want: -1}, test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: 127, want: -2}, test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: 127, want: -2}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: -128, want: 127}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: -128, want: 127}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: -127, want: 126}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: -127, want: 126}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: -1, want: 0}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: -1, want: 0}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: 0, want: -1}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: 0, want: -1}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: 1, want: -2}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: 1, want: -2}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: 126, want: -127}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: 126, want: -127}, test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: 127, want: -128}, test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: 127, want: -128}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: -128, want: -128}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: -128, want: -128}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: -127, want: -127}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: -127, want: -127}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: -1, want: -1}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: -1, want: -1}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: 0, want: 0}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: 0, want: 0}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: 1, want: 1}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: 1, want: 1}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: 126, want: 126}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: 126, want: 126}, test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: 127, want: 127}, test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: 127, want: 127}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: -128, want: -127}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: -128, want: -127}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: -127, want: -128}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: -127, want: -128}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: -1, want: -2}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: -1, want: -2}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: 0, want: 1}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: 0, want: 1}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: 1, want: 0}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: 1, want: 0}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: 126, want: 127}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: 126, want: 127}, test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: 127, want: 126}, test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: 127, want: 126}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: -128, want: -2}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: -128, want: -2}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: -127, want: -1}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: -127, want: -1}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: -1, want: -127}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: -1, want: -127}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: 0, want: 126}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: 0, want: 126}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: 1, want: 127}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: 1, want: 127}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: 126, want: 0}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: 126, want: 0}, test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: 127, want: 1}, test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: 127, want: 1}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: -128, want: -1}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: -128, want: -1}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: -127, want: -2}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: -127, want: -2}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: -1, want: -128}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: -1, want: -128}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: 0, want: 127}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: 0, want: 127}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: 1, want: 126}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: 1, want: 126}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: 126, want: 1}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: 126, want: 1}, test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: 127, want: 0}, test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: 127, want: 0}} var failed bool func main() { for _, test := range tests_uint64 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_int64 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_uint32 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_int32 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_uint16 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_int16 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_uint8 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } for _, test := range tests_int8 { if got := test.fn(test.in); got != test.want { fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) failed = true } } if failed { os.Exit(1) } } -- diff -- @@ -4,25191 +4,6633 @@ package main import "fmt" +import "os" //go:noinline -func add_uint64_0_ssa(a uint64) uint64 { - return a + 0 -} +func add_uint64_0(a uint64) uint64 { return a + 0 } + +//go:noinline +func add_0_uint64(a uint64) uint64 { return 0 + a } + +//go:noinline +func add_uint64_1(a uint64) uint64 { return a + 1 } + +//go:noinline +func add_1_uint64(a uint64) uint64 { return 1 + a } + +//go:noinline +func add_uint64_4294967296(a uint64) uint64 { return a + 4294967296 } + +//go:noinline +func add_4294967296_uint64(a uint64) uint64 { return 4294967296 + a } //go:noinline -func add_0_uint64_ssa(a uint64) uint64 { - return 0 + a -} +func add_uint64_9223372036854775808(a uint64) uint64 { return a + 9223372036854775808 } //go:noinline -func add_uint64_1_ssa(a uint64) uint64 { - return a + 1 -} +func add_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 + a } //go:noinline -func add_1_uint64_ssa(a uint64) uint64 { - return 1 + a -} +func add_uint64_18446744073709551615(a uint64) uint64 { return a + 18446744073709551615 } //go:noinline -func add_uint64_4294967296_ssa(a uint64) uint64 { - return a + 4294967296 -} +func add_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 + a } //go:noinline -func add_4294967296_uint64_ssa(a uint64) uint64 { - return 4294967296 + a -} +func sub_uint64_0(a uint64) uint64 { return a - 0 } //go:noinline -func add_uint64_9223372036854775808_ssa(a uint64) uint64 { - return a + 9223372036854775808 -} +func sub_0_uint64(a uint64) uint64 { return 0 - a } //go:noinline -func add_9223372036854775808_uint64_ssa(a uint64) uint64 { - return 9223372036854775808 + a -} +func sub_uint64_1(a uint64) uint64 { return a - 1 } //go:noinline -func add_uint64_18446744073709551615_ssa(a uint64) uint64 { - return a + 18446744073709551615 -} +func sub_1_uint64(a uint64) uint64 { return 1 - a } //go:noinline -func add_18446744073709551615_uint64_ssa(a uint64) uint64 { - return 18446744073709551615 + a -} +func sub_uint64_4294967296(a uint64) uint64 { return a - 4294967296 } //go:noinline -func sub_uint64_0_ssa(a uint64) uint64 { - return a - 0 -} +func sub_4294967296_uint64(a uint64) uint64 { return 4294967296 - a } //go:noinline -func sub_0_uint64_ssa(a uint64) uint64 { - return 0 - a -} +func sub_uint64_9223372036854775808(a uint64) uint64 { return a - 9223372036854775808 } //go:noinline -func sub_uint64_1_ssa(a uint64) uint64 { - return a - 1 -} +func sub_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 - a } //go:noinline -func sub_1_uint64_ssa(a uint64) uint64 { - return 1 - a -} +func sub_uint64_18446744073709551615(a uint64) uint64 { return a - 18446744073709551615 } //go:noinline -func sub_uint64_4294967296_ssa(a uint64) uint64 { - return a - 4294967296 -} +func sub_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 - a } //go:noinline -func sub_4294967296_uint64_ssa(a uint64) uint64 { - return 4294967296 - a -} +func div_0_uint64(a uint64) uint64 { return 0 / a } //go:noinline -func sub_uint64_9223372036854775808_ssa(a uint64) uint64 { - return a - 9223372036854775808 -} +func div_uint64_1(a uint64) uint64 { return a / 1 } //go:noinline -func sub_9223372036854775808_uint64_ssa(a uint64) uint64 { - return 9223372036854775808 - a -} +func div_1_uint64(a uint64) uint64 { return 1 / a } //go:noinline -func sub_uint64_18446744073709551615_ssa(a uint64) uint64 { - return a - 18446744073709551615 -} +func div_uint64_4294967296(a uint64) uint64 { return a / 4294967296 } //go:noinline -func sub_18446744073709551615_uint64_ssa(a uint64) uint64 { - return 18446744073709551615 - a -} +func div_4294967296_uint64(a uint64) uint64 { return 4294967296 / a } //go:noinline -func div_0_uint64_ssa(a uint64) uint64 { - return 0 / a -} +func div_uint64_9223372036854775808(a uint64) uint64 { return a / 9223372036854775808 } //go:noinline -func div_uint64_1_ssa(a uint64) uint64 { - return a / 1 -} +func div_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 / a } //go:noinline -func div_1_uint64_ssa(a uint64) uint64 { - return 1 / a -} +func div_uint64_18446744073709551615(a uint64) uint64 { return a / 18446744073709551615 } //go:noinline -func div_uint64_4294967296_ssa(a uint64) uint64 { - return a / 4294967296 -} +func div_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 / a } //go:noinline -func div_4294967296_uint64_ssa(a uint64) uint64 { - return 4294967296 / a -} +func mul_uint64_0(a uint64) uint64 { return a * 0 } //go:noinline -func div_uint64_9223372036854775808_ssa(a uint64) uint64 { - return a / 9223372036854775808 -} +func mul_0_uint64(a uint64) uint64 { return 0 * a } //go:noinline -func div_9223372036854775808_uint64_ssa(a uint64) uint64 { - return 9223372036854775808 / a -} +func mul_uint64_1(a uint64) uint64 { return a * 1 } //go:noinline -func div_uint64_18446744073709551615_ssa(a uint64) uint64 { - return a / 18446744073709551615 -} +func mul_1_uint64(a uint64) uint64 { return 1 * a } //go:noinline -func div_18446744073709551615_uint64_ssa(a uint64) uint64 { - return 18446744073709551615 / a -} +func mul_uint64_4294967296(a uint64) uint64 { return a * 4294967296 } //go:noinline -func mul_uint64_0_ssa(a uint64) uint64 { - return a * 0 -} +func mul_4294967296_uint64(a uint64) uint64 { return 4294967296 * a } //go:noinline -func mul_0_uint64_ssa(a uint64) uint64 { - return 0 * a -} +func mul_uint64_9223372036854775808(a uint64) uint64 { return a * 9223372036854775808 } //go:noinline -func mul_uint64_1_ssa(a uint64) uint64 { - return a * 1 -} +func mul_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 * a } //go:noinline -func mul_1_uint64_ssa(a uint64) uint64 { - return 1 * a -} +func mul_uint64_18446744073709551615(a uint64) uint64 { return a * 18446744073709551615 } //go:noinline -func mul_uint64_4294967296_ssa(a uint64) uint64 { - return a * 4294967296 -} +func mul_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 * a } //go:noinline -func mul_4294967296_uint64_ssa(a uint64) uint64 { - return 4294967296 * a -} +func lsh_uint64_0(a uint64) uint64 { return a << 0 } //go:noinline -func mul_uint64_9223372036854775808_ssa(a uint64) uint64 { - return a * 9223372036854775808 -} +func lsh_0_uint64(a uint64) uint64 { return 0 << a } //go:noinline -func mul_9223372036854775808_uint64_ssa(a uint64) uint64 { - return 9223372036854775808 * a -} +func lsh_uint64_1(a uint64) uint64 { return a << 1 } + +//go:noinline +func lsh_1_uint64(a uint64) uint64 { return 1 << a } //go:noinline -func mul_uint64_18446744073709551615_ssa(a uint64) uint64 { - return a * 18446744073709551615 -} +func lsh_uint64_4294967296(a uint64) uint64 { return a << uint64(4294967296) } //go:noinline -func mul_18446744073709551615_uint64_ssa(a uint64) uint64 { - return 18446744073709551615 * a -} +func lsh_4294967296_uint64(a uint64) uint64 { return 4294967296 << a } //go:noinline -func lsh_uint64_0_ssa(a uint64) uint64 { - return a << 0 -} +func lsh_uint64_9223372036854775808(a uint64) uint64 { return a << uint64(9223372036854775808) } //go:noinline -func lsh_0_uint64_ssa(a uint64) uint64 { - return 0 << a -} +func lsh_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 << a } //go:noinline -func lsh_uint64_1_ssa(a uint64) uint64 { - return a << 1 -} +func lsh_uint64_18446744073709551615(a uint64) uint64 { return a << uint64(18446744073709551615) } //go:noinline -func lsh_1_uint64_ssa(a uint64) uint64 { - return 1 << a -} +func lsh_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 << a } //go:noinline -func lsh_uint64_4294967296_ssa(a uint64) uint64 { - return a << uint64(4294967296) -} +func rsh_uint64_0(a uint64) uint64 { return a >> 0 } //go:noinline -func lsh_4294967296_uint64_ssa(a uint64) uint64 { - return 4294967296 << a -} +func rsh_0_uint64(a uint64) uint64 { return 0 >> a } //go:noinline -func lsh_uint64_9223372036854775808_ssa(a uint64) uint64 { - return a << uint64(9223372036854775808) -} +func rsh_uint64_1(a uint64) uint64 { return a >> 1 } //go:noinline -func lsh_9223372036854775808_uint64_ssa(a uint64) uint64 { - return 9223372036854775808 << a -} +func rsh_1_uint64(a uint64) uint64 { return 1 >> a } //go:noinline -func lsh_uint64_18446744073709551615_ssa(a uint64) uint64 { - return a << uint64(18446744073709551615) -} +func rsh_uint64_4294967296(a uint64) uint64 { return a >> uint64(4294967296) } //go:noinline -func lsh_18446744073709551615_uint64_ssa(a uint64) uint64 { - return 18446744073709551615 << a -} +func rsh_4294967296_uint64(a uint64) uint64 { return 4294967296 >> a } //go:noinline -func rsh_uint64_0_ssa(a uint64) uint64 { - return a >> 0 -} +func rsh_uint64_9223372036854775808(a uint64) uint64 { return a >> uint64(9223372036854775808) } //go:noinline -func rsh_0_uint64_ssa(a uint64) uint64 { - return 0 >> a -} +func rsh_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 >> a } //go:noinline -func rsh_uint64_1_ssa(a uint64) uint64 { - return a >> 1 -} +func rsh_uint64_18446744073709551615(a uint64) uint64 { return a >> uint64(18446744073709551615) } //go:noinline -func rsh_1_uint64_ssa(a uint64) uint64 { - return 1 >> a -} +func rsh_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 >> a } //go:noinline -func rsh_uint64_4294967296_ssa(a uint64) uint64 { - return a >> uint64(4294967296) -} +func mod_0_uint64(a uint64) uint64 { return 0 % a } //go:noinline -func rsh_4294967296_uint64_ssa(a uint64) uint64 { - return 4294967296 >> a -} +func mod_uint64_1(a uint64) uint64 { return a % 1 } //go:noinline -func rsh_uint64_9223372036854775808_ssa(a uint64) uint64 { - return a >> uint64(9223372036854775808) -} +func mod_1_uint64(a uint64) uint64 { return 1 % a } //go:noinline -func rsh_9223372036854775808_uint64_ssa(a uint64) uint64 { - return 9223372036854775808 >> a -} +func mod_uint64_4294967296(a uint64) uint64 { return a % 4294967296 } //go:noinline -func rsh_uint64_18446744073709551615_ssa(a uint64) uint64 { - return a >> uint64(18446744073709551615) -} +func mod_4294967296_uint64(a uint64) uint64 { return 4294967296 % a } //go:noinline -func rsh_18446744073709551615_uint64_ssa(a uint64) uint64 { - return 18446744073709551615 >> a -} +func mod_uint64_9223372036854775808(a uint64) uint64 { return a % 9223372036854775808 } //go:noinline -func mod_0_uint64_ssa(a uint64) uint64 { - return 0 % a -} +func mod_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 % a } //go:noinline -func mod_uint64_1_ssa(a uint64) uint64 { - return a % 1 -} +func mod_uint64_18446744073709551615(a uint64) uint64 { return a % 18446744073709551615 } //go:noinline -func mod_1_uint64_ssa(a uint64) uint64 { - return 1 % a -} +func mod_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 % a } //go:noinline -func mod_uint64_4294967296_ssa(a uint64) uint64 { - return a % 4294967296 -} +func and_uint64_0(a uint64) uint64 { return a & 0 } //go:noinline -func mod_4294967296_uint64_ssa(a uint64) uint64 { - return 4294967296 % a -} +func and_0_uint64(a uint64) uint64 { return 0 & a } //go:noinline -func mod_uint64_9223372036854775808_ssa(a uint64) uint64 { - return a % 9223372036854775808 -} +func and_uint64_1(a uint64) uint64 { return a & 1 } //go:noinline -func mod_9223372036854775808_uint64_ssa(a uint64) uint64 { - return 9223372036854775808 % a -} +func and_1_uint64(a uint64) uint64 { return 1 & a } //go:noinline -func mod_uint64_18446744073709551615_ssa(a uint64) uint64 { - return a % 18446744073709551615 -} +func and_uint64_4294967296(a uint64) uint64 { return a & 4294967296 } //go:noinline -func mod_18446744073709551615_uint64_ssa(a uint64) uint64 { - return 18446744073709551615 % a -} +func and_4294967296_uint64(a uint64) uint64 { return 4294967296 & a } //go:noinline -func and_uint64_0_ssa(a uint64) uint64 { - return a & 0 -} +func and_uint64_9223372036854775808(a uint64) uint64 { return a & 9223372036854775808 } //go:noinline -func and_0_uint64_ssa(a uint64) uint64 { - return 0 & a -} +func and_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 & a } //go:noinline -func and_uint64_1_ssa(a uint64) uint64 { - return a & 1 -} +func and_uint64_18446744073709551615(a uint64) uint64 { return a & 18446744073709551615 } //go:noinline -func and_1_uint64_ssa(a uint64) uint64 { - return 1 & a -} +func and_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 & a } //go:noinline -func and_uint64_4294967296_ssa(a uint64) uint64 { - return a & 4294967296 -} +func or_uint64_0(a uint64) uint64 { return a | 0 } //go:noinline -func and_4294967296_uint64_ssa(a uint64) uint64 { - return 4294967296 & a -} +func or_0_uint64(a uint64) uint64 { return 0 | a } //go:noinline -func and_uint64_9223372036854775808_ssa(a uint64) uint64 { - return a & 9223372036854775808 -} +func or_uint64_1(a uint64) uint64 { return a | 1 } //go:noinline -func and_9223372036854775808_uint64_ssa(a uint64) uint64 { - return 9223372036854775808 & a -} +func or_1_uint64(a uint64) uint64 { return 1 | a } //go:noinline -func and_uint64_18446744073709551615_ssa(a uint64) uint64 { - return a & 18446744073709551615 -} +func or_uint64_4294967296(a uint64) uint64 { return a | 4294967296 } //go:noinline -func and_18446744073709551615_uint64_ssa(a uint64) uint64 { - return 18446744073709551615 & a -} +func or_4294967296_uint64(a uint64) uint64 { return 4294967296 | a } //go:noinline -func or_uint64_0_ssa(a uint64) uint64 { - return a | 0 -} +func or_uint64_9223372036854775808(a uint64) uint64 { return a | 9223372036854775808 } //go:noinline -func or_0_uint64_ssa(a uint64) uint64 { - return 0 | a -} +func or_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 | a } //go:noinline -func or_uint64_1_ssa(a uint64) uint64 { - return a | 1 -} +func or_uint64_18446744073709551615(a uint64) uint64 { return a | 18446744073709551615 } //go:noinline -func or_1_uint64_ssa(a uint64) uint64 { - return 1 | a -} +func or_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 | a } //go:noinline -func or_uint64_4294967296_ssa(a uint64) uint64 { - return a | 4294967296 -} +func xor_uint64_0(a uint64) uint64 { return a ^ 0 } //go:noinline -func or_4294967296_uint64_ssa(a uint64) uint64 { - return 4294967296 | a -} +func xor_0_uint64(a uint64) uint64 { return 0 ^ a } //go:noinline -func or_uint64_9223372036854775808_ssa(a uint64) uint64 { - return a | 9223372036854775808 -} +func xor_uint64_1(a uint64) uint64 { return a ^ 1 } //go:noinline -func or_9223372036854775808_uint64_ssa(a uint64) uint64 { - return 9223372036854775808 | a -} +func xor_1_uint64(a uint64) uint64 { return 1 ^ a } //go:noinline -func or_uint64_18446744073709551615_ssa(a uint64) uint64 { - return a | 18446744073709551615 -} +func xor_uint64_4294967296(a uint64) uint64 { return a ^ 4294967296 } //go:noinline -func or_18446744073709551615_uint64_ssa(a uint64) uint64 { - return 18446744073709551615 | a -} +func xor_4294967296_uint64(a uint64) uint64 { return 4294967296 ^ a } //go:noinline -func xor_uint64_0_ssa(a uint64) uint64 { - return a ^ 0 -} +func xor_uint64_9223372036854775808(a uint64) uint64 { return a ^ 9223372036854775808 } //go:noinline -func xor_0_uint64_ssa(a uint64) uint64 { - return 0 ^ a -} +func xor_9223372036854775808_uint64(a uint64) uint64 { return 9223372036854775808 ^ a } //go:noinline -func xor_uint64_1_ssa(a uint64) uint64 { - return a ^ 1 -} +func xor_uint64_18446744073709551615(a uint64) uint64 { return a ^ 18446744073709551615 } //go:noinline -func xor_1_uint64_ssa(a uint64) uint64 { - return 1 ^ a -} +func xor_18446744073709551615_uint64(a uint64) uint64 { return 18446744073709551615 ^ a } //go:noinline -func xor_uint64_4294967296_ssa(a uint64) uint64 { - return a ^ 4294967296 -} +func add_int64_Neg9223372036854775808(a int64) int64 { return a + -9223372036854775808 } //go:noinline -func xor_4294967296_uint64_ssa(a uint64) uint64 { - return 4294967296 ^ a -} +func add_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 + a } //go:noinline -func xor_uint64_9223372036854775808_ssa(a uint64) uint64 { - return a ^ 9223372036854775808 -} +func add_int64_Neg9223372036854775807(a int64) int64 { return a + -9223372036854775807 } //go:noinline -func xor_9223372036854775808_uint64_ssa(a uint64) uint64 { - return 9223372036854775808 ^ a -} +func add_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 + a } //go:noinline -func xor_uint64_18446744073709551615_ssa(a uint64) uint64 { - return a ^ 18446744073709551615 -} +func add_int64_Neg4294967296(a int64) int64 { return a + -4294967296 } //go:noinline -func xor_18446744073709551615_uint64_ssa(a uint64) uint64 { - return 18446744073709551615 ^ a -} +func add_Neg4294967296_int64(a int64) int64 { return -4294967296 + a } //go:noinline -func add_int64_Neg9223372036854775808_ssa(a int64) int64 { - return a + -9223372036854775808 -} +func add_int64_Neg1(a int64) int64 { return a + -1 } //go:noinline -func add_Neg9223372036854775808_int64_ssa(a int64) int64 { - return -9223372036854775808 + a -} +func add_Neg1_int64(a int64) int64 { return -1 + a } //go:noinline -func add_int64_Neg9223372036854775807_ssa(a int64) int64 { - return a + -9223372036854775807 -} +func add_int64_0(a int64) int64 { return a + 0 } //go:noinline -func add_Neg9223372036854775807_int64_ssa(a int64) int64 { - return -9223372036854775807 + a -} +func add_0_int64(a int64) int64 { return 0 + a } //go:noinline -func add_int64_Neg4294967296_ssa(a int64) int64 { - return a + -4294967296 -} +func add_int64_1(a int64) int64 { return a + 1 } //go:noinline -func add_Neg4294967296_int64_ssa(a int64) int64 { - return -4294967296 + a -} +func add_1_int64(a int64) int64 { return 1 + a } //go:noinline -func add_int64_Neg1_ssa(a int64) int64 { - return a + -1 -} +func add_int64_4294967296(a int64) int64 { return a + 4294967296 } //go:noinline -func add_Neg1_int64_ssa(a int64) int64 { - return -1 + a -} +func add_4294967296_int64(a int64) int64 { return 4294967296 + a } //go:noinline -func add_int64_0_ssa(a int64) int64 { - return a + 0 -} +func add_int64_9223372036854775806(a int64) int64 { return a + 9223372036854775806 } //go:noinline -func add_0_int64_ssa(a int64) int64 { - return 0 + a -} +func add_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 + a } //go:noinline -func add_int64_1_ssa(a int64) int64 { - return a + 1 -} +func add_int64_9223372036854775807(a int64) int64 { return a + 9223372036854775807 } //go:noinline -func add_1_int64_ssa(a int64) int64 { - return 1 + a -} +func add_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 + a } //go:noinline -func add_int64_4294967296_ssa(a int64) int64 { - return a + 4294967296 -} +func sub_int64_Neg9223372036854775808(a int64) int64 { return a - -9223372036854775808 } //go:noinline -func add_4294967296_int64_ssa(a int64) int64 { - return 4294967296 + a -} +func sub_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 - a } //go:noinline -func add_int64_9223372036854775806_ssa(a int64) int64 { - return a + 9223372036854775806 -} +func sub_int64_Neg9223372036854775807(a int64) int64 { return a - -9223372036854775807 } //go:noinline -func add_9223372036854775806_int64_ssa(a int64) int64 { - return 9223372036854775806 + a -} +func sub_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 - a } //go:noinline -func add_int64_9223372036854775807_ssa(a int64) int64 { - return a + 9223372036854775807 -} +func sub_int64_Neg4294967296(a int64) int64 { return a - -4294967296 } //go:noinline -func add_9223372036854775807_int64_ssa(a int64) int64 { - return 9223372036854775807 + a -} +func sub_Neg4294967296_int64(a int64) int64 { return -4294967296 - a } //go:noinline -func sub_int64_Neg9223372036854775808_ssa(a int64) int64 { - return a - -9223372036854775808 -} +func sub_int64_Neg1(a int64) int64 { return a - -1 } //go:noinline -func sub_Neg9223372036854775808_int64_ssa(a int64) int64 { - return -9223372036854775808 - a -} +func sub_Neg1_int64(a int64) int64 { return -1 - a } //go:noinline -func sub_int64_Neg9223372036854775807_ssa(a int64) int64 { - return a - -9223372036854775807 -} +func sub_int64_0(a int64) int64 { return a - 0 } //go:noinline -func sub_Neg9223372036854775807_int64_ssa(a int64) int64 { - return -9223372036854775807 - a -} +func sub_0_int64(a int64) int64 { return 0 - a } //go:noinline -func sub_int64_Neg4294967296_ssa(a int64) int64 { - return a - -4294967296 -} +func sub_int64_1(a int64) int64 { return a - 1 } //go:noinline -func sub_Neg4294967296_int64_ssa(a int64) int64 { - return -4294967296 - a -} +func sub_1_int64(a int64) int64 { return 1 - a } //go:noinline -func sub_int64_Neg1_ssa(a int64) int64 { - return a - -1 -} +func sub_int64_4294967296(a int64) int64 { return a - 4294967296 } //go:noinline -func sub_Neg1_int64_ssa(a int64) int64 { - return -1 - a -} +func sub_4294967296_int64(a int64) int64 { return 4294967296 - a } //go:noinline -func sub_int64_0_ssa(a int64) int64 { - return a - 0 -} +func sub_int64_9223372036854775806(a int64) int64 { return a - 9223372036854775806 } //go:noinline -func sub_0_int64_ssa(a int64) int64 { - return 0 - a -} +func sub_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 - a } //go:noinline -func sub_int64_1_ssa(a int64) int64 { - return a - 1 -} +func sub_int64_9223372036854775807(a int64) int64 { return a - 9223372036854775807 } //go:noinline -func sub_1_int64_ssa(a int64) int64 { - return 1 - a -} +func sub_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 - a } //go:noinline -func sub_int64_4294967296_ssa(a int64) int64 { - return a - 4294967296 -} +func div_int64_Neg9223372036854775808(a int64) int64 { return a / -9223372036854775808 } //go:noinline -func sub_4294967296_int64_ssa(a int64) int64 { - return 4294967296 - a -} +func div_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 / a } //go:noinline -func sub_int64_9223372036854775806_ssa(a int64) int64 { - return a - 9223372036854775806 -} +func div_int64_Neg9223372036854775807(a int64) int64 { return a / -9223372036854775807 } //go:noinline -func sub_9223372036854775806_int64_ssa(a int64) int64 { - return 9223372036854775806 - a -} +func div_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 / a } //go:noinline -func sub_int64_9223372036854775807_ssa(a int64) int64 { - return a - 9223372036854775807 -} +func div_int64_Neg4294967296(a int64) int64 { return a / -4294967296 } //go:noinline -func sub_9223372036854775807_int64_ssa(a int64) int64 { - return 9223372036854775807 - a -} +func div_Neg4294967296_int64(a int64) int64 { return -4294967296 / a } //go:noinline -func div_int64_Neg9223372036854775808_ssa(a int64) int64 { - return a / -9223372036854775808 -} +func div_int64_Neg1(a int64) int64 { return a / -1 } //go:noinline -func div_Neg9223372036854775808_int64_ssa(a int64) int64 { - return -9223372036854775808 / a -} +func div_Neg1_int64(a int64) int64 { return -1 / a } //go:noinline -func div_int64_Neg9223372036854775807_ssa(a int64) int64 { - return a / -9223372036854775807 -} +func div_0_int64(a int64) int64 { return 0 / a } //go:noinline -func div_Neg9223372036854775807_int64_ssa(a int64) int64 { - return -9223372036854775807 / a -} +func div_int64_1(a int64) int64 { return a / 1 } //go:noinline -func div_int64_Neg4294967296_ssa(a int64) int64 { - return a / -4294967296 -} +func div_1_int64(a int64) int64 { return 1 / a } //go:noinline -func div_Neg4294967296_int64_ssa(a int64) int64 { - return -4294967296 / a -} +func div_int64_4294967296(a int64) int64 { return a / 4294967296 } //go:noinline -func div_int64_Neg1_ssa(a int64) int64 { - return a / -1 -} +func div_4294967296_int64(a int64) int64 { return 4294967296 / a } //go:noinline -func div_Neg1_int64_ssa(a int64) int64 { - return -1 / a -} +func div_int64_9223372036854775806(a int64) int64 { return a / 9223372036854775806 } //go:noinline -func div_0_int64_ssa(a int64) int64 { - return 0 / a -} +func div_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 / a } //go:noinline -func div_int64_1_ssa(a int64) int64 { - return a / 1 -} +func div_int64_9223372036854775807(a int64) int64 { return a / 9223372036854775807 } //go:noinline -func div_1_int64_ssa(a int64) int64 { - return 1 / a -} +func div_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 / a } //go:noinline -func div_int64_4294967296_ssa(a int64) int64 { - return a / 4294967296 -} +func mul_int64_Neg9223372036854775808(a int64) int64 { return a * -9223372036854775808 } //go:noinline -func div_4294967296_int64_ssa(a int64) int64 { - return 4294967296 / a -} +func mul_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 * a } //go:noinline -func div_int64_9223372036854775806_ssa(a int64) int64 { - return a / 9223372036854775806 -} +func mul_int64_Neg9223372036854775807(a int64) int64 { return a * -9223372036854775807 } //go:noinline -func div_9223372036854775806_int64_ssa(a int64) int64 { - return 9223372036854775806 / a -} +func mul_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 * a } //go:noinline -func div_int64_9223372036854775807_ssa(a int64) int64 { - return a / 9223372036854775807 -} +func mul_int64_Neg4294967296(a int64) int64 { return a * -4294967296 } //go:noinline -func div_9223372036854775807_int64_ssa(a int64) int64 { - return 9223372036854775807 / a -} +func mul_Neg4294967296_int64(a int64) int64 { return -4294967296 * a } //go:noinline -func mul_int64_Neg9223372036854775808_ssa(a int64) int64 { - return a * -9223372036854775808 -} +func mul_int64_Neg1(a int64) int64 { return a * -1 } //go:noinline -func mul_Neg9223372036854775808_int64_ssa(a int64) int64 { - return -9223372036854775808 * a -} +func mul_Neg1_int64(a int64) int64 { return -1 * a } //go:noinline -func mul_int64_Neg9223372036854775807_ssa(a int64) int64 { - return a * -9223372036854775807 -} +func mul_int64_0(a int64) int64 { return a * 0 } //go:noinline -func mul_Neg9223372036854775807_int64_ssa(a int64) int64 { - return -9223372036854775807 * a -} +func mul_0_int64(a int64) int64 { return 0 * a } //go:noinline -func mul_int64_Neg4294967296_ssa(a int64) int64 { - return a * -4294967296 -} +func mul_int64_1(a int64) int64 { return a * 1 } //go:noinline -func mul_Neg4294967296_int64_ssa(a int64) int64 { - return -4294967296 * a -} +func mul_1_int64(a int64) int64 { return 1 * a } //go:noinline -func mul_int64_Neg1_ssa(a int64) int64 { - return a * -1 -} +func mul_int64_4294967296(a int64) int64 { return a * 4294967296 } //go:noinline -func mul_Neg1_int64_ssa(a int64) int64 { - return -1 * a -} +func mul_4294967296_int64(a int64) int64 { return 4294967296 * a } //go:noinline -func mul_int64_0_ssa(a int64) int64 { - return a * 0 -} +func mul_int64_9223372036854775806(a int64) int64 { return a * 9223372036854775806 } //go:noinline -func mul_0_int64_ssa(a int64) int64 { - return 0 * a -} +func mul_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 * a } //go:noinline -func mul_int64_1_ssa(a int64) int64 { - return a * 1 -} +func mul_int64_9223372036854775807(a int64) int64 { return a * 9223372036854775807 } //go:noinline -func mul_1_int64_ssa(a int64) int64 { - return 1 * a -} +func mul_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 * a } //go:noinline -func mul_int64_4294967296_ssa(a int64) int64 { - return a * 4294967296 -} +func mod_int64_Neg9223372036854775808(a int64) int64 { return a % -9223372036854775808 } //go:noinline -func mul_4294967296_int64_ssa(a int64) int64 { - return 4294967296 * a -} +func mod_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 % a } //go:noinline -func mul_int64_9223372036854775806_ssa(a int64) int64 { - return a * 9223372036854775806 -} +func mod_int64_Neg9223372036854775807(a int64) int64 { return a % -9223372036854775807 } //go:noinline -func mul_9223372036854775806_int64_ssa(a int64) int64 { - return 9223372036854775806 * a -} +func mod_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 % a } //go:noinline -func mul_int64_9223372036854775807_ssa(a int64) int64 { - return a * 9223372036854775807 -} +func mod_int64_Neg4294967296(a int64) int64 { return a % -4294967296 } //go:noinline -func mul_9223372036854775807_int64_ssa(a int64) int64 { - return 9223372036854775807 * a -} +func mod_Neg4294967296_int64(a int64) int64 { return -4294967296 % a } //go:noinline -func mod_int64_Neg9223372036854775808_ssa(a int64) int64 { - return a % -9223372036854775808 -} +func mod_int64_Neg1(a int64) int64 { return a % -1 } //go:noinline -func mod_Neg9223372036854775808_int64_ssa(a int64) int64 { - return -9223372036854775808 % a -} +func mod_Neg1_int64(a int64) int64 { return -1 % a } //go:noinline -func mod_int64_Neg9223372036854775807_ssa(a int64) int64 { - return a % -9223372036854775807 -} +func mod_0_int64(a int64) int64 { return 0 % a } //go:noinline -func mod_Neg9223372036854775807_int64_ssa(a int64) int64 { - return -9223372036854775807 % a -} +func mod_int64_1(a int64) int64 { return a % 1 } //go:noinline -func mod_int64_Neg4294967296_ssa(a int64) int64 { - return a % -4294967296 -} +func mod_1_int64(a int64) int64 { return 1 % a } //go:noinline -func mod_Neg4294967296_int64_ssa(a int64) int64 { - return -4294967296 % a -} +func mod_int64_4294967296(a int64) int64 { return a % 4294967296 } //go:noinline -func mod_int64_Neg1_ssa(a int64) int64 { - return a % -1 -} +func mod_4294967296_int64(a int64) int64 { return 4294967296 % a } //go:noinline -func mod_Neg1_int64_ssa(a int64) int64 { - return -1 % a -} +func mod_int64_9223372036854775806(a int64) int64 { return a % 9223372036854775806 } + +//go:noinline +func mod_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 % a } //go:noinline -func mod_0_int64_ssa(a int64) int64 { - return 0 % a -} +func mod_int64_9223372036854775807(a int64) int64 { return a % 9223372036854775807 } //go:noinline -func mod_int64_1_ssa(a int64) int64 { - return a % 1 -} +func mod_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 % a } //go:noinline -func mod_1_int64_ssa(a int64) int64 { - return 1 % a -} +func and_int64_Neg9223372036854775808(a int64) int64 { return a & -9223372036854775808 } //go:noinline -func mod_int64_4294967296_ssa(a int64) int64 { - return a % 4294967296 -} +func and_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 & a } //go:noinline -func mod_4294967296_int64_ssa(a int64) int64 { - return 4294967296 % a -} +func and_int64_Neg9223372036854775807(a int64) int64 { return a & -9223372036854775807 } //go:noinline -func mod_int64_9223372036854775806_ssa(a int64) int64 { - return a % 9223372036854775806 -} +func and_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 & a } //go:noinline -func mod_9223372036854775806_int64_ssa(a int64) int64 { - return 9223372036854775806 % a -} +func and_int64_Neg4294967296(a int64) int64 { return a & -4294967296 } //go:noinline -func mod_int64_9223372036854775807_ssa(a int64) int64 { - return a % 9223372036854775807 -} +func and_Neg4294967296_int64(a int64) int64 { return -4294967296 & a } //go:noinline -func mod_9223372036854775807_int64_ssa(a int64) int64 { - return 9223372036854775807 % a -} +func and_int64_Neg1(a int64) int64 { return a & -1 } //go:noinline -func and_int64_Neg9223372036854775808_ssa(a int64) int64 { - return a & -9223372036854775808 -} +func and_Neg1_int64(a int64) int64 { return -1 & a } //go:noinline -func and_Neg9223372036854775808_int64_ssa(a int64) int64 { - return -9223372036854775808 & a -} +func and_int64_0(a int64) int64 { return a & 0 } //go:noinline -func and_int64_Neg9223372036854775807_ssa(a int64) int64 { - return a & -9223372036854775807 -} +func and_0_int64(a int64) int64 { return 0 & a } //go:noinline -func and_Neg9223372036854775807_int64_ssa(a int64) int64 { - return -9223372036854775807 & a -} +func and_int64_1(a int64) int64 { return a & 1 } //go:noinline -func and_int64_Neg4294967296_ssa(a int64) int64 { - return a & -4294967296 -} +func and_1_int64(a int64) int64 { return 1 & a } //go:noinline -func and_Neg4294967296_int64_ssa(a int64) int64 { - return -4294967296 & a -} +func and_int64_4294967296(a int64) int64 { return a & 4294967296 } //go:noinline -func and_int64_Neg1_ssa(a int64) int64 { - return a & -1 -} +func and_4294967296_int64(a int64) int64 { return 4294967296 & a } //go:noinline -func and_Neg1_int64_ssa(a int64) int64 { - return -1 & a -} +func and_int64_9223372036854775806(a int64) int64 { return a & 9223372036854775806 } //go:noinline -func and_int64_0_ssa(a int64) int64 { - return a & 0 -} +func and_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 & a } //go:noinline -func and_0_int64_ssa(a int64) int64 { - return 0 & a -} +func and_int64_9223372036854775807(a int64) int64 { return a & 9223372036854775807 } //go:noinline -func and_int64_1_ssa(a int64) int64 { - return a & 1 -} +func and_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 & a } //go:noinline -func and_1_int64_ssa(a int64) int64 { - return 1 & a -} +func or_int64_Neg9223372036854775808(a int64) int64 { return a | -9223372036854775808 } //go:noinline -func and_int64_4294967296_ssa(a int64) int64 { - return a & 4294967296 -} +func or_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 | a } //go:noinline -func and_4294967296_int64_ssa(a int64) int64 { - return 4294967296 & a -} +func or_int64_Neg9223372036854775807(a int64) int64 { return a | -9223372036854775807 } //go:noinline -func and_int64_9223372036854775806_ssa(a int64) int64 { - return a & 9223372036854775806 -} +func or_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 | a } //go:noinline -func and_9223372036854775806_int64_ssa(a int64) int64 { - return 9223372036854775806 & a -} +func or_int64_Neg4294967296(a int64) int64 { return a | -4294967296 } //go:noinline -func and_int64_9223372036854775807_ssa(a int64) int64 { - return a & 9223372036854775807 -} +func or_Neg4294967296_int64(a int64) int64 { return -4294967296 | a } //go:noinline -func and_9223372036854775807_int64_ssa(a int64) int64 { - return 9223372036854775807 & a -} +func or_int64_Neg1(a int64) int64 { return a | -1 } //go:noinline -func or_int64_Neg9223372036854775808_ssa(a int64) int64 { - return a | -9223372036854775808 -} +func or_Neg1_int64(a int64) int64 { return -1 | a } //go:noinline -func or_Neg9223372036854775808_int64_ssa(a int64) int64 { - return -9223372036854775808 | a -} +func or_int64_0(a int64) int64 { return a | 0 } //go:noinline -func or_int64_Neg9223372036854775807_ssa(a int64) int64 { - return a | -9223372036854775807 -} +func or_0_int64(a int64) int64 { return 0 | a } //go:noinline -func or_Neg9223372036854775807_int64_ssa(a int64) int64 { - return -9223372036854775807 | a -} +func or_int64_1(a int64) int64 { return a | 1 } //go:noinline -func or_int64_Neg4294967296_ssa(a int64) int64 { - return a | -4294967296 -} +func or_1_int64(a int64) int64 { return 1 | a } //go:noinline -func or_Neg4294967296_int64_ssa(a int64) int64 { - return -4294967296 | a -} +func or_int64_4294967296(a int64) int64 { return a | 4294967296 } //go:noinline -func or_int64_Neg1_ssa(a int64) int64 { - return a | -1 -} +func or_4294967296_int64(a int64) int64 { return 4294967296 | a } //go:noinline -func or_Neg1_int64_ssa(a int64) int64 { - return -1 | a -} +func or_int64_9223372036854775806(a int64) int64 { return a | 9223372036854775806 } //go:noinline -func or_int64_0_ssa(a int64) int64 { - return a | 0 -} +func or_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 | a } //go:noinline -func or_0_int64_ssa(a int64) int64 { - return 0 | a -} +func or_int64_9223372036854775807(a int64) int64 { return a | 9223372036854775807 } //go:noinline -func or_int64_1_ssa(a int64) int64 { - return a | 1 -} +func or_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 | a } //go:noinline -func or_1_int64_ssa(a int64) int64 { - return 1 | a -} +func xor_int64_Neg9223372036854775808(a int64) int64 { return a ^ -9223372036854775808 } //go:noinline -func or_int64_4294967296_ssa(a int64) int64 { - return a | 4294967296 -} +func xor_Neg9223372036854775808_int64(a int64) int64 { return -9223372036854775808 ^ a } //go:noinline -func or_4294967296_int64_ssa(a int64) int64 { - return 4294967296 | a -} +func xor_int64_Neg9223372036854775807(a int64) int64 { return a ^ -9223372036854775807 } //go:noinline -func or_int64_9223372036854775806_ssa(a int64) int64 { - return a | 9223372036854775806 -} +func xor_Neg9223372036854775807_int64(a int64) int64 { return -9223372036854775807 ^ a } //go:noinline -func or_9223372036854775806_int64_ssa(a int64) int64 { - return 9223372036854775806 | a -} +func xor_int64_Neg4294967296(a int64) int64 { return a ^ -4294967296 } //go:noinline -func or_int64_9223372036854775807_ssa(a int64) int64 { - return a | 9223372036854775807 -} +func xor_Neg4294967296_int64(a int64) int64 { return -4294967296 ^ a } //go:noinline -func or_9223372036854775807_int64_ssa(a int64) int64 { - return 9223372036854775807 | a -} +func xor_int64_Neg1(a int64) int64 { return a ^ -1 } //go:noinline -func xor_int64_Neg9223372036854775808_ssa(a int64) int64 { - return a ^ -9223372036854775808 -} +func xor_Neg1_int64(a int64) int64 { return -1 ^ a } //go:noinline -func xor_Neg9223372036854775808_int64_ssa(a int64) int64 { - return -9223372036854775808 ^ a -} +func xor_int64_0(a int64) int64 { return a ^ 0 } //go:noinline -func xor_int64_Neg9223372036854775807_ssa(a int64) int64 { - return a ^ -9223372036854775807 -} +func xor_0_int64(a int64) int64 { return 0 ^ a } //go:noinline -func xor_Neg9223372036854775807_int64_ssa(a int64) int64 { - return -9223372036854775807 ^ a -} +func xor_int64_1(a int64) int64 { return a ^ 1 } //go:noinline -func xor_int64_Neg4294967296_ssa(a int64) int64 { - return a ^ -4294967296 -} +func xor_1_int64(a int64) int64 { return 1 ^ a } //go:noinline -func xor_Neg4294967296_int64_ssa(a int64) int64 { - return -4294967296 ^ a -} +func xor_int64_4294967296(a int64) int64 { return a ^ 4294967296 } //go:noinline -func xor_int64_Neg1_ssa(a int64) int64 { - return a ^ -1 -} +func xor_4294967296_int64(a int64) int64 { return 4294967296 ^ a } //go:noinline -func xor_Neg1_int64_ssa(a int64) int64 { - return -1 ^ a -} +func xor_int64_9223372036854775806(a int64) int64 { return a ^ 9223372036854775806 } //go:noinline -func xor_int64_0_ssa(a int64) int64 { - return a ^ 0 -} +func xor_9223372036854775806_int64(a int64) int64 { return 9223372036854775806 ^ a } //go:noinline -func xor_0_int64_ssa(a int64) int64 { - return 0 ^ a -} +func xor_int64_9223372036854775807(a int64) int64 { return a ^ 9223372036854775807 } //go:noinline -func xor_int64_1_ssa(a int64) int64 { - return a ^ 1 -} +func xor_9223372036854775807_int64(a int64) int64 { return 9223372036854775807 ^ a } //go:noinline -func xor_1_int64_ssa(a int64) int64 { - return 1 ^ a -} +func add_uint32_0(a uint32) uint32 { return a + 0 } //go:noinline -func xor_int64_4294967296_ssa(a int64) int64 { - return a ^ 4294967296 -} +func add_0_uint32(a uint32) uint32 { return 0 + a } //go:noinline -func xor_4294967296_int64_ssa(a int64) int64 { - return 4294967296 ^ a -} +func add_uint32_1(a uint32) uint32 { return a + 1 } //go:noinline -func xor_int64_9223372036854775806_ssa(a int64) int64 { - return a ^ 9223372036854775806 -} +func add_1_uint32(a uint32) uint32 { return 1 + a } //go:noinline -func xor_9223372036854775806_int64_ssa(a int64) int64 { - return 9223372036854775806 ^ a -} +func add_uint32_4294967295(a uint32) uint32 { return a + 4294967295 } //go:noinline -func xor_int64_9223372036854775807_ssa(a int64) int64 { - return a ^ 9223372036854775807 -} +func add_4294967295_uint32(a uint32) uint32 { return 4294967295 + a } //go:noinline -func xor_9223372036854775807_int64_ssa(a int64) int64 { - return 9223372036854775807 ^ a -} +func sub_uint32_0(a uint32) uint32 { return a - 0 } //go:noinline -func add_uint32_0_ssa(a uint32) uint32 { - return a + 0 -} +func sub_0_uint32(a uint32) uint32 { return 0 - a } //go:noinline -func add_0_uint32_ssa(a uint32) uint32 { - return 0 + a -} +func sub_uint32_1(a uint32) uint32 { return a - 1 } //go:noinline -func add_uint32_1_ssa(a uint32) uint32 { - return a + 1 -} +func sub_1_uint32(a uint32) uint32 { return 1 - a } //go:noinline -func add_1_uint32_ssa(a uint32) uint32 { - return 1 + a -} +func sub_uint32_4294967295(a uint32) uint32 { return a - 4294967295 } //go:noinline -func add_uint32_4294967295_ssa(a uint32) uint32 { - return a + 4294967295 -} +func sub_4294967295_uint32(a uint32) uint32 { return 4294967295 - a } //go:noinline -func add_4294967295_uint32_ssa(a uint32) uint32 { - return 4294967295 + a -} +func div_0_uint32(a uint32) uint32 { return 0 / a } //go:noinline -func sub_uint32_0_ssa(a uint32) uint32 { - return a - 0 -} +func div_uint32_1(a uint32) uint32 { return a / 1 } //go:noinline -func sub_0_uint32_ssa(a uint32) uint32 { - return 0 - a -} +func div_1_uint32(a uint32) uint32 { return 1 / a } //go:noinline -func sub_uint32_1_ssa(a uint32) uint32 { - return a - 1 -} +func div_uint32_4294967295(a uint32) uint32 { return a / 4294967295 } //go:noinline -func sub_1_uint32_ssa(a uint32) uint32 { - return 1 - a -} +func div_4294967295_uint32(a uint32) uint32 { return 4294967295 / a } //go:noinline -func sub_uint32_4294967295_ssa(a uint32) uint32 { - return a - 4294967295 -} +func mul_uint32_0(a uint32) uint32 { return a * 0 } //go:noinline -func sub_4294967295_uint32_ssa(a uint32) uint32 { - return 4294967295 - a -} +func mul_0_uint32(a uint32) uint32 { return 0 * a } //go:noinline -func div_0_uint32_ssa(a uint32) uint32 { - return 0 / a -} +func mul_uint32_1(a uint32) uint32 { return a * 1 } //go:noinline -func div_uint32_1_ssa(a uint32) uint32 { - return a / 1 -} +func mul_1_uint32(a uint32) uint32 { return 1 * a } //go:noinline -func div_1_uint32_ssa(a uint32) uint32 { - return 1 / a -} +func mul_uint32_4294967295(a uint32) uint32 { return a * 4294967295 } //go:noinline -func div_uint32_4294967295_ssa(a uint32) uint32 { - return a / 4294967295 -} +func mul_4294967295_uint32(a uint32) uint32 { return 4294967295 * a } //go:noinline -func div_4294967295_uint32_ssa(a uint32) uint32 { - return 4294967295 / a -} +func lsh_uint32_0(a uint32) uint32 { return a << 0 } //go:noinline -func mul_uint32_0_ssa(a uint32) uint32 { - return a * 0 -} +func lsh_0_uint32(a uint32) uint32 { return 0 << a } //go:noinline -func mul_0_uint32_ssa(a uint32) uint32 { - return 0 * a -} +func lsh_uint32_1(a uint32) uint32 { return a << 1 } //go:noinline -func mul_uint32_1_ssa(a uint32) uint32 { - return a * 1 -} +func lsh_1_uint32(a uint32) uint32 { return 1 << a } //go:noinline -func mul_1_uint32_ssa(a uint32) uint32 { - return 1 * a -} +func lsh_uint32_4294967295(a uint32) uint32 { return a << 4294967295 } //go:noinline -func mul_uint32_4294967295_ssa(a uint32) uint32 { - return a * 4294967295 -} +func lsh_4294967295_uint32(a uint32) uint32 { return 4294967295 << a } //go:noinline -func mul_4294967295_uint32_ssa(a uint32) uint32 { - return 4294967295 * a -} +func rsh_uint32_0(a uint32) uint32 { return a >> 0 } //go:noinline -func lsh_uint32_0_ssa(a uint32) uint32 { - return a << 0 -} +func rsh_0_uint32(a uint32) uint32 { return 0 >> a } //go:noinline -func lsh_0_uint32_ssa(a uint32) uint32 { - return 0 << a -} +func rsh_uint32_1(a uint32) uint32 { return a >> 1 } //go:noinline -func lsh_uint32_1_ssa(a uint32) uint32 { - return a << 1 -} +func rsh_1_uint32(a uint32) uint32 { return 1 >> a } //go:noinline -func lsh_1_uint32_ssa(a uint32) uint32 { - return 1 << a -} +func rsh_uint32_4294967295(a uint32) uint32 { return a >> 4294967295 } //go:noinline -func lsh_uint32_4294967295_ssa(a uint32) uint32 { - return a << 4294967295 -} +func rsh_4294967295_uint32(a uint32) uint32 { return 4294967295 >> a } //go:noinline -func lsh_4294967295_uint32_ssa(a uint32) uint32 { - return 4294967295 << a -} +func mod_0_uint32(a uint32) uint32 { return 0 % a } //go:noinline -func rsh_uint32_0_ssa(a uint32) uint32 { - return a >> 0 -} +func mod_uint32_1(a uint32) uint32 { return a % 1 } //go:noinline -func rsh_0_uint32_ssa(a uint32) uint32 { - return 0 >> a -} +func mod_1_uint32(a uint32) uint32 { return 1 % a } //go:noinline -func rsh_uint32_1_ssa(a uint32) uint32 { - return a >> 1 -} +func mod_uint32_4294967295(a uint32) uint32 { return a % 4294967295 } //go:noinline -func rsh_1_uint32_ssa(a uint32) uint32 { - return 1 >> a -} +func mod_4294967295_uint32(a uint32) uint32 { return 4294967295 % a } //go:noinline -func rsh_uint32_4294967295_ssa(a uint32) uint32 { - return a >> 4294967295 -} +func and_uint32_0(a uint32) uint32 { return a & 0 } //go:noinline -func rsh_4294967295_uint32_ssa(a uint32) uint32 { - return 4294967295 >> a -} +func and_0_uint32(a uint32) uint32 { return 0 & a } //go:noinline -func mod_0_uint32_ssa(a uint32) uint32 { - return 0 % a -} +func and_uint32_1(a uint32) uint32 { return a & 1 } //go:noinline -func mod_uint32_1_ssa(a uint32) uint32 { - return a % 1 -} +func and_1_uint32(a uint32) uint32 { return 1 & a } //go:noinline -func mod_1_uint32_ssa(a uint32) uint32 { - return 1 % a -} +func and_uint32_4294967295(a uint32) uint32 { return a & 4294967295 } //go:noinline -func mod_uint32_4294967295_ssa(a uint32) uint32 { - return a % 4294967295 -} +func and_4294967295_uint32(a uint32) uint32 { return 4294967295 & a } //go:noinline -func mod_4294967295_uint32_ssa(a uint32) uint32 { - return 4294967295 % a -} +func or_uint32_0(a uint32) uint32 { return a | 0 } //go:noinline -func and_uint32_0_ssa(a uint32) uint32 { - return a & 0 -} +func or_0_uint32(a uint32) uint32 { return 0 | a } //go:noinline -func and_0_uint32_ssa(a uint32) uint32 { - return 0 & a -} +func or_uint32_1(a uint32) uint32 { return a | 1 } //go:noinline -func and_uint32_1_ssa(a uint32) uint32 { - return a & 1 -} +func or_1_uint32(a uint32) uint32 { return 1 | a } //go:noinline -func and_1_uint32_ssa(a uint32) uint32 { - return 1 & a -} +func or_uint32_4294967295(a uint32) uint32 { return a | 4294967295 } //go:noinline -func and_uint32_4294967295_ssa(a uint32) uint32 { - return a & 4294967295 -} +func or_4294967295_uint32(a uint32) uint32 { return 4294967295 | a } //go:noinline -func and_4294967295_uint32_ssa(a uint32) uint32 { - return 4294967295 & a -} +func xor_uint32_0(a uint32) uint32 { return a ^ 0 } //go:noinline -func or_uint32_0_ssa(a uint32) uint32 { - return a | 0 -} +func xor_0_uint32(a uint32) uint32 { return 0 ^ a } //go:noinline -func or_0_uint32_ssa(a uint32) uint32 { - return 0 | a -} +func xor_uint32_1(a uint32) uint32 { return a ^ 1 } //go:noinline -func or_uint32_1_ssa(a uint32) uint32 { - return a | 1 -} +func xor_1_uint32(a uint32) uint32 { return 1 ^ a } //go:noinline -func or_1_uint32_ssa(a uint32) uint32 { - return 1 | a -} +func xor_uint32_4294967295(a uint32) uint32 { return a ^ 4294967295 } //go:noinline -func or_uint32_4294967295_ssa(a uint32) uint32 { - return a | 4294967295 -} +func xor_4294967295_uint32(a uint32) uint32 { return 4294967295 ^ a } //go:noinline -func or_4294967295_uint32_ssa(a uint32) uint32 { - return 4294967295 | a -} +func add_int32_Neg2147483648(a int32) int32 { return a + -2147483648 } //go:noinline -func xor_uint32_0_ssa(a uint32) uint32 { - return a ^ 0 -} +func add_Neg2147483648_int32(a int32) int32 { return -2147483648 + a } //go:noinline -func xor_0_uint32_ssa(a uint32) uint32 { - return 0 ^ a -} +func add_int32_Neg2147483647(a int32) int32 { return a + -2147483647 } //go:noinline -func xor_uint32_1_ssa(a uint32) uint32 { - return a ^ 1 -} +func add_Neg2147483647_int32(a int32) int32 { return -2147483647 + a } //go:noinline -func xor_1_uint32_ssa(a uint32) uint32 { - return 1 ^ a -} +func add_int32_Neg1(a int32) int32 { return a + -1 } //go:noinline -func xor_uint32_4294967295_ssa(a uint32) uint32 { - return a ^ 4294967295 -} +func add_Neg1_int32(a int32) int32 { return -1 + a } //go:noinline -func xor_4294967295_uint32_ssa(a uint32) uint32 { - return 4294967295 ^ a -} +func add_int32_0(a int32) int32 { return a + 0 } //go:noinline -func add_int32_Neg2147483648_ssa(a int32) int32 { - return a + -2147483648 -} +func add_0_int32(a int32) int32 { return 0 + a } //go:noinline -func add_Neg2147483648_int32_ssa(a int32) int32 { - return -2147483648 + a -} +func add_int32_1(a int32) int32 { return a + 1 } //go:noinline -func add_int32_Neg2147483647_ssa(a int32) int32 { - return a + -2147483647 -} +func add_1_int32(a int32) int32 { return 1 + a } //go:noinline -func add_Neg2147483647_int32_ssa(a int32) int32 { - return -2147483647 + a -} +func add_int32_2147483647(a int32) int32 { return a + 2147483647 } //go:noinline -func add_int32_Neg1_ssa(a int32) int32 { - return a + -1 -} +func add_2147483647_int32(a int32) int32 { return 2147483647 + a } //go:noinline -func add_Neg1_int32_ssa(a int32) int32 { - return -1 + a -} +func sub_int32_Neg2147483648(a int32) int32 { return a - -2147483648 } //go:noinline -func add_int32_0_ssa(a int32) int32 { - return a + 0 -} +func sub_Neg2147483648_int32(a int32) int32 { return -2147483648 - a } //go:noinline -func add_0_int32_ssa(a int32) int32 { - return 0 + a -} +func sub_int32_Neg2147483647(a int32) int32 { return a - -2147483647 } //go:noinline -func add_int32_1_ssa(a int32) int32 { - return a + 1 -} +func sub_Neg2147483647_int32(a int32) int32 { return -2147483647 - a } //go:noinline -func add_1_int32_ssa(a int32) int32 { - return 1 + a -} +func sub_int32_Neg1(a int32) int32 { return a - -1 } //go:noinline -func add_int32_2147483647_ssa(a int32) int32 { - return a + 2147483647 -} +func sub_Neg1_int32(a int32) int32 { return -1 - a } //go:noinline -func add_2147483647_int32_ssa(a int32) int32 { - return 2147483647 + a -} +func sub_int32_0(a int32) int32 { return a - 0 } //go:noinline -func sub_int32_Neg2147483648_ssa(a int32) int32 { - return a - -2147483648 -} +func sub_0_int32(a int32) int32 { return 0 - a } //go:noinline -func sub_Neg2147483648_int32_ssa(a int32) int32 { - return -2147483648 - a -} +func sub_int32_1(a int32) int32 { return a - 1 } //go:noinline -func sub_int32_Neg2147483647_ssa(a int32) int32 { - return a - -2147483647 -} +func sub_1_int32(a int32) int32 { return 1 - a } //go:noinline -func sub_Neg2147483647_int32_ssa(a int32) int32 { - return -2147483647 - a -} +func sub_int32_2147483647(a int32) int32 { return a - 2147483647 } //go:noinline -func sub_int32_Neg1_ssa(a int32) int32 { - return a - -1 -} +func sub_2147483647_int32(a int32) int32 { return 2147483647 - a } //go:noinline -func sub_Neg1_int32_ssa(a int32) int32 { - return -1 - a -} +func div_int32_Neg2147483648(a int32) int32 { return a / -2147483648 } //go:noinline -func sub_int32_0_ssa(a int32) int32 { - return a - 0 -} +func div_Neg2147483648_int32(a int32) int32 { return -2147483648 / a } //go:noinline -func sub_0_int32_ssa(a int32) int32 { - return 0 - a -} +func div_int32_Neg2147483647(a int32) int32 { return a / -2147483647 } //go:noinline -func sub_int32_1_ssa(a int32) int32 { - return a - 1 -} +func div_Neg2147483647_int32(a int32) int32 { return -2147483647 / a } //go:noinline -func sub_1_int32_ssa(a int32) int32 { - return 1 - a -} +func div_int32_Neg1(a int32) int32 { return a / -1 } //go:noinline -func sub_int32_2147483647_ssa(a int32) int32 { - return a - 2147483647 -} +func div_Neg1_int32(a int32) int32 { return -1 / a } //go:noinline -func sub_2147483647_int32_ssa(a int32) int32 { - return 2147483647 - a -} +func div_0_int32(a int32) int32 { return 0 / a } //go:noinline -func div_int32_Neg2147483648_ssa(a int32) int32 { - return a / -2147483648 -} +func div_int32_1(a int32) int32 { return a / 1 } //go:noinline -func div_Neg2147483648_int32_ssa(a int32) int32 { - return -2147483648 / a -} +func div_1_int32(a int32) int32 { return 1 / a } //go:noinline -func div_int32_Neg2147483647_ssa(a int32) int32 { - return a / -2147483647 -} +func div_int32_2147483647(a int32) int32 { return a / 2147483647 } //go:noinline -func div_Neg2147483647_int32_ssa(a int32) int32 { - return -2147483647 / a -} +func div_2147483647_int32(a int32) int32 { return 2147483647 / a } //go:noinline -func div_int32_Neg1_ssa(a int32) int32 { - return a / -1 -} +func mul_int32_Neg2147483648(a int32) int32 { return a * -2147483648 } //go:noinline -func div_Neg1_int32_ssa(a int32) int32 { - return -1 / a -} +func mul_Neg2147483648_int32(a int32) int32 { return -2147483648 * a } //go:noinline -func div_0_int32_ssa(a int32) int32 { - return 0 / a -} +func mul_int32_Neg2147483647(a int32) int32 { return a * -2147483647 } //go:noinline -func div_int32_1_ssa(a int32) int32 { - return a / 1 -} +func mul_Neg2147483647_int32(a int32) int32 { return -2147483647 * a } //go:noinline -func div_1_int32_ssa(a int32) int32 { - return 1 / a -} +func mul_int32_Neg1(a int32) int32 { return a * -1 } //go:noinline -func div_int32_2147483647_ssa(a int32) int32 { - return a / 2147483647 -} +func mul_Neg1_int32(a int32) int32 { return -1 * a } //go:noinline -func div_2147483647_int32_ssa(a int32) int32 { - return 2147483647 / a -} +func mul_int32_0(a int32) int32 { return a * 0 } //go:noinline -func mul_int32_Neg2147483648_ssa(a int32) int32 { - return a * -2147483648 -} +func mul_0_int32(a int32) int32 { return 0 * a } //go:noinline -func mul_Neg2147483648_int32_ssa(a int32) int32 { - return -2147483648 * a -} +func mul_int32_1(a int32) int32 { return a * 1 } //go:noinline -func mul_int32_Neg2147483647_ssa(a int32) int32 { - return a * -2147483647 -} +func mul_1_int32(a int32) int32 { return 1 * a } //go:noinline -func mul_Neg2147483647_int32_ssa(a int32) int32 { - return -2147483647 * a -} +func mul_int32_2147483647(a int32) int32 { return a * 2147483647 } //go:noinline -func mul_int32_Neg1_ssa(a int32) int32 { - return a * -1 -} +func mul_2147483647_int32(a int32) int32 { return 2147483647 * a } //go:noinline -func mul_Neg1_int32_ssa(a int32) int32 { - return -1 * a -} +func mod_int32_Neg2147483648(a int32) int32 { return a % -2147483648 } //go:noinline -func mul_int32_0_ssa(a int32) int32 { - return a * 0 -} +func mod_Neg2147483648_int32(a int32) int32 { return -2147483648 % a } //go:noinline -func mul_0_int32_ssa(a int32) int32 { - return 0 * a -} +func mod_int32_Neg2147483647(a int32) int32 { return a % -2147483647 } //go:noinline -func mul_int32_1_ssa(a int32) int32 { - return a * 1 -} +func mod_Neg2147483647_int32(a int32) int32 { return -2147483647 % a } //go:noinline -func mul_1_int32_ssa(a int32) int32 { - return 1 * a -} +func mod_int32_Neg1(a int32) int32 { return a % -1 } //go:noinline -func mul_int32_2147483647_ssa(a int32) int32 { - return a * 2147483647 -} +func mod_Neg1_int32(a int32) int32 { return -1 % a } //go:noinline -func mul_2147483647_int32_ssa(a int32) int32 { - return 2147483647 * a -} +func mod_0_int32(a int32) int32 { return 0 % a } //go:noinline -func mod_int32_Neg2147483648_ssa(a int32) int32 { - return a % -2147483648 -} +func mod_int32_1(a int32) int32 { return a % 1 } //go:noinline -func mod_Neg2147483648_int32_ssa(a int32) int32 { - return -2147483648 % a -} +func mod_1_int32(a int32) int32 { return 1 % a } //go:noinline -func mod_int32_Neg2147483647_ssa(a int32) int32 { - return a % -2147483647 -} +func mod_int32_2147483647(a int32) int32 { return a % 2147483647 } //go:noinline -func mod_Neg2147483647_int32_ssa(a int32) int32 { - return -2147483647 % a -} +func mod_2147483647_int32(a int32) int32 { return 2147483647 % a } //go:noinline -func mod_int32_Neg1_ssa(a int32) int32 { - return a % -1 -} +func and_int32_Neg2147483648(a int32) int32 { return a & -2147483648 } //go:noinline -func mod_Neg1_int32_ssa(a int32) int32 { - return -1 % a -} +func and_Neg2147483648_int32(a int32) int32 { return -2147483648 & a } //go:noinline -func mod_0_int32_ssa(a int32) int32 { - return 0 % a -} +func and_int32_Neg2147483647(a int32) int32 { return a & -2147483647 } //go:noinline -func mod_int32_1_ssa(a int32) int32 { - return a % 1 -} +func and_Neg2147483647_int32(a int32) int32 { return -2147483647 & a } //go:noinline -func mod_1_int32_ssa(a int32) int32 { - return 1 % a -} +func and_int32_Neg1(a int32) int32 { return a & -1 } //go:noinline -func mod_int32_2147483647_ssa(a int32) int32 { - return a % 2147483647 -} +func and_Neg1_int32(a int32) int32 { return -1 & a } //go:noinline -func mod_2147483647_int32_ssa(a int32) int32 { - return 2147483647 % a -} +func and_int32_0(a int32) int32 { return a & 0 } //go:noinline -func and_int32_Neg2147483648_ssa(a int32) int32 { - return a & -2147483648 -} +func and_0_int32(a int32) int32 { return 0 & a } //go:noinline -func and_Neg2147483648_int32_ssa(a int32) int32 { - return -2147483648 & a -} +func and_int32_1(a int32) int32 { return a & 1 } //go:noinline -func and_int32_Neg2147483647_ssa(a int32) int32 { - return a & -2147483647 -} +func and_1_int32(a int32) int32 { return 1 & a } //go:noinline -func and_Neg2147483647_int32_ssa(a int32) int32 { - return -2147483647 & a -} +func and_int32_2147483647(a int32) int32 { return a & 2147483647 } //go:noinline -func and_int32_Neg1_ssa(a int32) int32 { - return a & -1 -} +func and_2147483647_int32(a int32) int32 { return 2147483647 & a } //go:noinline -func and_Neg1_int32_ssa(a int32) int32 { - return -1 & a -} +func or_int32_Neg2147483648(a int32) int32 { return a | -2147483648 } //go:noinline -func and_int32_0_ssa(a int32) int32 { - return a & 0 -} +func or_Neg2147483648_int32(a int32) int32 { return -2147483648 | a } //go:noinline -func and_0_int32_ssa(a int32) int32 { - return 0 & a -} +func or_int32_Neg2147483647(a int32) int32 { return a | -2147483647 } //go:noinline -func and_int32_1_ssa(a int32) int32 { - return a & 1 -} +func or_Neg2147483647_int32(a int32) int32 { return -2147483647 | a } //go:noinline -func and_1_int32_ssa(a int32) int32 { - return 1 & a -} +func or_int32_Neg1(a int32) int32 { return a | -1 } //go:noinline -func and_int32_2147483647_ssa(a int32) int32 { - return a & 2147483647 -} +func or_Neg1_int32(a int32) int32 { return -1 | a } //go:noinline -func and_2147483647_int32_ssa(a int32) int32 { - return 2147483647 & a -} +func or_int32_0(a int32) int32 { return a | 0 } //go:noinline -func or_int32_Neg2147483648_ssa(a int32) int32 { - return a | -2147483648 -} +func or_0_int32(a int32) int32 { return 0 | a } //go:noinline -func or_Neg2147483648_int32_ssa(a int32) int32 { - return -2147483648 | a -} +func or_int32_1(a int32) int32 { return a | 1 } //go:noinline -func or_int32_Neg2147483647_ssa(a int32) int32 { - return a | -2147483647 -} +func or_1_int32(a int32) int32 { return 1 | a } //go:noinline -func or_Neg2147483647_int32_ssa(a int32) int32 { - return -2147483647 | a -} +func or_int32_2147483647(a int32) int32 { return a | 2147483647 } //go:noinline -func or_int32_Neg1_ssa(a int32) int32 { - return a | -1 -} +func or_2147483647_int32(a int32) int32 { return 2147483647 | a } //go:noinline -func or_Neg1_int32_ssa(a int32) int32 { - return -1 | a -} +func xor_int32_Neg2147483648(a int32) int32 { return a ^ -2147483648 } //go:noinline -func or_int32_0_ssa(a int32) int32 { - return a | 0 -} +func xor_Neg2147483648_int32(a int32) int32 { return -2147483648 ^ a } //go:noinline -func or_0_int32_ssa(a int32) int32 { - return 0 | a -} +func xor_int32_Neg2147483647(a int32) int32 { return a ^ -2147483647 } //go:noinline -func or_int32_1_ssa(a int32) int32 { - return a | 1 -} +func xor_Neg2147483647_int32(a int32) int32 { return -2147483647 ^ a } //go:noinline -func or_1_int32_ssa(a int32) int32 { - return 1 | a -} +func xor_int32_Neg1(a int32) int32 { return a ^ -1 } //go:noinline -func or_int32_2147483647_ssa(a int32) int32 { - return a | 2147483647 -} +func xor_Neg1_int32(a int32) int32 { return -1 ^ a } //go:noinline -func or_2147483647_int32_ssa(a int32) int32 { - return 2147483647 | a -} +func xor_int32_0(a int32) int32 { return a ^ 0 } //go:noinline -func xor_int32_Neg2147483648_ssa(a int32) int32 { - return a ^ -2147483648 -} +func xor_0_int32(a int32) int32 { return 0 ^ a } //go:noinline -func xor_Neg2147483648_int32_ssa(a int32) int32 { - return -2147483648 ^ a -} +func xor_int32_1(a int32) int32 { return a ^ 1 } //go:noinline -func xor_int32_Neg2147483647_ssa(a int32) int32 { - return a ^ -2147483647 -} +func xor_1_int32(a int32) int32 { return 1 ^ a } //go:noinline -func xor_Neg2147483647_int32_ssa(a int32) int32 { - return -2147483647 ^ a -} +func xor_int32_2147483647(a int32) int32 { return a ^ 2147483647 } //go:noinline -func xor_int32_Neg1_ssa(a int32) int32 { - return a ^ -1 -} +func xor_2147483647_int32(a int32) int32 { return 2147483647 ^ a } //go:noinline -func xor_Neg1_int32_ssa(a int32) int32 { - return -1 ^ a -} +func add_uint16_0(a uint16) uint16 { return a + 0 } //go:noinline -func xor_int32_0_ssa(a int32) int32 { - return a ^ 0 -} +func add_0_uint16(a uint16) uint16 { return 0 + a } //go:noinline -func xor_0_int32_ssa(a int32) int32 { - return 0 ^ a -} +func add_uint16_1(a uint16) uint16 { return a + 1 } //go:noinline -func xor_int32_1_ssa(a int32) int32 { - return a ^ 1 -} +func add_1_uint16(a uint16) uint16 { return 1 + a } //go:noinline -func xor_1_int32_ssa(a int32) int32 { - return 1 ^ a -} +func add_uint16_65535(a uint16) uint16 { return a + 65535 } //go:noinline -func xor_int32_2147483647_ssa(a int32) int32 { - return a ^ 2147483647 -} +func add_65535_uint16(a uint16) uint16 { return 65535 + a } //go:noinline -func xor_2147483647_int32_ssa(a int32) int32 { - return 2147483647 ^ a -} +func sub_uint16_0(a uint16) uint16 { return a - 0 } //go:noinline -func add_uint16_0_ssa(a uint16) uint16 { - return a + 0 -} +func sub_0_uint16(a uint16) uint16 { return 0 - a } //go:noinline -func add_0_uint16_ssa(a uint16) uint16 { - return 0 + a -} +func sub_uint16_1(a uint16) uint16 { return a - 1 } //go:noinline -func add_uint16_1_ssa(a uint16) uint16 { - return a + 1 -} +func sub_1_uint16(a uint16) uint16 { return 1 - a } //go:noinline -func add_1_uint16_ssa(a uint16) uint16 { - return 1 + a -} +func sub_uint16_65535(a uint16) uint16 { return a - 65535 } //go:noinline -func add_uint16_65535_ssa(a uint16) uint16 { - return a + 65535 -} +func sub_65535_uint16(a uint16) uint16 { return 65535 - a } //go:noinline -func add_65535_uint16_ssa(a uint16) uint16 { - return 65535 + a -} +func div_0_uint16(a uint16) uint16 { return 0 / a } //go:noinline -func sub_uint16_0_ssa(a uint16) uint16 { - return a - 0 -} +func div_uint16_1(a uint16) uint16 { return a / 1 } //go:noinline -func sub_0_uint16_ssa(a uint16) uint16 { - return 0 - a -} +func div_1_uint16(a uint16) uint16 { return 1 / a } //go:noinline -func sub_uint16_1_ssa(a uint16) uint16 { - return a - 1 -} +func div_uint16_65535(a uint16) uint16 { return a / 65535 } //go:noinline -func sub_1_uint16_ssa(a uint16) uint16 { - return 1 - a -} +func div_65535_uint16(a uint16) uint16 { return 65535 / a } //go:noinline -func sub_uint16_65535_ssa(a uint16) uint16 { - return a - 65535 -} +func mul_uint16_0(a uint16) uint16 { return a * 0 } //go:noinline -func sub_65535_uint16_ssa(a uint16) uint16 { - return 65535 - a -} +func mul_0_uint16(a uint16) uint16 { return 0 * a } //go:noinline -func div_0_uint16_ssa(a uint16) uint16 { - return 0 / a -} +func mul_uint16_1(a uint16) uint16 { return a * 1 } //go:noinline -func div_uint16_1_ssa(a uint16) uint16 { - return a / 1 -} +func mul_1_uint16(a uint16) uint16 { return 1 * a } //go:noinline -func div_1_uint16_ssa(a uint16) uint16 { - return 1 / a -} +func mul_uint16_65535(a uint16) uint16 { return a * 65535 } //go:noinline -func div_uint16_65535_ssa(a uint16) uint16 { - return a / 65535 -} +func mul_65535_uint16(a uint16) uint16 { return 65535 * a } //go:noinline -func div_65535_uint16_ssa(a uint16) uint16 { - return 65535 / a -} +func lsh_uint16_0(a uint16) uint16 { return a << 0 } //go:noinline -func mul_uint16_0_ssa(a uint16) uint16 { - return a * 0 -} +func lsh_0_uint16(a uint16) uint16 { return 0 << a } //go:noinline -func mul_0_uint16_ssa(a uint16) uint16 { - return 0 * a -} +func lsh_uint16_1(a uint16) uint16 { return a << 1 } //go:noinline -func mul_uint16_1_ssa(a uint16) uint16 { - return a * 1 -} +func lsh_1_uint16(a uint16) uint16 { return 1 << a } //go:noinline -func mul_1_uint16_ssa(a uint16) uint16 { - return 1 * a -} +func lsh_uint16_65535(a uint16) uint16 { return a << 65535 } //go:noinline -func mul_uint16_65535_ssa(a uint16) uint16 { - return a * 65535 -} +func lsh_65535_uint16(a uint16) uint16 { return 65535 << a } //go:noinline -func mul_65535_uint16_ssa(a uint16) uint16 { - return 65535 * a -} +func rsh_uint16_0(a uint16) uint16 { return a >> 0 } //go:noinline -func lsh_uint16_0_ssa(a uint16) uint16 { - return a << 0 -} +func rsh_0_uint16(a uint16) uint16 { return 0 >> a } //go:noinline -func lsh_0_uint16_ssa(a uint16) uint16 { - return 0 << a -} +func rsh_uint16_1(a uint16) uint16 { return a >> 1 } //go:noinline -func lsh_uint16_1_ssa(a uint16) uint16 { - return a << 1 -} +func rsh_1_uint16(a uint16) uint16 { return 1 >> a } //go:noinline -func lsh_1_uint16_ssa(a uint16) uint16 { - return 1 << a -} +func rsh_uint16_65535(a uint16) uint16 { return a >> 65535 } //go:noinline -func lsh_uint16_65535_ssa(a uint16) uint16 { - return a << 65535 -} +func rsh_65535_uint16(a uint16) uint16 { return 65535 >> a } //go:noinline -func lsh_65535_uint16_ssa(a uint16) uint16 { - return 65535 << a -} +func mod_0_uint16(a uint16) uint16 { return 0 % a } //go:noinline -func rsh_uint16_0_ssa(a uint16) uint16 { - return a >> 0 -} +func mod_uint16_1(a uint16) uint16 { return a % 1 } //go:noinline -func rsh_0_uint16_ssa(a uint16) uint16 { - return 0 >> a -} +func mod_1_uint16(a uint16) uint16 { return 1 % a } //go:noinline -func rsh_uint16_1_ssa(a uint16) uint16 { - return a >> 1 -} +func mod_uint16_65535(a uint16) uint16 { return a % 65535 } //go:noinline -func rsh_1_uint16_ssa(a uint16) uint16 { - return 1 >> a -} +func mod_65535_uint16(a uint16) uint16 { return 65535 % a } //go:noinline -func rsh_uint16_65535_ssa(a uint16) uint16 { - return a >> 65535 -} +func and_uint16_0(a uint16) uint16 { return a & 0 } //go:noinline -func rsh_65535_uint16_ssa(a uint16) uint16 { - return 65535 >> a -} +func and_0_uint16(a uint16) uint16 { return 0 & a } //go:noinline -func mod_0_uint16_ssa(a uint16) uint16 { - return 0 % a -} +func and_uint16_1(a uint16) uint16 { return a & 1 } //go:noinline -func mod_uint16_1_ssa(a uint16) uint16 { - return a % 1 -} +func and_1_uint16(a uint16) uint16 { return 1 & a } //go:noinline -func mod_1_uint16_ssa(a uint16) uint16 { - return 1 % a -} +func and_uint16_65535(a uint16) uint16 { return a & 65535 } //go:noinline -func mod_uint16_65535_ssa(a uint16) uint16 { - return a % 65535 -} +func and_65535_uint16(a uint16) uint16 { return 65535 & a } //go:noinline -func mod_65535_uint16_ssa(a uint16) uint16 { - return 65535 % a -} +func or_uint16_0(a uint16) uint16 { return a | 0 } //go:noinline -func and_uint16_0_ssa(a uint16) uint16 { - return a & 0 -} +func or_0_uint16(a uint16) uint16 { return 0 | a } //go:noinline -func and_0_uint16_ssa(a uint16) uint16 { - return 0 & a -} +func or_uint16_1(a uint16) uint16 { return a | 1 } //go:noinline -func and_uint16_1_ssa(a uint16) uint16 { - return a & 1 -} +func or_1_uint16(a uint16) uint16 { return 1 | a } //go:noinline -func and_1_uint16_ssa(a uint16) uint16 { - return 1 & a -} +func or_uint16_65535(a uint16) uint16 { return a | 65535 } //go:noinline -func and_uint16_65535_ssa(a uint16) uint16 { - return a & 65535 -} +func or_65535_uint16(a uint16) uint16 { return 65535 | a } //go:noinline -func and_65535_uint16_ssa(a uint16) uint16 { - return 65535 & a -} +func xor_uint16_0(a uint16) uint16 { return a ^ 0 } //go:noinline -func or_uint16_0_ssa(a uint16) uint16 { - return a | 0 -} +func xor_0_uint16(a uint16) uint16 { return 0 ^ a } //go:noinline -func or_0_uint16_ssa(a uint16) uint16 { - return 0 | a -} +func xor_uint16_1(a uint16) uint16 { return a ^ 1 } //go:noinline -func or_uint16_1_ssa(a uint16) uint16 { - return a | 1 -} +func xor_1_uint16(a uint16) uint16 { return 1 ^ a } //go:noinline -func or_1_uint16_ssa(a uint16) uint16 { - return 1 | a -} +func xor_uint16_65535(a uint16) uint16 { return a ^ 65535 } //go:noinline -func or_uint16_65535_ssa(a uint16) uint16 { - return a | 65535 -} +func xor_65535_uint16(a uint16) uint16 { return 65535 ^ a } //go:noinline -func or_65535_uint16_ssa(a uint16) uint16 { - return 65535 | a -} +func add_int16_Neg32768(a int16) int16 { return a + -32768 } //go:noinline -func xor_uint16_0_ssa(a uint16) uint16 { - return a ^ 0 -} +func add_Neg32768_int16(a int16) int16 { return -32768 + a } //go:noinline -func xor_0_uint16_ssa(a uint16) uint16 { - return 0 ^ a -} +func add_int16_Neg32767(a int16) int16 { return a + -32767 } //go:noinline -func xor_uint16_1_ssa(a uint16) uint16 { - return a ^ 1 -} +func add_Neg32767_int16(a int16) int16 { return -32767 + a } //go:noinline -func xor_1_uint16_ssa(a uint16) uint16 { - return 1 ^ a -} +func add_int16_Neg1(a int16) int16 { return a + -1 } //go:noinline -func xor_uint16_65535_ssa(a uint16) uint16 { - return a ^ 65535 -} +func add_Neg1_int16(a int16) int16 { return -1 + a } //go:noinline -func xor_65535_uint16_ssa(a uint16) uint16 { - return 65535 ^ a -} +func add_int16_0(a int16) int16 { return a + 0 } //go:noinline -func add_int16_Neg32768_ssa(a int16) int16 { - return a + -32768 -} +func add_0_int16(a int16) int16 { return 0 + a } //go:noinline -func add_Neg32768_int16_ssa(a int16) int16 { - return -32768 + a -} +func add_int16_1(a int16) int16 { return a + 1 } //go:noinline -func add_int16_Neg32767_ssa(a int16) int16 { - return a + -32767 -} +func add_1_int16(a int16) int16 { return 1 + a } //go:noinline -func add_Neg32767_int16_ssa(a int16) int16 { - return -32767 + a -} +func add_int16_32766(a int16) int16 { return a + 32766 } //go:noinline -func add_int16_Neg1_ssa(a int16) int16 { - return a + -1 -} +func add_32766_int16(a int16) int16 { return 32766 + a } //go:noinline -func add_Neg1_int16_ssa(a int16) int16 { - return -1 + a -} +func add_int16_32767(a int16) int16 { return a + 32767 } //go:noinline -func add_int16_0_ssa(a int16) int16 { - return a + 0 -} +func add_32767_int16(a int16) int16 { return 32767 + a } //go:noinline -func add_0_int16_ssa(a int16) int16 { - return 0 + a -} +func sub_int16_Neg32768(a int16) int16 { return a - -32768 } //go:noinline -func add_int16_1_ssa(a int16) int16 { - return a + 1 -} +func sub_Neg32768_int16(a int16) int16 { return -32768 - a } //go:noinline -func add_1_int16_ssa(a int16) int16 { - return 1 + a -} +func sub_int16_Neg32767(a int16) int16 { return a - -32767 } //go:noinline -func add_int16_32766_ssa(a int16) int16 { - return a + 32766 -} +func sub_Neg32767_int16(a int16) int16 { return -32767 - a } //go:noinline -func add_32766_int16_ssa(a int16) int16 { - return 32766 + a -} +func sub_int16_Neg1(a int16) int16 { return a - -1 } //go:noinline -func add_int16_32767_ssa(a int16) int16 { - return a + 32767 -} +func sub_Neg1_int16(a int16) int16 { return -1 - a } //go:noinline -func add_32767_int16_ssa(a int16) int16 { - return 32767 + a -} +func sub_int16_0(a int16) int16 { return a - 0 } //go:noinline -func sub_int16_Neg32768_ssa(a int16) int16 { - return a - -32768 -} +func sub_0_int16(a int16) int16 { return 0 - a } //go:noinline -func sub_Neg32768_int16_ssa(a int16) int16 { - return -32768 - a -} +func sub_int16_1(a int16) int16 { return a - 1 } //go:noinline -func sub_int16_Neg32767_ssa(a int16) int16 { - return a - -32767 -} +func sub_1_int16(a int16) int16 { return 1 - a } //go:noinline -func sub_Neg32767_int16_ssa(a int16) int16 { - return -32767 - a -} +func sub_int16_32766(a int16) int16 { return a - 32766 } //go:noinline -func sub_int16_Neg1_ssa(a int16) int16 { - return a - -1 -} +func sub_32766_int16(a int16) int16 { return 32766 - a } //go:noinline -func sub_Neg1_int16_ssa(a int16) int16 { - return -1 - a -} +func sub_int16_32767(a int16) int16 { return a - 32767 } //go:noinline -func sub_int16_0_ssa(a int16) int16 { - return a - 0 -} +func sub_32767_int16(a int16) int16 { return 32767 - a } //go:noinline -func sub_0_int16_ssa(a int16) int16 { - return 0 - a -} +func div_int16_Neg32768(a int16) int16 { return a / -32768 } //go:noinline -func sub_int16_1_ssa(a int16) int16 { - return a - 1 -} +func div_Neg32768_int16(a int16) int16 { return -32768 / a } //go:noinline -func sub_1_int16_ssa(a int16) int16 { - return 1 - a -} +func div_int16_Neg32767(a int16) int16 { return a / -32767 } //go:noinline -func sub_int16_32766_ssa(a int16) int16 { - return a - 32766 -} +func div_Neg32767_int16(a int16) int16 { return -32767 / a } //go:noinline -func sub_32766_int16_ssa(a int16) int16 { - return 32766 - a -} +func div_int16_Neg1(a int16) int16 { return a / -1 } //go:noinline -func sub_int16_32767_ssa(a int16) int16 { - return a - 32767 -} +func div_Neg1_int16(a int16) int16 { return -1 / a } //go:noinline -func sub_32767_int16_ssa(a int16) int16 { - return 32767 - a -} +func div_0_int16(a int16) int16 { return 0 / a } //go:noinline -func div_int16_Neg32768_ssa(a int16) int16 { - return a / -32768 -} +func div_int16_1(a int16) int16 { return a / 1 } //go:noinline -func div_Neg32768_int16_ssa(a int16) int16 { - return -32768 / a -} +func div_1_int16(a int16) int16 { return 1 / a } //go:noinline -func div_int16_Neg32767_ssa(a int16) int16 { - return a / -32767 -} +func div_int16_32766(a int16) int16 { return a / 32766 } //go:noinline -func div_Neg32767_int16_ssa(a int16) int16 { - return -32767 / a -} +func div_32766_int16(a int16) int16 { return 32766 / a } //go:noinline -func div_int16_Neg1_ssa(a int16) int16 { - return a / -1 -} +func div_int16_32767(a int16) int16 { return a / 32767 } //go:noinline -func div_Neg1_int16_ssa(a int16) int16 { - return -1 / a -} +func div_32767_int16(a int16) int16 { return 32767 / a } //go:noinline -func div_0_int16_ssa(a int16) int16 { - return 0 / a -} +func mul_int16_Neg32768(a int16) int16 { return a * -32768 } //go:noinline -func div_int16_1_ssa(a int16) int16 { - return a / 1 -} +func mul_Neg32768_int16(a int16) int16 { return -32768 * a } //go:noinline -func div_1_int16_ssa(a int16) int16 { - return 1 / a -} +func mul_int16_Neg32767(a int16) int16 { return a * -32767 } //go:noinline -func div_int16_32766_ssa(a int16) int16 { - return a / 32766 -} +func mul_Neg32767_int16(a int16) int16 { return -32767 * a } //go:noinline -func div_32766_int16_ssa(a int16) int16 { - return 32766 / a -} +func mul_int16_Neg1(a int16) int16 { return a * -1 } //go:noinline -func div_int16_32767_ssa(a int16) int16 { - return a / 32767 -} +func mul_Neg1_int16(a int16) int16 { return -1 * a } //go:noinline -func div_32767_int16_ssa(a int16) int16 { - return 32767 / a -} +func mul_int16_0(a int16) int16 { return a * 0 } //go:noinline -func mul_int16_Neg32768_ssa(a int16) int16 { - return a * -32768 -} +func mul_0_int16(a int16) int16 { return 0 * a } //go:noinline -func mul_Neg32768_int16_ssa(a int16) int16 { - return -32768 * a -} +func mul_int16_1(a int16) int16 { return a * 1 } //go:noinline -func mul_int16_Neg32767_ssa(a int16) int16 { - return a * -32767 -} +func mul_1_int16(a int16) int16 { return 1 * a } //go:noinline -func mul_Neg32767_int16_ssa(a int16) int16 { - return -32767 * a -} +func mul_int16_32766(a int16) int16 { return a * 32766 } //go:noinline -func mul_int16_Neg1_ssa(a int16) int16 { - return a * -1 -} +func mul_32766_int16(a int16) int16 { return 32766 * a } //go:noinline -func mul_Neg1_int16_ssa(a int16) int16 { - return -1 * a -} +func mul_int16_32767(a int16) int16 { return a * 32767 } //go:noinline -func mul_int16_0_ssa(a int16) int16 { - return a * 0 -} +func mul_32767_int16(a int16) int16 { return 32767 * a } //go:noinline -func mul_0_int16_ssa(a int16) int16 { - return 0 * a -} +func mod_int16_Neg32768(a int16) int16 { return a % -32768 } //go:noinline -func mul_int16_1_ssa(a int16) int16 { - return a * 1 -} +func mod_Neg32768_int16(a int16) int16 { return -32768 % a } //go:noinline -func mul_1_int16_ssa(a int16) int16 { - return 1 * a -} +func mod_int16_Neg32767(a int16) int16 { return a % -32767 } //go:noinline -func mul_int16_32766_ssa(a int16) int16 { - return a * 32766 -} +func mod_Neg32767_int16(a int16) int16 { return -32767 % a } //go:noinline -func mul_32766_int16_ssa(a int16) int16 { - return 32766 * a -} +func mod_int16_Neg1(a int16) int16 { return a % -1 } //go:noinline -func mul_int16_32767_ssa(a int16) int16 { - return a * 32767 -} +func mod_Neg1_int16(a int16) int16 { return -1 % a } //go:noinline -func mul_32767_int16_ssa(a int16) int16 { - return 32767 * a -} +func mod_0_int16(a int16) int16 { return 0 % a } //go:noinline -func mod_int16_Neg32768_ssa(a int16) int16 { - return a % -32768 -} +func mod_int16_1(a int16) int16 { return a % 1 } //go:noinline -func mod_Neg32768_int16_ssa(a int16) int16 { - return -32768 % a -} +func mod_1_int16(a int16) int16 { return 1 % a } //go:noinline -func mod_int16_Neg32767_ssa(a int16) int16 { - return a % -32767 -} +func mod_int16_32766(a int16) int16 { return a % 32766 } //go:noinline -func mod_Neg32767_int16_ssa(a int16) int16 { - return -32767 % a -} +func mod_32766_int16(a int16) int16 { return 32766 % a } //go:noinline -func mod_int16_Neg1_ssa(a int16) int16 { - return a % -1 -} +func mod_int16_32767(a int16) int16 { return a % 32767 } //go:noinline -func mod_Neg1_int16_ssa(a int16) int16 { - return -1 % a -} +func mod_32767_int16(a int16) int16 { return 32767 % a } //go:noinline -func mod_0_int16_ssa(a int16) int16 { - return 0 % a -} +func and_int16_Neg32768(a int16) int16 { return a & -32768 } //go:noinline -func mod_int16_1_ssa(a int16) int16 { - return a % 1 -} +func and_Neg32768_int16(a int16) int16 { return -32768 & a } //go:noinline -func mod_1_int16_ssa(a int16) int16 { - return 1 % a -} +func and_int16_Neg32767(a int16) int16 { return a & -32767 } //go:noinline -func mod_int16_32766_ssa(a int16) int16 { - return a % 32766 -} +func and_Neg32767_int16(a int16) int16 { return -32767 & a } //go:noinline -func mod_32766_int16_ssa(a int16) int16 { - return 32766 % a -} +func and_int16_Neg1(a int16) int16 { return a & -1 } //go:noinline -func mod_int16_32767_ssa(a int16) int16 { - return a % 32767 -} +func and_Neg1_int16(a int16) int16 { return -1 & a } //go:noinline -func mod_32767_int16_ssa(a int16) int16 { - return 32767 % a -} +func and_int16_0(a int16) int16 { return a & 0 } //go:noinline -func and_int16_Neg32768_ssa(a int16) int16 { - return a & -32768 -} +func and_0_int16(a int16) int16 { return 0 & a } //go:noinline -func and_Neg32768_int16_ssa(a int16) int16 { - return -32768 & a -} +func and_int16_1(a int16) int16 { return a & 1 } //go:noinline -func and_int16_Neg32767_ssa(a int16) int16 { - return a & -32767 -} +func and_1_int16(a int16) int16 { return 1 & a } //go:noinline -func and_Neg32767_int16_ssa(a int16) int16 { - return -32767 & a -} +func and_int16_32766(a int16) int16 { return a & 32766 } //go:noinline -func and_int16_Neg1_ssa(a int16) int16 { - return a & -1 -} +func and_32766_int16(a int16) int16 { return 32766 & a } //go:noinline -func and_Neg1_int16_ssa(a int16) int16 { - return -1 & a -} +func and_int16_32767(a int16) int16 { return a & 32767 } //go:noinline -func and_int16_0_ssa(a int16) int16 { - return a & 0 -} +func and_32767_int16(a int16) int16 { return 32767 & a } //go:noinline -func and_0_int16_ssa(a int16) int16 { - return 0 & a -} +func or_int16_Neg32768(a int16) int16 { return a | -32768 } //go:noinline -func and_int16_1_ssa(a int16) int16 { - return a & 1 -} +func or_Neg32768_int16(a int16) int16 { return -32768 | a } //go:noinline -func and_1_int16_ssa(a int16) int16 { - return 1 & a -} +func or_int16_Neg32767(a int16) int16 { return a | -32767 } //go:noinline -func and_int16_32766_ssa(a int16) int16 { - return a & 32766 -} +func or_Neg32767_int16(a int16) int16 { return -32767 | a } //go:noinline -func and_32766_int16_ssa(a int16) int16 { - return 32766 & a -} +func or_int16_Neg1(a int16) int16 { return a | -1 } //go:noinline -func and_int16_32767_ssa(a int16) int16 { - return a & 32767 -} +func or_Neg1_int16(a int16) int16 { return -1 | a } //go:noinline -func and_32767_int16_ssa(a int16) int16 { - return 32767 & a -} +func or_int16_0(a int16) int16 { return a | 0 } //go:noinline -func or_int16_Neg32768_ssa(a int16) int16 { - return a | -32768 -} +func or_0_int16(a int16) int16 { return 0 | a } //go:noinline -func or_Neg32768_int16_ssa(a int16) int16 { - return -32768 | a -} +func or_int16_1(a int16) int16 { return a | 1 } //go:noinline -func or_int16_Neg32767_ssa(a int16) int16 { - return a | -32767 -} +func or_1_int16(a int16) int16 { return 1 | a } //go:noinline -func or_Neg32767_int16_ssa(a int16) int16 { - return -32767 | a -} +func or_int16_32766(a int16) int16 { return a | 32766 } //go:noinline -func or_int16_Neg1_ssa(a int16) int16 { - return a | -1 -} +func or_32766_int16(a int16) int16 { return 32766 | a } //go:noinline -func or_Neg1_int16_ssa(a int16) int16 { - return -1 | a -} +func or_int16_32767(a int16) int16 { return a | 32767 } //go:noinline -func or_int16_0_ssa(a int16) int16 { - return a | 0 -} +func or_32767_int16(a int16) int16 { return 32767 | a } //go:noinline -func or_0_int16_ssa(a int16) int16 { - return 0 | a -} +func xor_int16_Neg32768(a int16) int16 { return a ^ -32768 } //go:noinline -func or_int16_1_ssa(a int16) int16 { - return a | 1 -} +func xor_Neg32768_int16(a int16) int16 { return -32768 ^ a } //go:noinline -func or_1_int16_ssa(a int16) int16 { - return 1 | a -} +func xor_int16_Neg32767(a int16) int16 { return a ^ -32767 } //go:noinline -func or_int16_32766_ssa(a int16) int16 { - return a | 32766 -} +func xor_Neg32767_int16(a int16) int16 { return -32767 ^ a } //go:noinline -func or_32766_int16_ssa(a int16) int16 { - return 32766 | a -} +func xor_int16_Neg1(a int16) int16 { return a ^ -1 } //go:noinline -func or_int16_32767_ssa(a int16) int16 { - return a | 32767 -} +func xor_Neg1_int16(a int16) int16 { return -1 ^ a } //go:noinline -func or_32767_int16_ssa(a int16) int16 { - return 32767 | a -} +func xor_int16_0(a int16) int16 { return a ^ 0 } //go:noinline -func xor_int16_Neg32768_ssa(a int16) int16 { - return a ^ -32768 -} +func xor_0_int16(a int16) int16 { return 0 ^ a } //go:noinline -func xor_Neg32768_int16_ssa(a int16) int16 { - return -32768 ^ a -} +func xor_int16_1(a int16) int16 { return a ^ 1 } //go:noinline -func xor_int16_Neg32767_ssa(a int16) int16 { - return a ^ -32767 -} +func xor_1_int16(a int16) int16 { return 1 ^ a } //go:noinline -func xor_Neg32767_int16_ssa(a int16) int16 { - return -32767 ^ a -} +func xor_int16_32766(a int16) int16 { return a ^ 32766 } //go:noinline -func xor_int16_Neg1_ssa(a int16) int16 { - return a ^ -1 -} +func xor_32766_int16(a int16) int16 { return 32766 ^ a } //go:noinline -func xor_Neg1_int16_ssa(a int16) int16 { - return -1 ^ a -} +func xor_int16_32767(a int16) int16 { return a ^ 32767 } //go:noinline -func xor_int16_0_ssa(a int16) int16 { - return a ^ 0 -} +func xor_32767_int16(a int16) int16 { return 32767 ^ a } //go:noinline -func xor_0_int16_ssa(a int16) int16 { - return 0 ^ a -} +func add_uint8_0(a uint8) uint8 { return a + 0 } //go:noinline -func xor_int16_1_ssa(a int16) int16 { - return a ^ 1 -} +func add_0_uint8(a uint8) uint8 { return 0 + a } //go:noinline -func xor_1_int16_ssa(a int16) int16 { - return 1 ^ a -} +func add_uint8_1(a uint8) uint8 { return a + 1 } //go:noinline -func xor_int16_32766_ssa(a int16) int16 { - return a ^ 32766 -} +func add_1_uint8(a uint8) uint8 { return 1 + a } //go:noinline -func xor_32766_int16_ssa(a int16) int16 { - return 32766 ^ a -} +func add_uint8_255(a uint8) uint8 { return a + 255 } //go:noinline -func xor_int16_32767_ssa(a int16) int16 { - return a ^ 32767 -} +func add_255_uint8(a uint8) uint8 { return 255 + a } //go:noinline -func xor_32767_int16_ssa(a int16) int16 { - return 32767 ^ a -} +func sub_uint8_0(a uint8) uint8 { return a - 0 } //go:noinline -func add_uint8_0_ssa(a uint8) uint8 { - return a + 0 -} +func sub_0_uint8(a uint8) uint8 { return 0 - a } //go:noinline -func add_0_uint8_ssa(a uint8) uint8 { - return 0 + a -} +func sub_uint8_1(a uint8) uint8 { return a - 1 } //go:noinline -func add_uint8_1_ssa(a uint8) uint8 { - return a + 1 -} +func sub_1_uint8(a uint8) uint8 { return 1 - a } //go:noinline -func add_1_uint8_ssa(a uint8) uint8 { - return 1 + a -} +func sub_uint8_255(a uint8) uint8 { return a - 255 } //go:noinline -func add_uint8_255_ssa(a uint8) uint8 { - return a + 255 -} +func sub_255_uint8(a uint8) uint8 { return 255 - a } //go:noinline -func add_255_uint8_ssa(a uint8) uint8 { - return 255 + a -} +func div_0_uint8(a uint8) uint8 { return 0 / a } //go:noinline -func sub_uint8_0_ssa(a uint8) uint8 { - return a - 0 -} +func div_uint8_1(a uint8) uint8 { return a / 1 } //go:noinline -func sub_0_uint8_ssa(a uint8) uint8 { - return 0 - a -} +func div_1_uint8(a uint8) uint8 { return 1 / a } //go:noinline -func sub_uint8_1_ssa(a uint8) uint8 { - return a - 1 -} +func div_uint8_255(a uint8) uint8 { return a / 255 } //go:noinline -func sub_1_uint8_ssa(a uint8) uint8 { - return 1 - a -} +func div_255_uint8(a uint8) uint8 { return 255 / a } //go:noinline -func sub_uint8_255_ssa(a uint8) uint8 { - return a - 255 -} +func mul_uint8_0(a uint8) uint8 { return a * 0 } //go:noinline -func sub_255_uint8_ssa(a uint8) uint8 { - return 255 - a -} +func mul_0_uint8(a uint8) uint8 { return 0 * a } //go:noinline -func div_0_uint8_ssa(a uint8) uint8 { - return 0 / a -} +func mul_uint8_1(a uint8) uint8 { return a * 1 } //go:noinline -func div_uint8_1_ssa(a uint8) uint8 { - return a / 1 -} +func mul_1_uint8(a uint8) uint8 { return 1 * a } //go:noinline -func div_1_uint8_ssa(a uint8) uint8 { - return 1 / a -} +func mul_uint8_255(a uint8) uint8 { return a * 255 } //go:noinline -func div_uint8_255_ssa(a uint8) uint8 { - return a / 255 -} +func mul_255_uint8(a uint8) uint8 { return 255 * a } //go:noinline -func div_255_uint8_ssa(a uint8) uint8 { - return 255 / a -} +func lsh_uint8_0(a uint8) uint8 { return a << 0 } //go:noinline -func mul_uint8_0_ssa(a uint8) uint8 { - return a * 0 -} +func lsh_0_uint8(a uint8) uint8 { return 0 << a } //go:noinline -func mul_0_uint8_ssa(a uint8) uint8 { - return 0 * a -} +func lsh_uint8_1(a uint8) uint8 { return a << 1 } //go:noinline -func mul_uint8_1_ssa(a uint8) uint8 { - return a * 1 -} +func lsh_1_uint8(a uint8) uint8 { return 1 << a } //go:noinline -func mul_1_uint8_ssa(a uint8) uint8 { - return 1 * a -} +func lsh_uint8_255(a uint8) uint8 { return a << 255 } //go:noinline -func mul_uint8_255_ssa(a uint8) uint8 { - return a * 255 -} +func lsh_255_uint8(a uint8) uint8 { return 255 << a } //go:noinline -func mul_255_uint8_ssa(a uint8) uint8 { - return 255 * a -} +func rsh_uint8_0(a uint8) uint8 { return a >> 0 } //go:noinline -func lsh_uint8_0_ssa(a uint8) uint8 { - return a << 0 -} +func rsh_0_uint8(a uint8) uint8 { return 0 >> a } //go:noinline -func lsh_0_uint8_ssa(a uint8) uint8 { - return 0 << a -} +func rsh_uint8_1(a uint8) uint8 { return a >> 1 } //go:noinline -func lsh_uint8_1_ssa(a uint8) uint8 { - return a << 1 -} +func rsh_1_uint8(a uint8) uint8 { return 1 >> a } //go:noinline -func lsh_1_uint8_ssa(a uint8) uint8 { - return 1 << a -} +func rsh_uint8_255(a uint8) uint8 { return a >> 255 } //go:noinline -func lsh_uint8_255_ssa(a uint8) uint8 { - return a << 255 -} +func rsh_255_uint8(a uint8) uint8 { return 255 >> a } //go:noinline -func lsh_255_uint8_ssa(a uint8) uint8 { - return 255 << a -} +func mod_0_uint8(a uint8) uint8 { return 0 % a } //go:noinline -func rsh_uint8_0_ssa(a uint8) uint8 { - return a >> 0 -} +func mod_uint8_1(a uint8) uint8 { return a % 1 } //go:noinline -func rsh_0_uint8_ssa(a uint8) uint8 { - return 0 >> a -} +func mod_1_uint8(a uint8) uint8 { return 1 % a } //go:noinline -func rsh_uint8_1_ssa(a uint8) uint8 { - return a >> 1 -} +func mod_uint8_255(a uint8) uint8 { return a % 255 } //go:noinline -func rsh_1_uint8_ssa(a uint8) uint8 { - return 1 >> a -} +func mod_255_uint8(a uint8) uint8 { return 255 % a } //go:noinline -func rsh_uint8_255_ssa(a uint8) uint8 { - return a >> 255 -} +func and_uint8_0(a uint8) uint8 { return a & 0 } //go:noinline -func rsh_255_uint8_ssa(a uint8) uint8 { - return 255 >> a -} +func and_0_uint8(a uint8) uint8 { return 0 & a } //go:noinline -func mod_0_uint8_ssa(a uint8) uint8 { - return 0 % a -} +func and_uint8_1(a uint8) uint8 { return a & 1 } //go:noinline -func mod_uint8_1_ssa(a uint8) uint8 { - return a % 1 -} +func and_1_uint8(a uint8) uint8 { return 1 & a } //go:noinline -func mod_1_uint8_ssa(a uint8) uint8 { - return 1 % a -} +func and_uint8_255(a uint8) uint8 { return a & 255 } //go:noinline -func mod_uint8_255_ssa(a uint8) uint8 { - return a % 255 -} +func and_255_uint8(a uint8) uint8 { return 255 & a } //go:noinline -func mod_255_uint8_ssa(a uint8) uint8 { - return 255 % a -} +func or_uint8_0(a uint8) uint8 { return a | 0 } //go:noinline -func and_uint8_0_ssa(a uint8) uint8 { - return a & 0 -} +func or_0_uint8(a uint8) uint8 { return 0 | a } //go:noinline -func and_0_uint8_ssa(a uint8) uint8 { - return 0 & a -} +func or_uint8_1(a uint8) uint8 { return a | 1 } //go:noinline -func and_uint8_1_ssa(a uint8) uint8 { - return a & 1 -} +func or_1_uint8(a uint8) uint8 { return 1 | a } //go:noinline -func and_1_uint8_ssa(a uint8) uint8 { - return 1 & a -} +func or_uint8_255(a uint8) uint8 { return a | 255 } //go:noinline -func and_uint8_255_ssa(a uint8) uint8 { - return a & 255 -} +func or_255_uint8(a uint8) uint8 { return 255 | a } //go:noinline -func and_255_uint8_ssa(a uint8) uint8 { - return 255 & a -} +func xor_uint8_0(a uint8) uint8 { return a ^ 0 } //go:noinline -func or_uint8_0_ssa(a uint8) uint8 { - return a | 0 -} +func xor_0_uint8(a uint8) uint8 { return 0 ^ a } //go:noinline -func or_0_uint8_ssa(a uint8) uint8 { - return 0 | a -} +func xor_uint8_1(a uint8) uint8 { return a ^ 1 } //go:noinline -func or_uint8_1_ssa(a uint8) uint8 { - return a | 1 -} +func xor_1_uint8(a uint8) uint8 { return 1 ^ a } //go:noinline -func or_1_uint8_ssa(a uint8) uint8 { - return 1 | a -} +func xor_uint8_255(a uint8) uint8 { return a ^ 255 } //go:noinline -func or_uint8_255_ssa(a uint8) uint8 { - return a | 255 -} +func xor_255_uint8(a uint8) uint8 { return 255 ^ a } //go:noinline -func or_255_uint8_ssa(a uint8) uint8 { - return 255 | a -} +func add_int8_Neg128(a int8) int8 { return a + -128 } //go:noinline -func xor_uint8_0_ssa(a uint8) uint8 { - return a ^ 0 -} +func add_Neg128_int8(a int8) int8 { return -128 + a } //go:noinline -func xor_0_uint8_ssa(a uint8) uint8 { - return 0 ^ a -} +func add_int8_Neg127(a int8) int8 { return a + -127 } //go:noinline -func xor_uint8_1_ssa(a uint8) uint8 { - return a ^ 1 -} +func add_Neg127_int8(a int8) int8 { return -127 + a } //go:noinline -func xor_1_uint8_ssa(a uint8) uint8 { - return 1 ^ a -} +func add_int8_Neg1(a int8) int8 { return a + -1 } //go:noinline -func xor_uint8_255_ssa(a uint8) uint8 { - return a ^ 255 -} +func add_Neg1_int8(a int8) int8 { return -1 + a } //go:noinline -func xor_255_uint8_ssa(a uint8) uint8 { - return 255 ^ a -} +func add_int8_0(a int8) int8 { return a + 0 } //go:noinline -func add_int8_Neg128_ssa(a int8) int8 { - return a + -128 -} +func add_0_int8(a int8) int8 { return 0 + a } //go:noinline -func add_Neg128_int8_ssa(a int8) int8 { - return -128 + a -} +func add_int8_1(a int8) int8 { return a + 1 } //go:noinline -func add_int8_Neg127_ssa(a int8) int8 { - return a + -127 -} +func add_1_int8(a int8) int8 { return 1 + a } //go:noinline -func add_Neg127_int8_ssa(a int8) int8 { - return -127 + a -} +func add_int8_126(a int8) int8 { return a + 126 } //go:noinline -func add_int8_Neg1_ssa(a int8) int8 { - return a + -1 -} +func add_126_int8(a int8) int8 { return 126 + a } //go:noinline -func add_Neg1_int8_ssa(a int8) int8 { - return -1 + a -} +func add_int8_127(a int8) int8 { return a + 127 } //go:noinline -func add_int8_0_ssa(a int8) int8 { - return a + 0 -} +func add_127_int8(a int8) int8 { return 127 + a } //go:noinline -func add_0_int8_ssa(a int8) int8 { - return 0 + a -} +func sub_int8_Neg128(a int8) int8 { return a - -128 } //go:noinline -func add_int8_1_ssa(a int8) int8 { - return a + 1 -} +func sub_Neg128_int8(a int8) int8 { return -128 - a } //go:noinline -func add_1_int8_ssa(a int8) int8 { - return 1 + a -} +func sub_int8_Neg127(a int8) int8 { return a - -127 } //go:noinline -func add_int8_126_ssa(a int8) int8 { - return a + 126 -} +func sub_Neg127_int8(a int8) int8 { return -127 - a } //go:noinline -func add_126_int8_ssa(a int8) int8 { - return 126 + a -} +func sub_int8_Neg1(a int8) int8 { return a - -1 } //go:noinline -func add_int8_127_ssa(a int8) int8 { - return a + 127 -} +func sub_Neg1_int8(a int8) int8 { return -1 - a } //go:noinline -func add_127_int8_ssa(a int8) int8 { - return 127 + a -} +func sub_int8_0(a int8) int8 { return a - 0 } //go:noinline -func sub_int8_Neg128_ssa(a int8) int8 { - return a - -128 -} +func sub_0_int8(a int8) int8 { return 0 - a } //go:noinline -func sub_Neg128_int8_ssa(a int8) int8 { - return -128 - a -} +func sub_int8_1(a int8) int8 { return a - 1 } //go:noinline -func sub_int8_Neg127_ssa(a int8) int8 { - return a - -127 -} +func sub_1_int8(a int8) int8 { return 1 - a } //go:noinline -func sub_Neg127_int8_ssa(a int8) int8 { - return -127 - a -} +func sub_int8_126(a int8) int8 { return a - 126 } //go:noinline -func sub_int8_Neg1_ssa(a int8) int8 { - return a - -1 -} +func sub_126_int8(a int8) int8 { return 126 - a } //go:noinline -func sub_Neg1_int8_ssa(a int8) int8 { - return -1 - a -} +func sub_int8_127(a int8) int8 { return a - 127 } //go:noinline -func sub_int8_0_ssa(a int8) int8 { - return a - 0 -} +func sub_127_int8(a int8) int8 { return 127 - a } //go:noinline -func sub_0_int8_ssa(a int8) int8 { - return 0 - a -} +func div_int8_Neg128(a int8) int8 { return a / -128 } //go:noinline -func sub_int8_1_ssa(a int8) int8 { - return a - 1 -} +func div_Neg128_int8(a int8) int8 { return -128 / a } //go:noinline -func sub_1_int8_ssa(a int8) int8 { - return 1 - a -} +func div_int8_Neg127(a int8) int8 { return a / -127 } //go:noinline -func sub_int8_126_ssa(a int8) int8 { - return a - 126 -} +func div_Neg127_int8(a int8) int8 { return -127 / a } //go:noinline -func sub_126_int8_ssa(a int8) int8 { - return 126 - a -} +func div_int8_Neg1(a int8) int8 { return a / -1 } //go:noinline -func sub_int8_127_ssa(a int8) int8 { - return a - 127 -} +func div_Neg1_int8(a int8) int8 { return -1 / a } //go:noinline -func sub_127_int8_ssa(a int8) int8 { - return 127 - a -} +func div_0_int8(a int8) int8 { return 0 / a } //go:noinline -func div_int8_Neg128_ssa(a int8) int8 { - return a / -128 -} +func div_int8_1(a int8) int8 { return a / 1 } //go:noinline -func div_Neg128_int8_ssa(a int8) int8 { - return -128 / a -} +func div_1_int8(a int8) int8 { return 1 / a } //go:noinline -func div_int8_Neg127_ssa(a int8) int8 { - return a / -127 -} +func div_int8_126(a int8) int8 { return a / 126 } //go:noinline -func div_Neg127_int8_ssa(a int8) int8 { - return -127 / a -} +func div_126_int8(a int8) int8 { return 126 / a } //go:noinline -func div_int8_Neg1_ssa(a int8) int8 { - return a / -1 -} +func div_int8_127(a int8) int8 { return a / 127 } //go:noinline -func div_Neg1_int8_ssa(a int8) int8 { - return -1 / a -} +func div_127_int8(a int8) int8 { return 127 / a } //go:noinline -func div_0_int8_ssa(a int8) int8 { - return 0 / a -} +func mul_int8_Neg128(a int8) int8 { return a * -128 } //go:noinline -func div_int8_1_ssa(a int8) int8 { - return a / 1 -} +func mul_Neg128_int8(a int8) int8 { return -128 * a } //go:noinline -func div_1_int8_ssa(a int8) int8 { - return 1 / a -} +func mul_int8_Neg127(a int8) int8 { return a * -127 } //go:noinline -func div_int8_126_ssa(a int8) int8 { - return a / 126 -} +func mul_Neg127_int8(a int8) int8 { return -127 * a } //go:noinline -func div_126_int8_ssa(a int8) int8 { - return 126 / a -} +func mul_int8_Neg1(a int8) int8 { return a * -1 } //go:noinline -func div_int8_127_ssa(a int8) int8 { - return a / 127 -} +func mul_Neg1_int8(a int8) int8 { return -1 * a } //go:noinline -func div_127_int8_ssa(a int8) int8 { - return 127 / a -} +func mul_int8_0(a int8) int8 { return a * 0 } //go:noinline -func mul_int8_Neg128_ssa(a int8) int8 { - return a * -128 -} +func mul_0_int8(a int8) int8 { return 0 * a } //go:noinline -func mul_Neg128_int8_ssa(a int8) int8 { - return -128 * a -} +func mul_int8_1(a int8) int8 { return a * 1 } //go:noinline -func mul_int8_Neg127_ssa(a int8) int8 { - return a * -127 -} +func mul_1_int8(a int8) int8 { return 1 * a } //go:noinline -func mul_Neg127_int8_ssa(a int8) int8 { - return -127 * a -} +func mul_int8_126(a int8) int8 { return a * 126 } //go:noinline -func mul_int8_Neg1_ssa(a int8) int8 { - return a * -1 -} +func mul_126_int8(a int8) int8 { return 126 * a } //go:noinline -func mul_Neg1_int8_ssa(a int8) int8 { - return -1 * a -} +func mul_int8_127(a int8) int8 { return a * 127 } //go:noinline -func mul_int8_0_ssa(a int8) int8 { - return a * 0 -} +func mul_127_int8(a int8) int8 { return 127 * a } //go:noinline -func mul_0_int8_ssa(a int8) int8 { - return 0 * a -} +func mod_int8_Neg128(a int8) int8 { return a % -128 } //go:noinline -func mul_int8_1_ssa(a int8) int8 { - return a * 1 -} +func mod_Neg128_int8(a int8) int8 { return -128 % a } //go:noinline -func mul_1_int8_ssa(a int8) int8 { - return 1 * a -} +func mod_int8_Neg127(a int8) int8 { return a % -127 } //go:noinline -func mul_int8_126_ssa(a int8) int8 { - return a * 126 -} +func mod_Neg127_int8(a int8) int8 { return -127 % a } //go:noinline -func mul_126_int8_ssa(a int8) int8 { - return 126 * a -} +func mod_int8_Neg1(a int8) int8 { return a % -1 } //go:noinline -func mul_int8_127_ssa(a int8) int8 { - return a * 127 -} +func mod_Neg1_int8(a int8) int8 { return -1 % a } //go:noinline -func mul_127_int8_ssa(a int8) int8 { - return 127 * a -} +func mod_0_int8(a int8) int8 { return 0 % a } //go:noinline -func mod_int8_Neg128_ssa(a int8) int8 { - return a % -128 -} +func mod_int8_1(a int8) int8 { return a % 1 } //go:noinline -func mod_Neg128_int8_ssa(a int8) int8 { - return -128 % a -} +func mod_1_int8(a int8) int8 { return 1 % a } //go:noinline -func mod_int8_Neg127_ssa(a int8) int8 { - return a % -127 -} +func mod_int8_126(a int8) int8 { return a % 126 } //go:noinline -func mod_Neg127_int8_ssa(a int8) int8 { - return -127 % a -} +func mod_126_int8(a int8) int8 { return 126 % a } //go:noinline -func mod_int8_Neg1_ssa(a int8) int8 { - return a % -1 -} +func mod_int8_127(a int8) int8 { return a % 127 } //go:noinline -func mod_Neg1_int8_ssa(a int8) int8 { - return -1 % a -} +func mod_127_int8(a int8) int8 { return 127 % a } //go:noinline -func mod_0_int8_ssa(a int8) int8 { - return 0 % a -} +func and_int8_Neg128(a int8) int8 { return a & -128 } //go:noinline -func mod_int8_1_ssa(a int8) int8 { - return a % 1 -} +func and_Neg128_int8(a int8) int8 { return -128 & a } //go:noinline -func mod_1_int8_ssa(a int8) int8 { - return 1 % a -} +func and_int8_Neg127(a int8) int8 { return a & -127 } //go:noinline -func mod_int8_126_ssa(a int8) int8 { - return a % 126 -} +func and_Neg127_int8(a int8) int8 { return -127 & a } //go:noinline -func mod_126_int8_ssa(a int8) int8 { - return 126 % a -} +func and_int8_Neg1(a int8) int8 { return a & -1 } //go:noinline -func mod_int8_127_ssa(a int8) int8 { - return a % 127 -} +func and_Neg1_int8(a int8) int8 { return -1 & a } //go:noinline -func mod_127_int8_ssa(a int8) int8 { - return 127 % a -} +func and_int8_0(a int8) int8 { return a & 0 } //go:noinline -func and_int8_Neg128_ssa(a int8) int8 { - return a & -128 -} +func and_0_int8(a int8) int8 { return 0 & a } //go:noinline -func and_Neg128_int8_ssa(a int8) int8 { - return -128 & a -} +func and_int8_1(a int8) int8 { return a & 1 } //go:noinline -func and_int8_Neg127_ssa(a int8) int8 { - return a & -127 -} +func and_1_int8(a int8) int8 { return 1 & a } //go:noinline -func and_Neg127_int8_ssa(a int8) int8 { - return -127 & a -} +func and_int8_126(a int8) int8 { return a & 126 } //go:noinline -func and_int8_Neg1_ssa(a int8) int8 { - return a & -1 -} +func and_126_int8(a int8) int8 { return 126 & a } //go:noinline -func and_Neg1_int8_ssa(a int8) int8 { - return -1 & a -} +func and_int8_127(a int8) int8 { return a & 127 } //go:noinline -func and_int8_0_ssa(a int8) int8 { - return a & 0 -} +func and_127_int8(a int8) int8 { return 127 & a } //go:noinline -func and_0_int8_ssa(a int8) int8 { - return 0 & a -} +func or_int8_Neg128(a int8) int8 { return a | -128 } //go:noinline -func and_int8_1_ssa(a int8) int8 { - return a & 1 -} +func or_Neg128_int8(a int8) int8 { return -128 | a } //go:noinline -func and_1_int8_ssa(a int8) int8 { - return 1 & a -} +func or_int8_Neg127(a int8) int8 { return a | -127 } //go:noinline -func and_int8_126_ssa(a int8) int8 { - return a & 126 -} +func or_Neg127_int8(a int8) int8 { return -127 | a } //go:noinline -func and_126_int8_ssa(a int8) int8 { - return 126 & a -} +func or_int8_Neg1(a int8) int8 { return a | -1 } //go:noinline -func and_int8_127_ssa(a int8) int8 { - return a & 127 -} +func or_Neg1_int8(a int8) int8 { return -1 | a } //go:noinline -func and_127_int8_ssa(a int8) int8 { - return 127 & a -} +func or_int8_0(a int8) int8 { return a | 0 } //go:noinline -func or_int8_Neg128_ssa(a int8) int8 { - return a | -128 -} +func or_0_int8(a int8) int8 { return 0 | a } //go:noinline -func or_Neg128_int8_ssa(a int8) int8 { - return -128 | a -} +func or_int8_1(a int8) int8 { return a | 1 } //go:noinline -func or_int8_Neg127_ssa(a int8) int8 { - return a | -127 -} +func or_1_int8(a int8) int8 { return 1 | a } //go:noinline -func or_Neg127_int8_ssa(a int8) int8 { - return -127 | a -} +func or_int8_126(a int8) int8 { return a | 126 } //go:noinline -func or_int8_Neg1_ssa(a int8) int8 { - return a | -1 -} +func or_126_int8(a int8) int8 { return 126 | a } //go:noinline -func or_Neg1_int8_ssa(a int8) int8 { - return -1 | a -} +func or_int8_127(a int8) int8 { return a | 127 } //go:noinline -func or_int8_0_ssa(a int8) int8 { - return a | 0 -} +func or_127_int8(a int8) int8 { return 127 | a } //go:noinline -func or_0_int8_ssa(a int8) int8 { - return 0 | a -} +func xor_int8_Neg128(a int8) int8 { return a ^ -128 } //go:noinline -func or_int8_1_ssa(a int8) int8 { - return a | 1 -} +func xor_Neg128_int8(a int8) int8 { return -128 ^ a } //go:noinline -func or_1_int8_ssa(a int8) int8 { - return 1 | a -} +func xor_int8_Neg127(a int8) int8 { return a ^ -127 } //go:noinline -func or_int8_126_ssa(a int8) int8 { - return a | 126 -} +func xor_Neg127_int8(a int8) int8 { return -127 ^ a } //go:noinline -func or_126_int8_ssa(a int8) int8 { - return 126 | a -} +func xor_int8_Neg1(a int8) int8 { return a ^ -1 } //go:noinline -func or_int8_127_ssa(a int8) int8 { - return a | 127 -} +func xor_Neg1_int8(a int8) int8 { return -1 ^ a } //go:noinline -func or_127_int8_ssa(a int8) int8 { - return 127 | a -} +func xor_int8_0(a int8) int8 { return a ^ 0 } //go:noinline -func xor_int8_Neg128_ssa(a int8) int8 { - return a ^ -128 -} +func xor_0_int8(a int8) int8 { return 0 ^ a } //go:noinline -func xor_Neg128_int8_ssa(a int8) int8 { - return -128 ^ a -} +func xor_int8_1(a int8) int8 { return a ^ 1 } //go:noinline -func xor_int8_Neg127_ssa(a int8) int8 { - return a ^ -127 -} +func xor_1_int8(a int8) int8 { return 1 ^ a } //go:noinline -func xor_Neg127_int8_ssa(a int8) int8 { - return -127 ^ a -} +func xor_int8_126(a int8) int8 { return a ^ 126 } //go:noinline -func xor_int8_Neg1_ssa(a int8) int8 { - return a ^ -1 -} +func xor_126_int8(a int8) int8 { return 126 ^ a } //go:noinline -func xor_Neg1_int8_ssa(a int8) int8 { - return -1 ^ a -} +func xor_int8_127(a int8) int8 { return a ^ 127 } //go:noinline -func xor_int8_0_ssa(a int8) int8 { - return a ^ 0 +func xor_127_int8(a int8) int8 { return 127 ^ a } + +type test_uint64 struct { + fn func(uint64) uint64 + fnname string + in uint64 + want uint64 } -//go:noinline -func xor_0_int8_ssa(a int8) int8 { - return 0 ^ a +var tests_uint64 = []test_uint64{ + + test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 0, want: 0}, + test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 0, want: 0}, + test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 1, want: 1}, + test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 1, want: 1}, + test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 4294967296, want: 4294967296}, + test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 4294967296, want: 4294967296}, + test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: add_0_uint64, fnname: "add_0_uint64", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: add_uint64_0, fnname: "add_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 0, want: 1}, + test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 0, want: 1}, + test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 1, want: 2}, + test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 1, want: 2}, + test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 4294967296, want: 4294967297}, + test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 4294967296, want: 4294967297}, + test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 9223372036854775808, want: 9223372036854775809}, + test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 9223372036854775808, want: 9223372036854775809}, + test_uint64{fn: add_1_uint64, fnname: "add_1_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: add_uint64_1, fnname: "add_uint64_1", in: 18446744073709551615, want: 0}, + test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 0, want: 4294967296}, + test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 0, want: 4294967296}, + test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 1, want: 4294967297}, + test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 1, want: 4294967297}, + test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 4294967296, want: 8589934592}, + test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 4294967296, want: 8589934592}, + test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 9223372036854775808, want: 9223372041149743104}, + test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 9223372036854775808, want: 9223372041149743104}, + test_uint64{fn: add_4294967296_uint64, fnname: "add_4294967296_uint64", in: 18446744073709551615, want: 4294967295}, + test_uint64{fn: add_uint64_4294967296, fnname: "add_uint64_4294967296", in: 18446744073709551615, want: 4294967295}, + test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, + test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 0, want: 9223372036854775808}, + test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 1, want: 9223372036854775809}, + test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 1, want: 9223372036854775809}, + test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 4294967296, want: 9223372041149743104}, + test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 4294967296, want: 9223372041149743104}, + test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, + test_uint64{fn: add_9223372036854775808_uint64, fnname: "add_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775807}, + test_uint64{fn: add_uint64_9223372036854775808, fnname: "add_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775807}, + test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, + test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 0, want: 18446744073709551615}, + test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 1, want: 0}, + test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 1, want: 0}, + test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 4294967296, want: 4294967295}, + test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 4294967296, want: 4294967295}, + test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775807}, + test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775807}, + test_uint64{fn: add_18446744073709551615_uint64, fnname: "add_18446744073709551615_uint64", in: 18446744073709551615, want: 18446744073709551614}, + test_uint64{fn: add_uint64_18446744073709551615, fnname: "add_uint64_18446744073709551615", in: 18446744073709551615, want: 18446744073709551614}, + test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 0, want: 0}, + test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 0, want: 0}, + test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 1, want: 18446744073709551615}, + test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 1, want: 1}, + test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 4294967296, want: 18446744069414584320}, + test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 4294967296, want: 4294967296}, + test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: sub_0_uint64, fnname: "sub_0_uint64", in: 18446744073709551615, want: 1}, + test_uint64{fn: sub_uint64_0, fnname: "sub_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 0, want: 1}, + test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 0, want: 18446744073709551615}, + test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 1, want: 0}, + test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 1, want: 0}, + test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 4294967296, want: 18446744069414584321}, + test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 4294967296, want: 4294967295}, + test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 9223372036854775808, want: 9223372036854775809}, + test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 9223372036854775808, want: 9223372036854775807}, + test_uint64{fn: sub_1_uint64, fnname: "sub_1_uint64", in: 18446744073709551615, want: 2}, + test_uint64{fn: sub_uint64_1, fnname: "sub_uint64_1", in: 18446744073709551615, want: 18446744073709551614}, + test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 0, want: 4294967296}, + test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 0, want: 18446744069414584320}, + test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 1, want: 4294967295}, + test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 1, want: 18446744069414584321}, + test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 4294967296, want: 0}, + test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 4294967296, want: 0}, + test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 9223372036854775808, want: 9223372041149743104}, + test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 9223372036854775808, want: 9223372032559808512}, + test_uint64{fn: sub_4294967296_uint64, fnname: "sub_4294967296_uint64", in: 18446744073709551615, want: 4294967297}, + test_uint64{fn: sub_uint64_4294967296, fnname: "sub_uint64_4294967296", in: 18446744073709551615, want: 18446744069414584319}, + test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, + test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 0, want: 9223372036854775808}, + test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 1, want: 9223372036854775807}, + test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 1, want: 9223372036854775809}, + test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 4294967296, want: 9223372032559808512}, + test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 4294967296, want: 9223372041149743104}, + test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, + test_uint64{fn: sub_9223372036854775808_uint64, fnname: "sub_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775809}, + test_uint64{fn: sub_uint64_9223372036854775808, fnname: "sub_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775807}, + test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, + test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 0, want: 1}, + test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 1, want: 18446744073709551614}, + test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 1, want: 2}, + test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 4294967296, want: 18446744069414584319}, + test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 4294967296, want: 4294967297}, + test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775807}, + test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775809}, + test_uint64{fn: sub_18446744073709551615_uint64, fnname: "sub_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: sub_uint64_18446744073709551615, fnname: "sub_uint64_18446744073709551615", in: 18446744073709551615, want: 0}, + test_uint64{fn: div_0_uint64, fnname: "div_0_uint64", in: 1, want: 0}, + test_uint64{fn: div_0_uint64, fnname: "div_0_uint64", in: 4294967296, want: 0}, + test_uint64{fn: div_0_uint64, fnname: "div_0_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: div_0_uint64, fnname: "div_0_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 0, want: 0}, + test_uint64{fn: div_1_uint64, fnname: "div_1_uint64", in: 1, want: 1}, + test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 1, want: 1}, + test_uint64{fn: div_1_uint64, fnname: "div_1_uint64", in: 4294967296, want: 0}, + test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 4294967296, want: 4294967296}, + test_uint64{fn: div_1_uint64, fnname: "div_1_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: div_1_uint64, fnname: "div_1_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: div_uint64_1, fnname: "div_uint64_1", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 0, want: 0}, + test_uint64{fn: div_4294967296_uint64, fnname: "div_4294967296_uint64", in: 1, want: 4294967296}, + test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 1, want: 0}, + test_uint64{fn: div_4294967296_uint64, fnname: "div_4294967296_uint64", in: 4294967296, want: 1}, + test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 4294967296, want: 1}, + test_uint64{fn: div_4294967296_uint64, fnname: "div_4294967296_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 9223372036854775808, want: 2147483648}, + test_uint64{fn: div_4294967296_uint64, fnname: "div_4294967296_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: div_uint64_4294967296, fnname: "div_uint64_4294967296", in: 18446744073709551615, want: 4294967295}, + test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 0, want: 0}, + test_uint64{fn: div_9223372036854775808_uint64, fnname: "div_9223372036854775808_uint64", in: 1, want: 9223372036854775808}, + test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 1, want: 0}, + test_uint64{fn: div_9223372036854775808_uint64, fnname: "div_9223372036854775808_uint64", in: 4294967296, want: 2147483648}, + test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 4294967296, want: 0}, + test_uint64{fn: div_9223372036854775808_uint64, fnname: "div_9223372036854775808_uint64", in: 9223372036854775808, want: 1}, + test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 9223372036854775808, want: 1}, + test_uint64{fn: div_9223372036854775808_uint64, fnname: "div_9223372036854775808_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: div_uint64_9223372036854775808, fnname: "div_uint64_9223372036854775808", in: 18446744073709551615, want: 1}, + test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 0, want: 0}, + test_uint64{fn: div_18446744073709551615_uint64, fnname: "div_18446744073709551615_uint64", in: 1, want: 18446744073709551615}, + test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 1, want: 0}, + test_uint64{fn: div_18446744073709551615_uint64, fnname: "div_18446744073709551615_uint64", in: 4294967296, want: 4294967295}, + test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 4294967296, want: 0}, + test_uint64{fn: div_18446744073709551615_uint64, fnname: "div_18446744073709551615_uint64", in: 9223372036854775808, want: 1}, + test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 9223372036854775808, want: 0}, + test_uint64{fn: div_18446744073709551615_uint64, fnname: "div_18446744073709551615_uint64", in: 18446744073709551615, want: 1}, + test_uint64{fn: div_uint64_18446744073709551615, fnname: "div_uint64_18446744073709551615", in: 18446744073709551615, want: 1}, + test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 0, want: 0}, + test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 0, want: 0}, + test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 1, want: 0}, + test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 1, want: 0}, + test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 4294967296, want: 0}, + test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 4294967296, want: 0}, + test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 9223372036854775808, want: 0}, + test_uint64{fn: mul_0_uint64, fnname: "mul_0_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: mul_uint64_0, fnname: "mul_uint64_0", in: 18446744073709551615, want: 0}, + test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 0, want: 0}, + test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 0, want: 0}, + test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 1, want: 1}, + test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 1, want: 1}, + test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 4294967296, want: 4294967296}, + test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 4294967296, want: 4294967296}, + test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: mul_1_uint64, fnname: "mul_1_uint64", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: mul_uint64_1, fnname: "mul_uint64_1", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 0, want: 0}, + test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 0, want: 0}, + test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 1, want: 4294967296}, + test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 1, want: 4294967296}, + test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 4294967296, want: 0}, + test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 4294967296, want: 0}, + test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 9223372036854775808, want: 0}, + test_uint64{fn: mul_4294967296_uint64, fnname: "mul_4294967296_uint64", in: 18446744073709551615, want: 18446744069414584320}, + test_uint64{fn: mul_uint64_4294967296, fnname: "mul_uint64_4294967296", in: 18446744073709551615, want: 18446744069414584320}, + test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 0, want: 0}, + test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 0, want: 0}, + test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 1, want: 9223372036854775808}, + test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 1, want: 9223372036854775808}, + test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 4294967296, want: 0}, + test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 4294967296, want: 0}, + test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, + test_uint64{fn: mul_9223372036854775808_uint64, fnname: "mul_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775808}, + test_uint64{fn: mul_uint64_9223372036854775808, fnname: "mul_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775808}, + test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 0, want: 0}, + test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 0, want: 0}, + test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 1, want: 18446744073709551615}, + test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 1, want: 18446744073709551615}, + test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 4294967296, want: 18446744069414584320}, + test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 4294967296, want: 18446744069414584320}, + test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: mul_18446744073709551615_uint64, fnname: "mul_18446744073709551615_uint64", in: 18446744073709551615, want: 1}, + test_uint64{fn: mul_uint64_18446744073709551615, fnname: "mul_uint64_18446744073709551615", in: 18446744073709551615, want: 1}, + test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 0, want: 0}, + test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 0, want: 0}, + test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 1, want: 0}, + test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 1, want: 1}, + test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 4294967296, want: 0}, + test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 4294967296, want: 4294967296}, + test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: lsh_0_uint64, fnname: "lsh_0_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: lsh_uint64_0, fnname: "lsh_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 0, want: 1}, + test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 0, want: 0}, + test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 1, want: 2}, + test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 1, want: 2}, + test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 4294967296, want: 0}, + test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 4294967296, want: 8589934592}, + test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 9223372036854775808, want: 0}, + test_uint64{fn: lsh_1_uint64, fnname: "lsh_1_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: lsh_uint64_1, fnname: "lsh_uint64_1", in: 18446744073709551615, want: 18446744073709551614}, + test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 0, want: 4294967296}, + test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 0, want: 0}, + test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 1, want: 8589934592}, + test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 1, want: 0}, + test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 4294967296, want: 0}, + test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 4294967296, want: 0}, + test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 9223372036854775808, want: 0}, + test_uint64{fn: lsh_4294967296_uint64, fnname: "lsh_4294967296_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: lsh_uint64_4294967296, fnname: "lsh_uint64_4294967296", in: 18446744073709551615, want: 0}, + test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, + test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 0, want: 0}, + test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 1, want: 0}, + test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 1, want: 0}, + test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 4294967296, want: 0}, + test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 4294967296, want: 0}, + test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, + test_uint64{fn: lsh_9223372036854775808_uint64, fnname: "lsh_9223372036854775808_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: lsh_uint64_9223372036854775808, fnname: "lsh_uint64_9223372036854775808", in: 18446744073709551615, want: 0}, + test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, + test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 0, want: 0}, + test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 1, want: 18446744073709551614}, + test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 1, want: 0}, + test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 4294967296, want: 0}, + test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 4294967296, want: 0}, + test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 9223372036854775808, want: 0}, + test_uint64{fn: lsh_18446744073709551615_uint64, fnname: "lsh_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: lsh_uint64_18446744073709551615, fnname: "lsh_uint64_18446744073709551615", in: 18446744073709551615, want: 0}, + test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 0, want: 0}, + test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 0, want: 0}, + test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 1, want: 0}, + test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 1, want: 1}, + test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 4294967296, want: 0}, + test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 4294967296, want: 4294967296}, + test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: rsh_0_uint64, fnname: "rsh_0_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: rsh_uint64_0, fnname: "rsh_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 0, want: 1}, + test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 0, want: 0}, + test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 1, want: 0}, + test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 1, want: 0}, + test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 4294967296, want: 0}, + test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 4294967296, want: 2147483648}, + test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 9223372036854775808, want: 4611686018427387904}, + test_uint64{fn: rsh_1_uint64, fnname: "rsh_1_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: rsh_uint64_1, fnname: "rsh_uint64_1", in: 18446744073709551615, want: 9223372036854775807}, + test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 0, want: 4294967296}, + test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 0, want: 0}, + test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 1, want: 2147483648}, + test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 1, want: 0}, + test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 4294967296, want: 0}, + test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 4294967296, want: 0}, + test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 9223372036854775808, want: 0}, + test_uint64{fn: rsh_4294967296_uint64, fnname: "rsh_4294967296_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: rsh_uint64_4294967296, fnname: "rsh_uint64_4294967296", in: 18446744073709551615, want: 0}, + test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, + test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 0, want: 0}, + test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 1, want: 4611686018427387904}, + test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 1, want: 0}, + test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 4294967296, want: 0}, + test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 4294967296, want: 0}, + test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, + test_uint64{fn: rsh_9223372036854775808_uint64, fnname: "rsh_9223372036854775808_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: rsh_uint64_9223372036854775808, fnname: "rsh_uint64_9223372036854775808", in: 18446744073709551615, want: 0}, + test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, + test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 0, want: 0}, + test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 1, want: 9223372036854775807}, + test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 1, want: 0}, + test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 4294967296, want: 0}, + test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 4294967296, want: 0}, + test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 9223372036854775808, want: 0}, + test_uint64{fn: rsh_18446744073709551615_uint64, fnname: "rsh_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: rsh_uint64_18446744073709551615, fnname: "rsh_uint64_18446744073709551615", in: 18446744073709551615, want: 0}, + test_uint64{fn: mod_0_uint64, fnname: "mod_0_uint64", in: 1, want: 0}, + test_uint64{fn: mod_0_uint64, fnname: "mod_0_uint64", in: 4294967296, want: 0}, + test_uint64{fn: mod_0_uint64, fnname: "mod_0_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: mod_0_uint64, fnname: "mod_0_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 0, want: 0}, + test_uint64{fn: mod_1_uint64, fnname: "mod_1_uint64", in: 1, want: 0}, + test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 1, want: 0}, + test_uint64{fn: mod_1_uint64, fnname: "mod_1_uint64", in: 4294967296, want: 1}, + test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 4294967296, want: 0}, + test_uint64{fn: mod_1_uint64, fnname: "mod_1_uint64", in: 9223372036854775808, want: 1}, + test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 9223372036854775808, want: 0}, + test_uint64{fn: mod_1_uint64, fnname: "mod_1_uint64", in: 18446744073709551615, want: 1}, + test_uint64{fn: mod_uint64_1, fnname: "mod_uint64_1", in: 18446744073709551615, want: 0}, + test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 0, want: 0}, + test_uint64{fn: mod_4294967296_uint64, fnname: "mod_4294967296_uint64", in: 1, want: 0}, + test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 1, want: 1}, + test_uint64{fn: mod_4294967296_uint64, fnname: "mod_4294967296_uint64", in: 4294967296, want: 0}, + test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 4294967296, want: 0}, + test_uint64{fn: mod_4294967296_uint64, fnname: "mod_4294967296_uint64", in: 9223372036854775808, want: 4294967296}, + test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 9223372036854775808, want: 0}, + test_uint64{fn: mod_4294967296_uint64, fnname: "mod_4294967296_uint64", in: 18446744073709551615, want: 4294967296}, + test_uint64{fn: mod_uint64_4294967296, fnname: "mod_uint64_4294967296", in: 18446744073709551615, want: 4294967295}, + test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 0, want: 0}, + test_uint64{fn: mod_9223372036854775808_uint64, fnname: "mod_9223372036854775808_uint64", in: 1, want: 0}, + test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 1, want: 1}, + test_uint64{fn: mod_9223372036854775808_uint64, fnname: "mod_9223372036854775808_uint64", in: 4294967296, want: 0}, + test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 4294967296, want: 4294967296}, + test_uint64{fn: mod_9223372036854775808_uint64, fnname: "mod_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, + test_uint64{fn: mod_9223372036854775808_uint64, fnname: "mod_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775808}, + test_uint64{fn: mod_uint64_9223372036854775808, fnname: "mod_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775807}, + test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 0, want: 0}, + test_uint64{fn: mod_18446744073709551615_uint64, fnname: "mod_18446744073709551615_uint64", in: 1, want: 0}, + test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 1, want: 1}, + test_uint64{fn: mod_18446744073709551615_uint64, fnname: "mod_18446744073709551615_uint64", in: 4294967296, want: 4294967295}, + test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 4294967296, want: 4294967296}, + test_uint64{fn: mod_18446744073709551615_uint64, fnname: "mod_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775807}, + test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: mod_18446744073709551615_uint64, fnname: "mod_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: mod_uint64_18446744073709551615, fnname: "mod_uint64_18446744073709551615", in: 18446744073709551615, want: 0}, + test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 0, want: 0}, + test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 0, want: 0}, + test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 1, want: 0}, + test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 1, want: 0}, + test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 4294967296, want: 0}, + test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 4294967296, want: 0}, + test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 9223372036854775808, want: 0}, + test_uint64{fn: and_0_uint64, fnname: "and_0_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: and_uint64_0, fnname: "and_uint64_0", in: 18446744073709551615, want: 0}, + test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 0, want: 0}, + test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 0, want: 0}, + test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 1, want: 1}, + test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 1, want: 1}, + test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 4294967296, want: 0}, + test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 4294967296, want: 0}, + test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 9223372036854775808, want: 0}, + test_uint64{fn: and_1_uint64, fnname: "and_1_uint64", in: 18446744073709551615, want: 1}, + test_uint64{fn: and_uint64_1, fnname: "and_uint64_1", in: 18446744073709551615, want: 1}, + test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 0, want: 0}, + test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 0, want: 0}, + test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 1, want: 0}, + test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 1, want: 0}, + test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 4294967296, want: 4294967296}, + test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 4294967296, want: 4294967296}, + test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 9223372036854775808, want: 0}, + test_uint64{fn: and_4294967296_uint64, fnname: "and_4294967296_uint64", in: 18446744073709551615, want: 4294967296}, + test_uint64{fn: and_uint64_4294967296, fnname: "and_uint64_4294967296", in: 18446744073709551615, want: 4294967296}, + test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 0, want: 0}, + test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 0, want: 0}, + test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 1, want: 0}, + test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 1, want: 0}, + test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 4294967296, want: 0}, + test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 4294967296, want: 0}, + test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: and_9223372036854775808_uint64, fnname: "and_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775808}, + test_uint64{fn: and_uint64_9223372036854775808, fnname: "and_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775808}, + test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 0, want: 0}, + test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 0, want: 0}, + test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 1, want: 1}, + test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 1, want: 1}, + test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 4294967296, want: 4294967296}, + test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 4294967296, want: 4294967296}, + test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: and_18446744073709551615_uint64, fnname: "and_18446744073709551615_uint64", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: and_uint64_18446744073709551615, fnname: "and_uint64_18446744073709551615", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 0, want: 0}, + test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 0, want: 0}, + test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 1, want: 1}, + test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 1, want: 1}, + test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 4294967296, want: 4294967296}, + test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 4294967296, want: 4294967296}, + test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: or_0_uint64, fnname: "or_0_uint64", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: or_uint64_0, fnname: "or_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 0, want: 1}, + test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 0, want: 1}, + test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 1, want: 1}, + test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 1, want: 1}, + test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 4294967296, want: 4294967297}, + test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 4294967296, want: 4294967297}, + test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 9223372036854775808, want: 9223372036854775809}, + test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 9223372036854775808, want: 9223372036854775809}, + test_uint64{fn: or_1_uint64, fnname: "or_1_uint64", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: or_uint64_1, fnname: "or_uint64_1", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 0, want: 4294967296}, + test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 0, want: 4294967296}, + test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 1, want: 4294967297}, + test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 1, want: 4294967297}, + test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 4294967296, want: 4294967296}, + test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 4294967296, want: 4294967296}, + test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 9223372036854775808, want: 9223372041149743104}, + test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 9223372036854775808, want: 9223372041149743104}, + test_uint64{fn: or_4294967296_uint64, fnname: "or_4294967296_uint64", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: or_uint64_4294967296, fnname: "or_uint64_4294967296", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, + test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 0, want: 9223372036854775808}, + test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 1, want: 9223372036854775809}, + test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 1, want: 9223372036854775809}, + test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 4294967296, want: 9223372041149743104}, + test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 4294967296, want: 9223372041149743104}, + test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: or_9223372036854775808_uint64, fnname: "or_9223372036854775808_uint64", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: or_uint64_9223372036854775808, fnname: "or_uint64_9223372036854775808", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, + test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 0, want: 18446744073709551615}, + test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 1, want: 18446744073709551615}, + test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 1, want: 18446744073709551615}, + test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 4294967296, want: 18446744073709551615}, + test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 4294967296, want: 18446744073709551615}, + test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 9223372036854775808, want: 18446744073709551615}, + test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 9223372036854775808, want: 18446744073709551615}, + test_uint64{fn: or_18446744073709551615_uint64, fnname: "or_18446744073709551615_uint64", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: or_uint64_18446744073709551615, fnname: "or_uint64_18446744073709551615", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 0, want: 0}, + test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 0, want: 0}, + test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 1, want: 1}, + test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 1, want: 1}, + test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 4294967296, want: 4294967296}, + test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 4294967296, want: 4294967296}, + test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 9223372036854775808, want: 9223372036854775808}, + test_uint64{fn: xor_0_uint64, fnname: "xor_0_uint64", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: xor_uint64_0, fnname: "xor_uint64_0", in: 18446744073709551615, want: 18446744073709551615}, + test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 0, want: 1}, + test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 0, want: 1}, + test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 1, want: 0}, + test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 1, want: 0}, + test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 4294967296, want: 4294967297}, + test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 4294967296, want: 4294967297}, + test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 9223372036854775808, want: 9223372036854775809}, + test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 9223372036854775808, want: 9223372036854775809}, + test_uint64{fn: xor_1_uint64, fnname: "xor_1_uint64", in: 18446744073709551615, want: 18446744073709551614}, + test_uint64{fn: xor_uint64_1, fnname: "xor_uint64_1", in: 18446744073709551615, want: 18446744073709551614}, + test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 0, want: 4294967296}, + test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 0, want: 4294967296}, + test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 1, want: 4294967297}, + test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 1, want: 4294967297}, + test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 4294967296, want: 0}, + test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 4294967296, want: 0}, + test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 9223372036854775808, want: 9223372041149743104}, + test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 9223372036854775808, want: 9223372041149743104}, + test_uint64{fn: xor_4294967296_uint64, fnname: "xor_4294967296_uint64", in: 18446744073709551615, want: 18446744069414584319}, + test_uint64{fn: xor_uint64_4294967296, fnname: "xor_uint64_4294967296", in: 18446744073709551615, want: 18446744069414584319}, + test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 0, want: 9223372036854775808}, + test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 0, want: 9223372036854775808}, + test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 1, want: 9223372036854775809}, + test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 1, want: 9223372036854775809}, + test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 4294967296, want: 9223372041149743104}, + test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 4294967296, want: 9223372041149743104}, + test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 9223372036854775808, want: 0}, + test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 9223372036854775808, want: 0}, + test_uint64{fn: xor_9223372036854775808_uint64, fnname: "xor_9223372036854775808_uint64", in: 18446744073709551615, want: 9223372036854775807}, + test_uint64{fn: xor_uint64_9223372036854775808, fnname: "xor_uint64_9223372036854775808", in: 18446744073709551615, want: 9223372036854775807}, + test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 0, want: 18446744073709551615}, + test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 0, want: 18446744073709551615}, + test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 1, want: 18446744073709551614}, + test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 1, want: 18446744073709551614}, + test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 4294967296, want: 18446744069414584319}, + test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 4294967296, want: 18446744069414584319}, + test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 9223372036854775808, want: 9223372036854775807}, + test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 9223372036854775808, want: 9223372036854775807}, + test_uint64{fn: xor_18446744073709551615_uint64, fnname: "xor_18446744073709551615_uint64", in: 18446744073709551615, want: 0}, + test_uint64{fn: xor_uint64_18446744073709551615, fnname: "xor_uint64_18446744073709551615", in: 18446744073709551615, want: 0}} + +type test_int64 struct { + fn func(int64) int64 + fnname string + in int64 + want int64 } + +var tests_int64 = []test_int64{ -//go:noinline -func xor_int8_1_ssa(a int8) int8 { - return a ^ 1 + test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, + test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: -9223372036854775807, want: 1}, + test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: -9223372036854775807, want: 1}, + test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: -4294967296, want: 9223372032559808512}, + test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: -4294967296, want: 9223372032559808512}, + test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: -1, want: 9223372036854775807}, + test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: -1, want: 9223372036854775807}, + test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 0, want: -9223372036854775808}, + test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 0, want: -9223372036854775808}, + test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 1, want: -9223372036854775807}, + test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 1, want: -9223372036854775807}, + test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 4294967296, want: -9223372032559808512}, + test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 4294967296, want: -9223372032559808512}, + test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 9223372036854775806, want: -2}, + test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 9223372036854775806, want: -2}, + test_int64{fn: add_Neg9223372036854775808_int64, fnname: "add_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, + test_int64{fn: add_int64_Neg9223372036854775808, fnname: "add_int64_Neg9223372036854775808", in: 9223372036854775807, want: -1}, + test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: -9223372036854775808, want: 1}, + test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: -9223372036854775808, want: 1}, + test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: -9223372036854775807, want: 2}, + test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: -9223372036854775807, want: 2}, + test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: -4294967296, want: 9223372032559808513}, + test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: -4294967296, want: 9223372032559808513}, + test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: -1, want: -9223372036854775808}, + test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: -1, want: -9223372036854775808}, + test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 0, want: -9223372036854775807}, + test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 0, want: -9223372036854775807}, + test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 1, want: -9223372036854775806}, + test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 1, want: -9223372036854775806}, + test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 4294967296, want: -9223372032559808511}, + test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 4294967296, want: -9223372032559808511}, + test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, + test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 9223372036854775806, want: -1}, + test_int64{fn: add_Neg9223372036854775807_int64, fnname: "add_Neg9223372036854775807_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: add_int64_Neg9223372036854775807, fnname: "add_int64_Neg9223372036854775807", in: 9223372036854775807, want: 0}, + test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: -9223372036854775808, want: 9223372032559808512}, + test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: -9223372036854775808, want: 9223372032559808512}, + test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: -9223372036854775807, want: 9223372032559808513}, + test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: -9223372036854775807, want: 9223372032559808513}, + test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: -4294967296, want: -8589934592}, + test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: -4294967296, want: -8589934592}, + test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: -1, want: -4294967297}, + test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: -1, want: -4294967297}, + test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 0, want: -4294967296}, + test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 0, want: -4294967296}, + test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 1, want: -4294967295}, + test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 1, want: -4294967295}, + test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 4294967296, want: 0}, + test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 4294967296, want: 0}, + test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 9223372036854775806, want: 9223372032559808510}, + test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 9223372036854775806, want: 9223372032559808510}, + test_int64{fn: add_Neg4294967296_int64, fnname: "add_Neg4294967296_int64", in: 9223372036854775807, want: 9223372032559808511}, + test_int64{fn: add_int64_Neg4294967296, fnname: "add_int64_Neg4294967296", in: 9223372036854775807, want: 9223372032559808511}, + test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: -9223372036854775808, want: 9223372036854775807}, + test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: -9223372036854775808, want: 9223372036854775807}, + test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: -9223372036854775807, want: -9223372036854775808}, + test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: -9223372036854775807, want: -9223372036854775808}, + test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: -4294967296, want: -4294967297}, + test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: -4294967296, want: -4294967297}, + test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: -1, want: -2}, + test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: -1, want: -2}, + test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 0, want: -1}, + test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 0, want: -1}, + test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 1, want: 0}, + test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 1, want: 0}, + test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 4294967296, want: 4294967295}, + test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 4294967296, want: 4294967295}, + test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 9223372036854775806, want: 9223372036854775805}, + test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 9223372036854775806, want: 9223372036854775805}, + test_int64{fn: add_Neg1_int64, fnname: "add_Neg1_int64", in: 9223372036854775807, want: 9223372036854775806}, + test_int64{fn: add_int64_Neg1, fnname: "add_int64_Neg1", in: 9223372036854775807, want: 9223372036854775806}, + test_int64{fn: add_0_int64, fnname: "add_0_int64", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: add_int64_0, fnname: "add_int64_0", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: add_0_int64, fnname: "add_0_int64", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: add_int64_0, fnname: "add_int64_0", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: add_0_int64, fnname: "add_0_int64", in: -4294967296, want: -4294967296}, + test_int64{fn: add_int64_0, fnname: "add_int64_0", in: -4294967296, want: -4294967296}, + test_int64{fn: add_0_int64, fnname: "add_0_int64", in: -1, want: -1}, + test_int64{fn: add_int64_0, fnname: "add_int64_0", in: -1, want: -1}, + test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 0, want: 0}, + test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 0, want: 0}, + test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 1, want: 1}, + test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 1, want: 1}, + test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 4294967296, want: 4294967296}, + test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 4294967296, want: 4294967296}, + test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: add_0_int64, fnname: "add_0_int64", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: add_int64_0, fnname: "add_int64_0", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: add_1_int64, fnname: "add_1_int64", in: -9223372036854775808, want: -9223372036854775807}, + test_int64{fn: add_int64_1, fnname: "add_int64_1", in: -9223372036854775808, want: -9223372036854775807}, + test_int64{fn: add_1_int64, fnname: "add_1_int64", in: -9223372036854775807, want: -9223372036854775806}, + test_int64{fn: add_int64_1, fnname: "add_int64_1", in: -9223372036854775807, want: -9223372036854775806}, + test_int64{fn: add_1_int64, fnname: "add_1_int64", in: -4294967296, want: -4294967295}, + test_int64{fn: add_int64_1, fnname: "add_int64_1", in: -4294967296, want: -4294967295}, + test_int64{fn: add_1_int64, fnname: "add_1_int64", in: -1, want: 0}, + test_int64{fn: add_int64_1, fnname: "add_int64_1", in: -1, want: 0}, + test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 0, want: 1}, + test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 0, want: 1}, + test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 1, want: 2}, + test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 1, want: 2}, + test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 4294967296, want: 4294967297}, + test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 4294967296, want: 4294967297}, + test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 9223372036854775806, want: 9223372036854775807}, + test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 9223372036854775806, want: 9223372036854775807}, + test_int64{fn: add_1_int64, fnname: "add_1_int64", in: 9223372036854775807, want: -9223372036854775808}, + test_int64{fn: add_int64_1, fnname: "add_int64_1", in: 9223372036854775807, want: -9223372036854775808}, + test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: -9223372036854775808, want: -9223372032559808512}, + test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: -9223372036854775808, want: -9223372032559808512}, + test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: -9223372036854775807, want: -9223372032559808511}, + test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: -9223372036854775807, want: -9223372032559808511}, + test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: -4294967296, want: 0}, + test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: -4294967296, want: 0}, + test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: -1, want: 4294967295}, + test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: -1, want: 4294967295}, + test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 0, want: 4294967296}, + test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 0, want: 4294967296}, + test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 1, want: 4294967297}, + test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 1, want: 4294967297}, + test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 4294967296, want: 8589934592}, + test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 4294967296, want: 8589934592}, + test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 9223372036854775806, want: -9223372032559808514}, + test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 9223372036854775806, want: -9223372032559808514}, + test_int64{fn: add_4294967296_int64, fnname: "add_4294967296_int64", in: 9223372036854775807, want: -9223372032559808513}, + test_int64{fn: add_int64_4294967296, fnname: "add_int64_4294967296", in: 9223372036854775807, want: -9223372032559808513}, + test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: -9223372036854775808, want: -2}, + test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: -9223372036854775808, want: -2}, + test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: -9223372036854775807, want: -1}, + test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: -9223372036854775807, want: -1}, + test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: -4294967296, want: 9223372032559808510}, + test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: -4294967296, want: 9223372032559808510}, + test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: -1, want: 9223372036854775805}, + test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: -1, want: 9223372036854775805}, + test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 0, want: 9223372036854775806}, + test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 0, want: 9223372036854775806}, + test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 1, want: 9223372036854775807}, + test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 1, want: 9223372036854775807}, + test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 4294967296, want: -9223372032559808514}, + test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 4294967296, want: -9223372032559808514}, + test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 9223372036854775806, want: -4}, + test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 9223372036854775806, want: -4}, + test_int64{fn: add_9223372036854775806_int64, fnname: "add_9223372036854775806_int64", in: 9223372036854775807, want: -3}, + test_int64{fn: add_int64_9223372036854775806, fnname: "add_int64_9223372036854775806", in: 9223372036854775807, want: -3}, + test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: -9223372036854775808, want: -1}, + test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: -9223372036854775808, want: -1}, + test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: -9223372036854775807, want: 0}, + test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: -4294967296, want: 9223372032559808511}, + test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: -4294967296, want: 9223372032559808511}, + test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: -1, want: 9223372036854775806}, + test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: -1, want: 9223372036854775806}, + test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 0, want: 9223372036854775807}, + test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 0, want: 9223372036854775807}, + test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 1, want: -9223372036854775808}, + test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 1, want: -9223372036854775808}, + test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 4294967296, want: -9223372032559808513}, + test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 4294967296, want: -9223372032559808513}, + test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 9223372036854775806, want: -3}, + test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 9223372036854775806, want: -3}, + test_int64{fn: add_9223372036854775807_int64, fnname: "add_9223372036854775807_int64", in: 9223372036854775807, want: -2}, + test_int64{fn: add_int64_9223372036854775807, fnname: "add_int64_9223372036854775807", in: 9223372036854775807, want: -2}, + test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, + test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: -9223372036854775807, want: -1}, + test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: -9223372036854775807, want: 1}, + test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: -4294967296, want: -9223372032559808512}, + test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: -4294967296, want: 9223372032559808512}, + test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: -1, want: -9223372036854775807}, + test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: -1, want: 9223372036854775807}, + test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 0, want: -9223372036854775808}, + test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 0, want: -9223372036854775808}, + test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 1, want: 9223372036854775807}, + test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 1, want: -9223372036854775807}, + test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 4294967296, want: 9223372032559808512}, + test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 4294967296, want: -9223372032559808512}, + test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 9223372036854775806, want: 2}, + test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 9223372036854775806, want: -2}, + test_int64{fn: sub_Neg9223372036854775808_int64, fnname: "sub_Neg9223372036854775808_int64", in: 9223372036854775807, want: 1}, + test_int64{fn: sub_int64_Neg9223372036854775808, fnname: "sub_int64_Neg9223372036854775808", in: 9223372036854775807, want: -1}, + test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: -9223372036854775808, want: 1}, + test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: -9223372036854775808, want: -1}, + test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: -9223372036854775807, want: 0}, + test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: -4294967296, want: -9223372032559808511}, + test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: -4294967296, want: 9223372032559808511}, + test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: -1, want: -9223372036854775806}, + test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: -1, want: 9223372036854775806}, + test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 0, want: -9223372036854775807}, + test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 0, want: 9223372036854775807}, + test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 1, want: -9223372036854775808}, + test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 1, want: -9223372036854775808}, + test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 4294967296, want: 9223372032559808513}, + test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 4294967296, want: -9223372032559808513}, + test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 9223372036854775806, want: 3}, + test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 9223372036854775806, want: -3}, + test_int64{fn: sub_Neg9223372036854775807_int64, fnname: "sub_Neg9223372036854775807_int64", in: 9223372036854775807, want: 2}, + test_int64{fn: sub_int64_Neg9223372036854775807, fnname: "sub_int64_Neg9223372036854775807", in: 9223372036854775807, want: -2}, + test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: -9223372036854775808, want: 9223372032559808512}, + test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: -9223372036854775808, want: -9223372032559808512}, + test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: -9223372036854775807, want: 9223372032559808511}, + test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: -9223372036854775807, want: -9223372032559808511}, + test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: -4294967296, want: 0}, + test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: -4294967296, want: 0}, + test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: -1, want: -4294967295}, + test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: -1, want: 4294967295}, + test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 0, want: -4294967296}, + test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 0, want: 4294967296}, + test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 1, want: -4294967297}, + test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 1, want: 4294967297}, + test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 4294967296, want: -8589934592}, + test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 4294967296, want: 8589934592}, + test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 9223372036854775806, want: 9223372032559808514}, + test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 9223372036854775806, want: -9223372032559808514}, + test_int64{fn: sub_Neg4294967296_int64, fnname: "sub_Neg4294967296_int64", in: 9223372036854775807, want: 9223372032559808513}, + test_int64{fn: sub_int64_Neg4294967296, fnname: "sub_int64_Neg4294967296", in: 9223372036854775807, want: -9223372032559808513}, + test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: -9223372036854775808, want: 9223372036854775807}, + test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: -9223372036854775808, want: -9223372036854775807}, + test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: -9223372036854775807, want: 9223372036854775806}, + test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: -9223372036854775807, want: -9223372036854775806}, + test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: -4294967296, want: 4294967295}, + test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: -4294967296, want: -4294967295}, + test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: -1, want: 0}, + test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: -1, want: 0}, + test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 0, want: -1}, + test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 0, want: 1}, + test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 1, want: -2}, + test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 1, want: 2}, + test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 4294967296, want: -4294967297}, + test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 4294967296, want: 4294967297}, + test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 9223372036854775806, want: -9223372036854775807}, + test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 9223372036854775806, want: 9223372036854775807}, + test_int64{fn: sub_Neg1_int64, fnname: "sub_Neg1_int64", in: 9223372036854775807, want: -9223372036854775808}, + test_int64{fn: sub_int64_Neg1, fnname: "sub_int64_Neg1", in: 9223372036854775807, want: -9223372036854775808}, + test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: -9223372036854775807, want: 9223372036854775807}, + test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: -4294967296, want: 4294967296}, + test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: -4294967296, want: -4294967296}, + test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: -1, want: 1}, + test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: -1, want: -1}, + test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 0, want: 0}, + test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 0, want: 0}, + test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 1, want: -1}, + test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 1, want: 1}, + test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 4294967296, want: -4294967296}, + test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 4294967296, want: 4294967296}, + test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 9223372036854775806, want: -9223372036854775806}, + test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: sub_0_int64, fnname: "sub_0_int64", in: 9223372036854775807, want: -9223372036854775807}, + test_int64{fn: sub_int64_0, fnname: "sub_int64_0", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: -9223372036854775808, want: -9223372036854775807}, + test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: -9223372036854775808, want: 9223372036854775807}, + test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: -9223372036854775807, want: -9223372036854775808}, + test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: -9223372036854775807, want: -9223372036854775808}, + test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: -4294967296, want: 4294967297}, + test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: -4294967296, want: -4294967297}, + test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: -1, want: 2}, + test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: -1, want: -2}, + test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 0, want: 1}, + test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 0, want: -1}, + test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 1, want: 0}, + test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 1, want: 0}, + test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 4294967296, want: -4294967295}, + test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 4294967296, want: 4294967295}, + test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 9223372036854775806, want: -9223372036854775805}, + test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 9223372036854775806, want: 9223372036854775805}, + test_int64{fn: sub_1_int64, fnname: "sub_1_int64", in: 9223372036854775807, want: -9223372036854775806}, + test_int64{fn: sub_int64_1, fnname: "sub_int64_1", in: 9223372036854775807, want: 9223372036854775806}, + test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: -9223372036854775808, want: -9223372032559808512}, + test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: -9223372036854775808, want: 9223372032559808512}, + test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: -9223372036854775807, want: -9223372032559808513}, + test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: -9223372036854775807, want: 9223372032559808513}, + test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: -4294967296, want: 8589934592}, + test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: -4294967296, want: -8589934592}, + test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: -1, want: 4294967297}, + test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: -1, want: -4294967297}, + test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 0, want: 4294967296}, + test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 0, want: -4294967296}, + test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 1, want: 4294967295}, + test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 1, want: -4294967295}, + test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 4294967296, want: 0}, + test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 4294967296, want: 0}, + test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 9223372036854775806, want: -9223372032559808510}, + test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 9223372036854775806, want: 9223372032559808510}, + test_int64{fn: sub_4294967296_int64, fnname: "sub_4294967296_int64", in: 9223372036854775807, want: -9223372032559808511}, + test_int64{fn: sub_int64_4294967296, fnname: "sub_int64_4294967296", in: 9223372036854775807, want: 9223372032559808511}, + test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: -9223372036854775808, want: -2}, + test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: -9223372036854775808, want: 2}, + test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: -9223372036854775807, want: -3}, + test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: -9223372036854775807, want: 3}, + test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: -4294967296, want: -9223372032559808514}, + test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: -4294967296, want: 9223372032559808514}, + test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: -1, want: 9223372036854775807}, + test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: -1, want: -9223372036854775807}, + test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 0, want: 9223372036854775806}, + test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 0, want: -9223372036854775806}, + test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 1, want: 9223372036854775805}, + test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 1, want: -9223372036854775805}, + test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 4294967296, want: 9223372032559808510}, + test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 4294967296, want: -9223372032559808510}, + test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 9223372036854775806, want: 0}, + test_int64{fn: sub_9223372036854775806_int64, fnname: "sub_9223372036854775806_int64", in: 9223372036854775807, want: -1}, + test_int64{fn: sub_int64_9223372036854775806, fnname: "sub_int64_9223372036854775806", in: 9223372036854775807, want: 1}, + test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: -9223372036854775808, want: -1}, + test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: -9223372036854775808, want: 1}, + test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: -9223372036854775807, want: -2}, + test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: -9223372036854775807, want: 2}, + test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: -4294967296, want: -9223372032559808513}, + test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: -4294967296, want: 9223372032559808513}, + test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: -1, want: -9223372036854775808}, + test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: -1, want: -9223372036854775808}, + test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 0, want: 9223372036854775807}, + test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 0, want: -9223372036854775807}, + test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 1, want: 9223372036854775806}, + test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 1, want: -9223372036854775806}, + test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 4294967296, want: 9223372032559808511}, + test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 4294967296, want: -9223372032559808511}, + test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 9223372036854775806, want: 1}, + test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 9223372036854775806, want: -1}, + test_int64{fn: sub_9223372036854775807_int64, fnname: "sub_9223372036854775807_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: sub_int64_9223372036854775807, fnname: "sub_int64_9223372036854775807", in: 9223372036854775807, want: 0}, + test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: -9223372036854775808, want: 1}, + test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: -9223372036854775808, want: 1}, + test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: -9223372036854775807, want: 1}, + test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: -9223372036854775807, want: 0}, + test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: -4294967296, want: 2147483648}, + test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: -4294967296, want: 0}, + test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: -1, want: -9223372036854775808}, + test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: -1, want: 0}, + test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 0, want: 0}, + test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: 1, want: -9223372036854775808}, + test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 1, want: 0}, + test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: 4294967296, want: -2147483648}, + test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 4294967296, want: 0}, + test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: 9223372036854775806, want: -1}, + test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 9223372036854775806, want: 0}, + test_int64{fn: div_Neg9223372036854775808_int64, fnname: "div_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, + test_int64{fn: div_int64_Neg9223372036854775808, fnname: "div_int64_Neg9223372036854775808", in: 9223372036854775807, want: 0}, + test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: -9223372036854775808, want: 1}, + test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: -9223372036854775807, want: 1}, + test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: -9223372036854775807, want: 1}, + test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: -4294967296, want: 2147483647}, + test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: -4294967296, want: 0}, + test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: -1, want: 9223372036854775807}, + test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: -1, want: 0}, + test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 0, want: 0}, + test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: 1, want: -9223372036854775807}, + test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 1, want: 0}, + test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: 4294967296, want: -2147483647}, + test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 4294967296, want: 0}, + test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, + test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 9223372036854775806, want: 0}, + test_int64{fn: div_Neg9223372036854775807_int64, fnname: "div_Neg9223372036854775807_int64", in: 9223372036854775807, want: -1}, + test_int64{fn: div_int64_Neg9223372036854775807, fnname: "div_int64_Neg9223372036854775807", in: 9223372036854775807, want: -1}, + test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: -9223372036854775808, want: 2147483648}, + test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: -9223372036854775807, want: 2147483647}, + test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: -4294967296, want: 1}, + test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: -4294967296, want: 1}, + test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: -1, want: 4294967296}, + test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: -1, want: 0}, + test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 0, want: 0}, + test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: 1, want: -4294967296}, + test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 1, want: 0}, + test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: 4294967296, want: -1}, + test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 4294967296, want: -1}, + test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 9223372036854775806, want: -2147483647}, + test_int64{fn: div_Neg4294967296_int64, fnname: "div_Neg4294967296_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: div_int64_Neg4294967296, fnname: "div_int64_Neg4294967296", in: 9223372036854775807, want: -2147483647}, + test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: -9223372036854775807, want: 9223372036854775807}, + test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: -4294967296, want: 0}, + test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: -4294967296, want: 4294967296}, + test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: -1, want: 1}, + test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: -1, want: 1}, + test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 0, want: 0}, + test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: 1, want: -1}, + test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 1, want: -1}, + test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: 4294967296, want: 0}, + test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 4294967296, want: -4294967296}, + test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 9223372036854775806, want: -9223372036854775806}, + test_int64{fn: div_Neg1_int64, fnname: "div_Neg1_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: div_int64_Neg1, fnname: "div_int64_Neg1", in: 9223372036854775807, want: -9223372036854775807}, + test_int64{fn: div_0_int64, fnname: "div_0_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: div_0_int64, fnname: "div_0_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: div_0_int64, fnname: "div_0_int64", in: -4294967296, want: 0}, + test_int64{fn: div_0_int64, fnname: "div_0_int64", in: -1, want: 0}, + test_int64{fn: div_0_int64, fnname: "div_0_int64", in: 1, want: 0}, + test_int64{fn: div_0_int64, fnname: "div_0_int64", in: 4294967296, want: 0}, + test_int64{fn: div_0_int64, fnname: "div_0_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: div_0_int64, fnname: "div_0_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: div_1_int64, fnname: "div_1_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: div_int64_1, fnname: "div_int64_1", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: div_1_int64, fnname: "div_1_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: div_int64_1, fnname: "div_int64_1", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: div_1_int64, fnname: "div_1_int64", in: -4294967296, want: 0}, + test_int64{fn: div_int64_1, fnname: "div_int64_1", in: -4294967296, want: -4294967296}, + test_int64{fn: div_1_int64, fnname: "div_1_int64", in: -1, want: -1}, + test_int64{fn: div_int64_1, fnname: "div_int64_1", in: -1, want: -1}, + test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 0, want: 0}, + test_int64{fn: div_1_int64, fnname: "div_1_int64", in: 1, want: 1}, + test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 1, want: 1}, + test_int64{fn: div_1_int64, fnname: "div_1_int64", in: 4294967296, want: 0}, + test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 4294967296, want: 4294967296}, + test_int64{fn: div_1_int64, fnname: "div_1_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: div_1_int64, fnname: "div_1_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: div_int64_1, fnname: "div_int64_1", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: -9223372036854775808, want: -2147483648}, + test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: -9223372036854775807, want: -2147483647}, + test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: -4294967296, want: -1}, + test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: -4294967296, want: -1}, + test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: -1, want: -4294967296}, + test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: -1, want: 0}, + test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 0, want: 0}, + test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: 1, want: 4294967296}, + test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 1, want: 0}, + test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: 4294967296, want: 1}, + test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 4294967296, want: 1}, + test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 9223372036854775806, want: 2147483647}, + test_int64{fn: div_4294967296_int64, fnname: "div_4294967296_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: div_int64_4294967296, fnname: "div_int64_4294967296", in: 9223372036854775807, want: 2147483647}, + test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: -9223372036854775808, want: -1}, + test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: -9223372036854775807, want: -1}, + test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: -4294967296, want: -2147483647}, + test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: -4294967296, want: 0}, + test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: -1, want: -9223372036854775806}, + test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: -1, want: 0}, + test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 0, want: 0}, + test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: 1, want: 9223372036854775806}, + test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 1, want: 0}, + test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: 4294967296, want: 2147483647}, + test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 4294967296, want: 0}, + test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: 9223372036854775806, want: 1}, + test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 9223372036854775806, want: 1}, + test_int64{fn: div_9223372036854775806_int64, fnname: "div_9223372036854775806_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: div_int64_9223372036854775806, fnname: "div_int64_9223372036854775806", in: 9223372036854775807, want: 1}, + test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: -9223372036854775808, want: -1}, + test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: -9223372036854775807, want: -1}, + test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: -9223372036854775807, want: -1}, + test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: -4294967296, want: -2147483647}, + test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: -4294967296, want: 0}, + test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: -1, want: -9223372036854775807}, + test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: -1, want: 0}, + test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 0, want: 0}, + test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: 1, want: 9223372036854775807}, + test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 1, want: 0}, + test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: 4294967296, want: 2147483647}, + test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 4294967296, want: 0}, + test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: 9223372036854775806, want: 1}, + test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 9223372036854775806, want: 0}, + test_int64{fn: div_9223372036854775807_int64, fnname: "div_9223372036854775807_int64", in: 9223372036854775807, want: 1}, + test_int64{fn: div_int64_9223372036854775807, fnname: "div_int64_9223372036854775807", in: 9223372036854775807, want: 1}, + test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, + test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: -9223372036854775807, want: -9223372036854775808}, + test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: -9223372036854775807, want: -9223372036854775808}, + test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: -4294967296, want: 0}, + test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: -4294967296, want: 0}, + test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: -1, want: -9223372036854775808}, + test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: -1, want: -9223372036854775808}, + test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 0, want: 0}, + test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 0, want: 0}, + test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 1, want: -9223372036854775808}, + test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 1, want: -9223372036854775808}, + test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 4294967296, want: 0}, + test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 4294967296, want: 0}, + test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 9223372036854775806, want: 0}, + test_int64{fn: mul_Neg9223372036854775808_int64, fnname: "mul_Neg9223372036854775808_int64", in: 9223372036854775807, want: -9223372036854775808}, + test_int64{fn: mul_int64_Neg9223372036854775808, fnname: "mul_int64_Neg9223372036854775808", in: 9223372036854775807, want: -9223372036854775808}, + test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: -9223372036854775807, want: 1}, + test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: -9223372036854775807, want: 1}, + test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: -4294967296, want: -4294967296}, + test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: -4294967296, want: -4294967296}, + test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: -1, want: 9223372036854775807}, + test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: -1, want: 9223372036854775807}, + test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 0, want: 0}, + test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 0, want: 0}, + test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 1, want: -9223372036854775807}, + test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 1, want: -9223372036854775807}, + test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 4294967296, want: 4294967296}, + test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 4294967296, want: 4294967296}, + test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: mul_Neg9223372036854775807_int64, fnname: "mul_Neg9223372036854775807_int64", in: 9223372036854775807, want: -1}, + test_int64{fn: mul_int64_Neg9223372036854775807, fnname: "mul_int64_Neg9223372036854775807", in: 9223372036854775807, want: -1}, + test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: -9223372036854775808, want: 0}, + test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: -9223372036854775807, want: -4294967296}, + test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: -9223372036854775807, want: -4294967296}, + test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: -4294967296, want: 0}, + test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: -4294967296, want: 0}, + test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: -1, want: 4294967296}, + test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: -1, want: 4294967296}, + test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 0, want: 0}, + test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 0, want: 0}, + test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 1, want: -4294967296}, + test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 1, want: -4294967296}, + test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 4294967296, want: 0}, + test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 4294967296, want: 0}, + test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 9223372036854775806, want: 8589934592}, + test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 9223372036854775806, want: 8589934592}, + test_int64{fn: mul_Neg4294967296_int64, fnname: "mul_Neg4294967296_int64", in: 9223372036854775807, want: 4294967296}, + test_int64{fn: mul_int64_Neg4294967296, fnname: "mul_int64_Neg4294967296", in: 9223372036854775807, want: 4294967296}, + test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: -9223372036854775807, want: 9223372036854775807}, + test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: -9223372036854775807, want: 9223372036854775807}, + test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: -4294967296, want: 4294967296}, + test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: -4294967296, want: 4294967296}, + test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: -1, want: 1}, + test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: -1, want: 1}, + test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 0, want: 0}, + test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 0, want: 0}, + test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 1, want: -1}, + test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 1, want: -1}, + test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 4294967296, want: -4294967296}, + test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 4294967296, want: -4294967296}, + test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 9223372036854775806, want: -9223372036854775806}, + test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 9223372036854775806, want: -9223372036854775806}, + test_int64{fn: mul_Neg1_int64, fnname: "mul_Neg1_int64", in: 9223372036854775807, want: -9223372036854775807}, + test_int64{fn: mul_int64_Neg1, fnname: "mul_int64_Neg1", in: 9223372036854775807, want: -9223372036854775807}, + test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: -9223372036854775808, want: 0}, + test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: -9223372036854775807, want: 0}, + test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: -4294967296, want: 0}, + test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: -4294967296, want: 0}, + test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: -1, want: 0}, + test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: -1, want: 0}, + test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 0, want: 0}, + test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 0, want: 0}, + test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 1, want: 0}, + test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 1, want: 0}, + test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 4294967296, want: 0}, + test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 4294967296, want: 0}, + test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 9223372036854775806, want: 0}, + test_int64{fn: mul_0_int64, fnname: "mul_0_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: mul_int64_0, fnname: "mul_int64_0", in: 9223372036854775807, want: 0}, + test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: -4294967296, want: -4294967296}, + test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: -4294967296, want: -4294967296}, + test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: -1, want: -1}, + test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: -1, want: -1}, + test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 0, want: 0}, + test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 0, want: 0}, + test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 1, want: 1}, + test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 1, want: 1}, + test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 4294967296, want: 4294967296}, + test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 4294967296, want: 4294967296}, + test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: mul_1_int64, fnname: "mul_1_int64", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: mul_int64_1, fnname: "mul_int64_1", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: -9223372036854775808, want: 0}, + test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: -9223372036854775807, want: 4294967296}, + test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: -9223372036854775807, want: 4294967296}, + test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: -4294967296, want: 0}, + test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: -4294967296, want: 0}, + test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: -1, want: -4294967296}, + test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: -1, want: -4294967296}, + test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 0, want: 0}, + test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 0, want: 0}, + test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 1, want: 4294967296}, + test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 1, want: 4294967296}, + test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 4294967296, want: 0}, + test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 4294967296, want: 0}, + test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 9223372036854775806, want: -8589934592}, + test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 9223372036854775806, want: -8589934592}, + test_int64{fn: mul_4294967296_int64, fnname: "mul_4294967296_int64", in: 9223372036854775807, want: -4294967296}, + test_int64{fn: mul_int64_4294967296, fnname: "mul_int64_4294967296", in: 9223372036854775807, want: -4294967296}, + test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: -9223372036854775808, want: 0}, + test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: -9223372036854775807, want: 9223372036854775806}, + test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: -9223372036854775807, want: 9223372036854775806}, + test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: -4294967296, want: 8589934592}, + test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: -4294967296, want: 8589934592}, + test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: -1, want: -9223372036854775806}, + test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: -1, want: -9223372036854775806}, + test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 0, want: 0}, + test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 0, want: 0}, + test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 1, want: 9223372036854775806}, + test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 1, want: 9223372036854775806}, + test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 4294967296, want: -8589934592}, + test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 4294967296, want: -8589934592}, + test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 9223372036854775806, want: 4}, + test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 9223372036854775806, want: 4}, + test_int64{fn: mul_9223372036854775806_int64, fnname: "mul_9223372036854775806_int64", in: 9223372036854775807, want: -9223372036854775806}, + test_int64{fn: mul_int64_9223372036854775806, fnname: "mul_int64_9223372036854775806", in: 9223372036854775807, want: -9223372036854775806}, + test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: -9223372036854775807, want: -1}, + test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: -9223372036854775807, want: -1}, + test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: -4294967296, want: 4294967296}, + test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: -4294967296, want: 4294967296}, + test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: -1, want: -9223372036854775807}, + test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: -1, want: -9223372036854775807}, + test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 0, want: 0}, + test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 0, want: 0}, + test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 1, want: 9223372036854775807}, + test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 1, want: 9223372036854775807}, + test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 4294967296, want: -4294967296}, + test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 4294967296, want: -4294967296}, + test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 9223372036854775806, want: -9223372036854775806}, + test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 9223372036854775806, want: -9223372036854775806}, + test_int64{fn: mul_9223372036854775807_int64, fnname: "mul_9223372036854775807_int64", in: 9223372036854775807, want: 1}, + test_int64{fn: mul_int64_9223372036854775807, fnname: "mul_int64_9223372036854775807", in: 9223372036854775807, want: 1}, + test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, + test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: -9223372036854775807, want: -1}, + test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: -4294967296, want: 0}, + test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: -4294967296, want: -4294967296}, + test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: -1, want: 0}, + test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: -1, want: -1}, + test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 0, want: 0}, + test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: 1, want: 0}, + test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 1, want: 1}, + test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: 4294967296, want: 0}, + test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 4294967296, want: 4294967296}, + test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: 9223372036854775806, want: -2}, + test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: mod_Neg9223372036854775808_int64, fnname: "mod_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, + test_int64{fn: mod_int64_Neg9223372036854775808, fnname: "mod_int64_Neg9223372036854775808", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775807}, + test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: -9223372036854775808, want: -1}, + test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: -9223372036854775807, want: 0}, + test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: -4294967296, want: -4294967295}, + test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: -4294967296, want: -4294967296}, + test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: -1, want: 0}, + test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: -1, want: -1}, + test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 0, want: 0}, + test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: 1, want: 0}, + test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 1, want: 1}, + test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: 4294967296, want: -4294967295}, + test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 4294967296, want: 4294967296}, + test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, + test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: mod_Neg9223372036854775807_int64, fnname: "mod_Neg9223372036854775807_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: mod_int64_Neg9223372036854775807, fnname: "mod_int64_Neg9223372036854775807", in: 9223372036854775807, want: 0}, + test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: -9223372036854775808, want: -4294967296}, + test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: -9223372036854775808, want: 0}, + test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: -9223372036854775807, want: -4294967296}, + test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: -9223372036854775807, want: -4294967295}, + test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: -4294967296, want: 0}, + test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: -4294967296, want: 0}, + test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: -1, want: 0}, + test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: -1, want: -1}, + test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 0, want: 0}, + test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: 1, want: 0}, + test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 1, want: 1}, + test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: 4294967296, want: 0}, + test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 4294967296, want: 0}, + test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: 9223372036854775806, want: -4294967296}, + test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 9223372036854775806, want: 4294967294}, + test_int64{fn: mod_Neg4294967296_int64, fnname: "mod_Neg4294967296_int64", in: 9223372036854775807, want: -4294967296}, + test_int64{fn: mod_int64_Neg4294967296, fnname: "mod_int64_Neg4294967296", in: 9223372036854775807, want: 4294967295}, + test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: -9223372036854775808, want: -1}, + test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: -9223372036854775808, want: 0}, + test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: -9223372036854775807, want: -1}, + test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: -9223372036854775807, want: 0}, + test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: -4294967296, want: -1}, + test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: -4294967296, want: 0}, + test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: -1, want: 0}, + test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: -1, want: 0}, + test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 0, want: 0}, + test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: 1, want: 0}, + test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 1, want: 0}, + test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: 4294967296, want: -1}, + test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 4294967296, want: 0}, + test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: 9223372036854775806, want: -1}, + test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 9223372036854775806, want: 0}, + test_int64{fn: mod_Neg1_int64, fnname: "mod_Neg1_int64", in: 9223372036854775807, want: -1}, + test_int64{fn: mod_int64_Neg1, fnname: "mod_int64_Neg1", in: 9223372036854775807, want: 0}, + test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: -4294967296, want: 0}, + test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: -1, want: 0}, + test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: 1, want: 0}, + test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: 4294967296, want: 0}, + test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: mod_0_int64, fnname: "mod_0_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: -9223372036854775808, want: 1}, + test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: -9223372036854775808, want: 0}, + test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: -9223372036854775807, want: 1}, + test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: -9223372036854775807, want: 0}, + test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: -4294967296, want: 1}, + test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: -4294967296, want: 0}, + test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: -1, want: 0}, + test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: -1, want: 0}, + test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 0, want: 0}, + test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: 1, want: 0}, + test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 1, want: 0}, + test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: 4294967296, want: 1}, + test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 4294967296, want: 0}, + test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: 9223372036854775806, want: 1}, + test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 9223372036854775806, want: 0}, + test_int64{fn: mod_1_int64, fnname: "mod_1_int64", in: 9223372036854775807, want: 1}, + test_int64{fn: mod_int64_1, fnname: "mod_int64_1", in: 9223372036854775807, want: 0}, + test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: -9223372036854775808, want: 4294967296}, + test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: -9223372036854775808, want: 0}, + test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: -9223372036854775807, want: 4294967296}, + test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: -9223372036854775807, want: -4294967295}, + test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: -4294967296, want: 0}, + test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: -4294967296, want: 0}, + test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: -1, want: 0}, + test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: -1, want: -1}, + test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 0, want: 0}, + test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: 1, want: 0}, + test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 1, want: 1}, + test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: 4294967296, want: 0}, + test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 4294967296, want: 0}, + test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: 9223372036854775806, want: 4294967296}, + test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 9223372036854775806, want: 4294967294}, + test_int64{fn: mod_4294967296_int64, fnname: "mod_4294967296_int64", in: 9223372036854775807, want: 4294967296}, + test_int64{fn: mod_int64_4294967296, fnname: "mod_int64_4294967296", in: 9223372036854775807, want: 4294967295}, + test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: -9223372036854775808, want: 9223372036854775806}, + test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: -9223372036854775808, want: -2}, + test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: -9223372036854775807, want: 9223372036854775806}, + test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: -9223372036854775807, want: -1}, + test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: -4294967296, want: 4294967294}, + test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: -4294967296, want: -4294967296}, + test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: -1, want: 0}, + test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: -1, want: -1}, + test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 0, want: 0}, + test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: 1, want: 0}, + test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 1, want: 1}, + test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: 4294967296, want: 4294967294}, + test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 4294967296, want: 4294967296}, + test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 9223372036854775806, want: 0}, + test_int64{fn: mod_9223372036854775806_int64, fnname: "mod_9223372036854775806_int64", in: 9223372036854775807, want: 9223372036854775806}, + test_int64{fn: mod_int64_9223372036854775806, fnname: "mod_int64_9223372036854775806", in: 9223372036854775807, want: 1}, + test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: -9223372036854775808, want: 9223372036854775807}, + test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: -9223372036854775808, want: -1}, + test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: -9223372036854775807, want: 0}, + test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: -4294967296, want: 4294967295}, + test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: -4294967296, want: -4294967296}, + test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: -1, want: 0}, + test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: -1, want: -1}, + test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 0, want: 0}, + test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: 1, want: 0}, + test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 1, want: 1}, + test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: 4294967296, want: 4294967295}, + test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 4294967296, want: 4294967296}, + test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: 9223372036854775806, want: 1}, + test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: mod_9223372036854775807_int64, fnname: "mod_9223372036854775807_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: mod_int64_9223372036854775807, fnname: "mod_int64_9223372036854775807", in: 9223372036854775807, want: 0}, + test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: -9223372036854775807, want: -9223372036854775808}, + test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: -9223372036854775807, want: -9223372036854775808}, + test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: -4294967296, want: -9223372036854775808}, + test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: -4294967296, want: -9223372036854775808}, + test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: -1, want: -9223372036854775808}, + test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: -1, want: -9223372036854775808}, + test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 0, want: 0}, + test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 0, want: 0}, + test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 1, want: 0}, + test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 1, want: 0}, + test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 4294967296, want: 0}, + test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 4294967296, want: 0}, + test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 9223372036854775806, want: 0}, + test_int64{fn: and_Neg9223372036854775808_int64, fnname: "and_Neg9223372036854775808_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: and_int64_Neg9223372036854775808, fnname: "and_int64_Neg9223372036854775808", in: 9223372036854775807, want: 0}, + test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: -4294967296, want: -9223372036854775808}, + test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: -4294967296, want: -9223372036854775808}, + test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: -1, want: -9223372036854775807}, + test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: -1, want: -9223372036854775807}, + test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 0, want: 0}, + test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 0, want: 0}, + test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 1, want: 1}, + test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 1, want: 1}, + test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 4294967296, want: 0}, + test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 4294967296, want: 0}, + test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 9223372036854775806, want: 0}, + test_int64{fn: and_Neg9223372036854775807_int64, fnname: "and_Neg9223372036854775807_int64", in: 9223372036854775807, want: 1}, + test_int64{fn: and_int64_Neg9223372036854775807, fnname: "and_int64_Neg9223372036854775807", in: 9223372036854775807, want: 1}, + test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: -9223372036854775807, want: -9223372036854775808}, + test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: -9223372036854775807, want: -9223372036854775808}, + test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: -4294967296, want: -4294967296}, + test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: -4294967296, want: -4294967296}, + test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: -1, want: -4294967296}, + test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: -1, want: -4294967296}, + test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 0, want: 0}, + test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 0, want: 0}, + test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 1, want: 0}, + test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 1, want: 0}, + test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 4294967296, want: 4294967296}, + test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 4294967296, want: 4294967296}, + test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 9223372036854775806, want: 9223372032559808512}, + test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 9223372036854775806, want: 9223372032559808512}, + test_int64{fn: and_Neg4294967296_int64, fnname: "and_Neg4294967296_int64", in: 9223372036854775807, want: 9223372032559808512}, + test_int64{fn: and_int64_Neg4294967296, fnname: "and_int64_Neg4294967296", in: 9223372036854775807, want: 9223372032559808512}, + test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: -4294967296, want: -4294967296}, + test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: -4294967296, want: -4294967296}, + test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: -1, want: -1}, + test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: -1, want: -1}, + test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 0, want: 0}, + test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 0, want: 0}, + test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 1, want: 1}, + test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 1, want: 1}, + test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 4294967296, want: 4294967296}, + test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 4294967296, want: 4294967296}, + test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: and_Neg1_int64, fnname: "and_Neg1_int64", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: and_int64_Neg1, fnname: "and_int64_Neg1", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: and_0_int64, fnname: "and_0_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: and_int64_0, fnname: "and_int64_0", in: -9223372036854775808, want: 0}, + test_int64{fn: and_0_int64, fnname: "and_0_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: and_int64_0, fnname: "and_int64_0", in: -9223372036854775807, want: 0}, + test_int64{fn: and_0_int64, fnname: "and_0_int64", in: -4294967296, want: 0}, + test_int64{fn: and_int64_0, fnname: "and_int64_0", in: -4294967296, want: 0}, + test_int64{fn: and_0_int64, fnname: "and_0_int64", in: -1, want: 0}, + test_int64{fn: and_int64_0, fnname: "and_int64_0", in: -1, want: 0}, + test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 0, want: 0}, + test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 0, want: 0}, + test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 1, want: 0}, + test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 1, want: 0}, + test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 4294967296, want: 0}, + test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 4294967296, want: 0}, + test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 9223372036854775806, want: 0}, + test_int64{fn: and_0_int64, fnname: "and_0_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: and_int64_0, fnname: "and_int64_0", in: 9223372036854775807, want: 0}, + test_int64{fn: and_1_int64, fnname: "and_1_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: and_int64_1, fnname: "and_int64_1", in: -9223372036854775808, want: 0}, + test_int64{fn: and_1_int64, fnname: "and_1_int64", in: -9223372036854775807, want: 1}, + test_int64{fn: and_int64_1, fnname: "and_int64_1", in: -9223372036854775807, want: 1}, + test_int64{fn: and_1_int64, fnname: "and_1_int64", in: -4294967296, want: 0}, + test_int64{fn: and_int64_1, fnname: "and_int64_1", in: -4294967296, want: 0}, + test_int64{fn: and_1_int64, fnname: "and_1_int64", in: -1, want: 1}, + test_int64{fn: and_int64_1, fnname: "and_int64_1", in: -1, want: 1}, + test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 0, want: 0}, + test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 0, want: 0}, + test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 1, want: 1}, + test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 1, want: 1}, + test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 4294967296, want: 0}, + test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 4294967296, want: 0}, + test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 9223372036854775806, want: 0}, + test_int64{fn: and_1_int64, fnname: "and_1_int64", in: 9223372036854775807, want: 1}, + test_int64{fn: and_int64_1, fnname: "and_int64_1", in: 9223372036854775807, want: 1}, + test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: -9223372036854775808, want: 0}, + test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: -9223372036854775807, want: 0}, + test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: -4294967296, want: 4294967296}, + test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: -4294967296, want: 4294967296}, + test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: -1, want: 4294967296}, + test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: -1, want: 4294967296}, + test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 0, want: 0}, + test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 0, want: 0}, + test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 1, want: 0}, + test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 1, want: 0}, + test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 4294967296, want: 4294967296}, + test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 4294967296, want: 4294967296}, + test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 9223372036854775806, want: 4294967296}, + test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 9223372036854775806, want: 4294967296}, + test_int64{fn: and_4294967296_int64, fnname: "and_4294967296_int64", in: 9223372036854775807, want: 4294967296}, + test_int64{fn: and_int64_4294967296, fnname: "and_int64_4294967296", in: 9223372036854775807, want: 4294967296}, + test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: -9223372036854775808, want: 0}, + test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: -9223372036854775807, want: 0}, + test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: -4294967296, want: 9223372032559808512}, + test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: -4294967296, want: 9223372032559808512}, + test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: -1, want: 9223372036854775806}, + test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: -1, want: 9223372036854775806}, + test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 0, want: 0}, + test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 0, want: 0}, + test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 1, want: 0}, + test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 1, want: 0}, + test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 4294967296, want: 4294967296}, + test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 4294967296, want: 4294967296}, + test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: and_9223372036854775806_int64, fnname: "and_9223372036854775806_int64", in: 9223372036854775807, want: 9223372036854775806}, + test_int64{fn: and_int64_9223372036854775806, fnname: "and_int64_9223372036854775806", in: 9223372036854775807, want: 9223372036854775806}, + test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: -9223372036854775808, want: 0}, + test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: -9223372036854775807, want: 1}, + test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: -9223372036854775807, want: 1}, + test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: -4294967296, want: 9223372032559808512}, + test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: -4294967296, want: 9223372032559808512}, + test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: -1, want: 9223372036854775807}, + test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: -1, want: 9223372036854775807}, + test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 0, want: 0}, + test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 0, want: 0}, + test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 1, want: 1}, + test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 1, want: 1}, + test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 4294967296, want: 4294967296}, + test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 4294967296, want: 4294967296}, + test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: and_9223372036854775807_int64, fnname: "and_9223372036854775807_int64", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: and_int64_9223372036854775807, fnname: "and_int64_9223372036854775807", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: -4294967296, want: -4294967296}, + test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: -4294967296, want: -4294967296}, + test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: -1, want: -1}, + test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: -1, want: -1}, + test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 0, want: -9223372036854775808}, + test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 0, want: -9223372036854775808}, + test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 1, want: -9223372036854775807}, + test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 1, want: -9223372036854775807}, + test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 4294967296, want: -9223372032559808512}, + test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 4294967296, want: -9223372032559808512}, + test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 9223372036854775806, want: -2}, + test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 9223372036854775806, want: -2}, + test_int64{fn: or_Neg9223372036854775808_int64, fnname: "or_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, + test_int64{fn: or_int64_Neg9223372036854775808, fnname: "or_int64_Neg9223372036854775808", in: 9223372036854775807, want: -1}, + test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: -9223372036854775808, want: -9223372036854775807}, + test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: -9223372036854775808, want: -9223372036854775807}, + test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: -4294967296, want: -4294967295}, + test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: -4294967296, want: -4294967295}, + test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: -1, want: -1}, + test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: -1, want: -1}, + test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 0, want: -9223372036854775807}, + test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 0, want: -9223372036854775807}, + test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 1, want: -9223372036854775807}, + test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 1, want: -9223372036854775807}, + test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 4294967296, want: -9223372032559808511}, + test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 4294967296, want: -9223372032559808511}, + test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, + test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 9223372036854775806, want: -1}, + test_int64{fn: or_Neg9223372036854775807_int64, fnname: "or_Neg9223372036854775807_int64", in: 9223372036854775807, want: -1}, + test_int64{fn: or_int64_Neg9223372036854775807, fnname: "or_int64_Neg9223372036854775807", in: 9223372036854775807, want: -1}, + test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: -9223372036854775808, want: -4294967296}, + test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: -9223372036854775808, want: -4294967296}, + test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: -9223372036854775807, want: -4294967295}, + test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: -9223372036854775807, want: -4294967295}, + test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: -4294967296, want: -4294967296}, + test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: -4294967296, want: -4294967296}, + test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: -1, want: -1}, + test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: -1, want: -1}, + test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 0, want: -4294967296}, + test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 0, want: -4294967296}, + test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 1, want: -4294967295}, + test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 1, want: -4294967295}, + test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 4294967296, want: -4294967296}, + test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 4294967296, want: -4294967296}, + test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 9223372036854775806, want: -2}, + test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 9223372036854775806, want: -2}, + test_int64{fn: or_Neg4294967296_int64, fnname: "or_Neg4294967296_int64", in: 9223372036854775807, want: -1}, + test_int64{fn: or_int64_Neg4294967296, fnname: "or_int64_Neg4294967296", in: 9223372036854775807, want: -1}, + test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: -9223372036854775808, want: -1}, + test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: -9223372036854775808, want: -1}, + test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: -9223372036854775807, want: -1}, + test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: -9223372036854775807, want: -1}, + test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: -4294967296, want: -1}, + test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: -4294967296, want: -1}, + test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: -1, want: -1}, + test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: -1, want: -1}, + test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 0, want: -1}, + test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 0, want: -1}, + test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 1, want: -1}, + test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 1, want: -1}, + test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 4294967296, want: -1}, + test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 4294967296, want: -1}, + test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 9223372036854775806, want: -1}, + test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 9223372036854775806, want: -1}, + test_int64{fn: or_Neg1_int64, fnname: "or_Neg1_int64", in: 9223372036854775807, want: -1}, + test_int64{fn: or_int64_Neg1, fnname: "or_int64_Neg1", in: 9223372036854775807, want: -1}, + test_int64{fn: or_0_int64, fnname: "or_0_int64", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: or_int64_0, fnname: "or_int64_0", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: or_0_int64, fnname: "or_0_int64", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: or_int64_0, fnname: "or_int64_0", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: or_0_int64, fnname: "or_0_int64", in: -4294967296, want: -4294967296}, + test_int64{fn: or_int64_0, fnname: "or_int64_0", in: -4294967296, want: -4294967296}, + test_int64{fn: or_0_int64, fnname: "or_0_int64", in: -1, want: -1}, + test_int64{fn: or_int64_0, fnname: "or_int64_0", in: -1, want: -1}, + test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 0, want: 0}, + test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 0, want: 0}, + test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 1, want: 1}, + test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 1, want: 1}, + test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 4294967296, want: 4294967296}, + test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 4294967296, want: 4294967296}, + test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: or_0_int64, fnname: "or_0_int64", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: or_int64_0, fnname: "or_int64_0", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: or_1_int64, fnname: "or_1_int64", in: -9223372036854775808, want: -9223372036854775807}, + test_int64{fn: or_int64_1, fnname: "or_int64_1", in: -9223372036854775808, want: -9223372036854775807}, + test_int64{fn: or_1_int64, fnname: "or_1_int64", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: or_int64_1, fnname: "or_int64_1", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: or_1_int64, fnname: "or_1_int64", in: -4294967296, want: -4294967295}, + test_int64{fn: or_int64_1, fnname: "or_int64_1", in: -4294967296, want: -4294967295}, + test_int64{fn: or_1_int64, fnname: "or_1_int64", in: -1, want: -1}, + test_int64{fn: or_int64_1, fnname: "or_int64_1", in: -1, want: -1}, + test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 0, want: 1}, + test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 0, want: 1}, + test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 1, want: 1}, + test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 1, want: 1}, + test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 4294967296, want: 4294967297}, + test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 4294967296, want: 4294967297}, + test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 9223372036854775806, want: 9223372036854775807}, + test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 9223372036854775806, want: 9223372036854775807}, + test_int64{fn: or_1_int64, fnname: "or_1_int64", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: or_int64_1, fnname: "or_int64_1", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: -9223372036854775808, want: -9223372032559808512}, + test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: -9223372036854775808, want: -9223372032559808512}, + test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: -9223372036854775807, want: -9223372032559808511}, + test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: -9223372036854775807, want: -9223372032559808511}, + test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: -4294967296, want: -4294967296}, + test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: -4294967296, want: -4294967296}, + test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: -1, want: -1}, + test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: -1, want: -1}, + test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 0, want: 4294967296}, + test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 0, want: 4294967296}, + test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 1, want: 4294967297}, + test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 1, want: 4294967297}, + test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 4294967296, want: 4294967296}, + test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 4294967296, want: 4294967296}, + test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: or_4294967296_int64, fnname: "or_4294967296_int64", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: or_int64_4294967296, fnname: "or_int64_4294967296", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: -9223372036854775808, want: -2}, + test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: -9223372036854775808, want: -2}, + test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: -9223372036854775807, want: -1}, + test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: -9223372036854775807, want: -1}, + test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: -4294967296, want: -2}, + test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: -4294967296, want: -2}, + test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: -1, want: -1}, + test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: -1, want: -1}, + test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 0, want: 9223372036854775806}, + test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 0, want: 9223372036854775806}, + test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 1, want: 9223372036854775807}, + test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 1, want: 9223372036854775807}, + test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 4294967296, want: 9223372036854775806}, + test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 4294967296, want: 9223372036854775806}, + test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: or_9223372036854775806_int64, fnname: "or_9223372036854775806_int64", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: or_int64_9223372036854775806, fnname: "or_int64_9223372036854775806", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: -9223372036854775808, want: -1}, + test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: -9223372036854775808, want: -1}, + test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: -9223372036854775807, want: -1}, + test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: -9223372036854775807, want: -1}, + test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: -4294967296, want: -1}, + test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: -4294967296, want: -1}, + test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: -1, want: -1}, + test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: -1, want: -1}, + test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 0, want: 9223372036854775807}, + test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 0, want: 9223372036854775807}, + test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 1, want: 9223372036854775807}, + test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 1, want: 9223372036854775807}, + test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 4294967296, want: 9223372036854775807}, + test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 4294967296, want: 9223372036854775807}, + test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 9223372036854775806, want: 9223372036854775807}, + test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 9223372036854775806, want: 9223372036854775807}, + test_int64{fn: or_9223372036854775807_int64, fnname: "or_9223372036854775807_int64", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: or_int64_9223372036854775807, fnname: "or_int64_9223372036854775807", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: -9223372036854775808, want: 0}, + test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: -9223372036854775808, want: 0}, + test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: -9223372036854775807, want: 1}, + test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: -9223372036854775807, want: 1}, + test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: -4294967296, want: 9223372032559808512}, + test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: -4294967296, want: 9223372032559808512}, + test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: -1, want: 9223372036854775807}, + test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: -1, want: 9223372036854775807}, + test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 0, want: -9223372036854775808}, + test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 0, want: -9223372036854775808}, + test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 1, want: -9223372036854775807}, + test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 1, want: -9223372036854775807}, + test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 4294967296, want: -9223372032559808512}, + test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 4294967296, want: -9223372032559808512}, + test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 9223372036854775806, want: -2}, + test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 9223372036854775806, want: -2}, + test_int64{fn: xor_Neg9223372036854775808_int64, fnname: "xor_Neg9223372036854775808_int64", in: 9223372036854775807, want: -1}, + test_int64{fn: xor_int64_Neg9223372036854775808, fnname: "xor_int64_Neg9223372036854775808", in: 9223372036854775807, want: -1}, + test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: -9223372036854775808, want: 1}, + test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: -9223372036854775808, want: 1}, + test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: -9223372036854775807, want: 0}, + test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: -9223372036854775807, want: 0}, + test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: -4294967296, want: 9223372032559808513}, + test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: -4294967296, want: 9223372032559808513}, + test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: -1, want: 9223372036854775806}, + test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: -1, want: 9223372036854775806}, + test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 0, want: -9223372036854775807}, + test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 0, want: -9223372036854775807}, + test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 1, want: -9223372036854775808}, + test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 1, want: -9223372036854775808}, + test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 4294967296, want: -9223372032559808511}, + test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 4294967296, want: -9223372032559808511}, + test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 9223372036854775806, want: -1}, + test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 9223372036854775806, want: -1}, + test_int64{fn: xor_Neg9223372036854775807_int64, fnname: "xor_Neg9223372036854775807_int64", in: 9223372036854775807, want: -2}, + test_int64{fn: xor_int64_Neg9223372036854775807, fnname: "xor_int64_Neg9223372036854775807", in: 9223372036854775807, want: -2}, + test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: -9223372036854775808, want: 9223372032559808512}, + test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: -9223372036854775808, want: 9223372032559808512}, + test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: -9223372036854775807, want: 9223372032559808513}, + test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: -9223372036854775807, want: 9223372032559808513}, + test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: -4294967296, want: 0}, + test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: -4294967296, want: 0}, + test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: -1, want: 4294967295}, + test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: -1, want: 4294967295}, + test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 0, want: -4294967296}, + test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 0, want: -4294967296}, + test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 1, want: -4294967295}, + test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 1, want: -4294967295}, + test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 4294967296, want: -8589934592}, + test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 4294967296, want: -8589934592}, + test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 9223372036854775806, want: -9223372032559808514}, + test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 9223372036854775806, want: -9223372032559808514}, + test_int64{fn: xor_Neg4294967296_int64, fnname: "xor_Neg4294967296_int64", in: 9223372036854775807, want: -9223372032559808513}, + test_int64{fn: xor_int64_Neg4294967296, fnname: "xor_int64_Neg4294967296", in: 9223372036854775807, want: -9223372032559808513}, + test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: -9223372036854775808, want: 9223372036854775807}, + test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: -9223372036854775808, want: 9223372036854775807}, + test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: -9223372036854775807, want: 9223372036854775806}, + test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: -9223372036854775807, want: 9223372036854775806}, + test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: -4294967296, want: 4294967295}, + test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: -4294967296, want: 4294967295}, + test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: -1, want: 0}, + test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: -1, want: 0}, + test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 0, want: -1}, + test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 0, want: -1}, + test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 1, want: -2}, + test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 1, want: -2}, + test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 4294967296, want: -4294967297}, + test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 4294967296, want: -4294967297}, + test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 9223372036854775806, want: -9223372036854775807}, + test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 9223372036854775806, want: -9223372036854775807}, + test_int64{fn: xor_Neg1_int64, fnname: "xor_Neg1_int64", in: 9223372036854775807, want: -9223372036854775808}, + test_int64{fn: xor_int64_Neg1, fnname: "xor_int64_Neg1", in: 9223372036854775807, want: -9223372036854775808}, + test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: -9223372036854775808, want: -9223372036854775808}, + test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: -9223372036854775807, want: -9223372036854775807}, + test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: -4294967296, want: -4294967296}, + test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: -4294967296, want: -4294967296}, + test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: -1, want: -1}, + test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: -1, want: -1}, + test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 0, want: 0}, + test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 0, want: 0}, + test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 1, want: 1}, + test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 1, want: 1}, + test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 4294967296, want: 4294967296}, + test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 4294967296, want: 4294967296}, + test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 9223372036854775806, want: 9223372036854775806}, + test_int64{fn: xor_0_int64, fnname: "xor_0_int64", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: xor_int64_0, fnname: "xor_int64_0", in: 9223372036854775807, want: 9223372036854775807}, + test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: -9223372036854775808, want: -9223372036854775807}, + test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: -9223372036854775808, want: -9223372036854775807}, + test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: -9223372036854775807, want: -9223372036854775808}, + test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: -9223372036854775807, want: -9223372036854775808}, + test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: -4294967296, want: -4294967295}, + test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: -4294967296, want: -4294967295}, + test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: -1, want: -2}, + test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: -1, want: -2}, + test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 0, want: 1}, + test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 0, want: 1}, + test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 1, want: 0}, + test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 1, want: 0}, + test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 4294967296, want: 4294967297}, + test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 4294967296, want: 4294967297}, + test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 9223372036854775806, want: 9223372036854775807}, + test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 9223372036854775806, want: 9223372036854775807}, + test_int64{fn: xor_1_int64, fnname: "xor_1_int64", in: 9223372036854775807, want: 9223372036854775806}, + test_int64{fn: xor_int64_1, fnname: "xor_int64_1", in: 9223372036854775807, want: 9223372036854775806}, + test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: -9223372036854775808, want: -9223372032559808512}, + test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: -9223372036854775808, want: -9223372032559808512}, + test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: -9223372036854775807, want: -9223372032559808511}, + test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: -9223372036854775807, want: -9223372032559808511}, + test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: -4294967296, want: -8589934592}, + test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: -4294967296, want: -8589934592}, + test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: -1, want: -4294967297}, + test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: -1, want: -4294967297}, + test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 0, want: 4294967296}, + test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 0, want: 4294967296}, + test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 1, want: 4294967297}, + test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 1, want: 4294967297}, + test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 4294967296, want: 0}, + test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 4294967296, want: 0}, + test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 9223372036854775806, want: 9223372032559808510}, + test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 9223372036854775806, want: 9223372032559808510}, + test_int64{fn: xor_4294967296_int64, fnname: "xor_4294967296_int64", in: 9223372036854775807, want: 9223372032559808511}, + test_int64{fn: xor_int64_4294967296, fnname: "xor_int64_4294967296", in: 9223372036854775807, want: 9223372032559808511}, + test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: -9223372036854775808, want: -2}, + test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: -9223372036854775808, want: -2}, + test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: -9223372036854775807, want: -1}, + test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: -9223372036854775807, want: -1}, + test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: -4294967296, want: -9223372032559808514}, + test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: -4294967296, want: -9223372032559808514}, + test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: -1, want: -9223372036854775807}, + test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: -1, want: -9223372036854775807}, + test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 0, want: 9223372036854775806}, + test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 0, want: 9223372036854775806}, + test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 1, want: 9223372036854775807}, + test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 1, want: 9223372036854775807}, + test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 4294967296, want: 9223372032559808510}, + test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 4294967296, want: 9223372032559808510}, + test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 9223372036854775806, want: 0}, + test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 9223372036854775806, want: 0}, + test_int64{fn: xor_9223372036854775806_int64, fnname: "xor_9223372036854775806_int64", in: 9223372036854775807, want: 1}, + test_int64{fn: xor_int64_9223372036854775806, fnname: "xor_int64_9223372036854775806", in: 9223372036854775807, want: 1}, + test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: -9223372036854775808, want: -1}, + test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: -9223372036854775808, want: -1}, + test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: -9223372036854775807, want: -2}, + test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: -9223372036854775807, want: -2}, + test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: -4294967296, want: -9223372032559808513}, + test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: -4294967296, want: -9223372032559808513}, + test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: -1, want: -9223372036854775808}, + test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: -1, want: -9223372036854775808}, + test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 0, want: 9223372036854775807}, + test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 0, want: 9223372036854775807}, + test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 1, want: 9223372036854775806}, + test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 1, want: 9223372036854775806}, + test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 4294967296, want: 9223372032559808511}, + test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 4294967296, want: 9223372032559808511}, + test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 9223372036854775806, want: 1}, + test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 9223372036854775806, want: 1}, + test_int64{fn: xor_9223372036854775807_int64, fnname: "xor_9223372036854775807_int64", in: 9223372036854775807, want: 0}, + test_int64{fn: xor_int64_9223372036854775807, fnname: "xor_int64_9223372036854775807", in: 9223372036854775807, want: 0}} + +type test_uint32 struct { + fn func(uint32) uint32 + fnname string + in uint32 + want uint32 } + +var tests_uint32 = []test_uint32{ -//go:noinline -func xor_1_int8_ssa(a int8) int8 { - return 1 ^ a + test_uint32{fn: add_0_uint32, fnname: "add_0_uint32", in: 0, want: 0}, + test_uint32{fn: add_uint32_0, fnname: "add_uint32_0", in: 0, want: 0}, + test_uint32{fn: add_0_uint32, fnname: "add_0_uint32", in: 1, want: 1}, + test_uint32{fn: add_uint32_0, fnname: "add_uint32_0", in: 1, want: 1}, + test_uint32{fn: add_0_uint32, fnname: "add_0_uint32", in: 4294967295, want: 4294967295}, + test_uint32{fn: add_uint32_0, fnname: "add_uint32_0", in: 4294967295, want: 4294967295}, + test_uint32{fn: add_1_uint32, fnname: "add_1_uint32", in: 0, want: 1}, + test_uint32{fn: add_uint32_1, fnname: "add_uint32_1", in: 0, want: 1}, + test_uint32{fn: add_1_uint32, fnname: "add_1_uint32", in: 1, want: 2}, + test_uint32{fn: add_uint32_1, fnname: "add_uint32_1", in: 1, want: 2}, + test_uint32{fn: add_1_uint32, fnname: "add_1_uint32", in: 4294967295, want: 0}, + test_uint32{fn: add_uint32_1, fnname: "add_uint32_1", in: 4294967295, want: 0}, + test_uint32{fn: add_4294967295_uint32, fnname: "add_4294967295_uint32", in: 0, want: 4294967295}, + test_uint32{fn: add_uint32_4294967295, fnname: "add_uint32_4294967295", in: 0, want: 4294967295}, + test_uint32{fn: add_4294967295_uint32, fnname: "add_4294967295_uint32", in: 1, want: 0}, + test_uint32{fn: add_uint32_4294967295, fnname: "add_uint32_4294967295", in: 1, want: 0}, + test_uint32{fn: add_4294967295_uint32, fnname: "add_4294967295_uint32", in: 4294967295, want: 4294967294}, + test_uint32{fn: add_uint32_4294967295, fnname: "add_uint32_4294967295", in: 4294967295, want: 4294967294}, + test_uint32{fn: sub_0_uint32, fnname: "sub_0_uint32", in: 0, want: 0}, + test_uint32{fn: sub_uint32_0, fnname: "sub_uint32_0", in: 0, want: 0}, + test_uint32{fn: sub_0_uint32, fnname: "sub_0_uint32", in: 1, want: 4294967295}, + test_uint32{fn: sub_uint32_0, fnname: "sub_uint32_0", in: 1, want: 1}, + test_uint32{fn: sub_0_uint32, fnname: "sub_0_uint32", in: 4294967295, want: 1}, + test_uint32{fn: sub_uint32_0, fnname: "sub_uint32_0", in: 4294967295, want: 4294967295}, + test_uint32{fn: sub_1_uint32, fnname: "sub_1_uint32", in: 0, want: 1}, + test_uint32{fn: sub_uint32_1, fnname: "sub_uint32_1", in: 0, want: 4294967295}, + test_uint32{fn: sub_1_uint32, fnname: "sub_1_uint32", in: 1, want: 0}, + test_uint32{fn: sub_uint32_1, fnname: "sub_uint32_1", in: 1, want: 0}, + test_uint32{fn: sub_1_uint32, fnname: "sub_1_uint32", in: 4294967295, want: 2}, + test_uint32{fn: sub_uint32_1, fnname: "sub_uint32_1", in: 4294967295, want: 4294967294}, + test_uint32{fn: sub_4294967295_uint32, fnname: "sub_4294967295_uint32", in: 0, want: 4294967295}, + test_uint32{fn: sub_uint32_4294967295, fnname: "sub_uint32_4294967295", in: 0, want: 1}, + test_uint32{fn: sub_4294967295_uint32, fnname: "sub_4294967295_uint32", in: 1, want: 4294967294}, + test_uint32{fn: sub_uint32_4294967295, fnname: "sub_uint32_4294967295", in: 1, want: 2}, + test_uint32{fn: sub_4294967295_uint32, fnname: "sub_4294967295_uint32", in: 4294967295, want: 0}, + test_uint32{fn: sub_uint32_4294967295, fnname: "sub_uint32_4294967295", in: 4294967295, want: 0}, + test_uint32{fn: div_0_uint32, fnname: "div_0_uint32", in: 1, want: 0}, + test_uint32{fn: div_0_uint32, fnname: "div_0_uint32", in: 4294967295, want: 0}, + test_uint32{fn: div_uint32_1, fnname: "div_uint32_1", in: 0, want: 0}, + test_uint32{fn: div_1_uint32, fnname: "div_1_uint32", in: 1, want: 1}, + test_uint32{fn: div_uint32_1, fnname: "div_uint32_1", in: 1, want: 1}, + test_uint32{fn: div_1_uint32, fnname: "div_1_uint32", in: 4294967295, want: 0}, + test_uint32{fn: div_uint32_1, fnname: "div_uint32_1", in: 4294967295, want: 4294967295}, + test_uint32{fn: div_uint32_4294967295, fnname: "div_uint32_4294967295", in: 0, want: 0}, + test_uint32{fn: div_4294967295_uint32, fnname: "div_4294967295_uint32", in: 1, want: 4294967295}, + test_uint32{fn: div_uint32_4294967295, fnname: "div_uint32_4294967295", in: 1, want: 0}, + test_uint32{fn: div_4294967295_uint32, fnname: "div_4294967295_uint32", in: 4294967295, want: 1}, + test_uint32{fn: div_uint32_4294967295, fnname: "div_uint32_4294967295", in: 4294967295, want: 1}, + test_uint32{fn: mul_0_uint32, fnname: "mul_0_uint32", in: 0, want: 0}, + test_uint32{fn: mul_uint32_0, fnname: "mul_uint32_0", in: 0, want: 0}, + test_uint32{fn: mul_0_uint32, fnname: "mul_0_uint32", in: 1, want: 0}, + test_uint32{fn: mul_uint32_0, fnname: "mul_uint32_0", in: 1, want: 0}, + test_uint32{fn: mul_0_uint32, fnname: "mul_0_uint32", in: 4294967295, want: 0}, + test_uint32{fn: mul_uint32_0, fnname: "mul_uint32_0", in: 4294967295, want: 0}, + test_uint32{fn: mul_1_uint32, fnname: "mul_1_uint32", in: 0, want: 0}, + test_uint32{fn: mul_uint32_1, fnname: "mul_uint32_1", in: 0, want: 0}, + test_uint32{fn: mul_1_uint32, fnname: "mul_1_uint32", in: 1, want: 1}, + test_uint32{fn: mul_uint32_1, fnname: "mul_uint32_1", in: 1, want: 1}, + test_uint32{fn: mul_1_uint32, fnname: "mul_1_uint32", in: 4294967295, want: 4294967295}, + test_uint32{fn: mul_uint32_1, fnname: "mul_uint32_1", in: 4294967295, want: 4294967295}, + test_uint32{fn: mul_4294967295_uint32, fnname: "mul_4294967295_uint32", in: 0, want: 0}, + test_uint32{fn: mul_uint32_4294967295, fnname: "mul_uint32_4294967295", in: 0, want: 0}, + test_uint32{fn: mul_4294967295_uint32, fnname: "mul_4294967295_uint32", in: 1, want: 4294967295}, + test_uint32{fn: mul_uint32_4294967295, fnname: "mul_uint32_4294967295", in: 1, want: 4294967295}, + test_uint32{fn: mul_4294967295_uint32, fnname: "mul_4294967295_uint32", in: 4294967295, want: 1}, + test_uint32{fn: mul_uint32_4294967295, fnname: "mul_uint32_4294967295", in: 4294967295, want: 1}, + test_uint32{fn: lsh_0_uint32, fnname: "lsh_0_uint32", in: 0, want: 0}, + test_uint32{fn: lsh_uint32_0, fnname: "lsh_uint32_0", in: 0, want: 0}, + test_uint32{fn: lsh_0_uint32, fnname: "lsh_0_uint32", in: 1, want: 0}, + test_uint32{fn: lsh_uint32_0, fnname: "lsh_uint32_0", in: 1, want: 1}, + test_uint32{fn: lsh_0_uint32, fnname: "lsh_0_uint32", in: 4294967295, want: 0}, + test_uint32{fn: lsh_uint32_0, fnname: "lsh_uint32_0", in: 4294967295, want: 4294967295}, + test_uint32{fn: lsh_1_uint32, fnname: "lsh_1_uint32", in: 0, want: 1}, + test_uint32{fn: lsh_uint32_1, fnname: "lsh_uint32_1", in: 0, want: 0}, + test_uint32{fn: lsh_1_uint32, fnname: "lsh_1_uint32", in: 1, want: 2}, + test_uint32{fn: lsh_uint32_1, fnname: "lsh_uint32_1", in: 1, want: 2}, + test_uint32{fn: lsh_1_uint32, fnname: "lsh_1_uint32", in: 4294967295, want: 0}, + test_uint32{fn: lsh_uint32_1, fnname: "lsh_uint32_1", in: 4294967295, want: 4294967294}, + test_uint32{fn: lsh_4294967295_uint32, fnname: "lsh_4294967295_uint32", in: 0, want: 4294967295}, + test_uint32{fn: lsh_uint32_4294967295, fnname: "lsh_uint32_4294967295", in: 0, want: 0}, + test_uint32{fn: lsh_4294967295_uint32, fnname: "lsh_4294967295_uint32", in: 1, want: 4294967294}, + test_uint32{fn: lsh_uint32_4294967295, fnname: "lsh_uint32_4294967295", in: 1, want: 0}, + test_uint32{fn: lsh_4294967295_uint32, fnname: "lsh_4294967295_uint32", in: 4294967295, want: 0}, + test_uint32{fn: lsh_uint32_4294967295, fnname: "lsh_uint32_4294967295", in: 4294967295, want: 0}, + test_uint32{fn: rsh_0_uint32, fnname: "rsh_0_uint32", in: 0, want: 0}, + test_uint32{fn: rsh_uint32_0, fnname: "rsh_uint32_0", in: 0, want: 0}, + test_uint32{fn: rsh_0_uint32, fnname: "rsh_0_uint32", in: 1, want: 0}, + test_uint32{fn: rsh_uint32_0, fnname: "rsh_uint32_0", in: 1, want: 1}, + test_uint32{fn: rsh_0_uint32, fnname: "rsh_0_uint32", in: 4294967295, want: 0}, + test_uint32{fn: rsh_uint32_0, fnname: "rsh_uint32_0", in: 4294967295, want: 4294967295}, + test_uint32{fn: rsh_1_uint32, fnname: "rsh_1_uint32", in: 0, want: 1}, + test_uint32{fn: rsh_uint32_1, fnname: "rsh_uint32_1", in: 0, want: 0}, + test_uint32{fn: rsh_1_uint32, fnname: "rsh_1_uint32", in: 1, want: 0}, + test_uint32{fn: rsh_uint32_1, fnname: "rsh_uint32_1", in: 1, want: 0}, + test_uint32{fn: rsh_1_uint32, fnname: "rsh_1_uint32", in: 4294967295, want: 0}, + test_uint32{fn: rsh_uint32_1, fnname: "rsh_uint32_1", in: 4294967295, want: 2147483647}, + test_uint32{fn: rsh_4294967295_uint32, fnname: "rsh_4294967295_uint32", in: 0, want: 4294967295}, + test_uint32{fn: rsh_uint32_4294967295, fnname: "rsh_uint32_4294967295", in: 0, want: 0}, + test_uint32{fn: rsh_4294967295_uint32, fnname: "rsh_4294967295_uint32", in: 1, want: 2147483647}, + test_uint32{fn: rsh_uint32_4294967295, fnname: "rsh_uint32_4294967295", in: 1, want: 0}, + test_uint32{fn: rsh_4294967295_uint32, fnname: "rsh_4294967295_uint32", in: 4294967295, want: 0}, + test_uint32{fn: rsh_uint32_4294967295, fnname: "rsh_uint32_4294967295", in: 4294967295, want: 0}, + test_uint32{fn: mod_0_uint32, fnname: "mod_0_uint32", in: 1, want: 0}, + test_uint32{fn: mod_0_uint32, fnname: "mod_0_uint32", in: 4294967295, want: 0}, + test_uint32{fn: mod_uint32_1, fnname: "mod_uint32_1", in: 0, want: 0}, + test_uint32{fn: mod_1_uint32, fnname: "mod_1_uint32", in: 1, want: 0}, + test_uint32{fn: mod_uint32_1, fnname: "mod_uint32_1", in: 1, want: 0}, + test_uint32{fn: mod_1_uint32, fnname: "mod_1_uint32", in: 4294967295, want: 1}, + test_uint32{fn: mod_uint32_1, fnname: "mod_uint32_1", in: 4294967295, want: 0}, + test_uint32{fn: mod_uint32_4294967295, fnname: "mod_uint32_4294967295", in: 0, want: 0}, + test_uint32{fn: mod_4294967295_uint32, fnname: "mod_4294967295_uint32", in: 1, want: 0}, + test_uint32{fn: mod_uint32_4294967295, fnname: "mod_uint32_4294967295", in: 1, want: 1}, + test_uint32{fn: mod_4294967295_uint32, fnname: "mod_4294967295_uint32", in: 4294967295, want: 0}, + test_uint32{fn: mod_uint32_4294967295, fnname: "mod_uint32_4294967295", in: 4294967295, want: 0}, + test_uint32{fn: and_0_uint32, fnname: "and_0_uint32", in: 0, want: 0}, + test_uint32{fn: and_uint32_0, fnname: "and_uint32_0", in: 0, want: 0}, + test_uint32{fn: and_0_uint32, fnname: "and_0_uint32", in: 1, want: 0}, + test_uint32{fn: and_uint32_0, fnname: "and_uint32_0", in: 1, want: 0}, + test_uint32{fn: and_0_uint32, fnname: "and_0_uint32", in: 4294967295, want: 0}, + test_uint32{fn: and_uint32_0, fnname: "and_uint32_0", in: 4294967295, want: 0}, + test_uint32{fn: and_1_uint32, fnname: "and_1_uint32", in: 0, want: 0}, + test_uint32{fn: and_uint32_1, fnname: "and_uint32_1", in: 0, want: 0}, + test_uint32{fn: and_1_uint32, fnname: "and_1_uint32", in: 1, want: 1}, + test_uint32{fn: and_uint32_1, fnname: "and_uint32_1", in: 1, want: 1}, + test_uint32{fn: and_1_uint32, fnname: "and_1_uint32", in: 4294967295, want: 1}, + test_uint32{fn: and_uint32_1, fnname: "and_uint32_1", in: 4294967295, want: 1}, + test_uint32{fn: and_4294967295_uint32, fnname: "and_4294967295_uint32", in: 0, want: 0}, + test_uint32{fn: and_uint32_4294967295, fnname: "and_uint32_4294967295", in: 0, want: 0}, + test_uint32{fn: and_4294967295_uint32, fnname: "and_4294967295_uint32", in: 1, want: 1}, + test_uint32{fn: and_uint32_4294967295, fnname: "and_uint32_4294967295", in: 1, want: 1}, + test_uint32{fn: and_4294967295_uint32, fnname: "and_4294967295_uint32", in: 4294967295, want: 4294967295}, + test_uint32{fn: and_uint32_4294967295, fnname: "and_uint32_4294967295", in: 4294967295, want: 4294967295}, + test_uint32{fn: or_0_uint32, fnname: "or_0_uint32", in: 0, want: 0}, + test_uint32{fn: or_uint32_0, fnname: "or_uint32_0", in: 0, want: 0}, + test_uint32{fn: or_0_uint32, fnname: "or_0_uint32", in: 1, want: 1}, + test_uint32{fn: or_uint32_0, fnname: "or_uint32_0", in: 1, want: 1}, + test_uint32{fn: or_0_uint32, fnname: "or_0_uint32", in: 4294967295, want: 4294967295}, + test_uint32{fn: or_uint32_0, fnname: "or_uint32_0", in: 4294967295, want: 4294967295}, + test_uint32{fn: or_1_uint32, fnname: "or_1_uint32", in: 0, want: 1}, + test_uint32{fn: or_uint32_1, fnname: "or_uint32_1", in: 0, want: 1}, + test_uint32{fn: or_1_uint32, fnname: "or_1_uint32", in: 1, want: 1}, + test_uint32{fn: or_uint32_1, fnname: "or_uint32_1", in: 1, want: 1}, + test_uint32{fn: or_1_uint32, fnname: "or_1_uint32", in: 4294967295, want: 4294967295}, + test_uint32{fn: or_uint32_1, fnname: "or_uint32_1", in: 4294967295, want: 4294967295}, + test_uint32{fn: or_4294967295_uint32, fnname: "or_4294967295_uint32", in: 0, want: 4294967295}, + test_uint32{fn: or_uint32_4294967295, fnname: "or_uint32_4294967295", in: 0, want: 4294967295}, + test_uint32{fn: or_4294967295_uint32, fnname: "or_4294967295_uint32", in: 1, want: 4294967295}, + test_uint32{fn: or_uint32_4294967295, fnname: "or_uint32_4294967295", in: 1, want: 4294967295}, + test_uint32{fn: or_4294967295_uint32, fnname: "or_4294967295_uint32", in: 4294967295, want: 4294967295}, + test_uint32{fn: or_uint32_4294967295, fnname: "or_uint32_4294967295", in: 4294967295, want: 4294967295}, + test_uint32{fn: xor_0_uint32, fnname: "xor_0_uint32", in: 0, want: 0}, + test_uint32{fn: xor_uint32_0, fnname: "xor_uint32_0", in: 0, want: 0}, + test_uint32{fn: xor_0_uint32, fnname: "xor_0_uint32", in: 1, want: 1}, + test_uint32{fn: xor_uint32_0, fnname: "xor_uint32_0", in: 1, want: 1}, + test_uint32{fn: xor_0_uint32, fnname: "xor_0_uint32", in: 4294967295, want: 4294967295}, + test_uint32{fn: xor_uint32_0, fnname: "xor_uint32_0", in: 4294967295, want: 4294967295}, + test_uint32{fn: xor_1_uint32, fnname: "xor_1_uint32", in: 0, want: 1}, + test_uint32{fn: xor_uint32_1, fnname: "xor_uint32_1", in: 0, want: 1}, + test_uint32{fn: xor_1_uint32, fnname: "xor_1_uint32", in: 1, want: 0}, + test_uint32{fn: xor_uint32_1, fnname: "xor_uint32_1", in: 1, want: 0}, + test_uint32{fn: xor_1_uint32, fnname: "xor_1_uint32", in: 4294967295, want: 4294967294}, + test_uint32{fn: xor_uint32_1, fnname: "xor_uint32_1", in: 4294967295, want: 4294967294}, + test_uint32{fn: xor_4294967295_uint32, fnname: "xor_4294967295_uint32", in: 0, want: 4294967295}, + test_uint32{fn: xor_uint32_4294967295, fnname: "xor_uint32_4294967295", in: 0, want: 4294967295}, + test_uint32{fn: xor_4294967295_uint32, fnname: "xor_4294967295_uint32", in: 1, want: 4294967294}, + test_uint32{fn: xor_uint32_4294967295, fnname: "xor_uint32_4294967295", in: 1, want: 4294967294}, + test_uint32{fn: xor_4294967295_uint32, fnname: "xor_4294967295_uint32", in: 4294967295, want: 0}, + test_uint32{fn: xor_uint32_4294967295, fnname: "xor_uint32_4294967295", in: 4294967295, want: 0}} + +type test_int32 struct { + fn func(int32) int32 + fnname string + in int32 + want int32 } + +var tests_int32 = []test_int32{ -//go:noinline -func xor_int8_126_ssa(a int8) int8 { - return a ^ 126 + test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: -2147483648, want: 0}, + test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: -2147483648, want: 0}, + test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: -2147483647, want: 1}, + test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: -2147483647, want: 1}, + test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: -1, want: 2147483647}, + test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: -1, want: 2147483647}, + test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: 0, want: -2147483648}, + test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: 0, want: -2147483648}, + test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: 1, want: -2147483647}, + test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: 1, want: -2147483647}, + test_int32{fn: add_Neg2147483648_int32, fnname: "add_Neg2147483648_int32", in: 2147483647, want: -1}, + test_int32{fn: add_int32_Neg2147483648, fnname: "add_int32_Neg2147483648", in: 2147483647, want: -1}, + test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: -2147483648, want: 1}, + test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: -2147483648, want: 1}, + test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: -2147483647, want: 2}, + test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: -2147483647, want: 2}, + test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: -1, want: -2147483648}, + test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: -1, want: -2147483648}, + test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: 0, want: -2147483647}, + test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: 0, want: -2147483647}, + test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: 1, want: -2147483646}, + test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: 1, want: -2147483646}, + test_int32{fn: add_Neg2147483647_int32, fnname: "add_Neg2147483647_int32", in: 2147483647, want: 0}, + test_int32{fn: add_int32_Neg2147483647, fnname: "add_int32_Neg2147483647", in: 2147483647, want: 0}, + test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: -2147483648, want: 2147483647}, + test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: -2147483648, want: 2147483647}, + test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: -2147483647, want: -2147483648}, + test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: -2147483647, want: -2147483648}, + test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: -1, want: -2}, + test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: -1, want: -2}, + test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: 0, want: -1}, + test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: 0, want: -1}, + test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: 1, want: 0}, + test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: 1, want: 0}, + test_int32{fn: add_Neg1_int32, fnname: "add_Neg1_int32", in: 2147483647, want: 2147483646}, + test_int32{fn: add_int32_Neg1, fnname: "add_int32_Neg1", in: 2147483647, want: 2147483646}, + test_int32{fn: add_0_int32, fnname: "add_0_int32", in: -2147483648, want: -2147483648}, + test_int32{fn: add_int32_0, fnname: "add_int32_0", in: -2147483648, want: -2147483648}, + test_int32{fn: add_0_int32, fnname: "add_0_int32", in: -2147483647, want: -2147483647}, + test_int32{fn: add_int32_0, fnname: "add_int32_0", in: -2147483647, want: -2147483647}, + test_int32{fn: add_0_int32, fnname: "add_0_int32", in: -1, want: -1}, + test_int32{fn: add_int32_0, fnname: "add_int32_0", in: -1, want: -1}, + test_int32{fn: add_0_int32, fnname: "add_0_int32", in: 0, want: 0}, + test_int32{fn: add_int32_0, fnname: "add_int32_0", in: 0, want: 0}, + test_int32{fn: add_0_int32, fnname: "add_0_int32", in: 1, want: 1}, + test_int32{fn: add_int32_0, fnname: "add_int32_0", in: 1, want: 1}, + test_int32{fn: add_0_int32, fnname: "add_0_int32", in: 2147483647, want: 2147483647}, + test_int32{fn: add_int32_0, fnname: "add_int32_0", in: 2147483647, want: 2147483647}, + test_int32{fn: add_1_int32, fnname: "add_1_int32", in: -2147483648, want: -2147483647}, + test_int32{fn: add_int32_1, fnname: "add_int32_1", in: -2147483648, want: -2147483647}, + test_int32{fn: add_1_int32, fnname: "add_1_int32", in: -2147483647, want: -2147483646}, + test_int32{fn: add_int32_1, fnname: "add_int32_1", in: -2147483647, want: -2147483646}, + test_int32{fn: add_1_int32, fnname: "add_1_int32", in: -1, want: 0}, + test_int32{fn: add_int32_1, fnname: "add_int32_1", in: -1, want: 0}, + test_int32{fn: add_1_int32, fnname: "add_1_int32", in: 0, want: 1}, + test_int32{fn: add_int32_1, fnname: "add_int32_1", in: 0, want: 1}, + test_int32{fn: add_1_int32, fnname: "add_1_int32", in: 1, want: 2}, + test_int32{fn: add_int32_1, fnname: "add_int32_1", in: 1, want: 2}, + test_int32{fn: add_1_int32, fnname: "add_1_int32", in: 2147483647, want: -2147483648}, + test_int32{fn: add_int32_1, fnname: "add_int32_1", in: 2147483647, want: -2147483648}, + test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: -2147483648, want: -1}, + test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: -2147483648, want: -1}, + test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: -2147483647, want: 0}, + test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: -2147483647, want: 0}, + test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: -1, want: 2147483646}, + test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: -1, want: 2147483646}, + test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: 0, want: 2147483647}, + test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: 0, want: 2147483647}, + test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: 1, want: -2147483648}, + test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: 1, want: -2147483648}, + test_int32{fn: add_2147483647_int32, fnname: "add_2147483647_int32", in: 2147483647, want: -2}, + test_int32{fn: add_int32_2147483647, fnname: "add_int32_2147483647", in: 2147483647, want: -2}, + test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: -2147483648, want: 0}, + test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: -2147483648, want: 0}, + test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: -2147483647, want: -1}, + test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: -2147483647, want: 1}, + test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: -1, want: -2147483647}, + test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: -1, want: 2147483647}, + test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: 0, want: -2147483648}, + test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: 0, want: -2147483648}, + test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: 1, want: 2147483647}, + test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: 1, want: -2147483647}, + test_int32{fn: sub_Neg2147483648_int32, fnname: "sub_Neg2147483648_int32", in: 2147483647, want: 1}, + test_int32{fn: sub_int32_Neg2147483648, fnname: "sub_int32_Neg2147483648", in: 2147483647, want: -1}, + test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: -2147483648, want: 1}, + test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: -2147483648, want: -1}, + test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: -2147483647, want: 0}, + test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: -2147483647, want: 0}, + test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: -1, want: -2147483646}, + test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: -1, want: 2147483646}, + test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: 0, want: -2147483647}, + test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: 0, want: 2147483647}, + test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: 1, want: -2147483648}, + test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: 1, want: -2147483648}, + test_int32{fn: sub_Neg2147483647_int32, fnname: "sub_Neg2147483647_int32", in: 2147483647, want: 2}, + test_int32{fn: sub_int32_Neg2147483647, fnname: "sub_int32_Neg2147483647", in: 2147483647, want: -2}, + test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: -2147483648, want: 2147483647}, + test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: -2147483648, want: -2147483647}, + test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: -2147483647, want: 2147483646}, + test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: -2147483647, want: -2147483646}, + test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: -1, want: 0}, + test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: -1, want: 0}, + test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: 0, want: -1}, + test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: 0, want: 1}, + test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: 1, want: -2}, + test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: 1, want: 2}, + test_int32{fn: sub_Neg1_int32, fnname: "sub_Neg1_int32", in: 2147483647, want: -2147483648}, + test_int32{fn: sub_int32_Neg1, fnname: "sub_int32_Neg1", in: 2147483647, want: -2147483648}, + test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: -2147483648, want: -2147483648}, + test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: -2147483648, want: -2147483648}, + test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: -2147483647, want: 2147483647}, + test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: -2147483647, want: -2147483647}, + test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: -1, want: 1}, + test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: -1, want: -1}, + test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: 0, want: 0}, + test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: 0, want: 0}, + test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: 1, want: -1}, + test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: 1, want: 1}, + test_int32{fn: sub_0_int32, fnname: "sub_0_int32", in: 2147483647, want: -2147483647}, + test_int32{fn: sub_int32_0, fnname: "sub_int32_0", in: 2147483647, want: 2147483647}, + test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: -2147483648, want: -2147483647}, + test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: -2147483648, want: 2147483647}, + test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: -2147483647, want: -2147483648}, + test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: -2147483647, want: -2147483648}, + test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: -1, want: 2}, + test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: -1, want: -2}, + test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: 0, want: 1}, + test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: 0, want: -1}, + test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: 1, want: 0}, + test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: 1, want: 0}, + test_int32{fn: sub_1_int32, fnname: "sub_1_int32", in: 2147483647, want: -2147483646}, + test_int32{fn: sub_int32_1, fnname: "sub_int32_1", in: 2147483647, want: 2147483646}, + test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: -2147483648, want: -1}, + test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: -2147483648, want: 1}, + test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: -2147483647, want: -2}, + test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: -2147483647, want: 2}, + test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: -1, want: -2147483648}, + test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: -1, want: -2147483648}, + test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: 0, want: 2147483647}, + test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: 0, want: -2147483647}, + test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: 1, want: 2147483646}, + test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: 1, want: -2147483646}, + test_int32{fn: sub_2147483647_int32, fnname: "sub_2147483647_int32", in: 2147483647, want: 0}, + test_int32{fn: sub_int32_2147483647, fnname: "sub_int32_2147483647", in: 2147483647, want: 0}, + test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: -2147483648, want: 1}, + test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: -2147483648, want: 1}, + test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: -2147483647, want: 1}, + test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: -2147483647, want: 0}, + test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: -1, want: -2147483648}, + test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: -1, want: 0}, + test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: 0, want: 0}, + test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: 1, want: -2147483648}, + test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: 1, want: 0}, + test_int32{fn: div_Neg2147483648_int32, fnname: "div_Neg2147483648_int32", in: 2147483647, want: -1}, + test_int32{fn: div_int32_Neg2147483648, fnname: "div_int32_Neg2147483648", in: 2147483647, want: 0}, + test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: -2147483648, want: 0}, + test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: -2147483648, want: 1}, + test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: -2147483647, want: 1}, + test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: -2147483647, want: 1}, + test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: -1, want: 2147483647}, + test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: -1, want: 0}, + test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: 0, want: 0}, + test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: 1, want: -2147483647}, + test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: 1, want: 0}, + test_int32{fn: div_Neg2147483647_int32, fnname: "div_Neg2147483647_int32", in: 2147483647, want: -1}, + test_int32{fn: div_int32_Neg2147483647, fnname: "div_int32_Neg2147483647", in: 2147483647, want: -1}, + test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: -2147483648, want: 0}, + test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: -2147483648, want: -2147483648}, + test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: -2147483647, want: 0}, + test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: -2147483647, want: 2147483647}, + test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: -1, want: 1}, + test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: -1, want: 1}, + test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: 0, want: 0}, + test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: 1, want: -1}, + test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: 1, want: -1}, + test_int32{fn: div_Neg1_int32, fnname: "div_Neg1_int32", in: 2147483647, want: 0}, + test_int32{fn: div_int32_Neg1, fnname: "div_int32_Neg1", in: 2147483647, want: -2147483647}, + test_int32{fn: div_0_int32, fnname: "div_0_int32", in: -2147483648, want: 0}, + test_int32{fn: div_0_int32, fnname: "div_0_int32", in: -2147483647, want: 0}, + test_int32{fn: div_0_int32, fnname: "div_0_int32", in: -1, want: 0}, + test_int32{fn: div_0_int32, fnname: "div_0_int32", in: 1, want: 0}, + test_int32{fn: div_0_int32, fnname: "div_0_int32", in: 2147483647, want: 0}, + test_int32{fn: div_1_int32, fnname: "div_1_int32", in: -2147483648, want: 0}, + test_int32{fn: div_int32_1, fnname: "div_int32_1", in: -2147483648, want: -2147483648}, + test_int32{fn: div_1_int32, fnname: "div_1_int32", in: -2147483647, want: 0}, + test_int32{fn: div_int32_1, fnname: "div_int32_1", in: -2147483647, want: -2147483647}, + test_int32{fn: div_1_int32, fnname: "div_1_int32", in: -1, want: -1}, + test_int32{fn: div_int32_1, fnname: "div_int32_1", in: -1, want: -1}, + test_int32{fn: div_int32_1, fnname: "div_int32_1", in: 0, want: 0}, + test_int32{fn: div_1_int32, fnname: "div_1_int32", in: 1, want: 1}, + test_int32{fn: div_int32_1, fnname: "div_int32_1", in: 1, want: 1}, + test_int32{fn: div_1_int32, fnname: "div_1_int32", in: 2147483647, want: 0}, + test_int32{fn: div_int32_1, fnname: "div_int32_1", in: 2147483647, want: 2147483647}, + test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: -2147483648, want: 0}, + test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: -2147483648, want: -1}, + test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: -2147483647, want: -1}, + test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: -2147483647, want: -1}, + test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: -1, want: -2147483647}, + test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: -1, want: 0}, + test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: 0, want: 0}, + test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: 1, want: 2147483647}, + test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: 1, want: 0}, + test_int32{fn: div_2147483647_int32, fnname: "div_2147483647_int32", in: 2147483647, want: 1}, + test_int32{fn: div_int32_2147483647, fnname: "div_int32_2147483647", in: 2147483647, want: 1}, + test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: -2147483648, want: 0}, + test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: -2147483648, want: 0}, + test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: -2147483647, want: -2147483648}, + test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: -2147483647, want: -2147483648}, + test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: -1, want: -2147483648}, + test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: -1, want: -2147483648}, + test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: 0, want: 0}, + test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: 0, want: 0}, + test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: 1, want: -2147483648}, + test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: 1, want: -2147483648}, + test_int32{fn: mul_Neg2147483648_int32, fnname: "mul_Neg2147483648_int32", in: 2147483647, want: -2147483648}, + test_int32{fn: mul_int32_Neg2147483648, fnname: "mul_int32_Neg2147483648", in: 2147483647, want: -2147483648}, + test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: -2147483648, want: -2147483648}, + test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: -2147483648, want: -2147483648}, + test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: -2147483647, want: 1}, + test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: -2147483647, want: 1}, + test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: -1, want: 2147483647}, + test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: -1, want: 2147483647}, + test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: 0, want: 0}, + test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: 0, want: 0}, + test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: 1, want: -2147483647}, + test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: 1, want: -2147483647}, + test_int32{fn: mul_Neg2147483647_int32, fnname: "mul_Neg2147483647_int32", in: 2147483647, want: -1}, + test_int32{fn: mul_int32_Neg2147483647, fnname: "mul_int32_Neg2147483647", in: 2147483647, want: -1}, + test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: -2147483648, want: -2147483648}, + test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: -2147483648, want: -2147483648}, + test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: -2147483647, want: 2147483647}, + test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: -2147483647, want: 2147483647}, + test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: -1, want: 1}, + test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: -1, want: 1}, + test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: 0, want: 0}, + test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: 0, want: 0}, + test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: 1, want: -1}, + test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: 1, want: -1}, + test_int32{fn: mul_Neg1_int32, fnname: "mul_Neg1_int32", in: 2147483647, want: -2147483647}, + test_int32{fn: mul_int32_Neg1, fnname: "mul_int32_Neg1", in: 2147483647, want: -2147483647}, + test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: -2147483648, want: 0}, + test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: -2147483648, want: 0}, + test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: -2147483647, want: 0}, + test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: -2147483647, want: 0}, + test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: -1, want: 0}, + test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: -1, want: 0}, + test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: 0, want: 0}, + test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: 0, want: 0}, + test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: 1, want: 0}, + test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: 1, want: 0}, + test_int32{fn: mul_0_int32, fnname: "mul_0_int32", in: 2147483647, want: 0}, + test_int32{fn: mul_int32_0, fnname: "mul_int32_0", in: 2147483647, want: 0}, + test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: -2147483648, want: -2147483648}, + test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: -2147483648, want: -2147483648}, + test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: -2147483647, want: -2147483647}, + test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: -2147483647, want: -2147483647}, + test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: -1, want: -1}, + test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: -1, want: -1}, + test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: 0, want: 0}, + test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: 0, want: 0}, + test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: 1, want: 1}, + test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: 1, want: 1}, + test_int32{fn: mul_1_int32, fnname: "mul_1_int32", in: 2147483647, want: 2147483647}, + test_int32{fn: mul_int32_1, fnname: "mul_int32_1", in: 2147483647, want: 2147483647}, + test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: -2147483648, want: -2147483648}, + test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: -2147483648, want: -2147483648}, + test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: -2147483647, want: -1}, + test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: -2147483647, want: -1}, + test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: -1, want: -2147483647}, + test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: -1, want: -2147483647}, + test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: 0, want: 0}, + test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: 0, want: 0}, + test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: 1, want: 2147483647}, + test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: 1, want: 2147483647}, + test_int32{fn: mul_2147483647_int32, fnname: "mul_2147483647_int32", in: 2147483647, want: 1}, + test_int32{fn: mul_int32_2147483647, fnname: "mul_int32_2147483647", in: 2147483647, want: 1}, + test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: -2147483648, want: 0}, + test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: -2147483648, want: 0}, + test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: -2147483647, want: -1}, + test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: -2147483647, want: -2147483647}, + test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: -1, want: 0}, + test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: -1, want: -1}, + test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: 0, want: 0}, + test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: 1, want: 0}, + test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: 1, want: 1}, + test_int32{fn: mod_Neg2147483648_int32, fnname: "mod_Neg2147483648_int32", in: 2147483647, want: -1}, + test_int32{fn: mod_int32_Neg2147483648, fnname: "mod_int32_Neg2147483648", in: 2147483647, want: 2147483647}, + test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: -2147483648, want: -2147483647}, + test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: -2147483648, want: -1}, + test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: -2147483647, want: 0}, + test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: -2147483647, want: 0}, + test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: -1, want: 0}, + test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: -1, want: -1}, + test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: 0, want: 0}, + test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: 1, want: 0}, + test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: 1, want: 1}, + test_int32{fn: mod_Neg2147483647_int32, fnname: "mod_Neg2147483647_int32", in: 2147483647, want: 0}, + test_int32{fn: mod_int32_Neg2147483647, fnname: "mod_int32_Neg2147483647", in: 2147483647, want: 0}, + test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: -2147483648, want: -1}, + test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: -2147483648, want: 0}, + test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: -2147483647, want: -1}, + test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: -2147483647, want: 0}, + test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: -1, want: 0}, + test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: -1, want: 0}, + test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: 0, want: 0}, + test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: 1, want: 0}, + test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: 1, want: 0}, + test_int32{fn: mod_Neg1_int32, fnname: "mod_Neg1_int32", in: 2147483647, want: -1}, + test_int32{fn: mod_int32_Neg1, fnname: "mod_int32_Neg1", in: 2147483647, want: 0}, + test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: -2147483648, want: 0}, + test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: -2147483647, want: 0}, + test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: -1, want: 0}, + test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: 1, want: 0}, + test_int32{fn: mod_0_int32, fnname: "mod_0_int32", in: 2147483647, want: 0}, + test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: -2147483648, want: 1}, + test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: -2147483648, want: 0}, + test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: -2147483647, want: 1}, + test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: -2147483647, want: 0}, + test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: -1, want: 0}, + test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: -1, want: 0}, + test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: 0, want: 0}, + test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: 1, want: 0}, + test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: 1, want: 0}, + test_int32{fn: mod_1_int32, fnname: "mod_1_int32", in: 2147483647, want: 1}, + test_int32{fn: mod_int32_1, fnname: "mod_int32_1", in: 2147483647, want: 0}, + test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: -2147483648, want: 2147483647}, + test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: -2147483648, want: -1}, + test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: -2147483647, want: 0}, + test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: -2147483647, want: 0}, + test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: -1, want: 0}, + test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: -1, want: -1}, + test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: 0, want: 0}, + test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: 1, want: 0}, + test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: 1, want: 1}, + test_int32{fn: mod_2147483647_int32, fnname: "mod_2147483647_int32", in: 2147483647, want: 0}, + test_int32{fn: mod_int32_2147483647, fnname: "mod_int32_2147483647", in: 2147483647, want: 0}, + test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: -2147483648, want: -2147483648}, + test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: -2147483648, want: -2147483648}, + test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: -2147483647, want: -2147483648}, + test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: -2147483647, want: -2147483648}, + test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: -1, want: -2147483648}, + test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: -1, want: -2147483648}, + test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: 0, want: 0}, + test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: 0, want: 0}, + test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: 1, want: 0}, + test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: 1, want: 0}, + test_int32{fn: and_Neg2147483648_int32, fnname: "and_Neg2147483648_int32", in: 2147483647, want: 0}, + test_int32{fn: and_int32_Neg2147483648, fnname: "and_int32_Neg2147483648", in: 2147483647, want: 0}, + test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: -2147483648, want: -2147483648}, + test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: -2147483648, want: -2147483648}, + test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: -2147483647, want: -2147483647}, + test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: -2147483647, want: -2147483647}, + test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: -1, want: -2147483647}, + test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: -1, want: -2147483647}, + test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: 0, want: 0}, + test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: 0, want: 0}, + test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: 1, want: 1}, + test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: 1, want: 1}, + test_int32{fn: and_Neg2147483647_int32, fnname: "and_Neg2147483647_int32", in: 2147483647, want: 1}, + test_int32{fn: and_int32_Neg2147483647, fnname: "and_int32_Neg2147483647", in: 2147483647, want: 1}, + test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: -2147483648, want: -2147483648}, + test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: -2147483648, want: -2147483648}, + test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: -2147483647, want: -2147483647}, + test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: -2147483647, want: -2147483647}, + test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: -1, want: -1}, + test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: -1, want: -1}, + test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: 0, want: 0}, + test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: 0, want: 0}, + test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: 1, want: 1}, + test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: 1, want: 1}, + test_int32{fn: and_Neg1_int32, fnname: "and_Neg1_int32", in: 2147483647, want: 2147483647}, + test_int32{fn: and_int32_Neg1, fnname: "and_int32_Neg1", in: 2147483647, want: 2147483647}, + test_int32{fn: and_0_int32, fnname: "and_0_int32", in: -2147483648, want: 0}, + test_int32{fn: and_int32_0, fnname: "and_int32_0", in: -2147483648, want: 0}, + test_int32{fn: and_0_int32, fnname: "and_0_int32", in: -2147483647, want: 0}, + test_int32{fn: and_int32_0, fnname: "and_int32_0", in: -2147483647, want: 0}, + test_int32{fn: and_0_int32, fnname: "and_0_int32", in: -1, want: 0}, + test_int32{fn: and_int32_0, fnname: "and_int32_0", in: -1, want: 0}, + test_int32{fn: and_0_int32, fnname: "and_0_int32", in: 0, want: 0}, + test_int32{fn: and_int32_0, fnname: "and_int32_0", in: 0, want: 0}, + test_int32{fn: and_0_int32, fnname: "and_0_int32", in: 1, want: 0}, + test_int32{fn: and_int32_0, fnname: "and_int32_0", in: 1, want: 0}, + test_int32{fn: and_0_int32, fnname: "and_0_int32", in: 2147483647, want: 0}, + test_int32{fn: and_int32_0, fnname: "and_int32_0", in: 2147483647, want: 0}, + test_int32{fn: and_1_int32, fnname: "and_1_int32", in: -2147483648, want: 0}, + test_int32{fn: and_int32_1, fnname: "and_int32_1", in: -2147483648, want: 0}, + test_int32{fn: and_1_int32, fnname: "and_1_int32", in: -2147483647, want: 1}, + test_int32{fn: and_int32_1, fnname: "and_int32_1", in: -2147483647, want: 1}, + test_int32{fn: and_1_int32, fnname: "and_1_int32", in: -1, want: 1}, + test_int32{fn: and_int32_1, fnname: "and_int32_1", in: -1, want: 1}, + test_int32{fn: and_1_int32, fnname: "and_1_int32", in: 0, want: 0}, + test_int32{fn: and_int32_1, fnname: "and_int32_1", in: 0, want: 0}, + test_int32{fn: and_1_int32, fnname: "and_1_int32", in: 1, want: 1}, + test_int32{fn: and_int32_1, fnname: "and_int32_1", in: 1, want: 1}, + test_int32{fn: and_1_int32, fnname: "and_1_int32", in: 2147483647, want: 1}, + test_int32{fn: and_int32_1, fnname: "and_int32_1", in: 2147483647, want: 1}, + test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: -2147483648, want: 0}, + test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: -2147483648, want: 0}, + test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: -2147483647, want: 1}, + test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: -2147483647, want: 1}, + test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: -1, want: 2147483647}, + test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: -1, want: 2147483647}, + test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: 0, want: 0}, + test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: 0, want: 0}, + test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: 1, want: 1}, + test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: 1, want: 1}, + test_int32{fn: and_2147483647_int32, fnname: "and_2147483647_int32", in: 2147483647, want: 2147483647}, + test_int32{fn: and_int32_2147483647, fnname: "and_int32_2147483647", in: 2147483647, want: 2147483647}, + test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: -2147483648, want: -2147483648}, + test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: -2147483648, want: -2147483648}, + test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: -2147483647, want: -2147483647}, + test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: -2147483647, want: -2147483647}, + test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: -1, want: -1}, + test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: -1, want: -1}, + test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: 0, want: -2147483648}, + test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: 0, want: -2147483648}, + test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: 1, want: -2147483647}, + test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: 1, want: -2147483647}, + test_int32{fn: or_Neg2147483648_int32, fnname: "or_Neg2147483648_int32", in: 2147483647, want: -1}, + test_int32{fn: or_int32_Neg2147483648, fnname: "or_int32_Neg2147483648", in: 2147483647, want: -1}, + test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: -2147483648, want: -2147483647}, + test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: -2147483648, want: -2147483647}, + test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: -2147483647, want: -2147483647}, + test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: -2147483647, want: -2147483647}, + test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: -1, want: -1}, + test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: -1, want: -1}, + test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: 0, want: -2147483647}, + test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: 0, want: -2147483647}, + test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: 1, want: -2147483647}, + test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: 1, want: -2147483647}, + test_int32{fn: or_Neg2147483647_int32, fnname: "or_Neg2147483647_int32", in: 2147483647, want: -1}, + test_int32{fn: or_int32_Neg2147483647, fnname: "or_int32_Neg2147483647", in: 2147483647, want: -1}, + test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: -2147483648, want: -1}, + test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: -2147483648, want: -1}, + test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: -2147483647, want: -1}, + test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: -2147483647, want: -1}, + test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: -1, want: -1}, + test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: -1, want: -1}, + test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: 0, want: -1}, + test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: 0, want: -1}, + test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: 1, want: -1}, + test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: 1, want: -1}, + test_int32{fn: or_Neg1_int32, fnname: "or_Neg1_int32", in: 2147483647, want: -1}, + test_int32{fn: or_int32_Neg1, fnname: "or_int32_Neg1", in: 2147483647, want: -1}, + test_int32{fn: or_0_int32, fnname: "or_0_int32", in: -2147483648, want: -2147483648}, + test_int32{fn: or_int32_0, fnname: "or_int32_0", in: -2147483648, want: -2147483648}, + test_int32{fn: or_0_int32, fnname: "or_0_int32", in: -2147483647, want: -2147483647}, + test_int32{fn: or_int32_0, fnname: "or_int32_0", in: -2147483647, want: -2147483647}, + test_int32{fn: or_0_int32, fnname: "or_0_int32", in: -1, want: -1}, + test_int32{fn: or_int32_0, fnname: "or_int32_0", in: -1, want: -1}, + test_int32{fn: or_0_int32, fnname: "or_0_int32", in: 0, want: 0}, + test_int32{fn: or_int32_0, fnname: "or_int32_0", in: 0, want: 0}, + test_int32{fn: or_0_int32, fnname: "or_0_int32", in: 1, want: 1}, + test_int32{fn: or_int32_0, fnname: "or_int32_0", in: 1, want: 1}, + test_int32{fn: or_0_int32, fnname: "or_0_int32", in: 2147483647, want: 2147483647}, + test_int32{fn: or_int32_0, fnname: "or_int32_0", in: 2147483647, want: 2147483647}, + test_int32{fn: or_1_int32, fnname: "or_1_int32", in: -2147483648, want: -2147483647}, + test_int32{fn: or_int32_1, fnname: "or_int32_1", in: -2147483648, want: -2147483647}, + test_int32{fn: or_1_int32, fnname: "or_1_int32", in: -2147483647, want: -2147483647}, + test_int32{fn: or_int32_1, fnname: "or_int32_1", in: -2147483647, want: -2147483647}, + test_int32{fn: or_1_int32, fnname: "or_1_int32", in: -1, want: -1}, + test_int32{fn: or_int32_1, fnname: "or_int32_1", in: -1, want: -1}, + test_int32{fn: or_1_int32, fnname: "or_1_int32", in: 0, want: 1}, + test_int32{fn: or_int32_1, fnname: "or_int32_1", in: 0, want: 1}, + test_int32{fn: or_1_int32, fnname: "or_1_int32", in: 1, want: 1}, + test_int32{fn: or_int32_1, fnname: "or_int32_1", in: 1, want: 1}, + test_int32{fn: or_1_int32, fnname: "or_1_int32", in: 2147483647, want: 2147483647}, + test_int32{fn: or_int32_1, fnname: "or_int32_1", in: 2147483647, want: 2147483647}, + test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: -2147483648, want: -1}, + test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: -2147483648, want: -1}, + test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: -2147483647, want: -1}, + test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: -2147483647, want: -1}, + test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: -1, want: -1}, + test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: -1, want: -1}, + test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: 0, want: 2147483647}, + test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: 0, want: 2147483647}, + test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: 1, want: 2147483647}, + test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: 1, want: 2147483647}, + test_int32{fn: or_2147483647_int32, fnname: "or_2147483647_int32", in: 2147483647, want: 2147483647}, + test_int32{fn: or_int32_2147483647, fnname: "or_int32_2147483647", in: 2147483647, want: 2147483647}, + test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: -2147483648, want: 0}, + test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: -2147483648, want: 0}, + test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: -2147483647, want: 1}, + test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: -2147483647, want: 1}, + test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: -1, want: 2147483647}, + test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: -1, want: 2147483647}, + test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: 0, want: -2147483648}, + test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: 0, want: -2147483648}, + test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: 1, want: -2147483647}, + test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: 1, want: -2147483647}, + test_int32{fn: xor_Neg2147483648_int32, fnname: "xor_Neg2147483648_int32", in: 2147483647, want: -1}, + test_int32{fn: xor_int32_Neg2147483648, fnname: "xor_int32_Neg2147483648", in: 2147483647, want: -1}, + test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: -2147483648, want: 1}, + test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: -2147483648, want: 1}, + test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: -2147483647, want: 0}, + test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: -2147483647, want: 0}, + test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: -1, want: 2147483646}, + test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: -1, want: 2147483646}, + test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: 0, want: -2147483647}, + test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: 0, want: -2147483647}, + test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: 1, want: -2147483648}, + test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: 1, want: -2147483648}, + test_int32{fn: xor_Neg2147483647_int32, fnname: "xor_Neg2147483647_int32", in: 2147483647, want: -2}, + test_int32{fn: xor_int32_Neg2147483647, fnname: "xor_int32_Neg2147483647", in: 2147483647, want: -2}, + test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: -2147483648, want: 2147483647}, + test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: -2147483648, want: 2147483647}, + test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: -2147483647, want: 2147483646}, + test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: -2147483647, want: 2147483646}, + test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: -1, want: 0}, + test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: -1, want: 0}, + test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: 0, want: -1}, + test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: 0, want: -1}, + test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: 1, want: -2}, + test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: 1, want: -2}, + test_int32{fn: xor_Neg1_int32, fnname: "xor_Neg1_int32", in: 2147483647, want: -2147483648}, + test_int32{fn: xor_int32_Neg1, fnname: "xor_int32_Neg1", in: 2147483647, want: -2147483648}, + test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: -2147483648, want: -2147483648}, + test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: -2147483648, want: -2147483648}, + test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: -2147483647, want: -2147483647}, + test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: -2147483647, want: -2147483647}, + test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: -1, want: -1}, + test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: -1, want: -1}, + test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: 0, want: 0}, + test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: 0, want: 0}, + test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: 1, want: 1}, + test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: 1, want: 1}, + test_int32{fn: xor_0_int32, fnname: "xor_0_int32", in: 2147483647, want: 2147483647}, + test_int32{fn: xor_int32_0, fnname: "xor_int32_0", in: 2147483647, want: 2147483647}, + test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: -2147483648, want: -2147483647}, + test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: -2147483648, want: -2147483647}, + test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: -2147483647, want: -2147483648}, + test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: -2147483647, want: -2147483648}, + test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: -1, want: -2}, + test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: -1, want: -2}, + test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: 0, want: 1}, + test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: 0, want: 1}, + test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: 1, want: 0}, + test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: 1, want: 0}, + test_int32{fn: xor_1_int32, fnname: "xor_1_int32", in: 2147483647, want: 2147483646}, + test_int32{fn: xor_int32_1, fnname: "xor_int32_1", in: 2147483647, want: 2147483646}, + test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: -2147483648, want: -1}, + test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: -2147483648, want: -1}, + test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: -2147483647, want: -2}, + test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: -2147483647, want: -2}, + test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: -1, want: -2147483648}, + test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: -1, want: -2147483648}, + test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: 0, want: 2147483647}, + test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: 0, want: 2147483647}, + test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: 1, want: 2147483646}, + test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: 1, want: 2147483646}, + test_int32{fn: xor_2147483647_int32, fnname: "xor_2147483647_int32", in: 2147483647, want: 0}, + test_int32{fn: xor_int32_2147483647, fnname: "xor_int32_2147483647", in: 2147483647, want: 0}} + +type test_uint16 struct { + fn func(uint16) uint16 + fnname string + in uint16 + want uint16 } -//go:noinline -func xor_126_int8_ssa(a int8) int8 { - return 126 ^ a +var tests_uint16 = []test_uint16{ + + test_uint16{fn: add_0_uint16, fnname: "add_0_uint16", in: 0, want: 0}, + test_uint16{fn: add_uint16_0, fnname: "add_uint16_0", in: 0, want: 0}, + test_uint16{fn: add_0_uint16, fnname: "add_0_uint16", in: 1, want: 1}, + test_uint16{fn: add_uint16_0, fnname: "add_uint16_0", in: 1, want: 1}, + test_uint16{fn: add_0_uint16, fnname: "add_0_uint16", in: 65535, want: 65535}, + test_uint16{fn: add_uint16_0, fnname: "add_uint16_0", in: 65535, want: 65535}, + test_uint16{fn: add_1_uint16, fnname: "add_1_uint16", in: 0, want: 1}, + test_uint16{fn: add_uint16_1, fnname: "add_uint16_1", in: 0, want: 1}, + test_uint16{fn: add_1_uint16, fnname: "add_1_uint16", in: 1, want: 2}, + test_uint16{fn: add_uint16_1, fnname: "add_uint16_1", in: 1, want: 2}, + test_uint16{fn: add_1_uint16, fnname: "add_1_uint16", in: 65535, want: 0}, + test_uint16{fn: add_uint16_1, fnname: "add_uint16_1", in: 65535, want: 0}, + test_uint16{fn: add_65535_uint16, fnname: "add_65535_uint16", in: 0, want: 65535}, + test_uint16{fn: add_uint16_65535, fnname: "add_uint16_65535", in: 0, want: 65535}, + test_uint16{fn: add_65535_uint16, fnname: "add_65535_uint16", in: 1, want: 0}, + test_uint16{fn: add_uint16_65535, fnname: "add_uint16_65535", in: 1, want: 0}, + test_uint16{fn: add_65535_uint16, fnname: "add_65535_uint16", in: 65535, want: 65534}, + test_uint16{fn: add_uint16_65535, fnname: "add_uint16_65535", in: 65535, want: 65534}, + test_uint16{fn: sub_0_uint16, fnname: "sub_0_uint16", in: 0, want: 0}, + test_uint16{fn: sub_uint16_0, fnname: "sub_uint16_0", in: 0, want: 0}, + test_uint16{fn: sub_0_uint16, fnname: "sub_0_uint16", in: 1, want: 65535}, + test_uint16{fn: sub_uint16_0, fnname: "sub_uint16_0", in: 1, want: 1}, + test_uint16{fn: sub_0_uint16, fnname: "sub_0_uint16", in: 65535, want: 1}, + test_uint16{fn: sub_uint16_0, fnname: "sub_uint16_0", in: 65535, want: 65535}, + test_uint16{fn: sub_1_uint16, fnname: "sub_1_uint16", in: 0, want: 1}, + test_uint16{fn: sub_uint16_1, fnname: "sub_uint16_1", in: 0, want: 65535}, + test_uint16{fn: sub_1_uint16, fnname: "sub_1_uint16", in: 1, want: 0}, + test_uint16{fn: sub_uint16_1, fnname: "sub_uint16_1", in: 1, want: 0}, + test_uint16{fn: sub_1_uint16, fnname: "sub_1_uint16", in: 65535, want: 2}, + test_uint16{fn: sub_uint16_1, fnname: "sub_uint16_1", in: 65535, want: 65534}, + test_uint16{fn: sub_65535_uint16, fnname: "sub_65535_uint16", in: 0, want: 65535}, + test_uint16{fn: sub_uint16_65535, fnname: "sub_uint16_65535", in: 0, want: 1}, + test_uint16{fn: sub_65535_uint16, fnname: "sub_65535_uint16", in: 1, want: 65534}, + test_uint16{fn: sub_uint16_65535, fnname: "sub_uint16_65535", in: 1, want: 2}, + test_uint16{fn: sub_65535_uint16, fnname: "sub_65535_uint16", in: 65535, want: 0}, + test_uint16{fn: sub_uint16_65535, fnname: "sub_uint16_65535", in: 65535, want: 0}, + test_uint16{fn: div_0_uint16, fnname: "div_0_uint16", in: 1, want: 0}, + test_uint16{fn: div_0_uint16, fnname: "div_0_uint16", in: 65535, want: 0}, + test_uint16{fn: div_uint16_1, fnname: "div_uint16_1", in: 0, want: 0}, + test_uint16{fn: div_1_uint16, fnname: "div_1_uint16", in: 1, want: 1}, + test_uint16{fn: div_uint16_1, fnname: "div_uint16_1", in: 1, want: 1}, + test_uint16{fn: div_1_uint16, fnname: "div_1_uint16", in: 65535, want: 0}, + test_uint16{fn: div_uint16_1, fnname: "div_uint16_1", in: 65535, want: 65535}, + test_uint16{fn: div_uint16_65535, fnname: "div_uint16_65535", in: 0, want: 0}, + test_uint16{fn: div_65535_uint16, fnname: "div_65535_uint16", in: 1, want: 65535}, + test_uint16{fn: div_uint16_65535, fnname: "div_uint16_65535", in: 1, want: 0}, + test_uint16{fn: div_65535_uint16, fnname: "div_65535_uint16", in: 65535, want: 1}, + test_uint16{fn: div_uint16_65535, fnname: "div_uint16_65535", in: 65535, want: 1}, + test_uint16{fn: mul_0_uint16, fnname: "mul_0_uint16", in: 0, want: 0}, + test_uint16{fn: mul_uint16_0, fnname: "mul_uint16_0", in: 0, want: 0}, + test_uint16{fn: mul_0_uint16, fnname: "mul_0_uint16", in: 1, want: 0}, + test_uint16{fn: mul_uint16_0, fnname: "mul_uint16_0", in: 1, want: 0}, + test_uint16{fn: mul_0_uint16, fnname: "mul_0_uint16", in: 65535, want: 0}, + test_uint16{fn: mul_uint16_0, fnname: "mul_uint16_0", in: 65535, want: 0}, + test_uint16{fn: mul_1_uint16, fnname: "mul_1_uint16", in: 0, want: 0}, + test_uint16{fn: mul_uint16_1, fnname: "mul_uint16_1", in: 0, want: 0}, + test_uint16{fn: mul_1_uint16, fnname: "mul_1_uint16", in: 1, want: 1}, + test_uint16{fn: mul_uint16_1, fnname: "mul_uint16_1", in: 1, want: 1}, + test_uint16{fn: mul_1_uint16, fnname: "mul_1_uint16", in: 65535, want: 65535}, + test_uint16{fn: mul_uint16_1, fnname: "mul_uint16_1", in: 65535, want: 65535}, + test_uint16{fn: mul_65535_uint16, fnname: "mul_65535_uint16", in: 0, want: 0}, + test_uint16{fn: mul_uint16_65535, fnname: "mul_uint16_65535", in: 0, want: 0}, + test_uint16{fn: mul_65535_uint16, fnname: "mul_65535_uint16", in: 1, want: 65535}, + test_uint16{fn: mul_uint16_65535, fnname: "mul_uint16_65535", in: 1, want: 65535}, + test_uint16{fn: mul_65535_uint16, fnname: "mul_65535_uint16", in: 65535, want: 1}, + test_uint16{fn: mul_uint16_65535, fnname: "mul_uint16_65535", in: 65535, want: 1}, + test_uint16{fn: lsh_0_uint16, fnname: "lsh_0_uint16", in: 0, want: 0}, + test_uint16{fn: lsh_uint16_0, fnname: "lsh_uint16_0", in: 0, want: 0}, + test_uint16{fn: lsh_0_uint16, fnname: "lsh_0_uint16", in: 1, want: 0}, + test_uint16{fn: lsh_uint16_0, fnname: "lsh_uint16_0", in: 1, want: 1}, + test_uint16{fn: lsh_0_uint16, fnname: "lsh_0_uint16", in: 65535, want: 0}, + test_uint16{fn: lsh_uint16_0, fnname: "lsh_uint16_0", in: 65535, want: 65535}, + test_uint16{fn: lsh_1_uint16, fnname: "lsh_1_uint16", in: 0, want: 1}, + test_uint16{fn: lsh_uint16_1, fnname: "lsh_uint16_1", in: 0, want: 0}, + test_uint16{fn: lsh_1_uint16, fnname: "lsh_1_uint16", in: 1, want: 2}, + test_uint16{fn: lsh_uint16_1, fnname: "lsh_uint16_1", in: 1, want: 2}, + test_uint16{fn: lsh_1_uint16, fnname: "lsh_1_uint16", in: 65535, want: 0}, + test_uint16{fn: lsh_uint16_1, fnname: "lsh_uint16_1", in: 65535, want: 65534}, + test_uint16{fn: lsh_65535_uint16, fnname: "lsh_65535_uint16", in: 0, want: 65535}, + test_uint16{fn: lsh_uint16_65535, fnname: "lsh_uint16_65535", in: 0, want: 0}, + test_uint16{fn: lsh_65535_uint16, fnname: "lsh_65535_uint16", in: 1, want: 65534}, + test_uint16{fn: lsh_uint16_65535, fnname: "lsh_uint16_65535", in: 1, want: 0}, + test_uint16{fn: lsh_65535_uint16, fnname: "lsh_65535_uint16", in: 65535, want: 0}, + test_uint16{fn: lsh_uint16_65535, fnname: "lsh_uint16_65535", in: 65535, want: 0}, + test_uint16{fn: rsh_0_uint16, fnname: "rsh_0_uint16", in: 0, want: 0}, + test_uint16{fn: rsh_uint16_0, fnname: "rsh_uint16_0", in: 0, want: 0}, + test_uint16{fn: rsh_0_uint16, fnname: "rsh_0_uint16", in: 1, want: 0}, + test_uint16{fn: rsh_uint16_0, fnname: "rsh_uint16_0", in: 1, want: 1}, + test_uint16{fn: rsh_0_uint16, fnname: "rsh_0_uint16", in: 65535, want: 0}, + test_uint16{fn: rsh_uint16_0, fnname: "rsh_uint16_0", in: 65535, want: 65535}, + test_uint16{fn: rsh_1_uint16, fnname: "rsh_1_uint16", in: 0, want: 1}, + test_uint16{fn: rsh_uint16_1, fnname: "rsh_uint16_1", in: 0, want: 0}, + test_uint16{fn: rsh_1_uint16, fnname: "rsh_1_uint16", in: 1, want: 0}, + test_uint16{fn: rsh_uint16_1, fnname: "rsh_uint16_1", in: 1, want: 0}, + test_uint16{fn: rsh_1_uint16, fnname: "rsh_1_uint16", in: 65535, want: 0}, + test_uint16{fn: rsh_uint16_1, fnname: "rsh_uint16_1", in: 65535, want: 32767}, + test_uint16{fn: rsh_65535_uint16, fnname: "rsh_65535_uint16", in: 0, want: 65535}, + test_uint16{fn: rsh_uint16_65535, fnname: "rsh_uint16_65535", in: 0, want: 0}, + test_uint16{fn: rsh_65535_uint16, fnname: "rsh_65535_uint16", in: 1, want: 32767}, + test_uint16{fn: rsh_uint16_65535, fnname: "rsh_uint16_65535", in: 1, want: 0}, + test_uint16{fn: rsh_65535_uint16, fnname: "rsh_65535_uint16", in: 65535, want: 0}, + test_uint16{fn: rsh_uint16_65535, fnname: "rsh_uint16_65535", in: 65535, want: 0}, + test_uint16{fn: mod_0_uint16, fnname: "mod_0_uint16", in: 1, want: 0}, + test_uint16{fn: mod_0_uint16, fnname: "mod_0_uint16", in: 65535, want: 0}, + test_uint16{fn: mod_uint16_1, fnname: "mod_uint16_1", in: 0, want: 0}, + test_uint16{fn: mod_1_uint16, fnname: "mod_1_uint16", in: 1, want: 0}, + test_uint16{fn: mod_uint16_1, fnname: "mod_uint16_1", in: 1, want: 0}, + test_uint16{fn: mod_1_uint16, fnname: "mod_1_uint16", in: 65535, want: 1}, + test_uint16{fn: mod_uint16_1, fnname: "mod_uint16_1", in: 65535, want: 0}, + test_uint16{fn: mod_uint16_65535, fnname: "mod_uint16_65535", in: 0, want: 0}, + test_uint16{fn: mod_65535_uint16, fnname: "mod_65535_uint16", in: 1, want: 0}, + test_uint16{fn: mod_uint16_65535, fnname: "mod_uint16_65535", in: 1, want: 1}, + test_uint16{fn: mod_65535_uint16, fnname: "mod_65535_uint16", in: 65535, want: 0}, + test_uint16{fn: mod_uint16_65535, fnname: "mod_uint16_65535", in: 65535, want: 0}, + test_uint16{fn: and_0_uint16, fnname: "and_0_uint16", in: 0, want: 0}, + test_uint16{fn: and_uint16_0, fnname: "and_uint16_0", in: 0, want: 0}, + test_uint16{fn: and_0_uint16, fnname: "and_0_uint16", in: 1, want: 0}, + test_uint16{fn: and_uint16_0, fnname: "and_uint16_0", in: 1, want: 0}, + test_uint16{fn: and_0_uint16, fnname: "and_0_uint16", in: 65535, want: 0}, + test_uint16{fn: and_uint16_0, fnname: "and_uint16_0", in: 65535, want: 0}, + test_uint16{fn: and_1_uint16, fnname: "and_1_uint16", in: 0, want: 0}, + test_uint16{fn: and_uint16_1, fnname: "and_uint16_1", in: 0, want: 0}, + test_uint16{fn: and_1_uint16, fnname: "and_1_uint16", in: 1, want: 1}, + test_uint16{fn: and_uint16_1, fnname: "and_uint16_1", in: 1, want: 1}, + test_uint16{fn: and_1_uint16, fnname: "and_1_uint16", in: 65535, want: 1}, + test_uint16{fn: and_uint16_1, fnname: "and_uint16_1", in: 65535, want: 1}, + test_uint16{fn: and_65535_uint16, fnname: "and_65535_uint16", in: 0, want: 0}, + test_uint16{fn: and_uint16_65535, fnname: "and_uint16_65535", in: 0, want: 0}, + test_uint16{fn: and_65535_uint16, fnname: "and_65535_uint16", in: 1, want: 1}, + test_uint16{fn: and_uint16_65535, fnname: "and_uint16_65535", in: 1, want: 1}, + test_uint16{fn: and_65535_uint16, fnname: "and_65535_uint16", in: 65535, want: 65535}, + test_uint16{fn: and_uint16_65535, fnname: "and_uint16_65535", in: 65535, want: 65535}, + test_uint16{fn: or_0_uint16, fnname: "or_0_uint16", in: 0, want: 0}, + test_uint16{fn: or_uint16_0, fnname: "or_uint16_0", in: 0, want: 0}, + test_uint16{fn: or_0_uint16, fnname: "or_0_uint16", in: 1, want: 1}, + test_uint16{fn: or_uint16_0, fnname: "or_uint16_0", in: 1, want: 1}, + test_uint16{fn: or_0_uint16, fnname: "or_0_uint16", in: 65535, want: 65535}, + test_uint16{fn: or_uint16_0, fnname: "or_uint16_0", in: 65535, want: 65535}, + test_uint16{fn: or_1_uint16, fnname: "or_1_uint16", in: 0, want: 1}, + test_uint16{fn: or_uint16_1, fnname: "or_uint16_1", in: 0, want: 1}, + test_uint16{fn: or_1_uint16, fnname: "or_1_uint16", in: 1, want: 1}, + test_uint16{fn: or_uint16_1, fnname: "or_uint16_1", in: 1, want: 1}, + test_uint16{fn: or_1_uint16, fnname: "or_1_uint16", in: 65535, want: 65535}, + test_uint16{fn: or_uint16_1, fnname: "or_uint16_1", in: 65535, want: 65535}, + test_uint16{fn: or_65535_uint16, fnname: "or_65535_uint16", in: 0, want: 65535}, + test_uint16{fn: or_uint16_65535, fnname: "or_uint16_65535", in: 0, want: 65535}, + test_uint16{fn: or_65535_uint16, fnname: "or_65535_uint16", in: 1, want: 65535}, + test_uint16{fn: or_uint16_65535, fnname: "or_uint16_65535", in: 1, want: 65535}, + test_uint16{fn: or_65535_uint16, fnname: "or_65535_uint16", in: 65535, want: 65535}, + test_uint16{fn: or_uint16_65535, fnname: "or_uint16_65535", in: 65535, want: 65535}, + test_uint16{fn: xor_0_uint16, fnname: "xor_0_uint16", in: 0, want: 0}, + test_uint16{fn: xor_uint16_0, fnname: "xor_uint16_0", in: 0, want: 0}, + test_uint16{fn: xor_0_uint16, fnname: "xor_0_uint16", in: 1, want: 1}, + test_uint16{fn: xor_uint16_0, fnname: "xor_uint16_0", in: 1, want: 1}, + test_uint16{fn: xor_0_uint16, fnname: "xor_0_uint16", in: 65535, want: 65535}, + test_uint16{fn: xor_uint16_0, fnname: "xor_uint16_0", in: 65535, want: 65535}, + test_uint16{fn: xor_1_uint16, fnname: "xor_1_uint16", in: 0, want: 1}, + test_uint16{fn: xor_uint16_1, fnname: "xor_uint16_1", in: 0, want: 1}, + test_uint16{fn: xor_1_uint16, fnname: "xor_1_uint16", in: 1, want: 0}, + test_uint16{fn: xor_uint16_1, fnname: "xor_uint16_1", in: 1, want: 0}, + test_uint16{fn: xor_1_uint16, fnname: "xor_1_uint16", in: 65535, want: 65534}, + test_uint16{fn: xor_uint16_1, fnname: "xor_uint16_1", in: 65535, want: 65534}, + test_uint16{fn: xor_65535_uint16, fnname: "xor_65535_uint16", in: 0, want: 65535}, + test_uint16{fn: xor_uint16_65535, fnname: "xor_uint16_65535", in: 0, want: 65535}, + test_uint16{fn: xor_65535_uint16, fnname: "xor_65535_uint16", in: 1, want: 65534}, + test_uint16{fn: xor_uint16_65535, fnname: "xor_uint16_65535", in: 1, want: 65534}, + test_uint16{fn: xor_65535_uint16, fnname: "xor_65535_uint16", in: 65535, want: 0}, + test_uint16{fn: xor_uint16_65535, fnname: "xor_uint16_65535", in: 65535, want: 0}} + +type test_int16 struct { + fn func(int16) int16 + fnname string + in int16 + want int16 } + +var tests_int16 = []test_int16{ -//go:noinline -func xor_int8_127_ssa(a int8) int8 { - return a ^ 127 + test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: -32768, want: 0}, + test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: -32768, want: 0}, + test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: -32767, want: 1}, + test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: -32767, want: 1}, + test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: -1, want: 32767}, + test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: -1, want: 32767}, + test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: 0, want: -32768}, + test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: 0, want: -32768}, + test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: 1, want: -32767}, + test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: 1, want: -32767}, + test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: 32766, want: -2}, + test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: 32766, want: -2}, + test_int16{fn: add_Neg32768_int16, fnname: "add_Neg32768_int16", in: 32767, want: -1}, + test_int16{fn: add_int16_Neg32768, fnname: "add_int16_Neg32768", in: 32767, want: -1}, + test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: -32768, want: 1}, + test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: -32768, want: 1}, + test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: -32767, want: 2}, + test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: -32767, want: 2}, + test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: -1, want: -32768}, + test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: -1, want: -32768}, + test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: 0, want: -32767}, + test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: 0, want: -32767}, + test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: 1, want: -32766}, + test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: 1, want: -32766}, + test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: 32766, want: -1}, + test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: 32766, want: -1}, + test_int16{fn: add_Neg32767_int16, fnname: "add_Neg32767_int16", in: 32767, want: 0}, + test_int16{fn: add_int16_Neg32767, fnname: "add_int16_Neg32767", in: 32767, want: 0}, + test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: -32768, want: 32767}, + test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: -32768, want: 32767}, + test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: -32767, want: -32768}, + test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: -32767, want: -32768}, + test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: -1, want: -2}, + test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: -1, want: -2}, + test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: 0, want: -1}, + test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: 0, want: -1}, + test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: 1, want: 0}, + test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: 1, want: 0}, + test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: 32766, want: 32765}, + test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: 32766, want: 32765}, + test_int16{fn: add_Neg1_int16, fnname: "add_Neg1_int16", in: 32767, want: 32766}, + test_int16{fn: add_int16_Neg1, fnname: "add_int16_Neg1", in: 32767, want: 32766}, + test_int16{fn: add_0_int16, fnname: "add_0_int16", in: -32768, want: -32768}, + test_int16{fn: add_int16_0, fnname: "add_int16_0", in: -32768, want: -32768}, + test_int16{fn: add_0_int16, fnname: "add_0_int16", in: -32767, want: -32767}, + test_int16{fn: add_int16_0, fnname: "add_int16_0", in: -32767, want: -32767}, + test_int16{fn: add_0_int16, fnname: "add_0_int16", in: -1, want: -1}, + test_int16{fn: add_int16_0, fnname: "add_int16_0", in: -1, want: -1}, + test_int16{fn: add_0_int16, fnname: "add_0_int16", in: 0, want: 0}, + test_int16{fn: add_int16_0, fnname: "add_int16_0", in: 0, want: 0}, + test_int16{fn: add_0_int16, fnname: "add_0_int16", in: 1, want: 1}, + test_int16{fn: add_int16_0, fnname: "add_int16_0", in: 1, want: 1}, + test_int16{fn: add_0_int16, fnname: "add_0_int16", in: 32766, want: 32766}, + test_int16{fn: add_int16_0, fnname: "add_int16_0", in: 32766, want: 32766}, + test_int16{fn: add_0_int16, fnname: "add_0_int16", in: 32767, want: 32767}, + test_int16{fn: add_int16_0, fnname: "add_int16_0", in: 32767, want: 32767}, + test_int16{fn: add_1_int16, fnname: "add_1_int16", in: -32768, want: -32767}, + test_int16{fn: add_int16_1, fnname: "add_int16_1", in: -32768, want: -32767}, + test_int16{fn: add_1_int16, fnname: "add_1_int16", in: -32767, want: -32766}, + test_int16{fn: add_int16_1, fnname: "add_int16_1", in: -32767, want: -32766}, + test_int16{fn: add_1_int16, fnname: "add_1_int16", in: -1, want: 0}, + test_int16{fn: add_int16_1, fnname: "add_int16_1", in: -1, want: 0}, + test_int16{fn: add_1_int16, fnname: "add_1_int16", in: 0, want: 1}, + test_int16{fn: add_int16_1, fnname: "add_int16_1", in: 0, want: 1}, + test_int16{fn: add_1_int16, fnname: "add_1_int16", in: 1, want: 2}, + test_int16{fn: add_int16_1, fnname: "add_int16_1", in: 1, want: 2}, + test_int16{fn: add_1_int16, fnname: "add_1_int16", in: 32766, want: 32767}, + test_int16{fn: add_int16_1, fnname: "add_int16_1", in: 32766, want: 32767}, + test_int16{fn: add_1_int16, fnname: "add_1_int16", in: 32767, want: -32768}, + test_int16{fn: add_int16_1, fnname: "add_int16_1", in: 32767, want: -32768}, + test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: -32768, want: -2}, + test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: -32768, want: -2}, + test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: -32767, want: -1}, + test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: -32767, want: -1}, + test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: -1, want: 32765}, + test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: -1, want: 32765}, + test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: 0, want: 32766}, + test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: 0, want: 32766}, + test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: 1, want: 32767}, + test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: 1, want: 32767}, + test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: 32766, want: -4}, + test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: 32766, want: -4}, + test_int16{fn: add_32766_int16, fnname: "add_32766_int16", in: 32767, want: -3}, + test_int16{fn: add_int16_32766, fnname: "add_int16_32766", in: 32767, want: -3}, + test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: -32768, want: -1}, + test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: -32768, want: -1}, + test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: -32767, want: 0}, + test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: -32767, want: 0}, + test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: -1, want: 32766}, + test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: -1, want: 32766}, + test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: 0, want: 32767}, + test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: 0, want: 32767}, + test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: 1, want: -32768}, + test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: 1, want: -32768}, + test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: 32766, want: -3}, + test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: 32766, want: -3}, + test_int16{fn: add_32767_int16, fnname: "add_32767_int16", in: 32767, want: -2}, + test_int16{fn: add_int16_32767, fnname: "add_int16_32767", in: 32767, want: -2}, + test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: -32768, want: 0}, + test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: -32768, want: 0}, + test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: -32767, want: -1}, + test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: -32767, want: 1}, + test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: -1, want: -32767}, + test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: -1, want: 32767}, + test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: 0, want: -32768}, + test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: 0, want: -32768}, + test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: 1, want: 32767}, + test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: 1, want: -32767}, + test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: 32766, want: 2}, + test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: 32766, want: -2}, + test_int16{fn: sub_Neg32768_int16, fnname: "sub_Neg32768_int16", in: 32767, want: 1}, + test_int16{fn: sub_int16_Neg32768, fnname: "sub_int16_Neg32768", in: 32767, want: -1}, + test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: -32768, want: 1}, + test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: -32768, want: -1}, + test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: -32767, want: 0}, + test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: -32767, want: 0}, + test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: -1, want: -32766}, + test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: -1, want: 32766}, + test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: 0, want: -32767}, + test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: 0, want: 32767}, + test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: 1, want: -32768}, + test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: 1, want: -32768}, + test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: 32766, want: 3}, + test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: 32766, want: -3}, + test_int16{fn: sub_Neg32767_int16, fnname: "sub_Neg32767_int16", in: 32767, want: 2}, + test_int16{fn: sub_int16_Neg32767, fnname: "sub_int16_Neg32767", in: 32767, want: -2}, + test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: -32768, want: 32767}, + test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: -32768, want: -32767}, + test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: -32767, want: 32766}, + test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: -32767, want: -32766}, + test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: -1, want: 0}, + test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: -1, want: 0}, + test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: 0, want: -1}, + test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: 0, want: 1}, + test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: 1, want: -2}, + test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: 1, want: 2}, + test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: 32766, want: -32767}, + test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: 32766, want: 32767}, + test_int16{fn: sub_Neg1_int16, fnname: "sub_Neg1_int16", in: 32767, want: -32768}, + test_int16{fn: sub_int16_Neg1, fnname: "sub_int16_Neg1", in: 32767, want: -32768}, + test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: -32768, want: -32768}, + test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: -32768, want: -32768}, + test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: -32767, want: 32767}, + test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: -32767, want: -32767}, + test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: -1, want: 1}, + test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: -1, want: -1}, + test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: 0, want: 0}, + test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: 0, want: 0}, + test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: 1, want: -1}, + test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: 1, want: 1}, + test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: 32766, want: -32766}, + test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: 32766, want: 32766}, + test_int16{fn: sub_0_int16, fnname: "sub_0_int16", in: 32767, want: -32767}, + test_int16{fn: sub_int16_0, fnname: "sub_int16_0", in: 32767, want: 32767}, + test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: -32768, want: -32767}, + test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: -32768, want: 32767}, + test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: -32767, want: -32768}, + test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: -32767, want: -32768}, + test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: -1, want: 2}, + test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: -1, want: -2}, + test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: 0, want: 1}, + test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: 0, want: -1}, + test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: 1, want: 0}, + test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: 1, want: 0}, + test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: 32766, want: -32765}, + test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: 32766, want: 32765}, + test_int16{fn: sub_1_int16, fnname: "sub_1_int16", in: 32767, want: -32766}, + test_int16{fn: sub_int16_1, fnname: "sub_int16_1", in: 32767, want: 32766}, + test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: -32768, want: -2}, + test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: -32768, want: 2}, + test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: -32767, want: -3}, + test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: -32767, want: 3}, + test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: -1, want: 32767}, + test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: -1, want: -32767}, + test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: 0, want: 32766}, + test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: 0, want: -32766}, + test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: 1, want: 32765}, + test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: 1, want: -32765}, + test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: 32766, want: 0}, + test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: 32766, want: 0}, + test_int16{fn: sub_32766_int16, fnname: "sub_32766_int16", in: 32767, want: -1}, + test_int16{fn: sub_int16_32766, fnname: "sub_int16_32766", in: 32767, want: 1}, + test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: -32768, want: -1}, + test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: -32768, want: 1}, + test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: -32767, want: -2}, + test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: -32767, want: 2}, + test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: -1, want: -32768}, + test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: -1, want: -32768}, + test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: 0, want: 32767}, + test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: 0, want: -32767}, + test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: 1, want: 32766}, + test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: 1, want: -32766}, + test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: 32766, want: 1}, + test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: 32766, want: -1}, + test_int16{fn: sub_32767_int16, fnname: "sub_32767_int16", in: 32767, want: 0}, + test_int16{fn: sub_int16_32767, fnname: "sub_int16_32767", in: 32767, want: 0}, + test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: -32768, want: 1}, + test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: -32768, want: 1}, + test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: -32767, want: 1}, + test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: -32767, want: 0}, + test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: -1, want: -32768}, + test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: -1, want: 0}, + test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: 0, want: 0}, + test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: 1, want: -32768}, + test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: 1, want: 0}, + test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: 32766, want: -1}, + test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: 32766, want: 0}, + test_int16{fn: div_Neg32768_int16, fnname: "div_Neg32768_int16", in: 32767, want: -1}, + test_int16{fn: div_int16_Neg32768, fnname: "div_int16_Neg32768", in: 32767, want: 0}, + test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: -32768, want: 0}, + test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: -32768, want: 1}, + test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: -32767, want: 1}, + test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: -32767, want: 1}, + test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: -1, want: 32767}, + test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: -1, want: 0}, + test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: 0, want: 0}, + test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: 1, want: -32767}, + test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: 1, want: 0}, + test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: 32766, want: -1}, + test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: 32766, want: 0}, + test_int16{fn: div_Neg32767_int16, fnname: "div_Neg32767_int16", in: 32767, want: -1}, + test_int16{fn: div_int16_Neg32767, fnname: "div_int16_Neg32767", in: 32767, want: -1}, + test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: -32768, want: 0}, + test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: -32768, want: -32768}, + test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: -32767, want: 0}, + test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: -32767, want: 32767}, + test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: -1, want: 1}, + test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: -1, want: 1}, + test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: 0, want: 0}, + test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: 1, want: -1}, + test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: 1, want: -1}, + test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: 32766, want: 0}, + test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: 32766, want: -32766}, + test_int16{fn: div_Neg1_int16, fnname: "div_Neg1_int16", in: 32767, want: 0}, + test_int16{fn: div_int16_Neg1, fnname: "div_int16_Neg1", in: 32767, want: -32767}, + test_int16{fn: div_0_int16, fnname: "div_0_int16", in: -32768, want: 0}, + test_int16{fn: div_0_int16, fnname: "div_0_int16", in: -32767, want: 0}, + test_int16{fn: div_0_int16, fnname: "div_0_int16", in: -1, want: 0}, + test_int16{fn: div_0_int16, fnname: "div_0_int16", in: 1, want: 0}, + test_int16{fn: div_0_int16, fnname: "div_0_int16", in: 32766, want: 0}, + test_int16{fn: div_0_int16, fnname: "div_0_int16", in: 32767, want: 0}, + test_int16{fn: div_1_int16, fnname: "div_1_int16", in: -32768, want: 0}, + test_int16{fn: div_int16_1, fnname: "div_int16_1", in: -32768, want: -32768}, + test_int16{fn: div_1_int16, fnname: "div_1_int16", in: -32767, want: 0}, + test_int16{fn: div_int16_1, fnname: "div_int16_1", in: -32767, want: -32767}, + test_int16{fn: div_1_int16, fnname: "div_1_int16", in: -1, want: -1}, + test_int16{fn: div_int16_1, fnname: "div_int16_1", in: -1, want: -1}, + test_int16{fn: div_int16_1, fnname: "div_int16_1", in: 0, want: 0}, + test_int16{fn: div_1_int16, fnname: "div_1_int16", in: 1, want: 1}, + test_int16{fn: div_int16_1, fnname: "div_int16_1", in: 1, want: 1}, + test_int16{fn: div_1_int16, fnname: "div_1_int16", in: 32766, want: 0}, + test_int16{fn: div_int16_1, fnname: "div_int16_1", in: 32766, want: 32766}, + test_int16{fn: div_1_int16, fnname: "div_1_int16", in: 32767, want: 0}, + test_int16{fn: div_int16_1, fnname: "div_int16_1", in: 32767, want: 32767}, + test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: -32768, want: 0}, + test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: -32768, want: -1}, + test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: -32767, want: 0}, + test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: -32767, want: -1}, + test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: -1, want: -32766}, + test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: -1, want: 0}, + test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: 0, want: 0}, + test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: 1, want: 32766}, + test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: 1, want: 0}, + test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: 32766, want: 1}, + test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: 32766, want: 1}, + test_int16{fn: div_32766_int16, fnname: "div_32766_int16", in: 32767, want: 0}, + test_int16{fn: div_int16_32766, fnname: "div_int16_32766", in: 32767, want: 1}, + test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: -32768, want: 0}, + test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: -32768, want: -1}, + test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: -32767, want: -1}, + test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: -32767, want: -1}, + test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: -1, want: -32767}, + test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: -1, want: 0}, + test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: 0, want: 0}, + test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: 1, want: 32767}, + test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: 1, want: 0}, + test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: 32766, want: 1}, + test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: 32766, want: 0}, + test_int16{fn: div_32767_int16, fnname: "div_32767_int16", in: 32767, want: 1}, + test_int16{fn: div_int16_32767, fnname: "div_int16_32767", in: 32767, want: 1}, + test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: -32768, want: 0}, + test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: -32768, want: 0}, + test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: -32767, want: -32768}, + test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: -32767, want: -32768}, + test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: -1, want: -32768}, + test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: -1, want: -32768}, + test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: 0, want: 0}, + test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: 0, want: 0}, + test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: 1, want: -32768}, + test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: 1, want: -32768}, + test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: 32766, want: 0}, + test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: 32766, want: 0}, + test_int16{fn: mul_Neg32768_int16, fnname: "mul_Neg32768_int16", in: 32767, want: -32768}, + test_int16{fn: mul_int16_Neg32768, fnname: "mul_int16_Neg32768", in: 32767, want: -32768}, + test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: -32768, want: -32768}, + test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: -32768, want: -32768}, + test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: -32767, want: 1}, + test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: -32767, want: 1}, + test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: -1, want: 32767}, + test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: -1, want: 32767}, + test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: 0, want: 0}, + test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: 0, want: 0}, + test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: 1, want: -32767}, + test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: 1, want: -32767}, + test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: 32766, want: 32766}, + test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: 32766, want: 32766}, + test_int16{fn: mul_Neg32767_int16, fnname: "mul_Neg32767_int16", in: 32767, want: -1}, + test_int16{fn: mul_int16_Neg32767, fnname: "mul_int16_Neg32767", in: 32767, want: -1}, + test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: -32768, want: -32768}, + test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: -32768, want: -32768}, + test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: -32767, want: 32767}, + test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: -32767, want: 32767}, + test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: -1, want: 1}, + test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: -1, want: 1}, + test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: 0, want: 0}, + test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: 0, want: 0}, + test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: 1, want: -1}, + test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: 1, want: -1}, + test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: 32766, want: -32766}, + test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: 32766, want: -32766}, + test_int16{fn: mul_Neg1_int16, fnname: "mul_Neg1_int16", in: 32767, want: -32767}, + test_int16{fn: mul_int16_Neg1, fnname: "mul_int16_Neg1", in: 32767, want: -32767}, + test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: -32768, want: 0}, + test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: -32768, want: 0}, + test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: -32767, want: 0}, + test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: -32767, want: 0}, + test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: -1, want: 0}, + test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: -1, want: 0}, + test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: 0, want: 0}, + test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: 0, want: 0}, + test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: 1, want: 0}, + test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: 1, want: 0}, + test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: 32766, want: 0}, + test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: 32766, want: 0}, + test_int16{fn: mul_0_int16, fnname: "mul_0_int16", in: 32767, want: 0}, + test_int16{fn: mul_int16_0, fnname: "mul_int16_0", in: 32767, want: 0}, + test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: -32768, want: -32768}, + test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: -32768, want: -32768}, + test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: -32767, want: -32767}, + test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: -32767, want: -32767}, + test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: -1, want: -1}, + test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: -1, want: -1}, + test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: 0, want: 0}, + test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: 0, want: 0}, + test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: 1, want: 1}, + test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: 1, want: 1}, + test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: 32766, want: 32766}, + test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: 32766, want: 32766}, + test_int16{fn: mul_1_int16, fnname: "mul_1_int16", in: 32767, want: 32767}, + test_int16{fn: mul_int16_1, fnname: "mul_int16_1", in: 32767, want: 32767}, + test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: -32768, want: 0}, + test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: -32768, want: 0}, + test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: -32767, want: 32766}, + test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: -32767, want: 32766}, + test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: -1, want: -32766}, + test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: -1, want: -32766}, + test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: 0, want: 0}, + test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: 0, want: 0}, + test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: 1, want: 32766}, + test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: 1, want: 32766}, + test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: 32766, want: 4}, + test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: 32766, want: 4}, + test_int16{fn: mul_32766_int16, fnname: "mul_32766_int16", in: 32767, want: -32766}, + test_int16{fn: mul_int16_32766, fnname: "mul_int16_32766", in: 32767, want: -32766}, + test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: -32768, want: -32768}, + test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: -32768, want: -32768}, + test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: -32767, want: -1}, + test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: -32767, want: -1}, + test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: -1, want: -32767}, + test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: -1, want: -32767}, + test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: 0, want: 0}, + test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: 0, want: 0}, + test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: 1, want: 32767}, + test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: 1, want: 32767}, + test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: 32766, want: -32766}, + test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: 32766, want: -32766}, + test_int16{fn: mul_32767_int16, fnname: "mul_32767_int16", in: 32767, want: 1}, + test_int16{fn: mul_int16_32767, fnname: "mul_int16_32767", in: 32767, want: 1}, + test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: -32768, want: 0}, + test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: -32768, want: 0}, + test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: -32767, want: -1}, + test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: -32767, want: -32767}, + test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: -1, want: 0}, + test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: -1, want: -1}, + test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: 0, want: 0}, + test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: 1, want: 0}, + test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: 1, want: 1}, + test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: 32766, want: -2}, + test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: 32766, want: 32766}, + test_int16{fn: mod_Neg32768_int16, fnname: "mod_Neg32768_int16", in: 32767, want: -1}, + test_int16{fn: mod_int16_Neg32768, fnname: "mod_int16_Neg32768", in: 32767, want: 32767}, + test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: -32768, want: -32767}, + test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: -32768, want: -1}, + test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: -32767, want: 0}, + test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: -32767, want: 0}, + test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: -1, want: 0}, + test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: -1, want: -1}, + test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: 0, want: 0}, + test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: 1, want: 0}, + test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: 1, want: 1}, + test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: 32766, want: -1}, + test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: 32766, want: 32766}, + test_int16{fn: mod_Neg32767_int16, fnname: "mod_Neg32767_int16", in: 32767, want: 0}, + test_int16{fn: mod_int16_Neg32767, fnname: "mod_int16_Neg32767", in: 32767, want: 0}, + test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: -32768, want: -1}, + test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: -32768, want: 0}, + test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: -32767, want: -1}, + test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: -32767, want: 0}, + test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: -1, want: 0}, + test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: -1, want: 0}, + test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: 0, want: 0}, + test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: 1, want: 0}, + test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: 1, want: 0}, + test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: 32766, want: -1}, + test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: 32766, want: 0}, + test_int16{fn: mod_Neg1_int16, fnname: "mod_Neg1_int16", in: 32767, want: -1}, + test_int16{fn: mod_int16_Neg1, fnname: "mod_int16_Neg1", in: 32767, want: 0}, + test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: -32768, want: 0}, + test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: -32767, want: 0}, + test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: -1, want: 0}, + test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: 1, want: 0}, + test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: 32766, want: 0}, + test_int16{fn: mod_0_int16, fnname: "mod_0_int16", in: 32767, want: 0}, + test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: -32768, want: 1}, + test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: -32768, want: 0}, + test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: -32767, want: 1}, + test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: -32767, want: 0}, + test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: -1, want: 0}, + test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: -1, want: 0}, + test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: 0, want: 0}, + test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: 1, want: 0}, + test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: 1, want: 0}, + test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: 32766, want: 1}, + test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: 32766, want: 0}, + test_int16{fn: mod_1_int16, fnname: "mod_1_int16", in: 32767, want: 1}, + test_int16{fn: mod_int16_1, fnname: "mod_int16_1", in: 32767, want: 0}, + test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: -32768, want: 32766}, + test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: -32768, want: -2}, + test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: -32767, want: 32766}, + test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: -32767, want: -1}, + test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: -1, want: 0}, + test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: -1, want: -1}, + test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: 0, want: 0}, + test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: 1, want: 0}, + test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: 1, want: 1}, + test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: 32766, want: 0}, + test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: 32766, want: 0}, + test_int16{fn: mod_32766_int16, fnname: "mod_32766_int16", in: 32767, want: 32766}, + test_int16{fn: mod_int16_32766, fnname: "mod_int16_32766", in: 32767, want: 1}, + test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: -32768, want: 32767}, + test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: -32768, want: -1}, + test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: -32767, want: 0}, + test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: -32767, want: 0}, + test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: -1, want: 0}, + test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: -1, want: -1}, + test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: 0, want: 0}, + test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: 1, want: 0}, + test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: 1, want: 1}, + test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: 32766, want: 1}, + test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: 32766, want: 32766}, + test_int16{fn: mod_32767_int16, fnname: "mod_32767_int16", in: 32767, want: 0}, + test_int16{fn: mod_int16_32767, fnname: "mod_int16_32767", in: 32767, want: 0}, + test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: -32768, want: -32768}, + test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: -32768, want: -32768}, + test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: -32767, want: -32768}, + test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: -32767, want: -32768}, + test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: -1, want: -32768}, + test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: -1, want: -32768}, + test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: 0, want: 0}, + test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: 0, want: 0}, + test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: 1, want: 0}, + test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: 1, want: 0}, + test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: 32766, want: 0}, + test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: 32766, want: 0}, + test_int16{fn: and_Neg32768_int16, fnname: "and_Neg32768_int16", in: 32767, want: 0}, + test_int16{fn: and_int16_Neg32768, fnname: "and_int16_Neg32768", in: 32767, want: 0}, + test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: -32768, want: -32768}, + test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: -32768, want: -32768}, + test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: -32767, want: -32767}, + test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: -32767, want: -32767}, + test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: -1, want: -32767}, + test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: -1, want: -32767}, + test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: 0, want: 0}, + test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: 0, want: 0}, + test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: 1, want: 1}, + test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: 1, want: 1}, + test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: 32766, want: 0}, + test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: 32766, want: 0}, + test_int16{fn: and_Neg32767_int16, fnname: "and_Neg32767_int16", in: 32767, want: 1}, + test_int16{fn: and_int16_Neg32767, fnname: "and_int16_Neg32767", in: 32767, want: 1}, + test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: -32768, want: -32768}, + test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: -32768, want: -32768}, + test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: -32767, want: -32767}, + test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: -32767, want: -32767}, + test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: -1, want: -1}, + test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: -1, want: -1}, + test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: 0, want: 0}, + test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: 0, want: 0}, + test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: 1, want: 1}, + test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: 1, want: 1}, + test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: 32766, want: 32766}, + test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: 32766, want: 32766}, + test_int16{fn: and_Neg1_int16, fnname: "and_Neg1_int16", in: 32767, want: 32767}, + test_int16{fn: and_int16_Neg1, fnname: "and_int16_Neg1", in: 32767, want: 32767}, + test_int16{fn: and_0_int16, fnname: "and_0_int16", in: -32768, want: 0}, + test_int16{fn: and_int16_0, fnname: "and_int16_0", in: -32768, want: 0}, + test_int16{fn: and_0_int16, fnname: "and_0_int16", in: -32767, want: 0}, + test_int16{fn: and_int16_0, fnname: "and_int16_0", in: -32767, want: 0}, + test_int16{fn: and_0_int16, fnname: "and_0_int16", in: -1, want: 0}, + test_int16{fn: and_int16_0, fnname: "and_int16_0", in: -1, want: 0}, + test_int16{fn: and_0_int16, fnname: "and_0_int16", in: 0, want: 0}, + test_int16{fn: and_int16_0, fnname: "and_int16_0", in: 0, want: 0}, + test_int16{fn: and_0_int16, fnname: "and_0_int16", in: 1, want: 0}, + test_int16{fn: and_int16_0, fnname: "and_int16_0", in: 1, want: 0}, + test_int16{fn: and_0_int16, fnname: "and_0_int16", in: 32766, want: 0}, + test_int16{fn: and_int16_0, fnname: "and_int16_0", in: 32766, want: 0}, + test_int16{fn: and_0_int16, fnname: "and_0_int16", in: 32767, want: 0}, + test_int16{fn: and_int16_0, fnname: "and_int16_0", in: 32767, want: 0}, + test_int16{fn: and_1_int16, fnname: "and_1_int16", in: -32768, want: 0}, + test_int16{fn: and_int16_1, fnname: "and_int16_1", in: -32768, want: 0}, + test_int16{fn: and_1_int16, fnname: "and_1_int16", in: -32767, want: 1}, + test_int16{fn: and_int16_1, fnname: "and_int16_1", in: -32767, want: 1}, + test_int16{fn: and_1_int16, fnname: "and_1_int16", in: -1, want: 1}, + test_int16{fn: and_int16_1, fnname: "and_int16_1", in: -1, want: 1}, + test_int16{fn: and_1_int16, fnname: "and_1_int16", in: 0, want: 0}, + test_int16{fn: and_int16_1, fnname: "and_int16_1", in: 0, want: 0}, + test_int16{fn: and_1_int16, fnname: "and_1_int16", in: 1, want: 1}, + test_int16{fn: and_int16_1, fnname: "and_int16_1", in: 1, want: 1}, + test_int16{fn: and_1_int16, fnname: "and_1_int16", in: 32766, want: 0}, + test_int16{fn: and_int16_1, fnname: "and_int16_1", in: 32766, want: 0}, + test_int16{fn: and_1_int16, fnname: "and_1_int16", in: 32767, want: 1}, + test_int16{fn: and_int16_1, fnname: "and_int16_1", in: 32767, want: 1}, + test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: -32768, want: 0}, + test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: -32768, want: 0}, + test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: -32767, want: 0}, + test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: -32767, want: 0}, + test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: -1, want: 32766}, + test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: -1, want: 32766}, + test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: 0, want: 0}, + test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: 0, want: 0}, + test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: 1, want: 0}, + test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: 1, want: 0}, + test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: 32766, want: 32766}, + test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: 32766, want: 32766}, + test_int16{fn: and_32766_int16, fnname: "and_32766_int16", in: 32767, want: 32766}, + test_int16{fn: and_int16_32766, fnname: "and_int16_32766", in: 32767, want: 32766}, + test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: -32768, want: 0}, + test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: -32768, want: 0}, + test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: -32767, want: 1}, + test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: -32767, want: 1}, + test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: -1, want: 32767}, + test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: -1, want: 32767}, + test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: 0, want: 0}, + test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: 0, want: 0}, + test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: 1, want: 1}, + test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: 1, want: 1}, + test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: 32766, want: 32766}, + test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: 32766, want: 32766}, + test_int16{fn: and_32767_int16, fnname: "and_32767_int16", in: 32767, want: 32767}, + test_int16{fn: and_int16_32767, fnname: "and_int16_32767", in: 32767, want: 32767}, + test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: -32768, want: -32768}, + test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: -32768, want: -32768}, + test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: -32767, want: -32767}, + test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: -32767, want: -32767}, + test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: -1, want: -1}, + test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: -1, want: -1}, + test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: 0, want: -32768}, + test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: 0, want: -32768}, + test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: 1, want: -32767}, + test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: 1, want: -32767}, + test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: 32766, want: -2}, + test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: 32766, want: -2}, + test_int16{fn: or_Neg32768_int16, fnname: "or_Neg32768_int16", in: 32767, want: -1}, + test_int16{fn: or_int16_Neg32768, fnname: "or_int16_Neg32768", in: 32767, want: -1}, + test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: -32768, want: -32767}, + test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: -32768, want: -32767}, + test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: -32767, want: -32767}, + test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: -32767, want: -32767}, + test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: -1, want: -1}, + test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: -1, want: -1}, + test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: 0, want: -32767}, + test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: 0, want: -32767}, + test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: 1, want: -32767}, + test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: 1, want: -32767}, + test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: 32766, want: -1}, + test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: 32766, want: -1}, + test_int16{fn: or_Neg32767_int16, fnname: "or_Neg32767_int16", in: 32767, want: -1}, + test_int16{fn: or_int16_Neg32767, fnname: "or_int16_Neg32767", in: 32767, want: -1}, + test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: -32768, want: -1}, + test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: -32768, want: -1}, + test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: -32767, want: -1}, + test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: -32767, want: -1}, + test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: -1, want: -1}, + test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: -1, want: -1}, + test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: 0, want: -1}, + test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: 0, want: -1}, + test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: 1, want: -1}, + test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: 1, want: -1}, + test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: 32766, want: -1}, + test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: 32766, want: -1}, + test_int16{fn: or_Neg1_int16, fnname: "or_Neg1_int16", in: 32767, want: -1}, + test_int16{fn: or_int16_Neg1, fnname: "or_int16_Neg1", in: 32767, want: -1}, + test_int16{fn: or_0_int16, fnname: "or_0_int16", in: -32768, want: -32768}, + test_int16{fn: or_int16_0, fnname: "or_int16_0", in: -32768, want: -32768}, + test_int16{fn: or_0_int16, fnname: "or_0_int16", in: -32767, want: -32767}, + test_int16{fn: or_int16_0, fnname: "or_int16_0", in: -32767, want: -32767}, + test_int16{fn: or_0_int16, fnname: "or_0_int16", in: -1, want: -1}, + test_int16{fn: or_int16_0, fnname: "or_int16_0", in: -1, want: -1}, + test_int16{fn: or_0_int16, fnname: "or_0_int16", in: 0, want: 0}, + test_int16{fn: or_int16_0, fnname: "or_int16_0", in: 0, want: 0}, + test_int16{fn: or_0_int16, fnname: "or_0_int16", in: 1, want: 1}, + test_int16{fn: or_int16_0, fnname: "or_int16_0", in: 1, want: 1}, + test_int16{fn: or_0_int16, fnname: "or_0_int16", in: 32766, want: 32766}, + test_int16{fn: or_int16_0, fnname: "or_int16_0", in: 32766, want: 32766}, + test_int16{fn: or_0_int16, fnname: "or_0_int16", in: 32767, want: 32767}, + test_int16{fn: or_int16_0, fnname: "or_int16_0", in: 32767, want: 32767}, + test_int16{fn: or_1_int16, fnname: "or_1_int16", in: -32768, want: -32767}, + test_int16{fn: or_int16_1, fnname: "or_int16_1", in: -32768, want: -32767}, + test_int16{fn: or_1_int16, fnname: "or_1_int16", in: -32767, want: -32767}, + test_int16{fn: or_int16_1, fnname: "or_int16_1", in: -32767, want: -32767}, + test_int16{fn: or_1_int16, fnname: "or_1_int16", in: -1, want: -1}, + test_int16{fn: or_int16_1, fnname: "or_int16_1", in: -1, want: -1}, + test_int16{fn: or_1_int16, fnname: "or_1_int16", in: 0, want: 1}, + test_int16{fn: or_int16_1, fnname: "or_int16_1", in: 0, want: 1}, + test_int16{fn: or_1_int16, fnname: "or_1_int16", in: 1, want: 1}, + test_int16{fn: or_int16_1, fnname: "or_int16_1", in: 1, want: 1}, + test_int16{fn: or_1_int16, fnname: "or_1_int16", in: 32766, want: 32767}, + test_int16{fn: or_int16_1, fnname: "or_int16_1", in: 32766, want: 32767}, + test_int16{fn: or_1_int16, fnname: "or_1_int16", in: 32767, want: 32767}, + test_int16{fn: or_int16_1, fnname: "or_int16_1", in: 32767, want: 32767}, + test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: -32768, want: -2}, + test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: -32768, want: -2}, + test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: -32767, want: -1}, + test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: -32767, want: -1}, + test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: -1, want: -1}, + test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: -1, want: -1}, + test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: 0, want: 32766}, + test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: 0, want: 32766}, + test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: 1, want: 32767}, + test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: 1, want: 32767}, + test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: 32766, want: 32766}, + test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: 32766, want: 32766}, + test_int16{fn: or_32766_int16, fnname: "or_32766_int16", in: 32767, want: 32767}, + test_int16{fn: or_int16_32766, fnname: "or_int16_32766", in: 32767, want: 32767}, + test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: -32768, want: -1}, + test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: -32768, want: -1}, + test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: -32767, want: -1}, + test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: -32767, want: -1}, + test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: -1, want: -1}, + test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: -1, want: -1}, + test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: 0, want: 32767}, + test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: 0, want: 32767}, + test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: 1, want: 32767}, + test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: 1, want: 32767}, + test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: 32766, want: 32767}, + test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: 32766, want: 32767}, + test_int16{fn: or_32767_int16, fnname: "or_32767_int16", in: 32767, want: 32767}, + test_int16{fn: or_int16_32767, fnname: "or_int16_32767", in: 32767, want: 32767}, + test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: -32768, want: 0}, + test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: -32768, want: 0}, + test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: -32767, want: 1}, + test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: -32767, want: 1}, + test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: -1, want: 32767}, + test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: -1, want: 32767}, + test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: 0, want: -32768}, + test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: 0, want: -32768}, + test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: 1, want: -32767}, + test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: 1, want: -32767}, + test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: 32766, want: -2}, + test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: 32766, want: -2}, + test_int16{fn: xor_Neg32768_int16, fnname: "xor_Neg32768_int16", in: 32767, want: -1}, + test_int16{fn: xor_int16_Neg32768, fnname: "xor_int16_Neg32768", in: 32767, want: -1}, + test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: -32768, want: 1}, + test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: -32768, want: 1}, + test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: -32767, want: 0}, + test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: -32767, want: 0}, + test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: -1, want: 32766}, + test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: -1, want: 32766}, + test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: 0, want: -32767}, + test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: 0, want: -32767}, + test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: 1, want: -32768}, + test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: 1, want: -32768}, + test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: 32766, want: -1}, + test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: 32766, want: -1}, + test_int16{fn: xor_Neg32767_int16, fnname: "xor_Neg32767_int16", in: 32767, want: -2}, + test_int16{fn: xor_int16_Neg32767, fnname: "xor_int16_Neg32767", in: 32767, want: -2}, + test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: -32768, want: 32767}, + test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: -32768, want: 32767}, + test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: -32767, want: 32766}, + test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: -32767, want: 32766}, + test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: -1, want: 0}, + test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: -1, want: 0}, + test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: 0, want: -1}, + test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: 0, want: -1}, + test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: 1, want: -2}, + test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: 1, want: -2}, + test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: 32766, want: -32767}, + test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: 32766, want: -32767}, + test_int16{fn: xor_Neg1_int16, fnname: "xor_Neg1_int16", in: 32767, want: -32768}, + test_int16{fn: xor_int16_Neg1, fnname: "xor_int16_Neg1", in: 32767, want: -32768}, + test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: -32768, want: -32768}, + test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: -32768, want: -32768}, + test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: -32767, want: -32767}, + test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: -32767, want: -32767}, + test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: -1, want: -1}, + test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: -1, want: -1}, + test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: 0, want: 0}, + test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: 0, want: 0}, + test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: 1, want: 1}, + test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: 1, want: 1}, + test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: 32766, want: 32766}, + test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: 32766, want: 32766}, + test_int16{fn: xor_0_int16, fnname: "xor_0_int16", in: 32767, want: 32767}, + test_int16{fn: xor_int16_0, fnname: "xor_int16_0", in: 32767, want: 32767}, + test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: -32768, want: -32767}, + test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: -32768, want: -32767}, + test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: -32767, want: -32768}, + test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: -32767, want: -32768}, + test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: -1, want: -2}, + test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: -1, want: -2}, + test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: 0, want: 1}, + test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: 0, want: 1}, + test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: 1, want: 0}, + test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: 1, want: 0}, + test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: 32766, want: 32767}, + test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: 32766, want: 32767}, + test_int16{fn: xor_1_int16, fnname: "xor_1_int16", in: 32767, want: 32766}, + test_int16{fn: xor_int16_1, fnname: "xor_int16_1", in: 32767, want: 32766}, + test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: -32768, want: -2}, + test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: -32768, want: -2}, + test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: -32767, want: -1}, + test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: -32767, want: -1}, + test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: -1, want: -32767}, + test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: -1, want: -32767}, + test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: 0, want: 32766}, + test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: 0, want: 32766}, + test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: 1, want: 32767}, + test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: 1, want: 32767}, + test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: 32766, want: 0}, + test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: 32766, want: 0}, + test_int16{fn: xor_32766_int16, fnname: "xor_32766_int16", in: 32767, want: 1}, + test_int16{fn: xor_int16_32766, fnname: "xor_int16_32766", in: 32767, want: 1}, + test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: -32768, want: -1}, + test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: -32768, want: -1}, + test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: -32767, want: -2}, + test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: -32767, want: -2}, + test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: -1, want: -32768}, + test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: -1, want: -32768}, + test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: 0, want: 32767}, + test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: 0, want: 32767}, + test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: 1, want: 32766}, + test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: 1, want: 32766}, + test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: 32766, want: 1}, + test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: 32766, want: 1}, + test_int16{fn: xor_32767_int16, fnname: "xor_32767_int16", in: 32767, want: 0}, + test_int16{fn: xor_int16_32767, fnname: "xor_int16_32767", in: 32767, want: 0}} + +type test_uint8 struct { + fn func(uint8) uint8 + fnname string + in uint8 + want uint8 } -//go:noinline -func xor_127_int8_ssa(a int8) int8 { - return 127 ^ a +var tests_uint8 = []test_uint8{ + + test_uint8{fn: add_0_uint8, fnname: "add_0_uint8", in: 0, want: 0}, + test_uint8{fn: add_uint8_0, fnname: "add_uint8_0", in: 0, want: 0}, + test_uint8{fn: add_0_uint8, fnname: "add_0_uint8", in: 1, want: 1}, + test_uint8{fn: add_uint8_0, fnname: "add_uint8_0", in: 1, want: 1}, + test_uint8{fn: add_0_uint8, fnname: "add_0_uint8", in: 255, want: 255}, + test_uint8{fn: add_uint8_0, fnname: "add_uint8_0", in: 255, want: 255}, + test_uint8{fn: add_1_uint8, fnname: "add_1_uint8", in: 0, want: 1}, + test_uint8{fn: add_uint8_1, fnname: "add_uint8_1", in: 0, want: 1}, + test_uint8{fn: add_1_uint8, fnname: "add_1_uint8", in: 1, want: 2}, + test_uint8{fn: add_uint8_1, fnname: "add_uint8_1", in: 1, want: 2}, + test_uint8{fn: add_1_uint8, fnname: "add_1_uint8", in: 255, want: 0}, + test_uint8{fn: add_uint8_1, fnname: "add_uint8_1", in: 255, want: 0}, + test_uint8{fn: add_255_uint8, fnname: "add_255_uint8", in: 0, want: 255}, + test_uint8{fn: add_uint8_255, fnname: "add_uint8_255", in: 0, want: 255}, + test_uint8{fn: add_255_uint8, fnname: "add_255_uint8", in: 1, want: 0}, + test_uint8{fn: add_uint8_255, fnname: "add_uint8_255", in: 1, want: 0}, + test_uint8{fn: add_255_uint8, fnname: "add_255_uint8", in: 255, want: 254}, + test_uint8{fn: add_uint8_255, fnname: "add_uint8_255", in: 255, want: 254}, + test_uint8{fn: sub_0_uint8, fnname: "sub_0_uint8", in: 0, want: 0}, + test_uint8{fn: sub_uint8_0, fnname: "sub_uint8_0", in: 0, want: 0}, + test_uint8{fn: sub_0_uint8, fnname: "sub_0_uint8", in: 1, want: 255}, + test_uint8{fn: sub_uint8_0, fnname: "sub_uint8_0", in: 1, want: 1}, + test_uint8{fn: sub_0_uint8, fnname: "sub_0_uint8", in: 255, want: 1}, + test_uint8{fn: sub_uint8_0, fnname: "sub_uint8_0", in: 255, want: 255}, + test_uint8{fn: sub_1_uint8, fnname: "sub_1_uint8", in: 0, want: 1}, + test_uint8{fn: sub_uint8_1, fnname: "sub_uint8_1", in: 0, want: 255}, + test_uint8{fn: sub_1_uint8, fnname: "sub_1_uint8", in: 1, want: 0}, + test_uint8{fn: sub_uint8_1, fnname: "sub_uint8_1", in: 1, want: 0}, + test_uint8{fn: sub_1_uint8, fnname: "sub_1_uint8", in: 255, want: 2}, + test_uint8{fn: sub_uint8_1, fnname: "sub_uint8_1", in: 255, want: 254}, + test_uint8{fn: sub_255_uint8, fnname: "sub_255_uint8", in: 0, want: 255}, + test_uint8{fn: sub_uint8_255, fnname: "sub_uint8_255", in: 0, want: 1}, + test_uint8{fn: sub_255_uint8, fnname: "sub_255_uint8", in: 1, want: 254}, + test_uint8{fn: sub_uint8_255, fnname: "sub_uint8_255", in: 1, want: 2}, + test_uint8{fn: sub_255_uint8, fnname: "sub_255_uint8", in: 255, want: 0}, + test_uint8{fn: sub_uint8_255, fnname: "sub_uint8_255", in: 255, want: 0}, + test_uint8{fn: div_0_uint8, fnname: "div_0_uint8", in: 1, want: 0}, + test_uint8{fn: div_0_uint8, fnname: "div_0_uint8", in: 255, want: 0}, + test_uint8{fn: div_uint8_1, fnname: "div_uint8_1", in: 0, want: 0}, + test_uint8{fn: div_1_uint8, fnname: "div_1_uint8", in: 1, want: 1}, + test_uint8{fn: div_uint8_1, fnname: "div_uint8_1", in: 1, want: 1}, + test_uint8{fn: div_1_uint8, fnname: "div_1_uint8", in: 255, want: 0}, + test_uint8{fn: div_uint8_1, fnname: "div_uint8_1", in: 255, want: 255}, + test_uint8{fn: div_uint8_255, fnname: "div_uint8_255", in: 0, want: 0}, + test_uint8{fn: div_255_uint8, fnname: "div_255_uint8", in: 1, want: 255}, + test_uint8{fn: div_uint8_255, fnname: "div_uint8_255", in: 1, want: 0}, + test_uint8{fn: div_255_uint8, fnname: "div_255_uint8", in: 255, want: 1}, + test_uint8{fn: div_uint8_255, fnname: "div_uint8_255", in: 255, want: 1}, + test_uint8{fn: mul_0_uint8, fnname: "mul_0_uint8", in: 0, want: 0}, + test_uint8{fn: mul_uint8_0, fnname: "mul_uint8_0", in: 0, want: 0}, + test_uint8{fn: mul_0_uint8, fnname: "mul_0_uint8", in: 1, want: 0}, + test_uint8{fn: mul_uint8_0, fnname: "mul_uint8_0", in: 1, want: 0}, + test_uint8{fn: mul_0_uint8, fnname: "mul_0_uint8", in: 255, want: 0}, + test_uint8{fn: mul_uint8_0, fnname: "mul_uint8_0", in: 255, want: 0}, + test_uint8{fn: mul_1_uint8, fnname: "mul_1_uint8", in: 0, want: 0}, + test_uint8{fn: mul_uint8_1, fnname: "mul_uint8_1", in: 0, want: 0}, + test_uint8{fn: mul_1_uint8, fnname: "mul_1_uint8", in: 1, want: 1}, + test_uint8{fn: mul_uint8_1, fnname: "mul_uint8_1", in: 1, want: 1}, + test_uint8{fn: mul_1_uint8, fnname: "mul_1_uint8", in: 255, want: 255}, + test_uint8{fn: mul_uint8_1, fnname: "mul_uint8_1", in: 255, want: 255}, + test_uint8{fn: mul_255_uint8, fnname: "mul_255_uint8", in: 0, want: 0}, + test_uint8{fn: mul_uint8_255, fnname: "mul_uint8_255", in: 0, want: 0}, + test_uint8{fn: mul_255_uint8, fnname: "mul_255_uint8", in: 1, want: 255}, + test_uint8{fn: mul_uint8_255, fnname: "mul_uint8_255", in: 1, want: 255}, + test_uint8{fn: mul_255_uint8, fnname: "mul_255_uint8", in: 255, want: 1}, + test_uint8{fn: mul_uint8_255, fnname: "mul_uint8_255", in: 255, want: 1}, + test_uint8{fn: lsh_0_uint8, fnname: "lsh_0_uint8", in: 0, want: 0}, + test_uint8{fn: lsh_uint8_0, fnname: "lsh_uint8_0", in: 0, want: 0}, + test_uint8{fn: lsh_0_uint8, fnname: "lsh_0_uint8", in: 1, want: 0}, + test_uint8{fn: lsh_uint8_0, fnname: "lsh_uint8_0", in: 1, want: 1}, + test_uint8{fn: lsh_0_uint8, fnname: "lsh_0_uint8", in: 255, want: 0}, + test_uint8{fn: lsh_uint8_0, fnname: "lsh_uint8_0", in: 255, want: 255}, + test_uint8{fn: lsh_1_uint8, fnname: "lsh_1_uint8", in: 0, want: 1}, + test_uint8{fn: lsh_uint8_1, fnname: "lsh_uint8_1", in: 0, want: 0}, + test_uint8{fn: lsh_1_uint8, fnname: "lsh_1_uint8", in: 1, want: 2}, + test_uint8{fn: lsh_uint8_1, fnname: "lsh_uint8_1", in: 1, want: 2}, + test_uint8{fn: lsh_1_uint8, fnname: "lsh_1_uint8", in: 255, want: 0}, + test_uint8{fn: lsh_uint8_1, fnname: "lsh_uint8_1", in: 255, want: 254}, + test_uint8{fn: lsh_255_uint8, fnname: "lsh_255_uint8", in: 0, want: 255}, + test_uint8{fn: lsh_uint8_255, fnname: "lsh_uint8_255", in: 0, want: 0}, + test_uint8{fn: lsh_255_uint8, fnname: "lsh_255_uint8", in: 1, want: 254}, + test_uint8{fn: lsh_uint8_255, fnname: "lsh_uint8_255", in: 1, want: 0}, + test_uint8{fn: lsh_255_uint8, fnname: "lsh_255_uint8", in: 255, want: 0}, + test_uint8{fn: lsh_uint8_255, fnname: "lsh_uint8_255", in: 255, want: 0}, + test_uint8{fn: rsh_0_uint8, fnname: "rsh_0_uint8", in: 0, want: 0}, + test_uint8{fn: rsh_uint8_0, fnname: "rsh_uint8_0", in: 0, want: 0}, + test_uint8{fn: rsh_0_uint8, fnname: "rsh_0_uint8", in: 1, want: 0}, + test_uint8{fn: rsh_uint8_0, fnname: "rsh_uint8_0", in: 1, want: 1}, + test_uint8{fn: rsh_0_uint8, fnname: "rsh_0_uint8", in: 255, want: 0}, + test_uint8{fn: rsh_uint8_0, fnname: "rsh_uint8_0", in: 255, want: 255}, + test_uint8{fn: rsh_1_uint8, fnname: "rsh_1_uint8", in: 0, want: 1}, + test_uint8{fn: rsh_uint8_1, fnname: "rsh_uint8_1", in: 0, want: 0}, + test_uint8{fn: rsh_1_uint8, fnname: "rsh_1_uint8", in: 1, want: 0}, + test_uint8{fn: rsh_uint8_1, fnname: "rsh_uint8_1", in: 1, want: 0}, + test_uint8{fn: rsh_1_uint8, fnname: "rsh_1_uint8", in: 255, want: 0}, + test_uint8{fn: rsh_uint8_1, fnname: "rsh_uint8_1", in: 255, want: 127}, + test_uint8{fn: rsh_255_uint8, fnname: "rsh_255_uint8", in: 0, want: 255}, + test_uint8{fn: rsh_uint8_255, fnname: "rsh_uint8_255", in: 0, want: 0}, + test_uint8{fn: rsh_255_uint8, fnname: "rsh_255_uint8", in: 1, want: 127}, + test_uint8{fn: rsh_uint8_255, fnname: "rsh_uint8_255", in: 1, want: 0}, + test_uint8{fn: rsh_255_uint8, fnname: "rsh_255_uint8", in: 255, want: 0}, + test_uint8{fn: rsh_uint8_255, fnname: "rsh_uint8_255", in: 255, want: 0}, + test_uint8{fn: mod_0_uint8, fnname: "mod_0_uint8", in: 1, want: 0}, + test_uint8{fn: mod_0_uint8, fnname: "mod_0_uint8", in: 255, want: 0}, + test_uint8{fn: mod_uint8_1, fnname: "mod_uint8_1", in: 0, want: 0}, + test_uint8{fn: mod_1_uint8, fnname: "mod_1_uint8", in: 1, want: 0}, + test_uint8{fn: mod_uint8_1, fnname: "mod_uint8_1", in: 1, want: 0}, + test_uint8{fn: mod_1_uint8, fnname: "mod_1_uint8", in: 255, want: 1}, + test_uint8{fn: mod_uint8_1, fnname: "mod_uint8_1", in: 255, want: 0}, + test_uint8{fn: mod_uint8_255, fnname: "mod_uint8_255", in: 0, want: 0}, + test_uint8{fn: mod_255_uint8, fnname: "mod_255_uint8", in: 1, want: 0}, + test_uint8{fn: mod_uint8_255, fnname: "mod_uint8_255", in: 1, want: 1}, + test_uint8{fn: mod_255_uint8, fnname: "mod_255_uint8", in: 255, want: 0}, + test_uint8{fn: mod_uint8_255, fnname: "mod_uint8_255", in: 255, want: 0}, + test_uint8{fn: and_0_uint8, fnname: "and_0_uint8", in: 0, want: 0}, + test_uint8{fn: and_uint8_0, fnname: "and_uint8_0", in: 0, want: 0}, + test_uint8{fn: and_0_uint8, fnname: "and_0_uint8", in: 1, want: 0}, + test_uint8{fn: and_uint8_0, fnname: "and_uint8_0", in: 1, want: 0}, + test_uint8{fn: and_0_uint8, fnname: "and_0_uint8", in: 255, want: 0}, + test_uint8{fn: and_uint8_0, fnname: "and_uint8_0", in: 255, want: 0}, + test_uint8{fn: and_1_uint8, fnname: "and_1_uint8", in: 0, want: 0}, + test_uint8{fn: and_uint8_1, fnname: "and_uint8_1", in: 0, want: 0}, + test_uint8{fn: and_1_uint8, fnname: "and_1_uint8", in: 1, want: 1}, + test_uint8{fn: and_uint8_1, fnname: "and_uint8_1", in: 1, want: 1}, + test_uint8{fn: and_1_uint8, fnname: "and_1_uint8", in: 255, want: 1}, + test_uint8{fn: and_uint8_1, fnname: "and_uint8_1", in: 255, want: 1}, + test_uint8{fn: and_255_uint8, fnname: "and_255_uint8", in: 0, want: 0}, + test_uint8{fn: and_uint8_255, fnname: "and_uint8_255", in: 0, want: 0}, + test_uint8{fn: and_255_uint8, fnname: "and_255_uint8", in: 1, want: 1}, + test_uint8{fn: and_uint8_255, fnname: "and_uint8_255", in: 1, want: 1}, + test_uint8{fn: and_255_uint8, fnname: "and_255_uint8", in: 255, want: 255}, + test_uint8{fn: and_uint8_255, fnname: "and_uint8_255", in: 255, want: 255}, + test_uint8{fn: or_0_uint8, fnname: "or_0_uint8", in: 0, want: 0}, + test_uint8{fn: or_uint8_0, fnname: "or_uint8_0", in: 0, want: 0}, + test_uint8{fn: or_0_uint8, fnname: "or_0_uint8", in: 1, want: 1}, + test_uint8{fn: or_uint8_0, fnname: "or_uint8_0", in: 1, want: 1}, + test_uint8{fn: or_0_uint8, fnname: "or_0_uint8", in: 255, want: 255}, + test_uint8{fn: or_uint8_0, fnname: "or_uint8_0", in: 255, want: 255}, + test_uint8{fn: or_1_uint8, fnname: "or_1_uint8", in: 0, want: 1}, + test_uint8{fn: or_uint8_1, fnname: "or_uint8_1", in: 0, want: 1}, + test_uint8{fn: or_1_uint8, fnname: "or_1_uint8", in: 1, want: 1}, + test_uint8{fn: or_uint8_1, fnname: "or_uint8_1", in: 1, want: 1}, + test_uint8{fn: or_1_uint8, fnname: "or_1_uint8", in: 255, want: 255}, + test_uint8{fn: or_uint8_1, fnname: "or_uint8_1", in: 255, want: 255}, + test_uint8{fn: or_255_uint8, fnname: "or_255_uint8", in: 0, want: 255}, + test_uint8{fn: or_uint8_255, fnname: "or_uint8_255", in: 0, want: 255}, + test_uint8{fn: or_255_uint8, fnname: "or_255_uint8", in: 1, want: 255}, + test_uint8{fn: or_uint8_255, fnname: "or_uint8_255", in: 1, want: 255}, + test_uint8{fn: or_255_uint8, fnname: "or_255_uint8", in: 255, want: 255}, + test_uint8{fn: or_uint8_255, fnname: "or_uint8_255", in: 255, want: 255}, + test_uint8{fn: xor_0_uint8, fnname: "xor_0_uint8", in: 0, want: 0}, + test_uint8{fn: xor_uint8_0, fnname: "xor_uint8_0", in: 0, want: 0}, + test_uint8{fn: xor_0_uint8, fnname: "xor_0_uint8", in: 1, want: 1}, + test_uint8{fn: xor_uint8_0, fnname: "xor_uint8_0", in: 1, want: 1}, + test_uint8{fn: xor_0_uint8, fnname: "xor_0_uint8", in: 255, want: 255}, + test_uint8{fn: xor_uint8_0, fnname: "xor_uint8_0", in: 255, want: 255}, + test_uint8{fn: xor_1_uint8, fnname: "xor_1_uint8", in: 0, want: 1}, + test_uint8{fn: xor_uint8_1, fnname: "xor_uint8_1", in: 0, want: 1}, + test_uint8{fn: xor_1_uint8, fnname: "xor_1_uint8", in: 1, want: 0}, + test_uint8{fn: xor_uint8_1, fnname: "xor_uint8_1", in: 1, want: 0}, + test_uint8{fn: xor_1_uint8, fnname: "xor_1_uint8", in: 255, want: 254}, + test_uint8{fn: xor_uint8_1, fnname: "xor_uint8_1", in: 255, want: 254}, + test_uint8{fn: xor_255_uint8, fnname: "xor_255_uint8", in: 0, want: 255}, + test_uint8{fn: xor_uint8_255, fnname: "xor_uint8_255", in: 0, want: 255}, + test_uint8{fn: xor_255_uint8, fnname: "xor_255_uint8", in: 1, want: 254}, + test_uint8{fn: xor_uint8_255, fnname: "xor_uint8_255", in: 1, want: 254}, + test_uint8{fn: xor_255_uint8, fnname: "xor_255_uint8", in: 255, want: 0}, + test_uint8{fn: xor_uint8_255, fnname: "xor_uint8_255", in: 255, want: 0}} + +type test_int8 struct { + fn func(int8) int8 + fnname string + in int8 + want int8 } + +var tests_int8 = []test_int8{ + + test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: -128, want: 0}, + test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: -128, want: 0}, + test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: -127, want: 1}, + test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: -127, want: 1}, + test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: -1, want: 127}, + test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: -1, want: 127}, + test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: 0, want: -128}, + test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: 0, want: -128}, + test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: 1, want: -127}, + test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: 1, want: -127}, + test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: 126, want: -2}, + test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: 126, want: -2}, + test_int8{fn: add_Neg128_int8, fnname: "add_Neg128_int8", in: 127, want: -1}, + test_int8{fn: add_int8_Neg128, fnname: "add_int8_Neg128", in: 127, want: -1}, + test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: -128, want: 1}, + test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: -128, want: 1}, + test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: -127, want: 2}, + test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: -127, want: 2}, + test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: -1, want: -128}, + test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: -1, want: -128}, + test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: 0, want: -127}, + test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: 0, want: -127}, + test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: 1, want: -126}, + test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: 1, want: -126}, + test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: 126, want: -1}, + test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: 126, want: -1}, + test_int8{fn: add_Neg127_int8, fnname: "add_Neg127_int8", in: 127, want: 0}, + test_int8{fn: add_int8_Neg127, fnname: "add_int8_Neg127", in: 127, want: 0}, + test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: -128, want: 127}, + test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: -128, want: 127}, + test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: -127, want: -128}, + test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: -127, want: -128}, + test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: -1, want: -2}, + test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: -1, want: -2}, + test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: 0, want: -1}, + test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: 0, want: -1}, + test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: 1, want: 0}, + test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: 1, want: 0}, + test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: 126, want: 125}, + test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: 126, want: 125}, + test_int8{fn: add_Neg1_int8, fnname: "add_Neg1_int8", in: 127, want: 126}, + test_int8{fn: add_int8_Neg1, fnname: "add_int8_Neg1", in: 127, want: 126}, + test_int8{fn: add_0_int8, fnname: "add_0_int8", in: -128, want: -128}, + test_int8{fn: add_int8_0, fnname: "add_int8_0", in: -128, want: -128}, + test_int8{fn: add_0_int8, fnname: "add_0_int8", in: -127, want: -127}, + test_int8{fn: add_int8_0, fnname: "add_int8_0", in: -127, want: -127}, + test_int8{fn: add_0_int8, fnname: "add_0_int8", in: -1, want: -1}, + test_int8{fn: add_int8_0, fnname: "add_int8_0", in: -1, want: -1}, + test_int8{fn: add_0_int8, fnname: "add_0_int8", in: 0, want: 0}, + test_int8{fn: add_int8_0, fnname: "add_int8_0", in: 0, want: 0}, + test_int8{fn: add_0_int8, fnname: "add_0_int8", in: 1, want: 1}, + test_int8{fn: add_int8_0, fnname: "add_int8_0", in: 1, want: 1}, + test_int8{fn: add_0_int8, fnname: "add_0_int8", in: 126, want: 126}, + test_int8{fn: add_int8_0, fnname: "add_int8_0", in: 126, want: 126}, + test_int8{fn: add_0_int8, fnname: "add_0_int8", in: 127, want: 127}, + test_int8{fn: add_int8_0, fnname: "add_int8_0", in: 127, want: 127}, + test_int8{fn: add_1_int8, fnname: "add_1_int8", in: -128, want: -127}, + test_int8{fn: add_int8_1, fnname: "add_int8_1", in: -128, want: -127}, + test_int8{fn: add_1_int8, fnname: "add_1_int8", in: -127, want: -126}, + test_int8{fn: add_int8_1, fnname: "add_int8_1", in: -127, want: -126}, + test_int8{fn: add_1_int8, fnname: "add_1_int8", in: -1, want: 0}, + test_int8{fn: add_int8_1, fnname: "add_int8_1", in: -1, want: 0}, + test_int8{fn: add_1_int8, fnname: "add_1_int8", in: 0, want: 1}, + test_int8{fn: add_int8_1, fnname: "add_int8_1", in: 0, want: 1}, + test_int8{fn: add_1_int8, fnname: "add_1_int8", in: 1, want: 2}, + test_int8{fn: add_int8_1, fnname: "add_int8_1", in: 1, want: 2}, + test_int8{fn: add_1_int8, fnname: "add_1_int8", in: 126, want: 127}, + test_int8{fn: add_int8_1, fnname: "add_int8_1", in: 126, want: 127}, + test_int8{fn: add_1_int8, fnname: "add_1_int8", in: 127, want: -128}, + test_int8{fn: add_int8_1, fnname: "add_int8_1", in: 127, want: -128}, + test_int8{fn: add_126_int8, fnname: "add_126_int8", in: -128, want: -2}, + test_int8{fn: add_int8_126, fnname: "add_int8_126", in: -128, want: -2}, + test_int8{fn: add_126_int8, fnname: "add_126_int8", in: -127, want: -1}, + test_int8{fn: add_int8_126, fnname: "add_int8_126", in: -127, want: -1}, + test_int8{fn: add_126_int8, fnname: "add_126_int8", in: -1, want: 125}, + test_int8{fn: add_int8_126, fnname: "add_int8_126", in: -1, want: 125}, + test_int8{fn: add_126_int8, fnname: "add_126_int8", in: 0, want: 126}, + test_int8{fn: add_int8_126, fnname: "add_int8_126", in: 0, want: 126}, + test_int8{fn: add_126_int8, fnname: "add_126_int8", in: 1, want: 127}, + test_int8{fn: add_int8_126, fnname: "add_int8_126", in: 1, want: 127}, + test_int8{fn: add_126_int8, fnname: "add_126_int8", in: 126, want: -4}, + test_int8{fn: add_int8_126, fnname: "add_int8_126", in: 126, want: -4}, + test_int8{fn: add_126_int8, fnname: "add_126_int8", in: 127, want: -3}, + test_int8{fn: add_int8_126, fnname: "add_int8_126", in: 127, want: -3}, + test_int8{fn: add_127_int8, fnname: "add_127_int8", in: -128, want: -1}, + test_int8{fn: add_int8_127, fnname: "add_int8_127", in: -128, want: -1}, + test_int8{fn: add_127_int8, fnname: "add_127_int8", in: -127, want: 0}, + test_int8{fn: add_int8_127, fnname: "add_int8_127", in: -127, want: 0}, + test_int8{fn: add_127_int8, fnname: "add_127_int8", in: -1, want: 126}, + test_int8{fn: add_int8_127, fnname: "add_int8_127", in: -1, want: 126}, + test_int8{fn: add_127_int8, fnname: "add_127_int8", in: 0, want: 127}, + test_int8{fn: add_int8_127, fnname: "add_int8_127", in: 0, want: 127}, + test_int8{fn: add_127_int8, fnname: "add_127_int8", in: 1, want: -128}, + test_int8{fn: add_int8_127, fnname: "add_int8_127", in: 1, want: -128}, + test_int8{fn: add_127_int8, fnname: "add_127_int8", in: 126, want: -3}, + test_int8{fn: add_int8_127, fnname: "add_int8_127", in: 126, want: -3}, + test_int8{fn: add_127_int8, fnname: "add_127_int8", in: 127, want: -2}, + test_int8{fn: add_int8_127, fnname: "add_int8_127", in: 127, want: -2}, + test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: -128, want: 0}, + test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: -128, want: 0}, + test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: -127, want: -1}, + test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: -127, want: 1}, + test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: -1, want: -127}, + test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: -1, want: 127}, + test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: 0, want: -128}, + test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: 0, want: -128}, + test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: 1, want: 127}, + test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: 1, want: -127}, + test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: 126, want: 2}, + test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: 126, want: -2}, + test_int8{fn: sub_Neg128_int8, fnname: "sub_Neg128_int8", in: 127, want: 1}, + test_int8{fn: sub_int8_Neg128, fnname: "sub_int8_Neg128", in: 127, want: -1}, + test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: -128, want: 1}, + test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: -128, want: -1}, + test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: -127, want: 0}, + test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: -127, want: 0}, + test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: -1, want: -126}, + test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: -1, want: 126}, + test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: 0, want: -127}, + test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: 0, want: 127}, + test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: 1, want: -128}, + test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: 1, want: -128}, + test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: 126, want: 3}, + test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: 126, want: -3}, + test_int8{fn: sub_Neg127_int8, fnname: "sub_Neg127_int8", in: 127, want: 2}, + test_int8{fn: sub_int8_Neg127, fnname: "sub_int8_Neg127", in: 127, want: -2}, + test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: -128, want: 127}, + test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: -128, want: -127}, + test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: -127, want: 126}, + test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: -127, want: -126}, + test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: -1, want: 0}, + test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: -1, want: 0}, + test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: 0, want: -1}, + test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: 0, want: 1}, + test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: 1, want: -2}, + test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: 1, want: 2}, + test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: 126, want: -127}, + test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: 126, want: 127}, + test_int8{fn: sub_Neg1_int8, fnname: "sub_Neg1_int8", in: 127, want: -128}, + test_int8{fn: sub_int8_Neg1, fnname: "sub_int8_Neg1", in: 127, want: -128}, + test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: -128, want: -128}, + test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: -128, want: -128}, + test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: -127, want: 127}, + test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: -127, want: -127}, + test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: -1, want: 1}, + test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: -1, want: -1}, + test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: 0, want: 0}, + test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: 0, want: 0}, + test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: 1, want: -1}, + test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: 1, want: 1}, + test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: 126, want: -126}, + test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: 126, want: 126}, + test_int8{fn: sub_0_int8, fnname: "sub_0_int8", in: 127, want: -127}, + test_int8{fn: sub_int8_0, fnname: "sub_int8_0", in: 127, want: 127}, + test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: -128, want: -127}, + test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: -128, want: 127}, + test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: -127, want: -128}, + test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: -127, want: -128}, + test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: -1, want: 2}, + test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: -1, want: -2}, + test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: 0, want: 1}, + test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: 0, want: -1}, + test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: 1, want: 0}, + test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: 1, want: 0}, + test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: 126, want: -125}, + test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: 126, want: 125}, + test_int8{fn: sub_1_int8, fnname: "sub_1_int8", in: 127, want: -126}, + test_int8{fn: sub_int8_1, fnname: "sub_int8_1", in: 127, want: 126}, + test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: -128, want: -2}, + test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: -128, want: 2}, + test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: -127, want: -3}, + test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: -127, want: 3}, + test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: -1, want: 127}, + test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: -1, want: -127}, + test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: 0, want: 126}, + test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: 0, want: -126}, + test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: 1, want: 125}, + test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: 1, want: -125}, + test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: 126, want: 0}, + test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: 126, want: 0}, + test_int8{fn: sub_126_int8, fnname: "sub_126_int8", in: 127, want: -1}, + test_int8{fn: sub_int8_126, fnname: "sub_int8_126", in: 127, want: 1}, + test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: -128, want: -1}, + test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: -128, want: 1}, + test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: -127, want: -2}, + test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: -127, want: 2}, + test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: -1, want: -128}, + test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: -1, want: -128}, + test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: 0, want: 127}, + test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: 0, want: -127}, + test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: 1, want: 126}, + test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: 1, want: -126}, + test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: 126, want: 1}, + test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: 126, want: -1}, + test_int8{fn: sub_127_int8, fnname: "sub_127_int8", in: 127, want: 0}, + test_int8{fn: sub_int8_127, fnname: "sub_int8_127", in: 127, want: 0}, + test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: -128, want: 1}, + test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: -128, want: 1}, + test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: -127, want: 1}, + test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: -127, want: 0}, + test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: -1, want: -128}, + test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: -1, want: 0}, + test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: 0, want: 0}, + test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: 1, want: -128}, + test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: 1, want: 0}, + test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: 126, want: -1}, + test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: 126, want: 0}, + test_int8{fn: div_Neg128_int8, fnname: "div_Neg128_int8", in: 127, want: -1}, + test_int8{fn: div_int8_Neg128, fnname: "div_int8_Neg128", in: 127, want: 0}, + test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: -128, want: 0}, + test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: -128, want: 1}, + test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: -127, want: 1}, + test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: -127, want: 1}, + test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: -1, want: 127}, + test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: -1, want: 0}, + test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: 0, want: 0}, + test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: 1, want: -127}, + test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: 1, want: 0}, + test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: 126, want: -1}, + test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: 126, want: 0}, + test_int8{fn: div_Neg127_int8, fnname: "div_Neg127_int8", in: 127, want: -1}, + test_int8{fn: div_int8_Neg127, fnname: "div_int8_Neg127", in: 127, want: -1}, + test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: -128, want: 0}, + test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: -128, want: -128}, + test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: -127, want: 0}, + test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: -127, want: 127}, + test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: -1, want: 1}, + test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: -1, want: 1}, + test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: 0, want: 0}, + test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: 1, want: -1}, + test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: 1, want: -1}, + test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: 126, want: 0}, + test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: 126, want: -126}, + test_int8{fn: div_Neg1_int8, fnname: "div_Neg1_int8", in: 127, want: 0}, + test_int8{fn: div_int8_Neg1, fnname: "div_int8_Neg1", in: 127, want: -127}, + test_int8{fn: div_0_int8, fnname: "div_0_int8", in: -128, want: 0}, + test_int8{fn: div_0_int8, fnname: "div_0_int8", in: -127, want: 0}, + test_int8{fn: div_0_int8, fnname: "div_0_int8", in: -1, want: 0}, + test_int8{fn: div_0_int8, fnname: "div_0_int8", in: 1, want: 0}, + test_int8{fn: div_0_int8, fnname: "div_0_int8", in: 126, want: 0}, + test_int8{fn: div_0_int8, fnname: "div_0_int8", in: 127, want: 0}, + test_int8{fn: div_1_int8, fnname: "div_1_int8", in: -128, want: 0}, + test_int8{fn: div_int8_1, fnname: "div_int8_1", in: -128, want: -128}, + test_int8{fn: div_1_int8, fnname: "div_1_int8", in: -127, want: 0}, + test_int8{fn: div_int8_1, fnname: "div_int8_1", in: -127, want: -127}, + test_int8{fn: div_1_int8, fnname: "div_1_int8", in: -1, want: -1}, + test_int8{fn: div_int8_1, fnname: "div_int8_1", in: -1, want: -1}, + test_int8{fn: div_int8_1, fnname: "div_int8_1", in: 0, want: 0}, + test_int8{fn: div_1_int8, fnname: "div_1_int8", in: 1, want: 1}, + test_int8{fn: div_int8_1, fnname: "div_int8_1", in: 1, want: 1}, + test_int8{fn: div_1_int8, fnname: "div_1_int8", in: 126, want: 0}, + test_int8{fn: div_int8_1, fnname: "div_int8_1", in: 126, want: 126}, + test_int8{fn: div_1_int8, fnname: "div_1_int8", in: 127, want: 0}, + test_int8{fn: div_int8_1, fnname: "div_int8_1", in: 127, want: 127}, + test_int8{fn: div_126_int8, fnname: "div_126_int8", in: -128, want: 0}, + test_int8{fn: div_int8_126, fnname: "div_int8_126", in: -128, want: -1}, + test_int8{fn: div_126_int8, fnname: "div_126_int8", in: -127, want: 0}, + test_int8{fn: div_int8_126, fnname: "div_int8_126", in: -127, want: -1}, + test_int8{fn: div_126_int8, fnname: "div_126_int8", in: -1, want: -126}, + test_int8{fn: div_int8_126, fnname: "div_int8_126", in: -1, want: 0}, + test_int8{fn: div_int8_126, fnname: "div_int8_126", in: 0, want: 0}, + test_int8{fn: div_126_int8, fnname: "div_126_int8", in: 1, want: 126}, + test_int8{fn: div_int8_126, fnname: "div_int8_126", in: 1, want: 0}, + test_int8{fn: div_126_int8, fnname: "div_126_int8", in: 126, want: 1}, + test_int8{fn: div_int8_126, fnname: "div_int8_126", in: 126, want: 1}, + test_int8{fn: div_126_int8, fnname: "div_126_int8", in: 127, want: 0}, + test_int8{fn: div_int8_126, fnname: "div_int8_126", in: 127, want: 1}, + test_int8{fn: div_127_int8, fnname: "div_127_int8", in: -128, want: 0}, + test_int8{fn: div_int8_127, fnname: "div_int8_127", in: -128, want: -1}, + test_int8{fn: div_127_int8, fnname: "div_127_int8", in: -127, want: -1}, + test_int8{fn: div_int8_127, fnname: "div_int8_127", in: -127, want: -1}, + test_int8{fn: div_127_int8, fnname: "div_127_int8", in: -1, want: -127}, + test_int8{fn: div_int8_127, fnname: "div_int8_127", in: -1, want: 0}, + test_int8{fn: div_int8_127, fnname: "div_int8_127", in: 0, want: 0}, + test_int8{fn: div_127_int8, fnname: "div_127_int8", in: 1, want: 127}, + test_int8{fn: div_int8_127, fnname: "div_int8_127", in: 1, want: 0}, + test_int8{fn: div_127_int8, fnname: "div_127_int8", in: 126, want: 1}, + test_int8{fn: div_int8_127, fnname: "div_int8_127", in: 126, want: 0}, + test_int8{fn: div_127_int8, fnname: "div_127_int8", in: 127, want: 1}, + test_int8{fn: div_int8_127, fnname: "div_int8_127", in: 127, want: 1}, + test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: -128, want: 0}, + test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: -128, want: 0}, + test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: -127, want: -128}, + test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: -127, want: -128}, + test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: -1, want: -128}, + test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: -1, want: -128}, + test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: 0, want: 0}, + test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: 0, want: 0}, + test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: 1, want: -128}, + test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: 1, want: -128}, + test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: 126, want: 0}, + test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: 126, want: 0}, + test_int8{fn: mul_Neg128_int8, fnname: "mul_Neg128_int8", in: 127, want: -128}, + test_int8{fn: mul_int8_Neg128, fnname: "mul_int8_Neg128", in: 127, want: -128}, + test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: -128, want: -128}, + test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: -128, want: -128}, + test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: -127, want: 1}, + test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: -127, want: 1}, + test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: -1, want: 127}, + test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: -1, want: 127}, + test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: 0, want: 0}, + test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: 0, want: 0}, + test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: 1, want: -127}, + test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: 1, want: -127}, + test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: 126, want: 126}, + test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: 126, want: 126}, + test_int8{fn: mul_Neg127_int8, fnname: "mul_Neg127_int8", in: 127, want: -1}, + test_int8{fn: mul_int8_Neg127, fnname: "mul_int8_Neg127", in: 127, want: -1}, + test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: -128, want: -128}, + test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: -128, want: -128}, + test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: -127, want: 127}, + test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: -127, want: 127}, + test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: -1, want: 1}, + test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: -1, want: 1}, + test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: 0, want: 0}, + test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: 0, want: 0}, + test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: 1, want: -1}, + test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: 1, want: -1}, + test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: 126, want: -126}, + test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: 126, want: -126}, + test_int8{fn: mul_Neg1_int8, fnname: "mul_Neg1_int8", in: 127, want: -127}, + test_int8{fn: mul_int8_Neg1, fnname: "mul_int8_Neg1", in: 127, want: -127}, + test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: -128, want: 0}, + test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: -128, want: 0}, + test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: -127, want: 0}, + test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: -127, want: 0}, + test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: -1, want: 0}, + test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: -1, want: 0}, + test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: 0, want: 0}, + test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: 0, want: 0}, + test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: 1, want: 0}, + test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: 1, want: 0}, + test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: 126, want: 0}, + test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: 126, want: 0}, + test_int8{fn: mul_0_int8, fnname: "mul_0_int8", in: 127, want: 0}, + test_int8{fn: mul_int8_0, fnname: "mul_int8_0", in: 127, want: 0}, + test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: -128, want: -128}, + test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: -128, want: -128}, + test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: -127, want: -127}, + test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: -127, want: -127}, + test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: -1, want: -1}, + test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: -1, want: -1}, + test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: 0, want: 0}, + test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: 0, want: 0}, + test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: 1, want: 1}, + test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: 1, want: 1}, + test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: 126, want: 126}, + test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: 126, want: 126}, + test_int8{fn: mul_1_int8, fnname: "mul_1_int8", in: 127, want: 127}, + test_int8{fn: mul_int8_1, fnname: "mul_int8_1", in: 127, want: 127}, + test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: -128, want: 0}, + test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: -128, want: 0}, + test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: -127, want: 126}, + test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: -127, want: 126}, + test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: -1, want: -126}, + test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: -1, want: -126}, + test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: 0, want: 0}, + test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: 0, want: 0}, + test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: 1, want: 126}, + test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: 1, want: 126}, + test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: 126, want: 4}, + test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: 126, want: 4}, + test_int8{fn: mul_126_int8, fnname: "mul_126_int8", in: 127, want: -126}, + test_int8{fn: mul_int8_126, fnname: "mul_int8_126", in: 127, want: -126}, + test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: -128, want: -128}, + test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: -128, want: -128}, + test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: -127, want: -1}, + test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: -127, want: -1}, + test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: -1, want: -127}, + test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: -1, want: -127}, + test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: 0, want: 0}, + test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: 0, want: 0}, + test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: 1, want: 127}, + test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: 1, want: 127}, + test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: 126, want: -126}, + test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: 126, want: -126}, + test_int8{fn: mul_127_int8, fnname: "mul_127_int8", in: 127, want: 1}, + test_int8{fn: mul_int8_127, fnname: "mul_int8_127", in: 127, want: 1}, + test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: -128, want: 0}, + test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: -128, want: 0}, + test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: -127, want: -1}, + test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: -127, want: -127}, + test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: -1, want: 0}, + test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: -1, want: -1}, + test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: 0, want: 0}, + test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: 1, want: 0}, + test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: 1, want: 1}, + test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: 126, want: -2}, + test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: 126, want: 126}, + test_int8{fn: mod_Neg128_int8, fnname: "mod_Neg128_int8", in: 127, want: -1}, + test_int8{fn: mod_int8_Neg128, fnname: "mod_int8_Neg128", in: 127, want: 127}, + test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: -128, want: -127}, + test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: -128, want: -1}, + test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: -127, want: 0}, + test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: -127, want: 0}, + test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: -1, want: 0}, + test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: -1, want: -1}, + test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: 0, want: 0}, + test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: 1, want: 0}, + test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: 1, want: 1}, + test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: 126, want: -1}, + test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: 126, want: 126}, + test_int8{fn: mod_Neg127_int8, fnname: "mod_Neg127_int8", in: 127, want: 0}, + test_int8{fn: mod_int8_Neg127, fnname: "mod_int8_Neg127", in: 127, want: 0}, + test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: -128, want: -1}, + test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: -128, want: 0}, + test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: -127, want: -1}, + test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: -127, want: 0}, + test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: -1, want: 0}, + test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: -1, want: 0}, + test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: 0, want: 0}, + test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: 1, want: 0}, + test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: 1, want: 0}, + test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: 126, want: -1}, + test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: 126, want: 0}, + test_int8{fn: mod_Neg1_int8, fnname: "mod_Neg1_int8", in: 127, want: -1}, + test_int8{fn: mod_int8_Neg1, fnname: "mod_int8_Neg1", in: 127, want: 0}, + test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: -128, want: 0}, + test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: -127, want: 0}, + test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: -1, want: 0}, + test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: 1, want: 0}, + test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: 126, want: 0}, + test_int8{fn: mod_0_int8, fnname: "mod_0_int8", in: 127, want: 0}, + test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: -128, want: 1}, + test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: -128, want: 0}, + test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: -127, want: 1}, + test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: -127, want: 0}, + test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: -1, want: 0}, + test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: -1, want: 0}, + test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: 0, want: 0}, + test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: 1, want: 0}, + test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: 1, want: 0}, + test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: 126, want: 1}, + test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: 126, want: 0}, + test_int8{fn: mod_1_int8, fnname: "mod_1_int8", in: 127, want: 1}, + test_int8{fn: mod_int8_1, fnname: "mod_int8_1", in: 127, want: 0}, + test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: -128, want: 126}, + test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: -128, want: -2}, + test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: -127, want: 126}, + test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: -127, want: -1}, + test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: -1, want: 0}, + test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: -1, want: -1}, + test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: 0, want: 0}, + test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: 1, want: 0}, + test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: 1, want: 1}, + test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: 126, want: 0}, + test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: 126, want: 0}, + test_int8{fn: mod_126_int8, fnname: "mod_126_int8", in: 127, want: 126}, + test_int8{fn: mod_int8_126, fnname: "mod_int8_126", in: 127, want: 1}, + test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: -128, want: 127}, + test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: -128, want: -1}, + test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: -127, want: 0}, + test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: -127, want: 0}, + test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: -1, want: 0}, + test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: -1, want: -1}, + test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: 0, want: 0}, + test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: 1, want: 0}, + test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: 1, want: 1}, + test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: 126, want: 1}, + test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: 126, want: 126}, + test_int8{fn: mod_127_int8, fnname: "mod_127_int8", in: 127, want: 0}, + test_int8{fn: mod_int8_127, fnname: "mod_int8_127", in: 127, want: 0}, + test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: -128, want: -128}, + test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: -128, want: -128}, + test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: -127, want: -128}, + test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: -127, want: -128}, + test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: -1, want: -128}, + test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: -1, want: -128}, + test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: 0, want: 0}, + test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: 0, want: 0}, + test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: 1, want: 0}, + test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: 1, want: 0}, + test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: 126, want: 0}, + test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: 126, want: 0}, + test_int8{fn: and_Neg128_int8, fnname: "and_Neg128_int8", in: 127, want: 0}, + test_int8{fn: and_int8_Neg128, fnname: "and_int8_Neg128", in: 127, want: 0}, + test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: -128, want: -128}, + test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: -128, want: -128}, + test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: -127, want: -127}, + test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: -127, want: -127}, + test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: -1, want: -127}, + test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: -1, want: -127}, + test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: 0, want: 0}, + test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: 0, want: 0}, + test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: 1, want: 1}, + test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: 1, want: 1}, + test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: 126, want: 0}, + test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: 126, want: 0}, + test_int8{fn: and_Neg127_int8, fnname: "and_Neg127_int8", in: 127, want: 1}, + test_int8{fn: and_int8_Neg127, fnname: "and_int8_Neg127", in: 127, want: 1}, + test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: -128, want: -128}, + test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: -128, want: -128}, + test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: -127, want: -127}, + test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: -127, want: -127}, + test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: -1, want: -1}, + test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: -1, want: -1}, + test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: 0, want: 0}, + test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: 0, want: 0}, + test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: 1, want: 1}, + test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: 1, want: 1}, + test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: 126, want: 126}, + test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: 126, want: 126}, + test_int8{fn: and_Neg1_int8, fnname: "and_Neg1_int8", in: 127, want: 127}, + test_int8{fn: and_int8_Neg1, fnname: "and_int8_Neg1", in: 127, want: 127}, + test_int8{fn: and_0_int8, fnname: "and_0_int8", in: -128, want: 0}, + test_int8{fn: and_int8_0, fnname: "and_int8_0", in: -128, want: 0}, + test_int8{fn: and_0_int8, fnname: "and_0_int8", in: -127, want: 0}, + test_int8{fn: and_int8_0, fnname: "and_int8_0", in: -127, want: 0}, + test_int8{fn: and_0_int8, fnname: "and_0_int8", in: -1, want: 0}, + test_int8{fn: and_int8_0, fnname: "and_int8_0", in: -1, want: 0}, + test_int8{fn: and_0_int8, fnname: "and_0_int8", in: 0, want: 0}, + test_int8{fn: and_int8_0, fnname: "and_int8_0", in: 0, want: 0}, + test_int8{fn: and_0_int8, fnname: "and_0_int8", in: 1, want: 0}, + test_int8{fn: and_int8_0, fnname: "and_int8_0", in: 1, want: 0}, + test_int8{fn: and_0_int8, fnname: "and_0_int8", in: 126, want: 0}, + test_int8{fn: and_int8_0, fnname: "and_int8_0", in: 126, want: 0}, + test_int8{fn: and_0_int8, fnname: "and_0_int8", in: 127, want: 0}, + test_int8{fn: and_int8_0, fnname: "and_int8_0", in: 127, want: 0}, + test_int8{fn: and_1_int8, fnname: "and_1_int8", in: -128, want: 0}, + test_int8{fn: and_int8_1, fnname: "and_int8_1", in: -128, want: 0}, + test_int8{fn: and_1_int8, fnname: "and_1_int8", in: -127, want: 1}, + test_int8{fn: and_int8_1, fnname: "and_int8_1", in: -127, want: 1}, + test_int8{fn: and_1_int8, fnname: "and_1_int8", in: -1, want: 1}, + test_int8{fn: and_int8_1, fnname: "and_int8_1", in: -1, want: 1}, + test_int8{fn: and_1_int8, fnname: "and_1_int8", in: 0, want: 0}, + test_int8{fn: and_int8_1, fnname: "and_int8_1", in: 0, want: 0}, + test_int8{fn: and_1_int8, fnname: "and_1_int8", in: 1, want: 1}, + test_int8{fn: and_int8_1, fnname: "and_int8_1", in: 1, want: 1}, + test_int8{fn: and_1_int8, fnname: "and_1_int8", in: 126, want: 0}, + test_int8{fn: and_int8_1, fnname: "and_int8_1", in: 126, want: 0}, + test_int8{fn: and_1_int8, fnname: "and_1_int8", in: 127, want: 1}, + test_int8{fn: and_int8_1, fnname: "and_int8_1", in: 127, want: 1}, + test_int8{fn: and_126_int8, fnname: "and_126_int8", in: -128, want: 0}, + test_int8{fn: and_int8_126, fnname: "and_int8_126", in: -128, want: 0}, + test_int8{fn: and_126_int8, fnname: "and_126_int8", in: -127, want: 0}, + test_int8{fn: and_int8_126, fnname: "and_int8_126", in: -127, want: 0}, + test_int8{fn: and_126_int8, fnname: "and_126_int8", in: -1, want: 126}, + test_int8{fn: and_int8_126, fnname: "and_int8_126", in: -1, want: 126}, + test_int8{fn: and_126_int8, fnname: "and_126_int8", in: 0, want: 0}, + test_int8{fn: and_int8_126, fnname: "and_int8_126", in: 0, want: 0}, + test_int8{fn: and_126_int8, fnname: "and_126_int8", in: 1, want: 0}, + test_int8{fn: and_int8_126, fnname: "and_int8_126", in: 1, want: 0}, + test_int8{fn: and_126_int8, fnname: "and_126_int8", in: 126, want: 126}, + test_int8{fn: and_int8_126, fnname: "and_int8_126", in: 126, want: 126}, + test_int8{fn: and_126_int8, fnname: "and_126_int8", in: 127, want: 126}, + test_int8{fn: and_int8_126, fnname: "and_int8_126", in: 127, want: 126}, + test_int8{fn: and_127_int8, fnname: "and_127_int8", in: -128, want: 0}, + test_int8{fn: and_int8_127, fnname: "and_int8_127", in: -128, want: 0}, + test_int8{fn: and_127_int8, fnname: "and_127_int8", in: -127, want: 1}, + test_int8{fn: and_int8_127, fnname: "and_int8_127", in: -127, want: 1}, + test_int8{fn: and_127_int8, fnname: "and_127_int8", in: -1, want: 127}, + test_int8{fn: and_int8_127, fnname: "and_int8_127", in: -1, want: 127}, + test_int8{fn: and_127_int8, fnname: "and_127_int8", in: 0, want: 0}, + test_int8{fn: and_int8_127, fnname: "and_int8_127", in: 0, want: 0}, + test_int8{fn: and_127_int8, fnname: "and_127_int8", in: 1, want: 1}, + test_int8{fn: and_int8_127, fnname: "and_int8_127", in: 1, want: 1}, + test_int8{fn: and_127_int8, fnname: "and_127_int8", in: 126, want: 126}, + test_int8{fn: and_int8_127, fnname: "and_int8_127", in: 126, want: 126}, + test_int8{fn: and_127_int8, fnname: "and_127_int8", in: 127, want: 127}, + test_int8{fn: and_int8_127, fnname: "and_int8_127", in: 127, want: 127}, + test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: -128, want: -128}, + test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: -128, want: -128}, + test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: -127, want: -127}, + test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: -127, want: -127}, + test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: -1, want: -1}, + test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: -1, want: -1}, + test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: 0, want: -128}, + test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: 0, want: -128}, + test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: 1, want: -127}, + test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: 1, want: -127}, + test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: 126, want: -2}, + test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: 126, want: -2}, + test_int8{fn: or_Neg128_int8, fnname: "or_Neg128_int8", in: 127, want: -1}, + test_int8{fn: or_int8_Neg128, fnname: "or_int8_Neg128", in: 127, want: -1}, + test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: -128, want: -127}, + test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: -128, want: -127}, + test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: -127, want: -127}, + test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: -127, want: -127}, + test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: -1, want: -1}, + test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: -1, want: -1}, + test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: 0, want: -127}, + test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: 0, want: -127}, + test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: 1, want: -127}, + test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: 1, want: -127}, + test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: 126, want: -1}, + test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: 126, want: -1}, + test_int8{fn: or_Neg127_int8, fnname: "or_Neg127_int8", in: 127, want: -1}, + test_int8{fn: or_int8_Neg127, fnname: "or_int8_Neg127", in: 127, want: -1}, + test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: -128, want: -1}, + test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: -128, want: -1}, + test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: -127, want: -1}, + test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: -127, want: -1}, + test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: -1, want: -1}, + test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: -1, want: -1}, + test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: 0, want: -1}, + test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: 0, want: -1}, + test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: 1, want: -1}, + test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: 1, want: -1}, + test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: 126, want: -1}, + test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: 126, want: -1}, + test_int8{fn: or_Neg1_int8, fnname: "or_Neg1_int8", in: 127, want: -1}, + test_int8{fn: or_int8_Neg1, fnname: "or_int8_Neg1", in: 127, want: -1}, + test_int8{fn: or_0_int8, fnname: "or_0_int8", in: -128, want: -128}, + test_int8{fn: or_int8_0, fnname: "or_int8_0", in: -128, want: -128}, + test_int8{fn: or_0_int8, fnname: "or_0_int8", in: -127, want: -127}, + test_int8{fn: or_int8_0, fnname: "or_int8_0", in: -127, want: -127}, + test_int8{fn: or_0_int8, fnname: "or_0_int8", in: -1, want: -1}, + test_int8{fn: or_int8_0, fnname: "or_int8_0", in: -1, want: -1}, + test_int8{fn: or_0_int8, fnname: "or_0_int8", in: 0, want: 0}, + test_int8{fn: or_int8_0, fnname: "or_int8_0", in: 0, want: 0}, + test_int8{fn: or_0_int8, fnname: "or_0_int8", in: 1, want: 1}, + test_int8{fn: or_int8_0, fnname: "or_int8_0", in: 1, want: 1}, + test_int8{fn: or_0_int8, fnname: "or_0_int8", in: 126, want: 126}, + test_int8{fn: or_int8_0, fnname: "or_int8_0", in: 126, want: 126}, + test_int8{fn: or_0_int8, fnname: "or_0_int8", in: 127, want: 127}, + test_int8{fn: or_int8_0, fnname: "or_int8_0", in: 127, want: 127}, + test_int8{fn: or_1_int8, fnname: "or_1_int8", in: -128, want: -127}, + test_int8{fn: or_int8_1, fnname: "or_int8_1", in: -128, want: -127}, + test_int8{fn: or_1_int8, fnname: "or_1_int8", in: -127, want: -127}, + test_int8{fn: or_int8_1, fnname: "or_int8_1", in: -127, want: -127}, + test_int8{fn: or_1_int8, fnname: "or_1_int8", in: -1, want: -1}, + test_int8{fn: or_int8_1, fnname: "or_int8_1", in: -1, want: -1}, + test_int8{fn: or_1_int8, fnname: "or_1_int8", in: 0, want: 1}, + test_int8{fn: or_int8_1, fnname: "or_int8_1", in: 0, want: 1}, + test_int8{fn: or_1_int8, fnname: "or_1_int8", in: 1, want: 1}, + test_int8{fn: or_int8_1, fnname: "or_int8_1", in: 1, want: 1}, + test_int8{fn: or_1_int8, fnname: "or_1_int8", in: 126, want: 127}, + test_int8{fn: or_int8_1, fnname: "or_int8_1", in: 126, want: 127}, + test_int8{fn: or_1_int8, fnname: "or_1_int8", in: 127, want: 127}, + test_int8{fn: or_int8_1, fnname: "or_int8_1", in: 127, want: 127}, + test_int8{fn: or_126_int8, fnname: "or_126_int8", in: -128, want: -2}, + test_int8{fn: or_int8_126, fnname: "or_int8_126", in: -128, want: -2}, + test_int8{fn: or_126_int8, fnname: "or_126_int8", in: -127, want: -1}, + test_int8{fn: or_int8_126, fnname: "or_int8_126", in: -127, want: -1}, + test_int8{fn: or_126_int8, fnname: "or_126_int8", in: -1, want: -1}, + test_int8{fn: or_int8_126, fnname: "or_int8_126", in: -1, want: -1}, + test_int8{fn: or_126_int8, fnname: "or_126_int8", in: 0, want: 126}, + test_int8{fn: or_int8_126, fnname: "or_int8_126", in: 0, want: 126}, + test_int8{fn: or_126_int8, fnname: "or_126_int8", in: 1, want: 127}, + test_int8{fn: or_int8_126, fnname: "or_int8_126", in: 1, want: 127}, + test_int8{fn: or_126_int8, fnname: "or_126_int8", in: 126, want: 126}, + test_int8{fn: or_int8_126, fnname: "or_int8_126", in: 126, want: 126}, + test_int8{fn: or_126_int8, fnname: "or_126_int8", in: 127, want: 127}, + test_int8{fn: or_int8_126, fnname: "or_int8_126", in: 127, want: 127}, + test_int8{fn: or_127_int8, fnname: "or_127_int8", in: -128, want: -1}, + test_int8{fn: or_int8_127, fnname: "or_int8_127", in: -128, want: -1}, + test_int8{fn: or_127_int8, fnname: "or_127_int8", in: -127, want: -1}, + test_int8{fn: or_int8_127, fnname: "or_int8_127", in: -127, want: -1}, + test_int8{fn: or_127_int8, fnname: "or_127_int8", in: -1, want: -1}, + test_int8{fn: or_int8_127, fnname: "or_int8_127", in: -1, want: -1}, + test_int8{fn: or_127_int8, fnname: "or_127_int8", in: 0, want: 127}, + test_int8{fn: or_int8_127, fnname: "or_int8_127", in: 0, want: 127}, + test_int8{fn: or_127_int8, fnname: "or_127_int8", in: 1, want: 127}, + test_int8{fn: or_int8_127, fnname: "or_int8_127", in: 1, want: 127}, + test_int8{fn: or_127_int8, fnname: "or_127_int8", in: 126, want: 127}, + test_int8{fn: or_int8_127, fnname: "or_int8_127", in: 126, want: 127}, + test_int8{fn: or_127_int8, fnname: "or_127_int8", in: 127, want: 127}, + test_int8{fn: or_int8_127, fnname: "or_int8_127", in: 127, want: 127}, + test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: -128, want: 0}, + test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: -128, want: 0}, + test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: -127, want: 1}, + test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: -127, want: 1}, + test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: -1, want: 127}, + test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: -1, want: 127}, + test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: 0, want: -128}, + test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: 0, want: -128}, + test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: 1, want: -127}, + test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: 1, want: -127}, + test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: 126, want: -2}, + test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: 126, want: -2}, + test_int8{fn: xor_Neg128_int8, fnname: "xor_Neg128_int8", in: 127, want: -1}, + test_int8{fn: xor_int8_Neg128, fnname: "xor_int8_Neg128", in: 127, want: -1}, + test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: -128, want: 1}, + test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: -128, want: 1}, + test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: -127, want: 0}, + test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: -127, want: 0}, + test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: -1, want: 126}, + test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: -1, want: 126}, + test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: 0, want: -127}, + test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: 0, want: -127}, + test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: 1, want: -128}, + test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: 1, want: -128}, + test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: 126, want: -1}, + test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: 126, want: -1}, + test_int8{fn: xor_Neg127_int8, fnname: "xor_Neg127_int8", in: 127, want: -2}, + test_int8{fn: xor_int8_Neg127, fnname: "xor_int8_Neg127", in: 127, want: -2}, + test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: -128, want: 127}, + test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: -128, want: 127}, + test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: -127, want: 126}, + test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: -127, want: 126}, + test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: -1, want: 0}, + test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: -1, want: 0}, + test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: 0, want: -1}, + test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: 0, want: -1}, + test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: 1, want: -2}, + test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: 1, want: -2}, + test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: 126, want: -127}, + test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: 126, want: -127}, + test_int8{fn: xor_Neg1_int8, fnname: "xor_Neg1_int8", in: 127, want: -128}, + test_int8{fn: xor_int8_Neg1, fnname: "xor_int8_Neg1", in: 127, want: -128}, + test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: -128, want: -128}, + test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: -128, want: -128}, + test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: -127, want: -127}, + test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: -127, want: -127}, + test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: -1, want: -1}, + test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: -1, want: -1}, + test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: 0, want: 0}, + test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: 0, want: 0}, + test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: 1, want: 1}, + test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: 1, want: 1}, + test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: 126, want: 126}, + test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: 126, want: 126}, + test_int8{fn: xor_0_int8, fnname: "xor_0_int8", in: 127, want: 127}, + test_int8{fn: xor_int8_0, fnname: "xor_int8_0", in: 127, want: 127}, + test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: -128, want: -127}, + test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: -128, want: -127}, + test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: -127, want: -128}, + test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: -127, want: -128}, + test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: -1, want: -2}, + test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: -1, want: -2}, + test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: 0, want: 1}, + test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: 0, want: 1}, + test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: 1, want: 0}, + test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: 1, want: 0}, + test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: 126, want: 127}, + test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: 126, want: 127}, + test_int8{fn: xor_1_int8, fnname: "xor_1_int8", in: 127, want: 126}, + test_int8{fn: xor_int8_1, fnname: "xor_int8_1", in: 127, want: 126}, + test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: -128, want: -2}, + test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: -128, want: -2}, + test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: -127, want: -1}, + test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: -127, want: -1}, + test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: -1, want: -127}, + test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: -1, want: -127}, + test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: 0, want: 126}, + test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: 0, want: 126}, + test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: 1, want: 127}, + test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: 1, want: 127}, + test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: 126, want: 0}, + test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: 126, want: 0}, + test_int8{fn: xor_126_int8, fnname: "xor_126_int8", in: 127, want: 1}, + test_int8{fn: xor_int8_126, fnname: "xor_int8_126", in: 127, want: 1}, + test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: -128, want: -1}, + test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: -128, want: -1}, + test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: -127, want: -2}, + test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: -127, want: -2}, + test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: -1, want: -128}, + test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: -1, want: -128}, + test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: 0, want: 127}, + test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: 0, want: 127}, + test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: 1, want: 126}, + test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: 1, want: 126}, + test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: 126, want: 1}, + test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: 126, want: 1}, + test_int8{fn: xor_127_int8, fnname: "xor_127_int8", in: 127, want: 0}, + test_int8{fn: xor_int8_127, fnname: "xor_int8_127", in: 127, want: 0}} var failed bool func main() { - - if got := add_0_uint64_ssa(0); got != 0 { - fmt.Printf("add_uint64 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_uint64_0_ssa(0); got != 0 { - fmt.Printf("add_uint64 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_0_uint64_ssa(1); got != 1 { - fmt.Printf("add_uint64 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_uint64_0_ssa(1); got != 1 { - fmt.Printf("add_uint64 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_0_uint64_ssa(4294967296); got != 4294967296 { - fmt.Printf("add_uint64 0%s4294967296 = %d, wanted 4294967296\n", `+`, got) - failed = true - } - - if got := add_uint64_0_ssa(4294967296); got != 4294967296 { - fmt.Printf("add_uint64 4294967296%s0 = %d, wanted 4294967296\n", `+`, got) - failed = true - } - - if got := add_0_uint64_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("add_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("add_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_0_uint64_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("add_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `+`, got) - failed = true - } - - if got := add_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("add_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `+`, got) - failed = true - } - - if got := add_1_uint64_ssa(0); got != 1 { - fmt.Printf("add_uint64 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_uint64_1_ssa(0); got != 1 { - fmt.Printf("add_uint64 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_1_uint64_ssa(1); got != 2 { - fmt.Printf("add_uint64 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_uint64_1_ssa(1); got != 2 { - fmt.Printf("add_uint64 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_1_uint64_ssa(4294967296); got != 4294967297 { - fmt.Printf("add_uint64 1%s4294967296 = %d, wanted 4294967297\n", `+`, got) - failed = true - } - - if got := add_uint64_1_ssa(4294967296); got != 4294967297 { - fmt.Printf("add_uint64 4294967296%s1 = %d, wanted 4294967297\n", `+`, got) - failed = true - } - - if got := add_1_uint64_ssa(9223372036854775808); got != 9223372036854775809 { - fmt.Printf("add_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `+`, got) - failed = true - } - - if got := add_uint64_1_ssa(9223372036854775808); got != 9223372036854775809 { - fmt.Printf("add_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `+`, got) - failed = true - } - - if got := add_1_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("add_uint64 1%s18446744073709551615 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_uint64_1_ssa(18446744073709551615); got != 0 { - fmt.Printf("add_uint64 18446744073709551615%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_4294967296_uint64_ssa(0); got != 4294967296 { - fmt.Printf("add_uint64 4294967296%s0 = %d, wanted 4294967296\n", `+`, got) - failed = true - } - - if got := add_uint64_4294967296_ssa(0); got != 4294967296 { - fmt.Printf("add_uint64 0%s4294967296 = %d, wanted 4294967296\n", `+`, got) - failed = true - } - - if got := add_4294967296_uint64_ssa(1); got != 4294967297 { - fmt.Printf("add_uint64 4294967296%s1 = %d, wanted 4294967297\n", `+`, got) - failed = true - } - - if got := add_uint64_4294967296_ssa(1); got != 4294967297 { - fmt.Printf("add_uint64 1%s4294967296 = %d, wanted 4294967297\n", `+`, got) - failed = true - } - - if got := add_4294967296_uint64_ssa(4294967296); got != 8589934592 { - fmt.Printf("add_uint64 4294967296%s4294967296 = %d, wanted 8589934592\n", `+`, got) - failed = true - } - - if got := add_uint64_4294967296_ssa(4294967296); got != 8589934592 { - fmt.Printf("add_uint64 4294967296%s4294967296 = %d, wanted 8589934592\n", `+`, got) - failed = true - } - - if got := add_4294967296_uint64_ssa(9223372036854775808); got != 9223372041149743104 { - fmt.Printf("add_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `+`, got) - failed = true - } - - if got := add_uint64_4294967296_ssa(9223372036854775808); got != 9223372041149743104 { - fmt.Printf("add_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `+`, got) - failed = true - } - - if got := add_4294967296_uint64_ssa(18446744073709551615); got != 4294967295 { - fmt.Printf("add_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967295\n", `+`, got) - failed = true - } - - if got := add_uint64_4294967296_ssa(18446744073709551615); got != 4294967295 { - fmt.Printf("add_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `+`, got) - failed = true - } - - if got := add_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { - fmt.Printf("add_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_uint64_9223372036854775808_ssa(0); got != 9223372036854775808 { - fmt.Printf("add_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_9223372036854775808_uint64_ssa(1); got != 9223372036854775809 { - fmt.Printf("add_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `+`, got) - failed = true - } - - if got := add_uint64_9223372036854775808_ssa(1); got != 9223372036854775809 { - fmt.Printf("add_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `+`, got) - failed = true - } - - if got := add_9223372036854775808_uint64_ssa(4294967296); got != 9223372041149743104 { - fmt.Printf("add_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `+`, got) - failed = true - } - - if got := add_uint64_9223372036854775808_ssa(4294967296); got != 9223372041149743104 { - fmt.Printf("add_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `+`, got) - failed = true - } - - if got := add_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("add_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { - fmt.Printf("add_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775807 { - fmt.Printf("add_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775807 { - fmt.Printf("add_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { - fmt.Printf("add_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `+`, got) - failed = true - } - - if got := add_uint64_18446744073709551615_ssa(0); got != 18446744073709551615 { - fmt.Printf("add_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `+`, got) - failed = true - } - - if got := add_18446744073709551615_uint64_ssa(1); got != 0 { - fmt.Printf("add_uint64 18446744073709551615%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_uint64_18446744073709551615_ssa(1); got != 0 { - fmt.Printf("add_uint64 1%s18446744073709551615 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_18446744073709551615_uint64_ssa(4294967296); got != 4294967295 { - fmt.Printf("add_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `+`, got) - failed = true - } - - if got := add_uint64_18446744073709551615_ssa(4294967296); got != 4294967295 { - fmt.Printf("add_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967295\n", `+`, got) - failed = true - } - - if got := add_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775807 { - fmt.Printf("add_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775807 { - fmt.Printf("add_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_18446744073709551615_uint64_ssa(18446744073709551615); got != 18446744073709551614 { - fmt.Printf("add_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551614\n", `+`, got) - failed = true - } - - if got := add_uint64_18446744073709551615_ssa(18446744073709551615); got != 18446744073709551614 { - fmt.Printf("add_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551614\n", `+`, got) - failed = true - } - - if got := sub_0_uint64_ssa(0); got != 0 { - fmt.Printf("sub_uint64 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint64_0_ssa(0); got != 0 { - fmt.Printf("sub_uint64 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_0_uint64_ssa(1); got != 18446744073709551615 { - fmt.Printf("sub_uint64 0%s1 = %d, wanted 18446744073709551615\n", `-`, got) - failed = true - } - - if got := sub_uint64_0_ssa(1); got != 1 { - fmt.Printf("sub_uint64 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_0_uint64_ssa(4294967296); got != 18446744069414584320 { - fmt.Printf("sub_uint64 0%s4294967296 = %d, wanted 18446744069414584320\n", `-`, got) - failed = true - } - - if got := sub_uint64_0_ssa(4294967296); got != 4294967296 { - fmt.Printf("sub_uint64 4294967296%s0 = %d, wanted 4294967296\n", `-`, got) - failed = true - } - - if got := sub_0_uint64_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("sub_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("sub_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_0_uint64_ssa(18446744073709551615); got != 1 { - fmt.Printf("sub_uint64 0%s18446744073709551615 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("sub_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `-`, got) - failed = true - } - - if got := sub_1_uint64_ssa(0); got != 1 { - fmt.Printf("sub_uint64 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_uint64_1_ssa(0); got != 18446744073709551615 { - fmt.Printf("sub_uint64 0%s1 = %d, wanted 18446744073709551615\n", `-`, got) - failed = true - } - - if got := sub_1_uint64_ssa(1); got != 0 { - fmt.Printf("sub_uint64 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint64_1_ssa(1); got != 0 { - fmt.Printf("sub_uint64 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_1_uint64_ssa(4294967296); got != 18446744069414584321 { - fmt.Printf("sub_uint64 1%s4294967296 = %d, wanted 18446744069414584321\n", `-`, got) - failed = true - } - - if got := sub_uint64_1_ssa(4294967296); got != 4294967295 { - fmt.Printf("sub_uint64 4294967296%s1 = %d, wanted 4294967295\n", `-`, got) - failed = true - } - - if got := sub_1_uint64_ssa(9223372036854775808); got != 9223372036854775809 { - fmt.Printf("sub_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `-`, got) - failed = true - } - - if got := sub_uint64_1_ssa(9223372036854775808); got != 9223372036854775807 { - fmt.Printf("sub_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_1_uint64_ssa(18446744073709551615); got != 2 { - fmt.Printf("sub_uint64 1%s18446744073709551615 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_uint64_1_ssa(18446744073709551615); got != 18446744073709551614 { - fmt.Printf("sub_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `-`, got) - failed = true - } - - if got := sub_4294967296_uint64_ssa(0); got != 4294967296 { - fmt.Printf("sub_uint64 4294967296%s0 = %d, wanted 4294967296\n", `-`, got) - failed = true - } - - if got := sub_uint64_4294967296_ssa(0); got != 18446744069414584320 { - fmt.Printf("sub_uint64 0%s4294967296 = %d, wanted 18446744069414584320\n", `-`, got) - failed = true - } - - if got := sub_4294967296_uint64_ssa(1); got != 4294967295 { - fmt.Printf("sub_uint64 4294967296%s1 = %d, wanted 4294967295\n", `-`, got) - failed = true - } - - if got := sub_uint64_4294967296_ssa(1); got != 18446744069414584321 { - fmt.Printf("sub_uint64 1%s4294967296 = %d, wanted 18446744069414584321\n", `-`, got) - failed = true - } - - if got := sub_4294967296_uint64_ssa(4294967296); got != 0 { - fmt.Printf("sub_uint64 4294967296%s4294967296 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint64_4294967296_ssa(4294967296); got != 0 { - fmt.Printf("sub_uint64 4294967296%s4294967296 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_4294967296_uint64_ssa(9223372036854775808); got != 9223372041149743104 { - fmt.Printf("sub_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `-`, got) - failed = true - } - - if got := sub_uint64_4294967296_ssa(9223372036854775808); got != 9223372032559808512 { - fmt.Printf("sub_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372032559808512\n", `-`, got) - failed = true - } - - if got := sub_4294967296_uint64_ssa(18446744073709551615); got != 4294967297 { - fmt.Printf("sub_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967297\n", `-`, got) - failed = true - } - - if got := sub_uint64_4294967296_ssa(18446744073709551615); got != 18446744069414584319 { - fmt.Printf("sub_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584319\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { - fmt.Printf("sub_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_uint64_9223372036854775808_ssa(0); got != 9223372036854775808 { - fmt.Printf("sub_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775808_uint64_ssa(1); got != 9223372036854775807 { - fmt.Printf("sub_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_uint64_9223372036854775808_ssa(1); got != 9223372036854775809 { - fmt.Printf("sub_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775808_uint64_ssa(4294967296); got != 9223372032559808512 { - fmt.Printf("sub_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372032559808512\n", `-`, got) - failed = true - } - - if got := sub_uint64_9223372036854775808_ssa(4294967296); got != 9223372041149743104 { - fmt.Printf("sub_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("sub_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { - fmt.Printf("sub_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775809 { - fmt.Printf("sub_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775809\n", `-`, got) - failed = true - } - - if got := sub_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775807 { - fmt.Printf("sub_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { - fmt.Printf("sub_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `-`, got) - failed = true - } - - if got := sub_uint64_18446744073709551615_ssa(0); got != 1 { - fmt.Printf("sub_uint64 0%s18446744073709551615 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_18446744073709551615_uint64_ssa(1); got != 18446744073709551614 { - fmt.Printf("sub_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `-`, got) - failed = true - } - - if got := sub_uint64_18446744073709551615_ssa(1); got != 2 { - fmt.Printf("sub_uint64 1%s18446744073709551615 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_18446744073709551615_uint64_ssa(4294967296); got != 18446744069414584319 { - fmt.Printf("sub_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584319\n", `-`, got) - failed = true - } - - if got := sub_uint64_18446744073709551615_ssa(4294967296); got != 4294967297 { - fmt.Printf("sub_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967297\n", `-`, got) - failed = true - } - - if got := sub_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775807 { - fmt.Printf("sub_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775809 { - fmt.Printf("sub_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775809\n", `-`, got) - failed = true - } - - if got := sub_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("sub_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { - fmt.Printf("sub_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := div_0_uint64_ssa(1); got != 0 { - fmt.Printf("div_uint64 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_uint64_ssa(4294967296); got != 0 { - fmt.Printf("div_uint64 0%s4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("div_uint64 0%s9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("div_uint64 0%s18446744073709551615 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_uint64_1_ssa(0); got != 0 { - fmt.Printf("div_uint64 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_1_uint64_ssa(1); got != 1 { - fmt.Printf("div_uint64 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_uint64_1_ssa(1); got != 1 { - fmt.Printf("div_uint64 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_1_uint64_ssa(4294967296); got != 0 { - fmt.Printf("div_uint64 1%s4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_uint64_1_ssa(4294967296); got != 4294967296 { - fmt.Printf("div_uint64 4294967296%s1 = %d, wanted 4294967296\n", `/`, got) - failed = true - } - - if got := div_1_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("div_uint64 1%s9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_uint64_1_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("div_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775808\n", `/`, got) - failed = true - } - - if got := div_1_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("div_uint64 1%s18446744073709551615 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_uint64_1_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("div_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `/`, got) - failed = true - } - - if got := div_uint64_4294967296_ssa(0); got != 0 { - fmt.Printf("div_uint64 0%s4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_4294967296_uint64_ssa(1); got != 4294967296 { - fmt.Printf("div_uint64 4294967296%s1 = %d, wanted 4294967296\n", `/`, got) - failed = true - } - - if got := div_uint64_4294967296_ssa(1); got != 0 { - fmt.Printf("div_uint64 1%s4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_4294967296_uint64_ssa(4294967296); got != 1 { - fmt.Printf("div_uint64 4294967296%s4294967296 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_uint64_4294967296_ssa(4294967296); got != 1 { - fmt.Printf("div_uint64 4294967296%s4294967296 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_4294967296_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("div_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_uint64_4294967296_ssa(9223372036854775808); got != 2147483648 { - fmt.Printf("div_uint64 9223372036854775808%s4294967296 = %d, wanted 2147483648\n", `/`, got) - failed = true - } - - if got := div_4294967296_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("div_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_uint64_4294967296_ssa(18446744073709551615); got != 4294967295 { - fmt.Printf("div_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `/`, got) - failed = true - } - - if got := div_uint64_9223372036854775808_ssa(0); got != 0 { - fmt.Printf("div_uint64 0%s9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_9223372036854775808_uint64_ssa(1); got != 9223372036854775808 { - fmt.Printf("div_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775808\n", `/`, got) - failed = true - } - - if got := div_uint64_9223372036854775808_ssa(1); got != 0 { - fmt.Printf("div_uint64 1%s9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_9223372036854775808_uint64_ssa(4294967296); got != 2147483648 { - fmt.Printf("div_uint64 9223372036854775808%s4294967296 = %d, wanted 2147483648\n", `/`, got) - failed = true - } - - if got := div_uint64_9223372036854775808_ssa(4294967296); got != 0 { - fmt.Printf("div_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_9223372036854775808_uint64_ssa(9223372036854775808); got != 1 { - fmt.Printf("div_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_uint64_9223372036854775808_ssa(9223372036854775808); got != 1 { - fmt.Printf("div_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_9223372036854775808_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("div_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_uint64_9223372036854775808_ssa(18446744073709551615); got != 1 { - fmt.Printf("div_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_uint64_18446744073709551615_ssa(0); got != 0 { - fmt.Printf("div_uint64 0%s18446744073709551615 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_18446744073709551615_uint64_ssa(1); got != 18446744073709551615 { - fmt.Printf("div_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `/`, got) - failed = true - } - - if got := div_uint64_18446744073709551615_ssa(1); got != 0 { - fmt.Printf("div_uint64 1%s18446744073709551615 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_18446744073709551615_uint64_ssa(4294967296); got != 4294967295 { - fmt.Printf("div_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `/`, got) - failed = true - } - - if got := div_uint64_18446744073709551615_ssa(4294967296); got != 0 { - fmt.Printf("div_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_18446744073709551615_uint64_ssa(9223372036854775808); got != 1 { - fmt.Printf("div_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_uint64_18446744073709551615_ssa(9223372036854775808); got != 0 { - fmt.Printf("div_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_18446744073709551615_uint64_ssa(18446744073709551615); got != 1 { - fmt.Printf("div_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_uint64_18446744073709551615_ssa(18446744073709551615); got != 1 { - fmt.Printf("div_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := mul_0_uint64_ssa(0); got != 0 { - fmt.Printf("mul_uint64 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint64_0_ssa(0); got != 0 { - fmt.Printf("mul_uint64 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_uint64_ssa(1); got != 0 { - fmt.Printf("mul_uint64 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint64_0_ssa(1); got != 0 { - fmt.Printf("mul_uint64 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_uint64_ssa(4294967296); got != 0 { - fmt.Printf("mul_uint64 0%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint64_0_ssa(4294967296); got != 0 { - fmt.Printf("mul_uint64 4294967296%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("mul_uint64 0%s9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint64_0_ssa(9223372036854775808); got != 0 { - fmt.Printf("mul_uint64 9223372036854775808%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("mul_uint64 0%s18446744073709551615 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint64_0_ssa(18446744073709551615); got != 0 { - fmt.Printf("mul_uint64 18446744073709551615%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_uint64_ssa(0); got != 0 { - fmt.Printf("mul_uint64 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint64_1_ssa(0); got != 0 { - fmt.Printf("mul_uint64 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_uint64_ssa(1); got != 1 { - fmt.Printf("mul_uint64 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_uint64_1_ssa(1); got != 1 { - fmt.Printf("mul_uint64 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_1_uint64_ssa(4294967296); got != 4294967296 { - fmt.Printf("mul_uint64 1%s4294967296 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_uint64_1_ssa(4294967296); got != 4294967296 { - fmt.Printf("mul_uint64 4294967296%s1 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_1_uint64_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("mul_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_uint64_1_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("mul_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_1_uint64_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("mul_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551615\n", `*`, got) - failed = true - } - - if got := mul_uint64_1_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("mul_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `*`, got) - failed = true - } - - if got := mul_4294967296_uint64_ssa(0); got != 0 { - fmt.Printf("mul_uint64 4294967296%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint64_4294967296_ssa(0); got != 0 { - fmt.Printf("mul_uint64 0%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_4294967296_uint64_ssa(1); got != 4294967296 { - fmt.Printf("mul_uint64 4294967296%s1 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_uint64_4294967296_ssa(1); got != 4294967296 { - fmt.Printf("mul_uint64 1%s4294967296 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_4294967296_uint64_ssa(4294967296); got != 0 { - fmt.Printf("mul_uint64 4294967296%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint64_4294967296_ssa(4294967296); got != 0 { - fmt.Printf("mul_uint64 4294967296%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_4294967296_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("mul_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint64_4294967296_ssa(9223372036854775808); got != 0 { - fmt.Printf("mul_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_4294967296_uint64_ssa(18446744073709551615); got != 18446744069414584320 { - fmt.Printf("mul_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744069414584320\n", `*`, got) - failed = true - } - - if got := mul_uint64_4294967296_ssa(18446744073709551615); got != 18446744069414584320 { - fmt.Printf("mul_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584320\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775808_uint64_ssa(0); got != 0 { - fmt.Printf("mul_uint64 9223372036854775808%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint64_9223372036854775808_ssa(0); got != 0 { - fmt.Printf("mul_uint64 0%s9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775808_uint64_ssa(1); got != 9223372036854775808 { - fmt.Printf("mul_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_uint64_9223372036854775808_ssa(1); got != 9223372036854775808 { - fmt.Printf("mul_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775808_uint64_ssa(4294967296); got != 0 { - fmt.Printf("mul_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint64_9223372036854775808_ssa(4294967296); got != 0 { - fmt.Printf("mul_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("mul_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { - fmt.Printf("mul_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775808 { - fmt.Printf("mul_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775808 { - fmt.Printf("mul_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_18446744073709551615_uint64_ssa(0); got != 0 { - fmt.Printf("mul_uint64 18446744073709551615%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint64_18446744073709551615_ssa(0); got != 0 { - fmt.Printf("mul_uint64 0%s18446744073709551615 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_18446744073709551615_uint64_ssa(1); got != 18446744073709551615 { - fmt.Printf("mul_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `*`, got) - failed = true - } - - if got := mul_uint64_18446744073709551615_ssa(1); got != 18446744073709551615 { - fmt.Printf("mul_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551615\n", `*`, got) - failed = true - } - - if got := mul_18446744073709551615_uint64_ssa(4294967296); got != 18446744069414584320 { - fmt.Printf("mul_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584320\n", `*`, got) - failed = true - } - - if got := mul_uint64_18446744073709551615_ssa(4294967296); got != 18446744069414584320 { - fmt.Printf("mul_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744069414584320\n", `*`, got) - failed = true - } - - if got := mul_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("mul_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("mul_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_18446744073709551615_uint64_ssa(18446744073709551615); got != 1 { - fmt.Printf("mul_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_uint64_18446744073709551615_ssa(18446744073709551615); got != 1 { - fmt.Printf("mul_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := lsh_0_uint64_ssa(0); got != 0 { - fmt.Printf("lsh_uint64 0%s0 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_0_ssa(0); got != 0 { - fmt.Printf("lsh_uint64 0%s0 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_0_uint64_ssa(1); got != 0 { - fmt.Printf("lsh_uint64 0%s1 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_0_ssa(1); got != 1 { - fmt.Printf("lsh_uint64 1%s0 = %d, wanted 1\n", `<<`, got) - failed = true - } - - if got := lsh_0_uint64_ssa(4294967296); got != 0 { - fmt.Printf("lsh_uint64 0%s4294967296 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_0_ssa(4294967296); got != 4294967296 { - fmt.Printf("lsh_uint64 4294967296%s0 = %d, wanted 4294967296\n", `<<`, got) - failed = true - } - - if got := lsh_0_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("lsh_uint64 0%s9223372036854775808 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("lsh_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `<<`, got) - failed = true - } - - if got := lsh_0_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("lsh_uint64 0%s18446744073709551615 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("lsh_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint64_ssa(0); got != 1 { - fmt.Printf("lsh_uint64 1%s0 = %d, wanted 1\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_1_ssa(0); got != 0 { - fmt.Printf("lsh_uint64 0%s1 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint64_ssa(1); got != 2 { - fmt.Printf("lsh_uint64 1%s1 = %d, wanted 2\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_1_ssa(1); got != 2 { - fmt.Printf("lsh_uint64 1%s1 = %d, wanted 2\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint64_ssa(4294967296); got != 0 { - fmt.Printf("lsh_uint64 1%s4294967296 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_1_ssa(4294967296); got != 8589934592 { - fmt.Printf("lsh_uint64 4294967296%s1 = %d, wanted 8589934592\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("lsh_uint64 1%s9223372036854775808 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_1_ssa(9223372036854775808); got != 0 { - fmt.Printf("lsh_uint64 9223372036854775808%s1 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("lsh_uint64 1%s18446744073709551615 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_1_ssa(18446744073709551615); got != 18446744073709551614 { - fmt.Printf("lsh_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `<<`, got) - failed = true - } - - if got := lsh_4294967296_uint64_ssa(0); got != 4294967296 { - fmt.Printf("lsh_uint64 4294967296%s0 = %d, wanted 4294967296\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_4294967296_ssa(0); got != 0 { - fmt.Printf("lsh_uint64 0%s4294967296 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_4294967296_uint64_ssa(1); got != 8589934592 { - fmt.Printf("lsh_uint64 4294967296%s1 = %d, wanted 8589934592\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_4294967296_ssa(1); got != 0 { - fmt.Printf("lsh_uint64 1%s4294967296 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_4294967296_uint64_ssa(4294967296); got != 0 { - fmt.Printf("lsh_uint64 4294967296%s4294967296 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_4294967296_ssa(4294967296); got != 0 { - fmt.Printf("lsh_uint64 4294967296%s4294967296 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_4294967296_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("lsh_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_4294967296_ssa(9223372036854775808); got != 0 { - fmt.Printf("lsh_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_4294967296_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("lsh_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_4294967296_ssa(18446744073709551615); got != 0 { - fmt.Printf("lsh_uint64 18446744073709551615%s4294967296 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { - fmt.Printf("lsh_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_9223372036854775808_ssa(0); got != 0 { - fmt.Printf("lsh_uint64 0%s9223372036854775808 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_9223372036854775808_uint64_ssa(1); got != 0 { - fmt.Printf("lsh_uint64 9223372036854775808%s1 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_9223372036854775808_ssa(1); got != 0 { - fmt.Printf("lsh_uint64 1%s9223372036854775808 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_9223372036854775808_uint64_ssa(4294967296); got != 0 { - fmt.Printf("lsh_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_9223372036854775808_ssa(4294967296); got != 0 { - fmt.Printf("lsh_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("lsh_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { - fmt.Printf("lsh_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_9223372036854775808_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("lsh_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_9223372036854775808_ssa(18446744073709551615); got != 0 { - fmt.Printf("lsh_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { - fmt.Printf("lsh_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_18446744073709551615_ssa(0); got != 0 { - fmt.Printf("lsh_uint64 0%s18446744073709551615 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_18446744073709551615_uint64_ssa(1); got != 18446744073709551614 { - fmt.Printf("lsh_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_18446744073709551615_ssa(1); got != 0 { - fmt.Printf("lsh_uint64 1%s18446744073709551615 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_18446744073709551615_uint64_ssa(4294967296); got != 0 { - fmt.Printf("lsh_uint64 18446744073709551615%s4294967296 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_18446744073709551615_ssa(4294967296); got != 0 { - fmt.Printf("lsh_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_18446744073709551615_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("lsh_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_18446744073709551615_ssa(9223372036854775808); got != 0 { - fmt.Printf("lsh_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("lsh_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { - fmt.Printf("lsh_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := rsh_0_uint64_ssa(0); got != 0 { - fmt.Printf("rsh_uint64 0%s0 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_0_ssa(0); got != 0 { - fmt.Printf("rsh_uint64 0%s0 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_0_uint64_ssa(1); got != 0 { - fmt.Printf("rsh_uint64 0%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_0_ssa(1); got != 1 { - fmt.Printf("rsh_uint64 1%s0 = %d, wanted 1\n", `>>`, got) - failed = true - } - - if got := rsh_0_uint64_ssa(4294967296); got != 0 { - fmt.Printf("rsh_uint64 0%s4294967296 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_0_ssa(4294967296); got != 4294967296 { - fmt.Printf("rsh_uint64 4294967296%s0 = %d, wanted 4294967296\n", `>>`, got) - failed = true - } - - if got := rsh_0_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("rsh_uint64 0%s9223372036854775808 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("rsh_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `>>`, got) - failed = true - } - - if got := rsh_0_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("rsh_uint64 0%s18446744073709551615 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("rsh_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint64_ssa(0); got != 1 { - fmt.Printf("rsh_uint64 1%s0 = %d, wanted 1\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_1_ssa(0); got != 0 { - fmt.Printf("rsh_uint64 0%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint64_ssa(1); got != 0 { - fmt.Printf("rsh_uint64 1%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_1_ssa(1); got != 0 { - fmt.Printf("rsh_uint64 1%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint64_ssa(4294967296); got != 0 { - fmt.Printf("rsh_uint64 1%s4294967296 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_1_ssa(4294967296); got != 2147483648 { - fmt.Printf("rsh_uint64 4294967296%s1 = %d, wanted 2147483648\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("rsh_uint64 1%s9223372036854775808 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_1_ssa(9223372036854775808); got != 4611686018427387904 { - fmt.Printf("rsh_uint64 9223372036854775808%s1 = %d, wanted 4611686018427387904\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("rsh_uint64 1%s18446744073709551615 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_1_ssa(18446744073709551615); got != 9223372036854775807 { - fmt.Printf("rsh_uint64 18446744073709551615%s1 = %d, wanted 9223372036854775807\n", `>>`, got) - failed = true - } - - if got := rsh_4294967296_uint64_ssa(0); got != 4294967296 { - fmt.Printf("rsh_uint64 4294967296%s0 = %d, wanted 4294967296\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_4294967296_ssa(0); got != 0 { - fmt.Printf("rsh_uint64 0%s4294967296 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_4294967296_uint64_ssa(1); got != 2147483648 { - fmt.Printf("rsh_uint64 4294967296%s1 = %d, wanted 2147483648\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_4294967296_ssa(1); got != 0 { - fmt.Printf("rsh_uint64 1%s4294967296 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_4294967296_uint64_ssa(4294967296); got != 0 { - fmt.Printf("rsh_uint64 4294967296%s4294967296 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_4294967296_ssa(4294967296); got != 0 { - fmt.Printf("rsh_uint64 4294967296%s4294967296 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_4294967296_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("rsh_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_4294967296_ssa(9223372036854775808); got != 0 { - fmt.Printf("rsh_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_4294967296_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("rsh_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_4294967296_ssa(18446744073709551615); got != 0 { - fmt.Printf("rsh_uint64 18446744073709551615%s4294967296 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { - fmt.Printf("rsh_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_9223372036854775808_ssa(0); got != 0 { - fmt.Printf("rsh_uint64 0%s9223372036854775808 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_9223372036854775808_uint64_ssa(1); got != 4611686018427387904 { - fmt.Printf("rsh_uint64 9223372036854775808%s1 = %d, wanted 4611686018427387904\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_9223372036854775808_ssa(1); got != 0 { - fmt.Printf("rsh_uint64 1%s9223372036854775808 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_9223372036854775808_uint64_ssa(4294967296); got != 0 { - fmt.Printf("rsh_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_9223372036854775808_ssa(4294967296); got != 0 { - fmt.Printf("rsh_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("rsh_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { - fmt.Printf("rsh_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_9223372036854775808_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("rsh_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_9223372036854775808_ssa(18446744073709551615); got != 0 { - fmt.Printf("rsh_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { - fmt.Printf("rsh_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_18446744073709551615_ssa(0); got != 0 { - fmt.Printf("rsh_uint64 0%s18446744073709551615 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_18446744073709551615_uint64_ssa(1); got != 9223372036854775807 { - fmt.Printf("rsh_uint64 18446744073709551615%s1 = %d, wanted 9223372036854775807\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_18446744073709551615_ssa(1); got != 0 { - fmt.Printf("rsh_uint64 1%s18446744073709551615 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_18446744073709551615_uint64_ssa(4294967296); got != 0 { - fmt.Printf("rsh_uint64 18446744073709551615%s4294967296 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_18446744073709551615_ssa(4294967296); got != 0 { - fmt.Printf("rsh_uint64 4294967296%s18446744073709551615 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_18446744073709551615_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("rsh_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_18446744073709551615_ssa(9223372036854775808); got != 0 { - fmt.Printf("rsh_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("rsh_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { - fmt.Printf("rsh_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := mod_0_uint64_ssa(1); got != 0 { - fmt.Printf("mod_uint64 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_uint64_ssa(4294967296); got != 0 { - fmt.Printf("mod_uint64 0%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("mod_uint64 0%s9223372036854775808 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("mod_uint64 0%s18446744073709551615 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint64_1_ssa(0); got != 0 { - fmt.Printf("mod_uint64 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_uint64_ssa(1); got != 0 { - fmt.Printf("mod_uint64 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint64_1_ssa(1); got != 0 { - fmt.Printf("mod_uint64 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_uint64_ssa(4294967296); got != 1 { - fmt.Printf("mod_uint64 1%s4294967296 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_uint64_1_ssa(4294967296); got != 0 { - fmt.Printf("mod_uint64 4294967296%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_uint64_ssa(9223372036854775808); got != 1 { - fmt.Printf("mod_uint64 1%s9223372036854775808 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_uint64_1_ssa(9223372036854775808); got != 0 { - fmt.Printf("mod_uint64 9223372036854775808%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_uint64_ssa(18446744073709551615); got != 1 { - fmt.Printf("mod_uint64 1%s18446744073709551615 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_uint64_1_ssa(18446744073709551615); got != 0 { - fmt.Printf("mod_uint64 18446744073709551615%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint64_4294967296_ssa(0); got != 0 { - fmt.Printf("mod_uint64 0%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_4294967296_uint64_ssa(1); got != 0 { - fmt.Printf("mod_uint64 4294967296%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint64_4294967296_ssa(1); got != 1 { - fmt.Printf("mod_uint64 1%s4294967296 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_4294967296_uint64_ssa(4294967296); got != 0 { - fmt.Printf("mod_uint64 4294967296%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint64_4294967296_ssa(4294967296); got != 0 { - fmt.Printf("mod_uint64 4294967296%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_4294967296_uint64_ssa(9223372036854775808); got != 4294967296 { - fmt.Printf("mod_uint64 4294967296%s9223372036854775808 = %d, wanted 4294967296\n", `%`, got) - failed = true - } - - if got := mod_uint64_4294967296_ssa(9223372036854775808); got != 0 { - fmt.Printf("mod_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_4294967296_uint64_ssa(18446744073709551615); got != 4294967296 { - fmt.Printf("mod_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967296\n", `%`, got) - failed = true - } - - if got := mod_uint64_4294967296_ssa(18446744073709551615); got != 4294967295 { - fmt.Printf("mod_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `%`, got) - failed = true - } - - if got := mod_uint64_9223372036854775808_ssa(0); got != 0 { - fmt.Printf("mod_uint64 0%s9223372036854775808 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775808_uint64_ssa(1); got != 0 { - fmt.Printf("mod_uint64 9223372036854775808%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint64_9223372036854775808_ssa(1); got != 1 { - fmt.Printf("mod_uint64 1%s9223372036854775808 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775808_uint64_ssa(4294967296); got != 0 { - fmt.Printf("mod_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint64_9223372036854775808_ssa(4294967296); got != 4294967296 { - fmt.Printf("mod_uint64 4294967296%s9223372036854775808 = %d, wanted 4294967296\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("mod_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { - fmt.Printf("mod_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775808 { - fmt.Printf("mod_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `%`, got) - failed = true - } - - if got := mod_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775807 { - fmt.Printf("mod_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `%`, got) - failed = true - } - - if got := mod_uint64_18446744073709551615_ssa(0); got != 0 { - fmt.Printf("mod_uint64 0%s18446744073709551615 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_18446744073709551615_uint64_ssa(1); got != 0 { - fmt.Printf("mod_uint64 18446744073709551615%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint64_18446744073709551615_ssa(1); got != 1 { - fmt.Printf("mod_uint64 1%s18446744073709551615 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_18446744073709551615_uint64_ssa(4294967296); got != 4294967295 { - fmt.Printf("mod_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967295\n", `%`, got) - failed = true - } - - if got := mod_uint64_18446744073709551615_ssa(4294967296); got != 4294967296 { - fmt.Printf("mod_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967296\n", `%`, got) - failed = true - } - - if got := mod_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775807 { - fmt.Printf("mod_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `%`, got) - failed = true - } - - if got := mod_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("mod_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `%`, got) - failed = true - } - - if got := mod_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("mod_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { - fmt.Printf("mod_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := and_0_uint64_ssa(0); got != 0 { - fmt.Printf("and_uint64 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_0_ssa(0); got != 0 { - fmt.Printf("and_uint64 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_uint64_ssa(1); got != 0 { - fmt.Printf("and_uint64 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_0_ssa(1); got != 0 { - fmt.Printf("and_uint64 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_uint64_ssa(4294967296); got != 0 { - fmt.Printf("and_uint64 0%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_0_ssa(4294967296); got != 0 { - fmt.Printf("and_uint64 4294967296%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("and_uint64 0%s9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_0_ssa(9223372036854775808); got != 0 { - fmt.Printf("and_uint64 9223372036854775808%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("and_uint64 0%s18446744073709551615 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_0_ssa(18446744073709551615); got != 0 { - fmt.Printf("and_uint64 18446744073709551615%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_uint64_ssa(0); got != 0 { - fmt.Printf("and_uint64 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_1_ssa(0); got != 0 { - fmt.Printf("and_uint64 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_uint64_ssa(1); got != 1 { - fmt.Printf("and_uint64 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_uint64_1_ssa(1); got != 1 { - fmt.Printf("and_uint64 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_uint64_ssa(4294967296); got != 0 { - fmt.Printf("and_uint64 1%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_1_ssa(4294967296); got != 0 { - fmt.Printf("and_uint64 4294967296%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("and_uint64 1%s9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_1_ssa(9223372036854775808); got != 0 { - fmt.Printf("and_uint64 9223372036854775808%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_uint64_ssa(18446744073709551615); got != 1 { - fmt.Printf("and_uint64 1%s18446744073709551615 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_uint64_1_ssa(18446744073709551615); got != 1 { - fmt.Printf("and_uint64 18446744073709551615%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_4294967296_uint64_ssa(0); got != 0 { - fmt.Printf("and_uint64 4294967296%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_4294967296_ssa(0); got != 0 { - fmt.Printf("and_uint64 0%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_4294967296_uint64_ssa(1); got != 0 { - fmt.Printf("and_uint64 4294967296%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_4294967296_ssa(1); got != 0 { - fmt.Printf("and_uint64 1%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_4294967296_uint64_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_uint64 4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_uint64_4294967296_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_uint64 4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_4294967296_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("and_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_4294967296_ssa(9223372036854775808); got != 0 { - fmt.Printf("and_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_4294967296_uint64_ssa(18446744073709551615); got != 4294967296 { - fmt.Printf("and_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_uint64_4294967296_ssa(18446744073709551615); got != 4294967296 { - fmt.Printf("and_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_9223372036854775808_uint64_ssa(0); got != 0 { - fmt.Printf("and_uint64 9223372036854775808%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_9223372036854775808_ssa(0); got != 0 { - fmt.Printf("and_uint64 0%s9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_9223372036854775808_uint64_ssa(1); got != 0 { - fmt.Printf("and_uint64 9223372036854775808%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_9223372036854775808_ssa(1); got != 0 { - fmt.Printf("and_uint64 1%s9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_9223372036854775808_uint64_ssa(4294967296); got != 0 { - fmt.Printf("and_uint64 9223372036854775808%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_9223372036854775808_ssa(4294967296); got != 0 { - fmt.Printf("and_uint64 4294967296%s9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_9223372036854775808_uint64_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("and_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_uint64_9223372036854775808_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("and_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775808 { - fmt.Printf("and_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775808 { - fmt.Printf("and_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_18446744073709551615_uint64_ssa(0); got != 0 { - fmt.Printf("and_uint64 18446744073709551615%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint64_18446744073709551615_ssa(0); got != 0 { - fmt.Printf("and_uint64 0%s18446744073709551615 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_18446744073709551615_uint64_ssa(1); got != 1 { - fmt.Printf("and_uint64 18446744073709551615%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_uint64_18446744073709551615_ssa(1); got != 1 { - fmt.Printf("and_uint64 1%s18446744073709551615 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_18446744073709551615_uint64_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_uint64 18446744073709551615%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_uint64_18446744073709551615_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_uint64 4294967296%s18446744073709551615 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("and_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("and_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_18446744073709551615_uint64_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("and_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551615\n", `&`, got) - failed = true - } - - if got := and_uint64_18446744073709551615_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("and_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551615\n", `&`, got) - failed = true - } - - if got := or_0_uint64_ssa(0); got != 0 { - fmt.Printf("or_uint64 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_uint64_0_ssa(0); got != 0 { - fmt.Printf("or_uint64 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_0_uint64_ssa(1); got != 1 { - fmt.Printf("or_uint64 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_uint64_0_ssa(1); got != 1 { - fmt.Printf("or_uint64 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_0_uint64_ssa(4294967296); got != 4294967296 { - fmt.Printf("or_uint64 0%s4294967296 = %d, wanted 4294967296\n", `|`, got) - failed = true - } - - if got := or_uint64_0_ssa(4294967296); got != 4294967296 { - fmt.Printf("or_uint64 4294967296%s0 = %d, wanted 4294967296\n", `|`, got) - failed = true - } - - if got := or_0_uint64_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("or_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `|`, got) - failed = true - } - - if got := or_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("or_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `|`, got) - failed = true - } - - if got := or_0_uint64_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("or_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("or_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_1_uint64_ssa(0); got != 1 { - fmt.Printf("or_uint64 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_uint64_1_ssa(0); got != 1 { - fmt.Printf("or_uint64 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_uint64_ssa(1); got != 1 { - fmt.Printf("or_uint64 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_uint64_1_ssa(1); got != 1 { - fmt.Printf("or_uint64 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_uint64_ssa(4294967296); got != 4294967297 { - fmt.Printf("or_uint64 1%s4294967296 = %d, wanted 4294967297\n", `|`, got) - failed = true - } - - if got := or_uint64_1_ssa(4294967296); got != 4294967297 { - fmt.Printf("or_uint64 4294967296%s1 = %d, wanted 4294967297\n", `|`, got) - failed = true - } - - if got := or_1_uint64_ssa(9223372036854775808); got != 9223372036854775809 { - fmt.Printf("or_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `|`, got) - failed = true - } - - if got := or_uint64_1_ssa(9223372036854775808); got != 9223372036854775809 { - fmt.Printf("or_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `|`, got) - failed = true - } - - if got := or_1_uint64_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("or_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_uint64_1_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("or_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_4294967296_uint64_ssa(0); got != 4294967296 { - fmt.Printf("or_uint64 4294967296%s0 = %d, wanted 4294967296\n", `|`, got) - failed = true - } - - if got := or_uint64_4294967296_ssa(0); got != 4294967296 { - fmt.Printf("or_uint64 0%s4294967296 = %d, wanted 4294967296\n", `|`, got) - failed = true - } - - if got := or_4294967296_uint64_ssa(1); got != 4294967297 { - fmt.Printf("or_uint64 4294967296%s1 = %d, wanted 4294967297\n", `|`, got) - failed = true - } - - if got := or_uint64_4294967296_ssa(1); got != 4294967297 { - fmt.Printf("or_uint64 1%s4294967296 = %d, wanted 4294967297\n", `|`, got) - failed = true - } - - if got := or_4294967296_uint64_ssa(4294967296); got != 4294967296 { - fmt.Printf("or_uint64 4294967296%s4294967296 = %d, wanted 4294967296\n", `|`, got) - failed = true - } - - if got := or_uint64_4294967296_ssa(4294967296); got != 4294967296 { - fmt.Printf("or_uint64 4294967296%s4294967296 = %d, wanted 4294967296\n", `|`, got) - failed = true - } - - if got := or_4294967296_uint64_ssa(9223372036854775808); got != 9223372041149743104 { - fmt.Printf("or_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `|`, got) - failed = true - } - - if got := or_uint64_4294967296_ssa(9223372036854775808); got != 9223372041149743104 { - fmt.Printf("or_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `|`, got) - failed = true - } - - if got := or_4294967296_uint64_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("or_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_uint64_4294967296_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("or_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { - fmt.Printf("or_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `|`, got) - failed = true - } - - if got := or_uint64_9223372036854775808_ssa(0); got != 9223372036854775808 { - fmt.Printf("or_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `|`, got) - failed = true - } - - if got := or_9223372036854775808_uint64_ssa(1); got != 9223372036854775809 { - fmt.Printf("or_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `|`, got) - failed = true - } - - if got := or_uint64_9223372036854775808_ssa(1); got != 9223372036854775809 { - fmt.Printf("or_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `|`, got) - failed = true - } - - if got := or_9223372036854775808_uint64_ssa(4294967296); got != 9223372041149743104 { - fmt.Printf("or_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `|`, got) - failed = true - } - - if got := or_uint64_9223372036854775808_ssa(4294967296); got != 9223372041149743104 { - fmt.Printf("or_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `|`, got) - failed = true - } - - if got := or_9223372036854775808_uint64_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("or_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 9223372036854775808\n", `|`, got) - failed = true - } - - if got := or_uint64_9223372036854775808_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("or_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 9223372036854775808\n", `|`, got) - failed = true - } - - if got := or_9223372036854775808_uint64_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("or_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_uint64_9223372036854775808_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("or_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { - fmt.Printf("or_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_uint64_18446744073709551615_ssa(0); got != 18446744073709551615 { - fmt.Printf("or_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_18446744073709551615_uint64_ssa(1); got != 18446744073709551615 { - fmt.Printf("or_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_uint64_18446744073709551615_ssa(1); got != 18446744073709551615 { - fmt.Printf("or_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_18446744073709551615_uint64_ssa(4294967296); got != 18446744073709551615 { - fmt.Printf("or_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_uint64_18446744073709551615_ssa(4294967296); got != 18446744073709551615 { - fmt.Printf("or_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_18446744073709551615_uint64_ssa(9223372036854775808); got != 18446744073709551615 { - fmt.Printf("or_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_uint64_18446744073709551615_ssa(9223372036854775808); got != 18446744073709551615 { - fmt.Printf("or_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_18446744073709551615_uint64_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("or_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := or_uint64_18446744073709551615_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("or_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 18446744073709551615\n", `|`, got) - failed = true - } - - if got := xor_0_uint64_ssa(0); got != 0 { - fmt.Printf("xor_uint64 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint64_0_ssa(0); got != 0 { - fmt.Printf("xor_uint64 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_0_uint64_ssa(1); got != 1 { - fmt.Printf("xor_uint64 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_uint64_0_ssa(1); got != 1 { - fmt.Printf("xor_uint64 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_0_uint64_ssa(4294967296); got != 4294967296 { - fmt.Printf("xor_uint64 0%s4294967296 = %d, wanted 4294967296\n", `^`, got) - failed = true - } - - if got := xor_uint64_0_ssa(4294967296); got != 4294967296 { - fmt.Printf("xor_uint64 4294967296%s0 = %d, wanted 4294967296\n", `^`, got) - failed = true - } - - if got := xor_0_uint64_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("xor_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_uint64_0_ssa(9223372036854775808); got != 9223372036854775808 { - fmt.Printf("xor_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_0_uint64_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("xor_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `^`, got) - failed = true - } - - if got := xor_uint64_0_ssa(18446744073709551615); got != 18446744073709551615 { - fmt.Printf("xor_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `^`, got) - failed = true - } - - if got := xor_1_uint64_ssa(0); got != 1 { - fmt.Printf("xor_uint64 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_uint64_1_ssa(0); got != 1 { - fmt.Printf("xor_uint64 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_1_uint64_ssa(1); got != 0 { - fmt.Printf("xor_uint64 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint64_1_ssa(1); got != 0 { - fmt.Printf("xor_uint64 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_1_uint64_ssa(4294967296); got != 4294967297 { - fmt.Printf("xor_uint64 1%s4294967296 = %d, wanted 4294967297\n", `^`, got) - failed = true - } - - if got := xor_uint64_1_ssa(4294967296); got != 4294967297 { - fmt.Printf("xor_uint64 4294967296%s1 = %d, wanted 4294967297\n", `^`, got) - failed = true - } - - if got := xor_1_uint64_ssa(9223372036854775808); got != 9223372036854775809 { - fmt.Printf("xor_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `^`, got) - failed = true - } - - if got := xor_uint64_1_ssa(9223372036854775808); got != 9223372036854775809 { - fmt.Printf("xor_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `^`, got) - failed = true - } - - if got := xor_1_uint64_ssa(18446744073709551615); got != 18446744073709551614 { - fmt.Printf("xor_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551614\n", `^`, got) - failed = true - } - - if got := xor_uint64_1_ssa(18446744073709551615); got != 18446744073709551614 { - fmt.Printf("xor_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `^`, got) - failed = true - } - - if got := xor_4294967296_uint64_ssa(0); got != 4294967296 { - fmt.Printf("xor_uint64 4294967296%s0 = %d, wanted 4294967296\n", `^`, got) - failed = true - } - - if got := xor_uint64_4294967296_ssa(0); got != 4294967296 { - fmt.Printf("xor_uint64 0%s4294967296 = %d, wanted 4294967296\n", `^`, got) - failed = true - } - - if got := xor_4294967296_uint64_ssa(1); got != 4294967297 { - fmt.Printf("xor_uint64 4294967296%s1 = %d, wanted 4294967297\n", `^`, got) - failed = true - } - - if got := xor_uint64_4294967296_ssa(1); got != 4294967297 { - fmt.Printf("xor_uint64 1%s4294967296 = %d, wanted 4294967297\n", `^`, got) - failed = true - } - - if got := xor_4294967296_uint64_ssa(4294967296); got != 0 { - fmt.Printf("xor_uint64 4294967296%s4294967296 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint64_4294967296_ssa(4294967296); got != 0 { - fmt.Printf("xor_uint64 4294967296%s4294967296 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_4294967296_uint64_ssa(9223372036854775808); got != 9223372041149743104 { - fmt.Printf("xor_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `^`, got) - failed = true - } - - if got := xor_uint64_4294967296_ssa(9223372036854775808); got != 9223372041149743104 { - fmt.Printf("xor_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `^`, got) - failed = true - } - - if got := xor_4294967296_uint64_ssa(18446744073709551615); got != 18446744069414584319 { - fmt.Printf("xor_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744069414584319\n", `^`, got) - failed = true - } - - if got := xor_uint64_4294967296_ssa(18446744073709551615); got != 18446744069414584319 { - fmt.Printf("xor_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584319\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775808_uint64_ssa(0); got != 9223372036854775808 { - fmt.Printf("xor_uint64 9223372036854775808%s0 = %d, wanted 9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_uint64_9223372036854775808_ssa(0); got != 9223372036854775808 { - fmt.Printf("xor_uint64 0%s9223372036854775808 = %d, wanted 9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775808_uint64_ssa(1); got != 9223372036854775809 { - fmt.Printf("xor_uint64 9223372036854775808%s1 = %d, wanted 9223372036854775809\n", `^`, got) - failed = true - } - - if got := xor_uint64_9223372036854775808_ssa(1); got != 9223372036854775809 { - fmt.Printf("xor_uint64 1%s9223372036854775808 = %d, wanted 9223372036854775809\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775808_uint64_ssa(4294967296); got != 9223372041149743104 { - fmt.Printf("xor_uint64 9223372036854775808%s4294967296 = %d, wanted 9223372041149743104\n", `^`, got) - failed = true - } - - if got := xor_uint64_9223372036854775808_ssa(4294967296); got != 9223372041149743104 { - fmt.Printf("xor_uint64 4294967296%s9223372036854775808 = %d, wanted 9223372041149743104\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775808_uint64_ssa(9223372036854775808); got != 0 { - fmt.Printf("xor_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint64_9223372036854775808_ssa(9223372036854775808); got != 0 { - fmt.Printf("xor_uint64 9223372036854775808%s9223372036854775808 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775808_uint64_ssa(18446744073709551615); got != 9223372036854775807 { - fmt.Printf("xor_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_uint64_9223372036854775808_ssa(18446744073709551615); got != 9223372036854775807 { - fmt.Printf("xor_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_18446744073709551615_uint64_ssa(0); got != 18446744073709551615 { - fmt.Printf("xor_uint64 18446744073709551615%s0 = %d, wanted 18446744073709551615\n", `^`, got) - failed = true - } - - if got := xor_uint64_18446744073709551615_ssa(0); got != 18446744073709551615 { - fmt.Printf("xor_uint64 0%s18446744073709551615 = %d, wanted 18446744073709551615\n", `^`, got) - failed = true - } - - if got := xor_18446744073709551615_uint64_ssa(1); got != 18446744073709551614 { - fmt.Printf("xor_uint64 18446744073709551615%s1 = %d, wanted 18446744073709551614\n", `^`, got) - failed = true - } - - if got := xor_uint64_18446744073709551615_ssa(1); got != 18446744073709551614 { - fmt.Printf("xor_uint64 1%s18446744073709551615 = %d, wanted 18446744073709551614\n", `^`, got) - failed = true - } - - if got := xor_18446744073709551615_uint64_ssa(4294967296); got != 18446744069414584319 { - fmt.Printf("xor_uint64 18446744073709551615%s4294967296 = %d, wanted 18446744069414584319\n", `^`, got) - failed = true - } - - if got := xor_uint64_18446744073709551615_ssa(4294967296); got != 18446744069414584319 { - fmt.Printf("xor_uint64 4294967296%s18446744073709551615 = %d, wanted 18446744069414584319\n", `^`, got) - failed = true - } - - if got := xor_18446744073709551615_uint64_ssa(9223372036854775808); got != 9223372036854775807 { - fmt.Printf("xor_uint64 18446744073709551615%s9223372036854775808 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_uint64_18446744073709551615_ssa(9223372036854775808); got != 9223372036854775807 { - fmt.Printf("xor_uint64 9223372036854775808%s18446744073709551615 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_18446744073709551615_uint64_ssa(18446744073709551615); got != 0 { - fmt.Printf("xor_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint64_18446744073709551615_ssa(18446744073709551615); got != 0 { - fmt.Printf("xor_uint64 18446744073709551615%s18446744073709551615 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := add_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("add_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { - fmt.Printf("add_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != 1 { - fmt.Printf("add_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != 1 { - fmt.Printf("add_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775808_int64_ssa(-4294967296); got != 9223372032559808512 { - fmt.Printf("add_int64 -9223372036854775808%s-4294967296 = %d, wanted 9223372032559808512\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775808_ssa(-4294967296); got != 9223372032559808512 { - fmt.Printf("add_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775808_int64_ssa(-1); got != 9223372036854775807 { - fmt.Printf("add_int64 -9223372036854775808%s-1 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775808_ssa(-1); got != 9223372036854775807 { - fmt.Printf("add_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775808_int64_ssa(0); got != -9223372036854775808 { - fmt.Printf("add_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775808_ssa(0); got != -9223372036854775808 { - fmt.Printf("add_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775807 { - fmt.Printf("add_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775807 { - fmt.Printf("add_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775808_int64_ssa(4294967296); got != -9223372032559808512 { - fmt.Printf("add_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775808_ssa(4294967296); got != -9223372032559808512 { - fmt.Printf("add_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -2 { - fmt.Printf("add_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775808_ssa(9223372036854775806); got != -2 { - fmt.Printf("add_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { - fmt.Printf("add_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -1 { - fmt.Printf("add_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != 1 { - fmt.Printf("add_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != 1 { - fmt.Printf("add_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 2 { - fmt.Printf("add_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 2 { - fmt.Printf("add_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775807_int64_ssa(-4294967296); got != 9223372032559808513 { - fmt.Printf("add_int64 -9223372036854775807%s-4294967296 = %d, wanted 9223372032559808513\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775807_ssa(-4294967296); got != 9223372032559808513 { - fmt.Printf("add_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808513\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775807_int64_ssa(-1); got != -9223372036854775808 { - fmt.Printf("add_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775807_ssa(-1); got != -9223372036854775808 { - fmt.Printf("add_int64 -1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775807_int64_ssa(0); got != -9223372036854775807 { - fmt.Printf("add_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775807_ssa(0); got != -9223372036854775807 { - fmt.Printf("add_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775806 { - fmt.Printf("add_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775806\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775806 { - fmt.Printf("add_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775806\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775807_int64_ssa(4294967296); got != -9223372032559808511 { - fmt.Printf("add_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775807_ssa(4294967296); got != -9223372032559808511 { - fmt.Printf("add_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { - fmt.Printf("add_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775807_ssa(9223372036854775806); got != -1 { - fmt.Printf("add_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_Neg9223372036854775807_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("add_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int64_Neg9223372036854775807_ssa(9223372036854775807); got != 0 { - fmt.Printf("add_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_Neg4294967296_int64_ssa(-9223372036854775808); got != 9223372032559808512 { - fmt.Printf("add_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `+`, got) - failed = true - } - - if got := add_int64_Neg4294967296_ssa(-9223372036854775808); got != 9223372032559808512 { - fmt.Printf("add_int64 -9223372036854775808%s-4294967296 = %d, wanted 9223372032559808512\n", `+`, got) - failed = true - } - - if got := add_Neg4294967296_int64_ssa(-9223372036854775807); got != 9223372032559808513 { - fmt.Printf("add_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808513\n", `+`, got) - failed = true - } - - if got := add_int64_Neg4294967296_ssa(-9223372036854775807); got != 9223372032559808513 { - fmt.Printf("add_int64 -9223372036854775807%s-4294967296 = %d, wanted 9223372032559808513\n", `+`, got) - failed = true - } - - if got := add_Neg4294967296_int64_ssa(-4294967296); got != -8589934592 { - fmt.Printf("add_int64 -4294967296%s-4294967296 = %d, wanted -8589934592\n", `+`, got) - failed = true - } - - if got := add_int64_Neg4294967296_ssa(-4294967296); got != -8589934592 { - fmt.Printf("add_int64 -4294967296%s-4294967296 = %d, wanted -8589934592\n", `+`, got) - failed = true - } - - if got := add_Neg4294967296_int64_ssa(-1); got != -4294967297 { - fmt.Printf("add_int64 -4294967296%s-1 = %d, wanted -4294967297\n", `+`, got) - failed = true - } - - if got := add_int64_Neg4294967296_ssa(-1); got != -4294967297 { - fmt.Printf("add_int64 -1%s-4294967296 = %d, wanted -4294967297\n", `+`, got) - failed = true - } - - if got := add_Neg4294967296_int64_ssa(0); got != -4294967296 { - fmt.Printf("add_int64 -4294967296%s0 = %d, wanted -4294967296\n", `+`, got) - failed = true - } - - if got := add_int64_Neg4294967296_ssa(0); got != -4294967296 { - fmt.Printf("add_int64 0%s-4294967296 = %d, wanted -4294967296\n", `+`, got) - failed = true - } - - if got := add_Neg4294967296_int64_ssa(1); got != -4294967295 { - fmt.Printf("add_int64 -4294967296%s1 = %d, wanted -4294967295\n", `+`, got) - failed = true - } - - if got := add_int64_Neg4294967296_ssa(1); got != -4294967295 { - fmt.Printf("add_int64 1%s-4294967296 = %d, wanted -4294967295\n", `+`, got) - failed = true - } - - if got := add_Neg4294967296_int64_ssa(4294967296); got != 0 { - fmt.Printf("add_int64 -4294967296%s4294967296 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int64_Neg4294967296_ssa(4294967296); got != 0 { - fmt.Printf("add_int64 4294967296%s-4294967296 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_Neg4294967296_int64_ssa(9223372036854775806); got != 9223372032559808510 { - fmt.Printf("add_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808510\n", `+`, got) - failed = true - } - - if got := add_int64_Neg4294967296_ssa(9223372036854775806); got != 9223372032559808510 { - fmt.Printf("add_int64 9223372036854775806%s-4294967296 = %d, wanted 9223372032559808510\n", `+`, got) - failed = true - } - - if got := add_Neg4294967296_int64_ssa(9223372036854775807); got != 9223372032559808511 { - fmt.Printf("add_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808511\n", `+`, got) - failed = true - } - - if got := add_int64_Neg4294967296_ssa(9223372036854775807); got != 9223372032559808511 { - fmt.Printf("add_int64 9223372036854775807%s-4294967296 = %d, wanted 9223372032559808511\n", `+`, got) - failed = true - } - - if got := add_Neg1_int64_ssa(-9223372036854775808); got != 9223372036854775807 { - fmt.Printf("add_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_int64_Neg1_ssa(-9223372036854775808); got != 9223372036854775807 { - fmt.Printf("add_int64 -9223372036854775808%s-1 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_Neg1_int64_ssa(-9223372036854775807); got != -9223372036854775808 { - fmt.Printf("add_int64 -1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_int64_Neg1_ssa(-9223372036854775807); got != -9223372036854775808 { - fmt.Printf("add_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_Neg1_int64_ssa(-4294967296); got != -4294967297 { - fmt.Printf("add_int64 -1%s-4294967296 = %d, wanted -4294967297\n", `+`, got) - failed = true - } - - if got := add_int64_Neg1_ssa(-4294967296); got != -4294967297 { - fmt.Printf("add_int64 -4294967296%s-1 = %d, wanted -4294967297\n", `+`, got) - failed = true - } - - if got := add_Neg1_int64_ssa(-1); got != -2 { - fmt.Printf("add_int64 -1%s-1 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int64_Neg1_ssa(-1); got != -2 { - fmt.Printf("add_int64 -1%s-1 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_Neg1_int64_ssa(0); got != -1 { - fmt.Printf("add_int64 -1%s0 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int64_Neg1_ssa(0); got != -1 { - fmt.Printf("add_int64 0%s-1 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_Neg1_int64_ssa(1); got != 0 { - fmt.Printf("add_int64 -1%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int64_Neg1_ssa(1); got != 0 { - fmt.Printf("add_int64 1%s-1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_Neg1_int64_ssa(4294967296); got != 4294967295 { - fmt.Printf("add_int64 -1%s4294967296 = %d, wanted 4294967295\n", `+`, got) - failed = true - } - - if got := add_int64_Neg1_ssa(4294967296); got != 4294967295 { - fmt.Printf("add_int64 4294967296%s-1 = %d, wanted 4294967295\n", `+`, got) - failed = true - } - - if got := add_Neg1_int64_ssa(9223372036854775806); got != 9223372036854775805 { - fmt.Printf("add_int64 -1%s9223372036854775806 = %d, wanted 9223372036854775805\n", `+`, got) - failed = true - } - - if got := add_int64_Neg1_ssa(9223372036854775806); got != 9223372036854775805 { - fmt.Printf("add_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775805\n", `+`, got) - failed = true - } - - if got := add_Neg1_int64_ssa(9223372036854775807); got != 9223372036854775806 { - fmt.Printf("add_int64 -1%s9223372036854775807 = %d, wanted 9223372036854775806\n", `+`, got) - failed = true - } - - if got := add_int64_Neg1_ssa(9223372036854775807); got != 9223372036854775806 { - fmt.Printf("add_int64 9223372036854775807%s-1 = %d, wanted 9223372036854775806\n", `+`, got) - failed = true - } - - if got := add_0_int64_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("add_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_int64_0_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("add_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_0_int64_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("add_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_int64_0_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("add_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_0_int64_ssa(-4294967296); got != -4294967296 { - fmt.Printf("add_int64 0%s-4294967296 = %d, wanted -4294967296\n", `+`, got) - failed = true - } - - if got := add_int64_0_ssa(-4294967296); got != -4294967296 { - fmt.Printf("add_int64 -4294967296%s0 = %d, wanted -4294967296\n", `+`, got) - failed = true - } - - if got := add_0_int64_ssa(-1); got != -1 { - fmt.Printf("add_int64 0%s-1 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int64_0_ssa(-1); got != -1 { - fmt.Printf("add_int64 -1%s0 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_0_int64_ssa(0); got != 0 { - fmt.Printf("add_int64 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int64_0_ssa(0); got != 0 { - fmt.Printf("add_int64 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_0_int64_ssa(1); got != 1 { - fmt.Printf("add_int64 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int64_0_ssa(1); got != 1 { - fmt.Printf("add_int64 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_0_int64_ssa(4294967296); got != 4294967296 { - fmt.Printf("add_int64 0%s4294967296 = %d, wanted 4294967296\n", `+`, got) - failed = true - } - - if got := add_int64_0_ssa(4294967296); got != 4294967296 { - fmt.Printf("add_int64 4294967296%s0 = %d, wanted 4294967296\n", `+`, got) - failed = true - } - - if got := add_0_int64_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("add_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `+`, got) - failed = true - } - - if got := add_int64_0_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("add_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `+`, got) - failed = true - } - - if got := add_0_int64_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("add_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_int64_0_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("add_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_1_int64_ssa(-9223372036854775808); got != -9223372036854775807 { - fmt.Printf("add_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_int64_1_ssa(-9223372036854775808); got != -9223372036854775807 { - fmt.Printf("add_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_1_int64_ssa(-9223372036854775807); got != -9223372036854775806 { - fmt.Printf("add_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775806\n", `+`, got) - failed = true - } - - if got := add_int64_1_ssa(-9223372036854775807); got != -9223372036854775806 { - fmt.Printf("add_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775806\n", `+`, got) - failed = true - } - - if got := add_1_int64_ssa(-4294967296); got != -4294967295 { - fmt.Printf("add_int64 1%s-4294967296 = %d, wanted -4294967295\n", `+`, got) - failed = true - } - - if got := add_int64_1_ssa(-4294967296); got != -4294967295 { - fmt.Printf("add_int64 -4294967296%s1 = %d, wanted -4294967295\n", `+`, got) - failed = true - } - - if got := add_1_int64_ssa(-1); got != 0 { - fmt.Printf("add_int64 1%s-1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int64_1_ssa(-1); got != 0 { - fmt.Printf("add_int64 -1%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_1_int64_ssa(0); got != 1 { - fmt.Printf("add_int64 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int64_1_ssa(0); got != 1 { - fmt.Printf("add_int64 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_1_int64_ssa(1); got != 2 { - fmt.Printf("add_int64 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_int64_1_ssa(1); got != 2 { - fmt.Printf("add_int64 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_1_int64_ssa(4294967296); got != 4294967297 { - fmt.Printf("add_int64 1%s4294967296 = %d, wanted 4294967297\n", `+`, got) - failed = true - } - - if got := add_int64_1_ssa(4294967296); got != 4294967297 { - fmt.Printf("add_int64 4294967296%s1 = %d, wanted 4294967297\n", `+`, got) - failed = true - } - - if got := add_1_int64_ssa(9223372036854775806); got != 9223372036854775807 { - fmt.Printf("add_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_int64_1_ssa(9223372036854775806); got != 9223372036854775807 { - fmt.Printf("add_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_1_int64_ssa(9223372036854775807); got != -9223372036854775808 { - fmt.Printf("add_int64 1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_int64_1_ssa(9223372036854775807); got != -9223372036854775808 { - fmt.Printf("add_int64 9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_4294967296_int64_ssa(-9223372036854775808); got != -9223372032559808512 { - fmt.Printf("add_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `+`, got) - failed = true - } - - if got := add_int64_4294967296_ssa(-9223372036854775808); got != -9223372032559808512 { - fmt.Printf("add_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `+`, got) - failed = true - } - - if got := add_4294967296_int64_ssa(-9223372036854775807); got != -9223372032559808511 { - fmt.Printf("add_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `+`, got) - failed = true - } - - if got := add_int64_4294967296_ssa(-9223372036854775807); got != -9223372032559808511 { - fmt.Printf("add_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `+`, got) - failed = true - } - - if got := add_4294967296_int64_ssa(-4294967296); got != 0 { - fmt.Printf("add_int64 4294967296%s-4294967296 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int64_4294967296_ssa(-4294967296); got != 0 { - fmt.Printf("add_int64 -4294967296%s4294967296 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_4294967296_int64_ssa(-1); got != 4294967295 { - fmt.Printf("add_int64 4294967296%s-1 = %d, wanted 4294967295\n", `+`, got) - failed = true - } - - if got := add_int64_4294967296_ssa(-1); got != 4294967295 { - fmt.Printf("add_int64 -1%s4294967296 = %d, wanted 4294967295\n", `+`, got) - failed = true - } - - if got := add_4294967296_int64_ssa(0); got != 4294967296 { - fmt.Printf("add_int64 4294967296%s0 = %d, wanted 4294967296\n", `+`, got) - failed = true - } - - if got := add_int64_4294967296_ssa(0); got != 4294967296 { - fmt.Printf("add_int64 0%s4294967296 = %d, wanted 4294967296\n", `+`, got) - failed = true - } - - if got := add_4294967296_int64_ssa(1); got != 4294967297 { - fmt.Printf("add_int64 4294967296%s1 = %d, wanted 4294967297\n", `+`, got) - failed = true - } - - if got := add_int64_4294967296_ssa(1); got != 4294967297 { - fmt.Printf("add_int64 1%s4294967296 = %d, wanted 4294967297\n", `+`, got) - failed = true - } - - if got := add_4294967296_int64_ssa(4294967296); got != 8589934592 { - fmt.Printf("add_int64 4294967296%s4294967296 = %d, wanted 8589934592\n", `+`, got) - failed = true - } - - if got := add_int64_4294967296_ssa(4294967296); got != 8589934592 { - fmt.Printf("add_int64 4294967296%s4294967296 = %d, wanted 8589934592\n", `+`, got) - failed = true - } - - if got := add_4294967296_int64_ssa(9223372036854775806); got != -9223372032559808514 { - fmt.Printf("add_int64 4294967296%s9223372036854775806 = %d, wanted -9223372032559808514\n", `+`, got) - failed = true - } - - if got := add_int64_4294967296_ssa(9223372036854775806); got != -9223372032559808514 { - fmt.Printf("add_int64 9223372036854775806%s4294967296 = %d, wanted -9223372032559808514\n", `+`, got) - failed = true - } - - if got := add_4294967296_int64_ssa(9223372036854775807); got != -9223372032559808513 { - fmt.Printf("add_int64 4294967296%s9223372036854775807 = %d, wanted -9223372032559808513\n", `+`, got) - failed = true - } - - if got := add_int64_4294967296_ssa(9223372036854775807); got != -9223372032559808513 { - fmt.Printf("add_int64 9223372036854775807%s4294967296 = %d, wanted -9223372032559808513\n", `+`, got) - failed = true - } - - if got := add_9223372036854775806_int64_ssa(-9223372036854775808); got != -2 { - fmt.Printf("add_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775806_ssa(-9223372036854775808); got != -2 { - fmt.Printf("add_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_9223372036854775806_int64_ssa(-9223372036854775807); got != -1 { - fmt.Printf("add_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { - fmt.Printf("add_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_9223372036854775806_int64_ssa(-4294967296); got != 9223372032559808510 { - fmt.Printf("add_int64 9223372036854775806%s-4294967296 = %d, wanted 9223372032559808510\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775806_ssa(-4294967296); got != 9223372032559808510 { - fmt.Printf("add_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808510\n", `+`, got) - failed = true - } - - if got := add_9223372036854775806_int64_ssa(-1); got != 9223372036854775805 { - fmt.Printf("add_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775805\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775806_ssa(-1); got != 9223372036854775805 { - fmt.Printf("add_int64 -1%s9223372036854775806 = %d, wanted 9223372036854775805\n", `+`, got) - failed = true - } - - if got := add_9223372036854775806_int64_ssa(0); got != 9223372036854775806 { - fmt.Printf("add_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775806_ssa(0); got != 9223372036854775806 { - fmt.Printf("add_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `+`, got) - failed = true - } - - if got := add_9223372036854775806_int64_ssa(1); got != 9223372036854775807 { - fmt.Printf("add_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775806_ssa(1); got != 9223372036854775807 { - fmt.Printf("add_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_9223372036854775806_int64_ssa(4294967296); got != -9223372032559808514 { - fmt.Printf("add_int64 9223372036854775806%s4294967296 = %d, wanted -9223372032559808514\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775806_ssa(4294967296); got != -9223372032559808514 { - fmt.Printf("add_int64 4294967296%s9223372036854775806 = %d, wanted -9223372032559808514\n", `+`, got) - failed = true - } - - if got := add_9223372036854775806_int64_ssa(9223372036854775806); got != -4 { - fmt.Printf("add_int64 9223372036854775806%s9223372036854775806 = %d, wanted -4\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775806_ssa(9223372036854775806); got != -4 { - fmt.Printf("add_int64 9223372036854775806%s9223372036854775806 = %d, wanted -4\n", `+`, got) - failed = true - } - - if got := add_9223372036854775806_int64_ssa(9223372036854775807); got != -3 { - fmt.Printf("add_int64 9223372036854775806%s9223372036854775807 = %d, wanted -3\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775806_ssa(9223372036854775807); got != -3 { - fmt.Printf("add_int64 9223372036854775807%s9223372036854775806 = %d, wanted -3\n", `+`, got) - failed = true - } - - if got := add_9223372036854775807_int64_ssa(-9223372036854775808); got != -1 { - fmt.Printf("add_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { - fmt.Printf("add_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("add_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775807_ssa(-9223372036854775807); got != 0 { - fmt.Printf("add_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_9223372036854775807_int64_ssa(-4294967296); got != 9223372032559808511 { - fmt.Printf("add_int64 9223372036854775807%s-4294967296 = %d, wanted 9223372032559808511\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775807_ssa(-4294967296); got != 9223372032559808511 { - fmt.Printf("add_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808511\n", `+`, got) - failed = true - } - - if got := add_9223372036854775807_int64_ssa(-1); got != 9223372036854775806 { - fmt.Printf("add_int64 9223372036854775807%s-1 = %d, wanted 9223372036854775806\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775807_ssa(-1); got != 9223372036854775806 { - fmt.Printf("add_int64 -1%s9223372036854775807 = %d, wanted 9223372036854775806\n", `+`, got) - failed = true - } - - if got := add_9223372036854775807_int64_ssa(0); got != 9223372036854775807 { - fmt.Printf("add_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775807_ssa(0); got != 9223372036854775807 { - fmt.Printf("add_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `+`, got) - failed = true - } - - if got := add_9223372036854775807_int64_ssa(1); got != -9223372036854775808 { - fmt.Printf("add_int64 9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775807_ssa(1); got != -9223372036854775808 { - fmt.Printf("add_int64 1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `+`, got) - failed = true - } - - if got := add_9223372036854775807_int64_ssa(4294967296); got != -9223372032559808513 { - fmt.Printf("add_int64 9223372036854775807%s4294967296 = %d, wanted -9223372032559808513\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775807_ssa(4294967296); got != -9223372032559808513 { - fmt.Printf("add_int64 4294967296%s9223372036854775807 = %d, wanted -9223372032559808513\n", `+`, got) - failed = true - } - - if got := add_9223372036854775807_int64_ssa(9223372036854775806); got != -3 { - fmt.Printf("add_int64 9223372036854775807%s9223372036854775806 = %d, wanted -3\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775807_ssa(9223372036854775806); got != -3 { - fmt.Printf("add_int64 9223372036854775806%s9223372036854775807 = %d, wanted -3\n", `+`, got) - failed = true - } - - if got := add_9223372036854775807_int64_ssa(9223372036854775807); got != -2 { - fmt.Printf("add_int64 9223372036854775807%s9223372036854775807 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int64_9223372036854775807_ssa(9223372036854775807); got != -2 { - fmt.Printf("add_int64 9223372036854775807%s9223372036854775807 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := sub_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("sub_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { - fmt.Printf("sub_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -1 { - fmt.Printf("sub_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != 1 { - fmt.Printf("sub_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775808_int64_ssa(-4294967296); got != -9223372032559808512 { - fmt.Printf("sub_int64 -9223372036854775808%s-4294967296 = %d, wanted -9223372032559808512\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775808_ssa(-4294967296); got != 9223372032559808512 { - fmt.Printf("sub_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775808_int64_ssa(-1); got != -9223372036854775807 { - fmt.Printf("sub_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775808_ssa(-1); got != 9223372036854775807 { - fmt.Printf("sub_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775808_int64_ssa(0); got != -9223372036854775808 { - fmt.Printf("sub_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775808_ssa(0); got != -9223372036854775808 { - fmt.Printf("sub_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775808_int64_ssa(1); got != 9223372036854775807 { - fmt.Printf("sub_int64 -9223372036854775808%s1 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775807 { - fmt.Printf("sub_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775808_int64_ssa(4294967296); got != 9223372032559808512 { - fmt.Printf("sub_int64 -9223372036854775808%s4294967296 = %d, wanted 9223372032559808512\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775808_ssa(4294967296); got != -9223372032559808512 { - fmt.Printf("sub_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775808_int64_ssa(9223372036854775806); got != 2 { - fmt.Printf("sub_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775808_ssa(9223372036854775806); got != -2 { - fmt.Printf("sub_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775808_int64_ssa(9223372036854775807); got != 1 { - fmt.Printf("sub_int64 -9223372036854775808%s9223372036854775807 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -1 { - fmt.Printf("sub_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != 1 { - fmt.Printf("sub_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -1 { - fmt.Printf("sub_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("sub_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 0 { - fmt.Printf("sub_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775807_int64_ssa(-4294967296); got != -9223372032559808511 { - fmt.Printf("sub_int64 -9223372036854775807%s-4294967296 = %d, wanted -9223372032559808511\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775807_ssa(-4294967296); got != 9223372032559808511 { - fmt.Printf("sub_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808511\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775807_int64_ssa(-1); got != -9223372036854775806 { - fmt.Printf("sub_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775806\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775807_ssa(-1); got != 9223372036854775806 { - fmt.Printf("sub_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775807_int64_ssa(0); got != -9223372036854775807 { - fmt.Printf("sub_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775807_ssa(0); got != 9223372036854775807 { - fmt.Printf("sub_int64 0%s-9223372036854775807 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775808 { - fmt.Printf("sub_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775808 { - fmt.Printf("sub_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775807_int64_ssa(4294967296); got != 9223372032559808513 { - fmt.Printf("sub_int64 -9223372036854775807%s4294967296 = %d, wanted 9223372032559808513\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775807_ssa(4294967296); got != -9223372032559808513 { - fmt.Printf("sub_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808513\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775807_int64_ssa(9223372036854775806); got != 3 { - fmt.Printf("sub_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 3\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775807_ssa(9223372036854775806); got != -3 { - fmt.Printf("sub_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -3\n", `-`, got) - failed = true - } - - if got := sub_Neg9223372036854775807_int64_ssa(9223372036854775807); got != 2 { - fmt.Printf("sub_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -2 { - fmt.Printf("sub_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_Neg4294967296_int64_ssa(-9223372036854775808); got != 9223372032559808512 { - fmt.Printf("sub_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg4294967296_ssa(-9223372036854775808); got != -9223372032559808512 { - fmt.Printf("sub_int64 -9223372036854775808%s-4294967296 = %d, wanted -9223372032559808512\n", `-`, got) - failed = true - } - - if got := sub_Neg4294967296_int64_ssa(-9223372036854775807); got != 9223372032559808511 { - fmt.Printf("sub_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808511\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg4294967296_ssa(-9223372036854775807); got != -9223372032559808511 { - fmt.Printf("sub_int64 -9223372036854775807%s-4294967296 = %d, wanted -9223372032559808511\n", `-`, got) - failed = true - } - - if got := sub_Neg4294967296_int64_ssa(-4294967296); got != 0 { - fmt.Printf("sub_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg4294967296_ssa(-4294967296); got != 0 { - fmt.Printf("sub_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_Neg4294967296_int64_ssa(-1); got != -4294967295 { - fmt.Printf("sub_int64 -4294967296%s-1 = %d, wanted -4294967295\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg4294967296_ssa(-1); got != 4294967295 { - fmt.Printf("sub_int64 -1%s-4294967296 = %d, wanted 4294967295\n", `-`, got) - failed = true - } - - if got := sub_Neg4294967296_int64_ssa(0); got != -4294967296 { - fmt.Printf("sub_int64 -4294967296%s0 = %d, wanted -4294967296\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg4294967296_ssa(0); got != 4294967296 { - fmt.Printf("sub_int64 0%s-4294967296 = %d, wanted 4294967296\n", `-`, got) - failed = true - } - - if got := sub_Neg4294967296_int64_ssa(1); got != -4294967297 { - fmt.Printf("sub_int64 -4294967296%s1 = %d, wanted -4294967297\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg4294967296_ssa(1); got != 4294967297 { - fmt.Printf("sub_int64 1%s-4294967296 = %d, wanted 4294967297\n", `-`, got) - failed = true - } - - if got := sub_Neg4294967296_int64_ssa(4294967296); got != -8589934592 { - fmt.Printf("sub_int64 -4294967296%s4294967296 = %d, wanted -8589934592\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg4294967296_ssa(4294967296); got != 8589934592 { - fmt.Printf("sub_int64 4294967296%s-4294967296 = %d, wanted 8589934592\n", `-`, got) - failed = true - } - - if got := sub_Neg4294967296_int64_ssa(9223372036854775806); got != 9223372032559808514 { - fmt.Printf("sub_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808514\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg4294967296_ssa(9223372036854775806); got != -9223372032559808514 { - fmt.Printf("sub_int64 9223372036854775806%s-4294967296 = %d, wanted -9223372032559808514\n", `-`, got) - failed = true - } - - if got := sub_Neg4294967296_int64_ssa(9223372036854775807); got != 9223372032559808513 { - fmt.Printf("sub_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808513\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg4294967296_ssa(9223372036854775807); got != -9223372032559808513 { - fmt.Printf("sub_int64 9223372036854775807%s-4294967296 = %d, wanted -9223372032559808513\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int64_ssa(-9223372036854775808); got != 9223372036854775807 { - fmt.Printf("sub_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg1_ssa(-9223372036854775808); got != -9223372036854775807 { - fmt.Printf("sub_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int64_ssa(-9223372036854775807); got != 9223372036854775806 { - fmt.Printf("sub_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg1_ssa(-9223372036854775807); got != -9223372036854775806 { - fmt.Printf("sub_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775806\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int64_ssa(-4294967296); got != 4294967295 { - fmt.Printf("sub_int64 -1%s-4294967296 = %d, wanted 4294967295\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg1_ssa(-4294967296); got != -4294967295 { - fmt.Printf("sub_int64 -4294967296%s-1 = %d, wanted -4294967295\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int64_ssa(-1); got != 0 { - fmt.Printf("sub_int64 -1%s-1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg1_ssa(-1); got != 0 { - fmt.Printf("sub_int64 -1%s-1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int64_ssa(0); got != -1 { - fmt.Printf("sub_int64 -1%s0 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg1_ssa(0); got != 1 { - fmt.Printf("sub_int64 0%s-1 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int64_ssa(1); got != -2 { - fmt.Printf("sub_int64 -1%s1 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg1_ssa(1); got != 2 { - fmt.Printf("sub_int64 1%s-1 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int64_ssa(4294967296); got != -4294967297 { - fmt.Printf("sub_int64 -1%s4294967296 = %d, wanted -4294967297\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg1_ssa(4294967296); got != 4294967297 { - fmt.Printf("sub_int64 4294967296%s-1 = %d, wanted 4294967297\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int64_ssa(9223372036854775806); got != -9223372036854775807 { - fmt.Printf("sub_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg1_ssa(9223372036854775806); got != 9223372036854775807 { - fmt.Printf("sub_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int64_ssa(9223372036854775807); got != -9223372036854775808 { - fmt.Printf("sub_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_int64_Neg1_ssa(9223372036854775807); got != -9223372036854775808 { - fmt.Printf("sub_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_0_int64_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("sub_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_int64_0_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("sub_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_0_int64_ssa(-9223372036854775807); got != 9223372036854775807 { - fmt.Printf("sub_int64 0%s-9223372036854775807 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_int64_0_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("sub_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_0_int64_ssa(-4294967296); got != 4294967296 { - fmt.Printf("sub_int64 0%s-4294967296 = %d, wanted 4294967296\n", `-`, got) - failed = true - } - - if got := sub_int64_0_ssa(-4294967296); got != -4294967296 { - fmt.Printf("sub_int64 -4294967296%s0 = %d, wanted -4294967296\n", `-`, got) - failed = true - } - - if got := sub_0_int64_ssa(-1); got != 1 { - fmt.Printf("sub_int64 0%s-1 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int64_0_ssa(-1); got != -1 { - fmt.Printf("sub_int64 -1%s0 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_0_int64_ssa(0); got != 0 { - fmt.Printf("sub_int64 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int64_0_ssa(0); got != 0 { - fmt.Printf("sub_int64 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_0_int64_ssa(1); got != -1 { - fmt.Printf("sub_int64 0%s1 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int64_0_ssa(1); got != 1 { - fmt.Printf("sub_int64 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_0_int64_ssa(4294967296); got != -4294967296 { - fmt.Printf("sub_int64 0%s4294967296 = %d, wanted -4294967296\n", `-`, got) - failed = true - } - - if got := sub_int64_0_ssa(4294967296); got != 4294967296 { - fmt.Printf("sub_int64 4294967296%s0 = %d, wanted 4294967296\n", `-`, got) - failed = true - } - - if got := sub_0_int64_ssa(9223372036854775806); got != -9223372036854775806 { - fmt.Printf("sub_int64 0%s9223372036854775806 = %d, wanted -9223372036854775806\n", `-`, got) - failed = true - } - - if got := sub_int64_0_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("sub_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `-`, got) - failed = true - } - - if got := sub_0_int64_ssa(9223372036854775807); got != -9223372036854775807 { - fmt.Printf("sub_int64 0%s9223372036854775807 = %d, wanted -9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_int64_0_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("sub_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_1_int64_ssa(-9223372036854775808); got != -9223372036854775807 { - fmt.Printf("sub_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_int64_1_ssa(-9223372036854775808); got != 9223372036854775807 { - fmt.Printf("sub_int64 -9223372036854775808%s1 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_1_int64_ssa(-9223372036854775807); got != -9223372036854775808 { - fmt.Printf("sub_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_int64_1_ssa(-9223372036854775807); got != -9223372036854775808 { - fmt.Printf("sub_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_1_int64_ssa(-4294967296); got != 4294967297 { - fmt.Printf("sub_int64 1%s-4294967296 = %d, wanted 4294967297\n", `-`, got) - failed = true - } - - if got := sub_int64_1_ssa(-4294967296); got != -4294967297 { - fmt.Printf("sub_int64 -4294967296%s1 = %d, wanted -4294967297\n", `-`, got) - failed = true - } - - if got := sub_1_int64_ssa(-1); got != 2 { - fmt.Printf("sub_int64 1%s-1 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_int64_1_ssa(-1); got != -2 { - fmt.Printf("sub_int64 -1%s1 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_1_int64_ssa(0); got != 1 { - fmt.Printf("sub_int64 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int64_1_ssa(0); got != -1 { - fmt.Printf("sub_int64 0%s1 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_1_int64_ssa(1); got != 0 { - fmt.Printf("sub_int64 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int64_1_ssa(1); got != 0 { - fmt.Printf("sub_int64 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_1_int64_ssa(4294967296); got != -4294967295 { - fmt.Printf("sub_int64 1%s4294967296 = %d, wanted -4294967295\n", `-`, got) - failed = true - } - - if got := sub_int64_1_ssa(4294967296); got != 4294967295 { - fmt.Printf("sub_int64 4294967296%s1 = %d, wanted 4294967295\n", `-`, got) - failed = true - } - - if got := sub_1_int64_ssa(9223372036854775806); got != -9223372036854775805 { - fmt.Printf("sub_int64 1%s9223372036854775806 = %d, wanted -9223372036854775805\n", `-`, got) - failed = true - } - - if got := sub_int64_1_ssa(9223372036854775806); got != 9223372036854775805 { - fmt.Printf("sub_int64 9223372036854775806%s1 = %d, wanted 9223372036854775805\n", `-`, got) - failed = true - } - - if got := sub_1_int64_ssa(9223372036854775807); got != -9223372036854775806 { - fmt.Printf("sub_int64 1%s9223372036854775807 = %d, wanted -9223372036854775806\n", `-`, got) - failed = true - } - - if got := sub_int64_1_ssa(9223372036854775807); got != 9223372036854775806 { - fmt.Printf("sub_int64 9223372036854775807%s1 = %d, wanted 9223372036854775806\n", `-`, got) - failed = true - } - - if got := sub_4294967296_int64_ssa(-9223372036854775808); got != -9223372032559808512 { - fmt.Printf("sub_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `-`, got) - failed = true - } - - if got := sub_int64_4294967296_ssa(-9223372036854775808); got != 9223372032559808512 { - fmt.Printf("sub_int64 -9223372036854775808%s4294967296 = %d, wanted 9223372032559808512\n", `-`, got) - failed = true - } - - if got := sub_4294967296_int64_ssa(-9223372036854775807); got != -9223372032559808513 { - fmt.Printf("sub_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808513\n", `-`, got) - failed = true - } - - if got := sub_int64_4294967296_ssa(-9223372036854775807); got != 9223372032559808513 { - fmt.Printf("sub_int64 -9223372036854775807%s4294967296 = %d, wanted 9223372032559808513\n", `-`, got) - failed = true - } - - if got := sub_4294967296_int64_ssa(-4294967296); got != 8589934592 { - fmt.Printf("sub_int64 4294967296%s-4294967296 = %d, wanted 8589934592\n", `-`, got) - failed = true - } - - if got := sub_int64_4294967296_ssa(-4294967296); got != -8589934592 { - fmt.Printf("sub_int64 -4294967296%s4294967296 = %d, wanted -8589934592\n", `-`, got) - failed = true - } - - if got := sub_4294967296_int64_ssa(-1); got != 4294967297 { - fmt.Printf("sub_int64 4294967296%s-1 = %d, wanted 4294967297\n", `-`, got) - failed = true - } - - if got := sub_int64_4294967296_ssa(-1); got != -4294967297 { - fmt.Printf("sub_int64 -1%s4294967296 = %d, wanted -4294967297\n", `-`, got) - failed = true - } - - if got := sub_4294967296_int64_ssa(0); got != 4294967296 { - fmt.Printf("sub_int64 4294967296%s0 = %d, wanted 4294967296\n", `-`, got) - failed = true - } - - if got := sub_int64_4294967296_ssa(0); got != -4294967296 { - fmt.Printf("sub_int64 0%s4294967296 = %d, wanted -4294967296\n", `-`, got) - failed = true - } - - if got := sub_4294967296_int64_ssa(1); got != 4294967295 { - fmt.Printf("sub_int64 4294967296%s1 = %d, wanted 4294967295\n", `-`, got) - failed = true - } - - if got := sub_int64_4294967296_ssa(1); got != -4294967295 { - fmt.Printf("sub_int64 1%s4294967296 = %d, wanted -4294967295\n", `-`, got) - failed = true - } - - if got := sub_4294967296_int64_ssa(4294967296); got != 0 { - fmt.Printf("sub_int64 4294967296%s4294967296 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int64_4294967296_ssa(4294967296); got != 0 { - fmt.Printf("sub_int64 4294967296%s4294967296 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_4294967296_int64_ssa(9223372036854775806); got != -9223372032559808510 { - fmt.Printf("sub_int64 4294967296%s9223372036854775806 = %d, wanted -9223372032559808510\n", `-`, got) - failed = true - } - - if got := sub_int64_4294967296_ssa(9223372036854775806); got != 9223372032559808510 { - fmt.Printf("sub_int64 9223372036854775806%s4294967296 = %d, wanted 9223372032559808510\n", `-`, got) - failed = true - } - - if got := sub_4294967296_int64_ssa(9223372036854775807); got != -9223372032559808511 { - fmt.Printf("sub_int64 4294967296%s9223372036854775807 = %d, wanted -9223372032559808511\n", `-`, got) - failed = true - } - - if got := sub_int64_4294967296_ssa(9223372036854775807); got != 9223372032559808511 { - fmt.Printf("sub_int64 9223372036854775807%s4294967296 = %d, wanted 9223372032559808511\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775806_int64_ssa(-9223372036854775808); got != -2 { - fmt.Printf("sub_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775806_ssa(-9223372036854775808); got != 2 { - fmt.Printf("sub_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775806_int64_ssa(-9223372036854775807); got != -3 { - fmt.Printf("sub_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -3\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775806_ssa(-9223372036854775807); got != 3 { - fmt.Printf("sub_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 3\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775806_int64_ssa(-4294967296); got != -9223372032559808514 { - fmt.Printf("sub_int64 9223372036854775806%s-4294967296 = %d, wanted -9223372032559808514\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775806_ssa(-4294967296); got != 9223372032559808514 { - fmt.Printf("sub_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808514\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775806_int64_ssa(-1); got != 9223372036854775807 { - fmt.Printf("sub_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775806_ssa(-1); got != -9223372036854775807 { - fmt.Printf("sub_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775806_int64_ssa(0); got != 9223372036854775806 { - fmt.Printf("sub_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775806_ssa(0); got != -9223372036854775806 { - fmt.Printf("sub_int64 0%s9223372036854775806 = %d, wanted -9223372036854775806\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775806_int64_ssa(1); got != 9223372036854775805 { - fmt.Printf("sub_int64 9223372036854775806%s1 = %d, wanted 9223372036854775805\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775806_ssa(1); got != -9223372036854775805 { - fmt.Printf("sub_int64 1%s9223372036854775806 = %d, wanted -9223372036854775805\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775806_int64_ssa(4294967296); got != 9223372032559808510 { - fmt.Printf("sub_int64 9223372036854775806%s4294967296 = %d, wanted 9223372032559808510\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775806_ssa(4294967296); got != -9223372032559808510 { - fmt.Printf("sub_int64 4294967296%s9223372036854775806 = %d, wanted -9223372032559808510\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775806_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("sub_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775806_ssa(9223372036854775806); got != 0 { - fmt.Printf("sub_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775806_int64_ssa(9223372036854775807); got != -1 { - fmt.Printf("sub_int64 9223372036854775806%s9223372036854775807 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775806_ssa(9223372036854775807); got != 1 { - fmt.Printf("sub_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775807_int64_ssa(-9223372036854775808); got != -1 { - fmt.Printf("sub_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775807_ssa(-9223372036854775808); got != 1 { - fmt.Printf("sub_int64 -9223372036854775808%s9223372036854775807 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775807_int64_ssa(-9223372036854775807); got != -2 { - fmt.Printf("sub_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775807_ssa(-9223372036854775807); got != 2 { - fmt.Printf("sub_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775807_int64_ssa(-4294967296); got != -9223372032559808513 { - fmt.Printf("sub_int64 9223372036854775807%s-4294967296 = %d, wanted -9223372032559808513\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775807_ssa(-4294967296); got != 9223372032559808513 { - fmt.Printf("sub_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808513\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775807_int64_ssa(-1); got != -9223372036854775808 { - fmt.Printf("sub_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775807_ssa(-1); got != -9223372036854775808 { - fmt.Printf("sub_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775807_int64_ssa(0); got != 9223372036854775807 { - fmt.Printf("sub_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775807_ssa(0); got != -9223372036854775807 { - fmt.Printf("sub_int64 0%s9223372036854775807 = %d, wanted -9223372036854775807\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775807_int64_ssa(1); got != 9223372036854775806 { - fmt.Printf("sub_int64 9223372036854775807%s1 = %d, wanted 9223372036854775806\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775807_ssa(1); got != -9223372036854775806 { - fmt.Printf("sub_int64 1%s9223372036854775807 = %d, wanted -9223372036854775806\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775807_int64_ssa(4294967296); got != 9223372032559808511 { - fmt.Printf("sub_int64 9223372036854775807%s4294967296 = %d, wanted 9223372032559808511\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775807_ssa(4294967296); got != -9223372032559808511 { - fmt.Printf("sub_int64 4294967296%s9223372036854775807 = %d, wanted -9223372032559808511\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775807_int64_ssa(9223372036854775806); got != 1 { - fmt.Printf("sub_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775807_ssa(9223372036854775806); got != -1 { - fmt.Printf("sub_int64 9223372036854775806%s9223372036854775807 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_9223372036854775807_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("sub_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int64_9223372036854775807_ssa(9223372036854775807); got != 0 { - fmt.Printf("sub_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := div_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 1 { - fmt.Printf("div_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 1 { - fmt.Printf("div_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != 1 { - fmt.Printf("div_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != 0 { - fmt.Printf("div_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775808_int64_ssa(-4294967296); got != 2147483648 { - fmt.Printf("div_int64 -9223372036854775808%s-4294967296 = %d, wanted 2147483648\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775808_ssa(-4294967296); got != 0 { - fmt.Printf("div_int64 -4294967296%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775808_int64_ssa(-1); got != -9223372036854775808 { - fmt.Printf("div_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775808_ssa(-1); got != 0 { - fmt.Printf("div_int64 -1%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775808_ssa(0); got != 0 { - fmt.Printf("div_int64 0%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775808 { - fmt.Printf("div_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775808\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775808_ssa(1); got != 0 { - fmt.Printf("div_int64 1%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775808_int64_ssa(4294967296); got != -2147483648 { - fmt.Printf("div_int64 -9223372036854775808%s4294967296 = %d, wanted -2147483648\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775808_ssa(4294967296); got != 0 { - fmt.Printf("div_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -1 { - fmt.Printf("div_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775808_ssa(9223372036854775806); got != 0 { - fmt.Printf("div_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { - fmt.Printf("div_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775808_ssa(9223372036854775807); got != 0 { - fmt.Printf("div_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("div_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != 1 { - fmt.Printf("div_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 1 { - fmt.Printf("div_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 1 { - fmt.Printf("div_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775807_int64_ssa(-4294967296); got != 2147483647 { - fmt.Printf("div_int64 -9223372036854775807%s-4294967296 = %d, wanted 2147483647\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775807_ssa(-4294967296); got != 0 { - fmt.Printf("div_int64 -4294967296%s-9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775807_int64_ssa(-1); got != 9223372036854775807 { - fmt.Printf("div_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775807_ssa(-1); got != 0 { - fmt.Printf("div_int64 -1%s-9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775807_ssa(0); got != 0 { - fmt.Printf("div_int64 0%s-9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775807 { - fmt.Printf("div_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775807_ssa(1); got != 0 { - fmt.Printf("div_int64 1%s-9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775807_int64_ssa(4294967296); got != -2147483647 { - fmt.Printf("div_int64 -9223372036854775807%s4294967296 = %d, wanted -2147483647\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775807_ssa(4294967296); got != 0 { - fmt.Printf("div_int64 4294967296%s-9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { - fmt.Printf("div_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775807_ssa(9223372036854775806); got != 0 { - fmt.Printf("div_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg9223372036854775807_int64_ssa(9223372036854775807); got != -1 { - fmt.Printf("div_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -1 { - fmt.Printf("div_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_Neg4294967296_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("div_int64 -4294967296%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg4294967296_ssa(-9223372036854775808); got != 2147483648 { - fmt.Printf("div_int64 -9223372036854775808%s-4294967296 = %d, wanted 2147483648\n", `/`, got) - failed = true - } - - if got := div_Neg4294967296_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("div_int64 -4294967296%s-9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg4294967296_ssa(-9223372036854775807); got != 2147483647 { - fmt.Printf("div_int64 -9223372036854775807%s-4294967296 = %d, wanted 2147483647\n", `/`, got) - failed = true - } - - if got := div_Neg4294967296_int64_ssa(-4294967296); got != 1 { - fmt.Printf("div_int64 -4294967296%s-4294967296 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int64_Neg4294967296_ssa(-4294967296); got != 1 { - fmt.Printf("div_int64 -4294967296%s-4294967296 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_Neg4294967296_int64_ssa(-1); got != 4294967296 { - fmt.Printf("div_int64 -4294967296%s-1 = %d, wanted 4294967296\n", `/`, got) - failed = true - } - - if got := div_int64_Neg4294967296_ssa(-1); got != 0 { - fmt.Printf("div_int64 -1%s-4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg4294967296_ssa(0); got != 0 { - fmt.Printf("div_int64 0%s-4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg4294967296_int64_ssa(1); got != -4294967296 { - fmt.Printf("div_int64 -4294967296%s1 = %d, wanted -4294967296\n", `/`, got) - failed = true - } - - if got := div_int64_Neg4294967296_ssa(1); got != 0 { - fmt.Printf("div_int64 1%s-4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg4294967296_int64_ssa(4294967296); got != -1 { - fmt.Printf("div_int64 -4294967296%s4294967296 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int64_Neg4294967296_ssa(4294967296); got != -1 { - fmt.Printf("div_int64 4294967296%s-4294967296 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_Neg4294967296_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("div_int64 -4294967296%s9223372036854775806 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg4294967296_ssa(9223372036854775806); got != -2147483647 { - fmt.Printf("div_int64 9223372036854775806%s-4294967296 = %d, wanted -2147483647\n", `/`, got) - failed = true - } - - if got := div_Neg4294967296_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("div_int64 -4294967296%s9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg4294967296_ssa(9223372036854775807); got != -2147483647 { - fmt.Printf("div_int64 9223372036854775807%s-4294967296 = %d, wanted -2147483647\n", `/`, got) - failed = true - } - - if got := div_Neg1_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("div_int64 -1%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg1_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("div_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `/`, got) - failed = true - } - - if got := div_Neg1_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("div_int64 -1%s-9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg1_ssa(-9223372036854775807); got != 9223372036854775807 { - fmt.Printf("div_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `/`, got) - failed = true - } - - if got := div_Neg1_int64_ssa(-4294967296); got != 0 { - fmt.Printf("div_int64 -1%s-4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg1_ssa(-4294967296); got != 4294967296 { - fmt.Printf("div_int64 -4294967296%s-1 = %d, wanted 4294967296\n", `/`, got) - failed = true - } - - if got := div_Neg1_int64_ssa(-1); got != 1 { - fmt.Printf("div_int64 -1%s-1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int64_Neg1_ssa(-1); got != 1 { - fmt.Printf("div_int64 -1%s-1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int64_Neg1_ssa(0); got != 0 { - fmt.Printf("div_int64 0%s-1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg1_int64_ssa(1); got != -1 { - fmt.Printf("div_int64 -1%s1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int64_Neg1_ssa(1); got != -1 { - fmt.Printf("div_int64 1%s-1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_Neg1_int64_ssa(4294967296); got != 0 { - fmt.Printf("div_int64 -1%s4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg1_ssa(4294967296); got != -4294967296 { - fmt.Printf("div_int64 4294967296%s-1 = %d, wanted -4294967296\n", `/`, got) - failed = true - } - - if got := div_Neg1_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("div_int64 -1%s9223372036854775806 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg1_ssa(9223372036854775806); got != -9223372036854775806 { - fmt.Printf("div_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775806\n", `/`, got) - failed = true - } - - if got := div_Neg1_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("div_int64 -1%s9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_Neg1_ssa(9223372036854775807); got != -9223372036854775807 { - fmt.Printf("div_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `/`, got) - failed = true - } - - if got := div_0_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("div_int64 0%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("div_int64 0%s-9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int64_ssa(-4294967296); got != 0 { - fmt.Printf("div_int64 0%s-4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int64_ssa(-1); got != 0 { - fmt.Printf("div_int64 0%s-1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int64_ssa(1); got != 0 { - fmt.Printf("div_int64 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int64_ssa(4294967296); got != 0 { - fmt.Printf("div_int64 0%s4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("div_int64 0%s9223372036854775806 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("div_int64 0%s9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_1_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("div_int64 1%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_1_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("div_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775808\n", `/`, got) - failed = true - } - - if got := div_1_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("div_int64 1%s-9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_1_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("div_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `/`, got) - failed = true - } - - if got := div_1_int64_ssa(-4294967296); got != 0 { - fmt.Printf("div_int64 1%s-4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_1_ssa(-4294967296); got != -4294967296 { - fmt.Printf("div_int64 -4294967296%s1 = %d, wanted -4294967296\n", `/`, got) - failed = true - } - - if got := div_1_int64_ssa(-1); got != -1 { - fmt.Printf("div_int64 1%s-1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int64_1_ssa(-1); got != -1 { - fmt.Printf("div_int64 -1%s1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int64_1_ssa(0); got != 0 { - fmt.Printf("div_int64 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_1_int64_ssa(1); got != 1 { - fmt.Printf("div_int64 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int64_1_ssa(1); got != 1 { - fmt.Printf("div_int64 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_1_int64_ssa(4294967296); got != 0 { - fmt.Printf("div_int64 1%s4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_1_ssa(4294967296); got != 4294967296 { - fmt.Printf("div_int64 4294967296%s1 = %d, wanted 4294967296\n", `/`, got) - failed = true - } - - if got := div_1_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("div_int64 1%s9223372036854775806 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_1_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("div_int64 9223372036854775806%s1 = %d, wanted 9223372036854775806\n", `/`, got) - failed = true - } - - if got := div_1_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("div_int64 1%s9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_1_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("div_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `/`, got) - failed = true - } - - if got := div_4294967296_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("div_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_4294967296_ssa(-9223372036854775808); got != -2147483648 { - fmt.Printf("div_int64 -9223372036854775808%s4294967296 = %d, wanted -2147483648\n", `/`, got) - failed = true - } - - if got := div_4294967296_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("div_int64 4294967296%s-9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_4294967296_ssa(-9223372036854775807); got != -2147483647 { - fmt.Printf("div_int64 -9223372036854775807%s4294967296 = %d, wanted -2147483647\n", `/`, got) - failed = true - } - - if got := div_4294967296_int64_ssa(-4294967296); got != -1 { - fmt.Printf("div_int64 4294967296%s-4294967296 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int64_4294967296_ssa(-4294967296); got != -1 { - fmt.Printf("div_int64 -4294967296%s4294967296 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_4294967296_int64_ssa(-1); got != -4294967296 { - fmt.Printf("div_int64 4294967296%s-1 = %d, wanted -4294967296\n", `/`, got) - failed = true - } - - if got := div_int64_4294967296_ssa(-1); got != 0 { - fmt.Printf("div_int64 -1%s4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_4294967296_ssa(0); got != 0 { - fmt.Printf("div_int64 0%s4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_4294967296_int64_ssa(1); got != 4294967296 { - fmt.Printf("div_int64 4294967296%s1 = %d, wanted 4294967296\n", `/`, got) - failed = true - } - - if got := div_int64_4294967296_ssa(1); got != 0 { - fmt.Printf("div_int64 1%s4294967296 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_4294967296_int64_ssa(4294967296); got != 1 { - fmt.Printf("div_int64 4294967296%s4294967296 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int64_4294967296_ssa(4294967296); got != 1 { - fmt.Printf("div_int64 4294967296%s4294967296 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_4294967296_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("div_int64 4294967296%s9223372036854775806 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_4294967296_ssa(9223372036854775806); got != 2147483647 { - fmt.Printf("div_int64 9223372036854775806%s4294967296 = %d, wanted 2147483647\n", `/`, got) - failed = true - } - - if got := div_4294967296_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("div_int64 4294967296%s9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_4294967296_ssa(9223372036854775807); got != 2147483647 { - fmt.Printf("div_int64 9223372036854775807%s4294967296 = %d, wanted 2147483647\n", `/`, got) - failed = true - } - - if got := div_9223372036854775806_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("div_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775806_ssa(-9223372036854775808); got != -1 { - fmt.Printf("div_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_9223372036854775806_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("div_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { - fmt.Printf("div_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_9223372036854775806_int64_ssa(-4294967296); got != -2147483647 { - fmt.Printf("div_int64 9223372036854775806%s-4294967296 = %d, wanted -2147483647\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775806_ssa(-4294967296); got != 0 { - fmt.Printf("div_int64 -4294967296%s9223372036854775806 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_9223372036854775806_int64_ssa(-1); got != -9223372036854775806 { - fmt.Printf("div_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775806\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775806_ssa(-1); got != 0 { - fmt.Printf("div_int64 -1%s9223372036854775806 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775806_ssa(0); got != 0 { - fmt.Printf("div_int64 0%s9223372036854775806 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_9223372036854775806_int64_ssa(1); got != 9223372036854775806 { - fmt.Printf("div_int64 9223372036854775806%s1 = %d, wanted 9223372036854775806\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775806_ssa(1); got != 0 { - fmt.Printf("div_int64 1%s9223372036854775806 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_9223372036854775806_int64_ssa(4294967296); got != 2147483647 { - fmt.Printf("div_int64 9223372036854775806%s4294967296 = %d, wanted 2147483647\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775806_ssa(4294967296); got != 0 { - fmt.Printf("div_int64 4294967296%s9223372036854775806 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_9223372036854775806_int64_ssa(9223372036854775806); got != 1 { - fmt.Printf("div_int64 9223372036854775806%s9223372036854775806 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775806_ssa(9223372036854775806); got != 1 { - fmt.Printf("div_int64 9223372036854775806%s9223372036854775806 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_9223372036854775806_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("div_int64 9223372036854775806%s9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775806_ssa(9223372036854775807); got != 1 { - fmt.Printf("div_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_9223372036854775807_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("div_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { - fmt.Printf("div_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_9223372036854775807_int64_ssa(-9223372036854775807); got != -1 { - fmt.Printf("div_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775807_ssa(-9223372036854775807); got != -1 { - fmt.Printf("div_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_9223372036854775807_int64_ssa(-4294967296); got != -2147483647 { - fmt.Printf("div_int64 9223372036854775807%s-4294967296 = %d, wanted -2147483647\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775807_ssa(-4294967296); got != 0 { - fmt.Printf("div_int64 -4294967296%s9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_9223372036854775807_int64_ssa(-1); got != -9223372036854775807 { - fmt.Printf("div_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775807_ssa(-1); got != 0 { - fmt.Printf("div_int64 -1%s9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775807_ssa(0); got != 0 { - fmt.Printf("div_int64 0%s9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_9223372036854775807_int64_ssa(1); got != 9223372036854775807 { - fmt.Printf("div_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775807_ssa(1); got != 0 { - fmt.Printf("div_int64 1%s9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_9223372036854775807_int64_ssa(4294967296); got != 2147483647 { - fmt.Printf("div_int64 9223372036854775807%s4294967296 = %d, wanted 2147483647\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775807_ssa(4294967296); got != 0 { - fmt.Printf("div_int64 4294967296%s9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_9223372036854775807_int64_ssa(9223372036854775806); got != 1 { - fmt.Printf("div_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775807_ssa(9223372036854775806); got != 0 { - fmt.Printf("div_int64 9223372036854775806%s9223372036854775807 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_9223372036854775807_int64_ssa(9223372036854775807); got != 1 { - fmt.Printf("div_int64 9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int64_9223372036854775807_ssa(9223372036854775807); got != 1 { - fmt.Printf("div_int64 9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := mul_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mul_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mul_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -9223372036854775808 { - fmt.Printf("mul_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != -9223372036854775808 { - fmt.Printf("mul_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775808_int64_ssa(-4294967296); got != 0 { - fmt.Printf("mul_int64 -9223372036854775808%s-4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775808_ssa(-4294967296); got != 0 { - fmt.Printf("mul_int64 -4294967296%s-9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775808_int64_ssa(-1); got != -9223372036854775808 { - fmt.Printf("mul_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775808_ssa(-1); got != -9223372036854775808 { - fmt.Printf("mul_int64 -1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775808_int64_ssa(0); got != 0 { - fmt.Printf("mul_int64 -9223372036854775808%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775808_ssa(0); got != 0 { - fmt.Printf("mul_int64 0%s-9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775808 { - fmt.Printf("mul_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775808 { - fmt.Printf("mul_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775808_int64_ssa(4294967296); got != 0 { - fmt.Printf("mul_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775808_ssa(4294967296); got != 0 { - fmt.Printf("mul_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775808_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("mul_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775808_ssa(9223372036854775806); got != 0 { - fmt.Printf("mul_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -9223372036854775808 { - fmt.Printf("mul_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -9223372036854775808 { - fmt.Printf("mul_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("mul_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("mul_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 1 { - fmt.Printf("mul_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 1 { - fmt.Printf("mul_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775807_int64_ssa(-4294967296); got != -4294967296 { - fmt.Printf("mul_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775807_ssa(-4294967296); got != -4294967296 { - fmt.Printf("mul_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775807_int64_ssa(-1); got != 9223372036854775807 { - fmt.Printf("mul_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775807_ssa(-1); got != 9223372036854775807 { - fmt.Printf("mul_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775807_int64_ssa(0); got != 0 { - fmt.Printf("mul_int64 -9223372036854775807%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775807_ssa(0); got != 0 { - fmt.Printf("mul_int64 0%s-9223372036854775807 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775807 { - fmt.Printf("mul_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775807 { - fmt.Printf("mul_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775807_int64_ssa(4294967296); got != 4294967296 { - fmt.Printf("mul_int64 -9223372036854775807%s4294967296 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775807_ssa(4294967296); got != 4294967296 { - fmt.Printf("mul_int64 4294967296%s-9223372036854775807 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775807_int64_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("mul_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775807_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("mul_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_Neg9223372036854775807_int64_ssa(9223372036854775807); got != -1 { - fmt.Printf("mul_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -1 { - fmt.Printf("mul_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_Neg4294967296_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mul_int64 -4294967296%s-9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg4294967296_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mul_int64 -9223372036854775808%s-4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg4294967296_int64_ssa(-9223372036854775807); got != -4294967296 { - fmt.Printf("mul_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg4294967296_ssa(-9223372036854775807); got != -4294967296 { - fmt.Printf("mul_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_Neg4294967296_int64_ssa(-4294967296); got != 0 { - fmt.Printf("mul_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg4294967296_ssa(-4294967296); got != 0 { - fmt.Printf("mul_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg4294967296_int64_ssa(-1); got != 4294967296 { - fmt.Printf("mul_int64 -4294967296%s-1 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg4294967296_ssa(-1); got != 4294967296 { - fmt.Printf("mul_int64 -1%s-4294967296 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_Neg4294967296_int64_ssa(0); got != 0 { - fmt.Printf("mul_int64 -4294967296%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg4294967296_ssa(0); got != 0 { - fmt.Printf("mul_int64 0%s-4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg4294967296_int64_ssa(1); got != -4294967296 { - fmt.Printf("mul_int64 -4294967296%s1 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg4294967296_ssa(1); got != -4294967296 { - fmt.Printf("mul_int64 1%s-4294967296 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_Neg4294967296_int64_ssa(4294967296); got != 0 { - fmt.Printf("mul_int64 -4294967296%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg4294967296_ssa(4294967296); got != 0 { - fmt.Printf("mul_int64 4294967296%s-4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg4294967296_int64_ssa(9223372036854775806); got != 8589934592 { - fmt.Printf("mul_int64 -4294967296%s9223372036854775806 = %d, wanted 8589934592\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg4294967296_ssa(9223372036854775806); got != 8589934592 { - fmt.Printf("mul_int64 9223372036854775806%s-4294967296 = %d, wanted 8589934592\n", `*`, got) - failed = true - } - - if got := mul_Neg4294967296_int64_ssa(9223372036854775807); got != 4294967296 { - fmt.Printf("mul_int64 -4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg4294967296_ssa(9223372036854775807); got != 4294967296 { - fmt.Printf("mul_int64 9223372036854775807%s-4294967296 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int64_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("mul_int64 -1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg1_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("mul_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int64_ssa(-9223372036854775807); got != 9223372036854775807 { - fmt.Printf("mul_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg1_ssa(-9223372036854775807); got != 9223372036854775807 { - fmt.Printf("mul_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int64_ssa(-4294967296); got != 4294967296 { - fmt.Printf("mul_int64 -1%s-4294967296 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg1_ssa(-4294967296); got != 4294967296 { - fmt.Printf("mul_int64 -4294967296%s-1 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int64_ssa(-1); got != 1 { - fmt.Printf("mul_int64 -1%s-1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg1_ssa(-1); got != 1 { - fmt.Printf("mul_int64 -1%s-1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int64_ssa(0); got != 0 { - fmt.Printf("mul_int64 -1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg1_ssa(0); got != 0 { - fmt.Printf("mul_int64 0%s-1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int64_ssa(1); got != -1 { - fmt.Printf("mul_int64 -1%s1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg1_ssa(1); got != -1 { - fmt.Printf("mul_int64 1%s-1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int64_ssa(4294967296); got != -4294967296 { - fmt.Printf("mul_int64 -1%s4294967296 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg1_ssa(4294967296); got != -4294967296 { - fmt.Printf("mul_int64 4294967296%s-1 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int64_ssa(9223372036854775806); got != -9223372036854775806 { - fmt.Printf("mul_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg1_ssa(9223372036854775806); got != -9223372036854775806 { - fmt.Printf("mul_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int64_ssa(9223372036854775807); got != -9223372036854775807 { - fmt.Printf("mul_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_int64_Neg1_ssa(9223372036854775807); got != -9223372036854775807 { - fmt.Printf("mul_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_0_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mul_int64 0%s-9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_0_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mul_int64 -9223372036854775808%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("mul_int64 0%s-9223372036854775807 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_0_ssa(-9223372036854775807); got != 0 { - fmt.Printf("mul_int64 -9223372036854775807%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int64_ssa(-4294967296); got != 0 { - fmt.Printf("mul_int64 0%s-4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_0_ssa(-4294967296); got != 0 { - fmt.Printf("mul_int64 -4294967296%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int64_ssa(-1); got != 0 { - fmt.Printf("mul_int64 0%s-1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_0_ssa(-1); got != 0 { - fmt.Printf("mul_int64 -1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int64_ssa(0); got != 0 { - fmt.Printf("mul_int64 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_0_ssa(0); got != 0 { - fmt.Printf("mul_int64 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int64_ssa(1); got != 0 { - fmt.Printf("mul_int64 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_0_ssa(1); got != 0 { - fmt.Printf("mul_int64 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int64_ssa(4294967296); got != 0 { - fmt.Printf("mul_int64 0%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_0_ssa(4294967296); got != 0 { - fmt.Printf("mul_int64 4294967296%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("mul_int64 0%s9223372036854775806 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_0_ssa(9223372036854775806); got != 0 { - fmt.Printf("mul_int64 9223372036854775806%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("mul_int64 0%s9223372036854775807 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_0_ssa(9223372036854775807); got != 0 { - fmt.Printf("mul_int64 9223372036854775807%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_int64_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("mul_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_int64_1_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("mul_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_1_int64_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("mul_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_int64_1_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("mul_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_1_int64_ssa(-4294967296); got != -4294967296 { - fmt.Printf("mul_int64 1%s-4294967296 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_1_ssa(-4294967296); got != -4294967296 { - fmt.Printf("mul_int64 -4294967296%s1 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_1_int64_ssa(-1); got != -1 { - fmt.Printf("mul_int64 1%s-1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int64_1_ssa(-1); got != -1 { - fmt.Printf("mul_int64 -1%s1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_1_int64_ssa(0); got != 0 { - fmt.Printf("mul_int64 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_1_ssa(0); got != 0 { - fmt.Printf("mul_int64 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_int64_ssa(1); got != 1 { - fmt.Printf("mul_int64 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int64_1_ssa(1); got != 1 { - fmt.Printf("mul_int64 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_1_int64_ssa(4294967296); got != 4294967296 { - fmt.Printf("mul_int64 1%s4294967296 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_1_ssa(4294967296); got != 4294967296 { - fmt.Printf("mul_int64 4294967296%s1 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_1_int64_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("mul_int64 1%s9223372036854775806 = %d, wanted 9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_int64_1_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("mul_int64 9223372036854775806%s1 = %d, wanted 9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_1_int64_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("mul_int64 1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_int64_1_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("mul_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_4294967296_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mul_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_4294967296_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mul_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_4294967296_int64_ssa(-9223372036854775807); got != 4294967296 { - fmt.Printf("mul_int64 4294967296%s-9223372036854775807 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_4294967296_ssa(-9223372036854775807); got != 4294967296 { - fmt.Printf("mul_int64 -9223372036854775807%s4294967296 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_4294967296_int64_ssa(-4294967296); got != 0 { - fmt.Printf("mul_int64 4294967296%s-4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_4294967296_ssa(-4294967296); got != 0 { - fmt.Printf("mul_int64 -4294967296%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_4294967296_int64_ssa(-1); got != -4294967296 { - fmt.Printf("mul_int64 4294967296%s-1 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_4294967296_ssa(-1); got != -4294967296 { - fmt.Printf("mul_int64 -1%s4294967296 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_4294967296_int64_ssa(0); got != 0 { - fmt.Printf("mul_int64 4294967296%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_4294967296_ssa(0); got != 0 { - fmt.Printf("mul_int64 0%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_4294967296_int64_ssa(1); got != 4294967296 { - fmt.Printf("mul_int64 4294967296%s1 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_4294967296_ssa(1); got != 4294967296 { - fmt.Printf("mul_int64 1%s4294967296 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_4294967296_int64_ssa(4294967296); got != 0 { - fmt.Printf("mul_int64 4294967296%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_4294967296_ssa(4294967296); got != 0 { - fmt.Printf("mul_int64 4294967296%s4294967296 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_4294967296_int64_ssa(9223372036854775806); got != -8589934592 { - fmt.Printf("mul_int64 4294967296%s9223372036854775806 = %d, wanted -8589934592\n", `*`, got) - failed = true - } - - if got := mul_int64_4294967296_ssa(9223372036854775806); got != -8589934592 { - fmt.Printf("mul_int64 9223372036854775806%s4294967296 = %d, wanted -8589934592\n", `*`, got) - failed = true - } - - if got := mul_4294967296_int64_ssa(9223372036854775807); got != -4294967296 { - fmt.Printf("mul_int64 4294967296%s9223372036854775807 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_4294967296_ssa(9223372036854775807); got != -4294967296 { - fmt.Printf("mul_int64 9223372036854775807%s4294967296 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775806_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mul_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775806_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mul_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775806_int64_ssa(-9223372036854775807); got != 9223372036854775806 { - fmt.Printf("mul_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775806_ssa(-9223372036854775807); got != 9223372036854775806 { - fmt.Printf("mul_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775806_int64_ssa(-4294967296); got != 8589934592 { - fmt.Printf("mul_int64 9223372036854775806%s-4294967296 = %d, wanted 8589934592\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775806_ssa(-4294967296); got != 8589934592 { - fmt.Printf("mul_int64 -4294967296%s9223372036854775806 = %d, wanted 8589934592\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775806_int64_ssa(-1); got != -9223372036854775806 { - fmt.Printf("mul_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775806_ssa(-1); got != -9223372036854775806 { - fmt.Printf("mul_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775806_int64_ssa(0); got != 0 { - fmt.Printf("mul_int64 9223372036854775806%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775806_ssa(0); got != 0 { - fmt.Printf("mul_int64 0%s9223372036854775806 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775806_int64_ssa(1); got != 9223372036854775806 { - fmt.Printf("mul_int64 9223372036854775806%s1 = %d, wanted 9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775806_ssa(1); got != 9223372036854775806 { - fmt.Printf("mul_int64 1%s9223372036854775806 = %d, wanted 9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775806_int64_ssa(4294967296); got != -8589934592 { - fmt.Printf("mul_int64 9223372036854775806%s4294967296 = %d, wanted -8589934592\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775806_ssa(4294967296); got != -8589934592 { - fmt.Printf("mul_int64 4294967296%s9223372036854775806 = %d, wanted -8589934592\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775806_int64_ssa(9223372036854775806); got != 4 { - fmt.Printf("mul_int64 9223372036854775806%s9223372036854775806 = %d, wanted 4\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775806_ssa(9223372036854775806); got != 4 { - fmt.Printf("mul_int64 9223372036854775806%s9223372036854775806 = %d, wanted 4\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775806_int64_ssa(9223372036854775807); got != -9223372036854775806 { - fmt.Printf("mul_int64 9223372036854775806%s9223372036854775807 = %d, wanted -9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775806_ssa(9223372036854775807); got != -9223372036854775806 { - fmt.Printf("mul_int64 9223372036854775807%s9223372036854775806 = %d, wanted -9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("mul_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775807_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("mul_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -9223372036854775808\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775807_int64_ssa(-9223372036854775807); got != -1 { - fmt.Printf("mul_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775807_ssa(-9223372036854775807); got != -1 { - fmt.Printf("mul_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775807_int64_ssa(-4294967296); got != 4294967296 { - fmt.Printf("mul_int64 9223372036854775807%s-4294967296 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775807_ssa(-4294967296); got != 4294967296 { - fmt.Printf("mul_int64 -4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775807_int64_ssa(-1); got != -9223372036854775807 { - fmt.Printf("mul_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775807_ssa(-1); got != -9223372036854775807 { - fmt.Printf("mul_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775807_int64_ssa(0); got != 0 { - fmt.Printf("mul_int64 9223372036854775807%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775807_ssa(0); got != 0 { - fmt.Printf("mul_int64 0%s9223372036854775807 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775807_int64_ssa(1); got != 9223372036854775807 { - fmt.Printf("mul_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775807_ssa(1); got != 9223372036854775807 { - fmt.Printf("mul_int64 1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775807_int64_ssa(4294967296); got != -4294967296 { - fmt.Printf("mul_int64 9223372036854775807%s4294967296 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775807_ssa(4294967296); got != -4294967296 { - fmt.Printf("mul_int64 4294967296%s9223372036854775807 = %d, wanted -4294967296\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775807_int64_ssa(9223372036854775806); got != -9223372036854775806 { - fmt.Printf("mul_int64 9223372036854775807%s9223372036854775806 = %d, wanted -9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775807_ssa(9223372036854775806); got != -9223372036854775806 { - fmt.Printf("mul_int64 9223372036854775806%s9223372036854775807 = %d, wanted -9223372036854775806\n", `*`, got) - failed = true - } - - if got := mul_9223372036854775807_int64_ssa(9223372036854775807); got != 1 { - fmt.Printf("mul_int64 9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int64_9223372036854775807_ssa(9223372036854775807); got != 1 { - fmt.Printf("mul_int64 9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mod_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mod_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mod_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -1 { - fmt.Printf("mod_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("mod_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775808_int64_ssa(-4294967296); got != 0 { - fmt.Printf("mod_int64 -9223372036854775808%s-4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775808_ssa(-4294967296); got != -4294967296 { - fmt.Printf("mod_int64 -4294967296%s-9223372036854775808 = %d, wanted -4294967296\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775808_int64_ssa(-1); got != 0 { - fmt.Printf("mod_int64 -9223372036854775808%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775808_ssa(-1); got != -1 { - fmt.Printf("mod_int64 -1%s-9223372036854775808 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775808_ssa(0); got != 0 { - fmt.Printf("mod_int64 0%s-9223372036854775808 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775808_int64_ssa(1); got != 0 { - fmt.Printf("mod_int64 -9223372036854775808%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775808_ssa(1); got != 1 { - fmt.Printf("mod_int64 1%s-9223372036854775808 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775808_int64_ssa(4294967296); got != 0 { - fmt.Printf("mod_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775808_ssa(4294967296); got != 4294967296 { - fmt.Printf("mod_int64 4294967296%s-9223372036854775808 = %d, wanted 4294967296\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -2 { - fmt.Printf("mod_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775808_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("mod_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 9223372036854775806\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { - fmt.Printf("mod_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775808_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("mod_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775807 { - fmt.Printf("mod_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -1 { - fmt.Printf("mod_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("mod_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 0 { - fmt.Printf("mod_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775807_int64_ssa(-4294967296); got != -4294967295 { - fmt.Printf("mod_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967295\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775807_ssa(-4294967296); got != -4294967296 { - fmt.Printf("mod_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967296\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775807_int64_ssa(-1); got != 0 { - fmt.Printf("mod_int64 -9223372036854775807%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775807_ssa(-1); got != -1 { - fmt.Printf("mod_int64 -1%s-9223372036854775807 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775807_ssa(0); got != 0 { - fmt.Printf("mod_int64 0%s-9223372036854775807 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775807_int64_ssa(1); got != 0 { - fmt.Printf("mod_int64 -9223372036854775807%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775807_ssa(1); got != 1 { - fmt.Printf("mod_int64 1%s-9223372036854775807 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775807_int64_ssa(4294967296); got != -4294967295 { - fmt.Printf("mod_int64 -9223372036854775807%s4294967296 = %d, wanted -4294967295\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775807_ssa(4294967296); got != 4294967296 { - fmt.Printf("mod_int64 4294967296%s-9223372036854775807 = %d, wanted 4294967296\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { - fmt.Printf("mod_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775807_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("mod_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `%`, got) - failed = true - } - - if got := mod_Neg9223372036854775807_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("mod_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg9223372036854775807_ssa(9223372036854775807); got != 0 { - fmt.Printf("mod_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg4294967296_int64_ssa(-9223372036854775808); got != -4294967296 { - fmt.Printf("mod_int64 -4294967296%s-9223372036854775808 = %d, wanted -4294967296\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg4294967296_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mod_int64 -9223372036854775808%s-4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg4294967296_int64_ssa(-9223372036854775807); got != -4294967296 { - fmt.Printf("mod_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967296\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg4294967296_ssa(-9223372036854775807); got != -4294967295 { - fmt.Printf("mod_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967295\n", `%`, got) - failed = true - } - - if got := mod_Neg4294967296_int64_ssa(-4294967296); got != 0 { - fmt.Printf("mod_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg4294967296_ssa(-4294967296); got != 0 { - fmt.Printf("mod_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg4294967296_int64_ssa(-1); got != 0 { - fmt.Printf("mod_int64 -4294967296%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg4294967296_ssa(-1); got != -1 { - fmt.Printf("mod_int64 -1%s-4294967296 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg4294967296_ssa(0); got != 0 { - fmt.Printf("mod_int64 0%s-4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg4294967296_int64_ssa(1); got != 0 { - fmt.Printf("mod_int64 -4294967296%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg4294967296_ssa(1); got != 1 { - fmt.Printf("mod_int64 1%s-4294967296 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_Neg4294967296_int64_ssa(4294967296); got != 0 { - fmt.Printf("mod_int64 -4294967296%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg4294967296_ssa(4294967296); got != 0 { - fmt.Printf("mod_int64 4294967296%s-4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg4294967296_int64_ssa(9223372036854775806); got != -4294967296 { - fmt.Printf("mod_int64 -4294967296%s9223372036854775806 = %d, wanted -4294967296\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg4294967296_ssa(9223372036854775806); got != 4294967294 { - fmt.Printf("mod_int64 9223372036854775806%s-4294967296 = %d, wanted 4294967294\n", `%`, got) - failed = true - } - - if got := mod_Neg4294967296_int64_ssa(9223372036854775807); got != -4294967296 { - fmt.Printf("mod_int64 -4294967296%s9223372036854775807 = %d, wanted -4294967296\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg4294967296_ssa(9223372036854775807); got != 4294967295 { - fmt.Printf("mod_int64 9223372036854775807%s-4294967296 = %d, wanted 4294967295\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int64_ssa(-9223372036854775808); got != -1 { - fmt.Printf("mod_int64 -1%s-9223372036854775808 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg1_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mod_int64 -9223372036854775808%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int64_ssa(-9223372036854775807); got != -1 { - fmt.Printf("mod_int64 -1%s-9223372036854775807 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg1_ssa(-9223372036854775807); got != 0 { - fmt.Printf("mod_int64 -9223372036854775807%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int64_ssa(-4294967296); got != -1 { - fmt.Printf("mod_int64 -1%s-4294967296 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg1_ssa(-4294967296); got != 0 { - fmt.Printf("mod_int64 -4294967296%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int64_ssa(-1); got != 0 { - fmt.Printf("mod_int64 -1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg1_ssa(-1); got != 0 { - fmt.Printf("mod_int64 -1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg1_ssa(0); got != 0 { - fmt.Printf("mod_int64 0%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int64_ssa(1); got != 0 { - fmt.Printf("mod_int64 -1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg1_ssa(1); got != 0 { - fmt.Printf("mod_int64 1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int64_ssa(4294967296); got != -1 { - fmt.Printf("mod_int64 -1%s4294967296 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg1_ssa(4294967296); got != 0 { - fmt.Printf("mod_int64 4294967296%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int64_ssa(9223372036854775806); got != -1 { - fmt.Printf("mod_int64 -1%s9223372036854775806 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg1_ssa(9223372036854775806); got != 0 { - fmt.Printf("mod_int64 9223372036854775806%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int64_ssa(9223372036854775807); got != -1 { - fmt.Printf("mod_int64 -1%s9223372036854775807 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_Neg1_ssa(9223372036854775807); got != 0 { - fmt.Printf("mod_int64 9223372036854775807%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mod_int64 0%s-9223372036854775808 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("mod_int64 0%s-9223372036854775807 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int64_ssa(-4294967296); got != 0 { - fmt.Printf("mod_int64 0%s-4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int64_ssa(-1); got != 0 { - fmt.Printf("mod_int64 0%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int64_ssa(1); got != 0 { - fmt.Printf("mod_int64 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int64_ssa(4294967296); got != 0 { - fmt.Printf("mod_int64 0%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("mod_int64 0%s9223372036854775806 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("mod_int64 0%s9223372036854775807 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int64_ssa(-9223372036854775808); got != 1 { - fmt.Printf("mod_int64 1%s-9223372036854775808 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int64_1_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mod_int64 -9223372036854775808%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int64_ssa(-9223372036854775807); got != 1 { - fmt.Printf("mod_int64 1%s-9223372036854775807 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int64_1_ssa(-9223372036854775807); got != 0 { - fmt.Printf("mod_int64 -9223372036854775807%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int64_ssa(-4294967296); got != 1 { - fmt.Printf("mod_int64 1%s-4294967296 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int64_1_ssa(-4294967296); got != 0 { - fmt.Printf("mod_int64 -4294967296%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int64_ssa(-1); got != 0 { - fmt.Printf("mod_int64 1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_1_ssa(-1); got != 0 { - fmt.Printf("mod_int64 -1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_1_ssa(0); got != 0 { - fmt.Printf("mod_int64 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int64_ssa(1); got != 0 { - fmt.Printf("mod_int64 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_1_ssa(1); got != 0 { - fmt.Printf("mod_int64 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int64_ssa(4294967296); got != 1 { - fmt.Printf("mod_int64 1%s4294967296 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int64_1_ssa(4294967296); got != 0 { - fmt.Printf("mod_int64 4294967296%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int64_ssa(9223372036854775806); got != 1 { - fmt.Printf("mod_int64 1%s9223372036854775806 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int64_1_ssa(9223372036854775806); got != 0 { - fmt.Printf("mod_int64 9223372036854775806%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int64_ssa(9223372036854775807); got != 1 { - fmt.Printf("mod_int64 1%s9223372036854775807 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int64_1_ssa(9223372036854775807); got != 0 { - fmt.Printf("mod_int64 9223372036854775807%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_4294967296_int64_ssa(-9223372036854775808); got != 4294967296 { - fmt.Printf("mod_int64 4294967296%s-9223372036854775808 = %d, wanted 4294967296\n", `%`, got) - failed = true - } - - if got := mod_int64_4294967296_ssa(-9223372036854775808); got != 0 { - fmt.Printf("mod_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_4294967296_int64_ssa(-9223372036854775807); got != 4294967296 { - fmt.Printf("mod_int64 4294967296%s-9223372036854775807 = %d, wanted 4294967296\n", `%`, got) - failed = true - } - - if got := mod_int64_4294967296_ssa(-9223372036854775807); got != -4294967295 { - fmt.Printf("mod_int64 -9223372036854775807%s4294967296 = %d, wanted -4294967295\n", `%`, got) - failed = true - } - - if got := mod_4294967296_int64_ssa(-4294967296); got != 0 { - fmt.Printf("mod_int64 4294967296%s-4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_4294967296_ssa(-4294967296); got != 0 { - fmt.Printf("mod_int64 -4294967296%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_4294967296_int64_ssa(-1); got != 0 { - fmt.Printf("mod_int64 4294967296%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_4294967296_ssa(-1); got != -1 { - fmt.Printf("mod_int64 -1%s4294967296 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_4294967296_ssa(0); got != 0 { - fmt.Printf("mod_int64 0%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_4294967296_int64_ssa(1); got != 0 { - fmt.Printf("mod_int64 4294967296%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_4294967296_ssa(1); got != 1 { - fmt.Printf("mod_int64 1%s4294967296 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_4294967296_int64_ssa(4294967296); got != 0 { - fmt.Printf("mod_int64 4294967296%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_4294967296_ssa(4294967296); got != 0 { - fmt.Printf("mod_int64 4294967296%s4294967296 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_4294967296_int64_ssa(9223372036854775806); got != 4294967296 { - fmt.Printf("mod_int64 4294967296%s9223372036854775806 = %d, wanted 4294967296\n", `%`, got) - failed = true - } - - if got := mod_int64_4294967296_ssa(9223372036854775806); got != 4294967294 { - fmt.Printf("mod_int64 9223372036854775806%s4294967296 = %d, wanted 4294967294\n", `%`, got) - failed = true - } - - if got := mod_4294967296_int64_ssa(9223372036854775807); got != 4294967296 { - fmt.Printf("mod_int64 4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `%`, got) - failed = true - } - - if got := mod_int64_4294967296_ssa(9223372036854775807); got != 4294967295 { - fmt.Printf("mod_int64 9223372036854775807%s4294967296 = %d, wanted 4294967295\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775806_int64_ssa(-9223372036854775808); got != 9223372036854775806 { - fmt.Printf("mod_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 9223372036854775806\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775806_ssa(-9223372036854775808); got != -2 { - fmt.Printf("mod_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775806_int64_ssa(-9223372036854775807); got != 9223372036854775806 { - fmt.Printf("mod_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { - fmt.Printf("mod_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775806_int64_ssa(-4294967296); got != 4294967294 { - fmt.Printf("mod_int64 9223372036854775806%s-4294967296 = %d, wanted 4294967294\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775806_ssa(-4294967296); got != -4294967296 { - fmt.Printf("mod_int64 -4294967296%s9223372036854775806 = %d, wanted -4294967296\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775806_int64_ssa(-1); got != 0 { - fmt.Printf("mod_int64 9223372036854775806%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775806_ssa(-1); got != -1 { - fmt.Printf("mod_int64 -1%s9223372036854775806 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775806_ssa(0); got != 0 { - fmt.Printf("mod_int64 0%s9223372036854775806 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775806_int64_ssa(1); got != 0 { - fmt.Printf("mod_int64 9223372036854775806%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775806_ssa(1); got != 1 { - fmt.Printf("mod_int64 1%s9223372036854775806 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775806_int64_ssa(4294967296); got != 4294967294 { - fmt.Printf("mod_int64 9223372036854775806%s4294967296 = %d, wanted 4294967294\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775806_ssa(4294967296); got != 4294967296 { - fmt.Printf("mod_int64 4294967296%s9223372036854775806 = %d, wanted 4294967296\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775806_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("mod_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775806_ssa(9223372036854775806); got != 0 { - fmt.Printf("mod_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775806_int64_ssa(9223372036854775807); got != 9223372036854775806 { - fmt.Printf("mod_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775806\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775806_ssa(9223372036854775807); got != 1 { - fmt.Printf("mod_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775807_int64_ssa(-9223372036854775808); got != 9223372036854775807 { - fmt.Printf("mod_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { - fmt.Printf("mod_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("mod_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775807_ssa(-9223372036854775807); got != 0 { - fmt.Printf("mod_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775807_int64_ssa(-4294967296); got != 4294967295 { - fmt.Printf("mod_int64 9223372036854775807%s-4294967296 = %d, wanted 4294967295\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775807_ssa(-4294967296); got != -4294967296 { - fmt.Printf("mod_int64 -4294967296%s9223372036854775807 = %d, wanted -4294967296\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775807_int64_ssa(-1); got != 0 { - fmt.Printf("mod_int64 9223372036854775807%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775807_ssa(-1); got != -1 { - fmt.Printf("mod_int64 -1%s9223372036854775807 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775807_ssa(0); got != 0 { - fmt.Printf("mod_int64 0%s9223372036854775807 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775807_int64_ssa(1); got != 0 { - fmt.Printf("mod_int64 9223372036854775807%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775807_ssa(1); got != 1 { - fmt.Printf("mod_int64 1%s9223372036854775807 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775807_int64_ssa(4294967296); got != 4294967295 { - fmt.Printf("mod_int64 9223372036854775807%s4294967296 = %d, wanted 4294967295\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775807_ssa(4294967296); got != 4294967296 { - fmt.Printf("mod_int64 4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775807_int64_ssa(9223372036854775806); got != 1 { - fmt.Printf("mod_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775807_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("mod_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775806\n", `%`, got) - failed = true - } - - if got := mod_9223372036854775807_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("mod_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int64_9223372036854775807_ssa(9223372036854775807); got != 0 { - fmt.Printf("mod_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := and_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("and_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("and_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -9223372036854775808 { - fmt.Printf("and_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != -9223372036854775808 { - fmt.Printf("and_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775808_int64_ssa(-4294967296); got != -9223372036854775808 { - fmt.Printf("and_int64 -9223372036854775808%s-4294967296 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775808_ssa(-4294967296); got != -9223372036854775808 { - fmt.Printf("and_int64 -4294967296%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775808_int64_ssa(-1); got != -9223372036854775808 { - fmt.Printf("and_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775808_ssa(-1); got != -9223372036854775808 { - fmt.Printf("and_int64 -1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775808_int64_ssa(0); got != 0 { - fmt.Printf("and_int64 -9223372036854775808%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775808_ssa(0); got != 0 { - fmt.Printf("and_int64 0%s-9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775808_int64_ssa(1); got != 0 { - fmt.Printf("and_int64 -9223372036854775808%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775808_ssa(1); got != 0 { - fmt.Printf("and_int64 1%s-9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775808_int64_ssa(4294967296); got != 0 { - fmt.Printf("and_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775808_ssa(4294967296); got != 0 { - fmt.Printf("and_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775808_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("and_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775808_ssa(9223372036854775806); got != 0 { - fmt.Printf("and_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775808_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("and_int64 -9223372036854775808%s9223372036854775807 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775808_ssa(9223372036854775807); got != 0 { - fmt.Printf("and_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("and_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("and_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("and_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("and_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775807_int64_ssa(-4294967296); got != -9223372036854775808 { - fmt.Printf("and_int64 -9223372036854775807%s-4294967296 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775807_ssa(-4294967296); got != -9223372036854775808 { - fmt.Printf("and_int64 -4294967296%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775807_int64_ssa(-1); got != -9223372036854775807 { - fmt.Printf("and_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775807_ssa(-1); got != -9223372036854775807 { - fmt.Printf("and_int64 -1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775807_int64_ssa(0); got != 0 { - fmt.Printf("and_int64 -9223372036854775807%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775807_ssa(0); got != 0 { - fmt.Printf("and_int64 0%s-9223372036854775807 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775807_int64_ssa(1); got != 1 { - fmt.Printf("and_int64 -9223372036854775807%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775807_ssa(1); got != 1 { - fmt.Printf("and_int64 1%s-9223372036854775807 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775807_int64_ssa(4294967296); got != 0 { - fmt.Printf("and_int64 -9223372036854775807%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775807_ssa(4294967296); got != 0 { - fmt.Printf("and_int64 4294967296%s-9223372036854775807 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775807_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("and_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775807_ssa(9223372036854775806); got != 0 { - fmt.Printf("and_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg9223372036854775807_int64_ssa(9223372036854775807); got != 1 { - fmt.Printf("and_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int64_Neg9223372036854775807_ssa(9223372036854775807); got != 1 { - fmt.Printf("and_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_Neg4294967296_int64_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("and_int64 -4294967296%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_int64_Neg4294967296_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("and_int64 -9223372036854775808%s-4294967296 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_Neg4294967296_int64_ssa(-9223372036854775807); got != -9223372036854775808 { - fmt.Printf("and_int64 -4294967296%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_int64_Neg4294967296_ssa(-9223372036854775807); got != -9223372036854775808 { - fmt.Printf("and_int64 -9223372036854775807%s-4294967296 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_Neg4294967296_int64_ssa(-4294967296); got != -4294967296 { - fmt.Printf("and_int64 -4294967296%s-4294967296 = %d, wanted -4294967296\n", `&`, got) - failed = true - } - - if got := and_int64_Neg4294967296_ssa(-4294967296); got != -4294967296 { - fmt.Printf("and_int64 -4294967296%s-4294967296 = %d, wanted -4294967296\n", `&`, got) - failed = true - } - - if got := and_Neg4294967296_int64_ssa(-1); got != -4294967296 { - fmt.Printf("and_int64 -4294967296%s-1 = %d, wanted -4294967296\n", `&`, got) - failed = true - } - - if got := and_int64_Neg4294967296_ssa(-1); got != -4294967296 { - fmt.Printf("and_int64 -1%s-4294967296 = %d, wanted -4294967296\n", `&`, got) - failed = true - } - - if got := and_Neg4294967296_int64_ssa(0); got != 0 { - fmt.Printf("and_int64 -4294967296%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_Neg4294967296_ssa(0); got != 0 { - fmt.Printf("and_int64 0%s-4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg4294967296_int64_ssa(1); got != 0 { - fmt.Printf("and_int64 -4294967296%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_Neg4294967296_ssa(1); got != 0 { - fmt.Printf("and_int64 1%s-4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg4294967296_int64_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_int64 -4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_int64_Neg4294967296_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_int64 4294967296%s-4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_Neg4294967296_int64_ssa(9223372036854775806); got != 9223372032559808512 { - fmt.Printf("and_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808512\n", `&`, got) - failed = true - } - - if got := and_int64_Neg4294967296_ssa(9223372036854775806); got != 9223372032559808512 { - fmt.Printf("and_int64 9223372036854775806%s-4294967296 = %d, wanted 9223372032559808512\n", `&`, got) - failed = true - } - - if got := and_Neg4294967296_int64_ssa(9223372036854775807); got != 9223372032559808512 { - fmt.Printf("and_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808512\n", `&`, got) - failed = true - } - - if got := and_int64_Neg4294967296_ssa(9223372036854775807); got != 9223372032559808512 { - fmt.Printf("and_int64 9223372036854775807%s-4294967296 = %d, wanted 9223372032559808512\n", `&`, got) - failed = true - } - - if got := and_Neg1_int64_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("and_int64 -1%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_int64_Neg1_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("and_int64 -9223372036854775808%s-1 = %d, wanted -9223372036854775808\n", `&`, got) - failed = true - } - - if got := and_Neg1_int64_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("and_int64 -1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `&`, got) - failed = true - } - - if got := and_int64_Neg1_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("and_int64 -9223372036854775807%s-1 = %d, wanted -9223372036854775807\n", `&`, got) - failed = true - } - - if got := and_Neg1_int64_ssa(-4294967296); got != -4294967296 { - fmt.Printf("and_int64 -1%s-4294967296 = %d, wanted -4294967296\n", `&`, got) - failed = true - } - - if got := and_int64_Neg1_ssa(-4294967296); got != -4294967296 { - fmt.Printf("and_int64 -4294967296%s-1 = %d, wanted -4294967296\n", `&`, got) - failed = true - } - - if got := and_Neg1_int64_ssa(-1); got != -1 { - fmt.Printf("and_int64 -1%s-1 = %d, wanted -1\n", `&`, got) - failed = true - } - - if got := and_int64_Neg1_ssa(-1); got != -1 { - fmt.Printf("and_int64 -1%s-1 = %d, wanted -1\n", `&`, got) - failed = true - } - - if got := and_Neg1_int64_ssa(0); got != 0 { - fmt.Printf("and_int64 -1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_Neg1_ssa(0); got != 0 { - fmt.Printf("and_int64 0%s-1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg1_int64_ssa(1); got != 1 { - fmt.Printf("and_int64 -1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int64_Neg1_ssa(1); got != 1 { - fmt.Printf("and_int64 1%s-1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_Neg1_int64_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_int64 -1%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_int64_Neg1_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_int64 4294967296%s-1 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_Neg1_int64_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("and_int64 -1%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) - failed = true - } - - if got := and_int64_Neg1_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("and_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775806\n", `&`, got) - failed = true - } - - if got := and_Neg1_int64_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("and_int64 -1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `&`, got) - failed = true - } - - if got := and_int64_Neg1_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("and_int64 9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `&`, got) - failed = true - } - - if got := and_0_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("and_int64 0%s-9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_0_ssa(-9223372036854775808); got != 0 { - fmt.Printf("and_int64 -9223372036854775808%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("and_int64 0%s-9223372036854775807 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_0_ssa(-9223372036854775807); got != 0 { - fmt.Printf("and_int64 -9223372036854775807%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int64_ssa(-4294967296); got != 0 { - fmt.Printf("and_int64 0%s-4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_0_ssa(-4294967296); got != 0 { - fmt.Printf("and_int64 -4294967296%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int64_ssa(-1); got != 0 { - fmt.Printf("and_int64 0%s-1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_0_ssa(-1); got != 0 { - fmt.Printf("and_int64 -1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int64_ssa(0); got != 0 { - fmt.Printf("and_int64 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_0_ssa(0); got != 0 { - fmt.Printf("and_int64 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int64_ssa(1); got != 0 { - fmt.Printf("and_int64 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_0_ssa(1); got != 0 { - fmt.Printf("and_int64 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int64_ssa(4294967296); got != 0 { - fmt.Printf("and_int64 0%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_0_ssa(4294967296); got != 0 { - fmt.Printf("and_int64 4294967296%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("and_int64 0%s9223372036854775806 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_0_ssa(9223372036854775806); got != 0 { - fmt.Printf("and_int64 9223372036854775806%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("and_int64 0%s9223372036854775807 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_0_ssa(9223372036854775807); got != 0 { - fmt.Printf("and_int64 9223372036854775807%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("and_int64 1%s-9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_1_ssa(-9223372036854775808); got != 0 { - fmt.Printf("and_int64 -9223372036854775808%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int64_ssa(-9223372036854775807); got != 1 { - fmt.Printf("and_int64 1%s-9223372036854775807 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int64_1_ssa(-9223372036854775807); got != 1 { - fmt.Printf("and_int64 -9223372036854775807%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_int64_ssa(-4294967296); got != 0 { - fmt.Printf("and_int64 1%s-4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_1_ssa(-4294967296); got != 0 { - fmt.Printf("and_int64 -4294967296%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int64_ssa(-1); got != 1 { - fmt.Printf("and_int64 1%s-1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int64_1_ssa(-1); got != 1 { - fmt.Printf("and_int64 -1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_int64_ssa(0); got != 0 { - fmt.Printf("and_int64 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_1_ssa(0); got != 0 { - fmt.Printf("and_int64 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int64_ssa(1); got != 1 { - fmt.Printf("and_int64 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int64_1_ssa(1); got != 1 { - fmt.Printf("and_int64 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_int64_ssa(4294967296); got != 0 { - fmt.Printf("and_int64 1%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_1_ssa(4294967296); got != 0 { - fmt.Printf("and_int64 4294967296%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("and_int64 1%s9223372036854775806 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_1_ssa(9223372036854775806); got != 0 { - fmt.Printf("and_int64 9223372036854775806%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int64_ssa(9223372036854775807); got != 1 { - fmt.Printf("and_int64 1%s9223372036854775807 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int64_1_ssa(9223372036854775807); got != 1 { - fmt.Printf("and_int64 9223372036854775807%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_4294967296_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("and_int64 4294967296%s-9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_4294967296_ssa(-9223372036854775808); got != 0 { - fmt.Printf("and_int64 -9223372036854775808%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_4294967296_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("and_int64 4294967296%s-9223372036854775807 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_4294967296_ssa(-9223372036854775807); got != 0 { - fmt.Printf("and_int64 -9223372036854775807%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_4294967296_int64_ssa(-4294967296); got != 4294967296 { - fmt.Printf("and_int64 4294967296%s-4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_int64_4294967296_ssa(-4294967296); got != 4294967296 { - fmt.Printf("and_int64 -4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_4294967296_int64_ssa(-1); got != 4294967296 { - fmt.Printf("and_int64 4294967296%s-1 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_int64_4294967296_ssa(-1); got != 4294967296 { - fmt.Printf("and_int64 -1%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_4294967296_int64_ssa(0); got != 0 { - fmt.Printf("and_int64 4294967296%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_4294967296_ssa(0); got != 0 { - fmt.Printf("and_int64 0%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_4294967296_int64_ssa(1); got != 0 { - fmt.Printf("and_int64 4294967296%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_4294967296_ssa(1); got != 0 { - fmt.Printf("and_int64 1%s4294967296 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_4294967296_int64_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_int64 4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_int64_4294967296_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_int64 4294967296%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_4294967296_int64_ssa(9223372036854775806); got != 4294967296 { - fmt.Printf("and_int64 4294967296%s9223372036854775806 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_int64_4294967296_ssa(9223372036854775806); got != 4294967296 { - fmt.Printf("and_int64 9223372036854775806%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_4294967296_int64_ssa(9223372036854775807); got != 4294967296 { - fmt.Printf("and_int64 4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_int64_4294967296_ssa(9223372036854775807); got != 4294967296 { - fmt.Printf("and_int64 9223372036854775807%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_9223372036854775806_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("and_int64 9223372036854775806%s-9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775806_ssa(-9223372036854775808); got != 0 { - fmt.Printf("and_int64 -9223372036854775808%s9223372036854775806 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_9223372036854775806_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("and_int64 9223372036854775806%s-9223372036854775807 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775806_ssa(-9223372036854775807); got != 0 { - fmt.Printf("and_int64 -9223372036854775807%s9223372036854775806 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_9223372036854775806_int64_ssa(-4294967296); got != 9223372032559808512 { - fmt.Printf("and_int64 9223372036854775806%s-4294967296 = %d, wanted 9223372032559808512\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775806_ssa(-4294967296); got != 9223372032559808512 { - fmt.Printf("and_int64 -4294967296%s9223372036854775806 = %d, wanted 9223372032559808512\n", `&`, got) - failed = true - } - - if got := and_9223372036854775806_int64_ssa(-1); got != 9223372036854775806 { - fmt.Printf("and_int64 9223372036854775806%s-1 = %d, wanted 9223372036854775806\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775806_ssa(-1); got != 9223372036854775806 { - fmt.Printf("and_int64 -1%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) - failed = true - } - - if got := and_9223372036854775806_int64_ssa(0); got != 0 { - fmt.Printf("and_int64 9223372036854775806%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775806_ssa(0); got != 0 { - fmt.Printf("and_int64 0%s9223372036854775806 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_9223372036854775806_int64_ssa(1); got != 0 { - fmt.Printf("and_int64 9223372036854775806%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775806_ssa(1); got != 0 { - fmt.Printf("and_int64 1%s9223372036854775806 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_9223372036854775806_int64_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_int64 9223372036854775806%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775806_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_int64 4294967296%s9223372036854775806 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_9223372036854775806_int64_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("and_int64 9223372036854775806%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775806_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("and_int64 9223372036854775806%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) - failed = true - } - - if got := and_9223372036854775806_int64_ssa(9223372036854775807); got != 9223372036854775806 { - fmt.Printf("and_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775806\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775806_ssa(9223372036854775807); got != 9223372036854775806 { - fmt.Printf("and_int64 9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) - failed = true - } - - if got := and_9223372036854775807_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("and_int64 9223372036854775807%s-9223372036854775808 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775807_ssa(-9223372036854775808); got != 0 { - fmt.Printf("and_int64 -9223372036854775808%s9223372036854775807 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_9223372036854775807_int64_ssa(-9223372036854775807); got != 1 { - fmt.Printf("and_int64 9223372036854775807%s-9223372036854775807 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775807_ssa(-9223372036854775807); got != 1 { - fmt.Printf("and_int64 -9223372036854775807%s9223372036854775807 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_9223372036854775807_int64_ssa(-4294967296); got != 9223372032559808512 { - fmt.Printf("and_int64 9223372036854775807%s-4294967296 = %d, wanted 9223372032559808512\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775807_ssa(-4294967296); got != 9223372032559808512 { - fmt.Printf("and_int64 -4294967296%s9223372036854775807 = %d, wanted 9223372032559808512\n", `&`, got) - failed = true - } - - if got := and_9223372036854775807_int64_ssa(-1); got != 9223372036854775807 { - fmt.Printf("and_int64 9223372036854775807%s-1 = %d, wanted 9223372036854775807\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775807_ssa(-1); got != 9223372036854775807 { - fmt.Printf("and_int64 -1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `&`, got) - failed = true - } - - if got := and_9223372036854775807_int64_ssa(0); got != 0 { - fmt.Printf("and_int64 9223372036854775807%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775807_ssa(0); got != 0 { - fmt.Printf("and_int64 0%s9223372036854775807 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_9223372036854775807_int64_ssa(1); got != 1 { - fmt.Printf("and_int64 9223372036854775807%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775807_ssa(1); got != 1 { - fmt.Printf("and_int64 1%s9223372036854775807 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_9223372036854775807_int64_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_int64 9223372036854775807%s4294967296 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775807_ssa(4294967296); got != 4294967296 { - fmt.Printf("and_int64 4294967296%s9223372036854775807 = %d, wanted 4294967296\n", `&`, got) - failed = true - } - - if got := and_9223372036854775807_int64_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("and_int64 9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775806\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775807_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("and_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775806\n", `&`, got) - failed = true - } - - if got := and_9223372036854775807_int64_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("and_int64 9223372036854775807%s9223372036854775807 = %d, wanted 9223372036854775807\n", `&`, got) - failed = true - } - - if got := and_int64_9223372036854775807_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("and_int64 9223372036854775807%s9223372036854775807 = %d, wanted 9223372036854775807\n", `&`, got) - failed = true - } - - if got := or_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("or_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("or_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("or_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("or_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775808_int64_ssa(-4294967296); got != -4294967296 { - fmt.Printf("or_int64 -9223372036854775808%s-4294967296 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775808_ssa(-4294967296); got != -4294967296 { - fmt.Printf("or_int64 -4294967296%s-9223372036854775808 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775808_int64_ssa(-1); got != -1 { - fmt.Printf("or_int64 -9223372036854775808%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775808_ssa(-1); got != -1 { - fmt.Printf("or_int64 -1%s-9223372036854775808 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775808_int64_ssa(0); got != -9223372036854775808 { - fmt.Printf("or_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775808_ssa(0); got != -9223372036854775808 { - fmt.Printf("or_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775807 { - fmt.Printf("or_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775807 { - fmt.Printf("or_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775808_int64_ssa(4294967296); got != -9223372032559808512 { - fmt.Printf("or_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775808_ssa(4294967296); got != -9223372032559808512 { - fmt.Printf("or_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -2 { - fmt.Printf("or_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775808_ssa(9223372036854775806); got != -2 { - fmt.Printf("or_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { - fmt.Printf("or_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -1 { - fmt.Printf("or_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != -9223372036854775807 { - fmt.Printf("or_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != -9223372036854775807 { - fmt.Printf("or_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("or_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("or_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775807_int64_ssa(-4294967296); got != -4294967295 { - fmt.Printf("or_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967295\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775807_ssa(-4294967296); got != -4294967295 { - fmt.Printf("or_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967295\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775807_int64_ssa(-1); got != -1 { - fmt.Printf("or_int64 -9223372036854775807%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775807_ssa(-1); got != -1 { - fmt.Printf("or_int64 -1%s-9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775807_int64_ssa(0); got != -9223372036854775807 { - fmt.Printf("or_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775807_ssa(0); got != -9223372036854775807 { - fmt.Printf("or_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775807 { - fmt.Printf("or_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775807 { - fmt.Printf("or_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775807_int64_ssa(4294967296); got != -9223372032559808511 { - fmt.Printf("or_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775807_ssa(4294967296); got != -9223372032559808511 { - fmt.Printf("or_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { - fmt.Printf("or_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775807_ssa(9223372036854775806); got != -1 { - fmt.Printf("or_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg9223372036854775807_int64_ssa(9223372036854775807); got != -1 { - fmt.Printf("or_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -1 { - fmt.Printf("or_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg4294967296_int64_ssa(-9223372036854775808); got != -4294967296 { - fmt.Printf("or_int64 -4294967296%s-9223372036854775808 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_int64_Neg4294967296_ssa(-9223372036854775808); got != -4294967296 { - fmt.Printf("or_int64 -9223372036854775808%s-4294967296 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_Neg4294967296_int64_ssa(-9223372036854775807); got != -4294967295 { - fmt.Printf("or_int64 -4294967296%s-9223372036854775807 = %d, wanted -4294967295\n", `|`, got) - failed = true - } - - if got := or_int64_Neg4294967296_ssa(-9223372036854775807); got != -4294967295 { - fmt.Printf("or_int64 -9223372036854775807%s-4294967296 = %d, wanted -4294967295\n", `|`, got) - failed = true - } - - if got := or_Neg4294967296_int64_ssa(-4294967296); got != -4294967296 { - fmt.Printf("or_int64 -4294967296%s-4294967296 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_int64_Neg4294967296_ssa(-4294967296); got != -4294967296 { - fmt.Printf("or_int64 -4294967296%s-4294967296 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_Neg4294967296_int64_ssa(-1); got != -1 { - fmt.Printf("or_int64 -4294967296%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg4294967296_ssa(-1); got != -1 { - fmt.Printf("or_int64 -1%s-4294967296 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg4294967296_int64_ssa(0); got != -4294967296 { - fmt.Printf("or_int64 -4294967296%s0 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_int64_Neg4294967296_ssa(0); got != -4294967296 { - fmt.Printf("or_int64 0%s-4294967296 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_Neg4294967296_int64_ssa(1); got != -4294967295 { - fmt.Printf("or_int64 -4294967296%s1 = %d, wanted -4294967295\n", `|`, got) - failed = true - } - - if got := or_int64_Neg4294967296_ssa(1); got != -4294967295 { - fmt.Printf("or_int64 1%s-4294967296 = %d, wanted -4294967295\n", `|`, got) - failed = true - } - - if got := or_Neg4294967296_int64_ssa(4294967296); got != -4294967296 { - fmt.Printf("or_int64 -4294967296%s4294967296 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_int64_Neg4294967296_ssa(4294967296); got != -4294967296 { - fmt.Printf("or_int64 4294967296%s-4294967296 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_Neg4294967296_int64_ssa(9223372036854775806); got != -2 { - fmt.Printf("or_int64 -4294967296%s9223372036854775806 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_int64_Neg4294967296_ssa(9223372036854775806); got != -2 { - fmt.Printf("or_int64 9223372036854775806%s-4294967296 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_Neg4294967296_int64_ssa(9223372036854775807); got != -1 { - fmt.Printf("or_int64 -4294967296%s9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg4294967296_ssa(9223372036854775807); got != -1 { - fmt.Printf("or_int64 9223372036854775807%s-4294967296 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int64_ssa(-9223372036854775808); got != -1 { - fmt.Printf("or_int64 -1%s-9223372036854775808 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg1_ssa(-9223372036854775808); got != -1 { - fmt.Printf("or_int64 -9223372036854775808%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int64_ssa(-9223372036854775807); got != -1 { - fmt.Printf("or_int64 -1%s-9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg1_ssa(-9223372036854775807); got != -1 { - fmt.Printf("or_int64 -9223372036854775807%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int64_ssa(-4294967296); got != -1 { - fmt.Printf("or_int64 -1%s-4294967296 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg1_ssa(-4294967296); got != -1 { - fmt.Printf("or_int64 -4294967296%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int64_ssa(-1); got != -1 { - fmt.Printf("or_int64 -1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg1_ssa(-1); got != -1 { - fmt.Printf("or_int64 -1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int64_ssa(0); got != -1 { - fmt.Printf("or_int64 -1%s0 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg1_ssa(0); got != -1 { - fmt.Printf("or_int64 0%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int64_ssa(1); got != -1 { - fmt.Printf("or_int64 -1%s1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg1_ssa(1); got != -1 { - fmt.Printf("or_int64 1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int64_ssa(4294967296); got != -1 { - fmt.Printf("or_int64 -1%s4294967296 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg1_ssa(4294967296); got != -1 { - fmt.Printf("or_int64 4294967296%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int64_ssa(9223372036854775806); got != -1 { - fmt.Printf("or_int64 -1%s9223372036854775806 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg1_ssa(9223372036854775806); got != -1 { - fmt.Printf("or_int64 9223372036854775806%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int64_ssa(9223372036854775807); got != -1 { - fmt.Printf("or_int64 -1%s9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_Neg1_ssa(9223372036854775807); got != -1 { - fmt.Printf("or_int64 9223372036854775807%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_0_int64_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("or_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `|`, got) - failed = true - } - - if got := or_int64_0_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("or_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `|`, got) - failed = true - } - - if got := or_0_int64_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("or_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_0_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("or_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_0_int64_ssa(-4294967296); got != -4294967296 { - fmt.Printf("or_int64 0%s-4294967296 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_int64_0_ssa(-4294967296); got != -4294967296 { - fmt.Printf("or_int64 -4294967296%s0 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_0_int64_ssa(-1); got != -1 { - fmt.Printf("or_int64 0%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_0_ssa(-1); got != -1 { - fmt.Printf("or_int64 -1%s0 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_0_int64_ssa(0); got != 0 { - fmt.Printf("or_int64 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_int64_0_ssa(0); got != 0 { - fmt.Printf("or_int64 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_0_int64_ssa(1); got != 1 { - fmt.Printf("or_int64 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_int64_0_ssa(1); got != 1 { - fmt.Printf("or_int64 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_0_int64_ssa(4294967296); got != 4294967296 { - fmt.Printf("or_int64 0%s4294967296 = %d, wanted 4294967296\n", `|`, got) - failed = true - } - - if got := or_int64_0_ssa(4294967296); got != 4294967296 { - fmt.Printf("or_int64 4294967296%s0 = %d, wanted 4294967296\n", `|`, got) - failed = true - } - - if got := or_0_int64_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("or_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) - failed = true - } - - if got := or_int64_0_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("or_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `|`, got) - failed = true - } - - if got := or_0_int64_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("or_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_0_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_1_int64_ssa(-9223372036854775808); got != -9223372036854775807 { - fmt.Printf("or_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_1_ssa(-9223372036854775808); got != -9223372036854775807 { - fmt.Printf("or_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_1_int64_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("or_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_1_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("or_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_1_int64_ssa(-4294967296); got != -4294967295 { - fmt.Printf("or_int64 1%s-4294967296 = %d, wanted -4294967295\n", `|`, got) - failed = true - } - - if got := or_int64_1_ssa(-4294967296); got != -4294967295 { - fmt.Printf("or_int64 -4294967296%s1 = %d, wanted -4294967295\n", `|`, got) - failed = true - } - - if got := or_1_int64_ssa(-1); got != -1 { - fmt.Printf("or_int64 1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_1_ssa(-1); got != -1 { - fmt.Printf("or_int64 -1%s1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_1_int64_ssa(0); got != 1 { - fmt.Printf("or_int64 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_int64_1_ssa(0); got != 1 { - fmt.Printf("or_int64 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_int64_ssa(1); got != 1 { - fmt.Printf("or_int64 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_int64_1_ssa(1); got != 1 { - fmt.Printf("or_int64 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_int64_ssa(4294967296); got != 4294967297 { - fmt.Printf("or_int64 1%s4294967296 = %d, wanted 4294967297\n", `|`, got) - failed = true - } - - if got := or_int64_1_ssa(4294967296); got != 4294967297 { - fmt.Printf("or_int64 4294967296%s1 = %d, wanted 4294967297\n", `|`, got) - failed = true - } - - if got := or_1_int64_ssa(9223372036854775806); got != 9223372036854775807 { - fmt.Printf("or_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_1_ssa(9223372036854775806); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_1_int64_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("or_int64 1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_1_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_4294967296_int64_ssa(-9223372036854775808); got != -9223372032559808512 { - fmt.Printf("or_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `|`, got) - failed = true - } - - if got := or_int64_4294967296_ssa(-9223372036854775808); got != -9223372032559808512 { - fmt.Printf("or_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `|`, got) - failed = true - } - - if got := or_4294967296_int64_ssa(-9223372036854775807); got != -9223372032559808511 { - fmt.Printf("or_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `|`, got) - failed = true - } - - if got := or_int64_4294967296_ssa(-9223372036854775807); got != -9223372032559808511 { - fmt.Printf("or_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `|`, got) - failed = true - } - - if got := or_4294967296_int64_ssa(-4294967296); got != -4294967296 { - fmt.Printf("or_int64 4294967296%s-4294967296 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_int64_4294967296_ssa(-4294967296); got != -4294967296 { - fmt.Printf("or_int64 -4294967296%s4294967296 = %d, wanted -4294967296\n", `|`, got) - failed = true - } - - if got := or_4294967296_int64_ssa(-1); got != -1 { - fmt.Printf("or_int64 4294967296%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_4294967296_ssa(-1); got != -1 { - fmt.Printf("or_int64 -1%s4294967296 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_4294967296_int64_ssa(0); got != 4294967296 { - fmt.Printf("or_int64 4294967296%s0 = %d, wanted 4294967296\n", `|`, got) - failed = true - } - - if got := or_int64_4294967296_ssa(0); got != 4294967296 { - fmt.Printf("or_int64 0%s4294967296 = %d, wanted 4294967296\n", `|`, got) - failed = true - } - - if got := or_4294967296_int64_ssa(1); got != 4294967297 { - fmt.Printf("or_int64 4294967296%s1 = %d, wanted 4294967297\n", `|`, got) - failed = true - } - - if got := or_int64_4294967296_ssa(1); got != 4294967297 { - fmt.Printf("or_int64 1%s4294967296 = %d, wanted 4294967297\n", `|`, got) - failed = true - } - - if got := or_4294967296_int64_ssa(4294967296); got != 4294967296 { - fmt.Printf("or_int64 4294967296%s4294967296 = %d, wanted 4294967296\n", `|`, got) - failed = true - } - - if got := or_int64_4294967296_ssa(4294967296); got != 4294967296 { - fmt.Printf("or_int64 4294967296%s4294967296 = %d, wanted 4294967296\n", `|`, got) - failed = true - } - - if got := or_4294967296_int64_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("or_int64 4294967296%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) - failed = true - } - - if got := or_int64_4294967296_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("or_int64 9223372036854775806%s4294967296 = %d, wanted 9223372036854775806\n", `|`, got) - failed = true - } - - if got := or_4294967296_int64_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("or_int64 4294967296%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_4294967296_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775807%s4294967296 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_9223372036854775806_int64_ssa(-9223372036854775808); got != -2 { - fmt.Printf("or_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775806_ssa(-9223372036854775808); got != -2 { - fmt.Printf("or_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_9223372036854775806_int64_ssa(-9223372036854775807); got != -1 { - fmt.Printf("or_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { - fmt.Printf("or_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_9223372036854775806_int64_ssa(-4294967296); got != -2 { - fmt.Printf("or_int64 9223372036854775806%s-4294967296 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775806_ssa(-4294967296); got != -2 { - fmt.Printf("or_int64 -4294967296%s9223372036854775806 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_9223372036854775806_int64_ssa(-1); got != -1 { - fmt.Printf("or_int64 9223372036854775806%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775806_ssa(-1); got != -1 { - fmt.Printf("or_int64 -1%s9223372036854775806 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_9223372036854775806_int64_ssa(0); got != 9223372036854775806 { - fmt.Printf("or_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775806_ssa(0); got != 9223372036854775806 { - fmt.Printf("or_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) - failed = true - } - - if got := or_9223372036854775806_int64_ssa(1); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775806_ssa(1); got != 9223372036854775807 { - fmt.Printf("or_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_9223372036854775806_int64_ssa(4294967296); got != 9223372036854775806 { - fmt.Printf("or_int64 9223372036854775806%s4294967296 = %d, wanted 9223372036854775806\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775806_ssa(4294967296); got != 9223372036854775806 { - fmt.Printf("or_int64 4294967296%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) - failed = true - } - - if got := or_9223372036854775806_int64_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("or_int64 9223372036854775806%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775806_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("or_int64 9223372036854775806%s9223372036854775806 = %d, wanted 9223372036854775806\n", `|`, got) - failed = true - } - - if got := or_9223372036854775806_int64_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775806_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_9223372036854775807_int64_ssa(-9223372036854775808); got != -1 { - fmt.Printf("or_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { - fmt.Printf("or_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_9223372036854775807_int64_ssa(-9223372036854775807); got != -1 { - fmt.Printf("or_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775807_ssa(-9223372036854775807); got != -1 { - fmt.Printf("or_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_9223372036854775807_int64_ssa(-4294967296); got != -1 { - fmt.Printf("or_int64 9223372036854775807%s-4294967296 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775807_ssa(-4294967296); got != -1 { - fmt.Printf("or_int64 -4294967296%s9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_9223372036854775807_int64_ssa(-1); got != -1 { - fmt.Printf("or_int64 9223372036854775807%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775807_ssa(-1); got != -1 { - fmt.Printf("or_int64 -1%s9223372036854775807 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_9223372036854775807_int64_ssa(0); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775807_ssa(0); got != 9223372036854775807 { - fmt.Printf("or_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_9223372036854775807_int64_ssa(1); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775807%s1 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775807_ssa(1); got != 9223372036854775807 { - fmt.Printf("or_int64 1%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_9223372036854775807_int64_ssa(4294967296); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775807%s4294967296 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775807_ssa(4294967296); got != 9223372036854775807 { - fmt.Printf("or_int64 4294967296%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_9223372036854775807_int64_ssa(9223372036854775806); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775807%s9223372036854775806 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775807_ssa(9223372036854775806); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775806%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_9223372036854775807_int64_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775807%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := or_int64_9223372036854775807_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("or_int64 9223372036854775807%s9223372036854775807 = %d, wanted 9223372036854775807\n", `|`, got) - failed = true - } - - if got := xor_Neg9223372036854775808_int64_ssa(-9223372036854775808); got != 0 { - fmt.Printf("xor_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775808_ssa(-9223372036854775808); got != 0 { - fmt.Printf("xor_int64 -9223372036854775808%s-9223372036854775808 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775808_int64_ssa(-9223372036854775807); got != 1 { - fmt.Printf("xor_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775808_ssa(-9223372036854775807); got != 1 { - fmt.Printf("xor_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775808_int64_ssa(-4294967296); got != 9223372032559808512 { - fmt.Printf("xor_int64 -9223372036854775808%s-4294967296 = %d, wanted 9223372032559808512\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775808_ssa(-4294967296); got != 9223372032559808512 { - fmt.Printf("xor_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775808_int64_ssa(-1); got != 9223372036854775807 { - fmt.Printf("xor_int64 -9223372036854775808%s-1 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775808_ssa(-1); got != 9223372036854775807 { - fmt.Printf("xor_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775808_int64_ssa(0); got != -9223372036854775808 { - fmt.Printf("xor_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775808_ssa(0); got != -9223372036854775808 { - fmt.Printf("xor_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775808_int64_ssa(1); got != -9223372036854775807 { - fmt.Printf("xor_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775808_ssa(1); got != -9223372036854775807 { - fmt.Printf("xor_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775808_int64_ssa(4294967296); got != -9223372032559808512 { - fmt.Printf("xor_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775808_ssa(4294967296); got != -9223372032559808512 { - fmt.Printf("xor_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775808_int64_ssa(9223372036854775806); got != -2 { - fmt.Printf("xor_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775808_ssa(9223372036854775806); got != -2 { - fmt.Printf("xor_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775808_int64_ssa(9223372036854775807); got != -1 { - fmt.Printf("xor_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775808_ssa(9223372036854775807); got != -1 { - fmt.Printf("xor_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775807_int64_ssa(-9223372036854775808); got != 1 { - fmt.Printf("xor_int64 -9223372036854775807%s-9223372036854775808 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775807_ssa(-9223372036854775808); got != 1 { - fmt.Printf("xor_int64 -9223372036854775808%s-9223372036854775807 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775807_int64_ssa(-9223372036854775807); got != 0 { - fmt.Printf("xor_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775807_ssa(-9223372036854775807); got != 0 { - fmt.Printf("xor_int64 -9223372036854775807%s-9223372036854775807 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775807_int64_ssa(-4294967296); got != 9223372032559808513 { - fmt.Printf("xor_int64 -9223372036854775807%s-4294967296 = %d, wanted 9223372032559808513\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775807_ssa(-4294967296); got != 9223372032559808513 { - fmt.Printf("xor_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808513\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775807_int64_ssa(-1); got != 9223372036854775806 { - fmt.Printf("xor_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775806\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775807_ssa(-1); got != 9223372036854775806 { - fmt.Printf("xor_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775807_int64_ssa(0); got != -9223372036854775807 { - fmt.Printf("xor_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775807_ssa(0); got != -9223372036854775807 { - fmt.Printf("xor_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775807_int64_ssa(1); got != -9223372036854775808 { - fmt.Printf("xor_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775807_ssa(1); got != -9223372036854775808 { - fmt.Printf("xor_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775807_int64_ssa(4294967296); got != -9223372032559808511 { - fmt.Printf("xor_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775807_ssa(4294967296); got != -9223372032559808511 { - fmt.Printf("xor_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775807_int64_ssa(9223372036854775806); got != -1 { - fmt.Printf("xor_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775807_ssa(9223372036854775806); got != -1 { - fmt.Printf("xor_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_Neg9223372036854775807_int64_ssa(9223372036854775807); got != -2 { - fmt.Printf("xor_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg9223372036854775807_ssa(9223372036854775807); got != -2 { - fmt.Printf("xor_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_Neg4294967296_int64_ssa(-9223372036854775808); got != 9223372032559808512 { - fmt.Printf("xor_int64 -4294967296%s-9223372036854775808 = %d, wanted 9223372032559808512\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg4294967296_ssa(-9223372036854775808); got != 9223372032559808512 { - fmt.Printf("xor_int64 -9223372036854775808%s-4294967296 = %d, wanted 9223372032559808512\n", `^`, got) - failed = true - } - - if got := xor_Neg4294967296_int64_ssa(-9223372036854775807); got != 9223372032559808513 { - fmt.Printf("xor_int64 -4294967296%s-9223372036854775807 = %d, wanted 9223372032559808513\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg4294967296_ssa(-9223372036854775807); got != 9223372032559808513 { - fmt.Printf("xor_int64 -9223372036854775807%s-4294967296 = %d, wanted 9223372032559808513\n", `^`, got) - failed = true - } - - if got := xor_Neg4294967296_int64_ssa(-4294967296); got != 0 { - fmt.Printf("xor_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg4294967296_ssa(-4294967296); got != 0 { - fmt.Printf("xor_int64 -4294967296%s-4294967296 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_Neg4294967296_int64_ssa(-1); got != 4294967295 { - fmt.Printf("xor_int64 -4294967296%s-1 = %d, wanted 4294967295\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg4294967296_ssa(-1); got != 4294967295 { - fmt.Printf("xor_int64 -1%s-4294967296 = %d, wanted 4294967295\n", `^`, got) - failed = true - } - - if got := xor_Neg4294967296_int64_ssa(0); got != -4294967296 { - fmt.Printf("xor_int64 -4294967296%s0 = %d, wanted -4294967296\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg4294967296_ssa(0); got != -4294967296 { - fmt.Printf("xor_int64 0%s-4294967296 = %d, wanted -4294967296\n", `^`, got) - failed = true - } - - if got := xor_Neg4294967296_int64_ssa(1); got != -4294967295 { - fmt.Printf("xor_int64 -4294967296%s1 = %d, wanted -4294967295\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg4294967296_ssa(1); got != -4294967295 { - fmt.Printf("xor_int64 1%s-4294967296 = %d, wanted -4294967295\n", `^`, got) - failed = true - } - - if got := xor_Neg4294967296_int64_ssa(4294967296); got != -8589934592 { - fmt.Printf("xor_int64 -4294967296%s4294967296 = %d, wanted -8589934592\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg4294967296_ssa(4294967296); got != -8589934592 { - fmt.Printf("xor_int64 4294967296%s-4294967296 = %d, wanted -8589934592\n", `^`, got) - failed = true - } - - if got := xor_Neg4294967296_int64_ssa(9223372036854775806); got != -9223372032559808514 { - fmt.Printf("xor_int64 -4294967296%s9223372036854775806 = %d, wanted -9223372032559808514\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg4294967296_ssa(9223372036854775806); got != -9223372032559808514 { - fmt.Printf("xor_int64 9223372036854775806%s-4294967296 = %d, wanted -9223372032559808514\n", `^`, got) - failed = true - } - - if got := xor_Neg4294967296_int64_ssa(9223372036854775807); got != -9223372032559808513 { - fmt.Printf("xor_int64 -4294967296%s9223372036854775807 = %d, wanted -9223372032559808513\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg4294967296_ssa(9223372036854775807); got != -9223372032559808513 { - fmt.Printf("xor_int64 9223372036854775807%s-4294967296 = %d, wanted -9223372032559808513\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int64_ssa(-9223372036854775808); got != 9223372036854775807 { - fmt.Printf("xor_int64 -1%s-9223372036854775808 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg1_ssa(-9223372036854775808); got != 9223372036854775807 { - fmt.Printf("xor_int64 -9223372036854775808%s-1 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int64_ssa(-9223372036854775807); got != 9223372036854775806 { - fmt.Printf("xor_int64 -1%s-9223372036854775807 = %d, wanted 9223372036854775806\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg1_ssa(-9223372036854775807); got != 9223372036854775806 { - fmt.Printf("xor_int64 -9223372036854775807%s-1 = %d, wanted 9223372036854775806\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int64_ssa(-4294967296); got != 4294967295 { - fmt.Printf("xor_int64 -1%s-4294967296 = %d, wanted 4294967295\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg1_ssa(-4294967296); got != 4294967295 { - fmt.Printf("xor_int64 -4294967296%s-1 = %d, wanted 4294967295\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int64_ssa(-1); got != 0 { - fmt.Printf("xor_int64 -1%s-1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg1_ssa(-1); got != 0 { - fmt.Printf("xor_int64 -1%s-1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int64_ssa(0); got != -1 { - fmt.Printf("xor_int64 -1%s0 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg1_ssa(0); got != -1 { - fmt.Printf("xor_int64 0%s-1 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int64_ssa(1); got != -2 { - fmt.Printf("xor_int64 -1%s1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg1_ssa(1); got != -2 { - fmt.Printf("xor_int64 1%s-1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int64_ssa(4294967296); got != -4294967297 { - fmt.Printf("xor_int64 -1%s4294967296 = %d, wanted -4294967297\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg1_ssa(4294967296); got != -4294967297 { - fmt.Printf("xor_int64 4294967296%s-1 = %d, wanted -4294967297\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int64_ssa(9223372036854775806); got != -9223372036854775807 { - fmt.Printf("xor_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg1_ssa(9223372036854775806); got != -9223372036854775807 { - fmt.Printf("xor_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int64_ssa(9223372036854775807); got != -9223372036854775808 { - fmt.Printf("xor_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_int64_Neg1_ssa(9223372036854775807); got != -9223372036854775808 { - fmt.Printf("xor_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_0_int64_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("xor_int64 0%s-9223372036854775808 = %d, wanted -9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_int64_0_ssa(-9223372036854775808); got != -9223372036854775808 { - fmt.Printf("xor_int64 -9223372036854775808%s0 = %d, wanted -9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_0_int64_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("xor_int64 0%s-9223372036854775807 = %d, wanted -9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_int64_0_ssa(-9223372036854775807); got != -9223372036854775807 { - fmt.Printf("xor_int64 -9223372036854775807%s0 = %d, wanted -9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_0_int64_ssa(-4294967296); got != -4294967296 { - fmt.Printf("xor_int64 0%s-4294967296 = %d, wanted -4294967296\n", `^`, got) - failed = true - } - - if got := xor_int64_0_ssa(-4294967296); got != -4294967296 { - fmt.Printf("xor_int64 -4294967296%s0 = %d, wanted -4294967296\n", `^`, got) - failed = true - } - - if got := xor_0_int64_ssa(-1); got != -1 { - fmt.Printf("xor_int64 0%s-1 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int64_0_ssa(-1); got != -1 { - fmt.Printf("xor_int64 -1%s0 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_0_int64_ssa(0); got != 0 { - fmt.Printf("xor_int64 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int64_0_ssa(0); got != 0 { - fmt.Printf("xor_int64 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_0_int64_ssa(1); got != 1 { - fmt.Printf("xor_int64 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int64_0_ssa(1); got != 1 { - fmt.Printf("xor_int64 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_0_int64_ssa(4294967296); got != 4294967296 { - fmt.Printf("xor_int64 0%s4294967296 = %d, wanted 4294967296\n", `^`, got) - failed = true - } - - if got := xor_int64_0_ssa(4294967296); got != 4294967296 { - fmt.Printf("xor_int64 4294967296%s0 = %d, wanted 4294967296\n", `^`, got) - failed = true - } - - if got := xor_0_int64_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("xor_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `^`, got) - failed = true - } - - if got := xor_int64_0_ssa(9223372036854775806); got != 9223372036854775806 { - fmt.Printf("xor_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `^`, got) - failed = true - } - - if got := xor_0_int64_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("xor_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_int64_0_ssa(9223372036854775807); got != 9223372036854775807 { - fmt.Printf("xor_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_1_int64_ssa(-9223372036854775808); got != -9223372036854775807 { - fmt.Printf("xor_int64 1%s-9223372036854775808 = %d, wanted -9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_int64_1_ssa(-9223372036854775808); got != -9223372036854775807 { - fmt.Printf("xor_int64 -9223372036854775808%s1 = %d, wanted -9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_1_int64_ssa(-9223372036854775807); got != -9223372036854775808 { - fmt.Printf("xor_int64 1%s-9223372036854775807 = %d, wanted -9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_int64_1_ssa(-9223372036854775807); got != -9223372036854775808 { - fmt.Printf("xor_int64 -9223372036854775807%s1 = %d, wanted -9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_1_int64_ssa(-4294967296); got != -4294967295 { - fmt.Printf("xor_int64 1%s-4294967296 = %d, wanted -4294967295\n", `^`, got) - failed = true - } - - if got := xor_int64_1_ssa(-4294967296); got != -4294967295 { - fmt.Printf("xor_int64 -4294967296%s1 = %d, wanted -4294967295\n", `^`, got) - failed = true - } - - if got := xor_1_int64_ssa(-1); got != -2 { - fmt.Printf("xor_int64 1%s-1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int64_1_ssa(-1); got != -2 { - fmt.Printf("xor_int64 -1%s1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_1_int64_ssa(0); got != 1 { - fmt.Printf("xor_int64 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int64_1_ssa(0); got != 1 { - fmt.Printf("xor_int64 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_1_int64_ssa(1); got != 0 { - fmt.Printf("xor_int64 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int64_1_ssa(1); got != 0 { - fmt.Printf("xor_int64 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_1_int64_ssa(4294967296); got != 4294967297 { - fmt.Printf("xor_int64 1%s4294967296 = %d, wanted 4294967297\n", `^`, got) - failed = true - } - - if got := xor_int64_1_ssa(4294967296); got != 4294967297 { - fmt.Printf("xor_int64 4294967296%s1 = %d, wanted 4294967297\n", `^`, got) - failed = true - } - - if got := xor_1_int64_ssa(9223372036854775806); got != 9223372036854775807 { - fmt.Printf("xor_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_int64_1_ssa(9223372036854775806); got != 9223372036854775807 { - fmt.Printf("xor_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_1_int64_ssa(9223372036854775807); got != 9223372036854775806 { - fmt.Printf("xor_int64 1%s9223372036854775807 = %d, wanted 9223372036854775806\n", `^`, got) - failed = true - } - - if got := xor_int64_1_ssa(9223372036854775807); got != 9223372036854775806 { - fmt.Printf("xor_int64 9223372036854775807%s1 = %d, wanted 9223372036854775806\n", `^`, got) - failed = true - } - - if got := xor_4294967296_int64_ssa(-9223372036854775808); got != -9223372032559808512 { - fmt.Printf("xor_int64 4294967296%s-9223372036854775808 = %d, wanted -9223372032559808512\n", `^`, got) - failed = true - } - - if got := xor_int64_4294967296_ssa(-9223372036854775808); got != -9223372032559808512 { - fmt.Printf("xor_int64 -9223372036854775808%s4294967296 = %d, wanted -9223372032559808512\n", `^`, got) - failed = true - } - - if got := xor_4294967296_int64_ssa(-9223372036854775807); got != -9223372032559808511 { - fmt.Printf("xor_int64 4294967296%s-9223372036854775807 = %d, wanted -9223372032559808511\n", `^`, got) - failed = true - } - - if got := xor_int64_4294967296_ssa(-9223372036854775807); got != -9223372032559808511 { - fmt.Printf("xor_int64 -9223372036854775807%s4294967296 = %d, wanted -9223372032559808511\n", `^`, got) - failed = true - } - - if got := xor_4294967296_int64_ssa(-4294967296); got != -8589934592 { - fmt.Printf("xor_int64 4294967296%s-4294967296 = %d, wanted -8589934592\n", `^`, got) - failed = true - } - - if got := xor_int64_4294967296_ssa(-4294967296); got != -8589934592 { - fmt.Printf("xor_int64 -4294967296%s4294967296 = %d, wanted -8589934592\n", `^`, got) - failed = true - } - - if got := xor_4294967296_int64_ssa(-1); got != -4294967297 { - fmt.Printf("xor_int64 4294967296%s-1 = %d, wanted -4294967297\n", `^`, got) - failed = true - } - - if got := xor_int64_4294967296_ssa(-1); got != -4294967297 { - fmt.Printf("xor_int64 -1%s4294967296 = %d, wanted -4294967297\n", `^`, got) - failed = true - } - - if got := xor_4294967296_int64_ssa(0); got != 4294967296 { - fmt.Printf("xor_int64 4294967296%s0 = %d, wanted 4294967296\n", `^`, got) - failed = true - } - - if got := xor_int64_4294967296_ssa(0); got != 4294967296 { - fmt.Printf("xor_int64 0%s4294967296 = %d, wanted 4294967296\n", `^`, got) - failed = true - } - - if got := xor_4294967296_int64_ssa(1); got != 4294967297 { - fmt.Printf("xor_int64 4294967296%s1 = %d, wanted 4294967297\n", `^`, got) - failed = true - } - - if got := xor_int64_4294967296_ssa(1); got != 4294967297 { - fmt.Printf("xor_int64 1%s4294967296 = %d, wanted 4294967297\n", `^`, got) - failed = true - } - - if got := xor_4294967296_int64_ssa(4294967296); got != 0 { - fmt.Printf("xor_int64 4294967296%s4294967296 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int64_4294967296_ssa(4294967296); got != 0 { - fmt.Printf("xor_int64 4294967296%s4294967296 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_4294967296_int64_ssa(9223372036854775806); got != 9223372032559808510 { - fmt.Printf("xor_int64 4294967296%s9223372036854775806 = %d, wanted 9223372032559808510\n", `^`, got) - failed = true - } - - if got := xor_int64_4294967296_ssa(9223372036854775806); got != 9223372032559808510 { - fmt.Printf("xor_int64 9223372036854775806%s4294967296 = %d, wanted 9223372032559808510\n", `^`, got) - failed = true - } - - if got := xor_4294967296_int64_ssa(9223372036854775807); got != 9223372032559808511 { - fmt.Printf("xor_int64 4294967296%s9223372036854775807 = %d, wanted 9223372032559808511\n", `^`, got) - failed = true - } - - if got := xor_int64_4294967296_ssa(9223372036854775807); got != 9223372032559808511 { - fmt.Printf("xor_int64 9223372036854775807%s4294967296 = %d, wanted 9223372032559808511\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775806_int64_ssa(-9223372036854775808); got != -2 { - fmt.Printf("xor_int64 9223372036854775806%s-9223372036854775808 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775806_ssa(-9223372036854775808); got != -2 { - fmt.Printf("xor_int64 -9223372036854775808%s9223372036854775806 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775806_int64_ssa(-9223372036854775807); got != -1 { - fmt.Printf("xor_int64 9223372036854775806%s-9223372036854775807 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775806_ssa(-9223372036854775807); got != -1 { - fmt.Printf("xor_int64 -9223372036854775807%s9223372036854775806 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775806_int64_ssa(-4294967296); got != -9223372032559808514 { - fmt.Printf("xor_int64 9223372036854775806%s-4294967296 = %d, wanted -9223372032559808514\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775806_ssa(-4294967296); got != -9223372032559808514 { - fmt.Printf("xor_int64 -4294967296%s9223372036854775806 = %d, wanted -9223372032559808514\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775806_int64_ssa(-1); got != -9223372036854775807 { - fmt.Printf("xor_int64 9223372036854775806%s-1 = %d, wanted -9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775806_ssa(-1); got != -9223372036854775807 { - fmt.Printf("xor_int64 -1%s9223372036854775806 = %d, wanted -9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775806_int64_ssa(0); got != 9223372036854775806 { - fmt.Printf("xor_int64 9223372036854775806%s0 = %d, wanted 9223372036854775806\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775806_ssa(0); got != 9223372036854775806 { - fmt.Printf("xor_int64 0%s9223372036854775806 = %d, wanted 9223372036854775806\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775806_int64_ssa(1); got != 9223372036854775807 { - fmt.Printf("xor_int64 9223372036854775806%s1 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775806_ssa(1); got != 9223372036854775807 { - fmt.Printf("xor_int64 1%s9223372036854775806 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775806_int64_ssa(4294967296); got != 9223372032559808510 { - fmt.Printf("xor_int64 9223372036854775806%s4294967296 = %d, wanted 9223372032559808510\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775806_ssa(4294967296); got != 9223372032559808510 { - fmt.Printf("xor_int64 4294967296%s9223372036854775806 = %d, wanted 9223372032559808510\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775806_int64_ssa(9223372036854775806); got != 0 { - fmt.Printf("xor_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775806_ssa(9223372036854775806); got != 0 { - fmt.Printf("xor_int64 9223372036854775806%s9223372036854775806 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775806_int64_ssa(9223372036854775807); got != 1 { - fmt.Printf("xor_int64 9223372036854775806%s9223372036854775807 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775806_ssa(9223372036854775807); got != 1 { - fmt.Printf("xor_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775807_int64_ssa(-9223372036854775808); got != -1 { - fmt.Printf("xor_int64 9223372036854775807%s-9223372036854775808 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775807_ssa(-9223372036854775808); got != -1 { - fmt.Printf("xor_int64 -9223372036854775808%s9223372036854775807 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775807_int64_ssa(-9223372036854775807); got != -2 { - fmt.Printf("xor_int64 9223372036854775807%s-9223372036854775807 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775807_ssa(-9223372036854775807); got != -2 { - fmt.Printf("xor_int64 -9223372036854775807%s9223372036854775807 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775807_int64_ssa(-4294967296); got != -9223372032559808513 { - fmt.Printf("xor_int64 9223372036854775807%s-4294967296 = %d, wanted -9223372032559808513\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775807_ssa(-4294967296); got != -9223372032559808513 { - fmt.Printf("xor_int64 -4294967296%s9223372036854775807 = %d, wanted -9223372032559808513\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775807_int64_ssa(-1); got != -9223372036854775808 { - fmt.Printf("xor_int64 9223372036854775807%s-1 = %d, wanted -9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775807_ssa(-1); got != -9223372036854775808 { - fmt.Printf("xor_int64 -1%s9223372036854775807 = %d, wanted -9223372036854775808\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775807_int64_ssa(0); got != 9223372036854775807 { - fmt.Printf("xor_int64 9223372036854775807%s0 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775807_ssa(0); got != 9223372036854775807 { - fmt.Printf("xor_int64 0%s9223372036854775807 = %d, wanted 9223372036854775807\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775807_int64_ssa(1); got != 9223372036854775806 { - fmt.Printf("xor_int64 9223372036854775807%s1 = %d, wanted 9223372036854775806\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775807_ssa(1); got != 9223372036854775806 { - fmt.Printf("xor_int64 1%s9223372036854775807 = %d, wanted 9223372036854775806\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775807_int64_ssa(4294967296); got != 9223372032559808511 { - fmt.Printf("xor_int64 9223372036854775807%s4294967296 = %d, wanted 9223372032559808511\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775807_ssa(4294967296); got != 9223372032559808511 { - fmt.Printf("xor_int64 4294967296%s9223372036854775807 = %d, wanted 9223372032559808511\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775807_int64_ssa(9223372036854775806); got != 1 { - fmt.Printf("xor_int64 9223372036854775807%s9223372036854775806 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775807_ssa(9223372036854775806); got != 1 { - fmt.Printf("xor_int64 9223372036854775806%s9223372036854775807 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_9223372036854775807_int64_ssa(9223372036854775807); got != 0 { - fmt.Printf("xor_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int64_9223372036854775807_ssa(9223372036854775807); got != 0 { - fmt.Printf("xor_int64 9223372036854775807%s9223372036854775807 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := add_0_uint32_ssa(0); got != 0 { - fmt.Printf("add_uint32 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_uint32_0_ssa(0); got != 0 { - fmt.Printf("add_uint32 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_0_uint32_ssa(1); got != 1 { - fmt.Printf("add_uint32 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_uint32_0_ssa(1); got != 1 { - fmt.Printf("add_uint32 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_0_uint32_ssa(4294967295); got != 4294967295 { - fmt.Printf("add_uint32 0%s4294967295 = %d, wanted 4294967295\n", `+`, got) - failed = true - } - - if got := add_uint32_0_ssa(4294967295); got != 4294967295 { - fmt.Printf("add_uint32 4294967295%s0 = %d, wanted 4294967295\n", `+`, got) - failed = true - } - - if got := add_1_uint32_ssa(0); got != 1 { - fmt.Printf("add_uint32 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_uint32_1_ssa(0); got != 1 { - fmt.Printf("add_uint32 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_1_uint32_ssa(1); got != 2 { - fmt.Printf("add_uint32 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_uint32_1_ssa(1); got != 2 { - fmt.Printf("add_uint32 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_1_uint32_ssa(4294967295); got != 0 { - fmt.Printf("add_uint32 1%s4294967295 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_uint32_1_ssa(4294967295); got != 0 { - fmt.Printf("add_uint32 4294967295%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_4294967295_uint32_ssa(0); got != 4294967295 { - fmt.Printf("add_uint32 4294967295%s0 = %d, wanted 4294967295\n", `+`, got) - failed = true - } - - if got := add_uint32_4294967295_ssa(0); got != 4294967295 { - fmt.Printf("add_uint32 0%s4294967295 = %d, wanted 4294967295\n", `+`, got) - failed = true - } - - if got := add_4294967295_uint32_ssa(1); got != 0 { - fmt.Printf("add_uint32 4294967295%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_uint32_4294967295_ssa(1); got != 0 { - fmt.Printf("add_uint32 1%s4294967295 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_4294967295_uint32_ssa(4294967295); got != 4294967294 { - fmt.Printf("add_uint32 4294967295%s4294967295 = %d, wanted 4294967294\n", `+`, got) - failed = true - } - - if got := add_uint32_4294967295_ssa(4294967295); got != 4294967294 { - fmt.Printf("add_uint32 4294967295%s4294967295 = %d, wanted 4294967294\n", `+`, got) - failed = true - } - - if got := sub_0_uint32_ssa(0); got != 0 { - fmt.Printf("sub_uint32 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint32_0_ssa(0); got != 0 { - fmt.Printf("sub_uint32 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_0_uint32_ssa(1); got != 4294967295 { - fmt.Printf("sub_uint32 0%s1 = %d, wanted 4294967295\n", `-`, got) - failed = true - } - - if got := sub_uint32_0_ssa(1); got != 1 { - fmt.Printf("sub_uint32 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_0_uint32_ssa(4294967295); got != 1 { - fmt.Printf("sub_uint32 0%s4294967295 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_uint32_0_ssa(4294967295); got != 4294967295 { - fmt.Printf("sub_uint32 4294967295%s0 = %d, wanted 4294967295\n", `-`, got) - failed = true - } - - if got := sub_1_uint32_ssa(0); got != 1 { - fmt.Printf("sub_uint32 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_uint32_1_ssa(0); got != 4294967295 { - fmt.Printf("sub_uint32 0%s1 = %d, wanted 4294967295\n", `-`, got) - failed = true - } - - if got := sub_1_uint32_ssa(1); got != 0 { - fmt.Printf("sub_uint32 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint32_1_ssa(1); got != 0 { - fmt.Printf("sub_uint32 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_1_uint32_ssa(4294967295); got != 2 { - fmt.Printf("sub_uint32 1%s4294967295 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_uint32_1_ssa(4294967295); got != 4294967294 { - fmt.Printf("sub_uint32 4294967295%s1 = %d, wanted 4294967294\n", `-`, got) - failed = true - } - - if got := sub_4294967295_uint32_ssa(0); got != 4294967295 { - fmt.Printf("sub_uint32 4294967295%s0 = %d, wanted 4294967295\n", `-`, got) - failed = true - } - - if got := sub_uint32_4294967295_ssa(0); got != 1 { - fmt.Printf("sub_uint32 0%s4294967295 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_4294967295_uint32_ssa(1); got != 4294967294 { - fmt.Printf("sub_uint32 4294967295%s1 = %d, wanted 4294967294\n", `-`, got) - failed = true - } - - if got := sub_uint32_4294967295_ssa(1); got != 2 { - fmt.Printf("sub_uint32 1%s4294967295 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_4294967295_uint32_ssa(4294967295); got != 0 { - fmt.Printf("sub_uint32 4294967295%s4294967295 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint32_4294967295_ssa(4294967295); got != 0 { - fmt.Printf("sub_uint32 4294967295%s4294967295 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := div_0_uint32_ssa(1); got != 0 { - fmt.Printf("div_uint32 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_uint32_ssa(4294967295); got != 0 { - fmt.Printf("div_uint32 0%s4294967295 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_uint32_1_ssa(0); got != 0 { - fmt.Printf("div_uint32 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_1_uint32_ssa(1); got != 1 { - fmt.Printf("div_uint32 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_uint32_1_ssa(1); got != 1 { - fmt.Printf("div_uint32 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_1_uint32_ssa(4294967295); got != 0 { - fmt.Printf("div_uint32 1%s4294967295 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_uint32_1_ssa(4294967295); got != 4294967295 { - fmt.Printf("div_uint32 4294967295%s1 = %d, wanted 4294967295\n", `/`, got) - failed = true - } - - if got := div_uint32_4294967295_ssa(0); got != 0 { - fmt.Printf("div_uint32 0%s4294967295 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_4294967295_uint32_ssa(1); got != 4294967295 { - fmt.Printf("div_uint32 4294967295%s1 = %d, wanted 4294967295\n", `/`, got) - failed = true - } - - if got := div_uint32_4294967295_ssa(1); got != 0 { - fmt.Printf("div_uint32 1%s4294967295 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_4294967295_uint32_ssa(4294967295); got != 1 { - fmt.Printf("div_uint32 4294967295%s4294967295 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_uint32_4294967295_ssa(4294967295); got != 1 { - fmt.Printf("div_uint32 4294967295%s4294967295 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := mul_0_uint32_ssa(0); got != 0 { - fmt.Printf("mul_uint32 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint32_0_ssa(0); got != 0 { - fmt.Printf("mul_uint32 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_uint32_ssa(1); got != 0 { - fmt.Printf("mul_uint32 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint32_0_ssa(1); got != 0 { - fmt.Printf("mul_uint32 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_uint32_ssa(4294967295); got != 0 { - fmt.Printf("mul_uint32 0%s4294967295 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint32_0_ssa(4294967295); got != 0 { - fmt.Printf("mul_uint32 4294967295%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_uint32_ssa(0); got != 0 { - fmt.Printf("mul_uint32 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint32_1_ssa(0); got != 0 { - fmt.Printf("mul_uint32 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_uint32_ssa(1); got != 1 { - fmt.Printf("mul_uint32 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_uint32_1_ssa(1); got != 1 { - fmt.Printf("mul_uint32 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_1_uint32_ssa(4294967295); got != 4294967295 { - fmt.Printf("mul_uint32 1%s4294967295 = %d, wanted 4294967295\n", `*`, got) - failed = true - } - - if got := mul_uint32_1_ssa(4294967295); got != 4294967295 { - fmt.Printf("mul_uint32 4294967295%s1 = %d, wanted 4294967295\n", `*`, got) - failed = true - } - - if got := mul_4294967295_uint32_ssa(0); got != 0 { - fmt.Printf("mul_uint32 4294967295%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint32_4294967295_ssa(0); got != 0 { - fmt.Printf("mul_uint32 0%s4294967295 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_4294967295_uint32_ssa(1); got != 4294967295 { - fmt.Printf("mul_uint32 4294967295%s1 = %d, wanted 4294967295\n", `*`, got) - failed = true - } - - if got := mul_uint32_4294967295_ssa(1); got != 4294967295 { - fmt.Printf("mul_uint32 1%s4294967295 = %d, wanted 4294967295\n", `*`, got) - failed = true - } - - if got := mul_4294967295_uint32_ssa(4294967295); got != 1 { - fmt.Printf("mul_uint32 4294967295%s4294967295 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_uint32_4294967295_ssa(4294967295); got != 1 { - fmt.Printf("mul_uint32 4294967295%s4294967295 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := lsh_0_uint32_ssa(0); got != 0 { - fmt.Printf("lsh_uint32 0%s0 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint32_0_ssa(0); got != 0 { - fmt.Printf("lsh_uint32 0%s0 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_0_uint32_ssa(1); got != 0 { - fmt.Printf("lsh_uint32 0%s1 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint32_0_ssa(1); got != 1 { - fmt.Printf("lsh_uint32 1%s0 = %d, wanted 1\n", `<<`, got) - failed = true - } - - if got := lsh_0_uint32_ssa(4294967295); got != 0 { - fmt.Printf("lsh_uint32 0%s4294967295 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint32_0_ssa(4294967295); got != 4294967295 { - fmt.Printf("lsh_uint32 4294967295%s0 = %d, wanted 4294967295\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint32_ssa(0); got != 1 { - fmt.Printf("lsh_uint32 1%s0 = %d, wanted 1\n", `<<`, got) - failed = true - } - - if got := lsh_uint32_1_ssa(0); got != 0 { - fmt.Printf("lsh_uint32 0%s1 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint32_ssa(1); got != 2 { - fmt.Printf("lsh_uint32 1%s1 = %d, wanted 2\n", `<<`, got) - failed = true - } - - if got := lsh_uint32_1_ssa(1); got != 2 { - fmt.Printf("lsh_uint32 1%s1 = %d, wanted 2\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint32_ssa(4294967295); got != 0 { - fmt.Printf("lsh_uint32 1%s4294967295 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint32_1_ssa(4294967295); got != 4294967294 { - fmt.Printf("lsh_uint32 4294967295%s1 = %d, wanted 4294967294\n", `<<`, got) - failed = true - } - - if got := lsh_4294967295_uint32_ssa(0); got != 4294967295 { - fmt.Printf("lsh_uint32 4294967295%s0 = %d, wanted 4294967295\n", `<<`, got) - failed = true - } - - if got := lsh_uint32_4294967295_ssa(0); got != 0 { - fmt.Printf("lsh_uint32 0%s4294967295 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_4294967295_uint32_ssa(1); got != 4294967294 { - fmt.Printf("lsh_uint32 4294967295%s1 = %d, wanted 4294967294\n", `<<`, got) - failed = true - } - - if got := lsh_uint32_4294967295_ssa(1); got != 0 { - fmt.Printf("lsh_uint32 1%s4294967295 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_4294967295_uint32_ssa(4294967295); got != 0 { - fmt.Printf("lsh_uint32 4294967295%s4294967295 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint32_4294967295_ssa(4294967295); got != 0 { - fmt.Printf("lsh_uint32 4294967295%s4294967295 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := rsh_0_uint32_ssa(0); got != 0 { - fmt.Printf("rsh_uint32 0%s0 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint32_0_ssa(0); got != 0 { - fmt.Printf("rsh_uint32 0%s0 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_0_uint32_ssa(1); got != 0 { - fmt.Printf("rsh_uint32 0%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint32_0_ssa(1); got != 1 { - fmt.Printf("rsh_uint32 1%s0 = %d, wanted 1\n", `>>`, got) - failed = true - } - - if got := rsh_0_uint32_ssa(4294967295); got != 0 { - fmt.Printf("rsh_uint32 0%s4294967295 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint32_0_ssa(4294967295); got != 4294967295 { - fmt.Printf("rsh_uint32 4294967295%s0 = %d, wanted 4294967295\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint32_ssa(0); got != 1 { - fmt.Printf("rsh_uint32 1%s0 = %d, wanted 1\n", `>>`, got) - failed = true - } - - if got := rsh_uint32_1_ssa(0); got != 0 { - fmt.Printf("rsh_uint32 0%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint32_ssa(1); got != 0 { - fmt.Printf("rsh_uint32 1%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint32_1_ssa(1); got != 0 { - fmt.Printf("rsh_uint32 1%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint32_ssa(4294967295); got != 0 { - fmt.Printf("rsh_uint32 1%s4294967295 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint32_1_ssa(4294967295); got != 2147483647 { - fmt.Printf("rsh_uint32 4294967295%s1 = %d, wanted 2147483647\n", `>>`, got) - failed = true - } - - if got := rsh_4294967295_uint32_ssa(0); got != 4294967295 { - fmt.Printf("rsh_uint32 4294967295%s0 = %d, wanted 4294967295\n", `>>`, got) - failed = true - } - - if got := rsh_uint32_4294967295_ssa(0); got != 0 { - fmt.Printf("rsh_uint32 0%s4294967295 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_4294967295_uint32_ssa(1); got != 2147483647 { - fmt.Printf("rsh_uint32 4294967295%s1 = %d, wanted 2147483647\n", `>>`, got) - failed = true - } - - if got := rsh_uint32_4294967295_ssa(1); got != 0 { - fmt.Printf("rsh_uint32 1%s4294967295 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_4294967295_uint32_ssa(4294967295); got != 0 { - fmt.Printf("rsh_uint32 4294967295%s4294967295 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint32_4294967295_ssa(4294967295); got != 0 { - fmt.Printf("rsh_uint32 4294967295%s4294967295 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := mod_0_uint32_ssa(1); got != 0 { - fmt.Printf("mod_uint32 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_uint32_ssa(4294967295); got != 0 { - fmt.Printf("mod_uint32 0%s4294967295 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint32_1_ssa(0); got != 0 { - fmt.Printf("mod_uint32 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_uint32_ssa(1); got != 0 { - fmt.Printf("mod_uint32 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint32_1_ssa(1); got != 0 { - fmt.Printf("mod_uint32 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_uint32_ssa(4294967295); got != 1 { - fmt.Printf("mod_uint32 1%s4294967295 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_uint32_1_ssa(4294967295); got != 0 { - fmt.Printf("mod_uint32 4294967295%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint32_4294967295_ssa(0); got != 0 { - fmt.Printf("mod_uint32 0%s4294967295 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_4294967295_uint32_ssa(1); got != 0 { - fmt.Printf("mod_uint32 4294967295%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint32_4294967295_ssa(1); got != 1 { - fmt.Printf("mod_uint32 1%s4294967295 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_4294967295_uint32_ssa(4294967295); got != 0 { - fmt.Printf("mod_uint32 4294967295%s4294967295 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint32_4294967295_ssa(4294967295); got != 0 { - fmt.Printf("mod_uint32 4294967295%s4294967295 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := and_0_uint32_ssa(0); got != 0 { - fmt.Printf("and_uint32 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint32_0_ssa(0); got != 0 { - fmt.Printf("and_uint32 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_uint32_ssa(1); got != 0 { - fmt.Printf("and_uint32 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint32_0_ssa(1); got != 0 { - fmt.Printf("and_uint32 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_uint32_ssa(4294967295); got != 0 { - fmt.Printf("and_uint32 0%s4294967295 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint32_0_ssa(4294967295); got != 0 { - fmt.Printf("and_uint32 4294967295%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_uint32_ssa(0); got != 0 { - fmt.Printf("and_uint32 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint32_1_ssa(0); got != 0 { - fmt.Printf("and_uint32 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_uint32_ssa(1); got != 1 { - fmt.Printf("and_uint32 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_uint32_1_ssa(1); got != 1 { - fmt.Printf("and_uint32 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_uint32_ssa(4294967295); got != 1 { - fmt.Printf("and_uint32 1%s4294967295 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_uint32_1_ssa(4294967295); got != 1 { - fmt.Printf("and_uint32 4294967295%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_4294967295_uint32_ssa(0); got != 0 { - fmt.Printf("and_uint32 4294967295%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint32_4294967295_ssa(0); got != 0 { - fmt.Printf("and_uint32 0%s4294967295 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_4294967295_uint32_ssa(1); got != 1 { - fmt.Printf("and_uint32 4294967295%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_uint32_4294967295_ssa(1); got != 1 { - fmt.Printf("and_uint32 1%s4294967295 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_4294967295_uint32_ssa(4294967295); got != 4294967295 { - fmt.Printf("and_uint32 4294967295%s4294967295 = %d, wanted 4294967295\n", `&`, got) - failed = true - } - - if got := and_uint32_4294967295_ssa(4294967295); got != 4294967295 { - fmt.Printf("and_uint32 4294967295%s4294967295 = %d, wanted 4294967295\n", `&`, got) - failed = true - } - - if got := or_0_uint32_ssa(0); got != 0 { - fmt.Printf("or_uint32 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_uint32_0_ssa(0); got != 0 { - fmt.Printf("or_uint32 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_0_uint32_ssa(1); got != 1 { - fmt.Printf("or_uint32 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_uint32_0_ssa(1); got != 1 { - fmt.Printf("or_uint32 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_0_uint32_ssa(4294967295); got != 4294967295 { - fmt.Printf("or_uint32 0%s4294967295 = %d, wanted 4294967295\n", `|`, got) - failed = true - } - - if got := or_uint32_0_ssa(4294967295); got != 4294967295 { - fmt.Printf("or_uint32 4294967295%s0 = %d, wanted 4294967295\n", `|`, got) - failed = true - } - - if got := or_1_uint32_ssa(0); got != 1 { - fmt.Printf("or_uint32 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_uint32_1_ssa(0); got != 1 { - fmt.Printf("or_uint32 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_uint32_ssa(1); got != 1 { - fmt.Printf("or_uint32 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_uint32_1_ssa(1); got != 1 { - fmt.Printf("or_uint32 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_uint32_ssa(4294967295); got != 4294967295 { - fmt.Printf("or_uint32 1%s4294967295 = %d, wanted 4294967295\n", `|`, got) - failed = true - } - - if got := or_uint32_1_ssa(4294967295); got != 4294967295 { - fmt.Printf("or_uint32 4294967295%s1 = %d, wanted 4294967295\n", `|`, got) - failed = true - } - - if got := or_4294967295_uint32_ssa(0); got != 4294967295 { - fmt.Printf("or_uint32 4294967295%s0 = %d, wanted 4294967295\n", `|`, got) - failed = true - } - - if got := or_uint32_4294967295_ssa(0); got != 4294967295 { - fmt.Printf("or_uint32 0%s4294967295 = %d, wanted 4294967295\n", `|`, got) - failed = true - } - - if got := or_4294967295_uint32_ssa(1); got != 4294967295 { - fmt.Printf("or_uint32 4294967295%s1 = %d, wanted 4294967295\n", `|`, got) - failed = true - } - - if got := or_uint32_4294967295_ssa(1); got != 4294967295 { - fmt.Printf("or_uint32 1%s4294967295 = %d, wanted 4294967295\n", `|`, got) - failed = true - } - - if got := or_4294967295_uint32_ssa(4294967295); got != 4294967295 { - fmt.Printf("or_uint32 4294967295%s4294967295 = %d, wanted 4294967295\n", `|`, got) - failed = true - } - - if got := or_uint32_4294967295_ssa(4294967295); got != 4294967295 { - fmt.Printf("or_uint32 4294967295%s4294967295 = %d, wanted 4294967295\n", `|`, got) - failed = true - } - - if got := xor_0_uint32_ssa(0); got != 0 { - fmt.Printf("xor_uint32 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint32_0_ssa(0); got != 0 { - fmt.Printf("xor_uint32 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_0_uint32_ssa(1); got != 1 { - fmt.Printf("xor_uint32 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_uint32_0_ssa(1); got != 1 { - fmt.Printf("xor_uint32 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_0_uint32_ssa(4294967295); got != 4294967295 { - fmt.Printf("xor_uint32 0%s4294967295 = %d, wanted 4294967295\n", `^`, got) - failed = true - } - - if got := xor_uint32_0_ssa(4294967295); got != 4294967295 { - fmt.Printf("xor_uint32 4294967295%s0 = %d, wanted 4294967295\n", `^`, got) - failed = true - } - - if got := xor_1_uint32_ssa(0); got != 1 { - fmt.Printf("xor_uint32 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_uint32_1_ssa(0); got != 1 { - fmt.Printf("xor_uint32 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_1_uint32_ssa(1); got != 0 { - fmt.Printf("xor_uint32 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint32_1_ssa(1); got != 0 { - fmt.Printf("xor_uint32 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_1_uint32_ssa(4294967295); got != 4294967294 { - fmt.Printf("xor_uint32 1%s4294967295 = %d, wanted 4294967294\n", `^`, got) - failed = true - } - - if got := xor_uint32_1_ssa(4294967295); got != 4294967294 { - fmt.Printf("xor_uint32 4294967295%s1 = %d, wanted 4294967294\n", `^`, got) - failed = true - } - - if got := xor_4294967295_uint32_ssa(0); got != 4294967295 { - fmt.Printf("xor_uint32 4294967295%s0 = %d, wanted 4294967295\n", `^`, got) - failed = true - } - - if got := xor_uint32_4294967295_ssa(0); got != 4294967295 { - fmt.Printf("xor_uint32 0%s4294967295 = %d, wanted 4294967295\n", `^`, got) - failed = true - } - - if got := xor_4294967295_uint32_ssa(1); got != 4294967294 { - fmt.Printf("xor_uint32 4294967295%s1 = %d, wanted 4294967294\n", `^`, got) - failed = true - } - - if got := xor_uint32_4294967295_ssa(1); got != 4294967294 { - fmt.Printf("xor_uint32 1%s4294967295 = %d, wanted 4294967294\n", `^`, got) - failed = true - } - - if got := xor_4294967295_uint32_ssa(4294967295); got != 0 { - fmt.Printf("xor_uint32 4294967295%s4294967295 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint32_4294967295_ssa(4294967295); got != 0 { - fmt.Printf("xor_uint32 4294967295%s4294967295 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := add_Neg2147483648_int32_ssa(-2147483648); got != 0 { - fmt.Printf("add_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int32_Neg2147483648_ssa(-2147483648); got != 0 { - fmt.Printf("add_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_Neg2147483648_int32_ssa(-2147483647); got != 1 { - fmt.Printf("add_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int32_Neg2147483648_ssa(-2147483647); got != 1 { - fmt.Printf("add_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_Neg2147483648_int32_ssa(-1); got != 2147483647 { - fmt.Printf("add_int32 -2147483648%s-1 = %d, wanted 2147483647\n", `+`, got) - failed = true - } - - if got := add_int32_Neg2147483648_ssa(-1); got != 2147483647 { - fmt.Printf("add_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `+`, got) - failed = true - } - - if got := add_Neg2147483648_int32_ssa(0); got != -2147483648 { - fmt.Printf("add_int32 -2147483648%s0 = %d, wanted -2147483648\n", `+`, got) - failed = true - } - - if got := add_int32_Neg2147483648_ssa(0); got != -2147483648 { - fmt.Printf("add_int32 0%s-2147483648 = %d, wanted -2147483648\n", `+`, got) - failed = true - } - - if got := add_Neg2147483648_int32_ssa(1); got != -2147483647 { - fmt.Printf("add_int32 -2147483648%s1 = %d, wanted -2147483647\n", `+`, got) - failed = true - } - - if got := add_int32_Neg2147483648_ssa(1); got != -2147483647 { - fmt.Printf("add_int32 1%s-2147483648 = %d, wanted -2147483647\n", `+`, got) - failed = true - } - - if got := add_Neg2147483648_int32_ssa(2147483647); got != -1 { - fmt.Printf("add_int32 -2147483648%s2147483647 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int32_Neg2147483648_ssa(2147483647); got != -1 { - fmt.Printf("add_int32 2147483647%s-2147483648 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_Neg2147483647_int32_ssa(-2147483648); got != 1 { - fmt.Printf("add_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int32_Neg2147483647_ssa(-2147483648); got != 1 { - fmt.Printf("add_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_Neg2147483647_int32_ssa(-2147483647); got != 2 { - fmt.Printf("add_int32 -2147483647%s-2147483647 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_int32_Neg2147483647_ssa(-2147483647); got != 2 { - fmt.Printf("add_int32 -2147483647%s-2147483647 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_Neg2147483647_int32_ssa(-1); got != -2147483648 { - fmt.Printf("add_int32 -2147483647%s-1 = %d, wanted -2147483648\n", `+`, got) - failed = true - } - - if got := add_int32_Neg2147483647_ssa(-1); got != -2147483648 { - fmt.Printf("add_int32 -1%s-2147483647 = %d, wanted -2147483648\n", `+`, got) - failed = true - } - - if got := add_Neg2147483647_int32_ssa(0); got != -2147483647 { - fmt.Printf("add_int32 -2147483647%s0 = %d, wanted -2147483647\n", `+`, got) - failed = true - } - - if got := add_int32_Neg2147483647_ssa(0); got != -2147483647 { - fmt.Printf("add_int32 0%s-2147483647 = %d, wanted -2147483647\n", `+`, got) - failed = true - } - - if got := add_Neg2147483647_int32_ssa(1); got != -2147483646 { - fmt.Printf("add_int32 -2147483647%s1 = %d, wanted -2147483646\n", `+`, got) - failed = true - } - - if got := add_int32_Neg2147483647_ssa(1); got != -2147483646 { - fmt.Printf("add_int32 1%s-2147483647 = %d, wanted -2147483646\n", `+`, got) - failed = true - } - - if got := add_Neg2147483647_int32_ssa(2147483647); got != 0 { - fmt.Printf("add_int32 -2147483647%s2147483647 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int32_Neg2147483647_ssa(2147483647); got != 0 { - fmt.Printf("add_int32 2147483647%s-2147483647 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_Neg1_int32_ssa(-2147483648); got != 2147483647 { - fmt.Printf("add_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `+`, got) - failed = true - } - - if got := add_int32_Neg1_ssa(-2147483648); got != 2147483647 { - fmt.Printf("add_int32 -2147483648%s-1 = %d, wanted 2147483647\n", `+`, got) - failed = true - } - - if got := add_Neg1_int32_ssa(-2147483647); got != -2147483648 { - fmt.Printf("add_int32 -1%s-2147483647 = %d, wanted -2147483648\n", `+`, got) - failed = true - } - - if got := add_int32_Neg1_ssa(-2147483647); got != -2147483648 { - fmt.Printf("add_int32 -2147483647%s-1 = %d, wanted -2147483648\n", `+`, got) - failed = true - } - - if got := add_Neg1_int32_ssa(-1); got != -2 { - fmt.Printf("add_int32 -1%s-1 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int32_Neg1_ssa(-1); got != -2 { - fmt.Printf("add_int32 -1%s-1 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_Neg1_int32_ssa(0); got != -1 { - fmt.Printf("add_int32 -1%s0 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int32_Neg1_ssa(0); got != -1 { - fmt.Printf("add_int32 0%s-1 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_Neg1_int32_ssa(1); got != 0 { - fmt.Printf("add_int32 -1%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int32_Neg1_ssa(1); got != 0 { - fmt.Printf("add_int32 1%s-1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_Neg1_int32_ssa(2147483647); got != 2147483646 { - fmt.Printf("add_int32 -1%s2147483647 = %d, wanted 2147483646\n", `+`, got) - failed = true - } - - if got := add_int32_Neg1_ssa(2147483647); got != 2147483646 { - fmt.Printf("add_int32 2147483647%s-1 = %d, wanted 2147483646\n", `+`, got) - failed = true - } - - if got := add_0_int32_ssa(-2147483648); got != -2147483648 { - fmt.Printf("add_int32 0%s-2147483648 = %d, wanted -2147483648\n", `+`, got) - failed = true - } - - if got := add_int32_0_ssa(-2147483648); got != -2147483648 { - fmt.Printf("add_int32 -2147483648%s0 = %d, wanted -2147483648\n", `+`, got) - failed = true - } - - if got := add_0_int32_ssa(-2147483647); got != -2147483647 { - fmt.Printf("add_int32 0%s-2147483647 = %d, wanted -2147483647\n", `+`, got) - failed = true - } - - if got := add_int32_0_ssa(-2147483647); got != -2147483647 { - fmt.Printf("add_int32 -2147483647%s0 = %d, wanted -2147483647\n", `+`, got) - failed = true - } - - if got := add_0_int32_ssa(-1); got != -1 { - fmt.Printf("add_int32 0%s-1 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int32_0_ssa(-1); got != -1 { - fmt.Printf("add_int32 -1%s0 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_0_int32_ssa(0); got != 0 { - fmt.Printf("add_int32 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int32_0_ssa(0); got != 0 { - fmt.Printf("add_int32 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_0_int32_ssa(1); got != 1 { - fmt.Printf("add_int32 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int32_0_ssa(1); got != 1 { - fmt.Printf("add_int32 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_0_int32_ssa(2147483647); got != 2147483647 { - fmt.Printf("add_int32 0%s2147483647 = %d, wanted 2147483647\n", `+`, got) - failed = true - } - - if got := add_int32_0_ssa(2147483647); got != 2147483647 { - fmt.Printf("add_int32 2147483647%s0 = %d, wanted 2147483647\n", `+`, got) - failed = true - } - - if got := add_1_int32_ssa(-2147483648); got != -2147483647 { - fmt.Printf("add_int32 1%s-2147483648 = %d, wanted -2147483647\n", `+`, got) - failed = true - } - - if got := add_int32_1_ssa(-2147483648); got != -2147483647 { - fmt.Printf("add_int32 -2147483648%s1 = %d, wanted -2147483647\n", `+`, got) - failed = true - } - - if got := add_1_int32_ssa(-2147483647); got != -2147483646 { - fmt.Printf("add_int32 1%s-2147483647 = %d, wanted -2147483646\n", `+`, got) - failed = true - } - - if got := add_int32_1_ssa(-2147483647); got != -2147483646 { - fmt.Printf("add_int32 -2147483647%s1 = %d, wanted -2147483646\n", `+`, got) - failed = true - } - - if got := add_1_int32_ssa(-1); got != 0 { - fmt.Printf("add_int32 1%s-1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int32_1_ssa(-1); got != 0 { - fmt.Printf("add_int32 -1%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_1_int32_ssa(0); got != 1 { - fmt.Printf("add_int32 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int32_1_ssa(0); got != 1 { - fmt.Printf("add_int32 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_1_int32_ssa(1); got != 2 { - fmt.Printf("add_int32 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_int32_1_ssa(1); got != 2 { - fmt.Printf("add_int32 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_1_int32_ssa(2147483647); got != -2147483648 { - fmt.Printf("add_int32 1%s2147483647 = %d, wanted -2147483648\n", `+`, got) - failed = true - } - - if got := add_int32_1_ssa(2147483647); got != -2147483648 { - fmt.Printf("add_int32 2147483647%s1 = %d, wanted -2147483648\n", `+`, got) - failed = true - } - - if got := add_2147483647_int32_ssa(-2147483648); got != -1 { - fmt.Printf("add_int32 2147483647%s-2147483648 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int32_2147483647_ssa(-2147483648); got != -1 { - fmt.Printf("add_int32 -2147483648%s2147483647 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_2147483647_int32_ssa(-2147483647); got != 0 { - fmt.Printf("add_int32 2147483647%s-2147483647 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int32_2147483647_ssa(-2147483647); got != 0 { - fmt.Printf("add_int32 -2147483647%s2147483647 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_2147483647_int32_ssa(-1); got != 2147483646 { - fmt.Printf("add_int32 2147483647%s-1 = %d, wanted 2147483646\n", `+`, got) - failed = true - } - - if got := add_int32_2147483647_ssa(-1); got != 2147483646 { - fmt.Printf("add_int32 -1%s2147483647 = %d, wanted 2147483646\n", `+`, got) - failed = true - } - - if got := add_2147483647_int32_ssa(0); got != 2147483647 { - fmt.Printf("add_int32 2147483647%s0 = %d, wanted 2147483647\n", `+`, got) - failed = true - } - - if got := add_int32_2147483647_ssa(0); got != 2147483647 { - fmt.Printf("add_int32 0%s2147483647 = %d, wanted 2147483647\n", `+`, got) - failed = true - } - - if got := add_2147483647_int32_ssa(1); got != -2147483648 { - fmt.Printf("add_int32 2147483647%s1 = %d, wanted -2147483648\n", `+`, got) - failed = true - } - - if got := add_int32_2147483647_ssa(1); got != -2147483648 { - fmt.Printf("add_int32 1%s2147483647 = %d, wanted -2147483648\n", `+`, got) - failed = true - } - - if got := add_2147483647_int32_ssa(2147483647); got != -2 { - fmt.Printf("add_int32 2147483647%s2147483647 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int32_2147483647_ssa(2147483647); got != -2 { - fmt.Printf("add_int32 2147483647%s2147483647 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := sub_Neg2147483648_int32_ssa(-2147483648); got != 0 { - fmt.Printf("sub_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg2147483648_ssa(-2147483648); got != 0 { - fmt.Printf("sub_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_Neg2147483648_int32_ssa(-2147483647); got != -1 { - fmt.Printf("sub_int32 -2147483648%s-2147483647 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg2147483648_ssa(-2147483647); got != 1 { - fmt.Printf("sub_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_Neg2147483648_int32_ssa(-1); got != -2147483647 { - fmt.Printf("sub_int32 -2147483648%s-1 = %d, wanted -2147483647\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg2147483648_ssa(-1); got != 2147483647 { - fmt.Printf("sub_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `-`, got) - failed = true - } - - if got := sub_Neg2147483648_int32_ssa(0); got != -2147483648 { - fmt.Printf("sub_int32 -2147483648%s0 = %d, wanted -2147483648\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg2147483648_ssa(0); got != -2147483648 { - fmt.Printf("sub_int32 0%s-2147483648 = %d, wanted -2147483648\n", `-`, got) - failed = true - } - - if got := sub_Neg2147483648_int32_ssa(1); got != 2147483647 { - fmt.Printf("sub_int32 -2147483648%s1 = %d, wanted 2147483647\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg2147483648_ssa(1); got != -2147483647 { - fmt.Printf("sub_int32 1%s-2147483648 = %d, wanted -2147483647\n", `-`, got) - failed = true - } - - if got := sub_Neg2147483648_int32_ssa(2147483647); got != 1 { - fmt.Printf("sub_int32 -2147483648%s2147483647 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg2147483648_ssa(2147483647); got != -1 { - fmt.Printf("sub_int32 2147483647%s-2147483648 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_Neg2147483647_int32_ssa(-2147483648); got != 1 { - fmt.Printf("sub_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg2147483647_ssa(-2147483648); got != -1 { - fmt.Printf("sub_int32 -2147483648%s-2147483647 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_Neg2147483647_int32_ssa(-2147483647); got != 0 { - fmt.Printf("sub_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg2147483647_ssa(-2147483647); got != 0 { - fmt.Printf("sub_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_Neg2147483647_int32_ssa(-1); got != -2147483646 { - fmt.Printf("sub_int32 -2147483647%s-1 = %d, wanted -2147483646\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg2147483647_ssa(-1); got != 2147483646 { - fmt.Printf("sub_int32 -1%s-2147483647 = %d, wanted 2147483646\n", `-`, got) - failed = true - } - - if got := sub_Neg2147483647_int32_ssa(0); got != -2147483647 { - fmt.Printf("sub_int32 -2147483647%s0 = %d, wanted -2147483647\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg2147483647_ssa(0); got != 2147483647 { - fmt.Printf("sub_int32 0%s-2147483647 = %d, wanted 2147483647\n", `-`, got) - failed = true - } - - if got := sub_Neg2147483647_int32_ssa(1); got != -2147483648 { - fmt.Printf("sub_int32 -2147483647%s1 = %d, wanted -2147483648\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg2147483647_ssa(1); got != -2147483648 { - fmt.Printf("sub_int32 1%s-2147483647 = %d, wanted -2147483648\n", `-`, got) - failed = true - } - - if got := sub_Neg2147483647_int32_ssa(2147483647); got != 2 { - fmt.Printf("sub_int32 -2147483647%s2147483647 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg2147483647_ssa(2147483647); got != -2 { - fmt.Printf("sub_int32 2147483647%s-2147483647 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int32_ssa(-2147483648); got != 2147483647 { - fmt.Printf("sub_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg1_ssa(-2147483648); got != -2147483647 { - fmt.Printf("sub_int32 -2147483648%s-1 = %d, wanted -2147483647\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int32_ssa(-2147483647); got != 2147483646 { - fmt.Printf("sub_int32 -1%s-2147483647 = %d, wanted 2147483646\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg1_ssa(-2147483647); got != -2147483646 { - fmt.Printf("sub_int32 -2147483647%s-1 = %d, wanted -2147483646\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int32_ssa(-1); got != 0 { - fmt.Printf("sub_int32 -1%s-1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg1_ssa(-1); got != 0 { - fmt.Printf("sub_int32 -1%s-1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int32_ssa(0); got != -1 { - fmt.Printf("sub_int32 -1%s0 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg1_ssa(0); got != 1 { - fmt.Printf("sub_int32 0%s-1 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int32_ssa(1); got != -2 { - fmt.Printf("sub_int32 -1%s1 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg1_ssa(1); got != 2 { - fmt.Printf("sub_int32 1%s-1 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int32_ssa(2147483647); got != -2147483648 { - fmt.Printf("sub_int32 -1%s2147483647 = %d, wanted -2147483648\n", `-`, got) - failed = true - } - - if got := sub_int32_Neg1_ssa(2147483647); got != -2147483648 { - fmt.Printf("sub_int32 2147483647%s-1 = %d, wanted -2147483648\n", `-`, got) - failed = true - } - - if got := sub_0_int32_ssa(-2147483648); got != -2147483648 { - fmt.Printf("sub_int32 0%s-2147483648 = %d, wanted -2147483648\n", `-`, got) - failed = true - } - - if got := sub_int32_0_ssa(-2147483648); got != -2147483648 { - fmt.Printf("sub_int32 -2147483648%s0 = %d, wanted -2147483648\n", `-`, got) - failed = true - } - - if got := sub_0_int32_ssa(-2147483647); got != 2147483647 { - fmt.Printf("sub_int32 0%s-2147483647 = %d, wanted 2147483647\n", `-`, got) - failed = true - } - - if got := sub_int32_0_ssa(-2147483647); got != -2147483647 { - fmt.Printf("sub_int32 -2147483647%s0 = %d, wanted -2147483647\n", `-`, got) - failed = true - } - - if got := sub_0_int32_ssa(-1); got != 1 { - fmt.Printf("sub_int32 0%s-1 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int32_0_ssa(-1); got != -1 { - fmt.Printf("sub_int32 -1%s0 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_0_int32_ssa(0); got != 0 { - fmt.Printf("sub_int32 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int32_0_ssa(0); got != 0 { - fmt.Printf("sub_int32 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_0_int32_ssa(1); got != -1 { - fmt.Printf("sub_int32 0%s1 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int32_0_ssa(1); got != 1 { - fmt.Printf("sub_int32 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_0_int32_ssa(2147483647); got != -2147483647 { - fmt.Printf("sub_int32 0%s2147483647 = %d, wanted -2147483647\n", `-`, got) - failed = true - } - - if got := sub_int32_0_ssa(2147483647); got != 2147483647 { - fmt.Printf("sub_int32 2147483647%s0 = %d, wanted 2147483647\n", `-`, got) - failed = true - } - - if got := sub_1_int32_ssa(-2147483648); got != -2147483647 { - fmt.Printf("sub_int32 1%s-2147483648 = %d, wanted -2147483647\n", `-`, got) - failed = true - } - - if got := sub_int32_1_ssa(-2147483648); got != 2147483647 { - fmt.Printf("sub_int32 -2147483648%s1 = %d, wanted 2147483647\n", `-`, got) - failed = true - } - - if got := sub_1_int32_ssa(-2147483647); got != -2147483648 { - fmt.Printf("sub_int32 1%s-2147483647 = %d, wanted -2147483648\n", `-`, got) - failed = true - } - - if got := sub_int32_1_ssa(-2147483647); got != -2147483648 { - fmt.Printf("sub_int32 -2147483647%s1 = %d, wanted -2147483648\n", `-`, got) - failed = true - } - - if got := sub_1_int32_ssa(-1); got != 2 { - fmt.Printf("sub_int32 1%s-1 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_int32_1_ssa(-1); got != -2 { - fmt.Printf("sub_int32 -1%s1 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_1_int32_ssa(0); got != 1 { - fmt.Printf("sub_int32 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int32_1_ssa(0); got != -1 { - fmt.Printf("sub_int32 0%s1 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_1_int32_ssa(1); got != 0 { - fmt.Printf("sub_int32 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int32_1_ssa(1); got != 0 { - fmt.Printf("sub_int32 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_1_int32_ssa(2147483647); got != -2147483646 { - fmt.Printf("sub_int32 1%s2147483647 = %d, wanted -2147483646\n", `-`, got) - failed = true - } - - if got := sub_int32_1_ssa(2147483647); got != 2147483646 { - fmt.Printf("sub_int32 2147483647%s1 = %d, wanted 2147483646\n", `-`, got) - failed = true - } - - if got := sub_2147483647_int32_ssa(-2147483648); got != -1 { - fmt.Printf("sub_int32 2147483647%s-2147483648 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int32_2147483647_ssa(-2147483648); got != 1 { - fmt.Printf("sub_int32 -2147483648%s2147483647 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_2147483647_int32_ssa(-2147483647); got != -2 { - fmt.Printf("sub_int32 2147483647%s-2147483647 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_int32_2147483647_ssa(-2147483647); got != 2 { - fmt.Printf("sub_int32 -2147483647%s2147483647 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_2147483647_int32_ssa(-1); got != -2147483648 { - fmt.Printf("sub_int32 2147483647%s-1 = %d, wanted -2147483648\n", `-`, got) - failed = true - } - - if got := sub_int32_2147483647_ssa(-1); got != -2147483648 { - fmt.Printf("sub_int32 -1%s2147483647 = %d, wanted -2147483648\n", `-`, got) - failed = true - } - - if got := sub_2147483647_int32_ssa(0); got != 2147483647 { - fmt.Printf("sub_int32 2147483647%s0 = %d, wanted 2147483647\n", `-`, got) - failed = true - } - - if got := sub_int32_2147483647_ssa(0); got != -2147483647 { - fmt.Printf("sub_int32 0%s2147483647 = %d, wanted -2147483647\n", `-`, got) - failed = true - } - - if got := sub_2147483647_int32_ssa(1); got != 2147483646 { - fmt.Printf("sub_int32 2147483647%s1 = %d, wanted 2147483646\n", `-`, got) - failed = true - } - - if got := sub_int32_2147483647_ssa(1); got != -2147483646 { - fmt.Printf("sub_int32 1%s2147483647 = %d, wanted -2147483646\n", `-`, got) - failed = true - } - - if got := sub_2147483647_int32_ssa(2147483647); got != 0 { - fmt.Printf("sub_int32 2147483647%s2147483647 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int32_2147483647_ssa(2147483647); got != 0 { - fmt.Printf("sub_int32 2147483647%s2147483647 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := div_Neg2147483648_int32_ssa(-2147483648); got != 1 { - fmt.Printf("div_int32 -2147483648%s-2147483648 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int32_Neg2147483648_ssa(-2147483648); got != 1 { - fmt.Printf("div_int32 -2147483648%s-2147483648 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_Neg2147483648_int32_ssa(-2147483647); got != 1 { - fmt.Printf("div_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int32_Neg2147483648_ssa(-2147483647); got != 0 { - fmt.Printf("div_int32 -2147483647%s-2147483648 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg2147483648_int32_ssa(-1); got != -2147483648 { - fmt.Printf("div_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `/`, got) - failed = true - } - - if got := div_int32_Neg2147483648_ssa(-1); got != 0 { - fmt.Printf("div_int32 -1%s-2147483648 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int32_Neg2147483648_ssa(0); got != 0 { - fmt.Printf("div_int32 0%s-2147483648 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg2147483648_int32_ssa(1); got != -2147483648 { - fmt.Printf("div_int32 -2147483648%s1 = %d, wanted -2147483648\n", `/`, got) - failed = true - } - - if got := div_int32_Neg2147483648_ssa(1); got != 0 { - fmt.Printf("div_int32 1%s-2147483648 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg2147483648_int32_ssa(2147483647); got != -1 { - fmt.Printf("div_int32 -2147483648%s2147483647 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int32_Neg2147483648_ssa(2147483647); got != 0 { - fmt.Printf("div_int32 2147483647%s-2147483648 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg2147483647_int32_ssa(-2147483648); got != 0 { - fmt.Printf("div_int32 -2147483647%s-2147483648 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int32_Neg2147483647_ssa(-2147483648); got != 1 { - fmt.Printf("div_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_Neg2147483647_int32_ssa(-2147483647); got != 1 { - fmt.Printf("div_int32 -2147483647%s-2147483647 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int32_Neg2147483647_ssa(-2147483647); got != 1 { - fmt.Printf("div_int32 -2147483647%s-2147483647 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_Neg2147483647_int32_ssa(-1); got != 2147483647 { - fmt.Printf("div_int32 -2147483647%s-1 = %d, wanted 2147483647\n", `/`, got) - failed = true - } - - if got := div_int32_Neg2147483647_ssa(-1); got != 0 { - fmt.Printf("div_int32 -1%s-2147483647 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int32_Neg2147483647_ssa(0); got != 0 { - fmt.Printf("div_int32 0%s-2147483647 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg2147483647_int32_ssa(1); got != -2147483647 { - fmt.Printf("div_int32 -2147483647%s1 = %d, wanted -2147483647\n", `/`, got) - failed = true - } - - if got := div_int32_Neg2147483647_ssa(1); got != 0 { - fmt.Printf("div_int32 1%s-2147483647 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg2147483647_int32_ssa(2147483647); got != -1 { - fmt.Printf("div_int32 -2147483647%s2147483647 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int32_Neg2147483647_ssa(2147483647); got != -1 { - fmt.Printf("div_int32 2147483647%s-2147483647 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_Neg1_int32_ssa(-2147483648); got != 0 { - fmt.Printf("div_int32 -1%s-2147483648 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int32_Neg1_ssa(-2147483648); got != -2147483648 { - fmt.Printf("div_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `/`, got) - failed = true - } - - if got := div_Neg1_int32_ssa(-2147483647); got != 0 { - fmt.Printf("div_int32 -1%s-2147483647 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int32_Neg1_ssa(-2147483647); got != 2147483647 { - fmt.Printf("div_int32 -2147483647%s-1 = %d, wanted 2147483647\n", `/`, got) - failed = true - } - - if got := div_Neg1_int32_ssa(-1); got != 1 { - fmt.Printf("div_int32 -1%s-1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int32_Neg1_ssa(-1); got != 1 { - fmt.Printf("div_int32 -1%s-1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int32_Neg1_ssa(0); got != 0 { - fmt.Printf("div_int32 0%s-1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg1_int32_ssa(1); got != -1 { - fmt.Printf("div_int32 -1%s1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int32_Neg1_ssa(1); got != -1 { - fmt.Printf("div_int32 1%s-1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_Neg1_int32_ssa(2147483647); got != 0 { - fmt.Printf("div_int32 -1%s2147483647 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int32_Neg1_ssa(2147483647); got != -2147483647 { - fmt.Printf("div_int32 2147483647%s-1 = %d, wanted -2147483647\n", `/`, got) - failed = true - } - - if got := div_0_int32_ssa(-2147483648); got != 0 { - fmt.Printf("div_int32 0%s-2147483648 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int32_ssa(-2147483647); got != 0 { - fmt.Printf("div_int32 0%s-2147483647 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int32_ssa(-1); got != 0 { - fmt.Printf("div_int32 0%s-1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int32_ssa(1); got != 0 { - fmt.Printf("div_int32 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int32_ssa(2147483647); got != 0 { - fmt.Printf("div_int32 0%s2147483647 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_1_int32_ssa(-2147483648); got != 0 { - fmt.Printf("div_int32 1%s-2147483648 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int32_1_ssa(-2147483648); got != -2147483648 { - fmt.Printf("div_int32 -2147483648%s1 = %d, wanted -2147483648\n", `/`, got) - failed = true - } - - if got := div_1_int32_ssa(-2147483647); got != 0 { - fmt.Printf("div_int32 1%s-2147483647 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int32_1_ssa(-2147483647); got != -2147483647 { - fmt.Printf("div_int32 -2147483647%s1 = %d, wanted -2147483647\n", `/`, got) - failed = true - } - - if got := div_1_int32_ssa(-1); got != -1 { - fmt.Printf("div_int32 1%s-1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int32_1_ssa(-1); got != -1 { - fmt.Printf("div_int32 -1%s1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int32_1_ssa(0); got != 0 { - fmt.Printf("div_int32 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_1_int32_ssa(1); got != 1 { - fmt.Printf("div_int32 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int32_1_ssa(1); got != 1 { - fmt.Printf("div_int32 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_1_int32_ssa(2147483647); got != 0 { - fmt.Printf("div_int32 1%s2147483647 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int32_1_ssa(2147483647); got != 2147483647 { - fmt.Printf("div_int32 2147483647%s1 = %d, wanted 2147483647\n", `/`, got) - failed = true - } - - if got := div_2147483647_int32_ssa(-2147483648); got != 0 { - fmt.Printf("div_int32 2147483647%s-2147483648 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int32_2147483647_ssa(-2147483648); got != -1 { - fmt.Printf("div_int32 -2147483648%s2147483647 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_2147483647_int32_ssa(-2147483647); got != -1 { - fmt.Printf("div_int32 2147483647%s-2147483647 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int32_2147483647_ssa(-2147483647); got != -1 { - fmt.Printf("div_int32 -2147483647%s2147483647 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_2147483647_int32_ssa(-1); got != -2147483647 { - fmt.Printf("div_int32 2147483647%s-1 = %d, wanted -2147483647\n", `/`, got) - failed = true - } - - if got := div_int32_2147483647_ssa(-1); got != 0 { - fmt.Printf("div_int32 -1%s2147483647 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int32_2147483647_ssa(0); got != 0 { - fmt.Printf("div_int32 0%s2147483647 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_2147483647_int32_ssa(1); got != 2147483647 { - fmt.Printf("div_int32 2147483647%s1 = %d, wanted 2147483647\n", `/`, got) - failed = true - } - - if got := div_int32_2147483647_ssa(1); got != 0 { - fmt.Printf("div_int32 1%s2147483647 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_2147483647_int32_ssa(2147483647); got != 1 { - fmt.Printf("div_int32 2147483647%s2147483647 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int32_2147483647_ssa(2147483647); got != 1 { - fmt.Printf("div_int32 2147483647%s2147483647 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := mul_Neg2147483648_int32_ssa(-2147483648); got != 0 { - fmt.Printf("mul_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg2147483648_ssa(-2147483648); got != 0 { - fmt.Printf("mul_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg2147483648_int32_ssa(-2147483647); got != -2147483648 { - fmt.Printf("mul_int32 -2147483648%s-2147483647 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg2147483648_ssa(-2147483647); got != -2147483648 { - fmt.Printf("mul_int32 -2147483647%s-2147483648 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_Neg2147483648_int32_ssa(-1); got != -2147483648 { - fmt.Printf("mul_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg2147483648_ssa(-1); got != -2147483648 { - fmt.Printf("mul_int32 -1%s-2147483648 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_Neg2147483648_int32_ssa(0); got != 0 { - fmt.Printf("mul_int32 -2147483648%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg2147483648_ssa(0); got != 0 { - fmt.Printf("mul_int32 0%s-2147483648 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg2147483648_int32_ssa(1); got != -2147483648 { - fmt.Printf("mul_int32 -2147483648%s1 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg2147483648_ssa(1); got != -2147483648 { - fmt.Printf("mul_int32 1%s-2147483648 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_Neg2147483648_int32_ssa(2147483647); got != -2147483648 { - fmt.Printf("mul_int32 -2147483648%s2147483647 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg2147483648_ssa(2147483647); got != -2147483648 { - fmt.Printf("mul_int32 2147483647%s-2147483648 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_Neg2147483647_int32_ssa(-2147483648); got != -2147483648 { - fmt.Printf("mul_int32 -2147483647%s-2147483648 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg2147483647_ssa(-2147483648); got != -2147483648 { - fmt.Printf("mul_int32 -2147483648%s-2147483647 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_Neg2147483647_int32_ssa(-2147483647); got != 1 { - fmt.Printf("mul_int32 -2147483647%s-2147483647 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg2147483647_ssa(-2147483647); got != 1 { - fmt.Printf("mul_int32 -2147483647%s-2147483647 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_Neg2147483647_int32_ssa(-1); got != 2147483647 { - fmt.Printf("mul_int32 -2147483647%s-1 = %d, wanted 2147483647\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg2147483647_ssa(-1); got != 2147483647 { - fmt.Printf("mul_int32 -1%s-2147483647 = %d, wanted 2147483647\n", `*`, got) - failed = true - } - - if got := mul_Neg2147483647_int32_ssa(0); got != 0 { - fmt.Printf("mul_int32 -2147483647%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg2147483647_ssa(0); got != 0 { - fmt.Printf("mul_int32 0%s-2147483647 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg2147483647_int32_ssa(1); got != -2147483647 { - fmt.Printf("mul_int32 -2147483647%s1 = %d, wanted -2147483647\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg2147483647_ssa(1); got != -2147483647 { - fmt.Printf("mul_int32 1%s-2147483647 = %d, wanted -2147483647\n", `*`, got) - failed = true - } - - if got := mul_Neg2147483647_int32_ssa(2147483647); got != -1 { - fmt.Printf("mul_int32 -2147483647%s2147483647 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg2147483647_ssa(2147483647); got != -1 { - fmt.Printf("mul_int32 2147483647%s-2147483647 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int32_ssa(-2147483648); got != -2147483648 { - fmt.Printf("mul_int32 -1%s-2147483648 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg1_ssa(-2147483648); got != -2147483648 { - fmt.Printf("mul_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int32_ssa(-2147483647); got != 2147483647 { - fmt.Printf("mul_int32 -1%s-2147483647 = %d, wanted 2147483647\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg1_ssa(-2147483647); got != 2147483647 { - fmt.Printf("mul_int32 -2147483647%s-1 = %d, wanted 2147483647\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int32_ssa(-1); got != 1 { - fmt.Printf("mul_int32 -1%s-1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg1_ssa(-1); got != 1 { - fmt.Printf("mul_int32 -1%s-1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int32_ssa(0); got != 0 { - fmt.Printf("mul_int32 -1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg1_ssa(0); got != 0 { - fmt.Printf("mul_int32 0%s-1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int32_ssa(1); got != -1 { - fmt.Printf("mul_int32 -1%s1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg1_ssa(1); got != -1 { - fmt.Printf("mul_int32 1%s-1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int32_ssa(2147483647); got != -2147483647 { - fmt.Printf("mul_int32 -1%s2147483647 = %d, wanted -2147483647\n", `*`, got) - failed = true - } - - if got := mul_int32_Neg1_ssa(2147483647); got != -2147483647 { - fmt.Printf("mul_int32 2147483647%s-1 = %d, wanted -2147483647\n", `*`, got) - failed = true - } - - if got := mul_0_int32_ssa(-2147483648); got != 0 { - fmt.Printf("mul_int32 0%s-2147483648 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int32_0_ssa(-2147483648); got != 0 { - fmt.Printf("mul_int32 -2147483648%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int32_ssa(-2147483647); got != 0 { - fmt.Printf("mul_int32 0%s-2147483647 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int32_0_ssa(-2147483647); got != 0 { - fmt.Printf("mul_int32 -2147483647%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int32_ssa(-1); got != 0 { - fmt.Printf("mul_int32 0%s-1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int32_0_ssa(-1); got != 0 { - fmt.Printf("mul_int32 -1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int32_ssa(0); got != 0 { - fmt.Printf("mul_int32 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int32_0_ssa(0); got != 0 { - fmt.Printf("mul_int32 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int32_ssa(1); got != 0 { - fmt.Printf("mul_int32 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int32_0_ssa(1); got != 0 { - fmt.Printf("mul_int32 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int32_ssa(2147483647); got != 0 { - fmt.Printf("mul_int32 0%s2147483647 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int32_0_ssa(2147483647); got != 0 { - fmt.Printf("mul_int32 2147483647%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_int32_ssa(-2147483648); got != -2147483648 { - fmt.Printf("mul_int32 1%s-2147483648 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_int32_1_ssa(-2147483648); got != -2147483648 { - fmt.Printf("mul_int32 -2147483648%s1 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_1_int32_ssa(-2147483647); got != -2147483647 { - fmt.Printf("mul_int32 1%s-2147483647 = %d, wanted -2147483647\n", `*`, got) - failed = true - } - - if got := mul_int32_1_ssa(-2147483647); got != -2147483647 { - fmt.Printf("mul_int32 -2147483647%s1 = %d, wanted -2147483647\n", `*`, got) - failed = true - } - - if got := mul_1_int32_ssa(-1); got != -1 { - fmt.Printf("mul_int32 1%s-1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int32_1_ssa(-1); got != -1 { - fmt.Printf("mul_int32 -1%s1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_1_int32_ssa(0); got != 0 { - fmt.Printf("mul_int32 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int32_1_ssa(0); got != 0 { - fmt.Printf("mul_int32 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_int32_ssa(1); got != 1 { - fmt.Printf("mul_int32 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int32_1_ssa(1); got != 1 { - fmt.Printf("mul_int32 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_1_int32_ssa(2147483647); got != 2147483647 { - fmt.Printf("mul_int32 1%s2147483647 = %d, wanted 2147483647\n", `*`, got) - failed = true - } - - if got := mul_int32_1_ssa(2147483647); got != 2147483647 { - fmt.Printf("mul_int32 2147483647%s1 = %d, wanted 2147483647\n", `*`, got) - failed = true - } - - if got := mul_2147483647_int32_ssa(-2147483648); got != -2147483648 { - fmt.Printf("mul_int32 2147483647%s-2147483648 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_int32_2147483647_ssa(-2147483648); got != -2147483648 { - fmt.Printf("mul_int32 -2147483648%s2147483647 = %d, wanted -2147483648\n", `*`, got) - failed = true - } - - if got := mul_2147483647_int32_ssa(-2147483647); got != -1 { - fmt.Printf("mul_int32 2147483647%s-2147483647 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int32_2147483647_ssa(-2147483647); got != -1 { - fmt.Printf("mul_int32 -2147483647%s2147483647 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_2147483647_int32_ssa(-1); got != -2147483647 { - fmt.Printf("mul_int32 2147483647%s-1 = %d, wanted -2147483647\n", `*`, got) - failed = true - } - - if got := mul_int32_2147483647_ssa(-1); got != -2147483647 { - fmt.Printf("mul_int32 -1%s2147483647 = %d, wanted -2147483647\n", `*`, got) - failed = true - } - - if got := mul_2147483647_int32_ssa(0); got != 0 { - fmt.Printf("mul_int32 2147483647%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int32_2147483647_ssa(0); got != 0 { - fmt.Printf("mul_int32 0%s2147483647 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_2147483647_int32_ssa(1); got != 2147483647 { - fmt.Printf("mul_int32 2147483647%s1 = %d, wanted 2147483647\n", `*`, got) - failed = true - } - - if got := mul_int32_2147483647_ssa(1); got != 2147483647 { - fmt.Printf("mul_int32 1%s2147483647 = %d, wanted 2147483647\n", `*`, got) - failed = true - } - - if got := mul_2147483647_int32_ssa(2147483647); got != 1 { - fmt.Printf("mul_int32 2147483647%s2147483647 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int32_2147483647_ssa(2147483647); got != 1 { - fmt.Printf("mul_int32 2147483647%s2147483647 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mod_Neg2147483648_int32_ssa(-2147483648); got != 0 { - fmt.Printf("mod_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg2147483648_ssa(-2147483648); got != 0 { - fmt.Printf("mod_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg2147483648_int32_ssa(-2147483647); got != -1 { - fmt.Printf("mod_int32 -2147483648%s-2147483647 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg2147483648_ssa(-2147483647); got != -2147483647 { - fmt.Printf("mod_int32 -2147483647%s-2147483648 = %d, wanted -2147483647\n", `%`, got) - failed = true - } - - if got := mod_Neg2147483648_int32_ssa(-1); got != 0 { - fmt.Printf("mod_int32 -2147483648%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg2147483648_ssa(-1); got != -1 { - fmt.Printf("mod_int32 -1%s-2147483648 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg2147483648_ssa(0); got != 0 { - fmt.Printf("mod_int32 0%s-2147483648 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg2147483648_int32_ssa(1); got != 0 { - fmt.Printf("mod_int32 -2147483648%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg2147483648_ssa(1); got != 1 { - fmt.Printf("mod_int32 1%s-2147483648 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_Neg2147483648_int32_ssa(2147483647); got != -1 { - fmt.Printf("mod_int32 -2147483648%s2147483647 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg2147483648_ssa(2147483647); got != 2147483647 { - fmt.Printf("mod_int32 2147483647%s-2147483648 = %d, wanted 2147483647\n", `%`, got) - failed = true - } - - if got := mod_Neg2147483647_int32_ssa(-2147483648); got != -2147483647 { - fmt.Printf("mod_int32 -2147483647%s-2147483648 = %d, wanted -2147483647\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg2147483647_ssa(-2147483648); got != -1 { - fmt.Printf("mod_int32 -2147483648%s-2147483647 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_Neg2147483647_int32_ssa(-2147483647); got != 0 { - fmt.Printf("mod_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg2147483647_ssa(-2147483647); got != 0 { - fmt.Printf("mod_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg2147483647_int32_ssa(-1); got != 0 { - fmt.Printf("mod_int32 -2147483647%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg2147483647_ssa(-1); got != -1 { - fmt.Printf("mod_int32 -1%s-2147483647 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg2147483647_ssa(0); got != 0 { - fmt.Printf("mod_int32 0%s-2147483647 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg2147483647_int32_ssa(1); got != 0 { - fmt.Printf("mod_int32 -2147483647%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg2147483647_ssa(1); got != 1 { - fmt.Printf("mod_int32 1%s-2147483647 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_Neg2147483647_int32_ssa(2147483647); got != 0 { - fmt.Printf("mod_int32 -2147483647%s2147483647 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg2147483647_ssa(2147483647); got != 0 { - fmt.Printf("mod_int32 2147483647%s-2147483647 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int32_ssa(-2147483648); got != -1 { - fmt.Printf("mod_int32 -1%s-2147483648 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg1_ssa(-2147483648); got != 0 { - fmt.Printf("mod_int32 -2147483648%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int32_ssa(-2147483647); got != -1 { - fmt.Printf("mod_int32 -1%s-2147483647 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg1_ssa(-2147483647); got != 0 { - fmt.Printf("mod_int32 -2147483647%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int32_ssa(-1); got != 0 { - fmt.Printf("mod_int32 -1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg1_ssa(-1); got != 0 { - fmt.Printf("mod_int32 -1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg1_ssa(0); got != 0 { - fmt.Printf("mod_int32 0%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int32_ssa(1); got != 0 { - fmt.Printf("mod_int32 -1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg1_ssa(1); got != 0 { - fmt.Printf("mod_int32 1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int32_ssa(2147483647); got != -1 { - fmt.Printf("mod_int32 -1%s2147483647 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int32_Neg1_ssa(2147483647); got != 0 { - fmt.Printf("mod_int32 2147483647%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int32_ssa(-2147483648); got != 0 { - fmt.Printf("mod_int32 0%s-2147483648 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int32_ssa(-2147483647); got != 0 { - fmt.Printf("mod_int32 0%s-2147483647 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int32_ssa(-1); got != 0 { - fmt.Printf("mod_int32 0%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int32_ssa(1); got != 0 { - fmt.Printf("mod_int32 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int32_ssa(2147483647); got != 0 { - fmt.Printf("mod_int32 0%s2147483647 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int32_ssa(-2147483648); got != 1 { - fmt.Printf("mod_int32 1%s-2147483648 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int32_1_ssa(-2147483648); got != 0 { - fmt.Printf("mod_int32 -2147483648%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int32_ssa(-2147483647); got != 1 { - fmt.Printf("mod_int32 1%s-2147483647 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int32_1_ssa(-2147483647); got != 0 { - fmt.Printf("mod_int32 -2147483647%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int32_ssa(-1); got != 0 { - fmt.Printf("mod_int32 1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_1_ssa(-1); got != 0 { - fmt.Printf("mod_int32 -1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_1_ssa(0); got != 0 { - fmt.Printf("mod_int32 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int32_ssa(1); got != 0 { - fmt.Printf("mod_int32 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_1_ssa(1); got != 0 { - fmt.Printf("mod_int32 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int32_ssa(2147483647); got != 1 { - fmt.Printf("mod_int32 1%s2147483647 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int32_1_ssa(2147483647); got != 0 { - fmt.Printf("mod_int32 2147483647%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_2147483647_int32_ssa(-2147483648); got != 2147483647 { - fmt.Printf("mod_int32 2147483647%s-2147483648 = %d, wanted 2147483647\n", `%`, got) - failed = true - } - - if got := mod_int32_2147483647_ssa(-2147483648); got != -1 { - fmt.Printf("mod_int32 -2147483648%s2147483647 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_2147483647_int32_ssa(-2147483647); got != 0 { - fmt.Printf("mod_int32 2147483647%s-2147483647 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_2147483647_ssa(-2147483647); got != 0 { - fmt.Printf("mod_int32 -2147483647%s2147483647 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_2147483647_int32_ssa(-1); got != 0 { - fmt.Printf("mod_int32 2147483647%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_2147483647_ssa(-1); got != -1 { - fmt.Printf("mod_int32 -1%s2147483647 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int32_2147483647_ssa(0); got != 0 { - fmt.Printf("mod_int32 0%s2147483647 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_2147483647_int32_ssa(1); got != 0 { - fmt.Printf("mod_int32 2147483647%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_2147483647_ssa(1); got != 1 { - fmt.Printf("mod_int32 1%s2147483647 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_2147483647_int32_ssa(2147483647); got != 0 { - fmt.Printf("mod_int32 2147483647%s2147483647 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int32_2147483647_ssa(2147483647); got != 0 { - fmt.Printf("mod_int32 2147483647%s2147483647 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := and_Neg2147483648_int32_ssa(-2147483648); got != -2147483648 { - fmt.Printf("and_int32 -2147483648%s-2147483648 = %d, wanted -2147483648\n", `&`, got) - failed = true - } - - if got := and_int32_Neg2147483648_ssa(-2147483648); got != -2147483648 { - fmt.Printf("and_int32 -2147483648%s-2147483648 = %d, wanted -2147483648\n", `&`, got) - failed = true - } - - if got := and_Neg2147483648_int32_ssa(-2147483647); got != -2147483648 { - fmt.Printf("and_int32 -2147483648%s-2147483647 = %d, wanted -2147483648\n", `&`, got) - failed = true - } - - if got := and_int32_Neg2147483648_ssa(-2147483647); got != -2147483648 { - fmt.Printf("and_int32 -2147483647%s-2147483648 = %d, wanted -2147483648\n", `&`, got) - failed = true - } - - if got := and_Neg2147483648_int32_ssa(-1); got != -2147483648 { - fmt.Printf("and_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `&`, got) - failed = true - } - - if got := and_int32_Neg2147483648_ssa(-1); got != -2147483648 { - fmt.Printf("and_int32 -1%s-2147483648 = %d, wanted -2147483648\n", `&`, got) - failed = true - } - - if got := and_Neg2147483648_int32_ssa(0); got != 0 { - fmt.Printf("and_int32 -2147483648%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_Neg2147483648_ssa(0); got != 0 { - fmt.Printf("and_int32 0%s-2147483648 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg2147483648_int32_ssa(1); got != 0 { - fmt.Printf("and_int32 -2147483648%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_Neg2147483648_ssa(1); got != 0 { - fmt.Printf("and_int32 1%s-2147483648 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg2147483648_int32_ssa(2147483647); got != 0 { - fmt.Printf("and_int32 -2147483648%s2147483647 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_Neg2147483648_ssa(2147483647); got != 0 { - fmt.Printf("and_int32 2147483647%s-2147483648 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg2147483647_int32_ssa(-2147483648); got != -2147483648 { - fmt.Printf("and_int32 -2147483647%s-2147483648 = %d, wanted -2147483648\n", `&`, got) - failed = true - } - - if got := and_int32_Neg2147483647_ssa(-2147483648); got != -2147483648 { - fmt.Printf("and_int32 -2147483648%s-2147483647 = %d, wanted -2147483648\n", `&`, got) - failed = true - } - - if got := and_Neg2147483647_int32_ssa(-2147483647); got != -2147483647 { - fmt.Printf("and_int32 -2147483647%s-2147483647 = %d, wanted -2147483647\n", `&`, got) - failed = true - } - - if got := and_int32_Neg2147483647_ssa(-2147483647); got != -2147483647 { - fmt.Printf("and_int32 -2147483647%s-2147483647 = %d, wanted -2147483647\n", `&`, got) - failed = true - } - - if got := and_Neg2147483647_int32_ssa(-1); got != -2147483647 { - fmt.Printf("and_int32 -2147483647%s-1 = %d, wanted -2147483647\n", `&`, got) - failed = true - } - - if got := and_int32_Neg2147483647_ssa(-1); got != -2147483647 { - fmt.Printf("and_int32 -1%s-2147483647 = %d, wanted -2147483647\n", `&`, got) - failed = true - } - - if got := and_Neg2147483647_int32_ssa(0); got != 0 { - fmt.Printf("and_int32 -2147483647%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_Neg2147483647_ssa(0); got != 0 { - fmt.Printf("and_int32 0%s-2147483647 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg2147483647_int32_ssa(1); got != 1 { - fmt.Printf("and_int32 -2147483647%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int32_Neg2147483647_ssa(1); got != 1 { - fmt.Printf("and_int32 1%s-2147483647 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_Neg2147483647_int32_ssa(2147483647); got != 1 { - fmt.Printf("and_int32 -2147483647%s2147483647 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int32_Neg2147483647_ssa(2147483647); got != 1 { - fmt.Printf("and_int32 2147483647%s-2147483647 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_Neg1_int32_ssa(-2147483648); got != -2147483648 { - fmt.Printf("and_int32 -1%s-2147483648 = %d, wanted -2147483648\n", `&`, got) - failed = true - } - - if got := and_int32_Neg1_ssa(-2147483648); got != -2147483648 { - fmt.Printf("and_int32 -2147483648%s-1 = %d, wanted -2147483648\n", `&`, got) - failed = true - } - - if got := and_Neg1_int32_ssa(-2147483647); got != -2147483647 { - fmt.Printf("and_int32 -1%s-2147483647 = %d, wanted -2147483647\n", `&`, got) - failed = true - } - - if got := and_int32_Neg1_ssa(-2147483647); got != -2147483647 { - fmt.Printf("and_int32 -2147483647%s-1 = %d, wanted -2147483647\n", `&`, got) - failed = true - } - - if got := and_Neg1_int32_ssa(-1); got != -1 { - fmt.Printf("and_int32 -1%s-1 = %d, wanted -1\n", `&`, got) - failed = true - } - - if got := and_int32_Neg1_ssa(-1); got != -1 { - fmt.Printf("and_int32 -1%s-1 = %d, wanted -1\n", `&`, got) - failed = true - } - - if got := and_Neg1_int32_ssa(0); got != 0 { - fmt.Printf("and_int32 -1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_Neg1_ssa(0); got != 0 { - fmt.Printf("and_int32 0%s-1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg1_int32_ssa(1); got != 1 { - fmt.Printf("and_int32 -1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int32_Neg1_ssa(1); got != 1 { - fmt.Printf("and_int32 1%s-1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_Neg1_int32_ssa(2147483647); got != 2147483647 { - fmt.Printf("and_int32 -1%s2147483647 = %d, wanted 2147483647\n", `&`, got) - failed = true - } - - if got := and_int32_Neg1_ssa(2147483647); got != 2147483647 { - fmt.Printf("and_int32 2147483647%s-1 = %d, wanted 2147483647\n", `&`, got) - failed = true - } - - if got := and_0_int32_ssa(-2147483648); got != 0 { - fmt.Printf("and_int32 0%s-2147483648 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_0_ssa(-2147483648); got != 0 { - fmt.Printf("and_int32 -2147483648%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int32_ssa(-2147483647); got != 0 { - fmt.Printf("and_int32 0%s-2147483647 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_0_ssa(-2147483647); got != 0 { - fmt.Printf("and_int32 -2147483647%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int32_ssa(-1); got != 0 { - fmt.Printf("and_int32 0%s-1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_0_ssa(-1); got != 0 { - fmt.Printf("and_int32 -1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int32_ssa(0); got != 0 { - fmt.Printf("and_int32 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_0_ssa(0); got != 0 { - fmt.Printf("and_int32 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int32_ssa(1); got != 0 { - fmt.Printf("and_int32 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_0_ssa(1); got != 0 { - fmt.Printf("and_int32 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int32_ssa(2147483647); got != 0 { - fmt.Printf("and_int32 0%s2147483647 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_0_ssa(2147483647); got != 0 { - fmt.Printf("and_int32 2147483647%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int32_ssa(-2147483648); got != 0 { - fmt.Printf("and_int32 1%s-2147483648 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_1_ssa(-2147483648); got != 0 { - fmt.Printf("and_int32 -2147483648%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int32_ssa(-2147483647); got != 1 { - fmt.Printf("and_int32 1%s-2147483647 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int32_1_ssa(-2147483647); got != 1 { - fmt.Printf("and_int32 -2147483647%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_int32_ssa(-1); got != 1 { - fmt.Printf("and_int32 1%s-1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int32_1_ssa(-1); got != 1 { - fmt.Printf("and_int32 -1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_int32_ssa(0); got != 0 { - fmt.Printf("and_int32 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_1_ssa(0); got != 0 { - fmt.Printf("and_int32 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int32_ssa(1); got != 1 { - fmt.Printf("and_int32 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int32_1_ssa(1); got != 1 { - fmt.Printf("and_int32 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_int32_ssa(2147483647); got != 1 { - fmt.Printf("and_int32 1%s2147483647 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int32_1_ssa(2147483647); got != 1 { - fmt.Printf("and_int32 2147483647%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_2147483647_int32_ssa(-2147483648); got != 0 { - fmt.Printf("and_int32 2147483647%s-2147483648 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_2147483647_ssa(-2147483648); got != 0 { - fmt.Printf("and_int32 -2147483648%s2147483647 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_2147483647_int32_ssa(-2147483647); got != 1 { - fmt.Printf("and_int32 2147483647%s-2147483647 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int32_2147483647_ssa(-2147483647); got != 1 { - fmt.Printf("and_int32 -2147483647%s2147483647 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_2147483647_int32_ssa(-1); got != 2147483647 { - fmt.Printf("and_int32 2147483647%s-1 = %d, wanted 2147483647\n", `&`, got) - failed = true - } - - if got := and_int32_2147483647_ssa(-1); got != 2147483647 { - fmt.Printf("and_int32 -1%s2147483647 = %d, wanted 2147483647\n", `&`, got) - failed = true - } - - if got := and_2147483647_int32_ssa(0); got != 0 { - fmt.Printf("and_int32 2147483647%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int32_2147483647_ssa(0); got != 0 { - fmt.Printf("and_int32 0%s2147483647 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_2147483647_int32_ssa(1); got != 1 { - fmt.Printf("and_int32 2147483647%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int32_2147483647_ssa(1); got != 1 { - fmt.Printf("and_int32 1%s2147483647 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_2147483647_int32_ssa(2147483647); got != 2147483647 { - fmt.Printf("and_int32 2147483647%s2147483647 = %d, wanted 2147483647\n", `&`, got) - failed = true - } - - if got := and_int32_2147483647_ssa(2147483647); got != 2147483647 { - fmt.Printf("and_int32 2147483647%s2147483647 = %d, wanted 2147483647\n", `&`, got) - failed = true - } - - if got := or_Neg2147483648_int32_ssa(-2147483648); got != -2147483648 { - fmt.Printf("or_int32 -2147483648%s-2147483648 = %d, wanted -2147483648\n", `|`, got) - failed = true - } - - if got := or_int32_Neg2147483648_ssa(-2147483648); got != -2147483648 { - fmt.Printf("or_int32 -2147483648%s-2147483648 = %d, wanted -2147483648\n", `|`, got) - failed = true - } - - if got := or_Neg2147483648_int32_ssa(-2147483647); got != -2147483647 { - fmt.Printf("or_int32 -2147483648%s-2147483647 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_Neg2147483648_ssa(-2147483647); got != -2147483647 { - fmt.Printf("or_int32 -2147483647%s-2147483648 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_Neg2147483648_int32_ssa(-1); got != -1 { - fmt.Printf("or_int32 -2147483648%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_Neg2147483648_ssa(-1); got != -1 { - fmt.Printf("or_int32 -1%s-2147483648 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg2147483648_int32_ssa(0); got != -2147483648 { - fmt.Printf("or_int32 -2147483648%s0 = %d, wanted -2147483648\n", `|`, got) - failed = true - } - - if got := or_int32_Neg2147483648_ssa(0); got != -2147483648 { - fmt.Printf("or_int32 0%s-2147483648 = %d, wanted -2147483648\n", `|`, got) - failed = true - } - - if got := or_Neg2147483648_int32_ssa(1); got != -2147483647 { - fmt.Printf("or_int32 -2147483648%s1 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_Neg2147483648_ssa(1); got != -2147483647 { - fmt.Printf("or_int32 1%s-2147483648 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_Neg2147483648_int32_ssa(2147483647); got != -1 { - fmt.Printf("or_int32 -2147483648%s2147483647 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_Neg2147483648_ssa(2147483647); got != -1 { - fmt.Printf("or_int32 2147483647%s-2147483648 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg2147483647_int32_ssa(-2147483648); got != -2147483647 { - fmt.Printf("or_int32 -2147483647%s-2147483648 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_Neg2147483647_ssa(-2147483648); got != -2147483647 { - fmt.Printf("or_int32 -2147483648%s-2147483647 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_Neg2147483647_int32_ssa(-2147483647); got != -2147483647 { - fmt.Printf("or_int32 -2147483647%s-2147483647 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_Neg2147483647_ssa(-2147483647); got != -2147483647 { - fmt.Printf("or_int32 -2147483647%s-2147483647 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_Neg2147483647_int32_ssa(-1); got != -1 { - fmt.Printf("or_int32 -2147483647%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_Neg2147483647_ssa(-1); got != -1 { - fmt.Printf("or_int32 -1%s-2147483647 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg2147483647_int32_ssa(0); got != -2147483647 { - fmt.Printf("or_int32 -2147483647%s0 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_Neg2147483647_ssa(0); got != -2147483647 { - fmt.Printf("or_int32 0%s-2147483647 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_Neg2147483647_int32_ssa(1); got != -2147483647 { - fmt.Printf("or_int32 -2147483647%s1 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_Neg2147483647_ssa(1); got != -2147483647 { - fmt.Printf("or_int32 1%s-2147483647 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_Neg2147483647_int32_ssa(2147483647); got != -1 { - fmt.Printf("or_int32 -2147483647%s2147483647 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_Neg2147483647_ssa(2147483647); got != -1 { - fmt.Printf("or_int32 2147483647%s-2147483647 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int32_ssa(-2147483648); got != -1 { - fmt.Printf("or_int32 -1%s-2147483648 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_Neg1_ssa(-2147483648); got != -1 { - fmt.Printf("or_int32 -2147483648%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int32_ssa(-2147483647); got != -1 { - fmt.Printf("or_int32 -1%s-2147483647 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_Neg1_ssa(-2147483647); got != -1 { - fmt.Printf("or_int32 -2147483647%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int32_ssa(-1); got != -1 { - fmt.Printf("or_int32 -1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_Neg1_ssa(-1); got != -1 { - fmt.Printf("or_int32 -1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int32_ssa(0); got != -1 { - fmt.Printf("or_int32 -1%s0 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_Neg1_ssa(0); got != -1 { - fmt.Printf("or_int32 0%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int32_ssa(1); got != -1 { - fmt.Printf("or_int32 -1%s1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_Neg1_ssa(1); got != -1 { - fmt.Printf("or_int32 1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int32_ssa(2147483647); got != -1 { - fmt.Printf("or_int32 -1%s2147483647 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_Neg1_ssa(2147483647); got != -1 { - fmt.Printf("or_int32 2147483647%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_0_int32_ssa(-2147483648); got != -2147483648 { - fmt.Printf("or_int32 0%s-2147483648 = %d, wanted -2147483648\n", `|`, got) - failed = true - } - - if got := or_int32_0_ssa(-2147483648); got != -2147483648 { - fmt.Printf("or_int32 -2147483648%s0 = %d, wanted -2147483648\n", `|`, got) - failed = true - } - - if got := or_0_int32_ssa(-2147483647); got != -2147483647 { - fmt.Printf("or_int32 0%s-2147483647 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_0_ssa(-2147483647); got != -2147483647 { - fmt.Printf("or_int32 -2147483647%s0 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_0_int32_ssa(-1); got != -1 { - fmt.Printf("or_int32 0%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_0_ssa(-1); got != -1 { - fmt.Printf("or_int32 -1%s0 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_0_int32_ssa(0); got != 0 { - fmt.Printf("or_int32 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_int32_0_ssa(0); got != 0 { - fmt.Printf("or_int32 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_0_int32_ssa(1); got != 1 { - fmt.Printf("or_int32 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_int32_0_ssa(1); got != 1 { - fmt.Printf("or_int32 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_0_int32_ssa(2147483647); got != 2147483647 { - fmt.Printf("or_int32 0%s2147483647 = %d, wanted 2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_0_ssa(2147483647); got != 2147483647 { - fmt.Printf("or_int32 2147483647%s0 = %d, wanted 2147483647\n", `|`, got) - failed = true - } - - if got := or_1_int32_ssa(-2147483648); got != -2147483647 { - fmt.Printf("or_int32 1%s-2147483648 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_1_ssa(-2147483648); got != -2147483647 { - fmt.Printf("or_int32 -2147483648%s1 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_1_int32_ssa(-2147483647); got != -2147483647 { - fmt.Printf("or_int32 1%s-2147483647 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_1_ssa(-2147483647); got != -2147483647 { - fmt.Printf("or_int32 -2147483647%s1 = %d, wanted -2147483647\n", `|`, got) - failed = true - } - - if got := or_1_int32_ssa(-1); got != -1 { - fmt.Printf("or_int32 1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_1_ssa(-1); got != -1 { - fmt.Printf("or_int32 -1%s1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_1_int32_ssa(0); got != 1 { - fmt.Printf("or_int32 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_int32_1_ssa(0); got != 1 { - fmt.Printf("or_int32 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_int32_ssa(1); got != 1 { - fmt.Printf("or_int32 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_int32_1_ssa(1); got != 1 { - fmt.Printf("or_int32 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_int32_ssa(2147483647); got != 2147483647 { - fmt.Printf("or_int32 1%s2147483647 = %d, wanted 2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_1_ssa(2147483647); got != 2147483647 { - fmt.Printf("or_int32 2147483647%s1 = %d, wanted 2147483647\n", `|`, got) - failed = true - } - - if got := or_2147483647_int32_ssa(-2147483648); got != -1 { - fmt.Printf("or_int32 2147483647%s-2147483648 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_2147483647_ssa(-2147483648); got != -1 { - fmt.Printf("or_int32 -2147483648%s2147483647 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_2147483647_int32_ssa(-2147483647); got != -1 { - fmt.Printf("or_int32 2147483647%s-2147483647 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_2147483647_ssa(-2147483647); got != -1 { - fmt.Printf("or_int32 -2147483647%s2147483647 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_2147483647_int32_ssa(-1); got != -1 { - fmt.Printf("or_int32 2147483647%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int32_2147483647_ssa(-1); got != -1 { - fmt.Printf("or_int32 -1%s2147483647 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_2147483647_int32_ssa(0); got != 2147483647 { - fmt.Printf("or_int32 2147483647%s0 = %d, wanted 2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_2147483647_ssa(0); got != 2147483647 { - fmt.Printf("or_int32 0%s2147483647 = %d, wanted 2147483647\n", `|`, got) - failed = true - } - - if got := or_2147483647_int32_ssa(1); got != 2147483647 { - fmt.Printf("or_int32 2147483647%s1 = %d, wanted 2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_2147483647_ssa(1); got != 2147483647 { - fmt.Printf("or_int32 1%s2147483647 = %d, wanted 2147483647\n", `|`, got) - failed = true - } - - if got := or_2147483647_int32_ssa(2147483647); got != 2147483647 { - fmt.Printf("or_int32 2147483647%s2147483647 = %d, wanted 2147483647\n", `|`, got) - failed = true - } - - if got := or_int32_2147483647_ssa(2147483647); got != 2147483647 { - fmt.Printf("or_int32 2147483647%s2147483647 = %d, wanted 2147483647\n", `|`, got) - failed = true - } - - if got := xor_Neg2147483648_int32_ssa(-2147483648); got != 0 { - fmt.Printf("xor_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg2147483648_ssa(-2147483648); got != 0 { - fmt.Printf("xor_int32 -2147483648%s-2147483648 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_Neg2147483648_int32_ssa(-2147483647); got != 1 { - fmt.Printf("xor_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg2147483648_ssa(-2147483647); got != 1 { - fmt.Printf("xor_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_Neg2147483648_int32_ssa(-1); got != 2147483647 { - fmt.Printf("xor_int32 -2147483648%s-1 = %d, wanted 2147483647\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg2147483648_ssa(-1); got != 2147483647 { - fmt.Printf("xor_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `^`, got) - failed = true - } - - if got := xor_Neg2147483648_int32_ssa(0); got != -2147483648 { - fmt.Printf("xor_int32 -2147483648%s0 = %d, wanted -2147483648\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg2147483648_ssa(0); got != -2147483648 { - fmt.Printf("xor_int32 0%s-2147483648 = %d, wanted -2147483648\n", `^`, got) - failed = true - } - - if got := xor_Neg2147483648_int32_ssa(1); got != -2147483647 { - fmt.Printf("xor_int32 -2147483648%s1 = %d, wanted -2147483647\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg2147483648_ssa(1); got != -2147483647 { - fmt.Printf("xor_int32 1%s-2147483648 = %d, wanted -2147483647\n", `^`, got) - failed = true - } - - if got := xor_Neg2147483648_int32_ssa(2147483647); got != -1 { - fmt.Printf("xor_int32 -2147483648%s2147483647 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg2147483648_ssa(2147483647); got != -1 { - fmt.Printf("xor_int32 2147483647%s-2147483648 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_Neg2147483647_int32_ssa(-2147483648); got != 1 { - fmt.Printf("xor_int32 -2147483647%s-2147483648 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg2147483647_ssa(-2147483648); got != 1 { - fmt.Printf("xor_int32 -2147483648%s-2147483647 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_Neg2147483647_int32_ssa(-2147483647); got != 0 { - fmt.Printf("xor_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg2147483647_ssa(-2147483647); got != 0 { - fmt.Printf("xor_int32 -2147483647%s-2147483647 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_Neg2147483647_int32_ssa(-1); got != 2147483646 { - fmt.Printf("xor_int32 -2147483647%s-1 = %d, wanted 2147483646\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg2147483647_ssa(-1); got != 2147483646 { - fmt.Printf("xor_int32 -1%s-2147483647 = %d, wanted 2147483646\n", `^`, got) - failed = true - } - - if got := xor_Neg2147483647_int32_ssa(0); got != -2147483647 { - fmt.Printf("xor_int32 -2147483647%s0 = %d, wanted -2147483647\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg2147483647_ssa(0); got != -2147483647 { - fmt.Printf("xor_int32 0%s-2147483647 = %d, wanted -2147483647\n", `^`, got) - failed = true - } - - if got := xor_Neg2147483647_int32_ssa(1); got != -2147483648 { - fmt.Printf("xor_int32 -2147483647%s1 = %d, wanted -2147483648\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg2147483647_ssa(1); got != -2147483648 { - fmt.Printf("xor_int32 1%s-2147483647 = %d, wanted -2147483648\n", `^`, got) - failed = true - } - - if got := xor_Neg2147483647_int32_ssa(2147483647); got != -2 { - fmt.Printf("xor_int32 -2147483647%s2147483647 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg2147483647_ssa(2147483647); got != -2 { - fmt.Printf("xor_int32 2147483647%s-2147483647 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int32_ssa(-2147483648); got != 2147483647 { - fmt.Printf("xor_int32 -1%s-2147483648 = %d, wanted 2147483647\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg1_ssa(-2147483648); got != 2147483647 { - fmt.Printf("xor_int32 -2147483648%s-1 = %d, wanted 2147483647\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int32_ssa(-2147483647); got != 2147483646 { - fmt.Printf("xor_int32 -1%s-2147483647 = %d, wanted 2147483646\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg1_ssa(-2147483647); got != 2147483646 { - fmt.Printf("xor_int32 -2147483647%s-1 = %d, wanted 2147483646\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int32_ssa(-1); got != 0 { - fmt.Printf("xor_int32 -1%s-1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg1_ssa(-1); got != 0 { - fmt.Printf("xor_int32 -1%s-1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int32_ssa(0); got != -1 { - fmt.Printf("xor_int32 -1%s0 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg1_ssa(0); got != -1 { - fmt.Printf("xor_int32 0%s-1 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int32_ssa(1); got != -2 { - fmt.Printf("xor_int32 -1%s1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg1_ssa(1); got != -2 { - fmt.Printf("xor_int32 1%s-1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int32_ssa(2147483647); got != -2147483648 { - fmt.Printf("xor_int32 -1%s2147483647 = %d, wanted -2147483648\n", `^`, got) - failed = true - } - - if got := xor_int32_Neg1_ssa(2147483647); got != -2147483648 { - fmt.Printf("xor_int32 2147483647%s-1 = %d, wanted -2147483648\n", `^`, got) - failed = true - } - - if got := xor_0_int32_ssa(-2147483648); got != -2147483648 { - fmt.Printf("xor_int32 0%s-2147483648 = %d, wanted -2147483648\n", `^`, got) - failed = true - } - - if got := xor_int32_0_ssa(-2147483648); got != -2147483648 { - fmt.Printf("xor_int32 -2147483648%s0 = %d, wanted -2147483648\n", `^`, got) - failed = true - } - - if got := xor_0_int32_ssa(-2147483647); got != -2147483647 { - fmt.Printf("xor_int32 0%s-2147483647 = %d, wanted -2147483647\n", `^`, got) - failed = true - } - - if got := xor_int32_0_ssa(-2147483647); got != -2147483647 { - fmt.Printf("xor_int32 -2147483647%s0 = %d, wanted -2147483647\n", `^`, got) - failed = true - } - - if got := xor_0_int32_ssa(-1); got != -1 { - fmt.Printf("xor_int32 0%s-1 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int32_0_ssa(-1); got != -1 { - fmt.Printf("xor_int32 -1%s0 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_0_int32_ssa(0); got != 0 { - fmt.Printf("xor_int32 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int32_0_ssa(0); got != 0 { - fmt.Printf("xor_int32 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_0_int32_ssa(1); got != 1 { - fmt.Printf("xor_int32 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int32_0_ssa(1); got != 1 { - fmt.Printf("xor_int32 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_0_int32_ssa(2147483647); got != 2147483647 { - fmt.Printf("xor_int32 0%s2147483647 = %d, wanted 2147483647\n", `^`, got) - failed = true - } - - if got := xor_int32_0_ssa(2147483647); got != 2147483647 { - fmt.Printf("xor_int32 2147483647%s0 = %d, wanted 2147483647\n", `^`, got) - failed = true - } - - if got := xor_1_int32_ssa(-2147483648); got != -2147483647 { - fmt.Printf("xor_int32 1%s-2147483648 = %d, wanted -2147483647\n", `^`, got) - failed = true - } - - if got := xor_int32_1_ssa(-2147483648); got != -2147483647 { - fmt.Printf("xor_int32 -2147483648%s1 = %d, wanted -2147483647\n", `^`, got) - failed = true - } - - if got := xor_1_int32_ssa(-2147483647); got != -2147483648 { - fmt.Printf("xor_int32 1%s-2147483647 = %d, wanted -2147483648\n", `^`, got) - failed = true - } - - if got := xor_int32_1_ssa(-2147483647); got != -2147483648 { - fmt.Printf("xor_int32 -2147483647%s1 = %d, wanted -2147483648\n", `^`, got) - failed = true - } - - if got := xor_1_int32_ssa(-1); got != -2 { - fmt.Printf("xor_int32 1%s-1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int32_1_ssa(-1); got != -2 { - fmt.Printf("xor_int32 -1%s1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_1_int32_ssa(0); got != 1 { - fmt.Printf("xor_int32 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int32_1_ssa(0); got != 1 { - fmt.Printf("xor_int32 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_1_int32_ssa(1); got != 0 { - fmt.Printf("xor_int32 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int32_1_ssa(1); got != 0 { - fmt.Printf("xor_int32 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_1_int32_ssa(2147483647); got != 2147483646 { - fmt.Printf("xor_int32 1%s2147483647 = %d, wanted 2147483646\n", `^`, got) - failed = true - } - - if got := xor_int32_1_ssa(2147483647); got != 2147483646 { - fmt.Printf("xor_int32 2147483647%s1 = %d, wanted 2147483646\n", `^`, got) - failed = true - } - - if got := xor_2147483647_int32_ssa(-2147483648); got != -1 { - fmt.Printf("xor_int32 2147483647%s-2147483648 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int32_2147483647_ssa(-2147483648); got != -1 { - fmt.Printf("xor_int32 -2147483648%s2147483647 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_2147483647_int32_ssa(-2147483647); got != -2 { - fmt.Printf("xor_int32 2147483647%s-2147483647 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int32_2147483647_ssa(-2147483647); got != -2 { - fmt.Printf("xor_int32 -2147483647%s2147483647 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_2147483647_int32_ssa(-1); got != -2147483648 { - fmt.Printf("xor_int32 2147483647%s-1 = %d, wanted -2147483648\n", `^`, got) - failed = true - } - - if got := xor_int32_2147483647_ssa(-1); got != -2147483648 { - fmt.Printf("xor_int32 -1%s2147483647 = %d, wanted -2147483648\n", `^`, got) - failed = true - } - - if got := xor_2147483647_int32_ssa(0); got != 2147483647 { - fmt.Printf("xor_int32 2147483647%s0 = %d, wanted 2147483647\n", `^`, got) - failed = true - } - - if got := xor_int32_2147483647_ssa(0); got != 2147483647 { - fmt.Printf("xor_int32 0%s2147483647 = %d, wanted 2147483647\n", `^`, got) - failed = true - } - - if got := xor_2147483647_int32_ssa(1); got != 2147483646 { - fmt.Printf("xor_int32 2147483647%s1 = %d, wanted 2147483646\n", `^`, got) - failed = true - } - - if got := xor_int32_2147483647_ssa(1); got != 2147483646 { - fmt.Printf("xor_int32 1%s2147483647 = %d, wanted 2147483646\n", `^`, got) - failed = true - } - - if got := xor_2147483647_int32_ssa(2147483647); got != 0 { - fmt.Printf("xor_int32 2147483647%s2147483647 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int32_2147483647_ssa(2147483647); got != 0 { - fmt.Printf("xor_int32 2147483647%s2147483647 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := add_0_uint16_ssa(0); got != 0 { - fmt.Printf("add_uint16 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_uint16_0_ssa(0); got != 0 { - fmt.Printf("add_uint16 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_0_uint16_ssa(1); got != 1 { - fmt.Printf("add_uint16 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_uint16_0_ssa(1); got != 1 { - fmt.Printf("add_uint16 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_0_uint16_ssa(65535); got != 65535 { - fmt.Printf("add_uint16 0%s65535 = %d, wanted 65535\n", `+`, got) - failed = true - } - - if got := add_uint16_0_ssa(65535); got != 65535 { - fmt.Printf("add_uint16 65535%s0 = %d, wanted 65535\n", `+`, got) - failed = true - } - - if got := add_1_uint16_ssa(0); got != 1 { - fmt.Printf("add_uint16 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_uint16_1_ssa(0); got != 1 { - fmt.Printf("add_uint16 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_1_uint16_ssa(1); got != 2 { - fmt.Printf("add_uint16 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_uint16_1_ssa(1); got != 2 { - fmt.Printf("add_uint16 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_1_uint16_ssa(65535); got != 0 { - fmt.Printf("add_uint16 1%s65535 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_uint16_1_ssa(65535); got != 0 { - fmt.Printf("add_uint16 65535%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_65535_uint16_ssa(0); got != 65535 { - fmt.Printf("add_uint16 65535%s0 = %d, wanted 65535\n", `+`, got) - failed = true - } - - if got := add_uint16_65535_ssa(0); got != 65535 { - fmt.Printf("add_uint16 0%s65535 = %d, wanted 65535\n", `+`, got) - failed = true - } - - if got := add_65535_uint16_ssa(1); got != 0 { - fmt.Printf("add_uint16 65535%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_uint16_65535_ssa(1); got != 0 { - fmt.Printf("add_uint16 1%s65535 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_65535_uint16_ssa(65535); got != 65534 { - fmt.Printf("add_uint16 65535%s65535 = %d, wanted 65534\n", `+`, got) - failed = true - } - - if got := add_uint16_65535_ssa(65535); got != 65534 { - fmt.Printf("add_uint16 65535%s65535 = %d, wanted 65534\n", `+`, got) - failed = true - } - - if got := sub_0_uint16_ssa(0); got != 0 { - fmt.Printf("sub_uint16 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint16_0_ssa(0); got != 0 { - fmt.Printf("sub_uint16 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_0_uint16_ssa(1); got != 65535 { - fmt.Printf("sub_uint16 0%s1 = %d, wanted 65535\n", `-`, got) - failed = true - } - - if got := sub_uint16_0_ssa(1); got != 1 { - fmt.Printf("sub_uint16 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_0_uint16_ssa(65535); got != 1 { - fmt.Printf("sub_uint16 0%s65535 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_uint16_0_ssa(65535); got != 65535 { - fmt.Printf("sub_uint16 65535%s0 = %d, wanted 65535\n", `-`, got) - failed = true - } - - if got := sub_1_uint16_ssa(0); got != 1 { - fmt.Printf("sub_uint16 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_uint16_1_ssa(0); got != 65535 { - fmt.Printf("sub_uint16 0%s1 = %d, wanted 65535\n", `-`, got) - failed = true - } - - if got := sub_1_uint16_ssa(1); got != 0 { - fmt.Printf("sub_uint16 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint16_1_ssa(1); got != 0 { - fmt.Printf("sub_uint16 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_1_uint16_ssa(65535); got != 2 { - fmt.Printf("sub_uint16 1%s65535 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_uint16_1_ssa(65535); got != 65534 { - fmt.Printf("sub_uint16 65535%s1 = %d, wanted 65534\n", `-`, got) - failed = true - } - - if got := sub_65535_uint16_ssa(0); got != 65535 { - fmt.Printf("sub_uint16 65535%s0 = %d, wanted 65535\n", `-`, got) - failed = true - } - - if got := sub_uint16_65535_ssa(0); got != 1 { - fmt.Printf("sub_uint16 0%s65535 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_65535_uint16_ssa(1); got != 65534 { - fmt.Printf("sub_uint16 65535%s1 = %d, wanted 65534\n", `-`, got) - failed = true - } - - if got := sub_uint16_65535_ssa(1); got != 2 { - fmt.Printf("sub_uint16 1%s65535 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_65535_uint16_ssa(65535); got != 0 { - fmt.Printf("sub_uint16 65535%s65535 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint16_65535_ssa(65535); got != 0 { - fmt.Printf("sub_uint16 65535%s65535 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := div_0_uint16_ssa(1); got != 0 { - fmt.Printf("div_uint16 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_uint16_ssa(65535); got != 0 { - fmt.Printf("div_uint16 0%s65535 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_uint16_1_ssa(0); got != 0 { - fmt.Printf("div_uint16 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_1_uint16_ssa(1); got != 1 { - fmt.Printf("div_uint16 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_uint16_1_ssa(1); got != 1 { - fmt.Printf("div_uint16 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_1_uint16_ssa(65535); got != 0 { - fmt.Printf("div_uint16 1%s65535 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_uint16_1_ssa(65535); got != 65535 { - fmt.Printf("div_uint16 65535%s1 = %d, wanted 65535\n", `/`, got) - failed = true - } - - if got := div_uint16_65535_ssa(0); got != 0 { - fmt.Printf("div_uint16 0%s65535 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_65535_uint16_ssa(1); got != 65535 { - fmt.Printf("div_uint16 65535%s1 = %d, wanted 65535\n", `/`, got) - failed = true - } - - if got := div_uint16_65535_ssa(1); got != 0 { - fmt.Printf("div_uint16 1%s65535 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_65535_uint16_ssa(65535); got != 1 { - fmt.Printf("div_uint16 65535%s65535 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_uint16_65535_ssa(65535); got != 1 { - fmt.Printf("div_uint16 65535%s65535 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := mul_0_uint16_ssa(0); got != 0 { - fmt.Printf("mul_uint16 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint16_0_ssa(0); got != 0 { - fmt.Printf("mul_uint16 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_uint16_ssa(1); got != 0 { - fmt.Printf("mul_uint16 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint16_0_ssa(1); got != 0 { - fmt.Printf("mul_uint16 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_uint16_ssa(65535); got != 0 { - fmt.Printf("mul_uint16 0%s65535 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint16_0_ssa(65535); got != 0 { - fmt.Printf("mul_uint16 65535%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_uint16_ssa(0); got != 0 { - fmt.Printf("mul_uint16 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint16_1_ssa(0); got != 0 { - fmt.Printf("mul_uint16 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_uint16_ssa(1); got != 1 { - fmt.Printf("mul_uint16 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_uint16_1_ssa(1); got != 1 { - fmt.Printf("mul_uint16 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_1_uint16_ssa(65535); got != 65535 { - fmt.Printf("mul_uint16 1%s65535 = %d, wanted 65535\n", `*`, got) - failed = true - } - - if got := mul_uint16_1_ssa(65535); got != 65535 { - fmt.Printf("mul_uint16 65535%s1 = %d, wanted 65535\n", `*`, got) - failed = true - } - - if got := mul_65535_uint16_ssa(0); got != 0 { - fmt.Printf("mul_uint16 65535%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint16_65535_ssa(0); got != 0 { - fmt.Printf("mul_uint16 0%s65535 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_65535_uint16_ssa(1); got != 65535 { - fmt.Printf("mul_uint16 65535%s1 = %d, wanted 65535\n", `*`, got) - failed = true - } - - if got := mul_uint16_65535_ssa(1); got != 65535 { - fmt.Printf("mul_uint16 1%s65535 = %d, wanted 65535\n", `*`, got) - failed = true - } - - if got := mul_65535_uint16_ssa(65535); got != 1 { - fmt.Printf("mul_uint16 65535%s65535 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_uint16_65535_ssa(65535); got != 1 { - fmt.Printf("mul_uint16 65535%s65535 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := lsh_0_uint16_ssa(0); got != 0 { - fmt.Printf("lsh_uint16 0%s0 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint16_0_ssa(0); got != 0 { - fmt.Printf("lsh_uint16 0%s0 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_0_uint16_ssa(1); got != 0 { - fmt.Printf("lsh_uint16 0%s1 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint16_0_ssa(1); got != 1 { - fmt.Printf("lsh_uint16 1%s0 = %d, wanted 1\n", `<<`, got) - failed = true - } - - if got := lsh_0_uint16_ssa(65535); got != 0 { - fmt.Printf("lsh_uint16 0%s65535 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint16_0_ssa(65535); got != 65535 { - fmt.Printf("lsh_uint16 65535%s0 = %d, wanted 65535\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint16_ssa(0); got != 1 { - fmt.Printf("lsh_uint16 1%s0 = %d, wanted 1\n", `<<`, got) - failed = true - } - - if got := lsh_uint16_1_ssa(0); got != 0 { - fmt.Printf("lsh_uint16 0%s1 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint16_ssa(1); got != 2 { - fmt.Printf("lsh_uint16 1%s1 = %d, wanted 2\n", `<<`, got) - failed = true - } - - if got := lsh_uint16_1_ssa(1); got != 2 { - fmt.Printf("lsh_uint16 1%s1 = %d, wanted 2\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint16_ssa(65535); got != 0 { - fmt.Printf("lsh_uint16 1%s65535 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint16_1_ssa(65535); got != 65534 { - fmt.Printf("lsh_uint16 65535%s1 = %d, wanted 65534\n", `<<`, got) - failed = true - } - - if got := lsh_65535_uint16_ssa(0); got != 65535 { - fmt.Printf("lsh_uint16 65535%s0 = %d, wanted 65535\n", `<<`, got) - failed = true - } - - if got := lsh_uint16_65535_ssa(0); got != 0 { - fmt.Printf("lsh_uint16 0%s65535 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_65535_uint16_ssa(1); got != 65534 { - fmt.Printf("lsh_uint16 65535%s1 = %d, wanted 65534\n", `<<`, got) - failed = true - } - - if got := lsh_uint16_65535_ssa(1); got != 0 { - fmt.Printf("lsh_uint16 1%s65535 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_65535_uint16_ssa(65535); got != 0 { - fmt.Printf("lsh_uint16 65535%s65535 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint16_65535_ssa(65535); got != 0 { - fmt.Printf("lsh_uint16 65535%s65535 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := rsh_0_uint16_ssa(0); got != 0 { - fmt.Printf("rsh_uint16 0%s0 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint16_0_ssa(0); got != 0 { - fmt.Printf("rsh_uint16 0%s0 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_0_uint16_ssa(1); got != 0 { - fmt.Printf("rsh_uint16 0%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint16_0_ssa(1); got != 1 { - fmt.Printf("rsh_uint16 1%s0 = %d, wanted 1\n", `>>`, got) - failed = true - } - - if got := rsh_0_uint16_ssa(65535); got != 0 { - fmt.Printf("rsh_uint16 0%s65535 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint16_0_ssa(65535); got != 65535 { - fmt.Printf("rsh_uint16 65535%s0 = %d, wanted 65535\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint16_ssa(0); got != 1 { - fmt.Printf("rsh_uint16 1%s0 = %d, wanted 1\n", `>>`, got) - failed = true - } - - if got := rsh_uint16_1_ssa(0); got != 0 { - fmt.Printf("rsh_uint16 0%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint16_ssa(1); got != 0 { - fmt.Printf("rsh_uint16 1%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint16_1_ssa(1); got != 0 { - fmt.Printf("rsh_uint16 1%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint16_ssa(65535); got != 0 { - fmt.Printf("rsh_uint16 1%s65535 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint16_1_ssa(65535); got != 32767 { - fmt.Printf("rsh_uint16 65535%s1 = %d, wanted 32767\n", `>>`, got) - failed = true - } - - if got := rsh_65535_uint16_ssa(0); got != 65535 { - fmt.Printf("rsh_uint16 65535%s0 = %d, wanted 65535\n", `>>`, got) - failed = true - } - - if got := rsh_uint16_65535_ssa(0); got != 0 { - fmt.Printf("rsh_uint16 0%s65535 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_65535_uint16_ssa(1); got != 32767 { - fmt.Printf("rsh_uint16 65535%s1 = %d, wanted 32767\n", `>>`, got) - failed = true - } - - if got := rsh_uint16_65535_ssa(1); got != 0 { - fmt.Printf("rsh_uint16 1%s65535 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_65535_uint16_ssa(65535); got != 0 { - fmt.Printf("rsh_uint16 65535%s65535 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint16_65535_ssa(65535); got != 0 { - fmt.Printf("rsh_uint16 65535%s65535 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := mod_0_uint16_ssa(1); got != 0 { - fmt.Printf("mod_uint16 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_uint16_ssa(65535); got != 0 { - fmt.Printf("mod_uint16 0%s65535 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint16_1_ssa(0); got != 0 { - fmt.Printf("mod_uint16 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_uint16_ssa(1); got != 0 { - fmt.Printf("mod_uint16 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint16_1_ssa(1); got != 0 { - fmt.Printf("mod_uint16 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_uint16_ssa(65535); got != 1 { - fmt.Printf("mod_uint16 1%s65535 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_uint16_1_ssa(65535); got != 0 { - fmt.Printf("mod_uint16 65535%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint16_65535_ssa(0); got != 0 { - fmt.Printf("mod_uint16 0%s65535 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_65535_uint16_ssa(1); got != 0 { - fmt.Printf("mod_uint16 65535%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint16_65535_ssa(1); got != 1 { - fmt.Printf("mod_uint16 1%s65535 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_65535_uint16_ssa(65535); got != 0 { - fmt.Printf("mod_uint16 65535%s65535 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint16_65535_ssa(65535); got != 0 { - fmt.Printf("mod_uint16 65535%s65535 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := and_0_uint16_ssa(0); got != 0 { - fmt.Printf("and_uint16 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint16_0_ssa(0); got != 0 { - fmt.Printf("and_uint16 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_uint16_ssa(1); got != 0 { - fmt.Printf("and_uint16 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint16_0_ssa(1); got != 0 { - fmt.Printf("and_uint16 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_uint16_ssa(65535); got != 0 { - fmt.Printf("and_uint16 0%s65535 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint16_0_ssa(65535); got != 0 { - fmt.Printf("and_uint16 65535%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_uint16_ssa(0); got != 0 { - fmt.Printf("and_uint16 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint16_1_ssa(0); got != 0 { - fmt.Printf("and_uint16 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_uint16_ssa(1); got != 1 { - fmt.Printf("and_uint16 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_uint16_1_ssa(1); got != 1 { - fmt.Printf("and_uint16 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_uint16_ssa(65535); got != 1 { - fmt.Printf("and_uint16 1%s65535 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_uint16_1_ssa(65535); got != 1 { - fmt.Printf("and_uint16 65535%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_65535_uint16_ssa(0); got != 0 { - fmt.Printf("and_uint16 65535%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint16_65535_ssa(0); got != 0 { - fmt.Printf("and_uint16 0%s65535 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_65535_uint16_ssa(1); got != 1 { - fmt.Printf("and_uint16 65535%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_uint16_65535_ssa(1); got != 1 { - fmt.Printf("and_uint16 1%s65535 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_65535_uint16_ssa(65535); got != 65535 { - fmt.Printf("and_uint16 65535%s65535 = %d, wanted 65535\n", `&`, got) - failed = true - } - - if got := and_uint16_65535_ssa(65535); got != 65535 { - fmt.Printf("and_uint16 65535%s65535 = %d, wanted 65535\n", `&`, got) - failed = true - } - - if got := or_0_uint16_ssa(0); got != 0 { - fmt.Printf("or_uint16 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_uint16_0_ssa(0); got != 0 { - fmt.Printf("or_uint16 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_0_uint16_ssa(1); got != 1 { - fmt.Printf("or_uint16 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_uint16_0_ssa(1); got != 1 { - fmt.Printf("or_uint16 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_0_uint16_ssa(65535); got != 65535 { - fmt.Printf("or_uint16 0%s65535 = %d, wanted 65535\n", `|`, got) - failed = true - } - - if got := or_uint16_0_ssa(65535); got != 65535 { - fmt.Printf("or_uint16 65535%s0 = %d, wanted 65535\n", `|`, got) - failed = true - } - - if got := or_1_uint16_ssa(0); got != 1 { - fmt.Printf("or_uint16 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_uint16_1_ssa(0); got != 1 { - fmt.Printf("or_uint16 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_uint16_ssa(1); got != 1 { - fmt.Printf("or_uint16 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_uint16_1_ssa(1); got != 1 { - fmt.Printf("or_uint16 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_uint16_ssa(65535); got != 65535 { - fmt.Printf("or_uint16 1%s65535 = %d, wanted 65535\n", `|`, got) - failed = true - } - - if got := or_uint16_1_ssa(65535); got != 65535 { - fmt.Printf("or_uint16 65535%s1 = %d, wanted 65535\n", `|`, got) - failed = true - } - - if got := or_65535_uint16_ssa(0); got != 65535 { - fmt.Printf("or_uint16 65535%s0 = %d, wanted 65535\n", `|`, got) - failed = true - } - - if got := or_uint16_65535_ssa(0); got != 65535 { - fmt.Printf("or_uint16 0%s65535 = %d, wanted 65535\n", `|`, got) - failed = true - } - - if got := or_65535_uint16_ssa(1); got != 65535 { - fmt.Printf("or_uint16 65535%s1 = %d, wanted 65535\n", `|`, got) - failed = true - } - - if got := or_uint16_65535_ssa(1); got != 65535 { - fmt.Printf("or_uint16 1%s65535 = %d, wanted 65535\n", `|`, got) - failed = true - } - - if got := or_65535_uint16_ssa(65535); got != 65535 { - fmt.Printf("or_uint16 65535%s65535 = %d, wanted 65535\n", `|`, got) - failed = true - } - - if got := or_uint16_65535_ssa(65535); got != 65535 { - fmt.Printf("or_uint16 65535%s65535 = %d, wanted 65535\n", `|`, got) - failed = true - } - - if got := xor_0_uint16_ssa(0); got != 0 { - fmt.Printf("xor_uint16 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint16_0_ssa(0); got != 0 { - fmt.Printf("xor_uint16 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_0_uint16_ssa(1); got != 1 { - fmt.Printf("xor_uint16 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_uint16_0_ssa(1); got != 1 { - fmt.Printf("xor_uint16 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_0_uint16_ssa(65535); got != 65535 { - fmt.Printf("xor_uint16 0%s65535 = %d, wanted 65535\n", `^`, got) - failed = true - } - - if got := xor_uint16_0_ssa(65535); got != 65535 { - fmt.Printf("xor_uint16 65535%s0 = %d, wanted 65535\n", `^`, got) - failed = true - } - - if got := xor_1_uint16_ssa(0); got != 1 { - fmt.Printf("xor_uint16 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_uint16_1_ssa(0); got != 1 { - fmt.Printf("xor_uint16 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_1_uint16_ssa(1); got != 0 { - fmt.Printf("xor_uint16 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint16_1_ssa(1); got != 0 { - fmt.Printf("xor_uint16 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_1_uint16_ssa(65535); got != 65534 { - fmt.Printf("xor_uint16 1%s65535 = %d, wanted 65534\n", `^`, got) - failed = true - } - - if got := xor_uint16_1_ssa(65535); got != 65534 { - fmt.Printf("xor_uint16 65535%s1 = %d, wanted 65534\n", `^`, got) - failed = true - } - - if got := xor_65535_uint16_ssa(0); got != 65535 { - fmt.Printf("xor_uint16 65535%s0 = %d, wanted 65535\n", `^`, got) - failed = true - } - - if got := xor_uint16_65535_ssa(0); got != 65535 { - fmt.Printf("xor_uint16 0%s65535 = %d, wanted 65535\n", `^`, got) - failed = true - } - - if got := xor_65535_uint16_ssa(1); got != 65534 { - fmt.Printf("xor_uint16 65535%s1 = %d, wanted 65534\n", `^`, got) - failed = true - } - - if got := xor_uint16_65535_ssa(1); got != 65534 { - fmt.Printf("xor_uint16 1%s65535 = %d, wanted 65534\n", `^`, got) - failed = true - } - - if got := xor_65535_uint16_ssa(65535); got != 0 { - fmt.Printf("xor_uint16 65535%s65535 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint16_65535_ssa(65535); got != 0 { - fmt.Printf("xor_uint16 65535%s65535 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := add_Neg32768_int16_ssa(-32768); got != 0 { - fmt.Printf("add_int16 -32768%s-32768 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32768_ssa(-32768); got != 0 { - fmt.Printf("add_int16 -32768%s-32768 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_Neg32768_int16_ssa(-32767); got != 1 { - fmt.Printf("add_int16 -32768%s-32767 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32768_ssa(-32767); got != 1 { - fmt.Printf("add_int16 -32767%s-32768 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_Neg32768_int16_ssa(-1); got != 32767 { - fmt.Printf("add_int16 -32768%s-1 = %d, wanted 32767\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32768_ssa(-1); got != 32767 { - fmt.Printf("add_int16 -1%s-32768 = %d, wanted 32767\n", `+`, got) - failed = true - } - - if got := add_Neg32768_int16_ssa(0); got != -32768 { - fmt.Printf("add_int16 -32768%s0 = %d, wanted -32768\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32768_ssa(0); got != -32768 { - fmt.Printf("add_int16 0%s-32768 = %d, wanted -32768\n", `+`, got) - failed = true - } - - if got := add_Neg32768_int16_ssa(1); got != -32767 { - fmt.Printf("add_int16 -32768%s1 = %d, wanted -32767\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32768_ssa(1); got != -32767 { - fmt.Printf("add_int16 1%s-32768 = %d, wanted -32767\n", `+`, got) - failed = true - } - - if got := add_Neg32768_int16_ssa(32766); got != -2 { - fmt.Printf("add_int16 -32768%s32766 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32768_ssa(32766); got != -2 { - fmt.Printf("add_int16 32766%s-32768 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_Neg32768_int16_ssa(32767); got != -1 { - fmt.Printf("add_int16 -32768%s32767 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32768_ssa(32767); got != -1 { - fmt.Printf("add_int16 32767%s-32768 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_Neg32767_int16_ssa(-32768); got != 1 { - fmt.Printf("add_int16 -32767%s-32768 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32767_ssa(-32768); got != 1 { - fmt.Printf("add_int16 -32768%s-32767 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_Neg32767_int16_ssa(-32767); got != 2 { - fmt.Printf("add_int16 -32767%s-32767 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32767_ssa(-32767); got != 2 { - fmt.Printf("add_int16 -32767%s-32767 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_Neg32767_int16_ssa(-1); got != -32768 { - fmt.Printf("add_int16 -32767%s-1 = %d, wanted -32768\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32767_ssa(-1); got != -32768 { - fmt.Printf("add_int16 -1%s-32767 = %d, wanted -32768\n", `+`, got) - failed = true - } - - if got := add_Neg32767_int16_ssa(0); got != -32767 { - fmt.Printf("add_int16 -32767%s0 = %d, wanted -32767\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32767_ssa(0); got != -32767 { - fmt.Printf("add_int16 0%s-32767 = %d, wanted -32767\n", `+`, got) - failed = true - } - - if got := add_Neg32767_int16_ssa(1); got != -32766 { - fmt.Printf("add_int16 -32767%s1 = %d, wanted -32766\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32767_ssa(1); got != -32766 { - fmt.Printf("add_int16 1%s-32767 = %d, wanted -32766\n", `+`, got) - failed = true - } - - if got := add_Neg32767_int16_ssa(32766); got != -1 { - fmt.Printf("add_int16 -32767%s32766 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32767_ssa(32766); got != -1 { - fmt.Printf("add_int16 32766%s-32767 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_Neg32767_int16_ssa(32767); got != 0 { - fmt.Printf("add_int16 -32767%s32767 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int16_Neg32767_ssa(32767); got != 0 { - fmt.Printf("add_int16 32767%s-32767 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_Neg1_int16_ssa(-32768); got != 32767 { - fmt.Printf("add_int16 -1%s-32768 = %d, wanted 32767\n", `+`, got) - failed = true - } - - if got := add_int16_Neg1_ssa(-32768); got != 32767 { - fmt.Printf("add_int16 -32768%s-1 = %d, wanted 32767\n", `+`, got) - failed = true - } - - if got := add_Neg1_int16_ssa(-32767); got != -32768 { - fmt.Printf("add_int16 -1%s-32767 = %d, wanted -32768\n", `+`, got) - failed = true - } - - if got := add_int16_Neg1_ssa(-32767); got != -32768 { - fmt.Printf("add_int16 -32767%s-1 = %d, wanted -32768\n", `+`, got) - failed = true - } - - if got := add_Neg1_int16_ssa(-1); got != -2 { - fmt.Printf("add_int16 -1%s-1 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int16_Neg1_ssa(-1); got != -2 { - fmt.Printf("add_int16 -1%s-1 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_Neg1_int16_ssa(0); got != -1 { - fmt.Printf("add_int16 -1%s0 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int16_Neg1_ssa(0); got != -1 { - fmt.Printf("add_int16 0%s-1 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_Neg1_int16_ssa(1); got != 0 { - fmt.Printf("add_int16 -1%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int16_Neg1_ssa(1); got != 0 { - fmt.Printf("add_int16 1%s-1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_Neg1_int16_ssa(32766); got != 32765 { - fmt.Printf("add_int16 -1%s32766 = %d, wanted 32765\n", `+`, got) - failed = true - } - - if got := add_int16_Neg1_ssa(32766); got != 32765 { - fmt.Printf("add_int16 32766%s-1 = %d, wanted 32765\n", `+`, got) - failed = true - } - - if got := add_Neg1_int16_ssa(32767); got != 32766 { - fmt.Printf("add_int16 -1%s32767 = %d, wanted 32766\n", `+`, got) - failed = true - } - - if got := add_int16_Neg1_ssa(32767); got != 32766 { - fmt.Printf("add_int16 32767%s-1 = %d, wanted 32766\n", `+`, got) - failed = true - } - - if got := add_0_int16_ssa(-32768); got != -32768 { - fmt.Printf("add_int16 0%s-32768 = %d, wanted -32768\n", `+`, got) - failed = true - } - - if got := add_int16_0_ssa(-32768); got != -32768 { - fmt.Printf("add_int16 -32768%s0 = %d, wanted -32768\n", `+`, got) - failed = true - } - - if got := add_0_int16_ssa(-32767); got != -32767 { - fmt.Printf("add_int16 0%s-32767 = %d, wanted -32767\n", `+`, got) - failed = true - } - - if got := add_int16_0_ssa(-32767); got != -32767 { - fmt.Printf("add_int16 -32767%s0 = %d, wanted -32767\n", `+`, got) - failed = true - } - - if got := add_0_int16_ssa(-1); got != -1 { - fmt.Printf("add_int16 0%s-1 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int16_0_ssa(-1); got != -1 { - fmt.Printf("add_int16 -1%s0 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_0_int16_ssa(0); got != 0 { - fmt.Printf("add_int16 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int16_0_ssa(0); got != 0 { - fmt.Printf("add_int16 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_0_int16_ssa(1); got != 1 { - fmt.Printf("add_int16 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int16_0_ssa(1); got != 1 { - fmt.Printf("add_int16 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_0_int16_ssa(32766); got != 32766 { - fmt.Printf("add_int16 0%s32766 = %d, wanted 32766\n", `+`, got) - failed = true - } - - if got := add_int16_0_ssa(32766); got != 32766 { - fmt.Printf("add_int16 32766%s0 = %d, wanted 32766\n", `+`, got) - failed = true - } - - if got := add_0_int16_ssa(32767); got != 32767 { - fmt.Printf("add_int16 0%s32767 = %d, wanted 32767\n", `+`, got) - failed = true - } - - if got := add_int16_0_ssa(32767); got != 32767 { - fmt.Printf("add_int16 32767%s0 = %d, wanted 32767\n", `+`, got) - failed = true - } - - if got := add_1_int16_ssa(-32768); got != -32767 { - fmt.Printf("add_int16 1%s-32768 = %d, wanted -32767\n", `+`, got) - failed = true - } - - if got := add_int16_1_ssa(-32768); got != -32767 { - fmt.Printf("add_int16 -32768%s1 = %d, wanted -32767\n", `+`, got) - failed = true - } - - if got := add_1_int16_ssa(-32767); got != -32766 { - fmt.Printf("add_int16 1%s-32767 = %d, wanted -32766\n", `+`, got) - failed = true - } - - if got := add_int16_1_ssa(-32767); got != -32766 { - fmt.Printf("add_int16 -32767%s1 = %d, wanted -32766\n", `+`, got) - failed = true - } - - if got := add_1_int16_ssa(-1); got != 0 { - fmt.Printf("add_int16 1%s-1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int16_1_ssa(-1); got != 0 { - fmt.Printf("add_int16 -1%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_1_int16_ssa(0); got != 1 { - fmt.Printf("add_int16 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int16_1_ssa(0); got != 1 { - fmt.Printf("add_int16 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_1_int16_ssa(1); got != 2 { - fmt.Printf("add_int16 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_int16_1_ssa(1); got != 2 { - fmt.Printf("add_int16 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_1_int16_ssa(32766); got != 32767 { - fmt.Printf("add_int16 1%s32766 = %d, wanted 32767\n", `+`, got) - failed = true - } - - if got := add_int16_1_ssa(32766); got != 32767 { - fmt.Printf("add_int16 32766%s1 = %d, wanted 32767\n", `+`, got) - failed = true - } - - if got := add_1_int16_ssa(32767); got != -32768 { - fmt.Printf("add_int16 1%s32767 = %d, wanted -32768\n", `+`, got) - failed = true - } - - if got := add_int16_1_ssa(32767); got != -32768 { - fmt.Printf("add_int16 32767%s1 = %d, wanted -32768\n", `+`, got) - failed = true - } - - if got := add_32766_int16_ssa(-32768); got != -2 { - fmt.Printf("add_int16 32766%s-32768 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int16_32766_ssa(-32768); got != -2 { - fmt.Printf("add_int16 -32768%s32766 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_32766_int16_ssa(-32767); got != -1 { - fmt.Printf("add_int16 32766%s-32767 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int16_32766_ssa(-32767); got != -1 { - fmt.Printf("add_int16 -32767%s32766 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_32766_int16_ssa(-1); got != 32765 { - fmt.Printf("add_int16 32766%s-1 = %d, wanted 32765\n", `+`, got) - failed = true - } - - if got := add_int16_32766_ssa(-1); got != 32765 { - fmt.Printf("add_int16 -1%s32766 = %d, wanted 32765\n", `+`, got) - failed = true - } - - if got := add_32766_int16_ssa(0); got != 32766 { - fmt.Printf("add_int16 32766%s0 = %d, wanted 32766\n", `+`, got) - failed = true - } - - if got := add_int16_32766_ssa(0); got != 32766 { - fmt.Printf("add_int16 0%s32766 = %d, wanted 32766\n", `+`, got) - failed = true - } - - if got := add_32766_int16_ssa(1); got != 32767 { - fmt.Printf("add_int16 32766%s1 = %d, wanted 32767\n", `+`, got) - failed = true - } - - if got := add_int16_32766_ssa(1); got != 32767 { - fmt.Printf("add_int16 1%s32766 = %d, wanted 32767\n", `+`, got) - failed = true - } - - if got := add_32766_int16_ssa(32766); got != -4 { - fmt.Printf("add_int16 32766%s32766 = %d, wanted -4\n", `+`, got) - failed = true - } - - if got := add_int16_32766_ssa(32766); got != -4 { - fmt.Printf("add_int16 32766%s32766 = %d, wanted -4\n", `+`, got) - failed = true - } - - if got := add_32766_int16_ssa(32767); got != -3 { - fmt.Printf("add_int16 32766%s32767 = %d, wanted -3\n", `+`, got) - failed = true - } - - if got := add_int16_32766_ssa(32767); got != -3 { - fmt.Printf("add_int16 32767%s32766 = %d, wanted -3\n", `+`, got) - failed = true - } - - if got := add_32767_int16_ssa(-32768); got != -1 { - fmt.Printf("add_int16 32767%s-32768 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int16_32767_ssa(-32768); got != -1 { - fmt.Printf("add_int16 -32768%s32767 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_32767_int16_ssa(-32767); got != 0 { - fmt.Printf("add_int16 32767%s-32767 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int16_32767_ssa(-32767); got != 0 { - fmt.Printf("add_int16 -32767%s32767 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_32767_int16_ssa(-1); got != 32766 { - fmt.Printf("add_int16 32767%s-1 = %d, wanted 32766\n", `+`, got) - failed = true - } - - if got := add_int16_32767_ssa(-1); got != 32766 { - fmt.Printf("add_int16 -1%s32767 = %d, wanted 32766\n", `+`, got) - failed = true - } - - if got := add_32767_int16_ssa(0); got != 32767 { - fmt.Printf("add_int16 32767%s0 = %d, wanted 32767\n", `+`, got) - failed = true - } - - if got := add_int16_32767_ssa(0); got != 32767 { - fmt.Printf("add_int16 0%s32767 = %d, wanted 32767\n", `+`, got) - failed = true - } - - if got := add_32767_int16_ssa(1); got != -32768 { - fmt.Printf("add_int16 32767%s1 = %d, wanted -32768\n", `+`, got) - failed = true - } - - if got := add_int16_32767_ssa(1); got != -32768 { - fmt.Printf("add_int16 1%s32767 = %d, wanted -32768\n", `+`, got) - failed = true - } - - if got := add_32767_int16_ssa(32766); got != -3 { - fmt.Printf("add_int16 32767%s32766 = %d, wanted -3\n", `+`, got) - failed = true - } - - if got := add_int16_32767_ssa(32766); got != -3 { - fmt.Printf("add_int16 32766%s32767 = %d, wanted -3\n", `+`, got) - failed = true - } - - if got := add_32767_int16_ssa(32767); got != -2 { - fmt.Printf("add_int16 32767%s32767 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int16_32767_ssa(32767); got != -2 { - fmt.Printf("add_int16 32767%s32767 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := sub_Neg32768_int16_ssa(-32768); got != 0 { - fmt.Printf("sub_int16 -32768%s-32768 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32768_ssa(-32768); got != 0 { - fmt.Printf("sub_int16 -32768%s-32768 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_Neg32768_int16_ssa(-32767); got != -1 { - fmt.Printf("sub_int16 -32768%s-32767 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32768_ssa(-32767); got != 1 { - fmt.Printf("sub_int16 -32767%s-32768 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_Neg32768_int16_ssa(-1); got != -32767 { - fmt.Printf("sub_int16 -32768%s-1 = %d, wanted -32767\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32768_ssa(-1); got != 32767 { - fmt.Printf("sub_int16 -1%s-32768 = %d, wanted 32767\n", `-`, got) - failed = true - } - - if got := sub_Neg32768_int16_ssa(0); got != -32768 { - fmt.Printf("sub_int16 -32768%s0 = %d, wanted -32768\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32768_ssa(0); got != -32768 { - fmt.Printf("sub_int16 0%s-32768 = %d, wanted -32768\n", `-`, got) - failed = true - } - - if got := sub_Neg32768_int16_ssa(1); got != 32767 { - fmt.Printf("sub_int16 -32768%s1 = %d, wanted 32767\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32768_ssa(1); got != -32767 { - fmt.Printf("sub_int16 1%s-32768 = %d, wanted -32767\n", `-`, got) - failed = true - } - - if got := sub_Neg32768_int16_ssa(32766); got != 2 { - fmt.Printf("sub_int16 -32768%s32766 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32768_ssa(32766); got != -2 { - fmt.Printf("sub_int16 32766%s-32768 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_Neg32768_int16_ssa(32767); got != 1 { - fmt.Printf("sub_int16 -32768%s32767 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32768_ssa(32767); got != -1 { - fmt.Printf("sub_int16 32767%s-32768 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_Neg32767_int16_ssa(-32768); got != 1 { - fmt.Printf("sub_int16 -32767%s-32768 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32767_ssa(-32768); got != -1 { - fmt.Printf("sub_int16 -32768%s-32767 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_Neg32767_int16_ssa(-32767); got != 0 { - fmt.Printf("sub_int16 -32767%s-32767 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32767_ssa(-32767); got != 0 { - fmt.Printf("sub_int16 -32767%s-32767 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_Neg32767_int16_ssa(-1); got != -32766 { - fmt.Printf("sub_int16 -32767%s-1 = %d, wanted -32766\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32767_ssa(-1); got != 32766 { - fmt.Printf("sub_int16 -1%s-32767 = %d, wanted 32766\n", `-`, got) - failed = true - } - - if got := sub_Neg32767_int16_ssa(0); got != -32767 { - fmt.Printf("sub_int16 -32767%s0 = %d, wanted -32767\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32767_ssa(0); got != 32767 { - fmt.Printf("sub_int16 0%s-32767 = %d, wanted 32767\n", `-`, got) - failed = true - } - - if got := sub_Neg32767_int16_ssa(1); got != -32768 { - fmt.Printf("sub_int16 -32767%s1 = %d, wanted -32768\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32767_ssa(1); got != -32768 { - fmt.Printf("sub_int16 1%s-32767 = %d, wanted -32768\n", `-`, got) - failed = true - } - - if got := sub_Neg32767_int16_ssa(32766); got != 3 { - fmt.Printf("sub_int16 -32767%s32766 = %d, wanted 3\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32767_ssa(32766); got != -3 { - fmt.Printf("sub_int16 32766%s-32767 = %d, wanted -3\n", `-`, got) - failed = true - } - - if got := sub_Neg32767_int16_ssa(32767); got != 2 { - fmt.Printf("sub_int16 -32767%s32767 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg32767_ssa(32767); got != -2 { - fmt.Printf("sub_int16 32767%s-32767 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int16_ssa(-32768); got != 32767 { - fmt.Printf("sub_int16 -1%s-32768 = %d, wanted 32767\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg1_ssa(-32768); got != -32767 { - fmt.Printf("sub_int16 -32768%s-1 = %d, wanted -32767\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int16_ssa(-32767); got != 32766 { - fmt.Printf("sub_int16 -1%s-32767 = %d, wanted 32766\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg1_ssa(-32767); got != -32766 { - fmt.Printf("sub_int16 -32767%s-1 = %d, wanted -32766\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int16_ssa(-1); got != 0 { - fmt.Printf("sub_int16 -1%s-1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg1_ssa(-1); got != 0 { - fmt.Printf("sub_int16 -1%s-1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int16_ssa(0); got != -1 { - fmt.Printf("sub_int16 -1%s0 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg1_ssa(0); got != 1 { - fmt.Printf("sub_int16 0%s-1 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int16_ssa(1); got != -2 { - fmt.Printf("sub_int16 -1%s1 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg1_ssa(1); got != 2 { - fmt.Printf("sub_int16 1%s-1 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int16_ssa(32766); got != -32767 { - fmt.Printf("sub_int16 -1%s32766 = %d, wanted -32767\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg1_ssa(32766); got != 32767 { - fmt.Printf("sub_int16 32766%s-1 = %d, wanted 32767\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int16_ssa(32767); got != -32768 { - fmt.Printf("sub_int16 -1%s32767 = %d, wanted -32768\n", `-`, got) - failed = true - } - - if got := sub_int16_Neg1_ssa(32767); got != -32768 { - fmt.Printf("sub_int16 32767%s-1 = %d, wanted -32768\n", `-`, got) - failed = true - } - - if got := sub_0_int16_ssa(-32768); got != -32768 { - fmt.Printf("sub_int16 0%s-32768 = %d, wanted -32768\n", `-`, got) - failed = true - } - - if got := sub_int16_0_ssa(-32768); got != -32768 { - fmt.Printf("sub_int16 -32768%s0 = %d, wanted -32768\n", `-`, got) - failed = true - } - - if got := sub_0_int16_ssa(-32767); got != 32767 { - fmt.Printf("sub_int16 0%s-32767 = %d, wanted 32767\n", `-`, got) - failed = true - } - - if got := sub_int16_0_ssa(-32767); got != -32767 { - fmt.Printf("sub_int16 -32767%s0 = %d, wanted -32767\n", `-`, got) - failed = true - } - - if got := sub_0_int16_ssa(-1); got != 1 { - fmt.Printf("sub_int16 0%s-1 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int16_0_ssa(-1); got != -1 { - fmt.Printf("sub_int16 -1%s0 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_0_int16_ssa(0); got != 0 { - fmt.Printf("sub_int16 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int16_0_ssa(0); got != 0 { - fmt.Printf("sub_int16 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_0_int16_ssa(1); got != -1 { - fmt.Printf("sub_int16 0%s1 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int16_0_ssa(1); got != 1 { - fmt.Printf("sub_int16 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_0_int16_ssa(32766); got != -32766 { - fmt.Printf("sub_int16 0%s32766 = %d, wanted -32766\n", `-`, got) - failed = true - } - - if got := sub_int16_0_ssa(32766); got != 32766 { - fmt.Printf("sub_int16 32766%s0 = %d, wanted 32766\n", `-`, got) - failed = true - } - - if got := sub_0_int16_ssa(32767); got != -32767 { - fmt.Printf("sub_int16 0%s32767 = %d, wanted -32767\n", `-`, got) - failed = true - } - - if got := sub_int16_0_ssa(32767); got != 32767 { - fmt.Printf("sub_int16 32767%s0 = %d, wanted 32767\n", `-`, got) - failed = true - } - - if got := sub_1_int16_ssa(-32768); got != -32767 { - fmt.Printf("sub_int16 1%s-32768 = %d, wanted -32767\n", `-`, got) - failed = true - } - - if got := sub_int16_1_ssa(-32768); got != 32767 { - fmt.Printf("sub_int16 -32768%s1 = %d, wanted 32767\n", `-`, got) - failed = true - } - - if got := sub_1_int16_ssa(-32767); got != -32768 { - fmt.Printf("sub_int16 1%s-32767 = %d, wanted -32768\n", `-`, got) - failed = true - } - - if got := sub_int16_1_ssa(-32767); got != -32768 { - fmt.Printf("sub_int16 -32767%s1 = %d, wanted -32768\n", `-`, got) - failed = true - } - - if got := sub_1_int16_ssa(-1); got != 2 { - fmt.Printf("sub_int16 1%s-1 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_int16_1_ssa(-1); got != -2 { - fmt.Printf("sub_int16 -1%s1 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_1_int16_ssa(0); got != 1 { - fmt.Printf("sub_int16 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int16_1_ssa(0); got != -1 { - fmt.Printf("sub_int16 0%s1 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_1_int16_ssa(1); got != 0 { - fmt.Printf("sub_int16 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int16_1_ssa(1); got != 0 { - fmt.Printf("sub_int16 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_1_int16_ssa(32766); got != -32765 { - fmt.Printf("sub_int16 1%s32766 = %d, wanted -32765\n", `-`, got) - failed = true - } - - if got := sub_int16_1_ssa(32766); got != 32765 { - fmt.Printf("sub_int16 32766%s1 = %d, wanted 32765\n", `-`, got) - failed = true - } - - if got := sub_1_int16_ssa(32767); got != -32766 { - fmt.Printf("sub_int16 1%s32767 = %d, wanted -32766\n", `-`, got) - failed = true - } - - if got := sub_int16_1_ssa(32767); got != 32766 { - fmt.Printf("sub_int16 32767%s1 = %d, wanted 32766\n", `-`, got) - failed = true - } - - if got := sub_32766_int16_ssa(-32768); got != -2 { - fmt.Printf("sub_int16 32766%s-32768 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_int16_32766_ssa(-32768); got != 2 { - fmt.Printf("sub_int16 -32768%s32766 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_32766_int16_ssa(-32767); got != -3 { - fmt.Printf("sub_int16 32766%s-32767 = %d, wanted -3\n", `-`, got) - failed = true - } - - if got := sub_int16_32766_ssa(-32767); got != 3 { - fmt.Printf("sub_int16 -32767%s32766 = %d, wanted 3\n", `-`, got) - failed = true - } - - if got := sub_32766_int16_ssa(-1); got != 32767 { - fmt.Printf("sub_int16 32766%s-1 = %d, wanted 32767\n", `-`, got) - failed = true - } - - if got := sub_int16_32766_ssa(-1); got != -32767 { - fmt.Printf("sub_int16 -1%s32766 = %d, wanted -32767\n", `-`, got) - failed = true - } - - if got := sub_32766_int16_ssa(0); got != 32766 { - fmt.Printf("sub_int16 32766%s0 = %d, wanted 32766\n", `-`, got) - failed = true - } - - if got := sub_int16_32766_ssa(0); got != -32766 { - fmt.Printf("sub_int16 0%s32766 = %d, wanted -32766\n", `-`, got) - failed = true - } - - if got := sub_32766_int16_ssa(1); got != 32765 { - fmt.Printf("sub_int16 32766%s1 = %d, wanted 32765\n", `-`, got) - failed = true - } - - if got := sub_int16_32766_ssa(1); got != -32765 { - fmt.Printf("sub_int16 1%s32766 = %d, wanted -32765\n", `-`, got) - failed = true - } - - if got := sub_32766_int16_ssa(32766); got != 0 { - fmt.Printf("sub_int16 32766%s32766 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int16_32766_ssa(32766); got != 0 { - fmt.Printf("sub_int16 32766%s32766 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_32766_int16_ssa(32767); got != -1 { - fmt.Printf("sub_int16 32766%s32767 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int16_32766_ssa(32767); got != 1 { - fmt.Printf("sub_int16 32767%s32766 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_32767_int16_ssa(-32768); got != -1 { - fmt.Printf("sub_int16 32767%s-32768 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int16_32767_ssa(-32768); got != 1 { - fmt.Printf("sub_int16 -32768%s32767 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_32767_int16_ssa(-32767); got != -2 { - fmt.Printf("sub_int16 32767%s-32767 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_int16_32767_ssa(-32767); got != 2 { - fmt.Printf("sub_int16 -32767%s32767 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_32767_int16_ssa(-1); got != -32768 { - fmt.Printf("sub_int16 32767%s-1 = %d, wanted -32768\n", `-`, got) - failed = true - } - - if got := sub_int16_32767_ssa(-1); got != -32768 { - fmt.Printf("sub_int16 -1%s32767 = %d, wanted -32768\n", `-`, got) - failed = true - } - - if got := sub_32767_int16_ssa(0); got != 32767 { - fmt.Printf("sub_int16 32767%s0 = %d, wanted 32767\n", `-`, got) - failed = true - } - - if got := sub_int16_32767_ssa(0); got != -32767 { - fmt.Printf("sub_int16 0%s32767 = %d, wanted -32767\n", `-`, got) - failed = true - } - - if got := sub_32767_int16_ssa(1); got != 32766 { - fmt.Printf("sub_int16 32767%s1 = %d, wanted 32766\n", `-`, got) - failed = true - } - - if got := sub_int16_32767_ssa(1); got != -32766 { - fmt.Printf("sub_int16 1%s32767 = %d, wanted -32766\n", `-`, got) - failed = true - } - - if got := sub_32767_int16_ssa(32766); got != 1 { - fmt.Printf("sub_int16 32767%s32766 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int16_32767_ssa(32766); got != -1 { - fmt.Printf("sub_int16 32766%s32767 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_32767_int16_ssa(32767); got != 0 { - fmt.Printf("sub_int16 32767%s32767 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int16_32767_ssa(32767); got != 0 { - fmt.Printf("sub_int16 32767%s32767 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := div_Neg32768_int16_ssa(-32768); got != 1 { - fmt.Printf("div_int16 -32768%s-32768 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32768_ssa(-32768); got != 1 { - fmt.Printf("div_int16 -32768%s-32768 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_Neg32768_int16_ssa(-32767); got != 1 { - fmt.Printf("div_int16 -32768%s-32767 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32768_ssa(-32767); got != 0 { - fmt.Printf("div_int16 -32767%s-32768 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg32768_int16_ssa(-1); got != -32768 { - fmt.Printf("div_int16 -32768%s-1 = %d, wanted -32768\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32768_ssa(-1); got != 0 { - fmt.Printf("div_int16 -1%s-32768 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32768_ssa(0); got != 0 { - fmt.Printf("div_int16 0%s-32768 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg32768_int16_ssa(1); got != -32768 { - fmt.Printf("div_int16 -32768%s1 = %d, wanted -32768\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32768_ssa(1); got != 0 { - fmt.Printf("div_int16 1%s-32768 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg32768_int16_ssa(32766); got != -1 { - fmt.Printf("div_int16 -32768%s32766 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32768_ssa(32766); got != 0 { - fmt.Printf("div_int16 32766%s-32768 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg32768_int16_ssa(32767); got != -1 { - fmt.Printf("div_int16 -32768%s32767 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32768_ssa(32767); got != 0 { - fmt.Printf("div_int16 32767%s-32768 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg32767_int16_ssa(-32768); got != 0 { - fmt.Printf("div_int16 -32767%s-32768 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32767_ssa(-32768); got != 1 { - fmt.Printf("div_int16 -32768%s-32767 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_Neg32767_int16_ssa(-32767); got != 1 { - fmt.Printf("div_int16 -32767%s-32767 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32767_ssa(-32767); got != 1 { - fmt.Printf("div_int16 -32767%s-32767 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_Neg32767_int16_ssa(-1); got != 32767 { - fmt.Printf("div_int16 -32767%s-1 = %d, wanted 32767\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32767_ssa(-1); got != 0 { - fmt.Printf("div_int16 -1%s-32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32767_ssa(0); got != 0 { - fmt.Printf("div_int16 0%s-32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg32767_int16_ssa(1); got != -32767 { - fmt.Printf("div_int16 -32767%s1 = %d, wanted -32767\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32767_ssa(1); got != 0 { - fmt.Printf("div_int16 1%s-32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg32767_int16_ssa(32766); got != -1 { - fmt.Printf("div_int16 -32767%s32766 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32767_ssa(32766); got != 0 { - fmt.Printf("div_int16 32766%s-32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg32767_int16_ssa(32767); got != -1 { - fmt.Printf("div_int16 -32767%s32767 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int16_Neg32767_ssa(32767); got != -1 { - fmt.Printf("div_int16 32767%s-32767 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_Neg1_int16_ssa(-32768); got != 0 { - fmt.Printf("div_int16 -1%s-32768 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_Neg1_ssa(-32768); got != -32768 { - fmt.Printf("div_int16 -32768%s-1 = %d, wanted -32768\n", `/`, got) - failed = true - } - - if got := div_Neg1_int16_ssa(-32767); got != 0 { - fmt.Printf("div_int16 -1%s-32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_Neg1_ssa(-32767); got != 32767 { - fmt.Printf("div_int16 -32767%s-1 = %d, wanted 32767\n", `/`, got) - failed = true - } - - if got := div_Neg1_int16_ssa(-1); got != 1 { - fmt.Printf("div_int16 -1%s-1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int16_Neg1_ssa(-1); got != 1 { - fmt.Printf("div_int16 -1%s-1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int16_Neg1_ssa(0); got != 0 { - fmt.Printf("div_int16 0%s-1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg1_int16_ssa(1); got != -1 { - fmt.Printf("div_int16 -1%s1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int16_Neg1_ssa(1); got != -1 { - fmt.Printf("div_int16 1%s-1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_Neg1_int16_ssa(32766); got != 0 { - fmt.Printf("div_int16 -1%s32766 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_Neg1_ssa(32766); got != -32766 { - fmt.Printf("div_int16 32766%s-1 = %d, wanted -32766\n", `/`, got) - failed = true - } - - if got := div_Neg1_int16_ssa(32767); got != 0 { - fmt.Printf("div_int16 -1%s32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_Neg1_ssa(32767); got != -32767 { - fmt.Printf("div_int16 32767%s-1 = %d, wanted -32767\n", `/`, got) - failed = true - } - - if got := div_0_int16_ssa(-32768); got != 0 { - fmt.Printf("div_int16 0%s-32768 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int16_ssa(-32767); got != 0 { - fmt.Printf("div_int16 0%s-32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int16_ssa(-1); got != 0 { - fmt.Printf("div_int16 0%s-1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int16_ssa(1); got != 0 { - fmt.Printf("div_int16 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int16_ssa(32766); got != 0 { - fmt.Printf("div_int16 0%s32766 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int16_ssa(32767); got != 0 { - fmt.Printf("div_int16 0%s32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_1_int16_ssa(-32768); got != 0 { - fmt.Printf("div_int16 1%s-32768 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_1_ssa(-32768); got != -32768 { - fmt.Printf("div_int16 -32768%s1 = %d, wanted -32768\n", `/`, got) - failed = true - } - - if got := div_1_int16_ssa(-32767); got != 0 { - fmt.Printf("div_int16 1%s-32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_1_ssa(-32767); got != -32767 { - fmt.Printf("div_int16 -32767%s1 = %d, wanted -32767\n", `/`, got) - failed = true - } - - if got := div_1_int16_ssa(-1); got != -1 { - fmt.Printf("div_int16 1%s-1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int16_1_ssa(-1); got != -1 { - fmt.Printf("div_int16 -1%s1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int16_1_ssa(0); got != 0 { - fmt.Printf("div_int16 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_1_int16_ssa(1); got != 1 { - fmt.Printf("div_int16 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int16_1_ssa(1); got != 1 { - fmt.Printf("div_int16 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_1_int16_ssa(32766); got != 0 { - fmt.Printf("div_int16 1%s32766 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_1_ssa(32766); got != 32766 { - fmt.Printf("div_int16 32766%s1 = %d, wanted 32766\n", `/`, got) - failed = true - } - - if got := div_1_int16_ssa(32767); got != 0 { - fmt.Printf("div_int16 1%s32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_1_ssa(32767); got != 32767 { - fmt.Printf("div_int16 32767%s1 = %d, wanted 32767\n", `/`, got) - failed = true - } - - if got := div_32766_int16_ssa(-32768); got != 0 { - fmt.Printf("div_int16 32766%s-32768 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_32766_ssa(-32768); got != -1 { - fmt.Printf("div_int16 -32768%s32766 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_32766_int16_ssa(-32767); got != 0 { - fmt.Printf("div_int16 32766%s-32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_32766_ssa(-32767); got != -1 { - fmt.Printf("div_int16 -32767%s32766 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_32766_int16_ssa(-1); got != -32766 { - fmt.Printf("div_int16 32766%s-1 = %d, wanted -32766\n", `/`, got) - failed = true - } - - if got := div_int16_32766_ssa(-1); got != 0 { - fmt.Printf("div_int16 -1%s32766 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_32766_ssa(0); got != 0 { - fmt.Printf("div_int16 0%s32766 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_32766_int16_ssa(1); got != 32766 { - fmt.Printf("div_int16 32766%s1 = %d, wanted 32766\n", `/`, got) - failed = true - } - - if got := div_int16_32766_ssa(1); got != 0 { - fmt.Printf("div_int16 1%s32766 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_32766_int16_ssa(32766); got != 1 { - fmt.Printf("div_int16 32766%s32766 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int16_32766_ssa(32766); got != 1 { - fmt.Printf("div_int16 32766%s32766 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_32766_int16_ssa(32767); got != 0 { - fmt.Printf("div_int16 32766%s32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_32766_ssa(32767); got != 1 { - fmt.Printf("div_int16 32767%s32766 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_32767_int16_ssa(-32768); got != 0 { - fmt.Printf("div_int16 32767%s-32768 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_32767_ssa(-32768); got != -1 { - fmt.Printf("div_int16 -32768%s32767 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_32767_int16_ssa(-32767); got != -1 { - fmt.Printf("div_int16 32767%s-32767 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int16_32767_ssa(-32767); got != -1 { - fmt.Printf("div_int16 -32767%s32767 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_32767_int16_ssa(-1); got != -32767 { - fmt.Printf("div_int16 32767%s-1 = %d, wanted -32767\n", `/`, got) - failed = true - } - - if got := div_int16_32767_ssa(-1); got != 0 { - fmt.Printf("div_int16 -1%s32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int16_32767_ssa(0); got != 0 { - fmt.Printf("div_int16 0%s32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_32767_int16_ssa(1); got != 32767 { - fmt.Printf("div_int16 32767%s1 = %d, wanted 32767\n", `/`, got) - failed = true - } - - if got := div_int16_32767_ssa(1); got != 0 { - fmt.Printf("div_int16 1%s32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_32767_int16_ssa(32766); got != 1 { - fmt.Printf("div_int16 32767%s32766 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int16_32767_ssa(32766); got != 0 { - fmt.Printf("div_int16 32766%s32767 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_32767_int16_ssa(32767); got != 1 { - fmt.Printf("div_int16 32767%s32767 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int16_32767_ssa(32767); got != 1 { - fmt.Printf("div_int16 32767%s32767 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := mul_Neg32768_int16_ssa(-32768); got != 0 { - fmt.Printf("mul_int16 -32768%s-32768 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32768_ssa(-32768); got != 0 { - fmt.Printf("mul_int16 -32768%s-32768 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg32768_int16_ssa(-32767); got != -32768 { - fmt.Printf("mul_int16 -32768%s-32767 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32768_ssa(-32767); got != -32768 { - fmt.Printf("mul_int16 -32767%s-32768 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_Neg32768_int16_ssa(-1); got != -32768 { - fmt.Printf("mul_int16 -32768%s-1 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32768_ssa(-1); got != -32768 { - fmt.Printf("mul_int16 -1%s-32768 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_Neg32768_int16_ssa(0); got != 0 { - fmt.Printf("mul_int16 -32768%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32768_ssa(0); got != 0 { - fmt.Printf("mul_int16 0%s-32768 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg32768_int16_ssa(1); got != -32768 { - fmt.Printf("mul_int16 -32768%s1 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32768_ssa(1); got != -32768 { - fmt.Printf("mul_int16 1%s-32768 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_Neg32768_int16_ssa(32766); got != 0 { - fmt.Printf("mul_int16 -32768%s32766 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32768_ssa(32766); got != 0 { - fmt.Printf("mul_int16 32766%s-32768 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg32768_int16_ssa(32767); got != -32768 { - fmt.Printf("mul_int16 -32768%s32767 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32768_ssa(32767); got != -32768 { - fmt.Printf("mul_int16 32767%s-32768 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_Neg32767_int16_ssa(-32768); got != -32768 { - fmt.Printf("mul_int16 -32767%s-32768 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32767_ssa(-32768); got != -32768 { - fmt.Printf("mul_int16 -32768%s-32767 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_Neg32767_int16_ssa(-32767); got != 1 { - fmt.Printf("mul_int16 -32767%s-32767 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32767_ssa(-32767); got != 1 { - fmt.Printf("mul_int16 -32767%s-32767 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_Neg32767_int16_ssa(-1); got != 32767 { - fmt.Printf("mul_int16 -32767%s-1 = %d, wanted 32767\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32767_ssa(-1); got != 32767 { - fmt.Printf("mul_int16 -1%s-32767 = %d, wanted 32767\n", `*`, got) - failed = true - } - - if got := mul_Neg32767_int16_ssa(0); got != 0 { - fmt.Printf("mul_int16 -32767%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32767_ssa(0); got != 0 { - fmt.Printf("mul_int16 0%s-32767 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg32767_int16_ssa(1); got != -32767 { - fmt.Printf("mul_int16 -32767%s1 = %d, wanted -32767\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32767_ssa(1); got != -32767 { - fmt.Printf("mul_int16 1%s-32767 = %d, wanted -32767\n", `*`, got) - failed = true - } - - if got := mul_Neg32767_int16_ssa(32766); got != 32766 { - fmt.Printf("mul_int16 -32767%s32766 = %d, wanted 32766\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32767_ssa(32766); got != 32766 { - fmt.Printf("mul_int16 32766%s-32767 = %d, wanted 32766\n", `*`, got) - failed = true - } - - if got := mul_Neg32767_int16_ssa(32767); got != -1 { - fmt.Printf("mul_int16 -32767%s32767 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg32767_ssa(32767); got != -1 { - fmt.Printf("mul_int16 32767%s-32767 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int16_ssa(-32768); got != -32768 { - fmt.Printf("mul_int16 -1%s-32768 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg1_ssa(-32768); got != -32768 { - fmt.Printf("mul_int16 -32768%s-1 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int16_ssa(-32767); got != 32767 { - fmt.Printf("mul_int16 -1%s-32767 = %d, wanted 32767\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg1_ssa(-32767); got != 32767 { - fmt.Printf("mul_int16 -32767%s-1 = %d, wanted 32767\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int16_ssa(-1); got != 1 { - fmt.Printf("mul_int16 -1%s-1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg1_ssa(-1); got != 1 { - fmt.Printf("mul_int16 -1%s-1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int16_ssa(0); got != 0 { - fmt.Printf("mul_int16 -1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg1_ssa(0); got != 0 { - fmt.Printf("mul_int16 0%s-1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int16_ssa(1); got != -1 { - fmt.Printf("mul_int16 -1%s1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg1_ssa(1); got != -1 { - fmt.Printf("mul_int16 1%s-1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int16_ssa(32766); got != -32766 { - fmt.Printf("mul_int16 -1%s32766 = %d, wanted -32766\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg1_ssa(32766); got != -32766 { - fmt.Printf("mul_int16 32766%s-1 = %d, wanted -32766\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int16_ssa(32767); got != -32767 { - fmt.Printf("mul_int16 -1%s32767 = %d, wanted -32767\n", `*`, got) - failed = true - } - - if got := mul_int16_Neg1_ssa(32767); got != -32767 { - fmt.Printf("mul_int16 32767%s-1 = %d, wanted -32767\n", `*`, got) - failed = true - } - - if got := mul_0_int16_ssa(-32768); got != 0 { - fmt.Printf("mul_int16 0%s-32768 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_0_ssa(-32768); got != 0 { - fmt.Printf("mul_int16 -32768%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int16_ssa(-32767); got != 0 { - fmt.Printf("mul_int16 0%s-32767 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_0_ssa(-32767); got != 0 { - fmt.Printf("mul_int16 -32767%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int16_ssa(-1); got != 0 { - fmt.Printf("mul_int16 0%s-1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_0_ssa(-1); got != 0 { - fmt.Printf("mul_int16 -1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int16_ssa(0); got != 0 { - fmt.Printf("mul_int16 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_0_ssa(0); got != 0 { - fmt.Printf("mul_int16 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int16_ssa(1); got != 0 { - fmt.Printf("mul_int16 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_0_ssa(1); got != 0 { - fmt.Printf("mul_int16 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int16_ssa(32766); got != 0 { - fmt.Printf("mul_int16 0%s32766 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_0_ssa(32766); got != 0 { - fmt.Printf("mul_int16 32766%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int16_ssa(32767); got != 0 { - fmt.Printf("mul_int16 0%s32767 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_0_ssa(32767); got != 0 { - fmt.Printf("mul_int16 32767%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_int16_ssa(-32768); got != -32768 { - fmt.Printf("mul_int16 1%s-32768 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_int16_1_ssa(-32768); got != -32768 { - fmt.Printf("mul_int16 -32768%s1 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_1_int16_ssa(-32767); got != -32767 { - fmt.Printf("mul_int16 1%s-32767 = %d, wanted -32767\n", `*`, got) - failed = true - } - - if got := mul_int16_1_ssa(-32767); got != -32767 { - fmt.Printf("mul_int16 -32767%s1 = %d, wanted -32767\n", `*`, got) - failed = true - } - - if got := mul_1_int16_ssa(-1); got != -1 { - fmt.Printf("mul_int16 1%s-1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int16_1_ssa(-1); got != -1 { - fmt.Printf("mul_int16 -1%s1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_1_int16_ssa(0); got != 0 { - fmt.Printf("mul_int16 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_1_ssa(0); got != 0 { - fmt.Printf("mul_int16 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_int16_ssa(1); got != 1 { - fmt.Printf("mul_int16 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int16_1_ssa(1); got != 1 { - fmt.Printf("mul_int16 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_1_int16_ssa(32766); got != 32766 { - fmt.Printf("mul_int16 1%s32766 = %d, wanted 32766\n", `*`, got) - failed = true - } - - if got := mul_int16_1_ssa(32766); got != 32766 { - fmt.Printf("mul_int16 32766%s1 = %d, wanted 32766\n", `*`, got) - failed = true - } - - if got := mul_1_int16_ssa(32767); got != 32767 { - fmt.Printf("mul_int16 1%s32767 = %d, wanted 32767\n", `*`, got) - failed = true - } - - if got := mul_int16_1_ssa(32767); got != 32767 { - fmt.Printf("mul_int16 32767%s1 = %d, wanted 32767\n", `*`, got) - failed = true - } - - if got := mul_32766_int16_ssa(-32768); got != 0 { - fmt.Printf("mul_int16 32766%s-32768 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_32766_ssa(-32768); got != 0 { - fmt.Printf("mul_int16 -32768%s32766 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_32766_int16_ssa(-32767); got != 32766 { - fmt.Printf("mul_int16 32766%s-32767 = %d, wanted 32766\n", `*`, got) - failed = true - } - - if got := mul_int16_32766_ssa(-32767); got != 32766 { - fmt.Printf("mul_int16 -32767%s32766 = %d, wanted 32766\n", `*`, got) - failed = true - } - - if got := mul_32766_int16_ssa(-1); got != -32766 { - fmt.Printf("mul_int16 32766%s-1 = %d, wanted -32766\n", `*`, got) - failed = true - } - - if got := mul_int16_32766_ssa(-1); got != -32766 { - fmt.Printf("mul_int16 -1%s32766 = %d, wanted -32766\n", `*`, got) - failed = true - } - - if got := mul_32766_int16_ssa(0); got != 0 { - fmt.Printf("mul_int16 32766%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_32766_ssa(0); got != 0 { - fmt.Printf("mul_int16 0%s32766 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_32766_int16_ssa(1); got != 32766 { - fmt.Printf("mul_int16 32766%s1 = %d, wanted 32766\n", `*`, got) - failed = true - } - - if got := mul_int16_32766_ssa(1); got != 32766 { - fmt.Printf("mul_int16 1%s32766 = %d, wanted 32766\n", `*`, got) - failed = true - } - - if got := mul_32766_int16_ssa(32766); got != 4 { - fmt.Printf("mul_int16 32766%s32766 = %d, wanted 4\n", `*`, got) - failed = true - } - - if got := mul_int16_32766_ssa(32766); got != 4 { - fmt.Printf("mul_int16 32766%s32766 = %d, wanted 4\n", `*`, got) - failed = true - } - - if got := mul_32766_int16_ssa(32767); got != -32766 { - fmt.Printf("mul_int16 32766%s32767 = %d, wanted -32766\n", `*`, got) - failed = true - } - - if got := mul_int16_32766_ssa(32767); got != -32766 { - fmt.Printf("mul_int16 32767%s32766 = %d, wanted -32766\n", `*`, got) - failed = true - } - - if got := mul_32767_int16_ssa(-32768); got != -32768 { - fmt.Printf("mul_int16 32767%s-32768 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_int16_32767_ssa(-32768); got != -32768 { - fmt.Printf("mul_int16 -32768%s32767 = %d, wanted -32768\n", `*`, got) - failed = true - } - - if got := mul_32767_int16_ssa(-32767); got != -1 { - fmt.Printf("mul_int16 32767%s-32767 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int16_32767_ssa(-32767); got != -1 { - fmt.Printf("mul_int16 -32767%s32767 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_32767_int16_ssa(-1); got != -32767 { - fmt.Printf("mul_int16 32767%s-1 = %d, wanted -32767\n", `*`, got) - failed = true - } - - if got := mul_int16_32767_ssa(-1); got != -32767 { - fmt.Printf("mul_int16 -1%s32767 = %d, wanted -32767\n", `*`, got) - failed = true - } - - if got := mul_32767_int16_ssa(0); got != 0 { - fmt.Printf("mul_int16 32767%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int16_32767_ssa(0); got != 0 { - fmt.Printf("mul_int16 0%s32767 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_32767_int16_ssa(1); got != 32767 { - fmt.Printf("mul_int16 32767%s1 = %d, wanted 32767\n", `*`, got) - failed = true - } - - if got := mul_int16_32767_ssa(1); got != 32767 { - fmt.Printf("mul_int16 1%s32767 = %d, wanted 32767\n", `*`, got) - failed = true - } - - if got := mul_32767_int16_ssa(32766); got != -32766 { - fmt.Printf("mul_int16 32767%s32766 = %d, wanted -32766\n", `*`, got) - failed = true - } - - if got := mul_int16_32767_ssa(32766); got != -32766 { - fmt.Printf("mul_int16 32766%s32767 = %d, wanted -32766\n", `*`, got) - failed = true - } - - if got := mul_32767_int16_ssa(32767); got != 1 { - fmt.Printf("mul_int16 32767%s32767 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int16_32767_ssa(32767); got != 1 { - fmt.Printf("mul_int16 32767%s32767 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mod_Neg32768_int16_ssa(-32768); got != 0 { - fmt.Printf("mod_int16 -32768%s-32768 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32768_ssa(-32768); got != 0 { - fmt.Printf("mod_int16 -32768%s-32768 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg32768_int16_ssa(-32767); got != -1 { - fmt.Printf("mod_int16 -32768%s-32767 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32768_ssa(-32767); got != -32767 { - fmt.Printf("mod_int16 -32767%s-32768 = %d, wanted -32767\n", `%`, got) - failed = true - } - - if got := mod_Neg32768_int16_ssa(-1); got != 0 { - fmt.Printf("mod_int16 -32768%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32768_ssa(-1); got != -1 { - fmt.Printf("mod_int16 -1%s-32768 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32768_ssa(0); got != 0 { - fmt.Printf("mod_int16 0%s-32768 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg32768_int16_ssa(1); got != 0 { - fmt.Printf("mod_int16 -32768%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32768_ssa(1); got != 1 { - fmt.Printf("mod_int16 1%s-32768 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_Neg32768_int16_ssa(32766); got != -2 { - fmt.Printf("mod_int16 -32768%s32766 = %d, wanted -2\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32768_ssa(32766); got != 32766 { - fmt.Printf("mod_int16 32766%s-32768 = %d, wanted 32766\n", `%`, got) - failed = true - } - - if got := mod_Neg32768_int16_ssa(32767); got != -1 { - fmt.Printf("mod_int16 -32768%s32767 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32768_ssa(32767); got != 32767 { - fmt.Printf("mod_int16 32767%s-32768 = %d, wanted 32767\n", `%`, got) - failed = true - } - - if got := mod_Neg32767_int16_ssa(-32768); got != -32767 { - fmt.Printf("mod_int16 -32767%s-32768 = %d, wanted -32767\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32767_ssa(-32768); got != -1 { - fmt.Printf("mod_int16 -32768%s-32767 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_Neg32767_int16_ssa(-32767); got != 0 { - fmt.Printf("mod_int16 -32767%s-32767 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32767_ssa(-32767); got != 0 { - fmt.Printf("mod_int16 -32767%s-32767 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg32767_int16_ssa(-1); got != 0 { - fmt.Printf("mod_int16 -32767%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32767_ssa(-1); got != -1 { - fmt.Printf("mod_int16 -1%s-32767 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32767_ssa(0); got != 0 { - fmt.Printf("mod_int16 0%s-32767 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg32767_int16_ssa(1); got != 0 { - fmt.Printf("mod_int16 -32767%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32767_ssa(1); got != 1 { - fmt.Printf("mod_int16 1%s-32767 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_Neg32767_int16_ssa(32766); got != -1 { - fmt.Printf("mod_int16 -32767%s32766 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32767_ssa(32766); got != 32766 { - fmt.Printf("mod_int16 32766%s-32767 = %d, wanted 32766\n", `%`, got) - failed = true - } - - if got := mod_Neg32767_int16_ssa(32767); got != 0 { - fmt.Printf("mod_int16 -32767%s32767 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg32767_ssa(32767); got != 0 { - fmt.Printf("mod_int16 32767%s-32767 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int16_ssa(-32768); got != -1 { - fmt.Printf("mod_int16 -1%s-32768 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg1_ssa(-32768); got != 0 { - fmt.Printf("mod_int16 -32768%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int16_ssa(-32767); got != -1 { - fmt.Printf("mod_int16 -1%s-32767 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg1_ssa(-32767); got != 0 { - fmt.Printf("mod_int16 -32767%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int16_ssa(-1); got != 0 { - fmt.Printf("mod_int16 -1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg1_ssa(-1); got != 0 { - fmt.Printf("mod_int16 -1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg1_ssa(0); got != 0 { - fmt.Printf("mod_int16 0%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int16_ssa(1); got != 0 { - fmt.Printf("mod_int16 -1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg1_ssa(1); got != 0 { - fmt.Printf("mod_int16 1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int16_ssa(32766); got != -1 { - fmt.Printf("mod_int16 -1%s32766 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg1_ssa(32766); got != 0 { - fmt.Printf("mod_int16 32766%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int16_ssa(32767); got != -1 { - fmt.Printf("mod_int16 -1%s32767 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int16_Neg1_ssa(32767); got != 0 { - fmt.Printf("mod_int16 32767%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int16_ssa(-32768); got != 0 { - fmt.Printf("mod_int16 0%s-32768 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int16_ssa(-32767); got != 0 { - fmt.Printf("mod_int16 0%s-32767 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int16_ssa(-1); got != 0 { - fmt.Printf("mod_int16 0%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int16_ssa(1); got != 0 { - fmt.Printf("mod_int16 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int16_ssa(32766); got != 0 { - fmt.Printf("mod_int16 0%s32766 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int16_ssa(32767); got != 0 { - fmt.Printf("mod_int16 0%s32767 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int16_ssa(-32768); got != 1 { - fmt.Printf("mod_int16 1%s-32768 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int16_1_ssa(-32768); got != 0 { - fmt.Printf("mod_int16 -32768%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int16_ssa(-32767); got != 1 { - fmt.Printf("mod_int16 1%s-32767 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int16_1_ssa(-32767); got != 0 { - fmt.Printf("mod_int16 -32767%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int16_ssa(-1); got != 0 { - fmt.Printf("mod_int16 1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_1_ssa(-1); got != 0 { - fmt.Printf("mod_int16 -1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_1_ssa(0); got != 0 { - fmt.Printf("mod_int16 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int16_ssa(1); got != 0 { - fmt.Printf("mod_int16 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_1_ssa(1); got != 0 { - fmt.Printf("mod_int16 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int16_ssa(32766); got != 1 { - fmt.Printf("mod_int16 1%s32766 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int16_1_ssa(32766); got != 0 { - fmt.Printf("mod_int16 32766%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int16_ssa(32767); got != 1 { - fmt.Printf("mod_int16 1%s32767 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int16_1_ssa(32767); got != 0 { - fmt.Printf("mod_int16 32767%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_32766_int16_ssa(-32768); got != 32766 { - fmt.Printf("mod_int16 32766%s-32768 = %d, wanted 32766\n", `%`, got) - failed = true - } - - if got := mod_int16_32766_ssa(-32768); got != -2 { - fmt.Printf("mod_int16 -32768%s32766 = %d, wanted -2\n", `%`, got) - failed = true - } - - if got := mod_32766_int16_ssa(-32767); got != 32766 { - fmt.Printf("mod_int16 32766%s-32767 = %d, wanted 32766\n", `%`, got) - failed = true - } - - if got := mod_int16_32766_ssa(-32767); got != -1 { - fmt.Printf("mod_int16 -32767%s32766 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_32766_int16_ssa(-1); got != 0 { - fmt.Printf("mod_int16 32766%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_32766_ssa(-1); got != -1 { - fmt.Printf("mod_int16 -1%s32766 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int16_32766_ssa(0); got != 0 { - fmt.Printf("mod_int16 0%s32766 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_32766_int16_ssa(1); got != 0 { - fmt.Printf("mod_int16 32766%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_32766_ssa(1); got != 1 { - fmt.Printf("mod_int16 1%s32766 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_32766_int16_ssa(32766); got != 0 { - fmt.Printf("mod_int16 32766%s32766 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_32766_ssa(32766); got != 0 { - fmt.Printf("mod_int16 32766%s32766 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_32766_int16_ssa(32767); got != 32766 { - fmt.Printf("mod_int16 32766%s32767 = %d, wanted 32766\n", `%`, got) - failed = true - } - - if got := mod_int16_32766_ssa(32767); got != 1 { - fmt.Printf("mod_int16 32767%s32766 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_32767_int16_ssa(-32768); got != 32767 { - fmt.Printf("mod_int16 32767%s-32768 = %d, wanted 32767\n", `%`, got) - failed = true - } - - if got := mod_int16_32767_ssa(-32768); got != -1 { - fmt.Printf("mod_int16 -32768%s32767 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_32767_int16_ssa(-32767); got != 0 { - fmt.Printf("mod_int16 32767%s-32767 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_32767_ssa(-32767); got != 0 { - fmt.Printf("mod_int16 -32767%s32767 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_32767_int16_ssa(-1); got != 0 { - fmt.Printf("mod_int16 32767%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_32767_ssa(-1); got != -1 { - fmt.Printf("mod_int16 -1%s32767 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int16_32767_ssa(0); got != 0 { - fmt.Printf("mod_int16 0%s32767 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_32767_int16_ssa(1); got != 0 { - fmt.Printf("mod_int16 32767%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_32767_ssa(1); got != 1 { - fmt.Printf("mod_int16 1%s32767 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_32767_int16_ssa(32766); got != 1 { - fmt.Printf("mod_int16 32767%s32766 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int16_32767_ssa(32766); got != 32766 { - fmt.Printf("mod_int16 32766%s32767 = %d, wanted 32766\n", `%`, got) - failed = true - } - - if got := mod_32767_int16_ssa(32767); got != 0 { - fmt.Printf("mod_int16 32767%s32767 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int16_32767_ssa(32767); got != 0 { - fmt.Printf("mod_int16 32767%s32767 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := and_Neg32768_int16_ssa(-32768); got != -32768 { - fmt.Printf("and_int16 -32768%s-32768 = %d, wanted -32768\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32768_ssa(-32768); got != -32768 { - fmt.Printf("and_int16 -32768%s-32768 = %d, wanted -32768\n", `&`, got) - failed = true - } - - if got := and_Neg32768_int16_ssa(-32767); got != -32768 { - fmt.Printf("and_int16 -32768%s-32767 = %d, wanted -32768\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32768_ssa(-32767); got != -32768 { - fmt.Printf("and_int16 -32767%s-32768 = %d, wanted -32768\n", `&`, got) - failed = true - } - - if got := and_Neg32768_int16_ssa(-1); got != -32768 { - fmt.Printf("and_int16 -32768%s-1 = %d, wanted -32768\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32768_ssa(-1); got != -32768 { - fmt.Printf("and_int16 -1%s-32768 = %d, wanted -32768\n", `&`, got) - failed = true - } - - if got := and_Neg32768_int16_ssa(0); got != 0 { - fmt.Printf("and_int16 -32768%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32768_ssa(0); got != 0 { - fmt.Printf("and_int16 0%s-32768 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg32768_int16_ssa(1); got != 0 { - fmt.Printf("and_int16 -32768%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32768_ssa(1); got != 0 { - fmt.Printf("and_int16 1%s-32768 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg32768_int16_ssa(32766); got != 0 { - fmt.Printf("and_int16 -32768%s32766 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32768_ssa(32766); got != 0 { - fmt.Printf("and_int16 32766%s-32768 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg32768_int16_ssa(32767); got != 0 { - fmt.Printf("and_int16 -32768%s32767 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32768_ssa(32767); got != 0 { - fmt.Printf("and_int16 32767%s-32768 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg32767_int16_ssa(-32768); got != -32768 { - fmt.Printf("and_int16 -32767%s-32768 = %d, wanted -32768\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32767_ssa(-32768); got != -32768 { - fmt.Printf("and_int16 -32768%s-32767 = %d, wanted -32768\n", `&`, got) - failed = true - } - - if got := and_Neg32767_int16_ssa(-32767); got != -32767 { - fmt.Printf("and_int16 -32767%s-32767 = %d, wanted -32767\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32767_ssa(-32767); got != -32767 { - fmt.Printf("and_int16 -32767%s-32767 = %d, wanted -32767\n", `&`, got) - failed = true - } - - if got := and_Neg32767_int16_ssa(-1); got != -32767 { - fmt.Printf("and_int16 -32767%s-1 = %d, wanted -32767\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32767_ssa(-1); got != -32767 { - fmt.Printf("and_int16 -1%s-32767 = %d, wanted -32767\n", `&`, got) - failed = true - } - - if got := and_Neg32767_int16_ssa(0); got != 0 { - fmt.Printf("and_int16 -32767%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32767_ssa(0); got != 0 { - fmt.Printf("and_int16 0%s-32767 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg32767_int16_ssa(1); got != 1 { - fmt.Printf("and_int16 -32767%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32767_ssa(1); got != 1 { - fmt.Printf("and_int16 1%s-32767 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_Neg32767_int16_ssa(32766); got != 0 { - fmt.Printf("and_int16 -32767%s32766 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32767_ssa(32766); got != 0 { - fmt.Printf("and_int16 32766%s-32767 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg32767_int16_ssa(32767); got != 1 { - fmt.Printf("and_int16 -32767%s32767 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int16_Neg32767_ssa(32767); got != 1 { - fmt.Printf("and_int16 32767%s-32767 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_Neg1_int16_ssa(-32768); got != -32768 { - fmt.Printf("and_int16 -1%s-32768 = %d, wanted -32768\n", `&`, got) - failed = true - } - - if got := and_int16_Neg1_ssa(-32768); got != -32768 { - fmt.Printf("and_int16 -32768%s-1 = %d, wanted -32768\n", `&`, got) - failed = true - } - - if got := and_Neg1_int16_ssa(-32767); got != -32767 { - fmt.Printf("and_int16 -1%s-32767 = %d, wanted -32767\n", `&`, got) - failed = true - } - - if got := and_int16_Neg1_ssa(-32767); got != -32767 { - fmt.Printf("and_int16 -32767%s-1 = %d, wanted -32767\n", `&`, got) - failed = true - } - - if got := and_Neg1_int16_ssa(-1); got != -1 { - fmt.Printf("and_int16 -1%s-1 = %d, wanted -1\n", `&`, got) - failed = true - } - - if got := and_int16_Neg1_ssa(-1); got != -1 { - fmt.Printf("and_int16 -1%s-1 = %d, wanted -1\n", `&`, got) - failed = true - } - - if got := and_Neg1_int16_ssa(0); got != 0 { - fmt.Printf("and_int16 -1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_Neg1_ssa(0); got != 0 { - fmt.Printf("and_int16 0%s-1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg1_int16_ssa(1); got != 1 { - fmt.Printf("and_int16 -1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int16_Neg1_ssa(1); got != 1 { - fmt.Printf("and_int16 1%s-1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_Neg1_int16_ssa(32766); got != 32766 { - fmt.Printf("and_int16 -1%s32766 = %d, wanted 32766\n", `&`, got) - failed = true - } - - if got := and_int16_Neg1_ssa(32766); got != 32766 { - fmt.Printf("and_int16 32766%s-1 = %d, wanted 32766\n", `&`, got) - failed = true - } - - if got := and_Neg1_int16_ssa(32767); got != 32767 { - fmt.Printf("and_int16 -1%s32767 = %d, wanted 32767\n", `&`, got) - failed = true - } - - if got := and_int16_Neg1_ssa(32767); got != 32767 { - fmt.Printf("and_int16 32767%s-1 = %d, wanted 32767\n", `&`, got) - failed = true - } - - if got := and_0_int16_ssa(-32768); got != 0 { - fmt.Printf("and_int16 0%s-32768 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_0_ssa(-32768); got != 0 { - fmt.Printf("and_int16 -32768%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int16_ssa(-32767); got != 0 { - fmt.Printf("and_int16 0%s-32767 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_0_ssa(-32767); got != 0 { - fmt.Printf("and_int16 -32767%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int16_ssa(-1); got != 0 { - fmt.Printf("and_int16 0%s-1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_0_ssa(-1); got != 0 { - fmt.Printf("and_int16 -1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int16_ssa(0); got != 0 { - fmt.Printf("and_int16 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_0_ssa(0); got != 0 { - fmt.Printf("and_int16 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int16_ssa(1); got != 0 { - fmt.Printf("and_int16 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_0_ssa(1); got != 0 { - fmt.Printf("and_int16 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int16_ssa(32766); got != 0 { - fmt.Printf("and_int16 0%s32766 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_0_ssa(32766); got != 0 { - fmt.Printf("and_int16 32766%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int16_ssa(32767); got != 0 { - fmt.Printf("and_int16 0%s32767 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_0_ssa(32767); got != 0 { - fmt.Printf("and_int16 32767%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int16_ssa(-32768); got != 0 { - fmt.Printf("and_int16 1%s-32768 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_1_ssa(-32768); got != 0 { - fmt.Printf("and_int16 -32768%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int16_ssa(-32767); got != 1 { - fmt.Printf("and_int16 1%s-32767 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int16_1_ssa(-32767); got != 1 { - fmt.Printf("and_int16 -32767%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_int16_ssa(-1); got != 1 { - fmt.Printf("and_int16 1%s-1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int16_1_ssa(-1); got != 1 { - fmt.Printf("and_int16 -1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_int16_ssa(0); got != 0 { - fmt.Printf("and_int16 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_1_ssa(0); got != 0 { - fmt.Printf("and_int16 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int16_ssa(1); got != 1 { - fmt.Printf("and_int16 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int16_1_ssa(1); got != 1 { - fmt.Printf("and_int16 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_int16_ssa(32766); got != 0 { - fmt.Printf("and_int16 1%s32766 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_1_ssa(32766); got != 0 { - fmt.Printf("and_int16 32766%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int16_ssa(32767); got != 1 { - fmt.Printf("and_int16 1%s32767 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int16_1_ssa(32767); got != 1 { - fmt.Printf("and_int16 32767%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_32766_int16_ssa(-32768); got != 0 { - fmt.Printf("and_int16 32766%s-32768 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_32766_ssa(-32768); got != 0 { - fmt.Printf("and_int16 -32768%s32766 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_32766_int16_ssa(-32767); got != 0 { - fmt.Printf("and_int16 32766%s-32767 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_32766_ssa(-32767); got != 0 { - fmt.Printf("and_int16 -32767%s32766 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_32766_int16_ssa(-1); got != 32766 { - fmt.Printf("and_int16 32766%s-1 = %d, wanted 32766\n", `&`, got) - failed = true - } - - if got := and_int16_32766_ssa(-1); got != 32766 { - fmt.Printf("and_int16 -1%s32766 = %d, wanted 32766\n", `&`, got) - failed = true - } - - if got := and_32766_int16_ssa(0); got != 0 { - fmt.Printf("and_int16 32766%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_32766_ssa(0); got != 0 { - fmt.Printf("and_int16 0%s32766 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_32766_int16_ssa(1); got != 0 { - fmt.Printf("and_int16 32766%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_32766_ssa(1); got != 0 { - fmt.Printf("and_int16 1%s32766 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_32766_int16_ssa(32766); got != 32766 { - fmt.Printf("and_int16 32766%s32766 = %d, wanted 32766\n", `&`, got) - failed = true - } - - if got := and_int16_32766_ssa(32766); got != 32766 { - fmt.Printf("and_int16 32766%s32766 = %d, wanted 32766\n", `&`, got) - failed = true - } - - if got := and_32766_int16_ssa(32767); got != 32766 { - fmt.Printf("and_int16 32766%s32767 = %d, wanted 32766\n", `&`, got) - failed = true - } - - if got := and_int16_32766_ssa(32767); got != 32766 { - fmt.Printf("and_int16 32767%s32766 = %d, wanted 32766\n", `&`, got) - failed = true - } - - if got := and_32767_int16_ssa(-32768); got != 0 { - fmt.Printf("and_int16 32767%s-32768 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_32767_ssa(-32768); got != 0 { - fmt.Printf("and_int16 -32768%s32767 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_32767_int16_ssa(-32767); got != 1 { - fmt.Printf("and_int16 32767%s-32767 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int16_32767_ssa(-32767); got != 1 { - fmt.Printf("and_int16 -32767%s32767 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_32767_int16_ssa(-1); got != 32767 { - fmt.Printf("and_int16 32767%s-1 = %d, wanted 32767\n", `&`, got) - failed = true - } - - if got := and_int16_32767_ssa(-1); got != 32767 { - fmt.Printf("and_int16 -1%s32767 = %d, wanted 32767\n", `&`, got) - failed = true - } - - if got := and_32767_int16_ssa(0); got != 0 { - fmt.Printf("and_int16 32767%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int16_32767_ssa(0); got != 0 { - fmt.Printf("and_int16 0%s32767 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_32767_int16_ssa(1); got != 1 { - fmt.Printf("and_int16 32767%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int16_32767_ssa(1); got != 1 { - fmt.Printf("and_int16 1%s32767 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_32767_int16_ssa(32766); got != 32766 { - fmt.Printf("and_int16 32767%s32766 = %d, wanted 32766\n", `&`, got) - failed = true - } - - if got := and_int16_32767_ssa(32766); got != 32766 { - fmt.Printf("and_int16 32766%s32767 = %d, wanted 32766\n", `&`, got) - failed = true - } - - if got := and_32767_int16_ssa(32767); got != 32767 { - fmt.Printf("and_int16 32767%s32767 = %d, wanted 32767\n", `&`, got) - failed = true - } - - if got := and_int16_32767_ssa(32767); got != 32767 { - fmt.Printf("and_int16 32767%s32767 = %d, wanted 32767\n", `&`, got) - failed = true - } - - if got := or_Neg32768_int16_ssa(-32768); got != -32768 { - fmt.Printf("or_int16 -32768%s-32768 = %d, wanted -32768\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32768_ssa(-32768); got != -32768 { - fmt.Printf("or_int16 -32768%s-32768 = %d, wanted -32768\n", `|`, got) - failed = true - } - - if got := or_Neg32768_int16_ssa(-32767); got != -32767 { - fmt.Printf("or_int16 -32768%s-32767 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32768_ssa(-32767); got != -32767 { - fmt.Printf("or_int16 -32767%s-32768 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_Neg32768_int16_ssa(-1); got != -1 { - fmt.Printf("or_int16 -32768%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32768_ssa(-1); got != -1 { - fmt.Printf("or_int16 -1%s-32768 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg32768_int16_ssa(0); got != -32768 { - fmt.Printf("or_int16 -32768%s0 = %d, wanted -32768\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32768_ssa(0); got != -32768 { - fmt.Printf("or_int16 0%s-32768 = %d, wanted -32768\n", `|`, got) - failed = true - } - - if got := or_Neg32768_int16_ssa(1); got != -32767 { - fmt.Printf("or_int16 -32768%s1 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32768_ssa(1); got != -32767 { - fmt.Printf("or_int16 1%s-32768 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_Neg32768_int16_ssa(32766); got != -2 { - fmt.Printf("or_int16 -32768%s32766 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32768_ssa(32766); got != -2 { - fmt.Printf("or_int16 32766%s-32768 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_Neg32768_int16_ssa(32767); got != -1 { - fmt.Printf("or_int16 -32768%s32767 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32768_ssa(32767); got != -1 { - fmt.Printf("or_int16 32767%s-32768 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg32767_int16_ssa(-32768); got != -32767 { - fmt.Printf("or_int16 -32767%s-32768 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32767_ssa(-32768); got != -32767 { - fmt.Printf("or_int16 -32768%s-32767 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_Neg32767_int16_ssa(-32767); got != -32767 { - fmt.Printf("or_int16 -32767%s-32767 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32767_ssa(-32767); got != -32767 { - fmt.Printf("or_int16 -32767%s-32767 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_Neg32767_int16_ssa(-1); got != -1 { - fmt.Printf("or_int16 -32767%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32767_ssa(-1); got != -1 { - fmt.Printf("or_int16 -1%s-32767 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg32767_int16_ssa(0); got != -32767 { - fmt.Printf("or_int16 -32767%s0 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32767_ssa(0); got != -32767 { - fmt.Printf("or_int16 0%s-32767 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_Neg32767_int16_ssa(1); got != -32767 { - fmt.Printf("or_int16 -32767%s1 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32767_ssa(1); got != -32767 { - fmt.Printf("or_int16 1%s-32767 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_Neg32767_int16_ssa(32766); got != -1 { - fmt.Printf("or_int16 -32767%s32766 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32767_ssa(32766); got != -1 { - fmt.Printf("or_int16 32766%s-32767 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg32767_int16_ssa(32767); got != -1 { - fmt.Printf("or_int16 -32767%s32767 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_Neg32767_ssa(32767); got != -1 { - fmt.Printf("or_int16 32767%s-32767 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int16_ssa(-32768); got != -1 { - fmt.Printf("or_int16 -1%s-32768 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_Neg1_ssa(-32768); got != -1 { - fmt.Printf("or_int16 -32768%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int16_ssa(-32767); got != -1 { - fmt.Printf("or_int16 -1%s-32767 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_Neg1_ssa(-32767); got != -1 { - fmt.Printf("or_int16 -32767%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int16_ssa(-1); got != -1 { - fmt.Printf("or_int16 -1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_Neg1_ssa(-1); got != -1 { - fmt.Printf("or_int16 -1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int16_ssa(0); got != -1 { - fmt.Printf("or_int16 -1%s0 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_Neg1_ssa(0); got != -1 { - fmt.Printf("or_int16 0%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int16_ssa(1); got != -1 { - fmt.Printf("or_int16 -1%s1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_Neg1_ssa(1); got != -1 { - fmt.Printf("or_int16 1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int16_ssa(32766); got != -1 { - fmt.Printf("or_int16 -1%s32766 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_Neg1_ssa(32766); got != -1 { - fmt.Printf("or_int16 32766%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int16_ssa(32767); got != -1 { - fmt.Printf("or_int16 -1%s32767 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_Neg1_ssa(32767); got != -1 { - fmt.Printf("or_int16 32767%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_0_int16_ssa(-32768); got != -32768 { - fmt.Printf("or_int16 0%s-32768 = %d, wanted -32768\n", `|`, got) - failed = true - } - - if got := or_int16_0_ssa(-32768); got != -32768 { - fmt.Printf("or_int16 -32768%s0 = %d, wanted -32768\n", `|`, got) - failed = true - } - - if got := or_0_int16_ssa(-32767); got != -32767 { - fmt.Printf("or_int16 0%s-32767 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_int16_0_ssa(-32767); got != -32767 { - fmt.Printf("or_int16 -32767%s0 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_0_int16_ssa(-1); got != -1 { - fmt.Printf("or_int16 0%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_0_ssa(-1); got != -1 { - fmt.Printf("or_int16 -1%s0 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_0_int16_ssa(0); got != 0 { - fmt.Printf("or_int16 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_int16_0_ssa(0); got != 0 { - fmt.Printf("or_int16 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_0_int16_ssa(1); got != 1 { - fmt.Printf("or_int16 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_int16_0_ssa(1); got != 1 { - fmt.Printf("or_int16 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_0_int16_ssa(32766); got != 32766 { - fmt.Printf("or_int16 0%s32766 = %d, wanted 32766\n", `|`, got) - failed = true - } - - if got := or_int16_0_ssa(32766); got != 32766 { - fmt.Printf("or_int16 32766%s0 = %d, wanted 32766\n", `|`, got) - failed = true - } - - if got := or_0_int16_ssa(32767); got != 32767 { - fmt.Printf("or_int16 0%s32767 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_int16_0_ssa(32767); got != 32767 { - fmt.Printf("or_int16 32767%s0 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_1_int16_ssa(-32768); got != -32767 { - fmt.Printf("or_int16 1%s-32768 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_int16_1_ssa(-32768); got != -32767 { - fmt.Printf("or_int16 -32768%s1 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_1_int16_ssa(-32767); got != -32767 { - fmt.Printf("or_int16 1%s-32767 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_int16_1_ssa(-32767); got != -32767 { - fmt.Printf("or_int16 -32767%s1 = %d, wanted -32767\n", `|`, got) - failed = true - } - - if got := or_1_int16_ssa(-1); got != -1 { - fmt.Printf("or_int16 1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_1_ssa(-1); got != -1 { - fmt.Printf("or_int16 -1%s1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_1_int16_ssa(0); got != 1 { - fmt.Printf("or_int16 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_int16_1_ssa(0); got != 1 { - fmt.Printf("or_int16 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_int16_ssa(1); got != 1 { - fmt.Printf("or_int16 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_int16_1_ssa(1); got != 1 { - fmt.Printf("or_int16 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_int16_ssa(32766); got != 32767 { - fmt.Printf("or_int16 1%s32766 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_int16_1_ssa(32766); got != 32767 { - fmt.Printf("or_int16 32766%s1 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_1_int16_ssa(32767); got != 32767 { - fmt.Printf("or_int16 1%s32767 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_int16_1_ssa(32767); got != 32767 { - fmt.Printf("or_int16 32767%s1 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_32766_int16_ssa(-32768); got != -2 { - fmt.Printf("or_int16 32766%s-32768 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_int16_32766_ssa(-32768); got != -2 { - fmt.Printf("or_int16 -32768%s32766 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_32766_int16_ssa(-32767); got != -1 { - fmt.Printf("or_int16 32766%s-32767 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_32766_ssa(-32767); got != -1 { - fmt.Printf("or_int16 -32767%s32766 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_32766_int16_ssa(-1); got != -1 { - fmt.Printf("or_int16 32766%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_32766_ssa(-1); got != -1 { - fmt.Printf("or_int16 -1%s32766 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_32766_int16_ssa(0); got != 32766 { - fmt.Printf("or_int16 32766%s0 = %d, wanted 32766\n", `|`, got) - failed = true - } - - if got := or_int16_32766_ssa(0); got != 32766 { - fmt.Printf("or_int16 0%s32766 = %d, wanted 32766\n", `|`, got) - failed = true - } - - if got := or_32766_int16_ssa(1); got != 32767 { - fmt.Printf("or_int16 32766%s1 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_int16_32766_ssa(1); got != 32767 { - fmt.Printf("or_int16 1%s32766 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_32766_int16_ssa(32766); got != 32766 { - fmt.Printf("or_int16 32766%s32766 = %d, wanted 32766\n", `|`, got) - failed = true - } - - if got := or_int16_32766_ssa(32766); got != 32766 { - fmt.Printf("or_int16 32766%s32766 = %d, wanted 32766\n", `|`, got) - failed = true - } - - if got := or_32766_int16_ssa(32767); got != 32767 { - fmt.Printf("or_int16 32766%s32767 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_int16_32766_ssa(32767); got != 32767 { - fmt.Printf("or_int16 32767%s32766 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_32767_int16_ssa(-32768); got != -1 { - fmt.Printf("or_int16 32767%s-32768 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_32767_ssa(-32768); got != -1 { - fmt.Printf("or_int16 -32768%s32767 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_32767_int16_ssa(-32767); got != -1 { - fmt.Printf("or_int16 32767%s-32767 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_32767_ssa(-32767); got != -1 { - fmt.Printf("or_int16 -32767%s32767 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_32767_int16_ssa(-1); got != -1 { - fmt.Printf("or_int16 32767%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int16_32767_ssa(-1); got != -1 { - fmt.Printf("or_int16 -1%s32767 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_32767_int16_ssa(0); got != 32767 { - fmt.Printf("or_int16 32767%s0 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_int16_32767_ssa(0); got != 32767 { - fmt.Printf("or_int16 0%s32767 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_32767_int16_ssa(1); got != 32767 { - fmt.Printf("or_int16 32767%s1 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_int16_32767_ssa(1); got != 32767 { - fmt.Printf("or_int16 1%s32767 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_32767_int16_ssa(32766); got != 32767 { - fmt.Printf("or_int16 32767%s32766 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_int16_32767_ssa(32766); got != 32767 { - fmt.Printf("or_int16 32766%s32767 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_32767_int16_ssa(32767); got != 32767 { - fmt.Printf("or_int16 32767%s32767 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := or_int16_32767_ssa(32767); got != 32767 { - fmt.Printf("or_int16 32767%s32767 = %d, wanted 32767\n", `|`, got) - failed = true - } - - if got := xor_Neg32768_int16_ssa(-32768); got != 0 { - fmt.Printf("xor_int16 -32768%s-32768 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32768_ssa(-32768); got != 0 { - fmt.Printf("xor_int16 -32768%s-32768 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_Neg32768_int16_ssa(-32767); got != 1 { - fmt.Printf("xor_int16 -32768%s-32767 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32768_ssa(-32767); got != 1 { - fmt.Printf("xor_int16 -32767%s-32768 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_Neg32768_int16_ssa(-1); got != 32767 { - fmt.Printf("xor_int16 -32768%s-1 = %d, wanted 32767\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32768_ssa(-1); got != 32767 { - fmt.Printf("xor_int16 -1%s-32768 = %d, wanted 32767\n", `^`, got) - failed = true - } - - if got := xor_Neg32768_int16_ssa(0); got != -32768 { - fmt.Printf("xor_int16 -32768%s0 = %d, wanted -32768\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32768_ssa(0); got != -32768 { - fmt.Printf("xor_int16 0%s-32768 = %d, wanted -32768\n", `^`, got) - failed = true - } - - if got := xor_Neg32768_int16_ssa(1); got != -32767 { - fmt.Printf("xor_int16 -32768%s1 = %d, wanted -32767\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32768_ssa(1); got != -32767 { - fmt.Printf("xor_int16 1%s-32768 = %d, wanted -32767\n", `^`, got) - failed = true - } - - if got := xor_Neg32768_int16_ssa(32766); got != -2 { - fmt.Printf("xor_int16 -32768%s32766 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32768_ssa(32766); got != -2 { - fmt.Printf("xor_int16 32766%s-32768 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_Neg32768_int16_ssa(32767); got != -1 { - fmt.Printf("xor_int16 -32768%s32767 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32768_ssa(32767); got != -1 { - fmt.Printf("xor_int16 32767%s-32768 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_Neg32767_int16_ssa(-32768); got != 1 { - fmt.Printf("xor_int16 -32767%s-32768 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32767_ssa(-32768); got != 1 { - fmt.Printf("xor_int16 -32768%s-32767 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_Neg32767_int16_ssa(-32767); got != 0 { - fmt.Printf("xor_int16 -32767%s-32767 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32767_ssa(-32767); got != 0 { - fmt.Printf("xor_int16 -32767%s-32767 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_Neg32767_int16_ssa(-1); got != 32766 { - fmt.Printf("xor_int16 -32767%s-1 = %d, wanted 32766\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32767_ssa(-1); got != 32766 { - fmt.Printf("xor_int16 -1%s-32767 = %d, wanted 32766\n", `^`, got) - failed = true - } - - if got := xor_Neg32767_int16_ssa(0); got != -32767 { - fmt.Printf("xor_int16 -32767%s0 = %d, wanted -32767\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32767_ssa(0); got != -32767 { - fmt.Printf("xor_int16 0%s-32767 = %d, wanted -32767\n", `^`, got) - failed = true - } - - if got := xor_Neg32767_int16_ssa(1); got != -32768 { - fmt.Printf("xor_int16 -32767%s1 = %d, wanted -32768\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32767_ssa(1); got != -32768 { - fmt.Printf("xor_int16 1%s-32767 = %d, wanted -32768\n", `^`, got) - failed = true - } - - if got := xor_Neg32767_int16_ssa(32766); got != -1 { - fmt.Printf("xor_int16 -32767%s32766 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32767_ssa(32766); got != -1 { - fmt.Printf("xor_int16 32766%s-32767 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_Neg32767_int16_ssa(32767); got != -2 { - fmt.Printf("xor_int16 -32767%s32767 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg32767_ssa(32767); got != -2 { - fmt.Printf("xor_int16 32767%s-32767 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int16_ssa(-32768); got != 32767 { - fmt.Printf("xor_int16 -1%s-32768 = %d, wanted 32767\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg1_ssa(-32768); got != 32767 { - fmt.Printf("xor_int16 -32768%s-1 = %d, wanted 32767\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int16_ssa(-32767); got != 32766 { - fmt.Printf("xor_int16 -1%s-32767 = %d, wanted 32766\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg1_ssa(-32767); got != 32766 { - fmt.Printf("xor_int16 -32767%s-1 = %d, wanted 32766\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int16_ssa(-1); got != 0 { - fmt.Printf("xor_int16 -1%s-1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg1_ssa(-1); got != 0 { - fmt.Printf("xor_int16 -1%s-1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int16_ssa(0); got != -1 { - fmt.Printf("xor_int16 -1%s0 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg1_ssa(0); got != -1 { - fmt.Printf("xor_int16 0%s-1 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int16_ssa(1); got != -2 { - fmt.Printf("xor_int16 -1%s1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg1_ssa(1); got != -2 { - fmt.Printf("xor_int16 1%s-1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int16_ssa(32766); got != -32767 { - fmt.Printf("xor_int16 -1%s32766 = %d, wanted -32767\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg1_ssa(32766); got != -32767 { - fmt.Printf("xor_int16 32766%s-1 = %d, wanted -32767\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int16_ssa(32767); got != -32768 { - fmt.Printf("xor_int16 -1%s32767 = %d, wanted -32768\n", `^`, got) - failed = true - } - - if got := xor_int16_Neg1_ssa(32767); got != -32768 { - fmt.Printf("xor_int16 32767%s-1 = %d, wanted -32768\n", `^`, got) - failed = true - } - - if got := xor_0_int16_ssa(-32768); got != -32768 { - fmt.Printf("xor_int16 0%s-32768 = %d, wanted -32768\n", `^`, got) - failed = true - } - - if got := xor_int16_0_ssa(-32768); got != -32768 { - fmt.Printf("xor_int16 -32768%s0 = %d, wanted -32768\n", `^`, got) - failed = true - } - - if got := xor_0_int16_ssa(-32767); got != -32767 { - fmt.Printf("xor_int16 0%s-32767 = %d, wanted -32767\n", `^`, got) - failed = true - } - - if got := xor_int16_0_ssa(-32767); got != -32767 { - fmt.Printf("xor_int16 -32767%s0 = %d, wanted -32767\n", `^`, got) - failed = true - } - - if got := xor_0_int16_ssa(-1); got != -1 { - fmt.Printf("xor_int16 0%s-1 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int16_0_ssa(-1); got != -1 { - fmt.Printf("xor_int16 -1%s0 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_0_int16_ssa(0); got != 0 { - fmt.Printf("xor_int16 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int16_0_ssa(0); got != 0 { - fmt.Printf("xor_int16 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_0_int16_ssa(1); got != 1 { - fmt.Printf("xor_int16 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int16_0_ssa(1); got != 1 { - fmt.Printf("xor_int16 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_0_int16_ssa(32766); got != 32766 { - fmt.Printf("xor_int16 0%s32766 = %d, wanted 32766\n", `^`, got) - failed = true - } - - if got := xor_int16_0_ssa(32766); got != 32766 { - fmt.Printf("xor_int16 32766%s0 = %d, wanted 32766\n", `^`, got) - failed = true - } - - if got := xor_0_int16_ssa(32767); got != 32767 { - fmt.Printf("xor_int16 0%s32767 = %d, wanted 32767\n", `^`, got) - failed = true - } - - if got := xor_int16_0_ssa(32767); got != 32767 { - fmt.Printf("xor_int16 32767%s0 = %d, wanted 32767\n", `^`, got) - failed = true - } - - if got := xor_1_int16_ssa(-32768); got != -32767 { - fmt.Printf("xor_int16 1%s-32768 = %d, wanted -32767\n", `^`, got) - failed = true - } - - if got := xor_int16_1_ssa(-32768); got != -32767 { - fmt.Printf("xor_int16 -32768%s1 = %d, wanted -32767\n", `^`, got) - failed = true - } - - if got := xor_1_int16_ssa(-32767); got != -32768 { - fmt.Printf("xor_int16 1%s-32767 = %d, wanted -32768\n", `^`, got) - failed = true - } - - if got := xor_int16_1_ssa(-32767); got != -32768 { - fmt.Printf("xor_int16 -32767%s1 = %d, wanted -32768\n", `^`, got) - failed = true - } - - if got := xor_1_int16_ssa(-1); got != -2 { - fmt.Printf("xor_int16 1%s-1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int16_1_ssa(-1); got != -2 { - fmt.Printf("xor_int16 -1%s1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_1_int16_ssa(0); got != 1 { - fmt.Printf("xor_int16 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int16_1_ssa(0); got != 1 { - fmt.Printf("xor_int16 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_1_int16_ssa(1); got != 0 { - fmt.Printf("xor_int16 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int16_1_ssa(1); got != 0 { - fmt.Printf("xor_int16 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_1_int16_ssa(32766); got != 32767 { - fmt.Printf("xor_int16 1%s32766 = %d, wanted 32767\n", `^`, got) - failed = true - } - - if got := xor_int16_1_ssa(32766); got != 32767 { - fmt.Printf("xor_int16 32766%s1 = %d, wanted 32767\n", `^`, got) - failed = true - } - - if got := xor_1_int16_ssa(32767); got != 32766 { - fmt.Printf("xor_int16 1%s32767 = %d, wanted 32766\n", `^`, got) - failed = true - } - - if got := xor_int16_1_ssa(32767); got != 32766 { - fmt.Printf("xor_int16 32767%s1 = %d, wanted 32766\n", `^`, got) - failed = true - } - - if got := xor_32766_int16_ssa(-32768); got != -2 { - fmt.Printf("xor_int16 32766%s-32768 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int16_32766_ssa(-32768); got != -2 { - fmt.Printf("xor_int16 -32768%s32766 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_32766_int16_ssa(-32767); got != -1 { - fmt.Printf("xor_int16 32766%s-32767 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int16_32766_ssa(-32767); got != -1 { - fmt.Printf("xor_int16 -32767%s32766 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_32766_int16_ssa(-1); got != -32767 { - fmt.Printf("xor_int16 32766%s-1 = %d, wanted -32767\n", `^`, got) - failed = true - } - - if got := xor_int16_32766_ssa(-1); got != -32767 { - fmt.Printf("xor_int16 -1%s32766 = %d, wanted -32767\n", `^`, got) - failed = true - } - - if got := xor_32766_int16_ssa(0); got != 32766 { - fmt.Printf("xor_int16 32766%s0 = %d, wanted 32766\n", `^`, got) - failed = true - } - - if got := xor_int16_32766_ssa(0); got != 32766 { - fmt.Printf("xor_int16 0%s32766 = %d, wanted 32766\n", `^`, got) - failed = true - } - - if got := xor_32766_int16_ssa(1); got != 32767 { - fmt.Printf("xor_int16 32766%s1 = %d, wanted 32767\n", `^`, got) - failed = true - } - - if got := xor_int16_32766_ssa(1); got != 32767 { - fmt.Printf("xor_int16 1%s32766 = %d, wanted 32767\n", `^`, got) - failed = true - } - - if got := xor_32766_int16_ssa(32766); got != 0 { - fmt.Printf("xor_int16 32766%s32766 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int16_32766_ssa(32766); got != 0 { - fmt.Printf("xor_int16 32766%s32766 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_32766_int16_ssa(32767); got != 1 { - fmt.Printf("xor_int16 32766%s32767 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int16_32766_ssa(32767); got != 1 { - fmt.Printf("xor_int16 32767%s32766 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_32767_int16_ssa(-32768); got != -1 { - fmt.Printf("xor_int16 32767%s-32768 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int16_32767_ssa(-32768); got != -1 { - fmt.Printf("xor_int16 -32768%s32767 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_32767_int16_ssa(-32767); got != -2 { - fmt.Printf("xor_int16 32767%s-32767 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int16_32767_ssa(-32767); got != -2 { - fmt.Printf("xor_int16 -32767%s32767 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_32767_int16_ssa(-1); got != -32768 { - fmt.Printf("xor_int16 32767%s-1 = %d, wanted -32768\n", `^`, got) - failed = true - } - - if got := xor_int16_32767_ssa(-1); got != -32768 { - fmt.Printf("xor_int16 -1%s32767 = %d, wanted -32768\n", `^`, got) - failed = true - } - - if got := xor_32767_int16_ssa(0); got != 32767 { - fmt.Printf("xor_int16 32767%s0 = %d, wanted 32767\n", `^`, got) - failed = true - } - - if got := xor_int16_32767_ssa(0); got != 32767 { - fmt.Printf("xor_int16 0%s32767 = %d, wanted 32767\n", `^`, got) - failed = true - } - - if got := xor_32767_int16_ssa(1); got != 32766 { - fmt.Printf("xor_int16 32767%s1 = %d, wanted 32766\n", `^`, got) - failed = true - } - - if got := xor_int16_32767_ssa(1); got != 32766 { - fmt.Printf("xor_int16 1%s32767 = %d, wanted 32766\n", `^`, got) - failed = true - } - - if got := xor_32767_int16_ssa(32766); got != 1 { - fmt.Printf("xor_int16 32767%s32766 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int16_32767_ssa(32766); got != 1 { - fmt.Printf("xor_int16 32766%s32767 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_32767_int16_ssa(32767); got != 0 { - fmt.Printf("xor_int16 32767%s32767 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int16_32767_ssa(32767); got != 0 { - fmt.Printf("xor_int16 32767%s32767 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := add_0_uint8_ssa(0); got != 0 { - fmt.Printf("add_uint8 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_uint8_0_ssa(0); got != 0 { - fmt.Printf("add_uint8 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_0_uint8_ssa(1); got != 1 { - fmt.Printf("add_uint8 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_uint8_0_ssa(1); got != 1 { - fmt.Printf("add_uint8 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_0_uint8_ssa(255); got != 255 { - fmt.Printf("add_uint8 0%s255 = %d, wanted 255\n", `+`, got) - failed = true - } - - if got := add_uint8_0_ssa(255); got != 255 { - fmt.Printf("add_uint8 255%s0 = %d, wanted 255\n", `+`, got) - failed = true - } - - if got := add_1_uint8_ssa(0); got != 1 { - fmt.Printf("add_uint8 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_uint8_1_ssa(0); got != 1 { - fmt.Printf("add_uint8 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_1_uint8_ssa(1); got != 2 { - fmt.Printf("add_uint8 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_uint8_1_ssa(1); got != 2 { - fmt.Printf("add_uint8 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_1_uint8_ssa(255); got != 0 { - fmt.Printf("add_uint8 1%s255 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_uint8_1_ssa(255); got != 0 { - fmt.Printf("add_uint8 255%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_255_uint8_ssa(0); got != 255 { - fmt.Printf("add_uint8 255%s0 = %d, wanted 255\n", `+`, got) - failed = true - } - - if got := add_uint8_255_ssa(0); got != 255 { - fmt.Printf("add_uint8 0%s255 = %d, wanted 255\n", `+`, got) - failed = true - } - - if got := add_255_uint8_ssa(1); got != 0 { - fmt.Printf("add_uint8 255%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_uint8_255_ssa(1); got != 0 { - fmt.Printf("add_uint8 1%s255 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_255_uint8_ssa(255); got != 254 { - fmt.Printf("add_uint8 255%s255 = %d, wanted 254\n", `+`, got) - failed = true - } - - if got := add_uint8_255_ssa(255); got != 254 { - fmt.Printf("add_uint8 255%s255 = %d, wanted 254\n", `+`, got) - failed = true - } - - if got := sub_0_uint8_ssa(0); got != 0 { - fmt.Printf("sub_uint8 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint8_0_ssa(0); got != 0 { - fmt.Printf("sub_uint8 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_0_uint8_ssa(1); got != 255 { - fmt.Printf("sub_uint8 0%s1 = %d, wanted 255\n", `-`, got) - failed = true - } - - if got := sub_uint8_0_ssa(1); got != 1 { - fmt.Printf("sub_uint8 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_0_uint8_ssa(255); got != 1 { - fmt.Printf("sub_uint8 0%s255 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_uint8_0_ssa(255); got != 255 { - fmt.Printf("sub_uint8 255%s0 = %d, wanted 255\n", `-`, got) - failed = true - } - - if got := sub_1_uint8_ssa(0); got != 1 { - fmt.Printf("sub_uint8 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_uint8_1_ssa(0); got != 255 { - fmt.Printf("sub_uint8 0%s1 = %d, wanted 255\n", `-`, got) - failed = true - } - - if got := sub_1_uint8_ssa(1); got != 0 { - fmt.Printf("sub_uint8 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint8_1_ssa(1); got != 0 { - fmt.Printf("sub_uint8 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_1_uint8_ssa(255); got != 2 { - fmt.Printf("sub_uint8 1%s255 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_uint8_1_ssa(255); got != 254 { - fmt.Printf("sub_uint8 255%s1 = %d, wanted 254\n", `-`, got) - failed = true - } - - if got := sub_255_uint8_ssa(0); got != 255 { - fmt.Printf("sub_uint8 255%s0 = %d, wanted 255\n", `-`, got) - failed = true - } - - if got := sub_uint8_255_ssa(0); got != 1 { - fmt.Printf("sub_uint8 0%s255 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_255_uint8_ssa(1); got != 254 { - fmt.Printf("sub_uint8 255%s1 = %d, wanted 254\n", `-`, got) - failed = true - } - - if got := sub_uint8_255_ssa(1); got != 2 { - fmt.Printf("sub_uint8 1%s255 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_255_uint8_ssa(255); got != 0 { - fmt.Printf("sub_uint8 255%s255 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_uint8_255_ssa(255); got != 0 { - fmt.Printf("sub_uint8 255%s255 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := div_0_uint8_ssa(1); got != 0 { - fmt.Printf("div_uint8 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_uint8_ssa(255); got != 0 { - fmt.Printf("div_uint8 0%s255 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_uint8_1_ssa(0); got != 0 { - fmt.Printf("div_uint8 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_1_uint8_ssa(1); got != 1 { - fmt.Printf("div_uint8 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_uint8_1_ssa(1); got != 1 { - fmt.Printf("div_uint8 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_1_uint8_ssa(255); got != 0 { - fmt.Printf("div_uint8 1%s255 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_uint8_1_ssa(255); got != 255 { - fmt.Printf("div_uint8 255%s1 = %d, wanted 255\n", `/`, got) - failed = true - } - - if got := div_uint8_255_ssa(0); got != 0 { - fmt.Printf("div_uint8 0%s255 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_255_uint8_ssa(1); got != 255 { - fmt.Printf("div_uint8 255%s1 = %d, wanted 255\n", `/`, got) - failed = true - } - - if got := div_uint8_255_ssa(1); got != 0 { - fmt.Printf("div_uint8 1%s255 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_255_uint8_ssa(255); got != 1 { - fmt.Printf("div_uint8 255%s255 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_uint8_255_ssa(255); got != 1 { - fmt.Printf("div_uint8 255%s255 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := mul_0_uint8_ssa(0); got != 0 { - fmt.Printf("mul_uint8 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint8_0_ssa(0); got != 0 { - fmt.Printf("mul_uint8 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_uint8_ssa(1); got != 0 { - fmt.Printf("mul_uint8 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint8_0_ssa(1); got != 0 { - fmt.Printf("mul_uint8 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_uint8_ssa(255); got != 0 { - fmt.Printf("mul_uint8 0%s255 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint8_0_ssa(255); got != 0 { - fmt.Printf("mul_uint8 255%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_uint8_ssa(0); got != 0 { - fmt.Printf("mul_uint8 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint8_1_ssa(0); got != 0 { - fmt.Printf("mul_uint8 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_uint8_ssa(1); got != 1 { - fmt.Printf("mul_uint8 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_uint8_1_ssa(1); got != 1 { - fmt.Printf("mul_uint8 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_1_uint8_ssa(255); got != 255 { - fmt.Printf("mul_uint8 1%s255 = %d, wanted 255\n", `*`, got) - failed = true - } - - if got := mul_uint8_1_ssa(255); got != 255 { - fmt.Printf("mul_uint8 255%s1 = %d, wanted 255\n", `*`, got) - failed = true - } - - if got := mul_255_uint8_ssa(0); got != 0 { - fmt.Printf("mul_uint8 255%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_uint8_255_ssa(0); got != 0 { - fmt.Printf("mul_uint8 0%s255 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_255_uint8_ssa(1); got != 255 { - fmt.Printf("mul_uint8 255%s1 = %d, wanted 255\n", `*`, got) - failed = true - } - - if got := mul_uint8_255_ssa(1); got != 255 { - fmt.Printf("mul_uint8 1%s255 = %d, wanted 255\n", `*`, got) - failed = true - } - - if got := mul_255_uint8_ssa(255); got != 1 { - fmt.Printf("mul_uint8 255%s255 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_uint8_255_ssa(255); got != 1 { - fmt.Printf("mul_uint8 255%s255 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := lsh_0_uint8_ssa(0); got != 0 { - fmt.Printf("lsh_uint8 0%s0 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint8_0_ssa(0); got != 0 { - fmt.Printf("lsh_uint8 0%s0 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_0_uint8_ssa(1); got != 0 { - fmt.Printf("lsh_uint8 0%s1 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint8_0_ssa(1); got != 1 { - fmt.Printf("lsh_uint8 1%s0 = %d, wanted 1\n", `<<`, got) - failed = true - } - - if got := lsh_0_uint8_ssa(255); got != 0 { - fmt.Printf("lsh_uint8 0%s255 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint8_0_ssa(255); got != 255 { - fmt.Printf("lsh_uint8 255%s0 = %d, wanted 255\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint8_ssa(0); got != 1 { - fmt.Printf("lsh_uint8 1%s0 = %d, wanted 1\n", `<<`, got) - failed = true - } - - if got := lsh_uint8_1_ssa(0); got != 0 { - fmt.Printf("lsh_uint8 0%s1 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint8_ssa(1); got != 2 { - fmt.Printf("lsh_uint8 1%s1 = %d, wanted 2\n", `<<`, got) - failed = true - } - - if got := lsh_uint8_1_ssa(1); got != 2 { - fmt.Printf("lsh_uint8 1%s1 = %d, wanted 2\n", `<<`, got) - failed = true - } - - if got := lsh_1_uint8_ssa(255); got != 0 { - fmt.Printf("lsh_uint8 1%s255 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint8_1_ssa(255); got != 254 { - fmt.Printf("lsh_uint8 255%s1 = %d, wanted 254\n", `<<`, got) - failed = true - } - - if got := lsh_255_uint8_ssa(0); got != 255 { - fmt.Printf("lsh_uint8 255%s0 = %d, wanted 255\n", `<<`, got) - failed = true - } - - if got := lsh_uint8_255_ssa(0); got != 0 { - fmt.Printf("lsh_uint8 0%s255 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_255_uint8_ssa(1); got != 254 { - fmt.Printf("lsh_uint8 255%s1 = %d, wanted 254\n", `<<`, got) - failed = true - } - - if got := lsh_uint8_255_ssa(1); got != 0 { - fmt.Printf("lsh_uint8 1%s255 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_255_uint8_ssa(255); got != 0 { - fmt.Printf("lsh_uint8 255%s255 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := lsh_uint8_255_ssa(255); got != 0 { - fmt.Printf("lsh_uint8 255%s255 = %d, wanted 0\n", `<<`, got) - failed = true - } - - if got := rsh_0_uint8_ssa(0); got != 0 { - fmt.Printf("rsh_uint8 0%s0 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint8_0_ssa(0); got != 0 { - fmt.Printf("rsh_uint8 0%s0 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_0_uint8_ssa(1); got != 0 { - fmt.Printf("rsh_uint8 0%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint8_0_ssa(1); got != 1 { - fmt.Printf("rsh_uint8 1%s0 = %d, wanted 1\n", `>>`, got) - failed = true - } - - if got := rsh_0_uint8_ssa(255); got != 0 { - fmt.Printf("rsh_uint8 0%s255 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint8_0_ssa(255); got != 255 { - fmt.Printf("rsh_uint8 255%s0 = %d, wanted 255\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint8_ssa(0); got != 1 { - fmt.Printf("rsh_uint8 1%s0 = %d, wanted 1\n", `>>`, got) - failed = true - } - - if got := rsh_uint8_1_ssa(0); got != 0 { - fmt.Printf("rsh_uint8 0%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint8_ssa(1); got != 0 { - fmt.Printf("rsh_uint8 1%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint8_1_ssa(1); got != 0 { - fmt.Printf("rsh_uint8 1%s1 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_1_uint8_ssa(255); got != 0 { - fmt.Printf("rsh_uint8 1%s255 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint8_1_ssa(255); got != 127 { - fmt.Printf("rsh_uint8 255%s1 = %d, wanted 127\n", `>>`, got) - failed = true - } - - if got := rsh_255_uint8_ssa(0); got != 255 { - fmt.Printf("rsh_uint8 255%s0 = %d, wanted 255\n", `>>`, got) - failed = true - } - - if got := rsh_uint8_255_ssa(0); got != 0 { - fmt.Printf("rsh_uint8 0%s255 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_255_uint8_ssa(1); got != 127 { - fmt.Printf("rsh_uint8 255%s1 = %d, wanted 127\n", `>>`, got) - failed = true - } - - if got := rsh_uint8_255_ssa(1); got != 0 { - fmt.Printf("rsh_uint8 1%s255 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_255_uint8_ssa(255); got != 0 { - fmt.Printf("rsh_uint8 255%s255 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := rsh_uint8_255_ssa(255); got != 0 { - fmt.Printf("rsh_uint8 255%s255 = %d, wanted 0\n", `>>`, got) - failed = true - } - - if got := mod_0_uint8_ssa(1); got != 0 { - fmt.Printf("mod_uint8 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_uint8_ssa(255); got != 0 { - fmt.Printf("mod_uint8 0%s255 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint8_1_ssa(0); got != 0 { - fmt.Printf("mod_uint8 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_uint8_ssa(1); got != 0 { - fmt.Printf("mod_uint8 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint8_1_ssa(1); got != 0 { - fmt.Printf("mod_uint8 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_uint8_ssa(255); got != 1 { - fmt.Printf("mod_uint8 1%s255 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_uint8_1_ssa(255); got != 0 { - fmt.Printf("mod_uint8 255%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint8_255_ssa(0); got != 0 { - fmt.Printf("mod_uint8 0%s255 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_255_uint8_ssa(1); got != 0 { - fmt.Printf("mod_uint8 255%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint8_255_ssa(1); got != 1 { - fmt.Printf("mod_uint8 1%s255 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_255_uint8_ssa(255); got != 0 { - fmt.Printf("mod_uint8 255%s255 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_uint8_255_ssa(255); got != 0 { - fmt.Printf("mod_uint8 255%s255 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := and_0_uint8_ssa(0); got != 0 { - fmt.Printf("and_uint8 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint8_0_ssa(0); got != 0 { - fmt.Printf("and_uint8 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_uint8_ssa(1); got != 0 { - fmt.Printf("and_uint8 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint8_0_ssa(1); got != 0 { - fmt.Printf("and_uint8 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_uint8_ssa(255); got != 0 { - fmt.Printf("and_uint8 0%s255 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint8_0_ssa(255); got != 0 { - fmt.Printf("and_uint8 255%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_uint8_ssa(0); got != 0 { - fmt.Printf("and_uint8 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint8_1_ssa(0); got != 0 { - fmt.Printf("and_uint8 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_uint8_ssa(1); got != 1 { - fmt.Printf("and_uint8 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_uint8_1_ssa(1); got != 1 { - fmt.Printf("and_uint8 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_uint8_ssa(255); got != 1 { - fmt.Printf("and_uint8 1%s255 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_uint8_1_ssa(255); got != 1 { - fmt.Printf("and_uint8 255%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_255_uint8_ssa(0); got != 0 { - fmt.Printf("and_uint8 255%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_uint8_255_ssa(0); got != 0 { - fmt.Printf("and_uint8 0%s255 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_255_uint8_ssa(1); got != 1 { - fmt.Printf("and_uint8 255%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_uint8_255_ssa(1); got != 1 { - fmt.Printf("and_uint8 1%s255 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_255_uint8_ssa(255); got != 255 { - fmt.Printf("and_uint8 255%s255 = %d, wanted 255\n", `&`, got) - failed = true - } - - if got := and_uint8_255_ssa(255); got != 255 { - fmt.Printf("and_uint8 255%s255 = %d, wanted 255\n", `&`, got) - failed = true - } - - if got := or_0_uint8_ssa(0); got != 0 { - fmt.Printf("or_uint8 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_uint8_0_ssa(0); got != 0 { - fmt.Printf("or_uint8 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_0_uint8_ssa(1); got != 1 { - fmt.Printf("or_uint8 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_uint8_0_ssa(1); got != 1 { - fmt.Printf("or_uint8 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_0_uint8_ssa(255); got != 255 { - fmt.Printf("or_uint8 0%s255 = %d, wanted 255\n", `|`, got) - failed = true - } - - if got := or_uint8_0_ssa(255); got != 255 { - fmt.Printf("or_uint8 255%s0 = %d, wanted 255\n", `|`, got) - failed = true - } - - if got := or_1_uint8_ssa(0); got != 1 { - fmt.Printf("or_uint8 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_uint8_1_ssa(0); got != 1 { - fmt.Printf("or_uint8 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_uint8_ssa(1); got != 1 { - fmt.Printf("or_uint8 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_uint8_1_ssa(1); got != 1 { - fmt.Printf("or_uint8 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_uint8_ssa(255); got != 255 { - fmt.Printf("or_uint8 1%s255 = %d, wanted 255\n", `|`, got) - failed = true - } - - if got := or_uint8_1_ssa(255); got != 255 { - fmt.Printf("or_uint8 255%s1 = %d, wanted 255\n", `|`, got) - failed = true - } - - if got := or_255_uint8_ssa(0); got != 255 { - fmt.Printf("or_uint8 255%s0 = %d, wanted 255\n", `|`, got) - failed = true - } - - if got := or_uint8_255_ssa(0); got != 255 { - fmt.Printf("or_uint8 0%s255 = %d, wanted 255\n", `|`, got) - failed = true - } - - if got := or_255_uint8_ssa(1); got != 255 { - fmt.Printf("or_uint8 255%s1 = %d, wanted 255\n", `|`, got) - failed = true - } - - if got := or_uint8_255_ssa(1); got != 255 { - fmt.Printf("or_uint8 1%s255 = %d, wanted 255\n", `|`, got) - failed = true - } - - if got := or_255_uint8_ssa(255); got != 255 { - fmt.Printf("or_uint8 255%s255 = %d, wanted 255\n", `|`, got) - failed = true - } - - if got := or_uint8_255_ssa(255); got != 255 { - fmt.Printf("or_uint8 255%s255 = %d, wanted 255\n", `|`, got) - failed = true - } - - if got := xor_0_uint8_ssa(0); got != 0 { - fmt.Printf("xor_uint8 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint8_0_ssa(0); got != 0 { - fmt.Printf("xor_uint8 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_0_uint8_ssa(1); got != 1 { - fmt.Printf("xor_uint8 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_uint8_0_ssa(1); got != 1 { - fmt.Printf("xor_uint8 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_0_uint8_ssa(255); got != 255 { - fmt.Printf("xor_uint8 0%s255 = %d, wanted 255\n", `^`, got) - failed = true - } - - if got := xor_uint8_0_ssa(255); got != 255 { - fmt.Printf("xor_uint8 255%s0 = %d, wanted 255\n", `^`, got) - failed = true - } - - if got := xor_1_uint8_ssa(0); got != 1 { - fmt.Printf("xor_uint8 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_uint8_1_ssa(0); got != 1 { - fmt.Printf("xor_uint8 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_1_uint8_ssa(1); got != 0 { - fmt.Printf("xor_uint8 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint8_1_ssa(1); got != 0 { - fmt.Printf("xor_uint8 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_1_uint8_ssa(255); got != 254 { - fmt.Printf("xor_uint8 1%s255 = %d, wanted 254\n", `^`, got) - failed = true - } - - if got := xor_uint8_1_ssa(255); got != 254 { - fmt.Printf("xor_uint8 255%s1 = %d, wanted 254\n", `^`, got) - failed = true - } - - if got := xor_255_uint8_ssa(0); got != 255 { - fmt.Printf("xor_uint8 255%s0 = %d, wanted 255\n", `^`, got) - failed = true - } - - if got := xor_uint8_255_ssa(0); got != 255 { - fmt.Printf("xor_uint8 0%s255 = %d, wanted 255\n", `^`, got) - failed = true - } - - if got := xor_255_uint8_ssa(1); got != 254 { - fmt.Printf("xor_uint8 255%s1 = %d, wanted 254\n", `^`, got) - failed = true - } - - if got := xor_uint8_255_ssa(1); got != 254 { - fmt.Printf("xor_uint8 1%s255 = %d, wanted 254\n", `^`, got) - failed = true - } - - if got := xor_255_uint8_ssa(255); got != 0 { - fmt.Printf("xor_uint8 255%s255 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_uint8_255_ssa(255); got != 0 { - fmt.Printf("xor_uint8 255%s255 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := add_Neg128_int8_ssa(-128); got != 0 { - fmt.Printf("add_int8 -128%s-128 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int8_Neg128_ssa(-128); got != 0 { - fmt.Printf("add_int8 -128%s-128 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_Neg128_int8_ssa(-127); got != 1 { - fmt.Printf("add_int8 -128%s-127 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int8_Neg128_ssa(-127); got != 1 { - fmt.Printf("add_int8 -127%s-128 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_Neg128_int8_ssa(-1); got != 127 { - fmt.Printf("add_int8 -128%s-1 = %d, wanted 127\n", `+`, got) - failed = true - } - - if got := add_int8_Neg128_ssa(-1); got != 127 { - fmt.Printf("add_int8 -1%s-128 = %d, wanted 127\n", `+`, got) - failed = true - } - - if got := add_Neg128_int8_ssa(0); got != -128 { - fmt.Printf("add_int8 -128%s0 = %d, wanted -128\n", `+`, got) - failed = true - } - - if got := add_int8_Neg128_ssa(0); got != -128 { - fmt.Printf("add_int8 0%s-128 = %d, wanted -128\n", `+`, got) - failed = true - } - - if got := add_Neg128_int8_ssa(1); got != -127 { - fmt.Printf("add_int8 -128%s1 = %d, wanted -127\n", `+`, got) - failed = true - } - - if got := add_int8_Neg128_ssa(1); got != -127 { - fmt.Printf("add_int8 1%s-128 = %d, wanted -127\n", `+`, got) - failed = true - } - - if got := add_Neg128_int8_ssa(126); got != -2 { - fmt.Printf("add_int8 -128%s126 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int8_Neg128_ssa(126); got != -2 { - fmt.Printf("add_int8 126%s-128 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_Neg128_int8_ssa(127); got != -1 { - fmt.Printf("add_int8 -128%s127 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int8_Neg128_ssa(127); got != -1 { - fmt.Printf("add_int8 127%s-128 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_Neg127_int8_ssa(-128); got != 1 { - fmt.Printf("add_int8 -127%s-128 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int8_Neg127_ssa(-128); got != 1 { - fmt.Printf("add_int8 -128%s-127 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_Neg127_int8_ssa(-127); got != 2 { - fmt.Printf("add_int8 -127%s-127 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_int8_Neg127_ssa(-127); got != 2 { - fmt.Printf("add_int8 -127%s-127 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_Neg127_int8_ssa(-1); got != -128 { - fmt.Printf("add_int8 -127%s-1 = %d, wanted -128\n", `+`, got) - failed = true - } - - if got := add_int8_Neg127_ssa(-1); got != -128 { - fmt.Printf("add_int8 -1%s-127 = %d, wanted -128\n", `+`, got) - failed = true - } - - if got := add_Neg127_int8_ssa(0); got != -127 { - fmt.Printf("add_int8 -127%s0 = %d, wanted -127\n", `+`, got) - failed = true - } - - if got := add_int8_Neg127_ssa(0); got != -127 { - fmt.Printf("add_int8 0%s-127 = %d, wanted -127\n", `+`, got) - failed = true - } - - if got := add_Neg127_int8_ssa(1); got != -126 { - fmt.Printf("add_int8 -127%s1 = %d, wanted -126\n", `+`, got) - failed = true - } - - if got := add_int8_Neg127_ssa(1); got != -126 { - fmt.Printf("add_int8 1%s-127 = %d, wanted -126\n", `+`, got) - failed = true - } - - if got := add_Neg127_int8_ssa(126); got != -1 { - fmt.Printf("add_int8 -127%s126 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int8_Neg127_ssa(126); got != -1 { - fmt.Printf("add_int8 126%s-127 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_Neg127_int8_ssa(127); got != 0 { - fmt.Printf("add_int8 -127%s127 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int8_Neg127_ssa(127); got != 0 { - fmt.Printf("add_int8 127%s-127 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_Neg1_int8_ssa(-128); got != 127 { - fmt.Printf("add_int8 -1%s-128 = %d, wanted 127\n", `+`, got) - failed = true - } - - if got := add_int8_Neg1_ssa(-128); got != 127 { - fmt.Printf("add_int8 -128%s-1 = %d, wanted 127\n", `+`, got) - failed = true - } - - if got := add_Neg1_int8_ssa(-127); got != -128 { - fmt.Printf("add_int8 -1%s-127 = %d, wanted -128\n", `+`, got) - failed = true - } - - if got := add_int8_Neg1_ssa(-127); got != -128 { - fmt.Printf("add_int8 -127%s-1 = %d, wanted -128\n", `+`, got) - failed = true - } - - if got := add_Neg1_int8_ssa(-1); got != -2 { - fmt.Printf("add_int8 -1%s-1 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int8_Neg1_ssa(-1); got != -2 { - fmt.Printf("add_int8 -1%s-1 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_Neg1_int8_ssa(0); got != -1 { - fmt.Printf("add_int8 -1%s0 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int8_Neg1_ssa(0); got != -1 { - fmt.Printf("add_int8 0%s-1 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_Neg1_int8_ssa(1); got != 0 { - fmt.Printf("add_int8 -1%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int8_Neg1_ssa(1); got != 0 { - fmt.Printf("add_int8 1%s-1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_Neg1_int8_ssa(126); got != 125 { - fmt.Printf("add_int8 -1%s126 = %d, wanted 125\n", `+`, got) - failed = true - } - - if got := add_int8_Neg1_ssa(126); got != 125 { - fmt.Printf("add_int8 126%s-1 = %d, wanted 125\n", `+`, got) - failed = true - } - - if got := add_Neg1_int8_ssa(127); got != 126 { - fmt.Printf("add_int8 -1%s127 = %d, wanted 126\n", `+`, got) - failed = true - } - - if got := add_int8_Neg1_ssa(127); got != 126 { - fmt.Printf("add_int8 127%s-1 = %d, wanted 126\n", `+`, got) - failed = true - } - - if got := add_0_int8_ssa(-128); got != -128 { - fmt.Printf("add_int8 0%s-128 = %d, wanted -128\n", `+`, got) - failed = true - } - - if got := add_int8_0_ssa(-128); got != -128 { - fmt.Printf("add_int8 -128%s0 = %d, wanted -128\n", `+`, got) - failed = true - } - - if got := add_0_int8_ssa(-127); got != -127 { - fmt.Printf("add_int8 0%s-127 = %d, wanted -127\n", `+`, got) - failed = true - } - - if got := add_int8_0_ssa(-127); got != -127 { - fmt.Printf("add_int8 -127%s0 = %d, wanted -127\n", `+`, got) - failed = true - } - - if got := add_0_int8_ssa(-1); got != -1 { - fmt.Printf("add_int8 0%s-1 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int8_0_ssa(-1); got != -1 { - fmt.Printf("add_int8 -1%s0 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_0_int8_ssa(0); got != 0 { - fmt.Printf("add_int8 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int8_0_ssa(0); got != 0 { - fmt.Printf("add_int8 0%s0 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_0_int8_ssa(1); got != 1 { - fmt.Printf("add_int8 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int8_0_ssa(1); got != 1 { - fmt.Printf("add_int8 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_0_int8_ssa(126); got != 126 { - fmt.Printf("add_int8 0%s126 = %d, wanted 126\n", `+`, got) - failed = true - } - - if got := add_int8_0_ssa(126); got != 126 { - fmt.Printf("add_int8 126%s0 = %d, wanted 126\n", `+`, got) - failed = true - } - - if got := add_0_int8_ssa(127); got != 127 { - fmt.Printf("add_int8 0%s127 = %d, wanted 127\n", `+`, got) - failed = true - } - - if got := add_int8_0_ssa(127); got != 127 { - fmt.Printf("add_int8 127%s0 = %d, wanted 127\n", `+`, got) - failed = true - } - - if got := add_1_int8_ssa(-128); got != -127 { - fmt.Printf("add_int8 1%s-128 = %d, wanted -127\n", `+`, got) - failed = true - } - - if got := add_int8_1_ssa(-128); got != -127 { - fmt.Printf("add_int8 -128%s1 = %d, wanted -127\n", `+`, got) - failed = true - } - - if got := add_1_int8_ssa(-127); got != -126 { - fmt.Printf("add_int8 1%s-127 = %d, wanted -126\n", `+`, got) - failed = true - } - - if got := add_int8_1_ssa(-127); got != -126 { - fmt.Printf("add_int8 -127%s1 = %d, wanted -126\n", `+`, got) - failed = true - } - - if got := add_1_int8_ssa(-1); got != 0 { - fmt.Printf("add_int8 1%s-1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int8_1_ssa(-1); got != 0 { - fmt.Printf("add_int8 -1%s1 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_1_int8_ssa(0); got != 1 { - fmt.Printf("add_int8 1%s0 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_int8_1_ssa(0); got != 1 { - fmt.Printf("add_int8 0%s1 = %d, wanted 1\n", `+`, got) - failed = true - } - - if got := add_1_int8_ssa(1); got != 2 { - fmt.Printf("add_int8 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_int8_1_ssa(1); got != 2 { - fmt.Printf("add_int8 1%s1 = %d, wanted 2\n", `+`, got) - failed = true - } - - if got := add_1_int8_ssa(126); got != 127 { - fmt.Printf("add_int8 1%s126 = %d, wanted 127\n", `+`, got) - failed = true - } - - if got := add_int8_1_ssa(126); got != 127 { - fmt.Printf("add_int8 126%s1 = %d, wanted 127\n", `+`, got) - failed = true - } - - if got := add_1_int8_ssa(127); got != -128 { - fmt.Printf("add_int8 1%s127 = %d, wanted -128\n", `+`, got) - failed = true - } - - if got := add_int8_1_ssa(127); got != -128 { - fmt.Printf("add_int8 127%s1 = %d, wanted -128\n", `+`, got) - failed = true - } - - if got := add_126_int8_ssa(-128); got != -2 { - fmt.Printf("add_int8 126%s-128 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int8_126_ssa(-128); got != -2 { - fmt.Printf("add_int8 -128%s126 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_126_int8_ssa(-127); got != -1 { - fmt.Printf("add_int8 126%s-127 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int8_126_ssa(-127); got != -1 { - fmt.Printf("add_int8 -127%s126 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_126_int8_ssa(-1); got != 125 { - fmt.Printf("add_int8 126%s-1 = %d, wanted 125\n", `+`, got) - failed = true - } - - if got := add_int8_126_ssa(-1); got != 125 { - fmt.Printf("add_int8 -1%s126 = %d, wanted 125\n", `+`, got) - failed = true - } - - if got := add_126_int8_ssa(0); got != 126 { - fmt.Printf("add_int8 126%s0 = %d, wanted 126\n", `+`, got) - failed = true - } - - if got := add_int8_126_ssa(0); got != 126 { - fmt.Printf("add_int8 0%s126 = %d, wanted 126\n", `+`, got) - failed = true - } - - if got := add_126_int8_ssa(1); got != 127 { - fmt.Printf("add_int8 126%s1 = %d, wanted 127\n", `+`, got) - failed = true - } - - if got := add_int8_126_ssa(1); got != 127 { - fmt.Printf("add_int8 1%s126 = %d, wanted 127\n", `+`, got) - failed = true - } - - if got := add_126_int8_ssa(126); got != -4 { - fmt.Printf("add_int8 126%s126 = %d, wanted -4\n", `+`, got) - failed = true - } - - if got := add_int8_126_ssa(126); got != -4 { - fmt.Printf("add_int8 126%s126 = %d, wanted -4\n", `+`, got) - failed = true - } - - if got := add_126_int8_ssa(127); got != -3 { - fmt.Printf("add_int8 126%s127 = %d, wanted -3\n", `+`, got) - failed = true - } - - if got := add_int8_126_ssa(127); got != -3 { - fmt.Printf("add_int8 127%s126 = %d, wanted -3\n", `+`, got) - failed = true - } - - if got := add_127_int8_ssa(-128); got != -1 { - fmt.Printf("add_int8 127%s-128 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_int8_127_ssa(-128); got != -1 { - fmt.Printf("add_int8 -128%s127 = %d, wanted -1\n", `+`, got) - failed = true - } - - if got := add_127_int8_ssa(-127); got != 0 { - fmt.Printf("add_int8 127%s-127 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_int8_127_ssa(-127); got != 0 { - fmt.Printf("add_int8 -127%s127 = %d, wanted 0\n", `+`, got) - failed = true - } - - if got := add_127_int8_ssa(-1); got != 126 { - fmt.Printf("add_int8 127%s-1 = %d, wanted 126\n", `+`, got) - failed = true - } - - if got := add_int8_127_ssa(-1); got != 126 { - fmt.Printf("add_int8 -1%s127 = %d, wanted 126\n", `+`, got) - failed = true - } - - if got := add_127_int8_ssa(0); got != 127 { - fmt.Printf("add_int8 127%s0 = %d, wanted 127\n", `+`, got) - failed = true - } - - if got := add_int8_127_ssa(0); got != 127 { - fmt.Printf("add_int8 0%s127 = %d, wanted 127\n", `+`, got) - failed = true - } - - if got := add_127_int8_ssa(1); got != -128 { - fmt.Printf("add_int8 127%s1 = %d, wanted -128\n", `+`, got) - failed = true - } - - if got := add_int8_127_ssa(1); got != -128 { - fmt.Printf("add_int8 1%s127 = %d, wanted -128\n", `+`, got) - failed = true - } - - if got := add_127_int8_ssa(126); got != -3 { - fmt.Printf("add_int8 127%s126 = %d, wanted -3\n", `+`, got) - failed = true - } - - if got := add_int8_127_ssa(126); got != -3 { - fmt.Printf("add_int8 126%s127 = %d, wanted -3\n", `+`, got) - failed = true - } - - if got := add_127_int8_ssa(127); got != -2 { - fmt.Printf("add_int8 127%s127 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := add_int8_127_ssa(127); got != -2 { - fmt.Printf("add_int8 127%s127 = %d, wanted -2\n", `+`, got) - failed = true - } - - if got := sub_Neg128_int8_ssa(-128); got != 0 { - fmt.Printf("sub_int8 -128%s-128 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg128_ssa(-128); got != 0 { - fmt.Printf("sub_int8 -128%s-128 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_Neg128_int8_ssa(-127); got != -1 { - fmt.Printf("sub_int8 -128%s-127 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg128_ssa(-127); got != 1 { - fmt.Printf("sub_int8 -127%s-128 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_Neg128_int8_ssa(-1); got != -127 { - fmt.Printf("sub_int8 -128%s-1 = %d, wanted -127\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg128_ssa(-1); got != 127 { - fmt.Printf("sub_int8 -1%s-128 = %d, wanted 127\n", `-`, got) - failed = true - } - - if got := sub_Neg128_int8_ssa(0); got != -128 { - fmt.Printf("sub_int8 -128%s0 = %d, wanted -128\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg128_ssa(0); got != -128 { - fmt.Printf("sub_int8 0%s-128 = %d, wanted -128\n", `-`, got) - failed = true - } - - if got := sub_Neg128_int8_ssa(1); got != 127 { - fmt.Printf("sub_int8 -128%s1 = %d, wanted 127\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg128_ssa(1); got != -127 { - fmt.Printf("sub_int8 1%s-128 = %d, wanted -127\n", `-`, got) - failed = true - } - - if got := sub_Neg128_int8_ssa(126); got != 2 { - fmt.Printf("sub_int8 -128%s126 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg128_ssa(126); got != -2 { - fmt.Printf("sub_int8 126%s-128 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_Neg128_int8_ssa(127); got != 1 { - fmt.Printf("sub_int8 -128%s127 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg128_ssa(127); got != -1 { - fmt.Printf("sub_int8 127%s-128 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_Neg127_int8_ssa(-128); got != 1 { - fmt.Printf("sub_int8 -127%s-128 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg127_ssa(-128); got != -1 { - fmt.Printf("sub_int8 -128%s-127 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_Neg127_int8_ssa(-127); got != 0 { - fmt.Printf("sub_int8 -127%s-127 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg127_ssa(-127); got != 0 { - fmt.Printf("sub_int8 -127%s-127 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_Neg127_int8_ssa(-1); got != -126 { - fmt.Printf("sub_int8 -127%s-1 = %d, wanted -126\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg127_ssa(-1); got != 126 { - fmt.Printf("sub_int8 -1%s-127 = %d, wanted 126\n", `-`, got) - failed = true - } - - if got := sub_Neg127_int8_ssa(0); got != -127 { - fmt.Printf("sub_int8 -127%s0 = %d, wanted -127\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg127_ssa(0); got != 127 { - fmt.Printf("sub_int8 0%s-127 = %d, wanted 127\n", `-`, got) - failed = true - } - - if got := sub_Neg127_int8_ssa(1); got != -128 { - fmt.Printf("sub_int8 -127%s1 = %d, wanted -128\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg127_ssa(1); got != -128 { - fmt.Printf("sub_int8 1%s-127 = %d, wanted -128\n", `-`, got) - failed = true - } - - if got := sub_Neg127_int8_ssa(126); got != 3 { - fmt.Printf("sub_int8 -127%s126 = %d, wanted 3\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg127_ssa(126); got != -3 { - fmt.Printf("sub_int8 126%s-127 = %d, wanted -3\n", `-`, got) - failed = true - } - - if got := sub_Neg127_int8_ssa(127); got != 2 { - fmt.Printf("sub_int8 -127%s127 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg127_ssa(127); got != -2 { - fmt.Printf("sub_int8 127%s-127 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int8_ssa(-128); got != 127 { - fmt.Printf("sub_int8 -1%s-128 = %d, wanted 127\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg1_ssa(-128); got != -127 { - fmt.Printf("sub_int8 -128%s-1 = %d, wanted -127\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int8_ssa(-127); got != 126 { - fmt.Printf("sub_int8 -1%s-127 = %d, wanted 126\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg1_ssa(-127); got != -126 { - fmt.Printf("sub_int8 -127%s-1 = %d, wanted -126\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int8_ssa(-1); got != 0 { - fmt.Printf("sub_int8 -1%s-1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg1_ssa(-1); got != 0 { - fmt.Printf("sub_int8 -1%s-1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int8_ssa(0); got != -1 { - fmt.Printf("sub_int8 -1%s0 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg1_ssa(0); got != 1 { - fmt.Printf("sub_int8 0%s-1 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int8_ssa(1); got != -2 { - fmt.Printf("sub_int8 -1%s1 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg1_ssa(1); got != 2 { - fmt.Printf("sub_int8 1%s-1 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int8_ssa(126); got != -127 { - fmt.Printf("sub_int8 -1%s126 = %d, wanted -127\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg1_ssa(126); got != 127 { - fmt.Printf("sub_int8 126%s-1 = %d, wanted 127\n", `-`, got) - failed = true - } - - if got := sub_Neg1_int8_ssa(127); got != -128 { - fmt.Printf("sub_int8 -1%s127 = %d, wanted -128\n", `-`, got) - failed = true - } - - if got := sub_int8_Neg1_ssa(127); got != -128 { - fmt.Printf("sub_int8 127%s-1 = %d, wanted -128\n", `-`, got) - failed = true - } - - if got := sub_0_int8_ssa(-128); got != -128 { - fmt.Printf("sub_int8 0%s-128 = %d, wanted -128\n", `-`, got) - failed = true - } - - if got := sub_int8_0_ssa(-128); got != -128 { - fmt.Printf("sub_int8 -128%s0 = %d, wanted -128\n", `-`, got) - failed = true - } - - if got := sub_0_int8_ssa(-127); got != 127 { - fmt.Printf("sub_int8 0%s-127 = %d, wanted 127\n", `-`, got) - failed = true - } - - if got := sub_int8_0_ssa(-127); got != -127 { - fmt.Printf("sub_int8 -127%s0 = %d, wanted -127\n", `-`, got) - failed = true - } - - if got := sub_0_int8_ssa(-1); got != 1 { - fmt.Printf("sub_int8 0%s-1 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int8_0_ssa(-1); got != -1 { - fmt.Printf("sub_int8 -1%s0 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_0_int8_ssa(0); got != 0 { - fmt.Printf("sub_int8 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int8_0_ssa(0); got != 0 { - fmt.Printf("sub_int8 0%s0 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_0_int8_ssa(1); got != -1 { - fmt.Printf("sub_int8 0%s1 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int8_0_ssa(1); got != 1 { - fmt.Printf("sub_int8 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_0_int8_ssa(126); got != -126 { - fmt.Printf("sub_int8 0%s126 = %d, wanted -126\n", `-`, got) - failed = true - } - - if got := sub_int8_0_ssa(126); got != 126 { - fmt.Printf("sub_int8 126%s0 = %d, wanted 126\n", `-`, got) - failed = true - } - - if got := sub_0_int8_ssa(127); got != -127 { - fmt.Printf("sub_int8 0%s127 = %d, wanted -127\n", `-`, got) - failed = true - } - - if got := sub_int8_0_ssa(127); got != 127 { - fmt.Printf("sub_int8 127%s0 = %d, wanted 127\n", `-`, got) - failed = true - } - - if got := sub_1_int8_ssa(-128); got != -127 { - fmt.Printf("sub_int8 1%s-128 = %d, wanted -127\n", `-`, got) - failed = true - } - - if got := sub_int8_1_ssa(-128); got != 127 { - fmt.Printf("sub_int8 -128%s1 = %d, wanted 127\n", `-`, got) - failed = true - } - - if got := sub_1_int8_ssa(-127); got != -128 { - fmt.Printf("sub_int8 1%s-127 = %d, wanted -128\n", `-`, got) - failed = true - } - - if got := sub_int8_1_ssa(-127); got != -128 { - fmt.Printf("sub_int8 -127%s1 = %d, wanted -128\n", `-`, got) - failed = true - } - - if got := sub_1_int8_ssa(-1); got != 2 { - fmt.Printf("sub_int8 1%s-1 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_int8_1_ssa(-1); got != -2 { - fmt.Printf("sub_int8 -1%s1 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_1_int8_ssa(0); got != 1 { - fmt.Printf("sub_int8 1%s0 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int8_1_ssa(0); got != -1 { - fmt.Printf("sub_int8 0%s1 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_1_int8_ssa(1); got != 0 { - fmt.Printf("sub_int8 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int8_1_ssa(1); got != 0 { - fmt.Printf("sub_int8 1%s1 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_1_int8_ssa(126); got != -125 { - fmt.Printf("sub_int8 1%s126 = %d, wanted -125\n", `-`, got) - failed = true - } - - if got := sub_int8_1_ssa(126); got != 125 { - fmt.Printf("sub_int8 126%s1 = %d, wanted 125\n", `-`, got) - failed = true - } - - if got := sub_1_int8_ssa(127); got != -126 { - fmt.Printf("sub_int8 1%s127 = %d, wanted -126\n", `-`, got) - failed = true - } - - if got := sub_int8_1_ssa(127); got != 126 { - fmt.Printf("sub_int8 127%s1 = %d, wanted 126\n", `-`, got) - failed = true - } - - if got := sub_126_int8_ssa(-128); got != -2 { - fmt.Printf("sub_int8 126%s-128 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_int8_126_ssa(-128); got != 2 { - fmt.Printf("sub_int8 -128%s126 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_126_int8_ssa(-127); got != -3 { - fmt.Printf("sub_int8 126%s-127 = %d, wanted -3\n", `-`, got) - failed = true - } - - if got := sub_int8_126_ssa(-127); got != 3 { - fmt.Printf("sub_int8 -127%s126 = %d, wanted 3\n", `-`, got) - failed = true - } - - if got := sub_126_int8_ssa(-1); got != 127 { - fmt.Printf("sub_int8 126%s-1 = %d, wanted 127\n", `-`, got) - failed = true - } - - if got := sub_int8_126_ssa(-1); got != -127 { - fmt.Printf("sub_int8 -1%s126 = %d, wanted -127\n", `-`, got) - failed = true - } - - if got := sub_126_int8_ssa(0); got != 126 { - fmt.Printf("sub_int8 126%s0 = %d, wanted 126\n", `-`, got) - failed = true - } - - if got := sub_int8_126_ssa(0); got != -126 { - fmt.Printf("sub_int8 0%s126 = %d, wanted -126\n", `-`, got) - failed = true - } - - if got := sub_126_int8_ssa(1); got != 125 { - fmt.Printf("sub_int8 126%s1 = %d, wanted 125\n", `-`, got) - failed = true - } - - if got := sub_int8_126_ssa(1); got != -125 { - fmt.Printf("sub_int8 1%s126 = %d, wanted -125\n", `-`, got) - failed = true - } - - if got := sub_126_int8_ssa(126); got != 0 { - fmt.Printf("sub_int8 126%s126 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int8_126_ssa(126); got != 0 { - fmt.Printf("sub_int8 126%s126 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_126_int8_ssa(127); got != -1 { - fmt.Printf("sub_int8 126%s127 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int8_126_ssa(127); got != 1 { - fmt.Printf("sub_int8 127%s126 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_127_int8_ssa(-128); got != -1 { - fmt.Printf("sub_int8 127%s-128 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_int8_127_ssa(-128); got != 1 { - fmt.Printf("sub_int8 -128%s127 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_127_int8_ssa(-127); got != -2 { - fmt.Printf("sub_int8 127%s-127 = %d, wanted -2\n", `-`, got) - failed = true - } - - if got := sub_int8_127_ssa(-127); got != 2 { - fmt.Printf("sub_int8 -127%s127 = %d, wanted 2\n", `-`, got) - failed = true - } - - if got := sub_127_int8_ssa(-1); got != -128 { - fmt.Printf("sub_int8 127%s-1 = %d, wanted -128\n", `-`, got) - failed = true - } - - if got := sub_int8_127_ssa(-1); got != -128 { - fmt.Printf("sub_int8 -1%s127 = %d, wanted -128\n", `-`, got) - failed = true - } - - if got := sub_127_int8_ssa(0); got != 127 { - fmt.Printf("sub_int8 127%s0 = %d, wanted 127\n", `-`, got) - failed = true - } - - if got := sub_int8_127_ssa(0); got != -127 { - fmt.Printf("sub_int8 0%s127 = %d, wanted -127\n", `-`, got) - failed = true - } - - if got := sub_127_int8_ssa(1); got != 126 { - fmt.Printf("sub_int8 127%s1 = %d, wanted 126\n", `-`, got) - failed = true - } - - if got := sub_int8_127_ssa(1); got != -126 { - fmt.Printf("sub_int8 1%s127 = %d, wanted -126\n", `-`, got) - failed = true - } - - if got := sub_127_int8_ssa(126); got != 1 { - fmt.Printf("sub_int8 127%s126 = %d, wanted 1\n", `-`, got) - failed = true - } - - if got := sub_int8_127_ssa(126); got != -1 { - fmt.Printf("sub_int8 126%s127 = %d, wanted -1\n", `-`, got) - failed = true - } - - if got := sub_127_int8_ssa(127); got != 0 { - fmt.Printf("sub_int8 127%s127 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := sub_int8_127_ssa(127); got != 0 { - fmt.Printf("sub_int8 127%s127 = %d, wanted 0\n", `-`, got) - failed = true - } - - if got := div_Neg128_int8_ssa(-128); got != 1 { - fmt.Printf("div_int8 -128%s-128 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int8_Neg128_ssa(-128); got != 1 { - fmt.Printf("div_int8 -128%s-128 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_Neg128_int8_ssa(-127); got != 1 { - fmt.Printf("div_int8 -128%s-127 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int8_Neg128_ssa(-127); got != 0 { - fmt.Printf("div_int8 -127%s-128 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg128_int8_ssa(-1); got != -128 { - fmt.Printf("div_int8 -128%s-1 = %d, wanted -128\n", `/`, got) - failed = true - } - - if got := div_int8_Neg128_ssa(-1); got != 0 { - fmt.Printf("div_int8 -1%s-128 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_Neg128_ssa(0); got != 0 { - fmt.Printf("div_int8 0%s-128 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg128_int8_ssa(1); got != -128 { - fmt.Printf("div_int8 -128%s1 = %d, wanted -128\n", `/`, got) - failed = true - } - - if got := div_int8_Neg128_ssa(1); got != 0 { - fmt.Printf("div_int8 1%s-128 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg128_int8_ssa(126); got != -1 { - fmt.Printf("div_int8 -128%s126 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int8_Neg128_ssa(126); got != 0 { - fmt.Printf("div_int8 126%s-128 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg128_int8_ssa(127); got != -1 { - fmt.Printf("div_int8 -128%s127 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int8_Neg128_ssa(127); got != 0 { - fmt.Printf("div_int8 127%s-128 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg127_int8_ssa(-128); got != 0 { - fmt.Printf("div_int8 -127%s-128 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_Neg127_ssa(-128); got != 1 { - fmt.Printf("div_int8 -128%s-127 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_Neg127_int8_ssa(-127); got != 1 { - fmt.Printf("div_int8 -127%s-127 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int8_Neg127_ssa(-127); got != 1 { - fmt.Printf("div_int8 -127%s-127 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_Neg127_int8_ssa(-1); got != 127 { - fmt.Printf("div_int8 -127%s-1 = %d, wanted 127\n", `/`, got) - failed = true - } - - if got := div_int8_Neg127_ssa(-1); got != 0 { - fmt.Printf("div_int8 -1%s-127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_Neg127_ssa(0); got != 0 { - fmt.Printf("div_int8 0%s-127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg127_int8_ssa(1); got != -127 { - fmt.Printf("div_int8 -127%s1 = %d, wanted -127\n", `/`, got) - failed = true - } - - if got := div_int8_Neg127_ssa(1); got != 0 { - fmt.Printf("div_int8 1%s-127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg127_int8_ssa(126); got != -1 { - fmt.Printf("div_int8 -127%s126 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int8_Neg127_ssa(126); got != 0 { - fmt.Printf("div_int8 126%s-127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg127_int8_ssa(127); got != -1 { - fmt.Printf("div_int8 -127%s127 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int8_Neg127_ssa(127); got != -1 { - fmt.Printf("div_int8 127%s-127 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_Neg1_int8_ssa(-128); got != 0 { - fmt.Printf("div_int8 -1%s-128 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_Neg1_ssa(-128); got != -128 { - fmt.Printf("div_int8 -128%s-1 = %d, wanted -128\n", `/`, got) - failed = true - } - - if got := div_Neg1_int8_ssa(-127); got != 0 { - fmt.Printf("div_int8 -1%s-127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_Neg1_ssa(-127); got != 127 { - fmt.Printf("div_int8 -127%s-1 = %d, wanted 127\n", `/`, got) - failed = true - } - - if got := div_Neg1_int8_ssa(-1); got != 1 { - fmt.Printf("div_int8 -1%s-1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int8_Neg1_ssa(-1); got != 1 { - fmt.Printf("div_int8 -1%s-1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int8_Neg1_ssa(0); got != 0 { - fmt.Printf("div_int8 0%s-1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_Neg1_int8_ssa(1); got != -1 { - fmt.Printf("div_int8 -1%s1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int8_Neg1_ssa(1); got != -1 { - fmt.Printf("div_int8 1%s-1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_Neg1_int8_ssa(126); got != 0 { - fmt.Printf("div_int8 -1%s126 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_Neg1_ssa(126); got != -126 { - fmt.Printf("div_int8 126%s-1 = %d, wanted -126\n", `/`, got) - failed = true - } - - if got := div_Neg1_int8_ssa(127); got != 0 { - fmt.Printf("div_int8 -1%s127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_Neg1_ssa(127); got != -127 { - fmt.Printf("div_int8 127%s-1 = %d, wanted -127\n", `/`, got) - failed = true - } - - if got := div_0_int8_ssa(-128); got != 0 { - fmt.Printf("div_int8 0%s-128 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int8_ssa(-127); got != 0 { - fmt.Printf("div_int8 0%s-127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int8_ssa(-1); got != 0 { - fmt.Printf("div_int8 0%s-1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int8_ssa(1); got != 0 { - fmt.Printf("div_int8 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int8_ssa(126); got != 0 { - fmt.Printf("div_int8 0%s126 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_0_int8_ssa(127); got != 0 { - fmt.Printf("div_int8 0%s127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_1_int8_ssa(-128); got != 0 { - fmt.Printf("div_int8 1%s-128 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_1_ssa(-128); got != -128 { - fmt.Printf("div_int8 -128%s1 = %d, wanted -128\n", `/`, got) - failed = true - } - - if got := div_1_int8_ssa(-127); got != 0 { - fmt.Printf("div_int8 1%s-127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_1_ssa(-127); got != -127 { - fmt.Printf("div_int8 -127%s1 = %d, wanted -127\n", `/`, got) - failed = true - } - - if got := div_1_int8_ssa(-1); got != -1 { - fmt.Printf("div_int8 1%s-1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int8_1_ssa(-1); got != -1 { - fmt.Printf("div_int8 -1%s1 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int8_1_ssa(0); got != 0 { - fmt.Printf("div_int8 0%s1 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_1_int8_ssa(1); got != 1 { - fmt.Printf("div_int8 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int8_1_ssa(1); got != 1 { - fmt.Printf("div_int8 1%s1 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_1_int8_ssa(126); got != 0 { - fmt.Printf("div_int8 1%s126 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_1_ssa(126); got != 126 { - fmt.Printf("div_int8 126%s1 = %d, wanted 126\n", `/`, got) - failed = true - } - - if got := div_1_int8_ssa(127); got != 0 { - fmt.Printf("div_int8 1%s127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_1_ssa(127); got != 127 { - fmt.Printf("div_int8 127%s1 = %d, wanted 127\n", `/`, got) - failed = true - } - - if got := div_126_int8_ssa(-128); got != 0 { - fmt.Printf("div_int8 126%s-128 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_126_ssa(-128); got != -1 { - fmt.Printf("div_int8 -128%s126 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_126_int8_ssa(-127); got != 0 { - fmt.Printf("div_int8 126%s-127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_126_ssa(-127); got != -1 { - fmt.Printf("div_int8 -127%s126 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_126_int8_ssa(-1); got != -126 { - fmt.Printf("div_int8 126%s-1 = %d, wanted -126\n", `/`, got) - failed = true - } - - if got := div_int8_126_ssa(-1); got != 0 { - fmt.Printf("div_int8 -1%s126 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_126_ssa(0); got != 0 { - fmt.Printf("div_int8 0%s126 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_126_int8_ssa(1); got != 126 { - fmt.Printf("div_int8 126%s1 = %d, wanted 126\n", `/`, got) - failed = true - } - - if got := div_int8_126_ssa(1); got != 0 { - fmt.Printf("div_int8 1%s126 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_126_int8_ssa(126); got != 1 { - fmt.Printf("div_int8 126%s126 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int8_126_ssa(126); got != 1 { - fmt.Printf("div_int8 126%s126 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_126_int8_ssa(127); got != 0 { - fmt.Printf("div_int8 126%s127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_126_ssa(127); got != 1 { - fmt.Printf("div_int8 127%s126 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_127_int8_ssa(-128); got != 0 { - fmt.Printf("div_int8 127%s-128 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_127_ssa(-128); got != -1 { - fmt.Printf("div_int8 -128%s127 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_127_int8_ssa(-127); got != -1 { - fmt.Printf("div_int8 127%s-127 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_int8_127_ssa(-127); got != -1 { - fmt.Printf("div_int8 -127%s127 = %d, wanted -1\n", `/`, got) - failed = true - } - - if got := div_127_int8_ssa(-1); got != -127 { - fmt.Printf("div_int8 127%s-1 = %d, wanted -127\n", `/`, got) - failed = true - } - - if got := div_int8_127_ssa(-1); got != 0 { - fmt.Printf("div_int8 -1%s127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_int8_127_ssa(0); got != 0 { - fmt.Printf("div_int8 0%s127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_127_int8_ssa(1); got != 127 { - fmt.Printf("div_int8 127%s1 = %d, wanted 127\n", `/`, got) - failed = true - } - - if got := div_int8_127_ssa(1); got != 0 { - fmt.Printf("div_int8 1%s127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_127_int8_ssa(126); got != 1 { - fmt.Printf("div_int8 127%s126 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int8_127_ssa(126); got != 0 { - fmt.Printf("div_int8 126%s127 = %d, wanted 0\n", `/`, got) - failed = true - } - - if got := div_127_int8_ssa(127); got != 1 { - fmt.Printf("div_int8 127%s127 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := div_int8_127_ssa(127); got != 1 { - fmt.Printf("div_int8 127%s127 = %d, wanted 1\n", `/`, got) - failed = true - } - - if got := mul_Neg128_int8_ssa(-128); got != 0 { - fmt.Printf("mul_int8 -128%s-128 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg128_ssa(-128); got != 0 { - fmt.Printf("mul_int8 -128%s-128 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg128_int8_ssa(-127); got != -128 { - fmt.Printf("mul_int8 -128%s-127 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg128_ssa(-127); got != -128 { - fmt.Printf("mul_int8 -127%s-128 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_Neg128_int8_ssa(-1); got != -128 { - fmt.Printf("mul_int8 -128%s-1 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg128_ssa(-1); got != -128 { - fmt.Printf("mul_int8 -1%s-128 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_Neg128_int8_ssa(0); got != 0 { - fmt.Printf("mul_int8 -128%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg128_ssa(0); got != 0 { - fmt.Printf("mul_int8 0%s-128 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg128_int8_ssa(1); got != -128 { - fmt.Printf("mul_int8 -128%s1 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg128_ssa(1); got != -128 { - fmt.Printf("mul_int8 1%s-128 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_Neg128_int8_ssa(126); got != 0 { - fmt.Printf("mul_int8 -128%s126 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg128_ssa(126); got != 0 { - fmt.Printf("mul_int8 126%s-128 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg128_int8_ssa(127); got != -128 { - fmt.Printf("mul_int8 -128%s127 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg128_ssa(127); got != -128 { - fmt.Printf("mul_int8 127%s-128 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_Neg127_int8_ssa(-128); got != -128 { - fmt.Printf("mul_int8 -127%s-128 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg127_ssa(-128); got != -128 { - fmt.Printf("mul_int8 -128%s-127 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_Neg127_int8_ssa(-127); got != 1 { - fmt.Printf("mul_int8 -127%s-127 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg127_ssa(-127); got != 1 { - fmt.Printf("mul_int8 -127%s-127 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_Neg127_int8_ssa(-1); got != 127 { - fmt.Printf("mul_int8 -127%s-1 = %d, wanted 127\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg127_ssa(-1); got != 127 { - fmt.Printf("mul_int8 -1%s-127 = %d, wanted 127\n", `*`, got) - failed = true - } - - if got := mul_Neg127_int8_ssa(0); got != 0 { - fmt.Printf("mul_int8 -127%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg127_ssa(0); got != 0 { - fmt.Printf("mul_int8 0%s-127 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg127_int8_ssa(1); got != -127 { - fmt.Printf("mul_int8 -127%s1 = %d, wanted -127\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg127_ssa(1); got != -127 { - fmt.Printf("mul_int8 1%s-127 = %d, wanted -127\n", `*`, got) - failed = true - } - - if got := mul_Neg127_int8_ssa(126); got != 126 { - fmt.Printf("mul_int8 -127%s126 = %d, wanted 126\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg127_ssa(126); got != 126 { - fmt.Printf("mul_int8 126%s-127 = %d, wanted 126\n", `*`, got) - failed = true - } - - if got := mul_Neg127_int8_ssa(127); got != -1 { - fmt.Printf("mul_int8 -127%s127 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg127_ssa(127); got != -1 { - fmt.Printf("mul_int8 127%s-127 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int8_ssa(-128); got != -128 { - fmt.Printf("mul_int8 -1%s-128 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg1_ssa(-128); got != -128 { - fmt.Printf("mul_int8 -128%s-1 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int8_ssa(-127); got != 127 { - fmt.Printf("mul_int8 -1%s-127 = %d, wanted 127\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg1_ssa(-127); got != 127 { - fmt.Printf("mul_int8 -127%s-1 = %d, wanted 127\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int8_ssa(-1); got != 1 { - fmt.Printf("mul_int8 -1%s-1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg1_ssa(-1); got != 1 { - fmt.Printf("mul_int8 -1%s-1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int8_ssa(0); got != 0 { - fmt.Printf("mul_int8 -1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg1_ssa(0); got != 0 { - fmt.Printf("mul_int8 0%s-1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int8_ssa(1); got != -1 { - fmt.Printf("mul_int8 -1%s1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg1_ssa(1); got != -1 { - fmt.Printf("mul_int8 1%s-1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int8_ssa(126); got != -126 { - fmt.Printf("mul_int8 -1%s126 = %d, wanted -126\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg1_ssa(126); got != -126 { - fmt.Printf("mul_int8 126%s-1 = %d, wanted -126\n", `*`, got) - failed = true - } - - if got := mul_Neg1_int8_ssa(127); got != -127 { - fmt.Printf("mul_int8 -1%s127 = %d, wanted -127\n", `*`, got) - failed = true - } - - if got := mul_int8_Neg1_ssa(127); got != -127 { - fmt.Printf("mul_int8 127%s-1 = %d, wanted -127\n", `*`, got) - failed = true - } - - if got := mul_0_int8_ssa(-128); got != 0 { - fmt.Printf("mul_int8 0%s-128 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_0_ssa(-128); got != 0 { - fmt.Printf("mul_int8 -128%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int8_ssa(-127); got != 0 { - fmt.Printf("mul_int8 0%s-127 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_0_ssa(-127); got != 0 { - fmt.Printf("mul_int8 -127%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int8_ssa(-1); got != 0 { - fmt.Printf("mul_int8 0%s-1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_0_ssa(-1); got != 0 { - fmt.Printf("mul_int8 -1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int8_ssa(0); got != 0 { - fmt.Printf("mul_int8 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_0_ssa(0); got != 0 { - fmt.Printf("mul_int8 0%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int8_ssa(1); got != 0 { - fmt.Printf("mul_int8 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_0_ssa(1); got != 0 { - fmt.Printf("mul_int8 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int8_ssa(126); got != 0 { - fmt.Printf("mul_int8 0%s126 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_0_ssa(126); got != 0 { - fmt.Printf("mul_int8 126%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_0_int8_ssa(127); got != 0 { - fmt.Printf("mul_int8 0%s127 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_0_ssa(127); got != 0 { - fmt.Printf("mul_int8 127%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_int8_ssa(-128); got != -128 { - fmt.Printf("mul_int8 1%s-128 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_int8_1_ssa(-128); got != -128 { - fmt.Printf("mul_int8 -128%s1 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_1_int8_ssa(-127); got != -127 { - fmt.Printf("mul_int8 1%s-127 = %d, wanted -127\n", `*`, got) - failed = true - } - - if got := mul_int8_1_ssa(-127); got != -127 { - fmt.Printf("mul_int8 -127%s1 = %d, wanted -127\n", `*`, got) - failed = true - } - - if got := mul_1_int8_ssa(-1); got != -1 { - fmt.Printf("mul_int8 1%s-1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int8_1_ssa(-1); got != -1 { - fmt.Printf("mul_int8 -1%s1 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_1_int8_ssa(0); got != 0 { - fmt.Printf("mul_int8 1%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_1_ssa(0); got != 0 { - fmt.Printf("mul_int8 0%s1 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_1_int8_ssa(1); got != 1 { - fmt.Printf("mul_int8 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int8_1_ssa(1); got != 1 { - fmt.Printf("mul_int8 1%s1 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_1_int8_ssa(126); got != 126 { - fmt.Printf("mul_int8 1%s126 = %d, wanted 126\n", `*`, got) - failed = true - } - - if got := mul_int8_1_ssa(126); got != 126 { - fmt.Printf("mul_int8 126%s1 = %d, wanted 126\n", `*`, got) - failed = true - } - - if got := mul_1_int8_ssa(127); got != 127 { - fmt.Printf("mul_int8 1%s127 = %d, wanted 127\n", `*`, got) - failed = true - } - - if got := mul_int8_1_ssa(127); got != 127 { - fmt.Printf("mul_int8 127%s1 = %d, wanted 127\n", `*`, got) - failed = true - } - - if got := mul_126_int8_ssa(-128); got != 0 { - fmt.Printf("mul_int8 126%s-128 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_126_ssa(-128); got != 0 { - fmt.Printf("mul_int8 -128%s126 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_126_int8_ssa(-127); got != 126 { - fmt.Printf("mul_int8 126%s-127 = %d, wanted 126\n", `*`, got) - failed = true - } - - if got := mul_int8_126_ssa(-127); got != 126 { - fmt.Printf("mul_int8 -127%s126 = %d, wanted 126\n", `*`, got) - failed = true - } - - if got := mul_126_int8_ssa(-1); got != -126 { - fmt.Printf("mul_int8 126%s-1 = %d, wanted -126\n", `*`, got) - failed = true - } - - if got := mul_int8_126_ssa(-1); got != -126 { - fmt.Printf("mul_int8 -1%s126 = %d, wanted -126\n", `*`, got) - failed = true - } - - if got := mul_126_int8_ssa(0); got != 0 { - fmt.Printf("mul_int8 126%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_126_ssa(0); got != 0 { - fmt.Printf("mul_int8 0%s126 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_126_int8_ssa(1); got != 126 { - fmt.Printf("mul_int8 126%s1 = %d, wanted 126\n", `*`, got) - failed = true - } - - if got := mul_int8_126_ssa(1); got != 126 { - fmt.Printf("mul_int8 1%s126 = %d, wanted 126\n", `*`, got) - failed = true - } - - if got := mul_126_int8_ssa(126); got != 4 { - fmt.Printf("mul_int8 126%s126 = %d, wanted 4\n", `*`, got) - failed = true - } - - if got := mul_int8_126_ssa(126); got != 4 { - fmt.Printf("mul_int8 126%s126 = %d, wanted 4\n", `*`, got) - failed = true - } - - if got := mul_126_int8_ssa(127); got != -126 { - fmt.Printf("mul_int8 126%s127 = %d, wanted -126\n", `*`, got) - failed = true - } - - if got := mul_int8_126_ssa(127); got != -126 { - fmt.Printf("mul_int8 127%s126 = %d, wanted -126\n", `*`, got) - failed = true - } - - if got := mul_127_int8_ssa(-128); got != -128 { - fmt.Printf("mul_int8 127%s-128 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_int8_127_ssa(-128); got != -128 { - fmt.Printf("mul_int8 -128%s127 = %d, wanted -128\n", `*`, got) - failed = true - } - - if got := mul_127_int8_ssa(-127); got != -1 { - fmt.Printf("mul_int8 127%s-127 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_int8_127_ssa(-127); got != -1 { - fmt.Printf("mul_int8 -127%s127 = %d, wanted -1\n", `*`, got) - failed = true - } - - if got := mul_127_int8_ssa(-1); got != -127 { - fmt.Printf("mul_int8 127%s-1 = %d, wanted -127\n", `*`, got) - failed = true - } - - if got := mul_int8_127_ssa(-1); got != -127 { - fmt.Printf("mul_int8 -1%s127 = %d, wanted -127\n", `*`, got) - failed = true - } - - if got := mul_127_int8_ssa(0); got != 0 { - fmt.Printf("mul_int8 127%s0 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_int8_127_ssa(0); got != 0 { - fmt.Printf("mul_int8 0%s127 = %d, wanted 0\n", `*`, got) - failed = true - } - - if got := mul_127_int8_ssa(1); got != 127 { - fmt.Printf("mul_int8 127%s1 = %d, wanted 127\n", `*`, got) - failed = true - } - - if got := mul_int8_127_ssa(1); got != 127 { - fmt.Printf("mul_int8 1%s127 = %d, wanted 127\n", `*`, got) - failed = true - } - - if got := mul_127_int8_ssa(126); got != -126 { - fmt.Printf("mul_int8 127%s126 = %d, wanted -126\n", `*`, got) - failed = true - } - - if got := mul_int8_127_ssa(126); got != -126 { - fmt.Printf("mul_int8 126%s127 = %d, wanted -126\n", `*`, got) - failed = true - } - - if got := mul_127_int8_ssa(127); got != 1 { - fmt.Printf("mul_int8 127%s127 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mul_int8_127_ssa(127); got != 1 { - fmt.Printf("mul_int8 127%s127 = %d, wanted 1\n", `*`, got) - failed = true - } - - if got := mod_Neg128_int8_ssa(-128); got != 0 { - fmt.Printf("mod_int8 -128%s-128 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg128_ssa(-128); got != 0 { - fmt.Printf("mod_int8 -128%s-128 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg128_int8_ssa(-127); got != -1 { - fmt.Printf("mod_int8 -128%s-127 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg128_ssa(-127); got != -127 { - fmt.Printf("mod_int8 -127%s-128 = %d, wanted -127\n", `%`, got) - failed = true - } - - if got := mod_Neg128_int8_ssa(-1); got != 0 { - fmt.Printf("mod_int8 -128%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg128_ssa(-1); got != -1 { - fmt.Printf("mod_int8 -1%s-128 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg128_ssa(0); got != 0 { - fmt.Printf("mod_int8 0%s-128 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg128_int8_ssa(1); got != 0 { - fmt.Printf("mod_int8 -128%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg128_ssa(1); got != 1 { - fmt.Printf("mod_int8 1%s-128 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_Neg128_int8_ssa(126); got != -2 { - fmt.Printf("mod_int8 -128%s126 = %d, wanted -2\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg128_ssa(126); got != 126 { - fmt.Printf("mod_int8 126%s-128 = %d, wanted 126\n", `%`, got) - failed = true - } - - if got := mod_Neg128_int8_ssa(127); got != -1 { - fmt.Printf("mod_int8 -128%s127 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg128_ssa(127); got != 127 { - fmt.Printf("mod_int8 127%s-128 = %d, wanted 127\n", `%`, got) - failed = true - } - - if got := mod_Neg127_int8_ssa(-128); got != -127 { - fmt.Printf("mod_int8 -127%s-128 = %d, wanted -127\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg127_ssa(-128); got != -1 { - fmt.Printf("mod_int8 -128%s-127 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_Neg127_int8_ssa(-127); got != 0 { - fmt.Printf("mod_int8 -127%s-127 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg127_ssa(-127); got != 0 { - fmt.Printf("mod_int8 -127%s-127 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg127_int8_ssa(-1); got != 0 { - fmt.Printf("mod_int8 -127%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg127_ssa(-1); got != -1 { - fmt.Printf("mod_int8 -1%s-127 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg127_ssa(0); got != 0 { - fmt.Printf("mod_int8 0%s-127 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg127_int8_ssa(1); got != 0 { - fmt.Printf("mod_int8 -127%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg127_ssa(1); got != 1 { - fmt.Printf("mod_int8 1%s-127 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_Neg127_int8_ssa(126); got != -1 { - fmt.Printf("mod_int8 -127%s126 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg127_ssa(126); got != 126 { - fmt.Printf("mod_int8 126%s-127 = %d, wanted 126\n", `%`, got) - failed = true - } - - if got := mod_Neg127_int8_ssa(127); got != 0 { - fmt.Printf("mod_int8 -127%s127 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg127_ssa(127); got != 0 { - fmt.Printf("mod_int8 127%s-127 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int8_ssa(-128); got != -1 { - fmt.Printf("mod_int8 -1%s-128 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg1_ssa(-128); got != 0 { - fmt.Printf("mod_int8 -128%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int8_ssa(-127); got != -1 { - fmt.Printf("mod_int8 -1%s-127 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg1_ssa(-127); got != 0 { - fmt.Printf("mod_int8 -127%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int8_ssa(-1); got != 0 { - fmt.Printf("mod_int8 -1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg1_ssa(-1); got != 0 { - fmt.Printf("mod_int8 -1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg1_ssa(0); got != 0 { - fmt.Printf("mod_int8 0%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int8_ssa(1); got != 0 { - fmt.Printf("mod_int8 -1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg1_ssa(1); got != 0 { - fmt.Printf("mod_int8 1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int8_ssa(126); got != -1 { - fmt.Printf("mod_int8 -1%s126 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg1_ssa(126); got != 0 { - fmt.Printf("mod_int8 126%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_Neg1_int8_ssa(127); got != -1 { - fmt.Printf("mod_int8 -1%s127 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int8_Neg1_ssa(127); got != 0 { - fmt.Printf("mod_int8 127%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int8_ssa(-128); got != 0 { - fmt.Printf("mod_int8 0%s-128 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int8_ssa(-127); got != 0 { - fmt.Printf("mod_int8 0%s-127 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int8_ssa(-1); got != 0 { - fmt.Printf("mod_int8 0%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int8_ssa(1); got != 0 { - fmt.Printf("mod_int8 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int8_ssa(126); got != 0 { - fmt.Printf("mod_int8 0%s126 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_0_int8_ssa(127); got != 0 { - fmt.Printf("mod_int8 0%s127 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int8_ssa(-128); got != 1 { - fmt.Printf("mod_int8 1%s-128 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int8_1_ssa(-128); got != 0 { - fmt.Printf("mod_int8 -128%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int8_ssa(-127); got != 1 { - fmt.Printf("mod_int8 1%s-127 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int8_1_ssa(-127); got != 0 { - fmt.Printf("mod_int8 -127%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int8_ssa(-1); got != 0 { - fmt.Printf("mod_int8 1%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_1_ssa(-1); got != 0 { - fmt.Printf("mod_int8 -1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_1_ssa(0); got != 0 { - fmt.Printf("mod_int8 0%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int8_ssa(1); got != 0 { - fmt.Printf("mod_int8 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_1_ssa(1); got != 0 { - fmt.Printf("mod_int8 1%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int8_ssa(126); got != 1 { - fmt.Printf("mod_int8 1%s126 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int8_1_ssa(126); got != 0 { - fmt.Printf("mod_int8 126%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_1_int8_ssa(127); got != 1 { - fmt.Printf("mod_int8 1%s127 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int8_1_ssa(127); got != 0 { - fmt.Printf("mod_int8 127%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_126_int8_ssa(-128); got != 126 { - fmt.Printf("mod_int8 126%s-128 = %d, wanted 126\n", `%`, got) - failed = true - } - - if got := mod_int8_126_ssa(-128); got != -2 { - fmt.Printf("mod_int8 -128%s126 = %d, wanted -2\n", `%`, got) - failed = true - } - - if got := mod_126_int8_ssa(-127); got != 126 { - fmt.Printf("mod_int8 126%s-127 = %d, wanted 126\n", `%`, got) - failed = true - } - - if got := mod_int8_126_ssa(-127); got != -1 { - fmt.Printf("mod_int8 -127%s126 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_126_int8_ssa(-1); got != 0 { - fmt.Printf("mod_int8 126%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_126_ssa(-1); got != -1 { - fmt.Printf("mod_int8 -1%s126 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int8_126_ssa(0); got != 0 { - fmt.Printf("mod_int8 0%s126 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_126_int8_ssa(1); got != 0 { - fmt.Printf("mod_int8 126%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_126_ssa(1); got != 1 { - fmt.Printf("mod_int8 1%s126 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_126_int8_ssa(126); got != 0 { - fmt.Printf("mod_int8 126%s126 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_126_ssa(126); got != 0 { - fmt.Printf("mod_int8 126%s126 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_126_int8_ssa(127); got != 126 { - fmt.Printf("mod_int8 126%s127 = %d, wanted 126\n", `%`, got) - failed = true - } - - if got := mod_int8_126_ssa(127); got != 1 { - fmt.Printf("mod_int8 127%s126 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_127_int8_ssa(-128); got != 127 { - fmt.Printf("mod_int8 127%s-128 = %d, wanted 127\n", `%`, got) - failed = true - } - - if got := mod_int8_127_ssa(-128); got != -1 { - fmt.Printf("mod_int8 -128%s127 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_127_int8_ssa(-127); got != 0 { - fmt.Printf("mod_int8 127%s-127 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_127_ssa(-127); got != 0 { - fmt.Printf("mod_int8 -127%s127 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_127_int8_ssa(-1); got != 0 { - fmt.Printf("mod_int8 127%s-1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_127_ssa(-1); got != -1 { - fmt.Printf("mod_int8 -1%s127 = %d, wanted -1\n", `%`, got) - failed = true - } - - if got := mod_int8_127_ssa(0); got != 0 { - fmt.Printf("mod_int8 0%s127 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_127_int8_ssa(1); got != 0 { - fmt.Printf("mod_int8 127%s1 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_127_ssa(1); got != 1 { - fmt.Printf("mod_int8 1%s127 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_127_int8_ssa(126); got != 1 { - fmt.Printf("mod_int8 127%s126 = %d, wanted 1\n", `%`, got) - failed = true - } - - if got := mod_int8_127_ssa(126); got != 126 { - fmt.Printf("mod_int8 126%s127 = %d, wanted 126\n", `%`, got) - failed = true - } - - if got := mod_127_int8_ssa(127); got != 0 { - fmt.Printf("mod_int8 127%s127 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := mod_int8_127_ssa(127); got != 0 { - fmt.Printf("mod_int8 127%s127 = %d, wanted 0\n", `%`, got) - failed = true - } - - if got := and_Neg128_int8_ssa(-128); got != -128 { - fmt.Printf("and_int8 -128%s-128 = %d, wanted -128\n", `&`, got) - failed = true - } - - if got := and_int8_Neg128_ssa(-128); got != -128 { - fmt.Printf("and_int8 -128%s-128 = %d, wanted -128\n", `&`, got) - failed = true - } - - if got := and_Neg128_int8_ssa(-127); got != -128 { - fmt.Printf("and_int8 -128%s-127 = %d, wanted -128\n", `&`, got) - failed = true - } - - if got := and_int8_Neg128_ssa(-127); got != -128 { - fmt.Printf("and_int8 -127%s-128 = %d, wanted -128\n", `&`, got) - failed = true - } - - if got := and_Neg128_int8_ssa(-1); got != -128 { - fmt.Printf("and_int8 -128%s-1 = %d, wanted -128\n", `&`, got) - failed = true - } - - if got := and_int8_Neg128_ssa(-1); got != -128 { - fmt.Printf("and_int8 -1%s-128 = %d, wanted -128\n", `&`, got) - failed = true - } - - if got := and_Neg128_int8_ssa(0); got != 0 { - fmt.Printf("and_int8 -128%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_Neg128_ssa(0); got != 0 { - fmt.Printf("and_int8 0%s-128 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg128_int8_ssa(1); got != 0 { - fmt.Printf("and_int8 -128%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_Neg128_ssa(1); got != 0 { - fmt.Printf("and_int8 1%s-128 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg128_int8_ssa(126); got != 0 { - fmt.Printf("and_int8 -128%s126 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_Neg128_ssa(126); got != 0 { - fmt.Printf("and_int8 126%s-128 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg128_int8_ssa(127); got != 0 { - fmt.Printf("and_int8 -128%s127 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_Neg128_ssa(127); got != 0 { - fmt.Printf("and_int8 127%s-128 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg127_int8_ssa(-128); got != -128 { - fmt.Printf("and_int8 -127%s-128 = %d, wanted -128\n", `&`, got) - failed = true - } - - if got := and_int8_Neg127_ssa(-128); got != -128 { - fmt.Printf("and_int8 -128%s-127 = %d, wanted -128\n", `&`, got) - failed = true - } - - if got := and_Neg127_int8_ssa(-127); got != -127 { - fmt.Printf("and_int8 -127%s-127 = %d, wanted -127\n", `&`, got) - failed = true - } - - if got := and_int8_Neg127_ssa(-127); got != -127 { - fmt.Printf("and_int8 -127%s-127 = %d, wanted -127\n", `&`, got) - failed = true - } - - if got := and_Neg127_int8_ssa(-1); got != -127 { - fmt.Printf("and_int8 -127%s-1 = %d, wanted -127\n", `&`, got) - failed = true - } - - if got := and_int8_Neg127_ssa(-1); got != -127 { - fmt.Printf("and_int8 -1%s-127 = %d, wanted -127\n", `&`, got) - failed = true - } - - if got := and_Neg127_int8_ssa(0); got != 0 { - fmt.Printf("and_int8 -127%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_Neg127_ssa(0); got != 0 { - fmt.Printf("and_int8 0%s-127 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg127_int8_ssa(1); got != 1 { - fmt.Printf("and_int8 -127%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int8_Neg127_ssa(1); got != 1 { - fmt.Printf("and_int8 1%s-127 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_Neg127_int8_ssa(126); got != 0 { - fmt.Printf("and_int8 -127%s126 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_Neg127_ssa(126); got != 0 { - fmt.Printf("and_int8 126%s-127 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg127_int8_ssa(127); got != 1 { - fmt.Printf("and_int8 -127%s127 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int8_Neg127_ssa(127); got != 1 { - fmt.Printf("and_int8 127%s-127 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_Neg1_int8_ssa(-128); got != -128 { - fmt.Printf("and_int8 -1%s-128 = %d, wanted -128\n", `&`, got) - failed = true - } - - if got := and_int8_Neg1_ssa(-128); got != -128 { - fmt.Printf("and_int8 -128%s-1 = %d, wanted -128\n", `&`, got) - failed = true - } - - if got := and_Neg1_int8_ssa(-127); got != -127 { - fmt.Printf("and_int8 -1%s-127 = %d, wanted -127\n", `&`, got) - failed = true - } - - if got := and_int8_Neg1_ssa(-127); got != -127 { - fmt.Printf("and_int8 -127%s-1 = %d, wanted -127\n", `&`, got) - failed = true - } - - if got := and_Neg1_int8_ssa(-1); got != -1 { - fmt.Printf("and_int8 -1%s-1 = %d, wanted -1\n", `&`, got) - failed = true - } - - if got := and_int8_Neg1_ssa(-1); got != -1 { - fmt.Printf("and_int8 -1%s-1 = %d, wanted -1\n", `&`, got) - failed = true - } - - if got := and_Neg1_int8_ssa(0); got != 0 { - fmt.Printf("and_int8 -1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_Neg1_ssa(0); got != 0 { - fmt.Printf("and_int8 0%s-1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_Neg1_int8_ssa(1); got != 1 { - fmt.Printf("and_int8 -1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int8_Neg1_ssa(1); got != 1 { - fmt.Printf("and_int8 1%s-1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_Neg1_int8_ssa(126); got != 126 { - fmt.Printf("and_int8 -1%s126 = %d, wanted 126\n", `&`, got) - failed = true - } - - if got := and_int8_Neg1_ssa(126); got != 126 { - fmt.Printf("and_int8 126%s-1 = %d, wanted 126\n", `&`, got) - failed = true - } - - if got := and_Neg1_int8_ssa(127); got != 127 { - fmt.Printf("and_int8 -1%s127 = %d, wanted 127\n", `&`, got) - failed = true - } - - if got := and_int8_Neg1_ssa(127); got != 127 { - fmt.Printf("and_int8 127%s-1 = %d, wanted 127\n", `&`, got) - failed = true - } - - if got := and_0_int8_ssa(-128); got != 0 { - fmt.Printf("and_int8 0%s-128 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_0_ssa(-128); got != 0 { - fmt.Printf("and_int8 -128%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int8_ssa(-127); got != 0 { - fmt.Printf("and_int8 0%s-127 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_0_ssa(-127); got != 0 { - fmt.Printf("and_int8 -127%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int8_ssa(-1); got != 0 { - fmt.Printf("and_int8 0%s-1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_0_ssa(-1); got != 0 { - fmt.Printf("and_int8 -1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int8_ssa(0); got != 0 { - fmt.Printf("and_int8 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_0_ssa(0); got != 0 { - fmt.Printf("and_int8 0%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int8_ssa(1); got != 0 { - fmt.Printf("and_int8 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_0_ssa(1); got != 0 { - fmt.Printf("and_int8 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int8_ssa(126); got != 0 { - fmt.Printf("and_int8 0%s126 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_0_ssa(126); got != 0 { - fmt.Printf("and_int8 126%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_0_int8_ssa(127); got != 0 { - fmt.Printf("and_int8 0%s127 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_0_ssa(127); got != 0 { - fmt.Printf("and_int8 127%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int8_ssa(-128); got != 0 { - fmt.Printf("and_int8 1%s-128 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_1_ssa(-128); got != 0 { - fmt.Printf("and_int8 -128%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int8_ssa(-127); got != 1 { - fmt.Printf("and_int8 1%s-127 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int8_1_ssa(-127); got != 1 { - fmt.Printf("and_int8 -127%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_int8_ssa(-1); got != 1 { - fmt.Printf("and_int8 1%s-1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int8_1_ssa(-1); got != 1 { - fmt.Printf("and_int8 -1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_int8_ssa(0); got != 0 { - fmt.Printf("and_int8 1%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_1_ssa(0); got != 0 { - fmt.Printf("and_int8 0%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int8_ssa(1); got != 1 { - fmt.Printf("and_int8 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int8_1_ssa(1); got != 1 { - fmt.Printf("and_int8 1%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_1_int8_ssa(126); got != 0 { - fmt.Printf("and_int8 1%s126 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_1_ssa(126); got != 0 { - fmt.Printf("and_int8 126%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_1_int8_ssa(127); got != 1 { - fmt.Printf("and_int8 1%s127 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int8_1_ssa(127); got != 1 { - fmt.Printf("and_int8 127%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_126_int8_ssa(-128); got != 0 { - fmt.Printf("and_int8 126%s-128 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_126_ssa(-128); got != 0 { - fmt.Printf("and_int8 -128%s126 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_126_int8_ssa(-127); got != 0 { - fmt.Printf("and_int8 126%s-127 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_126_ssa(-127); got != 0 { - fmt.Printf("and_int8 -127%s126 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_126_int8_ssa(-1); got != 126 { - fmt.Printf("and_int8 126%s-1 = %d, wanted 126\n", `&`, got) - failed = true - } - - if got := and_int8_126_ssa(-1); got != 126 { - fmt.Printf("and_int8 -1%s126 = %d, wanted 126\n", `&`, got) - failed = true - } - - if got := and_126_int8_ssa(0); got != 0 { - fmt.Printf("and_int8 126%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_126_ssa(0); got != 0 { - fmt.Printf("and_int8 0%s126 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_126_int8_ssa(1); got != 0 { - fmt.Printf("and_int8 126%s1 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_126_ssa(1); got != 0 { - fmt.Printf("and_int8 1%s126 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_126_int8_ssa(126); got != 126 { - fmt.Printf("and_int8 126%s126 = %d, wanted 126\n", `&`, got) - failed = true - } - - if got := and_int8_126_ssa(126); got != 126 { - fmt.Printf("and_int8 126%s126 = %d, wanted 126\n", `&`, got) - failed = true - } - - if got := and_126_int8_ssa(127); got != 126 { - fmt.Printf("and_int8 126%s127 = %d, wanted 126\n", `&`, got) - failed = true - } - - if got := and_int8_126_ssa(127); got != 126 { - fmt.Printf("and_int8 127%s126 = %d, wanted 126\n", `&`, got) - failed = true - } - - if got := and_127_int8_ssa(-128); got != 0 { - fmt.Printf("and_int8 127%s-128 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_127_ssa(-128); got != 0 { - fmt.Printf("and_int8 -128%s127 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_127_int8_ssa(-127); got != 1 { - fmt.Printf("and_int8 127%s-127 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int8_127_ssa(-127); got != 1 { - fmt.Printf("and_int8 -127%s127 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_127_int8_ssa(-1); got != 127 { - fmt.Printf("and_int8 127%s-1 = %d, wanted 127\n", `&`, got) - failed = true - } - - if got := and_int8_127_ssa(-1); got != 127 { - fmt.Printf("and_int8 -1%s127 = %d, wanted 127\n", `&`, got) - failed = true - } - - if got := and_127_int8_ssa(0); got != 0 { - fmt.Printf("and_int8 127%s0 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_int8_127_ssa(0); got != 0 { - fmt.Printf("and_int8 0%s127 = %d, wanted 0\n", `&`, got) - failed = true - } - - if got := and_127_int8_ssa(1); got != 1 { - fmt.Printf("and_int8 127%s1 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_int8_127_ssa(1); got != 1 { - fmt.Printf("and_int8 1%s127 = %d, wanted 1\n", `&`, got) - failed = true - } - - if got := and_127_int8_ssa(126); got != 126 { - fmt.Printf("and_int8 127%s126 = %d, wanted 126\n", `&`, got) - failed = true - } - - if got := and_int8_127_ssa(126); got != 126 { - fmt.Printf("and_int8 126%s127 = %d, wanted 126\n", `&`, got) - failed = true - } - - if got := and_127_int8_ssa(127); got != 127 { - fmt.Printf("and_int8 127%s127 = %d, wanted 127\n", `&`, got) - failed = true - } - - if got := and_int8_127_ssa(127); got != 127 { - fmt.Printf("and_int8 127%s127 = %d, wanted 127\n", `&`, got) - failed = true - } - - if got := or_Neg128_int8_ssa(-128); got != -128 { - fmt.Printf("or_int8 -128%s-128 = %d, wanted -128\n", `|`, got) - failed = true - } - - if got := or_int8_Neg128_ssa(-128); got != -128 { - fmt.Printf("or_int8 -128%s-128 = %d, wanted -128\n", `|`, got) - failed = true - } - - if got := or_Neg128_int8_ssa(-127); got != -127 { - fmt.Printf("or_int8 -128%s-127 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_int8_Neg128_ssa(-127); got != -127 { - fmt.Printf("or_int8 -127%s-128 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_Neg128_int8_ssa(-1); got != -1 { - fmt.Printf("or_int8 -128%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_Neg128_ssa(-1); got != -1 { - fmt.Printf("or_int8 -1%s-128 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg128_int8_ssa(0); got != -128 { - fmt.Printf("or_int8 -128%s0 = %d, wanted -128\n", `|`, got) - failed = true - } - - if got := or_int8_Neg128_ssa(0); got != -128 { - fmt.Printf("or_int8 0%s-128 = %d, wanted -128\n", `|`, got) - failed = true - } - - if got := or_Neg128_int8_ssa(1); got != -127 { - fmt.Printf("or_int8 -128%s1 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_int8_Neg128_ssa(1); got != -127 { - fmt.Printf("or_int8 1%s-128 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_Neg128_int8_ssa(126); got != -2 { - fmt.Printf("or_int8 -128%s126 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_int8_Neg128_ssa(126); got != -2 { - fmt.Printf("or_int8 126%s-128 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_Neg128_int8_ssa(127); got != -1 { - fmt.Printf("or_int8 -128%s127 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_Neg128_ssa(127); got != -1 { - fmt.Printf("or_int8 127%s-128 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg127_int8_ssa(-128); got != -127 { - fmt.Printf("or_int8 -127%s-128 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_int8_Neg127_ssa(-128); got != -127 { - fmt.Printf("or_int8 -128%s-127 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_Neg127_int8_ssa(-127); got != -127 { - fmt.Printf("or_int8 -127%s-127 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_int8_Neg127_ssa(-127); got != -127 { - fmt.Printf("or_int8 -127%s-127 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_Neg127_int8_ssa(-1); got != -1 { - fmt.Printf("or_int8 -127%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_Neg127_ssa(-1); got != -1 { - fmt.Printf("or_int8 -1%s-127 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg127_int8_ssa(0); got != -127 { - fmt.Printf("or_int8 -127%s0 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_int8_Neg127_ssa(0); got != -127 { - fmt.Printf("or_int8 0%s-127 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_Neg127_int8_ssa(1); got != -127 { - fmt.Printf("or_int8 -127%s1 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_int8_Neg127_ssa(1); got != -127 { - fmt.Printf("or_int8 1%s-127 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_Neg127_int8_ssa(126); got != -1 { - fmt.Printf("or_int8 -127%s126 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_Neg127_ssa(126); got != -1 { - fmt.Printf("or_int8 126%s-127 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg127_int8_ssa(127); got != -1 { - fmt.Printf("or_int8 -127%s127 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_Neg127_ssa(127); got != -1 { - fmt.Printf("or_int8 127%s-127 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int8_ssa(-128); got != -1 { - fmt.Printf("or_int8 -1%s-128 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_Neg1_ssa(-128); got != -1 { - fmt.Printf("or_int8 -128%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int8_ssa(-127); got != -1 { - fmt.Printf("or_int8 -1%s-127 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_Neg1_ssa(-127); got != -1 { - fmt.Printf("or_int8 -127%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int8_ssa(-1); got != -1 { - fmt.Printf("or_int8 -1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_Neg1_ssa(-1); got != -1 { - fmt.Printf("or_int8 -1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int8_ssa(0); got != -1 { - fmt.Printf("or_int8 -1%s0 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_Neg1_ssa(0); got != -1 { - fmt.Printf("or_int8 0%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int8_ssa(1); got != -1 { - fmt.Printf("or_int8 -1%s1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_Neg1_ssa(1); got != -1 { - fmt.Printf("or_int8 1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int8_ssa(126); got != -1 { - fmt.Printf("or_int8 -1%s126 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_Neg1_ssa(126); got != -1 { - fmt.Printf("or_int8 126%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_Neg1_int8_ssa(127); got != -1 { - fmt.Printf("or_int8 -1%s127 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_Neg1_ssa(127); got != -1 { - fmt.Printf("or_int8 127%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_0_int8_ssa(-128); got != -128 { - fmt.Printf("or_int8 0%s-128 = %d, wanted -128\n", `|`, got) - failed = true - } - - if got := or_int8_0_ssa(-128); got != -128 { - fmt.Printf("or_int8 -128%s0 = %d, wanted -128\n", `|`, got) - failed = true - } - - if got := or_0_int8_ssa(-127); got != -127 { - fmt.Printf("or_int8 0%s-127 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_int8_0_ssa(-127); got != -127 { - fmt.Printf("or_int8 -127%s0 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_0_int8_ssa(-1); got != -1 { - fmt.Printf("or_int8 0%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_0_ssa(-1); got != -1 { - fmt.Printf("or_int8 -1%s0 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_0_int8_ssa(0); got != 0 { - fmt.Printf("or_int8 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_int8_0_ssa(0); got != 0 { - fmt.Printf("or_int8 0%s0 = %d, wanted 0\n", `|`, got) - failed = true - } - - if got := or_0_int8_ssa(1); got != 1 { - fmt.Printf("or_int8 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_int8_0_ssa(1); got != 1 { - fmt.Printf("or_int8 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_0_int8_ssa(126); got != 126 { - fmt.Printf("or_int8 0%s126 = %d, wanted 126\n", `|`, got) - failed = true - } - - if got := or_int8_0_ssa(126); got != 126 { - fmt.Printf("or_int8 126%s0 = %d, wanted 126\n", `|`, got) - failed = true - } - - if got := or_0_int8_ssa(127); got != 127 { - fmt.Printf("or_int8 0%s127 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_int8_0_ssa(127); got != 127 { - fmt.Printf("or_int8 127%s0 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_1_int8_ssa(-128); got != -127 { - fmt.Printf("or_int8 1%s-128 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_int8_1_ssa(-128); got != -127 { - fmt.Printf("or_int8 -128%s1 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_1_int8_ssa(-127); got != -127 { - fmt.Printf("or_int8 1%s-127 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_int8_1_ssa(-127); got != -127 { - fmt.Printf("or_int8 -127%s1 = %d, wanted -127\n", `|`, got) - failed = true - } - - if got := or_1_int8_ssa(-1); got != -1 { - fmt.Printf("or_int8 1%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_1_ssa(-1); got != -1 { - fmt.Printf("or_int8 -1%s1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_1_int8_ssa(0); got != 1 { - fmt.Printf("or_int8 1%s0 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_int8_1_ssa(0); got != 1 { - fmt.Printf("or_int8 0%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_int8_ssa(1); got != 1 { - fmt.Printf("or_int8 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_int8_1_ssa(1); got != 1 { - fmt.Printf("or_int8 1%s1 = %d, wanted 1\n", `|`, got) - failed = true - } - - if got := or_1_int8_ssa(126); got != 127 { - fmt.Printf("or_int8 1%s126 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_int8_1_ssa(126); got != 127 { - fmt.Printf("or_int8 126%s1 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_1_int8_ssa(127); got != 127 { - fmt.Printf("or_int8 1%s127 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_int8_1_ssa(127); got != 127 { - fmt.Printf("or_int8 127%s1 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_126_int8_ssa(-128); got != -2 { - fmt.Printf("or_int8 126%s-128 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_int8_126_ssa(-128); got != -2 { - fmt.Printf("or_int8 -128%s126 = %d, wanted -2\n", `|`, got) - failed = true - } - - if got := or_126_int8_ssa(-127); got != -1 { - fmt.Printf("or_int8 126%s-127 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_126_ssa(-127); got != -1 { - fmt.Printf("or_int8 -127%s126 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_126_int8_ssa(-1); got != -1 { - fmt.Printf("or_int8 126%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_126_ssa(-1); got != -1 { - fmt.Printf("or_int8 -1%s126 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_126_int8_ssa(0); got != 126 { - fmt.Printf("or_int8 126%s0 = %d, wanted 126\n", `|`, got) - failed = true - } - - if got := or_int8_126_ssa(0); got != 126 { - fmt.Printf("or_int8 0%s126 = %d, wanted 126\n", `|`, got) - failed = true - } - - if got := or_126_int8_ssa(1); got != 127 { - fmt.Printf("or_int8 126%s1 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_int8_126_ssa(1); got != 127 { - fmt.Printf("or_int8 1%s126 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_126_int8_ssa(126); got != 126 { - fmt.Printf("or_int8 126%s126 = %d, wanted 126\n", `|`, got) - failed = true - } - - if got := or_int8_126_ssa(126); got != 126 { - fmt.Printf("or_int8 126%s126 = %d, wanted 126\n", `|`, got) - failed = true - } - - if got := or_126_int8_ssa(127); got != 127 { - fmt.Printf("or_int8 126%s127 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_int8_126_ssa(127); got != 127 { - fmt.Printf("or_int8 127%s126 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_127_int8_ssa(-128); got != -1 { - fmt.Printf("or_int8 127%s-128 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_127_ssa(-128); got != -1 { - fmt.Printf("or_int8 -128%s127 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_127_int8_ssa(-127); got != -1 { - fmt.Printf("or_int8 127%s-127 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_127_ssa(-127); got != -1 { - fmt.Printf("or_int8 -127%s127 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_127_int8_ssa(-1); got != -1 { - fmt.Printf("or_int8 127%s-1 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_int8_127_ssa(-1); got != -1 { - fmt.Printf("or_int8 -1%s127 = %d, wanted -1\n", `|`, got) - failed = true - } - - if got := or_127_int8_ssa(0); got != 127 { - fmt.Printf("or_int8 127%s0 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_int8_127_ssa(0); got != 127 { - fmt.Printf("or_int8 0%s127 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_127_int8_ssa(1); got != 127 { - fmt.Printf("or_int8 127%s1 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_int8_127_ssa(1); got != 127 { - fmt.Printf("or_int8 1%s127 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_127_int8_ssa(126); got != 127 { - fmt.Printf("or_int8 127%s126 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_int8_127_ssa(126); got != 127 { - fmt.Printf("or_int8 126%s127 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_127_int8_ssa(127); got != 127 { - fmt.Printf("or_int8 127%s127 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := or_int8_127_ssa(127); got != 127 { - fmt.Printf("or_int8 127%s127 = %d, wanted 127\n", `|`, got) - failed = true - } - - if got := xor_Neg128_int8_ssa(-128); got != 0 { - fmt.Printf("xor_int8 -128%s-128 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg128_ssa(-128); got != 0 { - fmt.Printf("xor_int8 -128%s-128 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_Neg128_int8_ssa(-127); got != 1 { - fmt.Printf("xor_int8 -128%s-127 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg128_ssa(-127); got != 1 { - fmt.Printf("xor_int8 -127%s-128 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_Neg128_int8_ssa(-1); got != 127 { - fmt.Printf("xor_int8 -128%s-1 = %d, wanted 127\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg128_ssa(-1); got != 127 { - fmt.Printf("xor_int8 -1%s-128 = %d, wanted 127\n", `^`, got) - failed = true - } - - if got := xor_Neg128_int8_ssa(0); got != -128 { - fmt.Printf("xor_int8 -128%s0 = %d, wanted -128\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg128_ssa(0); got != -128 { - fmt.Printf("xor_int8 0%s-128 = %d, wanted -128\n", `^`, got) - failed = true - } - - if got := xor_Neg128_int8_ssa(1); got != -127 { - fmt.Printf("xor_int8 -128%s1 = %d, wanted -127\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg128_ssa(1); got != -127 { - fmt.Printf("xor_int8 1%s-128 = %d, wanted -127\n", `^`, got) - failed = true - } - - if got := xor_Neg128_int8_ssa(126); got != -2 { - fmt.Printf("xor_int8 -128%s126 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg128_ssa(126); got != -2 { - fmt.Printf("xor_int8 126%s-128 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_Neg128_int8_ssa(127); got != -1 { - fmt.Printf("xor_int8 -128%s127 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg128_ssa(127); got != -1 { - fmt.Printf("xor_int8 127%s-128 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_Neg127_int8_ssa(-128); got != 1 { - fmt.Printf("xor_int8 -127%s-128 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg127_ssa(-128); got != 1 { - fmt.Printf("xor_int8 -128%s-127 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_Neg127_int8_ssa(-127); got != 0 { - fmt.Printf("xor_int8 -127%s-127 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg127_ssa(-127); got != 0 { - fmt.Printf("xor_int8 -127%s-127 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_Neg127_int8_ssa(-1); got != 126 { - fmt.Printf("xor_int8 -127%s-1 = %d, wanted 126\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg127_ssa(-1); got != 126 { - fmt.Printf("xor_int8 -1%s-127 = %d, wanted 126\n", `^`, got) - failed = true - } - - if got := xor_Neg127_int8_ssa(0); got != -127 { - fmt.Printf("xor_int8 -127%s0 = %d, wanted -127\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg127_ssa(0); got != -127 { - fmt.Printf("xor_int8 0%s-127 = %d, wanted -127\n", `^`, got) - failed = true - } - - if got := xor_Neg127_int8_ssa(1); got != -128 { - fmt.Printf("xor_int8 -127%s1 = %d, wanted -128\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg127_ssa(1); got != -128 { - fmt.Printf("xor_int8 1%s-127 = %d, wanted -128\n", `^`, got) - failed = true - } - - if got := xor_Neg127_int8_ssa(126); got != -1 { - fmt.Printf("xor_int8 -127%s126 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg127_ssa(126); got != -1 { - fmt.Printf("xor_int8 126%s-127 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_Neg127_int8_ssa(127); got != -2 { - fmt.Printf("xor_int8 -127%s127 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg127_ssa(127); got != -2 { - fmt.Printf("xor_int8 127%s-127 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int8_ssa(-128); got != 127 { - fmt.Printf("xor_int8 -1%s-128 = %d, wanted 127\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg1_ssa(-128); got != 127 { - fmt.Printf("xor_int8 -128%s-1 = %d, wanted 127\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int8_ssa(-127); got != 126 { - fmt.Printf("xor_int8 -1%s-127 = %d, wanted 126\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg1_ssa(-127); got != 126 { - fmt.Printf("xor_int8 -127%s-1 = %d, wanted 126\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int8_ssa(-1); got != 0 { - fmt.Printf("xor_int8 -1%s-1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg1_ssa(-1); got != 0 { - fmt.Printf("xor_int8 -1%s-1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int8_ssa(0); got != -1 { - fmt.Printf("xor_int8 -1%s0 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg1_ssa(0); got != -1 { - fmt.Printf("xor_int8 0%s-1 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int8_ssa(1); got != -2 { - fmt.Printf("xor_int8 -1%s1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg1_ssa(1); got != -2 { - fmt.Printf("xor_int8 1%s-1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int8_ssa(126); got != -127 { - fmt.Printf("xor_int8 -1%s126 = %d, wanted -127\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg1_ssa(126); got != -127 { - fmt.Printf("xor_int8 126%s-1 = %d, wanted -127\n", `^`, got) - failed = true - } - - if got := xor_Neg1_int8_ssa(127); got != -128 { - fmt.Printf("xor_int8 -1%s127 = %d, wanted -128\n", `^`, got) - failed = true - } - - if got := xor_int8_Neg1_ssa(127); got != -128 { - fmt.Printf("xor_int8 127%s-1 = %d, wanted -128\n", `^`, got) - failed = true - } - - if got := xor_0_int8_ssa(-128); got != -128 { - fmt.Printf("xor_int8 0%s-128 = %d, wanted -128\n", `^`, got) - failed = true - } - - if got := xor_int8_0_ssa(-128); got != -128 { - fmt.Printf("xor_int8 -128%s0 = %d, wanted -128\n", `^`, got) - failed = true - } - - if got := xor_0_int8_ssa(-127); got != -127 { - fmt.Printf("xor_int8 0%s-127 = %d, wanted -127\n", `^`, got) - failed = true - } - - if got := xor_int8_0_ssa(-127); got != -127 { - fmt.Printf("xor_int8 -127%s0 = %d, wanted -127\n", `^`, got) - failed = true - } - - if got := xor_0_int8_ssa(-1); got != -1 { - fmt.Printf("xor_int8 0%s-1 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int8_0_ssa(-1); got != -1 { - fmt.Printf("xor_int8 -1%s0 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_0_int8_ssa(0); got != 0 { - fmt.Printf("xor_int8 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int8_0_ssa(0); got != 0 { - fmt.Printf("xor_int8 0%s0 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_0_int8_ssa(1); got != 1 { - fmt.Printf("xor_int8 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int8_0_ssa(1); got != 1 { - fmt.Printf("xor_int8 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_0_int8_ssa(126); got != 126 { - fmt.Printf("xor_int8 0%s126 = %d, wanted 126\n", `^`, got) - failed = true - } - - if got := xor_int8_0_ssa(126); got != 126 { - fmt.Printf("xor_int8 126%s0 = %d, wanted 126\n", `^`, got) - failed = true - } - - if got := xor_0_int8_ssa(127); got != 127 { - fmt.Printf("xor_int8 0%s127 = %d, wanted 127\n", `^`, got) - failed = true - } - - if got := xor_int8_0_ssa(127); got != 127 { - fmt.Printf("xor_int8 127%s0 = %d, wanted 127\n", `^`, got) - failed = true - } - - if got := xor_1_int8_ssa(-128); got != -127 { - fmt.Printf("xor_int8 1%s-128 = %d, wanted -127\n", `^`, got) - failed = true - } - - if got := xor_int8_1_ssa(-128); got != -127 { - fmt.Printf("xor_int8 -128%s1 = %d, wanted -127\n", `^`, got) - failed = true - } - - if got := xor_1_int8_ssa(-127); got != -128 { - fmt.Printf("xor_int8 1%s-127 = %d, wanted -128\n", `^`, got) - failed = true - } - - if got := xor_int8_1_ssa(-127); got != -128 { - fmt.Printf("xor_int8 -127%s1 = %d, wanted -128\n", `^`, got) - failed = true - } - - if got := xor_1_int8_ssa(-1); got != -2 { - fmt.Printf("xor_int8 1%s-1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int8_1_ssa(-1); got != -2 { - fmt.Printf("xor_int8 -1%s1 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_1_int8_ssa(0); got != 1 { - fmt.Printf("xor_int8 1%s0 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int8_1_ssa(0); got != 1 { - fmt.Printf("xor_int8 0%s1 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_1_int8_ssa(1); got != 0 { - fmt.Printf("xor_int8 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int8_1_ssa(1); got != 0 { - fmt.Printf("xor_int8 1%s1 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_1_int8_ssa(126); got != 127 { - fmt.Printf("xor_int8 1%s126 = %d, wanted 127\n", `^`, got) - failed = true - } - - if got := xor_int8_1_ssa(126); got != 127 { - fmt.Printf("xor_int8 126%s1 = %d, wanted 127\n", `^`, got) - failed = true - } - - if got := xor_1_int8_ssa(127); got != 126 { - fmt.Printf("xor_int8 1%s127 = %d, wanted 126\n", `^`, got) - failed = true - } - - if got := xor_int8_1_ssa(127); got != 126 { - fmt.Printf("xor_int8 127%s1 = %d, wanted 126\n", `^`, got) - failed = true - } - - if got := xor_126_int8_ssa(-128); got != -2 { - fmt.Printf("xor_int8 126%s-128 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int8_126_ssa(-128); got != -2 { - fmt.Printf("xor_int8 -128%s126 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_126_int8_ssa(-127); got != -1 { - fmt.Printf("xor_int8 126%s-127 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int8_126_ssa(-127); got != -1 { - fmt.Printf("xor_int8 -127%s126 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_126_int8_ssa(-1); got != -127 { - fmt.Printf("xor_int8 126%s-1 = %d, wanted -127\n", `^`, got) - failed = true - } - - if got := xor_int8_126_ssa(-1); got != -127 { - fmt.Printf("xor_int8 -1%s126 = %d, wanted -127\n", `^`, got) - failed = true - } - - if got := xor_126_int8_ssa(0); got != 126 { - fmt.Printf("xor_int8 126%s0 = %d, wanted 126\n", `^`, got) - failed = true - } - - if got := xor_int8_126_ssa(0); got != 126 { - fmt.Printf("xor_int8 0%s126 = %d, wanted 126\n", `^`, got) - failed = true - } - - if got := xor_126_int8_ssa(1); got != 127 { - fmt.Printf("xor_int8 126%s1 = %d, wanted 127\n", `^`, got) - failed = true - } - - if got := xor_int8_126_ssa(1); got != 127 { - fmt.Printf("xor_int8 1%s126 = %d, wanted 127\n", `^`, got) - failed = true - } - - if got := xor_126_int8_ssa(126); got != 0 { - fmt.Printf("xor_int8 126%s126 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_int8_126_ssa(126); got != 0 { - fmt.Printf("xor_int8 126%s126 = %d, wanted 0\n", `^`, got) - failed = true - } - - if got := xor_126_int8_ssa(127); got != 1 { - fmt.Printf("xor_int8 126%s127 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_int8_126_ssa(127); got != 1 { - fmt.Printf("xor_int8 127%s126 = %d, wanted 1\n", `^`, got) - failed = true - } - - if got := xor_127_int8_ssa(-128); got != -1 { - fmt.Printf("xor_int8 127%s-128 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_int8_127_ssa(-128); got != -1 { - fmt.Printf("xor_int8 -128%s127 = %d, wanted -1\n", `^`, got) - failed = true - } - - if got := xor_127_int8_ssa(-127); got != -2 { - fmt.Printf("xor_int8 127%s-127 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_int8_127_ssa(-127); got != -2 { - fmt.Printf("xor_int8 -127%s127 = %d, wanted -2\n", `^`, got) - failed = true - } - - if got := xor_127_int8_ssa(-1); got != -128 { - fmt.Printf("xor_int8 127%s-1 = %d, wanted -128\n", `^`, got) - failed = true - } - - if got := xor_int8_127_ssa(-1); got != -128 { - fmt.Printf("xor_int8 -1%s127 = %d, wanted -128\n", `^`, got) - failed = true + for _, test := range tests_uint64 { + if got := test.fn(test.in); got != test.want { + fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) + failed = true + } } - - if got := xor_127_int8_ssa(0); got != 127 { - fmt.Printf("xor_int8 127%s0 = %d, wanted 127\n", `^`, got) - failed = true + for _, test := range tests_int64 { + if got := test.fn(test.in); got != test.want { + fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) + failed = true + } } - - if got := xor_int8_127_ssa(0); got != 127 { - fmt.Printf("xor_int8 0%s127 = %d, wanted 127\n", `^`, got) - failed = true + for _, test := range tests_uint32 { + if got := test.fn(test.in); got != test.want { + fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) + failed = true + } } - - if got := xor_127_int8_ssa(1); got != 126 { - fmt.Printf("xor_int8 127%s1 = %d, wanted 126\n", `^`, got) - failed = true + for _, test := range tests_int32 { + if got := test.fn(test.in); got != test.want { + fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) + failed = true + } } - - if got := xor_int8_127_ssa(1); got != 126 { - fmt.Printf("xor_int8 1%s127 = %d, wanted 126\n", `^`, got) - failed = true + for _, test := range tests_uint16 { + if got := test.fn(test.in); got != test.want { + fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) + failed = true + } } - - if got := xor_127_int8_ssa(126); got != 1 { - fmt.Printf("xor_int8 127%s126 = %d, wanted 1\n", `^`, got) - failed = true + for _, test := range tests_int16 { + if got := test.fn(test.in); got != test.want { + fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) + failed = true + } } - - if got := xor_int8_127_ssa(126); got != 1 { - fmt.Printf("xor_int8 126%s127 = %d, wanted 1\n", `^`, got) - failed = true + for _, test := range tests_uint8 { + if got := test.fn(test.in); got != test.want { + fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) + failed = true + } } - - if got := xor_127_int8_ssa(127); got != 0 { - fmt.Printf("xor_int8 127%s127 = %d, wanted 0\n", `^`, got) - failed = true + for _, test := range tests_int8 { + if got := test.fn(test.in); got != test.want { + fmt.Printf("%s(%d) = %d, want %d\n", test.fnname, test.in, got, test.want) + failed = true + } } - if got := xor_int8_127_ssa(127); got != 0 { - fmt.Printf("xor_int8 127%s127 = %d, wanted 0\n", `^`, got) - failed = true - } if failed { - panic("tests failed") + os.Exit(1) } } go_bb1fd3b5ff10eb9ad1a40b5bf7c7f35bd20e626f_src_cmd_compile_internal_ssa_rewritePPC64.go.test000066400000000000000000075753051516001707200363100ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit bb1fd3b5ff10eb9ad1a40b5bf7c7f35bd20e626f file src/cmd/compile/internal/ssa/rewritePPC64.go -- x -- // Code generated from gen/PPC64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/internal/obj" import "cmd/internal/objabi" import "cmd/compile/internal/types" var _ = math.MinInt8 // in case not otherwise used var _ = obj.ANOP // in case not otherwise used var _ = objabi.GOROOT // in case not otherwise used var _ = types.TypeMem // in case not otherwise used func rewriteValuePPC64(v *Value) bool { switch v.Op { case OpAbs: return rewriteValuePPC64_OpAbs_0(v) case OpAdd16: return rewriteValuePPC64_OpAdd16_0(v) case OpAdd32: return rewriteValuePPC64_OpAdd32_0(v) case OpAdd32F: return rewriteValuePPC64_OpAdd32F_0(v) case OpAdd64: return rewriteValuePPC64_OpAdd64_0(v) case OpAdd64F: return rewriteValuePPC64_OpAdd64F_0(v) case OpAdd8: return rewriteValuePPC64_OpAdd8_0(v) case OpAddPtr: return rewriteValuePPC64_OpAddPtr_0(v) case OpAddr: return rewriteValuePPC64_OpAddr_0(v) case OpAnd16: return rewriteValuePPC64_OpAnd16_0(v) case OpAnd32: return rewriteValuePPC64_OpAnd32_0(v) case OpAnd64: return rewriteValuePPC64_OpAnd64_0(v) case OpAnd8: return rewriteValuePPC64_OpAnd8_0(v) case OpAndB: return rewriteValuePPC64_OpAndB_0(v) case OpAtomicAdd32: return rewriteValuePPC64_OpAtomicAdd32_0(v) case OpAtomicAdd64: return rewriteValuePPC64_OpAtomicAdd64_0(v) case OpAtomicAnd8: return rewriteValuePPC64_OpAtomicAnd8_0(v) case OpAtomicCompareAndSwap32: return rewriteValuePPC64_OpAtomicCompareAndSwap32_0(v) case OpAtomicCompareAndSwap64: return rewriteValuePPC64_OpAtomicCompareAndSwap64_0(v) case OpAtomicExchange32: return rewriteValuePPC64_OpAtomicExchange32_0(v) case OpAtomicExchange64: return rewriteValuePPC64_OpAtomicExchange64_0(v) case OpAtomicLoad32: return rewriteValuePPC64_OpAtomicLoad32_0(v) case OpAtomicLoad64: return rewriteValuePPC64_OpAtomicLoad64_0(v) case OpAtomicLoadPtr: return rewriteValuePPC64_OpAtomicLoadPtr_0(v) case OpAtomicOr8: return rewriteValuePPC64_OpAtomicOr8_0(v) case OpAtomicStore32: return rewriteValuePPC64_OpAtomicStore32_0(v) case OpAtomicStore64: return rewriteValuePPC64_OpAtomicStore64_0(v) case OpAvg64u: return rewriteValuePPC64_OpAvg64u_0(v) case OpBitLen32: return rewriteValuePPC64_OpBitLen32_0(v) case OpBitLen64: return rewriteValuePPC64_OpBitLen64_0(v) case OpCeil: return rewriteValuePPC64_OpCeil_0(v) case OpClosureCall: return rewriteValuePPC64_OpClosureCall_0(v) case OpCom16: return rewriteValuePPC64_OpCom16_0(v) case OpCom32: return rewriteValuePPC64_OpCom32_0(v) case OpCom64: return rewriteValuePPC64_OpCom64_0(v) case OpCom8: return rewriteValuePPC64_OpCom8_0(v) case OpConst16: return rewriteValuePPC64_OpConst16_0(v) case OpConst32: return rewriteValuePPC64_OpConst32_0(v) case OpConst32F: return rewriteValuePPC64_OpConst32F_0(v) case OpConst64: return rewriteValuePPC64_OpConst64_0(v) case OpConst64F: return rewriteValuePPC64_OpConst64F_0(v) case OpConst8: return rewriteValuePPC64_OpConst8_0(v) case OpConstBool: return rewriteValuePPC64_OpConstBool_0(v) case OpConstNil: return rewriteValuePPC64_OpConstNil_0(v) case OpConvert: return rewriteValuePPC64_OpConvert_0(v) case OpCopysign: return rewriteValuePPC64_OpCopysign_0(v) case OpCtz32: return rewriteValuePPC64_OpCtz32_0(v) case OpCtz64: return rewriteValuePPC64_OpCtz64_0(v) case OpCvt32Fto32: return rewriteValuePPC64_OpCvt32Fto32_0(v) case OpCvt32Fto64: return rewriteValuePPC64_OpCvt32Fto64_0(v) case OpCvt32Fto64F: return rewriteValuePPC64_OpCvt32Fto64F_0(v) case OpCvt32to32F: return rewriteValuePPC64_OpCvt32to32F_0(v) case OpCvt32to64F: return rewriteValuePPC64_OpCvt32to64F_0(v) case OpCvt64Fto32: return rewriteValuePPC64_OpCvt64Fto32_0(v) case OpCvt64Fto32F: return rewriteValuePPC64_OpCvt64Fto32F_0(v) case OpCvt64Fto64: return rewriteValuePPC64_OpCvt64Fto64_0(v) case OpCvt64to32F: return rewriteValuePPC64_OpCvt64to32F_0(v) case OpCvt64to64F: return rewriteValuePPC64_OpCvt64to64F_0(v) case OpDiv16: return rewriteValuePPC64_OpDiv16_0(v) case OpDiv16u: return rewriteValuePPC64_OpDiv16u_0(v) case OpDiv32: return rewriteValuePPC64_OpDiv32_0(v) case OpDiv32F: return rewriteValuePPC64_OpDiv32F_0(v) case OpDiv32u: return rewriteValuePPC64_OpDiv32u_0(v) case OpDiv64: return rewriteValuePPC64_OpDiv64_0(v) case OpDiv64F: return rewriteValuePPC64_OpDiv64F_0(v) case OpDiv64u: return rewriteValuePPC64_OpDiv64u_0(v) case OpDiv8: return rewriteValuePPC64_OpDiv8_0(v) case OpDiv8u: return rewriteValuePPC64_OpDiv8u_0(v) case OpEq16: return rewriteValuePPC64_OpEq16_0(v) case OpEq32: return rewriteValuePPC64_OpEq32_0(v) case OpEq32F: return rewriteValuePPC64_OpEq32F_0(v) case OpEq64: return rewriteValuePPC64_OpEq64_0(v) case OpEq64F: return rewriteValuePPC64_OpEq64F_0(v) case OpEq8: return rewriteValuePPC64_OpEq8_0(v) case OpEqB: return rewriteValuePPC64_OpEqB_0(v) case OpEqPtr: return rewriteValuePPC64_OpEqPtr_0(v) case OpFloor: return rewriteValuePPC64_OpFloor_0(v) case OpGeq16: return rewriteValuePPC64_OpGeq16_0(v) case OpGeq16U: return rewriteValuePPC64_OpGeq16U_0(v) case OpGeq32: return rewriteValuePPC64_OpGeq32_0(v) case OpGeq32F: return rewriteValuePPC64_OpGeq32F_0(v) case OpGeq32U: return rewriteValuePPC64_OpGeq32U_0(v) case OpGeq64: return rewriteValuePPC64_OpGeq64_0(v) case OpGeq64F: return rewriteValuePPC64_OpGeq64F_0(v) case OpGeq64U: return rewriteValuePPC64_OpGeq64U_0(v) case OpGeq8: return rewriteValuePPC64_OpGeq8_0(v) case OpGeq8U: return rewriteValuePPC64_OpGeq8U_0(v) case OpGetCallerSP: return rewriteValuePPC64_OpGetCallerSP_0(v) case OpGetClosurePtr: return rewriteValuePPC64_OpGetClosurePtr_0(v) case OpGreater16: return rewriteValuePPC64_OpGreater16_0(v) case OpGreater16U: return rewriteValuePPC64_OpGreater16U_0(v) case OpGreater32: return rewriteValuePPC64_OpGreater32_0(v) case OpGreater32F: return rewriteValuePPC64_OpGreater32F_0(v) case OpGreater32U: return rewriteValuePPC64_OpGreater32U_0(v) case OpGreater64: return rewriteValuePPC64_OpGreater64_0(v) case OpGreater64F: return rewriteValuePPC64_OpGreater64F_0(v) case OpGreater64U: return rewriteValuePPC64_OpGreater64U_0(v) case OpGreater8: return rewriteValuePPC64_OpGreater8_0(v) case OpGreater8U: return rewriteValuePPC64_OpGreater8U_0(v) case OpHmul32: return rewriteValuePPC64_OpHmul32_0(v) case OpHmul32u: return rewriteValuePPC64_OpHmul32u_0(v) case OpHmul64: return rewriteValuePPC64_OpHmul64_0(v) case OpHmul64u: return rewriteValuePPC64_OpHmul64u_0(v) case OpInterCall: return rewriteValuePPC64_OpInterCall_0(v) case OpIsInBounds: return rewriteValuePPC64_OpIsInBounds_0(v) case OpIsNonNil: return rewriteValuePPC64_OpIsNonNil_0(v) case OpIsSliceInBounds: return rewriteValuePPC64_OpIsSliceInBounds_0(v) case OpLeq16: return rewriteValuePPC64_OpLeq16_0(v) case OpLeq16U: return rewriteValuePPC64_OpLeq16U_0(v) case OpLeq32: return rewriteValuePPC64_OpLeq32_0(v) case OpLeq32F: return rewriteValuePPC64_OpLeq32F_0(v) case OpLeq32U: return rewriteValuePPC64_OpLeq32U_0(v) case OpLeq64: return rewriteValuePPC64_OpLeq64_0(v) case OpLeq64F: return rewriteValuePPC64_OpLeq64F_0(v) case OpLeq64U: return rewriteValuePPC64_OpLeq64U_0(v) case OpLeq8: return rewriteValuePPC64_OpLeq8_0(v) case OpLeq8U: return rewriteValuePPC64_OpLeq8U_0(v) case OpLess16: return rewriteValuePPC64_OpLess16_0(v) case OpLess16U: return rewriteValuePPC64_OpLess16U_0(v) case OpLess32: return rewriteValuePPC64_OpLess32_0(v) case OpLess32F: return rewriteValuePPC64_OpLess32F_0(v) case OpLess32U: return rewriteValuePPC64_OpLess32U_0(v) case OpLess64: return rewriteValuePPC64_OpLess64_0(v) case OpLess64F: return rewriteValuePPC64_OpLess64F_0(v) case OpLess64U: return rewriteValuePPC64_OpLess64U_0(v) case OpLess8: return rewriteValuePPC64_OpLess8_0(v) case OpLess8U: return rewriteValuePPC64_OpLess8U_0(v) case OpLoad: return rewriteValuePPC64_OpLoad_0(v) case OpLsh16x16: return rewriteValuePPC64_OpLsh16x16_0(v) case OpLsh16x32: return rewriteValuePPC64_OpLsh16x32_0(v) case OpLsh16x64: return rewriteValuePPC64_OpLsh16x64_0(v) case OpLsh16x8: return rewriteValuePPC64_OpLsh16x8_0(v) case OpLsh32x16: return rewriteValuePPC64_OpLsh32x16_0(v) case OpLsh32x32: return rewriteValuePPC64_OpLsh32x32_0(v) case OpLsh32x64: return rewriteValuePPC64_OpLsh32x64_0(v) case OpLsh32x8: return rewriteValuePPC64_OpLsh32x8_0(v) case OpLsh64x16: return rewriteValuePPC64_OpLsh64x16_0(v) case OpLsh64x32: return rewriteValuePPC64_OpLsh64x32_0(v) case OpLsh64x64: return rewriteValuePPC64_OpLsh64x64_0(v) case OpLsh64x8: return rewriteValuePPC64_OpLsh64x8_0(v) case OpLsh8x16: return rewriteValuePPC64_OpLsh8x16_0(v) case OpLsh8x32: return rewriteValuePPC64_OpLsh8x32_0(v) case OpLsh8x64: return rewriteValuePPC64_OpLsh8x64_0(v) case OpLsh8x8: return rewriteValuePPC64_OpLsh8x8_0(v) case OpMod16: return rewriteValuePPC64_OpMod16_0(v) case OpMod16u: return rewriteValuePPC64_OpMod16u_0(v) case OpMod32: return rewriteValuePPC64_OpMod32_0(v) case OpMod32u: return rewriteValuePPC64_OpMod32u_0(v) case OpMod64: return rewriteValuePPC64_OpMod64_0(v) case OpMod64u: return rewriteValuePPC64_OpMod64u_0(v) case OpMod8: return rewriteValuePPC64_OpMod8_0(v) case OpMod8u: return rewriteValuePPC64_OpMod8u_0(v) case OpMove: return rewriteValuePPC64_OpMove_0(v) || rewriteValuePPC64_OpMove_10(v) case OpMul16: return rewriteValuePPC64_OpMul16_0(v) case OpMul32: return rewriteValuePPC64_OpMul32_0(v) case OpMul32F: return rewriteValuePPC64_OpMul32F_0(v) case OpMul64: return rewriteValuePPC64_OpMul64_0(v) case OpMul64F: return rewriteValuePPC64_OpMul64F_0(v) case OpMul8: return rewriteValuePPC64_OpMul8_0(v) case OpNeg16: return rewriteValuePPC64_OpNeg16_0(v) case OpNeg32: return rewriteValuePPC64_OpNeg32_0(v) case OpNeg32F: return rewriteValuePPC64_OpNeg32F_0(v) case OpNeg64: return rewriteValuePPC64_OpNeg64_0(v) case OpNeg64F: return rewriteValuePPC64_OpNeg64F_0(v) case OpNeg8: return rewriteValuePPC64_OpNeg8_0(v) case OpNeq16: return rewriteValuePPC64_OpNeq16_0(v) case OpNeq32: return rewriteValuePPC64_OpNeq32_0(v) case OpNeq32F: return rewriteValuePPC64_OpNeq32F_0(v) case OpNeq64: return rewriteValuePPC64_OpNeq64_0(v) case OpNeq64F: return rewriteValuePPC64_OpNeq64F_0(v) case OpNeq8: return rewriteValuePPC64_OpNeq8_0(v) case OpNeqB: return rewriteValuePPC64_OpNeqB_0(v) case OpNeqPtr: return rewriteValuePPC64_OpNeqPtr_0(v) case OpNilCheck: return rewriteValuePPC64_OpNilCheck_0(v) case OpNot: return rewriteValuePPC64_OpNot_0(v) case OpOffPtr: return rewriteValuePPC64_OpOffPtr_0(v) case OpOr16: return rewriteValuePPC64_OpOr16_0(v) case OpOr32: return rewriteValuePPC64_OpOr32_0(v) case OpOr64: return rewriteValuePPC64_OpOr64_0(v) case OpOr8: return rewriteValuePPC64_OpOr8_0(v) case OpOrB: return rewriteValuePPC64_OpOrB_0(v) case OpPPC64ADD: return rewriteValuePPC64_OpPPC64ADD_0(v) case OpPPC64ADDconst: return rewriteValuePPC64_OpPPC64ADDconst_0(v) case OpPPC64AND: return rewriteValuePPC64_OpPPC64AND_0(v) case OpPPC64ANDconst: return rewriteValuePPC64_OpPPC64ANDconst_0(v) case OpPPC64CMP: return rewriteValuePPC64_OpPPC64CMP_0(v) case OpPPC64CMPU: return rewriteValuePPC64_OpPPC64CMPU_0(v) case OpPPC64CMPUconst: return rewriteValuePPC64_OpPPC64CMPUconst_0(v) case OpPPC64CMPW: return rewriteValuePPC64_OpPPC64CMPW_0(v) case OpPPC64CMPWU: return rewriteValuePPC64_OpPPC64CMPWU_0(v) case OpPPC64CMPWUconst: return rewriteValuePPC64_OpPPC64CMPWUconst_0(v) case OpPPC64CMPWconst: return rewriteValuePPC64_OpPPC64CMPWconst_0(v) case OpPPC64CMPconst: return rewriteValuePPC64_OpPPC64CMPconst_0(v) case OpPPC64Equal: return rewriteValuePPC64_OpPPC64Equal_0(v) case OpPPC64FABS: return rewriteValuePPC64_OpPPC64FABS_0(v) case OpPPC64FADD: return rewriteValuePPC64_OpPPC64FADD_0(v) case OpPPC64FADDS: return rewriteValuePPC64_OpPPC64FADDS_0(v) case OpPPC64FCEIL: return rewriteValuePPC64_OpPPC64FCEIL_0(v) case OpPPC64FFLOOR: return rewriteValuePPC64_OpPPC64FFLOOR_0(v) case OpPPC64FMOVDload: return rewriteValuePPC64_OpPPC64FMOVDload_0(v) case OpPPC64FMOVDstore: return rewriteValuePPC64_OpPPC64FMOVDstore_0(v) case OpPPC64FMOVSload: return rewriteValuePPC64_OpPPC64FMOVSload_0(v) case OpPPC64FMOVSstore: return rewriteValuePPC64_OpPPC64FMOVSstore_0(v) case OpPPC64FNEG: return rewriteValuePPC64_OpPPC64FNEG_0(v) case OpPPC64FSQRT: return rewriteValuePPC64_OpPPC64FSQRT_0(v) case OpPPC64FSUB: return rewriteValuePPC64_OpPPC64FSUB_0(v) case OpPPC64FSUBS: return rewriteValuePPC64_OpPPC64FSUBS_0(v) case OpPPC64FTRUNC: return rewriteValuePPC64_OpPPC64FTRUNC_0(v) case OpPPC64GreaterEqual: return rewriteValuePPC64_OpPPC64GreaterEqual_0(v) case OpPPC64GreaterThan: return rewriteValuePPC64_OpPPC64GreaterThan_0(v) case OpPPC64LessEqual: return rewriteValuePPC64_OpPPC64LessEqual_0(v) case OpPPC64LessThan: return rewriteValuePPC64_OpPPC64LessThan_0(v) case OpPPC64MFVSRD: return rewriteValuePPC64_OpPPC64MFVSRD_0(v) case OpPPC64MOVBZload: return rewriteValuePPC64_OpPPC64MOVBZload_0(v) case OpPPC64MOVBZreg: return rewriteValuePPC64_OpPPC64MOVBZreg_0(v) case OpPPC64MOVBreg: return rewriteValuePPC64_OpPPC64MOVBreg_0(v) case OpPPC64MOVBstore: return rewriteValuePPC64_OpPPC64MOVBstore_0(v) case OpPPC64MOVBstorezero: return rewriteValuePPC64_OpPPC64MOVBstorezero_0(v) case OpPPC64MOVDload: return rewriteValuePPC64_OpPPC64MOVDload_0(v) case OpPPC64MOVDstore: return rewriteValuePPC64_OpPPC64MOVDstore_0(v) case OpPPC64MOVDstorezero: return rewriteValuePPC64_OpPPC64MOVDstorezero_0(v) case OpPPC64MOVHZload: return rewriteValuePPC64_OpPPC64MOVHZload_0(v) case OpPPC64MOVHZreg: return rewriteValuePPC64_OpPPC64MOVHZreg_0(v) case OpPPC64MOVHload: return rewriteValuePPC64_OpPPC64MOVHload_0(v) case OpPPC64MOVHreg: return rewriteValuePPC64_OpPPC64MOVHreg_0(v) case OpPPC64MOVHstore: return rewriteValuePPC64_OpPPC64MOVHstore_0(v) case OpPPC64MOVHstorezero: return rewriteValuePPC64_OpPPC64MOVHstorezero_0(v) case OpPPC64MOVWZload: return rewriteValuePPC64_OpPPC64MOVWZload_0(v) case OpPPC64MOVWZreg: return rewriteValuePPC64_OpPPC64MOVWZreg_0(v) case OpPPC64MOVWload: return rewriteValuePPC64_OpPPC64MOVWload_0(v) case OpPPC64MOVWreg: return rewriteValuePPC64_OpPPC64MOVWreg_0(v) case OpPPC64MOVWstore: return rewriteValuePPC64_OpPPC64MOVWstore_0(v) case OpPPC64MOVWstorezero: return rewriteValuePPC64_OpPPC64MOVWstorezero_0(v) case OpPPC64MTVSRD: return rewriteValuePPC64_OpPPC64MTVSRD_0(v) case OpPPC64MaskIfNotCarry: return rewriteValuePPC64_OpPPC64MaskIfNotCarry_0(v) case OpPPC64NotEqual: return rewriteValuePPC64_OpPPC64NotEqual_0(v) case OpPPC64OR: return rewriteValuePPC64_OpPPC64OR_0(v) || rewriteValuePPC64_OpPPC64OR_10(v) case OpPPC64ORN: return rewriteValuePPC64_OpPPC64ORN_0(v) case OpPPC64ORconst: return rewriteValuePPC64_OpPPC64ORconst_0(v) case OpPPC64SUB: return rewriteValuePPC64_OpPPC64SUB_0(v) case OpPPC64XOR: return rewriteValuePPC64_OpPPC64XOR_0(v) || rewriteValuePPC64_OpPPC64XOR_10(v) case OpPPC64XORconst: return rewriteValuePPC64_OpPPC64XORconst_0(v) case OpPopCount16: return rewriteValuePPC64_OpPopCount16_0(v) case OpPopCount32: return rewriteValuePPC64_OpPopCount32_0(v) case OpPopCount64: return rewriteValuePPC64_OpPopCount64_0(v) case OpPopCount8: return rewriteValuePPC64_OpPopCount8_0(v) case OpRound32F: return rewriteValuePPC64_OpRound32F_0(v) case OpRound64F: return rewriteValuePPC64_OpRound64F_0(v) case OpRsh16Ux16: return rewriteValuePPC64_OpRsh16Ux16_0(v) case OpRsh16Ux32: return rewriteValuePPC64_OpRsh16Ux32_0(v) case OpRsh16Ux64: return rewriteValuePPC64_OpRsh16Ux64_0(v) case OpRsh16Ux8: return rewriteValuePPC64_OpRsh16Ux8_0(v) case OpRsh16x16: return rewriteValuePPC64_OpRsh16x16_0(v) case OpRsh16x32: return rewriteValuePPC64_OpRsh16x32_0(v) case OpRsh16x64: return rewriteValuePPC64_OpRsh16x64_0(v) case OpRsh16x8: return rewriteValuePPC64_OpRsh16x8_0(v) case OpRsh32Ux16: return rewriteValuePPC64_OpRsh32Ux16_0(v) case OpRsh32Ux32: return rewriteValuePPC64_OpRsh32Ux32_0(v) case OpRsh32Ux64: return rewriteValuePPC64_OpRsh32Ux64_0(v) case OpRsh32Ux8: return rewriteValuePPC64_OpRsh32Ux8_0(v) case OpRsh32x16: return rewriteValuePPC64_OpRsh32x16_0(v) case OpRsh32x32: return rewriteValuePPC64_OpRsh32x32_0(v) case OpRsh32x64: return rewriteValuePPC64_OpRsh32x64_0(v) case OpRsh32x8: return rewriteValuePPC64_OpRsh32x8_0(v) case OpRsh64Ux16: return rewriteValuePPC64_OpRsh64Ux16_0(v) case OpRsh64Ux32: return rewriteValuePPC64_OpRsh64Ux32_0(v) case OpRsh64Ux64: return rewriteValuePPC64_OpRsh64Ux64_0(v) case OpRsh64Ux8: return rewriteValuePPC64_OpRsh64Ux8_0(v) case OpRsh64x16: return rewriteValuePPC64_OpRsh64x16_0(v) case OpRsh64x32: return rewriteValuePPC64_OpRsh64x32_0(v) case OpRsh64x64: return rewriteValuePPC64_OpRsh64x64_0(v) case OpRsh64x8: return rewriteValuePPC64_OpRsh64x8_0(v) case OpRsh8Ux16: return rewriteValuePPC64_OpRsh8Ux16_0(v) case OpRsh8Ux32: return rewriteValuePPC64_OpRsh8Ux32_0(v) case OpRsh8Ux64: return rewriteValuePPC64_OpRsh8Ux64_0(v) case OpRsh8Ux8: return rewriteValuePPC64_OpRsh8Ux8_0(v) case OpRsh8x16: return rewriteValuePPC64_OpRsh8x16_0(v) case OpRsh8x32: return rewriteValuePPC64_OpRsh8x32_0(v) case OpRsh8x64: return rewriteValuePPC64_OpRsh8x64_0(v) case OpRsh8x8: return rewriteValuePPC64_OpRsh8x8_0(v) case OpSignExt16to32: return rewriteValuePPC64_OpSignExt16to32_0(v) case OpSignExt16to64: return rewriteValuePPC64_OpSignExt16to64_0(v) case OpSignExt32to64: return rewriteValuePPC64_OpSignExt32to64_0(v) case OpSignExt8to16: return rewriteValuePPC64_OpSignExt8to16_0(v) case OpSignExt8to32: return rewriteValuePPC64_OpSignExt8to32_0(v) case OpSignExt8to64: return rewriteValuePPC64_OpSignExt8to64_0(v) case OpSlicemask: return rewriteValuePPC64_OpSlicemask_0(v) case OpSqrt: return rewriteValuePPC64_OpSqrt_0(v) case OpStaticCall: return rewriteValuePPC64_OpStaticCall_0(v) case OpStore: return rewriteValuePPC64_OpStore_0(v) case OpSub16: return rewriteValuePPC64_OpSub16_0(v) case OpSub32: return rewriteValuePPC64_OpSub32_0(v) case OpSub32F: return rewriteValuePPC64_OpSub32F_0(v) case OpSub64: return rewriteValuePPC64_OpSub64_0(v) case OpSub64F: return rewriteValuePPC64_OpSub64F_0(v) case OpSub8: return rewriteValuePPC64_OpSub8_0(v) case OpSubPtr: return rewriteValuePPC64_OpSubPtr_0(v) case OpTrunc: return rewriteValuePPC64_OpTrunc_0(v) case OpTrunc16to8: return rewriteValuePPC64_OpTrunc16to8_0(v) case OpTrunc32to16: return rewriteValuePPC64_OpTrunc32to16_0(v) case OpTrunc32to8: return rewriteValuePPC64_OpTrunc32to8_0(v) case OpTrunc64to16: return rewriteValuePPC64_OpTrunc64to16_0(v) case OpTrunc64to32: return rewriteValuePPC64_OpTrunc64to32_0(v) case OpTrunc64to8: return rewriteValuePPC64_OpTrunc64to8_0(v) case OpXor16: return rewriteValuePPC64_OpXor16_0(v) case OpXor32: return rewriteValuePPC64_OpXor32_0(v) case OpXor64: return rewriteValuePPC64_OpXor64_0(v) case OpXor8: return rewriteValuePPC64_OpXor8_0(v) case OpZero: return rewriteValuePPC64_OpZero_0(v) || rewriteValuePPC64_OpZero_10(v) case OpZeroExt16to32: return rewriteValuePPC64_OpZeroExt16to32_0(v) case OpZeroExt16to64: return rewriteValuePPC64_OpZeroExt16to64_0(v) case OpZeroExt32to64: return rewriteValuePPC64_OpZeroExt32to64_0(v) case OpZeroExt8to16: return rewriteValuePPC64_OpZeroExt8to16_0(v) case OpZeroExt8to32: return rewriteValuePPC64_OpZeroExt8to32_0(v) case OpZeroExt8to64: return rewriteValuePPC64_OpZeroExt8to64_0(v) } return false } func rewriteValuePPC64_OpAbs_0(v *Value) bool { // match: (Abs x) // cond: // result: (FABS x) for { x := v.Args[0] v.reset(OpPPC64FABS) v.AddArg(x) return true } } func rewriteValuePPC64_OpAdd16_0(v *Value) bool { // match: (Add16 x y) // cond: // result: (ADD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd32_0(v *Value) bool { // match: (Add32 x y) // cond: // result: (ADD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd32F_0(v *Value) bool { // match: (Add32F x y) // cond: // result: (FADDS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FADDS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd64_0(v *Value) bool { // match: (Add64 x y) // cond: // result: (ADD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd64F_0(v *Value) bool { // match: (Add64F x y) // cond: // result: (FADD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd8_0(v *Value) bool { // match: (Add8 x y) // cond: // result: (ADD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAddPtr_0(v *Value) bool { // match: (AddPtr x y) // cond: // result: (ADD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAddr_0(v *Value) bool { // match: (Addr {sym} base) // cond: // result: (MOVDaddr {sym} base) for { sym := v.Aux base := v.Args[0] v.reset(OpPPC64MOVDaddr) v.Aux = sym v.AddArg(base) return true } } func rewriteValuePPC64_OpAnd16_0(v *Value) bool { // match: (And16 x y) // cond: // result: (AND x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAnd32_0(v *Value) bool { // match: (And32 x y) // cond: // result: (AND x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAnd64_0(v *Value) bool { // match: (And64 x y) // cond: // result: (AND x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAnd8_0(v *Value) bool { // match: (And8 x y) // cond: // result: (AND x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAndB_0(v *Value) bool { // match: (AndB x y) // cond: // result: (AND x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAtomicAdd32_0(v *Value) bool { // match: (AtomicAdd32 ptr val mem) // cond: // result: (LoweredAtomicAdd32 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicAdd32) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicAdd64_0(v *Value) bool { // match: (AtomicAdd64 ptr val mem) // cond: // result: (LoweredAtomicAdd64 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicAdd64) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicAnd8_0(v *Value) bool { // match: (AtomicAnd8 ptr val mem) // cond: // result: (LoweredAtomicAnd8 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicAnd8) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicCompareAndSwap32_0(v *Value) bool { // match: (AtomicCompareAndSwap32 ptr old new_ mem) // cond: // result: (LoweredAtomicCas32 ptr old new_ mem) for { _ = v.Args[3] ptr := v.Args[0] old := v.Args[1] new_ := v.Args[2] mem := v.Args[3] v.reset(OpPPC64LoweredAtomicCas32) v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicCompareAndSwap64_0(v *Value) bool { // match: (AtomicCompareAndSwap64 ptr old new_ mem) // cond: // result: (LoweredAtomicCas64 ptr old new_ mem) for { _ = v.Args[3] ptr := v.Args[0] old := v.Args[1] new_ := v.Args[2] mem := v.Args[3] v.reset(OpPPC64LoweredAtomicCas64) v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicExchange32_0(v *Value) bool { // match: (AtomicExchange32 ptr val mem) // cond: // result: (LoweredAtomicExchange32 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicExchange32) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicExchange64_0(v *Value) bool { // match: (AtomicExchange64 ptr val mem) // cond: // result: (LoweredAtomicExchange64 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicExchange64) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoad32_0(v *Value) bool { // match: (AtomicLoad32 ptr mem) // cond: // result: (LoweredAtomicLoad32 ptr mem) for { _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64LoweredAtomicLoad32) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoad64_0(v *Value) bool { // match: (AtomicLoad64 ptr mem) // cond: // result: (LoweredAtomicLoad64 ptr mem) for { _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64LoweredAtomicLoad64) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoadPtr_0(v *Value) bool { // match: (AtomicLoadPtr ptr mem) // cond: // result: (LoweredAtomicLoadPtr ptr mem) for { _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64LoweredAtomicLoadPtr) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicOr8_0(v *Value) bool { // match: (AtomicOr8 ptr val mem) // cond: // result: (LoweredAtomicOr8 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicOr8) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicStore32_0(v *Value) bool { // match: (AtomicStore32 ptr val mem) // cond: // result: (LoweredAtomicStore32 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicStore32) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicStore64_0(v *Value) bool { // match: (AtomicStore64 ptr val mem) // cond: // result: (LoweredAtomicStore64 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicStore64) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAvg64u_0(v *Value) bool { b := v.Block _ = b // match: (Avg64u x y) // cond: // result: (ADD (SRDconst (SUB x y) [1]) y) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ADD) v0 := b.NewValue0(v.Pos, OpPPC64SRDconst, t) v0.AuxInt = 1 v1 := b.NewValue0(v.Pos, OpPPC64SUB, t) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) v.AddArg(y) return true } } func rewriteValuePPC64_OpBitLen32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (BitLen32 x) // cond: // result: (SUB (MOVDconst [32]) (CNTLZW x)) for { x := v.Args[0] v.reset(OpPPC64SUB) v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 32 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64CNTLZW, typ.Int) v1.AddArg(x) v.AddArg(v1) return true } } func rewriteValuePPC64_OpBitLen64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (BitLen64 x) // cond: // result: (SUB (MOVDconst [64]) (CNTLZD x)) for { x := v.Args[0] v.reset(OpPPC64SUB) v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 64 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64CNTLZD, typ.Int) v1.AddArg(x) v.AddArg(v1) return true } } func rewriteValuePPC64_OpCeil_0(v *Value) bool { // match: (Ceil x) // cond: // result: (FCEIL x) for { x := v.Args[0] v.reset(OpPPC64FCEIL) v.AddArg(x) return true } } func rewriteValuePPC64_OpClosureCall_0(v *Value) bool { // match: (ClosureCall [argwid] entry closure mem) // cond: // result: (CALLclosure [argwid] entry closure mem) for { argwid := v.AuxInt _ = v.Args[2] entry := v.Args[0] closure := v.Args[1] mem := v.Args[2] v.reset(OpPPC64CALLclosure) v.AuxInt = argwid v.AddArg(entry) v.AddArg(closure) v.AddArg(mem) return true } } func rewriteValuePPC64_OpCom16_0(v *Value) bool { // match: (Com16 x) // cond: // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCom32_0(v *Value) bool { // match: (Com32 x) // cond: // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCom64_0(v *Value) bool { // match: (Com64 x) // cond: // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCom8_0(v *Value) bool { // match: (Com8 x) // cond: // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpConst16_0(v *Value) bool { // match: (Const16 [val]) // cond: // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst32_0(v *Value) bool { // match: (Const32 [val]) // cond: // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst32F_0(v *Value) bool { // match: (Const32F [val]) // cond: // result: (FMOVSconst [val]) for { val := v.AuxInt v.reset(OpPPC64FMOVSconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst64_0(v *Value) bool { // match: (Const64 [val]) // cond: // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst64F_0(v *Value) bool { // match: (Const64F [val]) // cond: // result: (FMOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst8_0(v *Value) bool { // match: (Const8 [val]) // cond: // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConstBool_0(v *Value) bool { // match: (ConstBool [b]) // cond: // result: (MOVDconst [b]) for { b := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = b return true } } func rewriteValuePPC64_OpConstNil_0(v *Value) bool { // match: (ConstNil) // cond: // result: (MOVDconst [0]) for { v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } } func rewriteValuePPC64_OpConvert_0(v *Value) bool { // match: (Convert x mem) // cond: // result: (MOVDconvert x mem) for { t := v.Type _ = v.Args[1] x := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVDconvert) v.Type = t v.AddArg(x) v.AddArg(mem) return true } } func rewriteValuePPC64_OpCopysign_0(v *Value) bool { // match: (Copysign x y) // cond: // result: (FCPSGN y x) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FCPSGN) v.AddArg(y) v.AddArg(x) return true } } func rewriteValuePPC64_OpCtz32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Ctz32 x) // cond: // result: (POPCNTW (MOVWZreg (ANDN (ADDconst [-1] x) x))) for { x := v.Args[0] v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZreg, typ.Int64) v1 := b.NewValue0(v.Pos, OpPPC64ANDN, typ.Int) v2 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.Int) v2.AuxInt = -1 v2.AddArg(x) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCtz64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Ctz64 x) // cond: // result: (POPCNTD (ANDN (ADDconst [-1] x) x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTD) v0 := b.NewValue0(v.Pos, OpPPC64ANDN, typ.Int64) v1 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.Int64) v1.AuxInt = -1 v1.AddArg(x) v0.AddArg(v1) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32Fto32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt32Fto32 x) // cond: // result: (MFVSRD (FCTIWZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIWZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32Fto64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt32Fto64 x) // cond: // result: (MFVSRD (FCTIDZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIDZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32Fto64F_0(v *Value) bool { // match: (Cvt32Fto64F x) // cond: // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValuePPC64_OpCvt32to32F_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt32to32F x) // cond: // result: (FCFIDS (MTVSRD (SignExt32to64 x))) for { x := v.Args[0] v.reset(OpPPC64FCFIDS) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32to64F_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt32to64F x) // cond: // result: (FCFID (MTVSRD (SignExt32to64 x))) for { x := v.Args[0] v.reset(OpPPC64FCFID) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64Fto32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt64Fto32 x) // cond: // result: (MFVSRD (FCTIWZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIWZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64Fto32F_0(v *Value) bool { // match: (Cvt64Fto32F x) // cond: // result: (FRSP x) for { x := v.Args[0] v.reset(OpPPC64FRSP) v.AddArg(x) return true } } func rewriteValuePPC64_OpCvt64Fto64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt64Fto64 x) // cond: // result: (MFVSRD (FCTIDZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIDZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64to32F_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt64to32F x) // cond: // result: (FCFIDS (MTVSRD x)) for { x := v.Args[0] v.reset(OpPPC64FCFIDS) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64to64F_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt64to64F x) // cond: // result: (FCFID (MTVSRD x)) for { x := v.Args[0] v.reset(OpPPC64FCFID) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpDiv16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Div16 x y) // cond: // result: (DIVW (SignExt16to32 x) (SignExt16to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpDiv16u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Div16u x y) // cond: // result: (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVWU) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpDiv32_0(v *Value) bool { // match: (Div32 x y) // cond: // result: (DIVW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv32F_0(v *Value) bool { // match: (Div32F x y) // cond: // result: (FDIVS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FDIVS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv32u_0(v *Value) bool { // match: (Div32u x y) // cond: // result: (DIVWU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVWU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv64_0(v *Value) bool { // match: (Div64 x y) // cond: // result: (DIVD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv64F_0(v *Value) bool { // match: (Div64F x y) // cond: // result: (FDIV x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FDIV) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv64u_0(v *Value) bool { // match: (Div64u x y) // cond: // result: (DIVDU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVDU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Div8 x y) // cond: // result: (DIVW (SignExt8to32 x) (SignExt8to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpDiv8u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Div8u x y) // cond: // result: (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVWU) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpEq16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Eq16 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Eq16 x y) // cond: // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq32_0(v *Value) bool { b := v.Block _ = b // match: (Eq32 x y) // cond: // result: (Equal (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq32F_0(v *Value) bool { b := v.Block _ = b // match: (Eq32F x y) // cond: // result: (Equal (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq64_0(v *Value) bool { b := v.Block _ = b // match: (Eq64 x y) // cond: // result: (Equal (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq64F_0(v *Value) bool { b := v.Block _ = b // match: (Eq64F x y) // cond: // result: (Equal (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Eq8 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Eq8 x y) // cond: // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEqB_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (EqB x y) // cond: // result: (ANDconst [1] (EQV x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ANDconst) v.AuxInt = 1 v0 := b.NewValue0(v.Pos, OpPPC64EQV, typ.Int64) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEqPtr_0(v *Value) bool { b := v.Block _ = b // match: (EqPtr x y) // cond: // result: (Equal (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpFloor_0(v *Value) bool { // match: (Floor x) // cond: // result: (FFLOOR x) for { x := v.Args[0] v.reset(OpPPC64FFLOOR) v.AddArg(x) return true } } func rewriteValuePPC64_OpGeq16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Geq16 x y) // cond: // result: (GreaterEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq16U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Geq16U x y) // cond: // result: (GreaterEqual (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq32_0(v *Value) bool { b := v.Block _ = b // match: (Geq32 x y) // cond: // result: (GreaterEqual (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq32F_0(v *Value) bool { b := v.Block _ = b // match: (Geq32F x y) // cond: // result: (FGreaterEqual (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FGreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq32U_0(v *Value) bool { b := v.Block _ = b // match: (Geq32U x y) // cond: // result: (GreaterEqual (CMPWU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq64_0(v *Value) bool { b := v.Block _ = b // match: (Geq64 x y) // cond: // result: (GreaterEqual (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq64F_0(v *Value) bool { b := v.Block _ = b // match: (Geq64F x y) // cond: // result: (FGreaterEqual (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FGreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq64U_0(v *Value) bool { b := v.Block _ = b // match: (Geq64U x y) // cond: // result: (GreaterEqual (CMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Geq8 x y) // cond: // result: (GreaterEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq8U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Geq8U x y) // cond: // result: (GreaterEqual (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGetCallerSP_0(v *Value) bool { // match: (GetCallerSP) // cond: // result: (LoweredGetCallerSP) for { v.reset(OpPPC64LoweredGetCallerSP) return true } } func rewriteValuePPC64_OpGetClosurePtr_0(v *Value) bool { // match: (GetClosurePtr) // cond: // result: (LoweredGetClosurePtr) for { v.reset(OpPPC64LoweredGetClosurePtr) return true } } func rewriteValuePPC64_OpGreater16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Greater16 x y) // cond: // result: (GreaterThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater16U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Greater16U x y) // cond: // result: (GreaterThan (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater32_0(v *Value) bool { b := v.Block _ = b // match: (Greater32 x y) // cond: // result: (GreaterThan (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater32F_0(v *Value) bool { b := v.Block _ = b // match: (Greater32F x y) // cond: // result: (FGreaterThan (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FGreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater32U_0(v *Value) bool { b := v.Block _ = b // match: (Greater32U x y) // cond: // result: (GreaterThan (CMPWU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater64_0(v *Value) bool { b := v.Block _ = b // match: (Greater64 x y) // cond: // result: (GreaterThan (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater64F_0(v *Value) bool { b := v.Block _ = b // match: (Greater64F x y) // cond: // result: (FGreaterThan (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FGreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater64U_0(v *Value) bool { b := v.Block _ = b // match: (Greater64U x y) // cond: // result: (GreaterThan (CMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Greater8 x y) // cond: // result: (GreaterThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater8U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Greater8U x y) // cond: // result: (GreaterThan (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpHmul32_0(v *Value) bool { // match: (Hmul32 x y) // cond: // result: (MULHW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULHW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpHmul32u_0(v *Value) bool { // match: (Hmul32u x y) // cond: // result: (MULHWU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULHWU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpHmul64_0(v *Value) bool { // match: (Hmul64 x y) // cond: // result: (MULHD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULHD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpHmul64u_0(v *Value) bool { // match: (Hmul64u x y) // cond: // result: (MULHDU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULHDU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpInterCall_0(v *Value) bool { // match: (InterCall [argwid] entry mem) // cond: // result: (CALLinter [argwid] entry mem) for { argwid := v.AuxInt _ = v.Args[1] entry := v.Args[0] mem := v.Args[1] v.reset(OpPPC64CALLinter) v.AuxInt = argwid v.AddArg(entry) v.AddArg(mem) return true } } func rewriteValuePPC64_OpIsInBounds_0(v *Value) bool { b := v.Block _ = b // match: (IsInBounds idx len) // cond: // result: (LessThan (CMPU idx len)) for { _ = v.Args[1] idx := v.Args[0] len := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValuePPC64_OpIsNonNil_0(v *Value) bool { b := v.Block _ = b // match: (IsNonNil ptr) // cond: // result: (NotEqual (CMPconst [0] ptr)) for { ptr := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(ptr) v.AddArg(v0) return true } } func rewriteValuePPC64_OpIsSliceInBounds_0(v *Value) bool { b := v.Block _ = b // match: (IsSliceInBounds idx len) // cond: // result: (LessEqual (CMPU idx len)) for { _ = v.Args[1] idx := v.Args[0] len := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Leq16 x y) // cond: // result: (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq16U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Leq16U x y) // cond: // result: (LessEqual (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq32_0(v *Value) bool { b := v.Block _ = b // match: (Leq32 x y) // cond: // result: (LessEqual (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq32F_0(v *Value) bool { b := v.Block _ = b // match: (Leq32F x y) // cond: // result: (FLessEqual (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FLessEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq32U_0(v *Value) bool { b := v.Block _ = b // match: (Leq32U x y) // cond: // result: (LessEqual (CMPWU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq64_0(v *Value) bool { b := v.Block _ = b // match: (Leq64 x y) // cond: // result: (LessEqual (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq64F_0(v *Value) bool { b := v.Block _ = b // match: (Leq64F x y) // cond: // result: (FLessEqual (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FLessEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq64U_0(v *Value) bool { b := v.Block _ = b // match: (Leq64U x y) // cond: // result: (LessEqual (CMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Leq8 x y) // cond: // result: (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq8U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Leq8U x y) // cond: // result: (LessEqual (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Less16 x y) // cond: // result: (LessThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess16U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Less16U x y) // cond: // result: (LessThan (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess32_0(v *Value) bool { b := v.Block _ = b // match: (Less32 x y) // cond: // result: (LessThan (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess32F_0(v *Value) bool { b := v.Block _ = b // match: (Less32F x y) // cond: // result: (FLessThan (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FLessThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess32U_0(v *Value) bool { b := v.Block _ = b // match: (Less32U x y) // cond: // result: (LessThan (CMPWU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess64_0(v *Value) bool { b := v.Block _ = b // match: (Less64 x y) // cond: // result: (LessThan (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess64F_0(v *Value) bool { b := v.Block _ = b // match: (Less64F x y) // cond: // result: (FLessThan (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FLessThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess64U_0(v *Value) bool { b := v.Block _ = b // match: (Less64U x y) // cond: // result: (LessThan (CMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Less8 x y) // cond: // result: (LessThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess8U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Less8U x y) // cond: // result: (LessThan (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLoad_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVDload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpPPC64MOVDload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) && isSigned(t) // result: (MOVWload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is32BitInt(t) && isSigned(t)) { break } v.reset(OpPPC64MOVWload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) && !isSigned(t) // result: (MOVWZload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is32BitInt(t) && !isSigned(t)) { break } v.reset(OpPPC64MOVWZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) && isSigned(t) // result: (MOVHload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is16BitInt(t) && isSigned(t)) { break } v.reset(OpPPC64MOVHload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) && !isSigned(t) // result: (MOVHZload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is16BitInt(t) && !isSigned(t)) { break } v.reset(OpPPC64MOVHZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: t.IsBoolean() // result: (MOVBZload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(t.IsBoolean()) { break } v.reset(OpPPC64MOVBZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is8BitInt(t) && isSigned(t) // result: (MOVBreg (MOVBZload ptr mem)) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is8BitInt(t) && isSigned(t)) { break } v.reset(OpPPC64MOVBreg) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Load ptr mem) // cond: is8BitInt(t) && !isSigned(t) // result: (MOVBZload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is8BitInt(t) && !isSigned(t)) { break } v.reset(OpPPC64MOVBZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (FMOVSload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is32BitFloat(t)) { break } v.reset(OpPPC64FMOVSload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (FMOVDload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is64BitFloat(t)) { break } v.reset(OpPPC64FMOVDload) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpLsh16x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh16x16 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh16x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh16x32 x (Const64 [c])) // cond: uint32(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x32 x (MOVDconst [c])) // cond: uint32(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x32 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh16x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh16x64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh16x64 x (MOVDconst [c])) // cond: uint64(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x64 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh16x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh16x8 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh32x16 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh32x32 x (Const64 [c])) // cond: uint32(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x32 x (MOVDconst [c])) // cond: uint32(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x32 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh32x64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh32x64 x (MOVDconst [c])) // cond: uint64(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x64 x (AND y (MOVDconst [31]))) // cond: // result: (SLW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst { break } if v_1_1.AuxInt != 31 { break } v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh32x64 x (AND (MOVDconst [31]) y)) // cond: // result: (SLW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 31 { break } y := v_1.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh32x64 x (ANDconst [31] y)) // cond: // result: (SLW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst { break } if v_1.Type != typ.Int32 { break } if v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh32x64 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh32x8 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh64x16 x y) // cond: // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh64x32 x (Const64 [c])) // cond: uint32(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x32 x (MOVDconst [c])) // cond: uint32(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x32 x y) // cond: // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh64x64 x (Const64 [c])) // cond: uint64(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh64x64 x (MOVDconst [c])) // cond: uint64(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x64 x (AND y (MOVDconst [63]))) // cond: // result: (SLD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst { break } if v_1_1.AuxInt != 63 { break } v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh64x64 x (AND (MOVDconst [63]) y)) // cond: // result: (SLD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 63 { break } y := v_1.Args[1] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh64x64 x (ANDconst [63] y)) // cond: // result: (SLD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst { break } if v_1.Type != typ.Int64 { break } if v_1.AuxInt != 63 { break } y := v_1.Args[0] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh64x64 x y) // cond: // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh64x8 x y) // cond: // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh8x16 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh8x32 x (Const64 [c])) // cond: uint32(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x32 x (MOVDconst [c])) // cond: uint32(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x32 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh8x64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh8x64 x (MOVDconst [c])) // cond: uint64(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x64 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh8x8 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod16 x y) // cond: // result: (Mod32 (SignExt16to32 x) (SignExt16to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpMod32) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMod16u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod16u x y) // cond: // result: (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpMod32u) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMod32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod32 x y) // cond: // result: (SUB x (MULLW y (DIVW x y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLW, typ.Int32) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVW, typ.Int32) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod32u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod32u x y) // cond: // result: (SUB x (MULLW y (DIVWU x y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLW, typ.Int32) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVWU, typ.Int32) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod64 x y) // cond: // result: (SUB x (MULLD y (DIVD x y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLD, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVD, typ.Int64) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod64u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod64u x y) // cond: // result: (SUB x (MULLD y (DIVDU x y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLD, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVDU, typ.Int64) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod8 x y) // cond: // result: (Mod32 (SignExt8to32 x) (SignExt8to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpMod32) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMod8u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod8u x y) // cond: // result: (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpMod32u) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMove_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Move [0] _ _ mem) // cond: // result: mem for { if v.AuxInt != 0 { break } _ = v.Args[2] mem := v.Args[2] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Move [1] dst src mem) // cond: // result: (MOVBstore dst (MOVBZload src mem) mem) for { if v.AuxInt != 1 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVBstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [2] dst src mem) // cond: // result: (MOVHstore dst (MOVHZload src mem) mem) for { if v.AuxInt != 2 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVHstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [4] dst src mem) // cond: // result: (MOVWstore dst (MOVWZload src mem) mem) for { if v.AuxInt != 4 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVWstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [8] {t} dst src mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstore dst (MOVDload src mem) mem) for { if v.AuxInt != 8 { break } t := v.Aux _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, typ.Int64) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [8] dst src mem) // cond: // result: (MOVWstore [4] dst (MOVWZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem)) for { if v.AuxInt != 8 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVWstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [3] dst src mem) // cond: // result: (MOVBstore [2] dst (MOVBZload [2] src mem) (MOVHstore dst (MOVHload src mem) mem)) for { if v.AuxInt != 3 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVBstore) v.AuxInt = 2 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AuxInt = 2 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVHstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVHload, typ.Int16) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [5] dst src mem) // cond: // result: (MOVBstore [4] dst (MOVBZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem)) for { if v.AuxInt != 5 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVBstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [6] dst src mem) // cond: // result: (MOVHstore [4] dst (MOVHZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem)) for { if v.AuxInt != 6 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVHstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [7] dst src mem) // cond: // result: (MOVBstore [6] dst (MOVBZload [6] src mem) (MOVHstore [4] dst (MOVHZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem))) for { if v.AuxInt != 7 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVBstore) v.AuxInt = 6 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AuxInt = 6 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVHstore, types.TypeMem) v1.AuxInt = 4 v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16) v2.AuxInt = 4 v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v3.AddArg(dst) v4 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v4.AddArg(src) v4.AddArg(mem) v3.AddArg(v4) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } return false } func rewriteValuePPC64_OpMove_10(v *Value) bool { // match: (Move [s] dst src mem) // cond: s > 8 // result: (LoweredMove [s] dst src mem) for { s := v.AuxInt _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] if !(s > 8) { break } v.reset(OpPPC64LoweredMove) v.AuxInt = s v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpMul16_0(v *Value) bool { // match: (Mul16 x y) // cond: // result: (MULLW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul32_0(v *Value) bool { // match: (Mul32 x y) // cond: // result: (MULLW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul32F_0(v *Value) bool { // match: (Mul32F x y) // cond: // result: (FMULS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FMULS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul64_0(v *Value) bool { // match: (Mul64 x y) // cond: // result: (MULLD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULLD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul64F_0(v *Value) bool { // match: (Mul64F x y) // cond: // result: (FMUL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FMUL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul8_0(v *Value) bool { // match: (Mul8 x y) // cond: // result: (MULLW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpNeg16_0(v *Value) bool { // match: (Neg16 x) // cond: // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg32_0(v *Value) bool { // match: (Neg32 x) // cond: // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg32F_0(v *Value) bool { // match: (Neg32F x) // cond: // result: (FNEG x) for { x := v.Args[0] v.reset(OpPPC64FNEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg64_0(v *Value) bool { // match: (Neg64 x) // cond: // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg64F_0(v *Value) bool { // match: (Neg64F x) // cond: // result: (FNEG x) for { x := v.Args[0] v.reset(OpPPC64FNEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg8_0(v *Value) bool { // match: (Neg8 x) // cond: // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeq16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Neq16 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Neq16 x y) // cond: // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq32_0(v *Value) bool { b := v.Block _ = b // match: (Neq32 x y) // cond: // result: (NotEqual (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq32F_0(v *Value) bool { b := v.Block _ = b // match: (Neq32F x y) // cond: // result: (NotEqual (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq64_0(v *Value) bool { b := v.Block _ = b // match: (Neq64 x y) // cond: // result: (NotEqual (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq64F_0(v *Value) bool { b := v.Block _ = b // match: (Neq64F x y) // cond: // result: (NotEqual (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Neq8 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Neq8 x y) // cond: // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeqB_0(v *Value) bool { // match: (NeqB x y) // cond: // result: (XOR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpNeqPtr_0(v *Value) bool { b := v.Block _ = b // match: (NeqPtr x y) // cond: // result: (NotEqual (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNilCheck_0(v *Value) bool { // match: (NilCheck ptr mem) // cond: // result: (LoweredNilCheck ptr mem) for { _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64LoweredNilCheck) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpNot_0(v *Value) bool { // match: (Not x) // cond: // result: (XORconst [1] x) for { x := v.Args[0] v.reset(OpPPC64XORconst) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValuePPC64_OpOffPtr_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (OffPtr [off] ptr) // cond: // result: (ADD (MOVDconst [off]) ptr) for { off := v.AuxInt ptr := v.Args[0] v.reset(OpPPC64ADD) v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = off v.AddArg(v0) v.AddArg(ptr) return true } } func rewriteValuePPC64_OpOr16_0(v *Value) bool { // match: (Or16 x y) // cond: // result: (OR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOr32_0(v *Value) bool { // match: (Or32 x y) // cond: // result: (OR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOr64_0(v *Value) bool { // match: (Or64 x y) // cond: // result: (OR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOr8_0(v *Value) bool { // match: (Or8 x y) // cond: // result: (OR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOrB_0(v *Value) bool { // match: (OrB x y) // cond: // result: (OR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpPPC64ADD_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (ADD (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLDconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (SRDconst x [d]) (SLDconst x [c])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLDconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLWconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (SRWconst x [d]) (SLWconst x [c])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLWconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // cond: // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst { break } if v_0_1.Type != typ.Int64 { break } if v_0_1.AuxInt != 63 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 64 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst { break } if v_1_1_1.Type != typ.UInt { break } if v_1_1_1.AuxInt != 63 { break } if y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (ADD (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) // cond: // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB { break } if v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst { break } if v_0_1_0.AuxInt != 64 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst { break } if v_0_1_1.Type != typ.UInt { break } if v_0_1_1.AuxInt != 63 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.Int64 { break } if v_1_1.AuxInt != 63 { break } if y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (ADD (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // cond: // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst { break } if v_0_1.Type != typ.Int32 { break } if v_0_1.AuxInt != 31 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 32 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst { break } if v_1_1_1.Type != typ.UInt { break } if v_1_1_1.AuxInt != 31 { break } if y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (ADD (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) // cond: // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB { break } if v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst { break } if v_0_1_0.AuxInt != 32 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst { break } if v_0_1_1.Type != typ.UInt { break } if v_0_1_1.AuxInt != 31 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.Int32 { break } if v_1_1.AuxInt != 31 { break } if y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (ADD x (MOVDconst [c])) // cond: is32Bit(c) // result: (ADDconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (MOVDconst [c]) x) // cond: is32Bit(c) // result: (ADDconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt x := v.Args[1] if !(is32Bit(c)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ADDconst_0(v *Value) bool { // match: (ADDconst [c] (ADDconst [d] x)) // cond: is32Bit(c+d) // result: (ADDconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = c + d v.AddArg(x) return true } // match: (ADDconst [0] x) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDconst [c] (MOVDaddr [d] {sym} x)) // cond: // result: (MOVDaddr [c+d] {sym} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDaddr { break } d := v_0.AuxInt sym := v_0.Aux x := v_0.Args[0] v.reset(OpPPC64MOVDaddr) v.AuxInt = c + d v.Aux = sym v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64AND_0(v *Value) bool { // match: (AND x (NOR y y)) // cond: // result: (ANDN x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64NOR { break } _ = v_1.Args[1] y := v_1.Args[0] if y != v_1.Args[1] { break } v.reset(OpPPC64ANDN) v.AddArg(x) v.AddArg(y) return true } // match: (AND (NOR y y) x) // cond: // result: (ANDN x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64NOR { break } _ = v_0.Args[1] y := v_0.Args[0] if y != v_0.Args[1] { break } x := v.Args[1] v.reset(OpPPC64ANDN) v.AddArg(x) v.AddArg(y) return true } // match: (AND (MOVDconst [c]) (MOVDconst [d])) // cond: // result: (MOVDconst [c&d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } d := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c & d return true } // match: (AND (MOVDconst [d]) (MOVDconst [c])) // cond: // result: (MOVDconst [c&d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c & d return true } // match: (AND x (MOVDconst [c])) // cond: isU16Bit(c) // result: (ANDconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64ANDconst) v.AuxInt = c v.AddArg(x) return true } // match: (AND (MOVDconst [c]) x) // cond: isU16Bit(c) // result: (ANDconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt x := v.Args[1] if !(isU16Bit(c)) { break } v.reset(OpPPC64ANDconst) v.AuxInt = c v.AddArg(x) return true } // match: (AND (MOVDconst [c]) x:(MOVBZload _ _)) // cond: // result: (ANDconst [c&0xFF] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt x := v.Args[1] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } // match: (AND x:(MOVBZload _ _) (MOVDconst [c])) // cond: // result: (ANDconst [c&0xFF] x) for { _ = v.Args[1] x := v.Args[0] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } // match: (AND x:(MOVBZload _ _) (MOVDconst [c])) // cond: // result: (ANDconst [c&0xFF] x) for { _ = v.Args[1] x := v.Args[0] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } // match: (AND (MOVDconst [c]) x:(MOVBZload _ _)) // cond: // result: (ANDconst [c&0xFF] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt x := v.Args[1] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ANDconst_0(v *Value) bool { // match: (ANDconst [c] (ANDconst [d] x)) // cond: // result: (ANDconst [c&d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64ANDconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDconst [-1] x) // cond: // result: x for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDconst [0] _) // cond: // result: (MOVDconst [0]) for { if v.AuxInt != 0 { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ANDconst [c] y:(MOVBZreg _)) // cond: c&0xFF == 0xFF // result: y for { c := v.AuxInt y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } if !(c&0xFF == 0xFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [c] y:(MOVHZreg _)) // cond: c&0xFFFF == 0xFFFF // result: y for { c := v.AuxInt y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } if !(c&0xFFFF == 0xFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [c] y:(MOVWZreg _)) // cond: c&0xFFFFFFFF == 0xFFFFFFFF // result: y for { c := v.AuxInt y := v.Args[0] if y.Op != OpPPC64MOVWZreg { break } if !(c&0xFFFFFFFF == 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [c] (MOVBZreg x)) // cond: // result: (ANDconst [c&0xFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBZreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } // match: (ANDconst [c] (MOVHZreg x)) // cond: // result: (ANDconst [c&0xFFFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVHZreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFFFF v.AddArg(x) return true } // match: (ANDconst [c] (MOVWZreg x)) // cond: // result: (ANDconst [c&0xFFFFFFFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWZreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFFFFFFFF v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64CMP_0(v *Value) bool { b := v.Block _ = b // match: (CMP x (MOVDconst [c])) // cond: is16Bit(c) // result: (CMPconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64CMPconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMP (MOVDconst [c]) y) // cond: is16Bit(c) // result: (InvertFlags (CMPconst y [c])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt y := v.Args[1] if !(is16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPU_0(v *Value) bool { b := v.Block _ = b // match: (CMPU x (MOVDconst [c])) // cond: isU16Bit(c) // result: (CMPUconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64CMPUconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPU (MOVDconst [c]) y) // cond: isU16Bit(c) // result: (InvertFlags (CMPUconst y [c])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt y := v.Args[1] if !(isU16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPUconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPUconst_0(v *Value) bool { // match: (CMPUconst (MOVDconst [x]) [y]) // cond: int64(x)==int64(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int64(x) == int64(y)) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPUconst (MOVDconst [x]) [y]) // cond: uint64(x)uint64(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(uint64(x) > uint64(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64CMPW_0(v *Value) bool { b := v.Block _ = b // match: (CMPW x (MOVWreg y)) // cond: // result: (CMPW x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } y := v_1.Args[0] v.reset(OpPPC64CMPW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPW (MOVWreg x) y) // cond: // result: (CMPW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWreg { break } x := v_0.Args[0] y := v.Args[1] v.reset(OpPPC64CMPW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPW x (MOVDconst [c])) // cond: is16Bit(c) // result: (CMPWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64CMPWconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPW (MOVDconst [c]) y) // cond: is16Bit(c) // result: (InvertFlags (CMPWconst y [c])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt y := v.Args[1] if !(is16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPWconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPWU_0(v *Value) bool { b := v.Block _ = b // match: (CMPWU x (MOVWZreg y)) // cond: // result: (CMPWU x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } y := v_1.Args[0] v.reset(OpPPC64CMPWU) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWU (MOVWZreg x) y) // cond: // result: (CMPWU x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWZreg { break } x := v_0.Args[0] y := v.Args[1] v.reset(OpPPC64CMPWU) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWU x (MOVDconst [c])) // cond: isU16Bit(c) // result: (CMPWUconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64CMPWUconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPWU (MOVDconst [c]) y) // cond: isU16Bit(c) // result: (InvertFlags (CMPWUconst y [c])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt y := v.Args[1] if !(isU16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPWUconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPWUconst_0(v *Value) bool { // match: (CMPWUconst (MOVDconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPWUconst (MOVDconst [x]) [y]) // cond: uint32(x)uint32(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(uint32(x) > uint32(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64CMPWconst_0(v *Value) bool { // match: (CMPWconst (MOVDconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPWconst (MOVDconst [x]) [y]) // cond: int32(x)int32(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int32(x) > int32(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64CMPconst_0(v *Value) bool { // match: (CMPconst (MOVDconst [x]) [y]) // cond: int64(x)==int64(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int64(x) == int64(y)) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPconst (MOVDconst [x]) [y]) // cond: int64(x)int64(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int64(x) > int64(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64Equal_0(v *Value) bool { // match: (Equal (FlagEQ)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (Equal (FlagLT)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Equal (FlagGT)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Equal (InvertFlags x)) // cond: // result: (Equal x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64Equal) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64FABS_0(v *Value) bool { // match: (FABS (FMOVDconst [x])) // cond: // result: (FMOVDconst [f2i(math.Abs(i2f(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = f2i(math.Abs(i2f(x))) return true } return false } func rewriteValuePPC64_OpPPC64FADD_0(v *Value) bool { // match: (FADD (FMUL x y) z) // cond: // result: (FMADD x y z) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMUL { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] z := v.Args[1] v.reset(OpPPC64FMADD) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } // match: (FADD z (FMUL x y)) // cond: // result: (FMADD x y z) for { _ = v.Args[1] z := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64FMUL { break } _ = v_1.Args[1] x := v_1.Args[0] y := v_1.Args[1] v.reset(OpPPC64FMADD) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FADDS_0(v *Value) bool { // match: (FADDS (FMULS x y) z) // cond: // result: (FMADDS x y z) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMULS { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] z := v.Args[1] v.reset(OpPPC64FMADDS) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } // match: (FADDS z (FMULS x y)) // cond: // result: (FMADDS x y z) for { _ = v.Args[1] z := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64FMULS { break } _ = v_1.Args[1] x := v_1.Args[0] y := v_1.Args[1] v.reset(OpPPC64FMADDS) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FCEIL_0(v *Value) bool { // match: (FCEIL (FMOVDconst [x])) // cond: // result: (FMOVDconst [f2i(math.Ceil(i2f(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = f2i(math.Ceil(i2f(x))) return true } return false } func rewriteValuePPC64_OpPPC64FFLOOR_0(v *Value) bool { // match: (FFLOOR (FMOVDconst [x])) // cond: // result: (FMOVDconst [f2i(math.Floor(i2f(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = f2i(math.Floor(i2f(x))) return true } return false } func rewriteValuePPC64_OpPPC64FMOVDload_0(v *Value) bool { // match: (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr x _)) // cond: // result: (MTVSRD x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDstore { break } if v_1.AuxInt != off { break } if v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } x := v_1.Args[1] v.reset(OpPPC64MTVSRD) v.AddArg(x) return true } // match: (FMOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is16Bit(off1+off2) // result: (FMOVDload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FMOVDstore_0(v *Value) bool { // match: (FMOVDstore [off] {sym} ptr (MTVSRD x) mem) // cond: // result: (MOVDstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MTVSRD { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVDstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is16Bit(off1+off2) // result: (FMOVDstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (FMOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] mem := v.Args[2] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FMOVSload_0(v *Value) bool { // match: (FMOVSload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is16Bit(off1+off2) // result: (FMOVSload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FMOVSstore_0(v *Value) bool { // match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is16Bit(off1+off2) // result: (FMOVSstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVSstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (FMOVSstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] mem := v.Args[2] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVSstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FNEG_0(v *Value) bool { // match: (FNEG (FABS x)) // cond: // result: (FNABS x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FABS { break } x := v_0.Args[0] v.reset(OpPPC64FNABS) v.AddArg(x) return true } // match: (FNEG (FNABS x)) // cond: // result: (FABS x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FNABS { break } x := v_0.Args[0] v.reset(OpPPC64FABS) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64FSQRT_0(v *Value) bool { // match: (FSQRT (FMOVDconst [x])) // cond: // result: (FMOVDconst [f2i(math.Sqrt(i2f(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = f2i(math.Sqrt(i2f(x))) return true } return false } func rewriteValuePPC64_OpPPC64FSUB_0(v *Value) bool { // match: (FSUB (FMUL x y) z) // cond: // result: (FMSUB x y z) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMUL { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] z := v.Args[1] v.reset(OpPPC64FMSUB) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FSUBS_0(v *Value) bool { // match: (FSUBS (FMULS x y) z) // cond: // result: (FMSUBS x y z) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMULS { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] z := v.Args[1] v.reset(OpPPC64FMSUBS) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FTRUNC_0(v *Value) bool { // match: (FTRUNC (FMOVDconst [x])) // cond: // result: (FMOVDconst [f2i(math.Trunc(i2f(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = f2i(math.Trunc(i2f(x))) return true } return false } func rewriteValuePPC64_OpPPC64GreaterEqual_0(v *Value) bool { // match: (GreaterEqual (FlagEQ)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (GreaterEqual (FlagLT)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (GreaterEqual (FlagGT)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (GreaterEqual (InvertFlags x)) // cond: // result: (LessEqual x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64LessEqual) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64GreaterThan_0(v *Value) bool { // match: (GreaterThan (FlagEQ)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (GreaterThan (FlagLT)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (GreaterThan (FlagGT)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (GreaterThan (InvertFlags x)) // cond: // result: (LessThan x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64LessThan) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64LessEqual_0(v *Value) bool { // match: (LessEqual (FlagEQ)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (LessEqual (FlagLT)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (LessEqual (FlagGT)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (LessEqual (InvertFlags x)) // cond: // result: (GreaterEqual x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64GreaterEqual) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64LessThan_0(v *Value) bool { // match: (LessThan (FlagEQ)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (LessThan (FlagLT)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (LessThan (FlagGT)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (LessThan (InvertFlags x)) // cond: // result: (GreaterThan x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64GreaterThan) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MFVSRD_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (MFVSRD (FMOVDconst [c])) // cond: // result: (MOVDconst [c]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c return true } // match: (MFVSRD x:(FMOVDload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVDload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpPPC64FMOVDload { break } off := x.AuxInt sym := x.Aux _ = x.Args[1] ptr := x.Args[0] mem := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, typ.Int64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBZload_0(v *Value) bool { // match: (MOVBZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVBZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVBZload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBZload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVBZload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVBZload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBZreg_0(v *Value) bool { // match: (MOVBZreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBZreg y:(MOVBZreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBZreg (MOVBreg x)) // cond: // result: (MOVBZreg x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBreg { break } x := v_0.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } // match: (MOVBZreg x:(MOVBZload _ _)) // cond: // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVBZreg (MOVDconst [c])) // cond: // result: (MOVDconst [int64(uint8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(uint8(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVBreg_0(v *Value) bool { // match: (MOVBreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0x7F // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0x7F) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBreg y:(MOVBreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBreg (MOVBZreg x)) // cond: // result: (MOVBreg x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBZreg { break } x := v_0.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } // match: (MOVBreg (MOVDconst [c])) // cond: // result: (MOVDconst [int64(int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(int8(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstore_0(v *Value) bool { // match: (MOVBstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] mem := v.Args[2] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVDconst [c]) mem) // cond: c == 0 // result: (MOVBstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt mem := v.Args[2] if !(c == 0) { break } v.reset(OpPPC64MOVBstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem) // cond: // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVBreg { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBZreg x) mem) // cond: // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVBZreg { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstorezero_0(v *Value) bool { // match: (MOVBstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVBstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVBstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVBstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDload_0(v *Value) bool { // match: (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr x _)) // cond: // result: (MFVSRD x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64FMOVDstore { break } if v_1.AuxInt != off { break } if v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } x := v_1.Args[1] v.reset(OpPPC64MFVSRD) v.AddArg(x) return true } // match: (MOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVDload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVDload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDstore_0(v *Value) bool { // match: (MOVDstore [off] {sym} ptr (MFVSRD x) mem) // cond: // result: (FMOVDstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MFVSRD { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64FMOVDstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVDstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVDstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] mem := v.Args[2] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVDstore [off] {sym} ptr (MOVDconst [c]) mem) // cond: c == 0 // result: (MOVDstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt mem := v.Args[2] if !(c == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDstorezero_0(v *Value) bool { // match: (MOVDstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVDstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVDstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHZload_0(v *Value) bool { // match: (MOVHZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVHZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHZload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHZload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVHZload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHZload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHZreg_0(v *Value) bool { // match: (MOVHZreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg y:(MOVHZreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg y:(MOVBZreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg y:(MOVHreg x)) // cond: // result: (MOVHZreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } x := y.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } // match: (MOVHZreg x:(MOVHZload _ _)) // cond: // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHZreg (MOVDconst [c])) // cond: // result: (MOVDconst [int64(uint16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(uint16(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVHload_0(v *Value) bool { // match: (MOVHload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVHload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHreg_0(v *Value) bool { // match: (MOVHreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0x7FFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0x7FFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHreg y:(MOVHreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHreg y:(MOVBreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHreg y:(MOVHZreg x)) // cond: // result: (MOVHreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } x := y.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHload _ _)) // cond: // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHreg (MOVDconst [c])) // cond: // result: (MOVDconst [int64(int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(int16(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVHstore_0(v *Value) bool { // match: (MOVHstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVHstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] mem := v.Args[2] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVDconst [c]) mem) // cond: c == 0 // result: (MOVHstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt mem := v.Args[2] if !(c == 0) { break } v.reset(OpPPC64MOVHstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem) // cond: // result: (MOVHstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHreg { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVHstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHZreg x) mem) // cond: // result: (MOVHstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHZreg { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVHstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHstorezero_0(v *Value) bool { // match: (MOVHstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVHstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZload_0(v *Value) bool { // match: (MOVWZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVWZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWZload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWZload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVWZload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWZload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZreg_0(v *Value) bool { // match: (MOVWZreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFFFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(AND (MOVDconst [c]) _)) // cond: uint64(c) <= 0xFFFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] y_0 := y.Args[0] if y_0.Op != OpPPC64MOVDconst { break } c := y_0.AuxInt if !(uint64(c) <= 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(AND _ (MOVDconst [c]))) // cond: uint64(c) <= 0xFFFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] y_1 := y.Args[1] if y_1.Op != OpPPC64MOVDconst { break } c := y_1.AuxInt if !(uint64(c) <= 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVWZreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVWZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVHZreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVBZreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVWreg x)) // cond: // result: (MOVWZreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVWreg { break } x := y.Args[0] v.reset(OpPPC64MOVWZreg) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MOVWload_0(v *Value) bool { // match: (MOVWload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVWload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWreg_0(v *Value) bool { // match: (MOVWreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(AND (MOVDconst [c]) _)) // cond: uint64(c) <= 0x7FFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] y_0 := y.Args[0] if y_0.Op != OpPPC64MOVDconst { break } c := y_0.AuxInt if !(uint64(c) <= 0x7FFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(AND _ (MOVDconst [c]))) // cond: uint64(c) <= 0x7FFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] y_1 := y.Args[1] if y_1.Op != OpPPC64MOVDconst { break } c := y_1.AuxInt if !(uint64(c) <= 0x7FFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(MOVWreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVWreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(MOVHreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(MOVBreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(MOVWZreg x)) // cond: // result: (MOVWreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVWZreg { break } x := y.Args[0] v.reset(OpPPC64MOVWreg) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MOVWstore_0(v *Value) bool { // match: (MOVWstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] mem := v.Args[2] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVDconst [c]) mem) // cond: c == 0 // result: (MOVWstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt mem := v.Args[2] if !(c == 0) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem) // cond: // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWZreg x) mem) // cond: // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWstorezero_0(v *Value) bool { // match: (MOVWstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVWstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MTVSRD_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (MTVSRD (MOVDconst [c])) // cond: // result: (FMOVDconst [c]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = c return true } // match: (MTVSRD x:(MOVDload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (FMOVDload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpPPC64MOVDload { break } off := x.AuxInt sym := x.Aux _ = x.Args[1] ptr := x.Args[0] mem := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpPPC64FMOVDload, typ.Float64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MaskIfNotCarry_0(v *Value) bool { // match: (MaskIfNotCarry (ADDconstForCarry [c] (ANDconst [d] _))) // cond: c < 0 && d > 0 && c + d < 0 // result: (MOVDconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconstForCarry { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } d := v_0_0.AuxInt if !(c < 0 && d > 0 && c+d < 0) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = -1 return true } return false } func rewriteValuePPC64_OpPPC64NotEqual_0(v *Value) bool { // match: (NotEqual (FlagEQ)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (NotEqual (FlagLT)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (NotEqual (FlagGT)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (NotEqual (InvertFlags x)) // cond: // result: (NotEqual x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64NotEqual) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64OR_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (OR (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLDconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (SRDconst x [d]) (SLDconst x [c])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLDconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLWconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (SRWconst x [d]) (SLWconst x [c])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLWconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // cond: // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst { break } if v_0_1.Type != typ.Int64 { break } if v_0_1.AuxInt != 63 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 64 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst { break } if v_1_1_1.Type != typ.UInt { break } if v_1_1_1.AuxInt != 63 { break } if y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (OR (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) // cond: // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB { break } if v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst { break } if v_0_1_0.AuxInt != 64 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst { break } if v_0_1_1.Type != typ.UInt { break } if v_0_1_1.AuxInt != 63 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.Int64 { break } if v_1_1.AuxInt != 63 { break } if y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (OR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // cond: // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst { break } if v_0_1.Type != typ.Int32 { break } if v_0_1.AuxInt != 31 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 32 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst { break } if v_1_1_1.Type != typ.UInt { break } if v_1_1_1.AuxInt != 31 { break } if y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (OR (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) // cond: // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB { break } if v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst { break } if v_0_1_0.AuxInt != 32 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst { break } if v_0_1_1.Type != typ.UInt { break } if v_0_1_1.AuxInt != 31 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.Int32 { break } if v_1_1.AuxInt != 31 { break } if y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (OR (MOVDconst [c]) (MOVDconst [d])) // cond: // result: (MOVDconst [c|d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } d := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c | d return true } // match: (OR (MOVDconst [d]) (MOVDconst [c])) // cond: // result: (MOVDconst [c|d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c | d return true } return false } func rewriteValuePPC64_OpPPC64OR_10(v *Value) bool { // match: (OR x (MOVDconst [c])) // cond: isU32Bit(c) // result: (ORconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU32Bit(c)) { break } v.reset(OpPPC64ORconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (MOVDconst [c]) x) // cond: isU32Bit(c) // result: (ORconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt x := v.Args[1] if !(isU32Bit(c)) { break } v.reset(OpPPC64ORconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ORN_0(v *Value) bool { // match: (ORN x (MOVDconst [-1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } if v_1.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ORconst_0(v *Value) bool { // match: (ORconst [c] (ORconst [d] x)) // cond: // result: (ORconst [c|d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64ORconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpPPC64ORconst) v.AuxInt = c | d v.AddArg(x) return true } // match: (ORconst [-1] _) // cond: // result: (MOVDconst [-1]) for { if v.AuxInt != -1 { break } v.reset(OpPPC64MOVDconst) v.AuxInt = -1 return true } // match: (ORconst [0] x) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64SUB_0(v *Value) bool { // match: (SUB x (MOVDconst [c])) // cond: is32Bit(-c) // result: (ADDconst [-c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is32Bit(-c)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = -c v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64XOR_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (XOR (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLDconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (SRDconst x [d]) (SLDconst x [c])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLDconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLWconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (SRWconst x [d]) (SLWconst x [c])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLWconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // cond: // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst { break } if v_0_1.Type != typ.Int64 { break } if v_0_1.AuxInt != 63 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 64 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst { break } if v_1_1_1.Type != typ.UInt { break } if v_1_1_1.AuxInt != 63 { break } if y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (XOR (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) // cond: // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB { break } if v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst { break } if v_0_1_0.AuxInt != 64 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst { break } if v_0_1_1.Type != typ.UInt { break } if v_0_1_1.AuxInt != 63 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.Int64 { break } if v_1_1.AuxInt != 63 { break } if y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (XOR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // cond: // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst { break } if v_0_1.Type != typ.Int32 { break } if v_0_1.AuxInt != 31 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 32 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst { break } if v_1_1_1.Type != typ.UInt { break } if v_1_1_1.AuxInt != 31 { break } if y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (XOR (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) // cond: // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB { break } if v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst { break } if v_0_1_0.AuxInt != 32 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst { break } if v_0_1_1.Type != typ.UInt { break } if v_0_1_1.AuxInt != 31 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.Int32 { break } if v_1_1.AuxInt != 31 { break } if y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (XOR (MOVDconst [c]) (MOVDconst [d])) // cond: // result: (MOVDconst [c^d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } d := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c ^ d return true } // match: (XOR (MOVDconst [d]) (MOVDconst [c])) // cond: // result: (MOVDconst [c^d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c ^ d return true } return false } func rewriteValuePPC64_OpPPC64XOR_10(v *Value) bool { // match: (XOR x (MOVDconst [c])) // cond: isU32Bit(c) // result: (XORconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU32Bit(c)) { break } v.reset(OpPPC64XORconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (MOVDconst [c]) x) // cond: isU32Bit(c) // result: (XORconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt x := v.Args[1] if !(isU32Bit(c)) { break } v.reset(OpPPC64XORconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64XORconst_0(v *Value) bool { // match: (XORconst [c] (XORconst [d] x)) // cond: // result: (XORconst [c^d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64XORconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpPPC64XORconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORconst [0] x) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPopCount16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (PopCount16 x) // cond: // result: (POPCNTW (MOVHZreg x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpPopCount32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (PopCount32 x) // cond: // result: (POPCNTW (MOVWZreg x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpPopCount64_0(v *Value) bool { // match: (PopCount64 x) // cond: // result: (POPCNTD x) for { x := v.Args[0] v.reset(OpPPC64POPCNTD) v.AddArg(x) return true } } func rewriteValuePPC64_OpPopCount8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (PopCount8 x) // cond: // result: (POPCNTB (MOVBreg x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTB) v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRound32F_0(v *Value) bool { // match: (Round32F x) // cond: // result: (LoweredRound32F x) for { x := v.Args[0] v.reset(OpPPC64LoweredRound32F) v.AddArg(x) return true } } func rewriteValuePPC64_OpRound64F_0(v *Value) bool { // match: (Round64F x) // cond: // result: (LoweredRound64F x) for { x := v.Args[0] v.reset(OpPPC64LoweredRound64F) v.AddArg(x) return true } } func rewriteValuePPC64_OpRsh16Ux16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16Ux16 x y) // cond: // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16Ux32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16Ux32 x (Const64 [c])) // cond: uint32(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux32 x (MOVDconst [c])) // cond: uint32(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux32 x y) // cond: // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16Ux64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16Ux64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh16Ux64 x (MOVDconst [c])) // cond: uint64(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux64 x y) // cond: // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16Ux8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16Ux8 x y) // cond: // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16x16 x y) // cond: // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16x32 x (Const64 [c])) // cond: uint32(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x32 x (MOVDconst [c])) // cond: uint32(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x32 x y) // cond: // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16x64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x64 x (Const64 [c])) // cond: uint64(c) >= 16 // result: (SRAWconst (SignExt16to32 x) [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x64 x (MOVDconst [c])) // cond: uint64(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x64 x y) // cond: // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16x8 x y) // cond: // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh32Ux16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32Ux16 x y) // cond: // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32Ux32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32Ux32 x (Const64 [c])) // cond: uint32(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux32 x (MOVDconst [c])) // cond: uint32(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux32 x y) // cond: // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32Ux64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32Ux64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh32Ux64 x (MOVDconst [c])) // cond: uint64(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux64 x (AND y (MOVDconst [31]))) // cond: // result: (SRW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst { break } if v_1_1.AuxInt != 31 { break } v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (AND (MOVDconst [31]) y)) // cond: // result: (SRW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 31 { break } y := v_1.Args[1] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (ANDconst [31] y)) // cond: // result: (SRW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst { break } if v_1.Type != typ.UInt { break } if v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (SUB (MOVDconst [32]) (ANDconst [31] y))) // cond: // result: (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.UInt { break } if v_1_1.AuxInt != 31 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (SUB (MOVDconst [32]) (AND y (MOVDconst [31])))) // cond: // result: (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] y := v_1_1.Args[0] v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64MOVDconst { break } if v_1_1_1.AuxInt != 31 { break } v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (SUB (MOVDconst [32]) (AND (MOVDconst [31]) y))) // cond: // result: (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 31 { break } y := v_1_1.Args[1] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32Ux64 x y) // cond: // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32Ux8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32Ux8 x y) // cond: // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32x16 x y) // cond: // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32x32 x (Const64 [c])) // cond: uint32(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x32 x (MOVDconst [c])) // cond: uint32(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x32 x y) // cond: // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32x64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x64 x (Const64 [c])) // cond: uint64(c) >= 32 // result: (SRAWconst x [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = 63 v.AddArg(x) return true } // match: (Rsh32x64 x (MOVDconst [c])) // cond: uint64(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x64 x (AND y (MOVDconst [31]))) // cond: // result: (SRAW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst { break } if v_1_1.AuxInt != 31 { break } v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32x64 x (AND (MOVDconst [31]) y)) // cond: // result: (SRAW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 31 { break } y := v_1.Args[1] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32x64 x (ANDconst [31] y)) // cond: // result: (SRAW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst { break } if v_1.Type != typ.UInt { break } if v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32x64 x (SUB (MOVDconst [32]) (ANDconst [31] y))) // cond: // result: (SRAW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.UInt { break } if v_1_1.AuxInt != 31 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32x64 x (SUB (MOVDconst [32]) (AND y (MOVDconst [31])))) // cond: // result: (SRAW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] y := v_1_1.Args[0] v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64MOVDconst { break } if v_1_1_1.AuxInt != 31 { break } v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32x64 x (SUB (MOVDconst [32]) (AND (MOVDconst [31]) y))) // cond: // result: (SRAW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 31 { break } y := v_1_1.Args[1] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32x64 x y) // cond: // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32x8 x y) // cond: // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64Ux16 x y) // cond: // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64Ux32 x (Const64 [c])) // cond: uint32(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux32 x (MOVDconst [c])) // cond: uint32(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux32 x y) // cond: // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64Ux64 x (Const64 [c])) // cond: uint64(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh64Ux64 x (MOVDconst [c])) // cond: uint64(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux64 x (AND y (MOVDconst [63]))) // cond: // result: (SRD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst { break } if v_1_1.AuxInt != 63 { break } v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (AND (MOVDconst [63]) y)) // cond: // result: (SRD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 63 { break } y := v_1.Args[1] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (ANDconst [63] y)) // cond: // result: (SRD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst { break } if v_1.Type != typ.UInt { break } if v_1.AuxInt != 63 { break } y := v_1.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (SUB (MOVDconst [64]) (ANDconst [63] y))) // cond: // result: (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.UInt { break } if v_1_1.AuxInt != 63 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (SUB (MOVDconst [64]) (AND y (MOVDconst [63])))) // cond: // result: (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] y := v_1_1.Args[0] v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64MOVDconst { break } if v_1_1_1.AuxInt != 63 { break } v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (SUB (MOVDconst [64]) (AND (MOVDconst [63]) y))) // cond: // result: (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 63 { break } y := v_1_1.Args[1] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64Ux64 x y) // cond: // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64Ux8 x y) // cond: // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64x16 x y) // cond: // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64x32 x (Const64 [c])) // cond: uint32(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x32 x (MOVDconst [c])) // cond: uint32(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x32 x y) // cond: // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64x64 x (Const64 [c])) // cond: uint64(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x64 x (Const64 [c])) // cond: uint64(c) >= 64 // result: (SRADconst x [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = 63 v.AddArg(x) return true } // match: (Rsh64x64 x (MOVDconst [c])) // cond: uint64(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x64 x (AND y (MOVDconst [63]))) // cond: // result: (SRAD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst { break } if v_1_1.AuxInt != 63 { break } v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64x64 x (AND (MOVDconst [63]) y)) // cond: // result: (SRAD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 63 { break } y := v_1.Args[1] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64x64 x (ANDconst [63] y)) // cond: // result: (SRAD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst { break } if v_1.Type != typ.UInt { break } if v_1.AuxInt != 63 { break } y := v_1.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64x64 x (SUB (MOVDconst [64]) (ANDconst [63] y))) // cond: // result: (SRAD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.UInt { break } if v_1_1.AuxInt != 63 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64x64 x (SUB (MOVDconst [64]) (AND y (MOVDconst [63])))) // cond: // result: (SRAD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] y := v_1_1.Args[0] v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64MOVDconst { break } if v_1_1_1.AuxInt != 63 { break } v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64x64 x (SUB (MOVDconst [64]) (AND (MOVDconst [63]) y))) // cond: // result: (SRAD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 63 { break } y := v_1_1.Args[1] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64x64 x y) // cond: // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64x8 x y) // cond: // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh8Ux16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8Ux16 x y) // cond: // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8Ux32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8Ux32 x (Const64 [c])) // cond: uint32(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux32 x (MOVDconst [c])) // cond: uint32(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux32 x y) // cond: // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8Ux64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8Ux64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh8Ux64 x (MOVDconst [c])) // cond: uint64(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux64 x y) // cond: // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8Ux8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8Ux8 x y) // cond: // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8x16 x y) // cond: // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8x32 x (Const64 [c])) // cond: uint32(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x32 x (MOVDconst [c])) // cond: uint32(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x32 x y) // cond: // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8x64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x64 x (Const64 [c])) // cond: uint64(c) >= 8 // result: (SRAWconst (SignExt8to32 x) [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x64 x (MOVDconst [c])) // cond: uint64(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x64 x y) // cond: // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8x8 x y) // cond: // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpSignExt16to32_0(v *Value) bool { // match: (SignExt16to32 x) // cond: // result: (MOVHreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt16to64_0(v *Value) bool { // match: (SignExt16to64 x) // cond: // result: (MOVHreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt32to64_0(v *Value) bool { // match: (SignExt32to64 x) // cond: // result: (MOVWreg x) for { x := v.Args[0] v.reset(OpPPC64MOVWreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt8to16_0(v *Value) bool { // match: (SignExt8to16 x) // cond: // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt8to32_0(v *Value) bool { // match: (SignExt8to32 x) // cond: // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt8to64_0(v *Value) bool { // match: (SignExt8to64 x) // cond: // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSlicemask_0(v *Value) bool { b := v.Block _ = b // match: (Slicemask x) // cond: // result: (SRADconst (NEG x) [63]) for { t := v.Type x := v.Args[0] v.reset(OpPPC64SRADconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpPPC64NEG, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpSqrt_0(v *Value) bool { // match: (Sqrt x) // cond: // result: (FSQRT x) for { x := v.Args[0] v.reset(OpPPC64FSQRT) v.AddArg(x) return true } } func rewriteValuePPC64_OpStaticCall_0(v *Value) bool { // match: (StaticCall [argwid] {target} mem) // cond: // result: (CALLstatic [argwid] {target} mem) for { argwid := v.AuxInt target := v.Aux mem := v.Args[0] v.reset(OpPPC64CALLstatic) v.AuxInt = argwid v.Aux = target v.AddArg(mem) return true } } func rewriteValuePPC64_OpStore_0(v *Value) bool { // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) // result: (FMOVDstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpPPC64FMOVDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is32BitFloat(val.Type) // result: (FMOVDstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 8 && is32BitFloat(val.Type)) { break } v.reset(OpPPC64FMOVDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) // result: (FMOVSstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpPPC64FMOVSstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && (is64BitInt(val.Type) || isPtr(val.Type)) // result: (MOVDstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 8 && (is64BitInt(val.Type) || isPtr(val.Type))) { break } v.reset(OpPPC64MOVDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitInt(val.Type) // result: (MOVWstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 4 && is32BitInt(val.Type)) { break } v.reset(OpPPC64MOVWstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 2 // result: (MOVHstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 2) { break } v.reset(OpPPC64MOVHstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 1 // result: (MOVBstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 1) { break } v.reset(OpPPC64MOVBstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpSub16_0(v *Value) bool { // match: (Sub16 x y) // cond: // result: (SUB x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub32_0(v *Value) bool { // match: (Sub32 x y) // cond: // result: (SUB x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub32F_0(v *Value) bool { // match: (Sub32F x y) // cond: // result: (FSUBS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FSUBS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub64_0(v *Value) bool { // match: (Sub64 x y) // cond: // result: (SUB x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub64F_0(v *Value) bool { // match: (Sub64F x y) // cond: // result: (FSUB x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FSUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub8_0(v *Value) bool { // match: (Sub8 x y) // cond: // result: (SUB x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSubPtr_0(v *Value) bool { // match: (SubPtr x y) // cond: // result: (SUB x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpTrunc_0(v *Value) bool { // match: (Trunc x) // cond: // result: (FTRUNC x) for { x := v.Args[0] v.reset(OpPPC64FTRUNC) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc16to8_0(v *Value) bool { // match: (Trunc16to8 x) // cond: // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc32to16_0(v *Value) bool { // match: (Trunc32to16 x) // cond: // result: (MOVHreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc32to8_0(v *Value) bool { // match: (Trunc32to8 x) // cond: // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc64to16_0(v *Value) bool { // match: (Trunc64to16 x) // cond: // result: (MOVHreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc64to32_0(v *Value) bool { // match: (Trunc64to32 x) // cond: // result: (MOVWreg x) for { x := v.Args[0] v.reset(OpPPC64MOVWreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc64to8_0(v *Value) bool { // match: (Trunc64to8 x) // cond: // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpXor16_0(v *Value) bool { // match: (Xor16 x y) // cond: // result: (XOR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpXor32_0(v *Value) bool { // match: (Xor32 x y) // cond: // result: (XOR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpXor64_0(v *Value) bool { // match: (Xor64 x y) // cond: // result: (XOR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpXor8_0(v *Value) bool { // match: (Xor8 x y) // cond: // result: (XOR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpZero_0(v *Value) bool { b := v.Block _ = b // match: (Zero [0] _ mem) // cond: // result: mem for { if v.AuxInt != 0 { break } _ = v.Args[1] mem := v.Args[1] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Zero [1] destptr mem) // cond: // result: (MOVBstorezero destptr mem) for { if v.AuxInt != 1 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVBstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [2] destptr mem) // cond: // result: (MOVHstorezero destptr mem) for { if v.AuxInt != 2 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVHstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [3] destptr mem) // cond: // result: (MOVBstorezero [2] destptr (MOVHstorezero destptr mem)) for { if v.AuxInt != 3 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVBstorezero) v.AuxInt = 2 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVHstorezero, types.TypeMem) v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [4] destptr mem) // cond: // result: (MOVWstorezero destptr mem) for { if v.AuxInt != 4 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVWstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [5] destptr mem) // cond: // result: (MOVBstorezero [4] destptr (MOVWstorezero destptr mem)) for { if v.AuxInt != 5 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVBstorezero) v.AuxInt = 4 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [6] destptr mem) // cond: // result: (MOVHstorezero [4] destptr (MOVWstorezero destptr mem)) for { if v.AuxInt != 6 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVHstorezero) v.AuxInt = 4 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [7] destptr mem) // cond: // result: (MOVBstorezero [6] destptr (MOVHstorezero [4] destptr (MOVWstorezero destptr mem))) for { if v.AuxInt != 7 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVBstorezero) v.AuxInt = 6 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVHstorezero, types.TypeMem) v0.AuxInt = 4 v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [8] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero destptr mem) for { if v.AuxInt != 8 { break } t := v.Aux _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [8] destptr mem) // cond: // result: (MOVWstorezero [4] destptr (MOVWstorezero [0] destptr mem)) for { if v.AuxInt != 8 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVWstorezero) v.AuxInt = 4 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpZero_10(v *Value) bool { b := v.Block _ = b // match: (Zero [12] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVWstorezero [8] destptr (MOVDstorezero [0] destptr mem)) for { if v.AuxInt != 12 { break } t := v.Aux _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = 8 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [16] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem)) for { if v.AuxInt != 16 { break } t := v.Aux _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = 8 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [24] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero [16] destptr (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem))) for { if v.AuxInt != 24 { break } t := v.Aux _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = 16 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 8 v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [32] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero [24] destptr (MOVDstorezero [16] destptr (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem)))) for { if v.AuxInt != 32 { break } t := v.Aux _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = 24 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 16 v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v1.AuxInt = 8 v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v2.AuxInt = 0 v2.AddArg(destptr) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [s] ptr mem) // cond: // result: (LoweredZero [s] ptr mem) for { s := v.AuxInt _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64LoweredZero) v.AuxInt = s v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpZeroExt16to32_0(v *Value) bool { // match: (ZeroExt16to32 x) // cond: // result: (MOVHZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt16to64_0(v *Value) bool { // match: (ZeroExt16to64 x) // cond: // result: (MOVHZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt32to64_0(v *Value) bool { // match: (ZeroExt32to64 x) // cond: // result: (MOVWZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVWZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt8to16_0(v *Value) bool { // match: (ZeroExt8to16 x) // cond: // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt8to32_0(v *Value) bool { // match: (ZeroExt8to32 x) // cond: // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt8to64_0(v *Value) bool { // match: (ZeroExt8to64 x) // cond: // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteBlockPPC64(b *Block) bool { config := b.Func.Config _ = config fe := b.Func.fe _ = fe typ := &config.Types _ = typ switch b.Kind { case BlockPPC64EQ: // match: (EQ (CMPconst [0] (ANDconst [c] x)) yes no) // cond: // result: (EQ (ANDCCconst [c] x) yes no) for { v := b.Control if v.Op != OpPPC64CMPconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64ANDconst { break } c := v_0.AuxInt x := v_0.Args[0] b.Kind = BlockPPC64EQ v0 := b.NewValue0(v.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.SetControl(v0) b.Aux = nil return true } // match: (EQ (CMPWconst [0] (ANDconst [c] x)) yes no) // cond: // result: (EQ (ANDCCconst [c] x) yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64ANDconst { break } c := v_0.AuxInt x := v_0.Args[0] b.Kind = BlockPPC64EQ v0 := b.NewValue0(v.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.SetControl(v0) b.Aux = nil return true } // match: (EQ (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (EQ (FlagLT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagLT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (EQ (FlagGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (EQ (InvertFlags cmp) yes no) // cond: // result: (EQ cmp yes no) for { v := b.Control if v.Op != OpPPC64InvertFlags { break } cmp := v.Args[0] b.Kind = BlockPPC64EQ b.SetControl(cmp) b.Aux = nil return true } case BlockPPC64GE: // match: (GE (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (GE (FlagLT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagLT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GE (FlagGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (GE (InvertFlags cmp) yes no) // cond: // result: (LE cmp yes no) for { v := b.Control if v.Op != OpPPC64InvertFlags { break } cmp := v.Args[0] b.Kind = BlockPPC64LE b.SetControl(cmp) b.Aux = nil return true } case BlockPPC64GT: // match: (GT (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GT (FlagLT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagLT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GT (FlagGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (GT (InvertFlags cmp) yes no) // cond: // result: (LT cmp yes no) for { v := b.Control if v.Op != OpPPC64InvertFlags { break } cmp := v.Args[0] b.Kind = BlockPPC64LT b.SetControl(cmp) b.Aux = nil return true } case BlockIf: // match: (If (Equal cc) yes no) // cond: // result: (EQ cc yes no) for { v := b.Control if v.Op != OpPPC64Equal { break } cc := v.Args[0] b.Kind = BlockPPC64EQ b.SetControl(cc) b.Aux = nil return true } // match: (If (NotEqual cc) yes no) // cond: // result: (NE cc yes no) for { v := b.Control if v.Op != OpPPC64NotEqual { break } cc := v.Args[0] b.Kind = BlockPPC64NE b.SetControl(cc) b.Aux = nil return true } // match: (If (LessThan cc) yes no) // cond: // result: (LT cc yes no) for { v := b.Control if v.Op != OpPPC64LessThan { break } cc := v.Args[0] b.Kind = BlockPPC64LT b.SetControl(cc) b.Aux = nil return true } // match: (If (LessEqual cc) yes no) // cond: // result: (LE cc yes no) for { v := b.Control if v.Op != OpPPC64LessEqual { break } cc := v.Args[0] b.Kind = BlockPPC64LE b.SetControl(cc) b.Aux = nil return true } // match: (If (GreaterThan cc) yes no) // cond: // result: (GT cc yes no) for { v := b.Control if v.Op != OpPPC64GreaterThan { break } cc := v.Args[0] b.Kind = BlockPPC64GT b.SetControl(cc) b.Aux = nil return true } // match: (If (GreaterEqual cc) yes no) // cond: // result: (GE cc yes no) for { v := b.Control if v.Op != OpPPC64GreaterEqual { break } cc := v.Args[0] b.Kind = BlockPPC64GE b.SetControl(cc) b.Aux = nil return true } // match: (If (FLessThan cc) yes no) // cond: // result: (FLT cc yes no) for { v := b.Control if v.Op != OpPPC64FLessThan { break } cc := v.Args[0] b.Kind = BlockPPC64FLT b.SetControl(cc) b.Aux = nil return true } // match: (If (FLessEqual cc) yes no) // cond: // result: (FLE cc yes no) for { v := b.Control if v.Op != OpPPC64FLessEqual { break } cc := v.Args[0] b.Kind = BlockPPC64FLE b.SetControl(cc) b.Aux = nil return true } // match: (If (FGreaterThan cc) yes no) // cond: // result: (FGT cc yes no) for { v := b.Control if v.Op != OpPPC64FGreaterThan { break } cc := v.Args[0] b.Kind = BlockPPC64FGT b.SetControl(cc) b.Aux = nil return true } // match: (If (FGreaterEqual cc) yes no) // cond: // result: (FGE cc yes no) for { v := b.Control if v.Op != OpPPC64FGreaterEqual { break } cc := v.Args[0] b.Kind = BlockPPC64FGE b.SetControl(cc) b.Aux = nil return true } // match: (If cond yes no) // cond: // result: (NE (CMPWconst [0] cond) yes no) for { v := b.Control _ = v cond := b.Control b.Kind = BlockPPC64NE v0 := b.NewValue0(v.Pos, OpPPC64CMPWconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(cond) b.SetControl(v0) b.Aux = nil return true } case BlockPPC64LE: // match: (LE (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LE (FlagLT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagLT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LE (FlagGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (LE (InvertFlags cmp) yes no) // cond: // result: (GE cmp yes no) for { v := b.Control if v.Op != OpPPC64InvertFlags { break } cmp := v.Args[0] b.Kind = BlockPPC64GE b.SetControl(cmp) b.Aux = nil return true } case BlockPPC64LT: // match: (LT (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (LT (FlagLT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagLT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LT (FlagGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (LT (InvertFlags cmp) yes no) // cond: // result: (GT cmp yes no) for { v := b.Control if v.Op != OpPPC64InvertFlags { break } cmp := v.Args[0] b.Kind = BlockPPC64GT b.SetControl(cmp) b.Aux = nil return true } case BlockPPC64NE: // match: (NE (CMPWconst [0] (Equal cc)) yes no) // cond: // result: (EQ cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64Equal { break } cc := v_0.Args[0] b.Kind = BlockPPC64EQ b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (NotEqual cc)) yes no) // cond: // result: (NE cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64NotEqual { break } cc := v_0.Args[0] b.Kind = BlockPPC64NE b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (LessThan cc)) yes no) // cond: // result: (LT cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64LessThan { break } cc := v_0.Args[0] b.Kind = BlockPPC64LT b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (LessEqual cc)) yes no) // cond: // result: (LE cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64LessEqual { break } cc := v_0.Args[0] b.Kind = BlockPPC64LE b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (GreaterThan cc)) yes no) // cond: // result: (GT cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64GreaterThan { break } cc := v_0.Args[0] b.Kind = BlockPPC64GT b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (GreaterEqual cc)) yes no) // cond: // result: (GE cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64GreaterEqual { break } cc := v_0.Args[0] b.Kind = BlockPPC64GE b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (FLessThan cc)) yes no) // cond: // result: (FLT cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64FLessThan { break } cc := v_0.Args[0] b.Kind = BlockPPC64FLT b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (FLessEqual cc)) yes no) // cond: // result: (FLE cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64FLessEqual { break } cc := v_0.Args[0] b.Kind = BlockPPC64FLE b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (FGreaterThan cc)) yes no) // cond: // result: (FGT cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64FGreaterThan { break } cc := v_0.Args[0] b.Kind = BlockPPC64FGT b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (FGreaterEqual cc)) yes no) // cond: // result: (FGE cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64FGreaterEqual { break } cc := v_0.Args[0] b.Kind = BlockPPC64FGE b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPconst [0] (ANDconst [c] x)) yes no) // cond: // result: (NE (ANDCCconst [c] x) yes no) for { v := b.Control if v.Op != OpPPC64CMPconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64ANDconst { break } c := v_0.AuxInt x := v_0.Args[0] b.Kind = BlockPPC64NE v0 := b.NewValue0(v.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.SetControl(v0) b.Aux = nil return true } // match: (NE (CMPWconst [0] (ANDconst [c] x)) yes no) // cond: // result: (NE (ANDCCconst [c] x) yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64ANDconst { break } c := v_0.AuxInt x := v_0.Args[0] b.Kind = BlockPPC64NE v0 := b.NewValue0(v.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.SetControl(v0) b.Aux = nil return true } // match: (NE (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (NE (FlagLT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagLT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (NE (FlagGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (NE (InvertFlags cmp) yes no) // cond: // result: (NE cmp yes no) for { v := b.Control if v.Op != OpPPC64InvertFlags { break } cmp := v.Args[0] b.Kind = BlockPPC64NE b.SetControl(cmp) b.Aux = nil return true } } return false } -- y -- // Code generated from gen/PPC64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/internal/obj" import "cmd/internal/objabi" import "cmd/compile/internal/types" var _ = math.MinInt8 // in case not otherwise used var _ = obj.ANOP // in case not otherwise used var _ = objabi.GOROOT // in case not otherwise used var _ = types.TypeMem // in case not otherwise used func rewriteValuePPC64(v *Value) bool { switch v.Op { case OpAbs: return rewriteValuePPC64_OpAbs_0(v) case OpAdd16: return rewriteValuePPC64_OpAdd16_0(v) case OpAdd32: return rewriteValuePPC64_OpAdd32_0(v) case OpAdd32F: return rewriteValuePPC64_OpAdd32F_0(v) case OpAdd64: return rewriteValuePPC64_OpAdd64_0(v) case OpAdd64F: return rewriteValuePPC64_OpAdd64F_0(v) case OpAdd8: return rewriteValuePPC64_OpAdd8_0(v) case OpAddPtr: return rewriteValuePPC64_OpAddPtr_0(v) case OpAddr: return rewriteValuePPC64_OpAddr_0(v) case OpAnd16: return rewriteValuePPC64_OpAnd16_0(v) case OpAnd32: return rewriteValuePPC64_OpAnd32_0(v) case OpAnd64: return rewriteValuePPC64_OpAnd64_0(v) case OpAnd8: return rewriteValuePPC64_OpAnd8_0(v) case OpAndB: return rewriteValuePPC64_OpAndB_0(v) case OpAtomicAdd32: return rewriteValuePPC64_OpAtomicAdd32_0(v) case OpAtomicAdd64: return rewriteValuePPC64_OpAtomicAdd64_0(v) case OpAtomicAnd8: return rewriteValuePPC64_OpAtomicAnd8_0(v) case OpAtomicCompareAndSwap32: return rewriteValuePPC64_OpAtomicCompareAndSwap32_0(v) case OpAtomicCompareAndSwap64: return rewriteValuePPC64_OpAtomicCompareAndSwap64_0(v) case OpAtomicExchange32: return rewriteValuePPC64_OpAtomicExchange32_0(v) case OpAtomicExchange64: return rewriteValuePPC64_OpAtomicExchange64_0(v) case OpAtomicLoad32: return rewriteValuePPC64_OpAtomicLoad32_0(v) case OpAtomicLoad64: return rewriteValuePPC64_OpAtomicLoad64_0(v) case OpAtomicLoadPtr: return rewriteValuePPC64_OpAtomicLoadPtr_0(v) case OpAtomicOr8: return rewriteValuePPC64_OpAtomicOr8_0(v) case OpAtomicStore32: return rewriteValuePPC64_OpAtomicStore32_0(v) case OpAtomicStore64: return rewriteValuePPC64_OpAtomicStore64_0(v) case OpAvg64u: return rewriteValuePPC64_OpAvg64u_0(v) case OpBitLen32: return rewriteValuePPC64_OpBitLen32_0(v) case OpBitLen64: return rewriteValuePPC64_OpBitLen64_0(v) case OpCeil: return rewriteValuePPC64_OpCeil_0(v) case OpClosureCall: return rewriteValuePPC64_OpClosureCall_0(v) case OpCom16: return rewriteValuePPC64_OpCom16_0(v) case OpCom32: return rewriteValuePPC64_OpCom32_0(v) case OpCom64: return rewriteValuePPC64_OpCom64_0(v) case OpCom8: return rewriteValuePPC64_OpCom8_0(v) case OpConst16: return rewriteValuePPC64_OpConst16_0(v) case OpConst32: return rewriteValuePPC64_OpConst32_0(v) case OpConst32F: return rewriteValuePPC64_OpConst32F_0(v) case OpConst64: return rewriteValuePPC64_OpConst64_0(v) case OpConst64F: return rewriteValuePPC64_OpConst64F_0(v) case OpConst8: return rewriteValuePPC64_OpConst8_0(v) case OpConstBool: return rewriteValuePPC64_OpConstBool_0(v) case OpConstNil: return rewriteValuePPC64_OpConstNil_0(v) case OpConvert: return rewriteValuePPC64_OpConvert_0(v) case OpCopysign: return rewriteValuePPC64_OpCopysign_0(v) case OpCtz32: return rewriteValuePPC64_OpCtz32_0(v) case OpCtz64: return rewriteValuePPC64_OpCtz64_0(v) case OpCvt32Fto32: return rewriteValuePPC64_OpCvt32Fto32_0(v) case OpCvt32Fto64: return rewriteValuePPC64_OpCvt32Fto64_0(v) case OpCvt32Fto64F: return rewriteValuePPC64_OpCvt32Fto64F_0(v) case OpCvt32to32F: return rewriteValuePPC64_OpCvt32to32F_0(v) case OpCvt32to64F: return rewriteValuePPC64_OpCvt32to64F_0(v) case OpCvt64Fto32: return rewriteValuePPC64_OpCvt64Fto32_0(v) case OpCvt64Fto32F: return rewriteValuePPC64_OpCvt64Fto32F_0(v) case OpCvt64Fto64: return rewriteValuePPC64_OpCvt64Fto64_0(v) case OpCvt64to32F: return rewriteValuePPC64_OpCvt64to32F_0(v) case OpCvt64to64F: return rewriteValuePPC64_OpCvt64to64F_0(v) case OpDiv16: return rewriteValuePPC64_OpDiv16_0(v) case OpDiv16u: return rewriteValuePPC64_OpDiv16u_0(v) case OpDiv32: return rewriteValuePPC64_OpDiv32_0(v) case OpDiv32F: return rewriteValuePPC64_OpDiv32F_0(v) case OpDiv32u: return rewriteValuePPC64_OpDiv32u_0(v) case OpDiv64: return rewriteValuePPC64_OpDiv64_0(v) case OpDiv64F: return rewriteValuePPC64_OpDiv64F_0(v) case OpDiv64u: return rewriteValuePPC64_OpDiv64u_0(v) case OpDiv8: return rewriteValuePPC64_OpDiv8_0(v) case OpDiv8u: return rewriteValuePPC64_OpDiv8u_0(v) case OpEq16: return rewriteValuePPC64_OpEq16_0(v) case OpEq32: return rewriteValuePPC64_OpEq32_0(v) case OpEq32F: return rewriteValuePPC64_OpEq32F_0(v) case OpEq64: return rewriteValuePPC64_OpEq64_0(v) case OpEq64F: return rewriteValuePPC64_OpEq64F_0(v) case OpEq8: return rewriteValuePPC64_OpEq8_0(v) case OpEqB: return rewriteValuePPC64_OpEqB_0(v) case OpEqPtr: return rewriteValuePPC64_OpEqPtr_0(v) case OpFloor: return rewriteValuePPC64_OpFloor_0(v) case OpGeq16: return rewriteValuePPC64_OpGeq16_0(v) case OpGeq16U: return rewriteValuePPC64_OpGeq16U_0(v) case OpGeq32: return rewriteValuePPC64_OpGeq32_0(v) case OpGeq32F: return rewriteValuePPC64_OpGeq32F_0(v) case OpGeq32U: return rewriteValuePPC64_OpGeq32U_0(v) case OpGeq64: return rewriteValuePPC64_OpGeq64_0(v) case OpGeq64F: return rewriteValuePPC64_OpGeq64F_0(v) case OpGeq64U: return rewriteValuePPC64_OpGeq64U_0(v) case OpGeq8: return rewriteValuePPC64_OpGeq8_0(v) case OpGeq8U: return rewriteValuePPC64_OpGeq8U_0(v) case OpGetCallerSP: return rewriteValuePPC64_OpGetCallerSP_0(v) case OpGetClosurePtr: return rewriteValuePPC64_OpGetClosurePtr_0(v) case OpGreater16: return rewriteValuePPC64_OpGreater16_0(v) case OpGreater16U: return rewriteValuePPC64_OpGreater16U_0(v) case OpGreater32: return rewriteValuePPC64_OpGreater32_0(v) case OpGreater32F: return rewriteValuePPC64_OpGreater32F_0(v) case OpGreater32U: return rewriteValuePPC64_OpGreater32U_0(v) case OpGreater64: return rewriteValuePPC64_OpGreater64_0(v) case OpGreater64F: return rewriteValuePPC64_OpGreater64F_0(v) case OpGreater64U: return rewriteValuePPC64_OpGreater64U_0(v) case OpGreater8: return rewriteValuePPC64_OpGreater8_0(v) case OpGreater8U: return rewriteValuePPC64_OpGreater8U_0(v) case OpHmul32: return rewriteValuePPC64_OpHmul32_0(v) case OpHmul32u: return rewriteValuePPC64_OpHmul32u_0(v) case OpHmul64: return rewriteValuePPC64_OpHmul64_0(v) case OpHmul64u: return rewriteValuePPC64_OpHmul64u_0(v) case OpInterCall: return rewriteValuePPC64_OpInterCall_0(v) case OpIsInBounds: return rewriteValuePPC64_OpIsInBounds_0(v) case OpIsNonNil: return rewriteValuePPC64_OpIsNonNil_0(v) case OpIsSliceInBounds: return rewriteValuePPC64_OpIsSliceInBounds_0(v) case OpLeq16: return rewriteValuePPC64_OpLeq16_0(v) case OpLeq16U: return rewriteValuePPC64_OpLeq16U_0(v) case OpLeq32: return rewriteValuePPC64_OpLeq32_0(v) case OpLeq32F: return rewriteValuePPC64_OpLeq32F_0(v) case OpLeq32U: return rewriteValuePPC64_OpLeq32U_0(v) case OpLeq64: return rewriteValuePPC64_OpLeq64_0(v) case OpLeq64F: return rewriteValuePPC64_OpLeq64F_0(v) case OpLeq64U: return rewriteValuePPC64_OpLeq64U_0(v) case OpLeq8: return rewriteValuePPC64_OpLeq8_0(v) case OpLeq8U: return rewriteValuePPC64_OpLeq8U_0(v) case OpLess16: return rewriteValuePPC64_OpLess16_0(v) case OpLess16U: return rewriteValuePPC64_OpLess16U_0(v) case OpLess32: return rewriteValuePPC64_OpLess32_0(v) case OpLess32F: return rewriteValuePPC64_OpLess32F_0(v) case OpLess32U: return rewriteValuePPC64_OpLess32U_0(v) case OpLess64: return rewriteValuePPC64_OpLess64_0(v) case OpLess64F: return rewriteValuePPC64_OpLess64F_0(v) case OpLess64U: return rewriteValuePPC64_OpLess64U_0(v) case OpLess8: return rewriteValuePPC64_OpLess8_0(v) case OpLess8U: return rewriteValuePPC64_OpLess8U_0(v) case OpLoad: return rewriteValuePPC64_OpLoad_0(v) case OpLsh16x16: return rewriteValuePPC64_OpLsh16x16_0(v) case OpLsh16x32: return rewriteValuePPC64_OpLsh16x32_0(v) case OpLsh16x64: return rewriteValuePPC64_OpLsh16x64_0(v) case OpLsh16x8: return rewriteValuePPC64_OpLsh16x8_0(v) case OpLsh32x16: return rewriteValuePPC64_OpLsh32x16_0(v) case OpLsh32x32: return rewriteValuePPC64_OpLsh32x32_0(v) case OpLsh32x64: return rewriteValuePPC64_OpLsh32x64_0(v) case OpLsh32x8: return rewriteValuePPC64_OpLsh32x8_0(v) case OpLsh64x16: return rewriteValuePPC64_OpLsh64x16_0(v) case OpLsh64x32: return rewriteValuePPC64_OpLsh64x32_0(v) case OpLsh64x64: return rewriteValuePPC64_OpLsh64x64_0(v) case OpLsh64x8: return rewriteValuePPC64_OpLsh64x8_0(v) case OpLsh8x16: return rewriteValuePPC64_OpLsh8x16_0(v) case OpLsh8x32: return rewriteValuePPC64_OpLsh8x32_0(v) case OpLsh8x64: return rewriteValuePPC64_OpLsh8x64_0(v) case OpLsh8x8: return rewriteValuePPC64_OpLsh8x8_0(v) case OpMod16: return rewriteValuePPC64_OpMod16_0(v) case OpMod16u: return rewriteValuePPC64_OpMod16u_0(v) case OpMod32: return rewriteValuePPC64_OpMod32_0(v) case OpMod32u: return rewriteValuePPC64_OpMod32u_0(v) case OpMod64: return rewriteValuePPC64_OpMod64_0(v) case OpMod64u: return rewriteValuePPC64_OpMod64u_0(v) case OpMod8: return rewriteValuePPC64_OpMod8_0(v) case OpMod8u: return rewriteValuePPC64_OpMod8u_0(v) case OpMove: return rewriteValuePPC64_OpMove_0(v) || rewriteValuePPC64_OpMove_10(v) case OpMul16: return rewriteValuePPC64_OpMul16_0(v) case OpMul32: return rewriteValuePPC64_OpMul32_0(v) case OpMul32F: return rewriteValuePPC64_OpMul32F_0(v) case OpMul64: return rewriteValuePPC64_OpMul64_0(v) case OpMul64F: return rewriteValuePPC64_OpMul64F_0(v) case OpMul8: return rewriteValuePPC64_OpMul8_0(v) case OpNeg16: return rewriteValuePPC64_OpNeg16_0(v) case OpNeg32: return rewriteValuePPC64_OpNeg32_0(v) case OpNeg32F: return rewriteValuePPC64_OpNeg32F_0(v) case OpNeg64: return rewriteValuePPC64_OpNeg64_0(v) case OpNeg64F: return rewriteValuePPC64_OpNeg64F_0(v) case OpNeg8: return rewriteValuePPC64_OpNeg8_0(v) case OpNeq16: return rewriteValuePPC64_OpNeq16_0(v) case OpNeq32: return rewriteValuePPC64_OpNeq32_0(v) case OpNeq32F: return rewriteValuePPC64_OpNeq32F_0(v) case OpNeq64: return rewriteValuePPC64_OpNeq64_0(v) case OpNeq64F: return rewriteValuePPC64_OpNeq64F_0(v) case OpNeq8: return rewriteValuePPC64_OpNeq8_0(v) case OpNeqB: return rewriteValuePPC64_OpNeqB_0(v) case OpNeqPtr: return rewriteValuePPC64_OpNeqPtr_0(v) case OpNilCheck: return rewriteValuePPC64_OpNilCheck_0(v) case OpNot: return rewriteValuePPC64_OpNot_0(v) case OpOffPtr: return rewriteValuePPC64_OpOffPtr_0(v) case OpOr16: return rewriteValuePPC64_OpOr16_0(v) case OpOr32: return rewriteValuePPC64_OpOr32_0(v) case OpOr64: return rewriteValuePPC64_OpOr64_0(v) case OpOr8: return rewriteValuePPC64_OpOr8_0(v) case OpOrB: return rewriteValuePPC64_OpOrB_0(v) case OpPPC64ADD: return rewriteValuePPC64_OpPPC64ADD_0(v) case OpPPC64ADDconst: return rewriteValuePPC64_OpPPC64ADDconst_0(v) case OpPPC64AND: return rewriteValuePPC64_OpPPC64AND_0(v) case OpPPC64ANDconst: return rewriteValuePPC64_OpPPC64ANDconst_0(v) case OpPPC64CMP: return rewriteValuePPC64_OpPPC64CMP_0(v) case OpPPC64CMPU: return rewriteValuePPC64_OpPPC64CMPU_0(v) case OpPPC64CMPUconst: return rewriteValuePPC64_OpPPC64CMPUconst_0(v) case OpPPC64CMPW: return rewriteValuePPC64_OpPPC64CMPW_0(v) case OpPPC64CMPWU: return rewriteValuePPC64_OpPPC64CMPWU_0(v) case OpPPC64CMPWUconst: return rewriteValuePPC64_OpPPC64CMPWUconst_0(v) case OpPPC64CMPWconst: return rewriteValuePPC64_OpPPC64CMPWconst_0(v) case OpPPC64CMPconst: return rewriteValuePPC64_OpPPC64CMPconst_0(v) case OpPPC64Equal: return rewriteValuePPC64_OpPPC64Equal_0(v) case OpPPC64FABS: return rewriteValuePPC64_OpPPC64FABS_0(v) case OpPPC64FADD: return rewriteValuePPC64_OpPPC64FADD_0(v) case OpPPC64FADDS: return rewriteValuePPC64_OpPPC64FADDS_0(v) case OpPPC64FCEIL: return rewriteValuePPC64_OpPPC64FCEIL_0(v) case OpPPC64FFLOOR: return rewriteValuePPC64_OpPPC64FFLOOR_0(v) case OpPPC64FMOVDload: return rewriteValuePPC64_OpPPC64FMOVDload_0(v) case OpPPC64FMOVDstore: return rewriteValuePPC64_OpPPC64FMOVDstore_0(v) case OpPPC64FMOVSload: return rewriteValuePPC64_OpPPC64FMOVSload_0(v) case OpPPC64FMOVSstore: return rewriteValuePPC64_OpPPC64FMOVSstore_0(v) case OpPPC64FNEG: return rewriteValuePPC64_OpPPC64FNEG_0(v) case OpPPC64FSQRT: return rewriteValuePPC64_OpPPC64FSQRT_0(v) case OpPPC64FSUB: return rewriteValuePPC64_OpPPC64FSUB_0(v) case OpPPC64FSUBS: return rewriteValuePPC64_OpPPC64FSUBS_0(v) case OpPPC64FTRUNC: return rewriteValuePPC64_OpPPC64FTRUNC_0(v) case OpPPC64GreaterEqual: return rewriteValuePPC64_OpPPC64GreaterEqual_0(v) case OpPPC64GreaterThan: return rewriteValuePPC64_OpPPC64GreaterThan_0(v) case OpPPC64LessEqual: return rewriteValuePPC64_OpPPC64LessEqual_0(v) case OpPPC64LessThan: return rewriteValuePPC64_OpPPC64LessThan_0(v) case OpPPC64MFVSRD: return rewriteValuePPC64_OpPPC64MFVSRD_0(v) case OpPPC64MOVBZload: return rewriteValuePPC64_OpPPC64MOVBZload_0(v) case OpPPC64MOVBZreg: return rewriteValuePPC64_OpPPC64MOVBZreg_0(v) case OpPPC64MOVBreg: return rewriteValuePPC64_OpPPC64MOVBreg_0(v) case OpPPC64MOVBstore: return rewriteValuePPC64_OpPPC64MOVBstore_0(v) case OpPPC64MOVBstorezero: return rewriteValuePPC64_OpPPC64MOVBstorezero_0(v) case OpPPC64MOVDload: return rewriteValuePPC64_OpPPC64MOVDload_0(v) case OpPPC64MOVDstore: return rewriteValuePPC64_OpPPC64MOVDstore_0(v) case OpPPC64MOVDstorezero: return rewriteValuePPC64_OpPPC64MOVDstorezero_0(v) case OpPPC64MOVHZload: return rewriteValuePPC64_OpPPC64MOVHZload_0(v) case OpPPC64MOVHZreg: return rewriteValuePPC64_OpPPC64MOVHZreg_0(v) case OpPPC64MOVHload: return rewriteValuePPC64_OpPPC64MOVHload_0(v) case OpPPC64MOVHreg: return rewriteValuePPC64_OpPPC64MOVHreg_0(v) case OpPPC64MOVHstore: return rewriteValuePPC64_OpPPC64MOVHstore_0(v) case OpPPC64MOVHstorezero: return rewriteValuePPC64_OpPPC64MOVHstorezero_0(v) case OpPPC64MOVWZload: return rewriteValuePPC64_OpPPC64MOVWZload_0(v) case OpPPC64MOVWZreg: return rewriteValuePPC64_OpPPC64MOVWZreg_0(v) case OpPPC64MOVWload: return rewriteValuePPC64_OpPPC64MOVWload_0(v) case OpPPC64MOVWreg: return rewriteValuePPC64_OpPPC64MOVWreg_0(v) case OpPPC64MOVWstore: return rewriteValuePPC64_OpPPC64MOVWstore_0(v) case OpPPC64MOVWstorezero: return rewriteValuePPC64_OpPPC64MOVWstorezero_0(v) case OpPPC64MTVSRD: return rewriteValuePPC64_OpPPC64MTVSRD_0(v) case OpPPC64MaskIfNotCarry: return rewriteValuePPC64_OpPPC64MaskIfNotCarry_0(v) case OpPPC64NotEqual: return rewriteValuePPC64_OpPPC64NotEqual_0(v) case OpPPC64OR: return rewriteValuePPC64_OpPPC64OR_0(v) || rewriteValuePPC64_OpPPC64OR_10(v) || rewriteValuePPC64_OpPPC64OR_20(v) || rewriteValuePPC64_OpPPC64OR_30(v) || rewriteValuePPC64_OpPPC64OR_40(v) || rewriteValuePPC64_OpPPC64OR_50(v) || rewriteValuePPC64_OpPPC64OR_60(v) || rewriteValuePPC64_OpPPC64OR_70(v) || rewriteValuePPC64_OpPPC64OR_80(v) || rewriteValuePPC64_OpPPC64OR_90(v) || rewriteValuePPC64_OpPPC64OR_100(v) || rewriteValuePPC64_OpPPC64OR_110(v) || rewriteValuePPC64_OpPPC64OR_120(v) || rewriteValuePPC64_OpPPC64OR_130(v) || rewriteValuePPC64_OpPPC64OR_140(v) case OpPPC64ORN: return rewriteValuePPC64_OpPPC64ORN_0(v) case OpPPC64ORconst: return rewriteValuePPC64_OpPPC64ORconst_0(v) case OpPPC64SUB: return rewriteValuePPC64_OpPPC64SUB_0(v) case OpPPC64XOR: return rewriteValuePPC64_OpPPC64XOR_0(v) || rewriteValuePPC64_OpPPC64XOR_10(v) case OpPPC64XORconst: return rewriteValuePPC64_OpPPC64XORconst_0(v) case OpPopCount16: return rewriteValuePPC64_OpPopCount16_0(v) case OpPopCount32: return rewriteValuePPC64_OpPopCount32_0(v) case OpPopCount64: return rewriteValuePPC64_OpPopCount64_0(v) case OpPopCount8: return rewriteValuePPC64_OpPopCount8_0(v) case OpRound32F: return rewriteValuePPC64_OpRound32F_0(v) case OpRound64F: return rewriteValuePPC64_OpRound64F_0(v) case OpRsh16Ux16: return rewriteValuePPC64_OpRsh16Ux16_0(v) case OpRsh16Ux32: return rewriteValuePPC64_OpRsh16Ux32_0(v) case OpRsh16Ux64: return rewriteValuePPC64_OpRsh16Ux64_0(v) case OpRsh16Ux8: return rewriteValuePPC64_OpRsh16Ux8_0(v) case OpRsh16x16: return rewriteValuePPC64_OpRsh16x16_0(v) case OpRsh16x32: return rewriteValuePPC64_OpRsh16x32_0(v) case OpRsh16x64: return rewriteValuePPC64_OpRsh16x64_0(v) case OpRsh16x8: return rewriteValuePPC64_OpRsh16x8_0(v) case OpRsh32Ux16: return rewriteValuePPC64_OpRsh32Ux16_0(v) case OpRsh32Ux32: return rewriteValuePPC64_OpRsh32Ux32_0(v) case OpRsh32Ux64: return rewriteValuePPC64_OpRsh32Ux64_0(v) case OpRsh32Ux8: return rewriteValuePPC64_OpRsh32Ux8_0(v) case OpRsh32x16: return rewriteValuePPC64_OpRsh32x16_0(v) case OpRsh32x32: return rewriteValuePPC64_OpRsh32x32_0(v) case OpRsh32x64: return rewriteValuePPC64_OpRsh32x64_0(v) case OpRsh32x8: return rewriteValuePPC64_OpRsh32x8_0(v) case OpRsh64Ux16: return rewriteValuePPC64_OpRsh64Ux16_0(v) case OpRsh64Ux32: return rewriteValuePPC64_OpRsh64Ux32_0(v) case OpRsh64Ux64: return rewriteValuePPC64_OpRsh64Ux64_0(v) case OpRsh64Ux8: return rewriteValuePPC64_OpRsh64Ux8_0(v) case OpRsh64x16: return rewriteValuePPC64_OpRsh64x16_0(v) case OpRsh64x32: return rewriteValuePPC64_OpRsh64x32_0(v) case OpRsh64x64: return rewriteValuePPC64_OpRsh64x64_0(v) case OpRsh64x8: return rewriteValuePPC64_OpRsh64x8_0(v) case OpRsh8Ux16: return rewriteValuePPC64_OpRsh8Ux16_0(v) case OpRsh8Ux32: return rewriteValuePPC64_OpRsh8Ux32_0(v) case OpRsh8Ux64: return rewriteValuePPC64_OpRsh8Ux64_0(v) case OpRsh8Ux8: return rewriteValuePPC64_OpRsh8Ux8_0(v) case OpRsh8x16: return rewriteValuePPC64_OpRsh8x16_0(v) case OpRsh8x32: return rewriteValuePPC64_OpRsh8x32_0(v) case OpRsh8x64: return rewriteValuePPC64_OpRsh8x64_0(v) case OpRsh8x8: return rewriteValuePPC64_OpRsh8x8_0(v) case OpSignExt16to32: return rewriteValuePPC64_OpSignExt16to32_0(v) case OpSignExt16to64: return rewriteValuePPC64_OpSignExt16to64_0(v) case OpSignExt32to64: return rewriteValuePPC64_OpSignExt32to64_0(v) case OpSignExt8to16: return rewriteValuePPC64_OpSignExt8to16_0(v) case OpSignExt8to32: return rewriteValuePPC64_OpSignExt8to32_0(v) case OpSignExt8to64: return rewriteValuePPC64_OpSignExt8to64_0(v) case OpSlicemask: return rewriteValuePPC64_OpSlicemask_0(v) case OpSqrt: return rewriteValuePPC64_OpSqrt_0(v) case OpStaticCall: return rewriteValuePPC64_OpStaticCall_0(v) case OpStore: return rewriteValuePPC64_OpStore_0(v) case OpSub16: return rewriteValuePPC64_OpSub16_0(v) case OpSub32: return rewriteValuePPC64_OpSub32_0(v) case OpSub32F: return rewriteValuePPC64_OpSub32F_0(v) case OpSub64: return rewriteValuePPC64_OpSub64_0(v) case OpSub64F: return rewriteValuePPC64_OpSub64F_0(v) case OpSub8: return rewriteValuePPC64_OpSub8_0(v) case OpSubPtr: return rewriteValuePPC64_OpSubPtr_0(v) case OpTrunc: return rewriteValuePPC64_OpTrunc_0(v) case OpTrunc16to8: return rewriteValuePPC64_OpTrunc16to8_0(v) case OpTrunc32to16: return rewriteValuePPC64_OpTrunc32to16_0(v) case OpTrunc32to8: return rewriteValuePPC64_OpTrunc32to8_0(v) case OpTrunc64to16: return rewriteValuePPC64_OpTrunc64to16_0(v) case OpTrunc64to32: return rewriteValuePPC64_OpTrunc64to32_0(v) case OpTrunc64to8: return rewriteValuePPC64_OpTrunc64to8_0(v) case OpXor16: return rewriteValuePPC64_OpXor16_0(v) case OpXor32: return rewriteValuePPC64_OpXor32_0(v) case OpXor64: return rewriteValuePPC64_OpXor64_0(v) case OpXor8: return rewriteValuePPC64_OpXor8_0(v) case OpZero: return rewriteValuePPC64_OpZero_0(v) || rewriteValuePPC64_OpZero_10(v) case OpZeroExt16to32: return rewriteValuePPC64_OpZeroExt16to32_0(v) case OpZeroExt16to64: return rewriteValuePPC64_OpZeroExt16to64_0(v) case OpZeroExt32to64: return rewriteValuePPC64_OpZeroExt32to64_0(v) case OpZeroExt8to16: return rewriteValuePPC64_OpZeroExt8to16_0(v) case OpZeroExt8to32: return rewriteValuePPC64_OpZeroExt8to32_0(v) case OpZeroExt8to64: return rewriteValuePPC64_OpZeroExt8to64_0(v) } return false } func rewriteValuePPC64_OpAbs_0(v *Value) bool { // match: (Abs x) // cond: // result: (FABS x) for { x := v.Args[0] v.reset(OpPPC64FABS) v.AddArg(x) return true } } func rewriteValuePPC64_OpAdd16_0(v *Value) bool { // match: (Add16 x y) // cond: // result: (ADD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd32_0(v *Value) bool { // match: (Add32 x y) // cond: // result: (ADD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd32F_0(v *Value) bool { // match: (Add32F x y) // cond: // result: (FADDS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FADDS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd64_0(v *Value) bool { // match: (Add64 x y) // cond: // result: (ADD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd64F_0(v *Value) bool { // match: (Add64F x y) // cond: // result: (FADD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd8_0(v *Value) bool { // match: (Add8 x y) // cond: // result: (ADD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAddPtr_0(v *Value) bool { // match: (AddPtr x y) // cond: // result: (ADD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAddr_0(v *Value) bool { // match: (Addr {sym} base) // cond: // result: (MOVDaddr {sym} base) for { sym := v.Aux base := v.Args[0] v.reset(OpPPC64MOVDaddr) v.Aux = sym v.AddArg(base) return true } } func rewriteValuePPC64_OpAnd16_0(v *Value) bool { // match: (And16 x y) // cond: // result: (AND x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAnd32_0(v *Value) bool { // match: (And32 x y) // cond: // result: (AND x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAnd64_0(v *Value) bool { // match: (And64 x y) // cond: // result: (AND x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAnd8_0(v *Value) bool { // match: (And8 x y) // cond: // result: (AND x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAndB_0(v *Value) bool { // match: (AndB x y) // cond: // result: (AND x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAtomicAdd32_0(v *Value) bool { // match: (AtomicAdd32 ptr val mem) // cond: // result: (LoweredAtomicAdd32 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicAdd32) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicAdd64_0(v *Value) bool { // match: (AtomicAdd64 ptr val mem) // cond: // result: (LoweredAtomicAdd64 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicAdd64) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicAnd8_0(v *Value) bool { // match: (AtomicAnd8 ptr val mem) // cond: // result: (LoweredAtomicAnd8 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicAnd8) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicCompareAndSwap32_0(v *Value) bool { // match: (AtomicCompareAndSwap32 ptr old new_ mem) // cond: // result: (LoweredAtomicCas32 ptr old new_ mem) for { _ = v.Args[3] ptr := v.Args[0] old := v.Args[1] new_ := v.Args[2] mem := v.Args[3] v.reset(OpPPC64LoweredAtomicCas32) v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicCompareAndSwap64_0(v *Value) bool { // match: (AtomicCompareAndSwap64 ptr old new_ mem) // cond: // result: (LoweredAtomicCas64 ptr old new_ mem) for { _ = v.Args[3] ptr := v.Args[0] old := v.Args[1] new_ := v.Args[2] mem := v.Args[3] v.reset(OpPPC64LoweredAtomicCas64) v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicExchange32_0(v *Value) bool { // match: (AtomicExchange32 ptr val mem) // cond: // result: (LoweredAtomicExchange32 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicExchange32) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicExchange64_0(v *Value) bool { // match: (AtomicExchange64 ptr val mem) // cond: // result: (LoweredAtomicExchange64 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicExchange64) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoad32_0(v *Value) bool { // match: (AtomicLoad32 ptr mem) // cond: // result: (LoweredAtomicLoad32 ptr mem) for { _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64LoweredAtomicLoad32) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoad64_0(v *Value) bool { // match: (AtomicLoad64 ptr mem) // cond: // result: (LoweredAtomicLoad64 ptr mem) for { _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64LoweredAtomicLoad64) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoadPtr_0(v *Value) bool { // match: (AtomicLoadPtr ptr mem) // cond: // result: (LoweredAtomicLoadPtr ptr mem) for { _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64LoweredAtomicLoadPtr) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicOr8_0(v *Value) bool { // match: (AtomicOr8 ptr val mem) // cond: // result: (LoweredAtomicOr8 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicOr8) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicStore32_0(v *Value) bool { // match: (AtomicStore32 ptr val mem) // cond: // result: (LoweredAtomicStore32 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicStore32) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicStore64_0(v *Value) bool { // match: (AtomicStore64 ptr val mem) // cond: // result: (LoweredAtomicStore64 ptr val mem) for { _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] v.reset(OpPPC64LoweredAtomicStore64) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAvg64u_0(v *Value) bool { b := v.Block _ = b // match: (Avg64u x y) // cond: // result: (ADD (SRDconst (SUB x y) [1]) y) for { t := v.Type _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ADD) v0 := b.NewValue0(v.Pos, OpPPC64SRDconst, t) v0.AuxInt = 1 v1 := b.NewValue0(v.Pos, OpPPC64SUB, t) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) v.AddArg(y) return true } } func rewriteValuePPC64_OpBitLen32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (BitLen32 x) // cond: // result: (SUB (MOVDconst [32]) (CNTLZW x)) for { x := v.Args[0] v.reset(OpPPC64SUB) v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 32 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64CNTLZW, typ.Int) v1.AddArg(x) v.AddArg(v1) return true } } func rewriteValuePPC64_OpBitLen64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (BitLen64 x) // cond: // result: (SUB (MOVDconst [64]) (CNTLZD x)) for { x := v.Args[0] v.reset(OpPPC64SUB) v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 64 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64CNTLZD, typ.Int) v1.AddArg(x) v.AddArg(v1) return true } } func rewriteValuePPC64_OpCeil_0(v *Value) bool { // match: (Ceil x) // cond: // result: (FCEIL x) for { x := v.Args[0] v.reset(OpPPC64FCEIL) v.AddArg(x) return true } } func rewriteValuePPC64_OpClosureCall_0(v *Value) bool { // match: (ClosureCall [argwid] entry closure mem) // cond: // result: (CALLclosure [argwid] entry closure mem) for { argwid := v.AuxInt _ = v.Args[2] entry := v.Args[0] closure := v.Args[1] mem := v.Args[2] v.reset(OpPPC64CALLclosure) v.AuxInt = argwid v.AddArg(entry) v.AddArg(closure) v.AddArg(mem) return true } } func rewriteValuePPC64_OpCom16_0(v *Value) bool { // match: (Com16 x) // cond: // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCom32_0(v *Value) bool { // match: (Com32 x) // cond: // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCom64_0(v *Value) bool { // match: (Com64 x) // cond: // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCom8_0(v *Value) bool { // match: (Com8 x) // cond: // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpConst16_0(v *Value) bool { // match: (Const16 [val]) // cond: // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst32_0(v *Value) bool { // match: (Const32 [val]) // cond: // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst32F_0(v *Value) bool { // match: (Const32F [val]) // cond: // result: (FMOVSconst [val]) for { val := v.AuxInt v.reset(OpPPC64FMOVSconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst64_0(v *Value) bool { // match: (Const64 [val]) // cond: // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst64F_0(v *Value) bool { // match: (Const64F [val]) // cond: // result: (FMOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst8_0(v *Value) bool { // match: (Const8 [val]) // cond: // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConstBool_0(v *Value) bool { // match: (ConstBool [b]) // cond: // result: (MOVDconst [b]) for { b := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = b return true } } func rewriteValuePPC64_OpConstNil_0(v *Value) bool { // match: (ConstNil) // cond: // result: (MOVDconst [0]) for { v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } } func rewriteValuePPC64_OpConvert_0(v *Value) bool { // match: (Convert x mem) // cond: // result: (MOVDconvert x mem) for { t := v.Type _ = v.Args[1] x := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVDconvert) v.Type = t v.AddArg(x) v.AddArg(mem) return true } } func rewriteValuePPC64_OpCopysign_0(v *Value) bool { // match: (Copysign x y) // cond: // result: (FCPSGN y x) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FCPSGN) v.AddArg(y) v.AddArg(x) return true } } func rewriteValuePPC64_OpCtz32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Ctz32 x) // cond: // result: (POPCNTW (MOVWZreg (ANDN (ADDconst [-1] x) x))) for { x := v.Args[0] v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZreg, typ.Int64) v1 := b.NewValue0(v.Pos, OpPPC64ANDN, typ.Int) v2 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.Int) v2.AuxInt = -1 v2.AddArg(x) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCtz64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Ctz64 x) // cond: // result: (POPCNTD (ANDN (ADDconst [-1] x) x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTD) v0 := b.NewValue0(v.Pos, OpPPC64ANDN, typ.Int64) v1 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.Int64) v1.AuxInt = -1 v1.AddArg(x) v0.AddArg(v1) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32Fto32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt32Fto32 x) // cond: // result: (MFVSRD (FCTIWZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIWZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32Fto64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt32Fto64 x) // cond: // result: (MFVSRD (FCTIDZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIDZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32Fto64F_0(v *Value) bool { // match: (Cvt32Fto64F x) // cond: // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValuePPC64_OpCvt32to32F_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt32to32F x) // cond: // result: (FCFIDS (MTVSRD (SignExt32to64 x))) for { x := v.Args[0] v.reset(OpPPC64FCFIDS) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32to64F_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt32to64F x) // cond: // result: (FCFID (MTVSRD (SignExt32to64 x))) for { x := v.Args[0] v.reset(OpPPC64FCFID) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64Fto32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt64Fto32 x) // cond: // result: (MFVSRD (FCTIWZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIWZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64Fto32F_0(v *Value) bool { // match: (Cvt64Fto32F x) // cond: // result: (FRSP x) for { x := v.Args[0] v.reset(OpPPC64FRSP) v.AddArg(x) return true } } func rewriteValuePPC64_OpCvt64Fto64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt64Fto64 x) // cond: // result: (MFVSRD (FCTIDZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIDZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64to32F_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt64to32F x) // cond: // result: (FCFIDS (MTVSRD x)) for { x := v.Args[0] v.reset(OpPPC64FCFIDS) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64to64F_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Cvt64to64F x) // cond: // result: (FCFID (MTVSRD x)) for { x := v.Args[0] v.reset(OpPPC64FCFID) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpDiv16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Div16 x y) // cond: // result: (DIVW (SignExt16to32 x) (SignExt16to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpDiv16u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Div16u x y) // cond: // result: (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVWU) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpDiv32_0(v *Value) bool { // match: (Div32 x y) // cond: // result: (DIVW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv32F_0(v *Value) bool { // match: (Div32F x y) // cond: // result: (FDIVS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FDIVS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv32u_0(v *Value) bool { // match: (Div32u x y) // cond: // result: (DIVWU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVWU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv64_0(v *Value) bool { // match: (Div64 x y) // cond: // result: (DIVD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv64F_0(v *Value) bool { // match: (Div64F x y) // cond: // result: (FDIV x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FDIV) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv64u_0(v *Value) bool { // match: (Div64u x y) // cond: // result: (DIVDU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVDU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Div8 x y) // cond: // result: (DIVW (SignExt8to32 x) (SignExt8to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpDiv8u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Div8u x y) // cond: // result: (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64DIVWU) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpEq16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Eq16 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Eq16 x y) // cond: // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq32_0(v *Value) bool { b := v.Block _ = b // match: (Eq32 x y) // cond: // result: (Equal (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq32F_0(v *Value) bool { b := v.Block _ = b // match: (Eq32F x y) // cond: // result: (Equal (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq64_0(v *Value) bool { b := v.Block _ = b // match: (Eq64 x y) // cond: // result: (Equal (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq64F_0(v *Value) bool { b := v.Block _ = b // match: (Eq64F x y) // cond: // result: (Equal (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Eq8 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Eq8 x y) // cond: // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEqB_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (EqB x y) // cond: // result: (ANDconst [1] (EQV x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64ANDconst) v.AuxInt = 1 v0 := b.NewValue0(v.Pos, OpPPC64EQV, typ.Int64) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEqPtr_0(v *Value) bool { b := v.Block _ = b // match: (EqPtr x y) // cond: // result: (Equal (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpFloor_0(v *Value) bool { // match: (Floor x) // cond: // result: (FFLOOR x) for { x := v.Args[0] v.reset(OpPPC64FFLOOR) v.AddArg(x) return true } } func rewriteValuePPC64_OpGeq16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Geq16 x y) // cond: // result: (GreaterEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq16U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Geq16U x y) // cond: // result: (GreaterEqual (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq32_0(v *Value) bool { b := v.Block _ = b // match: (Geq32 x y) // cond: // result: (GreaterEqual (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq32F_0(v *Value) bool { b := v.Block _ = b // match: (Geq32F x y) // cond: // result: (FGreaterEqual (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FGreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq32U_0(v *Value) bool { b := v.Block _ = b // match: (Geq32U x y) // cond: // result: (GreaterEqual (CMPWU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq64_0(v *Value) bool { b := v.Block _ = b // match: (Geq64 x y) // cond: // result: (GreaterEqual (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq64F_0(v *Value) bool { b := v.Block _ = b // match: (Geq64F x y) // cond: // result: (FGreaterEqual (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FGreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq64U_0(v *Value) bool { b := v.Block _ = b // match: (Geq64U x y) // cond: // result: (GreaterEqual (CMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Geq8 x y) // cond: // result: (GreaterEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq8U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Geq8U x y) // cond: // result: (GreaterEqual (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGetCallerSP_0(v *Value) bool { // match: (GetCallerSP) // cond: // result: (LoweredGetCallerSP) for { v.reset(OpPPC64LoweredGetCallerSP) return true } } func rewriteValuePPC64_OpGetClosurePtr_0(v *Value) bool { // match: (GetClosurePtr) // cond: // result: (LoweredGetClosurePtr) for { v.reset(OpPPC64LoweredGetClosurePtr) return true } } func rewriteValuePPC64_OpGreater16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Greater16 x y) // cond: // result: (GreaterThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater16U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Greater16U x y) // cond: // result: (GreaterThan (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater32_0(v *Value) bool { b := v.Block _ = b // match: (Greater32 x y) // cond: // result: (GreaterThan (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater32F_0(v *Value) bool { b := v.Block _ = b // match: (Greater32F x y) // cond: // result: (FGreaterThan (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FGreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater32U_0(v *Value) bool { b := v.Block _ = b // match: (Greater32U x y) // cond: // result: (GreaterThan (CMPWU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater64_0(v *Value) bool { b := v.Block _ = b // match: (Greater64 x y) // cond: // result: (GreaterThan (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater64F_0(v *Value) bool { b := v.Block _ = b // match: (Greater64F x y) // cond: // result: (FGreaterThan (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FGreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater64U_0(v *Value) bool { b := v.Block _ = b // match: (Greater64U x y) // cond: // result: (GreaterThan (CMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Greater8 x y) // cond: // result: (GreaterThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater8U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Greater8U x y) // cond: // result: (GreaterThan (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpHmul32_0(v *Value) bool { // match: (Hmul32 x y) // cond: // result: (MULHW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULHW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpHmul32u_0(v *Value) bool { // match: (Hmul32u x y) // cond: // result: (MULHWU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULHWU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpHmul64_0(v *Value) bool { // match: (Hmul64 x y) // cond: // result: (MULHD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULHD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpHmul64u_0(v *Value) bool { // match: (Hmul64u x y) // cond: // result: (MULHDU x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULHDU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpInterCall_0(v *Value) bool { // match: (InterCall [argwid] entry mem) // cond: // result: (CALLinter [argwid] entry mem) for { argwid := v.AuxInt _ = v.Args[1] entry := v.Args[0] mem := v.Args[1] v.reset(OpPPC64CALLinter) v.AuxInt = argwid v.AddArg(entry) v.AddArg(mem) return true } } func rewriteValuePPC64_OpIsInBounds_0(v *Value) bool { b := v.Block _ = b // match: (IsInBounds idx len) // cond: // result: (LessThan (CMPU idx len)) for { _ = v.Args[1] idx := v.Args[0] len := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValuePPC64_OpIsNonNil_0(v *Value) bool { b := v.Block _ = b // match: (IsNonNil ptr) // cond: // result: (NotEqual (CMPconst [0] ptr)) for { ptr := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(ptr) v.AddArg(v0) return true } } func rewriteValuePPC64_OpIsSliceInBounds_0(v *Value) bool { b := v.Block _ = b // match: (IsSliceInBounds idx len) // cond: // result: (LessEqual (CMPU idx len)) for { _ = v.Args[1] idx := v.Args[0] len := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Leq16 x y) // cond: // result: (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq16U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Leq16U x y) // cond: // result: (LessEqual (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq32_0(v *Value) bool { b := v.Block _ = b // match: (Leq32 x y) // cond: // result: (LessEqual (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq32F_0(v *Value) bool { b := v.Block _ = b // match: (Leq32F x y) // cond: // result: (FLessEqual (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FLessEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq32U_0(v *Value) bool { b := v.Block _ = b // match: (Leq32U x y) // cond: // result: (LessEqual (CMPWU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq64_0(v *Value) bool { b := v.Block _ = b // match: (Leq64 x y) // cond: // result: (LessEqual (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq64F_0(v *Value) bool { b := v.Block _ = b // match: (Leq64F x y) // cond: // result: (FLessEqual (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FLessEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq64U_0(v *Value) bool { b := v.Block _ = b // match: (Leq64U x y) // cond: // result: (LessEqual (CMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Leq8 x y) // cond: // result: (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq8U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Leq8U x y) // cond: // result: (LessEqual (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Less16 x y) // cond: // result: (LessThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess16U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Less16U x y) // cond: // result: (LessThan (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess32_0(v *Value) bool { b := v.Block _ = b // match: (Less32 x y) // cond: // result: (LessThan (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess32F_0(v *Value) bool { b := v.Block _ = b // match: (Less32F x y) // cond: // result: (FLessThan (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FLessThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess32U_0(v *Value) bool { b := v.Block _ = b // match: (Less32U x y) // cond: // result: (LessThan (CMPWU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess64_0(v *Value) bool { b := v.Block _ = b // match: (Less64 x y) // cond: // result: (LessThan (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess64F_0(v *Value) bool { b := v.Block _ = b // match: (Less64F x y) // cond: // result: (FLessThan (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FLessThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess64U_0(v *Value) bool { b := v.Block _ = b // match: (Less64U x y) // cond: // result: (LessThan (CMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Less8 x y) // cond: // result: (LessThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess8U_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Less8U x y) // cond: // result: (LessThan (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLoad_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVDload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpPPC64MOVDload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) && isSigned(t) // result: (MOVWload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is32BitInt(t) && isSigned(t)) { break } v.reset(OpPPC64MOVWload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) && !isSigned(t) // result: (MOVWZload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is32BitInt(t) && !isSigned(t)) { break } v.reset(OpPPC64MOVWZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) && isSigned(t) // result: (MOVHload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is16BitInt(t) && isSigned(t)) { break } v.reset(OpPPC64MOVHload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) && !isSigned(t) // result: (MOVHZload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is16BitInt(t) && !isSigned(t)) { break } v.reset(OpPPC64MOVHZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: t.IsBoolean() // result: (MOVBZload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(t.IsBoolean()) { break } v.reset(OpPPC64MOVBZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is8BitInt(t) && isSigned(t) // result: (MOVBreg (MOVBZload ptr mem)) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is8BitInt(t) && isSigned(t)) { break } v.reset(OpPPC64MOVBreg) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Load ptr mem) // cond: is8BitInt(t) && !isSigned(t) // result: (MOVBZload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is8BitInt(t) && !isSigned(t)) { break } v.reset(OpPPC64MOVBZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (FMOVSload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is32BitFloat(t)) { break } v.reset(OpPPC64FMOVSload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (FMOVDload ptr mem) for { t := v.Type _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] if !(is64BitFloat(t)) { break } v.reset(OpPPC64FMOVDload) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpLsh16x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh16x16 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh16x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh16x32 x (Const64 [c])) // cond: uint32(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x32 x (MOVDconst [c])) // cond: uint32(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x32 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh16x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh16x64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh16x64 x (MOVDconst [c])) // cond: uint64(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x64 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh16x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh16x8 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh32x16 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh32x32 x (Const64 [c])) // cond: uint32(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x32 x (MOVDconst [c])) // cond: uint32(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x32 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh32x64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh32x64 x (MOVDconst [c])) // cond: uint64(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x64 x (AND y (MOVDconst [31]))) // cond: // result: (SLW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst { break } if v_1_1.AuxInt != 31 { break } v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh32x64 x (AND (MOVDconst [31]) y)) // cond: // result: (SLW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 31 { break } y := v_1.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh32x64 x (ANDconst [31] y)) // cond: // result: (SLW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst { break } if v_1.Type != typ.Int32 { break } if v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh32x64 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh32x8 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh64x16 x y) // cond: // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh64x32 x (Const64 [c])) // cond: uint32(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x32 x (MOVDconst [c])) // cond: uint32(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x32 x y) // cond: // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh64x64 x (Const64 [c])) // cond: uint64(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh64x64 x (MOVDconst [c])) // cond: uint64(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x64 x (AND y (MOVDconst [63]))) // cond: // result: (SLD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst { break } if v_1_1.AuxInt != 63 { break } v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh64x64 x (AND (MOVDconst [63]) y)) // cond: // result: (SLD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 63 { break } y := v_1.Args[1] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh64x64 x (ANDconst [63] y)) // cond: // result: (SLD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst { break } if v_1.Type != typ.Int64 { break } if v_1.AuxInt != 63 { break } y := v_1.Args[0] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh64x64 x y) // cond: // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh64x8 x y) // cond: // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh8x16 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh8x32 x (Const64 [c])) // cond: uint32(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x32 x (MOVDconst [c])) // cond: uint32(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x32 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh8x64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh8x64 x (MOVDconst [c])) // cond: uint64(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x64 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Lsh8x8 x y) // cond: // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod16 x y) // cond: // result: (Mod32 (SignExt16to32 x) (SignExt16to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpMod32) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMod16u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod16u x y) // cond: // result: (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpMod32u) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMod32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod32 x y) // cond: // result: (SUB x (MULLW y (DIVW x y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLW, typ.Int32) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVW, typ.Int32) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod32u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod32u x y) // cond: // result: (SUB x (MULLW y (DIVWU x y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLW, typ.Int32) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVWU, typ.Int32) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod64 x y) // cond: // result: (SUB x (MULLD y (DIVD x y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLD, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVD, typ.Int64) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod64u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod64u x y) // cond: // result: (SUB x (MULLD y (DIVDU x y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLD, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVDU, typ.Int64) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod8 x y) // cond: // result: (Mod32 (SignExt8to32 x) (SignExt8to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpMod32) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMod8u_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Mod8u x y) // cond: // result: (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpMod32u) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMove_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Move [0] _ _ mem) // cond: // result: mem for { if v.AuxInt != 0 { break } _ = v.Args[2] mem := v.Args[2] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Move [1] dst src mem) // cond: // result: (MOVBstore dst (MOVBZload src mem) mem) for { if v.AuxInt != 1 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVBstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [2] dst src mem) // cond: // result: (MOVHstore dst (MOVHZload src mem) mem) for { if v.AuxInt != 2 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVHstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [4] dst src mem) // cond: // result: (MOVWstore dst (MOVWZload src mem) mem) for { if v.AuxInt != 4 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVWstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [8] {t} dst src mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstore dst (MOVDload src mem) mem) for { if v.AuxInt != 8 { break } t := v.Aux _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, typ.Int64) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [8] dst src mem) // cond: // result: (MOVWstore [4] dst (MOVWZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem)) for { if v.AuxInt != 8 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVWstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [3] dst src mem) // cond: // result: (MOVBstore [2] dst (MOVBZload [2] src mem) (MOVHstore dst (MOVHload src mem) mem)) for { if v.AuxInt != 3 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVBstore) v.AuxInt = 2 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AuxInt = 2 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVHstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVHload, typ.Int16) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [5] dst src mem) // cond: // result: (MOVBstore [4] dst (MOVBZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem)) for { if v.AuxInt != 5 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVBstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [6] dst src mem) // cond: // result: (MOVHstore [4] dst (MOVHZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem)) for { if v.AuxInt != 6 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVHstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [7] dst src mem) // cond: // result: (MOVBstore [6] dst (MOVBZload [6] src mem) (MOVHstore [4] dst (MOVHZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem))) for { if v.AuxInt != 7 { break } _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] v.reset(OpPPC64MOVBstore) v.AuxInt = 6 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AuxInt = 6 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVHstore, types.TypeMem) v1.AuxInt = 4 v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16) v2.AuxInt = 4 v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v3.AddArg(dst) v4 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v4.AddArg(src) v4.AddArg(mem) v3.AddArg(v4) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } return false } func rewriteValuePPC64_OpMove_10(v *Value) bool { // match: (Move [s] dst src mem) // cond: s > 8 // result: (LoweredMove [s] dst src mem) for { s := v.AuxInt _ = v.Args[2] dst := v.Args[0] src := v.Args[1] mem := v.Args[2] if !(s > 8) { break } v.reset(OpPPC64LoweredMove) v.AuxInt = s v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpMul16_0(v *Value) bool { // match: (Mul16 x y) // cond: // result: (MULLW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul32_0(v *Value) bool { // match: (Mul32 x y) // cond: // result: (MULLW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul32F_0(v *Value) bool { // match: (Mul32F x y) // cond: // result: (FMULS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FMULS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul64_0(v *Value) bool { // match: (Mul64 x y) // cond: // result: (MULLD x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULLD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul64F_0(v *Value) bool { // match: (Mul64F x y) // cond: // result: (FMUL x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FMUL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul8_0(v *Value) bool { // match: (Mul8 x y) // cond: // result: (MULLW x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64MULLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpNeg16_0(v *Value) bool { // match: (Neg16 x) // cond: // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg32_0(v *Value) bool { // match: (Neg32 x) // cond: // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg32F_0(v *Value) bool { // match: (Neg32F x) // cond: // result: (FNEG x) for { x := v.Args[0] v.reset(OpPPC64FNEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg64_0(v *Value) bool { // match: (Neg64 x) // cond: // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg64F_0(v *Value) bool { // match: (Neg64F x) // cond: // result: (FNEG x) for { x := v.Args[0] v.reset(OpPPC64FNEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg8_0(v *Value) bool { // match: (Neg8 x) // cond: // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeq16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Neq16 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Neq16 x y) // cond: // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq32_0(v *Value) bool { b := v.Block _ = b // match: (Neq32 x y) // cond: // result: (NotEqual (CMPW x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq32F_0(v *Value) bool { b := v.Block _ = b // match: (Neq32F x y) // cond: // result: (NotEqual (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq64_0(v *Value) bool { b := v.Block _ = b // match: (Neq64 x y) // cond: // result: (NotEqual (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq64F_0(v *Value) bool { b := v.Block _ = b // match: (Neq64F x y) // cond: // result: (NotEqual (FCMPU x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Neq8 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Neq8 x y) // cond: // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeqB_0(v *Value) bool { // match: (NeqB x y) // cond: // result: (XOR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpNeqPtr_0(v *Value) bool { b := v.Block _ = b // match: (NeqPtr x y) // cond: // result: (NotEqual (CMP x y)) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNilCheck_0(v *Value) bool { // match: (NilCheck ptr mem) // cond: // result: (LoweredNilCheck ptr mem) for { _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64LoweredNilCheck) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpNot_0(v *Value) bool { // match: (Not x) // cond: // result: (XORconst [1] x) for { x := v.Args[0] v.reset(OpPPC64XORconst) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValuePPC64_OpOffPtr_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (OffPtr [off] ptr) // cond: // result: (ADD (MOVDconst [off]) ptr) for { off := v.AuxInt ptr := v.Args[0] v.reset(OpPPC64ADD) v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = off v.AddArg(v0) v.AddArg(ptr) return true } } func rewriteValuePPC64_OpOr16_0(v *Value) bool { // match: (Or16 x y) // cond: // result: (OR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOr32_0(v *Value) bool { // match: (Or32 x y) // cond: // result: (OR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOr64_0(v *Value) bool { // match: (Or64 x y) // cond: // result: (OR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOr8_0(v *Value) bool { // match: (Or8 x y) // cond: // result: (OR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOrB_0(v *Value) bool { // match: (OrB x y) // cond: // result: (OR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpPPC64ADD_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (ADD (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLDconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (SRDconst x [d]) (SLDconst x [c])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLDconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLWconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (SRWconst x [d]) (SLWconst x [c])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLWconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // cond: // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst { break } if v_0_1.Type != typ.Int64 { break } if v_0_1.AuxInt != 63 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 64 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst { break } if v_1_1_1.Type != typ.UInt { break } if v_1_1_1.AuxInt != 63 { break } if y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (ADD (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) // cond: // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB { break } if v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst { break } if v_0_1_0.AuxInt != 64 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst { break } if v_0_1_1.Type != typ.UInt { break } if v_0_1_1.AuxInt != 63 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.Int64 { break } if v_1_1.AuxInt != 63 { break } if y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (ADD (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // cond: // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst { break } if v_0_1.Type != typ.Int32 { break } if v_0_1.AuxInt != 31 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 32 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst { break } if v_1_1_1.Type != typ.UInt { break } if v_1_1_1.AuxInt != 31 { break } if y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (ADD (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) // cond: // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB { break } if v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst { break } if v_0_1_0.AuxInt != 32 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst { break } if v_0_1_1.Type != typ.UInt { break } if v_0_1_1.AuxInt != 31 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.Int32 { break } if v_1_1.AuxInt != 31 { break } if y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (ADD x (MOVDconst [c])) // cond: is32Bit(c) // result: (ADDconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (MOVDconst [c]) x) // cond: is32Bit(c) // result: (ADDconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt x := v.Args[1] if !(is32Bit(c)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ADDconst_0(v *Value) bool { // match: (ADDconst [c] (ADDconst [d] x)) // cond: is32Bit(c+d) // result: (ADDconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = c + d v.AddArg(x) return true } // match: (ADDconst [0] x) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDconst [c] (MOVDaddr [d] {sym} x)) // cond: // result: (MOVDaddr [c+d] {sym} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDaddr { break } d := v_0.AuxInt sym := v_0.Aux x := v_0.Args[0] v.reset(OpPPC64MOVDaddr) v.AuxInt = c + d v.Aux = sym v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64AND_0(v *Value) bool { // match: (AND x (NOR y y)) // cond: // result: (ANDN x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64NOR { break } _ = v_1.Args[1] y := v_1.Args[0] if y != v_1.Args[1] { break } v.reset(OpPPC64ANDN) v.AddArg(x) v.AddArg(y) return true } // match: (AND (NOR y y) x) // cond: // result: (ANDN x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64NOR { break } _ = v_0.Args[1] y := v_0.Args[0] if y != v_0.Args[1] { break } x := v.Args[1] v.reset(OpPPC64ANDN) v.AddArg(x) v.AddArg(y) return true } // match: (AND (MOVDconst [c]) (MOVDconst [d])) // cond: // result: (MOVDconst [c&d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } d := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c & d return true } // match: (AND (MOVDconst [d]) (MOVDconst [c])) // cond: // result: (MOVDconst [c&d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c & d return true } // match: (AND x (MOVDconst [c])) // cond: isU16Bit(c) // result: (ANDconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64ANDconst) v.AuxInt = c v.AddArg(x) return true } // match: (AND (MOVDconst [c]) x) // cond: isU16Bit(c) // result: (ANDconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt x := v.Args[1] if !(isU16Bit(c)) { break } v.reset(OpPPC64ANDconst) v.AuxInt = c v.AddArg(x) return true } // match: (AND (MOVDconst [c]) x:(MOVBZload _ _)) // cond: // result: (ANDconst [c&0xFF] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt x := v.Args[1] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } // match: (AND x:(MOVBZload _ _) (MOVDconst [c])) // cond: // result: (ANDconst [c&0xFF] x) for { _ = v.Args[1] x := v.Args[0] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } // match: (AND x:(MOVBZload _ _) (MOVDconst [c])) // cond: // result: (ANDconst [c&0xFF] x) for { _ = v.Args[1] x := v.Args[0] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } // match: (AND (MOVDconst [c]) x:(MOVBZload _ _)) // cond: // result: (ANDconst [c&0xFF] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt x := v.Args[1] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ANDconst_0(v *Value) bool { // match: (ANDconst [c] (ANDconst [d] x)) // cond: // result: (ANDconst [c&d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64ANDconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDconst [-1] x) // cond: // result: x for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDconst [0] _) // cond: // result: (MOVDconst [0]) for { if v.AuxInt != 0 { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ANDconst [c] y:(MOVBZreg _)) // cond: c&0xFF == 0xFF // result: y for { c := v.AuxInt y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } if !(c&0xFF == 0xFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [c] y:(MOVHZreg _)) // cond: c&0xFFFF == 0xFFFF // result: y for { c := v.AuxInt y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } if !(c&0xFFFF == 0xFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [c] y:(MOVWZreg _)) // cond: c&0xFFFFFFFF == 0xFFFFFFFF // result: y for { c := v.AuxInt y := v.Args[0] if y.Op != OpPPC64MOVWZreg { break } if !(c&0xFFFFFFFF == 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [c] (MOVBZreg x)) // cond: // result: (ANDconst [c&0xFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBZreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } // match: (ANDconst [c] (MOVHZreg x)) // cond: // result: (ANDconst [c&0xFFFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVHZreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFFFF v.AddArg(x) return true } // match: (ANDconst [c] (MOVWZreg x)) // cond: // result: (ANDconst [c&0xFFFFFFFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWZreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFFFFFFFF v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64CMP_0(v *Value) bool { b := v.Block _ = b // match: (CMP x (MOVDconst [c])) // cond: is16Bit(c) // result: (CMPconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64CMPconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMP (MOVDconst [c]) y) // cond: is16Bit(c) // result: (InvertFlags (CMPconst y [c])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt y := v.Args[1] if !(is16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPU_0(v *Value) bool { b := v.Block _ = b // match: (CMPU x (MOVDconst [c])) // cond: isU16Bit(c) // result: (CMPUconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64CMPUconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPU (MOVDconst [c]) y) // cond: isU16Bit(c) // result: (InvertFlags (CMPUconst y [c])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt y := v.Args[1] if !(isU16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPUconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPUconst_0(v *Value) bool { // match: (CMPUconst (MOVDconst [x]) [y]) // cond: int64(x)==int64(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int64(x) == int64(y)) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPUconst (MOVDconst [x]) [y]) // cond: uint64(x)uint64(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(uint64(x) > uint64(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64CMPW_0(v *Value) bool { b := v.Block _ = b // match: (CMPW x (MOVWreg y)) // cond: // result: (CMPW x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } y := v_1.Args[0] v.reset(OpPPC64CMPW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPW (MOVWreg x) y) // cond: // result: (CMPW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWreg { break } x := v_0.Args[0] y := v.Args[1] v.reset(OpPPC64CMPW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPW x (MOVDconst [c])) // cond: is16Bit(c) // result: (CMPWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64CMPWconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPW (MOVDconst [c]) y) // cond: is16Bit(c) // result: (InvertFlags (CMPWconst y [c])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt y := v.Args[1] if !(is16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPWconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPWU_0(v *Value) bool { b := v.Block _ = b // match: (CMPWU x (MOVWZreg y)) // cond: // result: (CMPWU x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } y := v_1.Args[0] v.reset(OpPPC64CMPWU) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWU (MOVWZreg x) y) // cond: // result: (CMPWU x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWZreg { break } x := v_0.Args[0] y := v.Args[1] v.reset(OpPPC64CMPWU) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWU x (MOVDconst [c])) // cond: isU16Bit(c) // result: (CMPWUconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64CMPWUconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPWU (MOVDconst [c]) y) // cond: isU16Bit(c) // result: (InvertFlags (CMPWUconst y [c])) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt y := v.Args[1] if !(isU16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPWUconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPWUconst_0(v *Value) bool { // match: (CMPWUconst (MOVDconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPWUconst (MOVDconst [x]) [y]) // cond: uint32(x)uint32(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(uint32(x) > uint32(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64CMPWconst_0(v *Value) bool { // match: (CMPWconst (MOVDconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPWconst (MOVDconst [x]) [y]) // cond: int32(x)int32(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int32(x) > int32(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64CMPconst_0(v *Value) bool { // match: (CMPconst (MOVDconst [x]) [y]) // cond: int64(x)==int64(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int64(x) == int64(y)) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPconst (MOVDconst [x]) [y]) // cond: int64(x)int64(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int64(x) > int64(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64Equal_0(v *Value) bool { // match: (Equal (FlagEQ)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (Equal (FlagLT)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Equal (FlagGT)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Equal (InvertFlags x)) // cond: // result: (Equal x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64Equal) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64FABS_0(v *Value) bool { // match: (FABS (FMOVDconst [x])) // cond: // result: (FMOVDconst [f2i(math.Abs(i2f(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = f2i(math.Abs(i2f(x))) return true } return false } func rewriteValuePPC64_OpPPC64FADD_0(v *Value) bool { // match: (FADD (FMUL x y) z) // cond: // result: (FMADD x y z) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMUL { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] z := v.Args[1] v.reset(OpPPC64FMADD) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } // match: (FADD z (FMUL x y)) // cond: // result: (FMADD x y z) for { _ = v.Args[1] z := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64FMUL { break } _ = v_1.Args[1] x := v_1.Args[0] y := v_1.Args[1] v.reset(OpPPC64FMADD) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FADDS_0(v *Value) bool { // match: (FADDS (FMULS x y) z) // cond: // result: (FMADDS x y z) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMULS { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] z := v.Args[1] v.reset(OpPPC64FMADDS) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } // match: (FADDS z (FMULS x y)) // cond: // result: (FMADDS x y z) for { _ = v.Args[1] z := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64FMULS { break } _ = v_1.Args[1] x := v_1.Args[0] y := v_1.Args[1] v.reset(OpPPC64FMADDS) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FCEIL_0(v *Value) bool { // match: (FCEIL (FMOVDconst [x])) // cond: // result: (FMOVDconst [f2i(math.Ceil(i2f(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = f2i(math.Ceil(i2f(x))) return true } return false } func rewriteValuePPC64_OpPPC64FFLOOR_0(v *Value) bool { // match: (FFLOOR (FMOVDconst [x])) // cond: // result: (FMOVDconst [f2i(math.Floor(i2f(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = f2i(math.Floor(i2f(x))) return true } return false } func rewriteValuePPC64_OpPPC64FMOVDload_0(v *Value) bool { // match: (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr x _)) // cond: // result: (MTVSRD x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDstore { break } if v_1.AuxInt != off { break } if v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } x := v_1.Args[1] v.reset(OpPPC64MTVSRD) v.AddArg(x) return true } // match: (FMOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is16Bit(off1+off2) // result: (FMOVDload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FMOVDstore_0(v *Value) bool { // match: (FMOVDstore [off] {sym} ptr (MTVSRD x) mem) // cond: // result: (MOVDstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MTVSRD { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVDstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is16Bit(off1+off2) // result: (FMOVDstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (FMOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] mem := v.Args[2] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FMOVSload_0(v *Value) bool { // match: (FMOVSload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is16Bit(off1+off2) // result: (FMOVSload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FMOVSstore_0(v *Value) bool { // match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is16Bit(off1+off2) // result: (FMOVSstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVSstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (FMOVSstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] mem := v.Args[2] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVSstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FNEG_0(v *Value) bool { // match: (FNEG (FABS x)) // cond: // result: (FNABS x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FABS { break } x := v_0.Args[0] v.reset(OpPPC64FNABS) v.AddArg(x) return true } // match: (FNEG (FNABS x)) // cond: // result: (FABS x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FNABS { break } x := v_0.Args[0] v.reset(OpPPC64FABS) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64FSQRT_0(v *Value) bool { // match: (FSQRT (FMOVDconst [x])) // cond: // result: (FMOVDconst [f2i(math.Sqrt(i2f(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = f2i(math.Sqrt(i2f(x))) return true } return false } func rewriteValuePPC64_OpPPC64FSUB_0(v *Value) bool { // match: (FSUB (FMUL x y) z) // cond: // result: (FMSUB x y z) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMUL { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] z := v.Args[1] v.reset(OpPPC64FMSUB) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FSUBS_0(v *Value) bool { // match: (FSUBS (FMULS x y) z) // cond: // result: (FMSUBS x y z) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMULS { break } _ = v_0.Args[1] x := v_0.Args[0] y := v_0.Args[1] z := v.Args[1] v.reset(OpPPC64FMSUBS) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FTRUNC_0(v *Value) bool { // match: (FTRUNC (FMOVDconst [x])) // cond: // result: (FMOVDconst [f2i(math.Trunc(i2f(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = f2i(math.Trunc(i2f(x))) return true } return false } func rewriteValuePPC64_OpPPC64GreaterEqual_0(v *Value) bool { // match: (GreaterEqual (FlagEQ)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (GreaterEqual (FlagLT)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (GreaterEqual (FlagGT)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (GreaterEqual (InvertFlags x)) // cond: // result: (LessEqual x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64LessEqual) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64GreaterThan_0(v *Value) bool { // match: (GreaterThan (FlagEQ)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (GreaterThan (FlagLT)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (GreaterThan (FlagGT)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (GreaterThan (InvertFlags x)) // cond: // result: (LessThan x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64LessThan) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64LessEqual_0(v *Value) bool { // match: (LessEqual (FlagEQ)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (LessEqual (FlagLT)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (LessEqual (FlagGT)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (LessEqual (InvertFlags x)) // cond: // result: (GreaterEqual x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64GreaterEqual) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64LessThan_0(v *Value) bool { // match: (LessThan (FlagEQ)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (LessThan (FlagLT)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (LessThan (FlagGT)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (LessThan (InvertFlags x)) // cond: // result: (GreaterThan x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64GreaterThan) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MFVSRD_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (MFVSRD (FMOVDconst [c])) // cond: // result: (MOVDconst [c]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c return true } // match: (MFVSRD x:(FMOVDload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVDload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpPPC64FMOVDload { break } off := x.AuxInt sym := x.Aux _ = x.Args[1] ptr := x.Args[0] mem := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, typ.Int64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBZload_0(v *Value) bool { // match: (MOVBZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVBZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVBZload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBZload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVBZload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVBZload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBZreg_0(v *Value) bool { // match: (MOVBZreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBZreg y:(MOVBZreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBZreg (MOVBreg x)) // cond: // result: (MOVBZreg x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBreg { break } x := v_0.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } // match: (MOVBZreg x:(MOVBZload _ _)) // cond: // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVBZreg (MOVDconst [c])) // cond: // result: (MOVDconst [int64(uint8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(uint8(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVBreg_0(v *Value) bool { // match: (MOVBreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0x7F // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0x7F) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBreg y:(MOVBreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBreg (MOVBZreg x)) // cond: // result: (MOVBreg x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBZreg { break } x := v_0.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } // match: (MOVBreg (MOVDconst [c])) // cond: // result: (MOVDconst [int64(int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(int8(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstore_0(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (MOVBstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] mem := v.Args[2] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVDconst [c]) mem) // cond: c == 0 // result: (MOVBstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt mem := v.Args[2] if !(c == 0) { break } v.reset(OpPPC64MOVBstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem) // cond: // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVBreg { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBZreg x) mem) // cond: // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVBZreg { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [i1] {s} p (SRWconst (MOVHZreg w) [8]) x0:(MOVBstore [i0] {s} p w mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0) // result: (MOVHstore [i0] {s} p w mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } if v_1.AuxInt != 8 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVHZreg { break } w := v_1_0.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } if w != x0.Args[1] { break } mem := x0.Args[2] if !(!config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i3] {s} p (SRWconst w [24]) x0:(MOVBstore [i2] {s} p (SRWconst w [16]) x1:(MOVBstore [i1] {s} p (SRWconst w [8]) x2:(MOVBstore [i0] {s} p w mem)))) // cond: !config.BigEndian && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && clobber(x0) && clobber(x1) && clobber(x2) // result: (MOVWstore [i0] {s} p w mem) for { i3 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } if v_1.AuxInt != 24 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i2 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRWconst { break } if x0_1.AuxInt != 16 { break } if w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpPPC64MOVBstore { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpPPC64SRWconst { break } if x1_1.AuxInt != 8 { break } if w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpPPC64MOVBstore { break } i0 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } if w != x2.Args[1] { break } mem := x2.Args[2] if !(!config.BigEndian && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && clobber(x0) && clobber(x1) && clobber(x2)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i7] {s} p (SRDconst w [56]) x0:(MOVBstore [i6] {s} p (SRDconst w [48]) x1:(MOVBstore [i5] {s} p (SRDconst w [40]) x2:(MOVBstore [i4] {s} p (SRDconst w [32]) x3:(MOVBstore [i3] {s} p (SRDconst w [24]) x4:(MOVBstore [i2] {s} p (SRDconst w [16]) x5:(MOVBstore [i1] {s} p (SRDconst w [8]) x6:(MOVBstore [i0] {s} p w mem)))))))) // cond: !config.BigEndian && i0%4 == 0 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) // result: (MOVDstore [i0] {s} p w mem) for { i7 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst { break } if v_1.AuxInt != 56 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i6 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRDconst { break } if x0_1.AuxInt != 48 { break } if w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpPPC64MOVBstore { break } i5 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpPPC64SRDconst { break } if x1_1.AuxInt != 40 { break } if w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpPPC64MOVBstore { break } i4 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpPPC64SRDconst { break } if x2_1.AuxInt != 32 { break } if w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpPPC64MOVBstore { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpPPC64SRDconst { break } if x3_1.AuxInt != 24 { break } if w != x3_1.Args[0] { break } x4 := x3.Args[2] if x4.Op != OpPPC64MOVBstore { break } i2 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpPPC64SRDconst { break } if x4_1.AuxInt != 16 { break } if w != x4_1.Args[0] { break } x5 := x4.Args[2] if x5.Op != OpPPC64MOVBstore { break } i1 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpPPC64SRDconst { break } if x5_1.AuxInt != 8 { break } if w != x5_1.Args[0] { break } x6 := x5.Args[2] if x6.Op != OpPPC64MOVBstore { break } i0 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[2] if p != x6.Args[0] { break } if w != x6.Args[1] { break } mem := x6.Args[2] if !(!config.BigEndian && i0%4 == 0 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstorezero_0(v *Value) bool { // match: (MOVBstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVBstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVBstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVBstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDload_0(v *Value) bool { // match: (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr x _)) // cond: // result: (MFVSRD x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64FMOVDstore { break } if v_1.AuxInt != off { break } if v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } x := v_1.Args[1] v.reset(OpPPC64MFVSRD) v.AddArg(x) return true } // match: (MOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVDload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVDload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDstore_0(v *Value) bool { // match: (MOVDstore [off] {sym} ptr (MFVSRD x) mem) // cond: // result: (FMOVDstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MFVSRD { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64FMOVDstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVDstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVDstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] mem := v.Args[2] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVDstore [off] {sym} ptr (MOVDconst [c]) mem) // cond: c == 0 // result: (MOVDstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt mem := v.Args[2] if !(c == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDstorezero_0(v *Value) bool { // match: (MOVDstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVDstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVDstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHZload_0(v *Value) bool { // match: (MOVHZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVHZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHZload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHZload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVHZload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHZload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHZreg_0(v *Value) bool { // match: (MOVHZreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg y:(MOVHZreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg y:(MOVBZreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg y:(MOVHreg x)) // cond: // result: (MOVHZreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } x := y.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } // match: (MOVHZreg x:(MOVHZload _ _)) // cond: // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHZreg (MOVDconst [c])) // cond: // result: (MOVDconst [int64(uint16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(uint16(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVHload_0(v *Value) bool { // match: (MOVHload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVHload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHreg_0(v *Value) bool { // match: (MOVHreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0x7FFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0x7FFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHreg y:(MOVHreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHreg y:(MOVBreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHreg y:(MOVHZreg x)) // cond: // result: (MOVHreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } x := y.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHload _ _)) // cond: // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHreg (MOVDconst [c])) // cond: // result: (MOVDconst [int64(int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(int16(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVHstore_0(v *Value) bool { // match: (MOVHstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVHstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] mem := v.Args[2] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVDconst [c]) mem) // cond: c == 0 // result: (MOVHstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt mem := v.Args[2] if !(c == 0) { break } v.reset(OpPPC64MOVHstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem) // cond: // result: (MOVHstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHreg { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVHstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHZreg x) mem) // cond: // result: (MOVHstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHZreg { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVHstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHstorezero_0(v *Value) bool { // match: (MOVHstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVHstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZload_0(v *Value) bool { // match: (MOVWZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVWZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWZload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWZload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVWZload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWZload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZreg_0(v *Value) bool { // match: (MOVWZreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFFFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(AND (MOVDconst [c]) _)) // cond: uint64(c) <= 0xFFFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] y_0 := y.Args[0] if y_0.Op != OpPPC64MOVDconst { break } c := y_0.AuxInt if !(uint64(c) <= 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(AND _ (MOVDconst [c]))) // cond: uint64(c) <= 0xFFFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] y_1 := y.Args[1] if y_1.Op != OpPPC64MOVDconst { break } c := y_1.AuxInt if !(uint64(c) <= 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVWZreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVWZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVHZreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVBZreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVWreg x)) // cond: // result: (MOVWZreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVWreg { break } x := y.Args[0] v.reset(OpPPC64MOVWZreg) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MOVWload_0(v *Value) bool { // match: (MOVWload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVWload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWreg_0(v *Value) bool { // match: (MOVWreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(AND (MOVDconst [c]) _)) // cond: uint64(c) <= 0x7FFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] y_0 := y.Args[0] if y_0.Op != OpPPC64MOVDconst { break } c := y_0.AuxInt if !(uint64(c) <= 0x7FFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(AND _ (MOVDconst [c]))) // cond: uint64(c) <= 0x7FFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] y_1 := y.Args[1] if y_1.Op != OpPPC64MOVDconst { break } c := y_1.AuxInt if !(uint64(c) <= 0x7FFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(MOVWreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVWreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(MOVHreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(MOVBreg _)) // cond: // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(MOVWZreg x)) // cond: // result: (MOVWreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVWZreg { break } x := y.Args[0] v.reset(OpPPC64MOVWreg) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MOVWstore_0(v *Value) bool { // match: (MOVWstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] mem := v.Args[2] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] mem := v.Args[2] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVDconst [c]) mem) // cond: c == 0 // result: (MOVWstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt mem := v.Args[2] if !(c == 0) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem) // cond: // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWZreg x) mem) // cond: // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } x := v_1.Args[0] mem := v.Args[2] v.reset(OpPPC64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWstorezero_0(v *Value) bool { // match: (MOVWstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVWstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] mem := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] mem := v.Args[1] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MTVSRD_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (MTVSRD (MOVDconst [c])) // cond: // result: (FMOVDconst [c]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = c return true } // match: (MTVSRD x:(MOVDload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (FMOVDload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpPPC64MOVDload { break } off := x.AuxInt sym := x.Aux _ = x.Args[1] ptr := x.Args[0] mem := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpPPC64FMOVDload, typ.Float64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MaskIfNotCarry_0(v *Value) bool { // match: (MaskIfNotCarry (ADDconstForCarry [c] (ANDconst [d] _))) // cond: c < 0 && d > 0 && c + d < 0 // result: (MOVDconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconstForCarry { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } d := v_0_0.AuxInt if !(c < 0 && d > 0 && c+d < 0) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = -1 return true } return false } func rewriteValuePPC64_OpPPC64NotEqual_0(v *Value) bool { // match: (NotEqual (FlagEQ)) // cond: // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (NotEqual (FlagLT)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (NotEqual (FlagGT)) // cond: // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (NotEqual (InvertFlags x)) // cond: // result: (NotEqual x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64NotEqual) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64OR_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (OR (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLDconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (SRDconst x [d]) (SLDconst x [c])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLDconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLWconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (SRWconst x [d]) (SLWconst x [c])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLWconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // cond: // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst { break } if v_0_1.Type != typ.Int64 { break } if v_0_1.AuxInt != 63 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 64 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst { break } if v_1_1_1.Type != typ.UInt { break } if v_1_1_1.AuxInt != 63 { break } if y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (OR (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) // cond: // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB { break } if v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst { break } if v_0_1_0.AuxInt != 64 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst { break } if v_0_1_1.Type != typ.UInt { break } if v_0_1_1.AuxInt != 63 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.Int64 { break } if v_1_1.AuxInt != 63 { break } if y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (OR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // cond: // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst { break } if v_0_1.Type != typ.Int32 { break } if v_0_1.AuxInt != 31 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 32 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst { break } if v_1_1_1.Type != typ.UInt { break } if v_1_1_1.AuxInt != 31 { break } if y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (OR (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) // cond: // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB { break } if v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst { break } if v_0_1_0.AuxInt != 32 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst { break } if v_0_1_1.Type != typ.UInt { break } if v_0_1_1.AuxInt != 31 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.Int32 { break } if v_1_1.AuxInt != 31 { break } if y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (OR (MOVDconst [c]) (MOVDconst [d])) // cond: // result: (MOVDconst [c|d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } d := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c | d return true } // match: (OR (MOVDconst [d]) (MOVDconst [c])) // cond: // result: (MOVDconst [c|d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c | d return true } return false } func rewriteValuePPC64_OpPPC64OR_10(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR x (MOVDconst [c])) // cond: isU32Bit(c) // result: (ORconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU32Bit(c)) { break } v.reset(OpPPC64ORconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (MOVDconst [c]) x) // cond: isU32Bit(c) // result: (ORconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt x := v.Args[1] if !(isU32Bit(c)) { break } v.reset(OpPPC64ORconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR x0:(MOVBZload [i0] {s} p mem) o1:(SLWconst x1:(MOVBZload [i1] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[1] p := x0.Args[0] mem := x0.Args[1] o1 := v.Args[1] if o1.Op != OpPPC64SLWconst { break } if o1.AuxInt != 8 { break } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } if !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o1:(SLWconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o1 := v.Args[0] if o1.Op != OpPPC64SLWconst { break } if o1.AuxInt != 8 { break } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt s := x1.Aux _ = x1.Args[1] p := x1.Args[0] mem := x1.Args[1] x0 := v.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } if !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpPPC64SLWconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[1] p := x2.Args[0] mem := x2.Args[1] o0 := v.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLWconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVHZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } if !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpPPC64SLWconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt s := x2.Aux _ = x2.Args[1] p := x2.Args[0] mem := x2.Args[1] o0 := v.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVHZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLWconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } if !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem)) s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24])) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLWconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt s := x1.Aux _ = x1.Args[1] p := x1.Args[0] mem := x1.Args[1] x0 := o0.Args[1] if x0.Op != OpPPC64MOVHZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := v.Args[1] if s1.Op != OpPPC64SLWconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } if !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16])) s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24])) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVHZload { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[1] p := x0.Args[0] mem := x0.Args[1] s0 := o0.Args[1] if s0.Op != OpPPC64SLWconst { break } if s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := v.Args[1] if s1.Op != OpPPC64SLWconst { break } if s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } if !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_20(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_30(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_40(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_50(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_60(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_70(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_80(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux _ = x7.Args[1] p := x7.Args[0] mem := x7.Args[1] o5 := v.Args[1] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_90(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_100(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_110(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux _ = x6.Args[1] p := x6.Args[0] mem := x6.Args[1] o4 := o5.Args[1] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_120(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux _ = x5.Args[1] p := x5.Args[0] mem := x5.Args[1] o3 := o4.Args[1] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_130(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt s := x4.Aux _ = x4.Args[1] p := x4.Args[0] mem := x4.Args[1] o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt s := x4.Aux _ = x4.Args[1] p := x4.Args[0] mem := x4.Args[1] o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt s := x4.Aux _ = x4.Args[1] p := x4.Args[0] mem := x4.Args[1] o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt s := x4.Aux _ = x4.Args[1] p := x4.Args[0] mem := x4.Args[1] o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt s := x4.Aux _ = x4.Args[1] p := x4.Args[0] mem := x4.Args[1] o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt s := x4.Aux _ = x4.Args[1] p := x4.Args[0] mem := x4.Args[1] o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt s := x4.Aux _ = x4.Args[1] p := x4.Args[0] mem := x4.Args[1] o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt s := x4.Aux _ = x4.Args[1] p := x4.Args[0] mem := x4.Args[1] o2 := o3.Args[1] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt s := x3.Aux _ = x3.Args[1] p := x3.Args[0] mem := x3.Args[1] o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt s := x3.Aux _ = x3.Args[1] p := x3.Args[0] mem := x3.Args[1] o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_140(v *Value) bool { b := v.Block _ = b config := b.Func.Config _ = config // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt s := x3.Aux _ = x3.Args[1] p := x3.Args[0] mem := x3.Args[1] o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] s2 := o2.Args[0] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt s := x3.Aux _ = x3.Args[1] p := x3.Args[0] mem := x3.Args[1] o1 := o2.Args[1] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt s := x2.Aux _ = x2.Args[1] p := x2.Args[0] mem := x2.Args[1] o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] s1 := o1.Args[0] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt s := x2.Aux _ = x2.Args[1] p := x2.Args[0] mem := x2.Args[1] o0 := o1.Args[1] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt s := x1.Aux _ = x1.Args[1] p := x1.Args[0] mem := x1.Args[1] x0 := o0.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] { break } if mem != x0.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR { break } if o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR { break } if o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR { break } if o3.Type != t { break } _ = o3.Args[1] o2 := o3.Args[0] if o2.Op != OpPPC64OR { break } if o2.Type != t { break } _ = o2.Args[1] o1 := o2.Args[0] if o1.Op != OpPPC64OR { break } if o1.Type != t { break } _ = o1.Args[1] o0 := o1.Args[0] if o0.Op != OpPPC64OR { break } if o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt s := x0.Aux _ = x0.Args[1] p := x0.Args[0] mem := x0.Args[1] s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst { break } if s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] { break } if mem != x1.Args[1] { break } s1 := o1.Args[1] if s1.Op != OpPPC64SLDconst { break } if s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] { break } if mem != x2.Args[1] { break } s2 := o2.Args[1] if s2.Op != OpPPC64SLDconst { break } if s2.AuxInt != 24 { break } x3 := s2.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] { break } if mem != x3.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst { break } if s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] { break } if mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst { break } if s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] { break } if mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst { break } if s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] { break } if mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst { break } if s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] { break } if mem != x7.Args[1] { break } if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64ORN_0(v *Value) bool { // match: (ORN x (MOVDconst [-1])) // cond: // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } if v_1.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ORconst_0(v *Value) bool { // match: (ORconst [c] (ORconst [d] x)) // cond: // result: (ORconst [c|d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64ORconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpPPC64ORconst) v.AuxInt = c | d v.AddArg(x) return true } // match: (ORconst [-1] _) // cond: // result: (MOVDconst [-1]) for { if v.AuxInt != -1 { break } v.reset(OpPPC64MOVDconst) v.AuxInt = -1 return true } // match: (ORconst [0] x) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64SUB_0(v *Value) bool { // match: (SUB x (MOVDconst [c])) // cond: is32Bit(-c) // result: (ADDconst [-c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is32Bit(-c)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = -c v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64XOR_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (XOR (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLDconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (SRDconst x [d]) (SLDconst x [c])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLDconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLWconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (SRWconst x [d]) (SLWconst x [c])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLWconst { break } c := v_1.AuxInt if x != v_1.Args[0] { break } if !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // cond: // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst { break } if v_0_1.Type != typ.Int64 { break } if v_0_1.AuxInt != 63 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 64 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst { break } if v_1_1_1.Type != typ.UInt { break } if v_1_1_1.AuxInt != 63 { break } if y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (XOR (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) // cond: // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB { break } if v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst { break } if v_0_1_0.AuxInt != 64 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst { break } if v_0_1_1.Type != typ.UInt { break } if v_0_1_1.AuxInt != 63 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.Int64 { break } if v_1_1.AuxInt != 63 { break } if y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (XOR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // cond: // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst { break } if v_0_1.Type != typ.Int32 { break } if v_0_1.AuxInt != 31 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 32 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst { break } if v_1_1_1.Type != typ.UInt { break } if v_1_1_1.AuxInt != 31 { break } if y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (XOR (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) // cond: // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB { break } if v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst { break } if v_0_1_0.AuxInt != 32 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst { break } if v_0_1_1.Type != typ.UInt { break } if v_0_1_1.AuxInt != 31 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.Int32 { break } if v_1_1.AuxInt != 31 { break } if y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (XOR (MOVDconst [c]) (MOVDconst [d])) // cond: // result: (MOVDconst [c^d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } d := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c ^ d return true } // match: (XOR (MOVDconst [d]) (MOVDconst [c])) // cond: // result: (MOVDconst [c^d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c ^ d return true } return false } func rewriteValuePPC64_OpPPC64XOR_10(v *Value) bool { // match: (XOR x (MOVDconst [c])) // cond: isU32Bit(c) // result: (XORconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU32Bit(c)) { break } v.reset(OpPPC64XORconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (MOVDconst [c]) x) // cond: isU32Bit(c) // result: (XORconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt x := v.Args[1] if !(isU32Bit(c)) { break } v.reset(OpPPC64XORconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64XORconst_0(v *Value) bool { // match: (XORconst [c] (XORconst [d] x)) // cond: // result: (XORconst [c^d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64XORconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpPPC64XORconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORconst [0] x) // cond: // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPopCount16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (PopCount16 x) // cond: // result: (POPCNTW (MOVHZreg x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpPopCount32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (PopCount32 x) // cond: // result: (POPCNTW (MOVWZreg x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpPopCount64_0(v *Value) bool { // match: (PopCount64 x) // cond: // result: (POPCNTD x) for { x := v.Args[0] v.reset(OpPPC64POPCNTD) v.AddArg(x) return true } } func rewriteValuePPC64_OpPopCount8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (PopCount8 x) // cond: // result: (POPCNTB (MOVBreg x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTB) v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRound32F_0(v *Value) bool { // match: (Round32F x) // cond: // result: (LoweredRound32F x) for { x := v.Args[0] v.reset(OpPPC64LoweredRound32F) v.AddArg(x) return true } } func rewriteValuePPC64_OpRound64F_0(v *Value) bool { // match: (Round64F x) // cond: // result: (LoweredRound64F x) for { x := v.Args[0] v.reset(OpPPC64LoweredRound64F) v.AddArg(x) return true } } func rewriteValuePPC64_OpRsh16Ux16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16Ux16 x y) // cond: // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16Ux32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16Ux32 x (Const64 [c])) // cond: uint32(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux32 x (MOVDconst [c])) // cond: uint32(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux32 x y) // cond: // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16Ux64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16Ux64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh16Ux64 x (MOVDconst [c])) // cond: uint64(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux64 x y) // cond: // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16Ux8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16Ux8 x y) // cond: // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16x16 x y) // cond: // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16x32 x (Const64 [c])) // cond: uint32(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x32 x (MOVDconst [c])) // cond: uint32(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x32 x y) // cond: // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16x64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x64 x (Const64 [c])) // cond: uint64(c) >= 16 // result: (SRAWconst (SignExt16to32 x) [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x64 x (MOVDconst [c])) // cond: uint64(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x64 x y) // cond: // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh16x8 x y) // cond: // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh32Ux16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32Ux16 x y) // cond: // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32Ux32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32Ux32 x (Const64 [c])) // cond: uint32(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux32 x (MOVDconst [c])) // cond: uint32(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux32 x y) // cond: // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32Ux64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32Ux64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh32Ux64 x (MOVDconst [c])) // cond: uint64(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux64 x (AND y (MOVDconst [31]))) // cond: // result: (SRW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst { break } if v_1_1.AuxInt != 31 { break } v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (AND (MOVDconst [31]) y)) // cond: // result: (SRW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 31 { break } y := v_1.Args[1] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (ANDconst [31] y)) // cond: // result: (SRW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst { break } if v_1.Type != typ.UInt { break } if v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (SUB (MOVDconst [32]) (ANDconst [31] y))) // cond: // result: (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.UInt { break } if v_1_1.AuxInt != 31 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (SUB (MOVDconst [32]) (AND y (MOVDconst [31])))) // cond: // result: (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] y := v_1_1.Args[0] v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64MOVDconst { break } if v_1_1_1.AuxInt != 31 { break } v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (SUB (MOVDconst [32]) (AND (MOVDconst [31]) y))) // cond: // result: (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 31 { break } y := v_1_1.Args[1] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32Ux64 x y) // cond: // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32Ux8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32Ux8 x y) // cond: // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32x16 x y) // cond: // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32x32 x (Const64 [c])) // cond: uint32(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x32 x (MOVDconst [c])) // cond: uint32(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x32 x y) // cond: // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32x64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x64 x (Const64 [c])) // cond: uint64(c) >= 32 // result: (SRAWconst x [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = 63 v.AddArg(x) return true } // match: (Rsh32x64 x (MOVDconst [c])) // cond: uint64(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x64 x (AND y (MOVDconst [31]))) // cond: // result: (SRAW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst { break } if v_1_1.AuxInt != 31 { break } v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32x64 x (AND (MOVDconst [31]) y)) // cond: // result: (SRAW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 31 { break } y := v_1.Args[1] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32x64 x (ANDconst [31] y)) // cond: // result: (SRAW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst { break } if v_1.Type != typ.UInt { break } if v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32x64 x (SUB (MOVDconst [32]) (ANDconst [31] y))) // cond: // result: (SRAW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.UInt { break } if v_1_1.AuxInt != 31 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32x64 x (SUB (MOVDconst [32]) (AND y (MOVDconst [31])))) // cond: // result: (SRAW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] y := v_1_1.Args[0] v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64MOVDconst { break } if v_1_1_1.AuxInt != 31 { break } v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32x64 x (SUB (MOVDconst [32]) (AND (MOVDconst [31]) y))) // cond: // result: (SRAW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 31 { break } y := v_1_1.Args[1] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32x64 x y) // cond: // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh32x8 x y) // cond: // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64Ux16 x y) // cond: // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64Ux32 x (Const64 [c])) // cond: uint32(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux32 x (MOVDconst [c])) // cond: uint32(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux32 x y) // cond: // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64Ux64 x (Const64 [c])) // cond: uint64(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh64Ux64 x (MOVDconst [c])) // cond: uint64(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux64 x (AND y (MOVDconst [63]))) // cond: // result: (SRD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst { break } if v_1_1.AuxInt != 63 { break } v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (AND (MOVDconst [63]) y)) // cond: // result: (SRD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 63 { break } y := v_1.Args[1] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (ANDconst [63] y)) // cond: // result: (SRD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst { break } if v_1.Type != typ.UInt { break } if v_1.AuxInt != 63 { break } y := v_1.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (SUB (MOVDconst [64]) (ANDconst [63] y))) // cond: // result: (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.UInt { break } if v_1_1.AuxInt != 63 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (SUB (MOVDconst [64]) (AND y (MOVDconst [63])))) // cond: // result: (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] y := v_1_1.Args[0] v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64MOVDconst { break } if v_1_1_1.AuxInt != 63 { break } v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (SUB (MOVDconst [64]) (AND (MOVDconst [63]) y))) // cond: // result: (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 63 { break } y := v_1_1.Args[1] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64Ux64 x y) // cond: // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64Ux8 x y) // cond: // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64x16 x y) // cond: // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64x32 x (Const64 [c])) // cond: uint32(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x32 x (MOVDconst [c])) // cond: uint32(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x32 x y) // cond: // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64x64 x (Const64 [c])) // cond: uint64(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x64 x (Const64 [c])) // cond: uint64(c) >= 64 // result: (SRADconst x [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = 63 v.AddArg(x) return true } // match: (Rsh64x64 x (MOVDconst [c])) // cond: uint64(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x64 x (AND y (MOVDconst [63]))) // cond: // result: (SRAD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst { break } if v_1_1.AuxInt != 63 { break } v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64x64 x (AND (MOVDconst [63]) y)) // cond: // result: (SRAD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 63 { break } y := v_1.Args[1] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64x64 x (ANDconst [63] y)) // cond: // result: (SRAD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst { break } if v_1.Type != typ.UInt { break } if v_1.AuxInt != 63 { break } y := v_1.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64x64 x (SUB (MOVDconst [64]) (ANDconst [63] y))) // cond: // result: (SRAD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst { break } if v_1_1.Type != typ.UInt { break } if v_1_1.AuxInt != 63 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64x64 x (SUB (MOVDconst [64]) (AND y (MOVDconst [63])))) // cond: // result: (SRAD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] y := v_1_1.Args[0] v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64MOVDconst { break } if v_1_1_1.AuxInt != 63 { break } v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64x64 x (SUB (MOVDconst [64]) (AND (MOVDconst [63]) y))) // cond: // result: (SRAD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB { break } if v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst { break } if v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND { break } if v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst { break } if v_1_1_0.AuxInt != 63 { break } y := v_1_1.Args[1] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64x64 x y) // cond: // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh64x8 x y) // cond: // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh8Ux16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8Ux16 x y) // cond: // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8Ux32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8Ux32 x (Const64 [c])) // cond: uint32(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux32 x (MOVDconst [c])) // cond: uint32(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux32 x y) // cond: // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8Ux64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8Ux64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh8Ux64 x (MOVDconst [c])) // cond: uint64(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux64 x y) // cond: // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8Ux8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8Ux8 x y) // cond: // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x16_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8x16 x y) // cond: // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x32_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8x32 x (Const64 [c])) // cond: uint32(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x32 x (MOVDconst [c])) // cond: uint32(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x32 x y) // cond: // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x64_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8x64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x64 x (Const64 [c])) // cond: uint64(c) >= 8 // result: (SRAWconst (SignExt8to32 x) [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x64 x (MOVDconst [c])) // cond: uint64(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x64 x y) // cond: // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] y)))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x8_0(v *Value) bool { b := v.Block _ = b typ := &b.Func.Config.Types _ = typ // match: (Rsh8x8 x y) // cond: // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpSignExt16to32_0(v *Value) bool { // match: (SignExt16to32 x) // cond: // result: (MOVHreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt16to64_0(v *Value) bool { // match: (SignExt16to64 x) // cond: // result: (MOVHreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt32to64_0(v *Value) bool { // match: (SignExt32to64 x) // cond: // result: (MOVWreg x) for { x := v.Args[0] v.reset(OpPPC64MOVWreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt8to16_0(v *Value) bool { // match: (SignExt8to16 x) // cond: // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt8to32_0(v *Value) bool { // match: (SignExt8to32 x) // cond: // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt8to64_0(v *Value) bool { // match: (SignExt8to64 x) // cond: // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSlicemask_0(v *Value) bool { b := v.Block _ = b // match: (Slicemask x) // cond: // result: (SRADconst (NEG x) [63]) for { t := v.Type x := v.Args[0] v.reset(OpPPC64SRADconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpPPC64NEG, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpSqrt_0(v *Value) bool { // match: (Sqrt x) // cond: // result: (FSQRT x) for { x := v.Args[0] v.reset(OpPPC64FSQRT) v.AddArg(x) return true } } func rewriteValuePPC64_OpStaticCall_0(v *Value) bool { // match: (StaticCall [argwid] {target} mem) // cond: // result: (CALLstatic [argwid] {target} mem) for { argwid := v.AuxInt target := v.Aux mem := v.Args[0] v.reset(OpPPC64CALLstatic) v.AuxInt = argwid v.Aux = target v.AddArg(mem) return true } } func rewriteValuePPC64_OpStore_0(v *Value) bool { // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) // result: (FMOVDstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpPPC64FMOVDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is32BitFloat(val.Type) // result: (FMOVDstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 8 && is32BitFloat(val.Type)) { break } v.reset(OpPPC64FMOVDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) // result: (FMOVSstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpPPC64FMOVSstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && (is64BitInt(val.Type) || isPtr(val.Type)) // result: (MOVDstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 8 && (is64BitInt(val.Type) || isPtr(val.Type))) { break } v.reset(OpPPC64MOVDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitInt(val.Type) // result: (MOVWstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 4 && is32BitInt(val.Type)) { break } v.reset(OpPPC64MOVWstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 2 // result: (MOVHstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 2) { break } v.reset(OpPPC64MOVHstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 1 // result: (MOVBstore ptr val mem) for { t := v.Aux _ = v.Args[2] ptr := v.Args[0] val := v.Args[1] mem := v.Args[2] if !(t.(*types.Type).Size() == 1) { break } v.reset(OpPPC64MOVBstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpSub16_0(v *Value) bool { // match: (Sub16 x y) // cond: // result: (SUB x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub32_0(v *Value) bool { // match: (Sub32 x y) // cond: // result: (SUB x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub32F_0(v *Value) bool { // match: (Sub32F x y) // cond: // result: (FSUBS x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FSUBS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub64_0(v *Value) bool { // match: (Sub64 x y) // cond: // result: (SUB x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub64F_0(v *Value) bool { // match: (Sub64F x y) // cond: // result: (FSUB x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FSUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub8_0(v *Value) bool { // match: (Sub8 x y) // cond: // result: (SUB x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSubPtr_0(v *Value) bool { // match: (SubPtr x y) // cond: // result: (SUB x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpTrunc_0(v *Value) bool { // match: (Trunc x) // cond: // result: (FTRUNC x) for { x := v.Args[0] v.reset(OpPPC64FTRUNC) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc16to8_0(v *Value) bool { // match: (Trunc16to8 x) // cond: // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc32to16_0(v *Value) bool { // match: (Trunc32to16 x) // cond: // result: (MOVHreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc32to8_0(v *Value) bool { // match: (Trunc32to8 x) // cond: // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc64to16_0(v *Value) bool { // match: (Trunc64to16 x) // cond: // result: (MOVHreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc64to32_0(v *Value) bool { // match: (Trunc64to32 x) // cond: // result: (MOVWreg x) for { x := v.Args[0] v.reset(OpPPC64MOVWreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc64to8_0(v *Value) bool { // match: (Trunc64to8 x) // cond: // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpXor16_0(v *Value) bool { // match: (Xor16 x y) // cond: // result: (XOR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpXor32_0(v *Value) bool { // match: (Xor32 x y) // cond: // result: (XOR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpXor64_0(v *Value) bool { // match: (Xor64 x y) // cond: // result: (XOR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpXor8_0(v *Value) bool { // match: (Xor8 x y) // cond: // result: (XOR x y) for { _ = v.Args[1] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpZero_0(v *Value) bool { b := v.Block _ = b // match: (Zero [0] _ mem) // cond: // result: mem for { if v.AuxInt != 0 { break } _ = v.Args[1] mem := v.Args[1] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Zero [1] destptr mem) // cond: // result: (MOVBstorezero destptr mem) for { if v.AuxInt != 1 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVBstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [2] destptr mem) // cond: // result: (MOVHstorezero destptr mem) for { if v.AuxInt != 2 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVHstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [3] destptr mem) // cond: // result: (MOVBstorezero [2] destptr (MOVHstorezero destptr mem)) for { if v.AuxInt != 3 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVBstorezero) v.AuxInt = 2 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVHstorezero, types.TypeMem) v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [4] destptr mem) // cond: // result: (MOVWstorezero destptr mem) for { if v.AuxInt != 4 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVWstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [5] destptr mem) // cond: // result: (MOVBstorezero [4] destptr (MOVWstorezero destptr mem)) for { if v.AuxInt != 5 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVBstorezero) v.AuxInt = 4 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [6] destptr mem) // cond: // result: (MOVHstorezero [4] destptr (MOVWstorezero destptr mem)) for { if v.AuxInt != 6 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVHstorezero) v.AuxInt = 4 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [7] destptr mem) // cond: // result: (MOVBstorezero [6] destptr (MOVHstorezero [4] destptr (MOVWstorezero destptr mem))) for { if v.AuxInt != 7 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVBstorezero) v.AuxInt = 6 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVHstorezero, types.TypeMem) v0.AuxInt = 4 v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [8] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero destptr mem) for { if v.AuxInt != 8 { break } t := v.Aux _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [8] destptr mem) // cond: // result: (MOVWstorezero [4] destptr (MOVWstorezero [0] destptr mem)) for { if v.AuxInt != 8 { break } _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64MOVWstorezero) v.AuxInt = 4 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpZero_10(v *Value) bool { b := v.Block _ = b // match: (Zero [12] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVWstorezero [8] destptr (MOVDstorezero [0] destptr mem)) for { if v.AuxInt != 12 { break } t := v.Aux _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = 8 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [16] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem)) for { if v.AuxInt != 16 { break } t := v.Aux _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = 8 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [24] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero [16] destptr (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem))) for { if v.AuxInt != 24 { break } t := v.Aux _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = 16 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 8 v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [32] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero [24] destptr (MOVDstorezero [16] destptr (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem)))) for { if v.AuxInt != 32 { break } t := v.Aux _ = v.Args[1] destptr := v.Args[0] mem := v.Args[1] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = 24 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 16 v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v1.AuxInt = 8 v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v2.AuxInt = 0 v2.AddArg(destptr) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [s] ptr mem) // cond: // result: (LoweredZero [s] ptr mem) for { s := v.AuxInt _ = v.Args[1] ptr := v.Args[0] mem := v.Args[1] v.reset(OpPPC64LoweredZero) v.AuxInt = s v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpZeroExt16to32_0(v *Value) bool { // match: (ZeroExt16to32 x) // cond: // result: (MOVHZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt16to64_0(v *Value) bool { // match: (ZeroExt16to64 x) // cond: // result: (MOVHZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt32to64_0(v *Value) bool { // match: (ZeroExt32to64 x) // cond: // result: (MOVWZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVWZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt8to16_0(v *Value) bool { // match: (ZeroExt8to16 x) // cond: // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt8to32_0(v *Value) bool { // match: (ZeroExt8to32 x) // cond: // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt8to64_0(v *Value) bool { // match: (ZeroExt8to64 x) // cond: // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteBlockPPC64(b *Block) bool { config := b.Func.Config _ = config fe := b.Func.fe _ = fe typ := &config.Types _ = typ switch b.Kind { case BlockPPC64EQ: // match: (EQ (CMPconst [0] (ANDconst [c] x)) yes no) // cond: // result: (EQ (ANDCCconst [c] x) yes no) for { v := b.Control if v.Op != OpPPC64CMPconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64ANDconst { break } c := v_0.AuxInt x := v_0.Args[0] b.Kind = BlockPPC64EQ v0 := b.NewValue0(v.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.SetControl(v0) b.Aux = nil return true } // match: (EQ (CMPWconst [0] (ANDconst [c] x)) yes no) // cond: // result: (EQ (ANDCCconst [c] x) yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64ANDconst { break } c := v_0.AuxInt x := v_0.Args[0] b.Kind = BlockPPC64EQ v0 := b.NewValue0(v.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.SetControl(v0) b.Aux = nil return true } // match: (EQ (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (EQ (FlagLT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagLT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (EQ (FlagGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (EQ (InvertFlags cmp) yes no) // cond: // result: (EQ cmp yes no) for { v := b.Control if v.Op != OpPPC64InvertFlags { break } cmp := v.Args[0] b.Kind = BlockPPC64EQ b.SetControl(cmp) b.Aux = nil return true } case BlockPPC64GE: // match: (GE (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (GE (FlagLT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagLT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GE (FlagGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (GE (InvertFlags cmp) yes no) // cond: // result: (LE cmp yes no) for { v := b.Control if v.Op != OpPPC64InvertFlags { break } cmp := v.Args[0] b.Kind = BlockPPC64LE b.SetControl(cmp) b.Aux = nil return true } case BlockPPC64GT: // match: (GT (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GT (FlagLT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagLT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (GT (FlagGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (GT (InvertFlags cmp) yes no) // cond: // result: (LT cmp yes no) for { v := b.Control if v.Op != OpPPC64InvertFlags { break } cmp := v.Args[0] b.Kind = BlockPPC64LT b.SetControl(cmp) b.Aux = nil return true } case BlockIf: // match: (If (Equal cc) yes no) // cond: // result: (EQ cc yes no) for { v := b.Control if v.Op != OpPPC64Equal { break } cc := v.Args[0] b.Kind = BlockPPC64EQ b.SetControl(cc) b.Aux = nil return true } // match: (If (NotEqual cc) yes no) // cond: // result: (NE cc yes no) for { v := b.Control if v.Op != OpPPC64NotEqual { break } cc := v.Args[0] b.Kind = BlockPPC64NE b.SetControl(cc) b.Aux = nil return true } // match: (If (LessThan cc) yes no) // cond: // result: (LT cc yes no) for { v := b.Control if v.Op != OpPPC64LessThan { break } cc := v.Args[0] b.Kind = BlockPPC64LT b.SetControl(cc) b.Aux = nil return true } // match: (If (LessEqual cc) yes no) // cond: // result: (LE cc yes no) for { v := b.Control if v.Op != OpPPC64LessEqual { break } cc := v.Args[0] b.Kind = BlockPPC64LE b.SetControl(cc) b.Aux = nil return true } // match: (If (GreaterThan cc) yes no) // cond: // result: (GT cc yes no) for { v := b.Control if v.Op != OpPPC64GreaterThan { break } cc := v.Args[0] b.Kind = BlockPPC64GT b.SetControl(cc) b.Aux = nil return true } // match: (If (GreaterEqual cc) yes no) // cond: // result: (GE cc yes no) for { v := b.Control if v.Op != OpPPC64GreaterEqual { break } cc := v.Args[0] b.Kind = BlockPPC64GE b.SetControl(cc) b.Aux = nil return true } // match: (If (FLessThan cc) yes no) // cond: // result: (FLT cc yes no) for { v := b.Control if v.Op != OpPPC64FLessThan { break } cc := v.Args[0] b.Kind = BlockPPC64FLT b.SetControl(cc) b.Aux = nil return true } // match: (If (FLessEqual cc) yes no) // cond: // result: (FLE cc yes no) for { v := b.Control if v.Op != OpPPC64FLessEqual { break } cc := v.Args[0] b.Kind = BlockPPC64FLE b.SetControl(cc) b.Aux = nil return true } // match: (If (FGreaterThan cc) yes no) // cond: // result: (FGT cc yes no) for { v := b.Control if v.Op != OpPPC64FGreaterThan { break } cc := v.Args[0] b.Kind = BlockPPC64FGT b.SetControl(cc) b.Aux = nil return true } // match: (If (FGreaterEqual cc) yes no) // cond: // result: (FGE cc yes no) for { v := b.Control if v.Op != OpPPC64FGreaterEqual { break } cc := v.Args[0] b.Kind = BlockPPC64FGE b.SetControl(cc) b.Aux = nil return true } // match: (If cond yes no) // cond: // result: (NE (CMPWconst [0] cond) yes no) for { v := b.Control _ = v cond := b.Control b.Kind = BlockPPC64NE v0 := b.NewValue0(v.Pos, OpPPC64CMPWconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(cond) b.SetControl(v0) b.Aux = nil return true } case BlockPPC64LE: // match: (LE (FlagEQ) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LE (FlagLT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagLT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LE (FlagGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (LE (InvertFlags cmp) yes no) // cond: // result: (GE cmp yes no) for { v := b.Control if v.Op != OpPPC64InvertFlags { break } cmp := v.Args[0] b.Kind = BlockPPC64GE b.SetControl(cmp) b.Aux = nil return true } case BlockPPC64LT: // match: (LT (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (LT (FlagLT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagLT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (LT (FlagGT) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (LT (InvertFlags cmp) yes no) // cond: // result: (GT cmp yes no) for { v := b.Control if v.Op != OpPPC64InvertFlags { break } cmp := v.Args[0] b.Kind = BlockPPC64GT b.SetControl(cmp) b.Aux = nil return true } case BlockPPC64NE: // match: (NE (CMPWconst [0] (Equal cc)) yes no) // cond: // result: (EQ cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64Equal { break } cc := v_0.Args[0] b.Kind = BlockPPC64EQ b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (NotEqual cc)) yes no) // cond: // result: (NE cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64NotEqual { break } cc := v_0.Args[0] b.Kind = BlockPPC64NE b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (LessThan cc)) yes no) // cond: // result: (LT cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64LessThan { break } cc := v_0.Args[0] b.Kind = BlockPPC64LT b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (LessEqual cc)) yes no) // cond: // result: (LE cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64LessEqual { break } cc := v_0.Args[0] b.Kind = BlockPPC64LE b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (GreaterThan cc)) yes no) // cond: // result: (GT cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64GreaterThan { break } cc := v_0.Args[0] b.Kind = BlockPPC64GT b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (GreaterEqual cc)) yes no) // cond: // result: (GE cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64GreaterEqual { break } cc := v_0.Args[0] b.Kind = BlockPPC64GE b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (FLessThan cc)) yes no) // cond: // result: (FLT cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64FLessThan { break } cc := v_0.Args[0] b.Kind = BlockPPC64FLT b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (FLessEqual cc)) yes no) // cond: // result: (FLE cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64FLessEqual { break } cc := v_0.Args[0] b.Kind = BlockPPC64FLE b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (FGreaterThan cc)) yes no) // cond: // result: (FGT cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64FGreaterThan { break } cc := v_0.Args[0] b.Kind = BlockPPC64FGT b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPWconst [0] (FGreaterEqual cc)) yes no) // cond: // result: (FGE cc yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64FGreaterEqual { break } cc := v_0.Args[0] b.Kind = BlockPPC64FGE b.SetControl(cc) b.Aux = nil return true } // match: (NE (CMPconst [0] (ANDconst [c] x)) yes no) // cond: // result: (NE (ANDCCconst [c] x) yes no) for { v := b.Control if v.Op != OpPPC64CMPconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64ANDconst { break } c := v_0.AuxInt x := v_0.Args[0] b.Kind = BlockPPC64NE v0 := b.NewValue0(v.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.SetControl(v0) b.Aux = nil return true } // match: (NE (CMPWconst [0] (ANDconst [c] x)) yes no) // cond: // result: (NE (ANDCCconst [c] x) yes no) for { v := b.Control if v.Op != OpPPC64CMPWconst { break } if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpPPC64ANDconst { break } c := v_0.AuxInt x := v_0.Args[0] b.Kind = BlockPPC64NE v0 := b.NewValue0(v.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.SetControl(v0) b.Aux = nil return true } // match: (NE (FlagEQ) yes no) // cond: // result: (First nil no yes) for { v := b.Control if v.Op != OpPPC64FlagEQ { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil b.swapSuccessors() return true } // match: (NE (FlagLT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagLT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (NE (FlagGT) yes no) // cond: // result: (First nil yes no) for { v := b.Control if v.Op != OpPPC64FlagGT { break } b.Kind = BlockFirst b.SetControl(nil) b.Aux = nil return true } // match: (NE (InvertFlags cmp) yes no) // cond: // result: (NE cmp yes no) for { v := b.Control if v.Op != OpPPC64InvertFlags { break } cmp := v.Args[0] b.Kind = BlockPPC64NE b.SetControl(cmp) b.Aux = nil return true } } return false } -- diff -- @@ -488,7 +488,7 @@ case OpPPC64NotEqual: return rewriteValuePPC64_OpPPC64NotEqual_0(v) case OpPPC64OR: - return rewriteValuePPC64_OpPPC64OR_0(v) || rewriteValuePPC64_OpPPC64OR_10(v) + return rewriteValuePPC64_OpPPC64OR_0(v) || rewriteValuePPC64_OpPPC64OR_10(v) || rewriteValuePPC64_OpPPC64OR_20(v) || rewriteValuePPC64_OpPPC64OR_30(v) || rewriteValuePPC64_OpPPC64OR_40(v) || rewriteValuePPC64_OpPPC64OR_50(v) || rewriteValuePPC64_OpPPC64OR_60(v) || rewriteValuePPC64_OpPPC64OR_70(v) || rewriteValuePPC64_OpPPC64OR_80(v) || rewriteValuePPC64_OpPPC64OR_90(v) || rewriteValuePPC64_OpPPC64OR_100(v) || rewriteValuePPC64_OpPPC64OR_110(v) || rewriteValuePPC64_OpPPC64OR_120(v) || rewriteValuePPC64_OpPPC64OR_130(v) || rewriteValuePPC64_OpPPC64OR_140(v) case OpPPC64ORN: return rewriteValuePPC64_OpPPC64ORN_0(v) case OpPPC64ORconst: @@ -7150,6 +7150,10 @@ return false } func rewriteValuePPC64_OpPPC64MOVBstore_0(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config // match: (MOVBstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} x val mem) @@ -7271,6 +7275,315 @@ v.AddArg(mem) return true } + // match: (MOVBstore [i1] {s} p (SRWconst (MOVHZreg w) [8]) x0:(MOVBstore [i0] {s} p w mem)) + // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0) + // result: (MOVHstore [i0] {s} p w mem) + for { + i1 := v.AuxInt + s := v.Aux + _ = v.Args[2] + p := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpPPC64SRWconst { + break + } + if v_1.AuxInt != 8 { + break + } + v_1_0 := v_1.Args[0] + if v_1_0.Op != OpPPC64MOVHZreg { + break + } + w := v_1_0.Args[0] + x0 := v.Args[2] + if x0.Op != OpPPC64MOVBstore { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[2] + if p != x0.Args[0] { + break + } + if w != x0.Args[1] { + break + } + mem := x0.Args[2] + if !(!config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0)) { + break + } + v.reset(OpPPC64MOVHstore) + v.AuxInt = i0 + v.Aux = s + v.AddArg(p) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstore [i3] {s} p (SRWconst w [24]) x0:(MOVBstore [i2] {s} p (SRWconst w [16]) x1:(MOVBstore [i1] {s} p (SRWconst w [8]) x2:(MOVBstore [i0] {s} p w mem)))) + // cond: !config.BigEndian && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && clobber(x0) && clobber(x1) && clobber(x2) + // result: (MOVWstore [i0] {s} p w mem) + for { + i3 := v.AuxInt + s := v.Aux + _ = v.Args[2] + p := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpPPC64SRWconst { + break + } + if v_1.AuxInt != 24 { + break + } + w := v_1.Args[0] + x0 := v.Args[2] + if x0.Op != OpPPC64MOVBstore { + break + } + i2 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[2] + if p != x0.Args[0] { + break + } + x0_1 := x0.Args[1] + if x0_1.Op != OpPPC64SRWconst { + break + } + if x0_1.AuxInt != 16 { + break + } + if w != x0_1.Args[0] { + break + } + x1 := x0.Args[2] + if x1.Op != OpPPC64MOVBstore { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[2] + if p != x1.Args[0] { + break + } + x1_1 := x1.Args[1] + if x1_1.Op != OpPPC64SRWconst { + break + } + if x1_1.AuxInt != 8 { + break + } + if w != x1_1.Args[0] { + break + } + x2 := x1.Args[2] + if x2.Op != OpPPC64MOVBstore { + break + } + i0 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[2] + if p != x2.Args[0] { + break + } + if w != x2.Args[1] { + break + } + mem := x2.Args[2] + if !(!config.BigEndian && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && clobber(x0) && clobber(x1) && clobber(x2)) { + break + } + v.reset(OpPPC64MOVWstore) + v.AuxInt = i0 + v.Aux = s + v.AddArg(p) + v.AddArg(w) + v.AddArg(mem) + return true + } + // match: (MOVBstore [i7] {s} p (SRDconst w [56]) x0:(MOVBstore [i6] {s} p (SRDconst w [48]) x1:(MOVBstore [i5] {s} p (SRDconst w [40]) x2:(MOVBstore [i4] {s} p (SRDconst w [32]) x3:(MOVBstore [i3] {s} p (SRDconst w [24]) x4:(MOVBstore [i2] {s} p (SRDconst w [16]) x5:(MOVBstore [i1] {s} p (SRDconst w [8]) x6:(MOVBstore [i0] {s} p w mem)))))))) + // cond: !config.BigEndian && i0%4 == 0 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) + // result: (MOVDstore [i0] {s} p w mem) + for { + i7 := v.AuxInt + s := v.Aux + _ = v.Args[2] + p := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpPPC64SRDconst { + break + } + if v_1.AuxInt != 56 { + break + } + w := v_1.Args[0] + x0 := v.Args[2] + if x0.Op != OpPPC64MOVBstore { + break + } + i6 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[2] + if p != x0.Args[0] { + break + } + x0_1 := x0.Args[1] + if x0_1.Op != OpPPC64SRDconst { + break + } + if x0_1.AuxInt != 48 { + break + } + if w != x0_1.Args[0] { + break + } + x1 := x0.Args[2] + if x1.Op != OpPPC64MOVBstore { + break + } + i5 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[2] + if p != x1.Args[0] { + break + } + x1_1 := x1.Args[1] + if x1_1.Op != OpPPC64SRDconst { + break + } + if x1_1.AuxInt != 40 { + break + } + if w != x1_1.Args[0] { + break + } + x2 := x1.Args[2] + if x2.Op != OpPPC64MOVBstore { + break + } + i4 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[2] + if p != x2.Args[0] { + break + } + x2_1 := x2.Args[1] + if x2_1.Op != OpPPC64SRDconst { + break + } + if x2_1.AuxInt != 32 { + break + } + if w != x2_1.Args[0] { + break + } + x3 := x2.Args[2] + if x3.Op != OpPPC64MOVBstore { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[2] + if p != x3.Args[0] { + break + } + x3_1 := x3.Args[1] + if x3_1.Op != OpPPC64SRDconst { + break + } + if x3_1.AuxInt != 24 { + break + } + if w != x3_1.Args[0] { + break + } + x4 := x3.Args[2] + if x4.Op != OpPPC64MOVBstore { + break + } + i2 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[2] + if p != x4.Args[0] { + break + } + x4_1 := x4.Args[1] + if x4_1.Op != OpPPC64SRDconst { + break + } + if x4_1.AuxInt != 16 { + break + } + if w != x4_1.Args[0] { + break + } + x5 := x4.Args[2] + if x5.Op != OpPPC64MOVBstore { + break + } + i1 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[2] + if p != x5.Args[0] { + break + } + x5_1 := x5.Args[1] + if x5_1.Op != OpPPC64SRDconst { + break + } + if x5_1.AuxInt != 8 { + break + } + if w != x5_1.Args[0] { + break + } + x6 := x5.Args[2] + if x6.Op != OpPPC64MOVBstore { + break + } + i0 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[2] + if p != x6.Args[0] { + break + } + if w != x6.Args[1] { + break + } + mem := x6.Args[2] + if !(!config.BigEndian && i0%4 == 0 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { + break + } + v.reset(OpPPC64MOVDstore) + v.AuxInt = i0 + v.Aux = s + v.AddArg(p) + v.AddArg(w) + v.AddArg(mem) + return true + } return false } func rewriteValuePPC64_OpPPC64MOVBstorezero_0(v *Value) bool { @@ -9050,6 +9363,10 @@ return false } func rewriteValuePPC64_OpPPC64OR_10(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config // match: (OR x (MOVDconst [c])) // cond: isU32Bit(c) // result: (ORconst [c] x) @@ -9086,6 +9403,29957 @@ v.reset(OpPPC64ORconst) v.AuxInt = c v.AddArg(x) + return true + } + // match: (OR x0:(MOVBZload [i0] {s} p mem) o1:(SLWconst x1:(MOVBZload [i1] {s} p mem) [8])) + // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) + // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + x0 := v.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + s := x0.Aux + _ = x0.Args[1] + p := x0.Args[0] + mem := x0.Args[1] + o1 := v.Args[1] + if o1.Op != OpPPC64SLWconst { + break + } + if o1.AuxInt != 8 { + break + } + x1 := o1.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + if !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { + break + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o1:(SLWconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) + // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) + // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o1 := v.Args[0] + if o1.Op != OpPPC64SLWconst { + break + } + if o1.AuxInt != 8 { + break + } + x1 := o1.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + s := x1.Aux + _ = x1.Args[1] + p := x1.Args[0] + mem := x1.Args[1] + x0 := v.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + if !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { + break + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem))) + // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) + // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s1 := v.Args[0] + if s1.Op != OpPPC64SLWconst { + break + } + if s1.AuxInt != 24 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i3 := x2.AuxInt + s := x2.Aux + _ = x2.Args[1] + p := x2.Args[0] + mem := x2.Args[1] + o0 := v.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLWconst { + break + } + if s0.AuxInt != 16 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i2 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVHZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + if !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + break + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]))) + // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) + // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s1 := v.Args[0] + if s1.Op != OpPPC64SLWconst { + break + } + if s1.AuxInt != 24 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i3 := x2.AuxInt + s := x2.Aux + _ = x2.Args[1] + p := x2.Args[0] + mem := x2.Args[1] + o0 := v.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVHZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLWconst { + break + } + if s0.AuxInt != 16 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i2 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + if !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + break + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem)) s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24])) + // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) + // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o0 := v.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLWconst { + break + } + if s0.AuxInt != 16 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i2 := x1.AuxInt + s := x1.Aux + _ = x1.Args[1] + p := x1.Args[0] + mem := x1.Args[1] + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVHZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := v.Args[1] + if s1.Op != OpPPC64SLWconst { + break + } + if s1.AuxInt != 24 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i3 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + if !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + break + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16])) s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24])) + // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) + // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o0 := v.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVHZload { + break + } + i0 := x0.AuxInt + s := x0.Aux + _ = x0.Args[1] + p := x0.Args[0] + mem := x0.Args[1] + s0 := o0.Args[1] + if s0.Op != OpPPC64SLWconst { + break + } + if s0.AuxInt != 16 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i2 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := v.Args[1] + if s1.Op != OpPPC64SLWconst { + break + } + if s1.AuxInt != 24 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i3 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + if !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + break + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuePPC64_OpPPC64OR_20(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuePPC64_OpPPC64OR_30(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuePPC64_OpPPC64OR_40(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuePPC64_OpPPC64OR_50(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuePPC64_OpPPC64OR_60(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuePPC64_OpPPC64OR_70(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuePPC64_OpPPC64OR_80(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + s6 := v.Args[0] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + s := x7.Aux + _ = x7.Args[1] + p := x7.Args[0] + mem := x7.Args[1] + o5 := v.Args[1] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuePPC64_OpPPC64OR_90(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuePPC64_OpPPC64OR_100(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuePPC64_OpPPC64OR_110(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + s5 := o5.Args[0] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + s := x6.Aux + _ = x6.Args[1] + p := x6.Args[0] + mem := x6.Args[1] + o4 := o5.Args[1] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuePPC64_OpPPC64OR_120(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + s4 := o4.Args[0] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + s := x5.Aux + _ = x5.Args[1] + p := x5.Args[0] + mem := x5.Args[1] + o3 := o4.Args[1] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuePPC64_OpPPC64OR_130(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config + // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + s := x4.Aux + _ = x4.Args[1] + p := x4.Args[0] + mem := x4.Args[1] + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + s := x4.Aux + _ = x4.Args[1] + p := x4.Args[0] + mem := x4.Args[1] + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + s := x4.Aux + _ = x4.Args[1] + p := x4.Args[0] + mem := x4.Args[1] + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + s := x4.Aux + _ = x4.Args[1] + p := x4.Args[0] + mem := x4.Args[1] + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + s := x4.Aux + _ = x4.Args[1] + p := x4.Args[0] + mem := x4.Args[1] + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + s := x4.Aux + _ = x4.Args[1] + p := x4.Args[0] + mem := x4.Args[1] + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + s := x4.Aux + _ = x4.Args[1] + p := x4.Args[0] + mem := x4.Args[1] + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]))) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + s3 := o3.Args[0] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + s := x4.Aux + _ = x4.Args[1] + p := x4.Args[0] + mem := x4.Args[1] + o2 := o3.Args[1] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + s := x3.Aux + _ = x3.Args[1] + p := x3.Args[0] + mem := x3.Args[1] + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + s := x3.Aux + _ = x3.Args[1] + p := x3.Args[0] + mem := x3.Args[1] + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + return false +} +func rewriteValuePPC64_OpPPC64OR_140(v *Value) bool { + b := v.Block + _ = b + config := b.Func.Config + _ = config + // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + s := x3.Aux + _ = x3.Args[1] + p := x3.Args[0] + mem := x3.Args[1] + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24]) o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]))) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + s2 := o2.Args[0] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + s := x3.Aux + _ = x3.Args[1] + p := x3.Args[0] + mem := x3.Args[1] + o1 := o2.Args[1] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + s := x2.Aux + _ = x2.Args[1] + p := x2.Args[0] + mem := x2.Args[1] + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16]) o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]))) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + s1 := o1.Args[0] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + s := x2.Aux + _ = x2.Args[1] + p := x2.Args[0] + mem := x2.Args[1] + o0 := o1.Args[1] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + s0 := o0.Args[0] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + s := x1.Aux + _ = x1.Args[1] + p := x1.Args[0] + mem := x1.Args[1] + x0 := o0.Args[1] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + if x0.Aux != s { + break + } + _ = x0.Args[1] + if p != x0.Args[0] { + break + } + if mem != x0.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + // match: (OR o5:(OR o4:(OR o3:(OR o2:(OR o1:(OR o0:(OR x0:(MOVBZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) s1:(SLDconst x2:(MOVBZload [i2] {s} p mem) [16])) s2:(SLDconst x3:(MOVBZload [i3] {s} p mem) [24])) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) + // cond: !config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5) + // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) + for { + t := v.Type + _ = v.Args[1] + o5 := v.Args[0] + if o5.Op != OpPPC64OR { + break + } + if o5.Type != t { + break + } + _ = o5.Args[1] + o4 := o5.Args[0] + if o4.Op != OpPPC64OR { + break + } + if o4.Type != t { + break + } + _ = o4.Args[1] + o3 := o4.Args[0] + if o3.Op != OpPPC64OR { + break + } + if o3.Type != t { + break + } + _ = o3.Args[1] + o2 := o3.Args[0] + if o2.Op != OpPPC64OR { + break + } + if o2.Type != t { + break + } + _ = o2.Args[1] + o1 := o2.Args[0] + if o1.Op != OpPPC64OR { + break + } + if o1.Type != t { + break + } + _ = o1.Args[1] + o0 := o1.Args[0] + if o0.Op != OpPPC64OR { + break + } + if o0.Type != t { + break + } + _ = o0.Args[1] + x0 := o0.Args[0] + if x0.Op != OpPPC64MOVBZload { + break + } + i0 := x0.AuxInt + s := x0.Aux + _ = x0.Args[1] + p := x0.Args[0] + mem := x0.Args[1] + s0 := o0.Args[1] + if s0.Op != OpPPC64SLDconst { + break + } + if s0.AuxInt != 8 { + break + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + break + } + i1 := x1.AuxInt + if x1.Aux != s { + break + } + _ = x1.Args[1] + if p != x1.Args[0] { + break + } + if mem != x1.Args[1] { + break + } + s1 := o1.Args[1] + if s1.Op != OpPPC64SLDconst { + break + } + if s1.AuxInt != 16 { + break + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + break + } + i2 := x2.AuxInt + if x2.Aux != s { + break + } + _ = x2.Args[1] + if p != x2.Args[0] { + break + } + if mem != x2.Args[1] { + break + } + s2 := o2.Args[1] + if s2.Op != OpPPC64SLDconst { + break + } + if s2.AuxInt != 24 { + break + } + x3 := s2.Args[0] + if x3.Op != OpPPC64MOVBZload { + break + } + i3 := x3.AuxInt + if x3.Aux != s { + break + } + _ = x3.Args[1] + if p != x3.Args[0] { + break + } + if mem != x3.Args[1] { + break + } + s3 := o3.Args[1] + if s3.Op != OpPPC64SLDconst { + break + } + if s3.AuxInt != 32 { + break + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + break + } + i4 := x4.AuxInt + if x4.Aux != s { + break + } + _ = x4.Args[1] + if p != x4.Args[0] { + break + } + if mem != x4.Args[1] { + break + } + s4 := o4.Args[1] + if s4.Op != OpPPC64SLDconst { + break + } + if s4.AuxInt != 40 { + break + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + break + } + i5 := x5.AuxInt + if x5.Aux != s { + break + } + _ = x5.Args[1] + if p != x5.Args[0] { + break + } + if mem != x5.Args[1] { + break + } + s5 := o5.Args[1] + if s5.Op != OpPPC64SLDconst { + break + } + if s5.AuxInt != 48 { + break + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + break + } + i6 := x6.AuxInt + if x6.Aux != s { + break + } + _ = x6.Args[1] + if p != x6.Args[0] { + break + } + if mem != x6.Args[1] { + break + } + s6 := v.Args[1] + if s6.Op != OpPPC64SLDconst { + break + } + if s6.AuxInt != 56 { + break + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + break + } + i7 := x7.AuxInt + if x7.Aux != s { + break + } + _ = x7.Args[1] + if p != x7.Args[0] { + break + } + if mem != x7.Args[1] { + break + } + if !(!config.BigEndian && i0%4 == 0 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(o3) && clobber(o4) && clobber(o5)) { + break + } + b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) + v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) return true } return false go_bd6d78ef37b5a607abfb530f3e353cfa653492f1_src_cmd_compile_internal_ssa_rewriteAMD64.go.test000066400000000000000000165475131516001707200360120ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit bd6d78ef37b5a607abfb530f3e353cfa653492f1 file testdata/go_bd6d78ef37b5a607abfb530f3e353cfa653492f1_src_cmd_compile_internal_ssa_rewriteAMD64.go.test -- x -- // Code generated from gen/AMD64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/compile/internal/types" func rewriteValueAMD64(v *Value) bool { switch v.Op { case OpAMD64ADCQ: return rewriteValueAMD64_OpAMD64ADCQ_0(v) case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst_0(v) case OpAMD64ADDL: return rewriteValueAMD64_OpAMD64ADDL_0(v) || rewriteValueAMD64_OpAMD64ADDL_10(v) || rewriteValueAMD64_OpAMD64ADDL_20(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst_0(v) || rewriteValueAMD64_OpAMD64ADDLconst_10(v) case OpAMD64ADDLconstmodify: return rewriteValueAMD64_OpAMD64ADDLconstmodify_0(v) case OpAMD64ADDLload: return rewriteValueAMD64_OpAMD64ADDLload_0(v) case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify_0(v) case OpAMD64ADDQ: return rewriteValueAMD64_OpAMD64ADDQ_0(v) || rewriteValueAMD64_OpAMD64ADDQ_10(v) || rewriteValueAMD64_OpAMD64ADDQ_20(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry_0(v) case OpAMD64ADDQconst: return rewriteValueAMD64_OpAMD64ADDQconst_0(v) || rewriteValueAMD64_OpAMD64ADDQconst_10(v) case OpAMD64ADDQconstmodify: return rewriteValueAMD64_OpAMD64ADDQconstmodify_0(v) case OpAMD64ADDQload: return rewriteValueAMD64_OpAMD64ADDQload_0(v) case OpAMD64ADDQmodify: return rewriteValueAMD64_OpAMD64ADDQmodify_0(v) case OpAMD64ADDSD: return rewriteValueAMD64_OpAMD64ADDSD_0(v) case OpAMD64ADDSDload: return rewriteValueAMD64_OpAMD64ADDSDload_0(v) case OpAMD64ADDSS: return rewriteValueAMD64_OpAMD64ADDSS_0(v) case OpAMD64ADDSSload: return rewriteValueAMD64_OpAMD64ADDSSload_0(v) case OpAMD64ANDL: return rewriteValueAMD64_OpAMD64ANDL_0(v) case OpAMD64ANDLconst: return rewriteValueAMD64_OpAMD64ANDLconst_0(v) case OpAMD64ANDLconstmodify: return rewriteValueAMD64_OpAMD64ANDLconstmodify_0(v) case OpAMD64ANDLload: return rewriteValueAMD64_OpAMD64ANDLload_0(v) case OpAMD64ANDLmodify: return rewriteValueAMD64_OpAMD64ANDLmodify_0(v) case OpAMD64ANDQ: return rewriteValueAMD64_OpAMD64ANDQ_0(v) case OpAMD64ANDQconst: return rewriteValueAMD64_OpAMD64ANDQconst_0(v) case OpAMD64ANDQconstmodify: return rewriteValueAMD64_OpAMD64ANDQconstmodify_0(v) case OpAMD64ANDQload: return rewriteValueAMD64_OpAMD64ANDQload_0(v) case OpAMD64ANDQmodify: return rewriteValueAMD64_OpAMD64ANDQmodify_0(v) case OpAMD64BSFQ: return rewriteValueAMD64_OpAMD64BSFQ_0(v) case OpAMD64BTCLconst: return rewriteValueAMD64_OpAMD64BTCLconst_0(v) case OpAMD64BTCLconstmodify: return rewriteValueAMD64_OpAMD64BTCLconstmodify_0(v) case OpAMD64BTCLmodify: return rewriteValueAMD64_OpAMD64BTCLmodify_0(v) case OpAMD64BTCQconst: return rewriteValueAMD64_OpAMD64BTCQconst_0(v) case OpAMD64BTCQconstmodify: return rewriteValueAMD64_OpAMD64BTCQconstmodify_0(v) case OpAMD64BTCQmodify: return rewriteValueAMD64_OpAMD64BTCQmodify_0(v) case OpAMD64BTLconst: return rewriteValueAMD64_OpAMD64BTLconst_0(v) case OpAMD64BTQconst: return rewriteValueAMD64_OpAMD64BTQconst_0(v) case OpAMD64BTRLconst: return rewriteValueAMD64_OpAMD64BTRLconst_0(v) case OpAMD64BTRLconstmodify: return rewriteValueAMD64_OpAMD64BTRLconstmodify_0(v) case OpAMD64BTRLmodify: return rewriteValueAMD64_OpAMD64BTRLmodify_0(v) case OpAMD64BTRQconst: return rewriteValueAMD64_OpAMD64BTRQconst_0(v) case OpAMD64BTRQconstmodify: return rewriteValueAMD64_OpAMD64BTRQconstmodify_0(v) case OpAMD64BTRQmodify: return rewriteValueAMD64_OpAMD64BTRQmodify_0(v) case OpAMD64BTSLconst: return rewriteValueAMD64_OpAMD64BTSLconst_0(v) case OpAMD64BTSLconstmodify: return rewriteValueAMD64_OpAMD64BTSLconstmodify_0(v) case OpAMD64BTSLmodify: return rewriteValueAMD64_OpAMD64BTSLmodify_0(v) case OpAMD64BTSQconst: return rewriteValueAMD64_OpAMD64BTSQconst_0(v) case OpAMD64BTSQconstmodify: return rewriteValueAMD64_OpAMD64BTSQconstmodify_0(v) case OpAMD64BTSQmodify: return rewriteValueAMD64_OpAMD64BTSQmodify_0(v) case OpAMD64CMOVLCC: return rewriteValueAMD64_OpAMD64CMOVLCC_0(v) case OpAMD64CMOVLCS: return rewriteValueAMD64_OpAMD64CMOVLCS_0(v) case OpAMD64CMOVLEQ: return rewriteValueAMD64_OpAMD64CMOVLEQ_0(v) case OpAMD64CMOVLGE: return rewriteValueAMD64_OpAMD64CMOVLGE_0(v) case OpAMD64CMOVLGT: return rewriteValueAMD64_OpAMD64CMOVLGT_0(v) case OpAMD64CMOVLHI: return rewriteValueAMD64_OpAMD64CMOVLHI_0(v) case OpAMD64CMOVLLE: return rewriteValueAMD64_OpAMD64CMOVLLE_0(v) case OpAMD64CMOVLLS: return rewriteValueAMD64_OpAMD64CMOVLLS_0(v) case OpAMD64CMOVLLT: return rewriteValueAMD64_OpAMD64CMOVLLT_0(v) case OpAMD64CMOVLNE: return rewriteValueAMD64_OpAMD64CMOVLNE_0(v) case OpAMD64CMOVQCC: return rewriteValueAMD64_OpAMD64CMOVQCC_0(v) case OpAMD64CMOVQCS: return rewriteValueAMD64_OpAMD64CMOVQCS_0(v) case OpAMD64CMOVQEQ: return rewriteValueAMD64_OpAMD64CMOVQEQ_0(v) case OpAMD64CMOVQGE: return rewriteValueAMD64_OpAMD64CMOVQGE_0(v) case OpAMD64CMOVQGT: return rewriteValueAMD64_OpAMD64CMOVQGT_0(v) case OpAMD64CMOVQHI: return rewriteValueAMD64_OpAMD64CMOVQHI_0(v) case OpAMD64CMOVQLE: return rewriteValueAMD64_OpAMD64CMOVQLE_0(v) case OpAMD64CMOVQLS: return rewriteValueAMD64_OpAMD64CMOVQLS_0(v) case OpAMD64CMOVQLT: return rewriteValueAMD64_OpAMD64CMOVQLT_0(v) case OpAMD64CMOVQNE: return rewriteValueAMD64_OpAMD64CMOVQNE_0(v) case OpAMD64CMOVWCC: return rewriteValueAMD64_OpAMD64CMOVWCC_0(v) case OpAMD64CMOVWCS: return rewriteValueAMD64_OpAMD64CMOVWCS_0(v) case OpAMD64CMOVWEQ: return rewriteValueAMD64_OpAMD64CMOVWEQ_0(v) case OpAMD64CMOVWGE: return rewriteValueAMD64_OpAMD64CMOVWGE_0(v) case OpAMD64CMOVWGT: return rewriteValueAMD64_OpAMD64CMOVWGT_0(v) case OpAMD64CMOVWHI: return rewriteValueAMD64_OpAMD64CMOVWHI_0(v) case OpAMD64CMOVWLE: return rewriteValueAMD64_OpAMD64CMOVWLE_0(v) case OpAMD64CMOVWLS: return rewriteValueAMD64_OpAMD64CMOVWLS_0(v) case OpAMD64CMOVWLT: return rewriteValueAMD64_OpAMD64CMOVWLT_0(v) case OpAMD64CMOVWNE: return rewriteValueAMD64_OpAMD64CMOVWNE_0(v) case OpAMD64CMPB: return rewriteValueAMD64_OpAMD64CMPB_0(v) case OpAMD64CMPBconst: return rewriteValueAMD64_OpAMD64CMPBconst_0(v) case OpAMD64CMPBconstload: return rewriteValueAMD64_OpAMD64CMPBconstload_0(v) case OpAMD64CMPBload: return rewriteValueAMD64_OpAMD64CMPBload_0(v) case OpAMD64CMPL: return rewriteValueAMD64_OpAMD64CMPL_0(v) case OpAMD64CMPLconst: return rewriteValueAMD64_OpAMD64CMPLconst_0(v) || rewriteValueAMD64_OpAMD64CMPLconst_10(v) case OpAMD64CMPLconstload: return rewriteValueAMD64_OpAMD64CMPLconstload_0(v) case OpAMD64CMPLload: return rewriteValueAMD64_OpAMD64CMPLload_0(v) case OpAMD64CMPQ: return rewriteValueAMD64_OpAMD64CMPQ_0(v) case OpAMD64CMPQconst: return rewriteValueAMD64_OpAMD64CMPQconst_0(v) || rewriteValueAMD64_OpAMD64CMPQconst_10(v) case OpAMD64CMPQconstload: return rewriteValueAMD64_OpAMD64CMPQconstload_0(v) case OpAMD64CMPQload: return rewriteValueAMD64_OpAMD64CMPQload_0(v) case OpAMD64CMPW: return rewriteValueAMD64_OpAMD64CMPW_0(v) case OpAMD64CMPWconst: return rewriteValueAMD64_OpAMD64CMPWconst_0(v) case OpAMD64CMPWconstload: return rewriteValueAMD64_OpAMD64CMPWconstload_0(v) case OpAMD64CMPWload: return rewriteValueAMD64_OpAMD64CMPWload_0(v) case OpAMD64CMPXCHGLlock: return rewriteValueAMD64_OpAMD64CMPXCHGLlock_0(v) case OpAMD64CMPXCHGQlock: return rewriteValueAMD64_OpAMD64CMPXCHGQlock_0(v) case OpAMD64DIVSD: return rewriteValueAMD64_OpAMD64DIVSD_0(v) case OpAMD64DIVSDload: return rewriteValueAMD64_OpAMD64DIVSDload_0(v) case OpAMD64DIVSS: return rewriteValueAMD64_OpAMD64DIVSS_0(v) case OpAMD64DIVSSload: return rewriteValueAMD64_OpAMD64DIVSSload_0(v) case OpAMD64HMULL: return rewriteValueAMD64_OpAMD64HMULL_0(v) case OpAMD64HMULLU: return rewriteValueAMD64_OpAMD64HMULLU_0(v) case OpAMD64HMULQ: return rewriteValueAMD64_OpAMD64HMULQ_0(v) case OpAMD64HMULQU: return rewriteValueAMD64_OpAMD64HMULQU_0(v) case OpAMD64LEAL: return rewriteValueAMD64_OpAMD64LEAL_0(v) case OpAMD64LEAL1: return rewriteValueAMD64_OpAMD64LEAL1_0(v) case OpAMD64LEAL2: return rewriteValueAMD64_OpAMD64LEAL2_0(v) case OpAMD64LEAL4: return rewriteValueAMD64_OpAMD64LEAL4_0(v) case OpAMD64LEAL8: return rewriteValueAMD64_OpAMD64LEAL8_0(v) case OpAMD64LEAQ: return rewriteValueAMD64_OpAMD64LEAQ_0(v) case OpAMD64LEAQ1: return rewriteValueAMD64_OpAMD64LEAQ1_0(v) case OpAMD64LEAQ2: return rewriteValueAMD64_OpAMD64LEAQ2_0(v) case OpAMD64LEAQ4: return rewriteValueAMD64_OpAMD64LEAQ4_0(v) case OpAMD64LEAQ8: return rewriteValueAMD64_OpAMD64LEAQ8_0(v) case OpAMD64MOVBQSX: return rewriteValueAMD64_OpAMD64MOVBQSX_0(v) case OpAMD64MOVBQSXload: return rewriteValueAMD64_OpAMD64MOVBQSXload_0(v) case OpAMD64MOVBQZX: return rewriteValueAMD64_OpAMD64MOVBQZX_0(v) case OpAMD64MOVBatomicload: return rewriteValueAMD64_OpAMD64MOVBatomicload_0(v) case OpAMD64MOVBload: return rewriteValueAMD64_OpAMD64MOVBload_0(v) case OpAMD64MOVBloadidx1: return rewriteValueAMD64_OpAMD64MOVBloadidx1_0(v) case OpAMD64MOVBstore: return rewriteValueAMD64_OpAMD64MOVBstore_0(v) || rewriteValueAMD64_OpAMD64MOVBstore_10(v) || rewriteValueAMD64_OpAMD64MOVBstore_20(v) || rewriteValueAMD64_OpAMD64MOVBstore_30(v) case OpAMD64MOVBstoreconst: return rewriteValueAMD64_OpAMD64MOVBstoreconst_0(v) case OpAMD64MOVBstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVBstoreconstidx1_0(v) case OpAMD64MOVBstoreidx1: return rewriteValueAMD64_OpAMD64MOVBstoreidx1_0(v) || rewriteValueAMD64_OpAMD64MOVBstoreidx1_10(v) case OpAMD64MOVLQSX: return rewriteValueAMD64_OpAMD64MOVLQSX_0(v) case OpAMD64MOVLQSXload: return rewriteValueAMD64_OpAMD64MOVLQSXload_0(v) case OpAMD64MOVLQZX: return rewriteValueAMD64_OpAMD64MOVLQZX_0(v) case OpAMD64MOVLatomicload: return rewriteValueAMD64_OpAMD64MOVLatomicload_0(v) case OpAMD64MOVLf2i: return rewriteValueAMD64_OpAMD64MOVLf2i_0(v) case OpAMD64MOVLi2f: return rewriteValueAMD64_OpAMD64MOVLi2f_0(v) case OpAMD64MOVLload: return rewriteValueAMD64_OpAMD64MOVLload_0(v) || rewriteValueAMD64_OpAMD64MOVLload_10(v) case OpAMD64MOVLloadidx1: return rewriteValueAMD64_OpAMD64MOVLloadidx1_0(v) case OpAMD64MOVLloadidx4: return rewriteValueAMD64_OpAMD64MOVLloadidx4_0(v) case OpAMD64MOVLloadidx8: return rewriteValueAMD64_OpAMD64MOVLloadidx8_0(v) case OpAMD64MOVLstore: return rewriteValueAMD64_OpAMD64MOVLstore_0(v) || rewriteValueAMD64_OpAMD64MOVLstore_10(v) || rewriteValueAMD64_OpAMD64MOVLstore_20(v) || rewriteValueAMD64_OpAMD64MOVLstore_30(v) case OpAMD64MOVLstoreconst: return rewriteValueAMD64_OpAMD64MOVLstoreconst_0(v) case OpAMD64MOVLstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVLstoreconstidx1_0(v) case OpAMD64MOVLstoreconstidx4: return rewriteValueAMD64_OpAMD64MOVLstoreconstidx4_0(v) case OpAMD64MOVLstoreidx1: return rewriteValueAMD64_OpAMD64MOVLstoreidx1_0(v) case OpAMD64MOVLstoreidx4: return rewriteValueAMD64_OpAMD64MOVLstoreidx4_0(v) case OpAMD64MOVLstoreidx8: return rewriteValueAMD64_OpAMD64MOVLstoreidx8_0(v) case OpAMD64MOVOload: return rewriteValueAMD64_OpAMD64MOVOload_0(v) case OpAMD64MOVOstore: return rewriteValueAMD64_OpAMD64MOVOstore_0(v) case OpAMD64MOVQatomicload: return rewriteValueAMD64_OpAMD64MOVQatomicload_0(v) case OpAMD64MOVQf2i: return rewriteValueAMD64_OpAMD64MOVQf2i_0(v) case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f_0(v) case OpAMD64MOVQload: return rewriteValueAMD64_OpAMD64MOVQload_0(v) || rewriteValueAMD64_OpAMD64MOVQload_10(v) case OpAMD64MOVQloadidx1: return rewriteValueAMD64_OpAMD64MOVQloadidx1_0(v) case OpAMD64MOVQloadidx8: return rewriteValueAMD64_OpAMD64MOVQloadidx8_0(v) case OpAMD64MOVQstore: return rewriteValueAMD64_OpAMD64MOVQstore_0(v) || rewriteValueAMD64_OpAMD64MOVQstore_10(v) || rewriteValueAMD64_OpAMD64MOVQstore_20(v) || rewriteValueAMD64_OpAMD64MOVQstore_30(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst_0(v) case OpAMD64MOVQstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVQstoreconstidx1_0(v) case OpAMD64MOVQstoreconstidx8: return rewriteValueAMD64_OpAMD64MOVQstoreconstidx8_0(v) case OpAMD64MOVQstoreidx1: return rewriteValueAMD64_OpAMD64MOVQstoreidx1_0(v) case OpAMD64MOVQstoreidx8: return rewriteValueAMD64_OpAMD64MOVQstoreidx8_0(v) case OpAMD64MOVSDload: return rewriteValueAMD64_OpAMD64MOVSDload_0(v) case OpAMD64MOVSDloadidx1: return rewriteValueAMD64_OpAMD64MOVSDloadidx1_0(v) case OpAMD64MOVSDloadidx8: return rewriteValueAMD64_OpAMD64MOVSDloadidx8_0(v) case OpAMD64MOVSDstore: return rewriteValueAMD64_OpAMD64MOVSDstore_0(v) case OpAMD64MOVSDstoreidx1: return rewriteValueAMD64_OpAMD64MOVSDstoreidx1_0(v) case OpAMD64MOVSDstoreidx8: return rewriteValueAMD64_OpAMD64MOVSDstoreidx8_0(v) case OpAMD64MOVSSload: return rewriteValueAMD64_OpAMD64MOVSSload_0(v) case OpAMD64MOVSSloadidx1: return rewriteValueAMD64_OpAMD64MOVSSloadidx1_0(v) case OpAMD64MOVSSloadidx4: return rewriteValueAMD64_OpAMD64MOVSSloadidx4_0(v) case OpAMD64MOVSSstore: return rewriteValueAMD64_OpAMD64MOVSSstore_0(v) case OpAMD64MOVSSstoreidx1: return rewriteValueAMD64_OpAMD64MOVSSstoreidx1_0(v) case OpAMD64MOVSSstoreidx4: return rewriteValueAMD64_OpAMD64MOVSSstoreidx4_0(v) case OpAMD64MOVWQSX: return rewriteValueAMD64_OpAMD64MOVWQSX_0(v) case OpAMD64MOVWQSXload: return rewriteValueAMD64_OpAMD64MOVWQSXload_0(v) case OpAMD64MOVWQZX: return rewriteValueAMD64_OpAMD64MOVWQZX_0(v) case OpAMD64MOVWload: return rewriteValueAMD64_OpAMD64MOVWload_0(v) case OpAMD64MOVWloadidx1: return rewriteValueAMD64_OpAMD64MOVWloadidx1_0(v) case OpAMD64MOVWloadidx2: return rewriteValueAMD64_OpAMD64MOVWloadidx2_0(v) case OpAMD64MOVWstore: return rewriteValueAMD64_OpAMD64MOVWstore_0(v) || rewriteValueAMD64_OpAMD64MOVWstore_10(v) case OpAMD64MOVWstoreconst: return rewriteValueAMD64_OpAMD64MOVWstoreconst_0(v) case OpAMD64MOVWstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVWstoreconstidx1_0(v) case OpAMD64MOVWstoreconstidx2: return rewriteValueAMD64_OpAMD64MOVWstoreconstidx2_0(v) case OpAMD64MOVWstoreidx1: return rewriteValueAMD64_OpAMD64MOVWstoreidx1_0(v) case OpAMD64MOVWstoreidx2: return rewriteValueAMD64_OpAMD64MOVWstoreidx2_0(v) case OpAMD64MULL: return rewriteValueAMD64_OpAMD64MULL_0(v) case OpAMD64MULLconst: return rewriteValueAMD64_OpAMD64MULLconst_0(v) || rewriteValueAMD64_OpAMD64MULLconst_10(v) || rewriteValueAMD64_OpAMD64MULLconst_20(v) || rewriteValueAMD64_OpAMD64MULLconst_30(v) case OpAMD64MULQ: return rewriteValueAMD64_OpAMD64MULQ_0(v) case OpAMD64MULQconst: return rewriteValueAMD64_OpAMD64MULQconst_0(v) || rewriteValueAMD64_OpAMD64MULQconst_10(v) || rewriteValueAMD64_OpAMD64MULQconst_20(v) || rewriteValueAMD64_OpAMD64MULQconst_30(v) case OpAMD64MULSD: return rewriteValueAMD64_OpAMD64MULSD_0(v) case OpAMD64MULSDload: return rewriteValueAMD64_OpAMD64MULSDload_0(v) case OpAMD64MULSS: return rewriteValueAMD64_OpAMD64MULSS_0(v) case OpAMD64MULSSload: return rewriteValueAMD64_OpAMD64MULSSload_0(v) case OpAMD64NEGL: return rewriteValueAMD64_OpAMD64NEGL_0(v) case OpAMD64NEGQ: return rewriteValueAMD64_OpAMD64NEGQ_0(v) case OpAMD64NOTL: return rewriteValueAMD64_OpAMD64NOTL_0(v) case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ_0(v) case OpAMD64ORL: return rewriteValueAMD64_OpAMD64ORL_0(v) || rewriteValueAMD64_OpAMD64ORL_10(v) || rewriteValueAMD64_OpAMD64ORL_20(v) || rewriteValueAMD64_OpAMD64ORL_30(v) || rewriteValueAMD64_OpAMD64ORL_40(v) || rewriteValueAMD64_OpAMD64ORL_50(v) || rewriteValueAMD64_OpAMD64ORL_60(v) || rewriteValueAMD64_OpAMD64ORL_70(v) || rewriteValueAMD64_OpAMD64ORL_80(v) || rewriteValueAMD64_OpAMD64ORL_90(v) || rewriteValueAMD64_OpAMD64ORL_100(v) || rewriteValueAMD64_OpAMD64ORL_110(v) || rewriteValueAMD64_OpAMD64ORL_120(v) || rewriteValueAMD64_OpAMD64ORL_130(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst_0(v) case OpAMD64ORLconstmodify: return rewriteValueAMD64_OpAMD64ORLconstmodify_0(v) case OpAMD64ORLload: return rewriteValueAMD64_OpAMD64ORLload_0(v) case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify_0(v) case OpAMD64ORQ: return rewriteValueAMD64_OpAMD64ORQ_0(v) || rewriteValueAMD64_OpAMD64ORQ_10(v) || rewriteValueAMD64_OpAMD64ORQ_20(v) || rewriteValueAMD64_OpAMD64ORQ_30(v) || rewriteValueAMD64_OpAMD64ORQ_40(v) || rewriteValueAMD64_OpAMD64ORQ_50(v) || rewriteValueAMD64_OpAMD64ORQ_60(v) || rewriteValueAMD64_OpAMD64ORQ_70(v) || rewriteValueAMD64_OpAMD64ORQ_80(v) || rewriteValueAMD64_OpAMD64ORQ_90(v) || rewriteValueAMD64_OpAMD64ORQ_100(v) || rewriteValueAMD64_OpAMD64ORQ_110(v) || rewriteValueAMD64_OpAMD64ORQ_120(v) || rewriteValueAMD64_OpAMD64ORQ_130(v) || rewriteValueAMD64_OpAMD64ORQ_140(v) || rewriteValueAMD64_OpAMD64ORQ_150(v) || rewriteValueAMD64_OpAMD64ORQ_160(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst_0(v) case OpAMD64ORQconstmodify: return rewriteValueAMD64_OpAMD64ORQconstmodify_0(v) case OpAMD64ORQload: return rewriteValueAMD64_OpAMD64ORQload_0(v) case OpAMD64ORQmodify: return rewriteValueAMD64_OpAMD64ORQmodify_0(v) case OpAMD64ROLB: return rewriteValueAMD64_OpAMD64ROLB_0(v) case OpAMD64ROLBconst: return rewriteValueAMD64_OpAMD64ROLBconst_0(v) case OpAMD64ROLL: return rewriteValueAMD64_OpAMD64ROLL_0(v) case OpAMD64ROLLconst: return rewriteValueAMD64_OpAMD64ROLLconst_0(v) case OpAMD64ROLQ: return rewriteValueAMD64_OpAMD64ROLQ_0(v) case OpAMD64ROLQconst: return rewriteValueAMD64_OpAMD64ROLQconst_0(v) case OpAMD64ROLW: return rewriteValueAMD64_OpAMD64ROLW_0(v) case OpAMD64ROLWconst: return rewriteValueAMD64_OpAMD64ROLWconst_0(v) case OpAMD64RORB: return rewriteValueAMD64_OpAMD64RORB_0(v) case OpAMD64RORL: return rewriteValueAMD64_OpAMD64RORL_0(v) case OpAMD64RORQ: return rewriteValueAMD64_OpAMD64RORQ_0(v) case OpAMD64RORW: return rewriteValueAMD64_OpAMD64RORW_0(v) case OpAMD64SARB: return rewriteValueAMD64_OpAMD64SARB_0(v) case OpAMD64SARBconst: return rewriteValueAMD64_OpAMD64SARBconst_0(v) case OpAMD64SARL: return rewriteValueAMD64_OpAMD64SARL_0(v) case OpAMD64SARLconst: return rewriteValueAMD64_OpAMD64SARLconst_0(v) case OpAMD64SARQ: return rewriteValueAMD64_OpAMD64SARQ_0(v) case OpAMD64SARQconst: return rewriteValueAMD64_OpAMD64SARQconst_0(v) case OpAMD64SARW: return rewriteValueAMD64_OpAMD64SARW_0(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst_0(v) case OpAMD64SBBLcarrymask: return rewriteValueAMD64_OpAMD64SBBLcarrymask_0(v) case OpAMD64SBBQ: return rewriteValueAMD64_OpAMD64SBBQ_0(v) case OpAMD64SBBQcarrymask: return rewriteValueAMD64_OpAMD64SBBQcarrymask_0(v) case OpAMD64SBBQconst: return rewriteValueAMD64_OpAMD64SBBQconst_0(v) case OpAMD64SETA: return rewriteValueAMD64_OpAMD64SETA_0(v) case OpAMD64SETAE: return rewriteValueAMD64_OpAMD64SETAE_0(v) case OpAMD64SETAEstore: return rewriteValueAMD64_OpAMD64SETAEstore_0(v) case OpAMD64SETAstore: return rewriteValueAMD64_OpAMD64SETAstore_0(v) case OpAMD64SETB: return rewriteValueAMD64_OpAMD64SETB_0(v) case OpAMD64SETBE: return rewriteValueAMD64_OpAMD64SETBE_0(v) case OpAMD64SETBEstore: return rewriteValueAMD64_OpAMD64SETBEstore_0(v) case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore_0(v) case OpAMD64SETEQ: return rewriteValueAMD64_OpAMD64SETEQ_0(v) || rewriteValueAMD64_OpAMD64SETEQ_10(v) || rewriteValueAMD64_OpAMD64SETEQ_20(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore_0(v) || rewriteValueAMD64_OpAMD64SETEQstore_10(v) || rewriteValueAMD64_OpAMD64SETEQstore_20(v) case OpAMD64SETG: return rewriteValueAMD64_OpAMD64SETG_0(v) case OpAMD64SETGE: return rewriteValueAMD64_OpAMD64SETGE_0(v) case OpAMD64SETGEstore: return rewriteValueAMD64_OpAMD64SETGEstore_0(v) case OpAMD64SETGstore: return rewriteValueAMD64_OpAMD64SETGstore_0(v) case OpAMD64SETL: return rewriteValueAMD64_OpAMD64SETL_0(v) case OpAMD64SETLE: return rewriteValueAMD64_OpAMD64SETLE_0(v) case OpAMD64SETLEstore: return rewriteValueAMD64_OpAMD64SETLEstore_0(v) case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore_0(v) case OpAMD64SETNE: return rewriteValueAMD64_OpAMD64SETNE_0(v) || rewriteValueAMD64_OpAMD64SETNE_10(v) || rewriteValueAMD64_OpAMD64SETNE_20(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore_0(v) || rewriteValueAMD64_OpAMD64SETNEstore_10(v) || rewriteValueAMD64_OpAMD64SETNEstore_20(v) case OpAMD64SHLL: return rewriteValueAMD64_OpAMD64SHLL_0(v) case OpAMD64SHLLconst: return rewriteValueAMD64_OpAMD64SHLLconst_0(v) case OpAMD64SHLQ: return rewriteValueAMD64_OpAMD64SHLQ_0(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst_0(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB_0(v) case OpAMD64SHRBconst: return rewriteValueAMD64_OpAMD64SHRBconst_0(v) case OpAMD64SHRL: return rewriteValueAMD64_OpAMD64SHRL_0(v) case OpAMD64SHRLconst: return rewriteValueAMD64_OpAMD64SHRLconst_0(v) case OpAMD64SHRQ: return rewriteValueAMD64_OpAMD64SHRQ_0(v) case OpAMD64SHRQconst: return rewriteValueAMD64_OpAMD64SHRQconst_0(v) case OpAMD64SHRW: return rewriteValueAMD64_OpAMD64SHRW_0(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst_0(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL_0(v) case OpAMD64SUBLconst: return rewriteValueAMD64_OpAMD64SUBLconst_0(v) case OpAMD64SUBLload: return rewriteValueAMD64_OpAMD64SUBLload_0(v) case OpAMD64SUBLmodify: return rewriteValueAMD64_OpAMD64SUBLmodify_0(v) case OpAMD64SUBQ: return rewriteValueAMD64_OpAMD64SUBQ_0(v) case OpAMD64SUBQborrow: return rewriteValueAMD64_OpAMD64SUBQborrow_0(v) case OpAMD64SUBQconst: return rewriteValueAMD64_OpAMD64SUBQconst_0(v) case OpAMD64SUBQload: return rewriteValueAMD64_OpAMD64SUBQload_0(v) case OpAMD64SUBQmodify: return rewriteValueAMD64_OpAMD64SUBQmodify_0(v) case OpAMD64SUBSD: return rewriteValueAMD64_OpAMD64SUBSD_0(v) case OpAMD64SUBSDload: return rewriteValueAMD64_OpAMD64SUBSDload_0(v) case OpAMD64SUBSS: return rewriteValueAMD64_OpAMD64SUBSS_0(v) case OpAMD64SUBSSload: return rewriteValueAMD64_OpAMD64SUBSSload_0(v) case OpAMD64TESTB: return rewriteValueAMD64_OpAMD64TESTB_0(v) case OpAMD64TESTBconst: return rewriteValueAMD64_OpAMD64TESTBconst_0(v) case OpAMD64TESTL: return rewriteValueAMD64_OpAMD64TESTL_0(v) case OpAMD64TESTLconst: return rewriteValueAMD64_OpAMD64TESTLconst_0(v) case OpAMD64TESTQ: return rewriteValueAMD64_OpAMD64TESTQ_0(v) case OpAMD64TESTQconst: return rewriteValueAMD64_OpAMD64TESTQconst_0(v) case OpAMD64TESTW: return rewriteValueAMD64_OpAMD64TESTW_0(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst_0(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock_0(v) case OpAMD64XADDQlock: return rewriteValueAMD64_OpAMD64XADDQlock_0(v) case OpAMD64XCHGL: return rewriteValueAMD64_OpAMD64XCHGL_0(v) case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ_0(v) case OpAMD64XORL: return rewriteValueAMD64_OpAMD64XORL_0(v) || rewriteValueAMD64_OpAMD64XORL_10(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst_0(v) || rewriteValueAMD64_OpAMD64XORLconst_10(v) case OpAMD64XORLconstmodify: return rewriteValueAMD64_OpAMD64XORLconstmodify_0(v) case OpAMD64XORLload: return rewriteValueAMD64_OpAMD64XORLload_0(v) case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify_0(v) case OpAMD64XORQ: return rewriteValueAMD64_OpAMD64XORQ_0(v) || rewriteValueAMD64_OpAMD64XORQ_10(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst_0(v) case OpAMD64XORQconstmodify: return rewriteValueAMD64_OpAMD64XORQconstmodify_0(v) case OpAMD64XORQload: return rewriteValueAMD64_OpAMD64XORQload_0(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify_0(v) case OpAdd16: return rewriteValueAMD64_OpAdd16_0(v) case OpAdd32: return rewriteValueAMD64_OpAdd32_0(v) case OpAdd32F: return rewriteValueAMD64_OpAdd32F_0(v) case OpAdd64: return rewriteValueAMD64_OpAdd64_0(v) case OpAdd64F: return rewriteValueAMD64_OpAdd64F_0(v) case OpAdd8: return rewriteValueAMD64_OpAdd8_0(v) case OpAddPtr: return rewriteValueAMD64_OpAddPtr_0(v) case OpAddr: return rewriteValueAMD64_OpAddr_0(v) case OpAnd16: return rewriteValueAMD64_OpAnd16_0(v) case OpAnd32: return rewriteValueAMD64_OpAnd32_0(v) case OpAnd64: return rewriteValueAMD64_OpAnd64_0(v) case OpAnd8: return rewriteValueAMD64_OpAnd8_0(v) case OpAndB: return rewriteValueAMD64_OpAndB_0(v) case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32_0(v) case OpAtomicAdd64: return rewriteValueAMD64_OpAtomicAdd64_0(v) case OpAtomicAnd8: return rewriteValueAMD64_OpAtomicAnd8_0(v) case OpAtomicCompareAndSwap32: return rewriteValueAMD64_OpAtomicCompareAndSwap32_0(v) case OpAtomicCompareAndSwap64: return rewriteValueAMD64_OpAtomicCompareAndSwap64_0(v) case OpAtomicExchange32: return rewriteValueAMD64_OpAtomicExchange32_0(v) case OpAtomicExchange64: return rewriteValueAMD64_OpAtomicExchange64_0(v) case OpAtomicLoad32: return rewriteValueAMD64_OpAtomicLoad32_0(v) case OpAtomicLoad64: return rewriteValueAMD64_OpAtomicLoad64_0(v) case OpAtomicLoad8: return rewriteValueAMD64_OpAtomicLoad8_0(v) case OpAtomicLoadPtr: return rewriteValueAMD64_OpAtomicLoadPtr_0(v) case OpAtomicOr8: return rewriteValueAMD64_OpAtomicOr8_0(v) case OpAtomicStore32: return rewriteValueAMD64_OpAtomicStore32_0(v) case OpAtomicStore64: return rewriteValueAMD64_OpAtomicStore64_0(v) case OpAtomicStore8: return rewriteValueAMD64_OpAtomicStore8_0(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB_0(v) case OpAvg64u: return rewriteValueAMD64_OpAvg64u_0(v) case OpBitLen16: return rewriteValueAMD64_OpBitLen16_0(v) case OpBitLen32: return rewriteValueAMD64_OpBitLen32_0(v) case OpBitLen64: return rewriteValueAMD64_OpBitLen64_0(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8_0(v) case OpBswap32: return rewriteValueAMD64_OpBswap32_0(v) case OpBswap64: return rewriteValueAMD64_OpBswap64_0(v) case OpCeil: return rewriteValueAMD64_OpCeil_0(v) case OpClosureCall: return rewriteValueAMD64_OpClosureCall_0(v) case OpCom16: return rewriteValueAMD64_OpCom16_0(v) case OpCom32: return rewriteValueAMD64_OpCom32_0(v) case OpCom64: return rewriteValueAMD64_OpCom64_0(v) case OpCom8: return rewriteValueAMD64_OpCom8_0(v) case OpCondSelect: return rewriteValueAMD64_OpCondSelect_0(v) || rewriteValueAMD64_OpCondSelect_10(v) || rewriteValueAMD64_OpCondSelect_20(v) || rewriteValueAMD64_OpCondSelect_30(v) || rewriteValueAMD64_OpCondSelect_40(v) case OpConst16: return rewriteValueAMD64_OpConst16_0(v) case OpConst32: return rewriteValueAMD64_OpConst32_0(v) case OpConst32F: return rewriteValueAMD64_OpConst32F_0(v) case OpConst64: return rewriteValueAMD64_OpConst64_0(v) case OpConst64F: return rewriteValueAMD64_OpConst64F_0(v) case OpConst8: return rewriteValueAMD64_OpConst8_0(v) case OpConstBool: return rewriteValueAMD64_OpConstBool_0(v) case OpConstNil: return rewriteValueAMD64_OpConstNil_0(v) case OpCtz16: return rewriteValueAMD64_OpCtz16_0(v) case OpCtz16NonZero: return rewriteValueAMD64_OpCtz16NonZero_0(v) case OpCtz32: return rewriteValueAMD64_OpCtz32_0(v) case OpCtz32NonZero: return rewriteValueAMD64_OpCtz32NonZero_0(v) case OpCtz64: return rewriteValueAMD64_OpCtz64_0(v) case OpCtz64NonZero: return rewriteValueAMD64_OpCtz64NonZero_0(v) case OpCtz8: return rewriteValueAMD64_OpCtz8_0(v) case OpCtz8NonZero: return rewriteValueAMD64_OpCtz8NonZero_0(v) case OpCvt32Fto32: return rewriteValueAMD64_OpCvt32Fto32_0(v) case OpCvt32Fto64: return rewriteValueAMD64_OpCvt32Fto64_0(v) case OpCvt32Fto64F: return rewriteValueAMD64_OpCvt32Fto64F_0(v) case OpCvt32to32F: return rewriteValueAMD64_OpCvt32to32F_0(v) case OpCvt32to64F: return rewriteValueAMD64_OpCvt32to64F_0(v) case OpCvt64Fto32: return rewriteValueAMD64_OpCvt64Fto32_0(v) case OpCvt64Fto32F: return rewriteValueAMD64_OpCvt64Fto32F_0(v) case OpCvt64Fto64: return rewriteValueAMD64_OpCvt64Fto64_0(v) case OpCvt64to32F: return rewriteValueAMD64_OpCvt64to32F_0(v) case OpCvt64to64F: return rewriteValueAMD64_OpCvt64to64F_0(v) case OpDiv128u: return rewriteValueAMD64_OpDiv128u_0(v) case OpDiv16: return rewriteValueAMD64_OpDiv16_0(v) case OpDiv16u: return rewriteValueAMD64_OpDiv16u_0(v) case OpDiv32: return rewriteValueAMD64_OpDiv32_0(v) case OpDiv32F: return rewriteValueAMD64_OpDiv32F_0(v) case OpDiv32u: return rewriteValueAMD64_OpDiv32u_0(v) case OpDiv64: return rewriteValueAMD64_OpDiv64_0(v) case OpDiv64F: return rewriteValueAMD64_OpDiv64F_0(v) case OpDiv64u: return rewriteValueAMD64_OpDiv64u_0(v) case OpDiv8: return rewriteValueAMD64_OpDiv8_0(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u_0(v) case OpEq16: return rewriteValueAMD64_OpEq16_0(v) case OpEq32: return rewriteValueAMD64_OpEq32_0(v) case OpEq32F: return rewriteValueAMD64_OpEq32F_0(v) case OpEq64: return rewriteValueAMD64_OpEq64_0(v) case OpEq64F: return rewriteValueAMD64_OpEq64F_0(v) case OpEq8: return rewriteValueAMD64_OpEq8_0(v) case OpEqB: return rewriteValueAMD64_OpEqB_0(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr_0(v) case OpFMA: return rewriteValueAMD64_OpFMA_0(v) case OpFloor: return rewriteValueAMD64_OpFloor_0(v) case OpGeq16: return rewriteValueAMD64_OpGeq16_0(v) case OpGeq16U: return rewriteValueAMD64_OpGeq16U_0(v) case OpGeq32: return rewriteValueAMD64_OpGeq32_0(v) case OpGeq32F: return rewriteValueAMD64_OpGeq32F_0(v) case OpGeq32U: return rewriteValueAMD64_OpGeq32U_0(v) case OpGeq64: return rewriteValueAMD64_OpGeq64_0(v) case OpGeq64F: return rewriteValueAMD64_OpGeq64F_0(v) case OpGeq64U: return rewriteValueAMD64_OpGeq64U_0(v) case OpGeq8: return rewriteValueAMD64_OpGeq8_0(v) case OpGeq8U: return rewriteValueAMD64_OpGeq8U_0(v) case OpGetCallerPC: return rewriteValueAMD64_OpGetCallerPC_0(v) case OpGetCallerSP: return rewriteValueAMD64_OpGetCallerSP_0(v) case OpGetClosurePtr: return rewriteValueAMD64_OpGetClosurePtr_0(v) case OpGetG: return rewriteValueAMD64_OpGetG_0(v) case OpGreater16: return rewriteValueAMD64_OpGreater16_0(v) case OpGreater16U: return rewriteValueAMD64_OpGreater16U_0(v) case OpGreater32: return rewriteValueAMD64_OpGreater32_0(v) case OpGreater32F: return rewriteValueAMD64_OpGreater32F_0(v) case OpGreater32U: return rewriteValueAMD64_OpGreater32U_0(v) case OpGreater64: return rewriteValueAMD64_OpGreater64_0(v) case OpGreater64F: return rewriteValueAMD64_OpGreater64F_0(v) case OpGreater64U: return rewriteValueAMD64_OpGreater64U_0(v) case OpGreater8: return rewriteValueAMD64_OpGreater8_0(v) case OpGreater8U: return rewriteValueAMD64_OpGreater8U_0(v) case OpHmul32: return rewriteValueAMD64_OpHmul32_0(v) case OpHmul32u: return rewriteValueAMD64_OpHmul32u_0(v) case OpHmul64: return rewriteValueAMD64_OpHmul64_0(v) case OpHmul64u: return rewriteValueAMD64_OpHmul64u_0(v) case OpInterCall: return rewriteValueAMD64_OpInterCall_0(v) case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds_0(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil_0(v) case OpIsSliceInBounds: return rewriteValueAMD64_OpIsSliceInBounds_0(v) case OpLeq16: return rewriteValueAMD64_OpLeq16_0(v) case OpLeq16U: return rewriteValueAMD64_OpLeq16U_0(v) case OpLeq32: return rewriteValueAMD64_OpLeq32_0(v) case OpLeq32F: return rewriteValueAMD64_OpLeq32F_0(v) case OpLeq32U: return rewriteValueAMD64_OpLeq32U_0(v) case OpLeq64: return rewriteValueAMD64_OpLeq64_0(v) case OpLeq64F: return rewriteValueAMD64_OpLeq64F_0(v) case OpLeq64U: return rewriteValueAMD64_OpLeq64U_0(v) case OpLeq8: return rewriteValueAMD64_OpLeq8_0(v) case OpLeq8U: return rewriteValueAMD64_OpLeq8U_0(v) case OpLess16: return rewriteValueAMD64_OpLess16_0(v) case OpLess16U: return rewriteValueAMD64_OpLess16U_0(v) case OpLess32: return rewriteValueAMD64_OpLess32_0(v) case OpLess32F: return rewriteValueAMD64_OpLess32F_0(v) case OpLess32U: return rewriteValueAMD64_OpLess32U_0(v) case OpLess64: return rewriteValueAMD64_OpLess64_0(v) case OpLess64F: return rewriteValueAMD64_OpLess64F_0(v) case OpLess64U: return rewriteValueAMD64_OpLess64U_0(v) case OpLess8: return rewriteValueAMD64_OpLess8_0(v) case OpLess8U: return rewriteValueAMD64_OpLess8U_0(v) case OpLoad: return rewriteValueAMD64_OpLoad_0(v) case OpLocalAddr: return rewriteValueAMD64_OpLocalAddr_0(v) case OpLsh16x16: return rewriteValueAMD64_OpLsh16x16_0(v) case OpLsh16x32: return rewriteValueAMD64_OpLsh16x32_0(v) case OpLsh16x64: return rewriteValueAMD64_OpLsh16x64_0(v) case OpLsh16x8: return rewriteValueAMD64_OpLsh16x8_0(v) case OpLsh32x16: return rewriteValueAMD64_OpLsh32x16_0(v) case OpLsh32x32: return rewriteValueAMD64_OpLsh32x32_0(v) case OpLsh32x64: return rewriteValueAMD64_OpLsh32x64_0(v) case OpLsh32x8: return rewriteValueAMD64_OpLsh32x8_0(v) case OpLsh64x16: return rewriteValueAMD64_OpLsh64x16_0(v) case OpLsh64x32: return rewriteValueAMD64_OpLsh64x32_0(v) case OpLsh64x64: return rewriteValueAMD64_OpLsh64x64_0(v) case OpLsh64x8: return rewriteValueAMD64_OpLsh64x8_0(v) case OpLsh8x16: return rewriteValueAMD64_OpLsh8x16_0(v) case OpLsh8x32: return rewriteValueAMD64_OpLsh8x32_0(v) case OpLsh8x64: return rewriteValueAMD64_OpLsh8x64_0(v) case OpLsh8x8: return rewriteValueAMD64_OpLsh8x8_0(v) case OpMod16: return rewriteValueAMD64_OpMod16_0(v) case OpMod16u: return rewriteValueAMD64_OpMod16u_0(v) case OpMod32: return rewriteValueAMD64_OpMod32_0(v) case OpMod32u: return rewriteValueAMD64_OpMod32u_0(v) case OpMod64: return rewriteValueAMD64_OpMod64_0(v) case OpMod64u: return rewriteValueAMD64_OpMod64u_0(v) case OpMod8: return rewriteValueAMD64_OpMod8_0(v) case OpMod8u: return rewriteValueAMD64_OpMod8u_0(v) case OpMove: return rewriteValueAMD64_OpMove_0(v) || rewriteValueAMD64_OpMove_10(v) || rewriteValueAMD64_OpMove_20(v) case OpMul16: return rewriteValueAMD64_OpMul16_0(v) case OpMul32: return rewriteValueAMD64_OpMul32_0(v) case OpMul32F: return rewriteValueAMD64_OpMul32F_0(v) case OpMul64: return rewriteValueAMD64_OpMul64_0(v) case OpMul64F: return rewriteValueAMD64_OpMul64F_0(v) case OpMul64uhilo: return rewriteValueAMD64_OpMul64uhilo_0(v) case OpMul8: return rewriteValueAMD64_OpMul8_0(v) case OpNeg16: return rewriteValueAMD64_OpNeg16_0(v) case OpNeg32: return rewriteValueAMD64_OpNeg32_0(v) case OpNeg32F: return rewriteValueAMD64_OpNeg32F_0(v) case OpNeg64: return rewriteValueAMD64_OpNeg64_0(v) case OpNeg64F: return rewriteValueAMD64_OpNeg64F_0(v) case OpNeg8: return rewriteValueAMD64_OpNeg8_0(v) case OpNeq16: return rewriteValueAMD64_OpNeq16_0(v) case OpNeq32: return rewriteValueAMD64_OpNeq32_0(v) case OpNeq32F: return rewriteValueAMD64_OpNeq32F_0(v) case OpNeq64: return rewriteValueAMD64_OpNeq64_0(v) case OpNeq64F: return rewriteValueAMD64_OpNeq64F_0(v) case OpNeq8: return rewriteValueAMD64_OpNeq8_0(v) case OpNeqB: return rewriteValueAMD64_OpNeqB_0(v) case OpNeqPtr: return rewriteValueAMD64_OpNeqPtr_0(v) case OpNilCheck: return rewriteValueAMD64_OpNilCheck_0(v) case OpNot: return rewriteValueAMD64_OpNot_0(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr_0(v) case OpOr16: return rewriteValueAMD64_OpOr16_0(v) case OpOr32: return rewriteValueAMD64_OpOr32_0(v) case OpOr64: return rewriteValueAMD64_OpOr64_0(v) case OpOr8: return rewriteValueAMD64_OpOr8_0(v) case OpOrB: return rewriteValueAMD64_OpOrB_0(v) case OpPanicBounds: return rewriteValueAMD64_OpPanicBounds_0(v) case OpPopCount16: return rewriteValueAMD64_OpPopCount16_0(v) case OpPopCount32: return rewriteValueAMD64_OpPopCount32_0(v) case OpPopCount64: return rewriteValueAMD64_OpPopCount64_0(v) case OpPopCount8: return rewriteValueAMD64_OpPopCount8_0(v) case OpRotateLeft16: return rewriteValueAMD64_OpRotateLeft16_0(v) case OpRotateLeft32: return rewriteValueAMD64_OpRotateLeft32_0(v) case OpRotateLeft64: return rewriteValueAMD64_OpRotateLeft64_0(v) case OpRotateLeft8: return rewriteValueAMD64_OpRotateLeft8_0(v) case OpRound32F: return rewriteValueAMD64_OpRound32F_0(v) case OpRound64F: return rewriteValueAMD64_OpRound64F_0(v) case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven_0(v) case OpRsh16Ux16: return rewriteValueAMD64_OpRsh16Ux16_0(v) case OpRsh16Ux32: return rewriteValueAMD64_OpRsh16Ux32_0(v) case OpRsh16Ux64: return rewriteValueAMD64_OpRsh16Ux64_0(v) case OpRsh16Ux8: return rewriteValueAMD64_OpRsh16Ux8_0(v) case OpRsh16x16: return rewriteValueAMD64_OpRsh16x16_0(v) case OpRsh16x32: return rewriteValueAMD64_OpRsh16x32_0(v) case OpRsh16x64: return rewriteValueAMD64_OpRsh16x64_0(v) case OpRsh16x8: return rewriteValueAMD64_OpRsh16x8_0(v) case OpRsh32Ux16: return rewriteValueAMD64_OpRsh32Ux16_0(v) case OpRsh32Ux32: return rewriteValueAMD64_OpRsh32Ux32_0(v) case OpRsh32Ux64: return rewriteValueAMD64_OpRsh32Ux64_0(v) case OpRsh32Ux8: return rewriteValueAMD64_OpRsh32Ux8_0(v) case OpRsh32x16: return rewriteValueAMD64_OpRsh32x16_0(v) case OpRsh32x32: return rewriteValueAMD64_OpRsh32x32_0(v) case OpRsh32x64: return rewriteValueAMD64_OpRsh32x64_0(v) case OpRsh32x8: return rewriteValueAMD64_OpRsh32x8_0(v) case OpRsh64Ux16: return rewriteValueAMD64_OpRsh64Ux16_0(v) case OpRsh64Ux32: return rewriteValueAMD64_OpRsh64Ux32_0(v) case OpRsh64Ux64: return rewriteValueAMD64_OpRsh64Ux64_0(v) case OpRsh64Ux8: return rewriteValueAMD64_OpRsh64Ux8_0(v) case OpRsh64x16: return rewriteValueAMD64_OpRsh64x16_0(v) case OpRsh64x32: return rewriteValueAMD64_OpRsh64x32_0(v) case OpRsh64x64: return rewriteValueAMD64_OpRsh64x64_0(v) case OpRsh64x8: return rewriteValueAMD64_OpRsh64x8_0(v) case OpRsh8Ux16: return rewriteValueAMD64_OpRsh8Ux16_0(v) case OpRsh8Ux32: return rewriteValueAMD64_OpRsh8Ux32_0(v) case OpRsh8Ux64: return rewriteValueAMD64_OpRsh8Ux64_0(v) case OpRsh8Ux8: return rewriteValueAMD64_OpRsh8Ux8_0(v) case OpRsh8x16: return rewriteValueAMD64_OpRsh8x16_0(v) case OpRsh8x32: return rewriteValueAMD64_OpRsh8x32_0(v) case OpRsh8x64: return rewriteValueAMD64_OpRsh8x64_0(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8_0(v) case OpSelect0: return rewriteValueAMD64_OpSelect0_0(v) case OpSelect1: return rewriteValueAMD64_OpSelect1_0(v) case OpSignExt16to32: return rewriteValueAMD64_OpSignExt16to32_0(v) case OpSignExt16to64: return rewriteValueAMD64_OpSignExt16to64_0(v) case OpSignExt32to64: return rewriteValueAMD64_OpSignExt32to64_0(v) case OpSignExt8to16: return rewriteValueAMD64_OpSignExt8to16_0(v) case OpSignExt8to32: return rewriteValueAMD64_OpSignExt8to32_0(v) case OpSignExt8to64: return rewriteValueAMD64_OpSignExt8to64_0(v) case OpSlicemask: return rewriteValueAMD64_OpSlicemask_0(v) case OpSqrt: return rewriteValueAMD64_OpSqrt_0(v) case OpStaticCall: return rewriteValueAMD64_OpStaticCall_0(v) case OpStore: return rewriteValueAMD64_OpStore_0(v) case OpSub16: return rewriteValueAMD64_OpSub16_0(v) case OpSub32: return rewriteValueAMD64_OpSub32_0(v) case OpSub32F: return rewriteValueAMD64_OpSub32F_0(v) case OpSub64: return rewriteValueAMD64_OpSub64_0(v) case OpSub64F: return rewriteValueAMD64_OpSub64F_0(v) case OpSub8: return rewriteValueAMD64_OpSub8_0(v) case OpSubPtr: return rewriteValueAMD64_OpSubPtr_0(v) case OpTrunc: return rewriteValueAMD64_OpTrunc_0(v) case OpTrunc16to8: return rewriteValueAMD64_OpTrunc16to8_0(v) case OpTrunc32to16: return rewriteValueAMD64_OpTrunc32to16_0(v) case OpTrunc32to8: return rewriteValueAMD64_OpTrunc32to8_0(v) case OpTrunc64to16: return rewriteValueAMD64_OpTrunc64to16_0(v) case OpTrunc64to32: return rewriteValueAMD64_OpTrunc64to32_0(v) case OpTrunc64to8: return rewriteValueAMD64_OpTrunc64to8_0(v) case OpWB: return rewriteValueAMD64_OpWB_0(v) case OpXor16: return rewriteValueAMD64_OpXor16_0(v) case OpXor32: return rewriteValueAMD64_OpXor32_0(v) case OpXor64: return rewriteValueAMD64_OpXor64_0(v) case OpXor8: return rewriteValueAMD64_OpXor8_0(v) case OpZero: return rewriteValueAMD64_OpZero_0(v) || rewriteValueAMD64_OpZero_10(v) || rewriteValueAMD64_OpZero_20(v) case OpZeroExt16to32: return rewriteValueAMD64_OpZeroExt16to32_0(v) case OpZeroExt16to64: return rewriteValueAMD64_OpZeroExt16to64_0(v) case OpZeroExt32to64: return rewriteValueAMD64_OpZeroExt32to64_0(v) case OpZeroExt8to16: return rewriteValueAMD64_OpZeroExt8to16_0(v) case OpZeroExt8to32: return rewriteValueAMD64_OpZeroExt8to32_0(v) case OpZeroExt8to64: return rewriteValueAMD64_OpZeroExt8to64_0(v) } return false } func rewriteValueAMD64_OpAMD64ADCQ_0(v *Value) bool { // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) // result: (ADCQconst x [c] carry) for { carry := v.Args[2] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ADCQconst) v.AuxInt = c v.AddArg(x) v.AddArg(carry) return true } // match: (ADCQ (MOVQconst [c]) x carry) // cond: is32Bit(c) // result: (ADCQconst x [c] carry) for { carry := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt x := v.Args[1] if !(is32Bit(c)) { break } v.reset(OpAMD64ADCQconst) v.AuxInt = c v.AddArg(x) v.AddArg(carry) return true } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) for { _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQcarry) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ADCQconst_0(v *Value) bool { // match: (ADCQconst x [c] (FlagEQ)) // result: (ADDQconstcarry x [c]) for { c := v.AuxInt _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL_0(v *Value) bool { // match: (ADDL x (MOVLconst [c])) // result: (ADDLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64ADDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (MOVLconst [c]) x) // result: (ADDLconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64ADDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHRLconst x [d]) (SHLLconst x [c])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { break } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHRWconst x [d]) (SHLLconst x [c])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { break } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRBconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { break } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL (SHRBconst x [d]) (SHLLconst x [c])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRBconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { break } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (SHLLconst [3] y) x) // result: (LEAL8 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 3 { break } y := v_0.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ADDL_10(v *Value) bool { // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (SHLLconst [2] y) x) // result: (LEAL4 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 2 { break } y := v_0.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (SHLLconst [1] y) x) // result: (LEAL2 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { break } y := v_0.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDL { break } y := v_1.Args[1] if y != v_1.Args[0] { break } v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (ADDL y y) x) // result: (LEAL2 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] if y != v_0.Args[0] { break } v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDL { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpAMD64LEAL2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDL x (ADDL y x)) // result: (LEAL2 y x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDL { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpAMD64LEAL2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDL (ADDL x y) x) // result: (LEAL2 y x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpAMD64LEAL2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDL (ADDL y x) x) // result: (LEAL2 y x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpAMD64LEAL2) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL_20(v *Value) bool { // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDL y (ADDLconst [c] x)) // result: (LEAL1 [c] x y) for { _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt x := v_1.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAL { break } c := v_1.AuxInt s := v_1.Aux y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (LEAL [c] {s} y) x) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } c := v_0.AuxInt s := v_0.Aux y := v_0.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } y := v_1.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL (NEGL y) x) // result: (SUBL x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64NEGL { break } y := v_0.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconst_0(v *Value) bool { // match: (ADDLconst [c] (ADDL x y)) // result: (LEAL1 [c] x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (SHLLconst [1] x)) // result: (LEAL1 [c] x x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(c+d) // result: (LEAL [c+d] {s} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } d := v_0.AuxInt s := v_0.Aux x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL1 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL2 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL2 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL4 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL4 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL8 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL8 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] x) // cond: int32(c)==0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // result: (MOVLconst [int64(int32(c+d))]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = int64(int32(c + d)) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // result: (ADDLconst [int64(int32(c+d))] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int64(int32(c + d)) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconst_10(v *Value) bool { // match: (ADDLconst [off] x:(SP)) // result: (LEAL [off] x) for { off := v.AuxInt x := v.Args[0] if x.Op != OpSP { break } v.reset(OpAMD64LEAL) v.AuxInt = off v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconstmodify_0(v *Value) bool { // match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (ADDL x (MOVLf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSSstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDL) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDLmodify_0(v *Value) bool { // match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ_0(v *Value) bool { // match: (ADDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (ADDQconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDQ (SHRQconst x [d]) (SHLQconst x [c])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ (SHLQconst [3] y) x) // result: (LEAQ8 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { break } y := v_0.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ (SHLQconst [2] y) x) // result: (LEAQ4 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 { break } y := v_0.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ (SHLQconst [1] y) x) // result: (LEAQ2 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } y := v_0.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ_10(v *Value) bool { // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQ { break } y := v_1.Args[1] if y != v_1.Args[0] { break } v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ (ADDQ y y) x) // result: (LEAQ2 x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] if y != v_0.Args[0] { break } v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQ { break } y := v_1.Args[1] if x != v_1.Args[0] { break } v.reset(OpAMD64LEAQ2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDQ x (ADDQ y x)) // result: (LEAQ2 y x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQ { break } _ = v_1.Args[1] y := v_1.Args[0] if x != v_1.Args[1] { break } v.reset(OpAMD64LEAQ2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDQ (ADDQ x y) x) // result: (LEAQ2 y x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpAMD64LEAQ2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDQ (ADDQ y x) x) // result: (LEAQ2 y x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] y := v_0.Args[0] if x != v_0.Args[1] { break } v.reset(OpAMD64LEAQ2) v.AddArg(y) v.AddArg(x) return true } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ y (ADDQconst [c] x)) // result: (LEAQ1 [c] x y) for { _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt x := v_1.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } c := v_1.AuxInt s := v_1.Aux y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ (LEAQ [c] {s} y) x) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } c := v_0.AuxInt s := v_0.Aux y := v_0.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ_20(v *Value) bool { // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } y := v_1.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ (NEGQ y) x) // result: (SUBQ x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64NEGQ { break } y := v_0.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQcarry_0(v *Value) bool { // match: (ADDQcarry x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconstcarry x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = c v.AddArg(x) return true } // match: (ADDQcarry (MOVQconst [c]) x) // cond: is32Bit(c) // result: (ADDQconstcarry x [c]) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconst_0(v *Value) bool { // match: (ADDQconst [c] (ADDQ x y)) // result: (LEAQ1 [c] x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (SHLQconst [1] x)) // result: (LEAQ1 [c] x x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ [d] {s} x)) // cond: is32Bit(c+d) // result: (LEAQ [c+d] {s} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } d := v_0.AuxInt s := v_0.Aux x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ1 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ1 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (LEAQ2 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ2 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (LEAQ4 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ4 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (LEAQ8 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ8 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDQconst [c] (MOVQconst [d])) // result: (MOVQconst [c+d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = c + d return true } // match: (ADDQconst [c] (ADDQconst [d] x)) // cond: is32Bit(c+d) // result: (ADDQconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = c + d v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconst_10(v *Value) bool { // match: (ADDQconst [off] x:(SP)) // result: (LEAQ [off] x) for { off := v.AuxInt x := v.Args[0] if x.Op != OpSP { break } v.reset(OpAMD64LEAQ) v.AuxInt = off v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconstmodify_0(v *Value) bool { // match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ADDQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (ADDQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDQload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (ADDQ x (MOVQf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSDstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDQ) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDQmodify_0(v *Value) bool { // match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ADDQmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSD_0(v *Value) bool { // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDSD l:(MOVSDload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSDload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (ADDSD x (MOVQi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVQstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDSD) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDSS_0(v *Value) bool { // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ADDSS l:(MOVSSload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSSload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (ADDSS x (MOVLi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVLstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDSS) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ANDL_0(v *Value) bool { // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64NOTL { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { break } v.reset(OpAMD64BTRL) v.AddArg(x) v.AddArg(y) return true } // match: (ANDL x (NOTL (SHLL (MOVLconst [1]) y))) // result: (BTRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NOTL { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLL { break } y := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { break } v.reset(OpAMD64BTRL) v.AddArg(x) v.AddArg(y) return true } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRLconst [log2uint32(^c)] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = log2uint32(^c) v.AddArg(x) return true } // match: (ANDL x (MOVLconst [c])) // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRLconst [log2uint32(^c)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = log2uint32(^c) v.AddArg(x) return true } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64ANDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ANDL (MOVLconst [c]) x) // result: (ANDLconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64ANDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ANDL x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ANDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ANDL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ANDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ANDLconst_0(v *Value) bool { // match: (ANDLconst [c] x) // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRLconst [log2uint32(^c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = log2uint32(^c) v.AddArg(x) return true } // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDLconst [c] (BTRLconst [d] x)) // result: (ANDLconst [c &^ (1<= 128 // result: (BTRQconst [log2(^c)] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = log2(^c) v.AddArg(x) return true } // match: (ANDQ x (MOVQconst [c])) // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRQconst [log2(^c)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = log2(^c) v.AddArg(x) return true } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ANDQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ANDQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (ANDQconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ANDQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ANDQ x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ANDQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ANDQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ANDQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ANDQconst_0(v *Value) bool { // match: (ANDQconst [c] x) // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRQconst [log2(^c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = log2(^c) v.AddArg(x) return true } // match: (ANDQconst [c] (ANDQconst [d] x)) // result: (ANDQconst [c & d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDQconst [c] (BTRQconst [d] x)) // result: (ANDQconst [c &^ (1< [1<<8] (MOVBQZX x))) // result: (BSFQ (ORQconst [1<<8] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if v_0.AuxInt != 1<<8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVBQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = 1 << 8 v0.AddArg(x) v.AddArg(v0) return true } // match: (BSFQ (ORQconst [1<<16] (MOVWQZX x))) // result: (BSFQ (ORQconst [1<<16] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if v_0.AuxInt != 1<<16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVWQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = 1 << 16 v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64BTCLconst_0(v *Value) bool { // match: (BTCLconst [c] (XORLconst [d] x)) // result: (XORLconst [d ^ 1<d // result: (BTLconst [c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = c - d v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if v.AuxInt != 0 { break } s := v.Args[0] if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg(y) v.AddArg(x) return true } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !((c + d) < 32) { break } v.reset(OpAMD64BTLconst) v.AuxInt = c + d v.AddArg(x) return true } // match: (BTLconst [c] (SHLLconst [d] x)) // cond: c>d // result: (BTLconst [c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = c - d v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRL x y)) // result: (BTL y x) for { if v.AuxInt != 0 { break } s := v.Args[0] if s.Op != OpAMD64SHRL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64BTQconst_0(v *Value) bool { // match: (BTQconst [c] (SHRQconst [d] x)) // cond: (c+d)<64 // result: (BTQconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !((c + d) < 64) { break } v.reset(OpAMD64BTQconst) v.AuxInt = c + d v.AddArg(x) return true } // match: (BTQconst [c] (SHLQconst [d] x)) // cond: c>d // result: (BTQconst [c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTQconst) v.AuxInt = c - d v.AddArg(x) return true } // match: (BTQconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if v.AuxInt != 0 { break } s := v.Args[0] if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64BTRLconst_0(v *Value) bool { // match: (BTRLconst [c] (BTSLconst [c] x)) // result: (BTRLconst [c] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64BTSLconst || v_0.AuxInt != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = c v.AddArg(x) return true } // match: (BTRLconst [c] (BTCLconst [c] x)) // result: (BTRLconst [c] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64BTCLconst || v_0.AuxInt != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = c v.AddArg(x) return true } // match: (BTRLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [d &^ (1<uint8(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int8(x) < int8(y) && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>int8(y) && uint8(x) int8(y) && uint8(x) < uint8(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>int8(y) && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int8(x) > int8(y) && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < int8(n) // result: (FlagLT_ULT) for { n := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } m := v_0.AuxInt if !(0 <= int8(m) && int8(m) < int8(n)) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPBconst (ANDL x y) [0]) // result: (TESTB x y) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64TESTB) v.AddArg(x) v.AddArg(y) return true } // match: (CMPBconst (ANDLconst [c] x) [0]) // result: (TESTBconst [int64(int8(c))] x) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64TESTBconst) v.AuxInt = int64(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // result: (TESTB x x) for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpAMD64TESTB) v.AddArg(x) v.AddArg(x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(c,off)] ptr mem) for { c := v.AuxInt l := v.Args[0] if l.Op != OpAMD64MOVBload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(c, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconstload_0(v *Value) bool { // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (CMPBconstload [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (CMPBconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBload_0(v *Value) bool { // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (CMPBload [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // cond: validValAndOff(int64(int8(c)),off) // result: (CMPBconstload {sym} [makeValAndOff(int64(int8(c)),off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validValAndOff(int64(int8(c)), off)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPL_0(v *Value) bool { b := v.Block // match: (CMPL x (MOVLconst [c])) // result: (CMPLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64CMPLconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // result: (InvertFlags (CMPLconst x [c])) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPLload) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(x) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPLconst_0(v *Value) bool { // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)uint32(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int32(x) < int32(y) && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)>int32(y) && uint32(x) int32(y) && uint32(x) < uint32(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)>int32(y) && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int32(x) > int32(y) && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } x := v_0.AuxInt if !(x < y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>y && uint64(x)>uint64(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } x := v_0.AuxInt if !(x > y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQconst (MOVBQZX _) [c]) // cond: 0xFF < c // result: (FlagLT_ULT) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVWQZX _) [c]) // cond: 0xFFFF < c // result: (FlagLT_ULT) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVLQZX _) [c]) // cond: 0xFFFFFFFF < c // result: (FlagLT_ULT) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLQZX || !(0xFFFFFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } return false } func rewriteValueAMD64_OpAMD64CMPQconst_10(v *Value) bool { b := v.Block // match: (CMPQconst (SHRQconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 64 && (1<uint16(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int16(x) < int16(y) && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>int16(y) && uint16(x) int16(y) && uint16(x) < uint16(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>int16(y) && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int16(x) > int16(y) && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < int16(n) // result: (FlagLT_ULT) for { n := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } m := v_0.AuxInt if !(0 <= int16(m) && int16(m) < int16(n)) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPWconst (ANDL x y) [0]) // result: (TESTW x y) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64TESTW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWconst (ANDLconst [c] x) [0]) // result: (TESTWconst [int64(int16(c))] x) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64TESTWconst) v.AuxInt = int64(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // result: (TESTW x x) for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpAMD64TESTW) v.AddArg(x) v.AddArg(x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(c,off)] ptr mem) for { c := v.AuxInt l := v.Args[0] if l.Op != OpAMD64MOVWload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(c, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWconstload_0(v *Value) bool { // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (CMPWconstload [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (CMPWconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWload_0(v *Value) bool { // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (CMPWload [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // cond: validValAndOff(int64(int16(c)),off) // result: (CMPWconstload {sym} [makeValAndOff(int64(int16(c)),off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validValAndOff(int64(int16(c)), off)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGLlock_0(v *Value) bool { // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(off1+off2) // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] old := v.Args[1] new_ := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPXCHGLlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGQlock_0(v *Value) bool { // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(off1+off2) // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] old := v.Args[1] new_ := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPXCHGQlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSD_0(v *Value) bool { // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSDload_0(v *Value) bool { // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSS_0(v *Value) bool { // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSSload_0(v *Value) bool { // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64HMULL_0(v *Value) bool { // match: (HMULL x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULL y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULL) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64HMULLU_0(v *Value) bool { // match: (HMULLU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULLU y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULLU) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQ_0(v *Value) bool { // match: (HMULQ x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQ y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQ) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQU_0(v *Value) bool { // match: (HMULQU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQU y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQU) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAL_0(v *Value) bool { // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(c+d) // result: (LEAL [c+d] {s} x) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL [c] {s} (ADDL y x)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } x := v_0.Args[1] y := v_0.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL1_0(v *Value) bool { // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} y (ADDLconst [d] x)) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt x := v_1.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} (SHLLconst [1] y) x) // result: (LEAL2 [c] {s} x y) for { c := v.AuxInt s := v.Aux x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { break } y := v_0.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} (SHLLconst [2] y) x) // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 2 { break } y := v_0.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL1 [c] {s} (SHLLconst [3] y) x) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 3 { break } y := v_0.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL2_0(v *Value) bool { // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+2*d) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+2*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = c + 2*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL4_0(v *Value) bool { // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+4*d) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+4*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = c + 4*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL8_0(v *Value) bool { // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+8*d) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+8*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = c + 8*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ_0(v *Value) bool { // match: (LEAQ [c] {s} (ADDQconst [d] x)) // cond: is32Bit(c+d) // result: (LEAQ [c+d] {s} x) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (LEAQ [c] {s} (ADDQ x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [c] {s} (ADDQ y x)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } x := v_0.Args[1] y := v_0.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) return true } // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ1_0(v *Value) bool { // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} y (ADDQconst [d] x)) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt x := v_1.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} (SHLQconst [1] y) x) // result: (LEAQ2 [c] {s} x y) for { c := v.AuxInt s := v.Aux x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } y := v_0.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} (SHLQconst [2] y) x) // result: (LEAQ4 [c] {s} x y) for { c := v.AuxInt s := v.Aux x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 { break } y := v_0.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [c] {s} (SHLQconst [3] y) x) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { break } y := v_0.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ1 [off1] {sym1} y (LEAQ [off2] {sym2} x)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] y := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux x := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ2_0(v *Value) bool { // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ2 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(c+2*d) && y.Op != OpSB // result: (LEAQ2 [c+2*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+2*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = c + 2*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ4_0(v *Value) bool { // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ4 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(c+4*d) && y.Op != OpSB // result: (LEAQ4 [c+4*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+4*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = c + 4*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ4 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ8_0(v *Value) bool { // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ8 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(c+8*d) && y.Op != OpSB // result: (LEAQ8 [c+8*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+8*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = c + 8*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSX_0(v *Value) bool { b := v.Block // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVBload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0x7f v.AddArg(x) return true } // match: (MOVBQSX (MOVBQSX x)) // result: (MOVBQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSXload_0(v *Value) bool { // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBQSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQZX_0(v *Value) bool { b := v.Block // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVBload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x) // cond: zeroUpper56Bits(x,3) // result: x for { x := v.Args[0] if !(zeroUpper56Bits(x, 3)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVBQZX x:(MOVBloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVBloadidx1 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVBloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVBQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0xff v.AddArg(x) return true } // match: (MOVBQZX (MOVBQZX x)) // result: (MOVBQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBatomicload_0(v *Value) bool { // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBatomicload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBload_0(v *Value) bool { // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVBloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (ADDQ idx ptr) mem) // cond: ptr.Op != OpSB // result: (MOVBloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(read8(sym, off))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int64(read8(sym, off)) return true } return false } func rewriteValueAMD64_OpAMD64MOVBloadidx1_0(v *Value) bool { // match: (MOVBloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) // cond: is32Bit(c+d) // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) // cond: is32Bit(c+d) // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVBload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVBloadidx1 [i] {s} (MOVQconst [c]) p mem) // cond: is32Bit(i+c) // result: (MOVBload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt p := v.Args[1] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_0(v *Value) bool { // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) // cond: y.Uses == 1 // result: (SETLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETL { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) // cond: y.Uses == 1 // result: (SETLEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETLE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) // cond: y.Uses == 1 // result: (SETGstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETG { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETGstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) // cond: y.Uses == 1 // result: (SETGEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETGE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) // cond: y.Uses == 1 // result: (SETEQstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETEQ { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) // cond: y.Uses == 1 // result: (SETNEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETNE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) // cond: y.Uses == 1 // result: (SETBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETB { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) // cond: y.Uses == 1 // result: (SETBEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETBE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) // cond: y.Uses == 1 // result: (SETAstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETA { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETAstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) // cond: y.Uses == 1 // result: (SETAEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETAE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_10(v *Value) bool { b := v.Block // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBQSX { break } x := v_1.Args[0] v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBQZX { break } x := v_1.Args[0] v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validOff(off) // result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVBstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} (ADDQ idx ptr) val mem) // cond: ptr.Op != OpSB // result: (MOVBstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstore [i-1] {s} p (ROLWconst [8] w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x0 := v.Args[2] if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-1 || x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || x0_1.AuxInt != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = 8 v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_20(v *Value) bool { b := v.Block // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x2 := v.Args[2] if x2.Op != OpAMD64MOVBstore || x2.AuxInt != i-1 || x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || x2_1.AuxInt != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || x1.AuxInt != i-2 || x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || x1_1.AuxInt != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-3 || x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || x0_1.AuxInt != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 3 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x6 := v.Args[2] if x6.Op != OpAMD64MOVBstore || x6.AuxInt != i-1 || x6.Aux != s { break } _ = x6.Args[2] if p != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || x6_1.AuxInt != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || x5.AuxInt != i-2 || x5.Aux != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || x5_1.AuxInt != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || x4.AuxInt != i-3 || x4.Aux != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || x4_1.AuxInt != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || x3.AuxInt != i-4 || x3.Aux != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || x3_1.AuxInt != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || x2.AuxInt != i-5 || x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || x2_1.AuxInt != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || x1.AuxInt != i-6 || x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || x1_1.AuxInt != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-7 || x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || x0_1.AuxInt != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 7 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRWconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVBload { break } j := x1.AuxInt s2 := x1.Aux mem := x1.Args[1] p2 := x1.Args[0] mem2 := v.Args[2] if mem2.Op != OpAMD64MOVBstore || mem2.AuxInt != i-1 || mem2.Aux != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVBload || x2.AuxInt != j-1 || x2.Aux != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = j - 1 v0.Aux = s2 v0.AddArg(p2) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconst_0(v *Value) bool { // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVBstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVBstoreconst { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVBstoreconst [a] {s} p x:(MOVBstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem) for { a := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVBstoreconst { break } c := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconstidx1_0(v *Value) bool { // match: (MOVBstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconstidx1 [c] {s} p i x:(MOVBstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p i mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(i) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreidx1_0(v *Value) bool { b := v.Block // match: (MOVBstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x0:(MOVBstoreidx1 [i-1] {s} p idx (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstoreidx1 [i-1] {s} p idx (ROLWconst [8] w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x0 := v.Args[3] if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-1 || x0.Aux != s { break } mem := x0.Args[3] if p != x0.Args[0] || idx != x0.Args[1] { break } x0_2 := x0.Args[2] if x0_2.Op != OpAMD64SHRWconst || x0_2.AuxInt != 8 || w != x0_2.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = 8 v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x2:(MOVBstoreidx1 [i-1] {s} p idx (SHRLconst [8] w) x1:(MOVBstoreidx1 [i-2] {s} p idx (SHRLconst [16] w) x0:(MOVBstoreidx1 [i-3] {s} p idx (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) // result: (MOVLstoreidx1 [i-3] {s} p idx (BSWAPL w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x2 := v.Args[3] if x2.Op != OpAMD64MOVBstoreidx1 || x2.AuxInt != i-1 || x2.Aux != s { break } _ = x2.Args[3] if p != x2.Args[0] || idx != x2.Args[1] { break } x2_2 := x2.Args[2] if x2_2.Op != OpAMD64SHRLconst || x2_2.AuxInt != 8 || w != x2_2.Args[0] { break } x1 := x2.Args[3] if x1.Op != OpAMD64MOVBstoreidx1 || x1.AuxInt != i-2 || x1.Aux != s { break } _ = x1.Args[3] if p != x1.Args[0] || idx != x1.Args[1] { break } x1_2 := x1.Args[2] if x1_2.Op != OpAMD64SHRLconst || x1_2.AuxInt != 16 || w != x1_2.Args[0] { break } x0 := x1.Args[3] if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-3 || x0.Aux != s { break } mem := x0.Args[3] if p != x0.Args[0] || idx != x0.Args[1] { break } x0_2 := x0.Args[2] if x0_2.Op != OpAMD64SHRLconst || x0_2.AuxInt != 24 || w != x0_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 3 v.Aux = s v.AddArg(p) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x6:(MOVBstoreidx1 [i-1] {s} p idx (SHRQconst [8] w) x5:(MOVBstoreidx1 [i-2] {s} p idx (SHRQconst [16] w) x4:(MOVBstoreidx1 [i-3] {s} p idx (SHRQconst [24] w) x3:(MOVBstoreidx1 [i-4] {s} p idx (SHRQconst [32] w) x2:(MOVBstoreidx1 [i-5] {s} p idx (SHRQconst [40] w) x1:(MOVBstoreidx1 [i-6] {s} p idx (SHRQconst [48] w) x0:(MOVBstoreidx1 [i-7] {s} p idx (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) // result: (MOVQstoreidx1 [i-7] {s} p idx (BSWAPQ w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x6 := v.Args[3] if x6.Op != OpAMD64MOVBstoreidx1 || x6.AuxInt != i-1 || x6.Aux != s { break } _ = x6.Args[3] if p != x6.Args[0] || idx != x6.Args[1] { break } x6_2 := x6.Args[2] if x6_2.Op != OpAMD64SHRQconst || x6_2.AuxInt != 8 || w != x6_2.Args[0] { break } x5 := x6.Args[3] if x5.Op != OpAMD64MOVBstoreidx1 || x5.AuxInt != i-2 || x5.Aux != s { break } _ = x5.Args[3] if p != x5.Args[0] || idx != x5.Args[1] { break } x5_2 := x5.Args[2] if x5_2.Op != OpAMD64SHRQconst || x5_2.AuxInt != 16 || w != x5_2.Args[0] { break } x4 := x5.Args[3] if x4.Op != OpAMD64MOVBstoreidx1 || x4.AuxInt != i-3 || x4.Aux != s { break } _ = x4.Args[3] if p != x4.Args[0] || idx != x4.Args[1] { break } x4_2 := x4.Args[2] if x4_2.Op != OpAMD64SHRQconst || x4_2.AuxInt != 24 || w != x4_2.Args[0] { break } x3 := x4.Args[3] if x3.Op != OpAMD64MOVBstoreidx1 || x3.AuxInt != i-4 || x3.Aux != s { break } _ = x3.Args[3] if p != x3.Args[0] || idx != x3.Args[1] { break } x3_2 := x3.Args[2] if x3_2.Op != OpAMD64SHRQconst || x3_2.AuxInt != 32 || w != x3_2.Args[0] { break } x2 := x3.Args[3] if x2.Op != OpAMD64MOVBstoreidx1 || x2.AuxInt != i-5 || x2.Aux != s { break } _ = x2.Args[3] if p != x2.Args[0] || idx != x2.Args[1] { break } x2_2 := x2.Args[2] if x2_2.Op != OpAMD64SHRQconst || x2_2.AuxInt != 40 || w != x2_2.Args[0] { break } x1 := x2.Args[3] if x1.Op != OpAMD64MOVBstoreidx1 || x1.AuxInt != i-6 || x1.Aux != s { break } _ = x1.Args[3] if p != x1.Args[0] || idx != x1.Args[1] { break } x1_2 := x1.Args[2] if x1_2.Op != OpAMD64SHRQconst || x1_2.AuxInt != 48 || w != x1_2.Args[0] { break } x0 := x1.Args[3] if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-7 || x0.Aux != s { break } mem := x0.Args[3] if p != x0.Args[0] || idx != x0.Args[1] { break } x0_2 := x0.Args[2] if x0_2.Op != OpAMD64SHRQconst || x0_2.AuxInt != 56 || w != x0_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 7 v.Aux = s v.AddArg(p) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRWconst || v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst || v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRQconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreidx1_10(v *Value) bool { // match: (MOVBstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVBstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSX_0(v *Value) bool { b := v.Block // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQSX (ANDLconst [c] x)) // cond: c & 0x80000000 == 0 // result: (ANDLconst [c & 0x7fffffff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x80000000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0x7fffffff v.AddArg(x) return true } // match: (MOVLQSX (MOVLQSX x)) // result: (MOVLQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVWQSX x)) // result: (MOVWQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVBQSX x)) // result: (MOVBQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSXload_0(v *Value) bool { // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLQSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQZX_0(v *Value) bool { b := v.Block // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQZX x) // cond: zeroUpper32Bits(x,3) // result: x for { x := v.Args[0] if !(zeroUpper32Bits(x, 3)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVLQZX x:(MOVLloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLloadidx1 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVLQZX x:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLloadidx4 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLloadidx4 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx4, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVLQZX (ANDLconst [c] x)) // result: (ANDLconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVLQZX (MOVLQZX x)) // result: (MOVLQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVWQZX x)) // result: (MOVWQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVBQZX x)) // result: (MOVBQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLatomicload_0(v *Value) bool { // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLatomicload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLf2i_0(v *Value) bool { b := v.Block // match: (MOVLf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVLi2f_0(v *Value) bool { b := v.Block // match: (MOVLi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVLload_0(v *Value) bool { // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVLloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off] {sym} (ADDQ idx ptr) mem) // cond: ptr.Op != OpSB // result: (MOVLloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLload_10(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVSSstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVLf2i) v.AddArg(val) return true } // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64(read32(sym, off, config.BigEndian)) return true } return false } func rewriteValueAMD64_OpAMD64MOVLloadidx1_0(v *Value) bool { // match: (MOVLloadidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) // result: (MOVLloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (SHLQconst [2] idx) ptr mem) // result: (MOVLloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 { break } idx := v_0.Args[0] ptr := v.Args[1] v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVLloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (SHLQconst [3] idx) ptr mem) // result: (MOVLloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { break } idx := v_0.Args[0] ptr := v.Args[1] v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) // cond: is32Bit(c+d) // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) // cond: is32Bit(c+d) // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVLload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVLloadidx1 [i] {s} (MOVQconst [c]) p mem) // cond: is32Bit(i+c) // result: (MOVLload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt p := v.Args[1] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLloadidx4_0(v *Value) bool { // match: (MOVLloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVLloadidx4 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+4*d) // result: (MOVLloadidx4 [c+4*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx4 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+4*c) // result: (MOVLload [i+4*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLloadidx8_0(v *Value) bool { // match: (MOVLloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVLloadidx8 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+8*d) // result: (MOVLloadidx8 [c+8*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx8 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+8*c) // result: (MOVLload [i+8*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore_0(v *Value) bool { // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLQSX { break } x := v_1.Args[0] v.reset(OpAMD64MOVLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLQZX { break } x := v_1.Args[0] v.reset(OpAMD64MOVLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(int64(int32(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validOff(off) // result: (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(int64(int32(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVLstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstore [off] {sym} (ADDQ idx ptr) val mem) // cond: ptr.Op != OpSB // result: (MOVLstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst || v_1.AuxInt != 32 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVLstore || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVLstore || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVLload { break } j := x1.AuxInt s2 := x1.Aux mem := x1.Args[1] p2 := x1.Args[0] mem2 := v.Args[2] if mem2.Op != OpAMD64MOVLstore || mem2.AuxInt != i-4 || mem2.Aux != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVLload || x2.AuxInt != j-4 || x2.Aux != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x2.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = j - 4 v0.Aux = s2 v0.AddArg(p2) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore_20(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SUBL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORL x l:(MOVLload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORL { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(BTCL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTCLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTCL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTCLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore_30(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(BTRL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTRLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTRL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTRLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(BTSL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTSLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTSL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTSLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ADDLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ADDLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ANDLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ANDLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ANDLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ORLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ORLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ORLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (XORLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64XORLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64XORLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(BTCLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTCLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTCLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTCLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(BTRLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTRLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTRLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTRLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(BTSLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTSLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTSLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTSLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) // result: (MOVSSstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLf2i { break } val := v_1.Args[0] v.reset(OpAMD64MOVSSstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconst_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym1} (LEAQ4 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVLstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [c] {s} p x:(MOVLstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstore [ValAndOff(a).Off()] {s} p (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVLstoreconst { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVLstoreconst [a] {s} p x:(MOVLstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstore [ValAndOff(a).Off()] {s} p (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { a := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVLstoreconst { break } c := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconstidx1_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconstidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) // result: (MOVLstoreconstidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [c] {s} p i x:(MOVLstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstoreidx1 [ValAndOff(a).Off()] {s} p i (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVLstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconstidx4_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconstidx4 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx4 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(4*c) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(4*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(4 * c)) { break } v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(4 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx4 [c] {s} p i x:(MOVLstoreconstidx4 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstoreidx1 [ValAndOff(a).Off()] {s} p (SHLQconst [2] i) (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVLstoreconstidx4 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, i.Type) v0.AuxInt = 2 v0.AddArg(i) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v1) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreidx1_0(v *Value) bool { // match: (MOVLstoreidx1 [c] {sym} ptr (SHLQconst [2] idx) val mem) // result: (MOVLstoreidx4 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) // result: (MOVLstoreidx8 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [i] {s} p idx (SHRQconst [32] w) x:(MOVLstoreidx1 [i-4] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 32 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx1 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVLstoreidx1 [i-4] {s} p idx w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx1 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVLstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreidx4_0(v *Value) bool { b := v.Block // match: (MOVLstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx4 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+4*d) // result: (MOVLstoreidx4 [c+4*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [i] {s} p idx (SHRQconst [32] w) x:(MOVLstoreidx4 [i-4] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p (SHLQconst [2] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 32 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx4 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 2 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [i] {s} p idx (SHRQconst [j] w) x:(MOVLstoreidx4 [i-4] {s} p idx w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p (SHLQconst [2] idx) w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx4 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 2 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+4*c) // result: (MOVLstore [i+4*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreidx8_0(v *Value) bool { // match: (MOVLstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx8 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+8*d) // result: (MOVLstoreidx8 [c+8*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx8 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+8*c) // result: (MOVLstore [i+8*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOload_0(v *Value) bool { // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVOload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstore_0(v *Value) bool { // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVOstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQatomicload_0(v *Value) bool { // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVQatomicload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQf2i_0(v *Value) bool { b := v.Block // match: (MOVQf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVQi2f_0(v *Value) bool { b := v.Block // match: (MOVQi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVQload_0(v *Value) bool { // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVQloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQload [off] {sym} (ADDQ idx ptr) mem) // cond: ptr.Op != OpSB // result: (MOVQloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) // result: (MOVQf2i val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVSDstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVQf2i) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVQload_10(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64(read64(sym, off, config.BigEndian)) return true } return false } func rewriteValueAMD64_OpAMD64MOVQloadidx1_0(v *Value) bool { // match: (MOVQloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVQloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx1 [c] {sym} (SHLQconst [3] idx) ptr mem) // result: (MOVQloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { break } idx := v_0.Args[0] ptr := v.Args[1] v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) // cond: is32Bit(c+d) // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) // cond: is32Bit(c+d) // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVQload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVQloadidx1 [i] {s} (MOVQconst [c]) p mem) // cond: is32Bit(i+c) // result: (MOVQload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt p := v.Args[1] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQloadidx8_0(v *Value) bool { // match: (MOVQloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVQloadidx8 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+8*d) // result: (MOVQloadidx8 [c+8*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx8 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+8*c) // result: (MOVQload [i+8*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_0(v *Value) bool { // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validValAndOff(c,off) // result: (MOVQstoreconst [makeValAndOff(c,off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validValAndOff(c, off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVQstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} (ADDQ idx ptr) val mem) // cond: ptr.Op != OpSB // result: (MOVQstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_10(v *Value) bool { // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ x l:(MOVQload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDQ { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SUBQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ x l:(MOVQload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDQ { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQ x l:(MOVQload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORQ { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_20(v *Value) bool { // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQ x l:(MOVQload [off] {sym} ptr mem)) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORQ { break } _ = y.Args[1] x := y.Args[0] l := y.Args[1] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(BTCQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTCQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTCQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTCQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(BTRQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTRQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTRQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTRQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(BTSQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTSQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTSQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTSQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ADDQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ADDQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ANDQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ANDQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ANDQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ORQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ORQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ORQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (XORQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64XORQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64XORQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(BTCQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTCQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTCQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTCQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_30(v *Value) bool { // match: (MOVQstore [off] {sym} ptr a:(BTRQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTRQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTRQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTRQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(BTSQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTSQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTSQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTSQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) // result: (MOVSDstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQf2i { break } val := v_1.Args[0] v.reset(OpAMD64MOVSDstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconst_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVQstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconst [x] {sym1} (LEAQ8 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVQstoreconstidx8 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVQstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconst [c] {s} p x:(MOVQstoreconst [c2] {s} p mem)) // cond: config.useSSE && x.Uses == 1 && ValAndOff(c2).Off() + 8 == ValAndOff(c).Off() && ValAndOff(c).Val() == 0 && ValAndOff(c2).Val() == 0 && clobber(x) // result: (MOVOstore [ValAndOff(c2).Off()] {s} p (MOVOconst [0]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVQstoreconst { break } c2 := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(config.useSSE && x.Uses == 1 && ValAndOff(c2).Off()+8 == ValAndOff(c).Off() && ValAndOff(c).Val() == 0 && ValAndOff(c2).Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = ValAndOff(c2).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(x.Pos, OpAMD64MOVOconst, types.TypeInt128) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconstidx1_0(v *Value) bool { // match: (MOVQstoreconstidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVQstoreconstidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVQstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVQstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconstidx8_0(v *Value) bool { // match: (MOVQstoreconstidx8 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVQstoreconstidx8 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconstidx8 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(8*c) // result: (MOVQstoreconstidx8 [ValAndOff(x).add(8*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(8 * c)) { break } v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = ValAndOff(x).add(8 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreidx1_0(v *Value) bool { // match: (MOVQstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) // result: (MOVQstoreidx8 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVQstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVQstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVQstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreidx8_0(v *Value) bool { // match: (MOVQstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVQstoreidx8 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+8*d) // result: (MOVQstoreidx8 [c+8*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx8 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+8*c) // result: (MOVQstore [i+8*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDload_0(v *Value) bool { // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVSDloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off] {sym} (ADDQ idx ptr) mem) // cond: ptr.Op != OpSB // result: (MOVSDloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVQi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDloadidx1_0(v *Value) bool { // match: (MOVSDloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVSDloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSDloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVSDloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVSDload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDloadidx8_0(v *Value) bool { // match: (MOVSDloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSDloadidx8 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+8*d) // result: (MOVSDloadidx8 [c+8*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx8 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+8*c) // result: (MOVSDload [i+8*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstore_0(v *Value) bool { // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVSDstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off] {sym} (ADDQ idx ptr) val mem) // cond: ptr.Op != OpSB // result: (MOVSDstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQi2f { break } val := v_1.Args[0] v.reset(OpAMD64MOVQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstoreidx1_0(v *Value) bool { // match: (MOVSDstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) // result: (MOVSDstoreidx8 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSDstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVSDstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVSDstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstoreidx8_0(v *Value) bool { // match: (MOVSDstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSDstoreidx8 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+8*d) // result: (MOVSDstoreidx8 [c+8*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx8 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+8*c) // result: (MOVSDstore [i+8*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSload_0(v *Value) bool { // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVSSloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off] {sym} (ADDQ idx ptr) mem) // cond: ptr.Op != OpSB // result: (MOVSSloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVLi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSloadidx1_0(v *Value) bool { // match: (MOVSSloadidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) // result: (MOVSSloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSSloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVSSloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVSSload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSloadidx4_0(v *Value) bool { // match: (MOVSSloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSSloadidx4 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+4*d) // result: (MOVSSloadidx4 [c+4*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx4 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+4*c) // result: (MOVSSload [i+4*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstore_0(v *Value) bool { // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVSSstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off] {sym} (ADDQ idx ptr) val mem) // cond: ptr.Op != OpSB // result: (MOVSSstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLi2f { break } val := v_1.Args[0] v.reset(OpAMD64MOVLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstoreidx1_0(v *Value) bool { // match: (MOVSSstoreidx1 [c] {sym} ptr (SHLQconst [2] idx) val mem) // result: (MOVSSstoreidx4 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSSstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVSSstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVSSstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstoreidx4_0(v *Value) bool { // match: (MOVSSstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSSstoreidx4 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+4*d) // result: (MOVSSstoreidx4 [c+4*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx4 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+4*c) // result: (MOVSSstore [i+4*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSX_0(v *Value) bool { b := v.Block // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0x7fff v.AddArg(x) return true } // match: (MOVWQSX (MOVWQSX x)) // result: (MOVWQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSX (MOVBQSX x)) // result: (MOVBQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSXload_0(v *Value) bool { // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWQSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQZX_0(v *Value) bool { b := v.Block // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQZX x) // cond: zeroUpper48Bits(x,3) // result: x for { x := v.Args[0] if !(zeroUpper48Bits(x, 3)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWQZX x:(MOVWloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWloadidx1 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVWQZX x:(MOVWloadidx2 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWloadidx2 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWloadidx2 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx2, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVWQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xffff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0xffff v.AddArg(x) return true } // match: (MOVWQZX (MOVWQZX x)) // result: (MOVWQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWQZX (MOVBQZX x)) // result: (MOVBQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWload_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWloadidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWloadidx2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVWloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (ADDQ idx ptr) mem) // cond: ptr.Op != OpSB // result: (MOVWloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(read16(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int64(read16(sym, off, config.BigEndian)) return true } return false } func rewriteValueAMD64_OpAMD64MOVWloadidx1_0(v *Value) bool { // match: (MOVWloadidx1 [c] {sym} ptr (SHLQconst [1] idx) mem) // result: (MOVWloadidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} (SHLQconst [1] idx) ptr mem) // result: (MOVWloadidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } idx := v_0.Args[0] ptr := v.Args[1] v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) // cond: is32Bit(c+d) // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] idx := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) // cond: is32Bit(c+d) // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt idx := v_0.Args[0] ptr := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVWload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVWloadidx1 [i] {s} (MOVQconst [c]) p mem) // cond: is32Bit(i+c) // result: (MOVWload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt p := v.Args[1] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWloadidx2_0(v *Value) bool { // match: (MOVWloadidx2 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVWloadidx2 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx2 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+2*d) // result: (MOVWloadidx2 [c+2*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 2*d)) { break } v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c + 2*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx2 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+2*c) // result: (MOVWload [i+2*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 2*c)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = i + 2*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore_0(v *Value) bool { // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWQSX { break } x := v_1.Args[0] v.reset(OpAMD64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWQZX { break } x := v_1.Args[0] v.reset(OpAMD64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validOff(off) // result: (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstoreidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVWstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} (ADDQ idx ptr) val mem) // cond: ptr.Op != OpSB // result: (MOVWstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } ptr := v_0.Args[1] idx := v_0.Args[0] val := v.Args[1] if !(ptr.Op != OpSB) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst || v_1.AuxInt != 16 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst || v_1.AuxInt != 16 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVWload { break } j := x1.AuxInt s2 := x1.Aux mem := x1.Args[1] p2 := x1.Args[0] mem2 := v.Args[2] if mem2.Op != OpAMD64MOVWstore || mem2.AuxInt != i-2 || mem2.Aux != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVWload || x2.AuxInt != j-2 || x2.Aux != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x2.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = j - 2 v0.Aux = s2 v0.AddArg(p2) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconst_0(v *Value) bool { // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym1} (LEAQ2 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVWstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVWstoreconst { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVWstoreconst [a] {s} p x:(MOVWstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem) for { a := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVWstoreconst { break } c := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconstidx1_0(v *Value) bool { // match: (MOVWstoreconstidx1 [c] {sym} ptr (SHLQconst [1] idx) mem) // result: (MOVWstoreconstidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [c] {s} p i x:(MOVWstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p i mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVWstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(i) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconstidx2_0(v *Value) bool { b := v.Block // match: (MOVWstoreconstidx2 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx2 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(2*c) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(2*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(2 * c)) { break } v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(2 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx2 [c] {s} p i x:(MOVWstoreconstidx2 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p (SHLQconst [1] i) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVWstoreconstidx2 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, i.Type) v0.AuxInt = 1 v0.AddArg(i) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreidx1_0(v *Value) bool { // match: (MOVWstoreidx1 [c] {sym} ptr (SHLQconst [1] idx) val mem) // result: (MOVWstoreidx2 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVWstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVWstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRQconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVWstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreidx2_0(v *Value) bool { b := v.Block // match: (MOVWstoreidx2 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVWstoreidx2 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+2*d) // result: (MOVWstoreidx2 [c+2*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 2*d)) { break } v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = c + 2*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLQconst [1] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx2 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRQconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLQconst [1] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx2 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRQconst [j] w) x:(MOVWstoreidx2 [i-2] {s} p idx w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLQconst [1] idx) w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx2 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+2*c) // result: (MOVWstore [i+2*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 2*c)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i + 2*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MULL_0(v *Value) bool { // match: (MULL x (MOVLconst [c])) // result: (MULLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64MULLconst) v.AuxInt = c v.AddArg(x) return true } // match: (MULL (MOVLconst [c]) x) // result: (MULLconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64MULLconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_0(v *Value) bool { b := v.Block // match: (MULLconst [c] (MULLconst [d] x)) // result: (MULLconst [int64(int32(c * d))] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MULLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64MULLconst) v.AuxInt = int64(int32(c * d)) v.AddArg(x) return true } // match: (MULLconst [-9] x) // result: (NEGL (LEAL8 x x)) for { if v.AuxInt != -9 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // result: (NEGL (LEAL4 x x)) for { if v.AuxInt != -5 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // result: (NEGL (LEAL2 x x)) for { if v.AuxInt != -3 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // result: (NEGL x) for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } // match: (MULLconst [ 0] _) // result: (MOVLconst [0]) for { if v.AuxInt != 0 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (MULLconst [ 1] x) // result: x for { if v.AuxInt != 1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MULLconst [ 3] x) // result: (LEAL2 x x) for { if v.AuxInt != 3 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [ 5] x) // result: (LEAL4 x x) for { if v.AuxInt != 5 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [ 7] x) // result: (LEAL2 x (LEAL2 x x)) for { if v.AuxInt != 7 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_10(v *Value) bool { b := v.Block // match: (MULLconst [ 9] x) // result: (LEAL8 x x) for { if v.AuxInt != 9 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [11] x) // result: (LEAL2 x (LEAL4 x x)) for { if v.AuxInt != 11 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [13] x) // result: (LEAL4 x (LEAL2 x x)) for { if v.AuxInt != 13 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [19] x) // result: (LEAL2 x (LEAL8 x x)) for { if v.AuxInt != 19 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [21] x) // result: (LEAL4 x (LEAL4 x x)) for { if v.AuxInt != 21 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [25] x) // result: (LEAL8 x (LEAL2 x x)) for { if v.AuxInt != 25 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [27] x) // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if v.AuxInt != 27 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULLconst [37] x) // result: (LEAL4 x (LEAL8 x x)) for { if v.AuxInt != 37 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [41] x) // result: (LEAL8 x (LEAL4 x x)) for { if v.AuxInt != 41 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [45] x) // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if v.AuxInt != 45 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_20(v *Value) bool { b := v.Block // match: (MULLconst [73] x) // result: (LEAL8 x (LEAL8 x x)) for { if v.AuxInt != 73 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [81] x) // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if v.AuxInt != 81 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c+1) && c >= 15 // result: (SUBL (SHLLconst [log2(c+1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c+1) && c >= 15) { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c + 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [log2(c-1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-1) && c >= 17) { break } v.reset(OpAMD64LEAL1) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [log2(c-2)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-2) && c >= 34) { break } v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 2) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [log2(c-4)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-4) && c >= 68) { break } v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 4) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [log2(c-8)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-8) && c >= 136) { break } v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 8) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo(c/3) // result: (SHLLconst [log2(c/3)] (LEAL2 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%3 == 0 && isPowerOfTwo(c/3)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = log2(c / 3) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo(c/5) // result: (SHLLconst [log2(c/5)] (LEAL4 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%5 == 0 && isPowerOfTwo(c/5)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = log2(c / 5) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo(c/9) // result: (SHLLconst [log2(c/9)] (LEAL8 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%9 == 0 && isPowerOfTwo(c/9)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = log2(c / 9) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_30(v *Value) bool { // match: (MULLconst [c] (MOVLconst [d])) // result: (MOVLconst [int64(int32(c*d))]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = int64(int32(c * d)) return true } return false } func rewriteValueAMD64_OpAMD64MULQ_0(v *Value) bool { // match: (MULQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (MULQconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = c v.AddArg(x) return true } // match: (MULQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (MULQconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_0(v *Value) bool { b := v.Block // match: (MULQconst [c] (MULQconst [d] x)) // cond: is32Bit(c*d) // result: (MULQconst [c * d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MULQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c * d)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = c * d v.AddArg(x) return true } // match: (MULQconst [-9] x) // result: (NEGQ (LEAQ8 x x)) for { if v.AuxInt != -9 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [-5] x) // result: (NEGQ (LEAQ4 x x)) for { if v.AuxInt != -5 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [-3] x) // result: (NEGQ (LEAQ2 x x)) for { if v.AuxInt != -3 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [-1] x) // result: (NEGQ x) for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v.AddArg(x) return true } // match: (MULQconst [ 0] _) // result: (MOVQconst [0]) for { if v.AuxInt != 0 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (MULQconst [ 1] x) // result: x for { if v.AuxInt != 1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MULQconst [ 3] x) // result: (LEAQ2 x x) for { if v.AuxInt != 3 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(x) return true } // match: (MULQconst [ 5] x) // result: (LEAQ4 x x) for { if v.AuxInt != 5 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v.AddArg(x) return true } // match: (MULQconst [ 7] x) // result: (LEAQ2 x (LEAQ2 x x)) for { if v.AuxInt != 7 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_10(v *Value) bool { b := v.Block // match: (MULQconst [ 9] x) // result: (LEAQ8 x x) for { if v.AuxInt != 9 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v.AddArg(x) return true } // match: (MULQconst [11] x) // result: (LEAQ2 x (LEAQ4 x x)) for { if v.AuxInt != 11 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [13] x) // result: (LEAQ4 x (LEAQ2 x x)) for { if v.AuxInt != 13 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [19] x) // result: (LEAQ2 x (LEAQ8 x x)) for { if v.AuxInt != 19 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [21] x) // result: (LEAQ4 x (LEAQ4 x x)) for { if v.AuxInt != 21 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [25] x) // result: (LEAQ8 x (LEAQ2 x x)) for { if v.AuxInt != 25 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [27] x) // result: (LEAQ8 (LEAQ2 x x) (LEAQ2 x x)) for { if v.AuxInt != 27 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULQconst [37] x) // result: (LEAQ4 x (LEAQ8 x x)) for { if v.AuxInt != 37 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [41] x) // result: (LEAQ8 x (LEAQ4 x x)) for { if v.AuxInt != 41 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [45] x) // result: (LEAQ8 (LEAQ4 x x) (LEAQ4 x x)) for { if v.AuxInt != 45 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_20(v *Value) bool { b := v.Block // match: (MULQconst [73] x) // result: (LEAQ8 x (LEAQ8 x x)) for { if v.AuxInt != 73 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [81] x) // result: (LEAQ8 (LEAQ8 x x) (LEAQ8 x x)) for { if v.AuxInt != 81 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c+1) && c >= 15 // result: (SUBQ (SHLQconst [log2(c+1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c+1) && c >= 15) { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c + 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-1) && c >= 17 // result: (LEAQ1 (SHLQconst [log2(c-1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-1) && c >= 17) { break } v.reset(OpAMD64LEAQ1) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-2) && c >= 34 // result: (LEAQ2 (SHLQconst [log2(c-2)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-2) && c >= 34) { break } v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 2) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-4) && c >= 68 // result: (LEAQ4 (SHLQconst [log2(c-4)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-4) && c >= 68) { break } v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 4) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-8) && c >= 136 // result: (LEAQ8 (SHLQconst [log2(c-8)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-8) && c >= 136) { break } v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 8) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: c%3 == 0 && isPowerOfTwo(c/3) // result: (SHLQconst [log2(c/3)] (LEAQ2 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%3 == 0 && isPowerOfTwo(c/3)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = log2(c / 3) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%5 == 0 && isPowerOfTwo(c/5) // result: (SHLQconst [log2(c/5)] (LEAQ4 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%5 == 0 && isPowerOfTwo(c/5)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = log2(c / 5) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%9 == 0 && isPowerOfTwo(c/9) // result: (SHLQconst [log2(c/9)] (LEAQ8 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%9 == 0 && isPowerOfTwo(c/9)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = log2(c / 9) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_30(v *Value) bool { // match: (MULQconst [c] (MOVQconst [d])) // result: (MOVQconst [c*d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = c * d return true } // match: (MULQconst [c] (NEGQ x)) // cond: c != -(1<<31) // result: (MULQconst [-c] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = -c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULSD_0(v *Value) bool { // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MULSD l:(MOVSDload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MULSDload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (MULSD x (MOVQi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVQstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64MULSD) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULSS_0(v *Value) bool { // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MULSS l:(MOVSSload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MULSSload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (MULSS x (MOVLi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVLstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64MULSS) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64NEGL_0(v *Value) bool { // match: (NEGL (NEGL x)) // result: x for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGL { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (NEGL s:(SUBL x y)) // cond: s.Uses == 1 // result: (SUBL y x) for { s := v.Args[0] if s.Op != OpAMD64SUBL { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBL) v.AddArg(y) v.AddArg(x) return true } // match: (NEGL (MOVLconst [c])) // result: (MOVLconst [int64(int32(-c))]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = int64(int32(-c)) return true } return false } func rewriteValueAMD64_OpAMD64NEGQ_0(v *Value) bool { // match: (NEGQ (NEGQ x)) // result: x for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (NEGQ s:(SUBQ x y)) // cond: s.Uses == 1 // result: (SUBQ y x) for { s := v.Args[0] if s.Op != OpAMD64SUBQ { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBQ) v.AddArg(y) v.AddArg(x) return true } // match: (NEGQ (MOVQconst [c])) // result: (MOVQconst [-c]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = -c return true } // match: (NEGQ (ADDQconst [c] (NEGQ x))) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } x := v_0_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = -c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64NOTL_0(v *Value) bool { // match: (NOTL (MOVLconst [c])) // result: (MOVLconst [^c]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = ^c return true } return false } func rewriteValueAMD64_OpAMD64NOTQ_0(v *Value) bool { // match: (NOTQ (MOVQconst [c])) // result: (MOVQconst [^c]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = ^c return true } return false } func rewriteValueAMD64_OpAMD64ORL_0(v *Value) bool { // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { break } v.reset(OpAMD64BTSL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL x (SHLL (MOVLconst [1]) y)) // result: (BTSL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64MOVLconst || v_1_0.AuxInt != 1 { break } v.reset(OpAMD64BTSL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSLconst [log2uint32(c)] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (ORL x (MOVLconst [c])) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSLconst [log2uint32(c)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64ORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (MOVLconst [c]) x) // result: (ORLconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64ORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHRLconst x [d]) (SHLLconst x [c])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { break } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHRWconst x [d]) (SHLLconst x [c])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { break } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ORL_10(v *Value) bool { // match: (ORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRBconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { break } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHRBconst x [d]) (SHLLconst x [c])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRBconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { break } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRL { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x y) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHRL x (NEGQ y)))) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 32 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGQ { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -32 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRL { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32]))) (SHLL x y)) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRL { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGQ { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 32 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGQ { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -32 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHRL x (NEGQ y))) (SHLL x y)) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 32 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGQ { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -32 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 31 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRL { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRL { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x y) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHRL x (NEGL y)))) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 32 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGL { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -32 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRL { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32]))) (SHLL x y)) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRL { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGL { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 32 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGL { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -32 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHRL x (NEGL y))) (SHLL x y)) // result: (ROLL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 32 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGL { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -32 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 31 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRL { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_20(v *Value) bool { // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLL { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHRL x y) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHLL x (NEGQ y)))) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 32 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGQ { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -32 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLL { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32]))) (SHRL x y)) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGQ { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 32 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGQ { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -32 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHLL x (NEGQ y))) (SHRL x y)) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 32 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGQ { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -32 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 31 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLL { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLL { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHRL x y) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHLL x (NEGL y)))) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRL { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 32 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGL { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -32 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLL { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32]))) (SHRL x y)) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGL { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 32 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGL { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -32 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHLL x (NEGL y))) (SHRL x y)) // result: (RORL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 32 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGL { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -32 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 31 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLL { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRL { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRW { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { break } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -16 { break } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 16 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -16 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])) (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 16 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGQ { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -16 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 15 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRW { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGQ { break } v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpAMD64ADDQconst || v_1_1_1_0.AuxInt != -16 { break } v_1_1_1_0_0 := v_1_1_1_0.Args[0] if v_1_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_1_0_0.AuxInt != 15 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_30(v *Value) bool { // match: (ORL (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16]))) (SHLL x (ANDQconst y [15]))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRW { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGQ { break } v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpAMD64ADDQconst || v_0_0_1_0.AuxInt != -16 { break } v_0_0_1_0_0 := v_0_0_1_0.Args[0] if v_0_0_1_0_0.Op != OpAMD64ANDQconst || v_0_0_1_0_0.AuxInt != 15 { break } y := v_0_0_1_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 16 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGQ { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -16 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 15 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])) (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) (SHLL x (ANDQconst y [15]))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 16 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGQ { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -16 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 15 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRW { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGQ { break } v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpAMD64ADDQconst || v_0_1_1_0.AuxInt != -16 { break } v_0_1_1_0_0 := v_0_1_1_0.Args[0] if v_0_1_1_0_0.Op != OpAMD64ANDQconst || v_0_1_1_0_0.AuxInt != 15 || y != v_0_1_1_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRW { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { break } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -16 { break } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 16 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -16 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])) (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 16 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGL { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -16 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 15 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRW { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGL { break } v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpAMD64ADDLconst || v_1_1_1_0.AuxInt != -16 { break } v_1_1_1_0_0 := v_1_1_1_0.Args[0] if v_1_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_1_0_0.AuxInt != 15 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16]))) (SHLL x (ANDLconst y [15]))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRW { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGL { break } v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpAMD64ADDLconst || v_0_0_1_0.AuxInt != -16 { break } v_0_0_1_0_0 := v_0_0_1_0.Args[0] if v_0_0_1_0_0.Op != OpAMD64ANDLconst || v_0_0_1_0_0.AuxInt != 15 { break } y := v_0_0_1_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 16 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGL { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -16 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 15 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])) (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) (SHLL x (ANDLconst y [15]))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 16 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGL { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -16 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 15 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRW { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGL { break } v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpAMD64ADDLconst || v_0_1_1_0.AuxInt != -16 { break } v_0_1_1_0_0 := v_0_1_1_0.Args[0] if v_0_1_1_0_0.Op != OpAMD64ANDLconst || v_0_1_1_0_0.AuxInt != 15 || y != v_0_1_1_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHRW x (ANDQconst y [15])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -16 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64RORW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SHRW x (ANDQconst y [15]))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64NEGQ { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64ADDQconst || v_0_1_0.AuxInt != -16 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0.AuxInt != 15 { break } y := v_0_1_0_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64RORW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHRW x (ANDLconst y [15])) (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -16 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64RORW) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SHRW x (ANDLconst y [15]))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64NEGL { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64ADDLconst || v_0_1_0.AuxInt != -16 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0.AuxInt != 15 { break } y := v_0_1_0_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { break } v.reset(OpAMD64RORW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_40(v *Value) bool { // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRB { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { break } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -8 { break } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 8 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -8 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 8 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGQ { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -8 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 7 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRB { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGQ { break } v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpAMD64ADDQconst || v_1_1_1_0.AuxInt != -8 { break } v_1_1_1_0_0 := v_1_1_1_0.Args[0] if v_1_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_1_0_0.AuxInt != 7 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8]))) (SHLL x (ANDQconst y [ 7]))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRB { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGQ { break } v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpAMD64ADDQconst || v_0_0_1_0.AuxInt != -8 { break } v_0_0_1_0_0 := v_0_0_1_0.Args[0] if v_0_0_1_0_0.Op != OpAMD64ANDQconst || v_0_0_1_0_0.AuxInt != 7 { break } y := v_0_0_1_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 8 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGQ { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -8 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 7 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) (SHLL x (ANDQconst y [ 7]))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 8 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGQ { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -8 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 7 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRB { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGQ { break } v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpAMD64ADDQconst || v_0_1_1_0.AuxInt != -8 { break } v_0_1_1_0_0 := v_0_1_1_0.Args[0] if v_0_1_1_0_0.Op != OpAMD64ANDQconst || v_0_1_1_0_0.AuxInt != 7 || y != v_0_1_1_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRB { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { break } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -8 { break } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBLcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 8 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -8 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBLcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 8 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGL { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -8 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 7 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRB { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGL { break } v_1_1_1_0 := v_1_1_1.Args[0] if v_1_1_1_0.Op != OpAMD64ADDLconst || v_1_1_1_0.AuxInt != -8 { break } v_1_1_1_0_0 := v_1_1_1_0.Args[0] if v_1_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_1_0_0.AuxInt != 7 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8]))) (SHLL x (ANDLconst y [ 7]))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRB { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGL { break } v_0_0_1_0 := v_0_0_1.Args[0] if v_0_0_1_0.Op != OpAMD64ADDLconst || v_0_0_1_0.AuxInt != -8 { break } v_0_0_1_0_0 := v_0_0_1_0.Args[0] if v_0_0_1_0_0.Op != OpAMD64ANDLconst || v_0_0_1_0_0.AuxInt != 7 { break } y := v_0_0_1_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBLcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 8 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGL { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -8 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 7 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) (SHLL x (ANDLconst y [ 7]))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBLcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 8 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGL { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -8 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 7 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRB { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGL { break } v_0_1_1_0 := v_0_1_1.Args[0] if v_0_1_1_0.Op != OpAMD64ADDLconst || v_0_1_1_0.AuxInt != -8 { break } v_0_1_1_0_0 := v_0_1_1_0.Args[0] if v_0_1_1_0_0.Op != OpAMD64ANDLconst || v_0_1_1_0_0.AuxInt != 7 || y != v_0_1_1_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRB { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -8 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64RORB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SHRB x (ANDQconst y [ 7]))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64NEGQ { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64ADDQconst || v_0_1_0.AuxInt != -8 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0.AuxInt != 7 { break } y := v_0_1_0_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRB { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64RORB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_50(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRB { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -8 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64RORB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SHRB x (ANDLconst y [ 7]))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64NEGL { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64ADDLconst || v_0_1_0.AuxInt != -8 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0.AuxInt != 7 { break } y := v_0_1_0_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRB { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { break } v.reset(OpAMD64RORB) v.AddArg(x) v.AddArg(y) return true } // match: (ORL x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ORL x0:(MOVBload [i0] {s} p mem) sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem)) x0:(MOVBload [i0] {s} p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem)) x0:(MOVWload [i0] {s} p mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y) s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_60(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem))) s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORL_70(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_80(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_90(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem)) x1:(MOVBload [i1] {s} p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y) s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_100(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem))) s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64ORL_110(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_120(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORL_130(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORL { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLLconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLLconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ORL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORLconst_0(v *Value) bool { // match: (ORLconst [c] x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSLconst [log2uint32(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (ORLconst [c] (ORLconst [d] x)) // result: (ORLconst [c | d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ORLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ORLconst) v.AuxInt = c | d v.AddArg(x) return true } // match: (ORLconst [c] (BTSLconst [d] x)) // result: (ORLconst [c | 1<= 128 // result: (BTSQconst [log2(c)] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (ORQ x (MOVQconst [c])) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSQconst [log2(c)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ORQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (ORQconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64ORQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORQ (SHRQconst x [d]) (SHLQconst x [c])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRQ { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBQcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (SHLQ x y) (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHRQ x (NEGQ y)))) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBQcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 64 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGQ { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -64 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRQ { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_10(v *Value) bool { // match: (ORQ (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64]))) (SHLQ x y)) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRQ { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGQ { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBQcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 64 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGQ { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -64 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHRQ x (NEGQ y))) (SHLQ x y)) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBQcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 64 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGQ { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -64 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 63 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRQ { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHRQ { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBQcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (SHLQ x y) (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHRQ x (NEGL y)))) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBQcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 64 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGL { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -64 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHRQ { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64]))) (SHLQ x y)) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHRQ { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGL { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBQcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 64 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGL { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -64 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHRQ x (NEGL y))) (SHLQ x y)) // result: (ROLQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBQcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 64 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGL { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -64 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 63 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHRQ { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLQ { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBQcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (SHRQ x y) (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHLQ x (NEGQ y)))) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBQcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 64 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGQ { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -64 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLQ { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64]))) (SHRQ x y)) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLQ { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGQ { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBQcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 64 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGQ { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -64 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHLQ x (NEGQ y))) (SHRQ x y)) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBQcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 64 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGQ { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -64 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 63 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLQ { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLQ { break } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { break } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SBBQcarrymask { break } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { break } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { break } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { break } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (SHRQ x y) (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHLQ x (NEGL y)))) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQ { break } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SBBQcarrymask { break } v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 64 { break } v_1_0_0_0 := v_1_0_0.Args[0] if v_1_0_0_0.Op != OpAMD64NEGL { break } v_1_0_0_0_0 := v_1_0_0_0.Args[0] if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -64 { break } v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLQ { break } _ = v_1_1.Args[1] if x != v_1_1.Args[0] { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64]))) (SHRQ x y)) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLQ { break } _ = v_0_0.Args[1] x := v_0_0.Args[0] v_0_0_1 := v_0_0.Args[1] if v_0_0_1.Op != OpAMD64NEGL { break } y := v_0_0_1.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SBBQcarrymask { break } v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 64 { break } v_0_1_0_0 := v_0_1_0.Args[0] if v_0_1_0_0.Op != OpAMD64NEGL { break } v_0_1_0_0_0 := v_0_1_0_0.Args[0] if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -64 { break } v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHLQ x (NEGL y))) (SHRQ x y)) // result: (RORQ x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SBBQcarrymask { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 64 { break } v_0_0_0_0 := v_0_0_0.Args[0] if v_0_0_0_0.Op != OpAMD64NEGL { break } v_0_0_0_0_0 := v_0_0_0_0.Args[0] if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -64 { break } v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 63 { break } y := v_0_0_0_0_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLQ { break } _ = v_0_1.Args[1] x := v_0_1.Args[0] v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { break } v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQ { break } _ = v_1.Args[1] if x != v_1.Args[0] || y != v_1.Args[1] { break } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } // match: (ORQ x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ORQ x0:(MOVBload [i0] {s} p mem) sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem)) x0:(MOVBload [i0] {s} p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem)) x0:(MOVWload [i0] {s} p mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVLload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem)) x0:(MOVLload [i0] {s} p mem)) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpAMD64MOVLload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y) s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem))) s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y) s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem))) s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_40(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_50(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVLloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVLloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVLloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ x0:(MOVLloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem)) x0:(MOVLloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_60(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem)) x0:(MOVLloadidx1 [i0] {s} p idx mem)) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem)) x0:(MOVLloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem)) x0:(MOVLloadidx1 [i0] {s} idx p mem)) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] x0 := v.Args[1] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_70(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_80(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_90(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s0 := or.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s0 := or.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] s1 := v.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem)) x1:(MOVBload [i1] {s} p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_100(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem))) r1:(BSWAPL x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] r1 := v.Args[1] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y) s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem))) s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_110(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] x1 := v.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { break } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] x1 := v.Args[1] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_120(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { break } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] r1 := v.Args[0] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] sh := v.Args[1] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_130(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] sh := v.Args[0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { break } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] r1 := v.Args[1] if r1.Op != OpAMD64BSWAPL { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_140(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_150(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] p := x0.Args[0] idx := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] idx := x0.Args[0] p := x0.Args[1] or := v.Args[1] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ORQ_160(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } y := or.Args[1] s1 := or.Args[0] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] p := x1.Args[0] idx := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] or := v.Args[0] if or.Op != OpAMD64ORQ { break } _ = or.Args[1] y := or.Args[0] s1 := or.Args[1] if s1.Op != OpAMD64SHLQconst { break } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { break } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] idx := x1.Args[0] p := x1.Args[1] s0 := v.Args[1] if s0.Op != OpAMD64SHLQconst { break } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { break } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { break } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ORQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (ORQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64ORQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ORQconst_0(v *Value) bool { // match: (ORQconst [c] x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSQconst [log2(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (ORQconst [c] (ORQconst [d] x)) // result: (ORQconst [c | d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ORQconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ORQconst) v.AuxInt = c | d v.AddArg(x) return true } // match: (ORQconst [c] (BTSQconst [d] x)) // result: (ORQconst [c | 1<>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = int64(int8(d)) >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SARL_0(v *Value) bool { b := v.Block // match: (SARL x (MOVQconst [c])) // result: (SARLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SARLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SARL x (MOVLconst [c])) // result: (SARLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SARLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SARL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARLconst_0(v *Value) bool { // match: (SARLconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARLconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int32(d))>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = int64(int32(d)) >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SARQ_0(v *Value) bool { b := v.Block // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SARQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SARQ x (MOVLconst [c])) // result: (SARQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SARQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SARQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARQconst_0(v *Value) bool { // match: (SARQconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARQconst [c] (MOVQconst [d])) // result: (MOVQconst [d>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = d >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SARW_0(v *Value) bool { // match: (SARW x (MOVQconst [c])) // result: (SARWconst [min(c&31,15)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SARWconst) v.AuxInt = min(c&31, 15) v.AddArg(x) return true } // match: (SARW x (MOVLconst [c])) // result: (SARWconst [min(c&31,15)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SARWconst) v.AuxInt = min(c&31, 15) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SARWconst_0(v *Value) bool { // match: (SARWconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARWconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int16(d))>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = int64(int16(d)) >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SBBLcarrymask_0(v *Value) bool { // match: (SBBLcarrymask (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SBBLcarrymask (FlagLT_ULT)) // result: (MOVLconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = -1 return true } // match: (SBBLcarrymask (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SBBLcarrymask (FlagGT_ULT)) // result: (MOVLconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = -1 return true } // match: (SBBLcarrymask (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SBBQ_0(v *Value) bool { // match: (SBBQ x (MOVQconst [c]) borrow) // cond: is32Bit(c) // result: (SBBQconst x [c] borrow) for { borrow := v.Args[2] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64SBBQconst) v.AuxInt = c v.AddArg(x) v.AddArg(borrow) return true } // match: (SBBQ x y (FlagEQ)) // result: (SUBQborrow x y) for { _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQborrow) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64SBBQcarrymask_0(v *Value) bool { // match: (SBBQcarrymask (FlagEQ)) // result: (MOVQconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (SBBQcarrymask (FlagLT_ULT)) // result: (MOVQconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = -1 return true } // match: (SBBQcarrymask (FlagLT_UGT)) // result: (MOVQconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (SBBQcarrymask (FlagGT_ULT)) // result: (MOVQconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = -1 return true } // match: (SBBQcarrymask (FlagGT_UGT)) // result: (MOVQconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SBBQconst_0(v *Value) bool { // match: (SBBQconst x [c] (FlagEQ)) // result: (SUBQconstborrow x [c]) for { c := v.AuxInt _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SETA_0(v *Value) bool { // match: (SETA (InvertFlags x)) // result: (SETB x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETA (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETAE_0(v *Value) bool { // match: (SETAE (InvertFlags x)) // result: (SETBE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETAE (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETAE (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETAE (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETAE (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETAEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETBEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETAEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETAstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETAstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETB_0(v *Value) bool { // match: (SETB (InvertFlags x)) // result: (SETA x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETB (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETB (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETB (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETB (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETBE_0(v *Value) bool { // match: (SETBE (InvertFlags x)) // result: (SETAE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETBE (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETBEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETBEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETBstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETAstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETBstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ_0(v *Value) bool { b := v.Block // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETEQ (TESTL y (SHLL (MOVLconst [1]) x))) // result: (SETAE (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLL { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLQ { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETEQ (TESTQ y (SHLQ (MOVQconst [1]) x))) // result: (SETAE (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLQ { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (SETAE (BTLconst [log2uint32(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst { break } c := v_0_0.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ x (MOVQconst [c]))) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64MOVQconst { break } c := v_0_1.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPLconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETNE (CMPQconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPQconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ_10(v *Value) bool { b := v.Block // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z2 z1:(SHRQconst [63] x))) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ_20(v *Value) bool { b := v.Block // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTL z2 z1:(SHRLconst [31] x))) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETEQ (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore_0(v *Value) bool { b := v.Block // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLL { break } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTL y (SHLL (MOVLconst [1]) x)) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLL { break } x := v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64MOVLconst || v_1_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLQ { break } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ y (SHLQ (MOVQconst [1]) x)) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLQ { break } x := v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64MOVQconst || v_1_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTLconst [log2uint32(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTLconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64MOVQconst { break } c := v_1_0.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ x (MOVQconst [c])) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64MOVQconst { break } c := v_1_1.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPLconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPQconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore_10(v *Value) bool { b := v.Block // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x))) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTL z2 z1:(SHLLconst [31] (SHRLconst [31] x))) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x))) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x))) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] x)) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] x)) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETEQstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETG_0(v *Value) bool { // match: (SETG (InvertFlags x)) // result: (SETL x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETG (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETGE_0(v *Value) bool { // match: (SETGE (InvertFlags x)) // result: (SETLE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETGE (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETGE (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETGE (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETGE (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETGEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETLEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETGEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETGstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETGstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETL_0(v *Value) bool { // match: (SETL (InvertFlags x)) // result: (SETG x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETL (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETL (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETL (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETL (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETLE_0(v *Value) bool { // match: (SETLE (InvertFlags x)) // result: (SETGE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETLE (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETLEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETGEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETLEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETLstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETGstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETLstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNE_0(v *Value) bool { b := v.Block // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETNE (TESTL y (SHLL (MOVLconst [1]) x))) // result: (SETB (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLL { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLQ { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETNE (TESTQ y (SHLQ (MOVQconst [1]) x))) // result: (SETB (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLQ { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (SETB (BTLconst [log2uint32(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst { break } c := v_0_0.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ x (MOVQconst [c]))) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64MOVQconst { break } c := v_0_1.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPLconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETEQ (CMPQconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPQconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SETNE_10(v *Value) bool { b := v.Block // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ z2 z1:(SHRQconst [63] x))) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SETNE_20(v *Value) bool { b := v.Block // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTL z2 z1:(SHRLconst [31] x))) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (InvertFlags x)) // result: (SETNE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETNE (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore_0(v *Value) bool { b := v.Block // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLL { break } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTL y (SHLL (MOVLconst [1]) x)) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLL { break } x := v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64MOVLconst || v_1_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64SHLQ { break } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ y (SHLQ (MOVQconst [1]) x)) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64SHLQ { break } x := v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64MOVQconst || v_1_1_0.AuxInt != 1 { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTLconst [log2uint32(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTLconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } x := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64MOVQconst { break } c := v_1_0.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ x (MOVQconst [c])) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] x := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64MOVQconst { break } c := v_1_1.AuxInt if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPLconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPQconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore_10(v *Value) bool { b := v.Block // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x))) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTL z2 z1:(SHLLconst [31] (SHRLconst [31] x))) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x))) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x))) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] x)) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } z2 := v_1.Args[1] z1 := v_1.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] x)) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] z2 := v_1.Args[0] z1 := v_1.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETNEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLL_0(v *Value) bool { b := v.Block // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHLL x (MOVLconst [c])) // result: (SHLLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHLL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLLconst_0(v *Value) bool { // match: (SHLLconst [1] (SHRLconst [1] x)) // result: (BTRLconst [0] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = 0 v.AddArg(x) return true } // match: (SHLLconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHLQ_0(v *Value) bool { b := v.Block // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHLQ x (MOVLconst [c])) // result: (SHLQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHLQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLQconst_0(v *Value) bool { // match: (SHLQconst [1] (SHRQconst [1] x)) // result: (BTRQconst [0] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = 0 v.AddArg(x) return true } // match: (SHLQconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRB_0(v *Value) bool { // match: (SHRB x (MOVQconst [c])) // cond: c&31 < 8 // result: (SHRBconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRB _ (MOVQconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SHRBconst_0(v *Value) bool { // match: (SHRBconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRL_0(v *Value) bool { b := v.Block // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRL x (MOVLconst [c])) // result: (SHRLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRLconst_0(v *Value) bool { // match: (SHRLconst [1] (SHLLconst [1] x)) // result: (BTRLconst [31] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = 31 v.AddArg(x) return true } // match: (SHRLconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRQ_0(v *Value) bool { b := v.Block // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHRQ x (MOVLconst [c])) // result: (SHRQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHRQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRQconst_0(v *Value) bool { // match: (SHRQconst [1] (SHLQconst [1] x)) // result: (BTRQconst [63] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = 63 v.AddArg(x) return true } // match: (SHRQconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRW_0(v *Value) bool { // match: (SHRW x (MOVQconst [c])) // cond: c&31 < 16 // result: (SHRWconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRW _ (MOVQconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SHRWconst_0(v *Value) bool { // match: (SHRWconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBL_0(v *Value) bool { b := v.Block // match: (SUBL x (MOVLconst [c])) // result: (SUBLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SUBLconst) v.AuxInt = c v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // result: (NEGL (SUBLconst x [c])) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x x) // result: (MOVLconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBLconst_0(v *Value) bool { // match: (SUBLconst [c] x) // cond: int32(c) == 0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SUBLconst [c] x) // result: (ADDLconst [int64(int32(-c))] x) for { c := v.AuxInt x := v.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int64(int32(-c)) v.AddArg(x) return true } } func rewriteValueAMD64_OpAMD64SUBLload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (SUBL x (MOVLf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSSstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBL) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBLmodify_0(v *Value) bool { // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQ_0(v *Value) bool { b := v.Block // match: (SUBQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconst) v.AuxInt = c v.AddArg(x) return true } // match: (SUBQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (NEGQ (SUBQconst x [c])) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBQ x x) // result: (MOVQconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBQload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQborrow_0(v *Value) bool { // match: (SUBQborrow x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconstborrow x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQconst_0(v *Value) bool { // match: (SUBQconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SUBQconst [c] x) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { c := v.AuxInt x := v.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = -c v.AddArg(x) return true } // match: (SUBQconst (MOVQconst [d]) [c]) // result: (MOVQconst [d-c]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = d - c return true } // match: (SUBQconst (SUBQconst x [d]) [c]) // cond: is32Bit(-c-d) // result: (ADDQconst [-c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SUBQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(-c - d)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = -c - d v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBQload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (SUBQ x (MOVQf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSDstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBQ) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBQmodify_0(v *Value) bool { // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SUBQmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSD_0(v *Value) bool { // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSDload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (SUBSD x (MOVQi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVQstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBSD) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBSS_0(v *Value) bool { // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSSload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (SUBSS x (MOVLi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVLstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBSS) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64TESTB_0(v *Value) bool { b := v.Block // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64TESTBconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTB x (MOVLconst [c])) // result: (TESTBconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64TESTBconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0,off)] ptr mem) for { l2 := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVBload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (TESTB l2 l:(MOVBload {sym} [off] ptr mem)) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] l2 := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVBload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64TESTBconst_0(v *Value) bool { // match: (TESTBconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTB x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTB) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64TESTL_0(v *Value) bool { b := v.Block // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64TESTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTL x (MOVLconst [c])) // result: (TESTLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64TESTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0,off)] ptr mem) for { l2 := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (TESTL l2 l:(MOVLload {sym} [off] ptr mem)) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] l2 := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64TESTLconst_0(v *Value) bool { // match: (TESTLconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTL x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTL) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64TESTQ_0(v *Value) bool { b := v.Block // match: (TESTQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (TESTQconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64TESTQconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (TESTQconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64TESTQconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0,off)] ptr mem) for { l2 := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (TESTQ l2 l:(MOVQload {sym} [off] ptr mem)) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] l2 := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64TESTQconst_0(v *Value) bool { // match: (TESTQconst [-1] x) // cond: x.Op != OpAMD64MOVQconst // result: (TESTQ x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVQconst) { break } v.reset(OpAMD64TESTQ) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64TESTW_0(v *Value) bool { b := v.Block // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64TESTWconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTW x (MOVLconst [c])) // result: (TESTWconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64TESTWconst) v.AuxInt = c v.AddArg(x) return true } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0,off)] ptr mem) for { l2 := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVWload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (TESTW l2 l:(MOVWload {sym} [off] ptr mem)) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] l2 := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVWload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64TESTWconst_0(v *Value) bool { // match: (TESTWconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTW x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTW) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64XADDLlock_0(v *Value) bool { // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XADDLlock [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XADDLlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XADDQlock_0(v *Value) bool { // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XADDQlock [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XADDQlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGL_0(v *Value) bool { // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XCHGL [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XCHGL) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux ptr := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGL) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGQ_0(v *Value) bool { // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XCHGQ [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux ptr := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XORL_0(v *Value) bool { // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLL { break } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { break } v.reset(OpAMD64BTCL) v.AddArg(x) v.AddArg(y) return true } // match: (XORL x (SHLL (MOVLconst [1]) y)) // result: (BTCL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLL { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64MOVLconst || v_1_0.AuxInt != 1 { break } v.reset(OpAMD64BTCL) v.AddArg(x) v.AddArg(y) return true } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCLconst [log2uint32(c)] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (XORL x (MOVLconst [c])) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCLconst [log2uint32(c)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64XORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (MOVLconst [c]) x) // result: (XORLconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64XORLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHRLconst x [d]) (SHLLconst x [c])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { break } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHRWconst x [d]) (SHLLconst x [c])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { break } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64XORL_10(v *Value) bool { // match: (XORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRBconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { break } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL (SHRBconst x [d]) (SHLLconst x [c])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRBconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { break } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORL x x) // result: (MOVLconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64XORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } // match: (XORL l:(MOVLload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64XORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XORLconst_0(v *Value) bool { // match: (XORLconst [c] x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCLconst [log2uint32(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (XORLconst [1] (SETNE x)) // result: (SETEQ x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETNE { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (XORLconst [1] (SETEQ x)) // result: (SETNE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETEQ { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (XORLconst [1] (SETL x)) // result: (SETGE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETL { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (XORLconst [1] (SETGE x)) // result: (SETL x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETGE { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (XORLconst [1] (SETLE x)) // result: (SETG x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETLE { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (XORLconst [1] (SETG x)) // result: (SETLE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETG { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (XORLconst [1] (SETB x)) // result: (SETAE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETB { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (XORLconst [1] (SETAE x)) // result: (SETB x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETAE { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (XORLconst [1] (SETBE x)) // result: (SETA x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETBE { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64XORLconst_10(v *Value) bool { // match: (XORLconst [1] (SETA x)) // result: (SETBE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETA { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (XORLconst [c] (XORLconst [d] x)) // result: (XORLconst [c ^ d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64XORLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORLconst [c] (BTCLconst [d] x)) // result: (XORLconst [c ^ 1<= 128 // result: (BTCQconst [log2(c)] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (XORQ x (MOVQconst [c])) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCQconst [log2(c)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64XORQconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (XORQconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64XORQconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORQ (SHRQconst x [d]) (SHLQconst x [c])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } // match: (XORQ x x) // result: (MOVQconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64XORQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XORQ_10(v *Value) bool { // match: (XORQ l:(MOVQload [off] {sym} ptr mem) x) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64XORQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XORQconst_0(v *Value) bool { // match: (XORQconst [c] x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCQconst [log2(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (XORQconst [c] (XORQconst [d] x)) // result: (XORQconst [c ^ d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64XORQconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64XORQconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORQconst [c] (BTCQconst [d] x)) // result: (XORQconst [c ^ 1< val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore64 ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore8 ptr val mem) // result: (Select1 (XCHGB val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStorePtrNoWB_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (AtomicStorePtrNoWB ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAvg64u_0(v *Value) bool { // match: (Avg64u x y) // result: (AVGQU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64AVGQU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpBitLen16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen16 x) // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) for { x := v.Args[0] v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = 1 v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v2.AddArg(x) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) for { x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) v1.AuxInt = 1 v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v2.AddArg(x) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) for { t := v.Type x := v.Args[0] v.reset(OpAMD64ADDQconst) v.AuxInt = 1 v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) v1 := b.NewValue0(v.Pos, OpSelect0, t) v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v3.AuxInt = -1 v0.AddArg(v3) v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v5 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v5.AddArg(x) v4.AddArg(v5) v0.AddArg(v4) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen8 x) // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) for { x := v.Args[0] v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = 1 v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v2.AddArg(x) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBswap32_0(v *Value) bool { // match: (Bswap32 x) // result: (BSWAPL x) for { x := v.Args[0] v.reset(OpAMD64BSWAPL) v.AddArg(x) return true } } func rewriteValueAMD64_OpBswap64_0(v *Value) bool { // match: (Bswap64 x) // result: (BSWAPQ x) for { x := v.Args[0] v.reset(OpAMD64BSWAPQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCeil_0(v *Value) bool { // match: (Ceil x) // result: (ROUNDSD [2] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 2 v.AddArg(x) return true } } func rewriteValueAMD64_OpClosureCall_0(v *Value) bool { // match: (ClosureCall [argwid] entry closure mem) // result: (CALLclosure [argwid] entry closure mem) for { argwid := v.AuxInt mem := v.Args[2] entry := v.Args[0] closure := v.Args[1] v.reset(OpAMD64CALLclosure) v.AuxInt = argwid v.AddArg(entry) v.AddArg(closure) v.AddArg(mem) return true } } func rewriteValueAMD64_OpCom16_0(v *Value) bool { // match: (Com16 x) // result: (NOTL x) for { x := v.Args[0] v.reset(OpAMD64NOTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCom32_0(v *Value) bool { // match: (Com32 x) // result: (NOTL x) for { x := v.Args[0] v.reset(OpAMD64NOTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCom64_0(v *Value) bool { // match: (Com64 x) // result: (NOTQ x) for { x := v.Args[0] v.reset(OpAMD64NOTQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCom8_0(v *Value) bool { // match: (Com8 x) // result: (NOTL x) for { x := v.Args[0] v.reset(OpAMD64NOTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCondSelect_0(v *Value) bool { // match: (CondSelect x y (SETEQ cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQ y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQ) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETL cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETG cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETA cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQHI y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQHI) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETB cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCC y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCC) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_10(v *Value) bool { // match: (CondSelect x y (SETEQF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGTF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGTF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is32BitInt(t) // result: (CMOVLEQ y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQ) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is32BitInt(t) // result: (CMOVLNE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is32BitInt(t) // result: (CMOVLLT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is32BitInt(t) // result: (CMOVLGT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is32BitInt(t) // result: (CMOVLLE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is32BitInt(t) // result: (CMOVLGE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_20(v *Value) bool { // match: (CondSelect x y (SETA cond)) // cond: is32BitInt(t) // result: (CMOVLHI y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLHI) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is32BitInt(t) // result: (CMOVLCS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is32BitInt(t) // result: (CMOVLCC y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCC) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is32BitInt(t) // result: (CMOVLLS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is32BitInt(t) // result: (CMOVLEQF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is32BitInt(t) // result: (CMOVLNEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is32BitInt(t) // result: (CMOVLGTF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGTF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is32BitInt(t) // result: (CMOVLGEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is16BitInt(t) // result: (CMOVWEQ y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQ) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is16BitInt(t) // result: (CMOVWNE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_30(v *Value) bool { // match: (CondSelect x y (SETL cond)) // cond: is16BitInt(t) // result: (CMOVWLT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is16BitInt(t) // result: (CMOVWGT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is16BitInt(t) // result: (CMOVWLE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is16BitInt(t) // result: (CMOVWGE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is16BitInt(t) // result: (CMOVWHI y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWHI) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is16BitInt(t) // result: (CMOVWCS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is16BitInt(t) // result: (CMOVWCC y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCC) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is16BitInt(t) // result: (CMOVWLS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is16BitInt(t) // result: (CMOVWEQF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is16BitInt(t) // result: (CMOVWNEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_40(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (CondSelect x y (SETGF cond)) // cond: is16BitInt(t) // result: (CMOVWGTF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGTF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is16BitInt(t) // result: (CMOVWGEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 1 // result: (CondSelect x y (MOVBQZX check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 1) { break } v.reset(OpCondSelect) v.Type = t v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64) v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 2 // result: (CondSelect x y (MOVWQZX check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 2) { break } v.reset(OpCondSelect) v.Type = t v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64) v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 4 // result: (CondSelect x y (MOVLQZX check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 4) { break } v.reset(OpCondSelect) v.Type = t v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x (CMPQconst [0] check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { break } v.reset(OpAMD64CMOVQNE) v.AddArg(y) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) // result: (CMOVLNE y x (CMPQconst [0] check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg(y) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) // result: (CMOVWNE y x (CMPQconst [0] check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg(y) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(check) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpConst16_0(v *Value) bool { // match: (Const16 [val]) // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst32_0(v *Value) bool { // match: (Const32 [val]) // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst32F_0(v *Value) bool { // match: (Const32F [val]) // result: (MOVSSconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVSSconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst64_0(v *Value) bool { // match: (Const64 [val]) // result: (MOVQconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst64F_0(v *Value) bool { // match: (Const64F [val]) // result: (MOVSDconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVSDconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst8_0(v *Value) bool { // match: (Const8 [val]) // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConstBool_0(v *Value) bool { // match: (ConstBool [b]) // result: (MOVLconst [b]) for { b := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = b return true } } func rewriteValueAMD64_OpConstNil_0(v *Value) bool { // match: (ConstNil) // result: (MOVQconst [0]) for { v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } } func rewriteValueAMD64_OpCtz16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (BSFL (BTSLconst [16] x)) for { x := v.Args[0] v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = 16 v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz16NonZero_0(v *Value) bool { // match: (Ctz16NonZero x) // result: (BSFL x) for { x := v.Args[0] v.reset(OpAMD64BSFL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCtz32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // result: (Select0 (BSFQ (BTSQconst [32] x))) for { x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) v1.AuxInt = 32 v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz32NonZero_0(v *Value) bool { // match: (Ctz32NonZero x) // result: (BSFL x) for { x := v.Args[0] v.reset(OpAMD64BSFL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCtz64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) for { t := v.Type x := v.Args[0] v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v2.AuxInt = 64 v.AddArg(v2) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v4.AddArg(x) v3.AddArg(v4) v.AddArg(v3) return true } } func rewriteValueAMD64_OpCtz64NonZero_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz64NonZero x) // result: (Select0 (BSFQ x)) for { x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (BSFL (BTSLconst [ 8] x)) for { x := v.Args[0] v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = 8 v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8NonZero_0(v *Value) bool { // match: (Ctz8NonZero x) // result: (BSFL x) for { x := v.Args[0] v.reset(OpAMD64BSFL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32Fto32_0(v *Value) bool { // match: (Cvt32Fto32 x) // result: (CVTTSS2SL x) for { x := v.Args[0] v.reset(OpAMD64CVTTSS2SL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32Fto64_0(v *Value) bool { // match: (Cvt32Fto64 x) // result: (CVTTSS2SQ x) for { x := v.Args[0] v.reset(OpAMD64CVTTSS2SQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32Fto64F_0(v *Value) bool { // match: (Cvt32Fto64F x) // result: (CVTSS2SD x) for { x := v.Args[0] v.reset(OpAMD64CVTSS2SD) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32to32F_0(v *Value) bool { // match: (Cvt32to32F x) // result: (CVTSL2SS x) for { x := v.Args[0] v.reset(OpAMD64CVTSL2SS) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32to64F_0(v *Value) bool { // match: (Cvt32to64F x) // result: (CVTSL2SD x) for { x := v.Args[0] v.reset(OpAMD64CVTSL2SD) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64Fto32_0(v *Value) bool { // match: (Cvt64Fto32 x) // result: (CVTTSD2SL x) for { x := v.Args[0] v.reset(OpAMD64CVTTSD2SL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64Fto32F_0(v *Value) bool { // match: (Cvt64Fto32F x) // result: (CVTSD2SS x) for { x := v.Args[0] v.reset(OpAMD64CVTSD2SS) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64Fto64_0(v *Value) bool { // match: (Cvt64Fto64 x) // result: (CVTTSD2SQ x) for { x := v.Args[0] v.reset(OpAMD64CVTTSD2SQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64to32F_0(v *Value) bool { // match: (Cvt64to32F x) // result: (CVTSQ2SS x) for { x := v.Args[0] v.reset(OpAMD64CVTSQ2SS) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64to64F_0(v *Value) bool { // match: (Cvt64to64F x) // result: (CVTSQ2SD x) for { x := v.Args[0] v.reset(OpAMD64CVTSQ2SD) v.AddArg(x) return true } } func rewriteValueAMD64_OpDiv128u_0(v *Value) bool { // match: (Div128u xhi xlo y) // result: (DIVQU2 xhi xlo y) for { y := v.Args[2] xhi := v.Args[0] xlo := v.Args[1] v.reset(OpAMD64DIVQU2) v.AddArg(xhi) v.AddArg(xlo) v.AddArg(y) return true } } func rewriteValueAMD64_OpDiv16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16 [a] x y) // result: (Select0 (DIVW [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv16u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (Select0 (DIVWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div32 [a] x y) // result: (Select0 (DIVL [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32F_0(v *Value) bool { // match: (Div32F x y) // result: (DIVSS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64DIVSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpDiv32u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div32u x y) // result: (Select0 (DIVLU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div64 [a] x y) // result: (Select0 (DIVQ [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64F_0(v *Value) bool { // match: (Div64F x y) // result: (DIVSD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64DIVSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpDiv64u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div64u x y) // result: (Select0 (DIVQU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq16_0(v *Value) bool { b := v.Block // match: (Eq16 x y) // result: (SETEQ (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32_0(v *Value) bool { b := v.Block // match: (Eq32 x y) // result: (SETEQ (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32F_0(v *Value) bool { b := v.Block // match: (Eq32F x y) // result: (SETEQF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64_0(v *Value) bool { b := v.Block // match: (Eq64 x y) // result: (SETEQ (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64F_0(v *Value) bool { b := v.Block // match: (Eq64F x y) // result: (SETEQF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq8_0(v *Value) bool { b := v.Block // match: (Eq8 x y) // result: (SETEQ (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqB_0(v *Value) bool { b := v.Block // match: (EqB x y) // result: (SETEQ (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqPtr_0(v *Value) bool { b := v.Block // match: (EqPtr x y) // result: (SETEQ (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpFMA_0(v *Value) bool { // match: (FMA x y z) // result: (VFMADD231SD z x y) for { z := v.Args[2] x := v.Args[0] y := v.Args[1] v.reset(OpAMD64VFMADD231SD) v.AddArg(z) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpFloor_0(v *Value) bool { // match: (Floor x) // result: (ROUNDSD [1] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValueAMD64_OpGeq16_0(v *Value) bool { b := v.Block // match: (Geq16 x y) // result: (SETGE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq16U_0(v *Value) bool { b := v.Block // match: (Geq16U x y) // result: (SETAE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq32_0(v *Value) bool { b := v.Block // match: (Geq32 x y) // result: (SETGE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq32F_0(v *Value) bool { b := v.Block // match: (Geq32F x y) // result: (SETGEF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq32U_0(v *Value) bool { b := v.Block // match: (Geq32U x y) // result: (SETAE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq64_0(v *Value) bool { b := v.Block // match: (Geq64 x y) // result: (SETGE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq64F_0(v *Value) bool { b := v.Block // match: (Geq64F x y) // result: (SETGEF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq64U_0(v *Value) bool { b := v.Block // match: (Geq64U x y) // result: (SETAE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq8_0(v *Value) bool { b := v.Block // match: (Geq8 x y) // result: (SETGE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq8U_0(v *Value) bool { b := v.Block // match: (Geq8U x y) // result: (SETAE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGetCallerPC_0(v *Value) bool { // match: (GetCallerPC) // result: (LoweredGetCallerPC) for { v.reset(OpAMD64LoweredGetCallerPC) return true } } func rewriteValueAMD64_OpGetCallerSP_0(v *Value) bool { // match: (GetCallerSP) // result: (LoweredGetCallerSP) for { v.reset(OpAMD64LoweredGetCallerSP) return true } } func rewriteValueAMD64_OpGetClosurePtr_0(v *Value) bool { // match: (GetClosurePtr) // result: (LoweredGetClosurePtr) for { v.reset(OpAMD64LoweredGetClosurePtr) return true } } func rewriteValueAMD64_OpGetG_0(v *Value) bool { // match: (GetG mem) // result: (LoweredGetG mem) for { mem := v.Args[0] v.reset(OpAMD64LoweredGetG) v.AddArg(mem) return true } } func rewriteValueAMD64_OpGreater16_0(v *Value) bool { b := v.Block // match: (Greater16 x y) // result: (SETG (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater16U_0(v *Value) bool { b := v.Block // match: (Greater16U x y) // result: (SETA (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater32_0(v *Value) bool { b := v.Block // match: (Greater32 x y) // result: (SETG (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater32F_0(v *Value) bool { b := v.Block // match: (Greater32F x y) // result: (SETGF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater32U_0(v *Value) bool { b := v.Block // match: (Greater32U x y) // result: (SETA (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater64_0(v *Value) bool { b := v.Block // match: (Greater64 x y) // result: (SETG (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater64F_0(v *Value) bool { b := v.Block // match: (Greater64F x y) // result: (SETGF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater64U_0(v *Value) bool { b := v.Block // match: (Greater64U x y) // result: (SETA (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater8_0(v *Value) bool { b := v.Block // match: (Greater8 x y) // result: (SETG (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater8U_0(v *Value) bool { b := v.Block // match: (Greater8U x y) // result: (SETA (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpHmul32_0(v *Value) bool { // match: (Hmul32 x y) // result: (HMULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpHmul32u_0(v *Value) bool { // match: (Hmul32u x y) // result: (HMULLU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULLU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpHmul64_0(v *Value) bool { // match: (Hmul64 x y) // result: (HMULQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpHmul64u_0(v *Value) bool { // match: (Hmul64u x y) // result: (HMULQU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULQU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpInterCall_0(v *Value) bool { // match: (InterCall [argwid] entry mem) // result: (CALLinter [argwid] entry mem) for { argwid := v.AuxInt mem := v.Args[1] entry := v.Args[0] v.reset(OpAMD64CALLinter) v.AuxInt = argwid v.AddArg(entry) v.AddArg(mem) return true } } func rewriteValueAMD64_OpIsInBounds_0(v *Value) bool { b := v.Block // match: (IsInBounds idx len) // result: (SETB (CMPQ idx len)) for { len := v.Args[1] idx := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsNonNil_0(v *Value) bool { b := v.Block // match: (IsNonNil p) // result: (SETNE (TESTQ p p)) for { p := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) v0.AddArg(p) v0.AddArg(p) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsSliceInBounds_0(v *Value) bool { b := v.Block // match: (IsSliceInBounds idx len) // result: (SETBE (CMPQ idx len)) for { len := v.Args[1] idx := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16_0(v *Value) bool { b := v.Block // match: (Leq16 x y) // result: (SETLE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16U_0(v *Value) bool { b := v.Block // match: (Leq16U x y) // result: (SETBE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32_0(v *Value) bool { b := v.Block // match: (Leq32 x y) // result: (SETLE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32F_0(v *Value) bool { b := v.Block // match: (Leq32F x y) // result: (SETGEF (UCOMISS y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32U_0(v *Value) bool { b := v.Block // match: (Leq32U x y) // result: (SETBE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64_0(v *Value) bool { b := v.Block // match: (Leq64 x y) // result: (SETLE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64F_0(v *Value) bool { b := v.Block // match: (Leq64F x y) // result: (SETGEF (UCOMISD y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64U_0(v *Value) bool { b := v.Block // match: (Leq64U x y) // result: (SETBE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8_0(v *Value) bool { b := v.Block // match: (Leq8 x y) // result: (SETLE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8U_0(v *Value) bool { b := v.Block // match: (Leq8U x y) // result: (SETBE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16_0(v *Value) bool { b := v.Block // match: (Less16 x y) // result: (SETL (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16U_0(v *Value) bool { b := v.Block // match: (Less16U x y) // result: (SETB (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32_0(v *Value) bool { b := v.Block // match: (Less32 x y) // result: (SETL (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32F_0(v *Value) bool { b := v.Block // match: (Less32F x y) // result: (SETGF (UCOMISS y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32U_0(v *Value) bool { b := v.Block // match: (Less32U x y) // result: (SETB (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64_0(v *Value) bool { b := v.Block // match: (Less64 x y) // result: (SETL (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64F_0(v *Value) bool { b := v.Block // match: (Less64F x y) // result: (SETGF (UCOMISD y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64U_0(v *Value) bool { b := v.Block // match: (Less64U x y) // result: (SETB (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8_0(v *Value) bool { b := v.Block // match: (Less8 x y) // result: (SETL (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8U_0(v *Value) bool { b := v.Block // match: (Less8U x y) // result: (SETB (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLoad_0(v *Value) bool { // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVQload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64MOVQload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) // result: (MOVLload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64MOVLload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64MOVWload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(OpAMD64MOVBload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitFloat(t)) { break } v.reset(OpAMD64MOVSSload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is64BitFloat(t)) { break } v.reset(OpAMD64MOVSDload) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpLocalAddr_0(v *Value) bool { // match: (LocalAddr {sym} base _) // result: (LEAQ {sym} base) for { sym := v.Aux _ = v.Args[1] base := v.Args[0] v.reset(OpAMD64LEAQ) v.Aux = sym v.AddArg(base) return true } } func rewriteValueAMD64_OpLsh16x16_0(v *Value) bool { b := v.Block // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh16x32_0(v *Value) bool { b := v.Block // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh16x64_0(v *Value) bool { b := v.Block // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh16x8_0(v *Value) bool { b := v.Block // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x16_0(v *Value) bool { b := v.Block // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x32_0(v *Value) bool { b := v.Block // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x64_0(v *Value) bool { b := v.Block // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x8_0(v *Value) bool { b := v.Block // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x16_0(v *Value) bool { b := v.Block // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x32_0(v *Value) bool { b := v.Block // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x64_0(v *Value) bool { b := v.Block // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x8_0(v *Value) bool { b := v.Block // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x16_0(v *Value) bool { b := v.Block // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x32_0(v *Value) bool { b := v.Block // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x64_0(v *Value) bool { b := v.Block // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x8_0(v *Value) bool { b := v.Block // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpMod16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod16 [a] x y) // result: (Select1 (DIVW [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod16u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Select1 (DIVWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod32 [a] x y) // result: (Select1 (DIVL [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (Select1 (DIVLU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod64 [a] x y) // result: (Select1 (DIVQ [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (Select1 (DIVQU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMove_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if v.AuxInt != 0 { break } mem := v.Args[2] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBload src mem) mem) for { if v.AuxInt != 1 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [2] dst src mem) // result: (MOVWstore dst (MOVWload src mem) mem) for { if v.AuxInt != 2 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVWstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [4] dst src mem) // result: (MOVLstore dst (MOVLload src mem) mem) for { if v.AuxInt != 4 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVLstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [8] dst src mem) // result: (MOVQstore dst (MOVQload src mem) mem) for { if v.AuxInt != 8 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVQstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [16] dst src mem) // cond: config.useSSE // result: (MOVOstore dst (MOVOload src mem) mem) for { if v.AuxInt != 16 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [16] dst src mem) // cond: !config.useSSE // result: (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 16 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [32] dst src mem) // result: (Move [16] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if v.AuxInt != 32 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpMove) v.AuxInt = 16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = 16 v2.AddArg(dst) v2.AddArg(src) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Move [48] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if v.AuxInt != 48 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = 32 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = 16 v2.AddArg(dst) v2.AddArg(src) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Move [64] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [32]) (OffPtr src [32]) (Move [32] dst src mem)) for { if v.AuxInt != 64 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = 32 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = 32 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = 32 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = 32 v2.AddArg(dst) v2.AddArg(src) v2.AddArg(mem) v.AddArg(v2) return true } return false } func rewriteValueAMD64_OpMove_10(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if v.AuxInt != 3 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AuxInt = 2 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = 2 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 5 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [6] dst src mem) // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 6 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVWstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [7] dst src mem) // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 7 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVLstore) v.AuxInt = 3 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = 3 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 9 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [10] dst src mem) // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 10 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVWstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [12] dst src mem) // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 12 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVLstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [s] dst src mem) // cond: s == 11 || s >= 13 && s <= 15 // result: (MOVQstore [s-8] dst (MOVQload [s-8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s == 11 || s >= 13 && s <= 15) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = s - 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = s - 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 <= 8 // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore dst (MOVQload src mem) mem)) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 16 && s%16 != 0 && s%16 <= 8) { break } v.reset(OpMove) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = s % 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = s % 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVOstore dst (MOVOload src mem) mem)) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE) { break } v.reset(OpMove) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = s % 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = s % 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } return false } func rewriteValueAMD64_OpMove_20(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE) { break } v.reset(OpMove) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = s % 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = s % 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AuxInt = 8 v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AuxInt = 8 v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v5.AddArg(src) v5.AddArg(mem) v4.AddArg(v5) v4.AddArg(mem) v2.AddArg(v4) v.AddArg(v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice // result: (DUFFCOPY [14*(64-s/16)] dst src mem) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFCOPY) v.AuxInt = 14 * (64 - s/16) v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } // match: (Move [s] dst src mem) // cond: (s > 16*64 || config.noDuffDevice) && s%8 == 0 // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !((s > 16*64 || config.noDuffDevice) && s%8 == 0) { break } v.reset(OpAMD64REPMOVSQ) v.AddArg(dst) v.AddArg(src) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = s / 8 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpMul16_0(v *Value) bool { // match: (Mul16 x y) // result: (MULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul32_0(v *Value) bool { // match: (Mul32 x y) // result: (MULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul32F_0(v *Value) bool { // match: (Mul32F x y) // result: (MULSS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul64_0(v *Value) bool { // match: (Mul64 x y) // result: (MULQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul64F_0(v *Value) bool { // match: (Mul64F x y) // result: (MULSD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul64uhilo_0(v *Value) bool { // match: (Mul64uhilo x y) // result: (MULQU2 x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULQU2) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul8_0(v *Value) bool { // match: (Mul8 x y) // result: (MULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpNeg16_0(v *Value) bool { // match: (Neg16 x) // result: (NEGL x) for { x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeg32_0(v *Value) bool { // match: (Neg32 x) // result: (NEGL x) for { x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeg32F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Neg32F x) // result: (PXOR x (MOVSSconst [auxFrom32F(float32(math.Copysign(0, -1)))])) for { x := v.Args[0] v.reset(OpAMD64PXOR) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) v0.AuxInt = auxFrom32F(float32(math.Copysign(0, -1))) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeg64_0(v *Value) bool { // match: (Neg64 x) // result: (NEGQ x) for { x := v.Args[0] v.reset(OpAMD64NEGQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeg64F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Neg64F x) // result: (PXOR x (MOVSDconst [auxFrom64F(math.Copysign(0, -1))])) for { x := v.Args[0] v.reset(OpAMD64PXOR) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) v0.AuxInt = auxFrom64F(math.Copysign(0, -1)) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeg8_0(v *Value) bool { // match: (Neg8 x) // result: (NEGL x) for { x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeq16_0(v *Value) bool { b := v.Block // match: (Neq16 x y) // result: (SETNE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32_0(v *Value) bool { b := v.Block // match: (Neq32 x y) // result: (SETNE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32F_0(v *Value) bool { b := v.Block // match: (Neq32F x y) // result: (SETNEF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64_0(v *Value) bool { b := v.Block // match: (Neq64 x y) // result: (SETNE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64F_0(v *Value) bool { b := v.Block // match: (Neq64F x y) // result: (SETNEF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq8_0(v *Value) bool { b := v.Block // match: (Neq8 x y) // result: (SETNE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqB_0(v *Value) bool { b := v.Block // match: (NeqB x y) // result: (SETNE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqPtr_0(v *Value) bool { b := v.Block // match: (NeqPtr x y) // result: (SETNE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNilCheck_0(v *Value) bool { // match: (NilCheck ptr mem) // result: (LoweredNilCheck ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpAMD64LoweredNilCheck) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValueAMD64_OpNot_0(v *Value) bool { // match: (Not x) // result: (XORLconst [1] x) for { x := v.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValueAMD64_OpOffPtr_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // cond: is32Bit(off) // result: (ADDQconst [off] ptr) for { off := v.AuxInt ptr := v.Args[0] if !(is32Bit(off)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = off v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDQ (MOVQconst [off]) ptr) for { off := v.AuxInt ptr := v.Args[0] v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = off v.AddArg(v0) v.AddArg(ptr) return true } } func rewriteValueAMD64_OpOr16_0(v *Value) bool { // match: (Or16 x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOr32_0(v *Value) bool { // match: (Or32 x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOr64_0(v *Value) bool { // match: (Or64 x y) // result: (ORQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOr8_0(v *Value) bool { // match: (Or8 x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOrB_0(v *Value) bool { // match: (OrB x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpPanicBounds_0(v *Value) bool { // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 0) { break } v.reset(OpAMD64LoweredPanicBoundsA) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 1) { break } v.reset(OpAMD64LoweredPanicBoundsB) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 2) { break } v.reset(OpAMD64LoweredPanicBoundsC) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpPopCount16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTL (MOVWQZX x)) for { x := v.Args[0] v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpPopCount32_0(v *Value) bool { // match: (PopCount32 x) // result: (POPCNTL x) for { x := v.Args[0] v.reset(OpAMD64POPCNTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpPopCount64_0(v *Value) bool { // match: (PopCount64 x) // result: (POPCNTQ x) for { x := v.Args[0] v.reset(OpAMD64POPCNTQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpPopCount8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTL (MOVBQZX x)) for { x := v.Args[0] v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpRotateLeft16_0(v *Value) bool { // match: (RotateLeft16 a b) // result: (ROLW a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLW) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRotateLeft32_0(v *Value) bool { // match: (RotateLeft32 a b) // result: (ROLL a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLL) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRotateLeft64_0(v *Value) bool { // match: (RotateLeft64 a b) // result: (ROLQ a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLQ) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRotateLeft8_0(v *Value) bool { // match: (RotateLeft8 a b) // result: (ROLB a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLB) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRound32F_0(v *Value) bool { // match: (Round32F x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpRound64F_0(v *Value) bool { // match: (Round64F x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpRoundToEven_0(v *Value) bool { // match: (RoundToEven x) // result: (ROUNDSD [0] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 0 v.AddArg(x) return true } } func rewriteValueAMD64_OpRsh16Ux16_0(v *Value) bool { b := v.Block // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16Ux32_0(v *Value) bool { b := v.Block // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16Ux64_0(v *Value) bool { b := v.Block // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16Ux8_0(v *Value) bool { b := v.Block // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x16_0(v *Value) bool { b := v.Block // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x32_0(v *Value) bool { b := v.Block // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x64_0(v *Value) bool { b := v.Block // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x8_0(v *Value) bool { b := v.Block // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux16_0(v *Value) bool { b := v.Block // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux32_0(v *Value) bool { b := v.Block // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux64_0(v *Value) bool { b := v.Block // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux8_0(v *Value) bool { b := v.Block // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x16_0(v *Value) bool { b := v.Block // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x32_0(v *Value) bool { b := v.Block // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x64_0(v *Value) bool { b := v.Block // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x8_0(v *Value) bool { b := v.Block // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux16_0(v *Value) bool { b := v.Block // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux32_0(v *Value) bool { b := v.Block // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux64_0(v *Value) bool { b := v.Block // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux8_0(v *Value) bool { b := v.Block // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x16_0(v *Value) bool { b := v.Block // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x32_0(v *Value) bool { b := v.Block // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x64_0(v *Value) bool { b := v.Block // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x8_0(v *Value) bool { b := v.Block // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux16_0(v *Value) bool { b := v.Block // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux32_0(v *Value) bool { b := v.Block // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux64_0(v *Value) bool { b := v.Block // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux8_0(v *Value) bool { b := v.Block // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x16_0(v *Value) bool { b := v.Block // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x32_0(v *Value) bool { b := v.Block // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x64_0(v *Value) bool { b := v.Block // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x8_0(v *Value) bool { b := v.Block // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpSelect0_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uover x y)) // result: (Select0 (MULQU x y)) for { v_0 := v.Args[0] if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (Select0 (Mul32uover x y)) // result: (Select0 (MULLU x y)) for { v_0 := v.Args[0] if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) for { v_0 := v.Args[0] if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y c)) // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) for { v_0 := v.Args[0] if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst32 val tuple)) // result: (ADDL val (Select0 tuple)) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDL) v.AddArg(val) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst64 val tuple)) // result: (ADDQ val (Select0 tuple)) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDQ) v.AddArg(val) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpSelect1_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uover x y)) // result: (SETO (Select1 (MULQU x y))) for { v_0 := v.Args[0] if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul32uover x y)) // result: (SETO (Select1 (MULLU x y))) for { v_0 := v.Args[0] if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Add64carry x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) for { v_0 := v.Args[0] if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v2.AddArg(y) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) for { v_0 := v.Args[0] if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v2.AddArg(y) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (NEGLflags (MOVQconst [0]))) // result: (FlagEQ) for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst || v_0_0.AuxInt != 0 { break } v.reset(OpAMD64FlagEQ) return true } // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) // result: x for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64SBBQcarrymask { break } x := v_0_0_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Select1 (AddTupleFirst32 _ tuple)) // result: (Select1 tuple) for { v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } // match: (Select1 (AddTupleFirst64 _ tuple)) // result: (Select1 tuple) for { v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } return false } func rewriteValueAMD64_OpSignExt16to32_0(v *Value) bool { // match: (SignExt16to32 x) // result: (MOVWQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt16to64_0(v *Value) bool { // match: (SignExt16to64 x) // result: (MOVWQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt32to64_0(v *Value) bool { // match: (SignExt32to64 x) // result: (MOVLQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt8to16_0(v *Value) bool { // match: (SignExt8to16 x) // result: (MOVBQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt8to32_0(v *Value) bool { // match: (SignExt8to32 x) // result: (MOVBQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt8to64_0(v *Value) bool { // match: (SignExt8to64 x) // result: (MOVBQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSlicemask_0(v *Value) bool { b := v.Block // match: (Slicemask x) // result: (SARQconst (NEGQ x) [63]) for { t := v.Type x := v.Args[0] v.reset(OpAMD64SARQconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpSqrt_0(v *Value) bool { // match: (Sqrt x) // result: (SQRTSD x) for { x := v.Args[0] v.reset(OpAMD64SQRTSD) v.AddArg(x) return true } } func rewriteValueAMD64_OpStaticCall_0(v *Value) bool { // match: (StaticCall [argwid] {target} mem) // result: (CALLstatic [argwid] {target} mem) for { argwid := v.AuxInt target := v.Aux mem := v.Args[0] v.reset(OpAMD64CALLstatic) v.AuxInt = argwid v.Aux = target v.AddArg(mem) return true } } func rewriteValueAMD64_OpStore_0(v *Value) bool { // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) // result: (MOVSDstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) // result: (MOVSSstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSSstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 // result: (MOVQstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8) { break } v.reset(OpAMD64MOVQstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 // result: (MOVLstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 4) { break } v.reset(OpAMD64MOVLstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 2 // result: (MOVWstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 2) { break } v.reset(OpAMD64MOVWstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 1 // result: (MOVBstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 1) { break } v.reset(OpAMD64MOVBstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpSub16_0(v *Value) bool { // match: (Sub16 x y) // result: (SUBL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub32_0(v *Value) bool { // match: (Sub32 x y) // result: (SUBL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub32F_0(v *Value) bool { // match: (Sub32F x y) // result: (SUBSS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub64_0(v *Value) bool { // match: (Sub64 x y) // result: (SUBQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub64F_0(v *Value) bool { // match: (Sub64F x y) // result: (SUBSD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub8_0(v *Value) bool { // match: (Sub8 x y) // result: (SUBL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSubPtr_0(v *Value) bool { // match: (SubPtr x y) // result: (SUBQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpTrunc_0(v *Value) bool { // match: (Trunc x) // result: (ROUNDSD [3] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 3 v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc16to8_0(v *Value) bool { // match: (Trunc16to8 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc32to16_0(v *Value) bool { // match: (Trunc32to16 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc32to8_0(v *Value) bool { // match: (Trunc32to8 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc64to16_0(v *Value) bool { // match: (Trunc64to16 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc64to32_0(v *Value) bool { // match: (Trunc64to32 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc64to8_0(v *Value) bool { // match: (Trunc64to8 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpWB_0(v *Value) bool { // match: (WB {fn} destptr srcptr mem) // result: (LoweredWB {fn} destptr srcptr mem) for { fn := v.Aux mem := v.Args[2] destptr := v.Args[0] srcptr := v.Args[1] v.reset(OpAMD64LoweredWB) v.Aux = fn v.AddArg(destptr) v.AddArg(srcptr) v.AddArg(mem) return true } } func rewriteValueAMD64_OpXor16_0(v *Value) bool { // match: (Xor16 x y) // result: (XORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpXor32_0(v *Value) bool { // match: (Xor32 x y) // result: (XORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpXor64_0(v *Value) bool { // match: (Xor64 x y) // result: (XORQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpXor8_0(v *Value) bool { // match: (Xor8 x y) // result: (XORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpZero_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (Zero [0] _ mem) // result: mem for { if v.AuxInt != 0 { break } mem := v.Args[1] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstoreconst [0] destptr mem) for { if v.AuxInt != 1 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVBstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [2] destptr mem) // result: (MOVWstoreconst [0] destptr mem) for { if v.AuxInt != 2 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVWstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [4] destptr mem) // result: (MOVLstoreconst [0] destptr mem) for { if v.AuxInt != 4 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVLstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [8] destptr mem) // result: (MOVQstoreconst [0] destptr mem) for { if v.AuxInt != 8 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVQstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [0] destptr mem)) for { if v.AuxInt != 3 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(0, 2) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [5] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 5 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [6] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 6 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [7] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 7 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(0, 3) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s%8 != 0 && s > 8 && !config.useSSE // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVQstoreconst [0] destptr mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s%8 != 0 && s > 8 && !config.useSSE) { break } v.reset(OpZero) v.AuxInt = s - s%8 v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = s % 8 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v.AddArg(v1) return true } return false } func rewriteValueAMD64_OpZero_10(v *Value) bool { b := v.Block config := b.Func.Config // match: (Zero [16] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem)) for { if v.AuxInt != 16 { break } mem := v.Args[1] destptr := v.Args[0] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, 8) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [24] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem))) for { if v.AuxInt != 24 { break } mem := v.Args[1] destptr := v.Args[0] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, 16) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = makeValAndOff(0, 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [32] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem)))) for { if v.AuxInt != 32 { break } mem := v.Args[1] destptr := v.Args[0] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, 24) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = makeValAndOff(0, 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = makeValAndOff(0, 8) v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v2.AuxInt = 0 v2.AddArg(destptr) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s > 8 && s < 16 && config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,s-8)] destptr (MOVQstoreconst [0] destptr mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s > 8 && s < 16 && config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, s-8) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstore destptr (MOVOconst [0]) mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = s % 16 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v2.AuxInt = 0 v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVQstoreconst [0] destptr mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = s % 16 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Zero [16] destptr mem) // cond: config.useSSE // result: (MOVOstore destptr (MOVOconst [0]) mem) for { if v.AuxInt != 16 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (Zero [32] destptr mem) // cond: config.useSSE // result: (MOVOstore (OffPtr destptr [16]) (MOVOconst [0]) (MOVOstore destptr (MOVOconst [0]) mem)) for { if v.AuxInt != 32 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = 16 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v2.AddArg(destptr) v3 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v3.AuxInt = 0 v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Zero [48] destptr mem) // cond: config.useSSE // result: (MOVOstore (OffPtr destptr [32]) (MOVOconst [0]) (MOVOstore (OffPtr destptr [16]) (MOVOconst [0]) (MOVOstore destptr (MOVOconst [0]) mem))) for { if v.AuxInt != 48 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = 32 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v3.AuxInt = 16 v3.AddArg(destptr) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v4.AuxInt = 0 v2.AddArg(v4) v5 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v5.AddArg(destptr) v6 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v6.AuxInt = 0 v5.AddArg(v6) v5.AddArg(mem) v2.AddArg(v5) v.AddArg(v2) return true } // match: (Zero [64] destptr mem) // cond: config.useSSE // result: (MOVOstore (OffPtr destptr [48]) (MOVOconst [0]) (MOVOstore (OffPtr destptr [32]) (MOVOconst [0]) (MOVOstore (OffPtr destptr [16]) (MOVOconst [0]) (MOVOstore destptr (MOVOconst [0]) mem)))) for { if v.AuxInt != 64 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = 48 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v3.AuxInt = 32 v3.AddArg(destptr) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v4.AuxInt = 0 v2.AddArg(v4) v5 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v6 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v6.AuxInt = 16 v6.AddArg(destptr) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v7.AuxInt = 0 v5.AddArg(v7) v8 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v8.AddArg(destptr) v9 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v9.AuxInt = 0 v8.AddArg(v9) v8.AddArg(mem) v5.AddArg(v8) v2.AddArg(v5) v.AddArg(v2) return true } return false } func rewriteValueAMD64_OpZero_20(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [s] destptr mem) // cond: s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice // result: (DUFFZERO [s] destptr (MOVOconst [0]) mem) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFZERO) v.AuxInt = s v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0 // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !((s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0) { break } v.reset(OpAMD64REPSTOSQ) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = s / 8 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = 0 v.AddArg(v1) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpZeroExt16to32_0(v *Value) bool { // match: (ZeroExt16to32 x) // result: (MOVWQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt16to64_0(v *Value) bool { // match: (ZeroExt16to64 x) // result: (MOVWQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt32to64_0(v *Value) bool { // match: (ZeroExt32to64 x) // result: (MOVLQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt8to16_0(v *Value) bool { // match: (ZeroExt8to16 x) // result: (MOVBQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt8to32_0(v *Value) bool { // match: (ZeroExt8to32 x) // result: (MOVBQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt8to64_0(v *Value) bool { // match: (ZeroExt8to64 x) // result: (MOVBQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } } func rewriteBlockAMD64(b *Block) bool { switch b.Kind { case BlockAMD64EQ: // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (EQ (TESTL y (SHLL (MOVLconst [1]) x))) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLL { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLQ { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (EQ (TESTQ y (SHLQ (MOVQconst [1]) x))) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLQ { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (UGE (BTLconst [log2uint32(c)] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst { break } c := v_0_0.AuxInt if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ x (MOVQconst [c]))) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64MOVQconst { break } c := v_0_1.AuxInt if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ z2 z1:(SHRQconst [63] x))) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTL z2 z1:(SHRLconst [31] x))) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64EQ) b.AddControl(cmp) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64GE: // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LE) b.AddControl(cmp) return true } // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64GT: // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LT) b.AddControl(cmp) return true } // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockIf: // match: (If (SETL cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64SETL { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LT) b.AddControl(cmp) return true } // match: (If (SETLE cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64SETLE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LE) b.AddControl(cmp) return true } // match: (If (SETG cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64SETG { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GT) b.AddControl(cmp) return true } // match: (If (SETGE cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64SETGE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GE) b.AddControl(cmp) return true } // match: (If (SETEQ cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64SETEQ { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64EQ) b.AddControl(cmp) return true } // match: (If (SETNE cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64SETNE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64NE) b.AddControl(cmp) return true } // match: (If (SETB cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64SETB { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULT) b.AddControl(cmp) return true } // match: (If (SETBE cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64SETBE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULE) b.AddControl(cmp) return true } // match: (If (SETA cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETA { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (If (SETAE cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETAE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (If (SETO cmp) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64SETO { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64OS) b.AddControl(cmp) return true } // match: (If (SETGF cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETGF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (If (SETGEF cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETGEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (If (SETEQF cmp) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64SETEQF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64EQF) b.AddControl(cmp) return true } // match: (If (SETNEF cmp) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64SETNEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64NEF) b.AddControl(cmp) return true } // match: (If cond yes no) // result: (NE (TESTB cond cond) yes no) for { cond := b.Controls[0] b.Reset(BlockAMD64NE) v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) v0.AddArg(cond) v0.AddArg(cond) b.AddControl(v0) return true } case BlockAMD64LE: // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GE) b.AddControl(cmp) return true } // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64LT: // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GT) b.AddControl(cmp) return true } // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETL { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64LT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETLE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64LE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETG { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64GT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64GE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQ { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64EQ) b.AddControl(cmp) return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64NE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETB { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64ULT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETBE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64ULE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETA { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETAE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETO { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64OS) b.AddControl(cmp) return true } // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (NE (TESTL y (SHLL (MOVLconst [1]) x))) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLL { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLQ { break } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (NE (TESTQ y (SHLQ (MOVQconst [1]) x))) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] y := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SHLQ { break } x := v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (ULT (BTLconst [log2uint32(c)] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst { break } c := v_0_0.AuxInt if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ x (MOVQconst [c]))) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64MOVQconst { break } c := v_0_1.AuxInt if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { break } x := z1_0.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ z2 z1:(SHRQconst [63] x))) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] z2 := v_0.Args[1] z1 := v_0.Args[0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTL z2 z1:(SHRLconst [31] x))) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] z2 := v_0.Args[0] z1 := v_0.Args[1] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { break } x := z1.Args[0] if !(z1 == z2) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64EQF) b.AddControl(cmp) return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64NEF) b.AddControl(cmp) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64NE) b.AddControl(cmp) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGE: // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULE) b.AddControl(cmp) return true } // match: (UGE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (UGE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGT: // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULT) b.AddControl(cmp) return true } // match: (UGT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64ULE: // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (ULE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64ULT: // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (ULT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- y -- // Code generated from gen/AMD64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/compile/internal/types" func rewriteValueAMD64(v *Value) bool { switch v.Op { case OpAMD64ADCQ: return rewriteValueAMD64_OpAMD64ADCQ_0(v) case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst_0(v) case OpAMD64ADDL: return rewriteValueAMD64_OpAMD64ADDL_0(v) || rewriteValueAMD64_OpAMD64ADDL_10(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst_0(v) || rewriteValueAMD64_OpAMD64ADDLconst_10(v) case OpAMD64ADDLconstmodify: return rewriteValueAMD64_OpAMD64ADDLconstmodify_0(v) case OpAMD64ADDLload: return rewriteValueAMD64_OpAMD64ADDLload_0(v) case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify_0(v) case OpAMD64ADDQ: return rewriteValueAMD64_OpAMD64ADDQ_0(v) || rewriteValueAMD64_OpAMD64ADDQ_10(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry_0(v) case OpAMD64ADDQconst: return rewriteValueAMD64_OpAMD64ADDQconst_0(v) || rewriteValueAMD64_OpAMD64ADDQconst_10(v) case OpAMD64ADDQconstmodify: return rewriteValueAMD64_OpAMD64ADDQconstmodify_0(v) case OpAMD64ADDQload: return rewriteValueAMD64_OpAMD64ADDQload_0(v) case OpAMD64ADDQmodify: return rewriteValueAMD64_OpAMD64ADDQmodify_0(v) case OpAMD64ADDSD: return rewriteValueAMD64_OpAMD64ADDSD_0(v) case OpAMD64ADDSDload: return rewriteValueAMD64_OpAMD64ADDSDload_0(v) case OpAMD64ADDSS: return rewriteValueAMD64_OpAMD64ADDSS_0(v) case OpAMD64ADDSSload: return rewriteValueAMD64_OpAMD64ADDSSload_0(v) case OpAMD64ANDL: return rewriteValueAMD64_OpAMD64ANDL_0(v) case OpAMD64ANDLconst: return rewriteValueAMD64_OpAMD64ANDLconst_0(v) case OpAMD64ANDLconstmodify: return rewriteValueAMD64_OpAMD64ANDLconstmodify_0(v) case OpAMD64ANDLload: return rewriteValueAMD64_OpAMD64ANDLload_0(v) case OpAMD64ANDLmodify: return rewriteValueAMD64_OpAMD64ANDLmodify_0(v) case OpAMD64ANDQ: return rewriteValueAMD64_OpAMD64ANDQ_0(v) case OpAMD64ANDQconst: return rewriteValueAMD64_OpAMD64ANDQconst_0(v) case OpAMD64ANDQconstmodify: return rewriteValueAMD64_OpAMD64ANDQconstmodify_0(v) case OpAMD64ANDQload: return rewriteValueAMD64_OpAMD64ANDQload_0(v) case OpAMD64ANDQmodify: return rewriteValueAMD64_OpAMD64ANDQmodify_0(v) case OpAMD64BSFQ: return rewriteValueAMD64_OpAMD64BSFQ_0(v) case OpAMD64BTCLconst: return rewriteValueAMD64_OpAMD64BTCLconst_0(v) case OpAMD64BTCLconstmodify: return rewriteValueAMD64_OpAMD64BTCLconstmodify_0(v) case OpAMD64BTCLmodify: return rewriteValueAMD64_OpAMD64BTCLmodify_0(v) case OpAMD64BTCQconst: return rewriteValueAMD64_OpAMD64BTCQconst_0(v) case OpAMD64BTCQconstmodify: return rewriteValueAMD64_OpAMD64BTCQconstmodify_0(v) case OpAMD64BTCQmodify: return rewriteValueAMD64_OpAMD64BTCQmodify_0(v) case OpAMD64BTLconst: return rewriteValueAMD64_OpAMD64BTLconst_0(v) case OpAMD64BTQconst: return rewriteValueAMD64_OpAMD64BTQconst_0(v) case OpAMD64BTRLconst: return rewriteValueAMD64_OpAMD64BTRLconst_0(v) case OpAMD64BTRLconstmodify: return rewriteValueAMD64_OpAMD64BTRLconstmodify_0(v) case OpAMD64BTRLmodify: return rewriteValueAMD64_OpAMD64BTRLmodify_0(v) case OpAMD64BTRQconst: return rewriteValueAMD64_OpAMD64BTRQconst_0(v) case OpAMD64BTRQconstmodify: return rewriteValueAMD64_OpAMD64BTRQconstmodify_0(v) case OpAMD64BTRQmodify: return rewriteValueAMD64_OpAMD64BTRQmodify_0(v) case OpAMD64BTSLconst: return rewriteValueAMD64_OpAMD64BTSLconst_0(v) case OpAMD64BTSLconstmodify: return rewriteValueAMD64_OpAMD64BTSLconstmodify_0(v) case OpAMD64BTSLmodify: return rewriteValueAMD64_OpAMD64BTSLmodify_0(v) case OpAMD64BTSQconst: return rewriteValueAMD64_OpAMD64BTSQconst_0(v) case OpAMD64BTSQconstmodify: return rewriteValueAMD64_OpAMD64BTSQconstmodify_0(v) case OpAMD64BTSQmodify: return rewriteValueAMD64_OpAMD64BTSQmodify_0(v) case OpAMD64CMOVLCC: return rewriteValueAMD64_OpAMD64CMOVLCC_0(v) case OpAMD64CMOVLCS: return rewriteValueAMD64_OpAMD64CMOVLCS_0(v) case OpAMD64CMOVLEQ: return rewriteValueAMD64_OpAMD64CMOVLEQ_0(v) case OpAMD64CMOVLGE: return rewriteValueAMD64_OpAMD64CMOVLGE_0(v) case OpAMD64CMOVLGT: return rewriteValueAMD64_OpAMD64CMOVLGT_0(v) case OpAMD64CMOVLHI: return rewriteValueAMD64_OpAMD64CMOVLHI_0(v) case OpAMD64CMOVLLE: return rewriteValueAMD64_OpAMD64CMOVLLE_0(v) case OpAMD64CMOVLLS: return rewriteValueAMD64_OpAMD64CMOVLLS_0(v) case OpAMD64CMOVLLT: return rewriteValueAMD64_OpAMD64CMOVLLT_0(v) case OpAMD64CMOVLNE: return rewriteValueAMD64_OpAMD64CMOVLNE_0(v) case OpAMD64CMOVQCC: return rewriteValueAMD64_OpAMD64CMOVQCC_0(v) case OpAMD64CMOVQCS: return rewriteValueAMD64_OpAMD64CMOVQCS_0(v) case OpAMD64CMOVQEQ: return rewriteValueAMD64_OpAMD64CMOVQEQ_0(v) case OpAMD64CMOVQGE: return rewriteValueAMD64_OpAMD64CMOVQGE_0(v) case OpAMD64CMOVQGT: return rewriteValueAMD64_OpAMD64CMOVQGT_0(v) case OpAMD64CMOVQHI: return rewriteValueAMD64_OpAMD64CMOVQHI_0(v) case OpAMD64CMOVQLE: return rewriteValueAMD64_OpAMD64CMOVQLE_0(v) case OpAMD64CMOVQLS: return rewriteValueAMD64_OpAMD64CMOVQLS_0(v) case OpAMD64CMOVQLT: return rewriteValueAMD64_OpAMD64CMOVQLT_0(v) case OpAMD64CMOVQNE: return rewriteValueAMD64_OpAMD64CMOVQNE_0(v) case OpAMD64CMOVWCC: return rewriteValueAMD64_OpAMD64CMOVWCC_0(v) case OpAMD64CMOVWCS: return rewriteValueAMD64_OpAMD64CMOVWCS_0(v) case OpAMD64CMOVWEQ: return rewriteValueAMD64_OpAMD64CMOVWEQ_0(v) case OpAMD64CMOVWGE: return rewriteValueAMD64_OpAMD64CMOVWGE_0(v) case OpAMD64CMOVWGT: return rewriteValueAMD64_OpAMD64CMOVWGT_0(v) case OpAMD64CMOVWHI: return rewriteValueAMD64_OpAMD64CMOVWHI_0(v) case OpAMD64CMOVWLE: return rewriteValueAMD64_OpAMD64CMOVWLE_0(v) case OpAMD64CMOVWLS: return rewriteValueAMD64_OpAMD64CMOVWLS_0(v) case OpAMD64CMOVWLT: return rewriteValueAMD64_OpAMD64CMOVWLT_0(v) case OpAMD64CMOVWNE: return rewriteValueAMD64_OpAMD64CMOVWNE_0(v) case OpAMD64CMPB: return rewriteValueAMD64_OpAMD64CMPB_0(v) case OpAMD64CMPBconst: return rewriteValueAMD64_OpAMD64CMPBconst_0(v) case OpAMD64CMPBconstload: return rewriteValueAMD64_OpAMD64CMPBconstload_0(v) case OpAMD64CMPBload: return rewriteValueAMD64_OpAMD64CMPBload_0(v) case OpAMD64CMPL: return rewriteValueAMD64_OpAMD64CMPL_0(v) case OpAMD64CMPLconst: return rewriteValueAMD64_OpAMD64CMPLconst_0(v) || rewriteValueAMD64_OpAMD64CMPLconst_10(v) case OpAMD64CMPLconstload: return rewriteValueAMD64_OpAMD64CMPLconstload_0(v) case OpAMD64CMPLload: return rewriteValueAMD64_OpAMD64CMPLload_0(v) case OpAMD64CMPQ: return rewriteValueAMD64_OpAMD64CMPQ_0(v) case OpAMD64CMPQconst: return rewriteValueAMD64_OpAMD64CMPQconst_0(v) || rewriteValueAMD64_OpAMD64CMPQconst_10(v) case OpAMD64CMPQconstload: return rewriteValueAMD64_OpAMD64CMPQconstload_0(v) case OpAMD64CMPQload: return rewriteValueAMD64_OpAMD64CMPQload_0(v) case OpAMD64CMPW: return rewriteValueAMD64_OpAMD64CMPW_0(v) case OpAMD64CMPWconst: return rewriteValueAMD64_OpAMD64CMPWconst_0(v) case OpAMD64CMPWconstload: return rewriteValueAMD64_OpAMD64CMPWconstload_0(v) case OpAMD64CMPWload: return rewriteValueAMD64_OpAMD64CMPWload_0(v) case OpAMD64CMPXCHGLlock: return rewriteValueAMD64_OpAMD64CMPXCHGLlock_0(v) case OpAMD64CMPXCHGQlock: return rewriteValueAMD64_OpAMD64CMPXCHGQlock_0(v) case OpAMD64DIVSD: return rewriteValueAMD64_OpAMD64DIVSD_0(v) case OpAMD64DIVSDload: return rewriteValueAMD64_OpAMD64DIVSDload_0(v) case OpAMD64DIVSS: return rewriteValueAMD64_OpAMD64DIVSS_0(v) case OpAMD64DIVSSload: return rewriteValueAMD64_OpAMD64DIVSSload_0(v) case OpAMD64HMULL: return rewriteValueAMD64_OpAMD64HMULL_0(v) case OpAMD64HMULLU: return rewriteValueAMD64_OpAMD64HMULLU_0(v) case OpAMD64HMULQ: return rewriteValueAMD64_OpAMD64HMULQ_0(v) case OpAMD64HMULQU: return rewriteValueAMD64_OpAMD64HMULQU_0(v) case OpAMD64LEAL: return rewriteValueAMD64_OpAMD64LEAL_0(v) case OpAMD64LEAL1: return rewriteValueAMD64_OpAMD64LEAL1_0(v) case OpAMD64LEAL2: return rewriteValueAMD64_OpAMD64LEAL2_0(v) case OpAMD64LEAL4: return rewriteValueAMD64_OpAMD64LEAL4_0(v) case OpAMD64LEAL8: return rewriteValueAMD64_OpAMD64LEAL8_0(v) case OpAMD64LEAQ: return rewriteValueAMD64_OpAMD64LEAQ_0(v) case OpAMD64LEAQ1: return rewriteValueAMD64_OpAMD64LEAQ1_0(v) case OpAMD64LEAQ2: return rewriteValueAMD64_OpAMD64LEAQ2_0(v) case OpAMD64LEAQ4: return rewriteValueAMD64_OpAMD64LEAQ4_0(v) case OpAMD64LEAQ8: return rewriteValueAMD64_OpAMD64LEAQ8_0(v) case OpAMD64MOVBQSX: return rewriteValueAMD64_OpAMD64MOVBQSX_0(v) case OpAMD64MOVBQSXload: return rewriteValueAMD64_OpAMD64MOVBQSXload_0(v) case OpAMD64MOVBQZX: return rewriteValueAMD64_OpAMD64MOVBQZX_0(v) case OpAMD64MOVBatomicload: return rewriteValueAMD64_OpAMD64MOVBatomicload_0(v) case OpAMD64MOVBload: return rewriteValueAMD64_OpAMD64MOVBload_0(v) case OpAMD64MOVBloadidx1: return rewriteValueAMD64_OpAMD64MOVBloadidx1_0(v) case OpAMD64MOVBstore: return rewriteValueAMD64_OpAMD64MOVBstore_0(v) || rewriteValueAMD64_OpAMD64MOVBstore_10(v) || rewriteValueAMD64_OpAMD64MOVBstore_20(v) || rewriteValueAMD64_OpAMD64MOVBstore_30(v) case OpAMD64MOVBstoreconst: return rewriteValueAMD64_OpAMD64MOVBstoreconst_0(v) case OpAMD64MOVBstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVBstoreconstidx1_0(v) case OpAMD64MOVBstoreidx1: return rewriteValueAMD64_OpAMD64MOVBstoreidx1_0(v) || rewriteValueAMD64_OpAMD64MOVBstoreidx1_10(v) case OpAMD64MOVLQSX: return rewriteValueAMD64_OpAMD64MOVLQSX_0(v) case OpAMD64MOVLQSXload: return rewriteValueAMD64_OpAMD64MOVLQSXload_0(v) case OpAMD64MOVLQZX: return rewriteValueAMD64_OpAMD64MOVLQZX_0(v) case OpAMD64MOVLatomicload: return rewriteValueAMD64_OpAMD64MOVLatomicload_0(v) case OpAMD64MOVLf2i: return rewriteValueAMD64_OpAMD64MOVLf2i_0(v) case OpAMD64MOVLi2f: return rewriteValueAMD64_OpAMD64MOVLi2f_0(v) case OpAMD64MOVLload: return rewriteValueAMD64_OpAMD64MOVLload_0(v) || rewriteValueAMD64_OpAMD64MOVLload_10(v) case OpAMD64MOVLloadidx1: return rewriteValueAMD64_OpAMD64MOVLloadidx1_0(v) case OpAMD64MOVLloadidx4: return rewriteValueAMD64_OpAMD64MOVLloadidx4_0(v) case OpAMD64MOVLloadidx8: return rewriteValueAMD64_OpAMD64MOVLloadidx8_0(v) case OpAMD64MOVLstore: return rewriteValueAMD64_OpAMD64MOVLstore_0(v) || rewriteValueAMD64_OpAMD64MOVLstore_10(v) || rewriteValueAMD64_OpAMD64MOVLstore_20(v) || rewriteValueAMD64_OpAMD64MOVLstore_30(v) case OpAMD64MOVLstoreconst: return rewriteValueAMD64_OpAMD64MOVLstoreconst_0(v) case OpAMD64MOVLstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVLstoreconstidx1_0(v) case OpAMD64MOVLstoreconstidx4: return rewriteValueAMD64_OpAMD64MOVLstoreconstidx4_0(v) case OpAMD64MOVLstoreidx1: return rewriteValueAMD64_OpAMD64MOVLstoreidx1_0(v) case OpAMD64MOVLstoreidx4: return rewriteValueAMD64_OpAMD64MOVLstoreidx4_0(v) case OpAMD64MOVLstoreidx8: return rewriteValueAMD64_OpAMD64MOVLstoreidx8_0(v) case OpAMD64MOVOload: return rewriteValueAMD64_OpAMD64MOVOload_0(v) case OpAMD64MOVOstore: return rewriteValueAMD64_OpAMD64MOVOstore_0(v) case OpAMD64MOVQatomicload: return rewriteValueAMD64_OpAMD64MOVQatomicload_0(v) case OpAMD64MOVQf2i: return rewriteValueAMD64_OpAMD64MOVQf2i_0(v) case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f_0(v) case OpAMD64MOVQload: return rewriteValueAMD64_OpAMD64MOVQload_0(v) case OpAMD64MOVQloadidx1: return rewriteValueAMD64_OpAMD64MOVQloadidx1_0(v) case OpAMD64MOVQloadidx8: return rewriteValueAMD64_OpAMD64MOVQloadidx8_0(v) case OpAMD64MOVQstore: return rewriteValueAMD64_OpAMD64MOVQstore_0(v) || rewriteValueAMD64_OpAMD64MOVQstore_10(v) || rewriteValueAMD64_OpAMD64MOVQstore_20(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst_0(v) case OpAMD64MOVQstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVQstoreconstidx1_0(v) case OpAMD64MOVQstoreconstidx8: return rewriteValueAMD64_OpAMD64MOVQstoreconstidx8_0(v) case OpAMD64MOVQstoreidx1: return rewriteValueAMD64_OpAMD64MOVQstoreidx1_0(v) case OpAMD64MOVQstoreidx8: return rewriteValueAMD64_OpAMD64MOVQstoreidx8_0(v) case OpAMD64MOVSDload: return rewriteValueAMD64_OpAMD64MOVSDload_0(v) case OpAMD64MOVSDloadidx1: return rewriteValueAMD64_OpAMD64MOVSDloadidx1_0(v) case OpAMD64MOVSDloadidx8: return rewriteValueAMD64_OpAMD64MOVSDloadidx8_0(v) case OpAMD64MOVSDstore: return rewriteValueAMD64_OpAMD64MOVSDstore_0(v) case OpAMD64MOVSDstoreidx1: return rewriteValueAMD64_OpAMD64MOVSDstoreidx1_0(v) case OpAMD64MOVSDstoreidx8: return rewriteValueAMD64_OpAMD64MOVSDstoreidx8_0(v) case OpAMD64MOVSSload: return rewriteValueAMD64_OpAMD64MOVSSload_0(v) case OpAMD64MOVSSloadidx1: return rewriteValueAMD64_OpAMD64MOVSSloadidx1_0(v) case OpAMD64MOVSSloadidx4: return rewriteValueAMD64_OpAMD64MOVSSloadidx4_0(v) case OpAMD64MOVSSstore: return rewriteValueAMD64_OpAMD64MOVSSstore_0(v) case OpAMD64MOVSSstoreidx1: return rewriteValueAMD64_OpAMD64MOVSSstoreidx1_0(v) case OpAMD64MOVSSstoreidx4: return rewriteValueAMD64_OpAMD64MOVSSstoreidx4_0(v) case OpAMD64MOVWQSX: return rewriteValueAMD64_OpAMD64MOVWQSX_0(v) case OpAMD64MOVWQSXload: return rewriteValueAMD64_OpAMD64MOVWQSXload_0(v) case OpAMD64MOVWQZX: return rewriteValueAMD64_OpAMD64MOVWQZX_0(v) case OpAMD64MOVWload: return rewriteValueAMD64_OpAMD64MOVWload_0(v) case OpAMD64MOVWloadidx1: return rewriteValueAMD64_OpAMD64MOVWloadidx1_0(v) case OpAMD64MOVWloadidx2: return rewriteValueAMD64_OpAMD64MOVWloadidx2_0(v) case OpAMD64MOVWstore: return rewriteValueAMD64_OpAMD64MOVWstore_0(v) || rewriteValueAMD64_OpAMD64MOVWstore_10(v) case OpAMD64MOVWstoreconst: return rewriteValueAMD64_OpAMD64MOVWstoreconst_0(v) case OpAMD64MOVWstoreconstidx1: return rewriteValueAMD64_OpAMD64MOVWstoreconstidx1_0(v) case OpAMD64MOVWstoreconstidx2: return rewriteValueAMD64_OpAMD64MOVWstoreconstidx2_0(v) case OpAMD64MOVWstoreidx1: return rewriteValueAMD64_OpAMD64MOVWstoreidx1_0(v) case OpAMD64MOVWstoreidx2: return rewriteValueAMD64_OpAMD64MOVWstoreidx2_0(v) case OpAMD64MULL: return rewriteValueAMD64_OpAMD64MULL_0(v) case OpAMD64MULLconst: return rewriteValueAMD64_OpAMD64MULLconst_0(v) || rewriteValueAMD64_OpAMD64MULLconst_10(v) || rewriteValueAMD64_OpAMD64MULLconst_20(v) || rewriteValueAMD64_OpAMD64MULLconst_30(v) case OpAMD64MULQ: return rewriteValueAMD64_OpAMD64MULQ_0(v) case OpAMD64MULQconst: return rewriteValueAMD64_OpAMD64MULQconst_0(v) || rewriteValueAMD64_OpAMD64MULQconst_10(v) || rewriteValueAMD64_OpAMD64MULQconst_20(v) || rewriteValueAMD64_OpAMD64MULQconst_30(v) case OpAMD64MULSD: return rewriteValueAMD64_OpAMD64MULSD_0(v) case OpAMD64MULSDload: return rewriteValueAMD64_OpAMD64MULSDload_0(v) case OpAMD64MULSS: return rewriteValueAMD64_OpAMD64MULSS_0(v) case OpAMD64MULSSload: return rewriteValueAMD64_OpAMD64MULSSload_0(v) case OpAMD64NEGL: return rewriteValueAMD64_OpAMD64NEGL_0(v) case OpAMD64NEGQ: return rewriteValueAMD64_OpAMD64NEGQ_0(v) case OpAMD64NOTL: return rewriteValueAMD64_OpAMD64NOTL_0(v) case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ_0(v) case OpAMD64ORL: return rewriteValueAMD64_OpAMD64ORL_0(v) || rewriteValueAMD64_OpAMD64ORL_10(v) || rewriteValueAMD64_OpAMD64ORL_20(v) || rewriteValueAMD64_OpAMD64ORL_30(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst_0(v) case OpAMD64ORLconstmodify: return rewriteValueAMD64_OpAMD64ORLconstmodify_0(v) case OpAMD64ORLload: return rewriteValueAMD64_OpAMD64ORLload_0(v) case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify_0(v) case OpAMD64ORQ: return rewriteValueAMD64_OpAMD64ORQ_0(v) || rewriteValueAMD64_OpAMD64ORQ_10(v) || rewriteValueAMD64_OpAMD64ORQ_20(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst_0(v) case OpAMD64ORQconstmodify: return rewriteValueAMD64_OpAMD64ORQconstmodify_0(v) case OpAMD64ORQload: return rewriteValueAMD64_OpAMD64ORQload_0(v) case OpAMD64ORQmodify: return rewriteValueAMD64_OpAMD64ORQmodify_0(v) case OpAMD64ROLB: return rewriteValueAMD64_OpAMD64ROLB_0(v) case OpAMD64ROLBconst: return rewriteValueAMD64_OpAMD64ROLBconst_0(v) case OpAMD64ROLL: return rewriteValueAMD64_OpAMD64ROLL_0(v) case OpAMD64ROLLconst: return rewriteValueAMD64_OpAMD64ROLLconst_0(v) case OpAMD64ROLQ: return rewriteValueAMD64_OpAMD64ROLQ_0(v) case OpAMD64ROLQconst: return rewriteValueAMD64_OpAMD64ROLQconst_0(v) case OpAMD64ROLW: return rewriteValueAMD64_OpAMD64ROLW_0(v) case OpAMD64ROLWconst: return rewriteValueAMD64_OpAMD64ROLWconst_0(v) case OpAMD64RORB: return rewriteValueAMD64_OpAMD64RORB_0(v) case OpAMD64RORL: return rewriteValueAMD64_OpAMD64RORL_0(v) case OpAMD64RORQ: return rewriteValueAMD64_OpAMD64RORQ_0(v) case OpAMD64RORW: return rewriteValueAMD64_OpAMD64RORW_0(v) case OpAMD64SARB: return rewriteValueAMD64_OpAMD64SARB_0(v) case OpAMD64SARBconst: return rewriteValueAMD64_OpAMD64SARBconst_0(v) case OpAMD64SARL: return rewriteValueAMD64_OpAMD64SARL_0(v) case OpAMD64SARLconst: return rewriteValueAMD64_OpAMD64SARLconst_0(v) case OpAMD64SARQ: return rewriteValueAMD64_OpAMD64SARQ_0(v) case OpAMD64SARQconst: return rewriteValueAMD64_OpAMD64SARQconst_0(v) case OpAMD64SARW: return rewriteValueAMD64_OpAMD64SARW_0(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst_0(v) case OpAMD64SBBLcarrymask: return rewriteValueAMD64_OpAMD64SBBLcarrymask_0(v) case OpAMD64SBBQ: return rewriteValueAMD64_OpAMD64SBBQ_0(v) case OpAMD64SBBQcarrymask: return rewriteValueAMD64_OpAMD64SBBQcarrymask_0(v) case OpAMD64SBBQconst: return rewriteValueAMD64_OpAMD64SBBQconst_0(v) case OpAMD64SETA: return rewriteValueAMD64_OpAMD64SETA_0(v) case OpAMD64SETAE: return rewriteValueAMD64_OpAMD64SETAE_0(v) case OpAMD64SETAEstore: return rewriteValueAMD64_OpAMD64SETAEstore_0(v) case OpAMD64SETAstore: return rewriteValueAMD64_OpAMD64SETAstore_0(v) case OpAMD64SETB: return rewriteValueAMD64_OpAMD64SETB_0(v) case OpAMD64SETBE: return rewriteValueAMD64_OpAMD64SETBE_0(v) case OpAMD64SETBEstore: return rewriteValueAMD64_OpAMD64SETBEstore_0(v) case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore_0(v) case OpAMD64SETEQ: return rewriteValueAMD64_OpAMD64SETEQ_0(v) || rewriteValueAMD64_OpAMD64SETEQ_10(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore_0(v) || rewriteValueAMD64_OpAMD64SETEQstore_10(v) || rewriteValueAMD64_OpAMD64SETEQstore_20(v) case OpAMD64SETG: return rewriteValueAMD64_OpAMD64SETG_0(v) case OpAMD64SETGE: return rewriteValueAMD64_OpAMD64SETGE_0(v) case OpAMD64SETGEstore: return rewriteValueAMD64_OpAMD64SETGEstore_0(v) case OpAMD64SETGstore: return rewriteValueAMD64_OpAMD64SETGstore_0(v) case OpAMD64SETL: return rewriteValueAMD64_OpAMD64SETL_0(v) case OpAMD64SETLE: return rewriteValueAMD64_OpAMD64SETLE_0(v) case OpAMD64SETLEstore: return rewriteValueAMD64_OpAMD64SETLEstore_0(v) case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore_0(v) case OpAMD64SETNE: return rewriteValueAMD64_OpAMD64SETNE_0(v) || rewriteValueAMD64_OpAMD64SETNE_10(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore_0(v) || rewriteValueAMD64_OpAMD64SETNEstore_10(v) || rewriteValueAMD64_OpAMD64SETNEstore_20(v) case OpAMD64SHLL: return rewriteValueAMD64_OpAMD64SHLL_0(v) case OpAMD64SHLLconst: return rewriteValueAMD64_OpAMD64SHLLconst_0(v) case OpAMD64SHLQ: return rewriteValueAMD64_OpAMD64SHLQ_0(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst_0(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB_0(v) case OpAMD64SHRBconst: return rewriteValueAMD64_OpAMD64SHRBconst_0(v) case OpAMD64SHRL: return rewriteValueAMD64_OpAMD64SHRL_0(v) case OpAMD64SHRLconst: return rewriteValueAMD64_OpAMD64SHRLconst_0(v) case OpAMD64SHRQ: return rewriteValueAMD64_OpAMD64SHRQ_0(v) case OpAMD64SHRQconst: return rewriteValueAMD64_OpAMD64SHRQconst_0(v) case OpAMD64SHRW: return rewriteValueAMD64_OpAMD64SHRW_0(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst_0(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL_0(v) case OpAMD64SUBLconst: return rewriteValueAMD64_OpAMD64SUBLconst_0(v) case OpAMD64SUBLload: return rewriteValueAMD64_OpAMD64SUBLload_0(v) case OpAMD64SUBLmodify: return rewriteValueAMD64_OpAMD64SUBLmodify_0(v) case OpAMD64SUBQ: return rewriteValueAMD64_OpAMD64SUBQ_0(v) case OpAMD64SUBQborrow: return rewriteValueAMD64_OpAMD64SUBQborrow_0(v) case OpAMD64SUBQconst: return rewriteValueAMD64_OpAMD64SUBQconst_0(v) case OpAMD64SUBQload: return rewriteValueAMD64_OpAMD64SUBQload_0(v) case OpAMD64SUBQmodify: return rewriteValueAMD64_OpAMD64SUBQmodify_0(v) case OpAMD64SUBSD: return rewriteValueAMD64_OpAMD64SUBSD_0(v) case OpAMD64SUBSDload: return rewriteValueAMD64_OpAMD64SUBSDload_0(v) case OpAMD64SUBSS: return rewriteValueAMD64_OpAMD64SUBSS_0(v) case OpAMD64SUBSSload: return rewriteValueAMD64_OpAMD64SUBSSload_0(v) case OpAMD64TESTB: return rewriteValueAMD64_OpAMD64TESTB_0(v) case OpAMD64TESTBconst: return rewriteValueAMD64_OpAMD64TESTBconst_0(v) case OpAMD64TESTL: return rewriteValueAMD64_OpAMD64TESTL_0(v) case OpAMD64TESTLconst: return rewriteValueAMD64_OpAMD64TESTLconst_0(v) case OpAMD64TESTQ: return rewriteValueAMD64_OpAMD64TESTQ_0(v) case OpAMD64TESTQconst: return rewriteValueAMD64_OpAMD64TESTQconst_0(v) case OpAMD64TESTW: return rewriteValueAMD64_OpAMD64TESTW_0(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst_0(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock_0(v) case OpAMD64XADDQlock: return rewriteValueAMD64_OpAMD64XADDQlock_0(v) case OpAMD64XCHGL: return rewriteValueAMD64_OpAMD64XCHGL_0(v) case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ_0(v) case OpAMD64XORL: return rewriteValueAMD64_OpAMD64XORL_0(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst_0(v) || rewriteValueAMD64_OpAMD64XORLconst_10(v) case OpAMD64XORLconstmodify: return rewriteValueAMD64_OpAMD64XORLconstmodify_0(v) case OpAMD64XORLload: return rewriteValueAMD64_OpAMD64XORLload_0(v) case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify_0(v) case OpAMD64XORQ: return rewriteValueAMD64_OpAMD64XORQ_0(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst_0(v) case OpAMD64XORQconstmodify: return rewriteValueAMD64_OpAMD64XORQconstmodify_0(v) case OpAMD64XORQload: return rewriteValueAMD64_OpAMD64XORQload_0(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify_0(v) case OpAdd16: return rewriteValueAMD64_OpAdd16_0(v) case OpAdd32: return rewriteValueAMD64_OpAdd32_0(v) case OpAdd32F: return rewriteValueAMD64_OpAdd32F_0(v) case OpAdd64: return rewriteValueAMD64_OpAdd64_0(v) case OpAdd64F: return rewriteValueAMD64_OpAdd64F_0(v) case OpAdd8: return rewriteValueAMD64_OpAdd8_0(v) case OpAddPtr: return rewriteValueAMD64_OpAddPtr_0(v) case OpAddr: return rewriteValueAMD64_OpAddr_0(v) case OpAnd16: return rewriteValueAMD64_OpAnd16_0(v) case OpAnd32: return rewriteValueAMD64_OpAnd32_0(v) case OpAnd64: return rewriteValueAMD64_OpAnd64_0(v) case OpAnd8: return rewriteValueAMD64_OpAnd8_0(v) case OpAndB: return rewriteValueAMD64_OpAndB_0(v) case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32_0(v) case OpAtomicAdd64: return rewriteValueAMD64_OpAtomicAdd64_0(v) case OpAtomicAnd8: return rewriteValueAMD64_OpAtomicAnd8_0(v) case OpAtomicCompareAndSwap32: return rewriteValueAMD64_OpAtomicCompareAndSwap32_0(v) case OpAtomicCompareAndSwap64: return rewriteValueAMD64_OpAtomicCompareAndSwap64_0(v) case OpAtomicExchange32: return rewriteValueAMD64_OpAtomicExchange32_0(v) case OpAtomicExchange64: return rewriteValueAMD64_OpAtomicExchange64_0(v) case OpAtomicLoad32: return rewriteValueAMD64_OpAtomicLoad32_0(v) case OpAtomicLoad64: return rewriteValueAMD64_OpAtomicLoad64_0(v) case OpAtomicLoad8: return rewriteValueAMD64_OpAtomicLoad8_0(v) case OpAtomicLoadPtr: return rewriteValueAMD64_OpAtomicLoadPtr_0(v) case OpAtomicOr8: return rewriteValueAMD64_OpAtomicOr8_0(v) case OpAtomicStore32: return rewriteValueAMD64_OpAtomicStore32_0(v) case OpAtomicStore64: return rewriteValueAMD64_OpAtomicStore64_0(v) case OpAtomicStore8: return rewriteValueAMD64_OpAtomicStore8_0(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB_0(v) case OpAvg64u: return rewriteValueAMD64_OpAvg64u_0(v) case OpBitLen16: return rewriteValueAMD64_OpBitLen16_0(v) case OpBitLen32: return rewriteValueAMD64_OpBitLen32_0(v) case OpBitLen64: return rewriteValueAMD64_OpBitLen64_0(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8_0(v) case OpBswap32: return rewriteValueAMD64_OpBswap32_0(v) case OpBswap64: return rewriteValueAMD64_OpBswap64_0(v) case OpCeil: return rewriteValueAMD64_OpCeil_0(v) case OpClosureCall: return rewriteValueAMD64_OpClosureCall_0(v) case OpCom16: return rewriteValueAMD64_OpCom16_0(v) case OpCom32: return rewriteValueAMD64_OpCom32_0(v) case OpCom64: return rewriteValueAMD64_OpCom64_0(v) case OpCom8: return rewriteValueAMD64_OpCom8_0(v) case OpCondSelect: return rewriteValueAMD64_OpCondSelect_0(v) || rewriteValueAMD64_OpCondSelect_10(v) || rewriteValueAMD64_OpCondSelect_20(v) || rewriteValueAMD64_OpCondSelect_30(v) || rewriteValueAMD64_OpCondSelect_40(v) case OpConst16: return rewriteValueAMD64_OpConst16_0(v) case OpConst32: return rewriteValueAMD64_OpConst32_0(v) case OpConst32F: return rewriteValueAMD64_OpConst32F_0(v) case OpConst64: return rewriteValueAMD64_OpConst64_0(v) case OpConst64F: return rewriteValueAMD64_OpConst64F_0(v) case OpConst8: return rewriteValueAMD64_OpConst8_0(v) case OpConstBool: return rewriteValueAMD64_OpConstBool_0(v) case OpConstNil: return rewriteValueAMD64_OpConstNil_0(v) case OpCtz16: return rewriteValueAMD64_OpCtz16_0(v) case OpCtz16NonZero: return rewriteValueAMD64_OpCtz16NonZero_0(v) case OpCtz32: return rewriteValueAMD64_OpCtz32_0(v) case OpCtz32NonZero: return rewriteValueAMD64_OpCtz32NonZero_0(v) case OpCtz64: return rewriteValueAMD64_OpCtz64_0(v) case OpCtz64NonZero: return rewriteValueAMD64_OpCtz64NonZero_0(v) case OpCtz8: return rewriteValueAMD64_OpCtz8_0(v) case OpCtz8NonZero: return rewriteValueAMD64_OpCtz8NonZero_0(v) case OpCvt32Fto32: return rewriteValueAMD64_OpCvt32Fto32_0(v) case OpCvt32Fto64: return rewriteValueAMD64_OpCvt32Fto64_0(v) case OpCvt32Fto64F: return rewriteValueAMD64_OpCvt32Fto64F_0(v) case OpCvt32to32F: return rewriteValueAMD64_OpCvt32to32F_0(v) case OpCvt32to64F: return rewriteValueAMD64_OpCvt32to64F_0(v) case OpCvt64Fto32: return rewriteValueAMD64_OpCvt64Fto32_0(v) case OpCvt64Fto32F: return rewriteValueAMD64_OpCvt64Fto32F_0(v) case OpCvt64Fto64: return rewriteValueAMD64_OpCvt64Fto64_0(v) case OpCvt64to32F: return rewriteValueAMD64_OpCvt64to32F_0(v) case OpCvt64to64F: return rewriteValueAMD64_OpCvt64to64F_0(v) case OpDiv128u: return rewriteValueAMD64_OpDiv128u_0(v) case OpDiv16: return rewriteValueAMD64_OpDiv16_0(v) case OpDiv16u: return rewriteValueAMD64_OpDiv16u_0(v) case OpDiv32: return rewriteValueAMD64_OpDiv32_0(v) case OpDiv32F: return rewriteValueAMD64_OpDiv32F_0(v) case OpDiv32u: return rewriteValueAMD64_OpDiv32u_0(v) case OpDiv64: return rewriteValueAMD64_OpDiv64_0(v) case OpDiv64F: return rewriteValueAMD64_OpDiv64F_0(v) case OpDiv64u: return rewriteValueAMD64_OpDiv64u_0(v) case OpDiv8: return rewriteValueAMD64_OpDiv8_0(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u_0(v) case OpEq16: return rewriteValueAMD64_OpEq16_0(v) case OpEq32: return rewriteValueAMD64_OpEq32_0(v) case OpEq32F: return rewriteValueAMD64_OpEq32F_0(v) case OpEq64: return rewriteValueAMD64_OpEq64_0(v) case OpEq64F: return rewriteValueAMD64_OpEq64F_0(v) case OpEq8: return rewriteValueAMD64_OpEq8_0(v) case OpEqB: return rewriteValueAMD64_OpEqB_0(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr_0(v) case OpFMA: return rewriteValueAMD64_OpFMA_0(v) case OpFloor: return rewriteValueAMD64_OpFloor_0(v) case OpGeq16: return rewriteValueAMD64_OpGeq16_0(v) case OpGeq16U: return rewriteValueAMD64_OpGeq16U_0(v) case OpGeq32: return rewriteValueAMD64_OpGeq32_0(v) case OpGeq32F: return rewriteValueAMD64_OpGeq32F_0(v) case OpGeq32U: return rewriteValueAMD64_OpGeq32U_0(v) case OpGeq64: return rewriteValueAMD64_OpGeq64_0(v) case OpGeq64F: return rewriteValueAMD64_OpGeq64F_0(v) case OpGeq64U: return rewriteValueAMD64_OpGeq64U_0(v) case OpGeq8: return rewriteValueAMD64_OpGeq8_0(v) case OpGeq8U: return rewriteValueAMD64_OpGeq8U_0(v) case OpGetCallerPC: return rewriteValueAMD64_OpGetCallerPC_0(v) case OpGetCallerSP: return rewriteValueAMD64_OpGetCallerSP_0(v) case OpGetClosurePtr: return rewriteValueAMD64_OpGetClosurePtr_0(v) case OpGetG: return rewriteValueAMD64_OpGetG_0(v) case OpGreater16: return rewriteValueAMD64_OpGreater16_0(v) case OpGreater16U: return rewriteValueAMD64_OpGreater16U_0(v) case OpGreater32: return rewriteValueAMD64_OpGreater32_0(v) case OpGreater32F: return rewriteValueAMD64_OpGreater32F_0(v) case OpGreater32U: return rewriteValueAMD64_OpGreater32U_0(v) case OpGreater64: return rewriteValueAMD64_OpGreater64_0(v) case OpGreater64F: return rewriteValueAMD64_OpGreater64F_0(v) case OpGreater64U: return rewriteValueAMD64_OpGreater64U_0(v) case OpGreater8: return rewriteValueAMD64_OpGreater8_0(v) case OpGreater8U: return rewriteValueAMD64_OpGreater8U_0(v) case OpHmul32: return rewriteValueAMD64_OpHmul32_0(v) case OpHmul32u: return rewriteValueAMD64_OpHmul32u_0(v) case OpHmul64: return rewriteValueAMD64_OpHmul64_0(v) case OpHmul64u: return rewriteValueAMD64_OpHmul64u_0(v) case OpInterCall: return rewriteValueAMD64_OpInterCall_0(v) case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds_0(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil_0(v) case OpIsSliceInBounds: return rewriteValueAMD64_OpIsSliceInBounds_0(v) case OpLeq16: return rewriteValueAMD64_OpLeq16_0(v) case OpLeq16U: return rewriteValueAMD64_OpLeq16U_0(v) case OpLeq32: return rewriteValueAMD64_OpLeq32_0(v) case OpLeq32F: return rewriteValueAMD64_OpLeq32F_0(v) case OpLeq32U: return rewriteValueAMD64_OpLeq32U_0(v) case OpLeq64: return rewriteValueAMD64_OpLeq64_0(v) case OpLeq64F: return rewriteValueAMD64_OpLeq64F_0(v) case OpLeq64U: return rewriteValueAMD64_OpLeq64U_0(v) case OpLeq8: return rewriteValueAMD64_OpLeq8_0(v) case OpLeq8U: return rewriteValueAMD64_OpLeq8U_0(v) case OpLess16: return rewriteValueAMD64_OpLess16_0(v) case OpLess16U: return rewriteValueAMD64_OpLess16U_0(v) case OpLess32: return rewriteValueAMD64_OpLess32_0(v) case OpLess32F: return rewriteValueAMD64_OpLess32F_0(v) case OpLess32U: return rewriteValueAMD64_OpLess32U_0(v) case OpLess64: return rewriteValueAMD64_OpLess64_0(v) case OpLess64F: return rewriteValueAMD64_OpLess64F_0(v) case OpLess64U: return rewriteValueAMD64_OpLess64U_0(v) case OpLess8: return rewriteValueAMD64_OpLess8_0(v) case OpLess8U: return rewriteValueAMD64_OpLess8U_0(v) case OpLoad: return rewriteValueAMD64_OpLoad_0(v) case OpLocalAddr: return rewriteValueAMD64_OpLocalAddr_0(v) case OpLsh16x16: return rewriteValueAMD64_OpLsh16x16_0(v) case OpLsh16x32: return rewriteValueAMD64_OpLsh16x32_0(v) case OpLsh16x64: return rewriteValueAMD64_OpLsh16x64_0(v) case OpLsh16x8: return rewriteValueAMD64_OpLsh16x8_0(v) case OpLsh32x16: return rewriteValueAMD64_OpLsh32x16_0(v) case OpLsh32x32: return rewriteValueAMD64_OpLsh32x32_0(v) case OpLsh32x64: return rewriteValueAMD64_OpLsh32x64_0(v) case OpLsh32x8: return rewriteValueAMD64_OpLsh32x8_0(v) case OpLsh64x16: return rewriteValueAMD64_OpLsh64x16_0(v) case OpLsh64x32: return rewriteValueAMD64_OpLsh64x32_0(v) case OpLsh64x64: return rewriteValueAMD64_OpLsh64x64_0(v) case OpLsh64x8: return rewriteValueAMD64_OpLsh64x8_0(v) case OpLsh8x16: return rewriteValueAMD64_OpLsh8x16_0(v) case OpLsh8x32: return rewriteValueAMD64_OpLsh8x32_0(v) case OpLsh8x64: return rewriteValueAMD64_OpLsh8x64_0(v) case OpLsh8x8: return rewriteValueAMD64_OpLsh8x8_0(v) case OpMod16: return rewriteValueAMD64_OpMod16_0(v) case OpMod16u: return rewriteValueAMD64_OpMod16u_0(v) case OpMod32: return rewriteValueAMD64_OpMod32_0(v) case OpMod32u: return rewriteValueAMD64_OpMod32u_0(v) case OpMod64: return rewriteValueAMD64_OpMod64_0(v) case OpMod64u: return rewriteValueAMD64_OpMod64u_0(v) case OpMod8: return rewriteValueAMD64_OpMod8_0(v) case OpMod8u: return rewriteValueAMD64_OpMod8u_0(v) case OpMove: return rewriteValueAMD64_OpMove_0(v) || rewriteValueAMD64_OpMove_10(v) || rewriteValueAMD64_OpMove_20(v) case OpMul16: return rewriteValueAMD64_OpMul16_0(v) case OpMul32: return rewriteValueAMD64_OpMul32_0(v) case OpMul32F: return rewriteValueAMD64_OpMul32F_0(v) case OpMul64: return rewriteValueAMD64_OpMul64_0(v) case OpMul64F: return rewriteValueAMD64_OpMul64F_0(v) case OpMul64uhilo: return rewriteValueAMD64_OpMul64uhilo_0(v) case OpMul8: return rewriteValueAMD64_OpMul8_0(v) case OpNeg16: return rewriteValueAMD64_OpNeg16_0(v) case OpNeg32: return rewriteValueAMD64_OpNeg32_0(v) case OpNeg32F: return rewriteValueAMD64_OpNeg32F_0(v) case OpNeg64: return rewriteValueAMD64_OpNeg64_0(v) case OpNeg64F: return rewriteValueAMD64_OpNeg64F_0(v) case OpNeg8: return rewriteValueAMD64_OpNeg8_0(v) case OpNeq16: return rewriteValueAMD64_OpNeq16_0(v) case OpNeq32: return rewriteValueAMD64_OpNeq32_0(v) case OpNeq32F: return rewriteValueAMD64_OpNeq32F_0(v) case OpNeq64: return rewriteValueAMD64_OpNeq64_0(v) case OpNeq64F: return rewriteValueAMD64_OpNeq64F_0(v) case OpNeq8: return rewriteValueAMD64_OpNeq8_0(v) case OpNeqB: return rewriteValueAMD64_OpNeqB_0(v) case OpNeqPtr: return rewriteValueAMD64_OpNeqPtr_0(v) case OpNilCheck: return rewriteValueAMD64_OpNilCheck_0(v) case OpNot: return rewriteValueAMD64_OpNot_0(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr_0(v) case OpOr16: return rewriteValueAMD64_OpOr16_0(v) case OpOr32: return rewriteValueAMD64_OpOr32_0(v) case OpOr64: return rewriteValueAMD64_OpOr64_0(v) case OpOr8: return rewriteValueAMD64_OpOr8_0(v) case OpOrB: return rewriteValueAMD64_OpOrB_0(v) case OpPanicBounds: return rewriteValueAMD64_OpPanicBounds_0(v) case OpPopCount16: return rewriteValueAMD64_OpPopCount16_0(v) case OpPopCount32: return rewriteValueAMD64_OpPopCount32_0(v) case OpPopCount64: return rewriteValueAMD64_OpPopCount64_0(v) case OpPopCount8: return rewriteValueAMD64_OpPopCount8_0(v) case OpRotateLeft16: return rewriteValueAMD64_OpRotateLeft16_0(v) case OpRotateLeft32: return rewriteValueAMD64_OpRotateLeft32_0(v) case OpRotateLeft64: return rewriteValueAMD64_OpRotateLeft64_0(v) case OpRotateLeft8: return rewriteValueAMD64_OpRotateLeft8_0(v) case OpRound32F: return rewriteValueAMD64_OpRound32F_0(v) case OpRound64F: return rewriteValueAMD64_OpRound64F_0(v) case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven_0(v) case OpRsh16Ux16: return rewriteValueAMD64_OpRsh16Ux16_0(v) case OpRsh16Ux32: return rewriteValueAMD64_OpRsh16Ux32_0(v) case OpRsh16Ux64: return rewriteValueAMD64_OpRsh16Ux64_0(v) case OpRsh16Ux8: return rewriteValueAMD64_OpRsh16Ux8_0(v) case OpRsh16x16: return rewriteValueAMD64_OpRsh16x16_0(v) case OpRsh16x32: return rewriteValueAMD64_OpRsh16x32_0(v) case OpRsh16x64: return rewriteValueAMD64_OpRsh16x64_0(v) case OpRsh16x8: return rewriteValueAMD64_OpRsh16x8_0(v) case OpRsh32Ux16: return rewriteValueAMD64_OpRsh32Ux16_0(v) case OpRsh32Ux32: return rewriteValueAMD64_OpRsh32Ux32_0(v) case OpRsh32Ux64: return rewriteValueAMD64_OpRsh32Ux64_0(v) case OpRsh32Ux8: return rewriteValueAMD64_OpRsh32Ux8_0(v) case OpRsh32x16: return rewriteValueAMD64_OpRsh32x16_0(v) case OpRsh32x32: return rewriteValueAMD64_OpRsh32x32_0(v) case OpRsh32x64: return rewriteValueAMD64_OpRsh32x64_0(v) case OpRsh32x8: return rewriteValueAMD64_OpRsh32x8_0(v) case OpRsh64Ux16: return rewriteValueAMD64_OpRsh64Ux16_0(v) case OpRsh64Ux32: return rewriteValueAMD64_OpRsh64Ux32_0(v) case OpRsh64Ux64: return rewriteValueAMD64_OpRsh64Ux64_0(v) case OpRsh64Ux8: return rewriteValueAMD64_OpRsh64Ux8_0(v) case OpRsh64x16: return rewriteValueAMD64_OpRsh64x16_0(v) case OpRsh64x32: return rewriteValueAMD64_OpRsh64x32_0(v) case OpRsh64x64: return rewriteValueAMD64_OpRsh64x64_0(v) case OpRsh64x8: return rewriteValueAMD64_OpRsh64x8_0(v) case OpRsh8Ux16: return rewriteValueAMD64_OpRsh8Ux16_0(v) case OpRsh8Ux32: return rewriteValueAMD64_OpRsh8Ux32_0(v) case OpRsh8Ux64: return rewriteValueAMD64_OpRsh8Ux64_0(v) case OpRsh8Ux8: return rewriteValueAMD64_OpRsh8Ux8_0(v) case OpRsh8x16: return rewriteValueAMD64_OpRsh8x16_0(v) case OpRsh8x32: return rewriteValueAMD64_OpRsh8x32_0(v) case OpRsh8x64: return rewriteValueAMD64_OpRsh8x64_0(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8_0(v) case OpSelect0: return rewriteValueAMD64_OpSelect0_0(v) case OpSelect1: return rewriteValueAMD64_OpSelect1_0(v) case OpSignExt16to32: return rewriteValueAMD64_OpSignExt16to32_0(v) case OpSignExt16to64: return rewriteValueAMD64_OpSignExt16to64_0(v) case OpSignExt32to64: return rewriteValueAMD64_OpSignExt32to64_0(v) case OpSignExt8to16: return rewriteValueAMD64_OpSignExt8to16_0(v) case OpSignExt8to32: return rewriteValueAMD64_OpSignExt8to32_0(v) case OpSignExt8to64: return rewriteValueAMD64_OpSignExt8to64_0(v) case OpSlicemask: return rewriteValueAMD64_OpSlicemask_0(v) case OpSqrt: return rewriteValueAMD64_OpSqrt_0(v) case OpStaticCall: return rewriteValueAMD64_OpStaticCall_0(v) case OpStore: return rewriteValueAMD64_OpStore_0(v) case OpSub16: return rewriteValueAMD64_OpSub16_0(v) case OpSub32: return rewriteValueAMD64_OpSub32_0(v) case OpSub32F: return rewriteValueAMD64_OpSub32F_0(v) case OpSub64: return rewriteValueAMD64_OpSub64_0(v) case OpSub64F: return rewriteValueAMD64_OpSub64F_0(v) case OpSub8: return rewriteValueAMD64_OpSub8_0(v) case OpSubPtr: return rewriteValueAMD64_OpSubPtr_0(v) case OpTrunc: return rewriteValueAMD64_OpTrunc_0(v) case OpTrunc16to8: return rewriteValueAMD64_OpTrunc16to8_0(v) case OpTrunc32to16: return rewriteValueAMD64_OpTrunc32to16_0(v) case OpTrunc32to8: return rewriteValueAMD64_OpTrunc32to8_0(v) case OpTrunc64to16: return rewriteValueAMD64_OpTrunc64to16_0(v) case OpTrunc64to32: return rewriteValueAMD64_OpTrunc64to32_0(v) case OpTrunc64to8: return rewriteValueAMD64_OpTrunc64to8_0(v) case OpWB: return rewriteValueAMD64_OpWB_0(v) case OpXor16: return rewriteValueAMD64_OpXor16_0(v) case OpXor32: return rewriteValueAMD64_OpXor32_0(v) case OpXor64: return rewriteValueAMD64_OpXor64_0(v) case OpXor8: return rewriteValueAMD64_OpXor8_0(v) case OpZero: return rewriteValueAMD64_OpZero_0(v) || rewriteValueAMD64_OpZero_10(v) || rewriteValueAMD64_OpZero_20(v) case OpZeroExt16to32: return rewriteValueAMD64_OpZeroExt16to32_0(v) case OpZeroExt16to64: return rewriteValueAMD64_OpZeroExt16to64_0(v) case OpZeroExt32to64: return rewriteValueAMD64_OpZeroExt32to64_0(v) case OpZeroExt8to16: return rewriteValueAMD64_OpZeroExt8to16_0(v) case OpZeroExt8to32: return rewriteValueAMD64_OpZeroExt8to32_0(v) case OpZeroExt8to64: return rewriteValueAMD64_OpZeroExt8to64_0(v) } return false } func rewriteValueAMD64_OpAMD64ADCQ_0(v *Value) bool { // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) // result: (ADCQconst x [c] carry) for { carry := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64ADCQconst) v.AuxInt = c v.AddArg(x) v.AddArg(carry) return true } break } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) for { _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQcarry) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64ADCQconst_0(v *Value) bool { // match: (ADCQconst x [c] (FlagEQ)) // result: (ADDQconstcarry x [c]) for { c := v.AuxInt _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL_0(v *Value) bool { // match: (ADDL x (MOVLconst [c])) // result: (ADDLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVLconst { continue } c := v_1.AuxInt v.reset(OpAMD64ADDLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRLconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRWconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADDL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRBconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDL { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { if x != v_1.Args[_i1] { continue } y := v_1.Args[1^_i1] v.reset(OpAMD64LEAL2) v.AddArg(y) v.AddArg(x) return true } } break } // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDLconst { continue } c := v_0.AuxInt x := v_0.Args[0] y := v.Args[1^_i0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDL_10(v *Value) bool { // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64LEAL { continue } c := v_1.AuxInt s := v_1.Aux y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64NEGL { continue } y := v_1.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVLload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDLconst_0(v *Value) bool { // match: (ADDLconst [c] (ADDL x y)) // result: (LEAL1 [c] x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (SHLLconst [1] x)) // result: (LEAL1 [c] x x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = c v.AddArg(x) v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(c+d) // result: (LEAL [c+d] {s} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } d := v_0.AuxInt s := v_0.Aux x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL1 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL2 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL2 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL4 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL4 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAL8 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL8 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDLconst [c] x) // cond: int32(c)==0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // result: (MOVLconst [int64(int32(c+d))]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = int64(int32(c + d)) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // result: (ADDLconst [int64(int32(c+d))] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int64(int32(c + d)) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconst_10(v *Value) bool { // match: (ADDLconst [off] x:(SP)) // result: (LEAL [off] x) for { off := v.AuxInt x := v.Args[0] if x.Op != OpSP { break } v.reset(OpAMD64LEAL) v.AuxInt = off v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconstmodify_0(v *Value) bool { // match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (ADDL x (MOVLf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSSstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDL) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDLmodify_0(v *Value) bool { // match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ_0(v *Value) bool { // match: (ADDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADDQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLQconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRQconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDQ { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDQ { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { if x != v_1.Args[_i1] { continue } y := v_1.Args[1^_i1] v.reset(OpAMD64LEAQ2) v.AddArg(y) v.AddArg(x) return true } } break } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDQconst { continue } c := v_0.AuxInt x := v_0.Args[0] y := v.Args[1^_i0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64LEAQ { continue } c := v_1.AuxInt s := v_1.Aux y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64NEGQ { continue } y := v_1.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQ_10(v *Value) bool { // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVQload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQcarry_0(v *Value) bool { // match: (ADDQcarry x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconstcarry x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = c v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQconst_0(v *Value) bool { // match: (ADDQconst [c] (ADDQ x y)) // result: (LEAQ1 [c] x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (SHLQconst [1] x)) // result: (LEAQ1 [c] x x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = c v.AddArg(x) v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ [d] {s} x)) // cond: is32Bit(c+d) // result: (LEAQ [c+d] {s} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } d := v_0.AuxInt s := v_0.Aux x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ1 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ1 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (LEAQ2 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ2 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (LEAQ4 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ4 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [c] (LEAQ8 [d] {s} x y)) // cond: is32Bit(c+d) // result: (LEAQ8 [c+d] {s} x y) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } d := v_0.AuxInt s := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (ADDQconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDQconst [c] (MOVQconst [d])) // result: (MOVQconst [c+d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = c + d return true } // match: (ADDQconst [c] (ADDQconst [d] x)) // cond: is32Bit(c+d) // result: (ADDQconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = c + d v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconst_10(v *Value) bool { // match: (ADDQconst [off] x:(SP)) // result: (LEAQ [off] x) for { off := v.AuxInt x := v.Args[0] if x.Op != OpSP { break } v.reset(OpAMD64LEAQ) v.AuxInt = off v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconstmodify_0(v *Value) bool { // match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (ADDQconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (ADDQconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDQload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (ADDQ x (MOVQf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSDstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDQ) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDQmodify_0(v *Value) bool { // match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (ADDQmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSD_0(v *Value) bool { // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVSDload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSDload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (ADDSD x (MOVQi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVQstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDSD) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDSS_0(v *Value) bool { // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVSSload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSSload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (ADDSS x (MOVLi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVLstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64ADDSS) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64ANDL_0(v *Value) bool { // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { continue } x := v.Args[1^_i0] v.reset(OpAMD64BTRL) v.AddArg(x) v.AddArg(y) return true } break } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRLconst [log2uint32(^c)] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVLconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRLconst) v.AuxInt = log2uint32(^c) v.AddArg(x) return true } break } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVLconst { continue } c := v_1.AuxInt v.reset(OpAMD64ANDLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ANDL x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVLload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDLconst_0(v *Value) bool { // match: (ANDLconst [c] x) // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRLconst [log2uint32(^c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = log2uint32(^c) v.AddArg(x) return true } // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDLconst [c] (BTRLconst [d] x)) // result: (ANDLconst [c &^ (1<= 128 // result: (BTRQconst [log2(^c)] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVQconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRQconst) v.AuxInt = log2(^c) v.AddArg(x) return true } break } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64ANDQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ANDQ x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVQload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDQconst_0(v *Value) bool { // match: (ANDQconst [c] x) // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRQconst [log2(^c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = log2(^c) v.AddArg(x) return true } // match: (ANDQconst [c] (ANDQconst [d] x)) // result: (ANDQconst [c & d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDQconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDQconst [c] (BTRQconst [d] x)) // result: (ANDQconst [c &^ (1< [1<<8] (MOVBQZX x))) // result: (BSFQ (ORQconst [1<<8] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if v_0.AuxInt != 1<<8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVBQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = 1 << 8 v0.AddArg(x) v.AddArg(v0) return true } // match: (BSFQ (ORQconst [1<<16] (MOVWQZX x))) // result: (BSFQ (ORQconst [1<<16] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if v_0.AuxInt != 1<<16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVWQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = 1 << 16 v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64BTCLconst_0(v *Value) bool { // match: (BTCLconst [c] (XORLconst [d] x)) // result: (XORLconst [d ^ 1<d // result: (BTLconst [c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = c - d v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if v.AuxInt != 0 { break } s := v.Args[0] if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg(y) v.AddArg(x) return true } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !((c + d) < 32) { break } v.reset(OpAMD64BTLconst) v.AuxInt = c + d v.AddArg(x) return true } // match: (BTLconst [c] (SHLLconst [d] x)) // cond: c>d // result: (BTLconst [c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = c - d v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRL x y)) // result: (BTL y x) for { if v.AuxInt != 0 { break } s := v.Args[0] if s.Op != OpAMD64SHRL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64BTQconst_0(v *Value) bool { // match: (BTQconst [c] (SHRQconst [d] x)) // cond: (c+d)<64 // result: (BTQconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !((c + d) < 64) { break } v.reset(OpAMD64BTQconst) v.AuxInt = c + d v.AddArg(x) return true } // match: (BTQconst [c] (SHLQconst [d] x)) // cond: c>d // result: (BTQconst [c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTQconst) v.AuxInt = c - d v.AddArg(x) return true } // match: (BTQconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if v.AuxInt != 0 { break } s := v.Args[0] if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64BTRLconst_0(v *Value) bool { // match: (BTRLconst [c] (BTSLconst [c] x)) // result: (BTRLconst [c] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64BTSLconst || v_0.AuxInt != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = c v.AddArg(x) return true } // match: (BTRLconst [c] (BTCLconst [c] x)) // result: (BTRLconst [c] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64BTCLconst || v_0.AuxInt != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = c v.AddArg(x) return true } // match: (BTRLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [d &^ (1<uint8(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int8(x) < int8(y) && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>int8(y) && uint8(x) int8(y) && uint8(x) < uint8(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>int8(y) && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int8(x) > int8(y) && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < int8(n) // result: (FlagLT_ULT) for { n := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } m := v_0.AuxInt if !(0 <= int8(m) && int8(m) < int8(n)) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPBconst (ANDL x y) [0]) // result: (TESTB x y) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64TESTB) v.AddArg(x) v.AddArg(y) return true } // match: (CMPBconst (ANDLconst [c] x) [0]) // result: (TESTBconst [int64(int8(c))] x) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64TESTBconst) v.AuxInt = int64(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // result: (TESTB x x) for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpAMD64TESTB) v.AddArg(x) v.AddArg(x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(c,off)] ptr mem) for { c := v.AuxInt l := v.Args[0] if l.Op != OpAMD64MOVBload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(c, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconstload_0(v *Value) bool { // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (CMPBconstload [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (CMPBconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBload_0(v *Value) bool { // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (CMPBload [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // cond: validValAndOff(int64(int8(c)),off) // result: (CMPBconstload {sym} [makeValAndOff(int64(int8(c)),off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validValAndOff(int64(int8(c)), off)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPL_0(v *Value) bool { b := v.Block // match: (CMPL x (MOVLconst [c])) // result: (CMPLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64CMPLconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // result: (InvertFlags (CMPLconst x [c])) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { x := v.Args[1] l := v.Args[0] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPLload) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(x) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPLconst_0(v *Value) bool { // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)uint32(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int32(x) < int32(y) && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)>int32(y) && uint32(x) int32(y) && uint32(x) < uint32(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: int32(x)>int32(y) && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int32(x) > int32(y) && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } x := v_0.AuxInt if !(x < y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>y && uint64(x)>uint64(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } x := v_0.AuxInt if !(x > y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQconst (MOVBQZX _) [c]) // cond: 0xFF < c // result: (FlagLT_ULT) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVWQZX _) [c]) // cond: 0xFFFF < c // result: (FlagLT_ULT) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVLQZX _) [c]) // cond: 0xFFFFFFFF < c // result: (FlagLT_ULT) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLQZX || !(0xFFFFFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } return false } func rewriteValueAMD64_OpAMD64CMPQconst_10(v *Value) bool { b := v.Block // match: (CMPQconst (SHRQconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 64 && (1<uint16(y) // result: (FlagLT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int16(x) < int16(y) && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>int16(y) && uint16(x) int16(y) && uint16(x) < uint16(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>int16(y) && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } x := v_0.AuxInt if !(int16(x) > int16(y) && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < int16(n) // result: (FlagLT_ULT) for { n := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } m := v_0.AuxInt if !(0 <= int16(m) && int16(m) < int16(n)) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPWconst (ANDL x y) [0]) // result: (TESTW x y) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64TESTW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWconst (ANDLconst [c] x) [0]) // result: (TESTWconst [int64(int16(c))] x) for { if v.AuxInt != 0 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64TESTWconst) v.AuxInt = int64(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // result: (TESTW x x) for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpAMD64TESTW) v.AddArg(x) v.AddArg(x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(c,off)] ptr mem) for { c := v.AuxInt l := v.Args[0] if l.Op != OpAMD64MOVWload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(c, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWconstload_0(v *Value) bool { // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd(off2) // result: (CMPWconstload [ValAndOff(valoff1).add(off2)] {sym} base mem) for { valoff1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = sym v.AddArg(base) v.AddArg(mem) return true } // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) // result: (CMPWconstload [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = ValAndOff(valoff1).add(off2) v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWload_0(v *Value) bool { // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (CMPWload [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // cond: validValAndOff(int64(int16(c)),off) // result: (CMPWconstload {sym} [makeValAndOff(int64(int16(c)),off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validValAndOff(int64(int16(c)), off)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGLlock_0(v *Value) bool { // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(off1+off2) // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] old := v.Args[1] new_ := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPXCHGLlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGQlock_0(v *Value) bool { // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(off1+off2) // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] old := v.Args[1] new_ := v.Args[2] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64CMPXCHGQlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSD_0(v *Value) bool { // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSDload_0(v *Value) bool { // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSS_0(v *Value) bool { // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSSload_0(v *Value) bool { // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64HMULL_0(v *Value) bool { // match: (HMULL x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULL y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULL) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64HMULLU_0(v *Value) bool { // match: (HMULLU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULLU y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULLU) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQ_0(v *Value) bool { // match: (HMULQ x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQ y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQ) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQU_0(v *Value) bool { // match: (HMULQU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQU y x) for { y := v.Args[1] x := v.Args[0] if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQU) v.AddArg(y) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAL_0(v *Value) bool { // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(c+d) // result: (LEAL [c+d] {s} x) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAL) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v_0.Args[_i0] y := v_0.Args[1^_i0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL1_0(v *Value) bool { // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDLconst { continue } d := v_0.AuxInt x := v_0.Args[0] y := v.Args[1^_i0] if !(is32Bit(c+d) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL2_0(v *Value) bool { // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+2*d) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+2*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = c + 2*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // result: (LEAL4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL4_0(v *Value) bool { // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+4*d) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+4*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = c + 4*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // result: (LEAL8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL8_0(v *Value) bool { // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(c+8*d) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+8*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = c + 8*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ_0(v *Value) bool { // match: (LEAQ [c] {s} (ADDQconst [d] x)) // cond: is32Bit(c+d) // result: (LEAQ [c+d] {s} x) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = c + d v.Aux = s v.AddArg(x) return true } // match: (LEAQ [c] {s} (ADDQ x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := v.AuxInt s := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v_0.Args[_i0] y := v_0.Args[1^_i0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) return true } // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ1_0(v *Value) bool { // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDQconst { continue } d := v_0.AuxInt x := v_0.Args[0] y := v.Args[1^_i0] if !(is32Bit(c+d) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } break } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64LEAQ { continue } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] y := v.Args[1^_i0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAQ2_0(v *Value) bool { // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ2 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(c+2*d) && y.Op != OpSB // result: (LEAQ2 [c+2*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+2*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = c + 2*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ4 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ4_0(v *Value) bool { // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ4 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(c+4*d) && y.Op != OpSB // result: (LEAQ4 [c+4*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+4*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = c + 4*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ4 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ8 [c] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = c v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ8_0(v *Value) bool { // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ8 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c+d) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = c + d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(c+8*d) && y.Op != OpSB // result: (LEAQ8 [c+8*d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt y := v_1.Args[0] if !(is32Bit(c+8*d) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = c + 8*d v.Aux = s v.AddArg(x) v.AddArg(y) return true } // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux x := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSX_0(v *Value) bool { b := v.Block // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVBload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0x7f v.AddArg(x) return true } // match: (MOVBQSX (MOVBQSX x)) // result: (MOVBQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSXload_0(v *Value) bool { // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBQSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQZX_0(v *Value) bool { b := v.Block // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVBload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVBQZX x) // cond: zeroUpper56Bits(x,3) // result: x for { x := v.Args[0] if !(zeroUpper56Bits(x, 3)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVBQZX x:(MOVBloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVBloadidx1 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVBloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVBQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0xff v.AddArg(x) return true } // match: (MOVBQZX (MOVBQZX x)) // result: (MOVBQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBatomicload_0(v *Value) bool { // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBatomicload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBload_0(v *Value) bool { // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVBloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVBload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(read8(sym, off))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int64(read8(sym, off)) return true } return false } func rewriteValueAMD64_OpAMD64MOVBloadidx1_0(v *Value) bool { // match: (MOVBloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDQconst { continue } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1^_i0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVBloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDQconst { continue } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVBloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVBloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVBload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { p := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(i + c)) { continue } v.reset(OpAMD64MOVBload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MOVBstore_0(v *Value) bool { // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) // cond: y.Uses == 1 // result: (SETLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETL { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) // cond: y.Uses == 1 // result: (SETLEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETLE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) // cond: y.Uses == 1 // result: (SETGstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETG { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETGstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) // cond: y.Uses == 1 // result: (SETGEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETGE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) // cond: y.Uses == 1 // result: (SETEQstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETEQ { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) // cond: y.Uses == 1 // result: (SETNEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETNE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) // cond: y.Uses == 1 // result: (SETBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETB { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) // cond: y.Uses == 1 // result: (SETBEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETBE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) // cond: y.Uses == 1 // result: (SETAstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETA { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETAstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) // cond: y.Uses == 1 // result: (SETAEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SETAE { break } x := y.Args[0] if !(y.Uses == 1) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_10(v *Value) bool { b := v.Block // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBQSX { break } x := v_1.Args[0] v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVBQZX { break } x := v_1.Args[0] v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validOff(off) // result: (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(int64(int8(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVBstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVBstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] val := v.Args[1] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } break } // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstore [i-1] {s} p (ROLWconst [8] w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x0 := v.Args[2] if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-1 || x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || x0_1.AuxInt != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = 8 v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x2 := v.Args[2] if x2.Op != OpAMD64MOVBstore || x2.AuxInt != i-1 || x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || x2_1.AuxInt != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || x1.AuxInt != i-2 || x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || x1_1.AuxInt != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-3 || x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || x0_1.AuxInt != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 3 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x6 := v.Args[2] if x6.Op != OpAMD64MOVBstore || x6.AuxInt != i-1 || x6.Aux != s { break } _ = x6.Args[2] if p != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || x6_1.AuxInt != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || x5.AuxInt != i-2 || x5.Aux != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || x5_1.AuxInt != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || x4.AuxInt != i-3 || x4.Aux != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || x4_1.AuxInt != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || x3.AuxInt != i-4 || x3.Aux != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || x3_1.AuxInt != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || x2.AuxInt != i-5 || x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || x2_1.AuxInt != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || x1.AuxInt != i-6 || x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || x1_1.AuxInt != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || x0.AuxInt != i-7 || x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || x0_1.AuxInt != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 7 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRWconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i+1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || x_1.AuxInt != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVBstore || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVBload { break } j := x1.AuxInt s2 := x1.Aux mem := x1.Args[1] p2 := x1.Args[0] mem2 := v.Args[2] if mem2.Op != OpAMD64MOVBstore || mem2.AuxInt != i-1 || mem2.Aux != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVBload || x2.AuxInt != j-1 || x2.Aux != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = j - 1 v0.Aux = s2 v0.AddArg(p2) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore_30(v *Value) bool { // match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconst_0(v *Value) bool { // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVBstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVBstoreconst { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVBstoreconst [a] {s} p x:(MOVBstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconst [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p mem) for { a := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVBstoreconst { break } c := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconstidx1_0(v *Value) bool { // match: (MOVBstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVBstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVBstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVBstoreconstidx1 [c] {s} p i x:(MOVBstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() && clobber(x) // result: (MOVWstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xff | ValAndOff(c).Val()<<8, ValAndOff(a).Off())] {s} p i mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVBstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+1 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xff|ValAndOff(c).Val()<<8, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(i) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreidx1_0(v *Value) bool { b := v.Block // match: (MOVBstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVBstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVBstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x0:(MOVBstoreidx1 [i-1] {s} p idx (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstoreidx1 [i-1] {s} p idx (ROLWconst [8] w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x0 := v.Args[3] if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-1 || x0.Aux != s { break } mem := x0.Args[3] if p != x0.Args[0] || idx != x0.Args[1] { break } x0_2 := x0.Args[2] if x0_2.Op != OpAMD64SHRWconst || x0_2.AuxInt != 8 || w != x0_2.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, w.Type) v0.AuxInt = 8 v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x2:(MOVBstoreidx1 [i-1] {s} p idx (SHRLconst [8] w) x1:(MOVBstoreidx1 [i-2] {s} p idx (SHRLconst [16] w) x0:(MOVBstoreidx1 [i-3] {s} p idx (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) // result: (MOVLstoreidx1 [i-3] {s} p idx (BSWAPL w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x2 := v.Args[3] if x2.Op != OpAMD64MOVBstoreidx1 || x2.AuxInt != i-1 || x2.Aux != s { break } _ = x2.Args[3] if p != x2.Args[0] || idx != x2.Args[1] { break } x2_2 := x2.Args[2] if x2_2.Op != OpAMD64SHRLconst || x2_2.AuxInt != 8 || w != x2_2.Args[0] { break } x1 := x2.Args[3] if x1.Op != OpAMD64MOVBstoreidx1 || x1.AuxInt != i-2 || x1.Aux != s { break } _ = x1.Args[3] if p != x1.Args[0] || idx != x1.Args[1] { break } x1_2 := x1.Args[2] if x1_2.Op != OpAMD64SHRLconst || x1_2.AuxInt != 16 || w != x1_2.Args[0] { break } x0 := x1.Args[3] if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-3 || x0.Aux != s { break } mem := x0.Args[3] if p != x0.Args[0] || idx != x0.Args[1] { break } x0_2 := x0.Args[2] if x0_2.Op != OpAMD64SHRLconst || x0_2.AuxInt != 24 || w != x0_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 3 v.Aux = s v.AddArg(p) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx w x6:(MOVBstoreidx1 [i-1] {s} p idx (SHRQconst [8] w) x5:(MOVBstoreidx1 [i-2] {s} p idx (SHRQconst [16] w) x4:(MOVBstoreidx1 [i-3] {s} p idx (SHRQconst [24] w) x3:(MOVBstoreidx1 [i-4] {s} p idx (SHRQconst [32] w) x2:(MOVBstoreidx1 [i-5] {s} p idx (SHRQconst [40] w) x1:(MOVBstoreidx1 [i-6] {s} p idx (SHRQconst [48] w) x0:(MOVBstoreidx1 [i-7] {s} p idx (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) // result: (MOVQstoreidx1 [i-7] {s} p idx (BSWAPQ w) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] w := v.Args[2] x6 := v.Args[3] if x6.Op != OpAMD64MOVBstoreidx1 || x6.AuxInt != i-1 || x6.Aux != s { break } _ = x6.Args[3] if p != x6.Args[0] || idx != x6.Args[1] { break } x6_2 := x6.Args[2] if x6_2.Op != OpAMD64SHRQconst || x6_2.AuxInt != 8 || w != x6_2.Args[0] { break } x5 := x6.Args[3] if x5.Op != OpAMD64MOVBstoreidx1 || x5.AuxInt != i-2 || x5.Aux != s { break } _ = x5.Args[3] if p != x5.Args[0] || idx != x5.Args[1] { break } x5_2 := x5.Args[2] if x5_2.Op != OpAMD64SHRQconst || x5_2.AuxInt != 16 || w != x5_2.Args[0] { break } x4 := x5.Args[3] if x4.Op != OpAMD64MOVBstoreidx1 || x4.AuxInt != i-3 || x4.Aux != s { break } _ = x4.Args[3] if p != x4.Args[0] || idx != x4.Args[1] { break } x4_2 := x4.Args[2] if x4_2.Op != OpAMD64SHRQconst || x4_2.AuxInt != 24 || w != x4_2.Args[0] { break } x3 := x4.Args[3] if x3.Op != OpAMD64MOVBstoreidx1 || x3.AuxInt != i-4 || x3.Aux != s { break } _ = x3.Args[3] if p != x3.Args[0] || idx != x3.Args[1] { break } x3_2 := x3.Args[2] if x3_2.Op != OpAMD64SHRQconst || x3_2.AuxInt != 32 || w != x3_2.Args[0] { break } x2 := x3.Args[3] if x2.Op != OpAMD64MOVBstoreidx1 || x2.AuxInt != i-5 || x2.Aux != s { break } _ = x2.Args[3] if p != x2.Args[0] || idx != x2.Args[1] { break } x2_2 := x2.Args[2] if x2_2.Op != OpAMD64SHRQconst || x2_2.AuxInt != 40 || w != x2_2.Args[0] { break } x1 := x2.Args[3] if x1.Op != OpAMD64MOVBstoreidx1 || x1.AuxInt != i-6 || x1.Aux != s { break } _ = x1.Args[3] if p != x1.Args[0] || idx != x1.Args[1] { break } x1_2 := x1.Args[2] if x1_2.Op != OpAMD64SHRQconst || x1_2.AuxInt != 48 || w != x1_2.Args[0] { break } x0 := x1.Args[3] if x0.Op != OpAMD64MOVBstoreidx1 || x0.AuxInt != i-7 || x0.Aux != s { break } mem := x0.Args[3] if p != x0.Args[0] || idx != x0.Args[1] { break } x0_2 := x0.Args[2] if x0_2.Op != OpAMD64SHRQconst || x0_2.AuxInt != 56 || w != x0_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 7 v.Aux = s v.AddArg(p) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, w.Type) v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRWconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRWconst || v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst || v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRQconst [8] w) x:(MOVBstoreidx1 [i-1] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 8 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVBstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVBstoreidx1 [i-1] {s} p idx w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx1 [i-1] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVBstoreidx1 || x.AuxInt != i-1 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = i - 1 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreidx1_10(v *Value) bool { // match: (MOVBstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVBstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSX_0(v *Value) bool { b := v.Block // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQSX (ANDLconst [c] x)) // cond: c & 0x80000000 == 0 // result: (ANDLconst [c & 0x7fffffff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x80000000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0x7fffffff v.AddArg(x) return true } // match: (MOVLQSX (MOVLQSX x)) // result: (MOVLQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVWQSX x)) // result: (MOVWQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVBQSX x)) // result: (MOVBQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSXload_0(v *Value) bool { // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLQSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQZX_0(v *Value) bool { b := v.Block // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVLQZX x) // cond: zeroUpper32Bits(x,3) // result: x for { x := v.Args[0] if !(zeroUpper32Bits(x, 3)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVLQZX x:(MOVLloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLloadidx1 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVLQZX x:(MOVLloadidx4 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLloadidx4 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLloadidx4 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx4, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVLQZX (ANDLconst [c] x)) // result: (ANDLconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVLQZX (MOVLQZX x)) // result: (MOVLQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVWQZX x)) // result: (MOVWQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVBQZX x)) // result: (MOVBQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLatomicload_0(v *Value) bool { // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLatomicload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLf2i_0(v *Value) bool { b := v.Block // match: (MOVLf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVLi2f_0(v *Value) bool { b := v.Block // match: (MOVLi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVLload_0(v *Value) bool { // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVLloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVLload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVSSstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVLf2i) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVLload_10(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64(read32(sym, off, config.BigEndian)) return true } return false } func rewriteValueAMD64_OpAMD64MOVLloadidx1_0(v *Value) bool { // match: (MOVLloadidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) // result: (MOVLloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { continue } idx := v_1.Args[0] v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVLloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVLloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { continue } idx := v_1.Args[0] v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVLloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDQconst { continue } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1^_i0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVLloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDQconst { continue } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVLloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVLloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVLload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { p := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(i + c)) { continue } v.reset(OpAMD64MOVLload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MOVLloadidx4_0(v *Value) bool { // match: (MOVLloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVLloadidx4 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+4*d) // result: (MOVLloadidx4 [c+4*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVLloadidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx4 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+4*c) // result: (MOVLload [i+4*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLloadidx8_0(v *Value) bool { // match: (MOVLloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVLloadidx8 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+8*d) // result: (MOVLloadidx8 [c+8*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVLloadidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLloadidx8 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+8*c) // result: (MOVLload [i+8*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore_0(v *Value) bool { // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLQSX { break } x := v_1.Args[0] v.reset(OpAMD64MOVLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLQZX { break } x := v_1.Args[0] v.reset(OpAMD64MOVLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(int64(int32(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validOff(off) // result: (MOVLstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(int64(int32(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVLstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVLstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] val := v.Args[1] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MOVLstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst || v_1.AuxInt != 32 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVLstore || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVLstore || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVLload { break } j := x1.AuxInt s2 := x1.Aux mem := x1.Args[1] p2 := x1.Args[0] mem2 := v.Args[2] if mem2.Op != OpAMD64MOVLstore || mem2.AuxInt != i-4 || mem2.Aux != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVLload || x2.AuxInt != j-4 || x2.Aux != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x2.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = j - 4 v0.Aux = s2 v0.AddArg(p2) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORLload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDL { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64ADDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MOVLstore_20(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SUBL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDL { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64ANDLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORL { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64ORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORL { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64XORLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(BTCL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTCLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTCL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTCLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(BTRL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTRLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTRL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTRLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore {sym} [off] ptr y:(BTSL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTSLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTSL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTSLmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ADDLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ADDLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ANDLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ANDLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ANDLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ORLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ORLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ORLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore_30(v *Value) bool { // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (XORLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64XORLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64XORLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(BTCLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTCLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTCLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTCLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(BTRLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTRLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTRLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTRLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr a:(BTSLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTSLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTSLconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTSLconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) // result: (MOVSSstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLf2i { break } val := v_1.Args[0] v.reset(OpAMD64MOVSSstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconst_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym1} (LEAQ4 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVLstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconst [c] {s} p x:(MOVLstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstore [ValAndOff(a).Off()] {s} p (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVLstoreconst { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVLstoreconst [a] {s} p x:(MOVLstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstore [ValAndOff(a).Off()] {s} p (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { a := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVLstoreconst { break } c := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVLstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVLstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconstidx1_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconstidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) // result: (MOVLstoreconstidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVLstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx1 [c] {s} p i x:(MOVLstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstoreidx1 [ValAndOff(a).Off()] {s} p i (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVLstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v.AddArg(i) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconstidx4_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconstidx4 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx4 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(4*c) // result: (MOVLstoreconstidx4 [ValAndOff(x).add(4*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(4 * c)) { break } v.reset(OpAMD64MOVLstoreconstidx4) v.AuxInt = ValAndOff(x).add(4 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVLstoreconstidx4 [c] {s} p i x:(MOVLstoreconstidx4 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() && clobber(x) // result: (MOVQstoreidx1 [ValAndOff(a).Off()] {s} p (SHLQconst [2] i) (MOVQconst [ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVLstoreconstidx4 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+4 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = ValAndOff(a).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, i.Type) v0.AuxInt = 2 v0.AddArg(i) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = ValAndOff(a).Val()&0xffffffff | ValAndOff(c).Val()<<32 v.AddArg(v1) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreidx1_0(v *Value) bool { // match: (MOVLstoreidx1 [c] {sym} ptr (SHLQconst [2] idx) val mem) // result: (MOVLstoreidx4 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) // result: (MOVLstoreidx8 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [i] {s} p idx (SHRQconst [32] w) x:(MOVLstoreidx1 [i-4] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 32 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx1 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVLstoreidx1 [i-4] {s} p idx w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx1 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVLstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVLstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreidx4_0(v *Value) bool { b := v.Block // match: (MOVLstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx4 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+4*d) // result: (MOVLstoreidx4 [c+4*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVLstoreidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [i] {s} p idx (SHRQconst [32] w) x:(MOVLstoreidx4 [i-4] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p (SHLQconst [2] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 32 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx4 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 2 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [i] {s} p idx (SHRQconst [j] w) x:(MOVLstoreidx4 [i-4] {s} p idx w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstoreidx1 [i-4] {s} p (SHLQconst [2] idx) w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVLstoreidx4 || x.AuxInt != i-4 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = i - 4 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 2 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVLstoreidx4 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+4*c) // result: (MOVLstore [i+4*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreidx8_0(v *Value) bool { // match: (MOVLstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVLstoreidx8 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+8*d) // result: (MOVLstoreidx8 [c+8*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVLstoreidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVLstoreidx8 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+8*c) // result: (MOVLstore [i+8*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOload_0(v *Value) bool { // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVOload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstore_0(v *Value) bool { // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVOstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQatomicload_0(v *Value) bool { // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVQatomicload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQatomicload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQf2i_0(v *Value) bool { b := v.Block // match: (MOVQf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVQi2f_0(v *Value) bool { b := v.Block // match: (MOVQi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpArg { break } u := v_0.Type off := v_0.AuxInt sym := v_0.Aux if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym return true } return false } func rewriteValueAMD64_OpAMD64MOVQload_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVQloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVQload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVQload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) // result: (MOVQf2i val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVSDstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVQf2i) v.AddArg(val) return true } // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64(read64(sym, off, config.BigEndian)) return true } return false } func rewriteValueAMD64_OpAMD64MOVQloadidx1_0(v *Value) bool { // match: (MOVQloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVQloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { continue } idx := v_1.Args[0] v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVQloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDQconst { continue } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1^_i0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVQloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDQconst { continue } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVQloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVQloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVQload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { p := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(i + c)) { continue } v.reset(OpAMD64MOVQload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MOVQloadidx8_0(v *Value) bool { // match: (MOVQloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVQloadidx8 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+8*d) // result: (MOVQloadidx8 [c+8*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVQloadidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQloadidx8 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+8*c) // result: (MOVQload [i+8*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_0(v *Value) bool { // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validValAndOff(c,off) // result: (MOVQstoreconst [makeValAndOff(c,off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validValAndOff(c, off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVQstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVQstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] val := v.Args[1] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } break } // match: (MOVQstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_10(v *Value) bool { // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORQload || y.AuxInt != off || y.Aux != sym { break } _ = y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != y.Args[2] || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ADDQ { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64ADDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64SUBQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ANDQ { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64ANDQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64ORQ { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64ORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64XORQ { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := y.Args[_i0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { continue } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] { continue } x := y.Args[1^_i0] if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { continue } v.reset(OpAMD64XORQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(BTCQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTCQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTCQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTCQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(BTRQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTRQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTRQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTRQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVQstore {sym} [off] ptr y:(BTSQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTSQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] y := v.Args[1] if y.Op != OpAMD64BTSQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { break } v.reset(OpAMD64BTSQmodify) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore_20(v *Value) bool { // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ADDQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ADDQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ANDQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ANDQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ANDQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ORQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64ORQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64ORQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (XORQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64XORQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64XORQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(BTCQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTCQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTCQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTCQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(BTRQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTRQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTRQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTRQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr a:(BTSQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTSQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] a := v.Args[1] if a.Op != OpAMD64BTSQconst { break } c := a.AuxInt l := a.Args[0] if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { break } _ = l.Args[1] ptr2 := l.Args[0] if mem != l.Args[1] || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c, off) && clobber(l) && clobber(a)) { break } v.reset(OpAMD64BTSQconstmodify) v.AuxInt = makeValAndOff(c, off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) // result: (MOVSDstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQf2i { break } val := v_1.Args[0] v.reset(OpAMD64MOVSDstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconst_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVQstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconst [x] {sym1} (LEAQ8 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVQstoreconstidx8 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVQstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconst [c] {s} p x:(MOVQstoreconst [c2] {s} p mem)) // cond: config.useSSE && x.Uses == 1 && ValAndOff(c2).Off() + 8 == ValAndOff(c).Off() && ValAndOff(c).Val() == 0 && ValAndOff(c2).Val() == 0 && clobber(x) // result: (MOVOstore [ValAndOff(c2).Off()] {s} p (MOVOconst [0]) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVQstoreconst { break } c2 := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(config.useSSE && x.Uses == 1 && ValAndOff(c2).Off()+8 == ValAndOff(c).Off() && ValAndOff(c).Val() == 0 && ValAndOff(c2).Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = ValAndOff(c2).Off() v.Aux = s v.AddArg(p) v0 := b.NewValue0(x.Pos, OpAMD64MOVOconst, types.TypeInt128) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVQstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVQstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconstidx1_0(v *Value) bool { // match: (MOVQstoreconstidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVQstoreconstidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVQstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVQstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVQstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconstidx8_0(v *Value) bool { // match: (MOVQstoreconstidx8 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVQstoreconstidx8 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVQstoreconstidx8 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(8*c) // result: (MOVQstoreconstidx8 [ValAndOff(x).add(8*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(8 * c)) { break } v.reset(OpAMD64MOVQstoreconstidx8) v.AuxInt = ValAndOff(x).add(8 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreidx1_0(v *Value) bool { // match: (MOVQstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) // result: (MOVQstoreidx8 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVQstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVQstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVQstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreidx8_0(v *Value) bool { // match: (MOVQstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVQstoreidx8 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+8*d) // result: (MOVQstoreidx8 [c+8*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVQstoreidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVQstoreidx8 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+8*c) // result: (MOVQstore [i+8*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDload_0(v *Value) bool { // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDloadidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVSDloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVQi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDloadidx1_0(v *Value) bool { // match: (MOVSDloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVSDloadidx8 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSDloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVSDloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVSDload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDloadidx8_0(v *Value) bool { // match: (MOVSDloadidx8 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSDloadidx8 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx8 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+8*d) // result: (MOVSDloadidx8 [c+8*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVSDloadidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSDloadidx8 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+8*c) // result: (MOVSDload [i+8*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstore_0(v *Value) bool { // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSDstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ8 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVSDstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] val := v.Args[1] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } break } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQi2f { break } val := v_1.Args[0] v.reset(OpAMD64MOVQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstoreidx1_0(v *Value) bool { // match: (MOVSDstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) // result: (MOVSDstoreidx8 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSDstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVSDstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVSDstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstoreidx8_0(v *Value) bool { // match: (MOVSDstoreidx8 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSDstoreidx8 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx8 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+8*d) // result: (MOVSDstoreidx8 [c+8*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 8*d)) { break } v.reset(OpAMD64MOVSDstoreidx8) v.AuxInt = c + 8*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSDstoreidx8 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+8*c) // result: (MOVSDstore [i+8*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 8*c)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = i + 8*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSload_0(v *Value) bool { // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSloadidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVSSloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } val := v_1.Args[1] v.reset(OpAMD64MOVLi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSloadidx1_0(v *Value) bool { // match: (MOVSSloadidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) // result: (MOVSSloadidx4 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSSloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVSSloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVSSload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSloadidx4_0(v *Value) bool { // match: (MOVSSloadidx4 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVSSloadidx4 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx4 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+4*d) // result: (MOVSSloadidx4 [c+4*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVSSloadidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVSSloadidx4 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+4*c) // result: (MOVSSload [i+4*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstore_0(v *Value) bool { // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVSSstoreidx4 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ4 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVSSstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] val := v.Args[1] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } break } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLi2f { break } val := v_1.Args[0] v.reset(OpAMD64MOVLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstoreidx1_0(v *Value) bool { // match: (MOVSSstoreidx1 [c] {sym} ptr (SHLQconst [2] idx) val mem) // result: (MOVSSstoreidx4 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSSstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVSSstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVSSstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstoreidx4_0(v *Value) bool { // match: (MOVSSstoreidx4 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVSSstoreidx4 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx4 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+4*d) // result: (MOVSSstoreidx4 [c+4*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 4*d)) { break } v.reset(OpAMD64MOVSSstoreidx4) v.AuxInt = c + 4*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVSSstoreidx4 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+4*c) // result: (MOVSSstore [i+4*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 4*c)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = i + 4*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSX_0(v *Value) bool { b := v.Block // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0x7fff v.AddArg(x) return true } // match: (MOVWQSX (MOVWQSX x)) // result: (MOVWQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSX (MOVBQSX x)) // result: (MOVBQSX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSXload_0(v *Value) bool { // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQSX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWQSXload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQZX_0(v *Value) bool { b := v.Block // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVLload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpAMD64MOVQload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } // match: (MOVWQZX x) // cond: zeroUpper48Bits(x,3) // result: x for { x := v.Args[0] if !(zeroUpper48Bits(x, 3)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWQZX x:(MOVWloadidx1 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWloadidx1 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWloadidx1 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVWQZX x:(MOVWloadidx2 [off] {sym} ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWloadidx2 [off] {sym} ptr idx mem) for { x := v.Args[0] if x.Op != OpAMD64MOVWloadidx2 { break } off := x.AuxInt sym := x.Aux mem := x.Args[2] ptr := x.Args[0] idx := x.Args[1] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx2, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(idx) v0.AddArg(mem) return true } // match: (MOVWQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xffff] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ANDLconst { break } c := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = c & 0xffff v.AddArg(x) return true } // match: (MOVWQZX (MOVWQZX x)) // result: (MOVWQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWQZX (MOVBQZX x)) // result: (MOVBQZX x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWload_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQZX x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWstore { break } off2 := v_1.AuxInt sym2 := v_1.Aux _ = v_1.Args[2] ptr2 := v_1.Args[0] x := v_1.Args[1] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWloadidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWloadidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWloadidx2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (ADDQ ptr idx) mem) // cond: ptr.Op != OpSB // result: (MOVWloadidx1 [off] {sym} ptr idx mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym} (ADDLconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int64(read16(sym, off, config.BigEndian))]) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int64(read16(sym, off, config.BigEndian)) return true } return false } func rewriteValueAMD64_OpAMD64MOVWloadidx1_0(v *Value) bool { // match: (MOVWloadidx1 [c] {sym} ptr (SHLQconst [1] idx) mem) // result: (MOVWloadidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { continue } idx := v_1.Args[0] v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVWloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64ADDQconst { continue } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1^_i0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVWloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ADDQconst { continue } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + d)) { continue } v.reset(OpAMD64MOVWloadidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } break } // match: (MOVWloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) // result: (MOVWload [i+c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] for _i0 := 0; _i0 <= 1; _i0++ { p := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(i + c)) { continue } v.reset(OpAMD64MOVWload) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MOVWloadidx2_0(v *Value) bool { // match: (MOVWloadidx2 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) // result: (MOVWloadidx2 [c+d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx2 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+2*d) // result: (MOVWloadidx2 [c+2*d] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] if !(is32Bit(c + 2*d)) { break } v.reset(OpAMD64MOVWloadidx2) v.AuxInt = c + 2*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWloadidx2 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+2*c) // result: (MOVWload [i+2*c] {s} p mem) for { i := v.AuxInt s := v.Aux mem := v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(i + 2*c)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = i + 2*c v.Aux = s v.AddArg(p) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore_0(v *Value) bool { // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWQSX { break } x := v_1.Args[0] v.reset(OpAMD64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVWQZX { break } x := v_1.Args[0] v.reset(OpAMD64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // cond: validOff(off) // result: (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validOff(off) // result: (MOVWstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(validOff(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(int64(int16(c)), off) v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstoreidx1 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MOVWstoreidx2 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off2 := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} (ADDQ ptr idx) val mem) // cond: ptr.Op != OpSB // result: (MOVWstoreidx1 [off] {sym} ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { ptr := v_0.Args[_i0] idx := v_0.Args[1^_i0] val := v.Args[1] if !(ptr.Op != OpSB) { continue } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } break } // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst || v_1.AuxInt != 16 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst || v_1.AuxInt != 16 { break } w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRLconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHRQconst { break } j := v_1.AuxInt w := v_1.Args[0] x := v.Args[2] if x.Op != OpAMD64MOVWstore || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) for { i := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] x1 := v.Args[1] if x1.Op != OpAMD64MOVWload { break } j := x1.AuxInt s2 := x1.Aux mem := x1.Args[1] p2 := x1.Args[0] mem2 := v.Args[2] if mem2.Op != OpAMD64MOVWstore || mem2.AuxInt != i-2 || mem2.Aux != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVWload || x2.AuxInt != j-2 || x2.Aux != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x2.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = j - 2 v0.Aux = s2 v0.AddArg(p2) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym} (ADDLconst [off2] ptr) val mem) // cond: is32Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconst_0(v *Value) bool { // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym1} (LEAQ1 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ1 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym1} (LEAQ2 [off] {sym2} ptr idx) mem) // cond: canMergeSym(sym1, sym2) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(off)] {mergeSym(sym1,sym2)} ptr idx mem) for { x := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ2 { break } off := v_0.AuxInt sym2 := v_0.Aux idx := v_0.Args[1] ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [x] {sym} (ADDQ ptr idx) mem) // result: (MOVWstoreconstidx1 [x] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQ { break } idx := v_0.Args[1] ptr := v_0.Args[0] v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = x v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem) for { c := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVWstoreconst { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVWstoreconst [a] {s} p x:(MOVWstoreconst [c] {s} p mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconst [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p mem) for { a := v.AuxInt s := v.Aux _ = v.Args[1] p := v.Args[0] x := v.Args[1] if x.Op != OpAMD64MOVWstoreconst { break } c := x.AuxInt if x.Aux != s { break } mem := x.Args[1] if p != x.Args[0] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := v.AuxInt sym1 := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAL { break } off := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstoreconst [sc] {s} (ADDLconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd(off) // result: (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) for { sc := v.AuxInt s := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDLconst { break } off := v_0.AuxInt ptr := v_0.Args[0] if !(ValAndOff(sc).canAdd(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = ValAndOff(sc).add(off) v.Aux = s v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconstidx1_0(v *Value) bool { // match: (MOVWstoreconstidx1 [c] {sym} ptr (SHLQconst [1] idx) mem) // result: (MOVWstoreconstidx2 [c] {sym} ptr idx mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } idx := v_1.Args[0] v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVWstoreconstidx1 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVWstoreconstidx1) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx1 [c] {s} p i x:(MOVWstoreconstidx1 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p i mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVWstoreconstidx1 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v.AddArg(i) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconstidx2_0(v *Value) bool { b := v.Block // match: (MOVWstoreconstidx2 [x] {sym} (ADDQconst [c] ptr) idx mem) // cond: ValAndOff(x).canAdd(c) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] if !(ValAndOff(x).canAdd(c)) { break } v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx2 [x] {sym} ptr (ADDQconst [c] idx) mem) // cond: ValAndOff(x).canAdd(2*c) // result: (MOVWstoreconstidx2 [ValAndOff(x).add(2*c)] {sym} ptr idx mem) for { x := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt idx := v_1.Args[0] if !(ValAndOff(x).canAdd(2 * c)) { break } v.reset(OpAMD64MOVWstoreconstidx2) v.AuxInt = ValAndOff(x).add(2 * c) v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } // match: (MOVWstoreconstidx2 [c] {s} p i x:(MOVWstoreconstidx2 [a] {s} p i mem)) // cond: x.Uses == 1 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() && clobber(x) // result: (MOVLstoreconstidx1 [makeValAndOff(ValAndOff(a).Val()&0xffff | ValAndOff(c).Val()<<16, ValAndOff(a).Off())] {s} p (SHLQconst [1] i) mem) for { c := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] i := v.Args[1] x := v.Args[2] if x.Op != OpAMD64MOVWstoreconstidx2 { break } a := x.AuxInt if x.Aux != s { break } mem := x.Args[2] if p != x.Args[0] || i != x.Args[1] || !(x.Uses == 1 && ValAndOff(a).Off()+2 == ValAndOff(c).Off() && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconstidx1) v.AuxInt = makeValAndOff(ValAndOff(a).Val()&0xffff|ValAndOff(c).Val()<<16, ValAndOff(a).Off()) v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, i.Type) v0.AuxInt = 1 v0.AddArg(i) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreidx1_0(v *Value) bool { // match: (MOVWstoreidx1 [c] {sym} ptr (SHLQconst [1] idx) val mem) // result: (MOVWstoreidx2 [c] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { break } idx := v_1.Args[0] val := v.Args[2] v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = c v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVWstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+d) // result: (MOVWstoreidx1 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWstoreidx1) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRQconst [16] w) x:(MOVWstoreidx1 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRLconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRLconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p idx (SHRQconst [j] w) x:(MOVWstoreidx1 [i-2] {s} p idx w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p idx w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx1 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v.AddArg(idx) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx1 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+c) // result: (MOVWstore [i+c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + c)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i + c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreidx2_0(v *Value) bool { b := v.Block // match: (MOVWstoreidx2 [c] {sym} (ADDQconst [d] ptr) idx val mem) // cond: is32Bit(c+d) // result: (MOVWstoreidx2 [c+d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } d := v_0.AuxInt ptr := v_0.Args[0] idx := v.Args[1] val := v.Args[2] if !(is32Bit(c + d)) { break } v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = c + d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [c] {sym} ptr (ADDQconst [d] idx) val mem) // cond: is32Bit(c+2*d) // result: (MOVWstoreidx2 [c+2*d] {sym} ptr idx val mem) for { c := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } d := v_1.AuxInt idx := v_1.Args[0] val := v.Args[2] if !(is32Bit(c + 2*d)) { break } v.reset(OpAMD64MOVWstoreidx2) v.AuxInt = c + 2*d v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRLconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLQconst [1] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRLconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx2 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRQconst [16] w) x:(MOVWstoreidx2 [i-2] {s} p idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLQconst [1] idx) w mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst || v_2.AuxInt != 16 { break } w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx2 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p idx (SHRQconst [j] w) x:(MOVWstoreidx2 [i-2] {s} p idx w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstoreidx1 [i-2] {s} p (SHLQconst [1] idx) w0 mem) for { i := v.AuxInt s := v.Aux _ = v.Args[3] p := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SHRQconst { break } j := v_2.AuxInt w := v_2.Args[0] x := v.Args[3] if x.Op != OpAMD64MOVWstoreidx2 || x.AuxInt != i-2 || x.Aux != s { break } mem := x.Args[3] if p != x.Args[0] || idx != x.Args[1] { break } w0 := x.Args[2] if w0.Op != OpAMD64SHRQconst || w0.AuxInt != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstoreidx1) v.AuxInt = i - 2 v.Aux = s v.AddArg(p) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, idx.Type) v0.AuxInt = 1 v0.AddArg(idx) v.AddArg(v0) v.AddArg(w0) v.AddArg(mem) return true } // match: (MOVWstoreidx2 [i] {s} p (MOVQconst [c]) w mem) // cond: is32Bit(i+2*c) // result: (MOVWstore [i+2*c] {s} p w mem) for { i := v.AuxInt s := v.Aux mem := v.Args[3] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt w := v.Args[2] if !(is32Bit(i + 2*c)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = i + 2*c v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64MULL_0(v *Value) bool { // match: (MULL x (MOVLconst [c])) // result: (MULLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVLconst { continue } c := v_1.AuxInt v.reset(OpAMD64MULLconst) v.AuxInt = c v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULLconst_0(v *Value) bool { b := v.Block // match: (MULLconst [c] (MULLconst [d] x)) // result: (MULLconst [int64(int32(c * d))] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MULLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64MULLconst) v.AuxInt = int64(int32(c * d)) v.AddArg(x) return true } // match: (MULLconst [-9] x) // result: (NEGL (LEAL8 x x)) for { if v.AuxInt != -9 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // result: (NEGL (LEAL4 x x)) for { if v.AuxInt != -5 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // result: (NEGL (LEAL2 x x)) for { if v.AuxInt != -3 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // result: (NEGL x) for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } // match: (MULLconst [ 0] _) // result: (MOVLconst [0]) for { if v.AuxInt != 0 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (MULLconst [ 1] x) // result: x for { if v.AuxInt != 1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MULLconst [ 3] x) // result: (LEAL2 x x) for { if v.AuxInt != 3 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [ 5] x) // result: (LEAL4 x x) for { if v.AuxInt != 5 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [ 7] x) // result: (LEAL2 x (LEAL2 x x)) for { if v.AuxInt != 7 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_10(v *Value) bool { b := v.Block // match: (MULLconst [ 9] x) // result: (LEAL8 x x) for { if v.AuxInt != 9 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v.AddArg(x) return true } // match: (MULLconst [11] x) // result: (LEAL2 x (LEAL4 x x)) for { if v.AuxInt != 11 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [13] x) // result: (LEAL4 x (LEAL2 x x)) for { if v.AuxInt != 13 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [19] x) // result: (LEAL2 x (LEAL8 x x)) for { if v.AuxInt != 19 { break } x := v.Args[0] v.reset(OpAMD64LEAL2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [21] x) // result: (LEAL4 x (LEAL4 x x)) for { if v.AuxInt != 21 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [25] x) // result: (LEAL8 x (LEAL2 x x)) for { if v.AuxInt != 25 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [27] x) // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if v.AuxInt != 27 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULLconst [37] x) // result: (LEAL4 x (LEAL8 x x)) for { if v.AuxInt != 37 { break } x := v.Args[0] v.reset(OpAMD64LEAL4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [41] x) // result: (LEAL8 x (LEAL4 x x)) for { if v.AuxInt != 41 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [45] x) // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if v.AuxInt != 45 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_20(v *Value) bool { b := v.Block // match: (MULLconst [73] x) // result: (LEAL8 x (LEAL8 x x)) for { if v.AuxInt != 73 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [81] x) // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if v.AuxInt != 81 { break } x := v.Args[0] v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c+1) && c >= 15 // result: (SUBL (SHLLconst [log2(c+1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c+1) && c >= 15) { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c + 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [log2(c-1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-1) && c >= 17) { break } v.reset(OpAMD64LEAL1) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [log2(c-2)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-2) && c >= 34) { break } v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 2) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [log2(c-4)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-4) && c >= 68) { break } v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 4) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [log2(c-8)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-8) && c >= 136) { break } v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = log2(c - 8) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo(c/3) // result: (SHLLconst [log2(c/3)] (LEAL2 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%3 == 0 && isPowerOfTwo(c/3)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = log2(c / 3) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo(c/5) // result: (SHLLconst [log2(c/5)] (LEAL4 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%5 == 0 && isPowerOfTwo(c/5)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = log2(c / 5) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo(c/9) // result: (SHLLconst [log2(c/9)] (LEAL8 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%9 == 0 && isPowerOfTwo(c/9)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = log2(c / 9) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULLconst_30(v *Value) bool { // match: (MULLconst [c] (MOVLconst [d])) // result: (MOVLconst [int64(int32(c*d))]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = int64(int32(c * d)) return true } return false } func rewriteValueAMD64_OpAMD64MULQ_0(v *Value) bool { // match: (MULQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (MULQconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64MULQconst) v.AuxInt = c v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULQconst_0(v *Value) bool { b := v.Block // match: (MULQconst [c] (MULQconst [d] x)) // cond: is32Bit(c*d) // result: (MULQconst [c * d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MULQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c * d)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = c * d v.AddArg(x) return true } // match: (MULQconst [-9] x) // result: (NEGQ (LEAQ8 x x)) for { if v.AuxInt != -9 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [-5] x) // result: (NEGQ (LEAQ4 x x)) for { if v.AuxInt != -5 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [-3] x) // result: (NEGQ (LEAQ2 x x)) for { if v.AuxInt != -3 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [-1] x) // result: (NEGQ x) for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(OpAMD64NEGQ) v.AddArg(x) return true } // match: (MULQconst [ 0] _) // result: (MOVQconst [0]) for { if v.AuxInt != 0 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (MULQconst [ 1] x) // result: x for { if v.AuxInt != 1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MULQconst [ 3] x) // result: (LEAQ2 x x) for { if v.AuxInt != 3 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v.AddArg(x) return true } // match: (MULQconst [ 5] x) // result: (LEAQ4 x x) for { if v.AuxInt != 5 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v.AddArg(x) return true } // match: (MULQconst [ 7] x) // result: (LEAQ2 x (LEAQ2 x x)) for { if v.AuxInt != 7 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_10(v *Value) bool { b := v.Block // match: (MULQconst [ 9] x) // result: (LEAQ8 x x) for { if v.AuxInt != 9 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v.AddArg(x) return true } // match: (MULQconst [11] x) // result: (LEAQ2 x (LEAQ4 x x)) for { if v.AuxInt != 11 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [13] x) // result: (LEAQ4 x (LEAQ2 x x)) for { if v.AuxInt != 13 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [19] x) // result: (LEAQ2 x (LEAQ8 x x)) for { if v.AuxInt != 19 { break } x := v.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [21] x) // result: (LEAQ4 x (LEAQ4 x x)) for { if v.AuxInt != 21 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [25] x) // result: (LEAQ8 x (LEAQ2 x x)) for { if v.AuxInt != 25 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [27] x) // result: (LEAQ8 (LEAQ2 x x) (LEAQ2 x x)) for { if v.AuxInt != 27 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULQconst [37] x) // result: (LEAQ4 x (LEAQ8 x x)) for { if v.AuxInt != 37 { break } x := v.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [41] x) // result: (LEAQ8 x (LEAQ4 x x)) for { if v.AuxInt != 41 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [45] x) // result: (LEAQ8 (LEAQ4 x x) (LEAQ4 x x)) for { if v.AuxInt != 45 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_20(v *Value) bool { b := v.Block // match: (MULQconst [73] x) // result: (LEAQ8 x (LEAQ8 x x)) for { if v.AuxInt != 73 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [81] x) // result: (LEAQ8 (LEAQ8 x x) (LEAQ8 x x)) for { if v.AuxInt != 81 { break } x := v.Args[0] v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v1.AddArg(x) v1.AddArg(x) v.AddArg(v1) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c+1) && c >= 15 // result: (SUBQ (SHLQconst [log2(c+1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c+1) && c >= 15) { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c + 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-1) && c >= 17 // result: (LEAQ1 (SHLQconst [log2(c-1)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-1) && c >= 17) { break } v.reset(OpAMD64LEAQ1) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 1) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-2) && c >= 34 // result: (LEAQ2 (SHLQconst [log2(c-2)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-2) && c >= 34) { break } v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 2) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-4) && c >= 68 // result: (LEAQ4 (SHLQconst [log2(c-4)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-4) && c >= 68) { break } v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 4) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo(c-8) && c >= 136 // result: (LEAQ8 (SHLQconst [log2(c-8)] x) x) for { c := v.AuxInt x := v.Args[0] if !(isPowerOfTwo(c-8) && c >= 136) { break } v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = log2(c - 8) v0.AddArg(x) v.AddArg(v0) v.AddArg(x) return true } // match: (MULQconst [c] x) // cond: c%3 == 0 && isPowerOfTwo(c/3) // result: (SHLQconst [log2(c/3)] (LEAQ2 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%3 == 0 && isPowerOfTwo(c/3)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = log2(c / 3) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%5 == 0 && isPowerOfTwo(c/5) // result: (SHLQconst [log2(c/5)] (LEAQ4 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%5 == 0 && isPowerOfTwo(c/5)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = log2(c / 5) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%9 == 0 && isPowerOfTwo(c/9) // result: (SHLQconst [log2(c/9)] (LEAQ8 x x)) for { c := v.AuxInt x := v.Args[0] if !(c%9 == 0 && isPowerOfTwo(c/9)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = log2(c / 9) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg(x) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULQconst_30(v *Value) bool { // match: (MULQconst [c] (MOVQconst [d])) // result: (MOVQconst [c*d]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = c * d return true } // match: (MULQconst [c] (NEGQ x)) // cond: c != -(1<<31) // result: (MULQconst [-c] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = -c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULSD_0(v *Value) bool { // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVSDload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSDload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (MULSD x (MOVQi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVQstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64MULSD) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64MULSS_0(v *Value) bool { // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVSSload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSSload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (MULSS x (MOVLi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVLstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64MULSS) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64NEGL_0(v *Value) bool { // match: (NEGL (NEGL x)) // result: x for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGL { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (NEGL s:(SUBL x y)) // cond: s.Uses == 1 // result: (SUBL y x) for { s := v.Args[0] if s.Op != OpAMD64SUBL { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBL) v.AddArg(y) v.AddArg(x) return true } // match: (NEGL (MOVLconst [c])) // result: (MOVLconst [int64(int32(-c))]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = int64(int32(-c)) return true } return false } func rewriteValueAMD64_OpAMD64NEGQ_0(v *Value) bool { // match: (NEGQ (NEGQ x)) // result: x for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (NEGQ s:(SUBQ x y)) // cond: s.Uses == 1 // result: (SUBQ y x) for { s := v.Args[0] if s.Op != OpAMD64SUBQ { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBQ) v.AddArg(y) v.AddArg(x) return true } // match: (NEGQ (MOVQconst [c])) // result: (MOVQconst [-c]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = -c return true } // match: (NEGQ (ADDQconst [c] (NEGQ x))) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } x := v_0_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = -c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64NOTL_0(v *Value) bool { // match: (NOTL (MOVLconst [c])) // result: (MOVLconst [^c]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = ^c return true } return false } func rewriteValueAMD64_OpAMD64NOTQ_0(v *Value) bool { // match: (NOTQ (MOVQconst [c])) // result: (MOVQconst [^c]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = ^c return true } return false } func rewriteValueAMD64_OpAMD64ORL_0(v *Value) bool { // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { continue } x := v.Args[1^_i0] v.reset(OpAMD64BTSL) v.AddArg(x) v.AddArg(y) return true } break } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSLconst [log2uint32(c)] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVLconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } break } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVLconst { continue } c := v_1.AuxInt v.reset(OpAMD64ORLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRLconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRWconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRBconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLL) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (RORL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRL { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHLL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (RORL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRL { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHLL { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORL) v.AddArg(x) v.AddArg(y) return true } } break } return false } func rewriteValueAMD64_OpAMD64ORL_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRW { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -16 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -16 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64ROLW) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHRW x (ANDQconst y [15])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg(x) v.AddArg(y) return true } break } // match: (ORL (SHRW x (ANDLconst y [15])) (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -16 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { continue } v.reset(OpAMD64RORW) v.AddArg(x) v.AddArg(y) return true } break } // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDL { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRB { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL { continue } v_1_0_1_0 := v_1_0_1.Args[0] if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -8 { continue } v_1_0_1_0_0 := v_1_0_1_0.Args[0] if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBLcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -8 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64ROLB) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg(x) v.AddArg(y) return true } break } // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRB { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHLL { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGL { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -8 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { continue } v.reset(OpAMD64RORB) v.AddArg(x) v.AddArg(y) return true } break } // match: (ORL x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ORL x0:(MOVBload [i0] {s} p mem) sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORL_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVWload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpAMD64SHLLconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1^_i0] if or.Op != OpAMD64ORL { continue } _ = or.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s0 := or.Args[_i1] if s0.Op != OpAMD64SHLLconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or.Args[1^_i1] if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } break } // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } } } break } // match: (ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVWloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } } } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpAMD64SHLLconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] or := v.Args[1^_i0] if or.Op != OpAMD64ORL { continue } _ = or.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s0 := or.Args[_i2] if s0.Op != OpAMD64SHLLconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i3 := 0; _i3 <= 1; _i3++ { if p != x0.Args[_i3] || idx != x0.Args[1^_i3] || mem != x0.Args[2] { continue } y := or.Args[1^_i2] if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } } } break } // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x1 := v.Args[_i0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { r1 := v.Args[_i0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpAMD64SHLLconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1^_i0] if or.Op != OpAMD64ORL { continue } _ = or.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s1 := or.Args[_i1] if s1.Op != OpAMD64SHLLconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or.Args[1^_i1] if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } break } // match: (ORL x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x1 := v.Args[_i0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } } } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { r1 := v.Args[_i0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } } } break } return false } func rewriteValueAMD64_OpAMD64ORL_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpAMD64SHLLconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] or := v.Args[1^_i0] if or.Op != OpAMD64ORL { continue } _ = or.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s1 := or.Args[_i2] if s1.Op != OpAMD64SHLLconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i3 := 0; _i3 <= 1; _i3++ { if p != x1.Args[_i3] || idx != x1.Args[1^_i3] || mem != x1.Args[2] { continue } y := or.Args[1^_i2] if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } } } break } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVLload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORLconst_0(v *Value) bool { // match: (ORLconst [c] x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSLconst [log2uint32(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (ORLconst [c] (ORLconst [d] x)) // result: (ORLconst [c | d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ORLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ORLconst) v.AuxInt = c | d v.AddArg(x) return true } // match: (ORLconst [c] (BTSLconst [d] x)) // result: (ORLconst [c | 1<= 128 // result: (BTSQconst [log2(c)] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVQconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSQconst) v.AuxInt = log2(c) v.AddArg(x) return true } break } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64ORQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLQconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRQconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLQ { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLQ { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHRQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64ROLQ) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRQ { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHLQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGQ { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHRQ { continue } y := v_0.Args[1] x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64ANDQ { continue } _ = v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { v_1_0 := v_1.Args[_i1] if v_1_0.Op != OpAMD64SHLQ { continue } _ = v_1_0.Args[1] if x != v_1_0.Args[0] { continue } v_1_0_1 := v_1_0.Args[1] if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { continue } v_1_1 := v_1.Args[1^_i1] if v_1_1.Op != OpAMD64SBBQcarrymask { continue } v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { continue } v_1_1_0_0 := v_1_1_0.Args[0] if v_1_1_0_0.Op != OpAMD64NEGL { continue } v_1_1_0_0_0 := v_1_1_0_0.Args[0] if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { continue } v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { continue } v.reset(OpAMD64RORQ) v.AddArg(x) v.AddArg(y) return true } } break } // match: (ORQ x x) // result: x for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ORQ x0:(MOVBload [i0] {s} p mem) sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQ_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVWload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } break } // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVLload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s0 := or.Args[_i1] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or.Args[1^_i1] if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s0 := or.Args[_i1] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or.Args[1^_i1] if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } break } // match: (ORQ x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } } } break } // match: (ORQ x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVWloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } } } break } // match: (ORQ x0:(MOVLloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpAMD64MOVLloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(idx) v0.AddArg(mem) return true } } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s0 := or.Args[_i2] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i3 := 0; _i3 <= 1; _i3++ { if p != x0.Args[_i3] || idx != x0.Args[1^_i3] || mem != x0.Args[2] { continue } y := or.Args[1^_i2] if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s0 := or.Args[_i2] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i3 := 0; _i3 <= 1; _i3++ { if p != x0.Args[_i3] || idx != x0.Args[1^_i3] || mem != x0.Args[2] { continue } y := or.Args[1^_i2] if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j0 v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v2.AddArg(idx) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } } } break } // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x1 := v.Args[_i0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQ_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { r1 := v.Args[_i0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { r1 := v.Args[_i0] if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(mem) v0.AddArg(v1) return true } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s1 := or.Args[_i1] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or.Args[1^_i1] if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s1 := or.Args[_i1] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or.Args[1^_i1] if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } break } // match: (ORQ x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x1 := v.Args[_i0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 8 v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } } } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { r1 := v.Args[_i0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } } } break } // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { r1 := v.Args[_i0] if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLloadidx1 { continue } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x1.Args[_i1] idx := x1.Args[1^_i1] sh := v.Args[1^_i0] if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLloadidx1 { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[2] for _i2 := 0; _i2 <= 1; _i2++ { if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v1.AddArg(idx) v1.AddArg(mem) v0.AddArg(v1) return true } } } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpAMD64MOVBloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s1 := or.Args[_i2] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpAMD64MOVBloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i3 := 0; _i3 <= 1; _i3++ { if p != x1.Args[_i3] || idx != x1.Args[1^_i3] || mem != x1.Args[2] { continue } y := or.Args[1^_i2] if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = 8 v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpAMD64SHLQconst { continue } j0 := s0.AuxInt r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWloadidx1 { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[2] for _i1 := 0; _i1 <= 1; _i1++ { p := x0.Args[_i1] idx := x0.Args[1^_i1] or := v.Args[1^_i0] if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s1 := or.Args[_i2] if s1.Op != OpAMD64SHLQconst { continue } j1 := s1.AuxInt r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWloadidx1 { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[2] for _i3 := 0; _i3 <= 1; _i3++ { if p != x1.Args[_i3] || idx != x1.Args[1^_i3] || mem != x1.Args[2] { continue } y := or.Args[1^_i2] if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = j1 v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) v3.AuxInt = i0 v3.Aux = s v3.AddArg(p) v3.AddArg(idx) v3.AddArg(mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v0.AddArg(y) return true } } } } break } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVQload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQconst_0(v *Value) bool { // match: (ORQconst [c] x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSQconst [log2(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (ORQconst [c] (ORQconst [d] x)) // result: (ORQconst [c | d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64ORQconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64ORQconst) v.AuxInt = c | d v.AddArg(x) return true } // match: (ORQconst [c] (BTSQconst [d] x)) // result: (ORQconst [c | 1<>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = int64(int8(d)) >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SARL_0(v *Value) bool { b := v.Block // match: (SARL x (MOVQconst [c])) // result: (SARLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SARLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SARL x (MOVLconst [c])) // result: (SARLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SARLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SARL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } // match: (SARL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARLconst_0(v *Value) bool { // match: (SARLconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARLconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int32(d))>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = int64(int32(d)) >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SARQ_0(v *Value) bool { b := v.Block // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SARQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SARQ x (MOVLconst [c])) // result: (SARQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SARQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SARQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SARQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } // match: (SARQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARQconst_0(v *Value) bool { // match: (SARQconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARQconst [c] (MOVQconst [d])) // result: (MOVQconst [d>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = d >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SARW_0(v *Value) bool { // match: (SARW x (MOVQconst [c])) // result: (SARWconst [min(c&31,15)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SARWconst) v.AuxInt = min(c&31, 15) v.AddArg(x) return true } // match: (SARW x (MOVLconst [c])) // result: (SARWconst [min(c&31,15)] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SARWconst) v.AuxInt = min(c&31, 15) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SARWconst_0(v *Value) bool { // match: (SARWconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SARWconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int16(d))>>uint64(c)]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = int64(int16(d)) >> uint64(c) return true } return false } func rewriteValueAMD64_OpAMD64SBBLcarrymask_0(v *Value) bool { // match: (SBBLcarrymask (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SBBLcarrymask (FlagLT_ULT)) // result: (MOVLconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = -1 return true } // match: (SBBLcarrymask (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SBBLcarrymask (FlagGT_ULT)) // result: (MOVLconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = -1 return true } // match: (SBBLcarrymask (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SBBQ_0(v *Value) bool { // match: (SBBQ x (MOVQconst [c]) borrow) // cond: is32Bit(c) // result: (SBBQconst x [c] borrow) for { borrow := v.Args[2] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64SBBQconst) v.AuxInt = c v.AddArg(x) v.AddArg(borrow) return true } // match: (SBBQ x y (FlagEQ)) // result: (SUBQborrow x y) for { _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQborrow) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpAMD64SBBQcarrymask_0(v *Value) bool { // match: (SBBQcarrymask (FlagEQ)) // result: (MOVQconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (SBBQcarrymask (FlagLT_ULT)) // result: (MOVQconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = -1 return true } // match: (SBBQcarrymask (FlagLT_UGT)) // result: (MOVQconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (SBBQcarrymask (FlagGT_ULT)) // result: (MOVQconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = -1 return true } // match: (SBBQcarrymask (FlagGT_UGT)) // result: (MOVQconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SBBQconst_0(v *Value) bool { // match: (SBBQconst x [c] (FlagEQ)) // result: (SUBQconstborrow x [c]) for { c := v.AuxInt _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SETA_0(v *Value) bool { // match: (SETA (InvertFlags x)) // result: (SETB x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETA (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETA (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETAE_0(v *Value) bool { // match: (SETAE (InvertFlags x)) // result: (SETBE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETAE (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETAE (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETAE (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETAE (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETAEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETBEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETAEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETAstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETAstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETB_0(v *Value) bool { // match: (SETB (InvertFlags x)) // result: (SETA x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETB (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETB (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETB (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETB (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETBE_0(v *Value) bool { // match: (SETBE (InvertFlags x)) // result: (SETAE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETBE (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETBE (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETBEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETBEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETBstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETAstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETBstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ_0(v *Value) bool { b := v.Block // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (SETAE (BTLconst [log2uint32(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64MOVQconst { continue } c := v_0_0.AuxInt x := v_0.Args[1^_i0] if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPLconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETNE (CMPQconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPQconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } break } return false } func rewriteValueAMD64_OpAMD64SETEQ_10(v *Value) bool { b := v.Block // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETEQ (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETEQ (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore_0(v *Value) bool { b := v.Block // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_1_0 := v_1.Args[_i0] if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { continue } y := v_1.Args[1^_i0] v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_1_0 := v_1.Args[_i0] if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { continue } y := v_1.Args[1^_i0] v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTLconst [log2uint32(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTLconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_1_0 := v_1.Args[_i0] if v_1_0.Op != OpAMD64MOVQconst { continue } c := v_1_0.AuxInt x := v_1.Args[1^_i0] if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPLconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPQconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64SETEQstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } x := z1.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } x := z1.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETEQstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQstore_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETG_0(v *Value) bool { // match: (SETG (InvertFlags x)) // result: (SETL x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETG (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETG (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETGE_0(v *Value) bool { // match: (SETGE (InvertFlags x)) // result: (SETLE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETGE (FlagLT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETGE (FlagLT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETGE (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETGE (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETGEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETLEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETGEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETGstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETLstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETGstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETL_0(v *Value) bool { // match: (SETL (InvertFlags x)) // result: (SETG x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETL (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETL (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETL (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETL (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETLE_0(v *Value) bool { // match: (SETLE (InvertFlags x)) // result: (SETGE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETLE (FlagGT_ULT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETLE (FlagGT_UGT)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SETLEstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETGEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETLEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETLstore_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETGstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETLstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNE_0(v *Value) bool { b := v.Block // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } break } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (SETB (BTLconst [log2uint32(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTLconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64MOVQconst { continue } c := v_0_0.AuxInt x := v_0.Args[1^_i0] if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPLconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETEQ (CMPQconst [0] s)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64CMPQconst || v_0.AuxInt != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } break } return false } func rewriteValueAMD64_OpAMD64SETNE_10(v *Value) bool { b := v.Block // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (InvertFlags x)) // result: (SETNE x) for { v_0 := v.Args[0] if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // result: (MOVLconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SETNE (FlagLT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagLT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagGT_ULT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } // match: (SETNE (FlagGT_UGT)) // result: (MOVLconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 1 return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore_0(v *Value) bool { b := v.Block // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_1_0 := v_1.Args[_i0] if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { continue } y := v_1.Args[1^_i0] v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_1_0 := v_1.Args[_i0] if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { continue } y := v_1.Args[1^_i0] v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTLconst [log2uint32(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTLconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint32PowerOfTwo(c)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQconst { break } c := v_1.AuxInt x := v_1.Args[0] if !(isUint64PowerOfTwo(c)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_1_0 := v_1.Args[_i0] if v_1_0.Op != OpAMD64MOVQconst { continue } c := v_1_0.AuxInt x := v_1.Args[1^_i0] if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPLconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64CMPQconst || v_1.AuxInt != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || s.AuxInt != 1 { break } v.reset(OpAMD64SETEQstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(s) v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64SETNEstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } x := z1.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_1.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } x := z1.Args[0] z2 := v_1.Args[1^_i0] if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } break } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] v.reset(OpAMD64SETNEstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SETNEstore [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNEstore_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLL_0(v *Value) bool { b := v.Block // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHLL x (MOVLconst [c])) // result: (SHLLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHLL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } // match: (SHLL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLLconst_0(v *Value) bool { // match: (SHLLconst [1] (SHRLconst [1] x)) // result: (BTRLconst [0] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHRLconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = 0 v.AddArg(x) return true } // match: (SHLLconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHLQ_0(v *Value) bool { b := v.Block // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHLQ x (MOVLconst [c])) // result: (SHLQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHLQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHLQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHLQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHLQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLQconst_0(v *Value) bool { // match: (SHLQconst [1] (SHRQconst [1] x)) // result: (BTRQconst [0] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHRQconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = 0 v.AddArg(x) return true } // match: (SHLQconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRB_0(v *Value) bool { // match: (SHRB x (MOVQconst [c])) // cond: c&31 < 8 // result: (SHRBconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRB _ (MOVQconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SHRBconst_0(v *Value) bool { // match: (SHRBconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRL_0(v *Value) bool { b := v.Block // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRL x (MOVLconst [c])) // result: (SHRLconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRLconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } // match: (SHRL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRLconst_0(v *Value) bool { // match: (SHRLconst [1] (SHLLconst [1] x)) // result: (BTRLconst [31] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = 31 v.AddArg(x) return true } // match: (SHRLconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRQ_0(v *Value) bool { b := v.Block // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHRQ x (MOVLconst [c])) // result: (SHRQconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SHRQconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (SHRQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDQconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGQ y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } // match: (SHRQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ANDLconst { break } c := v_1.AuxInt y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } // match: (SHRQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGL y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := v_1_0.AuxInt y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRQconst_0(v *Value) bool { // match: (SHRQconst [1] (SHLQconst [1] x)) // result: (BTRQconst [63] x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = 63 v.AddArg(x) return true } // match: (SHRQconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRW_0(v *Value) bool { // match: (SHRW x (MOVQconst [c])) // cond: c&31 < 16 // result: (SHRWconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (SHRW _ (MOVQconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } return false } func rewriteValueAMD64_OpAMD64SHRWconst_0(v *Value) bool { // match: (SHRWconst x [0]) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBL_0(v *Value) bool { b := v.Block // match: (SUBL x (MOVLconst [c])) // result: (SUBLconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVLconst { break } c := v_1.AuxInt v.reset(OpAMD64SUBLconst) v.AuxInt = c v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // result: (NEGL (SUBLconst x [c])) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVLconst { break } c := v_0.AuxInt v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x x) // result: (MOVLconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVLload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBLconst_0(v *Value) bool { // match: (SUBLconst [c] x) // cond: int32(c) == 0 // result: x for { c := v.AuxInt x := v.Args[0] if !(int32(c) == 0) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SUBLconst [c] x) // result: (ADDLconst [int64(int32(-c))] x) for { c := v.AuxInt x := v.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int64(int32(-c)) v.AddArg(x) return true } } func rewriteValueAMD64_OpAMD64SUBLload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (SUBL x (MOVLf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSSstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBL) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBLmodify_0(v *Value) bool { // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQ_0(v *Value) bool { b := v.Block // match: (SUBQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconst) v.AuxInt = c v.AddArg(x) return true } // match: (SUBQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (NEGQ (SUBQconst x [c])) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBQ x x) // result: (MOVQconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBQload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVQload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQborrow_0(v *Value) bool { // match: (SUBQborrow x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconstborrow x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64MOVQconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQconst_0(v *Value) bool { // match: (SUBQconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (SUBQconst [c] x) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { c := v.AuxInt x := v.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = -c v.AddArg(x) return true } // match: (SUBQconst (MOVQconst [d]) [c]) // result: (MOVQconst [d-c]) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64MOVQconst { break } d := v_0.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = d - c return true } // match: (SUBQconst (SUBQconst x [d]) [c]) // cond: is32Bit(-c-d) // result: (ADDQconst [-c-d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64SUBQconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(-c - d)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = -c - d v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBQload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (SUBQ x (MOVQf2i y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVSDstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBQ) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBQmodify_0(v *Value) bool { // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(off1+off2) // result: (SUBQmodify [off1+off2] {sym} base val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64ADDQconst { break } off2 := v_0.AuxInt base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpAMD64LEAQ { break } off2 := v_0.AuxInt sym2 := v_0.Aux base := v_0.Args[0] val := v.Args[1] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(base) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSD_0(v *Value) bool { // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSDload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSDload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (SUBSD x (MOVQi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVQstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBSD) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBSS_0(v *Value) bool { // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { _ = v.Args[1] x := v.Args[0] l := v.Args[1] if l.Op != OpAMD64MOVSSload { break } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSSload_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(off1+off2) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt base := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux base := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(base) v.AddArg(mem) return true } // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (SUBSS x (MOVLi2f y)) for { off := v.AuxInt sym := v.Aux _ = v.Args[2] x := v.Args[0] ptr := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64MOVLstore || v_2.AuxInt != off || v_2.Aux != sym { break } _ = v_2.Args[2] if ptr != v_2.Args[0] { break } y := v_2.Args[1] v.reset(OpAMD64SUBSS) v.AddArg(x) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64TESTB_0(v *Value) bool { b := v.Block // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVLconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] v.reset(OpAMD64TESTBconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := v.Args[_i0] if l.Op != OpAMD64MOVBload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] l2 := v.Args[1^_i0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTBconst_0(v *Value) bool { // match: (TESTBconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTB x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTB) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64TESTL_0(v *Value) bool { b := v.Block // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVLconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] v.reset(OpAMD64TESTLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := v.Args[_i0] if l.Op != OpAMD64MOVLload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] l2 := v.Args[1^_i0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTLconst_0(v *Value) bool { // match: (TESTLconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTL x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTL) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64TESTQ_0(v *Value) bool { b := v.Block // match: (TESTQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (TESTQconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVQconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(is32Bit(c)) { continue } v.reset(OpAMD64TESTQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := v.Args[_i0] if l.Op != OpAMD64MOVQload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] l2 := v.Args[1^_i0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTQconst_0(v *Value) bool { // match: (TESTQconst [-1] x) // cond: x.Op != OpAMD64MOVQconst // result: (TESTQ x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVQconst) { break } v.reset(OpAMD64TESTQ) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64TESTW_0(v *Value) bool { b := v.Block // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVLconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] v.reset(OpAMD64TESTWconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { l := v.Args[_i0] if l.Op != OpAMD64MOVWload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] l2 := v.Args[1^_i0] if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = makeValAndOff(0, off) v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTWconst_0(v *Value) bool { // match: (TESTWconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTW x x) for { if v.AuxInt != -1 { break } x := v.Args[0] if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTW) v.AddArg(x) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64XADDLlock_0(v *Value) bool { // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XADDLlock [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XADDLlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XADDQlock_0(v *Value) bool { // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XADDQlock [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XADDQlock) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGL_0(v *Value) bool { // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XCHGL [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XCHGL) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux ptr := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGL) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGQ_0(v *Value) bool { // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(off1+off2) // result: (XCHGQ [off1+off2] {sym} val ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64ADDQconst { break } off2 := v_1.AuxInt ptr := v_1.Args[0] if !(is32Bit(off1 + off2)) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] val := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpAMD64LEAQ { break } off2 := v_1.AuxInt sym2 := v_1.Aux ptr := v_1.Args[0] if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(val) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpAMD64XORL_0(v *Value) bool { // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { continue } x := v.Args[1^_i0] v.reset(OpAMD64BTCL) v.AddArg(x) v.AddArg(y) return true } break } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCLconst [log2uint32(c)] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVLconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } break } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVLconst { continue } c := v_1.AuxInt v.reset(OpAMD64XORLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRLconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpAMD64ROLLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 // result: (ROLWconst x [c]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRWconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { continue } v.reset(OpAMD64ROLWconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLLconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRBconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { continue } v.reset(OpAMD64ROLBconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XORL x x) // result: (MOVLconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVLconst) v.AuxInt = 0 return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVLload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORLload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64XORLconst_0(v *Value) bool { // match: (XORLconst [c] x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCLconst [log2uint32(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = log2uint32(c) v.AddArg(x) return true } // match: (XORLconst [1] (SETNE x)) // result: (SETEQ x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETNE { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (XORLconst [1] (SETEQ x)) // result: (SETNE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETEQ { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (XORLconst [1] (SETL x)) // result: (SETGE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETL { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (XORLconst [1] (SETGE x)) // result: (SETL x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETGE { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (XORLconst [1] (SETLE x)) // result: (SETG x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETLE { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (XORLconst [1] (SETG x)) // result: (SETLE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETG { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (XORLconst [1] (SETB x)) // result: (SETAE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETB { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (XORLconst [1] (SETAE x)) // result: (SETB x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETAE { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (XORLconst [1] (SETBE x)) // result: (SETA x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETBE { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64XORLconst_10(v *Value) bool { // match: (XORLconst [1] (SETA x)) // result: (SETBE x) for { if v.AuxInt != 1 { break } v_0 := v.Args[0] if v_0.Op != OpAMD64SETA { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (XORLconst [c] (XORLconst [d] x)) // result: (XORLconst [c ^ d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64XORLconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORLconst [c] (BTCLconst [d] x)) // result: (XORLconst [c ^ 1<= 128 // result: (BTCQconst [log2(c)] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64MOVQconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCQconst) v.AuxInt = log2(c) v.AddArg(x) return true } break } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64MOVQconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpAMD64XORQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpAMD64SHLQconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpAMD64SHRQconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpAMD64ROLQconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XORQ x x) // result: (MOVQconst [0]) for { x := v.Args[1] if x != v.Args[0] { break } v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] l := v.Args[1^_i0] if l.Op != OpAMD64MOVQload { continue } off := l.AuxInt sym := l.Aux mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORQload) v.AuxInt = off v.Aux = sym v.AddArg(x) v.AddArg(ptr) v.AddArg(mem) return true } break } return false } func rewriteValueAMD64_OpAMD64XORQconst_0(v *Value) bool { // match: (XORQconst [c] x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCQconst [log2(c)] x) for { c := v.AuxInt x := v.Args[0] if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = log2(c) v.AddArg(x) return true } // match: (XORQconst [c] (XORQconst [d] x)) // result: (XORQconst [c ^ d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpAMD64XORQconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpAMD64XORQconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORQconst [c] (BTCQconst [d] x)) // result: (XORQconst [c ^ 1< val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore64 ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore8 ptr val mem) // result: (Select1 (XCHGB val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStorePtrNoWB_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (AtomicStorePtrNoWB ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) v0.AddArg(val) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAvg64u_0(v *Value) bool { // match: (Avg64u x y) // result: (AVGQU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64AVGQU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpBitLen16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen16 x) // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) for { x := v.Args[0] v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = 1 v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v2.AddArg(x) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) for { x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) v1.AuxInt = 1 v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v2.AddArg(x) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v3.AddArg(x) v1.AddArg(v3) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) for { t := v.Type x := v.Args[0] v.reset(OpAMD64ADDQconst) v.AuxInt = 1 v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) v1 := b.NewValue0(v.Pos, OpSelect0, t) v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v3.AuxInt = -1 v0.AddArg(v3) v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v5 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v5.AddArg(x) v4.AddArg(v5) v0.AddArg(v4) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen8 x) // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) for { x := v.Args[0] v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = 1 v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v2.AddArg(x) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBswap32_0(v *Value) bool { // match: (Bswap32 x) // result: (BSWAPL x) for { x := v.Args[0] v.reset(OpAMD64BSWAPL) v.AddArg(x) return true } } func rewriteValueAMD64_OpBswap64_0(v *Value) bool { // match: (Bswap64 x) // result: (BSWAPQ x) for { x := v.Args[0] v.reset(OpAMD64BSWAPQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCeil_0(v *Value) bool { // match: (Ceil x) // result: (ROUNDSD [2] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 2 v.AddArg(x) return true } } func rewriteValueAMD64_OpClosureCall_0(v *Value) bool { // match: (ClosureCall [argwid] entry closure mem) // result: (CALLclosure [argwid] entry closure mem) for { argwid := v.AuxInt mem := v.Args[2] entry := v.Args[0] closure := v.Args[1] v.reset(OpAMD64CALLclosure) v.AuxInt = argwid v.AddArg(entry) v.AddArg(closure) v.AddArg(mem) return true } } func rewriteValueAMD64_OpCom16_0(v *Value) bool { // match: (Com16 x) // result: (NOTL x) for { x := v.Args[0] v.reset(OpAMD64NOTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCom32_0(v *Value) bool { // match: (Com32 x) // result: (NOTL x) for { x := v.Args[0] v.reset(OpAMD64NOTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCom64_0(v *Value) bool { // match: (Com64 x) // result: (NOTQ x) for { x := v.Args[0] v.reset(OpAMD64NOTQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCom8_0(v *Value) bool { // match: (Com8 x) // result: (NOTL x) for { x := v.Args[0] v.reset(OpAMD64NOTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCondSelect_0(v *Value) bool { // match: (CondSelect x y (SETEQ cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQ y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQ) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETL cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETG cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETA cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQHI y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQHI) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETB cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCC y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCC) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_10(v *Value) bool { // match: (CondSelect x y (SETEQF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGTF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGTF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is32BitInt(t) // result: (CMOVLEQ y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQ) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is32BitInt(t) // result: (CMOVLNE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is32BitInt(t) // result: (CMOVLLT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is32BitInt(t) // result: (CMOVLGT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is32BitInt(t) // result: (CMOVLLE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is32BitInt(t) // result: (CMOVLGE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_20(v *Value) bool { // match: (CondSelect x y (SETA cond)) // cond: is32BitInt(t) // result: (CMOVLHI y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLHI) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is32BitInt(t) // result: (CMOVLCS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is32BitInt(t) // result: (CMOVLCC y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCC) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is32BitInt(t) // result: (CMOVLLS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is32BitInt(t) // result: (CMOVLEQF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is32BitInt(t) // result: (CMOVLNEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is32BitInt(t) // result: (CMOVLGTF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGTF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is32BitInt(t) // result: (CMOVLGEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is16BitInt(t) // result: (CMOVWEQ y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQ) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is16BitInt(t) // result: (CMOVWNE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_30(v *Value) bool { // match: (CondSelect x y (SETL cond)) // cond: is16BitInt(t) // result: (CMOVWLT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is16BitInt(t) // result: (CMOVWGT y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGT) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is16BitInt(t) // result: (CMOVWLE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is16BitInt(t) // result: (CMOVWGE y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGE) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is16BitInt(t) // result: (CMOVWHI y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWHI) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is16BitInt(t) // result: (CMOVWCS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is16BitInt(t) // result: (CMOVWCC y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCC) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is16BitInt(t) // result: (CMOVWLS y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLS) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is16BitInt(t) // result: (CMOVWEQF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is16BitInt(t) // result: (CMOVWNEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } return false } func rewriteValueAMD64_OpCondSelect_40(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (CondSelect x y (SETGF cond)) // cond: is16BitInt(t) // result: (CMOVWGTF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGTF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is16BitInt(t) // result: (CMOVWGEF y x cond) for { t := v.Type _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGEF) v.AddArg(y) v.AddArg(x) v.AddArg(cond) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 1 // result: (CondSelect x y (MOVBQZX check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 1) { break } v.reset(OpCondSelect) v.Type = t v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64) v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 2 // result: (CondSelect x y (MOVWQZX check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 2) { break } v.reset(OpCondSelect) v.Type = t v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64) v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 4 // result: (CondSelect x y (MOVLQZX check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 4) { break } v.reset(OpCondSelect) v.Type = t v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x (CMPQconst [0] check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { break } v.reset(OpAMD64CMOVQNE) v.AddArg(y) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) // result: (CMOVLNE y x (CMPQconst [0] check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg(y) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(check) v.AddArg(v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) // result: (CMOVWNE y x (CMPQconst [0] check)) for { t := v.Type check := v.Args[2] x := v.Args[0] y := v.Args[1] if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg(y) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(check) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpConst16_0(v *Value) bool { // match: (Const16 [val]) // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst32_0(v *Value) bool { // match: (Const32 [val]) // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst32F_0(v *Value) bool { // match: (Const32F [val]) // result: (MOVSSconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVSSconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst64_0(v *Value) bool { // match: (Const64 [val]) // result: (MOVQconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVQconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst64F_0(v *Value) bool { // match: (Const64F [val]) // result: (MOVSDconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVSDconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConst8_0(v *Value) bool { // match: (Const8 [val]) // result: (MOVLconst [val]) for { val := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = val return true } } func rewriteValueAMD64_OpConstBool_0(v *Value) bool { // match: (ConstBool [b]) // result: (MOVLconst [b]) for { b := v.AuxInt v.reset(OpAMD64MOVLconst) v.AuxInt = b return true } } func rewriteValueAMD64_OpConstNil_0(v *Value) bool { // match: (ConstNil) // result: (MOVQconst [0]) for { v.reset(OpAMD64MOVQconst) v.AuxInt = 0 return true } } func rewriteValueAMD64_OpCtz16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (BSFL (BTSLconst [16] x)) for { x := v.Args[0] v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = 16 v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz16NonZero_0(v *Value) bool { // match: (Ctz16NonZero x) // result: (BSFL x) for { x := v.Args[0] v.reset(OpAMD64BSFL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCtz32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // result: (Select0 (BSFQ (BTSQconst [32] x))) for { x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) v1.AuxInt = 32 v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz32NonZero_0(v *Value) bool { // match: (Ctz32NonZero x) // result: (BSFL x) for { x := v.Args[0] v.reset(OpAMD64BSFL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCtz64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) for { t := v.Type x := v.Args[0] v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v2.AuxInt = 64 v.AddArg(v2) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v4.AddArg(x) v3.AddArg(v4) v.AddArg(v3) return true } } func rewriteValueAMD64_OpCtz64NonZero_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz64NonZero x) // result: (Select0 (BSFQ x)) for { x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (BSFL (BTSLconst [ 8] x)) for { x := v.Args[0] v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = 8 v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8NonZero_0(v *Value) bool { // match: (Ctz8NonZero x) // result: (BSFL x) for { x := v.Args[0] v.reset(OpAMD64BSFL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32Fto32_0(v *Value) bool { // match: (Cvt32Fto32 x) // result: (CVTTSS2SL x) for { x := v.Args[0] v.reset(OpAMD64CVTTSS2SL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32Fto64_0(v *Value) bool { // match: (Cvt32Fto64 x) // result: (CVTTSS2SQ x) for { x := v.Args[0] v.reset(OpAMD64CVTTSS2SQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32Fto64F_0(v *Value) bool { // match: (Cvt32Fto64F x) // result: (CVTSS2SD x) for { x := v.Args[0] v.reset(OpAMD64CVTSS2SD) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32to32F_0(v *Value) bool { // match: (Cvt32to32F x) // result: (CVTSL2SS x) for { x := v.Args[0] v.reset(OpAMD64CVTSL2SS) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt32to64F_0(v *Value) bool { // match: (Cvt32to64F x) // result: (CVTSL2SD x) for { x := v.Args[0] v.reset(OpAMD64CVTSL2SD) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64Fto32_0(v *Value) bool { // match: (Cvt64Fto32 x) // result: (CVTTSD2SL x) for { x := v.Args[0] v.reset(OpAMD64CVTTSD2SL) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64Fto32F_0(v *Value) bool { // match: (Cvt64Fto32F x) // result: (CVTSD2SS x) for { x := v.Args[0] v.reset(OpAMD64CVTSD2SS) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64Fto64_0(v *Value) bool { // match: (Cvt64Fto64 x) // result: (CVTTSD2SQ x) for { x := v.Args[0] v.reset(OpAMD64CVTTSD2SQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64to32F_0(v *Value) bool { // match: (Cvt64to32F x) // result: (CVTSQ2SS x) for { x := v.Args[0] v.reset(OpAMD64CVTSQ2SS) v.AddArg(x) return true } } func rewriteValueAMD64_OpCvt64to64F_0(v *Value) bool { // match: (Cvt64to64F x) // result: (CVTSQ2SD x) for { x := v.Args[0] v.reset(OpAMD64CVTSQ2SD) v.AddArg(x) return true } } func rewriteValueAMD64_OpDiv128u_0(v *Value) bool { // match: (Div128u xhi xlo y) // result: (DIVQU2 xhi xlo y) for { y := v.Args[2] xhi := v.Args[0] xlo := v.Args[1] v.reset(OpAMD64DIVQU2) v.AddArg(xhi) v.AddArg(xlo) v.AddArg(y) return true } } func rewriteValueAMD64_OpDiv16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16 [a] x y) // result: (Select0 (DIVW [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv16u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (Select0 (DIVWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div32 [a] x y) // result: (Select0 (DIVL [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32F_0(v *Value) bool { // match: (Div32F x y) // result: (DIVSS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64DIVSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpDiv32u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div32u x y) // result: (Select0 (DIVLU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div64 [a] x y) // result: (Select0 (DIVQ [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64F_0(v *Value) bool { // match: (Div64F x y) // result: (DIVSD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64DIVSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpDiv64u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div64u x y) // result: (Select0 (DIVQU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq16_0(v *Value) bool { b := v.Block // match: (Eq16 x y) // result: (SETEQ (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32_0(v *Value) bool { b := v.Block // match: (Eq32 x y) // result: (SETEQ (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32F_0(v *Value) bool { b := v.Block // match: (Eq32F x y) // result: (SETEQF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64_0(v *Value) bool { b := v.Block // match: (Eq64 x y) // result: (SETEQ (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64F_0(v *Value) bool { b := v.Block // match: (Eq64F x y) // result: (SETEQF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq8_0(v *Value) bool { b := v.Block // match: (Eq8 x y) // result: (SETEQ (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqB_0(v *Value) bool { b := v.Block // match: (EqB x y) // result: (SETEQ (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqPtr_0(v *Value) bool { b := v.Block // match: (EqPtr x y) // result: (SETEQ (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpFMA_0(v *Value) bool { // match: (FMA x y z) // result: (VFMADD231SD z x y) for { z := v.Args[2] x := v.Args[0] y := v.Args[1] v.reset(OpAMD64VFMADD231SD) v.AddArg(z) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpFloor_0(v *Value) bool { // match: (Floor x) // result: (ROUNDSD [1] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValueAMD64_OpGeq16_0(v *Value) bool { b := v.Block // match: (Geq16 x y) // result: (SETGE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq16U_0(v *Value) bool { b := v.Block // match: (Geq16U x y) // result: (SETAE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq32_0(v *Value) bool { b := v.Block // match: (Geq32 x y) // result: (SETGE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq32F_0(v *Value) bool { b := v.Block // match: (Geq32F x y) // result: (SETGEF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq32U_0(v *Value) bool { b := v.Block // match: (Geq32U x y) // result: (SETAE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq64_0(v *Value) bool { b := v.Block // match: (Geq64 x y) // result: (SETGE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq64F_0(v *Value) bool { b := v.Block // match: (Geq64F x y) // result: (SETGEF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq64U_0(v *Value) bool { b := v.Block // match: (Geq64U x y) // result: (SETAE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq8_0(v *Value) bool { b := v.Block // match: (Geq8 x y) // result: (SETGE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGeq8U_0(v *Value) bool { b := v.Block // match: (Geq8U x y) // result: (SETAE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGetCallerPC_0(v *Value) bool { // match: (GetCallerPC) // result: (LoweredGetCallerPC) for { v.reset(OpAMD64LoweredGetCallerPC) return true } } func rewriteValueAMD64_OpGetCallerSP_0(v *Value) bool { // match: (GetCallerSP) // result: (LoweredGetCallerSP) for { v.reset(OpAMD64LoweredGetCallerSP) return true } } func rewriteValueAMD64_OpGetClosurePtr_0(v *Value) bool { // match: (GetClosurePtr) // result: (LoweredGetClosurePtr) for { v.reset(OpAMD64LoweredGetClosurePtr) return true } } func rewriteValueAMD64_OpGetG_0(v *Value) bool { // match: (GetG mem) // result: (LoweredGetG mem) for { mem := v.Args[0] v.reset(OpAMD64LoweredGetG) v.AddArg(mem) return true } } func rewriteValueAMD64_OpGreater16_0(v *Value) bool { b := v.Block // match: (Greater16 x y) // result: (SETG (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater16U_0(v *Value) bool { b := v.Block // match: (Greater16U x y) // result: (SETA (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater32_0(v *Value) bool { b := v.Block // match: (Greater32 x y) // result: (SETG (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater32F_0(v *Value) bool { b := v.Block // match: (Greater32F x y) // result: (SETGF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater32U_0(v *Value) bool { b := v.Block // match: (Greater32U x y) // result: (SETA (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater64_0(v *Value) bool { b := v.Block // match: (Greater64 x y) // result: (SETG (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater64F_0(v *Value) bool { b := v.Block // match: (Greater64F x y) // result: (SETGF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater64U_0(v *Value) bool { b := v.Block // match: (Greater64U x y) // result: (SETA (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater8_0(v *Value) bool { b := v.Block // match: (Greater8 x y) // result: (SETG (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETG) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpGreater8U_0(v *Value) bool { b := v.Block // match: (Greater8U x y) // result: (SETA (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETA) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpHmul32_0(v *Value) bool { // match: (Hmul32 x y) // result: (HMULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpHmul32u_0(v *Value) bool { // match: (Hmul32u x y) // result: (HMULLU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULLU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpHmul64_0(v *Value) bool { // match: (Hmul64 x y) // result: (HMULQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpHmul64u_0(v *Value) bool { // match: (Hmul64u x y) // result: (HMULQU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64HMULQU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpInterCall_0(v *Value) bool { // match: (InterCall [argwid] entry mem) // result: (CALLinter [argwid] entry mem) for { argwid := v.AuxInt mem := v.Args[1] entry := v.Args[0] v.reset(OpAMD64CALLinter) v.AuxInt = argwid v.AddArg(entry) v.AddArg(mem) return true } } func rewriteValueAMD64_OpIsInBounds_0(v *Value) bool { b := v.Block // match: (IsInBounds idx len) // result: (SETB (CMPQ idx len)) for { len := v.Args[1] idx := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsNonNil_0(v *Value) bool { b := v.Block // match: (IsNonNil p) // result: (SETNE (TESTQ p p)) for { p := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) v0.AddArg(p) v0.AddArg(p) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsSliceInBounds_0(v *Value) bool { b := v.Block // match: (IsSliceInBounds idx len) // result: (SETBE (CMPQ idx len)) for { len := v.Args[1] idx := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16_0(v *Value) bool { b := v.Block // match: (Leq16 x y) // result: (SETLE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16U_0(v *Value) bool { b := v.Block // match: (Leq16U x y) // result: (SETBE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32_0(v *Value) bool { b := v.Block // match: (Leq32 x y) // result: (SETLE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32F_0(v *Value) bool { b := v.Block // match: (Leq32F x y) // result: (SETGEF (UCOMISS y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32U_0(v *Value) bool { b := v.Block // match: (Leq32U x y) // result: (SETBE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64_0(v *Value) bool { b := v.Block // match: (Leq64 x y) // result: (SETLE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64F_0(v *Value) bool { b := v.Block // match: (Leq64F x y) // result: (SETGEF (UCOMISD y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64U_0(v *Value) bool { b := v.Block // match: (Leq64U x y) // result: (SETBE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8_0(v *Value) bool { b := v.Block // match: (Leq8 x y) // result: (SETLE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8U_0(v *Value) bool { b := v.Block // match: (Leq8U x y) // result: (SETBE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16_0(v *Value) bool { b := v.Block // match: (Less16 x y) // result: (SETL (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16U_0(v *Value) bool { b := v.Block // match: (Less16U x y) // result: (SETB (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32_0(v *Value) bool { b := v.Block // match: (Less32 x y) // result: (SETL (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32F_0(v *Value) bool { b := v.Block // match: (Less32F x y) // result: (SETGF (UCOMISS y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32U_0(v *Value) bool { b := v.Block // match: (Less32U x y) // result: (SETB (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64_0(v *Value) bool { b := v.Block // match: (Less64 x y) // result: (SETL (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64F_0(v *Value) bool { b := v.Block // match: (Less64F x y) // result: (SETGF (UCOMISD y x)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(y) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64U_0(v *Value) bool { b := v.Block // match: (Less64U x y) // result: (SETB (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8_0(v *Value) bool { b := v.Block // match: (Less8 x y) // result: (SETL (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8U_0(v *Value) bool { b := v.Block // match: (Less8U x y) // result: (SETB (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLoad_0(v *Value) bool { // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVQload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64MOVQload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) // result: (MOVLload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64MOVLload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64MOVWload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(OpAMD64MOVBload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitFloat(t)) { break } v.reset(OpAMD64MOVSSload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is64BitFloat(t)) { break } v.reset(OpAMD64MOVSDload) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpLocalAddr_0(v *Value) bool { // match: (LocalAddr {sym} base _) // result: (LEAQ {sym} base) for { sym := v.Aux _ = v.Args[1] base := v.Args[0] v.reset(OpAMD64LEAQ) v.Aux = sym v.AddArg(base) return true } } func rewriteValueAMD64_OpLsh16x16_0(v *Value) bool { b := v.Block // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh16x32_0(v *Value) bool { b := v.Block // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh16x64_0(v *Value) bool { b := v.Block // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh16x8_0(v *Value) bool { b := v.Block // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x16_0(v *Value) bool { b := v.Block // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x32_0(v *Value) bool { b := v.Block // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x64_0(v *Value) bool { b := v.Block // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh32x8_0(v *Value) bool { b := v.Block // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x16_0(v *Value) bool { b := v.Block // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x32_0(v *Value) bool { b := v.Block // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x64_0(v *Value) bool { b := v.Block // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh64x8_0(v *Value) bool { b := v.Block // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x16_0(v *Value) bool { b := v.Block // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x32_0(v *Value) bool { b := v.Block // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x64_0(v *Value) bool { b := v.Block // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpLsh8x8_0(v *Value) bool { b := v.Block // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpMod16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod16 [a] x y) // result: (Select1 (DIVW [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod16u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Select1 (DIVWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod32 [a] x y) // result: (Select1 (DIVL [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (Select1 (DIVLU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod64 [a] x y) // result: (Select1 (DIVQ [a] x y)) for { a := v.AuxInt y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = a v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (Select1 (DIVQU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMove_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if v.AuxInt != 0 { break } mem := v.Args[2] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBload src mem) mem) for { if v.AuxInt != 1 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [2] dst src mem) // result: (MOVWstore dst (MOVWload src mem) mem) for { if v.AuxInt != 2 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVWstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [4] dst src mem) // result: (MOVLstore dst (MOVLload src mem) mem) for { if v.AuxInt != 4 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVLstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [8] dst src mem) // result: (MOVQstore dst (MOVQload src mem) mem) for { if v.AuxInt != 8 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVQstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [16] dst src mem) // cond: config.useSSE // result: (MOVOstore dst (MOVOload src mem) mem) for { if v.AuxInt != 16 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [16] dst src mem) // cond: !config.useSSE // result: (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 16 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [32] dst src mem) // result: (Move [16] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if v.AuxInt != 32 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpMove) v.AuxInt = 16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = 16 v2.AddArg(dst) v2.AddArg(src) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Move [48] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if v.AuxInt != 48 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = 32 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = 16 v2.AddArg(dst) v2.AddArg(src) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Move [64] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [32]) (OffPtr src [32]) (Move [32] dst src mem)) for { if v.AuxInt != 64 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = 32 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = 32 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = 32 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = 32 v2.AddArg(dst) v2.AddArg(src) v2.AddArg(mem) v.AddArg(v2) return true } return false } func rewriteValueAMD64_OpMove_10(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if v.AuxInt != 3 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AuxInt = 2 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = 2 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 5 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [6] dst src mem) // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 6 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVWstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [7] dst src mem) // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if v.AuxInt != 7 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVLstore) v.AuxInt = 3 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = 3 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 9 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVBstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [10] dst src mem) // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 10 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVWstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [12] dst src mem) // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if v.AuxInt != 12 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpAMD64MOVLstore) v.AuxInt = 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [s] dst src mem) // cond: s == 11 || s >= 13 && s <= 15 // result: (MOVQstore [s-8] dst (MOVQload [s-8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s == 11 || s >= 13 && s <= 15) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = s - 8 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = s - 8 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 <= 8 // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore dst (MOVQload src mem) mem)) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 16 && s%16 != 0 && s%16 <= 8) { break } v.reset(OpMove) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = s % 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = s % 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVOstore dst (MOVOload src mem) mem)) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE) { break } v.reset(OpMove) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = s % 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = s % 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } return false } func rewriteValueAMD64_OpMove_20(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE) { break } v.reset(OpMove) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = s % 16 v0.AddArg(dst) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = s % 16 v1.AddArg(src) v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AuxInt = 8 v2.AddArg(dst) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AuxInt = 8 v3.AddArg(src) v3.AddArg(mem) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v4.AddArg(dst) v5 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v5.AddArg(src) v5.AddArg(mem) v4.AddArg(v5) v4.AddArg(mem) v2.AddArg(v4) v.AddArg(v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice // result: (DUFFCOPY [14*(64-s/16)] dst src mem) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFCOPY) v.AuxInt = 14 * (64 - s/16) v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } // match: (Move [s] dst src mem) // cond: (s > 16*64 || config.noDuffDevice) && s%8 == 0 // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !((s > 16*64 || config.noDuffDevice) && s%8 == 0) { break } v.reset(OpAMD64REPMOVSQ) v.AddArg(dst) v.AddArg(src) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = s / 8 v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpMul16_0(v *Value) bool { // match: (Mul16 x y) // result: (MULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul32_0(v *Value) bool { // match: (Mul32 x y) // result: (MULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul32F_0(v *Value) bool { // match: (Mul32F x y) // result: (MULSS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul64_0(v *Value) bool { // match: (Mul64 x y) // result: (MULQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul64F_0(v *Value) bool { // match: (Mul64F x y) // result: (MULSD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul64uhilo_0(v *Value) bool { // match: (Mul64uhilo x y) // result: (MULQU2 x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULQU2) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpMul8_0(v *Value) bool { // match: (Mul8 x y) // result: (MULL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64MULL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpNeg16_0(v *Value) bool { // match: (Neg16 x) // result: (NEGL x) for { x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeg32_0(v *Value) bool { // match: (Neg32 x) // result: (NEGL x) for { x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeg32F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Neg32F x) // result: (PXOR x (MOVSSconst [auxFrom32F(float32(math.Copysign(0, -1)))])) for { x := v.Args[0] v.reset(OpAMD64PXOR) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) v0.AuxInt = auxFrom32F(float32(math.Copysign(0, -1))) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeg64_0(v *Value) bool { // match: (Neg64 x) // result: (NEGQ x) for { x := v.Args[0] v.reset(OpAMD64NEGQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeg64F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Neg64F x) // result: (PXOR x (MOVSDconst [auxFrom64F(math.Copysign(0, -1))])) for { x := v.Args[0] v.reset(OpAMD64PXOR) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) v0.AuxInt = auxFrom64F(math.Copysign(0, -1)) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeg8_0(v *Value) bool { // match: (Neg8 x) // result: (NEGL x) for { x := v.Args[0] v.reset(OpAMD64NEGL) v.AddArg(x) return true } } func rewriteValueAMD64_OpNeq16_0(v *Value) bool { b := v.Block // match: (Neq16 x y) // result: (SETNE (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32_0(v *Value) bool { b := v.Block // match: (Neq32 x y) // result: (SETNE (CMPL x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32F_0(v *Value) bool { b := v.Block // match: (Neq32F x y) // result: (SETNEF (UCOMISS x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64_0(v *Value) bool { b := v.Block // match: (Neq64 x y) // result: (SETNE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64F_0(v *Value) bool { b := v.Block // match: (Neq64F x y) // result: (SETNEF (UCOMISD x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq8_0(v *Value) bool { b := v.Block // match: (Neq8 x y) // result: (SETNE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqB_0(v *Value) bool { b := v.Block // match: (NeqB x y) // result: (SETNE (CMPB x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqPtr_0(v *Value) bool { b := v.Block // match: (NeqPtr x y) // result: (SETNE (CMPQ x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNilCheck_0(v *Value) bool { // match: (NilCheck ptr mem) // result: (LoweredNilCheck ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpAMD64LoweredNilCheck) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValueAMD64_OpNot_0(v *Value) bool { // match: (Not x) // result: (XORLconst [1] x) for { x := v.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValueAMD64_OpOffPtr_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // cond: is32Bit(off) // result: (ADDQconst [off] ptr) for { off := v.AuxInt ptr := v.Args[0] if !(is32Bit(off)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = off v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDQ (MOVQconst [off]) ptr) for { off := v.AuxInt ptr := v.Args[0] v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = off v.AddArg(v0) v.AddArg(ptr) return true } } func rewriteValueAMD64_OpOr16_0(v *Value) bool { // match: (Or16 x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOr32_0(v *Value) bool { // match: (Or32 x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOr64_0(v *Value) bool { // match: (Or64 x y) // result: (ORQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOr8_0(v *Value) bool { // match: (Or8 x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpOrB_0(v *Value) bool { // match: (OrB x y) // result: (ORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64ORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpPanicBounds_0(v *Value) bool { // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 0) { break } v.reset(OpAMD64LoweredPanicBoundsA) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 1) { break } v.reset(OpAMD64LoweredPanicBoundsB) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 2) { break } v.reset(OpAMD64LoweredPanicBoundsC) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpPopCount16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTL (MOVWQZX x)) for { x := v.Args[0] v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpPopCount32_0(v *Value) bool { // match: (PopCount32 x) // result: (POPCNTL x) for { x := v.Args[0] v.reset(OpAMD64POPCNTL) v.AddArg(x) return true } } func rewriteValueAMD64_OpPopCount64_0(v *Value) bool { // match: (PopCount64 x) // result: (POPCNTQ x) for { x := v.Args[0] v.reset(OpAMD64POPCNTQ) v.AddArg(x) return true } } func rewriteValueAMD64_OpPopCount8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTL (MOVBQZX x)) for { x := v.Args[0] v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpRotateLeft16_0(v *Value) bool { // match: (RotateLeft16 a b) // result: (ROLW a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLW) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRotateLeft32_0(v *Value) bool { // match: (RotateLeft32 a b) // result: (ROLL a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLL) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRotateLeft64_0(v *Value) bool { // match: (RotateLeft64 a b) // result: (ROLQ a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLQ) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRotateLeft8_0(v *Value) bool { // match: (RotateLeft8 a b) // result: (ROLB a b) for { b := v.Args[1] a := v.Args[0] v.reset(OpAMD64ROLB) v.AddArg(a) v.AddArg(b) return true } } func rewriteValueAMD64_OpRound32F_0(v *Value) bool { // match: (Round32F x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpRound64F_0(v *Value) bool { // match: (Round64F x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpRoundToEven_0(v *Value) bool { // match: (RoundToEven x) // result: (ROUNDSD [0] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 0 v.AddArg(x) return true } } func rewriteValueAMD64_OpRsh16Ux16_0(v *Value) bool { b := v.Block // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16Ux32_0(v *Value) bool { b := v.Block // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16Ux64_0(v *Value) bool { b := v.Block // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16Ux8_0(v *Value) bool { b := v.Block // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 16 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x16_0(v *Value) bool { b := v.Block // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x32_0(v *Value) bool { b := v.Block // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x64_0(v *Value) bool { b := v.Block // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh16x8_0(v *Value) bool { b := v.Block // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux16_0(v *Value) bool { b := v.Block // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux32_0(v *Value) bool { b := v.Block // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux64_0(v *Value) bool { b := v.Block // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32Ux8_0(v *Value) bool { b := v.Block // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 32 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x16_0(v *Value) bool { b := v.Block // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x32_0(v *Value) bool { b := v.Block // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x64_0(v *Value) bool { b := v.Block // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh32x8_0(v *Value) bool { b := v.Block // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 32 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux16_0(v *Value) bool { b := v.Block // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux32_0(v *Value) bool { b := v.Block // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux64_0(v *Value) bool { b := v.Block // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64Ux8_0(v *Value) bool { b := v.Block // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 64 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x16_0(v *Value) bool { b := v.Block // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x32_0(v *Value) bool { b := v.Block // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x64_0(v *Value) bool { b := v.Block // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh64x8_0(v *Value) bool { b := v.Block // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 64 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux16_0(v *Value) bool { b := v.Block // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux32_0(v *Value) bool { b := v.Block // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux64_0(v *Value) bool { b := v.Block // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8Ux8_0(v *Value) bool { b := v.Block // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = 8 v2.AddArg(y) v1.AddArg(v2) v.AddArg(v1) return true } // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x16_0(v *Value) bool { b := v.Block // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x32_0(v *Value) bool { b := v.Block // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x64_0(v *Value) bool { b := v.Block // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpRsh8x8_0(v *Value) bool { b := v.Block // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type y := v.Args[1] x := v.Args[0] if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v.AddArg(x) v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = 8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg(x) v.AddArg(y) return true } return false } func rewriteValueAMD64_OpSelect0_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uover x y)) // result: (Select0 (MULQU x y)) for { v_0 := v.Args[0] if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (Select0 (Mul32uover x y)) // result: (Select0 (MULLU x y)) for { v_0 := v.Args[0] if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) for { v_0 := v.Args[0] if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y c)) // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) for { v_0 := v.Args[0] if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst32 val tuple)) // result: (ADDL val (Select0 tuple)) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDL) v.AddArg(val) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst64 val tuple)) // result: (ADDQ val (Select0 tuple)) for { t := v.Type v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDQ) v.AddArg(val) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpSelect1_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uover x y)) // result: (SETO (Select1 (MULQU x y))) for { v_0 := v.Args[0] if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul32uover x y)) // result: (SETO (Select1 (MULLU x y))) for { v_0 := v.Args[0] if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Add64carry x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) for { v_0 := v.Args[0] if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v2.AddArg(y) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) for { v_0 := v.Args[0] if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v2.AddArg(y) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (NEGLflags (MOVQconst [0]))) // result: (FlagEQ) for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst || v_0_0.AuxInt != 0 { break } v.reset(OpAMD64FlagEQ) return true } // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) // result: x for { v_0 := v.Args[0] if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64SBBQcarrymask { break } x := v_0_0_0.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (Select1 (AddTupleFirst32 _ tuple)) // result: (Select1 tuple) for { v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } // match: (Select1 (AddTupleFirst64 _ tuple)) // result: (Select1 tuple) for { v_0 := v.Args[0] if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } return false } func rewriteValueAMD64_OpSignExt16to32_0(v *Value) bool { // match: (SignExt16to32 x) // result: (MOVWQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt16to64_0(v *Value) bool { // match: (SignExt16to64 x) // result: (MOVWQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt32to64_0(v *Value) bool { // match: (SignExt32to64 x) // result: (MOVLQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt8to16_0(v *Value) bool { // match: (SignExt8to16 x) // result: (MOVBQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt8to32_0(v *Value) bool { // match: (SignExt8to32 x) // result: (MOVBQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSignExt8to64_0(v *Value) bool { // match: (SignExt8to64 x) // result: (MOVBQSX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } } func rewriteValueAMD64_OpSlicemask_0(v *Value) bool { b := v.Block // match: (Slicemask x) // result: (SARQconst (NEGQ x) [63]) for { t := v.Type x := v.Args[0] v.reset(OpAMD64SARQconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpSqrt_0(v *Value) bool { // match: (Sqrt x) // result: (SQRTSD x) for { x := v.Args[0] v.reset(OpAMD64SQRTSD) v.AddArg(x) return true } } func rewriteValueAMD64_OpStaticCall_0(v *Value) bool { // match: (StaticCall [argwid] {target} mem) // result: (CALLstatic [argwid] {target} mem) for { argwid := v.AuxInt target := v.Aux mem := v.Args[0] v.reset(OpAMD64CALLstatic) v.AuxInt = argwid v.Aux = target v.AddArg(mem) return true } } func rewriteValueAMD64_OpStore_0(v *Value) bool { // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) // result: (MOVSDstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) // result: (MOVSSstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpAMD64MOVSSstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 // result: (MOVQstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8) { break } v.reset(OpAMD64MOVQstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 // result: (MOVLstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 4) { break } v.reset(OpAMD64MOVLstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 2 // result: (MOVWstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 2) { break } v.reset(OpAMD64MOVWstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 1 // result: (MOVBstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 1) { break } v.reset(OpAMD64MOVBstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpSub16_0(v *Value) bool { // match: (Sub16 x y) // result: (SUBL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub32_0(v *Value) bool { // match: (Sub32 x y) // result: (SUBL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub32F_0(v *Value) bool { // match: (Sub32F x y) // result: (SUBSS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBSS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub64_0(v *Value) bool { // match: (Sub64 x y) // result: (SUBQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub64F_0(v *Value) bool { // match: (Sub64F x y) // result: (SUBSD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBSD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSub8_0(v *Value) bool { // match: (Sub8 x y) // result: (SUBL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpSubPtr_0(v *Value) bool { // match: (SubPtr x y) // result: (SUBQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64SUBQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpTrunc_0(v *Value) bool { // match: (Trunc x) // result: (ROUNDSD [3] x) for { x := v.Args[0] v.reset(OpAMD64ROUNDSD) v.AuxInt = 3 v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc16to8_0(v *Value) bool { // match: (Trunc16to8 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc32to16_0(v *Value) bool { // match: (Trunc32to16 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc32to8_0(v *Value) bool { // match: (Trunc32to8 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc64to16_0(v *Value) bool { // match: (Trunc64to16 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc64to32_0(v *Value) bool { // match: (Trunc64to32 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpTrunc64to8_0(v *Value) bool { // match: (Trunc64to8 x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValueAMD64_OpWB_0(v *Value) bool { // match: (WB {fn} destptr srcptr mem) // result: (LoweredWB {fn} destptr srcptr mem) for { fn := v.Aux mem := v.Args[2] destptr := v.Args[0] srcptr := v.Args[1] v.reset(OpAMD64LoweredWB) v.Aux = fn v.AddArg(destptr) v.AddArg(srcptr) v.AddArg(mem) return true } } func rewriteValueAMD64_OpXor16_0(v *Value) bool { // match: (Xor16 x y) // result: (XORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpXor32_0(v *Value) bool { // match: (Xor32 x y) // result: (XORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpXor64_0(v *Value) bool { // match: (Xor64 x y) // result: (XORQ x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORQ) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpXor8_0(v *Value) bool { // match: (Xor8 x y) // result: (XORL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpAMD64XORL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValueAMD64_OpZero_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (Zero [0] _ mem) // result: mem for { if v.AuxInt != 0 { break } mem := v.Args[1] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstoreconst [0] destptr mem) for { if v.AuxInt != 1 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVBstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [2] destptr mem) // result: (MOVWstoreconst [0] destptr mem) for { if v.AuxInt != 2 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVWstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [4] destptr mem) // result: (MOVLstoreconst [0] destptr mem) for { if v.AuxInt != 4 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVLstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [8] destptr mem) // result: (MOVQstoreconst [0] destptr mem) for { if v.AuxInt != 8 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVQstoreconst) v.AuxInt = 0 v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [0] destptr mem)) for { if v.AuxInt != 3 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(0, 2) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [5] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 5 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVBstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [6] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 6 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVWstoreconst) v.AuxInt = makeValAndOff(0, 4) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [7] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [0] destptr mem)) for { if v.AuxInt != 7 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpAMD64MOVLstoreconst) v.AuxInt = makeValAndOff(0, 3) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s%8 != 0 && s > 8 && !config.useSSE // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVQstoreconst [0] destptr mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s%8 != 0 && s > 8 && !config.useSSE) { break } v.reset(OpZero) v.AuxInt = s - s%8 v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = s % 8 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v.AddArg(v1) return true } return false } func rewriteValueAMD64_OpZero_10(v *Value) bool { b := v.Block config := b.Func.Config // match: (Zero [16] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem)) for { if v.AuxInt != 16 { break } mem := v.Args[1] destptr := v.Args[0] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, 8) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [24] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem))) for { if v.AuxInt != 24 { break } mem := v.Args[1] destptr := v.Args[0] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, 16) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = makeValAndOff(0, 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [32] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem)))) for { if v.AuxInt != 32 { break } mem := v.Args[1] destptr := v.Args[0] if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, 24) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = makeValAndOff(0, 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = makeValAndOff(0, 8) v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v2.AuxInt = 0 v2.AddArg(destptr) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s > 8 && s < 16 && config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,s-8)] destptr (MOVQstoreconst [0] destptr mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s > 8 && s < 16 && config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = makeValAndOff(0, s-8) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstore destptr (MOVOconst [0]) mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = s % 16 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v2.AuxInt = 0 v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVQstoreconst [0] destptr mem)) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = s - s%16 v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = s % 16 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Zero [16] destptr mem) // cond: config.useSSE // result: (MOVOstore destptr (MOVOconst [0]) mem) for { if v.AuxInt != 16 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (Zero [32] destptr mem) // cond: config.useSSE // result: (MOVOstore (OffPtr destptr [16]) (MOVOconst [0]) (MOVOstore destptr (MOVOconst [0]) mem)) for { if v.AuxInt != 32 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = 16 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v2.AddArg(destptr) v3 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v3.AuxInt = 0 v2.AddArg(v3) v2.AddArg(mem) v.AddArg(v2) return true } // match: (Zero [48] destptr mem) // cond: config.useSSE // result: (MOVOstore (OffPtr destptr [32]) (MOVOconst [0]) (MOVOstore (OffPtr destptr [16]) (MOVOconst [0]) (MOVOstore destptr (MOVOconst [0]) mem))) for { if v.AuxInt != 48 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = 32 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v3.AuxInt = 16 v3.AddArg(destptr) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v4.AuxInt = 0 v2.AddArg(v4) v5 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v5.AddArg(destptr) v6 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v6.AuxInt = 0 v5.AddArg(v6) v5.AddArg(mem) v2.AddArg(v5) v.AddArg(v2) return true } // match: (Zero [64] destptr mem) // cond: config.useSSE // result: (MOVOstore (OffPtr destptr [48]) (MOVOconst [0]) (MOVOstore (OffPtr destptr [32]) (MOVOconst [0]) (MOVOstore (OffPtr destptr [16]) (MOVOconst [0]) (MOVOstore destptr (MOVOconst [0]) mem)))) for { if v.AuxInt != 64 { break } mem := v.Args[1] destptr := v.Args[0] if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = 48 v0.AddArg(destptr) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v1.AuxInt = 0 v.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v3.AuxInt = 32 v3.AddArg(destptr) v2.AddArg(v3) v4 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v4.AuxInt = 0 v2.AddArg(v4) v5 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v6 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v6.AuxInt = 16 v6.AddArg(destptr) v5.AddArg(v6) v7 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v7.AuxInt = 0 v5.AddArg(v7) v8 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v8.AddArg(destptr) v9 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v9.AuxInt = 0 v8.AddArg(v9) v8.AddArg(mem) v5.AddArg(v8) v2.AddArg(v5) v.AddArg(v2) return true } return false } func rewriteValueAMD64_OpZero_20(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [s] destptr mem) // cond: s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice // result: (DUFFZERO [s] destptr (MOVOconst [0]) mem) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !(s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFZERO) v.AuxInt = s v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVOconst, types.TypeInt128) v0.AuxInt = 0 v.AddArg(v0) v.AddArg(mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0 // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) for { s := v.AuxInt mem := v.Args[1] destptr := v.Args[0] if !((s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0) { break } v.reset(OpAMD64REPSTOSQ) v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = s / 8 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = 0 v.AddArg(v1) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpZeroExt16to32_0(v *Value) bool { // match: (ZeroExt16to32 x) // result: (MOVWQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt16to64_0(v *Value) bool { // match: (ZeroExt16to64 x) // result: (MOVWQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt32to64_0(v *Value) bool { // match: (ZeroExt32to64 x) // result: (MOVLQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt8to16_0(v *Value) bool { // match: (ZeroExt8to16 x) // result: (MOVBQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt8to32_0(v *Value) bool { // match: (ZeroExt8to32 x) // result: (MOVBQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } } func rewriteValueAMD64_OpZeroExt8to64_0(v *Value) bool { // match: (ZeroExt8to64 x) // result: (MOVBQZX x) for { x := v.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } } func rewriteBlockAMD64(b *Block) bool { switch b.Kind { case BlockAMD64EQ: // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (UGE (BTLconst [log2uint32(c)] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64MOVQconst { continue } c := v_0_0.AuxInt x := v_0.Args[1^_i0] if !(isUint64PowerOfTwo(c)) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64UGE) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64EQ) b.AddControl(cmp) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64GE: // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LE) b.AddControl(cmp) return true } // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64GT: // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LT) b.AddControl(cmp) return true } // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockIf: // match: (If (SETL cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64SETL { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LT) b.AddControl(cmp) return true } // match: (If (SETLE cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64SETLE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64LE) b.AddControl(cmp) return true } // match: (If (SETG cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64SETG { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GT) b.AddControl(cmp) return true } // match: (If (SETGE cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64SETGE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GE) b.AddControl(cmp) return true } // match: (If (SETEQ cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64SETEQ { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64EQ) b.AddControl(cmp) return true } // match: (If (SETNE cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64SETNE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64NE) b.AddControl(cmp) return true } // match: (If (SETB cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64SETB { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULT) b.AddControl(cmp) return true } // match: (If (SETBE cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64SETBE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULE) b.AddControl(cmp) return true } // match: (If (SETA cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETA { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (If (SETAE cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETAE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (If (SETO cmp) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64SETO { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64OS) b.AddControl(cmp) return true } // match: (If (SETGF cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETGF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (If (SETGEF cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETGEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (If (SETEQF cmp) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64SETEQF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64EQF) b.AddControl(cmp) return true } // match: (If (SETNEF cmp) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64SETNEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64NEF) b.AddControl(cmp) return true } // match: (If cond yes no) // result: (NE (TESTB cond cond) yes no) for { cond := b.Controls[0] b.Reset(BlockAMD64NE) v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) v0.AddArg(cond) v0.AddArg(cond) b.AddControl(v0) return true } case BlockAMD64LE: // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GE) b.AddControl(cmp) return true } // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64LT: // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64GT) b.AddControl(cmp) return true } // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETL { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64LT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETLE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64LE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETG { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64GT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64GE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQ { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64EQ) b.AddControl(cmp) return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64NE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETB { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64ULT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETBE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64ULE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETA { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETAE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETO { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64OS) b.AddControl(cmp) return true } // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { continue } y := v_0.Args[1^_i0] b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) // result: (ULT (BTLconst [log2uint32(c)] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint32PowerOfTwo(c)) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = log2uint32(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := v_0.AuxInt x := v_0.Args[0] if !(isUint64PowerOfTwo(c)) { break } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0_0 := v_0.Args[_i0] if v_0_0.Op != OpAMD64MOVQconst { continue } c := v_0_0.AuxInt x := v_0.Args[1^_i0] if !(isUint64PowerOfTwo(c)) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = log2(c) v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { continue } x := z1_0.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = 63 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { z1 := v_0.Args[_i0] if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { continue } x := z1.Args[0] z2 := v_0.Args[1^_i0] if !(z1 == z2) { continue } b.Reset(BlockAMD64ULT) v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = 31 v0.AddArg(x) b.AddControl(v0) return true } break } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64EQF) b.AddControl(cmp) return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { break } b.Reset(BlockAMD64NEF) b.AddControl(cmp) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64NE) b.AddControl(cmp) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGE: // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULE) b.AddControl(cmp) return true } // match: (UGE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (UGE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGT: // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64ULT) b.AddControl(cmp) return true } // match: (UGT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64ULE: // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGE) b.AddControl(cmp) return true } // match: (ULE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64ULT: // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockAMD64UGT) b.AddControl(cmp) return true } // match: (ULT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- diff -- @@ -13,7 +13,7 @@ case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst_0(v) case OpAMD64ADDL: - return rewriteValueAMD64_OpAMD64ADDL_0(v) || rewriteValueAMD64_OpAMD64ADDL_10(v) || rewriteValueAMD64_OpAMD64ADDL_20(v) + return rewriteValueAMD64_OpAMD64ADDL_0(v) || rewriteValueAMD64_OpAMD64ADDL_10(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst_0(v) || rewriteValueAMD64_OpAMD64ADDLconst_10(v) case OpAMD64ADDLconstmodify: @@ -23,7 +23,7 @@ case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify_0(v) case OpAMD64ADDQ: - return rewriteValueAMD64_OpAMD64ADDQ_0(v) || rewriteValueAMD64_OpAMD64ADDQ_10(v) || rewriteValueAMD64_OpAMD64ADDQ_20(v) + return rewriteValueAMD64_OpAMD64ADDQ_0(v) || rewriteValueAMD64_OpAMD64ADDQ_10(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry_0(v) case OpAMD64ADDQconst: @@ -301,13 +301,13 @@ case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f_0(v) case OpAMD64MOVQload: - return rewriteValueAMD64_OpAMD64MOVQload_0(v) || rewriteValueAMD64_OpAMD64MOVQload_10(v) + return rewriteValueAMD64_OpAMD64MOVQload_0(v) case OpAMD64MOVQloadidx1: return rewriteValueAMD64_OpAMD64MOVQloadidx1_0(v) case OpAMD64MOVQloadidx8: return rewriteValueAMD64_OpAMD64MOVQloadidx8_0(v) case OpAMD64MOVQstore: - return rewriteValueAMD64_OpAMD64MOVQstore_0(v) || rewriteValueAMD64_OpAMD64MOVQstore_10(v) || rewriteValueAMD64_OpAMD64MOVQstore_20(v) || rewriteValueAMD64_OpAMD64MOVQstore_30(v) + return rewriteValueAMD64_OpAMD64MOVQstore_0(v) || rewriteValueAMD64_OpAMD64MOVQstore_10(v) || rewriteValueAMD64_OpAMD64MOVQstore_20(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst_0(v) case OpAMD64MOVQstoreconstidx1: @@ -391,7 +391,7 @@ case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ_0(v) case OpAMD64ORL: - return rewriteValueAMD64_OpAMD64ORL_0(v) || rewriteValueAMD64_OpAMD64ORL_10(v) || rewriteValueAMD64_OpAMD64ORL_20(v) || rewriteValueAMD64_OpAMD64ORL_30(v) || rewriteValueAMD64_OpAMD64ORL_40(v) || rewriteValueAMD64_OpAMD64ORL_50(v) || rewriteValueAMD64_OpAMD64ORL_60(v) || rewriteValueAMD64_OpAMD64ORL_70(v) || rewriteValueAMD64_OpAMD64ORL_80(v) || rewriteValueAMD64_OpAMD64ORL_90(v) || rewriteValueAMD64_OpAMD64ORL_100(v) || rewriteValueAMD64_OpAMD64ORL_110(v) || rewriteValueAMD64_OpAMD64ORL_120(v) || rewriteValueAMD64_OpAMD64ORL_130(v) + return rewriteValueAMD64_OpAMD64ORL_0(v) || rewriteValueAMD64_OpAMD64ORL_10(v) || rewriteValueAMD64_OpAMD64ORL_20(v) || rewriteValueAMD64_OpAMD64ORL_30(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst_0(v) case OpAMD64ORLconstmodify: @@ -401,7 +401,7 @@ case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify_0(v) case OpAMD64ORQ: - return rewriteValueAMD64_OpAMD64ORQ_0(v) || rewriteValueAMD64_OpAMD64ORQ_10(v) || rewriteValueAMD64_OpAMD64ORQ_20(v) || rewriteValueAMD64_OpAMD64ORQ_30(v) || rewriteValueAMD64_OpAMD64ORQ_40(v) || rewriteValueAMD64_OpAMD64ORQ_50(v) || rewriteValueAMD64_OpAMD64ORQ_60(v) || rewriteValueAMD64_OpAMD64ORQ_70(v) || rewriteValueAMD64_OpAMD64ORQ_80(v) || rewriteValueAMD64_OpAMD64ORQ_90(v) || rewriteValueAMD64_OpAMD64ORQ_100(v) || rewriteValueAMD64_OpAMD64ORQ_110(v) || rewriteValueAMD64_OpAMD64ORQ_120(v) || rewriteValueAMD64_OpAMD64ORQ_130(v) || rewriteValueAMD64_OpAMD64ORQ_140(v) || rewriteValueAMD64_OpAMD64ORQ_150(v) || rewriteValueAMD64_OpAMD64ORQ_160(v) + return rewriteValueAMD64_OpAMD64ORQ_0(v) || rewriteValueAMD64_OpAMD64ORQ_10(v) || rewriteValueAMD64_OpAMD64ORQ_20(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst_0(v) case OpAMD64ORQconstmodify: @@ -475,7 +475,7 @@ case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore_0(v) case OpAMD64SETEQ: - return rewriteValueAMD64_OpAMD64SETEQ_0(v) || rewriteValueAMD64_OpAMD64SETEQ_10(v) || rewriteValueAMD64_OpAMD64SETEQ_20(v) + return rewriteValueAMD64_OpAMD64SETEQ_0(v) || rewriteValueAMD64_OpAMD64SETEQ_10(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore_0(v) || rewriteValueAMD64_OpAMD64SETEQstore_10(v) || rewriteValueAMD64_OpAMD64SETEQstore_20(v) case OpAMD64SETG: @@ -495,7 +495,7 @@ case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore_0(v) case OpAMD64SETNE: - return rewriteValueAMD64_OpAMD64SETNE_0(v) || rewriteValueAMD64_OpAMD64SETNE_10(v) || rewriteValueAMD64_OpAMD64SETNE_20(v) + return rewriteValueAMD64_OpAMD64SETNE_0(v) || rewriteValueAMD64_OpAMD64SETNE_10(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore_0(v) || rewriteValueAMD64_OpAMD64SETNEstore_10(v) || rewriteValueAMD64_OpAMD64SETNEstore_20(v) case OpAMD64SHLL: @@ -573,7 +573,7 @@ case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ_0(v) case OpAMD64XORL: - return rewriteValueAMD64_OpAMD64XORL_0(v) || rewriteValueAMD64_OpAMD64XORL_10(v) + return rewriteValueAMD64_OpAMD64XORL_0(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst_0(v) || rewriteValueAMD64_OpAMD64XORLconst_10(v) case OpAMD64XORLconstmodify: @@ -583,7 +583,7 @@ case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify_0(v) case OpAMD64XORQ: - return rewriteValueAMD64_OpAMD64XORQ_0(v) || rewriteValueAMD64_OpAMD64XORQ_10(v) + return rewriteValueAMD64_OpAMD64XORQ_0(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst_0(v) case OpAMD64XORQconstmodify: @@ -1161,40 +1161,23 @@ // result: (ADCQconst x [c] carry) for { carry := v.Args[2] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(c)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64ADCQconst) + v.AuxInt = c + v.AddArg(x) + v.AddArg(carry) + return true } - v.reset(OpAMD64ADCQconst) - v.AuxInt = c - v.AddArg(x) - v.AddArg(carry) - return true - } - // match: (ADCQ (MOVQconst [c]) x carry) - // cond: is32Bit(c) - // result: (ADCQconst x [c] carry) - for { - carry := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - x := v.Args[1] - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ADCQconst) - v.AuxInt = c - v.AddArg(x) - v.AddArg(carry) - return true + break } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) @@ -1236,78 +1219,46 @@ // result: (ADDLconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break - } - c := v_1.AuxInt - v.reset(OpAMD64ADDLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDL (MOVLconst [c]) x) - // result: (ADDLconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVLconst { + continue + } + c := v_1.AuxInt + v.reset(OpAMD64ADDLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - v.reset(OpAMD64ADDLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADDL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRLconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 32-c) { + continue + } + v.reset(OpAMD64ROLLconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDL (SHRLconst x [d]) (SHLLconst x [c])) - // cond: d==32-c - // result: (ROLLconst x [c]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRLconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADDL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 @@ -1315,49 +1266,27 @@ for { t := v.Type _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRWconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - break - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDL (SHRWconst x [d]) (SHLLconst x [c])) - // cond: d==16-c && c < 16 && t.Size() == 2 - // result: (ROLWconst x [c]) - for { - t := v.Type - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRWconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRWconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { + continue + } + v.reset(OpAMD64ROLWconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - break - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADDL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 @@ -1365,405 +1294,221 @@ for { t := v.Type _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRBconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - break - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDL (SHRBconst x [d]) (SHLLconst x [c])) - // cond: d==8-c && c < 8 && t.Size() == 1 - // result: (ROLBconst x [c]) - for { - t := v.Type - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRBconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRBconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { + continue + } + v.reset(OpAMD64ROLBconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - break - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAL8) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL (SHLLconst [3] y) x) - // result: (LEAL8 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 3 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAL8) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAL8) - v.AddArg(x) - v.AddArg(y) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64ADDL_10(v *Value) bool { // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAL4) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL (SHLLconst [2] y) x) - // result: (LEAL4 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 2 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAL4) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAL4) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAL2) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_1.Args[0] - v.reset(OpAMD64LEAL2) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL (SHLLconst [1] y) x) - // result: (LEAL2 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { - break - } - y := v_0.Args[0] - v.reset(OpAMD64LEAL2) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDL { - break - } - y := v_1.Args[1] - if y != v_1.Args[0] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDL { + continue + } + y := v_1.Args[1] + if y != v_1.Args[0] { + continue + } + v.reset(OpAMD64LEAL2) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64LEAL2) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL (ADDL y y) x) - // result: (LEAL2 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDL { - break - } - y := v_0.Args[1] - if y != v_0.Args[0] { - break - } - v.reset(OpAMD64LEAL2) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDL { - break - } - y := v_1.Args[1] - if x != v_1.Args[0] { - break - } - v.reset(OpAMD64LEAL2) - v.AddArg(y) - v.AddArg(x) - return true - } - // match: (ADDL x (ADDL y x)) - // result: (LEAL2 y x) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + if x != v_1.Args[_i1] { + continue + } + y := v_1.Args[1^_i1] + v.reset(OpAMD64LEAL2) + v.AddArg(y) + v.AddArg(x) + return true + } } - _ = v_1.Args[1] - y := v_1.Args[0] - if x != v_1.Args[1] { - break - } - v.reset(OpAMD64LEAL2) - v.AddArg(y) - v.AddArg(x) - return true + break } - // match: (ADDL (ADDL x y) x) - // result: (LEAL2 y x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDL { - break - } - y := v_0.Args[1] - if x != v_0.Args[0] { - break - } - v.reset(OpAMD64LEAL2) - v.AddArg(y) - v.AddArg(x) - return true - } - // match: (ADDL (ADDL y x) x) - // result: (LEAL2 y x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDL { - break - } - _ = v_0.Args[1] - y := v_0.Args[0] - if x != v_0.Args[1] { - break - } - v.reset(OpAMD64LEAL2) - v.AddArg(y) - v.AddArg(x) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ADDL_20(v *Value) bool { // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) for { - y := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v.reset(OpAMD64LEAL1) - v.AuxInt = c - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL y (ADDLconst [c] x)) - // result: (LEAL1 [c] x y) - for { _ = v.Args[1] - y := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + y := v.Args[1^_i0] + v.reset(OpAMD64LEAL1) + v.AuxInt = c + v.AddArg(x) + v.AddArg(y) + return true } - c := v_1.AuxInt - x := v_1.Args[0] - v.reset(OpAMD64LEAL1) - v.AuxInt = c - v.AddArg(x) - v.AddArg(y) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64ADDL_10(v *Value) bool { // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64LEAL { - break - } - c := v_1.AuxInt - s := v_1.Aux - y := v_1.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64LEAL { + continue + } + c := v_1.AuxInt + s := v_1.Aux + y := v_1.Args[0] + if !(x.Op != OpSB && y.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAL1) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64LEAL1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL (LEAL [c] {s} y) x) - // cond: x.Op != OpSB && y.Op != OpSB - // result: (LEAL1 [c] {s} x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64LEAL { - break - } - c := v_0.AuxInt - s := v_0.Aux - y := v_0.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAL1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64NEGL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64NEGL { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64SUBL) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_1.Args[0] - v.reset(OpAMD64SUBL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL (NEGL y) x) - // result: (SUBL x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64NEGL { - break - } - y := v_0.Args[0] - v.reset(OpAMD64SUBL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ADDLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ADDL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ADDLload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVLload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ADDLload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ADDLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -2162,441 +1907,243 @@ // result: (ADDQconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ADDQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDQ (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (ADDQconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64ADDQconst) + v.AuxInt = c + v.AddArg(x) + return true } - v.reset(OpAMD64ADDQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADDQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRQconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 64-c) { + continue + } + v.reset(OpAMD64ROLQconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDQ (SHRQconst x [d]) (SHLQconst x [c])) - // cond: d==64-c - // result: (ROLQconst x [c]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ8) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDQ (SHLQconst [3] y) x) - // result: (LEAQ8 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAQ8) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAQ8) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ4) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDQ (SHLQconst [2] y) x) - // result: (LEAQ4 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAQ4) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAQ4) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ2) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDQ (SHLQconst [1] y) x) - // result: (LEAQ2 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAQ2) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAQ2) - v.AddArg(x) - v.AddArg(y) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64ADDQ_10(v *Value) bool { // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQ { - break - } - y := v_1.Args[1] - if y != v_1.Args[0] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDQ { + continue + } + y := v_1.Args[1] + if y != v_1.Args[0] { + continue + } + v.reset(OpAMD64LEAQ2) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64LEAQ2) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDQ (ADDQ y y) x) - // result: (LEAQ2 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - y := v_0.Args[1] - if y != v_0.Args[0] { - break - } - v.reset(OpAMD64LEAQ2) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQ { - break - } - y := v_1.Args[1] - if x != v_1.Args[0] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDQ { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + if x != v_1.Args[_i1] { + continue + } + y := v_1.Args[1^_i1] + v.reset(OpAMD64LEAQ2) + v.AddArg(y) + v.AddArg(x) + return true + } } - v.reset(OpAMD64LEAQ2) - v.AddArg(y) - v.AddArg(x) - return true - } - // match: (ADDQ x (ADDQ y x)) - // result: (LEAQ2 y x) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQ { - break - } - _ = v_1.Args[1] - y := v_1.Args[0] - if x != v_1.Args[1] { - break - } - v.reset(OpAMD64LEAQ2) - v.AddArg(y) - v.AddArg(x) - return true - } - // match: (ADDQ (ADDQ x y) x) - // result: (LEAQ2 y x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - y := v_0.Args[1] - if x != v_0.Args[0] { - break - } - v.reset(OpAMD64LEAQ2) - v.AddArg(y) - v.AddArg(x) - return true - } - // match: (ADDQ (ADDQ y x) x) - // result: (LEAQ2 y x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - _ = v_0.Args[1] - y := v_0.Args[0] - if x != v_0.Args[1] { - break - } - v.reset(OpAMD64LEAQ2) - v.AddArg(y) - v.AddArg(x) - return true + break } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) for { - y := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v.reset(OpAMD64LEAQ1) - v.AuxInt = c - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDQ y (ADDQconst [c] x)) - // result: (LEAQ1 [c] x y) - for { _ = v.Args[1] - y := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDQconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + y := v.Args[1^_i0] + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + v.AddArg(x) + v.AddArg(y) + return true } - c := v_1.AuxInt - x := v_1.Args[0] - v.reset(OpAMD64LEAQ1) - v.AuxInt = c - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64LEAQ { - break - } - c := v_1.AuxInt - s := v_1.Aux - y := v_1.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDQ (LEAQ [c] {s} y) x) - // cond: x.Op != OpSB && y.Op != OpSB - // result: (LEAQ1 [c] {s} x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64LEAQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64LEAQ { + continue + } + c := v_1.AuxInt + s := v_1.Aux + y := v_1.Args[0] + if !(x.Op != OpSB && y.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - c := v_0.AuxInt - s := v_0.Aux - y := v_0.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64ADDQ_20(v *Value) bool { // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64NEGQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64NEGQ { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64SUBQ) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_1.Args[0] - v.reset(OpAMD64SUBQ) - v.AddArg(x) - v.AddArg(y) - return true + break } - // match: (ADDQ (NEGQ y) x) - // result: (SUBQ x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64NEGQ { - break - } - y := v_0.Args[0] - v.reset(OpAMD64SUBQ) - v.AddArg(x) - v.AddArg(y) - return true - } + return false +} +func rewriteValueAMD64_OpAMD64ADDQ_10(v *Value) bool { // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ADDQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ADDQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ADDQload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVQload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ADDQload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ADDQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -2606,37 +2153,22 @@ // result: (ADDQconstcarry x [c]) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ADDQconstcarry) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDQcarry (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (ADDQconstcarry x [c]) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64ADDQconstcarry) + v.AuxInt = c + v.AddArg(x) + return true } - v.reset(OpAMD64ADDQconstcarry) - v.AuxInt = c - v.AddArg(x) - return true + break } return false } @@ -3037,49 +2569,28 @@ // result: (ADDSDload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVSDload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ADDSDload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ADDSD l:(MOVSDload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ADDSDload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVSDload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVSDload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ADDSDload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ADDSDload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -3169,49 +2680,28 @@ // result: (ADDSSload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVSSload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ADDSSload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ADDSS l:(MOVSSload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ADDSSload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVSSload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVSSload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ADDSSload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ADDSSload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -3299,113 +2789,68 @@ // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64NOTL { - break - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break - } - y := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTRL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ANDL x (NOTL (SHLL (MOVLconst [1]) y))) - // result: (BTRL x y) - for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64NOTL { - break - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLL { - break - } - y := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64NOTL { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SHLL { + continue + } + y := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { + continue + } + x := v.Args[1^_i0] + v.reset(OpAMD64BTRL) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64BTRL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ANDL (MOVLconst [c]) x) - // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 - // result: (BTRLconst [log2uint32(^c)] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { - break - } - v.reset(OpAMD64BTRLconst) - v.AuxInt = log2uint32(^c) - v.AddArg(x) - return true - } - // match: (ANDL x (MOVLconst [c])) // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRLconst [log2uint32(^c)] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break - } - c := v_1.AuxInt - if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { + continue + } + v.reset(OpAMD64BTRLconst) + v.AuxInt = log2uint32(^c) + v.AddArg(x) + return true } - v.reset(OpAMD64BTRLconst) - v.AuxInt = log2uint32(^c) - v.AddArg(x) - return true + break } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVLconst { + continue + } + c := v_1.AuxInt + v.reset(OpAMD64ANDLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - v.reset(OpAMD64ANDLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ANDL (MOVLconst [c]) x) - // result: (ANDLconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - v.reset(OpAMD64ANDLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ANDL x x) // result: x @@ -3424,49 +2869,28 @@ // result: (ANDLload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ANDLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ANDL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ANDLload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVLload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ANDLload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ANDLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -3766,121 +3190,72 @@ // match: (ANDQ (NOTQ (SHLQ (MOVQconst [1]) y)) x) // result: (BTRQ x y) for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64NOTQ { - break - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break - } - y := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTRQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ANDQ x (NOTQ (SHLQ (MOVQconst [1]) y))) - // result: (BTRQ x y) - for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64NOTQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64NOTQ { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SHLQ { + continue + } + y := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { + continue + } + x := v.Args[1^_i0] + v.reset(OpAMD64BTRQ) + v.AddArg(x) + v.AddArg(y) + return true } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLQ { - break - } - y := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTRQ) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ANDQ (MOVQconst [c]) x) - // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 - // result: (BTRQconst [log2(^c)] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { - break - } - v.reset(OpAMD64BTRQconst) - v.AuxInt = log2(^c) - v.AddArg(x) - return true - } - // match: (ANDQ x (MOVQconst [c])) // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRQconst [log2(^c)] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { + continue + } + v.reset(OpAMD64BTRQconst) + v.AuxInt = log2(^c) + v.AddArg(x) + return true } - v.reset(OpAMD64BTRQconst) - v.AuxInt = log2(^c) - v.AddArg(x) - return true + break } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64ANDQconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ANDQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ANDQ (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (ANDQconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ANDQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ANDQ x x) // result: x @@ -3899,49 +3274,28 @@ // result: (ANDQload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ANDQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ANDQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ANDQload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVQload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ANDQload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ANDQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -10208,39 +9562,21 @@ if v_0.Op != OpAMD64ADDL { break } - y := v_0.Args[1] - x := v_0.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAL1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAL [c] {s} (ADDL y x)) - // cond: x.Op != OpSB && y.Op != OpSB - // result: (LEAL1 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDL { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := v_0.Args[_i0] + y := v_0.Args[1^_i0] + if !(x.Op != OpSB && y.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAL1) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - x := v_0.Args[1] - y := v_0.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAL1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } return false } @@ -10251,46 +9587,26 @@ for { c := v.AuxInt s := v.Aux - y := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDLconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - if !(is32Bit(c+d) && x.Op != OpSB) { - break - } - v.reset(OpAMD64LEAL1) - v.AuxInt = c + d - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAL1 [c] {s} y (ADDLconst [d] x)) - // cond: is32Bit(c+d) && x.Op != OpSB - // result: (LEAL1 [c+d] {s} x y) - for { - c := v.AuxInt - s := v.Aux _ = v.Args[1] - y := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDLconst { - break - } - d := v_1.AuxInt - x := v_1.Args[0] - if !(is32Bit(c+d) && x.Op != OpSB) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDLconst { + continue + } + d := v_0.AuxInt + x := v_0.Args[0] + y := v.Args[1^_i0] + if !(is32Bit(c+d) && x.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAL1) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64LEAL1) - v.AuxInt = c + d - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) @@ -10298,36 +9614,21 @@ c := v.AuxInt s := v.Aux _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAL2) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - y := v_1.Args[0] - v.reset(OpAMD64LEAL2) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAL1 [c] {s} (SHLLconst [1] y) x) - // result: (LEAL2 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { - break - } - y := v_0.Args[0] - v.reset(OpAMD64LEAL2) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) @@ -10335,36 +9636,21 @@ c := v.AuxInt s := v.Aux _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAL4) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAL1 [c] {s} (SHLLconst [2] y) x) - // result: (LEAL4 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 2 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAL4) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAL4) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) @@ -10372,36 +9658,21 @@ c := v.AuxInt s := v.Aux _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAL8) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - y := v_1.Args[0] - v.reset(OpAMD64LEAL8) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAL1 [c] {s} (SHLLconst [3] y) x) - // result: (LEAL8 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 3 { - break - } - y := v_0.Args[0] - v.reset(OpAMD64LEAL8) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } return false } @@ -10644,39 +9915,21 @@ if v_0.Op != OpAMD64ADDQ { break } - y := v_0.Args[1] - x := v_0.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAQ [c] {s} (ADDQ y x)) - // cond: x.Op != OpSB && y.Op != OpSB - // result: (LEAQ1 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := v_0.Args[_i0] + y := v_0.Args[1^_i0] + if !(x.Op != OpSB && y.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - x := v_0.Args[1] - y := v_0.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) @@ -10805,46 +10058,26 @@ for { c := v.AuxInt s := v.Aux - y := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - if !(is32Bit(c+d) && x.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = c + d - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAQ1 [c] {s} y (ADDQconst [d] x)) - // cond: is32Bit(c+d) && x.Op != OpSB - // result: (LEAQ1 [c+d] {s} x y) - for { - c := v.AuxInt - s := v.Aux _ = v.Args[1] - y := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - x := v_1.Args[0] - if !(is32Bit(c+d) && x.Op != OpSB) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDQconst { + continue + } + d := v_0.AuxInt + x := v_0.Args[0] + y := v.Args[1^_i0] + if !(is32Bit(c+d) && x.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64LEAQ1) - v.AuxInt = c + d - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) @@ -10852,36 +10085,21 @@ c := v.AuxInt s := v.Aux _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAQ2) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ2) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAQ1 [c] {s} (SHLQconst [1] y) x) - // result: (LEAQ2 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { - break - } - y := v_0.Args[0] - v.reset(OpAMD64LEAQ2) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) @@ -10889,36 +10107,21 @@ c := v.AuxInt s := v.Aux _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ4) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAQ1 [c] {s} (SHLQconst [2] y) x) - // result: (LEAQ4 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAQ4) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAQ4) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) @@ -10926,36 +10129,21 @@ c := v.AuxInt s := v.Aux _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ8) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAQ1 [c] {s} (SHLQconst [3] y) x) - // result: (LEAQ8 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAQ8) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAQ8) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB @@ -10963,48 +10151,27 @@ for { off1 := v.AuxInt sym1 := v.Aux - y := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64LEAQ { - break - } - off2 := v_0.AuxInt - sym2 := v_0.Aux - x := v_0.Args[0] - if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = off1 + off2 - v.Aux = mergeSym(sym1, sym2) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAQ1 [off1] {sym1} y (LEAQ [off2] {sym2} x)) - // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) - for { - off1 := v.AuxInt - sym1 := v.Aux _ = v.Args[1] - y := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64LEAQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64LEAQ { + continue + } + off2 := v_0.AuxInt + sym2 := v_0.Aux + x := v_0.Args[0] + y := v.Args[1^_i0] + if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = off1 + off2 + v.Aux = mergeSym(sym1, sym2) + v.AddArg(x) + v.AddArg(y) + return true } - off2 := v_1.AuxInt - sym2 := v_1.Aux - x := v_1.Args[0] - if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = off1 + off2 - v.Aux = mergeSym(sym1, sym2) - v.AddArg(x) - v.AddArg(y) - return true + break } return false } @@ -11801,42 +10968,22 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVBloadidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVBloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVBload [off] {sym} (ADDQ idx ptr) mem) - // cond: ptr.Op != OpSB - // result: (MOVBloadidx1 [off] {sym} ptr idx mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVBloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) @@ -11910,48 +11057,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break - } - d := v_0.AuxInt - ptr := v_0.Args[0] - idx := v.Args[1] - if !(is32Bit(c + d)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDQconst { + continue + } + d := v_0.AuxInt + ptr := v_0.Args[0] + idx := v.Args[1^_i0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVBloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVBloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVBloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) - // cond: is32Bit(c+d) - // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - idx := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - ptr := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVBloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVBloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) @@ -11960,48 +11085,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - idx := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVBloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVBloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) - // cond: is32Bit(c+d) - // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDQconst { + continue + } + d := v_1.AuxInt + idx := v_1.Args[0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVBloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - d := v_0.AuxInt - idx := v_0.Args[0] - ptr := v.Args[1] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVBloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVBloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) @@ -12010,44 +11113,24 @@ i := v.AuxInt s := v.Aux mem := v.Args[2] - p := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVBload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true - } - // match: (MOVBloadidx1 [i] {s} (MOVQconst [c]) p mem) - // cond: is32Bit(i+c) - // result: (MOVBload [i+c] {s} p mem) - for { - i := v.AuxInt - s := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + p := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(i + c)) { + continue + } + v.reset(OpAMD64MOVBload) + v.AuxInt = i + c + v.Aux = s + v.AddArg(p) + v.AddArg(mem) + return true } - c := v_0.AuxInt - p := v.Args[1] - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVBload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true + break } return false } @@ -12472,46 +11555,24 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + val := v.Args[1] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVBstoreidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVBstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true - } - // match: (MOVBstore [off] {sym} (ADDQ idx ptr) val mem) - // cond: ptr.Op != OpSB - // result: (MOVBstoreidx1 [off] {sym} ptr idx val mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVBstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true + break } // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) @@ -12545,10 +11606,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVBstore_20(v *Value) bool { - b := v.Block // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) @@ -12604,6 +11661,11 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVBstore_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) @@ -12949,11 +12011,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVBstore_30(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) @@ -12999,6 +12056,9 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVBstore_30(v *Value) bool { // match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) @@ -14373,42 +13433,22 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVLloadidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVLloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVLload [off] {sym} (ADDQ idx ptr) mem) - // cond: ptr.Op != OpSB - // result: (MOVLloadidx1 [off] {sym} ptr idx mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVLloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) @@ -14457,11 +13497,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVLload_10(v *Value) bool { - b := v.Block - config := b.Func.Config // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { @@ -14482,6 +13517,11 @@ v.AddArg(val) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVLload_10(v *Value) bool { + b := v.Block + config := b.Func.Config // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, off, config.BigEndian))]) @@ -14506,39 +13546,22 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { + continue + } + idx := v_1.Args[0] + v.reset(OpAMD64MOVLloadidx4) + v.AuxInt = c + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - idx := v_1.Args[0] - v.reset(OpAMD64MOVLloadidx4) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVLloadidx1 [c] {sym} (SHLQconst [2] idx) ptr mem) - // result: (MOVLloadidx4 [c] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 { - break - } - idx := v_0.Args[0] - ptr := v.Args[1] - v.reset(OpAMD64MOVLloadidx4) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVLloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVLloadidx8 [c] {sym} ptr idx mem) @@ -14546,39 +13569,22 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { + continue + } + idx := v_1.Args[0] + v.reset(OpAMD64MOVLloadidx8) + v.AuxInt = c + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - idx := v_1.Args[0] - v.reset(OpAMD64MOVLloadidx8) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVLloadidx1 [c] {sym} (SHLQconst [3] idx) ptr mem) - // result: (MOVLloadidx8 [c] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { - break - } - idx := v_0.Args[0] - ptr := v.Args[1] - v.reset(OpAMD64MOVLloadidx8) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVLloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) @@ -14587,48 +13593,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break - } - d := v_0.AuxInt - ptr := v_0.Args[0] - idx := v.Args[1] - if !(is32Bit(c + d)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDQconst { + continue + } + d := v_0.AuxInt + ptr := v_0.Args[0] + idx := v.Args[1^_i0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVLloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVLloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVLloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) - // cond: is32Bit(c+d) - // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - idx := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - ptr := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVLloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVLloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) @@ -14637,48 +13621,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - idx := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVLloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVLloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) - // cond: is32Bit(c+d) - // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDQconst { + continue + } + d := v_1.AuxInt + idx := v_1.Args[0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVLloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - d := v_0.AuxInt - idx := v_0.Args[0] - ptr := v.Args[1] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVLloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVLloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) @@ -14687,44 +13649,24 @@ i := v.AuxInt s := v.Aux mem := v.Args[2] - p := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVLload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true - } - // match: (MOVLloadidx1 [i] {s} (MOVQconst [c]) p mem) - // cond: is32Bit(i+c) - // result: (MOVLload [i+c] {s} p mem) - for { - i := v.AuxInt - s := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + p := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(i + c)) { + continue + } + v.reset(OpAMD64MOVLload) + v.AuxInt = i + c + v.Aux = s + v.AddArg(p) + v.AddArg(mem) + return true } - c := v_0.AuxInt - p := v.Args[1] - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVLload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true + break } return false } @@ -15113,52 +14055,30 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + val := v.Args[1] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVLstoreidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVLstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true + break } return false } func rewriteValueAMD64_OpAMD64MOVLstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types - // match: (MOVLstore [off] {sym} (ADDQ idx ptr) val mem) - // cond: ptr.Op != OpSB - // result: (MOVLstoreidx1 [off] {sym} ptr idx val mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVLstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true - } // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w mem) @@ -15418,9 +14338,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVLstore_20(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodify [off] {sym} ptr x mem) @@ -15433,53 +14350,33 @@ if y.Op != OpAMD64ADDL { break } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ADDLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVLstore {sym} [off] ptr y:(ADDL x l:(MOVLload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (ADDLmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64ADDL { - break - } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64ADDLmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - v.reset(OpAMD64ADDLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64MOVLstore_20(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBLmodify [off] {sym} ptr x mem) @@ -15521,52 +14418,29 @@ if y.Op != OpAMD64ANDL { break } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ANDLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVLstore {sym} [off] ptr y:(ANDL x l:(MOVLload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (ANDLmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64ANDL { - break - } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64ANDLmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ANDLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) @@ -15580,52 +14454,29 @@ if y.Op != OpAMD64ORL { break } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ORLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVLstore {sym} [off] ptr y:(ORL x l:(MOVLload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (ORLmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64ORL { - break - } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64ORLmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ORLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) @@ -15639,52 +14490,29 @@ if y.Op != OpAMD64XORL { break } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64XORLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVLstore {sym} [off] ptr y:(XORL x l:(MOVLload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (XORLmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64XORL { - break - } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64XORLmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64XORLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } // match: (MOVLstore {sym} [off] ptr y:(BTCL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) @@ -15715,9 +14543,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVLstore_30(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(BTRL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTRLmodify [off] {sym} ptr x mem) @@ -15863,6 +14688,9 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVLstore_30(v *Value) bool { // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (XORLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) @@ -17069,6 +15897,8 @@ return false } func rewriteValueAMD64_OpAMD64MOVQload_0(v *Value) bool { + b := v.Block + config := b.Func.Config // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x @@ -17204,42 +16034,22 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVQloadidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVQloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVQload [off] {sym} (ADDQ idx ptr) mem) - // cond: ptr.Op != OpSB - // result: (MOVQloadidx1 [off] {sym} ptr idx mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVQloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVQload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) @@ -17308,11 +16118,6 @@ v.AddArg(val) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVQload_10(v *Value) bool { - b := v.Block - config := b.Func.Config // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, off, config.BigEndian))]) @@ -17337,39 +16142,22 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { + continue + } + idx := v_1.Args[0] + v.reset(OpAMD64MOVQloadidx8) + v.AuxInt = c + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - idx := v_1.Args[0] - v.reset(OpAMD64MOVQloadidx8) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVQloadidx1 [c] {sym} (SHLQconst [3] idx) ptr mem) - // result: (MOVQloadidx8 [c] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { - break - } - idx := v_0.Args[0] - ptr := v.Args[1] - v.reset(OpAMD64MOVQloadidx8) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVQloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) @@ -17378,48 +16166,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break - } - d := v_0.AuxInt - ptr := v_0.Args[0] - idx := v.Args[1] - if !(is32Bit(c + d)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDQconst { + continue + } + d := v_0.AuxInt + ptr := v_0.Args[0] + idx := v.Args[1^_i0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVQloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVQloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVQloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) - // cond: is32Bit(c+d) - // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - idx := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - ptr := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVQloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVQloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) @@ -17428,48 +16194,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - idx := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVQloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVQloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) - // cond: is32Bit(c+d) - // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDQconst { + continue + } + d := v_1.AuxInt + idx := v_1.Args[0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVQloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - d := v_0.AuxInt - idx := v_0.Args[0] - ptr := v.Args[1] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVQloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVQloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) @@ -17478,44 +16222,24 @@ i := v.AuxInt s := v.Aux mem := v.Args[2] - p := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVQload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true - } - // match: (MOVQloadidx1 [i] {s} (MOVQconst [c]) p mem) - // cond: is32Bit(i+c) - // result: (MOVQload [i+c] {s} p mem) - for { - i := v.AuxInt - s := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + p := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(i + c)) { + continue + } + v.reset(OpAMD64MOVQload) + v.AuxInt = i + c + v.Aux = s + v.AddArg(p) + v.AddArg(mem) + return true } - c := v_0.AuxInt - p := v.Args[1] - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVQload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true + break } return false } @@ -17737,46 +16461,24 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + val := v.Args[1] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVQstoreidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVQstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true - } - // match: (MOVQstore [off] {sym} (ADDQ idx ptr) val mem) - // cond: ptr.Op != OpSB - // result: (MOVQstoreidx1 [off] {sym} ptr idx val mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVQstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true + break } // match: (MOVQstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) @@ -17854,9 +16556,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVQstore_10(v *Value) bool { // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) @@ -17882,6 +16581,9 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVQstore_10(v *Value) bool { // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) @@ -17944,52 +16646,29 @@ if y.Op != OpAMD64ADDQ { break } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ADDQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVQstore {sym} [off] ptr y:(ADDQ x l:(MOVQload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (ADDQmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64ADDQ { - break - } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64ADDQmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ADDQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) @@ -18032,52 +16711,29 @@ if y.Op != OpAMD64ANDQ { break } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ANDQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVQstore {sym} [off] ptr y:(ANDQ x l:(MOVQload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (ANDQmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64ANDQ { - break - } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64ANDQmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ANDQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) @@ -18091,56 +16747,30 @@ if y.Op != OpAMD64ORQ { break } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ORQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVQstore {sym} [off] ptr y:(ORQ x l:(MOVQload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (ORQmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64ORQ { - break - } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64ORQmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - v.reset(OpAMD64ORQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVQstore_20(v *Value) bool { // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORQmodify [off] {sym} ptr x mem) @@ -18153,52 +16783,29 @@ if y.Op != OpAMD64XORQ { break } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64XORQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVQstore {sym} [off] ptr y:(XORQ x l:(MOVQload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (XORQmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64XORQ { - break - } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64XORQmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64XORQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } // match: (MOVQstore {sym} [off] ptr y:(BTCQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) @@ -18287,6 +16894,9 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVQstore_20(v *Value) bool { // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ADDQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) @@ -18432,9 +17042,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVQstore_30(v *Value) bool { // match: (MOVQstore [off] {sym} ptr a:(BTRQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTRQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) @@ -19139,42 +17746,22 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVSDloadidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVSDloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVSDload [off] {sym} (ADDQ idx ptr) mem) - // cond: ptr.Op != OpSB - // result: (MOVSDloadidx1 [off] {sym} ptr idx mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVSDloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) @@ -19489,46 +18076,24 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + val := v.Args[1] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVSDstoreidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVSDstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true - } - // match: (MOVSDstore [off] {sym} (ADDQ idx ptr) val mem) - // cond: ptr.Op != OpSB - // result: (MOVSDstoreidx1 [off] {sym} ptr idx val mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVSDstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true + break } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) @@ -19849,42 +18414,22 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVSSloadidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVSSloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVSSload [off] {sym} (ADDQ idx ptr) mem) - // cond: ptr.Op != OpSB - // result: (MOVSSloadidx1 [off] {sym} ptr idx mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVSSloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) @@ -20199,46 +18744,24 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + val := v.Args[1] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVSSstoreidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVSSstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true - } - // match: (MOVSSstore [off] {sym} (ADDQ idx ptr) val mem) - // cond: ptr.Op != OpSB - // result: (MOVSSstoreidx1 [off] {sym} ptr idx val mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVSSstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true + break } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) @@ -20941,42 +19464,22 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVWloadidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVWloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVWload [off] {sym} (ADDQ idx ptr) mem) - // cond: ptr.Op != OpSB - // result: (MOVWloadidx1 [off] {sym} ptr idx mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVWloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) @@ -21049,39 +19552,22 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { - break - } - idx := v_1.Args[0] - v.reset(OpAMD64MOVWloadidx2) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVWloadidx1 [c] {sym} (SHLQconst [1] idx) ptr mem) - // result: (MOVWloadidx2 [c] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { + continue + } + idx := v_1.Args[0] + v.reset(OpAMD64MOVWloadidx2) + v.AuxInt = c + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - idx := v_0.Args[0] - ptr := v.Args[1] - v.reset(OpAMD64MOVWloadidx2) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVWloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) @@ -21090,48 +19576,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break - } - d := v_0.AuxInt - ptr := v_0.Args[0] - idx := v.Args[1] - if !(is32Bit(c + d)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDQconst { + continue + } + d := v_0.AuxInt + ptr := v_0.Args[0] + idx := v.Args[1^_i0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVWloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVWloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVWloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) - // cond: is32Bit(c+d) - // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - idx := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - ptr := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVWloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVWloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) @@ -21140,48 +19604,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - idx := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVWloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVWloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) - // cond: is32Bit(c+d) - // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDQconst { + continue + } + d := v_1.AuxInt + idx := v_1.Args[0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVWloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - d := v_0.AuxInt - idx := v_0.Args[0] - ptr := v.Args[1] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVWloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVWloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) @@ -21190,44 +19632,24 @@ i := v.AuxInt s := v.Aux mem := v.Args[2] - p := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVWload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true - } - // match: (MOVWloadidx1 [i] {s} (MOVQconst [c]) p mem) - // cond: is32Bit(i+c) - // result: (MOVWload [i+c] {s} p mem) - for { - i := v.AuxInt - s := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + p := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(i + c)) { + continue + } + v.reset(OpAMD64MOVWload) + v.AuxInt = i + c + v.Aux = s + v.AddArg(p) + v.AddArg(mem) + return true } - c := v_0.AuxInt - p := v.Args[1] - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVWload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true + break } return false } @@ -21512,52 +19934,25 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVWstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true - } - // match: (MOVWstore [off] {sym} (ADDQ idx ptr) val mem) - // cond: ptr.Op != OpSB - // result: (MOVWstoreidx1 [off] {sym} ptr idx val mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + val := v.Args[1] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVWstoreidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true } - ptr := v_0.Args[1] - idx := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVWstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVWstore_10(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) @@ -21587,6 +19982,11 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVWstore_10(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) @@ -22626,30 +21026,19 @@ // result: (MULLconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break - } - c := v_1.AuxInt - v.reset(OpAMD64MULLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (MULL (MOVLconst [c]) x) - // result: (MULLconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVLconst { + continue + } + c := v_1.AuxInt + v.reset(OpAMD64MULLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - v.reset(OpAMD64MULLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } return false } @@ -23138,37 +21527,22 @@ // result: (MULQconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64MULQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (MULQ (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (MULQconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64MULQconst) + v.AuxInt = c + v.AddArg(x) + return true } - v.reset(OpAMD64MULQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } return false } @@ -23679,49 +22053,28 @@ // result: (MULSDload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVSDload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64MULSDload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (MULSD l:(MOVSDload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (MULSDload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVSDload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVSDload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64MULSDload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64MULSDload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -23811,49 +22164,28 @@ // result: (MULSSload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVSSload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64MULSSload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (MULSS l:(MOVSSload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (MULSSload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVSSload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVSSload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64MULSSload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64MULSSload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -24085,153 +22417,91 @@ // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTSL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL x (SHLL (MOVLconst [1]) y)) - // result: (BTSL x y) - for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVLconst || v_1_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { + continue + } + x := v.Args[1^_i0] + v.reset(OpAMD64BTSL) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64BTSL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSLconst [log2uint32(c)] x) for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { - break - } - v.reset(OpAMD64BTSLconst) - v.AuxInt = log2uint32(c) - v.AddArg(x) - return true - } - // match: (ORL x (MOVLconst [c])) - // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 - // result: (BTSLconst [log2uint32(c)] x) - for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break - } - c := v_1.AuxInt - if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { + continue + } + v.reset(OpAMD64BTSLconst) + v.AuxInt = log2uint32(c) + v.AddArg(x) + return true } - v.reset(OpAMD64BTSLconst) - v.AuxInt = log2uint32(c) - v.AddArg(x) - return true + break } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVLconst { + continue + } + c := v_1.AuxInt + v.reset(OpAMD64ORLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - v.reset(OpAMD64ORLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ORL (MOVLconst [c]) x) - // result: (ORLconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - v.reset(OpAMD64ORLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRLconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 32-c) { + continue + } + v.reset(OpAMD64ROLLconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ORL (SHRLconst x [d]) (SHLLconst x [c])) - // cond: d==32-c - // result: (ROLLconst x [c]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRLconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 @@ -24239,2340 +22509,748 @@ for { t := v.Type _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRWconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { + continue + } + v.reset(OpAMD64ROLWconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRWconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - break - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } - // match: (ORL (SHRWconst x [d]) (SHLLconst x [c])) - // cond: d==16-c && c < 16 && t.Size() == 2 - // result: (ROLWconst x [c]) - for { - t := v.Type - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRWconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - break - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_10(v *Value) bool { // match: (ORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRBconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - break - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ORL (SHRBconst x [d]) (SHLLconst x [c])) - // cond: d==8-c && c < 8 && t.Size() == 1 - // result: (ROLBconst x [c]) - for { - t := v.Type - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRBconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRBconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { + continue + } + v.reset(OpAMD64ROLBconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - break - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRL { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x y) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHRL x (NEGQ y)))) - // result: (ROLL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 32 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGQ { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -32 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRL { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32]))) (SHLL x y)) - // result: (ROLL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLL) + v.AddArg(x) + v.AddArg(y) + return true + } } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGQ { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGQ { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -32 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHRL x (NEGQ y))) (SHLL x y)) - // result: (ROLL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 32 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGQ { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -32 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 31 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRL { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRL { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLL) + v.AddArg(x) + v.AddArg(y) + return true + } } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true + break } - // match: (ORL (SHLL x y) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHRL x (NEGL y)))) - // result: (ROLL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 32 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGL { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -32 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRL { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32]))) (SHLL x y)) - // result: (ROLL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRL { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGL { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGL { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -32 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHRL x (NEGL y))) (SHLL x y)) - // result: (ROLL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 32 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGL { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -32 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 31 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRL { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_20(v *Value) bool { // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (RORL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLL { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHRL x y) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHLL x (NEGQ y)))) - // result: (RORL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 32 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGQ { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -32 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLL { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32]))) (SHRL x y)) - // result: (RORL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHLL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORL) + v.AddArg(x) + v.AddArg(y) + return true + } } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGQ { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGQ { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -32 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHLL x (NEGQ y))) (SHRL x y)) - // result: (RORL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 32 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGQ { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -32 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 31 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLL { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (RORL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLL { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHLL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORL) + v.AddArg(x) + v.AddArg(y) + return true + } } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true + break } - // match: (ORL (SHRL x y) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHLL x (NEGL y)))) - // result: (RORL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 32 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGL { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -32 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLL { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32]))) (SHRL x y)) - // result: (RORL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGL { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGL { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -32 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHLL x (NEGL y))) (SHRL x y)) - // result: (RORL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 32 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGL { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -32 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 31 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLL { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true - } + return false +} +func rewriteValueAMD64_OpAMD64ORL_10(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRW { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ { - break - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -16 { - break - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 16 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -16 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])) (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 16 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGQ { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -16 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 15 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRW { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGQ { - break - } - v_1_1_1_0 := v_1_1_1.Args[0] - if v_1_1_1_0.Op != OpAMD64ADDQconst || v_1_1_1_0.AuxInt != -16 { - break - } - v_1_1_1_0_0 := v_1_1_1_0.Args[0] - if v_1_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_1_0_0.AuxInt != 15 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_30(v *Value) bool { - // match: (ORL (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16]))) (SHLL x (ANDQconst y [15]))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRW { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRW { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -16 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -16 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64ROLW) + v.AddArg(x) + v.AddArg(y) + return true + } } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGQ { - break - } - v_0_0_1_0 := v_0_0_1.Args[0] - if v_0_0_1_0.Op != OpAMD64ADDQconst || v_0_0_1_0.AuxInt != -16 { - break - } - v_0_0_1_0_0 := v_0_0_1_0.Args[0] - if v_0_0_1_0_0.Op != OpAMD64ANDQconst || v_0_0_1_0_0.AuxInt != 15 { - break - } - y := v_0_0_1_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 16 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGQ { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -16 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 15 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])) (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) (SHLL x (ANDQconst y [15]))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 16 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGQ { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -16 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 15 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRW { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGQ { - break - } - v_0_1_1_0 := v_0_1_1.Args[0] - if v_0_1_1_0.Op != OpAMD64ADDQconst || v_0_1_1_0.AuxInt != -16 { - break - } - v_0_1_1_0_0 := v_0_1_1_0.Args[0] - if v_0_1_1_0_0.Op != OpAMD64ANDQconst || v_0_1_1_0_0.AuxInt != 15 || y != v_0_1_1_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRW { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL { - break - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -16 { - break - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 16 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -16 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])) (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 16 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGL { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -16 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRW { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -16 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -16 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64ROLW) + v.AddArg(x) + v.AddArg(y) + return true + } } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 15 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRW { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGL { - break - } - v_1_1_1_0 := v_1_1_1.Args[0] - if v_1_1_1_0.Op != OpAMD64ADDLconst || v_1_1_1_0.AuxInt != -16 { - break - } - v_1_1_1_0_0 := v_1_1_1_0.Args[0] - if v_1_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_1_0_0.AuxInt != 15 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16]))) (SHLL x (ANDLconst y [15]))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRW { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGL { - break - } - v_0_0_1_0 := v_0_0_1.Args[0] - if v_0_0_1_0.Op != OpAMD64ADDLconst || v_0_0_1_0.AuxInt != -16 { - break - } - v_0_0_1_0_0 := v_0_0_1_0.Args[0] - if v_0_0_1_0_0.Op != OpAMD64ANDLconst || v_0_0_1_0_0.AuxInt != 15 { - break - } - y := v_0_0_1_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 16 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGL { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -16 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 15 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])) (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) (SHLL x (ANDLconst y [15]))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 16 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGL { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -16 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 15 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRW { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGL { - break - } - v_0_1_1_0 := v_0_1_1.Args[0] - if v_0_1_1_0.Op != OpAMD64ADDLconst || v_0_1_1_0.AuxInt != -16 { - break - } - v_0_1_1_0_0 := v_0_1_1_0.Args[0] - if v_0_1_1_0_0.Op != OpAMD64ANDLconst || v_0_1_1_0_0.AuxInt != 15 || y != v_0_1_1_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHRW x (ANDQconst y [15])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRW { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGQ { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64RORW) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -16 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64RORW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SHRW x (ANDQconst y [15]))) - // cond: v.Type.Size() == 2 - // result: (RORW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64NEGQ { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64ADDQconst || v_0_1_0.AuxInt != -16 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0.AuxInt != 15 { - break - } - y := v_0_1_0_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64RORW) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHRW x (ANDLconst y [15])) (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRW { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGL { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -16 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGL { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64RORW) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64RORW) - v.AddArg(x) - v.AddArg(y) - return true + break } - // match: (ORL (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SHRW x (ANDLconst y [15]))) - // cond: v.Type.Size() == 2 - // result: (RORW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64NEGL { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64ADDLconst || v_0_1_0.AuxInt != -16 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0.AuxInt != 15 { - break - } - y := v_0_1_0_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64RORW) - v.AddArg(x) - v.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_40(v *Value) bool { // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRB { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ { - break - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -8 { - break - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 8 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -8 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 8 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGQ { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRB { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -8 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -8 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64ROLB) + v.AddArg(x) + v.AddArg(y) + return true + } } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 7 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRB { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGQ { - break - } - v_1_1_1_0 := v_1_1_1.Args[0] - if v_1_1_1_0.Op != OpAMD64ADDQconst || v_1_1_1_0.AuxInt != -8 { - break - } - v_1_1_1_0_0 := v_1_1_1_0.Args[0] - if v_1_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_1_0_0.AuxInt != 7 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8]))) (SHLL x (ANDQconst y [ 7]))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRB { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGQ { - break - } - v_0_0_1_0 := v_0_0_1.Args[0] - if v_0_0_1_0.Op != OpAMD64ADDQconst || v_0_0_1_0.AuxInt != -8 { - break - } - v_0_0_1_0_0 := v_0_0_1_0.Args[0] - if v_0_0_1_0_0.Op != OpAMD64ANDQconst || v_0_0_1_0_0.AuxInt != 7 { - break - } - y := v_0_0_1_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 8 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGQ { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -8 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 7 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) (SHLL x (ANDQconst y [ 7]))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 8 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGQ { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -8 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 7 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRB { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGQ { - break - } - v_0_1_1_0 := v_0_1_1.Args[0] - if v_0_1_1_0.Op != OpAMD64ADDQconst || v_0_1_1_0.AuxInt != -8 { - break - } - v_0_1_1_0_0 := v_0_1_1_0.Args[0] - if v_0_1_1_0_0.Op != OpAMD64ANDQconst || v_0_1_1_0_0.AuxInt != 7 || y != v_0_1_1_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRB { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL { - break - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -8 { - break - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 8 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -8 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 8 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGL { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRB { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -8 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -8 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64ROLB) + v.AddArg(x) + v.AddArg(y) + return true + } } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 7 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRB { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGL { - break - } - v_1_1_1_0 := v_1_1_1.Args[0] - if v_1_1_1_0.Op != OpAMD64ADDLconst || v_1_1_1_0.AuxInt != -8 { - break - } - v_1_1_1_0_0 := v_1_1_1_0.Args[0] - if v_1_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_1_0_0.AuxInt != 7 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8]))) (SHLL x (ANDLconst y [ 7]))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRB { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGL { - break - } - v_0_0_1_0 := v_0_0_1.Args[0] - if v_0_0_1_0.Op != OpAMD64ADDLconst || v_0_0_1_0.AuxInt != -8 { - break - } - v_0_0_1_0_0 := v_0_0_1_0.Args[0] - if v_0_0_1_0_0.Op != OpAMD64ANDLconst || v_0_0_1_0_0.AuxInt != 7 { - break - } - y := v_0_0_1_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 8 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGL { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -8 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 7 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) (SHLL x (ANDLconst y [ 7]))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 8 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGL { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -8 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 7 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRB { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGL { - break - } - v_0_1_1_0 := v_0_1_1.Args[0] - if v_0_1_1_0.Op != OpAMD64ADDLconst || v_0_1_1_0.AuxInt != -8 { - break - } - v_0_1_1_0_0 := v_0_1_1_0.Args[0] - if v_0_1_1_0_0.Op != OpAMD64ANDLconst || v_0_1_1_0_0.AuxInt != 7 || y != v_0_1_1_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRB { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRB { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGQ { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64RORB) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -8 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64RORB) - v.AddArg(x) - v.AddArg(y) - return true + break } - // match: (ORL (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SHRB x (ANDQconst y [ 7]))) - // cond: v.Type.Size() == 1 - // result: (RORB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64NEGQ { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64ADDQconst || v_0_1_0.AuxInt != -8 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0.AuxInt != 7 { - break - } - y := v_0_1_0_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRB { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64RORB) - v.AddArg(x) - v.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_50(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRB { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRB { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGL { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64RORB) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGL { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -8 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64RORB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SHRB x (ANDLconst y [ 7]))) - // cond: v.Type.Size() == 1 - // result: (RORB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64NEGL { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64ADDLconst || v_0_1_0.AuxInt != -8 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0.AuxInt != 7 { - break - } - y := v_0_1_0_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRB { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64RORB) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL x x) // result: x @@ -26591,4227 +23269,702 @@ // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } - // match: (ORL sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem)) x0:(MOVBload [i0] {s} p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } + return false +} +func rewriteValueAMD64_OpAMD64ORL_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVWload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVWload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem)) x0:(MOVWload [i0] {s} p mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y) s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_60(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem))) s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpAMD64SHLLconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORL { + continue + } + _ = or.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := or.Args[_i1] + if s0.Op != OpAMD64SHLLconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] { + continue + } + y := or.Args[1^_i1] + if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) + v1.AuxInt = j0 + v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v2.AddArg(mem) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(idx) + v0.AddArg(mem) + return true + } + } } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true + break } // match: (ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_70(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVWloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVWloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(idx) + v0.AddArg(mem) + return true + } + } } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true + break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpAMD64SHLLconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORL { + continue + } + _ = or.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s0 := or.Args[_i2] + if s0.Op != OpAMD64SHLLconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i3 := 0; _i3 <= 1; _i3++ { + if p != x0.Args[_i3] || idx != x0.Args[1^_i3] || mem != x0.Args[2] { + continue + } + y := or.Args[1^_i2] + if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) + v1.AuxInt = j0 + v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v2.AddArg(idx) + v2.AddArg(mem) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } + } + } } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_80(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_90(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem)) x1:(MOVBload [i1] {s} p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x1 := v.Args[_i0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { + continue + } + x0 := sh.Args[0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = 8 + v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + r1 := v.Args[_i0] + if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVWload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { + continue + } + r0 := sh.Args[0] + if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVWload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y) s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_100(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem))) s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpAMD64SHLLconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORL { + continue + } + _ = or.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s1 := or.Args[_i1] + if s1.Op != OpAMD64SHLLconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + y := or.Args[1^_i1] + if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) + v1.AuxInt = j1 + v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) + v2.AuxInt = 8 + v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) + v3.AuxInt = i0 + v3.Aux = s + v3.AddArg(p) + v3.AddArg(mem) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORL x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x1 := v.Args[_i0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { + continue + } + x0 := sh.Args[0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = 8 + v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(idx) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } + } } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + r1 := v.Args[_i0] + if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVWloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { + continue + } + r0 := sh.Args[0] + if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVWloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(idx) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } + } } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } return false } -func rewriteValueAMD64_OpAMD64ORL_110(v *Value) bool { +func rewriteValueAMD64_OpAMD64ORL_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types - // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpAMD64SHLLconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORL { + continue + } + _ = or.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s1 := or.Args[_i2] + if s1.Op != OpAMD64SHLLconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i3 := 0; _i3 <= 1; _i3++ { + if p != x1.Args[_i3] || idx != x1.Args[1^_i3] || mem != x1.Args[2] { + continue + } + y := or.Args[1^_i2] + if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) + v1.AuxInt = j1 + v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) + v2.AuxInt = 8 + v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) + v3.AuxInt = i0 + v3.Aux = s + v3.AddArg(p) + v3.AddArg(idx) + v3.AddArg(mem) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } + } + } } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_120(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_130(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ORLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ORL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ORLload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVLload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ORLload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ORLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -31005,7 +24158,7 @@ v.AddArg(mem) return true } - // match: (ORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) + // match: ( ORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: ( ORL x (MOVLf2i y)) for { off := v.AuxInt @@ -31086,1012 +24239,328 @@ return false } func rewriteValueAMD64_OpAMD64ORQ_0(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (ORQ (SHLQ (MOVQconst [1]) y) x) // result: (BTSQ x y) for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQ { - break - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst || v_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTSQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ x (SHLQ (MOVQconst [1]) y)) - // result: (BTSQ x y) - for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQ { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVQconst || v_1_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQ { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVQconst || v_0_0.AuxInt != 1 { + continue + } + x := v.Args[1^_i0] + v.reset(OpAMD64BTSQ) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64BTSQ) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORQ (MOVQconst [c]) x) - // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 - // result: (BTSQconst [log2(c)] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { - break - } - v.reset(OpAMD64BTSQconst) - v.AuxInt = log2(c) - v.AddArg(x) - return true - } - // match: (ORQ x (MOVQconst [c])) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSQconst [log2(c)] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { + continue + } + v.reset(OpAMD64BTSQconst) + v.AuxInt = log2(c) + v.AddArg(x) + return true } - v.reset(OpAMD64BTSQconst) - v.AuxInt = log2(c) - v.AddArg(x) - return true + break } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64ORQconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ORQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ORQ (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (ORQconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ORQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRQconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 64-c) { + continue + } + v.reset(OpAMD64ROLQconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ORQ (SHRQconst x [d]) (SHLQconst x [c])) - // cond: d==64-c - // result: (ROLQconst x [c]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRQ { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBQcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLQ) + v.AddArg(x) + v.AddArg(y) + return true + } } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (SHLQ x y) (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHRQ x (NEGQ y)))) - // result: (ROLQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBQcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 64 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGQ { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -64 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRQ { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_10(v *Value) bool { - // match: (ORQ (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64]))) (SHLQ x y)) - // result: (ROLQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRQ { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGQ { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBQcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGQ { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -64 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHRQ x (NEGQ y))) (SHLQ x y)) - // result: (ROLQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBQcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 64 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGQ { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -64 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 63 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRQ { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRQ { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBQcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (SHLQ x y) (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHRQ x (NEGL y)))) - // result: (ROLQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBQcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 64 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGL { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -64 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRQ { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64]))) (SHLQ x y)) - // result: (ROLQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLQ) + v.AddArg(x) + v.AddArg(y) + return true + } } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGL { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBQcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGL { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -64 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHRQ x (NEGL y))) (SHLQ x y)) - // result: (ROLQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBQcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 64 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGL { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -64 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 63 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRQ { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLQ { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBQcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (SHRQ x y) (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHLQ x (NEGQ y)))) - // result: (RORQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBQcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 64 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGQ { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -64 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLQ { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHLQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORQ) + v.AddArg(x) + v.AddArg(y) + return true + } } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true + break } - // match: (ORQ (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64]))) (SHRQ x y)) - // result: (RORQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGQ { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBQcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGQ { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -64 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHLQ x (NEGQ y))) (SHRQ x y)) - // result: (RORQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBQcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 64 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGQ { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -64 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 63 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLQ { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_20(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLQ { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBQcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (SHRQ x y) (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHLQ x (NEGL y)))) - // result: (RORQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBQcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 64 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGL { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -64 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLQ { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64]))) (SHRQ x y)) - // result: (RORQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHLQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORQ) + v.AddArg(x) + v.AddArg(y) + return true + } } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGL { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBQcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGL { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -64 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHLQ x (NEGL y))) (SHRQ x y)) - // result: (RORQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBQcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 64 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGL { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -64 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 63 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLQ { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORQ x x) // result: x @@ -32110,7693 +24579,1194 @@ // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } - // match: (ORQ sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem)) x0:(MOVBload [i0] {s} p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } + return false +} +func rewriteValueAMD64_OpAMD64ORQ_10(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVWload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVWload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem)) x0:(MOVWload [i0] {s} p mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVLload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVLload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVLload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_30(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem)) x0:(MOVLload [i0] {s} p mem)) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVLload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y) s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem))) s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := or.Args[_i1] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] { + continue + } + y := or.Args[1^_i1] + if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j0 + v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v2.AddArg(mem) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y) s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem))) s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVWload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := or.Args[_i1] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVWload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] { + continue + } + y := or.Args[1^_i1] + if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j0 + v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v2.AddArg(mem) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_40(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(idx) + v0.AddArg(mem) + return true + } + } } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true + break } // match: (ORQ x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_50(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVWloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVWloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(idx) + v0.AddArg(mem) + return true + } + } } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true + break } // match: (ORQ x0:(MOVLloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVLloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVLloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVLloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem)) x0:(MOVLloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_60(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem)) x0:(MOVLloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem)) x0:(MOVLloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem)) x0:(MOVLloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVLloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVLloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(idx) + v0.AddArg(mem) + return true + } + } } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true + break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s0 := or.Args[_i2] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i3 := 0; _i3 <= 1; _i3++ { + if p != x0.Args[_i3] || idx != x0.Args[1^_i3] || mem != x0.Args[2] { + continue + } + y := or.Args[1^_i2] + if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j0 + v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v2.AddArg(idx) + v2.AddArg(mem) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } + } + } } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_70(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_80(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y)) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y)) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVWloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s0 := or.Args[_i2] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVWloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i3 := 0; _i3 <= 1; _i3++ { + if p != x0.Args[_i3] || idx != x0.Args[1^_i3] || mem != x0.Args[2] { + continue + } + y := or.Args[1^_i2] + if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j0 + v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v2.AddArg(idx) + v2.AddArg(mem) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } + } + } } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y)) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_90(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x1 := v.Args[_i0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { + continue + } + x0 := sh.Args[0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = 8 + v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } - // match: (ORQ sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem)) x1:(MOVBload [i1] {s} p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } + return false +} +func rewriteValueAMD64_OpAMD64ORQ_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + r1 := v.Args[_i0] + if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVWload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { + continue + } + r0 := sh.Args[0] + if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVWload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64BSWAPL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + r1 := v.Args[_i0] + if r1.Op != OpAMD64BSWAPL { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVLload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { + continue + } + r0 := sh.Args[0] + if r0.Op != OpAMD64BSWAPL { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVLload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_100(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem))) r1:(BSWAPL x1:(MOVLload [i1] {s} p mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - r1 := v.Args[1] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y) s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem))) s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s1 := or.Args[_i1] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + y := or.Args[1^_i1] + if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j1 + v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) + v2.AuxInt = 8 + v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) + v3.AuxInt = i0 + v3.Aux = s + v3.AddArg(p) + v3.AddArg(mem) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + r0 := s0.Args[0] + if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVWload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s1 := or.Args[_i1] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + r1 := s1.Args[0] + if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVWload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + y := or.Args[1^_i1] + if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j1 + v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) + v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) + v3.AuxInt = i0 + v3.Aux = s + v3.AddArg(p) + v3.AddArg(mem) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_110(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x1 := v.Args[_i0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { + continue + } + x0 := sh.Args[0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = 8 + v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(idx) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } + } } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + r1 := v.Args[_i0] + if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVWloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { + continue + } + r0 := sh.Args[0] + if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVWloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(idx) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } + } } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_120(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + r1 := v.Args[_i0] + if r1.Op != OpAMD64BSWAPL { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVLloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { + continue + } + r0 := sh.Args[0] + if r0.Op != OpAMD64BSWAPL { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVLloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(idx) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } + } } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_130(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s1 := or.Args[_i2] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i3 := 0; _i3 <= 1; _i3++ { + if p != x1.Args[_i3] || idx != x1.Args[1^_i3] || mem != x1.Args[2] { + continue + } + y := or.Args[1^_i2] + if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j1 + v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) + v2.AuxInt = 8 + v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) + v3.AuxInt = i0 + v3.Aux = s + v3.AddArg(p) + v3.AddArg(idx) + v3.AddArg(mem) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } + } + } } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_140(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_150(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y)) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y)) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y)) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + r0 := s0.Args[0] + if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVWloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s1 := or.Args[_i2] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + r1 := s1.Args[0] + if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVWloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i3 := 0; _i3 <= 1; _i3++ { + if p != x1.Args[_i3] || idx != x1.Args[1^_i3] || mem != x1.Args[2] { + continue + } + y := or.Args[1^_i2] + if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j1 + v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) + v3.AuxInt = i0 + v3.Aux = s + v3.AddArg(p) + v3.AddArg(idx) + v3.AddArg(mem) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } + } + } } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_160(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ORQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ORQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ORQload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVQload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ORQload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ORQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -39986,7 +25956,7 @@ v.AddArg(mem) return true } - // match: (ORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) + // match: ( ORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: ( ORQ x (MOVQf2i y)) for { off := v.AuxInt @@ -42497,47 +28467,26 @@ if v_0.Op != OpAMD64TESTL { break } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTL y (SHLL (MOVLconst [1]) x))) - // result: (SETAE (BTL x y)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) @@ -42546,47 +28495,26 @@ if v_0.Op != OpAMD64TESTQ { break } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTQ y (SHLQ (MOVQconst [1]) x))) - // result: (SETAE (BTQ x y)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) @@ -42636,46 +28564,25 @@ if v_0.Op != OpAMD64TESTQ { break } - x := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst { - break - } - c := v_0_0.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTQ x (MOVQconst [c]))) - // cond: isUint64PowerOfTwo(c) - // result: (SETAE (BTQconst [log2(c)] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0_0.AuxInt + x := v_0.Args[1^_i0] + if !(isUint64PowerOfTwo(c)) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = log2(c) + v0.AddArg(x) + v.AddArg(v0) + return true } - c := v_0_1.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) @@ -42713,10 +28620,6 @@ v.AddArg(v0) return true } - return false -} -func rewriteValueAMD64_OpAMD64SETEQ_10(v *Value) bool { - b := v.Block // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) @@ -42725,54 +28628,29 @@ if v_0.Op != OpAMD64TESTQ { break } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) - // cond: z1==z2 - // result: (SETAE (BTQconst [63] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 @@ -42782,54 +28660,29 @@ if v_0.Op != OpAMD64TESTL { break } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) - // cond: z1==z2 - // result: (SETAE (BTQconst [31] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 @@ -42839,55 +28692,34 @@ if v_0.Op != OpAMD64TESTQ { break } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) - // cond: z1==z2 - // result: (SETAE (BTQconst [0] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + return true } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64SETEQ_10(v *Value) bool { + b := v.Block // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) @@ -42896,54 +28728,29 @@ if v_0.Op != OpAMD64TESTL { break } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) - // cond: z1==z2 - // result: (SETAE (BTLconst [0] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 @@ -42953,51 +28760,26 @@ if v_0.Op != OpAMD64TESTQ { break } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTQ z2 z1:(SHRQconst [63] x))) - // cond: z1==z2 - // result: (SETAE (BTQconst [63] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64SETEQ_20(v *Value) bool { - b := v.Block // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) @@ -43006,46 +28788,25 @@ if v_0.Op != OpAMD64TESTL { break } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTL z2 z1:(SHRLconst [31] x))) - // cond: z1==z2 - // result: (SETAE (BTLconst [31] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) @@ -43129,59 +28890,30 @@ if v_1.Op != OpAMD64TESTL { break } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLL { - break - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTL y (SHLL (MOVLconst [1]) x)) mem) - // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_1_0 := v_1.Args[_i0] + if v_1_0.Op != OpAMD64SHLL { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { + continue + } + y := v_1.Args[1^_i0] + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v.AddArg(mem) + return true } - x := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64MOVLconst || v_1_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) @@ -43194,59 +28926,30 @@ if v_1.Op != OpAMD64TESTQ { break } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLQ { - break - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTQ y (SHLQ (MOVQconst [1]) x)) mem) - // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_1_0 := v_1.Args[_i0] + if v_1_0.Op != OpAMD64SHLQ { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { + continue + } + y := v_1.Args[1^_i0] + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v.AddArg(mem) + return true } - x := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64MOVQconst || v_1_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(c) @@ -43316,58 +29019,29 @@ if v_1.Op != OpAMD64TESTQ { break } - x := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVQconst { - break - } - c := v_1_0.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTQ x (MOVQconst [c])) mem) - // cond: isUint64PowerOfTwo(c) - // result: (SETAEstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } _ = v_1.Args[1] - x := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_1_0 := v_1.Args[_i0] + if v_1_0.Op != OpAMD64MOVQconst { + continue + } + c := v_1_0.AuxInt + x := v_1.Args[1^_i0] + if !(isUint64PowerOfTwo(c)) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = log2(c) + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - c := v_1_1.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) @@ -43421,10 +29095,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64SETEQstore_10(v *Value) bool { - b := v.Block // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) @@ -43437,66 +29107,33 @@ if v_1.Op != OpAMD64TESTQ { break } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x))) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 @@ -43510,66 +29147,33 @@ if v_1.Op != OpAMD64TESTL { break } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTL z2 z1:(SHLLconst [31] (SHRLconst [31] x))) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 @@ -43583,67 +29187,39 @@ if v_1.Op != OpAMD64TESTQ { break } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x))) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64SETEQstore_10(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) @@ -43656,66 +29232,33 @@ if v_1.Op != OpAMD64TESTL { break } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x))) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 @@ -43729,64 +29272,30 @@ if v_1.Op != OpAMD64TESTQ { break } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] x)) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + x := z1.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64SETEQstore_20(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) @@ -43799,58 +29308,29 @@ if v_1.Op != OpAMD64TESTL { break } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] x)) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + x := z1.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) @@ -44007,6 +29487,11 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64SETEQstore_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { @@ -45043,47 +30528,26 @@ if v_0.Op != OpAMD64TESTL { break } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTL y (SHLL (MOVLconst [1]) x))) - // result: (SETB (BTL x y)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) @@ -45092,47 +30556,26 @@ if v_0.Op != OpAMD64TESTQ { break } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTQ y (SHLQ (MOVQconst [1]) x))) - // result: (SETB (BTQ x y)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) @@ -45182,46 +30625,25 @@ if v_0.Op != OpAMD64TESTQ { break } - x := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst { - break - } - c := v_0_0.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTQ x (MOVQconst [c]))) - // cond: isUint64PowerOfTwo(c) - // result: (SETB (BTQconst [log2(c)] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0_0.AuxInt + x := v_0.Args[1^_i0] + if !(isUint64PowerOfTwo(c)) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = log2(c) + v0.AddArg(x) + v.AddArg(v0) + return true } - c := v_0_1.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) @@ -45259,10 +30681,6 @@ v.AddArg(v0) return true } - return false -} -func rewriteValueAMD64_OpAMD64SETNE_10(v *Value) bool { - b := v.Block // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) @@ -45271,54 +30689,29 @@ if v_0.Op != OpAMD64TESTQ { break } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) - // cond: z1==z2 - // result: (SETB (BTQconst [63] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 @@ -45328,54 +30721,29 @@ if v_0.Op != OpAMD64TESTL { break } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) - // cond: z1==z2 - // result: (SETB (BTQconst [31] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 @@ -45385,55 +30753,34 @@ if v_0.Op != OpAMD64TESTQ { break } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) - // cond: z1==z2 - // result: (SETB (BTQconst [0] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + return true } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64SETNE_10(v *Value) bool { + b := v.Block // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) @@ -45442,54 +30789,29 @@ if v_0.Op != OpAMD64TESTL { break } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) - // cond: z1==z2 - // result: (SETB (BTLconst [0] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 @@ -45499,51 +30821,26 @@ if v_0.Op != OpAMD64TESTQ { break } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTQ z2 z1:(SHRQconst [63] x))) - // cond: z1==z2 - // result: (SETB (BTQconst [63] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64SETNE_20(v *Value) bool { - b := v.Block // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) @@ -45552,46 +30849,25 @@ if v_0.Op != OpAMD64TESTL { break } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTL z2 z1:(SHRLconst [31] x))) - // cond: z1==z2 - // result: (SETB (BTLconst [31] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETNE (InvertFlags x)) // result: (SETNE x) @@ -45675,59 +30951,30 @@ if v_1.Op != OpAMD64TESTL { break } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLL { - break - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTL y (SHLL (MOVLconst [1]) x)) mem) - // result: (SETBstore [off] {sym} ptr (BTL x y) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_1_0 := v_1.Args[_i0] + if v_1_0.Op != OpAMD64SHLL { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { + continue + } + y := v_1.Args[1^_i0] + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v.AddArg(mem) + return true } - x := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64MOVLconst || v_1_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) @@ -45740,59 +30987,30 @@ if v_1.Op != OpAMD64TESTQ { break } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLQ { - break - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTQ y (SHLQ (MOVQconst [1]) x)) mem) - // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_1_0 := v_1.Args[_i0] + if v_1_0.Op != OpAMD64SHLQ { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { + continue + } + y := v_1.Args[1^_i0] + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v.AddArg(mem) + return true } - x := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64MOVQconst || v_1_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(c) @@ -45862,58 +31080,29 @@ if v_1.Op != OpAMD64TESTQ { break } - x := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVQconst { - break - } - c := v_1_0.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTQ x (MOVQconst [c])) mem) - // cond: isUint64PowerOfTwo(c) - // result: (SETBstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } _ = v_1.Args[1] - x := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_1_0 := v_1.Args[_i0] + if v_1_0.Op != OpAMD64MOVQconst { + continue + } + c := v_1_0.AuxInt + x := v_1.Args[1^_i0] + if !(isUint64PowerOfTwo(c)) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = log2(c) + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - c := v_1_1.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) @@ -45967,10 +31156,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64SETNEstore_10(v *Value) bool { - b := v.Block // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) @@ -45983,66 +31168,33 @@ if v_1.Op != OpAMD64TESTQ { break } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x))) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 @@ -46056,66 +31208,33 @@ if v_1.Op != OpAMD64TESTL { break } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTL z2 z1:(SHLLconst [31] (SHRLconst [31] x))) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 @@ -46129,67 +31248,39 @@ if v_1.Op != OpAMD64TESTQ { break } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x))) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64SETNEstore_10(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) @@ -46202,66 +31293,33 @@ if v_1.Op != OpAMD64TESTL { break } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x))) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 @@ -46275,64 +31333,30 @@ if v_1.Op != OpAMD64TESTQ { break } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] x)) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + x := z1.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64SETNEstore_20(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) @@ -46345,58 +31369,29 @@ if v_1.Op != OpAMD64TESTL { break } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] x)) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + x := z1.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) @@ -46553,6 +31548,11 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64SETNEstore_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { @@ -48516,84 +33516,50 @@ // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [c] x) for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - v.reset(OpAMD64TESTBconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (TESTB x (MOVLconst [c])) - // result: (TESTBconst [c] x) - for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + v.reset(OpAMD64TESTBconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - v.reset(OpAMD64TESTBconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0,off)] ptr mem) for { - l2 := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVBload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true - } - // match: (TESTB l2 l:(MOVBload {sym} [off] ptr mem)) - // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) - // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0,off)] ptr mem) - for { _ = v.Args[1] - l2 := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVBload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := v.Args[_i0] + if l.Op != OpAMD64MOVBload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + l2 := v.Args[1^_i0] + if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { + continue + } + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = makeValAndOff(0, off) + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true + break } return false } @@ -48621,84 +33587,50 @@ // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - v.reset(OpAMD64TESTLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (TESTL x (MOVLconst [c])) - // result: (TESTLconst [c] x) - for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + v.reset(OpAMD64TESTLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - v.reset(OpAMD64TESTLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0,off)] ptr mem) for { - l2 := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true - } - // match: (TESTL l2 l:(MOVLload {sym} [off] ptr mem)) - // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) - // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0,off)] ptr mem) - for { _ = v.Args[1] - l2 := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVLload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := v.Args[_i0] + if l.Op != OpAMD64MOVLload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + l2 := v.Args[1^_i0] + if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { + continue + } + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = makeValAndOff(0, off) + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true + break } return false } @@ -48727,91 +33659,53 @@ // cond: is32Bit(c) // result: (TESTQconst [c] x) for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64TESTQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (TESTQ x (MOVQconst [c])) - // cond: is32Bit(c) - // result: (TESTQconst [c] x) - for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(c)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64TESTQconst) + v.AuxInt = c + v.AddArg(x) + return true } - v.reset(OpAMD64TESTQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0,off)] ptr mem) for { - l2 := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true - } - // match: (TESTQ l2 l:(MOVQload {sym} [off] ptr mem)) - // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) - // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0,off)] ptr mem) - for { _ = v.Args[1] - l2 := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVQload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := v.Args[_i0] + if l.Op != OpAMD64MOVQload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + l2 := v.Args[1^_i0] + if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { + continue + } + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = makeValAndOff(0, off) + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true + break } return false } @@ -48839,84 +33733,50 @@ // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [c] x) for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - v.reset(OpAMD64TESTWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (TESTW x (MOVLconst [c])) - // result: (TESTWconst [c] x) - for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + v.reset(OpAMD64TESTWconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - v.reset(OpAMD64TESTWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0,off)] ptr mem) for { - l2 := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVWload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true - } - // match: (TESTW l2 l:(MOVWload {sym} [off] ptr mem)) - // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) - // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0,off)] ptr mem) - for { _ = v.Args[1] - l2 := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVWload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := v.Args[_i0] + if l.Op != OpAMD64MOVWload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + l2 := v.Args[1^_i0] + if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { + continue + } + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = makeValAndOff(0, off) + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true + break } return false } @@ -49107,153 +33967,91 @@ // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTCL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (XORL x (SHLL (MOVLconst [1]) y)) - // result: (BTCL x y) - for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVLconst || v_1_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { + continue + } + x := v.Args[1^_i0] + v.reset(OpAMD64BTCL) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64BTCL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCLconst [log2uint32(c)] x) for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { - break - } - v.reset(OpAMD64BTCLconst) - v.AuxInt = log2uint32(c) - v.AddArg(x) - return true - } - // match: (XORL x (MOVLconst [c])) - // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 - // result: (BTCLconst [log2uint32(c)] x) - for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break - } - c := v_1.AuxInt - if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { + continue + } + v.reset(OpAMD64BTCLconst) + v.AuxInt = log2uint32(c) + v.AddArg(x) + return true } - v.reset(OpAMD64BTCLconst) - v.AuxInt = log2uint32(c) - v.AddArg(x) - return true + break } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVLconst { + continue + } + c := v_1.AuxInt + v.reset(OpAMD64XORLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - v.reset(OpAMD64XORLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XORL (MOVLconst [c]) x) - // result: (XORLconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - v.reset(OpAMD64XORLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRLconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 32-c) { + continue + } + v.reset(OpAMD64ROLLconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XORL (SHRLconst x [d]) (SHLLconst x [c])) - // cond: d==32-c - // result: (ROLLconst x [c]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRLconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 @@ -49261,102 +34059,55 @@ for { t := v.Type _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRWconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - break - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XORL (SHRWconst x [d]) (SHLLconst x [c])) - // cond: d==16-c && c < 16 && t.Size() == 2 - // result: (ROLWconst x [c]) - for { - t := v.Type - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRWconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRWconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { + continue + } + v.reset(OpAMD64ROLWconst) + v.AuxInt = c + v.AddArg(x) + return true } - v.reset(OpAMD64ROLWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64XORL_10(v *Value) bool { // match: (XORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRBconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - break - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XORL (SHRBconst x [d]) (SHLLconst x [c])) - // cond: d==8-c && c < 8 && t.Size() == 1 - // result: (ROLBconst x [c]) - for { - t := v.Type - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRBconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRBconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { + continue + } + v.reset(OpAMD64ROLBconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - break - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XORL x x) // result: (MOVLconst [0]) @@ -49374,49 +34125,28 @@ // result: (XORLload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64XORLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (XORL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (XORLload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVLload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64XORLload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64XORLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -49835,161 +34565,95 @@ // match: (XORQ (SHLQ (MOVQconst [1]) y) x) // result: (BTCQ x y) for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQ { - break - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst || v_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTCQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (XORQ x (SHLQ (MOVQconst [1]) y)) - // result: (BTCQ x y) - for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQ { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVQconst || v_1_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQ { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVQconst || v_0_0.AuxInt != 1 { + continue + } + x := v.Args[1^_i0] + v.reset(OpAMD64BTCQ) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64BTCQ) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (XORQ (MOVQconst [c]) x) - // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 - // result: (BTCQconst [log2(c)] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { - break - } - v.reset(OpAMD64BTCQconst) - v.AuxInt = log2(c) - v.AddArg(x) - return true - } - // match: (XORQ x (MOVQconst [c])) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCQconst [log2(c)] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { + continue + } + v.reset(OpAMD64BTCQconst) + v.AuxInt = log2(c) + v.AddArg(x) + return true } - v.reset(OpAMD64BTCQconst) - v.AuxInt = log2(c) - v.AddArg(x) - return true + break } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64XORQconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64XORQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XORQ (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (XORQconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64XORQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRQconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 64-c) { + continue + } + v.reset(OpAMD64ROLQconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XORQ (SHRQconst x [d]) (SHLQconst x [c])) - // cond: d==64-c - // result: (ROLQconst x [c]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XORQ x x) // result: (MOVQconst [0]) @@ -50007,52 +34671,28 @@ // result: (XORQload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64XORQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64XORQ_10(v *Value) bool { - // match: (XORQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (XORQload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVQload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVQload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64XORQload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64XORQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -58031,87 +42671,51 @@ // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true - } - // match: (EQ (TESTL y (SHLL (MOVLconst [1]) x))) - // result: (UGE (BTL x y)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true - } - // match: (EQ (TESTQ y (SHLQ (MOVQconst [1]) x))) - // result: (UGE (BTQ x y)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) @@ -58152,333 +42756,191 @@ // result: (UGE (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] - x := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst { - break - } - c := v_0_0.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTQ x (MOVQconst [c]))) - // cond: isUint64PowerOfTwo(c) - // result: (UGE (BTQconst [log2(c)] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0_0.AuxInt + x := v_0.Args[1^_i0] + if !(isUint64PowerOfTwo(c)) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = log2(c) + v0.AddArg(x) + b.AddControl(v0) + return true } - c := v_0_1.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) - // cond: z1==z2 - // result: (UGE (BTQconst [63] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) - // cond: z1==z2 - // result: (UGE (BTQconst [31] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) - // cond: z1==z2 - // result: (UGE (BTQconst [0] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) - // cond: z1==z2 - // result: (UGE (BTLconst [0] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTQ z2 z1:(SHRQconst [63] x))) - // cond: z1==z2 - // result: (UGE (BTQconst [63] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + b.AddControl(v0) + return true } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTL z2 z1:(SHRLconst [31] x))) - // cond: z1==z2 - // result: (UGE (BTLconst [31] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + b.AddControl(v0) + return true } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) @@ -59043,87 +43505,51 @@ // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true - } - // match: (NE (TESTL y (SHLL (MOVLconst [1]) x))) - // result: (ULT (BTL x y)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true - } - // match: (NE (TESTQ y (SHLQ (MOVQconst [1]) x))) - // result: (ULT (BTQ x y)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) @@ -59164,333 +43590,191 @@ // result: (ULT (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] - x := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst { - break - } - c := v_0_0.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTQ x (MOVQconst [c]))) - // cond: isUint64PowerOfTwo(c) - // result: (ULT (BTQconst [log2(c)] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0_0.AuxInt + x := v_0.Args[1^_i0] + if !(isUint64PowerOfTwo(c)) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = log2(c) + v0.AddArg(x) + b.AddControl(v0) + return true } - c := v_0_1.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) - // cond: z1==z2 - // result: (ULT (BTQconst [63] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) - // cond: z1==z2 - // result: (ULT (BTQconst [31] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) - // cond: z1==z2 - // result: (ULT (BTQconst [0] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) - // cond: z1==z2 - // result: (ULT (BTLconst [0] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTQ z2 z1:(SHRQconst [63] x))) - // cond: z1==z2 - // result: (ULT (BTQconst [63] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + b.AddControl(v0) + return true } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTL z2 z1:(SHRLconst [31] x))) - // cond: z1==z2 - // result: (ULT (BTLconst [31] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + b.AddControl(v0) + return true } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) -- diff -- # indent-heuristic: true @@ -13,7 +13,7 @@ case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst_0(v) case OpAMD64ADDL: - return rewriteValueAMD64_OpAMD64ADDL_0(v) || rewriteValueAMD64_OpAMD64ADDL_10(v) || rewriteValueAMD64_OpAMD64ADDL_20(v) + return rewriteValueAMD64_OpAMD64ADDL_0(v) || rewriteValueAMD64_OpAMD64ADDL_10(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst_0(v) || rewriteValueAMD64_OpAMD64ADDLconst_10(v) case OpAMD64ADDLconstmodify: @@ -23,7 +23,7 @@ case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify_0(v) case OpAMD64ADDQ: - return rewriteValueAMD64_OpAMD64ADDQ_0(v) || rewriteValueAMD64_OpAMD64ADDQ_10(v) || rewriteValueAMD64_OpAMD64ADDQ_20(v) + return rewriteValueAMD64_OpAMD64ADDQ_0(v) || rewriteValueAMD64_OpAMD64ADDQ_10(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry_0(v) case OpAMD64ADDQconst: @@ -301,13 +301,13 @@ case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f_0(v) case OpAMD64MOVQload: - return rewriteValueAMD64_OpAMD64MOVQload_0(v) || rewriteValueAMD64_OpAMD64MOVQload_10(v) + return rewriteValueAMD64_OpAMD64MOVQload_0(v) case OpAMD64MOVQloadidx1: return rewriteValueAMD64_OpAMD64MOVQloadidx1_0(v) case OpAMD64MOVQloadidx8: return rewriteValueAMD64_OpAMD64MOVQloadidx8_0(v) case OpAMD64MOVQstore: - return rewriteValueAMD64_OpAMD64MOVQstore_0(v) || rewriteValueAMD64_OpAMD64MOVQstore_10(v) || rewriteValueAMD64_OpAMD64MOVQstore_20(v) || rewriteValueAMD64_OpAMD64MOVQstore_30(v) + return rewriteValueAMD64_OpAMD64MOVQstore_0(v) || rewriteValueAMD64_OpAMD64MOVQstore_10(v) || rewriteValueAMD64_OpAMD64MOVQstore_20(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst_0(v) case OpAMD64MOVQstoreconstidx1: @@ -391,7 +391,7 @@ case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ_0(v) case OpAMD64ORL: - return rewriteValueAMD64_OpAMD64ORL_0(v) || rewriteValueAMD64_OpAMD64ORL_10(v) || rewriteValueAMD64_OpAMD64ORL_20(v) || rewriteValueAMD64_OpAMD64ORL_30(v) || rewriteValueAMD64_OpAMD64ORL_40(v) || rewriteValueAMD64_OpAMD64ORL_50(v) || rewriteValueAMD64_OpAMD64ORL_60(v) || rewriteValueAMD64_OpAMD64ORL_70(v) || rewriteValueAMD64_OpAMD64ORL_80(v) || rewriteValueAMD64_OpAMD64ORL_90(v) || rewriteValueAMD64_OpAMD64ORL_100(v) || rewriteValueAMD64_OpAMD64ORL_110(v) || rewriteValueAMD64_OpAMD64ORL_120(v) || rewriteValueAMD64_OpAMD64ORL_130(v) + return rewriteValueAMD64_OpAMD64ORL_0(v) || rewriteValueAMD64_OpAMD64ORL_10(v) || rewriteValueAMD64_OpAMD64ORL_20(v) || rewriteValueAMD64_OpAMD64ORL_30(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst_0(v) case OpAMD64ORLconstmodify: @@ -401,7 +401,7 @@ case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify_0(v) case OpAMD64ORQ: - return rewriteValueAMD64_OpAMD64ORQ_0(v) || rewriteValueAMD64_OpAMD64ORQ_10(v) || rewriteValueAMD64_OpAMD64ORQ_20(v) || rewriteValueAMD64_OpAMD64ORQ_30(v) || rewriteValueAMD64_OpAMD64ORQ_40(v) || rewriteValueAMD64_OpAMD64ORQ_50(v) || rewriteValueAMD64_OpAMD64ORQ_60(v) || rewriteValueAMD64_OpAMD64ORQ_70(v) || rewriteValueAMD64_OpAMD64ORQ_80(v) || rewriteValueAMD64_OpAMD64ORQ_90(v) || rewriteValueAMD64_OpAMD64ORQ_100(v) || rewriteValueAMD64_OpAMD64ORQ_110(v) || rewriteValueAMD64_OpAMD64ORQ_120(v) || rewriteValueAMD64_OpAMD64ORQ_130(v) || rewriteValueAMD64_OpAMD64ORQ_140(v) || rewriteValueAMD64_OpAMD64ORQ_150(v) || rewriteValueAMD64_OpAMD64ORQ_160(v) + return rewriteValueAMD64_OpAMD64ORQ_0(v) || rewriteValueAMD64_OpAMD64ORQ_10(v) || rewriteValueAMD64_OpAMD64ORQ_20(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst_0(v) case OpAMD64ORQconstmodify: @@ -475,7 +475,7 @@ case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore_0(v) case OpAMD64SETEQ: - return rewriteValueAMD64_OpAMD64SETEQ_0(v) || rewriteValueAMD64_OpAMD64SETEQ_10(v) || rewriteValueAMD64_OpAMD64SETEQ_20(v) + return rewriteValueAMD64_OpAMD64SETEQ_0(v) || rewriteValueAMD64_OpAMD64SETEQ_10(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore_0(v) || rewriteValueAMD64_OpAMD64SETEQstore_10(v) || rewriteValueAMD64_OpAMD64SETEQstore_20(v) case OpAMD64SETG: @@ -495,7 +495,7 @@ case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore_0(v) case OpAMD64SETNE: - return rewriteValueAMD64_OpAMD64SETNE_0(v) || rewriteValueAMD64_OpAMD64SETNE_10(v) || rewriteValueAMD64_OpAMD64SETNE_20(v) + return rewriteValueAMD64_OpAMD64SETNE_0(v) || rewriteValueAMD64_OpAMD64SETNE_10(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore_0(v) || rewriteValueAMD64_OpAMD64SETNEstore_10(v) || rewriteValueAMD64_OpAMD64SETNEstore_20(v) case OpAMD64SHLL: @@ -573,7 +573,7 @@ case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ_0(v) case OpAMD64XORL: - return rewriteValueAMD64_OpAMD64XORL_0(v) || rewriteValueAMD64_OpAMD64XORL_10(v) + return rewriteValueAMD64_OpAMD64XORL_0(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst_0(v) || rewriteValueAMD64_OpAMD64XORLconst_10(v) case OpAMD64XORLconstmodify: @@ -583,7 +583,7 @@ case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify_0(v) case OpAMD64XORQ: - return rewriteValueAMD64_OpAMD64XORQ_0(v) || rewriteValueAMD64_OpAMD64XORQ_10(v) + return rewriteValueAMD64_OpAMD64XORQ_0(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst_0(v) case OpAMD64XORQconstmodify: @@ -1161,40 +1161,23 @@ // result: (ADCQconst x [c] carry) for { carry := v.Args[2] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(c)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64ADCQconst) + v.AuxInt = c + v.AddArg(x) + v.AddArg(carry) + return true } - v.reset(OpAMD64ADCQconst) - v.AuxInt = c - v.AddArg(x) - v.AddArg(carry) - return true - } - // match: (ADCQ (MOVQconst [c]) x carry) - // cond: is32Bit(c) - // result: (ADCQconst x [c] carry) - for { - carry := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - x := v.Args[1] - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ADCQconst) - v.AuxInt = c - v.AddArg(x) - v.AddArg(carry) - return true + break } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) @@ -1236,78 +1219,46 @@ // result: (ADDLconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break - } - c := v_1.AuxInt - v.reset(OpAMD64ADDLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDL (MOVLconst [c]) x) - // result: (ADDLconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVLconst { + continue + } + c := v_1.AuxInt + v.reset(OpAMD64ADDLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - v.reset(OpAMD64ADDLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADDL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRLconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 32-c) { + continue + } + v.reset(OpAMD64ROLLconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDL (SHRLconst x [d]) (SHLLconst x [c])) - // cond: d==32-c - // result: (ROLLconst x [c]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRLconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADDL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 @@ -1315,49 +1266,27 @@ for { t := v.Type _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRWconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - break - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDL (SHRWconst x [d]) (SHLLconst x [c])) - // cond: d==16-c && c < 16 && t.Size() == 2 - // result: (ROLWconst x [c]) - for { - t := v.Type - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRWconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRWconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { + continue + } + v.reset(OpAMD64ROLWconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - break - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADDL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 @@ -1365,405 +1294,221 @@ for { t := v.Type _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRBconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - break - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDL (SHRBconst x [d]) (SHLLconst x [c])) - // cond: d==8-c && c < 8 && t.Size() == 1 - // result: (ROLBconst x [c]) - for { - t := v.Type - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRBconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRBconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { + continue + } + v.reset(OpAMD64ROLBconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - break - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAL8) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL (SHLLconst [3] y) x) - // result: (LEAL8 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 3 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAL8) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAL8) - v.AddArg(x) - v.AddArg(y) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64ADDL_10(v *Value) bool { // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAL4) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL (SHLLconst [2] y) x) - // result: (LEAL4 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 2 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAL4) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAL4) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAL2) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_1.Args[0] - v.reset(OpAMD64LEAL2) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL (SHLLconst [1] y) x) - // result: (LEAL2 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { - break - } - y := v_0.Args[0] - v.reset(OpAMD64LEAL2) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDL { - break - } - y := v_1.Args[1] - if y != v_1.Args[0] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDL { + continue + } + y := v_1.Args[1] + if y != v_1.Args[0] { + continue + } + v.reset(OpAMD64LEAL2) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64LEAL2) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL (ADDL y y) x) - // result: (LEAL2 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDL { - break - } - y := v_0.Args[1] - if y != v_0.Args[0] { - break - } - v.reset(OpAMD64LEAL2) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDL { - break - } - y := v_1.Args[1] - if x != v_1.Args[0] { - break - } - v.reset(OpAMD64LEAL2) - v.AddArg(y) - v.AddArg(x) - return true - } - // match: (ADDL x (ADDL y x)) - // result: (LEAL2 y x) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + if x != v_1.Args[_i1] { + continue + } + y := v_1.Args[1^_i1] + v.reset(OpAMD64LEAL2) + v.AddArg(y) + v.AddArg(x) + return true + } } - _ = v_1.Args[1] - y := v_1.Args[0] - if x != v_1.Args[1] { - break - } - v.reset(OpAMD64LEAL2) - v.AddArg(y) - v.AddArg(x) - return true + break } - // match: (ADDL (ADDL x y) x) - // result: (LEAL2 y x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDL { - break - } - y := v_0.Args[1] - if x != v_0.Args[0] { - break - } - v.reset(OpAMD64LEAL2) - v.AddArg(y) - v.AddArg(x) - return true - } - // match: (ADDL (ADDL y x) x) - // result: (LEAL2 y x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDL { - break - } - _ = v_0.Args[1] - y := v_0.Args[0] - if x != v_0.Args[1] { - break - } - v.reset(OpAMD64LEAL2) - v.AddArg(y) - v.AddArg(x) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ADDL_20(v *Value) bool { // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) - for { - y := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v.reset(OpAMD64LEAL1) - v.AuxInt = c - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL y (ADDLconst [c] x)) - // result: (LEAL1 [c] x y) for { _ = v.Args[1] - y := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + y := v.Args[1^_i0] + v.reset(OpAMD64LEAL1) + v.AuxInt = c + v.AddArg(x) + v.AddArg(y) + return true } - c := v_1.AuxInt - x := v_1.Args[0] - v.reset(OpAMD64LEAL1) - v.AuxInt = c - v.AddArg(x) - v.AddArg(y) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64ADDL_10(v *Value) bool { // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64LEAL { - break - } - c := v_1.AuxInt - s := v_1.Aux - y := v_1.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64LEAL { + continue + } + c := v_1.AuxInt + s := v_1.Aux + y := v_1.Args[0] + if !(x.Op != OpSB && y.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAL1) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64LEAL1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL (LEAL [c] {s} y) x) - // cond: x.Op != OpSB && y.Op != OpSB - // result: (LEAL1 [c] {s} x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64LEAL { - break - } - c := v_0.AuxInt - s := v_0.Aux - y := v_0.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAL1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64NEGL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64NEGL { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64SUBL) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_1.Args[0] - v.reset(OpAMD64SUBL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDL (NEGL y) x) - // result: (SUBL x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64NEGL { - break - } - y := v_0.Args[0] - v.reset(OpAMD64SUBL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ADDLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ADDL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ADDLload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVLload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ADDLload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ADDLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -2162,441 +1907,243 @@ // result: (ADDQconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ADDQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDQ (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (ADDQconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64ADDQconst) + v.AuxInt = c + v.AddArg(x) + return true } - v.reset(OpAMD64ADDQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADDQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRQconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 64-c) { + continue + } + v.reset(OpAMD64ROLQconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDQ (SHRQconst x [d]) (SHLQconst x [c])) - // cond: d==64-c - // result: (ROLQconst x [c]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ8) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDQ (SHLQconst [3] y) x) - // result: (LEAQ8 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAQ8) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAQ8) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ4) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDQ (SHLQconst [2] y) x) - // result: (LEAQ4 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAQ4) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAQ4) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ2) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDQ (SHLQconst [1] y) x) - // result: (LEAQ2 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAQ2) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAQ2) - v.AddArg(x) - v.AddArg(y) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64ADDQ_10(v *Value) bool { // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQ { - break - } - y := v_1.Args[1] - if y != v_1.Args[0] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDQ { + continue + } + y := v_1.Args[1] + if y != v_1.Args[0] { + continue + } + v.reset(OpAMD64LEAQ2) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64LEAQ2) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDQ (ADDQ y y) x) - // result: (LEAQ2 x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - y := v_0.Args[1] - if y != v_0.Args[0] { - break - } - v.reset(OpAMD64LEAQ2) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQ { - break - } - y := v_1.Args[1] - if x != v_1.Args[0] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDQ { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + if x != v_1.Args[_i1] { + continue + } + y := v_1.Args[1^_i1] + v.reset(OpAMD64LEAQ2) + v.AddArg(y) + v.AddArg(x) + return true + } } - v.reset(OpAMD64LEAQ2) - v.AddArg(y) - v.AddArg(x) - return true - } - // match: (ADDQ x (ADDQ y x)) - // result: (LEAQ2 y x) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQ { - break - } - _ = v_1.Args[1] - y := v_1.Args[0] - if x != v_1.Args[1] { - break - } - v.reset(OpAMD64LEAQ2) - v.AddArg(y) - v.AddArg(x) - return true - } - // match: (ADDQ (ADDQ x y) x) - // result: (LEAQ2 y x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - y := v_0.Args[1] - if x != v_0.Args[0] { - break - } - v.reset(OpAMD64LEAQ2) - v.AddArg(y) - v.AddArg(x) - return true - } - // match: (ADDQ (ADDQ y x) x) - // result: (LEAQ2 y x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - _ = v_0.Args[1] - y := v_0.Args[0] - if x != v_0.Args[1] { - break - } - v.reset(OpAMD64LEAQ2) - v.AddArg(y) - v.AddArg(x) - return true + break } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) - for { - y := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v.reset(OpAMD64LEAQ1) - v.AuxInt = c - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDQ y (ADDQconst [c] x)) - // result: (LEAQ1 [c] x y) for { _ = v.Args[1] - y := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDQconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + y := v.Args[1^_i0] + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + v.AddArg(x) + v.AddArg(y) + return true } - c := v_1.AuxInt - x := v_1.Args[0] - v.reset(OpAMD64LEAQ1) - v.AuxInt = c - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64LEAQ { - break - } - c := v_1.AuxInt - s := v_1.Aux - y := v_1.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDQ (LEAQ [c] {s} y) x) - // cond: x.Op != OpSB && y.Op != OpSB - // result: (LEAQ1 [c] {s} x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64LEAQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64LEAQ { + continue + } + c := v_1.AuxInt + s := v_1.Aux + y := v_1.Args[0] + if !(x.Op != OpSB && y.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - c := v_0.AuxInt - s := v_0.Aux - y := v_0.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64ADDQ_20(v *Value) bool { // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64NEGQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64NEGQ { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64SUBQ) + v.AddArg(x) + v.AddArg(y) + return true } - y := v_1.Args[0] - v.reset(OpAMD64SUBQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADDQ (NEGQ y) x) - // result: (SUBQ x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64NEGQ { - break - } - y := v_0.Args[0] - v.reset(OpAMD64SUBQ) - v.AddArg(x) - v.AddArg(y) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64ADDQ_10(v *Value) bool { // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ADDQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ADDQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ADDQload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVQload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ADDQload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ADDQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -2606,37 +2153,22 @@ // result: (ADDQconstcarry x [c]) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ADDQconstcarry) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADDQcarry (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (ADDQconstcarry x [c]) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64ADDQconstcarry) + v.AuxInt = c + v.AddArg(x) + return true } - v.reset(OpAMD64ADDQconstcarry) - v.AuxInt = c - v.AddArg(x) - return true + break } return false } @@ -3037,49 +2569,28 @@ // result: (ADDSDload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVSDload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ADDSDload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ADDSD l:(MOVSDload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ADDSDload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVSDload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVSDload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ADDSDload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ADDSDload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -3169,49 +2680,28 @@ // result: (ADDSSload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVSSload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ADDSSload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ADDSS l:(MOVSSload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ADDSSload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVSSload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVSSload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ADDSSload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ADDSSload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -3298,114 +2788,69 @@ func rewriteValueAMD64_OpAMD64ANDL_0(v *Value) bool { // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64NOTL { - break - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break - } - y := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTRL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ANDL x (NOTL (SHLL (MOVLconst [1]) y))) - // result: (BTRL x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64NOTL { - break - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLL { - break - } - y := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64NOTL { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SHLL { + continue + } + y := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { + continue + } + x := v.Args[1^_i0] + v.reset(OpAMD64BTRL) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64BTRL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRLconst [log2uint32(^c)] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { - break - } - v.reset(OpAMD64BTRLconst) - v.AuxInt = log2uint32(^c) - v.AddArg(x) - return true - } - // match: (ANDL x (MOVLconst [c])) - // cond: isUint32PowerOfTwo(^c) && uint64(^c) >= 128 - // result: (BTRLconst [log2uint32(^c)] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break - } - c := v_1.AuxInt - if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(isUint32PowerOfTwo(^c) && uint64(^c) >= 128) { + continue + } + v.reset(OpAMD64BTRLconst) + v.AuxInt = log2uint32(^c) + v.AddArg(x) + return true } - v.reset(OpAMD64BTRLconst) - v.AuxInt = log2uint32(^c) - v.AddArg(x) - return true + break } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVLconst { + continue + } + c := v_1.AuxInt + v.reset(OpAMD64ANDLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - v.reset(OpAMD64ANDLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ANDL (MOVLconst [c]) x) - // result: (ANDLconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - v.reset(OpAMD64ANDLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ANDL x x) // result: x @@ -3424,49 +2869,28 @@ // result: (ANDLload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ANDLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ANDL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ANDLload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVLload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ANDLload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ANDLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -3765,122 +3189,73 @@ func rewriteValueAMD64_OpAMD64ANDQ_0(v *Value) bool { // match: (ANDQ (NOTQ (SHLQ (MOVQconst [1]) y)) x) // result: (BTRQ x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64NOTQ { - break - } - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break - } - y := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTRQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ANDQ x (NOTQ (SHLQ (MOVQconst [1]) y))) - // result: (BTRQ x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64NOTQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64NOTQ { + continue + } + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64SHLQ { + continue + } + y := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { + continue + } + x := v.Args[1^_i0] + v.reset(OpAMD64BTRQ) + v.AddArg(x) + v.AddArg(y) + return true } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLQ { - break - } - y := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTRQ) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ANDQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 // result: (BTRQconst [log2(^c)] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { - break - } - v.reset(OpAMD64BTRQconst) - v.AuxInt = log2(^c) - v.AddArg(x) - return true - } - // match: (ANDQ x (MOVQconst [c])) - // cond: isUint64PowerOfTwo(^c) && uint64(^c) >= 128 - // result: (BTRQconst [log2(^c)] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { + continue + } + v.reset(OpAMD64BTRQconst) + v.AuxInt = log2(^c) + v.AddArg(x) + return true } - v.reset(OpAMD64BTRQconst) - v.AuxInt = log2(^c) - v.AddArg(x) - return true + break } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64ANDQconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ANDQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ANDQ (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (ANDQconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ANDQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ANDQ x x) // result: x @@ -3899,49 +3274,28 @@ // result: (ANDQload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ANDQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ANDQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ANDQload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVQload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ANDQload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ANDQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -10208,39 +9562,21 @@ if v_0.Op != OpAMD64ADDL { break } - y := v_0.Args[1] - x := v_0.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAL1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAL [c] {s} (ADDL y x)) - // cond: x.Op != OpSB && y.Op != OpSB - // result: (LEAL1 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDL { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := v_0.Args[_i0] + y := v_0.Args[1^_i0] + if !(x.Op != OpSB && y.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAL1) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - x := v_0.Args[1] - y := v_0.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAL1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } return false } @@ -10248,49 +9584,29 @@ // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) - for { - c := v.AuxInt - s := v.Aux - y := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDLconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - if !(is32Bit(c+d) && x.Op != OpSB) { - break - } - v.reset(OpAMD64LEAL1) - v.AuxInt = c + d - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAL1 [c] {s} y (ADDLconst [d] x)) - // cond: is32Bit(c+d) && x.Op != OpSB - // result: (LEAL1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] - y := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDLconst { - break - } - d := v_1.AuxInt - x := v_1.Args[0] - if !(is32Bit(c+d) && x.Op != OpSB) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDLconst { + continue + } + d := v_0.AuxInt + x := v_0.Args[0] + y := v.Args[1^_i0] + if !(is32Bit(c+d) && x.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAL1) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64LEAL1) - v.AuxInt = c + d - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) @@ -10298,36 +9614,21 @@ c := v.AuxInt s := v.Aux _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAL2) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - y := v_1.Args[0] - v.reset(OpAMD64LEAL2) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAL1 [c] {s} (SHLLconst [1] y) x) - // result: (LEAL2 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 1 { - break - } - y := v_0.Args[0] - v.reset(OpAMD64LEAL2) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) @@ -10335,36 +9636,21 @@ c := v.AuxInt s := v.Aux _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAL4) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAL1 [c] {s} (SHLLconst [2] y) x) - // result: (LEAL4 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 2 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 2 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAL4) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAL4) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) @@ -10372,36 +9658,21 @@ c := v.AuxInt s := v.Aux _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLLconst || v_1.AuxInt != 3 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAL8) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - y := v_1.Args[0] - v.reset(OpAMD64LEAL8) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAL1 [c] {s} (SHLLconst [3] y) x) - // result: (LEAL8 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst || v_0.AuxInt != 3 { - break - } - y := v_0.Args[0] - v.reset(OpAMD64LEAL8) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } return false } @@ -10644,39 +9915,21 @@ if v_0.Op != OpAMD64ADDQ { break } - y := v_0.Args[1] - x := v_0.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAQ [c] {s} (ADDQ y x)) - // cond: x.Op != OpSB && y.Op != OpSB - // result: (LEAQ1 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := v_0.Args[_i0] + y := v_0.Args[1^_i0] + if !(x.Op != OpSB && y.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - x := v_0.Args[1] - y := v_0.Args[0] - if !(x.Op != OpSB && y.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) @@ -10802,49 +10055,29 @@ // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(c+d) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) - for { - c := v.AuxInt - s := v.Aux - y := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - if !(is32Bit(c+d) && x.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = c + d - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAQ1 [c] {s} y (ADDQconst [d] x)) - // cond: is32Bit(c+d) && x.Op != OpSB - // result: (LEAQ1 [c+d] {s} x y) for { c := v.AuxInt s := v.Aux _ = v.Args[1] - y := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - x := v_1.Args[0] - if !(is32Bit(c+d) && x.Op != OpSB) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDQconst { + continue + } + d := v_0.AuxInt + x := v_0.Args[0] + y := v.Args[1^_i0] + if !(is32Bit(c+d) && x.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = c + d + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64LEAQ1) - v.AuxInt = c + d - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) @@ -10852,36 +10085,21 @@ c := v.AuxInt s := v.Aux _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAQ2) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ2) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAQ1 [c] {s} (SHLQconst [1] y) x) - // result: (LEAQ2 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { - break - } - y := v_0.Args[0] - v.reset(OpAMD64LEAQ2) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) @@ -10889,36 +10107,21 @@ c := v.AuxInt s := v.Aux _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ4) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAQ1 [c] {s} (SHLQconst [2] y) x) - // result: (LEAQ4 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAQ4) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAQ4) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) @@ -10926,85 +10129,49 @@ c := v.AuxInt s := v.Aux _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { - break - } - y := v_1.Args[0] - v.reset(OpAMD64LEAQ8) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAQ1 [c] {s} (SHLQconst [3] y) x) - // result: (LEAQ8 [c] {s} x y) - for { - c := v.AuxInt - s := v.Aux - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { + continue + } + y := v_1.Args[0] + v.reset(OpAMD64LEAQ8) + v.AuxInt = c + v.Aux = s + v.AddArg(x) + v.AddArg(y) + return true } - y := v_0.Args[0] - v.reset(OpAMD64LEAQ8) - v.AuxInt = c - v.Aux = s - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) - for { - off1 := v.AuxInt - sym1 := v.Aux - y := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64LEAQ { - break - } - off2 := v_0.AuxInt - sym2 := v_0.Aux - x := v_0.Args[0] - if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = off1 + off2 - v.Aux = mergeSym(sym1, sym2) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (LEAQ1 [off1] {sym1} y (LEAQ [off2] {sym2} x)) - // cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB - // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := v.AuxInt sym1 := v.Aux _ = v.Args[1] - y := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64LEAQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64LEAQ { + continue + } + off2 := v_0.AuxInt + sym2 := v_0.Aux + x := v_0.Args[0] + y := v.Args[1^_i0] + if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { + continue + } + v.reset(OpAMD64LEAQ1) + v.AuxInt = off1 + off2 + v.Aux = mergeSym(sym1, sym2) + v.AddArg(x) + v.AddArg(y) + return true } - off2 := v_1.AuxInt - sym2 := v_1.Aux - x := v_1.Args[0] - if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB) { - break - } - v.reset(OpAMD64LEAQ1) - v.AuxInt = off1 + off2 - v.Aux = mergeSym(sym1, sym2) - v.AddArg(x) - v.AddArg(y) - return true + break } return false } @@ -11801,42 +10968,22 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVBloadidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVBloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVBload [off] {sym} (ADDQ idx ptr) mem) - // cond: ptr.Op != OpSB - // result: (MOVBloadidx1 [off] {sym} ptr idx mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVBloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVBload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) @@ -11910,48 +11057,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break - } - d := v_0.AuxInt - ptr := v_0.Args[0] - idx := v.Args[1] - if !(is32Bit(c + d)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDQconst { + continue + } + d := v_0.AuxInt + ptr := v_0.Args[0] + idx := v.Args[1^_i0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVBloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVBloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVBloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) - // cond: is32Bit(c+d) - // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - idx := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - ptr := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVBloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVBloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) @@ -11960,48 +11085,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - idx := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVBloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVBloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) - // cond: is32Bit(c+d) - // result: (MOVBloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDQconst { + continue + } + d := v_1.AuxInt + idx := v_1.Args[0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVBloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - d := v_0.AuxInt - idx := v_0.Args[0] - ptr := v.Args[1] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVBloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVBloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) @@ -12010,44 +11113,24 @@ i := v.AuxInt s := v.Aux mem := v.Args[2] - p := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVBload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true - } - // match: (MOVBloadidx1 [i] {s} (MOVQconst [c]) p mem) - // cond: is32Bit(i+c) - // result: (MOVBload [i+c] {s} p mem) - for { - i := v.AuxInt - s := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + p := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(i + c)) { + continue + } + v.reset(OpAMD64MOVBload) + v.AuxInt = i + c + v.Aux = s + v.AddArg(p) + v.AddArg(mem) + return true } - c := v_0.AuxInt - p := v.Args[1] - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVBload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true + break } return false } @@ -12472,46 +11555,24 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + val := v.Args[1] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVBstoreidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVBstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true - } - // match: (MOVBstore [off] {sym} (ADDQ idx ptr) val mem) - // cond: ptr.Op != OpSB - // result: (MOVBstoreidx1 [off] {sym} ptr idx val mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVBstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true + break } // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) @@ -12545,10 +11606,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVBstore_20(v *Value) bool { - b := v.Block // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) @@ -12604,6 +11661,11 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVBstore_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) @@ -12949,11 +12011,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVBstore_30(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1) && clobber(x2) && clobber(mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) @@ -12999,6 +12056,9 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVBstore_30(v *Value) bool { // match: (MOVBstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) @@ -14373,42 +13433,22 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVLloadidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVLloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVLload [off] {sym} (ADDQ idx ptr) mem) - // cond: ptr.Op != OpSB - // result: (MOVLloadidx1 [off] {sym} ptr idx mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVLloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVLload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) @@ -14457,11 +13497,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVLload_10(v *Value) bool { - b := v.Block - config := b.Func.Config // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { @@ -14482,6 +13517,11 @@ v.AddArg(val) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVLload_10(v *Value) bool { + b := v.Block + config := b.Func.Config // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, off, config.BigEndian))]) @@ -14506,39 +13546,22 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 2 { + continue + } + idx := v_1.Args[0] + v.reset(OpAMD64MOVLloadidx4) + v.AuxInt = c + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - idx := v_1.Args[0] - v.reset(OpAMD64MOVLloadidx4) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVLloadidx1 [c] {sym} (SHLQconst [2] idx) ptr mem) - // result: (MOVLloadidx4 [c] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 2 { - break - } - idx := v_0.Args[0] - ptr := v.Args[1] - v.reset(OpAMD64MOVLloadidx4) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVLloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) // result: (MOVLloadidx8 [c] {sym} ptr idx mem) @@ -14546,39 +13569,22 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { + continue + } + idx := v_1.Args[0] + v.reset(OpAMD64MOVLloadidx8) + v.AuxInt = c + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - idx := v_1.Args[0] - v.reset(OpAMD64MOVLloadidx8) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVLloadidx1 [c] {sym} (SHLQconst [3] idx) ptr mem) - // result: (MOVLloadidx8 [c] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { - break - } - idx := v_0.Args[0] - ptr := v.Args[1] - v.reset(OpAMD64MOVLloadidx8) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVLloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) @@ -14587,48 +13593,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break - } - d := v_0.AuxInt - ptr := v_0.Args[0] - idx := v.Args[1] - if !(is32Bit(c + d)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDQconst { + continue + } + d := v_0.AuxInt + ptr := v_0.Args[0] + idx := v.Args[1^_i0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVLloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVLloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVLloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) - // cond: is32Bit(c+d) - // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - idx := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - ptr := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVLloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVLloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) @@ -14637,48 +13621,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - idx := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVLloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVLloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) - // cond: is32Bit(c+d) - // result: (MOVLloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDQconst { + continue + } + d := v_1.AuxInt + idx := v_1.Args[0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVLloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - d := v_0.AuxInt - idx := v_0.Args[0] - ptr := v.Args[1] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVLloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVLloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) @@ -14687,44 +13649,24 @@ i := v.AuxInt s := v.Aux mem := v.Args[2] - p := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVLload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true - } - // match: (MOVLloadidx1 [i] {s} (MOVQconst [c]) p mem) - // cond: is32Bit(i+c) - // result: (MOVLload [i+c] {s} p mem) - for { - i := v.AuxInt - s := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + p := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(i + c)) { + continue + } + v.reset(OpAMD64MOVLload) + v.AuxInt = i + c + v.Aux = s + v.AddArg(p) + v.AddArg(mem) + return true } - c := v_0.AuxInt - p := v.Args[1] - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVLload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true + break } return false } @@ -15113,52 +14055,30 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + val := v.Args[1] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVLstoreidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVLstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true + break } return false } func rewriteValueAMD64_OpAMD64MOVLstore_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types - // match: (MOVLstore [off] {sym} (ADDQ idx ptr) val mem) - // cond: ptr.Op != OpSB - // result: (MOVLstoreidx1 [off] {sym} ptr idx val mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVLstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true - } // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w mem) @@ -15418,41 +14338,9 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVLstore_20(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDLmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64ADDL { - break - } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ADDLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVLstore {sym} [off] ptr y:(ADDL x l:(MOVLload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (ADDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux @@ -15463,23 +14351,32 @@ break } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64ADDLmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - v.reset(OpAMD64ADDLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64MOVLstore_20(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (SUBLmodify [off] {sym} ptr x mem) @@ -15512,35 +14409,6 @@ // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDLmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64ANDL { - break - } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ANDLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVLstore {sym} [off] ptr y:(ANDL x l:(MOVLload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (ANDLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux @@ -15551,55 +14419,32 @@ break } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64ANDLmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ANDLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORLmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64ORL { - break - } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ORLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVLstore {sym} [off] ptr y:(ORL x l:(MOVLload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (ORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux @@ -15610,55 +14455,32 @@ break } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64ORLmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ORLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORLmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64XORL { - break - } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64XORLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVLstore {sym} [off] ptr y:(XORL x l:(MOVLload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (XORLmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux @@ -15669,22 +14491,28 @@ break } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVLload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64XORLmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64XORLmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } // match: (MOVLstore {sym} [off] ptr y:(BTCL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) @@ -15715,9 +14543,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVLstore_30(v *Value) bool { // match: (MOVLstore {sym} [off] ptr y:(BTRL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (BTRLmodify [off] {sym} ptr x mem) @@ -15863,6 +14688,9 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVLstore_30(v *Value) bool { // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (XORLconstmodify {sym} [makeValAndOff(c,off)] ptr mem) @@ -17069,6 +15897,8 @@ return false } func rewriteValueAMD64_OpAMD64MOVQload_0(v *Value) bool { + b := v.Block + config := b.Func.Config // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x @@ -17204,42 +16034,22 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVQloadidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVQloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVQload [off] {sym} (ADDQ idx ptr) mem) - // cond: ptr.Op != OpSB - // result: (MOVQloadidx1 [off] {sym} ptr idx mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVQloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVQload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) @@ -17308,11 +16118,6 @@ v.AddArg(val) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVQload_10(v *Value) bool { - b := v.Block - config := b.Func.Config // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, off, config.BigEndian))]) @@ -17337,39 +16142,22 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 3 { + continue + } + idx := v_1.Args[0] + v.reset(OpAMD64MOVQloadidx8) + v.AuxInt = c + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - idx := v_1.Args[0] - v.reset(OpAMD64MOVQloadidx8) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVQloadidx1 [c] {sym} (SHLQconst [3] idx) ptr mem) - // result: (MOVQloadidx8 [c] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 3 { - break - } - idx := v_0.Args[0] - ptr := v.Args[1] - v.reset(OpAMD64MOVQloadidx8) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVQloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) @@ -17378,48 +16166,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break - } - d := v_0.AuxInt - ptr := v_0.Args[0] - idx := v.Args[1] - if !(is32Bit(c + d)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDQconst { + continue + } + d := v_0.AuxInt + ptr := v_0.Args[0] + idx := v.Args[1^_i0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVQloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVQloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVQloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) - // cond: is32Bit(c+d) - // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - idx := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - ptr := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVQloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVQloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) @@ -17428,48 +16194,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - idx := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVQloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVQloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) - // cond: is32Bit(c+d) - // result: (MOVQloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDQconst { + continue + } + d := v_1.AuxInt + idx := v_1.Args[0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVQloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - d := v_0.AuxInt - idx := v_0.Args[0] - ptr := v.Args[1] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVQloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVQloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) @@ -17478,44 +16222,24 @@ i := v.AuxInt s := v.Aux mem := v.Args[2] - p := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVQload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true - } - // match: (MOVQloadidx1 [i] {s} (MOVQconst [c]) p mem) - // cond: is32Bit(i+c) - // result: (MOVQload [i+c] {s} p mem) - for { - i := v.AuxInt - s := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + p := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(i + c)) { + continue + } + v.reset(OpAMD64MOVQload) + v.AuxInt = i + c + v.Aux = s + v.AddArg(p) + v.AddArg(mem) + return true } - c := v_0.AuxInt - p := v.Args[1] - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVQload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true + break } return false } @@ -17737,46 +16461,24 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + val := v.Args[1] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVQstoreidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVQstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true - } - // match: (MOVQstore [off] {sym} (ADDQ idx ptr) val mem) - // cond: ptr.Op != OpSB - // result: (MOVQstoreidx1 [off] {sym} ptr idx val mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVQstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true + break } // match: (MOVQstore [off1] {sym1} (LEAL [off2] {sym2} base) val mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) @@ -17854,9 +16556,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVQstore_10(v *Value) bool { // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) @@ -17882,6 +16581,9 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVQstore_10(v *Value) bool { // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) @@ -17935,35 +16637,6 @@ // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ADDQmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64ADDQ { - break - } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ADDQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVQstore {sym} [off] ptr y:(ADDQ x l:(MOVQload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (ADDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux @@ -17974,22 +16647,28 @@ break } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64ADDQmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ADDQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) @@ -18023,35 +16702,6 @@ // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ANDQmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64ANDQ { - break - } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ANDQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVQstore {sym} [off] ptr y:(ANDQ x l:(MOVQload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (ANDQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux @@ -18062,55 +16712,32 @@ break } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64ANDQmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ANDQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (ORQmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64ORQ { - break - } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64ORQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVQstore {sym} [off] ptr y:(ORQ x l:(MOVQload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (ORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux @@ -18121,58 +16748,32 @@ break } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64ORQmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - v.reset(OpAMD64ORQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVQstore_20(v *Value) bool { // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) // result: (XORQmodify [off] {sym} ptr x mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - y := v.Args[1] - if y.Op != OpAMD64XORQ { - break - } - x := y.Args[1] - l := y.Args[0] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break - } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64XORQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true - } - // match: (MOVQstore {sym} [off] ptr y:(XORQ x l:(MOVQload [off] {sym} ptr mem)) mem) - // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) - // result: (XORQmodify [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux @@ -18183,22 +16784,28 @@ break } _ = y.Args[1] - x := y.Args[0] - l := y.Args[1] - if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := y.Args[_i0] + if l.Op != OpAMD64MOVQload || l.AuxInt != off || l.Aux != sym { + continue + } + _ = l.Args[1] + if ptr != l.Args[0] || mem != l.Args[1] { + continue + } + x := y.Args[1^_i0] + if !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { + continue + } + v.reset(OpAMD64XORQmodify) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(x) + v.AddArg(mem) + return true } - _ = l.Args[1] - if ptr != l.Args[0] || mem != l.Args[1] || !(y.Uses == 1 && l.Uses == 1 && clobber(y) && clobber(l)) { - break - } - v.reset(OpAMD64XORQmodify) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(x) - v.AddArg(mem) - return true + break } // match: (MOVQstore {sym} [off] ptr y:(BTCQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) @@ -18287,6 +16894,9 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVQstore_20(v *Value) bool { // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (ADDQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) @@ -18432,9 +17042,6 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64MOVQstore_30(v *Value) bool { // match: (MOVQstore [off] {sym} ptr a:(BTRQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) && clobber(l) && clobber(a) // result: (BTRQconstmodify {sym} [makeValAndOff(c,off)] ptr mem) @@ -19139,42 +17746,22 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVSDloadidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVSDloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVSDload [off] {sym} (ADDQ idx ptr) mem) - // cond: ptr.Op != OpSB - // result: (MOVSDloadidx1 [off] {sym} ptr idx mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVSDloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) @@ -19489,46 +18076,24 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + val := v.Args[1] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVSDstoreidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVSDstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true - } - // match: (MOVSDstore [off] {sym} (ADDQ idx ptr) val mem) - // cond: ptr.Op != OpSB - // result: (MOVSDstoreidx1 [off] {sym} ptr idx val mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVSDstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true + break } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) @@ -19849,42 +18414,22 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVSSloadidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVSSloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVSSload [off] {sym} (ADDQ idx ptr) mem) - // cond: ptr.Op != OpSB - // result: (MOVSSloadidx1 [off] {sym} ptr idx mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVSSloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) @@ -20199,46 +18744,24 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + val := v.Args[1] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVSSstoreidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVSSstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true - } - // match: (MOVSSstore [off] {sym} (ADDQ idx ptr) val mem) - // cond: ptr.Op != OpSB - // result: (MOVSSstoreidx1 [off] {sym} ptr idx val mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVSSstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true + break } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) @@ -20941,42 +19464,22 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - if !(ptr.Op != OpSB) { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVWloadidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVWloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVWload [off] {sym} (ADDQ idx ptr) mem) - // cond: ptr.Op != OpSB - // result: (MOVWloadidx1 [off] {sym} ptr idx mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break - } - ptr := v_0.Args[1] - idx := v_0.Args[0] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVWloadidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVWload [off1] {sym1} (LEAL [off2] {sym2} base) mem) // cond: canMergeSym(sym1, sym2) && is32Bit(off1+off2) @@ -21049,39 +19552,22 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { - break - } - idx := v_1.Args[0] - v.reset(OpAMD64MOVWloadidx2) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVWloadidx1 [c] {sym} (SHLQconst [1] idx) ptr mem) - // result: (MOVWloadidx2 [c] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst || v_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLQconst || v_1.AuxInt != 1 { + continue + } + idx := v_1.Args[0] + v.reset(OpAMD64MOVWloadidx2) + v.AuxInt = c + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - idx := v_0.Args[0] - ptr := v.Args[1] - v.reset(OpAMD64MOVWloadidx2) - v.AuxInt = c - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVWloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem) // cond: is32Bit(c+d) @@ -21090,48 +19576,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break - } - d := v_0.AuxInt - ptr := v_0.Args[0] - idx := v.Args[1] - if !(is32Bit(c + d)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64ADDQconst { + continue + } + d := v_0.AuxInt + ptr := v_0.Args[0] + idx := v.Args[1^_i0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVWloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - v.reset(OpAMD64MOVWloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVWloadidx1 [c] {sym} idx (ADDQconst [d] ptr) mem) - // cond: is32Bit(c+d) - // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - idx := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - ptr := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVWloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVWloadidx1 [c] {sym} ptr (ADDQconst [d] idx) mem) // cond: is32Bit(c+d) @@ -21140,48 +19604,26 @@ c := v.AuxInt sym := v.Aux mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ADDQconst { - break - } - d := v_1.AuxInt - idx := v_1.Args[0] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVWloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true - } - // match: (MOVWloadidx1 [c] {sym} (ADDQconst [d] idx) ptr mem) - // cond: is32Bit(c+d) - // result: (MOVWloadidx1 [c+d] {sym} ptr idx mem) - for { - c := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ADDQconst { + continue + } + d := v_1.AuxInt + idx := v_1.Args[0] + if !(is32Bit(c + d)) { + continue + } + v.reset(OpAMD64MOVWloadidx1) + v.AuxInt = c + d + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(mem) + return true } - d := v_0.AuxInt - idx := v_0.Args[0] - ptr := v.Args[1] - if !(is32Bit(c + d)) { - break - } - v.reset(OpAMD64MOVWloadidx1) - v.AuxInt = c + d - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(mem) - return true + break } // match: (MOVWloadidx1 [i] {s} p (MOVQconst [c]) mem) // cond: is32Bit(i+c) @@ -21190,44 +19632,24 @@ i := v.AuxInt s := v.Aux mem := v.Args[2] - p := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVWload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true - } - // match: (MOVWloadidx1 [i] {s} (MOVQconst [c]) p mem) - // cond: is32Bit(i+c) - // result: (MOVWload [i+c] {s} p mem) - for { - i := v.AuxInt - s := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + p := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(i + c)) { + continue + } + v.reset(OpAMD64MOVWload) + v.AuxInt = i + c + v.Aux = s + v.AddArg(p) + v.AddArg(mem) + return true } - c := v_0.AuxInt - p := v.Args[1] - if !(is32Bit(i + c)) { - break - } - v.reset(OpAMD64MOVWload) - v.AuxInt = i + c - v.Aux = s - v.AddArg(p) - v.AddArg(mem) - return true + break } return false } @@ -21512,52 +19934,25 @@ if v_0.Op != OpAMD64ADDQ { break } - idx := v_0.Args[1] - ptr := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVWstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true - } - // match: (MOVWstore [off] {sym} (ADDQ idx ptr) val mem) - // cond: ptr.Op != OpSB - // result: (MOVWstoreidx1 [off] {sym} ptr idx val mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ADDQ { - break + _ = v_0.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + ptr := v_0.Args[_i0] + idx := v_0.Args[1^_i0] + val := v.Args[1] + if !(ptr.Op != OpSB) { + continue + } + v.reset(OpAMD64MOVWstoreidx1) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v.AddArg(idx) + v.AddArg(val) + v.AddArg(mem) + return true } - ptr := v_0.Args[1] - idx := v_0.Args[0] - val := v.Args[1] - if !(ptr.Op != OpSB) { - break - } - v.reset(OpAMD64MOVWstoreidx1) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v.AddArg(idx) - v.AddArg(val) - v.AddArg(mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64MOVWstore_10(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) @@ -21587,6 +19982,11 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64MOVWstore_10(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) @@ -22626,30 +21026,19 @@ // result: (MULLconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break - } - c := v_1.AuxInt - v.reset(OpAMD64MULLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (MULL (MOVLconst [c]) x) - // result: (MULLconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVLconst { + continue + } + c := v_1.AuxInt + v.reset(OpAMD64MULLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - v.reset(OpAMD64MULLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } return false } @@ -23138,37 +21527,22 @@ // result: (MULQconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64MULQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (MULQ (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (MULQconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64MULQconst) + v.AuxInt = c + v.AddArg(x) + return true } - v.reset(OpAMD64MULQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } return false } @@ -23679,49 +22053,28 @@ // result: (MULSDload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVSDload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64MULSDload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (MULSD l:(MOVSDload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (MULSDload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVSDload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVSDload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64MULSDload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64MULSDload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -23811,49 +22164,28 @@ // result: (MULSSload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVSSload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64MULSSload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (MULSS l:(MOVSSload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (MULSSload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVSSload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVSSload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64MULSSload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64MULSSload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -24084,154 +22416,92 @@ func rewriteValueAMD64_OpAMD64ORL_0(v *Value) bool { // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTSL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL x (SHLL (MOVLconst [1]) y)) - // result: (BTSL x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVLconst || v_1_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { + continue + } + x := v.Args[1^_i0] + v.reset(OpAMD64BTSL) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64BTSL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSLconst [log2uint32(c)] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { - break - } - v.reset(OpAMD64BTSLconst) - v.AuxInt = log2uint32(c) - v.AddArg(x) - return true - } - // match: (ORL x (MOVLconst [c])) - // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 - // result: (BTSLconst [log2uint32(c)] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break - } - c := v_1.AuxInt - if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { + continue + } + v.reset(OpAMD64BTSLconst) + v.AuxInt = log2uint32(c) + v.AddArg(x) + return true } - v.reset(OpAMD64BTSLconst) - v.AuxInt = log2uint32(c) - v.AddArg(x) - return true + break } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVLconst { + continue + } + c := v_1.AuxInt + v.reset(OpAMD64ORLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - v.reset(OpAMD64ORLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ORL (MOVLconst [c]) x) - // result: (ORLconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - v.reset(OpAMD64ORLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRLconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 32-c) { + continue + } + v.reset(OpAMD64ROLLconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ORL (SHRLconst x [d]) (SHLLconst x [c])) - // cond: d==32-c - // result: (ROLLconst x [c]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRLconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 @@ -24239,2340 +22509,748 @@ for { t := v.Type _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRWconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { + continue + } + v.reset(OpAMD64ROLWconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRWconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - break - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } - // match: (ORL (SHRWconst x [d]) (SHLLconst x [c])) - // cond: d==16-c && c < 16 && t.Size() == 2 - // result: (ROLWconst x [c]) - for { - t := v.Type - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRWconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - break - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_10(v *Value) bool { // match: (ORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRBconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - break - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ORL (SHRBconst x [d]) (SHLLconst x [c])) - // cond: d==8-c && c < 8 && t.Size() == 1 - // result: (ROLBconst x [c]) - for { - t := v.Type - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRBconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRBconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { + continue + } + v.reset(OpAMD64ROLBconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - break - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRL { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x y) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHRL x (NEGQ y)))) - // result: (ROLL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 32 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGQ { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -32 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRL { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHRL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32]))) (SHLL x y)) - // result: (ROLL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLL) + v.AddArg(x) + v.AddArg(y) + return true + } } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGQ { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGQ { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -32 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHRL x (NEGQ y))) (SHLL x y)) - // result: (ROLL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 32 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGQ { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -32 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 31 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRL { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHLL x y) (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (ROLL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRL { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLL) + v.AddArg(x) + v.AddArg(y) + return true + } } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true + break } - // match: (ORL (SHLL x y) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHRL x (NEGL y)))) - // result: (ROLL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 32 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGL { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -32 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRL { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHRL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32]))) (SHLL x y)) - // result: (ROLL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRL { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGL { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGL { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -32 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHRL x (NEGL y))) (SHLL x y)) - // result: (ROLL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 32 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGL { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -32 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 31 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRL { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLL) - v.AddArg(x) - v.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_20(v *Value) bool { // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])))) // result: (RORL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLL { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHRL x y) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHLL x (NEGQ y)))) - // result: (RORL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 32 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGQ { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -32 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLL { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHLL x (NEGQ y)) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32]))) (SHRL x y)) - // result: (RORL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHLL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORL) + v.AddArg(x) + v.AddArg(y) + return true + } } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGQ { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGQ { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -32 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [31]) [-32])) [32])) (SHLL x (NEGQ y))) (SHRL x y)) - // result: (RORL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 32 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGQ { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -32 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 31 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLL { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHRL x y) (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])))) // result: (RORL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLL { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHLL { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -32 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORL) + v.AddArg(x) + v.AddArg(y) + return true + } } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 31 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHRL x y) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHLL x (NEGL y)))) - // result: (RORL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 32 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGL { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -32 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 31 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLL { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHLL x (NEGL y)) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32]))) (SHRL x y)) - // result: (RORL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGL { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGL { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -32 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 31 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [31]) [-32])) [32])) (SHLL x (NEGL y))) (SHRL x y)) - // result: (RORL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 32 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGL { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -32 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 31 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLL { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORL) - v.AddArg(x) - v.AddArg(y) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64ORL_10(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRW { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ { - break - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -16 { - break - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 16 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -16 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x (ANDQconst y [15])) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])) (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 16 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGQ { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -16 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 15 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRW { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGQ { - break - } - v_1_1_1_0 := v_1_1_1.Args[0] - if v_1_1_1_0.Op != OpAMD64ADDQconst || v_1_1_1_0.AuxInt != -16 { - break - } - v_1_1_1_0_0 := v_1_1_1_0.Args[0] - if v_1_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_1_0_0.AuxInt != 15 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_30(v *Value) bool { - // match: (ORL (ANDL (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16]))) (SHLL x (ANDQconst y [15]))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRW { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRW { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -16 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -16 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64ROLW) + v.AddArg(x) + v.AddArg(y) + return true + } } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGQ { - break - } - v_0_0_1_0 := v_0_0_1.Args[0] - if v_0_0_1_0.Op != OpAMD64ADDQconst || v_0_0_1_0.AuxInt != -16 { - break - } - v_0_0_1_0_0 := v_0_0_1_0.Args[0] - if v_0_0_1_0_0.Op != OpAMD64ANDQconst || v_0_0_1_0_0.AuxInt != 15 { - break - } - y := v_0_0_1_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 16 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGQ { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -16 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 15 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [15]) [-16])) [16])) (SHRW x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) (SHLL x (ANDQconst y [15]))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 16 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGQ { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -16 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 15 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRW { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGQ { - break - } - v_0_1_1_0 := v_0_1_1.Args[0] - if v_0_1_1_0.Op != OpAMD64ADDQconst || v_0_1_1_0.AuxInt != -16 { - break - } - v_0_1_1_0_0 := v_0_1_1_0.Args[0] - if v_0_1_1_0_0.Op != OpAMD64ANDQconst || v_0_1_1_0_0.AuxInt != 15 || y != v_0_1_1_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])))) // cond: v.Type.Size() == 2 // result: (ROLW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRW { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL { - break - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -16 { - break - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 16 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -16 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x (ANDLconst y [15])) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])) (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 16 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGL { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -16 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRW { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -16 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 15 || y != v_1_0_1_0_0.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -16 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 15 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64ROLW) + v.AddArg(x) + v.AddArg(y) + return true + } } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 15 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRW { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGL { - break - } - v_1_1_1_0 := v_1_1_1.Args[0] - if v_1_1_1_0.Op != OpAMD64ADDLconst || v_1_1_1_0.AuxInt != -16 { - break - } - v_1_1_1_0_0 := v_1_1_1_0.Args[0] - if v_1_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_1_0_0.AuxInt != 15 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16]))) (SHLL x (ANDLconst y [15]))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRW { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGL { - break - } - v_0_0_1_0 := v_0_0_1.Args[0] - if v_0_0_1_0.Op != OpAMD64ADDLconst || v_0_0_1_0.AuxInt != -16 { - break - } - v_0_0_1_0_0 := v_0_0_1_0.Args[0] - if v_0_0_1_0_0.Op != OpAMD64ANDLconst || v_0_0_1_0_0.AuxInt != 15 { - break - } - y := v_0_0_1_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 16 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGL { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -16 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 15 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [15]) [-16])) [16])) (SHRW x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) (SHLL x (ANDLconst y [15]))) - // cond: v.Type.Size() == 2 - // result: (ROLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 16 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGL { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -16 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 15 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRW { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGL { - break - } - v_0_1_1_0 := v_0_1_1.Args[0] - if v_0_1_1_0.Op != OpAMD64ADDLconst || v_0_1_1_0.AuxInt != -16 { - break - } - v_0_1_1_0_0 := v_0_1_1_0.Args[0] - if v_0_1_1_0_0.Op != OpAMD64ANDLconst || v_0_1_1_0_0.AuxInt != 15 || y != v_0_1_1_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64ROLW) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHRW x (ANDQconst y [15])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRW { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGQ { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64RORW) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 15 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -16 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64RORW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x (NEGQ (ADDQconst (ANDQconst y [15]) [-16]))) (SHRW x (ANDQconst y [15]))) - // cond: v.Type.Size() == 2 - // result: (RORW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64NEGQ { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64ADDQconst || v_0_1_0.AuxInt != -16 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0.AuxInt != 15 { - break - } - y := v_0_1_0_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64RORW) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHRW x (ANDLconst y [15])) (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16])))) // cond: v.Type.Size() == 2 // result: (RORW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRW { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGL { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -16 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 15 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGL { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -16 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 15 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 2) { + continue + } + v.reset(OpAMD64RORW) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64RORW) - v.AddArg(x) - v.AddArg(y) - return true + break } - // match: (ORL (SHLL x (NEGL (ADDLconst (ANDLconst y [15]) [-16]))) (SHRW x (ANDLconst y [15]))) - // cond: v.Type.Size() == 2 - // result: (RORW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64NEGL { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64ADDLconst || v_0_1_0.AuxInt != -16 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0.AuxInt != 15 { - break - } - y := v_0_1_0_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 15 || y != v_1_1.Args[0] || !(v.Type.Size() == 2) { - break - } - v.reset(OpAMD64RORW) - v.AddArg(x) - v.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_40(v *Value) bool { // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRB { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ { - break - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -8 { - break - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 8 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -8 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x (ANDQconst y [ 7])) (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 8 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGQ { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRB { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDQconst || v_1_0_1_0.AuxInt != -8 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDQconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -8 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64ROLB) + v.AddArg(x) + v.AddArg(y) + return true + } } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 7 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRB { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGQ { - break - } - v_1_1_1_0 := v_1_1_1.Args[0] - if v_1_1_1_0.Op != OpAMD64ADDQconst || v_1_1_1_0.AuxInt != -8 { - break - } - v_1_1_1_0_0 := v_1_1_1_0.Args[0] - if v_1_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_1_0_0.AuxInt != 7 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8]))) (SHLL x (ANDQconst y [ 7]))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRB { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGQ { - break - } - v_0_0_1_0 := v_0_0_1.Args[0] - if v_0_0_1_0.Op != OpAMD64ADDQconst || v_0_0_1_0.AuxInt != -8 { - break - } - v_0_0_1_0_0 := v_0_0_1_0.Args[0] - if v_0_0_1_0_0.Op != OpAMD64ANDQconst || v_0_0_1_0_0.AuxInt != 7 { - break - } - y := v_0_0_1_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 8 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGQ { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -8 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 7 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) (SHLL x (ANDQconst y [ 7]))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 8 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGQ { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -8 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 7 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRB { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGQ { - break - } - v_0_1_1_0 := v_0_1_1.Args[0] - if v_0_1_1_0.Op != OpAMD64ADDQconst || v_0_1_1_0.AuxInt != -8 { - break - } - v_0_1_1_0_0 := v_0_1_1_0.Args[0] - if v_0_1_1_0_0.Op != OpAMD64ANDQconst || v_0_1_1_0_0.AuxInt != 7 || y != v_0_1_1_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])))) // cond: v.Type.Size() == 1 // result: (ROLB x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRB { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL { - break - } - v_1_0_1_0 := v_1_0_1.Args[0] - if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -8 { - break - } - v_1_0_1_0_0 := v_1_0_1_0.Args[0] - if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBLcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 8 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -8 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x (ANDLconst y [ 7])) (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDL { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBLcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 8 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGL { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDL { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRB { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL { + continue + } + v_1_0_1_0 := v_1_0_1.Args[0] + if v_1_0_1_0.Op != OpAMD64ADDLconst || v_1_0_1_0.AuxInt != -8 { + continue + } + v_1_0_1_0_0 := v_1_0_1_0.Args[0] + if v_1_0_1_0_0.Op != OpAMD64ANDLconst || v_1_0_1_0_0.AuxInt != 7 || y != v_1_0_1_0_0.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBLcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -8 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 7 || y != v_1_1_0_0_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64ROLB) + v.AddArg(x) + v.AddArg(y) + return true + } } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 7 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRB { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGL { - break - } - v_1_1_1_0 := v_1_1_1.Args[0] - if v_1_1_1_0.Op != OpAMD64ADDLconst || v_1_1_1_0.AuxInt != -8 { - break - } - v_1_1_1_0_0 := v_1_1_1_0.Args[0] - if v_1_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_1_0_0.AuxInt != 7 || y != v_1_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8]))) (SHLL x (ANDLconst y [ 7]))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRB { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGL { - break - } - v_0_0_1_0 := v_0_0_1.Args[0] - if v_0_0_1_0.Op != OpAMD64ADDLconst || v_0_0_1_0.AuxInt != -8 { - break - } - v_0_0_1_0_0 := v_0_0_1_0.Args[0] - if v_0_0_1_0_0.Op != OpAMD64ANDLconst || v_0_0_1_0_0.AuxInt != 7 { - break - } - y := v_0_0_1_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBLcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 8 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGL { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -8 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 7 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (ANDL (SBBLcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])) [ 8])) (SHRB x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) (SHLL x (ANDLconst y [ 7]))) - // cond: v.Type.Size() == 1 - // result: (ROLB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDL { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBLcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 8 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGL { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -8 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 7 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRB { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGL { - break - } - v_0_1_1_0 := v_0_1_1.Args[0] - if v_0_1_1_0.Op != OpAMD64ADDLconst || v_0_1_1_0.AuxInt != -8 { - break - } - v_0_1_1_0_0 := v_0_1_1_0.Args[0] - if v_0_1_1_0_0.Op != OpAMD64ANDLconst || v_0_1_1_0_0.AuxInt != 7 || y != v_0_1_1_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64ROLB) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL (SHRB x (ANDQconst y [ 7])) (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRB { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRB { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGQ { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64RORB) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDQconst || v_0_1.AuxInt != 7 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGQ { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDQconst || v_1_1_0.AuxInt != -8 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64RORB) - v.AddArg(x) - v.AddArg(y) - return true + break } - // match: (ORL (SHLL x (NEGQ (ADDQconst (ANDQconst y [ 7]) [ -8]))) (SHRB x (ANDQconst y [ 7]))) - // cond: v.Type.Size() == 1 - // result: (RORB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64NEGQ { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64ADDQconst || v_0_1_0.AuxInt != -8 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0.AuxInt != 7 { - break - } - y := v_0_1_0_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRB { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDQconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64RORB) - v.AddArg(x) - v.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_50(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (ORL (SHRB x (ANDLconst y [ 7])) (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8])))) // cond: v.Type.Size() == 1 // result: (RORB x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRB { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRB { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHLL { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpAMD64NEGL { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -8 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { + continue + } + v.reset(OpAMD64RORB) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64ANDLconst || v_0_1.AuxInt != 7 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64NEGL { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64ADDLconst || v_1_1_0.AuxInt != -8 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0.AuxInt != 7 || y != v_1_1_0_0.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64RORB) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORL (SHLL x (NEGL (ADDLconst (ANDLconst y [ 7]) [ -8]))) (SHRB x (ANDLconst y [ 7]))) - // cond: v.Type.Size() == 1 - // result: (RORB x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64NEGL { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64ADDLconst || v_0_1_0.AuxInt != -8 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0.AuxInt != 7 { - break - } - y := v_0_1_0_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRB { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64ANDLconst || v_1_1.AuxInt != 7 || y != v_1_1.Args[0] || !(v.Type.Size() == 1) { - break - } - v.reset(OpAMD64RORB) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORL x x) // result: x @@ -26591,4227 +23269,702 @@ // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem)) x0:(MOVBload [i0] {s} p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64ORL_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVWload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVWload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem)) x0:(MOVWload [i0] {s} p mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y) s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_60(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem))) s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpAMD64SHLLconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORL { + continue + } + _ = or.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := or.Args[_i1] + if s0.Op != OpAMD64SHLLconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] { + continue + } + y := or.Args[1^_i1] + if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) + v1.AuxInt = j0 + v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v2.AddArg(mem) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(idx) + v0.AddArg(mem) + return true + } + } } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true + break } // match: (ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_70(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORL sh:(SHLLconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVWloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVWloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(idx) + v0.AddArg(mem) + return true + } + } } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true + break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpAMD64SHLLconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORL { + continue + } + _ = or.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s0 := or.Args[_i2] + if s0.Op != OpAMD64SHLLconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i3 := 0; _i3 <= 1; _i3++ { + if p != x0.Args[_i3] || idx != x0.Args[1^_i3] || mem != x0.Args[2] { + continue + } + y := or.Args[1^_i2] + if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) + v1.AuxInt = j0 + v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v2.AddArg(idx) + v2.AddArg(mem) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } + } + } } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_80(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_90(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL or:(ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem)) x1:(MOVBload [i1] {s} p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x1 := v.Args[_i0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { + continue + } + x0 := sh.Args[0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = 8 + v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + r1 := v.Args[_i0] + if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVWload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { + continue + } + r0 := sh.Args[0] + if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVWload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y) s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_100(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem))) s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpAMD64SHLLconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORL { + continue + } + _ = or.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s1 := or.Args[_i1] + if s1.Op != OpAMD64SHLLconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + y := or.Args[1^_i1] + if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) + v1.AuxInt = j1 + v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) + v2.AuxInt = 8 + v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) + v3.AuxInt = i0 + v3.Aux = s + v3.AddArg(p) + v3.AddArg(mem) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORL x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x1 := v.Args[_i0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 8 { + continue + } + x0 := sh.Args[0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = 8 + v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(idx) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } + } } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + r1 := v.Args[_i0] + if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVWloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { + continue + } + r0 := sh.Args[0] + if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVWloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(idx) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } + } } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } return false } -func rewriteValueAMD64_OpAMD64ORL_110(v *Value) bool { +func rewriteValueAMD64_OpAMD64ORL_30(v *Value) bool { b := v.Block typ := &b.Func.Config.Types - // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORL sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLLconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpAMD64SHLLconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORL { + continue + } + _ = or.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s1 := or.Args[_i2] + if s1.Op != OpAMD64SHLLconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i3 := 0; _i3 <= 1; _i3++ { + if p != x1.Args[_i3] || idx != x1.Args[1^_i3] || mem != x1.Args[2] { + continue + } + y := or.Args[1^_i2] + if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) + v1.AuxInt = j1 + v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) + v2.AuxInt = 8 + v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) + v3.AuxInt = i0 + v3.Aux = s + v3.AddArg(p) + v3.AddArg(idx) + v3.AddArg(mem) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } + } + } } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_120(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORL_130(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORL or:(ORL s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORL or:(ORL y s1:(SHLLconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLLconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORL { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLLconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLLconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ORLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ORL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ORLload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVLload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ORLload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ORLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -31005,7 +24158,7 @@ v.AddArg(mem) return true } - // match: (ORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) + // match: ( ORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: ( ORL x (MOVLf2i y)) for { off := v.AuxInt @@ -31086,1012 +24239,328 @@ return false } func rewriteValueAMD64_OpAMD64ORQ_0(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (ORQ (SHLQ (MOVQconst [1]) y) x) // result: (BTSQ x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQ { - break - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst || v_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTSQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ x (SHLQ (MOVQconst [1]) y)) - // result: (BTSQ x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQ { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVQconst || v_1_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQ { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVQconst || v_0_0.AuxInt != 1 { + continue + } + x := v.Args[1^_i0] + v.reset(OpAMD64BTSQ) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64BTSQ) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTSQconst [log2(c)] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { - break - } - v.reset(OpAMD64BTSQconst) - v.AuxInt = log2(c) - v.AddArg(x) - return true - } - // match: (ORQ x (MOVQconst [c])) - // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 - // result: (BTSQconst [log2(c)] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { + continue + } + v.reset(OpAMD64BTSQconst) + v.AuxInt = log2(c) + v.AddArg(x) + return true } - v.reset(OpAMD64BTSQconst) - v.AuxInt = log2(c) - v.AddArg(x) - return true + break } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64ORQconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ORQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ORQ (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (ORQconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64ORQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRQconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 64-c) { + continue + } + v.reset(OpAMD64ROLQconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ORQ (SHRQconst x [d]) (SHLQconst x [c])) - // cond: d==64-c - // result: (ROLQconst x [c]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRQ { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBQcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLQ) + v.AddArg(x) + v.AddArg(y) + return true + } } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (SHLQ x y) (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHRQ x (NEGQ y)))) - // result: (ROLQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBQcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 64 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGQ { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -64 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRQ { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_10(v *Value) bool { - // match: (ORQ (ANDQ (SHRQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64]))) (SHLQ x y)) - // result: (ROLQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRQ { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGQ { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBQcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGQ { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -64 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHRQ x (NEGQ y))) (SHLQ x y)) - // result: (ROLQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBQcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 64 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGQ { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -64 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 63 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRQ { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORQ (SHLQ x y) (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (ROLQ x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHRQ { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBQcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (SHLQ x y) (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHRQ x (NEGL y)))) - // result: (ROLQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBQcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 64 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGL { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -64 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHRQ { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (ANDQ (SHRQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64]))) (SHLQ x y)) - // result: (ROLQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHRQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHRQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64ROLQ) + v.AddArg(x) + v.AddArg(y) + return true + } } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGL { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBQcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGL { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -64 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHRQ x (NEGL y))) (SHLQ x y)) - // result: (ROLQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBQcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 64 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGL { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -64 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 63 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHRQ { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64ROLQ) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLQ { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBQcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGQ { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (SHRQ x y) (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHLQ x (NEGQ y)))) - // result: (RORQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBQcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPQconst || v_1_0_0.AuxInt != 64 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGQ { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDQconst || v_1_0_0_0_0.AuxInt != -64 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDQconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLQ { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGQ || y != v_1_1_1.Args[0] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHLQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGQ || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPQconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGQ { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDQconst || v_1_1_0_0_0.AuxInt != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDQconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORQ) + v.AddArg(x) + v.AddArg(y) + return true + } } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true + break } - // match: (ORQ (ANDQ (SHLQ x (NEGQ y)) (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64]))) (SHRQ x y)) - // result: (RORQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break - } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGQ { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBQcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPQconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGQ { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDQconst || v_0_1_0_0_0.AuxInt != -64 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDQconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (ANDQ (SBBQcarrymask (CMPQconst (NEGQ (ADDQconst (ANDQconst y [63]) [-64])) [64])) (SHLQ x (NEGQ y))) (SHRQ x y)) - // result: (RORQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBQcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPQconst || v_0_0_0.AuxInt != 64 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGQ { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDQconst || v_0_0_0_0_0.AuxInt != -64 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDQconst || v_0_0_0_0_0_0.AuxInt != 63 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLQ { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGQ || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_20(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (ORQ (SHRQ x y) (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])))) // result: (RORQ x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLQ { - break - } - _ = v_1_0.Args[1] - if x != v_1_0.Args[0] { - break - } - v_1_0_1 := v_1_0.Args[1] - if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SBBQcarrymask { - break - } - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_0_0 := v_1_1_0.Args[0] - if v_1_1_0_0.Op != OpAMD64NEGL { - break - } - v_1_1_0_0_0 := v_1_1_0_0.Args[0] - if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { - break - } - v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] - if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (SHRQ x y) (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHLQ x (NEGL y)))) - // result: (RORQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQ { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64ANDQ { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SBBQcarrymask { - break - } - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64CMPLconst || v_1_0_0.AuxInt != 64 { - break - } - v_1_0_0_0 := v_1_0_0.Args[0] - if v_1_0_0_0.Op != OpAMD64NEGL { - break - } - v_1_0_0_0_0 := v_1_0_0_0.Args[0] - if v_1_0_0_0_0.Op != OpAMD64ADDLconst || v_1_0_0_0_0.AuxInt != -64 { - break - } - v_1_0_0_0_0_0 := v_1_0_0_0_0.Args[0] - if v_1_0_0_0_0_0.Op != OpAMD64ANDLconst || v_1_0_0_0_0_0.AuxInt != 63 || y != v_1_0_0_0_0_0.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLQ { - break - } - _ = v_1_1.Args[1] - if x != v_1_1.Args[0] { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpAMD64NEGL || y != v_1_1_1.Args[0] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (ANDQ (SHLQ x (NEGL y)) (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64]))) (SHRQ x y)) - // result: (RORQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHRQ { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64ANDQ { + continue + } + _ = v_1.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + v_1_0 := v_1.Args[_i1] + if v_1_0.Op != OpAMD64SHLQ { + continue + } + _ = v_1_0.Args[1] + if x != v_1_0.Args[0] { + continue + } + v_1_0_1 := v_1_0.Args[1] + if v_1_0_1.Op != OpAMD64NEGL || y != v_1_0_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1^_i1] + if v_1_1.Op != OpAMD64SBBQcarrymask { + continue + } + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpAMD64CMPLconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_0_0 := v_1_1_0.Args[0] + if v_1_1_0_0.Op != OpAMD64NEGL { + continue + } + v_1_1_0_0_0 := v_1_1_0_0.Args[0] + if v_1_1_0_0_0.Op != OpAMD64ADDLconst || v_1_1_0_0_0.AuxInt != -64 { + continue + } + v_1_1_0_0_0_0 := v_1_1_0_0_0.Args[0] + if v_1_1_0_0_0_0.Op != OpAMD64ANDLconst || v_1_1_0_0_0_0.AuxInt != 63 || y != v_1_1_0_0_0_0.Args[0] { + continue + } + v.reset(OpAMD64RORQ) + v.AddArg(x) + v.AddArg(y) + return true + } } - _ = v_0_0.Args[1] - x := v_0_0.Args[0] - v_0_0_1 := v_0_0.Args[1] - if v_0_0_1.Op != OpAMD64NEGL { - break - } - y := v_0_0_1.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SBBQcarrymask { - break - } - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64CMPLconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_0_0 := v_0_1_0.Args[0] - if v_0_1_0_0.Op != OpAMD64NEGL { - break - } - v_0_1_0_0_0 := v_0_1_0_0.Args[0] - if v_0_1_0_0_0.Op != OpAMD64ADDLconst || v_0_1_0_0_0.AuxInt != -64 { - break - } - v_0_1_0_0_0_0 := v_0_1_0_0_0.Args[0] - if v_0_1_0_0_0_0.Op != OpAMD64ANDLconst || v_0_1_0_0_0_0.AuxInt != 63 || y != v_0_1_0_0_0_0.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ORQ (ANDQ (SBBQcarrymask (CMPLconst (NEGL (ADDLconst (ANDLconst y [63]) [-64])) [64])) (SHLQ x (NEGL y))) (SHRQ x y)) - // result: (RORQ x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64ANDQ { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SBBQcarrymask { - break - } - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64CMPLconst || v_0_0_0.AuxInt != 64 { - break - } - v_0_0_0_0 := v_0_0_0.Args[0] - if v_0_0_0_0.Op != OpAMD64NEGL { - break - } - v_0_0_0_0_0 := v_0_0_0_0.Args[0] - if v_0_0_0_0_0.Op != OpAMD64ADDLconst || v_0_0_0_0_0.AuxInt != -64 { - break - } - v_0_0_0_0_0_0 := v_0_0_0_0_0.Args[0] - if v_0_0_0_0_0_0.Op != OpAMD64ANDLconst || v_0_0_0_0_0_0.AuxInt != 63 { - break - } - y := v_0_0_0_0_0_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLQ { - break - } - _ = v_0_1.Args[1] - x := v_0_1.Args[0] - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpAMD64NEGL || y != v_0_1_1.Args[0] { - break - } - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQ { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] || y != v_1.Args[1] { - break - } - v.reset(OpAMD64RORQ) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ORQ x x) // result: x @@ -32110,7693 +24579,1194 @@ // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem)) x0:(MOVBload [i0] {s} p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64ORQ_10(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVWload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVWload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem)) x0:(MOVWload [i0] {s} p mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVLload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVLload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVLload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_30(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem)) x0:(MOVLload [i0] {s} p mem)) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVLload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y) s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem))) s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := or.Args[_i1] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] { + continue + } + y := or.Args[1^_i1] + if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j0 + v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v2.AddArg(mem) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y) s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem))) s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVWload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := or.Args[_i1] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVWload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] { + continue + } + y := or.Args[1^_i1] + if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j0 + v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v2.AddArg(mem) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_40(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVBloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVBloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} p idx mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [8] x1:(MOVBloadidx1 [i1] {s} idx p mem)) x0:(MOVBloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVWloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(idx) + v0.AddArg(mem) + return true + } + } } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true + break } // match: (ORQ x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVWloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_50(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ x0:(MOVWloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} p idx mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [16] x1:(MOVWloadidx1 [i1] {s} idx p mem)) x0:(MOVWloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVLloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVWloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVWloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(idx) + v0.AddArg(mem) + return true + } + } } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true + break } // match: (ORQ x0:(MOVLloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) for { _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVLloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVLloadidx1 [i0] {s} p idx mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ x0:(MOVLloadidx1 [i0] {s} idx p mem) sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem)) x0:(MOVLloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_60(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem)) x0:(MOVLloadidx1 [i0] {s} p idx mem)) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} p idx mem)) x0:(MOVLloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true - } - // match: (ORQ sh:(SHLQconst [32] x1:(MOVLloadidx1 [i1] {s} idx p mem)) x0:(MOVLloadidx1 [i0] {s} idx p mem)) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (MOVQloadidx1 [i0] {s} p idx mem) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - x0 := v.Args[1] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpAMD64MOVLloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { + continue + } + x1 := sh.Args[0] + if x1.Op != OpAMD64MOVLloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x1.Args[_i2] || idx != x1.Args[1^_i2] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(idx) + v0.AddArg(mem) + return true + } + } } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(idx) - v0.AddArg(mem) - return true + break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s0 := or.Args[_i2] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i3 := 0; _i3 <= 1; _i3++ { + if p != x0.Args[_i3] || idx != x0.Args[1^_i3] || mem != x0.Args[2] { + continue + } + y := or.Args[1^_i2] + if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j0 + v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v2.AddArg(idx) + v2.AddArg(mem) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } + } + } } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_70(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) for { _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_80(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y)) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y)) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVWloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s0 := or.Args[_i2] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVWloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i3 := 0; _i3 <= 1; _i3++ { + if p != x0.Args[_i3] || idx != x0.Args[1^_i3] || mem != x0.Args[2] { + continue + } + y := or.Args[1^_i2] + if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j0 + v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v2.AddArg(idx) + v2.AddArg(mem) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } + } + } } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y)) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem)) or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_90(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem)) y) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s0 := or.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} p idx mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s0:(SHLQconst [j0] x0:(MOVWloadidx1 [i0] {s} idx p mem))) s1:(SHLQconst [j1] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLloadidx1 [i0] {s} p idx mem)) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s0 := or.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - s1 := v.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j0 - v2 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v2.AddArg(idx) - v2.AddArg(mem) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x1 := v.Args[_i0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { + continue + } + x0 := sh.Args[0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = 8 + v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem)) x1:(MOVBload [i1] {s} p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64ORQ_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + r1 := v.Args[_i0] + if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVWload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { + continue + } + r0 := sh.Args[0] + if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVWload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64BSWAPL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + r1 := v.Args[_i0] + if r1.Op != OpAMD64BSWAPL { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVLload { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[1] + p := x1.Args[0] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { + continue + } + r0 := sh.Args[0] + if r0.Op != OpAMD64BSWAPL { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVLload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_100(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem))) r1:(BSWAPL x1:(MOVLload [i1] {s} p mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - r1 := v.Args[1] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y) s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem))) s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s1 := or.Args[_i1] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + y := or.Args[1^_i1] + if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j1 + v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) + v2.AuxInt = 8 + v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) + v3.AuxInt = i0 + v3.Aux = s + v3.AddArg(p) + v3.AddArg(mem) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + r0 := s0.Args[0] + if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVWload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s1 := or.Args[_i1] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + r1 := s1.Args[0] + if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVWload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + y := or.Args[1^_i1] + if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j1 + v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) + v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) + v3.AuxInt = i0 + v3.Aux = s + v3.AddArg(p) + v3.AddArg(mem) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_110(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ x1:(MOVBloadidx1 [i1] {s} p idx mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ x1:(MOVBloadidx1 [i1] {s} idx p mem) sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - x1 := v.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} p idx mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} p idx mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x1 := v.Args[_i0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { + continue + } + x0 := sh.Args[0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = 8 + v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(idx) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } + } } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [8] x0:(MOVBloadidx1 [i0] {s} idx p mem)) x1:(MOVBloadidx1 [i1] {s} idx p mem)) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 8 { - break - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - x1 := v.Args[1] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64ROLWconst, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 8 - v1 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + r1 := v.Args[_i0] + if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVWloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { + continue + } + r0 := sh.Args[0] + if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVWloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(idx) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } + } } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_120(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 16 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPL, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) for { _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + r1 := v.Args[_i0] + if r1.Op != OpAMD64BSWAPL { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVLloadidx1 { + continue + } + i1 := x1.AuxInt + s := x1.Aux + mem := x1.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x1.Args[_i1] + idx := x1.Args[1^_i1] + sh := v.Args[1^_i0] + if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { + continue + } + r0 := sh.Args[0] + if r0.Op != OpAMD64BSWAPL { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVLloadidx1 { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[2] + for _i2 := 0; _i2 <= 1; _i2++ { + if p != x0.Args[_i2] || idx != x0.Args[1^_i2] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v1.AddArg(idx) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } + } } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - r1 := v.Args[0] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - sh := v.Args[1] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_130(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} p idx mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} p idx mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (ORQ sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLloadidx1 [i0] {s} idx p mem))) r1:(BSWAPL x1:(MOVLloadidx1 [i1] {s} idx p mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQloadidx1 [i0] {s} p idx mem)) - for { - _ = v.Args[1] - sh := v.Args[0] - if sh.Op != OpAMD64SHLQconst || sh.AuxInt != 32 { - break - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - r1 := v.Args[1] - if r1.Op != OpAMD64BSWAPL { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(sh)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpAMD64BSWAPQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64MOVQloadidx1, typ.UInt64) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v1.AddArg(idx) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpAMD64MOVBloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s1 := or.Args[_i2] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpAMD64MOVBloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i3 := 0; _i3 <= 1; _i3++ { + if p != x1.Args[_i3] || idx != x1.Args[1^_i3] || mem != x1.Args[2] { + continue + } + y := or.Args[1^_i2] + if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j1 + v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) + v2.AuxInt = 8 + v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) + v3.AuxInt = i0 + v3.Aux = s + v3.AddArg(p) + v3.AddArg(idx) + v3.AddArg(mem) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } + } + } } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_140(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem)) or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} p idx mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem)) y) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} p idx mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] x1:(MOVBloadidx1 [i1] {s} idx p mem))) s0:(SHLQconst [j0] x0:(MOVBloadidx1 [i0] {s} idx p mem))) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = 8 - v3 := b.NewValue0(v.Pos, OpAMD64MOVWloadidx1, typ.UInt16) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) for { _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_150(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y)) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y)) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y)) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - p := x0.Args[0] - idx := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem))) or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[2] - idx := x0.Args[0] - p := x0.Args[1] - or := v.Args[1] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[2] - if idx != x1.Args[0] || p != x1.Args[1] || mem != x1.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpAMD64SHLQconst { + continue + } + j0 := s0.AuxInt + r0 := s0.Args[0] + if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { + continue + } + x0 := r0.Args[0] + if x0.Op != OpAMD64MOVWloadidx1 { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[2] + for _i1 := 0; _i1 <= 1; _i1++ { + p := x0.Args[_i1] + idx := x0.Args[1^_i1] + or := v.Args[1^_i0] + if or.Op != OpAMD64ORQ { + continue + } + _ = or.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s1 := or.Args[_i2] + if s1.Op != OpAMD64SHLQconst { + continue + } + j1 := s1.AuxInt + r1 := s1.Args[0] + if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { + continue + } + x1 := r1.Args[0] + if x1.Op != OpAMD64MOVWloadidx1 { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[2] + for _i3 := 0; _i3 <= 1; _i3++ { + if p != x1.Args[_i3] || idx != x1.Args[1^_i3] || mem != x1.Args[2] { + continue + } + y := or.Args[1^_i2] + if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { + continue + } + b = mergePoint(b, x0, x1, y) + v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) + v1.AuxInt = j1 + v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) + v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) + v3.AuxInt = i0 + v3.Aux = s + v3.AddArg(p) + v3.AddArg(idx) + v3.AddArg(mem) + v2.AddArg(v3) + v1.AddArg(v2) + v0.AddArg(v1) + v0.AddArg(y) + return true + } + } + } } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64ORQ_160(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} p idx mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] || idx != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem))) y) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - y := or.Args[1] - s1 := or.Args[0] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} p idx mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - p := x1.Args[0] - idx := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true - } - // match: (ORQ or:(ORQ y s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWloadidx1 [i1] {s} idx p mem)))) s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWloadidx1 [i0] {s} idx p mem)))) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLloadidx1 [i0] {s} p idx mem))) y) - for { - _ = v.Args[1] - or := v.Args[0] - if or.Op != OpAMD64ORQ { - break - } - _ = or.Args[1] - y := or.Args[0] - s1 := or.Args[1] - if s1.Op != OpAMD64SHLQconst { - break - } - j1 := s1.AuxInt - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || r1.AuxInt != 8 { - break - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWloadidx1 { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[2] - idx := x1.Args[0] - p := x1.Args[1] - s0 := v.Args[1] - if s0.Op != OpAMD64SHLQconst { - break - } - j0 := s0.AuxInt - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || r0.AuxInt != 8 { - break - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWloadidx1 { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[2] - if idx != x0.Args[0] || p != x0.Args[1] || mem != x0.Args[2] || !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0) && clobber(x1) && clobber(r0) && clobber(r1) && clobber(s0) && clobber(s1) && clobber(or)) { - break - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(v.Pos, OpAMD64ORQ, v.Type) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = j1 - v2 := b.NewValue0(v.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(v.Pos, OpAMD64MOVLloadidx1, typ.UInt32) - v3.AuxInt = i0 - v3.Aux = s - v3.AddArg(p) - v3.AddArg(idx) - v3.AddArg(mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg(v1) - v0.AddArg(y) - return true + break } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64ORQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (ORQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (ORQload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVQload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64ORQload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64ORQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -39986,7 +25956,7 @@ v.AddArg(mem) return true } - // match: (ORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) + // match: ( ORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: ( ORQ x (MOVQf2i y)) for { off := v.AuxInt @@ -42492,101 +28462,59 @@ b := v.Block // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTL y (SHLL (MOVLconst [1]) x))) - // result: (SETAE (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTQ y (SHLQ (MOVQconst [1]) x))) - // result: (SETAE (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) @@ -42631,51 +28559,30 @@ // match: (SETEQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [log2(c)] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } - x := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst { - break - } - c := v_0_0.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTQ x (MOVQconst [c]))) - // cond: isUint64PowerOfTwo(c) - // result: (SETAE (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0_0.AuxInt + x := v_0.Args[1^_i0] + if !(isUint64PowerOfTwo(c)) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = log2(c) + v0.AddArg(x) + v.AddArg(v0) + return true } - c := v_0_1.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) @@ -42713,339 +28620,193 @@ v.AddArg(v0) return true } - return false -} -func rewriteValueAMD64_OpAMD64SETEQ_10(v *Value) bool { - b := v.Block // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) - // cond: z1==z2 - // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) - // cond: z1==z2 - // result: (SETAE (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) - // cond: z1==z2 - // result: (SETAE (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + return true } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64SETEQ_10(v *Value) bool { + b := v.Block // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) - // cond: z1==z2 - // result: (SETAE (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTQ z2 z1:(SHRQconst [63] x))) - // cond: z1==z2 - // result: (SETAE (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64SETEQ_20(v *Value) bool { - b := v.Block // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETEQ (TESTL z2 z1:(SHRLconst [31] x))) - // cond: z1==z2 - // result: (SETAE (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAE) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETAE) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) @@ -43120,38 +28881,6 @@ b := v.Block // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLL { - break - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTL y (SHLL (MOVLconst [1]) x)) mem) - // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux @@ -43162,61 +28891,32 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_1_0 := v_1.Args[_i0] + if v_1_0.Op != OpAMD64SHLL { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { + continue + } + y := v_1.Args[1^_i0] + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v.AddArg(mem) + return true } - x := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64MOVLconst || v_1_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLQ { - break - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTQ y (SHLQ (MOVQconst [1]) x)) mem) - // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux @@ -43227,26 +28927,29 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_1_0 := v_1.Args[_i0] + if v_1_0.Op != OpAMD64SHLQ { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { + continue + } + y := v_1.Args[1^_i0] + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v.AddArg(mem) + return true } - x := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64MOVQconst || v_1_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(c) @@ -43307,38 +29010,6 @@ // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } - x := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVQconst { - break - } - c := v_1_0.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTQ x (MOVQconst [c])) mem) - // cond: isUint64PowerOfTwo(c) - // result: (SETAEstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux @@ -43349,25 +29020,28 @@ break } _ = v_1.Args[1] - x := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_1_0 := v_1.Args[_i0] + if v_1_0.Op != OpAMD64MOVQconst { + continue + } + c := v_1_0.AuxInt + x := v_1.Args[1^_i0] + if !(isUint64PowerOfTwo(c)) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = log2(c) + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - c := v_1_1.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) @@ -43421,49 +29095,9 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64SETEQstore_10(v *Value) bool { - b := v.Block // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x))) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux @@ -43474,69 +29108,36 @@ break } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTL z2 z1:(SHLLconst [31] (SHRLconst [31] x))) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux @@ -43547,69 +29148,36 @@ break } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x))) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux @@ -43620,69 +29188,41 @@ break } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64SETEQstore_10(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x))) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux @@ -43693,65 +29233,36 @@ break } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] x)) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux @@ -43762,66 +29273,32 @@ break } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + x := z1.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64SETEQstore_20(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETEQstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] x)) mem) - // cond: z1==z2 - // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux @@ -43832,25 +29309,28 @@ break } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + x := z1.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETAEstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - v.reset(OpAMD64SETAEstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) @@ -44007,6 +29487,11 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64SETEQstore_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { @@ -45038,101 +30523,59 @@ b := v.Block // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTL y (SHLL (MOVLconst [1]) x))) - // result: (SETB (BTL x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTQ y (SHLQ (MOVQconst [1]) x))) - // result: (SETB (BTQ x y)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) @@ -45177,51 +30620,30 @@ // match: (SETNE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [log2(c)] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } - x := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst { - break - } - c := v_0_0.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTQ x (MOVQconst [c]))) - // cond: isUint64PowerOfTwo(c) - // result: (SETB (BTQconst [log2(c)] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0_0.AuxInt + x := v_0.Args[1^_i0] + if !(isUint64PowerOfTwo(c)) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = log2(c) + v0.AddArg(x) + v.AddArg(v0) + return true } - c := v_0_1.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) @@ -45259,339 +30681,193 @@ v.AddArg(v0) return true } - return false -} -func rewriteValueAMD64_OpAMD64SETNE_10(v *Value) bool { - b := v.Block // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) - // cond: z1==z2 - // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) - // cond: z1==z2 - // result: (SETB (BTQconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) - // cond: z1==z2 - // result: (SETB (BTQconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + return true } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64SETNE_10(v *Value) bool { + b := v.Block // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) - // cond: z1==z2 - // result: (SETB (BTLconst [0] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTQ { - break - } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTQ z2 z1:(SHRQconst [63] x))) - // cond: z1==z2 - // result: (SETB (BTQconst [63] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64SETNE_20(v *Value) bool { - b := v.Block // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) - for { - v_0 := v.Args[0] - if v_0.Op != OpAMD64TESTL { - break - } - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true - } - // match: (SETNE (TESTL z2 z1:(SHRLconst [31] x))) - // cond: z1==z2 - // result: (SETB (BTLconst [31] x)) for { v_0 := v.Args[0] if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + return true } - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - return true + break } // match: (SETNE (InvertFlags x)) // result: (SETNE x) @@ -45666,38 +30942,6 @@ b := v.Block // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLL { - break - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTL y (SHLL (MOVLconst [1]) x)) mem) - // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := v.AuxInt sym := v.Aux @@ -45708,61 +30952,32 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_1_0 := v_1.Args[_i0] + if v_1_0.Op != OpAMD64SHLL { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVLconst || v_1_0_0.AuxInt != 1 { + continue + } + y := v_1.Args[1^_i0] + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v.AddArg(mem) + return true } - x := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64MOVLconst || v_1_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64SHLQ { - break - } - x := v_1_0.Args[1] - v_1_0_0 := v_1_0.Args[0] - if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTQ y (SHLQ (MOVQconst [1]) x)) mem) - // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := v.AuxInt sym := v.Aux @@ -45773,26 +30988,29 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_1_0 := v_1.Args[_i0] + if v_1_0.Op != OpAMD64SHLQ { + continue + } + x := v_1_0.Args[1] + v_1_0_0 := v_1_0.Args[0] + if v_1_0_0.Op != OpAMD64MOVQconst || v_1_0_0.AuxInt != 1 { + continue + } + y := v_1.Args[1^_i0] + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v.AddArg(mem) + return true } - x := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpAMD64MOVQconst || v_1_1_0.AuxInt != 1 { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(c) @@ -45853,38 +31071,6 @@ // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } - x := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVQconst { - break - } - c := v_1_0.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTQ x (MOVQconst [c])) mem) - // cond: isUint64PowerOfTwo(c) - // result: (SETBstore [off] {sym} ptr (BTQconst [log2(c)] x) mem) for { off := v.AuxInt sym := v.Aux @@ -45895,25 +31081,28 @@ break } _ = v_1.Args[1] - x := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_1_0 := v_1.Args[_i0] + if v_1_0.Op != OpAMD64MOVQconst { + continue + } + c := v_1_0.AuxInt + x := v_1.Args[1^_i0] + if !(isUint64PowerOfTwo(c)) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = log2(c) + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - c := v_1_1.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) @@ -45967,49 +31156,9 @@ v.AddArg(mem) return true } - return false -} -func rewriteValueAMD64_OpAMD64SETNEstore_10(v *Value) bool { - b := v.Block // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x))) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux @@ -46020,69 +31169,36 @@ break } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTL z2 z1:(SHLLconst [31] (SHRLconst [31] x))) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux @@ -46093,69 +31209,36 @@ break } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x))) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := v.AuxInt sym := v.Aux @@ -46166,69 +31249,41 @@ break } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } + return false +} +func rewriteValueAMD64_OpAMD64SETNEstore_10(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x))) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := v.AuxInt sym := v.Aux @@ -46239,65 +31294,36 @@ break } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTQ { - break - } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTQ z2 z1:(SHRQconst [63] x)) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := v.AuxInt sym := v.Aux @@ -46308,66 +31334,32 @@ break } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + x := z1.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64SETNEstore_20(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) - for { - off := v.AuxInt - sym := v.Aux - mem := v.Args[2] - ptr := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64TESTL { - break - } - z2 := v_1.Args[1] - z1 := v_1.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true - } - // match: (SETNEstore [off] {sym} ptr (TESTL z2 z1:(SHRLconst [31] x)) mem) - // cond: z1==z2 - // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := v.AuxInt sym := v.Aux @@ -46378,25 +31370,28 @@ break } _ = v_1.Args[1] - z2 := v_1.Args[0] - z1 := v_1.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_1.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + x := z1.Args[0] + z2 := v_1.Args[1^_i0] + if !(z1 == z2) { + continue + } + v.reset(OpAMD64SETBstore) + v.AuxInt = off + v.Aux = sym + v.AddArg(ptr) + v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + v.AddArg(v0) + v.AddArg(mem) + return true } - v.reset(OpAMD64SETBstore) - v.AuxInt = off - v.Aux = sym - v.AddArg(ptr) - v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - v.AddArg(v0) - v.AddArg(mem) - return true + break } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) @@ -46553,6 +31548,11 @@ v.AddArg(mem) return true } + return false +} +func rewriteValueAMD64_OpAMD64SETNEstore_20(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { @@ -48515,85 +33515,51 @@ b := v.Block // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - v.reset(OpAMD64TESTBconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (TESTB x (MOVLconst [c])) - // result: (TESTBconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + v.reset(OpAMD64TESTBconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - v.reset(OpAMD64TESTBconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0,off)] ptr mem) - for { - l2 := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVBload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true - } - // match: (TESTB l2 l:(MOVBload {sym} [off] ptr mem)) - // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) - // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] - l2 := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVBload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := v.Args[_i0] + if l.Op != OpAMD64MOVBload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + l2 := v.Args[1^_i0] + if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { + continue + } + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = makeValAndOff(0, off) + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true + break } return false } @@ -48620,85 +33586,51 @@ b := v.Block // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - v.reset(OpAMD64TESTLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (TESTL x (MOVLconst [c])) - // result: (TESTLconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + v.reset(OpAMD64TESTLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - v.reset(OpAMD64TESTLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0,off)] ptr mem) - for { - l2 := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true - } - // match: (TESTL l2 l:(MOVLload {sym} [off] ptr mem)) - // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) - // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] - l2 := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVLload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := v.Args[_i0] + if l.Op != OpAMD64MOVLload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + l2 := v.Args[1^_i0] + if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { + continue + } + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = makeValAndOff(0, off) + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true + break } return false } @@ -48726,92 +33658,54 @@ // match: (TESTQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (TESTQconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64TESTQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (TESTQ x (MOVQconst [c])) - // cond: is32Bit(c) - // result: (TESTQconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(is32Bit(c)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64TESTQconst) + v.AuxInt = c + v.AddArg(x) + return true } - v.reset(OpAMD64TESTQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0,off)] ptr mem) - for { - l2 := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true - } - // match: (TESTQ l2 l:(MOVQload {sym} [off] ptr mem)) - // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) - // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] - l2 := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVQload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := v.Args[_i0] + if l.Op != OpAMD64MOVQload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + l2 := v.Args[1^_i0] + if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { + continue + } + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = makeValAndOff(0, off) + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true + break } return false } @@ -48838,85 +33732,51 @@ b := v.Block // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - v.reset(OpAMD64TESTWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (TESTW x (MOVLconst [c])) - // result: (TESTWconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + v.reset(OpAMD64TESTWconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - v.reset(OpAMD64TESTWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0,off)] ptr mem) - for { - l2 := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVWload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true - } - // match: (TESTW l2 l:(MOVWload {sym} [off] ptr mem)) - // cond: l == l2 && l.Uses == 2 && validValAndOff(0,off) && clobber(l) - // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0,off)] ptr mem) for { _ = v.Args[1] - l2 := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVWload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + l := v.Args[_i0] + if l.Op != OpAMD64MOVWload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + l2 := v.Args[1^_i0] + if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { + continue + } + b = l.Block + v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = makeValAndOff(0, off) + v0.Aux = sym + v0.AddArg(ptr) + v0.AddArg(mem) + return true } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(l == l2 && l.Uses == 2 && validValAndOff(0, off) && clobber(l)) { - break - } - b = l.Block - v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = makeValAndOff(0, off) - v0.Aux = sym - v0.AddArg(ptr) - v0.AddArg(mem) - return true + break } return false } @@ -49106,154 +33966,92 @@ func rewriteValueAMD64_OpAMD64XORL_0(v *Value) bool { // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLL { - break - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTCL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (XORL x (SHLL (MOVLconst [1]) y)) - // result: (BTCL x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLL { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVLconst || v_1_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLL { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVLconst || v_0_0.AuxInt != 1 { + continue + } + x := v.Args[1^_i0] + v.reset(OpAMD64BTCL) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64BTCL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCLconst [log2uint32(c)] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { - break - } - v.reset(OpAMD64BTCLconst) - v.AuxInt = log2uint32(c) - v.AddArg(x) - return true - } - // match: (XORL x (MOVLconst [c])) - // cond: isUint32PowerOfTwo(c) && uint64(c) >= 128 - // result: (BTCLconst [log2uint32(c)] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break - } - c := v_1.AuxInt - if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVLconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(isUint32PowerOfTwo(c) && uint64(c) >= 128) { + continue + } + v.reset(OpAMD64BTCLconst) + v.AuxInt = log2uint32(c) + v.AddArg(x) + return true } - v.reset(OpAMD64BTCLconst) - v.AuxInt = log2uint32(c) - v.AddArg(x) - return true + break } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVLconst { + continue + } + c := v_1.AuxInt + v.reset(OpAMD64XORLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - v.reset(OpAMD64XORLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XORL (MOVLconst [c]) x) - // result: (XORLconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVLconst { - break - } - c := v_0.AuxInt - v.reset(OpAMD64XORLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XORL (SHLLconst x [c]) (SHRLconst x [d])) // cond: d==32-c // result: (ROLLconst x [c]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRLconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRLconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 32-c) { + continue + } + v.reset(OpAMD64ROLLconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XORL (SHRLconst x [d]) (SHLLconst x [c])) - // cond: d==32-c - // result: (ROLLconst x [c]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRLconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpAMD64ROLLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XORL (SHLLconst x [c]) (SHRWconst x [d])) // cond: d==16-c && c < 16 && t.Size() == 2 @@ -49261,102 +34059,55 @@ for { t := v.Type _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRWconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - break - } - v.reset(OpAMD64ROLWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XORL (SHRWconst x [d]) (SHLLconst x [c])) - // cond: d==16-c && c < 16 && t.Size() == 2 - // result: (ROLWconst x [c]) - for { - t := v.Type - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRWconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRWconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 16-c && c < 16 && t.Size() == 2) { + continue + } + v.reset(OpAMD64ROLWconst) + v.AuxInt = c + v.AddArg(x) + return true } - v.reset(OpAMD64ROLWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } - return false -} -func rewriteValueAMD64_OpAMD64XORL_10(v *Value) bool { // match: (XORL (SHLLconst x [c]) (SHRBconst x [d])) // cond: d==8-c && c < 8 && t.Size() == 1 // result: (ROLBconst x [c]) for { t := v.Type _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLLconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRBconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - break - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XORL (SHRBconst x [d]) (SHLLconst x [c])) - // cond: d==8-c && c < 8 && t.Size() == 1 - // result: (ROLBconst x [c]) - for { - t := v.Type - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRBconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLLconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRBconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { + continue + } + v.reset(OpAMD64ROLBconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLLconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 8-c && c < 8 && t.Size() == 1) { - break - } - v.reset(OpAMD64ROLBconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XORL x x) // result: (MOVLconst [0]) @@ -49374,49 +34125,28 @@ // result: (XORLload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64XORLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (XORL l:(MOVLload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (XORLload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVLload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVLload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64XORLload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - v.reset(OpAMD64XORLload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -49834,162 +34564,96 @@ func rewriteValueAMD64_OpAMD64XORQ_0(v *Value) bool { // match: (XORQ (SHLQ (MOVQconst [1]) y) x) // result: (BTCQ x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQ { - break - } - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst || v_0_0.AuxInt != 1 { - break - } - v.reset(OpAMD64BTCQ) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (XORQ x (SHLQ (MOVQconst [1]) y)) - // result: (BTCQ x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQ { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpAMD64MOVQconst || v_1_0.AuxInt != 1 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQ { + continue + } + y := v_0.Args[1] + v_0_0 := v_0.Args[0] + if v_0_0.Op != OpAMD64MOVQconst || v_0_0.AuxInt != 1 { + continue + } + x := v.Args[1^_i0] + v.reset(OpAMD64BTCQ) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpAMD64BTCQ) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (XORQ (MOVQconst [c]) x) // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 // result: (BTCQconst [log2(c)] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { - break - } - v.reset(OpAMD64BTCQconst) - v.AuxInt = log2(c) - v.AddArg(x) - return true - } - // match: (XORQ x (MOVQconst [c])) - // cond: isUint64PowerOfTwo(c) && uint64(c) >= 128 - // result: (BTCQconst [log2(c)] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break - } - c := v_1.AuxInt - if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { + continue + } + v.reset(OpAMD64BTCQconst) + v.AuxInt = log2(c) + v.AddArg(x) + return true } - v.reset(OpAMD64BTCQconst) - v.AuxInt = log2(c) - v.AddArg(x) - return true + break } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64MOVQconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpAMD64XORQconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64XORQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XORQ (MOVQconst [c]) x) - // cond: is32Bit(c) - // result: (XORQconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64MOVQconst { - break - } - c := v_0.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpAMD64XORQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XORQ (SHLQconst x [c]) (SHRQconst x [d])) // cond: d==64-c // result: (ROLQconst x [c]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHLQconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHRQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpAMD64SHLQconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpAMD64SHRQconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 64-c) { + continue + } + v.reset(OpAMD64ROLQconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XORQ (SHRQconst x [d]) (SHLQconst x [c])) - // cond: d==64-c - // result: (ROLQconst x [c]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpAMD64SHRQconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpAMD64SHLQconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpAMD64ROLQconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XORQ x x) // result: (MOVQconst [0]) @@ -50007,52 +34671,28 @@ // result: (XORQload x [off] {sym} ptr mem) for { _ = v.Args[1] - x := v.Args[0] - l := v.Args[1] - if l.Op != OpAMD64MOVQload { - break - } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64XORQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64XORQ_10(v *Value) bool { - // match: (XORQ l:(MOVQload [off] {sym} ptr mem) x) - // cond: canMergeLoadClobber(v, l, x) && clobber(l) - // result: (XORQload x [off] {sym} ptr mem) - for { - x := v.Args[1] - l := v.Args[0] - if l.Op != OpAMD64MOVQload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + l := v.Args[1^_i0] + if l.Op != OpAMD64MOVQload { + continue + } + off := l.AuxInt + sym := l.Aux + mem := l.Args[1] + ptr := l.Args[0] + if !(canMergeLoadClobber(v, l, x) && clobber(l)) { + continue + } + v.reset(OpAMD64XORQload) + v.AuxInt = off + v.Aux = sym + v.AddArg(x) + v.AddArg(ptr) + v.AddArg(mem) + return true } - off := l.AuxInt - sym := l.Aux - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoadClobber(v, l, x) && clobber(l)) { - break - } - v.reset(OpAMD64XORQload) - v.AuxInt = off - v.Aux = sym - v.AddArg(x) - v.AddArg(ptr) - v.AddArg(mem) - return true + break } return false } @@ -58029,89 +42669,53 @@ case BlockAMD64EQ: // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true - } - // match: (EQ (TESTL y (SHLL (MOVLconst [1]) x))) - // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true - } - // match: (EQ (TESTQ y (SHLQ (MOVQconst [1]) x))) - // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) @@ -58150,335 +42754,193 @@ // match: (EQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [log2(c)] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - x := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst { - break - } - c := v_0_0.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTQ x (MOVQconst [c]))) - // cond: isUint64PowerOfTwo(c) - // result: (UGE (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0_0.AuxInt + x := v_0.Args[1^_i0] + if !(isUint64PowerOfTwo(c)) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = log2(c) + v0.AddArg(x) + b.AddControl(v0) + return true } - c := v_0_1.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) - // cond: z1==z2 - // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) - // cond: z1==z2 - // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) - // cond: z1==z2 - // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) - // cond: z1==z2 - // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTQ z2 z1:(SHRQconst [63] x))) - // cond: z1==z2 - // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + b.AddControl(v0) + return true } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (EQ (TESTL z2 z1:(SHRLconst [31] x))) - // cond: z1==z2 - // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64UGE) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + b.AddControl(v0) + return true } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64UGE) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) @@ -59041,89 +43503,53 @@ } // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLL { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true - } - // match: (NE (TESTL y (SHLL (MOVLconst [1]) x))) - // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLL { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVLconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVLconst || v_0_1_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - y := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64SHLQ { - break - } - x := v_0_0.Args[1] - v_0_0_0 := v_0_0.Args[0] - if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true - } - // match: (NE (TESTQ y (SHLQ (MOVQconst [1]) x))) - // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] - y := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64SHLQ { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64SHLQ { + continue + } + x := v_0_0.Args[1] + v_0_0_0 := v_0_0.Args[0] + if v_0_0_0.Op != OpAMD64MOVQconst || v_0_0_0.AuxInt != 1 { + continue + } + y := v_0.Args[1^_i0] + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - x := v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpAMD64MOVQconst || v_0_1_0.AuxInt != 1 { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(c) @@ -59162,335 +43588,193 @@ // match: (NE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [log2(c)] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - x := v_0.Args[1] - v_0_0 := v_0.Args[0] - if v_0_0.Op != OpAMD64MOVQconst { - break - } - c := v_0_0.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTQ x (MOVQconst [c]))) - // cond: isUint64PowerOfTwo(c) - // result: (ULT (BTQconst [log2(c)] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpAMD64MOVQconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0_0 := v_0.Args[_i0] + if v_0_0.Op != OpAMD64MOVQconst { + continue + } + c := v_0_0.AuxInt + x := v_0.Args[1^_i0] + if !(isUint64PowerOfTwo(c)) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = log2(c) + v0.AddArg(x) + b.AddControl(v0) + return true } - c := v_0_1.AuxInt - if !(isUint64PowerOfTwo(c)) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = log2(c) - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTQ z2 z1:(SHLQconst [63] (SHRQconst [63] x)))) - // cond: z1==z2 - // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTL z2 z1:(SHLLconst [31] (SHRQconst [31] x)))) - // cond: z1==z2 - // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHLLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHRQconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTQ z2 z1:(SHRQconst [63] (SHLQconst [63] x)))) - // cond: z1==z2 - // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLQconst || z1_0.AuxInt != 63 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTL z2 z1:(SHRLconst [31] (SHLLconst [31] x)))) - // cond: z1==z2 - // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + z1_0 := z1.Args[0] + if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { + continue + } + x := z1_0.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 0 + v0.AddArg(x) + b.AddControl(v0) + return true } - z1_0 := z1.Args[0] - if z1_0.Op != OpAMD64SHLLconst || z1_0.AuxInt != 31 { - break - } - x := z1_0.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 0 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) - for b.Controls[0].Op == OpAMD64TESTQ { - v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTQ z2 z1:(SHRQconst [63] x))) - // cond: z1==z2 - // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRQconst || z1.AuxInt != 63 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) + v0.AuxInt = 63 + v0.AddArg(x) + b.AddControl(v0) + return true } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) - v0.AuxInt = 63 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) - for b.Controls[0].Op == OpAMD64TESTL { - v_0 := b.Controls[0] - z2 := v_0.Args[1] - z1 := v_0.Args[0] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break - } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true - } - // match: (NE (TESTL z2 z1:(SHRLconst [31] x))) - // cond: z1==z2 - // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] - z2 := v_0.Args[0] - z1 := v_0.Args[1] - if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + z1 := v_0.Args[_i0] + if z1.Op != OpAMD64SHRLconst || z1.AuxInt != 31 { + continue + } + x := z1.Args[0] + z2 := v_0.Args[1^_i0] + if !(z1 == z2) { + continue + } + b.Reset(BlockAMD64ULT) + v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) + v0.AuxInt = 31 + v0.AddArg(x) + b.AddControl(v0) + return true } - x := z1.Args[0] - if !(z1 == z2) { - break - } - b.Reset(BlockAMD64ULT) - v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) - v0.AuxInt = 31 - v0.AddArg(x) - b.AddControl(v0) - return true + break } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) go_bd6d78ef37b5a607abfb530f3e353cfa653492f1_src_cmd_compile_internal_ssa_rewritePPC64.go.test000066400000000000000000072311601516001707200360170ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit bd6d78ef37b5a607abfb530f3e353cfa653492f1 file testdata/go_bd6d78ef37b5a607abfb530f3e353cfa653492f1_src_cmd_compile_internal_ssa_rewritePPC64.go.test -- x -- // Code generated from gen/PPC64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/internal/objabi" import "cmd/compile/internal/types" func rewriteValuePPC64(v *Value) bool { switch v.Op { case OpAbs: return rewriteValuePPC64_OpAbs_0(v) case OpAdd16: return rewriteValuePPC64_OpAdd16_0(v) case OpAdd32: return rewriteValuePPC64_OpAdd32_0(v) case OpAdd32F: return rewriteValuePPC64_OpAdd32F_0(v) case OpAdd64: return rewriteValuePPC64_OpAdd64_0(v) case OpAdd64F: return rewriteValuePPC64_OpAdd64F_0(v) case OpAdd64carry: return rewriteValuePPC64_OpAdd64carry_0(v) case OpAdd8: return rewriteValuePPC64_OpAdd8_0(v) case OpAddPtr: return rewriteValuePPC64_OpAddPtr_0(v) case OpAddr: return rewriteValuePPC64_OpAddr_0(v) case OpAnd16: return rewriteValuePPC64_OpAnd16_0(v) case OpAnd32: return rewriteValuePPC64_OpAnd32_0(v) case OpAnd64: return rewriteValuePPC64_OpAnd64_0(v) case OpAnd8: return rewriteValuePPC64_OpAnd8_0(v) case OpAndB: return rewriteValuePPC64_OpAndB_0(v) case OpAtomicAdd32: return rewriteValuePPC64_OpAtomicAdd32_0(v) case OpAtomicAdd64: return rewriteValuePPC64_OpAtomicAdd64_0(v) case OpAtomicAnd8: return rewriteValuePPC64_OpAtomicAnd8_0(v) case OpAtomicCompareAndSwap32: return rewriteValuePPC64_OpAtomicCompareAndSwap32_0(v) case OpAtomicCompareAndSwap64: return rewriteValuePPC64_OpAtomicCompareAndSwap64_0(v) case OpAtomicCompareAndSwapRel32: return rewriteValuePPC64_OpAtomicCompareAndSwapRel32_0(v) case OpAtomicExchange32: return rewriteValuePPC64_OpAtomicExchange32_0(v) case OpAtomicExchange64: return rewriteValuePPC64_OpAtomicExchange64_0(v) case OpAtomicLoad32: return rewriteValuePPC64_OpAtomicLoad32_0(v) case OpAtomicLoad64: return rewriteValuePPC64_OpAtomicLoad64_0(v) case OpAtomicLoad8: return rewriteValuePPC64_OpAtomicLoad8_0(v) case OpAtomicLoadAcq32: return rewriteValuePPC64_OpAtomicLoadAcq32_0(v) case OpAtomicLoadPtr: return rewriteValuePPC64_OpAtomicLoadPtr_0(v) case OpAtomicOr8: return rewriteValuePPC64_OpAtomicOr8_0(v) case OpAtomicStore32: return rewriteValuePPC64_OpAtomicStore32_0(v) case OpAtomicStore64: return rewriteValuePPC64_OpAtomicStore64_0(v) case OpAtomicStore8: return rewriteValuePPC64_OpAtomicStore8_0(v) case OpAtomicStoreRel32: return rewriteValuePPC64_OpAtomicStoreRel32_0(v) case OpAvg64u: return rewriteValuePPC64_OpAvg64u_0(v) case OpBitLen32: return rewriteValuePPC64_OpBitLen32_0(v) case OpBitLen64: return rewriteValuePPC64_OpBitLen64_0(v) case OpCeil: return rewriteValuePPC64_OpCeil_0(v) case OpClosureCall: return rewriteValuePPC64_OpClosureCall_0(v) case OpCom16: return rewriteValuePPC64_OpCom16_0(v) case OpCom32: return rewriteValuePPC64_OpCom32_0(v) case OpCom64: return rewriteValuePPC64_OpCom64_0(v) case OpCom8: return rewriteValuePPC64_OpCom8_0(v) case OpCondSelect: return rewriteValuePPC64_OpCondSelect_0(v) case OpConst16: return rewriteValuePPC64_OpConst16_0(v) case OpConst32: return rewriteValuePPC64_OpConst32_0(v) case OpConst32F: return rewriteValuePPC64_OpConst32F_0(v) case OpConst64: return rewriteValuePPC64_OpConst64_0(v) case OpConst64F: return rewriteValuePPC64_OpConst64F_0(v) case OpConst8: return rewriteValuePPC64_OpConst8_0(v) case OpConstBool: return rewriteValuePPC64_OpConstBool_0(v) case OpConstNil: return rewriteValuePPC64_OpConstNil_0(v) case OpCopysign: return rewriteValuePPC64_OpCopysign_0(v) case OpCtz16: return rewriteValuePPC64_OpCtz16_0(v) case OpCtz32: return rewriteValuePPC64_OpCtz32_0(v) case OpCtz32NonZero: return rewriteValuePPC64_OpCtz32NonZero_0(v) case OpCtz64: return rewriteValuePPC64_OpCtz64_0(v) case OpCtz64NonZero: return rewriteValuePPC64_OpCtz64NonZero_0(v) case OpCtz8: return rewriteValuePPC64_OpCtz8_0(v) case OpCvt32Fto32: return rewriteValuePPC64_OpCvt32Fto32_0(v) case OpCvt32Fto64: return rewriteValuePPC64_OpCvt32Fto64_0(v) case OpCvt32Fto64F: return rewriteValuePPC64_OpCvt32Fto64F_0(v) case OpCvt32to32F: return rewriteValuePPC64_OpCvt32to32F_0(v) case OpCvt32to64F: return rewriteValuePPC64_OpCvt32to64F_0(v) case OpCvt64Fto32: return rewriteValuePPC64_OpCvt64Fto32_0(v) case OpCvt64Fto32F: return rewriteValuePPC64_OpCvt64Fto32F_0(v) case OpCvt64Fto64: return rewriteValuePPC64_OpCvt64Fto64_0(v) case OpCvt64to32F: return rewriteValuePPC64_OpCvt64to32F_0(v) case OpCvt64to64F: return rewriteValuePPC64_OpCvt64to64F_0(v) case OpDiv16: return rewriteValuePPC64_OpDiv16_0(v) case OpDiv16u: return rewriteValuePPC64_OpDiv16u_0(v) case OpDiv32: return rewriteValuePPC64_OpDiv32_0(v) case OpDiv32F: return rewriteValuePPC64_OpDiv32F_0(v) case OpDiv32u: return rewriteValuePPC64_OpDiv32u_0(v) case OpDiv64: return rewriteValuePPC64_OpDiv64_0(v) case OpDiv64F: return rewriteValuePPC64_OpDiv64F_0(v) case OpDiv64u: return rewriteValuePPC64_OpDiv64u_0(v) case OpDiv8: return rewriteValuePPC64_OpDiv8_0(v) case OpDiv8u: return rewriteValuePPC64_OpDiv8u_0(v) case OpEq16: return rewriteValuePPC64_OpEq16_0(v) case OpEq32: return rewriteValuePPC64_OpEq32_0(v) case OpEq32F: return rewriteValuePPC64_OpEq32F_0(v) case OpEq64: return rewriteValuePPC64_OpEq64_0(v) case OpEq64F: return rewriteValuePPC64_OpEq64F_0(v) case OpEq8: return rewriteValuePPC64_OpEq8_0(v) case OpEqB: return rewriteValuePPC64_OpEqB_0(v) case OpEqPtr: return rewriteValuePPC64_OpEqPtr_0(v) case OpFMA: return rewriteValuePPC64_OpFMA_0(v) case OpFloor: return rewriteValuePPC64_OpFloor_0(v) case OpGeq16: return rewriteValuePPC64_OpGeq16_0(v) case OpGeq16U: return rewriteValuePPC64_OpGeq16U_0(v) case OpGeq32: return rewriteValuePPC64_OpGeq32_0(v) case OpGeq32F: return rewriteValuePPC64_OpGeq32F_0(v) case OpGeq32U: return rewriteValuePPC64_OpGeq32U_0(v) case OpGeq64: return rewriteValuePPC64_OpGeq64_0(v) case OpGeq64F: return rewriteValuePPC64_OpGeq64F_0(v) case OpGeq64U: return rewriteValuePPC64_OpGeq64U_0(v) case OpGeq8: return rewriteValuePPC64_OpGeq8_0(v) case OpGeq8U: return rewriteValuePPC64_OpGeq8U_0(v) case OpGetCallerPC: return rewriteValuePPC64_OpGetCallerPC_0(v) case OpGetCallerSP: return rewriteValuePPC64_OpGetCallerSP_0(v) case OpGetClosurePtr: return rewriteValuePPC64_OpGetClosurePtr_0(v) case OpGreater16: return rewriteValuePPC64_OpGreater16_0(v) case OpGreater16U: return rewriteValuePPC64_OpGreater16U_0(v) case OpGreater32: return rewriteValuePPC64_OpGreater32_0(v) case OpGreater32F: return rewriteValuePPC64_OpGreater32F_0(v) case OpGreater32U: return rewriteValuePPC64_OpGreater32U_0(v) case OpGreater64: return rewriteValuePPC64_OpGreater64_0(v) case OpGreater64F: return rewriteValuePPC64_OpGreater64F_0(v) case OpGreater64U: return rewriteValuePPC64_OpGreater64U_0(v) case OpGreater8: return rewriteValuePPC64_OpGreater8_0(v) case OpGreater8U: return rewriteValuePPC64_OpGreater8U_0(v) case OpHmul32: return rewriteValuePPC64_OpHmul32_0(v) case OpHmul32u: return rewriteValuePPC64_OpHmul32u_0(v) case OpHmul64: return rewriteValuePPC64_OpHmul64_0(v) case OpHmul64u: return rewriteValuePPC64_OpHmul64u_0(v) case OpInterCall: return rewriteValuePPC64_OpInterCall_0(v) case OpIsInBounds: return rewriteValuePPC64_OpIsInBounds_0(v) case OpIsNonNil: return rewriteValuePPC64_OpIsNonNil_0(v) case OpIsSliceInBounds: return rewriteValuePPC64_OpIsSliceInBounds_0(v) case OpLeq16: return rewriteValuePPC64_OpLeq16_0(v) case OpLeq16U: return rewriteValuePPC64_OpLeq16U_0(v) case OpLeq32: return rewriteValuePPC64_OpLeq32_0(v) case OpLeq32F: return rewriteValuePPC64_OpLeq32F_0(v) case OpLeq32U: return rewriteValuePPC64_OpLeq32U_0(v) case OpLeq64: return rewriteValuePPC64_OpLeq64_0(v) case OpLeq64F: return rewriteValuePPC64_OpLeq64F_0(v) case OpLeq64U: return rewriteValuePPC64_OpLeq64U_0(v) case OpLeq8: return rewriteValuePPC64_OpLeq8_0(v) case OpLeq8U: return rewriteValuePPC64_OpLeq8U_0(v) case OpLess16: return rewriteValuePPC64_OpLess16_0(v) case OpLess16U: return rewriteValuePPC64_OpLess16U_0(v) case OpLess32: return rewriteValuePPC64_OpLess32_0(v) case OpLess32F: return rewriteValuePPC64_OpLess32F_0(v) case OpLess32U: return rewriteValuePPC64_OpLess32U_0(v) case OpLess64: return rewriteValuePPC64_OpLess64_0(v) case OpLess64F: return rewriteValuePPC64_OpLess64F_0(v) case OpLess64U: return rewriteValuePPC64_OpLess64U_0(v) case OpLess8: return rewriteValuePPC64_OpLess8_0(v) case OpLess8U: return rewriteValuePPC64_OpLess8U_0(v) case OpLoad: return rewriteValuePPC64_OpLoad_0(v) case OpLocalAddr: return rewriteValuePPC64_OpLocalAddr_0(v) case OpLsh16x16: return rewriteValuePPC64_OpLsh16x16_0(v) case OpLsh16x32: return rewriteValuePPC64_OpLsh16x32_0(v) case OpLsh16x64: return rewriteValuePPC64_OpLsh16x64_0(v) case OpLsh16x8: return rewriteValuePPC64_OpLsh16x8_0(v) case OpLsh32x16: return rewriteValuePPC64_OpLsh32x16_0(v) case OpLsh32x32: return rewriteValuePPC64_OpLsh32x32_0(v) case OpLsh32x64: return rewriteValuePPC64_OpLsh32x64_0(v) case OpLsh32x8: return rewriteValuePPC64_OpLsh32x8_0(v) case OpLsh64x16: return rewriteValuePPC64_OpLsh64x16_0(v) case OpLsh64x32: return rewriteValuePPC64_OpLsh64x32_0(v) case OpLsh64x64: return rewriteValuePPC64_OpLsh64x64_0(v) case OpLsh64x8: return rewriteValuePPC64_OpLsh64x8_0(v) case OpLsh8x16: return rewriteValuePPC64_OpLsh8x16_0(v) case OpLsh8x32: return rewriteValuePPC64_OpLsh8x32_0(v) case OpLsh8x64: return rewriteValuePPC64_OpLsh8x64_0(v) case OpLsh8x8: return rewriteValuePPC64_OpLsh8x8_0(v) case OpMod16: return rewriteValuePPC64_OpMod16_0(v) case OpMod16u: return rewriteValuePPC64_OpMod16u_0(v) case OpMod32: return rewriteValuePPC64_OpMod32_0(v) case OpMod32u: return rewriteValuePPC64_OpMod32u_0(v) case OpMod64: return rewriteValuePPC64_OpMod64_0(v) case OpMod64u: return rewriteValuePPC64_OpMod64u_0(v) case OpMod8: return rewriteValuePPC64_OpMod8_0(v) case OpMod8u: return rewriteValuePPC64_OpMod8u_0(v) case OpMove: return rewriteValuePPC64_OpMove_0(v) || rewriteValuePPC64_OpMove_10(v) case OpMul16: return rewriteValuePPC64_OpMul16_0(v) case OpMul32: return rewriteValuePPC64_OpMul32_0(v) case OpMul32F: return rewriteValuePPC64_OpMul32F_0(v) case OpMul64: return rewriteValuePPC64_OpMul64_0(v) case OpMul64F: return rewriteValuePPC64_OpMul64F_0(v) case OpMul64uhilo: return rewriteValuePPC64_OpMul64uhilo_0(v) case OpMul8: return rewriteValuePPC64_OpMul8_0(v) case OpNeg16: return rewriteValuePPC64_OpNeg16_0(v) case OpNeg32: return rewriteValuePPC64_OpNeg32_0(v) case OpNeg32F: return rewriteValuePPC64_OpNeg32F_0(v) case OpNeg64: return rewriteValuePPC64_OpNeg64_0(v) case OpNeg64F: return rewriteValuePPC64_OpNeg64F_0(v) case OpNeg8: return rewriteValuePPC64_OpNeg8_0(v) case OpNeq16: return rewriteValuePPC64_OpNeq16_0(v) case OpNeq32: return rewriteValuePPC64_OpNeq32_0(v) case OpNeq32F: return rewriteValuePPC64_OpNeq32F_0(v) case OpNeq64: return rewriteValuePPC64_OpNeq64_0(v) case OpNeq64F: return rewriteValuePPC64_OpNeq64F_0(v) case OpNeq8: return rewriteValuePPC64_OpNeq8_0(v) case OpNeqB: return rewriteValuePPC64_OpNeqB_0(v) case OpNeqPtr: return rewriteValuePPC64_OpNeqPtr_0(v) case OpNilCheck: return rewriteValuePPC64_OpNilCheck_0(v) case OpNot: return rewriteValuePPC64_OpNot_0(v) case OpOffPtr: return rewriteValuePPC64_OpOffPtr_0(v) case OpOr16: return rewriteValuePPC64_OpOr16_0(v) case OpOr32: return rewriteValuePPC64_OpOr32_0(v) case OpOr64: return rewriteValuePPC64_OpOr64_0(v) case OpOr8: return rewriteValuePPC64_OpOr8_0(v) case OpOrB: return rewriteValuePPC64_OpOrB_0(v) case OpPPC64ADD: return rewriteValuePPC64_OpPPC64ADD_0(v) case OpPPC64ADDconst: return rewriteValuePPC64_OpPPC64ADDconst_0(v) case OpPPC64AND: return rewriteValuePPC64_OpPPC64AND_0(v) || rewriteValuePPC64_OpPPC64AND_10(v) case OpPPC64ANDconst: return rewriteValuePPC64_OpPPC64ANDconst_0(v) || rewriteValuePPC64_OpPPC64ANDconst_10(v) case OpPPC64CMP: return rewriteValuePPC64_OpPPC64CMP_0(v) case OpPPC64CMPU: return rewriteValuePPC64_OpPPC64CMPU_0(v) case OpPPC64CMPUconst: return rewriteValuePPC64_OpPPC64CMPUconst_0(v) case OpPPC64CMPW: return rewriteValuePPC64_OpPPC64CMPW_0(v) case OpPPC64CMPWU: return rewriteValuePPC64_OpPPC64CMPWU_0(v) case OpPPC64CMPWUconst: return rewriteValuePPC64_OpPPC64CMPWUconst_0(v) case OpPPC64CMPWconst: return rewriteValuePPC64_OpPPC64CMPWconst_0(v) case OpPPC64CMPconst: return rewriteValuePPC64_OpPPC64CMPconst_0(v) case OpPPC64Equal: return rewriteValuePPC64_OpPPC64Equal_0(v) case OpPPC64FABS: return rewriteValuePPC64_OpPPC64FABS_0(v) case OpPPC64FADD: return rewriteValuePPC64_OpPPC64FADD_0(v) case OpPPC64FADDS: return rewriteValuePPC64_OpPPC64FADDS_0(v) case OpPPC64FCEIL: return rewriteValuePPC64_OpPPC64FCEIL_0(v) case OpPPC64FFLOOR: return rewriteValuePPC64_OpPPC64FFLOOR_0(v) case OpPPC64FGreaterEqual: return rewriteValuePPC64_OpPPC64FGreaterEqual_0(v) case OpPPC64FGreaterThan: return rewriteValuePPC64_OpPPC64FGreaterThan_0(v) case OpPPC64FLessEqual: return rewriteValuePPC64_OpPPC64FLessEqual_0(v) case OpPPC64FLessThan: return rewriteValuePPC64_OpPPC64FLessThan_0(v) case OpPPC64FMOVDload: return rewriteValuePPC64_OpPPC64FMOVDload_0(v) case OpPPC64FMOVDstore: return rewriteValuePPC64_OpPPC64FMOVDstore_0(v) case OpPPC64FMOVSload: return rewriteValuePPC64_OpPPC64FMOVSload_0(v) case OpPPC64FMOVSstore: return rewriteValuePPC64_OpPPC64FMOVSstore_0(v) case OpPPC64FNEG: return rewriteValuePPC64_OpPPC64FNEG_0(v) case OpPPC64FSQRT: return rewriteValuePPC64_OpPPC64FSQRT_0(v) case OpPPC64FSUB: return rewriteValuePPC64_OpPPC64FSUB_0(v) case OpPPC64FSUBS: return rewriteValuePPC64_OpPPC64FSUBS_0(v) case OpPPC64FTRUNC: return rewriteValuePPC64_OpPPC64FTRUNC_0(v) case OpPPC64GreaterEqual: return rewriteValuePPC64_OpPPC64GreaterEqual_0(v) case OpPPC64GreaterThan: return rewriteValuePPC64_OpPPC64GreaterThan_0(v) case OpPPC64ISEL: return rewriteValuePPC64_OpPPC64ISEL_0(v) || rewriteValuePPC64_OpPPC64ISEL_10(v) || rewriteValuePPC64_OpPPC64ISEL_20(v) case OpPPC64ISELB: return rewriteValuePPC64_OpPPC64ISELB_0(v) || rewriteValuePPC64_OpPPC64ISELB_10(v) || rewriteValuePPC64_OpPPC64ISELB_20(v) case OpPPC64LessEqual: return rewriteValuePPC64_OpPPC64LessEqual_0(v) case OpPPC64LessThan: return rewriteValuePPC64_OpPPC64LessThan_0(v) case OpPPC64MFVSRD: return rewriteValuePPC64_OpPPC64MFVSRD_0(v) case OpPPC64MOVBZload: return rewriteValuePPC64_OpPPC64MOVBZload_0(v) case OpPPC64MOVBZloadidx: return rewriteValuePPC64_OpPPC64MOVBZloadidx_0(v) case OpPPC64MOVBZreg: return rewriteValuePPC64_OpPPC64MOVBZreg_0(v) || rewriteValuePPC64_OpPPC64MOVBZreg_10(v) case OpPPC64MOVBreg: return rewriteValuePPC64_OpPPC64MOVBreg_0(v) || rewriteValuePPC64_OpPPC64MOVBreg_10(v) case OpPPC64MOVBstore: return rewriteValuePPC64_OpPPC64MOVBstore_0(v) || rewriteValuePPC64_OpPPC64MOVBstore_10(v) || rewriteValuePPC64_OpPPC64MOVBstore_20(v) case OpPPC64MOVBstoreidx: return rewriteValuePPC64_OpPPC64MOVBstoreidx_0(v) || rewriteValuePPC64_OpPPC64MOVBstoreidx_10(v) case OpPPC64MOVBstorezero: return rewriteValuePPC64_OpPPC64MOVBstorezero_0(v) case OpPPC64MOVDload: return rewriteValuePPC64_OpPPC64MOVDload_0(v) case OpPPC64MOVDloadidx: return rewriteValuePPC64_OpPPC64MOVDloadidx_0(v) case OpPPC64MOVDstore: return rewriteValuePPC64_OpPPC64MOVDstore_0(v) case OpPPC64MOVDstoreidx: return rewriteValuePPC64_OpPPC64MOVDstoreidx_0(v) case OpPPC64MOVDstorezero: return rewriteValuePPC64_OpPPC64MOVDstorezero_0(v) case OpPPC64MOVHBRstore: return rewriteValuePPC64_OpPPC64MOVHBRstore_0(v) case OpPPC64MOVHZload: return rewriteValuePPC64_OpPPC64MOVHZload_0(v) case OpPPC64MOVHZloadidx: return rewriteValuePPC64_OpPPC64MOVHZloadidx_0(v) case OpPPC64MOVHZreg: return rewriteValuePPC64_OpPPC64MOVHZreg_0(v) || rewriteValuePPC64_OpPPC64MOVHZreg_10(v) case OpPPC64MOVHload: return rewriteValuePPC64_OpPPC64MOVHload_0(v) case OpPPC64MOVHloadidx: return rewriteValuePPC64_OpPPC64MOVHloadidx_0(v) case OpPPC64MOVHreg: return rewriteValuePPC64_OpPPC64MOVHreg_0(v) || rewriteValuePPC64_OpPPC64MOVHreg_10(v) case OpPPC64MOVHstore: return rewriteValuePPC64_OpPPC64MOVHstore_0(v) case OpPPC64MOVHstoreidx: return rewriteValuePPC64_OpPPC64MOVHstoreidx_0(v) case OpPPC64MOVHstorezero: return rewriteValuePPC64_OpPPC64MOVHstorezero_0(v) case OpPPC64MOVWBRstore: return rewriteValuePPC64_OpPPC64MOVWBRstore_0(v) case OpPPC64MOVWZload: return rewriteValuePPC64_OpPPC64MOVWZload_0(v) case OpPPC64MOVWZloadidx: return rewriteValuePPC64_OpPPC64MOVWZloadidx_0(v) case OpPPC64MOVWZreg: return rewriteValuePPC64_OpPPC64MOVWZreg_0(v) || rewriteValuePPC64_OpPPC64MOVWZreg_10(v) || rewriteValuePPC64_OpPPC64MOVWZreg_20(v) case OpPPC64MOVWload: return rewriteValuePPC64_OpPPC64MOVWload_0(v) case OpPPC64MOVWloadidx: return rewriteValuePPC64_OpPPC64MOVWloadidx_0(v) case OpPPC64MOVWreg: return rewriteValuePPC64_OpPPC64MOVWreg_0(v) || rewriteValuePPC64_OpPPC64MOVWreg_10(v) case OpPPC64MOVWstore: return rewriteValuePPC64_OpPPC64MOVWstore_0(v) case OpPPC64MOVWstoreidx: return rewriteValuePPC64_OpPPC64MOVWstoreidx_0(v) case OpPPC64MOVWstorezero: return rewriteValuePPC64_OpPPC64MOVWstorezero_0(v) case OpPPC64MTVSRD: return rewriteValuePPC64_OpPPC64MTVSRD_0(v) case OpPPC64MaskIfNotCarry: return rewriteValuePPC64_OpPPC64MaskIfNotCarry_0(v) case OpPPC64NotEqual: return rewriteValuePPC64_OpPPC64NotEqual_0(v) case OpPPC64OR: return rewriteValuePPC64_OpPPC64OR_0(v) || rewriteValuePPC64_OpPPC64OR_10(v) || rewriteValuePPC64_OpPPC64OR_20(v) || rewriteValuePPC64_OpPPC64OR_30(v) || rewriteValuePPC64_OpPPC64OR_40(v) || rewriteValuePPC64_OpPPC64OR_50(v) || rewriteValuePPC64_OpPPC64OR_60(v) || rewriteValuePPC64_OpPPC64OR_70(v) || rewriteValuePPC64_OpPPC64OR_80(v) || rewriteValuePPC64_OpPPC64OR_90(v) || rewriteValuePPC64_OpPPC64OR_100(v) || rewriteValuePPC64_OpPPC64OR_110(v) case OpPPC64ORN: return rewriteValuePPC64_OpPPC64ORN_0(v) case OpPPC64ORconst: return rewriteValuePPC64_OpPPC64ORconst_0(v) case OpPPC64ROTL: return rewriteValuePPC64_OpPPC64ROTL_0(v) case OpPPC64ROTLW: return rewriteValuePPC64_OpPPC64ROTLW_0(v) case OpPPC64SUB: return rewriteValuePPC64_OpPPC64SUB_0(v) case OpPPC64XOR: return rewriteValuePPC64_OpPPC64XOR_0(v) || rewriteValuePPC64_OpPPC64XOR_10(v) case OpPPC64XORconst: return rewriteValuePPC64_OpPPC64XORconst_0(v) case OpPanicBounds: return rewriteValuePPC64_OpPanicBounds_0(v) case OpPopCount16: return rewriteValuePPC64_OpPopCount16_0(v) case OpPopCount32: return rewriteValuePPC64_OpPopCount32_0(v) case OpPopCount64: return rewriteValuePPC64_OpPopCount64_0(v) case OpPopCount8: return rewriteValuePPC64_OpPopCount8_0(v) case OpRotateLeft16: return rewriteValuePPC64_OpRotateLeft16_0(v) case OpRotateLeft32: return rewriteValuePPC64_OpRotateLeft32_0(v) case OpRotateLeft64: return rewriteValuePPC64_OpRotateLeft64_0(v) case OpRotateLeft8: return rewriteValuePPC64_OpRotateLeft8_0(v) case OpRound: return rewriteValuePPC64_OpRound_0(v) case OpRound32F: return rewriteValuePPC64_OpRound32F_0(v) case OpRound64F: return rewriteValuePPC64_OpRound64F_0(v) case OpRsh16Ux16: return rewriteValuePPC64_OpRsh16Ux16_0(v) case OpRsh16Ux32: return rewriteValuePPC64_OpRsh16Ux32_0(v) case OpRsh16Ux64: return rewriteValuePPC64_OpRsh16Ux64_0(v) case OpRsh16Ux8: return rewriteValuePPC64_OpRsh16Ux8_0(v) case OpRsh16x16: return rewriteValuePPC64_OpRsh16x16_0(v) case OpRsh16x32: return rewriteValuePPC64_OpRsh16x32_0(v) case OpRsh16x64: return rewriteValuePPC64_OpRsh16x64_0(v) case OpRsh16x8: return rewriteValuePPC64_OpRsh16x8_0(v) case OpRsh32Ux16: return rewriteValuePPC64_OpRsh32Ux16_0(v) case OpRsh32Ux32: return rewriteValuePPC64_OpRsh32Ux32_0(v) case OpRsh32Ux64: return rewriteValuePPC64_OpRsh32Ux64_0(v) || rewriteValuePPC64_OpRsh32Ux64_10(v) case OpRsh32Ux8: return rewriteValuePPC64_OpRsh32Ux8_0(v) case OpRsh32x16: return rewriteValuePPC64_OpRsh32x16_0(v) case OpRsh32x32: return rewriteValuePPC64_OpRsh32x32_0(v) case OpRsh32x64: return rewriteValuePPC64_OpRsh32x64_0(v) || rewriteValuePPC64_OpRsh32x64_10(v) case OpRsh32x8: return rewriteValuePPC64_OpRsh32x8_0(v) case OpRsh64Ux16: return rewriteValuePPC64_OpRsh64Ux16_0(v) case OpRsh64Ux32: return rewriteValuePPC64_OpRsh64Ux32_0(v) case OpRsh64Ux64: return rewriteValuePPC64_OpRsh64Ux64_0(v) || rewriteValuePPC64_OpRsh64Ux64_10(v) case OpRsh64Ux8: return rewriteValuePPC64_OpRsh64Ux8_0(v) case OpRsh64x16: return rewriteValuePPC64_OpRsh64x16_0(v) case OpRsh64x32: return rewriteValuePPC64_OpRsh64x32_0(v) case OpRsh64x64: return rewriteValuePPC64_OpRsh64x64_0(v) || rewriteValuePPC64_OpRsh64x64_10(v) case OpRsh64x8: return rewriteValuePPC64_OpRsh64x8_0(v) case OpRsh8Ux16: return rewriteValuePPC64_OpRsh8Ux16_0(v) case OpRsh8Ux32: return rewriteValuePPC64_OpRsh8Ux32_0(v) case OpRsh8Ux64: return rewriteValuePPC64_OpRsh8Ux64_0(v) case OpRsh8Ux8: return rewriteValuePPC64_OpRsh8Ux8_0(v) case OpRsh8x16: return rewriteValuePPC64_OpRsh8x16_0(v) case OpRsh8x32: return rewriteValuePPC64_OpRsh8x32_0(v) case OpRsh8x64: return rewriteValuePPC64_OpRsh8x64_0(v) case OpRsh8x8: return rewriteValuePPC64_OpRsh8x8_0(v) case OpSignExt16to32: return rewriteValuePPC64_OpSignExt16to32_0(v) case OpSignExt16to64: return rewriteValuePPC64_OpSignExt16to64_0(v) case OpSignExt32to64: return rewriteValuePPC64_OpSignExt32to64_0(v) case OpSignExt8to16: return rewriteValuePPC64_OpSignExt8to16_0(v) case OpSignExt8to32: return rewriteValuePPC64_OpSignExt8to32_0(v) case OpSignExt8to64: return rewriteValuePPC64_OpSignExt8to64_0(v) case OpSlicemask: return rewriteValuePPC64_OpSlicemask_0(v) case OpSqrt: return rewriteValuePPC64_OpSqrt_0(v) case OpStaticCall: return rewriteValuePPC64_OpStaticCall_0(v) case OpStore: return rewriteValuePPC64_OpStore_0(v) case OpSub16: return rewriteValuePPC64_OpSub16_0(v) case OpSub32: return rewriteValuePPC64_OpSub32_0(v) case OpSub32F: return rewriteValuePPC64_OpSub32F_0(v) case OpSub64: return rewriteValuePPC64_OpSub64_0(v) case OpSub64F: return rewriteValuePPC64_OpSub64F_0(v) case OpSub8: return rewriteValuePPC64_OpSub8_0(v) case OpSubPtr: return rewriteValuePPC64_OpSubPtr_0(v) case OpTrunc: return rewriteValuePPC64_OpTrunc_0(v) case OpTrunc16to8: return rewriteValuePPC64_OpTrunc16to8_0(v) case OpTrunc32to16: return rewriteValuePPC64_OpTrunc32to16_0(v) case OpTrunc32to8: return rewriteValuePPC64_OpTrunc32to8_0(v) case OpTrunc64to16: return rewriteValuePPC64_OpTrunc64to16_0(v) case OpTrunc64to32: return rewriteValuePPC64_OpTrunc64to32_0(v) case OpTrunc64to8: return rewriteValuePPC64_OpTrunc64to8_0(v) case OpWB: return rewriteValuePPC64_OpWB_0(v) case OpXor16: return rewriteValuePPC64_OpXor16_0(v) case OpXor32: return rewriteValuePPC64_OpXor32_0(v) case OpXor64: return rewriteValuePPC64_OpXor64_0(v) case OpXor8: return rewriteValuePPC64_OpXor8_0(v) case OpZero: return rewriteValuePPC64_OpZero_0(v) || rewriteValuePPC64_OpZero_10(v) case OpZeroExt16to32: return rewriteValuePPC64_OpZeroExt16to32_0(v) case OpZeroExt16to64: return rewriteValuePPC64_OpZeroExt16to64_0(v) case OpZeroExt32to64: return rewriteValuePPC64_OpZeroExt32to64_0(v) case OpZeroExt8to16: return rewriteValuePPC64_OpZeroExt8to16_0(v) case OpZeroExt8to32: return rewriteValuePPC64_OpZeroExt8to32_0(v) case OpZeroExt8to64: return rewriteValuePPC64_OpZeroExt8to64_0(v) } return false } func rewriteValuePPC64_OpAbs_0(v *Value) bool { // match: (Abs x) // result: (FABS x) for { x := v.Args[0] v.reset(OpPPC64FABS) v.AddArg(x) return true } } func rewriteValuePPC64_OpAdd16_0(v *Value) bool { // match: (Add16 x y) // result: (ADD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd32_0(v *Value) bool { // match: (Add32 x y) // result: (ADD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd32F_0(v *Value) bool { // match: (Add32F x y) // result: (FADDS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FADDS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd64_0(v *Value) bool { // match: (Add64 x y) // result: (ADD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd64F_0(v *Value) bool { // match: (Add64F x y) // result: (FADD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd64carry_0(v *Value) bool { // match: (Add64carry x y c) // result: (LoweredAdd64Carry x y c) for { c := v.Args[2] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LoweredAdd64Carry) v.AddArg(x) v.AddArg(y) v.AddArg(c) return true } } func rewriteValuePPC64_OpAdd8_0(v *Value) bool { // match: (Add8 x y) // result: (ADD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAddPtr_0(v *Value) bool { // match: (AddPtr x y) // result: (ADD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAddr_0(v *Value) bool { // match: (Addr {sym} base) // result: (MOVDaddr {sym} base) for { sym := v.Aux base := v.Args[0] v.reset(OpPPC64MOVDaddr) v.Aux = sym v.AddArg(base) return true } } func rewriteValuePPC64_OpAnd16_0(v *Value) bool { // match: (And16 x y) // result: (AND x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAnd32_0(v *Value) bool { // match: (And32 x y) // result: (AND x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAnd64_0(v *Value) bool { // match: (And64 x y) // result: (AND x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAnd8_0(v *Value) bool { // match: (And8 x y) // result: (AND x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAndB_0(v *Value) bool { // match: (AndB x y) // result: (AND x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAtomicAdd32_0(v *Value) bool { // match: (AtomicAdd32 ptr val mem) // result: (LoweredAtomicAdd32 ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicAdd32) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicAdd64_0(v *Value) bool { // match: (AtomicAdd64 ptr val mem) // result: (LoweredAtomicAdd64 ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicAdd64) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicAnd8_0(v *Value) bool { // match: (AtomicAnd8 ptr val mem) // result: (LoweredAtomicAnd8 ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicAnd8) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicCompareAndSwap32_0(v *Value) bool { // match: (AtomicCompareAndSwap32 ptr old new_ mem) // result: (LoweredAtomicCas32 [1] ptr old new_ mem) for { mem := v.Args[3] ptr := v.Args[0] old := v.Args[1] new_ := v.Args[2] v.reset(OpPPC64LoweredAtomicCas32) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicCompareAndSwap64_0(v *Value) bool { // match: (AtomicCompareAndSwap64 ptr old new_ mem) // result: (LoweredAtomicCas64 [1] ptr old new_ mem) for { mem := v.Args[3] ptr := v.Args[0] old := v.Args[1] new_ := v.Args[2] v.reset(OpPPC64LoweredAtomicCas64) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicCompareAndSwapRel32_0(v *Value) bool { // match: (AtomicCompareAndSwapRel32 ptr old new_ mem) // result: (LoweredAtomicCas32 [0] ptr old new_ mem) for { mem := v.Args[3] ptr := v.Args[0] old := v.Args[1] new_ := v.Args[2] v.reset(OpPPC64LoweredAtomicCas32) v.AuxInt = 0 v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicExchange32_0(v *Value) bool { // match: (AtomicExchange32 ptr val mem) // result: (LoweredAtomicExchange32 ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicExchange32) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicExchange64_0(v *Value) bool { // match: (AtomicExchange64 ptr val mem) // result: (LoweredAtomicExchange64 ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicExchange64) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoad32_0(v *Value) bool { // match: (AtomicLoad32 ptr mem) // result: (LoweredAtomicLoad32 [1] ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredAtomicLoad32) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoad64_0(v *Value) bool { // match: (AtomicLoad64 ptr mem) // result: (LoweredAtomicLoad64 [1] ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredAtomicLoad64) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoad8_0(v *Value) bool { // match: (AtomicLoad8 ptr mem) // result: (LoweredAtomicLoad8 [1] ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredAtomicLoad8) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoadAcq32_0(v *Value) bool { // match: (AtomicLoadAcq32 ptr mem) // result: (LoweredAtomicLoad32 [0] ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredAtomicLoad32) v.AuxInt = 0 v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoadPtr_0(v *Value) bool { // match: (AtomicLoadPtr ptr mem) // result: (LoweredAtomicLoadPtr [1] ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredAtomicLoadPtr) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicOr8_0(v *Value) bool { // match: (AtomicOr8 ptr val mem) // result: (LoweredAtomicOr8 ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicOr8) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicStore32_0(v *Value) bool { // match: (AtomicStore32 ptr val mem) // result: (LoweredAtomicStore32 [1] ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicStore32) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicStore64_0(v *Value) bool { // match: (AtomicStore64 ptr val mem) // result: (LoweredAtomicStore64 [1] ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicStore64) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicStore8_0(v *Value) bool { // match: (AtomicStore8 ptr val mem) // result: (LoweredAtomicStore8 [1] ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicStore8) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicStoreRel32_0(v *Value) bool { // match: (AtomicStoreRel32 ptr val mem) // result: (LoweredAtomicStore32 [0] ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicStore32) v.AuxInt = 0 v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAvg64u_0(v *Value) bool { b := v.Block // match: (Avg64u x y) // result: (ADD (SRDconst (SUB x y) [1]) y) for { t := v.Type y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ADD) v0 := b.NewValue0(v.Pos, OpPPC64SRDconst, t) v0.AuxInt = 1 v1 := b.NewValue0(v.Pos, OpPPC64SUB, t) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) v.AddArg(y) return true } } func rewriteValuePPC64_OpBitLen32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // result: (SUB (MOVDconst [32]) (CNTLZW x)) for { x := v.Args[0] v.reset(OpPPC64SUB) v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 32 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64CNTLZW, typ.Int) v1.AddArg(x) v.AddArg(v1) return true } } func rewriteValuePPC64_OpBitLen64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // result: (SUB (MOVDconst [64]) (CNTLZD x)) for { x := v.Args[0] v.reset(OpPPC64SUB) v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 64 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64CNTLZD, typ.Int) v1.AddArg(x) v.AddArg(v1) return true } } func rewriteValuePPC64_OpCeil_0(v *Value) bool { // match: (Ceil x) // result: (FCEIL x) for { x := v.Args[0] v.reset(OpPPC64FCEIL) v.AddArg(x) return true } } func rewriteValuePPC64_OpClosureCall_0(v *Value) bool { // match: (ClosureCall [argwid] entry closure mem) // result: (CALLclosure [argwid] entry closure mem) for { argwid := v.AuxInt mem := v.Args[2] entry := v.Args[0] closure := v.Args[1] v.reset(OpPPC64CALLclosure) v.AuxInt = argwid v.AddArg(entry) v.AddArg(closure) v.AddArg(mem) return true } } func rewriteValuePPC64_OpCom16_0(v *Value) bool { // match: (Com16 x) // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCom32_0(v *Value) bool { // match: (Com32 x) // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCom64_0(v *Value) bool { // match: (Com64 x) // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCom8_0(v *Value) bool { // match: (Com8 x) // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCondSelect_0(v *Value) bool { b := v.Block // match: (CondSelect x y bool) // cond: flagArg(bool) != nil // result: (ISEL [2] x y bool) for { bool := v.Args[2] x := v.Args[0] y := v.Args[1] if !(flagArg(bool) != nil) { break } v.reset(OpPPC64ISEL) v.AuxInt = 2 v.AddArg(x) v.AddArg(y) v.AddArg(bool) return true } // match: (CondSelect x y bool) // cond: flagArg(bool) == nil // result: (ISEL [2] x y (CMPWconst [0] bool)) for { bool := v.Args[2] x := v.Args[0] y := v.Args[1] if !(flagArg(bool) == nil) { break } v.reset(OpPPC64ISEL) v.AuxInt = 2 v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpPPC64CMPWconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(bool) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpConst16_0(v *Value) bool { // match: (Const16 [val]) // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst32_0(v *Value) bool { // match: (Const32 [val]) // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst32F_0(v *Value) bool { // match: (Const32F [val]) // result: (FMOVSconst [val]) for { val := v.AuxInt v.reset(OpPPC64FMOVSconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst64_0(v *Value) bool { // match: (Const64 [val]) // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst64F_0(v *Value) bool { // match: (Const64F [val]) // result: (FMOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst8_0(v *Value) bool { // match: (Const8 [val]) // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConstBool_0(v *Value) bool { // match: (ConstBool [b]) // result: (MOVDconst [b]) for { b := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = b return true } } func rewriteValuePPC64_OpConstNil_0(v *Value) bool { // match: (ConstNil) // result: (MOVDconst [0]) for { v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } } func rewriteValuePPC64_OpCopysign_0(v *Value) bool { // match: (Copysign x y) // result: (FCPSGN y x) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FCPSGN) v.AddArg(y) v.AddArg(x) return true } } func rewriteValuePPC64_OpCtz16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (POPCNTW (MOVHZreg (ANDN (ADDconst [-1] x) x))) for { x := v.Args[0] v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v1 := b.NewValue0(v.Pos, OpPPC64ANDN, typ.Int16) v2 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.Int16) v2.AuxInt = -1 v2.AddArg(x) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCtz32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // cond: objabi.GOPPC64<=8 // result: (POPCNTW (MOVWZreg (ANDN (ADDconst [-1] x) x))) for { x := v.Args[0] if !(objabi.GOPPC64 <= 8) { break } v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZreg, typ.Int64) v1 := b.NewValue0(v.Pos, OpPPC64ANDN, typ.Int) v2 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.Int) v2.AuxInt = -1 v2.AddArg(x) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Ctz32 x) // result: (CNTTZW (MOVWZreg x)) for { x := v.Args[0] v.reset(OpPPC64CNTTZW) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCtz32NonZero_0(v *Value) bool { // match: (Ctz32NonZero x) // result: (Ctz32 x) for { x := v.Args[0] v.reset(OpCtz32) v.AddArg(x) return true } } func rewriteValuePPC64_OpCtz64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // cond: objabi.GOPPC64<=8 // result: (POPCNTD (ANDN (ADDconst [-1] x) x)) for { x := v.Args[0] if !(objabi.GOPPC64 <= 8) { break } v.reset(OpPPC64POPCNTD) v0 := b.NewValue0(v.Pos, OpPPC64ANDN, typ.Int64) v1 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.Int64) v1.AuxInt = -1 v1.AddArg(x) v0.AddArg(v1) v0.AddArg(x) v.AddArg(v0) return true } // match: (Ctz64 x) // result: (CNTTZD x) for { x := v.Args[0] v.reset(OpPPC64CNTTZD) v.AddArg(x) return true } } func rewriteValuePPC64_OpCtz64NonZero_0(v *Value) bool { // match: (Ctz64NonZero x) // result: (Ctz64 x) for { x := v.Args[0] v.reset(OpCtz64) v.AddArg(x) return true } } func rewriteValuePPC64_OpCtz8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (POPCNTB (MOVBZreg (ANDN (ADDconst [-1] x) x))) for { x := v.Args[0] v.reset(OpPPC64POPCNTB) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v1 := b.NewValue0(v.Pos, OpPPC64ANDN, typ.UInt8) v2 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.UInt8) v2.AuxInt = -1 v2.AddArg(x) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32Fto32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt32Fto32 x) // result: (MFVSRD (FCTIWZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIWZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32Fto64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt32Fto64 x) // result: (MFVSRD (FCTIDZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIDZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32Fto64F_0(v *Value) bool { // match: (Cvt32Fto64F x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValuePPC64_OpCvt32to32F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt32to32F x) // result: (FCFIDS (MTVSRD (SignExt32to64 x))) for { x := v.Args[0] v.reset(OpPPC64FCFIDS) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32to64F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt32to64F x) // result: (FCFID (MTVSRD (SignExt32to64 x))) for { x := v.Args[0] v.reset(OpPPC64FCFID) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64Fto32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt64Fto32 x) // result: (MFVSRD (FCTIWZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIWZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64Fto32F_0(v *Value) bool { // match: (Cvt64Fto32F x) // result: (FRSP x) for { x := v.Args[0] v.reset(OpPPC64FRSP) v.AddArg(x) return true } } func rewriteValuePPC64_OpCvt64Fto64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt64Fto64 x) // result: (MFVSRD (FCTIDZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIDZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64to32F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt64to32F x) // result: (FCFIDS (MTVSRD x)) for { x := v.Args[0] v.reset(OpPPC64FCFIDS) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64to64F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt64to64F x) // result: (FCFID (MTVSRD x)) for { x := v.Args[0] v.reset(OpPPC64FCFID) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpDiv16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16 x y) // result: (DIVW (SignExt16to32 x) (SignExt16to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpDiv16u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVWU) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpDiv32_0(v *Value) bool { // match: (Div32 x y) // result: (DIVW x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv32F_0(v *Value) bool { // match: (Div32F x y) // result: (FDIVS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FDIVS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv32u_0(v *Value) bool { // match: (Div32u x y) // result: (DIVWU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVWU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv64_0(v *Value) bool { // match: (Div64 x y) // result: (DIVD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv64F_0(v *Value) bool { // match: (Div64F x y) // result: (FDIV x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FDIV) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv64u_0(v *Value) bool { // match: (Div64u x y) // result: (DIVDU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVDU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (DIVW (SignExt8to32 x) (SignExt8to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpDiv8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVWU) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpEq16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq16 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { y := v.Args[1] x := v.Args[0] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Eq16 y x) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { x := v.Args[1] y := v.Args[0] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Eq16 x y) // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq32_0(v *Value) bool { b := v.Block // match: (Eq32 x y) // result: (Equal (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq32F_0(v *Value) bool { b := v.Block // match: (Eq32F x y) // result: (Equal (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq64_0(v *Value) bool { b := v.Block // match: (Eq64 x y) // result: (Equal (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq64F_0(v *Value) bool { b := v.Block // match: (Eq64F x y) // result: (Equal (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq8 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { y := v.Args[1] x := v.Args[0] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Eq8 y x) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { x := v.Args[1] y := v.Args[0] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Eq8 x y) // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEqB_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (EqB x y) // result: (ANDconst [1] (EQV x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = 1 v0 := b.NewValue0(v.Pos, OpPPC64EQV, typ.Int64) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEqPtr_0(v *Value) bool { b := v.Block // match: (EqPtr x y) // result: (Equal (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpFMA_0(v *Value) bool { // match: (FMA x y z) // result: (FMADD x y z) for { z := v.Args[2] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FMADD) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } } func rewriteValuePPC64_OpFloor_0(v *Value) bool { // match: (Floor x) // result: (FFLOOR x) for { x := v.Args[0] v.reset(OpPPC64FFLOOR) v.AddArg(x) return true } } func rewriteValuePPC64_OpGeq16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Geq16 x y) // result: (GreaterEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq16U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Geq16U x y) // result: (GreaterEqual (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq32_0(v *Value) bool { b := v.Block // match: (Geq32 x y) // result: (GreaterEqual (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq32F_0(v *Value) bool { b := v.Block // match: (Geq32F x y) // result: (FGreaterEqual (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FGreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq32U_0(v *Value) bool { b := v.Block // match: (Geq32U x y) // result: (GreaterEqual (CMPWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq64_0(v *Value) bool { b := v.Block // match: (Geq64 x y) // result: (GreaterEqual (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq64F_0(v *Value) bool { b := v.Block // match: (Geq64F x y) // result: (FGreaterEqual (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FGreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq64U_0(v *Value) bool { b := v.Block // match: (Geq64U x y) // result: (GreaterEqual (CMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Geq8 x y) // result: (GreaterEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq8U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Geq8U x y) // result: (GreaterEqual (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGetCallerPC_0(v *Value) bool { // match: (GetCallerPC) // result: (LoweredGetCallerPC) for { v.reset(OpPPC64LoweredGetCallerPC) return true } } func rewriteValuePPC64_OpGetCallerSP_0(v *Value) bool { // match: (GetCallerSP) // result: (LoweredGetCallerSP) for { v.reset(OpPPC64LoweredGetCallerSP) return true } } func rewriteValuePPC64_OpGetClosurePtr_0(v *Value) bool { // match: (GetClosurePtr) // result: (LoweredGetClosurePtr) for { v.reset(OpPPC64LoweredGetClosurePtr) return true } } func rewriteValuePPC64_OpGreater16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Greater16 x y) // result: (GreaterThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater16U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Greater16U x y) // result: (GreaterThan (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater32_0(v *Value) bool { b := v.Block // match: (Greater32 x y) // result: (GreaterThan (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater32F_0(v *Value) bool { b := v.Block // match: (Greater32F x y) // result: (FGreaterThan (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FGreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater32U_0(v *Value) bool { b := v.Block // match: (Greater32U x y) // result: (GreaterThan (CMPWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater64_0(v *Value) bool { b := v.Block // match: (Greater64 x y) // result: (GreaterThan (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater64F_0(v *Value) bool { b := v.Block // match: (Greater64F x y) // result: (FGreaterThan (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FGreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater64U_0(v *Value) bool { b := v.Block // match: (Greater64U x y) // result: (GreaterThan (CMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Greater8 x y) // result: (GreaterThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater8U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Greater8U x y) // result: (GreaterThan (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpHmul32_0(v *Value) bool { // match: (Hmul32 x y) // result: (MULHW x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULHW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpHmul32u_0(v *Value) bool { // match: (Hmul32u x y) // result: (MULHWU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULHWU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpHmul64_0(v *Value) bool { // match: (Hmul64 x y) // result: (MULHD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULHD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpHmul64u_0(v *Value) bool { // match: (Hmul64u x y) // result: (MULHDU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULHDU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpInterCall_0(v *Value) bool { // match: (InterCall [argwid] entry mem) // result: (CALLinter [argwid] entry mem) for { argwid := v.AuxInt mem := v.Args[1] entry := v.Args[0] v.reset(OpPPC64CALLinter) v.AuxInt = argwid v.AddArg(entry) v.AddArg(mem) return true } } func rewriteValuePPC64_OpIsInBounds_0(v *Value) bool { b := v.Block // match: (IsInBounds idx len) // result: (LessThan (CMPU idx len)) for { len := v.Args[1] idx := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValuePPC64_OpIsNonNil_0(v *Value) bool { b := v.Block // match: (IsNonNil ptr) // result: (NotEqual (CMPconst [0] ptr)) for { ptr := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(ptr) v.AddArg(v0) return true } } func rewriteValuePPC64_OpIsSliceInBounds_0(v *Value) bool { b := v.Block // match: (IsSliceInBounds idx len) // result: (LessEqual (CMPU idx len)) for { len := v.Args[1] idx := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Leq16 x y) // result: (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq16U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Leq16U x y) // result: (LessEqual (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq32_0(v *Value) bool { b := v.Block // match: (Leq32 x y) // result: (LessEqual (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq32F_0(v *Value) bool { b := v.Block // match: (Leq32F x y) // result: (FLessEqual (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FLessEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq32U_0(v *Value) bool { b := v.Block // match: (Leq32U x y) // result: (LessEqual (CMPWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq64_0(v *Value) bool { b := v.Block // match: (Leq64 x y) // result: (LessEqual (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq64F_0(v *Value) bool { b := v.Block // match: (Leq64F x y) // result: (FLessEqual (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FLessEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq64U_0(v *Value) bool { b := v.Block // match: (Leq64U x y) // result: (LessEqual (CMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Leq8 x y) // result: (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq8U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Leq8U x y) // result: (LessEqual (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Less16 x y) // result: (LessThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess16U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Less16U x y) // result: (LessThan (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess32_0(v *Value) bool { b := v.Block // match: (Less32 x y) // result: (LessThan (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess32F_0(v *Value) bool { b := v.Block // match: (Less32F x y) // result: (FLessThan (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FLessThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess32U_0(v *Value) bool { b := v.Block // match: (Less32U x y) // result: (LessThan (CMPWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess64_0(v *Value) bool { b := v.Block // match: (Less64 x y) // result: (LessThan (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess64F_0(v *Value) bool { b := v.Block // match: (Less64F x y) // result: (FLessThan (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FLessThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess64U_0(v *Value) bool { b := v.Block // match: (Less64U x y) // result: (LessThan (CMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Less8 x y) // result: (LessThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess8U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Less8U x y) // result: (LessThan (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLoad_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVDload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpPPC64MOVDload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) && isSigned(t) // result: (MOVWload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitInt(t) && isSigned(t)) { break } v.reset(OpPPC64MOVWload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) && !isSigned(t) // result: (MOVWZload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitInt(t) && !isSigned(t)) { break } v.reset(OpPPC64MOVWZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) && isSigned(t) // result: (MOVHload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is16BitInt(t) && isSigned(t)) { break } v.reset(OpPPC64MOVHload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) && !isSigned(t) // result: (MOVHZload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is16BitInt(t) && !isSigned(t)) { break } v.reset(OpPPC64MOVHZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: t.IsBoolean() // result: (MOVBZload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsBoolean()) { break } v.reset(OpPPC64MOVBZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is8BitInt(t) && isSigned(t) // result: (MOVBreg (MOVBZload ptr mem)) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is8BitInt(t) && isSigned(t)) { break } v.reset(OpPPC64MOVBreg) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Load ptr mem) // cond: is8BitInt(t) && !isSigned(t) // result: (MOVBZload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is8BitInt(t) && !isSigned(t)) { break } v.reset(OpPPC64MOVBZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (FMOVSload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitFloat(t)) { break } v.reset(OpPPC64FMOVSload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (FMOVDload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is64BitFloat(t)) { break } v.reset(OpPPC64FMOVDload) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpLocalAddr_0(v *Value) bool { // match: (LocalAddr {sym} base _) // result: (MOVDaddr {sym} base) for { sym := v.Aux _ = v.Args[1] base := v.Args[0] v.reset(OpPPC64MOVDaddr) v.Aux = sym v.AddArg(base) return true } } func rewriteValuePPC64_OpLsh16x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh16x16 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh16x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x32 x (Const64 [c])) // cond: uint32(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x32 x (MOVDconst [c])) // cond: uint32(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh16x32 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh16x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh16x64 x (MOVDconst [c])) // cond: uint64(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh16x64 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh16x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh16x8 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh32x16 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x32 x (Const64 [c])) // cond: uint32(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x32 x (MOVDconst [c])) // cond: uint32(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh32x32 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh32x64 x (MOVDconst [c])) // cond: uint64(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh32x64 x (AND y (MOVDconst [31]))) // result: (SLW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { break } v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh32x64 x (AND (MOVDconst [31]) y)) // result: (SLW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 31 { break } v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh32x64 x (ANDconst [31] y)) // result: (SLW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst || v_1.Type != typ.Int32 || v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh32x64 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh32x8 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SLD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLD) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh64x16 x y) // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x32 x (Const64 [c])) // cond: uint32(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x32 x (MOVDconst [c])) // cond: uint32(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SLD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLD) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh64x32 x y) // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x64 x (Const64 [c])) // cond: uint64(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh64x64 x (MOVDconst [c])) // cond: uint64(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SLD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLD) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh64x64 x (AND y (MOVDconst [63]))) // result: (SLD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { break } v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh64x64 x (AND (MOVDconst [63]) y)) // result: (SLD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 63 { break } v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh64x64 x (ANDconst [63] y)) // result: (SLD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst || v_1.Type != typ.Int64 || v_1.AuxInt != 63 { break } y := v_1.Args[0] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh64x64 x y) // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SLD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLD) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh64x8 x y) // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh8x16 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x32 x (Const64 [c])) // cond: uint32(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x32 x (MOVDconst [c])) // cond: uint32(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh8x32 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh8x64 x (MOVDconst [c])) // cond: uint64(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh8x64 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh8x8 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod16 x y) // result: (Mod32 (SignExt16to32 x) (SignExt16to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpMod32) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMod16u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpMod32u) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMod32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod32 x y) // result: (SUB x (MULLW y (DIVW x y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLW, typ.Int32) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVW, typ.Int32) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod32u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (SUB x (MULLW y (DIVWU x y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLW, typ.Int32) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVWU, typ.Int32) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod64 x y) // result: (SUB x (MULLD y (DIVD x y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLD, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVD, typ.Int64) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod64u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (SUB x (MULLD y (DIVDU x y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLD, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVDU, typ.Int64) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Mod32 (SignExt8to32 x) (SignExt8to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpMod32) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMod8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpMod32u) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMove_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if v.AuxInt != 0 { break } mem := v.Args[2] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBZload src mem) mem) for { if v.AuxInt != 1 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVBstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [2] dst src mem) // result: (MOVHstore dst (MOVHZload src mem) mem) for { if v.AuxInt != 2 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVHstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [4] dst src mem) // result: (MOVWstore dst (MOVWZload src mem) mem) for { if v.AuxInt != 4 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVWstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [8] {t} dst src mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstore dst (MOVDload src mem) mem) for { if v.AuxInt != 8 { break } t := v.Aux mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, typ.Int64) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [8] dst src mem) // result: (MOVWstore [4] dst (MOVWZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem)) for { if v.AuxInt != 8 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVWstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBZload [2] src mem) (MOVHstore dst (MOVHload src mem) mem)) for { if v.AuxInt != 3 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVBstore) v.AuxInt = 2 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AuxInt = 2 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVHstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVHload, typ.Int16) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem)) for { if v.AuxInt != 5 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVBstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [6] dst src mem) // result: (MOVHstore [4] dst (MOVHZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem)) for { if v.AuxInt != 6 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVHstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [7] dst src mem) // result: (MOVBstore [6] dst (MOVBZload [6] src mem) (MOVHstore [4] dst (MOVHZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem))) for { if v.AuxInt != 7 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVBstore) v.AuxInt = 6 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AuxInt = 6 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVHstore, types.TypeMem) v1.AuxInt = 4 v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16) v2.AuxInt = 4 v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v3.AddArg(dst) v4 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v4.AddArg(src) v4.AddArg(mem) v3.AddArg(v4) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } return false } func rewriteValuePPC64_OpMove_10(v *Value) bool { // match: (Move [s] dst src mem) // cond: s > 8 // result: (LoweredMove [s] dst src mem) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 8) { break } v.reset(OpPPC64LoweredMove) v.AuxInt = s v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpMul16_0(v *Value) bool { // match: (Mul16 x y) // result: (MULLW x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul32_0(v *Value) bool { // match: (Mul32 x y) // result: (MULLW x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul32F_0(v *Value) bool { // match: (Mul32F x y) // result: (FMULS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FMULS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul64_0(v *Value) bool { // match: (Mul64 x y) // result: (MULLD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULLD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul64F_0(v *Value) bool { // match: (Mul64F x y) // result: (FMUL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FMUL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul64uhilo_0(v *Value) bool { // match: (Mul64uhilo x y) // result: (LoweredMuluhilo x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LoweredMuluhilo) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul8_0(v *Value) bool { // match: (Mul8 x y) // result: (MULLW x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpNeg16_0(v *Value) bool { // match: (Neg16 x) // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg32_0(v *Value) bool { // match: (Neg32 x) // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg32F_0(v *Value) bool { // match: (Neg32F x) // result: (FNEG x) for { x := v.Args[0] v.reset(OpPPC64FNEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg64_0(v *Value) bool { // match: (Neg64 x) // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg64F_0(v *Value) bool { // match: (Neg64F x) // result: (FNEG x) for { x := v.Args[0] v.reset(OpPPC64FNEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg8_0(v *Value) bool { // match: (Neg8 x) // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeq16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Neq16 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { y := v.Args[1] x := v.Args[0] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Neq16 y x) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { x := v.Args[1] y := v.Args[0] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Neq16 x y) // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq32_0(v *Value) bool { b := v.Block // match: (Neq32 x y) // result: (NotEqual (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq32F_0(v *Value) bool { b := v.Block // match: (Neq32F x y) // result: (NotEqual (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq64_0(v *Value) bool { b := v.Block // match: (Neq64 x y) // result: (NotEqual (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq64F_0(v *Value) bool { b := v.Block // match: (Neq64F x y) // result: (NotEqual (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Neq8 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { y := v.Args[1] x := v.Args[0] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Neq8 y x) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { x := v.Args[1] y := v.Args[0] if !(isSigned(x.Type) && isSigned(y.Type)) { break } v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Neq8 x y) // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeqB_0(v *Value) bool { // match: (NeqB x y) // result: (XOR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpNeqPtr_0(v *Value) bool { b := v.Block // match: (NeqPtr x y) // result: (NotEqual (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNilCheck_0(v *Value) bool { // match: (NilCheck ptr mem) // result: (LoweredNilCheck ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredNilCheck) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpNot_0(v *Value) bool { // match: (Not x) // result: (XORconst [1] x) for { x := v.Args[0] v.reset(OpPPC64XORconst) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValuePPC64_OpOffPtr_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // result: (ADD (MOVDconst [off]) ptr) for { off := v.AuxInt ptr := v.Args[0] v.reset(OpPPC64ADD) v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = off v.AddArg(v0) v.AddArg(ptr) return true } } func rewriteValuePPC64_OpOr16_0(v *Value) bool { // match: (Or16 x y) // result: (OR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOr32_0(v *Value) bool { // match: (Or32 x y) // result: (OR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOr64_0(v *Value) bool { // match: (Or64 x y) // result: (OR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOr8_0(v *Value) bool { // match: (Or8 x y) // result: (OR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOrB_0(v *Value) bool { // match: (OrB x y) // result: (OR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpPPC64ADD_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADD (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLDconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (SRDconst x [d]) (SLDconst x [c])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLDconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLWconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (SRWconst x [d]) (SLWconst x [c])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLWconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (ADD (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 64 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 63 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int64 || v_1_1.AuxInt != 63 || y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (ADD (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (ADD (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 32 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 31 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int32 || v_1_1.AuxInt != 31 || y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (ADD x (MOVDconst [c])) // cond: is32Bit(c) // result: (ADDconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is32Bit(c)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = c v.AddArg(x) return true } // match: (ADD (MOVDconst [c]) x) // cond: is32Bit(c) // result: (ADDconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt if !(is32Bit(c)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ADDconst_0(v *Value) bool { // match: (ADDconst [c] (ADDconst [d] x)) // cond: is32Bit(c+d) // result: (ADDconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = c + d v.AddArg(x) return true } // match: (ADDconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDconst [c] (MOVDaddr [d] {sym} x)) // result: (MOVDaddr [c+d] {sym} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDaddr { break } d := v_0.AuxInt sym := v_0.Aux x := v_0.Args[0] v.reset(OpPPC64MOVDaddr) v.AuxInt = c + d v.Aux = sym v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64AND_0(v *Value) bool { // match: (AND x (NOR y y)) // result: (ANDN x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64NOR { break } y := v_1.Args[1] if y != v_1.Args[0] { break } v.reset(OpPPC64ANDN) v.AddArg(x) v.AddArg(y) return true } // match: (AND (NOR y y) x) // result: (ANDN x y) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64NOR { break } y := v_0.Args[1] if y != v_0.Args[0] { break } v.reset(OpPPC64ANDN) v.AddArg(x) v.AddArg(y) return true } // match: (AND (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c&d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } d := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c & d return true } // match: (AND (MOVDconst [d]) (MOVDconst [c])) // result: (MOVDconst [c&d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c & d return true } // match: (AND x (MOVDconst [c])) // cond: isU16Bit(c) // result: (ANDconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64ANDconst) v.AuxInt = c v.AddArg(x) return true } // match: (AND (MOVDconst [c]) x) // cond: isU16Bit(c) // result: (ANDconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64ANDconst) v.AuxInt = c v.AddArg(x) return true } // match: (AND (MOVDconst [c]) y:(MOVWZreg _)) // cond: c&0xFFFFFFFF == 0xFFFFFFFF // result: y for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt y := v.Args[1] if y.Op != OpPPC64MOVWZreg || !(c&0xFFFFFFFF == 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (AND y:(MOVWZreg _) (MOVDconst [c])) // cond: c&0xFFFFFFFF == 0xFFFFFFFF // result: y for { _ = v.Args[1] y := v.Args[0] if y.Op != OpPPC64MOVWZreg { break } v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(c&0xFFFFFFFF == 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (AND (MOVDconst [0xFFFFFFFF]) y:(MOVWreg x)) // result: (MOVWZreg x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst || v_0.AuxInt != 0xFFFFFFFF { break } y := v.Args[1] if y.Op != OpPPC64MOVWreg { break } x := y.Args[0] v.reset(OpPPC64MOVWZreg) v.AddArg(x) return true } // match: (AND y:(MOVWreg x) (MOVDconst [0xFFFFFFFF])) // result: (MOVWZreg x) for { _ = v.Args[1] y := v.Args[0] if y.Op != OpPPC64MOVWreg { break } x := y.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst || v_1.AuxInt != 0xFFFFFFFF { break } v.reset(OpPPC64MOVWZreg) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64AND_10(v *Value) bool { // match: (AND (MOVDconst [c]) x:(MOVBZload _ _)) // result: (ANDconst [c&0xFF] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt x := v.Args[1] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } // match: (AND x:(MOVBZload _ _) (MOVDconst [c])) // result: (ANDconst [c&0xFF] x) for { _ = v.Args[1] x := v.Args[0] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ANDconst_0(v *Value) bool { // match: (ANDconst [c] (ANDconst [d] x)) // result: (ANDconst [c&d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64ANDconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDconst [-1] x) // result: x for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDconst [0] _) // result: (MOVDconst [0]) for { if v.AuxInt != 0 { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ANDconst [c] y:(MOVBZreg _)) // cond: c&0xFF == 0xFF // result: y for { c := v.AuxInt y := v.Args[0] if y.Op != OpPPC64MOVBZreg || !(c&0xFF == 0xFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [0xFF] y:(MOVBreg _)) // result: y for { if v.AuxInt != 0xFF { break } y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [c] y:(MOVHZreg _)) // cond: c&0xFFFF == 0xFFFF // result: y for { c := v.AuxInt y := v.Args[0] if y.Op != OpPPC64MOVHZreg || !(c&0xFFFF == 0xFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [0xFFFF] y:(MOVHreg _)) // result: y for { if v.AuxInt != 0xFFFF { break } y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [c] (MOVBreg x)) // result: (ANDconst [c&0xFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } // match: (ANDconst [c] (MOVBZreg x)) // result: (ANDconst [c&0xFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBZreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } // match: (ANDconst [c] (MOVHreg x)) // result: (ANDconst [c&0xFFFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVHreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFFFF v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ANDconst_10(v *Value) bool { // match: (ANDconst [c] (MOVHZreg x)) // result: (ANDconst [c&0xFFFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVHZreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFFFF v.AddArg(x) return true } // match: (ANDconst [c] (MOVWreg x)) // result: (ANDconst [c&0xFFFFFFFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFFFFFFFF v.AddArg(x) return true } // match: (ANDconst [c] (MOVWZreg x)) // result: (ANDconst [c&0xFFFFFFFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWZreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFFFFFFFF v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64CMP_0(v *Value) bool { b := v.Block // match: (CMP x (MOVDconst [c])) // cond: is16Bit(c) // result: (CMPconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64CMPconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMP (MOVDconst [c]) y) // cond: is16Bit(c) // result: (InvertFlags (CMPconst y [c])) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPU_0(v *Value) bool { b := v.Block // match: (CMPU x (MOVDconst [c])) // cond: isU16Bit(c) // result: (CMPUconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64CMPUconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPU (MOVDconst [c]) y) // cond: isU16Bit(c) // result: (InvertFlags (CMPUconst y [c])) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPUconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPUconst_0(v *Value) bool { // match: (CMPUconst (MOVDconst [x]) [y]) // cond: x==y // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(x == y) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPUconst (MOVDconst [x]) [y]) // cond: uint64(x)uint64(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(uint64(x) > uint64(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64CMPW_0(v *Value) bool { b := v.Block // match: (CMPW x (MOVWreg y)) // result: (CMPW x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } y := v_1.Args[0] v.reset(OpPPC64CMPW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPW (MOVWreg x) y) // result: (CMPW x y) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWreg { break } x := v_0.Args[0] v.reset(OpPPC64CMPW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPW x (MOVDconst [c])) // cond: is16Bit(c) // result: (CMPWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64CMPWconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPW (MOVDconst [c]) y) // cond: is16Bit(c) // result: (InvertFlags (CMPWconst y [c])) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPWconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPWU_0(v *Value) bool { b := v.Block // match: (CMPWU x (MOVWZreg y)) // result: (CMPWU x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } y := v_1.Args[0] v.reset(OpPPC64CMPWU) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWU (MOVWZreg x) y) // result: (CMPWU x y) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWZreg { break } x := v_0.Args[0] v.reset(OpPPC64CMPWU) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWU x (MOVDconst [c])) // cond: isU16Bit(c) // result: (CMPWUconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64CMPWUconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPWU (MOVDconst [c]) y) // cond: isU16Bit(c) // result: (InvertFlags (CMPWUconst y [c])) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPWUconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPWUconst_0(v *Value) bool { // match: (CMPWUconst (MOVDconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPWUconst (MOVDconst [x]) [y]) // cond: uint32(x)uint32(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(uint32(x) > uint32(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64CMPWconst_0(v *Value) bool { // match: (CMPWconst (MOVDconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPWconst (MOVDconst [x]) [y]) // cond: int32(x)int32(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int32(x) > int32(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64CMPconst_0(v *Value) bool { // match: (CMPconst (MOVDconst [x]) [y]) // cond: x==y // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(x == y) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPconst (MOVDconst [x]) [y]) // cond: xy // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(x > y) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64Equal_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Equal (FlagEQ)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (Equal (FlagLT)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Equal (FlagGT)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Equal (InvertFlags x)) // result: (Equal x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64Equal) v.AddArg(x) return true } // match: (Equal cmp) // result: (ISELB [2] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 2 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64FABS_0(v *Value) bool { // match: (FABS (FMOVDconst [x])) // result: (FMOVDconst [auxFrom64F(math.Abs(auxTo64F(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = auxFrom64F(math.Abs(auxTo64F(x))) return true } return false } func rewriteValuePPC64_OpPPC64FADD_0(v *Value) bool { // match: (FADD (FMUL x y) z) // result: (FMADD x y z) for { z := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMUL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpPPC64FMADD) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } // match: (FADD z (FMUL x y)) // result: (FMADD x y z) for { _ = v.Args[1] z := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64FMUL { break } y := v_1.Args[1] x := v_1.Args[0] v.reset(OpPPC64FMADD) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FADDS_0(v *Value) bool { // match: (FADDS (FMULS x y) z) // result: (FMADDS x y z) for { z := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMULS { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpPPC64FMADDS) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } // match: (FADDS z (FMULS x y)) // result: (FMADDS x y z) for { _ = v.Args[1] z := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64FMULS { break } y := v_1.Args[1] x := v_1.Args[0] v.reset(OpPPC64FMADDS) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FCEIL_0(v *Value) bool { // match: (FCEIL (FMOVDconst [x])) // result: (FMOVDconst [auxFrom64F(math.Ceil(auxTo64F(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = auxFrom64F(math.Ceil(auxTo64F(x))) return true } return false } func rewriteValuePPC64_OpPPC64FFLOOR_0(v *Value) bool { // match: (FFLOOR (FMOVDconst [x])) // result: (FMOVDconst [auxFrom64F(math.Floor(auxTo64F(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = auxFrom64F(math.Floor(auxTo64F(x))) return true } return false } func rewriteValuePPC64_OpPPC64FGreaterEqual_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (FGreaterEqual cmp) // result: (ISEL [2] (MOVDconst [1]) (ISELB [1] (MOVDconst [1]) cmp) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISEL) v.AuxInt = 2 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ISELB, typ.Int32) v1.AuxInt = 1 v2 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v2.AuxInt = 1 v1.AddArg(v2) v1.AddArg(cmp) v.AddArg(v1) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64FGreaterThan_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (FGreaterThan cmp) // result: (ISELB [1] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 1 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64FLessEqual_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (FLessEqual cmp) // result: (ISEL [2] (MOVDconst [1]) (ISELB [0] (MOVDconst [1]) cmp) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISEL) v.AuxInt = 2 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ISELB, typ.Int32) v1.AuxInt = 0 v2 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v2.AuxInt = 1 v1.AddArg(v2) v1.AddArg(cmp) v.AddArg(v1) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64FLessThan_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (FLessThan cmp) // result: (ISELB [0] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 0 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64FMOVDload_0(v *Value) bool { // match: (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr x _)) // result: (MTVSRD x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } x := v_1.Args[1] v.reset(OpPPC64MTVSRD) v.AddArg(x) return true } // match: (FMOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is16Bit(off1+off2) // result: (FMOVDload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FMOVDstore_0(v *Value) bool { // match: (FMOVDstore [off] {sym} ptr (MTVSRD x) mem) // result: (MOVDstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MTVSRD { break } x := v_1.Args[0] v.reset(OpPPC64MOVDstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is16Bit(off1+off2) // result: (FMOVDstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (FMOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FMOVSload_0(v *Value) bool { // match: (FMOVSload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is16Bit(off1+off2) // result: (FMOVSload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FMOVSstore_0(v *Value) bool { // match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is16Bit(off1+off2) // result: (FMOVSstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVSstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (FMOVSstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVSstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FNEG_0(v *Value) bool { // match: (FNEG (FABS x)) // result: (FNABS x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FABS { break } x := v_0.Args[0] v.reset(OpPPC64FNABS) v.AddArg(x) return true } // match: (FNEG (FNABS x)) // result: (FABS x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FNABS { break } x := v_0.Args[0] v.reset(OpPPC64FABS) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64FSQRT_0(v *Value) bool { // match: (FSQRT (FMOVDconst [x])) // result: (FMOVDconst [auxFrom64F(math.Sqrt(auxTo64F(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = auxFrom64F(math.Sqrt(auxTo64F(x))) return true } return false } func rewriteValuePPC64_OpPPC64FSUB_0(v *Value) bool { // match: (FSUB (FMUL x y) z) // result: (FMSUB x y z) for { z := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMUL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpPPC64FMSUB) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FSUBS_0(v *Value) bool { // match: (FSUBS (FMULS x y) z) // result: (FMSUBS x y z) for { z := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMULS { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpPPC64FMSUBS) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FTRUNC_0(v *Value) bool { // match: (FTRUNC (FMOVDconst [x])) // result: (FMOVDconst [auxFrom64F(math.Trunc(auxTo64F(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = auxFrom64F(math.Trunc(auxTo64F(x))) return true } return false } func rewriteValuePPC64_OpPPC64GreaterEqual_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (GreaterEqual (FlagEQ)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (GreaterEqual (FlagLT)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (GreaterEqual (FlagGT)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (GreaterEqual (InvertFlags x)) // result: (LessEqual x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64LessEqual) v.AddArg(x) return true } // match: (GreaterEqual cmp) // result: (ISELB [4] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 4 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64GreaterThan_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (GreaterThan (FlagEQ)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (GreaterThan (FlagLT)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (GreaterThan (FlagGT)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (GreaterThan (InvertFlags x)) // result: (LessThan x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64LessThan) v.AddArg(x) return true } // match: (GreaterThan cmp) // result: (ISELB [1] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 1 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64ISEL_0(v *Value) bool { // match: (ISEL [2] x _ (FlagEQ)) // result: x for { if v.AuxInt != 2 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagEQ { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [2] _ y (FlagLT)) // result: y for { if v.AuxInt != 2 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagLT { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [2] _ y (FlagGT)) // result: y for { if v.AuxInt != 2 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagGT { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [6] _ y (FlagEQ)) // result: y for { if v.AuxInt != 6 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagEQ { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [6] x _ (FlagLT)) // result: x for { if v.AuxInt != 6 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagLT { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [6] x _ (FlagGT)) // result: x for { if v.AuxInt != 6 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagGT { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [0] _ y (FlagEQ)) // result: y for { if v.AuxInt != 0 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagEQ { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [0] _ y (FlagGT)) // result: y for { if v.AuxInt != 0 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagGT { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [0] x _ (FlagLT)) // result: x for { if v.AuxInt != 0 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagLT { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [5] _ x (FlagEQ)) // result: x for { if v.AuxInt != 5 { break } _ = v.Args[2] x := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagEQ { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ISEL_10(v *Value) bool { // match: (ISEL [5] _ x (FlagLT)) // result: x for { if v.AuxInt != 5 { break } _ = v.Args[2] x := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagLT { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [5] y _ (FlagGT)) // result: y for { if v.AuxInt != 5 { break } _ = v.Args[2] y := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagGT { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [1] _ y (FlagEQ)) // result: y for { if v.AuxInt != 1 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagEQ { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [1] _ y (FlagLT)) // result: y for { if v.AuxInt != 1 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagLT { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [1] x _ (FlagGT)) // result: x for { if v.AuxInt != 1 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagGT { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [4] x _ (FlagEQ)) // result: x for { if v.AuxInt != 4 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagEQ { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [4] x _ (FlagGT)) // result: x for { if v.AuxInt != 4 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagGT { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [4] _ y (FlagLT)) // result: y for { if v.AuxInt != 4 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagLT { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [n] x y (InvertFlags bool)) // cond: n%4 == 0 // result: (ISEL [n+1] x y bool) for { n := v.AuxInt _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64InvertFlags { break } bool := v_2.Args[0] if !(n%4 == 0) { break } v.reset(OpPPC64ISEL) v.AuxInt = n + 1 v.AddArg(x) v.AddArg(y) v.AddArg(bool) return true } // match: (ISEL [n] x y (InvertFlags bool)) // cond: n%4 == 1 // result: (ISEL [n-1] x y bool) for { n := v.AuxInt _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64InvertFlags { break } bool := v_2.Args[0] if !(n%4 == 1) { break } v.reset(OpPPC64ISEL) v.AuxInt = n - 1 v.AddArg(x) v.AddArg(y) v.AddArg(bool) return true } return false } func rewriteValuePPC64_OpPPC64ISEL_20(v *Value) bool { // match: (ISEL [n] x y (InvertFlags bool)) // cond: n%4 == 2 // result: (ISEL [n] x y bool) for { n := v.AuxInt _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64InvertFlags { break } bool := v_2.Args[0] if !(n%4 == 2) { break } v.reset(OpPPC64ISEL) v.AuxInt = n v.AddArg(x) v.AddArg(y) v.AddArg(bool) return true } return false } func rewriteValuePPC64_OpPPC64ISELB_0(v *Value) bool { // match: (ISELB [0] _ (FlagLT)) // result: (MOVDconst [1]) for { if v.AuxInt != 0 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [0] _ (FlagGT)) // result: (MOVDconst [0]) for { if v.AuxInt != 0 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [0] _ (FlagEQ)) // result: (MOVDconst [0]) for { if v.AuxInt != 0 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [1] _ (FlagGT)) // result: (MOVDconst [1]) for { if v.AuxInt != 1 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [1] _ (FlagLT)) // result: (MOVDconst [0]) for { if v.AuxInt != 1 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [1] _ (FlagEQ)) // result: (MOVDconst [0]) for { if v.AuxInt != 1 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [2] _ (FlagEQ)) // result: (MOVDconst [1]) for { if v.AuxInt != 2 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [2] _ (FlagLT)) // result: (MOVDconst [0]) for { if v.AuxInt != 2 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [2] _ (FlagGT)) // result: (MOVDconst [0]) for { if v.AuxInt != 2 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [4] _ (FlagLT)) // result: (MOVDconst [0]) for { if v.AuxInt != 4 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } return false } func rewriteValuePPC64_OpPPC64ISELB_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ISELB [4] _ (FlagGT)) // result: (MOVDconst [1]) for { if v.AuxInt != 4 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [4] _ (FlagEQ)) // result: (MOVDconst [1]) for { if v.AuxInt != 4 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [5] _ (FlagGT)) // result: (MOVDconst [0]) for { if v.AuxInt != 5 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [5] _ (FlagLT)) // result: (MOVDconst [1]) for { if v.AuxInt != 5 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [5] _ (FlagEQ)) // result: (MOVDconst [1]) for { if v.AuxInt != 5 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [6] _ (FlagEQ)) // result: (MOVDconst [0]) for { if v.AuxInt != 6 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [6] _ (FlagLT)) // result: (MOVDconst [1]) for { if v.AuxInt != 6 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [6] _ (FlagGT)) // result: (MOVDconst [1]) for { if v.AuxInt != 6 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [n] (MOVDconst [1]) (InvertFlags bool)) // cond: n%4 == 0 // result: (ISELB [n+1] (MOVDconst [1]) bool) for { n := v.AuxInt _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst || v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpPPC64InvertFlags { break } bool := v_1.Args[0] if !(n%4 == 0) { break } v.reset(OpPPC64ISELB) v.AuxInt = n + 1 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(bool) return true } // match: (ISELB [n] (MOVDconst [1]) (InvertFlags bool)) // cond: n%4 == 1 // result: (ISELB [n-1] (MOVDconst [1]) bool) for { n := v.AuxInt _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst || v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpPPC64InvertFlags { break } bool := v_1.Args[0] if !(n%4 == 1) { break } v.reset(OpPPC64ISELB) v.AuxInt = n - 1 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(bool) return true } return false } func rewriteValuePPC64_OpPPC64ISELB_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ISELB [n] (MOVDconst [1]) (InvertFlags bool)) // cond: n%4 == 2 // result: (ISELB [n] (MOVDconst [1]) bool) for { n := v.AuxInt _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst || v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpPPC64InvertFlags { break } bool := v_1.Args[0] if !(n%4 == 2) { break } v.reset(OpPPC64ISELB) v.AuxInt = n v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(bool) return true } return false } func rewriteValuePPC64_OpPPC64LessEqual_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (LessEqual (FlagEQ)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (LessEqual (FlagLT)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (LessEqual (FlagGT)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (LessEqual (InvertFlags x)) // result: (GreaterEqual x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64GreaterEqual) v.AddArg(x) return true } // match: (LessEqual cmp) // result: (ISELB [5] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 5 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64LessThan_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (LessThan (FlagEQ)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (LessThan (FlagLT)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (LessThan (FlagGT)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (LessThan (InvertFlags x)) // result: (GreaterThan x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64GreaterThan) v.AddArg(x) return true } // match: (LessThan cmp) // result: (ISELB [0] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 0 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64MFVSRD_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MFVSRD (FMOVDconst [c])) // result: (MOVDconst [c]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c return true } // match: (MFVSRD x:(FMOVDload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVDload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpPPC64FMOVDload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpPPC64MOVDload, typ.Int64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBZload_0(v *Value) bool { // match: (MOVBZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVBZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVBZload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBZload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVBZload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVBZload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBZload [0] {sym} p:(ADD ptr idx) mem) // cond: sym == nil && p.Uses == 1 // result: (MOVBZloadidx ptr idx mem) for { if v.AuxInt != 0 { break } sym := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] if !(sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVBZloadidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBZloadidx_0(v *Value) bool { // match: (MOVBZloadidx ptr (MOVDconst [c]) mem) // cond: is16Bit(c) // result: (MOVBZload [c] ptr mem) for { mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64MOVBZload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBZloadidx (MOVDconst [c]) ptr mem) // cond: is16Bit(c) // result: (MOVBZload [c] ptr mem) for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVBZload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBZreg_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVBZreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBZreg (SRWconst [c] (MOVBZreg x))) // result: (SRWconst [c] (MOVBZreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVBZreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVBZreg (SRWconst [c] x)) // cond: sizeof(x.Type) == 8 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(sizeof(x.Type) == 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBZreg (SRDconst [c] x)) // cond: c>=56 // result: (SRDconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c >= 56) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBZreg (SRWconst [c] x)) // cond: c>=24 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c >= 24) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBZreg y:(MOVBZreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBZreg (MOVBreg x)) // result: (MOVBZreg x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBreg { break } x := v_0.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } // match: (MOVBZreg x:(MOVBZload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVBZreg x:(MOVBZloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVBZreg x:(Arg )) // cond: is8BitInt(t) && !isSigned(t) // result: x for { x := v.Args[0] if x.Op != OpArg { break } t := x.Type if !(is8BitInt(t) && !isSigned(t)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MOVBZreg_10(v *Value) bool { // match: (MOVBZreg (MOVDconst [c])) // result: (MOVDconst [int64(uint8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(uint8(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVBreg_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVBreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0x7F // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0x7F) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBreg (SRAWconst [c] (MOVBreg x))) // result: (SRAWconst [c] (MOVBreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVBreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVBreg (SRAWconst [c] x)) // cond: sizeof(x.Type) == 8 // result: (SRAWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(sizeof(x.Type) == 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBreg (SRDconst [c] x)) // cond: c>56 // result: (SRDconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c > 56) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBreg (SRDconst [c] x)) // cond: c==56 // result: (SRADconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c == 56) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBreg (SRWconst [c] x)) // cond: c>24 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c > 24) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBreg (SRWconst [c] x)) // cond: c==24 // result: (SRAWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c == 24) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBreg y:(MOVBreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBreg (MOVBZreg x)) // result: (MOVBreg x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBZreg { break } x := v_0.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } // match: (MOVBreg x:(Arg )) // cond: is8BitInt(t) && isSigned(t) // result: x for { x := v.Args[0] if x.Op != OpArg { break } t := x.Type if !(is8BitInt(t) && isSigned(t)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MOVBreg_10(v *Value) bool { // match: (MOVBreg (MOVDconst [c])) // result: (MOVDconst [int64(int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(int8(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstore_0(v *Value) bool { // match: (MOVBstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVBstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst || v_1.AuxInt != 0 { break } v.reset(OpPPC64MOVBstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} p:(ADD ptr idx) val mem) // cond: off == 0 && sym == nil && p.Uses == 1 // result: (MOVBstoreidx ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] val := v.Args[1] if !(off == 0 && sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVBstoreidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVBreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBZreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVBZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVHZreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVWZreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstore_10(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVBstore [off] {sym} ptr (SRWconst (MOVHreg x) [c]) mem) // cond: c <= 8 // result: (MOVBstore [off] {sym} ptr (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } c := v_1.AuxInt v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVHreg { break } x := v_1_0.Args[0] if !(c <= 8) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (SRWconst (MOVHZreg x) [c]) mem) // cond: c <= 8 // result: (MOVBstore [off] {sym} ptr (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } c := v_1.AuxInt v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVHZreg { break } x := v_1_0.Args[0] if !(c <= 8) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (SRWconst (MOVWreg x) [c]) mem) // cond: c <= 24 // result: (MOVBstore [off] {sym} ptr (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } c := v_1.AuxInt v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVWreg { break } x := v_1_0.Args[0] if !(c <= 24) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (SRWconst (MOVWZreg x) [c]) mem) // cond: c <= 24 // result: (MOVBstore [off] {sym} ptr (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } c := v_1.AuxInt v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVWZreg { break } x := v_1_0.Args[0] if !(c <= 24) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i1] {s} p (SRWconst w [24]) x0:(MOVBstore [i0] {s} p (SRWconst w [16]) mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0) // result: (MOVHstore [i0] {s} p (SRWconst w [16]) mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst || v_1.AuxInt != 24 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRWconst || x0_1.AuxInt != 16 || w != x0_1.Args[0] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpPPC64SRWconst, typ.UInt16) v0.AuxInt = 16 v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i1] {s} p (SRDconst w [24]) x0:(MOVBstore [i0] {s} p (SRDconst w [16]) mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0) // result: (MOVHstore [i0] {s} p (SRWconst w [16]) mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst || v_1.AuxInt != 24 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRDconst || x0_1.AuxInt != 16 || w != x0_1.Args[0] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpPPC64SRWconst, typ.UInt16) v0.AuxInt = 16 v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i1] {s} p (SRWconst w [8]) x0:(MOVBstore [i0] {s} p w mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0) // result: (MOVHstore [i0] {s} p w mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] || w != x0.Args[1] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i1] {s} p (SRDconst w [8]) x0:(MOVBstore [i0] {s} p w mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0) // result: (MOVHstore [i0] {s} p w mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] || w != x0.Args[1] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i3] {s} p w x0:(MOVBstore [i2] {s} p (SRWconst w [8]) x1:(MOVBstore [i1] {s} p (SRWconst w [16]) x2:(MOVBstore [i0] {s} p (SRWconst w [24]) mem)))) // cond: !config.BigEndian && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && clobber(x0) && clobber(x1) && clobber(x2) // result: (MOVWBRstore (MOVDaddr [i0] {s} p) w mem) for { i3 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i2 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRWconst || x0_1.AuxInt != 8 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpPPC64MOVBstore { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpPPC64SRWconst || x1_1.AuxInt != 16 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpPPC64MOVBstore { break } i0 := x2.AuxInt if x2.Aux != s { break } mem := x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpPPC64SRWconst || x2_1.AuxInt != 24 || w != x2_1.Args[0] || !(!config.BigEndian && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && clobber(x0) && clobber(x1) && clobber(x2)) { break } v.reset(OpPPC64MOVWBRstore) v0 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i1] {s} p w x0:(MOVBstore [i0] {s} p (SRWconst w [8]) mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0) // result: (MOVHBRstore (MOVDaddr [i0] {s} p) w mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRWconst || x0_1.AuxInt != 8 || w != x0_1.Args[0] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0)) { break } v.reset(OpPPC64MOVHBRstore) v0 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstore_20(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVBstore [i7] {s} p (SRDconst w [56]) x0:(MOVBstore [i6] {s} p (SRDconst w [48]) x1:(MOVBstore [i5] {s} p (SRDconst w [40]) x2:(MOVBstore [i4] {s} p (SRDconst w [32]) x3:(MOVWstore [i0] {s} p w mem))))) // cond: !config.BigEndian && i0%4 == 0 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) // result: (MOVDstore [i0] {s} p w mem) for { i7 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst || v_1.AuxInt != 56 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i6 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRDconst || x0_1.AuxInt != 48 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpPPC64MOVBstore { break } i5 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpPPC64SRDconst || x1_1.AuxInt != 40 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpPPC64MOVBstore { break } i4 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpPPC64SRDconst || x2_1.AuxInt != 32 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpPPC64MOVWstore { break } i0 := x3.AuxInt if x3.Aux != s { break } mem := x3.Args[2] if p != x3.Args[0] || w != x3.Args[1] || !(!config.BigEndian && i0%4 == 0 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3)) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i7] {s} p w x0:(MOVBstore [i6] {s} p (SRDconst w [8]) x1:(MOVBstore [i5] {s} p (SRDconst w [16]) x2:(MOVBstore [i4] {s} p (SRDconst w [24]) x3:(MOVBstore [i3] {s} p (SRDconst w [32]) x4:(MOVBstore [i2] {s} p (SRDconst w [40]) x5:(MOVBstore [i1] {s} p (SRDconst w [48]) x6:(MOVBstore [i0] {s} p (SRDconst w [56]) mem)))))))) // cond: !config.BigEndian && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) // result: (MOVDBRstore (MOVDaddr [i0] {s} p) w mem) for { i7 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i6 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRDconst || x0_1.AuxInt != 8 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpPPC64MOVBstore { break } i5 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpPPC64SRDconst || x1_1.AuxInt != 16 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpPPC64MOVBstore { break } i4 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpPPC64SRDconst || x2_1.AuxInt != 24 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpPPC64MOVBstore { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpPPC64SRDconst || x3_1.AuxInt != 32 || w != x3_1.Args[0] { break } x4 := x3.Args[2] if x4.Op != OpPPC64MOVBstore { break } i2 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpPPC64SRDconst || x4_1.AuxInt != 40 || w != x4_1.Args[0] { break } x5 := x4.Args[2] if x5.Op != OpPPC64MOVBstore { break } i1 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpPPC64SRDconst || x5_1.AuxInt != 48 || w != x5_1.Args[0] { break } x6 := x5.Args[2] if x6.Op != OpPPC64MOVBstore { break } i0 := x6.AuxInt if x6.Aux != s { break } mem := x6.Args[2] if p != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpPPC64SRDconst || x6_1.AuxInt != 56 || w != x6_1.Args[0] || !(!config.BigEndian && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { break } v.reset(OpPPC64MOVDBRstore) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstoreidx_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVBstoreidx ptr (MOVDconst [c]) val mem) // cond: is16Bit(c) // result: (MOVBstore [c] ptr val mem) for { mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt val := v.Args[2] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx (MOVDconst [c]) ptr val mem) // cond: is16Bit(c) // result: (MOVBstore [c] ptr val mem) for { mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] val := v.Args[2] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (MOVBreg x) mem) // result: (MOVBstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVBreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (MOVBZreg x) mem) // result: (MOVBstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVBZreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (MOVHreg x) mem) // result: (MOVBstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVHreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (MOVHZreg x) mem) // result: (MOVBstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVHZreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (MOVWreg x) mem) // result: (MOVBstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVWreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (MOVWZreg x) mem) // result: (MOVBstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVWZreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (SRWconst (MOVHreg x) [c]) mem) // cond: c <= 8 // result: (MOVBstoreidx [off] {sym} ptr idx (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64SRWconst { break } c := v_2.AuxInt v_2_0 := v_2.Args[0] if v_2_0.Op != OpPPC64MOVHreg { break } x := v_2_0.Args[0] if !(c <= 8) { break } v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (SRWconst (MOVHZreg x) [c]) mem) // cond: c <= 8 // result: (MOVBstoreidx [off] {sym} ptr idx (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64SRWconst { break } c := v_2.AuxInt v_2_0 := v_2.Args[0] if v_2_0.Op != OpPPC64MOVHZreg { break } x := v_2_0.Args[0] if !(c <= 8) { break } v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstoreidx_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVBstoreidx [off] {sym} ptr idx (SRWconst (MOVWreg x) [c]) mem) // cond: c <= 24 // result: (MOVBstoreidx [off] {sym} ptr idx (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64SRWconst { break } c := v_2.AuxInt v_2_0 := v_2.Args[0] if v_2_0.Op != OpPPC64MOVWreg { break } x := v_2_0.Args[0] if !(c <= 24) { break } v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (SRWconst (MOVWZreg x) [c]) mem) // cond: c <= 24 // result: (MOVBstoreidx [off] {sym} ptr idx (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64SRWconst { break } c := v_2.AuxInt v_2_0 := v_2.Args[0] if v_2_0.Op != OpPPC64MOVWZreg { break } x := v_2_0.Args[0] if !(c <= 24) { break } v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstorezero_0(v *Value) bool { // match: (MOVBstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVBstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVBstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVBstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDload_0(v *Value) bool { // match: (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr x _)) // result: (MFVSRD x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64FMOVDstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } x := v_1.Args[1] v.reset(OpPPC64MFVSRD) v.AddArg(x) return true } // match: (MOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVDload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) && (off1+off2)%4 == 0 // result: (MOVDload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1+off2) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVDload [0] {sym} p:(ADD ptr idx) mem) // cond: sym == nil && p.Uses == 1 // result: (MOVDloadidx ptr idx mem) for { if v.AuxInt != 0 { break } sym := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] if !(sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVDloadidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDloadidx_0(v *Value) bool { // match: (MOVDloadidx ptr (MOVDconst [c]) mem) // cond: is16Bit(c) && c%4 == 0 // result: (MOVDload [c] ptr mem) for { mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c) && c%4 == 0) { break } v.reset(OpPPC64MOVDload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVDloadidx (MOVDconst [c]) ptr mem) // cond: is16Bit(c) && c%4 == 0 // result: (MOVDload [c] ptr mem) for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] if !(is16Bit(c) && c%4 == 0) { break } v.reset(OpPPC64MOVDload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDstore_0(v *Value) bool { // match: (MOVDstore [off] {sym} ptr (MFVSRD x) mem) // result: (FMOVDstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MFVSRD { break } x := v_1.Args[0] v.reset(OpPPC64FMOVDstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVDstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) && (off1+off2)%4 == 0 // result: (MOVDstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] if !(is16Bit(off1+off2) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVDstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVDstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst || v_1.AuxInt != 0 { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVDstore [off] {sym} p:(ADD ptr idx) val mem) // cond: off == 0 && sym == nil && p.Uses == 1 // result: (MOVDstoreidx ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] val := v.Args[1] if !(off == 0 && sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVDstoreidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDstoreidx_0(v *Value) bool { // match: (MOVDstoreidx ptr (MOVDconst [c]) val mem) // cond: is16Bit(c) && c%4 == 0 // result: (MOVDstore [c] ptr val mem) for { mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt val := v.Args[2] if !(is16Bit(c) && c%4 == 0) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVDstoreidx (MOVDconst [c]) ptr val mem) // cond: is16Bit(c) && c%4 == 0 // result: (MOVDstore [c] ptr val mem) for { mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] val := v.Args[2] if !(is16Bit(c) && c%4 == 0) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDstorezero_0(v *Value) bool { // match: (MOVDstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) && (off1+off2)%4 == 0 // result: (MOVDstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1+off2) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVDstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 // result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHBRstore_0(v *Value) bool { // match: (MOVHBRstore {sym} ptr (MOVHreg x) mem) // result: (MOVHBRstore {sym} ptr x mem) for { sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHBRstore) v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHBRstore {sym} ptr (MOVHZreg x) mem) // result: (MOVHBRstore {sym} ptr x mem) for { sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHBRstore) v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHBRstore {sym} ptr (MOVWreg x) mem) // result: (MOVHBRstore {sym} ptr x mem) for { sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHBRstore) v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHBRstore {sym} ptr (MOVWZreg x) mem) // result: (MOVHBRstore {sym} ptr x mem) for { sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHBRstore) v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHZload_0(v *Value) bool { // match: (MOVHZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVHZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHZload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHZload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVHZload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHZload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHZload [0] {sym} p:(ADD ptr idx) mem) // cond: sym == nil && p.Uses == 1 // result: (MOVHZloadidx ptr idx mem) for { if v.AuxInt != 0 { break } sym := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] if !(sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVHZloadidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHZloadidx_0(v *Value) bool { // match: (MOVHZloadidx ptr (MOVDconst [c]) mem) // cond: is16Bit(c) // result: (MOVHZload [c] ptr mem) for { mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64MOVHZload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHZloadidx (MOVDconst [c]) ptr mem) // cond: is16Bit(c) // result: (MOVHZload [c] ptr mem) for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVHZload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHZreg_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVHZreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg (SRWconst [c] (MOVBZreg x))) // result: (SRWconst [c] (MOVBZreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVBZreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVHZreg (SRWconst [c] (MOVHZreg x))) // result: (SRWconst [c] (MOVHZreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVHZreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVHZreg (SRWconst [c] x)) // cond: sizeof(x.Type) <= 16 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(sizeof(x.Type) <= 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHZreg (SRDconst [c] x)) // cond: c>=48 // result: (SRDconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c >= 48) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHZreg (SRWconst [c] x)) // cond: c>=16 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c >= 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHZreg y:(MOVHZreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg y:(MOVBZreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg y:(MOVHBRload _ _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHBRload { break } _ = y.Args[1] v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg y:(MOVHreg x)) // result: (MOVHZreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } x := y.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MOVHZreg_10(v *Value) bool { // match: (MOVHZreg x:(MOVBZload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHZreg x:(MOVBZloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHZreg x:(MOVHZload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHZreg x:(MOVHZloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHZloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHZreg x:(Arg )) // cond: (is8BitInt(t) || is16BitInt(t)) && !isSigned(t) // result: x for { x := v.Args[0] if x.Op != OpArg { break } t := x.Type if !((is8BitInt(t) || is16BitInt(t)) && !isSigned(t)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHZreg (MOVDconst [c])) // result: (MOVDconst [int64(uint16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(uint16(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVHload_0(v *Value) bool { // match: (MOVHload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVHload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHload [0] {sym} p:(ADD ptr idx) mem) // cond: sym == nil && p.Uses == 1 // result: (MOVHloadidx ptr idx mem) for { if v.AuxInt != 0 { break } sym := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] if !(sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVHloadidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHloadidx_0(v *Value) bool { // match: (MOVHloadidx ptr (MOVDconst [c]) mem) // cond: is16Bit(c) // result: (MOVHload [c] ptr mem) for { mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64MOVHload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHloadidx (MOVDconst [c]) ptr mem) // cond: is16Bit(c) // result: (MOVHload [c] ptr mem) for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVHload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHreg_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVHreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0x7FFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0x7FFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHreg (SRAWconst [c] (MOVBreg x))) // result: (SRAWconst [c] (MOVBreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVBreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVHreg (SRAWconst [c] (MOVHreg x))) // result: (SRAWconst [c] (MOVHreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVHreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVHreg (SRAWconst [c] x)) // cond: sizeof(x.Type) <= 16 // result: (SRAWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(sizeof(x.Type) <= 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHreg (SRDconst [c] x)) // cond: c>48 // result: (SRDconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c > 48) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHreg (SRDconst [c] x)) // cond: c==48 // result: (SRADconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c == 48) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHreg (SRWconst [c] x)) // cond: c>16 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c > 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHreg (SRWconst [c] x)) // cond: c==16 // result: (SRAWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c == 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHreg y:(MOVHreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHreg y:(MOVBreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } return false } func rewriteValuePPC64_OpPPC64MOVHreg_10(v *Value) bool { // match: (MOVHreg y:(MOVHZreg x)) // result: (MOVHreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } x := y.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHreg x:(MOVHloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHreg x:(Arg )) // cond: (is8BitInt(t) || is16BitInt(t)) && isSigned(t) // result: x for { x := v.Args[0] if x.Op != OpArg { break } t := x.Type if !((is8BitInt(t) || is16BitInt(t)) && isSigned(t)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHreg (MOVDconst [c])) // result: (MOVDconst [int64(int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(int16(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVHstore_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVHstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVHstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVHstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst || v_1.AuxInt != 0 { break } v.reset(OpPPC64MOVHstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} p:(ADD ptr idx) val mem) // cond: off == 0 && sym == nil && p.Uses == 1 // result: (MOVHstoreidx ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] val := v.Args[1] if !(off == 0 && sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVHstoreidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHZreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVWZreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstore [i1] {s} p (SRWconst w [16]) x0:(MOVHstore [i0] {s} p w mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+2 && clobber(x0) // result: (MOVWstore [i0] {s} p w mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst || v_1.AuxInt != 16 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVHstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] || w != x0.Args[1] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+2 && clobber(x0)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVHstore [i1] {s} p (SRDconst w [16]) x0:(MOVHstore [i0] {s} p w mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+2 && clobber(x0) // result: (MOVWstore [i0] {s} p w mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst || v_1.AuxInt != 16 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVHstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] || w != x0.Args[1] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+2 && clobber(x0)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHstoreidx_0(v *Value) bool { // match: (MOVHstoreidx ptr (MOVDconst [c]) val mem) // cond: is16Bit(c) // result: (MOVHstore [c] ptr val mem) for { mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt val := v.Args[2] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstoreidx (MOVDconst [c]) ptr val mem) // cond: is16Bit(c) // result: (MOVHstore [c] ptr val mem) for { mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] val := v.Args[2] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstoreidx [off] {sym} ptr idx (MOVHreg x) mem) // result: (MOVHstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVHreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVHstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstoreidx [off] {sym} ptr idx (MOVHZreg x) mem) // result: (MOVHstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVHZreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVHstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstoreidx [off] {sym} ptr idx (MOVWreg x) mem) // result: (MOVHstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVWreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVHstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstoreidx [off] {sym} ptr idx (MOVWZreg x) mem) // result: (MOVHstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVWZreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVHstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHstorezero_0(v *Value) bool { // match: (MOVHstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVHstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWBRstore_0(v *Value) bool { // match: (MOVWBRstore {sym} ptr (MOVWreg x) mem) // result: (MOVWBRstore {sym} ptr x mem) for { sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVWBRstore) v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWBRstore {sym} ptr (MOVWZreg x) mem) // result: (MOVWBRstore {sym} ptr x mem) for { sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVWBRstore) v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZload_0(v *Value) bool { // match: (MOVWZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVWZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWZload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWZload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVWZload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWZload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWZload [0] {sym} p:(ADD ptr idx) mem) // cond: sym == nil && p.Uses == 1 // result: (MOVWZloadidx ptr idx mem) for { if v.AuxInt != 0 { break } sym := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] if !(sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVWZloadidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZloadidx_0(v *Value) bool { // match: (MOVWZloadidx ptr (MOVDconst [c]) mem) // cond: is16Bit(c) // result: (MOVWZload [c] ptr mem) for { mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64MOVWZload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWZloadidx (MOVDconst [c]) ptr mem) // cond: is16Bit(c) // result: (MOVWZload [c] ptr mem) for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVWZload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZreg_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVWZreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFFFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(AND (MOVDconst [c]) _)) // cond: uint64(c) <= 0xFFFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] y_0 := y.Args[0] if y_0.Op != OpPPC64MOVDconst { break } c := y_0.AuxInt if !(uint64(c) <= 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(AND _ (MOVDconst [c]))) // cond: uint64(c) <= 0xFFFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] y_1 := y.Args[1] if y_1.Op != OpPPC64MOVDconst { break } c := y_1.AuxInt if !(uint64(c) <= 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg (SRWconst [c] (MOVBZreg x))) // result: (SRWconst [c] (MOVBZreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVBZreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVWZreg (SRWconst [c] (MOVHZreg x))) // result: (SRWconst [c] (MOVHZreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVHZreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVWZreg (SRWconst [c] (MOVWZreg x))) // result: (SRWconst [c] (MOVWZreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVWZreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVWZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVWZreg (SRWconst [c] x)) // cond: sizeof(x.Type) <= 32 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(sizeof(x.Type) <= 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVWZreg (SRDconst [c] x)) // cond: c>=32 // result: (SRDconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c >= 32) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVWZreg y:(MOVWZreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVWZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVHZreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZreg_10(v *Value) bool { // match: (MOVWZreg y:(MOVBZreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVHBRload _ _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHBRload { break } _ = y.Args[1] v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVWBRload _ _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVWBRload { break } _ = y.Args[1] v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVWreg x)) // result: (MOVWZreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVWreg { break } x := y.Args[0] v.reset(OpPPC64MOVWZreg) v.AddArg(x) return true } // match: (MOVWZreg x:(MOVBZload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWZreg x:(MOVBZloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWZreg x:(MOVHZload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWZreg x:(MOVHZloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHZloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWZreg x:(MOVWZload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVWZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWZreg x:(MOVWZloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVWZloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZreg_20(v *Value) bool { // match: (MOVWZreg x:(Arg )) // cond: (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !isSigned(t) // result: x for { x := v.Args[0] if x.Op != OpArg { break } t := x.Type if !((is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !isSigned(t)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWZreg (MOVDconst [c])) // result: (MOVDconst [int64(uint32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(uint32(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVWload_0(v *Value) bool { // match: (MOVWload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) && (off1+off2)%4 == 0 // result: (MOVWload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1+off2) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWload [0] {sym} p:(ADD ptr idx) mem) // cond: sym == nil && p.Uses == 1 // result: (MOVWloadidx ptr idx mem) for { if v.AuxInt != 0 { break } sym := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] if !(sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVWloadidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWloadidx_0(v *Value) bool { // match: (MOVWloadidx ptr (MOVDconst [c]) mem) // cond: is16Bit(c) && c%4 == 0 // result: (MOVWload [c] ptr mem) for { mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c) && c%4 == 0) { break } v.reset(OpPPC64MOVWload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWloadidx (MOVDconst [c]) ptr mem) // cond: is16Bit(c) && c%4 == 0 // result: (MOVWload [c] ptr mem) for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] if !(is16Bit(c) && c%4 == 0) { break } v.reset(OpPPC64MOVWload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWreg_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVWreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(AND (MOVDconst [c]) _)) // cond: uint64(c) <= 0x7FFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] y_0 := y.Args[0] if y_0.Op != OpPPC64MOVDconst { break } c := y_0.AuxInt if !(uint64(c) <= 0x7FFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(AND _ (MOVDconst [c]))) // cond: uint64(c) <= 0x7FFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] y_1 := y.Args[1] if y_1.Op != OpPPC64MOVDconst { break } c := y_1.AuxInt if !(uint64(c) <= 0x7FFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg (SRAWconst [c] (MOVBreg x))) // result: (SRAWconst [c] (MOVBreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVBreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVWreg (SRAWconst [c] (MOVHreg x))) // result: (SRAWconst [c] (MOVHreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVHreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVWreg (SRAWconst [c] (MOVWreg x))) // result: (SRAWconst [c] (MOVWreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVWreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVWreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVWreg (SRAWconst [c] x)) // cond: sizeof(x.Type) <= 32 // result: (SRAWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(sizeof(x.Type) <= 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVWreg (SRDconst [c] x)) // cond: c>32 // result: (SRDconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c > 32) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVWreg (SRDconst [c] x)) // cond: c==32 // result: (SRADconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c == 32) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVWreg y:(MOVWreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVWreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } return false } func rewriteValuePPC64_OpPPC64MOVWreg_10(v *Value) bool { // match: (MOVWreg y:(MOVHreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(MOVBreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(MOVWZreg x)) // result: (MOVWreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVWZreg { break } x := y.Args[0] v.reset(OpPPC64MOVWreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWreg x:(MOVHloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWreg x:(MOVWload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVWload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWreg x:(MOVWloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVWloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWreg x:(Arg )) // cond: (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && isSigned(t) // result: x for { x := v.Args[0] if x.Op != OpArg { break } t := x.Type if !((is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && isSigned(t)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWreg (MOVDconst [c])) // result: (MOVDconst [int64(int32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(int32(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVWstore_0(v *Value) bool { // match: (MOVWstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVWstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst || v_1.AuxInt != 0 { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} p:(ADD ptr idx) val mem) // cond: off == 0 && sym == nil && p.Uses == 1 // result: (MOVWstoreidx ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] val := v.Args[1] if !(off == 0 && sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVWstoreidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWZreg x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWstoreidx_0(v *Value) bool { // match: (MOVWstoreidx ptr (MOVDconst [c]) val mem) // cond: is16Bit(c) // result: (MOVWstore [c] ptr val mem) for { mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt val := v.Args[2] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx (MOVDconst [c]) ptr val mem) // cond: is16Bit(c) // result: (MOVWstore [c] ptr val mem) for { mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] val := v.Args[2] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx [off] {sym} ptr idx (MOVWreg x) mem) // result: (MOVWstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVWreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVWstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstoreidx [off] {sym} ptr idx (MOVWZreg x) mem) // result: (MOVWstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVWZreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVWstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWstorezero_0(v *Value) bool { // match: (MOVWstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVWstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MTVSRD_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MTVSRD (MOVDconst [c])) // result: (FMOVDconst [c]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = c return true } // match: (MTVSRD x:(MOVDload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (FMOVDload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpPPC64MOVDload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpPPC64FMOVDload, typ.Float64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MaskIfNotCarry_0(v *Value) bool { // match: (MaskIfNotCarry (ADDconstForCarry [c] (ANDconst [d] _))) // cond: c < 0 && d > 0 && c + d < 0 // result: (MOVDconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconstForCarry { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } d := v_0_0.AuxInt if !(c < 0 && d > 0 && c+d < 0) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = -1 return true } return false } func rewriteValuePPC64_OpPPC64NotEqual_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (NotEqual (FlagEQ)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (NotEqual (FlagLT)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (NotEqual (FlagGT)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (NotEqual (InvertFlags x)) // result: (NotEqual x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64NotEqual) v.AddArg(x) return true } // match: (NotEqual cmp) // result: (ISELB [6] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 6 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64OR_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (OR (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLDconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (SRDconst x [d]) (SLDconst x [c])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLDconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLWconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (SRWconst x [d]) (SLWconst x [c])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLWconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (OR (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 64 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 63 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int64 || v_1_1.AuxInt != 63 || y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (OR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (OR (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 32 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 31 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int32 || v_1_1.AuxInt != 31 || y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (OR (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c|d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } d := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c | d return true } // match: (OR (MOVDconst [d]) (MOVDconst [c])) // result: (MOVDconst [c|d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c | d return true } return false } func rewriteValuePPC64_OpPPC64OR_10(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (OR x (MOVDconst [c])) // cond: isU32Bit(c) // result: (ORconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU32Bit(c)) { break } v.reset(OpPPC64ORconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR (MOVDconst [c]) x) // cond: isU32Bit(c) // result: (ORconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt if !(isU32Bit(c)) { break } v.reset(OpPPC64ORconst) v.AuxInt = c v.AddArg(x) return true } // match: (OR x0:(MOVBZload [i0] {s} p mem) o1:(SLWconst x1:(MOVBZload [i1] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o1 := v.Args[1] if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { break } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpPPC64MOVHZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o1:(SLWconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o1 := v.Args[0] if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { break } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpPPC64MOVHZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR x0:(MOVBZload [i0] {s} p mem) o1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o1 := v.Args[1] if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { break } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpPPC64MOVHZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o1 := v.Args[0] if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { break } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpPPC64MOVHZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR x0:(MOVBZload [i1] {s} p mem) o1:(SLWconst x1:(MOVBZload [i0] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpPPC64MOVBZload { break } i1 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o1 := v.Args[1] if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { break } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i0 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o1:(SLWconst x1:(MOVBZload [i0] {s} p mem) [8]) x0:(MOVBZload [i1] {s} p mem)) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o1 := v.Args[0] if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { break } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i0 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpPPC64MOVBZload { break } i1 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpPPC64MOVHBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x0:(MOVBZload [i1] {s} p mem) o1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpPPC64MOVBZload { break } i1 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o1 := v.Args[1] if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { break } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i0 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [8]) x0:(MOVBZload [i1] {s} p mem)) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o1 := v.Args[0] if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { break } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i0 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := v.Args[1] if x0.Op != OpPPC64MOVBZload { break } i1 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpPPC64MOVHBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_20(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (OR s0:(SLWconst x0:(MOVBZload [i1] {s} p mem) [n1]) s1:(SLWconst x1:(MOVBZload [i0] {s} p mem) [n2])) // cond: !config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) // result: @mergePoint(b,x0,x1) (SLDconst (MOVHBRload (MOVDaddr [i0] {s} p) mem) [n1]) for { t := v.Type _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpPPC64SLWconst { break } n1 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i1 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpPPC64SLWconst { break } n2 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i0 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = n1 v1 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (OR s1:(SLWconst x1:(MOVBZload [i0] {s} p mem) [n2]) s0:(SLWconst x0:(MOVBZload [i1] {s} p mem) [n1])) // cond: !config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) // result: @mergePoint(b,x0,x1) (SLDconst (MOVHBRload (MOVDaddr [i0] {s} p) mem) [n1]) for { t := v.Type _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpPPC64SLWconst { break } n2 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i0 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpPPC64SLWconst { break } n1 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i1 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = n1 v1 := b.NewValue0(x0.Pos, OpPPC64MOVHBRload, t) v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (OR s0:(SLDconst x0:(MOVBZload [i1] {s} p mem) [n1]) s1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [n2])) // cond: !config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) // result: @mergePoint(b,x0,x1) (SLDconst (MOVHBRload (MOVDaddr [i0] {s} p) mem) [n1]) for { t := v.Type _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpPPC64SLDconst { break } n1 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i1 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1] if s1.Op != OpPPC64SLDconst { break } n2 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i0 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = n1 v1 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (OR s1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [n2]) s0:(SLDconst x0:(MOVBZload [i1] {s} p mem) [n1])) // cond: !config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) // result: @mergePoint(b,x0,x1) (SLDconst (MOVHBRload (MOVDaddr [i0] {s} p) mem) [n1]) for { t := v.Type _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpPPC64SLDconst { break } n2 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i0 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := v.Args[1] if s0.Op != OpPPC64SLDconst { break } n1 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i1 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = n1 v1 := b.NewValue0(x0.Pos, OpPPC64MOVHBRload, t) v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (OR s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVHZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVHZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x1.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem)) s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24])) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := o0.Args[1] if x0.Op != OpPPC64MOVHZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s1 := v.Args[1] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16])) s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24])) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVHZload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s0 := o0.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s1 := v.Args[1] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s1:(SLDconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVHZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s1:(SLDconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [16]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVHZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x1.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_30(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (OR o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i3] {s} p mem) [24])) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := o0.Args[1] if x0.Op != OpPPC64MOVHZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s1 := v.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [16])) s1:(SLDconst x2:(MOVBZload [i3] {s} p mem) [24])) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVHZload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s1 := v.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s1:(SLWconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR s0:(SLWconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i0 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i2 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR s1:(SLWconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) s0:(SLWconst x1:(MOVBZload [i1] {s} p mem) [16]))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i0 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i2 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR s0:(SLWconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem)) s1:(SLWconst x2:(MOVBZload [i0] {s} p mem) [24])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := o0.Args[1] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i2 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { break } s1 := v.Args[1] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i0 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) s0:(SLWconst x1:(MOVBZload [i1] {s} p mem) [16])) s1:(SLWconst x2:(MOVBZload [i0] {s} p mem) [24])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } mem := x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i2 := x0_0.AuxInt s := x0_0.Aux p := x0_0.Args[0] s0 := o0.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s1 := v.Args[1] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i0 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR s1:(SLDconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i0 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } x0 := o0.Args[1] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i2 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR s1:(SLDconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [16]))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] s1 := v.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i0 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i2 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem)) s1:(SLDconst x2:(MOVBZload [i0] {s} p mem) [24])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] x0 := o0.Args[1] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i2 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { break } s1 := v.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i0 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [16])) s1:(SLDconst x2:(MOVBZload [i0] {s} p mem) [24])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } mem := x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i2 := x0_0.AuxInt s := x0_0.Aux p := x0_0.Args[0] s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s1 := v.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { break } i0 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_40(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLWconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpPPC64MOVBZload { break } i3 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s1 := o0.Args[1] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVHBRload || x2.Type != t { break } _ = x2.Args[1] x2_0 := x2.Args[0] if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { break } i0 := x2_0.AuxInt if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s1:(SLWconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [8]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpPPC64MOVBZload { break } i3 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVHBRload || x2.Type != t { break } _ = x2.Args[1] x2_0 := x2.Args[0] if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { break } i0 := x2_0.AuxInt if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLWconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16])) x0:(MOVBZload [i3] {s} p mem)) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s1 := o0.Args[1] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVHBRload || x2.Type != t { break } _ = x2.Args[1] x2_0 := x2.Args[0] if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { break } i0 := x2_0.AuxInt if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] { break } x0 := v.Args[1] if x0.Op != OpPPC64MOVBZload { break } i3 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR s1:(SLWconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [8])) x0:(MOVBZload [i3] {s} p mem)) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVHBRload || x2.Type != t { break } mem := x2.Args[1] x2_0 := x2.Args[0] if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { break } i0 := x2_0.AuxInt s := x2_0.Aux p := x2_0.Args[0] s0 := o0.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } x0 := v.Args[1] if x0.Op != OpPPC64MOVBZload { break } i3 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLDconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpPPC64MOVBZload { break } i3 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVHBRload || x2.Type != t { break } _ = x2.Args[1] x2_0 := x2.Args[0] if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { break } i0 := x2_0.AuxInt if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s1:(SLDconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]) s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [8]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x0 := v.Args[0] if x0.Op != OpPPC64MOVBZload { break } i3 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVHBRload || x2.Type != t { break } _ = x2.Args[1] x2_0 := x2.Args[0] if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { break } i0 := x2_0.AuxInt if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLDconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16])) x0:(MOVBZload [i3] {s} p mem)) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVHBRload || x2.Type != t { break } _ = x2.Args[1] x2_0 := x2.Args[0] if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { break } i0 := x2_0.AuxInt if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] { break } x0 := v.Args[1] if x0.Op != OpPPC64MOVBZload { break } i3 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR s1:(SLDconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]) s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [8])) x0:(MOVBZload [i3] {s} p mem)) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { break } x2 := s1.Args[0] if x2.Op != OpPPC64MOVHBRload || x2.Type != t { break } mem := x2.Args[1] x2_0 := x2.Args[0] if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { break } i0 := x2_0.AuxInt s := x2_0.Aux p := x2_0.Args[0] s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { break } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } x0 := v.Args[1] if x0.Op != OpPPC64MOVBZload { break } i3 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR s2:(SLDconst x2:(MOVBZload [i3] {s} p mem) [32]) o0:(OR s1:(SLDconst x1:(MOVBZload [i2] {s} p mem) [40]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [48]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) for { t := v.Type _ = v.Args[1] s2 := v.Args[0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i0 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 32 v1 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (OR s2:(SLDconst x2:(MOVBZload [i3] {s} p mem) [32]) o0:(OR s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [48]) s1:(SLDconst x1:(MOVBZload [i2] {s} p mem) [40]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) for { t := v.Type _ = v.Args[1] s2 := v.Args[0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i0 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { break } s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 32 v1 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } return false } func rewriteValuePPC64_OpPPC64OR_50(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i2] {s} p mem) [40]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [48])) s2:(SLDconst x2:(MOVBZload [i3] {s} p mem) [32])) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i0 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { break } s2 := v.Args[1] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 32 v1 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) v2 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (OR o0:(OR s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [48]) s1:(SLDconst x1:(MOVBZload [i2] {s} p mem) [40])) s2:(SLDconst x2:(MOVBZload [i3] {s} p mem) [32])) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } mem := x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i0 := x0_0.AuxInt s := x0_0.Aux p := x0_0.Args[0] s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i2 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s2 := v.Args[1] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i3 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 32 v1 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) v2 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (OR s2:(SLDconst x2:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) [32]))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) for { t := v.Type _ = v.Args[1] s2 := v.Args[0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i0 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i2 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 32 v1 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (OR s2:(SLDconst x2:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) [32]) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) for { t := v.Type _ = v.Args[1] s2 := v.Args[0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i0 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i2 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { break } s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 32 v1 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) [32])) s2:(SLDconst x2:(MOVBZload [i0] {s} p mem) [56])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] s0 := o0.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i2 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { break } s2 := v.Args[1] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i0 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 32 v1 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) v2 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (OR o0:(OR s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) [32]) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s2:(SLDconst x2:(MOVBZload [i0] {s} p mem) [56])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s0 := o0.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { break } mem := x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { break } i2 := x0_0.AuxInt s := x0_0.Aux p := x0_0.Args[0] s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s2 := v.Args[1] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i0 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 32 v1 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) v2 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem))))) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } x0 := o3.Args[1] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x0.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] x0 := o3.Args[0] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x4.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } x0 := o3.Args[1] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x5.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] x0 := o3.Args[0] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x5.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_60(v *Value) bool { b := v.Block config := b.Func.Config // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } x0 := o3.Args[1] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] x0 := o3.Args[0] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } x0 := o3.Args[1] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] s6 := v.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] x0 := o3.Args[0] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux mem := x6.Args[1] p := x6.Args[0] o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } x0 := o3.Args[1] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux mem := x6.Args[1] p := x6.Args[0] o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] x0 := o3.Args[0] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux mem := x6.Args[1] p := x6.Args[0] o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } x0 := o3.Args[1] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s5 := o5.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux mem := x6.Args[1] p := x6.Args[0] o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] x0 := o3.Args[0] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux mem := x5.Args[1] p := x5.Args[0] o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } x0 := o3.Args[1] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s4 := o4.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux mem := x5.Args[1] p := x5.Args[0] o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] x0 := o3.Args[0] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_70(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s3 := o3.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt s := x4.Aux mem := x4.Args[1] p := x4.Args[0] x0 := o3.Args[1] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] x0 := o3.Args[0] if x0.Op != OpPPC64MOVWZload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s3 := o3.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s4 := o4.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { break } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s5 := o5.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { break } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } s6 := v.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { break } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { break } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem))))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } o1 := o0.Args[1] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] s2 := o1.Args[0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } o2 := o1.Args[1] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] s3 := o2.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } x4 := o2.Args[1] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x4.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x4.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]))))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } o1 := o0.Args[1] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] s2 := o1.Args[0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } o2 := o1.Args[1] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] x4 := o2.Args[0] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s3 := o2.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } o1 := o0.Args[1] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] s3 := o2.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } x4 := o2.Args[1] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s2 := o1.Args[1] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x2.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } o1 := o0.Args[1] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] x4 := o2.Args[0] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s3 := o2.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } s2 := o1.Args[1] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x2.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem))) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] s2 := o1.Args[0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } o2 := o1.Args[1] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] s3 := o2.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } x4 := o2.Args[1] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x1.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]))) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] s2 := o1.Args[0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } o2 := o1.Args[1] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] x4 := o2.Args[0] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s3 := o2.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x1.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR o1:(OR o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] s3 := o2.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } x4 := o2.Args[1] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s2 := o1.Args[1] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x1.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR o1:(OR o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] s0 := v.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] x4 := o2.Args[0] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s3 := o2.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } s2 := o1.Args[1] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x1.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_80(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)))) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] o1 := o0.Args[1] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] s2 := o1.Args[0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } o2 := o1.Args[1] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] s3 := o2.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } x4 := o2.Args[1] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s0 := v.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])))) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] o1 := o0.Args[1] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] s2 := o1.Args[0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } o2 := o1.Args[1] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] x4 := o2.Args[0] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s3 := o2.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } s0 := v.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]))) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] o1 := o0.Args[1] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] s3 := o2.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } x4 := o2.Args[1] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s2 := o1.Args[1] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } s0 := v.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]))) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] s1 := o0.Args[0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt s := x1.Aux mem := x1.Args[1] p := x1.Args[0] o1 := o0.Args[1] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] x4 := o2.Args[0] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s3 := o2.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } s2 := o1.Args[1] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } s0 := v.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem))) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] s2 := o1.Args[0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o2 := o1.Args[1] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] s3 := o2.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } x4 := o2.Args[1] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s0 := v.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]))) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] s2 := o1.Args[0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o2 := o1.Args[1] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] x4 := o2.Args[0] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s3 := o2.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s0 := v.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR o1:(OR o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] s3 := o2.Args[0] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt s := x3.Aux mem := x3.Args[1] p := x3.Args[0] x4 := o2.Args[1] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] { break } s2 := o1.Args[1] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s0 := v.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o0:(OR o1:(OR o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o0 := v.Args[0] if o0.Op != OpPPC64OR || o0.Type != t { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpPPC64OR || o1.Type != t { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpPPC64OR || o2.Type != t { break } _ = o2.Args[1] x4 := o2.Args[0] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { break } mem := x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { break } i4 := x4_0.AuxInt p := x4_0.Args[0] s3 := o2.Args[1] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { break } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { break } i3 := x3.AuxInt s := x3.Aux _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } s2 := o1.Args[1] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { break } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { break } i2 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } s1 := o0.Args[1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { break } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } s0 := v.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { break } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { break } i0 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x4.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x4.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_90(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x5.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x5.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x5.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x5.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])))) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux mem := x6.Args[1] p := x6.Args[0] o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])))) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux mem := x6.Args[1] p := x6.Args[0] o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]))) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux mem := x6.Args[1] p := x6.Args[0] o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]))) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux mem := x6.Args[1] p := x6.Args[0] o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_100(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (OR o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux mem := x5.Args[1] p := x5.Args[0] o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux mem := x5.Args[1] p := x5.Args[0] o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt s := x4.Aux mem := x4.Args[1] p := x4.Args[0] s0 := o3.Args[1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } mem := x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt s := x3_0.Aux p := x3_0.Args[0] s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x4.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x4.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x5.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x5.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x5.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x5.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64OR_110(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] x7 := v.Args[0] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])))) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux mem := x6.Args[1] p := x6.Args[0] o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])))) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux mem := x6.Args[1] p := x6.Args[0] o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]))) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux mem := x6.Args[1] p := x6.Args[0] o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]))) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] s6 := o5.Args[0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt s := x6.Aux mem := x6.Args[1] p := x6.Args[0] o4 := o5.Args[1] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux mem := x5.Args[1] p := x5.Args[0] o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s0 := o3.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] s5 := o4.Args[0] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt s := x5.Aux mem := x5.Args[1] p := x5.Args[0] o3 := o4.Args[1] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s4 := o3.Args[0] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt s := x4.Aux mem := x4.Args[1] p := x4.Args[0] s0 := o3.Args[1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } // match: (OR o5:(OR o4:(OR o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] o5 := v.Args[0] if o5.Op != OpPPC64OR || o5.Type != t { break } _ = o5.Args[1] o4 := o5.Args[0] if o4.Op != OpPPC64OR || o4.Type != t { break } _ = o4.Args[1] o3 := o4.Args[0] if o3.Op != OpPPC64OR || o3.Type != t { break } _ = o3.Args[1] s0 := o3.Args[0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { break } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { break } mem := x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { break } i0 := x3_0.AuxInt s := x3_0.Aux p := x3_0.Args[0] s4 := o3.Args[1] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { break } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { break } i4 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { break } s5 := o4.Args[1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { break } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { break } i5 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { break } s6 := o5.Args[1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { break } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { break } i6 := x6.AuxInt if x6.Aux != s { break } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { break } x7 := v.Args[1] if x7.Op != OpPPC64MOVBZload { break } i7 := x7.AuxInt if x7.Aux != s { break } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { break } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64ORN_0(v *Value) bool { // match: (ORN x (MOVDconst [-1])) // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst || v_1.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ORconst_0(v *Value) bool { // match: (ORconst [c] (ORconst [d] x)) // result: (ORconst [c|d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64ORconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpPPC64ORconst) v.AuxInt = c | d v.AddArg(x) return true } // match: (ORconst [-1] _) // result: (MOVDconst [-1]) for { if v.AuxInt != -1 { break } v.reset(OpPPC64MOVDconst) v.AuxInt = -1 return true } // match: (ORconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ROTL_0(v *Value) bool { // match: (ROTL x (MOVDconst [c])) // result: (ROTLconst x [c&63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64ROTLconst) v.AuxInt = c & 63 v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ROTLW_0(v *Value) bool { // match: (ROTLW x (MOVDconst [c])) // result: (ROTLWconst x [c&31]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64ROTLWconst) v.AuxInt = c & 31 v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64SUB_0(v *Value) bool { // match: (SUB x (MOVDconst [c])) // cond: is32Bit(-c) // result: (ADDconst [-c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is32Bit(-c)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = -c v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64XOR_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (XOR (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLDconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (SRDconst x [d]) (SLDconst x [c])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLDconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { break } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLWconst { break } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (SRWconst x [d]) (SLWconst x [c])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } d := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLWconst { break } c := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { break } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (XOR (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) // result: (ROTL x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRD { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 64 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 63 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLD { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int64 || v_1_1.AuxInt != 63 || y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } // match: (XOR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SLW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { break } y := v_0_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { break } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (XOR (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) // result: (ROTLW x y) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64SRW { break } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { break } _ = v_0_1.Args[1] v_0_1_0 := v_0_1.Args[0] if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 32 { break } v_0_1_1 := v_0_1.Args[1] if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 31 { break } y := v_0_1_1.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SLW { break } _ = v_1.Args[1] if x != v_1.Args[0] { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int32 || v_1_1.AuxInt != 31 || y != v_1_1.Args[0] { break } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } // match: (XOR (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c^d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } d := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c ^ d return true } // match: (XOR (MOVDconst [d]) (MOVDconst [c])) // result: (MOVDconst [c^d]) for { _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } d := v_0.AuxInt v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c ^ d return true } return false } func rewriteValuePPC64_OpPPC64XOR_10(v *Value) bool { // match: (XOR x (MOVDconst [c])) // cond: isU32Bit(c) // result: (XORconst [c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU32Bit(c)) { break } v.reset(OpPPC64XORconst) v.AuxInt = c v.AddArg(x) return true } // match: (XOR (MOVDconst [c]) x) // cond: isU32Bit(c) // result: (XORconst [c] x) for { x := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt if !(isU32Bit(c)) { break } v.reset(OpPPC64XORconst) v.AuxInt = c v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64XORconst_0(v *Value) bool { // match: (XORconst [c] (XORconst [d] x)) // result: (XORconst [c^d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64XORconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpPPC64XORconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPanicBounds_0(v *Value) bool { // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 0) { break } v.reset(OpPPC64LoweredPanicBoundsA) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 1) { break } v.reset(OpPPC64LoweredPanicBoundsB) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 2) { break } v.reset(OpPPC64LoweredPanicBoundsC) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPopCount16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTW (MOVHZreg x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpPopCount32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount32 x) // result: (POPCNTW (MOVWZreg x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpPopCount64_0(v *Value) bool { // match: (PopCount64 x) // result: (POPCNTD x) for { x := v.Args[0] v.reset(OpPPC64POPCNTD) v.AddArg(x) return true } } func rewriteValuePPC64_OpPopCount8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTB (MOVBZreg x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTB) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRotateLeft16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (RotateLeft16 x (MOVDconst [c])) // result: (Or16 (Lsh16x64 x (MOVDconst [c&15])) (Rsh16Ux64 x (MOVDconst [-c&15]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = c & 15 v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpRsh16Ux64, t) v2.AddArg(x) v3 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v3.AuxInt = -c & 15 v2.AddArg(v3) v.AddArg(v2) return true } return false } func rewriteValuePPC64_OpRotateLeft32_0(v *Value) bool { // match: (RotateLeft32 x (MOVDconst [c])) // result: (ROTLWconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64ROTLWconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (RotateLeft32 x y) // result: (ROTLW x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpRotateLeft64_0(v *Value) bool { // match: (RotateLeft64 x (MOVDconst [c])) // result: (ROTLconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64ROTLconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (RotateLeft64 x y) // result: (ROTL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpRotateLeft8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (RotateLeft8 x (MOVDconst [c])) // result: (Or8 (Lsh8x64 x (MOVDconst [c&7])) (Rsh8Ux64 x (MOVDconst [-c&7]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = c & 7 v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpRsh8Ux64, t) v2.AddArg(x) v3 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v3.AuxInt = -c & 7 v2.AddArg(v3) v.AddArg(v2) return true } return false } func rewriteValuePPC64_OpRound_0(v *Value) bool { // match: (Round x) // result: (FROUND x) for { x := v.Args[0] v.reset(OpPPC64FROUND) v.AddArg(x) return true } } func rewriteValuePPC64_OpRound32F_0(v *Value) bool { // match: (Round32F x) // result: (LoweredRound32F x) for { x := v.Args[0] v.reset(OpPPC64LoweredRound32F) v.AddArg(x) return true } } func rewriteValuePPC64_OpRound64F_0(v *Value) bool { // match: (Round64F x) // result: (LoweredRound64F x) for { x := v.Args[0] v.reset(OpPPC64LoweredRound64F) v.AddArg(x) return true } } func rewriteValuePPC64_OpRsh16Ux16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVHZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16Ux16 x y) // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16Ux32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux32 x (Const64 [c])) // cond: uint32(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux32 x (MOVDconst [c])) // cond: uint32(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVHZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16Ux32 x y) // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh16Ux64 x (MOVDconst [c])) // cond: uint64(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVHZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16Ux64 x y) // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16Ux8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVHZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16Ux8 x y) // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVHreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16x16 x y) // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x32 x (Const64 [c])) // cond: uint32(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x32 x (MOVDconst [c])) // cond: uint32(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVHreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16x32 x y) // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x64 x (Const64 [c])) // cond: uint64(c) >= 16 // result: (SRAWconst (SignExt16to32 x) [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x64 x (MOVDconst [c])) // cond: uint64(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVHreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16x64 x y) // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVHreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16x8 x y) // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh32Ux16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32Ux16 x y) // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32Ux32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux32 x (Const64 [c])) // cond: uint32(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux32 x (MOVDconst [c])) // cond: uint32(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32Ux32 x y) // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh32Ux64 x (MOVDconst [c])) // cond: uint64(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32Ux64 x (AND y (MOVDconst [31]))) // result: (SRW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { break } v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (AND (MOVDconst [31]) y)) // result: (SRW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 31 { break } v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (ANDconst [31] y)) // result: (SRW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst || v_1.Type != typ.UInt || v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (SUB (MOVDconst [32]) (ANDconst [31] y))) // result: (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.UInt || v_1_1.AuxInt != 31 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (SUB (MOVDconst [32]) (AND y (MOVDconst [31])))) // result: (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] y := v_1_1.Args[0] v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 31 { break } v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (SUB (MOVDconst [32]) (AND (MOVDconst [31]) y))) // result: (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { break } y := v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 31 { break } v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpRsh32Ux64_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux64 x y) // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32Ux8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32Ux8 x y) // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SRAW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32x16 x y) // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x32 x (Const64 [c])) // cond: uint32(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x32 x (MOVDconst [c])) // cond: uint32(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SRAW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32x32 x y) // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x64 x (Const64 [c])) // cond: uint64(c) >= 32 // result: (SRAWconst x [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = 63 v.AddArg(x) return true } // match: (Rsh32x64 x (MOVDconst [c])) // cond: uint64(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SRAW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32x64 x (AND y (MOVDconst [31]))) // result: (SRAW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { break } v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32x64 x (AND (MOVDconst [31]) y)) // result: (SRAW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 31 { break } v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32x64 x (ANDconst [31] y)) // result: (SRAW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst || v_1.Type != typ.UInt || v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32x64 x (SUB (MOVDconst [32]) (ANDconst [31] y))) // result: (SRAW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.UInt || v_1_1.AuxInt != 31 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32x64 x (SUB (MOVDconst [32]) (AND y (MOVDconst [31])))) // result: (SRAW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] y := v_1_1.Args[0] v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 31 { break } v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32x64 x (SUB (MOVDconst [32]) (AND (MOVDconst [31]) y))) // result: (SRAW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { break } y := v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 31 { break } v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpRsh32x64_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x64 x y) // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SRAW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32x8 x y) // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SRD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64Ux16 x y) // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux32 x (Const64 [c])) // cond: uint32(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux32 x (MOVDconst [c])) // cond: uint32(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SRD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64Ux32 x y) // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux64 x (Const64 [c])) // cond: uint64(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh64Ux64 x (MOVDconst [c])) // cond: uint64(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SRD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64Ux64 x (AND y (MOVDconst [63]))) // result: (SRD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { break } v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (AND (MOVDconst [63]) y)) // result: (SRD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 63 { break } v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (ANDconst [63] y)) // result: (SRD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst || v_1.Type != typ.UInt || v_1.AuxInt != 63 { break } y := v_1.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (SUB (MOVDconst [64]) (ANDconst [63] y))) // result: (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.UInt || v_1_1.AuxInt != 63 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (SUB (MOVDconst [64]) (AND y (MOVDconst [63])))) // result: (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] y := v_1_1.Args[0] v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 63 { break } v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (SUB (MOVDconst [64]) (AND (MOVDconst [63]) y))) // result: (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { break } y := v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 63 { break } v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpRsh64Ux64_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux64 x y) // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SRD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64Ux8 x y) // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SRAD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64x16 x y) // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x32 x (Const64 [c])) // cond: uint32(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x32 x (MOVDconst [c])) // cond: uint32(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SRAD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64x32 x y) // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x64 x (Const64 [c])) // cond: uint64(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x64 x (Const64 [c])) // cond: uint64(c) >= 64 // result: (SRADconst x [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = 63 v.AddArg(x) return true } // match: (Rsh64x64 x (MOVDconst [c])) // cond: uint64(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SRAD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64x64 x (AND y (MOVDconst [63]))) // result: (SRAD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] y := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { break } v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64x64 x (AND (MOVDconst [63]) y)) // result: (SRAD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } y := v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 63 { break } v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64x64 x (ANDconst [63] y)) // result: (SRAD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst || v_1.Type != typ.UInt || v_1.AuxInt != 63 { break } y := v_1.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64x64 x (SUB (MOVDconst [64]) (ANDconst [63] y))) // result: (SRAD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.UInt || v_1_1.AuxInt != 63 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64x64 x (SUB (MOVDconst [64]) (AND y (MOVDconst [63])))) // result: (SRAD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] y := v_1_1.Args[0] v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 63 { break } v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64x64 x (SUB (MOVDconst [64]) (AND (MOVDconst [63]) y))) // result: (SRAD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { break } y := v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 63 { break } v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpRsh64x64_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x64 x y) // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SRAD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64x8 x y) // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh8Ux16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVBZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8Ux16 x y) // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8Ux32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux32 x (Const64 [c])) // cond: uint32(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux32 x (MOVDconst [c])) // cond: uint32(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVBZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8Ux32 x y) // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh8Ux64 x (MOVDconst [c])) // cond: uint64(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVBZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8Ux64 x y) // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8Ux8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVBZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8Ux8 x y) // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVBreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8x16 x y) // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x32 x (Const64 [c])) // cond: uint32(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x32 x (MOVDconst [c])) // cond: uint32(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVBreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8x32 x y) // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x64 x (Const64 [c])) // cond: uint64(c) >= 8 // result: (SRAWconst (SignExt8to32 x) [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x64 x (MOVDconst [c])) // cond: uint64(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVBreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8x64 x y) // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVBreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8x8 x y) // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpSignExt16to32_0(v *Value) bool { // match: (SignExt16to32 x) // result: (MOVHreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt16to64_0(v *Value) bool { // match: (SignExt16to64 x) // result: (MOVHreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt32to64_0(v *Value) bool { // match: (SignExt32to64 x) // result: (MOVWreg x) for { x := v.Args[0] v.reset(OpPPC64MOVWreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt8to16_0(v *Value) bool { // match: (SignExt8to16 x) // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt8to32_0(v *Value) bool { // match: (SignExt8to32 x) // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt8to64_0(v *Value) bool { // match: (SignExt8to64 x) // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSlicemask_0(v *Value) bool { b := v.Block // match: (Slicemask x) // result: (SRADconst (NEG x) [63]) for { t := v.Type x := v.Args[0] v.reset(OpPPC64SRADconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpPPC64NEG, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpSqrt_0(v *Value) bool { // match: (Sqrt x) // result: (FSQRT x) for { x := v.Args[0] v.reset(OpPPC64FSQRT) v.AddArg(x) return true } } func rewriteValuePPC64_OpStaticCall_0(v *Value) bool { // match: (StaticCall [argwid] {target} mem) // result: (CALLstatic [argwid] {target} mem) for { argwid := v.AuxInt target := v.Aux mem := v.Args[0] v.reset(OpPPC64CALLstatic) v.AuxInt = argwid v.Aux = target v.AddArg(mem) return true } } func rewriteValuePPC64_OpStore_0(v *Value) bool { // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) // result: (FMOVDstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpPPC64FMOVDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is32BitFloat(val.Type) // result: (FMOVDstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8 && is32BitFloat(val.Type)) { break } v.reset(OpPPC64FMOVDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) // result: (FMOVSstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpPPC64FMOVSstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && (is64BitInt(val.Type) || isPtr(val.Type)) // result: (MOVDstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8 && (is64BitInt(val.Type) || isPtr(val.Type))) { break } v.reset(OpPPC64MOVDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitInt(val.Type) // result: (MOVWstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 4 && is32BitInt(val.Type)) { break } v.reset(OpPPC64MOVWstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 2 // result: (MOVHstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 2) { break } v.reset(OpPPC64MOVHstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 1 // result: (MOVBstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 1) { break } v.reset(OpPPC64MOVBstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpSub16_0(v *Value) bool { // match: (Sub16 x y) // result: (SUB x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub32_0(v *Value) bool { // match: (Sub32 x y) // result: (SUB x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub32F_0(v *Value) bool { // match: (Sub32F x y) // result: (FSUBS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FSUBS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub64_0(v *Value) bool { // match: (Sub64 x y) // result: (SUB x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub64F_0(v *Value) bool { // match: (Sub64F x y) // result: (FSUB x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FSUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub8_0(v *Value) bool { // match: (Sub8 x y) // result: (SUB x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSubPtr_0(v *Value) bool { // match: (SubPtr x y) // result: (SUB x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpTrunc_0(v *Value) bool { // match: (Trunc x) // result: (FTRUNC x) for { x := v.Args[0] v.reset(OpPPC64FTRUNC) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc16to8_0(v *Value) bool { // match: (Trunc16to8 x) // cond: isSigned(t) // result: (MOVBreg x) for { t := v.Type x := v.Args[0] if !(isSigned(t)) { break } v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } // match: (Trunc16to8 x) // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc32to16_0(v *Value) bool { // match: (Trunc32to16 x) // cond: isSigned(t) // result: (MOVHreg x) for { t := v.Type x := v.Args[0] if !(isSigned(t)) { break } v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } // match: (Trunc32to16 x) // result: (MOVHZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc32to8_0(v *Value) bool { // match: (Trunc32to8 x) // cond: isSigned(t) // result: (MOVBreg x) for { t := v.Type x := v.Args[0] if !(isSigned(t)) { break } v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } // match: (Trunc32to8 x) // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc64to16_0(v *Value) bool { // match: (Trunc64to16 x) // cond: isSigned(t) // result: (MOVHreg x) for { t := v.Type x := v.Args[0] if !(isSigned(t)) { break } v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } // match: (Trunc64to16 x) // result: (MOVHZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc64to32_0(v *Value) bool { // match: (Trunc64to32 x) // cond: isSigned(t) // result: (MOVWreg x) for { t := v.Type x := v.Args[0] if !(isSigned(t)) { break } v.reset(OpPPC64MOVWreg) v.AddArg(x) return true } // match: (Trunc64to32 x) // result: (MOVWZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVWZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc64to8_0(v *Value) bool { // match: (Trunc64to8 x) // cond: isSigned(t) // result: (MOVBreg x) for { t := v.Type x := v.Args[0] if !(isSigned(t)) { break } v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } // match: (Trunc64to8 x) // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpWB_0(v *Value) bool { // match: (WB {fn} destptr srcptr mem) // result: (LoweredWB {fn} destptr srcptr mem) for { fn := v.Aux mem := v.Args[2] destptr := v.Args[0] srcptr := v.Args[1] v.reset(OpPPC64LoweredWB) v.Aux = fn v.AddArg(destptr) v.AddArg(srcptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpXor16_0(v *Value) bool { // match: (Xor16 x y) // result: (XOR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpXor32_0(v *Value) bool { // match: (Xor32 x y) // result: (XOR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpXor64_0(v *Value) bool { // match: (Xor64 x y) // result: (XOR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpXor8_0(v *Value) bool { // match: (Xor8 x y) // result: (XOR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpZero_0(v *Value) bool { b := v.Block // match: (Zero [0] _ mem) // result: mem for { if v.AuxInt != 0 { break } mem := v.Args[1] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstorezero destptr mem) for { if v.AuxInt != 1 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVBstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [2] destptr mem) // result: (MOVHstorezero destptr mem) for { if v.AuxInt != 2 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVHstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstorezero [2] destptr (MOVHstorezero destptr mem)) for { if v.AuxInt != 3 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVBstorezero) v.AuxInt = 2 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVHstorezero, types.TypeMem) v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [4] destptr mem) // result: (MOVWstorezero destptr mem) for { if v.AuxInt != 4 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVWstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [5] destptr mem) // result: (MOVBstorezero [4] destptr (MOVWstorezero destptr mem)) for { if v.AuxInt != 5 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVBstorezero) v.AuxInt = 4 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [6] destptr mem) // result: (MOVHstorezero [4] destptr (MOVWstorezero destptr mem)) for { if v.AuxInt != 6 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVHstorezero) v.AuxInt = 4 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [7] destptr mem) // result: (MOVBstorezero [6] destptr (MOVHstorezero [4] destptr (MOVWstorezero destptr mem))) for { if v.AuxInt != 7 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVBstorezero) v.AuxInt = 6 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVHstorezero, types.TypeMem) v0.AuxInt = 4 v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [8] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero destptr mem) for { if v.AuxInt != 8 { break } t := v.Aux mem := v.Args[1] destptr := v.Args[0] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [8] destptr mem) // result: (MOVWstorezero [4] destptr (MOVWstorezero [0] destptr mem)) for { if v.AuxInt != 8 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVWstorezero) v.AuxInt = 4 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpZero_10(v *Value) bool { b := v.Block // match: (Zero [12] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVWstorezero [8] destptr (MOVDstorezero [0] destptr mem)) for { if v.AuxInt != 12 { break } t := v.Aux mem := v.Args[1] destptr := v.Args[0] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = 8 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [16] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem)) for { if v.AuxInt != 16 { break } t := v.Aux mem := v.Args[1] destptr := v.Args[0] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = 8 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [24] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero [16] destptr (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem))) for { if v.AuxInt != 24 { break } t := v.Aux mem := v.Args[1] destptr := v.Args[0] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = 16 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 8 v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [32] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero [24] destptr (MOVDstorezero [16] destptr (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem)))) for { if v.AuxInt != 32 { break } t := v.Aux mem := v.Args[1] destptr := v.Args[0] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = 24 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 16 v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v1.AuxInt = 8 v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v2.AuxInt = 0 v2.AddArg(destptr) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [s] ptr mem) // result: (LoweredZero [s] ptr mem) for { s := v.AuxInt mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredZero) v.AuxInt = s v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpZeroExt16to32_0(v *Value) bool { // match: (ZeroExt16to32 x) // result: (MOVHZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt16to64_0(v *Value) bool { // match: (ZeroExt16to64 x) // result: (MOVHZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt32to64_0(v *Value) bool { // match: (ZeroExt32to64 x) // result: (MOVWZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVWZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt8to16_0(v *Value) bool { // match: (ZeroExt8to16 x) // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt8to32_0(v *Value) bool { // match: (ZeroExt8to32 x) // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt8to64_0(v *Value) bool { // match: (ZeroExt8to64 x) // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteBlockPPC64(b *Block) bool { switch b.Kind { case BlockPPC64EQ: // match: (EQ (CMPconst [0] (ANDconst [c] x)) yes no) // result: (EQ (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (EQ (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagLT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpPPC64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockPPC64EQ) b.AddControl(cmp) return true } // match: (EQ (CMPconst [0] (ANDconst [c] x)) yes no) // result: (EQ (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (EQ (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (EQ (ANDCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (EQ (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 // result: (EQ (ORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64OR { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (EQ (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 // result: (EQ (XORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64XOR { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } case BlockPPC64GE: // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagLT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagGT { b.Reset(BlockFirst) return true } // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpPPC64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockPPC64LE) b.AddControl(cmp) return true } // match: (GE (CMPconst [0] (ANDconst [c] x)) yes no) // result: (GE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64GE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (GE (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (GE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64GE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (GE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GE (ANDCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64GE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (GE (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 // result: (GE (ORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64OR { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64GE) v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (GE (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 // result: (GE (XORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64XOR { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64GE) v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } case BlockPPC64GT: // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagLT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagGT { b.Reset(BlockFirst) return true } // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpPPC64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockPPC64LT) b.AddControl(cmp) return true } // match: (GT (CMPconst [0] (ANDconst [c] x)) yes no) // result: (GT (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64GT) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (GT (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (GT (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64GT) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (GT (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GT (ANDCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64GT) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (GT (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 // result: (GT (ORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64OR { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64GT) v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (GT (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 // result: (GT (XORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64XOR { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64GT) v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } case BlockIf: // match: (If (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpPPC64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64EQ) b.AddControl(cc) return true } // match: (If (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpPPC64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64NE) b.AddControl(cc) return true } // match: (If (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpPPC64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64LT) b.AddControl(cc) return true } // match: (If (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpPPC64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64LE) b.AddControl(cc) return true } // match: (If (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpPPC64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64GT) b.AddControl(cc) return true } // match: (If (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpPPC64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64GE) b.AddControl(cc) return true } // match: (If (FLessThan cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpPPC64FLessThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64FLT) b.AddControl(cc) return true } // match: (If (FLessEqual cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpPPC64FLessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64FLE) b.AddControl(cc) return true } // match: (If (FGreaterThan cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpPPC64FGreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64FGT) b.AddControl(cc) return true } // match: (If (FGreaterEqual cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpPPC64FGreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64FGE) b.AddControl(cc) return true } // match: (If cond yes no) // result: (NE (CMPWconst [0] cond) yes no) for { cond := b.Controls[0] b.Reset(BlockPPC64NE) v0 := b.NewValue0(cond.Pos, OpPPC64CMPWconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(cond) b.AddControl(v0) return true } case BlockPPC64LE: // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagLT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpPPC64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockPPC64GE) b.AddControl(cmp) return true } // match: (LE (CMPconst [0] (ANDconst [c] x)) yes no) // result: (LE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64LE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (LE (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (LE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64LE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (LE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LE (ANDCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64LE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (LE (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 // result: (LE (ORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64OR { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64LE) v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (LE (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 // result: (LE (XORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64XOR { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64LE) v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } case BlockPPC64LT: // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagLT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpPPC64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockPPC64GT) b.AddControl(cmp) return true } // match: (LT (CMPconst [0] (ANDconst [c] x)) yes no) // result: (LT (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64LT) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (LT (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (LT (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64LT) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (LT (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LT (ANDCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64LT) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (LT (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 // result: (LT (ORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64OR { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64LT) v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (LT (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 // result: (LT (XORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64XOR { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64LT) v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } case BlockPPC64NE: // match: (NE (CMPWconst [0] (Equal cc)) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64Equal { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64EQ) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (NotEqual cc)) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64NotEqual { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64NE) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (LessThan cc)) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64LessThan { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64LT) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (LessEqual cc)) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64LessEqual { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64LE) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (GreaterThan cc)) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64GreaterThan { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64GT) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (GreaterEqual cc)) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64GreaterEqual { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64GE) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (FLessThan cc)) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64FLessThan { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64FLT) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (FLessEqual cc)) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64FLessEqual { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64FLE) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (FGreaterThan cc)) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64FGreaterThan { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64FGT) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (FGreaterEqual cc)) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64FGreaterEqual { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64FGE) b.AddControl(cc) return true } // match: (NE (CMPconst [0] (ANDconst [c] x)) yes no) // result: (NE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (NE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagLT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagGT { b.Reset(BlockFirst) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpPPC64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockPPC64NE) b.AddControl(cmp) return true } // match: (NE (CMPconst [0] (ANDconst [c] x)) yes no) // result: (NE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (NE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (NE (ANDCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (NE (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 // result: (NE (ORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64OR { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } // match: (NE (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 // result: (NE (XORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64XOR { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } } return false } -- y -- // Code generated from gen/PPC64.rules; DO NOT EDIT. // generated with: cd gen; go run *.go package ssa import "math" import "cmd/internal/objabi" import "cmd/compile/internal/types" func rewriteValuePPC64(v *Value) bool { switch v.Op { case OpAbs: return rewriteValuePPC64_OpAbs_0(v) case OpAdd16: return rewriteValuePPC64_OpAdd16_0(v) case OpAdd32: return rewriteValuePPC64_OpAdd32_0(v) case OpAdd32F: return rewriteValuePPC64_OpAdd32F_0(v) case OpAdd64: return rewriteValuePPC64_OpAdd64_0(v) case OpAdd64F: return rewriteValuePPC64_OpAdd64F_0(v) case OpAdd64carry: return rewriteValuePPC64_OpAdd64carry_0(v) case OpAdd8: return rewriteValuePPC64_OpAdd8_0(v) case OpAddPtr: return rewriteValuePPC64_OpAddPtr_0(v) case OpAddr: return rewriteValuePPC64_OpAddr_0(v) case OpAnd16: return rewriteValuePPC64_OpAnd16_0(v) case OpAnd32: return rewriteValuePPC64_OpAnd32_0(v) case OpAnd64: return rewriteValuePPC64_OpAnd64_0(v) case OpAnd8: return rewriteValuePPC64_OpAnd8_0(v) case OpAndB: return rewriteValuePPC64_OpAndB_0(v) case OpAtomicAdd32: return rewriteValuePPC64_OpAtomicAdd32_0(v) case OpAtomicAdd64: return rewriteValuePPC64_OpAtomicAdd64_0(v) case OpAtomicAnd8: return rewriteValuePPC64_OpAtomicAnd8_0(v) case OpAtomicCompareAndSwap32: return rewriteValuePPC64_OpAtomicCompareAndSwap32_0(v) case OpAtomicCompareAndSwap64: return rewriteValuePPC64_OpAtomicCompareAndSwap64_0(v) case OpAtomicCompareAndSwapRel32: return rewriteValuePPC64_OpAtomicCompareAndSwapRel32_0(v) case OpAtomicExchange32: return rewriteValuePPC64_OpAtomicExchange32_0(v) case OpAtomicExchange64: return rewriteValuePPC64_OpAtomicExchange64_0(v) case OpAtomicLoad32: return rewriteValuePPC64_OpAtomicLoad32_0(v) case OpAtomicLoad64: return rewriteValuePPC64_OpAtomicLoad64_0(v) case OpAtomicLoad8: return rewriteValuePPC64_OpAtomicLoad8_0(v) case OpAtomicLoadAcq32: return rewriteValuePPC64_OpAtomicLoadAcq32_0(v) case OpAtomicLoadPtr: return rewriteValuePPC64_OpAtomicLoadPtr_0(v) case OpAtomicOr8: return rewriteValuePPC64_OpAtomicOr8_0(v) case OpAtomicStore32: return rewriteValuePPC64_OpAtomicStore32_0(v) case OpAtomicStore64: return rewriteValuePPC64_OpAtomicStore64_0(v) case OpAtomicStore8: return rewriteValuePPC64_OpAtomicStore8_0(v) case OpAtomicStoreRel32: return rewriteValuePPC64_OpAtomicStoreRel32_0(v) case OpAvg64u: return rewriteValuePPC64_OpAvg64u_0(v) case OpBitLen32: return rewriteValuePPC64_OpBitLen32_0(v) case OpBitLen64: return rewriteValuePPC64_OpBitLen64_0(v) case OpCeil: return rewriteValuePPC64_OpCeil_0(v) case OpClosureCall: return rewriteValuePPC64_OpClosureCall_0(v) case OpCom16: return rewriteValuePPC64_OpCom16_0(v) case OpCom32: return rewriteValuePPC64_OpCom32_0(v) case OpCom64: return rewriteValuePPC64_OpCom64_0(v) case OpCom8: return rewriteValuePPC64_OpCom8_0(v) case OpCondSelect: return rewriteValuePPC64_OpCondSelect_0(v) case OpConst16: return rewriteValuePPC64_OpConst16_0(v) case OpConst32: return rewriteValuePPC64_OpConst32_0(v) case OpConst32F: return rewriteValuePPC64_OpConst32F_0(v) case OpConst64: return rewriteValuePPC64_OpConst64_0(v) case OpConst64F: return rewriteValuePPC64_OpConst64F_0(v) case OpConst8: return rewriteValuePPC64_OpConst8_0(v) case OpConstBool: return rewriteValuePPC64_OpConstBool_0(v) case OpConstNil: return rewriteValuePPC64_OpConstNil_0(v) case OpCopysign: return rewriteValuePPC64_OpCopysign_0(v) case OpCtz16: return rewriteValuePPC64_OpCtz16_0(v) case OpCtz32: return rewriteValuePPC64_OpCtz32_0(v) case OpCtz32NonZero: return rewriteValuePPC64_OpCtz32NonZero_0(v) case OpCtz64: return rewriteValuePPC64_OpCtz64_0(v) case OpCtz64NonZero: return rewriteValuePPC64_OpCtz64NonZero_0(v) case OpCtz8: return rewriteValuePPC64_OpCtz8_0(v) case OpCvt32Fto32: return rewriteValuePPC64_OpCvt32Fto32_0(v) case OpCvt32Fto64: return rewriteValuePPC64_OpCvt32Fto64_0(v) case OpCvt32Fto64F: return rewriteValuePPC64_OpCvt32Fto64F_0(v) case OpCvt32to32F: return rewriteValuePPC64_OpCvt32to32F_0(v) case OpCvt32to64F: return rewriteValuePPC64_OpCvt32to64F_0(v) case OpCvt64Fto32: return rewriteValuePPC64_OpCvt64Fto32_0(v) case OpCvt64Fto32F: return rewriteValuePPC64_OpCvt64Fto32F_0(v) case OpCvt64Fto64: return rewriteValuePPC64_OpCvt64Fto64_0(v) case OpCvt64to32F: return rewriteValuePPC64_OpCvt64to32F_0(v) case OpCvt64to64F: return rewriteValuePPC64_OpCvt64to64F_0(v) case OpDiv16: return rewriteValuePPC64_OpDiv16_0(v) case OpDiv16u: return rewriteValuePPC64_OpDiv16u_0(v) case OpDiv32: return rewriteValuePPC64_OpDiv32_0(v) case OpDiv32F: return rewriteValuePPC64_OpDiv32F_0(v) case OpDiv32u: return rewriteValuePPC64_OpDiv32u_0(v) case OpDiv64: return rewriteValuePPC64_OpDiv64_0(v) case OpDiv64F: return rewriteValuePPC64_OpDiv64F_0(v) case OpDiv64u: return rewriteValuePPC64_OpDiv64u_0(v) case OpDiv8: return rewriteValuePPC64_OpDiv8_0(v) case OpDiv8u: return rewriteValuePPC64_OpDiv8u_0(v) case OpEq16: return rewriteValuePPC64_OpEq16_0(v) case OpEq32: return rewriteValuePPC64_OpEq32_0(v) case OpEq32F: return rewriteValuePPC64_OpEq32F_0(v) case OpEq64: return rewriteValuePPC64_OpEq64_0(v) case OpEq64F: return rewriteValuePPC64_OpEq64F_0(v) case OpEq8: return rewriteValuePPC64_OpEq8_0(v) case OpEqB: return rewriteValuePPC64_OpEqB_0(v) case OpEqPtr: return rewriteValuePPC64_OpEqPtr_0(v) case OpFMA: return rewriteValuePPC64_OpFMA_0(v) case OpFloor: return rewriteValuePPC64_OpFloor_0(v) case OpGeq16: return rewriteValuePPC64_OpGeq16_0(v) case OpGeq16U: return rewriteValuePPC64_OpGeq16U_0(v) case OpGeq32: return rewriteValuePPC64_OpGeq32_0(v) case OpGeq32F: return rewriteValuePPC64_OpGeq32F_0(v) case OpGeq32U: return rewriteValuePPC64_OpGeq32U_0(v) case OpGeq64: return rewriteValuePPC64_OpGeq64_0(v) case OpGeq64F: return rewriteValuePPC64_OpGeq64F_0(v) case OpGeq64U: return rewriteValuePPC64_OpGeq64U_0(v) case OpGeq8: return rewriteValuePPC64_OpGeq8_0(v) case OpGeq8U: return rewriteValuePPC64_OpGeq8U_0(v) case OpGetCallerPC: return rewriteValuePPC64_OpGetCallerPC_0(v) case OpGetCallerSP: return rewriteValuePPC64_OpGetCallerSP_0(v) case OpGetClosurePtr: return rewriteValuePPC64_OpGetClosurePtr_0(v) case OpGreater16: return rewriteValuePPC64_OpGreater16_0(v) case OpGreater16U: return rewriteValuePPC64_OpGreater16U_0(v) case OpGreater32: return rewriteValuePPC64_OpGreater32_0(v) case OpGreater32F: return rewriteValuePPC64_OpGreater32F_0(v) case OpGreater32U: return rewriteValuePPC64_OpGreater32U_0(v) case OpGreater64: return rewriteValuePPC64_OpGreater64_0(v) case OpGreater64F: return rewriteValuePPC64_OpGreater64F_0(v) case OpGreater64U: return rewriteValuePPC64_OpGreater64U_0(v) case OpGreater8: return rewriteValuePPC64_OpGreater8_0(v) case OpGreater8U: return rewriteValuePPC64_OpGreater8U_0(v) case OpHmul32: return rewriteValuePPC64_OpHmul32_0(v) case OpHmul32u: return rewriteValuePPC64_OpHmul32u_0(v) case OpHmul64: return rewriteValuePPC64_OpHmul64_0(v) case OpHmul64u: return rewriteValuePPC64_OpHmul64u_0(v) case OpInterCall: return rewriteValuePPC64_OpInterCall_0(v) case OpIsInBounds: return rewriteValuePPC64_OpIsInBounds_0(v) case OpIsNonNil: return rewriteValuePPC64_OpIsNonNil_0(v) case OpIsSliceInBounds: return rewriteValuePPC64_OpIsSliceInBounds_0(v) case OpLeq16: return rewriteValuePPC64_OpLeq16_0(v) case OpLeq16U: return rewriteValuePPC64_OpLeq16U_0(v) case OpLeq32: return rewriteValuePPC64_OpLeq32_0(v) case OpLeq32F: return rewriteValuePPC64_OpLeq32F_0(v) case OpLeq32U: return rewriteValuePPC64_OpLeq32U_0(v) case OpLeq64: return rewriteValuePPC64_OpLeq64_0(v) case OpLeq64F: return rewriteValuePPC64_OpLeq64F_0(v) case OpLeq64U: return rewriteValuePPC64_OpLeq64U_0(v) case OpLeq8: return rewriteValuePPC64_OpLeq8_0(v) case OpLeq8U: return rewriteValuePPC64_OpLeq8U_0(v) case OpLess16: return rewriteValuePPC64_OpLess16_0(v) case OpLess16U: return rewriteValuePPC64_OpLess16U_0(v) case OpLess32: return rewriteValuePPC64_OpLess32_0(v) case OpLess32F: return rewriteValuePPC64_OpLess32F_0(v) case OpLess32U: return rewriteValuePPC64_OpLess32U_0(v) case OpLess64: return rewriteValuePPC64_OpLess64_0(v) case OpLess64F: return rewriteValuePPC64_OpLess64F_0(v) case OpLess64U: return rewriteValuePPC64_OpLess64U_0(v) case OpLess8: return rewriteValuePPC64_OpLess8_0(v) case OpLess8U: return rewriteValuePPC64_OpLess8U_0(v) case OpLoad: return rewriteValuePPC64_OpLoad_0(v) case OpLocalAddr: return rewriteValuePPC64_OpLocalAddr_0(v) case OpLsh16x16: return rewriteValuePPC64_OpLsh16x16_0(v) case OpLsh16x32: return rewriteValuePPC64_OpLsh16x32_0(v) case OpLsh16x64: return rewriteValuePPC64_OpLsh16x64_0(v) case OpLsh16x8: return rewriteValuePPC64_OpLsh16x8_0(v) case OpLsh32x16: return rewriteValuePPC64_OpLsh32x16_0(v) case OpLsh32x32: return rewriteValuePPC64_OpLsh32x32_0(v) case OpLsh32x64: return rewriteValuePPC64_OpLsh32x64_0(v) case OpLsh32x8: return rewriteValuePPC64_OpLsh32x8_0(v) case OpLsh64x16: return rewriteValuePPC64_OpLsh64x16_0(v) case OpLsh64x32: return rewriteValuePPC64_OpLsh64x32_0(v) case OpLsh64x64: return rewriteValuePPC64_OpLsh64x64_0(v) case OpLsh64x8: return rewriteValuePPC64_OpLsh64x8_0(v) case OpLsh8x16: return rewriteValuePPC64_OpLsh8x16_0(v) case OpLsh8x32: return rewriteValuePPC64_OpLsh8x32_0(v) case OpLsh8x64: return rewriteValuePPC64_OpLsh8x64_0(v) case OpLsh8x8: return rewriteValuePPC64_OpLsh8x8_0(v) case OpMod16: return rewriteValuePPC64_OpMod16_0(v) case OpMod16u: return rewriteValuePPC64_OpMod16u_0(v) case OpMod32: return rewriteValuePPC64_OpMod32_0(v) case OpMod32u: return rewriteValuePPC64_OpMod32u_0(v) case OpMod64: return rewriteValuePPC64_OpMod64_0(v) case OpMod64u: return rewriteValuePPC64_OpMod64u_0(v) case OpMod8: return rewriteValuePPC64_OpMod8_0(v) case OpMod8u: return rewriteValuePPC64_OpMod8u_0(v) case OpMove: return rewriteValuePPC64_OpMove_0(v) || rewriteValuePPC64_OpMove_10(v) case OpMul16: return rewriteValuePPC64_OpMul16_0(v) case OpMul32: return rewriteValuePPC64_OpMul32_0(v) case OpMul32F: return rewriteValuePPC64_OpMul32F_0(v) case OpMul64: return rewriteValuePPC64_OpMul64_0(v) case OpMul64F: return rewriteValuePPC64_OpMul64F_0(v) case OpMul64uhilo: return rewriteValuePPC64_OpMul64uhilo_0(v) case OpMul8: return rewriteValuePPC64_OpMul8_0(v) case OpNeg16: return rewriteValuePPC64_OpNeg16_0(v) case OpNeg32: return rewriteValuePPC64_OpNeg32_0(v) case OpNeg32F: return rewriteValuePPC64_OpNeg32F_0(v) case OpNeg64: return rewriteValuePPC64_OpNeg64_0(v) case OpNeg64F: return rewriteValuePPC64_OpNeg64F_0(v) case OpNeg8: return rewriteValuePPC64_OpNeg8_0(v) case OpNeq16: return rewriteValuePPC64_OpNeq16_0(v) case OpNeq32: return rewriteValuePPC64_OpNeq32_0(v) case OpNeq32F: return rewriteValuePPC64_OpNeq32F_0(v) case OpNeq64: return rewriteValuePPC64_OpNeq64_0(v) case OpNeq64F: return rewriteValuePPC64_OpNeq64F_0(v) case OpNeq8: return rewriteValuePPC64_OpNeq8_0(v) case OpNeqB: return rewriteValuePPC64_OpNeqB_0(v) case OpNeqPtr: return rewriteValuePPC64_OpNeqPtr_0(v) case OpNilCheck: return rewriteValuePPC64_OpNilCheck_0(v) case OpNot: return rewriteValuePPC64_OpNot_0(v) case OpOffPtr: return rewriteValuePPC64_OpOffPtr_0(v) case OpOr16: return rewriteValuePPC64_OpOr16_0(v) case OpOr32: return rewriteValuePPC64_OpOr32_0(v) case OpOr64: return rewriteValuePPC64_OpOr64_0(v) case OpOr8: return rewriteValuePPC64_OpOr8_0(v) case OpOrB: return rewriteValuePPC64_OpOrB_0(v) case OpPPC64ADD: return rewriteValuePPC64_OpPPC64ADD_0(v) case OpPPC64ADDconst: return rewriteValuePPC64_OpPPC64ADDconst_0(v) case OpPPC64AND: return rewriteValuePPC64_OpPPC64AND_0(v) case OpPPC64ANDconst: return rewriteValuePPC64_OpPPC64ANDconst_0(v) || rewriteValuePPC64_OpPPC64ANDconst_10(v) case OpPPC64CMP: return rewriteValuePPC64_OpPPC64CMP_0(v) case OpPPC64CMPU: return rewriteValuePPC64_OpPPC64CMPU_0(v) case OpPPC64CMPUconst: return rewriteValuePPC64_OpPPC64CMPUconst_0(v) case OpPPC64CMPW: return rewriteValuePPC64_OpPPC64CMPW_0(v) case OpPPC64CMPWU: return rewriteValuePPC64_OpPPC64CMPWU_0(v) case OpPPC64CMPWUconst: return rewriteValuePPC64_OpPPC64CMPWUconst_0(v) case OpPPC64CMPWconst: return rewriteValuePPC64_OpPPC64CMPWconst_0(v) case OpPPC64CMPconst: return rewriteValuePPC64_OpPPC64CMPconst_0(v) case OpPPC64Equal: return rewriteValuePPC64_OpPPC64Equal_0(v) case OpPPC64FABS: return rewriteValuePPC64_OpPPC64FABS_0(v) case OpPPC64FADD: return rewriteValuePPC64_OpPPC64FADD_0(v) case OpPPC64FADDS: return rewriteValuePPC64_OpPPC64FADDS_0(v) case OpPPC64FCEIL: return rewriteValuePPC64_OpPPC64FCEIL_0(v) case OpPPC64FFLOOR: return rewriteValuePPC64_OpPPC64FFLOOR_0(v) case OpPPC64FGreaterEqual: return rewriteValuePPC64_OpPPC64FGreaterEqual_0(v) case OpPPC64FGreaterThan: return rewriteValuePPC64_OpPPC64FGreaterThan_0(v) case OpPPC64FLessEqual: return rewriteValuePPC64_OpPPC64FLessEqual_0(v) case OpPPC64FLessThan: return rewriteValuePPC64_OpPPC64FLessThan_0(v) case OpPPC64FMOVDload: return rewriteValuePPC64_OpPPC64FMOVDload_0(v) case OpPPC64FMOVDstore: return rewriteValuePPC64_OpPPC64FMOVDstore_0(v) case OpPPC64FMOVSload: return rewriteValuePPC64_OpPPC64FMOVSload_0(v) case OpPPC64FMOVSstore: return rewriteValuePPC64_OpPPC64FMOVSstore_0(v) case OpPPC64FNEG: return rewriteValuePPC64_OpPPC64FNEG_0(v) case OpPPC64FSQRT: return rewriteValuePPC64_OpPPC64FSQRT_0(v) case OpPPC64FSUB: return rewriteValuePPC64_OpPPC64FSUB_0(v) case OpPPC64FSUBS: return rewriteValuePPC64_OpPPC64FSUBS_0(v) case OpPPC64FTRUNC: return rewriteValuePPC64_OpPPC64FTRUNC_0(v) case OpPPC64GreaterEqual: return rewriteValuePPC64_OpPPC64GreaterEqual_0(v) case OpPPC64GreaterThan: return rewriteValuePPC64_OpPPC64GreaterThan_0(v) case OpPPC64ISEL: return rewriteValuePPC64_OpPPC64ISEL_0(v) || rewriteValuePPC64_OpPPC64ISEL_10(v) || rewriteValuePPC64_OpPPC64ISEL_20(v) case OpPPC64ISELB: return rewriteValuePPC64_OpPPC64ISELB_0(v) || rewriteValuePPC64_OpPPC64ISELB_10(v) || rewriteValuePPC64_OpPPC64ISELB_20(v) case OpPPC64LessEqual: return rewriteValuePPC64_OpPPC64LessEqual_0(v) case OpPPC64LessThan: return rewriteValuePPC64_OpPPC64LessThan_0(v) case OpPPC64MFVSRD: return rewriteValuePPC64_OpPPC64MFVSRD_0(v) case OpPPC64MOVBZload: return rewriteValuePPC64_OpPPC64MOVBZload_0(v) case OpPPC64MOVBZloadidx: return rewriteValuePPC64_OpPPC64MOVBZloadidx_0(v) case OpPPC64MOVBZreg: return rewriteValuePPC64_OpPPC64MOVBZreg_0(v) || rewriteValuePPC64_OpPPC64MOVBZreg_10(v) case OpPPC64MOVBreg: return rewriteValuePPC64_OpPPC64MOVBreg_0(v) || rewriteValuePPC64_OpPPC64MOVBreg_10(v) case OpPPC64MOVBstore: return rewriteValuePPC64_OpPPC64MOVBstore_0(v) || rewriteValuePPC64_OpPPC64MOVBstore_10(v) || rewriteValuePPC64_OpPPC64MOVBstore_20(v) case OpPPC64MOVBstoreidx: return rewriteValuePPC64_OpPPC64MOVBstoreidx_0(v) || rewriteValuePPC64_OpPPC64MOVBstoreidx_10(v) case OpPPC64MOVBstorezero: return rewriteValuePPC64_OpPPC64MOVBstorezero_0(v) case OpPPC64MOVDload: return rewriteValuePPC64_OpPPC64MOVDload_0(v) case OpPPC64MOVDloadidx: return rewriteValuePPC64_OpPPC64MOVDloadidx_0(v) case OpPPC64MOVDstore: return rewriteValuePPC64_OpPPC64MOVDstore_0(v) case OpPPC64MOVDstoreidx: return rewriteValuePPC64_OpPPC64MOVDstoreidx_0(v) case OpPPC64MOVDstorezero: return rewriteValuePPC64_OpPPC64MOVDstorezero_0(v) case OpPPC64MOVHBRstore: return rewriteValuePPC64_OpPPC64MOVHBRstore_0(v) case OpPPC64MOVHZload: return rewriteValuePPC64_OpPPC64MOVHZload_0(v) case OpPPC64MOVHZloadidx: return rewriteValuePPC64_OpPPC64MOVHZloadidx_0(v) case OpPPC64MOVHZreg: return rewriteValuePPC64_OpPPC64MOVHZreg_0(v) || rewriteValuePPC64_OpPPC64MOVHZreg_10(v) case OpPPC64MOVHload: return rewriteValuePPC64_OpPPC64MOVHload_0(v) case OpPPC64MOVHloadidx: return rewriteValuePPC64_OpPPC64MOVHloadidx_0(v) case OpPPC64MOVHreg: return rewriteValuePPC64_OpPPC64MOVHreg_0(v) || rewriteValuePPC64_OpPPC64MOVHreg_10(v) case OpPPC64MOVHstore: return rewriteValuePPC64_OpPPC64MOVHstore_0(v) case OpPPC64MOVHstoreidx: return rewriteValuePPC64_OpPPC64MOVHstoreidx_0(v) case OpPPC64MOVHstorezero: return rewriteValuePPC64_OpPPC64MOVHstorezero_0(v) case OpPPC64MOVWBRstore: return rewriteValuePPC64_OpPPC64MOVWBRstore_0(v) case OpPPC64MOVWZload: return rewriteValuePPC64_OpPPC64MOVWZload_0(v) case OpPPC64MOVWZloadidx: return rewriteValuePPC64_OpPPC64MOVWZloadidx_0(v) case OpPPC64MOVWZreg: return rewriteValuePPC64_OpPPC64MOVWZreg_0(v) || rewriteValuePPC64_OpPPC64MOVWZreg_10(v) || rewriteValuePPC64_OpPPC64MOVWZreg_20(v) case OpPPC64MOVWload: return rewriteValuePPC64_OpPPC64MOVWload_0(v) case OpPPC64MOVWloadidx: return rewriteValuePPC64_OpPPC64MOVWloadidx_0(v) case OpPPC64MOVWreg: return rewriteValuePPC64_OpPPC64MOVWreg_0(v) || rewriteValuePPC64_OpPPC64MOVWreg_10(v) case OpPPC64MOVWstore: return rewriteValuePPC64_OpPPC64MOVWstore_0(v) case OpPPC64MOVWstoreidx: return rewriteValuePPC64_OpPPC64MOVWstoreidx_0(v) case OpPPC64MOVWstorezero: return rewriteValuePPC64_OpPPC64MOVWstorezero_0(v) case OpPPC64MTVSRD: return rewriteValuePPC64_OpPPC64MTVSRD_0(v) case OpPPC64MaskIfNotCarry: return rewriteValuePPC64_OpPPC64MaskIfNotCarry_0(v) case OpPPC64NotEqual: return rewriteValuePPC64_OpPPC64NotEqual_0(v) case OpPPC64OR: return rewriteValuePPC64_OpPPC64OR_0(v) || rewriteValuePPC64_OpPPC64OR_10(v) || rewriteValuePPC64_OpPPC64OR_20(v) case OpPPC64ORN: return rewriteValuePPC64_OpPPC64ORN_0(v) case OpPPC64ORconst: return rewriteValuePPC64_OpPPC64ORconst_0(v) case OpPPC64ROTL: return rewriteValuePPC64_OpPPC64ROTL_0(v) case OpPPC64ROTLW: return rewriteValuePPC64_OpPPC64ROTLW_0(v) case OpPPC64SUB: return rewriteValuePPC64_OpPPC64SUB_0(v) case OpPPC64XOR: return rewriteValuePPC64_OpPPC64XOR_0(v) case OpPPC64XORconst: return rewriteValuePPC64_OpPPC64XORconst_0(v) case OpPanicBounds: return rewriteValuePPC64_OpPanicBounds_0(v) case OpPopCount16: return rewriteValuePPC64_OpPopCount16_0(v) case OpPopCount32: return rewriteValuePPC64_OpPopCount32_0(v) case OpPopCount64: return rewriteValuePPC64_OpPopCount64_0(v) case OpPopCount8: return rewriteValuePPC64_OpPopCount8_0(v) case OpRotateLeft16: return rewriteValuePPC64_OpRotateLeft16_0(v) case OpRotateLeft32: return rewriteValuePPC64_OpRotateLeft32_0(v) case OpRotateLeft64: return rewriteValuePPC64_OpRotateLeft64_0(v) case OpRotateLeft8: return rewriteValuePPC64_OpRotateLeft8_0(v) case OpRound: return rewriteValuePPC64_OpRound_0(v) case OpRound32F: return rewriteValuePPC64_OpRound32F_0(v) case OpRound64F: return rewriteValuePPC64_OpRound64F_0(v) case OpRsh16Ux16: return rewriteValuePPC64_OpRsh16Ux16_0(v) case OpRsh16Ux32: return rewriteValuePPC64_OpRsh16Ux32_0(v) case OpRsh16Ux64: return rewriteValuePPC64_OpRsh16Ux64_0(v) case OpRsh16Ux8: return rewriteValuePPC64_OpRsh16Ux8_0(v) case OpRsh16x16: return rewriteValuePPC64_OpRsh16x16_0(v) case OpRsh16x32: return rewriteValuePPC64_OpRsh16x32_0(v) case OpRsh16x64: return rewriteValuePPC64_OpRsh16x64_0(v) case OpRsh16x8: return rewriteValuePPC64_OpRsh16x8_0(v) case OpRsh32Ux16: return rewriteValuePPC64_OpRsh32Ux16_0(v) case OpRsh32Ux32: return rewriteValuePPC64_OpRsh32Ux32_0(v) case OpRsh32Ux64: return rewriteValuePPC64_OpRsh32Ux64_0(v) case OpRsh32Ux8: return rewriteValuePPC64_OpRsh32Ux8_0(v) case OpRsh32x16: return rewriteValuePPC64_OpRsh32x16_0(v) case OpRsh32x32: return rewriteValuePPC64_OpRsh32x32_0(v) case OpRsh32x64: return rewriteValuePPC64_OpRsh32x64_0(v) case OpRsh32x8: return rewriteValuePPC64_OpRsh32x8_0(v) case OpRsh64Ux16: return rewriteValuePPC64_OpRsh64Ux16_0(v) case OpRsh64Ux32: return rewriteValuePPC64_OpRsh64Ux32_0(v) case OpRsh64Ux64: return rewriteValuePPC64_OpRsh64Ux64_0(v) case OpRsh64Ux8: return rewriteValuePPC64_OpRsh64Ux8_0(v) case OpRsh64x16: return rewriteValuePPC64_OpRsh64x16_0(v) case OpRsh64x32: return rewriteValuePPC64_OpRsh64x32_0(v) case OpRsh64x64: return rewriteValuePPC64_OpRsh64x64_0(v) case OpRsh64x8: return rewriteValuePPC64_OpRsh64x8_0(v) case OpRsh8Ux16: return rewriteValuePPC64_OpRsh8Ux16_0(v) case OpRsh8Ux32: return rewriteValuePPC64_OpRsh8Ux32_0(v) case OpRsh8Ux64: return rewriteValuePPC64_OpRsh8Ux64_0(v) case OpRsh8Ux8: return rewriteValuePPC64_OpRsh8Ux8_0(v) case OpRsh8x16: return rewriteValuePPC64_OpRsh8x16_0(v) case OpRsh8x32: return rewriteValuePPC64_OpRsh8x32_0(v) case OpRsh8x64: return rewriteValuePPC64_OpRsh8x64_0(v) case OpRsh8x8: return rewriteValuePPC64_OpRsh8x8_0(v) case OpSignExt16to32: return rewriteValuePPC64_OpSignExt16to32_0(v) case OpSignExt16to64: return rewriteValuePPC64_OpSignExt16to64_0(v) case OpSignExt32to64: return rewriteValuePPC64_OpSignExt32to64_0(v) case OpSignExt8to16: return rewriteValuePPC64_OpSignExt8to16_0(v) case OpSignExt8to32: return rewriteValuePPC64_OpSignExt8to32_0(v) case OpSignExt8to64: return rewriteValuePPC64_OpSignExt8to64_0(v) case OpSlicemask: return rewriteValuePPC64_OpSlicemask_0(v) case OpSqrt: return rewriteValuePPC64_OpSqrt_0(v) case OpStaticCall: return rewriteValuePPC64_OpStaticCall_0(v) case OpStore: return rewriteValuePPC64_OpStore_0(v) case OpSub16: return rewriteValuePPC64_OpSub16_0(v) case OpSub32: return rewriteValuePPC64_OpSub32_0(v) case OpSub32F: return rewriteValuePPC64_OpSub32F_0(v) case OpSub64: return rewriteValuePPC64_OpSub64_0(v) case OpSub64F: return rewriteValuePPC64_OpSub64F_0(v) case OpSub8: return rewriteValuePPC64_OpSub8_0(v) case OpSubPtr: return rewriteValuePPC64_OpSubPtr_0(v) case OpTrunc: return rewriteValuePPC64_OpTrunc_0(v) case OpTrunc16to8: return rewriteValuePPC64_OpTrunc16to8_0(v) case OpTrunc32to16: return rewriteValuePPC64_OpTrunc32to16_0(v) case OpTrunc32to8: return rewriteValuePPC64_OpTrunc32to8_0(v) case OpTrunc64to16: return rewriteValuePPC64_OpTrunc64to16_0(v) case OpTrunc64to32: return rewriteValuePPC64_OpTrunc64to32_0(v) case OpTrunc64to8: return rewriteValuePPC64_OpTrunc64to8_0(v) case OpWB: return rewriteValuePPC64_OpWB_0(v) case OpXor16: return rewriteValuePPC64_OpXor16_0(v) case OpXor32: return rewriteValuePPC64_OpXor32_0(v) case OpXor64: return rewriteValuePPC64_OpXor64_0(v) case OpXor8: return rewriteValuePPC64_OpXor8_0(v) case OpZero: return rewriteValuePPC64_OpZero_0(v) || rewriteValuePPC64_OpZero_10(v) case OpZeroExt16to32: return rewriteValuePPC64_OpZeroExt16to32_0(v) case OpZeroExt16to64: return rewriteValuePPC64_OpZeroExt16to64_0(v) case OpZeroExt32to64: return rewriteValuePPC64_OpZeroExt32to64_0(v) case OpZeroExt8to16: return rewriteValuePPC64_OpZeroExt8to16_0(v) case OpZeroExt8to32: return rewriteValuePPC64_OpZeroExt8to32_0(v) case OpZeroExt8to64: return rewriteValuePPC64_OpZeroExt8to64_0(v) } return false } func rewriteValuePPC64_OpAbs_0(v *Value) bool { // match: (Abs x) // result: (FABS x) for { x := v.Args[0] v.reset(OpPPC64FABS) v.AddArg(x) return true } } func rewriteValuePPC64_OpAdd16_0(v *Value) bool { // match: (Add16 x y) // result: (ADD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd32_0(v *Value) bool { // match: (Add32 x y) // result: (ADD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd32F_0(v *Value) bool { // match: (Add32F x y) // result: (FADDS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FADDS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd64_0(v *Value) bool { // match: (Add64 x y) // result: (ADD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd64F_0(v *Value) bool { // match: (Add64F x y) // result: (FADD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAdd64carry_0(v *Value) bool { // match: (Add64carry x y c) // result: (LoweredAdd64Carry x y c) for { c := v.Args[2] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64LoweredAdd64Carry) v.AddArg(x) v.AddArg(y) v.AddArg(c) return true } } func rewriteValuePPC64_OpAdd8_0(v *Value) bool { // match: (Add8 x y) // result: (ADD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAddPtr_0(v *Value) bool { // match: (AddPtr x y) // result: (ADD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ADD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAddr_0(v *Value) bool { // match: (Addr {sym} base) // result: (MOVDaddr {sym} base) for { sym := v.Aux base := v.Args[0] v.reset(OpPPC64MOVDaddr) v.Aux = sym v.AddArg(base) return true } } func rewriteValuePPC64_OpAnd16_0(v *Value) bool { // match: (And16 x y) // result: (AND x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAnd32_0(v *Value) bool { // match: (And32 x y) // result: (AND x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAnd64_0(v *Value) bool { // match: (And64 x y) // result: (AND x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAnd8_0(v *Value) bool { // match: (And8 x y) // result: (AND x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAndB_0(v *Value) bool { // match: (AndB x y) // result: (AND x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64AND) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpAtomicAdd32_0(v *Value) bool { // match: (AtomicAdd32 ptr val mem) // result: (LoweredAtomicAdd32 ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicAdd32) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicAdd64_0(v *Value) bool { // match: (AtomicAdd64 ptr val mem) // result: (LoweredAtomicAdd64 ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicAdd64) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicAnd8_0(v *Value) bool { // match: (AtomicAnd8 ptr val mem) // result: (LoweredAtomicAnd8 ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicAnd8) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicCompareAndSwap32_0(v *Value) bool { // match: (AtomicCompareAndSwap32 ptr old new_ mem) // result: (LoweredAtomicCas32 [1] ptr old new_ mem) for { mem := v.Args[3] ptr := v.Args[0] old := v.Args[1] new_ := v.Args[2] v.reset(OpPPC64LoweredAtomicCas32) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicCompareAndSwap64_0(v *Value) bool { // match: (AtomicCompareAndSwap64 ptr old new_ mem) // result: (LoweredAtomicCas64 [1] ptr old new_ mem) for { mem := v.Args[3] ptr := v.Args[0] old := v.Args[1] new_ := v.Args[2] v.reset(OpPPC64LoweredAtomicCas64) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicCompareAndSwapRel32_0(v *Value) bool { // match: (AtomicCompareAndSwapRel32 ptr old new_ mem) // result: (LoweredAtomicCas32 [0] ptr old new_ mem) for { mem := v.Args[3] ptr := v.Args[0] old := v.Args[1] new_ := v.Args[2] v.reset(OpPPC64LoweredAtomicCas32) v.AuxInt = 0 v.AddArg(ptr) v.AddArg(old) v.AddArg(new_) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicExchange32_0(v *Value) bool { // match: (AtomicExchange32 ptr val mem) // result: (LoweredAtomicExchange32 ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicExchange32) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicExchange64_0(v *Value) bool { // match: (AtomicExchange64 ptr val mem) // result: (LoweredAtomicExchange64 ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicExchange64) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoad32_0(v *Value) bool { // match: (AtomicLoad32 ptr mem) // result: (LoweredAtomicLoad32 [1] ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredAtomicLoad32) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoad64_0(v *Value) bool { // match: (AtomicLoad64 ptr mem) // result: (LoweredAtomicLoad64 [1] ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredAtomicLoad64) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoad8_0(v *Value) bool { // match: (AtomicLoad8 ptr mem) // result: (LoweredAtomicLoad8 [1] ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredAtomicLoad8) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoadAcq32_0(v *Value) bool { // match: (AtomicLoadAcq32 ptr mem) // result: (LoweredAtomicLoad32 [0] ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredAtomicLoad32) v.AuxInt = 0 v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicLoadPtr_0(v *Value) bool { // match: (AtomicLoadPtr ptr mem) // result: (LoweredAtomicLoadPtr [1] ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredAtomicLoadPtr) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicOr8_0(v *Value) bool { // match: (AtomicOr8 ptr val mem) // result: (LoweredAtomicOr8 ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicOr8) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicStore32_0(v *Value) bool { // match: (AtomicStore32 ptr val mem) // result: (LoweredAtomicStore32 [1] ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicStore32) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicStore64_0(v *Value) bool { // match: (AtomicStore64 ptr val mem) // result: (LoweredAtomicStore64 [1] ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicStore64) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicStore8_0(v *Value) bool { // match: (AtomicStore8 ptr val mem) // result: (LoweredAtomicStore8 [1] ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicStore8) v.AuxInt = 1 v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAtomicStoreRel32_0(v *Value) bool { // match: (AtomicStoreRel32 ptr val mem) // result: (LoweredAtomicStore32 [0] ptr val mem) for { mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] v.reset(OpPPC64LoweredAtomicStore32) v.AuxInt = 0 v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } } func rewriteValuePPC64_OpAvg64u_0(v *Value) bool { b := v.Block // match: (Avg64u x y) // result: (ADD (SRDconst (SUB x y) [1]) y) for { t := v.Type y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ADD) v0 := b.NewValue0(v.Pos, OpPPC64SRDconst, t) v0.AuxInt = 1 v1 := b.NewValue0(v.Pos, OpPPC64SUB, t) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) v.AddArg(y) return true } } func rewriteValuePPC64_OpBitLen32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // result: (SUB (MOVDconst [32]) (CNTLZW x)) for { x := v.Args[0] v.reset(OpPPC64SUB) v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 32 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64CNTLZW, typ.Int) v1.AddArg(x) v.AddArg(v1) return true } } func rewriteValuePPC64_OpBitLen64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // result: (SUB (MOVDconst [64]) (CNTLZD x)) for { x := v.Args[0] v.reset(OpPPC64SUB) v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 64 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64CNTLZD, typ.Int) v1.AddArg(x) v.AddArg(v1) return true } } func rewriteValuePPC64_OpCeil_0(v *Value) bool { // match: (Ceil x) // result: (FCEIL x) for { x := v.Args[0] v.reset(OpPPC64FCEIL) v.AddArg(x) return true } } func rewriteValuePPC64_OpClosureCall_0(v *Value) bool { // match: (ClosureCall [argwid] entry closure mem) // result: (CALLclosure [argwid] entry closure mem) for { argwid := v.AuxInt mem := v.Args[2] entry := v.Args[0] closure := v.Args[1] v.reset(OpPPC64CALLclosure) v.AuxInt = argwid v.AddArg(entry) v.AddArg(closure) v.AddArg(mem) return true } } func rewriteValuePPC64_OpCom16_0(v *Value) bool { // match: (Com16 x) // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCom32_0(v *Value) bool { // match: (Com32 x) // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCom64_0(v *Value) bool { // match: (Com64 x) // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCom8_0(v *Value) bool { // match: (Com8 x) // result: (NOR x x) for { x := v.Args[0] v.reset(OpPPC64NOR) v.AddArg(x) v.AddArg(x) return true } } func rewriteValuePPC64_OpCondSelect_0(v *Value) bool { b := v.Block // match: (CondSelect x y bool) // cond: flagArg(bool) != nil // result: (ISEL [2] x y bool) for { bool := v.Args[2] x := v.Args[0] y := v.Args[1] if !(flagArg(bool) != nil) { break } v.reset(OpPPC64ISEL) v.AuxInt = 2 v.AddArg(x) v.AddArg(y) v.AddArg(bool) return true } // match: (CondSelect x y bool) // cond: flagArg(bool) == nil // result: (ISEL [2] x y (CMPWconst [0] bool)) for { bool := v.Args[2] x := v.Args[0] y := v.Args[1] if !(flagArg(bool) == nil) { break } v.reset(OpPPC64ISEL) v.AuxInt = 2 v.AddArg(x) v.AddArg(y) v0 := b.NewValue0(v.Pos, OpPPC64CMPWconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(bool) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpConst16_0(v *Value) bool { // match: (Const16 [val]) // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst32_0(v *Value) bool { // match: (Const32 [val]) // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst32F_0(v *Value) bool { // match: (Const32F [val]) // result: (FMOVSconst [val]) for { val := v.AuxInt v.reset(OpPPC64FMOVSconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst64_0(v *Value) bool { // match: (Const64 [val]) // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst64F_0(v *Value) bool { // match: (Const64F [val]) // result: (FMOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConst8_0(v *Value) bool { // match: (Const8 [val]) // result: (MOVDconst [val]) for { val := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = val return true } } func rewriteValuePPC64_OpConstBool_0(v *Value) bool { // match: (ConstBool [b]) // result: (MOVDconst [b]) for { b := v.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = b return true } } func rewriteValuePPC64_OpConstNil_0(v *Value) bool { // match: (ConstNil) // result: (MOVDconst [0]) for { v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } } func rewriteValuePPC64_OpCopysign_0(v *Value) bool { // match: (Copysign x y) // result: (FCPSGN y x) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FCPSGN) v.AddArg(y) v.AddArg(x) return true } } func rewriteValuePPC64_OpCtz16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (POPCNTW (MOVHZreg (ANDN (ADDconst [-1] x) x))) for { x := v.Args[0] v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v1 := b.NewValue0(v.Pos, OpPPC64ANDN, typ.Int16) v2 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.Int16) v2.AuxInt = -1 v2.AddArg(x) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCtz32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // cond: objabi.GOPPC64<=8 // result: (POPCNTW (MOVWZreg (ANDN (ADDconst [-1] x) x))) for { x := v.Args[0] if !(objabi.GOPPC64 <= 8) { break } v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZreg, typ.Int64) v1 := b.NewValue0(v.Pos, OpPPC64ANDN, typ.Int) v2 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.Int) v2.AuxInt = -1 v2.AddArg(x) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Ctz32 x) // result: (CNTTZW (MOVWZreg x)) for { x := v.Args[0] v.reset(OpPPC64CNTTZW) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCtz32NonZero_0(v *Value) bool { // match: (Ctz32NonZero x) // result: (Ctz32 x) for { x := v.Args[0] v.reset(OpCtz32) v.AddArg(x) return true } } func rewriteValuePPC64_OpCtz64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // cond: objabi.GOPPC64<=8 // result: (POPCNTD (ANDN (ADDconst [-1] x) x)) for { x := v.Args[0] if !(objabi.GOPPC64 <= 8) { break } v.reset(OpPPC64POPCNTD) v0 := b.NewValue0(v.Pos, OpPPC64ANDN, typ.Int64) v1 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.Int64) v1.AuxInt = -1 v1.AddArg(x) v0.AddArg(v1) v0.AddArg(x) v.AddArg(v0) return true } // match: (Ctz64 x) // result: (CNTTZD x) for { x := v.Args[0] v.reset(OpPPC64CNTTZD) v.AddArg(x) return true } } func rewriteValuePPC64_OpCtz64NonZero_0(v *Value) bool { // match: (Ctz64NonZero x) // result: (Ctz64 x) for { x := v.Args[0] v.reset(OpCtz64) v.AddArg(x) return true } } func rewriteValuePPC64_OpCtz8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (POPCNTB (MOVBZreg (ANDN (ADDconst [-1] x) x))) for { x := v.Args[0] v.reset(OpPPC64POPCNTB) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v1 := b.NewValue0(v.Pos, OpPPC64ANDN, typ.UInt8) v2 := b.NewValue0(v.Pos, OpPPC64ADDconst, typ.UInt8) v2.AuxInt = -1 v2.AddArg(x) v1.AddArg(v2) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32Fto32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt32Fto32 x) // result: (MFVSRD (FCTIWZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIWZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32Fto64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt32Fto64 x) // result: (MFVSRD (FCTIDZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIDZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32Fto64F_0(v *Value) bool { // match: (Cvt32Fto64F x) // result: x for { x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } } func rewriteValuePPC64_OpCvt32to32F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt32to32F x) // result: (FCFIDS (MTVSRD (SignExt32to64 x))) for { x := v.Args[0] v.reset(OpPPC64FCFIDS) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt32to64F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt32to64F x) // result: (FCFID (MTVSRD (SignExt32to64 x))) for { x := v.Args[0] v.reset(OpPPC64FCFID) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v1 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64Fto32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt64Fto32 x) // result: (MFVSRD (FCTIWZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIWZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64Fto32F_0(v *Value) bool { // match: (Cvt64Fto32F x) // result: (FRSP x) for { x := v.Args[0] v.reset(OpPPC64FRSP) v.AddArg(x) return true } } func rewriteValuePPC64_OpCvt64Fto64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt64Fto64 x) // result: (MFVSRD (FCTIDZ x)) for { x := v.Args[0] v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIDZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64to32F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt64to32F x) // result: (FCFIDS (MTVSRD x)) for { x := v.Args[0] v.reset(OpPPC64FCFIDS) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64to64F_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Cvt64to64F x) // result: (FCFID (MTVSRD x)) for { x := v.Args[0] v.reset(OpPPC64FCFID) v0 := b.NewValue0(v.Pos, OpPPC64MTVSRD, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpDiv16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16 x y) // result: (DIVW (SignExt16to32 x) (SignExt16to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpDiv16u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVWU) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpDiv32_0(v *Value) bool { // match: (Div32 x y) // result: (DIVW x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv32F_0(v *Value) bool { // match: (Div32F x y) // result: (FDIVS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FDIVS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv32u_0(v *Value) bool { // match: (Div32u x y) // result: (DIVWU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVWU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv64_0(v *Value) bool { // match: (Div64 x y) // result: (DIVD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv64F_0(v *Value) bool { // match: (Div64F x y) // result: (FDIV x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FDIV) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv64u_0(v *Value) bool { // match: (Div64u x y) // result: (DIVDU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVDU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpDiv8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (DIVW (SignExt8to32 x) (SignExt8to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpDiv8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64DIVWU) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpEq16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq16 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] y := v.Args[1^_i0] if !(isSigned(x.Type) && isSigned(y.Type)) { continue } v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } break } // match: (Eq16 x y) // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq32_0(v *Value) bool { b := v.Block // match: (Eq32 x y) // result: (Equal (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq32F_0(v *Value) bool { b := v.Block // match: (Eq32F x y) // result: (Equal (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq64_0(v *Value) bool { b := v.Block // match: (Eq64 x y) // result: (Equal (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq64F_0(v *Value) bool { b := v.Block // match: (Eq64F x y) // result: (Equal (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEq8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Eq8 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] y := v.Args[1^_i0] if !(isSigned(x.Type) && isSigned(y.Type)) { continue } v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } break } // match: (Eq8 x y) // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEqB_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (EqB x y) // result: (ANDconst [1] (EQV x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = 1 v0 := b.NewValue0(v.Pos, OpPPC64EQV, typ.Int64) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpEqPtr_0(v *Value) bool { b := v.Block // match: (EqPtr x y) // result: (Equal (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64Equal) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpFMA_0(v *Value) bool { // match: (FMA x y z) // result: (FMADD x y z) for { z := v.Args[2] x := v.Args[0] y := v.Args[1] v.reset(OpPPC64FMADD) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } } func rewriteValuePPC64_OpFloor_0(v *Value) bool { // match: (Floor x) // result: (FFLOOR x) for { x := v.Args[0] v.reset(OpPPC64FFLOOR) v.AddArg(x) return true } } func rewriteValuePPC64_OpGeq16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Geq16 x y) // result: (GreaterEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq16U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Geq16U x y) // result: (GreaterEqual (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq32_0(v *Value) bool { b := v.Block // match: (Geq32 x y) // result: (GreaterEqual (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq32F_0(v *Value) bool { b := v.Block // match: (Geq32F x y) // result: (FGreaterEqual (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FGreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq32U_0(v *Value) bool { b := v.Block // match: (Geq32U x y) // result: (GreaterEqual (CMPWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq64_0(v *Value) bool { b := v.Block // match: (Geq64 x y) // result: (GreaterEqual (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq64F_0(v *Value) bool { b := v.Block // match: (Geq64F x y) // result: (FGreaterEqual (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FGreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq64U_0(v *Value) bool { b := v.Block // match: (Geq64U x y) // result: (GreaterEqual (CMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Geq8 x y) // result: (GreaterEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGeq8U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Geq8U x y) // result: (GreaterEqual (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGetCallerPC_0(v *Value) bool { // match: (GetCallerPC) // result: (LoweredGetCallerPC) for { v.reset(OpPPC64LoweredGetCallerPC) return true } } func rewriteValuePPC64_OpGetCallerSP_0(v *Value) bool { // match: (GetCallerSP) // result: (LoweredGetCallerSP) for { v.reset(OpPPC64LoweredGetCallerSP) return true } } func rewriteValuePPC64_OpGetClosurePtr_0(v *Value) bool { // match: (GetClosurePtr) // result: (LoweredGetClosurePtr) for { v.reset(OpPPC64LoweredGetClosurePtr) return true } } func rewriteValuePPC64_OpGreater16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Greater16 x y) // result: (GreaterThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater16U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Greater16U x y) // result: (GreaterThan (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater32_0(v *Value) bool { b := v.Block // match: (Greater32 x y) // result: (GreaterThan (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater32F_0(v *Value) bool { b := v.Block // match: (Greater32F x y) // result: (FGreaterThan (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FGreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater32U_0(v *Value) bool { b := v.Block // match: (Greater32U x y) // result: (GreaterThan (CMPWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater64_0(v *Value) bool { b := v.Block // match: (Greater64 x y) // result: (GreaterThan (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater64F_0(v *Value) bool { b := v.Block // match: (Greater64F x y) // result: (FGreaterThan (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FGreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater64U_0(v *Value) bool { b := v.Block // match: (Greater64U x y) // result: (GreaterThan (CMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Greater8 x y) // result: (GreaterThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpGreater8U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Greater8U x y) // result: (GreaterThan (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64GreaterThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpHmul32_0(v *Value) bool { // match: (Hmul32 x y) // result: (MULHW x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULHW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpHmul32u_0(v *Value) bool { // match: (Hmul32u x y) // result: (MULHWU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULHWU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpHmul64_0(v *Value) bool { // match: (Hmul64 x y) // result: (MULHD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULHD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpHmul64u_0(v *Value) bool { // match: (Hmul64u x y) // result: (MULHDU x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULHDU) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpInterCall_0(v *Value) bool { // match: (InterCall [argwid] entry mem) // result: (CALLinter [argwid] entry mem) for { argwid := v.AuxInt mem := v.Args[1] entry := v.Args[0] v.reset(OpPPC64CALLinter) v.AuxInt = argwid v.AddArg(entry) v.AddArg(mem) return true } } func rewriteValuePPC64_OpIsInBounds_0(v *Value) bool { b := v.Block // match: (IsInBounds idx len) // result: (LessThan (CMPU idx len)) for { len := v.Args[1] idx := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValuePPC64_OpIsNonNil_0(v *Value) bool { b := v.Block // match: (IsNonNil ptr) // result: (NotEqual (CMPconst [0] ptr)) for { ptr := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(ptr) v.AddArg(v0) return true } } func rewriteValuePPC64_OpIsSliceInBounds_0(v *Value) bool { b := v.Block // match: (IsSliceInBounds idx len) // result: (LessEqual (CMPU idx len)) for { len := v.Args[1] idx := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(idx) v0.AddArg(len) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Leq16 x y) // result: (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq16U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Leq16U x y) // result: (LessEqual (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq32_0(v *Value) bool { b := v.Block // match: (Leq32 x y) // result: (LessEqual (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq32F_0(v *Value) bool { b := v.Block // match: (Leq32F x y) // result: (FLessEqual (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FLessEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq32U_0(v *Value) bool { b := v.Block // match: (Leq32U x y) // result: (LessEqual (CMPWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq64_0(v *Value) bool { b := v.Block // match: (Leq64 x y) // result: (LessEqual (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq64F_0(v *Value) bool { b := v.Block // match: (Leq64F x y) // result: (FLessEqual (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FLessEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq64U_0(v *Value) bool { b := v.Block // match: (Leq64U x y) // result: (LessEqual (CMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Leq8 x y) // result: (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq8U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Leq8U x y) // result: (LessEqual (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Less16 x y) // result: (LessThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess16U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Less16U x y) // result: (LessThan (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess32_0(v *Value) bool { b := v.Block // match: (Less32 x y) // result: (LessThan (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess32F_0(v *Value) bool { b := v.Block // match: (Less32F x y) // result: (FLessThan (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FLessThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess32U_0(v *Value) bool { b := v.Block // match: (Less32U x y) // result: (LessThan (CMPWU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess64_0(v *Value) bool { b := v.Block // match: (Less64 x y) // result: (LessThan (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess64F_0(v *Value) bool { b := v.Block // match: (Less64F x y) // result: (FLessThan (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FLessThan) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess64U_0(v *Value) bool { b := v.Block // match: (Less64U x y) // result: (LessThan (CMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Less8 x y) // result: (LessThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLess8U_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Less8U x y) // result: (LessThan (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LessThan) v0 := b.NewValue0(v.Pos, OpPPC64CMPWU, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLoad_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVDload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpPPC64MOVDload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) && isSigned(t) // result: (MOVWload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitInt(t) && isSigned(t)) { break } v.reset(OpPPC64MOVWload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) && !isSigned(t) // result: (MOVWZload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitInt(t) && !isSigned(t)) { break } v.reset(OpPPC64MOVWZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) && isSigned(t) // result: (MOVHload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is16BitInt(t) && isSigned(t)) { break } v.reset(OpPPC64MOVHload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) && !isSigned(t) // result: (MOVHZload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is16BitInt(t) && !isSigned(t)) { break } v.reset(OpPPC64MOVHZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: t.IsBoolean() // result: (MOVBZload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(t.IsBoolean()) { break } v.reset(OpPPC64MOVBZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is8BitInt(t) && isSigned(t) // result: (MOVBreg (MOVBZload ptr mem)) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is8BitInt(t) && isSigned(t)) { break } v.reset(OpPPC64MOVBreg) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AddArg(ptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Load ptr mem) // cond: is8BitInt(t) && !isSigned(t) // result: (MOVBZload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is8BitInt(t) && !isSigned(t)) { break } v.reset(OpPPC64MOVBZload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (FMOVSload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is32BitFloat(t)) { break } v.reset(OpPPC64FMOVSload) v.AddArg(ptr) v.AddArg(mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (FMOVDload ptr mem) for { t := v.Type mem := v.Args[1] ptr := v.Args[0] if !(is64BitFloat(t)) { break } v.reset(OpPPC64FMOVDload) v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpLocalAddr_0(v *Value) bool { // match: (LocalAddr {sym} base _) // result: (MOVDaddr {sym} base) for { sym := v.Aux _ = v.Args[1] base := v.Args[0] v.reset(OpPPC64MOVDaddr) v.Aux = sym v.AddArg(base) return true } } func rewriteValuePPC64_OpLsh16x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh16x16 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh16x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x32 x (Const64 [c])) // cond: uint32(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x32 x (MOVDconst [c])) // cond: uint32(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh16x32 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh16x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh16x64 x (MOVDconst [c])) // cond: uint64(c) < 16 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh16x64 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh16x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh16x8 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -16 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh32x16 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x32 x (Const64 [c])) // cond: uint32(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x32 x (MOVDconst [c])) // cond: uint32(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh32x32 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh32x64 x (MOVDconst [c])) // cond: uint64(c) < 32 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh32x64 x (AND y (MOVDconst [31]))) // result: (SLW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { y := v_1.Args[_i0] v_1_1 := v_1.Args[1^_i0] if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { continue } v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } break } // match: (Lsh32x64 x (ANDconst [31] y)) // result: (SLW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst || v_1.Type != typ.Int32 || v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh32x64 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh32x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh32x8 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SLD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLD) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh64x16 x y) // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x32 x (Const64 [c])) // cond: uint32(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x32 x (MOVDconst [c])) // cond: uint32(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SLD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLD) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh64x32 x y) // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x64 x (Const64 [c])) // cond: uint64(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh64x64 x (MOVDconst [c])) // cond: uint64(c) < 64 // result: (SLDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SLDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SLD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLD) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh64x64 x (AND y (MOVDconst [63]))) // result: (SLD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { y := v_1.Args[_i0] v_1_1 := v_1.Args[1^_i0] if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { continue } v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } break } // match: (Lsh64x64 x (ANDconst [63] y)) // result: (SLD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst || v_1.Type != typ.Int64 || v_1.AuxInt != 63 { break } y := v_1.Args[0] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Lsh64x64 x y) // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh64x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SLD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLD) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh64x8 x y) // result: (SLD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh8x16 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x32 x (Const64 [c])) // cond: uint32(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x32 x (MOVDconst [c])) // cond: uint32(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh8x32 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Lsh8x64 x (MOVDconst [c])) // cond: uint64(c) < 8 // result: (SLWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SLWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh8x64 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpLsh8x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg(x) v.AddArg(y) return true } // match: (Lsh8x8 x y) // result: (SLW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SLW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -8 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod16 x y) // result: (Mod32 (SignExt16to32 x) (SignExt16to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpMod32) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMod16u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpMod32u) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMod32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod32 x y) // result: (SUB x (MULLW y (DIVW x y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLW, typ.Int32) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVW, typ.Int32) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod32u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (SUB x (MULLW y (DIVWU x y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLW, typ.Int32) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVWU, typ.Int32) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod64 x y) // result: (SUB x (MULLD y (DIVD x y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLD, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVD, typ.Int64) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod64u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (SUB x (MULLD y (DIVDU x y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64MULLD, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64DIVDU, typ.Int64) v1.AddArg(x) v1.AddArg(y) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpMod8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Mod32 (SignExt8to32 x) (SignExt8to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpMod32) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMod8u_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpMod32u) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg(v1) return true } } func rewriteValuePPC64_OpMove_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if v.AuxInt != 0 { break } mem := v.Args[2] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBZload src mem) mem) for { if v.AuxInt != 1 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVBstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [2] dst src mem) // result: (MOVHstore dst (MOVHZload src mem) mem) for { if v.AuxInt != 2 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVHstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [4] dst src mem) // result: (MOVWstore dst (MOVWZload src mem) mem) for { if v.AuxInt != 4 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVWstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [8] {t} dst src mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstore dst (MOVDload src mem) mem) for { if v.AuxInt != 8 { break } t := v.Aux mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstore) v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVDload, typ.Int64) v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v.AddArg(mem) return true } // match: (Move [8] dst src mem) // result: (MOVWstore [4] dst (MOVWZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem)) for { if v.AuxInt != 8 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVWstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBZload [2] src mem) (MOVHstore dst (MOVHload src mem) mem)) for { if v.AuxInt != 3 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVBstore) v.AuxInt = 2 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AuxInt = 2 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVHstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVHload, typ.Int16) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem)) for { if v.AuxInt != 5 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVBstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [6] dst src mem) // result: (MOVHstore [4] dst (MOVHZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem)) for { if v.AuxInt != 6 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVHstore) v.AuxInt = 4 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16) v0.AuxInt = 4 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v1.AddArg(mem) v.AddArg(v1) return true } // match: (Move [7] dst src mem) // result: (MOVBstore [6] dst (MOVBZload [6] src mem) (MOVHstore [4] dst (MOVHZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem))) for { if v.AuxInt != 7 { break } mem := v.Args[2] dst := v.Args[0] src := v.Args[1] v.reset(OpPPC64MOVBstore) v.AuxInt = 6 v.AddArg(dst) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, typ.UInt8) v0.AuxInt = 6 v0.AddArg(src) v0.AddArg(mem) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64MOVHstore, types.TypeMem) v1.AuxInt = 4 v1.AddArg(dst) v2 := b.NewValue0(v.Pos, OpPPC64MOVHZload, typ.UInt16) v2.AuxInt = 4 v2.AddArg(src) v2.AddArg(mem) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpPPC64MOVWstore, types.TypeMem) v3.AddArg(dst) v4 := b.NewValue0(v.Pos, OpPPC64MOVWZload, typ.UInt32) v4.AddArg(src) v4.AddArg(mem) v3.AddArg(v4) v3.AddArg(mem) v1.AddArg(v3) v.AddArg(v1) return true } return false } func rewriteValuePPC64_OpMove_10(v *Value) bool { // match: (Move [s] dst src mem) // cond: s > 8 // result: (LoweredMove [s] dst src mem) for { s := v.AuxInt mem := v.Args[2] dst := v.Args[0] src := v.Args[1] if !(s > 8) { break } v.reset(OpPPC64LoweredMove) v.AuxInt = s v.AddArg(dst) v.AddArg(src) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpMul16_0(v *Value) bool { // match: (Mul16 x y) // result: (MULLW x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul32_0(v *Value) bool { // match: (Mul32 x y) // result: (MULLW x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul32F_0(v *Value) bool { // match: (Mul32F x y) // result: (FMULS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FMULS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul64_0(v *Value) bool { // match: (Mul64 x y) // result: (MULLD x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULLD) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul64F_0(v *Value) bool { // match: (Mul64F x y) // result: (FMUL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FMUL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul64uhilo_0(v *Value) bool { // match: (Mul64uhilo x y) // result: (LoweredMuluhilo x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64LoweredMuluhilo) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpMul8_0(v *Value) bool { // match: (Mul8 x y) // result: (MULLW x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64MULLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpNeg16_0(v *Value) bool { // match: (Neg16 x) // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg32_0(v *Value) bool { // match: (Neg32 x) // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg32F_0(v *Value) bool { // match: (Neg32F x) // result: (FNEG x) for { x := v.Args[0] v.reset(OpPPC64FNEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg64_0(v *Value) bool { // match: (Neg64 x) // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg64F_0(v *Value) bool { // match: (Neg64F x) // result: (FNEG x) for { x := v.Args[0] v.reset(OpPPC64FNEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeg8_0(v *Value) bool { // match: (Neg8 x) // result: (NEG x) for { x := v.Args[0] v.reset(OpPPC64NEG) v.AddArg(x) return true } } func rewriteValuePPC64_OpNeq16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Neq16 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] y := v.Args[1^_i0] if !(isSigned(x.Type) && isSigned(y.Type)) { continue } v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } break } // match: (Neq16 x y) // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq32_0(v *Value) bool { b := v.Block // match: (Neq32 x y) // result: (NotEqual (CMPW x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq32F_0(v *Value) bool { b := v.Block // match: (Neq32F x y) // result: (NotEqual (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq64_0(v *Value) bool { b := v.Block // match: (Neq64 x y) // result: (NotEqual (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq64F_0(v *Value) bool { b := v.Block // match: (Neq64F x y) // result: (NotEqual (FCMPU x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeq8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Neq8 x y) // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] y := v.Args[1^_i0] if !(isSigned(x.Type) && isSigned(y.Type)) { continue } v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } break } // match: (Neq8 x y) // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNeqB_0(v *Value) bool { // match: (NeqB x y) // result: (XOR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpNeqPtr_0(v *Value) bool { b := v.Block // match: (NeqPtr x y) // result: (NotEqual (CMP x y)) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64NotEqual) v0 := b.NewValue0(v.Pos, OpPPC64CMP, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) v.AddArg(v0) return true } } func rewriteValuePPC64_OpNilCheck_0(v *Value) bool { // match: (NilCheck ptr mem) // result: (LoweredNilCheck ptr mem) for { mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredNilCheck) v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpNot_0(v *Value) bool { // match: (Not x) // result: (XORconst [1] x) for { x := v.Args[0] v.reset(OpPPC64XORconst) v.AuxInt = 1 v.AddArg(x) return true } } func rewriteValuePPC64_OpOffPtr_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // result: (ADD (MOVDconst [off]) ptr) for { off := v.AuxInt ptr := v.Args[0] v.reset(OpPPC64ADD) v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = off v.AddArg(v0) v.AddArg(ptr) return true } } func rewriteValuePPC64_OpOr16_0(v *Value) bool { // match: (Or16 x y) // result: (OR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOr32_0(v *Value) bool { // match: (Or32 x y) // result: (OR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOr64_0(v *Value) bool { // match: (Or64 x y) // result: (OR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOr8_0(v *Value) bool { // match: (Or8 x y) // result: (OR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpOrB_0(v *Value) bool { // match: (OrB x y) // result: (OR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64OR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpPPC64ADD_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ADD (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64SLDconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64SRDconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADD (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64SLWconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64SRWconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (ADD (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // result: (ROTL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64SLD { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64SRD { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { continue } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADD (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // result: (ROTLW x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64SLW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64SRW { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { continue } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } break } // match: (ADD x (MOVDconst [c])) // cond: is32Bit(c) // result: (ADDconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64MOVDconst { continue } c := v_1.AuxInt if !(is32Bit(c)) { continue } v.reset(OpPPC64ADDconst) v.AuxInt = c v.AddArg(x) return true } break } return false } func rewriteValuePPC64_OpPPC64ADDconst_0(v *Value) bool { // match: (ADDconst [c] (ADDconst [d] x)) // cond: is32Bit(c+d) // result: (ADDconst [c+d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } d := v_0.AuxInt x := v_0.Args[0] if !(is32Bit(c + d)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = c + d v.AddArg(x) return true } // match: (ADDconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ADDconst [c] (MOVDaddr [d] {sym} x)) // result: (MOVDaddr [c+d] {sym} x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDaddr { break } d := v_0.AuxInt sym := v_0.Aux x := v_0.Args[0] v.reset(OpPPC64MOVDaddr) v.AuxInt = c + d v.Aux = sym v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64AND_0(v *Value) bool { // match: (AND x (NOR y y)) // result: (ANDN x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64NOR { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpPPC64ANDN) v.AddArg(x) v.AddArg(y) return true } break } // match: (AND (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c&d]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64MOVDconst { continue } c := v_0.AuxInt v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64MOVDconst { continue } d := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c & d return true } break } // match: (AND x (MOVDconst [c])) // cond: isU16Bit(c) // result: (ANDconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64MOVDconst { continue } c := v_1.AuxInt if !(isU16Bit(c)) { continue } v.reset(OpPPC64ANDconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (AND (MOVDconst [c]) y:(MOVWZreg _)) // cond: c&0xFFFFFFFF == 0xFFFFFFFF // result: y for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64MOVDconst { continue } c := v_0.AuxInt y := v.Args[1^_i0] if y.Op != OpPPC64MOVWZreg || !(c&0xFFFFFFFF == 0xFFFFFFFF) { continue } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } break } // match: (AND (MOVDconst [0xFFFFFFFF]) y:(MOVWreg x)) // result: (MOVWZreg x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64MOVDconst || v_0.AuxInt != 0xFFFFFFFF { continue } y := v.Args[1^_i0] if y.Op != OpPPC64MOVWreg { continue } x := y.Args[0] v.reset(OpPPC64MOVWZreg) v.AddArg(x) return true } break } // match: (AND (MOVDconst [c]) x:(MOVBZload _ _)) // result: (ANDconst [c&0xFF] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64MOVDconst { continue } c := v_0.AuxInt x := v.Args[1^_i0] if x.Op != OpPPC64MOVBZload { continue } _ = x.Args[1] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } break } return false } func rewriteValuePPC64_OpPPC64ANDconst_0(v *Value) bool { // match: (ANDconst [c] (ANDconst [d] x)) // result: (ANDconst [c&d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64ANDconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & d v.AddArg(x) return true } // match: (ANDconst [-1] x) // result: x for { if v.AuxInt != -1 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ANDconst [0] _) // result: (MOVDconst [0]) for { if v.AuxInt != 0 { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ANDconst [c] y:(MOVBZreg _)) // cond: c&0xFF == 0xFF // result: y for { c := v.AuxInt y := v.Args[0] if y.Op != OpPPC64MOVBZreg || !(c&0xFF == 0xFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [0xFF] y:(MOVBreg _)) // result: y for { if v.AuxInt != 0xFF { break } y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [c] y:(MOVHZreg _)) // cond: c&0xFFFF == 0xFFFF // result: y for { c := v.AuxInt y := v.Args[0] if y.Op != OpPPC64MOVHZreg || !(c&0xFFFF == 0xFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [0xFFFF] y:(MOVHreg _)) // result: y for { if v.AuxInt != 0xFFFF { break } y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ANDconst [c] (MOVBreg x)) // result: (ANDconst [c&0xFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } // match: (ANDconst [c] (MOVBZreg x)) // result: (ANDconst [c&0xFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBZreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFF v.AddArg(x) return true } // match: (ANDconst [c] (MOVHreg x)) // result: (ANDconst [c&0xFFFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVHreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFFFF v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ANDconst_10(v *Value) bool { // match: (ANDconst [c] (MOVHZreg x)) // result: (ANDconst [c&0xFFFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVHZreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFFFF v.AddArg(x) return true } // match: (ANDconst [c] (MOVWreg x)) // result: (ANDconst [c&0xFFFFFFFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFFFFFFFF v.AddArg(x) return true } // match: (ANDconst [c] (MOVWZreg x)) // result: (ANDconst [c&0xFFFFFFFF] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWZreg { break } x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = c & 0xFFFFFFFF v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64CMP_0(v *Value) bool { b := v.Block // match: (CMP x (MOVDconst [c])) // cond: is16Bit(c) // result: (CMPconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64CMPconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMP (MOVDconst [c]) y) // cond: is16Bit(c) // result: (InvertFlags (CMPconst y [c])) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPU_0(v *Value) bool { b := v.Block // match: (CMPU x (MOVDconst [c])) // cond: isU16Bit(c) // result: (CMPUconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64CMPUconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPU (MOVDconst [c]) y) // cond: isU16Bit(c) // result: (InvertFlags (CMPUconst y [c])) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPUconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPUconst_0(v *Value) bool { // match: (CMPUconst (MOVDconst [x]) [y]) // cond: x==y // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(x == y) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPUconst (MOVDconst [x]) [y]) // cond: uint64(x)uint64(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(uint64(x) > uint64(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64CMPW_0(v *Value) bool { b := v.Block // match: (CMPW x (MOVWreg y)) // result: (CMPW x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } y := v_1.Args[0] v.reset(OpPPC64CMPW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPW (MOVWreg x) y) // result: (CMPW x y) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWreg { break } x := v_0.Args[0] v.reset(OpPPC64CMPW) v.AddArg(x) v.AddArg(y) return true } // match: (CMPW x (MOVDconst [c])) // cond: is16Bit(c) // result: (CMPWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64CMPWconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPW (MOVDconst [c]) y) // cond: is16Bit(c) // result: (InvertFlags (CMPWconst y [c])) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPWconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPWU_0(v *Value) bool { b := v.Block // match: (CMPWU x (MOVWZreg y)) // result: (CMPWU x y) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } y := v_1.Args[0] v.reset(OpPPC64CMPWU) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWU (MOVWZreg x) y) // result: (CMPWU x y) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVWZreg { break } x := v_0.Args[0] v.reset(OpPPC64CMPWU) v.AddArg(x) v.AddArg(y) return true } // match: (CMPWU x (MOVDconst [c])) // cond: isU16Bit(c) // result: (CMPWUconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64CMPWUconst) v.AuxInt = c v.AddArg(x) return true } // match: (CMPWU (MOVDconst [c]) y) // cond: isU16Bit(c) // result: (InvertFlags (CMPWUconst y [c])) for { y := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt if !(isU16Bit(c)) { break } v.reset(OpPPC64InvertFlags) v0 := b.NewValue0(v.Pos, OpPPC64CMPWUconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(y) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpPPC64CMPWUconst_0(v *Value) bool { // match: (CMPWUconst (MOVDconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPWUconst (MOVDconst [x]) [y]) // cond: uint32(x)uint32(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(uint32(x) > uint32(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64CMPWconst_0(v *Value) bool { // match: (CMPWconst (MOVDconst [x]) [y]) // cond: int32(x)==int32(y) // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int32(x) == int32(y)) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPWconst (MOVDconst [x]) [y]) // cond: int32(x)int32(y) // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(int32(x) > int32(y)) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64CMPconst_0(v *Value) bool { // match: (CMPconst (MOVDconst [x]) [y]) // cond: x==y // result: (FlagEQ) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(x == y) { break } v.reset(OpPPC64FlagEQ) return true } // match: (CMPconst (MOVDconst [x]) [y]) // cond: xy // result: (FlagGT) for { y := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } x := v_0.AuxInt if !(x > y) { break } v.reset(OpPPC64FlagGT) return true } return false } func rewriteValuePPC64_OpPPC64Equal_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Equal (FlagEQ)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (Equal (FlagLT)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Equal (FlagGT)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Equal (InvertFlags x)) // result: (Equal x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64Equal) v.AddArg(x) return true } // match: (Equal cmp) // result: (ISELB [2] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 2 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64FABS_0(v *Value) bool { // match: (FABS (FMOVDconst [x])) // result: (FMOVDconst [auxFrom64F(math.Abs(auxTo64F(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = auxFrom64F(math.Abs(auxTo64F(x))) return true } return false } func rewriteValuePPC64_OpPPC64FADD_0(v *Value) bool { // match: (FADD (FMUL x y) z) // result: (FMADD x y z) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64FMUL { continue } y := v_0.Args[1] x := v_0.Args[0] z := v.Args[1^_i0] v.reset(OpPPC64FMADD) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } break } return false } func rewriteValuePPC64_OpPPC64FADDS_0(v *Value) bool { // match: (FADDS (FMULS x y) z) // result: (FMADDS x y z) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64FMULS { continue } y := v_0.Args[1] x := v_0.Args[0] z := v.Args[1^_i0] v.reset(OpPPC64FMADDS) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } break } return false } func rewriteValuePPC64_OpPPC64FCEIL_0(v *Value) bool { // match: (FCEIL (FMOVDconst [x])) // result: (FMOVDconst [auxFrom64F(math.Ceil(auxTo64F(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = auxFrom64F(math.Ceil(auxTo64F(x))) return true } return false } func rewriteValuePPC64_OpPPC64FFLOOR_0(v *Value) bool { // match: (FFLOOR (FMOVDconst [x])) // result: (FMOVDconst [auxFrom64F(math.Floor(auxTo64F(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = auxFrom64F(math.Floor(auxTo64F(x))) return true } return false } func rewriteValuePPC64_OpPPC64FGreaterEqual_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (FGreaterEqual cmp) // result: (ISEL [2] (MOVDconst [1]) (ISELB [1] (MOVDconst [1]) cmp) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISEL) v.AuxInt = 2 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ISELB, typ.Int32) v1.AuxInt = 1 v2 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v2.AuxInt = 1 v1.AddArg(v2) v1.AddArg(cmp) v.AddArg(v1) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64FGreaterThan_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (FGreaterThan cmp) // result: (ISELB [1] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 1 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64FLessEqual_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (FLessEqual cmp) // result: (ISEL [2] (MOVDconst [1]) (ISELB [0] (MOVDconst [1]) cmp) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISEL) v.AuxInt = 2 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ISELB, typ.Int32) v1.AuxInt = 0 v2 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v2.AuxInt = 1 v1.AddArg(v2) v1.AddArg(cmp) v.AddArg(v1) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64FLessThan_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (FLessThan cmp) // result: (ISELB [0] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 0 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64FMOVDload_0(v *Value) bool { // match: (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr x _)) // result: (MTVSRD x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } x := v_1.Args[1] v.reset(OpPPC64MTVSRD) v.AddArg(x) return true } // match: (FMOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is16Bit(off1+off2) // result: (FMOVDload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FMOVDstore_0(v *Value) bool { // match: (FMOVDstore [off] {sym} ptr (MTVSRD x) mem) // result: (MOVDstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MTVSRD { break } x := v_1.Args[0] v.reset(OpPPC64MOVDstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is16Bit(off1+off2) // result: (FMOVDstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (FMOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FMOVSload_0(v *Value) bool { // match: (FMOVSload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVSload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is16Bit(off1+off2) // result: (FMOVSload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVSload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FMOVSstore_0(v *Value) bool { // match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is16Bit(off1+off2) // result: (FMOVSstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] val := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64FMOVSstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (FMOVSstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64FMOVSstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64FNEG_0(v *Value) bool { // match: (FNEG (FABS x)) // result: (FNABS x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FABS { break } x := v_0.Args[0] v.reset(OpPPC64FNABS) v.AddArg(x) return true } // match: (FNEG (FNABS x)) // result: (FABS x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FNABS { break } x := v_0.Args[0] v.reset(OpPPC64FABS) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64FSQRT_0(v *Value) bool { // match: (FSQRT (FMOVDconst [x])) // result: (FMOVDconst [auxFrom64F(math.Sqrt(auxTo64F(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = auxFrom64F(math.Sqrt(auxTo64F(x))) return true } return false } func rewriteValuePPC64_OpPPC64FSUB_0(v *Value) bool { // match: (FSUB (FMUL x y) z) // result: (FMSUB x y z) for { z := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMUL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpPPC64FMSUB) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FSUBS_0(v *Value) bool { // match: (FSUBS (FMULS x y) z) // result: (FMSUBS x y z) for { z := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64FMULS { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpPPC64FMSUBS) v.AddArg(x) v.AddArg(y) v.AddArg(z) return true } return false } func rewriteValuePPC64_OpPPC64FTRUNC_0(v *Value) bool { // match: (FTRUNC (FMOVDconst [x])) // result: (FMOVDconst [auxFrom64F(math.Trunc(auxTo64F(x)))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } x := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = auxFrom64F(math.Trunc(auxTo64F(x))) return true } return false } func rewriteValuePPC64_OpPPC64GreaterEqual_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (GreaterEqual (FlagEQ)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (GreaterEqual (FlagLT)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (GreaterEqual (FlagGT)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (GreaterEqual (InvertFlags x)) // result: (LessEqual x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64LessEqual) v.AddArg(x) return true } // match: (GreaterEqual cmp) // result: (ISELB [4] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 4 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64GreaterThan_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (GreaterThan (FlagEQ)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (GreaterThan (FlagLT)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (GreaterThan (FlagGT)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (GreaterThan (InvertFlags x)) // result: (LessThan x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64LessThan) v.AddArg(x) return true } // match: (GreaterThan cmp) // result: (ISELB [1] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 1 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64ISEL_0(v *Value) bool { // match: (ISEL [2] x _ (FlagEQ)) // result: x for { if v.AuxInt != 2 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagEQ { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [2] _ y (FlagLT)) // result: y for { if v.AuxInt != 2 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagLT { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [2] _ y (FlagGT)) // result: y for { if v.AuxInt != 2 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagGT { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [6] _ y (FlagEQ)) // result: y for { if v.AuxInt != 6 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagEQ { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [6] x _ (FlagLT)) // result: x for { if v.AuxInt != 6 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagLT { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [6] x _ (FlagGT)) // result: x for { if v.AuxInt != 6 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagGT { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [0] _ y (FlagEQ)) // result: y for { if v.AuxInt != 0 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagEQ { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [0] _ y (FlagGT)) // result: y for { if v.AuxInt != 0 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagGT { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [0] x _ (FlagLT)) // result: x for { if v.AuxInt != 0 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagLT { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [5] _ x (FlagEQ)) // result: x for { if v.AuxInt != 5 { break } _ = v.Args[2] x := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagEQ { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ISEL_10(v *Value) bool { // match: (ISEL [5] _ x (FlagLT)) // result: x for { if v.AuxInt != 5 { break } _ = v.Args[2] x := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagLT { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [5] y _ (FlagGT)) // result: y for { if v.AuxInt != 5 { break } _ = v.Args[2] y := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagGT { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [1] _ y (FlagEQ)) // result: y for { if v.AuxInt != 1 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagEQ { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [1] _ y (FlagLT)) // result: y for { if v.AuxInt != 1 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagLT { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [1] x _ (FlagGT)) // result: x for { if v.AuxInt != 1 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagGT { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [4] x _ (FlagEQ)) // result: x for { if v.AuxInt != 4 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagEQ { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [4] x _ (FlagGT)) // result: x for { if v.AuxInt != 4 { break } _ = v.Args[2] x := v.Args[0] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagGT { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (ISEL [4] _ y (FlagLT)) // result: y for { if v.AuxInt != 4 { break } _ = v.Args[2] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64FlagLT { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (ISEL [n] x y (InvertFlags bool)) // cond: n%4 == 0 // result: (ISEL [n+1] x y bool) for { n := v.AuxInt _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64InvertFlags { break } bool := v_2.Args[0] if !(n%4 == 0) { break } v.reset(OpPPC64ISEL) v.AuxInt = n + 1 v.AddArg(x) v.AddArg(y) v.AddArg(bool) return true } // match: (ISEL [n] x y (InvertFlags bool)) // cond: n%4 == 1 // result: (ISEL [n-1] x y bool) for { n := v.AuxInt _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64InvertFlags { break } bool := v_2.Args[0] if !(n%4 == 1) { break } v.reset(OpPPC64ISEL) v.AuxInt = n - 1 v.AddArg(x) v.AddArg(y) v.AddArg(bool) return true } return false } func rewriteValuePPC64_OpPPC64ISEL_20(v *Value) bool { // match: (ISEL [n] x y (InvertFlags bool)) // cond: n%4 == 2 // result: (ISEL [n] x y bool) for { n := v.AuxInt _ = v.Args[2] x := v.Args[0] y := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64InvertFlags { break } bool := v_2.Args[0] if !(n%4 == 2) { break } v.reset(OpPPC64ISEL) v.AuxInt = n v.AddArg(x) v.AddArg(y) v.AddArg(bool) return true } return false } func rewriteValuePPC64_OpPPC64ISELB_0(v *Value) bool { // match: (ISELB [0] _ (FlagLT)) // result: (MOVDconst [1]) for { if v.AuxInt != 0 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [0] _ (FlagGT)) // result: (MOVDconst [0]) for { if v.AuxInt != 0 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [0] _ (FlagEQ)) // result: (MOVDconst [0]) for { if v.AuxInt != 0 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [1] _ (FlagGT)) // result: (MOVDconst [1]) for { if v.AuxInt != 1 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [1] _ (FlagLT)) // result: (MOVDconst [0]) for { if v.AuxInt != 1 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [1] _ (FlagEQ)) // result: (MOVDconst [0]) for { if v.AuxInt != 1 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [2] _ (FlagEQ)) // result: (MOVDconst [1]) for { if v.AuxInt != 2 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [2] _ (FlagLT)) // result: (MOVDconst [0]) for { if v.AuxInt != 2 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [2] _ (FlagGT)) // result: (MOVDconst [0]) for { if v.AuxInt != 2 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [4] _ (FlagLT)) // result: (MOVDconst [0]) for { if v.AuxInt != 4 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } return false } func rewriteValuePPC64_OpPPC64ISELB_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ISELB [4] _ (FlagGT)) // result: (MOVDconst [1]) for { if v.AuxInt != 4 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [4] _ (FlagEQ)) // result: (MOVDconst [1]) for { if v.AuxInt != 4 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [5] _ (FlagGT)) // result: (MOVDconst [0]) for { if v.AuxInt != 5 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [5] _ (FlagLT)) // result: (MOVDconst [1]) for { if v.AuxInt != 5 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [5] _ (FlagEQ)) // result: (MOVDconst [1]) for { if v.AuxInt != 5 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [6] _ (FlagEQ)) // result: (MOVDconst [0]) for { if v.AuxInt != 6 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (ISELB [6] _ (FlagLT)) // result: (MOVDconst [1]) for { if v.AuxInt != 6 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [6] _ (FlagGT)) // result: (MOVDconst [1]) for { if v.AuxInt != 6 { break } _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (ISELB [n] (MOVDconst [1]) (InvertFlags bool)) // cond: n%4 == 0 // result: (ISELB [n+1] (MOVDconst [1]) bool) for { n := v.AuxInt _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst || v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpPPC64InvertFlags { break } bool := v_1.Args[0] if !(n%4 == 0) { break } v.reset(OpPPC64ISELB) v.AuxInt = n + 1 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(bool) return true } // match: (ISELB [n] (MOVDconst [1]) (InvertFlags bool)) // cond: n%4 == 1 // result: (ISELB [n-1] (MOVDconst [1]) bool) for { n := v.AuxInt _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst || v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpPPC64InvertFlags { break } bool := v_1.Args[0] if !(n%4 == 1) { break } v.reset(OpPPC64ISELB) v.AuxInt = n - 1 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(bool) return true } return false } func rewriteValuePPC64_OpPPC64ISELB_20(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (ISELB [n] (MOVDconst [1]) (InvertFlags bool)) // cond: n%4 == 2 // result: (ISELB [n] (MOVDconst [1]) bool) for { n := v.AuxInt _ = v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst || v_0.AuxInt != 1 { break } v_1 := v.Args[1] if v_1.Op != OpPPC64InvertFlags { break } bool := v_1.Args[0] if !(n%4 == 2) { break } v.reset(OpPPC64ISELB) v.AuxInt = n v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(bool) return true } return false } func rewriteValuePPC64_OpPPC64LessEqual_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (LessEqual (FlagEQ)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (LessEqual (FlagLT)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (LessEqual (FlagGT)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (LessEqual (InvertFlags x)) // result: (GreaterEqual x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64GreaterEqual) v.AddArg(x) return true } // match: (LessEqual cmp) // result: (ISELB [5] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 5 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64LessThan_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (LessThan (FlagEQ)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (LessThan (FlagLT)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (LessThan (FlagGT)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (LessThan (InvertFlags x)) // result: (GreaterThan x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64GreaterThan) v.AddArg(x) return true } // match: (LessThan cmp) // result: (ISELB [0] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 0 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64MFVSRD_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MFVSRD (FMOVDconst [c])) // result: (MOVDconst [c]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FMOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c return true } // match: (MFVSRD x:(FMOVDload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVDload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpPPC64FMOVDload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpPPC64MOVDload, typ.Int64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBZload_0(v *Value) bool { // match: (MOVBZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVBZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVBZload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBZload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVBZload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVBZload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBZload [0] {sym} p:(ADD ptr idx) mem) // cond: sym == nil && p.Uses == 1 // result: (MOVBZloadidx ptr idx mem) for { if v.AuxInt != 0 { break } sym := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] if !(sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVBZloadidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBZloadidx_0(v *Value) bool { // match: (MOVBZloadidx ptr (MOVDconst [c]) mem) // cond: is16Bit(c) // result: (MOVBZload [c] ptr mem) for { mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64MOVBZload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBZloadidx (MOVDconst [c]) ptr mem) // cond: is16Bit(c) // result: (MOVBZload [c] ptr mem) for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVBZload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBZreg_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVBZreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBZreg (SRWconst [c] (MOVBZreg x))) // result: (SRWconst [c] (MOVBZreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVBZreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVBZreg (SRWconst [c] x)) // cond: sizeof(x.Type) == 8 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(sizeof(x.Type) == 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBZreg (SRDconst [c] x)) // cond: c>=56 // result: (SRDconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c >= 56) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBZreg (SRWconst [c] x)) // cond: c>=24 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c >= 24) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBZreg y:(MOVBZreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBZreg (MOVBreg x)) // result: (MOVBZreg x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBreg { break } x := v_0.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } // match: (MOVBZreg x:(MOVBZload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVBZreg x:(MOVBZloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVBZreg x:(Arg )) // cond: is8BitInt(t) && !isSigned(t) // result: x for { x := v.Args[0] if x.Op != OpArg { break } t := x.Type if !(is8BitInt(t) && !isSigned(t)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MOVBZreg_10(v *Value) bool { // match: (MOVBZreg (MOVDconst [c])) // result: (MOVDconst [int64(uint8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(uint8(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVBreg_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVBreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0x7F // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0x7F) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBreg (SRAWconst [c] (MOVBreg x))) // result: (SRAWconst [c] (MOVBreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVBreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVBreg (SRAWconst [c] x)) // cond: sizeof(x.Type) == 8 // result: (SRAWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(sizeof(x.Type) == 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBreg (SRDconst [c] x)) // cond: c>56 // result: (SRDconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c > 56) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBreg (SRDconst [c] x)) // cond: c==56 // result: (SRADconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c == 56) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBreg (SRWconst [c] x)) // cond: c>24 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c > 24) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBreg (SRWconst [c] x)) // cond: c==24 // result: (SRAWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c == 24) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVBreg y:(MOVBreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVBreg (MOVBZreg x)) // result: (MOVBreg x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVBZreg { break } x := v_0.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } // match: (MOVBreg x:(Arg )) // cond: is8BitInt(t) && isSigned(t) // result: x for { x := v.Args[0] if x.Op != OpArg { break } t := x.Type if !(is8BitInt(t) && isSigned(t)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MOVBreg_10(v *Value) bool { // match: (MOVBreg (MOVDconst [c])) // result: (MOVDconst [int64(int8(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(int8(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstore_0(v *Value) bool { // match: (MOVBstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVBstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVBstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst || v_1.AuxInt != 0 { break } v.reset(OpPPC64MOVBstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} p:(ADD ptr idx) val mem) // cond: off == 0 && sym == nil && p.Uses == 1 // result: (MOVBstoreidx ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] val := v.Args[1] if !(off == 0 && sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVBstoreidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVBreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBZreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVBZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVHZreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVWZreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstore_10(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVBstore [off] {sym} ptr (SRWconst (MOVHreg x) [c]) mem) // cond: c <= 8 // result: (MOVBstore [off] {sym} ptr (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } c := v_1.AuxInt v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVHreg { break } x := v_1_0.Args[0] if !(c <= 8) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (SRWconst (MOVHZreg x) [c]) mem) // cond: c <= 8 // result: (MOVBstore [off] {sym} ptr (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } c := v_1.AuxInt v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVHZreg { break } x := v_1_0.Args[0] if !(c <= 8) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (SRWconst (MOVWreg x) [c]) mem) // cond: c <= 24 // result: (MOVBstore [off] {sym} ptr (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } c := v_1.AuxInt v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVWreg { break } x := v_1_0.Args[0] if !(c <= 24) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [off] {sym} ptr (SRWconst (MOVWZreg x) [c]) mem) // cond: c <= 24 // result: (MOVBstore [off] {sym} ptr (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst { break } c := v_1.AuxInt v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVWZreg { break } x := v_1_0.Args[0] if !(c <= 24) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i1] {s} p (SRWconst w [24]) x0:(MOVBstore [i0] {s} p (SRWconst w [16]) mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0) // result: (MOVHstore [i0] {s} p (SRWconst w [16]) mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst || v_1.AuxInt != 24 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRWconst || x0_1.AuxInt != 16 || w != x0_1.Args[0] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpPPC64SRWconst, typ.UInt16) v0.AuxInt = 16 v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i1] {s} p (SRDconst w [24]) x0:(MOVBstore [i0] {s} p (SRDconst w [16]) mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0) // result: (MOVHstore [i0] {s} p (SRWconst w [16]) mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst || v_1.AuxInt != 24 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRDconst || x0_1.AuxInt != 16 || w != x0_1.Args[0] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v0 := b.NewValue0(x0.Pos, OpPPC64SRWconst, typ.UInt16) v0.AuxInt = 16 v0.AddArg(w) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstore [i1] {s} p (SRWconst w [8]) x0:(MOVBstore [i0] {s} p w mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0) // result: (MOVHstore [i0] {s} p w mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] || w != x0.Args[1] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i1] {s} p (SRDconst w [8]) x0:(MOVBstore [i0] {s} p w mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0) // result: (MOVHstore [i0] {s} p w mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst || v_1.AuxInt != 8 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] || w != x0.Args[1] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i3] {s} p w x0:(MOVBstore [i2] {s} p (SRWconst w [8]) x1:(MOVBstore [i1] {s} p (SRWconst w [16]) x2:(MOVBstore [i0] {s} p (SRWconst w [24]) mem)))) // cond: !config.BigEndian && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && clobber(x0) && clobber(x1) && clobber(x2) // result: (MOVWBRstore (MOVDaddr [i0] {s} p) w mem) for { i3 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i2 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRWconst || x0_1.AuxInt != 8 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpPPC64MOVBstore { break } i1 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpPPC64SRWconst || x1_1.AuxInt != 16 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpPPC64MOVBstore { break } i0 := x2.AuxInt if x2.Aux != s { break } mem := x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpPPC64SRWconst || x2_1.AuxInt != 24 || w != x2_1.Args[0] || !(!config.BigEndian && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && clobber(x0) && clobber(x1) && clobber(x2)) { break } v.reset(OpPPC64MOVWBRstore) v0 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i1] {s} p w x0:(MOVBstore [i0] {s} p (SRWconst w [8]) mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0) // result: (MOVHBRstore (MOVDaddr [i0] {s} p) w mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRWconst || x0_1.AuxInt != 8 || w != x0_1.Args[0] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+1 && clobber(x0)) { break } v.reset(OpPPC64MOVHBRstore) v0 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstore_20(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVBstore [i7] {s} p (SRDconst w [56]) x0:(MOVBstore [i6] {s} p (SRDconst w [48]) x1:(MOVBstore [i5] {s} p (SRDconst w [40]) x2:(MOVBstore [i4] {s} p (SRDconst w [32]) x3:(MOVWstore [i0] {s} p w mem))))) // cond: !config.BigEndian && i0%4 == 0 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) // result: (MOVDstore [i0] {s} p w mem) for { i7 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst || v_1.AuxInt != 56 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i6 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRDconst || x0_1.AuxInt != 48 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpPPC64MOVBstore { break } i5 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpPPC64SRDconst || x1_1.AuxInt != 40 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpPPC64MOVBstore { break } i4 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpPPC64SRDconst || x2_1.AuxInt != 32 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpPPC64MOVWstore { break } i0 := x3.AuxInt if x3.Aux != s { break } mem := x3.Args[2] if p != x3.Args[0] || w != x3.Args[1] || !(!config.BigEndian && i0%4 == 0 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3)) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVBstore [i7] {s} p w x0:(MOVBstore [i6] {s} p (SRDconst w [8]) x1:(MOVBstore [i5] {s} p (SRDconst w [16]) x2:(MOVBstore [i4] {s} p (SRDconst w [24]) x3:(MOVBstore [i3] {s} p (SRDconst w [32]) x4:(MOVBstore [i2] {s} p (SRDconst w [40]) x5:(MOVBstore [i1] {s} p (SRDconst w [48]) x6:(MOVBstore [i0] {s} p (SRDconst w [56]) mem)))))))) // cond: !config.BigEndian && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) // result: (MOVDBRstore (MOVDaddr [i0] {s} p) w mem) for { i7 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] w := v.Args[1] x0 := v.Args[2] if x0.Op != OpPPC64MOVBstore { break } i6 := x0.AuxInt if x0.Aux != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpPPC64SRDconst || x0_1.AuxInt != 8 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpPPC64MOVBstore { break } i5 := x1.AuxInt if x1.Aux != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpPPC64SRDconst || x1_1.AuxInt != 16 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpPPC64MOVBstore { break } i4 := x2.AuxInt if x2.Aux != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpPPC64SRDconst || x2_1.AuxInt != 24 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpPPC64MOVBstore { break } i3 := x3.AuxInt if x3.Aux != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpPPC64SRDconst || x3_1.AuxInt != 32 || w != x3_1.Args[0] { break } x4 := x3.Args[2] if x4.Op != OpPPC64MOVBstore { break } i2 := x4.AuxInt if x4.Aux != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpPPC64SRDconst || x4_1.AuxInt != 40 || w != x4_1.Args[0] { break } x5 := x4.Args[2] if x5.Op != OpPPC64MOVBstore { break } i1 := x5.AuxInt if x5.Aux != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpPPC64SRDconst || x5_1.AuxInt != 48 || w != x5_1.Args[0] { break } x6 := x5.Args[2] if x6.Op != OpPPC64MOVBstore { break } i0 := x6.AuxInt if x6.Aux != s { break } mem := x6.Args[2] if p != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpPPC64SRDconst || x6_1.AuxInt != 56 || w != x6_1.Args[0] || !(!config.BigEndian && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { break } v.reset(OpPPC64MOVDBRstore) v0 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v.AddArg(v0) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstoreidx_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVBstoreidx ptr (MOVDconst [c]) val mem) // cond: is16Bit(c) // result: (MOVBstore [c] ptr val mem) for { mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt val := v.Args[2] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx (MOVDconst [c]) ptr val mem) // cond: is16Bit(c) // result: (MOVBstore [c] ptr val mem) for { mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] val := v.Args[2] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVBstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (MOVBreg x) mem) // result: (MOVBstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVBreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (MOVBZreg x) mem) // result: (MOVBstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVBZreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (MOVHreg x) mem) // result: (MOVBstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVHreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (MOVHZreg x) mem) // result: (MOVBstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVHZreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (MOVWreg x) mem) // result: (MOVBstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVWreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (MOVWZreg x) mem) // result: (MOVBstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVWZreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (SRWconst (MOVHreg x) [c]) mem) // cond: c <= 8 // result: (MOVBstoreidx [off] {sym} ptr idx (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64SRWconst { break } c := v_2.AuxInt v_2_0 := v_2.Args[0] if v_2_0.Op != OpPPC64MOVHreg { break } x := v_2_0.Args[0] if !(c <= 8) { break } v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (SRWconst (MOVHZreg x) [c]) mem) // cond: c <= 8 // result: (MOVBstoreidx [off] {sym} ptr idx (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64SRWconst { break } c := v_2.AuxInt v_2_0 := v_2.Args[0] if v_2_0.Op != OpPPC64MOVHZreg { break } x := v_2_0.Args[0] if !(c <= 8) { break } v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstoreidx_10(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVBstoreidx [off] {sym} ptr idx (SRWconst (MOVWreg x) [c]) mem) // cond: c <= 24 // result: (MOVBstoreidx [off] {sym} ptr idx (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64SRWconst { break } c := v_2.AuxInt v_2_0 := v_2.Args[0] if v_2_0.Op != OpPPC64MOVWreg { break } x := v_2_0.Args[0] if !(c <= 24) { break } v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } // match: (MOVBstoreidx [off] {sym} ptr idx (SRWconst (MOVWZreg x) [c]) mem) // cond: c <= 24 // result: (MOVBstoreidx [off] {sym} ptr idx (SRWconst x [c]) mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64SRWconst { break } c := v_2.AuxInt v_2_0 := v_2.Args[0] if v_2_0.Op != OpPPC64MOVWZreg { break } x := v_2_0.Args[0] if !(c <= 24) { break } v.reset(OpPPC64MOVBstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v0 := b.NewValue0(v.Pos, OpPPC64SRWconst, typ.UInt32) v0.AuxInt = c v0.AddArg(x) v.AddArg(v0) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVBstorezero_0(v *Value) bool { // match: (MOVBstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVBstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVBstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVBstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVBstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDload_0(v *Value) bool { // match: (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr x _)) // result: (MFVSRD x) for { off := v.AuxInt sym := v.Aux _ = v.Args[1] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64FMOVDstore || v_1.AuxInt != off || v_1.Aux != sym { break } _ = v_1.Args[2] if ptr != v_1.Args[0] { break } x := v_1.Args[1] v.reset(OpPPC64MFVSRD) v.AddArg(x) return true } // match: (MOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVDload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVDload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) && (off1+off2)%4 == 0 // result: (MOVDload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1+off2) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVDload [0] {sym} p:(ADD ptr idx) mem) // cond: sym == nil && p.Uses == 1 // result: (MOVDloadidx ptr idx mem) for { if v.AuxInt != 0 { break } sym := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] if !(sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVDloadidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDloadidx_0(v *Value) bool { // match: (MOVDloadidx ptr (MOVDconst [c]) mem) // cond: is16Bit(c) && c%4 == 0 // result: (MOVDload [c] ptr mem) for { mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c) && c%4 == 0) { break } v.reset(OpPPC64MOVDload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVDloadidx (MOVDconst [c]) ptr mem) // cond: is16Bit(c) && c%4 == 0 // result: (MOVDload [c] ptr mem) for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] if !(is16Bit(c) && c%4 == 0) { break } v.reset(OpPPC64MOVDload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDstore_0(v *Value) bool { // match: (MOVDstore [off] {sym} ptr (MFVSRD x) mem) // result: (FMOVDstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MFVSRD { break } x := v_1.Args[0] v.reset(OpPPC64FMOVDstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVDstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) && (off1+off2)%4 == 0 // result: (MOVDstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] if !(is16Bit(off1+off2) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVDstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVDstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst || v_1.AuxInt != 0 { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVDstore [off] {sym} p:(ADD ptr idx) val mem) // cond: off == 0 && sym == nil && p.Uses == 1 // result: (MOVDstoreidx ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] val := v.Args[1] if !(off == 0 && sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVDstoreidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDstoreidx_0(v *Value) bool { // match: (MOVDstoreidx ptr (MOVDconst [c]) val mem) // cond: is16Bit(c) && c%4 == 0 // result: (MOVDstore [c] ptr val mem) for { mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt val := v.Args[2] if !(is16Bit(c) && c%4 == 0) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVDstoreidx (MOVDconst [c]) ptr val mem) // cond: is16Bit(c) && c%4 == 0 // result: (MOVDstore [c] ptr val mem) for { mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] val := v.Args[2] if !(is16Bit(c) && c%4 == 0) { break } v.reset(OpPPC64MOVDstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVDstorezero_0(v *Value) bool { // match: (MOVDstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) && (off1+off2)%4 == 0 // result: (MOVDstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1+off2) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVDstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 // result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHBRstore_0(v *Value) bool { // match: (MOVHBRstore {sym} ptr (MOVHreg x) mem) // result: (MOVHBRstore {sym} ptr x mem) for { sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHBRstore) v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHBRstore {sym} ptr (MOVHZreg x) mem) // result: (MOVHBRstore {sym} ptr x mem) for { sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHBRstore) v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHBRstore {sym} ptr (MOVWreg x) mem) // result: (MOVHBRstore {sym} ptr x mem) for { sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHBRstore) v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHBRstore {sym} ptr (MOVWZreg x) mem) // result: (MOVHBRstore {sym} ptr x mem) for { sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHBRstore) v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHZload_0(v *Value) bool { // match: (MOVHZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVHZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHZload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHZload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVHZload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHZload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHZload [0] {sym} p:(ADD ptr idx) mem) // cond: sym == nil && p.Uses == 1 // result: (MOVHZloadidx ptr idx mem) for { if v.AuxInt != 0 { break } sym := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] if !(sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVHZloadidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHZloadidx_0(v *Value) bool { // match: (MOVHZloadidx ptr (MOVDconst [c]) mem) // cond: is16Bit(c) // result: (MOVHZload [c] ptr mem) for { mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64MOVHZload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHZloadidx (MOVDconst [c]) ptr mem) // cond: is16Bit(c) // result: (MOVHZload [c] ptr mem) for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVHZload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHZreg_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVHZreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg (SRWconst [c] (MOVBZreg x))) // result: (SRWconst [c] (MOVBZreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVBZreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVHZreg (SRWconst [c] (MOVHZreg x))) // result: (SRWconst [c] (MOVHZreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVHZreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVHZreg (SRWconst [c] x)) // cond: sizeof(x.Type) <= 16 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(sizeof(x.Type) <= 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHZreg (SRDconst [c] x)) // cond: c>=48 // result: (SRDconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c >= 48) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHZreg (SRWconst [c] x)) // cond: c>=16 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c >= 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHZreg y:(MOVHZreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg y:(MOVBZreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg y:(MOVHBRload _ _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHBRload { break } _ = y.Args[1] v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHZreg y:(MOVHreg x)) // result: (MOVHZreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } x := y.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MOVHZreg_10(v *Value) bool { // match: (MOVHZreg x:(MOVBZload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHZreg x:(MOVBZloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHZreg x:(MOVHZload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHZreg x:(MOVHZloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHZloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHZreg x:(Arg )) // cond: (is8BitInt(t) || is16BitInt(t)) && !isSigned(t) // result: x for { x := v.Args[0] if x.Op != OpArg { break } t := x.Type if !((is8BitInt(t) || is16BitInt(t)) && !isSigned(t)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHZreg (MOVDconst [c])) // result: (MOVDconst [int64(uint16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(uint16(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVHload_0(v *Value) bool { // match: (MOVHload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVHload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHload [0] {sym} p:(ADD ptr idx) mem) // cond: sym == nil && p.Uses == 1 // result: (MOVHloadidx ptr idx mem) for { if v.AuxInt != 0 { break } sym := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] if !(sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVHloadidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHloadidx_0(v *Value) bool { // match: (MOVHloadidx ptr (MOVDconst [c]) mem) // cond: is16Bit(c) // result: (MOVHload [c] ptr mem) for { mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64MOVHload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHloadidx (MOVDconst [c]) ptr mem) // cond: is16Bit(c) // result: (MOVHload [c] ptr mem) for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVHload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHreg_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVHreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0x7FFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0x7FFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHreg (SRAWconst [c] (MOVBreg x))) // result: (SRAWconst [c] (MOVBreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVBreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVHreg (SRAWconst [c] (MOVHreg x))) // result: (SRAWconst [c] (MOVHreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVHreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVHreg (SRAWconst [c] x)) // cond: sizeof(x.Type) <= 16 // result: (SRAWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(sizeof(x.Type) <= 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHreg (SRDconst [c] x)) // cond: c>48 // result: (SRDconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c > 48) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHreg (SRDconst [c] x)) // cond: c==48 // result: (SRADconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c == 48) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHreg (SRWconst [c] x)) // cond: c>16 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c > 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHreg (SRWconst [c] x)) // cond: c==16 // result: (SRAWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c == 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVHreg y:(MOVHreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVHreg y:(MOVBreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } return false } func rewriteValuePPC64_OpPPC64MOVHreg_10(v *Value) bool { // match: (MOVHreg y:(MOVHZreg x)) // result: (MOVHreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } x := y.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHreg x:(MOVHloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHreg x:(Arg )) // cond: (is8BitInt(t) || is16BitInt(t)) && isSigned(t) // result: x for { x := v.Args[0] if x.Op != OpArg { break } t := x.Type if !((is8BitInt(t) || is16BitInt(t)) && isSigned(t)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVHreg (MOVDconst [c])) // result: (MOVDconst [int64(int16(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(int16(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVHstore_0(v *Value) bool { b := v.Block config := b.Func.Config // match: (MOVHstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVHstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVHstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst || v_1.AuxInt != 0 { break } v.reset(OpPPC64MOVHstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} p:(ADD ptr idx) val mem) // cond: off == 0 && sym == nil && p.Uses == 1 // result: (MOVHstoreidx ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] val := v.Args[1] if !(off == 0 && sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVHstoreidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHZreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVHZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVWZreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVHstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstore [i1] {s} p (SRWconst w [16]) x0:(MOVHstore [i0] {s} p w mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+2 && clobber(x0) // result: (MOVWstore [i0] {s} p w mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRWconst || v_1.AuxInt != 16 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVHstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] || w != x0.Args[1] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+2 && clobber(x0)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } // match: (MOVHstore [i1] {s} p (SRDconst w [16]) x0:(MOVHstore [i0] {s} p w mem)) // cond: !config.BigEndian && x0.Uses == 1 && i1 == i0+2 && clobber(x0) // result: (MOVWstore [i0] {s} p w mem) for { i1 := v.AuxInt s := v.Aux _ = v.Args[2] p := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SRDconst || v_1.AuxInt != 16 { break } w := v_1.Args[0] x0 := v.Args[2] if x0.Op != OpPPC64MOVHstore { break } i0 := x0.AuxInt if x0.Aux != s { break } mem := x0.Args[2] if p != x0.Args[0] || w != x0.Args[1] || !(!config.BigEndian && x0.Uses == 1 && i1 == i0+2 && clobber(x0)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = i0 v.Aux = s v.AddArg(p) v.AddArg(w) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHstoreidx_0(v *Value) bool { // match: (MOVHstoreidx ptr (MOVDconst [c]) val mem) // cond: is16Bit(c) // result: (MOVHstore [c] ptr val mem) for { mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt val := v.Args[2] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstoreidx (MOVDconst [c]) ptr val mem) // cond: is16Bit(c) // result: (MOVHstore [c] ptr val mem) for { mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] val := v.Args[2] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVHstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVHstoreidx [off] {sym} ptr idx (MOVHreg x) mem) // result: (MOVHstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVHreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVHstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstoreidx [off] {sym} ptr idx (MOVHZreg x) mem) // result: (MOVHstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVHZreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVHstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstoreidx [off] {sym} ptr idx (MOVWreg x) mem) // result: (MOVHstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVWreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVHstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstoreidx [off] {sym} ptr idx (MOVWZreg x) mem) // result: (MOVHstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVWZreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVHstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVHstorezero_0(v *Value) bool { // match: (MOVHstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVHstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVHstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVHstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVHstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWBRstore_0(v *Value) bool { // match: (MOVWBRstore {sym} ptr (MOVWreg x) mem) // result: (MOVWBRstore {sym} ptr x mem) for { sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVWBRstore) v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWBRstore {sym} ptr (MOVWZreg x) mem) // result: (MOVWBRstore {sym} ptr x mem) for { sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVWBRstore) v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZload_0(v *Value) bool { // match: (MOVWZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVWZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWZload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWZload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVWZload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWZload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWZload [0] {sym} p:(ADD ptr idx) mem) // cond: sym == nil && p.Uses == 1 // result: (MOVWZloadidx ptr idx mem) for { if v.AuxInt != 0 { break } sym := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] if !(sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVWZloadidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZloadidx_0(v *Value) bool { // match: (MOVWZloadidx ptr (MOVDconst [c]) mem) // cond: is16Bit(c) // result: (MOVWZload [c] ptr mem) for { mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c)) { break } v.reset(OpPPC64MOVWZload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWZloadidx (MOVDconst [c]) ptr mem) // cond: is16Bit(c) // result: (MOVWZload [c] ptr mem) for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVWZload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZreg_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVWZreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFFFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFFFFFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(AND (MOVDconst [c]) _)) // cond: uint64(c) <= 0xFFFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { y_0 := y.Args[_i0] if y_0.Op != OpPPC64MOVDconst { continue } c := y_0.AuxInt if !(uint64(c) <= 0xFFFFFFFF) { continue } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } break } // match: (MOVWZreg (SRWconst [c] (MOVBZreg x))) // result: (SRWconst [c] (MOVBZreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVBZreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVWZreg (SRWconst [c] (MOVHZreg x))) // result: (SRWconst [c] (MOVHZreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVHZreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVWZreg (SRWconst [c] (MOVWZreg x))) // result: (SRWconst [c] (MOVWZreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVWZreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVWZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVWZreg (SRWconst [c] x)) // cond: sizeof(x.Type) <= 32 // result: (SRWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(sizeof(x.Type) <= 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVWZreg (SRDconst [c] x)) // cond: c>=32 // result: (SRDconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c >= 32) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVWZreg y:(MOVWZreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVWZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVHZreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVBZreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBZreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZreg_10(v *Value) bool { // match: (MOVWZreg y:(MOVHBRload _ _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHBRload { break } _ = y.Args[1] v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVWBRload _ _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVWBRload { break } _ = y.Args[1] v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWZreg y:(MOVWreg x)) // result: (MOVWZreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVWreg { break } x := y.Args[0] v.reset(OpPPC64MOVWZreg) v.AddArg(x) return true } // match: (MOVWZreg x:(MOVBZload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWZreg x:(MOVBZloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVBZloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWZreg x:(MOVHZload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWZreg x:(MOVHZloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHZloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWZreg x:(MOVWZload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVWZload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWZreg x:(MOVWZloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVWZloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWZreg x:(Arg )) // cond: (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !isSigned(t) // result: x for { x := v.Args[0] if x.Op != OpArg { break } t := x.Type if !((is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !isSigned(t)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64MOVWZreg_20(v *Value) bool { // match: (MOVWZreg (MOVDconst [c])) // result: (MOVDconst [int64(uint32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(uint32(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVWload_0(v *Value) bool { // match: (MOVWload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVWload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWload [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) && (off1+off2)%4 == 0 // result: (MOVWload [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1+off2) && (off1+off2)%4 == 0) { break } v.reset(OpPPC64MOVWload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWload [0] {sym} p:(ADD ptr idx) mem) // cond: sym == nil && p.Uses == 1 // result: (MOVWloadidx ptr idx mem) for { if v.AuxInt != 0 { break } sym := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] if !(sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVWloadidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWloadidx_0(v *Value) bool { // match: (MOVWloadidx ptr (MOVDconst [c]) mem) // cond: is16Bit(c) && c%4 == 0 // result: (MOVWload [c] ptr mem) for { mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is16Bit(c) && c%4 == 0) { break } v.reset(OpPPC64MOVWload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWloadidx (MOVDconst [c]) ptr mem) // cond: is16Bit(c) && c%4 == 0 // result: (MOVWload [c] ptr mem) for { mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] if !(is16Bit(c) && c%4 == 0) { break } v.reset(OpPPC64MOVWload) v.AuxInt = c v.AddArg(ptr) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWreg_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MOVWreg y:(ANDconst [c] _)) // cond: uint64(c) <= 0xFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64ANDconst { break } c := y.AuxInt if !(uint64(c) <= 0xFFFF) { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(AND (MOVDconst [c]) _)) // cond: uint64(c) <= 0x7FFFFFFF // result: y for { y := v.Args[0] if y.Op != OpPPC64AND { break } _ = y.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { y_0 := y.Args[_i0] if y_0.Op != OpPPC64MOVDconst { continue } c := y_0.AuxInt if !(uint64(c) <= 0x7FFFFFFF) { continue } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } break } // match: (MOVWreg (SRAWconst [c] (MOVBreg x))) // result: (SRAWconst [c] (MOVBreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVBreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVWreg (SRAWconst [c] (MOVHreg x))) // result: (SRAWconst [c] (MOVHreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVHreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVWreg (SRAWconst [c] (MOVWreg x))) // result: (SRAWconst [c] (MOVWreg x)) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVWreg { break } x := v_0_0.Args[0] v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpPPC64MOVWreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } // match: (MOVWreg (SRAWconst [c] x)) // cond: sizeof(x.Type) <= 32 // result: (SRAWconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRAWconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(sizeof(x.Type) <= 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVWreg (SRDconst [c] x)) // cond: c>32 // result: (SRDconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c > 32) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVWreg (SRDconst [c] x)) // cond: c==32 // result: (SRADconst [c] x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64SRDconst { break } c := v_0.AuxInt x := v_0.Args[0] if !(c == 32) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (MOVWreg y:(MOVWreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVWreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(MOVHreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVHreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } return false } func rewriteValuePPC64_OpPPC64MOVWreg_10(v *Value) bool { // match: (MOVWreg y:(MOVBreg _)) // result: y for { y := v.Args[0] if y.Op != OpPPC64MOVBreg { break } v.reset(OpCopy) v.Type = y.Type v.AddArg(y) return true } // match: (MOVWreg y:(MOVWZreg x)) // result: (MOVWreg x) for { y := v.Args[0] if y.Op != OpPPC64MOVWZreg { break } x := y.Args[0] v.reset(OpPPC64MOVWreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWreg x:(MOVHloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVHloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWreg x:(MOVWload _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVWload { break } _ = x.Args[1] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWreg x:(MOVWloadidx _ _ _)) // result: x for { x := v.Args[0] if x.Op != OpPPC64MOVWloadidx { break } _ = x.Args[2] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWreg x:(Arg )) // cond: (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && isSigned(t) // result: x for { x := v.Args[0] if x.Op != OpArg { break } t := x.Type if !((is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && isSigned(t)) { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } // match: (MOVWreg (MOVDconst [c])) // result: (MOVDconst [int64(int32(c))]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = int64(int32(c)) return true } return false } func rewriteValuePPC64_OpPPC64MOVWstore_0(v *Value) bool { // match: (MOVWstore [off1] {sym} (ADDconst [off2] x) val mem) // cond: is16Bit(off1+off2) // result: (MOVWstore [off1+off2] {sym} x val mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[2] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] val := v.Args[1] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && (ptr.Op != OpSB || p.Uses == 1) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux ptr := p.Args[0] val := v.Args[1] if !(canMergeSym(sym1, sym2) && (ptr.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVWstorezero [off] {sym} ptr mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst || v_1.AuxInt != 0 { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} p:(ADD ptr idx) val mem) // cond: off == 0 && sym == nil && p.Uses == 1 // result: (MOVWstoreidx ptr idx val mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] p := v.Args[0] if p.Op != OpPPC64ADD { break } idx := p.Args[1] ptr := p.Args[0] val := v.Args[1] if !(off == 0 && sym == nil && p.Uses == 1) { break } v.reset(OpPPC64MOVWstoreidx) v.AddArg(ptr) v.AddArg(idx) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWZreg x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[2] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVWZreg { break } x := v_1.Args[0] v.reset(OpPPC64MOVWstore) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWstoreidx_0(v *Value) bool { // match: (MOVWstoreidx ptr (MOVDconst [c]) val mem) // cond: is16Bit(c) // result: (MOVWstore [c] ptr val mem) for { mem := v.Args[3] ptr := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt val := v.Args[2] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx (MOVDconst [c]) ptr val mem) // cond: is16Bit(c) // result: (MOVWstore [c] ptr val mem) for { mem := v.Args[3] v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt ptr := v.Args[1] val := v.Args[2] if !(is16Bit(c)) { break } v.reset(OpPPC64MOVWstore) v.AuxInt = c v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (MOVWstoreidx [off] {sym} ptr idx (MOVWreg x) mem) // result: (MOVWstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVWreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVWstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstoreidx [off] {sym} ptr idx (MOVWZreg x) mem) // result: (MOVWstoreidx [off] {sym} ptr idx x mem) for { off := v.AuxInt sym := v.Aux mem := v.Args[3] ptr := v.Args[0] idx := v.Args[1] v_2 := v.Args[2] if v_2.Op != OpPPC64MOVWZreg { break } x := v_2.Args[0] v.reset(OpPPC64MOVWstoreidx) v.AuxInt = off v.Aux = sym v.AddArg(ptr) v.AddArg(idx) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MOVWstorezero_0(v *Value) bool { // match: (MOVWstorezero [off1] {sym} (ADDconst [off2] x) mem) // cond: is16Bit(off1+off2) // result: (MOVWstorezero [off1+off2] {sym} x mem) for { off1 := v.AuxInt sym := v.Aux mem := v.Args[1] v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconst { break } off2 := v_0.AuxInt x := v_0.Args[0] if !(is16Bit(off1 + off2)) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(x) v.AddArg(mem) return true } // match: (MOVWstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) // cond: canMergeSym(sym1,sym2) && (x.Op != OpSB || p.Uses == 1) // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) for { off1 := v.AuxInt sym1 := v.Aux mem := v.Args[1] p := v.Args[0] if p.Op != OpPPC64MOVDaddr { break } off2 := p.AuxInt sym2 := p.Aux x := p.Args[0] if !(canMergeSym(sym1, sym2) && (x.Op != OpSB || p.Uses == 1)) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(x) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MTVSRD_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (MTVSRD (MOVDconst [c])) // result: (FMOVDconst [c]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64MOVDconst { break } c := v_0.AuxInt v.reset(OpPPC64FMOVDconst) v.AuxInt = c return true } // match: (MTVSRD x:(MOVDload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (FMOVDload [off] {sym} ptr mem) for { x := v.Args[0] if x.Op != OpPPC64MOVDload { break } off := x.AuxInt sym := x.Aux mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpPPC64FMOVDload, typ.Float64) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = off v0.Aux = sym v0.AddArg(ptr) v0.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPPC64MaskIfNotCarry_0(v *Value) bool { // match: (MaskIfNotCarry (ADDconstForCarry [c] (ANDconst [d] _))) // cond: c < 0 && d > 0 && c + d < 0 // result: (MOVDconst [-1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64ADDconstForCarry { break } c := v_0.AuxInt v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } d := v_0_0.AuxInt if !(c < 0 && d > 0 && c+d < 0) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = -1 return true } return false } func rewriteValuePPC64_OpPPC64NotEqual_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (NotEqual (FlagEQ)) // result: (MOVDconst [0]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagEQ { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (NotEqual (FlagLT)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagLT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (NotEqual (FlagGT)) // result: (MOVDconst [1]) for { v_0 := v.Args[0] if v_0.Op != OpPPC64FlagGT { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 1 return true } // match: (NotEqual (InvertFlags x)) // result: (NotEqual x) for { v_0 := v.Args[0] if v_0.Op != OpPPC64InvertFlags { break } x := v_0.Args[0] v.reset(OpPPC64NotEqual) v.AddArg(x) return true } // match: (NotEqual cmp) // result: (ISELB [6] (MOVDconst [1]) cmp) for { cmp := v.Args[0] v.reset(OpPPC64ISELB) v.AuxInt = 6 v0 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v0.AuxInt = 1 v.AddArg(v0) v.AddArg(cmp) return true } } func rewriteValuePPC64_OpPPC64OR_0(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: ( OR (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64SLDconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64SRDconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: ( OR (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64SLWconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64SRWconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } break } // match: ( OR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // result: (ROTL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64SLD { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64SRD { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { continue } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } break } // match: ( OR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // result: (ROTLW x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64SLW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64SRW { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { continue } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } break } // match: (OR (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c|d]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64MOVDconst { continue } c := v_0.AuxInt v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64MOVDconst { continue } d := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c | d return true } break } // match: (OR x (MOVDconst [c])) // cond: isU32Bit(c) // result: (ORconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64MOVDconst { continue } c := v_1.AuxInt if !(isU32Bit(c)) { continue } v.reset(OpPPC64ORconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (OR x0:(MOVBZload [i0] {s} p mem) o1:(SLWconst x1:(MOVBZload [i1] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpPPC64MOVBZload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o1 := v.Args[1^_i0] if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { continue } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpPPC64MOVHZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } break } // match: (OR x0:(MOVBZload [i0] {s} p mem) o1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpPPC64MOVBZload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o1 := v.Args[1^_i0] if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { continue } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpPPC64MOVHZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } break } // match: (OR x0:(MOVBZload [i1] {s} p mem) o1:(SLWconst x1:(MOVBZload [i0] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpPPC64MOVBZload { continue } i1 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o1 := v.Args[1^_i0] if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { continue } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i0 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } break } // match: (OR x0:(MOVBZload [i1] {s} p mem) o1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) // result: @mergePoint(b,x0,x1) (MOVHBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpPPC64MOVBZload { continue } i1 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o1 := v.Args[1^_i0] if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { continue } x1 := o1.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i0 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } break } return false } func rewriteValuePPC64_OpPPC64OR_10(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (OR s0:(SLWconst x0:(MOVBZload [i1] {s} p mem) [n1]) s1:(SLWconst x1:(MOVBZload [i0] {s} p mem) [n2])) // cond: !config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) // result: @mergePoint(b,x0,x1) (SLDconst (MOVHBRload (MOVDaddr [i0] {s} p) mem) [n1]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpPPC64SLWconst { continue } n1 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { continue } i1 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1^_i0] if s1.Op != OpPPC64SLWconst { continue } n2 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i0 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = n1 v1 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } break } // match: (OR s0:(SLDconst x0:(MOVBZload [i1] {s} p mem) [n1]) s1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [n2])) // cond: !config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) // result: @mergePoint(b,x0,x1) (SLDconst (MOVHBRload (MOVDaddr [i0] {s} p) mem) [n1]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpPPC64SLDconst { continue } n1 := s0.AuxInt x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { continue } i1 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] s1 := v.Args[1^_i0] if s1.Op != OpPPC64SLDconst { continue } n2 := s1.AuxInt x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i0 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = n1 v1 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } break } // match: (OR s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { continue } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { continue } i3 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1^_i0] if o0.Op != OpPPC64OR || o0.Type != t { continue } _ = o0.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s0 := o0.Args[_i1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { continue } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i2 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } x0 := o0.Args[1^_i1] if x0.Op != OpPPC64MOVHZload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { continue } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } } break } // match: (OR s1:(SLDconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { continue } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { continue } i3 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1^_i0] if o0.Op != OpPPC64OR || o0.Type != t { continue } _ = o0.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s0 := o0.Args[_i1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { continue } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i2 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } x0 := o0.Args[1^_i1] if x0.Op != OpPPC64MOVHZload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { continue } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64MOVWZload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } } break } // match: (OR s1:(SLWconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR s0:(SLWconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { continue } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { continue } i0 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1^_i0] if o0.Op != OpPPC64OR || o0.Type != t { continue } _ = o0.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s0 := o0.Args[_i1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { continue } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } x0 := o0.Args[1^_i1] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { continue } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { continue } i2 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { continue } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } } break } // match: (OR s1:(SLDconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s1 := v.Args[_i0] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { continue } x2 := s1.Args[0] if x2.Op != OpPPC64MOVBZload { continue } i0 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1^_i0] if o0.Op != OpPPC64OR || o0.Type != t { continue } _ = o0.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s0 := o0.Args[_i1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { continue } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } x0 := o0.Args[1^_i1] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { continue } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { continue } i2 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { continue } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } } break } // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLWconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpPPC64MOVBZload { continue } i3 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1^_i0] if o0.Op != OpPPC64OR || o0.Type != t { continue } _ = o0.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s0 := o0.Args[_i1] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { continue } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i2 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } s1 := o0.Args[1^_i1] if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { continue } x2 := s1.Args[0] if x2.Op != OpPPC64MOVHBRload || x2.Type != t { continue } _ = x2.Args[1] x2_0 := x2.Args[0] if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { continue } i0 := x2_0.AuxInt if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { continue } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } } break } // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLDconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x0 := v.Args[_i0] if x0.Op != OpPPC64MOVBZload { continue } i3 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1^_i0] if o0.Op != OpPPC64OR || o0.Type != t { continue } _ = o0.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s0 := o0.Args[_i1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { continue } x1 := s0.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i2 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } s1 := o0.Args[1^_i1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { continue } x2 := s1.Args[0] if x2.Op != OpPPC64MOVHBRload || x2.Type != t { continue } _ = x2.Args[1] x2_0 := x2.Args[0] if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { continue } i0 := x2_0.AuxInt if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { continue } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } } break } // match: (OR s2:(SLDconst x2:(MOVBZload [i3] {s} p mem) [32]) o0:(OR s1:(SLDconst x1:(MOVBZload [i2] {s} p mem) [40]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [48]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s2 := v.Args[_i0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { continue } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { continue } i3 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1^_i0] if o0.Op != OpPPC64OR || o0.Type != t { continue } _ = o0.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s1 := o0.Args[_i1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { continue } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i2 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } s0 := o0.Args[1^_i1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { continue } x0 := s0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { continue } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { continue } i0 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { continue } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 32 v1 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } } break } // match: (OR s2:(SLDconst x2:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) [32]))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s2 := v.Args[_i0] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { continue } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { continue } i0 := x2.AuxInt s := x2.Aux mem := x2.Args[1] p := x2.Args[0] o0 := v.Args[1^_i0] if o0.Op != OpPPC64OR || o0.Type != t { continue } _ = o0.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s1 := o0.Args[_i1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { continue } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } s0 := o0.Args[1^_i1] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { continue } x0 := s0.Args[0] if x0.Op != OpPPC64MOVHBRload || x0.Type != t { continue } _ = x0.Args[1] x0_0 := x0.Args[0] if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { continue } i2 := x0_0.AuxInt if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { continue } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = 32 v1 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) v2.AuxInt = i0 v2.Aux = s v2.AddArg(p) v1.AddArg(v2) v1.AddArg(mem) v0.AddArg(v1) return true } } break } return false } func rewriteValuePPC64_OpPPC64OR_20(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem))))) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s6 := v.Args[_i0] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { continue } x7 := s6.Args[0] if x7.Op != OpPPC64MOVBZload { continue } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1^_i0] if o5.Op != OpPPC64OR || o5.Type != t { continue } _ = o5.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s5 := o5.Args[_i1] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { continue } x6 := s5.Args[0] if x6.Op != OpPPC64MOVBZload { continue } i6 := x6.AuxInt if x6.Aux != s { continue } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { continue } o4 := o5.Args[1^_i1] if o4.Op != OpPPC64OR || o4.Type != t { continue } _ = o4.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s4 := o4.Args[_i2] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { continue } x5 := s4.Args[0] if x5.Op != OpPPC64MOVBZload { continue } i5 := x5.AuxInt if x5.Aux != s { continue } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { continue } o3 := o4.Args[1^_i2] if o3.Op != OpPPC64OR || o3.Type != t { continue } _ = o3.Args[1] for _i3 := 0; _i3 <= 1; _i3++ { s3 := o3.Args[_i3] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { continue } x4 := s3.Args[0] if x4.Op != OpPPC64MOVBZload { continue } i4 := x4.AuxInt if x4.Aux != s { continue } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { continue } x0 := o3.Args[1^_i3] if x0.Op != OpPPC64MOVWZload { continue } i0 := x0.AuxInt if x0.Aux != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { continue } b = mergePoint(b, x0, x4, x5, x6, x7) v0 := b.NewValue0(x0.Pos, OpPPC64MOVDload, t) v.reset(OpCopy) v.AddArg(v0) v0.AuxInt = i0 v0.Aux = s v0.AddArg(p) v0.AddArg(mem) return true } } } } break } // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem))))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { s0 := v.Args[_i0] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { continue } x0 := s0.Args[0] if x0.Op != OpPPC64MOVBZload { continue } i0 := x0.AuxInt s := x0.Aux mem := x0.Args[1] p := x0.Args[0] o0 := v.Args[1^_i0] if o0.Op != OpPPC64OR || o0.Type != t { continue } _ = o0.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s1 := o0.Args[_i1] if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { continue } x1 := s1.Args[0] if x1.Op != OpPPC64MOVBZload { continue } i1 := x1.AuxInt if x1.Aux != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } o1 := o0.Args[1^_i1] if o1.Op != OpPPC64OR || o1.Type != t { continue } _ = o1.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s2 := o1.Args[_i2] if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { continue } x2 := s2.Args[0] if x2.Op != OpPPC64MOVBZload { continue } i2 := x2.AuxInt if x2.Aux != s { continue } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { continue } o2 := o1.Args[1^_i2] if o2.Op != OpPPC64OR || o2.Type != t { continue } _ = o2.Args[1] for _i3 := 0; _i3 <= 1; _i3++ { s3 := o2.Args[_i3] if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { continue } x3 := s3.Args[0] if x3.Op != OpPPC64MOVBZload { continue } i3 := x3.AuxInt if x3.Aux != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { continue } x4 := o2.Args[1^_i3] if x4.Op != OpPPC64MOVWBRload || x4.Type != t { continue } _ = x4.Args[1] x4_0 := x4.Args[0] if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { continue } i4 := x4_0.AuxInt if p != x4_0.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x4.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x4.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } } } } break } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x7 := v.Args[_i0] if x7.Op != OpPPC64MOVBZload { continue } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1^_i0] if o5.Op != OpPPC64OR || o5.Type != t { continue } _ = o5.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s6 := o5.Args[_i1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { continue } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { continue } i6 := x6.AuxInt if x6.Aux != s { continue } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { continue } o4 := o5.Args[1^_i1] if o4.Op != OpPPC64OR || o4.Type != t { continue } _ = o4.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s5 := o4.Args[_i2] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { continue } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { continue } i5 := x5.AuxInt if x5.Aux != s { continue } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { continue } o3 := o4.Args[1^_i2] if o3.Op != OpPPC64OR || o3.Type != t { continue } _ = o3.Args[1] for _i3 := 0; _i3 <= 1; _i3++ { s4 := o3.Args[_i3] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { continue } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { continue } i4 := x4.AuxInt if x4.Aux != s { continue } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { continue } s0 := o3.Args[1^_i3] if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { continue } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { continue } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { continue } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { continue } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } } } } break } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x7 := v.Args[_i0] if x7.Op != OpPPC64MOVBZload { continue } i7 := x7.AuxInt s := x7.Aux mem := x7.Args[1] p := x7.Args[0] o5 := v.Args[1^_i0] if o5.Op != OpPPC64OR || o5.Type != t { continue } _ = o5.Args[1] for _i1 := 0; _i1 <= 1; _i1++ { s6 := o5.Args[_i1] if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { continue } x6 := s6.Args[0] if x6.Op != OpPPC64MOVBZload { continue } i6 := x6.AuxInt if x6.Aux != s { continue } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { continue } o4 := o5.Args[1^_i1] if o4.Op != OpPPC64OR || o4.Type != t { continue } _ = o4.Args[1] for _i2 := 0; _i2 <= 1; _i2++ { s5 := o4.Args[_i2] if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { continue } x5 := s5.Args[0] if x5.Op != OpPPC64MOVBZload { continue } i5 := x5.AuxInt if x5.Aux != s { continue } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { continue } o3 := o4.Args[1^_i2] if o3.Op != OpPPC64OR || o3.Type != t { continue } _ = o3.Args[1] for _i3 := 0; _i3 <= 1; _i3++ { s4 := o3.Args[_i3] if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { continue } x4 := s4.Args[0] if x4.Op != OpPPC64MOVBZload { continue } i4 := x4.AuxInt if x4.Aux != s { continue } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { continue } s0 := o3.Args[1^_i3] if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { continue } x3 := s0.Args[0] if x3.Op != OpPPC64MOVWBRload || x3.Type != t { continue } _ = x3.Args[1] x3_0 := x3.Args[0] if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { continue } i0 := x3_0.AuxInt if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { continue } b = mergePoint(b, x3, x4, x5, x6, x7) v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) v.reset(OpCopy) v.AddArg(v0) v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) v1.AuxInt = i0 v1.Aux = s v1.AddArg(p) v0.AddArg(v1) v0.AddArg(mem) return true } } } } break } return false } func rewriteValuePPC64_OpPPC64ORN_0(v *Value) bool { // match: (ORN x (MOVDconst [-1])) // result: x for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst || v_1.AuxInt != -1 { break } v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ORconst_0(v *Value) bool { // match: (ORconst [c] (ORconst [d] x)) // result: (ORconst [c|d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64ORconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpPPC64ORconst) v.AuxInt = c | d v.AddArg(x) return true } // match: (ORconst [-1] _) // result: (MOVDconst [-1]) for { if v.AuxInt != -1 { break } v.reset(OpPPC64MOVDconst) v.AuxInt = -1 return true } // match: (ORconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ROTL_0(v *Value) bool { // match: (ROTL x (MOVDconst [c])) // result: (ROTLconst x [c&63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64ROTLconst) v.AuxInt = c & 63 v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64ROTLW_0(v *Value) bool { // match: (ROTLW x (MOVDconst [c])) // result: (ROTLWconst x [c&31]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64ROTLWconst) v.AuxInt = c & 31 v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64SUB_0(v *Value) bool { // match: (SUB x (MOVDconst [c])) // cond: is32Bit(-c) // result: (ADDconst [-c] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(is32Bit(-c)) { break } v.reset(OpPPC64ADDconst) v.AuxInt = -c v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPPC64XOR_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (XOR (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64SLDconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64SRDconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 64-c) { continue } v.reset(OpPPC64ROTLconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XOR (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64SLWconst { continue } c := v_0.AuxInt x := v_0.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64SRWconst { continue } d := v_1.AuxInt if x != v_1.Args[0] || !(d == 32-c) { continue } v.reset(OpPPC64ROTLWconst) v.AuxInt = c v.AddArg(x) return true } break } // match: (XOR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // result: (ROTL x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64SLD { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64SRD { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { continue } v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } break } // match: (XOR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // result: (ROTLW x y) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64SLW { continue } _ = v_0.Args[1] x := v_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { continue } y := v_0_1.Args[0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64SRW { continue } _ = v_1.Args[1] if x != v_1.Args[0] { continue } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { continue } _ = v_1_1.Args[1] v_1_1_0 := v_1_1.Args[0] if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { continue } v_1_1_1 := v_1_1.Args[1] if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { continue } v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } break } // match: (XOR (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c^d]) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { v_0 := v.Args[_i0] if v_0.Op != OpPPC64MOVDconst { continue } c := v_0.AuxInt v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64MOVDconst { continue } d := v_1.AuxInt v.reset(OpPPC64MOVDconst) v.AuxInt = c ^ d return true } break } // match: (XOR x (MOVDconst [c])) // cond: isU32Bit(c) // result: (XORconst [c] x) for { _ = v.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := v.Args[_i0] v_1 := v.Args[1^_i0] if v_1.Op != OpPPC64MOVDconst { continue } c := v_1.AuxInt if !(isU32Bit(c)) { continue } v.reset(OpPPC64XORconst) v.AuxInt = c v.AddArg(x) return true } break } return false } func rewriteValuePPC64_OpPPC64XORconst_0(v *Value) bool { // match: (XORconst [c] (XORconst [d] x)) // result: (XORconst [c^d] x) for { c := v.AuxInt v_0 := v.Args[0] if v_0.Op != OpPPC64XORconst { break } d := v_0.AuxInt x := v_0.Args[0] v.reset(OpPPC64XORconst) v.AuxInt = c ^ d v.AddArg(x) return true } // match: (XORconst [0] x) // result: x for { if v.AuxInt != 0 { break } x := v.Args[0] v.reset(OpCopy) v.Type = x.Type v.AddArg(x) return true } return false } func rewriteValuePPC64_OpPanicBounds_0(v *Value) bool { // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 0) { break } v.reset(OpPPC64LoweredPanicBoundsA) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 1) { break } v.reset(OpPPC64LoweredPanicBoundsB) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := v.AuxInt mem := v.Args[2] x := v.Args[0] y := v.Args[1] if !(boundsABI(kind) == 2) { break } v.reset(OpPPC64LoweredPanicBoundsC) v.AuxInt = kind v.AddArg(x) v.AddArg(y) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpPopCount16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTW (MOVHZreg x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpPopCount32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount32 x) // result: (POPCNTW (MOVWZreg x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTW) v0 := b.NewValue0(v.Pos, OpPPC64MOVWZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpPopCount64_0(v *Value) bool { // match: (PopCount64 x) // result: (POPCNTD x) for { x := v.Args[0] v.reset(OpPPC64POPCNTD) v.AddArg(x) return true } } func rewriteValuePPC64_OpPopCount8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTB (MOVBZreg x)) for { x := v.Args[0] v.reset(OpPPC64POPCNTB) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRotateLeft16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (RotateLeft16 x (MOVDconst [c])) // result: (Or16 (Lsh16x64 x (MOVDconst [c&15])) (Rsh16Ux64 x (MOVDconst [-c&15]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = c & 15 v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpRsh16Ux64, t) v2.AddArg(x) v3 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v3.AuxInt = -c & 15 v2.AddArg(v3) v.AddArg(v2) return true } return false } func rewriteValuePPC64_OpRotateLeft32_0(v *Value) bool { // match: (RotateLeft32 x (MOVDconst [c])) // result: (ROTLWconst [c&31] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64ROTLWconst) v.AuxInt = c & 31 v.AddArg(x) return true } // match: (RotateLeft32 x y) // result: (ROTLW x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ROTLW) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpRotateLeft64_0(v *Value) bool { // match: (RotateLeft64 x (MOVDconst [c])) // result: (ROTLconst [c&63] x) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpPPC64ROTLconst) v.AuxInt = c & 63 v.AddArg(x) return true } // match: (RotateLeft64 x y) // result: (ROTL x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64ROTL) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpRotateLeft8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (RotateLeft8 x (MOVDconst [c])) // result: (Or8 (Lsh8x64 x (MOVDconst [c&7])) (Rsh8Ux64 x (MOVDconst [-c&7]))) for { t := v.Type _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = c & 7 v0.AddArg(v1) v.AddArg(v0) v2 := b.NewValue0(v.Pos, OpRsh8Ux64, t) v2.AddArg(x) v3 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v3.AuxInt = -c & 7 v2.AddArg(v3) v.AddArg(v2) return true } return false } func rewriteValuePPC64_OpRound_0(v *Value) bool { // match: (Round x) // result: (FROUND x) for { x := v.Args[0] v.reset(OpPPC64FROUND) v.AddArg(x) return true } } func rewriteValuePPC64_OpRound32F_0(v *Value) bool { // match: (Round32F x) // result: (LoweredRound32F x) for { x := v.Args[0] v.reset(OpPPC64LoweredRound32F) v.AddArg(x) return true } } func rewriteValuePPC64_OpRound64F_0(v *Value) bool { // match: (Round64F x) // result: (LoweredRound64F x) for { x := v.Args[0] v.reset(OpPPC64LoweredRound64F) v.AddArg(x) return true } } func rewriteValuePPC64_OpRsh16Ux16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVHZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16Ux16 x y) // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16Ux32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux32 x (Const64 [c])) // cond: uint32(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux32 x (MOVDconst [c])) // cond: uint32(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVHZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16Ux32 x y) // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux64 _ (Const64 [c])) // cond: uint64(c) >= 16 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh16Ux64 x (MOVDconst [c])) // cond: uint64(c) < 16 // result: (SRWconst (ZeroExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVHZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16Ux64 x y) // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16Ux8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVHZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16Ux8 x y) // result: (SRW (ZeroExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVHreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16x16 x y) // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x32 x (Const64 [c])) // cond: uint32(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x32 x (MOVDconst [c])) // cond: uint32(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVHreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16x32 x y) // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x64 x (Const64 [c])) // cond: uint64(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x64 x (Const64 [c])) // cond: uint64(c) >= 16 // result: (SRAWconst (SignExt16to32 x) [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x64 x (MOVDconst [c])) // cond: uint64(c) < 16 // result: (SRAWconst (SignExt16to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 16) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVHreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16x64 x y) // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh16x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVHreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVHreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh16x8 x y) // result: (SRAW (SignExt16to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -16 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh32Ux16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32Ux16 x y) // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32Ux32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux32 x (Const64 [c])) // cond: uint32(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux32 x (MOVDconst [c])) // cond: uint32(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32Ux32 x y) // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux64 _ (Const64 [c])) // cond: uint64(c) >= 32 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh32Ux64 x (MOVDconst [c])) // cond: uint64(c) < 32 // result: (SRWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32Ux64 x (AND y (MOVDconst [31]))) // result: (SRW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { y := v_1.Args[_i0] v_1_1 := v_1.Args[1^_i0] if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { continue } v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } break } // match: (Rsh32Ux64 x (ANDconst [31] y)) // result: (SRW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst || v_1.Type != typ.UInt || v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (SUB (MOVDconst [32]) (ANDconst [31] y))) // result: (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.UInt || v_1_1.AuxInt != 31 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32Ux64 x (SUB (MOVDconst [32]) (AND y (MOVDconst [31])))) // result: (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { y := v_1_1.Args[_i0] v_1_1_1 := v_1_1.Args[1^_i0] if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 31 { continue } v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } break } // match: (Rsh32Ux64 x y) // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32Ux8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SRW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32Ux8 x y) // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SRAW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32x16 x y) // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x32 x (Const64 [c])) // cond: uint32(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x32 x (MOVDconst [c])) // cond: uint32(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SRAW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32x32 x y) // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x64 x (Const64 [c])) // cond: uint64(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x64 x (Const64 [c])) // cond: uint64(c) >= 32 // result: (SRAWconst x [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = 63 v.AddArg(x) return true } // match: (Rsh32x64 x (MOVDconst [c])) // cond: uint64(c) < 32 // result: (SRAWconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 32) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SRAW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32x64 x (AND y (MOVDconst [31]))) // result: (SRAW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { y := v_1.Args[_i0] v_1_1 := v_1.Args[1^_i0] if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { continue } v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } break } // match: (Rsh32x64 x (ANDconst [31] y)) // result: (SRAW x (ANDconst [31] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst || v_1.Type != typ.UInt || v_1.AuxInt != 31 { break } y := v_1.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 31 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh32x64 x (SUB (MOVDconst [32]) (ANDconst [31] y))) // result: (SRAW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.UInt || v_1_1.AuxInt != 31 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh32x64 x (SUB (MOVDconst [32]) (AND y (MOVDconst [31])))) // result: (SRAW x (SUB (MOVDconst [32]) (ANDconst [31] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { y := v_1_1.Args[_i0] v_1_1_1 := v_1_1.Args[1^_i0] if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 31 { continue } v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 32 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 31 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } break } // match: (Rsh32x64 x y) // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh32x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SRAW x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh32x8 x y) // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -32 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SRD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64Ux16 x y) // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux32 x (Const64 [c])) // cond: uint32(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux32 x (MOVDconst [c])) // cond: uint32(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SRD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64Ux32 x y) // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux64 x (Const64 [c])) // cond: uint64(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux64 _ (Const64 [c])) // cond: uint64(c) >= 64 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh64Ux64 x (MOVDconst [c])) // cond: uint64(c) < 64 // result: (SRDconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRDconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SRD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64Ux64 x (AND y (MOVDconst [63]))) // result: (SRD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { y := v_1.Args[_i0] v_1_1 := v_1.Args[1^_i0] if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { continue } v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } break } // match: (Rsh64Ux64 x (ANDconst [63] y)) // result: (SRD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst || v_1.Type != typ.UInt || v_1.AuxInt != 63 { break } y := v_1.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (SUB (MOVDconst [64]) (ANDconst [63] y))) // result: (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.UInt || v_1_1.AuxInt != 63 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64Ux64 x (SUB (MOVDconst [64]) (AND y (MOVDconst [63])))) // result: (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { y := v_1_1.Args[_i0] v_1_1_1 := v_1_1.Args[1^_i0] if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 63 { continue } v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } break } // match: (Rsh64Ux64 x y) // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64Ux8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SRD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64Ux8 x y) // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SRAD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64x16 x y) // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x32 x (Const64 [c])) // cond: uint32(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x32 x (MOVDconst [c])) // cond: uint32(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SRAD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64x32 x y) // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x64 x (Const64 [c])) // cond: uint64(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x64 x (Const64 [c])) // cond: uint64(c) >= 64 // result: (SRADconst x [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = 63 v.AddArg(x) return true } // match: (Rsh64x64 x (MOVDconst [c])) // cond: uint64(c) < 64 // result: (SRADconst x [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 64) { break } v.reset(OpPPC64SRADconst) v.AuxInt = c v.AddArg(x) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SRAD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64x64 x (AND y (MOVDconst [63]))) // result: (SRAD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64AND { break } _ = v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { y := v_1.Args[_i0] v_1_1 := v_1.Args[1^_i0] if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { continue } v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } break } // match: (Rsh64x64 x (ANDconst [63] y)) // result: (SRAD x (ANDconst [63] y)) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64ANDconst || v_1.Type != typ.UInt || v_1.AuxInt != 63 { break } y := v_1.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v0.AuxInt = 63 v0.AddArg(y) v.AddArg(v0) return true } // match: (Rsh64x64 x (SUB (MOVDconst [64]) (ANDconst [63] y))) // result: (SRAD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.UInt || v_1_1.AuxInt != 63 { break } y := v_1_1.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } // match: (Rsh64x64 x (SUB (MOVDconst [64]) (AND y (MOVDconst [63])))) // result: (SRAD x (SUB (MOVDconst [64]) (ANDconst [63] y))) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { break } v_1_1 := v_1.Args[1] if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { break } _ = v_1_1.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { y := v_1_1.Args[_i0] v_1_1_1 := v_1_1.Args[1^_i0] if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 63 { continue } v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) v1.AuxInt = 64 v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) v2.AuxInt = 63 v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) return true } break } // match: (Rsh64x64 x y) // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v2.AddArg(y) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh64x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SRAD x y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAD) v.AddArg(x) v.AddArg(y) return true } // match: (Rsh64x8 x y) // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAD) v.AddArg(x) v0 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v0.AddArg(y) v1 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v2 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v2.AuxInt = -64 v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValuePPC64_OpRsh8Ux16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVBZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8Ux16 x y) // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8Ux32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux32 x (Const64 [c])) // cond: uint32(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux32 x (MOVDconst [c])) // cond: uint32(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVBZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8Ux32 x y) // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8Ux64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux64 _ (Const64 [c])) // cond: uint64(c) >= 8 // result: (MOVDconst [0]) for { _ = v.Args[1] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpPPC64MOVDconst) v.AuxInt = 0 return true } // match: (Rsh8Ux64 x (MOVDconst [c])) // cond: uint64(c) < 8 // result: (SRWconst (ZeroExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVBZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8Ux64 x y) // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8Ux8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SRW (MOVBZreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBZreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8Ux8 x y) // result: (SRW (ZeroExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x16_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVBreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8x16 x y) // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x32_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x32 x (Const64 [c])) // cond: uint32(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x32 x (MOVDconst [c])) // cond: uint32(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint32(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVBreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8x32 x y) // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x64_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x64 x (Const64 [c])) // cond: uint64(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x64 x (Const64 [c])) // cond: uint64(c) >= 8 // result: (SRAWconst (SignExt8to32 x) [63]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpConst64 { break } c := v_1.AuxInt if !(uint64(c) >= 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x64 x (MOVDconst [c])) // cond: uint64(c) < 8 // result: (SRAWconst (SignExt8to32 x) [c]) for { _ = v.Args[1] x := v.Args[0] v_1 := v.Args[1] if v_1.Op != OpPPC64MOVDconst { break } c := v_1.AuxInt if !(uint64(c) < 8) { break } v.reset(OpPPC64SRAWconst) v.AuxInt = c v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVBreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8x64 x y) // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] y)))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpRsh8x8_0(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SRAW (MOVBreg x) y) for { y := v.Args[1] x := v.Args[0] if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpPPC64MOVBreg, typ.Int64) v0.AddArg(x) v.AddArg(v0) v.AddArg(y) return true } // match: (Rsh8x8 x y) // result: (SRAW (SignExt8to32 x) (ORN y (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SRAW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v.AddArg(v0) v1 := b.NewValue0(v.Pos, OpPPC64ORN, typ.Int64) v1.AddArg(y) v2 := b.NewValue0(v.Pos, OpPPC64MaskIfNotCarry, typ.Int64) v3 := b.NewValue0(v.Pos, OpPPC64ADDconstForCarry, types.TypeFlags) v3.AuxInt = -8 v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v2.AddArg(v3) v1.AddArg(v2) v.AddArg(v1) return true } } func rewriteValuePPC64_OpSignExt16to32_0(v *Value) bool { // match: (SignExt16to32 x) // result: (MOVHreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt16to64_0(v *Value) bool { // match: (SignExt16to64 x) // result: (MOVHreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt32to64_0(v *Value) bool { // match: (SignExt32to64 x) // result: (MOVWreg x) for { x := v.Args[0] v.reset(OpPPC64MOVWreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt8to16_0(v *Value) bool { // match: (SignExt8to16 x) // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt8to32_0(v *Value) bool { // match: (SignExt8to32 x) // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSignExt8to64_0(v *Value) bool { // match: (SignExt8to64 x) // result: (MOVBreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpSlicemask_0(v *Value) bool { b := v.Block // match: (Slicemask x) // result: (SRADconst (NEG x) [63]) for { t := v.Type x := v.Args[0] v.reset(OpPPC64SRADconst) v.AuxInt = 63 v0 := b.NewValue0(v.Pos, OpPPC64NEG, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpSqrt_0(v *Value) bool { // match: (Sqrt x) // result: (FSQRT x) for { x := v.Args[0] v.reset(OpPPC64FSQRT) v.AddArg(x) return true } } func rewriteValuePPC64_OpStaticCall_0(v *Value) bool { // match: (StaticCall [argwid] {target} mem) // result: (CALLstatic [argwid] {target} mem) for { argwid := v.AuxInt target := v.Aux mem := v.Args[0] v.reset(OpPPC64CALLstatic) v.AuxInt = argwid v.Aux = target v.AddArg(mem) return true } } func rewriteValuePPC64_OpStore_0(v *Value) bool { // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) // result: (FMOVDstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8 && is64BitFloat(val.Type)) { break } v.reset(OpPPC64FMOVDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && is32BitFloat(val.Type) // result: (FMOVDstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8 && is32BitFloat(val.Type)) { break } v.reset(OpPPC64FMOVDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) // result: (FMOVSstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 4 && is32BitFloat(val.Type)) { break } v.reset(OpPPC64FMOVSstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 8 && (is64BitInt(val.Type) || isPtr(val.Type)) // result: (MOVDstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 8 && (is64BitInt(val.Type) || isPtr(val.Type))) { break } v.reset(OpPPC64MOVDstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 4 && is32BitInt(val.Type) // result: (MOVWstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 4 && is32BitInt(val.Type)) { break } v.reset(OpPPC64MOVWstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 2 // result: (MOVHstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 2) { break } v.reset(OpPPC64MOVHstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } // match: (Store {t} ptr val mem) // cond: t.(*types.Type).Size() == 1 // result: (MOVBstore ptr val mem) for { t := v.Aux mem := v.Args[2] ptr := v.Args[0] val := v.Args[1] if !(t.(*types.Type).Size() == 1) { break } v.reset(OpPPC64MOVBstore) v.AddArg(ptr) v.AddArg(val) v.AddArg(mem) return true } return false } func rewriteValuePPC64_OpSub16_0(v *Value) bool { // match: (Sub16 x y) // result: (SUB x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub32_0(v *Value) bool { // match: (Sub32 x y) // result: (SUB x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub32F_0(v *Value) bool { // match: (Sub32F x y) // result: (FSUBS x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FSUBS) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub64_0(v *Value) bool { // match: (Sub64 x y) // result: (SUB x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub64F_0(v *Value) bool { // match: (Sub64F x y) // result: (FSUB x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64FSUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSub8_0(v *Value) bool { // match: (Sub8 x y) // result: (SUB x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpSubPtr_0(v *Value) bool { // match: (SubPtr x y) // result: (SUB x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64SUB) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpTrunc_0(v *Value) bool { // match: (Trunc x) // result: (FTRUNC x) for { x := v.Args[0] v.reset(OpPPC64FTRUNC) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc16to8_0(v *Value) bool { // match: (Trunc16to8 x) // cond: isSigned(t) // result: (MOVBreg x) for { t := v.Type x := v.Args[0] if !(isSigned(t)) { break } v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } // match: (Trunc16to8 x) // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc32to16_0(v *Value) bool { // match: (Trunc32to16 x) // cond: isSigned(t) // result: (MOVHreg x) for { t := v.Type x := v.Args[0] if !(isSigned(t)) { break } v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } // match: (Trunc32to16 x) // result: (MOVHZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc32to8_0(v *Value) bool { // match: (Trunc32to8 x) // cond: isSigned(t) // result: (MOVBreg x) for { t := v.Type x := v.Args[0] if !(isSigned(t)) { break } v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } // match: (Trunc32to8 x) // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc64to16_0(v *Value) bool { // match: (Trunc64to16 x) // cond: isSigned(t) // result: (MOVHreg x) for { t := v.Type x := v.Args[0] if !(isSigned(t)) { break } v.reset(OpPPC64MOVHreg) v.AddArg(x) return true } // match: (Trunc64to16 x) // result: (MOVHZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc64to32_0(v *Value) bool { // match: (Trunc64to32 x) // cond: isSigned(t) // result: (MOVWreg x) for { t := v.Type x := v.Args[0] if !(isSigned(t)) { break } v.reset(OpPPC64MOVWreg) v.AddArg(x) return true } // match: (Trunc64to32 x) // result: (MOVWZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVWZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpTrunc64to8_0(v *Value) bool { // match: (Trunc64to8 x) // cond: isSigned(t) // result: (MOVBreg x) for { t := v.Type x := v.Args[0] if !(isSigned(t)) { break } v.reset(OpPPC64MOVBreg) v.AddArg(x) return true } // match: (Trunc64to8 x) // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpWB_0(v *Value) bool { // match: (WB {fn} destptr srcptr mem) // result: (LoweredWB {fn} destptr srcptr mem) for { fn := v.Aux mem := v.Args[2] destptr := v.Args[0] srcptr := v.Args[1] v.reset(OpPPC64LoweredWB) v.Aux = fn v.AddArg(destptr) v.AddArg(srcptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpXor16_0(v *Value) bool { // match: (Xor16 x y) // result: (XOR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpXor32_0(v *Value) bool { // match: (Xor32 x y) // result: (XOR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpXor64_0(v *Value) bool { // match: (Xor64 x y) // result: (XOR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpXor8_0(v *Value) bool { // match: (Xor8 x y) // result: (XOR x y) for { y := v.Args[1] x := v.Args[0] v.reset(OpPPC64XOR) v.AddArg(x) v.AddArg(y) return true } } func rewriteValuePPC64_OpZero_0(v *Value) bool { b := v.Block // match: (Zero [0] _ mem) // result: mem for { if v.AuxInt != 0 { break } mem := v.Args[1] v.reset(OpCopy) v.Type = mem.Type v.AddArg(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstorezero destptr mem) for { if v.AuxInt != 1 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVBstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [2] destptr mem) // result: (MOVHstorezero destptr mem) for { if v.AuxInt != 2 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVHstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstorezero [2] destptr (MOVHstorezero destptr mem)) for { if v.AuxInt != 3 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVBstorezero) v.AuxInt = 2 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVHstorezero, types.TypeMem) v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [4] destptr mem) // result: (MOVWstorezero destptr mem) for { if v.AuxInt != 4 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVWstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [5] destptr mem) // result: (MOVBstorezero [4] destptr (MOVWstorezero destptr mem)) for { if v.AuxInt != 5 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVBstorezero) v.AuxInt = 4 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [6] destptr mem) // result: (MOVHstorezero [4] destptr (MOVWstorezero destptr mem)) for { if v.AuxInt != 6 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVHstorezero) v.AuxInt = 4 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [7] destptr mem) // result: (MOVBstorezero [6] destptr (MOVHstorezero [4] destptr (MOVWstorezero destptr mem))) for { if v.AuxInt != 7 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVBstorezero) v.AuxInt = 6 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVHstorezero, types.TypeMem) v0.AuxInt = 4 v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [8] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero destptr mem) for { if v.AuxInt != 8 { break } t := v.Aux mem := v.Args[1] destptr := v.Args[0] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AddArg(destptr) v.AddArg(mem) return true } // match: (Zero [8] destptr mem) // result: (MOVWstorezero [4] destptr (MOVWstorezero [0] destptr mem)) for { if v.AuxInt != 8 { break } mem := v.Args[1] destptr := v.Args[0] v.reset(OpPPC64MOVWstorezero) v.AuxInt = 4 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVWstorezero, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } return false } func rewriteValuePPC64_OpZero_10(v *Value) bool { b := v.Block // match: (Zero [12] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVWstorezero [8] destptr (MOVDstorezero [0] destptr mem)) for { if v.AuxInt != 12 { break } t := v.Aux mem := v.Args[1] destptr := v.Args[0] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVWstorezero) v.AuxInt = 8 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [16] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem)) for { if v.AuxInt != 16 { break } t := v.Aux mem := v.Args[1] destptr := v.Args[0] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = 8 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 0 v0.AddArg(destptr) v0.AddArg(mem) v.AddArg(v0) return true } // match: (Zero [24] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero [16] destptr (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem))) for { if v.AuxInt != 24 { break } t := v.Aux mem := v.Args[1] destptr := v.Args[0] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = 16 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 8 v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v1.AuxInt = 0 v1.AddArg(destptr) v1.AddArg(mem) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [32] {t} destptr mem) // cond: t.(*types.Type).Alignment()%4 == 0 // result: (MOVDstorezero [24] destptr (MOVDstorezero [16] destptr (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem)))) for { if v.AuxInt != 32 { break } t := v.Aux mem := v.Args[1] destptr := v.Args[0] if !(t.(*types.Type).Alignment()%4 == 0) { break } v.reset(OpPPC64MOVDstorezero) v.AuxInt = 24 v.AddArg(destptr) v0 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v0.AuxInt = 16 v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v1.AuxInt = 8 v1.AddArg(destptr) v2 := b.NewValue0(v.Pos, OpPPC64MOVDstorezero, types.TypeMem) v2.AuxInt = 0 v2.AddArg(destptr) v2.AddArg(mem) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Zero [s] ptr mem) // result: (LoweredZero [s] ptr mem) for { s := v.AuxInt mem := v.Args[1] ptr := v.Args[0] v.reset(OpPPC64LoweredZero) v.AuxInt = s v.AddArg(ptr) v.AddArg(mem) return true } } func rewriteValuePPC64_OpZeroExt16to32_0(v *Value) bool { // match: (ZeroExt16to32 x) // result: (MOVHZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt16to64_0(v *Value) bool { // match: (ZeroExt16to64 x) // result: (MOVHZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVHZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt32to64_0(v *Value) bool { // match: (ZeroExt32to64 x) // result: (MOVWZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVWZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt8to16_0(v *Value) bool { // match: (ZeroExt8to16 x) // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt8to32_0(v *Value) bool { // match: (ZeroExt8to32 x) // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteValuePPC64_OpZeroExt8to64_0(v *Value) bool { // match: (ZeroExt8to64 x) // result: (MOVBZreg x) for { x := v.Args[0] v.reset(OpPPC64MOVBZreg) v.AddArg(x) return true } } func rewriteBlockPPC64(b *Block) bool { switch b.Kind { case BlockPPC64EQ: // match: (EQ (CMPconst [0] (ANDconst [c] x)) yes no) // result: (EQ (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (EQ (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagLT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpPPC64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockPPC64EQ) b.AddControl(cmp) return true } // match: (EQ (CMPconst [0] (ANDconst [c] x)) yes no) // result: (EQ (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (EQ (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (EQ (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (EQ (ANDCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64AND { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (EQ (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 // result: (EQ (ORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64OR { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (EQ (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 // result: (EQ (XORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64XOR { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64EQ) v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } case BlockPPC64GE: // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagLT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagGT { b.Reset(BlockFirst) return true } // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpPPC64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockPPC64LE) b.AddControl(cmp) return true } // match: (GE (CMPconst [0] (ANDconst [c] x)) yes no) // result: (GE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64GE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (GE (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (GE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64GE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (GE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GE (ANDCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64AND { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64GE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (GE (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 // result: (GE (ORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64OR { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64GE) v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (GE (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 // result: (GE (XORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64XOR { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64GE) v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } case BlockPPC64GT: // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagLT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagGT { b.Reset(BlockFirst) return true } // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpPPC64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockPPC64LT) b.AddControl(cmp) return true } // match: (GT (CMPconst [0] (ANDconst [c] x)) yes no) // result: (GT (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64GT) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (GT (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (GT (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64GT) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (GT (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GT (ANDCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64AND { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64GT) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (GT (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 // result: (GT (ORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64OR { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64GT) v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (GT (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 // result: (GT (XORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64XOR { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64GT) v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } case BlockIf: // match: (If (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpPPC64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64EQ) b.AddControl(cc) return true } // match: (If (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpPPC64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64NE) b.AddControl(cc) return true } // match: (If (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpPPC64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64LT) b.AddControl(cc) return true } // match: (If (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpPPC64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64LE) b.AddControl(cc) return true } // match: (If (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpPPC64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64GT) b.AddControl(cc) return true } // match: (If (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpPPC64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64GE) b.AddControl(cc) return true } // match: (If (FLessThan cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpPPC64FLessThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64FLT) b.AddControl(cc) return true } // match: (If (FLessEqual cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpPPC64FLessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64FLE) b.AddControl(cc) return true } // match: (If (FGreaterThan cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpPPC64FGreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64FGT) b.AddControl(cc) return true } // match: (If (FGreaterEqual cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpPPC64FGreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.Reset(BlockPPC64FGE) b.AddControl(cc) return true } // match: (If cond yes no) // result: (NE (CMPWconst [0] cond) yes no) for { cond := b.Controls[0] b.Reset(BlockPPC64NE) v0 := b.NewValue0(cond.Pos, OpPPC64CMPWconst, types.TypeFlags) v0.AuxInt = 0 v0.AddArg(cond) b.AddControl(v0) return true } case BlockPPC64LE: // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagLT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpPPC64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockPPC64GE) b.AddControl(cmp) return true } // match: (LE (CMPconst [0] (ANDconst [c] x)) yes no) // result: (LE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64LE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (LE (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (LE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64LE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (LE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LE (ANDCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64AND { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64LE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (LE (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 // result: (LE (ORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64OR { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64LE) v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (LE (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 // result: (LE (XORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64XOR { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64LE) v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } case BlockPPC64LT: // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagLT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpPPC64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockPPC64GT) b.AddControl(cmp) return true } // match: (LT (CMPconst [0] (ANDconst [c] x)) yes no) // result: (LT (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64LT) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (LT (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (LT (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64LT) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (LT (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LT (ANDCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64AND { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64LT) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (LT (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 // result: (LT (ORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64OR { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64LT) v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (LT (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 // result: (LT (XORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64XOR { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64LT) v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } case BlockPPC64NE: // match: (NE (CMPWconst [0] (Equal cc)) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64Equal { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64EQ) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (NotEqual cc)) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64NotEqual { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64NE) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (LessThan cc)) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64LessThan { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64LT) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (LessEqual cc)) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64LessEqual { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64LE) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (GreaterThan cc)) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64GreaterThan { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64GT) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (GreaterEqual cc)) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64GreaterEqual { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64GE) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (FLessThan cc)) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64FLessThan { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64FLT) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (FLessEqual cc)) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64FLessEqual { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64FLE) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (FGreaterThan cc)) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64FGreaterThan { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64FGT) b.AddControl(cc) return true } // match: (NE (CMPWconst [0] (FGreaterEqual cc)) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64FGreaterEqual { break } cc := v_0_0.Args[0] b.Reset(BlockPPC64FGE) b.AddControl(cc) return true } // match: (NE (CMPconst [0] (ANDconst [c] x)) yes no) // result: (NE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (NE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpPPC64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagLT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpPPC64FlagGT { b.Reset(BlockFirst) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpPPC64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.Reset(BlockPPC64NE) b.AddControl(cmp) return true } // match: (NE (CMPconst [0] (ANDconst [c] x)) yes no) // result: (NE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (CMPWconst [0] (ANDconst [c] x)) yes no) // result: (NE (ANDCCconst [c] x) yes no) for b.Controls[0].Op == OpPPC64CMPWconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64ANDconst { break } c := v_0_0.AuxInt x := v_0_0.Args[0] b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCCconst, types.TypeFlags) v0.AuxInt = c v0.AddArg(x) b.AddControl(v0) return true } // match: (NE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (NE (ANDCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64AND { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (NE (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 // result: (NE (ORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64OR { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } // match: (NE (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 // result: (NE (XORCC x y) yes no) for b.Controls[0].Op == OpPPC64CMPconst { v_0 := b.Controls[0] if v_0.AuxInt != 0 { break } z := v_0.Args[0] if z.Op != OpPPC64XOR { break } _ = z.Args[1] for _i0 := 0; _i0 <= 1; _i0++ { x := z.Args[_i0] y := z.Args[1^_i0] if !(z.Uses == 1) { continue } b.Reset(BlockPPC64NE) v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) v0.AddArg(x) v0.AddArg(y) b.AddControl(v0) return true } break } } return false } -- diff -- @@ -404,7 +404,7 @@ case OpPPC64ADDconst: return rewriteValuePPC64_OpPPC64ADDconst_0(v) case OpPPC64AND: - return rewriteValuePPC64_OpPPC64AND_0(v) || rewriteValuePPC64_OpPPC64AND_10(v) + return rewriteValuePPC64_OpPPC64AND_0(v) case OpPPC64ANDconst: return rewriteValuePPC64_OpPPC64ANDconst_0(v) || rewriteValuePPC64_OpPPC64ANDconst_10(v) case OpPPC64CMP: @@ -546,7 +546,7 @@ case OpPPC64NotEqual: return rewriteValuePPC64_OpPPC64NotEqual_0(v) case OpPPC64OR: - return rewriteValuePPC64_OpPPC64OR_0(v) || rewriteValuePPC64_OpPPC64OR_10(v) || rewriteValuePPC64_OpPPC64OR_20(v) || rewriteValuePPC64_OpPPC64OR_30(v) || rewriteValuePPC64_OpPPC64OR_40(v) || rewriteValuePPC64_OpPPC64OR_50(v) || rewriteValuePPC64_OpPPC64OR_60(v) || rewriteValuePPC64_OpPPC64OR_70(v) || rewriteValuePPC64_OpPPC64OR_80(v) || rewriteValuePPC64_OpPPC64OR_90(v) || rewriteValuePPC64_OpPPC64OR_100(v) || rewriteValuePPC64_OpPPC64OR_110(v) + return rewriteValuePPC64_OpPPC64OR_0(v) || rewriteValuePPC64_OpPPC64OR_10(v) || rewriteValuePPC64_OpPPC64OR_20(v) case OpPPC64ORN: return rewriteValuePPC64_OpPPC64ORN_0(v) case OpPPC64ORconst: @@ -558,7 +558,7 @@ case OpPPC64SUB: return rewriteValuePPC64_OpPPC64SUB_0(v) case OpPPC64XOR: - return rewriteValuePPC64_OpPPC64XOR_0(v) || rewriteValuePPC64_OpPPC64XOR_10(v) + return rewriteValuePPC64_OpPPC64XOR_0(v) case OpPPC64XORconst: return rewriteValuePPC64_OpPPC64XORconst_0(v) case OpPanicBounds: @@ -606,7 +606,7 @@ case OpRsh32Ux32: return rewriteValuePPC64_OpRsh32Ux32_0(v) case OpRsh32Ux64: - return rewriteValuePPC64_OpRsh32Ux64_0(v) || rewriteValuePPC64_OpRsh32Ux64_10(v) + return rewriteValuePPC64_OpRsh32Ux64_0(v) case OpRsh32Ux8: return rewriteValuePPC64_OpRsh32Ux8_0(v) case OpRsh32x16: @@ -614,7 +614,7 @@ case OpRsh32x32: return rewriteValuePPC64_OpRsh32x32_0(v) case OpRsh32x64: - return rewriteValuePPC64_OpRsh32x64_0(v) || rewriteValuePPC64_OpRsh32x64_10(v) + return rewriteValuePPC64_OpRsh32x64_0(v) case OpRsh32x8: return rewriteValuePPC64_OpRsh32x8_0(v) case OpRsh64Ux16: @@ -622,7 +622,7 @@ case OpRsh64Ux32: return rewriteValuePPC64_OpRsh64Ux32_0(v) case OpRsh64Ux64: - return rewriteValuePPC64_OpRsh64Ux64_0(v) || rewriteValuePPC64_OpRsh64Ux64_10(v) + return rewriteValuePPC64_OpRsh64Ux64_0(v) case OpRsh64Ux8: return rewriteValuePPC64_OpRsh64Ux8_0(v) case OpRsh64x16: @@ -630,7 +630,7 @@ case OpRsh64x32: return rewriteValuePPC64_OpRsh64x32_0(v) case OpRsh64x64: - return rewriteValuePPC64_OpRsh64x64_0(v) || rewriteValuePPC64_OpRsh64x64_10(v) + return rewriteValuePPC64_OpRsh64x64_0(v) case OpRsh64x8: return rewriteValuePPC64_OpRsh64x8_0(v) case OpRsh8Ux16: @@ -1832,41 +1832,25 @@ // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { - y := v.Args[1] - x := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break - } - v.reset(OpPPC64Equal) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Eq16 y x) - // cond: isSigned(x.Type) && isSigned(y.Type) - // result: (Equal (CMPW (SignExt16to32 x) (SignExt16to32 y))) - for { - x := v.Args[1] - y := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break + _ = v.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + y := v.Args[1^_i0] + if !(isSigned(x.Type) && isSigned(y.Type)) { + continue + } + v.reset(OpPPC64Equal) + v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v.reset(OpPPC64Equal) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } // match: (Eq16 x y) // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) @@ -1952,41 +1936,25 @@ // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { - y := v.Args[1] - x := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break - } - v.reset(OpPPC64Equal) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Eq8 y x) - // cond: isSigned(x.Type) && isSigned(y.Type) - // result: (Equal (CMPW (SignExt8to32 x) (SignExt8to32 y))) - for { - x := v.Args[1] - y := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break + _ = v.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + y := v.Args[1^_i0] + if !(isSigned(x.Type) && isSigned(y.Type)) { + continue + } + v.reset(OpPPC64Equal) + v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v.reset(OpPPC64Equal) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } // match: (Eq8 x y) // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) @@ -3480,40 +3448,21 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { - break - } - v.reset(OpPPC64SLW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) - v0.AuxInt = 31 - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (Lsh32x64 x (AND (MOVDconst [31]) y)) - // result: (SLW x (ANDconst [31] y)) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64AND { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1.Args[_i0] + v_1_1 := v_1.Args[1^_i0] + if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { + continue + } + v.reset(OpPPC64SLW) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) + v0.AuxInt = 31 + v0.AddArg(y) + v.AddArg(v0) + return true } - v.reset(OpPPC64SLW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) - v0.AuxInt = 31 - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (Lsh32x64 x (ANDconst [31] y)) // result: (SLW x (ANDconst [31] y)) @@ -3786,40 +3735,21 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { - break - } - v.reset(OpPPC64SLD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) - v0.AuxInt = 63 - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (Lsh64x64 x (AND (MOVDconst [63]) y)) - // result: (SLD x (ANDconst [63] y)) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64AND { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1.Args[_i0] + v_1_1 := v_1.Args[1^_i0] + if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { + continue + } + v.reset(OpPPC64SLD) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) + v0.AuxInt = 63 + v0.AddArg(y) + v.AddArg(v0) + return true } - v.reset(OpPPC64SLD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) - v0.AuxInt = 63 - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (Lsh64x64 x (ANDconst [63] y)) // result: (SLD x (ANDconst [63] y)) @@ -4701,41 +4631,25 @@ // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { - y := v.Args[1] - x := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break - } - v.reset(OpPPC64NotEqual) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Neq16 y x) - // cond: isSigned(x.Type) && isSigned(y.Type) - // result: (NotEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) - for { - x := v.Args[1] - y := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break + _ = v.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + y := v.Args[1^_i0] + if !(isSigned(x.Type) && isSigned(y.Type)) { + continue + } + v.reset(OpPPC64NotEqual) + v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v.reset(OpPPC64NotEqual) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } // match: (Neq16 x y) // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) @@ -4821,41 +4735,25 @@ // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { - y := v.Args[1] - x := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break - } - v.reset(OpPPC64NotEqual) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Neq8 y x) - // cond: isSigned(x.Type) && isSigned(y.Type) - // result: (NotEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) - for { - x := v.Args[1] - y := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break + _ = v.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + y := v.Args[1^_i0] + if !(isSigned(x.Type) && isSigned(y.Type)) { + continue + } + v.reset(OpPPC64NotEqual) + v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v.reset(OpPPC64NotEqual) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } // match: (Neq8 x y) // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) @@ -5008,297 +4906,164 @@ // result: (ROTLconst [c] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLDconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRDconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpPPC64ROTLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADD (SRDconst x [d]) (SLDconst x [c])) - // cond: d == 64-c - // result: (ROTLconst [c] x) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLDconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRDconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 64-c) { + continue + } + v.reset(OpPPC64ROTLconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLDconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpPPC64ROTLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADD (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLWconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRWconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLWconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRWconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 32-c) { + continue + } + v.reset(OpPPC64ROTLWconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpPPC64ROTLWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADD (SRWconst x [d]) (SLWconst x [c])) - // cond: d == 32-c - // result: (ROTLWconst [c] x) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRWconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLWconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpPPC64ROTLWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADD (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // result: (ROTL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLD { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRD { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { - break - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADD (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) - // result: (ROTL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRD { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLD { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRD { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { + continue + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { + continue + } + v.reset(OpPPC64ROTL) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { - break - } - _ = v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 63 { - break - } - y := v_0_1_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLD { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int64 || v_1_1.AuxInt != 63 || y != v_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADD (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // result: (ROTLW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLW { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { - break - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADD (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) - // result: (ROTLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRW { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRW { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { + continue + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { + continue + } + v.reset(OpPPC64ROTLW) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { - break - } - _ = v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 31 { - break - } - y := v_0_1_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int32 || v_1_1.AuxInt != 31 || y != v_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTLW) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADD x (MOVDconst [c])) // cond: is32Bit(c) // result: (ADDconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpPPC64ADDconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADD (MOVDconst [c]) x) - // cond: is32Bit(c) - // result: (ADDconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpPPC64ADDconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpPPC64ADDconst) - v.AuxInt = c - v.AddArg(x) - return true + break } return false } @@ -5358,225 +5123,129 @@ // result: (ANDN x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64NOR { - break - } - y := v_1.Args[1] - if y != v_1.Args[0] { - break - } - v.reset(OpPPC64ANDN) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (AND (NOR y y) x) - // result: (ANDN x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64NOR { - break - } - y := v_0.Args[1] - if y != v_0.Args[0] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64NOR { + continue + } + y := v_1.Args[1] + if y != v_1.Args[0] { + continue + } + v.reset(OpPPC64ANDN) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpPPC64ANDN) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (AND (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c&d]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - c := v_0.AuxInt - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64MOVDconst { + continue + } + c := v_0.AuxInt + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + d := v_1.AuxInt + v.reset(OpPPC64MOVDconst) + v.AuxInt = c & d + return true } - d := v_1.AuxInt - v.reset(OpPPC64MOVDconst) - v.AuxInt = c & d - return true - } - // match: (AND (MOVDconst [d]) (MOVDconst [c])) - // result: (MOVDconst [c&d]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - d := v_0.AuxInt - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - v.reset(OpPPC64MOVDconst) - v.AuxInt = c & d - return true + break } // match: (AND x (MOVDconst [c])) // cond: isU16Bit(c) // result: (ANDconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - if !(isU16Bit(c)) { - break - } - v.reset(OpPPC64ANDconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (AND (MOVDconst [c]) x) - // cond: isU16Bit(c) - // result: (ANDconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - c := v_0.AuxInt - if !(isU16Bit(c)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + c := v_1.AuxInt + if !(isU16Bit(c)) { + continue + } + v.reset(OpPPC64ANDconst) + v.AuxInt = c + v.AddArg(x) + return true } - v.reset(OpPPC64ANDconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (AND (MOVDconst [c]) y:(MOVWZreg _)) // cond: c&0xFFFFFFFF == 0xFFFFFFFF // result: y for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - c := v_0.AuxInt - y := v.Args[1] - if y.Op != OpPPC64MOVWZreg || !(c&0xFFFFFFFF == 0xFFFFFFFF) { - break - } - v.reset(OpCopy) - v.Type = y.Type - v.AddArg(y) - return true - } - // match: (AND y:(MOVWZreg _) (MOVDconst [c])) - // cond: c&0xFFFFFFFF == 0xFFFFFFFF - // result: y - for { - _ = v.Args[1] - y := v.Args[0] - if y.Op != OpPPC64MOVWZreg { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64MOVDconst { + continue + } + c := v_0.AuxInt + y := v.Args[1^_i0] + if y.Op != OpPPC64MOVWZreg || !(c&0xFFFFFFFF == 0xFFFFFFFF) { + continue + } + v.reset(OpCopy) + v.Type = y.Type + v.AddArg(y) + return true } - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - if !(c&0xFFFFFFFF == 0xFFFFFFFF) { - break - } - v.reset(OpCopy) - v.Type = y.Type - v.AddArg(y) - return true + break } // match: (AND (MOVDconst [0xFFFFFFFF]) y:(MOVWreg x)) // result: (MOVWZreg x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst || v_0.AuxInt != 0xFFFFFFFF { - break - } - y := v.Args[1] - if y.Op != OpPPC64MOVWreg { - break - } - x := y.Args[0] - v.reset(OpPPC64MOVWZreg) - v.AddArg(x) - return true - } - // match: (AND y:(MOVWreg x) (MOVDconst [0xFFFFFFFF])) - // result: (MOVWZreg x) - for { - _ = v.Args[1] - y := v.Args[0] - if y.Op != OpPPC64MOVWreg { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64MOVDconst || v_0.AuxInt != 0xFFFFFFFF { + continue + } + y := v.Args[1^_i0] + if y.Op != OpPPC64MOVWreg { + continue + } + x := y.Args[0] + v.reset(OpPPC64MOVWZreg) + v.AddArg(x) + return true } - x := y.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst || v_1.AuxInt != 0xFFFFFFFF { - break - } - v.reset(OpPPC64MOVWZreg) - v.AddArg(x) - return true + break } - return false -} -func rewriteValuePPC64_OpPPC64AND_10(v *Value) bool { // match: (AND (MOVDconst [c]) x:(MOVBZload _ _)) // result: (ANDconst [c&0xFF] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - c := v_0.AuxInt - x := v.Args[1] - if x.Op != OpPPC64MOVBZload { - break - } - _ = x.Args[1] - v.reset(OpPPC64ANDconst) - v.AuxInt = c & 0xFF - v.AddArg(x) - return true - } - // match: (AND x:(MOVBZload _ _) (MOVDconst [c])) - // result: (ANDconst [c&0xFF] x) - for { - _ = v.Args[1] - x := v.Args[0] - if x.Op != OpPPC64MOVBZload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64MOVDconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if x.Op != OpPPC64MOVBZload { + continue + } + _ = x.Args[1] + v.reset(OpPPC64ANDconst) + v.AuxInt = c & 0xFF + v.AddArg(x) + return true } - _ = x.Args[1] - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - v.reset(OpPPC64ANDconst) - v.AuxInt = c & 0xFF - v.AddArg(x) - return true + break } return false } @@ -6279,35 +5948,22 @@ // match: (FADD (FMUL x y) z) // result: (FMADD x y z) for { - z := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64FMUL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v.reset(OpPPC64FMADD) - v.AddArg(x) - v.AddArg(y) - v.AddArg(z) - return true - } - // match: (FADD z (FMUL x y)) - // result: (FMADD x y z) - for { _ = v.Args[1] - z := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64FMUL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64FMUL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v.Args[1^_i0] + v.reset(OpPPC64FMADD) + v.AddArg(x) + v.AddArg(y) + v.AddArg(z) + return true } - y := v_1.Args[1] - x := v_1.Args[0] - v.reset(OpPPC64FMADD) - v.AddArg(x) - v.AddArg(y) - v.AddArg(z) - return true + break } return false } @@ -6315,35 +5971,22 @@ // match: (FADDS (FMULS x y) z) // result: (FMADDS x y z) for { - z := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64FMULS { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v.reset(OpPPC64FMADDS) - v.AddArg(x) - v.AddArg(y) - v.AddArg(z) - return true - } - // match: (FADDS z (FMULS x y)) - // result: (FMADDS x y z) - for { _ = v.Args[1] - z := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64FMULS { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64FMULS { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v.Args[1^_i0] + v.reset(OpPPC64FMADDS) + v.AddArg(x) + v.AddArg(y) + v.AddArg(z) + return true } - y := v_1.Args[1] - x := v_1.Args[0] - v.reset(OpPPC64FMADDS) - v.AddArg(x) - v.AddArg(y) - v.AddArg(z) - return true + break } return false } @@ -11268,40 +10911,21 @@ break } _ = y.Args[1] - y_0 := y.Args[0] - if y_0.Op != OpPPC64MOVDconst { - break - } - c := y_0.AuxInt - if !(uint64(c) <= 0xFFFFFFFF) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y_0 := y.Args[_i0] + if y_0.Op != OpPPC64MOVDconst { + continue + } + c := y_0.AuxInt + if !(uint64(c) <= 0xFFFFFFFF) { + continue + } + v.reset(OpCopy) + v.Type = y.Type + v.AddArg(y) + return true } - v.reset(OpCopy) - v.Type = y.Type - v.AddArg(y) - return true - } - // match: (MOVWZreg y:(AND _ (MOVDconst [c]))) - // cond: uint64(c) <= 0xFFFFFFFF - // result: y - for { - y := v.Args[0] - if y.Op != OpPPC64AND { - break - } - _ = y.Args[1] - y_1 := y.Args[1] - if y_1.Op != OpPPC64MOVDconst { - break - } - c := y_1.AuxInt - if !(uint64(c) <= 0xFFFFFFFF) { - break - } - v.reset(OpCopy) - v.Type = y.Type - v.AddArg(y) - return true + break } // match: (MOVWZreg (SRWconst [c] (MOVBZreg x))) // result: (SRWconst [c] (MOVBZreg x)) @@ -11423,9 +11047,6 @@ v.AddArg(y) return true } - return false -} -func rewriteValuePPC64_OpPPC64MOVWZreg_10(v *Value) bool { // match: (MOVWZreg y:(MOVBZreg _)) // result: y for { @@ -11438,6 +11059,9 @@ v.AddArg(y) return true } + return false +} +func rewriteValuePPC64_OpPPC64MOVWZreg_10(v *Value) bool { // match: (MOVWZreg y:(MOVHBRload _ _)) // result: y for { @@ -11554,9 +11178,6 @@ v.AddArg(x) return true } - return false -} -func rewriteValuePPC64_OpPPC64MOVWZreg_20(v *Value) bool { // match: (MOVWZreg x:(Arg )) // cond: (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !isSigned(t) // result: x @@ -11574,6 +11195,9 @@ v.AddArg(x) return true } + return false +} +func rewriteValuePPC64_OpPPC64MOVWZreg_20(v *Value) bool { // match: (MOVWZreg (MOVDconst [c])) // result: (MOVDconst [int64(uint32(c))]) for { @@ -11734,40 +11358,21 @@ break } _ = y.Args[1] - y_0 := y.Args[0] - if y_0.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y_0 := y.Args[_i0] + if y_0.Op != OpPPC64MOVDconst { + continue + } + c := y_0.AuxInt + if !(uint64(c) <= 0x7FFFFFFF) { + continue + } + v.reset(OpCopy) + v.Type = y.Type + v.AddArg(y) + return true } - c := y_0.AuxInt - if !(uint64(c) <= 0x7FFFFFFF) { - break - } - v.reset(OpCopy) - v.Type = y.Type - v.AddArg(y) - return true - } - // match: (MOVWreg y:(AND _ (MOVDconst [c]))) - // cond: uint64(c) <= 0x7FFFFFFF - // result: y - for { - y := v.Args[0] - if y.Op != OpPPC64AND { - break - } - _ = y.Args[1] - y_1 := y.Args[1] - if y_1.Op != OpPPC64MOVDconst { - break - } - c := y_1.AuxInt - if !(uint64(c) <= 0x7FFFFFFF) { - break - } - v.reset(OpCopy) - v.Type = y.Type - v.AddArg(y) - return true + break } // match: (MOVWreg (SRAWconst [c] (MOVBreg x))) // result: (SRAWconst [c] (MOVBreg x)) @@ -11895,9 +11500,6 @@ v.AddArg(y) return true } - return false -} -func rewriteValuePPC64_OpPPC64MOVWreg_10(v *Value) bool { // match: (MOVWreg y:(MOVHreg _)) // result: y for { @@ -11910,6 +11512,9 @@ v.AddArg(y) return true } + return false +} +func rewriteValuePPC64_OpPPC64MOVWreg_10(v *Value) bool { // match: (MOVWreg y:(MOVBreg _)) // result: y for { @@ -12423,345 +12028,192 @@ } func rewriteValuePPC64_OpPPC64OR_0(v *Value) bool { b := v.Block + config := b.Func.Config typ := &b.Func.Config.Types - // match: (OR (SLDconst x [c]) (SRDconst x [d])) + // match: ( OR (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLDconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRDconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 64-c) { + continue + } + v.reset(OpPPC64ROTLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRDconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpPPC64ROTLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } - // match: (OR (SRDconst x [d]) (SLDconst x [c])) - // cond: d == 64-c - // result: (ROTLconst [c] x) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRDconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLDconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpPPC64ROTLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (OR (SLWconst x [c]) (SRWconst x [d])) + // match: ( OR (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLWconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLWconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRWconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 32-c) { + continue + } + v.reset(OpPPC64ROTLWconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRWconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpPPC64ROTLWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (OR (SRWconst x [d]) (SLWconst x [c])) - // cond: d == 32-c - // result: (ROTLWconst [c] x) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRWconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLWconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpPPC64ROTLWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } - // match: (OR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) + // match: ( OR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // result: (ROTL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLD { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRD { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLD { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRD { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { + continue + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { + continue + } + v.reset(OpPPC64ROTL) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTL) - v.AddArg(x) - v.AddArg(y) - return true + break } - // match: (OR (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) - // result: (ROTL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRD { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { - break - } - _ = v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 63 { - break - } - y := v_0_1_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLD { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int64 || v_1_1.AuxInt != 63 || y != v_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (OR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) + // match: ( OR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // result: (ROTLW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLW { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRW { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { + continue + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { + continue + } + v.reset(OpPPC64ROTLW) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { - break - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (OR (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) - // result: (ROTLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRW { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { - break - } - _ = v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 31 { - break - } - y := v_0_1_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int32 || v_1_1.AuxInt != 31 || y != v_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTLW) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (OR (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c|d]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64MOVDconst { + continue + } + c := v_0.AuxInt + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + d := v_1.AuxInt + v.reset(OpPPC64MOVDconst) + v.AuxInt = c | d + return true } - c := v_0.AuxInt - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - d := v_1.AuxInt - v.reset(OpPPC64MOVDconst) - v.AuxInt = c | d - return true + break } - // match: (OR (MOVDconst [d]) (MOVDconst [c])) - // result: (MOVDconst [c|d]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - d := v_0.AuxInt - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - v.reset(OpPPC64MOVDconst) - v.AuxInt = c | d - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_10(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types // match: (OR x (MOVDconst [c])) // cond: isU32Bit(c) // result: (ORconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - if !(isU32Bit(c)) { - break - } - v.reset(OpPPC64ORconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (OR (MOVDconst [c]) x) - // cond: isU32Bit(c) - // result: (ORconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + c := v_1.AuxInt + if !(isU32Bit(c)) { + continue + } + v.reset(OpPPC64ORconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - if !(isU32Bit(c)) { - break - } - v.reset(OpPPC64ORconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (OR x0:(MOVBZload [i0] {s} p mem) o1:(SLWconst x1:(MOVBZload [i1] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) @@ -12769,79 +12221,42 @@ for { t := v.Type _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o1 := v.Args[1] - if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o1 := v.Args[1^_i0] + if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { + continue + } + x1 := o1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpPPC64MOVHZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVHZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o1:(SLWconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) - // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) - // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o1 := v.Args[0] - if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVHZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (OR x0:(MOVBZload [i0] {s} p mem) o1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) @@ -12849,79 +12264,42 @@ for { t := v.Type _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o1 := v.Args[1] - if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o1 := v.Args[1^_i0] + if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { + continue + } + x1 := o1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpPPC64MOVHZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVHZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) - // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) - // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o1 := v.Args[0] - if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVHZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (OR x0:(MOVBZload [i1] {s} p mem) o1:(SLWconst x1:(MOVBZload [i0] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) @@ -12929,83 +12307,44 @@ for { t := v.Type _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o1 := v.Args[1] - if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i1 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o1 := v.Args[1^_i0] + if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { + continue + } + x1 := o1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i0 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o1:(SLWconst x1:(MOVBZload [i0] {s} p mem) [8]) x0:(MOVBZload [i1] {s} p mem)) - // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) - // result: @mergePoint(b,x0,x1) (MOVHBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o1 := v.Args[0] - if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVHBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } // match: (OR x0:(MOVBZload [i1] {s} p mem) o1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) @@ -13013,87 +12352,48 @@ for { t := v.Type _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o1 := v.Args[1] - if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i1 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o1 := v.Args[1^_i0] + if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { + continue + } + x1 := o1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i0 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true } - i0 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } - // match: (OR o1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [8]) x0:(MOVBZload [i1] {s} p mem)) - // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) - // result: @mergePoint(b,x0,x1) (MOVHBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o1 := v.Args[0] - if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVHBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } return false } -func rewriteValuePPC64_OpPPC64OR_20(v *Value) bool { +func rewriteValuePPC64_OpPPC64OR_10(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types @@ -13103,101 +12403,53 @@ for { t := v.Type _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLWconst { - break - } - n1 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpPPC64SLWconst { - break - } - n2 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = n1 - v1 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) - v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (OR s1:(SLWconst x1:(MOVBZload [i0] {s} p mem) [n2]) s0:(SLWconst x0:(MOVBZload [i1] {s} p mem) [n1])) - // cond: !config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) - // result: @mergePoint(b,x0,x1) (SLDconst (MOVHBRload (MOVDaddr [i0] {s} p) mem) [n1]) - for { - t := v.Type - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLWconst { - break - } - n2 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpPPC64SLWconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpPPC64SLWconst { + continue + } + n1 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i1 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + s1 := v.Args[1^_i0] + if s1.Op != OpPPC64SLWconst { + continue + } + n2 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i0 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = n1 + v1 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) + v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v1.AddArg(v2) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - n1 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = n1 - v1 := b.NewValue0(x0.Pos, OpPPC64MOVHBRload, t) - v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (OR s0:(SLDconst x0:(MOVBZload [i1] {s} p mem) [n1]) s1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [n2])) // cond: !config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) @@ -13205,101 +12457,53 @@ for { t := v.Type _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst { - break - } - n1 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpPPC64SLDconst { - break - } - n2 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = n1 - v1 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) - v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (OR s1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [n2]) s0:(SLDconst x0:(MOVBZload [i1] {s} p mem) [n1])) - // cond: !config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) - // result: @mergePoint(b,x0,x1) (SLDconst (MOVHBRload (MOVDaddr [i0] {s} p) mem) [n1]) - for { - t := v.Type - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLDconst { - break - } - n2 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpPPC64SLDconst { + continue + } + n1 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i1 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + s1 := v.Args[1^_i0] + if s1.Op != OpPPC64SLDconst { + continue + } + n2 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i0 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = n1 + v1 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) + v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v1.AddArg(v2) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - n1 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = n1 - v1 := b.NewValue0(x0.Pos, OpPPC64MOVHBRload, t) - v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (OR s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) @@ -13307,243 +12511,65 @@ for { t := v.Type _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHZload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { + continue + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i3 := x2.AuxInt + s := x2.Aux + mem := x2.Args[1] + p := x2.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := o0.Args[_i1] + if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { + continue + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i2 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + x0 := o0.Args[1^_i1] + if x0.Op != OpPPC64MOVHZload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x0.Pos, OpPPC64MOVWZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]))) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem)) s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24])) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16])) s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24])) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (OR s1:(SLDconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) @@ -13551,249 +12577,65 @@ for { t := v.Type _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s1:(SLDconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [16]))) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_30(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i3] {s} p mem) [24])) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { + continue + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i3 := x2.AuxInt + s := x2.Aux + mem := x2.Args[1] + p := x2.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := o0.Args[_i1] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { + continue + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i2 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + x0 := o0.Args[1^_i1] + if x0.Op != OpPPC64MOVHZload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x0.Pos, OpPPC64MOVWZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [16])) s1:(SLDconst x2:(MOVBZload [i3] {s} p mem) [24])) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (OR s1:(SLWconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR s0:(SLWconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) @@ -13801,258 +12643,68 @@ for { t := v.Type _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s1:(SLWconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) s0:(SLWconst x1:(MOVBZload [i1] {s} p mem) [16]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s0:(SLWconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem)) s1:(SLWconst x2:(MOVBZload [i0] {s} p mem) [24])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) s0:(SLWconst x1:(MOVBZload [i1] {s} p mem) [16])) s1:(SLWconst x2:(MOVBZload [i0] {s} p mem) [24])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - mem := x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - s := x0_0.Aux - p := x0_0.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { + continue + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i0 := x2.AuxInt + s := x2.Aux + mem := x2.Args[1] + p := x2.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := o0.Args[_i1] + if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { + continue + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + x0 := o0.Args[1^_i1] + if x0.Op != OpPPC64MOVHBRload || x0.Type != t { + continue + } + _ = x0.Args[1] + x0_0 := x0.Args[0] + if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { + continue + } + i2 := x0_0.AuxInt + if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } } - s1 := v.Args[1] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } // match: (OR s1:(SLDconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) @@ -14060,523 +12712,137 @@ for { t := v.Type _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { + continue + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i0 := x2.AuxInt + s := x2.Aux + mem := x2.Args[1] + p := x2.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := o0.Args[_i1] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { + continue + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + x0 := o0.Args[1^_i1] + if x0.Op != OpPPC64MOVHBRload || x0.Type != t { + continue + } + _ = x0.Args[1] + x0_0 := x0.Args[0] + if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { + continue + } + i2 := x0_0.AuxInt + if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } } - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } - // match: (OR s1:(SLDconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [16]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem)) s1:(SLDconst x2:(MOVBZload [i0] {s} p mem) [24])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [16])) s1:(SLDconst x2:(MOVBZload [i0] {s} p mem) [24])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - mem := x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - s := x0_0.Aux - p := x0_0.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_40(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLWconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - _ = x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s1:(SLWconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [8]))) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - _ = x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i3 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := o0.Args[_i1] + if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { + continue + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i2 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + s1 := o0.Args[1^_i1] + if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { + continue + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVHBRload || x2.Type != t { + continue + } + _ = x2.Args[1] + x2_0 := x2.Args[0] + if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { + continue + } + i0 := x2_0.AuxInt + if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLWconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16])) x0:(MOVBZload [i3] {s} p mem)) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s1 := o0.Args[1] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - _ = x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] { - break - } - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s1:(SLWconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [8])) x0:(MOVBZload [i3] {s} p mem)) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - mem := x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - s := x2_0.Aux - p := x2_0.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLDconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) @@ -14584,258 +12850,68 @@ for { t := v.Type _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - _ = x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s1:(SLDconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]) s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [8]))) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - _ = x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i3 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := o0.Args[_i1] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { + continue + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i2 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + s1 := o0.Args[1^_i1] + if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { + continue + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVHBRload || x2.Type != t { + continue + } + _ = x2.Args[1] + x2_0 := x2.Args[0] + if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { + continue + } + i0 := x2_0.AuxInt + if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLDconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16])) x0:(MOVBZload [i3] {s} p mem)) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - _ = x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] { - break - } - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s1:(SLDconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]) s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [8])) x0:(MOVBZload [i3] {s} p mem)) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - mem := x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - s := x2_0.Aux - p := x2_0.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } // match: (OR s2:(SLDconst x2:(MOVBZload [i3] {s} p mem) [32]) o0:(OR s1:(SLDconst x1:(MOVBZload [i2] {s} p mem) [40]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [48]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) @@ -14843,292 +12919,75 @@ for { t := v.Type _ = v.Args[1] - s2 := v.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i0 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s2 := v.Args[_i0] + if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { + continue + } + x2 := s2.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i3 := x2.AuxInt + s := x2.Aux + mem := x2.Args[1] + p := x2.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s1 := o0.Args[_i1] + if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { + continue + } + x1 := s1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i2 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + s0 := o0.Args[1^_i1] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { + continue + } + x0 := s0.Args[0] + if x0.Op != OpPPC64MOVHBRload || x0.Type != t { + continue + } + _ = x0.Args[1] + x0_0 := x0.Args[0] + if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { + continue + } + i0 := x0_0.AuxInt + if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = 32 + v1 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) + v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v1.AddArg(v2) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (OR s2:(SLDconst x2:(MOVBZload [i3] {s} p mem) [32]) o0:(OR s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [48]) s1:(SLDconst x1:(MOVBZload [i2] {s} p mem) [40]))) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) - for { - t := v.Type - _ = v.Args[1] - s2 := v.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i0 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_50(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i2] {s} p mem) [40]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [48])) s2:(SLDconst x2:(MOVBZload [i3] {s} p mem) [32])) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i0 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s2 := v.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (OR o0:(OR s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [48]) s1:(SLDconst x1:(MOVBZload [i2] {s} p mem) [40])) s2:(SLDconst x2:(MOVBZload [i3] {s} p mem) [32])) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - mem := x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i0 := x0_0.AuxInt - s := x0_0.Aux - p := x0_0.Args[0] - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s2 := v.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (OR s2:(SLDconst x2:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) [32]))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) @@ -15136,1945 +12995,193 @@ for { t := v.Type _ = v.Args[1] - s2 := v.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s2 := v.Args[_i0] + if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { + continue + } + x2 := s2.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i0 := x2.AuxInt + s := x2.Aux + mem := x2.Args[1] + p := x2.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s1 := o0.Args[_i1] + if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { + continue + } + x1 := s1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + s0 := o0.Args[1^_i1] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { + continue + } + x0 := s0.Args[0] + if x0.Op != OpPPC64MOVHBRload || x0.Type != t { + continue + } + _ = x0.Args[1] + x0_0 := x0.Args[0] + if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { + continue + } + i2 := x0_0.AuxInt + if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = 32 + v1 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) + v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v1.AddArg(v2) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } - // match: (OR s2:(SLDconst x2:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) [32]) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) - for { - t := v.Type - _ = v.Args[1] - s2 := v.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) [32])) s2:(SLDconst x2:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s2 := v.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (OR o0:(OR s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) [32]) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s2:(SLDconst x2:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - mem := x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - s := x0_0.Aux - p := x0_0.Args[0] - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s2 := v.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } + return false +} +func rewriteValuePPC64_OpPPC64OR_20(v *Value) bool { + b := v.Block + config := b.Func.Config + typ := &b.Func.Config.Types // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem))))) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x4.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x5.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x5.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_60(v *Value) bool { - b := v.Block - config := b.Func.Config - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s6 := v.Args[_i0] + if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { + continue + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + continue + } + i7 := x7.AuxInt + s := x7.Aux + mem := x7.Args[1] + p := x7.Args[0] + o5 := v.Args[1^_i0] + if o5.Op != OpPPC64OR || o5.Type != t { + continue + } + _ = o5.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s5 := o5.Args[_i1] + if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { + continue + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + continue + } + i6 := x6.AuxInt + if x6.Aux != s { + continue + } + _ = x6.Args[1] + if p != x6.Args[0] || mem != x6.Args[1] { + continue + } + o4 := o5.Args[1^_i1] + if o4.Op != OpPPC64OR || o4.Type != t { + continue + } + _ = o4.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s4 := o4.Args[_i2] + if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { + continue + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + continue + } + i5 := x5.AuxInt + if x5.Aux != s { + continue + } + _ = x5.Args[1] + if p != x5.Args[0] || mem != x5.Args[1] { + continue + } + o3 := o4.Args[1^_i2] + if o3.Op != OpPPC64OR || o3.Type != t { + continue + } + _ = o3.Args[1] + for _i3 := 0; _i3 <= 1; _i3++ { + s3 := o3.Args[_i3] + if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { + continue + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + continue + } + i4 := x4.AuxInt + if x4.Aux != s { + continue + } + _ = x4.Args[1] + if p != x4.Args[0] || mem != x4.Args[1] { + continue + } + x0 := o3.Args[1^_i3] + if x0.Op != OpPPC64MOVWZload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { + continue + } + b = mergePoint(b, x0, x4, x5, x6, x7) + v0 := b.NewValue0(x0.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + } + } } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - s := x5.Aux - mem := x5.Args[1] - p := x5.Args[0] - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - s := x5.Aux - mem := x5.Args[1] - p := x5.Args[0] - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_70(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - s := x4.Aux - mem := x4.Args[1] - p := x4.Args[0] - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem))))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) @@ -17082,1701 +13189,114 @@ for { t := v.Type _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x4.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x4.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]))))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem))) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]))) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR o1:(OR o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR o1:(OR o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_80(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)))) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { + continue + } + x0 := s0.Args[0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s1 := o0.Args[_i1] + if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { + continue + } + x1 := s1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + o1 := o0.Args[1^_i1] + if o1.Op != OpPPC64OR || o1.Type != t { + continue + } + _ = o1.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s2 := o1.Args[_i2] + if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { + continue + } + x2 := s2.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i2 := x2.AuxInt + if x2.Aux != s { + continue + } + _ = x2.Args[1] + if p != x2.Args[0] || mem != x2.Args[1] { + continue + } + o2 := o1.Args[1^_i2] + if o2.Op != OpPPC64OR || o2.Type != t { + continue + } + _ = o2.Args[1] + for _i3 := 0; _i3 <= 1; _i3++ { + s3 := o2.Args[_i3] + if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { + continue + } + x3 := s3.Args[0] + if x3.Op != OpPPC64MOVBZload { + continue + } + i3 := x3.AuxInt + if x3.Aux != s { + continue + } + _ = x3.Args[1] + if p != x3.Args[0] || mem != x3.Args[1] { + continue + } + x4 := o2.Args[1^_i3] + if x4.Op != OpPPC64MOVWBRload || x4.Type != t { + continue + } + _ = x4.Args[1] + x4_0 := x4.Args[0] + if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { + continue + } + i4 := x4_0.AuxInt + if p != x4_0.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { + continue + } + b = mergePoint(b, x0, x1, x2, x3, x4) + v0 := b.NewValue0(x4.Pos, OpPPC64MOVDBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x4.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } + } + } } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])))) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]))) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]))) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem))) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]))) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR o1:(OR o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - s := x3.Aux - mem := x3.Args[1] - p := x3.Args[0] - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR o1:(OR o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - mem := x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - p := x4_0.Args[0] - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - s := x3.Aux - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) @@ -18784,1710 +13304,114 @@ for { t := v.Type _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x7 := v.Args[_i0] + if x7.Op != OpPPC64MOVBZload { + continue + } + i7 := x7.AuxInt + s := x7.Aux + mem := x7.Args[1] + p := x7.Args[0] + o5 := v.Args[1^_i0] + if o5.Op != OpPPC64OR || o5.Type != t { + continue + } + _ = o5.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s6 := o5.Args[_i1] + if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { + continue + } + x6 := s6.Args[0] + if x6.Op != OpPPC64MOVBZload { + continue + } + i6 := x6.AuxInt + if x6.Aux != s { + continue + } + _ = x6.Args[1] + if p != x6.Args[0] || mem != x6.Args[1] { + continue + } + o4 := o5.Args[1^_i1] + if o4.Op != OpPPC64OR || o4.Type != t { + continue + } + _ = o4.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s5 := o4.Args[_i2] + if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { + continue + } + x5 := s5.Args[0] + if x5.Op != OpPPC64MOVBZload { + continue + } + i5 := x5.AuxInt + if x5.Aux != s { + continue + } + _ = x5.Args[1] + if p != x5.Args[0] || mem != x5.Args[1] { + continue + } + o3 := o4.Args[1^_i2] + if o3.Op != OpPPC64OR || o3.Type != t { + continue + } + _ = o3.Args[1] + for _i3 := 0; _i3 <= 1; _i3++ { + s4 := o3.Args[_i3] + if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { + continue + } + x4 := s4.Args[0] + if x4.Op != OpPPC64MOVBZload { + continue + } + i4 := x4.AuxInt + if x4.Aux != s { + continue + } + _ = x4.Args[1] + if p != x4.Args[0] || mem != x4.Args[1] { + continue + } + s0 := o3.Args[1^_i3] + if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { + continue + } + x3 := s0.Args[0] + if x3.Op != OpPPC64MOVWBRload || x3.Type != t { + continue + } + _ = x3.Args[1] + x3_0 := x3.Args[0] + if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { + continue + } + i0 := x3_0.AuxInt + if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { + continue + } + b = mergePoint(b, x3, x4, x5, x6, x7) + v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } + } + } } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x4.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x4.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_90(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x5.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x5.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x5.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x5.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_100(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - s := x5.Aux - mem := x5.Args[1] - p := x5.Args[0] - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - s := x5.Aux - mem := x5.Args[1] - p := x5.Args[0] - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - s := x4.Aux - mem := x4.Args[1] - p := x4.Args[0] - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - mem := x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - s := x3_0.Aux - p := x3_0.Args[0] - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) @@ -20495,1704 +13419,114 @@ for { t := v.Type _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x4.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x4.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x5.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x5.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x5.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x5.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_110(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - s := x5.Aux - mem := x5.Args[1] - p := x5.Args[0] - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - s := x5.Aux - mem := x5.Args[1] - p := x5.Args[0] - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x7 := v.Args[_i0] + if x7.Op != OpPPC64MOVBZload { + continue + } + i7 := x7.AuxInt + s := x7.Aux + mem := x7.Args[1] + p := x7.Args[0] + o5 := v.Args[1^_i0] + if o5.Op != OpPPC64OR || o5.Type != t { + continue + } + _ = o5.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s6 := o5.Args[_i1] + if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { + continue + } + x6 := s6.Args[0] + if x6.Op != OpPPC64MOVBZload { + continue + } + i6 := x6.AuxInt + if x6.Aux != s { + continue + } + _ = x6.Args[1] + if p != x6.Args[0] || mem != x6.Args[1] { + continue + } + o4 := o5.Args[1^_i1] + if o4.Op != OpPPC64OR || o4.Type != t { + continue + } + _ = o4.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s5 := o4.Args[_i2] + if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { + continue + } + x5 := s5.Args[0] + if x5.Op != OpPPC64MOVBZload { + continue + } + i5 := x5.AuxInt + if x5.Aux != s { + continue + } + _ = x5.Args[1] + if p != x5.Args[0] || mem != x5.Args[1] { + continue + } + o3 := o4.Args[1^_i2] + if o3.Op != OpPPC64OR || o3.Type != t { + continue + } + _ = o3.Args[1] + for _i3 := 0; _i3 <= 1; _i3++ { + s4 := o3.Args[_i3] + if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { + continue + } + x4 := s4.Args[0] + if x4.Op != OpPPC64MOVBZload { + continue + } + i4 := x4.AuxInt + if x4.Aux != s { + continue + } + _ = x4.Args[1] + if p != x4.Args[0] || mem != x4.Args[1] { + continue + } + s0 := o3.Args[1^_i3] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { + continue + } + x3 := s0.Args[0] + if x3.Op != OpPPC64MOVWBRload || x3.Type != t { + continue + } + _ = x3.Args[1] + x3_0 := x3.Args[0] + if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { + continue + } + i0 := x3_0.AuxInt + if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { + continue + } + b = mergePoint(b, x3, x4, x5, x6, x7) + v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } + } + } } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - s := x4.Aux - mem := x4.Args[1] - p := x4.Args[0] - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - mem := x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - s := x3_0.Aux - p := x3_0.Args[0] - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } return false } @@ -22319,336 +13653,185 @@ // result: (ROTLconst [c] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLDconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRDconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpPPC64ROTLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XOR (SRDconst x [d]) (SLDconst x [c])) - // cond: d == 64-c - // result: (ROTLconst [c] x) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLDconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRDconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 64-c) { + continue + } + v.reset(OpPPC64ROTLconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLDconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpPPC64ROTLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XOR (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLWconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRWconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLWconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRWconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 32-c) { + continue + } + v.reset(OpPPC64ROTLWconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpPPC64ROTLWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XOR (SRWconst x [d]) (SLWconst x [c])) - // cond: d == 32-c - // result: (ROTLWconst [c] x) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRWconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLWconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpPPC64ROTLWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XOR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // result: (ROTL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLD { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRD { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { - break - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (XOR (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) - // result: (ROTL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRD { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLD { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRD { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { + continue + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { + continue + } + v.reset(OpPPC64ROTL) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { - break - } - _ = v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 63 { - break - } - y := v_0_1_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLD { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int64 || v_1_1.AuxInt != 63 || y != v_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (XOR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // result: (ROTLW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLW { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { - break - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (XOR (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) - // result: (ROTLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRW { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRW { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { + continue + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { + continue + } + v.reset(OpPPC64ROTLW) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { - break - } - _ = v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 31 { - break - } - y := v_0_1_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int32 || v_1_1.AuxInt != 31 || y != v_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTLW) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (XOR (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c^d]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64MOVDconst { + continue + } + c := v_0.AuxInt + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + d := v_1.AuxInt + v.reset(OpPPC64MOVDconst) + v.AuxInt = c ^ d + return true } - c := v_0.AuxInt - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - d := v_1.AuxInt - v.reset(OpPPC64MOVDconst) - v.AuxInt = c ^ d - return true + break } - // match: (XOR (MOVDconst [d]) (MOVDconst [c])) - // result: (MOVDconst [c^d]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - d := v_0.AuxInt - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - v.reset(OpPPC64MOVDconst) - v.AuxInt = c ^ d - return true - } - return false -} -func rewriteValuePPC64_OpPPC64XOR_10(v *Value) bool { // match: (XOR x (MOVDconst [c])) // cond: isU32Bit(c) // result: (XORconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - if !(isU32Bit(c)) { - break - } - v.reset(OpPPC64XORconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XOR (MOVDconst [c]) x) - // cond: isU32Bit(c) - // result: (XORconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + c := v_1.AuxInt + if !(isU32Bit(c)) { + continue + } + v.reset(OpPPC64XORconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - if !(isU32Bit(c)) { - break - } - v.reset(OpPPC64XORconst) - v.AuxInt = c - v.AddArg(x) - return true + break } return false } @@ -23671,40 +14854,21 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { - break - } - v.reset(OpPPC64SRW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) - v0.AuxInt = 31 - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (Rsh32Ux64 x (AND (MOVDconst [31]) y)) - // result: (SRW x (ANDconst [31] y)) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64AND { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1.Args[_i0] + v_1_1 := v_1.Args[1^_i0] + if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { + continue + } + v.reset(OpPPC64SRW) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) + v0.AuxInt = 31 + v0.AddArg(y) + v.AddArg(v0) + return true } - v.reset(OpPPC64SRW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) - v0.AuxInt = 31 - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (Rsh32Ux64 x (ANDconst [31] y)) // result: (SRW x (ANDconst [31] y)) @@ -23775,65 +14939,27 @@ break } _ = v_1_1.Args[1] - y := v_1_1.Args[0] - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 31 { - break - } - v.reset(OpPPC64SRW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 32 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 31 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Rsh32Ux64 x (SUB (MOVDconst [32]) (AND (MOVDconst [31]) y))) - // result: (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1_1.Args[_i0] + v_1_1_1 := v_1_1.Args[1^_i0] + if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 31 { + continue + } + v.reset(OpPPC64SRW) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) + v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) + v1.AuxInt = 32 + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) + v2.AuxInt = 31 + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { - break - } - y := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 31 { - break - } - v.reset(OpPPC64SRW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 32 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 31 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValuePPC64_OpRsh32Ux64_10(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Rsh32Ux64 x y) // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { @@ -24089,40 +15215,21 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { - break - } - v.reset(OpPPC64SRAW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) - v0.AuxInt = 31 - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (Rsh32x64 x (AND (MOVDconst [31]) y)) - // result: (SRAW x (ANDconst [31] y)) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64AND { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1.Args[_i0] + v_1_1 := v_1.Args[1^_i0] + if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { + continue + } + v.reset(OpPPC64SRAW) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) + v0.AuxInt = 31 + v0.AddArg(y) + v.AddArg(v0) + return true } - v.reset(OpPPC64SRAW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) - v0.AuxInt = 31 - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (Rsh32x64 x (ANDconst [31] y)) // result: (SRAW x (ANDconst [31] y)) @@ -24193,65 +15300,27 @@ break } _ = v_1_1.Args[1] - y := v_1_1.Args[0] - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 31 { - break - } - v.reset(OpPPC64SRAW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 32 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 31 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Rsh32x64 x (SUB (MOVDconst [32]) (AND (MOVDconst [31]) y))) - // result: (SRAW x (SUB (MOVDconst [32]) (ANDconst [31] y))) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1_1.Args[_i0] + v_1_1_1 := v_1_1.Args[1^_i0] + if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 31 { + continue + } + v.reset(OpPPC64SRAW) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) + v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) + v1.AuxInt = 32 + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) + v2.AuxInt = 31 + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { - break - } - y := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 31 { - break - } - v.reset(OpPPC64SRAW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 32 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 31 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValuePPC64_OpRsh32x64_10(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Rsh32x64 x y) // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { @@ -24505,40 +15574,21 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { - break - } - v.reset(OpPPC64SRD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) - v0.AuxInt = 63 - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (Rsh64Ux64 x (AND (MOVDconst [63]) y)) - // result: (SRD x (ANDconst [63] y)) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64AND { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1.Args[_i0] + v_1_1 := v_1.Args[1^_i0] + if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { + continue + } + v.reset(OpPPC64SRD) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) + v0.AuxInt = 63 + v0.AddArg(y) + v.AddArg(v0) + return true } - v.reset(OpPPC64SRD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) - v0.AuxInt = 63 - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (Rsh64Ux64 x (ANDconst [63] y)) // result: (SRD x (ANDconst [63] y)) @@ -24609,65 +15659,27 @@ break } _ = v_1_1.Args[1] - y := v_1_1.Args[0] - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 63 { - break - } - v.reset(OpPPC64SRD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 64 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 63 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Rsh64Ux64 x (SUB (MOVDconst [64]) (AND (MOVDconst [63]) y))) - // result: (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1_1.Args[_i0] + v_1_1_1 := v_1_1.Args[1^_i0] + if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 63 { + continue + } + v.reset(OpPPC64SRD) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) + v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) + v1.AuxInt = 64 + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) + v2.AuxInt = 63 + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { - break - } - y := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 63 { - break - } - v.reset(OpPPC64SRD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 64 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 63 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValuePPC64_OpRsh64Ux64_10(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Rsh64Ux64 x y) // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { @@ -24923,40 +15935,21 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { - break - } - v.reset(OpPPC64SRAD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) - v0.AuxInt = 63 - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (Rsh64x64 x (AND (MOVDconst [63]) y)) - // result: (SRAD x (ANDconst [63] y)) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64AND { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1.Args[_i0] + v_1_1 := v_1.Args[1^_i0] + if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { + continue + } + v.reset(OpPPC64SRAD) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) + v0.AuxInt = 63 + v0.AddArg(y) + v.AddArg(v0) + return true } - v.reset(OpPPC64SRAD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) - v0.AuxInt = 63 - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (Rsh64x64 x (ANDconst [63] y)) // result: (SRAD x (ANDconst [63] y)) @@ -25027,65 +16020,27 @@ break } _ = v_1_1.Args[1] - y := v_1_1.Args[0] - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 63 { - break - } - v.reset(OpPPC64SRAD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 64 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 63 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Rsh64x64 x (SUB (MOVDconst [64]) (AND (MOVDconst [63]) y))) - // result: (SRAD x (SUB (MOVDconst [64]) (ANDconst [63] y))) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1_1.Args[_i0] + v_1_1_1 := v_1_1.Args[1^_i0] + if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 63 { + continue + } + v.reset(OpPPC64SRAD) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) + v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) + v1.AuxInt = 64 + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) + v2.AuxInt = 63 + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { - break - } - y := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 63 { - break - } - v.reset(OpPPC64SRAD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 64 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 63 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValuePPC64_OpRsh64x64_10(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Rsh64x64 x y) // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { @@ -26664,17 +17619,21 @@ if z.Op != OpPPC64AND { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64EQ) + v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64EQ) - v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (EQ (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 @@ -26688,17 +17647,21 @@ if z.Op != OpPPC64OR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64EQ) + v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64EQ) - v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (EQ (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 @@ -26712,17 +17675,21 @@ if z.Op != OpPPC64XOR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64EQ) + v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64EQ) - v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } case BlockPPC64GE: // match: (GE (FlagEQ) yes no) @@ -26805,17 +17772,21 @@ if z.Op != OpPPC64AND { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64GE) + v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64GE) - v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (GE (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 @@ -26829,17 +17800,21 @@ if z.Op != OpPPC64OR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64GE) + v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64GE) - v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (GE (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 @@ -26853,17 +17828,21 @@ if z.Op != OpPPC64XOR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64GE) + v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64GE) - v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } case BlockPPC64GT: // match: (GT (FlagEQ) yes no) @@ -26947,17 +17926,21 @@ if z.Op != OpPPC64AND { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64GT) + v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64GT) - v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (GT (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 @@ -26971,17 +17954,21 @@ if z.Op != OpPPC64OR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64GT) + v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64GT) - v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (GT (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 @@ -26995,17 +17982,21 @@ if z.Op != OpPPC64XOR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64GT) + v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64GT) - v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } case BlockIf: // match: (If (Equal cc) yes no) @@ -27190,17 +18181,21 @@ if z.Op != OpPPC64AND { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64LE) + v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64LE) - v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (LE (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 @@ -27214,17 +18209,21 @@ if z.Op != OpPPC64OR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64LE) + v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64LE) - v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (LE (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 @@ -27238,17 +18237,21 @@ if z.Op != OpPPC64XOR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64LE) + v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64LE) - v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } case BlockPPC64LT: // match: (LT (FlagEQ) yes no) @@ -27332,17 +18335,21 @@ if z.Op != OpPPC64AND { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64LT) + v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64LT) - v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (LT (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 @@ -27356,17 +18363,21 @@ if z.Op != OpPPC64OR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64LT) + v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64LT) - v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (LT (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 @@ -27380,17 +18391,21 @@ if z.Op != OpPPC64XOR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64LT) + v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64LT) - v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } case BlockPPC64NE: // match: (NE (CMPWconst [0] (Equal cc)) yes no) @@ -27673,17 +18688,21 @@ if z.Op != OpPPC64AND { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64NE) + v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64NE) - v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (NE (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 @@ -27697,17 +18716,21 @@ if z.Op != OpPPC64OR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64NE) + v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64NE) - v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (NE (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 @@ -27721,17 +18744,21 @@ if z.Op != OpPPC64XOR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64NE) + v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64NE) - v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } } return false -- diff -- # indent-heuristic: true @@ -404,7 +404,7 @@ case OpPPC64ADDconst: return rewriteValuePPC64_OpPPC64ADDconst_0(v) case OpPPC64AND: - return rewriteValuePPC64_OpPPC64AND_0(v) || rewriteValuePPC64_OpPPC64AND_10(v) + return rewriteValuePPC64_OpPPC64AND_0(v) case OpPPC64ANDconst: return rewriteValuePPC64_OpPPC64ANDconst_0(v) || rewriteValuePPC64_OpPPC64ANDconst_10(v) case OpPPC64CMP: @@ -546,7 +546,7 @@ case OpPPC64NotEqual: return rewriteValuePPC64_OpPPC64NotEqual_0(v) case OpPPC64OR: - return rewriteValuePPC64_OpPPC64OR_0(v) || rewriteValuePPC64_OpPPC64OR_10(v) || rewriteValuePPC64_OpPPC64OR_20(v) || rewriteValuePPC64_OpPPC64OR_30(v) || rewriteValuePPC64_OpPPC64OR_40(v) || rewriteValuePPC64_OpPPC64OR_50(v) || rewriteValuePPC64_OpPPC64OR_60(v) || rewriteValuePPC64_OpPPC64OR_70(v) || rewriteValuePPC64_OpPPC64OR_80(v) || rewriteValuePPC64_OpPPC64OR_90(v) || rewriteValuePPC64_OpPPC64OR_100(v) || rewriteValuePPC64_OpPPC64OR_110(v) + return rewriteValuePPC64_OpPPC64OR_0(v) || rewriteValuePPC64_OpPPC64OR_10(v) || rewriteValuePPC64_OpPPC64OR_20(v) case OpPPC64ORN: return rewriteValuePPC64_OpPPC64ORN_0(v) case OpPPC64ORconst: @@ -558,7 +558,7 @@ case OpPPC64SUB: return rewriteValuePPC64_OpPPC64SUB_0(v) case OpPPC64XOR: - return rewriteValuePPC64_OpPPC64XOR_0(v) || rewriteValuePPC64_OpPPC64XOR_10(v) + return rewriteValuePPC64_OpPPC64XOR_0(v) case OpPPC64XORconst: return rewriteValuePPC64_OpPPC64XORconst_0(v) case OpPanicBounds: @@ -606,7 +606,7 @@ case OpRsh32Ux32: return rewriteValuePPC64_OpRsh32Ux32_0(v) case OpRsh32Ux64: - return rewriteValuePPC64_OpRsh32Ux64_0(v) || rewriteValuePPC64_OpRsh32Ux64_10(v) + return rewriteValuePPC64_OpRsh32Ux64_0(v) case OpRsh32Ux8: return rewriteValuePPC64_OpRsh32Ux8_0(v) case OpRsh32x16: @@ -614,7 +614,7 @@ case OpRsh32x32: return rewriteValuePPC64_OpRsh32x32_0(v) case OpRsh32x64: - return rewriteValuePPC64_OpRsh32x64_0(v) || rewriteValuePPC64_OpRsh32x64_10(v) + return rewriteValuePPC64_OpRsh32x64_0(v) case OpRsh32x8: return rewriteValuePPC64_OpRsh32x8_0(v) case OpRsh64Ux16: @@ -622,7 +622,7 @@ case OpRsh64Ux32: return rewriteValuePPC64_OpRsh64Ux32_0(v) case OpRsh64Ux64: - return rewriteValuePPC64_OpRsh64Ux64_0(v) || rewriteValuePPC64_OpRsh64Ux64_10(v) + return rewriteValuePPC64_OpRsh64Ux64_0(v) case OpRsh64Ux8: return rewriteValuePPC64_OpRsh64Ux8_0(v) case OpRsh64x16: @@ -630,7 +630,7 @@ case OpRsh64x32: return rewriteValuePPC64_OpRsh64x32_0(v) case OpRsh64x64: - return rewriteValuePPC64_OpRsh64x64_0(v) || rewriteValuePPC64_OpRsh64x64_10(v) + return rewriteValuePPC64_OpRsh64x64_0(v) case OpRsh64x8: return rewriteValuePPC64_OpRsh64x8_0(v) case OpRsh8Ux16: @@ -1832,41 +1832,25 @@ // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { - y := v.Args[1] - x := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break - } - v.reset(OpPPC64Equal) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Eq16 y x) - // cond: isSigned(x.Type) && isSigned(y.Type) - // result: (Equal (CMPW (SignExt16to32 x) (SignExt16to32 y))) - for { - x := v.Args[1] - y := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break + _ = v.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + y := v.Args[1^_i0] + if !(isSigned(x.Type) && isSigned(y.Type)) { + continue + } + v.reset(OpPPC64Equal) + v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v.reset(OpPPC64Equal) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } // match: (Eq16 x y) // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) @@ -1952,41 +1936,25 @@ // cond: isSigned(x.Type) && isSigned(y.Type) // result: (Equal (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { - y := v.Args[1] - x := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break - } - v.reset(OpPPC64Equal) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Eq8 y x) - // cond: isSigned(x.Type) && isSigned(y.Type) - // result: (Equal (CMPW (SignExt8to32 x) (SignExt8to32 y))) - for { - x := v.Args[1] - y := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break + _ = v.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + y := v.Args[1^_i0] + if !(isSigned(x.Type) && isSigned(y.Type)) { + continue + } + v.reset(OpPPC64Equal) + v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v.reset(OpPPC64Equal) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } // match: (Eq8 x y) // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) @@ -3480,40 +3448,21 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { - break - } - v.reset(OpPPC64SLW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) - v0.AuxInt = 31 - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (Lsh32x64 x (AND (MOVDconst [31]) y)) - // result: (SLW x (ANDconst [31] y)) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64AND { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1.Args[_i0] + v_1_1 := v_1.Args[1^_i0] + if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { + continue + } + v.reset(OpPPC64SLW) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) + v0.AuxInt = 31 + v0.AddArg(y) + v.AddArg(v0) + return true } - v.reset(OpPPC64SLW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) - v0.AuxInt = 31 - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (Lsh32x64 x (ANDconst [31] y)) // result: (SLW x (ANDconst [31] y)) @@ -3786,40 +3735,21 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { - break - } - v.reset(OpPPC64SLD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) - v0.AuxInt = 63 - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (Lsh64x64 x (AND (MOVDconst [63]) y)) - // result: (SLD x (ANDconst [63] y)) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64AND { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1.Args[_i0] + v_1_1 := v_1.Args[1^_i0] + if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { + continue + } + v.reset(OpPPC64SLD) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) + v0.AuxInt = 63 + v0.AddArg(y) + v.AddArg(v0) + return true } - v.reset(OpPPC64SLD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) - v0.AuxInt = 63 - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (Lsh64x64 x (ANDconst [63] y)) // result: (SLD x (ANDconst [63] y)) @@ -4701,41 +4631,25 @@ // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { - y := v.Args[1] - x := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break - } - v.reset(OpPPC64NotEqual) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Neq16 y x) - // cond: isSigned(x.Type) && isSigned(y.Type) - // result: (NotEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) - for { - x := v.Args[1] - y := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break + _ = v.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + y := v.Args[1^_i0] + if !(isSigned(x.Type) && isSigned(y.Type)) { + continue + } + v.reset(OpPPC64NotEqual) + v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v.reset(OpPPC64NotEqual) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } // match: (Neq16 x y) // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) @@ -4821,41 +4735,25 @@ // cond: isSigned(x.Type) && isSigned(y.Type) // result: (NotEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { - y := v.Args[1] - x := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break - } - v.reset(OpPPC64NotEqual) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Neq8 y x) - // cond: isSigned(x.Type) && isSigned(y.Type) - // result: (NotEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) - for { - x := v.Args[1] - y := v.Args[0] - if !(isSigned(x.Type) && isSigned(y.Type)) { - break + _ = v.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + y := v.Args[1^_i0] + if !(isSigned(x.Type) && isSigned(y.Type)) { + continue + } + v.reset(OpPPC64NotEqual) + v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) + v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v.reset(OpPPC64NotEqual) - v0 := b.NewValue0(v.Pos, OpPPC64CMPW, types.TypeFlags) - v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v1.AddArg(x) - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } // match: (Neq8 x y) // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) @@ -5008,297 +4906,164 @@ // result: (ROTLconst [c] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLDconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRDconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpPPC64ROTLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADD (SRDconst x [d]) (SLDconst x [c])) - // cond: d == 64-c - // result: (ROTLconst [c] x) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLDconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRDconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 64-c) { + continue + } + v.reset(OpPPC64ROTLconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLDconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpPPC64ROTLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADD (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLWconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRWconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLWconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRWconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 32-c) { + continue + } + v.reset(OpPPC64ROTLWconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpPPC64ROTLWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADD (SRWconst x [d]) (SLWconst x [c])) - // cond: d == 32-c - // result: (ROTLWconst [c] x) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRWconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLWconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpPPC64ROTLWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (ADD (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // result: (ROTL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLD { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRD { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { - break - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADD (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) - // result: (ROTL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRD { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLD { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRD { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { + continue + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { + continue + } + v.reset(OpPPC64ROTL) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { - break - } - _ = v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 63 { - break - } - y := v_0_1_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLD { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int64 || v_1_1.AuxInt != 63 || y != v_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADD (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // result: (ROTLW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLW { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { - break - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (ADD (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) - // result: (ROTLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRW { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRW { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { + continue + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { + continue + } + v.reset(OpPPC64ROTLW) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { - break - } - _ = v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 31 { - break - } - y := v_0_1_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int32 || v_1_1.AuxInt != 31 || y != v_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTLW) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (ADD x (MOVDconst [c])) // cond: is32Bit(c) // result: (ADDconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpPPC64ADDconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (ADD (MOVDconst [c]) x) - // cond: is32Bit(c) - // result: (ADDconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + c := v_1.AuxInt + if !(is32Bit(c)) { + continue + } + v.reset(OpPPC64ADDconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - if !(is32Bit(c)) { - break - } - v.reset(OpPPC64ADDconst) - v.AuxInt = c - v.AddArg(x) - return true + break } return false } @@ -5358,225 +5123,129 @@ // result: (ANDN x y) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64NOR { - break - } - y := v_1.Args[1] - if y != v_1.Args[0] { - break - } - v.reset(OpPPC64ANDN) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (AND (NOR y y) x) - // result: (ANDN x y) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64NOR { - break - } - y := v_0.Args[1] - if y != v_0.Args[0] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64NOR { + continue + } + y := v_1.Args[1] + if y != v_1.Args[0] { + continue + } + v.reset(OpPPC64ANDN) + v.AddArg(x) + v.AddArg(y) + return true } - v.reset(OpPPC64ANDN) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (AND (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c&d]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - c := v_0.AuxInt - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64MOVDconst { + continue + } + c := v_0.AuxInt + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + d := v_1.AuxInt + v.reset(OpPPC64MOVDconst) + v.AuxInt = c & d + return true } - d := v_1.AuxInt - v.reset(OpPPC64MOVDconst) - v.AuxInt = c & d - return true - } - // match: (AND (MOVDconst [d]) (MOVDconst [c])) - // result: (MOVDconst [c&d]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - d := v_0.AuxInt - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - v.reset(OpPPC64MOVDconst) - v.AuxInt = c & d - return true + break } // match: (AND x (MOVDconst [c])) // cond: isU16Bit(c) // result: (ANDconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - if !(isU16Bit(c)) { - break - } - v.reset(OpPPC64ANDconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (AND (MOVDconst [c]) x) - // cond: isU16Bit(c) - // result: (ANDconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - c := v_0.AuxInt - if !(isU16Bit(c)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + c := v_1.AuxInt + if !(isU16Bit(c)) { + continue + } + v.reset(OpPPC64ANDconst) + v.AuxInt = c + v.AddArg(x) + return true } - v.reset(OpPPC64ANDconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (AND (MOVDconst [c]) y:(MOVWZreg _)) // cond: c&0xFFFFFFFF == 0xFFFFFFFF // result: y for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - c := v_0.AuxInt - y := v.Args[1] - if y.Op != OpPPC64MOVWZreg || !(c&0xFFFFFFFF == 0xFFFFFFFF) { - break - } - v.reset(OpCopy) - v.Type = y.Type - v.AddArg(y) - return true - } - // match: (AND y:(MOVWZreg _) (MOVDconst [c])) - // cond: c&0xFFFFFFFF == 0xFFFFFFFF - // result: y - for { - _ = v.Args[1] - y := v.Args[0] - if y.Op != OpPPC64MOVWZreg { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64MOVDconst { + continue + } + c := v_0.AuxInt + y := v.Args[1^_i0] + if y.Op != OpPPC64MOVWZreg || !(c&0xFFFFFFFF == 0xFFFFFFFF) { + continue + } + v.reset(OpCopy) + v.Type = y.Type + v.AddArg(y) + return true } - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - if !(c&0xFFFFFFFF == 0xFFFFFFFF) { - break - } - v.reset(OpCopy) - v.Type = y.Type - v.AddArg(y) - return true + break } // match: (AND (MOVDconst [0xFFFFFFFF]) y:(MOVWreg x)) // result: (MOVWZreg x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst || v_0.AuxInt != 0xFFFFFFFF { - break - } - y := v.Args[1] - if y.Op != OpPPC64MOVWreg { - break - } - x := y.Args[0] - v.reset(OpPPC64MOVWZreg) - v.AddArg(x) - return true - } - // match: (AND y:(MOVWreg x) (MOVDconst [0xFFFFFFFF])) - // result: (MOVWZreg x) - for { - _ = v.Args[1] - y := v.Args[0] - if y.Op != OpPPC64MOVWreg { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64MOVDconst || v_0.AuxInt != 0xFFFFFFFF { + continue + } + y := v.Args[1^_i0] + if y.Op != OpPPC64MOVWreg { + continue + } + x := y.Args[0] + v.reset(OpPPC64MOVWZreg) + v.AddArg(x) + return true } - x := y.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst || v_1.AuxInt != 0xFFFFFFFF { - break - } - v.reset(OpPPC64MOVWZreg) - v.AddArg(x) - return true + break } - return false -} -func rewriteValuePPC64_OpPPC64AND_10(v *Value) bool { // match: (AND (MOVDconst [c]) x:(MOVBZload _ _)) // result: (ANDconst [c&0xFF] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - c := v_0.AuxInt - x := v.Args[1] - if x.Op != OpPPC64MOVBZload { - break - } - _ = x.Args[1] - v.reset(OpPPC64ANDconst) - v.AuxInt = c & 0xFF - v.AddArg(x) - return true - } - // match: (AND x:(MOVBZload _ _) (MOVDconst [c])) - // result: (ANDconst [c&0xFF] x) - for { - _ = v.Args[1] - x := v.Args[0] - if x.Op != OpPPC64MOVBZload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64MOVDconst { + continue + } + c := v_0.AuxInt + x := v.Args[1^_i0] + if x.Op != OpPPC64MOVBZload { + continue + } + _ = x.Args[1] + v.reset(OpPPC64ANDconst) + v.AuxInt = c & 0xFF + v.AddArg(x) + return true } - _ = x.Args[1] - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - v.reset(OpPPC64ANDconst) - v.AuxInt = c & 0xFF - v.AddArg(x) - return true + break } return false } @@ -6278,72 +5947,46 @@ func rewriteValuePPC64_OpPPC64FADD_0(v *Value) bool { // match: (FADD (FMUL x y) z) // result: (FMADD x y z) - for { - z := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64FMUL { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v.reset(OpPPC64FMADD) - v.AddArg(x) - v.AddArg(y) - v.AddArg(z) - return true - } - // match: (FADD z (FMUL x y)) - // result: (FMADD x y z) for { _ = v.Args[1] - z := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64FMUL { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64FMUL { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v.Args[1^_i0] + v.reset(OpPPC64FMADD) + v.AddArg(x) + v.AddArg(y) + v.AddArg(z) + return true } - y := v_1.Args[1] - x := v_1.Args[0] - v.reset(OpPPC64FMADD) - v.AddArg(x) - v.AddArg(y) - v.AddArg(z) - return true + break } return false } func rewriteValuePPC64_OpPPC64FADDS_0(v *Value) bool { // match: (FADDS (FMULS x y) z) // result: (FMADDS x y z) - for { - z := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64FMULS { - break - } - y := v_0.Args[1] - x := v_0.Args[0] - v.reset(OpPPC64FMADDS) - v.AddArg(x) - v.AddArg(y) - v.AddArg(z) - return true - } - // match: (FADDS z (FMULS x y)) - // result: (FMADDS x y z) for { _ = v.Args[1] - z := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64FMULS { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64FMULS { + continue + } + y := v_0.Args[1] + x := v_0.Args[0] + z := v.Args[1^_i0] + v.reset(OpPPC64FMADDS) + v.AddArg(x) + v.AddArg(y) + v.AddArg(z) + return true } - y := v_1.Args[1] - x := v_1.Args[0] - v.reset(OpPPC64FMADDS) - v.AddArg(x) - v.AddArg(y) - v.AddArg(z) - return true + break } return false } @@ -11268,40 +10911,21 @@ break } _ = y.Args[1] - y_0 := y.Args[0] - if y_0.Op != OpPPC64MOVDconst { - break - } - c := y_0.AuxInt - if !(uint64(c) <= 0xFFFFFFFF) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y_0 := y.Args[_i0] + if y_0.Op != OpPPC64MOVDconst { + continue + } + c := y_0.AuxInt + if !(uint64(c) <= 0xFFFFFFFF) { + continue + } + v.reset(OpCopy) + v.Type = y.Type + v.AddArg(y) + return true } - v.reset(OpCopy) - v.Type = y.Type - v.AddArg(y) - return true - } - // match: (MOVWZreg y:(AND _ (MOVDconst [c]))) - // cond: uint64(c) <= 0xFFFFFFFF - // result: y - for { - y := v.Args[0] - if y.Op != OpPPC64AND { - break - } - _ = y.Args[1] - y_1 := y.Args[1] - if y_1.Op != OpPPC64MOVDconst { - break - } - c := y_1.AuxInt - if !(uint64(c) <= 0xFFFFFFFF) { - break - } - v.reset(OpCopy) - v.Type = y.Type - v.AddArg(y) - return true + break } // match: (MOVWZreg (SRWconst [c] (MOVBZreg x))) // result: (SRWconst [c] (MOVBZreg x)) @@ -11423,9 +11047,6 @@ v.AddArg(y) return true } - return false -} -func rewriteValuePPC64_OpPPC64MOVWZreg_10(v *Value) bool { // match: (MOVWZreg y:(MOVBZreg _)) // result: y for { @@ -11438,6 +11059,9 @@ v.AddArg(y) return true } + return false +} +func rewriteValuePPC64_OpPPC64MOVWZreg_10(v *Value) bool { // match: (MOVWZreg y:(MOVHBRload _ _)) // result: y for { @@ -11554,9 +11178,6 @@ v.AddArg(x) return true } - return false -} -func rewriteValuePPC64_OpPPC64MOVWZreg_20(v *Value) bool { // match: (MOVWZreg x:(Arg )) // cond: (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !isSigned(t) // result: x @@ -11574,6 +11195,9 @@ v.AddArg(x) return true } + return false +} +func rewriteValuePPC64_OpPPC64MOVWZreg_20(v *Value) bool { // match: (MOVWZreg (MOVDconst [c])) // result: (MOVDconst [int64(uint32(c))]) for { @@ -11734,40 +11358,21 @@ break } _ = y.Args[1] - y_0 := y.Args[0] - if y_0.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y_0 := y.Args[_i0] + if y_0.Op != OpPPC64MOVDconst { + continue + } + c := y_0.AuxInt + if !(uint64(c) <= 0x7FFFFFFF) { + continue + } + v.reset(OpCopy) + v.Type = y.Type + v.AddArg(y) + return true } - c := y_0.AuxInt - if !(uint64(c) <= 0x7FFFFFFF) { - break - } - v.reset(OpCopy) - v.Type = y.Type - v.AddArg(y) - return true - } - // match: (MOVWreg y:(AND _ (MOVDconst [c]))) - // cond: uint64(c) <= 0x7FFFFFFF - // result: y - for { - y := v.Args[0] - if y.Op != OpPPC64AND { - break - } - _ = y.Args[1] - y_1 := y.Args[1] - if y_1.Op != OpPPC64MOVDconst { - break - } - c := y_1.AuxInt - if !(uint64(c) <= 0x7FFFFFFF) { - break - } - v.reset(OpCopy) - v.Type = y.Type - v.AddArg(y) - return true + break } // match: (MOVWreg (SRAWconst [c] (MOVBreg x))) // result: (SRAWconst [c] (MOVBreg x)) @@ -11895,9 +11500,6 @@ v.AddArg(y) return true } - return false -} -func rewriteValuePPC64_OpPPC64MOVWreg_10(v *Value) bool { // match: (MOVWreg y:(MOVHreg _)) // result: y for { @@ -11910,6 +11512,9 @@ v.AddArg(y) return true } + return false +} +func rewriteValuePPC64_OpPPC64MOVWreg_10(v *Value) bool { // match: (MOVWreg y:(MOVBreg _)) // result: y for { @@ -12423,345 +12028,192 @@ } func rewriteValuePPC64_OpPPC64OR_0(v *Value) bool { b := v.Block + config := b.Func.Config typ := &b.Func.Config.Types - // match: (OR (SLDconst x [c]) (SRDconst x [d])) + // match: ( OR (SLDconst x [c]) (SRDconst x [d])) // cond: d == 64-c // result: (ROTLconst [c] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLDconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRDconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 64-c) { + continue + } + v.reset(OpPPC64ROTLconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRDconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpPPC64ROTLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } - // match: (OR (SRDconst x [d]) (SLDconst x [c])) - // cond: d == 64-c - // result: (ROTLconst [c] x) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRDconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLDconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpPPC64ROTLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (OR (SLWconst x [c]) (SRWconst x [d])) + // match: ( OR (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLWconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLWconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRWconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 32-c) { + continue + } + v.reset(OpPPC64ROTLWconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRWconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpPPC64ROTLWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (OR (SRWconst x [d]) (SLWconst x [c])) - // cond: d == 32-c - // result: (ROTLWconst [c] x) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRWconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLWconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpPPC64ROTLWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } - // match: (OR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) + // match: ( OR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // result: (ROTL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLD { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRD { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLD { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRD { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { + continue + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { + continue + } + v.reset(OpPPC64ROTL) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTL) - v.AddArg(x) - v.AddArg(y) - return true + break } - // match: (OR (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) - // result: (ROTL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRD { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { - break - } - _ = v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 63 { - break - } - y := v_0_1_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLD { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int64 || v_1_1.AuxInt != 63 || y != v_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (OR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) + // match: ( OR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // result: (ROTLW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLW { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRW { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { + continue + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { + continue + } + v.reset(OpPPC64ROTLW) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { - break - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (OR (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) - // result: (ROTLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRW { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { - break - } - _ = v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 31 { - break - } - y := v_0_1_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int32 || v_1_1.AuxInt != 31 || y != v_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTLW) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (OR (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c|d]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64MOVDconst { + continue + } + c := v_0.AuxInt + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + d := v_1.AuxInt + v.reset(OpPPC64MOVDconst) + v.AuxInt = c | d + return true } - c := v_0.AuxInt - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - d := v_1.AuxInt - v.reset(OpPPC64MOVDconst) - v.AuxInt = c | d - return true + break } - // match: (OR (MOVDconst [d]) (MOVDconst [c])) - // result: (MOVDconst [c|d]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - d := v_0.AuxInt - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - v.reset(OpPPC64MOVDconst) - v.AuxInt = c | d - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_10(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types // match: (OR x (MOVDconst [c])) // cond: isU32Bit(c) // result: (ORconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - if !(isU32Bit(c)) { - break - } - v.reset(OpPPC64ORconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (OR (MOVDconst [c]) x) - // cond: isU32Bit(c) - // result: (ORconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + c := v_1.AuxInt + if !(isU32Bit(c)) { + continue + } + v.reset(OpPPC64ORconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - if !(isU32Bit(c)) { - break - } - v.reset(OpPPC64ORconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (OR x0:(MOVBZload [i0] {s} p mem) o1:(SLWconst x1:(MOVBZload [i1] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) @@ -12769,79 +12221,42 @@ for { t := v.Type _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o1 := v.Args[1] - if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o1 := v.Args[1^_i0] + if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { + continue + } + x1 := o1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpPPC64MOVHZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVHZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o1:(SLWconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) - // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) - // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o1 := v.Args[0] - if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVHZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (OR x0:(MOVBZload [i0] {s} p mem) o1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) @@ -12849,79 +12264,42 @@ for { t := v.Type _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o1 := v.Args[1] - if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o1 := v.Args[1^_i0] + if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { + continue + } + x1 := o1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpPPC64MOVHZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVHZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [8]) x0:(MOVBZload [i0] {s} p mem)) - // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) - // result: @mergePoint(b,x0,x1) (MOVHZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o1 := v.Args[0] - if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVHZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (OR x0:(MOVBZload [i1] {s} p mem) o1:(SLWconst x1:(MOVBZload [i0] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) @@ -12929,83 +12307,44 @@ for { t := v.Type _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o1 := v.Args[1] - if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i1 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o1 := v.Args[1^_i0] + if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { + continue + } + x1 := o1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i0 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o1:(SLWconst x1:(MOVBZload [i0] {s} p mem) [8]) x0:(MOVBZload [i1] {s} p mem)) - // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) - // result: @mergePoint(b,x0,x1) (MOVHBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o1 := v.Args[0] - if o1.Op != OpPPC64SLWconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVHBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } // match: (OR x0:(MOVBZload [i1] {s} p mem) o1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [8])) // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) @@ -13013,87 +12352,48 @@ for { t := v.Type _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o1 := v.Args[1] - if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i1 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o1 := v.Args[1^_i0] + if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { + continue + } + x1 := o1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i0 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true } - i0 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [8]) x0:(MOVBZload [i1] {s} p mem)) - // cond: !config.BigEndian && i1 == i0+1 && x0.Uses ==1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1) - // result: @mergePoint(b,x0,x1) (MOVHBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o1 := v.Args[0] - if o1.Op != OpPPC64SLDconst || o1.AuxInt != 8 { - break - } - x1 := o1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && o1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(o1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVHBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } return false } -func rewriteValuePPC64_OpPPC64OR_20(v *Value) bool { +func rewriteValuePPC64_OpPPC64OR_10(v *Value) bool { b := v.Block config := b.Func.Config typ := &b.Func.Config.Types @@ -13103,101 +12403,53 @@ for { t := v.Type _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLWconst { - break - } - n1 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpPPC64SLWconst { - break - } - n2 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = n1 - v1 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) - v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (OR s1:(SLWconst x1:(MOVBZload [i0] {s} p mem) [n2]) s0:(SLWconst x0:(MOVBZload [i1] {s} p mem) [n1])) - // cond: !config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) - // result: @mergePoint(b,x0,x1) (SLDconst (MOVHBRload (MOVDaddr [i0] {s} p) mem) [n1]) - for { - t := v.Type - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLWconst { - break - } - n2 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpPPC64SLWconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpPPC64SLWconst { + continue + } + n1 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i1 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + s1 := v.Args[1^_i0] + if s1.Op != OpPPC64SLWconst { + continue + } + n2 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i0 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = n1 + v1 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) + v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v1.AddArg(v2) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - n1 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = n1 - v1 := b.NewValue0(x0.Pos, OpPPC64MOVHBRload, t) - v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (OR s0:(SLDconst x0:(MOVBZload [i1] {s} p mem) [n1]) s1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [n2])) // cond: !config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) @@ -13205,101 +12457,53 @@ for { t := v.Type _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst { - break - } - n1 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s1 := v.Args[1] - if s1.Op != OpPPC64SLDconst { - break - } - n2 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = n1 - v1 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) - v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (OR s1:(SLDconst x1:(MOVBZload [i0] {s} p mem) [n2]) s0:(SLDconst x0:(MOVBZload [i1] {s} p mem) [n1])) - // cond: !config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1) - // result: @mergePoint(b,x0,x1) (SLDconst (MOVHBRload (MOVDaddr [i0] {s} p) mem) [n1]) - for { - t := v.Type - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLDconst { - break - } - n2 := s1.AuxInt - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i0 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpPPC64SLDconst { + continue + } + n1 := s0.AuxInt + x0 := s0.Args[0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i1 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + s1 := v.Args[1^_i0] + if s1.Op != OpPPC64SLDconst { + continue + } + n2 := s1.AuxInt + x1 := s1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i0 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { + continue + } + b = mergePoint(b, x0, x1) + v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = n1 + v1 := b.NewValue0(x1.Pos, OpPPC64MOVHBRload, t) + v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v1.AddArg(v2) + v1.AddArg(mem) + v0.AddArg(v1) + return true } - n1 := s0.AuxInt - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i1 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && n1%8 == 0 && n2 == n1+8 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0) && clobber(x1) && clobber(s0) && clobber(s1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = n1 - v1 := b.NewValue0(x0.Pos, OpPPC64MOVHBRload, t) - v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (OR s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) @@ -13307,243 +12511,65 @@ for { t := v.Type _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHZload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { + continue + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i3 := x2.AuxInt + s := x2.Aux + mem := x2.Args[1] + p := x2.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := o0.Args[_i1] + if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { + continue + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i2 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + x0 := o0.Args[1^_i1] + if x0.Op != OpPPC64MOVHZload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x0.Pos, OpPPC64MOVWZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]))) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem)) s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24])) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [16])) s1:(SLWconst x2:(MOVBZload [i3] {s} p mem) [24])) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (OR s1:(SLDconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) @@ -13551,249 +12577,65 @@ for { t := v.Type _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s1:(SLDconst x2:(MOVBZload [i3] {s} p mem) [24]) o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [16]))) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_30(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [16]) x0:(MOVHZload [i0] {s} p mem)) s1:(SLDconst x2:(MOVBZload [i3] {s} p mem) [24])) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { + continue + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i3 := x2.AuxInt + s := x2.Aux + mem := x2.Args[1] + p := x2.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := o0.Args[_i1] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { + continue + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i2 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + x0 := o0.Args[1^_i1] + if x0.Op != OpPPC64MOVHZload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x0.Pos, OpPPC64MOVWZload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR x0:(MOVHZload [i0] {s} p mem) s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [16])) s1:(SLDconst x2:(MOVBZload [i3] {s} p mem) [24])) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses ==1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWZload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWZload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (OR s1:(SLWconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR s0:(SLWconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) @@ -13801,258 +12643,68 @@ for { t := v.Type _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s1:(SLWconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) s0:(SLWconst x1:(MOVBZload [i1] {s} p mem) [16]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s0:(SLWconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem)) s1:(SLWconst x2:(MOVBZload [i0] {s} p mem) [24])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) s0:(SLWconst x1:(MOVBZload [i1] {s} p mem) [16])) s1:(SLWconst x2:(MOVBZload [i0] {s} p mem) [24])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - mem := x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - s := x0_0.Aux - p := x0_0.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { + continue + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i0 := x2.AuxInt + s := x2.Aux + mem := x2.Args[1] + p := x2.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := o0.Args[_i1] + if s0.Op != OpPPC64SLWconst || s0.AuxInt != 16 { + continue + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + x0 := o0.Args[1^_i1] + if x0.Op != OpPPC64MOVHBRload || x0.Type != t { + continue + } + _ = x0.Args[1] + x0_0 := x0.Args[0] + if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { + continue + } + i2 := x0_0.AuxInt + if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } } - s1 := v.Args[1] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } // match: (OR s1:(SLDconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) @@ -14060,523 +12712,137 @@ for { t := v.Type _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s1 := v.Args[_i0] + if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { + continue + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i0 := x2.AuxInt + s := x2.Aux + mem := x2.Args[1] + p := x2.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := o0.Args[_i1] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { + continue + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + x0 := o0.Args[1^_i1] + if x0.Op != OpPPC64MOVHBRload || x0.Type != t { + continue + } + _ = x0.Args[1] + x0_0 := x0.Args[0] + if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { + continue + } + i2 := x0_0.AuxInt + if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } } - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } - // match: (OR s1:(SLDconst x2:(MOVBZload [i0] {s} p mem) [24]) o0:(OR x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [16]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s1 := v.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [16]) x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem)) s1:(SLDconst x2:(MOVBZload [i0] {s} p mem) [24])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - x0 := o0.Args[1] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) s0:(SLDconst x1:(MOVBZload [i1] {s} p mem) [16])) s1:(SLDconst x2:(MOVBZload [i0] {s} p mem) [24])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - mem := x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - s := x0_0.Aux - p := x0_0.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 16 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s1 := v.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 24 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_40(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLWconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) for { t := v.Type _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - _ = x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s1:(SLWconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [8]))) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - _ = x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i3 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := o0.Args[_i1] + if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { + continue + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i2 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + s1 := o0.Args[1^_i1] + if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { + continue + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVHBRload || x2.Type != t { + continue + } + _ = x2.Args[1] + x2_0 := x2.Args[0] + if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { + continue + } + i0 := x2_0.AuxInt + if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLWconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16])) x0:(MOVBZload [i3] {s} p mem)) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s1 := o0.Args[1] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - _ = x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] { - break - } - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s1:(SLWconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]) s0:(SLWconst x1:(MOVBZload [i2] {s} p mem) [8])) x0:(MOVBZload [i3] {s} p mem)) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLWconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - mem := x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - s := x2_0.Aux - p := x2_0.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLDconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) @@ -14584,258 +12850,68 @@ for { t := v.Type _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - _ = x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x0:(MOVBZload [i3] {s} p mem) o0:(OR s1:(SLDconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]) s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [8]))) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x0 := v.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - _ = x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x0 := v.Args[_i0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i3 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s0 := o0.Args[_i1] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { + continue + } + x1 := s0.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i2 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + s1 := o0.Args[1^_i1] + if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { + continue + } + x2 := s1.Args[0] + if x2.Op != OpPPC64MOVHBRload || x2.Type != t { + continue + } + _ = x2.Args[1] + x2_0 := x2.Args[0] + if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { + continue + } + i0 := x2_0.AuxInt + if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [8]) s1:(SLDconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16])) x0:(MOVBZload [i3] {s} p mem)) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - _ = x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - if x2_0.Aux != s || p != x2_0.Args[0] || mem != x2.Args[1] { - break - } - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s1:(SLDconst x2:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [16]) s0:(SLDconst x1:(MOVBZload [i2] {s} p mem) [8])) x0:(MOVBZload [i3] {s} p mem)) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 16 { - break - } - x2 := s1.Args[0] - if x2.Op != OpPPC64MOVHBRload || x2.Type != t { - break - } - mem := x2.Args[1] - x2_0 := x2.Args[0] - if x2_0.Op != OpPPC64MOVDaddr || x2_0.Type != typ.Uintptr { - break - } - i0 := x2_0.AuxInt - s := x2_0.Aux - p := x2_0.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 8 { - break - } - x1 := s0.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - x0 := v.Args[1] - if x0.Op != OpPPC64MOVBZload { - break - } - i3 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } // match: (OR s2:(SLDconst x2:(MOVBZload [i3] {s} p mem) [32]) o0:(OR s1:(SLDconst x1:(MOVBZload [i2] {s} p mem) [40]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [48]))) // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) @@ -14843,292 +12919,75 @@ for { t := v.Type _ = v.Args[1] - s2 := v.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i0 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s2 := v.Args[_i0] + if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { + continue + } + x2 := s2.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i3 := x2.AuxInt + s := x2.Aux + mem := x2.Args[1] + p := x2.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s1 := o0.Args[_i1] + if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { + continue + } + x1 := s1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i2 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + s0 := o0.Args[1^_i1] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { + continue + } + x0 := s0.Args[0] + if x0.Op != OpPPC64MOVHBRload || x0.Type != t { + continue + } + _ = x0.Args[1] + x0_0 := x0.Args[0] + if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { + continue + } + i0 := x0_0.AuxInt + if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = 32 + v1 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) + v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v1.AddArg(v2) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (OR s2:(SLDconst x2:(MOVBZload [i3] {s} p mem) [32]) o0:(OR s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [48]) s1:(SLDconst x1:(MOVBZload [i2] {s} p mem) [40]))) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) - for { - t := v.Type - _ = v.Args[1] - s2 := v.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i0 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_50(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i2] {s} p mem) [40]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [48])) s2:(SLDconst x2:(MOVBZload [i3] {s} p mem) [32])) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i0 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s2 := v.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (OR o0:(OR s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i0] {s} p) mem) [48]) s1:(SLDconst x1:(MOVBZload [i2] {s} p mem) [40])) s2:(SLDconst x2:(MOVBZload [i3] {s} p mem) [32])) - // cond: !config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 48 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - mem := x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i0 := x0_0.AuxInt - s := x0_0.Aux - p := x0_0.Args[0] - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 40 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i2 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s2 := v.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 32 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i3 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } // match: (OR s2:(SLDconst x2:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) [32]))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) @@ -15136,1945 +12995,193 @@ for { t := v.Type _ = v.Args[1] - s2 := v.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s2 := v.Args[_i0] + if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { + continue + } + x2 := s2.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i0 := x2.AuxInt + s := x2.Aux + mem := x2.Args[1] + p := x2.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s1 := o0.Args[_i1] + if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { + continue + } + x1 := s1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + s0 := o0.Args[1^_i1] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { + continue + } + x0 := s0.Args[0] + if x0.Op != OpPPC64MOVHBRload || x0.Type != t { + continue + } + _ = x0.Args[1] + x0_0 := x0.Args[0] + if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { + continue + } + i2 := x0_0.AuxInt + if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { + continue + } + b = mergePoint(b, x0, x1, x2) + v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = 32 + v1 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) + v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v2.AuxInt = i0 + v2.Aux = s + v2.AddArg(p) + v1.AddArg(v2) + v1.AddArg(mem) + v0.AddArg(v1) + return true + } } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x0.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x0.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (OR s2:(SLDconst x2:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) [32]) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) - for { - t := v.Type - _ = v.Args[1] - s2 := v.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x1.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) [32])) s2:(SLDconst x2:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - s0 := o0.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - _ = x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - if x0_0.Aux != s || p != x0_0.Args[0] || mem != x0.Args[1] { - break - } - s2 := v.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true - } - // match: (OR o0:(OR s0:(SLDconst x0:(MOVHBRload (MOVDaddr [i2] {s} p) mem) [32]) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s2:(SLDconst x2:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0) - // result: @mergePoint(b,x0,x1,x2) (SLDconst (MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s0 := o0.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVHBRload || x0.Type != t { - break - } - mem := x0.Args[1] - x0_0 := x0.Args[0] - if x0_0.Op != OpPPC64MOVDaddr || x0_0.Type != typ.Uintptr { - break - } - i2 := x0_0.AuxInt - s := x0_0.Aux - p := x0_0.Args[0] - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s2 := v.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 56 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i0 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && o0.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpPPC64SLDconst, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = 32 - v1 := b.NewValue0(x2.Pos, OpPPC64MOVWBRload, t) - v2 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v2.AuxInt = i0 - v2.Aux = s - v2.AddArg(p) - v1.AddArg(v2) - v1.AddArg(mem) - v0.AddArg(v1) - return true + break } + return false +} +func rewriteValuePPC64_OpPPC64OR_20(v *Value) bool { + b := v.Block + config := b.Func.Config + typ := &b.Func.Config.Types // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem))))) // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) for { t := v.Type _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x4.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x5.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x5.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_60(v *Value) bool { - b := v.Block - config := b.Func.Config - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56]) o5:(OR o4:(OR o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]))) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - s6 := v.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48]) o4:(OR o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]))) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s5 := o5.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s6 := v.Args[_i0] + if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { + continue + } + x7 := s6.Args[0] + if x7.Op != OpPPC64MOVBZload { + continue + } + i7 := x7.AuxInt + s := x7.Aux + mem := x7.Args[1] + p := x7.Args[0] + o5 := v.Args[1^_i0] + if o5.Op != OpPPC64OR || o5.Type != t { + continue + } + _ = o5.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s5 := o5.Args[_i1] + if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { + continue + } + x6 := s5.Args[0] + if x6.Op != OpPPC64MOVBZload { + continue + } + i6 := x6.AuxInt + if x6.Aux != s { + continue + } + _ = x6.Args[1] + if p != x6.Args[0] || mem != x6.Args[1] { + continue + } + o4 := o5.Args[1^_i1] + if o4.Op != OpPPC64OR || o4.Type != t { + continue + } + _ = o4.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s4 := o4.Args[_i2] + if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { + continue + } + x5 := s4.Args[0] + if x5.Op != OpPPC64MOVBZload { + continue + } + i5 := x5.AuxInt + if x5.Aux != s { + continue + } + _ = x5.Args[1] + if p != x5.Args[0] || mem != x5.Args[1] { + continue + } + o3 := o4.Args[1^_i2] + if o3.Op != OpPPC64OR || o3.Type != t { + continue + } + _ = o3.Args[1] + for _i3 := 0; _i3 <= 1; _i3++ { + s3 := o3.Args[_i3] + if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { + continue + } + x4 := s3.Args[0] + if x4.Op != OpPPC64MOVBZload { + continue + } + i4 := x4.AuxInt + if x4.Aux != s { + continue + } + _ = x4.Args[1] + if p != x4.Args[0] || mem != x4.Args[1] { + continue + } + x0 := o3.Args[1^_i3] + if x0.Op != OpPPC64MOVWZload { + continue + } + i0 := x0.AuxInt + if x0.Aux != s { + continue + } + _ = x0.Args[1] + if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { + continue + } + b = mergePoint(b, x0, x4, x5, x6, x7) + v0 := b.NewValue0(x0.Pos, OpPPC64MOVDload, t) + v.reset(OpCopy) + v.AddArg(v0) + v0.AuxInt = i0 + v0.Aux = s + v0.AddArg(p) + v0.AddArg(mem) + return true + } + } + } } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - s := x5.Aux - mem := x5.Args[1] - p := x5.Args[0] - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40]) o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]))) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s4 := o4.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - s := x5.Aux - mem := x5.Args[1] - p := x5.Args[0] - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_70(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR o5:(OR o4:(OR o3:(OR s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32]) x0:(MOVWZload {s} [i0] p mem)) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s3 := o3.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - s := x4.Aux - mem := x4.Args[1] - p := x4.Args[0] - x0 := o3.Args[1] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR o3:(OR x0:(MOVWZload {s} [i0] p mem) s3:(SLDconst x4:(MOVBZload [i4] {s} p mem) [32])) s4:(SLDconst x5:(MOVBZload [i5] {s} p mem) [40])) s5:(SLDconst x6:(MOVBZload [i6] {s} p mem) [48])) s6:(SLDconst x7:(MOVBZload [i7] {s} p mem) [56])) - // cond: !config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses ==1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber (s6) && clobber(o3) && clobber(o4) && clobber(o5) - // result: @mergePoint(b,x0,x4,x5,x6,x7) (MOVDload {s} [i0] p mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - x0 := o3.Args[0] - if x0.Op != OpPPC64MOVWZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - s3 := o3.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x4 := s3.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s4 := o4.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 40 { - break - } - x5 := s4.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s5 := o5.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 48 { - break - } - x6 := s5.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - s6 := v.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 56 { - break - } - x7 := s6.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i0%4 == 0 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s3.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x0, x4, x5, x6, x7) != nil && clobber(x0) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(s3) && clobber(s4) && clobber(s5) && clobber(s6) && clobber(o3) && clobber(o4) && clobber(o5)) { - break - } - b = mergePoint(b, x0, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDload, t) - v.reset(OpCopy) - v.AddArg(v0) - v0.AuxInt = i0 - v0.Aux = s - v0.AddArg(p) - v0.AddArg(mem) - return true + break } // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem))))) // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) @@ -17082,1701 +13189,114 @@ for { t := v.Type _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x4.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x4.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]))))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x2.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x2.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem))) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]))) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR o1:(OR o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56]) o0:(OR o1:(OR o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]))) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - s0 := v.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - s := x0.Aux - mem := x0.Args[1] - p := x0.Args[0] - o0 := v.Args[1] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x1.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x1.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_80(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)))) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break + for _i0 := 0; _i0 <= 1; _i0++ { + s0 := v.Args[_i0] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { + continue + } + x0 := s0.Args[0] + if x0.Op != OpPPC64MOVBZload { + continue + } + i0 := x0.AuxInt + s := x0.Aux + mem := x0.Args[1] + p := x0.Args[0] + o0 := v.Args[1^_i0] + if o0.Op != OpPPC64OR || o0.Type != t { + continue + } + _ = o0.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s1 := o0.Args[_i1] + if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { + continue + } + x1 := s1.Args[0] + if x1.Op != OpPPC64MOVBZload { + continue + } + i1 := x1.AuxInt + if x1.Aux != s { + continue + } + _ = x1.Args[1] + if p != x1.Args[0] || mem != x1.Args[1] { + continue + } + o1 := o0.Args[1^_i1] + if o1.Op != OpPPC64OR || o1.Type != t { + continue + } + _ = o1.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s2 := o1.Args[_i2] + if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { + continue + } + x2 := s2.Args[0] + if x2.Op != OpPPC64MOVBZload { + continue + } + i2 := x2.AuxInt + if x2.Aux != s { + continue + } + _ = x2.Args[1] + if p != x2.Args[0] || mem != x2.Args[1] { + continue + } + o2 := o1.Args[1^_i2] + if o2.Op != OpPPC64OR || o2.Type != t { + continue + } + _ = o2.Args[1] + for _i3 := 0; _i3 <= 1; _i3++ { + s3 := o2.Args[_i3] + if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { + continue + } + x3 := s3.Args[0] + if x3.Op != OpPPC64MOVBZload { + continue + } + i3 := x3.AuxInt + if x3.Aux != s { + continue + } + _ = x3.Args[1] + if p != x3.Args[0] || mem != x3.Args[1] { + continue + } + x4 := o2.Args[1^_i3] + if x4.Op != OpPPC64MOVWBRload || x4.Type != t { + continue + } + _ = x4.Args[1] + x4_0 := x4.Args[0] + if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { + continue + } + i4 := x4_0.AuxInt + if p != x4_0.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { + continue + } + b = mergePoint(b, x0, x1, x2, x3, x4) + v0 := b.NewValue0(x4.Pos, OpPPC64MOVDBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x4.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } + } + } } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])))) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]))) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48]) o1:(OR o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]))) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - s1 := o0.Args[0] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - s := x1.Aux - mem := x1.Args[1] - p := x1.Args[0] - o1 := o0.Args[1] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem))) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR o1:(OR s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40]) o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]))) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - s2 := o1.Args[0] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - s := x2.Aux - mem := x2.Args[1] - p := x2.Args[0] - o2 := o1.Args[1] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - if x3.Aux != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR o1:(OR o2:(OR s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32]) x4:(MOVWBRload (MOVDaddr [i4] p) mem)) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - s3 := o2.Args[0] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - s := x3.Aux - mem := x3.Args[1] - p := x3.Args[0] - x4 := o2.Args[1] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - _ = x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - if p != x4_0.Args[0] || mem != x4.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o0:(OR o1:(OR o2:(OR x4:(MOVWBRload (MOVDaddr [i4] p) mem) s3:(SLDconst x3:(MOVBZload [i3] {s} p mem) [32])) s2:(SLDconst x2:(MOVBZload [i2] {s} p mem) [40])) s1:(SLDconst x1:(MOVBZload [i1] {s} p mem) [48])) s0:(SLDconst x0:(MOVBZload [i0] {s} p mem) [56])) - // cond: !config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o0 := v.Args[0] - if o0.Op != OpPPC64OR || o0.Type != t { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpPPC64OR || o1.Type != t { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpPPC64OR || o2.Type != t { - break - } - _ = o2.Args[1] - x4 := o2.Args[0] - if x4.Op != OpPPC64MOVWBRload || x4.Type != t { - break - } - mem := x4.Args[1] - x4_0 := x4.Args[0] - if x4_0.Op != OpPPC64MOVDaddr || x4_0.Type != typ.Uintptr { - break - } - i4 := x4_0.AuxInt - p := x4_0.Args[0] - s3 := o2.Args[1] - if s3.Op != OpPPC64SLDconst || s3.AuxInt != 32 { - break - } - x3 := s3.Args[0] - if x3.Op != OpPPC64MOVBZload { - break - } - i3 := x3.AuxInt - s := x3.Aux - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - s2 := o1.Args[1] - if s2.Op != OpPPC64SLDconst || s2.AuxInt != 40 { - break - } - x2 := s2.Args[0] - if x2.Op != OpPPC64MOVBZload { - break - } - i2 := x2.AuxInt - if x2.Aux != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - s1 := o0.Args[1] - if s1.Op != OpPPC64SLDconst || s1.AuxInt != 48 { - break - } - x1 := s1.Args[0] - if x1.Op != OpPPC64MOVBZload { - break - } - i1 := x1.AuxInt - if x1.Aux != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - s0 := v.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 56 { - break - } - x0 := s0.Args[0] - if x0.Op != OpPPC64MOVBZload { - break - } - i0 := x0.AuxInt - if x0.Aux != s { - break - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(!config.BigEndian && i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(o0) && clobber(o1) && clobber(o2) && clobber(s0) && clobber(s1) && clobber(s2) && clobber(s3)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x0.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x0.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) @@ -18784,1710 +13304,114 @@ for { t := v.Type _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x7 := v.Args[_i0] + if x7.Op != OpPPC64MOVBZload { + continue + } + i7 := x7.AuxInt + s := x7.Aux + mem := x7.Args[1] + p := x7.Args[0] + o5 := v.Args[1^_i0] + if o5.Op != OpPPC64OR || o5.Type != t { + continue + } + _ = o5.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s6 := o5.Args[_i1] + if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { + continue + } + x6 := s6.Args[0] + if x6.Op != OpPPC64MOVBZload { + continue + } + i6 := x6.AuxInt + if x6.Aux != s { + continue + } + _ = x6.Args[1] + if p != x6.Args[0] || mem != x6.Args[1] { + continue + } + o4 := o5.Args[1^_i1] + if o4.Op != OpPPC64OR || o4.Type != t { + continue + } + _ = o4.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s5 := o4.Args[_i2] + if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { + continue + } + x5 := s5.Args[0] + if x5.Op != OpPPC64MOVBZload { + continue + } + i5 := x5.AuxInt + if x5.Aux != s { + continue + } + _ = x5.Args[1] + if p != x5.Args[0] || mem != x5.Args[1] { + continue + } + o3 := o4.Args[1^_i2] + if o3.Op != OpPPC64OR || o3.Type != t { + continue + } + _ = o3.Args[1] + for _i3 := 0; _i3 <= 1; _i3++ { + s4 := o3.Args[_i3] + if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { + continue + } + x4 := s4.Args[0] + if x4.Op != OpPPC64MOVBZload { + continue + } + i4 := x4.AuxInt + if x4.Aux != s { + continue + } + _ = x4.Args[1] + if p != x4.Args[0] || mem != x4.Args[1] { + continue + } + s0 := o3.Args[1^_i3] + if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { + continue + } + x3 := s0.Args[0] + if x3.Op != OpPPC64MOVWBRload || x3.Type != t { + continue + } + _ = x3.Args[1] + x3_0 := x3.Args[0] + if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { + continue + } + i0 := x3_0.AuxInt + if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { + continue + } + b = mergePoint(b, x3, x4, x5, x6, x7) + v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } + } + } } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x4.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x4.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_90(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x5.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x5.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x5.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x5.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_100(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - s := x5.Aux - mem := x5.Args[1] - p := x5.Args[0] - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - s := x5.Aux - mem := x5.Args[1] - p := x5.Args[0] - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - s := x4.Aux - mem := x4.Args[1] - p := x4.Args[0] - s0 := o3.Args[1] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR o3:(OR s0:(SLWconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLWconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - mem := x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - s := x3_0.Aux - p := x3_0.Args[0] - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))))) // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) @@ -20495,1704 +13419,114 @@ for { t := v.Type _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x4.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x4.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x5.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x5.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x5.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x5.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - return false -} -func rewriteValuePPC64_OpPPC64OR_110(v *Value) bool { - b := v.Block - config := b.Func.Config - typ := &b.Func.Config.Types - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR x7:(MOVBZload [i7] {s} p mem) o5:(OR o4:(OR o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]))) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - x7 := v.Args[0] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - s := x7.Aux - mem := x7.Args[1] - p := x7.Args[0] - o5 := v.Args[1] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x6.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8]) o4:(OR o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]))) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - s6 := o5.Args[0] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - s := x6.Aux - mem := x6.Args[1] - p := x6.Args[0] - o4 := o5.Args[1] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - s := x5.Aux - mem := x5.Args[1] - p := x5.Args[0] - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16]) o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]))) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - s5 := o4.Args[0] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - s := x5.Aux - mem := x5.Args[1] - p := x5.Args[0] - o3 := o4.Args[1] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x7 := v.Args[_i0] + if x7.Op != OpPPC64MOVBZload { + continue + } + i7 := x7.AuxInt + s := x7.Aux + mem := x7.Args[1] + p := x7.Args[0] + o5 := v.Args[1^_i0] + if o5.Op != OpPPC64OR || o5.Type != t { + continue + } + _ = o5.Args[1] + for _i1 := 0; _i1 <= 1; _i1++ { + s6 := o5.Args[_i1] + if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { + continue + } + x6 := s6.Args[0] + if x6.Op != OpPPC64MOVBZload { + continue + } + i6 := x6.AuxInt + if x6.Aux != s { + continue + } + _ = x6.Args[1] + if p != x6.Args[0] || mem != x6.Args[1] { + continue + } + o4 := o5.Args[1^_i1] + if o4.Op != OpPPC64OR || o4.Type != t { + continue + } + _ = o4.Args[1] + for _i2 := 0; _i2 <= 1; _i2++ { + s5 := o4.Args[_i2] + if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { + continue + } + x5 := s5.Args[0] + if x5.Op != OpPPC64MOVBZload { + continue + } + i5 := x5.AuxInt + if x5.Aux != s { + continue + } + _ = x5.Args[1] + if p != x5.Args[0] || mem != x5.Args[1] { + continue + } + o3 := o4.Args[1^_i2] + if o3.Op != OpPPC64OR || o3.Type != t { + continue + } + _ = o3.Args[1] + for _i3 := 0; _i3 <= 1; _i3++ { + s4 := o3.Args[_i3] + if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { + continue + } + x4 := s4.Args[0] + if x4.Op != OpPPC64MOVBZload { + continue + } + i4 := x4.AuxInt + if x4.Aux != s { + continue + } + _ = x4.Args[1] + if p != x4.Args[0] || mem != x4.Args[1] { + continue + } + s0 := o3.Args[1^_i3] + if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { + continue + } + x3 := s0.Args[0] + if x3.Op != OpPPC64MOVWBRload || x3.Type != t { + continue + } + _ = x3.Args[1] + x3_0 := x3.Args[0] + if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { + continue + } + i0 := x3_0.AuxInt + if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { + continue + } + b = mergePoint(b, x3, x4, x5, x6, x7) + v0 := b.NewValue0(x3.Pos, OpPPC64MOVDBRload, t) + v.reset(OpCopy) + v.AddArg(v0) + v1 := b.NewValue0(x3.Pos, OpPPC64MOVDaddr, typ.Uintptr) + v1.AuxInt = i0 + v1.Aux = s + v1.AddArg(p) + v0.AddArg(v1) + v0.AddArg(mem) + return true + } + } + } } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR o3:(OR s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24]) s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s4 := o3.Args[0] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - s := x4.Aux - mem := x4.Args[1] - p := x4.Args[0] - s0 := o3.Args[1] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - _ = x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - if x3_0.Aux != s || p != x3_0.Args[0] || mem != x3.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true - } - // match: (OR o5:(OR o4:(OR o3:(OR s0:(SLDconst x3:(MOVWBRload (MOVDaddr [i0] {s} p) mem) [32]) s4:(SLDconst x4:(MOVBZload [i4] {s} p mem) [24])) s5:(SLDconst x5:(MOVBZload [i5] {s} p mem) [16])) s6:(SLDconst x6:(MOVBZload [i6] {s} p mem) [8])) x7:(MOVBZload [i7] {s} p mem)) - // cond: !config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6) - // result: @mergePoint(b,x3,x4,x5,x6,x7) (MOVDBRload (MOVDaddr [i0] {s} p) mem) - for { - t := v.Type - _ = v.Args[1] - o5 := v.Args[0] - if o5.Op != OpPPC64OR || o5.Type != t { - break - } - _ = o5.Args[1] - o4 := o5.Args[0] - if o4.Op != OpPPC64OR || o4.Type != t { - break - } - _ = o4.Args[1] - o3 := o4.Args[0] - if o3.Op != OpPPC64OR || o3.Type != t { - break - } - _ = o3.Args[1] - s0 := o3.Args[0] - if s0.Op != OpPPC64SLDconst || s0.AuxInt != 32 { - break - } - x3 := s0.Args[0] - if x3.Op != OpPPC64MOVWBRload || x3.Type != t { - break - } - mem := x3.Args[1] - x3_0 := x3.Args[0] - if x3_0.Op != OpPPC64MOVDaddr || x3_0.Type != typ.Uintptr { - break - } - i0 := x3_0.AuxInt - s := x3_0.Aux - p := x3_0.Args[0] - s4 := o3.Args[1] - if s4.Op != OpPPC64SLDconst || s4.AuxInt != 24 { - break - } - x4 := s4.Args[0] - if x4.Op != OpPPC64MOVBZload { - break - } - i4 := x4.AuxInt - if x4.Aux != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - break - } - s5 := o4.Args[1] - if s5.Op != OpPPC64SLDconst || s5.AuxInt != 16 { - break - } - x5 := s5.Args[0] - if x5.Op != OpPPC64MOVBZload { - break - } - i5 := x5.AuxInt - if x5.Aux != s { - break - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - break - } - s6 := o5.Args[1] - if s6.Op != OpPPC64SLDconst || s6.AuxInt != 8 { - break - } - x6 := s6.Args[0] - if x6.Op != OpPPC64MOVBZload { - break - } - i6 := x6.AuxInt - if x6.Aux != s { - break - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - break - } - x7 := v.Args[1] - if x7.Op != OpPPC64MOVBZload { - break - } - i7 := x7.AuxInt - if x7.Aux != s { - break - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(!config.BigEndian && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && s4.Uses == 1 && s5.Uses == 1 && s6.Uses == 1 && mergePoint(b, x3, x4, x5, x6, x7) != nil && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) && clobber(x7) && clobber(o3) && clobber(o4) && clobber(o5) && clobber(s0) && clobber(s4) && clobber(s5) && clobber(s6)) { - break - } - b = mergePoint(b, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpPPC64MOVDBRload, t) - v.reset(OpCopy) - v.AddArg(v0) - v1 := b.NewValue0(x7.Pos, OpPPC64MOVDaddr, typ.Uintptr) - v1.AuxInt = i0 - v1.Aux = s - v1.AddArg(p) - v0.AddArg(v1) - v0.AddArg(mem) - return true + break } return false } @@ -22319,336 +13653,185 @@ // result: (ROTLconst [c] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLDconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRDconst { - break - } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpPPC64ROTLconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XOR (SRDconst x [d]) (SLDconst x [c])) - // cond: d == 64-c - // result: (ROTLconst [c] x) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLDconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRDconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 64-c) { + continue + } + v.reset(OpPPC64ROTLconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLDconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 64-c) { - break - } - v.reset(OpPPC64ROTLconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XOR (SLWconst x [c]) (SRWconst x [d])) // cond: d == 32-c // result: (ROTLWconst [c] x) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLWconst { - break - } - c := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRWconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLWconst { + continue + } + c := v_0.AuxInt + x := v_0.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRWconst { + continue + } + d := v_1.AuxInt + if x != v_1.Args[0] || !(d == 32-c) { + continue + } + v.reset(OpPPC64ROTLWconst) + v.AuxInt = c + v.AddArg(x) + return true } - d := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpPPC64ROTLWconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XOR (SRWconst x [d]) (SLWconst x [c])) - // cond: d == 32-c - // result: (ROTLWconst [c] x) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRWconst { - break - } - d := v_0.AuxInt - x := v_0.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLWconst { - break - } - c := v_1.AuxInt - if x != v_1.Args[0] || !(d == 32-c) { - break - } - v.reset(OpPPC64ROTLWconst) - v.AuxInt = c - v.AddArg(x) - return true + break } // match: (XOR (SLD x (ANDconst [63] y)) (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y)))) // result: (ROTL x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLD { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRD { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { - break - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTL) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (XOR (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) (SLD x (ANDconst [63] y))) - // result: (ROTL x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRD { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLD { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int64 || v_0_1.AuxInt != 63 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRD { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { + continue + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 64 { + continue + } + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 63 || y != v_1_1_1.Args[0] { + continue + } + v.reset(OpPPC64ROTL) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { - break - } - _ = v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 64 { - break - } - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 63 { - break - } - y := v_0_1_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLD { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int64 || v_1_1.AuxInt != 63 || y != v_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTL) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (XOR (SLW x (ANDconst [31] y)) (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y)))) // result: (ROTLW x y) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SLW { - break - } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { - break - } - y := v_0_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SRW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { - break - } - _ = v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { - break - } - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTLW) - v.AddArg(x) - v.AddArg(y) - return true - } - // match: (XOR (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) (SLW x (ANDconst [31] y))) - // result: (ROTLW x y) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64SRW { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64SLW { + continue + } + _ = v_0.Args[1] + x := v_0.Args[0] + v_0_1 := v_0.Args[1] + if v_0_1.Op != OpPPC64ANDconst || v_0_1.Type != typ.Int32 || v_0_1.AuxInt != 31 { + continue + } + y := v_0_1.Args[0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64SRW { + continue + } + _ = v_1.Args[1] + if x != v_1.Args[0] { + continue + } + v_1_1 := v_1.Args[1] + if v_1_1.Op != OpPPC64SUB || v_1_1.Type != typ.UInt { + continue + } + _ = v_1_1.Args[1] + v_1_1_0 := v_1_1.Args[0] + if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 32 { + continue + } + v_1_1_1 := v_1_1.Args[1] + if v_1_1_1.Op != OpPPC64ANDconst || v_1_1_1.Type != typ.UInt || v_1_1_1.AuxInt != 31 || y != v_1_1_1.Args[0] { + continue + } + v.reset(OpPPC64ROTLW) + v.AddArg(x) + v.AddArg(y) + return true } - _ = v_0.Args[1] - x := v_0.Args[0] - v_0_1 := v_0.Args[1] - if v_0_1.Op != OpPPC64SUB || v_0_1.Type != typ.UInt { - break - } - _ = v_0_1.Args[1] - v_0_1_0 := v_0_1.Args[0] - if v_0_1_0.Op != OpPPC64MOVDconst || v_0_1_0.AuxInt != 32 { - break - } - v_0_1_1 := v_0_1.Args[1] - if v_0_1_1.Op != OpPPC64ANDconst || v_0_1_1.Type != typ.UInt || v_0_1_1.AuxInt != 31 { - break - } - y := v_0_1_1.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SLW { - break - } - _ = v_1.Args[1] - if x != v_1.Args[0] { - break - } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64ANDconst || v_1_1.Type != typ.Int32 || v_1_1.AuxInt != 31 || y != v_1_1.Args[0] { - break - } - v.reset(OpPPC64ROTLW) - v.AddArg(x) - v.AddArg(y) - return true + break } // match: (XOR (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c^d]) for { _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + v_0 := v.Args[_i0] + if v_0.Op != OpPPC64MOVDconst { + continue + } + c := v_0.AuxInt + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + d := v_1.AuxInt + v.reset(OpPPC64MOVDconst) + v.AuxInt = c ^ d + return true } - c := v_0.AuxInt - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - d := v_1.AuxInt - v.reset(OpPPC64MOVDconst) - v.AuxInt = c ^ d - return true + break } - // match: (XOR (MOVDconst [d]) (MOVDconst [c])) - // result: (MOVDconst [c^d]) - for { - _ = v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break - } - d := v_0.AuxInt - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - v.reset(OpPPC64MOVDconst) - v.AuxInt = c ^ d - return true - } - return false -} -func rewriteValuePPC64_OpPPC64XOR_10(v *Value) bool { // match: (XOR x (MOVDconst [c])) // cond: isU32Bit(c) // result: (XORconst [c] x) for { _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64MOVDconst { - break - } - c := v_1.AuxInt - if !(isU32Bit(c)) { - break - } - v.reset(OpPPC64XORconst) - v.AuxInt = c - v.AddArg(x) - return true - } - // match: (XOR (MOVDconst [c]) x) - // cond: isU32Bit(c) - // result: (XORconst [c] x) - for { - x := v.Args[1] - v_0 := v.Args[0] - if v_0.Op != OpPPC64MOVDconst { - break + for _i0 := 0; _i0 <= 1; _i0++ { + x := v.Args[_i0] + v_1 := v.Args[1^_i0] + if v_1.Op != OpPPC64MOVDconst { + continue + } + c := v_1.AuxInt + if !(isU32Bit(c)) { + continue + } + v.reset(OpPPC64XORconst) + v.AuxInt = c + v.AddArg(x) + return true } - c := v_0.AuxInt - if !(isU32Bit(c)) { - break - } - v.reset(OpPPC64XORconst) - v.AuxInt = c - v.AddArg(x) - return true + break } return false } @@ -23671,40 +14854,21 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { - break - } - v.reset(OpPPC64SRW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) - v0.AuxInt = 31 - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (Rsh32Ux64 x (AND (MOVDconst [31]) y)) - // result: (SRW x (ANDconst [31] y)) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64AND { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1.Args[_i0] + v_1_1 := v_1.Args[1^_i0] + if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { + continue + } + v.reset(OpPPC64SRW) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) + v0.AuxInt = 31 + v0.AddArg(y) + v.AddArg(v0) + return true } - v.reset(OpPPC64SRW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) - v0.AuxInt = 31 - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (Rsh32Ux64 x (ANDconst [31] y)) // result: (SRW x (ANDconst [31] y)) @@ -23775,65 +14939,27 @@ break } _ = v_1_1.Args[1] - y := v_1_1.Args[0] - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 31 { - break - } - v.reset(OpPPC64SRW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 32 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 31 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Rsh32Ux64 x (SUB (MOVDconst [32]) (AND (MOVDconst [31]) y))) - // result: (SRW x (SUB (MOVDconst [32]) (ANDconst [31] y))) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1_1.Args[_i0] + v_1_1_1 := v_1_1.Args[1^_i0] + if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 31 { + continue + } + v.reset(OpPPC64SRW) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) + v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) + v1.AuxInt = 32 + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) + v2.AuxInt = 31 + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { - break - } - y := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 31 { - break - } - v.reset(OpPPC64SRW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 32 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 31 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValuePPC64_OpRsh32Ux64_10(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Rsh32Ux64 x y) // result: (SRW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { @@ -24089,40 +15215,21 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { - break - } - v.reset(OpPPC64SRAW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) - v0.AuxInt = 31 - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (Rsh32x64 x (AND (MOVDconst [31]) y)) - // result: (SRAW x (ANDconst [31] y)) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64AND { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 31 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1.Args[_i0] + v_1_1 := v_1.Args[1^_i0] + if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 31 { + continue + } + v.reset(OpPPC64SRAW) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) + v0.AuxInt = 31 + v0.AddArg(y) + v.AddArg(v0) + return true } - v.reset(OpPPC64SRAW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int32) - v0.AuxInt = 31 - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (Rsh32x64 x (ANDconst [31] y)) // result: (SRAW x (ANDconst [31] y)) @@ -24193,65 +15300,27 @@ break } _ = v_1_1.Args[1] - y := v_1_1.Args[0] - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 31 { - break - } - v.reset(OpPPC64SRAW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 32 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 31 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Rsh32x64 x (SUB (MOVDconst [32]) (AND (MOVDconst [31]) y))) - // result: (SRAW x (SUB (MOVDconst [32]) (ANDconst [31] y))) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 32 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1_1.Args[_i0] + v_1_1_1 := v_1_1.Args[1^_i0] + if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 31 { + continue + } + v.reset(OpPPC64SRAW) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) + v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) + v1.AuxInt = 32 + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) + v2.AuxInt = 31 + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { - break - } - y := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 31 { - break - } - v.reset(OpPPC64SRAW) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 32 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 31 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValuePPC64_OpRsh32x64_10(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Rsh32x64 x y) // result: (SRAW x (ORN y (MaskIfNotCarry (ADDconstForCarry [-32] y)))) for { @@ -24505,40 +15574,21 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { - break - } - v.reset(OpPPC64SRD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) - v0.AuxInt = 63 - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (Rsh64Ux64 x (AND (MOVDconst [63]) y)) - // result: (SRD x (ANDconst [63] y)) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64AND { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1.Args[_i0] + v_1_1 := v_1.Args[1^_i0] + if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { + continue + } + v.reset(OpPPC64SRD) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) + v0.AuxInt = 63 + v0.AddArg(y) + v.AddArg(v0) + return true } - v.reset(OpPPC64SRD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) - v0.AuxInt = 63 - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (Rsh64Ux64 x (ANDconst [63] y)) // result: (SRD x (ANDconst [63] y)) @@ -24609,65 +15659,27 @@ break } _ = v_1_1.Args[1] - y := v_1_1.Args[0] - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 63 { - break - } - v.reset(OpPPC64SRD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 64 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 63 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Rsh64Ux64 x (SUB (MOVDconst [64]) (AND (MOVDconst [63]) y))) - // result: (SRD x (SUB (MOVDconst [64]) (ANDconst [63] y))) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1_1.Args[_i0] + v_1_1_1 := v_1_1.Args[1^_i0] + if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 63 { + continue + } + v.reset(OpPPC64SRD) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) + v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) + v1.AuxInt = 64 + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) + v2.AuxInt = 63 + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { - break - } - y := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 63 { - break - } - v.reset(OpPPC64SRD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 64 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 63 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValuePPC64_OpRsh64Ux64_10(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Rsh64Ux64 x y) // result: (SRD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { @@ -24923,40 +15935,21 @@ break } _ = v_1.Args[1] - y := v_1.Args[0] - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { - break - } - v.reset(OpPPC64SRAD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) - v0.AuxInt = 63 - v0.AddArg(y) - v.AddArg(v0) - return true - } - // match: (Rsh64x64 x (AND (MOVDconst [63]) y)) - // result: (SRAD x (ANDconst [63] y)) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64AND { - break - } - y := v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 63 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1.Args[_i0] + v_1_1 := v_1.Args[1^_i0] + if v_1_1.Op != OpPPC64MOVDconst || v_1_1.AuxInt != 63 { + continue + } + v.reset(OpPPC64SRAD) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) + v0.AuxInt = 63 + v0.AddArg(y) + v.AddArg(v0) + return true } - v.reset(OpPPC64SRAD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.Int64) - v0.AuxInt = 63 - v0.AddArg(y) - v.AddArg(v0) - return true + break } // match: (Rsh64x64 x (ANDconst [63] y)) // result: (SRAD x (ANDconst [63] y)) @@ -25027,65 +16020,27 @@ break } _ = v_1_1.Args[1] - y := v_1_1.Args[0] - v_1_1_1 := v_1_1.Args[1] - if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 63 { - break - } - v.reset(OpPPC64SRAD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 64 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 63 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true - } - // match: (Rsh64x64 x (SUB (MOVDconst [64]) (AND (MOVDconst [63]) y))) - // result: (SRAD x (SUB (MOVDconst [64]) (ANDconst [63] y))) - for { - _ = v.Args[1] - x := v.Args[0] - v_1 := v.Args[1] - if v_1.Op != OpPPC64SUB || v_1.Type != typ.UInt { - break - } - _ = v_1.Args[1] - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpPPC64MOVDconst || v_1_0.AuxInt != 64 { - break + for _i0 := 0; _i0 <= 1; _i0++ { + y := v_1_1.Args[_i0] + v_1_1_1 := v_1_1.Args[1^_i0] + if v_1_1_1.Op != OpPPC64MOVDconst || v_1_1_1.AuxInt != 63 { + continue + } + v.reset(OpPPC64SRAD) + v.AddArg(x) + v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) + v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) + v1.AuxInt = 64 + v0.AddArg(v1) + v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) + v2.AuxInt = 63 + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true } - v_1_1 := v_1.Args[1] - if v_1_1.Op != OpPPC64AND || v_1_1.Type != typ.UInt { - break - } - y := v_1_1.Args[1] - v_1_1_0 := v_1_1.Args[0] - if v_1_1_0.Op != OpPPC64MOVDconst || v_1_1_0.AuxInt != 63 { - break - } - v.reset(OpPPC64SRAD) - v.AddArg(x) - v0 := b.NewValue0(v.Pos, OpPPC64SUB, typ.UInt) - v1 := b.NewValue0(v.Pos, OpPPC64MOVDconst, typ.Int64) - v1.AuxInt = 64 - v0.AddArg(v1) - v2 := b.NewValue0(v.Pos, OpPPC64ANDconst, typ.UInt) - v2.AuxInt = 63 - v2.AddArg(y) - v0.AddArg(v2) - v.AddArg(v0) - return true + break } - return false -} -func rewriteValuePPC64_OpRsh64x64_10(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types // match: (Rsh64x64 x y) // result: (SRAD x (ORN y (MaskIfNotCarry (ADDconstForCarry [-64] y)))) for { @@ -26664,17 +17619,21 @@ if z.Op != OpPPC64AND { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64EQ) + v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64EQ) - v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (EQ (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 @@ -26688,17 +17647,21 @@ if z.Op != OpPPC64OR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64EQ) + v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64EQ) - v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (EQ (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 @@ -26712,17 +17675,21 @@ if z.Op != OpPPC64XOR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64EQ) + v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64EQ) - v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } case BlockPPC64GE: // match: (GE (FlagEQ) yes no) @@ -26805,17 +17772,21 @@ if z.Op != OpPPC64AND { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64GE) + v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64GE) - v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (GE (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 @@ -26829,17 +17800,21 @@ if z.Op != OpPPC64OR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64GE) + v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64GE) - v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (GE (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 @@ -26853,17 +17828,21 @@ if z.Op != OpPPC64XOR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64GE) + v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64GE) - v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } case BlockPPC64GT: // match: (GT (FlagEQ) yes no) @@ -26947,17 +17926,21 @@ if z.Op != OpPPC64AND { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64GT) + v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64GT) - v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (GT (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 @@ -26971,17 +17954,21 @@ if z.Op != OpPPC64OR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64GT) + v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64GT) - v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (GT (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 @@ -26995,17 +17982,21 @@ if z.Op != OpPPC64XOR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64GT) + v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64GT) - v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } case BlockIf: // match: (If (Equal cc) yes no) @@ -27190,17 +18181,21 @@ if z.Op != OpPPC64AND { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64LE) + v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64LE) - v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (LE (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 @@ -27214,17 +18209,21 @@ if z.Op != OpPPC64OR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64LE) + v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64LE) - v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (LE (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 @@ -27238,17 +18237,21 @@ if z.Op != OpPPC64XOR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64LE) + v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64LE) - v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } case BlockPPC64LT: // match: (LT (FlagEQ) yes no) @@ -27332,17 +18335,21 @@ if z.Op != OpPPC64AND { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64LT) + v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64LT) - v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (LT (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 @@ -27356,17 +18363,21 @@ if z.Op != OpPPC64OR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64LT) + v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64LT) - v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (LT (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 @@ -27380,17 +18391,21 @@ if z.Op != OpPPC64XOR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64LT) + v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64LT) - v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } case BlockPPC64NE: // match: (NE (CMPWconst [0] (Equal cc)) yes no) @@ -27673,17 +18688,21 @@ if z.Op != OpPPC64AND { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64NE) + v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64NE) - v0 := b.NewValue0(v_0.Pos, OpPPC64ANDCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (NE (CMPconst [0] z:(OR x y)) yes no) // cond: z.Uses == 1 @@ -27697,17 +18716,21 @@ if z.Op != OpPPC64OR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64NE) + v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64NE) - v0 := b.NewValue0(v_0.Pos, OpPPC64ORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } // match: (NE (CMPconst [0] z:(XOR x y)) yes no) // cond: z.Uses == 1 @@ -27721,17 +18744,21 @@ if z.Op != OpPPC64XOR { break } - y := z.Args[1] - x := z.Args[0] - if !(z.Uses == 1) { - break + _ = z.Args[1] + for _i0 := 0; _i0 <= 1; _i0++ { + x := z.Args[_i0] + y := z.Args[1^_i0] + if !(z.Uses == 1) { + continue + } + b.Reset(BlockPPC64NE) + v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + b.AddControl(v0) + return true } - b.Reset(BlockPPC64NE) - v0 := b.NewValue0(v_0.Pos, OpPPC64XORCC, types.TypeFlags) - v0.AddArg(x) - v0.AddArg(y) - b.AddControl(v0) - return true + break } } return false go_c4e6ab9750e9d673a29203a9f41a517bcdc7a64c_test_fixedbugs_bug385_64.go.test000066400000000000000000151756051516001707200322320ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit c4e6ab9750e9d673a29203a9f41a517bcdc7a64c file test/fixedbugs/bug385_64.go -- x -- // errorcheck //go:build amd64 // Copyright 2011 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // Issue 2444 // Issue 4666: issue with arrays of exactly 4GB. package main var z [1 << 17]byte func main() { // GC_ERROR "stack frame too large" // seq 1 16480 | sed 's/.*/ var x& [1<<17]byte/' // seq 1 16480 | sed 's/.*/ z = x&/' var x1 [1 << 17]byte var x2 [1 << 17]byte var x3 [1 << 17]byte var x4 [1 << 17]byte var x5 [1 << 17]byte var x6 [1 << 17]byte var x7 [1 << 17]byte var x8 [1 << 17]byte var x9 [1 << 17]byte var x10 [1 << 17]byte var x11 [1 << 17]byte var x12 [1 << 17]byte var x13 [1 << 17]byte var x14 [1 << 17]byte var x15 [1 << 17]byte var x16 [1 << 17]byte var x17 [1 << 17]byte var x18 [1 << 17]byte var x19 [1 << 17]byte var x20 [1 << 17]byte var x21 [1 << 17]byte var x22 [1 << 17]byte var x23 [1 << 17]byte var x24 [1 << 17]byte var x25 [1 << 17]byte var x26 [1 << 17]byte var x27 [1 << 17]byte var x28 [1 << 17]byte var x29 [1 << 17]byte var x30 [1 << 17]byte var x31 [1 << 17]byte var x32 [1 << 17]byte var x33 [1 << 17]byte var x34 [1 << 17]byte var x35 [1 << 17]byte var x36 [1 << 17]byte var x37 [1 << 17]byte var x38 [1 << 17]byte var x39 [1 << 17]byte var x40 [1 << 17]byte var x41 [1 << 17]byte var x42 [1 << 17]byte var x43 [1 << 17]byte var x44 [1 << 17]byte var x45 [1 << 17]byte var x46 [1 << 17]byte var x47 [1 << 17]byte var x48 [1 << 17]byte var x49 [1 << 17]byte var x50 [1 << 17]byte var x51 [1 << 17]byte var x52 [1 << 17]byte var x53 [1 << 17]byte var x54 [1 << 17]byte var x55 [1 << 17]byte var x56 [1 << 17]byte var x57 [1 << 17]byte var x58 [1 << 17]byte var x59 [1 << 17]byte var x60 [1 << 17]byte var x61 [1 << 17]byte var x62 [1 << 17]byte var x63 [1 << 17]byte var x64 [1 << 17]byte var x65 [1 << 17]byte var x66 [1 << 17]byte var x67 [1 << 17]byte var x68 [1 << 17]byte var x69 [1 << 17]byte var x70 [1 << 17]byte var x71 [1 << 17]byte var x72 [1 << 17]byte var x73 [1 << 17]byte var x74 [1 << 17]byte var x75 [1 << 17]byte var x76 [1 << 17]byte var x77 [1 << 17]byte var x78 [1 << 17]byte var x79 [1 << 17]byte var x80 [1 << 17]byte var x81 [1 << 17]byte var x82 [1 << 17]byte var x83 [1 << 17]byte var x84 [1 << 17]byte var x85 [1 << 17]byte var x86 [1 << 17]byte var x87 [1 << 17]byte var x88 [1 << 17]byte var x89 [1 << 17]byte var x90 [1 << 17]byte var x91 [1 << 17]byte var x92 [1 << 17]byte var x93 [1 << 17]byte var x94 [1 << 17]byte var x95 [1 << 17]byte var x96 [1 << 17]byte var x97 [1 << 17]byte var x98 [1 << 17]byte var x99 [1 << 17]byte var x100 [1 << 17]byte var x101 [1 << 17]byte var x102 [1 << 17]byte var x103 [1 << 17]byte var x104 [1 << 17]byte var x105 [1 << 17]byte var x106 [1 << 17]byte var x107 [1 << 17]byte var x108 [1 << 17]byte var x109 [1 << 17]byte var x110 [1 << 17]byte var x111 [1 << 17]byte var x112 [1 << 17]byte var x113 [1 << 17]byte var x114 [1 << 17]byte var x115 [1 << 17]byte var x116 [1 << 17]byte var x117 [1 << 17]byte var x118 [1 << 17]byte var x119 [1 << 17]byte var x120 [1 << 17]byte var x121 [1 << 17]byte var x122 [1 << 17]byte var x123 [1 << 17]byte var x124 [1 << 17]byte var x125 [1 << 17]byte var x126 [1 << 17]byte var x127 [1 << 17]byte var x128 [1 << 17]byte var x129 [1 << 17]byte var x130 [1 << 17]byte var x131 [1 << 17]byte var x132 [1 << 17]byte var x133 [1 << 17]byte var x134 [1 << 17]byte var x135 [1 << 17]byte var x136 [1 << 17]byte var x137 [1 << 17]byte var x138 [1 << 17]byte var x139 [1 << 17]byte var x140 [1 << 17]byte var x141 [1 << 17]byte var x142 [1 << 17]byte var x143 [1 << 17]byte var x144 [1 << 17]byte var x145 [1 << 17]byte var x146 [1 << 17]byte var x147 [1 << 17]byte var x148 [1 << 17]byte var x149 [1 << 17]byte var x150 [1 << 17]byte var x151 [1 << 17]byte var x152 [1 << 17]byte var x153 [1 << 17]byte var x154 [1 << 17]byte var x155 [1 << 17]byte var x156 [1 << 17]byte var x157 [1 << 17]byte var x158 [1 << 17]byte var x159 [1 << 17]byte var x160 [1 << 17]byte var x161 [1 << 17]byte var x162 [1 << 17]byte var x163 [1 << 17]byte var x164 [1 << 17]byte var x165 [1 << 17]byte var x166 [1 << 17]byte var x167 [1 << 17]byte var x168 [1 << 17]byte var x169 [1 << 17]byte var x170 [1 << 17]byte var x171 [1 << 17]byte var x172 [1 << 17]byte var x173 [1 << 17]byte var x174 [1 << 17]byte var x175 [1 << 17]byte var x176 [1 << 17]byte var x177 [1 << 17]byte var x178 [1 << 17]byte var x179 [1 << 17]byte var x180 [1 << 17]byte var x181 [1 << 17]byte var x182 [1 << 17]byte var x183 [1 << 17]byte var x184 [1 << 17]byte var x185 [1 << 17]byte var x186 [1 << 17]byte var x187 [1 << 17]byte var x188 [1 << 17]byte var x189 [1 << 17]byte var x190 [1 << 17]byte var x191 [1 << 17]byte var x192 [1 << 17]byte var x193 [1 << 17]byte var x194 [1 << 17]byte var x195 [1 << 17]byte var x196 [1 << 17]byte var x197 [1 << 17]byte var x198 [1 << 17]byte var x199 [1 << 17]byte var x200 [1 << 17]byte var x201 [1 << 17]byte var x202 [1 << 17]byte var x203 [1 << 17]byte var x204 [1 << 17]byte var x205 [1 << 17]byte var x206 [1 << 17]byte var x207 [1 << 17]byte var x208 [1 << 17]byte var x209 [1 << 17]byte var x210 [1 << 17]byte var x211 [1 << 17]byte var x212 [1 << 17]byte var x213 [1 << 17]byte var x214 [1 << 17]byte var x215 [1 << 17]byte var x216 [1 << 17]byte var x217 [1 << 17]byte var x218 [1 << 17]byte var x219 [1 << 17]byte var x220 [1 << 17]byte var x221 [1 << 17]byte var x222 [1 << 17]byte var x223 [1 << 17]byte var x224 [1 << 17]byte var x225 [1 << 17]byte var x226 [1 << 17]byte var x227 [1 << 17]byte var x228 [1 << 17]byte var x229 [1 << 17]byte var x230 [1 << 17]byte var x231 [1 << 17]byte var x232 [1 << 17]byte var x233 [1 << 17]byte var x234 [1 << 17]byte var x235 [1 << 17]byte var x236 [1 << 17]byte var x237 [1 << 17]byte var x238 [1 << 17]byte var x239 [1 << 17]byte var x240 [1 << 17]byte var x241 [1 << 17]byte var x242 [1 << 17]byte var x243 [1 << 17]byte var x244 [1 << 17]byte var x245 [1 << 17]byte var x246 [1 << 17]byte var x247 [1 << 17]byte var x248 [1 << 17]byte var x249 [1 << 17]byte var x250 [1 << 17]byte var x251 [1 << 17]byte var x252 [1 << 17]byte var x253 [1 << 17]byte var x254 [1 << 17]byte var x255 [1 << 17]byte var x256 [1 << 17]byte var x257 [1 << 17]byte var x258 [1 << 17]byte var x259 [1 << 17]byte var x260 [1 << 17]byte var x261 [1 << 17]byte var x262 [1 << 17]byte var x263 [1 << 17]byte var x264 [1 << 17]byte var x265 [1 << 17]byte var x266 [1 << 17]byte var x267 [1 << 17]byte var x268 [1 << 17]byte var x269 [1 << 17]byte var x270 [1 << 17]byte var x271 [1 << 17]byte var x272 [1 << 17]byte var x273 [1 << 17]byte var x274 [1 << 17]byte var x275 [1 << 17]byte var x276 [1 << 17]byte var x277 [1 << 17]byte var x278 [1 << 17]byte var x279 [1 << 17]byte var x280 [1 << 17]byte var x281 [1 << 17]byte var x282 [1 << 17]byte var x283 [1 << 17]byte var x284 [1 << 17]byte var x285 [1 << 17]byte var x286 [1 << 17]byte var x287 [1 << 17]byte var x288 [1 << 17]byte var x289 [1 << 17]byte var x290 [1 << 17]byte var x291 [1 << 17]byte var x292 [1 << 17]byte var x293 [1 << 17]byte var x294 [1 << 17]byte var x295 [1 << 17]byte var x296 [1 << 17]byte var x297 [1 << 17]byte var x298 [1 << 17]byte var x299 [1 << 17]byte var x300 [1 << 17]byte var x301 [1 << 17]byte var x302 [1 << 17]byte var x303 [1 << 17]byte var x304 [1 << 17]byte var x305 [1 << 17]byte var x306 [1 << 17]byte var x307 [1 << 17]byte var x308 [1 << 17]byte var x309 [1 << 17]byte var x310 [1 << 17]byte var x311 [1 << 17]byte var x312 [1 << 17]byte var x313 [1 << 17]byte var x314 [1 << 17]byte var x315 [1 << 17]byte var x316 [1 << 17]byte var x317 [1 << 17]byte var x318 [1 << 17]byte var x319 [1 << 17]byte var x320 [1 << 17]byte var x321 [1 << 17]byte var x322 [1 << 17]byte var x323 [1 << 17]byte var x324 [1 << 17]byte var x325 [1 << 17]byte var x326 [1 << 17]byte var x327 [1 << 17]byte var x328 [1 << 17]byte var x329 [1 << 17]byte var x330 [1 << 17]byte var x331 [1 << 17]byte var x332 [1 << 17]byte var x333 [1 << 17]byte var x334 [1 << 17]byte var x335 [1 << 17]byte var x336 [1 << 17]byte var x337 [1 << 17]byte var x338 [1 << 17]byte var x339 [1 << 17]byte var x340 [1 << 17]byte var x341 [1 << 17]byte var x342 [1 << 17]byte var x343 [1 << 17]byte var x344 [1 << 17]byte var x345 [1 << 17]byte var x346 [1 << 17]byte var x347 [1 << 17]byte var x348 [1 << 17]byte var x349 [1 << 17]byte var x350 [1 << 17]byte var x351 [1 << 17]byte var x352 [1 << 17]byte var x353 [1 << 17]byte var x354 [1 << 17]byte var x355 [1 << 17]byte var x356 [1 << 17]byte var x357 [1 << 17]byte var x358 [1 << 17]byte var x359 [1 << 17]byte var x360 [1 << 17]byte var x361 [1 << 17]byte var x362 [1 << 17]byte var x363 [1 << 17]byte var x364 [1 << 17]byte var x365 [1 << 17]byte var x366 [1 << 17]byte var x367 [1 << 17]byte var x368 [1 << 17]byte var x369 [1 << 17]byte var x370 [1 << 17]byte var x371 [1 << 17]byte var x372 [1 << 17]byte var x373 [1 << 17]byte var x374 [1 << 17]byte var x375 [1 << 17]byte var x376 [1 << 17]byte var x377 [1 << 17]byte var x378 [1 << 17]byte var x379 [1 << 17]byte var x380 [1 << 17]byte var x381 [1 << 17]byte var x382 [1 << 17]byte var x383 [1 << 17]byte var x384 [1 << 17]byte var x385 [1 << 17]byte var x386 [1 << 17]byte var x387 [1 << 17]byte var x388 [1 << 17]byte var x389 [1 << 17]byte var x390 [1 << 17]byte var x391 [1 << 17]byte var x392 [1 << 17]byte var x393 [1 << 17]byte var x394 [1 << 17]byte var x395 [1 << 17]byte var x396 [1 << 17]byte var x397 [1 << 17]byte var x398 [1 << 17]byte var x399 [1 << 17]byte var x400 [1 << 17]byte var x401 [1 << 17]byte var x402 [1 << 17]byte var x403 [1 << 17]byte var x404 [1 << 17]byte var x405 [1 << 17]byte var x406 [1 << 17]byte var x407 [1 << 17]byte var x408 [1 << 17]byte var x409 [1 << 17]byte var x410 [1 << 17]byte var x411 [1 << 17]byte var x412 [1 << 17]byte var x413 [1 << 17]byte var x414 [1 << 17]byte var x415 [1 << 17]byte var x416 [1 << 17]byte var x417 [1 << 17]byte var x418 [1 << 17]byte var x419 [1 << 17]byte var x420 [1 << 17]byte var x421 [1 << 17]byte var x422 [1 << 17]byte var x423 [1 << 17]byte var x424 [1 << 17]byte var x425 [1 << 17]byte var x426 [1 << 17]byte var x427 [1 << 17]byte var x428 [1 << 17]byte var x429 [1 << 17]byte var x430 [1 << 17]byte var x431 [1 << 17]byte var x432 [1 << 17]byte var x433 [1 << 17]byte var x434 [1 << 17]byte var x435 [1 << 17]byte var x436 [1 << 17]byte var x437 [1 << 17]byte var x438 [1 << 17]byte var x439 [1 << 17]byte var x440 [1 << 17]byte var x441 [1 << 17]byte var x442 [1 << 17]byte var x443 [1 << 17]byte var x444 [1 << 17]byte var x445 [1 << 17]byte var x446 [1 << 17]byte var x447 [1 << 17]byte var x448 [1 << 17]byte var x449 [1 << 17]byte var x450 [1 << 17]byte var x451 [1 << 17]byte var x452 [1 << 17]byte var x453 [1 << 17]byte var x454 [1 << 17]byte var x455 [1 << 17]byte var x456 [1 << 17]byte var x457 [1 << 17]byte var x458 [1 << 17]byte var x459 [1 << 17]byte var x460 [1 << 17]byte var x461 [1 << 17]byte var x462 [1 << 17]byte var x463 [1 << 17]byte var x464 [1 << 17]byte var x465 [1 << 17]byte var x466 [1 << 17]byte var x467 [1 << 17]byte var x468 [1 << 17]byte var x469 [1 << 17]byte var x470 [1 << 17]byte var x471 [1 << 17]byte var x472 [1 << 17]byte var x473 [1 << 17]byte var x474 [1 << 17]byte var x475 [1 << 17]byte var x476 [1 << 17]byte var x477 [1 << 17]byte var x478 [1 << 17]byte var x479 [1 << 17]byte var x480 [1 << 17]byte var x481 [1 << 17]byte var x482 [1 << 17]byte var x483 [1 << 17]byte var x484 [1 << 17]byte var x485 [1 << 17]byte var x486 [1 << 17]byte var x487 [1 << 17]byte var x488 [1 << 17]byte var x489 [1 << 17]byte var x490 [1 << 17]byte var x491 [1 << 17]byte var x492 [1 << 17]byte var x493 [1 << 17]byte var x494 [1 << 17]byte var x495 [1 << 17]byte var x496 [1 << 17]byte var x497 [1 << 17]byte var x498 [1 << 17]byte var x499 [1 << 17]byte var x500 [1 << 17]byte var x501 [1 << 17]byte var x502 [1 << 17]byte var x503 [1 << 17]byte var x504 [1 << 17]byte var x505 [1 << 17]byte var x506 [1 << 17]byte var x507 [1 << 17]byte var x508 [1 << 17]byte var x509 [1 << 17]byte var x510 [1 << 17]byte var x511 [1 << 17]byte var x512 [1 << 17]byte var x513 [1 << 17]byte var x514 [1 << 17]byte var x515 [1 << 17]byte var x516 [1 << 17]byte var x517 [1 << 17]byte var x518 [1 << 17]byte var x519 [1 << 17]byte var x520 [1 << 17]byte var x521 [1 << 17]byte var x522 [1 << 17]byte var x523 [1 << 17]byte var x524 [1 << 17]byte var x525 [1 << 17]byte var x526 [1 << 17]byte var x527 [1 << 17]byte var x528 [1 << 17]byte var x529 [1 << 17]byte var x530 [1 << 17]byte var x531 [1 << 17]byte var x532 [1 << 17]byte var x533 [1 << 17]byte var x534 [1 << 17]byte var x535 [1 << 17]byte var x536 [1 << 17]byte var x537 [1 << 17]byte var x538 [1 << 17]byte var x539 [1 << 17]byte var x540 [1 << 17]byte var x541 [1 << 17]byte var x542 [1 << 17]byte var x543 [1 << 17]byte var x544 [1 << 17]byte var x545 [1 << 17]byte var x546 [1 << 17]byte var x547 [1 << 17]byte var x548 [1 << 17]byte var x549 [1 << 17]byte var x550 [1 << 17]byte var x551 [1 << 17]byte var x552 [1 << 17]byte var x553 [1 << 17]byte var x554 [1 << 17]byte var x555 [1 << 17]byte var x556 [1 << 17]byte var x557 [1 << 17]byte var x558 [1 << 17]byte var x559 [1 << 17]byte var x560 [1 << 17]byte var x561 [1 << 17]byte var x562 [1 << 17]byte var x563 [1 << 17]byte var x564 [1 << 17]byte var x565 [1 << 17]byte var x566 [1 << 17]byte var x567 [1 << 17]byte var x568 [1 << 17]byte var x569 [1 << 17]byte var x570 [1 << 17]byte var x571 [1 << 17]byte var x572 [1 << 17]byte var x573 [1 << 17]byte var x574 [1 << 17]byte var x575 [1 << 17]byte var x576 [1 << 17]byte var x577 [1 << 17]byte var x578 [1 << 17]byte var x579 [1 << 17]byte var x580 [1 << 17]byte var x581 [1 << 17]byte var x582 [1 << 17]byte var x583 [1 << 17]byte var x584 [1 << 17]byte var x585 [1 << 17]byte var x586 [1 << 17]byte var x587 [1 << 17]byte var x588 [1 << 17]byte var x589 [1 << 17]byte var x590 [1 << 17]byte var x591 [1 << 17]byte var x592 [1 << 17]byte var x593 [1 << 17]byte var x594 [1 << 17]byte var x595 [1 << 17]byte var x596 [1 << 17]byte var x597 [1 << 17]byte var x598 [1 << 17]byte var x599 [1 << 17]byte var x600 [1 << 17]byte var x601 [1 << 17]byte var x602 [1 << 17]byte var x603 [1 << 17]byte var x604 [1 << 17]byte var x605 [1 << 17]byte var x606 [1 << 17]byte var x607 [1 << 17]byte var x608 [1 << 17]byte var x609 [1 << 17]byte var x610 [1 << 17]byte var x611 [1 << 17]byte var x612 [1 << 17]byte var x613 [1 << 17]byte var x614 [1 << 17]byte var x615 [1 << 17]byte var x616 [1 << 17]byte var x617 [1 << 17]byte var x618 [1 << 17]byte var x619 [1 << 17]byte var x620 [1 << 17]byte var x621 [1 << 17]byte var x622 [1 << 17]byte var x623 [1 << 17]byte var x624 [1 << 17]byte var x625 [1 << 17]byte var x626 [1 << 17]byte var x627 [1 << 17]byte var x628 [1 << 17]byte var x629 [1 << 17]byte var x630 [1 << 17]byte var x631 [1 << 17]byte var x632 [1 << 17]byte var x633 [1 << 17]byte var x634 [1 << 17]byte var x635 [1 << 17]byte var x636 [1 << 17]byte var x637 [1 << 17]byte var x638 [1 << 17]byte var x639 [1 << 17]byte var x640 [1 << 17]byte var x641 [1 << 17]byte var x642 [1 << 17]byte var x643 [1 << 17]byte var x644 [1 << 17]byte var x645 [1 << 17]byte var x646 [1 << 17]byte var x647 [1 << 17]byte var x648 [1 << 17]byte var x649 [1 << 17]byte var x650 [1 << 17]byte var x651 [1 << 17]byte var x652 [1 << 17]byte var x653 [1 << 17]byte var x654 [1 << 17]byte var x655 [1 << 17]byte var x656 [1 << 17]byte var x657 [1 << 17]byte var x658 [1 << 17]byte var x659 [1 << 17]byte var x660 [1 << 17]byte var x661 [1 << 17]byte var x662 [1 << 17]byte var x663 [1 << 17]byte var x664 [1 << 17]byte var x665 [1 << 17]byte var x666 [1 << 17]byte var x667 [1 << 17]byte var x668 [1 << 17]byte var x669 [1 << 17]byte var x670 [1 << 17]byte var x671 [1 << 17]byte var x672 [1 << 17]byte var x673 [1 << 17]byte var x674 [1 << 17]byte var x675 [1 << 17]byte var x676 [1 << 17]byte var x677 [1 << 17]byte var x678 [1 << 17]byte var x679 [1 << 17]byte var x680 [1 << 17]byte var x681 [1 << 17]byte var x682 [1 << 17]byte var x683 [1 << 17]byte var x684 [1 << 17]byte var x685 [1 << 17]byte var x686 [1 << 17]byte var x687 [1 << 17]byte var x688 [1 << 17]byte var x689 [1 << 17]byte var x690 [1 << 17]byte var x691 [1 << 17]byte var x692 [1 << 17]byte var x693 [1 << 17]byte var x694 [1 << 17]byte var x695 [1 << 17]byte var x696 [1 << 17]byte var x697 [1 << 17]byte var x698 [1 << 17]byte var x699 [1 << 17]byte var x700 [1 << 17]byte var x701 [1 << 17]byte var x702 [1 << 17]byte var x703 [1 << 17]byte var x704 [1 << 17]byte var x705 [1 << 17]byte var x706 [1 << 17]byte var x707 [1 << 17]byte var x708 [1 << 17]byte var x709 [1 << 17]byte var x710 [1 << 17]byte var x711 [1 << 17]byte var x712 [1 << 17]byte var x713 [1 << 17]byte var x714 [1 << 17]byte var x715 [1 << 17]byte var x716 [1 << 17]byte var x717 [1 << 17]byte var x718 [1 << 17]byte var x719 [1 << 17]byte var x720 [1 << 17]byte var x721 [1 << 17]byte var x722 [1 << 17]byte var x723 [1 << 17]byte var x724 [1 << 17]byte var x725 [1 << 17]byte var x726 [1 << 17]byte var x727 [1 << 17]byte var x728 [1 << 17]byte var x729 [1 << 17]byte var x730 [1 << 17]byte var x731 [1 << 17]byte var x732 [1 << 17]byte var x733 [1 << 17]byte var x734 [1 << 17]byte var x735 [1 << 17]byte var x736 [1 << 17]byte var x737 [1 << 17]byte var x738 [1 << 17]byte var x739 [1 << 17]byte var x740 [1 << 17]byte var x741 [1 << 17]byte var x742 [1 << 17]byte var x743 [1 << 17]byte var x744 [1 << 17]byte var x745 [1 << 17]byte var x746 [1 << 17]byte var x747 [1 << 17]byte var x748 [1 << 17]byte var x749 [1 << 17]byte var x750 [1 << 17]byte var x751 [1 << 17]byte var x752 [1 << 17]byte var x753 [1 << 17]byte var x754 [1 << 17]byte var x755 [1 << 17]byte var x756 [1 << 17]byte var x757 [1 << 17]byte var x758 [1 << 17]byte var x759 [1 << 17]byte var x760 [1 << 17]byte var x761 [1 << 17]byte var x762 [1 << 17]byte var x763 [1 << 17]byte var x764 [1 << 17]byte var x765 [1 << 17]byte var x766 [1 << 17]byte var x767 [1 << 17]byte var x768 [1 << 17]byte var x769 [1 << 17]byte var x770 [1 << 17]byte var x771 [1 << 17]byte var x772 [1 << 17]byte var x773 [1 << 17]byte var x774 [1 << 17]byte var x775 [1 << 17]byte var x776 [1 << 17]byte var x777 [1 << 17]byte var x778 [1 << 17]byte var x779 [1 << 17]byte var x780 [1 << 17]byte var x781 [1 << 17]byte var x782 [1 << 17]byte var x783 [1 << 17]byte var x784 [1 << 17]byte var x785 [1 << 17]byte var x786 [1 << 17]byte var x787 [1 << 17]byte var x788 [1 << 17]byte var x789 [1 << 17]byte var x790 [1 << 17]byte var x791 [1 << 17]byte var x792 [1 << 17]byte var x793 [1 << 17]byte var x794 [1 << 17]byte var x795 [1 << 17]byte var x796 [1 << 17]byte var x797 [1 << 17]byte var x798 [1 << 17]byte var x799 [1 << 17]byte var x800 [1 << 17]byte var x801 [1 << 17]byte var x802 [1 << 17]byte var x803 [1 << 17]byte var x804 [1 << 17]byte var x805 [1 << 17]byte var x806 [1 << 17]byte var x807 [1 << 17]byte var x808 [1 << 17]byte var x809 [1 << 17]byte var x810 [1 << 17]byte var x811 [1 << 17]byte var x812 [1 << 17]byte var x813 [1 << 17]byte var x814 [1 << 17]byte var x815 [1 << 17]byte var x816 [1 << 17]byte var x817 [1 << 17]byte var x818 [1 << 17]byte var x819 [1 << 17]byte var x820 [1 << 17]byte var x821 [1 << 17]byte var x822 [1 << 17]byte var x823 [1 << 17]byte var x824 [1 << 17]byte var x825 [1 << 17]byte var x826 [1 << 17]byte var x827 [1 << 17]byte var x828 [1 << 17]byte var x829 [1 << 17]byte var x830 [1 << 17]byte var x831 [1 << 17]byte var x832 [1 << 17]byte var x833 [1 << 17]byte var x834 [1 << 17]byte var x835 [1 << 17]byte var x836 [1 << 17]byte var x837 [1 << 17]byte var x838 [1 << 17]byte var x839 [1 << 17]byte var x840 [1 << 17]byte var x841 [1 << 17]byte var x842 [1 << 17]byte var x843 [1 << 17]byte var x844 [1 << 17]byte var x845 [1 << 17]byte var x846 [1 << 17]byte var x847 [1 << 17]byte var x848 [1 << 17]byte var x849 [1 << 17]byte var x850 [1 << 17]byte var x851 [1 << 17]byte var x852 [1 << 17]byte var x853 [1 << 17]byte var x854 [1 << 17]byte var x855 [1 << 17]byte var x856 [1 << 17]byte var x857 [1 << 17]byte var x858 [1 << 17]byte var x859 [1 << 17]byte var x860 [1 << 17]byte var x861 [1 << 17]byte var x862 [1 << 17]byte var x863 [1 << 17]byte var x864 [1 << 17]byte var x865 [1 << 17]byte var x866 [1 << 17]byte var x867 [1 << 17]byte var x868 [1 << 17]byte var x869 [1 << 17]byte var x870 [1 << 17]byte var x871 [1 << 17]byte var x872 [1 << 17]byte var x873 [1 << 17]byte var x874 [1 << 17]byte var x875 [1 << 17]byte var x876 [1 << 17]byte var x877 [1 << 17]byte var x878 [1 << 17]byte var x879 [1 << 17]byte var x880 [1 << 17]byte var x881 [1 << 17]byte var x882 [1 << 17]byte var x883 [1 << 17]byte var x884 [1 << 17]byte var x885 [1 << 17]byte var x886 [1 << 17]byte var x887 [1 << 17]byte var x888 [1 << 17]byte var x889 [1 << 17]byte var x890 [1 << 17]byte var x891 [1 << 17]byte var x892 [1 << 17]byte var x893 [1 << 17]byte var x894 [1 << 17]byte var x895 [1 << 17]byte var x896 [1 << 17]byte var x897 [1 << 17]byte var x898 [1 << 17]byte var x899 [1 << 17]byte var x900 [1 << 17]byte var x901 [1 << 17]byte var x902 [1 << 17]byte var x903 [1 << 17]byte var x904 [1 << 17]byte var x905 [1 << 17]byte var x906 [1 << 17]byte var x907 [1 << 17]byte var x908 [1 << 17]byte var x909 [1 << 17]byte var x910 [1 << 17]byte var x911 [1 << 17]byte var x912 [1 << 17]byte var x913 [1 << 17]byte var x914 [1 << 17]byte var x915 [1 << 17]byte var x916 [1 << 17]byte var x917 [1 << 17]byte var x918 [1 << 17]byte var x919 [1 << 17]byte var x920 [1 << 17]byte var x921 [1 << 17]byte var x922 [1 << 17]byte var x923 [1 << 17]byte var x924 [1 << 17]byte var x925 [1 << 17]byte var x926 [1 << 17]byte var x927 [1 << 17]byte var x928 [1 << 17]byte var x929 [1 << 17]byte var x930 [1 << 17]byte var x931 [1 << 17]byte var x932 [1 << 17]byte var x933 [1 << 17]byte var x934 [1 << 17]byte var x935 [1 << 17]byte var x936 [1 << 17]byte var x937 [1 << 17]byte var x938 [1 << 17]byte var x939 [1 << 17]byte var x940 [1 << 17]byte var x941 [1 << 17]byte var x942 [1 << 17]byte var x943 [1 << 17]byte var x944 [1 << 17]byte var x945 [1 << 17]byte var x946 [1 << 17]byte var x947 [1 << 17]byte var x948 [1 << 17]byte var x949 [1 << 17]byte var x950 [1 << 17]byte var x951 [1 << 17]byte var x952 [1 << 17]byte var x953 [1 << 17]byte var x954 [1 << 17]byte var x955 [1 << 17]byte var x956 [1 << 17]byte var x957 [1 << 17]byte var x958 [1 << 17]byte var x959 [1 << 17]byte var x960 [1 << 17]byte var x961 [1 << 17]byte var x962 [1 << 17]byte var x963 [1 << 17]byte var x964 [1 << 17]byte var x965 [1 << 17]byte var x966 [1 << 17]byte var x967 [1 << 17]byte var x968 [1 << 17]byte var x969 [1 << 17]byte var x970 [1 << 17]byte var x971 [1 << 17]byte var x972 [1 << 17]byte var x973 [1 << 17]byte var x974 [1 << 17]byte var x975 [1 << 17]byte var x976 [1 << 17]byte var x977 [1 << 17]byte var x978 [1 << 17]byte var x979 [1 << 17]byte var x980 [1 << 17]byte var x981 [1 << 17]byte var x982 [1 << 17]byte var x983 [1 << 17]byte var x984 [1 << 17]byte var x985 [1 << 17]byte var x986 [1 << 17]byte var x987 [1 << 17]byte var x988 [1 << 17]byte var x989 [1 << 17]byte var x990 [1 << 17]byte var x991 [1 << 17]byte var x992 [1 << 17]byte var x993 [1 << 17]byte var x994 [1 << 17]byte var x995 [1 << 17]byte var x996 [1 << 17]byte var x997 [1 << 17]byte var x998 [1 << 17]byte var x999 [1 << 17]byte var x1000 [1 << 17]byte var x1001 [1 << 17]byte var x1002 [1 << 17]byte var x1003 [1 << 17]byte var x1004 [1 << 17]byte var x1005 [1 << 17]byte var x1006 [1 << 17]byte var x1007 [1 << 17]byte var x1008 [1 << 17]byte var x1009 [1 << 17]byte var x1010 [1 << 17]byte var x1011 [1 << 17]byte var x1012 [1 << 17]byte var x1013 [1 << 17]byte var x1014 [1 << 17]byte var x1015 [1 << 17]byte var x1016 [1 << 17]byte var x1017 [1 << 17]byte var x1018 [1 << 17]byte var x1019 [1 << 17]byte var x1020 [1 << 17]byte var x1021 [1 << 17]byte var x1022 [1 << 17]byte var x1023 [1 << 17]byte var x1024 [1 << 17]byte var x1025 [1 << 17]byte var x1026 [1 << 17]byte var x1027 [1 << 17]byte var x1028 [1 << 17]byte var x1029 [1 << 17]byte var x1030 [1 << 17]byte var x1031 [1 << 17]byte var x1032 [1 << 17]byte var x1033 [1 << 17]byte var x1034 [1 << 17]byte var x1035 [1 << 17]byte var x1036 [1 << 17]byte var x1037 [1 << 17]byte var x1038 [1 << 17]byte var x1039 [1 << 17]byte var x1040 [1 << 17]byte var x1041 [1 << 17]byte var x1042 [1 << 17]byte var x1043 [1 << 17]byte var x1044 [1 << 17]byte var x1045 [1 << 17]byte var x1046 [1 << 17]byte var x1047 [1 << 17]byte var x1048 [1 << 17]byte var x1049 [1 << 17]byte var x1050 [1 << 17]byte var x1051 [1 << 17]byte var x1052 [1 << 17]byte var x1053 [1 << 17]byte var x1054 [1 << 17]byte var x1055 [1 << 17]byte var x1056 [1 << 17]byte var x1057 [1 << 17]byte var x1058 [1 << 17]byte var x1059 [1 << 17]byte var x1060 [1 << 17]byte var x1061 [1 << 17]byte var x1062 [1 << 17]byte var x1063 [1 << 17]byte var x1064 [1 << 17]byte var x1065 [1 << 17]byte var x1066 [1 << 17]byte var x1067 [1 << 17]byte var x1068 [1 << 17]byte var x1069 [1 << 17]byte var x1070 [1 << 17]byte var x1071 [1 << 17]byte var x1072 [1 << 17]byte var x1073 [1 << 17]byte var x1074 [1 << 17]byte var x1075 [1 << 17]byte var x1076 [1 << 17]byte var x1077 [1 << 17]byte var x1078 [1 << 17]byte var x1079 [1 << 17]byte var x1080 [1 << 17]byte var x1081 [1 << 17]byte var x1082 [1 << 17]byte var x1083 [1 << 17]byte var x1084 [1 << 17]byte var x1085 [1 << 17]byte var x1086 [1 << 17]byte var x1087 [1 << 17]byte var x1088 [1 << 17]byte var x1089 [1 << 17]byte var x1090 [1 << 17]byte var x1091 [1 << 17]byte var x1092 [1 << 17]byte var x1093 [1 << 17]byte var x1094 [1 << 17]byte var x1095 [1 << 17]byte var x1096 [1 << 17]byte var x1097 [1 << 17]byte var x1098 [1 << 17]byte var x1099 [1 << 17]byte var x1100 [1 << 17]byte var x1101 [1 << 17]byte var x1102 [1 << 17]byte var x1103 [1 << 17]byte var x1104 [1 << 17]byte var x1105 [1 << 17]byte var x1106 [1 << 17]byte var x1107 [1 << 17]byte var x1108 [1 << 17]byte var x1109 [1 << 17]byte var x1110 [1 << 17]byte var x1111 [1 << 17]byte var x1112 [1 << 17]byte var x1113 [1 << 17]byte var x1114 [1 << 17]byte var x1115 [1 << 17]byte var x1116 [1 << 17]byte var x1117 [1 << 17]byte var x1118 [1 << 17]byte var x1119 [1 << 17]byte var x1120 [1 << 17]byte var x1121 [1 << 17]byte var x1122 [1 << 17]byte var x1123 [1 << 17]byte var x1124 [1 << 17]byte var x1125 [1 << 17]byte var x1126 [1 << 17]byte var x1127 [1 << 17]byte var x1128 [1 << 17]byte var x1129 [1 << 17]byte var x1130 [1 << 17]byte var x1131 [1 << 17]byte var x1132 [1 << 17]byte var x1133 [1 << 17]byte var x1134 [1 << 17]byte var x1135 [1 << 17]byte var x1136 [1 << 17]byte var x1137 [1 << 17]byte var x1138 [1 << 17]byte var x1139 [1 << 17]byte var x1140 [1 << 17]byte var x1141 [1 << 17]byte var x1142 [1 << 17]byte var x1143 [1 << 17]byte var x1144 [1 << 17]byte var x1145 [1 << 17]byte var x1146 [1 << 17]byte var x1147 [1 << 17]byte var x1148 [1 << 17]byte var x1149 [1 << 17]byte var x1150 [1 << 17]byte var x1151 [1 << 17]byte var x1152 [1 << 17]byte var x1153 [1 << 17]byte var x1154 [1 << 17]byte var x1155 [1 << 17]byte var x1156 [1 << 17]byte var x1157 [1 << 17]byte var x1158 [1 << 17]byte var x1159 [1 << 17]byte var x1160 [1 << 17]byte var x1161 [1 << 17]byte var x1162 [1 << 17]byte var x1163 [1 << 17]byte var x1164 [1 << 17]byte var x1165 [1 << 17]byte var x1166 [1 << 17]byte var x1167 [1 << 17]byte var x1168 [1 << 17]byte var x1169 [1 << 17]byte var x1170 [1 << 17]byte var x1171 [1 << 17]byte var x1172 [1 << 17]byte var x1173 [1 << 17]byte var x1174 [1 << 17]byte var x1175 [1 << 17]byte var x1176 [1 << 17]byte var x1177 [1 << 17]byte var x1178 [1 << 17]byte var x1179 [1 << 17]byte var x1180 [1 << 17]byte var x1181 [1 << 17]byte var x1182 [1 << 17]byte var x1183 [1 << 17]byte var x1184 [1 << 17]byte var x1185 [1 << 17]byte var x1186 [1 << 17]byte var x1187 [1 << 17]byte var x1188 [1 << 17]byte var x1189 [1 << 17]byte var x1190 [1 << 17]byte var x1191 [1 << 17]byte var x1192 [1 << 17]byte var x1193 [1 << 17]byte var x1194 [1 << 17]byte var x1195 [1 << 17]byte var x1196 [1 << 17]byte var x1197 [1 << 17]byte var x1198 [1 << 17]byte var x1199 [1 << 17]byte var x1200 [1 << 17]byte var x1201 [1 << 17]byte var x1202 [1 << 17]byte var x1203 [1 << 17]byte var x1204 [1 << 17]byte var x1205 [1 << 17]byte var x1206 [1 << 17]byte var x1207 [1 << 17]byte var x1208 [1 << 17]byte var x1209 [1 << 17]byte var x1210 [1 << 17]byte var x1211 [1 << 17]byte var x1212 [1 << 17]byte var x1213 [1 << 17]byte var x1214 [1 << 17]byte var x1215 [1 << 17]byte var x1216 [1 << 17]byte var x1217 [1 << 17]byte var x1218 [1 << 17]byte var x1219 [1 << 17]byte var x1220 [1 << 17]byte var x1221 [1 << 17]byte var x1222 [1 << 17]byte var x1223 [1 << 17]byte var x1224 [1 << 17]byte var x1225 [1 << 17]byte var x1226 [1 << 17]byte var x1227 [1 << 17]byte var x1228 [1 << 17]byte var x1229 [1 << 17]byte var x1230 [1 << 17]byte var x1231 [1 << 17]byte var x1232 [1 << 17]byte var x1233 [1 << 17]byte var x1234 [1 << 17]byte var x1235 [1 << 17]byte var x1236 [1 << 17]byte var x1237 [1 << 17]byte var x1238 [1 << 17]byte var x1239 [1 << 17]byte var x1240 [1 << 17]byte var x1241 [1 << 17]byte var x1242 [1 << 17]byte var x1243 [1 << 17]byte var x1244 [1 << 17]byte var x1245 [1 << 17]byte var x1246 [1 << 17]byte var x1247 [1 << 17]byte var x1248 [1 << 17]byte var x1249 [1 << 17]byte var x1250 [1 << 17]byte var x1251 [1 << 17]byte var x1252 [1 << 17]byte var x1253 [1 << 17]byte var x1254 [1 << 17]byte var x1255 [1 << 17]byte var x1256 [1 << 17]byte var x1257 [1 << 17]byte var x1258 [1 << 17]byte var x1259 [1 << 17]byte var x1260 [1 << 17]byte var x1261 [1 << 17]byte var x1262 [1 << 17]byte var x1263 [1 << 17]byte var x1264 [1 << 17]byte var x1265 [1 << 17]byte var x1266 [1 << 17]byte var x1267 [1 << 17]byte var x1268 [1 << 17]byte var x1269 [1 << 17]byte var x1270 [1 << 17]byte var x1271 [1 << 17]byte var x1272 [1 << 17]byte var x1273 [1 << 17]byte var x1274 [1 << 17]byte var x1275 [1 << 17]byte var x1276 [1 << 17]byte var x1277 [1 << 17]byte var x1278 [1 << 17]byte var x1279 [1 << 17]byte var x1280 [1 << 17]byte var x1281 [1 << 17]byte var x1282 [1 << 17]byte var x1283 [1 << 17]byte var x1284 [1 << 17]byte var x1285 [1 << 17]byte var x1286 [1 << 17]byte var x1287 [1 << 17]byte var x1288 [1 << 17]byte var x1289 [1 << 17]byte var x1290 [1 << 17]byte var x1291 [1 << 17]byte var x1292 [1 << 17]byte var x1293 [1 << 17]byte var x1294 [1 << 17]byte var x1295 [1 << 17]byte var x1296 [1 << 17]byte var x1297 [1 << 17]byte var x1298 [1 << 17]byte var x1299 [1 << 17]byte var x1300 [1 << 17]byte var x1301 [1 << 17]byte var x1302 [1 << 17]byte var x1303 [1 << 17]byte var x1304 [1 << 17]byte var x1305 [1 << 17]byte var x1306 [1 << 17]byte var x1307 [1 << 17]byte var x1308 [1 << 17]byte var x1309 [1 << 17]byte var x1310 [1 << 17]byte var x1311 [1 << 17]byte var x1312 [1 << 17]byte var x1313 [1 << 17]byte var x1314 [1 << 17]byte var x1315 [1 << 17]byte var x1316 [1 << 17]byte var x1317 [1 << 17]byte var x1318 [1 << 17]byte var x1319 [1 << 17]byte var x1320 [1 << 17]byte var x1321 [1 << 17]byte var x1322 [1 << 17]byte var x1323 [1 << 17]byte var x1324 [1 << 17]byte var x1325 [1 << 17]byte var x1326 [1 << 17]byte var x1327 [1 << 17]byte var x1328 [1 << 17]byte var x1329 [1 << 17]byte var x1330 [1 << 17]byte var x1331 [1 << 17]byte var x1332 [1 << 17]byte var x1333 [1 << 17]byte var x1334 [1 << 17]byte var x1335 [1 << 17]byte var x1336 [1 << 17]byte var x1337 [1 << 17]byte var x1338 [1 << 17]byte var x1339 [1 << 17]byte var x1340 [1 << 17]byte var x1341 [1 << 17]byte var x1342 [1 << 17]byte var x1343 [1 << 17]byte var x1344 [1 << 17]byte var x1345 [1 << 17]byte var x1346 [1 << 17]byte var x1347 [1 << 17]byte var x1348 [1 << 17]byte var x1349 [1 << 17]byte var x1350 [1 << 17]byte var x1351 [1 << 17]byte var x1352 [1 << 17]byte var x1353 [1 << 17]byte var x1354 [1 << 17]byte var x1355 [1 << 17]byte var x1356 [1 << 17]byte var x1357 [1 << 17]byte var x1358 [1 << 17]byte var x1359 [1 << 17]byte var x1360 [1 << 17]byte var x1361 [1 << 17]byte var x1362 [1 << 17]byte var x1363 [1 << 17]byte var x1364 [1 << 17]byte var x1365 [1 << 17]byte var x1366 [1 << 17]byte var x1367 [1 << 17]byte var x1368 [1 << 17]byte var x1369 [1 << 17]byte var x1370 [1 << 17]byte var x1371 [1 << 17]byte var x1372 [1 << 17]byte var x1373 [1 << 17]byte var x1374 [1 << 17]byte var x1375 [1 << 17]byte var x1376 [1 << 17]byte var x1377 [1 << 17]byte var x1378 [1 << 17]byte var x1379 [1 << 17]byte var x1380 [1 << 17]byte var x1381 [1 << 17]byte var x1382 [1 << 17]byte var x1383 [1 << 17]byte var x1384 [1 << 17]byte var x1385 [1 << 17]byte var x1386 [1 << 17]byte var x1387 [1 << 17]byte var x1388 [1 << 17]byte var x1389 [1 << 17]byte var x1390 [1 << 17]byte var x1391 [1 << 17]byte var x1392 [1 << 17]byte var x1393 [1 << 17]byte var x1394 [1 << 17]byte var x1395 [1 << 17]byte var x1396 [1 << 17]byte var x1397 [1 << 17]byte var x1398 [1 << 17]byte var x1399 [1 << 17]byte var x1400 [1 << 17]byte var x1401 [1 << 17]byte var x1402 [1 << 17]byte var x1403 [1 << 17]byte var x1404 [1 << 17]byte var x1405 [1 << 17]byte var x1406 [1 << 17]byte var x1407 [1 << 17]byte var x1408 [1 << 17]byte var x1409 [1 << 17]byte var x1410 [1 << 17]byte var x1411 [1 << 17]byte var x1412 [1 << 17]byte var x1413 [1 << 17]byte var x1414 [1 << 17]byte var x1415 [1 << 17]byte var x1416 [1 << 17]byte var x1417 [1 << 17]byte var x1418 [1 << 17]byte var x1419 [1 << 17]byte var x1420 [1 << 17]byte var x1421 [1 << 17]byte var x1422 [1 << 17]byte var x1423 [1 << 17]byte var x1424 [1 << 17]byte var x1425 [1 << 17]byte var x1426 [1 << 17]byte var x1427 [1 << 17]byte var x1428 [1 << 17]byte var x1429 [1 << 17]byte var x1430 [1 << 17]byte var x1431 [1 << 17]byte var x1432 [1 << 17]byte var x1433 [1 << 17]byte var x1434 [1 << 17]byte var x1435 [1 << 17]byte var x1436 [1 << 17]byte var x1437 [1 << 17]byte var x1438 [1 << 17]byte var x1439 [1 << 17]byte var x1440 [1 << 17]byte var x1441 [1 << 17]byte var x1442 [1 << 17]byte var x1443 [1 << 17]byte var x1444 [1 << 17]byte var x1445 [1 << 17]byte var x1446 [1 << 17]byte var x1447 [1 << 17]byte var x1448 [1 << 17]byte var x1449 [1 << 17]byte var x1450 [1 << 17]byte var x1451 [1 << 17]byte var x1452 [1 << 17]byte var x1453 [1 << 17]byte var x1454 [1 << 17]byte var x1455 [1 << 17]byte var x1456 [1 << 17]byte var x1457 [1 << 17]byte var x1458 [1 << 17]byte var x1459 [1 << 17]byte var x1460 [1 << 17]byte var x1461 [1 << 17]byte var x1462 [1 << 17]byte var x1463 [1 << 17]byte var x1464 [1 << 17]byte var x1465 [1 << 17]byte var x1466 [1 << 17]byte var x1467 [1 << 17]byte var x1468 [1 << 17]byte var x1469 [1 << 17]byte var x1470 [1 << 17]byte var x1471 [1 << 17]byte var x1472 [1 << 17]byte var x1473 [1 << 17]byte var x1474 [1 << 17]byte var x1475 [1 << 17]byte var x1476 [1 << 17]byte var x1477 [1 << 17]byte var x1478 [1 << 17]byte var x1479 [1 << 17]byte var x1480 [1 << 17]byte var x1481 [1 << 17]byte var x1482 [1 << 17]byte var x1483 [1 << 17]byte var x1484 [1 << 17]byte var x1485 [1 << 17]byte var x1486 [1 << 17]byte var x1487 [1 << 17]byte var x1488 [1 << 17]byte var x1489 [1 << 17]byte var x1490 [1 << 17]byte var x1491 [1 << 17]byte var x1492 [1 << 17]byte var x1493 [1 << 17]byte var x1494 [1 << 17]byte var x1495 [1 << 17]byte var x1496 [1 << 17]byte var x1497 [1 << 17]byte var x1498 [1 << 17]byte var x1499 [1 << 17]byte var x1500 [1 << 17]byte var x1501 [1 << 17]byte var x1502 [1 << 17]byte var x1503 [1 << 17]byte var x1504 [1 << 17]byte var x1505 [1 << 17]byte var x1506 [1 << 17]byte var x1507 [1 << 17]byte var x1508 [1 << 17]byte var x1509 [1 << 17]byte var x1510 [1 << 17]byte var x1511 [1 << 17]byte var x1512 [1 << 17]byte var x1513 [1 << 17]byte var x1514 [1 << 17]byte var x1515 [1 << 17]byte var x1516 [1 << 17]byte var x1517 [1 << 17]byte var x1518 [1 << 17]byte var x1519 [1 << 17]byte var x1520 [1 << 17]byte var x1521 [1 << 17]byte var x1522 [1 << 17]byte var x1523 [1 << 17]byte var x1524 [1 << 17]byte var x1525 [1 << 17]byte var x1526 [1 << 17]byte var x1527 [1 << 17]byte var x1528 [1 << 17]byte var x1529 [1 << 17]byte var x1530 [1 << 17]byte var x1531 [1 << 17]byte var x1532 [1 << 17]byte var x1533 [1 << 17]byte var x1534 [1 << 17]byte var x1535 [1 << 17]byte var x1536 [1 << 17]byte var x1537 [1 << 17]byte var x1538 [1 << 17]byte var x1539 [1 << 17]byte var x1540 [1 << 17]byte var x1541 [1 << 17]byte var x1542 [1 << 17]byte var x1543 [1 << 17]byte var x1544 [1 << 17]byte var x1545 [1 << 17]byte var x1546 [1 << 17]byte var x1547 [1 << 17]byte var x1548 [1 << 17]byte var x1549 [1 << 17]byte var x1550 [1 << 17]byte var x1551 [1 << 17]byte var x1552 [1 << 17]byte var x1553 [1 << 17]byte var x1554 [1 << 17]byte var x1555 [1 << 17]byte var x1556 [1 << 17]byte var x1557 [1 << 17]byte var x1558 [1 << 17]byte var x1559 [1 << 17]byte var x1560 [1 << 17]byte var x1561 [1 << 17]byte var x1562 [1 << 17]byte var x1563 [1 << 17]byte var x1564 [1 << 17]byte var x1565 [1 << 17]byte var x1566 [1 << 17]byte var x1567 [1 << 17]byte var x1568 [1 << 17]byte var x1569 [1 << 17]byte var x1570 [1 << 17]byte var x1571 [1 << 17]byte var x1572 [1 << 17]byte var x1573 [1 << 17]byte var x1574 [1 << 17]byte var x1575 [1 << 17]byte var x1576 [1 << 17]byte var x1577 [1 << 17]byte var x1578 [1 << 17]byte var x1579 [1 << 17]byte var x1580 [1 << 17]byte var x1581 [1 << 17]byte var x1582 [1 << 17]byte var x1583 [1 << 17]byte var x1584 [1 << 17]byte var x1585 [1 << 17]byte var x1586 [1 << 17]byte var x1587 [1 << 17]byte var x1588 [1 << 17]byte var x1589 [1 << 17]byte var x1590 [1 << 17]byte var x1591 [1 << 17]byte var x1592 [1 << 17]byte var x1593 [1 << 17]byte var x1594 [1 << 17]byte var x1595 [1 << 17]byte var x1596 [1 << 17]byte var x1597 [1 << 17]byte var x1598 [1 << 17]byte var x1599 [1 << 17]byte var x1600 [1 << 17]byte var x1601 [1 << 17]byte var x1602 [1 << 17]byte var x1603 [1 << 17]byte var x1604 [1 << 17]byte var x1605 [1 << 17]byte var x1606 [1 << 17]byte var x1607 [1 << 17]byte var x1608 [1 << 17]byte var x1609 [1 << 17]byte var x1610 [1 << 17]byte var x1611 [1 << 17]byte var x1612 [1 << 17]byte var x1613 [1 << 17]byte var x1614 [1 << 17]byte var x1615 [1 << 17]byte var x1616 [1 << 17]byte var x1617 [1 << 17]byte var x1618 [1 << 17]byte var x1619 [1 << 17]byte var x1620 [1 << 17]byte var x1621 [1 << 17]byte var x1622 [1 << 17]byte var x1623 [1 << 17]byte var x1624 [1 << 17]byte var x1625 [1 << 17]byte var x1626 [1 << 17]byte var x1627 [1 << 17]byte var x1628 [1 << 17]byte var x1629 [1 << 17]byte var x1630 [1 << 17]byte var x1631 [1 << 17]byte var x1632 [1 << 17]byte var x1633 [1 << 17]byte var x1634 [1 << 17]byte var x1635 [1 << 17]byte var x1636 [1 << 17]byte var x1637 [1 << 17]byte var x1638 [1 << 17]byte var x1639 [1 << 17]byte var x1640 [1 << 17]byte var x1641 [1 << 17]byte var x1642 [1 << 17]byte var x1643 [1 << 17]byte var x1644 [1 << 17]byte var x1645 [1 << 17]byte var x1646 [1 << 17]byte var x1647 [1 << 17]byte var x1648 [1 << 17]byte var x1649 [1 << 17]byte var x1650 [1 << 17]byte var x1651 [1 << 17]byte var x1652 [1 << 17]byte var x1653 [1 << 17]byte var x1654 [1 << 17]byte var x1655 [1 << 17]byte var x1656 [1 << 17]byte var x1657 [1 << 17]byte var x1658 [1 << 17]byte var x1659 [1 << 17]byte var x1660 [1 << 17]byte var x1661 [1 << 17]byte var x1662 [1 << 17]byte var x1663 [1 << 17]byte var x1664 [1 << 17]byte var x1665 [1 << 17]byte var x1666 [1 << 17]byte var x1667 [1 << 17]byte var x1668 [1 << 17]byte var x1669 [1 << 17]byte var x1670 [1 << 17]byte var x1671 [1 << 17]byte var x1672 [1 << 17]byte var x1673 [1 << 17]byte var x1674 [1 << 17]byte var x1675 [1 << 17]byte var x1676 [1 << 17]byte var x1677 [1 << 17]byte var x1678 [1 << 17]byte var x1679 [1 << 17]byte var x1680 [1 << 17]byte var x1681 [1 << 17]byte var x1682 [1 << 17]byte var x1683 [1 << 17]byte var x1684 [1 << 17]byte var x1685 [1 << 17]byte var x1686 [1 << 17]byte var x1687 [1 << 17]byte var x1688 [1 << 17]byte var x1689 [1 << 17]byte var x1690 [1 << 17]byte var x1691 [1 << 17]byte var x1692 [1 << 17]byte var x1693 [1 << 17]byte var x1694 [1 << 17]byte var x1695 [1 << 17]byte var x1696 [1 << 17]byte var x1697 [1 << 17]byte var x1698 [1 << 17]byte var x1699 [1 << 17]byte var x1700 [1 << 17]byte var x1701 [1 << 17]byte var x1702 [1 << 17]byte var x1703 [1 << 17]byte var x1704 [1 << 17]byte var x1705 [1 << 17]byte var x1706 [1 << 17]byte var x1707 [1 << 17]byte var x1708 [1 << 17]byte var x1709 [1 << 17]byte var x1710 [1 << 17]byte var x1711 [1 << 17]byte var x1712 [1 << 17]byte var x1713 [1 << 17]byte var x1714 [1 << 17]byte var x1715 [1 << 17]byte var x1716 [1 << 17]byte var x1717 [1 << 17]byte var x1718 [1 << 17]byte var x1719 [1 << 17]byte var x1720 [1 << 17]byte var x1721 [1 << 17]byte var x1722 [1 << 17]byte var x1723 [1 << 17]byte var x1724 [1 << 17]byte var x1725 [1 << 17]byte var x1726 [1 << 17]byte var x1727 [1 << 17]byte var x1728 [1 << 17]byte var x1729 [1 << 17]byte var x1730 [1 << 17]byte var x1731 [1 << 17]byte var x1732 [1 << 17]byte var x1733 [1 << 17]byte var x1734 [1 << 17]byte var x1735 [1 << 17]byte var x1736 [1 << 17]byte var x1737 [1 << 17]byte var x1738 [1 << 17]byte var x1739 [1 << 17]byte var x1740 [1 << 17]byte var x1741 [1 << 17]byte var x1742 [1 << 17]byte var x1743 [1 << 17]byte var x1744 [1 << 17]byte var x1745 [1 << 17]byte var x1746 [1 << 17]byte var x1747 [1 << 17]byte var x1748 [1 << 17]byte var x1749 [1 << 17]byte var x1750 [1 << 17]byte var x1751 [1 << 17]byte var x1752 [1 << 17]byte var x1753 [1 << 17]byte var x1754 [1 << 17]byte var x1755 [1 << 17]byte var x1756 [1 << 17]byte var x1757 [1 << 17]byte var x1758 [1 << 17]byte var x1759 [1 << 17]byte var x1760 [1 << 17]byte var x1761 [1 << 17]byte var x1762 [1 << 17]byte var x1763 [1 << 17]byte var x1764 [1 << 17]byte var x1765 [1 << 17]byte var x1766 [1 << 17]byte var x1767 [1 << 17]byte var x1768 [1 << 17]byte var x1769 [1 << 17]byte var x1770 [1 << 17]byte var x1771 [1 << 17]byte var x1772 [1 << 17]byte var x1773 [1 << 17]byte var x1774 [1 << 17]byte var x1775 [1 << 17]byte var x1776 [1 << 17]byte var x1777 [1 << 17]byte var x1778 [1 << 17]byte var x1779 [1 << 17]byte var x1780 [1 << 17]byte var x1781 [1 << 17]byte var x1782 [1 << 17]byte var x1783 [1 << 17]byte var x1784 [1 << 17]byte var x1785 [1 << 17]byte var x1786 [1 << 17]byte var x1787 [1 << 17]byte var x1788 [1 << 17]byte var x1789 [1 << 17]byte var x1790 [1 << 17]byte var x1791 [1 << 17]byte var x1792 [1 << 17]byte var x1793 [1 << 17]byte var x1794 [1 << 17]byte var x1795 [1 << 17]byte var x1796 [1 << 17]byte var x1797 [1 << 17]byte var x1798 [1 << 17]byte var x1799 [1 << 17]byte var x1800 [1 << 17]byte var x1801 [1 << 17]byte var x1802 [1 << 17]byte var x1803 [1 << 17]byte var x1804 [1 << 17]byte var x1805 [1 << 17]byte var x1806 [1 << 17]byte var x1807 [1 << 17]byte var x1808 [1 << 17]byte var x1809 [1 << 17]byte var x1810 [1 << 17]byte var x1811 [1 << 17]byte var x1812 [1 << 17]byte var x1813 [1 << 17]byte var x1814 [1 << 17]byte var x1815 [1 << 17]byte var x1816 [1 << 17]byte var x1817 [1 << 17]byte var x1818 [1 << 17]byte var x1819 [1 << 17]byte var x1820 [1 << 17]byte var x1821 [1 << 17]byte var x1822 [1 << 17]byte var x1823 [1 << 17]byte var x1824 [1 << 17]byte var x1825 [1 << 17]byte var x1826 [1 << 17]byte var x1827 [1 << 17]byte var x1828 [1 << 17]byte var x1829 [1 << 17]byte var x1830 [1 << 17]byte var x1831 [1 << 17]byte var x1832 [1 << 17]byte var x1833 [1 << 17]byte var x1834 [1 << 17]byte var x1835 [1 << 17]byte var x1836 [1 << 17]byte var x1837 [1 << 17]byte var x1838 [1 << 17]byte var x1839 [1 << 17]byte var x1840 [1 << 17]byte var x1841 [1 << 17]byte var x1842 [1 << 17]byte var x1843 [1 << 17]byte var x1844 [1 << 17]byte var x1845 [1 << 17]byte var x1846 [1 << 17]byte var x1847 [1 << 17]byte var x1848 [1 << 17]byte var x1849 [1 << 17]byte var x1850 [1 << 17]byte var x1851 [1 << 17]byte var x1852 [1 << 17]byte var x1853 [1 << 17]byte var x1854 [1 << 17]byte var x1855 [1 << 17]byte var x1856 [1 << 17]byte var x1857 [1 << 17]byte var x1858 [1 << 17]byte var x1859 [1 << 17]byte var x1860 [1 << 17]byte var x1861 [1 << 17]byte var x1862 [1 << 17]byte var x1863 [1 << 17]byte var x1864 [1 << 17]byte var x1865 [1 << 17]byte var x1866 [1 << 17]byte var x1867 [1 << 17]byte var x1868 [1 << 17]byte var x1869 [1 << 17]byte var x1870 [1 << 17]byte var x1871 [1 << 17]byte var x1872 [1 << 17]byte var x1873 [1 << 17]byte var x1874 [1 << 17]byte var x1875 [1 << 17]byte var x1876 [1 << 17]byte var x1877 [1 << 17]byte var x1878 [1 << 17]byte var x1879 [1 << 17]byte var x1880 [1 << 17]byte var x1881 [1 << 17]byte var x1882 [1 << 17]byte var x1883 [1 << 17]byte var x1884 [1 << 17]byte var x1885 [1 << 17]byte var x1886 [1 << 17]byte var x1887 [1 << 17]byte var x1888 [1 << 17]byte var x1889 [1 << 17]byte var x1890 [1 << 17]byte var x1891 [1 << 17]byte var x1892 [1 << 17]byte var x1893 [1 << 17]byte var x1894 [1 << 17]byte var x1895 [1 << 17]byte var x1896 [1 << 17]byte var x1897 [1 << 17]byte var x1898 [1 << 17]byte var x1899 [1 << 17]byte var x1900 [1 << 17]byte var x1901 [1 << 17]byte var x1902 [1 << 17]byte var x1903 [1 << 17]byte var x1904 [1 << 17]byte var x1905 [1 << 17]byte var x1906 [1 << 17]byte var x1907 [1 << 17]byte var x1908 [1 << 17]byte var x1909 [1 << 17]byte var x1910 [1 << 17]byte var x1911 [1 << 17]byte var x1912 [1 << 17]byte var x1913 [1 << 17]byte var x1914 [1 << 17]byte var x1915 [1 << 17]byte var x1916 [1 << 17]byte var x1917 [1 << 17]byte var x1918 [1 << 17]byte var x1919 [1 << 17]byte var x1920 [1 << 17]byte var x1921 [1 << 17]byte var x1922 [1 << 17]byte var x1923 [1 << 17]byte var x1924 [1 << 17]byte var x1925 [1 << 17]byte var x1926 [1 << 17]byte var x1927 [1 << 17]byte var x1928 [1 << 17]byte var x1929 [1 << 17]byte var x1930 [1 << 17]byte var x1931 [1 << 17]byte var x1932 [1 << 17]byte var x1933 [1 << 17]byte var x1934 [1 << 17]byte var x1935 [1 << 17]byte var x1936 [1 << 17]byte var x1937 [1 << 17]byte var x1938 [1 << 17]byte var x1939 [1 << 17]byte var x1940 [1 << 17]byte var x1941 [1 << 17]byte var x1942 [1 << 17]byte var x1943 [1 << 17]byte var x1944 [1 << 17]byte var x1945 [1 << 17]byte var x1946 [1 << 17]byte var x1947 [1 << 17]byte var x1948 [1 << 17]byte var x1949 [1 << 17]byte var x1950 [1 << 17]byte var x1951 [1 << 17]byte var x1952 [1 << 17]byte var x1953 [1 << 17]byte var x1954 [1 << 17]byte var x1955 [1 << 17]byte var x1956 [1 << 17]byte var x1957 [1 << 17]byte var x1958 [1 << 17]byte var x1959 [1 << 17]byte var x1960 [1 << 17]byte var x1961 [1 << 17]byte var x1962 [1 << 17]byte var x1963 [1 << 17]byte var x1964 [1 << 17]byte var x1965 [1 << 17]byte var x1966 [1 << 17]byte var x1967 [1 << 17]byte var x1968 [1 << 17]byte var x1969 [1 << 17]byte var x1970 [1 << 17]byte var x1971 [1 << 17]byte var x1972 [1 << 17]byte var x1973 [1 << 17]byte var x1974 [1 << 17]byte var x1975 [1 << 17]byte var x1976 [1 << 17]byte var x1977 [1 << 17]byte var x1978 [1 << 17]byte var x1979 [1 << 17]byte var x1980 [1 << 17]byte var x1981 [1 << 17]byte var x1982 [1 << 17]byte var x1983 [1 << 17]byte var x1984 [1 << 17]byte var x1985 [1 << 17]byte var x1986 [1 << 17]byte var x1987 [1 << 17]byte var x1988 [1 << 17]byte var x1989 [1 << 17]byte var x1990 [1 << 17]byte var x1991 [1 << 17]byte var x1992 [1 << 17]byte var x1993 [1 << 17]byte var x1994 [1 << 17]byte var x1995 [1 << 17]byte var x1996 [1 << 17]byte var x1997 [1 << 17]byte var x1998 [1 << 17]byte var x1999 [1 << 17]byte var x2000 [1 << 17]byte var x2001 [1 << 17]byte var x2002 [1 << 17]byte var x2003 [1 << 17]byte var x2004 [1 << 17]byte var x2005 [1 << 17]byte var x2006 [1 << 17]byte var x2007 [1 << 17]byte var x2008 [1 << 17]byte var x2009 [1 << 17]byte var x2010 [1 << 17]byte var x2011 [1 << 17]byte var x2012 [1 << 17]byte var x2013 [1 << 17]byte var x2014 [1 << 17]byte var x2015 [1 << 17]byte var x2016 [1 << 17]byte var x2017 [1 << 17]byte var x2018 [1 << 17]byte var x2019 [1 << 17]byte var x2020 [1 << 17]byte var x2021 [1 << 17]byte var x2022 [1 << 17]byte var x2023 [1 << 17]byte var x2024 [1 << 17]byte var x2025 [1 << 17]byte var x2026 [1 << 17]byte var x2027 [1 << 17]byte var x2028 [1 << 17]byte var x2029 [1 << 17]byte var x2030 [1 << 17]byte var x2031 [1 << 17]byte var x2032 [1 << 17]byte var x2033 [1 << 17]byte var x2034 [1 << 17]byte var x2035 [1 << 17]byte var x2036 [1 << 17]byte var x2037 [1 << 17]byte var x2038 [1 << 17]byte var x2039 [1 << 17]byte var x2040 [1 << 17]byte var x2041 [1 << 17]byte var x2042 [1 << 17]byte var x2043 [1 << 17]byte var x2044 [1 << 17]byte var x2045 [1 << 17]byte var x2046 [1 << 17]byte var x2047 [1 << 17]byte var x2048 [1 << 17]byte var x2049 [1 << 17]byte var x2050 [1 << 17]byte var x2051 [1 << 17]byte var x2052 [1 << 17]byte var x2053 [1 << 17]byte var x2054 [1 << 17]byte var x2055 [1 << 17]byte var x2056 [1 << 17]byte var x2057 [1 << 17]byte var x2058 [1 << 17]byte var x2059 [1 << 17]byte var x2060 [1 << 17]byte var x2061 [1 << 17]byte var x2062 [1 << 17]byte var x2063 [1 << 17]byte var x2064 [1 << 17]byte var x2065 [1 << 17]byte var x2066 [1 << 17]byte var x2067 [1 << 17]byte var x2068 [1 << 17]byte var x2069 [1 << 17]byte var x2070 [1 << 17]byte var x2071 [1 << 17]byte var x2072 [1 << 17]byte var x2073 [1 << 17]byte var x2074 [1 << 17]byte var x2075 [1 << 17]byte var x2076 [1 << 17]byte var x2077 [1 << 17]byte var x2078 [1 << 17]byte var x2079 [1 << 17]byte var x2080 [1 << 17]byte var x2081 [1 << 17]byte var x2082 [1 << 17]byte var x2083 [1 << 17]byte var x2084 [1 << 17]byte var x2085 [1 << 17]byte var x2086 [1 << 17]byte var x2087 [1 << 17]byte var x2088 [1 << 17]byte var x2089 [1 << 17]byte var x2090 [1 << 17]byte var x2091 [1 << 17]byte var x2092 [1 << 17]byte var x2093 [1 << 17]byte var x2094 [1 << 17]byte var x2095 [1 << 17]byte var x2096 [1 << 17]byte var x2097 [1 << 17]byte var x2098 [1 << 17]byte var x2099 [1 << 17]byte var x2100 [1 << 17]byte var x2101 [1 << 17]byte var x2102 [1 << 17]byte var x2103 [1 << 17]byte var x2104 [1 << 17]byte var x2105 [1 << 17]byte var x2106 [1 << 17]byte var x2107 [1 << 17]byte var x2108 [1 << 17]byte var x2109 [1 << 17]byte var x2110 [1 << 17]byte var x2111 [1 << 17]byte var x2112 [1 << 17]byte var x2113 [1 << 17]byte var x2114 [1 << 17]byte var x2115 [1 << 17]byte var x2116 [1 << 17]byte var x2117 [1 << 17]byte var x2118 [1 << 17]byte var x2119 [1 << 17]byte var x2120 [1 << 17]byte var x2121 [1 << 17]byte var x2122 [1 << 17]byte var x2123 [1 << 17]byte var x2124 [1 << 17]byte var x2125 [1 << 17]byte var x2126 [1 << 17]byte var x2127 [1 << 17]byte var x2128 [1 << 17]byte var x2129 [1 << 17]byte var x2130 [1 << 17]byte var x2131 [1 << 17]byte var x2132 [1 << 17]byte var x2133 [1 << 17]byte var x2134 [1 << 17]byte var x2135 [1 << 17]byte var x2136 [1 << 17]byte var x2137 [1 << 17]byte var x2138 [1 << 17]byte var x2139 [1 << 17]byte var x2140 [1 << 17]byte var x2141 [1 << 17]byte var x2142 [1 << 17]byte var x2143 [1 << 17]byte var x2144 [1 << 17]byte var x2145 [1 << 17]byte var x2146 [1 << 17]byte var x2147 [1 << 17]byte var x2148 [1 << 17]byte var x2149 [1 << 17]byte var x2150 [1 << 17]byte var x2151 [1 << 17]byte var x2152 [1 << 17]byte var x2153 [1 << 17]byte var x2154 [1 << 17]byte var x2155 [1 << 17]byte var x2156 [1 << 17]byte var x2157 [1 << 17]byte var x2158 [1 << 17]byte var x2159 [1 << 17]byte var x2160 [1 << 17]byte var x2161 [1 << 17]byte var x2162 [1 << 17]byte var x2163 [1 << 17]byte var x2164 [1 << 17]byte var x2165 [1 << 17]byte var x2166 [1 << 17]byte var x2167 [1 << 17]byte var x2168 [1 << 17]byte var x2169 [1 << 17]byte var x2170 [1 << 17]byte var x2171 [1 << 17]byte var x2172 [1 << 17]byte var x2173 [1 << 17]byte var x2174 [1 << 17]byte var x2175 [1 << 17]byte var x2176 [1 << 17]byte var x2177 [1 << 17]byte var x2178 [1 << 17]byte var x2179 [1 << 17]byte var x2180 [1 << 17]byte var x2181 [1 << 17]byte var x2182 [1 << 17]byte var x2183 [1 << 17]byte var x2184 [1 << 17]byte var x2185 [1 << 17]byte var x2186 [1 << 17]byte var x2187 [1 << 17]byte var x2188 [1 << 17]byte var x2189 [1 << 17]byte var x2190 [1 << 17]byte var x2191 [1 << 17]byte var x2192 [1 << 17]byte var x2193 [1 << 17]byte var x2194 [1 << 17]byte var x2195 [1 << 17]byte var x2196 [1 << 17]byte var x2197 [1 << 17]byte var x2198 [1 << 17]byte var x2199 [1 << 17]byte var x2200 [1 << 17]byte var x2201 [1 << 17]byte var x2202 [1 << 17]byte var x2203 [1 << 17]byte var x2204 [1 << 17]byte var x2205 [1 << 17]byte var x2206 [1 << 17]byte var x2207 [1 << 17]byte var x2208 [1 << 17]byte var x2209 [1 << 17]byte var x2210 [1 << 17]byte var x2211 [1 << 17]byte var x2212 [1 << 17]byte var x2213 [1 << 17]byte var x2214 [1 << 17]byte var x2215 [1 << 17]byte var x2216 [1 << 17]byte var x2217 [1 << 17]byte var x2218 [1 << 17]byte var x2219 [1 << 17]byte var x2220 [1 << 17]byte var x2221 [1 << 17]byte var x2222 [1 << 17]byte var x2223 [1 << 17]byte var x2224 [1 << 17]byte var x2225 [1 << 17]byte var x2226 [1 << 17]byte var x2227 [1 << 17]byte var x2228 [1 << 17]byte var x2229 [1 << 17]byte var x2230 [1 << 17]byte var x2231 [1 << 17]byte var x2232 [1 << 17]byte var x2233 [1 << 17]byte var x2234 [1 << 17]byte var x2235 [1 << 17]byte var x2236 [1 << 17]byte var x2237 [1 << 17]byte var x2238 [1 << 17]byte var x2239 [1 << 17]byte var x2240 [1 << 17]byte var x2241 [1 << 17]byte var x2242 [1 << 17]byte var x2243 [1 << 17]byte var x2244 [1 << 17]byte var x2245 [1 << 17]byte var x2246 [1 << 17]byte var x2247 [1 << 17]byte var x2248 [1 << 17]byte var x2249 [1 << 17]byte var x2250 [1 << 17]byte var x2251 [1 << 17]byte var x2252 [1 << 17]byte var x2253 [1 << 17]byte var x2254 [1 << 17]byte var x2255 [1 << 17]byte var x2256 [1 << 17]byte var x2257 [1 << 17]byte var x2258 [1 << 17]byte var x2259 [1 << 17]byte var x2260 [1 << 17]byte var x2261 [1 << 17]byte var x2262 [1 << 17]byte var x2263 [1 << 17]byte var x2264 [1 << 17]byte var x2265 [1 << 17]byte var x2266 [1 << 17]byte var x2267 [1 << 17]byte var x2268 [1 << 17]byte var x2269 [1 << 17]byte var x2270 [1 << 17]byte var x2271 [1 << 17]byte var x2272 [1 << 17]byte var x2273 [1 << 17]byte var x2274 [1 << 17]byte var x2275 [1 << 17]byte var x2276 [1 << 17]byte var x2277 [1 << 17]byte var x2278 [1 << 17]byte var x2279 [1 << 17]byte var x2280 [1 << 17]byte var x2281 [1 << 17]byte var x2282 [1 << 17]byte var x2283 [1 << 17]byte var x2284 [1 << 17]byte var x2285 [1 << 17]byte var x2286 [1 << 17]byte var x2287 [1 << 17]byte var x2288 [1 << 17]byte var x2289 [1 << 17]byte var x2290 [1 << 17]byte var x2291 [1 << 17]byte var x2292 [1 << 17]byte var x2293 [1 << 17]byte var x2294 [1 << 17]byte var x2295 [1 << 17]byte var x2296 [1 << 17]byte var x2297 [1 << 17]byte var x2298 [1 << 17]byte var x2299 [1 << 17]byte var x2300 [1 << 17]byte var x2301 [1 << 17]byte var x2302 [1 << 17]byte var x2303 [1 << 17]byte var x2304 [1 << 17]byte var x2305 [1 << 17]byte var x2306 [1 << 17]byte var x2307 [1 << 17]byte var x2308 [1 << 17]byte var x2309 [1 << 17]byte var x2310 [1 << 17]byte var x2311 [1 << 17]byte var x2312 [1 << 17]byte var x2313 [1 << 17]byte var x2314 [1 << 17]byte var x2315 [1 << 17]byte var x2316 [1 << 17]byte var x2317 [1 << 17]byte var x2318 [1 << 17]byte var x2319 [1 << 17]byte var x2320 [1 << 17]byte var x2321 [1 << 17]byte var x2322 [1 << 17]byte var x2323 [1 << 17]byte var x2324 [1 << 17]byte var x2325 [1 << 17]byte var x2326 [1 << 17]byte var x2327 [1 << 17]byte var x2328 [1 << 17]byte var x2329 [1 << 17]byte var x2330 [1 << 17]byte var x2331 [1 << 17]byte var x2332 [1 << 17]byte var x2333 [1 << 17]byte var x2334 [1 << 17]byte var x2335 [1 << 17]byte var x2336 [1 << 17]byte var x2337 [1 << 17]byte var x2338 [1 << 17]byte var x2339 [1 << 17]byte var x2340 [1 << 17]byte var x2341 [1 << 17]byte var x2342 [1 << 17]byte var x2343 [1 << 17]byte var x2344 [1 << 17]byte var x2345 [1 << 17]byte var x2346 [1 << 17]byte var x2347 [1 << 17]byte var x2348 [1 << 17]byte var x2349 [1 << 17]byte var x2350 [1 << 17]byte var x2351 [1 << 17]byte var x2352 [1 << 17]byte var x2353 [1 << 17]byte var x2354 [1 << 17]byte var x2355 [1 << 17]byte var x2356 [1 << 17]byte var x2357 [1 << 17]byte var x2358 [1 << 17]byte var x2359 [1 << 17]byte var x2360 [1 << 17]byte var x2361 [1 << 17]byte var x2362 [1 << 17]byte var x2363 [1 << 17]byte var x2364 [1 << 17]byte var x2365 [1 << 17]byte var x2366 [1 << 17]byte var x2367 [1 << 17]byte var x2368 [1 << 17]byte var x2369 [1 << 17]byte var x2370 [1 << 17]byte var x2371 [1 << 17]byte var x2372 [1 << 17]byte var x2373 [1 << 17]byte var x2374 [1 << 17]byte var x2375 [1 << 17]byte var x2376 [1 << 17]byte var x2377 [1 << 17]byte var x2378 [1 << 17]byte var x2379 [1 << 17]byte var x2380 [1 << 17]byte var x2381 [1 << 17]byte var x2382 [1 << 17]byte var x2383 [1 << 17]byte var x2384 [1 << 17]byte var x2385 [1 << 17]byte var x2386 [1 << 17]byte var x2387 [1 << 17]byte var x2388 [1 << 17]byte var x2389 [1 << 17]byte var x2390 [1 << 17]byte var x2391 [1 << 17]byte var x2392 [1 << 17]byte var x2393 [1 << 17]byte var x2394 [1 << 17]byte var x2395 [1 << 17]byte var x2396 [1 << 17]byte var x2397 [1 << 17]byte var x2398 [1 << 17]byte var x2399 [1 << 17]byte var x2400 [1 << 17]byte var x2401 [1 << 17]byte var x2402 [1 << 17]byte var x2403 [1 << 17]byte var x2404 [1 << 17]byte var x2405 [1 << 17]byte var x2406 [1 << 17]byte var x2407 [1 << 17]byte var x2408 [1 << 17]byte var x2409 [1 << 17]byte var x2410 [1 << 17]byte var x2411 [1 << 17]byte var x2412 [1 << 17]byte var x2413 [1 << 17]byte var x2414 [1 << 17]byte var x2415 [1 << 17]byte var x2416 [1 << 17]byte var x2417 [1 << 17]byte var x2418 [1 << 17]byte var x2419 [1 << 17]byte var x2420 [1 << 17]byte var x2421 [1 << 17]byte var x2422 [1 << 17]byte var x2423 [1 << 17]byte var x2424 [1 << 17]byte var x2425 [1 << 17]byte var x2426 [1 << 17]byte var x2427 [1 << 17]byte var x2428 [1 << 17]byte var x2429 [1 << 17]byte var x2430 [1 << 17]byte var x2431 [1 << 17]byte var x2432 [1 << 17]byte var x2433 [1 << 17]byte var x2434 [1 << 17]byte var x2435 [1 << 17]byte var x2436 [1 << 17]byte var x2437 [1 << 17]byte var x2438 [1 << 17]byte var x2439 [1 << 17]byte var x2440 [1 << 17]byte var x2441 [1 << 17]byte var x2442 [1 << 17]byte var x2443 [1 << 17]byte var x2444 [1 << 17]byte var x2445 [1 << 17]byte var x2446 [1 << 17]byte var x2447 [1 << 17]byte var x2448 [1 << 17]byte var x2449 [1 << 17]byte var x2450 [1 << 17]byte var x2451 [1 << 17]byte var x2452 [1 << 17]byte var x2453 [1 << 17]byte var x2454 [1 << 17]byte var x2455 [1 << 17]byte var x2456 [1 << 17]byte var x2457 [1 << 17]byte var x2458 [1 << 17]byte var x2459 [1 << 17]byte var x2460 [1 << 17]byte var x2461 [1 << 17]byte var x2462 [1 << 17]byte var x2463 [1 << 17]byte var x2464 [1 << 17]byte var x2465 [1 << 17]byte var x2466 [1 << 17]byte var x2467 [1 << 17]byte var x2468 [1 << 17]byte var x2469 [1 << 17]byte var x2470 [1 << 17]byte var x2471 [1 << 17]byte var x2472 [1 << 17]byte var x2473 [1 << 17]byte var x2474 [1 << 17]byte var x2475 [1 << 17]byte var x2476 [1 << 17]byte var x2477 [1 << 17]byte var x2478 [1 << 17]byte var x2479 [1 << 17]byte var x2480 [1 << 17]byte var x2481 [1 << 17]byte var x2482 [1 << 17]byte var x2483 [1 << 17]byte var x2484 [1 << 17]byte var x2485 [1 << 17]byte var x2486 [1 << 17]byte var x2487 [1 << 17]byte var x2488 [1 << 17]byte var x2489 [1 << 17]byte var x2490 [1 << 17]byte var x2491 [1 << 17]byte var x2492 [1 << 17]byte var x2493 [1 << 17]byte var x2494 [1 << 17]byte var x2495 [1 << 17]byte var x2496 [1 << 17]byte var x2497 [1 << 17]byte var x2498 [1 << 17]byte var x2499 [1 << 17]byte var x2500 [1 << 17]byte var x2501 [1 << 17]byte var x2502 [1 << 17]byte var x2503 [1 << 17]byte var x2504 [1 << 17]byte var x2505 [1 << 17]byte var x2506 [1 << 17]byte var x2507 [1 << 17]byte var x2508 [1 << 17]byte var x2509 [1 << 17]byte var x2510 [1 << 17]byte var x2511 [1 << 17]byte var x2512 [1 << 17]byte var x2513 [1 << 17]byte var x2514 [1 << 17]byte var x2515 [1 << 17]byte var x2516 [1 << 17]byte var x2517 [1 << 17]byte var x2518 [1 << 17]byte var x2519 [1 << 17]byte var x2520 [1 << 17]byte var x2521 [1 << 17]byte var x2522 [1 << 17]byte var x2523 [1 << 17]byte var x2524 [1 << 17]byte var x2525 [1 << 17]byte var x2526 [1 << 17]byte var x2527 [1 << 17]byte var x2528 [1 << 17]byte var x2529 [1 << 17]byte var x2530 [1 << 17]byte var x2531 [1 << 17]byte var x2532 [1 << 17]byte var x2533 [1 << 17]byte var x2534 [1 << 17]byte var x2535 [1 << 17]byte var x2536 [1 << 17]byte var x2537 [1 << 17]byte var x2538 [1 << 17]byte var x2539 [1 << 17]byte var x2540 [1 << 17]byte var x2541 [1 << 17]byte var x2542 [1 << 17]byte var x2543 [1 << 17]byte var x2544 [1 << 17]byte var x2545 [1 << 17]byte var x2546 [1 << 17]byte var x2547 [1 << 17]byte var x2548 [1 << 17]byte var x2549 [1 << 17]byte var x2550 [1 << 17]byte var x2551 [1 << 17]byte var x2552 [1 << 17]byte var x2553 [1 << 17]byte var x2554 [1 << 17]byte var x2555 [1 << 17]byte var x2556 [1 << 17]byte var x2557 [1 << 17]byte var x2558 [1 << 17]byte var x2559 [1 << 17]byte var x2560 [1 << 17]byte var x2561 [1 << 17]byte var x2562 [1 << 17]byte var x2563 [1 << 17]byte var x2564 [1 << 17]byte var x2565 [1 << 17]byte var x2566 [1 << 17]byte var x2567 [1 << 17]byte var x2568 [1 << 17]byte var x2569 [1 << 17]byte var x2570 [1 << 17]byte var x2571 [1 << 17]byte var x2572 [1 << 17]byte var x2573 [1 << 17]byte var x2574 [1 << 17]byte var x2575 [1 << 17]byte var x2576 [1 << 17]byte var x2577 [1 << 17]byte var x2578 [1 << 17]byte var x2579 [1 << 17]byte var x2580 [1 << 17]byte var x2581 [1 << 17]byte var x2582 [1 << 17]byte var x2583 [1 << 17]byte var x2584 [1 << 17]byte var x2585 [1 << 17]byte var x2586 [1 << 17]byte var x2587 [1 << 17]byte var x2588 [1 << 17]byte var x2589 [1 << 17]byte var x2590 [1 << 17]byte var x2591 [1 << 17]byte var x2592 [1 << 17]byte var x2593 [1 << 17]byte var x2594 [1 << 17]byte var x2595 [1 << 17]byte var x2596 [1 << 17]byte var x2597 [1 << 17]byte var x2598 [1 << 17]byte var x2599 [1 << 17]byte var x2600 [1 << 17]byte var x2601 [1 << 17]byte var x2602 [1 << 17]byte var x2603 [1 << 17]byte var x2604 [1 << 17]byte var x2605 [1 << 17]byte var x2606 [1 << 17]byte var x2607 [1 << 17]byte var x2608 [1 << 17]byte var x2609 [1 << 17]byte var x2610 [1 << 17]byte var x2611 [1 << 17]byte var x2612 [1 << 17]byte var x2613 [1 << 17]byte var x2614 [1 << 17]byte var x2615 [1 << 17]byte var x2616 [1 << 17]byte var x2617 [1 << 17]byte var x2618 [1 << 17]byte var x2619 [1 << 17]byte var x2620 [1 << 17]byte var x2621 [1 << 17]byte var x2622 [1 << 17]byte var x2623 [1 << 17]byte var x2624 [1 << 17]byte var x2625 [1 << 17]byte var x2626 [1 << 17]byte var x2627 [1 << 17]byte var x2628 [1 << 17]byte var x2629 [1 << 17]byte var x2630 [1 << 17]byte var x2631 [1 << 17]byte var x2632 [1 << 17]byte var x2633 [1 << 17]byte var x2634 [1 << 17]byte var x2635 [1 << 17]byte var x2636 [1 << 17]byte var x2637 [1 << 17]byte var x2638 [1 << 17]byte var x2639 [1 << 17]byte var x2640 [1 << 17]byte var x2641 [1 << 17]byte var x2642 [1 << 17]byte var x2643 [1 << 17]byte var x2644 [1 << 17]byte var x2645 [1 << 17]byte var x2646 [1 << 17]byte var x2647 [1 << 17]byte var x2648 [1 << 17]byte var x2649 [1 << 17]byte var x2650 [1 << 17]byte var x2651 [1 << 17]byte var x2652 [1 << 17]byte var x2653 [1 << 17]byte var x2654 [1 << 17]byte var x2655 [1 << 17]byte var x2656 [1 << 17]byte var x2657 [1 << 17]byte var x2658 [1 << 17]byte var x2659 [1 << 17]byte var x2660 [1 << 17]byte var x2661 [1 << 17]byte var x2662 [1 << 17]byte var x2663 [1 << 17]byte var x2664 [1 << 17]byte var x2665 [1 << 17]byte var x2666 [1 << 17]byte var x2667 [1 << 17]byte var x2668 [1 << 17]byte var x2669 [1 << 17]byte var x2670 [1 << 17]byte var x2671 [1 << 17]byte var x2672 [1 << 17]byte var x2673 [1 << 17]byte var x2674 [1 << 17]byte var x2675 [1 << 17]byte var x2676 [1 << 17]byte var x2677 [1 << 17]byte var x2678 [1 << 17]byte var x2679 [1 << 17]byte var x2680 [1 << 17]byte var x2681 [1 << 17]byte var x2682 [1 << 17]byte var x2683 [1 << 17]byte var x2684 [1 << 17]byte var x2685 [1 << 17]byte var x2686 [1 << 17]byte var x2687 [1 << 17]byte var x2688 [1 << 17]byte var x2689 [1 << 17]byte var x2690 [1 << 17]byte var x2691 [1 << 17]byte var x2692 [1 << 17]byte var x2693 [1 << 17]byte var x2694 [1 << 17]byte var x2695 [1 << 17]byte var x2696 [1 << 17]byte var x2697 [1 << 17]byte var x2698 [1 << 17]byte var x2699 [1 << 17]byte var x2700 [1 << 17]byte var x2701 [1 << 17]byte var x2702 [1 << 17]byte var x2703 [1 << 17]byte var x2704 [1 << 17]byte var x2705 [1 << 17]byte var x2706 [1 << 17]byte var x2707 [1 << 17]byte var x2708 [1 << 17]byte var x2709 [1 << 17]byte var x2710 [1 << 17]byte var x2711 [1 << 17]byte var x2712 [1 << 17]byte var x2713 [1 << 17]byte var x2714 [1 << 17]byte var x2715 [1 << 17]byte var x2716 [1 << 17]byte var x2717 [1 << 17]byte var x2718 [1 << 17]byte var x2719 [1 << 17]byte var x2720 [1 << 17]byte var x2721 [1 << 17]byte var x2722 [1 << 17]byte var x2723 [1 << 17]byte var x2724 [1 << 17]byte var x2725 [1 << 17]byte var x2726 [1 << 17]byte var x2727 [1 << 17]byte var x2728 [1 << 17]byte var x2729 [1 << 17]byte var x2730 [1 << 17]byte var x2731 [1 << 17]byte var x2732 [1 << 17]byte var x2733 [1 << 17]byte var x2734 [1 << 17]byte var x2735 [1 << 17]byte var x2736 [1 << 17]byte var x2737 [1 << 17]byte var x2738 [1 << 17]byte var x2739 [1 << 17]byte var x2740 [1 << 17]byte var x2741 [1 << 17]byte var x2742 [1 << 17]byte var x2743 [1 << 17]byte var x2744 [1 << 17]byte var x2745 [1 << 17]byte var x2746 [1 << 17]byte var x2747 [1 << 17]byte var x2748 [1 << 17]byte var x2749 [1 << 17]byte var x2750 [1 << 17]byte var x2751 [1 << 17]byte var x2752 [1 << 17]byte var x2753 [1 << 17]byte var x2754 [1 << 17]byte var x2755 [1 << 17]byte var x2756 [1 << 17]byte var x2757 [1 << 17]byte var x2758 [1 << 17]byte var x2759 [1 << 17]byte var x2760 [1 << 17]byte var x2761 [1 << 17]byte var x2762 [1 << 17]byte var x2763 [1 << 17]byte var x2764 [1 << 17]byte var x2765 [1 << 17]byte var x2766 [1 << 17]byte var x2767 [1 << 17]byte var x2768 [1 << 17]byte var x2769 [1 << 17]byte var x2770 [1 << 17]byte var x2771 [1 << 17]byte var x2772 [1 << 17]byte var x2773 [1 << 17]byte var x2774 [1 << 17]byte var x2775 [1 << 17]byte var x2776 [1 << 17]byte var x2777 [1 << 17]byte var x2778 [1 << 17]byte var x2779 [1 << 17]byte var x2780 [1 << 17]byte var x2781 [1 << 17]byte var x2782 [1 << 17]byte var x2783 [1 << 17]byte var x2784 [1 << 17]byte var x2785 [1 << 17]byte var x2786 [1 << 17]byte var x2787 [1 << 17]byte var x2788 [1 << 17]byte var x2789 [1 << 17]byte var x2790 [1 << 17]byte var x2791 [1 << 17]byte var x2792 [1 << 17]byte var x2793 [1 << 17]byte var x2794 [1 << 17]byte var x2795 [1 << 17]byte var x2796 [1 << 17]byte var x2797 [1 << 17]byte var x2798 [1 << 17]byte var x2799 [1 << 17]byte var x2800 [1 << 17]byte var x2801 [1 << 17]byte var x2802 [1 << 17]byte var x2803 [1 << 17]byte var x2804 [1 << 17]byte var x2805 [1 << 17]byte var x2806 [1 << 17]byte var x2807 [1 << 17]byte var x2808 [1 << 17]byte var x2809 [1 << 17]byte var x2810 [1 << 17]byte var x2811 [1 << 17]byte var x2812 [1 << 17]byte var x2813 [1 << 17]byte var x2814 [1 << 17]byte var x2815 [1 << 17]byte var x2816 [1 << 17]byte var x2817 [1 << 17]byte var x2818 [1 << 17]byte var x2819 [1 << 17]byte var x2820 [1 << 17]byte var x2821 [1 << 17]byte var x2822 [1 << 17]byte var x2823 [1 << 17]byte var x2824 [1 << 17]byte var x2825 [1 << 17]byte var x2826 [1 << 17]byte var x2827 [1 << 17]byte var x2828 [1 << 17]byte var x2829 [1 << 17]byte var x2830 [1 << 17]byte var x2831 [1 << 17]byte var x2832 [1 << 17]byte var x2833 [1 << 17]byte var x2834 [1 << 17]byte var x2835 [1 << 17]byte var x2836 [1 << 17]byte var x2837 [1 << 17]byte var x2838 [1 << 17]byte var x2839 [1 << 17]byte var x2840 [1 << 17]byte var x2841 [1 << 17]byte var x2842 [1 << 17]byte var x2843 [1 << 17]byte var x2844 [1 << 17]byte var x2845 [1 << 17]byte var x2846 [1 << 17]byte var x2847 [1 << 17]byte var x2848 [1 << 17]byte var x2849 [1 << 17]byte var x2850 [1 << 17]byte var x2851 [1 << 17]byte var x2852 [1 << 17]byte var x2853 [1 << 17]byte var x2854 [1 << 17]byte var x2855 [1 << 17]byte var x2856 [1 << 17]byte var x2857 [1 << 17]byte var x2858 [1 << 17]byte var x2859 [1 << 17]byte var x2860 [1 << 17]byte var x2861 [1 << 17]byte var x2862 [1 << 17]byte var x2863 [1 << 17]byte var x2864 [1 << 17]byte var x2865 [1 << 17]byte var x2866 [1 << 17]byte var x2867 [1 << 17]byte var x2868 [1 << 17]byte var x2869 [1 << 17]byte var x2870 [1 << 17]byte var x2871 [1 << 17]byte var x2872 [1 << 17]byte var x2873 [1 << 17]byte var x2874 [1 << 17]byte var x2875 [1 << 17]byte var x2876 [1 << 17]byte var x2877 [1 << 17]byte var x2878 [1 << 17]byte var x2879 [1 << 17]byte var x2880 [1 << 17]byte var x2881 [1 << 17]byte var x2882 [1 << 17]byte var x2883 [1 << 17]byte var x2884 [1 << 17]byte var x2885 [1 << 17]byte var x2886 [1 << 17]byte var x2887 [1 << 17]byte var x2888 [1 << 17]byte var x2889 [1 << 17]byte var x2890 [1 << 17]byte var x2891 [1 << 17]byte var x2892 [1 << 17]byte var x2893 [1 << 17]byte var x2894 [1 << 17]byte var x2895 [1 << 17]byte var x2896 [1 << 17]byte var x2897 [1 << 17]byte var x2898 [1 << 17]byte var x2899 [1 << 17]byte var x2900 [1 << 17]byte var x2901 [1 << 17]byte var x2902 [1 << 17]byte var x2903 [1 << 17]byte var x2904 [1 << 17]byte var x2905 [1 << 17]byte var x2906 [1 << 17]byte var x2907 [1 << 17]byte var x2908 [1 << 17]byte var x2909 [1 << 17]byte var x2910 [1 << 17]byte var x2911 [1 << 17]byte var x2912 [1 << 17]byte var x2913 [1 << 17]byte var x2914 [1 << 17]byte var x2915 [1 << 17]byte var x2916 [1 << 17]byte var x2917 [1 << 17]byte var x2918 [1 << 17]byte var x2919 [1 << 17]byte var x2920 [1 << 17]byte var x2921 [1 << 17]byte var x2922 [1 << 17]byte var x2923 [1 << 17]byte var x2924 [1 << 17]byte var x2925 [1 << 17]byte var x2926 [1 << 17]byte var x2927 [1 << 17]byte var x2928 [1 << 17]byte var x2929 [1 << 17]byte var x2930 [1 << 17]byte var x2931 [1 << 17]byte var x2932 [1 << 17]byte var x2933 [1 << 17]byte var x2934 [1 << 17]byte var x2935 [1 << 17]byte var x2936 [1 << 17]byte var x2937 [1 << 17]byte var x2938 [1 << 17]byte var x2939 [1 << 17]byte var x2940 [1 << 17]byte var x2941 [1 << 17]byte var x2942 [1 << 17]byte var x2943 [1 << 17]byte var x2944 [1 << 17]byte var x2945 [1 << 17]byte var x2946 [1 << 17]byte var x2947 [1 << 17]byte var x2948 [1 << 17]byte var x2949 [1 << 17]byte var x2950 [1 << 17]byte var x2951 [1 << 17]byte var x2952 [1 << 17]byte var x2953 [1 << 17]byte var x2954 [1 << 17]byte var x2955 [1 << 17]byte var x2956 [1 << 17]byte var x2957 [1 << 17]byte var x2958 [1 << 17]byte var x2959 [1 << 17]byte var x2960 [1 << 17]byte var x2961 [1 << 17]byte var x2962 [1 << 17]byte var x2963 [1 << 17]byte var x2964 [1 << 17]byte var x2965 [1 << 17]byte var x2966 [1 << 17]byte var x2967 [1 << 17]byte var x2968 [1 << 17]byte var x2969 [1 << 17]byte var x2970 [1 << 17]byte var x2971 [1 << 17]byte var x2972 [1 << 17]byte var x2973 [1 << 17]byte var x2974 [1 << 17]byte var x2975 [1 << 17]byte var x2976 [1 << 17]byte var x2977 [1 << 17]byte var x2978 [1 << 17]byte var x2979 [1 << 17]byte var x2980 [1 << 17]byte var x2981 [1 << 17]byte var x2982 [1 << 17]byte var x2983 [1 << 17]byte var x2984 [1 << 17]byte var x2985 [1 << 17]byte var x2986 [1 << 17]byte var x2987 [1 << 17]byte var x2988 [1 << 17]byte var x2989 [1 << 17]byte var x2990 [1 << 17]byte var x2991 [1 << 17]byte var x2992 [1 << 17]byte var x2993 [1 << 17]byte var x2994 [1 << 17]byte var x2995 [1 << 17]byte var x2996 [1 << 17]byte var x2997 [1 << 17]byte var x2998 [1 << 17]byte var x2999 [1 << 17]byte var x3000 [1 << 17]byte var x3001 [1 << 17]byte var x3002 [1 << 17]byte var x3003 [1 << 17]byte var x3004 [1 << 17]byte var x3005 [1 << 17]byte var x3006 [1 << 17]byte var x3007 [1 << 17]byte var x3008 [1 << 17]byte var x3009 [1 << 17]byte var x3010 [1 << 17]byte var x3011 [1 << 17]byte var x3012 [1 << 17]byte var x3013 [1 << 17]byte var x3014 [1 << 17]byte var x3015 [1 << 17]byte var x3016 [1 << 17]byte var x3017 [1 << 17]byte var x3018 [1 << 17]byte var x3019 [1 << 17]byte var x3020 [1 << 17]byte var x3021 [1 << 17]byte var x3022 [1 << 17]byte var x3023 [1 << 17]byte var x3024 [1 << 17]byte var x3025 [1 << 17]byte var x3026 [1 << 17]byte var x3027 [1 << 17]byte var x3028 [1 << 17]byte var x3029 [1 << 17]byte var x3030 [1 << 17]byte var x3031 [1 << 17]byte var x3032 [1 << 17]byte var x3033 [1 << 17]byte var x3034 [1 << 17]byte var x3035 [1 << 17]byte var x3036 [1 << 17]byte var x3037 [1 << 17]byte var x3038 [1 << 17]byte var x3039 [1 << 17]byte var x3040 [1 << 17]byte var x3041 [1 << 17]byte var x3042 [1 << 17]byte var x3043 [1 << 17]byte var x3044 [1 << 17]byte var x3045 [1 << 17]byte var x3046 [1 << 17]byte var x3047 [1 << 17]byte var x3048 [1 << 17]byte var x3049 [1 << 17]byte var x3050 [1 << 17]byte var x3051 [1 << 17]byte var x3052 [1 << 17]byte var x3053 [1 << 17]byte var x3054 [1 << 17]byte var x3055 [1 << 17]byte var x3056 [1 << 17]byte var x3057 [1 << 17]byte var x3058 [1 << 17]byte var x3059 [1 << 17]byte var x3060 [1 << 17]byte var x3061 [1 << 17]byte var x3062 [1 << 17]byte var x3063 [1 << 17]byte var x3064 [1 << 17]byte var x3065 [1 << 17]byte var x3066 [1 << 17]byte var x3067 [1 << 17]byte var x3068 [1 << 17]byte var x3069 [1 << 17]byte var x3070 [1 << 17]byte var x3071 [1 << 17]byte var x3072 [1 << 17]byte var x3073 [1 << 17]byte var x3074 [1 << 17]byte var x3075 [1 << 17]byte var x3076 [1 << 17]byte var x3077 [1 << 17]byte var x3078 [1 << 17]byte var x3079 [1 << 17]byte var x3080 [1 << 17]byte var x3081 [1 << 17]byte var x3082 [1 << 17]byte var x3083 [1 << 17]byte var x3084 [1 << 17]byte var x3085 [1 << 17]byte var x3086 [1 << 17]byte var x3087 [1 << 17]byte var x3088 [1 << 17]byte var x3089 [1 << 17]byte var x3090 [1 << 17]byte var x3091 [1 << 17]byte var x3092 [1 << 17]byte var x3093 [1 << 17]byte var x3094 [1 << 17]byte var x3095 [1 << 17]byte var x3096 [1 << 17]byte var x3097 [1 << 17]byte var x3098 [1 << 17]byte var x3099 [1 << 17]byte var x3100 [1 << 17]byte var x3101 [1 << 17]byte var x3102 [1 << 17]byte var x3103 [1 << 17]byte var x3104 [1 << 17]byte var x3105 [1 << 17]byte var x3106 [1 << 17]byte var x3107 [1 << 17]byte var x3108 [1 << 17]byte var x3109 [1 << 17]byte var x3110 [1 << 17]byte var x3111 [1 << 17]byte var x3112 [1 << 17]byte var x3113 [1 << 17]byte var x3114 [1 << 17]byte var x3115 [1 << 17]byte var x3116 [1 << 17]byte var x3117 [1 << 17]byte var x3118 [1 << 17]byte var x3119 [1 << 17]byte var x3120 [1 << 17]byte var x3121 [1 << 17]byte var x3122 [1 << 17]byte var x3123 [1 << 17]byte var x3124 [1 << 17]byte var x3125 [1 << 17]byte var x3126 [1 << 17]byte var x3127 [1 << 17]byte var x3128 [1 << 17]byte var x3129 [1 << 17]byte var x3130 [1 << 17]byte var x3131 [1 << 17]byte var x3132 [1 << 17]byte var x3133 [1 << 17]byte var x3134 [1 << 17]byte var x3135 [1 << 17]byte var x3136 [1 << 17]byte var x3137 [1 << 17]byte var x3138 [1 << 17]byte var x3139 [1 << 17]byte var x3140 [1 << 17]byte var x3141 [1 << 17]byte var x3142 [1 << 17]byte var x3143 [1 << 17]byte var x3144 [1 << 17]byte var x3145 [1 << 17]byte var x3146 [1 << 17]byte var x3147 [1 << 17]byte var x3148 [1 << 17]byte var x3149 [1 << 17]byte var x3150 [1 << 17]byte var x3151 [1 << 17]byte var x3152 [1 << 17]byte var x3153 [1 << 17]byte var x3154 [1 << 17]byte var x3155 [1 << 17]byte var x3156 [1 << 17]byte var x3157 [1 << 17]byte var x3158 [1 << 17]byte var x3159 [1 << 17]byte var x3160 [1 << 17]byte var x3161 [1 << 17]byte var x3162 [1 << 17]byte var x3163 [1 << 17]byte var x3164 [1 << 17]byte var x3165 [1 << 17]byte var x3166 [1 << 17]byte var x3167 [1 << 17]byte var x3168 [1 << 17]byte var x3169 [1 << 17]byte var x3170 [1 << 17]byte var x3171 [1 << 17]byte var x3172 [1 << 17]byte var x3173 [1 << 17]byte var x3174 [1 << 17]byte var x3175 [1 << 17]byte var x3176 [1 << 17]byte var x3177 [1 << 17]byte var x3178 [1 << 17]byte var x3179 [1 << 17]byte var x3180 [1 << 17]byte var x3181 [1 << 17]byte var x3182 [1 << 17]byte var x3183 [1 << 17]byte var x3184 [1 << 17]byte var x3185 [1 << 17]byte var x3186 [1 << 17]byte var x3187 [1 << 17]byte var x3188 [1 << 17]byte var x3189 [1 << 17]byte var x3190 [1 << 17]byte var x3191 [1 << 17]byte var x3192 [1 << 17]byte var x3193 [1 << 17]byte var x3194 [1 << 17]byte var x3195 [1 << 17]byte var x3196 [1 << 17]byte var x3197 [1 << 17]byte var x3198 [1 << 17]byte var x3199 [1 << 17]byte var x3200 [1 << 17]byte var x3201 [1 << 17]byte var x3202 [1 << 17]byte var x3203 [1 << 17]byte var x3204 [1 << 17]byte var x3205 [1 << 17]byte var x3206 [1 << 17]byte var x3207 [1 << 17]byte var x3208 [1 << 17]byte var x3209 [1 << 17]byte var x3210 [1 << 17]byte var x3211 [1 << 17]byte var x3212 [1 << 17]byte var x3213 [1 << 17]byte var x3214 [1 << 17]byte var x3215 [1 << 17]byte var x3216 [1 << 17]byte var x3217 [1 << 17]byte var x3218 [1 << 17]byte var x3219 [1 << 17]byte var x3220 [1 << 17]byte var x3221 [1 << 17]byte var x3222 [1 << 17]byte var x3223 [1 << 17]byte var x3224 [1 << 17]byte var x3225 [1 << 17]byte var x3226 [1 << 17]byte var x3227 [1 << 17]byte var x3228 [1 << 17]byte var x3229 [1 << 17]byte var x3230 [1 << 17]byte var x3231 [1 << 17]byte var x3232 [1 << 17]byte var x3233 [1 << 17]byte var x3234 [1 << 17]byte var x3235 [1 << 17]byte var x3236 [1 << 17]byte var x3237 [1 << 17]byte var x3238 [1 << 17]byte var x3239 [1 << 17]byte var x3240 [1 << 17]byte var x3241 [1 << 17]byte var x3242 [1 << 17]byte var x3243 [1 << 17]byte var x3244 [1 << 17]byte var x3245 [1 << 17]byte var x3246 [1 << 17]byte var x3247 [1 << 17]byte var x3248 [1 << 17]byte var x3249 [1 << 17]byte var x3250 [1 << 17]byte var x3251 [1 << 17]byte var x3252 [1 << 17]byte var x3253 [1 << 17]byte var x3254 [1 << 17]byte var x3255 [1 << 17]byte var x3256 [1 << 17]byte var x3257 [1 << 17]byte var x3258 [1 << 17]byte var x3259 [1 << 17]byte var x3260 [1 << 17]byte var x3261 [1 << 17]byte var x3262 [1 << 17]byte var x3263 [1 << 17]byte var x3264 [1 << 17]byte var x3265 [1 << 17]byte var x3266 [1 << 17]byte var x3267 [1 << 17]byte var x3268 [1 << 17]byte var x3269 [1 << 17]byte var x3270 [1 << 17]byte var x3271 [1 << 17]byte var x3272 [1 << 17]byte var x3273 [1 << 17]byte var x3274 [1 << 17]byte var x3275 [1 << 17]byte var x3276 [1 << 17]byte var x3277 [1 << 17]byte var x3278 [1 << 17]byte var x3279 [1 << 17]byte var x3280 [1 << 17]byte var x3281 [1 << 17]byte var x3282 [1 << 17]byte var x3283 [1 << 17]byte var x3284 [1 << 17]byte var x3285 [1 << 17]byte var x3286 [1 << 17]byte var x3287 [1 << 17]byte var x3288 [1 << 17]byte var x3289 [1 << 17]byte var x3290 [1 << 17]byte var x3291 [1 << 17]byte var x3292 [1 << 17]byte var x3293 [1 << 17]byte var x3294 [1 << 17]byte var x3295 [1 << 17]byte var x3296 [1 << 17]byte var x3297 [1 << 17]byte var x3298 [1 << 17]byte var x3299 [1 << 17]byte var x3300 [1 << 17]byte var x3301 [1 << 17]byte var x3302 [1 << 17]byte var x3303 [1 << 17]byte var x3304 [1 << 17]byte var x3305 [1 << 17]byte var x3306 [1 << 17]byte var x3307 [1 << 17]byte var x3308 [1 << 17]byte var x3309 [1 << 17]byte var x3310 [1 << 17]byte var x3311 [1 << 17]byte var x3312 [1 << 17]byte var x3313 [1 << 17]byte var x3314 [1 << 17]byte var x3315 [1 << 17]byte var x3316 [1 << 17]byte var x3317 [1 << 17]byte var x3318 [1 << 17]byte var x3319 [1 << 17]byte var x3320 [1 << 17]byte var x3321 [1 << 17]byte var x3322 [1 << 17]byte var x3323 [1 << 17]byte var x3324 [1 << 17]byte var x3325 [1 << 17]byte var x3326 [1 << 17]byte var x3327 [1 << 17]byte var x3328 [1 << 17]byte var x3329 [1 << 17]byte var x3330 [1 << 17]byte var x3331 [1 << 17]byte var x3332 [1 << 17]byte var x3333 [1 << 17]byte var x3334 [1 << 17]byte var x3335 [1 << 17]byte var x3336 [1 << 17]byte var x3337 [1 << 17]byte var x3338 [1 << 17]byte var x3339 [1 << 17]byte var x3340 [1 << 17]byte var x3341 [1 << 17]byte var x3342 [1 << 17]byte var x3343 [1 << 17]byte var x3344 [1 << 17]byte var x3345 [1 << 17]byte var x3346 [1 << 17]byte var x3347 [1 << 17]byte var x3348 [1 << 17]byte var x3349 [1 << 17]byte var x3350 [1 << 17]byte var x3351 [1 << 17]byte var x3352 [1 << 17]byte var x3353 [1 << 17]byte var x3354 [1 << 17]byte var x3355 [1 << 17]byte var x3356 [1 << 17]byte var x3357 [1 << 17]byte var x3358 [1 << 17]byte var x3359 [1 << 17]byte var x3360 [1 << 17]byte var x3361 [1 << 17]byte var x3362 [1 << 17]byte var x3363 [1 << 17]byte var x3364 [1 << 17]byte var x3365 [1 << 17]byte var x3366 [1 << 17]byte var x3367 [1 << 17]byte var x3368 [1 << 17]byte var x3369 [1 << 17]byte var x3370 [1 << 17]byte var x3371 [1 << 17]byte var x3372 [1 << 17]byte var x3373 [1 << 17]byte var x3374 [1 << 17]byte var x3375 [1 << 17]byte var x3376 [1 << 17]byte var x3377 [1 << 17]byte var x3378 [1 << 17]byte var x3379 [1 << 17]byte var x3380 [1 << 17]byte var x3381 [1 << 17]byte var x3382 [1 << 17]byte var x3383 [1 << 17]byte var x3384 [1 << 17]byte var x3385 [1 << 17]byte var x3386 [1 << 17]byte var x3387 [1 << 17]byte var x3388 [1 << 17]byte var x3389 [1 << 17]byte var x3390 [1 << 17]byte var x3391 [1 << 17]byte var x3392 [1 << 17]byte var x3393 [1 << 17]byte var x3394 [1 << 17]byte var x3395 [1 << 17]byte var x3396 [1 << 17]byte var x3397 [1 << 17]byte var x3398 [1 << 17]byte var x3399 [1 << 17]byte var x3400 [1 << 17]byte var x3401 [1 << 17]byte var x3402 [1 << 17]byte var x3403 [1 << 17]byte var x3404 [1 << 17]byte var x3405 [1 << 17]byte var x3406 [1 << 17]byte var x3407 [1 << 17]byte var x3408 [1 << 17]byte var x3409 [1 << 17]byte var x3410 [1 << 17]byte var x3411 [1 << 17]byte var x3412 [1 << 17]byte var x3413 [1 << 17]byte var x3414 [1 << 17]byte var x3415 [1 << 17]byte var x3416 [1 << 17]byte var x3417 [1 << 17]byte var x3418 [1 << 17]byte var x3419 [1 << 17]byte var x3420 [1 << 17]byte var x3421 [1 << 17]byte var x3422 [1 << 17]byte var x3423 [1 << 17]byte var x3424 [1 << 17]byte var x3425 [1 << 17]byte var x3426 [1 << 17]byte var x3427 [1 << 17]byte var x3428 [1 << 17]byte var x3429 [1 << 17]byte var x3430 [1 << 17]byte var x3431 [1 << 17]byte var x3432 [1 << 17]byte var x3433 [1 << 17]byte var x3434 [1 << 17]byte var x3435 [1 << 17]byte var x3436 [1 << 17]byte var x3437 [1 << 17]byte var x3438 [1 << 17]byte var x3439 [1 << 17]byte var x3440 [1 << 17]byte var x3441 [1 << 17]byte var x3442 [1 << 17]byte var x3443 [1 << 17]byte var x3444 [1 << 17]byte var x3445 [1 << 17]byte var x3446 [1 << 17]byte var x3447 [1 << 17]byte var x3448 [1 << 17]byte var x3449 [1 << 17]byte var x3450 [1 << 17]byte var x3451 [1 << 17]byte var x3452 [1 << 17]byte var x3453 [1 << 17]byte var x3454 [1 << 17]byte var x3455 [1 << 17]byte var x3456 [1 << 17]byte var x3457 [1 << 17]byte var x3458 [1 << 17]byte var x3459 [1 << 17]byte var x3460 [1 << 17]byte var x3461 [1 << 17]byte var x3462 [1 << 17]byte var x3463 [1 << 17]byte var x3464 [1 << 17]byte var x3465 [1 << 17]byte var x3466 [1 << 17]byte var x3467 [1 << 17]byte var x3468 [1 << 17]byte var x3469 [1 << 17]byte var x3470 [1 << 17]byte var x3471 [1 << 17]byte var x3472 [1 << 17]byte var x3473 [1 << 17]byte var x3474 [1 << 17]byte var x3475 [1 << 17]byte var x3476 [1 << 17]byte var x3477 [1 << 17]byte var x3478 [1 << 17]byte var x3479 [1 << 17]byte var x3480 [1 << 17]byte var x3481 [1 << 17]byte var x3482 [1 << 17]byte var x3483 [1 << 17]byte var x3484 [1 << 17]byte var x3485 [1 << 17]byte var x3486 [1 << 17]byte var x3487 [1 << 17]byte var x3488 [1 << 17]byte var x3489 [1 << 17]byte var x3490 [1 << 17]byte var x3491 [1 << 17]byte var x3492 [1 << 17]byte var x3493 [1 << 17]byte var x3494 [1 << 17]byte var x3495 [1 << 17]byte var x3496 [1 << 17]byte var x3497 [1 << 17]byte var x3498 [1 << 17]byte var x3499 [1 << 17]byte var x3500 [1 << 17]byte var x3501 [1 << 17]byte var x3502 [1 << 17]byte var x3503 [1 << 17]byte var x3504 [1 << 17]byte var x3505 [1 << 17]byte var x3506 [1 << 17]byte var x3507 [1 << 17]byte var x3508 [1 << 17]byte var x3509 [1 << 17]byte var x3510 [1 << 17]byte var x3511 [1 << 17]byte var x3512 [1 << 17]byte var x3513 [1 << 17]byte var x3514 [1 << 17]byte var x3515 [1 << 17]byte var x3516 [1 << 17]byte var x3517 [1 << 17]byte var x3518 [1 << 17]byte var x3519 [1 << 17]byte var x3520 [1 << 17]byte var x3521 [1 << 17]byte var x3522 [1 << 17]byte var x3523 [1 << 17]byte var x3524 [1 << 17]byte var x3525 [1 << 17]byte var x3526 [1 << 17]byte var x3527 [1 << 17]byte var x3528 [1 << 17]byte var x3529 [1 << 17]byte var x3530 [1 << 17]byte var x3531 [1 << 17]byte var x3532 [1 << 17]byte var x3533 [1 << 17]byte var x3534 [1 << 17]byte var x3535 [1 << 17]byte var x3536 [1 << 17]byte var x3537 [1 << 17]byte var x3538 [1 << 17]byte var x3539 [1 << 17]byte var x3540 [1 << 17]byte var x3541 [1 << 17]byte var x3542 [1 << 17]byte var x3543 [1 << 17]byte var x3544 [1 << 17]byte var x3545 [1 << 17]byte var x3546 [1 << 17]byte var x3547 [1 << 17]byte var x3548 [1 << 17]byte var x3549 [1 << 17]byte var x3550 [1 << 17]byte var x3551 [1 << 17]byte var x3552 [1 << 17]byte var x3553 [1 << 17]byte var x3554 [1 << 17]byte var x3555 [1 << 17]byte var x3556 [1 << 17]byte var x3557 [1 << 17]byte var x3558 [1 << 17]byte var x3559 [1 << 17]byte var x3560 [1 << 17]byte var x3561 [1 << 17]byte var x3562 [1 << 17]byte var x3563 [1 << 17]byte var x3564 [1 << 17]byte var x3565 [1 << 17]byte var x3566 [1 << 17]byte var x3567 [1 << 17]byte var x3568 [1 << 17]byte var x3569 [1 << 17]byte var x3570 [1 << 17]byte var x3571 [1 << 17]byte var x3572 [1 << 17]byte var x3573 [1 << 17]byte var x3574 [1 << 17]byte var x3575 [1 << 17]byte var x3576 [1 << 17]byte var x3577 [1 << 17]byte var x3578 [1 << 17]byte var x3579 [1 << 17]byte var x3580 [1 << 17]byte var x3581 [1 << 17]byte var x3582 [1 << 17]byte var x3583 [1 << 17]byte var x3584 [1 << 17]byte var x3585 [1 << 17]byte var x3586 [1 << 17]byte var x3587 [1 << 17]byte var x3588 [1 << 17]byte var x3589 [1 << 17]byte var x3590 [1 << 17]byte var x3591 [1 << 17]byte var x3592 [1 << 17]byte var x3593 [1 << 17]byte var x3594 [1 << 17]byte var x3595 [1 << 17]byte var x3596 [1 << 17]byte var x3597 [1 << 17]byte var x3598 [1 << 17]byte var x3599 [1 << 17]byte var x3600 [1 << 17]byte var x3601 [1 << 17]byte var x3602 [1 << 17]byte var x3603 [1 << 17]byte var x3604 [1 << 17]byte var x3605 [1 << 17]byte var x3606 [1 << 17]byte var x3607 [1 << 17]byte var x3608 [1 << 17]byte var x3609 [1 << 17]byte var x3610 [1 << 17]byte var x3611 [1 << 17]byte var x3612 [1 << 17]byte var x3613 [1 << 17]byte var x3614 [1 << 17]byte var x3615 [1 << 17]byte var x3616 [1 << 17]byte var x3617 [1 << 17]byte var x3618 [1 << 17]byte var x3619 [1 << 17]byte var x3620 [1 << 17]byte var x3621 [1 << 17]byte var x3622 [1 << 17]byte var x3623 [1 << 17]byte var x3624 [1 << 17]byte var x3625 [1 << 17]byte var x3626 [1 << 17]byte var x3627 [1 << 17]byte var x3628 [1 << 17]byte var x3629 [1 << 17]byte var x3630 [1 << 17]byte var x3631 [1 << 17]byte var x3632 [1 << 17]byte var x3633 [1 << 17]byte var x3634 [1 << 17]byte var x3635 [1 << 17]byte var x3636 [1 << 17]byte var x3637 [1 << 17]byte var x3638 [1 << 17]byte var x3639 [1 << 17]byte var x3640 [1 << 17]byte var x3641 [1 << 17]byte var x3642 [1 << 17]byte var x3643 [1 << 17]byte var x3644 [1 << 17]byte var x3645 [1 << 17]byte var x3646 [1 << 17]byte var x3647 [1 << 17]byte var x3648 [1 << 17]byte var x3649 [1 << 17]byte var x3650 [1 << 17]byte var x3651 [1 << 17]byte var x3652 [1 << 17]byte var x3653 [1 << 17]byte var x3654 [1 << 17]byte var x3655 [1 << 17]byte var x3656 [1 << 17]byte var x3657 [1 << 17]byte var x3658 [1 << 17]byte var x3659 [1 << 17]byte var x3660 [1 << 17]byte var x3661 [1 << 17]byte var x3662 [1 << 17]byte var x3663 [1 << 17]byte var x3664 [1 << 17]byte var x3665 [1 << 17]byte var x3666 [1 << 17]byte var x3667 [1 << 17]byte var x3668 [1 << 17]byte var x3669 [1 << 17]byte var x3670 [1 << 17]byte var x3671 [1 << 17]byte var x3672 [1 << 17]byte var x3673 [1 << 17]byte var x3674 [1 << 17]byte var x3675 [1 << 17]byte var x3676 [1 << 17]byte var x3677 [1 << 17]byte var x3678 [1 << 17]byte var x3679 [1 << 17]byte var x3680 [1 << 17]byte var x3681 [1 << 17]byte var x3682 [1 << 17]byte var x3683 [1 << 17]byte var x3684 [1 << 17]byte var x3685 [1 << 17]byte var x3686 [1 << 17]byte var x3687 [1 << 17]byte var x3688 [1 << 17]byte var x3689 [1 << 17]byte var x3690 [1 << 17]byte var x3691 [1 << 17]byte var x3692 [1 << 17]byte var x3693 [1 << 17]byte var x3694 [1 << 17]byte var x3695 [1 << 17]byte var x3696 [1 << 17]byte var x3697 [1 << 17]byte var x3698 [1 << 17]byte var x3699 [1 << 17]byte var x3700 [1 << 17]byte var x3701 [1 << 17]byte var x3702 [1 << 17]byte var x3703 [1 << 17]byte var x3704 [1 << 17]byte var x3705 [1 << 17]byte var x3706 [1 << 17]byte var x3707 [1 << 17]byte var x3708 [1 << 17]byte var x3709 [1 << 17]byte var x3710 [1 << 17]byte var x3711 [1 << 17]byte var x3712 [1 << 17]byte var x3713 [1 << 17]byte var x3714 [1 << 17]byte var x3715 [1 << 17]byte var x3716 [1 << 17]byte var x3717 [1 << 17]byte var x3718 [1 << 17]byte var x3719 [1 << 17]byte var x3720 [1 << 17]byte var x3721 [1 << 17]byte var x3722 [1 << 17]byte var x3723 [1 << 17]byte var x3724 [1 << 17]byte var x3725 [1 << 17]byte var x3726 [1 << 17]byte var x3727 [1 << 17]byte var x3728 [1 << 17]byte var x3729 [1 << 17]byte var x3730 [1 << 17]byte var x3731 [1 << 17]byte var x3732 [1 << 17]byte var x3733 [1 << 17]byte var x3734 [1 << 17]byte var x3735 [1 << 17]byte var x3736 [1 << 17]byte var x3737 [1 << 17]byte var x3738 [1 << 17]byte var x3739 [1 << 17]byte var x3740 [1 << 17]byte var x3741 [1 << 17]byte var x3742 [1 << 17]byte var x3743 [1 << 17]byte var x3744 [1 << 17]byte var x3745 [1 << 17]byte var x3746 [1 << 17]byte var x3747 [1 << 17]byte var x3748 [1 << 17]byte var x3749 [1 << 17]byte var x3750 [1 << 17]byte var x3751 [1 << 17]byte var x3752 [1 << 17]byte var x3753 [1 << 17]byte var x3754 [1 << 17]byte var x3755 [1 << 17]byte var x3756 [1 << 17]byte var x3757 [1 << 17]byte var x3758 [1 << 17]byte var x3759 [1 << 17]byte var x3760 [1 << 17]byte var x3761 [1 << 17]byte var x3762 [1 << 17]byte var x3763 [1 << 17]byte var x3764 [1 << 17]byte var x3765 [1 << 17]byte var x3766 [1 << 17]byte var x3767 [1 << 17]byte var x3768 [1 << 17]byte var x3769 [1 << 17]byte var x3770 [1 << 17]byte var x3771 [1 << 17]byte var x3772 [1 << 17]byte var x3773 [1 << 17]byte var x3774 [1 << 17]byte var x3775 [1 << 17]byte var x3776 [1 << 17]byte var x3777 [1 << 17]byte var x3778 [1 << 17]byte var x3779 [1 << 17]byte var x3780 [1 << 17]byte var x3781 [1 << 17]byte var x3782 [1 << 17]byte var x3783 [1 << 17]byte var x3784 [1 << 17]byte var x3785 [1 << 17]byte var x3786 [1 << 17]byte var x3787 [1 << 17]byte var x3788 [1 << 17]byte var x3789 [1 << 17]byte var x3790 [1 << 17]byte var x3791 [1 << 17]byte var x3792 [1 << 17]byte var x3793 [1 << 17]byte var x3794 [1 << 17]byte var x3795 [1 << 17]byte var x3796 [1 << 17]byte var x3797 [1 << 17]byte var x3798 [1 << 17]byte var x3799 [1 << 17]byte var x3800 [1 << 17]byte var x3801 [1 << 17]byte var x3802 [1 << 17]byte var x3803 [1 << 17]byte var x3804 [1 << 17]byte var x3805 [1 << 17]byte var x3806 [1 << 17]byte var x3807 [1 << 17]byte var x3808 [1 << 17]byte var x3809 [1 << 17]byte var x3810 [1 << 17]byte var x3811 [1 << 17]byte var x3812 [1 << 17]byte var x3813 [1 << 17]byte var x3814 [1 << 17]byte var x3815 [1 << 17]byte var x3816 [1 << 17]byte var x3817 [1 << 17]byte var x3818 [1 << 17]byte var x3819 [1 << 17]byte var x3820 [1 << 17]byte var x3821 [1 << 17]byte var x3822 [1 << 17]byte var x3823 [1 << 17]byte var x3824 [1 << 17]byte var x3825 [1 << 17]byte var x3826 [1 << 17]byte var x3827 [1 << 17]byte var x3828 [1 << 17]byte var x3829 [1 << 17]byte var x3830 [1 << 17]byte var x3831 [1 << 17]byte var x3832 [1 << 17]byte var x3833 [1 << 17]byte var x3834 [1 << 17]byte var x3835 [1 << 17]byte var x3836 [1 << 17]byte var x3837 [1 << 17]byte var x3838 [1 << 17]byte var x3839 [1 << 17]byte var x3840 [1 << 17]byte var x3841 [1 << 17]byte var x3842 [1 << 17]byte var x3843 [1 << 17]byte var x3844 [1 << 17]byte var x3845 [1 << 17]byte var x3846 [1 << 17]byte var x3847 [1 << 17]byte var x3848 [1 << 17]byte var x3849 [1 << 17]byte var x3850 [1 << 17]byte var x3851 [1 << 17]byte var x3852 [1 << 17]byte var x3853 [1 << 17]byte var x3854 [1 << 17]byte var x3855 [1 << 17]byte var x3856 [1 << 17]byte var x3857 [1 << 17]byte var x3858 [1 << 17]byte var x3859 [1 << 17]byte var x3860 [1 << 17]byte var x3861 [1 << 17]byte var x3862 [1 << 17]byte var x3863 [1 << 17]byte var x3864 [1 << 17]byte var x3865 [1 << 17]byte var x3866 [1 << 17]byte var x3867 [1 << 17]byte var x3868 [1 << 17]byte var x3869 [1 << 17]byte var x3870 [1 << 17]byte var x3871 [1 << 17]byte var x3872 [1 << 17]byte var x3873 [1 << 17]byte var x3874 [1 << 17]byte var x3875 [1 << 17]byte var x3876 [1 << 17]byte var x3877 [1 << 17]byte var x3878 [1 << 17]byte var x3879 [1 << 17]byte var x3880 [1 << 17]byte var x3881 [1 << 17]byte var x3882 [1 << 17]byte var x3883 [1 << 17]byte var x3884 [1 << 17]byte var x3885 [1 << 17]byte var x3886 [1 << 17]byte var x3887 [1 << 17]byte var x3888 [1 << 17]byte var x3889 [1 << 17]byte var x3890 [1 << 17]byte var x3891 [1 << 17]byte var x3892 [1 << 17]byte var x3893 [1 << 17]byte var x3894 [1 << 17]byte var x3895 [1 << 17]byte var x3896 [1 << 17]byte var x3897 [1 << 17]byte var x3898 [1 << 17]byte var x3899 [1 << 17]byte var x3900 [1 << 17]byte var x3901 [1 << 17]byte var x3902 [1 << 17]byte var x3903 [1 << 17]byte var x3904 [1 << 17]byte var x3905 [1 << 17]byte var x3906 [1 << 17]byte var x3907 [1 << 17]byte var x3908 [1 << 17]byte var x3909 [1 << 17]byte var x3910 [1 << 17]byte var x3911 [1 << 17]byte var x3912 [1 << 17]byte var x3913 [1 << 17]byte var x3914 [1 << 17]byte var x3915 [1 << 17]byte var x3916 [1 << 17]byte var x3917 [1 << 17]byte var x3918 [1 << 17]byte var x3919 [1 << 17]byte var x3920 [1 << 17]byte var x3921 [1 << 17]byte var x3922 [1 << 17]byte var x3923 [1 << 17]byte var x3924 [1 << 17]byte var x3925 [1 << 17]byte var x3926 [1 << 17]byte var x3927 [1 << 17]byte var x3928 [1 << 17]byte var x3929 [1 << 17]byte var x3930 [1 << 17]byte var x3931 [1 << 17]byte var x3932 [1 << 17]byte var x3933 [1 << 17]byte var x3934 [1 << 17]byte var x3935 [1 << 17]byte var x3936 [1 << 17]byte var x3937 [1 << 17]byte var x3938 [1 << 17]byte var x3939 [1 << 17]byte var x3940 [1 << 17]byte var x3941 [1 << 17]byte var x3942 [1 << 17]byte var x3943 [1 << 17]byte var x3944 [1 << 17]byte var x3945 [1 << 17]byte var x3946 [1 << 17]byte var x3947 [1 << 17]byte var x3948 [1 << 17]byte var x3949 [1 << 17]byte var x3950 [1 << 17]byte var x3951 [1 << 17]byte var x3952 [1 << 17]byte var x3953 [1 << 17]byte var x3954 [1 << 17]byte var x3955 [1 << 17]byte var x3956 [1 << 17]byte var x3957 [1 << 17]byte var x3958 [1 << 17]byte var x3959 [1 << 17]byte var x3960 [1 << 17]byte var x3961 [1 << 17]byte var x3962 [1 << 17]byte var x3963 [1 << 17]byte var x3964 [1 << 17]byte var x3965 [1 << 17]byte var x3966 [1 << 17]byte var x3967 [1 << 17]byte var x3968 [1 << 17]byte var x3969 [1 << 17]byte var x3970 [1 << 17]byte var x3971 [1 << 17]byte var x3972 [1 << 17]byte var x3973 [1 << 17]byte var x3974 [1 << 17]byte var x3975 [1 << 17]byte var x3976 [1 << 17]byte var x3977 [1 << 17]byte var x3978 [1 << 17]byte var x3979 [1 << 17]byte var x3980 [1 << 17]byte var x3981 [1 << 17]byte var x3982 [1 << 17]byte var x3983 [1 << 17]byte var x3984 [1 << 17]byte var x3985 [1 << 17]byte var x3986 [1 << 17]byte var x3987 [1 << 17]byte var x3988 [1 << 17]byte var x3989 [1 << 17]byte var x3990 [1 << 17]byte var x3991 [1 << 17]byte var x3992 [1 << 17]byte var x3993 [1 << 17]byte var x3994 [1 << 17]byte var x3995 [1 << 17]byte var x3996 [1 << 17]byte var x3997 [1 << 17]byte var x3998 [1 << 17]byte var x3999 [1 << 17]byte var x4000 [1 << 17]byte var x4001 [1 << 17]byte var x4002 [1 << 17]byte var x4003 [1 << 17]byte var x4004 [1 << 17]byte var x4005 [1 << 17]byte var x4006 [1 << 17]byte var x4007 [1 << 17]byte var x4008 [1 << 17]byte var x4009 [1 << 17]byte var x4010 [1 << 17]byte var x4011 [1 << 17]byte var x4012 [1 << 17]byte var x4013 [1 << 17]byte var x4014 [1 << 17]byte var x4015 [1 << 17]byte var x4016 [1 << 17]byte var x4017 [1 << 17]byte var x4018 [1 << 17]byte var x4019 [1 << 17]byte var x4020 [1 << 17]byte var x4021 [1 << 17]byte var x4022 [1 << 17]byte var x4023 [1 << 17]byte var x4024 [1 << 17]byte var x4025 [1 << 17]byte var x4026 [1 << 17]byte var x4027 [1 << 17]byte var x4028 [1 << 17]byte var x4029 [1 << 17]byte var x4030 [1 << 17]byte var x4031 [1 << 17]byte var x4032 [1 << 17]byte var x4033 [1 << 17]byte var x4034 [1 << 17]byte var x4035 [1 << 17]byte var x4036 [1 << 17]byte var x4037 [1 << 17]byte var x4038 [1 << 17]byte var x4039 [1 << 17]byte var x4040 [1 << 17]byte var x4041 [1 << 17]byte var x4042 [1 << 17]byte var x4043 [1 << 17]byte var x4044 [1 << 17]byte var x4045 [1 << 17]byte var x4046 [1 << 17]byte var x4047 [1 << 17]byte var x4048 [1 << 17]byte var x4049 [1 << 17]byte var x4050 [1 << 17]byte var x4051 [1 << 17]byte var x4052 [1 << 17]byte var x4053 [1 << 17]byte var x4054 [1 << 17]byte var x4055 [1 << 17]byte var x4056 [1 << 17]byte var x4057 [1 << 17]byte var x4058 [1 << 17]byte var x4059 [1 << 17]byte var x4060 [1 << 17]byte var x4061 [1 << 17]byte var x4062 [1 << 17]byte var x4063 [1 << 17]byte var x4064 [1 << 17]byte var x4065 [1 << 17]byte var x4066 [1 << 17]byte var x4067 [1 << 17]byte var x4068 [1 << 17]byte var x4069 [1 << 17]byte var x4070 [1 << 17]byte var x4071 [1 << 17]byte var x4072 [1 << 17]byte var x4073 [1 << 17]byte var x4074 [1 << 17]byte var x4075 [1 << 17]byte var x4076 [1 << 17]byte var x4077 [1 << 17]byte var x4078 [1 << 17]byte var x4079 [1 << 17]byte var x4080 [1 << 17]byte var x4081 [1 << 17]byte var x4082 [1 << 17]byte var x4083 [1 << 17]byte var x4084 [1 << 17]byte var x4085 [1 << 17]byte var x4086 [1 << 17]byte var x4087 [1 << 17]byte var x4088 [1 << 17]byte var x4089 [1 << 17]byte var x4090 [1 << 17]byte var x4091 [1 << 17]byte var x4092 [1 << 17]byte var x4093 [1 << 17]byte var x4094 [1 << 17]byte var x4095 [1 << 17]byte var x4096 [1 << 17]byte var x4097 [1 << 17]byte var x4098 [1 << 17]byte var x4099 [1 << 17]byte var x4100 [1 << 17]byte var x4101 [1 << 17]byte var x4102 [1 << 17]byte var x4103 [1 << 17]byte var x4104 [1 << 17]byte var x4105 [1 << 17]byte var x4106 [1 << 17]byte var x4107 [1 << 17]byte var x4108 [1 << 17]byte var x4109 [1 << 17]byte var x4110 [1 << 17]byte var x4111 [1 << 17]byte var x4112 [1 << 17]byte var x4113 [1 << 17]byte var x4114 [1 << 17]byte var x4115 [1 << 17]byte var x4116 [1 << 17]byte var x4117 [1 << 17]byte var x4118 [1 << 17]byte var x4119 [1 << 17]byte var x4120 [1 << 17]byte var x4121 [1 << 17]byte var x4122 [1 << 17]byte var x4123 [1 << 17]byte var x4124 [1 << 17]byte var x4125 [1 << 17]byte var x4126 [1 << 17]byte var x4127 [1 << 17]byte var x4128 [1 << 17]byte var x4129 [1 << 17]byte var x4130 [1 << 17]byte var x4131 [1 << 17]byte var x4132 [1 << 17]byte var x4133 [1 << 17]byte var x4134 [1 << 17]byte var x4135 [1 << 17]byte var x4136 [1 << 17]byte var x4137 [1 << 17]byte var x4138 [1 << 17]byte var x4139 [1 << 17]byte var x4140 [1 << 17]byte var x4141 [1 << 17]byte var x4142 [1 << 17]byte var x4143 [1 << 17]byte var x4144 [1 << 17]byte var x4145 [1 << 17]byte var x4146 [1 << 17]byte var x4147 [1 << 17]byte var x4148 [1 << 17]byte var x4149 [1 << 17]byte var x4150 [1 << 17]byte var x4151 [1 << 17]byte var x4152 [1 << 17]byte var x4153 [1 << 17]byte var x4154 [1 << 17]byte var x4155 [1 << 17]byte var x4156 [1 << 17]byte var x4157 [1 << 17]byte var x4158 [1 << 17]byte var x4159 [1 << 17]byte var x4160 [1 << 17]byte var x4161 [1 << 17]byte var x4162 [1 << 17]byte var x4163 [1 << 17]byte var x4164 [1 << 17]byte var x4165 [1 << 17]byte var x4166 [1 << 17]byte var x4167 [1 << 17]byte var x4168 [1 << 17]byte var x4169 [1 << 17]byte var x4170 [1 << 17]byte var x4171 [1 << 17]byte var x4172 [1 << 17]byte var x4173 [1 << 17]byte var x4174 [1 << 17]byte var x4175 [1 << 17]byte var x4176 [1 << 17]byte var x4177 [1 << 17]byte var x4178 [1 << 17]byte var x4179 [1 << 17]byte var x4180 [1 << 17]byte var x4181 [1 << 17]byte var x4182 [1 << 17]byte var x4183 [1 << 17]byte var x4184 [1 << 17]byte var x4185 [1 << 17]byte var x4186 [1 << 17]byte var x4187 [1 << 17]byte var x4188 [1 << 17]byte var x4189 [1 << 17]byte var x4190 [1 << 17]byte var x4191 [1 << 17]byte var x4192 [1 << 17]byte var x4193 [1 << 17]byte var x4194 [1 << 17]byte var x4195 [1 << 17]byte var x4196 [1 << 17]byte var x4197 [1 << 17]byte var x4198 [1 << 17]byte var x4199 [1 << 17]byte var x4200 [1 << 17]byte var x4201 [1 << 17]byte var x4202 [1 << 17]byte var x4203 [1 << 17]byte var x4204 [1 << 17]byte var x4205 [1 << 17]byte var x4206 [1 << 17]byte var x4207 [1 << 17]byte var x4208 [1 << 17]byte var x4209 [1 << 17]byte var x4210 [1 << 17]byte var x4211 [1 << 17]byte var x4212 [1 << 17]byte var x4213 [1 << 17]byte var x4214 [1 << 17]byte var x4215 [1 << 17]byte var x4216 [1 << 17]byte var x4217 [1 << 17]byte var x4218 [1 << 17]byte var x4219 [1 << 17]byte var x4220 [1 << 17]byte var x4221 [1 << 17]byte var x4222 [1 << 17]byte var x4223 [1 << 17]byte var x4224 [1 << 17]byte var x4225 [1 << 17]byte var x4226 [1 << 17]byte var x4227 [1 << 17]byte var x4228 [1 << 17]byte var x4229 [1 << 17]byte var x4230 [1 << 17]byte var x4231 [1 << 17]byte var x4232 [1 << 17]byte var x4233 [1 << 17]byte var x4234 [1 << 17]byte var x4235 [1 << 17]byte var x4236 [1 << 17]byte var x4237 [1 << 17]byte var x4238 [1 << 17]byte var x4239 [1 << 17]byte var x4240 [1 << 17]byte var x4241 [1 << 17]byte var x4242 [1 << 17]byte var x4243 [1 << 17]byte var x4244 [1 << 17]byte var x4245 [1 << 17]byte var x4246 [1 << 17]byte var x4247 [1 << 17]byte var x4248 [1 << 17]byte var x4249 [1 << 17]byte var x4250 [1 << 17]byte var x4251 [1 << 17]byte var x4252 [1 << 17]byte var x4253 [1 << 17]byte var x4254 [1 << 17]byte var x4255 [1 << 17]byte var x4256 [1 << 17]byte var x4257 [1 << 17]byte var x4258 [1 << 17]byte var x4259 [1 << 17]byte var x4260 [1 << 17]byte var x4261 [1 << 17]byte var x4262 [1 << 17]byte var x4263 [1 << 17]byte var x4264 [1 << 17]byte var x4265 [1 << 17]byte var x4266 [1 << 17]byte var x4267 [1 << 17]byte var x4268 [1 << 17]byte var x4269 [1 << 17]byte var x4270 [1 << 17]byte var x4271 [1 << 17]byte var x4272 [1 << 17]byte var x4273 [1 << 17]byte var x4274 [1 << 17]byte var x4275 [1 << 17]byte var x4276 [1 << 17]byte var x4277 [1 << 17]byte var x4278 [1 << 17]byte var x4279 [1 << 17]byte var x4280 [1 << 17]byte var x4281 [1 << 17]byte var x4282 [1 << 17]byte var x4283 [1 << 17]byte var x4284 [1 << 17]byte var x4285 [1 << 17]byte var x4286 [1 << 17]byte var x4287 [1 << 17]byte var x4288 [1 << 17]byte var x4289 [1 << 17]byte var x4290 [1 << 17]byte var x4291 [1 << 17]byte var x4292 [1 << 17]byte var x4293 [1 << 17]byte var x4294 [1 << 17]byte var x4295 [1 << 17]byte var x4296 [1 << 17]byte var x4297 [1 << 17]byte var x4298 [1 << 17]byte var x4299 [1 << 17]byte var x4300 [1 << 17]byte var x4301 [1 << 17]byte var x4302 [1 << 17]byte var x4303 [1 << 17]byte var x4304 [1 << 17]byte var x4305 [1 << 17]byte var x4306 [1 << 17]byte var x4307 [1 << 17]byte var x4308 [1 << 17]byte var x4309 [1 << 17]byte var x4310 [1 << 17]byte var x4311 [1 << 17]byte var x4312 [1 << 17]byte var x4313 [1 << 17]byte var x4314 [1 << 17]byte var x4315 [1 << 17]byte var x4316 [1 << 17]byte var x4317 [1 << 17]byte var x4318 [1 << 17]byte var x4319 [1 << 17]byte var x4320 [1 << 17]byte var x4321 [1 << 17]byte var x4322 [1 << 17]byte var x4323 [1 << 17]byte var x4324 [1 << 17]byte var x4325 [1 << 17]byte var x4326 [1 << 17]byte var x4327 [1 << 17]byte var x4328 [1 << 17]byte var x4329 [1 << 17]byte var x4330 [1 << 17]byte var x4331 [1 << 17]byte var x4332 [1 << 17]byte var x4333 [1 << 17]byte var x4334 [1 << 17]byte var x4335 [1 << 17]byte var x4336 [1 << 17]byte var x4337 [1 << 17]byte var x4338 [1 << 17]byte var x4339 [1 << 17]byte var x4340 [1 << 17]byte var x4341 [1 << 17]byte var x4342 [1 << 17]byte var x4343 [1 << 17]byte var x4344 [1 << 17]byte var x4345 [1 << 17]byte var x4346 [1 << 17]byte var x4347 [1 << 17]byte var x4348 [1 << 17]byte var x4349 [1 << 17]byte var x4350 [1 << 17]byte var x4351 [1 << 17]byte var x4352 [1 << 17]byte var x4353 [1 << 17]byte var x4354 [1 << 17]byte var x4355 [1 << 17]byte var x4356 [1 << 17]byte var x4357 [1 << 17]byte var x4358 [1 << 17]byte var x4359 [1 << 17]byte var x4360 [1 << 17]byte var x4361 [1 << 17]byte var x4362 [1 << 17]byte var x4363 [1 << 17]byte var x4364 [1 << 17]byte var x4365 [1 << 17]byte var x4366 [1 << 17]byte var x4367 [1 << 17]byte var x4368 [1 << 17]byte var x4369 [1 << 17]byte var x4370 [1 << 17]byte var x4371 [1 << 17]byte var x4372 [1 << 17]byte var x4373 [1 << 17]byte var x4374 [1 << 17]byte var x4375 [1 << 17]byte var x4376 [1 << 17]byte var x4377 [1 << 17]byte var x4378 [1 << 17]byte var x4379 [1 << 17]byte var x4380 [1 << 17]byte var x4381 [1 << 17]byte var x4382 [1 << 17]byte var x4383 [1 << 17]byte var x4384 [1 << 17]byte var x4385 [1 << 17]byte var x4386 [1 << 17]byte var x4387 [1 << 17]byte var x4388 [1 << 17]byte var x4389 [1 << 17]byte var x4390 [1 << 17]byte var x4391 [1 << 17]byte var x4392 [1 << 17]byte var x4393 [1 << 17]byte var x4394 [1 << 17]byte var x4395 [1 << 17]byte var x4396 [1 << 17]byte var x4397 [1 << 17]byte var x4398 [1 << 17]byte var x4399 [1 << 17]byte var x4400 [1 << 17]byte var x4401 [1 << 17]byte var x4402 [1 << 17]byte var x4403 [1 << 17]byte var x4404 [1 << 17]byte var x4405 [1 << 17]byte var x4406 [1 << 17]byte var x4407 [1 << 17]byte var x4408 [1 << 17]byte var x4409 [1 << 17]byte var x4410 [1 << 17]byte var x4411 [1 << 17]byte var x4412 [1 << 17]byte var x4413 [1 << 17]byte var x4414 [1 << 17]byte var x4415 [1 << 17]byte var x4416 [1 << 17]byte var x4417 [1 << 17]byte var x4418 [1 << 17]byte var x4419 [1 << 17]byte var x4420 [1 << 17]byte var x4421 [1 << 17]byte var x4422 [1 << 17]byte var x4423 [1 << 17]byte var x4424 [1 << 17]byte var x4425 [1 << 17]byte var x4426 [1 << 17]byte var x4427 [1 << 17]byte var x4428 [1 << 17]byte var x4429 [1 << 17]byte var x4430 [1 << 17]byte var x4431 [1 << 17]byte var x4432 [1 << 17]byte var x4433 [1 << 17]byte var x4434 [1 << 17]byte var x4435 [1 << 17]byte var x4436 [1 << 17]byte var x4437 [1 << 17]byte var x4438 [1 << 17]byte var x4439 [1 << 17]byte var x4440 [1 << 17]byte var x4441 [1 << 17]byte var x4442 [1 << 17]byte var x4443 [1 << 17]byte var x4444 [1 << 17]byte var x4445 [1 << 17]byte var x4446 [1 << 17]byte var x4447 [1 << 17]byte var x4448 [1 << 17]byte var x4449 [1 << 17]byte var x4450 [1 << 17]byte var x4451 [1 << 17]byte var x4452 [1 << 17]byte var x4453 [1 << 17]byte var x4454 [1 << 17]byte var x4455 [1 << 17]byte var x4456 [1 << 17]byte var x4457 [1 << 17]byte var x4458 [1 << 17]byte var x4459 [1 << 17]byte var x4460 [1 << 17]byte var x4461 [1 << 17]byte var x4462 [1 << 17]byte var x4463 [1 << 17]byte var x4464 [1 << 17]byte var x4465 [1 << 17]byte var x4466 [1 << 17]byte var x4467 [1 << 17]byte var x4468 [1 << 17]byte var x4469 [1 << 17]byte var x4470 [1 << 17]byte var x4471 [1 << 17]byte var x4472 [1 << 17]byte var x4473 [1 << 17]byte var x4474 [1 << 17]byte var x4475 [1 << 17]byte var x4476 [1 << 17]byte var x4477 [1 << 17]byte var x4478 [1 << 17]byte var x4479 [1 << 17]byte var x4480 [1 << 17]byte var x4481 [1 << 17]byte var x4482 [1 << 17]byte var x4483 [1 << 17]byte var x4484 [1 << 17]byte var x4485 [1 << 17]byte var x4486 [1 << 17]byte var x4487 [1 << 17]byte var x4488 [1 << 17]byte var x4489 [1 << 17]byte var x4490 [1 << 17]byte var x4491 [1 << 17]byte var x4492 [1 << 17]byte var x4493 [1 << 17]byte var x4494 [1 << 17]byte var x4495 [1 << 17]byte var x4496 [1 << 17]byte var x4497 [1 << 17]byte var x4498 [1 << 17]byte var x4499 [1 << 17]byte var x4500 [1 << 17]byte var x4501 [1 << 17]byte var x4502 [1 << 17]byte var x4503 [1 << 17]byte var x4504 [1 << 17]byte var x4505 [1 << 17]byte var x4506 [1 << 17]byte var x4507 [1 << 17]byte var x4508 [1 << 17]byte var x4509 [1 << 17]byte var x4510 [1 << 17]byte var x4511 [1 << 17]byte var x4512 [1 << 17]byte var x4513 [1 << 17]byte var x4514 [1 << 17]byte var x4515 [1 << 17]byte var x4516 [1 << 17]byte var x4517 [1 << 17]byte var x4518 [1 << 17]byte var x4519 [1 << 17]byte var x4520 [1 << 17]byte var x4521 [1 << 17]byte var x4522 [1 << 17]byte var x4523 [1 << 17]byte var x4524 [1 << 17]byte var x4525 [1 << 17]byte var x4526 [1 << 17]byte var x4527 [1 << 17]byte var x4528 [1 << 17]byte var x4529 [1 << 17]byte var x4530 [1 << 17]byte var x4531 [1 << 17]byte var x4532 [1 << 17]byte var x4533 [1 << 17]byte var x4534 [1 << 17]byte var x4535 [1 << 17]byte var x4536 [1 << 17]byte var x4537 [1 << 17]byte var x4538 [1 << 17]byte var x4539 [1 << 17]byte var x4540 [1 << 17]byte var x4541 [1 << 17]byte var x4542 [1 << 17]byte var x4543 [1 << 17]byte var x4544 [1 << 17]byte var x4545 [1 << 17]byte var x4546 [1 << 17]byte var x4547 [1 << 17]byte var x4548 [1 << 17]byte var x4549 [1 << 17]byte var x4550 [1 << 17]byte var x4551 [1 << 17]byte var x4552 [1 << 17]byte var x4553 [1 << 17]byte var x4554 [1 << 17]byte var x4555 [1 << 17]byte var x4556 [1 << 17]byte var x4557 [1 << 17]byte var x4558 [1 << 17]byte var x4559 [1 << 17]byte var x4560 [1 << 17]byte var x4561 [1 << 17]byte var x4562 [1 << 17]byte var x4563 [1 << 17]byte var x4564 [1 << 17]byte var x4565 [1 << 17]byte var x4566 [1 << 17]byte var x4567 [1 << 17]byte var x4568 [1 << 17]byte var x4569 [1 << 17]byte var x4570 [1 << 17]byte var x4571 [1 << 17]byte var x4572 [1 << 17]byte var x4573 [1 << 17]byte var x4574 [1 << 17]byte var x4575 [1 << 17]byte var x4576 [1 << 17]byte var x4577 [1 << 17]byte var x4578 [1 << 17]byte var x4579 [1 << 17]byte var x4580 [1 << 17]byte var x4581 [1 << 17]byte var x4582 [1 << 17]byte var x4583 [1 << 17]byte var x4584 [1 << 17]byte var x4585 [1 << 17]byte var x4586 [1 << 17]byte var x4587 [1 << 17]byte var x4588 [1 << 17]byte var x4589 [1 << 17]byte var x4590 [1 << 17]byte var x4591 [1 << 17]byte var x4592 [1 << 17]byte var x4593 [1 << 17]byte var x4594 [1 << 17]byte var x4595 [1 << 17]byte var x4596 [1 << 17]byte var x4597 [1 << 17]byte var x4598 [1 << 17]byte var x4599 [1 << 17]byte var x4600 [1 << 17]byte var x4601 [1 << 17]byte var x4602 [1 << 17]byte var x4603 [1 << 17]byte var x4604 [1 << 17]byte var x4605 [1 << 17]byte var x4606 [1 << 17]byte var x4607 [1 << 17]byte var x4608 [1 << 17]byte var x4609 [1 << 17]byte var x4610 [1 << 17]byte var x4611 [1 << 17]byte var x4612 [1 << 17]byte var x4613 [1 << 17]byte var x4614 [1 << 17]byte var x4615 [1 << 17]byte var x4616 [1 << 17]byte var x4617 [1 << 17]byte var x4618 [1 << 17]byte var x4619 [1 << 17]byte var x4620 [1 << 17]byte var x4621 [1 << 17]byte var x4622 [1 << 17]byte var x4623 [1 << 17]byte var x4624 [1 << 17]byte var x4625 [1 << 17]byte var x4626 [1 << 17]byte var x4627 [1 << 17]byte var x4628 [1 << 17]byte var x4629 [1 << 17]byte var x4630 [1 << 17]byte var x4631 [1 << 17]byte var x4632 [1 << 17]byte var x4633 [1 << 17]byte var x4634 [1 << 17]byte var x4635 [1 << 17]byte var x4636 [1 << 17]byte var x4637 [1 << 17]byte var x4638 [1 << 17]byte var x4639 [1 << 17]byte var x4640 [1 << 17]byte var x4641 [1 << 17]byte var x4642 [1 << 17]byte var x4643 [1 << 17]byte var x4644 [1 << 17]byte var x4645 [1 << 17]byte var x4646 [1 << 17]byte var x4647 [1 << 17]byte var x4648 [1 << 17]byte var x4649 [1 << 17]byte var x4650 [1 << 17]byte var x4651 [1 << 17]byte var x4652 [1 << 17]byte var x4653 [1 << 17]byte var x4654 [1 << 17]byte var x4655 [1 << 17]byte var x4656 [1 << 17]byte var x4657 [1 << 17]byte var x4658 [1 << 17]byte var x4659 [1 << 17]byte var x4660 [1 << 17]byte var x4661 [1 << 17]byte var x4662 [1 << 17]byte var x4663 [1 << 17]byte var x4664 [1 << 17]byte var x4665 [1 << 17]byte var x4666 [1 << 17]byte var x4667 [1 << 17]byte var x4668 [1 << 17]byte var x4669 [1 << 17]byte var x4670 [1 << 17]byte var x4671 [1 << 17]byte var x4672 [1 << 17]byte var x4673 [1 << 17]byte var x4674 [1 << 17]byte var x4675 [1 << 17]byte var x4676 [1 << 17]byte var x4677 [1 << 17]byte var x4678 [1 << 17]byte var x4679 [1 << 17]byte var x4680 [1 << 17]byte var x4681 [1 << 17]byte var x4682 [1 << 17]byte var x4683 [1 << 17]byte var x4684 [1 << 17]byte var x4685 [1 << 17]byte var x4686 [1 << 17]byte var x4687 [1 << 17]byte var x4688 [1 << 17]byte var x4689 [1 << 17]byte var x4690 [1 << 17]byte var x4691 [1 << 17]byte var x4692 [1 << 17]byte var x4693 [1 << 17]byte var x4694 [1 << 17]byte var x4695 [1 << 17]byte var x4696 [1 << 17]byte var x4697 [1 << 17]byte var x4698 [1 << 17]byte var x4699 [1 << 17]byte var x4700 [1 << 17]byte var x4701 [1 << 17]byte var x4702 [1 << 17]byte var x4703 [1 << 17]byte var x4704 [1 << 17]byte var x4705 [1 << 17]byte var x4706 [1 << 17]byte var x4707 [1 << 17]byte var x4708 [1 << 17]byte var x4709 [1 << 17]byte var x4710 [1 << 17]byte var x4711 [1 << 17]byte var x4712 [1 << 17]byte var x4713 [1 << 17]byte var x4714 [1 << 17]byte var x4715 [1 << 17]byte var x4716 [1 << 17]byte var x4717 [1 << 17]byte var x4718 [1 << 17]byte var x4719 [1 << 17]byte var x4720 [1 << 17]byte var x4721 [1 << 17]byte var x4722 [1 << 17]byte var x4723 [1 << 17]byte var x4724 [1 << 17]byte var x4725 [1 << 17]byte var x4726 [1 << 17]byte var x4727 [1 << 17]byte var x4728 [1 << 17]byte var x4729 [1 << 17]byte var x4730 [1 << 17]byte var x4731 [1 << 17]byte var x4732 [1 << 17]byte var x4733 [1 << 17]byte var x4734 [1 << 17]byte var x4735 [1 << 17]byte var x4736 [1 << 17]byte var x4737 [1 << 17]byte var x4738 [1 << 17]byte var x4739 [1 << 17]byte var x4740 [1 << 17]byte var x4741 [1 << 17]byte var x4742 [1 << 17]byte var x4743 [1 << 17]byte var x4744 [1 << 17]byte var x4745 [1 << 17]byte var x4746 [1 << 17]byte var x4747 [1 << 17]byte var x4748 [1 << 17]byte var x4749 [1 << 17]byte var x4750 [1 << 17]byte var x4751 [1 << 17]byte var x4752 [1 << 17]byte var x4753 [1 << 17]byte var x4754 [1 << 17]byte var x4755 [1 << 17]byte var x4756 [1 << 17]byte var x4757 [1 << 17]byte var x4758 [1 << 17]byte var x4759 [1 << 17]byte var x4760 [1 << 17]byte var x4761 [1 << 17]byte var x4762 [1 << 17]byte var x4763 [1 << 17]byte var x4764 [1 << 17]byte var x4765 [1 << 17]byte var x4766 [1 << 17]byte var x4767 [1 << 17]byte var x4768 [1 << 17]byte var x4769 [1 << 17]byte var x4770 [1 << 17]byte var x4771 [1 << 17]byte var x4772 [1 << 17]byte var x4773 [1 << 17]byte var x4774 [1 << 17]byte var x4775 [1 << 17]byte var x4776 [1 << 17]byte var x4777 [1 << 17]byte var x4778 [1 << 17]byte var x4779 [1 << 17]byte var x4780 [1 << 17]byte var x4781 [1 << 17]byte var x4782 [1 << 17]byte var x4783 [1 << 17]byte var x4784 [1 << 17]byte var x4785 [1 << 17]byte var x4786 [1 << 17]byte var x4787 [1 << 17]byte var x4788 [1 << 17]byte var x4789 [1 << 17]byte var x4790 [1 << 17]byte var x4791 [1 << 17]byte var x4792 [1 << 17]byte var x4793 [1 << 17]byte var x4794 [1 << 17]byte var x4795 [1 << 17]byte var x4796 [1 << 17]byte var x4797 [1 << 17]byte var x4798 [1 << 17]byte var x4799 [1 << 17]byte var x4800 [1 << 17]byte var x4801 [1 << 17]byte var x4802 [1 << 17]byte var x4803 [1 << 17]byte var x4804 [1 << 17]byte var x4805 [1 << 17]byte var x4806 [1 << 17]byte var x4807 [1 << 17]byte var x4808 [1 << 17]byte var x4809 [1 << 17]byte var x4810 [1 << 17]byte var x4811 [1 << 17]byte var x4812 [1 << 17]byte var x4813 [1 << 17]byte var x4814 [1 << 17]byte var x4815 [1 << 17]byte var x4816 [1 << 17]byte var x4817 [1 << 17]byte var x4818 [1 << 17]byte var x4819 [1 << 17]byte var x4820 [1 << 17]byte var x4821 [1 << 17]byte var x4822 [1 << 17]byte var x4823 [1 << 17]byte var x4824 [1 << 17]byte var x4825 [1 << 17]byte var x4826 [1 << 17]byte var x4827 [1 << 17]byte var x4828 [1 << 17]byte var x4829 [1 << 17]byte var x4830 [1 << 17]byte var x4831 [1 << 17]byte var x4832 [1 << 17]byte var x4833 [1 << 17]byte var x4834 [1 << 17]byte var x4835 [1 << 17]byte var x4836 [1 << 17]byte var x4837 [1 << 17]byte var x4838 [1 << 17]byte var x4839 [1 << 17]byte var x4840 [1 << 17]byte var x4841 [1 << 17]byte var x4842 [1 << 17]byte var x4843 [1 << 17]byte var x4844 [1 << 17]byte var x4845 [1 << 17]byte var x4846 [1 << 17]byte var x4847 [1 << 17]byte var x4848 [1 << 17]byte var x4849 [1 << 17]byte var x4850 [1 << 17]byte var x4851 [1 << 17]byte var x4852 [1 << 17]byte var x4853 [1 << 17]byte var x4854 [1 << 17]byte var x4855 [1 << 17]byte var x4856 [1 << 17]byte var x4857 [1 << 17]byte var x4858 [1 << 17]byte var x4859 [1 << 17]byte var x4860 [1 << 17]byte var x4861 [1 << 17]byte var x4862 [1 << 17]byte var x4863 [1 << 17]byte var x4864 [1 << 17]byte var x4865 [1 << 17]byte var x4866 [1 << 17]byte var x4867 [1 << 17]byte var x4868 [1 << 17]byte var x4869 [1 << 17]byte var x4870 [1 << 17]byte var x4871 [1 << 17]byte var x4872 [1 << 17]byte var x4873 [1 << 17]byte var x4874 [1 << 17]byte var x4875 [1 << 17]byte var x4876 [1 << 17]byte var x4877 [1 << 17]byte var x4878 [1 << 17]byte var x4879 [1 << 17]byte var x4880 [1 << 17]byte var x4881 [1 << 17]byte var x4882 [1 << 17]byte var x4883 [1 << 17]byte var x4884 [1 << 17]byte var x4885 [1 << 17]byte var x4886 [1 << 17]byte var x4887 [1 << 17]byte var x4888 [1 << 17]byte var x4889 [1 << 17]byte var x4890 [1 << 17]byte var x4891 [1 << 17]byte var x4892 [1 << 17]byte var x4893 [1 << 17]byte var x4894 [1 << 17]byte var x4895 [1 << 17]byte var x4896 [1 << 17]byte var x4897 [1 << 17]byte var x4898 [1 << 17]byte var x4899 [1 << 17]byte var x4900 [1 << 17]byte var x4901 [1 << 17]byte var x4902 [1 << 17]byte var x4903 [1 << 17]byte var x4904 [1 << 17]byte var x4905 [1 << 17]byte var x4906 [1 << 17]byte var x4907 [1 << 17]byte var x4908 [1 << 17]byte var x4909 [1 << 17]byte var x4910 [1 << 17]byte var x4911 [1 << 17]byte var x4912 [1 << 17]byte var x4913 [1 << 17]byte var x4914 [1 << 17]byte var x4915 [1 << 17]byte var x4916 [1 << 17]byte var x4917 [1 << 17]byte var x4918 [1 << 17]byte var x4919 [1 << 17]byte var x4920 [1 << 17]byte var x4921 [1 << 17]byte var x4922 [1 << 17]byte var x4923 [1 << 17]byte var x4924 [1 << 17]byte var x4925 [1 << 17]byte var x4926 [1 << 17]byte var x4927 [1 << 17]byte var x4928 [1 << 17]byte var x4929 [1 << 17]byte var x4930 [1 << 17]byte var x4931 [1 << 17]byte var x4932 [1 << 17]byte var x4933 [1 << 17]byte var x4934 [1 << 17]byte var x4935 [1 << 17]byte var x4936 [1 << 17]byte var x4937 [1 << 17]byte var x4938 [1 << 17]byte var x4939 [1 << 17]byte var x4940 [1 << 17]byte var x4941 [1 << 17]byte var x4942 [1 << 17]byte var x4943 [1 << 17]byte var x4944 [1 << 17]byte var x4945 [1 << 17]byte var x4946 [1 << 17]byte var x4947 [1 << 17]byte var x4948 [1 << 17]byte var x4949 [1 << 17]byte var x4950 [1 << 17]byte var x4951 [1 << 17]byte var x4952 [1 << 17]byte var x4953 [1 << 17]byte var x4954 [1 << 17]byte var x4955 [1 << 17]byte var x4956 [1 << 17]byte var x4957 [1 << 17]byte var x4958 [1 << 17]byte var x4959 [1 << 17]byte var x4960 [1 << 17]byte var x4961 [1 << 17]byte var x4962 [1 << 17]byte var x4963 [1 << 17]byte var x4964 [1 << 17]byte var x4965 [1 << 17]byte var x4966 [1 << 17]byte var x4967 [1 << 17]byte var x4968 [1 << 17]byte var x4969 [1 << 17]byte var x4970 [1 << 17]byte var x4971 [1 << 17]byte var x4972 [1 << 17]byte var x4973 [1 << 17]byte var x4974 [1 << 17]byte var x4975 [1 << 17]byte var x4976 [1 << 17]byte var x4977 [1 << 17]byte var x4978 [1 << 17]byte var x4979 [1 << 17]byte var x4980 [1 << 17]byte var x4981 [1 << 17]byte var x4982 [1 << 17]byte var x4983 [1 << 17]byte var x4984 [1 << 17]byte var x4985 [1 << 17]byte var x4986 [1 << 17]byte var x4987 [1 << 17]byte var x4988 [1 << 17]byte var x4989 [1 << 17]byte var x4990 [1 << 17]byte var x4991 [1 << 17]byte var x4992 [1 << 17]byte var x4993 [1 << 17]byte var x4994 [1 << 17]byte var x4995 [1 << 17]byte var x4996 [1 << 17]byte var x4997 [1 << 17]byte var x4998 [1 << 17]byte var x4999 [1 << 17]byte var x5000 [1 << 17]byte var x5001 [1 << 17]byte var x5002 [1 << 17]byte var x5003 [1 << 17]byte var x5004 [1 << 17]byte var x5005 [1 << 17]byte var x5006 [1 << 17]byte var x5007 [1 << 17]byte var x5008 [1 << 17]byte var x5009 [1 << 17]byte var x5010 [1 << 17]byte var x5011 [1 << 17]byte var x5012 [1 << 17]byte var x5013 [1 << 17]byte var x5014 [1 << 17]byte var x5015 [1 << 17]byte var x5016 [1 << 17]byte var x5017 [1 << 17]byte var x5018 [1 << 17]byte var x5019 [1 << 17]byte var x5020 [1 << 17]byte var x5021 [1 << 17]byte var x5022 [1 << 17]byte var x5023 [1 << 17]byte var x5024 [1 << 17]byte var x5025 [1 << 17]byte var x5026 [1 << 17]byte var x5027 [1 << 17]byte var x5028 [1 << 17]byte var x5029 [1 << 17]byte var x5030 [1 << 17]byte var x5031 [1 << 17]byte var x5032 [1 << 17]byte var x5033 [1 << 17]byte var x5034 [1 << 17]byte var x5035 [1 << 17]byte var x5036 [1 << 17]byte var x5037 [1 << 17]byte var x5038 [1 << 17]byte var x5039 [1 << 17]byte var x5040 [1 << 17]byte var x5041 [1 << 17]byte var x5042 [1 << 17]byte var x5043 [1 << 17]byte var x5044 [1 << 17]byte var x5045 [1 << 17]byte var x5046 [1 << 17]byte var x5047 [1 << 17]byte var x5048 [1 << 17]byte var x5049 [1 << 17]byte var x5050 [1 << 17]byte var x5051 [1 << 17]byte var x5052 [1 << 17]byte var x5053 [1 << 17]byte var x5054 [1 << 17]byte var x5055 [1 << 17]byte var x5056 [1 << 17]byte var x5057 [1 << 17]byte var x5058 [1 << 17]byte var x5059 [1 << 17]byte var x5060 [1 << 17]byte var x5061 [1 << 17]byte var x5062 [1 << 17]byte var x5063 [1 << 17]byte var x5064 [1 << 17]byte var x5065 [1 << 17]byte var x5066 [1 << 17]byte var x5067 [1 << 17]byte var x5068 [1 << 17]byte var x5069 [1 << 17]byte var x5070 [1 << 17]byte var x5071 [1 << 17]byte var x5072 [1 << 17]byte var x5073 [1 << 17]byte var x5074 [1 << 17]byte var x5075 [1 << 17]byte var x5076 [1 << 17]byte var x5077 [1 << 17]byte var x5078 [1 << 17]byte var x5079 [1 << 17]byte var x5080 [1 << 17]byte var x5081 [1 << 17]byte var x5082 [1 << 17]byte var x5083 [1 << 17]byte var x5084 [1 << 17]byte var x5085 [1 << 17]byte var x5086 [1 << 17]byte var x5087 [1 << 17]byte var x5088 [1 << 17]byte var x5089 [1 << 17]byte var x5090 [1 << 17]byte var x5091 [1 << 17]byte var x5092 [1 << 17]byte var x5093 [1 << 17]byte var x5094 [1 << 17]byte var x5095 [1 << 17]byte var x5096 [1 << 17]byte var x5097 [1 << 17]byte var x5098 [1 << 17]byte var x5099 [1 << 17]byte var x5100 [1 << 17]byte var x5101 [1 << 17]byte var x5102 [1 << 17]byte var x5103 [1 << 17]byte var x5104 [1 << 17]byte var x5105 [1 << 17]byte var x5106 [1 << 17]byte var x5107 [1 << 17]byte var x5108 [1 << 17]byte var x5109 [1 << 17]byte var x5110 [1 << 17]byte var x5111 [1 << 17]byte var x5112 [1 << 17]byte var x5113 [1 << 17]byte var x5114 [1 << 17]byte var x5115 [1 << 17]byte var x5116 [1 << 17]byte var x5117 [1 << 17]byte var x5118 [1 << 17]byte var x5119 [1 << 17]byte var x5120 [1 << 17]byte var x5121 [1 << 17]byte var x5122 [1 << 17]byte var x5123 [1 << 17]byte var x5124 [1 << 17]byte var x5125 [1 << 17]byte var x5126 [1 << 17]byte var x5127 [1 << 17]byte var x5128 [1 << 17]byte var x5129 [1 << 17]byte var x5130 [1 << 17]byte var x5131 [1 << 17]byte var x5132 [1 << 17]byte var x5133 [1 << 17]byte var x5134 [1 << 17]byte var x5135 [1 << 17]byte var x5136 [1 << 17]byte var x5137 [1 << 17]byte var x5138 [1 << 17]byte var x5139 [1 << 17]byte var x5140 [1 << 17]byte var x5141 [1 << 17]byte var x5142 [1 << 17]byte var x5143 [1 << 17]byte var x5144 [1 << 17]byte var x5145 [1 << 17]byte var x5146 [1 << 17]byte var x5147 [1 << 17]byte var x5148 [1 << 17]byte var x5149 [1 << 17]byte var x5150 [1 << 17]byte var x5151 [1 << 17]byte var x5152 [1 << 17]byte var x5153 [1 << 17]byte var x5154 [1 << 17]byte var x5155 [1 << 17]byte var x5156 [1 << 17]byte var x5157 [1 << 17]byte var x5158 [1 << 17]byte var x5159 [1 << 17]byte var x5160 [1 << 17]byte var x5161 [1 << 17]byte var x5162 [1 << 17]byte var x5163 [1 << 17]byte var x5164 [1 << 17]byte var x5165 [1 << 17]byte var x5166 [1 << 17]byte var x5167 [1 << 17]byte var x5168 [1 << 17]byte var x5169 [1 << 17]byte var x5170 [1 << 17]byte var x5171 [1 << 17]byte var x5172 [1 << 17]byte var x5173 [1 << 17]byte var x5174 [1 << 17]byte var x5175 [1 << 17]byte var x5176 [1 << 17]byte var x5177 [1 << 17]byte var x5178 [1 << 17]byte var x5179 [1 << 17]byte var x5180 [1 << 17]byte var x5181 [1 << 17]byte var x5182 [1 << 17]byte var x5183 [1 << 17]byte var x5184 [1 << 17]byte var x5185 [1 << 17]byte var x5186 [1 << 17]byte var x5187 [1 << 17]byte var x5188 [1 << 17]byte var x5189 [1 << 17]byte var x5190 [1 << 17]byte var x5191 [1 << 17]byte var x5192 [1 << 17]byte var x5193 [1 << 17]byte var x5194 [1 << 17]byte var x5195 [1 << 17]byte var x5196 [1 << 17]byte var x5197 [1 << 17]byte var x5198 [1 << 17]byte var x5199 [1 << 17]byte var x5200 [1 << 17]byte var x5201 [1 << 17]byte var x5202 [1 << 17]byte var x5203 [1 << 17]byte var x5204 [1 << 17]byte var x5205 [1 << 17]byte var x5206 [1 << 17]byte var x5207 [1 << 17]byte var x5208 [1 << 17]byte var x5209 [1 << 17]byte var x5210 [1 << 17]byte var x5211 [1 << 17]byte var x5212 [1 << 17]byte var x5213 [1 << 17]byte var x5214 [1 << 17]byte var x5215 [1 << 17]byte var x5216 [1 << 17]byte var x5217 [1 << 17]byte var x5218 [1 << 17]byte var x5219 [1 << 17]byte var x5220 [1 << 17]byte var x5221 [1 << 17]byte var x5222 [1 << 17]byte var x5223 [1 << 17]byte var x5224 [1 << 17]byte var x5225 [1 << 17]byte var x5226 [1 << 17]byte var x5227 [1 << 17]byte var x5228 [1 << 17]byte var x5229 [1 << 17]byte var x5230 [1 << 17]byte var x5231 [1 << 17]byte var x5232 [1 << 17]byte var x5233 [1 << 17]byte var x5234 [1 << 17]byte var x5235 [1 << 17]byte var x5236 [1 << 17]byte var x5237 [1 << 17]byte var x5238 [1 << 17]byte var x5239 [1 << 17]byte var x5240 [1 << 17]byte var x5241 [1 << 17]byte var x5242 [1 << 17]byte var x5243 [1 << 17]byte var x5244 [1 << 17]byte var x5245 [1 << 17]byte var x5246 [1 << 17]byte var x5247 [1 << 17]byte var x5248 [1 << 17]byte var x5249 [1 << 17]byte var x5250 [1 << 17]byte var x5251 [1 << 17]byte var x5252 [1 << 17]byte var x5253 [1 << 17]byte var x5254 [1 << 17]byte var x5255 [1 << 17]byte var x5256 [1 << 17]byte var x5257 [1 << 17]byte var x5258 [1 << 17]byte var x5259 [1 << 17]byte var x5260 [1 << 17]byte var x5261 [1 << 17]byte var x5262 [1 << 17]byte var x5263 [1 << 17]byte var x5264 [1 << 17]byte var x5265 [1 << 17]byte var x5266 [1 << 17]byte var x5267 [1 << 17]byte var x5268 [1 << 17]byte var x5269 [1 << 17]byte var x5270 [1 << 17]byte var x5271 [1 << 17]byte var x5272 [1 << 17]byte var x5273 [1 << 17]byte var x5274 [1 << 17]byte var x5275 [1 << 17]byte var x5276 [1 << 17]byte var x5277 [1 << 17]byte var x5278 [1 << 17]byte var x5279 [1 << 17]byte var x5280 [1 << 17]byte var x5281 [1 << 17]byte var x5282 [1 << 17]byte var x5283 [1 << 17]byte var x5284 [1 << 17]byte var x5285 [1 << 17]byte var x5286 [1 << 17]byte var x5287 [1 << 17]byte var x5288 [1 << 17]byte var x5289 [1 << 17]byte var x5290 [1 << 17]byte var x5291 [1 << 17]byte var x5292 [1 << 17]byte var x5293 [1 << 17]byte var x5294 [1 << 17]byte var x5295 [1 << 17]byte var x5296 [1 << 17]byte var x5297 [1 << 17]byte var x5298 [1 << 17]byte var x5299 [1 << 17]byte var x5300 [1 << 17]byte var x5301 [1 << 17]byte var x5302 [1 << 17]byte var x5303 [1 << 17]byte var x5304 [1 << 17]byte var x5305 [1 << 17]byte var x5306 [1 << 17]byte var x5307 [1 << 17]byte var x5308 [1 << 17]byte var x5309 [1 << 17]byte var x5310 [1 << 17]byte var x5311 [1 << 17]byte var x5312 [1 << 17]byte var x5313 [1 << 17]byte var x5314 [1 << 17]byte var x5315 [1 << 17]byte var x5316 [1 << 17]byte var x5317 [1 << 17]byte var x5318 [1 << 17]byte var x5319 [1 << 17]byte var x5320 [1 << 17]byte var x5321 [1 << 17]byte var x5322 [1 << 17]byte var x5323 [1 << 17]byte var x5324 [1 << 17]byte var x5325 [1 << 17]byte var x5326 [1 << 17]byte var x5327 [1 << 17]byte var x5328 [1 << 17]byte var x5329 [1 << 17]byte var x5330 [1 << 17]byte var x5331 [1 << 17]byte var x5332 [1 << 17]byte var x5333 [1 << 17]byte var x5334 [1 << 17]byte var x5335 [1 << 17]byte var x5336 [1 << 17]byte var x5337 [1 << 17]byte var x5338 [1 << 17]byte var x5339 [1 << 17]byte var x5340 [1 << 17]byte var x5341 [1 << 17]byte var x5342 [1 << 17]byte var x5343 [1 << 17]byte var x5344 [1 << 17]byte var x5345 [1 << 17]byte var x5346 [1 << 17]byte var x5347 [1 << 17]byte var x5348 [1 << 17]byte var x5349 [1 << 17]byte var x5350 [1 << 17]byte var x5351 [1 << 17]byte var x5352 [1 << 17]byte var x5353 [1 << 17]byte var x5354 [1 << 17]byte var x5355 [1 << 17]byte var x5356 [1 << 17]byte var x5357 [1 << 17]byte var x5358 [1 << 17]byte var x5359 [1 << 17]byte var x5360 [1 << 17]byte var x5361 [1 << 17]byte var x5362 [1 << 17]byte var x5363 [1 << 17]byte var x5364 [1 << 17]byte var x5365 [1 << 17]byte var x5366 [1 << 17]byte var x5367 [1 << 17]byte var x5368 [1 << 17]byte var x5369 [1 << 17]byte var x5370 [1 << 17]byte var x5371 [1 << 17]byte var x5372 [1 << 17]byte var x5373 [1 << 17]byte var x5374 [1 << 17]byte var x5375 [1 << 17]byte var x5376 [1 << 17]byte var x5377 [1 << 17]byte var x5378 [1 << 17]byte var x5379 [1 << 17]byte var x5380 [1 << 17]byte var x5381 [1 << 17]byte var x5382 [1 << 17]byte var x5383 [1 << 17]byte var x5384 [1 << 17]byte var x5385 [1 << 17]byte var x5386 [1 << 17]byte var x5387 [1 << 17]byte var x5388 [1 << 17]byte var x5389 [1 << 17]byte var x5390 [1 << 17]byte var x5391 [1 << 17]byte var x5392 [1 << 17]byte var x5393 [1 << 17]byte var x5394 [1 << 17]byte var x5395 [1 << 17]byte var x5396 [1 << 17]byte var x5397 [1 << 17]byte var x5398 [1 << 17]byte var x5399 [1 << 17]byte var x5400 [1 << 17]byte var x5401 [1 << 17]byte var x5402 [1 << 17]byte var x5403 [1 << 17]byte var x5404 [1 << 17]byte var x5405 [1 << 17]byte var x5406 [1 << 17]byte var x5407 [1 << 17]byte var x5408 [1 << 17]byte var x5409 [1 << 17]byte var x5410 [1 << 17]byte var x5411 [1 << 17]byte var x5412 [1 << 17]byte var x5413 [1 << 17]byte var x5414 [1 << 17]byte var x5415 [1 << 17]byte var x5416 [1 << 17]byte var x5417 [1 << 17]byte var x5418 [1 << 17]byte var x5419 [1 << 17]byte var x5420 [1 << 17]byte var x5421 [1 << 17]byte var x5422 [1 << 17]byte var x5423 [1 << 17]byte var x5424 [1 << 17]byte var x5425 [1 << 17]byte var x5426 [1 << 17]byte var x5427 [1 << 17]byte var x5428 [1 << 17]byte var x5429 [1 << 17]byte var x5430 [1 << 17]byte var x5431 [1 << 17]byte var x5432 [1 << 17]byte var x5433 [1 << 17]byte var x5434 [1 << 17]byte var x5435 [1 << 17]byte var x5436 [1 << 17]byte var x5437 [1 << 17]byte var x5438 [1 << 17]byte var x5439 [1 << 17]byte var x5440 [1 << 17]byte var x5441 [1 << 17]byte var x5442 [1 << 17]byte var x5443 [1 << 17]byte var x5444 [1 << 17]byte var x5445 [1 << 17]byte var x5446 [1 << 17]byte var x5447 [1 << 17]byte var x5448 [1 << 17]byte var x5449 [1 << 17]byte var x5450 [1 << 17]byte var x5451 [1 << 17]byte var x5452 [1 << 17]byte var x5453 [1 << 17]byte var x5454 [1 << 17]byte var x5455 [1 << 17]byte var x5456 [1 << 17]byte var x5457 [1 << 17]byte var x5458 [1 << 17]byte var x5459 [1 << 17]byte var x5460 [1 << 17]byte var x5461 [1 << 17]byte var x5462 [1 << 17]byte var x5463 [1 << 17]byte var x5464 [1 << 17]byte var x5465 [1 << 17]byte var x5466 [1 << 17]byte var x5467 [1 << 17]byte var x5468 [1 << 17]byte var x5469 [1 << 17]byte var x5470 [1 << 17]byte var x5471 [1 << 17]byte var x5472 [1 << 17]byte var x5473 [1 << 17]byte var x5474 [1 << 17]byte var x5475 [1 << 17]byte var x5476 [1 << 17]byte var x5477 [1 << 17]byte var x5478 [1 << 17]byte var x5479 [1 << 17]byte var x5480 [1 << 17]byte var x5481 [1 << 17]byte var x5482 [1 << 17]byte var x5483 [1 << 17]byte var x5484 [1 << 17]byte var x5485 [1 << 17]byte var x5486 [1 << 17]byte var x5487 [1 << 17]byte var x5488 [1 << 17]byte var x5489 [1 << 17]byte var x5490 [1 << 17]byte var x5491 [1 << 17]byte var x5492 [1 << 17]byte var x5493 [1 << 17]byte var x5494 [1 << 17]byte var x5495 [1 << 17]byte var x5496 [1 << 17]byte var x5497 [1 << 17]byte var x5498 [1 << 17]byte var x5499 [1 << 17]byte var x5500 [1 << 17]byte var x5501 [1 << 17]byte var x5502 [1 << 17]byte var x5503 [1 << 17]byte var x5504 [1 << 17]byte var x5505 [1 << 17]byte var x5506 [1 << 17]byte var x5507 [1 << 17]byte var x5508 [1 << 17]byte var x5509 [1 << 17]byte var x5510 [1 << 17]byte var x5511 [1 << 17]byte var x5512 [1 << 17]byte var x5513 [1 << 17]byte var x5514 [1 << 17]byte var x5515 [1 << 17]byte var x5516 [1 << 17]byte var x5517 [1 << 17]byte var x5518 [1 << 17]byte var x5519 [1 << 17]byte var x5520 [1 << 17]byte var x5521 [1 << 17]byte var x5522 [1 << 17]byte var x5523 [1 << 17]byte var x5524 [1 << 17]byte var x5525 [1 << 17]byte var x5526 [1 << 17]byte var x5527 [1 << 17]byte var x5528 [1 << 17]byte var x5529 [1 << 17]byte var x5530 [1 << 17]byte var x5531 [1 << 17]byte var x5532 [1 << 17]byte var x5533 [1 << 17]byte var x5534 [1 << 17]byte var x5535 [1 << 17]byte var x5536 [1 << 17]byte var x5537 [1 << 17]byte var x5538 [1 << 17]byte var x5539 [1 << 17]byte var x5540 [1 << 17]byte var x5541 [1 << 17]byte var x5542 [1 << 17]byte var x5543 [1 << 17]byte var x5544 [1 << 17]byte var x5545 [1 << 17]byte var x5546 [1 << 17]byte var x5547 [1 << 17]byte var x5548 [1 << 17]byte var x5549 [1 << 17]byte var x5550 [1 << 17]byte var x5551 [1 << 17]byte var x5552 [1 << 17]byte var x5553 [1 << 17]byte var x5554 [1 << 17]byte var x5555 [1 << 17]byte var x5556 [1 << 17]byte var x5557 [1 << 17]byte var x5558 [1 << 17]byte var x5559 [1 << 17]byte var x5560 [1 << 17]byte var x5561 [1 << 17]byte var x5562 [1 << 17]byte var x5563 [1 << 17]byte var x5564 [1 << 17]byte var x5565 [1 << 17]byte var x5566 [1 << 17]byte var x5567 [1 << 17]byte var x5568 [1 << 17]byte var x5569 [1 << 17]byte var x5570 [1 << 17]byte var x5571 [1 << 17]byte var x5572 [1 << 17]byte var x5573 [1 << 17]byte var x5574 [1 << 17]byte var x5575 [1 << 17]byte var x5576 [1 << 17]byte var x5577 [1 << 17]byte var x5578 [1 << 17]byte var x5579 [1 << 17]byte var x5580 [1 << 17]byte var x5581 [1 << 17]byte var x5582 [1 << 17]byte var x5583 [1 << 17]byte var x5584 [1 << 17]byte var x5585 [1 << 17]byte var x5586 [1 << 17]byte var x5587 [1 << 17]byte var x5588 [1 << 17]byte var x5589 [1 << 17]byte var x5590 [1 << 17]byte var x5591 [1 << 17]byte var x5592 [1 << 17]byte var x5593 [1 << 17]byte var x5594 [1 << 17]byte var x5595 [1 << 17]byte var x5596 [1 << 17]byte var x5597 [1 << 17]byte var x5598 [1 << 17]byte var x5599 [1 << 17]byte var x5600 [1 << 17]byte var x5601 [1 << 17]byte var x5602 [1 << 17]byte var x5603 [1 << 17]byte var x5604 [1 << 17]byte var x5605 [1 << 17]byte var x5606 [1 << 17]byte var x5607 [1 << 17]byte var x5608 [1 << 17]byte var x5609 [1 << 17]byte var x5610 [1 << 17]byte var x5611 [1 << 17]byte var x5612 [1 << 17]byte var x5613 [1 << 17]byte var x5614 [1 << 17]byte var x5615 [1 << 17]byte var x5616 [1 << 17]byte var x5617 [1 << 17]byte var x5618 [1 << 17]byte var x5619 [1 << 17]byte var x5620 [1 << 17]byte var x5621 [1 << 17]byte var x5622 [1 << 17]byte var x5623 [1 << 17]byte var x5624 [1 << 17]byte var x5625 [1 << 17]byte var x5626 [1 << 17]byte var x5627 [1 << 17]byte var x5628 [1 << 17]byte var x5629 [1 << 17]byte var x5630 [1 << 17]byte var x5631 [1 << 17]byte var x5632 [1 << 17]byte var x5633 [1 << 17]byte var x5634 [1 << 17]byte var x5635 [1 << 17]byte var x5636 [1 << 17]byte var x5637 [1 << 17]byte var x5638 [1 << 17]byte var x5639 [1 << 17]byte var x5640 [1 << 17]byte var x5641 [1 << 17]byte var x5642 [1 << 17]byte var x5643 [1 << 17]byte var x5644 [1 << 17]byte var x5645 [1 << 17]byte var x5646 [1 << 17]byte var x5647 [1 << 17]byte var x5648 [1 << 17]byte var x5649 [1 << 17]byte var x5650 [1 << 17]byte var x5651 [1 << 17]byte var x5652 [1 << 17]byte var x5653 [1 << 17]byte var x5654 [1 << 17]byte var x5655 [1 << 17]byte var x5656 [1 << 17]byte var x5657 [1 << 17]byte var x5658 [1 << 17]byte var x5659 [1 << 17]byte var x5660 [1 << 17]byte var x5661 [1 << 17]byte var x5662 [1 << 17]byte var x5663 [1 << 17]byte var x5664 [1 << 17]byte var x5665 [1 << 17]byte var x5666 [1 << 17]byte var x5667 [1 << 17]byte var x5668 [1 << 17]byte var x5669 [1 << 17]byte var x5670 [1 << 17]byte var x5671 [1 << 17]byte var x5672 [1 << 17]byte var x5673 [1 << 17]byte var x5674 [1 << 17]byte var x5675 [1 << 17]byte var x5676 [1 << 17]byte var x5677 [1 << 17]byte var x5678 [1 << 17]byte var x5679 [1 << 17]byte var x5680 [1 << 17]byte var x5681 [1 << 17]byte var x5682 [1 << 17]byte var x5683 [1 << 17]byte var x5684 [1 << 17]byte var x5685 [1 << 17]byte var x5686 [1 << 17]byte var x5687 [1 << 17]byte var x5688 [1 << 17]byte var x5689 [1 << 17]byte var x5690 [1 << 17]byte var x5691 [1 << 17]byte var x5692 [1 << 17]byte var x5693 [1 << 17]byte var x5694 [1 << 17]byte var x5695 [1 << 17]byte var x5696 [1 << 17]byte var x5697 [1 << 17]byte var x5698 [1 << 17]byte var x5699 [1 << 17]byte var x5700 [1 << 17]byte var x5701 [1 << 17]byte var x5702 [1 << 17]byte var x5703 [1 << 17]byte var x5704 [1 << 17]byte var x5705 [1 << 17]byte var x5706 [1 << 17]byte var x5707 [1 << 17]byte var x5708 [1 << 17]byte var x5709 [1 << 17]byte var x5710 [1 << 17]byte var x5711 [1 << 17]byte var x5712 [1 << 17]byte var x5713 [1 << 17]byte var x5714 [1 << 17]byte var x5715 [1 << 17]byte var x5716 [1 << 17]byte var x5717 [1 << 17]byte var x5718 [1 << 17]byte var x5719 [1 << 17]byte var x5720 [1 << 17]byte var x5721 [1 << 17]byte var x5722 [1 << 17]byte var x5723 [1 << 17]byte var x5724 [1 << 17]byte var x5725 [1 << 17]byte var x5726 [1 << 17]byte var x5727 [1 << 17]byte var x5728 [1 << 17]byte var x5729 [1 << 17]byte var x5730 [1 << 17]byte var x5731 [1 << 17]byte var x5732 [1 << 17]byte var x5733 [1 << 17]byte var x5734 [1 << 17]byte var x5735 [1 << 17]byte var x5736 [1 << 17]byte var x5737 [1 << 17]byte var x5738 [1 << 17]byte var x5739 [1 << 17]byte var x5740 [1 << 17]byte var x5741 [1 << 17]byte var x5742 [1 << 17]byte var x5743 [1 << 17]byte var x5744 [1 << 17]byte var x5745 [1 << 17]byte var x5746 [1 << 17]byte var x5747 [1 << 17]byte var x5748 [1 << 17]byte var x5749 [1 << 17]byte var x5750 [1 << 17]byte var x5751 [1 << 17]byte var x5752 [1 << 17]byte var x5753 [1 << 17]byte var x5754 [1 << 17]byte var x5755 [1 << 17]byte var x5756 [1 << 17]byte var x5757 [1 << 17]byte var x5758 [1 << 17]byte var x5759 [1 << 17]byte var x5760 [1 << 17]byte var x5761 [1 << 17]byte var x5762 [1 << 17]byte var x5763 [1 << 17]byte var x5764 [1 << 17]byte var x5765 [1 << 17]byte var x5766 [1 << 17]byte var x5767 [1 << 17]byte var x5768 [1 << 17]byte var x5769 [1 << 17]byte var x5770 [1 << 17]byte var x5771 [1 << 17]byte var x5772 [1 << 17]byte var x5773 [1 << 17]byte var x5774 [1 << 17]byte var x5775 [1 << 17]byte var x5776 [1 << 17]byte var x5777 [1 << 17]byte var x5778 [1 << 17]byte var x5779 [1 << 17]byte var x5780 [1 << 17]byte var x5781 [1 << 17]byte var x5782 [1 << 17]byte var x5783 [1 << 17]byte var x5784 [1 << 17]byte var x5785 [1 << 17]byte var x5786 [1 << 17]byte var x5787 [1 << 17]byte var x5788 [1 << 17]byte var x5789 [1 << 17]byte var x5790 [1 << 17]byte var x5791 [1 << 17]byte var x5792 [1 << 17]byte var x5793 [1 << 17]byte var x5794 [1 << 17]byte var x5795 [1 << 17]byte var x5796 [1 << 17]byte var x5797 [1 << 17]byte var x5798 [1 << 17]byte var x5799 [1 << 17]byte var x5800 [1 << 17]byte var x5801 [1 << 17]byte var x5802 [1 << 17]byte var x5803 [1 << 17]byte var x5804 [1 << 17]byte var x5805 [1 << 17]byte var x5806 [1 << 17]byte var x5807 [1 << 17]byte var x5808 [1 << 17]byte var x5809 [1 << 17]byte var x5810 [1 << 17]byte var x5811 [1 << 17]byte var x5812 [1 << 17]byte var x5813 [1 << 17]byte var x5814 [1 << 17]byte var x5815 [1 << 17]byte var x5816 [1 << 17]byte var x5817 [1 << 17]byte var x5818 [1 << 17]byte var x5819 [1 << 17]byte var x5820 [1 << 17]byte var x5821 [1 << 17]byte var x5822 [1 << 17]byte var x5823 [1 << 17]byte var x5824 [1 << 17]byte var x5825 [1 << 17]byte var x5826 [1 << 17]byte var x5827 [1 << 17]byte var x5828 [1 << 17]byte var x5829 [1 << 17]byte var x5830 [1 << 17]byte var x5831 [1 << 17]byte var x5832 [1 << 17]byte var x5833 [1 << 17]byte var x5834 [1 << 17]byte var x5835 [1 << 17]byte var x5836 [1 << 17]byte var x5837 [1 << 17]byte var x5838 [1 << 17]byte var x5839 [1 << 17]byte var x5840 [1 << 17]byte var x5841 [1 << 17]byte var x5842 [1 << 17]byte var x5843 [1 << 17]byte var x5844 [1 << 17]byte var x5845 [1 << 17]byte var x5846 [1 << 17]byte var x5847 [1 << 17]byte var x5848 [1 << 17]byte var x5849 [1 << 17]byte var x5850 [1 << 17]byte var x5851 [1 << 17]byte var x5852 [1 << 17]byte var x5853 [1 << 17]byte var x5854 [1 << 17]byte var x5855 [1 << 17]byte var x5856 [1 << 17]byte var x5857 [1 << 17]byte var x5858 [1 << 17]byte var x5859 [1 << 17]byte var x5860 [1 << 17]byte var x5861 [1 << 17]byte var x5862 [1 << 17]byte var x5863 [1 << 17]byte var x5864 [1 << 17]byte var x5865 [1 << 17]byte var x5866 [1 << 17]byte var x5867 [1 << 17]byte var x5868 [1 << 17]byte var x5869 [1 << 17]byte var x5870 [1 << 17]byte var x5871 [1 << 17]byte var x5872 [1 << 17]byte var x5873 [1 << 17]byte var x5874 [1 << 17]byte var x5875 [1 << 17]byte var x5876 [1 << 17]byte var x5877 [1 << 17]byte var x5878 [1 << 17]byte var x5879 [1 << 17]byte var x5880 [1 << 17]byte var x5881 [1 << 17]byte var x5882 [1 << 17]byte var x5883 [1 << 17]byte var x5884 [1 << 17]byte var x5885 [1 << 17]byte var x5886 [1 << 17]byte var x5887 [1 << 17]byte var x5888 [1 << 17]byte var x5889 [1 << 17]byte var x5890 [1 << 17]byte var x5891 [1 << 17]byte var x5892 [1 << 17]byte var x5893 [1 << 17]byte var x5894 [1 << 17]byte var x5895 [1 << 17]byte var x5896 [1 << 17]byte var x5897 [1 << 17]byte var x5898 [1 << 17]byte var x5899 [1 << 17]byte var x5900 [1 << 17]byte var x5901 [1 << 17]byte var x5902 [1 << 17]byte var x5903 [1 << 17]byte var x5904 [1 << 17]byte var x5905 [1 << 17]byte var x5906 [1 << 17]byte var x5907 [1 << 17]byte var x5908 [1 << 17]byte var x5909 [1 << 17]byte var x5910 [1 << 17]byte var x5911 [1 << 17]byte var x5912 [1 << 17]byte var x5913 [1 << 17]byte var x5914 [1 << 17]byte var x5915 [1 << 17]byte var x5916 [1 << 17]byte var x5917 [1 << 17]byte var x5918 [1 << 17]byte var x5919 [1 << 17]byte var x5920 [1 << 17]byte var x5921 [1 << 17]byte var x5922 [1 << 17]byte var x5923 [1 << 17]byte var x5924 [1 << 17]byte var x5925 [1 << 17]byte var x5926 [1 << 17]byte var x5927 [1 << 17]byte var x5928 [1 << 17]byte var x5929 [1 << 17]byte var x5930 [1 << 17]byte var x5931 [1 << 17]byte var x5932 [1 << 17]byte var x5933 [1 << 17]byte var x5934 [1 << 17]byte var x5935 [1 << 17]byte var x5936 [1 << 17]byte var x5937 [1 << 17]byte var x5938 [1 << 17]byte var x5939 [1 << 17]byte var x5940 [1 << 17]byte var x5941 [1 << 17]byte var x5942 [1 << 17]byte var x5943 [1 << 17]byte var x5944 [1 << 17]byte var x5945 [1 << 17]byte var x5946 [1 << 17]byte var x5947 [1 << 17]byte var x5948 [1 << 17]byte var x5949 [1 << 17]byte var x5950 [1 << 17]byte var x5951 [1 << 17]byte var x5952 [1 << 17]byte var x5953 [1 << 17]byte var x5954 [1 << 17]byte var x5955 [1 << 17]byte var x5956 [1 << 17]byte var x5957 [1 << 17]byte var x5958 [1 << 17]byte var x5959 [1 << 17]byte var x5960 [1 << 17]byte var x5961 [1 << 17]byte var x5962 [1 << 17]byte var x5963 [1 << 17]byte var x5964 [1 << 17]byte var x5965 [1 << 17]byte var x5966 [1 << 17]byte var x5967 [1 << 17]byte var x5968 [1 << 17]byte var x5969 [1 << 17]byte var x5970 [1 << 17]byte var x5971 [1 << 17]byte var x5972 [1 << 17]byte var x5973 [1 << 17]byte var x5974 [1 << 17]byte var x5975 [1 << 17]byte var x5976 [1 << 17]byte var x5977 [1 << 17]byte var x5978 [1 << 17]byte var x5979 [1 << 17]byte var x5980 [1 << 17]byte var x5981 [1 << 17]byte var x5982 [1 << 17]byte var x5983 [1 << 17]byte var x5984 [1 << 17]byte var x5985 [1 << 17]byte var x5986 [1 << 17]byte var x5987 [1 << 17]byte var x5988 [1 << 17]byte var x5989 [1 << 17]byte var x5990 [1 << 17]byte var x5991 [1 << 17]byte var x5992 [1 << 17]byte var x5993 [1 << 17]byte var x5994 [1 << 17]byte var x5995 [1 << 17]byte var x5996 [1 << 17]byte var x5997 [1 << 17]byte var x5998 [1 << 17]byte var x5999 [1 << 17]byte var x6000 [1 << 17]byte var x6001 [1 << 17]byte var x6002 [1 << 17]byte var x6003 [1 << 17]byte var x6004 [1 << 17]byte var x6005 [1 << 17]byte var x6006 [1 << 17]byte var x6007 [1 << 17]byte var x6008 [1 << 17]byte var x6009 [1 << 17]byte var x6010 [1 << 17]byte var x6011 [1 << 17]byte var x6012 [1 << 17]byte var x6013 [1 << 17]byte var x6014 [1 << 17]byte var x6015 [1 << 17]byte var x6016 [1 << 17]byte var x6017 [1 << 17]byte var x6018 [1 << 17]byte var x6019 [1 << 17]byte var x6020 [1 << 17]byte var x6021 [1 << 17]byte var x6022 [1 << 17]byte var x6023 [1 << 17]byte var x6024 [1 << 17]byte var x6025 [1 << 17]byte var x6026 [1 << 17]byte var x6027 [1 << 17]byte var x6028 [1 << 17]byte var x6029 [1 << 17]byte var x6030 [1 << 17]byte var x6031 [1 << 17]byte var x6032 [1 << 17]byte var x6033 [1 << 17]byte var x6034 [1 << 17]byte var x6035 [1 << 17]byte var x6036 [1 << 17]byte var x6037 [1 << 17]byte var x6038 [1 << 17]byte var x6039 [1 << 17]byte var x6040 [1 << 17]byte var x6041 [1 << 17]byte var x6042 [1 << 17]byte var x6043 [1 << 17]byte var x6044 [1 << 17]byte var x6045 [1 << 17]byte var x6046 [1 << 17]byte var x6047 [1 << 17]byte var x6048 [1 << 17]byte var x6049 [1 << 17]byte var x6050 [1 << 17]byte var x6051 [1 << 17]byte var x6052 [1 << 17]byte var x6053 [1 << 17]byte var x6054 [1 << 17]byte var x6055 [1 << 17]byte var x6056 [1 << 17]byte var x6057 [1 << 17]byte var x6058 [1 << 17]byte var x6059 [1 << 17]byte var x6060 [1 << 17]byte var x6061 [1 << 17]byte var x6062 [1 << 17]byte var x6063 [1 << 17]byte var x6064 [1 << 17]byte var x6065 [1 << 17]byte var x6066 [1 << 17]byte var x6067 [1 << 17]byte var x6068 [1 << 17]byte var x6069 [1 << 17]byte var x6070 [1 << 17]byte var x6071 [1 << 17]byte var x6072 [1 << 17]byte var x6073 [1 << 17]byte var x6074 [1 << 17]byte var x6075 [1 << 17]byte var x6076 [1 << 17]byte var x6077 [1 << 17]byte var x6078 [1 << 17]byte var x6079 [1 << 17]byte var x6080 [1 << 17]byte var x6081 [1 << 17]byte var x6082 [1 << 17]byte var x6083 [1 << 17]byte var x6084 [1 << 17]byte var x6085 [1 << 17]byte var x6086 [1 << 17]byte var x6087 [1 << 17]byte var x6088 [1 << 17]byte var x6089 [1 << 17]byte var x6090 [1 << 17]byte var x6091 [1 << 17]byte var x6092 [1 << 17]byte var x6093 [1 << 17]byte var x6094 [1 << 17]byte var x6095 [1 << 17]byte var x6096 [1 << 17]byte var x6097 [1 << 17]byte var x6098 [1 << 17]byte var x6099 [1 << 17]byte var x6100 [1 << 17]byte var x6101 [1 << 17]byte var x6102 [1 << 17]byte var x6103 [1 << 17]byte var x6104 [1 << 17]byte var x6105 [1 << 17]byte var x6106 [1 << 17]byte var x6107 [1 << 17]byte var x6108 [1 << 17]byte var x6109 [1 << 17]byte var x6110 [1 << 17]byte var x6111 [1 << 17]byte var x6112 [1 << 17]byte var x6113 [1 << 17]byte var x6114 [1 << 17]byte var x6115 [1 << 17]byte var x6116 [1 << 17]byte var x6117 [1 << 17]byte var x6118 [1 << 17]byte var x6119 [1 << 17]byte var x6120 [1 << 17]byte var x6121 [1 << 17]byte var x6122 [1 << 17]byte var x6123 [1 << 17]byte var x6124 [1 << 17]byte var x6125 [1 << 17]byte var x6126 [1 << 17]byte var x6127 [1 << 17]byte var x6128 [1 << 17]byte var x6129 [1 << 17]byte var x6130 [1 << 17]byte var x6131 [1 << 17]byte var x6132 [1 << 17]byte var x6133 [1 << 17]byte var x6134 [1 << 17]byte var x6135 [1 << 17]byte var x6136 [1 << 17]byte var x6137 [1 << 17]byte var x6138 [1 << 17]byte var x6139 [1 << 17]byte var x6140 [1 << 17]byte var x6141 [1 << 17]byte var x6142 [1 << 17]byte var x6143 [1 << 17]byte var x6144 [1 << 17]byte var x6145 [1 << 17]byte var x6146 [1 << 17]byte var x6147 [1 << 17]byte var x6148 [1 << 17]byte var x6149 [1 << 17]byte var x6150 [1 << 17]byte var x6151 [1 << 17]byte var x6152 [1 << 17]byte var x6153 [1 << 17]byte var x6154 [1 << 17]byte var x6155 [1 << 17]byte var x6156 [1 << 17]byte var x6157 [1 << 17]byte var x6158 [1 << 17]byte var x6159 [1 << 17]byte var x6160 [1 << 17]byte var x6161 [1 << 17]byte var x6162 [1 << 17]byte var x6163 [1 << 17]byte var x6164 [1 << 17]byte var x6165 [1 << 17]byte var x6166 [1 << 17]byte var x6167 [1 << 17]byte var x6168 [1 << 17]byte var x6169 [1 << 17]byte var x6170 [1 << 17]byte var x6171 [1 << 17]byte var x6172 [1 << 17]byte var x6173 [1 << 17]byte var x6174 [1 << 17]byte var x6175 [1 << 17]byte var x6176 [1 << 17]byte var x6177 [1 << 17]byte var x6178 [1 << 17]byte var x6179 [1 << 17]byte var x6180 [1 << 17]byte var x6181 [1 << 17]byte var x6182 [1 << 17]byte var x6183 [1 << 17]byte var x6184 [1 << 17]byte var x6185 [1 << 17]byte var x6186 [1 << 17]byte var x6187 [1 << 17]byte var x6188 [1 << 17]byte var x6189 [1 << 17]byte var x6190 [1 << 17]byte var x6191 [1 << 17]byte var x6192 [1 << 17]byte var x6193 [1 << 17]byte var x6194 [1 << 17]byte var x6195 [1 << 17]byte var x6196 [1 << 17]byte var x6197 [1 << 17]byte var x6198 [1 << 17]byte var x6199 [1 << 17]byte var x6200 [1 << 17]byte var x6201 [1 << 17]byte var x6202 [1 << 17]byte var x6203 [1 << 17]byte var x6204 [1 << 17]byte var x6205 [1 << 17]byte var x6206 [1 << 17]byte var x6207 [1 << 17]byte var x6208 [1 << 17]byte var x6209 [1 << 17]byte var x6210 [1 << 17]byte var x6211 [1 << 17]byte var x6212 [1 << 17]byte var x6213 [1 << 17]byte var x6214 [1 << 17]byte var x6215 [1 << 17]byte var x6216 [1 << 17]byte var x6217 [1 << 17]byte var x6218 [1 << 17]byte var x6219 [1 << 17]byte var x6220 [1 << 17]byte var x6221 [1 << 17]byte var x6222 [1 << 17]byte var x6223 [1 << 17]byte var x6224 [1 << 17]byte var x6225 [1 << 17]byte var x6226 [1 << 17]byte var x6227 [1 << 17]byte var x6228 [1 << 17]byte var x6229 [1 << 17]byte var x6230 [1 << 17]byte var x6231 [1 << 17]byte var x6232 [1 << 17]byte var x6233 [1 << 17]byte var x6234 [1 << 17]byte var x6235 [1 << 17]byte var x6236 [1 << 17]byte var x6237 [1 << 17]byte var x6238 [1 << 17]byte var x6239 [1 << 17]byte var x6240 [1 << 17]byte var x6241 [1 << 17]byte var x6242 [1 << 17]byte var x6243 [1 << 17]byte var x6244 [1 << 17]byte var x6245 [1 << 17]byte var x6246 [1 << 17]byte var x6247 [1 << 17]byte var x6248 [1 << 17]byte var x6249 [1 << 17]byte var x6250 [1 << 17]byte var x6251 [1 << 17]byte var x6252 [1 << 17]byte var x6253 [1 << 17]byte var x6254 [1 << 17]byte var x6255 [1 << 17]byte var x6256 [1 << 17]byte var x6257 [1 << 17]byte var x6258 [1 << 17]byte var x6259 [1 << 17]byte var x6260 [1 << 17]byte var x6261 [1 << 17]byte var x6262 [1 << 17]byte var x6263 [1 << 17]byte var x6264 [1 << 17]byte var x6265 [1 << 17]byte var x6266 [1 << 17]byte var x6267 [1 << 17]byte var x6268 [1 << 17]byte var x6269 [1 << 17]byte var x6270 [1 << 17]byte var x6271 [1 << 17]byte var x6272 [1 << 17]byte var x6273 [1 << 17]byte var x6274 [1 << 17]byte var x6275 [1 << 17]byte var x6276 [1 << 17]byte var x6277 [1 << 17]byte var x6278 [1 << 17]byte var x6279 [1 << 17]byte var x6280 [1 << 17]byte var x6281 [1 << 17]byte var x6282 [1 << 17]byte var x6283 [1 << 17]byte var x6284 [1 << 17]byte var x6285 [1 << 17]byte var x6286 [1 << 17]byte var x6287 [1 << 17]byte var x6288 [1 << 17]byte var x6289 [1 << 17]byte var x6290 [1 << 17]byte var x6291 [1 << 17]byte var x6292 [1 << 17]byte var x6293 [1 << 17]byte var x6294 [1 << 17]byte var x6295 [1 << 17]byte var x6296 [1 << 17]byte var x6297 [1 << 17]byte var x6298 [1 << 17]byte var x6299 [1 << 17]byte var x6300 [1 << 17]byte var x6301 [1 << 17]byte var x6302 [1 << 17]byte var x6303 [1 << 17]byte var x6304 [1 << 17]byte var x6305 [1 << 17]byte var x6306 [1 << 17]byte var x6307 [1 << 17]byte var x6308 [1 << 17]byte var x6309 [1 << 17]byte var x6310 [1 << 17]byte var x6311 [1 << 17]byte var x6312 [1 << 17]byte var x6313 [1 << 17]byte var x6314 [1 << 17]byte var x6315 [1 << 17]byte var x6316 [1 << 17]byte var x6317 [1 << 17]byte var x6318 [1 << 17]byte var x6319 [1 << 17]byte var x6320 [1 << 17]byte var x6321 [1 << 17]byte var x6322 [1 << 17]byte var x6323 [1 << 17]byte var x6324 [1 << 17]byte var x6325 [1 << 17]byte var x6326 [1 << 17]byte var x6327 [1 << 17]byte var x6328 [1 << 17]byte var x6329 [1 << 17]byte var x6330 [1 << 17]byte var x6331 [1 << 17]byte var x6332 [1 << 17]byte var x6333 [1 << 17]byte var x6334 [1 << 17]byte var x6335 [1 << 17]byte var x6336 [1 << 17]byte var x6337 [1 << 17]byte var x6338 [1 << 17]byte var x6339 [1 << 17]byte var x6340 [1 << 17]byte var x6341 [1 << 17]byte var x6342 [1 << 17]byte var x6343 [1 << 17]byte var x6344 [1 << 17]byte var x6345 [1 << 17]byte var x6346 [1 << 17]byte var x6347 [1 << 17]byte var x6348 [1 << 17]byte var x6349 [1 << 17]byte var x6350 [1 << 17]byte var x6351 [1 << 17]byte var x6352 [1 << 17]byte var x6353 [1 << 17]byte var x6354 [1 << 17]byte var x6355 [1 << 17]byte var x6356 [1 << 17]byte var x6357 [1 << 17]byte var x6358 [1 << 17]byte var x6359 [1 << 17]byte var x6360 [1 << 17]byte var x6361 [1 << 17]byte var x6362 [1 << 17]byte var x6363 [1 << 17]byte var x6364 [1 << 17]byte var x6365 [1 << 17]byte var x6366 [1 << 17]byte var x6367 [1 << 17]byte var x6368 [1 << 17]byte var x6369 [1 << 17]byte var x6370 [1 << 17]byte var x6371 [1 << 17]byte var x6372 [1 << 17]byte var x6373 [1 << 17]byte var x6374 [1 << 17]byte var x6375 [1 << 17]byte var x6376 [1 << 17]byte var x6377 [1 << 17]byte var x6378 [1 << 17]byte var x6379 [1 << 17]byte var x6380 [1 << 17]byte var x6381 [1 << 17]byte var x6382 [1 << 17]byte var x6383 [1 << 17]byte var x6384 [1 << 17]byte var x6385 [1 << 17]byte var x6386 [1 << 17]byte var x6387 [1 << 17]byte var x6388 [1 << 17]byte var x6389 [1 << 17]byte var x6390 [1 << 17]byte var x6391 [1 << 17]byte var x6392 [1 << 17]byte var x6393 [1 << 17]byte var x6394 [1 << 17]byte var x6395 [1 << 17]byte var x6396 [1 << 17]byte var x6397 [1 << 17]byte var x6398 [1 << 17]byte var x6399 [1 << 17]byte var x6400 [1 << 17]byte var x6401 [1 << 17]byte var x6402 [1 << 17]byte var x6403 [1 << 17]byte var x6404 [1 << 17]byte var x6405 [1 << 17]byte var x6406 [1 << 17]byte var x6407 [1 << 17]byte var x6408 [1 << 17]byte var x6409 [1 << 17]byte var x6410 [1 << 17]byte var x6411 [1 << 17]byte var x6412 [1 << 17]byte var x6413 [1 << 17]byte var x6414 [1 << 17]byte var x6415 [1 << 17]byte var x6416 [1 << 17]byte var x6417 [1 << 17]byte var x6418 [1 << 17]byte var x6419 [1 << 17]byte var x6420 [1 << 17]byte var x6421 [1 << 17]byte var x6422 [1 << 17]byte var x6423 [1 << 17]byte var x6424 [1 << 17]byte var x6425 [1 << 17]byte var x6426 [1 << 17]byte var x6427 [1 << 17]byte var x6428 [1 << 17]byte var x6429 [1 << 17]byte var x6430 [1 << 17]byte var x6431 [1 << 17]byte var x6432 [1 << 17]byte var x6433 [1 << 17]byte var x6434 [1 << 17]byte var x6435 [1 << 17]byte var x6436 [1 << 17]byte var x6437 [1 << 17]byte var x6438 [1 << 17]byte var x6439 [1 << 17]byte var x6440 [1 << 17]byte var x6441 [1 << 17]byte var x6442 [1 << 17]byte var x6443 [1 << 17]byte var x6444 [1 << 17]byte var x6445 [1 << 17]byte var x6446 [1 << 17]byte var x6447 [1 << 17]byte var x6448 [1 << 17]byte var x6449 [1 << 17]byte var x6450 [1 << 17]byte var x6451 [1 << 17]byte var x6452 [1 << 17]byte var x6453 [1 << 17]byte var x6454 [1 << 17]byte var x6455 [1 << 17]byte var x6456 [1 << 17]byte var x6457 [1 << 17]byte var x6458 [1 << 17]byte var x6459 [1 << 17]byte var x6460 [1 << 17]byte var x6461 [1 << 17]byte var x6462 [1 << 17]byte var x6463 [1 << 17]byte var x6464 [1 << 17]byte var x6465 [1 << 17]byte var x6466 [1 << 17]byte var x6467 [1 << 17]byte var x6468 [1 << 17]byte var x6469 [1 << 17]byte var x6470 [1 << 17]byte var x6471 [1 << 17]byte var x6472 [1 << 17]byte var x6473 [1 << 17]byte var x6474 [1 << 17]byte var x6475 [1 << 17]byte var x6476 [1 << 17]byte var x6477 [1 << 17]byte var x6478 [1 << 17]byte var x6479 [1 << 17]byte var x6480 [1 << 17]byte var x6481 [1 << 17]byte var x6482 [1 << 17]byte var x6483 [1 << 17]byte var x6484 [1 << 17]byte var x6485 [1 << 17]byte var x6486 [1 << 17]byte var x6487 [1 << 17]byte var x6488 [1 << 17]byte var x6489 [1 << 17]byte var x6490 [1 << 17]byte var x6491 [1 << 17]byte var x6492 [1 << 17]byte var x6493 [1 << 17]byte var x6494 [1 << 17]byte var x6495 [1 << 17]byte var x6496 [1 << 17]byte var x6497 [1 << 17]byte var x6498 [1 << 17]byte var x6499 [1 << 17]byte var x6500 [1 << 17]byte var x6501 [1 << 17]byte var x6502 [1 << 17]byte var x6503 [1 << 17]byte var x6504 [1 << 17]byte var x6505 [1 << 17]byte var x6506 [1 << 17]byte var x6507 [1 << 17]byte var x6508 [1 << 17]byte var x6509 [1 << 17]byte var x6510 [1 << 17]byte var x6511 [1 << 17]byte var x6512 [1 << 17]byte var x6513 [1 << 17]byte var x6514 [1 << 17]byte var x6515 [1 << 17]byte var x6516 [1 << 17]byte var x6517 [1 << 17]byte var x6518 [1 << 17]byte var x6519 [1 << 17]byte var x6520 [1 << 17]byte var x6521 [1 << 17]byte var x6522 [1 << 17]byte var x6523 [1 << 17]byte var x6524 [1 << 17]byte var x6525 [1 << 17]byte var x6526 [1 << 17]byte var x6527 [1 << 17]byte var x6528 [1 << 17]byte var x6529 [1 << 17]byte var x6530 [1 << 17]byte var x6531 [1 << 17]byte var x6532 [1 << 17]byte var x6533 [1 << 17]byte var x6534 [1 << 17]byte var x6535 [1 << 17]byte var x6536 [1 << 17]byte var x6537 [1 << 17]byte var x6538 [1 << 17]byte var x6539 [1 << 17]byte var x6540 [1 << 17]byte var x6541 [1 << 17]byte var x6542 [1 << 17]byte var x6543 [1 << 17]byte var x6544 [1 << 17]byte var x6545 [1 << 17]byte var x6546 [1 << 17]byte var x6547 [1 << 17]byte var x6548 [1 << 17]byte var x6549 [1 << 17]byte var x6550 [1 << 17]byte var x6551 [1 << 17]byte var x6552 [1 << 17]byte var x6553 [1 << 17]byte var x6554 [1 << 17]byte var x6555 [1 << 17]byte var x6556 [1 << 17]byte var x6557 [1 << 17]byte var x6558 [1 << 17]byte var x6559 [1 << 17]byte var x6560 [1 << 17]byte var x6561 [1 << 17]byte var x6562 [1 << 17]byte var x6563 [1 << 17]byte var x6564 [1 << 17]byte var x6565 [1 << 17]byte var x6566 [1 << 17]byte var x6567 [1 << 17]byte var x6568 [1 << 17]byte var x6569 [1 << 17]byte var x6570 [1 << 17]byte var x6571 [1 << 17]byte var x6572 [1 << 17]byte var x6573 [1 << 17]byte var x6574 [1 << 17]byte var x6575 [1 << 17]byte var x6576 [1 << 17]byte var x6577 [1 << 17]byte var x6578 [1 << 17]byte var x6579 [1 << 17]byte var x6580 [1 << 17]byte var x6581 [1 << 17]byte var x6582 [1 << 17]byte var x6583 [1 << 17]byte var x6584 [1 << 17]byte var x6585 [1 << 17]byte var x6586 [1 << 17]byte var x6587 [1 << 17]byte var x6588 [1 << 17]byte var x6589 [1 << 17]byte var x6590 [1 << 17]byte var x6591 [1 << 17]byte var x6592 [1 << 17]byte var x6593 [1 << 17]byte var x6594 [1 << 17]byte var x6595 [1 << 17]byte var x6596 [1 << 17]byte var x6597 [1 << 17]byte var x6598 [1 << 17]byte var x6599 [1 << 17]byte var x6600 [1 << 17]byte var x6601 [1 << 17]byte var x6602 [1 << 17]byte var x6603 [1 << 17]byte var x6604 [1 << 17]byte var x6605 [1 << 17]byte var x6606 [1 << 17]byte var x6607 [1 << 17]byte var x6608 [1 << 17]byte var x6609 [1 << 17]byte var x6610 [1 << 17]byte var x6611 [1 << 17]byte var x6612 [1 << 17]byte var x6613 [1 << 17]byte var x6614 [1 << 17]byte var x6615 [1 << 17]byte var x6616 [1 << 17]byte var x6617 [1 << 17]byte var x6618 [1 << 17]byte var x6619 [1 << 17]byte var x6620 [1 << 17]byte var x6621 [1 << 17]byte var x6622 [1 << 17]byte var x6623 [1 << 17]byte var x6624 [1 << 17]byte var x6625 [1 << 17]byte var x6626 [1 << 17]byte var x6627 [1 << 17]byte var x6628 [1 << 17]byte var x6629 [1 << 17]byte var x6630 [1 << 17]byte var x6631 [1 << 17]byte var x6632 [1 << 17]byte var x6633 [1 << 17]byte var x6634 [1 << 17]byte var x6635 [1 << 17]byte var x6636 [1 << 17]byte var x6637 [1 << 17]byte var x6638 [1 << 17]byte var x6639 [1 << 17]byte var x6640 [1 << 17]byte var x6641 [1 << 17]byte var x6642 [1 << 17]byte var x6643 [1 << 17]byte var x6644 [1 << 17]byte var x6645 [1 << 17]byte var x6646 [1 << 17]byte var x6647 [1 << 17]byte var x6648 [1 << 17]byte var x6649 [1 << 17]byte var x6650 [1 << 17]byte var x6651 [1 << 17]byte var x6652 [1 << 17]byte var x6653 [1 << 17]byte var x6654 [1 << 17]byte var x6655 [1 << 17]byte var x6656 [1 << 17]byte var x6657 [1 << 17]byte var x6658 [1 << 17]byte var x6659 [1 << 17]byte var x6660 [1 << 17]byte var x6661 [1 << 17]byte var x6662 [1 << 17]byte var x6663 [1 << 17]byte var x6664 [1 << 17]byte var x6665 [1 << 17]byte var x6666 [1 << 17]byte var x6667 [1 << 17]byte var x6668 [1 << 17]byte var x6669 [1 << 17]byte var x6670 [1 << 17]byte var x6671 [1 << 17]byte var x6672 [1 << 17]byte var x6673 [1 << 17]byte var x6674 [1 << 17]byte var x6675 [1 << 17]byte var x6676 [1 << 17]byte var x6677 [1 << 17]byte var x6678 [1 << 17]byte var x6679 [1 << 17]byte var x6680 [1 << 17]byte var x6681 [1 << 17]byte var x6682 [1 << 17]byte var x6683 [1 << 17]byte var x6684 [1 << 17]byte var x6685 [1 << 17]byte var x6686 [1 << 17]byte var x6687 [1 << 17]byte var x6688 [1 << 17]byte var x6689 [1 << 17]byte var x6690 [1 << 17]byte var x6691 [1 << 17]byte var x6692 [1 << 17]byte var x6693 [1 << 17]byte var x6694 [1 << 17]byte var x6695 [1 << 17]byte var x6696 [1 << 17]byte var x6697 [1 << 17]byte var x6698 [1 << 17]byte var x6699 [1 << 17]byte var x6700 [1 << 17]byte var x6701 [1 << 17]byte var x6702 [1 << 17]byte var x6703 [1 << 17]byte var x6704 [1 << 17]byte var x6705 [1 << 17]byte var x6706 [1 << 17]byte var x6707 [1 << 17]byte var x6708 [1 << 17]byte var x6709 [1 << 17]byte var x6710 [1 << 17]byte var x6711 [1 << 17]byte var x6712 [1 << 17]byte var x6713 [1 << 17]byte var x6714 [1 << 17]byte var x6715 [1 << 17]byte var x6716 [1 << 17]byte var x6717 [1 << 17]byte var x6718 [1 << 17]byte var x6719 [1 << 17]byte var x6720 [1 << 17]byte var x6721 [1 << 17]byte var x6722 [1 << 17]byte var x6723 [1 << 17]byte var x6724 [1 << 17]byte var x6725 [1 << 17]byte var x6726 [1 << 17]byte var x6727 [1 << 17]byte var x6728 [1 << 17]byte var x6729 [1 << 17]byte var x6730 [1 << 17]byte var x6731 [1 << 17]byte var x6732 [1 << 17]byte var x6733 [1 << 17]byte var x6734 [1 << 17]byte var x6735 [1 << 17]byte var x6736 [1 << 17]byte var x6737 [1 << 17]byte var x6738 [1 << 17]byte var x6739 [1 << 17]byte var x6740 [1 << 17]byte var x6741 [1 << 17]byte var x6742 [1 << 17]byte var x6743 [1 << 17]byte var x6744 [1 << 17]byte var x6745 [1 << 17]byte var x6746 [1 << 17]byte var x6747 [1 << 17]byte var x6748 [1 << 17]byte var x6749 [1 << 17]byte var x6750 [1 << 17]byte var x6751 [1 << 17]byte var x6752 [1 << 17]byte var x6753 [1 << 17]byte var x6754 [1 << 17]byte var x6755 [1 << 17]byte var x6756 [1 << 17]byte var x6757 [1 << 17]byte var x6758 [1 << 17]byte var x6759 [1 << 17]byte var x6760 [1 << 17]byte var x6761 [1 << 17]byte var x6762 [1 << 17]byte var x6763 [1 << 17]byte var x6764 [1 << 17]byte var x6765 [1 << 17]byte var x6766 [1 << 17]byte var x6767 [1 << 17]byte var x6768 [1 << 17]byte var x6769 [1 << 17]byte var x6770 [1 << 17]byte var x6771 [1 << 17]byte var x6772 [1 << 17]byte var x6773 [1 << 17]byte var x6774 [1 << 17]byte var x6775 [1 << 17]byte var x6776 [1 << 17]byte var x6777 [1 << 17]byte var x6778 [1 << 17]byte var x6779 [1 << 17]byte var x6780 [1 << 17]byte var x6781 [1 << 17]byte var x6782 [1 << 17]byte var x6783 [1 << 17]byte var x6784 [1 << 17]byte var x6785 [1 << 17]byte var x6786 [1 << 17]byte var x6787 [1 << 17]byte var x6788 [1 << 17]byte var x6789 [1 << 17]byte var x6790 [1 << 17]byte var x6791 [1 << 17]byte var x6792 [1 << 17]byte var x6793 [1 << 17]byte var x6794 [1 << 17]byte var x6795 [1 << 17]byte var x6796 [1 << 17]byte var x6797 [1 << 17]byte var x6798 [1 << 17]byte var x6799 [1 << 17]byte var x6800 [1 << 17]byte var x6801 [1 << 17]byte var x6802 [1 << 17]byte var x6803 [1 << 17]byte var x6804 [1 << 17]byte var x6805 [1 << 17]byte var x6806 [1 << 17]byte var x6807 [1 << 17]byte var x6808 [1 << 17]byte var x6809 [1 << 17]byte var x6810 [1 << 17]byte var x6811 [1 << 17]byte var x6812 [1 << 17]byte var x6813 [1 << 17]byte var x6814 [1 << 17]byte var x6815 [1 << 17]byte var x6816 [1 << 17]byte var x6817 [1 << 17]byte var x6818 [1 << 17]byte var x6819 [1 << 17]byte var x6820 [1 << 17]byte var x6821 [1 << 17]byte var x6822 [1 << 17]byte var x6823 [1 << 17]byte var x6824 [1 << 17]byte var x6825 [1 << 17]byte var x6826 [1 << 17]byte var x6827 [1 << 17]byte var x6828 [1 << 17]byte var x6829 [1 << 17]byte var x6830 [1 << 17]byte var x6831 [1 << 17]byte var x6832 [1 << 17]byte var x6833 [1 << 17]byte var x6834 [1 << 17]byte var x6835 [1 << 17]byte var x6836 [1 << 17]byte var x6837 [1 << 17]byte var x6838 [1 << 17]byte var x6839 [1 << 17]byte var x6840 [1 << 17]byte var x6841 [1 << 17]byte var x6842 [1 << 17]byte var x6843 [1 << 17]byte var x6844 [1 << 17]byte var x6845 [1 << 17]byte var x6846 [1 << 17]byte var x6847 [1 << 17]byte var x6848 [1 << 17]byte var x6849 [1 << 17]byte var x6850 [1 << 17]byte var x6851 [1 << 17]byte var x6852 [1 << 17]byte var x6853 [1 << 17]byte var x6854 [1 << 17]byte var x6855 [1 << 17]byte var x6856 [1 << 17]byte var x6857 [1 << 17]byte var x6858 [1 << 17]byte var x6859 [1 << 17]byte var x6860 [1 << 17]byte var x6861 [1 << 17]byte var x6862 [1 << 17]byte var x6863 [1 << 17]byte var x6864 [1 << 17]byte var x6865 [1 << 17]byte var x6866 [1 << 17]byte var x6867 [1 << 17]byte var x6868 [1 << 17]byte var x6869 [1 << 17]byte var x6870 [1 << 17]byte var x6871 [1 << 17]byte var x6872 [1 << 17]byte var x6873 [1 << 17]byte var x6874 [1 << 17]byte var x6875 [1 << 17]byte var x6876 [1 << 17]byte var x6877 [1 << 17]byte var x6878 [1 << 17]byte var x6879 [1 << 17]byte var x6880 [1 << 17]byte var x6881 [1 << 17]byte var x6882 [1 << 17]byte var x6883 [1 << 17]byte var x6884 [1 << 17]byte var x6885 [1 << 17]byte var x6886 [1 << 17]byte var x6887 [1 << 17]byte var x6888 [1 << 17]byte var x6889 [1 << 17]byte var x6890 [1 << 17]byte var x6891 [1 << 17]byte var x6892 [1 << 17]byte var x6893 [1 << 17]byte var x6894 [1 << 17]byte var x6895 [1 << 17]byte var x6896 [1 << 17]byte var x6897 [1 << 17]byte var x6898 [1 << 17]byte var x6899 [1 << 17]byte var x6900 [1 << 17]byte var x6901 [1 << 17]byte var x6902 [1 << 17]byte var x6903 [1 << 17]byte var x6904 [1 << 17]byte var x6905 [1 << 17]byte var x6906 [1 << 17]byte var x6907 [1 << 17]byte var x6908 [1 << 17]byte var x6909 [1 << 17]byte var x6910 [1 << 17]byte var x6911 [1 << 17]byte var x6912 [1 << 17]byte var x6913 [1 << 17]byte var x6914 [1 << 17]byte var x6915 [1 << 17]byte var x6916 [1 << 17]byte var x6917 [1 << 17]byte var x6918 [1 << 17]byte var x6919 [1 << 17]byte var x6920 [1 << 17]byte var x6921 [1 << 17]byte var x6922 [1 << 17]byte var x6923 [1 << 17]byte var x6924 [1 << 17]byte var x6925 [1 << 17]byte var x6926 [1 << 17]byte var x6927 [1 << 17]byte var x6928 [1 << 17]byte var x6929 [1 << 17]byte var x6930 [1 << 17]byte var x6931 [1 << 17]byte var x6932 [1 << 17]byte var x6933 [1 << 17]byte var x6934 [1 << 17]byte var x6935 [1 << 17]byte var x6936 [1 << 17]byte var x6937 [1 << 17]byte var x6938 [1 << 17]byte var x6939 [1 << 17]byte var x6940 [1 << 17]byte var x6941 [1 << 17]byte var x6942 [1 << 17]byte var x6943 [1 << 17]byte var x6944 [1 << 17]byte var x6945 [1 << 17]byte var x6946 [1 << 17]byte var x6947 [1 << 17]byte var x6948 [1 << 17]byte var x6949 [1 << 17]byte var x6950 [1 << 17]byte var x6951 [1 << 17]byte var x6952 [1 << 17]byte var x6953 [1 << 17]byte var x6954 [1 << 17]byte var x6955 [1 << 17]byte var x6956 [1 << 17]byte var x6957 [1 << 17]byte var x6958 [1 << 17]byte var x6959 [1 << 17]byte var x6960 [1 << 17]byte var x6961 [1 << 17]byte var x6962 [1 << 17]byte var x6963 [1 << 17]byte var x6964 [1 << 17]byte var x6965 [1 << 17]byte var x6966 [1 << 17]byte var x6967 [1 << 17]byte var x6968 [1 << 17]byte var x6969 [1 << 17]byte var x6970 [1 << 17]byte var x6971 [1 << 17]byte var x6972 [1 << 17]byte var x6973 [1 << 17]byte var x6974 [1 << 17]byte var x6975 [1 << 17]byte var x6976 [1 << 17]byte var x6977 [1 << 17]byte var x6978 [1 << 17]byte var x6979 [1 << 17]byte var x6980 [1 << 17]byte var x6981 [1 << 17]byte var x6982 [1 << 17]byte var x6983 [1 << 17]byte var x6984 [1 << 17]byte var x6985 [1 << 17]byte var x6986 [1 << 17]byte var x6987 [1 << 17]byte var x6988 [1 << 17]byte var x6989 [1 << 17]byte var x6990 [1 << 17]byte var x6991 [1 << 17]byte var x6992 [1 << 17]byte var x6993 [1 << 17]byte var x6994 [1 << 17]byte var x6995 [1 << 17]byte var x6996 [1 << 17]byte var x6997 [1 << 17]byte var x6998 [1 << 17]byte var x6999 [1 << 17]byte var x7000 [1 << 17]byte var x7001 [1 << 17]byte var x7002 [1 << 17]byte var x7003 [1 << 17]byte var x7004 [1 << 17]byte var x7005 [1 << 17]byte var x7006 [1 << 17]byte var x7007 [1 << 17]byte var x7008 [1 << 17]byte var x7009 [1 << 17]byte var x7010 [1 << 17]byte var x7011 [1 << 17]byte var x7012 [1 << 17]byte var x7013 [1 << 17]byte var x7014 [1 << 17]byte var x7015 [1 << 17]byte var x7016 [1 << 17]byte var x7017 [1 << 17]byte var x7018 [1 << 17]byte var x7019 [1 << 17]byte var x7020 [1 << 17]byte var x7021 [1 << 17]byte var x7022 [1 << 17]byte var x7023 [1 << 17]byte var x7024 [1 << 17]byte var x7025 [1 << 17]byte var x7026 [1 << 17]byte var x7027 [1 << 17]byte var x7028 [1 << 17]byte var x7029 [1 << 17]byte var x7030 [1 << 17]byte var x7031 [1 << 17]byte var x7032 [1 << 17]byte var x7033 [1 << 17]byte var x7034 [1 << 17]byte var x7035 [1 << 17]byte var x7036 [1 << 17]byte var x7037 [1 << 17]byte var x7038 [1 << 17]byte var x7039 [1 << 17]byte var x7040 [1 << 17]byte var x7041 [1 << 17]byte var x7042 [1 << 17]byte var x7043 [1 << 17]byte var x7044 [1 << 17]byte var x7045 [1 << 17]byte var x7046 [1 << 17]byte var x7047 [1 << 17]byte var x7048 [1 << 17]byte var x7049 [1 << 17]byte var x7050 [1 << 17]byte var x7051 [1 << 17]byte var x7052 [1 << 17]byte var x7053 [1 << 17]byte var x7054 [1 << 17]byte var x7055 [1 << 17]byte var x7056 [1 << 17]byte var x7057 [1 << 17]byte var x7058 [1 << 17]byte var x7059 [1 << 17]byte var x7060 [1 << 17]byte var x7061 [1 << 17]byte var x7062 [1 << 17]byte var x7063 [1 << 17]byte var x7064 [1 << 17]byte var x7065 [1 << 17]byte var x7066 [1 << 17]byte var x7067 [1 << 17]byte var x7068 [1 << 17]byte var x7069 [1 << 17]byte var x7070 [1 << 17]byte var x7071 [1 << 17]byte var x7072 [1 << 17]byte var x7073 [1 << 17]byte var x7074 [1 << 17]byte var x7075 [1 << 17]byte var x7076 [1 << 17]byte var x7077 [1 << 17]byte var x7078 [1 << 17]byte var x7079 [1 << 17]byte var x7080 [1 << 17]byte var x7081 [1 << 17]byte var x7082 [1 << 17]byte var x7083 [1 << 17]byte var x7084 [1 << 17]byte var x7085 [1 << 17]byte var x7086 [1 << 17]byte var x7087 [1 << 17]byte var x7088 [1 << 17]byte var x7089 [1 << 17]byte var x7090 [1 << 17]byte var x7091 [1 << 17]byte var x7092 [1 << 17]byte var x7093 [1 << 17]byte var x7094 [1 << 17]byte var x7095 [1 << 17]byte var x7096 [1 << 17]byte var x7097 [1 << 17]byte var x7098 [1 << 17]byte var x7099 [1 << 17]byte var x7100 [1 << 17]byte var x7101 [1 << 17]byte var x7102 [1 << 17]byte var x7103 [1 << 17]byte var x7104 [1 << 17]byte var x7105 [1 << 17]byte var x7106 [1 << 17]byte var x7107 [1 << 17]byte var x7108 [1 << 17]byte var x7109 [1 << 17]byte var x7110 [1 << 17]byte var x7111 [1 << 17]byte var x7112 [1 << 17]byte var x7113 [1 << 17]byte var x7114 [1 << 17]byte var x7115 [1 << 17]byte var x7116 [1 << 17]byte var x7117 [1 << 17]byte var x7118 [1 << 17]byte var x7119 [1 << 17]byte var x7120 [1 << 17]byte var x7121 [1 << 17]byte var x7122 [1 << 17]byte var x7123 [1 << 17]byte var x7124 [1 << 17]byte var x7125 [1 << 17]byte var x7126 [1 << 17]byte var x7127 [1 << 17]byte var x7128 [1 << 17]byte var x7129 [1 << 17]byte var x7130 [1 << 17]byte var x7131 [1 << 17]byte var x7132 [1 << 17]byte var x7133 [1 << 17]byte var x7134 [1 << 17]byte var x7135 [1 << 17]byte var x7136 [1 << 17]byte var x7137 [1 << 17]byte var x7138 [1 << 17]byte var x7139 [1 << 17]byte var x7140 [1 << 17]byte var x7141 [1 << 17]byte var x7142 [1 << 17]byte var x7143 [1 << 17]byte var x7144 [1 << 17]byte var x7145 [1 << 17]byte var x7146 [1 << 17]byte var x7147 [1 << 17]byte var x7148 [1 << 17]byte var x7149 [1 << 17]byte var x7150 [1 << 17]byte var x7151 [1 << 17]byte var x7152 [1 << 17]byte var x7153 [1 << 17]byte var x7154 [1 << 17]byte var x7155 [1 << 17]byte var x7156 [1 << 17]byte var x7157 [1 << 17]byte var x7158 [1 << 17]byte var x7159 [1 << 17]byte var x7160 [1 << 17]byte var x7161 [1 << 17]byte var x7162 [1 << 17]byte var x7163 [1 << 17]byte var x7164 [1 << 17]byte var x7165 [1 << 17]byte var x7166 [1 << 17]byte var x7167 [1 << 17]byte var x7168 [1 << 17]byte var x7169 [1 << 17]byte var x7170 [1 << 17]byte var x7171 [1 << 17]byte var x7172 [1 << 17]byte var x7173 [1 << 17]byte var x7174 [1 << 17]byte var x7175 [1 << 17]byte var x7176 [1 << 17]byte var x7177 [1 << 17]byte var x7178 [1 << 17]byte var x7179 [1 << 17]byte var x7180 [1 << 17]byte var x7181 [1 << 17]byte var x7182 [1 << 17]byte var x7183 [1 << 17]byte var x7184 [1 << 17]byte var x7185 [1 << 17]byte var x7186 [1 << 17]byte var x7187 [1 << 17]byte var x7188 [1 << 17]byte var x7189 [1 << 17]byte var x7190 [1 << 17]byte var x7191 [1 << 17]byte var x7192 [1 << 17]byte var x7193 [1 << 17]byte var x7194 [1 << 17]byte var x7195 [1 << 17]byte var x7196 [1 << 17]byte var x7197 [1 << 17]byte var x7198 [1 << 17]byte var x7199 [1 << 17]byte var x7200 [1 << 17]byte var x7201 [1 << 17]byte var x7202 [1 << 17]byte var x7203 [1 << 17]byte var x7204 [1 << 17]byte var x7205 [1 << 17]byte var x7206 [1 << 17]byte var x7207 [1 << 17]byte var x7208 [1 << 17]byte var x7209 [1 << 17]byte var x7210 [1 << 17]byte var x7211 [1 << 17]byte var x7212 [1 << 17]byte var x7213 [1 << 17]byte var x7214 [1 << 17]byte var x7215 [1 << 17]byte var x7216 [1 << 17]byte var x7217 [1 << 17]byte var x7218 [1 << 17]byte var x7219 [1 << 17]byte var x7220 [1 << 17]byte var x7221 [1 << 17]byte var x7222 [1 << 17]byte var x7223 [1 << 17]byte var x7224 [1 << 17]byte var x7225 [1 << 17]byte var x7226 [1 << 17]byte var x7227 [1 << 17]byte var x7228 [1 << 17]byte var x7229 [1 << 17]byte var x7230 [1 << 17]byte var x7231 [1 << 17]byte var x7232 [1 << 17]byte var x7233 [1 << 17]byte var x7234 [1 << 17]byte var x7235 [1 << 17]byte var x7236 [1 << 17]byte var x7237 [1 << 17]byte var x7238 [1 << 17]byte var x7239 [1 << 17]byte var x7240 [1 << 17]byte var x7241 [1 << 17]byte var x7242 [1 << 17]byte var x7243 [1 << 17]byte var x7244 [1 << 17]byte var x7245 [1 << 17]byte var x7246 [1 << 17]byte var x7247 [1 << 17]byte var x7248 [1 << 17]byte var x7249 [1 << 17]byte var x7250 [1 << 17]byte var x7251 [1 << 17]byte var x7252 [1 << 17]byte var x7253 [1 << 17]byte var x7254 [1 << 17]byte var x7255 [1 << 17]byte var x7256 [1 << 17]byte var x7257 [1 << 17]byte var x7258 [1 << 17]byte var x7259 [1 << 17]byte var x7260 [1 << 17]byte var x7261 [1 << 17]byte var x7262 [1 << 17]byte var x7263 [1 << 17]byte var x7264 [1 << 17]byte var x7265 [1 << 17]byte var x7266 [1 << 17]byte var x7267 [1 << 17]byte var x7268 [1 << 17]byte var x7269 [1 << 17]byte var x7270 [1 << 17]byte var x7271 [1 << 17]byte var x7272 [1 << 17]byte var x7273 [1 << 17]byte var x7274 [1 << 17]byte var x7275 [1 << 17]byte var x7276 [1 << 17]byte var x7277 [1 << 17]byte var x7278 [1 << 17]byte var x7279 [1 << 17]byte var x7280 [1 << 17]byte var x7281 [1 << 17]byte var x7282 [1 << 17]byte var x7283 [1 << 17]byte var x7284 [1 << 17]byte var x7285 [1 << 17]byte var x7286 [1 << 17]byte var x7287 [1 << 17]byte var x7288 [1 << 17]byte var x7289 [1 << 17]byte var x7290 [1 << 17]byte var x7291 [1 << 17]byte var x7292 [1 << 17]byte var x7293 [1 << 17]byte var x7294 [1 << 17]byte var x7295 [1 << 17]byte var x7296 [1 << 17]byte var x7297 [1 << 17]byte var x7298 [1 << 17]byte var x7299 [1 << 17]byte var x7300 [1 << 17]byte var x7301 [1 << 17]byte var x7302 [1 << 17]byte var x7303 [1 << 17]byte var x7304 [1 << 17]byte var x7305 [1 << 17]byte var x7306 [1 << 17]byte var x7307 [1 << 17]byte var x7308 [1 << 17]byte var x7309 [1 << 17]byte var x7310 [1 << 17]byte var x7311 [1 << 17]byte var x7312 [1 << 17]byte var x7313 [1 << 17]byte var x7314 [1 << 17]byte var x7315 [1 << 17]byte var x7316 [1 << 17]byte var x7317 [1 << 17]byte var x7318 [1 << 17]byte var x7319 [1 << 17]byte var x7320 [1 << 17]byte var x7321 [1 << 17]byte var x7322 [1 << 17]byte var x7323 [1 << 17]byte var x7324 [1 << 17]byte var x7325 [1 << 17]byte var x7326 [1 << 17]byte var x7327 [1 << 17]byte var x7328 [1 << 17]byte var x7329 [1 << 17]byte var x7330 [1 << 17]byte var x7331 [1 << 17]byte var x7332 [1 << 17]byte var x7333 [1 << 17]byte var x7334 [1 << 17]byte var x7335 [1 << 17]byte var x7336 [1 << 17]byte var x7337 [1 << 17]byte var x7338 [1 << 17]byte var x7339 [1 << 17]byte var x7340 [1 << 17]byte var x7341 [1 << 17]byte var x7342 [1 << 17]byte var x7343 [1 << 17]byte var x7344 [1 << 17]byte var x7345 [1 << 17]byte var x7346 [1 << 17]byte var x7347 [1 << 17]byte var x7348 [1 << 17]byte var x7349 [1 << 17]byte var x7350 [1 << 17]byte var x7351 [1 << 17]byte var x7352 [1 << 17]byte var x7353 [1 << 17]byte var x7354 [1 << 17]byte var x7355 [1 << 17]byte var x7356 [1 << 17]byte var x7357 [1 << 17]byte var x7358 [1 << 17]byte var x7359 [1 << 17]byte var x7360 [1 << 17]byte var x7361 [1 << 17]byte var x7362 [1 << 17]byte var x7363 [1 << 17]byte var x7364 [1 << 17]byte var x7365 [1 << 17]byte var x7366 [1 << 17]byte var x7367 [1 << 17]byte var x7368 [1 << 17]byte var x7369 [1 << 17]byte var x7370 [1 << 17]byte var x7371 [1 << 17]byte var x7372 [1 << 17]byte var x7373 [1 << 17]byte var x7374 [1 << 17]byte var x7375 [1 << 17]byte var x7376 [1 << 17]byte var x7377 [1 << 17]byte var x7378 [1 << 17]byte var x7379 [1 << 17]byte var x7380 [1 << 17]byte var x7381 [1 << 17]byte var x7382 [1 << 17]byte var x7383 [1 << 17]byte var x7384 [1 << 17]byte var x7385 [1 << 17]byte var x7386 [1 << 17]byte var x7387 [1 << 17]byte var x7388 [1 << 17]byte var x7389 [1 << 17]byte var x7390 [1 << 17]byte var x7391 [1 << 17]byte var x7392 [1 << 17]byte var x7393 [1 << 17]byte var x7394 [1 << 17]byte var x7395 [1 << 17]byte var x7396 [1 << 17]byte var x7397 [1 << 17]byte var x7398 [1 << 17]byte var x7399 [1 << 17]byte var x7400 [1 << 17]byte var x7401 [1 << 17]byte var x7402 [1 << 17]byte var x7403 [1 << 17]byte var x7404 [1 << 17]byte var x7405 [1 << 17]byte var x7406 [1 << 17]byte var x7407 [1 << 17]byte var x7408 [1 << 17]byte var x7409 [1 << 17]byte var x7410 [1 << 17]byte var x7411 [1 << 17]byte var x7412 [1 << 17]byte var x7413 [1 << 17]byte var x7414 [1 << 17]byte var x7415 [1 << 17]byte var x7416 [1 << 17]byte var x7417 [1 << 17]byte var x7418 [1 << 17]byte var x7419 [1 << 17]byte var x7420 [1 << 17]byte var x7421 [1 << 17]byte var x7422 [1 << 17]byte var x7423 [1 << 17]byte var x7424 [1 << 17]byte var x7425 [1 << 17]byte var x7426 [1 << 17]byte var x7427 [1 << 17]byte var x7428 [1 << 17]byte var x7429 [1 << 17]byte var x7430 [1 << 17]byte var x7431 [1 << 17]byte var x7432 [1 << 17]byte var x7433 [1 << 17]byte var x7434 [1 << 17]byte var x7435 [1 << 17]byte var x7436 [1 << 17]byte var x7437 [1 << 17]byte var x7438 [1 << 17]byte var x7439 [1 << 17]byte var x7440 [1 << 17]byte var x7441 [1 << 17]byte var x7442 [1 << 17]byte var x7443 [1 << 17]byte var x7444 [1 << 17]byte var x7445 [1 << 17]byte var x7446 [1 << 17]byte var x7447 [1 << 17]byte var x7448 [1 << 17]byte var x7449 [1 << 17]byte var x7450 [1 << 17]byte var x7451 [1 << 17]byte var x7452 [1 << 17]byte var x7453 [1 << 17]byte var x7454 [1 << 17]byte var x7455 [1 << 17]byte var x7456 [1 << 17]byte var x7457 [1 << 17]byte var x7458 [1 << 17]byte var x7459 [1 << 17]byte var x7460 [1 << 17]byte var x7461 [1 << 17]byte var x7462 [1 << 17]byte var x7463 [1 << 17]byte var x7464 [1 << 17]byte var x7465 [1 << 17]byte var x7466 [1 << 17]byte var x7467 [1 << 17]byte var x7468 [1 << 17]byte var x7469 [1 << 17]byte var x7470 [1 << 17]byte var x7471 [1 << 17]byte var x7472 [1 << 17]byte var x7473 [1 << 17]byte var x7474 [1 << 17]byte var x7475 [1 << 17]byte var x7476 [1 << 17]byte var x7477 [1 << 17]byte var x7478 [1 << 17]byte var x7479 [1 << 17]byte var x7480 [1 << 17]byte var x7481 [1 << 17]byte var x7482 [1 << 17]byte var x7483 [1 << 17]byte var x7484 [1 << 17]byte var x7485 [1 << 17]byte var x7486 [1 << 17]byte var x7487 [1 << 17]byte var x7488 [1 << 17]byte var x7489 [1 << 17]byte var x7490 [1 << 17]byte var x7491 [1 << 17]byte var x7492 [1 << 17]byte var x7493 [1 << 17]byte var x7494 [1 << 17]byte var x7495 [1 << 17]byte var x7496 [1 << 17]byte var x7497 [1 << 17]byte var x7498 [1 << 17]byte var x7499 [1 << 17]byte var x7500 [1 << 17]byte var x7501 [1 << 17]byte var x7502 [1 << 17]byte var x7503 [1 << 17]byte var x7504 [1 << 17]byte var x7505 [1 << 17]byte var x7506 [1 << 17]byte var x7507 [1 << 17]byte var x7508 [1 << 17]byte var x7509 [1 << 17]byte var x7510 [1 << 17]byte var x7511 [1 << 17]byte var x7512 [1 << 17]byte var x7513 [1 << 17]byte var x7514 [1 << 17]byte var x7515 [1 << 17]byte var x7516 [1 << 17]byte var x7517 [1 << 17]byte var x7518 [1 << 17]byte var x7519 [1 << 17]byte var x7520 [1 << 17]byte var x7521 [1 << 17]byte var x7522 [1 << 17]byte var x7523 [1 << 17]byte var x7524 [1 << 17]byte var x7525 [1 << 17]byte var x7526 [1 << 17]byte var x7527 [1 << 17]byte var x7528 [1 << 17]byte var x7529 [1 << 17]byte var x7530 [1 << 17]byte var x7531 [1 << 17]byte var x7532 [1 << 17]byte var x7533 [1 << 17]byte var x7534 [1 << 17]byte var x7535 [1 << 17]byte var x7536 [1 << 17]byte var x7537 [1 << 17]byte var x7538 [1 << 17]byte var x7539 [1 << 17]byte var x7540 [1 << 17]byte var x7541 [1 << 17]byte var x7542 [1 << 17]byte var x7543 [1 << 17]byte var x7544 [1 << 17]byte var x7545 [1 << 17]byte var x7546 [1 << 17]byte var x7547 [1 << 17]byte var x7548 [1 << 17]byte var x7549 [1 << 17]byte var x7550 [1 << 17]byte var x7551 [1 << 17]byte var x7552 [1 << 17]byte var x7553 [1 << 17]byte var x7554 [1 << 17]byte var x7555 [1 << 17]byte var x7556 [1 << 17]byte var x7557 [1 << 17]byte var x7558 [1 << 17]byte var x7559 [1 << 17]byte var x7560 [1 << 17]byte var x7561 [1 << 17]byte var x7562 [1 << 17]byte var x7563 [1 << 17]byte var x7564 [1 << 17]byte var x7565 [1 << 17]byte var x7566 [1 << 17]byte var x7567 [1 << 17]byte var x7568 [1 << 17]byte var x7569 [1 << 17]byte var x7570 [1 << 17]byte var x7571 [1 << 17]byte var x7572 [1 << 17]byte var x7573 [1 << 17]byte var x7574 [1 << 17]byte var x7575 [1 << 17]byte var x7576 [1 << 17]byte var x7577 [1 << 17]byte var x7578 [1 << 17]byte var x7579 [1 << 17]byte var x7580 [1 << 17]byte var x7581 [1 << 17]byte var x7582 [1 << 17]byte var x7583 [1 << 17]byte var x7584 [1 << 17]byte var x7585 [1 << 17]byte var x7586 [1 << 17]byte var x7587 [1 << 17]byte var x7588 [1 << 17]byte var x7589 [1 << 17]byte var x7590 [1 << 17]byte var x7591 [1 << 17]byte var x7592 [1 << 17]byte var x7593 [1 << 17]byte var x7594 [1 << 17]byte var x7595 [1 << 17]byte var x7596 [1 << 17]byte var x7597 [1 << 17]byte var x7598 [1 << 17]byte var x7599 [1 << 17]byte var x7600 [1 << 17]byte var x7601 [1 << 17]byte var x7602 [1 << 17]byte var x7603 [1 << 17]byte var x7604 [1 << 17]byte var x7605 [1 << 17]byte var x7606 [1 << 17]byte var x7607 [1 << 17]byte var x7608 [1 << 17]byte var x7609 [1 << 17]byte var x7610 [1 << 17]byte var x7611 [1 << 17]byte var x7612 [1 << 17]byte var x7613 [1 << 17]byte var x7614 [1 << 17]byte var x7615 [1 << 17]byte var x7616 [1 << 17]byte var x7617 [1 << 17]byte var x7618 [1 << 17]byte var x7619 [1 << 17]byte var x7620 [1 << 17]byte var x7621 [1 << 17]byte var x7622 [1 << 17]byte var x7623 [1 << 17]byte var x7624 [1 << 17]byte var x7625 [1 << 17]byte var x7626 [1 << 17]byte var x7627 [1 << 17]byte var x7628 [1 << 17]byte var x7629 [1 << 17]byte var x7630 [1 << 17]byte var x7631 [1 << 17]byte var x7632 [1 << 17]byte var x7633 [1 << 17]byte var x7634 [1 << 17]byte var x7635 [1 << 17]byte var x7636 [1 << 17]byte var x7637 [1 << 17]byte var x7638 [1 << 17]byte var x7639 [1 << 17]byte var x7640 [1 << 17]byte var x7641 [1 << 17]byte var x7642 [1 << 17]byte var x7643 [1 << 17]byte var x7644 [1 << 17]byte var x7645 [1 << 17]byte var x7646 [1 << 17]byte var x7647 [1 << 17]byte var x7648 [1 << 17]byte var x7649 [1 << 17]byte var x7650 [1 << 17]byte var x7651 [1 << 17]byte var x7652 [1 << 17]byte var x7653 [1 << 17]byte var x7654 [1 << 17]byte var x7655 [1 << 17]byte var x7656 [1 << 17]byte var x7657 [1 << 17]byte var x7658 [1 << 17]byte var x7659 [1 << 17]byte var x7660 [1 << 17]byte var x7661 [1 << 17]byte var x7662 [1 << 17]byte var x7663 [1 << 17]byte var x7664 [1 << 17]byte var x7665 [1 << 17]byte var x7666 [1 << 17]byte var x7667 [1 << 17]byte var x7668 [1 << 17]byte var x7669 [1 << 17]byte var x7670 [1 << 17]byte var x7671 [1 << 17]byte var x7672 [1 << 17]byte var x7673 [1 << 17]byte var x7674 [1 << 17]byte var x7675 [1 << 17]byte var x7676 [1 << 17]byte var x7677 [1 << 17]byte var x7678 [1 << 17]byte var x7679 [1 << 17]byte var x7680 [1 << 17]byte var x7681 [1 << 17]byte var x7682 [1 << 17]byte var x7683 [1 << 17]byte var x7684 [1 << 17]byte var x7685 [1 << 17]byte var x7686 [1 << 17]byte var x7687 [1 << 17]byte var x7688 [1 << 17]byte var x7689 [1 << 17]byte var x7690 [1 << 17]byte var x7691 [1 << 17]byte var x7692 [1 << 17]byte var x7693 [1 << 17]byte var x7694 [1 << 17]byte var x7695 [1 << 17]byte var x7696 [1 << 17]byte var x7697 [1 << 17]byte var x7698 [1 << 17]byte var x7699 [1 << 17]byte var x7700 [1 << 17]byte var x7701 [1 << 17]byte var x7702 [1 << 17]byte var x7703 [1 << 17]byte var x7704 [1 << 17]byte var x7705 [1 << 17]byte var x7706 [1 << 17]byte var x7707 [1 << 17]byte var x7708 [1 << 17]byte var x7709 [1 << 17]byte var x7710 [1 << 17]byte var x7711 [1 << 17]byte var x7712 [1 << 17]byte var x7713 [1 << 17]byte var x7714 [1 << 17]byte var x7715 [1 << 17]byte var x7716 [1 << 17]byte var x7717 [1 << 17]byte var x7718 [1 << 17]byte var x7719 [1 << 17]byte var x7720 [1 << 17]byte var x7721 [1 << 17]byte var x7722 [1 << 17]byte var x7723 [1 << 17]byte var x7724 [1 << 17]byte var x7725 [1 << 17]byte var x7726 [1 << 17]byte var x7727 [1 << 17]byte var x7728 [1 << 17]byte var x7729 [1 << 17]byte var x7730 [1 << 17]byte var x7731 [1 << 17]byte var x7732 [1 << 17]byte var x7733 [1 << 17]byte var x7734 [1 << 17]byte var x7735 [1 << 17]byte var x7736 [1 << 17]byte var x7737 [1 << 17]byte var x7738 [1 << 17]byte var x7739 [1 << 17]byte var x7740 [1 << 17]byte var x7741 [1 << 17]byte var x7742 [1 << 17]byte var x7743 [1 << 17]byte var x7744 [1 << 17]byte var x7745 [1 << 17]byte var x7746 [1 << 17]byte var x7747 [1 << 17]byte var x7748 [1 << 17]byte var x7749 [1 << 17]byte var x7750 [1 << 17]byte var x7751 [1 << 17]byte var x7752 [1 << 17]byte var x7753 [1 << 17]byte var x7754 [1 << 17]byte var x7755 [1 << 17]byte var x7756 [1 << 17]byte var x7757 [1 << 17]byte var x7758 [1 << 17]byte var x7759 [1 << 17]byte var x7760 [1 << 17]byte var x7761 [1 << 17]byte var x7762 [1 << 17]byte var x7763 [1 << 17]byte var x7764 [1 << 17]byte var x7765 [1 << 17]byte var x7766 [1 << 17]byte var x7767 [1 << 17]byte var x7768 [1 << 17]byte var x7769 [1 << 17]byte var x7770 [1 << 17]byte var x7771 [1 << 17]byte var x7772 [1 << 17]byte var x7773 [1 << 17]byte var x7774 [1 << 17]byte var x7775 [1 << 17]byte var x7776 [1 << 17]byte var x7777 [1 << 17]byte var x7778 [1 << 17]byte var x7779 [1 << 17]byte var x7780 [1 << 17]byte var x7781 [1 << 17]byte var x7782 [1 << 17]byte var x7783 [1 << 17]byte var x7784 [1 << 17]byte var x7785 [1 << 17]byte var x7786 [1 << 17]byte var x7787 [1 << 17]byte var x7788 [1 << 17]byte var x7789 [1 << 17]byte var x7790 [1 << 17]byte var x7791 [1 << 17]byte var x7792 [1 << 17]byte var x7793 [1 << 17]byte var x7794 [1 << 17]byte var x7795 [1 << 17]byte var x7796 [1 << 17]byte var x7797 [1 << 17]byte var x7798 [1 << 17]byte var x7799 [1 << 17]byte var x7800 [1 << 17]byte var x7801 [1 << 17]byte var x7802 [1 << 17]byte var x7803 [1 << 17]byte var x7804 [1 << 17]byte var x7805 [1 << 17]byte var x7806 [1 << 17]byte var x7807 [1 << 17]byte var x7808 [1 << 17]byte var x7809 [1 << 17]byte var x7810 [1 << 17]byte var x7811 [1 << 17]byte var x7812 [1 << 17]byte var x7813 [1 << 17]byte var x7814 [1 << 17]byte var x7815 [1 << 17]byte var x7816 [1 << 17]byte var x7817 [1 << 17]byte var x7818 [1 << 17]byte var x7819 [1 << 17]byte var x7820 [1 << 17]byte var x7821 [1 << 17]byte var x7822 [1 << 17]byte var x7823 [1 << 17]byte var x7824 [1 << 17]byte var x7825 [1 << 17]byte var x7826 [1 << 17]byte var x7827 [1 << 17]byte var x7828 [1 << 17]byte var x7829 [1 << 17]byte var x7830 [1 << 17]byte var x7831 [1 << 17]byte var x7832 [1 << 17]byte var x7833 [1 << 17]byte var x7834 [1 << 17]byte var x7835 [1 << 17]byte var x7836 [1 << 17]byte var x7837 [1 << 17]byte var x7838 [1 << 17]byte var x7839 [1 << 17]byte var x7840 [1 << 17]byte var x7841 [1 << 17]byte var x7842 [1 << 17]byte var x7843 [1 << 17]byte var x7844 [1 << 17]byte var x7845 [1 << 17]byte var x7846 [1 << 17]byte var x7847 [1 << 17]byte var x7848 [1 << 17]byte var x7849 [1 << 17]byte var x7850 [1 << 17]byte var x7851 [1 << 17]byte var x7852 [1 << 17]byte var x7853 [1 << 17]byte var x7854 [1 << 17]byte var x7855 [1 << 17]byte var x7856 [1 << 17]byte var x7857 [1 << 17]byte var x7858 [1 << 17]byte var x7859 [1 << 17]byte var x7860 [1 << 17]byte var x7861 [1 << 17]byte var x7862 [1 << 17]byte var x7863 [1 << 17]byte var x7864 [1 << 17]byte var x7865 [1 << 17]byte var x7866 [1 << 17]byte var x7867 [1 << 17]byte var x7868 [1 << 17]byte var x7869 [1 << 17]byte var x7870 [1 << 17]byte var x7871 [1 << 17]byte var x7872 [1 << 17]byte var x7873 [1 << 17]byte var x7874 [1 << 17]byte var x7875 [1 << 17]byte var x7876 [1 << 17]byte var x7877 [1 << 17]byte var x7878 [1 << 17]byte var x7879 [1 << 17]byte var x7880 [1 << 17]byte var x7881 [1 << 17]byte var x7882 [1 << 17]byte var x7883 [1 << 17]byte var x7884 [1 << 17]byte var x7885 [1 << 17]byte var x7886 [1 << 17]byte var x7887 [1 << 17]byte var x7888 [1 << 17]byte var x7889 [1 << 17]byte var x7890 [1 << 17]byte var x7891 [1 << 17]byte var x7892 [1 << 17]byte var x7893 [1 << 17]byte var x7894 [1 << 17]byte var x7895 [1 << 17]byte var x7896 [1 << 17]byte var x7897 [1 << 17]byte var x7898 [1 << 17]byte var x7899 [1 << 17]byte var x7900 [1 << 17]byte var x7901 [1 << 17]byte var x7902 [1 << 17]byte var x7903 [1 << 17]byte var x7904 [1 << 17]byte var x7905 [1 << 17]byte var x7906 [1 << 17]byte var x7907 [1 << 17]byte var x7908 [1 << 17]byte var x7909 [1 << 17]byte var x7910 [1 << 17]byte var x7911 [1 << 17]byte var x7912 [1 << 17]byte var x7913 [1 << 17]byte var x7914 [1 << 17]byte var x7915 [1 << 17]byte var x7916 [1 << 17]byte var x7917 [1 << 17]byte var x7918 [1 << 17]byte var x7919 [1 << 17]byte var x7920 [1 << 17]byte var x7921 [1 << 17]byte var x7922 [1 << 17]byte var x7923 [1 << 17]byte var x7924 [1 << 17]byte var x7925 [1 << 17]byte var x7926 [1 << 17]byte var x7927 [1 << 17]byte var x7928 [1 << 17]byte var x7929 [1 << 17]byte var x7930 [1 << 17]byte var x7931 [1 << 17]byte var x7932 [1 << 17]byte var x7933 [1 << 17]byte var x7934 [1 << 17]byte var x7935 [1 << 17]byte var x7936 [1 << 17]byte var x7937 [1 << 17]byte var x7938 [1 << 17]byte var x7939 [1 << 17]byte var x7940 [1 << 17]byte var x7941 [1 << 17]byte var x7942 [1 << 17]byte var x7943 [1 << 17]byte var x7944 [1 << 17]byte var x7945 [1 << 17]byte var x7946 [1 << 17]byte var x7947 [1 << 17]byte var x7948 [1 << 17]byte var x7949 [1 << 17]byte var x7950 [1 << 17]byte var x7951 [1 << 17]byte var x7952 [1 << 17]byte var x7953 [1 << 17]byte var x7954 [1 << 17]byte var x7955 [1 << 17]byte var x7956 [1 << 17]byte var x7957 [1 << 17]byte var x7958 [1 << 17]byte var x7959 [1 << 17]byte var x7960 [1 << 17]byte var x7961 [1 << 17]byte var x7962 [1 << 17]byte var x7963 [1 << 17]byte var x7964 [1 << 17]byte var x7965 [1 << 17]byte var x7966 [1 << 17]byte var x7967 [1 << 17]byte var x7968 [1 << 17]byte var x7969 [1 << 17]byte var x7970 [1 << 17]byte var x7971 [1 << 17]byte var x7972 [1 << 17]byte var x7973 [1 << 17]byte var x7974 [1 << 17]byte var x7975 [1 << 17]byte var x7976 [1 << 17]byte var x7977 [1 << 17]byte var x7978 [1 << 17]byte var x7979 [1 << 17]byte var x7980 [1 << 17]byte var x7981 [1 << 17]byte var x7982 [1 << 17]byte var x7983 [1 << 17]byte var x7984 [1 << 17]byte var x7985 [1 << 17]byte var x7986 [1 << 17]byte var x7987 [1 << 17]byte var x7988 [1 << 17]byte var x7989 [1 << 17]byte var x7990 [1 << 17]byte var x7991 [1 << 17]byte var x7992 [1 << 17]byte var x7993 [1 << 17]byte var x7994 [1 << 17]byte var x7995 [1 << 17]byte var x7996 [1 << 17]byte var x7997 [1 << 17]byte var x7998 [1 << 17]byte var x7999 [1 << 17]byte var x8000 [1 << 17]byte var x8001 [1 << 17]byte var x8002 [1 << 17]byte var x8003 [1 << 17]byte var x8004 [1 << 17]byte var x8005 [1 << 17]byte var x8006 [1 << 17]byte var x8007 [1 << 17]byte var x8008 [1 << 17]byte var x8009 [1 << 17]byte var x8010 [1 << 17]byte var x8011 [1 << 17]byte var x8012 [1 << 17]byte var x8013 [1 << 17]byte var x8014 [1 << 17]byte var x8015 [1 << 17]byte var x8016 [1 << 17]byte var x8017 [1 << 17]byte var x8018 [1 << 17]byte var x8019 [1 << 17]byte var x8020 [1 << 17]byte var x8021 [1 << 17]byte var x8022 [1 << 17]byte var x8023 [1 << 17]byte var x8024 [1 << 17]byte var x8025 [1 << 17]byte var x8026 [1 << 17]byte var x8027 [1 << 17]byte var x8028 [1 << 17]byte var x8029 [1 << 17]byte var x8030 [1 << 17]byte var x8031 [1 << 17]byte var x8032 [1 << 17]byte var x8033 [1 << 17]byte var x8034 [1 << 17]byte var x8035 [1 << 17]byte var x8036 [1 << 17]byte var x8037 [1 << 17]byte var x8038 [1 << 17]byte var x8039 [1 << 17]byte var x8040 [1 << 17]byte var x8041 [1 << 17]byte var x8042 [1 << 17]byte var x8043 [1 << 17]byte var x8044 [1 << 17]byte var x8045 [1 << 17]byte var x8046 [1 << 17]byte var x8047 [1 << 17]byte var x8048 [1 << 17]byte var x8049 [1 << 17]byte var x8050 [1 << 17]byte var x8051 [1 << 17]byte var x8052 [1 << 17]byte var x8053 [1 << 17]byte var x8054 [1 << 17]byte var x8055 [1 << 17]byte var x8056 [1 << 17]byte var x8057 [1 << 17]byte var x8058 [1 << 17]byte var x8059 [1 << 17]byte var x8060 [1 << 17]byte var x8061 [1 << 17]byte var x8062 [1 << 17]byte var x8063 [1 << 17]byte var x8064 [1 << 17]byte var x8065 [1 << 17]byte var x8066 [1 << 17]byte var x8067 [1 << 17]byte var x8068 [1 << 17]byte var x8069 [1 << 17]byte var x8070 [1 << 17]byte var x8071 [1 << 17]byte var x8072 [1 << 17]byte var x8073 [1 << 17]byte var x8074 [1 << 17]byte var x8075 [1 << 17]byte var x8076 [1 << 17]byte var x8077 [1 << 17]byte var x8078 [1 << 17]byte var x8079 [1 << 17]byte var x8080 [1 << 17]byte var x8081 [1 << 17]byte var x8082 [1 << 17]byte var x8083 [1 << 17]byte var x8084 [1 << 17]byte var x8085 [1 << 17]byte var x8086 [1 << 17]byte var x8087 [1 << 17]byte var x8088 [1 << 17]byte var x8089 [1 << 17]byte var x8090 [1 << 17]byte var x8091 [1 << 17]byte var x8092 [1 << 17]byte var x8093 [1 << 17]byte var x8094 [1 << 17]byte var x8095 [1 << 17]byte var x8096 [1 << 17]byte var x8097 [1 << 17]byte var x8098 [1 << 17]byte var x8099 [1 << 17]byte var x8100 [1 << 17]byte var x8101 [1 << 17]byte var x8102 [1 << 17]byte var x8103 [1 << 17]byte var x8104 [1 << 17]byte var x8105 [1 << 17]byte var x8106 [1 << 17]byte var x8107 [1 << 17]byte var x8108 [1 << 17]byte var x8109 [1 << 17]byte var x8110 [1 << 17]byte var x8111 [1 << 17]byte var x8112 [1 << 17]byte var x8113 [1 << 17]byte var x8114 [1 << 17]byte var x8115 [1 << 17]byte var x8116 [1 << 17]byte var x8117 [1 << 17]byte var x8118 [1 << 17]byte var x8119 [1 << 17]byte var x8120 [1 << 17]byte var x8121 [1 << 17]byte var x8122 [1 << 17]byte var x8123 [1 << 17]byte var x8124 [1 << 17]byte var x8125 [1 << 17]byte var x8126 [1 << 17]byte var x8127 [1 << 17]byte var x8128 [1 << 17]byte var x8129 [1 << 17]byte var x8130 [1 << 17]byte var x8131 [1 << 17]byte var x8132 [1 << 17]byte var x8133 [1 << 17]byte var x8134 [1 << 17]byte var x8135 [1 << 17]byte var x8136 [1 << 17]byte var x8137 [1 << 17]byte var x8138 [1 << 17]byte var x8139 [1 << 17]byte var x8140 [1 << 17]byte var x8141 [1 << 17]byte var x8142 [1 << 17]byte var x8143 [1 << 17]byte var x8144 [1 << 17]byte var x8145 [1 << 17]byte var x8146 [1 << 17]byte var x8147 [1 << 17]byte var x8148 [1 << 17]byte var x8149 [1 << 17]byte var x8150 [1 << 17]byte var x8151 [1 << 17]byte var x8152 [1 << 17]byte var x8153 [1 << 17]byte var x8154 [1 << 17]byte var x8155 [1 << 17]byte var x8156 [1 << 17]byte var x8157 [1 << 17]byte var x8158 [1 << 17]byte var x8159 [1 << 17]byte var x8160 [1 << 17]byte var x8161 [1 << 17]byte var x8162 [1 << 17]byte var x8163 [1 << 17]byte var x8164 [1 << 17]byte var x8165 [1 << 17]byte var x8166 [1 << 17]byte var x8167 [1 << 17]byte var x8168 [1 << 17]byte var x8169 [1 << 17]byte var x8170 [1 << 17]byte var x8171 [1 << 17]byte var x8172 [1 << 17]byte var x8173 [1 << 17]byte var x8174 [1 << 17]byte var x8175 [1 << 17]byte var x8176 [1 << 17]byte var x8177 [1 << 17]byte var x8178 [1 << 17]byte var x8179 [1 << 17]byte var x8180 [1 << 17]byte var x8181 [1 << 17]byte var x8182 [1 << 17]byte var x8183 [1 << 17]byte var x8184 [1 << 17]byte var x8185 [1 << 17]byte var x8186 [1 << 17]byte var x8187 [1 << 17]byte var x8188 [1 << 17]byte var x8189 [1 << 17]byte var x8190 [1 << 17]byte var x8191 [1 << 17]byte var x8192 [1 << 17]byte var x8193 [1 << 17]byte var x8194 [1 << 17]byte var x8195 [1 << 17]byte var x8196 [1 << 17]byte var x8197 [1 << 17]byte var x8198 [1 << 17]byte var x8199 [1 << 17]byte var x8200 [1 << 17]byte var x8201 [1 << 17]byte var x8202 [1 << 17]byte var x8203 [1 << 17]byte var x8204 [1 << 17]byte var x8205 [1 << 17]byte var x8206 [1 << 17]byte var x8207 [1 << 17]byte var x8208 [1 << 17]byte var x8209 [1 << 17]byte var x8210 [1 << 17]byte var x8211 [1 << 17]byte var x8212 [1 << 17]byte var x8213 [1 << 17]byte var x8214 [1 << 17]byte var x8215 [1 << 17]byte var x8216 [1 << 17]byte var x8217 [1 << 17]byte var x8218 [1 << 17]byte var x8219 [1 << 17]byte var x8220 [1 << 17]byte var x8221 [1 << 17]byte var x8222 [1 << 17]byte var x8223 [1 << 17]byte var x8224 [1 << 17]byte var x8225 [1 << 17]byte var x8226 [1 << 17]byte var x8227 [1 << 17]byte var x8228 [1 << 17]byte var x8229 [1 << 17]byte var x8230 [1 << 17]byte var x8231 [1 << 17]byte var x8232 [1 << 17]byte var x8233 [1 << 17]byte var x8234 [1 << 17]byte var x8235 [1 << 17]byte var x8236 [1 << 17]byte var x8237 [1 << 17]byte var x8238 [1 << 17]byte var x8239 [1 << 17]byte var x8240 [1 << 17]byte var x8241 [1 << 17]byte var x8242 [1 << 17]byte var x8243 [1 << 17]byte var x8244 [1 << 17]byte var x8245 [1 << 17]byte var x8246 [1 << 17]byte var x8247 [1 << 17]byte var x8248 [1 << 17]byte var x8249 [1 << 17]byte var x8250 [1 << 17]byte var x8251 [1 << 17]byte var x8252 [1 << 17]byte var x8253 [1 << 17]byte var x8254 [1 << 17]byte var x8255 [1 << 17]byte var x8256 [1 << 17]byte var x8257 [1 << 17]byte var x8258 [1 << 17]byte var x8259 [1 << 17]byte var x8260 [1 << 17]byte var x8261 [1 << 17]byte var x8262 [1 << 17]byte var x8263 [1 << 17]byte var x8264 [1 << 17]byte var x8265 [1 << 17]byte var x8266 [1 << 17]byte var x8267 [1 << 17]byte var x8268 [1 << 17]byte var x8269 [1 << 17]byte var x8270 [1 << 17]byte var x8271 [1 << 17]byte var x8272 [1 << 17]byte var x8273 [1 << 17]byte var x8274 [1 << 17]byte var x8275 [1 << 17]byte var x8276 [1 << 17]byte var x8277 [1 << 17]byte var x8278 [1 << 17]byte var x8279 [1 << 17]byte var x8280 [1 << 17]byte var x8281 [1 << 17]byte var x8282 [1 << 17]byte var x8283 [1 << 17]byte var x8284 [1 << 17]byte var x8285 [1 << 17]byte var x8286 [1 << 17]byte var x8287 [1 << 17]byte var x8288 [1 << 17]byte var x8289 [1 << 17]byte var x8290 [1 << 17]byte var x8291 [1 << 17]byte var x8292 [1 << 17]byte var x8293 [1 << 17]byte var x8294 [1 << 17]byte var x8295 [1 << 17]byte var x8296 [1 << 17]byte var x8297 [1 << 17]byte var x8298 [1 << 17]byte var x8299 [1 << 17]byte var x8300 [1 << 17]byte var x8301 [1 << 17]byte var x8302 [1 << 17]byte var x8303 [1 << 17]byte var x8304 [1 << 17]byte var x8305 [1 << 17]byte var x8306 [1 << 17]byte var x8307 [1 << 17]byte var x8308 [1 << 17]byte var x8309 [1 << 17]byte var x8310 [1 << 17]byte var x8311 [1 << 17]byte var x8312 [1 << 17]byte var x8313 [1 << 17]byte var x8314 [1 << 17]byte var x8315 [1 << 17]byte var x8316 [1 << 17]byte var x8317 [1 << 17]byte var x8318 [1 << 17]byte var x8319 [1 << 17]byte var x8320 [1 << 17]byte var x8321 [1 << 17]byte var x8322 [1 << 17]byte var x8323 [1 << 17]byte var x8324 [1 << 17]byte var x8325 [1 << 17]byte var x8326 [1 << 17]byte var x8327 [1 << 17]byte var x8328 [1 << 17]byte var x8329 [1 << 17]byte var x8330 [1 << 17]byte var x8331 [1 << 17]byte var x8332 [1 << 17]byte var x8333 [1 << 17]byte var x8334 [1 << 17]byte var x8335 [1 << 17]byte var x8336 [1 << 17]byte var x8337 [1 << 17]byte var x8338 [1 << 17]byte var x8339 [1 << 17]byte var x8340 [1 << 17]byte var x8341 [1 << 17]byte var x8342 [1 << 17]byte var x8343 [1 << 17]byte var x8344 [1 << 17]byte var x8345 [1 << 17]byte var x8346 [1 << 17]byte var x8347 [1 << 17]byte var x8348 [1 << 17]byte var x8349 [1 << 17]byte var x8350 [1 << 17]byte var x8351 [1 << 17]byte var x8352 [1 << 17]byte var x8353 [1 << 17]byte var x8354 [1 << 17]byte var x8355 [1 << 17]byte var x8356 [1 << 17]byte var x8357 [1 << 17]byte var x8358 [1 << 17]byte var x8359 [1 << 17]byte var x8360 [1 << 17]byte var x8361 [1 << 17]byte var x8362 [1 << 17]byte var x8363 [1 << 17]byte var x8364 [1 << 17]byte var x8365 [1 << 17]byte var x8366 [1 << 17]byte var x8367 [1 << 17]byte var x8368 [1 << 17]byte var x8369 [1 << 17]byte var x8370 [1 << 17]byte var x8371 [1 << 17]byte var x8372 [1 << 17]byte var x8373 [1 << 17]byte var x8374 [1 << 17]byte var x8375 [1 << 17]byte var x8376 [1 << 17]byte var x8377 [1 << 17]byte var x8378 [1 << 17]byte var x8379 [1 << 17]byte var x8380 [1 << 17]byte var x8381 [1 << 17]byte var x8382 [1 << 17]byte var x8383 [1 << 17]byte var x8384 [1 << 17]byte var x8385 [1 << 17]byte var x8386 [1 << 17]byte var x8387 [1 << 17]byte var x8388 [1 << 17]byte var x8389 [1 << 17]byte var x8390 [1 << 17]byte var x8391 [1 << 17]byte var x8392 [1 << 17]byte var x8393 [1 << 17]byte var x8394 [1 << 17]byte var x8395 [1 << 17]byte var x8396 [1 << 17]byte var x8397 [1 << 17]byte var x8398 [1 << 17]byte var x8399 [1 << 17]byte var x8400 [1 << 17]byte var x8401 [1 << 17]byte var x8402 [1 << 17]byte var x8403 [1 << 17]byte var x8404 [1 << 17]byte var x8405 [1 << 17]byte var x8406 [1 << 17]byte var x8407 [1 << 17]byte var x8408 [1 << 17]byte var x8409 [1 << 17]byte var x8410 [1 << 17]byte var x8411 [1 << 17]byte var x8412 [1 << 17]byte var x8413 [1 << 17]byte var x8414 [1 << 17]byte var x8415 [1 << 17]byte var x8416 [1 << 17]byte var x8417 [1 << 17]byte var x8418 [1 << 17]byte var x8419 [1 << 17]byte var x8420 [1 << 17]byte var x8421 [1 << 17]byte var x8422 [1 << 17]byte var x8423 [1 << 17]byte var x8424 [1 << 17]byte var x8425 [1 << 17]byte var x8426 [1 << 17]byte var x8427 [1 << 17]byte var x8428 [1 << 17]byte var x8429 [1 << 17]byte var x8430 [1 << 17]byte var x8431 [1 << 17]byte var x8432 [1 << 17]byte var x8433 [1 << 17]byte var x8434 [1 << 17]byte var x8435 [1 << 17]byte var x8436 [1 << 17]byte var x8437 [1 << 17]byte var x8438 [1 << 17]byte var x8439 [1 << 17]byte var x8440 [1 << 17]byte var x8441 [1 << 17]byte var x8442 [1 << 17]byte var x8443 [1 << 17]byte var x8444 [1 << 17]byte var x8445 [1 << 17]byte var x8446 [1 << 17]byte var x8447 [1 << 17]byte var x8448 [1 << 17]byte var x8449 [1 << 17]byte var x8450 [1 << 17]byte var x8451 [1 << 17]byte var x8452 [1 << 17]byte var x8453 [1 << 17]byte var x8454 [1 << 17]byte var x8455 [1 << 17]byte var x8456 [1 << 17]byte var x8457 [1 << 17]byte var x8458 [1 << 17]byte var x8459 [1 << 17]byte var x8460 [1 << 17]byte var x8461 [1 << 17]byte var x8462 [1 << 17]byte var x8463 [1 << 17]byte var x8464 [1 << 17]byte var x8465 [1 << 17]byte var x8466 [1 << 17]byte var x8467 [1 << 17]byte var x8468 [1 << 17]byte var x8469 [1 << 17]byte var x8470 [1 << 17]byte var x8471 [1 << 17]byte var x8472 [1 << 17]byte var x8473 [1 << 17]byte var x8474 [1 << 17]byte var x8475 [1 << 17]byte var x8476 [1 << 17]byte var x8477 [1 << 17]byte var x8478 [1 << 17]byte var x8479 [1 << 17]byte var x8480 [1 << 17]byte var x8481 [1 << 17]byte var x8482 [1 << 17]byte var x8483 [1 << 17]byte var x8484 [1 << 17]byte var x8485 [1 << 17]byte var x8486 [1 << 17]byte var x8487 [1 << 17]byte var x8488 [1 << 17]byte var x8489 [1 << 17]byte var x8490 [1 << 17]byte var x8491 [1 << 17]byte var x8492 [1 << 17]byte var x8493 [1 << 17]byte var x8494 [1 << 17]byte var x8495 [1 << 17]byte var x8496 [1 << 17]byte var x8497 [1 << 17]byte var x8498 [1 << 17]byte var x8499 [1 << 17]byte var x8500 [1 << 17]byte var x8501 [1 << 17]byte var x8502 [1 << 17]byte var x8503 [1 << 17]byte var x8504 [1 << 17]byte var x8505 [1 << 17]byte var x8506 [1 << 17]byte var x8507 [1 << 17]byte var x8508 [1 << 17]byte var x8509 [1 << 17]byte var x8510 [1 << 17]byte var x8511 [1 << 17]byte var x8512 [1 << 17]byte var x8513 [1 << 17]byte var x8514 [1 << 17]byte var x8515 [1 << 17]byte var x8516 [1 << 17]byte var x8517 [1 << 17]byte var x8518 [1 << 17]byte var x8519 [1 << 17]byte var x8520 [1 << 17]byte var x8521 [1 << 17]byte var x8522 [1 << 17]byte var x8523 [1 << 17]byte var x8524 [1 << 17]byte var x8525 [1 << 17]byte var x8526 [1 << 17]byte var x8527 [1 << 17]byte var x8528 [1 << 17]byte var x8529 [1 << 17]byte var x8530 [1 << 17]byte var x8531 [1 << 17]byte var x8532 [1 << 17]byte var x8533 [1 << 17]byte var x8534 [1 << 17]byte var x8535 [1 << 17]byte var x8536 [1 << 17]byte var x8537 [1 << 17]byte var x8538 [1 << 17]byte var x8539 [1 << 17]byte var x8540 [1 << 17]byte var x8541 [1 << 17]byte var x8542 [1 << 17]byte var x8543 [1 << 17]byte var x8544 [1 << 17]byte var x8545 [1 << 17]byte var x8546 [1 << 17]byte var x8547 [1 << 17]byte var x8548 [1 << 17]byte var x8549 [1 << 17]byte var x8550 [1 << 17]byte var x8551 [1 << 17]byte var x8552 [1 << 17]byte var x8553 [1 << 17]byte var x8554 [1 << 17]byte var x8555 [1 << 17]byte var x8556 [1 << 17]byte var x8557 [1 << 17]byte var x8558 [1 << 17]byte var x8559 [1 << 17]byte var x8560 [1 << 17]byte var x8561 [1 << 17]byte var x8562 [1 << 17]byte var x8563 [1 << 17]byte var x8564 [1 << 17]byte var x8565 [1 << 17]byte var x8566 [1 << 17]byte var x8567 [1 << 17]byte var x8568 [1 << 17]byte var x8569 [1 << 17]byte var x8570 [1 << 17]byte var x8571 [1 << 17]byte var x8572 [1 << 17]byte var x8573 [1 << 17]byte var x8574 [1 << 17]byte var x8575 [1 << 17]byte var x8576 [1 << 17]byte var x8577 [1 << 17]byte var x8578 [1 << 17]byte var x8579 [1 << 17]byte var x8580 [1 << 17]byte var x8581 [1 << 17]byte var x8582 [1 << 17]byte var x8583 [1 << 17]byte var x8584 [1 << 17]byte var x8585 [1 << 17]byte var x8586 [1 << 17]byte var x8587 [1 << 17]byte var x8588 [1 << 17]byte var x8589 [1 << 17]byte var x8590 [1 << 17]byte var x8591 [1 << 17]byte var x8592 [1 << 17]byte var x8593 [1 << 17]byte var x8594 [1 << 17]byte var x8595 [1 << 17]byte var x8596 [1 << 17]byte var x8597 [1 << 17]byte var x8598 [1 << 17]byte var x8599 [1 << 17]byte var x8600 [1 << 17]byte var x8601 [1 << 17]byte var x8602 [1 << 17]byte var x8603 [1 << 17]byte var x8604 [1 << 17]byte var x8605 [1 << 17]byte var x8606 [1 << 17]byte var x8607 [1 << 17]byte var x8608 [1 << 17]byte var x8609 [1 << 17]byte var x8610 [1 << 17]byte var x8611 [1 << 17]byte var x8612 [1 << 17]byte var x8613 [1 << 17]byte var x8614 [1 << 17]byte var x8615 [1 << 17]byte var x8616 [1 << 17]byte var x8617 [1 << 17]byte var x8618 [1 << 17]byte var x8619 [1 << 17]byte var x8620 [1 << 17]byte var x8621 [1 << 17]byte var x8622 [1 << 17]byte var x8623 [1 << 17]byte var x8624 [1 << 17]byte var x8625 [1 << 17]byte var x8626 [1 << 17]byte var x8627 [1 << 17]byte var x8628 [1 << 17]byte var x8629 [1 << 17]byte var x8630 [1 << 17]byte var x8631 [1 << 17]byte var x8632 [1 << 17]byte var x8633 [1 << 17]byte var x8634 [1 << 17]byte var x8635 [1 << 17]byte var x8636 [1 << 17]byte var x8637 [1 << 17]byte var x8638 [1 << 17]byte var x8639 [1 << 17]byte var x8640 [1 << 17]byte var x8641 [1 << 17]byte var x8642 [1 << 17]byte var x8643 [1 << 17]byte var x8644 [1 << 17]byte var x8645 [1 << 17]byte var x8646 [1 << 17]byte var x8647 [1 << 17]byte var x8648 [1 << 17]byte var x8649 [1 << 17]byte var x8650 [1 << 17]byte var x8651 [1 << 17]byte var x8652 [1 << 17]byte var x8653 [1 << 17]byte var x8654 [1 << 17]byte var x8655 [1 << 17]byte var x8656 [1 << 17]byte var x8657 [1 << 17]byte var x8658 [1 << 17]byte var x8659 [1 << 17]byte var x8660 [1 << 17]byte var x8661 [1 << 17]byte var x8662 [1 << 17]byte var x8663 [1 << 17]byte var x8664 [1 << 17]byte var x8665 [1 << 17]byte var x8666 [1 << 17]byte var x8667 [1 << 17]byte var x8668 [1 << 17]byte var x8669 [1 << 17]byte var x8670 [1 << 17]byte var x8671 [1 << 17]byte var x8672 [1 << 17]byte var x8673 [1 << 17]byte var x8674 [1 << 17]byte var x8675 [1 << 17]byte var x8676 [1 << 17]byte var x8677 [1 << 17]byte var x8678 [1 << 17]byte var x8679 [1 << 17]byte var x8680 [1 << 17]byte var x8681 [1 << 17]byte var x8682 [1 << 17]byte var x8683 [1 << 17]byte var x8684 [1 << 17]byte var x8685 [1 << 17]byte var x8686 [1 << 17]byte var x8687 [1 << 17]byte var x8688 [1 << 17]byte var x8689 [1 << 17]byte var x8690 [1 << 17]byte var x8691 [1 << 17]byte var x8692 [1 << 17]byte var x8693 [1 << 17]byte var x8694 [1 << 17]byte var x8695 [1 << 17]byte var x8696 [1 << 17]byte var x8697 [1 << 17]byte var x8698 [1 << 17]byte var x8699 [1 << 17]byte var x8700 [1 << 17]byte var x8701 [1 << 17]byte var x8702 [1 << 17]byte var x8703 [1 << 17]byte var x8704 [1 << 17]byte var x8705 [1 << 17]byte var x8706 [1 << 17]byte var x8707 [1 << 17]byte var x8708 [1 << 17]byte var x8709 [1 << 17]byte var x8710 [1 << 17]byte var x8711 [1 << 17]byte var x8712 [1 << 17]byte var x8713 [1 << 17]byte var x8714 [1 << 17]byte var x8715 [1 << 17]byte var x8716 [1 << 17]byte var x8717 [1 << 17]byte var x8718 [1 << 17]byte var x8719 [1 << 17]byte var x8720 [1 << 17]byte var x8721 [1 << 17]byte var x8722 [1 << 17]byte var x8723 [1 << 17]byte var x8724 [1 << 17]byte var x8725 [1 << 17]byte var x8726 [1 << 17]byte var x8727 [1 << 17]byte var x8728 [1 << 17]byte var x8729 [1 << 17]byte var x8730 [1 << 17]byte var x8731 [1 << 17]byte var x8732 [1 << 17]byte var x8733 [1 << 17]byte var x8734 [1 << 17]byte var x8735 [1 << 17]byte var x8736 [1 << 17]byte var x8737 [1 << 17]byte var x8738 [1 << 17]byte var x8739 [1 << 17]byte var x8740 [1 << 17]byte var x8741 [1 << 17]byte var x8742 [1 << 17]byte var x8743 [1 << 17]byte var x8744 [1 << 17]byte var x8745 [1 << 17]byte var x8746 [1 << 17]byte var x8747 [1 << 17]byte var x8748 [1 << 17]byte var x8749 [1 << 17]byte var x8750 [1 << 17]byte var x8751 [1 << 17]byte var x8752 [1 << 17]byte var x8753 [1 << 17]byte var x8754 [1 << 17]byte var x8755 [1 << 17]byte var x8756 [1 << 17]byte var x8757 [1 << 17]byte var x8758 [1 << 17]byte var x8759 [1 << 17]byte var x8760 [1 << 17]byte var x8761 [1 << 17]byte var x8762 [1 << 17]byte var x8763 [1 << 17]byte var x8764 [1 << 17]byte var x8765 [1 << 17]byte var x8766 [1 << 17]byte var x8767 [1 << 17]byte var x8768 [1 << 17]byte var x8769 [1 << 17]byte var x8770 [1 << 17]byte var x8771 [1 << 17]byte var x8772 [1 << 17]byte var x8773 [1 << 17]byte var x8774 [1 << 17]byte var x8775 [1 << 17]byte var x8776 [1 << 17]byte var x8777 [1 << 17]byte var x8778 [1 << 17]byte var x8779 [1 << 17]byte var x8780 [1 << 17]byte var x8781 [1 << 17]byte var x8782 [1 << 17]byte var x8783 [1 << 17]byte var x8784 [1 << 17]byte var x8785 [1 << 17]byte var x8786 [1 << 17]byte var x8787 [1 << 17]byte var x8788 [1 << 17]byte var x8789 [1 << 17]byte var x8790 [1 << 17]byte var x8791 [1 << 17]byte var x8792 [1 << 17]byte var x8793 [1 << 17]byte var x8794 [1 << 17]byte var x8795 [1 << 17]byte var x8796 [1 << 17]byte var x8797 [1 << 17]byte var x8798 [1 << 17]byte var x8799 [1 << 17]byte var x8800 [1 << 17]byte var x8801 [1 << 17]byte var x8802 [1 << 17]byte var x8803 [1 << 17]byte var x8804 [1 << 17]byte var x8805 [1 << 17]byte var x8806 [1 << 17]byte var x8807 [1 << 17]byte var x8808 [1 << 17]byte var x8809 [1 << 17]byte var x8810 [1 << 17]byte var x8811 [1 << 17]byte var x8812 [1 << 17]byte var x8813 [1 << 17]byte var x8814 [1 << 17]byte var x8815 [1 << 17]byte var x8816 [1 << 17]byte var x8817 [1 << 17]byte var x8818 [1 << 17]byte var x8819 [1 << 17]byte var x8820 [1 << 17]byte var x8821 [1 << 17]byte var x8822 [1 << 17]byte var x8823 [1 << 17]byte var x8824 [1 << 17]byte var x8825 [1 << 17]byte var x8826 [1 << 17]byte var x8827 [1 << 17]byte var x8828 [1 << 17]byte var x8829 [1 << 17]byte var x8830 [1 << 17]byte var x8831 [1 << 17]byte var x8832 [1 << 17]byte var x8833 [1 << 17]byte var x8834 [1 << 17]byte var x8835 [1 << 17]byte var x8836 [1 << 17]byte var x8837 [1 << 17]byte var x8838 [1 << 17]byte var x8839 [1 << 17]byte var x8840 [1 << 17]byte var x8841 [1 << 17]byte var x8842 [1 << 17]byte var x8843 [1 << 17]byte var x8844 [1 << 17]byte var x8845 [1 << 17]byte var x8846 [1 << 17]byte var x8847 [1 << 17]byte var x8848 [1 << 17]byte var x8849 [1 << 17]byte var x8850 [1 << 17]byte var x8851 [1 << 17]byte var x8852 [1 << 17]byte var x8853 [1 << 17]byte var x8854 [1 << 17]byte var x8855 [1 << 17]byte var x8856 [1 << 17]byte var x8857 [1 << 17]byte var x8858 [1 << 17]byte var x8859 [1 << 17]byte var x8860 [1 << 17]byte var x8861 [1 << 17]byte var x8862 [1 << 17]byte var x8863 [1 << 17]byte var x8864 [1 << 17]byte var x8865 [1 << 17]byte var x8866 [1 << 17]byte var x8867 [1 << 17]byte var x8868 [1 << 17]byte var x8869 [1 << 17]byte var x8870 [1 << 17]byte var x8871 [1 << 17]byte var x8872 [1 << 17]byte var x8873 [1 << 17]byte var x8874 [1 << 17]byte var x8875 [1 << 17]byte var x8876 [1 << 17]byte var x8877 [1 << 17]byte var x8878 [1 << 17]byte var x8879 [1 << 17]byte var x8880 [1 << 17]byte var x8881 [1 << 17]byte var x8882 [1 << 17]byte var x8883 [1 << 17]byte var x8884 [1 << 17]byte var x8885 [1 << 17]byte var x8886 [1 << 17]byte var x8887 [1 << 17]byte var x8888 [1 << 17]byte var x8889 [1 << 17]byte var x8890 [1 << 17]byte var x8891 [1 << 17]byte var x8892 [1 << 17]byte var x8893 [1 << 17]byte var x8894 [1 << 17]byte var x8895 [1 << 17]byte var x8896 [1 << 17]byte var x8897 [1 << 17]byte var x8898 [1 << 17]byte var x8899 [1 << 17]byte var x8900 [1 << 17]byte var x8901 [1 << 17]byte var x8902 [1 << 17]byte var x8903 [1 << 17]byte var x8904 [1 << 17]byte var x8905 [1 << 17]byte var x8906 [1 << 17]byte var x8907 [1 << 17]byte var x8908 [1 << 17]byte var x8909 [1 << 17]byte var x8910 [1 << 17]byte var x8911 [1 << 17]byte var x8912 [1 << 17]byte var x8913 [1 << 17]byte var x8914 [1 << 17]byte var x8915 [1 << 17]byte var x8916 [1 << 17]byte var x8917 [1 << 17]byte var x8918 [1 << 17]byte var x8919 [1 << 17]byte var x8920 [1 << 17]byte var x8921 [1 << 17]byte var x8922 [1 << 17]byte var x8923 [1 << 17]byte var x8924 [1 << 17]byte var x8925 [1 << 17]byte var x8926 [1 << 17]byte var x8927 [1 << 17]byte var x8928 [1 << 17]byte var x8929 [1 << 17]byte var x8930 [1 << 17]byte var x8931 [1 << 17]byte var x8932 [1 << 17]byte var x8933 [1 << 17]byte var x8934 [1 << 17]byte var x8935 [1 << 17]byte var x8936 [1 << 17]byte var x8937 [1 << 17]byte var x8938 [1 << 17]byte var x8939 [1 << 17]byte var x8940 [1 << 17]byte var x8941 [1 << 17]byte var x8942 [1 << 17]byte var x8943 [1 << 17]byte var x8944 [1 << 17]byte var x8945 [1 << 17]byte var x8946 [1 << 17]byte var x8947 [1 << 17]byte var x8948 [1 << 17]byte var x8949 [1 << 17]byte var x8950 [1 << 17]byte var x8951 [1 << 17]byte var x8952 [1 << 17]byte var x8953 [1 << 17]byte var x8954 [1 << 17]byte var x8955 [1 << 17]byte var x8956 [1 << 17]byte var x8957 [1 << 17]byte var x8958 [1 << 17]byte var x8959 [1 << 17]byte var x8960 [1 << 17]byte var x8961 [1 << 17]byte var x8962 [1 << 17]byte var x8963 [1 << 17]byte var x8964 [1 << 17]byte var x8965 [1 << 17]byte var x8966 [1 << 17]byte var x8967 [1 << 17]byte var x8968 [1 << 17]byte var x8969 [1 << 17]byte var x8970 [1 << 17]byte var x8971 [1 << 17]byte var x8972 [1 << 17]byte var x8973 [1 << 17]byte var x8974 [1 << 17]byte var x8975 [1 << 17]byte var x8976 [1 << 17]byte var x8977 [1 << 17]byte var x8978 [1 << 17]byte var x8979 [1 << 17]byte var x8980 [1 << 17]byte var x8981 [1 << 17]byte var x8982 [1 << 17]byte var x8983 [1 << 17]byte var x8984 [1 << 17]byte var x8985 [1 << 17]byte var x8986 [1 << 17]byte var x8987 [1 << 17]byte var x8988 [1 << 17]byte var x8989 [1 << 17]byte var x8990 [1 << 17]byte var x8991 [1 << 17]byte var x8992 [1 << 17]byte var x8993 [1 << 17]byte var x8994 [1 << 17]byte var x8995 [1 << 17]byte var x8996 [1 << 17]byte var x8997 [1 << 17]byte var x8998 [1 << 17]byte var x8999 [1 << 17]byte var x9000 [1 << 17]byte var x9001 [1 << 17]byte var x9002 [1 << 17]byte var x9003 [1 << 17]byte var x9004 [1 << 17]byte var x9005 [1 << 17]byte var x9006 [1 << 17]byte var x9007 [1 << 17]byte var x9008 [1 << 17]byte var x9009 [1 << 17]byte var x9010 [1 << 17]byte var x9011 [1 << 17]byte var x9012 [1 << 17]byte var x9013 [1 << 17]byte var x9014 [1 << 17]byte var x9015 [1 << 17]byte var x9016 [1 << 17]byte var x9017 [1 << 17]byte var x9018 [1 << 17]byte var x9019 [1 << 17]byte var x9020 [1 << 17]byte var x9021 [1 << 17]byte var x9022 [1 << 17]byte var x9023 [1 << 17]byte var x9024 [1 << 17]byte var x9025 [1 << 17]byte var x9026 [1 << 17]byte var x9027 [1 << 17]byte var x9028 [1 << 17]byte var x9029 [1 << 17]byte var x9030 [1 << 17]byte var x9031 [1 << 17]byte var x9032 [1 << 17]byte var x9033 [1 << 17]byte var x9034 [1 << 17]byte var x9035 [1 << 17]byte var x9036 [1 << 17]byte var x9037 [1 << 17]byte var x9038 [1 << 17]byte var x9039 [1 << 17]byte var x9040 [1 << 17]byte var x9041 [1 << 17]byte var x9042 [1 << 17]byte var x9043 [1 << 17]byte var x9044 [1 << 17]byte var x9045 [1 << 17]byte var x9046 [1 << 17]byte var x9047 [1 << 17]byte var x9048 [1 << 17]byte var x9049 [1 << 17]byte var x9050 [1 << 17]byte var x9051 [1 << 17]byte var x9052 [1 << 17]byte var x9053 [1 << 17]byte var x9054 [1 << 17]byte var x9055 [1 << 17]byte var x9056 [1 << 17]byte var x9057 [1 << 17]byte var x9058 [1 << 17]byte var x9059 [1 << 17]byte var x9060 [1 << 17]byte var x9061 [1 << 17]byte var x9062 [1 << 17]byte var x9063 [1 << 17]byte var x9064 [1 << 17]byte var x9065 [1 << 17]byte var x9066 [1 << 17]byte var x9067 [1 << 17]byte var x9068 [1 << 17]byte var x9069 [1 << 17]byte var x9070 [1 << 17]byte var x9071 [1 << 17]byte var x9072 [1 << 17]byte var x9073 [1 << 17]byte var x9074 [1 << 17]byte var x9075 [1 << 17]byte var x9076 [1 << 17]byte var x9077 [1 << 17]byte var x9078 [1 << 17]byte var x9079 [1 << 17]byte var x9080 [1 << 17]byte var x9081 [1 << 17]byte var x9082 [1 << 17]byte var x9083 [1 << 17]byte var x9084 [1 << 17]byte var x9085 [1 << 17]byte var x9086 [1 << 17]byte var x9087 [1 << 17]byte var x9088 [1 << 17]byte var x9089 [1 << 17]byte var x9090 [1 << 17]byte var x9091 [1 << 17]byte var x9092 [1 << 17]byte var x9093 [1 << 17]byte var x9094 [1 << 17]byte var x9095 [1 << 17]byte var x9096 [1 << 17]byte var x9097 [1 << 17]byte var x9098 [1 << 17]byte var x9099 [1 << 17]byte var x9100 [1 << 17]byte var x9101 [1 << 17]byte var x9102 [1 << 17]byte var x9103 [1 << 17]byte var x9104 [1 << 17]byte var x9105 [1 << 17]byte var x9106 [1 << 17]byte var x9107 [1 << 17]byte var x9108 [1 << 17]byte var x9109 [1 << 17]byte var x9110 [1 << 17]byte var x9111 [1 << 17]byte var x9112 [1 << 17]byte var x9113 [1 << 17]byte var x9114 [1 << 17]byte var x9115 [1 << 17]byte var x9116 [1 << 17]byte var x9117 [1 << 17]byte var x9118 [1 << 17]byte var x9119 [1 << 17]byte var x9120 [1 << 17]byte var x9121 [1 << 17]byte var x9122 [1 << 17]byte var x9123 [1 << 17]byte var x9124 [1 << 17]byte var x9125 [1 << 17]byte var x9126 [1 << 17]byte var x9127 [1 << 17]byte var x9128 [1 << 17]byte var x9129 [1 << 17]byte var x9130 [1 << 17]byte var x9131 [1 << 17]byte var x9132 [1 << 17]byte var x9133 [1 << 17]byte var x9134 [1 << 17]byte var x9135 [1 << 17]byte var x9136 [1 << 17]byte var x9137 [1 << 17]byte var x9138 [1 << 17]byte var x9139 [1 << 17]byte var x9140 [1 << 17]byte var x9141 [1 << 17]byte var x9142 [1 << 17]byte var x9143 [1 << 17]byte var x9144 [1 << 17]byte var x9145 [1 << 17]byte var x9146 [1 << 17]byte var x9147 [1 << 17]byte var x9148 [1 << 17]byte var x9149 [1 << 17]byte var x9150 [1 << 17]byte var x9151 [1 << 17]byte var x9152 [1 << 17]byte var x9153 [1 << 17]byte var x9154 [1 << 17]byte var x9155 [1 << 17]byte var x9156 [1 << 17]byte var x9157 [1 << 17]byte var x9158 [1 << 17]byte var x9159 [1 << 17]byte var x9160 [1 << 17]byte var x9161 [1 << 17]byte var x9162 [1 << 17]byte var x9163 [1 << 17]byte var x9164 [1 << 17]byte var x9165 [1 << 17]byte var x9166 [1 << 17]byte var x9167 [1 << 17]byte var x9168 [1 << 17]byte var x9169 [1 << 17]byte var x9170 [1 << 17]byte var x9171 [1 << 17]byte var x9172 [1 << 17]byte var x9173 [1 << 17]byte var x9174 [1 << 17]byte var x9175 [1 << 17]byte var x9176 [1 << 17]byte var x9177 [1 << 17]byte var x9178 [1 << 17]byte var x9179 [1 << 17]byte var x9180 [1 << 17]byte var x9181 [1 << 17]byte var x9182 [1 << 17]byte var x9183 [1 << 17]byte var x9184 [1 << 17]byte var x9185 [1 << 17]byte var x9186 [1 << 17]byte var x9187 [1 << 17]byte var x9188 [1 << 17]byte var x9189 [1 << 17]byte var x9190 [1 << 17]byte var x9191 [1 << 17]byte var x9192 [1 << 17]byte var x9193 [1 << 17]byte var x9194 [1 << 17]byte var x9195 [1 << 17]byte var x9196 [1 << 17]byte var x9197 [1 << 17]byte var x9198 [1 << 17]byte var x9199 [1 << 17]byte var x9200 [1 << 17]byte var x9201 [1 << 17]byte var x9202 [1 << 17]byte var x9203 [1 << 17]byte var x9204 [1 << 17]byte var x9205 [1 << 17]byte var x9206 [1 << 17]byte var x9207 [1 << 17]byte var x9208 [1 << 17]byte var x9209 [1 << 17]byte var x9210 [1 << 17]byte var x9211 [1 << 17]byte var x9212 [1 << 17]byte var x9213 [1 << 17]byte var x9214 [1 << 17]byte var x9215 [1 << 17]byte var x9216 [1 << 17]byte var x9217 [1 << 17]byte var x9218 [1 << 17]byte var x9219 [1 << 17]byte var x9220 [1 << 17]byte var x9221 [1 << 17]byte var x9222 [1 << 17]byte var x9223 [1 << 17]byte var x9224 [1 << 17]byte var x9225 [1 << 17]byte var x9226 [1 << 17]byte var x9227 [1 << 17]byte var x9228 [1 << 17]byte var x9229 [1 << 17]byte var x9230 [1 << 17]byte var x9231 [1 << 17]byte var x9232 [1 << 17]byte var x9233 [1 << 17]byte var x9234 [1 << 17]byte var x9235 [1 << 17]byte var x9236 [1 << 17]byte var x9237 [1 << 17]byte var x9238 [1 << 17]byte var x9239 [1 << 17]byte var x9240 [1 << 17]byte var x9241 [1 << 17]byte var x9242 [1 << 17]byte var x9243 [1 << 17]byte var x9244 [1 << 17]byte var x9245 [1 << 17]byte var x9246 [1 << 17]byte var x9247 [1 << 17]byte var x9248 [1 << 17]byte var x9249 [1 << 17]byte var x9250 [1 << 17]byte var x9251 [1 << 17]byte var x9252 [1 << 17]byte var x9253 [1 << 17]byte var x9254 [1 << 17]byte var x9255 [1 << 17]byte var x9256 [1 << 17]byte var x9257 [1 << 17]byte var x9258 [1 << 17]byte var x9259 [1 << 17]byte var x9260 [1 << 17]byte var x9261 [1 << 17]byte var x9262 [1 << 17]byte var x9263 [1 << 17]byte var x9264 [1 << 17]byte var x9265 [1 << 17]byte var x9266 [1 << 17]byte var x9267 [1 << 17]byte var x9268 [1 << 17]byte var x9269 [1 << 17]byte var x9270 [1 << 17]byte var x9271 [1 << 17]byte var x9272 [1 << 17]byte var x9273 [1 << 17]byte var x9274 [1 << 17]byte var x9275 [1 << 17]byte var x9276 [1 << 17]byte var x9277 [1 << 17]byte var x9278 [1 << 17]byte var x9279 [1 << 17]byte var x9280 [1 << 17]byte var x9281 [1 << 17]byte var x9282 [1 << 17]byte var x9283 [1 << 17]byte var x9284 [1 << 17]byte var x9285 [1 << 17]byte var x9286 [1 << 17]byte var x9287 [1 << 17]byte var x9288 [1 << 17]byte var x9289 [1 << 17]byte var x9290 [1 << 17]byte var x9291 [1 << 17]byte var x9292 [1 << 17]byte var x9293 [1 << 17]byte var x9294 [1 << 17]byte var x9295 [1 << 17]byte var x9296 [1 << 17]byte var x9297 [1 << 17]byte var x9298 [1 << 17]byte var x9299 [1 << 17]byte var x9300 [1 << 17]byte var x9301 [1 << 17]byte var x9302 [1 << 17]byte var x9303 [1 << 17]byte var x9304 [1 << 17]byte var x9305 [1 << 17]byte var x9306 [1 << 17]byte var x9307 [1 << 17]byte var x9308 [1 << 17]byte var x9309 [1 << 17]byte var x9310 [1 << 17]byte var x9311 [1 << 17]byte var x9312 [1 << 17]byte var x9313 [1 << 17]byte var x9314 [1 << 17]byte var x9315 [1 << 17]byte var x9316 [1 << 17]byte var x9317 [1 << 17]byte var x9318 [1 << 17]byte var x9319 [1 << 17]byte var x9320 [1 << 17]byte var x9321 [1 << 17]byte var x9322 [1 << 17]byte var x9323 [1 << 17]byte var x9324 [1 << 17]byte var x9325 [1 << 17]byte var x9326 [1 << 17]byte var x9327 [1 << 17]byte var x9328 [1 << 17]byte var x9329 [1 << 17]byte var x9330 [1 << 17]byte var x9331 [1 << 17]byte var x9332 [1 << 17]byte var x9333 [1 << 17]byte var x9334 [1 << 17]byte var x9335 [1 << 17]byte var x9336 [1 << 17]byte var x9337 [1 << 17]byte var x9338 [1 << 17]byte var x9339 [1 << 17]byte var x9340 [1 << 17]byte var x9341 [1 << 17]byte var x9342 [1 << 17]byte var x9343 [1 << 17]byte var x9344 [1 << 17]byte var x9345 [1 << 17]byte var x9346 [1 << 17]byte var x9347 [1 << 17]byte var x9348 [1 << 17]byte var x9349 [1 << 17]byte var x9350 [1 << 17]byte var x9351 [1 << 17]byte var x9352 [1 << 17]byte var x9353 [1 << 17]byte var x9354 [1 << 17]byte var x9355 [1 << 17]byte var x9356 [1 << 17]byte var x9357 [1 << 17]byte var x9358 [1 << 17]byte var x9359 [1 << 17]byte var x9360 [1 << 17]byte var x9361 [1 << 17]byte var x9362 [1 << 17]byte var x9363 [1 << 17]byte var x9364 [1 << 17]byte var x9365 [1 << 17]byte var x9366 [1 << 17]byte var x9367 [1 << 17]byte var x9368 [1 << 17]byte var x9369 [1 << 17]byte var x9370 [1 << 17]byte var x9371 [1 << 17]byte var x9372 [1 << 17]byte var x9373 [1 << 17]byte var x9374 [1 << 17]byte var x9375 [1 << 17]byte var x9376 [1 << 17]byte var x9377 [1 << 17]byte var x9378 [1 << 17]byte var x9379 [1 << 17]byte var x9380 [1 << 17]byte var x9381 [1 << 17]byte var x9382 [1 << 17]byte var x9383 [1 << 17]byte var x9384 [1 << 17]byte var x9385 [1 << 17]byte var x9386 [1 << 17]byte var x9387 [1 << 17]byte var x9388 [1 << 17]byte var x9389 [1 << 17]byte var x9390 [1 << 17]byte var x9391 [1 << 17]byte var x9392 [1 << 17]byte var x9393 [1 << 17]byte var x9394 [1 << 17]byte var x9395 [1 << 17]byte var x9396 [1 << 17]byte var x9397 [1 << 17]byte var x9398 [1 << 17]byte var x9399 [1 << 17]byte var x9400 [1 << 17]byte var x9401 [1 << 17]byte var x9402 [1 << 17]byte var x9403 [1 << 17]byte var x9404 [1 << 17]byte var x9405 [1 << 17]byte var x9406 [1 << 17]byte var x9407 [1 << 17]byte var x9408 [1 << 17]byte var x9409 [1 << 17]byte var x9410 [1 << 17]byte var x9411 [1 << 17]byte var x9412 [1 << 17]byte var x9413 [1 << 17]byte var x9414 [1 << 17]byte var x9415 [1 << 17]byte var x9416 [1 << 17]byte var x9417 [1 << 17]byte var x9418 [1 << 17]byte var x9419 [1 << 17]byte var x9420 [1 << 17]byte var x9421 [1 << 17]byte var x9422 [1 << 17]byte var x9423 [1 << 17]byte var x9424 [1 << 17]byte var x9425 [1 << 17]byte var x9426 [1 << 17]byte var x9427 [1 << 17]byte var x9428 [1 << 17]byte var x9429 [1 << 17]byte var x9430 [1 << 17]byte var x9431 [1 << 17]byte var x9432 [1 << 17]byte var x9433 [1 << 17]byte var x9434 [1 << 17]byte var x9435 [1 << 17]byte var x9436 [1 << 17]byte var x9437 [1 << 17]byte var x9438 [1 << 17]byte var x9439 [1 << 17]byte var x9440 [1 << 17]byte var x9441 [1 << 17]byte var x9442 [1 << 17]byte var x9443 [1 << 17]byte var x9444 [1 << 17]byte var x9445 [1 << 17]byte var x9446 [1 << 17]byte var x9447 [1 << 17]byte var x9448 [1 << 17]byte var x9449 [1 << 17]byte var x9450 [1 << 17]byte var x9451 [1 << 17]byte var x9452 [1 << 17]byte var x9453 [1 << 17]byte var x9454 [1 << 17]byte var x9455 [1 << 17]byte var x9456 [1 << 17]byte var x9457 [1 << 17]byte var x9458 [1 << 17]byte var x9459 [1 << 17]byte var x9460 [1 << 17]byte var x9461 [1 << 17]byte var x9462 [1 << 17]byte var x9463 [1 << 17]byte var x9464 [1 << 17]byte var x9465 [1 << 17]byte var x9466 [1 << 17]byte var x9467 [1 << 17]byte var x9468 [1 << 17]byte var x9469 [1 << 17]byte var x9470 [1 << 17]byte var x9471 [1 << 17]byte var x9472 [1 << 17]byte var x9473 [1 << 17]byte var x9474 [1 << 17]byte var x9475 [1 << 17]byte var x9476 [1 << 17]byte var x9477 [1 << 17]byte var x9478 [1 << 17]byte var x9479 [1 << 17]byte var x9480 [1 << 17]byte var x9481 [1 << 17]byte var x9482 [1 << 17]byte var x9483 [1 << 17]byte var x9484 [1 << 17]byte var x9485 [1 << 17]byte var x9486 [1 << 17]byte var x9487 [1 << 17]byte var x9488 [1 << 17]byte var x9489 [1 << 17]byte var x9490 [1 << 17]byte var x9491 [1 << 17]byte var x9492 [1 << 17]byte var x9493 [1 << 17]byte var x9494 [1 << 17]byte var x9495 [1 << 17]byte var x9496 [1 << 17]byte var x9497 [1 << 17]byte var x9498 [1 << 17]byte var x9499 [1 << 17]byte var x9500 [1 << 17]byte var x9501 [1 << 17]byte var x9502 [1 << 17]byte var x9503 [1 << 17]byte var x9504 [1 << 17]byte var x9505 [1 << 17]byte var x9506 [1 << 17]byte var x9507 [1 << 17]byte var x9508 [1 << 17]byte var x9509 [1 << 17]byte var x9510 [1 << 17]byte var x9511 [1 << 17]byte var x9512 [1 << 17]byte var x9513 [1 << 17]byte var x9514 [1 << 17]byte var x9515 [1 << 17]byte var x9516 [1 << 17]byte var x9517 [1 << 17]byte var x9518 [1 << 17]byte var x9519 [1 << 17]byte var x9520 [1 << 17]byte var x9521 [1 << 17]byte var x9522 [1 << 17]byte var x9523 [1 << 17]byte var x9524 [1 << 17]byte var x9525 [1 << 17]byte var x9526 [1 << 17]byte var x9527 [1 << 17]byte var x9528 [1 << 17]byte var x9529 [1 << 17]byte var x9530 [1 << 17]byte var x9531 [1 << 17]byte var x9532 [1 << 17]byte var x9533 [1 << 17]byte var x9534 [1 << 17]byte var x9535 [1 << 17]byte var x9536 [1 << 17]byte var x9537 [1 << 17]byte var x9538 [1 << 17]byte var x9539 [1 << 17]byte var x9540 [1 << 17]byte var x9541 [1 << 17]byte var x9542 [1 << 17]byte var x9543 [1 << 17]byte var x9544 [1 << 17]byte var x9545 [1 << 17]byte var x9546 [1 << 17]byte var x9547 [1 << 17]byte var x9548 [1 << 17]byte var x9549 [1 << 17]byte var x9550 [1 << 17]byte var x9551 [1 << 17]byte var x9552 [1 << 17]byte var x9553 [1 << 17]byte var x9554 [1 << 17]byte var x9555 [1 << 17]byte var x9556 [1 << 17]byte var x9557 [1 << 17]byte var x9558 [1 << 17]byte var x9559 [1 << 17]byte var x9560 [1 << 17]byte var x9561 [1 << 17]byte var x9562 [1 << 17]byte var x9563 [1 << 17]byte var x9564 [1 << 17]byte var x9565 [1 << 17]byte var x9566 [1 << 17]byte var x9567 [1 << 17]byte var x9568 [1 << 17]byte var x9569 [1 << 17]byte var x9570 [1 << 17]byte var x9571 [1 << 17]byte var x9572 [1 << 17]byte var x9573 [1 << 17]byte var x9574 [1 << 17]byte var x9575 [1 << 17]byte var x9576 [1 << 17]byte var x9577 [1 << 17]byte var x9578 [1 << 17]byte var x9579 [1 << 17]byte var x9580 [1 << 17]byte var x9581 [1 << 17]byte var x9582 [1 << 17]byte var x9583 [1 << 17]byte var x9584 [1 << 17]byte var x9585 [1 << 17]byte var x9586 [1 << 17]byte var x9587 [1 << 17]byte var x9588 [1 << 17]byte var x9589 [1 << 17]byte var x9590 [1 << 17]byte var x9591 [1 << 17]byte var x9592 [1 << 17]byte var x9593 [1 << 17]byte var x9594 [1 << 17]byte var x9595 [1 << 17]byte var x9596 [1 << 17]byte var x9597 [1 << 17]byte var x9598 [1 << 17]byte var x9599 [1 << 17]byte var x9600 [1 << 17]byte var x9601 [1 << 17]byte var x9602 [1 << 17]byte var x9603 [1 << 17]byte var x9604 [1 << 17]byte var x9605 [1 << 17]byte var x9606 [1 << 17]byte var x9607 [1 << 17]byte var x9608 [1 << 17]byte var x9609 [1 << 17]byte var x9610 [1 << 17]byte var x9611 [1 << 17]byte var x9612 [1 << 17]byte var x9613 [1 << 17]byte var x9614 [1 << 17]byte var x9615 [1 << 17]byte var x9616 [1 << 17]byte var x9617 [1 << 17]byte var x9618 [1 << 17]byte var x9619 [1 << 17]byte var x9620 [1 << 17]byte var x9621 [1 << 17]byte var x9622 [1 << 17]byte var x9623 [1 << 17]byte var x9624 [1 << 17]byte var x9625 [1 << 17]byte var x9626 [1 << 17]byte var x9627 [1 << 17]byte var x9628 [1 << 17]byte var x9629 [1 << 17]byte var x9630 [1 << 17]byte var x9631 [1 << 17]byte var x9632 [1 << 17]byte var x9633 [1 << 17]byte var x9634 [1 << 17]byte var x9635 [1 << 17]byte var x9636 [1 << 17]byte var x9637 [1 << 17]byte var x9638 [1 << 17]byte var x9639 [1 << 17]byte var x9640 [1 << 17]byte var x9641 [1 << 17]byte var x9642 [1 << 17]byte var x9643 [1 << 17]byte var x9644 [1 << 17]byte var x9645 [1 << 17]byte var x9646 [1 << 17]byte var x9647 [1 << 17]byte var x9648 [1 << 17]byte var x9649 [1 << 17]byte var x9650 [1 << 17]byte var x9651 [1 << 17]byte var x9652 [1 << 17]byte var x9653 [1 << 17]byte var x9654 [1 << 17]byte var x9655 [1 << 17]byte var x9656 [1 << 17]byte var x9657 [1 << 17]byte var x9658 [1 << 17]byte var x9659 [1 << 17]byte var x9660 [1 << 17]byte var x9661 [1 << 17]byte var x9662 [1 << 17]byte var x9663 [1 << 17]byte var x9664 [1 << 17]byte var x9665 [1 << 17]byte var x9666 [1 << 17]byte var x9667 [1 << 17]byte var x9668 [1 << 17]byte var x9669 [1 << 17]byte var x9670 [1 << 17]byte var x9671 [1 << 17]byte var x9672 [1 << 17]byte var x9673 [1 << 17]byte var x9674 [1 << 17]byte var x9675 [1 << 17]byte var x9676 [1 << 17]byte var x9677 [1 << 17]byte var x9678 [1 << 17]byte var x9679 [1 << 17]byte var x9680 [1 << 17]byte var x9681 [1 << 17]byte var x9682 [1 << 17]byte var x9683 [1 << 17]byte var x9684 [1 << 17]byte var x9685 [1 << 17]byte var x9686 [1 << 17]byte var x9687 [1 << 17]byte var x9688 [1 << 17]byte var x9689 [1 << 17]byte var x9690 [1 << 17]byte var x9691 [1 << 17]byte var x9692 [1 << 17]byte var x9693 [1 << 17]byte var x9694 [1 << 17]byte var x9695 [1 << 17]byte var x9696 [1 << 17]byte var x9697 [1 << 17]byte var x9698 [1 << 17]byte var x9699 [1 << 17]byte var x9700 [1 << 17]byte var x9701 [1 << 17]byte var x9702 [1 << 17]byte var x9703 [1 << 17]byte var x9704 [1 << 17]byte var x9705 [1 << 17]byte var x9706 [1 << 17]byte var x9707 [1 << 17]byte var x9708 [1 << 17]byte var x9709 [1 << 17]byte var x9710 [1 << 17]byte var x9711 [1 << 17]byte var x9712 [1 << 17]byte var x9713 [1 << 17]byte var x9714 [1 << 17]byte var x9715 [1 << 17]byte var x9716 [1 << 17]byte var x9717 [1 << 17]byte var x9718 [1 << 17]byte var x9719 [1 << 17]byte var x9720 [1 << 17]byte var x9721 [1 << 17]byte var x9722 [1 << 17]byte var x9723 [1 << 17]byte var x9724 [1 << 17]byte var x9725 [1 << 17]byte var x9726 [1 << 17]byte var x9727 [1 << 17]byte var x9728 [1 << 17]byte var x9729 [1 << 17]byte var x9730 [1 << 17]byte var x9731 [1 << 17]byte var x9732 [1 << 17]byte var x9733 [1 << 17]byte var x9734 [1 << 17]byte var x9735 [1 << 17]byte var x9736 [1 << 17]byte var x9737 [1 << 17]byte var x9738 [1 << 17]byte var x9739 [1 << 17]byte var x9740 [1 << 17]byte var x9741 [1 << 17]byte var x9742 [1 << 17]byte var x9743 [1 << 17]byte var x9744 [1 << 17]byte var x9745 [1 << 17]byte var x9746 [1 << 17]byte var x9747 [1 << 17]byte var x9748 [1 << 17]byte var x9749 [1 << 17]byte var x9750 [1 << 17]byte var x9751 [1 << 17]byte var x9752 [1 << 17]byte var x9753 [1 << 17]byte var x9754 [1 << 17]byte var x9755 [1 << 17]byte var x9756 [1 << 17]byte var x9757 [1 << 17]byte var x9758 [1 << 17]byte var x9759 [1 << 17]byte var x9760 [1 << 17]byte var x9761 [1 << 17]byte var x9762 [1 << 17]byte var x9763 [1 << 17]byte var x9764 [1 << 17]byte var x9765 [1 << 17]byte var x9766 [1 << 17]byte var x9767 [1 << 17]byte var x9768 [1 << 17]byte var x9769 [1 << 17]byte var x9770 [1 << 17]byte var x9771 [1 << 17]byte var x9772 [1 << 17]byte var x9773 [1 << 17]byte var x9774 [1 << 17]byte var x9775 [1 << 17]byte var x9776 [1 << 17]byte var x9777 [1 << 17]byte var x9778 [1 << 17]byte var x9779 [1 << 17]byte var x9780 [1 << 17]byte var x9781 [1 << 17]byte var x9782 [1 << 17]byte var x9783 [1 << 17]byte var x9784 [1 << 17]byte var x9785 [1 << 17]byte var x9786 [1 << 17]byte var x9787 [1 << 17]byte var x9788 [1 << 17]byte var x9789 [1 << 17]byte var x9790 [1 << 17]byte var x9791 [1 << 17]byte var x9792 [1 << 17]byte var x9793 [1 << 17]byte var x9794 [1 << 17]byte var x9795 [1 << 17]byte var x9796 [1 << 17]byte var x9797 [1 << 17]byte var x9798 [1 << 17]byte var x9799 [1 << 17]byte var x9800 [1 << 17]byte var x9801 [1 << 17]byte var x9802 [1 << 17]byte var x9803 [1 << 17]byte var x9804 [1 << 17]byte var x9805 [1 << 17]byte var x9806 [1 << 17]byte var x9807 [1 << 17]byte var x9808 [1 << 17]byte var x9809 [1 << 17]byte var x9810 [1 << 17]byte var x9811 [1 << 17]byte var x9812 [1 << 17]byte var x9813 [1 << 17]byte var x9814 [1 << 17]byte var x9815 [1 << 17]byte var x9816 [1 << 17]byte var x9817 [1 << 17]byte var x9818 [1 << 17]byte var x9819 [1 << 17]byte var x9820 [1 << 17]byte var x9821 [1 << 17]byte var x9822 [1 << 17]byte var x9823 [1 << 17]byte var x9824 [1 << 17]byte var x9825 [1 << 17]byte var x9826 [1 << 17]byte var x9827 [1 << 17]byte var x9828 [1 << 17]byte var x9829 [1 << 17]byte var x9830 [1 << 17]byte var x9831 [1 << 17]byte var x9832 [1 << 17]byte var x9833 [1 << 17]byte var x9834 [1 << 17]byte var x9835 [1 << 17]byte var x9836 [1 << 17]byte var x9837 [1 << 17]byte var x9838 [1 << 17]byte var x9839 [1 << 17]byte var x9840 [1 << 17]byte var x9841 [1 << 17]byte var x9842 [1 << 17]byte var x9843 [1 << 17]byte var x9844 [1 << 17]byte var x9845 [1 << 17]byte var x9846 [1 << 17]byte var x9847 [1 << 17]byte var x9848 [1 << 17]byte var x9849 [1 << 17]byte var x9850 [1 << 17]byte var x9851 [1 << 17]byte var x9852 [1 << 17]byte var x9853 [1 << 17]byte var x9854 [1 << 17]byte var x9855 [1 << 17]byte var x9856 [1 << 17]byte var x9857 [1 << 17]byte var x9858 [1 << 17]byte var x9859 [1 << 17]byte var x9860 [1 << 17]byte var x9861 [1 << 17]byte var x9862 [1 << 17]byte var x9863 [1 << 17]byte var x9864 [1 << 17]byte var x9865 [1 << 17]byte var x9866 [1 << 17]byte var x9867 [1 << 17]byte var x9868 [1 << 17]byte var x9869 [1 << 17]byte var x9870 [1 << 17]byte var x9871 [1 << 17]byte var x9872 [1 << 17]byte var x9873 [1 << 17]byte var x9874 [1 << 17]byte var x9875 [1 << 17]byte var x9876 [1 << 17]byte var x9877 [1 << 17]byte var x9878 [1 << 17]byte var x9879 [1 << 17]byte var x9880 [1 << 17]byte var x9881 [1 << 17]byte var x9882 [1 << 17]byte var x9883 [1 << 17]byte var x9884 [1 << 17]byte var x9885 [1 << 17]byte var x9886 [1 << 17]byte var x9887 [1 << 17]byte var x9888 [1 << 17]byte var x9889 [1 << 17]byte var x9890 [1 << 17]byte var x9891 [1 << 17]byte var x9892 [1 << 17]byte var x9893 [1 << 17]byte var x9894 [1 << 17]byte var x9895 [1 << 17]byte var x9896 [1 << 17]byte var x9897 [1 << 17]byte var x9898 [1 << 17]byte var x9899 [1 << 17]byte var x9900 [1 << 17]byte var x9901 [1 << 17]byte var x9902 [1 << 17]byte var x9903 [1 << 17]byte var x9904 [1 << 17]byte var x9905 [1 << 17]byte var x9906 [1 << 17]byte var x9907 [1 << 17]byte var x9908 [1 << 17]byte var x9909 [1 << 17]byte var x9910 [1 << 17]byte var x9911 [1 << 17]byte var x9912 [1 << 17]byte var x9913 [1 << 17]byte var x9914 [1 << 17]byte var x9915 [1 << 17]byte var x9916 [1 << 17]byte var x9917 [1 << 17]byte var x9918 [1 << 17]byte var x9919 [1 << 17]byte var x9920 [1 << 17]byte var x9921 [1 << 17]byte var x9922 [1 << 17]byte var x9923 [1 << 17]byte var x9924 [1 << 17]byte var x9925 [1 << 17]byte var x9926 [1 << 17]byte var x9927 [1 << 17]byte var x9928 [1 << 17]byte var x9929 [1 << 17]byte var x9930 [1 << 17]byte var x9931 [1 << 17]byte var x9932 [1 << 17]byte var x9933 [1 << 17]byte var x9934 [1 << 17]byte var x9935 [1 << 17]byte var x9936 [1 << 17]byte var x9937 [1 << 17]byte var x9938 [1 << 17]byte var x9939 [1 << 17]byte var x9940 [1 << 17]byte var x9941 [1 << 17]byte var x9942 [1 << 17]byte var x9943 [1 << 17]byte var x9944 [1 << 17]byte var x9945 [1 << 17]byte var x9946 [1 << 17]byte var x9947 [1 << 17]byte var x9948 [1 << 17]byte var x9949 [1 << 17]byte var x9950 [1 << 17]byte var x9951 [1 << 17]byte var x9952 [1 << 17]byte var x9953 [1 << 17]byte var x9954 [1 << 17]byte var x9955 [1 << 17]byte var x9956 [1 << 17]byte var x9957 [1 << 17]byte var x9958 [1 << 17]byte var x9959 [1 << 17]byte var x9960 [1 << 17]byte var x9961 [1 << 17]byte var x9962 [1 << 17]byte var x9963 [1 << 17]byte var x9964 [1 << 17]byte var x9965 [1 << 17]byte var x9966 [1 << 17]byte var x9967 [1 << 17]byte var x9968 [1 << 17]byte var x9969 [1 << 17]byte var x9970 [1 << 17]byte var x9971 [1 << 17]byte var x9972 [1 << 17]byte var x9973 [1 << 17]byte var x9974 [1 << 17]byte var x9975 [1 << 17]byte var x9976 [1 << 17]byte var x9977 [1 << 17]byte var x9978 [1 << 17]byte var x9979 [1 << 17]byte var x9980 [1 << 17]byte var x9981 [1 << 17]byte var x9982 [1 << 17]byte var x9983 [1 << 17]byte var x9984 [1 << 17]byte var x9985 [1 << 17]byte var x9986 [1 << 17]byte var x9987 [1 << 17]byte var x9988 [1 << 17]byte var x9989 [1 << 17]byte var x9990 [1 << 17]byte var x9991 [1 << 17]byte var x9992 [1 << 17]byte var x9993 [1 << 17]byte var x9994 [1 << 17]byte var x9995 [1 << 17]byte var x9996 [1 << 17]byte var x9997 [1 << 17]byte var x9998 [1 << 17]byte var x9999 [1 << 17]byte var x10000 [1 << 17]byte var x10001 [1 << 17]byte var x10002 [1 << 17]byte var x10003 [1 << 17]byte var x10004 [1 << 17]byte var x10005 [1 << 17]byte var x10006 [1 << 17]byte var x10007 [1 << 17]byte var x10008 [1 << 17]byte var x10009 [1 << 17]byte var x10010 [1 << 17]byte var x10011 [1 << 17]byte var x10012 [1 << 17]byte var x10013 [1 << 17]byte var x10014 [1 << 17]byte var x10015 [1 << 17]byte var x10016 [1 << 17]byte var x10017 [1 << 17]byte var x10018 [1 << 17]byte var x10019 [1 << 17]byte var x10020 [1 << 17]byte var x10021 [1 << 17]byte var x10022 [1 << 17]byte var x10023 [1 << 17]byte var x10024 [1 << 17]byte var x10025 [1 << 17]byte var x10026 [1 << 17]byte var x10027 [1 << 17]byte var x10028 [1 << 17]byte var x10029 [1 << 17]byte var x10030 [1 << 17]byte var x10031 [1 << 17]byte var x10032 [1 << 17]byte var x10033 [1 << 17]byte var x10034 [1 << 17]byte var x10035 [1 << 17]byte var x10036 [1 << 17]byte var x10037 [1 << 17]byte var x10038 [1 << 17]byte var x10039 [1 << 17]byte var x10040 [1 << 17]byte var x10041 [1 << 17]byte var x10042 [1 << 17]byte var x10043 [1 << 17]byte var x10044 [1 << 17]byte var x10045 [1 << 17]byte var x10046 [1 << 17]byte var x10047 [1 << 17]byte var x10048 [1 << 17]byte var x10049 [1 << 17]byte var x10050 [1 << 17]byte var x10051 [1 << 17]byte var x10052 [1 << 17]byte var x10053 [1 << 17]byte var x10054 [1 << 17]byte var x10055 [1 << 17]byte var x10056 [1 << 17]byte var x10057 [1 << 17]byte var x10058 [1 << 17]byte var x10059 [1 << 17]byte var x10060 [1 << 17]byte var x10061 [1 << 17]byte var x10062 [1 << 17]byte var x10063 [1 << 17]byte var x10064 [1 << 17]byte var x10065 [1 << 17]byte var x10066 [1 << 17]byte var x10067 [1 << 17]byte var x10068 [1 << 17]byte var x10069 [1 << 17]byte var x10070 [1 << 17]byte var x10071 [1 << 17]byte var x10072 [1 << 17]byte var x10073 [1 << 17]byte var x10074 [1 << 17]byte var x10075 [1 << 17]byte var x10076 [1 << 17]byte var x10077 [1 << 17]byte var x10078 [1 << 17]byte var x10079 [1 << 17]byte var x10080 [1 << 17]byte var x10081 [1 << 17]byte var x10082 [1 << 17]byte var x10083 [1 << 17]byte var x10084 [1 << 17]byte var x10085 [1 << 17]byte var x10086 [1 << 17]byte var x10087 [1 << 17]byte var x10088 [1 << 17]byte var x10089 [1 << 17]byte var x10090 [1 << 17]byte var x10091 [1 << 17]byte var x10092 [1 << 17]byte var x10093 [1 << 17]byte var x10094 [1 << 17]byte var x10095 [1 << 17]byte var x10096 [1 << 17]byte var x10097 [1 << 17]byte var x10098 [1 << 17]byte var x10099 [1 << 17]byte var x10100 [1 << 17]byte var x10101 [1 << 17]byte var x10102 [1 << 17]byte var x10103 [1 << 17]byte var x10104 [1 << 17]byte var x10105 [1 << 17]byte var x10106 [1 << 17]byte var x10107 [1 << 17]byte var x10108 [1 << 17]byte var x10109 [1 << 17]byte var x10110 [1 << 17]byte var x10111 [1 << 17]byte var x10112 [1 << 17]byte var x10113 [1 << 17]byte var x10114 [1 << 17]byte var x10115 [1 << 17]byte var x10116 [1 << 17]byte var x10117 [1 << 17]byte var x10118 [1 << 17]byte var x10119 [1 << 17]byte var x10120 [1 << 17]byte var x10121 [1 << 17]byte var x10122 [1 << 17]byte var x10123 [1 << 17]byte var x10124 [1 << 17]byte var x10125 [1 << 17]byte var x10126 [1 << 17]byte var x10127 [1 << 17]byte var x10128 [1 << 17]byte var x10129 [1 << 17]byte var x10130 [1 << 17]byte var x10131 [1 << 17]byte var x10132 [1 << 17]byte var x10133 [1 << 17]byte var x10134 [1 << 17]byte var x10135 [1 << 17]byte var x10136 [1 << 17]byte var x10137 [1 << 17]byte var x10138 [1 << 17]byte var x10139 [1 << 17]byte var x10140 [1 << 17]byte var x10141 [1 << 17]byte var x10142 [1 << 17]byte var x10143 [1 << 17]byte var x10144 [1 << 17]byte var x10145 [1 << 17]byte var x10146 [1 << 17]byte var x10147 [1 << 17]byte var x10148 [1 << 17]byte var x10149 [1 << 17]byte var x10150 [1 << 17]byte var x10151 [1 << 17]byte var x10152 [1 << 17]byte var x10153 [1 << 17]byte var x10154 [1 << 17]byte var x10155 [1 << 17]byte var x10156 [1 << 17]byte var x10157 [1 << 17]byte var x10158 [1 << 17]byte var x10159 [1 << 17]byte var x10160 [1 << 17]byte var x10161 [1 << 17]byte var x10162 [1 << 17]byte var x10163 [1 << 17]byte var x10164 [1 << 17]byte var x10165 [1 << 17]byte var x10166 [1 << 17]byte var x10167 [1 << 17]byte var x10168 [1 << 17]byte var x10169 [1 << 17]byte var x10170 [1 << 17]byte var x10171 [1 << 17]byte var x10172 [1 << 17]byte var x10173 [1 << 17]byte var x10174 [1 << 17]byte var x10175 [1 << 17]byte var x10176 [1 << 17]byte var x10177 [1 << 17]byte var x10178 [1 << 17]byte var x10179 [1 << 17]byte var x10180 [1 << 17]byte var x10181 [1 << 17]byte var x10182 [1 << 17]byte var x10183 [1 << 17]byte var x10184 [1 << 17]byte var x10185 [1 << 17]byte var x10186 [1 << 17]byte var x10187 [1 << 17]byte var x10188 [1 << 17]byte var x10189 [1 << 17]byte var x10190 [1 << 17]byte var x10191 [1 << 17]byte var x10192 [1 << 17]byte var x10193 [1 << 17]byte var x10194 [1 << 17]byte var x10195 [1 << 17]byte var x10196 [1 << 17]byte var x10197 [1 << 17]byte var x10198 [1 << 17]byte var x10199 [1 << 17]byte var x10200 [1 << 17]byte var x10201 [1 << 17]byte var x10202 [1 << 17]byte var x10203 [1 << 17]byte var x10204 [1 << 17]byte var x10205 [1 << 17]byte var x10206 [1 << 17]byte var x10207 [1 << 17]byte var x10208 [1 << 17]byte var x10209 [1 << 17]byte var x10210 [1 << 17]byte var x10211 [1 << 17]byte var x10212 [1 << 17]byte var x10213 [1 << 17]byte var x10214 [1 << 17]byte var x10215 [1 << 17]byte var x10216 [1 << 17]byte var x10217 [1 << 17]byte var x10218 [1 << 17]byte var x10219 [1 << 17]byte var x10220 [1 << 17]byte var x10221 [1 << 17]byte var x10222 [1 << 17]byte var x10223 [1 << 17]byte var x10224 [1 << 17]byte var x10225 [1 << 17]byte var x10226 [1 << 17]byte var x10227 [1 << 17]byte var x10228 [1 << 17]byte var x10229 [1 << 17]byte var x10230 [1 << 17]byte var x10231 [1 << 17]byte var x10232 [1 << 17]byte var x10233 [1 << 17]byte var x10234 [1 << 17]byte var x10235 [1 << 17]byte var x10236 [1 << 17]byte var x10237 [1 << 17]byte var x10238 [1 << 17]byte var x10239 [1 << 17]byte var x10240 [1 << 17]byte var x10241 [1 << 17]byte var x10242 [1 << 17]byte var x10243 [1 << 17]byte var x10244 [1 << 17]byte var x10245 [1 << 17]byte var x10246 [1 << 17]byte var x10247 [1 << 17]byte var x10248 [1 << 17]byte var x10249 [1 << 17]byte var x10250 [1 << 17]byte var x10251 [1 << 17]byte var x10252 [1 << 17]byte var x10253 [1 << 17]byte var x10254 [1 << 17]byte var x10255 [1 << 17]byte var x10256 [1 << 17]byte var x10257 [1 << 17]byte var x10258 [1 << 17]byte var x10259 [1 << 17]byte var x10260 [1 << 17]byte var x10261 [1 << 17]byte var x10262 [1 << 17]byte var x10263 [1 << 17]byte var x10264 [1 << 17]byte var x10265 [1 << 17]byte var x10266 [1 << 17]byte var x10267 [1 << 17]byte var x10268 [1 << 17]byte var x10269 [1 << 17]byte var x10270 [1 << 17]byte var x10271 [1 << 17]byte var x10272 [1 << 17]byte var x10273 [1 << 17]byte var x10274 [1 << 17]byte var x10275 [1 << 17]byte var x10276 [1 << 17]byte var x10277 [1 << 17]byte var x10278 [1 << 17]byte var x10279 [1 << 17]byte var x10280 [1 << 17]byte var x10281 [1 << 17]byte var x10282 [1 << 17]byte var x10283 [1 << 17]byte var x10284 [1 << 17]byte var x10285 [1 << 17]byte var x10286 [1 << 17]byte var x10287 [1 << 17]byte var x10288 [1 << 17]byte var x10289 [1 << 17]byte var x10290 [1 << 17]byte var x10291 [1 << 17]byte var x10292 [1 << 17]byte var x10293 [1 << 17]byte var x10294 [1 << 17]byte var x10295 [1 << 17]byte var x10296 [1 << 17]byte var x10297 [1 << 17]byte var x10298 [1 << 17]byte var x10299 [1 << 17]byte var x10300 [1 << 17]byte var x10301 [1 << 17]byte var x10302 [1 << 17]byte var x10303 [1 << 17]byte var x10304 [1 << 17]byte var x10305 [1 << 17]byte var x10306 [1 << 17]byte var x10307 [1 << 17]byte var x10308 [1 << 17]byte var x10309 [1 << 17]byte var x10310 [1 << 17]byte var x10311 [1 << 17]byte var x10312 [1 << 17]byte var x10313 [1 << 17]byte var x10314 [1 << 17]byte var x10315 [1 << 17]byte var x10316 [1 << 17]byte var x10317 [1 << 17]byte var x10318 [1 << 17]byte var x10319 [1 << 17]byte var x10320 [1 << 17]byte var x10321 [1 << 17]byte var x10322 [1 << 17]byte var x10323 [1 << 17]byte var x10324 [1 << 17]byte var x10325 [1 << 17]byte var x10326 [1 << 17]byte var x10327 [1 << 17]byte var x10328 [1 << 17]byte var x10329 [1 << 17]byte var x10330 [1 << 17]byte var x10331 [1 << 17]byte var x10332 [1 << 17]byte var x10333 [1 << 17]byte var x10334 [1 << 17]byte var x10335 [1 << 17]byte var x10336 [1 << 17]byte var x10337 [1 << 17]byte var x10338 [1 << 17]byte var x10339 [1 << 17]byte var x10340 [1 << 17]byte var x10341 [1 << 17]byte var x10342 [1 << 17]byte var x10343 [1 << 17]byte var x10344 [1 << 17]byte var x10345 [1 << 17]byte var x10346 [1 << 17]byte var x10347 [1 << 17]byte var x10348 [1 << 17]byte var x10349 [1 << 17]byte var x10350 [1 << 17]byte var x10351 [1 << 17]byte var x10352 [1 << 17]byte var x10353 [1 << 17]byte var x10354 [1 << 17]byte var x10355 [1 << 17]byte var x10356 [1 << 17]byte var x10357 [1 << 17]byte var x10358 [1 << 17]byte var x10359 [1 << 17]byte var x10360 [1 << 17]byte var x10361 [1 << 17]byte var x10362 [1 << 17]byte var x10363 [1 << 17]byte var x10364 [1 << 17]byte var x10365 [1 << 17]byte var x10366 [1 << 17]byte var x10367 [1 << 17]byte var x10368 [1 << 17]byte var x10369 [1 << 17]byte var x10370 [1 << 17]byte var x10371 [1 << 17]byte var x10372 [1 << 17]byte var x10373 [1 << 17]byte var x10374 [1 << 17]byte var x10375 [1 << 17]byte var x10376 [1 << 17]byte var x10377 [1 << 17]byte var x10378 [1 << 17]byte var x10379 [1 << 17]byte var x10380 [1 << 17]byte var x10381 [1 << 17]byte var x10382 [1 << 17]byte var x10383 [1 << 17]byte var x10384 [1 << 17]byte var x10385 [1 << 17]byte var x10386 [1 << 17]byte var x10387 [1 << 17]byte var x10388 [1 << 17]byte var x10389 [1 << 17]byte var x10390 [1 << 17]byte var x10391 [1 << 17]byte var x10392 [1 << 17]byte var x10393 [1 << 17]byte var x10394 [1 << 17]byte var x10395 [1 << 17]byte var x10396 [1 << 17]byte var x10397 [1 << 17]byte var x10398 [1 << 17]byte var x10399 [1 << 17]byte var x10400 [1 << 17]byte var x10401 [1 << 17]byte var x10402 [1 << 17]byte var x10403 [1 << 17]byte var x10404 [1 << 17]byte var x10405 [1 << 17]byte var x10406 [1 << 17]byte var x10407 [1 << 17]byte var x10408 [1 << 17]byte var x10409 [1 << 17]byte var x10410 [1 << 17]byte var x10411 [1 << 17]byte var x10412 [1 << 17]byte var x10413 [1 << 17]byte var x10414 [1 << 17]byte var x10415 [1 << 17]byte var x10416 [1 << 17]byte var x10417 [1 << 17]byte var x10418 [1 << 17]byte var x10419 [1 << 17]byte var x10420 [1 << 17]byte var x10421 [1 << 17]byte var x10422 [1 << 17]byte var x10423 [1 << 17]byte var x10424 [1 << 17]byte var x10425 [1 << 17]byte var x10426 [1 << 17]byte var x10427 [1 << 17]byte var x10428 [1 << 17]byte var x10429 [1 << 17]byte var x10430 [1 << 17]byte var x10431 [1 << 17]byte var x10432 [1 << 17]byte var x10433 [1 << 17]byte var x10434 [1 << 17]byte var x10435 [1 << 17]byte var x10436 [1 << 17]byte var x10437 [1 << 17]byte var x10438 [1 << 17]byte var x10439 [1 << 17]byte var x10440 [1 << 17]byte var x10441 [1 << 17]byte var x10442 [1 << 17]byte var x10443 [1 << 17]byte var x10444 [1 << 17]byte var x10445 [1 << 17]byte var x10446 [1 << 17]byte var x10447 [1 << 17]byte var x10448 [1 << 17]byte var x10449 [1 << 17]byte var x10450 [1 << 17]byte var x10451 [1 << 17]byte var x10452 [1 << 17]byte var x10453 [1 << 17]byte var x10454 [1 << 17]byte var x10455 [1 << 17]byte var x10456 [1 << 17]byte var x10457 [1 << 17]byte var x10458 [1 << 17]byte var x10459 [1 << 17]byte var x10460 [1 << 17]byte var x10461 [1 << 17]byte var x10462 [1 << 17]byte var x10463 [1 << 17]byte var x10464 [1 << 17]byte var x10465 [1 << 17]byte var x10466 [1 << 17]byte var x10467 [1 << 17]byte var x10468 [1 << 17]byte var x10469 [1 << 17]byte var x10470 [1 << 17]byte var x10471 [1 << 17]byte var x10472 [1 << 17]byte var x10473 [1 << 17]byte var x10474 [1 << 17]byte var x10475 [1 << 17]byte var x10476 [1 << 17]byte var x10477 [1 << 17]byte var x10478 [1 << 17]byte var x10479 [1 << 17]byte var x10480 [1 << 17]byte var x10481 [1 << 17]byte var x10482 [1 << 17]byte var x10483 [1 << 17]byte var x10484 [1 << 17]byte var x10485 [1 << 17]byte var x10486 [1 << 17]byte var x10487 [1 << 17]byte var x10488 [1 << 17]byte var x10489 [1 << 17]byte var x10490 [1 << 17]byte var x10491 [1 << 17]byte var x10492 [1 << 17]byte var x10493 [1 << 17]byte var x10494 [1 << 17]byte var x10495 [1 << 17]byte var x10496 [1 << 17]byte var x10497 [1 << 17]byte var x10498 [1 << 17]byte var x10499 [1 << 17]byte var x10500 [1 << 17]byte var x10501 [1 << 17]byte var x10502 [1 << 17]byte var x10503 [1 << 17]byte var x10504 [1 << 17]byte var x10505 [1 << 17]byte var x10506 [1 << 17]byte var x10507 [1 << 17]byte var x10508 [1 << 17]byte var x10509 [1 << 17]byte var x10510 [1 << 17]byte var x10511 [1 << 17]byte var x10512 [1 << 17]byte var x10513 [1 << 17]byte var x10514 [1 << 17]byte var x10515 [1 << 17]byte var x10516 [1 << 17]byte var x10517 [1 << 17]byte var x10518 [1 << 17]byte var x10519 [1 << 17]byte var x10520 [1 << 17]byte var x10521 [1 << 17]byte var x10522 [1 << 17]byte var x10523 [1 << 17]byte var x10524 [1 << 17]byte var x10525 [1 << 17]byte var x10526 [1 << 17]byte var x10527 [1 << 17]byte var x10528 [1 << 17]byte var x10529 [1 << 17]byte var x10530 [1 << 17]byte var x10531 [1 << 17]byte var x10532 [1 << 17]byte var x10533 [1 << 17]byte var x10534 [1 << 17]byte var x10535 [1 << 17]byte var x10536 [1 << 17]byte var x10537 [1 << 17]byte var x10538 [1 << 17]byte var x10539 [1 << 17]byte var x10540 [1 << 17]byte var x10541 [1 << 17]byte var x10542 [1 << 17]byte var x10543 [1 << 17]byte var x10544 [1 << 17]byte var x10545 [1 << 17]byte var x10546 [1 << 17]byte var x10547 [1 << 17]byte var x10548 [1 << 17]byte var x10549 [1 << 17]byte var x10550 [1 << 17]byte var x10551 [1 << 17]byte var x10552 [1 << 17]byte var x10553 [1 << 17]byte var x10554 [1 << 17]byte var x10555 [1 << 17]byte var x10556 [1 << 17]byte var x10557 [1 << 17]byte var x10558 [1 << 17]byte var x10559 [1 << 17]byte var x10560 [1 << 17]byte var x10561 [1 << 17]byte var x10562 [1 << 17]byte var x10563 [1 << 17]byte var x10564 [1 << 17]byte var x10565 [1 << 17]byte var x10566 [1 << 17]byte var x10567 [1 << 17]byte var x10568 [1 << 17]byte var x10569 [1 << 17]byte var x10570 [1 << 17]byte var x10571 [1 << 17]byte var x10572 [1 << 17]byte var x10573 [1 << 17]byte var x10574 [1 << 17]byte var x10575 [1 << 17]byte var x10576 [1 << 17]byte var x10577 [1 << 17]byte var x10578 [1 << 17]byte var x10579 [1 << 17]byte var x10580 [1 << 17]byte var x10581 [1 << 17]byte var x10582 [1 << 17]byte var x10583 [1 << 17]byte var x10584 [1 << 17]byte var x10585 [1 << 17]byte var x10586 [1 << 17]byte var x10587 [1 << 17]byte var x10588 [1 << 17]byte var x10589 [1 << 17]byte var x10590 [1 << 17]byte var x10591 [1 << 17]byte var x10592 [1 << 17]byte var x10593 [1 << 17]byte var x10594 [1 << 17]byte var x10595 [1 << 17]byte var x10596 [1 << 17]byte var x10597 [1 << 17]byte var x10598 [1 << 17]byte var x10599 [1 << 17]byte var x10600 [1 << 17]byte var x10601 [1 << 17]byte var x10602 [1 << 17]byte var x10603 [1 << 17]byte var x10604 [1 << 17]byte var x10605 [1 << 17]byte var x10606 [1 << 17]byte var x10607 [1 << 17]byte var x10608 [1 << 17]byte var x10609 [1 << 17]byte var x10610 [1 << 17]byte var x10611 [1 << 17]byte var x10612 [1 << 17]byte var x10613 [1 << 17]byte var x10614 [1 << 17]byte var x10615 [1 << 17]byte var x10616 [1 << 17]byte var x10617 [1 << 17]byte var x10618 [1 << 17]byte var x10619 [1 << 17]byte var x10620 [1 << 17]byte var x10621 [1 << 17]byte var x10622 [1 << 17]byte var x10623 [1 << 17]byte var x10624 [1 << 17]byte var x10625 [1 << 17]byte var x10626 [1 << 17]byte var x10627 [1 << 17]byte var x10628 [1 << 17]byte var x10629 [1 << 17]byte var x10630 [1 << 17]byte var x10631 [1 << 17]byte var x10632 [1 << 17]byte var x10633 [1 << 17]byte var x10634 [1 << 17]byte var x10635 [1 << 17]byte var x10636 [1 << 17]byte var x10637 [1 << 17]byte var x10638 [1 << 17]byte var x10639 [1 << 17]byte var x10640 [1 << 17]byte var x10641 [1 << 17]byte var x10642 [1 << 17]byte var x10643 [1 << 17]byte var x10644 [1 << 17]byte var x10645 [1 << 17]byte var x10646 [1 << 17]byte var x10647 [1 << 17]byte var x10648 [1 << 17]byte var x10649 [1 << 17]byte var x10650 [1 << 17]byte var x10651 [1 << 17]byte var x10652 [1 << 17]byte var x10653 [1 << 17]byte var x10654 [1 << 17]byte var x10655 [1 << 17]byte var x10656 [1 << 17]byte var x10657 [1 << 17]byte var x10658 [1 << 17]byte var x10659 [1 << 17]byte var x10660 [1 << 17]byte var x10661 [1 << 17]byte var x10662 [1 << 17]byte var x10663 [1 << 17]byte var x10664 [1 << 17]byte var x10665 [1 << 17]byte var x10666 [1 << 17]byte var x10667 [1 << 17]byte var x10668 [1 << 17]byte var x10669 [1 << 17]byte var x10670 [1 << 17]byte var x10671 [1 << 17]byte var x10672 [1 << 17]byte var x10673 [1 << 17]byte var x10674 [1 << 17]byte var x10675 [1 << 17]byte var x10676 [1 << 17]byte var x10677 [1 << 17]byte var x10678 [1 << 17]byte var x10679 [1 << 17]byte var x10680 [1 << 17]byte var x10681 [1 << 17]byte var x10682 [1 << 17]byte var x10683 [1 << 17]byte var x10684 [1 << 17]byte var x10685 [1 << 17]byte var x10686 [1 << 17]byte var x10687 [1 << 17]byte var x10688 [1 << 17]byte var x10689 [1 << 17]byte var x10690 [1 << 17]byte var x10691 [1 << 17]byte var x10692 [1 << 17]byte var x10693 [1 << 17]byte var x10694 [1 << 17]byte var x10695 [1 << 17]byte var x10696 [1 << 17]byte var x10697 [1 << 17]byte var x10698 [1 << 17]byte var x10699 [1 << 17]byte var x10700 [1 << 17]byte var x10701 [1 << 17]byte var x10702 [1 << 17]byte var x10703 [1 << 17]byte var x10704 [1 << 17]byte var x10705 [1 << 17]byte var x10706 [1 << 17]byte var x10707 [1 << 17]byte var x10708 [1 << 17]byte var x10709 [1 << 17]byte var x10710 [1 << 17]byte var x10711 [1 << 17]byte var x10712 [1 << 17]byte var x10713 [1 << 17]byte var x10714 [1 << 17]byte var x10715 [1 << 17]byte var x10716 [1 << 17]byte var x10717 [1 << 17]byte var x10718 [1 << 17]byte var x10719 [1 << 17]byte var x10720 [1 << 17]byte var x10721 [1 << 17]byte var x10722 [1 << 17]byte var x10723 [1 << 17]byte var x10724 [1 << 17]byte var x10725 [1 << 17]byte var x10726 [1 << 17]byte var x10727 [1 << 17]byte var x10728 [1 << 17]byte var x10729 [1 << 17]byte var x10730 [1 << 17]byte var x10731 [1 << 17]byte var x10732 [1 << 17]byte var x10733 [1 << 17]byte var x10734 [1 << 17]byte var x10735 [1 << 17]byte var x10736 [1 << 17]byte var x10737 [1 << 17]byte var x10738 [1 << 17]byte var x10739 [1 << 17]byte var x10740 [1 << 17]byte var x10741 [1 << 17]byte var x10742 [1 << 17]byte var x10743 [1 << 17]byte var x10744 [1 << 17]byte var x10745 [1 << 17]byte var x10746 [1 << 17]byte var x10747 [1 << 17]byte var x10748 [1 << 17]byte var x10749 [1 << 17]byte var x10750 [1 << 17]byte var x10751 [1 << 17]byte var x10752 [1 << 17]byte var x10753 [1 << 17]byte var x10754 [1 << 17]byte var x10755 [1 << 17]byte var x10756 [1 << 17]byte var x10757 [1 << 17]byte var x10758 [1 << 17]byte var x10759 [1 << 17]byte var x10760 [1 << 17]byte var x10761 [1 << 17]byte var x10762 [1 << 17]byte var x10763 [1 << 17]byte var x10764 [1 << 17]byte var x10765 [1 << 17]byte var x10766 [1 << 17]byte var x10767 [1 << 17]byte var x10768 [1 << 17]byte var x10769 [1 << 17]byte var x10770 [1 << 17]byte var x10771 [1 << 17]byte var x10772 [1 << 17]byte var x10773 [1 << 17]byte var x10774 [1 << 17]byte var x10775 [1 << 17]byte var x10776 [1 << 17]byte var x10777 [1 << 17]byte var x10778 [1 << 17]byte var x10779 [1 << 17]byte var x10780 [1 << 17]byte var x10781 [1 << 17]byte var x10782 [1 << 17]byte var x10783 [1 << 17]byte var x10784 [1 << 17]byte var x10785 [1 << 17]byte var x10786 [1 << 17]byte var x10787 [1 << 17]byte var x10788 [1 << 17]byte var x10789 [1 << 17]byte var x10790 [1 << 17]byte var x10791 [1 << 17]byte var x10792 [1 << 17]byte var x10793 [1 << 17]byte var x10794 [1 << 17]byte var x10795 [1 << 17]byte var x10796 [1 << 17]byte var x10797 [1 << 17]byte var x10798 [1 << 17]byte var x10799 [1 << 17]byte var x10800 [1 << 17]byte var x10801 [1 << 17]byte var x10802 [1 << 17]byte var x10803 [1 << 17]byte var x10804 [1 << 17]byte var x10805 [1 << 17]byte var x10806 [1 << 17]byte var x10807 [1 << 17]byte var x10808 [1 << 17]byte var x10809 [1 << 17]byte var x10810 [1 << 17]byte var x10811 [1 << 17]byte var x10812 [1 << 17]byte var x10813 [1 << 17]byte var x10814 [1 << 17]byte var x10815 [1 << 17]byte var x10816 [1 << 17]byte var x10817 [1 << 17]byte var x10818 [1 << 17]byte var x10819 [1 << 17]byte var x10820 [1 << 17]byte var x10821 [1 << 17]byte var x10822 [1 << 17]byte var x10823 [1 << 17]byte var x10824 [1 << 17]byte var x10825 [1 << 17]byte var x10826 [1 << 17]byte var x10827 [1 << 17]byte var x10828 [1 << 17]byte var x10829 [1 << 17]byte var x10830 [1 << 17]byte var x10831 [1 << 17]byte var x10832 [1 << 17]byte var x10833 [1 << 17]byte var x10834 [1 << 17]byte var x10835 [1 << 17]byte var x10836 [1 << 17]byte var x10837 [1 << 17]byte var x10838 [1 << 17]byte var x10839 [1 << 17]byte var x10840 [1 << 17]byte var x10841 [1 << 17]byte var x10842 [1 << 17]byte var x10843 [1 << 17]byte var x10844 [1 << 17]byte var x10845 [1 << 17]byte var x10846 [1 << 17]byte var x10847 [1 << 17]byte var x10848 [1 << 17]byte var x10849 [1 << 17]byte var x10850 [1 << 17]byte var x10851 [1 << 17]byte var x10852 [1 << 17]byte var x10853 [1 << 17]byte var x10854 [1 << 17]byte var x10855 [1 << 17]byte var x10856 [1 << 17]byte var x10857 [1 << 17]byte var x10858 [1 << 17]byte var x10859 [1 << 17]byte var x10860 [1 << 17]byte var x10861 [1 << 17]byte var x10862 [1 << 17]byte var x10863 [1 << 17]byte var x10864 [1 << 17]byte var x10865 [1 << 17]byte var x10866 [1 << 17]byte var x10867 [1 << 17]byte var x10868 [1 << 17]byte var x10869 [1 << 17]byte var x10870 [1 << 17]byte var x10871 [1 << 17]byte var x10872 [1 << 17]byte var x10873 [1 << 17]byte var x10874 [1 << 17]byte var x10875 [1 << 17]byte var x10876 [1 << 17]byte var x10877 [1 << 17]byte var x10878 [1 << 17]byte var x10879 [1 << 17]byte var x10880 [1 << 17]byte var x10881 [1 << 17]byte var x10882 [1 << 17]byte var x10883 [1 << 17]byte var x10884 [1 << 17]byte var x10885 [1 << 17]byte var x10886 [1 << 17]byte var x10887 [1 << 17]byte var x10888 [1 << 17]byte var x10889 [1 << 17]byte var x10890 [1 << 17]byte var x10891 [1 << 17]byte var x10892 [1 << 17]byte var x10893 [1 << 17]byte var x10894 [1 << 17]byte var x10895 [1 << 17]byte var x10896 [1 << 17]byte var x10897 [1 << 17]byte var x10898 [1 << 17]byte var x10899 [1 << 17]byte var x10900 [1 << 17]byte var x10901 [1 << 17]byte var x10902 [1 << 17]byte var x10903 [1 << 17]byte var x10904 [1 << 17]byte var x10905 [1 << 17]byte var x10906 [1 << 17]byte var x10907 [1 << 17]byte var x10908 [1 << 17]byte var x10909 [1 << 17]byte var x10910 [1 << 17]byte var x10911 [1 << 17]byte var x10912 [1 << 17]byte var x10913 [1 << 17]byte var x10914 [1 << 17]byte var x10915 [1 << 17]byte var x10916 [1 << 17]byte var x10917 [1 << 17]byte var x10918 [1 << 17]byte var x10919 [1 << 17]byte var x10920 [1 << 17]byte var x10921 [1 << 17]byte var x10922 [1 << 17]byte var x10923 [1 << 17]byte var x10924 [1 << 17]byte var x10925 [1 << 17]byte var x10926 [1 << 17]byte var x10927 [1 << 17]byte var x10928 [1 << 17]byte var x10929 [1 << 17]byte var x10930 [1 << 17]byte var x10931 [1 << 17]byte var x10932 [1 << 17]byte var x10933 [1 << 17]byte var x10934 [1 << 17]byte var x10935 [1 << 17]byte var x10936 [1 << 17]byte var x10937 [1 << 17]byte var x10938 [1 << 17]byte var x10939 [1 << 17]byte var x10940 [1 << 17]byte var x10941 [1 << 17]byte var x10942 [1 << 17]byte var x10943 [1 << 17]byte var x10944 [1 << 17]byte var x10945 [1 << 17]byte var x10946 [1 << 17]byte var x10947 [1 << 17]byte var x10948 [1 << 17]byte var x10949 [1 << 17]byte var x10950 [1 << 17]byte var x10951 [1 << 17]byte var x10952 [1 << 17]byte var x10953 [1 << 17]byte var x10954 [1 << 17]byte var x10955 [1 << 17]byte var x10956 [1 << 17]byte var x10957 [1 << 17]byte var x10958 [1 << 17]byte var x10959 [1 << 17]byte var x10960 [1 << 17]byte var x10961 [1 << 17]byte var x10962 [1 << 17]byte var x10963 [1 << 17]byte var x10964 [1 << 17]byte var x10965 [1 << 17]byte var x10966 [1 << 17]byte var x10967 [1 << 17]byte var x10968 [1 << 17]byte var x10969 [1 << 17]byte var x10970 [1 << 17]byte var x10971 [1 << 17]byte var x10972 [1 << 17]byte var x10973 [1 << 17]byte var x10974 [1 << 17]byte var x10975 [1 << 17]byte var x10976 [1 << 17]byte var x10977 [1 << 17]byte var x10978 [1 << 17]byte var x10979 [1 << 17]byte var x10980 [1 << 17]byte var x10981 [1 << 17]byte var x10982 [1 << 17]byte var x10983 [1 << 17]byte var x10984 [1 << 17]byte var x10985 [1 << 17]byte var x10986 [1 << 17]byte var x10987 [1 << 17]byte var x10988 [1 << 17]byte var x10989 [1 << 17]byte var x10990 [1 << 17]byte var x10991 [1 << 17]byte var x10992 [1 << 17]byte var x10993 [1 << 17]byte var x10994 [1 << 17]byte var x10995 [1 << 17]byte var x10996 [1 << 17]byte var x10997 [1 << 17]byte var x10998 [1 << 17]byte var x10999 [1 << 17]byte var x11000 [1 << 17]byte var x11001 [1 << 17]byte var x11002 [1 << 17]byte var x11003 [1 << 17]byte var x11004 [1 << 17]byte var x11005 [1 << 17]byte var x11006 [1 << 17]byte var x11007 [1 << 17]byte var x11008 [1 << 17]byte var x11009 [1 << 17]byte var x11010 [1 << 17]byte var x11011 [1 << 17]byte var x11012 [1 << 17]byte var x11013 [1 << 17]byte var x11014 [1 << 17]byte var x11015 [1 << 17]byte var x11016 [1 << 17]byte var x11017 [1 << 17]byte var x11018 [1 << 17]byte var x11019 [1 << 17]byte var x11020 [1 << 17]byte var x11021 [1 << 17]byte var x11022 [1 << 17]byte var x11023 [1 << 17]byte var x11024 [1 << 17]byte var x11025 [1 << 17]byte var x11026 [1 << 17]byte var x11027 [1 << 17]byte var x11028 [1 << 17]byte var x11029 [1 << 17]byte var x11030 [1 << 17]byte var x11031 [1 << 17]byte var x11032 [1 << 17]byte var x11033 [1 << 17]byte var x11034 [1 << 17]byte var x11035 [1 << 17]byte var x11036 [1 << 17]byte var x11037 [1 << 17]byte var x11038 [1 << 17]byte var x11039 [1 << 17]byte var x11040 [1 << 17]byte var x11041 [1 << 17]byte var x11042 [1 << 17]byte var x11043 [1 << 17]byte var x11044 [1 << 17]byte var x11045 [1 << 17]byte var x11046 [1 << 17]byte var x11047 [1 << 17]byte var x11048 [1 << 17]byte var x11049 [1 << 17]byte var x11050 [1 << 17]byte var x11051 [1 << 17]byte var x11052 [1 << 17]byte var x11053 [1 << 17]byte var x11054 [1 << 17]byte var x11055 [1 << 17]byte var x11056 [1 << 17]byte var x11057 [1 << 17]byte var x11058 [1 << 17]byte var x11059 [1 << 17]byte var x11060 [1 << 17]byte var x11061 [1 << 17]byte var x11062 [1 << 17]byte var x11063 [1 << 17]byte var x11064 [1 << 17]byte var x11065 [1 << 17]byte var x11066 [1 << 17]byte var x11067 [1 << 17]byte var x11068 [1 << 17]byte var x11069 [1 << 17]byte var x11070 [1 << 17]byte var x11071 [1 << 17]byte var x11072 [1 << 17]byte var x11073 [1 << 17]byte var x11074 [1 << 17]byte var x11075 [1 << 17]byte var x11076 [1 << 17]byte var x11077 [1 << 17]byte var x11078 [1 << 17]byte var x11079 [1 << 17]byte var x11080 [1 << 17]byte var x11081 [1 << 17]byte var x11082 [1 << 17]byte var x11083 [1 << 17]byte var x11084 [1 << 17]byte var x11085 [1 << 17]byte var x11086 [1 << 17]byte var x11087 [1 << 17]byte var x11088 [1 << 17]byte var x11089 [1 << 17]byte var x11090 [1 << 17]byte var x11091 [1 << 17]byte var x11092 [1 << 17]byte var x11093 [1 << 17]byte var x11094 [1 << 17]byte var x11095 [1 << 17]byte var x11096 [1 << 17]byte var x11097 [1 << 17]byte var x11098 [1 << 17]byte var x11099 [1 << 17]byte var x11100 [1 << 17]byte var x11101 [1 << 17]byte var x11102 [1 << 17]byte var x11103 [1 << 17]byte var x11104 [1 << 17]byte var x11105 [1 << 17]byte var x11106 [1 << 17]byte var x11107 [1 << 17]byte var x11108 [1 << 17]byte var x11109 [1 << 17]byte var x11110 [1 << 17]byte var x11111 [1 << 17]byte var x11112 [1 << 17]byte var x11113 [1 << 17]byte var x11114 [1 << 17]byte var x11115 [1 << 17]byte var x11116 [1 << 17]byte var x11117 [1 << 17]byte var x11118 [1 << 17]byte var x11119 [1 << 17]byte var x11120 [1 << 17]byte var x11121 [1 << 17]byte var x11122 [1 << 17]byte var x11123 [1 << 17]byte var x11124 [1 << 17]byte var x11125 [1 << 17]byte var x11126 [1 << 17]byte var x11127 [1 << 17]byte var x11128 [1 << 17]byte var x11129 [1 << 17]byte var x11130 [1 << 17]byte var x11131 [1 << 17]byte var x11132 [1 << 17]byte var x11133 [1 << 17]byte var x11134 [1 << 17]byte var x11135 [1 << 17]byte var x11136 [1 << 17]byte var x11137 [1 << 17]byte var x11138 [1 << 17]byte var x11139 [1 << 17]byte var x11140 [1 << 17]byte var x11141 [1 << 17]byte var x11142 [1 << 17]byte var x11143 [1 << 17]byte var x11144 [1 << 17]byte var x11145 [1 << 17]byte var x11146 [1 << 17]byte var x11147 [1 << 17]byte var x11148 [1 << 17]byte var x11149 [1 << 17]byte var x11150 [1 << 17]byte var x11151 [1 << 17]byte var x11152 [1 << 17]byte var x11153 [1 << 17]byte var x11154 [1 << 17]byte var x11155 [1 << 17]byte var x11156 [1 << 17]byte var x11157 [1 << 17]byte var x11158 [1 << 17]byte var x11159 [1 << 17]byte var x11160 [1 << 17]byte var x11161 [1 << 17]byte var x11162 [1 << 17]byte var x11163 [1 << 17]byte var x11164 [1 << 17]byte var x11165 [1 << 17]byte var x11166 [1 << 17]byte var x11167 [1 << 17]byte var x11168 [1 << 17]byte var x11169 [1 << 17]byte var x11170 [1 << 17]byte var x11171 [1 << 17]byte var x11172 [1 << 17]byte var x11173 [1 << 17]byte var x11174 [1 << 17]byte var x11175 [1 << 17]byte var x11176 [1 << 17]byte var x11177 [1 << 17]byte var x11178 [1 << 17]byte var x11179 [1 << 17]byte var x11180 [1 << 17]byte var x11181 [1 << 17]byte var x11182 [1 << 17]byte var x11183 [1 << 17]byte var x11184 [1 << 17]byte var x11185 [1 << 17]byte var x11186 [1 << 17]byte var x11187 [1 << 17]byte var x11188 [1 << 17]byte var x11189 [1 << 17]byte var x11190 [1 << 17]byte var x11191 [1 << 17]byte var x11192 [1 << 17]byte var x11193 [1 << 17]byte var x11194 [1 << 17]byte var x11195 [1 << 17]byte var x11196 [1 << 17]byte var x11197 [1 << 17]byte var x11198 [1 << 17]byte var x11199 [1 << 17]byte var x11200 [1 << 17]byte var x11201 [1 << 17]byte var x11202 [1 << 17]byte var x11203 [1 << 17]byte var x11204 [1 << 17]byte var x11205 [1 << 17]byte var x11206 [1 << 17]byte var x11207 [1 << 17]byte var x11208 [1 << 17]byte var x11209 [1 << 17]byte var x11210 [1 << 17]byte var x11211 [1 << 17]byte var x11212 [1 << 17]byte var x11213 [1 << 17]byte var x11214 [1 << 17]byte var x11215 [1 << 17]byte var x11216 [1 << 17]byte var x11217 [1 << 17]byte var x11218 [1 << 17]byte var x11219 [1 << 17]byte var x11220 [1 << 17]byte var x11221 [1 << 17]byte var x11222 [1 << 17]byte var x11223 [1 << 17]byte var x11224 [1 << 17]byte var x11225 [1 << 17]byte var x11226 [1 << 17]byte var x11227 [1 << 17]byte var x11228 [1 << 17]byte var x11229 [1 << 17]byte var x11230 [1 << 17]byte var x11231 [1 << 17]byte var x11232 [1 << 17]byte var x11233 [1 << 17]byte var x11234 [1 << 17]byte var x11235 [1 << 17]byte var x11236 [1 << 17]byte var x11237 [1 << 17]byte var x11238 [1 << 17]byte var x11239 [1 << 17]byte var x11240 [1 << 17]byte var x11241 [1 << 17]byte var x11242 [1 << 17]byte var x11243 [1 << 17]byte var x11244 [1 << 17]byte var x11245 [1 << 17]byte var x11246 [1 << 17]byte var x11247 [1 << 17]byte var x11248 [1 << 17]byte var x11249 [1 << 17]byte var x11250 [1 << 17]byte var x11251 [1 << 17]byte var x11252 [1 << 17]byte var x11253 [1 << 17]byte var x11254 [1 << 17]byte var x11255 [1 << 17]byte var x11256 [1 << 17]byte var x11257 [1 << 17]byte var x11258 [1 << 17]byte var x11259 [1 << 17]byte var x11260 [1 << 17]byte var x11261 [1 << 17]byte var x11262 [1 << 17]byte var x11263 [1 << 17]byte var x11264 [1 << 17]byte var x11265 [1 << 17]byte var x11266 [1 << 17]byte var x11267 [1 << 17]byte var x11268 [1 << 17]byte var x11269 [1 << 17]byte var x11270 [1 << 17]byte var x11271 [1 << 17]byte var x11272 [1 << 17]byte var x11273 [1 << 17]byte var x11274 [1 << 17]byte var x11275 [1 << 17]byte var x11276 [1 << 17]byte var x11277 [1 << 17]byte var x11278 [1 << 17]byte var x11279 [1 << 17]byte var x11280 [1 << 17]byte var x11281 [1 << 17]byte var x11282 [1 << 17]byte var x11283 [1 << 17]byte var x11284 [1 << 17]byte var x11285 [1 << 17]byte var x11286 [1 << 17]byte var x11287 [1 << 17]byte var x11288 [1 << 17]byte var x11289 [1 << 17]byte var x11290 [1 << 17]byte var x11291 [1 << 17]byte var x11292 [1 << 17]byte var x11293 [1 << 17]byte var x11294 [1 << 17]byte var x11295 [1 << 17]byte var x11296 [1 << 17]byte var x11297 [1 << 17]byte var x11298 [1 << 17]byte var x11299 [1 << 17]byte var x11300 [1 << 17]byte var x11301 [1 << 17]byte var x11302 [1 << 17]byte var x11303 [1 << 17]byte var x11304 [1 << 17]byte var x11305 [1 << 17]byte var x11306 [1 << 17]byte var x11307 [1 << 17]byte var x11308 [1 << 17]byte var x11309 [1 << 17]byte var x11310 [1 << 17]byte var x11311 [1 << 17]byte var x11312 [1 << 17]byte var x11313 [1 << 17]byte var x11314 [1 << 17]byte var x11315 [1 << 17]byte var x11316 [1 << 17]byte var x11317 [1 << 17]byte var x11318 [1 << 17]byte var x11319 [1 << 17]byte var x11320 [1 << 17]byte var x11321 [1 << 17]byte var x11322 [1 << 17]byte var x11323 [1 << 17]byte var x11324 [1 << 17]byte var x11325 [1 << 17]byte var x11326 [1 << 17]byte var x11327 [1 << 17]byte var x11328 [1 << 17]byte var x11329 [1 << 17]byte var x11330 [1 << 17]byte var x11331 [1 << 17]byte var x11332 [1 << 17]byte var x11333 [1 << 17]byte var x11334 [1 << 17]byte var x11335 [1 << 17]byte var x11336 [1 << 17]byte var x11337 [1 << 17]byte var x11338 [1 << 17]byte var x11339 [1 << 17]byte var x11340 [1 << 17]byte var x11341 [1 << 17]byte var x11342 [1 << 17]byte var x11343 [1 << 17]byte var x11344 [1 << 17]byte var x11345 [1 << 17]byte var x11346 [1 << 17]byte var x11347 [1 << 17]byte var x11348 [1 << 17]byte var x11349 [1 << 17]byte var x11350 [1 << 17]byte var x11351 [1 << 17]byte var x11352 [1 << 17]byte var x11353 [1 << 17]byte var x11354 [1 << 17]byte var x11355 [1 << 17]byte var x11356 [1 << 17]byte var x11357 [1 << 17]byte var x11358 [1 << 17]byte var x11359 [1 << 17]byte var x11360 [1 << 17]byte var x11361 [1 << 17]byte var x11362 [1 << 17]byte var x11363 [1 << 17]byte var x11364 [1 << 17]byte var x11365 [1 << 17]byte var x11366 [1 << 17]byte var x11367 [1 << 17]byte var x11368 [1 << 17]byte var x11369 [1 << 17]byte var x11370 [1 << 17]byte var x11371 [1 << 17]byte var x11372 [1 << 17]byte var x11373 [1 << 17]byte var x11374 [1 << 17]byte var x11375 [1 << 17]byte var x11376 [1 << 17]byte var x11377 [1 << 17]byte var x11378 [1 << 17]byte var x11379 [1 << 17]byte var x11380 [1 << 17]byte var x11381 [1 << 17]byte var x11382 [1 << 17]byte var x11383 [1 << 17]byte var x11384 [1 << 17]byte var x11385 [1 << 17]byte var x11386 [1 << 17]byte var x11387 [1 << 17]byte var x11388 [1 << 17]byte var x11389 [1 << 17]byte var x11390 [1 << 17]byte var x11391 [1 << 17]byte var x11392 [1 << 17]byte var x11393 [1 << 17]byte var x11394 [1 << 17]byte var x11395 [1 << 17]byte var x11396 [1 << 17]byte var x11397 [1 << 17]byte var x11398 [1 << 17]byte var x11399 [1 << 17]byte var x11400 [1 << 17]byte var x11401 [1 << 17]byte var x11402 [1 << 17]byte var x11403 [1 << 17]byte var x11404 [1 << 17]byte var x11405 [1 << 17]byte var x11406 [1 << 17]byte var x11407 [1 << 17]byte var x11408 [1 << 17]byte var x11409 [1 << 17]byte var x11410 [1 << 17]byte var x11411 [1 << 17]byte var x11412 [1 << 17]byte var x11413 [1 << 17]byte var x11414 [1 << 17]byte var x11415 [1 << 17]byte var x11416 [1 << 17]byte var x11417 [1 << 17]byte var x11418 [1 << 17]byte var x11419 [1 << 17]byte var x11420 [1 << 17]byte var x11421 [1 << 17]byte var x11422 [1 << 17]byte var x11423 [1 << 17]byte var x11424 [1 << 17]byte var x11425 [1 << 17]byte var x11426 [1 << 17]byte var x11427 [1 << 17]byte var x11428 [1 << 17]byte var x11429 [1 << 17]byte var x11430 [1 << 17]byte var x11431 [1 << 17]byte var x11432 [1 << 17]byte var x11433 [1 << 17]byte var x11434 [1 << 17]byte var x11435 [1 << 17]byte var x11436 [1 << 17]byte var x11437 [1 << 17]byte var x11438 [1 << 17]byte var x11439 [1 << 17]byte var x11440 [1 << 17]byte var x11441 [1 << 17]byte var x11442 [1 << 17]byte var x11443 [1 << 17]byte var x11444 [1 << 17]byte var x11445 [1 << 17]byte var x11446 [1 << 17]byte var x11447 [1 << 17]byte var x11448 [1 << 17]byte var x11449 [1 << 17]byte var x11450 [1 << 17]byte var x11451 [1 << 17]byte var x11452 [1 << 17]byte var x11453 [1 << 17]byte var x11454 [1 << 17]byte var x11455 [1 << 17]byte var x11456 [1 << 17]byte var x11457 [1 << 17]byte var x11458 [1 << 17]byte var x11459 [1 << 17]byte var x11460 [1 << 17]byte var x11461 [1 << 17]byte var x11462 [1 << 17]byte var x11463 [1 << 17]byte var x11464 [1 << 17]byte var x11465 [1 << 17]byte var x11466 [1 << 17]byte var x11467 [1 << 17]byte var x11468 [1 << 17]byte var x11469 [1 << 17]byte var x11470 [1 << 17]byte var x11471 [1 << 17]byte var x11472 [1 << 17]byte var x11473 [1 << 17]byte var x11474 [1 << 17]byte var x11475 [1 << 17]byte var x11476 [1 << 17]byte var x11477 [1 << 17]byte var x11478 [1 << 17]byte var x11479 [1 << 17]byte var x11480 [1 << 17]byte var x11481 [1 << 17]byte var x11482 [1 << 17]byte var x11483 [1 << 17]byte var x11484 [1 << 17]byte var x11485 [1 << 17]byte var x11486 [1 << 17]byte var x11487 [1 << 17]byte var x11488 [1 << 17]byte var x11489 [1 << 17]byte var x11490 [1 << 17]byte var x11491 [1 << 17]byte var x11492 [1 << 17]byte var x11493 [1 << 17]byte var x11494 [1 << 17]byte var x11495 [1 << 17]byte var x11496 [1 << 17]byte var x11497 [1 << 17]byte var x11498 [1 << 17]byte var x11499 [1 << 17]byte var x11500 [1 << 17]byte var x11501 [1 << 17]byte var x11502 [1 << 17]byte var x11503 [1 << 17]byte var x11504 [1 << 17]byte var x11505 [1 << 17]byte var x11506 [1 << 17]byte var x11507 [1 << 17]byte var x11508 [1 << 17]byte var x11509 [1 << 17]byte var x11510 [1 << 17]byte var x11511 [1 << 17]byte var x11512 [1 << 17]byte var x11513 [1 << 17]byte var x11514 [1 << 17]byte var x11515 [1 << 17]byte var x11516 [1 << 17]byte var x11517 [1 << 17]byte var x11518 [1 << 17]byte var x11519 [1 << 17]byte var x11520 [1 << 17]byte var x11521 [1 << 17]byte var x11522 [1 << 17]byte var x11523 [1 << 17]byte var x11524 [1 << 17]byte var x11525 [1 << 17]byte var x11526 [1 << 17]byte var x11527 [1 << 17]byte var x11528 [1 << 17]byte var x11529 [1 << 17]byte var x11530 [1 << 17]byte var x11531 [1 << 17]byte var x11532 [1 << 17]byte var x11533 [1 << 17]byte var x11534 [1 << 17]byte var x11535 [1 << 17]byte var x11536 [1 << 17]byte var x11537 [1 << 17]byte var x11538 [1 << 17]byte var x11539 [1 << 17]byte var x11540 [1 << 17]byte var x11541 [1 << 17]byte var x11542 [1 << 17]byte var x11543 [1 << 17]byte var x11544 [1 << 17]byte var x11545 [1 << 17]byte var x11546 [1 << 17]byte var x11547 [1 << 17]byte var x11548 [1 << 17]byte var x11549 [1 << 17]byte var x11550 [1 << 17]byte var x11551 [1 << 17]byte var x11552 [1 << 17]byte var x11553 [1 << 17]byte var x11554 [1 << 17]byte var x11555 [1 << 17]byte var x11556 [1 << 17]byte var x11557 [1 << 17]byte var x11558 [1 << 17]byte var x11559 [1 << 17]byte var x11560 [1 << 17]byte var x11561 [1 << 17]byte var x11562 [1 << 17]byte var x11563 [1 << 17]byte var x11564 [1 << 17]byte var x11565 [1 << 17]byte var x11566 [1 << 17]byte var x11567 [1 << 17]byte var x11568 [1 << 17]byte var x11569 [1 << 17]byte var x11570 [1 << 17]byte var x11571 [1 << 17]byte var x11572 [1 << 17]byte var x11573 [1 << 17]byte var x11574 [1 << 17]byte var x11575 [1 << 17]byte var x11576 [1 << 17]byte var x11577 [1 << 17]byte var x11578 [1 << 17]byte var x11579 [1 << 17]byte var x11580 [1 << 17]byte var x11581 [1 << 17]byte var x11582 [1 << 17]byte var x11583 [1 << 17]byte var x11584 [1 << 17]byte var x11585 [1 << 17]byte var x11586 [1 << 17]byte var x11587 [1 << 17]byte var x11588 [1 << 17]byte var x11589 [1 << 17]byte var x11590 [1 << 17]byte var x11591 [1 << 17]byte var x11592 [1 << 17]byte var x11593 [1 << 17]byte var x11594 [1 << 17]byte var x11595 [1 << 17]byte var x11596 [1 << 17]byte var x11597 [1 << 17]byte var x11598 [1 << 17]byte var x11599 [1 << 17]byte var x11600 [1 << 17]byte var x11601 [1 << 17]byte var x11602 [1 << 17]byte var x11603 [1 << 17]byte var x11604 [1 << 17]byte var x11605 [1 << 17]byte var x11606 [1 << 17]byte var x11607 [1 << 17]byte var x11608 [1 << 17]byte var x11609 [1 << 17]byte var x11610 [1 << 17]byte var x11611 [1 << 17]byte var x11612 [1 << 17]byte var x11613 [1 << 17]byte var x11614 [1 << 17]byte var x11615 [1 << 17]byte var x11616 [1 << 17]byte var x11617 [1 << 17]byte var x11618 [1 << 17]byte var x11619 [1 << 17]byte var x11620 [1 << 17]byte var x11621 [1 << 17]byte var x11622 [1 << 17]byte var x11623 [1 << 17]byte var x11624 [1 << 17]byte var x11625 [1 << 17]byte var x11626 [1 << 17]byte var x11627 [1 << 17]byte var x11628 [1 << 17]byte var x11629 [1 << 17]byte var x11630 [1 << 17]byte var x11631 [1 << 17]byte var x11632 [1 << 17]byte var x11633 [1 << 17]byte var x11634 [1 << 17]byte var x11635 [1 << 17]byte var x11636 [1 << 17]byte var x11637 [1 << 17]byte var x11638 [1 << 17]byte var x11639 [1 << 17]byte var x11640 [1 << 17]byte var x11641 [1 << 17]byte var x11642 [1 << 17]byte var x11643 [1 << 17]byte var x11644 [1 << 17]byte var x11645 [1 << 17]byte var x11646 [1 << 17]byte var x11647 [1 << 17]byte var x11648 [1 << 17]byte var x11649 [1 << 17]byte var x11650 [1 << 17]byte var x11651 [1 << 17]byte var x11652 [1 << 17]byte var x11653 [1 << 17]byte var x11654 [1 << 17]byte var x11655 [1 << 17]byte var x11656 [1 << 17]byte var x11657 [1 << 17]byte var x11658 [1 << 17]byte var x11659 [1 << 17]byte var x11660 [1 << 17]byte var x11661 [1 << 17]byte var x11662 [1 << 17]byte var x11663 [1 << 17]byte var x11664 [1 << 17]byte var x11665 [1 << 17]byte var x11666 [1 << 17]byte var x11667 [1 << 17]byte var x11668 [1 << 17]byte var x11669 [1 << 17]byte var x11670 [1 << 17]byte var x11671 [1 << 17]byte var x11672 [1 << 17]byte var x11673 [1 << 17]byte var x11674 [1 << 17]byte var x11675 [1 << 17]byte var x11676 [1 << 17]byte var x11677 [1 << 17]byte var x11678 [1 << 17]byte var x11679 [1 << 17]byte var x11680 [1 << 17]byte var x11681 [1 << 17]byte var x11682 [1 << 17]byte var x11683 [1 << 17]byte var x11684 [1 << 17]byte var x11685 [1 << 17]byte var x11686 [1 << 17]byte var x11687 [1 << 17]byte var x11688 [1 << 17]byte var x11689 [1 << 17]byte var x11690 [1 << 17]byte var x11691 [1 << 17]byte var x11692 [1 << 17]byte var x11693 [1 << 17]byte var x11694 [1 << 17]byte var x11695 [1 << 17]byte var x11696 [1 << 17]byte var x11697 [1 << 17]byte var x11698 [1 << 17]byte var x11699 [1 << 17]byte var x11700 [1 << 17]byte var x11701 [1 << 17]byte var x11702 [1 << 17]byte var x11703 [1 << 17]byte var x11704 [1 << 17]byte var x11705 [1 << 17]byte var x11706 [1 << 17]byte var x11707 [1 << 17]byte var x11708 [1 << 17]byte var x11709 [1 << 17]byte var x11710 [1 << 17]byte var x11711 [1 << 17]byte var x11712 [1 << 17]byte var x11713 [1 << 17]byte var x11714 [1 << 17]byte var x11715 [1 << 17]byte var x11716 [1 << 17]byte var x11717 [1 << 17]byte var x11718 [1 << 17]byte var x11719 [1 << 17]byte var x11720 [1 << 17]byte var x11721 [1 << 17]byte var x11722 [1 << 17]byte var x11723 [1 << 17]byte var x11724 [1 << 17]byte var x11725 [1 << 17]byte var x11726 [1 << 17]byte var x11727 [1 << 17]byte var x11728 [1 << 17]byte var x11729 [1 << 17]byte var x11730 [1 << 17]byte var x11731 [1 << 17]byte var x11732 [1 << 17]byte var x11733 [1 << 17]byte var x11734 [1 << 17]byte var x11735 [1 << 17]byte var x11736 [1 << 17]byte var x11737 [1 << 17]byte var x11738 [1 << 17]byte var x11739 [1 << 17]byte var x11740 [1 << 17]byte var x11741 [1 << 17]byte var x11742 [1 << 17]byte var x11743 [1 << 17]byte var x11744 [1 << 17]byte var x11745 [1 << 17]byte var x11746 [1 << 17]byte var x11747 [1 << 17]byte var x11748 [1 << 17]byte var x11749 [1 << 17]byte var x11750 [1 << 17]byte var x11751 [1 << 17]byte var x11752 [1 << 17]byte var x11753 [1 << 17]byte var x11754 [1 << 17]byte var x11755 [1 << 17]byte var x11756 [1 << 17]byte var x11757 [1 << 17]byte var x11758 [1 << 17]byte var x11759 [1 << 17]byte var x11760 [1 << 17]byte var x11761 [1 << 17]byte var x11762 [1 << 17]byte var x11763 [1 << 17]byte var x11764 [1 << 17]byte var x11765 [1 << 17]byte var x11766 [1 << 17]byte var x11767 [1 << 17]byte var x11768 [1 << 17]byte var x11769 [1 << 17]byte var x11770 [1 << 17]byte var x11771 [1 << 17]byte var x11772 [1 << 17]byte var x11773 [1 << 17]byte var x11774 [1 << 17]byte var x11775 [1 << 17]byte var x11776 [1 << 17]byte var x11777 [1 << 17]byte var x11778 [1 << 17]byte var x11779 [1 << 17]byte var x11780 [1 << 17]byte var x11781 [1 << 17]byte var x11782 [1 << 17]byte var x11783 [1 << 17]byte var x11784 [1 << 17]byte var x11785 [1 << 17]byte var x11786 [1 << 17]byte var x11787 [1 << 17]byte var x11788 [1 << 17]byte var x11789 [1 << 17]byte var x11790 [1 << 17]byte var x11791 [1 << 17]byte var x11792 [1 << 17]byte var x11793 [1 << 17]byte var x11794 [1 << 17]byte var x11795 [1 << 17]byte var x11796 [1 << 17]byte var x11797 [1 << 17]byte var x11798 [1 << 17]byte var x11799 [1 << 17]byte var x11800 [1 << 17]byte var x11801 [1 << 17]byte var x11802 [1 << 17]byte var x11803 [1 << 17]byte var x11804 [1 << 17]byte var x11805 [1 << 17]byte var x11806 [1 << 17]byte var x11807 [1 << 17]byte var x11808 [1 << 17]byte var x11809 [1 << 17]byte var x11810 [1 << 17]byte var x11811 [1 << 17]byte var x11812 [1 << 17]byte var x11813 [1 << 17]byte var x11814 [1 << 17]byte var x11815 [1 << 17]byte var x11816 [1 << 17]byte var x11817 [1 << 17]byte var x11818 [1 << 17]byte var x11819 [1 << 17]byte var x11820 [1 << 17]byte var x11821 [1 << 17]byte var x11822 [1 << 17]byte var x11823 [1 << 17]byte var x11824 [1 << 17]byte var x11825 [1 << 17]byte var x11826 [1 << 17]byte var x11827 [1 << 17]byte var x11828 [1 << 17]byte var x11829 [1 << 17]byte var x11830 [1 << 17]byte var x11831 [1 << 17]byte var x11832 [1 << 17]byte var x11833 [1 << 17]byte var x11834 [1 << 17]byte var x11835 [1 << 17]byte var x11836 [1 << 17]byte var x11837 [1 << 17]byte var x11838 [1 << 17]byte var x11839 [1 << 17]byte var x11840 [1 << 17]byte var x11841 [1 << 17]byte var x11842 [1 << 17]byte var x11843 [1 << 17]byte var x11844 [1 << 17]byte var x11845 [1 << 17]byte var x11846 [1 << 17]byte var x11847 [1 << 17]byte var x11848 [1 << 17]byte var x11849 [1 << 17]byte var x11850 [1 << 17]byte var x11851 [1 << 17]byte var x11852 [1 << 17]byte var x11853 [1 << 17]byte var x11854 [1 << 17]byte var x11855 [1 << 17]byte var x11856 [1 << 17]byte var x11857 [1 << 17]byte var x11858 [1 << 17]byte var x11859 [1 << 17]byte var x11860 [1 << 17]byte var x11861 [1 << 17]byte var x11862 [1 << 17]byte var x11863 [1 << 17]byte var x11864 [1 << 17]byte var x11865 [1 << 17]byte var x11866 [1 << 17]byte var x11867 [1 << 17]byte var x11868 [1 << 17]byte var x11869 [1 << 17]byte var x11870 [1 << 17]byte var x11871 [1 << 17]byte var x11872 [1 << 17]byte var x11873 [1 << 17]byte var x11874 [1 << 17]byte var x11875 [1 << 17]byte var x11876 [1 << 17]byte var x11877 [1 << 17]byte var x11878 [1 << 17]byte var x11879 [1 << 17]byte var x11880 [1 << 17]byte var x11881 [1 << 17]byte var x11882 [1 << 17]byte var x11883 [1 << 17]byte var x11884 [1 << 17]byte var x11885 [1 << 17]byte var x11886 [1 << 17]byte var x11887 [1 << 17]byte var x11888 [1 << 17]byte var x11889 [1 << 17]byte var x11890 [1 << 17]byte var x11891 [1 << 17]byte var x11892 [1 << 17]byte var x11893 [1 << 17]byte var x11894 [1 << 17]byte var x11895 [1 << 17]byte var x11896 [1 << 17]byte var x11897 [1 << 17]byte var x11898 [1 << 17]byte var x11899 [1 << 17]byte var x11900 [1 << 17]byte var x11901 [1 << 17]byte var x11902 [1 << 17]byte var x11903 [1 << 17]byte var x11904 [1 << 17]byte var x11905 [1 << 17]byte var x11906 [1 << 17]byte var x11907 [1 << 17]byte var x11908 [1 << 17]byte var x11909 [1 << 17]byte var x11910 [1 << 17]byte var x11911 [1 << 17]byte var x11912 [1 << 17]byte var x11913 [1 << 17]byte var x11914 [1 << 17]byte var x11915 [1 << 17]byte var x11916 [1 << 17]byte var x11917 [1 << 17]byte var x11918 [1 << 17]byte var x11919 [1 << 17]byte var x11920 [1 << 17]byte var x11921 [1 << 17]byte var x11922 [1 << 17]byte var x11923 [1 << 17]byte var x11924 [1 << 17]byte var x11925 [1 << 17]byte var x11926 [1 << 17]byte var x11927 [1 << 17]byte var x11928 [1 << 17]byte var x11929 [1 << 17]byte var x11930 [1 << 17]byte var x11931 [1 << 17]byte var x11932 [1 << 17]byte var x11933 [1 << 17]byte var x11934 [1 << 17]byte var x11935 [1 << 17]byte var x11936 [1 << 17]byte var x11937 [1 << 17]byte var x11938 [1 << 17]byte var x11939 [1 << 17]byte var x11940 [1 << 17]byte var x11941 [1 << 17]byte var x11942 [1 << 17]byte var x11943 [1 << 17]byte var x11944 [1 << 17]byte var x11945 [1 << 17]byte var x11946 [1 << 17]byte var x11947 [1 << 17]byte var x11948 [1 << 17]byte var x11949 [1 << 17]byte var x11950 [1 << 17]byte var x11951 [1 << 17]byte var x11952 [1 << 17]byte var x11953 [1 << 17]byte var x11954 [1 << 17]byte var x11955 [1 << 17]byte var x11956 [1 << 17]byte var x11957 [1 << 17]byte var x11958 [1 << 17]byte var x11959 [1 << 17]byte var x11960 [1 << 17]byte var x11961 [1 << 17]byte var x11962 [1 << 17]byte var x11963 [1 << 17]byte var x11964 [1 << 17]byte var x11965 [1 << 17]byte var x11966 [1 << 17]byte var x11967 [1 << 17]byte var x11968 [1 << 17]byte var x11969 [1 << 17]byte var x11970 [1 << 17]byte var x11971 [1 << 17]byte var x11972 [1 << 17]byte var x11973 [1 << 17]byte var x11974 [1 << 17]byte var x11975 [1 << 17]byte var x11976 [1 << 17]byte var x11977 [1 << 17]byte var x11978 [1 << 17]byte var x11979 [1 << 17]byte var x11980 [1 << 17]byte var x11981 [1 << 17]byte var x11982 [1 << 17]byte var x11983 [1 << 17]byte var x11984 [1 << 17]byte var x11985 [1 << 17]byte var x11986 [1 << 17]byte var x11987 [1 << 17]byte var x11988 [1 << 17]byte var x11989 [1 << 17]byte var x11990 [1 << 17]byte var x11991 [1 << 17]byte var x11992 [1 << 17]byte var x11993 [1 << 17]byte var x11994 [1 << 17]byte var x11995 [1 << 17]byte var x11996 [1 << 17]byte var x11997 [1 << 17]byte var x11998 [1 << 17]byte var x11999 [1 << 17]byte var x12000 [1 << 17]byte var x12001 [1 << 17]byte var x12002 [1 << 17]byte var x12003 [1 << 17]byte var x12004 [1 << 17]byte var x12005 [1 << 17]byte var x12006 [1 << 17]byte var x12007 [1 << 17]byte var x12008 [1 << 17]byte var x12009 [1 << 17]byte var x12010 [1 << 17]byte var x12011 [1 << 17]byte var x12012 [1 << 17]byte var x12013 [1 << 17]byte var x12014 [1 << 17]byte var x12015 [1 << 17]byte var x12016 [1 << 17]byte var x12017 [1 << 17]byte var x12018 [1 << 17]byte var x12019 [1 << 17]byte var x12020 [1 << 17]byte var x12021 [1 << 17]byte var x12022 [1 << 17]byte var x12023 [1 << 17]byte var x12024 [1 << 17]byte var x12025 [1 << 17]byte var x12026 [1 << 17]byte var x12027 [1 << 17]byte var x12028 [1 << 17]byte var x12029 [1 << 17]byte var x12030 [1 << 17]byte var x12031 [1 << 17]byte var x12032 [1 << 17]byte var x12033 [1 << 17]byte var x12034 [1 << 17]byte var x12035 [1 << 17]byte var x12036 [1 << 17]byte var x12037 [1 << 17]byte var x12038 [1 << 17]byte var x12039 [1 << 17]byte var x12040 [1 << 17]byte var x12041 [1 << 17]byte var x12042 [1 << 17]byte var x12043 [1 << 17]byte var x12044 [1 << 17]byte var x12045 [1 << 17]byte var x12046 [1 << 17]byte var x12047 [1 << 17]byte var x12048 [1 << 17]byte var x12049 [1 << 17]byte var x12050 [1 << 17]byte var x12051 [1 << 17]byte var x12052 [1 << 17]byte var x12053 [1 << 17]byte var x12054 [1 << 17]byte var x12055 [1 << 17]byte var x12056 [1 << 17]byte var x12057 [1 << 17]byte var x12058 [1 << 17]byte var x12059 [1 << 17]byte var x12060 [1 << 17]byte var x12061 [1 << 17]byte var x12062 [1 << 17]byte var x12063 [1 << 17]byte var x12064 [1 << 17]byte var x12065 [1 << 17]byte var x12066 [1 << 17]byte var x12067 [1 << 17]byte var x12068 [1 << 17]byte var x12069 [1 << 17]byte var x12070 [1 << 17]byte var x12071 [1 << 17]byte var x12072 [1 << 17]byte var x12073 [1 << 17]byte var x12074 [1 << 17]byte var x12075 [1 << 17]byte var x12076 [1 << 17]byte var x12077 [1 << 17]byte var x12078 [1 << 17]byte var x12079 [1 << 17]byte var x12080 [1 << 17]byte var x12081 [1 << 17]byte var x12082 [1 << 17]byte var x12083 [1 << 17]byte var x12084 [1 << 17]byte var x12085 [1 << 17]byte var x12086 [1 << 17]byte var x12087 [1 << 17]byte var x12088 [1 << 17]byte var x12089 [1 << 17]byte var x12090 [1 << 17]byte var x12091 [1 << 17]byte var x12092 [1 << 17]byte var x12093 [1 << 17]byte var x12094 [1 << 17]byte var x12095 [1 << 17]byte var x12096 [1 << 17]byte var x12097 [1 << 17]byte var x12098 [1 << 17]byte var x12099 [1 << 17]byte var x12100 [1 << 17]byte var x12101 [1 << 17]byte var x12102 [1 << 17]byte var x12103 [1 << 17]byte var x12104 [1 << 17]byte var x12105 [1 << 17]byte var x12106 [1 << 17]byte var x12107 [1 << 17]byte var x12108 [1 << 17]byte var x12109 [1 << 17]byte var x12110 [1 << 17]byte var x12111 [1 << 17]byte var x12112 [1 << 17]byte var x12113 [1 << 17]byte var x12114 [1 << 17]byte var x12115 [1 << 17]byte var x12116 [1 << 17]byte var x12117 [1 << 17]byte var x12118 [1 << 17]byte var x12119 [1 << 17]byte var x12120 [1 << 17]byte var x12121 [1 << 17]byte var x12122 [1 << 17]byte var x12123 [1 << 17]byte var x12124 [1 << 17]byte var x12125 [1 << 17]byte var x12126 [1 << 17]byte var x12127 [1 << 17]byte var x12128 [1 << 17]byte var x12129 [1 << 17]byte var x12130 [1 << 17]byte var x12131 [1 << 17]byte var x12132 [1 << 17]byte var x12133 [1 << 17]byte var x12134 [1 << 17]byte var x12135 [1 << 17]byte var x12136 [1 << 17]byte var x12137 [1 << 17]byte var x12138 [1 << 17]byte var x12139 [1 << 17]byte var x12140 [1 << 17]byte var x12141 [1 << 17]byte var x12142 [1 << 17]byte var x12143 [1 << 17]byte var x12144 [1 << 17]byte var x12145 [1 << 17]byte var x12146 [1 << 17]byte var x12147 [1 << 17]byte var x12148 [1 << 17]byte var x12149 [1 << 17]byte var x12150 [1 << 17]byte var x12151 [1 << 17]byte var x12152 [1 << 17]byte var x12153 [1 << 17]byte var x12154 [1 << 17]byte var x12155 [1 << 17]byte var x12156 [1 << 17]byte var x12157 [1 << 17]byte var x12158 [1 << 17]byte var x12159 [1 << 17]byte var x12160 [1 << 17]byte var x12161 [1 << 17]byte var x12162 [1 << 17]byte var x12163 [1 << 17]byte var x12164 [1 << 17]byte var x12165 [1 << 17]byte var x12166 [1 << 17]byte var x12167 [1 << 17]byte var x12168 [1 << 17]byte var x12169 [1 << 17]byte var x12170 [1 << 17]byte var x12171 [1 << 17]byte var x12172 [1 << 17]byte var x12173 [1 << 17]byte var x12174 [1 << 17]byte var x12175 [1 << 17]byte var x12176 [1 << 17]byte var x12177 [1 << 17]byte var x12178 [1 << 17]byte var x12179 [1 << 17]byte var x12180 [1 << 17]byte var x12181 [1 << 17]byte var x12182 [1 << 17]byte var x12183 [1 << 17]byte var x12184 [1 << 17]byte var x12185 [1 << 17]byte var x12186 [1 << 17]byte var x12187 [1 << 17]byte var x12188 [1 << 17]byte var x12189 [1 << 17]byte var x12190 [1 << 17]byte var x12191 [1 << 17]byte var x12192 [1 << 17]byte var x12193 [1 << 17]byte var x12194 [1 << 17]byte var x12195 [1 << 17]byte var x12196 [1 << 17]byte var x12197 [1 << 17]byte var x12198 [1 << 17]byte var x12199 [1 << 17]byte var x12200 [1 << 17]byte var x12201 [1 << 17]byte var x12202 [1 << 17]byte var x12203 [1 << 17]byte var x12204 [1 << 17]byte var x12205 [1 << 17]byte var x12206 [1 << 17]byte var x12207 [1 << 17]byte var x12208 [1 << 17]byte var x12209 [1 << 17]byte var x12210 [1 << 17]byte var x12211 [1 << 17]byte var x12212 [1 << 17]byte var x12213 [1 << 17]byte var x12214 [1 << 17]byte var x12215 [1 << 17]byte var x12216 [1 << 17]byte var x12217 [1 << 17]byte var x12218 [1 << 17]byte var x12219 [1 << 17]byte var x12220 [1 << 17]byte var x12221 [1 << 17]byte var x12222 [1 << 17]byte var x12223 [1 << 17]byte var x12224 [1 << 17]byte var x12225 [1 << 17]byte var x12226 [1 << 17]byte var x12227 [1 << 17]byte var x12228 [1 << 17]byte var x12229 [1 << 17]byte var x12230 [1 << 17]byte var x12231 [1 << 17]byte var x12232 [1 << 17]byte var x12233 [1 << 17]byte var x12234 [1 << 17]byte var x12235 [1 << 17]byte var x12236 [1 << 17]byte var x12237 [1 << 17]byte var x12238 [1 << 17]byte var x12239 [1 << 17]byte var x12240 [1 << 17]byte var x12241 [1 << 17]byte var x12242 [1 << 17]byte var x12243 [1 << 17]byte var x12244 [1 << 17]byte var x12245 [1 << 17]byte var x12246 [1 << 17]byte var x12247 [1 << 17]byte var x12248 [1 << 17]byte var x12249 [1 << 17]byte var x12250 [1 << 17]byte var x12251 [1 << 17]byte var x12252 [1 << 17]byte var x12253 [1 << 17]byte var x12254 [1 << 17]byte var x12255 [1 << 17]byte var x12256 [1 << 17]byte var x12257 [1 << 17]byte var x12258 [1 << 17]byte var x12259 [1 << 17]byte var x12260 [1 << 17]byte var x12261 [1 << 17]byte var x12262 [1 << 17]byte var x12263 [1 << 17]byte var x12264 [1 << 17]byte var x12265 [1 << 17]byte var x12266 [1 << 17]byte var x12267 [1 << 17]byte var x12268 [1 << 17]byte var x12269 [1 << 17]byte var x12270 [1 << 17]byte var x12271 [1 << 17]byte var x12272 [1 << 17]byte var x12273 [1 << 17]byte var x12274 [1 << 17]byte var x12275 [1 << 17]byte var x12276 [1 << 17]byte var x12277 [1 << 17]byte var x12278 [1 << 17]byte var x12279 [1 << 17]byte var x12280 [1 << 17]byte var x12281 [1 << 17]byte var x12282 [1 << 17]byte var x12283 [1 << 17]byte var x12284 [1 << 17]byte var x12285 [1 << 17]byte var x12286 [1 << 17]byte var x12287 [1 << 17]byte var x12288 [1 << 17]byte var x12289 [1 << 17]byte var x12290 [1 << 17]byte var x12291 [1 << 17]byte var x12292 [1 << 17]byte var x12293 [1 << 17]byte var x12294 [1 << 17]byte var x12295 [1 << 17]byte var x12296 [1 << 17]byte var x12297 [1 << 17]byte var x12298 [1 << 17]byte var x12299 [1 << 17]byte var x12300 [1 << 17]byte var x12301 [1 << 17]byte var x12302 [1 << 17]byte var x12303 [1 << 17]byte var x12304 [1 << 17]byte var x12305 [1 << 17]byte var x12306 [1 << 17]byte var x12307 [1 << 17]byte var x12308 [1 << 17]byte var x12309 [1 << 17]byte var x12310 [1 << 17]byte var x12311 [1 << 17]byte var x12312 [1 << 17]byte var x12313 [1 << 17]byte var x12314 [1 << 17]byte var x12315 [1 << 17]byte var x12316 [1 << 17]byte var x12317 [1 << 17]byte var x12318 [1 << 17]byte var x12319 [1 << 17]byte var x12320 [1 << 17]byte var x12321 [1 << 17]byte var x12322 [1 << 17]byte var x12323 [1 << 17]byte var x12324 [1 << 17]byte var x12325 [1 << 17]byte var x12326 [1 << 17]byte var x12327 [1 << 17]byte var x12328 [1 << 17]byte var x12329 [1 << 17]byte var x12330 [1 << 17]byte var x12331 [1 << 17]byte var x12332 [1 << 17]byte var x12333 [1 << 17]byte var x12334 [1 << 17]byte var x12335 [1 << 17]byte var x12336 [1 << 17]byte var x12337 [1 << 17]byte var x12338 [1 << 17]byte var x12339 [1 << 17]byte var x12340 [1 << 17]byte var x12341 [1 << 17]byte var x12342 [1 << 17]byte var x12343 [1 << 17]byte var x12344 [1 << 17]byte var x12345 [1 << 17]byte var x12346 [1 << 17]byte var x12347 [1 << 17]byte var x12348 [1 << 17]byte var x12349 [1 << 17]byte var x12350 [1 << 17]byte var x12351 [1 << 17]byte var x12352 [1 << 17]byte var x12353 [1 << 17]byte var x12354 [1 << 17]byte var x12355 [1 << 17]byte var x12356 [1 << 17]byte var x12357 [1 << 17]byte var x12358 [1 << 17]byte var x12359 [1 << 17]byte var x12360 [1 << 17]byte var x12361 [1 << 17]byte var x12362 [1 << 17]byte var x12363 [1 << 17]byte var x12364 [1 << 17]byte var x12365 [1 << 17]byte var x12366 [1 << 17]byte var x12367 [1 << 17]byte var x12368 [1 << 17]byte var x12369 [1 << 17]byte var x12370 [1 << 17]byte var x12371 [1 << 17]byte var x12372 [1 << 17]byte var x12373 [1 << 17]byte var x12374 [1 << 17]byte var x12375 [1 << 17]byte var x12376 [1 << 17]byte var x12377 [1 << 17]byte var x12378 [1 << 17]byte var x12379 [1 << 17]byte var x12380 [1 << 17]byte var x12381 [1 << 17]byte var x12382 [1 << 17]byte var x12383 [1 << 17]byte var x12384 [1 << 17]byte var x12385 [1 << 17]byte var x12386 [1 << 17]byte var x12387 [1 << 17]byte var x12388 [1 << 17]byte var x12389 [1 << 17]byte var x12390 [1 << 17]byte var x12391 [1 << 17]byte var x12392 [1 << 17]byte var x12393 [1 << 17]byte var x12394 [1 << 17]byte var x12395 [1 << 17]byte var x12396 [1 << 17]byte var x12397 [1 << 17]byte var x12398 [1 << 17]byte var x12399 [1 << 17]byte var x12400 [1 << 17]byte var x12401 [1 << 17]byte var x12402 [1 << 17]byte var x12403 [1 << 17]byte var x12404 [1 << 17]byte var x12405 [1 << 17]byte var x12406 [1 << 17]byte var x12407 [1 << 17]byte var x12408 [1 << 17]byte var x12409 [1 << 17]byte var x12410 [1 << 17]byte var x12411 [1 << 17]byte var x12412 [1 << 17]byte var x12413 [1 << 17]byte var x12414 [1 << 17]byte var x12415 [1 << 17]byte var x12416 [1 << 17]byte var x12417 [1 << 17]byte var x12418 [1 << 17]byte var x12419 [1 << 17]byte var x12420 [1 << 17]byte var x12421 [1 << 17]byte var x12422 [1 << 17]byte var x12423 [1 << 17]byte var x12424 [1 << 17]byte var x12425 [1 << 17]byte var x12426 [1 << 17]byte var x12427 [1 << 17]byte var x12428 [1 << 17]byte var x12429 [1 << 17]byte var x12430 [1 << 17]byte var x12431 [1 << 17]byte var x12432 [1 << 17]byte var x12433 [1 << 17]byte var x12434 [1 << 17]byte var x12435 [1 << 17]byte var x12436 [1 << 17]byte var x12437 [1 << 17]byte var x12438 [1 << 17]byte var x12439 [1 << 17]byte var x12440 [1 << 17]byte var x12441 [1 << 17]byte var x12442 [1 << 17]byte var x12443 [1 << 17]byte var x12444 [1 << 17]byte var x12445 [1 << 17]byte var x12446 [1 << 17]byte var x12447 [1 << 17]byte var x12448 [1 << 17]byte var x12449 [1 << 17]byte var x12450 [1 << 17]byte var x12451 [1 << 17]byte var x12452 [1 << 17]byte var x12453 [1 << 17]byte var x12454 [1 << 17]byte var x12455 [1 << 17]byte var x12456 [1 << 17]byte var x12457 [1 << 17]byte var x12458 [1 << 17]byte var x12459 [1 << 17]byte var x12460 [1 << 17]byte var x12461 [1 << 17]byte var x12462 [1 << 17]byte var x12463 [1 << 17]byte var x12464 [1 << 17]byte var x12465 [1 << 17]byte var x12466 [1 << 17]byte var x12467 [1 << 17]byte var x12468 [1 << 17]byte var x12469 [1 << 17]byte var x12470 [1 << 17]byte var x12471 [1 << 17]byte var x12472 [1 << 17]byte var x12473 [1 << 17]byte var x12474 [1 << 17]byte var x12475 [1 << 17]byte var x12476 [1 << 17]byte var x12477 [1 << 17]byte var x12478 [1 << 17]byte var x12479 [1 << 17]byte var x12480 [1 << 17]byte var x12481 [1 << 17]byte var x12482 [1 << 17]byte var x12483 [1 << 17]byte var x12484 [1 << 17]byte var x12485 [1 << 17]byte var x12486 [1 << 17]byte var x12487 [1 << 17]byte var x12488 [1 << 17]byte var x12489 [1 << 17]byte var x12490 [1 << 17]byte var x12491 [1 << 17]byte var x12492 [1 << 17]byte var x12493 [1 << 17]byte var x12494 [1 << 17]byte var x12495 [1 << 17]byte var x12496 [1 << 17]byte var x12497 [1 << 17]byte var x12498 [1 << 17]byte var x12499 [1 << 17]byte var x12500 [1 << 17]byte var x12501 [1 << 17]byte var x12502 [1 << 17]byte var x12503 [1 << 17]byte var x12504 [1 << 17]byte var x12505 [1 << 17]byte var x12506 [1 << 17]byte var x12507 [1 << 17]byte var x12508 [1 << 17]byte var x12509 [1 << 17]byte var x12510 [1 << 17]byte var x12511 [1 << 17]byte var x12512 [1 << 17]byte var x12513 [1 << 17]byte var x12514 [1 << 17]byte var x12515 [1 << 17]byte var x12516 [1 << 17]byte var x12517 [1 << 17]byte var x12518 [1 << 17]byte var x12519 [1 << 17]byte var x12520 [1 << 17]byte var x12521 [1 << 17]byte var x12522 [1 << 17]byte var x12523 [1 << 17]byte var x12524 [1 << 17]byte var x12525 [1 << 17]byte var x12526 [1 << 17]byte var x12527 [1 << 17]byte var x12528 [1 << 17]byte var x12529 [1 << 17]byte var x12530 [1 << 17]byte var x12531 [1 << 17]byte var x12532 [1 << 17]byte var x12533 [1 << 17]byte var x12534 [1 << 17]byte var x12535 [1 << 17]byte var x12536 [1 << 17]byte var x12537 [1 << 17]byte var x12538 [1 << 17]byte var x12539 [1 << 17]byte var x12540 [1 << 17]byte var x12541 [1 << 17]byte var x12542 [1 << 17]byte var x12543 [1 << 17]byte var x12544 [1 << 17]byte var x12545 [1 << 17]byte var x12546 [1 << 17]byte var x12547 [1 << 17]byte var x12548 [1 << 17]byte var x12549 [1 << 17]byte var x12550 [1 << 17]byte var x12551 [1 << 17]byte var x12552 [1 << 17]byte var x12553 [1 << 17]byte var x12554 [1 << 17]byte var x12555 [1 << 17]byte var x12556 [1 << 17]byte var x12557 [1 << 17]byte var x12558 [1 << 17]byte var x12559 [1 << 17]byte var x12560 [1 << 17]byte var x12561 [1 << 17]byte var x12562 [1 << 17]byte var x12563 [1 << 17]byte var x12564 [1 << 17]byte var x12565 [1 << 17]byte var x12566 [1 << 17]byte var x12567 [1 << 17]byte var x12568 [1 << 17]byte var x12569 [1 << 17]byte var x12570 [1 << 17]byte var x12571 [1 << 17]byte var x12572 [1 << 17]byte var x12573 [1 << 17]byte var x12574 [1 << 17]byte var x12575 [1 << 17]byte var x12576 [1 << 17]byte var x12577 [1 << 17]byte var x12578 [1 << 17]byte var x12579 [1 << 17]byte var x12580 [1 << 17]byte var x12581 [1 << 17]byte var x12582 [1 << 17]byte var x12583 [1 << 17]byte var x12584 [1 << 17]byte var x12585 [1 << 17]byte var x12586 [1 << 17]byte var x12587 [1 << 17]byte var x12588 [1 << 17]byte var x12589 [1 << 17]byte var x12590 [1 << 17]byte var x12591 [1 << 17]byte var x12592 [1 << 17]byte var x12593 [1 << 17]byte var x12594 [1 << 17]byte var x12595 [1 << 17]byte var x12596 [1 << 17]byte var x12597 [1 << 17]byte var x12598 [1 << 17]byte var x12599 [1 << 17]byte var x12600 [1 << 17]byte var x12601 [1 << 17]byte var x12602 [1 << 17]byte var x12603 [1 << 17]byte var x12604 [1 << 17]byte var x12605 [1 << 17]byte var x12606 [1 << 17]byte var x12607 [1 << 17]byte var x12608 [1 << 17]byte var x12609 [1 << 17]byte var x12610 [1 << 17]byte var x12611 [1 << 17]byte var x12612 [1 << 17]byte var x12613 [1 << 17]byte var x12614 [1 << 17]byte var x12615 [1 << 17]byte var x12616 [1 << 17]byte var x12617 [1 << 17]byte var x12618 [1 << 17]byte var x12619 [1 << 17]byte var x12620 [1 << 17]byte var x12621 [1 << 17]byte var x12622 [1 << 17]byte var x12623 [1 << 17]byte var x12624 [1 << 17]byte var x12625 [1 << 17]byte var x12626 [1 << 17]byte var x12627 [1 << 17]byte var x12628 [1 << 17]byte var x12629 [1 << 17]byte var x12630 [1 << 17]byte var x12631 [1 << 17]byte var x12632 [1 << 17]byte var x12633 [1 << 17]byte var x12634 [1 << 17]byte var x12635 [1 << 17]byte var x12636 [1 << 17]byte var x12637 [1 << 17]byte var x12638 [1 << 17]byte var x12639 [1 << 17]byte var x12640 [1 << 17]byte var x12641 [1 << 17]byte var x12642 [1 << 17]byte var x12643 [1 << 17]byte var x12644 [1 << 17]byte var x12645 [1 << 17]byte var x12646 [1 << 17]byte var x12647 [1 << 17]byte var x12648 [1 << 17]byte var x12649 [1 << 17]byte var x12650 [1 << 17]byte var x12651 [1 << 17]byte var x12652 [1 << 17]byte var x12653 [1 << 17]byte var x12654 [1 << 17]byte var x12655 [1 << 17]byte var x12656 [1 << 17]byte var x12657 [1 << 17]byte var x12658 [1 << 17]byte var x12659 [1 << 17]byte var x12660 [1 << 17]byte var x12661 [1 << 17]byte var x12662 [1 << 17]byte var x12663 [1 << 17]byte var x12664 [1 << 17]byte var x12665 [1 << 17]byte var x12666 [1 << 17]byte var x12667 [1 << 17]byte var x12668 [1 << 17]byte var x12669 [1 << 17]byte var x12670 [1 << 17]byte var x12671 [1 << 17]byte var x12672 [1 << 17]byte var x12673 [1 << 17]byte var x12674 [1 << 17]byte var x12675 [1 << 17]byte var x12676 [1 << 17]byte var x12677 [1 << 17]byte var x12678 [1 << 17]byte var x12679 [1 << 17]byte var x12680 [1 << 17]byte var x12681 [1 << 17]byte var x12682 [1 << 17]byte var x12683 [1 << 17]byte var x12684 [1 << 17]byte var x12685 [1 << 17]byte var x12686 [1 << 17]byte var x12687 [1 << 17]byte var x12688 [1 << 17]byte var x12689 [1 << 17]byte var x12690 [1 << 17]byte var x12691 [1 << 17]byte var x12692 [1 << 17]byte var x12693 [1 << 17]byte var x12694 [1 << 17]byte var x12695 [1 << 17]byte var x12696 [1 << 17]byte var x12697 [1 << 17]byte var x12698 [1 << 17]byte var x12699 [1 << 17]byte var x12700 [1 << 17]byte var x12701 [1 << 17]byte var x12702 [1 << 17]byte var x12703 [1 << 17]byte var x12704 [1 << 17]byte var x12705 [1 << 17]byte var x12706 [1 << 17]byte var x12707 [1 << 17]byte var x12708 [1 << 17]byte var x12709 [1 << 17]byte var x12710 [1 << 17]byte var x12711 [1 << 17]byte var x12712 [1 << 17]byte var x12713 [1 << 17]byte var x12714 [1 << 17]byte var x12715 [1 << 17]byte var x12716 [1 << 17]byte var x12717 [1 << 17]byte var x12718 [1 << 17]byte var x12719 [1 << 17]byte var x12720 [1 << 17]byte var x12721 [1 << 17]byte var x12722 [1 << 17]byte var x12723 [1 << 17]byte var x12724 [1 << 17]byte var x12725 [1 << 17]byte var x12726 [1 << 17]byte var x12727 [1 << 17]byte var x12728 [1 << 17]byte var x12729 [1 << 17]byte var x12730 [1 << 17]byte var x12731 [1 << 17]byte var x12732 [1 << 17]byte var x12733 [1 << 17]byte var x12734 [1 << 17]byte var x12735 [1 << 17]byte var x12736 [1 << 17]byte var x12737 [1 << 17]byte var x12738 [1 << 17]byte var x12739 [1 << 17]byte var x12740 [1 << 17]byte var x12741 [1 << 17]byte var x12742 [1 << 17]byte var x12743 [1 << 17]byte var x12744 [1 << 17]byte var x12745 [1 << 17]byte var x12746 [1 << 17]byte var x12747 [1 << 17]byte var x12748 [1 << 17]byte var x12749 [1 << 17]byte var x12750 [1 << 17]byte var x12751 [1 << 17]byte var x12752 [1 << 17]byte var x12753 [1 << 17]byte var x12754 [1 << 17]byte var x12755 [1 << 17]byte var x12756 [1 << 17]byte var x12757 [1 << 17]byte var x12758 [1 << 17]byte var x12759 [1 << 17]byte var x12760 [1 << 17]byte var x12761 [1 << 17]byte var x12762 [1 << 17]byte var x12763 [1 << 17]byte var x12764 [1 << 17]byte var x12765 [1 << 17]byte var x12766 [1 << 17]byte var x12767 [1 << 17]byte var x12768 [1 << 17]byte var x12769 [1 << 17]byte var x12770 [1 << 17]byte var x12771 [1 << 17]byte var x12772 [1 << 17]byte var x12773 [1 << 17]byte var x12774 [1 << 17]byte var x12775 [1 << 17]byte var x12776 [1 << 17]byte var x12777 [1 << 17]byte var x12778 [1 << 17]byte var x12779 [1 << 17]byte var x12780 [1 << 17]byte var x12781 [1 << 17]byte var x12782 [1 << 17]byte var x12783 [1 << 17]byte var x12784 [1 << 17]byte var x12785 [1 << 17]byte var x12786 [1 << 17]byte var x12787 [1 << 17]byte var x12788 [1 << 17]byte var x12789 [1 << 17]byte var x12790 [1 << 17]byte var x12791 [1 << 17]byte var x12792 [1 << 17]byte var x12793 [1 << 17]byte var x12794 [1 << 17]byte var x12795 [1 << 17]byte var x12796 [1 << 17]byte var x12797 [1 << 17]byte var x12798 [1 << 17]byte var x12799 [1 << 17]byte var x12800 [1 << 17]byte var x12801 [1 << 17]byte var x12802 [1 << 17]byte var x12803 [1 << 17]byte var x12804 [1 << 17]byte var x12805 [1 << 17]byte var x12806 [1 << 17]byte var x12807 [1 << 17]byte var x12808 [1 << 17]byte var x12809 [1 << 17]byte var x12810 [1 << 17]byte var x12811 [1 << 17]byte var x12812 [1 << 17]byte var x12813 [1 << 17]byte var x12814 [1 << 17]byte var x12815 [1 << 17]byte var x12816 [1 << 17]byte var x12817 [1 << 17]byte var x12818 [1 << 17]byte var x12819 [1 << 17]byte var x12820 [1 << 17]byte var x12821 [1 << 17]byte var x12822 [1 << 17]byte var x12823 [1 << 17]byte var x12824 [1 << 17]byte var x12825 [1 << 17]byte var x12826 [1 << 17]byte var x12827 [1 << 17]byte var x12828 [1 << 17]byte var x12829 [1 << 17]byte var x12830 [1 << 17]byte var x12831 [1 << 17]byte var x12832 [1 << 17]byte var x12833 [1 << 17]byte var x12834 [1 << 17]byte var x12835 [1 << 17]byte var x12836 [1 << 17]byte var x12837 [1 << 17]byte var x12838 [1 << 17]byte var x12839 [1 << 17]byte var x12840 [1 << 17]byte var x12841 [1 << 17]byte var x12842 [1 << 17]byte var x12843 [1 << 17]byte var x12844 [1 << 17]byte var x12845 [1 << 17]byte var x12846 [1 << 17]byte var x12847 [1 << 17]byte var x12848 [1 << 17]byte var x12849 [1 << 17]byte var x12850 [1 << 17]byte var x12851 [1 << 17]byte var x12852 [1 << 17]byte var x12853 [1 << 17]byte var x12854 [1 << 17]byte var x12855 [1 << 17]byte var x12856 [1 << 17]byte var x12857 [1 << 17]byte var x12858 [1 << 17]byte var x12859 [1 << 17]byte var x12860 [1 << 17]byte var x12861 [1 << 17]byte var x12862 [1 << 17]byte var x12863 [1 << 17]byte var x12864 [1 << 17]byte var x12865 [1 << 17]byte var x12866 [1 << 17]byte var x12867 [1 << 17]byte var x12868 [1 << 17]byte var x12869 [1 << 17]byte var x12870 [1 << 17]byte var x12871 [1 << 17]byte var x12872 [1 << 17]byte var x12873 [1 << 17]byte var x12874 [1 << 17]byte var x12875 [1 << 17]byte var x12876 [1 << 17]byte var x12877 [1 << 17]byte var x12878 [1 << 17]byte var x12879 [1 << 17]byte var x12880 [1 << 17]byte var x12881 [1 << 17]byte var x12882 [1 << 17]byte var x12883 [1 << 17]byte var x12884 [1 << 17]byte var x12885 [1 << 17]byte var x12886 [1 << 17]byte var x12887 [1 << 17]byte var x12888 [1 << 17]byte var x12889 [1 << 17]byte var x12890 [1 << 17]byte var x12891 [1 << 17]byte var x12892 [1 << 17]byte var x12893 [1 << 17]byte var x12894 [1 << 17]byte var x12895 [1 << 17]byte var x12896 [1 << 17]byte var x12897 [1 << 17]byte var x12898 [1 << 17]byte var x12899 [1 << 17]byte var x12900 [1 << 17]byte var x12901 [1 << 17]byte var x12902 [1 << 17]byte var x12903 [1 << 17]byte var x12904 [1 << 17]byte var x12905 [1 << 17]byte var x12906 [1 << 17]byte var x12907 [1 << 17]byte var x12908 [1 << 17]byte var x12909 [1 << 17]byte var x12910 [1 << 17]byte var x12911 [1 << 17]byte var x12912 [1 << 17]byte var x12913 [1 << 17]byte var x12914 [1 << 17]byte var x12915 [1 << 17]byte var x12916 [1 << 17]byte var x12917 [1 << 17]byte var x12918 [1 << 17]byte var x12919 [1 << 17]byte var x12920 [1 << 17]byte var x12921 [1 << 17]byte var x12922 [1 << 17]byte var x12923 [1 << 17]byte var x12924 [1 << 17]byte var x12925 [1 << 17]byte var x12926 [1 << 17]byte var x12927 [1 << 17]byte var x12928 [1 << 17]byte var x12929 [1 << 17]byte var x12930 [1 << 17]byte var x12931 [1 << 17]byte var x12932 [1 << 17]byte var x12933 [1 << 17]byte var x12934 [1 << 17]byte var x12935 [1 << 17]byte var x12936 [1 << 17]byte var x12937 [1 << 17]byte var x12938 [1 << 17]byte var x12939 [1 << 17]byte var x12940 [1 << 17]byte var x12941 [1 << 17]byte var x12942 [1 << 17]byte var x12943 [1 << 17]byte var x12944 [1 << 17]byte var x12945 [1 << 17]byte var x12946 [1 << 17]byte var x12947 [1 << 17]byte var x12948 [1 << 17]byte var x12949 [1 << 17]byte var x12950 [1 << 17]byte var x12951 [1 << 17]byte var x12952 [1 << 17]byte var x12953 [1 << 17]byte var x12954 [1 << 17]byte var x12955 [1 << 17]byte var x12956 [1 << 17]byte var x12957 [1 << 17]byte var x12958 [1 << 17]byte var x12959 [1 << 17]byte var x12960 [1 << 17]byte var x12961 [1 << 17]byte var x12962 [1 << 17]byte var x12963 [1 << 17]byte var x12964 [1 << 17]byte var x12965 [1 << 17]byte var x12966 [1 << 17]byte var x12967 [1 << 17]byte var x12968 [1 << 17]byte var x12969 [1 << 17]byte var x12970 [1 << 17]byte var x12971 [1 << 17]byte var x12972 [1 << 17]byte var x12973 [1 << 17]byte var x12974 [1 << 17]byte var x12975 [1 << 17]byte var x12976 [1 << 17]byte var x12977 [1 << 17]byte var x12978 [1 << 17]byte var x12979 [1 << 17]byte var x12980 [1 << 17]byte var x12981 [1 << 17]byte var x12982 [1 << 17]byte var x12983 [1 << 17]byte var x12984 [1 << 17]byte var x12985 [1 << 17]byte var x12986 [1 << 17]byte var x12987 [1 << 17]byte var x12988 [1 << 17]byte var x12989 [1 << 17]byte var x12990 [1 << 17]byte var x12991 [1 << 17]byte var x12992 [1 << 17]byte var x12993 [1 << 17]byte var x12994 [1 << 17]byte var x12995 [1 << 17]byte var x12996 [1 << 17]byte var x12997 [1 << 17]byte var x12998 [1 << 17]byte var x12999 [1 << 17]byte var x13000 [1 << 17]byte var x13001 [1 << 17]byte var x13002 [1 << 17]byte var x13003 [1 << 17]byte var x13004 [1 << 17]byte var x13005 [1 << 17]byte var x13006 [1 << 17]byte var x13007 [1 << 17]byte var x13008 [1 << 17]byte var x13009 [1 << 17]byte var x13010 [1 << 17]byte var x13011 [1 << 17]byte var x13012 [1 << 17]byte var x13013 [1 << 17]byte var x13014 [1 << 17]byte var x13015 [1 << 17]byte var x13016 [1 << 17]byte var x13017 [1 << 17]byte var x13018 [1 << 17]byte var x13019 [1 << 17]byte var x13020 [1 << 17]byte var x13021 [1 << 17]byte var x13022 [1 << 17]byte var x13023 [1 << 17]byte var x13024 [1 << 17]byte var x13025 [1 << 17]byte var x13026 [1 << 17]byte var x13027 [1 << 17]byte var x13028 [1 << 17]byte var x13029 [1 << 17]byte var x13030 [1 << 17]byte var x13031 [1 << 17]byte var x13032 [1 << 17]byte var x13033 [1 << 17]byte var x13034 [1 << 17]byte var x13035 [1 << 17]byte var x13036 [1 << 17]byte var x13037 [1 << 17]byte var x13038 [1 << 17]byte var x13039 [1 << 17]byte var x13040 [1 << 17]byte var x13041 [1 << 17]byte var x13042 [1 << 17]byte var x13043 [1 << 17]byte var x13044 [1 << 17]byte var x13045 [1 << 17]byte var x13046 [1 << 17]byte var x13047 [1 << 17]byte var x13048 [1 << 17]byte var x13049 [1 << 17]byte var x13050 [1 << 17]byte var x13051 [1 << 17]byte var x13052 [1 << 17]byte var x13053 [1 << 17]byte var x13054 [1 << 17]byte var x13055 [1 << 17]byte var x13056 [1 << 17]byte var x13057 [1 << 17]byte var x13058 [1 << 17]byte var x13059 [1 << 17]byte var x13060 [1 << 17]byte var x13061 [1 << 17]byte var x13062 [1 << 17]byte var x13063 [1 << 17]byte var x13064 [1 << 17]byte var x13065 [1 << 17]byte var x13066 [1 << 17]byte var x13067 [1 << 17]byte var x13068 [1 << 17]byte var x13069 [1 << 17]byte var x13070 [1 << 17]byte var x13071 [1 << 17]byte var x13072 [1 << 17]byte var x13073 [1 << 17]byte var x13074 [1 << 17]byte var x13075 [1 << 17]byte var x13076 [1 << 17]byte var x13077 [1 << 17]byte var x13078 [1 << 17]byte var x13079 [1 << 17]byte var x13080 [1 << 17]byte var x13081 [1 << 17]byte var x13082 [1 << 17]byte var x13083 [1 << 17]byte var x13084 [1 << 17]byte var x13085 [1 << 17]byte var x13086 [1 << 17]byte var x13087 [1 << 17]byte var x13088 [1 << 17]byte var x13089 [1 << 17]byte var x13090 [1 << 17]byte var x13091 [1 << 17]byte var x13092 [1 << 17]byte var x13093 [1 << 17]byte var x13094 [1 << 17]byte var x13095 [1 << 17]byte var x13096 [1 << 17]byte var x13097 [1 << 17]byte var x13098 [1 << 17]byte var x13099 [1 << 17]byte var x13100 [1 << 17]byte var x13101 [1 << 17]byte var x13102 [1 << 17]byte var x13103 [1 << 17]byte var x13104 [1 << 17]byte var x13105 [1 << 17]byte var x13106 [1 << 17]byte var x13107 [1 << 17]byte var x13108 [1 << 17]byte var x13109 [1 << 17]byte var x13110 [1 << 17]byte var x13111 [1 << 17]byte var x13112 [1 << 17]byte var x13113 [1 << 17]byte var x13114 [1 << 17]byte var x13115 [1 << 17]byte var x13116 [1 << 17]byte var x13117 [1 << 17]byte var x13118 [1 << 17]byte var x13119 [1 << 17]byte var x13120 [1 << 17]byte var x13121 [1 << 17]byte var x13122 [1 << 17]byte var x13123 [1 << 17]byte var x13124 [1 << 17]byte var x13125 [1 << 17]byte var x13126 [1 << 17]byte var x13127 [1 << 17]byte var x13128 [1 << 17]byte var x13129 [1 << 17]byte var x13130 [1 << 17]byte var x13131 [1 << 17]byte var x13132 [1 << 17]byte var x13133 [1 << 17]byte var x13134 [1 << 17]byte var x13135 [1 << 17]byte var x13136 [1 << 17]byte var x13137 [1 << 17]byte var x13138 [1 << 17]byte var x13139 [1 << 17]byte var x13140 [1 << 17]byte var x13141 [1 << 17]byte var x13142 [1 << 17]byte var x13143 [1 << 17]byte var x13144 [1 << 17]byte var x13145 [1 << 17]byte var x13146 [1 << 17]byte var x13147 [1 << 17]byte var x13148 [1 << 17]byte var x13149 [1 << 17]byte var x13150 [1 << 17]byte var x13151 [1 << 17]byte var x13152 [1 << 17]byte var x13153 [1 << 17]byte var x13154 [1 << 17]byte var x13155 [1 << 17]byte var x13156 [1 << 17]byte var x13157 [1 << 17]byte var x13158 [1 << 17]byte var x13159 [1 << 17]byte var x13160 [1 << 17]byte var x13161 [1 << 17]byte var x13162 [1 << 17]byte var x13163 [1 << 17]byte var x13164 [1 << 17]byte var x13165 [1 << 17]byte var x13166 [1 << 17]byte var x13167 [1 << 17]byte var x13168 [1 << 17]byte var x13169 [1 << 17]byte var x13170 [1 << 17]byte var x13171 [1 << 17]byte var x13172 [1 << 17]byte var x13173 [1 << 17]byte var x13174 [1 << 17]byte var x13175 [1 << 17]byte var x13176 [1 << 17]byte var x13177 [1 << 17]byte var x13178 [1 << 17]byte var x13179 [1 << 17]byte var x13180 [1 << 17]byte var x13181 [1 << 17]byte var x13182 [1 << 17]byte var x13183 [1 << 17]byte var x13184 [1 << 17]byte var x13185 [1 << 17]byte var x13186 [1 << 17]byte var x13187 [1 << 17]byte var x13188 [1 << 17]byte var x13189 [1 << 17]byte var x13190 [1 << 17]byte var x13191 [1 << 17]byte var x13192 [1 << 17]byte var x13193 [1 << 17]byte var x13194 [1 << 17]byte var x13195 [1 << 17]byte var x13196 [1 << 17]byte var x13197 [1 << 17]byte var x13198 [1 << 17]byte var x13199 [1 << 17]byte var x13200 [1 << 17]byte var x13201 [1 << 17]byte var x13202 [1 << 17]byte var x13203 [1 << 17]byte var x13204 [1 << 17]byte var x13205 [1 << 17]byte var x13206 [1 << 17]byte var x13207 [1 << 17]byte var x13208 [1 << 17]byte var x13209 [1 << 17]byte var x13210 [1 << 17]byte var x13211 [1 << 17]byte var x13212 [1 << 17]byte var x13213 [1 << 17]byte var x13214 [1 << 17]byte var x13215 [1 << 17]byte var x13216 [1 << 17]byte var x13217 [1 << 17]byte var x13218 [1 << 17]byte var x13219 [1 << 17]byte var x13220 [1 << 17]byte var x13221 [1 << 17]byte var x13222 [1 << 17]byte var x13223 [1 << 17]byte var x13224 [1 << 17]byte var x13225 [1 << 17]byte var x13226 [1 << 17]byte var x13227 [1 << 17]byte var x13228 [1 << 17]byte var x13229 [1 << 17]byte var x13230 [1 << 17]byte var x13231 [1 << 17]byte var x13232 [1 << 17]byte var x13233 [1 << 17]byte var x13234 [1 << 17]byte var x13235 [1 << 17]byte var x13236 [1 << 17]byte var x13237 [1 << 17]byte var x13238 [1 << 17]byte var x13239 [1 << 17]byte var x13240 [1 << 17]byte var x13241 [1 << 17]byte var x13242 [1 << 17]byte var x13243 [1 << 17]byte var x13244 [1 << 17]byte var x13245 [1 << 17]byte var x13246 [1 << 17]byte var x13247 [1 << 17]byte var x13248 [1 << 17]byte var x13249 [1 << 17]byte var x13250 [1 << 17]byte var x13251 [1 << 17]byte var x13252 [1 << 17]byte var x13253 [1 << 17]byte var x13254 [1 << 17]byte var x13255 [1 << 17]byte var x13256 [1 << 17]byte var x13257 [1 << 17]byte var x13258 [1 << 17]byte var x13259 [1 << 17]byte var x13260 [1 << 17]byte var x13261 [1 << 17]byte var x13262 [1 << 17]byte var x13263 [1 << 17]byte var x13264 [1 << 17]byte var x13265 [1 << 17]byte var x13266 [1 << 17]byte var x13267 [1 << 17]byte var x13268 [1 << 17]byte var x13269 [1 << 17]byte var x13270 [1 << 17]byte var x13271 [1 << 17]byte var x13272 [1 << 17]byte var x13273 [1 << 17]byte var x13274 [1 << 17]byte var x13275 [1 << 17]byte var x13276 [1 << 17]byte var x13277 [1 << 17]byte var x13278 [1 << 17]byte var x13279 [1 << 17]byte var x13280 [1 << 17]byte var x13281 [1 << 17]byte var x13282 [1 << 17]byte var x13283 [1 << 17]byte var x13284 [1 << 17]byte var x13285 [1 << 17]byte var x13286 [1 << 17]byte var x13287 [1 << 17]byte var x13288 [1 << 17]byte var x13289 [1 << 17]byte var x13290 [1 << 17]byte var x13291 [1 << 17]byte var x13292 [1 << 17]byte var x13293 [1 << 17]byte var x13294 [1 << 17]byte var x13295 [1 << 17]byte var x13296 [1 << 17]byte var x13297 [1 << 17]byte var x13298 [1 << 17]byte var x13299 [1 << 17]byte var x13300 [1 << 17]byte var x13301 [1 << 17]byte var x13302 [1 << 17]byte var x13303 [1 << 17]byte var x13304 [1 << 17]byte var x13305 [1 << 17]byte var x13306 [1 << 17]byte var x13307 [1 << 17]byte var x13308 [1 << 17]byte var x13309 [1 << 17]byte var x13310 [1 << 17]byte var x13311 [1 << 17]byte var x13312 [1 << 17]byte var x13313 [1 << 17]byte var x13314 [1 << 17]byte var x13315 [1 << 17]byte var x13316 [1 << 17]byte var x13317 [1 << 17]byte var x13318 [1 << 17]byte var x13319 [1 << 17]byte var x13320 [1 << 17]byte var x13321 [1 << 17]byte var x13322 [1 << 17]byte var x13323 [1 << 17]byte var x13324 [1 << 17]byte var x13325 [1 << 17]byte var x13326 [1 << 17]byte var x13327 [1 << 17]byte var x13328 [1 << 17]byte var x13329 [1 << 17]byte var x13330 [1 << 17]byte var x13331 [1 << 17]byte var x13332 [1 << 17]byte var x13333 [1 << 17]byte var x13334 [1 << 17]byte var x13335 [1 << 17]byte var x13336 [1 << 17]byte var x13337 [1 << 17]byte var x13338 [1 << 17]byte var x13339 [1 << 17]byte var x13340 [1 << 17]byte var x13341 [1 << 17]byte var x13342 [1 << 17]byte var x13343 [1 << 17]byte var x13344 [1 << 17]byte var x13345 [1 << 17]byte var x13346 [1 << 17]byte var x13347 [1 << 17]byte var x13348 [1 << 17]byte var x13349 [1 << 17]byte var x13350 [1 << 17]byte var x13351 [1 << 17]byte var x13352 [1 << 17]byte var x13353 [1 << 17]byte var x13354 [1 << 17]byte var x13355 [1 << 17]byte var x13356 [1 << 17]byte var x13357 [1 << 17]byte var x13358 [1 << 17]byte var x13359 [1 << 17]byte var x13360 [1 << 17]byte var x13361 [1 << 17]byte var x13362 [1 << 17]byte var x13363 [1 << 17]byte var x13364 [1 << 17]byte var x13365 [1 << 17]byte var x13366 [1 << 17]byte var x13367 [1 << 17]byte var x13368 [1 << 17]byte var x13369 [1 << 17]byte var x13370 [1 << 17]byte var x13371 [1 << 17]byte var x13372 [1 << 17]byte var x13373 [1 << 17]byte var x13374 [1 << 17]byte var x13375 [1 << 17]byte var x13376 [1 << 17]byte var x13377 [1 << 17]byte var x13378 [1 << 17]byte var x13379 [1 << 17]byte var x13380 [1 << 17]byte var x13381 [1 << 17]byte var x13382 [1 << 17]byte var x13383 [1 << 17]byte var x13384 [1 << 17]byte var x13385 [1 << 17]byte var x13386 [1 << 17]byte var x13387 [1 << 17]byte var x13388 [1 << 17]byte var x13389 [1 << 17]byte var x13390 [1 << 17]byte var x13391 [1 << 17]byte var x13392 [1 << 17]byte var x13393 [1 << 17]byte var x13394 [1 << 17]byte var x13395 [1 << 17]byte var x13396 [1 << 17]byte var x13397 [1 << 17]byte var x13398 [1 << 17]byte var x13399 [1 << 17]byte var x13400 [1 << 17]byte var x13401 [1 << 17]byte var x13402 [1 << 17]byte var x13403 [1 << 17]byte var x13404 [1 << 17]byte var x13405 [1 << 17]byte var x13406 [1 << 17]byte var x13407 [1 << 17]byte var x13408 [1 << 17]byte var x13409 [1 << 17]byte var x13410 [1 << 17]byte var x13411 [1 << 17]byte var x13412 [1 << 17]byte var x13413 [1 << 17]byte var x13414 [1 << 17]byte var x13415 [1 << 17]byte var x13416 [1 << 17]byte var x13417 [1 << 17]byte var x13418 [1 << 17]byte var x13419 [1 << 17]byte var x13420 [1 << 17]byte var x13421 [1 << 17]byte var x13422 [1 << 17]byte var x13423 [1 << 17]byte var x13424 [1 << 17]byte var x13425 [1 << 17]byte var x13426 [1 << 17]byte var x13427 [1 << 17]byte var x13428 [1 << 17]byte var x13429 [1 << 17]byte var x13430 [1 << 17]byte var x13431 [1 << 17]byte var x13432 [1 << 17]byte var x13433 [1 << 17]byte var x13434 [1 << 17]byte var x13435 [1 << 17]byte var x13436 [1 << 17]byte var x13437 [1 << 17]byte var x13438 [1 << 17]byte var x13439 [1 << 17]byte var x13440 [1 << 17]byte var x13441 [1 << 17]byte var x13442 [1 << 17]byte var x13443 [1 << 17]byte var x13444 [1 << 17]byte var x13445 [1 << 17]byte var x13446 [1 << 17]byte var x13447 [1 << 17]byte var x13448 [1 << 17]byte var x13449 [1 << 17]byte var x13450 [1 << 17]byte var x13451 [1 << 17]byte var x13452 [1 << 17]byte var x13453 [1 << 17]byte var x13454 [1 << 17]byte var x13455 [1 << 17]byte var x13456 [1 << 17]byte var x13457 [1 << 17]byte var x13458 [1 << 17]byte var x13459 [1 << 17]byte var x13460 [1 << 17]byte var x13461 [1 << 17]byte var x13462 [1 << 17]byte var x13463 [1 << 17]byte var x13464 [1 << 17]byte var x13465 [1 << 17]byte var x13466 [1 << 17]byte var x13467 [1 << 17]byte var x13468 [1 << 17]byte var x13469 [1 << 17]byte var x13470 [1 << 17]byte var x13471 [1 << 17]byte var x13472 [1 << 17]byte var x13473 [1 << 17]byte var x13474 [1 << 17]byte var x13475 [1 << 17]byte var x13476 [1 << 17]byte var x13477 [1 << 17]byte var x13478 [1 << 17]byte var x13479 [1 << 17]byte var x13480 [1 << 17]byte var x13481 [1 << 17]byte var x13482 [1 << 17]byte var x13483 [1 << 17]byte var x13484 [1 << 17]byte var x13485 [1 << 17]byte var x13486 [1 << 17]byte var x13487 [1 << 17]byte var x13488 [1 << 17]byte var x13489 [1 << 17]byte var x13490 [1 << 17]byte var x13491 [1 << 17]byte var x13492 [1 << 17]byte var x13493 [1 << 17]byte var x13494 [1 << 17]byte var x13495 [1 << 17]byte var x13496 [1 << 17]byte var x13497 [1 << 17]byte var x13498 [1 << 17]byte var x13499 [1 << 17]byte var x13500 [1 << 17]byte var x13501 [1 << 17]byte var x13502 [1 << 17]byte var x13503 [1 << 17]byte var x13504 [1 << 17]byte var x13505 [1 << 17]byte var x13506 [1 << 17]byte var x13507 [1 << 17]byte var x13508 [1 << 17]byte var x13509 [1 << 17]byte var x13510 [1 << 17]byte var x13511 [1 << 17]byte var x13512 [1 << 17]byte var x13513 [1 << 17]byte var x13514 [1 << 17]byte var x13515 [1 << 17]byte var x13516 [1 << 17]byte var x13517 [1 << 17]byte var x13518 [1 << 17]byte var x13519 [1 << 17]byte var x13520 [1 << 17]byte var x13521 [1 << 17]byte var x13522 [1 << 17]byte var x13523 [1 << 17]byte var x13524 [1 << 17]byte var x13525 [1 << 17]byte var x13526 [1 << 17]byte var x13527 [1 << 17]byte var x13528 [1 << 17]byte var x13529 [1 << 17]byte var x13530 [1 << 17]byte var x13531 [1 << 17]byte var x13532 [1 << 17]byte var x13533 [1 << 17]byte var x13534 [1 << 17]byte var x13535 [1 << 17]byte var x13536 [1 << 17]byte var x13537 [1 << 17]byte var x13538 [1 << 17]byte var x13539 [1 << 17]byte var x13540 [1 << 17]byte var x13541 [1 << 17]byte var x13542 [1 << 17]byte var x13543 [1 << 17]byte var x13544 [1 << 17]byte var x13545 [1 << 17]byte var x13546 [1 << 17]byte var x13547 [1 << 17]byte var x13548 [1 << 17]byte var x13549 [1 << 17]byte var x13550 [1 << 17]byte var x13551 [1 << 17]byte var x13552 [1 << 17]byte var x13553 [1 << 17]byte var x13554 [1 << 17]byte var x13555 [1 << 17]byte var x13556 [1 << 17]byte var x13557 [1 << 17]byte var x13558 [1 << 17]byte var x13559 [1 << 17]byte var x13560 [1 << 17]byte var x13561 [1 << 17]byte var x13562 [1 << 17]byte var x13563 [1 << 17]byte var x13564 [1 << 17]byte var x13565 [1 << 17]byte var x13566 [1 << 17]byte var x13567 [1 << 17]byte var x13568 [1 << 17]byte var x13569 [1 << 17]byte var x13570 [1 << 17]byte var x13571 [1 << 17]byte var x13572 [1 << 17]byte var x13573 [1 << 17]byte var x13574 [1 << 17]byte var x13575 [1 << 17]byte var x13576 [1 << 17]byte var x13577 [1 << 17]byte var x13578 [1 << 17]byte var x13579 [1 << 17]byte var x13580 [1 << 17]byte var x13581 [1 << 17]byte var x13582 [1 << 17]byte var x13583 [1 << 17]byte var x13584 [1 << 17]byte var x13585 [1 << 17]byte var x13586 [1 << 17]byte var x13587 [1 << 17]byte var x13588 [1 << 17]byte var x13589 [1 << 17]byte var x13590 [1 << 17]byte var x13591 [1 << 17]byte var x13592 [1 << 17]byte var x13593 [1 << 17]byte var x13594 [1 << 17]byte var x13595 [1 << 17]byte var x13596 [1 << 17]byte var x13597 [1 << 17]byte var x13598 [1 << 17]byte var x13599 [1 << 17]byte var x13600 [1 << 17]byte var x13601 [1 << 17]byte var x13602 [1 << 17]byte var x13603 [1 << 17]byte var x13604 [1 << 17]byte var x13605 [1 << 17]byte var x13606 [1 << 17]byte var x13607 [1 << 17]byte var x13608 [1 << 17]byte var x13609 [1 << 17]byte var x13610 [1 << 17]byte var x13611 [1 << 17]byte var x13612 [1 << 17]byte var x13613 [1 << 17]byte var x13614 [1 << 17]byte var x13615 [1 << 17]byte var x13616 [1 << 17]byte var x13617 [1 << 17]byte var x13618 [1 << 17]byte var x13619 [1 << 17]byte var x13620 [1 << 17]byte var x13621 [1 << 17]byte var x13622 [1 << 17]byte var x13623 [1 << 17]byte var x13624 [1 << 17]byte var x13625 [1 << 17]byte var x13626 [1 << 17]byte var x13627 [1 << 17]byte var x13628 [1 << 17]byte var x13629 [1 << 17]byte var x13630 [1 << 17]byte var x13631 [1 << 17]byte var x13632 [1 << 17]byte var x13633 [1 << 17]byte var x13634 [1 << 17]byte var x13635 [1 << 17]byte var x13636 [1 << 17]byte var x13637 [1 << 17]byte var x13638 [1 << 17]byte var x13639 [1 << 17]byte var x13640 [1 << 17]byte var x13641 [1 << 17]byte var x13642 [1 << 17]byte var x13643 [1 << 17]byte var x13644 [1 << 17]byte var x13645 [1 << 17]byte var x13646 [1 << 17]byte var x13647 [1 << 17]byte var x13648 [1 << 17]byte var x13649 [1 << 17]byte var x13650 [1 << 17]byte var x13651 [1 << 17]byte var x13652 [1 << 17]byte var x13653 [1 << 17]byte var x13654 [1 << 17]byte var x13655 [1 << 17]byte var x13656 [1 << 17]byte var x13657 [1 << 17]byte var x13658 [1 << 17]byte var x13659 [1 << 17]byte var x13660 [1 << 17]byte var x13661 [1 << 17]byte var x13662 [1 << 17]byte var x13663 [1 << 17]byte var x13664 [1 << 17]byte var x13665 [1 << 17]byte var x13666 [1 << 17]byte var x13667 [1 << 17]byte var x13668 [1 << 17]byte var x13669 [1 << 17]byte var x13670 [1 << 17]byte var x13671 [1 << 17]byte var x13672 [1 << 17]byte var x13673 [1 << 17]byte var x13674 [1 << 17]byte var x13675 [1 << 17]byte var x13676 [1 << 17]byte var x13677 [1 << 17]byte var x13678 [1 << 17]byte var x13679 [1 << 17]byte var x13680 [1 << 17]byte var x13681 [1 << 17]byte var x13682 [1 << 17]byte var x13683 [1 << 17]byte var x13684 [1 << 17]byte var x13685 [1 << 17]byte var x13686 [1 << 17]byte var x13687 [1 << 17]byte var x13688 [1 << 17]byte var x13689 [1 << 17]byte var x13690 [1 << 17]byte var x13691 [1 << 17]byte var x13692 [1 << 17]byte var x13693 [1 << 17]byte var x13694 [1 << 17]byte var x13695 [1 << 17]byte var x13696 [1 << 17]byte var x13697 [1 << 17]byte var x13698 [1 << 17]byte var x13699 [1 << 17]byte var x13700 [1 << 17]byte var x13701 [1 << 17]byte var x13702 [1 << 17]byte var x13703 [1 << 17]byte var x13704 [1 << 17]byte var x13705 [1 << 17]byte var x13706 [1 << 17]byte var x13707 [1 << 17]byte var x13708 [1 << 17]byte var x13709 [1 << 17]byte var x13710 [1 << 17]byte var x13711 [1 << 17]byte var x13712 [1 << 17]byte var x13713 [1 << 17]byte var x13714 [1 << 17]byte var x13715 [1 << 17]byte var x13716 [1 << 17]byte var x13717 [1 << 17]byte var x13718 [1 << 17]byte var x13719 [1 << 17]byte var x13720 [1 << 17]byte var x13721 [1 << 17]byte var x13722 [1 << 17]byte var x13723 [1 << 17]byte var x13724 [1 << 17]byte var x13725 [1 << 17]byte var x13726 [1 << 17]byte var x13727 [1 << 17]byte var x13728 [1 << 17]byte var x13729 [1 << 17]byte var x13730 [1 << 17]byte var x13731 [1 << 17]byte var x13732 [1 << 17]byte var x13733 [1 << 17]byte var x13734 [1 << 17]byte var x13735 [1 << 17]byte var x13736 [1 << 17]byte var x13737 [1 << 17]byte var x13738 [1 << 17]byte var x13739 [1 << 17]byte var x13740 [1 << 17]byte var x13741 [1 << 17]byte var x13742 [1 << 17]byte var x13743 [1 << 17]byte var x13744 [1 << 17]byte var x13745 [1 << 17]byte var x13746 [1 << 17]byte var x13747 [1 << 17]byte var x13748 [1 << 17]byte var x13749 [1 << 17]byte var x13750 [1 << 17]byte var x13751 [1 << 17]byte var x13752 [1 << 17]byte var x13753 [1 << 17]byte var x13754 [1 << 17]byte var x13755 [1 << 17]byte var x13756 [1 << 17]byte var x13757 [1 << 17]byte var x13758 [1 << 17]byte var x13759 [1 << 17]byte var x13760 [1 << 17]byte var x13761 [1 << 17]byte var x13762 [1 << 17]byte var x13763 [1 << 17]byte var x13764 [1 << 17]byte var x13765 [1 << 17]byte var x13766 [1 << 17]byte var x13767 [1 << 17]byte var x13768 [1 << 17]byte var x13769 [1 << 17]byte var x13770 [1 << 17]byte var x13771 [1 << 17]byte var x13772 [1 << 17]byte var x13773 [1 << 17]byte var x13774 [1 << 17]byte var x13775 [1 << 17]byte var x13776 [1 << 17]byte var x13777 [1 << 17]byte var x13778 [1 << 17]byte var x13779 [1 << 17]byte var x13780 [1 << 17]byte var x13781 [1 << 17]byte var x13782 [1 << 17]byte var x13783 [1 << 17]byte var x13784 [1 << 17]byte var x13785 [1 << 17]byte var x13786 [1 << 17]byte var x13787 [1 << 17]byte var x13788 [1 << 17]byte var x13789 [1 << 17]byte var x13790 [1 << 17]byte var x13791 [1 << 17]byte var x13792 [1 << 17]byte var x13793 [1 << 17]byte var x13794 [1 << 17]byte var x13795 [1 << 17]byte var x13796 [1 << 17]byte var x13797 [1 << 17]byte var x13798 [1 << 17]byte var x13799 [1 << 17]byte var x13800 [1 << 17]byte var x13801 [1 << 17]byte var x13802 [1 << 17]byte var x13803 [1 << 17]byte var x13804 [1 << 17]byte var x13805 [1 << 17]byte var x13806 [1 << 17]byte var x13807 [1 << 17]byte var x13808 [1 << 17]byte var x13809 [1 << 17]byte var x13810 [1 << 17]byte var x13811 [1 << 17]byte var x13812 [1 << 17]byte var x13813 [1 << 17]byte var x13814 [1 << 17]byte var x13815 [1 << 17]byte var x13816 [1 << 17]byte var x13817 [1 << 17]byte var x13818 [1 << 17]byte var x13819 [1 << 17]byte var x13820 [1 << 17]byte var x13821 [1 << 17]byte var x13822 [1 << 17]byte var x13823 [1 << 17]byte var x13824 [1 << 17]byte var x13825 [1 << 17]byte var x13826 [1 << 17]byte var x13827 [1 << 17]byte var x13828 [1 << 17]byte var x13829 [1 << 17]byte var x13830 [1 << 17]byte var x13831 [1 << 17]byte var x13832 [1 << 17]byte var x13833 [1 << 17]byte var x13834 [1 << 17]byte var x13835 [1 << 17]byte var x13836 [1 << 17]byte var x13837 [1 << 17]byte var x13838 [1 << 17]byte var x13839 [1 << 17]byte var x13840 [1 << 17]byte var x13841 [1 << 17]byte var x13842 [1 << 17]byte var x13843 [1 << 17]byte var x13844 [1 << 17]byte var x13845 [1 << 17]byte var x13846 [1 << 17]byte var x13847 [1 << 17]byte var x13848 [1 << 17]byte var x13849 [1 << 17]byte var x13850 [1 << 17]byte var x13851 [1 << 17]byte var x13852 [1 << 17]byte var x13853 [1 << 17]byte var x13854 [1 << 17]byte var x13855 [1 << 17]byte var x13856 [1 << 17]byte var x13857 [1 << 17]byte var x13858 [1 << 17]byte var x13859 [1 << 17]byte var x13860 [1 << 17]byte var x13861 [1 << 17]byte var x13862 [1 << 17]byte var x13863 [1 << 17]byte var x13864 [1 << 17]byte var x13865 [1 << 17]byte var x13866 [1 << 17]byte var x13867 [1 << 17]byte var x13868 [1 << 17]byte var x13869 [1 << 17]byte var x13870 [1 << 17]byte var x13871 [1 << 17]byte var x13872 [1 << 17]byte var x13873 [1 << 17]byte var x13874 [1 << 17]byte var x13875 [1 << 17]byte var x13876 [1 << 17]byte var x13877 [1 << 17]byte var x13878 [1 << 17]byte var x13879 [1 << 17]byte var x13880 [1 << 17]byte var x13881 [1 << 17]byte var x13882 [1 << 17]byte var x13883 [1 << 17]byte var x13884 [1 << 17]byte var x13885 [1 << 17]byte var x13886 [1 << 17]byte var x13887 [1 << 17]byte var x13888 [1 << 17]byte var x13889 [1 << 17]byte var x13890 [1 << 17]byte var x13891 [1 << 17]byte var x13892 [1 << 17]byte var x13893 [1 << 17]byte var x13894 [1 << 17]byte var x13895 [1 << 17]byte var x13896 [1 << 17]byte var x13897 [1 << 17]byte var x13898 [1 << 17]byte var x13899 [1 << 17]byte var x13900 [1 << 17]byte var x13901 [1 << 17]byte var x13902 [1 << 17]byte var x13903 [1 << 17]byte var x13904 [1 << 17]byte var x13905 [1 << 17]byte var x13906 [1 << 17]byte var x13907 [1 << 17]byte var x13908 [1 << 17]byte var x13909 [1 << 17]byte var x13910 [1 << 17]byte var x13911 [1 << 17]byte var x13912 [1 << 17]byte var x13913 [1 << 17]byte var x13914 [1 << 17]byte var x13915 [1 << 17]byte var x13916 [1 << 17]byte var x13917 [1 << 17]byte var x13918 [1 << 17]byte var x13919 [1 << 17]byte var x13920 [1 << 17]byte var x13921 [1 << 17]byte var x13922 [1 << 17]byte var x13923 [1 << 17]byte var x13924 [1 << 17]byte var x13925 [1 << 17]byte var x13926 [1 << 17]byte var x13927 [1 << 17]byte var x13928 [1 << 17]byte var x13929 [1 << 17]byte var x13930 [1 << 17]byte var x13931 [1 << 17]byte var x13932 [1 << 17]byte var x13933 [1 << 17]byte var x13934 [1 << 17]byte var x13935 [1 << 17]byte var x13936 [1 << 17]byte var x13937 [1 << 17]byte var x13938 [1 << 17]byte var x13939 [1 << 17]byte var x13940 [1 << 17]byte var x13941 [1 << 17]byte var x13942 [1 << 17]byte var x13943 [1 << 17]byte var x13944 [1 << 17]byte var x13945 [1 << 17]byte var x13946 [1 << 17]byte var x13947 [1 << 17]byte var x13948 [1 << 17]byte var x13949 [1 << 17]byte var x13950 [1 << 17]byte var x13951 [1 << 17]byte var x13952 [1 << 17]byte var x13953 [1 << 17]byte var x13954 [1 << 17]byte var x13955 [1 << 17]byte var x13956 [1 << 17]byte var x13957 [1 << 17]byte var x13958 [1 << 17]byte var x13959 [1 << 17]byte var x13960 [1 << 17]byte var x13961 [1 << 17]byte var x13962 [1 << 17]byte var x13963 [1 << 17]byte var x13964 [1 << 17]byte var x13965 [1 << 17]byte var x13966 [1 << 17]byte var x13967 [1 << 17]byte var x13968 [1 << 17]byte var x13969 [1 << 17]byte var x13970 [1 << 17]byte var x13971 [1 << 17]byte var x13972 [1 << 17]byte var x13973 [1 << 17]byte var x13974 [1 << 17]byte var x13975 [1 << 17]byte var x13976 [1 << 17]byte var x13977 [1 << 17]byte var x13978 [1 << 17]byte var x13979 [1 << 17]byte var x13980 [1 << 17]byte var x13981 [1 << 17]byte var x13982 [1 << 17]byte var x13983 [1 << 17]byte var x13984 [1 << 17]byte var x13985 [1 << 17]byte var x13986 [1 << 17]byte var x13987 [1 << 17]byte var x13988 [1 << 17]byte var x13989 [1 << 17]byte var x13990 [1 << 17]byte var x13991 [1 << 17]byte var x13992 [1 << 17]byte var x13993 [1 << 17]byte var x13994 [1 << 17]byte var x13995 [1 << 17]byte var x13996 [1 << 17]byte var x13997 [1 << 17]byte var x13998 [1 << 17]byte var x13999 [1 << 17]byte var x14000 [1 << 17]byte var x14001 [1 << 17]byte var x14002 [1 << 17]byte var x14003 [1 << 17]byte var x14004 [1 << 17]byte var x14005 [1 << 17]byte var x14006 [1 << 17]byte var x14007 [1 << 17]byte var x14008 [1 << 17]byte var x14009 [1 << 17]byte var x14010 [1 << 17]byte var x14011 [1 << 17]byte var x14012 [1 << 17]byte var x14013 [1 << 17]byte var x14014 [1 << 17]byte var x14015 [1 << 17]byte var x14016 [1 << 17]byte var x14017 [1 << 17]byte var x14018 [1 << 17]byte var x14019 [1 << 17]byte var x14020 [1 << 17]byte var x14021 [1 << 17]byte var x14022 [1 << 17]byte var x14023 [1 << 17]byte var x14024 [1 << 17]byte var x14025 [1 << 17]byte var x14026 [1 << 17]byte var x14027 [1 << 17]byte var x14028 [1 << 17]byte var x14029 [1 << 17]byte var x14030 [1 << 17]byte var x14031 [1 << 17]byte var x14032 [1 << 17]byte var x14033 [1 << 17]byte var x14034 [1 << 17]byte var x14035 [1 << 17]byte var x14036 [1 << 17]byte var x14037 [1 << 17]byte var x14038 [1 << 17]byte var x14039 [1 << 17]byte var x14040 [1 << 17]byte var x14041 [1 << 17]byte var x14042 [1 << 17]byte var x14043 [1 << 17]byte var x14044 [1 << 17]byte var x14045 [1 << 17]byte var x14046 [1 << 17]byte var x14047 [1 << 17]byte var x14048 [1 << 17]byte var x14049 [1 << 17]byte var x14050 [1 << 17]byte var x14051 [1 << 17]byte var x14052 [1 << 17]byte var x14053 [1 << 17]byte var x14054 [1 << 17]byte var x14055 [1 << 17]byte var x14056 [1 << 17]byte var x14057 [1 << 17]byte var x14058 [1 << 17]byte var x14059 [1 << 17]byte var x14060 [1 << 17]byte var x14061 [1 << 17]byte var x14062 [1 << 17]byte var x14063 [1 << 17]byte var x14064 [1 << 17]byte var x14065 [1 << 17]byte var x14066 [1 << 17]byte var x14067 [1 << 17]byte var x14068 [1 << 17]byte var x14069 [1 << 17]byte var x14070 [1 << 17]byte var x14071 [1 << 17]byte var x14072 [1 << 17]byte var x14073 [1 << 17]byte var x14074 [1 << 17]byte var x14075 [1 << 17]byte var x14076 [1 << 17]byte var x14077 [1 << 17]byte var x14078 [1 << 17]byte var x14079 [1 << 17]byte var x14080 [1 << 17]byte var x14081 [1 << 17]byte var x14082 [1 << 17]byte var x14083 [1 << 17]byte var x14084 [1 << 17]byte var x14085 [1 << 17]byte var x14086 [1 << 17]byte var x14087 [1 << 17]byte var x14088 [1 << 17]byte var x14089 [1 << 17]byte var x14090 [1 << 17]byte var x14091 [1 << 17]byte var x14092 [1 << 17]byte var x14093 [1 << 17]byte var x14094 [1 << 17]byte var x14095 [1 << 17]byte var x14096 [1 << 17]byte var x14097 [1 << 17]byte var x14098 [1 << 17]byte var x14099 [1 << 17]byte var x14100 [1 << 17]byte var x14101 [1 << 17]byte var x14102 [1 << 17]byte var x14103 [1 << 17]byte var x14104 [1 << 17]byte var x14105 [1 << 17]byte var x14106 [1 << 17]byte var x14107 [1 << 17]byte var x14108 [1 << 17]byte var x14109 [1 << 17]byte var x14110 [1 << 17]byte var x14111 [1 << 17]byte var x14112 [1 << 17]byte var x14113 [1 << 17]byte var x14114 [1 << 17]byte var x14115 [1 << 17]byte var x14116 [1 << 17]byte var x14117 [1 << 17]byte var x14118 [1 << 17]byte var x14119 [1 << 17]byte var x14120 [1 << 17]byte var x14121 [1 << 17]byte var x14122 [1 << 17]byte var x14123 [1 << 17]byte var x14124 [1 << 17]byte var x14125 [1 << 17]byte var x14126 [1 << 17]byte var x14127 [1 << 17]byte var x14128 [1 << 17]byte var x14129 [1 << 17]byte var x14130 [1 << 17]byte var x14131 [1 << 17]byte var x14132 [1 << 17]byte var x14133 [1 << 17]byte var x14134 [1 << 17]byte var x14135 [1 << 17]byte var x14136 [1 << 17]byte var x14137 [1 << 17]byte var x14138 [1 << 17]byte var x14139 [1 << 17]byte var x14140 [1 << 17]byte var x14141 [1 << 17]byte var x14142 [1 << 17]byte var x14143 [1 << 17]byte var x14144 [1 << 17]byte var x14145 [1 << 17]byte var x14146 [1 << 17]byte var x14147 [1 << 17]byte var x14148 [1 << 17]byte var x14149 [1 << 17]byte var x14150 [1 << 17]byte var x14151 [1 << 17]byte var x14152 [1 << 17]byte var x14153 [1 << 17]byte var x14154 [1 << 17]byte var x14155 [1 << 17]byte var x14156 [1 << 17]byte var x14157 [1 << 17]byte var x14158 [1 << 17]byte var x14159 [1 << 17]byte var x14160 [1 << 17]byte var x14161 [1 << 17]byte var x14162 [1 << 17]byte var x14163 [1 << 17]byte var x14164 [1 << 17]byte var x14165 [1 << 17]byte var x14166 [1 << 17]byte var x14167 [1 << 17]byte var x14168 [1 << 17]byte var x14169 [1 << 17]byte var x14170 [1 << 17]byte var x14171 [1 << 17]byte var x14172 [1 << 17]byte var x14173 [1 << 17]byte var x14174 [1 << 17]byte var x14175 [1 << 17]byte var x14176 [1 << 17]byte var x14177 [1 << 17]byte var x14178 [1 << 17]byte var x14179 [1 << 17]byte var x14180 [1 << 17]byte var x14181 [1 << 17]byte var x14182 [1 << 17]byte var x14183 [1 << 17]byte var x14184 [1 << 17]byte var x14185 [1 << 17]byte var x14186 [1 << 17]byte var x14187 [1 << 17]byte var x14188 [1 << 17]byte var x14189 [1 << 17]byte var x14190 [1 << 17]byte var x14191 [1 << 17]byte var x14192 [1 << 17]byte var x14193 [1 << 17]byte var x14194 [1 << 17]byte var x14195 [1 << 17]byte var x14196 [1 << 17]byte var x14197 [1 << 17]byte var x14198 [1 << 17]byte var x14199 [1 << 17]byte var x14200 [1 << 17]byte var x14201 [1 << 17]byte var x14202 [1 << 17]byte var x14203 [1 << 17]byte var x14204 [1 << 17]byte var x14205 [1 << 17]byte var x14206 [1 << 17]byte var x14207 [1 << 17]byte var x14208 [1 << 17]byte var x14209 [1 << 17]byte var x14210 [1 << 17]byte var x14211 [1 << 17]byte var x14212 [1 << 17]byte var x14213 [1 << 17]byte var x14214 [1 << 17]byte var x14215 [1 << 17]byte var x14216 [1 << 17]byte var x14217 [1 << 17]byte var x14218 [1 << 17]byte var x14219 [1 << 17]byte var x14220 [1 << 17]byte var x14221 [1 << 17]byte var x14222 [1 << 17]byte var x14223 [1 << 17]byte var x14224 [1 << 17]byte var x14225 [1 << 17]byte var x14226 [1 << 17]byte var x14227 [1 << 17]byte var x14228 [1 << 17]byte var x14229 [1 << 17]byte var x14230 [1 << 17]byte var x14231 [1 << 17]byte var x14232 [1 << 17]byte var x14233 [1 << 17]byte var x14234 [1 << 17]byte var x14235 [1 << 17]byte var x14236 [1 << 17]byte var x14237 [1 << 17]byte var x14238 [1 << 17]byte var x14239 [1 << 17]byte var x14240 [1 << 17]byte var x14241 [1 << 17]byte var x14242 [1 << 17]byte var x14243 [1 << 17]byte var x14244 [1 << 17]byte var x14245 [1 << 17]byte var x14246 [1 << 17]byte var x14247 [1 << 17]byte var x14248 [1 << 17]byte var x14249 [1 << 17]byte var x14250 [1 << 17]byte var x14251 [1 << 17]byte var x14252 [1 << 17]byte var x14253 [1 << 17]byte var x14254 [1 << 17]byte var x14255 [1 << 17]byte var x14256 [1 << 17]byte var x14257 [1 << 17]byte var x14258 [1 << 17]byte var x14259 [1 << 17]byte var x14260 [1 << 17]byte var x14261 [1 << 17]byte var x14262 [1 << 17]byte var x14263 [1 << 17]byte var x14264 [1 << 17]byte var x14265 [1 << 17]byte var x14266 [1 << 17]byte var x14267 [1 << 17]byte var x14268 [1 << 17]byte var x14269 [1 << 17]byte var x14270 [1 << 17]byte var x14271 [1 << 17]byte var x14272 [1 << 17]byte var x14273 [1 << 17]byte var x14274 [1 << 17]byte var x14275 [1 << 17]byte var x14276 [1 << 17]byte var x14277 [1 << 17]byte var x14278 [1 << 17]byte var x14279 [1 << 17]byte var x14280 [1 << 17]byte var x14281 [1 << 17]byte var x14282 [1 << 17]byte var x14283 [1 << 17]byte var x14284 [1 << 17]byte var x14285 [1 << 17]byte var x14286 [1 << 17]byte var x14287 [1 << 17]byte var x14288 [1 << 17]byte var x14289 [1 << 17]byte var x14290 [1 << 17]byte var x14291 [1 << 17]byte var x14292 [1 << 17]byte var x14293 [1 << 17]byte var x14294 [1 << 17]byte var x14295 [1 << 17]byte var x14296 [1 << 17]byte var x14297 [1 << 17]byte var x14298 [1 << 17]byte var x14299 [1 << 17]byte var x14300 [1 << 17]byte var x14301 [1 << 17]byte var x14302 [1 << 17]byte var x14303 [1 << 17]byte var x14304 [1 << 17]byte var x14305 [1 << 17]byte var x14306 [1 << 17]byte var x14307 [1 << 17]byte var x14308 [1 << 17]byte var x14309 [1 << 17]byte var x14310 [1 << 17]byte var x14311 [1 << 17]byte var x14312 [1 << 17]byte var x14313 [1 << 17]byte var x14314 [1 << 17]byte var x14315 [1 << 17]byte var x14316 [1 << 17]byte var x14317 [1 << 17]byte var x14318 [1 << 17]byte var x14319 [1 << 17]byte var x14320 [1 << 17]byte var x14321 [1 << 17]byte var x14322 [1 << 17]byte var x14323 [1 << 17]byte var x14324 [1 << 17]byte var x14325 [1 << 17]byte var x14326 [1 << 17]byte var x14327 [1 << 17]byte var x14328 [1 << 17]byte var x14329 [1 << 17]byte var x14330 [1 << 17]byte var x14331 [1 << 17]byte var x14332 [1 << 17]byte var x14333 [1 << 17]byte var x14334 [1 << 17]byte var x14335 [1 << 17]byte var x14336 [1 << 17]byte var x14337 [1 << 17]byte var x14338 [1 << 17]byte var x14339 [1 << 17]byte var x14340 [1 << 17]byte var x14341 [1 << 17]byte var x14342 [1 << 17]byte var x14343 [1 << 17]byte var x14344 [1 << 17]byte var x14345 [1 << 17]byte var x14346 [1 << 17]byte var x14347 [1 << 17]byte var x14348 [1 << 17]byte var x14349 [1 << 17]byte var x14350 [1 << 17]byte var x14351 [1 << 17]byte var x14352 [1 << 17]byte var x14353 [1 << 17]byte var x14354 [1 << 17]byte var x14355 [1 << 17]byte var x14356 [1 << 17]byte var x14357 [1 << 17]byte var x14358 [1 << 17]byte var x14359 [1 << 17]byte var x14360 [1 << 17]byte var x14361 [1 << 17]byte var x14362 [1 << 17]byte var x14363 [1 << 17]byte var x14364 [1 << 17]byte var x14365 [1 << 17]byte var x14366 [1 << 17]byte var x14367 [1 << 17]byte var x14368 [1 << 17]byte var x14369 [1 << 17]byte var x14370 [1 << 17]byte var x14371 [1 << 17]byte var x14372 [1 << 17]byte var x14373 [1 << 17]byte var x14374 [1 << 17]byte var x14375 [1 << 17]byte var x14376 [1 << 17]byte var x14377 [1 << 17]byte var x14378 [1 << 17]byte var x14379 [1 << 17]byte var x14380 [1 << 17]byte var x14381 [1 << 17]byte var x14382 [1 << 17]byte var x14383 [1 << 17]byte var x14384 [1 << 17]byte var x14385 [1 << 17]byte var x14386 [1 << 17]byte var x14387 [1 << 17]byte var x14388 [1 << 17]byte var x14389 [1 << 17]byte var x14390 [1 << 17]byte var x14391 [1 << 17]byte var x14392 [1 << 17]byte var x14393 [1 << 17]byte var x14394 [1 << 17]byte var x14395 [1 << 17]byte var x14396 [1 << 17]byte var x14397 [1 << 17]byte var x14398 [1 << 17]byte var x14399 [1 << 17]byte var x14400 [1 << 17]byte var x14401 [1 << 17]byte var x14402 [1 << 17]byte var x14403 [1 << 17]byte var x14404 [1 << 17]byte var x14405 [1 << 17]byte var x14406 [1 << 17]byte var x14407 [1 << 17]byte var x14408 [1 << 17]byte var x14409 [1 << 17]byte var x14410 [1 << 17]byte var x14411 [1 << 17]byte var x14412 [1 << 17]byte var x14413 [1 << 17]byte var x14414 [1 << 17]byte var x14415 [1 << 17]byte var x14416 [1 << 17]byte var x14417 [1 << 17]byte var x14418 [1 << 17]byte var x14419 [1 << 17]byte var x14420 [1 << 17]byte var x14421 [1 << 17]byte var x14422 [1 << 17]byte var x14423 [1 << 17]byte var x14424 [1 << 17]byte var x14425 [1 << 17]byte var x14426 [1 << 17]byte var x14427 [1 << 17]byte var x14428 [1 << 17]byte var x14429 [1 << 17]byte var x14430 [1 << 17]byte var x14431 [1 << 17]byte var x14432 [1 << 17]byte var x14433 [1 << 17]byte var x14434 [1 << 17]byte var x14435 [1 << 17]byte var x14436 [1 << 17]byte var x14437 [1 << 17]byte var x14438 [1 << 17]byte var x14439 [1 << 17]byte var x14440 [1 << 17]byte var x14441 [1 << 17]byte var x14442 [1 << 17]byte var x14443 [1 << 17]byte var x14444 [1 << 17]byte var x14445 [1 << 17]byte var x14446 [1 << 17]byte var x14447 [1 << 17]byte var x14448 [1 << 17]byte var x14449 [1 << 17]byte var x14450 [1 << 17]byte var x14451 [1 << 17]byte var x14452 [1 << 17]byte var x14453 [1 << 17]byte var x14454 [1 << 17]byte var x14455 [1 << 17]byte var x14456 [1 << 17]byte var x14457 [1 << 17]byte var x14458 [1 << 17]byte var x14459 [1 << 17]byte var x14460 [1 << 17]byte var x14461 [1 << 17]byte var x14462 [1 << 17]byte var x14463 [1 << 17]byte var x14464 [1 << 17]byte var x14465 [1 << 17]byte var x14466 [1 << 17]byte var x14467 [1 << 17]byte var x14468 [1 << 17]byte var x14469 [1 << 17]byte var x14470 [1 << 17]byte var x14471 [1 << 17]byte var x14472 [1 << 17]byte var x14473 [1 << 17]byte var x14474 [1 << 17]byte var x14475 [1 << 17]byte var x14476 [1 << 17]byte var x14477 [1 << 17]byte var x14478 [1 << 17]byte var x14479 [1 << 17]byte var x14480 [1 << 17]byte var x14481 [1 << 17]byte var x14482 [1 << 17]byte var x14483 [1 << 17]byte var x14484 [1 << 17]byte var x14485 [1 << 17]byte var x14486 [1 << 17]byte var x14487 [1 << 17]byte var x14488 [1 << 17]byte var x14489 [1 << 17]byte var x14490 [1 << 17]byte var x14491 [1 << 17]byte var x14492 [1 << 17]byte var x14493 [1 << 17]byte var x14494 [1 << 17]byte var x14495 [1 << 17]byte var x14496 [1 << 17]byte var x14497 [1 << 17]byte var x14498 [1 << 17]byte var x14499 [1 << 17]byte var x14500 [1 << 17]byte var x14501 [1 << 17]byte var x14502 [1 << 17]byte var x14503 [1 << 17]byte var x14504 [1 << 17]byte var x14505 [1 << 17]byte var x14506 [1 << 17]byte var x14507 [1 << 17]byte var x14508 [1 << 17]byte var x14509 [1 << 17]byte var x14510 [1 << 17]byte var x14511 [1 << 17]byte var x14512 [1 << 17]byte var x14513 [1 << 17]byte var x14514 [1 << 17]byte var x14515 [1 << 17]byte var x14516 [1 << 17]byte var x14517 [1 << 17]byte var x14518 [1 << 17]byte var x14519 [1 << 17]byte var x14520 [1 << 17]byte var x14521 [1 << 17]byte var x14522 [1 << 17]byte var x14523 [1 << 17]byte var x14524 [1 << 17]byte var x14525 [1 << 17]byte var x14526 [1 << 17]byte var x14527 [1 << 17]byte var x14528 [1 << 17]byte var x14529 [1 << 17]byte var x14530 [1 << 17]byte var x14531 [1 << 17]byte var x14532 [1 << 17]byte var x14533 [1 << 17]byte var x14534 [1 << 17]byte var x14535 [1 << 17]byte var x14536 [1 << 17]byte var x14537 [1 << 17]byte var x14538 [1 << 17]byte var x14539 [1 << 17]byte var x14540 [1 << 17]byte var x14541 [1 << 17]byte var x14542 [1 << 17]byte var x14543 [1 << 17]byte var x14544 [1 << 17]byte var x14545 [1 << 17]byte var x14546 [1 << 17]byte var x14547 [1 << 17]byte var x14548 [1 << 17]byte var x14549 [1 << 17]byte var x14550 [1 << 17]byte var x14551 [1 << 17]byte var x14552 [1 << 17]byte var x14553 [1 << 17]byte var x14554 [1 << 17]byte var x14555 [1 << 17]byte var x14556 [1 << 17]byte var x14557 [1 << 17]byte var x14558 [1 << 17]byte var x14559 [1 << 17]byte var x14560 [1 << 17]byte var x14561 [1 << 17]byte var x14562 [1 << 17]byte var x14563 [1 << 17]byte var x14564 [1 << 17]byte var x14565 [1 << 17]byte var x14566 [1 << 17]byte var x14567 [1 << 17]byte var x14568 [1 << 17]byte var x14569 [1 << 17]byte var x14570 [1 << 17]byte var x14571 [1 << 17]byte var x14572 [1 << 17]byte var x14573 [1 << 17]byte var x14574 [1 << 17]byte var x14575 [1 << 17]byte var x14576 [1 << 17]byte var x14577 [1 << 17]byte var x14578 [1 << 17]byte var x14579 [1 << 17]byte var x14580 [1 << 17]byte var x14581 [1 << 17]byte var x14582 [1 << 17]byte var x14583 [1 << 17]byte var x14584 [1 << 17]byte var x14585 [1 << 17]byte var x14586 [1 << 17]byte var x14587 [1 << 17]byte var x14588 [1 << 17]byte var x14589 [1 << 17]byte var x14590 [1 << 17]byte var x14591 [1 << 17]byte var x14592 [1 << 17]byte var x14593 [1 << 17]byte var x14594 [1 << 17]byte var x14595 [1 << 17]byte var x14596 [1 << 17]byte var x14597 [1 << 17]byte var x14598 [1 << 17]byte var x14599 [1 << 17]byte var x14600 [1 << 17]byte var x14601 [1 << 17]byte var x14602 [1 << 17]byte var x14603 [1 << 17]byte var x14604 [1 << 17]byte var x14605 [1 << 17]byte var x14606 [1 << 17]byte var x14607 [1 << 17]byte var x14608 [1 << 17]byte var x14609 [1 << 17]byte var x14610 [1 << 17]byte var x14611 [1 << 17]byte var x14612 [1 << 17]byte var x14613 [1 << 17]byte var x14614 [1 << 17]byte var x14615 [1 << 17]byte var x14616 [1 << 17]byte var x14617 [1 << 17]byte var x14618 [1 << 17]byte var x14619 [1 << 17]byte var x14620 [1 << 17]byte var x14621 [1 << 17]byte var x14622 [1 << 17]byte var x14623 [1 << 17]byte var x14624 [1 << 17]byte var x14625 [1 << 17]byte var x14626 [1 << 17]byte var x14627 [1 << 17]byte var x14628 [1 << 17]byte var x14629 [1 << 17]byte var x14630 [1 << 17]byte var x14631 [1 << 17]byte var x14632 [1 << 17]byte var x14633 [1 << 17]byte var x14634 [1 << 17]byte var x14635 [1 << 17]byte var x14636 [1 << 17]byte var x14637 [1 << 17]byte var x14638 [1 << 17]byte var x14639 [1 << 17]byte var x14640 [1 << 17]byte var x14641 [1 << 17]byte var x14642 [1 << 17]byte var x14643 [1 << 17]byte var x14644 [1 << 17]byte var x14645 [1 << 17]byte var x14646 [1 << 17]byte var x14647 [1 << 17]byte var x14648 [1 << 17]byte var x14649 [1 << 17]byte var x14650 [1 << 17]byte var x14651 [1 << 17]byte var x14652 [1 << 17]byte var x14653 [1 << 17]byte var x14654 [1 << 17]byte var x14655 [1 << 17]byte var x14656 [1 << 17]byte var x14657 [1 << 17]byte var x14658 [1 << 17]byte var x14659 [1 << 17]byte var x14660 [1 << 17]byte var x14661 [1 << 17]byte var x14662 [1 << 17]byte var x14663 [1 << 17]byte var x14664 [1 << 17]byte var x14665 [1 << 17]byte var x14666 [1 << 17]byte var x14667 [1 << 17]byte var x14668 [1 << 17]byte var x14669 [1 << 17]byte var x14670 [1 << 17]byte var x14671 [1 << 17]byte var x14672 [1 << 17]byte var x14673 [1 << 17]byte var x14674 [1 << 17]byte var x14675 [1 << 17]byte var x14676 [1 << 17]byte var x14677 [1 << 17]byte var x14678 [1 << 17]byte var x14679 [1 << 17]byte var x14680 [1 << 17]byte var x14681 [1 << 17]byte var x14682 [1 << 17]byte var x14683 [1 << 17]byte var x14684 [1 << 17]byte var x14685 [1 << 17]byte var x14686 [1 << 17]byte var x14687 [1 << 17]byte var x14688 [1 << 17]byte var x14689 [1 << 17]byte var x14690 [1 << 17]byte var x14691 [1 << 17]byte var x14692 [1 << 17]byte var x14693 [1 << 17]byte var x14694 [1 << 17]byte var x14695 [1 << 17]byte var x14696 [1 << 17]byte var x14697 [1 << 17]byte var x14698 [1 << 17]byte var x14699 [1 << 17]byte var x14700 [1 << 17]byte var x14701 [1 << 17]byte var x14702 [1 << 17]byte var x14703 [1 << 17]byte var x14704 [1 << 17]byte var x14705 [1 << 17]byte var x14706 [1 << 17]byte var x14707 [1 << 17]byte var x14708 [1 << 17]byte var x14709 [1 << 17]byte var x14710 [1 << 17]byte var x14711 [1 << 17]byte var x14712 [1 << 17]byte var x14713 [1 << 17]byte var x14714 [1 << 17]byte var x14715 [1 << 17]byte var x14716 [1 << 17]byte var x14717 [1 << 17]byte var x14718 [1 << 17]byte var x14719 [1 << 17]byte var x14720 [1 << 17]byte var x14721 [1 << 17]byte var x14722 [1 << 17]byte var x14723 [1 << 17]byte var x14724 [1 << 17]byte var x14725 [1 << 17]byte var x14726 [1 << 17]byte var x14727 [1 << 17]byte var x14728 [1 << 17]byte var x14729 [1 << 17]byte var x14730 [1 << 17]byte var x14731 [1 << 17]byte var x14732 [1 << 17]byte var x14733 [1 << 17]byte var x14734 [1 << 17]byte var x14735 [1 << 17]byte var x14736 [1 << 17]byte var x14737 [1 << 17]byte var x14738 [1 << 17]byte var x14739 [1 << 17]byte var x14740 [1 << 17]byte var x14741 [1 << 17]byte var x14742 [1 << 17]byte var x14743 [1 << 17]byte var x14744 [1 << 17]byte var x14745 [1 << 17]byte var x14746 [1 << 17]byte var x14747 [1 << 17]byte var x14748 [1 << 17]byte var x14749 [1 << 17]byte var x14750 [1 << 17]byte var x14751 [1 << 17]byte var x14752 [1 << 17]byte var x14753 [1 << 17]byte var x14754 [1 << 17]byte var x14755 [1 << 17]byte var x14756 [1 << 17]byte var x14757 [1 << 17]byte var x14758 [1 << 17]byte var x14759 [1 << 17]byte var x14760 [1 << 17]byte var x14761 [1 << 17]byte var x14762 [1 << 17]byte var x14763 [1 << 17]byte var x14764 [1 << 17]byte var x14765 [1 << 17]byte var x14766 [1 << 17]byte var x14767 [1 << 17]byte var x14768 [1 << 17]byte var x14769 [1 << 17]byte var x14770 [1 << 17]byte var x14771 [1 << 17]byte var x14772 [1 << 17]byte var x14773 [1 << 17]byte var x14774 [1 << 17]byte var x14775 [1 << 17]byte var x14776 [1 << 17]byte var x14777 [1 << 17]byte var x14778 [1 << 17]byte var x14779 [1 << 17]byte var x14780 [1 << 17]byte var x14781 [1 << 17]byte var x14782 [1 << 17]byte var x14783 [1 << 17]byte var x14784 [1 << 17]byte var x14785 [1 << 17]byte var x14786 [1 << 17]byte var x14787 [1 << 17]byte var x14788 [1 << 17]byte var x14789 [1 << 17]byte var x14790 [1 << 17]byte var x14791 [1 << 17]byte var x14792 [1 << 17]byte var x14793 [1 << 17]byte var x14794 [1 << 17]byte var x14795 [1 << 17]byte var x14796 [1 << 17]byte var x14797 [1 << 17]byte var x14798 [1 << 17]byte var x14799 [1 << 17]byte var x14800 [1 << 17]byte var x14801 [1 << 17]byte var x14802 [1 << 17]byte var x14803 [1 << 17]byte var x14804 [1 << 17]byte var x14805 [1 << 17]byte var x14806 [1 << 17]byte var x14807 [1 << 17]byte var x14808 [1 << 17]byte var x14809 [1 << 17]byte var x14810 [1 << 17]byte var x14811 [1 << 17]byte var x14812 [1 << 17]byte var x14813 [1 << 17]byte var x14814 [1 << 17]byte var x14815 [1 << 17]byte var x14816 [1 << 17]byte var x14817 [1 << 17]byte var x14818 [1 << 17]byte var x14819 [1 << 17]byte var x14820 [1 << 17]byte var x14821 [1 << 17]byte var x14822 [1 << 17]byte var x14823 [1 << 17]byte var x14824 [1 << 17]byte var x14825 [1 << 17]byte var x14826 [1 << 17]byte var x14827 [1 << 17]byte var x14828 [1 << 17]byte var x14829 [1 << 17]byte var x14830 [1 << 17]byte var x14831 [1 << 17]byte var x14832 [1 << 17]byte var x14833 [1 << 17]byte var x14834 [1 << 17]byte var x14835 [1 << 17]byte var x14836 [1 << 17]byte var x14837 [1 << 17]byte var x14838 [1 << 17]byte var x14839 [1 << 17]byte var x14840 [1 << 17]byte var x14841 [1 << 17]byte var x14842 [1 << 17]byte var x14843 [1 << 17]byte var x14844 [1 << 17]byte var x14845 [1 << 17]byte var x14846 [1 << 17]byte var x14847 [1 << 17]byte var x14848 [1 << 17]byte var x14849 [1 << 17]byte var x14850 [1 << 17]byte var x14851 [1 << 17]byte var x14852 [1 << 17]byte var x14853 [1 << 17]byte var x14854 [1 << 17]byte var x14855 [1 << 17]byte var x14856 [1 << 17]byte var x14857 [1 << 17]byte var x14858 [1 << 17]byte var x14859 [1 << 17]byte var x14860 [1 << 17]byte var x14861 [1 << 17]byte var x14862 [1 << 17]byte var x14863 [1 << 17]byte var x14864 [1 << 17]byte var x14865 [1 << 17]byte var x14866 [1 << 17]byte var x14867 [1 << 17]byte var x14868 [1 << 17]byte var x14869 [1 << 17]byte var x14870 [1 << 17]byte var x14871 [1 << 17]byte var x14872 [1 << 17]byte var x14873 [1 << 17]byte var x14874 [1 << 17]byte var x14875 [1 << 17]byte var x14876 [1 << 17]byte var x14877 [1 << 17]byte var x14878 [1 << 17]byte var x14879 [1 << 17]byte var x14880 [1 << 17]byte var x14881 [1 << 17]byte var x14882 [1 << 17]byte var x14883 [1 << 17]byte var x14884 [1 << 17]byte var x14885 [1 << 17]byte var x14886 [1 << 17]byte var x14887 [1 << 17]byte var x14888 [1 << 17]byte var x14889 [1 << 17]byte var x14890 [1 << 17]byte var x14891 [1 << 17]byte var x14892 [1 << 17]byte var x14893 [1 << 17]byte var x14894 [1 << 17]byte var x14895 [1 << 17]byte var x14896 [1 << 17]byte var x14897 [1 << 17]byte var x14898 [1 << 17]byte var x14899 [1 << 17]byte var x14900 [1 << 17]byte var x14901 [1 << 17]byte var x14902 [1 << 17]byte var x14903 [1 << 17]byte var x14904 [1 << 17]byte var x14905 [1 << 17]byte var x14906 [1 << 17]byte var x14907 [1 << 17]byte var x14908 [1 << 17]byte var x14909 [1 << 17]byte var x14910 [1 << 17]byte var x14911 [1 << 17]byte var x14912 [1 << 17]byte var x14913 [1 << 17]byte var x14914 [1 << 17]byte var x14915 [1 << 17]byte var x14916 [1 << 17]byte var x14917 [1 << 17]byte var x14918 [1 << 17]byte var x14919 [1 << 17]byte var x14920 [1 << 17]byte var x14921 [1 << 17]byte var x14922 [1 << 17]byte var x14923 [1 << 17]byte var x14924 [1 << 17]byte var x14925 [1 << 17]byte var x14926 [1 << 17]byte var x14927 [1 << 17]byte var x14928 [1 << 17]byte var x14929 [1 << 17]byte var x14930 [1 << 17]byte var x14931 [1 << 17]byte var x14932 [1 << 17]byte var x14933 [1 << 17]byte var x14934 [1 << 17]byte var x14935 [1 << 17]byte var x14936 [1 << 17]byte var x14937 [1 << 17]byte var x14938 [1 << 17]byte var x14939 [1 << 17]byte var x14940 [1 << 17]byte var x14941 [1 << 17]byte var x14942 [1 << 17]byte var x14943 [1 << 17]byte var x14944 [1 << 17]byte var x14945 [1 << 17]byte var x14946 [1 << 17]byte var x14947 [1 << 17]byte var x14948 [1 << 17]byte var x14949 [1 << 17]byte var x14950 [1 << 17]byte var x14951 [1 << 17]byte var x14952 [1 << 17]byte var x14953 [1 << 17]byte var x14954 [1 << 17]byte var x14955 [1 << 17]byte var x14956 [1 << 17]byte var x14957 [1 << 17]byte var x14958 [1 << 17]byte var x14959 [1 << 17]byte var x14960 [1 << 17]byte var x14961 [1 << 17]byte var x14962 [1 << 17]byte var x14963 [1 << 17]byte var x14964 [1 << 17]byte var x14965 [1 << 17]byte var x14966 [1 << 17]byte var x14967 [1 << 17]byte var x14968 [1 << 17]byte var x14969 [1 << 17]byte var x14970 [1 << 17]byte var x14971 [1 << 17]byte var x14972 [1 << 17]byte var x14973 [1 << 17]byte var x14974 [1 << 17]byte var x14975 [1 << 17]byte var x14976 [1 << 17]byte var x14977 [1 << 17]byte var x14978 [1 << 17]byte var x14979 [1 << 17]byte var x14980 [1 << 17]byte var x14981 [1 << 17]byte var x14982 [1 << 17]byte var x14983 [1 << 17]byte var x14984 [1 << 17]byte var x14985 [1 << 17]byte var x14986 [1 << 17]byte var x14987 [1 << 17]byte var x14988 [1 << 17]byte var x14989 [1 << 17]byte var x14990 [1 << 17]byte var x14991 [1 << 17]byte var x14992 [1 << 17]byte var x14993 [1 << 17]byte var x14994 [1 << 17]byte var x14995 [1 << 17]byte var x14996 [1 << 17]byte var x14997 [1 << 17]byte var x14998 [1 << 17]byte var x14999 [1 << 17]byte var x15000 [1 << 17]byte var x15001 [1 << 17]byte var x15002 [1 << 17]byte var x15003 [1 << 17]byte var x15004 [1 << 17]byte var x15005 [1 << 17]byte var x15006 [1 << 17]byte var x15007 [1 << 17]byte var x15008 [1 << 17]byte var x15009 [1 << 17]byte var x15010 [1 << 17]byte var x15011 [1 << 17]byte var x15012 [1 << 17]byte var x15013 [1 << 17]byte var x15014 [1 << 17]byte var x15015 [1 << 17]byte var x15016 [1 << 17]byte var x15017 [1 << 17]byte var x15018 [1 << 17]byte var x15019 [1 << 17]byte var x15020 [1 << 17]byte var x15021 [1 << 17]byte var x15022 [1 << 17]byte var x15023 [1 << 17]byte var x15024 [1 << 17]byte var x15025 [1 << 17]byte var x15026 [1 << 17]byte var x15027 [1 << 17]byte var x15028 [1 << 17]byte var x15029 [1 << 17]byte var x15030 [1 << 17]byte var x15031 [1 << 17]byte var x15032 [1 << 17]byte var x15033 [1 << 17]byte var x15034 [1 << 17]byte var x15035 [1 << 17]byte var x15036 [1 << 17]byte var x15037 [1 << 17]byte var x15038 [1 << 17]byte var x15039 [1 << 17]byte var x15040 [1 << 17]byte var x15041 [1 << 17]byte var x15042 [1 << 17]byte var x15043 [1 << 17]byte var x15044 [1 << 17]byte var x15045 [1 << 17]byte var x15046 [1 << 17]byte var x15047 [1 << 17]byte var x15048 [1 << 17]byte var x15049 [1 << 17]byte var x15050 [1 << 17]byte var x15051 [1 << 17]byte var x15052 [1 << 17]byte var x15053 [1 << 17]byte var x15054 [1 << 17]byte var x15055 [1 << 17]byte var x15056 [1 << 17]byte var x15057 [1 << 17]byte var x15058 [1 << 17]byte var x15059 [1 << 17]byte var x15060 [1 << 17]byte var x15061 [1 << 17]byte var x15062 [1 << 17]byte var x15063 [1 << 17]byte var x15064 [1 << 17]byte var x15065 [1 << 17]byte var x15066 [1 << 17]byte var x15067 [1 << 17]byte var x15068 [1 << 17]byte var x15069 [1 << 17]byte var x15070 [1 << 17]byte var x15071 [1 << 17]byte var x15072 [1 << 17]byte var x15073 [1 << 17]byte var x15074 [1 << 17]byte var x15075 [1 << 17]byte var x15076 [1 << 17]byte var x15077 [1 << 17]byte var x15078 [1 << 17]byte var x15079 [1 << 17]byte var x15080 [1 << 17]byte var x15081 [1 << 17]byte var x15082 [1 << 17]byte var x15083 [1 << 17]byte var x15084 [1 << 17]byte var x15085 [1 << 17]byte var x15086 [1 << 17]byte var x15087 [1 << 17]byte var x15088 [1 << 17]byte var x15089 [1 << 17]byte var x15090 [1 << 17]byte var x15091 [1 << 17]byte var x15092 [1 << 17]byte var x15093 [1 << 17]byte var x15094 [1 << 17]byte var x15095 [1 << 17]byte var x15096 [1 << 17]byte var x15097 [1 << 17]byte var x15098 [1 << 17]byte var x15099 [1 << 17]byte var x15100 [1 << 17]byte var x15101 [1 << 17]byte var x15102 [1 << 17]byte var x15103 [1 << 17]byte var x15104 [1 << 17]byte var x15105 [1 << 17]byte var x15106 [1 << 17]byte var x15107 [1 << 17]byte var x15108 [1 << 17]byte var x15109 [1 << 17]byte var x15110 [1 << 17]byte var x15111 [1 << 17]byte var x15112 [1 << 17]byte var x15113 [1 << 17]byte var x15114 [1 << 17]byte var x15115 [1 << 17]byte var x15116 [1 << 17]byte var x15117 [1 << 17]byte var x15118 [1 << 17]byte var x15119 [1 << 17]byte var x15120 [1 << 17]byte var x15121 [1 << 17]byte var x15122 [1 << 17]byte var x15123 [1 << 17]byte var x15124 [1 << 17]byte var x15125 [1 << 17]byte var x15126 [1 << 17]byte var x15127 [1 << 17]byte var x15128 [1 << 17]byte var x15129 [1 << 17]byte var x15130 [1 << 17]byte var x15131 [1 << 17]byte var x15132 [1 << 17]byte var x15133 [1 << 17]byte var x15134 [1 << 17]byte var x15135 [1 << 17]byte var x15136 [1 << 17]byte var x15137 [1 << 17]byte var x15138 [1 << 17]byte var x15139 [1 << 17]byte var x15140 [1 << 17]byte var x15141 [1 << 17]byte var x15142 [1 << 17]byte var x15143 [1 << 17]byte var x15144 [1 << 17]byte var x15145 [1 << 17]byte var x15146 [1 << 17]byte var x15147 [1 << 17]byte var x15148 [1 << 17]byte var x15149 [1 << 17]byte var x15150 [1 << 17]byte var x15151 [1 << 17]byte var x15152 [1 << 17]byte var x15153 [1 << 17]byte var x15154 [1 << 17]byte var x15155 [1 << 17]byte var x15156 [1 << 17]byte var x15157 [1 << 17]byte var x15158 [1 << 17]byte var x15159 [1 << 17]byte var x15160 [1 << 17]byte var x15161 [1 << 17]byte var x15162 [1 << 17]byte var x15163 [1 << 17]byte var x15164 [1 << 17]byte var x15165 [1 << 17]byte var x15166 [1 << 17]byte var x15167 [1 << 17]byte var x15168 [1 << 17]byte var x15169 [1 << 17]byte var x15170 [1 << 17]byte var x15171 [1 << 17]byte var x15172 [1 << 17]byte var x15173 [1 << 17]byte var x15174 [1 << 17]byte var x15175 [1 << 17]byte var x15176 [1 << 17]byte var x15177 [1 << 17]byte var x15178 [1 << 17]byte var x15179 [1 << 17]byte var x15180 [1 << 17]byte var x15181 [1 << 17]byte var x15182 [1 << 17]byte var x15183 [1 << 17]byte var x15184 [1 << 17]byte var x15185 [1 << 17]byte var x15186 [1 << 17]byte var x15187 [1 << 17]byte var x15188 [1 << 17]byte var x15189 [1 << 17]byte var x15190 [1 << 17]byte var x15191 [1 << 17]byte var x15192 [1 << 17]byte var x15193 [1 << 17]byte var x15194 [1 << 17]byte var x15195 [1 << 17]byte var x15196 [1 << 17]byte var x15197 [1 << 17]byte var x15198 [1 << 17]byte var x15199 [1 << 17]byte var x15200 [1 << 17]byte var x15201 [1 << 17]byte var x15202 [1 << 17]byte var x15203 [1 << 17]byte var x15204 [1 << 17]byte var x15205 [1 << 17]byte var x15206 [1 << 17]byte var x15207 [1 << 17]byte var x15208 [1 << 17]byte var x15209 [1 << 17]byte var x15210 [1 << 17]byte var x15211 [1 << 17]byte var x15212 [1 << 17]byte var x15213 [1 << 17]byte var x15214 [1 << 17]byte var x15215 [1 << 17]byte var x15216 [1 << 17]byte var x15217 [1 << 17]byte var x15218 [1 << 17]byte var x15219 [1 << 17]byte var x15220 [1 << 17]byte var x15221 [1 << 17]byte var x15222 [1 << 17]byte var x15223 [1 << 17]byte var x15224 [1 << 17]byte var x15225 [1 << 17]byte var x15226 [1 << 17]byte var x15227 [1 << 17]byte var x15228 [1 << 17]byte var x15229 [1 << 17]byte var x15230 [1 << 17]byte var x15231 [1 << 17]byte var x15232 [1 << 17]byte var x15233 [1 << 17]byte var x15234 [1 << 17]byte var x15235 [1 << 17]byte var x15236 [1 << 17]byte var x15237 [1 << 17]byte var x15238 [1 << 17]byte var x15239 [1 << 17]byte var x15240 [1 << 17]byte var x15241 [1 << 17]byte var x15242 [1 << 17]byte var x15243 [1 << 17]byte var x15244 [1 << 17]byte var x15245 [1 << 17]byte var x15246 [1 << 17]byte var x15247 [1 << 17]byte var x15248 [1 << 17]byte var x15249 [1 << 17]byte var x15250 [1 << 17]byte var x15251 [1 << 17]byte var x15252 [1 << 17]byte var x15253 [1 << 17]byte var x15254 [1 << 17]byte var x15255 [1 << 17]byte var x15256 [1 << 17]byte var x15257 [1 << 17]byte var x15258 [1 << 17]byte var x15259 [1 << 17]byte var x15260 [1 << 17]byte var x15261 [1 << 17]byte var x15262 [1 << 17]byte var x15263 [1 << 17]byte var x15264 [1 << 17]byte var x15265 [1 << 17]byte var x15266 [1 << 17]byte var x15267 [1 << 17]byte var x15268 [1 << 17]byte var x15269 [1 << 17]byte var x15270 [1 << 17]byte var x15271 [1 << 17]byte var x15272 [1 << 17]byte var x15273 [1 << 17]byte var x15274 [1 << 17]byte var x15275 [1 << 17]byte var x15276 [1 << 17]byte var x15277 [1 << 17]byte var x15278 [1 << 17]byte var x15279 [1 << 17]byte var x15280 [1 << 17]byte var x15281 [1 << 17]byte var x15282 [1 << 17]byte var x15283 [1 << 17]byte var x15284 [1 << 17]byte var x15285 [1 << 17]byte var x15286 [1 << 17]byte var x15287 [1 << 17]byte var x15288 [1 << 17]byte var x15289 [1 << 17]byte var x15290 [1 << 17]byte var x15291 [1 << 17]byte var x15292 [1 << 17]byte var x15293 [1 << 17]byte var x15294 [1 << 17]byte var x15295 [1 << 17]byte var x15296 [1 << 17]byte var x15297 [1 << 17]byte var x15298 [1 << 17]byte var x15299 [1 << 17]byte var x15300 [1 << 17]byte var x15301 [1 << 17]byte var x15302 [1 << 17]byte var x15303 [1 << 17]byte var x15304 [1 << 17]byte var x15305 [1 << 17]byte var x15306 [1 << 17]byte var x15307 [1 << 17]byte var x15308 [1 << 17]byte var x15309 [1 << 17]byte var x15310 [1 << 17]byte var x15311 [1 << 17]byte var x15312 [1 << 17]byte var x15313 [1 << 17]byte var x15314 [1 << 17]byte var x15315 [1 << 17]byte var x15316 [1 << 17]byte var x15317 [1 << 17]byte var x15318 [1 << 17]byte var x15319 [1 << 17]byte var x15320 [1 << 17]byte var x15321 [1 << 17]byte var x15322 [1 << 17]byte var x15323 [1 << 17]byte var x15324 [1 << 17]byte var x15325 [1 << 17]byte var x15326 [1 << 17]byte var x15327 [1 << 17]byte var x15328 [1 << 17]byte var x15329 [1 << 17]byte var x15330 [1 << 17]byte var x15331 [1 << 17]byte var x15332 [1 << 17]byte var x15333 [1 << 17]byte var x15334 [1 << 17]byte var x15335 [1 << 17]byte var x15336 [1 << 17]byte var x15337 [1 << 17]byte var x15338 [1 << 17]byte var x15339 [1 << 17]byte var x15340 [1 << 17]byte var x15341 [1 << 17]byte var x15342 [1 << 17]byte var x15343 [1 << 17]byte var x15344 [1 << 17]byte var x15345 [1 << 17]byte var x15346 [1 << 17]byte var x15347 [1 << 17]byte var x15348 [1 << 17]byte var x15349 [1 << 17]byte var x15350 [1 << 17]byte var x15351 [1 << 17]byte var x15352 [1 << 17]byte var x15353 [1 << 17]byte var x15354 [1 << 17]byte var x15355 [1 << 17]byte var x15356 [1 << 17]byte var x15357 [1 << 17]byte var x15358 [1 << 17]byte var x15359 [1 << 17]byte var x15360 [1 << 17]byte var x15361 [1 << 17]byte var x15362 [1 << 17]byte var x15363 [1 << 17]byte var x15364 [1 << 17]byte var x15365 [1 << 17]byte var x15366 [1 << 17]byte var x15367 [1 << 17]byte var x15368 [1 << 17]byte var x15369 [1 << 17]byte var x15370 [1 << 17]byte var x15371 [1 << 17]byte var x15372 [1 << 17]byte var x15373 [1 << 17]byte var x15374 [1 << 17]byte var x15375 [1 << 17]byte var x15376 [1 << 17]byte var x15377 [1 << 17]byte var x15378 [1 << 17]byte var x15379 [1 << 17]byte var x15380 [1 << 17]byte var x15381 [1 << 17]byte var x15382 [1 << 17]byte var x15383 [1 << 17]byte var x15384 [1 << 17]byte var x15385 [1 << 17]byte var x15386 [1 << 17]byte var x15387 [1 << 17]byte var x15388 [1 << 17]byte var x15389 [1 << 17]byte var x15390 [1 << 17]byte var x15391 [1 << 17]byte var x15392 [1 << 17]byte var x15393 [1 << 17]byte var x15394 [1 << 17]byte var x15395 [1 << 17]byte var x15396 [1 << 17]byte var x15397 [1 << 17]byte var x15398 [1 << 17]byte var x15399 [1 << 17]byte var x15400 [1 << 17]byte var x15401 [1 << 17]byte var x15402 [1 << 17]byte var x15403 [1 << 17]byte var x15404 [1 << 17]byte var x15405 [1 << 17]byte var x15406 [1 << 17]byte var x15407 [1 << 17]byte var x15408 [1 << 17]byte var x15409 [1 << 17]byte var x15410 [1 << 17]byte var x15411 [1 << 17]byte var x15412 [1 << 17]byte var x15413 [1 << 17]byte var x15414 [1 << 17]byte var x15415 [1 << 17]byte var x15416 [1 << 17]byte var x15417 [1 << 17]byte var x15418 [1 << 17]byte var x15419 [1 << 17]byte var x15420 [1 << 17]byte var x15421 [1 << 17]byte var x15422 [1 << 17]byte var x15423 [1 << 17]byte var x15424 [1 << 17]byte var x15425 [1 << 17]byte var x15426 [1 << 17]byte var x15427 [1 << 17]byte var x15428 [1 << 17]byte var x15429 [1 << 17]byte var x15430 [1 << 17]byte var x15431 [1 << 17]byte var x15432 [1 << 17]byte var x15433 [1 << 17]byte var x15434 [1 << 17]byte var x15435 [1 << 17]byte var x15436 [1 << 17]byte var x15437 [1 << 17]byte var x15438 [1 << 17]byte var x15439 [1 << 17]byte var x15440 [1 << 17]byte var x15441 [1 << 17]byte var x15442 [1 << 17]byte var x15443 [1 << 17]byte var x15444 [1 << 17]byte var x15445 [1 << 17]byte var x15446 [1 << 17]byte var x15447 [1 << 17]byte var x15448 [1 << 17]byte var x15449 [1 << 17]byte var x15450 [1 << 17]byte var x15451 [1 << 17]byte var x15452 [1 << 17]byte var x15453 [1 << 17]byte var x15454 [1 << 17]byte var x15455 [1 << 17]byte var x15456 [1 << 17]byte var x15457 [1 << 17]byte var x15458 [1 << 17]byte var x15459 [1 << 17]byte var x15460 [1 << 17]byte var x15461 [1 << 17]byte var x15462 [1 << 17]byte var x15463 [1 << 17]byte var x15464 [1 << 17]byte var x15465 [1 << 17]byte var x15466 [1 << 17]byte var x15467 [1 << 17]byte var x15468 [1 << 17]byte var x15469 [1 << 17]byte var x15470 [1 << 17]byte var x15471 [1 << 17]byte var x15472 [1 << 17]byte var x15473 [1 << 17]byte var x15474 [1 << 17]byte var x15475 [1 << 17]byte var x15476 [1 << 17]byte var x15477 [1 << 17]byte var x15478 [1 << 17]byte var x15479 [1 << 17]byte var x15480 [1 << 17]byte var x15481 [1 << 17]byte var x15482 [1 << 17]byte var x15483 [1 << 17]byte var x15484 [1 << 17]byte var x15485 [1 << 17]byte var x15486 [1 << 17]byte var x15487 [1 << 17]byte var x15488 [1 << 17]byte var x15489 [1 << 17]byte var x15490 [1 << 17]byte var x15491 [1 << 17]byte var x15492 [1 << 17]byte var x15493 [1 << 17]byte var x15494 [1 << 17]byte var x15495 [1 << 17]byte var x15496 [1 << 17]byte var x15497 [1 << 17]byte var x15498 [1 << 17]byte var x15499 [1 << 17]byte var x15500 [1 << 17]byte var x15501 [1 << 17]byte var x15502 [1 << 17]byte var x15503 [1 << 17]byte var x15504 [1 << 17]byte var x15505 [1 << 17]byte var x15506 [1 << 17]byte var x15507 [1 << 17]byte var x15508 [1 << 17]byte var x15509 [1 << 17]byte var x15510 [1 << 17]byte var x15511 [1 << 17]byte var x15512 [1 << 17]byte var x15513 [1 << 17]byte var x15514 [1 << 17]byte var x15515 [1 << 17]byte var x15516 [1 << 17]byte var x15517 [1 << 17]byte var x15518 [1 << 17]byte var x15519 [1 << 17]byte var x15520 [1 << 17]byte var x15521 [1 << 17]byte var x15522 [1 << 17]byte var x15523 [1 << 17]byte var x15524 [1 << 17]byte var x15525 [1 << 17]byte var x15526 [1 << 17]byte var x15527 [1 << 17]byte var x15528 [1 << 17]byte var x15529 [1 << 17]byte var x15530 [1 << 17]byte var x15531 [1 << 17]byte var x15532 [1 << 17]byte var x15533 [1 << 17]byte var x15534 [1 << 17]byte var x15535 [1 << 17]byte var x15536 [1 << 17]byte var x15537 [1 << 17]byte var x15538 [1 << 17]byte var x15539 [1 << 17]byte var x15540 [1 << 17]byte var x15541 [1 << 17]byte var x15542 [1 << 17]byte var x15543 [1 << 17]byte var x15544 [1 << 17]byte var x15545 [1 << 17]byte var x15546 [1 << 17]byte var x15547 [1 << 17]byte var x15548 [1 << 17]byte var x15549 [1 << 17]byte var x15550 [1 << 17]byte var x15551 [1 << 17]byte var x15552 [1 << 17]byte var x15553 [1 << 17]byte var x15554 [1 << 17]byte var x15555 [1 << 17]byte var x15556 [1 << 17]byte var x15557 [1 << 17]byte var x15558 [1 << 17]byte var x15559 [1 << 17]byte var x15560 [1 << 17]byte var x15561 [1 << 17]byte var x15562 [1 << 17]byte var x15563 [1 << 17]byte var x15564 [1 << 17]byte var x15565 [1 << 17]byte var x15566 [1 << 17]byte var x15567 [1 << 17]byte var x15568 [1 << 17]byte var x15569 [1 << 17]byte var x15570 [1 << 17]byte var x15571 [1 << 17]byte var x15572 [1 << 17]byte var x15573 [1 << 17]byte var x15574 [1 << 17]byte var x15575 [1 << 17]byte var x15576 [1 << 17]byte var x15577 [1 << 17]byte var x15578 [1 << 17]byte var x15579 [1 << 17]byte var x15580 [1 << 17]byte var x15581 [1 << 17]byte var x15582 [1 << 17]byte var x15583 [1 << 17]byte var x15584 [1 << 17]byte var x15585 [1 << 17]byte var x15586 [1 << 17]byte var x15587 [1 << 17]byte var x15588 [1 << 17]byte var x15589 [1 << 17]byte var x15590 [1 << 17]byte var x15591 [1 << 17]byte var x15592 [1 << 17]byte var x15593 [1 << 17]byte var x15594 [1 << 17]byte var x15595 [1 << 17]byte var x15596 [1 << 17]byte var x15597 [1 << 17]byte var x15598 [1 << 17]byte var x15599 [1 << 17]byte var x15600 [1 << 17]byte var x15601 [1 << 17]byte var x15602 [1 << 17]byte var x15603 [1 << 17]byte var x15604 [1 << 17]byte var x15605 [1 << 17]byte var x15606 [1 << 17]byte var x15607 [1 << 17]byte var x15608 [1 << 17]byte var x15609 [1 << 17]byte var x15610 [1 << 17]byte var x15611 [1 << 17]byte var x15612 [1 << 17]byte var x15613 [1 << 17]byte var x15614 [1 << 17]byte var x15615 [1 << 17]byte var x15616 [1 << 17]byte var x15617 [1 << 17]byte var x15618 [1 << 17]byte var x15619 [1 << 17]byte var x15620 [1 << 17]byte var x15621 [1 << 17]byte var x15622 [1 << 17]byte var x15623 [1 << 17]byte var x15624 [1 << 17]byte var x15625 [1 << 17]byte var x15626 [1 << 17]byte var x15627 [1 << 17]byte var x15628 [1 << 17]byte var x15629 [1 << 17]byte var x15630 [1 << 17]byte var x15631 [1 << 17]byte var x15632 [1 << 17]byte var x15633 [1 << 17]byte var x15634 [1 << 17]byte var x15635 [1 << 17]byte var x15636 [1 << 17]byte var x15637 [1 << 17]byte var x15638 [1 << 17]byte var x15639 [1 << 17]byte var x15640 [1 << 17]byte var x15641 [1 << 17]byte var x15642 [1 << 17]byte var x15643 [1 << 17]byte var x15644 [1 << 17]byte var x15645 [1 << 17]byte var x15646 [1 << 17]byte var x15647 [1 << 17]byte var x15648 [1 << 17]byte var x15649 [1 << 17]byte var x15650 [1 << 17]byte var x15651 [1 << 17]byte var x15652 [1 << 17]byte var x15653 [1 << 17]byte var x15654 [1 << 17]byte var x15655 [1 << 17]byte var x15656 [1 << 17]byte var x15657 [1 << 17]byte var x15658 [1 << 17]byte var x15659 [1 << 17]byte var x15660 [1 << 17]byte var x15661 [1 << 17]byte var x15662 [1 << 17]byte var x15663 [1 << 17]byte var x15664 [1 << 17]byte var x15665 [1 << 17]byte var x15666 [1 << 17]byte var x15667 [1 << 17]byte var x15668 [1 << 17]byte var x15669 [1 << 17]byte var x15670 [1 << 17]byte var x15671 [1 << 17]byte var x15672 [1 << 17]byte var x15673 [1 << 17]byte var x15674 [1 << 17]byte var x15675 [1 << 17]byte var x15676 [1 << 17]byte var x15677 [1 << 17]byte var x15678 [1 << 17]byte var x15679 [1 << 17]byte var x15680 [1 << 17]byte var x15681 [1 << 17]byte var x15682 [1 << 17]byte var x15683 [1 << 17]byte var x15684 [1 << 17]byte var x15685 [1 << 17]byte var x15686 [1 << 17]byte var x15687 [1 << 17]byte var x15688 [1 << 17]byte var x15689 [1 << 17]byte var x15690 [1 << 17]byte var x15691 [1 << 17]byte var x15692 [1 << 17]byte var x15693 [1 << 17]byte var x15694 [1 << 17]byte var x15695 [1 << 17]byte var x15696 [1 << 17]byte var x15697 [1 << 17]byte var x15698 [1 << 17]byte var x15699 [1 << 17]byte var x15700 [1 << 17]byte var x15701 [1 << 17]byte var x15702 [1 << 17]byte var x15703 [1 << 17]byte var x15704 [1 << 17]byte var x15705 [1 << 17]byte var x15706 [1 << 17]byte var x15707 [1 << 17]byte var x15708 [1 << 17]byte var x15709 [1 << 17]byte var x15710 [1 << 17]byte var x15711 [1 << 17]byte var x15712 [1 << 17]byte var x15713 [1 << 17]byte var x15714 [1 << 17]byte var x15715 [1 << 17]byte var x15716 [1 << 17]byte var x15717 [1 << 17]byte var x15718 [1 << 17]byte var x15719 [1 << 17]byte var x15720 [1 << 17]byte var x15721 [1 << 17]byte var x15722 [1 << 17]byte var x15723 [1 << 17]byte var x15724 [1 << 17]byte var x15725 [1 << 17]byte var x15726 [1 << 17]byte var x15727 [1 << 17]byte var x15728 [1 << 17]byte var x15729 [1 << 17]byte var x15730 [1 << 17]byte var x15731 [1 << 17]byte var x15732 [1 << 17]byte var x15733 [1 << 17]byte var x15734 [1 << 17]byte var x15735 [1 << 17]byte var x15736 [1 << 17]byte var x15737 [1 << 17]byte var x15738 [1 << 17]byte var x15739 [1 << 17]byte var x15740 [1 << 17]byte var x15741 [1 << 17]byte var x15742 [1 << 17]byte var x15743 [1 << 17]byte var x15744 [1 << 17]byte var x15745 [1 << 17]byte var x15746 [1 << 17]byte var x15747 [1 << 17]byte var x15748 [1 << 17]byte var x15749 [1 << 17]byte var x15750 [1 << 17]byte var x15751 [1 << 17]byte var x15752 [1 << 17]byte var x15753 [1 << 17]byte var x15754 [1 << 17]byte var x15755 [1 << 17]byte var x15756 [1 << 17]byte var x15757 [1 << 17]byte var x15758 [1 << 17]byte var x15759 [1 << 17]byte var x15760 [1 << 17]byte var x15761 [1 << 17]byte var x15762 [1 << 17]byte var x15763 [1 << 17]byte var x15764 [1 << 17]byte var x15765 [1 << 17]byte var x15766 [1 << 17]byte var x15767 [1 << 17]byte var x15768 [1 << 17]byte var x15769 [1 << 17]byte var x15770 [1 << 17]byte var x15771 [1 << 17]byte var x15772 [1 << 17]byte var x15773 [1 << 17]byte var x15774 [1 << 17]byte var x15775 [1 << 17]byte var x15776 [1 << 17]byte var x15777 [1 << 17]byte var x15778 [1 << 17]byte var x15779 [1 << 17]byte var x15780 [1 << 17]byte var x15781 [1 << 17]byte var x15782 [1 << 17]byte var x15783 [1 << 17]byte var x15784 [1 << 17]byte var x15785 [1 << 17]byte var x15786 [1 << 17]byte var x15787 [1 << 17]byte var x15788 [1 << 17]byte var x15789 [1 << 17]byte var x15790 [1 << 17]byte var x15791 [1 << 17]byte var x15792 [1 << 17]byte var x15793 [1 << 17]byte var x15794 [1 << 17]byte var x15795 [1 << 17]byte var x15796 [1 << 17]byte var x15797 [1 << 17]byte var x15798 [1 << 17]byte var x15799 [1 << 17]byte var x15800 [1 << 17]byte var x15801 [1 << 17]byte var x15802 [1 << 17]byte var x15803 [1 << 17]byte var x15804 [1 << 17]byte var x15805 [1 << 17]byte var x15806 [1 << 17]byte var x15807 [1 << 17]byte var x15808 [1 << 17]byte var x15809 [1 << 17]byte var x15810 [1 << 17]byte var x15811 [1 << 17]byte var x15812 [1 << 17]byte var x15813 [1 << 17]byte var x15814 [1 << 17]byte var x15815 [1 << 17]byte var x15816 [1 << 17]byte var x15817 [1 << 17]byte var x15818 [1 << 17]byte var x15819 [1 << 17]byte var x15820 [1 << 17]byte var x15821 [1 << 17]byte var x15822 [1 << 17]byte var x15823 [1 << 17]byte var x15824 [1 << 17]byte var x15825 [1 << 17]byte var x15826 [1 << 17]byte var x15827 [1 << 17]byte var x15828 [1 << 17]byte var x15829 [1 << 17]byte var x15830 [1 << 17]byte var x15831 [1 << 17]byte var x15832 [1 << 17]byte var x15833 [1 << 17]byte var x15834 [1 << 17]byte var x15835 [1 << 17]byte var x15836 [1 << 17]byte var x15837 [1 << 17]byte var x15838 [1 << 17]byte var x15839 [1 << 17]byte var x15840 [1 << 17]byte var x15841 [1 << 17]byte var x15842 [1 << 17]byte var x15843 [1 << 17]byte var x15844 [1 << 17]byte var x15845 [1 << 17]byte var x15846 [1 << 17]byte var x15847 [1 << 17]byte var x15848 [1 << 17]byte var x15849 [1 << 17]byte var x15850 [1 << 17]byte var x15851 [1 << 17]byte var x15852 [1 << 17]byte var x15853 [1 << 17]byte var x15854 [1 << 17]byte var x15855 [1 << 17]byte var x15856 [1 << 17]byte var x15857 [1 << 17]byte var x15858 [1 << 17]byte var x15859 [1 << 17]byte var x15860 [1 << 17]byte var x15861 [1 << 17]byte var x15862 [1 << 17]byte var x15863 [1 << 17]byte var x15864 [1 << 17]byte var x15865 [1 << 17]byte var x15866 [1 << 17]byte var x15867 [1 << 17]byte var x15868 [1 << 17]byte var x15869 [1 << 17]byte var x15870 [1 << 17]byte var x15871 [1 << 17]byte var x15872 [1 << 17]byte var x15873 [1 << 17]byte var x15874 [1 << 17]byte var x15875 [1 << 17]byte var x15876 [1 << 17]byte var x15877 [1 << 17]byte var x15878 [1 << 17]byte var x15879 [1 << 17]byte var x15880 [1 << 17]byte var x15881 [1 << 17]byte var x15882 [1 << 17]byte var x15883 [1 << 17]byte var x15884 [1 << 17]byte var x15885 [1 << 17]byte var x15886 [1 << 17]byte var x15887 [1 << 17]byte var x15888 [1 << 17]byte var x15889 [1 << 17]byte var x15890 [1 << 17]byte var x15891 [1 << 17]byte var x15892 [1 << 17]byte var x15893 [1 << 17]byte var x15894 [1 << 17]byte var x15895 [1 << 17]byte var x15896 [1 << 17]byte var x15897 [1 << 17]byte var x15898 [1 << 17]byte var x15899 [1 << 17]byte var x15900 [1 << 17]byte var x15901 [1 << 17]byte var x15902 [1 << 17]byte var x15903 [1 << 17]byte var x15904 [1 << 17]byte var x15905 [1 << 17]byte var x15906 [1 << 17]byte var x15907 [1 << 17]byte var x15908 [1 << 17]byte var x15909 [1 << 17]byte var x15910 [1 << 17]byte var x15911 [1 << 17]byte var x15912 [1 << 17]byte var x15913 [1 << 17]byte var x15914 [1 << 17]byte var x15915 [1 << 17]byte var x15916 [1 << 17]byte var x15917 [1 << 17]byte var x15918 [1 << 17]byte var x15919 [1 << 17]byte var x15920 [1 << 17]byte var x15921 [1 << 17]byte var x15922 [1 << 17]byte var x15923 [1 << 17]byte var x15924 [1 << 17]byte var x15925 [1 << 17]byte var x15926 [1 << 17]byte var x15927 [1 << 17]byte var x15928 [1 << 17]byte var x15929 [1 << 17]byte var x15930 [1 << 17]byte var x15931 [1 << 17]byte var x15932 [1 << 17]byte var x15933 [1 << 17]byte var x15934 [1 << 17]byte var x15935 [1 << 17]byte var x15936 [1 << 17]byte var x15937 [1 << 17]byte var x15938 [1 << 17]byte var x15939 [1 << 17]byte var x15940 [1 << 17]byte var x15941 [1 << 17]byte var x15942 [1 << 17]byte var x15943 [1 << 17]byte var x15944 [1 << 17]byte var x15945 [1 << 17]byte var x15946 [1 << 17]byte var x15947 [1 << 17]byte var x15948 [1 << 17]byte var x15949 [1 << 17]byte var x15950 [1 << 17]byte var x15951 [1 << 17]byte var x15952 [1 << 17]byte var x15953 [1 << 17]byte var x15954 [1 << 17]byte var x15955 [1 << 17]byte var x15956 [1 << 17]byte var x15957 [1 << 17]byte var x15958 [1 << 17]byte var x15959 [1 << 17]byte var x15960 [1 << 17]byte var x15961 [1 << 17]byte var x15962 [1 << 17]byte var x15963 [1 << 17]byte var x15964 [1 << 17]byte var x15965 [1 << 17]byte var x15966 [1 << 17]byte var x15967 [1 << 17]byte var x15968 [1 << 17]byte var x15969 [1 << 17]byte var x15970 [1 << 17]byte var x15971 [1 << 17]byte var x15972 [1 << 17]byte var x15973 [1 << 17]byte var x15974 [1 << 17]byte var x15975 [1 << 17]byte var x15976 [1 << 17]byte var x15977 [1 << 17]byte var x15978 [1 << 17]byte var x15979 [1 << 17]byte var x15980 [1 << 17]byte var x15981 [1 << 17]byte var x15982 [1 << 17]byte var x15983 [1 << 17]byte var x15984 [1 << 17]byte var x15985 [1 << 17]byte var x15986 [1 << 17]byte var x15987 [1 << 17]byte var x15988 [1 << 17]byte var x15989 [1 << 17]byte var x15990 [1 << 17]byte var x15991 [1 << 17]byte var x15992 [1 << 17]byte var x15993 [1 << 17]byte var x15994 [1 << 17]byte var x15995 [1 << 17]byte var x15996 [1 << 17]byte var x15997 [1 << 17]byte var x15998 [1 << 17]byte var x15999 [1 << 17]byte var x16000 [1 << 17]byte var x16001 [1 << 17]byte var x16002 [1 << 17]byte var x16003 [1 << 17]byte var x16004 [1 << 17]byte var x16005 [1 << 17]byte var x16006 [1 << 17]byte var x16007 [1 << 17]byte var x16008 [1 << 17]byte var x16009 [1 << 17]byte var x16010 [1 << 17]byte var x16011 [1 << 17]byte var x16012 [1 << 17]byte var x16013 [1 << 17]byte var x16014 [1 << 17]byte var x16015 [1 << 17]byte var x16016 [1 << 17]byte var x16017 [1 << 17]byte var x16018 [1 << 17]byte var x16019 [1 << 17]byte var x16020 [1 << 17]byte var x16021 [1 << 17]byte var x16022 [1 << 17]byte var x16023 [1 << 17]byte var x16024 [1 << 17]byte var x16025 [1 << 17]byte var x16026 [1 << 17]byte var x16027 [1 << 17]byte var x16028 [1 << 17]byte var x16029 [1 << 17]byte var x16030 [1 << 17]byte var x16031 [1 << 17]byte var x16032 [1 << 17]byte var x16033 [1 << 17]byte var x16034 [1 << 17]byte var x16035 [1 << 17]byte var x16036 [1 << 17]byte var x16037 [1 << 17]byte var x16038 [1 << 17]byte var x16039 [1 << 17]byte var x16040 [1 << 17]byte var x16041 [1 << 17]byte var x16042 [1 << 17]byte var x16043 [1 << 17]byte var x16044 [1 << 17]byte var x16045 [1 << 17]byte var x16046 [1 << 17]byte var x16047 [1 << 17]byte var x16048 [1 << 17]byte var x16049 [1 << 17]byte var x16050 [1 << 17]byte var x16051 [1 << 17]byte var x16052 [1 << 17]byte var x16053 [1 << 17]byte var x16054 [1 << 17]byte var x16055 [1 << 17]byte var x16056 [1 << 17]byte var x16057 [1 << 17]byte var x16058 [1 << 17]byte var x16059 [1 << 17]byte var x16060 [1 << 17]byte var x16061 [1 << 17]byte var x16062 [1 << 17]byte var x16063 [1 << 17]byte var x16064 [1 << 17]byte var x16065 [1 << 17]byte var x16066 [1 << 17]byte var x16067 [1 << 17]byte var x16068 [1 << 17]byte var x16069 [1 << 17]byte var x16070 [1 << 17]byte var x16071 [1 << 17]byte var x16072 [1 << 17]byte var x16073 [1 << 17]byte var x16074 [1 << 17]byte var x16075 [1 << 17]byte var x16076 [1 << 17]byte var x16077 [1 << 17]byte var x16078 [1 << 17]byte var x16079 [1 << 17]byte var x16080 [1 << 17]byte var x16081 [1 << 17]byte var x16082 [1 << 17]byte var x16083 [1 << 17]byte var x16084 [1 << 17]byte var x16085 [1 << 17]byte var x16086 [1 << 17]byte var x16087 [1 << 17]byte var x16088 [1 << 17]byte var x16089 [1 << 17]byte var x16090 [1 << 17]byte var x16091 [1 << 17]byte var x16092 [1 << 17]byte var x16093 [1 << 17]byte var x16094 [1 << 17]byte var x16095 [1 << 17]byte var x16096 [1 << 17]byte var x16097 [1 << 17]byte var x16098 [1 << 17]byte var x16099 [1 << 17]byte var x16100 [1 << 17]byte var x16101 [1 << 17]byte var x16102 [1 << 17]byte var x16103 [1 << 17]byte var x16104 [1 << 17]byte var x16105 [1 << 17]byte var x16106 [1 << 17]byte var x16107 [1 << 17]byte var x16108 [1 << 17]byte var x16109 [1 << 17]byte var x16110 [1 << 17]byte var x16111 [1 << 17]byte var x16112 [1 << 17]byte var x16113 [1 << 17]byte var x16114 [1 << 17]byte var x16115 [1 << 17]byte var x16116 [1 << 17]byte var x16117 [1 << 17]byte var x16118 [1 << 17]byte var x16119 [1 << 17]byte var x16120 [1 << 17]byte var x16121 [1 << 17]byte var x16122 [1 << 17]byte var x16123 [1 << 17]byte var x16124 [1 << 17]byte var x16125 [1 << 17]byte var x16126 [1 << 17]byte var x16127 [1 << 17]byte var x16128 [1 << 17]byte var x16129 [1 << 17]byte var x16130 [1 << 17]byte var x16131 [1 << 17]byte var x16132 [1 << 17]byte var x16133 [1 << 17]byte var x16134 [1 << 17]byte var x16135 [1 << 17]byte var x16136 [1 << 17]byte var x16137 [1 << 17]byte var x16138 [1 << 17]byte var x16139 [1 << 17]byte var x16140 [1 << 17]byte var x16141 [1 << 17]byte var x16142 [1 << 17]byte var x16143 [1 << 17]byte var x16144 [1 << 17]byte var x16145 [1 << 17]byte var x16146 [1 << 17]byte var x16147 [1 << 17]byte var x16148 [1 << 17]byte var x16149 [1 << 17]byte var x16150 [1 << 17]byte var x16151 [1 << 17]byte var x16152 [1 << 17]byte var x16153 [1 << 17]byte var x16154 [1 << 17]byte var x16155 [1 << 17]byte var x16156 [1 << 17]byte var x16157 [1 << 17]byte var x16158 [1 << 17]byte var x16159 [1 << 17]byte var x16160 [1 << 17]byte var x16161 [1 << 17]byte var x16162 [1 << 17]byte var x16163 [1 << 17]byte var x16164 [1 << 17]byte var x16165 [1 << 17]byte var x16166 [1 << 17]byte var x16167 [1 << 17]byte var x16168 [1 << 17]byte var x16169 [1 << 17]byte var x16170 [1 << 17]byte var x16171 [1 << 17]byte var x16172 [1 << 17]byte var x16173 [1 << 17]byte var x16174 [1 << 17]byte var x16175 [1 << 17]byte var x16176 [1 << 17]byte var x16177 [1 << 17]byte var x16178 [1 << 17]byte var x16179 [1 << 17]byte var x16180 [1 << 17]byte var x16181 [1 << 17]byte var x16182 [1 << 17]byte var x16183 [1 << 17]byte var x16184 [1 << 17]byte var x16185 [1 << 17]byte var x16186 [1 << 17]byte var x16187 [1 << 17]byte var x16188 [1 << 17]byte var x16189 [1 << 17]byte var x16190 [1 << 17]byte var x16191 [1 << 17]byte var x16192 [1 << 17]byte var x16193 [1 << 17]byte var x16194 [1 << 17]byte var x16195 [1 << 17]byte var x16196 [1 << 17]byte var x16197 [1 << 17]byte var x16198 [1 << 17]byte var x16199 [1 << 17]byte var x16200 [1 << 17]byte var x16201 [1 << 17]byte var x16202 [1 << 17]byte var x16203 [1 << 17]byte var x16204 [1 << 17]byte var x16205 [1 << 17]byte var x16206 [1 << 17]byte var x16207 [1 << 17]byte var x16208 [1 << 17]byte var x16209 [1 << 17]byte var x16210 [1 << 17]byte var x16211 [1 << 17]byte var x16212 [1 << 17]byte var x16213 [1 << 17]byte var x16214 [1 << 17]byte var x16215 [1 << 17]byte var x16216 [1 << 17]byte var x16217 [1 << 17]byte var x16218 [1 << 17]byte var x16219 [1 << 17]byte var x16220 [1 << 17]byte var x16221 [1 << 17]byte var x16222 [1 << 17]byte var x16223 [1 << 17]byte var x16224 [1 << 17]byte var x16225 [1 << 17]byte var x16226 [1 << 17]byte var x16227 [1 << 17]byte var x16228 [1 << 17]byte var x16229 [1 << 17]byte var x16230 [1 << 17]byte var x16231 [1 << 17]byte var x16232 [1 << 17]byte var x16233 [1 << 17]byte var x16234 [1 << 17]byte var x16235 [1 << 17]byte var x16236 [1 << 17]byte var x16237 [1 << 17]byte var x16238 [1 << 17]byte var x16239 [1 << 17]byte var x16240 [1 << 17]byte var x16241 [1 << 17]byte var x16242 [1 << 17]byte var x16243 [1 << 17]byte var x16244 [1 << 17]byte var x16245 [1 << 17]byte var x16246 [1 << 17]byte var x16247 [1 << 17]byte var x16248 [1 << 17]byte var x16249 [1 << 17]byte var x16250 [1 << 17]byte var x16251 [1 << 17]byte var x16252 [1 << 17]byte var x16253 [1 << 17]byte var x16254 [1 << 17]byte var x16255 [1 << 17]byte var x16256 [1 << 17]byte var x16257 [1 << 17]byte var x16258 [1 << 17]byte var x16259 [1 << 17]byte var x16260 [1 << 17]byte var x16261 [1 << 17]byte var x16262 [1 << 17]byte var x16263 [1 << 17]byte var x16264 [1 << 17]byte var x16265 [1 << 17]byte var x16266 [1 << 17]byte var x16267 [1 << 17]byte var x16268 [1 << 17]byte var x16269 [1 << 17]byte var x16270 [1 << 17]byte var x16271 [1 << 17]byte var x16272 [1 << 17]byte var x16273 [1 << 17]byte var x16274 [1 << 17]byte var x16275 [1 << 17]byte var x16276 [1 << 17]byte var x16277 [1 << 17]byte var x16278 [1 << 17]byte var x16279 [1 << 17]byte var x16280 [1 << 17]byte var x16281 [1 << 17]byte var x16282 [1 << 17]byte var x16283 [1 << 17]byte var x16284 [1 << 17]byte var x16285 [1 << 17]byte var x16286 [1 << 17]byte var x16287 [1 << 17]byte var x16288 [1 << 17]byte var x16289 [1 << 17]byte var x16290 [1 << 17]byte var x16291 [1 << 17]byte var x16292 [1 << 17]byte var x16293 [1 << 17]byte var x16294 [1 << 17]byte var x16295 [1 << 17]byte var x16296 [1 << 17]byte var x16297 [1 << 17]byte var x16298 [1 << 17]byte var x16299 [1 << 17]byte var x16300 [1 << 17]byte var x16301 [1 << 17]byte var x16302 [1 << 17]byte var x16303 [1 << 17]byte var x16304 [1 << 17]byte var x16305 [1 << 17]byte var x16306 [1 << 17]byte var x16307 [1 << 17]byte var x16308 [1 << 17]byte var x16309 [1 << 17]byte var x16310 [1 << 17]byte var x16311 [1 << 17]byte var x16312 [1 << 17]byte var x16313 [1 << 17]byte var x16314 [1 << 17]byte var x16315 [1 << 17]byte var x16316 [1 << 17]byte var x16317 [1 << 17]byte var x16318 [1 << 17]byte var x16319 [1 << 17]byte var x16320 [1 << 17]byte var x16321 [1 << 17]byte var x16322 [1 << 17]byte var x16323 [1 << 17]byte var x16324 [1 << 17]byte var x16325 [1 << 17]byte var x16326 [1 << 17]byte var x16327 [1 << 17]byte var x16328 [1 << 17]byte var x16329 [1 << 17]byte var x16330 [1 << 17]byte var x16331 [1 << 17]byte var x16332 [1 << 17]byte var x16333 [1 << 17]byte var x16334 [1 << 17]byte var x16335 [1 << 17]byte var x16336 [1 << 17]byte var x16337 [1 << 17]byte var x16338 [1 << 17]byte var x16339 [1 << 17]byte var x16340 [1 << 17]byte var x16341 [1 << 17]byte var x16342 [1 << 17]byte var x16343 [1 << 17]byte var x16344 [1 << 17]byte var x16345 [1 << 17]byte var x16346 [1 << 17]byte var x16347 [1 << 17]byte var x16348 [1 << 17]byte var x16349 [1 << 17]byte var x16350 [1 << 17]byte var x16351 [1 << 17]byte var x16352 [1 << 17]byte var x16353 [1 << 17]byte var x16354 [1 << 17]byte var x16355 [1 << 17]byte var x16356 [1 << 17]byte var x16357 [1 << 17]byte var x16358 [1 << 17]byte var x16359 [1 << 17]byte var x16360 [1 << 17]byte var x16361 [1 << 17]byte var x16362 [1 << 17]byte var x16363 [1 << 17]byte var x16364 [1 << 17]byte var x16365 [1 << 17]byte var x16366 [1 << 17]byte var x16367 [1 << 17]byte var x16368 [1 << 17]byte var x16369 [1 << 17]byte var x16370 [1 << 17]byte var x16371 [1 << 17]byte var x16372 [1 << 17]byte var x16373 [1 << 17]byte var x16374 [1 << 17]byte var x16375 [1 << 17]byte var x16376 [1 << 17]byte var x16377 [1 << 17]byte var x16378 [1 << 17]byte var x16379 [1 << 17]byte var x16380 [1 << 17]byte var x16381 [1 << 17]byte var x16382 [1 << 17]byte var x16383 [1 << 17]byte var x16384 [1 << 17]byte var x16385 [1 << 17]byte var x16386 [1 << 17]byte var x16387 [1 << 17]byte var x16388 [1 << 17]byte var x16389 [1 << 17]byte var x16390 [1 << 17]byte var x16391 [1 << 17]byte var x16392 [1 << 17]byte var x16393 [1 << 17]byte var x16394 [1 << 17]byte var x16395 [1 << 17]byte var x16396 [1 << 17]byte var x16397 [1 << 17]byte var x16398 [1 << 17]byte var x16399 [1 << 17]byte var x16400 [1 << 17]byte var x16401 [1 << 17]byte var x16402 [1 << 17]byte var x16403 [1 << 17]byte var x16404 [1 << 17]byte var x16405 [1 << 17]byte var x16406 [1 << 17]byte var x16407 [1 << 17]byte var x16408 [1 << 17]byte var x16409 [1 << 17]byte var x16410 [1 << 17]byte var x16411 [1 << 17]byte var x16412 [1 << 17]byte var x16413 [1 << 17]byte var x16414 [1 << 17]byte var x16415 [1 << 17]byte var x16416 [1 << 17]byte var x16417 [1 << 17]byte var x16418 [1 << 17]byte var x16419 [1 << 17]byte var x16420 [1 << 17]byte var x16421 [1 << 17]byte var x16422 [1 << 17]byte var x16423 [1 << 17]byte var x16424 [1 << 17]byte var x16425 [1 << 17]byte var x16426 [1 << 17]byte var x16427 [1 << 17]byte var x16428 [1 << 17]byte var x16429 [1 << 17]byte var x16430 [1 << 17]byte var x16431 [1 << 17]byte var x16432 [1 << 17]byte var x16433 [1 << 17]byte var x16434 [1 << 17]byte var x16435 [1 << 17]byte var x16436 [1 << 17]byte var x16437 [1 << 17]byte var x16438 [1 << 17]byte var x16439 [1 << 17]byte var x16440 [1 << 17]byte var x16441 [1 << 17]byte var x16442 [1 << 17]byte var x16443 [1 << 17]byte var x16444 [1 << 17]byte var x16445 [1 << 17]byte var x16446 [1 << 17]byte var x16447 [1 << 17]byte var x16448 [1 << 17]byte var x16449 [1 << 17]byte var x16450 [1 << 17]byte var x16451 [1 << 17]byte var x16452 [1 << 17]byte var x16453 [1 << 17]byte var x16454 [1 << 17]byte var x16455 [1 << 17]byte var x16456 [1 << 17]byte var x16457 [1 << 17]byte var x16458 [1 << 17]byte var x16459 [1 << 17]byte var x16460 [1 << 17]byte var x16461 [1 << 17]byte var x16462 [1 << 17]byte var x16463 [1 << 17]byte var x16464 [1 << 17]byte var x16465 [1 << 17]byte var x16466 [1 << 17]byte var x16467 [1 << 17]byte var x16468 [1 << 17]byte var x16469 [1 << 17]byte var x16470 [1 << 17]byte var x16471 [1 << 17]byte var x16472 [1 << 17]byte var x16473 [1 << 17]byte var x16474 [1 << 17]byte var x16475 [1 << 17]byte var x16476 [1 << 17]byte var x16477 [1 << 17]byte var x16478 [1 << 17]byte var x16479 [1 << 17]byte var x16480 [1 << 17]byte z = x1 z = x2 z = x3 z = x4 z = x5 z = x6 z = x7 z = x8 z = x9 z = x10 z = x11 z = x12 z = x13 z = x14 z = x15 z = x16 z = x17 z = x18 z = x19 z = x20 z = x21 z = x22 z = x23 z = x24 z = x25 z = x26 z = x27 z = x28 z = x29 z = x30 z = x31 z = x32 z = x33 z = x34 z = x35 z = x36 z = x37 z = x38 z = x39 z = x40 z = x41 z = x42 z = x43 z = x44 z = x45 z = x46 z = x47 z = x48 z = x49 z = x50 z = x51 z = x52 z = x53 z = x54 z = x55 z = x56 z = x57 z = x58 z = x59 z = x60 z = x61 z = x62 z = x63 z = x64 z = x65 z = x66 z = x67 z = x68 z = x69 z = x70 z = x71 z = x72 z = x73 z = x74 z = x75 z = x76 z = x77 z = x78 z = x79 z = x80 z = x81 z = x82 z = x83 z = x84 z = x85 z = x86 z = x87 z = x88 z = x89 z = x90 z = x91 z = x92 z = x93 z = x94 z = x95 z = x96 z = x97 z = x98 z = x99 z = x100 z = x101 z = x102 z = x103 z = x104 z = x105 z = x106 z = x107 z = x108 z = x109 z = x110 z = x111 z = x112 z = x113 z = x114 z = x115 z = x116 z = x117 z = x118 z = x119 z = x120 z = x121 z = x122 z = x123 z = x124 z = x125 z = x126 z = x127 z = x128 z = x129 z = x130 z = x131 z = x132 z = x133 z = x134 z = x135 z = x136 z = x137 z = x138 z = x139 z = x140 z = x141 z = x142 z = x143 z = x144 z = x145 z = x146 z = x147 z = x148 z = x149 z = x150 z = x151 z = x152 z = x153 z = x154 z = x155 z = x156 z = x157 z = x158 z = x159 z = x160 z = x161 z = x162 z = x163 z = x164 z = x165 z = x166 z = x167 z = x168 z = x169 z = x170 z = x171 z = x172 z = x173 z = x174 z = x175 z = x176 z = x177 z = x178 z = x179 z = x180 z = x181 z = x182 z = x183 z = x184 z = x185 z = x186 z = x187 z = x188 z = x189 z = x190 z = x191 z = x192 z = x193 z = x194 z = x195 z = x196 z = x197 z = x198 z = x199 z = x200 z = x201 z = x202 z = x203 z = x204 z = x205 z = x206 z = x207 z = x208 z = x209 z = x210 z = x211 z = x212 z = x213 z = x214 z = x215 z = x216 z = x217 z = x218 z = x219 z = x220 z = x221 z = x222 z = x223 z = x224 z = x225 z = x226 z = x227 z = x228 z = x229 z = x230 z = x231 z = x232 z = x233 z = x234 z = x235 z = x236 z = x237 z = x238 z = x239 z = x240 z = x241 z = x242 z = x243 z = x244 z = x245 z = x246 z = x247 z = x248 z = x249 z = x250 z = x251 z = x252 z = x253 z = x254 z = x255 z = x256 z = x257 z = x258 z = x259 z = x260 z = x261 z = x262 z = x263 z = x264 z = x265 z = x266 z = x267 z = x268 z = x269 z = x270 z = x271 z = x272 z = x273 z = x274 z = x275 z = x276 z = x277 z = x278 z = x279 z = x280 z = x281 z = x282 z = x283 z = x284 z = x285 z = x286 z = x287 z = x288 z = x289 z = x290 z = x291 z = x292 z = x293 z = x294 z = x295 z = x296 z = x297 z = x298 z = x299 z = x300 z = x301 z = x302 z = x303 z = x304 z = x305 z = x306 z = x307 z = x308 z = x309 z = x310 z = x311 z = x312 z = x313 z = x314 z = x315 z = x316 z = x317 z = x318 z = x319 z = x320 z = x321 z = x322 z = x323 z = x324 z = x325 z = x326 z = x327 z = x328 z = x329 z = x330 z = x331 z = x332 z = x333 z = x334 z = x335 z = x336 z = x337 z = x338 z = x339 z = x340 z = x341 z = x342 z = x343 z = x344 z = x345 z = x346 z = x347 z = x348 z = x349 z = x350 z = x351 z = x352 z = x353 z = x354 z = x355 z = x356 z = x357 z = x358 z = x359 z = x360 z = x361 z = x362 z = x363 z = x364 z = x365 z = x366 z = x367 z = x368 z = x369 z = x370 z = x371 z = x372 z = x373 z = x374 z = x375 z = x376 z = x377 z = x378 z = x379 z = x380 z = x381 z = x382 z = x383 z = x384 z = x385 z = x386 z = x387 z = x388 z = x389 z = x390 z = x391 z = x392 z = x393 z = x394 z = x395 z = x396 z = x397 z = x398 z = x399 z = x400 z = x401 z = x402 z = x403 z = x404 z = x405 z = x406 z = x407 z = x408 z = x409 z = x410 z = x411 z = x412 z = x413 z = x414 z = x415 z = x416 z = x417 z = x418 z = x419 z = x420 z = x421 z = x422 z = x423 z = x424 z = x425 z = x426 z = x427 z = x428 z = x429 z = x430 z = x431 z = x432 z = x433 z = x434 z = x435 z = x436 z = x437 z = x438 z = x439 z = x440 z = x441 z = x442 z = x443 z = x444 z = x445 z = x446 z = x447 z = x448 z = x449 z = x450 z = x451 z = x452 z = x453 z = x454 z = x455 z = x456 z = x457 z = x458 z = x459 z = x460 z = x461 z = x462 z = x463 z = x464 z = x465 z = x466 z = x467 z = x468 z = x469 z = x470 z = x471 z = x472 z = x473 z = x474 z = x475 z = x476 z = x477 z = x478 z = x479 z = x480 z = x481 z = x482 z = x483 z = x484 z = x485 z = x486 z = x487 z = x488 z = x489 z = x490 z = x491 z = x492 z = x493 z = x494 z = x495 z = x496 z = x497 z = x498 z = x499 z = x500 z = x501 z = x502 z = x503 z = x504 z = x505 z = x506 z = x507 z = x508 z = x509 z = x510 z = x511 z = x512 z = x513 z = x514 z = x515 z = x516 z = x517 z = x518 z = x519 z = x520 z = x521 z = x522 z = x523 z = x524 z = x525 z = x526 z = x527 z = x528 z = x529 z = x530 z = x531 z = x532 z = x533 z = x534 z = x535 z = x536 z = x537 z = x538 z = x539 z = x540 z = x541 z = x542 z = x543 z = x544 z = x545 z = x546 z = x547 z = x548 z = x549 z = x550 z = x551 z = x552 z = x553 z = x554 z = x555 z = x556 z = x557 z = x558 z = x559 z = x560 z = x561 z = x562 z = x563 z = x564 z = x565 z = x566 z = x567 z = x568 z = x569 z = x570 z = x571 z = x572 z = x573 z = x574 z = x575 z = x576 z = x577 z = x578 z = x579 z = x580 z = x581 z = x582 z = x583 z = x584 z = x585 z = x586 z = x587 z = x588 z = x589 z = x590 z = x591 z = x592 z = x593 z = x594 z = x595 z = x596 z = x597 z = x598 z = x599 z = x600 z = x601 z = x602 z = x603 z = x604 z = x605 z = x606 z = x607 z = x608 z = x609 z = x610 z = x611 z = x612 z = x613 z = x614 z = x615 z = x616 z = x617 z = x618 z = x619 z = x620 z = x621 z = x622 z = x623 z = x624 z = x625 z = x626 z = x627 z = x628 z = x629 z = x630 z = x631 z = x632 z = x633 z = x634 z = x635 z = x636 z = x637 z = x638 z = x639 z = x640 z = x641 z = x642 z = x643 z = x644 z = x645 z = x646 z = x647 z = x648 z = x649 z = x650 z = x651 z = x652 z = x653 z = x654 z = x655 z = x656 z = x657 z = x658 z = x659 z = x660 z = x661 z = x662 z = x663 z = x664 z = x665 z = x666 z = x667 z = x668 z = x669 z = x670 z = x671 z = x672 z = x673 z = x674 z = x675 z = x676 z = x677 z = x678 z = x679 z = x680 z = x681 z = x682 z = x683 z = x684 z = x685 z = x686 z = x687 z = x688 z = x689 z = x690 z = x691 z = x692 z = x693 z = x694 z = x695 z = x696 z = x697 z = x698 z = x699 z = x700 z = x701 z = x702 z = x703 z = x704 z = x705 z = x706 z = x707 z = x708 z = x709 z = x710 z = x711 z = x712 z = x713 z = x714 z = x715 z = x716 z = x717 z = x718 z = x719 z = x720 z = x721 z = x722 z = x723 z = x724 z = x725 z = x726 z = x727 z = x728 z = x729 z = x730 z = x731 z = x732 z = x733 z = x734 z = x735 z = x736 z = x737 z = x738 z = x739 z = x740 z = x741 z = x742 z = x743 z = x744 z = x745 z = x746 z = x747 z = x748 z = x749 z = x750 z = x751 z = x752 z = x753 z = x754 z = x755 z = x756 z = x757 z = x758 z = x759 z = x760 z = x761 z = x762 z = x763 z = x764 z = x765 z = x766 z = x767 z = x768 z = x769 z = x770 z = x771 z = x772 z = x773 z = x774 z = x775 z = x776 z = x777 z = x778 z = x779 z = x780 z = x781 z = x782 z = x783 z = x784 z = x785 z = x786 z = x787 z = x788 z = x789 z = x790 z = x791 z = x792 z = x793 z = x794 z = x795 z = x796 z = x797 z = x798 z = x799 z = x800 z = x801 z = x802 z = x803 z = x804 z = x805 z = x806 z = x807 z = x808 z = x809 z = x810 z = x811 z = x812 z = x813 z = x814 z = x815 z = x816 z = x817 z = x818 z = x819 z = x820 z = x821 z = x822 z = x823 z = x824 z = x825 z = x826 z = x827 z = x828 z = x829 z = x830 z = x831 z = x832 z = x833 z = x834 z = x835 z = x836 z = x837 z = x838 z = x839 z = x840 z = x841 z = x842 z = x843 z = x844 z = x845 z = x846 z = x847 z = x848 z = x849 z = x850 z = x851 z = x852 z = x853 z = x854 z = x855 z = x856 z = x857 z = x858 z = x859 z = x860 z = x861 z = x862 z = x863 z = x864 z = x865 z = x866 z = x867 z = x868 z = x869 z = x870 z = x871 z = x872 z = x873 z = x874 z = x875 z = x876 z = x877 z = x878 z = x879 z = x880 z = x881 z = x882 z = x883 z = x884 z = x885 z = x886 z = x887 z = x888 z = x889 z = x890 z = x891 z = x892 z = x893 z = x894 z = x895 z = x896 z = x897 z = x898 z = x899 z = x900 z = x901 z = x902 z = x903 z = x904 z = x905 z = x906 z = x907 z = x908 z = x909 z = x910 z = x911 z = x912 z = x913 z = x914 z = x915 z = x916 z = x917 z = x918 z = x919 z = x920 z = x921 z = x922 z = x923 z = x924 z = x925 z = x926 z = x927 z = x928 z = x929 z = x930 z = x931 z = x932 z = x933 z = x934 z = x935 z = x936 z = x937 z = x938 z = x939 z = x940 z = x941 z = x942 z = x943 z = x944 z = x945 z = x946 z = x947 z = x948 z = x949 z = x950 z = x951 z = x952 z = x953 z = x954 z = x955 z = x956 z = x957 z = x958 z = x959 z = x960 z = x961 z = x962 z = x963 z = x964 z = x965 z = x966 z = x967 z = x968 z = x969 z = x970 z = x971 z = x972 z = x973 z = x974 z = x975 z = x976 z = x977 z = x978 z = x979 z = x980 z = x981 z = x982 z = x983 z = x984 z = x985 z = x986 z = x987 z = x988 z = x989 z = x990 z = x991 z = x992 z = x993 z = x994 z = x995 z = x996 z = x997 z = x998 z = x999 z = x1000 z = x1001 z = x1002 z = x1003 z = x1004 z = x1005 z = x1006 z = x1007 z = x1008 z = x1009 z = x1010 z = x1011 z = x1012 z = x1013 z = x1014 z = x1015 z = x1016 z = x1017 z = x1018 z = x1019 z = x1020 z = x1021 z = x1022 z = x1023 z = x1024 z = x1025 z = x1026 z = x1027 z = x1028 z = x1029 z = x1030 z = x1031 z = x1032 z = x1033 z = x1034 z = x1035 z = x1036 z = x1037 z = x1038 z = x1039 z = x1040 z = x1041 z = x1042 z = x1043 z = x1044 z = x1045 z = x1046 z = x1047 z = x1048 z = x1049 z = x1050 z = x1051 z = x1052 z = x1053 z = x1054 z = x1055 z = x1056 z = x1057 z = x1058 z = x1059 z = x1060 z = x1061 z = x1062 z = x1063 z = x1064 z = x1065 z = x1066 z = x1067 z = x1068 z = x1069 z = x1070 z = x1071 z = x1072 z = x1073 z = x1074 z = x1075 z = x1076 z = x1077 z = x1078 z = x1079 z = x1080 z = x1081 z = x1082 z = x1083 z = x1084 z = x1085 z = x1086 z = x1087 z = x1088 z = x1089 z = x1090 z = x1091 z = x1092 z = x1093 z = x1094 z = x1095 z = x1096 z = x1097 z = x1098 z = x1099 z = x1100 z = x1101 z = x1102 z = x1103 z = x1104 z = x1105 z = x1106 z = x1107 z = x1108 z = x1109 z = x1110 z = x1111 z = x1112 z = x1113 z = x1114 z = x1115 z = x1116 z = x1117 z = x1118 z = x1119 z = x1120 z = x1121 z = x1122 z = x1123 z = x1124 z = x1125 z = x1126 z = x1127 z = x1128 z = x1129 z = x1130 z = x1131 z = x1132 z = x1133 z = x1134 z = x1135 z = x1136 z = x1137 z = x1138 z = x1139 z = x1140 z = x1141 z = x1142 z = x1143 z = x1144 z = x1145 z = x1146 z = x1147 z = x1148 z = x1149 z = x1150 z = x1151 z = x1152 z = x1153 z = x1154 z = x1155 z = x1156 z = x1157 z = x1158 z = x1159 z = x1160 z = x1161 z = x1162 z = x1163 z = x1164 z = x1165 z = x1166 z = x1167 z = x1168 z = x1169 z = x1170 z = x1171 z = x1172 z = x1173 z = x1174 z = x1175 z = x1176 z = x1177 z = x1178 z = x1179 z = x1180 z = x1181 z = x1182 z = x1183 z = x1184 z = x1185 z = x1186 z = x1187 z = x1188 z = x1189 z = x1190 z = x1191 z = x1192 z = x1193 z = x1194 z = x1195 z = x1196 z = x1197 z = x1198 z = x1199 z = x1200 z = x1201 z = x1202 z = x1203 z = x1204 z = x1205 z = x1206 z = x1207 z = x1208 z = x1209 z = x1210 z = x1211 z = x1212 z = x1213 z = x1214 z = x1215 z = x1216 z = x1217 z = x1218 z = x1219 z = x1220 z = x1221 z = x1222 z = x1223 z = x1224 z = x1225 z = x1226 z = x1227 z = x1228 z = x1229 z = x1230 z = x1231 z = x1232 z = x1233 z = x1234 z = x1235 z = x1236 z = x1237 z = x1238 z = x1239 z = x1240 z = x1241 z = x1242 z = x1243 z = x1244 z = x1245 z = x1246 z = x1247 z = x1248 z = x1249 z = x1250 z = x1251 z = x1252 z = x1253 z = x1254 z = x1255 z = x1256 z = x1257 z = x1258 z = x1259 z = x1260 z = x1261 z = x1262 z = x1263 z = x1264 z = x1265 z = x1266 z = x1267 z = x1268 z = x1269 z = x1270 z = x1271 z = x1272 z = x1273 z = x1274 z = x1275 z = x1276 z = x1277 z = x1278 z = x1279 z = x1280 z = x1281 z = x1282 z = x1283 z = x1284 z = x1285 z = x1286 z = x1287 z = x1288 z = x1289 z = x1290 z = x1291 z = x1292 z = x1293 z = x1294 z = x1295 z = x1296 z = x1297 z = x1298 z = x1299 z = x1300 z = x1301 z = x1302 z = x1303 z = x1304 z = x1305 z = x1306 z = x1307 z = x1308 z = x1309 z = x1310 z = x1311 z = x1312 z = x1313 z = x1314 z = x1315 z = x1316 z = x1317 z = x1318 z = x1319 z = x1320 z = x1321 z = x1322 z = x1323 z = x1324 z = x1325 z = x1326 z = x1327 z = x1328 z = x1329 z = x1330 z = x1331 z = x1332 z = x1333 z = x1334 z = x1335 z = x1336 z = x1337 z = x1338 z = x1339 z = x1340 z = x1341 z = x1342 z = x1343 z = x1344 z = x1345 z = x1346 z = x1347 z = x1348 z = x1349 z = x1350 z = x1351 z = x1352 z = x1353 z = x1354 z = x1355 z = x1356 z = x1357 z = x1358 z = x1359 z = x1360 z = x1361 z = x1362 z = x1363 z = x1364 z = x1365 z = x1366 z = x1367 z = x1368 z = x1369 z = x1370 z = x1371 z = x1372 z = x1373 z = x1374 z = x1375 z = x1376 z = x1377 z = x1378 z = x1379 z = x1380 z = x1381 z = x1382 z = x1383 z = x1384 z = x1385 z = x1386 z = x1387 z = x1388 z = x1389 z = x1390 z = x1391 z = x1392 z = x1393 z = x1394 z = x1395 z = x1396 z = x1397 z = x1398 z = x1399 z = x1400 z = x1401 z = x1402 z = x1403 z = x1404 z = x1405 z = x1406 z = x1407 z = x1408 z = x1409 z = x1410 z = x1411 z = x1412 z = x1413 z = x1414 z = x1415 z = x1416 z = x1417 z = x1418 z = x1419 z = x1420 z = x1421 z = x1422 z = x1423 z = x1424 z = x1425 z = x1426 z = x1427 z = x1428 z = x1429 z = x1430 z = x1431 z = x1432 z = x1433 z = x1434 z = x1435 z = x1436 z = x1437 z = x1438 z = x1439 z = x1440 z = x1441 z = x1442 z = x1443 z = x1444 z = x1445 z = x1446 z = x1447 z = x1448 z = x1449 z = x1450 z = x1451 z = x1452 z = x1453 z = x1454 z = x1455 z = x1456 z = x1457 z = x1458 z = x1459 z = x1460 z = x1461 z = x1462 z = x1463 z = x1464 z = x1465 z = x1466 z = x1467 z = x1468 z = x1469 z = x1470 z = x1471 z = x1472 z = x1473 z = x1474 z = x1475 z = x1476 z = x1477 z = x1478 z = x1479 z = x1480 z = x1481 z = x1482 z = x1483 z = x1484 z = x1485 z = x1486 z = x1487 z = x1488 z = x1489 z = x1490 z = x1491 z = x1492 z = x1493 z = x1494 z = x1495 z = x1496 z = x1497 z = x1498 z = x1499 z = x1500 z = x1501 z = x1502 z = x1503 z = x1504 z = x1505 z = x1506 z = x1507 z = x1508 z = x1509 z = x1510 z = x1511 z = x1512 z = x1513 z = x1514 z = x1515 z = x1516 z = x1517 z = x1518 z = x1519 z = x1520 z = x1521 z = x1522 z = x1523 z = x1524 z = x1525 z = x1526 z = x1527 z = x1528 z = x1529 z = x1530 z = x1531 z = x1532 z = x1533 z = x1534 z = x1535 z = x1536 z = x1537 z = x1538 z = x1539 z = x1540 z = x1541 z = x1542 z = x1543 z = x1544 z = x1545 z = x1546 z = x1547 z = x1548 z = x1549 z = x1550 z = x1551 z = x1552 z = x1553 z = x1554 z = x1555 z = x1556 z = x1557 z = x1558 z = x1559 z = x1560 z = x1561 z = x1562 z = x1563 z = x1564 z = x1565 z = x1566 z = x1567 z = x1568 z = x1569 z = x1570 z = x1571 z = x1572 z = x1573 z = x1574 z = x1575 z = x1576 z = x1577 z = x1578 z = x1579 z = x1580 z = x1581 z = x1582 z = x1583 z = x1584 z = x1585 z = x1586 z = x1587 z = x1588 z = x1589 z = x1590 z = x1591 z = x1592 z = x1593 z = x1594 z = x1595 z = x1596 z = x1597 z = x1598 z = x1599 z = x1600 z = x1601 z = x1602 z = x1603 z = x1604 z = x1605 z = x1606 z = x1607 z = x1608 z = x1609 z = x1610 z = x1611 z = x1612 z = x1613 z = x1614 z = x1615 z = x1616 z = x1617 z = x1618 z = x1619 z = x1620 z = x1621 z = x1622 z = x1623 z = x1624 z = x1625 z = x1626 z = x1627 z = x1628 z = x1629 z = x1630 z = x1631 z = x1632 z = x1633 z = x1634 z = x1635 z = x1636 z = x1637 z = x1638 z = x1639 z = x1640 z = x1641 z = x1642 z = x1643 z = x1644 z = x1645 z = x1646 z = x1647 z = x1648 z = x1649 z = x1650 z = x1651 z = x1652 z = x1653 z = x1654 z = x1655 z = x1656 z = x1657 z = x1658 z = x1659 z = x1660 z = x1661 z = x1662 z = x1663 z = x1664 z = x1665 z = x1666 z = x1667 z = x1668 z = x1669 z = x1670 z = x1671 z = x1672 z = x1673 z = x1674 z = x1675 z = x1676 z = x1677 z = x1678 z = x1679 z = x1680 z = x1681 z = x1682 z = x1683 z = x1684 z = x1685 z = x1686 z = x1687 z = x1688 z = x1689 z = x1690 z = x1691 z = x1692 z = x1693 z = x1694 z = x1695 z = x1696 z = x1697 z = x1698 z = x1699 z = x1700 z = x1701 z = x1702 z = x1703 z = x1704 z = x1705 z = x1706 z = x1707 z = x1708 z = x1709 z = x1710 z = x1711 z = x1712 z = x1713 z = x1714 z = x1715 z = x1716 z = x1717 z = x1718 z = x1719 z = x1720 z = x1721 z = x1722 z = x1723 z = x1724 z = x1725 z = x1726 z = x1727 z = x1728 z = x1729 z = x1730 z = x1731 z = x1732 z = x1733 z = x1734 z = x1735 z = x1736 z = x1737 z = x1738 z = x1739 z = x1740 z = x1741 z = x1742 z = x1743 z = x1744 z = x1745 z = x1746 z = x1747 z = x1748 z = x1749 z = x1750 z = x1751 z = x1752 z = x1753 z = x1754 z = x1755 z = x1756 z = x1757 z = x1758 z = x1759 z = x1760 z = x1761 z = x1762 z = x1763 z = x1764 z = x1765 z = x1766 z = x1767 z = x1768 z = x1769 z = x1770 z = x1771 z = x1772 z = x1773 z = x1774 z = x1775 z = x1776 z = x1777 z = x1778 z = x1779 z = x1780 z = x1781 z = x1782 z = x1783 z = x1784 z = x1785 z = x1786 z = x1787 z = x1788 z = x1789 z = x1790 z = x1791 z = x1792 z = x1793 z = x1794 z = x1795 z = x1796 z = x1797 z = x1798 z = x1799 z = x1800 z = x1801 z = x1802 z = x1803 z = x1804 z = x1805 z = x1806 z = x1807 z = x1808 z = x1809 z = x1810 z = x1811 z = x1812 z = x1813 z = x1814 z = x1815 z = x1816 z = x1817 z = x1818 z = x1819 z = x1820 z = x1821 z = x1822 z = x1823 z = x1824 z = x1825 z = x1826 z = x1827 z = x1828 z = x1829 z = x1830 z = x1831 z = x1832 z = x1833 z = x1834 z = x1835 z = x1836 z = x1837 z = x1838 z = x1839 z = x1840 z = x1841 z = x1842 z = x1843 z = x1844 z = x1845 z = x1846 z = x1847 z = x1848 z = x1849 z = x1850 z = x1851 z = x1852 z = x1853 z = x1854 z = x1855 z = x1856 z = x1857 z = x1858 z = x1859 z = x1860 z = x1861 z = x1862 z = x1863 z = x1864 z = x1865 z = x1866 z = x1867 z = x1868 z = x1869 z = x1870 z = x1871 z = x1872 z = x1873 z = x1874 z = x1875 z = x1876 z = x1877 z = x1878 z = x1879 z = x1880 z = x1881 z = x1882 z = x1883 z = x1884 z = x1885 z = x1886 z = x1887 z = x1888 z = x1889 z = x1890 z = x1891 z = x1892 z = x1893 z = x1894 z = x1895 z = x1896 z = x1897 z = x1898 z = x1899 z = x1900 z = x1901 z = x1902 z = x1903 z = x1904 z = x1905 z = x1906 z = x1907 z = x1908 z = x1909 z = x1910 z = x1911 z = x1912 z = x1913 z = x1914 z = x1915 z = x1916 z = x1917 z = x1918 z = x1919 z = x1920 z = x1921 z = x1922 z = x1923 z = x1924 z = x1925 z = x1926 z = x1927 z = x1928 z = x1929 z = x1930 z = x1931 z = x1932 z = x1933 z = x1934 z = x1935 z = x1936 z = x1937 z = x1938 z = x1939 z = x1940 z = x1941 z = x1942 z = x1943 z = x1944 z = x1945 z = x1946 z = x1947 z = x1948 z = x1949 z = x1950 z = x1951 z = x1952 z = x1953 z = x1954 z = x1955 z = x1956 z = x1957 z = x1958 z = x1959 z = x1960 z = x1961 z = x1962 z = x1963 z = x1964 z = x1965 z = x1966 z = x1967 z = x1968 z = x1969 z = x1970 z = x1971 z = x1972 z = x1973 z = x1974 z = x1975 z = x1976 z = x1977 z = x1978 z = x1979 z = x1980 z = x1981 z = x1982 z = x1983 z = x1984 z = x1985 z = x1986 z = x1987 z = x1988 z = x1989 z = x1990 z = x1991 z = x1992 z = x1993 z = x1994 z = x1995 z = x1996 z = x1997 z = x1998 z = x1999 z = x2000 z = x2001 z = x2002 z = x2003 z = x2004 z = x2005 z = x2006 z = x2007 z = x2008 z = x2009 z = x2010 z = x2011 z = x2012 z = x2013 z = x2014 z = x2015 z = x2016 z = x2017 z = x2018 z = x2019 z = x2020 z = x2021 z = x2022 z = x2023 z = x2024 z = x2025 z = x2026 z = x2027 z = x2028 z = x2029 z = x2030 z = x2031 z = x2032 z = x2033 z = x2034 z = x2035 z = x2036 z = x2037 z = x2038 z = x2039 z = x2040 z = x2041 z = x2042 z = x2043 z = x2044 z = x2045 z = x2046 z = x2047 z = x2048 z = x2049 z = x2050 z = x2051 z = x2052 z = x2053 z = x2054 z = x2055 z = x2056 z = x2057 z = x2058 z = x2059 z = x2060 z = x2061 z = x2062 z = x2063 z = x2064 z = x2065 z = x2066 z = x2067 z = x2068 z = x2069 z = x2070 z = x2071 z = x2072 z = x2073 z = x2074 z = x2075 z = x2076 z = x2077 z = x2078 z = x2079 z = x2080 z = x2081 z = x2082 z = x2083 z = x2084 z = x2085 z = x2086 z = x2087 z = x2088 z = x2089 z = x2090 z = x2091 z = x2092 z = x2093 z = x2094 z = x2095 z = x2096 z = x2097 z = x2098 z = x2099 z = x2100 z = x2101 z = x2102 z = x2103 z = x2104 z = x2105 z = x2106 z = x2107 z = x2108 z = x2109 z = x2110 z = x2111 z = x2112 z = x2113 z = x2114 z = x2115 z = x2116 z = x2117 z = x2118 z = x2119 z = x2120 z = x2121 z = x2122 z = x2123 z = x2124 z = x2125 z = x2126 z = x2127 z = x2128 z = x2129 z = x2130 z = x2131 z = x2132 z = x2133 z = x2134 z = x2135 z = x2136 z = x2137 z = x2138 z = x2139 z = x2140 z = x2141 z = x2142 z = x2143 z = x2144 z = x2145 z = x2146 z = x2147 z = x2148 z = x2149 z = x2150 z = x2151 z = x2152 z = x2153 z = x2154 z = x2155 z = x2156 z = x2157 z = x2158 z = x2159 z = x2160 z = x2161 z = x2162 z = x2163 z = x2164 z = x2165 z = x2166 z = x2167 z = x2168 z = x2169 z = x2170 z = x2171 z = x2172 z = x2173 z = x2174 z = x2175 z = x2176 z = x2177 z = x2178 z = x2179 z = x2180 z = x2181 z = x2182 z = x2183 z = x2184 z = x2185 z = x2186 z = x2187 z = x2188 z = x2189 z = x2190 z = x2191 z = x2192 z = x2193 z = x2194 z = x2195 z = x2196 z = x2197 z = x2198 z = x2199 z = x2200 z = x2201 z = x2202 z = x2203 z = x2204 z = x2205 z = x2206 z = x2207 z = x2208 z = x2209 z = x2210 z = x2211 z = x2212 z = x2213 z = x2214 z = x2215 z = x2216 z = x2217 z = x2218 z = x2219 z = x2220 z = x2221 z = x2222 z = x2223 z = x2224 z = x2225 z = x2226 z = x2227 z = x2228 z = x2229 z = x2230 z = x2231 z = x2232 z = x2233 z = x2234 z = x2235 z = x2236 z = x2237 z = x2238 z = x2239 z = x2240 z = x2241 z = x2242 z = x2243 z = x2244 z = x2245 z = x2246 z = x2247 z = x2248 z = x2249 z = x2250 z = x2251 z = x2252 z = x2253 z = x2254 z = x2255 z = x2256 z = x2257 z = x2258 z = x2259 z = x2260 z = x2261 z = x2262 z = x2263 z = x2264 z = x2265 z = x2266 z = x2267 z = x2268 z = x2269 z = x2270 z = x2271 z = x2272 z = x2273 z = x2274 z = x2275 z = x2276 z = x2277 z = x2278 z = x2279 z = x2280 z = x2281 z = x2282 z = x2283 z = x2284 z = x2285 z = x2286 z = x2287 z = x2288 z = x2289 z = x2290 z = x2291 z = x2292 z = x2293 z = x2294 z = x2295 z = x2296 z = x2297 z = x2298 z = x2299 z = x2300 z = x2301 z = x2302 z = x2303 z = x2304 z = x2305 z = x2306 z = x2307 z = x2308 z = x2309 z = x2310 z = x2311 z = x2312 z = x2313 z = x2314 z = x2315 z = x2316 z = x2317 z = x2318 z = x2319 z = x2320 z = x2321 z = x2322 z = x2323 z = x2324 z = x2325 z = x2326 z = x2327 z = x2328 z = x2329 z = x2330 z = x2331 z = x2332 z = x2333 z = x2334 z = x2335 z = x2336 z = x2337 z = x2338 z = x2339 z = x2340 z = x2341 z = x2342 z = x2343 z = x2344 z = x2345 z = x2346 z = x2347 z = x2348 z = x2349 z = x2350 z = x2351 z = x2352 z = x2353 z = x2354 z = x2355 z = x2356 z = x2357 z = x2358 z = x2359 z = x2360 z = x2361 z = x2362 z = x2363 z = x2364 z = x2365 z = x2366 z = x2367 z = x2368 z = x2369 z = x2370 z = x2371 z = x2372 z = x2373 z = x2374 z = x2375 z = x2376 z = x2377 z = x2378 z = x2379 z = x2380 z = x2381 z = x2382 z = x2383 z = x2384 z = x2385 z = x2386 z = x2387 z = x2388 z = x2389 z = x2390 z = x2391 z = x2392 z = x2393 z = x2394 z = x2395 z = x2396 z = x2397 z = x2398 z = x2399 z = x2400 z = x2401 z = x2402 z = x2403 z = x2404 z = x2405 z = x2406 z = x2407 z = x2408 z = x2409 z = x2410 z = x2411 z = x2412 z = x2413 z = x2414 z = x2415 z = x2416 z = x2417 z = x2418 z = x2419 z = x2420 z = x2421 z = x2422 z = x2423 z = x2424 z = x2425 z = x2426 z = x2427 z = x2428 z = x2429 z = x2430 z = x2431 z = x2432 z = x2433 z = x2434 z = x2435 z = x2436 z = x2437 z = x2438 z = x2439 z = x2440 z = x2441 z = x2442 z = x2443 z = x2444 z = x2445 z = x2446 z = x2447 z = x2448 z = x2449 z = x2450 z = x2451 z = x2452 z = x2453 z = x2454 z = x2455 z = x2456 z = x2457 z = x2458 z = x2459 z = x2460 z = x2461 z = x2462 z = x2463 z = x2464 z = x2465 z = x2466 z = x2467 z = x2468 z = x2469 z = x2470 z = x2471 z = x2472 z = x2473 z = x2474 z = x2475 z = x2476 z = x2477 z = x2478 z = x2479 z = x2480 z = x2481 z = x2482 z = x2483 z = x2484 z = x2485 z = x2486 z = x2487 z = x2488 z = x2489 z = x2490 z = x2491 z = x2492 z = x2493 z = x2494 z = x2495 z = x2496 z = x2497 z = x2498 z = x2499 z = x2500 z = x2501 z = x2502 z = x2503 z = x2504 z = x2505 z = x2506 z = x2507 z = x2508 z = x2509 z = x2510 z = x2511 z = x2512 z = x2513 z = x2514 z = x2515 z = x2516 z = x2517 z = x2518 z = x2519 z = x2520 z = x2521 z = x2522 z = x2523 z = x2524 z = x2525 z = x2526 z = x2527 z = x2528 z = x2529 z = x2530 z = x2531 z = x2532 z = x2533 z = x2534 z = x2535 z = x2536 z = x2537 z = x2538 z = x2539 z = x2540 z = x2541 z = x2542 z = x2543 z = x2544 z = x2545 z = x2546 z = x2547 z = x2548 z = x2549 z = x2550 z = x2551 z = x2552 z = x2553 z = x2554 z = x2555 z = x2556 z = x2557 z = x2558 z = x2559 z = x2560 z = x2561 z = x2562 z = x2563 z = x2564 z = x2565 z = x2566 z = x2567 z = x2568 z = x2569 z = x2570 z = x2571 z = x2572 z = x2573 z = x2574 z = x2575 z = x2576 z = x2577 z = x2578 z = x2579 z = x2580 z = x2581 z = x2582 z = x2583 z = x2584 z = x2585 z = x2586 z = x2587 z = x2588 z = x2589 z = x2590 z = x2591 z = x2592 z = x2593 z = x2594 z = x2595 z = x2596 z = x2597 z = x2598 z = x2599 z = x2600 z = x2601 z = x2602 z = x2603 z = x2604 z = x2605 z = x2606 z = x2607 z = x2608 z = x2609 z = x2610 z = x2611 z = x2612 z = x2613 z = x2614 z = x2615 z = x2616 z = x2617 z = x2618 z = x2619 z = x2620 z = x2621 z = x2622 z = x2623 z = x2624 z = x2625 z = x2626 z = x2627 z = x2628 z = x2629 z = x2630 z = x2631 z = x2632 z = x2633 z = x2634 z = x2635 z = x2636 z = x2637 z = x2638 z = x2639 z = x2640 z = x2641 z = x2642 z = x2643 z = x2644 z = x2645 z = x2646 z = x2647 z = x2648 z = x2649 z = x2650 z = x2651 z = x2652 z = x2653 z = x2654 z = x2655 z = x2656 z = x2657 z = x2658 z = x2659 z = x2660 z = x2661 z = x2662 z = x2663 z = x2664 z = x2665 z = x2666 z = x2667 z = x2668 z = x2669 z = x2670 z = x2671 z = x2672 z = x2673 z = x2674 z = x2675 z = x2676 z = x2677 z = x2678 z = x2679 z = x2680 z = x2681 z = x2682 z = x2683 z = x2684 z = x2685 z = x2686 z = x2687 z = x2688 z = x2689 z = x2690 z = x2691 z = x2692 z = x2693 z = x2694 z = x2695 z = x2696 z = x2697 z = x2698 z = x2699 z = x2700 z = x2701 z = x2702 z = x2703 z = x2704 z = x2705 z = x2706 z = x2707 z = x2708 z = x2709 z = x2710 z = x2711 z = x2712 z = x2713 z = x2714 z = x2715 z = x2716 z = x2717 z = x2718 z = x2719 z = x2720 z = x2721 z = x2722 z = x2723 z = x2724 z = x2725 z = x2726 z = x2727 z = x2728 z = x2729 z = x2730 z = x2731 z = x2732 z = x2733 z = x2734 z = x2735 z = x2736 z = x2737 z = x2738 z = x2739 z = x2740 z = x2741 z = x2742 z = x2743 z = x2744 z = x2745 z = x2746 z = x2747 z = x2748 z = x2749 z = x2750 z = x2751 z = x2752 z = x2753 z = x2754 z = x2755 z = x2756 z = x2757 z = x2758 z = x2759 z = x2760 z = x2761 z = x2762 z = x2763 z = x2764 z = x2765 z = x2766 z = x2767 z = x2768 z = x2769 z = x2770 z = x2771 z = x2772 z = x2773 z = x2774 z = x2775 z = x2776 z = x2777 z = x2778 z = x2779 z = x2780 z = x2781 z = x2782 z = x2783 z = x2784 z = x2785 z = x2786 z = x2787 z = x2788 z = x2789 z = x2790 z = x2791 z = x2792 z = x2793 z = x2794 z = x2795 z = x2796 z = x2797 z = x2798 z = x2799 z = x2800 z = x2801 z = x2802 z = x2803 z = x2804 z = x2805 z = x2806 z = x2807 z = x2808 z = x2809 z = x2810 z = x2811 z = x2812 z = x2813 z = x2814 z = x2815 z = x2816 z = x2817 z = x2818 z = x2819 z = x2820 z = x2821 z = x2822 z = x2823 z = x2824 z = x2825 z = x2826 z = x2827 z = x2828 z = x2829 z = x2830 z = x2831 z = x2832 z = x2833 z = x2834 z = x2835 z = x2836 z = x2837 z = x2838 z = x2839 z = x2840 z = x2841 z = x2842 z = x2843 z = x2844 z = x2845 z = x2846 z = x2847 z = x2848 z = x2849 z = x2850 z = x2851 z = x2852 z = x2853 z = x2854 z = x2855 z = x2856 z = x2857 z = x2858 z = x2859 z = x2860 z = x2861 z = x2862 z = x2863 z = x2864 z = x2865 z = x2866 z = x2867 z = x2868 z = x2869 z = x2870 z = x2871 z = x2872 z = x2873 z = x2874 z = x2875 z = x2876 z = x2877 z = x2878 z = x2879 z = x2880 z = x2881 z = x2882 z = x2883 z = x2884 z = x2885 z = x2886 z = x2887 z = x2888 z = x2889 z = x2890 z = x2891 z = x2892 z = x2893 z = x2894 z = x2895 z = x2896 z = x2897 z = x2898 z = x2899 z = x2900 z = x2901 z = x2902 z = x2903 z = x2904 z = x2905 z = x2906 z = x2907 z = x2908 z = x2909 z = x2910 z = x2911 z = x2912 z = x2913 z = x2914 z = x2915 z = x2916 z = x2917 z = x2918 z = x2919 z = x2920 z = x2921 z = x2922 z = x2923 z = x2924 z = x2925 z = x2926 z = x2927 z = x2928 z = x2929 z = x2930 z = x2931 z = x2932 z = x2933 z = x2934 z = x2935 z = x2936 z = x2937 z = x2938 z = x2939 z = x2940 z = x2941 z = x2942 z = x2943 z = x2944 z = x2945 z = x2946 z = x2947 z = x2948 z = x2949 z = x2950 z = x2951 z = x2952 z = x2953 z = x2954 z = x2955 z = x2956 z = x2957 z = x2958 z = x2959 z = x2960 z = x2961 z = x2962 z = x2963 z = x2964 z = x2965 z = x2966 z = x2967 z = x2968 z = x2969 z = x2970 z = x2971 z = x2972 z = x2973 z = x2974 z = x2975 z = x2976 z = x2977 z = x2978 z = x2979 z = x2980 z = x2981 z = x2982 z = x2983 z = x2984 z = x2985 z = x2986 z = x2987 z = x2988 z = x2989 z = x2990 z = x2991 z = x2992 z = x2993 z = x2994 z = x2995 z = x2996 z = x2997 z = x2998 z = x2999 z = x3000 z = x3001 z = x3002 z = x3003 z = x3004 z = x3005 z = x3006 z = x3007 z = x3008 z = x3009 z = x3010 z = x3011 z = x3012 z = x3013 z = x3014 z = x3015 z = x3016 z = x3017 z = x3018 z = x3019 z = x3020 z = x3021 z = x3022 z = x3023 z = x3024 z = x3025 z = x3026 z = x3027 z = x3028 z = x3029 z = x3030 z = x3031 z = x3032 z = x3033 z = x3034 z = x3035 z = x3036 z = x3037 z = x3038 z = x3039 z = x3040 z = x3041 z = x3042 z = x3043 z = x3044 z = x3045 z = x3046 z = x3047 z = x3048 z = x3049 z = x3050 z = x3051 z = x3052 z = x3053 z = x3054 z = x3055 z = x3056 z = x3057 z = x3058 z = x3059 z = x3060 z = x3061 z = x3062 z = x3063 z = x3064 z = x3065 z = x3066 z = x3067 z = x3068 z = x3069 z = x3070 z = x3071 z = x3072 z = x3073 z = x3074 z = x3075 z = x3076 z = x3077 z = x3078 z = x3079 z = x3080 z = x3081 z = x3082 z = x3083 z = x3084 z = x3085 z = x3086 z = x3087 z = x3088 z = x3089 z = x3090 z = x3091 z = x3092 z = x3093 z = x3094 z = x3095 z = x3096 z = x3097 z = x3098 z = x3099 z = x3100 z = x3101 z = x3102 z = x3103 z = x3104 z = x3105 z = x3106 z = x3107 z = x3108 z = x3109 z = x3110 z = x3111 z = x3112 z = x3113 z = x3114 z = x3115 z = x3116 z = x3117 z = x3118 z = x3119 z = x3120 z = x3121 z = x3122 z = x3123 z = x3124 z = x3125 z = x3126 z = x3127 z = x3128 z = x3129 z = x3130 z = x3131 z = x3132 z = x3133 z = x3134 z = x3135 z = x3136 z = x3137 z = x3138 z = x3139 z = x3140 z = x3141 z = x3142 z = x3143 z = x3144 z = x3145 z = x3146 z = x3147 z = x3148 z = x3149 z = x3150 z = x3151 z = x3152 z = x3153 z = x3154 z = x3155 z = x3156 z = x3157 z = x3158 z = x3159 z = x3160 z = x3161 z = x3162 z = x3163 z = x3164 z = x3165 z = x3166 z = x3167 z = x3168 z = x3169 z = x3170 z = x3171 z = x3172 z = x3173 z = x3174 z = x3175 z = x3176 z = x3177 z = x3178 z = x3179 z = x3180 z = x3181 z = x3182 z = x3183 z = x3184 z = x3185 z = x3186 z = x3187 z = x3188 z = x3189 z = x3190 z = x3191 z = x3192 z = x3193 z = x3194 z = x3195 z = x3196 z = x3197 z = x3198 z = x3199 z = x3200 z = x3201 z = x3202 z = x3203 z = x3204 z = x3205 z = x3206 z = x3207 z = x3208 z = x3209 z = x3210 z = x3211 z = x3212 z = x3213 z = x3214 z = x3215 z = x3216 z = x3217 z = x3218 z = x3219 z = x3220 z = x3221 z = x3222 z = x3223 z = x3224 z = x3225 z = x3226 z = x3227 z = x3228 z = x3229 z = x3230 z = x3231 z = x3232 z = x3233 z = x3234 z = x3235 z = x3236 z = x3237 z = x3238 z = x3239 z = x3240 z = x3241 z = x3242 z = x3243 z = x3244 z = x3245 z = x3246 z = x3247 z = x3248 z = x3249 z = x3250 z = x3251 z = x3252 z = x3253 z = x3254 z = x3255 z = x3256 z = x3257 z = x3258 z = x3259 z = x3260 z = x3261 z = x3262 z = x3263 z = x3264 z = x3265 z = x3266 z = x3267 z = x3268 z = x3269 z = x3270 z = x3271 z = x3272 z = x3273 z = x3274 z = x3275 z = x3276 z = x3277 z = x3278 z = x3279 z = x3280 z = x3281 z = x3282 z = x3283 z = x3284 z = x3285 z = x3286 z = x3287 z = x3288 z = x3289 z = x3290 z = x3291 z = x3292 z = x3293 z = x3294 z = x3295 z = x3296 z = x3297 z = x3298 z = x3299 z = x3300 z = x3301 z = x3302 z = x3303 z = x3304 z = x3305 z = x3306 z = x3307 z = x3308 z = x3309 z = x3310 z = x3311 z = x3312 z = x3313 z = x3314 z = x3315 z = x3316 z = x3317 z = x3318 z = x3319 z = x3320 z = x3321 z = x3322 z = x3323 z = x3324 z = x3325 z = x3326 z = x3327 z = x3328 z = x3329 z = x3330 z = x3331 z = x3332 z = x3333 z = x3334 z = x3335 z = x3336 z = x3337 z = x3338 z = x3339 z = x3340 z = x3341 z = x3342 z = x3343 z = x3344 z = x3345 z = x3346 z = x3347 z = x3348 z = x3349 z = x3350 z = x3351 z = x3352 z = x3353 z = x3354 z = x3355 z = x3356 z = x3357 z = x3358 z = x3359 z = x3360 z = x3361 z = x3362 z = x3363 z = x3364 z = x3365 z = x3366 z = x3367 z = x3368 z = x3369 z = x3370 z = x3371 z = x3372 z = x3373 z = x3374 z = x3375 z = x3376 z = x3377 z = x3378 z = x3379 z = x3380 z = x3381 z = x3382 z = x3383 z = x3384 z = x3385 z = x3386 z = x3387 z = x3388 z = x3389 z = x3390 z = x3391 z = x3392 z = x3393 z = x3394 z = x3395 z = x3396 z = x3397 z = x3398 z = x3399 z = x3400 z = x3401 z = x3402 z = x3403 z = x3404 z = x3405 z = x3406 z = x3407 z = x3408 z = x3409 z = x3410 z = x3411 z = x3412 z = x3413 z = x3414 z = x3415 z = x3416 z = x3417 z = x3418 z = x3419 z = x3420 z = x3421 z = x3422 z = x3423 z = x3424 z = x3425 z = x3426 z = x3427 z = x3428 z = x3429 z = x3430 z = x3431 z = x3432 z = x3433 z = x3434 z = x3435 z = x3436 z = x3437 z = x3438 z = x3439 z = x3440 z = x3441 z = x3442 z = x3443 z = x3444 z = x3445 z = x3446 z = x3447 z = x3448 z = x3449 z = x3450 z = x3451 z = x3452 z = x3453 z = x3454 z = x3455 z = x3456 z = x3457 z = x3458 z = x3459 z = x3460 z = x3461 z = x3462 z = x3463 z = x3464 z = x3465 z = x3466 z = x3467 z = x3468 z = x3469 z = x3470 z = x3471 z = x3472 z = x3473 z = x3474 z = x3475 z = x3476 z = x3477 z = x3478 z = x3479 z = x3480 z = x3481 z = x3482 z = x3483 z = x3484 z = x3485 z = x3486 z = x3487 z = x3488 z = x3489 z = x3490 z = x3491 z = x3492 z = x3493 z = x3494 z = x3495 z = x3496 z = x3497 z = x3498 z = x3499 z = x3500 z = x3501 z = x3502 z = x3503 z = x3504 z = x3505 z = x3506 z = x3507 z = x3508 z = x3509 z = x3510 z = x3511 z = x3512 z = x3513 z = x3514 z = x3515 z = x3516 z = x3517 z = x3518 z = x3519 z = x3520 z = x3521 z = x3522 z = x3523 z = x3524 z = x3525 z = x3526 z = x3527 z = x3528 z = x3529 z = x3530 z = x3531 z = x3532 z = x3533 z = x3534 z = x3535 z = x3536 z = x3537 z = x3538 z = x3539 z = x3540 z = x3541 z = x3542 z = x3543 z = x3544 z = x3545 z = x3546 z = x3547 z = x3548 z = x3549 z = x3550 z = x3551 z = x3552 z = x3553 z = x3554 z = x3555 z = x3556 z = x3557 z = x3558 z = x3559 z = x3560 z = x3561 z = x3562 z = x3563 z = x3564 z = x3565 z = x3566 z = x3567 z = x3568 z = x3569 z = x3570 z = x3571 z = x3572 z = x3573 z = x3574 z = x3575 z = x3576 z = x3577 z = x3578 z = x3579 z = x3580 z = x3581 z = x3582 z = x3583 z = x3584 z = x3585 z = x3586 z = x3587 z = x3588 z = x3589 z = x3590 z = x3591 z = x3592 z = x3593 z = x3594 z = x3595 z = x3596 z = x3597 z = x3598 z = x3599 z = x3600 z = x3601 z = x3602 z = x3603 z = x3604 z = x3605 z = x3606 z = x3607 z = x3608 z = x3609 z = x3610 z = x3611 z = x3612 z = x3613 z = x3614 z = x3615 z = x3616 z = x3617 z = x3618 z = x3619 z = x3620 z = x3621 z = x3622 z = x3623 z = x3624 z = x3625 z = x3626 z = x3627 z = x3628 z = x3629 z = x3630 z = x3631 z = x3632 z = x3633 z = x3634 z = x3635 z = x3636 z = x3637 z = x3638 z = x3639 z = x3640 z = x3641 z = x3642 z = x3643 z = x3644 z = x3645 z = x3646 z = x3647 z = x3648 z = x3649 z = x3650 z = x3651 z = x3652 z = x3653 z = x3654 z = x3655 z = x3656 z = x3657 z = x3658 z = x3659 z = x3660 z = x3661 z = x3662 z = x3663 z = x3664 z = x3665 z = x3666 z = x3667 z = x3668 z = x3669 z = x3670 z = x3671 z = x3672 z = x3673 z = x3674 z = x3675 z = x3676 z = x3677 z = x3678 z = x3679 z = x3680 z = x3681 z = x3682 z = x3683 z = x3684 z = x3685 z = x3686 z = x3687 z = x3688 z = x3689 z = x3690 z = x3691 z = x3692 z = x3693 z = x3694 z = x3695 z = x3696 z = x3697 z = x3698 z = x3699 z = x3700 z = x3701 z = x3702 z = x3703 z = x3704 z = x3705 z = x3706 z = x3707 z = x3708 z = x3709 z = x3710 z = x3711 z = x3712 z = x3713 z = x3714 z = x3715 z = x3716 z = x3717 z = x3718 z = x3719 z = x3720 z = x3721 z = x3722 z = x3723 z = x3724 z = x3725 z = x3726 z = x3727 z = x3728 z = x3729 z = x3730 z = x3731 z = x3732 z = x3733 z = x3734 z = x3735 z = x3736 z = x3737 z = x3738 z = x3739 z = x3740 z = x3741 z = x3742 z = x3743 z = x3744 z = x3745 z = x3746 z = x3747 z = x3748 z = x3749 z = x3750 z = x3751 z = x3752 z = x3753 z = x3754 z = x3755 z = x3756 z = x3757 z = x3758 z = x3759 z = x3760 z = x3761 z = x3762 z = x3763 z = x3764 z = x3765 z = x3766 z = x3767 z = x3768 z = x3769 z = x3770 z = x3771 z = x3772 z = x3773 z = x3774 z = x3775 z = x3776 z = x3777 z = x3778 z = x3779 z = x3780 z = x3781 z = x3782 z = x3783 z = x3784 z = x3785 z = x3786 z = x3787 z = x3788 z = x3789 z = x3790 z = x3791 z = x3792 z = x3793 z = x3794 z = x3795 z = x3796 z = x3797 z = x3798 z = x3799 z = x3800 z = x3801 z = x3802 z = x3803 z = x3804 z = x3805 z = x3806 z = x3807 z = x3808 z = x3809 z = x3810 z = x3811 z = x3812 z = x3813 z = x3814 z = x3815 z = x3816 z = x3817 z = x3818 z = x3819 z = x3820 z = x3821 z = x3822 z = x3823 z = x3824 z = x3825 z = x3826 z = x3827 z = x3828 z = x3829 z = x3830 z = x3831 z = x3832 z = x3833 z = x3834 z = x3835 z = x3836 z = x3837 z = x3838 z = x3839 z = x3840 z = x3841 z = x3842 z = x3843 z = x3844 z = x3845 z = x3846 z = x3847 z = x3848 z = x3849 z = x3850 z = x3851 z = x3852 z = x3853 z = x3854 z = x3855 z = x3856 z = x3857 z = x3858 z = x3859 z = x3860 z = x3861 z = x3862 z = x3863 z = x3864 z = x3865 z = x3866 z = x3867 z = x3868 z = x3869 z = x3870 z = x3871 z = x3872 z = x3873 z = x3874 z = x3875 z = x3876 z = x3877 z = x3878 z = x3879 z = x3880 z = x3881 z = x3882 z = x3883 z = x3884 z = x3885 z = x3886 z = x3887 z = x3888 z = x3889 z = x3890 z = x3891 z = x3892 z = x3893 z = x3894 z = x3895 z = x3896 z = x3897 z = x3898 z = x3899 z = x3900 z = x3901 z = x3902 z = x3903 z = x3904 z = x3905 z = x3906 z = x3907 z = x3908 z = x3909 z = x3910 z = x3911 z = x3912 z = x3913 z = x3914 z = x3915 z = x3916 z = x3917 z = x3918 z = x3919 z = x3920 z = x3921 z = x3922 z = x3923 z = x3924 z = x3925 z = x3926 z = x3927 z = x3928 z = x3929 z = x3930 z = x3931 z = x3932 z = x3933 z = x3934 z = x3935 z = x3936 z = x3937 z = x3938 z = x3939 z = x3940 z = x3941 z = x3942 z = x3943 z = x3944 z = x3945 z = x3946 z = x3947 z = x3948 z = x3949 z = x3950 z = x3951 z = x3952 z = x3953 z = x3954 z = x3955 z = x3956 z = x3957 z = x3958 z = x3959 z = x3960 z = x3961 z = x3962 z = x3963 z = x3964 z = x3965 z = x3966 z = x3967 z = x3968 z = x3969 z = x3970 z = x3971 z = x3972 z = x3973 z = x3974 z = x3975 z = x3976 z = x3977 z = x3978 z = x3979 z = x3980 z = x3981 z = x3982 z = x3983 z = x3984 z = x3985 z = x3986 z = x3987 z = x3988 z = x3989 z = x3990 z = x3991 z = x3992 z = x3993 z = x3994 z = x3995 z = x3996 z = x3997 z = x3998 z = x3999 z = x4000 z = x4001 z = x4002 z = x4003 z = x4004 z = x4005 z = x4006 z = x4007 z = x4008 z = x4009 z = x4010 z = x4011 z = x4012 z = x4013 z = x4014 z = x4015 z = x4016 z = x4017 z = x4018 z = x4019 z = x4020 z = x4021 z = x4022 z = x4023 z = x4024 z = x4025 z = x4026 z = x4027 z = x4028 z = x4029 z = x4030 z = x4031 z = x4032 z = x4033 z = x4034 z = x4035 z = x4036 z = x4037 z = x4038 z = x4039 z = x4040 z = x4041 z = x4042 z = x4043 z = x4044 z = x4045 z = x4046 z = x4047 z = x4048 z = x4049 z = x4050 z = x4051 z = x4052 z = x4053 z = x4054 z = x4055 z = x4056 z = x4057 z = x4058 z = x4059 z = x4060 z = x4061 z = x4062 z = x4063 z = x4064 z = x4065 z = x4066 z = x4067 z = x4068 z = x4069 z = x4070 z = x4071 z = x4072 z = x4073 z = x4074 z = x4075 z = x4076 z = x4077 z = x4078 z = x4079 z = x4080 z = x4081 z = x4082 z = x4083 z = x4084 z = x4085 z = x4086 z = x4087 z = x4088 z = x4089 z = x4090 z = x4091 z = x4092 z = x4093 z = x4094 z = x4095 z = x4096 z = x4097 z = x4098 z = x4099 z = x4100 z = x4101 z = x4102 z = x4103 z = x4104 z = x4105 z = x4106 z = x4107 z = x4108 z = x4109 z = x4110 z = x4111 z = x4112 z = x4113 z = x4114 z = x4115 z = x4116 z = x4117 z = x4118 z = x4119 z = x4120 z = x4121 z = x4122 z = x4123 z = x4124 z = x4125 z = x4126 z = x4127 z = x4128 z = x4129 z = x4130 z = x4131 z = x4132 z = x4133 z = x4134 z = x4135 z = x4136 z = x4137 z = x4138 z = x4139 z = x4140 z = x4141 z = x4142 z = x4143 z = x4144 z = x4145 z = x4146 z = x4147 z = x4148 z = x4149 z = x4150 z = x4151 z = x4152 z = x4153 z = x4154 z = x4155 z = x4156 z = x4157 z = x4158 z = x4159 z = x4160 z = x4161 z = x4162 z = x4163 z = x4164 z = x4165 z = x4166 z = x4167 z = x4168 z = x4169 z = x4170 z = x4171 z = x4172 z = x4173 z = x4174 z = x4175 z = x4176 z = x4177 z = x4178 z = x4179 z = x4180 z = x4181 z = x4182 z = x4183 z = x4184 z = x4185 z = x4186 z = x4187 z = x4188 z = x4189 z = x4190 z = x4191 z = x4192 z = x4193 z = x4194 z = x4195 z = x4196 z = x4197 z = x4198 z = x4199 z = x4200 z = x4201 z = x4202 z = x4203 z = x4204 z = x4205 z = x4206 z = x4207 z = x4208 z = x4209 z = x4210 z = x4211 z = x4212 z = x4213 z = x4214 z = x4215 z = x4216 z = x4217 z = x4218 z = x4219 z = x4220 z = x4221 z = x4222 z = x4223 z = x4224 z = x4225 z = x4226 z = x4227 z = x4228 z = x4229 z = x4230 z = x4231 z = x4232 z = x4233 z = x4234 z = x4235 z = x4236 z = x4237 z = x4238 z = x4239 z = x4240 z = x4241 z = x4242 z = x4243 z = x4244 z = x4245 z = x4246 z = x4247 z = x4248 z = x4249 z = x4250 z = x4251 z = x4252 z = x4253 z = x4254 z = x4255 z = x4256 z = x4257 z = x4258 z = x4259 z = x4260 z = x4261 z = x4262 z = x4263 z = x4264 z = x4265 z = x4266 z = x4267 z = x4268 z = x4269 z = x4270 z = x4271 z = x4272 z = x4273 z = x4274 z = x4275 z = x4276 z = x4277 z = x4278 z = x4279 z = x4280 z = x4281 z = x4282 z = x4283 z = x4284 z = x4285 z = x4286 z = x4287 z = x4288 z = x4289 z = x4290 z = x4291 z = x4292 z = x4293 z = x4294 z = x4295 z = x4296 z = x4297 z = x4298 z = x4299 z = x4300 z = x4301 z = x4302 z = x4303 z = x4304 z = x4305 z = x4306 z = x4307 z = x4308 z = x4309 z = x4310 z = x4311 z = x4312 z = x4313 z = x4314 z = x4315 z = x4316 z = x4317 z = x4318 z = x4319 z = x4320 z = x4321 z = x4322 z = x4323 z = x4324 z = x4325 z = x4326 z = x4327 z = x4328 z = x4329 z = x4330 z = x4331 z = x4332 z = x4333 z = x4334 z = x4335 z = x4336 z = x4337 z = x4338 z = x4339 z = x4340 z = x4341 z = x4342 z = x4343 z = x4344 z = x4345 z = x4346 z = x4347 z = x4348 z = x4349 z = x4350 z = x4351 z = x4352 z = x4353 z = x4354 z = x4355 z = x4356 z = x4357 z = x4358 z = x4359 z = x4360 z = x4361 z = x4362 z = x4363 z = x4364 z = x4365 z = x4366 z = x4367 z = x4368 z = x4369 z = x4370 z = x4371 z = x4372 z = x4373 z = x4374 z = x4375 z = x4376 z = x4377 z = x4378 z = x4379 z = x4380 z = x4381 z = x4382 z = x4383 z = x4384 z = x4385 z = x4386 z = x4387 z = x4388 z = x4389 z = x4390 z = x4391 z = x4392 z = x4393 z = x4394 z = x4395 z = x4396 z = x4397 z = x4398 z = x4399 z = x4400 z = x4401 z = x4402 z = x4403 z = x4404 z = x4405 z = x4406 z = x4407 z = x4408 z = x4409 z = x4410 z = x4411 z = x4412 z = x4413 z = x4414 z = x4415 z = x4416 z = x4417 z = x4418 z = x4419 z = x4420 z = x4421 z = x4422 z = x4423 z = x4424 z = x4425 z = x4426 z = x4427 z = x4428 z = x4429 z = x4430 z = x4431 z = x4432 z = x4433 z = x4434 z = x4435 z = x4436 z = x4437 z = x4438 z = x4439 z = x4440 z = x4441 z = x4442 z = x4443 z = x4444 z = x4445 z = x4446 z = x4447 z = x4448 z = x4449 z = x4450 z = x4451 z = x4452 z = x4453 z = x4454 z = x4455 z = x4456 z = x4457 z = x4458 z = x4459 z = x4460 z = x4461 z = x4462 z = x4463 z = x4464 z = x4465 z = x4466 z = x4467 z = x4468 z = x4469 z = x4470 z = x4471 z = x4472 z = x4473 z = x4474 z = x4475 z = x4476 z = x4477 z = x4478 z = x4479 z = x4480 z = x4481 z = x4482 z = x4483 z = x4484 z = x4485 z = x4486 z = x4487 z = x4488 z = x4489 z = x4490 z = x4491 z = x4492 z = x4493 z = x4494 z = x4495 z = x4496 z = x4497 z = x4498 z = x4499 z = x4500 z = x4501 z = x4502 z = x4503 z = x4504 z = x4505 z = x4506 z = x4507 z = x4508 z = x4509 z = x4510 z = x4511 z = x4512 z = x4513 z = x4514 z = x4515 z = x4516 z = x4517 z = x4518 z = x4519 z = x4520 z = x4521 z = x4522 z = x4523 z = x4524 z = x4525 z = x4526 z = x4527 z = x4528 z = x4529 z = x4530 z = x4531 z = x4532 z = x4533 z = x4534 z = x4535 z = x4536 z = x4537 z = x4538 z = x4539 z = x4540 z = x4541 z = x4542 z = x4543 z = x4544 z = x4545 z = x4546 z = x4547 z = x4548 z = x4549 z = x4550 z = x4551 z = x4552 z = x4553 z = x4554 z = x4555 z = x4556 z = x4557 z = x4558 z = x4559 z = x4560 z = x4561 z = x4562 z = x4563 z = x4564 z = x4565 z = x4566 z = x4567 z = x4568 z = x4569 z = x4570 z = x4571 z = x4572 z = x4573 z = x4574 z = x4575 z = x4576 z = x4577 z = x4578 z = x4579 z = x4580 z = x4581 z = x4582 z = x4583 z = x4584 z = x4585 z = x4586 z = x4587 z = x4588 z = x4589 z = x4590 z = x4591 z = x4592 z = x4593 z = x4594 z = x4595 z = x4596 z = x4597 z = x4598 z = x4599 z = x4600 z = x4601 z = x4602 z = x4603 z = x4604 z = x4605 z = x4606 z = x4607 z = x4608 z = x4609 z = x4610 z = x4611 z = x4612 z = x4613 z = x4614 z = x4615 z = x4616 z = x4617 z = x4618 z = x4619 z = x4620 z = x4621 z = x4622 z = x4623 z = x4624 z = x4625 z = x4626 z = x4627 z = x4628 z = x4629 z = x4630 z = x4631 z = x4632 z = x4633 z = x4634 z = x4635 z = x4636 z = x4637 z = x4638 z = x4639 z = x4640 z = x4641 z = x4642 z = x4643 z = x4644 z = x4645 z = x4646 z = x4647 z = x4648 z = x4649 z = x4650 z = x4651 z = x4652 z = x4653 z = x4654 z = x4655 z = x4656 z = x4657 z = x4658 z = x4659 z = x4660 z = x4661 z = x4662 z = x4663 z = x4664 z = x4665 z = x4666 z = x4667 z = x4668 z = x4669 z = x4670 z = x4671 z = x4672 z = x4673 z = x4674 z = x4675 z = x4676 z = x4677 z = x4678 z = x4679 z = x4680 z = x4681 z = x4682 z = x4683 z = x4684 z = x4685 z = x4686 z = x4687 z = x4688 z = x4689 z = x4690 z = x4691 z = x4692 z = x4693 z = x4694 z = x4695 z = x4696 z = x4697 z = x4698 z = x4699 z = x4700 z = x4701 z = x4702 z = x4703 z = x4704 z = x4705 z = x4706 z = x4707 z = x4708 z = x4709 z = x4710 z = x4711 z = x4712 z = x4713 z = x4714 z = x4715 z = x4716 z = x4717 z = x4718 z = x4719 z = x4720 z = x4721 z = x4722 z = x4723 z = x4724 z = x4725 z = x4726 z = x4727 z = x4728 z = x4729 z = x4730 z = x4731 z = x4732 z = x4733 z = x4734 z = x4735 z = x4736 z = x4737 z = x4738 z = x4739 z = x4740 z = x4741 z = x4742 z = x4743 z = x4744 z = x4745 z = x4746 z = x4747 z = x4748 z = x4749 z = x4750 z = x4751 z = x4752 z = x4753 z = x4754 z = x4755 z = x4756 z = x4757 z = x4758 z = x4759 z = x4760 z = x4761 z = x4762 z = x4763 z = x4764 z = x4765 z = x4766 z = x4767 z = x4768 z = x4769 z = x4770 z = x4771 z = x4772 z = x4773 z = x4774 z = x4775 z = x4776 z = x4777 z = x4778 z = x4779 z = x4780 z = x4781 z = x4782 z = x4783 z = x4784 z = x4785 z = x4786 z = x4787 z = x4788 z = x4789 z = x4790 z = x4791 z = x4792 z = x4793 z = x4794 z = x4795 z = x4796 z = x4797 z = x4798 z = x4799 z = x4800 z = x4801 z = x4802 z = x4803 z = x4804 z = x4805 z = x4806 z = x4807 z = x4808 z = x4809 z = x4810 z = x4811 z = x4812 z = x4813 z = x4814 z = x4815 z = x4816 z = x4817 z = x4818 z = x4819 z = x4820 z = x4821 z = x4822 z = x4823 z = x4824 z = x4825 z = x4826 z = x4827 z = x4828 z = x4829 z = x4830 z = x4831 z = x4832 z = x4833 z = x4834 z = x4835 z = x4836 z = x4837 z = x4838 z = x4839 z = x4840 z = x4841 z = x4842 z = x4843 z = x4844 z = x4845 z = x4846 z = x4847 z = x4848 z = x4849 z = x4850 z = x4851 z = x4852 z = x4853 z = x4854 z = x4855 z = x4856 z = x4857 z = x4858 z = x4859 z = x4860 z = x4861 z = x4862 z = x4863 z = x4864 z = x4865 z = x4866 z = x4867 z = x4868 z = x4869 z = x4870 z = x4871 z = x4872 z = x4873 z = x4874 z = x4875 z = x4876 z = x4877 z = x4878 z = x4879 z = x4880 z = x4881 z = x4882 z = x4883 z = x4884 z = x4885 z = x4886 z = x4887 z = x4888 z = x4889 z = x4890 z = x4891 z = x4892 z = x4893 z = x4894 z = x4895 z = x4896 z = x4897 z = x4898 z = x4899 z = x4900 z = x4901 z = x4902 z = x4903 z = x4904 z = x4905 z = x4906 z = x4907 z = x4908 z = x4909 z = x4910 z = x4911 z = x4912 z = x4913 z = x4914 z = x4915 z = x4916 z = x4917 z = x4918 z = x4919 z = x4920 z = x4921 z = x4922 z = x4923 z = x4924 z = x4925 z = x4926 z = x4927 z = x4928 z = x4929 z = x4930 z = x4931 z = x4932 z = x4933 z = x4934 z = x4935 z = x4936 z = x4937 z = x4938 z = x4939 z = x4940 z = x4941 z = x4942 z = x4943 z = x4944 z = x4945 z = x4946 z = x4947 z = x4948 z = x4949 z = x4950 z = x4951 z = x4952 z = x4953 z = x4954 z = x4955 z = x4956 z = x4957 z = x4958 z = x4959 z = x4960 z = x4961 z = x4962 z = x4963 z = x4964 z = x4965 z = x4966 z = x4967 z = x4968 z = x4969 z = x4970 z = x4971 z = x4972 z = x4973 z = x4974 z = x4975 z = x4976 z = x4977 z = x4978 z = x4979 z = x4980 z = x4981 z = x4982 z = x4983 z = x4984 z = x4985 z = x4986 z = x4987 z = x4988 z = x4989 z = x4990 z = x4991 z = x4992 z = x4993 z = x4994 z = x4995 z = x4996 z = x4997 z = x4998 z = x4999 z = x5000 z = x5001 z = x5002 z = x5003 z = x5004 z = x5005 z = x5006 z = x5007 z = x5008 z = x5009 z = x5010 z = x5011 z = x5012 z = x5013 z = x5014 z = x5015 z = x5016 z = x5017 z = x5018 z = x5019 z = x5020 z = x5021 z = x5022 z = x5023 z = x5024 z = x5025 z = x5026 z = x5027 z = x5028 z = x5029 z = x5030 z = x5031 z = x5032 z = x5033 z = x5034 z = x5035 z = x5036 z = x5037 z = x5038 z = x5039 z = x5040 z = x5041 z = x5042 z = x5043 z = x5044 z = x5045 z = x5046 z = x5047 z = x5048 z = x5049 z = x5050 z = x5051 z = x5052 z = x5053 z = x5054 z = x5055 z = x5056 z = x5057 z = x5058 z = x5059 z = x5060 z = x5061 z = x5062 z = x5063 z = x5064 z = x5065 z = x5066 z = x5067 z = x5068 z = x5069 z = x5070 z = x5071 z = x5072 z = x5073 z = x5074 z = x5075 z = x5076 z = x5077 z = x5078 z = x5079 z = x5080 z = x5081 z = x5082 z = x5083 z = x5084 z = x5085 z = x5086 z = x5087 z = x5088 z = x5089 z = x5090 z = x5091 z = x5092 z = x5093 z = x5094 z = x5095 z = x5096 z = x5097 z = x5098 z = x5099 z = x5100 z = x5101 z = x5102 z = x5103 z = x5104 z = x5105 z = x5106 z = x5107 z = x5108 z = x5109 z = x5110 z = x5111 z = x5112 z = x5113 z = x5114 z = x5115 z = x5116 z = x5117 z = x5118 z = x5119 z = x5120 z = x5121 z = x5122 z = x5123 z = x5124 z = x5125 z = x5126 z = x5127 z = x5128 z = x5129 z = x5130 z = x5131 z = x5132 z = x5133 z = x5134 z = x5135 z = x5136 z = x5137 z = x5138 z = x5139 z = x5140 z = x5141 z = x5142 z = x5143 z = x5144 z = x5145 z = x5146 z = x5147 z = x5148 z = x5149 z = x5150 z = x5151 z = x5152 z = x5153 z = x5154 z = x5155 z = x5156 z = x5157 z = x5158 z = x5159 z = x5160 z = x5161 z = x5162 z = x5163 z = x5164 z = x5165 z = x5166 z = x5167 z = x5168 z = x5169 z = x5170 z = x5171 z = x5172 z = x5173 z = x5174 z = x5175 z = x5176 z = x5177 z = x5178 z = x5179 z = x5180 z = x5181 z = x5182 z = x5183 z = x5184 z = x5185 z = x5186 z = x5187 z = x5188 z = x5189 z = x5190 z = x5191 z = x5192 z = x5193 z = x5194 z = x5195 z = x5196 z = x5197 z = x5198 z = x5199 z = x5200 z = x5201 z = x5202 z = x5203 z = x5204 z = x5205 z = x5206 z = x5207 z = x5208 z = x5209 z = x5210 z = x5211 z = x5212 z = x5213 z = x5214 z = x5215 z = x5216 z = x5217 z = x5218 z = x5219 z = x5220 z = x5221 z = x5222 z = x5223 z = x5224 z = x5225 z = x5226 z = x5227 z = x5228 z = x5229 z = x5230 z = x5231 z = x5232 z = x5233 z = x5234 z = x5235 z = x5236 z = x5237 z = x5238 z = x5239 z = x5240 z = x5241 z = x5242 z = x5243 z = x5244 z = x5245 z = x5246 z = x5247 z = x5248 z = x5249 z = x5250 z = x5251 z = x5252 z = x5253 z = x5254 z = x5255 z = x5256 z = x5257 z = x5258 z = x5259 z = x5260 z = x5261 z = x5262 z = x5263 z = x5264 z = x5265 z = x5266 z = x5267 z = x5268 z = x5269 z = x5270 z = x5271 z = x5272 z = x5273 z = x5274 z = x5275 z = x5276 z = x5277 z = x5278 z = x5279 z = x5280 z = x5281 z = x5282 z = x5283 z = x5284 z = x5285 z = x5286 z = x5287 z = x5288 z = x5289 z = x5290 z = x5291 z = x5292 z = x5293 z = x5294 z = x5295 z = x5296 z = x5297 z = x5298 z = x5299 z = x5300 z = x5301 z = x5302 z = x5303 z = x5304 z = x5305 z = x5306 z = x5307 z = x5308 z = x5309 z = x5310 z = x5311 z = x5312 z = x5313 z = x5314 z = x5315 z = x5316 z = x5317 z = x5318 z = x5319 z = x5320 z = x5321 z = x5322 z = x5323 z = x5324 z = x5325 z = x5326 z = x5327 z = x5328 z = x5329 z = x5330 z = x5331 z = x5332 z = x5333 z = x5334 z = x5335 z = x5336 z = x5337 z = x5338 z = x5339 z = x5340 z = x5341 z = x5342 z = x5343 z = x5344 z = x5345 z = x5346 z = x5347 z = x5348 z = x5349 z = x5350 z = x5351 z = x5352 z = x5353 z = x5354 z = x5355 z = x5356 z = x5357 z = x5358 z = x5359 z = x5360 z = x5361 z = x5362 z = x5363 z = x5364 z = x5365 z = x5366 z = x5367 z = x5368 z = x5369 z = x5370 z = x5371 z = x5372 z = x5373 z = x5374 z = x5375 z = x5376 z = x5377 z = x5378 z = x5379 z = x5380 z = x5381 z = x5382 z = x5383 z = x5384 z = x5385 z = x5386 z = x5387 z = x5388 z = x5389 z = x5390 z = x5391 z = x5392 z = x5393 z = x5394 z = x5395 z = x5396 z = x5397 z = x5398 z = x5399 z = x5400 z = x5401 z = x5402 z = x5403 z = x5404 z = x5405 z = x5406 z = x5407 z = x5408 z = x5409 z = x5410 z = x5411 z = x5412 z = x5413 z = x5414 z = x5415 z = x5416 z = x5417 z = x5418 z = x5419 z = x5420 z = x5421 z = x5422 z = x5423 z = x5424 z = x5425 z = x5426 z = x5427 z = x5428 z = x5429 z = x5430 z = x5431 z = x5432 z = x5433 z = x5434 z = x5435 z = x5436 z = x5437 z = x5438 z = x5439 z = x5440 z = x5441 z = x5442 z = x5443 z = x5444 z = x5445 z = x5446 z = x5447 z = x5448 z = x5449 z = x5450 z = x5451 z = x5452 z = x5453 z = x5454 z = x5455 z = x5456 z = x5457 z = x5458 z = x5459 z = x5460 z = x5461 z = x5462 z = x5463 z = x5464 z = x5465 z = x5466 z = x5467 z = x5468 z = x5469 z = x5470 z = x5471 z = x5472 z = x5473 z = x5474 z = x5475 z = x5476 z = x5477 z = x5478 z = x5479 z = x5480 z = x5481 z = x5482 z = x5483 z = x5484 z = x5485 z = x5486 z = x5487 z = x5488 z = x5489 z = x5490 z = x5491 z = x5492 z = x5493 z = x5494 z = x5495 z = x5496 z = x5497 z = x5498 z = x5499 z = x5500 z = x5501 z = x5502 z = x5503 z = x5504 z = x5505 z = x5506 z = x5507 z = x5508 z = x5509 z = x5510 z = x5511 z = x5512 z = x5513 z = x5514 z = x5515 z = x5516 z = x5517 z = x5518 z = x5519 z = x5520 z = x5521 z = x5522 z = x5523 z = x5524 z = x5525 z = x5526 z = x5527 z = x5528 z = x5529 z = x5530 z = x5531 z = x5532 z = x5533 z = x5534 z = x5535 z = x5536 z = x5537 z = x5538 z = x5539 z = x5540 z = x5541 z = x5542 z = x5543 z = x5544 z = x5545 z = x5546 z = x5547 z = x5548 z = x5549 z = x5550 z = x5551 z = x5552 z = x5553 z = x5554 z = x5555 z = x5556 z = x5557 z = x5558 z = x5559 z = x5560 z = x5561 z = x5562 z = x5563 z = x5564 z = x5565 z = x5566 z = x5567 z = x5568 z = x5569 z = x5570 z = x5571 z = x5572 z = x5573 z = x5574 z = x5575 z = x5576 z = x5577 z = x5578 z = x5579 z = x5580 z = x5581 z = x5582 z = x5583 z = x5584 z = x5585 z = x5586 z = x5587 z = x5588 z = x5589 z = x5590 z = x5591 z = x5592 z = x5593 z = x5594 z = x5595 z = x5596 z = x5597 z = x5598 z = x5599 z = x5600 z = x5601 z = x5602 z = x5603 z = x5604 z = x5605 z = x5606 z = x5607 z = x5608 z = x5609 z = x5610 z = x5611 z = x5612 z = x5613 z = x5614 z = x5615 z = x5616 z = x5617 z = x5618 z = x5619 z = x5620 z = x5621 z = x5622 z = x5623 z = x5624 z = x5625 z = x5626 z = x5627 z = x5628 z = x5629 z = x5630 z = x5631 z = x5632 z = x5633 z = x5634 z = x5635 z = x5636 z = x5637 z = x5638 z = x5639 z = x5640 z = x5641 z = x5642 z = x5643 z = x5644 z = x5645 z = x5646 z = x5647 z = x5648 z = x5649 z = x5650 z = x5651 z = x5652 z = x5653 z = x5654 z = x5655 z = x5656 z = x5657 z = x5658 z = x5659 z = x5660 z = x5661 z = x5662 z = x5663 z = x5664 z = x5665 z = x5666 z = x5667 z = x5668 z = x5669 z = x5670 z = x5671 z = x5672 z = x5673 z = x5674 z = x5675 z = x5676 z = x5677 z = x5678 z = x5679 z = x5680 z = x5681 z = x5682 z = x5683 z = x5684 z = x5685 z = x5686 z = x5687 z = x5688 z = x5689 z = x5690 z = x5691 z = x5692 z = x5693 z = x5694 z = x5695 z = x5696 z = x5697 z = x5698 z = x5699 z = x5700 z = x5701 z = x5702 z = x5703 z = x5704 z = x5705 z = x5706 z = x5707 z = x5708 z = x5709 z = x5710 z = x5711 z = x5712 z = x5713 z = x5714 z = x5715 z = x5716 z = x5717 z = x5718 z = x5719 z = x5720 z = x5721 z = x5722 z = x5723 z = x5724 z = x5725 z = x5726 z = x5727 z = x5728 z = x5729 z = x5730 z = x5731 z = x5732 z = x5733 z = x5734 z = x5735 z = x5736 z = x5737 z = x5738 z = x5739 z = x5740 z = x5741 z = x5742 z = x5743 z = x5744 z = x5745 z = x5746 z = x5747 z = x5748 z = x5749 z = x5750 z = x5751 z = x5752 z = x5753 z = x5754 z = x5755 z = x5756 z = x5757 z = x5758 z = x5759 z = x5760 z = x5761 z = x5762 z = x5763 z = x5764 z = x5765 z = x5766 z = x5767 z = x5768 z = x5769 z = x5770 z = x5771 z = x5772 z = x5773 z = x5774 z = x5775 z = x5776 z = x5777 z = x5778 z = x5779 z = x5780 z = x5781 z = x5782 z = x5783 z = x5784 z = x5785 z = x5786 z = x5787 z = x5788 z = x5789 z = x5790 z = x5791 z = x5792 z = x5793 z = x5794 z = x5795 z = x5796 z = x5797 z = x5798 z = x5799 z = x5800 z = x5801 z = x5802 z = x5803 z = x5804 z = x5805 z = x5806 z = x5807 z = x5808 z = x5809 z = x5810 z = x5811 z = x5812 z = x5813 z = x5814 z = x5815 z = x5816 z = x5817 z = x5818 z = x5819 z = x5820 z = x5821 z = x5822 z = x5823 z = x5824 z = x5825 z = x5826 z = x5827 z = x5828 z = x5829 z = x5830 z = x5831 z = x5832 z = x5833 z = x5834 z = x5835 z = x5836 z = x5837 z = x5838 z = x5839 z = x5840 z = x5841 z = x5842 z = x5843 z = x5844 z = x5845 z = x5846 z = x5847 z = x5848 z = x5849 z = x5850 z = x5851 z = x5852 z = x5853 z = x5854 z = x5855 z = x5856 z = x5857 z = x5858 z = x5859 z = x5860 z = x5861 z = x5862 z = x5863 z = x5864 z = x5865 z = x5866 z = x5867 z = x5868 z = x5869 z = x5870 z = x5871 z = x5872 z = x5873 z = x5874 z = x5875 z = x5876 z = x5877 z = x5878 z = x5879 z = x5880 z = x5881 z = x5882 z = x5883 z = x5884 z = x5885 z = x5886 z = x5887 z = x5888 z = x5889 z = x5890 z = x5891 z = x5892 z = x5893 z = x5894 z = x5895 z = x5896 z = x5897 z = x5898 z = x5899 z = x5900 z = x5901 z = x5902 z = x5903 z = x5904 z = x5905 z = x5906 z = x5907 z = x5908 z = x5909 z = x5910 z = x5911 z = x5912 z = x5913 z = x5914 z = x5915 z = x5916 z = x5917 z = x5918 z = x5919 z = x5920 z = x5921 z = x5922 z = x5923 z = x5924 z = x5925 z = x5926 z = x5927 z = x5928 z = x5929 z = x5930 z = x5931 z = x5932 z = x5933 z = x5934 z = x5935 z = x5936 z = x5937 z = x5938 z = x5939 z = x5940 z = x5941 z = x5942 z = x5943 z = x5944 z = x5945 z = x5946 z = x5947 z = x5948 z = x5949 z = x5950 z = x5951 z = x5952 z = x5953 z = x5954 z = x5955 z = x5956 z = x5957 z = x5958 z = x5959 z = x5960 z = x5961 z = x5962 z = x5963 z = x5964 z = x5965 z = x5966 z = x5967 z = x5968 z = x5969 z = x5970 z = x5971 z = x5972 z = x5973 z = x5974 z = x5975 z = x5976 z = x5977 z = x5978 z = x5979 z = x5980 z = x5981 z = x5982 z = x5983 z = x5984 z = x5985 z = x5986 z = x5987 z = x5988 z = x5989 z = x5990 z = x5991 z = x5992 z = x5993 z = x5994 z = x5995 z = x5996 z = x5997 z = x5998 z = x5999 z = x6000 z = x6001 z = x6002 z = x6003 z = x6004 z = x6005 z = x6006 z = x6007 z = x6008 z = x6009 z = x6010 z = x6011 z = x6012 z = x6013 z = x6014 z = x6015 z = x6016 z = x6017 z = x6018 z = x6019 z = x6020 z = x6021 z = x6022 z = x6023 z = x6024 z = x6025 z = x6026 z = x6027 z = x6028 z = x6029 z = x6030 z = x6031 z = x6032 z = x6033 z = x6034 z = x6035 z = x6036 z = x6037 z = x6038 z = x6039 z = x6040 z = x6041 z = x6042 z = x6043 z = x6044 z = x6045 z = x6046 z = x6047 z = x6048 z = x6049 z = x6050 z = x6051 z = x6052 z = x6053 z = x6054 z = x6055 z = x6056 z = x6057 z = x6058 z = x6059 z = x6060 z = x6061 z = x6062 z = x6063 z = x6064 z = x6065 z = x6066 z = x6067 z = x6068 z = x6069 z = x6070 z = x6071 z = x6072 z = x6073 z = x6074 z = x6075 z = x6076 z = x6077 z = x6078 z = x6079 z = x6080 z = x6081 z = x6082 z = x6083 z = x6084 z = x6085 z = x6086 z = x6087 z = x6088 z = x6089 z = x6090 z = x6091 z = x6092 z = x6093 z = x6094 z = x6095 z = x6096 z = x6097 z = x6098 z = x6099 z = x6100 z = x6101 z = x6102 z = x6103 z = x6104 z = x6105 z = x6106 z = x6107 z = x6108 z = x6109 z = x6110 z = x6111 z = x6112 z = x6113 z = x6114 z = x6115 z = x6116 z = x6117 z = x6118 z = x6119 z = x6120 z = x6121 z = x6122 z = x6123 z = x6124 z = x6125 z = x6126 z = x6127 z = x6128 z = x6129 z = x6130 z = x6131 z = x6132 z = x6133 z = x6134 z = x6135 z = x6136 z = x6137 z = x6138 z = x6139 z = x6140 z = x6141 z = x6142 z = x6143 z = x6144 z = x6145 z = x6146 z = x6147 z = x6148 z = x6149 z = x6150 z = x6151 z = x6152 z = x6153 z = x6154 z = x6155 z = x6156 z = x6157 z = x6158 z = x6159 z = x6160 z = x6161 z = x6162 z = x6163 z = x6164 z = x6165 z = x6166 z = x6167 z = x6168 z = x6169 z = x6170 z = x6171 z = x6172 z = x6173 z = x6174 z = x6175 z = x6176 z = x6177 z = x6178 z = x6179 z = x6180 z = x6181 z = x6182 z = x6183 z = x6184 z = x6185 z = x6186 z = x6187 z = x6188 z = x6189 z = x6190 z = x6191 z = x6192 z = x6193 z = x6194 z = x6195 z = x6196 z = x6197 z = x6198 z = x6199 z = x6200 z = x6201 z = x6202 z = x6203 z = x6204 z = x6205 z = x6206 z = x6207 z = x6208 z = x6209 z = x6210 z = x6211 z = x6212 z = x6213 z = x6214 z = x6215 z = x6216 z = x6217 z = x6218 z = x6219 z = x6220 z = x6221 z = x6222 z = x6223 z = x6224 z = x6225 z = x6226 z = x6227 z = x6228 z = x6229 z = x6230 z = x6231 z = x6232 z = x6233 z = x6234 z = x6235 z = x6236 z = x6237 z = x6238 z = x6239 z = x6240 z = x6241 z = x6242 z = x6243 z = x6244 z = x6245 z = x6246 z = x6247 z = x6248 z = x6249 z = x6250 z = x6251 z = x6252 z = x6253 z = x6254 z = x6255 z = x6256 z = x6257 z = x6258 z = x6259 z = x6260 z = x6261 z = x6262 z = x6263 z = x6264 z = x6265 z = x6266 z = x6267 z = x6268 z = x6269 z = x6270 z = x6271 z = x6272 z = x6273 z = x6274 z = x6275 z = x6276 z = x6277 z = x6278 z = x6279 z = x6280 z = x6281 z = x6282 z = x6283 z = x6284 z = x6285 z = x6286 z = x6287 z = x6288 z = x6289 z = x6290 z = x6291 z = x6292 z = x6293 z = x6294 z = x6295 z = x6296 z = x6297 z = x6298 z = x6299 z = x6300 z = x6301 z = x6302 z = x6303 z = x6304 z = x6305 z = x6306 z = x6307 z = x6308 z = x6309 z = x6310 z = x6311 z = x6312 z = x6313 z = x6314 z = x6315 z = x6316 z = x6317 z = x6318 z = x6319 z = x6320 z = x6321 z = x6322 z = x6323 z = x6324 z = x6325 z = x6326 z = x6327 z = x6328 z = x6329 z = x6330 z = x6331 z = x6332 z = x6333 z = x6334 z = x6335 z = x6336 z = x6337 z = x6338 z = x6339 z = x6340 z = x6341 z = x6342 z = x6343 z = x6344 z = x6345 z = x6346 z = x6347 z = x6348 z = x6349 z = x6350 z = x6351 z = x6352 z = x6353 z = x6354 z = x6355 z = x6356 z = x6357 z = x6358 z = x6359 z = x6360 z = x6361 z = x6362 z = x6363 z = x6364 z = x6365 z = x6366 z = x6367 z = x6368 z = x6369 z = x6370 z = x6371 z = x6372 z = x6373 z = x6374 z = x6375 z = x6376 z = x6377 z = x6378 z = x6379 z = x6380 z = x6381 z = x6382 z = x6383 z = x6384 z = x6385 z = x6386 z = x6387 z = x6388 z = x6389 z = x6390 z = x6391 z = x6392 z = x6393 z = x6394 z = x6395 z = x6396 z = x6397 z = x6398 z = x6399 z = x6400 z = x6401 z = x6402 z = x6403 z = x6404 z = x6405 z = x6406 z = x6407 z = x6408 z = x6409 z = x6410 z = x6411 z = x6412 z = x6413 z = x6414 z = x6415 z = x6416 z = x6417 z = x6418 z = x6419 z = x6420 z = x6421 z = x6422 z = x6423 z = x6424 z = x6425 z = x6426 z = x6427 z = x6428 z = x6429 z = x6430 z = x6431 z = x6432 z = x6433 z = x6434 z = x6435 z = x6436 z = x6437 z = x6438 z = x6439 z = x6440 z = x6441 z = x6442 z = x6443 z = x6444 z = x6445 z = x6446 z = x6447 z = x6448 z = x6449 z = x6450 z = x6451 z = x6452 z = x6453 z = x6454 z = x6455 z = x6456 z = x6457 z = x6458 z = x6459 z = x6460 z = x6461 z = x6462 z = x6463 z = x6464 z = x6465 z = x6466 z = x6467 z = x6468 z = x6469 z = x6470 z = x6471 z = x6472 z = x6473 z = x6474 z = x6475 z = x6476 z = x6477 z = x6478 z = x6479 z = x6480 z = x6481 z = x6482 z = x6483 z = x6484 z = x6485 z = x6486 z = x6487 z = x6488 z = x6489 z = x6490 z = x6491 z = x6492 z = x6493 z = x6494 z = x6495 z = x6496 z = x6497 z = x6498 z = x6499 z = x6500 z = x6501 z = x6502 z = x6503 z = x6504 z = x6505 z = x6506 z = x6507 z = x6508 z = x6509 z = x6510 z = x6511 z = x6512 z = x6513 z = x6514 z = x6515 z = x6516 z = x6517 z = x6518 z = x6519 z = x6520 z = x6521 z = x6522 z = x6523 z = x6524 z = x6525 z = x6526 z = x6527 z = x6528 z = x6529 z = x6530 z = x6531 z = x6532 z = x6533 z = x6534 z = x6535 z = x6536 z = x6537 z = x6538 z = x6539 z = x6540 z = x6541 z = x6542 z = x6543 z = x6544 z = x6545 z = x6546 z = x6547 z = x6548 z = x6549 z = x6550 z = x6551 z = x6552 z = x6553 z = x6554 z = x6555 z = x6556 z = x6557 z = x6558 z = x6559 z = x6560 z = x6561 z = x6562 z = x6563 z = x6564 z = x6565 z = x6566 z = x6567 z = x6568 z = x6569 z = x6570 z = x6571 z = x6572 z = x6573 z = x6574 z = x6575 z = x6576 z = x6577 z = x6578 z = x6579 z = x6580 z = x6581 z = x6582 z = x6583 z = x6584 z = x6585 z = x6586 z = x6587 z = x6588 z = x6589 z = x6590 z = x6591 z = x6592 z = x6593 z = x6594 z = x6595 z = x6596 z = x6597 z = x6598 z = x6599 z = x6600 z = x6601 z = x6602 z = x6603 z = x6604 z = x6605 z = x6606 z = x6607 z = x6608 z = x6609 z = x6610 z = x6611 z = x6612 z = x6613 z = x6614 z = x6615 z = x6616 z = x6617 z = x6618 z = x6619 z = x6620 z = x6621 z = x6622 z = x6623 z = x6624 z = x6625 z = x6626 z = x6627 z = x6628 z = x6629 z = x6630 z = x6631 z = x6632 z = x6633 z = x6634 z = x6635 z = x6636 z = x6637 z = x6638 z = x6639 z = x6640 z = x6641 z = x6642 z = x6643 z = x6644 z = x6645 z = x6646 z = x6647 z = x6648 z = x6649 z = x6650 z = x6651 z = x6652 z = x6653 z = x6654 z = x6655 z = x6656 z = x6657 z = x6658 z = x6659 z = x6660 z = x6661 z = x6662 z = x6663 z = x6664 z = x6665 z = x6666 z = x6667 z = x6668 z = x6669 z = x6670 z = x6671 z = x6672 z = x6673 z = x6674 z = x6675 z = x6676 z = x6677 z = x6678 z = x6679 z = x6680 z = x6681 z = x6682 z = x6683 z = x6684 z = x6685 z = x6686 z = x6687 z = x6688 z = x6689 z = x6690 z = x6691 z = x6692 z = x6693 z = x6694 z = x6695 z = x6696 z = x6697 z = x6698 z = x6699 z = x6700 z = x6701 z = x6702 z = x6703 z = x6704 z = x6705 z = x6706 z = x6707 z = x6708 z = x6709 z = x6710 z = x6711 z = x6712 z = x6713 z = x6714 z = x6715 z = x6716 z = x6717 z = x6718 z = x6719 z = x6720 z = x6721 z = x6722 z = x6723 z = x6724 z = x6725 z = x6726 z = x6727 z = x6728 z = x6729 z = x6730 z = x6731 z = x6732 z = x6733 z = x6734 z = x6735 z = x6736 z = x6737 z = x6738 z = x6739 z = x6740 z = x6741 z = x6742 z = x6743 z = x6744 z = x6745 z = x6746 z = x6747 z = x6748 z = x6749 z = x6750 z = x6751 z = x6752 z = x6753 z = x6754 z = x6755 z = x6756 z = x6757 z = x6758 z = x6759 z = x6760 z = x6761 z = x6762 z = x6763 z = x6764 z = x6765 z = x6766 z = x6767 z = x6768 z = x6769 z = x6770 z = x6771 z = x6772 z = x6773 z = x6774 z = x6775 z = x6776 z = x6777 z = x6778 z = x6779 z = x6780 z = x6781 z = x6782 z = x6783 z = x6784 z = x6785 z = x6786 z = x6787 z = x6788 z = x6789 z = x6790 z = x6791 z = x6792 z = x6793 z = x6794 z = x6795 z = x6796 z = x6797 z = x6798 z = x6799 z = x6800 z = x6801 z = x6802 z = x6803 z = x6804 z = x6805 z = x6806 z = x6807 z = x6808 z = x6809 z = x6810 z = x6811 z = x6812 z = x6813 z = x6814 z = x6815 z = x6816 z = x6817 z = x6818 z = x6819 z = x6820 z = x6821 z = x6822 z = x6823 z = x6824 z = x6825 z = x6826 z = x6827 z = x6828 z = x6829 z = x6830 z = x6831 z = x6832 z = x6833 z = x6834 z = x6835 z = x6836 z = x6837 z = x6838 z = x6839 z = x6840 z = x6841 z = x6842 z = x6843 z = x6844 z = x6845 z = x6846 z = x6847 z = x6848 z = x6849 z = x6850 z = x6851 z = x6852 z = x6853 z = x6854 z = x6855 z = x6856 z = x6857 z = x6858 z = x6859 z = x6860 z = x6861 z = x6862 z = x6863 z = x6864 z = x6865 z = x6866 z = x6867 z = x6868 z = x6869 z = x6870 z = x6871 z = x6872 z = x6873 z = x6874 z = x6875 z = x6876 z = x6877 z = x6878 z = x6879 z = x6880 z = x6881 z = x6882 z = x6883 z = x6884 z = x6885 z = x6886 z = x6887 z = x6888 z = x6889 z = x6890 z = x6891 z = x6892 z = x6893 z = x6894 z = x6895 z = x6896 z = x6897 z = x6898 z = x6899 z = x6900 z = x6901 z = x6902 z = x6903 z = x6904 z = x6905 z = x6906 z = x6907 z = x6908 z = x6909 z = x6910 z = x6911 z = x6912 z = x6913 z = x6914 z = x6915 z = x6916 z = x6917 z = x6918 z = x6919 z = x6920 z = x6921 z = x6922 z = x6923 z = x6924 z = x6925 z = x6926 z = x6927 z = x6928 z = x6929 z = x6930 z = x6931 z = x6932 z = x6933 z = x6934 z = x6935 z = x6936 z = x6937 z = x6938 z = x6939 z = x6940 z = x6941 z = x6942 z = x6943 z = x6944 z = x6945 z = x6946 z = x6947 z = x6948 z = x6949 z = x6950 z = x6951 z = x6952 z = x6953 z = x6954 z = x6955 z = x6956 z = x6957 z = x6958 z = x6959 z = x6960 z = x6961 z = x6962 z = x6963 z = x6964 z = x6965 z = x6966 z = x6967 z = x6968 z = x6969 z = x6970 z = x6971 z = x6972 z = x6973 z = x6974 z = x6975 z = x6976 z = x6977 z = x6978 z = x6979 z = x6980 z = x6981 z = x6982 z = x6983 z = x6984 z = x6985 z = x6986 z = x6987 z = x6988 z = x6989 z = x6990 z = x6991 z = x6992 z = x6993 z = x6994 z = x6995 z = x6996 z = x6997 z = x6998 z = x6999 z = x7000 z = x7001 z = x7002 z = x7003 z = x7004 z = x7005 z = x7006 z = x7007 z = x7008 z = x7009 z = x7010 z = x7011 z = x7012 z = x7013 z = x7014 z = x7015 z = x7016 z = x7017 z = x7018 z = x7019 z = x7020 z = x7021 z = x7022 z = x7023 z = x7024 z = x7025 z = x7026 z = x7027 z = x7028 z = x7029 z = x7030 z = x7031 z = x7032 z = x7033 z = x7034 z = x7035 z = x7036 z = x7037 z = x7038 z = x7039 z = x7040 z = x7041 z = x7042 z = x7043 z = x7044 z = x7045 z = x7046 z = x7047 z = x7048 z = x7049 z = x7050 z = x7051 z = x7052 z = x7053 z = x7054 z = x7055 z = x7056 z = x7057 z = x7058 z = x7059 z = x7060 z = x7061 z = x7062 z = x7063 z = x7064 z = x7065 z = x7066 z = x7067 z = x7068 z = x7069 z = x7070 z = x7071 z = x7072 z = x7073 z = x7074 z = x7075 z = x7076 z = x7077 z = x7078 z = x7079 z = x7080 z = x7081 z = x7082 z = x7083 z = x7084 z = x7085 z = x7086 z = x7087 z = x7088 z = x7089 z = x7090 z = x7091 z = x7092 z = x7093 z = x7094 z = x7095 z = x7096 z = x7097 z = x7098 z = x7099 z = x7100 z = x7101 z = x7102 z = x7103 z = x7104 z = x7105 z = x7106 z = x7107 z = x7108 z = x7109 z = x7110 z = x7111 z = x7112 z = x7113 z = x7114 z = x7115 z = x7116 z = x7117 z = x7118 z = x7119 z = x7120 z = x7121 z = x7122 z = x7123 z = x7124 z = x7125 z = x7126 z = x7127 z = x7128 z = x7129 z = x7130 z = x7131 z = x7132 z = x7133 z = x7134 z = x7135 z = x7136 z = x7137 z = x7138 z = x7139 z = x7140 z = x7141 z = x7142 z = x7143 z = x7144 z = x7145 z = x7146 z = x7147 z = x7148 z = x7149 z = x7150 z = x7151 z = x7152 z = x7153 z = x7154 z = x7155 z = x7156 z = x7157 z = x7158 z = x7159 z = x7160 z = x7161 z = x7162 z = x7163 z = x7164 z = x7165 z = x7166 z = x7167 z = x7168 z = x7169 z = x7170 z = x7171 z = x7172 z = x7173 z = x7174 z = x7175 z = x7176 z = x7177 z = x7178 z = x7179 z = x7180 z = x7181 z = x7182 z = x7183 z = x7184 z = x7185 z = x7186 z = x7187 z = x7188 z = x7189 z = x7190 z = x7191 z = x7192 z = x7193 z = x7194 z = x7195 z = x7196 z = x7197 z = x7198 z = x7199 z = x7200 z = x7201 z = x7202 z = x7203 z = x7204 z = x7205 z = x7206 z = x7207 z = x7208 z = x7209 z = x7210 z = x7211 z = x7212 z = x7213 z = x7214 z = x7215 z = x7216 z = x7217 z = x7218 z = x7219 z = x7220 z = x7221 z = x7222 z = x7223 z = x7224 z = x7225 z = x7226 z = x7227 z = x7228 z = x7229 z = x7230 z = x7231 z = x7232 z = x7233 z = x7234 z = x7235 z = x7236 z = x7237 z = x7238 z = x7239 z = x7240 z = x7241 z = x7242 z = x7243 z = x7244 z = x7245 z = x7246 z = x7247 z = x7248 z = x7249 z = x7250 z = x7251 z = x7252 z = x7253 z = x7254 z = x7255 z = x7256 z = x7257 z = x7258 z = x7259 z = x7260 z = x7261 z = x7262 z = x7263 z = x7264 z = x7265 z = x7266 z = x7267 z = x7268 z = x7269 z = x7270 z = x7271 z = x7272 z = x7273 z = x7274 z = x7275 z = x7276 z = x7277 z = x7278 z = x7279 z = x7280 z = x7281 z = x7282 z = x7283 z = x7284 z = x7285 z = x7286 z = x7287 z = x7288 z = x7289 z = x7290 z = x7291 z = x7292 z = x7293 z = x7294 z = x7295 z = x7296 z = x7297 z = x7298 z = x7299 z = x7300 z = x7301 z = x7302 z = x7303 z = x7304 z = x7305 z = x7306 z = x7307 z = x7308 z = x7309 z = x7310 z = x7311 z = x7312 z = x7313 z = x7314 z = x7315 z = x7316 z = x7317 z = x7318 z = x7319 z = x7320 z = x7321 z = x7322 z = x7323 z = x7324 z = x7325 z = x7326 z = x7327 z = x7328 z = x7329 z = x7330 z = x7331 z = x7332 z = x7333 z = x7334 z = x7335 z = x7336 z = x7337 z = x7338 z = x7339 z = x7340 z = x7341 z = x7342 z = x7343 z = x7344 z = x7345 z = x7346 z = x7347 z = x7348 z = x7349 z = x7350 z = x7351 z = x7352 z = x7353 z = x7354 z = x7355 z = x7356 z = x7357 z = x7358 z = x7359 z = x7360 z = x7361 z = x7362 z = x7363 z = x7364 z = x7365 z = x7366 z = x7367 z = x7368 z = x7369 z = x7370 z = x7371 z = x7372 z = x7373 z = x7374 z = x7375 z = x7376 z = x7377 z = x7378 z = x7379 z = x7380 z = x7381 z = x7382 z = x7383 z = x7384 z = x7385 z = x7386 z = x7387 z = x7388 z = x7389 z = x7390 z = x7391 z = x7392 z = x7393 z = x7394 z = x7395 z = x7396 z = x7397 z = x7398 z = x7399 z = x7400 z = x7401 z = x7402 z = x7403 z = x7404 z = x7405 z = x7406 z = x7407 z = x7408 z = x7409 z = x7410 z = x7411 z = x7412 z = x7413 z = x7414 z = x7415 z = x7416 z = x7417 z = x7418 z = x7419 z = x7420 z = x7421 z = x7422 z = x7423 z = x7424 z = x7425 z = x7426 z = x7427 z = x7428 z = x7429 z = x7430 z = x7431 z = x7432 z = x7433 z = x7434 z = x7435 z = x7436 z = x7437 z = x7438 z = x7439 z = x7440 z = x7441 z = x7442 z = x7443 z = x7444 z = x7445 z = x7446 z = x7447 z = x7448 z = x7449 z = x7450 z = x7451 z = x7452 z = x7453 z = x7454 z = x7455 z = x7456 z = x7457 z = x7458 z = x7459 z = x7460 z = x7461 z = x7462 z = x7463 z = x7464 z = x7465 z = x7466 z = x7467 z = x7468 z = x7469 z = x7470 z = x7471 z = x7472 z = x7473 z = x7474 z = x7475 z = x7476 z = x7477 z = x7478 z = x7479 z = x7480 z = x7481 z = x7482 z = x7483 z = x7484 z = x7485 z = x7486 z = x7487 z = x7488 z = x7489 z = x7490 z = x7491 z = x7492 z = x7493 z = x7494 z = x7495 z = x7496 z = x7497 z = x7498 z = x7499 z = x7500 z = x7501 z = x7502 z = x7503 z = x7504 z = x7505 z = x7506 z = x7507 z = x7508 z = x7509 z = x7510 z = x7511 z = x7512 z = x7513 z = x7514 z = x7515 z = x7516 z = x7517 z = x7518 z = x7519 z = x7520 z = x7521 z = x7522 z = x7523 z = x7524 z = x7525 z = x7526 z = x7527 z = x7528 z = x7529 z = x7530 z = x7531 z = x7532 z = x7533 z = x7534 z = x7535 z = x7536 z = x7537 z = x7538 z = x7539 z = x7540 z = x7541 z = x7542 z = x7543 z = x7544 z = x7545 z = x7546 z = x7547 z = x7548 z = x7549 z = x7550 z = x7551 z = x7552 z = x7553 z = x7554 z = x7555 z = x7556 z = x7557 z = x7558 z = x7559 z = x7560 z = x7561 z = x7562 z = x7563 z = x7564 z = x7565 z = x7566 z = x7567 z = x7568 z = x7569 z = x7570 z = x7571 z = x7572 z = x7573 z = x7574 z = x7575 z = x7576 z = x7577 z = x7578 z = x7579 z = x7580 z = x7581 z = x7582 z = x7583 z = x7584 z = x7585 z = x7586 z = x7587 z = x7588 z = x7589 z = x7590 z = x7591 z = x7592 z = x7593 z = x7594 z = x7595 z = x7596 z = x7597 z = x7598 z = x7599 z = x7600 z = x7601 z = x7602 z = x7603 z = x7604 z = x7605 z = x7606 z = x7607 z = x7608 z = x7609 z = x7610 z = x7611 z = x7612 z = x7613 z = x7614 z = x7615 z = x7616 z = x7617 z = x7618 z = x7619 z = x7620 z = x7621 z = x7622 z = x7623 z = x7624 z = x7625 z = x7626 z = x7627 z = x7628 z = x7629 z = x7630 z = x7631 z = x7632 z = x7633 z = x7634 z = x7635 z = x7636 z = x7637 z = x7638 z = x7639 z = x7640 z = x7641 z = x7642 z = x7643 z = x7644 z = x7645 z = x7646 z = x7647 z = x7648 z = x7649 z = x7650 z = x7651 z = x7652 z = x7653 z = x7654 z = x7655 z = x7656 z = x7657 z = x7658 z = x7659 z = x7660 z = x7661 z = x7662 z = x7663 z = x7664 z = x7665 z = x7666 z = x7667 z = x7668 z = x7669 z = x7670 z = x7671 z = x7672 z = x7673 z = x7674 z = x7675 z = x7676 z = x7677 z = x7678 z = x7679 z = x7680 z = x7681 z = x7682 z = x7683 z = x7684 z = x7685 z = x7686 z = x7687 z = x7688 z = x7689 z = x7690 z = x7691 z = x7692 z = x7693 z = x7694 z = x7695 z = x7696 z = x7697 z = x7698 z = x7699 z = x7700 z = x7701 z = x7702 z = x7703 z = x7704 z = x7705 z = x7706 z = x7707 z = x7708 z = x7709 z = x7710 z = x7711 z = x7712 z = x7713 z = x7714 z = x7715 z = x7716 z = x7717 z = x7718 z = x7719 z = x7720 z = x7721 z = x7722 z = x7723 z = x7724 z = x7725 z = x7726 z = x7727 z = x7728 z = x7729 z = x7730 z = x7731 z = x7732 z = x7733 z = x7734 z = x7735 z = x7736 z = x7737 z = x7738 z = x7739 z = x7740 z = x7741 z = x7742 z = x7743 z = x7744 z = x7745 z = x7746 z = x7747 z = x7748 z = x7749 z = x7750 z = x7751 z = x7752 z = x7753 z = x7754 z = x7755 z = x7756 z = x7757 z = x7758 z = x7759 z = x7760 z = x7761 z = x7762 z = x7763 z = x7764 z = x7765 z = x7766 z = x7767 z = x7768 z = x7769 z = x7770 z = x7771 z = x7772 z = x7773 z = x7774 z = x7775 z = x7776 z = x7777 z = x7778 z = x7779 z = x7780 z = x7781 z = x7782 z = x7783 z = x7784 z = x7785 z = x7786 z = x7787 z = x7788 z = x7789 z = x7790 z = x7791 z = x7792 z = x7793 z = x7794 z = x7795 z = x7796 z = x7797 z = x7798 z = x7799 z = x7800 z = x7801 z = x7802 z = x7803 z = x7804 z = x7805 z = x7806 z = x7807 z = x7808 z = x7809 z = x7810 z = x7811 z = x7812 z = x7813 z = x7814 z = x7815 z = x7816 z = x7817 z = x7818 z = x7819 z = x7820 z = x7821 z = x7822 z = x7823 z = x7824 z = x7825 z = x7826 z = x7827 z = x7828 z = x7829 z = x7830 z = x7831 z = x7832 z = x7833 z = x7834 z = x7835 z = x7836 z = x7837 z = x7838 z = x7839 z = x7840 z = x7841 z = x7842 z = x7843 z = x7844 z = x7845 z = x7846 z = x7847 z = x7848 z = x7849 z = x7850 z = x7851 z = x7852 z = x7853 z = x7854 z = x7855 z = x7856 z = x7857 z = x7858 z = x7859 z = x7860 z = x7861 z = x7862 z = x7863 z = x7864 z = x7865 z = x7866 z = x7867 z = x7868 z = x7869 z = x7870 z = x7871 z = x7872 z = x7873 z = x7874 z = x7875 z = x7876 z = x7877 z = x7878 z = x7879 z = x7880 z = x7881 z = x7882 z = x7883 z = x7884 z = x7885 z = x7886 z = x7887 z = x7888 z = x7889 z = x7890 z = x7891 z = x7892 z = x7893 z = x7894 z = x7895 z = x7896 z = x7897 z = x7898 z = x7899 z = x7900 z = x7901 z = x7902 z = x7903 z = x7904 z = x7905 z = x7906 z = x7907 z = x7908 z = x7909 z = x7910 z = x7911 z = x7912 z = x7913 z = x7914 z = x7915 z = x7916 z = x7917 z = x7918 z = x7919 z = x7920 z = x7921 z = x7922 z = x7923 z = x7924 z = x7925 z = x7926 z = x7927 z = x7928 z = x7929 z = x7930 z = x7931 z = x7932 z = x7933 z = x7934 z = x7935 z = x7936 z = x7937 z = x7938 z = x7939 z = x7940 z = x7941 z = x7942 z = x7943 z = x7944 z = x7945 z = x7946 z = x7947 z = x7948 z = x7949 z = x7950 z = x7951 z = x7952 z = x7953 z = x7954 z = x7955 z = x7956 z = x7957 z = x7958 z = x7959 z = x7960 z = x7961 z = x7962 z = x7963 z = x7964 z = x7965 z = x7966 z = x7967 z = x7968 z = x7969 z = x7970 z = x7971 z = x7972 z = x7973 z = x7974 z = x7975 z = x7976 z = x7977 z = x7978 z = x7979 z = x7980 z = x7981 z = x7982 z = x7983 z = x7984 z = x7985 z = x7986 z = x7987 z = x7988 z = x7989 z = x7990 z = x7991 z = x7992 z = x7993 z = x7994 z = x7995 z = x7996 z = x7997 z = x7998 z = x7999 z = x8000 z = x8001 z = x8002 z = x8003 z = x8004 z = x8005 z = x8006 z = x8007 z = x8008 z = x8009 z = x8010 z = x8011 z = x8012 z = x8013 z = x8014 z = x8015 z = x8016 z = x8017 z = x8018 z = x8019 z = x8020 z = x8021 z = x8022 z = x8023 z = x8024 z = x8025 z = x8026 z = x8027 z = x8028 z = x8029 z = x8030 z = x8031 z = x8032 z = x8033 z = x8034 z = x8035 z = x8036 z = x8037 z = x8038 z = x8039 z = x8040 z = x8041 z = x8042 z = x8043 z = x8044 z = x8045 z = x8046 z = x8047 z = x8048 z = x8049 z = x8050 z = x8051 z = x8052 z = x8053 z = x8054 z = x8055 z = x8056 z = x8057 z = x8058 z = x8059 z = x8060 z = x8061 z = x8062 z = x8063 z = x8064 z = x8065 z = x8066 z = x8067 z = x8068 z = x8069 z = x8070 z = x8071 z = x8072 z = x8073 z = x8074 z = x8075 z = x8076 z = x8077 z = x8078 z = x8079 z = x8080 z = x8081 z = x8082 z = x8083 z = x8084 z = x8085 z = x8086 z = x8087 z = x8088 z = x8089 z = x8090 z = x8091 z = x8092 z = x8093 z = x8094 z = x8095 z = x8096 z = x8097 z = x8098 z = x8099 z = x8100 z = x8101 z = x8102 z = x8103 z = x8104 z = x8105 z = x8106 z = x8107 z = x8108 z = x8109 z = x8110 z = x8111 z = x8112 z = x8113 z = x8114 z = x8115 z = x8116 z = x8117 z = x8118 z = x8119 z = x8120 z = x8121 z = x8122 z = x8123 z = x8124 z = x8125 z = x8126 z = x8127 z = x8128 z = x8129 z = x8130 z = x8131 z = x8132 z = x8133 z = x8134 z = x8135 z = x8136 z = x8137 z = x8138 z = x8139 z = x8140 z = x8141 z = x8142 z = x8143 z = x8144 z = x8145 z = x8146 z = x8147 z = x8148 z = x8149 z = x8150 z = x8151 z = x8152 z = x8153 z = x8154 z = x8155 z = x8156 z = x8157 z = x8158 z = x8159 z = x8160 z = x8161 z = x8162 z = x8163 z = x8164 z = x8165 z = x8166 z = x8167 z = x8168 z = x8169 z = x8170 z = x8171 z = x8172 z = x8173 z = x8174 z = x8175 z = x8176 z = x8177 z = x8178 z = x8179 z = x8180 z = x8181 z = x8182 z = x8183 z = x8184 z = x8185 z = x8186 z = x8187 z = x8188 z = x8189 z = x8190 z = x8191 z = x8192 z = x8193 z = x8194 z = x8195 z = x8196 z = x8197 z = x8198 z = x8199 z = x8200 z = x8201 z = x8202 z = x8203 z = x8204 z = x8205 z = x8206 z = x8207 z = x8208 z = x8209 z = x8210 z = x8211 z = x8212 z = x8213 z = x8214 z = x8215 z = x8216 z = x8217 z = x8218 z = x8219 z = x8220 z = x8221 z = x8222 z = x8223 z = x8224 z = x8225 z = x8226 z = x8227 z = x8228 z = x8229 z = x8230 z = x8231 z = x8232 z = x8233 z = x8234 z = x8235 z = x8236 z = x8237 z = x8238 z = x8239 z = x8240 z = x8241 z = x8242 z = x8243 z = x8244 z = x8245 z = x8246 z = x8247 z = x8248 z = x8249 z = x8250 z = x8251 z = x8252 z = x8253 z = x8254 z = x8255 z = x8256 z = x8257 z = x8258 z = x8259 z = x8260 z = x8261 z = x8262 z = x8263 z = x8264 z = x8265 z = x8266 z = x8267 z = x8268 z = x8269 z = x8270 z = x8271 z = x8272 z = x8273 z = x8274 z = x8275 z = x8276 z = x8277 z = x8278 z = x8279 z = x8280 z = x8281 z = x8282 z = x8283 z = x8284 z = x8285 z = x8286 z = x8287 z = x8288 z = x8289 z = x8290 z = x8291 z = x8292 z = x8293 z = x8294 z = x8295 z = x8296 z = x8297 z = x8298 z = x8299 z = x8300 z = x8301 z = x8302 z = x8303 z = x8304 z = x8305 z = x8306 z = x8307 z = x8308 z = x8309 z = x8310 z = x8311 z = x8312 z = x8313 z = x8314 z = x8315 z = x8316 z = x8317 z = x8318 z = x8319 z = x8320 z = x8321 z = x8322 z = x8323 z = x8324 z = x8325 z = x8326 z = x8327 z = x8328 z = x8329 z = x8330 z = x8331 z = x8332 z = x8333 z = x8334 z = x8335 z = x8336 z = x8337 z = x8338 z = x8339 z = x8340 z = x8341 z = x8342 z = x8343 z = x8344 z = x8345 z = x8346 z = x8347 z = x8348 z = x8349 z = x8350 z = x8351 z = x8352 z = x8353 z = x8354 z = x8355 z = x8356 z = x8357 z = x8358 z = x8359 z = x8360 z = x8361 z = x8362 z = x8363 z = x8364 z = x8365 z = x8366 z = x8367 z = x8368 z = x8369 z = x8370 z = x8371 z = x8372 z = x8373 z = x8374 z = x8375 z = x8376 z = x8377 z = x8378 z = x8379 z = x8380 z = x8381 z = x8382 z = x8383 z = x8384 z = x8385 z = x8386 z = x8387 z = x8388 z = x8389 z = x8390 z = x8391 z = x8392 z = x8393 z = x8394 z = x8395 z = x8396 z = x8397 z = x8398 z = x8399 z = x8400 z = x8401 z = x8402 z = x8403 z = x8404 z = x8405 z = x8406 z = x8407 z = x8408 z = x8409 z = x8410 z = x8411 z = x8412 z = x8413 z = x8414 z = x8415 z = x8416 z = x8417 z = x8418 z = x8419 z = x8420 z = x8421 z = x8422 z = x8423 z = x8424 z = x8425 z = x8426 z = x8427 z = x8428 z = x8429 z = x8430 z = x8431 z = x8432 z = x8433 z = x8434 z = x8435 z = x8436 z = x8437 z = x8438 z = x8439 z = x8440 z = x8441 z = x8442 z = x8443 z = x8444 z = x8445 z = x8446 z = x8447 z = x8448 z = x8449 z = x8450 z = x8451 z = x8452 z = x8453 z = x8454 z = x8455 z = x8456 z = x8457 z = x8458 z = x8459 z = x8460 z = x8461 z = x8462 z = x8463 z = x8464 z = x8465 z = x8466 z = x8467 z = x8468 z = x8469 z = x8470 z = x8471 z = x8472 z = x8473 z = x8474 z = x8475 z = x8476 z = x8477 z = x8478 z = x8479 z = x8480 z = x8481 z = x8482 z = x8483 z = x8484 z = x8485 z = x8486 z = x8487 z = x8488 z = x8489 z = x8490 z = x8491 z = x8492 z = x8493 z = x8494 z = x8495 z = x8496 z = x8497 z = x8498 z = x8499 z = x8500 z = x8501 z = x8502 z = x8503 z = x8504 z = x8505 z = x8506 z = x8507 z = x8508 z = x8509 z = x8510 z = x8511 z = x8512 z = x8513 z = x8514 z = x8515 z = x8516 z = x8517 z = x8518 z = x8519 z = x8520 z = x8521 z = x8522 z = x8523 z = x8524 z = x8525 z = x8526 z = x8527 z = x8528 z = x8529 z = x8530 z = x8531 z = x8532 z = x8533 z = x8534 z = x8535 z = x8536 z = x8537 z = x8538 z = x8539 z = x8540 z = x8541 z = x8542 z = x8543 z = x8544 z = x8545 z = x8546 z = x8547 z = x8548 z = x8549 z = x8550 z = x8551 z = x8552 z = x8553 z = x8554 z = x8555 z = x8556 z = x8557 z = x8558 z = x8559 z = x8560 z = x8561 z = x8562 z = x8563 z = x8564 z = x8565 z = x8566 z = x8567 z = x8568 z = x8569 z = x8570 z = x8571 z = x8572 z = x8573 z = x8574 z = x8575 z = x8576 z = x8577 z = x8578 z = x8579 z = x8580 z = x8581 z = x8582 z = x8583 z = x8584 z = x8585 z = x8586 z = x8587 z = x8588 z = x8589 z = x8590 z = x8591 z = x8592 z = x8593 z = x8594 z = x8595 z = x8596 z = x8597 z = x8598 z = x8599 z = x8600 z = x8601 z = x8602 z = x8603 z = x8604 z = x8605 z = x8606 z = x8607 z = x8608 z = x8609 z = x8610 z = x8611 z = x8612 z = x8613 z = x8614 z = x8615 z = x8616 z = x8617 z = x8618 z = x8619 z = x8620 z = x8621 z = x8622 z = x8623 z = x8624 z = x8625 z = x8626 z = x8627 z = x8628 z = x8629 z = x8630 z = x8631 z = x8632 z = x8633 z = x8634 z = x8635 z = x8636 z = x8637 z = x8638 z = x8639 z = x8640 z = x8641 z = x8642 z = x8643 z = x8644 z = x8645 z = x8646 z = x8647 z = x8648 z = x8649 z = x8650 z = x8651 z = x8652 z = x8653 z = x8654 z = x8655 z = x8656 z = x8657 z = x8658 z = x8659 z = x8660 z = x8661 z = x8662 z = x8663 z = x8664 z = x8665 z = x8666 z = x8667 z = x8668 z = x8669 z = x8670 z = x8671 z = x8672 z = x8673 z = x8674 z = x8675 z = x8676 z = x8677 z = x8678 z = x8679 z = x8680 z = x8681 z = x8682 z = x8683 z = x8684 z = x8685 z = x8686 z = x8687 z = x8688 z = x8689 z = x8690 z = x8691 z = x8692 z = x8693 z = x8694 z = x8695 z = x8696 z = x8697 z = x8698 z = x8699 z = x8700 z = x8701 z = x8702 z = x8703 z = x8704 z = x8705 z = x8706 z = x8707 z = x8708 z = x8709 z = x8710 z = x8711 z = x8712 z = x8713 z = x8714 z = x8715 z = x8716 z = x8717 z = x8718 z = x8719 z = x8720 z = x8721 z = x8722 z = x8723 z = x8724 z = x8725 z = x8726 z = x8727 z = x8728 z = x8729 z = x8730 z = x8731 z = x8732 z = x8733 z = x8734 z = x8735 z = x8736 z = x8737 z = x8738 z = x8739 z = x8740 z = x8741 z = x8742 z = x8743 z = x8744 z = x8745 z = x8746 z = x8747 z = x8748 z = x8749 z = x8750 z = x8751 z = x8752 z = x8753 z = x8754 z = x8755 z = x8756 z = x8757 z = x8758 z = x8759 z = x8760 z = x8761 z = x8762 z = x8763 z = x8764 z = x8765 z = x8766 z = x8767 z = x8768 z = x8769 z = x8770 z = x8771 z = x8772 z = x8773 z = x8774 z = x8775 z = x8776 z = x8777 z = x8778 z = x8779 z = x8780 z = x8781 z = x8782 z = x8783 z = x8784 z = x8785 z = x8786 z = x8787 z = x8788 z = x8789 z = x8790 z = x8791 z = x8792 z = x8793 z = x8794 z = x8795 z = x8796 z = x8797 z = x8798 z = x8799 z = x8800 z = x8801 z = x8802 z = x8803 z = x8804 z = x8805 z = x8806 z = x8807 z = x8808 z = x8809 z = x8810 z = x8811 z = x8812 z = x8813 z = x8814 z = x8815 z = x8816 z = x8817 z = x8818 z = x8819 z = x8820 z = x8821 z = x8822 z = x8823 z = x8824 z = x8825 z = x8826 z = x8827 z = x8828 z = x8829 z = x8830 z = x8831 z = x8832 z = x8833 z = x8834 z = x8835 z = x8836 z = x8837 z = x8838 z = x8839 z = x8840 z = x8841 z = x8842 z = x8843 z = x8844 z = x8845 z = x8846 z = x8847 z = x8848 z = x8849 z = x8850 z = x8851 z = x8852 z = x8853 z = x8854 z = x8855 z = x8856 z = x8857 z = x8858 z = x8859 z = x8860 z = x8861 z = x8862 z = x8863 z = x8864 z = x8865 z = x8866 z = x8867 z = x8868 z = x8869 z = x8870 z = x8871 z = x8872 z = x8873 z = x8874 z = x8875 z = x8876 z = x8877 z = x8878 z = x8879 z = x8880 z = x8881 z = x8882 z = x8883 z = x8884 z = x8885 z = x8886 z = x8887 z = x8888 z = x8889 z = x8890 z = x8891 z = x8892 z = x8893 z = x8894 z = x8895 z = x8896 z = x8897 z = x8898 z = x8899 z = x8900 z = x8901 z = x8902 z = x8903 z = x8904 z = x8905 z = x8906 z = x8907 z = x8908 z = x8909 z = x8910 z = x8911 z = x8912 z = x8913 z = x8914 z = x8915 z = x8916 z = x8917 z = x8918 z = x8919 z = x8920 z = x8921 z = x8922 z = x8923 z = x8924 z = x8925 z = x8926 z = x8927 z = x8928 z = x8929 z = x8930 z = x8931 z = x8932 z = x8933 z = x8934 z = x8935 z = x8936 z = x8937 z = x8938 z = x8939 z = x8940 z = x8941 z = x8942 z = x8943 z = x8944 z = x8945 z = x8946 z = x8947 z = x8948 z = x8949 z = x8950 z = x8951 z = x8952 z = x8953 z = x8954 z = x8955 z = x8956 z = x8957 z = x8958 z = x8959 z = x8960 z = x8961 z = x8962 z = x8963 z = x8964 z = x8965 z = x8966 z = x8967 z = x8968 z = x8969 z = x8970 z = x8971 z = x8972 z = x8973 z = x8974 z = x8975 z = x8976 z = x8977 z = x8978 z = x8979 z = x8980 z = x8981 z = x8982 z = x8983 z = x8984 z = x8985 z = x8986 z = x8987 z = x8988 z = x8989 z = x8990 z = x8991 z = x8992 z = x8993 z = x8994 z = x8995 z = x8996 z = x8997 z = x8998 z = x8999 z = x9000 z = x9001 z = x9002 z = x9003 z = x9004 z = x9005 z = x9006 z = x9007 z = x9008 z = x9009 z = x9010 z = x9011 z = x9012 z = x9013 z = x9014 z = x9015 z = x9016 z = x9017 z = x9018 z = x9019 z = x9020 z = x9021 z = x9022 z = x9023 z = x9024 z = x9025 z = x9026 z = x9027 z = x9028 z = x9029 z = x9030 z = x9031 z = x9032 z = x9033 z = x9034 z = x9035 z = x9036 z = x9037 z = x9038 z = x9039 z = x9040 z = x9041 z = x9042 z = x9043 z = x9044 z = x9045 z = x9046 z = x9047 z = x9048 z = x9049 z = x9050 z = x9051 z = x9052 z = x9053 z = x9054 z = x9055 z = x9056 z = x9057 z = x9058 z = x9059 z = x9060 z = x9061 z = x9062 z = x9063 z = x9064 z = x9065 z = x9066 z = x9067 z = x9068 z = x9069 z = x9070 z = x9071 z = x9072 z = x9073 z = x9074 z = x9075 z = x9076 z = x9077 z = x9078 z = x9079 z = x9080 z = x9081 z = x9082 z = x9083 z = x9084 z = x9085 z = x9086 z = x9087 z = x9088 z = x9089 z = x9090 z = x9091 z = x9092 z = x9093 z = x9094 z = x9095 z = x9096 z = x9097 z = x9098 z = x9099 z = x9100 z = x9101 z = x9102 z = x9103 z = x9104 z = x9105 z = x9106 z = x9107 z = x9108 z = x9109 z = x9110 z = x9111 z = x9112 z = x9113 z = x9114 z = x9115 z = x9116 z = x9117 z = x9118 z = x9119 z = x9120 z = x9121 z = x9122 z = x9123 z = x9124 z = x9125 z = x9126 z = x9127 z = x9128 z = x9129 z = x9130 z = x9131 z = x9132 z = x9133 z = x9134 z = x9135 z = x9136 z = x9137 z = x9138 z = x9139 z = x9140 z = x9141 z = x9142 z = x9143 z = x9144 z = x9145 z = x9146 z = x9147 z = x9148 z = x9149 z = x9150 z = x9151 z = x9152 z = x9153 z = x9154 z = x9155 z = x9156 z = x9157 z = x9158 z = x9159 z = x9160 z = x9161 z = x9162 z = x9163 z = x9164 z = x9165 z = x9166 z = x9167 z = x9168 z = x9169 z = x9170 z = x9171 z = x9172 z = x9173 z = x9174 z = x9175 z = x9176 z = x9177 z = x9178 z = x9179 z = x9180 z = x9181 z = x9182 z = x9183 z = x9184 z = x9185 z = x9186 z = x9187 z = x9188 z = x9189 z = x9190 z = x9191 z = x9192 z = x9193 z = x9194 z = x9195 z = x9196 z = x9197 z = x9198 z = x9199 z = x9200 z = x9201 z = x9202 z = x9203 z = x9204 z = x9205 z = x9206 z = x9207 z = x9208 z = x9209 z = x9210 z = x9211 z = x9212 z = x9213 z = x9214 z = x9215 z = x9216 z = x9217 z = x9218 z = x9219 z = x9220 z = x9221 z = x9222 z = x9223 z = x9224 z = x9225 z = x9226 z = x9227 z = x9228 z = x9229 z = x9230 z = x9231 z = x9232 z = x9233 z = x9234 z = x9235 z = x9236 z = x9237 z = x9238 z = x9239 z = x9240 z = x9241 z = x9242 z = x9243 z = x9244 z = x9245 z = x9246 z = x9247 z = x9248 z = x9249 z = x9250 z = x9251 z = x9252 z = x9253 z = x9254 z = x9255 z = x9256 z = x9257 z = x9258 z = x9259 z = x9260 z = x9261 z = x9262 z = x9263 z = x9264 z = x9265 z = x9266 z = x9267 z = x9268 z = x9269 z = x9270 z = x9271 z = x9272 z = x9273 z = x9274 z = x9275 z = x9276 z = x9277 z = x9278 z = x9279 z = x9280 z = x9281 z = x9282 z = x9283 z = x9284 z = x9285 z = x9286 z = x9287 z = x9288 z = x9289 z = x9290 z = x9291 z = x9292 z = x9293 z = x9294 z = x9295 z = x9296 z = x9297 z = x9298 z = x9299 z = x9300 z = x9301 z = x9302 z = x9303 z = x9304 z = x9305 z = x9306 z = x9307 z = x9308 z = x9309 z = x9310 z = x9311 z = x9312 z = x9313 z = x9314 z = x9315 z = x9316 z = x9317 z = x9318 z = x9319 z = x9320 z = x9321 z = x9322 z = x9323 z = x9324 z = x9325 z = x9326 z = x9327 z = x9328 z = x9329 z = x9330 z = x9331 z = x9332 z = x9333 z = x9334 z = x9335 z = x9336 z = x9337 z = x9338 z = x9339 z = x9340 z = x9341 z = x9342 z = x9343 z = x9344 z = x9345 z = x9346 z = x9347 z = x9348 z = x9349 z = x9350 z = x9351 z = x9352 z = x9353 z = x9354 z = x9355 z = x9356 z = x9357 z = x9358 z = x9359 z = x9360 z = x9361 z = x9362 z = x9363 z = x9364 z = x9365 z = x9366 z = x9367 z = x9368 z = x9369 z = x9370 z = x9371 z = x9372 z = x9373 z = x9374 z = x9375 z = x9376 z = x9377 z = x9378 z = x9379 z = x9380 z = x9381 z = x9382 z = x9383 z = x9384 z = x9385 z = x9386 z = x9387 z = x9388 z = x9389 z = x9390 z = x9391 z = x9392 z = x9393 z = x9394 z = x9395 z = x9396 z = x9397 z = x9398 z = x9399 z = x9400 z = x9401 z = x9402 z = x9403 z = x9404 z = x9405 z = x9406 z = x9407 z = x9408 z = x9409 z = x9410 z = x9411 z = x9412 z = x9413 z = x9414 z = x9415 z = x9416 z = x9417 z = x9418 z = x9419 z = x9420 z = x9421 z = x9422 z = x9423 z = x9424 z = x9425 z = x9426 z = x9427 z = x9428 z = x9429 z = x9430 z = x9431 z = x9432 z = x9433 z = x9434 z = x9435 z = x9436 z = x9437 z = x9438 z = x9439 z = x9440 z = x9441 z = x9442 z = x9443 z = x9444 z = x9445 z = x9446 z = x9447 z = x9448 z = x9449 z = x9450 z = x9451 z = x9452 z = x9453 z = x9454 z = x9455 z = x9456 z = x9457 z = x9458 z = x9459 z = x9460 z = x9461 z = x9462 z = x9463 z = x9464 z = x9465 z = x9466 z = x9467 z = x9468 z = x9469 z = x9470 z = x9471 z = x9472 z = x9473 z = x9474 z = x9475 z = x9476 z = x9477 z = x9478 z = x9479 z = x9480 z = x9481 z = x9482 z = x9483 z = x9484 z = x9485 z = x9486 z = x9487 z = x9488 z = x9489 z = x9490 z = x9491 z = x9492 z = x9493 z = x9494 z = x9495 z = x9496 z = x9497 z = x9498 z = x9499 z = x9500 z = x9501 z = x9502 z = x9503 z = x9504 z = x9505 z = x9506 z = x9507 z = x9508 z = x9509 z = x9510 z = x9511 z = x9512 z = x9513 z = x9514 z = x9515 z = x9516 z = x9517 z = x9518 z = x9519 z = x9520 z = x9521 z = x9522 z = x9523 z = x9524 z = x9525 z = x9526 z = x9527 z = x9528 z = x9529 z = x9530 z = x9531 z = x9532 z = x9533 z = x9534 z = x9535 z = x9536 z = x9537 z = x9538 z = x9539 z = x9540 z = x9541 z = x9542 z = x9543 z = x9544 z = x9545 z = x9546 z = x9547 z = x9548 z = x9549 z = x9550 z = x9551 z = x9552 z = x9553 z = x9554 z = x9555 z = x9556 z = x9557 z = x9558 z = x9559 z = x9560 z = x9561 z = x9562 z = x9563 z = x9564 z = x9565 z = x9566 z = x9567 z = x9568 z = x9569 z = x9570 z = x9571 z = x9572 z = x9573 z = x9574 z = x9575 z = x9576 z = x9577 z = x9578 z = x9579 z = x9580 z = x9581 z = x9582 z = x9583 z = x9584 z = x9585 z = x9586 z = x9587 z = x9588 z = x9589 z = x9590 z = x9591 z = x9592 z = x9593 z = x9594 z = x9595 z = x9596 z = x9597 z = x9598 z = x9599 z = x9600 z = x9601 z = x9602 z = x9603 z = x9604 z = x9605 z = x9606 z = x9607 z = x9608 z = x9609 z = x9610 z = x9611 z = x9612 z = x9613 z = x9614 z = x9615 z = x9616 z = x9617 z = x9618 z = x9619 z = x9620 z = x9621 z = x9622 z = x9623 z = x9624 z = x9625 z = x9626 z = x9627 z = x9628 z = x9629 z = x9630 z = x9631 z = x9632 z = x9633 z = x9634 z = x9635 z = x9636 z = x9637 z = x9638 z = x9639 z = x9640 z = x9641 z = x9642 z = x9643 z = x9644 z = x9645 z = x9646 z = x9647 z = x9648 z = x9649 z = x9650 z = x9651 z = x9652 z = x9653 z = x9654 z = x9655 z = x9656 z = x9657 z = x9658 z = x9659 z = x9660 z = x9661 z = x9662 z = x9663 z = x9664 z = x9665 z = x9666 z = x9667 z = x9668 z = x9669 z = x9670 z = x9671 z = x9672 z = x9673 z = x9674 z = x9675 z = x9676 z = x9677 z = x9678 z = x9679 z = x9680 z = x9681 z = x9682 z = x9683 z = x9684 z = x9685 z = x9686 z = x9687 z = x9688 z = x9689 z = x9690 z = x9691 z = x9692 z = x9693 z = x9694 z = x9695 z = x9696 z = x9697 z = x9698 z = x9699 z = x9700 z = x9701 z = x9702 z = x9703 z = x9704 z = x9705 z = x9706 z = x9707 z = x9708 z = x9709 z = x9710 z = x9711 z = x9712 z = x9713 z = x9714 z = x9715 z = x9716 z = x9717 z = x9718 z = x9719 z = x9720 z = x9721 z = x9722 z = x9723 z = x9724 z = x9725 z = x9726 z = x9727 z = x9728 z = x9729 z = x9730 z = x9731 z = x9732 z = x9733 z = x9734 z = x9735 z = x9736 z = x9737 z = x9738 z = x9739 z = x9740 z = x9741 z = x9742 z = x9743 z = x9744 z = x9745 z = x9746 z = x9747 z = x9748 z = x9749 z = x9750 z = x9751 z = x9752 z = x9753 z = x9754 z = x9755 z = x9756 z = x9757 z = x9758 z = x9759 z = x9760 z = x9761 z = x9762 z = x9763 z = x9764 z = x9765 z = x9766 z = x9767 z = x9768 z = x9769 z = x9770 z = x9771 z = x9772 z = x9773 z = x9774 z = x9775 z = x9776 z = x9777 z = x9778 z = x9779 z = x9780 z = x9781 z = x9782 z = x9783 z = x9784 z = x9785 z = x9786 z = x9787 z = x9788 z = x9789 z = x9790 z = x9791 z = x9792 z = x9793 z = x9794 z = x9795 z = x9796 z = x9797 z = x9798 z = x9799 z = x9800 z = x9801 z = x9802 z = x9803 z = x9804 z = x9805 z = x9806 z = x9807 z = x9808 z = x9809 z = x9810 z = x9811 z = x9812 z = x9813 z = x9814 z = x9815 z = x9816 z = x9817 z = x9818 z = x9819 z = x9820 z = x9821 z = x9822 z = x9823 z = x9824 z = x9825 z = x9826 z = x9827 z = x9828 z = x9829 z = x9830 z = x9831 z = x9832 z = x9833 z = x9834 z = x9835 z = x9836 z = x9837 z = x9838 z = x9839 z = x9840 z = x9841 z = x9842 z = x9843 z = x9844 z = x9845 z = x9846 z = x9847 z = x9848 z = x9849 z = x9850 z = x9851 z = x9852 z = x9853 z = x9854 z = x9855 z = x9856 z = x9857 z = x9858 z = x9859 z = x9860 z = x9861 z = x9862 z = x9863 z = x9864 z = x9865 z = x9866 z = x9867 z = x9868 z = x9869 z = x9870 z = x9871 z = x9872 z = x9873 z = x9874 z = x9875 z = x9876 z = x9877 z = x9878 z = x9879 z = x9880 z = x9881 z = x9882 z = x9883 z = x9884 z = x9885 z = x9886 z = x9887 z = x9888 z = x9889 z = x9890 z = x9891 z = x9892 z = x9893 z = x9894 z = x9895 z = x9896 z = x9897 z = x9898 z = x9899 z = x9900 z = x9901 z = x9902 z = x9903 z = x9904 z = x9905 z = x9906 z = x9907 z = x9908 z = x9909 z = x9910 z = x9911 z = x9912 z = x9913 z = x9914 z = x9915 z = x9916 z = x9917 z = x9918 z = x9919 z = x9920 z = x9921 z = x9922 z = x9923 z = x9924 z = x9925 z = x9926 z = x9927 z = x9928 z = x9929 z = x9930 z = x9931 z = x9932 z = x9933 z = x9934 z = x9935 z = x9936 z = x9937 z = x9938 z = x9939 z = x9940 z = x9941 z = x9942 z = x9943 z = x9944 z = x9945 z = x9946 z = x9947 z = x9948 z = x9949 z = x9950 z = x9951 z = x9952 z = x9953 z = x9954 z = x9955 z = x9956 z = x9957 z = x9958 z = x9959 z = x9960 z = x9961 z = x9962 z = x9963 z = x9964 z = x9965 z = x9966 z = x9967 z = x9968 z = x9969 z = x9970 z = x9971 z = x9972 z = x9973 z = x9974 z = x9975 z = x9976 z = x9977 z = x9978 z = x9979 z = x9980 z = x9981 z = x9982 z = x9983 z = x9984 z = x9985 z = x9986 z = x9987 z = x9988 z = x9989 z = x9990 z = x9991 z = x9992 z = x9993 z = x9994 z = x9995 z = x9996 z = x9997 z = x9998 z = x9999 z = x10000 z = x10001 z = x10002 z = x10003 z = x10004 z = x10005 z = x10006 z = x10007 z = x10008 z = x10009 z = x10010 z = x10011 z = x10012 z = x10013 z = x10014 z = x10015 z = x10016 z = x10017 z = x10018 z = x10019 z = x10020 z = x10021 z = x10022 z = x10023 z = x10024 z = x10025 z = x10026 z = x10027 z = x10028 z = x10029 z = x10030 z = x10031 z = x10032 z = x10033 z = x10034 z = x10035 z = x10036 z = x10037 z = x10038 z = x10039 z = x10040 z = x10041 z = x10042 z = x10043 z = x10044 z = x10045 z = x10046 z = x10047 z = x10048 z = x10049 z = x10050 z = x10051 z = x10052 z = x10053 z = x10054 z = x10055 z = x10056 z = x10057 z = x10058 z = x10059 z = x10060 z = x10061 z = x10062 z = x10063 z = x10064 z = x10065 z = x10066 z = x10067 z = x10068 z = x10069 z = x10070 z = x10071 z = x10072 z = x10073 z = x10074 z = x10075 z = x10076 z = x10077 z = x10078 z = x10079 z = x10080 z = x10081 z = x10082 z = x10083 z = x10084 z = x10085 z = x10086 z = x10087 z = x10088 z = x10089 z = x10090 z = x10091 z = x10092 z = x10093 z = x10094 z = x10095 z = x10096 z = x10097 z = x10098 z = x10099 z = x10100 z = x10101 z = x10102 z = x10103 z = x10104 z = x10105 z = x10106 z = x10107 z = x10108 z = x10109 z = x10110 z = x10111 z = x10112 z = x10113 z = x10114 z = x10115 z = x10116 z = x10117 z = x10118 z = x10119 z = x10120 z = x10121 z = x10122 z = x10123 z = x10124 z = x10125 z = x10126 z = x10127 z = x10128 z = x10129 z = x10130 z = x10131 z = x10132 z = x10133 z = x10134 z = x10135 z = x10136 z = x10137 z = x10138 z = x10139 z = x10140 z = x10141 z = x10142 z = x10143 z = x10144 z = x10145 z = x10146 z = x10147 z = x10148 z = x10149 z = x10150 z = x10151 z = x10152 z = x10153 z = x10154 z = x10155 z = x10156 z = x10157 z = x10158 z = x10159 z = x10160 z = x10161 z = x10162 z = x10163 z = x10164 z = x10165 z = x10166 z = x10167 z = x10168 z = x10169 z = x10170 z = x10171 z = x10172 z = x10173 z = x10174 z = x10175 z = x10176 z = x10177 z = x10178 z = x10179 z = x10180 z = x10181 z = x10182 z = x10183 z = x10184 z = x10185 z = x10186 z = x10187 z = x10188 z = x10189 z = x10190 z = x10191 z = x10192 z = x10193 z = x10194 z = x10195 z = x10196 z = x10197 z = x10198 z = x10199 z = x10200 z = x10201 z = x10202 z = x10203 z = x10204 z = x10205 z = x10206 z = x10207 z = x10208 z = x10209 z = x10210 z = x10211 z = x10212 z = x10213 z = x10214 z = x10215 z = x10216 z = x10217 z = x10218 z = x10219 z = x10220 z = x10221 z = x10222 z = x10223 z = x10224 z = x10225 z = x10226 z = x10227 z = x10228 z = x10229 z = x10230 z = x10231 z = x10232 z = x10233 z = x10234 z = x10235 z = x10236 z = x10237 z = x10238 z = x10239 z = x10240 z = x10241 z = x10242 z = x10243 z = x10244 z = x10245 z = x10246 z = x10247 z = x10248 z = x10249 z = x10250 z = x10251 z = x10252 z = x10253 z = x10254 z = x10255 z = x10256 z = x10257 z = x10258 z = x10259 z = x10260 z = x10261 z = x10262 z = x10263 z = x10264 z = x10265 z = x10266 z = x10267 z = x10268 z = x10269 z = x10270 z = x10271 z = x10272 z = x10273 z = x10274 z = x10275 z = x10276 z = x10277 z = x10278 z = x10279 z = x10280 z = x10281 z = x10282 z = x10283 z = x10284 z = x10285 z = x10286 z = x10287 z = x10288 z = x10289 z = x10290 z = x10291 z = x10292 z = x10293 z = x10294 z = x10295 z = x10296 z = x10297 z = x10298 z = x10299 z = x10300 z = x10301 z = x10302 z = x10303 z = x10304 z = x10305 z = x10306 z = x10307 z = x10308 z = x10309 z = x10310 z = x10311 z = x10312 z = x10313 z = x10314 z = x10315 z = x10316 z = x10317 z = x10318 z = x10319 z = x10320 z = x10321 z = x10322 z = x10323 z = x10324 z = x10325 z = x10326 z = x10327 z = x10328 z = x10329 z = x10330 z = x10331 z = x10332 z = x10333 z = x10334 z = x10335 z = x10336 z = x10337 z = x10338 z = x10339 z = x10340 z = x10341 z = x10342 z = x10343 z = x10344 z = x10345 z = x10346 z = x10347 z = x10348 z = x10349 z = x10350 z = x10351 z = x10352 z = x10353 z = x10354 z = x10355 z = x10356 z = x10357 z = x10358 z = x10359 z = x10360 z = x10361 z = x10362 z = x10363 z = x10364 z = x10365 z = x10366 z = x10367 z = x10368 z = x10369 z = x10370 z = x10371 z = x10372 z = x10373 z = x10374 z = x10375 z = x10376 z = x10377 z = x10378 z = x10379 z = x10380 z = x10381 z = x10382 z = x10383 z = x10384 z = x10385 z = x10386 z = x10387 z = x10388 z = x10389 z = x10390 z = x10391 z = x10392 z = x10393 z = x10394 z = x10395 z = x10396 z = x10397 z = x10398 z = x10399 z = x10400 z = x10401 z = x10402 z = x10403 z = x10404 z = x10405 z = x10406 z = x10407 z = x10408 z = x10409 z = x10410 z = x10411 z = x10412 z = x10413 z = x10414 z = x10415 z = x10416 z = x10417 z = x10418 z = x10419 z = x10420 z = x10421 z = x10422 z = x10423 z = x10424 z = x10425 z = x10426 z = x10427 z = x10428 z = x10429 z = x10430 z = x10431 z = x10432 z = x10433 z = x10434 z = x10435 z = x10436 z = x10437 z = x10438 z = x10439 z = x10440 z = x10441 z = x10442 z = x10443 z = x10444 z = x10445 z = x10446 z = x10447 z = x10448 z = x10449 z = x10450 z = x10451 z = x10452 z = x10453 z = x10454 z = x10455 z = x10456 z = x10457 z = x10458 z = x10459 z = x10460 z = x10461 z = x10462 z = x10463 z = x10464 z = x10465 z = x10466 z = x10467 z = x10468 z = x10469 z = x10470 z = x10471 z = x10472 z = x10473 z = x10474 z = x10475 z = x10476 z = x10477 z = x10478 z = x10479 z = x10480 z = x10481 z = x10482 z = x10483 z = x10484 z = x10485 z = x10486 z = x10487 z = x10488 z = x10489 z = x10490 z = x10491 z = x10492 z = x10493 z = x10494 z = x10495 z = x10496 z = x10497 z = x10498 z = x10499 z = x10500 z = x10501 z = x10502 z = x10503 z = x10504 z = x10505 z = x10506 z = x10507 z = x10508 z = x10509 z = x10510 z = x10511 z = x10512 z = x10513 z = x10514 z = x10515 z = x10516 z = x10517 z = x10518 z = x10519 z = x10520 z = x10521 z = x10522 z = x10523 z = x10524 z = x10525 z = x10526 z = x10527 z = x10528 z = x10529 z = x10530 z = x10531 z = x10532 z = x10533 z = x10534 z = x10535 z = x10536 z = x10537 z = x10538 z = x10539 z = x10540 z = x10541 z = x10542 z = x10543 z = x10544 z = x10545 z = x10546 z = x10547 z = x10548 z = x10549 z = x10550 z = x10551 z = x10552 z = x10553 z = x10554 z = x10555 z = x10556 z = x10557 z = x10558 z = x10559 z = x10560 z = x10561 z = x10562 z = x10563 z = x10564 z = x10565 z = x10566 z = x10567 z = x10568 z = x10569 z = x10570 z = x10571 z = x10572 z = x10573 z = x10574 z = x10575 z = x10576 z = x10577 z = x10578 z = x10579 z = x10580 z = x10581 z = x10582 z = x10583 z = x10584 z = x10585 z = x10586 z = x10587 z = x10588 z = x10589 z = x10590 z = x10591 z = x10592 z = x10593 z = x10594 z = x10595 z = x10596 z = x10597 z = x10598 z = x10599 z = x10600 z = x10601 z = x10602 z = x10603 z = x10604 z = x10605 z = x10606 z = x10607 z = x10608 z = x10609 z = x10610 z = x10611 z = x10612 z = x10613 z = x10614 z = x10615 z = x10616 z = x10617 z = x10618 z = x10619 z = x10620 z = x10621 z = x10622 z = x10623 z = x10624 z = x10625 z = x10626 z = x10627 z = x10628 z = x10629 z = x10630 z = x10631 z = x10632 z = x10633 z = x10634 z = x10635 z = x10636 z = x10637 z = x10638 z = x10639 z = x10640 z = x10641 z = x10642 z = x10643 z = x10644 z = x10645 z = x10646 z = x10647 z = x10648 z = x10649 z = x10650 z = x10651 z = x10652 z = x10653 z = x10654 z = x10655 z = x10656 z = x10657 z = x10658 z = x10659 z = x10660 z = x10661 z = x10662 z = x10663 z = x10664 z = x10665 z = x10666 z = x10667 z = x10668 z = x10669 z = x10670 z = x10671 z = x10672 z = x10673 z = x10674 z = x10675 z = x10676 z = x10677 z = x10678 z = x10679 z = x10680 z = x10681 z = x10682 z = x10683 z = x10684 z = x10685 z = x10686 z = x10687 z = x10688 z = x10689 z = x10690 z = x10691 z = x10692 z = x10693 z = x10694 z = x10695 z = x10696 z = x10697 z = x10698 z = x10699 z = x10700 z = x10701 z = x10702 z = x10703 z = x10704 z = x10705 z = x10706 z = x10707 z = x10708 z = x10709 z = x10710 z = x10711 z = x10712 z = x10713 z = x10714 z = x10715 z = x10716 z = x10717 z = x10718 z = x10719 z = x10720 z = x10721 z = x10722 z = x10723 z = x10724 z = x10725 z = x10726 z = x10727 z = x10728 z = x10729 z = x10730 z = x10731 z = x10732 z = x10733 z = x10734 z = x10735 z = x10736 z = x10737 z = x10738 z = x10739 z = x10740 z = x10741 z = x10742 z = x10743 z = x10744 z = x10745 z = x10746 z = x10747 z = x10748 z = x10749 z = x10750 z = x10751 z = x10752 z = x10753 z = x10754 z = x10755 z = x10756 z = x10757 z = x10758 z = x10759 z = x10760 z = x10761 z = x10762 z = x10763 z = x10764 z = x10765 z = x10766 z = x10767 z = x10768 z = x10769 z = x10770 z = x10771 z = x10772 z = x10773 z = x10774 z = x10775 z = x10776 z = x10777 z = x10778 z = x10779 z = x10780 z = x10781 z = x10782 z = x10783 z = x10784 z = x10785 z = x10786 z = x10787 z = x10788 z = x10789 z = x10790 z = x10791 z = x10792 z = x10793 z = x10794 z = x10795 z = x10796 z = x10797 z = x10798 z = x10799 z = x10800 z = x10801 z = x10802 z = x10803 z = x10804 z = x10805 z = x10806 z = x10807 z = x10808 z = x10809 z = x10810 z = x10811 z = x10812 z = x10813 z = x10814 z = x10815 z = x10816 z = x10817 z = x10818 z = x10819 z = x10820 z = x10821 z = x10822 z = x10823 z = x10824 z = x10825 z = x10826 z = x10827 z = x10828 z = x10829 z = x10830 z = x10831 z = x10832 z = x10833 z = x10834 z = x10835 z = x10836 z = x10837 z = x10838 z = x10839 z = x10840 z = x10841 z = x10842 z = x10843 z = x10844 z = x10845 z = x10846 z = x10847 z = x10848 z = x10849 z = x10850 z = x10851 z = x10852 z = x10853 z = x10854 z = x10855 z = x10856 z = x10857 z = x10858 z = x10859 z = x10860 z = x10861 z = x10862 z = x10863 z = x10864 z = x10865 z = x10866 z = x10867 z = x10868 z = x10869 z = x10870 z = x10871 z = x10872 z = x10873 z = x10874 z = x10875 z = x10876 z = x10877 z = x10878 z = x10879 z = x10880 z = x10881 z = x10882 z = x10883 z = x10884 z = x10885 z = x10886 z = x10887 z = x10888 z = x10889 z = x10890 z = x10891 z = x10892 z = x10893 z = x10894 z = x10895 z = x10896 z = x10897 z = x10898 z = x10899 z = x10900 z = x10901 z = x10902 z = x10903 z = x10904 z = x10905 z = x10906 z = x10907 z = x10908 z = x10909 z = x10910 z = x10911 z = x10912 z = x10913 z = x10914 z = x10915 z = x10916 z = x10917 z = x10918 z = x10919 z = x10920 z = x10921 z = x10922 z = x10923 z = x10924 z = x10925 z = x10926 z = x10927 z = x10928 z = x10929 z = x10930 z = x10931 z = x10932 z = x10933 z = x10934 z = x10935 z = x10936 z = x10937 z = x10938 z = x10939 z = x10940 z = x10941 z = x10942 z = x10943 z = x10944 z = x10945 z = x10946 z = x10947 z = x10948 z = x10949 z = x10950 z = x10951 z = x10952 z = x10953 z = x10954 z = x10955 z = x10956 z = x10957 z = x10958 z = x10959 z = x10960 z = x10961 z = x10962 z = x10963 z = x10964 z = x10965 z = x10966 z = x10967 z = x10968 z = x10969 z = x10970 z = x10971 z = x10972 z = x10973 z = x10974 z = x10975 z = x10976 z = x10977 z = x10978 z = x10979 z = x10980 z = x10981 z = x10982 z = x10983 z = x10984 z = x10985 z = x10986 z = x10987 z = x10988 z = x10989 z = x10990 z = x10991 z = x10992 z = x10993 z = x10994 z = x10995 z = x10996 z = x10997 z = x10998 z = x10999 z = x11000 z = x11001 z = x11002 z = x11003 z = x11004 z = x11005 z = x11006 z = x11007 z = x11008 z = x11009 z = x11010 z = x11011 z = x11012 z = x11013 z = x11014 z = x11015 z = x11016 z = x11017 z = x11018 z = x11019 z = x11020 z = x11021 z = x11022 z = x11023 z = x11024 z = x11025 z = x11026 z = x11027 z = x11028 z = x11029 z = x11030 z = x11031 z = x11032 z = x11033 z = x11034 z = x11035 z = x11036 z = x11037 z = x11038 z = x11039 z = x11040 z = x11041 z = x11042 z = x11043 z = x11044 z = x11045 z = x11046 z = x11047 z = x11048 z = x11049 z = x11050 z = x11051 z = x11052 z = x11053 z = x11054 z = x11055 z = x11056 z = x11057 z = x11058 z = x11059 z = x11060 z = x11061 z = x11062 z = x11063 z = x11064 z = x11065 z = x11066 z = x11067 z = x11068 z = x11069 z = x11070 z = x11071 z = x11072 z = x11073 z = x11074 z = x11075 z = x11076 z = x11077 z = x11078 z = x11079 z = x11080 z = x11081 z = x11082 z = x11083 z = x11084 z = x11085 z = x11086 z = x11087 z = x11088 z = x11089 z = x11090 z = x11091 z = x11092 z = x11093 z = x11094 z = x11095 z = x11096 z = x11097 z = x11098 z = x11099 z = x11100 z = x11101 z = x11102 z = x11103 z = x11104 z = x11105 z = x11106 z = x11107 z = x11108 z = x11109 z = x11110 z = x11111 z = x11112 z = x11113 z = x11114 z = x11115 z = x11116 z = x11117 z = x11118 z = x11119 z = x11120 z = x11121 z = x11122 z = x11123 z = x11124 z = x11125 z = x11126 z = x11127 z = x11128 z = x11129 z = x11130 z = x11131 z = x11132 z = x11133 z = x11134 z = x11135 z = x11136 z = x11137 z = x11138 z = x11139 z = x11140 z = x11141 z = x11142 z = x11143 z = x11144 z = x11145 z = x11146 z = x11147 z = x11148 z = x11149 z = x11150 z = x11151 z = x11152 z = x11153 z = x11154 z = x11155 z = x11156 z = x11157 z = x11158 z = x11159 z = x11160 z = x11161 z = x11162 z = x11163 z = x11164 z = x11165 z = x11166 z = x11167 z = x11168 z = x11169 z = x11170 z = x11171 z = x11172 z = x11173 z = x11174 z = x11175 z = x11176 z = x11177 z = x11178 z = x11179 z = x11180 z = x11181 z = x11182 z = x11183 z = x11184 z = x11185 z = x11186 z = x11187 z = x11188 z = x11189 z = x11190 z = x11191 z = x11192 z = x11193 z = x11194 z = x11195 z = x11196 z = x11197 z = x11198 z = x11199 z = x11200 z = x11201 z = x11202 z = x11203 z = x11204 z = x11205 z = x11206 z = x11207 z = x11208 z = x11209 z = x11210 z = x11211 z = x11212 z = x11213 z = x11214 z = x11215 z = x11216 z = x11217 z = x11218 z = x11219 z = x11220 z = x11221 z = x11222 z = x11223 z = x11224 z = x11225 z = x11226 z = x11227 z = x11228 z = x11229 z = x11230 z = x11231 z = x11232 z = x11233 z = x11234 z = x11235 z = x11236 z = x11237 z = x11238 z = x11239 z = x11240 z = x11241 z = x11242 z = x11243 z = x11244 z = x11245 z = x11246 z = x11247 z = x11248 z = x11249 z = x11250 z = x11251 z = x11252 z = x11253 z = x11254 z = x11255 z = x11256 z = x11257 z = x11258 z = x11259 z = x11260 z = x11261 z = x11262 z = x11263 z = x11264 z = x11265 z = x11266 z = x11267 z = x11268 z = x11269 z = x11270 z = x11271 z = x11272 z = x11273 z = x11274 z = x11275 z = x11276 z = x11277 z = x11278 z = x11279 z = x11280 z = x11281 z = x11282 z = x11283 z = x11284 z = x11285 z = x11286 z = x11287 z = x11288 z = x11289 z = x11290 z = x11291 z = x11292 z = x11293 z = x11294 z = x11295 z = x11296 z = x11297 z = x11298 z = x11299 z = x11300 z = x11301 z = x11302 z = x11303 z = x11304 z = x11305 z = x11306 z = x11307 z = x11308 z = x11309 z = x11310 z = x11311 z = x11312 z = x11313 z = x11314 z = x11315 z = x11316 z = x11317 z = x11318 z = x11319 z = x11320 z = x11321 z = x11322 z = x11323 z = x11324 z = x11325 z = x11326 z = x11327 z = x11328 z = x11329 z = x11330 z = x11331 z = x11332 z = x11333 z = x11334 z = x11335 z = x11336 z = x11337 z = x11338 z = x11339 z = x11340 z = x11341 z = x11342 z = x11343 z = x11344 z = x11345 z = x11346 z = x11347 z = x11348 z = x11349 z = x11350 z = x11351 z = x11352 z = x11353 z = x11354 z = x11355 z = x11356 z = x11357 z = x11358 z = x11359 z = x11360 z = x11361 z = x11362 z = x11363 z = x11364 z = x11365 z = x11366 z = x11367 z = x11368 z = x11369 z = x11370 z = x11371 z = x11372 z = x11373 z = x11374 z = x11375 z = x11376 z = x11377 z = x11378 z = x11379 z = x11380 z = x11381 z = x11382 z = x11383 z = x11384 z = x11385 z = x11386 z = x11387 z = x11388 z = x11389 z = x11390 z = x11391 z = x11392 z = x11393 z = x11394 z = x11395 z = x11396 z = x11397 z = x11398 z = x11399 z = x11400 z = x11401 z = x11402 z = x11403 z = x11404 z = x11405 z = x11406 z = x11407 z = x11408 z = x11409 z = x11410 z = x11411 z = x11412 z = x11413 z = x11414 z = x11415 z = x11416 z = x11417 z = x11418 z = x11419 z = x11420 z = x11421 z = x11422 z = x11423 z = x11424 z = x11425 z = x11426 z = x11427 z = x11428 z = x11429 z = x11430 z = x11431 z = x11432 z = x11433 z = x11434 z = x11435 z = x11436 z = x11437 z = x11438 z = x11439 z = x11440 z = x11441 z = x11442 z = x11443 z = x11444 z = x11445 z = x11446 z = x11447 z = x11448 z = x11449 z = x11450 z = x11451 z = x11452 z = x11453 z = x11454 z = x11455 z = x11456 z = x11457 z = x11458 z = x11459 z = x11460 z = x11461 z = x11462 z = x11463 z = x11464 z = x11465 z = x11466 z = x11467 z = x11468 z = x11469 z = x11470 z = x11471 z = x11472 z = x11473 z = x11474 z = x11475 z = x11476 z = x11477 z = x11478 z = x11479 z = x11480 z = x11481 z = x11482 z = x11483 z = x11484 z = x11485 z = x11486 z = x11487 z = x11488 z = x11489 z = x11490 z = x11491 z = x11492 z = x11493 z = x11494 z = x11495 z = x11496 z = x11497 z = x11498 z = x11499 z = x11500 z = x11501 z = x11502 z = x11503 z = x11504 z = x11505 z = x11506 z = x11507 z = x11508 z = x11509 z = x11510 z = x11511 z = x11512 z = x11513 z = x11514 z = x11515 z = x11516 z = x11517 z = x11518 z = x11519 z = x11520 z = x11521 z = x11522 z = x11523 z = x11524 z = x11525 z = x11526 z = x11527 z = x11528 z = x11529 z = x11530 z = x11531 z = x11532 z = x11533 z = x11534 z = x11535 z = x11536 z = x11537 z = x11538 z = x11539 z = x11540 z = x11541 z = x11542 z = x11543 z = x11544 z = x11545 z = x11546 z = x11547 z = x11548 z = x11549 z = x11550 z = x11551 z = x11552 z = x11553 z = x11554 z = x11555 z = x11556 z = x11557 z = x11558 z = x11559 z = x11560 z = x11561 z = x11562 z = x11563 z = x11564 z = x11565 z = x11566 z = x11567 z = x11568 z = x11569 z = x11570 z = x11571 z = x11572 z = x11573 z = x11574 z = x11575 z = x11576 z = x11577 z = x11578 z = x11579 z = x11580 z = x11581 z = x11582 z = x11583 z = x11584 z = x11585 z = x11586 z = x11587 z = x11588 z = x11589 z = x11590 z = x11591 z = x11592 z = x11593 z = x11594 z = x11595 z = x11596 z = x11597 z = x11598 z = x11599 z = x11600 z = x11601 z = x11602 z = x11603 z = x11604 z = x11605 z = x11606 z = x11607 z = x11608 z = x11609 z = x11610 z = x11611 z = x11612 z = x11613 z = x11614 z = x11615 z = x11616 z = x11617 z = x11618 z = x11619 z = x11620 z = x11621 z = x11622 z = x11623 z = x11624 z = x11625 z = x11626 z = x11627 z = x11628 z = x11629 z = x11630 z = x11631 z = x11632 z = x11633 z = x11634 z = x11635 z = x11636 z = x11637 z = x11638 z = x11639 z = x11640 z = x11641 z = x11642 z = x11643 z = x11644 z = x11645 z = x11646 z = x11647 z = x11648 z = x11649 z = x11650 z = x11651 z = x11652 z = x11653 z = x11654 z = x11655 z = x11656 z = x11657 z = x11658 z = x11659 z = x11660 z = x11661 z = x11662 z = x11663 z = x11664 z = x11665 z = x11666 z = x11667 z = x11668 z = x11669 z = x11670 z = x11671 z = x11672 z = x11673 z = x11674 z = x11675 z = x11676 z = x11677 z = x11678 z = x11679 z = x11680 z = x11681 z = x11682 z = x11683 z = x11684 z = x11685 z = x11686 z = x11687 z = x11688 z = x11689 z = x11690 z = x11691 z = x11692 z = x11693 z = x11694 z = x11695 z = x11696 z = x11697 z = x11698 z = x11699 z = x11700 z = x11701 z = x11702 z = x11703 z = x11704 z = x11705 z = x11706 z = x11707 z = x11708 z = x11709 z = x11710 z = x11711 z = x11712 z = x11713 z = x11714 z = x11715 z = x11716 z = x11717 z = x11718 z = x11719 z = x11720 z = x11721 z = x11722 z = x11723 z = x11724 z = x11725 z = x11726 z = x11727 z = x11728 z = x11729 z = x11730 z = x11731 z = x11732 z = x11733 z = x11734 z = x11735 z = x11736 z = x11737 z = x11738 z = x11739 z = x11740 z = x11741 z = x11742 z = x11743 z = x11744 z = x11745 z = x11746 z = x11747 z = x11748 z = x11749 z = x11750 z = x11751 z = x11752 z = x11753 z = x11754 z = x11755 z = x11756 z = x11757 z = x11758 z = x11759 z = x11760 z = x11761 z = x11762 z = x11763 z = x11764 z = x11765 z = x11766 z = x11767 z = x11768 z = x11769 z = x11770 z = x11771 z = x11772 z = x11773 z = x11774 z = x11775 z = x11776 z = x11777 z = x11778 z = x11779 z = x11780 z = x11781 z = x11782 z = x11783 z = x11784 z = x11785 z = x11786 z = x11787 z = x11788 z = x11789 z = x11790 z = x11791 z = x11792 z = x11793 z = x11794 z = x11795 z = x11796 z = x11797 z = x11798 z = x11799 z = x11800 z = x11801 z = x11802 z = x11803 z = x11804 z = x11805 z = x11806 z = x11807 z = x11808 z = x11809 z = x11810 z = x11811 z = x11812 z = x11813 z = x11814 z = x11815 z = x11816 z = x11817 z = x11818 z = x11819 z = x11820 z = x11821 z = x11822 z = x11823 z = x11824 z = x11825 z = x11826 z = x11827 z = x11828 z = x11829 z = x11830 z = x11831 z = x11832 z = x11833 z = x11834 z = x11835 z = x11836 z = x11837 z = x11838 z = x11839 z = x11840 z = x11841 z = x11842 z = x11843 z = x11844 z = x11845 z = x11846 z = x11847 z = x11848 z = x11849 z = x11850 z = x11851 z = x11852 z = x11853 z = x11854 z = x11855 z = x11856 z = x11857 z = x11858 z = x11859 z = x11860 z = x11861 z = x11862 z = x11863 z = x11864 z = x11865 z = x11866 z = x11867 z = x11868 z = x11869 z = x11870 z = x11871 z = x11872 z = x11873 z = x11874 z = x11875 z = x11876 z = x11877 z = x11878 z = x11879 z = x11880 z = x11881 z = x11882 z = x11883 z = x11884 z = x11885 z = x11886 z = x11887 z = x11888 z = x11889 z = x11890 z = x11891 z = x11892 z = x11893 z = x11894 z = x11895 z = x11896 z = x11897 z = x11898 z = x11899 z = x11900 z = x11901 z = x11902 z = x11903 z = x11904 z = x11905 z = x11906 z = x11907 z = x11908 z = x11909 z = x11910 z = x11911 z = x11912 z = x11913 z = x11914 z = x11915 z = x11916 z = x11917 z = x11918 z = x11919 z = x11920 z = x11921 z = x11922 z = x11923 z = x11924 z = x11925 z = x11926 z = x11927 z = x11928 z = x11929 z = x11930 z = x11931 z = x11932 z = x11933 z = x11934 z = x11935 z = x11936 z = x11937 z = x11938 z = x11939 z = x11940 z = x11941 z = x11942 z = x11943 z = x11944 z = x11945 z = x11946 z = x11947 z = x11948 z = x11949 z = x11950 z = x11951 z = x11952 z = x11953 z = x11954 z = x11955 z = x11956 z = x11957 z = x11958 z = x11959 z = x11960 z = x11961 z = x11962 z = x11963 z = x11964 z = x11965 z = x11966 z = x11967 z = x11968 z = x11969 z = x11970 z = x11971 z = x11972 z = x11973 z = x11974 z = x11975 z = x11976 z = x11977 z = x11978 z = x11979 z = x11980 z = x11981 z = x11982 z = x11983 z = x11984 z = x11985 z = x11986 z = x11987 z = x11988 z = x11989 z = x11990 z = x11991 z = x11992 z = x11993 z = x11994 z = x11995 z = x11996 z = x11997 z = x11998 z = x11999 z = x12000 z = x12001 z = x12002 z = x12003 z = x12004 z = x12005 z = x12006 z = x12007 z = x12008 z = x12009 z = x12010 z = x12011 z = x12012 z = x12013 z = x12014 z = x12015 z = x12016 z = x12017 z = x12018 z = x12019 z = x12020 z = x12021 z = x12022 z = x12023 z = x12024 z = x12025 z = x12026 z = x12027 z = x12028 z = x12029 z = x12030 z = x12031 z = x12032 z = x12033 z = x12034 z = x12035 z = x12036 z = x12037 z = x12038 z = x12039 z = x12040 z = x12041 z = x12042 z = x12043 z = x12044 z = x12045 z = x12046 z = x12047 z = x12048 z = x12049 z = x12050 z = x12051 z = x12052 z = x12053 z = x12054 z = x12055 z = x12056 z = x12057 z = x12058 z = x12059 z = x12060 z = x12061 z = x12062 z = x12063 z = x12064 z = x12065 z = x12066 z = x12067 z = x12068 z = x12069 z = x12070 z = x12071 z = x12072 z = x12073 z = x12074 z = x12075 z = x12076 z = x12077 z = x12078 z = x12079 z = x12080 z = x12081 z = x12082 z = x12083 z = x12084 z = x12085 z = x12086 z = x12087 z = x12088 z = x12089 z = x12090 z = x12091 z = x12092 z = x12093 z = x12094 z = x12095 z = x12096 z = x12097 z = x12098 z = x12099 z = x12100 z = x12101 z = x12102 z = x12103 z = x12104 z = x12105 z = x12106 z = x12107 z = x12108 z = x12109 z = x12110 z = x12111 z = x12112 z = x12113 z = x12114 z = x12115 z = x12116 z = x12117 z = x12118 z = x12119 z = x12120 z = x12121 z = x12122 z = x12123 z = x12124 z = x12125 z = x12126 z = x12127 z = x12128 z = x12129 z = x12130 z = x12131 z = x12132 z = x12133 z = x12134 z = x12135 z = x12136 z = x12137 z = x12138 z = x12139 z = x12140 z = x12141 z = x12142 z = x12143 z = x12144 z = x12145 z = x12146 z = x12147 z = x12148 z = x12149 z = x12150 z = x12151 z = x12152 z = x12153 z = x12154 z = x12155 z = x12156 z = x12157 z = x12158 z = x12159 z = x12160 z = x12161 z = x12162 z = x12163 z = x12164 z = x12165 z = x12166 z = x12167 z = x12168 z = x12169 z = x12170 z = x12171 z = x12172 z = x12173 z = x12174 z = x12175 z = x12176 z = x12177 z = x12178 z = x12179 z = x12180 z = x12181 z = x12182 z = x12183 z = x12184 z = x12185 z = x12186 z = x12187 z = x12188 z = x12189 z = x12190 z = x12191 z = x12192 z = x12193 z = x12194 z = x12195 z = x12196 z = x12197 z = x12198 z = x12199 z = x12200 z = x12201 z = x12202 z = x12203 z = x12204 z = x12205 z = x12206 z = x12207 z = x12208 z = x12209 z = x12210 z = x12211 z = x12212 z = x12213 z = x12214 z = x12215 z = x12216 z = x12217 z = x12218 z = x12219 z = x12220 z = x12221 z = x12222 z = x12223 z = x12224 z = x12225 z = x12226 z = x12227 z = x12228 z = x12229 z = x12230 z = x12231 z = x12232 z = x12233 z = x12234 z = x12235 z = x12236 z = x12237 z = x12238 z = x12239 z = x12240 z = x12241 z = x12242 z = x12243 z = x12244 z = x12245 z = x12246 z = x12247 z = x12248 z = x12249 z = x12250 z = x12251 z = x12252 z = x12253 z = x12254 z = x12255 z = x12256 z = x12257 z = x12258 z = x12259 z = x12260 z = x12261 z = x12262 z = x12263 z = x12264 z = x12265 z = x12266 z = x12267 z = x12268 z = x12269 z = x12270 z = x12271 z = x12272 z = x12273 z = x12274 z = x12275 z = x12276 z = x12277 z = x12278 z = x12279 z = x12280 z = x12281 z = x12282 z = x12283 z = x12284 z = x12285 z = x12286 z = x12287 z = x12288 z = x12289 z = x12290 z = x12291 z = x12292 z = x12293 z = x12294 z = x12295 z = x12296 z = x12297 z = x12298 z = x12299 z = x12300 z = x12301 z = x12302 z = x12303 z = x12304 z = x12305 z = x12306 z = x12307 z = x12308 z = x12309 z = x12310 z = x12311 z = x12312 z = x12313 z = x12314 z = x12315 z = x12316 z = x12317 z = x12318 z = x12319 z = x12320 z = x12321 z = x12322 z = x12323 z = x12324 z = x12325 z = x12326 z = x12327 z = x12328 z = x12329 z = x12330 z = x12331 z = x12332 z = x12333 z = x12334 z = x12335 z = x12336 z = x12337 z = x12338 z = x12339 z = x12340 z = x12341 z = x12342 z = x12343 z = x12344 z = x12345 z = x12346 z = x12347 z = x12348 z = x12349 z = x12350 z = x12351 z = x12352 z = x12353 z = x12354 z = x12355 z = x12356 z = x12357 z = x12358 z = x12359 z = x12360 z = x12361 z = x12362 z = x12363 z = x12364 z = x12365 z = x12366 z = x12367 z = x12368 z = x12369 z = x12370 z = x12371 z = x12372 z = x12373 z = x12374 z = x12375 z = x12376 z = x12377 z = x12378 z = x12379 z = x12380 z = x12381 z = x12382 z = x12383 z = x12384 z = x12385 z = x12386 z = x12387 z = x12388 z = x12389 z = x12390 z = x12391 z = x12392 z = x12393 z = x12394 z = x12395 z = x12396 z = x12397 z = x12398 z = x12399 z = x12400 z = x12401 z = x12402 z = x12403 z = x12404 z = x12405 z = x12406 z = x12407 z = x12408 z = x12409 z = x12410 z = x12411 z = x12412 z = x12413 z = x12414 z = x12415 z = x12416 z = x12417 z = x12418 z = x12419 z = x12420 z = x12421 z = x12422 z = x12423 z = x12424 z = x12425 z = x12426 z = x12427 z = x12428 z = x12429 z = x12430 z = x12431 z = x12432 z = x12433 z = x12434 z = x12435 z = x12436 z = x12437 z = x12438 z = x12439 z = x12440 z = x12441 z = x12442 z = x12443 z = x12444 z = x12445 z = x12446 z = x12447 z = x12448 z = x12449 z = x12450 z = x12451 z = x12452 z = x12453 z = x12454 z = x12455 z = x12456 z = x12457 z = x12458 z = x12459 z = x12460 z = x12461 z = x12462 z = x12463 z = x12464 z = x12465 z = x12466 z = x12467 z = x12468 z = x12469 z = x12470 z = x12471 z = x12472 z = x12473 z = x12474 z = x12475 z = x12476 z = x12477 z = x12478 z = x12479 z = x12480 z = x12481 z = x12482 z = x12483 z = x12484 z = x12485 z = x12486 z = x12487 z = x12488 z = x12489 z = x12490 z = x12491 z = x12492 z = x12493 z = x12494 z = x12495 z = x12496 z = x12497 z = x12498 z = x12499 z = x12500 z = x12501 z = x12502 z = x12503 z = x12504 z = x12505 z = x12506 z = x12507 z = x12508 z = x12509 z = x12510 z = x12511 z = x12512 z = x12513 z = x12514 z = x12515 z = x12516 z = x12517 z = x12518 z = x12519 z = x12520 z = x12521 z = x12522 z = x12523 z = x12524 z = x12525 z = x12526 z = x12527 z = x12528 z = x12529 z = x12530 z = x12531 z = x12532 z = x12533 z = x12534 z = x12535 z = x12536 z = x12537 z = x12538 z = x12539 z = x12540 z = x12541 z = x12542 z = x12543 z = x12544 z = x12545 z = x12546 z = x12547 z = x12548 z = x12549 z = x12550 z = x12551 z = x12552 z = x12553 z = x12554 z = x12555 z = x12556 z = x12557 z = x12558 z = x12559 z = x12560 z = x12561 z = x12562 z = x12563 z = x12564 z = x12565 z = x12566 z = x12567 z = x12568 z = x12569 z = x12570 z = x12571 z = x12572 z = x12573 z = x12574 z = x12575 z = x12576 z = x12577 z = x12578 z = x12579 z = x12580 z = x12581 z = x12582 z = x12583 z = x12584 z = x12585 z = x12586 z = x12587 z = x12588 z = x12589 z = x12590 z = x12591 z = x12592 z = x12593 z = x12594 z = x12595 z = x12596 z = x12597 z = x12598 z = x12599 z = x12600 z = x12601 z = x12602 z = x12603 z = x12604 z = x12605 z = x12606 z = x12607 z = x12608 z = x12609 z = x12610 z = x12611 z = x12612 z = x12613 z = x12614 z = x12615 z = x12616 z = x12617 z = x12618 z = x12619 z = x12620 z = x12621 z = x12622 z = x12623 z = x12624 z = x12625 z = x12626 z = x12627 z = x12628 z = x12629 z = x12630 z = x12631 z = x12632 z = x12633 z = x12634 z = x12635 z = x12636 z = x12637 z = x12638 z = x12639 z = x12640 z = x12641 z = x12642 z = x12643 z = x12644 z = x12645 z = x12646 z = x12647 z = x12648 z = x12649 z = x12650 z = x12651 z = x12652 z = x12653 z = x12654 z = x12655 z = x12656 z = x12657 z = x12658 z = x12659 z = x12660 z = x12661 z = x12662 z = x12663 z = x12664 z = x12665 z = x12666 z = x12667 z = x12668 z = x12669 z = x12670 z = x12671 z = x12672 z = x12673 z = x12674 z = x12675 z = x12676 z = x12677 z = x12678 z = x12679 z = x12680 z = x12681 z = x12682 z = x12683 z = x12684 z = x12685 z = x12686 z = x12687 z = x12688 z = x12689 z = x12690 z = x12691 z = x12692 z = x12693 z = x12694 z = x12695 z = x12696 z = x12697 z = x12698 z = x12699 z = x12700 z = x12701 z = x12702 z = x12703 z = x12704 z = x12705 z = x12706 z = x12707 z = x12708 z = x12709 z = x12710 z = x12711 z = x12712 z = x12713 z = x12714 z = x12715 z = x12716 z = x12717 z = x12718 z = x12719 z = x12720 z = x12721 z = x12722 z = x12723 z = x12724 z = x12725 z = x12726 z = x12727 z = x12728 z = x12729 z = x12730 z = x12731 z = x12732 z = x12733 z = x12734 z = x12735 z = x12736 z = x12737 z = x12738 z = x12739 z = x12740 z = x12741 z = x12742 z = x12743 z = x12744 z = x12745 z = x12746 z = x12747 z = x12748 z = x12749 z = x12750 z = x12751 z = x12752 z = x12753 z = x12754 z = x12755 z = x12756 z = x12757 z = x12758 z = x12759 z = x12760 z = x12761 z = x12762 z = x12763 z = x12764 z = x12765 z = x12766 z = x12767 z = x12768 z = x12769 z = x12770 z = x12771 z = x12772 z = x12773 z = x12774 z = x12775 z = x12776 z = x12777 z = x12778 z = x12779 z = x12780 z = x12781 z = x12782 z = x12783 z = x12784 z = x12785 z = x12786 z = x12787 z = x12788 z = x12789 z = x12790 z = x12791 z = x12792 z = x12793 z = x12794 z = x12795 z = x12796 z = x12797 z = x12798 z = x12799 z = x12800 z = x12801 z = x12802 z = x12803 z = x12804 z = x12805 z = x12806 z = x12807 z = x12808 z = x12809 z = x12810 z = x12811 z = x12812 z = x12813 z = x12814 z = x12815 z = x12816 z = x12817 z = x12818 z = x12819 z = x12820 z = x12821 z = x12822 z = x12823 z = x12824 z = x12825 z = x12826 z = x12827 z = x12828 z = x12829 z = x12830 z = x12831 z = x12832 z = x12833 z = x12834 z = x12835 z = x12836 z = x12837 z = x12838 z = x12839 z = x12840 z = x12841 z = x12842 z = x12843 z = x12844 z = x12845 z = x12846 z = x12847 z = x12848 z = x12849 z = x12850 z = x12851 z = x12852 z = x12853 z = x12854 z = x12855 z = x12856 z = x12857 z = x12858 z = x12859 z = x12860 z = x12861 z = x12862 z = x12863 z = x12864 z = x12865 z = x12866 z = x12867 z = x12868 z = x12869 z = x12870 z = x12871 z = x12872 z = x12873 z = x12874 z = x12875 z = x12876 z = x12877 z = x12878 z = x12879 z = x12880 z = x12881 z = x12882 z = x12883 z = x12884 z = x12885 z = x12886 z = x12887 z = x12888 z = x12889 z = x12890 z = x12891 z = x12892 z = x12893 z = x12894 z = x12895 z = x12896 z = x12897 z = x12898 z = x12899 z = x12900 z = x12901 z = x12902 z = x12903 z = x12904 z = x12905 z = x12906 z = x12907 z = x12908 z = x12909 z = x12910 z = x12911 z = x12912 z = x12913 z = x12914 z = x12915 z = x12916 z = x12917 z = x12918 z = x12919 z = x12920 z = x12921 z = x12922 z = x12923 z = x12924 z = x12925 z = x12926 z = x12927 z = x12928 z = x12929 z = x12930 z = x12931 z = x12932 z = x12933 z = x12934 z = x12935 z = x12936 z = x12937 z = x12938 z = x12939 z = x12940 z = x12941 z = x12942 z = x12943 z = x12944 z = x12945 z = x12946 z = x12947 z = x12948 z = x12949 z = x12950 z = x12951 z = x12952 z = x12953 z = x12954 z = x12955 z = x12956 z = x12957 z = x12958 z = x12959 z = x12960 z = x12961 z = x12962 z = x12963 z = x12964 z = x12965 z = x12966 z = x12967 z = x12968 z = x12969 z = x12970 z = x12971 z = x12972 z = x12973 z = x12974 z = x12975 z = x12976 z = x12977 z = x12978 z = x12979 z = x12980 z = x12981 z = x12982 z = x12983 z = x12984 z = x12985 z = x12986 z = x12987 z = x12988 z = x12989 z = x12990 z = x12991 z = x12992 z = x12993 z = x12994 z = x12995 z = x12996 z = x12997 z = x12998 z = x12999 z = x13000 z = x13001 z = x13002 z = x13003 z = x13004 z = x13005 z = x13006 z = x13007 z = x13008 z = x13009 z = x13010 z = x13011 z = x13012 z = x13013 z = x13014 z = x13015 z = x13016 z = x13017 z = x13018 z = x13019 z = x13020 z = x13021 z = x13022 z = x13023 z = x13024 z = x13025 z = x13026 z = x13027 z = x13028 z = x13029 z = x13030 z = x13031 z = x13032 z = x13033 z = x13034 z = x13035 z = x13036 z = x13037 z = x13038 z = x13039 z = x13040 z = x13041 z = x13042 z = x13043 z = x13044 z = x13045 z = x13046 z = x13047 z = x13048 z = x13049 z = x13050 z = x13051 z = x13052 z = x13053 z = x13054 z = x13055 z = x13056 z = x13057 z = x13058 z = x13059 z = x13060 z = x13061 z = x13062 z = x13063 z = x13064 z = x13065 z = x13066 z = x13067 z = x13068 z = x13069 z = x13070 z = x13071 z = x13072 z = x13073 z = x13074 z = x13075 z = x13076 z = x13077 z = x13078 z = x13079 z = x13080 z = x13081 z = x13082 z = x13083 z = x13084 z = x13085 z = x13086 z = x13087 z = x13088 z = x13089 z = x13090 z = x13091 z = x13092 z = x13093 z = x13094 z = x13095 z = x13096 z = x13097 z = x13098 z = x13099 z = x13100 z = x13101 z = x13102 z = x13103 z = x13104 z = x13105 z = x13106 z = x13107 z = x13108 z = x13109 z = x13110 z = x13111 z = x13112 z = x13113 z = x13114 z = x13115 z = x13116 z = x13117 z = x13118 z = x13119 z = x13120 z = x13121 z = x13122 z = x13123 z = x13124 z = x13125 z = x13126 z = x13127 z = x13128 z = x13129 z = x13130 z = x13131 z = x13132 z = x13133 z = x13134 z = x13135 z = x13136 z = x13137 z = x13138 z = x13139 z = x13140 z = x13141 z = x13142 z = x13143 z = x13144 z = x13145 z = x13146 z = x13147 z = x13148 z = x13149 z = x13150 z = x13151 z = x13152 z = x13153 z = x13154 z = x13155 z = x13156 z = x13157 z = x13158 z = x13159 z = x13160 z = x13161 z = x13162 z = x13163 z = x13164 z = x13165 z = x13166 z = x13167 z = x13168 z = x13169 z = x13170 z = x13171 z = x13172 z = x13173 z = x13174 z = x13175 z = x13176 z = x13177 z = x13178 z = x13179 z = x13180 z = x13181 z = x13182 z = x13183 z = x13184 z = x13185 z = x13186 z = x13187 z = x13188 z = x13189 z = x13190 z = x13191 z = x13192 z = x13193 z = x13194 z = x13195 z = x13196 z = x13197 z = x13198 z = x13199 z = x13200 z = x13201 z = x13202 z = x13203 z = x13204 z = x13205 z = x13206 z = x13207 z = x13208 z = x13209 z = x13210 z = x13211 z = x13212 z = x13213 z = x13214 z = x13215 z = x13216 z = x13217 z = x13218 z = x13219 z = x13220 z = x13221 z = x13222 z = x13223 z = x13224 z = x13225 z = x13226 z = x13227 z = x13228 z = x13229 z = x13230 z = x13231 z = x13232 z = x13233 z = x13234 z = x13235 z = x13236 z = x13237 z = x13238 z = x13239 z = x13240 z = x13241 z = x13242 z = x13243 z = x13244 z = x13245 z = x13246 z = x13247 z = x13248 z = x13249 z = x13250 z = x13251 z = x13252 z = x13253 z = x13254 z = x13255 z = x13256 z = x13257 z = x13258 z = x13259 z = x13260 z = x13261 z = x13262 z = x13263 z = x13264 z = x13265 z = x13266 z = x13267 z = x13268 z = x13269 z = x13270 z = x13271 z = x13272 z = x13273 z = x13274 z = x13275 z = x13276 z = x13277 z = x13278 z = x13279 z = x13280 z = x13281 z = x13282 z = x13283 z = x13284 z = x13285 z = x13286 z = x13287 z = x13288 z = x13289 z = x13290 z = x13291 z = x13292 z = x13293 z = x13294 z = x13295 z = x13296 z = x13297 z = x13298 z = x13299 z = x13300 z = x13301 z = x13302 z = x13303 z = x13304 z = x13305 z = x13306 z = x13307 z = x13308 z = x13309 z = x13310 z = x13311 z = x13312 z = x13313 z = x13314 z = x13315 z = x13316 z = x13317 z = x13318 z = x13319 z = x13320 z = x13321 z = x13322 z = x13323 z = x13324 z = x13325 z = x13326 z = x13327 z = x13328 z = x13329 z = x13330 z = x13331 z = x13332 z = x13333 z = x13334 z = x13335 z = x13336 z = x13337 z = x13338 z = x13339 z = x13340 z = x13341 z = x13342 z = x13343 z = x13344 z = x13345 z = x13346 z = x13347 z = x13348 z = x13349 z = x13350 z = x13351 z = x13352 z = x13353 z = x13354 z = x13355 z = x13356 z = x13357 z = x13358 z = x13359 z = x13360 z = x13361 z = x13362 z = x13363 z = x13364 z = x13365 z = x13366 z = x13367 z = x13368 z = x13369 z = x13370 z = x13371 z = x13372 z = x13373 z = x13374 z = x13375 z = x13376 z = x13377 z = x13378 z = x13379 z = x13380 z = x13381 z = x13382 z = x13383 z = x13384 z = x13385 z = x13386 z = x13387 z = x13388 z = x13389 z = x13390 z = x13391 z = x13392 z = x13393 z = x13394 z = x13395 z = x13396 z = x13397 z = x13398 z = x13399 z = x13400 z = x13401 z = x13402 z = x13403 z = x13404 z = x13405 z = x13406 z = x13407 z = x13408 z = x13409 z = x13410 z = x13411 z = x13412 z = x13413 z = x13414 z = x13415 z = x13416 z = x13417 z = x13418 z = x13419 z = x13420 z = x13421 z = x13422 z = x13423 z = x13424 z = x13425 z = x13426 z = x13427 z = x13428 z = x13429 z = x13430 z = x13431 z = x13432 z = x13433 z = x13434 z = x13435 z = x13436 z = x13437 z = x13438 z = x13439 z = x13440 z = x13441 z = x13442 z = x13443 z = x13444 z = x13445 z = x13446 z = x13447 z = x13448 z = x13449 z = x13450 z = x13451 z = x13452 z = x13453 z = x13454 z = x13455 z = x13456 z = x13457 z = x13458 z = x13459 z = x13460 z = x13461 z = x13462 z = x13463 z = x13464 z = x13465 z = x13466 z = x13467 z = x13468 z = x13469 z = x13470 z = x13471 z = x13472 z = x13473 z = x13474 z = x13475 z = x13476 z = x13477 z = x13478 z = x13479 z = x13480 z = x13481 z = x13482 z = x13483 z = x13484 z = x13485 z = x13486 z = x13487 z = x13488 z = x13489 z = x13490 z = x13491 z = x13492 z = x13493 z = x13494 z = x13495 z = x13496 z = x13497 z = x13498 z = x13499 z = x13500 z = x13501 z = x13502 z = x13503 z = x13504 z = x13505 z = x13506 z = x13507 z = x13508 z = x13509 z = x13510 z = x13511 z = x13512 z = x13513 z = x13514 z = x13515 z = x13516 z = x13517 z = x13518 z = x13519 z = x13520 z = x13521 z = x13522 z = x13523 z = x13524 z = x13525 z = x13526 z = x13527 z = x13528 z = x13529 z = x13530 z = x13531 z = x13532 z = x13533 z = x13534 z = x13535 z = x13536 z = x13537 z = x13538 z = x13539 z = x13540 z = x13541 z = x13542 z = x13543 z = x13544 z = x13545 z = x13546 z = x13547 z = x13548 z = x13549 z = x13550 z = x13551 z = x13552 z = x13553 z = x13554 z = x13555 z = x13556 z = x13557 z = x13558 z = x13559 z = x13560 z = x13561 z = x13562 z = x13563 z = x13564 z = x13565 z = x13566 z = x13567 z = x13568 z = x13569 z = x13570 z = x13571 z = x13572 z = x13573 z = x13574 z = x13575 z = x13576 z = x13577 z = x13578 z = x13579 z = x13580 z = x13581 z = x13582 z = x13583 z = x13584 z = x13585 z = x13586 z = x13587 z = x13588 z = x13589 z = x13590 z = x13591 z = x13592 z = x13593 z = x13594 z = x13595 z = x13596 z = x13597 z = x13598 z = x13599 z = x13600 z = x13601 z = x13602 z = x13603 z = x13604 z = x13605 z = x13606 z = x13607 z = x13608 z = x13609 z = x13610 z = x13611 z = x13612 z = x13613 z = x13614 z = x13615 z = x13616 z = x13617 z = x13618 z = x13619 z = x13620 z = x13621 z = x13622 z = x13623 z = x13624 z = x13625 z = x13626 z = x13627 z = x13628 z = x13629 z = x13630 z = x13631 z = x13632 z = x13633 z = x13634 z = x13635 z = x13636 z = x13637 z = x13638 z = x13639 z = x13640 z = x13641 z = x13642 z = x13643 z = x13644 z = x13645 z = x13646 z = x13647 z = x13648 z = x13649 z = x13650 z = x13651 z = x13652 z = x13653 z = x13654 z = x13655 z = x13656 z = x13657 z = x13658 z = x13659 z = x13660 z = x13661 z = x13662 z = x13663 z = x13664 z = x13665 z = x13666 z = x13667 z = x13668 z = x13669 z = x13670 z = x13671 z = x13672 z = x13673 z = x13674 z = x13675 z = x13676 z = x13677 z = x13678 z = x13679 z = x13680 z = x13681 z = x13682 z = x13683 z = x13684 z = x13685 z = x13686 z = x13687 z = x13688 z = x13689 z = x13690 z = x13691 z = x13692 z = x13693 z = x13694 z = x13695 z = x13696 z = x13697 z = x13698 z = x13699 z = x13700 z = x13701 z = x13702 z = x13703 z = x13704 z = x13705 z = x13706 z = x13707 z = x13708 z = x13709 z = x13710 z = x13711 z = x13712 z = x13713 z = x13714 z = x13715 z = x13716 z = x13717 z = x13718 z = x13719 z = x13720 z = x13721 z = x13722 z = x13723 z = x13724 z = x13725 z = x13726 z = x13727 z = x13728 z = x13729 z = x13730 z = x13731 z = x13732 z = x13733 z = x13734 z = x13735 z = x13736 z = x13737 z = x13738 z = x13739 z = x13740 z = x13741 z = x13742 z = x13743 z = x13744 z = x13745 z = x13746 z = x13747 z = x13748 z = x13749 z = x13750 z = x13751 z = x13752 z = x13753 z = x13754 z = x13755 z = x13756 z = x13757 z = x13758 z = x13759 z = x13760 z = x13761 z = x13762 z = x13763 z = x13764 z = x13765 z = x13766 z = x13767 z = x13768 z = x13769 z = x13770 z = x13771 z = x13772 z = x13773 z = x13774 z = x13775 z = x13776 z = x13777 z = x13778 z = x13779 z = x13780 z = x13781 z = x13782 z = x13783 z = x13784 z = x13785 z = x13786 z = x13787 z = x13788 z = x13789 z = x13790 z = x13791 z = x13792 z = x13793 z = x13794 z = x13795 z = x13796 z = x13797 z = x13798 z = x13799 z = x13800 z = x13801 z = x13802 z = x13803 z = x13804 z = x13805 z = x13806 z = x13807 z = x13808 z = x13809 z = x13810 z = x13811 z = x13812 z = x13813 z = x13814 z = x13815 z = x13816 z = x13817 z = x13818 z = x13819 z = x13820 z = x13821 z = x13822 z = x13823 z = x13824 z = x13825 z = x13826 z = x13827 z = x13828 z = x13829 z = x13830 z = x13831 z = x13832 z = x13833 z = x13834 z = x13835 z = x13836 z = x13837 z = x13838 z = x13839 z = x13840 z = x13841 z = x13842 z = x13843 z = x13844 z = x13845 z = x13846 z = x13847 z = x13848 z = x13849 z = x13850 z = x13851 z = x13852 z = x13853 z = x13854 z = x13855 z = x13856 z = x13857 z = x13858 z = x13859 z = x13860 z = x13861 z = x13862 z = x13863 z = x13864 z = x13865 z = x13866 z = x13867 z = x13868 z = x13869 z = x13870 z = x13871 z = x13872 z = x13873 z = x13874 z = x13875 z = x13876 z = x13877 z = x13878 z = x13879 z = x13880 z = x13881 z = x13882 z = x13883 z = x13884 z = x13885 z = x13886 z = x13887 z = x13888 z = x13889 z = x13890 z = x13891 z = x13892 z = x13893 z = x13894 z = x13895 z = x13896 z = x13897 z = x13898 z = x13899 z = x13900 z = x13901 z = x13902 z = x13903 z = x13904 z = x13905 z = x13906 z = x13907 z = x13908 z = x13909 z = x13910 z = x13911 z = x13912 z = x13913 z = x13914 z = x13915 z = x13916 z = x13917 z = x13918 z = x13919 z = x13920 z = x13921 z = x13922 z = x13923 z = x13924 z = x13925 z = x13926 z = x13927 z = x13928 z = x13929 z = x13930 z = x13931 z = x13932 z = x13933 z = x13934 z = x13935 z = x13936 z = x13937 z = x13938 z = x13939 z = x13940 z = x13941 z = x13942 z = x13943 z = x13944 z = x13945 z = x13946 z = x13947 z = x13948 z = x13949 z = x13950 z = x13951 z = x13952 z = x13953 z = x13954 z = x13955 z = x13956 z = x13957 z = x13958 z = x13959 z = x13960 z = x13961 z = x13962 z = x13963 z = x13964 z = x13965 z = x13966 z = x13967 z = x13968 z = x13969 z = x13970 z = x13971 z = x13972 z = x13973 z = x13974 z = x13975 z = x13976 z = x13977 z = x13978 z = x13979 z = x13980 z = x13981 z = x13982 z = x13983 z = x13984 z = x13985 z = x13986 z = x13987 z = x13988 z = x13989 z = x13990 z = x13991 z = x13992 z = x13993 z = x13994 z = x13995 z = x13996 z = x13997 z = x13998 z = x13999 z = x14000 z = x14001 z = x14002 z = x14003 z = x14004 z = x14005 z = x14006 z = x14007 z = x14008 z = x14009 z = x14010 z = x14011 z = x14012 z = x14013 z = x14014 z = x14015 z = x14016 z = x14017 z = x14018 z = x14019 z = x14020 z = x14021 z = x14022 z = x14023 z = x14024 z = x14025 z = x14026 z = x14027 z = x14028 z = x14029 z = x14030 z = x14031 z = x14032 z = x14033 z = x14034 z = x14035 z = x14036 z = x14037 z = x14038 z = x14039 z = x14040 z = x14041 z = x14042 z = x14043 z = x14044 z = x14045 z = x14046 z = x14047 z = x14048 z = x14049 z = x14050 z = x14051 z = x14052 z = x14053 z = x14054 z = x14055 z = x14056 z = x14057 z = x14058 z = x14059 z = x14060 z = x14061 z = x14062 z = x14063 z = x14064 z = x14065 z = x14066 z = x14067 z = x14068 z = x14069 z = x14070 z = x14071 z = x14072 z = x14073 z = x14074 z = x14075 z = x14076 z = x14077 z = x14078 z = x14079 z = x14080 z = x14081 z = x14082 z = x14083 z = x14084 z = x14085 z = x14086 z = x14087 z = x14088 z = x14089 z = x14090 z = x14091 z = x14092 z = x14093 z = x14094 z = x14095 z = x14096 z = x14097 z = x14098 z = x14099 z = x14100 z = x14101 z = x14102 z = x14103 z = x14104 z = x14105 z = x14106 z = x14107 z = x14108 z = x14109 z = x14110 z = x14111 z = x14112 z = x14113 z = x14114 z = x14115 z = x14116 z = x14117 z = x14118 z = x14119 z = x14120 z = x14121 z = x14122 z = x14123 z = x14124 z = x14125 z = x14126 z = x14127 z = x14128 z = x14129 z = x14130 z = x14131 z = x14132 z = x14133 z = x14134 z = x14135 z = x14136 z = x14137 z = x14138 z = x14139 z = x14140 z = x14141 z = x14142 z = x14143 z = x14144 z = x14145 z = x14146 z = x14147 z = x14148 z = x14149 z = x14150 z = x14151 z = x14152 z = x14153 z = x14154 z = x14155 z = x14156 z = x14157 z = x14158 z = x14159 z = x14160 z = x14161 z = x14162 z = x14163 z = x14164 z = x14165 z = x14166 z = x14167 z = x14168 z = x14169 z = x14170 z = x14171 z = x14172 z = x14173 z = x14174 z = x14175 z = x14176 z = x14177 z = x14178 z = x14179 z = x14180 z = x14181 z = x14182 z = x14183 z = x14184 z = x14185 z = x14186 z = x14187 z = x14188 z = x14189 z = x14190 z = x14191 z = x14192 z = x14193 z = x14194 z = x14195 z = x14196 z = x14197 z = x14198 z = x14199 z = x14200 z = x14201 z = x14202 z = x14203 z = x14204 z = x14205 z = x14206 z = x14207 z = x14208 z = x14209 z = x14210 z = x14211 z = x14212 z = x14213 z = x14214 z = x14215 z = x14216 z = x14217 z = x14218 z = x14219 z = x14220 z = x14221 z = x14222 z = x14223 z = x14224 z = x14225 z = x14226 z = x14227 z = x14228 z = x14229 z = x14230 z = x14231 z = x14232 z = x14233 z = x14234 z = x14235 z = x14236 z = x14237 z = x14238 z = x14239 z = x14240 z = x14241 z = x14242 z = x14243 z = x14244 z = x14245 z = x14246 z = x14247 z = x14248 z = x14249 z = x14250 z = x14251 z = x14252 z = x14253 z = x14254 z = x14255 z = x14256 z = x14257 z = x14258 z = x14259 z = x14260 z = x14261 z = x14262 z = x14263 z = x14264 z = x14265 z = x14266 z = x14267 z = x14268 z = x14269 z = x14270 z = x14271 z = x14272 z = x14273 z = x14274 z = x14275 z = x14276 z = x14277 z = x14278 z = x14279 z = x14280 z = x14281 z = x14282 z = x14283 z = x14284 z = x14285 z = x14286 z = x14287 z = x14288 z = x14289 z = x14290 z = x14291 z = x14292 z = x14293 z = x14294 z = x14295 z = x14296 z = x14297 z = x14298 z = x14299 z = x14300 z = x14301 z = x14302 z = x14303 z = x14304 z = x14305 z = x14306 z = x14307 z = x14308 z = x14309 z = x14310 z = x14311 z = x14312 z = x14313 z = x14314 z = x14315 z = x14316 z = x14317 z = x14318 z = x14319 z = x14320 z = x14321 z = x14322 z = x14323 z = x14324 z = x14325 z = x14326 z = x14327 z = x14328 z = x14329 z = x14330 z = x14331 z = x14332 z = x14333 z = x14334 z = x14335 z = x14336 z = x14337 z = x14338 z = x14339 z = x14340 z = x14341 z = x14342 z = x14343 z = x14344 z = x14345 z = x14346 z = x14347 z = x14348 z = x14349 z = x14350 z = x14351 z = x14352 z = x14353 z = x14354 z = x14355 z = x14356 z = x14357 z = x14358 z = x14359 z = x14360 z = x14361 z = x14362 z = x14363 z = x14364 z = x14365 z = x14366 z = x14367 z = x14368 z = x14369 z = x14370 z = x14371 z = x14372 z = x14373 z = x14374 z = x14375 z = x14376 z = x14377 z = x14378 z = x14379 z = x14380 z = x14381 z = x14382 z = x14383 z = x14384 z = x14385 z = x14386 z = x14387 z = x14388 z = x14389 z = x14390 z = x14391 z = x14392 z = x14393 z = x14394 z = x14395 z = x14396 z = x14397 z = x14398 z = x14399 z = x14400 z = x14401 z = x14402 z = x14403 z = x14404 z = x14405 z = x14406 z = x14407 z = x14408 z = x14409 z = x14410 z = x14411 z = x14412 z = x14413 z = x14414 z = x14415 z = x14416 z = x14417 z = x14418 z = x14419 z = x14420 z = x14421 z = x14422 z = x14423 z = x14424 z = x14425 z = x14426 z = x14427 z = x14428 z = x14429 z = x14430 z = x14431 z = x14432 z = x14433 z = x14434 z = x14435 z = x14436 z = x14437 z = x14438 z = x14439 z = x14440 z = x14441 z = x14442 z = x14443 z = x14444 z = x14445 z = x14446 z = x14447 z = x14448 z = x14449 z = x14450 z = x14451 z = x14452 z = x14453 z = x14454 z = x14455 z = x14456 z = x14457 z = x14458 z = x14459 z = x14460 z = x14461 z = x14462 z = x14463 z = x14464 z = x14465 z = x14466 z = x14467 z = x14468 z = x14469 z = x14470 z = x14471 z = x14472 z = x14473 z = x14474 z = x14475 z = x14476 z = x14477 z = x14478 z = x14479 z = x14480 z = x14481 z = x14482 z = x14483 z = x14484 z = x14485 z = x14486 z = x14487 z = x14488 z = x14489 z = x14490 z = x14491 z = x14492 z = x14493 z = x14494 z = x14495 z = x14496 z = x14497 z = x14498 z = x14499 z = x14500 z = x14501 z = x14502 z = x14503 z = x14504 z = x14505 z = x14506 z = x14507 z = x14508 z = x14509 z = x14510 z = x14511 z = x14512 z = x14513 z = x14514 z = x14515 z = x14516 z = x14517 z = x14518 z = x14519 z = x14520 z = x14521 z = x14522 z = x14523 z = x14524 z = x14525 z = x14526 z = x14527 z = x14528 z = x14529 z = x14530 z = x14531 z = x14532 z = x14533 z = x14534 z = x14535 z = x14536 z = x14537 z = x14538 z = x14539 z = x14540 z = x14541 z = x14542 z = x14543 z = x14544 z = x14545 z = x14546 z = x14547 z = x14548 z = x14549 z = x14550 z = x14551 z = x14552 z = x14553 z = x14554 z = x14555 z = x14556 z = x14557 z = x14558 z = x14559 z = x14560 z = x14561 z = x14562 z = x14563 z = x14564 z = x14565 z = x14566 z = x14567 z = x14568 z = x14569 z = x14570 z = x14571 z = x14572 z = x14573 z = x14574 z = x14575 z = x14576 z = x14577 z = x14578 z = x14579 z = x14580 z = x14581 z = x14582 z = x14583 z = x14584 z = x14585 z = x14586 z = x14587 z = x14588 z = x14589 z = x14590 z = x14591 z = x14592 z = x14593 z = x14594 z = x14595 z = x14596 z = x14597 z = x14598 z = x14599 z = x14600 z = x14601 z = x14602 z = x14603 z = x14604 z = x14605 z = x14606 z = x14607 z = x14608 z = x14609 z = x14610 z = x14611 z = x14612 z = x14613 z = x14614 z = x14615 z = x14616 z = x14617 z = x14618 z = x14619 z = x14620 z = x14621 z = x14622 z = x14623 z = x14624 z = x14625 z = x14626 z = x14627 z = x14628 z = x14629 z = x14630 z = x14631 z = x14632 z = x14633 z = x14634 z = x14635 z = x14636 z = x14637 z = x14638 z = x14639 z = x14640 z = x14641 z = x14642 z = x14643 z = x14644 z = x14645 z = x14646 z = x14647 z = x14648 z = x14649 z = x14650 z = x14651 z = x14652 z = x14653 z = x14654 z = x14655 z = x14656 z = x14657 z = x14658 z = x14659 z = x14660 z = x14661 z = x14662 z = x14663 z = x14664 z = x14665 z = x14666 z = x14667 z = x14668 z = x14669 z = x14670 z = x14671 z = x14672 z = x14673 z = x14674 z = x14675 z = x14676 z = x14677 z = x14678 z = x14679 z = x14680 z = x14681 z = x14682 z = x14683 z = x14684 z = x14685 z = x14686 z = x14687 z = x14688 z = x14689 z = x14690 z = x14691 z = x14692 z = x14693 z = x14694 z = x14695 z = x14696 z = x14697 z = x14698 z = x14699 z = x14700 z = x14701 z = x14702 z = x14703 z = x14704 z = x14705 z = x14706 z = x14707 z = x14708 z = x14709 z = x14710 z = x14711 z = x14712 z = x14713 z = x14714 z = x14715 z = x14716 z = x14717 z = x14718 z = x14719 z = x14720 z = x14721 z = x14722 z = x14723 z = x14724 z = x14725 z = x14726 z = x14727 z = x14728 z = x14729 z = x14730 z = x14731 z = x14732 z = x14733 z = x14734 z = x14735 z = x14736 z = x14737 z = x14738 z = x14739 z = x14740 z = x14741 z = x14742 z = x14743 z = x14744 z = x14745 z = x14746 z = x14747 z = x14748 z = x14749 z = x14750 z = x14751 z = x14752 z = x14753 z = x14754 z = x14755 z = x14756 z = x14757 z = x14758 z = x14759 z = x14760 z = x14761 z = x14762 z = x14763 z = x14764 z = x14765 z = x14766 z = x14767 z = x14768 z = x14769 z = x14770 z = x14771 z = x14772 z = x14773 z = x14774 z = x14775 z = x14776 z = x14777 z = x14778 z = x14779 z = x14780 z = x14781 z = x14782 z = x14783 z = x14784 z = x14785 z = x14786 z = x14787 z = x14788 z = x14789 z = x14790 z = x14791 z = x14792 z = x14793 z = x14794 z = x14795 z = x14796 z = x14797 z = x14798 z = x14799 z = x14800 z = x14801 z = x14802 z = x14803 z = x14804 z = x14805 z = x14806 z = x14807 z = x14808 z = x14809 z = x14810 z = x14811 z = x14812 z = x14813 z = x14814 z = x14815 z = x14816 z = x14817 z = x14818 z = x14819 z = x14820 z = x14821 z = x14822 z = x14823 z = x14824 z = x14825 z = x14826 z = x14827 z = x14828 z = x14829 z = x14830 z = x14831 z = x14832 z = x14833 z = x14834 z = x14835 z = x14836 z = x14837 z = x14838 z = x14839 z = x14840 z = x14841 z = x14842 z = x14843 z = x14844 z = x14845 z = x14846 z = x14847 z = x14848 z = x14849 z = x14850 z = x14851 z = x14852 z = x14853 z = x14854 z = x14855 z = x14856 z = x14857 z = x14858 z = x14859 z = x14860 z = x14861 z = x14862 z = x14863 z = x14864 z = x14865 z = x14866 z = x14867 z = x14868 z = x14869 z = x14870 z = x14871 z = x14872 z = x14873 z = x14874 z = x14875 z = x14876 z = x14877 z = x14878 z = x14879 z = x14880 z = x14881 z = x14882 z = x14883 z = x14884 z = x14885 z = x14886 z = x14887 z = x14888 z = x14889 z = x14890 z = x14891 z = x14892 z = x14893 z = x14894 z = x14895 z = x14896 z = x14897 z = x14898 z = x14899 z = x14900 z = x14901 z = x14902 z = x14903 z = x14904 z = x14905 z = x14906 z = x14907 z = x14908 z = x14909 z = x14910 z = x14911 z = x14912 z = x14913 z = x14914 z = x14915 z = x14916 z = x14917 z = x14918 z = x14919 z = x14920 z = x14921 z = x14922 z = x14923 z = x14924 z = x14925 z = x14926 z = x14927 z = x14928 z = x14929 z = x14930 z = x14931 z = x14932 z = x14933 z = x14934 z = x14935 z = x14936 z = x14937 z = x14938 z = x14939 z = x14940 z = x14941 z = x14942 z = x14943 z = x14944 z = x14945 z = x14946 z = x14947 z = x14948 z = x14949 z = x14950 z = x14951 z = x14952 z = x14953 z = x14954 z = x14955 z = x14956 z = x14957 z = x14958 z = x14959 z = x14960 z = x14961 z = x14962 z = x14963 z = x14964 z = x14965 z = x14966 z = x14967 z = x14968 z = x14969 z = x14970 z = x14971 z = x14972 z = x14973 z = x14974 z = x14975 z = x14976 z = x14977 z = x14978 z = x14979 z = x14980 z = x14981 z = x14982 z = x14983 z = x14984 z = x14985 z = x14986 z = x14987 z = x14988 z = x14989 z = x14990 z = x14991 z = x14992 z = x14993 z = x14994 z = x14995 z = x14996 z = x14997 z = x14998 z = x14999 z = x15000 z = x15001 z = x15002 z = x15003 z = x15004 z = x15005 z = x15006 z = x15007 z = x15008 z = x15009 z = x15010 z = x15011 z = x15012 z = x15013 z = x15014 z = x15015 z = x15016 z = x15017 z = x15018 z = x15019 z = x15020 z = x15021 z = x15022 z = x15023 z = x15024 z = x15025 z = x15026 z = x15027 z = x15028 z = x15029 z = x15030 z = x15031 z = x15032 z = x15033 z = x15034 z = x15035 z = x15036 z = x15037 z = x15038 z = x15039 z = x15040 z = x15041 z = x15042 z = x15043 z = x15044 z = x15045 z = x15046 z = x15047 z = x15048 z = x15049 z = x15050 z = x15051 z = x15052 z = x15053 z = x15054 z = x15055 z = x15056 z = x15057 z = x15058 z = x15059 z = x15060 z = x15061 z = x15062 z = x15063 z = x15064 z = x15065 z = x15066 z = x15067 z = x15068 z = x15069 z = x15070 z = x15071 z = x15072 z = x15073 z = x15074 z = x15075 z = x15076 z = x15077 z = x15078 z = x15079 z = x15080 z = x15081 z = x15082 z = x15083 z = x15084 z = x15085 z = x15086 z = x15087 z = x15088 z = x15089 z = x15090 z = x15091 z = x15092 z = x15093 z = x15094 z = x15095 z = x15096 z = x15097 z = x15098 z = x15099 z = x15100 z = x15101 z = x15102 z = x15103 z = x15104 z = x15105 z = x15106 z = x15107 z = x15108 z = x15109 z = x15110 z = x15111 z = x15112 z = x15113 z = x15114 z = x15115 z = x15116 z = x15117 z = x15118 z = x15119 z = x15120 z = x15121 z = x15122 z = x15123 z = x15124 z = x15125 z = x15126 z = x15127 z = x15128 z = x15129 z = x15130 z = x15131 z = x15132 z = x15133 z = x15134 z = x15135 z = x15136 z = x15137 z = x15138 z = x15139 z = x15140 z = x15141 z = x15142 z = x15143 z = x15144 z = x15145 z = x15146 z = x15147 z = x15148 z = x15149 z = x15150 z = x15151 z = x15152 z = x15153 z = x15154 z = x15155 z = x15156 z = x15157 z = x15158 z = x15159 z = x15160 z = x15161 z = x15162 z = x15163 z = x15164 z = x15165 z = x15166 z = x15167 z = x15168 z = x15169 z = x15170 z = x15171 z = x15172 z = x15173 z = x15174 z = x15175 z = x15176 z = x15177 z = x15178 z = x15179 z = x15180 z = x15181 z = x15182 z = x15183 z = x15184 z = x15185 z = x15186 z = x15187 z = x15188 z = x15189 z = x15190 z = x15191 z = x15192 z = x15193 z = x15194 z = x15195 z = x15196 z = x15197 z = x15198 z = x15199 z = x15200 z = x15201 z = x15202 z = x15203 z = x15204 z = x15205 z = x15206 z = x15207 z = x15208 z = x15209 z = x15210 z = x15211 z = x15212 z = x15213 z = x15214 z = x15215 z = x15216 z = x15217 z = x15218 z = x15219 z = x15220 z = x15221 z = x15222 z = x15223 z = x15224 z = x15225 z = x15226 z = x15227 z = x15228 z = x15229 z = x15230 z = x15231 z = x15232 z = x15233 z = x15234 z = x15235 z = x15236 z = x15237 z = x15238 z = x15239 z = x15240 z = x15241 z = x15242 z = x15243 z = x15244 z = x15245 z = x15246 z = x15247 z = x15248 z = x15249 z = x15250 z = x15251 z = x15252 z = x15253 z = x15254 z = x15255 z = x15256 z = x15257 z = x15258 z = x15259 z = x15260 z = x15261 z = x15262 z = x15263 z = x15264 z = x15265 z = x15266 z = x15267 z = x15268 z = x15269 z = x15270 z = x15271 z = x15272 z = x15273 z = x15274 z = x15275 z = x15276 z = x15277 z = x15278 z = x15279 z = x15280 z = x15281 z = x15282 z = x15283 z = x15284 z = x15285 z = x15286 z = x15287 z = x15288 z = x15289 z = x15290 z = x15291 z = x15292 z = x15293 z = x15294 z = x15295 z = x15296 z = x15297 z = x15298 z = x15299 z = x15300 z = x15301 z = x15302 z = x15303 z = x15304 z = x15305 z = x15306 z = x15307 z = x15308 z = x15309 z = x15310 z = x15311 z = x15312 z = x15313 z = x15314 z = x15315 z = x15316 z = x15317 z = x15318 z = x15319 z = x15320 z = x15321 z = x15322 z = x15323 z = x15324 z = x15325 z = x15326 z = x15327 z = x15328 z = x15329 z = x15330 z = x15331 z = x15332 z = x15333 z = x15334 z = x15335 z = x15336 z = x15337 z = x15338 z = x15339 z = x15340 z = x15341 z = x15342 z = x15343 z = x15344 z = x15345 z = x15346 z = x15347 z = x15348 z = x15349 z = x15350 z = x15351 z = x15352 z = x15353 z = x15354 z = x15355 z = x15356 z = x15357 z = x15358 z = x15359 z = x15360 z = x15361 z = x15362 z = x15363 z = x15364 z = x15365 z = x15366 z = x15367 z = x15368 z = x15369 z = x15370 z = x15371 z = x15372 z = x15373 z = x15374 z = x15375 z = x15376 z = x15377 z = x15378 z = x15379 z = x15380 z = x15381 z = x15382 z = x15383 z = x15384 z = x15385 z = x15386 z = x15387 z = x15388 z = x15389 z = x15390 z = x15391 z = x15392 z = x15393 z = x15394 z = x15395 z = x15396 z = x15397 z = x15398 z = x15399 z = x15400 z = x15401 z = x15402 z = x15403 z = x15404 z = x15405 z = x15406 z = x15407 z = x15408 z = x15409 z = x15410 z = x15411 z = x15412 z = x15413 z = x15414 z = x15415 z = x15416 z = x15417 z = x15418 z = x15419 z = x15420 z = x15421 z = x15422 z = x15423 z = x15424 z = x15425 z = x15426 z = x15427 z = x15428 z = x15429 z = x15430 z = x15431 z = x15432 z = x15433 z = x15434 z = x15435 z = x15436 z = x15437 z = x15438 z = x15439 z = x15440 z = x15441 z = x15442 z = x15443 z = x15444 z = x15445 z = x15446 z = x15447 z = x15448 z = x15449 z = x15450 z = x15451 z = x15452 z = x15453 z = x15454 z = x15455 z = x15456 z = x15457 z = x15458 z = x15459 z = x15460 z = x15461 z = x15462 z = x15463 z = x15464 z = x15465 z = x15466 z = x15467 z = x15468 z = x15469 z = x15470 z = x15471 z = x15472 z = x15473 z = x15474 z = x15475 z = x15476 z = x15477 z = x15478 z = x15479 z = x15480 z = x15481 z = x15482 z = x15483 z = x15484 z = x15485 z = x15486 z = x15487 z = x15488 z = x15489 z = x15490 z = x15491 z = x15492 z = x15493 z = x15494 z = x15495 z = x15496 z = x15497 z = x15498 z = x15499 z = x15500 z = x15501 z = x15502 z = x15503 z = x15504 z = x15505 z = x15506 z = x15507 z = x15508 z = x15509 z = x15510 z = x15511 z = x15512 z = x15513 z = x15514 z = x15515 z = x15516 z = x15517 z = x15518 z = x15519 z = x15520 z = x15521 z = x15522 z = x15523 z = x15524 z = x15525 z = x15526 z = x15527 z = x15528 z = x15529 z = x15530 z = x15531 z = x15532 z = x15533 z = x15534 z = x15535 z = x15536 z = x15537 z = x15538 z = x15539 z = x15540 z = x15541 z = x15542 z = x15543 z = x15544 z = x15545 z = x15546 z = x15547 z = x15548 z = x15549 z = x15550 z = x15551 z = x15552 z = x15553 z = x15554 z = x15555 z = x15556 z = x15557 z = x15558 z = x15559 z = x15560 z = x15561 z = x15562 z = x15563 z = x15564 z = x15565 z = x15566 z = x15567 z = x15568 z = x15569 z = x15570 z = x15571 z = x15572 z = x15573 z = x15574 z = x15575 z = x15576 z = x15577 z = x15578 z = x15579 z = x15580 z = x15581 z = x15582 z = x15583 z = x15584 z = x15585 z = x15586 z = x15587 z = x15588 z = x15589 z = x15590 z = x15591 z = x15592 z = x15593 z = x15594 z = x15595 z = x15596 z = x15597 z = x15598 z = x15599 z = x15600 z = x15601 z = x15602 z = x15603 z = x15604 z = x15605 z = x15606 z = x15607 z = x15608 z = x15609 z = x15610 z = x15611 z = x15612 z = x15613 z = x15614 z = x15615 z = x15616 z = x15617 z = x15618 z = x15619 z = x15620 z = x15621 z = x15622 z = x15623 z = x15624 z = x15625 z = x15626 z = x15627 z = x15628 z = x15629 z = x15630 z = x15631 z = x15632 z = x15633 z = x15634 z = x15635 z = x15636 z = x15637 z = x15638 z = x15639 z = x15640 z = x15641 z = x15642 z = x15643 z = x15644 z = x15645 z = x15646 z = x15647 z = x15648 z = x15649 z = x15650 z = x15651 z = x15652 z = x15653 z = x15654 z = x15655 z = x15656 z = x15657 z = x15658 z = x15659 z = x15660 z = x15661 z = x15662 z = x15663 z = x15664 z = x15665 z = x15666 z = x15667 z = x15668 z = x15669 z = x15670 z = x15671 z = x15672 z = x15673 z = x15674 z = x15675 z = x15676 z = x15677 z = x15678 z = x15679 z = x15680 z = x15681 z = x15682 z = x15683 z = x15684 z = x15685 z = x15686 z = x15687 z = x15688 z = x15689 z = x15690 z = x15691 z = x15692 z = x15693 z = x15694 z = x15695 z = x15696 z = x15697 z = x15698 z = x15699 z = x15700 z = x15701 z = x15702 z = x15703 z = x15704 z = x15705 z = x15706 z = x15707 z = x15708 z = x15709 z = x15710 z = x15711 z = x15712 z = x15713 z = x15714 z = x15715 z = x15716 z = x15717 z = x15718 z = x15719 z = x15720 z = x15721 z = x15722 z = x15723 z = x15724 z = x15725 z = x15726 z = x15727 z = x15728 z = x15729 z = x15730 z = x15731 z = x15732 z = x15733 z = x15734 z = x15735 z = x15736 z = x15737 z = x15738 z = x15739 z = x15740 z = x15741 z = x15742 z = x15743 z = x15744 z = x15745 z = x15746 z = x15747 z = x15748 z = x15749 z = x15750 z = x15751 z = x15752 z = x15753 z = x15754 z = x15755 z = x15756 z = x15757 z = x15758 z = x15759 z = x15760 z = x15761 z = x15762 z = x15763 z = x15764 z = x15765 z = x15766 z = x15767 z = x15768 z = x15769 z = x15770 z = x15771 z = x15772 z = x15773 z = x15774 z = x15775 z = x15776 z = x15777 z = x15778 z = x15779 z = x15780 z = x15781 z = x15782 z = x15783 z = x15784 z = x15785 z = x15786 z = x15787 z = x15788 z = x15789 z = x15790 z = x15791 z = x15792 z = x15793 z = x15794 z = x15795 z = x15796 z = x15797 z = x15798 z = x15799 z = x15800 z = x15801 z = x15802 z = x15803 z = x15804 z = x15805 z = x15806 z = x15807 z = x15808 z = x15809 z = x15810 z = x15811 z = x15812 z = x15813 z = x15814 z = x15815 z = x15816 z = x15817 z = x15818 z = x15819 z = x15820 z = x15821 z = x15822 z = x15823 z = x15824 z = x15825 z = x15826 z = x15827 z = x15828 z = x15829 z = x15830 z = x15831 z = x15832 z = x15833 z = x15834 z = x15835 z = x15836 z = x15837 z = x15838 z = x15839 z = x15840 z = x15841 z = x15842 z = x15843 z = x15844 z = x15845 z = x15846 z = x15847 z = x15848 z = x15849 z = x15850 z = x15851 z = x15852 z = x15853 z = x15854 z = x15855 z = x15856 z = x15857 z = x15858 z = x15859 z = x15860 z = x15861 z = x15862 z = x15863 z = x15864 z = x15865 z = x15866 z = x15867 z = x15868 z = x15869 z = x15870 z = x15871 z = x15872 z = x15873 z = x15874 z = x15875 z = x15876 z = x15877 z = x15878 z = x15879 z = x15880 z = x15881 z = x15882 z = x15883 z = x15884 z = x15885 z = x15886 z = x15887 z = x15888 z = x15889 z = x15890 z = x15891 z = x15892 z = x15893 z = x15894 z = x15895 z = x15896 z = x15897 z = x15898 z = x15899 z = x15900 z = x15901 z = x15902 z = x15903 z = x15904 z = x15905 z = x15906 z = x15907 z = x15908 z = x15909 z = x15910 z = x15911 z = x15912 z = x15913 z = x15914 z = x15915 z = x15916 z = x15917 z = x15918 z = x15919 z = x15920 z = x15921 z = x15922 z = x15923 z = x15924 z = x15925 z = x15926 z = x15927 z = x15928 z = x15929 z = x15930 z = x15931 z = x15932 z = x15933 z = x15934 z = x15935 z = x15936 z = x15937 z = x15938 z = x15939 z = x15940 z = x15941 z = x15942 z = x15943 z = x15944 z = x15945 z = x15946 z = x15947 z = x15948 z = x15949 z = x15950 z = x15951 z = x15952 z = x15953 z = x15954 z = x15955 z = x15956 z = x15957 z = x15958 z = x15959 z = x15960 z = x15961 z = x15962 z = x15963 z = x15964 z = x15965 z = x15966 z = x15967 z = x15968 z = x15969 z = x15970 z = x15971 z = x15972 z = x15973 z = x15974 z = x15975 z = x15976 z = x15977 z = x15978 z = x15979 z = x15980 z = x15981 z = x15982 z = x15983 z = x15984 z = x15985 z = x15986 z = x15987 z = x15988 z = x15989 z = x15990 z = x15991 z = x15992 z = x15993 z = x15994 z = x15995 z = x15996 z = x15997 z = x15998 z = x15999 z = x16000 z = x16001 z = x16002 z = x16003 z = x16004 z = x16005 z = x16006 z = x16007 z = x16008 z = x16009 z = x16010 z = x16011 z = x16012 z = x16013 z = x16014 z = x16015 z = x16016 z = x16017 z = x16018 z = x16019 z = x16020 z = x16021 z = x16022 z = x16023 z = x16024 z = x16025 z = x16026 z = x16027 z = x16028 z = x16029 z = x16030 z = x16031 z = x16032 z = x16033 z = x16034 z = x16035 z = x16036 z = x16037 z = x16038 z = x16039 z = x16040 z = x16041 z = x16042 z = x16043 z = x16044 z = x16045 z = x16046 z = x16047 z = x16048 z = x16049 z = x16050 z = x16051 z = x16052 z = x16053 z = x16054 z = x16055 z = x16056 z = x16057 z = x16058 z = x16059 z = x16060 z = x16061 z = x16062 z = x16063 z = x16064 z = x16065 z = x16066 z = x16067 z = x16068 z = x16069 z = x16070 z = x16071 z = x16072 z = x16073 z = x16074 z = x16075 z = x16076 z = x16077 z = x16078 z = x16079 z = x16080 z = x16081 z = x16082 z = x16083 z = x16084 z = x16085 z = x16086 z = x16087 z = x16088 z = x16089 z = x16090 z = x16091 z = x16092 z = x16093 z = x16094 z = x16095 z = x16096 z = x16097 z = x16098 z = x16099 z = x16100 z = x16101 z = x16102 z = x16103 z = x16104 z = x16105 z = x16106 z = x16107 z = x16108 z = x16109 z = x16110 z = x16111 z = x16112 z = x16113 z = x16114 z = x16115 z = x16116 z = x16117 z = x16118 z = x16119 z = x16120 z = x16121 z = x16122 z = x16123 z = x16124 z = x16125 z = x16126 z = x16127 z = x16128 z = x16129 z = x16130 z = x16131 z = x16132 z = x16133 z = x16134 z = x16135 z = x16136 z = x16137 z = x16138 z = x16139 z = x16140 z = x16141 z = x16142 z = x16143 z = x16144 z = x16145 z = x16146 z = x16147 z = x16148 z = x16149 z = x16150 z = x16151 z = x16152 z = x16153 z = x16154 z = x16155 z = x16156 z = x16157 z = x16158 z = x16159 z = x16160 z = x16161 z = x16162 z = x16163 z = x16164 z = x16165 z = x16166 z = x16167 z = x16168 z = x16169 z = x16170 z = x16171 z = x16172 z = x16173 z = x16174 z = x16175 z = x16176 z = x16177 z = x16178 z = x16179 z = x16180 z = x16181 z = x16182 z = x16183 z = x16184 z = x16185 z = x16186 z = x16187 z = x16188 z = x16189 z = x16190 z = x16191 z = x16192 z = x16193 z = x16194 z = x16195 z = x16196 z = x16197 z = x16198 z = x16199 z = x16200 z = x16201 z = x16202 z = x16203 z = x16204 z = x16205 z = x16206 z = x16207 z = x16208 z = x16209 z = x16210 z = x16211 z = x16212 z = x16213 z = x16214 z = x16215 z = x16216 z = x16217 z = x16218 z = x16219 z = x16220 z = x16221 z = x16222 z = x16223 z = x16224 z = x16225 z = x16226 z = x16227 z = x16228 z = x16229 z = x16230 z = x16231 z = x16232 z = x16233 z = x16234 z = x16235 z = x16236 z = x16237 z = x16238 z = x16239 z = x16240 z = x16241 z = x16242 z = x16243 z = x16244 z = x16245 z = x16246 z = x16247 z = x16248 z = x16249 z = x16250 z = x16251 z = x16252 z = x16253 z = x16254 z = x16255 z = x16256 z = x16257 z = x16258 z = x16259 z = x16260 z = x16261 z = x16262 z = x16263 z = x16264 z = x16265 z = x16266 z = x16267 z = x16268 z = x16269 z = x16270 z = x16271 z = x16272 z = x16273 z = x16274 z = x16275 z = x16276 z = x16277 z = x16278 z = x16279 z = x16280 z = x16281 z = x16282 z = x16283 z = x16284 z = x16285 z = x16286 z = x16287 z = x16288 z = x16289 z = x16290 z = x16291 z = x16292 z = x16293 z = x16294 z = x16295 z = x16296 z = x16297 z = x16298 z = x16299 z = x16300 z = x16301 z = x16302 z = x16303 z = x16304 z = x16305 z = x16306 z = x16307 z = x16308 z = x16309 z = x16310 z = x16311 z = x16312 z = x16313 z = x16314 z = x16315 z = x16316 z = x16317 z = x16318 z = x16319 z = x16320 z = x16321 z = x16322 z = x16323 z = x16324 z = x16325 z = x16326 z = x16327 z = x16328 z = x16329 z = x16330 z = x16331 z = x16332 z = x16333 z = x16334 z = x16335 z = x16336 z = x16337 z = x16338 z = x16339 z = x16340 z = x16341 z = x16342 z = x16343 z = x16344 z = x16345 z = x16346 z = x16347 z = x16348 z = x16349 z = x16350 z = x16351 z = x16352 z = x16353 z = x16354 z = x16355 z = x16356 z = x16357 z = x16358 z = x16359 z = x16360 z = x16361 z = x16362 z = x16363 z = x16364 z = x16365 z = x16366 z = x16367 z = x16368 z = x16369 z = x16370 z = x16371 z = x16372 z = x16373 z = x16374 z = x16375 z = x16376 z = x16377 z = x16378 z = x16379 z = x16380 z = x16381 z = x16382 z = x16383 z = x16384 z = x16385 z = x16386 z = x16387 z = x16388 z = x16389 z = x16390 z = x16391 z = x16392 z = x16393 z = x16394 z = x16395 z = x16396 z = x16397 z = x16398 z = x16399 z = x16400 z = x16401 z = x16402 z = x16403 z = x16404 z = x16405 z = x16406 z = x16407 z = x16408 z = x16409 z = x16410 z = x16411 z = x16412 z = x16413 z = x16414 z = x16415 z = x16416 z = x16417 z = x16418 z = x16419 z = x16420 z = x16421 z = x16422 z = x16423 z = x16424 z = x16425 z = x16426 z = x16427 z = x16428 z = x16429 z = x16430 z = x16431 z = x16432 z = x16433 z = x16434 z = x16435 z = x16436 z = x16437 z = x16438 z = x16439 z = x16440 z = x16441 z = x16442 z = x16443 z = x16444 z = x16445 z = x16446 z = x16447 z = x16448 z = x16449 z = x16450 z = x16451 z = x16452 z = x16453 z = x16454 z = x16455 z = x16456 z = x16457 z = x16458 z = x16459 z = x16460 z = x16461 z = x16462 z = x16463 z = x16464 z = x16465 z = x16466 z = x16467 z = x16468 z = x16469 z = x16470 z = x16471 z = x16472 z = x16473 z = x16474 z = x16475 z = x16476 z = x16477 z = x16478 z = x16479 z = x16480 } -- y -- // errorcheck //go:build amd64 // Copyright 2011 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // Issue 2444 // Issue 4666: issue with arrays of exactly 4GB. package main // seq 1 16480 | sed 's/.*/var z& [1 << 17]byte/' var z1 [1 << 17]byte var z2 [1 << 17]byte var z3 [1 << 17]byte var z4 [1 << 17]byte var z5 [1 << 17]byte var z6 [1 << 17]byte var z7 [1 << 17]byte var z8 [1 << 17]byte var z9 [1 << 17]byte var z10 [1 << 17]byte var z11 [1 << 17]byte var z12 [1 << 17]byte var z13 [1 << 17]byte var z14 [1 << 17]byte var z15 [1 << 17]byte var z16 [1 << 17]byte var z17 [1 << 17]byte var z18 [1 << 17]byte var z19 [1 << 17]byte var z20 [1 << 17]byte var z21 [1 << 17]byte var z22 [1 << 17]byte var z23 [1 << 17]byte var z24 [1 << 17]byte var z25 [1 << 17]byte var z26 [1 << 17]byte var z27 [1 << 17]byte var z28 [1 << 17]byte var z29 [1 << 17]byte var z30 [1 << 17]byte var z31 [1 << 17]byte var z32 [1 << 17]byte var z33 [1 << 17]byte var z34 [1 << 17]byte var z35 [1 << 17]byte var z36 [1 << 17]byte var z37 [1 << 17]byte var z38 [1 << 17]byte var z39 [1 << 17]byte var z40 [1 << 17]byte var z41 [1 << 17]byte var z42 [1 << 17]byte var z43 [1 << 17]byte var z44 [1 << 17]byte var z45 [1 << 17]byte var z46 [1 << 17]byte var z47 [1 << 17]byte var z48 [1 << 17]byte var z49 [1 << 17]byte var z50 [1 << 17]byte var z51 [1 << 17]byte var z52 [1 << 17]byte var z53 [1 << 17]byte var z54 [1 << 17]byte var z55 [1 << 17]byte var z56 [1 << 17]byte var z57 [1 << 17]byte var z58 [1 << 17]byte var z59 [1 << 17]byte var z60 [1 << 17]byte var z61 [1 << 17]byte var z62 [1 << 17]byte var z63 [1 << 17]byte var z64 [1 << 17]byte var z65 [1 << 17]byte var z66 [1 << 17]byte var z67 [1 << 17]byte var z68 [1 << 17]byte var z69 [1 << 17]byte var z70 [1 << 17]byte var z71 [1 << 17]byte var z72 [1 << 17]byte var z73 [1 << 17]byte var z74 [1 << 17]byte var z75 [1 << 17]byte var z76 [1 << 17]byte var z77 [1 << 17]byte var z78 [1 << 17]byte var z79 [1 << 17]byte var z80 [1 << 17]byte var z81 [1 << 17]byte var z82 [1 << 17]byte var z83 [1 << 17]byte var z84 [1 << 17]byte var z85 [1 << 17]byte var z86 [1 << 17]byte var z87 [1 << 17]byte var z88 [1 << 17]byte var z89 [1 << 17]byte var z90 [1 << 17]byte var z91 [1 << 17]byte var z92 [1 << 17]byte var z93 [1 << 17]byte var z94 [1 << 17]byte var z95 [1 << 17]byte var z96 [1 << 17]byte var z97 [1 << 17]byte var z98 [1 << 17]byte var z99 [1 << 17]byte var z100 [1 << 17]byte var z101 [1 << 17]byte var z102 [1 << 17]byte var z103 [1 << 17]byte var z104 [1 << 17]byte var z105 [1 << 17]byte var z106 [1 << 17]byte var z107 [1 << 17]byte var z108 [1 << 17]byte var z109 [1 << 17]byte var z110 [1 << 17]byte var z111 [1 << 17]byte var z112 [1 << 17]byte var z113 [1 << 17]byte var z114 [1 << 17]byte var z115 [1 << 17]byte var z116 [1 << 17]byte var z117 [1 << 17]byte var z118 [1 << 17]byte var z119 [1 << 17]byte var z120 [1 << 17]byte var z121 [1 << 17]byte var z122 [1 << 17]byte var z123 [1 << 17]byte var z124 [1 << 17]byte var z125 [1 << 17]byte var z126 [1 << 17]byte var z127 [1 << 17]byte var z128 [1 << 17]byte var z129 [1 << 17]byte var z130 [1 << 17]byte var z131 [1 << 17]byte var z132 [1 << 17]byte var z133 [1 << 17]byte var z134 [1 << 17]byte var z135 [1 << 17]byte var z136 [1 << 17]byte var z137 [1 << 17]byte var z138 [1 << 17]byte var z139 [1 << 17]byte var z140 [1 << 17]byte var z141 [1 << 17]byte var z142 [1 << 17]byte var z143 [1 << 17]byte var z144 [1 << 17]byte var z145 [1 << 17]byte var z146 [1 << 17]byte var z147 [1 << 17]byte var z148 [1 << 17]byte var z149 [1 << 17]byte var z150 [1 << 17]byte var z151 [1 << 17]byte var z152 [1 << 17]byte var z153 [1 << 17]byte var z154 [1 << 17]byte var z155 [1 << 17]byte var z156 [1 << 17]byte var z157 [1 << 17]byte var z158 [1 << 17]byte var z159 [1 << 17]byte var z160 [1 << 17]byte var z161 [1 << 17]byte var z162 [1 << 17]byte var z163 [1 << 17]byte var z164 [1 << 17]byte var z165 [1 << 17]byte var z166 [1 << 17]byte var z167 [1 << 17]byte var z168 [1 << 17]byte var z169 [1 << 17]byte var z170 [1 << 17]byte var z171 [1 << 17]byte var z172 [1 << 17]byte var z173 [1 << 17]byte var z174 [1 << 17]byte var z175 [1 << 17]byte var z176 [1 << 17]byte var z177 [1 << 17]byte var z178 [1 << 17]byte var z179 [1 << 17]byte var z180 [1 << 17]byte var z181 [1 << 17]byte var z182 [1 << 17]byte var z183 [1 << 17]byte var z184 [1 << 17]byte var z185 [1 << 17]byte var z186 [1 << 17]byte var z187 [1 << 17]byte var z188 [1 << 17]byte var z189 [1 << 17]byte var z190 [1 << 17]byte var z191 [1 << 17]byte var z192 [1 << 17]byte var z193 [1 << 17]byte var z194 [1 << 17]byte var z195 [1 << 17]byte var z196 [1 << 17]byte var z197 [1 << 17]byte var z198 [1 << 17]byte var z199 [1 << 17]byte var z200 [1 << 17]byte var z201 [1 << 17]byte var z202 [1 << 17]byte var z203 [1 << 17]byte var z204 [1 << 17]byte var z205 [1 << 17]byte var z206 [1 << 17]byte var z207 [1 << 17]byte var z208 [1 << 17]byte var z209 [1 << 17]byte var z210 [1 << 17]byte var z211 [1 << 17]byte var z212 [1 << 17]byte var z213 [1 << 17]byte var z214 [1 << 17]byte var z215 [1 << 17]byte var z216 [1 << 17]byte var z217 [1 << 17]byte var z218 [1 << 17]byte var z219 [1 << 17]byte var z220 [1 << 17]byte var z221 [1 << 17]byte var z222 [1 << 17]byte var z223 [1 << 17]byte var z224 [1 << 17]byte var z225 [1 << 17]byte var z226 [1 << 17]byte var z227 [1 << 17]byte var z228 [1 << 17]byte var z229 [1 << 17]byte var z230 [1 << 17]byte var z231 [1 << 17]byte var z232 [1 << 17]byte var z233 [1 << 17]byte var z234 [1 << 17]byte var z235 [1 << 17]byte var z236 [1 << 17]byte var z237 [1 << 17]byte var z238 [1 << 17]byte var z239 [1 << 17]byte var z240 [1 << 17]byte var z241 [1 << 17]byte var z242 [1 << 17]byte var z243 [1 << 17]byte var z244 [1 << 17]byte var z245 [1 << 17]byte var z246 [1 << 17]byte var z247 [1 << 17]byte var z248 [1 << 17]byte var z249 [1 << 17]byte var z250 [1 << 17]byte var z251 [1 << 17]byte var z252 [1 << 17]byte var z253 [1 << 17]byte var z254 [1 << 17]byte var z255 [1 << 17]byte var z256 [1 << 17]byte var z257 [1 << 17]byte var z258 [1 << 17]byte var z259 [1 << 17]byte var z260 [1 << 17]byte var z261 [1 << 17]byte var z262 [1 << 17]byte var z263 [1 << 17]byte var z264 [1 << 17]byte var z265 [1 << 17]byte var z266 [1 << 17]byte var z267 [1 << 17]byte var z268 [1 << 17]byte var z269 [1 << 17]byte var z270 [1 << 17]byte var z271 [1 << 17]byte var z272 [1 << 17]byte var z273 [1 << 17]byte var z274 [1 << 17]byte var z275 [1 << 17]byte var z276 [1 << 17]byte var z277 [1 << 17]byte var z278 [1 << 17]byte var z279 [1 << 17]byte var z280 [1 << 17]byte var z281 [1 << 17]byte var z282 [1 << 17]byte var z283 [1 << 17]byte var z284 [1 << 17]byte var z285 [1 << 17]byte var z286 [1 << 17]byte var z287 [1 << 17]byte var z288 [1 << 17]byte var z289 [1 << 17]byte var z290 [1 << 17]byte var z291 [1 << 17]byte var z292 [1 << 17]byte var z293 [1 << 17]byte var z294 [1 << 17]byte var z295 [1 << 17]byte var z296 [1 << 17]byte var z297 [1 << 17]byte var z298 [1 << 17]byte var z299 [1 << 17]byte var z300 [1 << 17]byte var z301 [1 << 17]byte var z302 [1 << 17]byte var z303 [1 << 17]byte var z304 [1 << 17]byte var z305 [1 << 17]byte var z306 [1 << 17]byte var z307 [1 << 17]byte var z308 [1 << 17]byte var z309 [1 << 17]byte var z310 [1 << 17]byte var z311 [1 << 17]byte var z312 [1 << 17]byte var z313 [1 << 17]byte var z314 [1 << 17]byte var z315 [1 << 17]byte var z316 [1 << 17]byte var z317 [1 << 17]byte var z318 [1 << 17]byte var z319 [1 << 17]byte var z320 [1 << 17]byte var z321 [1 << 17]byte var z322 [1 << 17]byte var z323 [1 << 17]byte var z324 [1 << 17]byte var z325 [1 << 17]byte var z326 [1 << 17]byte var z327 [1 << 17]byte var z328 [1 << 17]byte var z329 [1 << 17]byte var z330 [1 << 17]byte var z331 [1 << 17]byte var z332 [1 << 17]byte var z333 [1 << 17]byte var z334 [1 << 17]byte var z335 [1 << 17]byte var z336 [1 << 17]byte var z337 [1 << 17]byte var z338 [1 << 17]byte var z339 [1 << 17]byte var z340 [1 << 17]byte var z341 [1 << 17]byte var z342 [1 << 17]byte var z343 [1 << 17]byte var z344 [1 << 17]byte var z345 [1 << 17]byte var z346 [1 << 17]byte var z347 [1 << 17]byte var z348 [1 << 17]byte var z349 [1 << 17]byte var z350 [1 << 17]byte var z351 [1 << 17]byte var z352 [1 << 17]byte var z353 [1 << 17]byte var z354 [1 << 17]byte var z355 [1 << 17]byte var z356 [1 << 17]byte var z357 [1 << 17]byte var z358 [1 << 17]byte var z359 [1 << 17]byte var z360 [1 << 17]byte var z361 [1 << 17]byte var z362 [1 << 17]byte var z363 [1 << 17]byte var z364 [1 << 17]byte var z365 [1 << 17]byte var z366 [1 << 17]byte var z367 [1 << 17]byte var z368 [1 << 17]byte var z369 [1 << 17]byte var z370 [1 << 17]byte var z371 [1 << 17]byte var z372 [1 << 17]byte var z373 [1 << 17]byte var z374 [1 << 17]byte var z375 [1 << 17]byte var z376 [1 << 17]byte var z377 [1 << 17]byte var z378 [1 << 17]byte var z379 [1 << 17]byte var z380 [1 << 17]byte var z381 [1 << 17]byte var z382 [1 << 17]byte var z383 [1 << 17]byte var z384 [1 << 17]byte var z385 [1 << 17]byte var z386 [1 << 17]byte var z387 [1 << 17]byte var z388 [1 << 17]byte var z389 [1 << 17]byte var z390 [1 << 17]byte var z391 [1 << 17]byte var z392 [1 << 17]byte var z393 [1 << 17]byte var z394 [1 << 17]byte var z395 [1 << 17]byte var z396 [1 << 17]byte var z397 [1 << 17]byte var z398 [1 << 17]byte var z399 [1 << 17]byte var z400 [1 << 17]byte var z401 [1 << 17]byte var z402 [1 << 17]byte var z403 [1 << 17]byte var z404 [1 << 17]byte var z405 [1 << 17]byte var z406 [1 << 17]byte var z407 [1 << 17]byte var z408 [1 << 17]byte var z409 [1 << 17]byte var z410 [1 << 17]byte var z411 [1 << 17]byte var z412 [1 << 17]byte var z413 [1 << 17]byte var z414 [1 << 17]byte var z415 [1 << 17]byte var z416 [1 << 17]byte var z417 [1 << 17]byte var z418 [1 << 17]byte var z419 [1 << 17]byte var z420 [1 << 17]byte var z421 [1 << 17]byte var z422 [1 << 17]byte var z423 [1 << 17]byte var z424 [1 << 17]byte var z425 [1 << 17]byte var z426 [1 << 17]byte var z427 [1 << 17]byte var z428 [1 << 17]byte var z429 [1 << 17]byte var z430 [1 << 17]byte var z431 [1 << 17]byte var z432 [1 << 17]byte var z433 [1 << 17]byte var z434 [1 << 17]byte var z435 [1 << 17]byte var z436 [1 << 17]byte var z437 [1 << 17]byte var z438 [1 << 17]byte var z439 [1 << 17]byte var z440 [1 << 17]byte var z441 [1 << 17]byte var z442 [1 << 17]byte var z443 [1 << 17]byte var z444 [1 << 17]byte var z445 [1 << 17]byte var z446 [1 << 17]byte var z447 [1 << 17]byte var z448 [1 << 17]byte var z449 [1 << 17]byte var z450 [1 << 17]byte var z451 [1 << 17]byte var z452 [1 << 17]byte var z453 [1 << 17]byte var z454 [1 << 17]byte var z455 [1 << 17]byte var z456 [1 << 17]byte var z457 [1 << 17]byte var z458 [1 << 17]byte var z459 [1 << 17]byte var z460 [1 << 17]byte var z461 [1 << 17]byte var z462 [1 << 17]byte var z463 [1 << 17]byte var z464 [1 << 17]byte var z465 [1 << 17]byte var z466 [1 << 17]byte var z467 [1 << 17]byte var z468 [1 << 17]byte var z469 [1 << 17]byte var z470 [1 << 17]byte var z471 [1 << 17]byte var z472 [1 << 17]byte var z473 [1 << 17]byte var z474 [1 << 17]byte var z475 [1 << 17]byte var z476 [1 << 17]byte var z477 [1 << 17]byte var z478 [1 << 17]byte var z479 [1 << 17]byte var z480 [1 << 17]byte var z481 [1 << 17]byte var z482 [1 << 17]byte var z483 [1 << 17]byte var z484 [1 << 17]byte var z485 [1 << 17]byte var z486 [1 << 17]byte var z487 [1 << 17]byte var z488 [1 << 17]byte var z489 [1 << 17]byte var z490 [1 << 17]byte var z491 [1 << 17]byte var z492 [1 << 17]byte var z493 [1 << 17]byte var z494 [1 << 17]byte var z495 [1 << 17]byte var z496 [1 << 17]byte var z497 [1 << 17]byte var z498 [1 << 17]byte var z499 [1 << 17]byte var z500 [1 << 17]byte var z501 [1 << 17]byte var z502 [1 << 17]byte var z503 [1 << 17]byte var z504 [1 << 17]byte var z505 [1 << 17]byte var z506 [1 << 17]byte var z507 [1 << 17]byte var z508 [1 << 17]byte var z509 [1 << 17]byte var z510 [1 << 17]byte var z511 [1 << 17]byte var z512 [1 << 17]byte var z513 [1 << 17]byte var z514 [1 << 17]byte var z515 [1 << 17]byte var z516 [1 << 17]byte var z517 [1 << 17]byte var z518 [1 << 17]byte var z519 [1 << 17]byte var z520 [1 << 17]byte var z521 [1 << 17]byte var z522 [1 << 17]byte var z523 [1 << 17]byte var z524 [1 << 17]byte var z525 [1 << 17]byte var z526 [1 << 17]byte var z527 [1 << 17]byte var z528 [1 << 17]byte var z529 [1 << 17]byte var z530 [1 << 17]byte var z531 [1 << 17]byte var z532 [1 << 17]byte var z533 [1 << 17]byte var z534 [1 << 17]byte var z535 [1 << 17]byte var z536 [1 << 17]byte var z537 [1 << 17]byte var z538 [1 << 17]byte var z539 [1 << 17]byte var z540 [1 << 17]byte var z541 [1 << 17]byte var z542 [1 << 17]byte var z543 [1 << 17]byte var z544 [1 << 17]byte var z545 [1 << 17]byte var z546 [1 << 17]byte var z547 [1 << 17]byte var z548 [1 << 17]byte var z549 [1 << 17]byte var z550 [1 << 17]byte var z551 [1 << 17]byte var z552 [1 << 17]byte var z553 [1 << 17]byte var z554 [1 << 17]byte var z555 [1 << 17]byte var z556 [1 << 17]byte var z557 [1 << 17]byte var z558 [1 << 17]byte var z559 [1 << 17]byte var z560 [1 << 17]byte var z561 [1 << 17]byte var z562 [1 << 17]byte var z563 [1 << 17]byte var z564 [1 << 17]byte var z565 [1 << 17]byte var z566 [1 << 17]byte var z567 [1 << 17]byte var z568 [1 << 17]byte var z569 [1 << 17]byte var z570 [1 << 17]byte var z571 [1 << 17]byte var z572 [1 << 17]byte var z573 [1 << 17]byte var z574 [1 << 17]byte var z575 [1 << 17]byte var z576 [1 << 17]byte var z577 [1 << 17]byte var z578 [1 << 17]byte var z579 [1 << 17]byte var z580 [1 << 17]byte var z581 [1 << 17]byte var z582 [1 << 17]byte var z583 [1 << 17]byte var z584 [1 << 17]byte var z585 [1 << 17]byte var z586 [1 << 17]byte var z587 [1 << 17]byte var z588 [1 << 17]byte var z589 [1 << 17]byte var z590 [1 << 17]byte var z591 [1 << 17]byte var z592 [1 << 17]byte var z593 [1 << 17]byte var z594 [1 << 17]byte var z595 [1 << 17]byte var z596 [1 << 17]byte var z597 [1 << 17]byte var z598 [1 << 17]byte var z599 [1 << 17]byte var z600 [1 << 17]byte var z601 [1 << 17]byte var z602 [1 << 17]byte var z603 [1 << 17]byte var z604 [1 << 17]byte var z605 [1 << 17]byte var z606 [1 << 17]byte var z607 [1 << 17]byte var z608 [1 << 17]byte var z609 [1 << 17]byte var z610 [1 << 17]byte var z611 [1 << 17]byte var z612 [1 << 17]byte var z613 [1 << 17]byte var z614 [1 << 17]byte var z615 [1 << 17]byte var z616 [1 << 17]byte var z617 [1 << 17]byte var z618 [1 << 17]byte var z619 [1 << 17]byte var z620 [1 << 17]byte var z621 [1 << 17]byte var z622 [1 << 17]byte var z623 [1 << 17]byte var z624 [1 << 17]byte var z625 [1 << 17]byte var z626 [1 << 17]byte var z627 [1 << 17]byte var z628 [1 << 17]byte var z629 [1 << 17]byte var z630 [1 << 17]byte var z631 [1 << 17]byte var z632 [1 << 17]byte var z633 [1 << 17]byte var z634 [1 << 17]byte var z635 [1 << 17]byte var z636 [1 << 17]byte var z637 [1 << 17]byte var z638 [1 << 17]byte var z639 [1 << 17]byte var z640 [1 << 17]byte var z641 [1 << 17]byte var z642 [1 << 17]byte var z643 [1 << 17]byte var z644 [1 << 17]byte var z645 [1 << 17]byte var z646 [1 << 17]byte var z647 [1 << 17]byte var z648 [1 << 17]byte var z649 [1 << 17]byte var z650 [1 << 17]byte var z651 [1 << 17]byte var z652 [1 << 17]byte var z653 [1 << 17]byte var z654 [1 << 17]byte var z655 [1 << 17]byte var z656 [1 << 17]byte var z657 [1 << 17]byte var z658 [1 << 17]byte var z659 [1 << 17]byte var z660 [1 << 17]byte var z661 [1 << 17]byte var z662 [1 << 17]byte var z663 [1 << 17]byte var z664 [1 << 17]byte var z665 [1 << 17]byte var z666 [1 << 17]byte var z667 [1 << 17]byte var z668 [1 << 17]byte var z669 [1 << 17]byte var z670 [1 << 17]byte var z671 [1 << 17]byte var z672 [1 << 17]byte var z673 [1 << 17]byte var z674 [1 << 17]byte var z675 [1 << 17]byte var z676 [1 << 17]byte var z677 [1 << 17]byte var z678 [1 << 17]byte var z679 [1 << 17]byte var z680 [1 << 17]byte var z681 [1 << 17]byte var z682 [1 << 17]byte var z683 [1 << 17]byte var z684 [1 << 17]byte var z685 [1 << 17]byte var z686 [1 << 17]byte var z687 [1 << 17]byte var z688 [1 << 17]byte var z689 [1 << 17]byte var z690 [1 << 17]byte var z691 [1 << 17]byte var z692 [1 << 17]byte var z693 [1 << 17]byte var z694 [1 << 17]byte var z695 [1 << 17]byte var z696 [1 << 17]byte var z697 [1 << 17]byte var z698 [1 << 17]byte var z699 [1 << 17]byte var z700 [1 << 17]byte var z701 [1 << 17]byte var z702 [1 << 17]byte var z703 [1 << 17]byte var z704 [1 << 17]byte var z705 [1 << 17]byte var z706 [1 << 17]byte var z707 [1 << 17]byte var z708 [1 << 17]byte var z709 [1 << 17]byte var z710 [1 << 17]byte var z711 [1 << 17]byte var z712 [1 << 17]byte var z713 [1 << 17]byte var z714 [1 << 17]byte var z715 [1 << 17]byte var z716 [1 << 17]byte var z717 [1 << 17]byte var z718 [1 << 17]byte var z719 [1 << 17]byte var z720 [1 << 17]byte var z721 [1 << 17]byte var z722 [1 << 17]byte var z723 [1 << 17]byte var z724 [1 << 17]byte var z725 [1 << 17]byte var z726 [1 << 17]byte var z727 [1 << 17]byte var z728 [1 << 17]byte var z729 [1 << 17]byte var z730 [1 << 17]byte var z731 [1 << 17]byte var z732 [1 << 17]byte var z733 [1 << 17]byte var z734 [1 << 17]byte var z735 [1 << 17]byte var z736 [1 << 17]byte var z737 [1 << 17]byte var z738 [1 << 17]byte var z739 [1 << 17]byte var z740 [1 << 17]byte var z741 [1 << 17]byte var z742 [1 << 17]byte var z743 [1 << 17]byte var z744 [1 << 17]byte var z745 [1 << 17]byte var z746 [1 << 17]byte var z747 [1 << 17]byte var z748 [1 << 17]byte var z749 [1 << 17]byte var z750 [1 << 17]byte var z751 [1 << 17]byte var z752 [1 << 17]byte var z753 [1 << 17]byte var z754 [1 << 17]byte var z755 [1 << 17]byte var z756 [1 << 17]byte var z757 [1 << 17]byte var z758 [1 << 17]byte var z759 [1 << 17]byte var z760 [1 << 17]byte var z761 [1 << 17]byte var z762 [1 << 17]byte var z763 [1 << 17]byte var z764 [1 << 17]byte var z765 [1 << 17]byte var z766 [1 << 17]byte var z767 [1 << 17]byte var z768 [1 << 17]byte var z769 [1 << 17]byte var z770 [1 << 17]byte var z771 [1 << 17]byte var z772 [1 << 17]byte var z773 [1 << 17]byte var z774 [1 << 17]byte var z775 [1 << 17]byte var z776 [1 << 17]byte var z777 [1 << 17]byte var z778 [1 << 17]byte var z779 [1 << 17]byte var z780 [1 << 17]byte var z781 [1 << 17]byte var z782 [1 << 17]byte var z783 [1 << 17]byte var z784 [1 << 17]byte var z785 [1 << 17]byte var z786 [1 << 17]byte var z787 [1 << 17]byte var z788 [1 << 17]byte var z789 [1 << 17]byte var z790 [1 << 17]byte var z791 [1 << 17]byte var z792 [1 << 17]byte var z793 [1 << 17]byte var z794 [1 << 17]byte var z795 [1 << 17]byte var z796 [1 << 17]byte var z797 [1 << 17]byte var z798 [1 << 17]byte var z799 [1 << 17]byte var z800 [1 << 17]byte var z801 [1 << 17]byte var z802 [1 << 17]byte var z803 [1 << 17]byte var z804 [1 << 17]byte var z805 [1 << 17]byte var z806 [1 << 17]byte var z807 [1 << 17]byte var z808 [1 << 17]byte var z809 [1 << 17]byte var z810 [1 << 17]byte var z811 [1 << 17]byte var z812 [1 << 17]byte var z813 [1 << 17]byte var z814 [1 << 17]byte var z815 [1 << 17]byte var z816 [1 << 17]byte var z817 [1 << 17]byte var z818 [1 << 17]byte var z819 [1 << 17]byte var z820 [1 << 17]byte var z821 [1 << 17]byte var z822 [1 << 17]byte var z823 [1 << 17]byte var z824 [1 << 17]byte var z825 [1 << 17]byte var z826 [1 << 17]byte var z827 [1 << 17]byte var z828 [1 << 17]byte var z829 [1 << 17]byte var z830 [1 << 17]byte var z831 [1 << 17]byte var z832 [1 << 17]byte var z833 [1 << 17]byte var z834 [1 << 17]byte var z835 [1 << 17]byte var z836 [1 << 17]byte var z837 [1 << 17]byte var z838 [1 << 17]byte var z839 [1 << 17]byte var z840 [1 << 17]byte var z841 [1 << 17]byte var z842 [1 << 17]byte var z843 [1 << 17]byte var z844 [1 << 17]byte var z845 [1 << 17]byte var z846 [1 << 17]byte var z847 [1 << 17]byte var z848 [1 << 17]byte var z849 [1 << 17]byte var z850 [1 << 17]byte var z851 [1 << 17]byte var z852 [1 << 17]byte var z853 [1 << 17]byte var z854 [1 << 17]byte var z855 [1 << 17]byte var z856 [1 << 17]byte var z857 [1 << 17]byte var z858 [1 << 17]byte var z859 [1 << 17]byte var z860 [1 << 17]byte var z861 [1 << 17]byte var z862 [1 << 17]byte var z863 [1 << 17]byte var z864 [1 << 17]byte var z865 [1 << 17]byte var z866 [1 << 17]byte var z867 [1 << 17]byte var z868 [1 << 17]byte var z869 [1 << 17]byte var z870 [1 << 17]byte var z871 [1 << 17]byte var z872 [1 << 17]byte var z873 [1 << 17]byte var z874 [1 << 17]byte var z875 [1 << 17]byte var z876 [1 << 17]byte var z877 [1 << 17]byte var z878 [1 << 17]byte var z879 [1 << 17]byte var z880 [1 << 17]byte var z881 [1 << 17]byte var z882 [1 << 17]byte var z883 [1 << 17]byte var z884 [1 << 17]byte var z885 [1 << 17]byte var z886 [1 << 17]byte var z887 [1 << 17]byte var z888 [1 << 17]byte var z889 [1 << 17]byte var z890 [1 << 17]byte var z891 [1 << 17]byte var z892 [1 << 17]byte var z893 [1 << 17]byte var z894 [1 << 17]byte var z895 [1 << 17]byte var z896 [1 << 17]byte var z897 [1 << 17]byte var z898 [1 << 17]byte var z899 [1 << 17]byte var z900 [1 << 17]byte var z901 [1 << 17]byte var z902 [1 << 17]byte var z903 [1 << 17]byte var z904 [1 << 17]byte var z905 [1 << 17]byte var z906 [1 << 17]byte var z907 [1 << 17]byte var z908 [1 << 17]byte var z909 [1 << 17]byte var z910 [1 << 17]byte var z911 [1 << 17]byte var z912 [1 << 17]byte var z913 [1 << 17]byte var z914 [1 << 17]byte var z915 [1 << 17]byte var z916 [1 << 17]byte var z917 [1 << 17]byte var z918 [1 << 17]byte var z919 [1 << 17]byte var z920 [1 << 17]byte var z921 [1 << 17]byte var z922 [1 << 17]byte var z923 [1 << 17]byte var z924 [1 << 17]byte var z925 [1 << 17]byte var z926 [1 << 17]byte var z927 [1 << 17]byte var z928 [1 << 17]byte var z929 [1 << 17]byte var z930 [1 << 17]byte var z931 [1 << 17]byte var z932 [1 << 17]byte var z933 [1 << 17]byte var z934 [1 << 17]byte var z935 [1 << 17]byte var z936 [1 << 17]byte var z937 [1 << 17]byte var z938 [1 << 17]byte var z939 [1 << 17]byte var z940 [1 << 17]byte var z941 [1 << 17]byte var z942 [1 << 17]byte var z943 [1 << 17]byte var z944 [1 << 17]byte var z945 [1 << 17]byte var z946 [1 << 17]byte var z947 [1 << 17]byte var z948 [1 << 17]byte var z949 [1 << 17]byte var z950 [1 << 17]byte var z951 [1 << 17]byte var z952 [1 << 17]byte var z953 [1 << 17]byte var z954 [1 << 17]byte var z955 [1 << 17]byte var z956 [1 << 17]byte var z957 [1 << 17]byte var z958 [1 << 17]byte var z959 [1 << 17]byte var z960 [1 << 17]byte var z961 [1 << 17]byte var z962 [1 << 17]byte var z963 [1 << 17]byte var z964 [1 << 17]byte var z965 [1 << 17]byte var z966 [1 << 17]byte var z967 [1 << 17]byte var z968 [1 << 17]byte var z969 [1 << 17]byte var z970 [1 << 17]byte var z971 [1 << 17]byte var z972 [1 << 17]byte var z973 [1 << 17]byte var z974 [1 << 17]byte var z975 [1 << 17]byte var z976 [1 << 17]byte var z977 [1 << 17]byte var z978 [1 << 17]byte var z979 [1 << 17]byte var z980 [1 << 17]byte var z981 [1 << 17]byte var z982 [1 << 17]byte var z983 [1 << 17]byte var z984 [1 << 17]byte var z985 [1 << 17]byte var z986 [1 << 17]byte var z987 [1 << 17]byte var z988 [1 << 17]byte var z989 [1 << 17]byte var z990 [1 << 17]byte var z991 [1 << 17]byte var z992 [1 << 17]byte var z993 [1 << 17]byte var z994 [1 << 17]byte var z995 [1 << 17]byte var z996 [1 << 17]byte var z997 [1 << 17]byte var z998 [1 << 17]byte var z999 [1 << 17]byte var z1000 [1 << 17]byte var z1001 [1 << 17]byte var z1002 [1 << 17]byte var z1003 [1 << 17]byte var z1004 [1 << 17]byte var z1005 [1 << 17]byte var z1006 [1 << 17]byte var z1007 [1 << 17]byte var z1008 [1 << 17]byte var z1009 [1 << 17]byte var z1010 [1 << 17]byte var z1011 [1 << 17]byte var z1012 [1 << 17]byte var z1013 [1 << 17]byte var z1014 [1 << 17]byte var z1015 [1 << 17]byte var z1016 [1 << 17]byte var z1017 [1 << 17]byte var z1018 [1 << 17]byte var z1019 [1 << 17]byte var z1020 [1 << 17]byte var z1021 [1 << 17]byte var z1022 [1 << 17]byte var z1023 [1 << 17]byte var z1024 [1 << 17]byte var z1025 [1 << 17]byte var z1026 [1 << 17]byte var z1027 [1 << 17]byte var z1028 [1 << 17]byte var z1029 [1 << 17]byte var z1030 [1 << 17]byte var z1031 [1 << 17]byte var z1032 [1 << 17]byte var z1033 [1 << 17]byte var z1034 [1 << 17]byte var z1035 [1 << 17]byte var z1036 [1 << 17]byte var z1037 [1 << 17]byte var z1038 [1 << 17]byte var z1039 [1 << 17]byte var z1040 [1 << 17]byte var z1041 [1 << 17]byte var z1042 [1 << 17]byte var z1043 [1 << 17]byte var z1044 [1 << 17]byte var z1045 [1 << 17]byte var z1046 [1 << 17]byte var z1047 [1 << 17]byte var z1048 [1 << 17]byte var z1049 [1 << 17]byte var z1050 [1 << 17]byte var z1051 [1 << 17]byte var z1052 [1 << 17]byte var z1053 [1 << 17]byte var z1054 [1 << 17]byte var z1055 [1 << 17]byte var z1056 [1 << 17]byte var z1057 [1 << 17]byte var z1058 [1 << 17]byte var z1059 [1 << 17]byte var z1060 [1 << 17]byte var z1061 [1 << 17]byte var z1062 [1 << 17]byte var z1063 [1 << 17]byte var z1064 [1 << 17]byte var z1065 [1 << 17]byte var z1066 [1 << 17]byte var z1067 [1 << 17]byte var z1068 [1 << 17]byte var z1069 [1 << 17]byte var z1070 [1 << 17]byte var z1071 [1 << 17]byte var z1072 [1 << 17]byte var z1073 [1 << 17]byte var z1074 [1 << 17]byte var z1075 [1 << 17]byte var z1076 [1 << 17]byte var z1077 [1 << 17]byte var z1078 [1 << 17]byte var z1079 [1 << 17]byte var z1080 [1 << 17]byte var z1081 [1 << 17]byte var z1082 [1 << 17]byte var z1083 [1 << 17]byte var z1084 [1 << 17]byte var z1085 [1 << 17]byte var z1086 [1 << 17]byte var z1087 [1 << 17]byte var z1088 [1 << 17]byte var z1089 [1 << 17]byte var z1090 [1 << 17]byte var z1091 [1 << 17]byte var z1092 [1 << 17]byte var z1093 [1 << 17]byte var z1094 [1 << 17]byte var z1095 [1 << 17]byte var z1096 [1 << 17]byte var z1097 [1 << 17]byte var z1098 [1 << 17]byte var z1099 [1 << 17]byte var z1100 [1 << 17]byte var z1101 [1 << 17]byte var z1102 [1 << 17]byte var z1103 [1 << 17]byte var z1104 [1 << 17]byte var z1105 [1 << 17]byte var z1106 [1 << 17]byte var z1107 [1 << 17]byte var z1108 [1 << 17]byte var z1109 [1 << 17]byte var z1110 [1 << 17]byte var z1111 [1 << 17]byte var z1112 [1 << 17]byte var z1113 [1 << 17]byte var z1114 [1 << 17]byte var z1115 [1 << 17]byte var z1116 [1 << 17]byte var z1117 [1 << 17]byte var z1118 [1 << 17]byte var z1119 [1 << 17]byte var z1120 [1 << 17]byte var z1121 [1 << 17]byte var z1122 [1 << 17]byte var z1123 [1 << 17]byte var z1124 [1 << 17]byte var z1125 [1 << 17]byte var z1126 [1 << 17]byte var z1127 [1 << 17]byte var z1128 [1 << 17]byte var z1129 [1 << 17]byte var z1130 [1 << 17]byte var z1131 [1 << 17]byte var z1132 [1 << 17]byte var z1133 [1 << 17]byte var z1134 [1 << 17]byte var z1135 [1 << 17]byte var z1136 [1 << 17]byte var z1137 [1 << 17]byte var z1138 [1 << 17]byte var z1139 [1 << 17]byte var z1140 [1 << 17]byte var z1141 [1 << 17]byte var z1142 [1 << 17]byte var z1143 [1 << 17]byte var z1144 [1 << 17]byte var z1145 [1 << 17]byte var z1146 [1 << 17]byte var z1147 [1 << 17]byte var z1148 [1 << 17]byte var z1149 [1 << 17]byte var z1150 [1 << 17]byte var z1151 [1 << 17]byte var z1152 [1 << 17]byte var z1153 [1 << 17]byte var z1154 [1 << 17]byte var z1155 [1 << 17]byte var z1156 [1 << 17]byte var z1157 [1 << 17]byte var z1158 [1 << 17]byte var z1159 [1 << 17]byte var z1160 [1 << 17]byte var z1161 [1 << 17]byte var z1162 [1 << 17]byte var z1163 [1 << 17]byte var z1164 [1 << 17]byte var z1165 [1 << 17]byte var z1166 [1 << 17]byte var z1167 [1 << 17]byte var z1168 [1 << 17]byte var z1169 [1 << 17]byte var z1170 [1 << 17]byte var z1171 [1 << 17]byte var z1172 [1 << 17]byte var z1173 [1 << 17]byte var z1174 [1 << 17]byte var z1175 [1 << 17]byte var z1176 [1 << 17]byte var z1177 [1 << 17]byte var z1178 [1 << 17]byte var z1179 [1 << 17]byte var z1180 [1 << 17]byte var z1181 [1 << 17]byte var z1182 [1 << 17]byte var z1183 [1 << 17]byte var z1184 [1 << 17]byte var z1185 [1 << 17]byte var z1186 [1 << 17]byte var z1187 [1 << 17]byte var z1188 [1 << 17]byte var z1189 [1 << 17]byte var z1190 [1 << 17]byte var z1191 [1 << 17]byte var z1192 [1 << 17]byte var z1193 [1 << 17]byte var z1194 [1 << 17]byte var z1195 [1 << 17]byte var z1196 [1 << 17]byte var z1197 [1 << 17]byte var z1198 [1 << 17]byte var z1199 [1 << 17]byte var z1200 [1 << 17]byte var z1201 [1 << 17]byte var z1202 [1 << 17]byte var z1203 [1 << 17]byte var z1204 [1 << 17]byte var z1205 [1 << 17]byte var z1206 [1 << 17]byte var z1207 [1 << 17]byte var z1208 [1 << 17]byte var z1209 [1 << 17]byte var z1210 [1 << 17]byte var z1211 [1 << 17]byte var z1212 [1 << 17]byte var z1213 [1 << 17]byte var z1214 [1 << 17]byte var z1215 [1 << 17]byte var z1216 [1 << 17]byte var z1217 [1 << 17]byte var z1218 [1 << 17]byte var z1219 [1 << 17]byte var z1220 [1 << 17]byte var z1221 [1 << 17]byte var z1222 [1 << 17]byte var z1223 [1 << 17]byte var z1224 [1 << 17]byte var z1225 [1 << 17]byte var z1226 [1 << 17]byte var z1227 [1 << 17]byte var z1228 [1 << 17]byte var z1229 [1 << 17]byte var z1230 [1 << 17]byte var z1231 [1 << 17]byte var z1232 [1 << 17]byte var z1233 [1 << 17]byte var z1234 [1 << 17]byte var z1235 [1 << 17]byte var z1236 [1 << 17]byte var z1237 [1 << 17]byte var z1238 [1 << 17]byte var z1239 [1 << 17]byte var z1240 [1 << 17]byte var z1241 [1 << 17]byte var z1242 [1 << 17]byte var z1243 [1 << 17]byte var z1244 [1 << 17]byte var z1245 [1 << 17]byte var z1246 [1 << 17]byte var z1247 [1 << 17]byte var z1248 [1 << 17]byte var z1249 [1 << 17]byte var z1250 [1 << 17]byte var z1251 [1 << 17]byte var z1252 [1 << 17]byte var z1253 [1 << 17]byte var z1254 [1 << 17]byte var z1255 [1 << 17]byte var z1256 [1 << 17]byte var z1257 [1 << 17]byte var z1258 [1 << 17]byte var z1259 [1 << 17]byte var z1260 [1 << 17]byte var z1261 [1 << 17]byte var z1262 [1 << 17]byte var z1263 [1 << 17]byte var z1264 [1 << 17]byte var z1265 [1 << 17]byte var z1266 [1 << 17]byte var z1267 [1 << 17]byte var z1268 [1 << 17]byte var z1269 [1 << 17]byte var z1270 [1 << 17]byte var z1271 [1 << 17]byte var z1272 [1 << 17]byte var z1273 [1 << 17]byte var z1274 [1 << 17]byte var z1275 [1 << 17]byte var z1276 [1 << 17]byte var z1277 [1 << 17]byte var z1278 [1 << 17]byte var z1279 [1 << 17]byte var z1280 [1 << 17]byte var z1281 [1 << 17]byte var z1282 [1 << 17]byte var z1283 [1 << 17]byte var z1284 [1 << 17]byte var z1285 [1 << 17]byte var z1286 [1 << 17]byte var z1287 [1 << 17]byte var z1288 [1 << 17]byte var z1289 [1 << 17]byte var z1290 [1 << 17]byte var z1291 [1 << 17]byte var z1292 [1 << 17]byte var z1293 [1 << 17]byte var z1294 [1 << 17]byte var z1295 [1 << 17]byte var z1296 [1 << 17]byte var z1297 [1 << 17]byte var z1298 [1 << 17]byte var z1299 [1 << 17]byte var z1300 [1 << 17]byte var z1301 [1 << 17]byte var z1302 [1 << 17]byte var z1303 [1 << 17]byte var z1304 [1 << 17]byte var z1305 [1 << 17]byte var z1306 [1 << 17]byte var z1307 [1 << 17]byte var z1308 [1 << 17]byte var z1309 [1 << 17]byte var z1310 [1 << 17]byte var z1311 [1 << 17]byte var z1312 [1 << 17]byte var z1313 [1 << 17]byte var z1314 [1 << 17]byte var z1315 [1 << 17]byte var z1316 [1 << 17]byte var z1317 [1 << 17]byte var z1318 [1 << 17]byte var z1319 [1 << 17]byte var z1320 [1 << 17]byte var z1321 [1 << 17]byte var z1322 [1 << 17]byte var z1323 [1 << 17]byte var z1324 [1 << 17]byte var z1325 [1 << 17]byte var z1326 [1 << 17]byte var z1327 [1 << 17]byte var z1328 [1 << 17]byte var z1329 [1 << 17]byte var z1330 [1 << 17]byte var z1331 [1 << 17]byte var z1332 [1 << 17]byte var z1333 [1 << 17]byte var z1334 [1 << 17]byte var z1335 [1 << 17]byte var z1336 [1 << 17]byte var z1337 [1 << 17]byte var z1338 [1 << 17]byte var z1339 [1 << 17]byte var z1340 [1 << 17]byte var z1341 [1 << 17]byte var z1342 [1 << 17]byte var z1343 [1 << 17]byte var z1344 [1 << 17]byte var z1345 [1 << 17]byte var z1346 [1 << 17]byte var z1347 [1 << 17]byte var z1348 [1 << 17]byte var z1349 [1 << 17]byte var z1350 [1 << 17]byte var z1351 [1 << 17]byte var z1352 [1 << 17]byte var z1353 [1 << 17]byte var z1354 [1 << 17]byte var z1355 [1 << 17]byte var z1356 [1 << 17]byte var z1357 [1 << 17]byte var z1358 [1 << 17]byte var z1359 [1 << 17]byte var z1360 [1 << 17]byte var z1361 [1 << 17]byte var z1362 [1 << 17]byte var z1363 [1 << 17]byte var z1364 [1 << 17]byte var z1365 [1 << 17]byte var z1366 [1 << 17]byte var z1367 [1 << 17]byte var z1368 [1 << 17]byte var z1369 [1 << 17]byte var z1370 [1 << 17]byte var z1371 [1 << 17]byte var z1372 [1 << 17]byte var z1373 [1 << 17]byte var z1374 [1 << 17]byte var z1375 [1 << 17]byte var z1376 [1 << 17]byte var z1377 [1 << 17]byte var z1378 [1 << 17]byte var z1379 [1 << 17]byte var z1380 [1 << 17]byte var z1381 [1 << 17]byte var z1382 [1 << 17]byte var z1383 [1 << 17]byte var z1384 [1 << 17]byte var z1385 [1 << 17]byte var z1386 [1 << 17]byte var z1387 [1 << 17]byte var z1388 [1 << 17]byte var z1389 [1 << 17]byte var z1390 [1 << 17]byte var z1391 [1 << 17]byte var z1392 [1 << 17]byte var z1393 [1 << 17]byte var z1394 [1 << 17]byte var z1395 [1 << 17]byte var z1396 [1 << 17]byte var z1397 [1 << 17]byte var z1398 [1 << 17]byte var z1399 [1 << 17]byte var z1400 [1 << 17]byte var z1401 [1 << 17]byte var z1402 [1 << 17]byte var z1403 [1 << 17]byte var z1404 [1 << 17]byte var z1405 [1 << 17]byte var z1406 [1 << 17]byte var z1407 [1 << 17]byte var z1408 [1 << 17]byte var z1409 [1 << 17]byte var z1410 [1 << 17]byte var z1411 [1 << 17]byte var z1412 [1 << 17]byte var z1413 [1 << 17]byte var z1414 [1 << 17]byte var z1415 [1 << 17]byte var z1416 [1 << 17]byte var z1417 [1 << 17]byte var z1418 [1 << 17]byte var z1419 [1 << 17]byte var z1420 [1 << 17]byte var z1421 [1 << 17]byte var z1422 [1 << 17]byte var z1423 [1 << 17]byte var z1424 [1 << 17]byte var z1425 [1 << 17]byte var z1426 [1 << 17]byte var z1427 [1 << 17]byte var z1428 [1 << 17]byte var z1429 [1 << 17]byte var z1430 [1 << 17]byte var z1431 [1 << 17]byte var z1432 [1 << 17]byte var z1433 [1 << 17]byte var z1434 [1 << 17]byte var z1435 [1 << 17]byte var z1436 [1 << 17]byte var z1437 [1 << 17]byte var z1438 [1 << 17]byte var z1439 [1 << 17]byte var z1440 [1 << 17]byte var z1441 [1 << 17]byte var z1442 [1 << 17]byte var z1443 [1 << 17]byte var z1444 [1 << 17]byte var z1445 [1 << 17]byte var z1446 [1 << 17]byte var z1447 [1 << 17]byte var z1448 [1 << 17]byte var z1449 [1 << 17]byte var z1450 [1 << 17]byte var z1451 [1 << 17]byte var z1452 [1 << 17]byte var z1453 [1 << 17]byte var z1454 [1 << 17]byte var z1455 [1 << 17]byte var z1456 [1 << 17]byte var z1457 [1 << 17]byte var z1458 [1 << 17]byte var z1459 [1 << 17]byte var z1460 [1 << 17]byte var z1461 [1 << 17]byte var z1462 [1 << 17]byte var z1463 [1 << 17]byte var z1464 [1 << 17]byte var z1465 [1 << 17]byte var z1466 [1 << 17]byte var z1467 [1 << 17]byte var z1468 [1 << 17]byte var z1469 [1 << 17]byte var z1470 [1 << 17]byte var z1471 [1 << 17]byte var z1472 [1 << 17]byte var z1473 [1 << 17]byte var z1474 [1 << 17]byte var z1475 [1 << 17]byte var z1476 [1 << 17]byte var z1477 [1 << 17]byte var z1478 [1 << 17]byte var z1479 [1 << 17]byte var z1480 [1 << 17]byte var z1481 [1 << 17]byte var z1482 [1 << 17]byte var z1483 [1 << 17]byte var z1484 [1 << 17]byte var z1485 [1 << 17]byte var z1486 [1 << 17]byte var z1487 [1 << 17]byte var z1488 [1 << 17]byte var z1489 [1 << 17]byte var z1490 [1 << 17]byte var z1491 [1 << 17]byte var z1492 [1 << 17]byte var z1493 [1 << 17]byte var z1494 [1 << 17]byte var z1495 [1 << 17]byte var z1496 [1 << 17]byte var z1497 [1 << 17]byte var z1498 [1 << 17]byte var z1499 [1 << 17]byte var z1500 [1 << 17]byte var z1501 [1 << 17]byte var z1502 [1 << 17]byte var z1503 [1 << 17]byte var z1504 [1 << 17]byte var z1505 [1 << 17]byte var z1506 [1 << 17]byte var z1507 [1 << 17]byte var z1508 [1 << 17]byte var z1509 [1 << 17]byte var z1510 [1 << 17]byte var z1511 [1 << 17]byte var z1512 [1 << 17]byte var z1513 [1 << 17]byte var z1514 [1 << 17]byte var z1515 [1 << 17]byte var z1516 [1 << 17]byte var z1517 [1 << 17]byte var z1518 [1 << 17]byte var z1519 [1 << 17]byte var z1520 [1 << 17]byte var z1521 [1 << 17]byte var z1522 [1 << 17]byte var z1523 [1 << 17]byte var z1524 [1 << 17]byte var z1525 [1 << 17]byte var z1526 [1 << 17]byte var z1527 [1 << 17]byte var z1528 [1 << 17]byte var z1529 [1 << 17]byte var z1530 [1 << 17]byte var z1531 [1 << 17]byte var z1532 [1 << 17]byte var z1533 [1 << 17]byte var z1534 [1 << 17]byte var z1535 [1 << 17]byte var z1536 [1 << 17]byte var z1537 [1 << 17]byte var z1538 [1 << 17]byte var z1539 [1 << 17]byte var z1540 [1 << 17]byte var z1541 [1 << 17]byte var z1542 [1 << 17]byte var z1543 [1 << 17]byte var z1544 [1 << 17]byte var z1545 [1 << 17]byte var z1546 [1 << 17]byte var z1547 [1 << 17]byte var z1548 [1 << 17]byte var z1549 [1 << 17]byte var z1550 [1 << 17]byte var z1551 [1 << 17]byte var z1552 [1 << 17]byte var z1553 [1 << 17]byte var z1554 [1 << 17]byte var z1555 [1 << 17]byte var z1556 [1 << 17]byte var z1557 [1 << 17]byte var z1558 [1 << 17]byte var z1559 [1 << 17]byte var z1560 [1 << 17]byte var z1561 [1 << 17]byte var z1562 [1 << 17]byte var z1563 [1 << 17]byte var z1564 [1 << 17]byte var z1565 [1 << 17]byte var z1566 [1 << 17]byte var z1567 [1 << 17]byte var z1568 [1 << 17]byte var z1569 [1 << 17]byte var z1570 [1 << 17]byte var z1571 [1 << 17]byte var z1572 [1 << 17]byte var z1573 [1 << 17]byte var z1574 [1 << 17]byte var z1575 [1 << 17]byte var z1576 [1 << 17]byte var z1577 [1 << 17]byte var z1578 [1 << 17]byte var z1579 [1 << 17]byte var z1580 [1 << 17]byte var z1581 [1 << 17]byte var z1582 [1 << 17]byte var z1583 [1 << 17]byte var z1584 [1 << 17]byte var z1585 [1 << 17]byte var z1586 [1 << 17]byte var z1587 [1 << 17]byte var z1588 [1 << 17]byte var z1589 [1 << 17]byte var z1590 [1 << 17]byte var z1591 [1 << 17]byte var z1592 [1 << 17]byte var z1593 [1 << 17]byte var z1594 [1 << 17]byte var z1595 [1 << 17]byte var z1596 [1 << 17]byte var z1597 [1 << 17]byte var z1598 [1 << 17]byte var z1599 [1 << 17]byte var z1600 [1 << 17]byte var z1601 [1 << 17]byte var z1602 [1 << 17]byte var z1603 [1 << 17]byte var z1604 [1 << 17]byte var z1605 [1 << 17]byte var z1606 [1 << 17]byte var z1607 [1 << 17]byte var z1608 [1 << 17]byte var z1609 [1 << 17]byte var z1610 [1 << 17]byte var z1611 [1 << 17]byte var z1612 [1 << 17]byte var z1613 [1 << 17]byte var z1614 [1 << 17]byte var z1615 [1 << 17]byte var z1616 [1 << 17]byte var z1617 [1 << 17]byte var z1618 [1 << 17]byte var z1619 [1 << 17]byte var z1620 [1 << 17]byte var z1621 [1 << 17]byte var z1622 [1 << 17]byte var z1623 [1 << 17]byte var z1624 [1 << 17]byte var z1625 [1 << 17]byte var z1626 [1 << 17]byte var z1627 [1 << 17]byte var z1628 [1 << 17]byte var z1629 [1 << 17]byte var z1630 [1 << 17]byte var z1631 [1 << 17]byte var z1632 [1 << 17]byte var z1633 [1 << 17]byte var z1634 [1 << 17]byte var z1635 [1 << 17]byte var z1636 [1 << 17]byte var z1637 [1 << 17]byte var z1638 [1 << 17]byte var z1639 [1 << 17]byte var z1640 [1 << 17]byte var z1641 [1 << 17]byte var z1642 [1 << 17]byte var z1643 [1 << 17]byte var z1644 [1 << 17]byte var z1645 [1 << 17]byte var z1646 [1 << 17]byte var z1647 [1 << 17]byte var z1648 [1 << 17]byte var z1649 [1 << 17]byte var z1650 [1 << 17]byte var z1651 [1 << 17]byte var z1652 [1 << 17]byte var z1653 [1 << 17]byte var z1654 [1 << 17]byte var z1655 [1 << 17]byte var z1656 [1 << 17]byte var z1657 [1 << 17]byte var z1658 [1 << 17]byte var z1659 [1 << 17]byte var z1660 [1 << 17]byte var z1661 [1 << 17]byte var z1662 [1 << 17]byte var z1663 [1 << 17]byte var z1664 [1 << 17]byte var z1665 [1 << 17]byte var z1666 [1 << 17]byte var z1667 [1 << 17]byte var z1668 [1 << 17]byte var z1669 [1 << 17]byte var z1670 [1 << 17]byte var z1671 [1 << 17]byte var z1672 [1 << 17]byte var z1673 [1 << 17]byte var z1674 [1 << 17]byte var z1675 [1 << 17]byte var z1676 [1 << 17]byte var z1677 [1 << 17]byte var z1678 [1 << 17]byte var z1679 [1 << 17]byte var z1680 [1 << 17]byte var z1681 [1 << 17]byte var z1682 [1 << 17]byte var z1683 [1 << 17]byte var z1684 [1 << 17]byte var z1685 [1 << 17]byte var z1686 [1 << 17]byte var z1687 [1 << 17]byte var z1688 [1 << 17]byte var z1689 [1 << 17]byte var z1690 [1 << 17]byte var z1691 [1 << 17]byte var z1692 [1 << 17]byte var z1693 [1 << 17]byte var z1694 [1 << 17]byte var z1695 [1 << 17]byte var z1696 [1 << 17]byte var z1697 [1 << 17]byte var z1698 [1 << 17]byte var z1699 [1 << 17]byte var z1700 [1 << 17]byte var z1701 [1 << 17]byte var z1702 [1 << 17]byte var z1703 [1 << 17]byte var z1704 [1 << 17]byte var z1705 [1 << 17]byte var z1706 [1 << 17]byte var z1707 [1 << 17]byte var z1708 [1 << 17]byte var z1709 [1 << 17]byte var z1710 [1 << 17]byte var z1711 [1 << 17]byte var z1712 [1 << 17]byte var z1713 [1 << 17]byte var z1714 [1 << 17]byte var z1715 [1 << 17]byte var z1716 [1 << 17]byte var z1717 [1 << 17]byte var z1718 [1 << 17]byte var z1719 [1 << 17]byte var z1720 [1 << 17]byte var z1721 [1 << 17]byte var z1722 [1 << 17]byte var z1723 [1 << 17]byte var z1724 [1 << 17]byte var z1725 [1 << 17]byte var z1726 [1 << 17]byte var z1727 [1 << 17]byte var z1728 [1 << 17]byte var z1729 [1 << 17]byte var z1730 [1 << 17]byte var z1731 [1 << 17]byte var z1732 [1 << 17]byte var z1733 [1 << 17]byte var z1734 [1 << 17]byte var z1735 [1 << 17]byte var z1736 [1 << 17]byte var z1737 [1 << 17]byte var z1738 [1 << 17]byte var z1739 [1 << 17]byte var z1740 [1 << 17]byte var z1741 [1 << 17]byte var z1742 [1 << 17]byte var z1743 [1 << 17]byte var z1744 [1 << 17]byte var z1745 [1 << 17]byte var z1746 [1 << 17]byte var z1747 [1 << 17]byte var z1748 [1 << 17]byte var z1749 [1 << 17]byte var z1750 [1 << 17]byte var z1751 [1 << 17]byte var z1752 [1 << 17]byte var z1753 [1 << 17]byte var z1754 [1 << 17]byte var z1755 [1 << 17]byte var z1756 [1 << 17]byte var z1757 [1 << 17]byte var z1758 [1 << 17]byte var z1759 [1 << 17]byte var z1760 [1 << 17]byte var z1761 [1 << 17]byte var z1762 [1 << 17]byte var z1763 [1 << 17]byte var z1764 [1 << 17]byte var z1765 [1 << 17]byte var z1766 [1 << 17]byte var z1767 [1 << 17]byte var z1768 [1 << 17]byte var z1769 [1 << 17]byte var z1770 [1 << 17]byte var z1771 [1 << 17]byte var z1772 [1 << 17]byte var z1773 [1 << 17]byte var z1774 [1 << 17]byte var z1775 [1 << 17]byte var z1776 [1 << 17]byte var z1777 [1 << 17]byte var z1778 [1 << 17]byte var z1779 [1 << 17]byte var z1780 [1 << 17]byte var z1781 [1 << 17]byte var z1782 [1 << 17]byte var z1783 [1 << 17]byte var z1784 [1 << 17]byte var z1785 [1 << 17]byte var z1786 [1 << 17]byte var z1787 [1 << 17]byte var z1788 [1 << 17]byte var z1789 [1 << 17]byte var z1790 [1 << 17]byte var z1791 [1 << 17]byte var z1792 [1 << 17]byte var z1793 [1 << 17]byte var z1794 [1 << 17]byte var z1795 [1 << 17]byte var z1796 [1 << 17]byte var z1797 [1 << 17]byte var z1798 [1 << 17]byte var z1799 [1 << 17]byte var z1800 [1 << 17]byte var z1801 [1 << 17]byte var z1802 [1 << 17]byte var z1803 [1 << 17]byte var z1804 [1 << 17]byte var z1805 [1 << 17]byte var z1806 [1 << 17]byte var z1807 [1 << 17]byte var z1808 [1 << 17]byte var z1809 [1 << 17]byte var z1810 [1 << 17]byte var z1811 [1 << 17]byte var z1812 [1 << 17]byte var z1813 [1 << 17]byte var z1814 [1 << 17]byte var z1815 [1 << 17]byte var z1816 [1 << 17]byte var z1817 [1 << 17]byte var z1818 [1 << 17]byte var z1819 [1 << 17]byte var z1820 [1 << 17]byte var z1821 [1 << 17]byte var z1822 [1 << 17]byte var z1823 [1 << 17]byte var z1824 [1 << 17]byte var z1825 [1 << 17]byte var z1826 [1 << 17]byte var z1827 [1 << 17]byte var z1828 [1 << 17]byte var z1829 [1 << 17]byte var z1830 [1 << 17]byte var z1831 [1 << 17]byte var z1832 [1 << 17]byte var z1833 [1 << 17]byte var z1834 [1 << 17]byte var z1835 [1 << 17]byte var z1836 [1 << 17]byte var z1837 [1 << 17]byte var z1838 [1 << 17]byte var z1839 [1 << 17]byte var z1840 [1 << 17]byte var z1841 [1 << 17]byte var z1842 [1 << 17]byte var z1843 [1 << 17]byte var z1844 [1 << 17]byte var z1845 [1 << 17]byte var z1846 [1 << 17]byte var z1847 [1 << 17]byte var z1848 [1 << 17]byte var z1849 [1 << 17]byte var z1850 [1 << 17]byte var z1851 [1 << 17]byte var z1852 [1 << 17]byte var z1853 [1 << 17]byte var z1854 [1 << 17]byte var z1855 [1 << 17]byte var z1856 [1 << 17]byte var z1857 [1 << 17]byte var z1858 [1 << 17]byte var z1859 [1 << 17]byte var z1860 [1 << 17]byte var z1861 [1 << 17]byte var z1862 [1 << 17]byte var z1863 [1 << 17]byte var z1864 [1 << 17]byte var z1865 [1 << 17]byte var z1866 [1 << 17]byte var z1867 [1 << 17]byte var z1868 [1 << 17]byte var z1869 [1 << 17]byte var z1870 [1 << 17]byte var z1871 [1 << 17]byte var z1872 [1 << 17]byte var z1873 [1 << 17]byte var z1874 [1 << 17]byte var z1875 [1 << 17]byte var z1876 [1 << 17]byte var z1877 [1 << 17]byte var z1878 [1 << 17]byte var z1879 [1 << 17]byte var z1880 [1 << 17]byte var z1881 [1 << 17]byte var z1882 [1 << 17]byte var z1883 [1 << 17]byte var z1884 [1 << 17]byte var z1885 [1 << 17]byte var z1886 [1 << 17]byte var z1887 [1 << 17]byte var z1888 [1 << 17]byte var z1889 [1 << 17]byte var z1890 [1 << 17]byte var z1891 [1 << 17]byte var z1892 [1 << 17]byte var z1893 [1 << 17]byte var z1894 [1 << 17]byte var z1895 [1 << 17]byte var z1896 [1 << 17]byte var z1897 [1 << 17]byte var z1898 [1 << 17]byte var z1899 [1 << 17]byte var z1900 [1 << 17]byte var z1901 [1 << 17]byte var z1902 [1 << 17]byte var z1903 [1 << 17]byte var z1904 [1 << 17]byte var z1905 [1 << 17]byte var z1906 [1 << 17]byte var z1907 [1 << 17]byte var z1908 [1 << 17]byte var z1909 [1 << 17]byte var z1910 [1 << 17]byte var z1911 [1 << 17]byte var z1912 [1 << 17]byte var z1913 [1 << 17]byte var z1914 [1 << 17]byte var z1915 [1 << 17]byte var z1916 [1 << 17]byte var z1917 [1 << 17]byte var z1918 [1 << 17]byte var z1919 [1 << 17]byte var z1920 [1 << 17]byte var z1921 [1 << 17]byte var z1922 [1 << 17]byte var z1923 [1 << 17]byte var z1924 [1 << 17]byte var z1925 [1 << 17]byte var z1926 [1 << 17]byte var z1927 [1 << 17]byte var z1928 [1 << 17]byte var z1929 [1 << 17]byte var z1930 [1 << 17]byte var z1931 [1 << 17]byte var z1932 [1 << 17]byte var z1933 [1 << 17]byte var z1934 [1 << 17]byte var z1935 [1 << 17]byte var z1936 [1 << 17]byte var z1937 [1 << 17]byte var z1938 [1 << 17]byte var z1939 [1 << 17]byte var z1940 [1 << 17]byte var z1941 [1 << 17]byte var z1942 [1 << 17]byte var z1943 [1 << 17]byte var z1944 [1 << 17]byte var z1945 [1 << 17]byte var z1946 [1 << 17]byte var z1947 [1 << 17]byte var z1948 [1 << 17]byte var z1949 [1 << 17]byte var z1950 [1 << 17]byte var z1951 [1 << 17]byte var z1952 [1 << 17]byte var z1953 [1 << 17]byte var z1954 [1 << 17]byte var z1955 [1 << 17]byte var z1956 [1 << 17]byte var z1957 [1 << 17]byte var z1958 [1 << 17]byte var z1959 [1 << 17]byte var z1960 [1 << 17]byte var z1961 [1 << 17]byte var z1962 [1 << 17]byte var z1963 [1 << 17]byte var z1964 [1 << 17]byte var z1965 [1 << 17]byte var z1966 [1 << 17]byte var z1967 [1 << 17]byte var z1968 [1 << 17]byte var z1969 [1 << 17]byte var z1970 [1 << 17]byte var z1971 [1 << 17]byte var z1972 [1 << 17]byte var z1973 [1 << 17]byte var z1974 [1 << 17]byte var z1975 [1 << 17]byte var z1976 [1 << 17]byte var z1977 [1 << 17]byte var z1978 [1 << 17]byte var z1979 [1 << 17]byte var z1980 [1 << 17]byte var z1981 [1 << 17]byte var z1982 [1 << 17]byte var z1983 [1 << 17]byte var z1984 [1 << 17]byte var z1985 [1 << 17]byte var z1986 [1 << 17]byte var z1987 [1 << 17]byte var z1988 [1 << 17]byte var z1989 [1 << 17]byte var z1990 [1 << 17]byte var z1991 [1 << 17]byte var z1992 [1 << 17]byte var z1993 [1 << 17]byte var z1994 [1 << 17]byte var z1995 [1 << 17]byte var z1996 [1 << 17]byte var z1997 [1 << 17]byte var z1998 [1 << 17]byte var z1999 [1 << 17]byte var z2000 [1 << 17]byte var z2001 [1 << 17]byte var z2002 [1 << 17]byte var z2003 [1 << 17]byte var z2004 [1 << 17]byte var z2005 [1 << 17]byte var z2006 [1 << 17]byte var z2007 [1 << 17]byte var z2008 [1 << 17]byte var z2009 [1 << 17]byte var z2010 [1 << 17]byte var z2011 [1 << 17]byte var z2012 [1 << 17]byte var z2013 [1 << 17]byte var z2014 [1 << 17]byte var z2015 [1 << 17]byte var z2016 [1 << 17]byte var z2017 [1 << 17]byte var z2018 [1 << 17]byte var z2019 [1 << 17]byte var z2020 [1 << 17]byte var z2021 [1 << 17]byte var z2022 [1 << 17]byte var z2023 [1 << 17]byte var z2024 [1 << 17]byte var z2025 [1 << 17]byte var z2026 [1 << 17]byte var z2027 [1 << 17]byte var z2028 [1 << 17]byte var z2029 [1 << 17]byte var z2030 [1 << 17]byte var z2031 [1 << 17]byte var z2032 [1 << 17]byte var z2033 [1 << 17]byte var z2034 [1 << 17]byte var z2035 [1 << 17]byte var z2036 [1 << 17]byte var z2037 [1 << 17]byte var z2038 [1 << 17]byte var z2039 [1 << 17]byte var z2040 [1 << 17]byte var z2041 [1 << 17]byte var z2042 [1 << 17]byte var z2043 [1 << 17]byte var z2044 [1 << 17]byte var z2045 [1 << 17]byte var z2046 [1 << 17]byte var z2047 [1 << 17]byte var z2048 [1 << 17]byte var z2049 [1 << 17]byte var z2050 [1 << 17]byte var z2051 [1 << 17]byte var z2052 [1 << 17]byte var z2053 [1 << 17]byte var z2054 [1 << 17]byte var z2055 [1 << 17]byte var z2056 [1 << 17]byte var z2057 [1 << 17]byte var z2058 [1 << 17]byte var z2059 [1 << 17]byte var z2060 [1 << 17]byte var z2061 [1 << 17]byte var z2062 [1 << 17]byte var z2063 [1 << 17]byte var z2064 [1 << 17]byte var z2065 [1 << 17]byte var z2066 [1 << 17]byte var z2067 [1 << 17]byte var z2068 [1 << 17]byte var z2069 [1 << 17]byte var z2070 [1 << 17]byte var z2071 [1 << 17]byte var z2072 [1 << 17]byte var z2073 [1 << 17]byte var z2074 [1 << 17]byte var z2075 [1 << 17]byte var z2076 [1 << 17]byte var z2077 [1 << 17]byte var z2078 [1 << 17]byte var z2079 [1 << 17]byte var z2080 [1 << 17]byte var z2081 [1 << 17]byte var z2082 [1 << 17]byte var z2083 [1 << 17]byte var z2084 [1 << 17]byte var z2085 [1 << 17]byte var z2086 [1 << 17]byte var z2087 [1 << 17]byte var z2088 [1 << 17]byte var z2089 [1 << 17]byte var z2090 [1 << 17]byte var z2091 [1 << 17]byte var z2092 [1 << 17]byte var z2093 [1 << 17]byte var z2094 [1 << 17]byte var z2095 [1 << 17]byte var z2096 [1 << 17]byte var z2097 [1 << 17]byte var z2098 [1 << 17]byte var z2099 [1 << 17]byte var z2100 [1 << 17]byte var z2101 [1 << 17]byte var z2102 [1 << 17]byte var z2103 [1 << 17]byte var z2104 [1 << 17]byte var z2105 [1 << 17]byte var z2106 [1 << 17]byte var z2107 [1 << 17]byte var z2108 [1 << 17]byte var z2109 [1 << 17]byte var z2110 [1 << 17]byte var z2111 [1 << 17]byte var z2112 [1 << 17]byte var z2113 [1 << 17]byte var z2114 [1 << 17]byte var z2115 [1 << 17]byte var z2116 [1 << 17]byte var z2117 [1 << 17]byte var z2118 [1 << 17]byte var z2119 [1 << 17]byte var z2120 [1 << 17]byte var z2121 [1 << 17]byte var z2122 [1 << 17]byte var z2123 [1 << 17]byte var z2124 [1 << 17]byte var z2125 [1 << 17]byte var z2126 [1 << 17]byte var z2127 [1 << 17]byte var z2128 [1 << 17]byte var z2129 [1 << 17]byte var z2130 [1 << 17]byte var z2131 [1 << 17]byte var z2132 [1 << 17]byte var z2133 [1 << 17]byte var z2134 [1 << 17]byte var z2135 [1 << 17]byte var z2136 [1 << 17]byte var z2137 [1 << 17]byte var z2138 [1 << 17]byte var z2139 [1 << 17]byte var z2140 [1 << 17]byte var z2141 [1 << 17]byte var z2142 [1 << 17]byte var z2143 [1 << 17]byte var z2144 [1 << 17]byte var z2145 [1 << 17]byte var z2146 [1 << 17]byte var z2147 [1 << 17]byte var z2148 [1 << 17]byte var z2149 [1 << 17]byte var z2150 [1 << 17]byte var z2151 [1 << 17]byte var z2152 [1 << 17]byte var z2153 [1 << 17]byte var z2154 [1 << 17]byte var z2155 [1 << 17]byte var z2156 [1 << 17]byte var z2157 [1 << 17]byte var z2158 [1 << 17]byte var z2159 [1 << 17]byte var z2160 [1 << 17]byte var z2161 [1 << 17]byte var z2162 [1 << 17]byte var z2163 [1 << 17]byte var z2164 [1 << 17]byte var z2165 [1 << 17]byte var z2166 [1 << 17]byte var z2167 [1 << 17]byte var z2168 [1 << 17]byte var z2169 [1 << 17]byte var z2170 [1 << 17]byte var z2171 [1 << 17]byte var z2172 [1 << 17]byte var z2173 [1 << 17]byte var z2174 [1 << 17]byte var z2175 [1 << 17]byte var z2176 [1 << 17]byte var z2177 [1 << 17]byte var z2178 [1 << 17]byte var z2179 [1 << 17]byte var z2180 [1 << 17]byte var z2181 [1 << 17]byte var z2182 [1 << 17]byte var z2183 [1 << 17]byte var z2184 [1 << 17]byte var z2185 [1 << 17]byte var z2186 [1 << 17]byte var z2187 [1 << 17]byte var z2188 [1 << 17]byte var z2189 [1 << 17]byte var z2190 [1 << 17]byte var z2191 [1 << 17]byte var z2192 [1 << 17]byte var z2193 [1 << 17]byte var z2194 [1 << 17]byte var z2195 [1 << 17]byte var z2196 [1 << 17]byte var z2197 [1 << 17]byte var z2198 [1 << 17]byte var z2199 [1 << 17]byte var z2200 [1 << 17]byte var z2201 [1 << 17]byte var z2202 [1 << 17]byte var z2203 [1 << 17]byte var z2204 [1 << 17]byte var z2205 [1 << 17]byte var z2206 [1 << 17]byte var z2207 [1 << 17]byte var z2208 [1 << 17]byte var z2209 [1 << 17]byte var z2210 [1 << 17]byte var z2211 [1 << 17]byte var z2212 [1 << 17]byte var z2213 [1 << 17]byte var z2214 [1 << 17]byte var z2215 [1 << 17]byte var z2216 [1 << 17]byte var z2217 [1 << 17]byte var z2218 [1 << 17]byte var z2219 [1 << 17]byte var z2220 [1 << 17]byte var z2221 [1 << 17]byte var z2222 [1 << 17]byte var z2223 [1 << 17]byte var z2224 [1 << 17]byte var z2225 [1 << 17]byte var z2226 [1 << 17]byte var z2227 [1 << 17]byte var z2228 [1 << 17]byte var z2229 [1 << 17]byte var z2230 [1 << 17]byte var z2231 [1 << 17]byte var z2232 [1 << 17]byte var z2233 [1 << 17]byte var z2234 [1 << 17]byte var z2235 [1 << 17]byte var z2236 [1 << 17]byte var z2237 [1 << 17]byte var z2238 [1 << 17]byte var z2239 [1 << 17]byte var z2240 [1 << 17]byte var z2241 [1 << 17]byte var z2242 [1 << 17]byte var z2243 [1 << 17]byte var z2244 [1 << 17]byte var z2245 [1 << 17]byte var z2246 [1 << 17]byte var z2247 [1 << 17]byte var z2248 [1 << 17]byte var z2249 [1 << 17]byte var z2250 [1 << 17]byte var z2251 [1 << 17]byte var z2252 [1 << 17]byte var z2253 [1 << 17]byte var z2254 [1 << 17]byte var z2255 [1 << 17]byte var z2256 [1 << 17]byte var z2257 [1 << 17]byte var z2258 [1 << 17]byte var z2259 [1 << 17]byte var z2260 [1 << 17]byte var z2261 [1 << 17]byte var z2262 [1 << 17]byte var z2263 [1 << 17]byte var z2264 [1 << 17]byte var z2265 [1 << 17]byte var z2266 [1 << 17]byte var z2267 [1 << 17]byte var z2268 [1 << 17]byte var z2269 [1 << 17]byte var z2270 [1 << 17]byte var z2271 [1 << 17]byte var z2272 [1 << 17]byte var z2273 [1 << 17]byte var z2274 [1 << 17]byte var z2275 [1 << 17]byte var z2276 [1 << 17]byte var z2277 [1 << 17]byte var z2278 [1 << 17]byte var z2279 [1 << 17]byte var z2280 [1 << 17]byte var z2281 [1 << 17]byte var z2282 [1 << 17]byte var z2283 [1 << 17]byte var z2284 [1 << 17]byte var z2285 [1 << 17]byte var z2286 [1 << 17]byte var z2287 [1 << 17]byte var z2288 [1 << 17]byte var z2289 [1 << 17]byte var z2290 [1 << 17]byte var z2291 [1 << 17]byte var z2292 [1 << 17]byte var z2293 [1 << 17]byte var z2294 [1 << 17]byte var z2295 [1 << 17]byte var z2296 [1 << 17]byte var z2297 [1 << 17]byte var z2298 [1 << 17]byte var z2299 [1 << 17]byte var z2300 [1 << 17]byte var z2301 [1 << 17]byte var z2302 [1 << 17]byte var z2303 [1 << 17]byte var z2304 [1 << 17]byte var z2305 [1 << 17]byte var z2306 [1 << 17]byte var z2307 [1 << 17]byte var z2308 [1 << 17]byte var z2309 [1 << 17]byte var z2310 [1 << 17]byte var z2311 [1 << 17]byte var z2312 [1 << 17]byte var z2313 [1 << 17]byte var z2314 [1 << 17]byte var z2315 [1 << 17]byte var z2316 [1 << 17]byte var z2317 [1 << 17]byte var z2318 [1 << 17]byte var z2319 [1 << 17]byte var z2320 [1 << 17]byte var z2321 [1 << 17]byte var z2322 [1 << 17]byte var z2323 [1 << 17]byte var z2324 [1 << 17]byte var z2325 [1 << 17]byte var z2326 [1 << 17]byte var z2327 [1 << 17]byte var z2328 [1 << 17]byte var z2329 [1 << 17]byte var z2330 [1 << 17]byte var z2331 [1 << 17]byte var z2332 [1 << 17]byte var z2333 [1 << 17]byte var z2334 [1 << 17]byte var z2335 [1 << 17]byte var z2336 [1 << 17]byte var z2337 [1 << 17]byte var z2338 [1 << 17]byte var z2339 [1 << 17]byte var z2340 [1 << 17]byte var z2341 [1 << 17]byte var z2342 [1 << 17]byte var z2343 [1 << 17]byte var z2344 [1 << 17]byte var z2345 [1 << 17]byte var z2346 [1 << 17]byte var z2347 [1 << 17]byte var z2348 [1 << 17]byte var z2349 [1 << 17]byte var z2350 [1 << 17]byte var z2351 [1 << 17]byte var z2352 [1 << 17]byte var z2353 [1 << 17]byte var z2354 [1 << 17]byte var z2355 [1 << 17]byte var z2356 [1 << 17]byte var z2357 [1 << 17]byte var z2358 [1 << 17]byte var z2359 [1 << 17]byte var z2360 [1 << 17]byte var z2361 [1 << 17]byte var z2362 [1 << 17]byte var z2363 [1 << 17]byte var z2364 [1 << 17]byte var z2365 [1 << 17]byte var z2366 [1 << 17]byte var z2367 [1 << 17]byte var z2368 [1 << 17]byte var z2369 [1 << 17]byte var z2370 [1 << 17]byte var z2371 [1 << 17]byte var z2372 [1 << 17]byte var z2373 [1 << 17]byte var z2374 [1 << 17]byte var z2375 [1 << 17]byte var z2376 [1 << 17]byte var z2377 [1 << 17]byte var z2378 [1 << 17]byte var z2379 [1 << 17]byte var z2380 [1 << 17]byte var z2381 [1 << 17]byte var z2382 [1 << 17]byte var z2383 [1 << 17]byte var z2384 [1 << 17]byte var z2385 [1 << 17]byte var z2386 [1 << 17]byte var z2387 [1 << 17]byte var z2388 [1 << 17]byte var z2389 [1 << 17]byte var z2390 [1 << 17]byte var z2391 [1 << 17]byte var z2392 [1 << 17]byte var z2393 [1 << 17]byte var z2394 [1 << 17]byte var z2395 [1 << 17]byte var z2396 [1 << 17]byte var z2397 [1 << 17]byte var z2398 [1 << 17]byte var z2399 [1 << 17]byte var z2400 [1 << 17]byte var z2401 [1 << 17]byte var z2402 [1 << 17]byte var z2403 [1 << 17]byte var z2404 [1 << 17]byte var z2405 [1 << 17]byte var z2406 [1 << 17]byte var z2407 [1 << 17]byte var z2408 [1 << 17]byte var z2409 [1 << 17]byte var z2410 [1 << 17]byte var z2411 [1 << 17]byte var z2412 [1 << 17]byte var z2413 [1 << 17]byte var z2414 [1 << 17]byte var z2415 [1 << 17]byte var z2416 [1 << 17]byte var z2417 [1 << 17]byte var z2418 [1 << 17]byte var z2419 [1 << 17]byte var z2420 [1 << 17]byte var z2421 [1 << 17]byte var z2422 [1 << 17]byte var z2423 [1 << 17]byte var z2424 [1 << 17]byte var z2425 [1 << 17]byte var z2426 [1 << 17]byte var z2427 [1 << 17]byte var z2428 [1 << 17]byte var z2429 [1 << 17]byte var z2430 [1 << 17]byte var z2431 [1 << 17]byte var z2432 [1 << 17]byte var z2433 [1 << 17]byte var z2434 [1 << 17]byte var z2435 [1 << 17]byte var z2436 [1 << 17]byte var z2437 [1 << 17]byte var z2438 [1 << 17]byte var z2439 [1 << 17]byte var z2440 [1 << 17]byte var z2441 [1 << 17]byte var z2442 [1 << 17]byte var z2443 [1 << 17]byte var z2444 [1 << 17]byte var z2445 [1 << 17]byte var z2446 [1 << 17]byte var z2447 [1 << 17]byte var z2448 [1 << 17]byte var z2449 [1 << 17]byte var z2450 [1 << 17]byte var z2451 [1 << 17]byte var z2452 [1 << 17]byte var z2453 [1 << 17]byte var z2454 [1 << 17]byte var z2455 [1 << 17]byte var z2456 [1 << 17]byte var z2457 [1 << 17]byte var z2458 [1 << 17]byte var z2459 [1 << 17]byte var z2460 [1 << 17]byte var z2461 [1 << 17]byte var z2462 [1 << 17]byte var z2463 [1 << 17]byte var z2464 [1 << 17]byte var z2465 [1 << 17]byte var z2466 [1 << 17]byte var z2467 [1 << 17]byte var z2468 [1 << 17]byte var z2469 [1 << 17]byte var z2470 [1 << 17]byte var z2471 [1 << 17]byte var z2472 [1 << 17]byte var z2473 [1 << 17]byte var z2474 [1 << 17]byte var z2475 [1 << 17]byte var z2476 [1 << 17]byte var z2477 [1 << 17]byte var z2478 [1 << 17]byte var z2479 [1 << 17]byte var z2480 [1 << 17]byte var z2481 [1 << 17]byte var z2482 [1 << 17]byte var z2483 [1 << 17]byte var z2484 [1 << 17]byte var z2485 [1 << 17]byte var z2486 [1 << 17]byte var z2487 [1 << 17]byte var z2488 [1 << 17]byte var z2489 [1 << 17]byte var z2490 [1 << 17]byte var z2491 [1 << 17]byte var z2492 [1 << 17]byte var z2493 [1 << 17]byte var z2494 [1 << 17]byte var z2495 [1 << 17]byte var z2496 [1 << 17]byte var z2497 [1 << 17]byte var z2498 [1 << 17]byte var z2499 [1 << 17]byte var z2500 [1 << 17]byte var z2501 [1 << 17]byte var z2502 [1 << 17]byte var z2503 [1 << 17]byte var z2504 [1 << 17]byte var z2505 [1 << 17]byte var z2506 [1 << 17]byte var z2507 [1 << 17]byte var z2508 [1 << 17]byte var z2509 [1 << 17]byte var z2510 [1 << 17]byte var z2511 [1 << 17]byte var z2512 [1 << 17]byte var z2513 [1 << 17]byte var z2514 [1 << 17]byte var z2515 [1 << 17]byte var z2516 [1 << 17]byte var z2517 [1 << 17]byte var z2518 [1 << 17]byte var z2519 [1 << 17]byte var z2520 [1 << 17]byte var z2521 [1 << 17]byte var z2522 [1 << 17]byte var z2523 [1 << 17]byte var z2524 [1 << 17]byte var z2525 [1 << 17]byte var z2526 [1 << 17]byte var z2527 [1 << 17]byte var z2528 [1 << 17]byte var z2529 [1 << 17]byte var z2530 [1 << 17]byte var z2531 [1 << 17]byte var z2532 [1 << 17]byte var z2533 [1 << 17]byte var z2534 [1 << 17]byte var z2535 [1 << 17]byte var z2536 [1 << 17]byte var z2537 [1 << 17]byte var z2538 [1 << 17]byte var z2539 [1 << 17]byte var z2540 [1 << 17]byte var z2541 [1 << 17]byte var z2542 [1 << 17]byte var z2543 [1 << 17]byte var z2544 [1 << 17]byte var z2545 [1 << 17]byte var z2546 [1 << 17]byte var z2547 [1 << 17]byte var z2548 [1 << 17]byte var z2549 [1 << 17]byte var z2550 [1 << 17]byte var z2551 [1 << 17]byte var z2552 [1 << 17]byte var z2553 [1 << 17]byte var z2554 [1 << 17]byte var z2555 [1 << 17]byte var z2556 [1 << 17]byte var z2557 [1 << 17]byte var z2558 [1 << 17]byte var z2559 [1 << 17]byte var z2560 [1 << 17]byte var z2561 [1 << 17]byte var z2562 [1 << 17]byte var z2563 [1 << 17]byte var z2564 [1 << 17]byte var z2565 [1 << 17]byte var z2566 [1 << 17]byte var z2567 [1 << 17]byte var z2568 [1 << 17]byte var z2569 [1 << 17]byte var z2570 [1 << 17]byte var z2571 [1 << 17]byte var z2572 [1 << 17]byte var z2573 [1 << 17]byte var z2574 [1 << 17]byte var z2575 [1 << 17]byte var z2576 [1 << 17]byte var z2577 [1 << 17]byte var z2578 [1 << 17]byte var z2579 [1 << 17]byte var z2580 [1 << 17]byte var z2581 [1 << 17]byte var z2582 [1 << 17]byte var z2583 [1 << 17]byte var z2584 [1 << 17]byte var z2585 [1 << 17]byte var z2586 [1 << 17]byte var z2587 [1 << 17]byte var z2588 [1 << 17]byte var z2589 [1 << 17]byte var z2590 [1 << 17]byte var z2591 [1 << 17]byte var z2592 [1 << 17]byte var z2593 [1 << 17]byte var z2594 [1 << 17]byte var z2595 [1 << 17]byte var z2596 [1 << 17]byte var z2597 [1 << 17]byte var z2598 [1 << 17]byte var z2599 [1 << 17]byte var z2600 [1 << 17]byte var z2601 [1 << 17]byte var z2602 [1 << 17]byte var z2603 [1 << 17]byte var z2604 [1 << 17]byte var z2605 [1 << 17]byte var z2606 [1 << 17]byte var z2607 [1 << 17]byte var z2608 [1 << 17]byte var z2609 [1 << 17]byte var z2610 [1 << 17]byte var z2611 [1 << 17]byte var z2612 [1 << 17]byte var z2613 [1 << 17]byte var z2614 [1 << 17]byte var z2615 [1 << 17]byte var z2616 [1 << 17]byte var z2617 [1 << 17]byte var z2618 [1 << 17]byte var z2619 [1 << 17]byte var z2620 [1 << 17]byte var z2621 [1 << 17]byte var z2622 [1 << 17]byte var z2623 [1 << 17]byte var z2624 [1 << 17]byte var z2625 [1 << 17]byte var z2626 [1 << 17]byte var z2627 [1 << 17]byte var z2628 [1 << 17]byte var z2629 [1 << 17]byte var z2630 [1 << 17]byte var z2631 [1 << 17]byte var z2632 [1 << 17]byte var z2633 [1 << 17]byte var z2634 [1 << 17]byte var z2635 [1 << 17]byte var z2636 [1 << 17]byte var z2637 [1 << 17]byte var z2638 [1 << 17]byte var z2639 [1 << 17]byte var z2640 [1 << 17]byte var z2641 [1 << 17]byte var z2642 [1 << 17]byte var z2643 [1 << 17]byte var z2644 [1 << 17]byte var z2645 [1 << 17]byte var z2646 [1 << 17]byte var z2647 [1 << 17]byte var z2648 [1 << 17]byte var z2649 [1 << 17]byte var z2650 [1 << 17]byte var z2651 [1 << 17]byte var z2652 [1 << 17]byte var z2653 [1 << 17]byte var z2654 [1 << 17]byte var z2655 [1 << 17]byte var z2656 [1 << 17]byte var z2657 [1 << 17]byte var z2658 [1 << 17]byte var z2659 [1 << 17]byte var z2660 [1 << 17]byte var z2661 [1 << 17]byte var z2662 [1 << 17]byte var z2663 [1 << 17]byte var z2664 [1 << 17]byte var z2665 [1 << 17]byte var z2666 [1 << 17]byte var z2667 [1 << 17]byte var z2668 [1 << 17]byte var z2669 [1 << 17]byte var z2670 [1 << 17]byte var z2671 [1 << 17]byte var z2672 [1 << 17]byte var z2673 [1 << 17]byte var z2674 [1 << 17]byte var z2675 [1 << 17]byte var z2676 [1 << 17]byte var z2677 [1 << 17]byte var z2678 [1 << 17]byte var z2679 [1 << 17]byte var z2680 [1 << 17]byte var z2681 [1 << 17]byte var z2682 [1 << 17]byte var z2683 [1 << 17]byte var z2684 [1 << 17]byte var z2685 [1 << 17]byte var z2686 [1 << 17]byte var z2687 [1 << 17]byte var z2688 [1 << 17]byte var z2689 [1 << 17]byte var z2690 [1 << 17]byte var z2691 [1 << 17]byte var z2692 [1 << 17]byte var z2693 [1 << 17]byte var z2694 [1 << 17]byte var z2695 [1 << 17]byte var z2696 [1 << 17]byte var z2697 [1 << 17]byte var z2698 [1 << 17]byte var z2699 [1 << 17]byte var z2700 [1 << 17]byte var z2701 [1 << 17]byte var z2702 [1 << 17]byte var z2703 [1 << 17]byte var z2704 [1 << 17]byte var z2705 [1 << 17]byte var z2706 [1 << 17]byte var z2707 [1 << 17]byte var z2708 [1 << 17]byte var z2709 [1 << 17]byte var z2710 [1 << 17]byte var z2711 [1 << 17]byte var z2712 [1 << 17]byte var z2713 [1 << 17]byte var z2714 [1 << 17]byte var z2715 [1 << 17]byte var z2716 [1 << 17]byte var z2717 [1 << 17]byte var z2718 [1 << 17]byte var z2719 [1 << 17]byte var z2720 [1 << 17]byte var z2721 [1 << 17]byte var z2722 [1 << 17]byte var z2723 [1 << 17]byte var z2724 [1 << 17]byte var z2725 [1 << 17]byte var z2726 [1 << 17]byte var z2727 [1 << 17]byte var z2728 [1 << 17]byte var z2729 [1 << 17]byte var z2730 [1 << 17]byte var z2731 [1 << 17]byte var z2732 [1 << 17]byte var z2733 [1 << 17]byte var z2734 [1 << 17]byte var z2735 [1 << 17]byte var z2736 [1 << 17]byte var z2737 [1 << 17]byte var z2738 [1 << 17]byte var z2739 [1 << 17]byte var z2740 [1 << 17]byte var z2741 [1 << 17]byte var z2742 [1 << 17]byte var z2743 [1 << 17]byte var z2744 [1 << 17]byte var z2745 [1 << 17]byte var z2746 [1 << 17]byte var z2747 [1 << 17]byte var z2748 [1 << 17]byte var z2749 [1 << 17]byte var z2750 [1 << 17]byte var z2751 [1 << 17]byte var z2752 [1 << 17]byte var z2753 [1 << 17]byte var z2754 [1 << 17]byte var z2755 [1 << 17]byte var z2756 [1 << 17]byte var z2757 [1 << 17]byte var z2758 [1 << 17]byte var z2759 [1 << 17]byte var z2760 [1 << 17]byte var z2761 [1 << 17]byte var z2762 [1 << 17]byte var z2763 [1 << 17]byte var z2764 [1 << 17]byte var z2765 [1 << 17]byte var z2766 [1 << 17]byte var z2767 [1 << 17]byte var z2768 [1 << 17]byte var z2769 [1 << 17]byte var z2770 [1 << 17]byte var z2771 [1 << 17]byte var z2772 [1 << 17]byte var z2773 [1 << 17]byte var z2774 [1 << 17]byte var z2775 [1 << 17]byte var z2776 [1 << 17]byte var z2777 [1 << 17]byte var z2778 [1 << 17]byte var z2779 [1 << 17]byte var z2780 [1 << 17]byte var z2781 [1 << 17]byte var z2782 [1 << 17]byte var z2783 [1 << 17]byte var z2784 [1 << 17]byte var z2785 [1 << 17]byte var z2786 [1 << 17]byte var z2787 [1 << 17]byte var z2788 [1 << 17]byte var z2789 [1 << 17]byte var z2790 [1 << 17]byte var z2791 [1 << 17]byte var z2792 [1 << 17]byte var z2793 [1 << 17]byte var z2794 [1 << 17]byte var z2795 [1 << 17]byte var z2796 [1 << 17]byte var z2797 [1 << 17]byte var z2798 [1 << 17]byte var z2799 [1 << 17]byte var z2800 [1 << 17]byte var z2801 [1 << 17]byte var z2802 [1 << 17]byte var z2803 [1 << 17]byte var z2804 [1 << 17]byte var z2805 [1 << 17]byte var z2806 [1 << 17]byte var z2807 [1 << 17]byte var z2808 [1 << 17]byte var z2809 [1 << 17]byte var z2810 [1 << 17]byte var z2811 [1 << 17]byte var z2812 [1 << 17]byte var z2813 [1 << 17]byte var z2814 [1 << 17]byte var z2815 [1 << 17]byte var z2816 [1 << 17]byte var z2817 [1 << 17]byte var z2818 [1 << 17]byte var z2819 [1 << 17]byte var z2820 [1 << 17]byte var z2821 [1 << 17]byte var z2822 [1 << 17]byte var z2823 [1 << 17]byte var z2824 [1 << 17]byte var z2825 [1 << 17]byte var z2826 [1 << 17]byte var z2827 [1 << 17]byte var z2828 [1 << 17]byte var z2829 [1 << 17]byte var z2830 [1 << 17]byte var z2831 [1 << 17]byte var z2832 [1 << 17]byte var z2833 [1 << 17]byte var z2834 [1 << 17]byte var z2835 [1 << 17]byte var z2836 [1 << 17]byte var z2837 [1 << 17]byte var z2838 [1 << 17]byte var z2839 [1 << 17]byte var z2840 [1 << 17]byte var z2841 [1 << 17]byte var z2842 [1 << 17]byte var z2843 [1 << 17]byte var z2844 [1 << 17]byte var z2845 [1 << 17]byte var z2846 [1 << 17]byte var z2847 [1 << 17]byte var z2848 [1 << 17]byte var z2849 [1 << 17]byte var z2850 [1 << 17]byte var z2851 [1 << 17]byte var z2852 [1 << 17]byte var z2853 [1 << 17]byte var z2854 [1 << 17]byte var z2855 [1 << 17]byte var z2856 [1 << 17]byte var z2857 [1 << 17]byte var z2858 [1 << 17]byte var z2859 [1 << 17]byte var z2860 [1 << 17]byte var z2861 [1 << 17]byte var z2862 [1 << 17]byte var z2863 [1 << 17]byte var z2864 [1 << 17]byte var z2865 [1 << 17]byte var z2866 [1 << 17]byte var z2867 [1 << 17]byte var z2868 [1 << 17]byte var z2869 [1 << 17]byte var z2870 [1 << 17]byte var z2871 [1 << 17]byte var z2872 [1 << 17]byte var z2873 [1 << 17]byte var z2874 [1 << 17]byte var z2875 [1 << 17]byte var z2876 [1 << 17]byte var z2877 [1 << 17]byte var z2878 [1 << 17]byte var z2879 [1 << 17]byte var z2880 [1 << 17]byte var z2881 [1 << 17]byte var z2882 [1 << 17]byte var z2883 [1 << 17]byte var z2884 [1 << 17]byte var z2885 [1 << 17]byte var z2886 [1 << 17]byte var z2887 [1 << 17]byte var z2888 [1 << 17]byte var z2889 [1 << 17]byte var z2890 [1 << 17]byte var z2891 [1 << 17]byte var z2892 [1 << 17]byte var z2893 [1 << 17]byte var z2894 [1 << 17]byte var z2895 [1 << 17]byte var z2896 [1 << 17]byte var z2897 [1 << 17]byte var z2898 [1 << 17]byte var z2899 [1 << 17]byte var z2900 [1 << 17]byte var z2901 [1 << 17]byte var z2902 [1 << 17]byte var z2903 [1 << 17]byte var z2904 [1 << 17]byte var z2905 [1 << 17]byte var z2906 [1 << 17]byte var z2907 [1 << 17]byte var z2908 [1 << 17]byte var z2909 [1 << 17]byte var z2910 [1 << 17]byte var z2911 [1 << 17]byte var z2912 [1 << 17]byte var z2913 [1 << 17]byte var z2914 [1 << 17]byte var z2915 [1 << 17]byte var z2916 [1 << 17]byte var z2917 [1 << 17]byte var z2918 [1 << 17]byte var z2919 [1 << 17]byte var z2920 [1 << 17]byte var z2921 [1 << 17]byte var z2922 [1 << 17]byte var z2923 [1 << 17]byte var z2924 [1 << 17]byte var z2925 [1 << 17]byte var z2926 [1 << 17]byte var z2927 [1 << 17]byte var z2928 [1 << 17]byte var z2929 [1 << 17]byte var z2930 [1 << 17]byte var z2931 [1 << 17]byte var z2932 [1 << 17]byte var z2933 [1 << 17]byte var z2934 [1 << 17]byte var z2935 [1 << 17]byte var z2936 [1 << 17]byte var z2937 [1 << 17]byte var z2938 [1 << 17]byte var z2939 [1 << 17]byte var z2940 [1 << 17]byte var z2941 [1 << 17]byte var z2942 [1 << 17]byte var z2943 [1 << 17]byte var z2944 [1 << 17]byte var z2945 [1 << 17]byte var z2946 [1 << 17]byte var z2947 [1 << 17]byte var z2948 [1 << 17]byte var z2949 [1 << 17]byte var z2950 [1 << 17]byte var z2951 [1 << 17]byte var z2952 [1 << 17]byte var z2953 [1 << 17]byte var z2954 [1 << 17]byte var z2955 [1 << 17]byte var z2956 [1 << 17]byte var z2957 [1 << 17]byte var z2958 [1 << 17]byte var z2959 [1 << 17]byte var z2960 [1 << 17]byte var z2961 [1 << 17]byte var z2962 [1 << 17]byte var z2963 [1 << 17]byte var z2964 [1 << 17]byte var z2965 [1 << 17]byte var z2966 [1 << 17]byte var z2967 [1 << 17]byte var z2968 [1 << 17]byte var z2969 [1 << 17]byte var z2970 [1 << 17]byte var z2971 [1 << 17]byte var z2972 [1 << 17]byte var z2973 [1 << 17]byte var z2974 [1 << 17]byte var z2975 [1 << 17]byte var z2976 [1 << 17]byte var z2977 [1 << 17]byte var z2978 [1 << 17]byte var z2979 [1 << 17]byte var z2980 [1 << 17]byte var z2981 [1 << 17]byte var z2982 [1 << 17]byte var z2983 [1 << 17]byte var z2984 [1 << 17]byte var z2985 [1 << 17]byte var z2986 [1 << 17]byte var z2987 [1 << 17]byte var z2988 [1 << 17]byte var z2989 [1 << 17]byte var z2990 [1 << 17]byte var z2991 [1 << 17]byte var z2992 [1 << 17]byte var z2993 [1 << 17]byte var z2994 [1 << 17]byte var z2995 [1 << 17]byte var z2996 [1 << 17]byte var z2997 [1 << 17]byte var z2998 [1 << 17]byte var z2999 [1 << 17]byte var z3000 [1 << 17]byte var z3001 [1 << 17]byte var z3002 [1 << 17]byte var z3003 [1 << 17]byte var z3004 [1 << 17]byte var z3005 [1 << 17]byte var z3006 [1 << 17]byte var z3007 [1 << 17]byte var z3008 [1 << 17]byte var z3009 [1 << 17]byte var z3010 [1 << 17]byte var z3011 [1 << 17]byte var z3012 [1 << 17]byte var z3013 [1 << 17]byte var z3014 [1 << 17]byte var z3015 [1 << 17]byte var z3016 [1 << 17]byte var z3017 [1 << 17]byte var z3018 [1 << 17]byte var z3019 [1 << 17]byte var z3020 [1 << 17]byte var z3021 [1 << 17]byte var z3022 [1 << 17]byte var z3023 [1 << 17]byte var z3024 [1 << 17]byte var z3025 [1 << 17]byte var z3026 [1 << 17]byte var z3027 [1 << 17]byte var z3028 [1 << 17]byte var z3029 [1 << 17]byte var z3030 [1 << 17]byte var z3031 [1 << 17]byte var z3032 [1 << 17]byte var z3033 [1 << 17]byte var z3034 [1 << 17]byte var z3035 [1 << 17]byte var z3036 [1 << 17]byte var z3037 [1 << 17]byte var z3038 [1 << 17]byte var z3039 [1 << 17]byte var z3040 [1 << 17]byte var z3041 [1 << 17]byte var z3042 [1 << 17]byte var z3043 [1 << 17]byte var z3044 [1 << 17]byte var z3045 [1 << 17]byte var z3046 [1 << 17]byte var z3047 [1 << 17]byte var z3048 [1 << 17]byte var z3049 [1 << 17]byte var z3050 [1 << 17]byte var z3051 [1 << 17]byte var z3052 [1 << 17]byte var z3053 [1 << 17]byte var z3054 [1 << 17]byte var z3055 [1 << 17]byte var z3056 [1 << 17]byte var z3057 [1 << 17]byte var z3058 [1 << 17]byte var z3059 [1 << 17]byte var z3060 [1 << 17]byte var z3061 [1 << 17]byte var z3062 [1 << 17]byte var z3063 [1 << 17]byte var z3064 [1 << 17]byte var z3065 [1 << 17]byte var z3066 [1 << 17]byte var z3067 [1 << 17]byte var z3068 [1 << 17]byte var z3069 [1 << 17]byte var z3070 [1 << 17]byte var z3071 [1 << 17]byte var z3072 [1 << 17]byte var z3073 [1 << 17]byte var z3074 [1 << 17]byte var z3075 [1 << 17]byte var z3076 [1 << 17]byte var z3077 [1 << 17]byte var z3078 [1 << 17]byte var z3079 [1 << 17]byte var z3080 [1 << 17]byte var z3081 [1 << 17]byte var z3082 [1 << 17]byte var z3083 [1 << 17]byte var z3084 [1 << 17]byte var z3085 [1 << 17]byte var z3086 [1 << 17]byte var z3087 [1 << 17]byte var z3088 [1 << 17]byte var z3089 [1 << 17]byte var z3090 [1 << 17]byte var z3091 [1 << 17]byte var z3092 [1 << 17]byte var z3093 [1 << 17]byte var z3094 [1 << 17]byte var z3095 [1 << 17]byte var z3096 [1 << 17]byte var z3097 [1 << 17]byte var z3098 [1 << 17]byte var z3099 [1 << 17]byte var z3100 [1 << 17]byte var z3101 [1 << 17]byte var z3102 [1 << 17]byte var z3103 [1 << 17]byte var z3104 [1 << 17]byte var z3105 [1 << 17]byte var z3106 [1 << 17]byte var z3107 [1 << 17]byte var z3108 [1 << 17]byte var z3109 [1 << 17]byte var z3110 [1 << 17]byte var z3111 [1 << 17]byte var z3112 [1 << 17]byte var z3113 [1 << 17]byte var z3114 [1 << 17]byte var z3115 [1 << 17]byte var z3116 [1 << 17]byte var z3117 [1 << 17]byte var z3118 [1 << 17]byte var z3119 [1 << 17]byte var z3120 [1 << 17]byte var z3121 [1 << 17]byte var z3122 [1 << 17]byte var z3123 [1 << 17]byte var z3124 [1 << 17]byte var z3125 [1 << 17]byte var z3126 [1 << 17]byte var z3127 [1 << 17]byte var z3128 [1 << 17]byte var z3129 [1 << 17]byte var z3130 [1 << 17]byte var z3131 [1 << 17]byte var z3132 [1 << 17]byte var z3133 [1 << 17]byte var z3134 [1 << 17]byte var z3135 [1 << 17]byte var z3136 [1 << 17]byte var z3137 [1 << 17]byte var z3138 [1 << 17]byte var z3139 [1 << 17]byte var z3140 [1 << 17]byte var z3141 [1 << 17]byte var z3142 [1 << 17]byte var z3143 [1 << 17]byte var z3144 [1 << 17]byte var z3145 [1 << 17]byte var z3146 [1 << 17]byte var z3147 [1 << 17]byte var z3148 [1 << 17]byte var z3149 [1 << 17]byte var z3150 [1 << 17]byte var z3151 [1 << 17]byte var z3152 [1 << 17]byte var z3153 [1 << 17]byte var z3154 [1 << 17]byte var z3155 [1 << 17]byte var z3156 [1 << 17]byte var z3157 [1 << 17]byte var z3158 [1 << 17]byte var z3159 [1 << 17]byte var z3160 [1 << 17]byte var z3161 [1 << 17]byte var z3162 [1 << 17]byte var z3163 [1 << 17]byte var z3164 [1 << 17]byte var z3165 [1 << 17]byte var z3166 [1 << 17]byte var z3167 [1 << 17]byte var z3168 [1 << 17]byte var z3169 [1 << 17]byte var z3170 [1 << 17]byte var z3171 [1 << 17]byte var z3172 [1 << 17]byte var z3173 [1 << 17]byte var z3174 [1 << 17]byte var z3175 [1 << 17]byte var z3176 [1 << 17]byte var z3177 [1 << 17]byte var z3178 [1 << 17]byte var z3179 [1 << 17]byte var z3180 [1 << 17]byte var z3181 [1 << 17]byte var z3182 [1 << 17]byte var z3183 [1 << 17]byte var z3184 [1 << 17]byte var z3185 [1 << 17]byte var z3186 [1 << 17]byte var z3187 [1 << 17]byte var z3188 [1 << 17]byte var z3189 [1 << 17]byte var z3190 [1 << 17]byte var z3191 [1 << 17]byte var z3192 [1 << 17]byte var z3193 [1 << 17]byte var z3194 [1 << 17]byte var z3195 [1 << 17]byte var z3196 [1 << 17]byte var z3197 [1 << 17]byte var z3198 [1 << 17]byte var z3199 [1 << 17]byte var z3200 [1 << 17]byte var z3201 [1 << 17]byte var z3202 [1 << 17]byte var z3203 [1 << 17]byte var z3204 [1 << 17]byte var z3205 [1 << 17]byte var z3206 [1 << 17]byte var z3207 [1 << 17]byte var z3208 [1 << 17]byte var z3209 [1 << 17]byte var z3210 [1 << 17]byte var z3211 [1 << 17]byte var z3212 [1 << 17]byte var z3213 [1 << 17]byte var z3214 [1 << 17]byte var z3215 [1 << 17]byte var z3216 [1 << 17]byte var z3217 [1 << 17]byte var z3218 [1 << 17]byte var z3219 [1 << 17]byte var z3220 [1 << 17]byte var z3221 [1 << 17]byte var z3222 [1 << 17]byte var z3223 [1 << 17]byte var z3224 [1 << 17]byte var z3225 [1 << 17]byte var z3226 [1 << 17]byte var z3227 [1 << 17]byte var z3228 [1 << 17]byte var z3229 [1 << 17]byte var z3230 [1 << 17]byte var z3231 [1 << 17]byte var z3232 [1 << 17]byte var z3233 [1 << 17]byte var z3234 [1 << 17]byte var z3235 [1 << 17]byte var z3236 [1 << 17]byte var z3237 [1 << 17]byte var z3238 [1 << 17]byte var z3239 [1 << 17]byte var z3240 [1 << 17]byte var z3241 [1 << 17]byte var z3242 [1 << 17]byte var z3243 [1 << 17]byte var z3244 [1 << 17]byte var z3245 [1 << 17]byte var z3246 [1 << 17]byte var z3247 [1 << 17]byte var z3248 [1 << 17]byte var z3249 [1 << 17]byte var z3250 [1 << 17]byte var z3251 [1 << 17]byte var z3252 [1 << 17]byte var z3253 [1 << 17]byte var z3254 [1 << 17]byte var z3255 [1 << 17]byte var z3256 [1 << 17]byte var z3257 [1 << 17]byte var z3258 [1 << 17]byte var z3259 [1 << 17]byte var z3260 [1 << 17]byte var z3261 [1 << 17]byte var z3262 [1 << 17]byte var z3263 [1 << 17]byte var z3264 [1 << 17]byte var z3265 [1 << 17]byte var z3266 [1 << 17]byte var z3267 [1 << 17]byte var z3268 [1 << 17]byte var z3269 [1 << 17]byte var z3270 [1 << 17]byte var z3271 [1 << 17]byte var z3272 [1 << 17]byte var z3273 [1 << 17]byte var z3274 [1 << 17]byte var z3275 [1 << 17]byte var z3276 [1 << 17]byte var z3277 [1 << 17]byte var z3278 [1 << 17]byte var z3279 [1 << 17]byte var z3280 [1 << 17]byte var z3281 [1 << 17]byte var z3282 [1 << 17]byte var z3283 [1 << 17]byte var z3284 [1 << 17]byte var z3285 [1 << 17]byte var z3286 [1 << 17]byte var z3287 [1 << 17]byte var z3288 [1 << 17]byte var z3289 [1 << 17]byte var z3290 [1 << 17]byte var z3291 [1 << 17]byte var z3292 [1 << 17]byte var z3293 [1 << 17]byte var z3294 [1 << 17]byte var z3295 [1 << 17]byte var z3296 [1 << 17]byte var z3297 [1 << 17]byte var z3298 [1 << 17]byte var z3299 [1 << 17]byte var z3300 [1 << 17]byte var z3301 [1 << 17]byte var z3302 [1 << 17]byte var z3303 [1 << 17]byte var z3304 [1 << 17]byte var z3305 [1 << 17]byte var z3306 [1 << 17]byte var z3307 [1 << 17]byte var z3308 [1 << 17]byte var z3309 [1 << 17]byte var z3310 [1 << 17]byte var z3311 [1 << 17]byte var z3312 [1 << 17]byte var z3313 [1 << 17]byte var z3314 [1 << 17]byte var z3315 [1 << 17]byte var z3316 [1 << 17]byte var z3317 [1 << 17]byte var z3318 [1 << 17]byte var z3319 [1 << 17]byte var z3320 [1 << 17]byte var z3321 [1 << 17]byte var z3322 [1 << 17]byte var z3323 [1 << 17]byte var z3324 [1 << 17]byte var z3325 [1 << 17]byte var z3326 [1 << 17]byte var z3327 [1 << 17]byte var z3328 [1 << 17]byte var z3329 [1 << 17]byte var z3330 [1 << 17]byte var z3331 [1 << 17]byte var z3332 [1 << 17]byte var z3333 [1 << 17]byte var z3334 [1 << 17]byte var z3335 [1 << 17]byte var z3336 [1 << 17]byte var z3337 [1 << 17]byte var z3338 [1 << 17]byte var z3339 [1 << 17]byte var z3340 [1 << 17]byte var z3341 [1 << 17]byte var z3342 [1 << 17]byte var z3343 [1 << 17]byte var z3344 [1 << 17]byte var z3345 [1 << 17]byte var z3346 [1 << 17]byte var z3347 [1 << 17]byte var z3348 [1 << 17]byte var z3349 [1 << 17]byte var z3350 [1 << 17]byte var z3351 [1 << 17]byte var z3352 [1 << 17]byte var z3353 [1 << 17]byte var z3354 [1 << 17]byte var z3355 [1 << 17]byte var z3356 [1 << 17]byte var z3357 [1 << 17]byte var z3358 [1 << 17]byte var z3359 [1 << 17]byte var z3360 [1 << 17]byte var z3361 [1 << 17]byte var z3362 [1 << 17]byte var z3363 [1 << 17]byte var z3364 [1 << 17]byte var z3365 [1 << 17]byte var z3366 [1 << 17]byte var z3367 [1 << 17]byte var z3368 [1 << 17]byte var z3369 [1 << 17]byte var z3370 [1 << 17]byte var z3371 [1 << 17]byte var z3372 [1 << 17]byte var z3373 [1 << 17]byte var z3374 [1 << 17]byte var z3375 [1 << 17]byte var z3376 [1 << 17]byte var z3377 [1 << 17]byte var z3378 [1 << 17]byte var z3379 [1 << 17]byte var z3380 [1 << 17]byte var z3381 [1 << 17]byte var z3382 [1 << 17]byte var z3383 [1 << 17]byte var z3384 [1 << 17]byte var z3385 [1 << 17]byte var z3386 [1 << 17]byte var z3387 [1 << 17]byte var z3388 [1 << 17]byte var z3389 [1 << 17]byte var z3390 [1 << 17]byte var z3391 [1 << 17]byte var z3392 [1 << 17]byte var z3393 [1 << 17]byte var z3394 [1 << 17]byte var z3395 [1 << 17]byte var z3396 [1 << 17]byte var z3397 [1 << 17]byte var z3398 [1 << 17]byte var z3399 [1 << 17]byte var z3400 [1 << 17]byte var z3401 [1 << 17]byte var z3402 [1 << 17]byte var z3403 [1 << 17]byte var z3404 [1 << 17]byte var z3405 [1 << 17]byte var z3406 [1 << 17]byte var z3407 [1 << 17]byte var z3408 [1 << 17]byte var z3409 [1 << 17]byte var z3410 [1 << 17]byte var z3411 [1 << 17]byte var z3412 [1 << 17]byte var z3413 [1 << 17]byte var z3414 [1 << 17]byte var z3415 [1 << 17]byte var z3416 [1 << 17]byte var z3417 [1 << 17]byte var z3418 [1 << 17]byte var z3419 [1 << 17]byte var z3420 [1 << 17]byte var z3421 [1 << 17]byte var z3422 [1 << 17]byte var z3423 [1 << 17]byte var z3424 [1 << 17]byte var z3425 [1 << 17]byte var z3426 [1 << 17]byte var z3427 [1 << 17]byte var z3428 [1 << 17]byte var z3429 [1 << 17]byte var z3430 [1 << 17]byte var z3431 [1 << 17]byte var z3432 [1 << 17]byte var z3433 [1 << 17]byte var z3434 [1 << 17]byte var z3435 [1 << 17]byte var z3436 [1 << 17]byte var z3437 [1 << 17]byte var z3438 [1 << 17]byte var z3439 [1 << 17]byte var z3440 [1 << 17]byte var z3441 [1 << 17]byte var z3442 [1 << 17]byte var z3443 [1 << 17]byte var z3444 [1 << 17]byte var z3445 [1 << 17]byte var z3446 [1 << 17]byte var z3447 [1 << 17]byte var z3448 [1 << 17]byte var z3449 [1 << 17]byte var z3450 [1 << 17]byte var z3451 [1 << 17]byte var z3452 [1 << 17]byte var z3453 [1 << 17]byte var z3454 [1 << 17]byte var z3455 [1 << 17]byte var z3456 [1 << 17]byte var z3457 [1 << 17]byte var z3458 [1 << 17]byte var z3459 [1 << 17]byte var z3460 [1 << 17]byte var z3461 [1 << 17]byte var z3462 [1 << 17]byte var z3463 [1 << 17]byte var z3464 [1 << 17]byte var z3465 [1 << 17]byte var z3466 [1 << 17]byte var z3467 [1 << 17]byte var z3468 [1 << 17]byte var z3469 [1 << 17]byte var z3470 [1 << 17]byte var z3471 [1 << 17]byte var z3472 [1 << 17]byte var z3473 [1 << 17]byte var z3474 [1 << 17]byte var z3475 [1 << 17]byte var z3476 [1 << 17]byte var z3477 [1 << 17]byte var z3478 [1 << 17]byte var z3479 [1 << 17]byte var z3480 [1 << 17]byte var z3481 [1 << 17]byte var z3482 [1 << 17]byte var z3483 [1 << 17]byte var z3484 [1 << 17]byte var z3485 [1 << 17]byte var z3486 [1 << 17]byte var z3487 [1 << 17]byte var z3488 [1 << 17]byte var z3489 [1 << 17]byte var z3490 [1 << 17]byte var z3491 [1 << 17]byte var z3492 [1 << 17]byte var z3493 [1 << 17]byte var z3494 [1 << 17]byte var z3495 [1 << 17]byte var z3496 [1 << 17]byte var z3497 [1 << 17]byte var z3498 [1 << 17]byte var z3499 [1 << 17]byte var z3500 [1 << 17]byte var z3501 [1 << 17]byte var z3502 [1 << 17]byte var z3503 [1 << 17]byte var z3504 [1 << 17]byte var z3505 [1 << 17]byte var z3506 [1 << 17]byte var z3507 [1 << 17]byte var z3508 [1 << 17]byte var z3509 [1 << 17]byte var z3510 [1 << 17]byte var z3511 [1 << 17]byte var z3512 [1 << 17]byte var z3513 [1 << 17]byte var z3514 [1 << 17]byte var z3515 [1 << 17]byte var z3516 [1 << 17]byte var z3517 [1 << 17]byte var z3518 [1 << 17]byte var z3519 [1 << 17]byte var z3520 [1 << 17]byte var z3521 [1 << 17]byte var z3522 [1 << 17]byte var z3523 [1 << 17]byte var z3524 [1 << 17]byte var z3525 [1 << 17]byte var z3526 [1 << 17]byte var z3527 [1 << 17]byte var z3528 [1 << 17]byte var z3529 [1 << 17]byte var z3530 [1 << 17]byte var z3531 [1 << 17]byte var z3532 [1 << 17]byte var z3533 [1 << 17]byte var z3534 [1 << 17]byte var z3535 [1 << 17]byte var z3536 [1 << 17]byte var z3537 [1 << 17]byte var z3538 [1 << 17]byte var z3539 [1 << 17]byte var z3540 [1 << 17]byte var z3541 [1 << 17]byte var z3542 [1 << 17]byte var z3543 [1 << 17]byte var z3544 [1 << 17]byte var z3545 [1 << 17]byte var z3546 [1 << 17]byte var z3547 [1 << 17]byte var z3548 [1 << 17]byte var z3549 [1 << 17]byte var z3550 [1 << 17]byte var z3551 [1 << 17]byte var z3552 [1 << 17]byte var z3553 [1 << 17]byte var z3554 [1 << 17]byte var z3555 [1 << 17]byte var z3556 [1 << 17]byte var z3557 [1 << 17]byte var z3558 [1 << 17]byte var z3559 [1 << 17]byte var z3560 [1 << 17]byte var z3561 [1 << 17]byte var z3562 [1 << 17]byte var z3563 [1 << 17]byte var z3564 [1 << 17]byte var z3565 [1 << 17]byte var z3566 [1 << 17]byte var z3567 [1 << 17]byte var z3568 [1 << 17]byte var z3569 [1 << 17]byte var z3570 [1 << 17]byte var z3571 [1 << 17]byte var z3572 [1 << 17]byte var z3573 [1 << 17]byte var z3574 [1 << 17]byte var z3575 [1 << 17]byte var z3576 [1 << 17]byte var z3577 [1 << 17]byte var z3578 [1 << 17]byte var z3579 [1 << 17]byte var z3580 [1 << 17]byte var z3581 [1 << 17]byte var z3582 [1 << 17]byte var z3583 [1 << 17]byte var z3584 [1 << 17]byte var z3585 [1 << 17]byte var z3586 [1 << 17]byte var z3587 [1 << 17]byte var z3588 [1 << 17]byte var z3589 [1 << 17]byte var z3590 [1 << 17]byte var z3591 [1 << 17]byte var z3592 [1 << 17]byte var z3593 [1 << 17]byte var z3594 [1 << 17]byte var z3595 [1 << 17]byte var z3596 [1 << 17]byte var z3597 [1 << 17]byte var z3598 [1 << 17]byte var z3599 [1 << 17]byte var z3600 [1 << 17]byte var z3601 [1 << 17]byte var z3602 [1 << 17]byte var z3603 [1 << 17]byte var z3604 [1 << 17]byte var z3605 [1 << 17]byte var z3606 [1 << 17]byte var z3607 [1 << 17]byte var z3608 [1 << 17]byte var z3609 [1 << 17]byte var z3610 [1 << 17]byte var z3611 [1 << 17]byte var z3612 [1 << 17]byte var z3613 [1 << 17]byte var z3614 [1 << 17]byte var z3615 [1 << 17]byte var z3616 [1 << 17]byte var z3617 [1 << 17]byte var z3618 [1 << 17]byte var z3619 [1 << 17]byte var z3620 [1 << 17]byte var z3621 [1 << 17]byte var z3622 [1 << 17]byte var z3623 [1 << 17]byte var z3624 [1 << 17]byte var z3625 [1 << 17]byte var z3626 [1 << 17]byte var z3627 [1 << 17]byte var z3628 [1 << 17]byte var z3629 [1 << 17]byte var z3630 [1 << 17]byte var z3631 [1 << 17]byte var z3632 [1 << 17]byte var z3633 [1 << 17]byte var z3634 [1 << 17]byte var z3635 [1 << 17]byte var z3636 [1 << 17]byte var z3637 [1 << 17]byte var z3638 [1 << 17]byte var z3639 [1 << 17]byte var z3640 [1 << 17]byte var z3641 [1 << 17]byte var z3642 [1 << 17]byte var z3643 [1 << 17]byte var z3644 [1 << 17]byte var z3645 [1 << 17]byte var z3646 [1 << 17]byte var z3647 [1 << 17]byte var z3648 [1 << 17]byte var z3649 [1 << 17]byte var z3650 [1 << 17]byte var z3651 [1 << 17]byte var z3652 [1 << 17]byte var z3653 [1 << 17]byte var z3654 [1 << 17]byte var z3655 [1 << 17]byte var z3656 [1 << 17]byte var z3657 [1 << 17]byte var z3658 [1 << 17]byte var z3659 [1 << 17]byte var z3660 [1 << 17]byte var z3661 [1 << 17]byte var z3662 [1 << 17]byte var z3663 [1 << 17]byte var z3664 [1 << 17]byte var z3665 [1 << 17]byte var z3666 [1 << 17]byte var z3667 [1 << 17]byte var z3668 [1 << 17]byte var z3669 [1 << 17]byte var z3670 [1 << 17]byte var z3671 [1 << 17]byte var z3672 [1 << 17]byte var z3673 [1 << 17]byte var z3674 [1 << 17]byte var z3675 [1 << 17]byte var z3676 [1 << 17]byte var z3677 [1 << 17]byte var z3678 [1 << 17]byte var z3679 [1 << 17]byte var z3680 [1 << 17]byte var z3681 [1 << 17]byte var z3682 [1 << 17]byte var z3683 [1 << 17]byte var z3684 [1 << 17]byte var z3685 [1 << 17]byte var z3686 [1 << 17]byte var z3687 [1 << 17]byte var z3688 [1 << 17]byte var z3689 [1 << 17]byte var z3690 [1 << 17]byte var z3691 [1 << 17]byte var z3692 [1 << 17]byte var z3693 [1 << 17]byte var z3694 [1 << 17]byte var z3695 [1 << 17]byte var z3696 [1 << 17]byte var z3697 [1 << 17]byte var z3698 [1 << 17]byte var z3699 [1 << 17]byte var z3700 [1 << 17]byte var z3701 [1 << 17]byte var z3702 [1 << 17]byte var z3703 [1 << 17]byte var z3704 [1 << 17]byte var z3705 [1 << 17]byte var z3706 [1 << 17]byte var z3707 [1 << 17]byte var z3708 [1 << 17]byte var z3709 [1 << 17]byte var z3710 [1 << 17]byte var z3711 [1 << 17]byte var z3712 [1 << 17]byte var z3713 [1 << 17]byte var z3714 [1 << 17]byte var z3715 [1 << 17]byte var z3716 [1 << 17]byte var z3717 [1 << 17]byte var z3718 [1 << 17]byte var z3719 [1 << 17]byte var z3720 [1 << 17]byte var z3721 [1 << 17]byte var z3722 [1 << 17]byte var z3723 [1 << 17]byte var z3724 [1 << 17]byte var z3725 [1 << 17]byte var z3726 [1 << 17]byte var z3727 [1 << 17]byte var z3728 [1 << 17]byte var z3729 [1 << 17]byte var z3730 [1 << 17]byte var z3731 [1 << 17]byte var z3732 [1 << 17]byte var z3733 [1 << 17]byte var z3734 [1 << 17]byte var z3735 [1 << 17]byte var z3736 [1 << 17]byte var z3737 [1 << 17]byte var z3738 [1 << 17]byte var z3739 [1 << 17]byte var z3740 [1 << 17]byte var z3741 [1 << 17]byte var z3742 [1 << 17]byte var z3743 [1 << 17]byte var z3744 [1 << 17]byte var z3745 [1 << 17]byte var z3746 [1 << 17]byte var z3747 [1 << 17]byte var z3748 [1 << 17]byte var z3749 [1 << 17]byte var z3750 [1 << 17]byte var z3751 [1 << 17]byte var z3752 [1 << 17]byte var z3753 [1 << 17]byte var z3754 [1 << 17]byte var z3755 [1 << 17]byte var z3756 [1 << 17]byte var z3757 [1 << 17]byte var z3758 [1 << 17]byte var z3759 [1 << 17]byte var z3760 [1 << 17]byte var z3761 [1 << 17]byte var z3762 [1 << 17]byte var z3763 [1 << 17]byte var z3764 [1 << 17]byte var z3765 [1 << 17]byte var z3766 [1 << 17]byte var z3767 [1 << 17]byte var z3768 [1 << 17]byte var z3769 [1 << 17]byte var z3770 [1 << 17]byte var z3771 [1 << 17]byte var z3772 [1 << 17]byte var z3773 [1 << 17]byte var z3774 [1 << 17]byte var z3775 [1 << 17]byte var z3776 [1 << 17]byte var z3777 [1 << 17]byte var z3778 [1 << 17]byte var z3779 [1 << 17]byte var z3780 [1 << 17]byte var z3781 [1 << 17]byte var z3782 [1 << 17]byte var z3783 [1 << 17]byte var z3784 [1 << 17]byte var z3785 [1 << 17]byte var z3786 [1 << 17]byte var z3787 [1 << 17]byte var z3788 [1 << 17]byte var z3789 [1 << 17]byte var z3790 [1 << 17]byte var z3791 [1 << 17]byte var z3792 [1 << 17]byte var z3793 [1 << 17]byte var z3794 [1 << 17]byte var z3795 [1 << 17]byte var z3796 [1 << 17]byte var z3797 [1 << 17]byte var z3798 [1 << 17]byte var z3799 [1 << 17]byte var z3800 [1 << 17]byte var z3801 [1 << 17]byte var z3802 [1 << 17]byte var z3803 [1 << 17]byte var z3804 [1 << 17]byte var z3805 [1 << 17]byte var z3806 [1 << 17]byte var z3807 [1 << 17]byte var z3808 [1 << 17]byte var z3809 [1 << 17]byte var z3810 [1 << 17]byte var z3811 [1 << 17]byte var z3812 [1 << 17]byte var z3813 [1 << 17]byte var z3814 [1 << 17]byte var z3815 [1 << 17]byte var z3816 [1 << 17]byte var z3817 [1 << 17]byte var z3818 [1 << 17]byte var z3819 [1 << 17]byte var z3820 [1 << 17]byte var z3821 [1 << 17]byte var z3822 [1 << 17]byte var z3823 [1 << 17]byte var z3824 [1 << 17]byte var z3825 [1 << 17]byte var z3826 [1 << 17]byte var z3827 [1 << 17]byte var z3828 [1 << 17]byte var z3829 [1 << 17]byte var z3830 [1 << 17]byte var z3831 [1 << 17]byte var z3832 [1 << 17]byte var z3833 [1 << 17]byte var z3834 [1 << 17]byte var z3835 [1 << 17]byte var z3836 [1 << 17]byte var z3837 [1 << 17]byte var z3838 [1 << 17]byte var z3839 [1 << 17]byte var z3840 [1 << 17]byte var z3841 [1 << 17]byte var z3842 [1 << 17]byte var z3843 [1 << 17]byte var z3844 [1 << 17]byte var z3845 [1 << 17]byte var z3846 [1 << 17]byte var z3847 [1 << 17]byte var z3848 [1 << 17]byte var z3849 [1 << 17]byte var z3850 [1 << 17]byte var z3851 [1 << 17]byte var z3852 [1 << 17]byte var z3853 [1 << 17]byte var z3854 [1 << 17]byte var z3855 [1 << 17]byte var z3856 [1 << 17]byte var z3857 [1 << 17]byte var z3858 [1 << 17]byte var z3859 [1 << 17]byte var z3860 [1 << 17]byte var z3861 [1 << 17]byte var z3862 [1 << 17]byte var z3863 [1 << 17]byte var z3864 [1 << 17]byte var z3865 [1 << 17]byte var z3866 [1 << 17]byte var z3867 [1 << 17]byte var z3868 [1 << 17]byte var z3869 [1 << 17]byte var z3870 [1 << 17]byte var z3871 [1 << 17]byte var z3872 [1 << 17]byte var z3873 [1 << 17]byte var z3874 [1 << 17]byte var z3875 [1 << 17]byte var z3876 [1 << 17]byte var z3877 [1 << 17]byte var z3878 [1 << 17]byte var z3879 [1 << 17]byte var z3880 [1 << 17]byte var z3881 [1 << 17]byte var z3882 [1 << 17]byte var z3883 [1 << 17]byte var z3884 [1 << 17]byte var z3885 [1 << 17]byte var z3886 [1 << 17]byte var z3887 [1 << 17]byte var z3888 [1 << 17]byte var z3889 [1 << 17]byte var z3890 [1 << 17]byte var z3891 [1 << 17]byte var z3892 [1 << 17]byte var z3893 [1 << 17]byte var z3894 [1 << 17]byte var z3895 [1 << 17]byte var z3896 [1 << 17]byte var z3897 [1 << 17]byte var z3898 [1 << 17]byte var z3899 [1 << 17]byte var z3900 [1 << 17]byte var z3901 [1 << 17]byte var z3902 [1 << 17]byte var z3903 [1 << 17]byte var z3904 [1 << 17]byte var z3905 [1 << 17]byte var z3906 [1 << 17]byte var z3907 [1 << 17]byte var z3908 [1 << 17]byte var z3909 [1 << 17]byte var z3910 [1 << 17]byte var z3911 [1 << 17]byte var z3912 [1 << 17]byte var z3913 [1 << 17]byte var z3914 [1 << 17]byte var z3915 [1 << 17]byte var z3916 [1 << 17]byte var z3917 [1 << 17]byte var z3918 [1 << 17]byte var z3919 [1 << 17]byte var z3920 [1 << 17]byte var z3921 [1 << 17]byte var z3922 [1 << 17]byte var z3923 [1 << 17]byte var z3924 [1 << 17]byte var z3925 [1 << 17]byte var z3926 [1 << 17]byte var z3927 [1 << 17]byte var z3928 [1 << 17]byte var z3929 [1 << 17]byte var z3930 [1 << 17]byte var z3931 [1 << 17]byte var z3932 [1 << 17]byte var z3933 [1 << 17]byte var z3934 [1 << 17]byte var z3935 [1 << 17]byte var z3936 [1 << 17]byte var z3937 [1 << 17]byte var z3938 [1 << 17]byte var z3939 [1 << 17]byte var z3940 [1 << 17]byte var z3941 [1 << 17]byte var z3942 [1 << 17]byte var z3943 [1 << 17]byte var z3944 [1 << 17]byte var z3945 [1 << 17]byte var z3946 [1 << 17]byte var z3947 [1 << 17]byte var z3948 [1 << 17]byte var z3949 [1 << 17]byte var z3950 [1 << 17]byte var z3951 [1 << 17]byte var z3952 [1 << 17]byte var z3953 [1 << 17]byte var z3954 [1 << 17]byte var z3955 [1 << 17]byte var z3956 [1 << 17]byte var z3957 [1 << 17]byte var z3958 [1 << 17]byte var z3959 [1 << 17]byte var z3960 [1 << 17]byte var z3961 [1 << 17]byte var z3962 [1 << 17]byte var z3963 [1 << 17]byte var z3964 [1 << 17]byte var z3965 [1 << 17]byte var z3966 [1 << 17]byte var z3967 [1 << 17]byte var z3968 [1 << 17]byte var z3969 [1 << 17]byte var z3970 [1 << 17]byte var z3971 [1 << 17]byte var z3972 [1 << 17]byte var z3973 [1 << 17]byte var z3974 [1 << 17]byte var z3975 [1 << 17]byte var z3976 [1 << 17]byte var z3977 [1 << 17]byte var z3978 [1 << 17]byte var z3979 [1 << 17]byte var z3980 [1 << 17]byte var z3981 [1 << 17]byte var z3982 [1 << 17]byte var z3983 [1 << 17]byte var z3984 [1 << 17]byte var z3985 [1 << 17]byte var z3986 [1 << 17]byte var z3987 [1 << 17]byte var z3988 [1 << 17]byte var z3989 [1 << 17]byte var z3990 [1 << 17]byte var z3991 [1 << 17]byte var z3992 [1 << 17]byte var z3993 [1 << 17]byte var z3994 [1 << 17]byte var z3995 [1 << 17]byte var z3996 [1 << 17]byte var z3997 [1 << 17]byte var z3998 [1 << 17]byte var z3999 [1 << 17]byte var z4000 [1 << 17]byte var z4001 [1 << 17]byte var z4002 [1 << 17]byte var z4003 [1 << 17]byte var z4004 [1 << 17]byte var z4005 [1 << 17]byte var z4006 [1 << 17]byte var z4007 [1 << 17]byte var z4008 [1 << 17]byte var z4009 [1 << 17]byte var z4010 [1 << 17]byte var z4011 [1 << 17]byte var z4012 [1 << 17]byte var z4013 [1 << 17]byte var z4014 [1 << 17]byte var z4015 [1 << 17]byte var z4016 [1 << 17]byte var z4017 [1 << 17]byte var z4018 [1 << 17]byte var z4019 [1 << 17]byte var z4020 [1 << 17]byte var z4021 [1 << 17]byte var z4022 [1 << 17]byte var z4023 [1 << 17]byte var z4024 [1 << 17]byte var z4025 [1 << 17]byte var z4026 [1 << 17]byte var z4027 [1 << 17]byte var z4028 [1 << 17]byte var z4029 [1 << 17]byte var z4030 [1 << 17]byte var z4031 [1 << 17]byte var z4032 [1 << 17]byte var z4033 [1 << 17]byte var z4034 [1 << 17]byte var z4035 [1 << 17]byte var z4036 [1 << 17]byte var z4037 [1 << 17]byte var z4038 [1 << 17]byte var z4039 [1 << 17]byte var z4040 [1 << 17]byte var z4041 [1 << 17]byte var z4042 [1 << 17]byte var z4043 [1 << 17]byte var z4044 [1 << 17]byte var z4045 [1 << 17]byte var z4046 [1 << 17]byte var z4047 [1 << 17]byte var z4048 [1 << 17]byte var z4049 [1 << 17]byte var z4050 [1 << 17]byte var z4051 [1 << 17]byte var z4052 [1 << 17]byte var z4053 [1 << 17]byte var z4054 [1 << 17]byte var z4055 [1 << 17]byte var z4056 [1 << 17]byte var z4057 [1 << 17]byte var z4058 [1 << 17]byte var z4059 [1 << 17]byte var z4060 [1 << 17]byte var z4061 [1 << 17]byte var z4062 [1 << 17]byte var z4063 [1 << 17]byte var z4064 [1 << 17]byte var z4065 [1 << 17]byte var z4066 [1 << 17]byte var z4067 [1 << 17]byte var z4068 [1 << 17]byte var z4069 [1 << 17]byte var z4070 [1 << 17]byte var z4071 [1 << 17]byte var z4072 [1 << 17]byte var z4073 [1 << 17]byte var z4074 [1 << 17]byte var z4075 [1 << 17]byte var z4076 [1 << 17]byte var z4077 [1 << 17]byte var z4078 [1 << 17]byte var z4079 [1 << 17]byte var z4080 [1 << 17]byte var z4081 [1 << 17]byte var z4082 [1 << 17]byte var z4083 [1 << 17]byte var z4084 [1 << 17]byte var z4085 [1 << 17]byte var z4086 [1 << 17]byte var z4087 [1 << 17]byte var z4088 [1 << 17]byte var z4089 [1 << 17]byte var z4090 [1 << 17]byte var z4091 [1 << 17]byte var z4092 [1 << 17]byte var z4093 [1 << 17]byte var z4094 [1 << 17]byte var z4095 [1 << 17]byte var z4096 [1 << 17]byte var z4097 [1 << 17]byte var z4098 [1 << 17]byte var z4099 [1 << 17]byte var z4100 [1 << 17]byte var z4101 [1 << 17]byte var z4102 [1 << 17]byte var z4103 [1 << 17]byte var z4104 [1 << 17]byte var z4105 [1 << 17]byte var z4106 [1 << 17]byte var z4107 [1 << 17]byte var z4108 [1 << 17]byte var z4109 [1 << 17]byte var z4110 [1 << 17]byte var z4111 [1 << 17]byte var z4112 [1 << 17]byte var z4113 [1 << 17]byte var z4114 [1 << 17]byte var z4115 [1 << 17]byte var z4116 [1 << 17]byte var z4117 [1 << 17]byte var z4118 [1 << 17]byte var z4119 [1 << 17]byte var z4120 [1 << 17]byte var z4121 [1 << 17]byte var z4122 [1 << 17]byte var z4123 [1 << 17]byte var z4124 [1 << 17]byte var z4125 [1 << 17]byte var z4126 [1 << 17]byte var z4127 [1 << 17]byte var z4128 [1 << 17]byte var z4129 [1 << 17]byte var z4130 [1 << 17]byte var z4131 [1 << 17]byte var z4132 [1 << 17]byte var z4133 [1 << 17]byte var z4134 [1 << 17]byte var z4135 [1 << 17]byte var z4136 [1 << 17]byte var z4137 [1 << 17]byte var z4138 [1 << 17]byte var z4139 [1 << 17]byte var z4140 [1 << 17]byte var z4141 [1 << 17]byte var z4142 [1 << 17]byte var z4143 [1 << 17]byte var z4144 [1 << 17]byte var z4145 [1 << 17]byte var z4146 [1 << 17]byte var z4147 [1 << 17]byte var z4148 [1 << 17]byte var z4149 [1 << 17]byte var z4150 [1 << 17]byte var z4151 [1 << 17]byte var z4152 [1 << 17]byte var z4153 [1 << 17]byte var z4154 [1 << 17]byte var z4155 [1 << 17]byte var z4156 [1 << 17]byte var z4157 [1 << 17]byte var z4158 [1 << 17]byte var z4159 [1 << 17]byte var z4160 [1 << 17]byte var z4161 [1 << 17]byte var z4162 [1 << 17]byte var z4163 [1 << 17]byte var z4164 [1 << 17]byte var z4165 [1 << 17]byte var z4166 [1 << 17]byte var z4167 [1 << 17]byte var z4168 [1 << 17]byte var z4169 [1 << 17]byte var z4170 [1 << 17]byte var z4171 [1 << 17]byte var z4172 [1 << 17]byte var z4173 [1 << 17]byte var z4174 [1 << 17]byte var z4175 [1 << 17]byte var z4176 [1 << 17]byte var z4177 [1 << 17]byte var z4178 [1 << 17]byte var z4179 [1 << 17]byte var z4180 [1 << 17]byte var z4181 [1 << 17]byte var z4182 [1 << 17]byte var z4183 [1 << 17]byte var z4184 [1 << 17]byte var z4185 [1 << 17]byte var z4186 [1 << 17]byte var z4187 [1 << 17]byte var z4188 [1 << 17]byte var z4189 [1 << 17]byte var z4190 [1 << 17]byte var z4191 [1 << 17]byte var z4192 [1 << 17]byte var z4193 [1 << 17]byte var z4194 [1 << 17]byte var z4195 [1 << 17]byte var z4196 [1 << 17]byte var z4197 [1 << 17]byte var z4198 [1 << 17]byte var z4199 [1 << 17]byte var z4200 [1 << 17]byte var z4201 [1 << 17]byte var z4202 [1 << 17]byte var z4203 [1 << 17]byte var z4204 [1 << 17]byte var z4205 [1 << 17]byte var z4206 [1 << 17]byte var z4207 [1 << 17]byte var z4208 [1 << 17]byte var z4209 [1 << 17]byte var z4210 [1 << 17]byte var z4211 [1 << 17]byte var z4212 [1 << 17]byte var z4213 [1 << 17]byte var z4214 [1 << 17]byte var z4215 [1 << 17]byte var z4216 [1 << 17]byte var z4217 [1 << 17]byte var z4218 [1 << 17]byte var z4219 [1 << 17]byte var z4220 [1 << 17]byte var z4221 [1 << 17]byte var z4222 [1 << 17]byte var z4223 [1 << 17]byte var z4224 [1 << 17]byte var z4225 [1 << 17]byte var z4226 [1 << 17]byte var z4227 [1 << 17]byte var z4228 [1 << 17]byte var z4229 [1 << 17]byte var z4230 [1 << 17]byte var z4231 [1 << 17]byte var z4232 [1 << 17]byte var z4233 [1 << 17]byte var z4234 [1 << 17]byte var z4235 [1 << 17]byte var z4236 [1 << 17]byte var z4237 [1 << 17]byte var z4238 [1 << 17]byte var z4239 [1 << 17]byte var z4240 [1 << 17]byte var z4241 [1 << 17]byte var z4242 [1 << 17]byte var z4243 [1 << 17]byte var z4244 [1 << 17]byte var z4245 [1 << 17]byte var z4246 [1 << 17]byte var z4247 [1 << 17]byte var z4248 [1 << 17]byte var z4249 [1 << 17]byte var z4250 [1 << 17]byte var z4251 [1 << 17]byte var z4252 [1 << 17]byte var z4253 [1 << 17]byte var z4254 [1 << 17]byte var z4255 [1 << 17]byte var z4256 [1 << 17]byte var z4257 [1 << 17]byte var z4258 [1 << 17]byte var z4259 [1 << 17]byte var z4260 [1 << 17]byte var z4261 [1 << 17]byte var z4262 [1 << 17]byte var z4263 [1 << 17]byte var z4264 [1 << 17]byte var z4265 [1 << 17]byte var z4266 [1 << 17]byte var z4267 [1 << 17]byte var z4268 [1 << 17]byte var z4269 [1 << 17]byte var z4270 [1 << 17]byte var z4271 [1 << 17]byte var z4272 [1 << 17]byte var z4273 [1 << 17]byte var z4274 [1 << 17]byte var z4275 [1 << 17]byte var z4276 [1 << 17]byte var z4277 [1 << 17]byte var z4278 [1 << 17]byte var z4279 [1 << 17]byte var z4280 [1 << 17]byte var z4281 [1 << 17]byte var z4282 [1 << 17]byte var z4283 [1 << 17]byte var z4284 [1 << 17]byte var z4285 [1 << 17]byte var z4286 [1 << 17]byte var z4287 [1 << 17]byte var z4288 [1 << 17]byte var z4289 [1 << 17]byte var z4290 [1 << 17]byte var z4291 [1 << 17]byte var z4292 [1 << 17]byte var z4293 [1 << 17]byte var z4294 [1 << 17]byte var z4295 [1 << 17]byte var z4296 [1 << 17]byte var z4297 [1 << 17]byte var z4298 [1 << 17]byte var z4299 [1 << 17]byte var z4300 [1 << 17]byte var z4301 [1 << 17]byte var z4302 [1 << 17]byte var z4303 [1 << 17]byte var z4304 [1 << 17]byte var z4305 [1 << 17]byte var z4306 [1 << 17]byte var z4307 [1 << 17]byte var z4308 [1 << 17]byte var z4309 [1 << 17]byte var z4310 [1 << 17]byte var z4311 [1 << 17]byte var z4312 [1 << 17]byte var z4313 [1 << 17]byte var z4314 [1 << 17]byte var z4315 [1 << 17]byte var z4316 [1 << 17]byte var z4317 [1 << 17]byte var z4318 [1 << 17]byte var z4319 [1 << 17]byte var z4320 [1 << 17]byte var z4321 [1 << 17]byte var z4322 [1 << 17]byte var z4323 [1 << 17]byte var z4324 [1 << 17]byte var z4325 [1 << 17]byte var z4326 [1 << 17]byte var z4327 [1 << 17]byte var z4328 [1 << 17]byte var z4329 [1 << 17]byte var z4330 [1 << 17]byte var z4331 [1 << 17]byte var z4332 [1 << 17]byte var z4333 [1 << 17]byte var z4334 [1 << 17]byte var z4335 [1 << 17]byte var z4336 [1 << 17]byte var z4337 [1 << 17]byte var z4338 [1 << 17]byte var z4339 [1 << 17]byte var z4340 [1 << 17]byte var z4341 [1 << 17]byte var z4342 [1 << 17]byte var z4343 [1 << 17]byte var z4344 [1 << 17]byte var z4345 [1 << 17]byte var z4346 [1 << 17]byte var z4347 [1 << 17]byte var z4348 [1 << 17]byte var z4349 [1 << 17]byte var z4350 [1 << 17]byte var z4351 [1 << 17]byte var z4352 [1 << 17]byte var z4353 [1 << 17]byte var z4354 [1 << 17]byte var z4355 [1 << 17]byte var z4356 [1 << 17]byte var z4357 [1 << 17]byte var z4358 [1 << 17]byte var z4359 [1 << 17]byte var z4360 [1 << 17]byte var z4361 [1 << 17]byte var z4362 [1 << 17]byte var z4363 [1 << 17]byte var z4364 [1 << 17]byte var z4365 [1 << 17]byte var z4366 [1 << 17]byte var z4367 [1 << 17]byte var z4368 [1 << 17]byte var z4369 [1 << 17]byte var z4370 [1 << 17]byte var z4371 [1 << 17]byte var z4372 [1 << 17]byte var z4373 [1 << 17]byte var z4374 [1 << 17]byte var z4375 [1 << 17]byte var z4376 [1 << 17]byte var z4377 [1 << 17]byte var z4378 [1 << 17]byte var z4379 [1 << 17]byte var z4380 [1 << 17]byte var z4381 [1 << 17]byte var z4382 [1 << 17]byte var z4383 [1 << 17]byte var z4384 [1 << 17]byte var z4385 [1 << 17]byte var z4386 [1 << 17]byte var z4387 [1 << 17]byte var z4388 [1 << 17]byte var z4389 [1 << 17]byte var z4390 [1 << 17]byte var z4391 [1 << 17]byte var z4392 [1 << 17]byte var z4393 [1 << 17]byte var z4394 [1 << 17]byte var z4395 [1 << 17]byte var z4396 [1 << 17]byte var z4397 [1 << 17]byte var z4398 [1 << 17]byte var z4399 [1 << 17]byte var z4400 [1 << 17]byte var z4401 [1 << 17]byte var z4402 [1 << 17]byte var z4403 [1 << 17]byte var z4404 [1 << 17]byte var z4405 [1 << 17]byte var z4406 [1 << 17]byte var z4407 [1 << 17]byte var z4408 [1 << 17]byte var z4409 [1 << 17]byte var z4410 [1 << 17]byte var z4411 [1 << 17]byte var z4412 [1 << 17]byte var z4413 [1 << 17]byte var z4414 [1 << 17]byte var z4415 [1 << 17]byte var z4416 [1 << 17]byte var z4417 [1 << 17]byte var z4418 [1 << 17]byte var z4419 [1 << 17]byte var z4420 [1 << 17]byte var z4421 [1 << 17]byte var z4422 [1 << 17]byte var z4423 [1 << 17]byte var z4424 [1 << 17]byte var z4425 [1 << 17]byte var z4426 [1 << 17]byte var z4427 [1 << 17]byte var z4428 [1 << 17]byte var z4429 [1 << 17]byte var z4430 [1 << 17]byte var z4431 [1 << 17]byte var z4432 [1 << 17]byte var z4433 [1 << 17]byte var z4434 [1 << 17]byte var z4435 [1 << 17]byte var z4436 [1 << 17]byte var z4437 [1 << 17]byte var z4438 [1 << 17]byte var z4439 [1 << 17]byte var z4440 [1 << 17]byte var z4441 [1 << 17]byte var z4442 [1 << 17]byte var z4443 [1 << 17]byte var z4444 [1 << 17]byte var z4445 [1 << 17]byte var z4446 [1 << 17]byte var z4447 [1 << 17]byte var z4448 [1 << 17]byte var z4449 [1 << 17]byte var z4450 [1 << 17]byte var z4451 [1 << 17]byte var z4452 [1 << 17]byte var z4453 [1 << 17]byte var z4454 [1 << 17]byte var z4455 [1 << 17]byte var z4456 [1 << 17]byte var z4457 [1 << 17]byte var z4458 [1 << 17]byte var z4459 [1 << 17]byte var z4460 [1 << 17]byte var z4461 [1 << 17]byte var z4462 [1 << 17]byte var z4463 [1 << 17]byte var z4464 [1 << 17]byte var z4465 [1 << 17]byte var z4466 [1 << 17]byte var z4467 [1 << 17]byte var z4468 [1 << 17]byte var z4469 [1 << 17]byte var z4470 [1 << 17]byte var z4471 [1 << 17]byte var z4472 [1 << 17]byte var z4473 [1 << 17]byte var z4474 [1 << 17]byte var z4475 [1 << 17]byte var z4476 [1 << 17]byte var z4477 [1 << 17]byte var z4478 [1 << 17]byte var z4479 [1 << 17]byte var z4480 [1 << 17]byte var z4481 [1 << 17]byte var z4482 [1 << 17]byte var z4483 [1 << 17]byte var z4484 [1 << 17]byte var z4485 [1 << 17]byte var z4486 [1 << 17]byte var z4487 [1 << 17]byte var z4488 [1 << 17]byte var z4489 [1 << 17]byte var z4490 [1 << 17]byte var z4491 [1 << 17]byte var z4492 [1 << 17]byte var z4493 [1 << 17]byte var z4494 [1 << 17]byte var z4495 [1 << 17]byte var z4496 [1 << 17]byte var z4497 [1 << 17]byte var z4498 [1 << 17]byte var z4499 [1 << 17]byte var z4500 [1 << 17]byte var z4501 [1 << 17]byte var z4502 [1 << 17]byte var z4503 [1 << 17]byte var z4504 [1 << 17]byte var z4505 [1 << 17]byte var z4506 [1 << 17]byte var z4507 [1 << 17]byte var z4508 [1 << 17]byte var z4509 [1 << 17]byte var z4510 [1 << 17]byte var z4511 [1 << 17]byte var z4512 [1 << 17]byte var z4513 [1 << 17]byte var z4514 [1 << 17]byte var z4515 [1 << 17]byte var z4516 [1 << 17]byte var z4517 [1 << 17]byte var z4518 [1 << 17]byte var z4519 [1 << 17]byte var z4520 [1 << 17]byte var z4521 [1 << 17]byte var z4522 [1 << 17]byte var z4523 [1 << 17]byte var z4524 [1 << 17]byte var z4525 [1 << 17]byte var z4526 [1 << 17]byte var z4527 [1 << 17]byte var z4528 [1 << 17]byte var z4529 [1 << 17]byte var z4530 [1 << 17]byte var z4531 [1 << 17]byte var z4532 [1 << 17]byte var z4533 [1 << 17]byte var z4534 [1 << 17]byte var z4535 [1 << 17]byte var z4536 [1 << 17]byte var z4537 [1 << 17]byte var z4538 [1 << 17]byte var z4539 [1 << 17]byte var z4540 [1 << 17]byte var z4541 [1 << 17]byte var z4542 [1 << 17]byte var z4543 [1 << 17]byte var z4544 [1 << 17]byte var z4545 [1 << 17]byte var z4546 [1 << 17]byte var z4547 [1 << 17]byte var z4548 [1 << 17]byte var z4549 [1 << 17]byte var z4550 [1 << 17]byte var z4551 [1 << 17]byte var z4552 [1 << 17]byte var z4553 [1 << 17]byte var z4554 [1 << 17]byte var z4555 [1 << 17]byte var z4556 [1 << 17]byte var z4557 [1 << 17]byte var z4558 [1 << 17]byte var z4559 [1 << 17]byte var z4560 [1 << 17]byte var z4561 [1 << 17]byte var z4562 [1 << 17]byte var z4563 [1 << 17]byte var z4564 [1 << 17]byte var z4565 [1 << 17]byte var z4566 [1 << 17]byte var z4567 [1 << 17]byte var z4568 [1 << 17]byte var z4569 [1 << 17]byte var z4570 [1 << 17]byte var z4571 [1 << 17]byte var z4572 [1 << 17]byte var z4573 [1 << 17]byte var z4574 [1 << 17]byte var z4575 [1 << 17]byte var z4576 [1 << 17]byte var z4577 [1 << 17]byte var z4578 [1 << 17]byte var z4579 [1 << 17]byte var z4580 [1 << 17]byte var z4581 [1 << 17]byte var z4582 [1 << 17]byte var z4583 [1 << 17]byte var z4584 [1 << 17]byte var z4585 [1 << 17]byte var z4586 [1 << 17]byte var z4587 [1 << 17]byte var z4588 [1 << 17]byte var z4589 [1 << 17]byte var z4590 [1 << 17]byte var z4591 [1 << 17]byte var z4592 [1 << 17]byte var z4593 [1 << 17]byte var z4594 [1 << 17]byte var z4595 [1 << 17]byte var z4596 [1 << 17]byte var z4597 [1 << 17]byte var z4598 [1 << 17]byte var z4599 [1 << 17]byte var z4600 [1 << 17]byte var z4601 [1 << 17]byte var z4602 [1 << 17]byte var z4603 [1 << 17]byte var z4604 [1 << 17]byte var z4605 [1 << 17]byte var z4606 [1 << 17]byte var z4607 [1 << 17]byte var z4608 [1 << 17]byte var z4609 [1 << 17]byte var z4610 [1 << 17]byte var z4611 [1 << 17]byte var z4612 [1 << 17]byte var z4613 [1 << 17]byte var z4614 [1 << 17]byte var z4615 [1 << 17]byte var z4616 [1 << 17]byte var z4617 [1 << 17]byte var z4618 [1 << 17]byte var z4619 [1 << 17]byte var z4620 [1 << 17]byte var z4621 [1 << 17]byte var z4622 [1 << 17]byte var z4623 [1 << 17]byte var z4624 [1 << 17]byte var z4625 [1 << 17]byte var z4626 [1 << 17]byte var z4627 [1 << 17]byte var z4628 [1 << 17]byte var z4629 [1 << 17]byte var z4630 [1 << 17]byte var z4631 [1 << 17]byte var z4632 [1 << 17]byte var z4633 [1 << 17]byte var z4634 [1 << 17]byte var z4635 [1 << 17]byte var z4636 [1 << 17]byte var z4637 [1 << 17]byte var z4638 [1 << 17]byte var z4639 [1 << 17]byte var z4640 [1 << 17]byte var z4641 [1 << 17]byte var z4642 [1 << 17]byte var z4643 [1 << 17]byte var z4644 [1 << 17]byte var z4645 [1 << 17]byte var z4646 [1 << 17]byte var z4647 [1 << 17]byte var z4648 [1 << 17]byte var z4649 [1 << 17]byte var z4650 [1 << 17]byte var z4651 [1 << 17]byte var z4652 [1 << 17]byte var z4653 [1 << 17]byte var z4654 [1 << 17]byte var z4655 [1 << 17]byte var z4656 [1 << 17]byte var z4657 [1 << 17]byte var z4658 [1 << 17]byte var z4659 [1 << 17]byte var z4660 [1 << 17]byte var z4661 [1 << 17]byte var z4662 [1 << 17]byte var z4663 [1 << 17]byte var z4664 [1 << 17]byte var z4665 [1 << 17]byte var z4666 [1 << 17]byte var z4667 [1 << 17]byte var z4668 [1 << 17]byte var z4669 [1 << 17]byte var z4670 [1 << 17]byte var z4671 [1 << 17]byte var z4672 [1 << 17]byte var z4673 [1 << 17]byte var z4674 [1 << 17]byte var z4675 [1 << 17]byte var z4676 [1 << 17]byte var z4677 [1 << 17]byte var z4678 [1 << 17]byte var z4679 [1 << 17]byte var z4680 [1 << 17]byte var z4681 [1 << 17]byte var z4682 [1 << 17]byte var z4683 [1 << 17]byte var z4684 [1 << 17]byte var z4685 [1 << 17]byte var z4686 [1 << 17]byte var z4687 [1 << 17]byte var z4688 [1 << 17]byte var z4689 [1 << 17]byte var z4690 [1 << 17]byte var z4691 [1 << 17]byte var z4692 [1 << 17]byte var z4693 [1 << 17]byte var z4694 [1 << 17]byte var z4695 [1 << 17]byte var z4696 [1 << 17]byte var z4697 [1 << 17]byte var z4698 [1 << 17]byte var z4699 [1 << 17]byte var z4700 [1 << 17]byte var z4701 [1 << 17]byte var z4702 [1 << 17]byte var z4703 [1 << 17]byte var z4704 [1 << 17]byte var z4705 [1 << 17]byte var z4706 [1 << 17]byte var z4707 [1 << 17]byte var z4708 [1 << 17]byte var z4709 [1 << 17]byte var z4710 [1 << 17]byte var z4711 [1 << 17]byte var z4712 [1 << 17]byte var z4713 [1 << 17]byte var z4714 [1 << 17]byte var z4715 [1 << 17]byte var z4716 [1 << 17]byte var z4717 [1 << 17]byte var z4718 [1 << 17]byte var z4719 [1 << 17]byte var z4720 [1 << 17]byte var z4721 [1 << 17]byte var z4722 [1 << 17]byte var z4723 [1 << 17]byte var z4724 [1 << 17]byte var z4725 [1 << 17]byte var z4726 [1 << 17]byte var z4727 [1 << 17]byte var z4728 [1 << 17]byte var z4729 [1 << 17]byte var z4730 [1 << 17]byte var z4731 [1 << 17]byte var z4732 [1 << 17]byte var z4733 [1 << 17]byte var z4734 [1 << 17]byte var z4735 [1 << 17]byte var z4736 [1 << 17]byte var z4737 [1 << 17]byte var z4738 [1 << 17]byte var z4739 [1 << 17]byte var z4740 [1 << 17]byte var z4741 [1 << 17]byte var z4742 [1 << 17]byte var z4743 [1 << 17]byte var z4744 [1 << 17]byte var z4745 [1 << 17]byte var z4746 [1 << 17]byte var z4747 [1 << 17]byte var z4748 [1 << 17]byte var z4749 [1 << 17]byte var z4750 [1 << 17]byte var z4751 [1 << 17]byte var z4752 [1 << 17]byte var z4753 [1 << 17]byte var z4754 [1 << 17]byte var z4755 [1 << 17]byte var z4756 [1 << 17]byte var z4757 [1 << 17]byte var z4758 [1 << 17]byte var z4759 [1 << 17]byte var z4760 [1 << 17]byte var z4761 [1 << 17]byte var z4762 [1 << 17]byte var z4763 [1 << 17]byte var z4764 [1 << 17]byte var z4765 [1 << 17]byte var z4766 [1 << 17]byte var z4767 [1 << 17]byte var z4768 [1 << 17]byte var z4769 [1 << 17]byte var z4770 [1 << 17]byte var z4771 [1 << 17]byte var z4772 [1 << 17]byte var z4773 [1 << 17]byte var z4774 [1 << 17]byte var z4775 [1 << 17]byte var z4776 [1 << 17]byte var z4777 [1 << 17]byte var z4778 [1 << 17]byte var z4779 [1 << 17]byte var z4780 [1 << 17]byte var z4781 [1 << 17]byte var z4782 [1 << 17]byte var z4783 [1 << 17]byte var z4784 [1 << 17]byte var z4785 [1 << 17]byte var z4786 [1 << 17]byte var z4787 [1 << 17]byte var z4788 [1 << 17]byte var z4789 [1 << 17]byte var z4790 [1 << 17]byte var z4791 [1 << 17]byte var z4792 [1 << 17]byte var z4793 [1 << 17]byte var z4794 [1 << 17]byte var z4795 [1 << 17]byte var z4796 [1 << 17]byte var z4797 [1 << 17]byte var z4798 [1 << 17]byte var z4799 [1 << 17]byte var z4800 [1 << 17]byte var z4801 [1 << 17]byte var z4802 [1 << 17]byte var z4803 [1 << 17]byte var z4804 [1 << 17]byte var z4805 [1 << 17]byte var z4806 [1 << 17]byte var z4807 [1 << 17]byte var z4808 [1 << 17]byte var z4809 [1 << 17]byte var z4810 [1 << 17]byte var z4811 [1 << 17]byte var z4812 [1 << 17]byte var z4813 [1 << 17]byte var z4814 [1 << 17]byte var z4815 [1 << 17]byte var z4816 [1 << 17]byte var z4817 [1 << 17]byte var z4818 [1 << 17]byte var z4819 [1 << 17]byte var z4820 [1 << 17]byte var z4821 [1 << 17]byte var z4822 [1 << 17]byte var z4823 [1 << 17]byte var z4824 [1 << 17]byte var z4825 [1 << 17]byte var z4826 [1 << 17]byte var z4827 [1 << 17]byte var z4828 [1 << 17]byte var z4829 [1 << 17]byte var z4830 [1 << 17]byte var z4831 [1 << 17]byte var z4832 [1 << 17]byte var z4833 [1 << 17]byte var z4834 [1 << 17]byte var z4835 [1 << 17]byte var z4836 [1 << 17]byte var z4837 [1 << 17]byte var z4838 [1 << 17]byte var z4839 [1 << 17]byte var z4840 [1 << 17]byte var z4841 [1 << 17]byte var z4842 [1 << 17]byte var z4843 [1 << 17]byte var z4844 [1 << 17]byte var z4845 [1 << 17]byte var z4846 [1 << 17]byte var z4847 [1 << 17]byte var z4848 [1 << 17]byte var z4849 [1 << 17]byte var z4850 [1 << 17]byte var z4851 [1 << 17]byte var z4852 [1 << 17]byte var z4853 [1 << 17]byte var z4854 [1 << 17]byte var z4855 [1 << 17]byte var z4856 [1 << 17]byte var z4857 [1 << 17]byte var z4858 [1 << 17]byte var z4859 [1 << 17]byte var z4860 [1 << 17]byte var z4861 [1 << 17]byte var z4862 [1 << 17]byte var z4863 [1 << 17]byte var z4864 [1 << 17]byte var z4865 [1 << 17]byte var z4866 [1 << 17]byte var z4867 [1 << 17]byte var z4868 [1 << 17]byte var z4869 [1 << 17]byte var z4870 [1 << 17]byte var z4871 [1 << 17]byte var z4872 [1 << 17]byte var z4873 [1 << 17]byte var z4874 [1 << 17]byte var z4875 [1 << 17]byte var z4876 [1 << 17]byte var z4877 [1 << 17]byte var z4878 [1 << 17]byte var z4879 [1 << 17]byte var z4880 [1 << 17]byte var z4881 [1 << 17]byte var z4882 [1 << 17]byte var z4883 [1 << 17]byte var z4884 [1 << 17]byte var z4885 [1 << 17]byte var z4886 [1 << 17]byte var z4887 [1 << 17]byte var z4888 [1 << 17]byte var z4889 [1 << 17]byte var z4890 [1 << 17]byte var z4891 [1 << 17]byte var z4892 [1 << 17]byte var z4893 [1 << 17]byte var z4894 [1 << 17]byte var z4895 [1 << 17]byte var z4896 [1 << 17]byte var z4897 [1 << 17]byte var z4898 [1 << 17]byte var z4899 [1 << 17]byte var z4900 [1 << 17]byte var z4901 [1 << 17]byte var z4902 [1 << 17]byte var z4903 [1 << 17]byte var z4904 [1 << 17]byte var z4905 [1 << 17]byte var z4906 [1 << 17]byte var z4907 [1 << 17]byte var z4908 [1 << 17]byte var z4909 [1 << 17]byte var z4910 [1 << 17]byte var z4911 [1 << 17]byte var z4912 [1 << 17]byte var z4913 [1 << 17]byte var z4914 [1 << 17]byte var z4915 [1 << 17]byte var z4916 [1 << 17]byte var z4917 [1 << 17]byte var z4918 [1 << 17]byte var z4919 [1 << 17]byte var z4920 [1 << 17]byte var z4921 [1 << 17]byte var z4922 [1 << 17]byte var z4923 [1 << 17]byte var z4924 [1 << 17]byte var z4925 [1 << 17]byte var z4926 [1 << 17]byte var z4927 [1 << 17]byte var z4928 [1 << 17]byte var z4929 [1 << 17]byte var z4930 [1 << 17]byte var z4931 [1 << 17]byte var z4932 [1 << 17]byte var z4933 [1 << 17]byte var z4934 [1 << 17]byte var z4935 [1 << 17]byte var z4936 [1 << 17]byte var z4937 [1 << 17]byte var z4938 [1 << 17]byte var z4939 [1 << 17]byte var z4940 [1 << 17]byte var z4941 [1 << 17]byte var z4942 [1 << 17]byte var z4943 [1 << 17]byte var z4944 [1 << 17]byte var z4945 [1 << 17]byte var z4946 [1 << 17]byte var z4947 [1 << 17]byte var z4948 [1 << 17]byte var z4949 [1 << 17]byte var z4950 [1 << 17]byte var z4951 [1 << 17]byte var z4952 [1 << 17]byte var z4953 [1 << 17]byte var z4954 [1 << 17]byte var z4955 [1 << 17]byte var z4956 [1 << 17]byte var z4957 [1 << 17]byte var z4958 [1 << 17]byte var z4959 [1 << 17]byte var z4960 [1 << 17]byte var z4961 [1 << 17]byte var z4962 [1 << 17]byte var z4963 [1 << 17]byte var z4964 [1 << 17]byte var z4965 [1 << 17]byte var z4966 [1 << 17]byte var z4967 [1 << 17]byte var z4968 [1 << 17]byte var z4969 [1 << 17]byte var z4970 [1 << 17]byte var z4971 [1 << 17]byte var z4972 [1 << 17]byte var z4973 [1 << 17]byte var z4974 [1 << 17]byte var z4975 [1 << 17]byte var z4976 [1 << 17]byte var z4977 [1 << 17]byte var z4978 [1 << 17]byte var z4979 [1 << 17]byte var z4980 [1 << 17]byte var z4981 [1 << 17]byte var z4982 [1 << 17]byte var z4983 [1 << 17]byte var z4984 [1 << 17]byte var z4985 [1 << 17]byte var z4986 [1 << 17]byte var z4987 [1 << 17]byte var z4988 [1 << 17]byte var z4989 [1 << 17]byte var z4990 [1 << 17]byte var z4991 [1 << 17]byte var z4992 [1 << 17]byte var z4993 [1 << 17]byte var z4994 [1 << 17]byte var z4995 [1 << 17]byte var z4996 [1 << 17]byte var z4997 [1 << 17]byte var z4998 [1 << 17]byte var z4999 [1 << 17]byte var z5000 [1 << 17]byte var z5001 [1 << 17]byte var z5002 [1 << 17]byte var z5003 [1 << 17]byte var z5004 [1 << 17]byte var z5005 [1 << 17]byte var z5006 [1 << 17]byte var z5007 [1 << 17]byte var z5008 [1 << 17]byte var z5009 [1 << 17]byte var z5010 [1 << 17]byte var z5011 [1 << 17]byte var z5012 [1 << 17]byte var z5013 [1 << 17]byte var z5014 [1 << 17]byte var z5015 [1 << 17]byte var z5016 [1 << 17]byte var z5017 [1 << 17]byte var z5018 [1 << 17]byte var z5019 [1 << 17]byte var z5020 [1 << 17]byte var z5021 [1 << 17]byte var z5022 [1 << 17]byte var z5023 [1 << 17]byte var z5024 [1 << 17]byte var z5025 [1 << 17]byte var z5026 [1 << 17]byte var z5027 [1 << 17]byte var z5028 [1 << 17]byte var z5029 [1 << 17]byte var z5030 [1 << 17]byte var z5031 [1 << 17]byte var z5032 [1 << 17]byte var z5033 [1 << 17]byte var z5034 [1 << 17]byte var z5035 [1 << 17]byte var z5036 [1 << 17]byte var z5037 [1 << 17]byte var z5038 [1 << 17]byte var z5039 [1 << 17]byte var z5040 [1 << 17]byte var z5041 [1 << 17]byte var z5042 [1 << 17]byte var z5043 [1 << 17]byte var z5044 [1 << 17]byte var z5045 [1 << 17]byte var z5046 [1 << 17]byte var z5047 [1 << 17]byte var z5048 [1 << 17]byte var z5049 [1 << 17]byte var z5050 [1 << 17]byte var z5051 [1 << 17]byte var z5052 [1 << 17]byte var z5053 [1 << 17]byte var z5054 [1 << 17]byte var z5055 [1 << 17]byte var z5056 [1 << 17]byte var z5057 [1 << 17]byte var z5058 [1 << 17]byte var z5059 [1 << 17]byte var z5060 [1 << 17]byte var z5061 [1 << 17]byte var z5062 [1 << 17]byte var z5063 [1 << 17]byte var z5064 [1 << 17]byte var z5065 [1 << 17]byte var z5066 [1 << 17]byte var z5067 [1 << 17]byte var z5068 [1 << 17]byte var z5069 [1 << 17]byte var z5070 [1 << 17]byte var z5071 [1 << 17]byte var z5072 [1 << 17]byte var z5073 [1 << 17]byte var z5074 [1 << 17]byte var z5075 [1 << 17]byte var z5076 [1 << 17]byte var z5077 [1 << 17]byte var z5078 [1 << 17]byte var z5079 [1 << 17]byte var z5080 [1 << 17]byte var z5081 [1 << 17]byte var z5082 [1 << 17]byte var z5083 [1 << 17]byte var z5084 [1 << 17]byte var z5085 [1 << 17]byte var z5086 [1 << 17]byte var z5087 [1 << 17]byte var z5088 [1 << 17]byte var z5089 [1 << 17]byte var z5090 [1 << 17]byte var z5091 [1 << 17]byte var z5092 [1 << 17]byte var z5093 [1 << 17]byte var z5094 [1 << 17]byte var z5095 [1 << 17]byte var z5096 [1 << 17]byte var z5097 [1 << 17]byte var z5098 [1 << 17]byte var z5099 [1 << 17]byte var z5100 [1 << 17]byte var z5101 [1 << 17]byte var z5102 [1 << 17]byte var z5103 [1 << 17]byte var z5104 [1 << 17]byte var z5105 [1 << 17]byte var z5106 [1 << 17]byte var z5107 [1 << 17]byte var z5108 [1 << 17]byte var z5109 [1 << 17]byte var z5110 [1 << 17]byte var z5111 [1 << 17]byte var z5112 [1 << 17]byte var z5113 [1 << 17]byte var z5114 [1 << 17]byte var z5115 [1 << 17]byte var z5116 [1 << 17]byte var z5117 [1 << 17]byte var z5118 [1 << 17]byte var z5119 [1 << 17]byte var z5120 [1 << 17]byte var z5121 [1 << 17]byte var z5122 [1 << 17]byte var z5123 [1 << 17]byte var z5124 [1 << 17]byte var z5125 [1 << 17]byte var z5126 [1 << 17]byte var z5127 [1 << 17]byte var z5128 [1 << 17]byte var z5129 [1 << 17]byte var z5130 [1 << 17]byte var z5131 [1 << 17]byte var z5132 [1 << 17]byte var z5133 [1 << 17]byte var z5134 [1 << 17]byte var z5135 [1 << 17]byte var z5136 [1 << 17]byte var z5137 [1 << 17]byte var z5138 [1 << 17]byte var z5139 [1 << 17]byte var z5140 [1 << 17]byte var z5141 [1 << 17]byte var z5142 [1 << 17]byte var z5143 [1 << 17]byte var z5144 [1 << 17]byte var z5145 [1 << 17]byte var z5146 [1 << 17]byte var z5147 [1 << 17]byte var z5148 [1 << 17]byte var z5149 [1 << 17]byte var z5150 [1 << 17]byte var z5151 [1 << 17]byte var z5152 [1 << 17]byte var z5153 [1 << 17]byte var z5154 [1 << 17]byte var z5155 [1 << 17]byte var z5156 [1 << 17]byte var z5157 [1 << 17]byte var z5158 [1 << 17]byte var z5159 [1 << 17]byte var z5160 [1 << 17]byte var z5161 [1 << 17]byte var z5162 [1 << 17]byte var z5163 [1 << 17]byte var z5164 [1 << 17]byte var z5165 [1 << 17]byte var z5166 [1 << 17]byte var z5167 [1 << 17]byte var z5168 [1 << 17]byte var z5169 [1 << 17]byte var z5170 [1 << 17]byte var z5171 [1 << 17]byte var z5172 [1 << 17]byte var z5173 [1 << 17]byte var z5174 [1 << 17]byte var z5175 [1 << 17]byte var z5176 [1 << 17]byte var z5177 [1 << 17]byte var z5178 [1 << 17]byte var z5179 [1 << 17]byte var z5180 [1 << 17]byte var z5181 [1 << 17]byte var z5182 [1 << 17]byte var z5183 [1 << 17]byte var z5184 [1 << 17]byte var z5185 [1 << 17]byte var z5186 [1 << 17]byte var z5187 [1 << 17]byte var z5188 [1 << 17]byte var z5189 [1 << 17]byte var z5190 [1 << 17]byte var z5191 [1 << 17]byte var z5192 [1 << 17]byte var z5193 [1 << 17]byte var z5194 [1 << 17]byte var z5195 [1 << 17]byte var z5196 [1 << 17]byte var z5197 [1 << 17]byte var z5198 [1 << 17]byte var z5199 [1 << 17]byte var z5200 [1 << 17]byte var z5201 [1 << 17]byte var z5202 [1 << 17]byte var z5203 [1 << 17]byte var z5204 [1 << 17]byte var z5205 [1 << 17]byte var z5206 [1 << 17]byte var z5207 [1 << 17]byte var z5208 [1 << 17]byte var z5209 [1 << 17]byte var z5210 [1 << 17]byte var z5211 [1 << 17]byte var z5212 [1 << 17]byte var z5213 [1 << 17]byte var z5214 [1 << 17]byte var z5215 [1 << 17]byte var z5216 [1 << 17]byte var z5217 [1 << 17]byte var z5218 [1 << 17]byte var z5219 [1 << 17]byte var z5220 [1 << 17]byte var z5221 [1 << 17]byte var z5222 [1 << 17]byte var z5223 [1 << 17]byte var z5224 [1 << 17]byte var z5225 [1 << 17]byte var z5226 [1 << 17]byte var z5227 [1 << 17]byte var z5228 [1 << 17]byte var z5229 [1 << 17]byte var z5230 [1 << 17]byte var z5231 [1 << 17]byte var z5232 [1 << 17]byte var z5233 [1 << 17]byte var z5234 [1 << 17]byte var z5235 [1 << 17]byte var z5236 [1 << 17]byte var z5237 [1 << 17]byte var z5238 [1 << 17]byte var z5239 [1 << 17]byte var z5240 [1 << 17]byte var z5241 [1 << 17]byte var z5242 [1 << 17]byte var z5243 [1 << 17]byte var z5244 [1 << 17]byte var z5245 [1 << 17]byte var z5246 [1 << 17]byte var z5247 [1 << 17]byte var z5248 [1 << 17]byte var z5249 [1 << 17]byte var z5250 [1 << 17]byte var z5251 [1 << 17]byte var z5252 [1 << 17]byte var z5253 [1 << 17]byte var z5254 [1 << 17]byte var z5255 [1 << 17]byte var z5256 [1 << 17]byte var z5257 [1 << 17]byte var z5258 [1 << 17]byte var z5259 [1 << 17]byte var z5260 [1 << 17]byte var z5261 [1 << 17]byte var z5262 [1 << 17]byte var z5263 [1 << 17]byte var z5264 [1 << 17]byte var z5265 [1 << 17]byte var z5266 [1 << 17]byte var z5267 [1 << 17]byte var z5268 [1 << 17]byte var z5269 [1 << 17]byte var z5270 [1 << 17]byte var z5271 [1 << 17]byte var z5272 [1 << 17]byte var z5273 [1 << 17]byte var z5274 [1 << 17]byte var z5275 [1 << 17]byte var z5276 [1 << 17]byte var z5277 [1 << 17]byte var z5278 [1 << 17]byte var z5279 [1 << 17]byte var z5280 [1 << 17]byte var z5281 [1 << 17]byte var z5282 [1 << 17]byte var z5283 [1 << 17]byte var z5284 [1 << 17]byte var z5285 [1 << 17]byte var z5286 [1 << 17]byte var z5287 [1 << 17]byte var z5288 [1 << 17]byte var z5289 [1 << 17]byte var z5290 [1 << 17]byte var z5291 [1 << 17]byte var z5292 [1 << 17]byte var z5293 [1 << 17]byte var z5294 [1 << 17]byte var z5295 [1 << 17]byte var z5296 [1 << 17]byte var z5297 [1 << 17]byte var z5298 [1 << 17]byte var z5299 [1 << 17]byte var z5300 [1 << 17]byte var z5301 [1 << 17]byte var z5302 [1 << 17]byte var z5303 [1 << 17]byte var z5304 [1 << 17]byte var z5305 [1 << 17]byte var z5306 [1 << 17]byte var z5307 [1 << 17]byte var z5308 [1 << 17]byte var z5309 [1 << 17]byte var z5310 [1 << 17]byte var z5311 [1 << 17]byte var z5312 [1 << 17]byte var z5313 [1 << 17]byte var z5314 [1 << 17]byte var z5315 [1 << 17]byte var z5316 [1 << 17]byte var z5317 [1 << 17]byte var z5318 [1 << 17]byte var z5319 [1 << 17]byte var z5320 [1 << 17]byte var z5321 [1 << 17]byte var z5322 [1 << 17]byte var z5323 [1 << 17]byte var z5324 [1 << 17]byte var z5325 [1 << 17]byte var z5326 [1 << 17]byte var z5327 [1 << 17]byte var z5328 [1 << 17]byte var z5329 [1 << 17]byte var z5330 [1 << 17]byte var z5331 [1 << 17]byte var z5332 [1 << 17]byte var z5333 [1 << 17]byte var z5334 [1 << 17]byte var z5335 [1 << 17]byte var z5336 [1 << 17]byte var z5337 [1 << 17]byte var z5338 [1 << 17]byte var z5339 [1 << 17]byte var z5340 [1 << 17]byte var z5341 [1 << 17]byte var z5342 [1 << 17]byte var z5343 [1 << 17]byte var z5344 [1 << 17]byte var z5345 [1 << 17]byte var z5346 [1 << 17]byte var z5347 [1 << 17]byte var z5348 [1 << 17]byte var z5349 [1 << 17]byte var z5350 [1 << 17]byte var z5351 [1 << 17]byte var z5352 [1 << 17]byte var z5353 [1 << 17]byte var z5354 [1 << 17]byte var z5355 [1 << 17]byte var z5356 [1 << 17]byte var z5357 [1 << 17]byte var z5358 [1 << 17]byte var z5359 [1 << 17]byte var z5360 [1 << 17]byte var z5361 [1 << 17]byte var z5362 [1 << 17]byte var z5363 [1 << 17]byte var z5364 [1 << 17]byte var z5365 [1 << 17]byte var z5366 [1 << 17]byte var z5367 [1 << 17]byte var z5368 [1 << 17]byte var z5369 [1 << 17]byte var z5370 [1 << 17]byte var z5371 [1 << 17]byte var z5372 [1 << 17]byte var z5373 [1 << 17]byte var z5374 [1 << 17]byte var z5375 [1 << 17]byte var z5376 [1 << 17]byte var z5377 [1 << 17]byte var z5378 [1 << 17]byte var z5379 [1 << 17]byte var z5380 [1 << 17]byte var z5381 [1 << 17]byte var z5382 [1 << 17]byte var z5383 [1 << 17]byte var z5384 [1 << 17]byte var z5385 [1 << 17]byte var z5386 [1 << 17]byte var z5387 [1 << 17]byte var z5388 [1 << 17]byte var z5389 [1 << 17]byte var z5390 [1 << 17]byte var z5391 [1 << 17]byte var z5392 [1 << 17]byte var z5393 [1 << 17]byte var z5394 [1 << 17]byte var z5395 [1 << 17]byte var z5396 [1 << 17]byte var z5397 [1 << 17]byte var z5398 [1 << 17]byte var z5399 [1 << 17]byte var z5400 [1 << 17]byte var z5401 [1 << 17]byte var z5402 [1 << 17]byte var z5403 [1 << 17]byte var z5404 [1 << 17]byte var z5405 [1 << 17]byte var z5406 [1 << 17]byte var z5407 [1 << 17]byte var z5408 [1 << 17]byte var z5409 [1 << 17]byte var z5410 [1 << 17]byte var z5411 [1 << 17]byte var z5412 [1 << 17]byte var z5413 [1 << 17]byte var z5414 [1 << 17]byte var z5415 [1 << 17]byte var z5416 [1 << 17]byte var z5417 [1 << 17]byte var z5418 [1 << 17]byte var z5419 [1 << 17]byte var z5420 [1 << 17]byte var z5421 [1 << 17]byte var z5422 [1 << 17]byte var z5423 [1 << 17]byte var z5424 [1 << 17]byte var z5425 [1 << 17]byte var z5426 [1 << 17]byte var z5427 [1 << 17]byte var z5428 [1 << 17]byte var z5429 [1 << 17]byte var z5430 [1 << 17]byte var z5431 [1 << 17]byte var z5432 [1 << 17]byte var z5433 [1 << 17]byte var z5434 [1 << 17]byte var z5435 [1 << 17]byte var z5436 [1 << 17]byte var z5437 [1 << 17]byte var z5438 [1 << 17]byte var z5439 [1 << 17]byte var z5440 [1 << 17]byte var z5441 [1 << 17]byte var z5442 [1 << 17]byte var z5443 [1 << 17]byte var z5444 [1 << 17]byte var z5445 [1 << 17]byte var z5446 [1 << 17]byte var z5447 [1 << 17]byte var z5448 [1 << 17]byte var z5449 [1 << 17]byte var z5450 [1 << 17]byte var z5451 [1 << 17]byte var z5452 [1 << 17]byte var z5453 [1 << 17]byte var z5454 [1 << 17]byte var z5455 [1 << 17]byte var z5456 [1 << 17]byte var z5457 [1 << 17]byte var z5458 [1 << 17]byte var z5459 [1 << 17]byte var z5460 [1 << 17]byte var z5461 [1 << 17]byte var z5462 [1 << 17]byte var z5463 [1 << 17]byte var z5464 [1 << 17]byte var z5465 [1 << 17]byte var z5466 [1 << 17]byte var z5467 [1 << 17]byte var z5468 [1 << 17]byte var z5469 [1 << 17]byte var z5470 [1 << 17]byte var z5471 [1 << 17]byte var z5472 [1 << 17]byte var z5473 [1 << 17]byte var z5474 [1 << 17]byte var z5475 [1 << 17]byte var z5476 [1 << 17]byte var z5477 [1 << 17]byte var z5478 [1 << 17]byte var z5479 [1 << 17]byte var z5480 [1 << 17]byte var z5481 [1 << 17]byte var z5482 [1 << 17]byte var z5483 [1 << 17]byte var z5484 [1 << 17]byte var z5485 [1 << 17]byte var z5486 [1 << 17]byte var z5487 [1 << 17]byte var z5488 [1 << 17]byte var z5489 [1 << 17]byte var z5490 [1 << 17]byte var z5491 [1 << 17]byte var z5492 [1 << 17]byte var z5493 [1 << 17]byte var z5494 [1 << 17]byte var z5495 [1 << 17]byte var z5496 [1 << 17]byte var z5497 [1 << 17]byte var z5498 [1 << 17]byte var z5499 [1 << 17]byte var z5500 [1 << 17]byte var z5501 [1 << 17]byte var z5502 [1 << 17]byte var z5503 [1 << 17]byte var z5504 [1 << 17]byte var z5505 [1 << 17]byte var z5506 [1 << 17]byte var z5507 [1 << 17]byte var z5508 [1 << 17]byte var z5509 [1 << 17]byte var z5510 [1 << 17]byte var z5511 [1 << 17]byte var z5512 [1 << 17]byte var z5513 [1 << 17]byte var z5514 [1 << 17]byte var z5515 [1 << 17]byte var z5516 [1 << 17]byte var z5517 [1 << 17]byte var z5518 [1 << 17]byte var z5519 [1 << 17]byte var z5520 [1 << 17]byte var z5521 [1 << 17]byte var z5522 [1 << 17]byte var z5523 [1 << 17]byte var z5524 [1 << 17]byte var z5525 [1 << 17]byte var z5526 [1 << 17]byte var z5527 [1 << 17]byte var z5528 [1 << 17]byte var z5529 [1 << 17]byte var z5530 [1 << 17]byte var z5531 [1 << 17]byte var z5532 [1 << 17]byte var z5533 [1 << 17]byte var z5534 [1 << 17]byte var z5535 [1 << 17]byte var z5536 [1 << 17]byte var z5537 [1 << 17]byte var z5538 [1 << 17]byte var z5539 [1 << 17]byte var z5540 [1 << 17]byte var z5541 [1 << 17]byte var z5542 [1 << 17]byte var z5543 [1 << 17]byte var z5544 [1 << 17]byte var z5545 [1 << 17]byte var z5546 [1 << 17]byte var z5547 [1 << 17]byte var z5548 [1 << 17]byte var z5549 [1 << 17]byte var z5550 [1 << 17]byte var z5551 [1 << 17]byte var z5552 [1 << 17]byte var z5553 [1 << 17]byte var z5554 [1 << 17]byte var z5555 [1 << 17]byte var z5556 [1 << 17]byte var z5557 [1 << 17]byte var z5558 [1 << 17]byte var z5559 [1 << 17]byte var z5560 [1 << 17]byte var z5561 [1 << 17]byte var z5562 [1 << 17]byte var z5563 [1 << 17]byte var z5564 [1 << 17]byte var z5565 [1 << 17]byte var z5566 [1 << 17]byte var z5567 [1 << 17]byte var z5568 [1 << 17]byte var z5569 [1 << 17]byte var z5570 [1 << 17]byte var z5571 [1 << 17]byte var z5572 [1 << 17]byte var z5573 [1 << 17]byte var z5574 [1 << 17]byte var z5575 [1 << 17]byte var z5576 [1 << 17]byte var z5577 [1 << 17]byte var z5578 [1 << 17]byte var z5579 [1 << 17]byte var z5580 [1 << 17]byte var z5581 [1 << 17]byte var z5582 [1 << 17]byte var z5583 [1 << 17]byte var z5584 [1 << 17]byte var z5585 [1 << 17]byte var z5586 [1 << 17]byte var z5587 [1 << 17]byte var z5588 [1 << 17]byte var z5589 [1 << 17]byte var z5590 [1 << 17]byte var z5591 [1 << 17]byte var z5592 [1 << 17]byte var z5593 [1 << 17]byte var z5594 [1 << 17]byte var z5595 [1 << 17]byte var z5596 [1 << 17]byte var z5597 [1 << 17]byte var z5598 [1 << 17]byte var z5599 [1 << 17]byte var z5600 [1 << 17]byte var z5601 [1 << 17]byte var z5602 [1 << 17]byte var z5603 [1 << 17]byte var z5604 [1 << 17]byte var z5605 [1 << 17]byte var z5606 [1 << 17]byte var z5607 [1 << 17]byte var z5608 [1 << 17]byte var z5609 [1 << 17]byte var z5610 [1 << 17]byte var z5611 [1 << 17]byte var z5612 [1 << 17]byte var z5613 [1 << 17]byte var z5614 [1 << 17]byte var z5615 [1 << 17]byte var z5616 [1 << 17]byte var z5617 [1 << 17]byte var z5618 [1 << 17]byte var z5619 [1 << 17]byte var z5620 [1 << 17]byte var z5621 [1 << 17]byte var z5622 [1 << 17]byte var z5623 [1 << 17]byte var z5624 [1 << 17]byte var z5625 [1 << 17]byte var z5626 [1 << 17]byte var z5627 [1 << 17]byte var z5628 [1 << 17]byte var z5629 [1 << 17]byte var z5630 [1 << 17]byte var z5631 [1 << 17]byte var z5632 [1 << 17]byte var z5633 [1 << 17]byte var z5634 [1 << 17]byte var z5635 [1 << 17]byte var z5636 [1 << 17]byte var z5637 [1 << 17]byte var z5638 [1 << 17]byte var z5639 [1 << 17]byte var z5640 [1 << 17]byte var z5641 [1 << 17]byte var z5642 [1 << 17]byte var z5643 [1 << 17]byte var z5644 [1 << 17]byte var z5645 [1 << 17]byte var z5646 [1 << 17]byte var z5647 [1 << 17]byte var z5648 [1 << 17]byte var z5649 [1 << 17]byte var z5650 [1 << 17]byte var z5651 [1 << 17]byte var z5652 [1 << 17]byte var z5653 [1 << 17]byte var z5654 [1 << 17]byte var z5655 [1 << 17]byte var z5656 [1 << 17]byte var z5657 [1 << 17]byte var z5658 [1 << 17]byte var z5659 [1 << 17]byte var z5660 [1 << 17]byte var z5661 [1 << 17]byte var z5662 [1 << 17]byte var z5663 [1 << 17]byte var z5664 [1 << 17]byte var z5665 [1 << 17]byte var z5666 [1 << 17]byte var z5667 [1 << 17]byte var z5668 [1 << 17]byte var z5669 [1 << 17]byte var z5670 [1 << 17]byte var z5671 [1 << 17]byte var z5672 [1 << 17]byte var z5673 [1 << 17]byte var z5674 [1 << 17]byte var z5675 [1 << 17]byte var z5676 [1 << 17]byte var z5677 [1 << 17]byte var z5678 [1 << 17]byte var z5679 [1 << 17]byte var z5680 [1 << 17]byte var z5681 [1 << 17]byte var z5682 [1 << 17]byte var z5683 [1 << 17]byte var z5684 [1 << 17]byte var z5685 [1 << 17]byte var z5686 [1 << 17]byte var z5687 [1 << 17]byte var z5688 [1 << 17]byte var z5689 [1 << 17]byte var z5690 [1 << 17]byte var z5691 [1 << 17]byte var z5692 [1 << 17]byte var z5693 [1 << 17]byte var z5694 [1 << 17]byte var z5695 [1 << 17]byte var z5696 [1 << 17]byte var z5697 [1 << 17]byte var z5698 [1 << 17]byte var z5699 [1 << 17]byte var z5700 [1 << 17]byte var z5701 [1 << 17]byte var z5702 [1 << 17]byte var z5703 [1 << 17]byte var z5704 [1 << 17]byte var z5705 [1 << 17]byte var z5706 [1 << 17]byte var z5707 [1 << 17]byte var z5708 [1 << 17]byte var z5709 [1 << 17]byte var z5710 [1 << 17]byte var z5711 [1 << 17]byte var z5712 [1 << 17]byte var z5713 [1 << 17]byte var z5714 [1 << 17]byte var z5715 [1 << 17]byte var z5716 [1 << 17]byte var z5717 [1 << 17]byte var z5718 [1 << 17]byte var z5719 [1 << 17]byte var z5720 [1 << 17]byte var z5721 [1 << 17]byte var z5722 [1 << 17]byte var z5723 [1 << 17]byte var z5724 [1 << 17]byte var z5725 [1 << 17]byte var z5726 [1 << 17]byte var z5727 [1 << 17]byte var z5728 [1 << 17]byte var z5729 [1 << 17]byte var z5730 [1 << 17]byte var z5731 [1 << 17]byte var z5732 [1 << 17]byte var z5733 [1 << 17]byte var z5734 [1 << 17]byte var z5735 [1 << 17]byte var z5736 [1 << 17]byte var z5737 [1 << 17]byte var z5738 [1 << 17]byte var z5739 [1 << 17]byte var z5740 [1 << 17]byte var z5741 [1 << 17]byte var z5742 [1 << 17]byte var z5743 [1 << 17]byte var z5744 [1 << 17]byte var z5745 [1 << 17]byte var z5746 [1 << 17]byte var z5747 [1 << 17]byte var z5748 [1 << 17]byte var z5749 [1 << 17]byte var z5750 [1 << 17]byte var z5751 [1 << 17]byte var z5752 [1 << 17]byte var z5753 [1 << 17]byte var z5754 [1 << 17]byte var z5755 [1 << 17]byte var z5756 [1 << 17]byte var z5757 [1 << 17]byte var z5758 [1 << 17]byte var z5759 [1 << 17]byte var z5760 [1 << 17]byte var z5761 [1 << 17]byte var z5762 [1 << 17]byte var z5763 [1 << 17]byte var z5764 [1 << 17]byte var z5765 [1 << 17]byte var z5766 [1 << 17]byte var z5767 [1 << 17]byte var z5768 [1 << 17]byte var z5769 [1 << 17]byte var z5770 [1 << 17]byte var z5771 [1 << 17]byte var z5772 [1 << 17]byte var z5773 [1 << 17]byte var z5774 [1 << 17]byte var z5775 [1 << 17]byte var z5776 [1 << 17]byte var z5777 [1 << 17]byte var z5778 [1 << 17]byte var z5779 [1 << 17]byte var z5780 [1 << 17]byte var z5781 [1 << 17]byte var z5782 [1 << 17]byte var z5783 [1 << 17]byte var z5784 [1 << 17]byte var z5785 [1 << 17]byte var z5786 [1 << 17]byte var z5787 [1 << 17]byte var z5788 [1 << 17]byte var z5789 [1 << 17]byte var z5790 [1 << 17]byte var z5791 [1 << 17]byte var z5792 [1 << 17]byte var z5793 [1 << 17]byte var z5794 [1 << 17]byte var z5795 [1 << 17]byte var z5796 [1 << 17]byte var z5797 [1 << 17]byte var z5798 [1 << 17]byte var z5799 [1 << 17]byte var z5800 [1 << 17]byte var z5801 [1 << 17]byte var z5802 [1 << 17]byte var z5803 [1 << 17]byte var z5804 [1 << 17]byte var z5805 [1 << 17]byte var z5806 [1 << 17]byte var z5807 [1 << 17]byte var z5808 [1 << 17]byte var z5809 [1 << 17]byte var z5810 [1 << 17]byte var z5811 [1 << 17]byte var z5812 [1 << 17]byte var z5813 [1 << 17]byte var z5814 [1 << 17]byte var z5815 [1 << 17]byte var z5816 [1 << 17]byte var z5817 [1 << 17]byte var z5818 [1 << 17]byte var z5819 [1 << 17]byte var z5820 [1 << 17]byte var z5821 [1 << 17]byte var z5822 [1 << 17]byte var z5823 [1 << 17]byte var z5824 [1 << 17]byte var z5825 [1 << 17]byte var z5826 [1 << 17]byte var z5827 [1 << 17]byte var z5828 [1 << 17]byte var z5829 [1 << 17]byte var z5830 [1 << 17]byte var z5831 [1 << 17]byte var z5832 [1 << 17]byte var z5833 [1 << 17]byte var z5834 [1 << 17]byte var z5835 [1 << 17]byte var z5836 [1 << 17]byte var z5837 [1 << 17]byte var z5838 [1 << 17]byte var z5839 [1 << 17]byte var z5840 [1 << 17]byte var z5841 [1 << 17]byte var z5842 [1 << 17]byte var z5843 [1 << 17]byte var z5844 [1 << 17]byte var z5845 [1 << 17]byte var z5846 [1 << 17]byte var z5847 [1 << 17]byte var z5848 [1 << 17]byte var z5849 [1 << 17]byte var z5850 [1 << 17]byte var z5851 [1 << 17]byte var z5852 [1 << 17]byte var z5853 [1 << 17]byte var z5854 [1 << 17]byte var z5855 [1 << 17]byte var z5856 [1 << 17]byte var z5857 [1 << 17]byte var z5858 [1 << 17]byte var z5859 [1 << 17]byte var z5860 [1 << 17]byte var z5861 [1 << 17]byte var z5862 [1 << 17]byte var z5863 [1 << 17]byte var z5864 [1 << 17]byte var z5865 [1 << 17]byte var z5866 [1 << 17]byte var z5867 [1 << 17]byte var z5868 [1 << 17]byte var z5869 [1 << 17]byte var z5870 [1 << 17]byte var z5871 [1 << 17]byte var z5872 [1 << 17]byte var z5873 [1 << 17]byte var z5874 [1 << 17]byte var z5875 [1 << 17]byte var z5876 [1 << 17]byte var z5877 [1 << 17]byte var z5878 [1 << 17]byte var z5879 [1 << 17]byte var z5880 [1 << 17]byte var z5881 [1 << 17]byte var z5882 [1 << 17]byte var z5883 [1 << 17]byte var z5884 [1 << 17]byte var z5885 [1 << 17]byte var z5886 [1 << 17]byte var z5887 [1 << 17]byte var z5888 [1 << 17]byte var z5889 [1 << 17]byte var z5890 [1 << 17]byte var z5891 [1 << 17]byte var z5892 [1 << 17]byte var z5893 [1 << 17]byte var z5894 [1 << 17]byte var z5895 [1 << 17]byte var z5896 [1 << 17]byte var z5897 [1 << 17]byte var z5898 [1 << 17]byte var z5899 [1 << 17]byte var z5900 [1 << 17]byte var z5901 [1 << 17]byte var z5902 [1 << 17]byte var z5903 [1 << 17]byte var z5904 [1 << 17]byte var z5905 [1 << 17]byte var z5906 [1 << 17]byte var z5907 [1 << 17]byte var z5908 [1 << 17]byte var z5909 [1 << 17]byte var z5910 [1 << 17]byte var z5911 [1 << 17]byte var z5912 [1 << 17]byte var z5913 [1 << 17]byte var z5914 [1 << 17]byte var z5915 [1 << 17]byte var z5916 [1 << 17]byte var z5917 [1 << 17]byte var z5918 [1 << 17]byte var z5919 [1 << 17]byte var z5920 [1 << 17]byte var z5921 [1 << 17]byte var z5922 [1 << 17]byte var z5923 [1 << 17]byte var z5924 [1 << 17]byte var z5925 [1 << 17]byte var z5926 [1 << 17]byte var z5927 [1 << 17]byte var z5928 [1 << 17]byte var z5929 [1 << 17]byte var z5930 [1 << 17]byte var z5931 [1 << 17]byte var z5932 [1 << 17]byte var z5933 [1 << 17]byte var z5934 [1 << 17]byte var z5935 [1 << 17]byte var z5936 [1 << 17]byte var z5937 [1 << 17]byte var z5938 [1 << 17]byte var z5939 [1 << 17]byte var z5940 [1 << 17]byte var z5941 [1 << 17]byte var z5942 [1 << 17]byte var z5943 [1 << 17]byte var z5944 [1 << 17]byte var z5945 [1 << 17]byte var z5946 [1 << 17]byte var z5947 [1 << 17]byte var z5948 [1 << 17]byte var z5949 [1 << 17]byte var z5950 [1 << 17]byte var z5951 [1 << 17]byte var z5952 [1 << 17]byte var z5953 [1 << 17]byte var z5954 [1 << 17]byte var z5955 [1 << 17]byte var z5956 [1 << 17]byte var z5957 [1 << 17]byte var z5958 [1 << 17]byte var z5959 [1 << 17]byte var z5960 [1 << 17]byte var z5961 [1 << 17]byte var z5962 [1 << 17]byte var z5963 [1 << 17]byte var z5964 [1 << 17]byte var z5965 [1 << 17]byte var z5966 [1 << 17]byte var z5967 [1 << 17]byte var z5968 [1 << 17]byte var z5969 [1 << 17]byte var z5970 [1 << 17]byte var z5971 [1 << 17]byte var z5972 [1 << 17]byte var z5973 [1 << 17]byte var z5974 [1 << 17]byte var z5975 [1 << 17]byte var z5976 [1 << 17]byte var z5977 [1 << 17]byte var z5978 [1 << 17]byte var z5979 [1 << 17]byte var z5980 [1 << 17]byte var z5981 [1 << 17]byte var z5982 [1 << 17]byte var z5983 [1 << 17]byte var z5984 [1 << 17]byte var z5985 [1 << 17]byte var z5986 [1 << 17]byte var z5987 [1 << 17]byte var z5988 [1 << 17]byte var z5989 [1 << 17]byte var z5990 [1 << 17]byte var z5991 [1 << 17]byte var z5992 [1 << 17]byte var z5993 [1 << 17]byte var z5994 [1 << 17]byte var z5995 [1 << 17]byte var z5996 [1 << 17]byte var z5997 [1 << 17]byte var z5998 [1 << 17]byte var z5999 [1 << 17]byte var z6000 [1 << 17]byte var z6001 [1 << 17]byte var z6002 [1 << 17]byte var z6003 [1 << 17]byte var z6004 [1 << 17]byte var z6005 [1 << 17]byte var z6006 [1 << 17]byte var z6007 [1 << 17]byte var z6008 [1 << 17]byte var z6009 [1 << 17]byte var z6010 [1 << 17]byte var z6011 [1 << 17]byte var z6012 [1 << 17]byte var z6013 [1 << 17]byte var z6014 [1 << 17]byte var z6015 [1 << 17]byte var z6016 [1 << 17]byte var z6017 [1 << 17]byte var z6018 [1 << 17]byte var z6019 [1 << 17]byte var z6020 [1 << 17]byte var z6021 [1 << 17]byte var z6022 [1 << 17]byte var z6023 [1 << 17]byte var z6024 [1 << 17]byte var z6025 [1 << 17]byte var z6026 [1 << 17]byte var z6027 [1 << 17]byte var z6028 [1 << 17]byte var z6029 [1 << 17]byte var z6030 [1 << 17]byte var z6031 [1 << 17]byte var z6032 [1 << 17]byte var z6033 [1 << 17]byte var z6034 [1 << 17]byte var z6035 [1 << 17]byte var z6036 [1 << 17]byte var z6037 [1 << 17]byte var z6038 [1 << 17]byte var z6039 [1 << 17]byte var z6040 [1 << 17]byte var z6041 [1 << 17]byte var z6042 [1 << 17]byte var z6043 [1 << 17]byte var z6044 [1 << 17]byte var z6045 [1 << 17]byte var z6046 [1 << 17]byte var z6047 [1 << 17]byte var z6048 [1 << 17]byte var z6049 [1 << 17]byte var z6050 [1 << 17]byte var z6051 [1 << 17]byte var z6052 [1 << 17]byte var z6053 [1 << 17]byte var z6054 [1 << 17]byte var z6055 [1 << 17]byte var z6056 [1 << 17]byte var z6057 [1 << 17]byte var z6058 [1 << 17]byte var z6059 [1 << 17]byte var z6060 [1 << 17]byte var z6061 [1 << 17]byte var z6062 [1 << 17]byte var z6063 [1 << 17]byte var z6064 [1 << 17]byte var z6065 [1 << 17]byte var z6066 [1 << 17]byte var z6067 [1 << 17]byte var z6068 [1 << 17]byte var z6069 [1 << 17]byte var z6070 [1 << 17]byte var z6071 [1 << 17]byte var z6072 [1 << 17]byte var z6073 [1 << 17]byte var z6074 [1 << 17]byte var z6075 [1 << 17]byte var z6076 [1 << 17]byte var z6077 [1 << 17]byte var z6078 [1 << 17]byte var z6079 [1 << 17]byte var z6080 [1 << 17]byte var z6081 [1 << 17]byte var z6082 [1 << 17]byte var z6083 [1 << 17]byte var z6084 [1 << 17]byte var z6085 [1 << 17]byte var z6086 [1 << 17]byte var z6087 [1 << 17]byte var z6088 [1 << 17]byte var z6089 [1 << 17]byte var z6090 [1 << 17]byte var z6091 [1 << 17]byte var z6092 [1 << 17]byte var z6093 [1 << 17]byte var z6094 [1 << 17]byte var z6095 [1 << 17]byte var z6096 [1 << 17]byte var z6097 [1 << 17]byte var z6098 [1 << 17]byte var z6099 [1 << 17]byte var z6100 [1 << 17]byte var z6101 [1 << 17]byte var z6102 [1 << 17]byte var z6103 [1 << 17]byte var z6104 [1 << 17]byte var z6105 [1 << 17]byte var z6106 [1 << 17]byte var z6107 [1 << 17]byte var z6108 [1 << 17]byte var z6109 [1 << 17]byte var z6110 [1 << 17]byte var z6111 [1 << 17]byte var z6112 [1 << 17]byte var z6113 [1 << 17]byte var z6114 [1 << 17]byte var z6115 [1 << 17]byte var z6116 [1 << 17]byte var z6117 [1 << 17]byte var z6118 [1 << 17]byte var z6119 [1 << 17]byte var z6120 [1 << 17]byte var z6121 [1 << 17]byte var z6122 [1 << 17]byte var z6123 [1 << 17]byte var z6124 [1 << 17]byte var z6125 [1 << 17]byte var z6126 [1 << 17]byte var z6127 [1 << 17]byte var z6128 [1 << 17]byte var z6129 [1 << 17]byte var z6130 [1 << 17]byte var z6131 [1 << 17]byte var z6132 [1 << 17]byte var z6133 [1 << 17]byte var z6134 [1 << 17]byte var z6135 [1 << 17]byte var z6136 [1 << 17]byte var z6137 [1 << 17]byte var z6138 [1 << 17]byte var z6139 [1 << 17]byte var z6140 [1 << 17]byte var z6141 [1 << 17]byte var z6142 [1 << 17]byte var z6143 [1 << 17]byte var z6144 [1 << 17]byte var z6145 [1 << 17]byte var z6146 [1 << 17]byte var z6147 [1 << 17]byte var z6148 [1 << 17]byte var z6149 [1 << 17]byte var z6150 [1 << 17]byte var z6151 [1 << 17]byte var z6152 [1 << 17]byte var z6153 [1 << 17]byte var z6154 [1 << 17]byte var z6155 [1 << 17]byte var z6156 [1 << 17]byte var z6157 [1 << 17]byte var z6158 [1 << 17]byte var z6159 [1 << 17]byte var z6160 [1 << 17]byte var z6161 [1 << 17]byte var z6162 [1 << 17]byte var z6163 [1 << 17]byte var z6164 [1 << 17]byte var z6165 [1 << 17]byte var z6166 [1 << 17]byte var z6167 [1 << 17]byte var z6168 [1 << 17]byte var z6169 [1 << 17]byte var z6170 [1 << 17]byte var z6171 [1 << 17]byte var z6172 [1 << 17]byte var z6173 [1 << 17]byte var z6174 [1 << 17]byte var z6175 [1 << 17]byte var z6176 [1 << 17]byte var z6177 [1 << 17]byte var z6178 [1 << 17]byte var z6179 [1 << 17]byte var z6180 [1 << 17]byte var z6181 [1 << 17]byte var z6182 [1 << 17]byte var z6183 [1 << 17]byte var z6184 [1 << 17]byte var z6185 [1 << 17]byte var z6186 [1 << 17]byte var z6187 [1 << 17]byte var z6188 [1 << 17]byte var z6189 [1 << 17]byte var z6190 [1 << 17]byte var z6191 [1 << 17]byte var z6192 [1 << 17]byte var z6193 [1 << 17]byte var z6194 [1 << 17]byte var z6195 [1 << 17]byte var z6196 [1 << 17]byte var z6197 [1 << 17]byte var z6198 [1 << 17]byte var z6199 [1 << 17]byte var z6200 [1 << 17]byte var z6201 [1 << 17]byte var z6202 [1 << 17]byte var z6203 [1 << 17]byte var z6204 [1 << 17]byte var z6205 [1 << 17]byte var z6206 [1 << 17]byte var z6207 [1 << 17]byte var z6208 [1 << 17]byte var z6209 [1 << 17]byte var z6210 [1 << 17]byte var z6211 [1 << 17]byte var z6212 [1 << 17]byte var z6213 [1 << 17]byte var z6214 [1 << 17]byte var z6215 [1 << 17]byte var z6216 [1 << 17]byte var z6217 [1 << 17]byte var z6218 [1 << 17]byte var z6219 [1 << 17]byte var z6220 [1 << 17]byte var z6221 [1 << 17]byte var z6222 [1 << 17]byte var z6223 [1 << 17]byte var z6224 [1 << 17]byte var z6225 [1 << 17]byte var z6226 [1 << 17]byte var z6227 [1 << 17]byte var z6228 [1 << 17]byte var z6229 [1 << 17]byte var z6230 [1 << 17]byte var z6231 [1 << 17]byte var z6232 [1 << 17]byte var z6233 [1 << 17]byte var z6234 [1 << 17]byte var z6235 [1 << 17]byte var z6236 [1 << 17]byte var z6237 [1 << 17]byte var z6238 [1 << 17]byte var z6239 [1 << 17]byte var z6240 [1 << 17]byte var z6241 [1 << 17]byte var z6242 [1 << 17]byte var z6243 [1 << 17]byte var z6244 [1 << 17]byte var z6245 [1 << 17]byte var z6246 [1 << 17]byte var z6247 [1 << 17]byte var z6248 [1 << 17]byte var z6249 [1 << 17]byte var z6250 [1 << 17]byte var z6251 [1 << 17]byte var z6252 [1 << 17]byte var z6253 [1 << 17]byte var z6254 [1 << 17]byte var z6255 [1 << 17]byte var z6256 [1 << 17]byte var z6257 [1 << 17]byte var z6258 [1 << 17]byte var z6259 [1 << 17]byte var z6260 [1 << 17]byte var z6261 [1 << 17]byte var z6262 [1 << 17]byte var z6263 [1 << 17]byte var z6264 [1 << 17]byte var z6265 [1 << 17]byte var z6266 [1 << 17]byte var z6267 [1 << 17]byte var z6268 [1 << 17]byte var z6269 [1 << 17]byte var z6270 [1 << 17]byte var z6271 [1 << 17]byte var z6272 [1 << 17]byte var z6273 [1 << 17]byte var z6274 [1 << 17]byte var z6275 [1 << 17]byte var z6276 [1 << 17]byte var z6277 [1 << 17]byte var z6278 [1 << 17]byte var z6279 [1 << 17]byte var z6280 [1 << 17]byte var z6281 [1 << 17]byte var z6282 [1 << 17]byte var z6283 [1 << 17]byte var z6284 [1 << 17]byte var z6285 [1 << 17]byte var z6286 [1 << 17]byte var z6287 [1 << 17]byte var z6288 [1 << 17]byte var z6289 [1 << 17]byte var z6290 [1 << 17]byte var z6291 [1 << 17]byte var z6292 [1 << 17]byte var z6293 [1 << 17]byte var z6294 [1 << 17]byte var z6295 [1 << 17]byte var z6296 [1 << 17]byte var z6297 [1 << 17]byte var z6298 [1 << 17]byte var z6299 [1 << 17]byte var z6300 [1 << 17]byte var z6301 [1 << 17]byte var z6302 [1 << 17]byte var z6303 [1 << 17]byte var z6304 [1 << 17]byte var z6305 [1 << 17]byte var z6306 [1 << 17]byte var z6307 [1 << 17]byte var z6308 [1 << 17]byte var z6309 [1 << 17]byte var z6310 [1 << 17]byte var z6311 [1 << 17]byte var z6312 [1 << 17]byte var z6313 [1 << 17]byte var z6314 [1 << 17]byte var z6315 [1 << 17]byte var z6316 [1 << 17]byte var z6317 [1 << 17]byte var z6318 [1 << 17]byte var z6319 [1 << 17]byte var z6320 [1 << 17]byte var z6321 [1 << 17]byte var z6322 [1 << 17]byte var z6323 [1 << 17]byte var z6324 [1 << 17]byte var z6325 [1 << 17]byte var z6326 [1 << 17]byte var z6327 [1 << 17]byte var z6328 [1 << 17]byte var z6329 [1 << 17]byte var z6330 [1 << 17]byte var z6331 [1 << 17]byte var z6332 [1 << 17]byte var z6333 [1 << 17]byte var z6334 [1 << 17]byte var z6335 [1 << 17]byte var z6336 [1 << 17]byte var z6337 [1 << 17]byte var z6338 [1 << 17]byte var z6339 [1 << 17]byte var z6340 [1 << 17]byte var z6341 [1 << 17]byte var z6342 [1 << 17]byte var z6343 [1 << 17]byte var z6344 [1 << 17]byte var z6345 [1 << 17]byte var z6346 [1 << 17]byte var z6347 [1 << 17]byte var z6348 [1 << 17]byte var z6349 [1 << 17]byte var z6350 [1 << 17]byte var z6351 [1 << 17]byte var z6352 [1 << 17]byte var z6353 [1 << 17]byte var z6354 [1 << 17]byte var z6355 [1 << 17]byte var z6356 [1 << 17]byte var z6357 [1 << 17]byte var z6358 [1 << 17]byte var z6359 [1 << 17]byte var z6360 [1 << 17]byte var z6361 [1 << 17]byte var z6362 [1 << 17]byte var z6363 [1 << 17]byte var z6364 [1 << 17]byte var z6365 [1 << 17]byte var z6366 [1 << 17]byte var z6367 [1 << 17]byte var z6368 [1 << 17]byte var z6369 [1 << 17]byte var z6370 [1 << 17]byte var z6371 [1 << 17]byte var z6372 [1 << 17]byte var z6373 [1 << 17]byte var z6374 [1 << 17]byte var z6375 [1 << 17]byte var z6376 [1 << 17]byte var z6377 [1 << 17]byte var z6378 [1 << 17]byte var z6379 [1 << 17]byte var z6380 [1 << 17]byte var z6381 [1 << 17]byte var z6382 [1 << 17]byte var z6383 [1 << 17]byte var z6384 [1 << 17]byte var z6385 [1 << 17]byte var z6386 [1 << 17]byte var z6387 [1 << 17]byte var z6388 [1 << 17]byte var z6389 [1 << 17]byte var z6390 [1 << 17]byte var z6391 [1 << 17]byte var z6392 [1 << 17]byte var z6393 [1 << 17]byte var z6394 [1 << 17]byte var z6395 [1 << 17]byte var z6396 [1 << 17]byte var z6397 [1 << 17]byte var z6398 [1 << 17]byte var z6399 [1 << 17]byte var z6400 [1 << 17]byte var z6401 [1 << 17]byte var z6402 [1 << 17]byte var z6403 [1 << 17]byte var z6404 [1 << 17]byte var z6405 [1 << 17]byte var z6406 [1 << 17]byte var z6407 [1 << 17]byte var z6408 [1 << 17]byte var z6409 [1 << 17]byte var z6410 [1 << 17]byte var z6411 [1 << 17]byte var z6412 [1 << 17]byte var z6413 [1 << 17]byte var z6414 [1 << 17]byte var z6415 [1 << 17]byte var z6416 [1 << 17]byte var z6417 [1 << 17]byte var z6418 [1 << 17]byte var z6419 [1 << 17]byte var z6420 [1 << 17]byte var z6421 [1 << 17]byte var z6422 [1 << 17]byte var z6423 [1 << 17]byte var z6424 [1 << 17]byte var z6425 [1 << 17]byte var z6426 [1 << 17]byte var z6427 [1 << 17]byte var z6428 [1 << 17]byte var z6429 [1 << 17]byte var z6430 [1 << 17]byte var z6431 [1 << 17]byte var z6432 [1 << 17]byte var z6433 [1 << 17]byte var z6434 [1 << 17]byte var z6435 [1 << 17]byte var z6436 [1 << 17]byte var z6437 [1 << 17]byte var z6438 [1 << 17]byte var z6439 [1 << 17]byte var z6440 [1 << 17]byte var z6441 [1 << 17]byte var z6442 [1 << 17]byte var z6443 [1 << 17]byte var z6444 [1 << 17]byte var z6445 [1 << 17]byte var z6446 [1 << 17]byte var z6447 [1 << 17]byte var z6448 [1 << 17]byte var z6449 [1 << 17]byte var z6450 [1 << 17]byte var z6451 [1 << 17]byte var z6452 [1 << 17]byte var z6453 [1 << 17]byte var z6454 [1 << 17]byte var z6455 [1 << 17]byte var z6456 [1 << 17]byte var z6457 [1 << 17]byte var z6458 [1 << 17]byte var z6459 [1 << 17]byte var z6460 [1 << 17]byte var z6461 [1 << 17]byte var z6462 [1 << 17]byte var z6463 [1 << 17]byte var z6464 [1 << 17]byte var z6465 [1 << 17]byte var z6466 [1 << 17]byte var z6467 [1 << 17]byte var z6468 [1 << 17]byte var z6469 [1 << 17]byte var z6470 [1 << 17]byte var z6471 [1 << 17]byte var z6472 [1 << 17]byte var z6473 [1 << 17]byte var z6474 [1 << 17]byte var z6475 [1 << 17]byte var z6476 [1 << 17]byte var z6477 [1 << 17]byte var z6478 [1 << 17]byte var z6479 [1 << 17]byte var z6480 [1 << 17]byte var z6481 [1 << 17]byte var z6482 [1 << 17]byte var z6483 [1 << 17]byte var z6484 [1 << 17]byte var z6485 [1 << 17]byte var z6486 [1 << 17]byte var z6487 [1 << 17]byte var z6488 [1 << 17]byte var z6489 [1 << 17]byte var z6490 [1 << 17]byte var z6491 [1 << 17]byte var z6492 [1 << 17]byte var z6493 [1 << 17]byte var z6494 [1 << 17]byte var z6495 [1 << 17]byte var z6496 [1 << 17]byte var z6497 [1 << 17]byte var z6498 [1 << 17]byte var z6499 [1 << 17]byte var z6500 [1 << 17]byte var z6501 [1 << 17]byte var z6502 [1 << 17]byte var z6503 [1 << 17]byte var z6504 [1 << 17]byte var z6505 [1 << 17]byte var z6506 [1 << 17]byte var z6507 [1 << 17]byte var z6508 [1 << 17]byte var z6509 [1 << 17]byte var z6510 [1 << 17]byte var z6511 [1 << 17]byte var z6512 [1 << 17]byte var z6513 [1 << 17]byte var z6514 [1 << 17]byte var z6515 [1 << 17]byte var z6516 [1 << 17]byte var z6517 [1 << 17]byte var z6518 [1 << 17]byte var z6519 [1 << 17]byte var z6520 [1 << 17]byte var z6521 [1 << 17]byte var z6522 [1 << 17]byte var z6523 [1 << 17]byte var z6524 [1 << 17]byte var z6525 [1 << 17]byte var z6526 [1 << 17]byte var z6527 [1 << 17]byte var z6528 [1 << 17]byte var z6529 [1 << 17]byte var z6530 [1 << 17]byte var z6531 [1 << 17]byte var z6532 [1 << 17]byte var z6533 [1 << 17]byte var z6534 [1 << 17]byte var z6535 [1 << 17]byte var z6536 [1 << 17]byte var z6537 [1 << 17]byte var z6538 [1 << 17]byte var z6539 [1 << 17]byte var z6540 [1 << 17]byte var z6541 [1 << 17]byte var z6542 [1 << 17]byte var z6543 [1 << 17]byte var z6544 [1 << 17]byte var z6545 [1 << 17]byte var z6546 [1 << 17]byte var z6547 [1 << 17]byte var z6548 [1 << 17]byte var z6549 [1 << 17]byte var z6550 [1 << 17]byte var z6551 [1 << 17]byte var z6552 [1 << 17]byte var z6553 [1 << 17]byte var z6554 [1 << 17]byte var z6555 [1 << 17]byte var z6556 [1 << 17]byte var z6557 [1 << 17]byte var z6558 [1 << 17]byte var z6559 [1 << 17]byte var z6560 [1 << 17]byte var z6561 [1 << 17]byte var z6562 [1 << 17]byte var z6563 [1 << 17]byte var z6564 [1 << 17]byte var z6565 [1 << 17]byte var z6566 [1 << 17]byte var z6567 [1 << 17]byte var z6568 [1 << 17]byte var z6569 [1 << 17]byte var z6570 [1 << 17]byte var z6571 [1 << 17]byte var z6572 [1 << 17]byte var z6573 [1 << 17]byte var z6574 [1 << 17]byte var z6575 [1 << 17]byte var z6576 [1 << 17]byte var z6577 [1 << 17]byte var z6578 [1 << 17]byte var z6579 [1 << 17]byte var z6580 [1 << 17]byte var z6581 [1 << 17]byte var z6582 [1 << 17]byte var z6583 [1 << 17]byte var z6584 [1 << 17]byte var z6585 [1 << 17]byte var z6586 [1 << 17]byte var z6587 [1 << 17]byte var z6588 [1 << 17]byte var z6589 [1 << 17]byte var z6590 [1 << 17]byte var z6591 [1 << 17]byte var z6592 [1 << 17]byte var z6593 [1 << 17]byte var z6594 [1 << 17]byte var z6595 [1 << 17]byte var z6596 [1 << 17]byte var z6597 [1 << 17]byte var z6598 [1 << 17]byte var z6599 [1 << 17]byte var z6600 [1 << 17]byte var z6601 [1 << 17]byte var z6602 [1 << 17]byte var z6603 [1 << 17]byte var z6604 [1 << 17]byte var z6605 [1 << 17]byte var z6606 [1 << 17]byte var z6607 [1 << 17]byte var z6608 [1 << 17]byte var z6609 [1 << 17]byte var z6610 [1 << 17]byte var z6611 [1 << 17]byte var z6612 [1 << 17]byte var z6613 [1 << 17]byte var z6614 [1 << 17]byte var z6615 [1 << 17]byte var z6616 [1 << 17]byte var z6617 [1 << 17]byte var z6618 [1 << 17]byte var z6619 [1 << 17]byte var z6620 [1 << 17]byte var z6621 [1 << 17]byte var z6622 [1 << 17]byte var z6623 [1 << 17]byte var z6624 [1 << 17]byte var z6625 [1 << 17]byte var z6626 [1 << 17]byte var z6627 [1 << 17]byte var z6628 [1 << 17]byte var z6629 [1 << 17]byte var z6630 [1 << 17]byte var z6631 [1 << 17]byte var z6632 [1 << 17]byte var z6633 [1 << 17]byte var z6634 [1 << 17]byte var z6635 [1 << 17]byte var z6636 [1 << 17]byte var z6637 [1 << 17]byte var z6638 [1 << 17]byte var z6639 [1 << 17]byte var z6640 [1 << 17]byte var z6641 [1 << 17]byte var z6642 [1 << 17]byte var z6643 [1 << 17]byte var z6644 [1 << 17]byte var z6645 [1 << 17]byte var z6646 [1 << 17]byte var z6647 [1 << 17]byte var z6648 [1 << 17]byte var z6649 [1 << 17]byte var z6650 [1 << 17]byte var z6651 [1 << 17]byte var z6652 [1 << 17]byte var z6653 [1 << 17]byte var z6654 [1 << 17]byte var z6655 [1 << 17]byte var z6656 [1 << 17]byte var z6657 [1 << 17]byte var z6658 [1 << 17]byte var z6659 [1 << 17]byte var z6660 [1 << 17]byte var z6661 [1 << 17]byte var z6662 [1 << 17]byte var z6663 [1 << 17]byte var z6664 [1 << 17]byte var z6665 [1 << 17]byte var z6666 [1 << 17]byte var z6667 [1 << 17]byte var z6668 [1 << 17]byte var z6669 [1 << 17]byte var z6670 [1 << 17]byte var z6671 [1 << 17]byte var z6672 [1 << 17]byte var z6673 [1 << 17]byte var z6674 [1 << 17]byte var z6675 [1 << 17]byte var z6676 [1 << 17]byte var z6677 [1 << 17]byte var z6678 [1 << 17]byte var z6679 [1 << 17]byte var z6680 [1 << 17]byte var z6681 [1 << 17]byte var z6682 [1 << 17]byte var z6683 [1 << 17]byte var z6684 [1 << 17]byte var z6685 [1 << 17]byte var z6686 [1 << 17]byte var z6687 [1 << 17]byte var z6688 [1 << 17]byte var z6689 [1 << 17]byte var z6690 [1 << 17]byte var z6691 [1 << 17]byte var z6692 [1 << 17]byte var z6693 [1 << 17]byte var z6694 [1 << 17]byte var z6695 [1 << 17]byte var z6696 [1 << 17]byte var z6697 [1 << 17]byte var z6698 [1 << 17]byte var z6699 [1 << 17]byte var z6700 [1 << 17]byte var z6701 [1 << 17]byte var z6702 [1 << 17]byte var z6703 [1 << 17]byte var z6704 [1 << 17]byte var z6705 [1 << 17]byte var z6706 [1 << 17]byte var z6707 [1 << 17]byte var z6708 [1 << 17]byte var z6709 [1 << 17]byte var z6710 [1 << 17]byte var z6711 [1 << 17]byte var z6712 [1 << 17]byte var z6713 [1 << 17]byte var z6714 [1 << 17]byte var z6715 [1 << 17]byte var z6716 [1 << 17]byte var z6717 [1 << 17]byte var z6718 [1 << 17]byte var z6719 [1 << 17]byte var z6720 [1 << 17]byte var z6721 [1 << 17]byte var z6722 [1 << 17]byte var z6723 [1 << 17]byte var z6724 [1 << 17]byte var z6725 [1 << 17]byte var z6726 [1 << 17]byte var z6727 [1 << 17]byte var z6728 [1 << 17]byte var z6729 [1 << 17]byte var z6730 [1 << 17]byte var z6731 [1 << 17]byte var z6732 [1 << 17]byte var z6733 [1 << 17]byte var z6734 [1 << 17]byte var z6735 [1 << 17]byte var z6736 [1 << 17]byte var z6737 [1 << 17]byte var z6738 [1 << 17]byte var z6739 [1 << 17]byte var z6740 [1 << 17]byte var z6741 [1 << 17]byte var z6742 [1 << 17]byte var z6743 [1 << 17]byte var z6744 [1 << 17]byte var z6745 [1 << 17]byte var z6746 [1 << 17]byte var z6747 [1 << 17]byte var z6748 [1 << 17]byte var z6749 [1 << 17]byte var z6750 [1 << 17]byte var z6751 [1 << 17]byte var z6752 [1 << 17]byte var z6753 [1 << 17]byte var z6754 [1 << 17]byte var z6755 [1 << 17]byte var z6756 [1 << 17]byte var z6757 [1 << 17]byte var z6758 [1 << 17]byte var z6759 [1 << 17]byte var z6760 [1 << 17]byte var z6761 [1 << 17]byte var z6762 [1 << 17]byte var z6763 [1 << 17]byte var z6764 [1 << 17]byte var z6765 [1 << 17]byte var z6766 [1 << 17]byte var z6767 [1 << 17]byte var z6768 [1 << 17]byte var z6769 [1 << 17]byte var z6770 [1 << 17]byte var z6771 [1 << 17]byte var z6772 [1 << 17]byte var z6773 [1 << 17]byte var z6774 [1 << 17]byte var z6775 [1 << 17]byte var z6776 [1 << 17]byte var z6777 [1 << 17]byte var z6778 [1 << 17]byte var z6779 [1 << 17]byte var z6780 [1 << 17]byte var z6781 [1 << 17]byte var z6782 [1 << 17]byte var z6783 [1 << 17]byte var z6784 [1 << 17]byte var z6785 [1 << 17]byte var z6786 [1 << 17]byte var z6787 [1 << 17]byte var z6788 [1 << 17]byte var z6789 [1 << 17]byte var z6790 [1 << 17]byte var z6791 [1 << 17]byte var z6792 [1 << 17]byte var z6793 [1 << 17]byte var z6794 [1 << 17]byte var z6795 [1 << 17]byte var z6796 [1 << 17]byte var z6797 [1 << 17]byte var z6798 [1 << 17]byte var z6799 [1 << 17]byte var z6800 [1 << 17]byte var z6801 [1 << 17]byte var z6802 [1 << 17]byte var z6803 [1 << 17]byte var z6804 [1 << 17]byte var z6805 [1 << 17]byte var z6806 [1 << 17]byte var z6807 [1 << 17]byte var z6808 [1 << 17]byte var z6809 [1 << 17]byte var z6810 [1 << 17]byte var z6811 [1 << 17]byte var z6812 [1 << 17]byte var z6813 [1 << 17]byte var z6814 [1 << 17]byte var z6815 [1 << 17]byte var z6816 [1 << 17]byte var z6817 [1 << 17]byte var z6818 [1 << 17]byte var z6819 [1 << 17]byte var z6820 [1 << 17]byte var z6821 [1 << 17]byte var z6822 [1 << 17]byte var z6823 [1 << 17]byte var z6824 [1 << 17]byte var z6825 [1 << 17]byte var z6826 [1 << 17]byte var z6827 [1 << 17]byte var z6828 [1 << 17]byte var z6829 [1 << 17]byte var z6830 [1 << 17]byte var z6831 [1 << 17]byte var z6832 [1 << 17]byte var z6833 [1 << 17]byte var z6834 [1 << 17]byte var z6835 [1 << 17]byte var z6836 [1 << 17]byte var z6837 [1 << 17]byte var z6838 [1 << 17]byte var z6839 [1 << 17]byte var z6840 [1 << 17]byte var z6841 [1 << 17]byte var z6842 [1 << 17]byte var z6843 [1 << 17]byte var z6844 [1 << 17]byte var z6845 [1 << 17]byte var z6846 [1 << 17]byte var z6847 [1 << 17]byte var z6848 [1 << 17]byte var z6849 [1 << 17]byte var z6850 [1 << 17]byte var z6851 [1 << 17]byte var z6852 [1 << 17]byte var z6853 [1 << 17]byte var z6854 [1 << 17]byte var z6855 [1 << 17]byte var z6856 [1 << 17]byte var z6857 [1 << 17]byte var z6858 [1 << 17]byte var z6859 [1 << 17]byte var z6860 [1 << 17]byte var z6861 [1 << 17]byte var z6862 [1 << 17]byte var z6863 [1 << 17]byte var z6864 [1 << 17]byte var z6865 [1 << 17]byte var z6866 [1 << 17]byte var z6867 [1 << 17]byte var z6868 [1 << 17]byte var z6869 [1 << 17]byte var z6870 [1 << 17]byte var z6871 [1 << 17]byte var z6872 [1 << 17]byte var z6873 [1 << 17]byte var z6874 [1 << 17]byte var z6875 [1 << 17]byte var z6876 [1 << 17]byte var z6877 [1 << 17]byte var z6878 [1 << 17]byte var z6879 [1 << 17]byte var z6880 [1 << 17]byte var z6881 [1 << 17]byte var z6882 [1 << 17]byte var z6883 [1 << 17]byte var z6884 [1 << 17]byte var z6885 [1 << 17]byte var z6886 [1 << 17]byte var z6887 [1 << 17]byte var z6888 [1 << 17]byte var z6889 [1 << 17]byte var z6890 [1 << 17]byte var z6891 [1 << 17]byte var z6892 [1 << 17]byte var z6893 [1 << 17]byte var z6894 [1 << 17]byte var z6895 [1 << 17]byte var z6896 [1 << 17]byte var z6897 [1 << 17]byte var z6898 [1 << 17]byte var z6899 [1 << 17]byte var z6900 [1 << 17]byte var z6901 [1 << 17]byte var z6902 [1 << 17]byte var z6903 [1 << 17]byte var z6904 [1 << 17]byte var z6905 [1 << 17]byte var z6906 [1 << 17]byte var z6907 [1 << 17]byte var z6908 [1 << 17]byte var z6909 [1 << 17]byte var z6910 [1 << 17]byte var z6911 [1 << 17]byte var z6912 [1 << 17]byte var z6913 [1 << 17]byte var z6914 [1 << 17]byte var z6915 [1 << 17]byte var z6916 [1 << 17]byte var z6917 [1 << 17]byte var z6918 [1 << 17]byte var z6919 [1 << 17]byte var z6920 [1 << 17]byte var z6921 [1 << 17]byte var z6922 [1 << 17]byte var z6923 [1 << 17]byte var z6924 [1 << 17]byte var z6925 [1 << 17]byte var z6926 [1 << 17]byte var z6927 [1 << 17]byte var z6928 [1 << 17]byte var z6929 [1 << 17]byte var z6930 [1 << 17]byte var z6931 [1 << 17]byte var z6932 [1 << 17]byte var z6933 [1 << 17]byte var z6934 [1 << 17]byte var z6935 [1 << 17]byte var z6936 [1 << 17]byte var z6937 [1 << 17]byte var z6938 [1 << 17]byte var z6939 [1 << 17]byte var z6940 [1 << 17]byte var z6941 [1 << 17]byte var z6942 [1 << 17]byte var z6943 [1 << 17]byte var z6944 [1 << 17]byte var z6945 [1 << 17]byte var z6946 [1 << 17]byte var z6947 [1 << 17]byte var z6948 [1 << 17]byte var z6949 [1 << 17]byte var z6950 [1 << 17]byte var z6951 [1 << 17]byte var z6952 [1 << 17]byte var z6953 [1 << 17]byte var z6954 [1 << 17]byte var z6955 [1 << 17]byte var z6956 [1 << 17]byte var z6957 [1 << 17]byte var z6958 [1 << 17]byte var z6959 [1 << 17]byte var z6960 [1 << 17]byte var z6961 [1 << 17]byte var z6962 [1 << 17]byte var z6963 [1 << 17]byte var z6964 [1 << 17]byte var z6965 [1 << 17]byte var z6966 [1 << 17]byte var z6967 [1 << 17]byte var z6968 [1 << 17]byte var z6969 [1 << 17]byte var z6970 [1 << 17]byte var z6971 [1 << 17]byte var z6972 [1 << 17]byte var z6973 [1 << 17]byte var z6974 [1 << 17]byte var z6975 [1 << 17]byte var z6976 [1 << 17]byte var z6977 [1 << 17]byte var z6978 [1 << 17]byte var z6979 [1 << 17]byte var z6980 [1 << 17]byte var z6981 [1 << 17]byte var z6982 [1 << 17]byte var z6983 [1 << 17]byte var z6984 [1 << 17]byte var z6985 [1 << 17]byte var z6986 [1 << 17]byte var z6987 [1 << 17]byte var z6988 [1 << 17]byte var z6989 [1 << 17]byte var z6990 [1 << 17]byte var z6991 [1 << 17]byte var z6992 [1 << 17]byte var z6993 [1 << 17]byte var z6994 [1 << 17]byte var z6995 [1 << 17]byte var z6996 [1 << 17]byte var z6997 [1 << 17]byte var z6998 [1 << 17]byte var z6999 [1 << 17]byte var z7000 [1 << 17]byte var z7001 [1 << 17]byte var z7002 [1 << 17]byte var z7003 [1 << 17]byte var z7004 [1 << 17]byte var z7005 [1 << 17]byte var z7006 [1 << 17]byte var z7007 [1 << 17]byte var z7008 [1 << 17]byte var z7009 [1 << 17]byte var z7010 [1 << 17]byte var z7011 [1 << 17]byte var z7012 [1 << 17]byte var z7013 [1 << 17]byte var z7014 [1 << 17]byte var z7015 [1 << 17]byte var z7016 [1 << 17]byte var z7017 [1 << 17]byte var z7018 [1 << 17]byte var z7019 [1 << 17]byte var z7020 [1 << 17]byte var z7021 [1 << 17]byte var z7022 [1 << 17]byte var z7023 [1 << 17]byte var z7024 [1 << 17]byte var z7025 [1 << 17]byte var z7026 [1 << 17]byte var z7027 [1 << 17]byte var z7028 [1 << 17]byte var z7029 [1 << 17]byte var z7030 [1 << 17]byte var z7031 [1 << 17]byte var z7032 [1 << 17]byte var z7033 [1 << 17]byte var z7034 [1 << 17]byte var z7035 [1 << 17]byte var z7036 [1 << 17]byte var z7037 [1 << 17]byte var z7038 [1 << 17]byte var z7039 [1 << 17]byte var z7040 [1 << 17]byte var z7041 [1 << 17]byte var z7042 [1 << 17]byte var z7043 [1 << 17]byte var z7044 [1 << 17]byte var z7045 [1 << 17]byte var z7046 [1 << 17]byte var z7047 [1 << 17]byte var z7048 [1 << 17]byte var z7049 [1 << 17]byte var z7050 [1 << 17]byte var z7051 [1 << 17]byte var z7052 [1 << 17]byte var z7053 [1 << 17]byte var z7054 [1 << 17]byte var z7055 [1 << 17]byte var z7056 [1 << 17]byte var z7057 [1 << 17]byte var z7058 [1 << 17]byte var z7059 [1 << 17]byte var z7060 [1 << 17]byte var z7061 [1 << 17]byte var z7062 [1 << 17]byte var z7063 [1 << 17]byte var z7064 [1 << 17]byte var z7065 [1 << 17]byte var z7066 [1 << 17]byte var z7067 [1 << 17]byte var z7068 [1 << 17]byte var z7069 [1 << 17]byte var z7070 [1 << 17]byte var z7071 [1 << 17]byte var z7072 [1 << 17]byte var z7073 [1 << 17]byte var z7074 [1 << 17]byte var z7075 [1 << 17]byte var z7076 [1 << 17]byte var z7077 [1 << 17]byte var z7078 [1 << 17]byte var z7079 [1 << 17]byte var z7080 [1 << 17]byte var z7081 [1 << 17]byte var z7082 [1 << 17]byte var z7083 [1 << 17]byte var z7084 [1 << 17]byte var z7085 [1 << 17]byte var z7086 [1 << 17]byte var z7087 [1 << 17]byte var z7088 [1 << 17]byte var z7089 [1 << 17]byte var z7090 [1 << 17]byte var z7091 [1 << 17]byte var z7092 [1 << 17]byte var z7093 [1 << 17]byte var z7094 [1 << 17]byte var z7095 [1 << 17]byte var z7096 [1 << 17]byte var z7097 [1 << 17]byte var z7098 [1 << 17]byte var z7099 [1 << 17]byte var z7100 [1 << 17]byte var z7101 [1 << 17]byte var z7102 [1 << 17]byte var z7103 [1 << 17]byte var z7104 [1 << 17]byte var z7105 [1 << 17]byte var z7106 [1 << 17]byte var z7107 [1 << 17]byte var z7108 [1 << 17]byte var z7109 [1 << 17]byte var z7110 [1 << 17]byte var z7111 [1 << 17]byte var z7112 [1 << 17]byte var z7113 [1 << 17]byte var z7114 [1 << 17]byte var z7115 [1 << 17]byte var z7116 [1 << 17]byte var z7117 [1 << 17]byte var z7118 [1 << 17]byte var z7119 [1 << 17]byte var z7120 [1 << 17]byte var z7121 [1 << 17]byte var z7122 [1 << 17]byte var z7123 [1 << 17]byte var z7124 [1 << 17]byte var z7125 [1 << 17]byte var z7126 [1 << 17]byte var z7127 [1 << 17]byte var z7128 [1 << 17]byte var z7129 [1 << 17]byte var z7130 [1 << 17]byte var z7131 [1 << 17]byte var z7132 [1 << 17]byte var z7133 [1 << 17]byte var z7134 [1 << 17]byte var z7135 [1 << 17]byte var z7136 [1 << 17]byte var z7137 [1 << 17]byte var z7138 [1 << 17]byte var z7139 [1 << 17]byte var z7140 [1 << 17]byte var z7141 [1 << 17]byte var z7142 [1 << 17]byte var z7143 [1 << 17]byte var z7144 [1 << 17]byte var z7145 [1 << 17]byte var z7146 [1 << 17]byte var z7147 [1 << 17]byte var z7148 [1 << 17]byte var z7149 [1 << 17]byte var z7150 [1 << 17]byte var z7151 [1 << 17]byte var z7152 [1 << 17]byte var z7153 [1 << 17]byte var z7154 [1 << 17]byte var z7155 [1 << 17]byte var z7156 [1 << 17]byte var z7157 [1 << 17]byte var z7158 [1 << 17]byte var z7159 [1 << 17]byte var z7160 [1 << 17]byte var z7161 [1 << 17]byte var z7162 [1 << 17]byte var z7163 [1 << 17]byte var z7164 [1 << 17]byte var z7165 [1 << 17]byte var z7166 [1 << 17]byte var z7167 [1 << 17]byte var z7168 [1 << 17]byte var z7169 [1 << 17]byte var z7170 [1 << 17]byte var z7171 [1 << 17]byte var z7172 [1 << 17]byte var z7173 [1 << 17]byte var z7174 [1 << 17]byte var z7175 [1 << 17]byte var z7176 [1 << 17]byte var z7177 [1 << 17]byte var z7178 [1 << 17]byte var z7179 [1 << 17]byte var z7180 [1 << 17]byte var z7181 [1 << 17]byte var z7182 [1 << 17]byte var z7183 [1 << 17]byte var z7184 [1 << 17]byte var z7185 [1 << 17]byte var z7186 [1 << 17]byte var z7187 [1 << 17]byte var z7188 [1 << 17]byte var z7189 [1 << 17]byte var z7190 [1 << 17]byte var z7191 [1 << 17]byte var z7192 [1 << 17]byte var z7193 [1 << 17]byte var z7194 [1 << 17]byte var z7195 [1 << 17]byte var z7196 [1 << 17]byte var z7197 [1 << 17]byte var z7198 [1 << 17]byte var z7199 [1 << 17]byte var z7200 [1 << 17]byte var z7201 [1 << 17]byte var z7202 [1 << 17]byte var z7203 [1 << 17]byte var z7204 [1 << 17]byte var z7205 [1 << 17]byte var z7206 [1 << 17]byte var z7207 [1 << 17]byte var z7208 [1 << 17]byte var z7209 [1 << 17]byte var z7210 [1 << 17]byte var z7211 [1 << 17]byte var z7212 [1 << 17]byte var z7213 [1 << 17]byte var z7214 [1 << 17]byte var z7215 [1 << 17]byte var z7216 [1 << 17]byte var z7217 [1 << 17]byte var z7218 [1 << 17]byte var z7219 [1 << 17]byte var z7220 [1 << 17]byte var z7221 [1 << 17]byte var z7222 [1 << 17]byte var z7223 [1 << 17]byte var z7224 [1 << 17]byte var z7225 [1 << 17]byte var z7226 [1 << 17]byte var z7227 [1 << 17]byte var z7228 [1 << 17]byte var z7229 [1 << 17]byte var z7230 [1 << 17]byte var z7231 [1 << 17]byte var z7232 [1 << 17]byte var z7233 [1 << 17]byte var z7234 [1 << 17]byte var z7235 [1 << 17]byte var z7236 [1 << 17]byte var z7237 [1 << 17]byte var z7238 [1 << 17]byte var z7239 [1 << 17]byte var z7240 [1 << 17]byte var z7241 [1 << 17]byte var z7242 [1 << 17]byte var z7243 [1 << 17]byte var z7244 [1 << 17]byte var z7245 [1 << 17]byte var z7246 [1 << 17]byte var z7247 [1 << 17]byte var z7248 [1 << 17]byte var z7249 [1 << 17]byte var z7250 [1 << 17]byte var z7251 [1 << 17]byte var z7252 [1 << 17]byte var z7253 [1 << 17]byte var z7254 [1 << 17]byte var z7255 [1 << 17]byte var z7256 [1 << 17]byte var z7257 [1 << 17]byte var z7258 [1 << 17]byte var z7259 [1 << 17]byte var z7260 [1 << 17]byte var z7261 [1 << 17]byte var z7262 [1 << 17]byte var z7263 [1 << 17]byte var z7264 [1 << 17]byte var z7265 [1 << 17]byte var z7266 [1 << 17]byte var z7267 [1 << 17]byte var z7268 [1 << 17]byte var z7269 [1 << 17]byte var z7270 [1 << 17]byte var z7271 [1 << 17]byte var z7272 [1 << 17]byte var z7273 [1 << 17]byte var z7274 [1 << 17]byte var z7275 [1 << 17]byte var z7276 [1 << 17]byte var z7277 [1 << 17]byte var z7278 [1 << 17]byte var z7279 [1 << 17]byte var z7280 [1 << 17]byte var z7281 [1 << 17]byte var z7282 [1 << 17]byte var z7283 [1 << 17]byte var z7284 [1 << 17]byte var z7285 [1 << 17]byte var z7286 [1 << 17]byte var z7287 [1 << 17]byte var z7288 [1 << 17]byte var z7289 [1 << 17]byte var z7290 [1 << 17]byte var z7291 [1 << 17]byte var z7292 [1 << 17]byte var z7293 [1 << 17]byte var z7294 [1 << 17]byte var z7295 [1 << 17]byte var z7296 [1 << 17]byte var z7297 [1 << 17]byte var z7298 [1 << 17]byte var z7299 [1 << 17]byte var z7300 [1 << 17]byte var z7301 [1 << 17]byte var z7302 [1 << 17]byte var z7303 [1 << 17]byte var z7304 [1 << 17]byte var z7305 [1 << 17]byte var z7306 [1 << 17]byte var z7307 [1 << 17]byte var z7308 [1 << 17]byte var z7309 [1 << 17]byte var z7310 [1 << 17]byte var z7311 [1 << 17]byte var z7312 [1 << 17]byte var z7313 [1 << 17]byte var z7314 [1 << 17]byte var z7315 [1 << 17]byte var z7316 [1 << 17]byte var z7317 [1 << 17]byte var z7318 [1 << 17]byte var z7319 [1 << 17]byte var z7320 [1 << 17]byte var z7321 [1 << 17]byte var z7322 [1 << 17]byte var z7323 [1 << 17]byte var z7324 [1 << 17]byte var z7325 [1 << 17]byte var z7326 [1 << 17]byte var z7327 [1 << 17]byte var z7328 [1 << 17]byte var z7329 [1 << 17]byte var z7330 [1 << 17]byte var z7331 [1 << 17]byte var z7332 [1 << 17]byte var z7333 [1 << 17]byte var z7334 [1 << 17]byte var z7335 [1 << 17]byte var z7336 [1 << 17]byte var z7337 [1 << 17]byte var z7338 [1 << 17]byte var z7339 [1 << 17]byte var z7340 [1 << 17]byte var z7341 [1 << 17]byte var z7342 [1 << 17]byte var z7343 [1 << 17]byte var z7344 [1 << 17]byte var z7345 [1 << 17]byte var z7346 [1 << 17]byte var z7347 [1 << 17]byte var z7348 [1 << 17]byte var z7349 [1 << 17]byte var z7350 [1 << 17]byte var z7351 [1 << 17]byte var z7352 [1 << 17]byte var z7353 [1 << 17]byte var z7354 [1 << 17]byte var z7355 [1 << 17]byte var z7356 [1 << 17]byte var z7357 [1 << 17]byte var z7358 [1 << 17]byte var z7359 [1 << 17]byte var z7360 [1 << 17]byte var z7361 [1 << 17]byte var z7362 [1 << 17]byte var z7363 [1 << 17]byte var z7364 [1 << 17]byte var z7365 [1 << 17]byte var z7366 [1 << 17]byte var z7367 [1 << 17]byte var z7368 [1 << 17]byte var z7369 [1 << 17]byte var z7370 [1 << 17]byte var z7371 [1 << 17]byte var z7372 [1 << 17]byte var z7373 [1 << 17]byte var z7374 [1 << 17]byte var z7375 [1 << 17]byte var z7376 [1 << 17]byte var z7377 [1 << 17]byte var z7378 [1 << 17]byte var z7379 [1 << 17]byte var z7380 [1 << 17]byte var z7381 [1 << 17]byte var z7382 [1 << 17]byte var z7383 [1 << 17]byte var z7384 [1 << 17]byte var z7385 [1 << 17]byte var z7386 [1 << 17]byte var z7387 [1 << 17]byte var z7388 [1 << 17]byte var z7389 [1 << 17]byte var z7390 [1 << 17]byte var z7391 [1 << 17]byte var z7392 [1 << 17]byte var z7393 [1 << 17]byte var z7394 [1 << 17]byte var z7395 [1 << 17]byte var z7396 [1 << 17]byte var z7397 [1 << 17]byte var z7398 [1 << 17]byte var z7399 [1 << 17]byte var z7400 [1 << 17]byte var z7401 [1 << 17]byte var z7402 [1 << 17]byte var z7403 [1 << 17]byte var z7404 [1 << 17]byte var z7405 [1 << 17]byte var z7406 [1 << 17]byte var z7407 [1 << 17]byte var z7408 [1 << 17]byte var z7409 [1 << 17]byte var z7410 [1 << 17]byte var z7411 [1 << 17]byte var z7412 [1 << 17]byte var z7413 [1 << 17]byte var z7414 [1 << 17]byte var z7415 [1 << 17]byte var z7416 [1 << 17]byte var z7417 [1 << 17]byte var z7418 [1 << 17]byte var z7419 [1 << 17]byte var z7420 [1 << 17]byte var z7421 [1 << 17]byte var z7422 [1 << 17]byte var z7423 [1 << 17]byte var z7424 [1 << 17]byte var z7425 [1 << 17]byte var z7426 [1 << 17]byte var z7427 [1 << 17]byte var z7428 [1 << 17]byte var z7429 [1 << 17]byte var z7430 [1 << 17]byte var z7431 [1 << 17]byte var z7432 [1 << 17]byte var z7433 [1 << 17]byte var z7434 [1 << 17]byte var z7435 [1 << 17]byte var z7436 [1 << 17]byte var z7437 [1 << 17]byte var z7438 [1 << 17]byte var z7439 [1 << 17]byte var z7440 [1 << 17]byte var z7441 [1 << 17]byte var z7442 [1 << 17]byte var z7443 [1 << 17]byte var z7444 [1 << 17]byte var z7445 [1 << 17]byte var z7446 [1 << 17]byte var z7447 [1 << 17]byte var z7448 [1 << 17]byte var z7449 [1 << 17]byte var z7450 [1 << 17]byte var z7451 [1 << 17]byte var z7452 [1 << 17]byte var z7453 [1 << 17]byte var z7454 [1 << 17]byte var z7455 [1 << 17]byte var z7456 [1 << 17]byte var z7457 [1 << 17]byte var z7458 [1 << 17]byte var z7459 [1 << 17]byte var z7460 [1 << 17]byte var z7461 [1 << 17]byte var z7462 [1 << 17]byte var z7463 [1 << 17]byte var z7464 [1 << 17]byte var z7465 [1 << 17]byte var z7466 [1 << 17]byte var z7467 [1 << 17]byte var z7468 [1 << 17]byte var z7469 [1 << 17]byte var z7470 [1 << 17]byte var z7471 [1 << 17]byte var z7472 [1 << 17]byte var z7473 [1 << 17]byte var z7474 [1 << 17]byte var z7475 [1 << 17]byte var z7476 [1 << 17]byte var z7477 [1 << 17]byte var z7478 [1 << 17]byte var z7479 [1 << 17]byte var z7480 [1 << 17]byte var z7481 [1 << 17]byte var z7482 [1 << 17]byte var z7483 [1 << 17]byte var z7484 [1 << 17]byte var z7485 [1 << 17]byte var z7486 [1 << 17]byte var z7487 [1 << 17]byte var z7488 [1 << 17]byte var z7489 [1 << 17]byte var z7490 [1 << 17]byte var z7491 [1 << 17]byte var z7492 [1 << 17]byte var z7493 [1 << 17]byte var z7494 [1 << 17]byte var z7495 [1 << 17]byte var z7496 [1 << 17]byte var z7497 [1 << 17]byte var z7498 [1 << 17]byte var z7499 [1 << 17]byte var z7500 [1 << 17]byte var z7501 [1 << 17]byte var z7502 [1 << 17]byte var z7503 [1 << 17]byte var z7504 [1 << 17]byte var z7505 [1 << 17]byte var z7506 [1 << 17]byte var z7507 [1 << 17]byte var z7508 [1 << 17]byte var z7509 [1 << 17]byte var z7510 [1 << 17]byte var z7511 [1 << 17]byte var z7512 [1 << 17]byte var z7513 [1 << 17]byte var z7514 [1 << 17]byte var z7515 [1 << 17]byte var z7516 [1 << 17]byte var z7517 [1 << 17]byte var z7518 [1 << 17]byte var z7519 [1 << 17]byte var z7520 [1 << 17]byte var z7521 [1 << 17]byte var z7522 [1 << 17]byte var z7523 [1 << 17]byte var z7524 [1 << 17]byte var z7525 [1 << 17]byte var z7526 [1 << 17]byte var z7527 [1 << 17]byte var z7528 [1 << 17]byte var z7529 [1 << 17]byte var z7530 [1 << 17]byte var z7531 [1 << 17]byte var z7532 [1 << 17]byte var z7533 [1 << 17]byte var z7534 [1 << 17]byte var z7535 [1 << 17]byte var z7536 [1 << 17]byte var z7537 [1 << 17]byte var z7538 [1 << 17]byte var z7539 [1 << 17]byte var z7540 [1 << 17]byte var z7541 [1 << 17]byte var z7542 [1 << 17]byte var z7543 [1 << 17]byte var z7544 [1 << 17]byte var z7545 [1 << 17]byte var z7546 [1 << 17]byte var z7547 [1 << 17]byte var z7548 [1 << 17]byte var z7549 [1 << 17]byte var z7550 [1 << 17]byte var z7551 [1 << 17]byte var z7552 [1 << 17]byte var z7553 [1 << 17]byte var z7554 [1 << 17]byte var z7555 [1 << 17]byte var z7556 [1 << 17]byte var z7557 [1 << 17]byte var z7558 [1 << 17]byte var z7559 [1 << 17]byte var z7560 [1 << 17]byte var z7561 [1 << 17]byte var z7562 [1 << 17]byte var z7563 [1 << 17]byte var z7564 [1 << 17]byte var z7565 [1 << 17]byte var z7566 [1 << 17]byte var z7567 [1 << 17]byte var z7568 [1 << 17]byte var z7569 [1 << 17]byte var z7570 [1 << 17]byte var z7571 [1 << 17]byte var z7572 [1 << 17]byte var z7573 [1 << 17]byte var z7574 [1 << 17]byte var z7575 [1 << 17]byte var z7576 [1 << 17]byte var z7577 [1 << 17]byte var z7578 [1 << 17]byte var z7579 [1 << 17]byte var z7580 [1 << 17]byte var z7581 [1 << 17]byte var z7582 [1 << 17]byte var z7583 [1 << 17]byte var z7584 [1 << 17]byte var z7585 [1 << 17]byte var z7586 [1 << 17]byte var z7587 [1 << 17]byte var z7588 [1 << 17]byte var z7589 [1 << 17]byte var z7590 [1 << 17]byte var z7591 [1 << 17]byte var z7592 [1 << 17]byte var z7593 [1 << 17]byte var z7594 [1 << 17]byte var z7595 [1 << 17]byte var z7596 [1 << 17]byte var z7597 [1 << 17]byte var z7598 [1 << 17]byte var z7599 [1 << 17]byte var z7600 [1 << 17]byte var z7601 [1 << 17]byte var z7602 [1 << 17]byte var z7603 [1 << 17]byte var z7604 [1 << 17]byte var z7605 [1 << 17]byte var z7606 [1 << 17]byte var z7607 [1 << 17]byte var z7608 [1 << 17]byte var z7609 [1 << 17]byte var z7610 [1 << 17]byte var z7611 [1 << 17]byte var z7612 [1 << 17]byte var z7613 [1 << 17]byte var z7614 [1 << 17]byte var z7615 [1 << 17]byte var z7616 [1 << 17]byte var z7617 [1 << 17]byte var z7618 [1 << 17]byte var z7619 [1 << 17]byte var z7620 [1 << 17]byte var z7621 [1 << 17]byte var z7622 [1 << 17]byte var z7623 [1 << 17]byte var z7624 [1 << 17]byte var z7625 [1 << 17]byte var z7626 [1 << 17]byte var z7627 [1 << 17]byte var z7628 [1 << 17]byte var z7629 [1 << 17]byte var z7630 [1 << 17]byte var z7631 [1 << 17]byte var z7632 [1 << 17]byte var z7633 [1 << 17]byte var z7634 [1 << 17]byte var z7635 [1 << 17]byte var z7636 [1 << 17]byte var z7637 [1 << 17]byte var z7638 [1 << 17]byte var z7639 [1 << 17]byte var z7640 [1 << 17]byte var z7641 [1 << 17]byte var z7642 [1 << 17]byte var z7643 [1 << 17]byte var z7644 [1 << 17]byte var z7645 [1 << 17]byte var z7646 [1 << 17]byte var z7647 [1 << 17]byte var z7648 [1 << 17]byte var z7649 [1 << 17]byte var z7650 [1 << 17]byte var z7651 [1 << 17]byte var z7652 [1 << 17]byte var z7653 [1 << 17]byte var z7654 [1 << 17]byte var z7655 [1 << 17]byte var z7656 [1 << 17]byte var z7657 [1 << 17]byte var z7658 [1 << 17]byte var z7659 [1 << 17]byte var z7660 [1 << 17]byte var z7661 [1 << 17]byte var z7662 [1 << 17]byte var z7663 [1 << 17]byte var z7664 [1 << 17]byte var z7665 [1 << 17]byte var z7666 [1 << 17]byte var z7667 [1 << 17]byte var z7668 [1 << 17]byte var z7669 [1 << 17]byte var z7670 [1 << 17]byte var z7671 [1 << 17]byte var z7672 [1 << 17]byte var z7673 [1 << 17]byte var z7674 [1 << 17]byte var z7675 [1 << 17]byte var z7676 [1 << 17]byte var z7677 [1 << 17]byte var z7678 [1 << 17]byte var z7679 [1 << 17]byte var z7680 [1 << 17]byte var z7681 [1 << 17]byte var z7682 [1 << 17]byte var z7683 [1 << 17]byte var z7684 [1 << 17]byte var z7685 [1 << 17]byte var z7686 [1 << 17]byte var z7687 [1 << 17]byte var z7688 [1 << 17]byte var z7689 [1 << 17]byte var z7690 [1 << 17]byte var z7691 [1 << 17]byte var z7692 [1 << 17]byte var z7693 [1 << 17]byte var z7694 [1 << 17]byte var z7695 [1 << 17]byte var z7696 [1 << 17]byte var z7697 [1 << 17]byte var z7698 [1 << 17]byte var z7699 [1 << 17]byte var z7700 [1 << 17]byte var z7701 [1 << 17]byte var z7702 [1 << 17]byte var z7703 [1 << 17]byte var z7704 [1 << 17]byte var z7705 [1 << 17]byte var z7706 [1 << 17]byte var z7707 [1 << 17]byte var z7708 [1 << 17]byte var z7709 [1 << 17]byte var z7710 [1 << 17]byte var z7711 [1 << 17]byte var z7712 [1 << 17]byte var z7713 [1 << 17]byte var z7714 [1 << 17]byte var z7715 [1 << 17]byte var z7716 [1 << 17]byte var z7717 [1 << 17]byte var z7718 [1 << 17]byte var z7719 [1 << 17]byte var z7720 [1 << 17]byte var z7721 [1 << 17]byte var z7722 [1 << 17]byte var z7723 [1 << 17]byte var z7724 [1 << 17]byte var z7725 [1 << 17]byte var z7726 [1 << 17]byte var z7727 [1 << 17]byte var z7728 [1 << 17]byte var z7729 [1 << 17]byte var z7730 [1 << 17]byte var z7731 [1 << 17]byte var z7732 [1 << 17]byte var z7733 [1 << 17]byte var z7734 [1 << 17]byte var z7735 [1 << 17]byte var z7736 [1 << 17]byte var z7737 [1 << 17]byte var z7738 [1 << 17]byte var z7739 [1 << 17]byte var z7740 [1 << 17]byte var z7741 [1 << 17]byte var z7742 [1 << 17]byte var z7743 [1 << 17]byte var z7744 [1 << 17]byte var z7745 [1 << 17]byte var z7746 [1 << 17]byte var z7747 [1 << 17]byte var z7748 [1 << 17]byte var z7749 [1 << 17]byte var z7750 [1 << 17]byte var z7751 [1 << 17]byte var z7752 [1 << 17]byte var z7753 [1 << 17]byte var z7754 [1 << 17]byte var z7755 [1 << 17]byte var z7756 [1 << 17]byte var z7757 [1 << 17]byte var z7758 [1 << 17]byte var z7759 [1 << 17]byte var z7760 [1 << 17]byte var z7761 [1 << 17]byte var z7762 [1 << 17]byte var z7763 [1 << 17]byte var z7764 [1 << 17]byte var z7765 [1 << 17]byte var z7766 [1 << 17]byte var z7767 [1 << 17]byte var z7768 [1 << 17]byte var z7769 [1 << 17]byte var z7770 [1 << 17]byte var z7771 [1 << 17]byte var z7772 [1 << 17]byte var z7773 [1 << 17]byte var z7774 [1 << 17]byte var z7775 [1 << 17]byte var z7776 [1 << 17]byte var z7777 [1 << 17]byte var z7778 [1 << 17]byte var z7779 [1 << 17]byte var z7780 [1 << 17]byte var z7781 [1 << 17]byte var z7782 [1 << 17]byte var z7783 [1 << 17]byte var z7784 [1 << 17]byte var z7785 [1 << 17]byte var z7786 [1 << 17]byte var z7787 [1 << 17]byte var z7788 [1 << 17]byte var z7789 [1 << 17]byte var z7790 [1 << 17]byte var z7791 [1 << 17]byte var z7792 [1 << 17]byte var z7793 [1 << 17]byte var z7794 [1 << 17]byte var z7795 [1 << 17]byte var z7796 [1 << 17]byte var z7797 [1 << 17]byte var z7798 [1 << 17]byte var z7799 [1 << 17]byte var z7800 [1 << 17]byte var z7801 [1 << 17]byte var z7802 [1 << 17]byte var z7803 [1 << 17]byte var z7804 [1 << 17]byte var z7805 [1 << 17]byte var z7806 [1 << 17]byte var z7807 [1 << 17]byte var z7808 [1 << 17]byte var z7809 [1 << 17]byte var z7810 [1 << 17]byte var z7811 [1 << 17]byte var z7812 [1 << 17]byte var z7813 [1 << 17]byte var z7814 [1 << 17]byte var z7815 [1 << 17]byte var z7816 [1 << 17]byte var z7817 [1 << 17]byte var z7818 [1 << 17]byte var z7819 [1 << 17]byte var z7820 [1 << 17]byte var z7821 [1 << 17]byte var z7822 [1 << 17]byte var z7823 [1 << 17]byte var z7824 [1 << 17]byte var z7825 [1 << 17]byte var z7826 [1 << 17]byte var z7827 [1 << 17]byte var z7828 [1 << 17]byte var z7829 [1 << 17]byte var z7830 [1 << 17]byte var z7831 [1 << 17]byte var z7832 [1 << 17]byte var z7833 [1 << 17]byte var z7834 [1 << 17]byte var z7835 [1 << 17]byte var z7836 [1 << 17]byte var z7837 [1 << 17]byte var z7838 [1 << 17]byte var z7839 [1 << 17]byte var z7840 [1 << 17]byte var z7841 [1 << 17]byte var z7842 [1 << 17]byte var z7843 [1 << 17]byte var z7844 [1 << 17]byte var z7845 [1 << 17]byte var z7846 [1 << 17]byte var z7847 [1 << 17]byte var z7848 [1 << 17]byte var z7849 [1 << 17]byte var z7850 [1 << 17]byte var z7851 [1 << 17]byte var z7852 [1 << 17]byte var z7853 [1 << 17]byte var z7854 [1 << 17]byte var z7855 [1 << 17]byte var z7856 [1 << 17]byte var z7857 [1 << 17]byte var z7858 [1 << 17]byte var z7859 [1 << 17]byte var z7860 [1 << 17]byte var z7861 [1 << 17]byte var z7862 [1 << 17]byte var z7863 [1 << 17]byte var z7864 [1 << 17]byte var z7865 [1 << 17]byte var z7866 [1 << 17]byte var z7867 [1 << 17]byte var z7868 [1 << 17]byte var z7869 [1 << 17]byte var z7870 [1 << 17]byte var z7871 [1 << 17]byte var z7872 [1 << 17]byte var z7873 [1 << 17]byte var z7874 [1 << 17]byte var z7875 [1 << 17]byte var z7876 [1 << 17]byte var z7877 [1 << 17]byte var z7878 [1 << 17]byte var z7879 [1 << 17]byte var z7880 [1 << 17]byte var z7881 [1 << 17]byte var z7882 [1 << 17]byte var z7883 [1 << 17]byte var z7884 [1 << 17]byte var z7885 [1 << 17]byte var z7886 [1 << 17]byte var z7887 [1 << 17]byte var z7888 [1 << 17]byte var z7889 [1 << 17]byte var z7890 [1 << 17]byte var z7891 [1 << 17]byte var z7892 [1 << 17]byte var z7893 [1 << 17]byte var z7894 [1 << 17]byte var z7895 [1 << 17]byte var z7896 [1 << 17]byte var z7897 [1 << 17]byte var z7898 [1 << 17]byte var z7899 [1 << 17]byte var z7900 [1 << 17]byte var z7901 [1 << 17]byte var z7902 [1 << 17]byte var z7903 [1 << 17]byte var z7904 [1 << 17]byte var z7905 [1 << 17]byte var z7906 [1 << 17]byte var z7907 [1 << 17]byte var z7908 [1 << 17]byte var z7909 [1 << 17]byte var z7910 [1 << 17]byte var z7911 [1 << 17]byte var z7912 [1 << 17]byte var z7913 [1 << 17]byte var z7914 [1 << 17]byte var z7915 [1 << 17]byte var z7916 [1 << 17]byte var z7917 [1 << 17]byte var z7918 [1 << 17]byte var z7919 [1 << 17]byte var z7920 [1 << 17]byte var z7921 [1 << 17]byte var z7922 [1 << 17]byte var z7923 [1 << 17]byte var z7924 [1 << 17]byte var z7925 [1 << 17]byte var z7926 [1 << 17]byte var z7927 [1 << 17]byte var z7928 [1 << 17]byte var z7929 [1 << 17]byte var z7930 [1 << 17]byte var z7931 [1 << 17]byte var z7932 [1 << 17]byte var z7933 [1 << 17]byte var z7934 [1 << 17]byte var z7935 [1 << 17]byte var z7936 [1 << 17]byte var z7937 [1 << 17]byte var z7938 [1 << 17]byte var z7939 [1 << 17]byte var z7940 [1 << 17]byte var z7941 [1 << 17]byte var z7942 [1 << 17]byte var z7943 [1 << 17]byte var z7944 [1 << 17]byte var z7945 [1 << 17]byte var z7946 [1 << 17]byte var z7947 [1 << 17]byte var z7948 [1 << 17]byte var z7949 [1 << 17]byte var z7950 [1 << 17]byte var z7951 [1 << 17]byte var z7952 [1 << 17]byte var z7953 [1 << 17]byte var z7954 [1 << 17]byte var z7955 [1 << 17]byte var z7956 [1 << 17]byte var z7957 [1 << 17]byte var z7958 [1 << 17]byte var z7959 [1 << 17]byte var z7960 [1 << 17]byte var z7961 [1 << 17]byte var z7962 [1 << 17]byte var z7963 [1 << 17]byte var z7964 [1 << 17]byte var z7965 [1 << 17]byte var z7966 [1 << 17]byte var z7967 [1 << 17]byte var z7968 [1 << 17]byte var z7969 [1 << 17]byte var z7970 [1 << 17]byte var z7971 [1 << 17]byte var z7972 [1 << 17]byte var z7973 [1 << 17]byte var z7974 [1 << 17]byte var z7975 [1 << 17]byte var z7976 [1 << 17]byte var z7977 [1 << 17]byte var z7978 [1 << 17]byte var z7979 [1 << 17]byte var z7980 [1 << 17]byte var z7981 [1 << 17]byte var z7982 [1 << 17]byte var z7983 [1 << 17]byte var z7984 [1 << 17]byte var z7985 [1 << 17]byte var z7986 [1 << 17]byte var z7987 [1 << 17]byte var z7988 [1 << 17]byte var z7989 [1 << 17]byte var z7990 [1 << 17]byte var z7991 [1 << 17]byte var z7992 [1 << 17]byte var z7993 [1 << 17]byte var z7994 [1 << 17]byte var z7995 [1 << 17]byte var z7996 [1 << 17]byte var z7997 [1 << 17]byte var z7998 [1 << 17]byte var z7999 [1 << 17]byte var z8000 [1 << 17]byte var z8001 [1 << 17]byte var z8002 [1 << 17]byte var z8003 [1 << 17]byte var z8004 [1 << 17]byte var z8005 [1 << 17]byte var z8006 [1 << 17]byte var z8007 [1 << 17]byte var z8008 [1 << 17]byte var z8009 [1 << 17]byte var z8010 [1 << 17]byte var z8011 [1 << 17]byte var z8012 [1 << 17]byte var z8013 [1 << 17]byte var z8014 [1 << 17]byte var z8015 [1 << 17]byte var z8016 [1 << 17]byte var z8017 [1 << 17]byte var z8018 [1 << 17]byte var z8019 [1 << 17]byte var z8020 [1 << 17]byte var z8021 [1 << 17]byte var z8022 [1 << 17]byte var z8023 [1 << 17]byte var z8024 [1 << 17]byte var z8025 [1 << 17]byte var z8026 [1 << 17]byte var z8027 [1 << 17]byte var z8028 [1 << 17]byte var z8029 [1 << 17]byte var z8030 [1 << 17]byte var z8031 [1 << 17]byte var z8032 [1 << 17]byte var z8033 [1 << 17]byte var z8034 [1 << 17]byte var z8035 [1 << 17]byte var z8036 [1 << 17]byte var z8037 [1 << 17]byte var z8038 [1 << 17]byte var z8039 [1 << 17]byte var z8040 [1 << 17]byte var z8041 [1 << 17]byte var z8042 [1 << 17]byte var z8043 [1 << 17]byte var z8044 [1 << 17]byte var z8045 [1 << 17]byte var z8046 [1 << 17]byte var z8047 [1 << 17]byte var z8048 [1 << 17]byte var z8049 [1 << 17]byte var z8050 [1 << 17]byte var z8051 [1 << 17]byte var z8052 [1 << 17]byte var z8053 [1 << 17]byte var z8054 [1 << 17]byte var z8055 [1 << 17]byte var z8056 [1 << 17]byte var z8057 [1 << 17]byte var z8058 [1 << 17]byte var z8059 [1 << 17]byte var z8060 [1 << 17]byte var z8061 [1 << 17]byte var z8062 [1 << 17]byte var z8063 [1 << 17]byte var z8064 [1 << 17]byte var z8065 [1 << 17]byte var z8066 [1 << 17]byte var z8067 [1 << 17]byte var z8068 [1 << 17]byte var z8069 [1 << 17]byte var z8070 [1 << 17]byte var z8071 [1 << 17]byte var z8072 [1 << 17]byte var z8073 [1 << 17]byte var z8074 [1 << 17]byte var z8075 [1 << 17]byte var z8076 [1 << 17]byte var z8077 [1 << 17]byte var z8078 [1 << 17]byte var z8079 [1 << 17]byte var z8080 [1 << 17]byte var z8081 [1 << 17]byte var z8082 [1 << 17]byte var z8083 [1 << 17]byte var z8084 [1 << 17]byte var z8085 [1 << 17]byte var z8086 [1 << 17]byte var z8087 [1 << 17]byte var z8088 [1 << 17]byte var z8089 [1 << 17]byte var z8090 [1 << 17]byte var z8091 [1 << 17]byte var z8092 [1 << 17]byte var z8093 [1 << 17]byte var z8094 [1 << 17]byte var z8095 [1 << 17]byte var z8096 [1 << 17]byte var z8097 [1 << 17]byte var z8098 [1 << 17]byte var z8099 [1 << 17]byte var z8100 [1 << 17]byte var z8101 [1 << 17]byte var z8102 [1 << 17]byte var z8103 [1 << 17]byte var z8104 [1 << 17]byte var z8105 [1 << 17]byte var z8106 [1 << 17]byte var z8107 [1 << 17]byte var z8108 [1 << 17]byte var z8109 [1 << 17]byte var z8110 [1 << 17]byte var z8111 [1 << 17]byte var z8112 [1 << 17]byte var z8113 [1 << 17]byte var z8114 [1 << 17]byte var z8115 [1 << 17]byte var z8116 [1 << 17]byte var z8117 [1 << 17]byte var z8118 [1 << 17]byte var z8119 [1 << 17]byte var z8120 [1 << 17]byte var z8121 [1 << 17]byte var z8122 [1 << 17]byte var z8123 [1 << 17]byte var z8124 [1 << 17]byte var z8125 [1 << 17]byte var z8126 [1 << 17]byte var z8127 [1 << 17]byte var z8128 [1 << 17]byte var z8129 [1 << 17]byte var z8130 [1 << 17]byte var z8131 [1 << 17]byte var z8132 [1 << 17]byte var z8133 [1 << 17]byte var z8134 [1 << 17]byte var z8135 [1 << 17]byte var z8136 [1 << 17]byte var z8137 [1 << 17]byte var z8138 [1 << 17]byte var z8139 [1 << 17]byte var z8140 [1 << 17]byte var z8141 [1 << 17]byte var z8142 [1 << 17]byte var z8143 [1 << 17]byte var z8144 [1 << 17]byte var z8145 [1 << 17]byte var z8146 [1 << 17]byte var z8147 [1 << 17]byte var z8148 [1 << 17]byte var z8149 [1 << 17]byte var z8150 [1 << 17]byte var z8151 [1 << 17]byte var z8152 [1 << 17]byte var z8153 [1 << 17]byte var z8154 [1 << 17]byte var z8155 [1 << 17]byte var z8156 [1 << 17]byte var z8157 [1 << 17]byte var z8158 [1 << 17]byte var z8159 [1 << 17]byte var z8160 [1 << 17]byte var z8161 [1 << 17]byte var z8162 [1 << 17]byte var z8163 [1 << 17]byte var z8164 [1 << 17]byte var z8165 [1 << 17]byte var z8166 [1 << 17]byte var z8167 [1 << 17]byte var z8168 [1 << 17]byte var z8169 [1 << 17]byte var z8170 [1 << 17]byte var z8171 [1 << 17]byte var z8172 [1 << 17]byte var z8173 [1 << 17]byte var z8174 [1 << 17]byte var z8175 [1 << 17]byte var z8176 [1 << 17]byte var z8177 [1 << 17]byte var z8178 [1 << 17]byte var z8179 [1 << 17]byte var z8180 [1 << 17]byte var z8181 [1 << 17]byte var z8182 [1 << 17]byte var z8183 [1 << 17]byte var z8184 [1 << 17]byte var z8185 [1 << 17]byte var z8186 [1 << 17]byte var z8187 [1 << 17]byte var z8188 [1 << 17]byte var z8189 [1 << 17]byte var z8190 [1 << 17]byte var z8191 [1 << 17]byte var z8192 [1 << 17]byte var z8193 [1 << 17]byte var z8194 [1 << 17]byte var z8195 [1 << 17]byte var z8196 [1 << 17]byte var z8197 [1 << 17]byte var z8198 [1 << 17]byte var z8199 [1 << 17]byte var z8200 [1 << 17]byte var z8201 [1 << 17]byte var z8202 [1 << 17]byte var z8203 [1 << 17]byte var z8204 [1 << 17]byte var z8205 [1 << 17]byte var z8206 [1 << 17]byte var z8207 [1 << 17]byte var z8208 [1 << 17]byte var z8209 [1 << 17]byte var z8210 [1 << 17]byte var z8211 [1 << 17]byte var z8212 [1 << 17]byte var z8213 [1 << 17]byte var z8214 [1 << 17]byte var z8215 [1 << 17]byte var z8216 [1 << 17]byte var z8217 [1 << 17]byte var z8218 [1 << 17]byte var z8219 [1 << 17]byte var z8220 [1 << 17]byte var z8221 [1 << 17]byte var z8222 [1 << 17]byte var z8223 [1 << 17]byte var z8224 [1 << 17]byte var z8225 [1 << 17]byte var z8226 [1 << 17]byte var z8227 [1 << 17]byte var z8228 [1 << 17]byte var z8229 [1 << 17]byte var z8230 [1 << 17]byte var z8231 [1 << 17]byte var z8232 [1 << 17]byte var z8233 [1 << 17]byte var z8234 [1 << 17]byte var z8235 [1 << 17]byte var z8236 [1 << 17]byte var z8237 [1 << 17]byte var z8238 [1 << 17]byte var z8239 [1 << 17]byte var z8240 [1 << 17]byte var z8241 [1 << 17]byte var z8242 [1 << 17]byte var z8243 [1 << 17]byte var z8244 [1 << 17]byte var z8245 [1 << 17]byte var z8246 [1 << 17]byte var z8247 [1 << 17]byte var z8248 [1 << 17]byte var z8249 [1 << 17]byte var z8250 [1 << 17]byte var z8251 [1 << 17]byte var z8252 [1 << 17]byte var z8253 [1 << 17]byte var z8254 [1 << 17]byte var z8255 [1 << 17]byte var z8256 [1 << 17]byte var z8257 [1 << 17]byte var z8258 [1 << 17]byte var z8259 [1 << 17]byte var z8260 [1 << 17]byte var z8261 [1 << 17]byte var z8262 [1 << 17]byte var z8263 [1 << 17]byte var z8264 [1 << 17]byte var z8265 [1 << 17]byte var z8266 [1 << 17]byte var z8267 [1 << 17]byte var z8268 [1 << 17]byte var z8269 [1 << 17]byte var z8270 [1 << 17]byte var z8271 [1 << 17]byte var z8272 [1 << 17]byte var z8273 [1 << 17]byte var z8274 [1 << 17]byte var z8275 [1 << 17]byte var z8276 [1 << 17]byte var z8277 [1 << 17]byte var z8278 [1 << 17]byte var z8279 [1 << 17]byte var z8280 [1 << 17]byte var z8281 [1 << 17]byte var z8282 [1 << 17]byte var z8283 [1 << 17]byte var z8284 [1 << 17]byte var z8285 [1 << 17]byte var z8286 [1 << 17]byte var z8287 [1 << 17]byte var z8288 [1 << 17]byte var z8289 [1 << 17]byte var z8290 [1 << 17]byte var z8291 [1 << 17]byte var z8292 [1 << 17]byte var z8293 [1 << 17]byte var z8294 [1 << 17]byte var z8295 [1 << 17]byte var z8296 [1 << 17]byte var z8297 [1 << 17]byte var z8298 [1 << 17]byte var z8299 [1 << 17]byte var z8300 [1 << 17]byte var z8301 [1 << 17]byte var z8302 [1 << 17]byte var z8303 [1 << 17]byte var z8304 [1 << 17]byte var z8305 [1 << 17]byte var z8306 [1 << 17]byte var z8307 [1 << 17]byte var z8308 [1 << 17]byte var z8309 [1 << 17]byte var z8310 [1 << 17]byte var z8311 [1 << 17]byte var z8312 [1 << 17]byte var z8313 [1 << 17]byte var z8314 [1 << 17]byte var z8315 [1 << 17]byte var z8316 [1 << 17]byte var z8317 [1 << 17]byte var z8318 [1 << 17]byte var z8319 [1 << 17]byte var z8320 [1 << 17]byte var z8321 [1 << 17]byte var z8322 [1 << 17]byte var z8323 [1 << 17]byte var z8324 [1 << 17]byte var z8325 [1 << 17]byte var z8326 [1 << 17]byte var z8327 [1 << 17]byte var z8328 [1 << 17]byte var z8329 [1 << 17]byte var z8330 [1 << 17]byte var z8331 [1 << 17]byte var z8332 [1 << 17]byte var z8333 [1 << 17]byte var z8334 [1 << 17]byte var z8335 [1 << 17]byte var z8336 [1 << 17]byte var z8337 [1 << 17]byte var z8338 [1 << 17]byte var z8339 [1 << 17]byte var z8340 [1 << 17]byte var z8341 [1 << 17]byte var z8342 [1 << 17]byte var z8343 [1 << 17]byte var z8344 [1 << 17]byte var z8345 [1 << 17]byte var z8346 [1 << 17]byte var z8347 [1 << 17]byte var z8348 [1 << 17]byte var z8349 [1 << 17]byte var z8350 [1 << 17]byte var z8351 [1 << 17]byte var z8352 [1 << 17]byte var z8353 [1 << 17]byte var z8354 [1 << 17]byte var z8355 [1 << 17]byte var z8356 [1 << 17]byte var z8357 [1 << 17]byte var z8358 [1 << 17]byte var z8359 [1 << 17]byte var z8360 [1 << 17]byte var z8361 [1 << 17]byte var z8362 [1 << 17]byte var z8363 [1 << 17]byte var z8364 [1 << 17]byte var z8365 [1 << 17]byte var z8366 [1 << 17]byte var z8367 [1 << 17]byte var z8368 [1 << 17]byte var z8369 [1 << 17]byte var z8370 [1 << 17]byte var z8371 [1 << 17]byte var z8372 [1 << 17]byte var z8373 [1 << 17]byte var z8374 [1 << 17]byte var z8375 [1 << 17]byte var z8376 [1 << 17]byte var z8377 [1 << 17]byte var z8378 [1 << 17]byte var z8379 [1 << 17]byte var z8380 [1 << 17]byte var z8381 [1 << 17]byte var z8382 [1 << 17]byte var z8383 [1 << 17]byte var z8384 [1 << 17]byte var z8385 [1 << 17]byte var z8386 [1 << 17]byte var z8387 [1 << 17]byte var z8388 [1 << 17]byte var z8389 [1 << 17]byte var z8390 [1 << 17]byte var z8391 [1 << 17]byte var z8392 [1 << 17]byte var z8393 [1 << 17]byte var z8394 [1 << 17]byte var z8395 [1 << 17]byte var z8396 [1 << 17]byte var z8397 [1 << 17]byte var z8398 [1 << 17]byte var z8399 [1 << 17]byte var z8400 [1 << 17]byte var z8401 [1 << 17]byte var z8402 [1 << 17]byte var z8403 [1 << 17]byte var z8404 [1 << 17]byte var z8405 [1 << 17]byte var z8406 [1 << 17]byte var z8407 [1 << 17]byte var z8408 [1 << 17]byte var z8409 [1 << 17]byte var z8410 [1 << 17]byte var z8411 [1 << 17]byte var z8412 [1 << 17]byte var z8413 [1 << 17]byte var z8414 [1 << 17]byte var z8415 [1 << 17]byte var z8416 [1 << 17]byte var z8417 [1 << 17]byte var z8418 [1 << 17]byte var z8419 [1 << 17]byte var z8420 [1 << 17]byte var z8421 [1 << 17]byte var z8422 [1 << 17]byte var z8423 [1 << 17]byte var z8424 [1 << 17]byte var z8425 [1 << 17]byte var z8426 [1 << 17]byte var z8427 [1 << 17]byte var z8428 [1 << 17]byte var z8429 [1 << 17]byte var z8430 [1 << 17]byte var z8431 [1 << 17]byte var z8432 [1 << 17]byte var z8433 [1 << 17]byte var z8434 [1 << 17]byte var z8435 [1 << 17]byte var z8436 [1 << 17]byte var z8437 [1 << 17]byte var z8438 [1 << 17]byte var z8439 [1 << 17]byte var z8440 [1 << 17]byte var z8441 [1 << 17]byte var z8442 [1 << 17]byte var z8443 [1 << 17]byte var z8444 [1 << 17]byte var z8445 [1 << 17]byte var z8446 [1 << 17]byte var z8447 [1 << 17]byte var z8448 [1 << 17]byte var z8449 [1 << 17]byte var z8450 [1 << 17]byte var z8451 [1 << 17]byte var z8452 [1 << 17]byte var z8453 [1 << 17]byte var z8454 [1 << 17]byte var z8455 [1 << 17]byte var z8456 [1 << 17]byte var z8457 [1 << 17]byte var z8458 [1 << 17]byte var z8459 [1 << 17]byte var z8460 [1 << 17]byte var z8461 [1 << 17]byte var z8462 [1 << 17]byte var z8463 [1 << 17]byte var z8464 [1 << 17]byte var z8465 [1 << 17]byte var z8466 [1 << 17]byte var z8467 [1 << 17]byte var z8468 [1 << 17]byte var z8469 [1 << 17]byte var z8470 [1 << 17]byte var z8471 [1 << 17]byte var z8472 [1 << 17]byte var z8473 [1 << 17]byte var z8474 [1 << 17]byte var z8475 [1 << 17]byte var z8476 [1 << 17]byte var z8477 [1 << 17]byte var z8478 [1 << 17]byte var z8479 [1 << 17]byte var z8480 [1 << 17]byte var z8481 [1 << 17]byte var z8482 [1 << 17]byte var z8483 [1 << 17]byte var z8484 [1 << 17]byte var z8485 [1 << 17]byte var z8486 [1 << 17]byte var z8487 [1 << 17]byte var z8488 [1 << 17]byte var z8489 [1 << 17]byte var z8490 [1 << 17]byte var z8491 [1 << 17]byte var z8492 [1 << 17]byte var z8493 [1 << 17]byte var z8494 [1 << 17]byte var z8495 [1 << 17]byte var z8496 [1 << 17]byte var z8497 [1 << 17]byte var z8498 [1 << 17]byte var z8499 [1 << 17]byte var z8500 [1 << 17]byte var z8501 [1 << 17]byte var z8502 [1 << 17]byte var z8503 [1 << 17]byte var z8504 [1 << 17]byte var z8505 [1 << 17]byte var z8506 [1 << 17]byte var z8507 [1 << 17]byte var z8508 [1 << 17]byte var z8509 [1 << 17]byte var z8510 [1 << 17]byte var z8511 [1 << 17]byte var z8512 [1 << 17]byte var z8513 [1 << 17]byte var z8514 [1 << 17]byte var z8515 [1 << 17]byte var z8516 [1 << 17]byte var z8517 [1 << 17]byte var z8518 [1 << 17]byte var z8519 [1 << 17]byte var z8520 [1 << 17]byte var z8521 [1 << 17]byte var z8522 [1 << 17]byte var z8523 [1 << 17]byte var z8524 [1 << 17]byte var z8525 [1 << 17]byte var z8526 [1 << 17]byte var z8527 [1 << 17]byte var z8528 [1 << 17]byte var z8529 [1 << 17]byte var z8530 [1 << 17]byte var z8531 [1 << 17]byte var z8532 [1 << 17]byte var z8533 [1 << 17]byte var z8534 [1 << 17]byte var z8535 [1 << 17]byte var z8536 [1 << 17]byte var z8537 [1 << 17]byte var z8538 [1 << 17]byte var z8539 [1 << 17]byte var z8540 [1 << 17]byte var z8541 [1 << 17]byte var z8542 [1 << 17]byte var z8543 [1 << 17]byte var z8544 [1 << 17]byte var z8545 [1 << 17]byte var z8546 [1 << 17]byte var z8547 [1 << 17]byte var z8548 [1 << 17]byte var z8549 [1 << 17]byte var z8550 [1 << 17]byte var z8551 [1 << 17]byte var z8552 [1 << 17]byte var z8553 [1 << 17]byte var z8554 [1 << 17]byte var z8555 [1 << 17]byte var z8556 [1 << 17]byte var z8557 [1 << 17]byte var z8558 [1 << 17]byte var z8559 [1 << 17]byte var z8560 [1 << 17]byte var z8561 [1 << 17]byte var z8562 [1 << 17]byte var z8563 [1 << 17]byte var z8564 [1 << 17]byte var z8565 [1 << 17]byte var z8566 [1 << 17]byte var z8567 [1 << 17]byte var z8568 [1 << 17]byte var z8569 [1 << 17]byte var z8570 [1 << 17]byte var z8571 [1 << 17]byte var z8572 [1 << 17]byte var z8573 [1 << 17]byte var z8574 [1 << 17]byte var z8575 [1 << 17]byte var z8576 [1 << 17]byte var z8577 [1 << 17]byte var z8578 [1 << 17]byte var z8579 [1 << 17]byte var z8580 [1 << 17]byte var z8581 [1 << 17]byte var z8582 [1 << 17]byte var z8583 [1 << 17]byte var z8584 [1 << 17]byte var z8585 [1 << 17]byte var z8586 [1 << 17]byte var z8587 [1 << 17]byte var z8588 [1 << 17]byte var z8589 [1 << 17]byte var z8590 [1 << 17]byte var z8591 [1 << 17]byte var z8592 [1 << 17]byte var z8593 [1 << 17]byte var z8594 [1 << 17]byte var z8595 [1 << 17]byte var z8596 [1 << 17]byte var z8597 [1 << 17]byte var z8598 [1 << 17]byte var z8599 [1 << 17]byte var z8600 [1 << 17]byte var z8601 [1 << 17]byte var z8602 [1 << 17]byte var z8603 [1 << 17]byte var z8604 [1 << 17]byte var z8605 [1 << 17]byte var z8606 [1 << 17]byte var z8607 [1 << 17]byte var z8608 [1 << 17]byte var z8609 [1 << 17]byte var z8610 [1 << 17]byte var z8611 [1 << 17]byte var z8612 [1 << 17]byte var z8613 [1 << 17]byte var z8614 [1 << 17]byte var z8615 [1 << 17]byte var z8616 [1 << 17]byte var z8617 [1 << 17]byte var z8618 [1 << 17]byte var z8619 [1 << 17]byte var z8620 [1 << 17]byte var z8621 [1 << 17]byte var z8622 [1 << 17]byte var z8623 [1 << 17]byte var z8624 [1 << 17]byte var z8625 [1 << 17]byte var z8626 [1 << 17]byte var z8627 [1 << 17]byte var z8628 [1 << 17]byte var z8629 [1 << 17]byte var z8630 [1 << 17]byte var z8631 [1 << 17]byte var z8632 [1 << 17]byte var z8633 [1 << 17]byte var z8634 [1 << 17]byte var z8635 [1 << 17]byte var z8636 [1 << 17]byte var z8637 [1 << 17]byte var z8638 [1 << 17]byte var z8639 [1 << 17]byte var z8640 [1 << 17]byte var z8641 [1 << 17]byte var z8642 [1 << 17]byte var z8643 [1 << 17]byte var z8644 [1 << 17]byte var z8645 [1 << 17]byte var z8646 [1 << 17]byte var z8647 [1 << 17]byte var z8648 [1 << 17]byte var z8649 [1 << 17]byte var z8650 [1 << 17]byte var z8651 [1 << 17]byte var z8652 [1 << 17]byte var z8653 [1 << 17]byte var z8654 [1 << 17]byte var z8655 [1 << 17]byte var z8656 [1 << 17]byte var z8657 [1 << 17]byte var z8658 [1 << 17]byte var z8659 [1 << 17]byte var z8660 [1 << 17]byte var z8661 [1 << 17]byte var z8662 [1 << 17]byte var z8663 [1 << 17]byte var z8664 [1 << 17]byte var z8665 [1 << 17]byte var z8666 [1 << 17]byte var z8667 [1 << 17]byte var z8668 [1 << 17]byte var z8669 [1 << 17]byte var z8670 [1 << 17]byte var z8671 [1 << 17]byte var z8672 [1 << 17]byte var z8673 [1 << 17]byte var z8674 [1 << 17]byte var z8675 [1 << 17]byte var z8676 [1 << 17]byte var z8677 [1 << 17]byte var z8678 [1 << 17]byte var z8679 [1 << 17]byte var z8680 [1 << 17]byte var z8681 [1 << 17]byte var z8682 [1 << 17]byte var z8683 [1 << 17]byte var z8684 [1 << 17]byte var z8685 [1 << 17]byte var z8686 [1 << 17]byte var z8687 [1 << 17]byte var z8688 [1 << 17]byte var z8689 [1 << 17]byte var z8690 [1 << 17]byte var z8691 [1 << 17]byte var z8692 [1 << 17]byte var z8693 [1 << 17]byte var z8694 [1 << 17]byte var z8695 [1 << 17]byte var z8696 [1 << 17]byte var z8697 [1 << 17]byte var z8698 [1 << 17]byte var z8699 [1 << 17]byte var z8700 [1 << 17]byte var z8701 [1 << 17]byte var z8702 [1 << 17]byte var z8703 [1 << 17]byte var z8704 [1 << 17]byte var z8705 [1 << 17]byte var z8706 [1 << 17]byte var z8707 [1 << 17]byte var z8708 [1 << 17]byte var z8709 [1 << 17]byte var z8710 [1 << 17]byte var z8711 [1 << 17]byte var z8712 [1 << 17]byte var z8713 [1 << 17]byte var z8714 [1 << 17]byte var z8715 [1 << 17]byte var z8716 [1 << 17]byte var z8717 [1 << 17]byte var z8718 [1 << 17]byte var z8719 [1 << 17]byte var z8720 [1 << 17]byte var z8721 [1 << 17]byte var z8722 [1 << 17]byte var z8723 [1 << 17]byte var z8724 [1 << 17]byte var z8725 [1 << 17]byte var z8726 [1 << 17]byte var z8727 [1 << 17]byte var z8728 [1 << 17]byte var z8729 [1 << 17]byte var z8730 [1 << 17]byte var z8731 [1 << 17]byte var z8732 [1 << 17]byte var z8733 [1 << 17]byte var z8734 [1 << 17]byte var z8735 [1 << 17]byte var z8736 [1 << 17]byte var z8737 [1 << 17]byte var z8738 [1 << 17]byte var z8739 [1 << 17]byte var z8740 [1 << 17]byte var z8741 [1 << 17]byte var z8742 [1 << 17]byte var z8743 [1 << 17]byte var z8744 [1 << 17]byte var z8745 [1 << 17]byte var z8746 [1 << 17]byte var z8747 [1 << 17]byte var z8748 [1 << 17]byte var z8749 [1 << 17]byte var z8750 [1 << 17]byte var z8751 [1 << 17]byte var z8752 [1 << 17]byte var z8753 [1 << 17]byte var z8754 [1 << 17]byte var z8755 [1 << 17]byte var z8756 [1 << 17]byte var z8757 [1 << 17]byte var z8758 [1 << 17]byte var z8759 [1 << 17]byte var z8760 [1 << 17]byte var z8761 [1 << 17]byte var z8762 [1 << 17]byte var z8763 [1 << 17]byte var z8764 [1 << 17]byte var z8765 [1 << 17]byte var z8766 [1 << 17]byte var z8767 [1 << 17]byte var z8768 [1 << 17]byte var z8769 [1 << 17]byte var z8770 [1 << 17]byte var z8771 [1 << 17]byte var z8772 [1 << 17]byte var z8773 [1 << 17]byte var z8774 [1 << 17]byte var z8775 [1 << 17]byte var z8776 [1 << 17]byte var z8777 [1 << 17]byte var z8778 [1 << 17]byte var z8779 [1 << 17]byte var z8780 [1 << 17]byte var z8781 [1 << 17]byte var z8782 [1 << 17]byte var z8783 [1 << 17]byte var z8784 [1 << 17]byte var z8785 [1 << 17]byte var z8786 [1 << 17]byte var z8787 [1 << 17]byte var z8788 [1 << 17]byte var z8789 [1 << 17]byte var z8790 [1 << 17]byte var z8791 [1 << 17]byte var z8792 [1 << 17]byte var z8793 [1 << 17]byte var z8794 [1 << 17]byte var z8795 [1 << 17]byte var z8796 [1 << 17]byte var z8797 [1 << 17]byte var z8798 [1 << 17]byte var z8799 [1 << 17]byte var z8800 [1 << 17]byte var z8801 [1 << 17]byte var z8802 [1 << 17]byte var z8803 [1 << 17]byte var z8804 [1 << 17]byte var z8805 [1 << 17]byte var z8806 [1 << 17]byte var z8807 [1 << 17]byte var z8808 [1 << 17]byte var z8809 [1 << 17]byte var z8810 [1 << 17]byte var z8811 [1 << 17]byte var z8812 [1 << 17]byte var z8813 [1 << 17]byte var z8814 [1 << 17]byte var z8815 [1 << 17]byte var z8816 [1 << 17]byte var z8817 [1 << 17]byte var z8818 [1 << 17]byte var z8819 [1 << 17]byte var z8820 [1 << 17]byte var z8821 [1 << 17]byte var z8822 [1 << 17]byte var z8823 [1 << 17]byte var z8824 [1 << 17]byte var z8825 [1 << 17]byte var z8826 [1 << 17]byte var z8827 [1 << 17]byte var z8828 [1 << 17]byte var z8829 [1 << 17]byte var z8830 [1 << 17]byte var z8831 [1 << 17]byte var z8832 [1 << 17]byte var z8833 [1 << 17]byte var z8834 [1 << 17]byte var z8835 [1 << 17]byte var z8836 [1 << 17]byte var z8837 [1 << 17]byte var z8838 [1 << 17]byte var z8839 [1 << 17]byte var z8840 [1 << 17]byte var z8841 [1 << 17]byte var z8842 [1 << 17]byte var z8843 [1 << 17]byte var z8844 [1 << 17]byte var z8845 [1 << 17]byte var z8846 [1 << 17]byte var z8847 [1 << 17]byte var z8848 [1 << 17]byte var z8849 [1 << 17]byte var z8850 [1 << 17]byte var z8851 [1 << 17]byte var z8852 [1 << 17]byte var z8853 [1 << 17]byte var z8854 [1 << 17]byte var z8855 [1 << 17]byte var z8856 [1 << 17]byte var z8857 [1 << 17]byte var z8858 [1 << 17]byte var z8859 [1 << 17]byte var z8860 [1 << 17]byte var z8861 [1 << 17]byte var z8862 [1 << 17]byte var z8863 [1 << 17]byte var z8864 [1 << 17]byte var z8865 [1 << 17]byte var z8866 [1 << 17]byte var z8867 [1 << 17]byte var z8868 [1 << 17]byte var z8869 [1 << 17]byte var z8870 [1 << 17]byte var z8871 [1 << 17]byte var z8872 [1 << 17]byte var z8873 [1 << 17]byte var z8874 [1 << 17]byte var z8875 [1 << 17]byte var z8876 [1 << 17]byte var z8877 [1 << 17]byte var z8878 [1 << 17]byte var z8879 [1 << 17]byte var z8880 [1 << 17]byte var z8881 [1 << 17]byte var z8882 [1 << 17]byte var z8883 [1 << 17]byte var z8884 [1 << 17]byte var z8885 [1 << 17]byte var z8886 [1 << 17]byte var z8887 [1 << 17]byte var z8888 [1 << 17]byte var z8889 [1 << 17]byte var z8890 [1 << 17]byte var z8891 [1 << 17]byte var z8892 [1 << 17]byte var z8893 [1 << 17]byte var z8894 [1 << 17]byte var z8895 [1 << 17]byte var z8896 [1 << 17]byte var z8897 [1 << 17]byte var z8898 [1 << 17]byte var z8899 [1 << 17]byte var z8900 [1 << 17]byte var z8901 [1 << 17]byte var z8902 [1 << 17]byte var z8903 [1 << 17]byte var z8904 [1 << 17]byte var z8905 [1 << 17]byte var z8906 [1 << 17]byte var z8907 [1 << 17]byte var z8908 [1 << 17]byte var z8909 [1 << 17]byte var z8910 [1 << 17]byte var z8911 [1 << 17]byte var z8912 [1 << 17]byte var z8913 [1 << 17]byte var z8914 [1 << 17]byte var z8915 [1 << 17]byte var z8916 [1 << 17]byte var z8917 [1 << 17]byte var z8918 [1 << 17]byte var z8919 [1 << 17]byte var z8920 [1 << 17]byte var z8921 [1 << 17]byte var z8922 [1 << 17]byte var z8923 [1 << 17]byte var z8924 [1 << 17]byte var z8925 [1 << 17]byte var z8926 [1 << 17]byte var z8927 [1 << 17]byte var z8928 [1 << 17]byte var z8929 [1 << 17]byte var z8930 [1 << 17]byte var z8931 [1 << 17]byte var z8932 [1 << 17]byte var z8933 [1 << 17]byte var z8934 [1 << 17]byte var z8935 [1 << 17]byte var z8936 [1 << 17]byte var z8937 [1 << 17]byte var z8938 [1 << 17]byte var z8939 [1 << 17]byte var z8940 [1 << 17]byte var z8941 [1 << 17]byte var z8942 [1 << 17]byte var z8943 [1 << 17]byte var z8944 [1 << 17]byte var z8945 [1 << 17]byte var z8946 [1 << 17]byte var z8947 [1 << 17]byte var z8948 [1 << 17]byte var z8949 [1 << 17]byte var z8950 [1 << 17]byte var z8951 [1 << 17]byte var z8952 [1 << 17]byte var z8953 [1 << 17]byte var z8954 [1 << 17]byte var z8955 [1 << 17]byte var z8956 [1 << 17]byte var z8957 [1 << 17]byte var z8958 [1 << 17]byte var z8959 [1 << 17]byte var z8960 [1 << 17]byte var z8961 [1 << 17]byte var z8962 [1 << 17]byte var z8963 [1 << 17]byte var z8964 [1 << 17]byte var z8965 [1 << 17]byte var z8966 [1 << 17]byte var z8967 [1 << 17]byte var z8968 [1 << 17]byte var z8969 [1 << 17]byte var z8970 [1 << 17]byte var z8971 [1 << 17]byte var z8972 [1 << 17]byte var z8973 [1 << 17]byte var z8974 [1 << 17]byte var z8975 [1 << 17]byte var z8976 [1 << 17]byte var z8977 [1 << 17]byte var z8978 [1 << 17]byte var z8979 [1 << 17]byte var z8980 [1 << 17]byte var z8981 [1 << 17]byte var z8982 [1 << 17]byte var z8983 [1 << 17]byte var z8984 [1 << 17]byte var z8985 [1 << 17]byte var z8986 [1 << 17]byte var z8987 [1 << 17]byte var z8988 [1 << 17]byte var z8989 [1 << 17]byte var z8990 [1 << 17]byte var z8991 [1 << 17]byte var z8992 [1 << 17]byte var z8993 [1 << 17]byte var z8994 [1 << 17]byte var z8995 [1 << 17]byte var z8996 [1 << 17]byte var z8997 [1 << 17]byte var z8998 [1 << 17]byte var z8999 [1 << 17]byte var z9000 [1 << 17]byte var z9001 [1 << 17]byte var z9002 [1 << 17]byte var z9003 [1 << 17]byte var z9004 [1 << 17]byte var z9005 [1 << 17]byte var z9006 [1 << 17]byte var z9007 [1 << 17]byte var z9008 [1 << 17]byte var z9009 [1 << 17]byte var z9010 [1 << 17]byte var z9011 [1 << 17]byte var z9012 [1 << 17]byte var z9013 [1 << 17]byte var z9014 [1 << 17]byte var z9015 [1 << 17]byte var z9016 [1 << 17]byte var z9017 [1 << 17]byte var z9018 [1 << 17]byte var z9019 [1 << 17]byte var z9020 [1 << 17]byte var z9021 [1 << 17]byte var z9022 [1 << 17]byte var z9023 [1 << 17]byte var z9024 [1 << 17]byte var z9025 [1 << 17]byte var z9026 [1 << 17]byte var z9027 [1 << 17]byte var z9028 [1 << 17]byte var z9029 [1 << 17]byte var z9030 [1 << 17]byte var z9031 [1 << 17]byte var z9032 [1 << 17]byte var z9033 [1 << 17]byte var z9034 [1 << 17]byte var z9035 [1 << 17]byte var z9036 [1 << 17]byte var z9037 [1 << 17]byte var z9038 [1 << 17]byte var z9039 [1 << 17]byte var z9040 [1 << 17]byte var z9041 [1 << 17]byte var z9042 [1 << 17]byte var z9043 [1 << 17]byte var z9044 [1 << 17]byte var z9045 [1 << 17]byte var z9046 [1 << 17]byte var z9047 [1 << 17]byte var z9048 [1 << 17]byte var z9049 [1 << 17]byte var z9050 [1 << 17]byte var z9051 [1 << 17]byte var z9052 [1 << 17]byte var z9053 [1 << 17]byte var z9054 [1 << 17]byte var z9055 [1 << 17]byte var z9056 [1 << 17]byte var z9057 [1 << 17]byte var z9058 [1 << 17]byte var z9059 [1 << 17]byte var z9060 [1 << 17]byte var z9061 [1 << 17]byte var z9062 [1 << 17]byte var z9063 [1 << 17]byte var z9064 [1 << 17]byte var z9065 [1 << 17]byte var z9066 [1 << 17]byte var z9067 [1 << 17]byte var z9068 [1 << 17]byte var z9069 [1 << 17]byte var z9070 [1 << 17]byte var z9071 [1 << 17]byte var z9072 [1 << 17]byte var z9073 [1 << 17]byte var z9074 [1 << 17]byte var z9075 [1 << 17]byte var z9076 [1 << 17]byte var z9077 [1 << 17]byte var z9078 [1 << 17]byte var z9079 [1 << 17]byte var z9080 [1 << 17]byte var z9081 [1 << 17]byte var z9082 [1 << 17]byte var z9083 [1 << 17]byte var z9084 [1 << 17]byte var z9085 [1 << 17]byte var z9086 [1 << 17]byte var z9087 [1 << 17]byte var z9088 [1 << 17]byte var z9089 [1 << 17]byte var z9090 [1 << 17]byte var z9091 [1 << 17]byte var z9092 [1 << 17]byte var z9093 [1 << 17]byte var z9094 [1 << 17]byte var z9095 [1 << 17]byte var z9096 [1 << 17]byte var z9097 [1 << 17]byte var z9098 [1 << 17]byte var z9099 [1 << 17]byte var z9100 [1 << 17]byte var z9101 [1 << 17]byte var z9102 [1 << 17]byte var z9103 [1 << 17]byte var z9104 [1 << 17]byte var z9105 [1 << 17]byte var z9106 [1 << 17]byte var z9107 [1 << 17]byte var z9108 [1 << 17]byte var z9109 [1 << 17]byte var z9110 [1 << 17]byte var z9111 [1 << 17]byte var z9112 [1 << 17]byte var z9113 [1 << 17]byte var z9114 [1 << 17]byte var z9115 [1 << 17]byte var z9116 [1 << 17]byte var z9117 [1 << 17]byte var z9118 [1 << 17]byte var z9119 [1 << 17]byte var z9120 [1 << 17]byte var z9121 [1 << 17]byte var z9122 [1 << 17]byte var z9123 [1 << 17]byte var z9124 [1 << 17]byte var z9125 [1 << 17]byte var z9126 [1 << 17]byte var z9127 [1 << 17]byte var z9128 [1 << 17]byte var z9129 [1 << 17]byte var z9130 [1 << 17]byte var z9131 [1 << 17]byte var z9132 [1 << 17]byte var z9133 [1 << 17]byte var z9134 [1 << 17]byte var z9135 [1 << 17]byte var z9136 [1 << 17]byte var z9137 [1 << 17]byte var z9138 [1 << 17]byte var z9139 [1 << 17]byte var z9140 [1 << 17]byte var z9141 [1 << 17]byte var z9142 [1 << 17]byte var z9143 [1 << 17]byte var z9144 [1 << 17]byte var z9145 [1 << 17]byte var z9146 [1 << 17]byte var z9147 [1 << 17]byte var z9148 [1 << 17]byte var z9149 [1 << 17]byte var z9150 [1 << 17]byte var z9151 [1 << 17]byte var z9152 [1 << 17]byte var z9153 [1 << 17]byte var z9154 [1 << 17]byte var z9155 [1 << 17]byte var z9156 [1 << 17]byte var z9157 [1 << 17]byte var z9158 [1 << 17]byte var z9159 [1 << 17]byte var z9160 [1 << 17]byte var z9161 [1 << 17]byte var z9162 [1 << 17]byte var z9163 [1 << 17]byte var z9164 [1 << 17]byte var z9165 [1 << 17]byte var z9166 [1 << 17]byte var z9167 [1 << 17]byte var z9168 [1 << 17]byte var z9169 [1 << 17]byte var z9170 [1 << 17]byte var z9171 [1 << 17]byte var z9172 [1 << 17]byte var z9173 [1 << 17]byte var z9174 [1 << 17]byte var z9175 [1 << 17]byte var z9176 [1 << 17]byte var z9177 [1 << 17]byte var z9178 [1 << 17]byte var z9179 [1 << 17]byte var z9180 [1 << 17]byte var z9181 [1 << 17]byte var z9182 [1 << 17]byte var z9183 [1 << 17]byte var z9184 [1 << 17]byte var z9185 [1 << 17]byte var z9186 [1 << 17]byte var z9187 [1 << 17]byte var z9188 [1 << 17]byte var z9189 [1 << 17]byte var z9190 [1 << 17]byte var z9191 [1 << 17]byte var z9192 [1 << 17]byte var z9193 [1 << 17]byte var z9194 [1 << 17]byte var z9195 [1 << 17]byte var z9196 [1 << 17]byte var z9197 [1 << 17]byte var z9198 [1 << 17]byte var z9199 [1 << 17]byte var z9200 [1 << 17]byte var z9201 [1 << 17]byte var z9202 [1 << 17]byte var z9203 [1 << 17]byte var z9204 [1 << 17]byte var z9205 [1 << 17]byte var z9206 [1 << 17]byte var z9207 [1 << 17]byte var z9208 [1 << 17]byte var z9209 [1 << 17]byte var z9210 [1 << 17]byte var z9211 [1 << 17]byte var z9212 [1 << 17]byte var z9213 [1 << 17]byte var z9214 [1 << 17]byte var z9215 [1 << 17]byte var z9216 [1 << 17]byte var z9217 [1 << 17]byte var z9218 [1 << 17]byte var z9219 [1 << 17]byte var z9220 [1 << 17]byte var z9221 [1 << 17]byte var z9222 [1 << 17]byte var z9223 [1 << 17]byte var z9224 [1 << 17]byte var z9225 [1 << 17]byte var z9226 [1 << 17]byte var z9227 [1 << 17]byte var z9228 [1 << 17]byte var z9229 [1 << 17]byte var z9230 [1 << 17]byte var z9231 [1 << 17]byte var z9232 [1 << 17]byte var z9233 [1 << 17]byte var z9234 [1 << 17]byte var z9235 [1 << 17]byte var z9236 [1 << 17]byte var z9237 [1 << 17]byte var z9238 [1 << 17]byte var z9239 [1 << 17]byte var z9240 [1 << 17]byte var z9241 [1 << 17]byte var z9242 [1 << 17]byte var z9243 [1 << 17]byte var z9244 [1 << 17]byte var z9245 [1 << 17]byte var z9246 [1 << 17]byte var z9247 [1 << 17]byte var z9248 [1 << 17]byte var z9249 [1 << 17]byte var z9250 [1 << 17]byte var z9251 [1 << 17]byte var z9252 [1 << 17]byte var z9253 [1 << 17]byte var z9254 [1 << 17]byte var z9255 [1 << 17]byte var z9256 [1 << 17]byte var z9257 [1 << 17]byte var z9258 [1 << 17]byte var z9259 [1 << 17]byte var z9260 [1 << 17]byte var z9261 [1 << 17]byte var z9262 [1 << 17]byte var z9263 [1 << 17]byte var z9264 [1 << 17]byte var z9265 [1 << 17]byte var z9266 [1 << 17]byte var z9267 [1 << 17]byte var z9268 [1 << 17]byte var z9269 [1 << 17]byte var z9270 [1 << 17]byte var z9271 [1 << 17]byte var z9272 [1 << 17]byte var z9273 [1 << 17]byte var z9274 [1 << 17]byte var z9275 [1 << 17]byte var z9276 [1 << 17]byte var z9277 [1 << 17]byte var z9278 [1 << 17]byte var z9279 [1 << 17]byte var z9280 [1 << 17]byte var z9281 [1 << 17]byte var z9282 [1 << 17]byte var z9283 [1 << 17]byte var z9284 [1 << 17]byte var z9285 [1 << 17]byte var z9286 [1 << 17]byte var z9287 [1 << 17]byte var z9288 [1 << 17]byte var z9289 [1 << 17]byte var z9290 [1 << 17]byte var z9291 [1 << 17]byte var z9292 [1 << 17]byte var z9293 [1 << 17]byte var z9294 [1 << 17]byte var z9295 [1 << 17]byte var z9296 [1 << 17]byte var z9297 [1 << 17]byte var z9298 [1 << 17]byte var z9299 [1 << 17]byte var z9300 [1 << 17]byte var z9301 [1 << 17]byte var z9302 [1 << 17]byte var z9303 [1 << 17]byte var z9304 [1 << 17]byte var z9305 [1 << 17]byte var z9306 [1 << 17]byte var z9307 [1 << 17]byte var z9308 [1 << 17]byte var z9309 [1 << 17]byte var z9310 [1 << 17]byte var z9311 [1 << 17]byte var z9312 [1 << 17]byte var z9313 [1 << 17]byte var z9314 [1 << 17]byte var z9315 [1 << 17]byte var z9316 [1 << 17]byte var z9317 [1 << 17]byte var z9318 [1 << 17]byte var z9319 [1 << 17]byte var z9320 [1 << 17]byte var z9321 [1 << 17]byte var z9322 [1 << 17]byte var z9323 [1 << 17]byte var z9324 [1 << 17]byte var z9325 [1 << 17]byte var z9326 [1 << 17]byte var z9327 [1 << 17]byte var z9328 [1 << 17]byte var z9329 [1 << 17]byte var z9330 [1 << 17]byte var z9331 [1 << 17]byte var z9332 [1 << 17]byte var z9333 [1 << 17]byte var z9334 [1 << 17]byte var z9335 [1 << 17]byte var z9336 [1 << 17]byte var z9337 [1 << 17]byte var z9338 [1 << 17]byte var z9339 [1 << 17]byte var z9340 [1 << 17]byte var z9341 [1 << 17]byte var z9342 [1 << 17]byte var z9343 [1 << 17]byte var z9344 [1 << 17]byte var z9345 [1 << 17]byte var z9346 [1 << 17]byte var z9347 [1 << 17]byte var z9348 [1 << 17]byte var z9349 [1 << 17]byte var z9350 [1 << 17]byte var z9351 [1 << 17]byte var z9352 [1 << 17]byte var z9353 [1 << 17]byte var z9354 [1 << 17]byte var z9355 [1 << 17]byte var z9356 [1 << 17]byte var z9357 [1 << 17]byte var z9358 [1 << 17]byte var z9359 [1 << 17]byte var z9360 [1 << 17]byte var z9361 [1 << 17]byte var z9362 [1 << 17]byte var z9363 [1 << 17]byte var z9364 [1 << 17]byte var z9365 [1 << 17]byte var z9366 [1 << 17]byte var z9367 [1 << 17]byte var z9368 [1 << 17]byte var z9369 [1 << 17]byte var z9370 [1 << 17]byte var z9371 [1 << 17]byte var z9372 [1 << 17]byte var z9373 [1 << 17]byte var z9374 [1 << 17]byte var z9375 [1 << 17]byte var z9376 [1 << 17]byte var z9377 [1 << 17]byte var z9378 [1 << 17]byte var z9379 [1 << 17]byte var z9380 [1 << 17]byte var z9381 [1 << 17]byte var z9382 [1 << 17]byte var z9383 [1 << 17]byte var z9384 [1 << 17]byte var z9385 [1 << 17]byte var z9386 [1 << 17]byte var z9387 [1 << 17]byte var z9388 [1 << 17]byte var z9389 [1 << 17]byte var z9390 [1 << 17]byte var z9391 [1 << 17]byte var z9392 [1 << 17]byte var z9393 [1 << 17]byte var z9394 [1 << 17]byte var z9395 [1 << 17]byte var z9396 [1 << 17]byte var z9397 [1 << 17]byte var z9398 [1 << 17]byte var z9399 [1 << 17]byte var z9400 [1 << 17]byte var z9401 [1 << 17]byte var z9402 [1 << 17]byte var z9403 [1 << 17]byte var z9404 [1 << 17]byte var z9405 [1 << 17]byte var z9406 [1 << 17]byte var z9407 [1 << 17]byte var z9408 [1 << 17]byte var z9409 [1 << 17]byte var z9410 [1 << 17]byte var z9411 [1 << 17]byte var z9412 [1 << 17]byte var z9413 [1 << 17]byte var z9414 [1 << 17]byte var z9415 [1 << 17]byte var z9416 [1 << 17]byte var z9417 [1 << 17]byte var z9418 [1 << 17]byte var z9419 [1 << 17]byte var z9420 [1 << 17]byte var z9421 [1 << 17]byte var z9422 [1 << 17]byte var z9423 [1 << 17]byte var z9424 [1 << 17]byte var z9425 [1 << 17]byte var z9426 [1 << 17]byte var z9427 [1 << 17]byte var z9428 [1 << 17]byte var z9429 [1 << 17]byte var z9430 [1 << 17]byte var z9431 [1 << 17]byte var z9432 [1 << 17]byte var z9433 [1 << 17]byte var z9434 [1 << 17]byte var z9435 [1 << 17]byte var z9436 [1 << 17]byte var z9437 [1 << 17]byte var z9438 [1 << 17]byte var z9439 [1 << 17]byte var z9440 [1 << 17]byte var z9441 [1 << 17]byte var z9442 [1 << 17]byte var z9443 [1 << 17]byte var z9444 [1 << 17]byte var z9445 [1 << 17]byte var z9446 [1 << 17]byte var z9447 [1 << 17]byte var z9448 [1 << 17]byte var z9449 [1 << 17]byte var z9450 [1 << 17]byte var z9451 [1 << 17]byte var z9452 [1 << 17]byte var z9453 [1 << 17]byte var z9454 [1 << 17]byte var z9455 [1 << 17]byte var z9456 [1 << 17]byte var z9457 [1 << 17]byte var z9458 [1 << 17]byte var z9459 [1 << 17]byte var z9460 [1 << 17]byte var z9461 [1 << 17]byte var z9462 [1 << 17]byte var z9463 [1 << 17]byte var z9464 [1 << 17]byte var z9465 [1 << 17]byte var z9466 [1 << 17]byte var z9467 [1 << 17]byte var z9468 [1 << 17]byte var z9469 [1 << 17]byte var z9470 [1 << 17]byte var z9471 [1 << 17]byte var z9472 [1 << 17]byte var z9473 [1 << 17]byte var z9474 [1 << 17]byte var z9475 [1 << 17]byte var z9476 [1 << 17]byte var z9477 [1 << 17]byte var z9478 [1 << 17]byte var z9479 [1 << 17]byte var z9480 [1 << 17]byte var z9481 [1 << 17]byte var z9482 [1 << 17]byte var z9483 [1 << 17]byte var z9484 [1 << 17]byte var z9485 [1 << 17]byte var z9486 [1 << 17]byte var z9487 [1 << 17]byte var z9488 [1 << 17]byte var z9489 [1 << 17]byte var z9490 [1 << 17]byte var z9491 [1 << 17]byte var z9492 [1 << 17]byte var z9493 [1 << 17]byte var z9494 [1 << 17]byte var z9495 [1 << 17]byte var z9496 [1 << 17]byte var z9497 [1 << 17]byte var z9498 [1 << 17]byte var z9499 [1 << 17]byte var z9500 [1 << 17]byte var z9501 [1 << 17]byte var z9502 [1 << 17]byte var z9503 [1 << 17]byte var z9504 [1 << 17]byte var z9505 [1 << 17]byte var z9506 [1 << 17]byte var z9507 [1 << 17]byte var z9508 [1 << 17]byte var z9509 [1 << 17]byte var z9510 [1 << 17]byte var z9511 [1 << 17]byte var z9512 [1 << 17]byte var z9513 [1 << 17]byte var z9514 [1 << 17]byte var z9515 [1 << 17]byte var z9516 [1 << 17]byte var z9517 [1 << 17]byte var z9518 [1 << 17]byte var z9519 [1 << 17]byte var z9520 [1 << 17]byte var z9521 [1 << 17]byte var z9522 [1 << 17]byte var z9523 [1 << 17]byte var z9524 [1 << 17]byte var z9525 [1 << 17]byte var z9526 [1 << 17]byte var z9527 [1 << 17]byte var z9528 [1 << 17]byte var z9529 [1 << 17]byte var z9530 [1 << 17]byte var z9531 [1 << 17]byte var z9532 [1 << 17]byte var z9533 [1 << 17]byte var z9534 [1 << 17]byte var z9535 [1 << 17]byte var z9536 [1 << 17]byte var z9537 [1 << 17]byte var z9538 [1 << 17]byte var z9539 [1 << 17]byte var z9540 [1 << 17]byte var z9541 [1 << 17]byte var z9542 [1 << 17]byte var z9543 [1 << 17]byte var z9544 [1 << 17]byte var z9545 [1 << 17]byte var z9546 [1 << 17]byte var z9547 [1 << 17]byte var z9548 [1 << 17]byte var z9549 [1 << 17]byte var z9550 [1 << 17]byte var z9551 [1 << 17]byte var z9552 [1 << 17]byte var z9553 [1 << 17]byte var z9554 [1 << 17]byte var z9555 [1 << 17]byte var z9556 [1 << 17]byte var z9557 [1 << 17]byte var z9558 [1 << 17]byte var z9559 [1 << 17]byte var z9560 [1 << 17]byte var z9561 [1 << 17]byte var z9562 [1 << 17]byte var z9563 [1 << 17]byte var z9564 [1 << 17]byte var z9565 [1 << 17]byte var z9566 [1 << 17]byte var z9567 [1 << 17]byte var z9568 [1 << 17]byte var z9569 [1 << 17]byte var z9570 [1 << 17]byte var z9571 [1 << 17]byte var z9572 [1 << 17]byte var z9573 [1 << 17]byte var z9574 [1 << 17]byte var z9575 [1 << 17]byte var z9576 [1 << 17]byte var z9577 [1 << 17]byte var z9578 [1 << 17]byte var z9579 [1 << 17]byte var z9580 [1 << 17]byte var z9581 [1 << 17]byte var z9582 [1 << 17]byte var z9583 [1 << 17]byte var z9584 [1 << 17]byte var z9585 [1 << 17]byte var z9586 [1 << 17]byte var z9587 [1 << 17]byte var z9588 [1 << 17]byte var z9589 [1 << 17]byte var z9590 [1 << 17]byte var z9591 [1 << 17]byte var z9592 [1 << 17]byte var z9593 [1 << 17]byte var z9594 [1 << 17]byte var z9595 [1 << 17]byte var z9596 [1 << 17]byte var z9597 [1 << 17]byte var z9598 [1 << 17]byte var z9599 [1 << 17]byte var z9600 [1 << 17]byte var z9601 [1 << 17]byte var z9602 [1 << 17]byte var z9603 [1 << 17]byte var z9604 [1 << 17]byte var z9605 [1 << 17]byte var z9606 [1 << 17]byte var z9607 [1 << 17]byte var z9608 [1 << 17]byte var z9609 [1 << 17]byte var z9610 [1 << 17]byte var z9611 [1 << 17]byte var z9612 [1 << 17]byte var z9613 [1 << 17]byte var z9614 [1 << 17]byte var z9615 [1 << 17]byte var z9616 [1 << 17]byte var z9617 [1 << 17]byte var z9618 [1 << 17]byte var z9619 [1 << 17]byte var z9620 [1 << 17]byte var z9621 [1 << 17]byte var z9622 [1 << 17]byte var z9623 [1 << 17]byte var z9624 [1 << 17]byte var z9625 [1 << 17]byte var z9626 [1 << 17]byte var z9627 [1 << 17]byte var z9628 [1 << 17]byte var z9629 [1 << 17]byte var z9630 [1 << 17]byte var z9631 [1 << 17]byte var z9632 [1 << 17]byte var z9633 [1 << 17]byte var z9634 [1 << 17]byte var z9635 [1 << 17]byte var z9636 [1 << 17]byte var z9637 [1 << 17]byte var z9638 [1 << 17]byte var z9639 [1 << 17]byte var z9640 [1 << 17]byte var z9641 [1 << 17]byte var z9642 [1 << 17]byte var z9643 [1 << 17]byte var z9644 [1 << 17]byte var z9645 [1 << 17]byte var z9646 [1 << 17]byte var z9647 [1 << 17]byte var z9648 [1 << 17]byte var z9649 [1 << 17]byte var z9650 [1 << 17]byte var z9651 [1 << 17]byte var z9652 [1 << 17]byte var z9653 [1 << 17]byte var z9654 [1 << 17]byte var z9655 [1 << 17]byte var z9656 [1 << 17]byte var z9657 [1 << 17]byte var z9658 [1 << 17]byte var z9659 [1 << 17]byte var z9660 [1 << 17]byte var z9661 [1 << 17]byte var z9662 [1 << 17]byte var z9663 [1 << 17]byte var z9664 [1 << 17]byte var z9665 [1 << 17]byte var z9666 [1 << 17]byte var z9667 [1 << 17]byte var z9668 [1 << 17]byte var z9669 [1 << 17]byte var z9670 [1 << 17]byte var z9671 [1 << 17]byte var z9672 [1 << 17]byte var z9673 [1 << 17]byte var z9674 [1 << 17]byte var z9675 [1 << 17]byte var z9676 [1 << 17]byte var z9677 [1 << 17]byte var z9678 [1 << 17]byte var z9679 [1 << 17]byte var z9680 [1 << 17]byte var z9681 [1 << 17]byte var z9682 [1 << 17]byte var z9683 [1 << 17]byte var z9684 [1 << 17]byte var z9685 [1 << 17]byte var z9686 [1 << 17]byte var z9687 [1 << 17]byte var z9688 [1 << 17]byte var z9689 [1 << 17]byte var z9690 [1 << 17]byte var z9691 [1 << 17]byte var z9692 [1 << 17]byte var z9693 [1 << 17]byte var z9694 [1 << 17]byte var z9695 [1 << 17]byte var z9696 [1 << 17]byte var z9697 [1 << 17]byte var z9698 [1 << 17]byte var z9699 [1 << 17]byte var z9700 [1 << 17]byte var z9701 [1 << 17]byte var z9702 [1 << 17]byte var z9703 [1 << 17]byte var z9704 [1 << 17]byte var z9705 [1 << 17]byte var z9706 [1 << 17]byte var z9707 [1 << 17]byte var z9708 [1 << 17]byte var z9709 [1 << 17]byte var z9710 [1 << 17]byte var z9711 [1 << 17]byte var z9712 [1 << 17]byte var z9713 [1 << 17]byte var z9714 [1 << 17]byte var z9715 [1 << 17]byte var z9716 [1 << 17]byte var z9717 [1 << 17]byte var z9718 [1 << 17]byte var z9719 [1 << 17]byte var z9720 [1 << 17]byte var z9721 [1 << 17]byte var z9722 [1 << 17]byte var z9723 [1 << 17]byte var z9724 [1 << 17]byte var z9725 [1 << 17]byte var z9726 [1 << 17]byte var z9727 [1 << 17]byte var z9728 [1 << 17]byte var z9729 [1 << 17]byte var z9730 [1 << 17]byte var z9731 [1 << 17]byte var z9732 [1 << 17]byte var z9733 [1 << 17]byte var z9734 [1 << 17]byte var z9735 [1 << 17]byte var z9736 [1 << 17]byte var z9737 [1 << 17]byte var z9738 [1 << 17]byte var z9739 [1 << 17]byte var z9740 [1 << 17]byte var z9741 [1 << 17]byte var z9742 [1 << 17]byte var z9743 [1 << 17]byte var z9744 [1 << 17]byte var z9745 [1 << 17]byte var z9746 [1 << 17]byte var z9747 [1 << 17]byte var z9748 [1 << 17]byte var z9749 [1 << 17]byte var z9750 [1 << 17]byte var z9751 [1 << 17]byte var z9752 [1 << 17]byte var z9753 [1 << 17]byte var z9754 [1 << 17]byte var z9755 [1 << 17]byte var z9756 [1 << 17]byte var z9757 [1 << 17]byte var z9758 [1 << 17]byte var z9759 [1 << 17]byte var z9760 [1 << 17]byte var z9761 [1 << 17]byte var z9762 [1 << 17]byte var z9763 [1 << 17]byte var z9764 [1 << 17]byte var z9765 [1 << 17]byte var z9766 [1 << 17]byte var z9767 [1 << 17]byte var z9768 [1 << 17]byte var z9769 [1 << 17]byte var z9770 [1 << 17]byte var z9771 [1 << 17]byte var z9772 [1 << 17]byte var z9773 [1 << 17]byte var z9774 [1 << 17]byte var z9775 [1 << 17]byte var z9776 [1 << 17]byte var z9777 [1 << 17]byte var z9778 [1 << 17]byte var z9779 [1 << 17]byte var z9780 [1 << 17]byte var z9781 [1 << 17]byte var z9782 [1 << 17]byte var z9783 [1 << 17]byte var z9784 [1 << 17]byte var z9785 [1 << 17]byte var z9786 [1 << 17]byte var z9787 [1 << 17]byte var z9788 [1 << 17]byte var z9789 [1 << 17]byte var z9790 [1 << 17]byte var z9791 [1 << 17]byte var z9792 [1 << 17]byte var z9793 [1 << 17]byte var z9794 [1 << 17]byte var z9795 [1 << 17]byte var z9796 [1 << 17]byte var z9797 [1 << 17]byte var z9798 [1 << 17]byte var z9799 [1 << 17]byte var z9800 [1 << 17]byte var z9801 [1 << 17]byte var z9802 [1 << 17]byte var z9803 [1 << 17]byte var z9804 [1 << 17]byte var z9805 [1 << 17]byte var z9806 [1 << 17]byte var z9807 [1 << 17]byte var z9808 [1 << 17]byte var z9809 [1 << 17]byte var z9810 [1 << 17]byte var z9811 [1 << 17]byte var z9812 [1 << 17]byte var z9813 [1 << 17]byte var z9814 [1 << 17]byte var z9815 [1 << 17]byte var z9816 [1 << 17]byte var z9817 [1 << 17]byte var z9818 [1 << 17]byte var z9819 [1 << 17]byte var z9820 [1 << 17]byte var z9821 [1 << 17]byte var z9822 [1 << 17]byte var z9823 [1 << 17]byte var z9824 [1 << 17]byte var z9825 [1 << 17]byte var z9826 [1 << 17]byte var z9827 [1 << 17]byte var z9828 [1 << 17]byte var z9829 [1 << 17]byte var z9830 [1 << 17]byte var z9831 [1 << 17]byte var z9832 [1 << 17]byte var z9833 [1 << 17]byte var z9834 [1 << 17]byte var z9835 [1 << 17]byte var z9836 [1 << 17]byte var z9837 [1 << 17]byte var z9838 [1 << 17]byte var z9839 [1 << 17]byte var z9840 [1 << 17]byte var z9841 [1 << 17]byte var z9842 [1 << 17]byte var z9843 [1 << 17]byte var z9844 [1 << 17]byte var z9845 [1 << 17]byte var z9846 [1 << 17]byte var z9847 [1 << 17]byte var z9848 [1 << 17]byte var z9849 [1 << 17]byte var z9850 [1 << 17]byte var z9851 [1 << 17]byte var z9852 [1 << 17]byte var z9853 [1 << 17]byte var z9854 [1 << 17]byte var z9855 [1 << 17]byte var z9856 [1 << 17]byte var z9857 [1 << 17]byte var z9858 [1 << 17]byte var z9859 [1 << 17]byte var z9860 [1 << 17]byte var z9861 [1 << 17]byte var z9862 [1 << 17]byte var z9863 [1 << 17]byte var z9864 [1 << 17]byte var z9865 [1 << 17]byte var z9866 [1 << 17]byte var z9867 [1 << 17]byte var z9868 [1 << 17]byte var z9869 [1 << 17]byte var z9870 [1 << 17]byte var z9871 [1 << 17]byte var z9872 [1 << 17]byte var z9873 [1 << 17]byte var z9874 [1 << 17]byte var z9875 [1 << 17]byte var z9876 [1 << 17]byte var z9877 [1 << 17]byte var z9878 [1 << 17]byte var z9879 [1 << 17]byte var z9880 [1 << 17]byte var z9881 [1 << 17]byte var z9882 [1 << 17]byte var z9883 [1 << 17]byte var z9884 [1 << 17]byte var z9885 [1 << 17]byte var z9886 [1 << 17]byte var z9887 [1 << 17]byte var z9888 [1 << 17]byte var z9889 [1 << 17]byte var z9890 [1 << 17]byte var z9891 [1 << 17]byte var z9892 [1 << 17]byte var z9893 [1 << 17]byte var z9894 [1 << 17]byte var z9895 [1 << 17]byte var z9896 [1 << 17]byte var z9897 [1 << 17]byte var z9898 [1 << 17]byte var z9899 [1 << 17]byte var z9900 [1 << 17]byte var z9901 [1 << 17]byte var z9902 [1 << 17]byte var z9903 [1 << 17]byte var z9904 [1 << 17]byte var z9905 [1 << 17]byte var z9906 [1 << 17]byte var z9907 [1 << 17]byte var z9908 [1 << 17]byte var z9909 [1 << 17]byte var z9910 [1 << 17]byte var z9911 [1 << 17]byte var z9912 [1 << 17]byte var z9913 [1 << 17]byte var z9914 [1 << 17]byte var z9915 [1 << 17]byte var z9916 [1 << 17]byte var z9917 [1 << 17]byte var z9918 [1 << 17]byte var z9919 [1 << 17]byte var z9920 [1 << 17]byte var z9921 [1 << 17]byte var z9922 [1 << 17]byte var z9923 [1 << 17]byte var z9924 [1 << 17]byte var z9925 [1 << 17]byte var z9926 [1 << 17]byte var z9927 [1 << 17]byte var z9928 [1 << 17]byte var z9929 [1 << 17]byte var z9930 [1 << 17]byte var z9931 [1 << 17]byte var z9932 [1 << 17]byte var z9933 [1 << 17]byte var z9934 [1 << 17]byte var z9935 [1 << 17]byte var z9936 [1 << 17]byte var z9937 [1 << 17]byte var z9938 [1 << 17]byte var z9939 [1 << 17]byte var z9940 [1 << 17]byte var z9941 [1 << 17]byte var z9942 [1 << 17]byte var z9943 [1 << 17]byte var z9944 [1 << 17]byte var z9945 [1 << 17]byte var z9946 [1 << 17]byte var z9947 [1 << 17]byte var z9948 [1 << 17]byte var z9949 [1 << 17]byte var z9950 [1 << 17]byte var z9951 [1 << 17]byte var z9952 [1 << 17]byte var z9953 [1 << 17]byte var z9954 [1 << 17]byte var z9955 [1 << 17]byte var z9956 [1 << 17]byte var z9957 [1 << 17]byte var z9958 [1 << 17]byte var z9959 [1 << 17]byte var z9960 [1 << 17]byte var z9961 [1 << 17]byte var z9962 [1 << 17]byte var z9963 [1 << 17]byte var z9964 [1 << 17]byte var z9965 [1 << 17]byte var z9966 [1 << 17]byte var z9967 [1 << 17]byte var z9968 [1 << 17]byte var z9969 [1 << 17]byte var z9970 [1 << 17]byte var z9971 [1 << 17]byte var z9972 [1 << 17]byte var z9973 [1 << 17]byte var z9974 [1 << 17]byte var z9975 [1 << 17]byte var z9976 [1 << 17]byte var z9977 [1 << 17]byte var z9978 [1 << 17]byte var z9979 [1 << 17]byte var z9980 [1 << 17]byte var z9981 [1 << 17]byte var z9982 [1 << 17]byte var z9983 [1 << 17]byte var z9984 [1 << 17]byte var z9985 [1 << 17]byte var z9986 [1 << 17]byte var z9987 [1 << 17]byte var z9988 [1 << 17]byte var z9989 [1 << 17]byte var z9990 [1 << 17]byte var z9991 [1 << 17]byte var z9992 [1 << 17]byte var z9993 [1 << 17]byte var z9994 [1 << 17]byte var z9995 [1 << 17]byte var z9996 [1 << 17]byte var z9997 [1 << 17]byte var z9998 [1 << 17]byte var z9999 [1 << 17]byte var z10000 [1 << 17]byte var z10001 [1 << 17]byte var z10002 [1 << 17]byte var z10003 [1 << 17]byte var z10004 [1 << 17]byte var z10005 [1 << 17]byte var z10006 [1 << 17]byte var z10007 [1 << 17]byte var z10008 [1 << 17]byte var z10009 [1 << 17]byte var z10010 [1 << 17]byte var z10011 [1 << 17]byte var z10012 [1 << 17]byte var z10013 [1 << 17]byte var z10014 [1 << 17]byte var z10015 [1 << 17]byte var z10016 [1 << 17]byte var z10017 [1 << 17]byte var z10018 [1 << 17]byte var z10019 [1 << 17]byte var z10020 [1 << 17]byte var z10021 [1 << 17]byte var z10022 [1 << 17]byte var z10023 [1 << 17]byte var z10024 [1 << 17]byte var z10025 [1 << 17]byte var z10026 [1 << 17]byte var z10027 [1 << 17]byte var z10028 [1 << 17]byte var z10029 [1 << 17]byte var z10030 [1 << 17]byte var z10031 [1 << 17]byte var z10032 [1 << 17]byte var z10033 [1 << 17]byte var z10034 [1 << 17]byte var z10035 [1 << 17]byte var z10036 [1 << 17]byte var z10037 [1 << 17]byte var z10038 [1 << 17]byte var z10039 [1 << 17]byte var z10040 [1 << 17]byte var z10041 [1 << 17]byte var z10042 [1 << 17]byte var z10043 [1 << 17]byte var z10044 [1 << 17]byte var z10045 [1 << 17]byte var z10046 [1 << 17]byte var z10047 [1 << 17]byte var z10048 [1 << 17]byte var z10049 [1 << 17]byte var z10050 [1 << 17]byte var z10051 [1 << 17]byte var z10052 [1 << 17]byte var z10053 [1 << 17]byte var z10054 [1 << 17]byte var z10055 [1 << 17]byte var z10056 [1 << 17]byte var z10057 [1 << 17]byte var z10058 [1 << 17]byte var z10059 [1 << 17]byte var z10060 [1 << 17]byte var z10061 [1 << 17]byte var z10062 [1 << 17]byte var z10063 [1 << 17]byte var z10064 [1 << 17]byte var z10065 [1 << 17]byte var z10066 [1 << 17]byte var z10067 [1 << 17]byte var z10068 [1 << 17]byte var z10069 [1 << 17]byte var z10070 [1 << 17]byte var z10071 [1 << 17]byte var z10072 [1 << 17]byte var z10073 [1 << 17]byte var z10074 [1 << 17]byte var z10075 [1 << 17]byte var z10076 [1 << 17]byte var z10077 [1 << 17]byte var z10078 [1 << 17]byte var z10079 [1 << 17]byte var z10080 [1 << 17]byte var z10081 [1 << 17]byte var z10082 [1 << 17]byte var z10083 [1 << 17]byte var z10084 [1 << 17]byte var z10085 [1 << 17]byte var z10086 [1 << 17]byte var z10087 [1 << 17]byte var z10088 [1 << 17]byte var z10089 [1 << 17]byte var z10090 [1 << 17]byte var z10091 [1 << 17]byte var z10092 [1 << 17]byte var z10093 [1 << 17]byte var z10094 [1 << 17]byte var z10095 [1 << 17]byte var z10096 [1 << 17]byte var z10097 [1 << 17]byte var z10098 [1 << 17]byte var z10099 [1 << 17]byte var z10100 [1 << 17]byte var z10101 [1 << 17]byte var z10102 [1 << 17]byte var z10103 [1 << 17]byte var z10104 [1 << 17]byte var z10105 [1 << 17]byte var z10106 [1 << 17]byte var z10107 [1 << 17]byte var z10108 [1 << 17]byte var z10109 [1 << 17]byte var z10110 [1 << 17]byte var z10111 [1 << 17]byte var z10112 [1 << 17]byte var z10113 [1 << 17]byte var z10114 [1 << 17]byte var z10115 [1 << 17]byte var z10116 [1 << 17]byte var z10117 [1 << 17]byte var z10118 [1 << 17]byte var z10119 [1 << 17]byte var z10120 [1 << 17]byte var z10121 [1 << 17]byte var z10122 [1 << 17]byte var z10123 [1 << 17]byte var z10124 [1 << 17]byte var z10125 [1 << 17]byte var z10126 [1 << 17]byte var z10127 [1 << 17]byte var z10128 [1 << 17]byte var z10129 [1 << 17]byte var z10130 [1 << 17]byte var z10131 [1 << 17]byte var z10132 [1 << 17]byte var z10133 [1 << 17]byte var z10134 [1 << 17]byte var z10135 [1 << 17]byte var z10136 [1 << 17]byte var z10137 [1 << 17]byte var z10138 [1 << 17]byte var z10139 [1 << 17]byte var z10140 [1 << 17]byte var z10141 [1 << 17]byte var z10142 [1 << 17]byte var z10143 [1 << 17]byte var z10144 [1 << 17]byte var z10145 [1 << 17]byte var z10146 [1 << 17]byte var z10147 [1 << 17]byte var z10148 [1 << 17]byte var z10149 [1 << 17]byte var z10150 [1 << 17]byte var z10151 [1 << 17]byte var z10152 [1 << 17]byte var z10153 [1 << 17]byte var z10154 [1 << 17]byte var z10155 [1 << 17]byte var z10156 [1 << 17]byte var z10157 [1 << 17]byte var z10158 [1 << 17]byte var z10159 [1 << 17]byte var z10160 [1 << 17]byte var z10161 [1 << 17]byte var z10162 [1 << 17]byte var z10163 [1 << 17]byte var z10164 [1 << 17]byte var z10165 [1 << 17]byte var z10166 [1 << 17]byte var z10167 [1 << 17]byte var z10168 [1 << 17]byte var z10169 [1 << 17]byte var z10170 [1 << 17]byte var z10171 [1 << 17]byte var z10172 [1 << 17]byte var z10173 [1 << 17]byte var z10174 [1 << 17]byte var z10175 [1 << 17]byte var z10176 [1 << 17]byte var z10177 [1 << 17]byte var z10178 [1 << 17]byte var z10179 [1 << 17]byte var z10180 [1 << 17]byte var z10181 [1 << 17]byte var z10182 [1 << 17]byte var z10183 [1 << 17]byte var z10184 [1 << 17]byte var z10185 [1 << 17]byte var z10186 [1 << 17]byte var z10187 [1 << 17]byte var z10188 [1 << 17]byte var z10189 [1 << 17]byte var z10190 [1 << 17]byte var z10191 [1 << 17]byte var z10192 [1 << 17]byte var z10193 [1 << 17]byte var z10194 [1 << 17]byte var z10195 [1 << 17]byte var z10196 [1 << 17]byte var z10197 [1 << 17]byte var z10198 [1 << 17]byte var z10199 [1 << 17]byte var z10200 [1 << 17]byte var z10201 [1 << 17]byte var z10202 [1 << 17]byte var z10203 [1 << 17]byte var z10204 [1 << 17]byte var z10205 [1 << 17]byte var z10206 [1 << 17]byte var z10207 [1 << 17]byte var z10208 [1 << 17]byte var z10209 [1 << 17]byte var z10210 [1 << 17]byte var z10211 [1 << 17]byte var z10212 [1 << 17]byte var z10213 [1 << 17]byte var z10214 [1 << 17]byte var z10215 [1 << 17]byte var z10216 [1 << 17]byte var z10217 [1 << 17]byte var z10218 [1 << 17]byte var z10219 [1 << 17]byte var z10220 [1 << 17]byte var z10221 [1 << 17]byte var z10222 [1 << 17]byte var z10223 [1 << 17]byte var z10224 [1 << 17]byte var z10225 [1 << 17]byte var z10226 [1 << 17]byte var z10227 [1 << 17]byte var z10228 [1 << 17]byte var z10229 [1 << 17]byte var z10230 [1 << 17]byte var z10231 [1 << 17]byte var z10232 [1 << 17]byte var z10233 [1 << 17]byte var z10234 [1 << 17]byte var z10235 [1 << 17]byte var z10236 [1 << 17]byte var z10237 [1 << 17]byte var z10238 [1 << 17]byte var z10239 [1 << 17]byte var z10240 [1 << 17]byte var z10241 [1 << 17]byte var z10242 [1 << 17]byte var z10243 [1 << 17]byte var z10244 [1 << 17]byte var z10245 [1 << 17]byte var z10246 [1 << 17]byte var z10247 [1 << 17]byte var z10248 [1 << 17]byte var z10249 [1 << 17]byte var z10250 [1 << 17]byte var z10251 [1 << 17]byte var z10252 [1 << 17]byte var z10253 [1 << 17]byte var z10254 [1 << 17]byte var z10255 [1 << 17]byte var z10256 [1 << 17]byte var z10257 [1 << 17]byte var z10258 [1 << 17]byte var z10259 [1 << 17]byte var z10260 [1 << 17]byte var z10261 [1 << 17]byte var z10262 [1 << 17]byte var z10263 [1 << 17]byte var z10264 [1 << 17]byte var z10265 [1 << 17]byte var z10266 [1 << 17]byte var z10267 [1 << 17]byte var z10268 [1 << 17]byte var z10269 [1 << 17]byte var z10270 [1 << 17]byte var z10271 [1 << 17]byte var z10272 [1 << 17]byte var z10273 [1 << 17]byte var z10274 [1 << 17]byte var z10275 [1 << 17]byte var z10276 [1 << 17]byte var z10277 [1 << 17]byte var z10278 [1 << 17]byte var z10279 [1 << 17]byte var z10280 [1 << 17]byte var z10281 [1 << 17]byte var z10282 [1 << 17]byte var z10283 [1 << 17]byte var z10284 [1 << 17]byte var z10285 [1 << 17]byte var z10286 [1 << 17]byte var z10287 [1 << 17]byte var z10288 [1 << 17]byte var z10289 [1 << 17]byte var z10290 [1 << 17]byte var z10291 [1 << 17]byte var z10292 [1 << 17]byte var z10293 [1 << 17]byte var z10294 [1 << 17]byte var z10295 [1 << 17]byte var z10296 [1 << 17]byte var z10297 [1 << 17]byte var z10298 [1 << 17]byte var z10299 [1 << 17]byte var z10300 [1 << 17]byte var z10301 [1 << 17]byte var z10302 [1 << 17]byte var z10303 [1 << 17]byte var z10304 [1 << 17]byte var z10305 [1 << 17]byte var z10306 [1 << 17]byte var z10307 [1 << 17]byte var z10308 [1 << 17]byte var z10309 [1 << 17]byte var z10310 [1 << 17]byte var z10311 [1 << 17]byte var z10312 [1 << 17]byte var z10313 [1 << 17]byte var z10314 [1 << 17]byte var z10315 [1 << 17]byte var z10316 [1 << 17]byte var z10317 [1 << 17]byte var z10318 [1 << 17]byte var z10319 [1 << 17]byte var z10320 [1 << 17]byte var z10321 [1 << 17]byte var z10322 [1 << 17]byte var z10323 [1 << 17]byte var z10324 [1 << 17]byte var z10325 [1 << 17]byte var z10326 [1 << 17]byte var z10327 [1 << 17]byte var z10328 [1 << 17]byte var z10329 [1 << 17]byte var z10330 [1 << 17]byte var z10331 [1 << 17]byte var z10332 [1 << 17]byte var z10333 [1 << 17]byte var z10334 [1 << 17]byte var z10335 [1 << 17]byte var z10336 [1 << 17]byte var z10337 [1 << 17]byte var z10338 [1 << 17]byte var z10339 [1 << 17]byte var z10340 [1 << 17]byte var z10341 [1 << 17]byte var z10342 [1 << 17]byte var z10343 [1 << 17]byte var z10344 [1 << 17]byte var z10345 [1 << 17]byte var z10346 [1 << 17]byte var z10347 [1 << 17]byte var z10348 [1 << 17]byte var z10349 [1 << 17]byte var z10350 [1 << 17]byte var z10351 [1 << 17]byte var z10352 [1 << 17]byte var z10353 [1 << 17]byte var z10354 [1 << 17]byte var z10355 [1 << 17]byte var z10356 [1 << 17]byte var z10357 [1 << 17]byte var z10358 [1 << 17]byte var z10359 [1 << 17]byte var z10360 [1 << 17]byte var z10361 [1 << 17]byte var z10362 [1 << 17]byte var z10363 [1 << 17]byte var z10364 [1 << 17]byte var z10365 [1 << 17]byte var z10366 [1 << 17]byte var z10367 [1 << 17]byte var z10368 [1 << 17]byte var z10369 [1 << 17]byte var z10370 [1 << 17]byte var z10371 [1 << 17]byte var z10372 [1 << 17]byte var z10373 [1 << 17]byte var z10374 [1 << 17]byte var z10375 [1 << 17]byte var z10376 [1 << 17]byte var z10377 [1 << 17]byte var z10378 [1 << 17]byte var z10379 [1 << 17]byte var z10380 [1 << 17]byte var z10381 [1 << 17]byte var z10382 [1 << 17]byte var z10383 [1 << 17]byte var z10384 [1 << 17]byte var z10385 [1 << 17]byte var z10386 [1 << 17]byte var z10387 [1 << 17]byte var z10388 [1 << 17]byte var z10389 [1 << 17]byte var z10390 [1 << 17]byte var z10391 [1 << 17]byte var z10392 [1 << 17]byte var z10393 [1 << 17]byte var z10394 [1 << 17]byte var z10395 [1 << 17]byte var z10396 [1 << 17]byte var z10397 [1 << 17]byte var z10398 [1 << 17]byte var z10399 [1 << 17]byte var z10400 [1 << 17]byte var z10401 [1 << 17]byte var z10402 [1 << 17]byte var z10403 [1 << 17]byte var z10404 [1 << 17]byte var z10405 [1 << 17]byte var z10406 [1 << 17]byte var z10407 [1 << 17]byte var z10408 [1 << 17]byte var z10409 [1 << 17]byte var z10410 [1 << 17]byte var z10411 [1 << 17]byte var z10412 [1 << 17]byte var z10413 [1 << 17]byte var z10414 [1 << 17]byte var z10415 [1 << 17]byte var z10416 [1 << 17]byte var z10417 [1 << 17]byte var z10418 [1 << 17]byte var z10419 [1 << 17]byte var z10420 [1 << 17]byte var z10421 [1 << 17]byte var z10422 [1 << 17]byte var z10423 [1 << 17]byte var z10424 [1 << 17]byte var z10425 [1 << 17]byte var z10426 [1 << 17]byte var z10427 [1 << 17]byte var z10428 [1 << 17]byte var z10429 [1 << 17]byte var z10430 [1 << 17]byte var z10431 [1 << 17]byte var z10432 [1 << 17]byte var z10433 [1 << 17]byte var z10434 [1 << 17]byte var z10435 [1 << 17]byte var z10436 [1 << 17]byte var z10437 [1 << 17]byte var z10438 [1 << 17]byte var z10439 [1 << 17]byte var z10440 [1 << 17]byte var z10441 [1 << 17]byte var z10442 [1 << 17]byte var z10443 [1 << 17]byte var z10444 [1 << 17]byte var z10445 [1 << 17]byte var z10446 [1 << 17]byte var z10447 [1 << 17]byte var z10448 [1 << 17]byte var z10449 [1 << 17]byte var z10450 [1 << 17]byte var z10451 [1 << 17]byte var z10452 [1 << 17]byte var z10453 [1 << 17]byte var z10454 [1 << 17]byte var z10455 [1 << 17]byte var z10456 [1 << 17]byte var z10457 [1 << 17]byte var z10458 [1 << 17]byte var z10459 [1 << 17]byte var z10460 [1 << 17]byte var z10461 [1 << 17]byte var z10462 [1 << 17]byte var z10463 [1 << 17]byte var z10464 [1 << 17]byte var z10465 [1 << 17]byte var z10466 [1 << 17]byte var z10467 [1 << 17]byte var z10468 [1 << 17]byte var z10469 [1 << 17]byte var z10470 [1 << 17]byte var z10471 [1 << 17]byte var z10472 [1 << 17]byte var z10473 [1 << 17]byte var z10474 [1 << 17]byte var z10475 [1 << 17]byte var z10476 [1 << 17]byte var z10477 [1 << 17]byte var z10478 [1 << 17]byte var z10479 [1 << 17]byte var z10480 [1 << 17]byte var z10481 [1 << 17]byte var z10482 [1 << 17]byte var z10483 [1 << 17]byte var z10484 [1 << 17]byte var z10485 [1 << 17]byte var z10486 [1 << 17]byte var z10487 [1 << 17]byte var z10488 [1 << 17]byte var z10489 [1 << 17]byte var z10490 [1 << 17]byte var z10491 [1 << 17]byte var z10492 [1 << 17]byte var z10493 [1 << 17]byte var z10494 [1 << 17]byte var z10495 [1 << 17]byte var z10496 [1 << 17]byte var z10497 [1 << 17]byte var z10498 [1 << 17]byte var z10499 [1 << 17]byte var z10500 [1 << 17]byte var z10501 [1 << 17]byte var z10502 [1 << 17]byte var z10503 [1 << 17]byte var z10504 [1 << 17]byte var z10505 [1 << 17]byte var z10506 [1 << 17]byte var z10507 [1 << 17]byte var z10508 [1 << 17]byte var z10509 [1 << 17]byte var z10510 [1 << 17]byte var z10511 [1 << 17]byte var z10512 [1 << 17]byte var z10513 [1 << 17]byte var z10514 [1 << 17]byte var z10515 [1 << 17]byte var z10516 [1 << 17]byte var z10517 [1 << 17]byte var z10518 [1 << 17]byte var z10519 [1 << 17]byte var z10520 [1 << 17]byte var z10521 [1 << 17]byte var z10522 [1 << 17]byte var z10523 [1 << 17]byte var z10524 [1 << 17]byte var z10525 [1 << 17]byte var z10526 [1 << 17]byte var z10527 [1 << 17]byte var z10528 [1 << 17]byte var z10529 [1 << 17]byte var z10530 [1 << 17]byte var z10531 [1 << 17]byte var z10532 [1 << 17]byte var z10533 [1 << 17]byte var z10534 [1 << 17]byte var z10535 [1 << 17]byte var z10536 [1 << 17]byte var z10537 [1 << 17]byte var z10538 [1 << 17]byte var z10539 [1 << 17]byte var z10540 [1 << 17]byte var z10541 [1 << 17]byte var z10542 [1 << 17]byte var z10543 [1 << 17]byte var z10544 [1 << 17]byte var z10545 [1 << 17]byte var z10546 [1 << 17]byte var z10547 [1 << 17]byte var z10548 [1 << 17]byte var z10549 [1 << 17]byte var z10550 [1 << 17]byte var z10551 [1 << 17]byte var z10552 [1 << 17]byte var z10553 [1 << 17]byte var z10554 [1 << 17]byte var z10555 [1 << 17]byte var z10556 [1 << 17]byte var z10557 [1 << 17]byte var z10558 [1 << 17]byte var z10559 [1 << 17]byte var z10560 [1 << 17]byte var z10561 [1 << 17]byte var z10562 [1 << 17]byte var z10563 [1 << 17]byte var z10564 [1 << 17]byte var z10565 [1 << 17]byte var z10566 [1 << 17]byte var z10567 [1 << 17]byte var z10568 [1 << 17]byte var z10569 [1 << 17]byte var z10570 [1 << 17]byte var z10571 [1 << 17]byte var z10572 [1 << 17]byte var z10573 [1 << 17]byte var z10574 [1 << 17]byte var z10575 [1 << 17]byte var z10576 [1 << 17]byte var z10577 [1 << 17]byte var z10578 [1 << 17]byte var z10579 [1 << 17]byte var z10580 [1 << 17]byte var z10581 [1 << 17]byte var z10582 [1 << 17]byte var z10583 [1 << 17]byte var z10584 [1 << 17]byte var z10585 [1 << 17]byte var z10586 [1 << 17]byte var z10587 [1 << 17]byte var z10588 [1 << 17]byte var z10589 [1 << 17]byte var z10590 [1 << 17]byte var z10591 [1 << 17]byte var z10592 [1 << 17]byte var z10593 [1 << 17]byte var z10594 [1 << 17]byte var z10595 [1 << 17]byte var z10596 [1 << 17]byte var z10597 [1 << 17]byte var z10598 [1 << 17]byte var z10599 [1 << 17]byte var z10600 [1 << 17]byte var z10601 [1 << 17]byte var z10602 [1 << 17]byte var z10603 [1 << 17]byte var z10604 [1 << 17]byte var z10605 [1 << 17]byte var z10606 [1 << 17]byte var z10607 [1 << 17]byte var z10608 [1 << 17]byte var z10609 [1 << 17]byte var z10610 [1 << 17]byte var z10611 [1 << 17]byte var z10612 [1 << 17]byte var z10613 [1 << 17]byte var z10614 [1 << 17]byte var z10615 [1 << 17]byte var z10616 [1 << 17]byte var z10617 [1 << 17]byte var z10618 [1 << 17]byte var z10619 [1 << 17]byte var z10620 [1 << 17]byte var z10621 [1 << 17]byte var z10622 [1 << 17]byte var z10623 [1 << 17]byte var z10624 [1 << 17]byte var z10625 [1 << 17]byte var z10626 [1 << 17]byte var z10627 [1 << 17]byte var z10628 [1 << 17]byte var z10629 [1 << 17]byte var z10630 [1 << 17]byte var z10631 [1 << 17]byte var z10632 [1 << 17]byte var z10633 [1 << 17]byte var z10634 [1 << 17]byte var z10635 [1 << 17]byte var z10636 [1 << 17]byte var z10637 [1 << 17]byte var z10638 [1 << 17]byte var z10639 [1 << 17]byte var z10640 [1 << 17]byte var z10641 [1 << 17]byte var z10642 [1 << 17]byte var z10643 [1 << 17]byte var z10644 [1 << 17]byte var z10645 [1 << 17]byte var z10646 [1 << 17]byte var z10647 [1 << 17]byte var z10648 [1 << 17]byte var z10649 [1 << 17]byte var z10650 [1 << 17]byte var z10651 [1 << 17]byte var z10652 [1 << 17]byte var z10653 [1 << 17]byte var z10654 [1 << 17]byte var z10655 [1 << 17]byte var z10656 [1 << 17]byte var z10657 [1 << 17]byte var z10658 [1 << 17]byte var z10659 [1 << 17]byte var z10660 [1 << 17]byte var z10661 [1 << 17]byte var z10662 [1 << 17]byte var z10663 [1 << 17]byte var z10664 [1 << 17]byte var z10665 [1 << 17]byte var z10666 [1 << 17]byte var z10667 [1 << 17]byte var z10668 [1 << 17]byte var z10669 [1 << 17]byte var z10670 [1 << 17]byte var z10671 [1 << 17]byte var z10672 [1 << 17]byte var z10673 [1 << 17]byte var z10674 [1 << 17]byte var z10675 [1 << 17]byte var z10676 [1 << 17]byte var z10677 [1 << 17]byte var z10678 [1 << 17]byte var z10679 [1 << 17]byte var z10680 [1 << 17]byte var z10681 [1 << 17]byte var z10682 [1 << 17]byte var z10683 [1 << 17]byte var z10684 [1 << 17]byte var z10685 [1 << 17]byte var z10686 [1 << 17]byte var z10687 [1 << 17]byte var z10688 [1 << 17]byte var z10689 [1 << 17]byte var z10690 [1 << 17]byte var z10691 [1 << 17]byte var z10692 [1 << 17]byte var z10693 [1 << 17]byte var z10694 [1 << 17]byte var z10695 [1 << 17]byte var z10696 [1 << 17]byte var z10697 [1 << 17]byte var z10698 [1 << 17]byte var z10699 [1 << 17]byte var z10700 [1 << 17]byte var z10701 [1 << 17]byte var z10702 [1 << 17]byte var z10703 [1 << 17]byte var z10704 [1 << 17]byte var z10705 [1 << 17]byte var z10706 [1 << 17]byte var z10707 [1 << 17]byte var z10708 [1 << 17]byte var z10709 [1 << 17]byte var z10710 [1 << 17]byte var z10711 [1 << 17]byte var z10712 [1 << 17]byte var z10713 [1 << 17]byte var z10714 [1 << 17]byte var z10715 [1 << 17]byte var z10716 [1 << 17]byte var z10717 [1 << 17]byte var z10718 [1 << 17]byte var z10719 [1 << 17]byte var z10720 [1 << 17]byte var z10721 [1 << 17]byte var z10722 [1 << 17]byte var z10723 [1 << 17]byte var z10724 [1 << 17]byte var z10725 [1 << 17]byte var z10726 [1 << 17]byte var z10727 [1 << 17]byte var z10728 [1 << 17]byte var z10729 [1 << 17]byte var z10730 [1 << 17]byte var z10731 [1 << 17]byte var z10732 [1 << 17]byte var z10733 [1 << 17]byte var z10734 [1 << 17]byte var z10735 [1 << 17]byte var z10736 [1 << 17]byte var z10737 [1 << 17]byte var z10738 [1 << 17]byte var z10739 [1 << 17]byte var z10740 [1 << 17]byte var z10741 [1 << 17]byte var z10742 [1 << 17]byte var z10743 [1 << 17]byte var z10744 [1 << 17]byte var z10745 [1 << 17]byte var z10746 [1 << 17]byte var z10747 [1 << 17]byte var z10748 [1 << 17]byte var z10749 [1 << 17]byte var z10750 [1 << 17]byte var z10751 [1 << 17]byte var z10752 [1 << 17]byte var z10753 [1 << 17]byte var z10754 [1 << 17]byte var z10755 [1 << 17]byte var z10756 [1 << 17]byte var z10757 [1 << 17]byte var z10758 [1 << 17]byte var z10759 [1 << 17]byte var z10760 [1 << 17]byte var z10761 [1 << 17]byte var z10762 [1 << 17]byte var z10763 [1 << 17]byte var z10764 [1 << 17]byte var z10765 [1 << 17]byte var z10766 [1 << 17]byte var z10767 [1 << 17]byte var z10768 [1 << 17]byte var z10769 [1 << 17]byte var z10770 [1 << 17]byte var z10771 [1 << 17]byte var z10772 [1 << 17]byte var z10773 [1 << 17]byte var z10774 [1 << 17]byte var z10775 [1 << 17]byte var z10776 [1 << 17]byte var z10777 [1 << 17]byte var z10778 [1 << 17]byte var z10779 [1 << 17]byte var z10780 [1 << 17]byte var z10781 [1 << 17]byte var z10782 [1 << 17]byte var z10783 [1 << 17]byte var z10784 [1 << 17]byte var z10785 [1 << 17]byte var z10786 [1 << 17]byte var z10787 [1 << 17]byte var z10788 [1 << 17]byte var z10789 [1 << 17]byte var z10790 [1 << 17]byte var z10791 [1 << 17]byte var z10792 [1 << 17]byte var z10793 [1 << 17]byte var z10794 [1 << 17]byte var z10795 [1 << 17]byte var z10796 [1 << 17]byte var z10797 [1 << 17]byte var z10798 [1 << 17]byte var z10799 [1 << 17]byte var z10800 [1 << 17]byte var z10801 [1 << 17]byte var z10802 [1 << 17]byte var z10803 [1 << 17]byte var z10804 [1 << 17]byte var z10805 [1 << 17]byte var z10806 [1 << 17]byte var z10807 [1 << 17]byte var z10808 [1 << 17]byte var z10809 [1 << 17]byte var z10810 [1 << 17]byte var z10811 [1 << 17]byte var z10812 [1 << 17]byte var z10813 [1 << 17]byte var z10814 [1 << 17]byte var z10815 [1 << 17]byte var z10816 [1 << 17]byte var z10817 [1 << 17]byte var z10818 [1 << 17]byte var z10819 [1 << 17]byte var z10820 [1 << 17]byte var z10821 [1 << 17]byte var z10822 [1 << 17]byte var z10823 [1 << 17]byte var z10824 [1 << 17]byte var z10825 [1 << 17]byte var z10826 [1 << 17]byte var z10827 [1 << 17]byte var z10828 [1 << 17]byte var z10829 [1 << 17]byte var z10830 [1 << 17]byte var z10831 [1 << 17]byte var z10832 [1 << 17]byte var z10833 [1 << 17]byte var z10834 [1 << 17]byte var z10835 [1 << 17]byte var z10836 [1 << 17]byte var z10837 [1 << 17]byte var z10838 [1 << 17]byte var z10839 [1 << 17]byte var z10840 [1 << 17]byte var z10841 [1 << 17]byte var z10842 [1 << 17]byte var z10843 [1 << 17]byte var z10844 [1 << 17]byte var z10845 [1 << 17]byte var z10846 [1 << 17]byte var z10847 [1 << 17]byte var z10848 [1 << 17]byte var z10849 [1 << 17]byte var z10850 [1 << 17]byte var z10851 [1 << 17]byte var z10852 [1 << 17]byte var z10853 [1 << 17]byte var z10854 [1 << 17]byte var z10855 [1 << 17]byte var z10856 [1 << 17]byte var z10857 [1 << 17]byte var z10858 [1 << 17]byte var z10859 [1 << 17]byte var z10860 [1 << 17]byte var z10861 [1 << 17]byte var z10862 [1 << 17]byte var z10863 [1 << 17]byte var z10864 [1 << 17]byte var z10865 [1 << 17]byte var z10866 [1 << 17]byte var z10867 [1 << 17]byte var z10868 [1 << 17]byte var z10869 [1 << 17]byte var z10870 [1 << 17]byte var z10871 [1 << 17]byte var z10872 [1 << 17]byte var z10873 [1 << 17]byte var z10874 [1 << 17]byte var z10875 [1 << 17]byte var z10876 [1 << 17]byte var z10877 [1 << 17]byte var z10878 [1 << 17]byte var z10879 [1 << 17]byte var z10880 [1 << 17]byte var z10881 [1 << 17]byte var z10882 [1 << 17]byte var z10883 [1 << 17]byte var z10884 [1 << 17]byte var z10885 [1 << 17]byte var z10886 [1 << 17]byte var z10887 [1 << 17]byte var z10888 [1 << 17]byte var z10889 [1 << 17]byte var z10890 [1 << 17]byte var z10891 [1 << 17]byte var z10892 [1 << 17]byte var z10893 [1 << 17]byte var z10894 [1 << 17]byte var z10895 [1 << 17]byte var z10896 [1 << 17]byte var z10897 [1 << 17]byte var z10898 [1 << 17]byte var z10899 [1 << 17]byte var z10900 [1 << 17]byte var z10901 [1 << 17]byte var z10902 [1 << 17]byte var z10903 [1 << 17]byte var z10904 [1 << 17]byte var z10905 [1 << 17]byte var z10906 [1 << 17]byte var z10907 [1 << 17]byte var z10908 [1 << 17]byte var z10909 [1 << 17]byte var z10910 [1 << 17]byte var z10911 [1 << 17]byte var z10912 [1 << 17]byte var z10913 [1 << 17]byte var z10914 [1 << 17]byte var z10915 [1 << 17]byte var z10916 [1 << 17]byte var z10917 [1 << 17]byte var z10918 [1 << 17]byte var z10919 [1 << 17]byte var z10920 [1 << 17]byte var z10921 [1 << 17]byte var z10922 [1 << 17]byte var z10923 [1 << 17]byte var z10924 [1 << 17]byte var z10925 [1 << 17]byte var z10926 [1 << 17]byte var z10927 [1 << 17]byte var z10928 [1 << 17]byte var z10929 [1 << 17]byte var z10930 [1 << 17]byte var z10931 [1 << 17]byte var z10932 [1 << 17]byte var z10933 [1 << 17]byte var z10934 [1 << 17]byte var z10935 [1 << 17]byte var z10936 [1 << 17]byte var z10937 [1 << 17]byte var z10938 [1 << 17]byte var z10939 [1 << 17]byte var z10940 [1 << 17]byte var z10941 [1 << 17]byte var z10942 [1 << 17]byte var z10943 [1 << 17]byte var z10944 [1 << 17]byte var z10945 [1 << 17]byte var z10946 [1 << 17]byte var z10947 [1 << 17]byte var z10948 [1 << 17]byte var z10949 [1 << 17]byte var z10950 [1 << 17]byte var z10951 [1 << 17]byte var z10952 [1 << 17]byte var z10953 [1 << 17]byte var z10954 [1 << 17]byte var z10955 [1 << 17]byte var z10956 [1 << 17]byte var z10957 [1 << 17]byte var z10958 [1 << 17]byte var z10959 [1 << 17]byte var z10960 [1 << 17]byte var z10961 [1 << 17]byte var z10962 [1 << 17]byte var z10963 [1 << 17]byte var z10964 [1 << 17]byte var z10965 [1 << 17]byte var z10966 [1 << 17]byte var z10967 [1 << 17]byte var z10968 [1 << 17]byte var z10969 [1 << 17]byte var z10970 [1 << 17]byte var z10971 [1 << 17]byte var z10972 [1 << 17]byte var z10973 [1 << 17]byte var z10974 [1 << 17]byte var z10975 [1 << 17]byte var z10976 [1 << 17]byte var z10977 [1 << 17]byte var z10978 [1 << 17]byte var z10979 [1 << 17]byte var z10980 [1 << 17]byte var z10981 [1 << 17]byte var z10982 [1 << 17]byte var z10983 [1 << 17]byte var z10984 [1 << 17]byte var z10985 [1 << 17]byte var z10986 [1 << 17]byte var z10987 [1 << 17]byte var z10988 [1 << 17]byte var z10989 [1 << 17]byte var z10990 [1 << 17]byte var z10991 [1 << 17]byte var z10992 [1 << 17]byte var z10993 [1 << 17]byte var z10994 [1 << 17]byte var z10995 [1 << 17]byte var z10996 [1 << 17]byte var z10997 [1 << 17]byte var z10998 [1 << 17]byte var z10999 [1 << 17]byte var z11000 [1 << 17]byte var z11001 [1 << 17]byte var z11002 [1 << 17]byte var z11003 [1 << 17]byte var z11004 [1 << 17]byte var z11005 [1 << 17]byte var z11006 [1 << 17]byte var z11007 [1 << 17]byte var z11008 [1 << 17]byte var z11009 [1 << 17]byte var z11010 [1 << 17]byte var z11011 [1 << 17]byte var z11012 [1 << 17]byte var z11013 [1 << 17]byte var z11014 [1 << 17]byte var z11015 [1 << 17]byte var z11016 [1 << 17]byte var z11017 [1 << 17]byte var z11018 [1 << 17]byte var z11019 [1 << 17]byte var z11020 [1 << 17]byte var z11021 [1 << 17]byte var z11022 [1 << 17]byte var z11023 [1 << 17]byte var z11024 [1 << 17]byte var z11025 [1 << 17]byte var z11026 [1 << 17]byte var z11027 [1 << 17]byte var z11028 [1 << 17]byte var z11029 [1 << 17]byte var z11030 [1 << 17]byte var z11031 [1 << 17]byte var z11032 [1 << 17]byte var z11033 [1 << 17]byte var z11034 [1 << 17]byte var z11035 [1 << 17]byte var z11036 [1 << 17]byte var z11037 [1 << 17]byte var z11038 [1 << 17]byte var z11039 [1 << 17]byte var z11040 [1 << 17]byte var z11041 [1 << 17]byte var z11042 [1 << 17]byte var z11043 [1 << 17]byte var z11044 [1 << 17]byte var z11045 [1 << 17]byte var z11046 [1 << 17]byte var z11047 [1 << 17]byte var z11048 [1 << 17]byte var z11049 [1 << 17]byte var z11050 [1 << 17]byte var z11051 [1 << 17]byte var z11052 [1 << 17]byte var z11053 [1 << 17]byte var z11054 [1 << 17]byte var z11055 [1 << 17]byte var z11056 [1 << 17]byte var z11057 [1 << 17]byte var z11058 [1 << 17]byte var z11059 [1 << 17]byte var z11060 [1 << 17]byte var z11061 [1 << 17]byte var z11062 [1 << 17]byte var z11063 [1 << 17]byte var z11064 [1 << 17]byte var z11065 [1 << 17]byte var z11066 [1 << 17]byte var z11067 [1 << 17]byte var z11068 [1 << 17]byte var z11069 [1 << 17]byte var z11070 [1 << 17]byte var z11071 [1 << 17]byte var z11072 [1 << 17]byte var z11073 [1 << 17]byte var z11074 [1 << 17]byte var z11075 [1 << 17]byte var z11076 [1 << 17]byte var z11077 [1 << 17]byte var z11078 [1 << 17]byte var z11079 [1 << 17]byte var z11080 [1 << 17]byte var z11081 [1 << 17]byte var z11082 [1 << 17]byte var z11083 [1 << 17]byte var z11084 [1 << 17]byte var z11085 [1 << 17]byte var z11086 [1 << 17]byte var z11087 [1 << 17]byte var z11088 [1 << 17]byte var z11089 [1 << 17]byte var z11090 [1 << 17]byte var z11091 [1 << 17]byte var z11092 [1 << 17]byte var z11093 [1 << 17]byte var z11094 [1 << 17]byte var z11095 [1 << 17]byte var z11096 [1 << 17]byte var z11097 [1 << 17]byte var z11098 [1 << 17]byte var z11099 [1 << 17]byte var z11100 [1 << 17]byte var z11101 [1 << 17]byte var z11102 [1 << 17]byte var z11103 [1 << 17]byte var z11104 [1 << 17]byte var z11105 [1 << 17]byte var z11106 [1 << 17]byte var z11107 [1 << 17]byte var z11108 [1 << 17]byte var z11109 [1 << 17]byte var z11110 [1 << 17]byte var z11111 [1 << 17]byte var z11112 [1 << 17]byte var z11113 [1 << 17]byte var z11114 [1 << 17]byte var z11115 [1 << 17]byte var z11116 [1 << 17]byte var z11117 [1 << 17]byte var z11118 [1 << 17]byte var z11119 [1 << 17]byte var z11120 [1 << 17]byte var z11121 [1 << 17]byte var z11122 [1 << 17]byte var z11123 [1 << 17]byte var z11124 [1 << 17]byte var z11125 [1 << 17]byte var z11126 [1 << 17]byte var z11127 [1 << 17]byte var z11128 [1 << 17]byte var z11129 [1 << 17]byte var z11130 [1 << 17]byte var z11131 [1 << 17]byte var z11132 [1 << 17]byte var z11133 [1 << 17]byte var z11134 [1 << 17]byte var z11135 [1 << 17]byte var z11136 [1 << 17]byte var z11137 [1 << 17]byte var z11138 [1 << 17]byte var z11139 [1 << 17]byte var z11140 [1 << 17]byte var z11141 [1 << 17]byte var z11142 [1 << 17]byte var z11143 [1 << 17]byte var z11144 [1 << 17]byte var z11145 [1 << 17]byte var z11146 [1 << 17]byte var z11147 [1 << 17]byte var z11148 [1 << 17]byte var z11149 [1 << 17]byte var z11150 [1 << 17]byte var z11151 [1 << 17]byte var z11152 [1 << 17]byte var z11153 [1 << 17]byte var z11154 [1 << 17]byte var z11155 [1 << 17]byte var z11156 [1 << 17]byte var z11157 [1 << 17]byte var z11158 [1 << 17]byte var z11159 [1 << 17]byte var z11160 [1 << 17]byte var z11161 [1 << 17]byte var z11162 [1 << 17]byte var z11163 [1 << 17]byte var z11164 [1 << 17]byte var z11165 [1 << 17]byte var z11166 [1 << 17]byte var z11167 [1 << 17]byte var z11168 [1 << 17]byte var z11169 [1 << 17]byte var z11170 [1 << 17]byte var z11171 [1 << 17]byte var z11172 [1 << 17]byte var z11173 [1 << 17]byte var z11174 [1 << 17]byte var z11175 [1 << 17]byte var z11176 [1 << 17]byte var z11177 [1 << 17]byte var z11178 [1 << 17]byte var z11179 [1 << 17]byte var z11180 [1 << 17]byte var z11181 [1 << 17]byte var z11182 [1 << 17]byte var z11183 [1 << 17]byte var z11184 [1 << 17]byte var z11185 [1 << 17]byte var z11186 [1 << 17]byte var z11187 [1 << 17]byte var z11188 [1 << 17]byte var z11189 [1 << 17]byte var z11190 [1 << 17]byte var z11191 [1 << 17]byte var z11192 [1 << 17]byte var z11193 [1 << 17]byte var z11194 [1 << 17]byte var z11195 [1 << 17]byte var z11196 [1 << 17]byte var z11197 [1 << 17]byte var z11198 [1 << 17]byte var z11199 [1 << 17]byte var z11200 [1 << 17]byte var z11201 [1 << 17]byte var z11202 [1 << 17]byte var z11203 [1 << 17]byte var z11204 [1 << 17]byte var z11205 [1 << 17]byte var z11206 [1 << 17]byte var z11207 [1 << 17]byte var z11208 [1 << 17]byte var z11209 [1 << 17]byte var z11210 [1 << 17]byte var z11211 [1 << 17]byte var z11212 [1 << 17]byte var z11213 [1 << 17]byte var z11214 [1 << 17]byte var z11215 [1 << 17]byte var z11216 [1 << 17]byte var z11217 [1 << 17]byte var z11218 [1 << 17]byte var z11219 [1 << 17]byte var z11220 [1 << 17]byte var z11221 [1 << 17]byte var z11222 [1 << 17]byte var z11223 [1 << 17]byte var z11224 [1 << 17]byte var z11225 [1 << 17]byte var z11226 [1 << 17]byte var z11227 [1 << 17]byte var z11228 [1 << 17]byte var z11229 [1 << 17]byte var z11230 [1 << 17]byte var z11231 [1 << 17]byte var z11232 [1 << 17]byte var z11233 [1 << 17]byte var z11234 [1 << 17]byte var z11235 [1 << 17]byte var z11236 [1 << 17]byte var z11237 [1 << 17]byte var z11238 [1 << 17]byte var z11239 [1 << 17]byte var z11240 [1 << 17]byte var z11241 [1 << 17]byte var z11242 [1 << 17]byte var z11243 [1 << 17]byte var z11244 [1 << 17]byte var z11245 [1 << 17]byte var z11246 [1 << 17]byte var z11247 [1 << 17]byte var z11248 [1 << 17]byte var z11249 [1 << 17]byte var z11250 [1 << 17]byte var z11251 [1 << 17]byte var z11252 [1 << 17]byte var z11253 [1 << 17]byte var z11254 [1 << 17]byte var z11255 [1 << 17]byte var z11256 [1 << 17]byte var z11257 [1 << 17]byte var z11258 [1 << 17]byte var z11259 [1 << 17]byte var z11260 [1 << 17]byte var z11261 [1 << 17]byte var z11262 [1 << 17]byte var z11263 [1 << 17]byte var z11264 [1 << 17]byte var z11265 [1 << 17]byte var z11266 [1 << 17]byte var z11267 [1 << 17]byte var z11268 [1 << 17]byte var z11269 [1 << 17]byte var z11270 [1 << 17]byte var z11271 [1 << 17]byte var z11272 [1 << 17]byte var z11273 [1 << 17]byte var z11274 [1 << 17]byte var z11275 [1 << 17]byte var z11276 [1 << 17]byte var z11277 [1 << 17]byte var z11278 [1 << 17]byte var z11279 [1 << 17]byte var z11280 [1 << 17]byte var z11281 [1 << 17]byte var z11282 [1 << 17]byte var z11283 [1 << 17]byte var z11284 [1 << 17]byte var z11285 [1 << 17]byte var z11286 [1 << 17]byte var z11287 [1 << 17]byte var z11288 [1 << 17]byte var z11289 [1 << 17]byte var z11290 [1 << 17]byte var z11291 [1 << 17]byte var z11292 [1 << 17]byte var z11293 [1 << 17]byte var z11294 [1 << 17]byte var z11295 [1 << 17]byte var z11296 [1 << 17]byte var z11297 [1 << 17]byte var z11298 [1 << 17]byte var z11299 [1 << 17]byte var z11300 [1 << 17]byte var z11301 [1 << 17]byte var z11302 [1 << 17]byte var z11303 [1 << 17]byte var z11304 [1 << 17]byte var z11305 [1 << 17]byte var z11306 [1 << 17]byte var z11307 [1 << 17]byte var z11308 [1 << 17]byte var z11309 [1 << 17]byte var z11310 [1 << 17]byte var z11311 [1 << 17]byte var z11312 [1 << 17]byte var z11313 [1 << 17]byte var z11314 [1 << 17]byte var z11315 [1 << 17]byte var z11316 [1 << 17]byte var z11317 [1 << 17]byte var z11318 [1 << 17]byte var z11319 [1 << 17]byte var z11320 [1 << 17]byte var z11321 [1 << 17]byte var z11322 [1 << 17]byte var z11323 [1 << 17]byte var z11324 [1 << 17]byte var z11325 [1 << 17]byte var z11326 [1 << 17]byte var z11327 [1 << 17]byte var z11328 [1 << 17]byte var z11329 [1 << 17]byte var z11330 [1 << 17]byte var z11331 [1 << 17]byte var z11332 [1 << 17]byte var z11333 [1 << 17]byte var z11334 [1 << 17]byte var z11335 [1 << 17]byte var z11336 [1 << 17]byte var z11337 [1 << 17]byte var z11338 [1 << 17]byte var z11339 [1 << 17]byte var z11340 [1 << 17]byte var z11341 [1 << 17]byte var z11342 [1 << 17]byte var z11343 [1 << 17]byte var z11344 [1 << 17]byte var z11345 [1 << 17]byte var z11346 [1 << 17]byte var z11347 [1 << 17]byte var z11348 [1 << 17]byte var z11349 [1 << 17]byte var z11350 [1 << 17]byte var z11351 [1 << 17]byte var z11352 [1 << 17]byte var z11353 [1 << 17]byte var z11354 [1 << 17]byte var z11355 [1 << 17]byte var z11356 [1 << 17]byte var z11357 [1 << 17]byte var z11358 [1 << 17]byte var z11359 [1 << 17]byte var z11360 [1 << 17]byte var z11361 [1 << 17]byte var z11362 [1 << 17]byte var z11363 [1 << 17]byte var z11364 [1 << 17]byte var z11365 [1 << 17]byte var z11366 [1 << 17]byte var z11367 [1 << 17]byte var z11368 [1 << 17]byte var z11369 [1 << 17]byte var z11370 [1 << 17]byte var z11371 [1 << 17]byte var z11372 [1 << 17]byte var z11373 [1 << 17]byte var z11374 [1 << 17]byte var z11375 [1 << 17]byte var z11376 [1 << 17]byte var z11377 [1 << 17]byte var z11378 [1 << 17]byte var z11379 [1 << 17]byte var z11380 [1 << 17]byte var z11381 [1 << 17]byte var z11382 [1 << 17]byte var z11383 [1 << 17]byte var z11384 [1 << 17]byte var z11385 [1 << 17]byte var z11386 [1 << 17]byte var z11387 [1 << 17]byte var z11388 [1 << 17]byte var z11389 [1 << 17]byte var z11390 [1 << 17]byte var z11391 [1 << 17]byte var z11392 [1 << 17]byte var z11393 [1 << 17]byte var z11394 [1 << 17]byte var z11395 [1 << 17]byte var z11396 [1 << 17]byte var z11397 [1 << 17]byte var z11398 [1 << 17]byte var z11399 [1 << 17]byte var z11400 [1 << 17]byte var z11401 [1 << 17]byte var z11402 [1 << 17]byte var z11403 [1 << 17]byte var z11404 [1 << 17]byte var z11405 [1 << 17]byte var z11406 [1 << 17]byte var z11407 [1 << 17]byte var z11408 [1 << 17]byte var z11409 [1 << 17]byte var z11410 [1 << 17]byte var z11411 [1 << 17]byte var z11412 [1 << 17]byte var z11413 [1 << 17]byte var z11414 [1 << 17]byte var z11415 [1 << 17]byte var z11416 [1 << 17]byte var z11417 [1 << 17]byte var z11418 [1 << 17]byte var z11419 [1 << 17]byte var z11420 [1 << 17]byte var z11421 [1 << 17]byte var z11422 [1 << 17]byte var z11423 [1 << 17]byte var z11424 [1 << 17]byte var z11425 [1 << 17]byte var z11426 [1 << 17]byte var z11427 [1 << 17]byte var z11428 [1 << 17]byte var z11429 [1 << 17]byte var z11430 [1 << 17]byte var z11431 [1 << 17]byte var z11432 [1 << 17]byte var z11433 [1 << 17]byte var z11434 [1 << 17]byte var z11435 [1 << 17]byte var z11436 [1 << 17]byte var z11437 [1 << 17]byte var z11438 [1 << 17]byte var z11439 [1 << 17]byte var z11440 [1 << 17]byte var z11441 [1 << 17]byte var z11442 [1 << 17]byte var z11443 [1 << 17]byte var z11444 [1 << 17]byte var z11445 [1 << 17]byte var z11446 [1 << 17]byte var z11447 [1 << 17]byte var z11448 [1 << 17]byte var z11449 [1 << 17]byte var z11450 [1 << 17]byte var z11451 [1 << 17]byte var z11452 [1 << 17]byte var z11453 [1 << 17]byte var z11454 [1 << 17]byte var z11455 [1 << 17]byte var z11456 [1 << 17]byte var z11457 [1 << 17]byte var z11458 [1 << 17]byte var z11459 [1 << 17]byte var z11460 [1 << 17]byte var z11461 [1 << 17]byte var z11462 [1 << 17]byte var z11463 [1 << 17]byte var z11464 [1 << 17]byte var z11465 [1 << 17]byte var z11466 [1 << 17]byte var z11467 [1 << 17]byte var z11468 [1 << 17]byte var z11469 [1 << 17]byte var z11470 [1 << 17]byte var z11471 [1 << 17]byte var z11472 [1 << 17]byte var z11473 [1 << 17]byte var z11474 [1 << 17]byte var z11475 [1 << 17]byte var z11476 [1 << 17]byte var z11477 [1 << 17]byte var z11478 [1 << 17]byte var z11479 [1 << 17]byte var z11480 [1 << 17]byte var z11481 [1 << 17]byte var z11482 [1 << 17]byte var z11483 [1 << 17]byte var z11484 [1 << 17]byte var z11485 [1 << 17]byte var z11486 [1 << 17]byte var z11487 [1 << 17]byte var z11488 [1 << 17]byte var z11489 [1 << 17]byte var z11490 [1 << 17]byte var z11491 [1 << 17]byte var z11492 [1 << 17]byte var z11493 [1 << 17]byte var z11494 [1 << 17]byte var z11495 [1 << 17]byte var z11496 [1 << 17]byte var z11497 [1 << 17]byte var z11498 [1 << 17]byte var z11499 [1 << 17]byte var z11500 [1 << 17]byte var z11501 [1 << 17]byte var z11502 [1 << 17]byte var z11503 [1 << 17]byte var z11504 [1 << 17]byte var z11505 [1 << 17]byte var z11506 [1 << 17]byte var z11507 [1 << 17]byte var z11508 [1 << 17]byte var z11509 [1 << 17]byte var z11510 [1 << 17]byte var z11511 [1 << 17]byte var z11512 [1 << 17]byte var z11513 [1 << 17]byte var z11514 [1 << 17]byte var z11515 [1 << 17]byte var z11516 [1 << 17]byte var z11517 [1 << 17]byte var z11518 [1 << 17]byte var z11519 [1 << 17]byte var z11520 [1 << 17]byte var z11521 [1 << 17]byte var z11522 [1 << 17]byte var z11523 [1 << 17]byte var z11524 [1 << 17]byte var z11525 [1 << 17]byte var z11526 [1 << 17]byte var z11527 [1 << 17]byte var z11528 [1 << 17]byte var z11529 [1 << 17]byte var z11530 [1 << 17]byte var z11531 [1 << 17]byte var z11532 [1 << 17]byte var z11533 [1 << 17]byte var z11534 [1 << 17]byte var z11535 [1 << 17]byte var z11536 [1 << 17]byte var z11537 [1 << 17]byte var z11538 [1 << 17]byte var z11539 [1 << 17]byte var z11540 [1 << 17]byte var z11541 [1 << 17]byte var z11542 [1 << 17]byte var z11543 [1 << 17]byte var z11544 [1 << 17]byte var z11545 [1 << 17]byte var z11546 [1 << 17]byte var z11547 [1 << 17]byte var z11548 [1 << 17]byte var z11549 [1 << 17]byte var z11550 [1 << 17]byte var z11551 [1 << 17]byte var z11552 [1 << 17]byte var z11553 [1 << 17]byte var z11554 [1 << 17]byte var z11555 [1 << 17]byte var z11556 [1 << 17]byte var z11557 [1 << 17]byte var z11558 [1 << 17]byte var z11559 [1 << 17]byte var z11560 [1 << 17]byte var z11561 [1 << 17]byte var z11562 [1 << 17]byte var z11563 [1 << 17]byte var z11564 [1 << 17]byte var z11565 [1 << 17]byte var z11566 [1 << 17]byte var z11567 [1 << 17]byte var z11568 [1 << 17]byte var z11569 [1 << 17]byte var z11570 [1 << 17]byte var z11571 [1 << 17]byte var z11572 [1 << 17]byte var z11573 [1 << 17]byte var z11574 [1 << 17]byte var z11575 [1 << 17]byte var z11576 [1 << 17]byte var z11577 [1 << 17]byte var z11578 [1 << 17]byte var z11579 [1 << 17]byte var z11580 [1 << 17]byte var z11581 [1 << 17]byte var z11582 [1 << 17]byte var z11583 [1 << 17]byte var z11584 [1 << 17]byte var z11585 [1 << 17]byte var z11586 [1 << 17]byte var z11587 [1 << 17]byte var z11588 [1 << 17]byte var z11589 [1 << 17]byte var z11590 [1 << 17]byte var z11591 [1 << 17]byte var z11592 [1 << 17]byte var z11593 [1 << 17]byte var z11594 [1 << 17]byte var z11595 [1 << 17]byte var z11596 [1 << 17]byte var z11597 [1 << 17]byte var z11598 [1 << 17]byte var z11599 [1 << 17]byte var z11600 [1 << 17]byte var z11601 [1 << 17]byte var z11602 [1 << 17]byte var z11603 [1 << 17]byte var z11604 [1 << 17]byte var z11605 [1 << 17]byte var z11606 [1 << 17]byte var z11607 [1 << 17]byte var z11608 [1 << 17]byte var z11609 [1 << 17]byte var z11610 [1 << 17]byte var z11611 [1 << 17]byte var z11612 [1 << 17]byte var z11613 [1 << 17]byte var z11614 [1 << 17]byte var z11615 [1 << 17]byte var z11616 [1 << 17]byte var z11617 [1 << 17]byte var z11618 [1 << 17]byte var z11619 [1 << 17]byte var z11620 [1 << 17]byte var z11621 [1 << 17]byte var z11622 [1 << 17]byte var z11623 [1 << 17]byte var z11624 [1 << 17]byte var z11625 [1 << 17]byte var z11626 [1 << 17]byte var z11627 [1 << 17]byte var z11628 [1 << 17]byte var z11629 [1 << 17]byte var z11630 [1 << 17]byte var z11631 [1 << 17]byte var z11632 [1 << 17]byte var z11633 [1 << 17]byte var z11634 [1 << 17]byte var z11635 [1 << 17]byte var z11636 [1 << 17]byte var z11637 [1 << 17]byte var z11638 [1 << 17]byte var z11639 [1 << 17]byte var z11640 [1 << 17]byte var z11641 [1 << 17]byte var z11642 [1 << 17]byte var z11643 [1 << 17]byte var z11644 [1 << 17]byte var z11645 [1 << 17]byte var z11646 [1 << 17]byte var z11647 [1 << 17]byte var z11648 [1 << 17]byte var z11649 [1 << 17]byte var z11650 [1 << 17]byte var z11651 [1 << 17]byte var z11652 [1 << 17]byte var z11653 [1 << 17]byte var z11654 [1 << 17]byte var z11655 [1 << 17]byte var z11656 [1 << 17]byte var z11657 [1 << 17]byte var z11658 [1 << 17]byte var z11659 [1 << 17]byte var z11660 [1 << 17]byte var z11661 [1 << 17]byte var z11662 [1 << 17]byte var z11663 [1 << 17]byte var z11664 [1 << 17]byte var z11665 [1 << 17]byte var z11666 [1 << 17]byte var z11667 [1 << 17]byte var z11668 [1 << 17]byte var z11669 [1 << 17]byte var z11670 [1 << 17]byte var z11671 [1 << 17]byte var z11672 [1 << 17]byte var z11673 [1 << 17]byte var z11674 [1 << 17]byte var z11675 [1 << 17]byte var z11676 [1 << 17]byte var z11677 [1 << 17]byte var z11678 [1 << 17]byte var z11679 [1 << 17]byte var z11680 [1 << 17]byte var z11681 [1 << 17]byte var z11682 [1 << 17]byte var z11683 [1 << 17]byte var z11684 [1 << 17]byte var z11685 [1 << 17]byte var z11686 [1 << 17]byte var z11687 [1 << 17]byte var z11688 [1 << 17]byte var z11689 [1 << 17]byte var z11690 [1 << 17]byte var z11691 [1 << 17]byte var z11692 [1 << 17]byte var z11693 [1 << 17]byte var z11694 [1 << 17]byte var z11695 [1 << 17]byte var z11696 [1 << 17]byte var z11697 [1 << 17]byte var z11698 [1 << 17]byte var z11699 [1 << 17]byte var z11700 [1 << 17]byte var z11701 [1 << 17]byte var z11702 [1 << 17]byte var z11703 [1 << 17]byte var z11704 [1 << 17]byte var z11705 [1 << 17]byte var z11706 [1 << 17]byte var z11707 [1 << 17]byte var z11708 [1 << 17]byte var z11709 [1 << 17]byte var z11710 [1 << 17]byte var z11711 [1 << 17]byte var z11712 [1 << 17]byte var z11713 [1 << 17]byte var z11714 [1 << 17]byte var z11715 [1 << 17]byte var z11716 [1 << 17]byte var z11717 [1 << 17]byte var z11718 [1 << 17]byte var z11719 [1 << 17]byte var z11720 [1 << 17]byte var z11721 [1 << 17]byte var z11722 [1 << 17]byte var z11723 [1 << 17]byte var z11724 [1 << 17]byte var z11725 [1 << 17]byte var z11726 [1 << 17]byte var z11727 [1 << 17]byte var z11728 [1 << 17]byte var z11729 [1 << 17]byte var z11730 [1 << 17]byte var z11731 [1 << 17]byte var z11732 [1 << 17]byte var z11733 [1 << 17]byte var z11734 [1 << 17]byte var z11735 [1 << 17]byte var z11736 [1 << 17]byte var z11737 [1 << 17]byte var z11738 [1 << 17]byte var z11739 [1 << 17]byte var z11740 [1 << 17]byte var z11741 [1 << 17]byte var z11742 [1 << 17]byte var z11743 [1 << 17]byte var z11744 [1 << 17]byte var z11745 [1 << 17]byte var z11746 [1 << 17]byte var z11747 [1 << 17]byte var z11748 [1 << 17]byte var z11749 [1 << 17]byte var z11750 [1 << 17]byte var z11751 [1 << 17]byte var z11752 [1 << 17]byte var z11753 [1 << 17]byte var z11754 [1 << 17]byte var z11755 [1 << 17]byte var z11756 [1 << 17]byte var z11757 [1 << 17]byte var z11758 [1 << 17]byte var z11759 [1 << 17]byte var z11760 [1 << 17]byte var z11761 [1 << 17]byte var z11762 [1 << 17]byte var z11763 [1 << 17]byte var z11764 [1 << 17]byte var z11765 [1 << 17]byte var z11766 [1 << 17]byte var z11767 [1 << 17]byte var z11768 [1 << 17]byte var z11769 [1 << 17]byte var z11770 [1 << 17]byte var z11771 [1 << 17]byte var z11772 [1 << 17]byte var z11773 [1 << 17]byte var z11774 [1 << 17]byte var z11775 [1 << 17]byte var z11776 [1 << 17]byte var z11777 [1 << 17]byte var z11778 [1 << 17]byte var z11779 [1 << 17]byte var z11780 [1 << 17]byte var z11781 [1 << 17]byte var z11782 [1 << 17]byte var z11783 [1 << 17]byte var z11784 [1 << 17]byte var z11785 [1 << 17]byte var z11786 [1 << 17]byte var z11787 [1 << 17]byte var z11788 [1 << 17]byte var z11789 [1 << 17]byte var z11790 [1 << 17]byte var z11791 [1 << 17]byte var z11792 [1 << 17]byte var z11793 [1 << 17]byte var z11794 [1 << 17]byte var z11795 [1 << 17]byte var z11796 [1 << 17]byte var z11797 [1 << 17]byte var z11798 [1 << 17]byte var z11799 [1 << 17]byte var z11800 [1 << 17]byte var z11801 [1 << 17]byte var z11802 [1 << 17]byte var z11803 [1 << 17]byte var z11804 [1 << 17]byte var z11805 [1 << 17]byte var z11806 [1 << 17]byte var z11807 [1 << 17]byte var z11808 [1 << 17]byte var z11809 [1 << 17]byte var z11810 [1 << 17]byte var z11811 [1 << 17]byte var z11812 [1 << 17]byte var z11813 [1 << 17]byte var z11814 [1 << 17]byte var z11815 [1 << 17]byte var z11816 [1 << 17]byte var z11817 [1 << 17]byte var z11818 [1 << 17]byte var z11819 [1 << 17]byte var z11820 [1 << 17]byte var z11821 [1 << 17]byte var z11822 [1 << 17]byte var z11823 [1 << 17]byte var z11824 [1 << 17]byte var z11825 [1 << 17]byte var z11826 [1 << 17]byte var z11827 [1 << 17]byte var z11828 [1 << 17]byte var z11829 [1 << 17]byte var z11830 [1 << 17]byte var z11831 [1 << 17]byte var z11832 [1 << 17]byte var z11833 [1 << 17]byte var z11834 [1 << 17]byte var z11835 [1 << 17]byte var z11836 [1 << 17]byte var z11837 [1 << 17]byte var z11838 [1 << 17]byte var z11839 [1 << 17]byte var z11840 [1 << 17]byte var z11841 [1 << 17]byte var z11842 [1 << 17]byte var z11843 [1 << 17]byte var z11844 [1 << 17]byte var z11845 [1 << 17]byte var z11846 [1 << 17]byte var z11847 [1 << 17]byte var z11848 [1 << 17]byte var z11849 [1 << 17]byte var z11850 [1 << 17]byte var z11851 [1 << 17]byte var z11852 [1 << 17]byte var z11853 [1 << 17]byte var z11854 [1 << 17]byte var z11855 [1 << 17]byte var z11856 [1 << 17]byte var z11857 [1 << 17]byte var z11858 [1 << 17]byte var z11859 [1 << 17]byte var z11860 [1 << 17]byte var z11861 [1 << 17]byte var z11862 [1 << 17]byte var z11863 [1 << 17]byte var z11864 [1 << 17]byte var z11865 [1 << 17]byte var z11866 [1 << 17]byte var z11867 [1 << 17]byte var z11868 [1 << 17]byte var z11869 [1 << 17]byte var z11870 [1 << 17]byte var z11871 [1 << 17]byte var z11872 [1 << 17]byte var z11873 [1 << 17]byte var z11874 [1 << 17]byte var z11875 [1 << 17]byte var z11876 [1 << 17]byte var z11877 [1 << 17]byte var z11878 [1 << 17]byte var z11879 [1 << 17]byte var z11880 [1 << 17]byte var z11881 [1 << 17]byte var z11882 [1 << 17]byte var z11883 [1 << 17]byte var z11884 [1 << 17]byte var z11885 [1 << 17]byte var z11886 [1 << 17]byte var z11887 [1 << 17]byte var z11888 [1 << 17]byte var z11889 [1 << 17]byte var z11890 [1 << 17]byte var z11891 [1 << 17]byte var z11892 [1 << 17]byte var z11893 [1 << 17]byte var z11894 [1 << 17]byte var z11895 [1 << 17]byte var z11896 [1 << 17]byte var z11897 [1 << 17]byte var z11898 [1 << 17]byte var z11899 [1 << 17]byte var z11900 [1 << 17]byte var z11901 [1 << 17]byte var z11902 [1 << 17]byte var z11903 [1 << 17]byte var z11904 [1 << 17]byte var z11905 [1 << 17]byte var z11906 [1 << 17]byte var z11907 [1 << 17]byte var z11908 [1 << 17]byte var z11909 [1 << 17]byte var z11910 [1 << 17]byte var z11911 [1 << 17]byte var z11912 [1 << 17]byte var z11913 [1 << 17]byte var z11914 [1 << 17]byte var z11915 [1 << 17]byte var z11916 [1 << 17]byte var z11917 [1 << 17]byte var z11918 [1 << 17]byte var z11919 [1 << 17]byte var z11920 [1 << 17]byte var z11921 [1 << 17]byte var z11922 [1 << 17]byte var z11923 [1 << 17]byte var z11924 [1 << 17]byte var z11925 [1 << 17]byte var z11926 [1 << 17]byte var z11927 [1 << 17]byte var z11928 [1 << 17]byte var z11929 [1 << 17]byte var z11930 [1 << 17]byte var z11931 [1 << 17]byte var z11932 [1 << 17]byte var z11933 [1 << 17]byte var z11934 [1 << 17]byte var z11935 [1 << 17]byte var z11936 [1 << 17]byte var z11937 [1 << 17]byte var z11938 [1 << 17]byte var z11939 [1 << 17]byte var z11940 [1 << 17]byte var z11941 [1 << 17]byte var z11942 [1 << 17]byte var z11943 [1 << 17]byte var z11944 [1 << 17]byte var z11945 [1 << 17]byte var z11946 [1 << 17]byte var z11947 [1 << 17]byte var z11948 [1 << 17]byte var z11949 [1 << 17]byte var z11950 [1 << 17]byte var z11951 [1 << 17]byte var z11952 [1 << 17]byte var z11953 [1 << 17]byte var z11954 [1 << 17]byte var z11955 [1 << 17]byte var z11956 [1 << 17]byte var z11957 [1 << 17]byte var z11958 [1 << 17]byte var z11959 [1 << 17]byte var z11960 [1 << 17]byte var z11961 [1 << 17]byte var z11962 [1 << 17]byte var z11963 [1 << 17]byte var z11964 [1 << 17]byte var z11965 [1 << 17]byte var z11966 [1 << 17]byte var z11967 [1 << 17]byte var z11968 [1 << 17]byte var z11969 [1 << 17]byte var z11970 [1 << 17]byte var z11971 [1 << 17]byte var z11972 [1 << 17]byte var z11973 [1 << 17]byte var z11974 [1 << 17]byte var z11975 [1 << 17]byte var z11976 [1 << 17]byte var z11977 [1 << 17]byte var z11978 [1 << 17]byte var z11979 [1 << 17]byte var z11980 [1 << 17]byte var z11981 [1 << 17]byte var z11982 [1 << 17]byte var z11983 [1 << 17]byte var z11984 [1 << 17]byte var z11985 [1 << 17]byte var z11986 [1 << 17]byte var z11987 [1 << 17]byte var z11988 [1 << 17]byte var z11989 [1 << 17]byte var z11990 [1 << 17]byte var z11991 [1 << 17]byte var z11992 [1 << 17]byte var z11993 [1 << 17]byte var z11994 [1 << 17]byte var z11995 [1 << 17]byte var z11996 [1 << 17]byte var z11997 [1 << 17]byte var z11998 [1 << 17]byte var z11999 [1 << 17]byte var z12000 [1 << 17]byte var z12001 [1 << 17]byte var z12002 [1 << 17]byte var z12003 [1 << 17]byte var z12004 [1 << 17]byte var z12005 [1 << 17]byte var z12006 [1 << 17]byte var z12007 [1 << 17]byte var z12008 [1 << 17]byte var z12009 [1 << 17]byte var z12010 [1 << 17]byte var z12011 [1 << 17]byte var z12012 [1 << 17]byte var z12013 [1 << 17]byte var z12014 [1 << 17]byte var z12015 [1 << 17]byte var z12016 [1 << 17]byte var z12017 [1 << 17]byte var z12018 [1 << 17]byte var z12019 [1 << 17]byte var z12020 [1 << 17]byte var z12021 [1 << 17]byte var z12022 [1 << 17]byte var z12023 [1 << 17]byte var z12024 [1 << 17]byte var z12025 [1 << 17]byte var z12026 [1 << 17]byte var z12027 [1 << 17]byte var z12028 [1 << 17]byte var z12029 [1 << 17]byte var z12030 [1 << 17]byte var z12031 [1 << 17]byte var z12032 [1 << 17]byte var z12033 [1 << 17]byte var z12034 [1 << 17]byte var z12035 [1 << 17]byte var z12036 [1 << 17]byte var z12037 [1 << 17]byte var z12038 [1 << 17]byte var z12039 [1 << 17]byte var z12040 [1 << 17]byte var z12041 [1 << 17]byte var z12042 [1 << 17]byte var z12043 [1 << 17]byte var z12044 [1 << 17]byte var z12045 [1 << 17]byte var z12046 [1 << 17]byte var z12047 [1 << 17]byte var z12048 [1 << 17]byte var z12049 [1 << 17]byte var z12050 [1 << 17]byte var z12051 [1 << 17]byte var z12052 [1 << 17]byte var z12053 [1 << 17]byte var z12054 [1 << 17]byte var z12055 [1 << 17]byte var z12056 [1 << 17]byte var z12057 [1 << 17]byte var z12058 [1 << 17]byte var z12059 [1 << 17]byte var z12060 [1 << 17]byte var z12061 [1 << 17]byte var z12062 [1 << 17]byte var z12063 [1 << 17]byte var z12064 [1 << 17]byte var z12065 [1 << 17]byte var z12066 [1 << 17]byte var z12067 [1 << 17]byte var z12068 [1 << 17]byte var z12069 [1 << 17]byte var z12070 [1 << 17]byte var z12071 [1 << 17]byte var z12072 [1 << 17]byte var z12073 [1 << 17]byte var z12074 [1 << 17]byte var z12075 [1 << 17]byte var z12076 [1 << 17]byte var z12077 [1 << 17]byte var z12078 [1 << 17]byte var z12079 [1 << 17]byte var z12080 [1 << 17]byte var z12081 [1 << 17]byte var z12082 [1 << 17]byte var z12083 [1 << 17]byte var z12084 [1 << 17]byte var z12085 [1 << 17]byte var z12086 [1 << 17]byte var z12087 [1 << 17]byte var z12088 [1 << 17]byte var z12089 [1 << 17]byte var z12090 [1 << 17]byte var z12091 [1 << 17]byte var z12092 [1 << 17]byte var z12093 [1 << 17]byte var z12094 [1 << 17]byte var z12095 [1 << 17]byte var z12096 [1 << 17]byte var z12097 [1 << 17]byte var z12098 [1 << 17]byte var z12099 [1 << 17]byte var z12100 [1 << 17]byte var z12101 [1 << 17]byte var z12102 [1 << 17]byte var z12103 [1 << 17]byte var z12104 [1 << 17]byte var z12105 [1 << 17]byte var z12106 [1 << 17]byte var z12107 [1 << 17]byte var z12108 [1 << 17]byte var z12109 [1 << 17]byte var z12110 [1 << 17]byte var z12111 [1 << 17]byte var z12112 [1 << 17]byte var z12113 [1 << 17]byte var z12114 [1 << 17]byte var z12115 [1 << 17]byte var z12116 [1 << 17]byte var z12117 [1 << 17]byte var z12118 [1 << 17]byte var z12119 [1 << 17]byte var z12120 [1 << 17]byte var z12121 [1 << 17]byte var z12122 [1 << 17]byte var z12123 [1 << 17]byte var z12124 [1 << 17]byte var z12125 [1 << 17]byte var z12126 [1 << 17]byte var z12127 [1 << 17]byte var z12128 [1 << 17]byte var z12129 [1 << 17]byte var z12130 [1 << 17]byte var z12131 [1 << 17]byte var z12132 [1 << 17]byte var z12133 [1 << 17]byte var z12134 [1 << 17]byte var z12135 [1 << 17]byte var z12136 [1 << 17]byte var z12137 [1 << 17]byte var z12138 [1 << 17]byte var z12139 [1 << 17]byte var z12140 [1 << 17]byte var z12141 [1 << 17]byte var z12142 [1 << 17]byte var z12143 [1 << 17]byte var z12144 [1 << 17]byte var z12145 [1 << 17]byte var z12146 [1 << 17]byte var z12147 [1 << 17]byte var z12148 [1 << 17]byte var z12149 [1 << 17]byte var z12150 [1 << 17]byte var z12151 [1 << 17]byte var z12152 [1 << 17]byte var z12153 [1 << 17]byte var z12154 [1 << 17]byte var z12155 [1 << 17]byte var z12156 [1 << 17]byte var z12157 [1 << 17]byte var z12158 [1 << 17]byte var z12159 [1 << 17]byte var z12160 [1 << 17]byte var z12161 [1 << 17]byte var z12162 [1 << 17]byte var z12163 [1 << 17]byte var z12164 [1 << 17]byte var z12165 [1 << 17]byte var z12166 [1 << 17]byte var z12167 [1 << 17]byte var z12168 [1 << 17]byte var z12169 [1 << 17]byte var z12170 [1 << 17]byte var z12171 [1 << 17]byte var z12172 [1 << 17]byte var z12173 [1 << 17]byte var z12174 [1 << 17]byte var z12175 [1 << 17]byte var z12176 [1 << 17]byte var z12177 [1 << 17]byte var z12178 [1 << 17]byte var z12179 [1 << 17]byte var z12180 [1 << 17]byte var z12181 [1 << 17]byte var z12182 [1 << 17]byte var z12183 [1 << 17]byte var z12184 [1 << 17]byte var z12185 [1 << 17]byte var z12186 [1 << 17]byte var z12187 [1 << 17]byte var z12188 [1 << 17]byte var z12189 [1 << 17]byte var z12190 [1 << 17]byte var z12191 [1 << 17]byte var z12192 [1 << 17]byte var z12193 [1 << 17]byte var z12194 [1 << 17]byte var z12195 [1 << 17]byte var z12196 [1 << 17]byte var z12197 [1 << 17]byte var z12198 [1 << 17]byte var z12199 [1 << 17]byte var z12200 [1 << 17]byte var z12201 [1 << 17]byte var z12202 [1 << 17]byte var z12203 [1 << 17]byte var z12204 [1 << 17]byte var z12205 [1 << 17]byte var z12206 [1 << 17]byte var z12207 [1 << 17]byte var z12208 [1 << 17]byte var z12209 [1 << 17]byte var z12210 [1 << 17]byte var z12211 [1 << 17]byte var z12212 [1 << 17]byte var z12213 [1 << 17]byte var z12214 [1 << 17]byte var z12215 [1 << 17]byte var z12216 [1 << 17]byte var z12217 [1 << 17]byte var z12218 [1 << 17]byte var z12219 [1 << 17]byte var z12220 [1 << 17]byte var z12221 [1 << 17]byte var z12222 [1 << 17]byte var z12223 [1 << 17]byte var z12224 [1 << 17]byte var z12225 [1 << 17]byte var z12226 [1 << 17]byte var z12227 [1 << 17]byte var z12228 [1 << 17]byte var z12229 [1 << 17]byte var z12230 [1 << 17]byte var z12231 [1 << 17]byte var z12232 [1 << 17]byte var z12233 [1 << 17]byte var z12234 [1 << 17]byte var z12235 [1 << 17]byte var z12236 [1 << 17]byte var z12237 [1 << 17]byte var z12238 [1 << 17]byte var z12239 [1 << 17]byte var z12240 [1 << 17]byte var z12241 [1 << 17]byte var z12242 [1 << 17]byte var z12243 [1 << 17]byte var z12244 [1 << 17]byte var z12245 [1 << 17]byte var z12246 [1 << 17]byte var z12247 [1 << 17]byte var z12248 [1 << 17]byte var z12249 [1 << 17]byte var z12250 [1 << 17]byte var z12251 [1 << 17]byte var z12252 [1 << 17]byte var z12253 [1 << 17]byte var z12254 [1 << 17]byte var z12255 [1 << 17]byte var z12256 [1 << 17]byte var z12257 [1 << 17]byte var z12258 [1 << 17]byte var z12259 [1 << 17]byte var z12260 [1 << 17]byte var z12261 [1 << 17]byte var z12262 [1 << 17]byte var z12263 [1 << 17]byte var z12264 [1 << 17]byte var z12265 [1 << 17]byte var z12266 [1 << 17]byte var z12267 [1 << 17]byte var z12268 [1 << 17]byte var z12269 [1 << 17]byte var z12270 [1 << 17]byte var z12271 [1 << 17]byte var z12272 [1 << 17]byte var z12273 [1 << 17]byte var z12274 [1 << 17]byte var z12275 [1 << 17]byte var z12276 [1 << 17]byte var z12277 [1 << 17]byte var z12278 [1 << 17]byte var z12279 [1 << 17]byte var z12280 [1 << 17]byte var z12281 [1 << 17]byte var z12282 [1 << 17]byte var z12283 [1 << 17]byte var z12284 [1 << 17]byte var z12285 [1 << 17]byte var z12286 [1 << 17]byte var z12287 [1 << 17]byte var z12288 [1 << 17]byte var z12289 [1 << 17]byte var z12290 [1 << 17]byte var z12291 [1 << 17]byte var z12292 [1 << 17]byte var z12293 [1 << 17]byte var z12294 [1 << 17]byte var z12295 [1 << 17]byte var z12296 [1 << 17]byte var z12297 [1 << 17]byte var z12298 [1 << 17]byte var z12299 [1 << 17]byte var z12300 [1 << 17]byte var z12301 [1 << 17]byte var z12302 [1 << 17]byte var z12303 [1 << 17]byte var z12304 [1 << 17]byte var z12305 [1 << 17]byte var z12306 [1 << 17]byte var z12307 [1 << 17]byte var z12308 [1 << 17]byte var z12309 [1 << 17]byte var z12310 [1 << 17]byte var z12311 [1 << 17]byte var z12312 [1 << 17]byte var z12313 [1 << 17]byte var z12314 [1 << 17]byte var z12315 [1 << 17]byte var z12316 [1 << 17]byte var z12317 [1 << 17]byte var z12318 [1 << 17]byte var z12319 [1 << 17]byte var z12320 [1 << 17]byte var z12321 [1 << 17]byte var z12322 [1 << 17]byte var z12323 [1 << 17]byte var z12324 [1 << 17]byte var z12325 [1 << 17]byte var z12326 [1 << 17]byte var z12327 [1 << 17]byte var z12328 [1 << 17]byte var z12329 [1 << 17]byte var z12330 [1 << 17]byte var z12331 [1 << 17]byte var z12332 [1 << 17]byte var z12333 [1 << 17]byte var z12334 [1 << 17]byte var z12335 [1 << 17]byte var z12336 [1 << 17]byte var z12337 [1 << 17]byte var z12338 [1 << 17]byte var z12339 [1 << 17]byte var z12340 [1 << 17]byte var z12341 [1 << 17]byte var z12342 [1 << 17]byte var z12343 [1 << 17]byte var z12344 [1 << 17]byte var z12345 [1 << 17]byte var z12346 [1 << 17]byte var z12347 [1 << 17]byte var z12348 [1 << 17]byte var z12349 [1 << 17]byte var z12350 [1 << 17]byte var z12351 [1 << 17]byte var z12352 [1 << 17]byte var z12353 [1 << 17]byte var z12354 [1 << 17]byte var z12355 [1 << 17]byte var z12356 [1 << 17]byte var z12357 [1 << 17]byte var z12358 [1 << 17]byte var z12359 [1 << 17]byte var z12360 [1 << 17]byte var z12361 [1 << 17]byte var z12362 [1 << 17]byte var z12363 [1 << 17]byte var z12364 [1 << 17]byte var z12365 [1 << 17]byte var z12366 [1 << 17]byte var z12367 [1 << 17]byte var z12368 [1 << 17]byte var z12369 [1 << 17]byte var z12370 [1 << 17]byte var z12371 [1 << 17]byte var z12372 [1 << 17]byte var z12373 [1 << 17]byte var z12374 [1 << 17]byte var z12375 [1 << 17]byte var z12376 [1 << 17]byte var z12377 [1 << 17]byte var z12378 [1 << 17]byte var z12379 [1 << 17]byte var z12380 [1 << 17]byte var z12381 [1 << 17]byte var z12382 [1 << 17]byte var z12383 [1 << 17]byte var z12384 [1 << 17]byte var z12385 [1 << 17]byte var z12386 [1 << 17]byte var z12387 [1 << 17]byte var z12388 [1 << 17]byte var z12389 [1 << 17]byte var z12390 [1 << 17]byte var z12391 [1 << 17]byte var z12392 [1 << 17]byte var z12393 [1 << 17]byte var z12394 [1 << 17]byte var z12395 [1 << 17]byte var z12396 [1 << 17]byte var z12397 [1 << 17]byte var z12398 [1 << 17]byte var z12399 [1 << 17]byte var z12400 [1 << 17]byte var z12401 [1 << 17]byte var z12402 [1 << 17]byte var z12403 [1 << 17]byte var z12404 [1 << 17]byte var z12405 [1 << 17]byte var z12406 [1 << 17]byte var z12407 [1 << 17]byte var z12408 [1 << 17]byte var z12409 [1 << 17]byte var z12410 [1 << 17]byte var z12411 [1 << 17]byte var z12412 [1 << 17]byte var z12413 [1 << 17]byte var z12414 [1 << 17]byte var z12415 [1 << 17]byte var z12416 [1 << 17]byte var z12417 [1 << 17]byte var z12418 [1 << 17]byte var z12419 [1 << 17]byte var z12420 [1 << 17]byte var z12421 [1 << 17]byte var z12422 [1 << 17]byte var z12423 [1 << 17]byte var z12424 [1 << 17]byte var z12425 [1 << 17]byte var z12426 [1 << 17]byte var z12427 [1 << 17]byte var z12428 [1 << 17]byte var z12429 [1 << 17]byte var z12430 [1 << 17]byte var z12431 [1 << 17]byte var z12432 [1 << 17]byte var z12433 [1 << 17]byte var z12434 [1 << 17]byte var z12435 [1 << 17]byte var z12436 [1 << 17]byte var z12437 [1 << 17]byte var z12438 [1 << 17]byte var z12439 [1 << 17]byte var z12440 [1 << 17]byte var z12441 [1 << 17]byte var z12442 [1 << 17]byte var z12443 [1 << 17]byte var z12444 [1 << 17]byte var z12445 [1 << 17]byte var z12446 [1 << 17]byte var z12447 [1 << 17]byte var z12448 [1 << 17]byte var z12449 [1 << 17]byte var z12450 [1 << 17]byte var z12451 [1 << 17]byte var z12452 [1 << 17]byte var z12453 [1 << 17]byte var z12454 [1 << 17]byte var z12455 [1 << 17]byte var z12456 [1 << 17]byte var z12457 [1 << 17]byte var z12458 [1 << 17]byte var z12459 [1 << 17]byte var z12460 [1 << 17]byte var z12461 [1 << 17]byte var z12462 [1 << 17]byte var z12463 [1 << 17]byte var z12464 [1 << 17]byte var z12465 [1 << 17]byte var z12466 [1 << 17]byte var z12467 [1 << 17]byte var z12468 [1 << 17]byte var z12469 [1 << 17]byte var z12470 [1 << 17]byte var z12471 [1 << 17]byte var z12472 [1 << 17]byte var z12473 [1 << 17]byte var z12474 [1 << 17]byte var z12475 [1 << 17]byte var z12476 [1 << 17]byte var z12477 [1 << 17]byte var z12478 [1 << 17]byte var z12479 [1 << 17]byte var z12480 [1 << 17]byte var z12481 [1 << 17]byte var z12482 [1 << 17]byte var z12483 [1 << 17]byte var z12484 [1 << 17]byte var z12485 [1 << 17]byte var z12486 [1 << 17]byte var z12487 [1 << 17]byte var z12488 [1 << 17]byte var z12489 [1 << 17]byte var z12490 [1 << 17]byte var z12491 [1 << 17]byte var z12492 [1 << 17]byte var z12493 [1 << 17]byte var z12494 [1 << 17]byte var z12495 [1 << 17]byte var z12496 [1 << 17]byte var z12497 [1 << 17]byte var z12498 [1 << 17]byte var z12499 [1 << 17]byte var z12500 [1 << 17]byte var z12501 [1 << 17]byte var z12502 [1 << 17]byte var z12503 [1 << 17]byte var z12504 [1 << 17]byte var z12505 [1 << 17]byte var z12506 [1 << 17]byte var z12507 [1 << 17]byte var z12508 [1 << 17]byte var z12509 [1 << 17]byte var z12510 [1 << 17]byte var z12511 [1 << 17]byte var z12512 [1 << 17]byte var z12513 [1 << 17]byte var z12514 [1 << 17]byte var z12515 [1 << 17]byte var z12516 [1 << 17]byte var z12517 [1 << 17]byte var z12518 [1 << 17]byte var z12519 [1 << 17]byte var z12520 [1 << 17]byte var z12521 [1 << 17]byte var z12522 [1 << 17]byte var z12523 [1 << 17]byte var z12524 [1 << 17]byte var z12525 [1 << 17]byte var z12526 [1 << 17]byte var z12527 [1 << 17]byte var z12528 [1 << 17]byte var z12529 [1 << 17]byte var z12530 [1 << 17]byte var z12531 [1 << 17]byte var z12532 [1 << 17]byte var z12533 [1 << 17]byte var z12534 [1 << 17]byte var z12535 [1 << 17]byte var z12536 [1 << 17]byte var z12537 [1 << 17]byte var z12538 [1 << 17]byte var z12539 [1 << 17]byte var z12540 [1 << 17]byte var z12541 [1 << 17]byte var z12542 [1 << 17]byte var z12543 [1 << 17]byte var z12544 [1 << 17]byte var z12545 [1 << 17]byte var z12546 [1 << 17]byte var z12547 [1 << 17]byte var z12548 [1 << 17]byte var z12549 [1 << 17]byte var z12550 [1 << 17]byte var z12551 [1 << 17]byte var z12552 [1 << 17]byte var z12553 [1 << 17]byte var z12554 [1 << 17]byte var z12555 [1 << 17]byte var z12556 [1 << 17]byte var z12557 [1 << 17]byte var z12558 [1 << 17]byte var z12559 [1 << 17]byte var z12560 [1 << 17]byte var z12561 [1 << 17]byte var z12562 [1 << 17]byte var z12563 [1 << 17]byte var z12564 [1 << 17]byte var z12565 [1 << 17]byte var z12566 [1 << 17]byte var z12567 [1 << 17]byte var z12568 [1 << 17]byte var z12569 [1 << 17]byte var z12570 [1 << 17]byte var z12571 [1 << 17]byte var z12572 [1 << 17]byte var z12573 [1 << 17]byte var z12574 [1 << 17]byte var z12575 [1 << 17]byte var z12576 [1 << 17]byte var z12577 [1 << 17]byte var z12578 [1 << 17]byte var z12579 [1 << 17]byte var z12580 [1 << 17]byte var z12581 [1 << 17]byte var z12582 [1 << 17]byte var z12583 [1 << 17]byte var z12584 [1 << 17]byte var z12585 [1 << 17]byte var z12586 [1 << 17]byte var z12587 [1 << 17]byte var z12588 [1 << 17]byte var z12589 [1 << 17]byte var z12590 [1 << 17]byte var z12591 [1 << 17]byte var z12592 [1 << 17]byte var z12593 [1 << 17]byte var z12594 [1 << 17]byte var z12595 [1 << 17]byte var z12596 [1 << 17]byte var z12597 [1 << 17]byte var z12598 [1 << 17]byte var z12599 [1 << 17]byte var z12600 [1 << 17]byte var z12601 [1 << 17]byte var z12602 [1 << 17]byte var z12603 [1 << 17]byte var z12604 [1 << 17]byte var z12605 [1 << 17]byte var z12606 [1 << 17]byte var z12607 [1 << 17]byte var z12608 [1 << 17]byte var z12609 [1 << 17]byte var z12610 [1 << 17]byte var z12611 [1 << 17]byte var z12612 [1 << 17]byte var z12613 [1 << 17]byte var z12614 [1 << 17]byte var z12615 [1 << 17]byte var z12616 [1 << 17]byte var z12617 [1 << 17]byte var z12618 [1 << 17]byte var z12619 [1 << 17]byte var z12620 [1 << 17]byte var z12621 [1 << 17]byte var z12622 [1 << 17]byte var z12623 [1 << 17]byte var z12624 [1 << 17]byte var z12625 [1 << 17]byte var z12626 [1 << 17]byte var z12627 [1 << 17]byte var z12628 [1 << 17]byte var z12629 [1 << 17]byte var z12630 [1 << 17]byte var z12631 [1 << 17]byte var z12632 [1 << 17]byte var z12633 [1 << 17]byte var z12634 [1 << 17]byte var z12635 [1 << 17]byte var z12636 [1 << 17]byte var z12637 [1 << 17]byte var z12638 [1 << 17]byte var z12639 [1 << 17]byte var z12640 [1 << 17]byte var z12641 [1 << 17]byte var z12642 [1 << 17]byte var z12643 [1 << 17]byte var z12644 [1 << 17]byte var z12645 [1 << 17]byte var z12646 [1 << 17]byte var z12647 [1 << 17]byte var z12648 [1 << 17]byte var z12649 [1 << 17]byte var z12650 [1 << 17]byte var z12651 [1 << 17]byte var z12652 [1 << 17]byte var z12653 [1 << 17]byte var z12654 [1 << 17]byte var z12655 [1 << 17]byte var z12656 [1 << 17]byte var z12657 [1 << 17]byte var z12658 [1 << 17]byte var z12659 [1 << 17]byte var z12660 [1 << 17]byte var z12661 [1 << 17]byte var z12662 [1 << 17]byte var z12663 [1 << 17]byte var z12664 [1 << 17]byte var z12665 [1 << 17]byte var z12666 [1 << 17]byte var z12667 [1 << 17]byte var z12668 [1 << 17]byte var z12669 [1 << 17]byte var z12670 [1 << 17]byte var z12671 [1 << 17]byte var z12672 [1 << 17]byte var z12673 [1 << 17]byte var z12674 [1 << 17]byte var z12675 [1 << 17]byte var z12676 [1 << 17]byte var z12677 [1 << 17]byte var z12678 [1 << 17]byte var z12679 [1 << 17]byte var z12680 [1 << 17]byte var z12681 [1 << 17]byte var z12682 [1 << 17]byte var z12683 [1 << 17]byte var z12684 [1 << 17]byte var z12685 [1 << 17]byte var z12686 [1 << 17]byte var z12687 [1 << 17]byte var z12688 [1 << 17]byte var z12689 [1 << 17]byte var z12690 [1 << 17]byte var z12691 [1 << 17]byte var z12692 [1 << 17]byte var z12693 [1 << 17]byte var z12694 [1 << 17]byte var z12695 [1 << 17]byte var z12696 [1 << 17]byte var z12697 [1 << 17]byte var z12698 [1 << 17]byte var z12699 [1 << 17]byte var z12700 [1 << 17]byte var z12701 [1 << 17]byte var z12702 [1 << 17]byte var z12703 [1 << 17]byte var z12704 [1 << 17]byte var z12705 [1 << 17]byte var z12706 [1 << 17]byte var z12707 [1 << 17]byte var z12708 [1 << 17]byte var z12709 [1 << 17]byte var z12710 [1 << 17]byte var z12711 [1 << 17]byte var z12712 [1 << 17]byte var z12713 [1 << 17]byte var z12714 [1 << 17]byte var z12715 [1 << 17]byte var z12716 [1 << 17]byte var z12717 [1 << 17]byte var z12718 [1 << 17]byte var z12719 [1 << 17]byte var z12720 [1 << 17]byte var z12721 [1 << 17]byte var z12722 [1 << 17]byte var z12723 [1 << 17]byte var z12724 [1 << 17]byte var z12725 [1 << 17]byte var z12726 [1 << 17]byte var z12727 [1 << 17]byte var z12728 [1 << 17]byte var z12729 [1 << 17]byte var z12730 [1 << 17]byte var z12731 [1 << 17]byte var z12732 [1 << 17]byte var z12733 [1 << 17]byte var z12734 [1 << 17]byte var z12735 [1 << 17]byte var z12736 [1 << 17]byte var z12737 [1 << 17]byte var z12738 [1 << 17]byte var z12739 [1 << 17]byte var z12740 [1 << 17]byte var z12741 [1 << 17]byte var z12742 [1 << 17]byte var z12743 [1 << 17]byte var z12744 [1 << 17]byte var z12745 [1 << 17]byte var z12746 [1 << 17]byte var z12747 [1 << 17]byte var z12748 [1 << 17]byte var z12749 [1 << 17]byte var z12750 [1 << 17]byte var z12751 [1 << 17]byte var z12752 [1 << 17]byte var z12753 [1 << 17]byte var z12754 [1 << 17]byte var z12755 [1 << 17]byte var z12756 [1 << 17]byte var z12757 [1 << 17]byte var z12758 [1 << 17]byte var z12759 [1 << 17]byte var z12760 [1 << 17]byte var z12761 [1 << 17]byte var z12762 [1 << 17]byte var z12763 [1 << 17]byte var z12764 [1 << 17]byte var z12765 [1 << 17]byte var z12766 [1 << 17]byte var z12767 [1 << 17]byte var z12768 [1 << 17]byte var z12769 [1 << 17]byte var z12770 [1 << 17]byte var z12771 [1 << 17]byte var z12772 [1 << 17]byte var z12773 [1 << 17]byte var z12774 [1 << 17]byte var z12775 [1 << 17]byte var z12776 [1 << 17]byte var z12777 [1 << 17]byte var z12778 [1 << 17]byte var z12779 [1 << 17]byte var z12780 [1 << 17]byte var z12781 [1 << 17]byte var z12782 [1 << 17]byte var z12783 [1 << 17]byte var z12784 [1 << 17]byte var z12785 [1 << 17]byte var z12786 [1 << 17]byte var z12787 [1 << 17]byte var z12788 [1 << 17]byte var z12789 [1 << 17]byte var z12790 [1 << 17]byte var z12791 [1 << 17]byte var z12792 [1 << 17]byte var z12793 [1 << 17]byte var z12794 [1 << 17]byte var z12795 [1 << 17]byte var z12796 [1 << 17]byte var z12797 [1 << 17]byte var z12798 [1 << 17]byte var z12799 [1 << 17]byte var z12800 [1 << 17]byte var z12801 [1 << 17]byte var z12802 [1 << 17]byte var z12803 [1 << 17]byte var z12804 [1 << 17]byte var z12805 [1 << 17]byte var z12806 [1 << 17]byte var z12807 [1 << 17]byte var z12808 [1 << 17]byte var z12809 [1 << 17]byte var z12810 [1 << 17]byte var z12811 [1 << 17]byte var z12812 [1 << 17]byte var z12813 [1 << 17]byte var z12814 [1 << 17]byte var z12815 [1 << 17]byte var z12816 [1 << 17]byte var z12817 [1 << 17]byte var z12818 [1 << 17]byte var z12819 [1 << 17]byte var z12820 [1 << 17]byte var z12821 [1 << 17]byte var z12822 [1 << 17]byte var z12823 [1 << 17]byte var z12824 [1 << 17]byte var z12825 [1 << 17]byte var z12826 [1 << 17]byte var z12827 [1 << 17]byte var z12828 [1 << 17]byte var z12829 [1 << 17]byte var z12830 [1 << 17]byte var z12831 [1 << 17]byte var z12832 [1 << 17]byte var z12833 [1 << 17]byte var z12834 [1 << 17]byte var z12835 [1 << 17]byte var z12836 [1 << 17]byte var z12837 [1 << 17]byte var z12838 [1 << 17]byte var z12839 [1 << 17]byte var z12840 [1 << 17]byte var z12841 [1 << 17]byte var z12842 [1 << 17]byte var z12843 [1 << 17]byte var z12844 [1 << 17]byte var z12845 [1 << 17]byte var z12846 [1 << 17]byte var z12847 [1 << 17]byte var z12848 [1 << 17]byte var z12849 [1 << 17]byte var z12850 [1 << 17]byte var z12851 [1 << 17]byte var z12852 [1 << 17]byte var z12853 [1 << 17]byte var z12854 [1 << 17]byte var z12855 [1 << 17]byte var z12856 [1 << 17]byte var z12857 [1 << 17]byte var z12858 [1 << 17]byte var z12859 [1 << 17]byte var z12860 [1 << 17]byte var z12861 [1 << 17]byte var z12862 [1 << 17]byte var z12863 [1 << 17]byte var z12864 [1 << 17]byte var z12865 [1 << 17]byte var z12866 [1 << 17]byte var z12867 [1 << 17]byte var z12868 [1 << 17]byte var z12869 [1 << 17]byte var z12870 [1 << 17]byte var z12871 [1 << 17]byte var z12872 [1 << 17]byte var z12873 [1 << 17]byte var z12874 [1 << 17]byte var z12875 [1 << 17]byte var z12876 [1 << 17]byte var z12877 [1 << 17]byte var z12878 [1 << 17]byte var z12879 [1 << 17]byte var z12880 [1 << 17]byte var z12881 [1 << 17]byte var z12882 [1 << 17]byte var z12883 [1 << 17]byte var z12884 [1 << 17]byte var z12885 [1 << 17]byte var z12886 [1 << 17]byte var z12887 [1 << 17]byte var z12888 [1 << 17]byte var z12889 [1 << 17]byte var z12890 [1 << 17]byte var z12891 [1 << 17]byte var z12892 [1 << 17]byte var z12893 [1 << 17]byte var z12894 [1 << 17]byte var z12895 [1 << 17]byte var z12896 [1 << 17]byte var z12897 [1 << 17]byte var z12898 [1 << 17]byte var z12899 [1 << 17]byte var z12900 [1 << 17]byte var z12901 [1 << 17]byte var z12902 [1 << 17]byte var z12903 [1 << 17]byte var z12904 [1 << 17]byte var z12905 [1 << 17]byte var z12906 [1 << 17]byte var z12907 [1 << 17]byte var z12908 [1 << 17]byte var z12909 [1 << 17]byte var z12910 [1 << 17]byte var z12911 [1 << 17]byte var z12912 [1 << 17]byte var z12913 [1 << 17]byte var z12914 [1 << 17]byte var z12915 [1 << 17]byte var z12916 [1 << 17]byte var z12917 [1 << 17]byte var z12918 [1 << 17]byte var z12919 [1 << 17]byte var z12920 [1 << 17]byte var z12921 [1 << 17]byte var z12922 [1 << 17]byte var z12923 [1 << 17]byte var z12924 [1 << 17]byte var z12925 [1 << 17]byte var z12926 [1 << 17]byte var z12927 [1 << 17]byte var z12928 [1 << 17]byte var z12929 [1 << 17]byte var z12930 [1 << 17]byte var z12931 [1 << 17]byte var z12932 [1 << 17]byte var z12933 [1 << 17]byte var z12934 [1 << 17]byte var z12935 [1 << 17]byte var z12936 [1 << 17]byte var z12937 [1 << 17]byte var z12938 [1 << 17]byte var z12939 [1 << 17]byte var z12940 [1 << 17]byte var z12941 [1 << 17]byte var z12942 [1 << 17]byte var z12943 [1 << 17]byte var z12944 [1 << 17]byte var z12945 [1 << 17]byte var z12946 [1 << 17]byte var z12947 [1 << 17]byte var z12948 [1 << 17]byte var z12949 [1 << 17]byte var z12950 [1 << 17]byte var z12951 [1 << 17]byte var z12952 [1 << 17]byte var z12953 [1 << 17]byte var z12954 [1 << 17]byte var z12955 [1 << 17]byte var z12956 [1 << 17]byte var z12957 [1 << 17]byte var z12958 [1 << 17]byte var z12959 [1 << 17]byte var z12960 [1 << 17]byte var z12961 [1 << 17]byte var z12962 [1 << 17]byte var z12963 [1 << 17]byte var z12964 [1 << 17]byte var z12965 [1 << 17]byte var z12966 [1 << 17]byte var z12967 [1 << 17]byte var z12968 [1 << 17]byte var z12969 [1 << 17]byte var z12970 [1 << 17]byte var z12971 [1 << 17]byte var z12972 [1 << 17]byte var z12973 [1 << 17]byte var z12974 [1 << 17]byte var z12975 [1 << 17]byte var z12976 [1 << 17]byte var z12977 [1 << 17]byte var z12978 [1 << 17]byte var z12979 [1 << 17]byte var z12980 [1 << 17]byte var z12981 [1 << 17]byte var z12982 [1 << 17]byte var z12983 [1 << 17]byte var z12984 [1 << 17]byte var z12985 [1 << 17]byte var z12986 [1 << 17]byte var z12987 [1 << 17]byte var z12988 [1 << 17]byte var z12989 [1 << 17]byte var z12990 [1 << 17]byte var z12991 [1 << 17]byte var z12992 [1 << 17]byte var z12993 [1 << 17]byte var z12994 [1 << 17]byte var z12995 [1 << 17]byte var z12996 [1 << 17]byte var z12997 [1 << 17]byte var z12998 [1 << 17]byte var z12999 [1 << 17]byte var z13000 [1 << 17]byte var z13001 [1 << 17]byte var z13002 [1 << 17]byte var z13003 [1 << 17]byte var z13004 [1 << 17]byte var z13005 [1 << 17]byte var z13006 [1 << 17]byte var z13007 [1 << 17]byte var z13008 [1 << 17]byte var z13009 [1 << 17]byte var z13010 [1 << 17]byte var z13011 [1 << 17]byte var z13012 [1 << 17]byte var z13013 [1 << 17]byte var z13014 [1 << 17]byte var z13015 [1 << 17]byte var z13016 [1 << 17]byte var z13017 [1 << 17]byte var z13018 [1 << 17]byte var z13019 [1 << 17]byte var z13020 [1 << 17]byte var z13021 [1 << 17]byte var z13022 [1 << 17]byte var z13023 [1 << 17]byte var z13024 [1 << 17]byte var z13025 [1 << 17]byte var z13026 [1 << 17]byte var z13027 [1 << 17]byte var z13028 [1 << 17]byte var z13029 [1 << 17]byte var z13030 [1 << 17]byte var z13031 [1 << 17]byte var z13032 [1 << 17]byte var z13033 [1 << 17]byte var z13034 [1 << 17]byte var z13035 [1 << 17]byte var z13036 [1 << 17]byte var z13037 [1 << 17]byte var z13038 [1 << 17]byte var z13039 [1 << 17]byte var z13040 [1 << 17]byte var z13041 [1 << 17]byte var z13042 [1 << 17]byte var z13043 [1 << 17]byte var z13044 [1 << 17]byte var z13045 [1 << 17]byte var z13046 [1 << 17]byte var z13047 [1 << 17]byte var z13048 [1 << 17]byte var z13049 [1 << 17]byte var z13050 [1 << 17]byte var z13051 [1 << 17]byte var z13052 [1 << 17]byte var z13053 [1 << 17]byte var z13054 [1 << 17]byte var z13055 [1 << 17]byte var z13056 [1 << 17]byte var z13057 [1 << 17]byte var z13058 [1 << 17]byte var z13059 [1 << 17]byte var z13060 [1 << 17]byte var z13061 [1 << 17]byte var z13062 [1 << 17]byte var z13063 [1 << 17]byte var z13064 [1 << 17]byte var z13065 [1 << 17]byte var z13066 [1 << 17]byte var z13067 [1 << 17]byte var z13068 [1 << 17]byte var z13069 [1 << 17]byte var z13070 [1 << 17]byte var z13071 [1 << 17]byte var z13072 [1 << 17]byte var z13073 [1 << 17]byte var z13074 [1 << 17]byte var z13075 [1 << 17]byte var z13076 [1 << 17]byte var z13077 [1 << 17]byte var z13078 [1 << 17]byte var z13079 [1 << 17]byte var z13080 [1 << 17]byte var z13081 [1 << 17]byte var z13082 [1 << 17]byte var z13083 [1 << 17]byte var z13084 [1 << 17]byte var z13085 [1 << 17]byte var z13086 [1 << 17]byte var z13087 [1 << 17]byte var z13088 [1 << 17]byte var z13089 [1 << 17]byte var z13090 [1 << 17]byte var z13091 [1 << 17]byte var z13092 [1 << 17]byte var z13093 [1 << 17]byte var z13094 [1 << 17]byte var z13095 [1 << 17]byte var z13096 [1 << 17]byte var z13097 [1 << 17]byte var z13098 [1 << 17]byte var z13099 [1 << 17]byte var z13100 [1 << 17]byte var z13101 [1 << 17]byte var z13102 [1 << 17]byte var z13103 [1 << 17]byte var z13104 [1 << 17]byte var z13105 [1 << 17]byte var z13106 [1 << 17]byte var z13107 [1 << 17]byte var z13108 [1 << 17]byte var z13109 [1 << 17]byte var z13110 [1 << 17]byte var z13111 [1 << 17]byte var z13112 [1 << 17]byte var z13113 [1 << 17]byte var z13114 [1 << 17]byte var z13115 [1 << 17]byte var z13116 [1 << 17]byte var z13117 [1 << 17]byte var z13118 [1 << 17]byte var z13119 [1 << 17]byte var z13120 [1 << 17]byte var z13121 [1 << 17]byte var z13122 [1 << 17]byte var z13123 [1 << 17]byte var z13124 [1 << 17]byte var z13125 [1 << 17]byte var z13126 [1 << 17]byte var z13127 [1 << 17]byte var z13128 [1 << 17]byte var z13129 [1 << 17]byte var z13130 [1 << 17]byte var z13131 [1 << 17]byte var z13132 [1 << 17]byte var z13133 [1 << 17]byte var z13134 [1 << 17]byte var z13135 [1 << 17]byte var z13136 [1 << 17]byte var z13137 [1 << 17]byte var z13138 [1 << 17]byte var z13139 [1 << 17]byte var z13140 [1 << 17]byte var z13141 [1 << 17]byte var z13142 [1 << 17]byte var z13143 [1 << 17]byte var z13144 [1 << 17]byte var z13145 [1 << 17]byte var z13146 [1 << 17]byte var z13147 [1 << 17]byte var z13148 [1 << 17]byte var z13149 [1 << 17]byte var z13150 [1 << 17]byte var z13151 [1 << 17]byte var z13152 [1 << 17]byte var z13153 [1 << 17]byte var z13154 [1 << 17]byte var z13155 [1 << 17]byte var z13156 [1 << 17]byte var z13157 [1 << 17]byte var z13158 [1 << 17]byte var z13159 [1 << 17]byte var z13160 [1 << 17]byte var z13161 [1 << 17]byte var z13162 [1 << 17]byte var z13163 [1 << 17]byte var z13164 [1 << 17]byte var z13165 [1 << 17]byte var z13166 [1 << 17]byte var z13167 [1 << 17]byte var z13168 [1 << 17]byte var z13169 [1 << 17]byte var z13170 [1 << 17]byte var z13171 [1 << 17]byte var z13172 [1 << 17]byte var z13173 [1 << 17]byte var z13174 [1 << 17]byte var z13175 [1 << 17]byte var z13176 [1 << 17]byte var z13177 [1 << 17]byte var z13178 [1 << 17]byte var z13179 [1 << 17]byte var z13180 [1 << 17]byte var z13181 [1 << 17]byte var z13182 [1 << 17]byte var z13183 [1 << 17]byte var z13184 [1 << 17]byte var z13185 [1 << 17]byte var z13186 [1 << 17]byte var z13187 [1 << 17]byte var z13188 [1 << 17]byte var z13189 [1 << 17]byte var z13190 [1 << 17]byte var z13191 [1 << 17]byte var z13192 [1 << 17]byte var z13193 [1 << 17]byte var z13194 [1 << 17]byte var z13195 [1 << 17]byte var z13196 [1 << 17]byte var z13197 [1 << 17]byte var z13198 [1 << 17]byte var z13199 [1 << 17]byte var z13200 [1 << 17]byte var z13201 [1 << 17]byte var z13202 [1 << 17]byte var z13203 [1 << 17]byte var z13204 [1 << 17]byte var z13205 [1 << 17]byte var z13206 [1 << 17]byte var z13207 [1 << 17]byte var z13208 [1 << 17]byte var z13209 [1 << 17]byte var z13210 [1 << 17]byte var z13211 [1 << 17]byte var z13212 [1 << 17]byte var z13213 [1 << 17]byte var z13214 [1 << 17]byte var z13215 [1 << 17]byte var z13216 [1 << 17]byte var z13217 [1 << 17]byte var z13218 [1 << 17]byte var z13219 [1 << 17]byte var z13220 [1 << 17]byte var z13221 [1 << 17]byte var z13222 [1 << 17]byte var z13223 [1 << 17]byte var z13224 [1 << 17]byte var z13225 [1 << 17]byte var z13226 [1 << 17]byte var z13227 [1 << 17]byte var z13228 [1 << 17]byte var z13229 [1 << 17]byte var z13230 [1 << 17]byte var z13231 [1 << 17]byte var z13232 [1 << 17]byte var z13233 [1 << 17]byte var z13234 [1 << 17]byte var z13235 [1 << 17]byte var z13236 [1 << 17]byte var z13237 [1 << 17]byte var z13238 [1 << 17]byte var z13239 [1 << 17]byte var z13240 [1 << 17]byte var z13241 [1 << 17]byte var z13242 [1 << 17]byte var z13243 [1 << 17]byte var z13244 [1 << 17]byte var z13245 [1 << 17]byte var z13246 [1 << 17]byte var z13247 [1 << 17]byte var z13248 [1 << 17]byte var z13249 [1 << 17]byte var z13250 [1 << 17]byte var z13251 [1 << 17]byte var z13252 [1 << 17]byte var z13253 [1 << 17]byte var z13254 [1 << 17]byte var z13255 [1 << 17]byte var z13256 [1 << 17]byte var z13257 [1 << 17]byte var z13258 [1 << 17]byte var z13259 [1 << 17]byte var z13260 [1 << 17]byte var z13261 [1 << 17]byte var z13262 [1 << 17]byte var z13263 [1 << 17]byte var z13264 [1 << 17]byte var z13265 [1 << 17]byte var z13266 [1 << 17]byte var z13267 [1 << 17]byte var z13268 [1 << 17]byte var z13269 [1 << 17]byte var z13270 [1 << 17]byte var z13271 [1 << 17]byte var z13272 [1 << 17]byte var z13273 [1 << 17]byte var z13274 [1 << 17]byte var z13275 [1 << 17]byte var z13276 [1 << 17]byte var z13277 [1 << 17]byte var z13278 [1 << 17]byte var z13279 [1 << 17]byte var z13280 [1 << 17]byte var z13281 [1 << 17]byte var z13282 [1 << 17]byte var z13283 [1 << 17]byte var z13284 [1 << 17]byte var z13285 [1 << 17]byte var z13286 [1 << 17]byte var z13287 [1 << 17]byte var z13288 [1 << 17]byte var z13289 [1 << 17]byte var z13290 [1 << 17]byte var z13291 [1 << 17]byte var z13292 [1 << 17]byte var z13293 [1 << 17]byte var z13294 [1 << 17]byte var z13295 [1 << 17]byte var z13296 [1 << 17]byte var z13297 [1 << 17]byte var z13298 [1 << 17]byte var z13299 [1 << 17]byte var z13300 [1 << 17]byte var z13301 [1 << 17]byte var z13302 [1 << 17]byte var z13303 [1 << 17]byte var z13304 [1 << 17]byte var z13305 [1 << 17]byte var z13306 [1 << 17]byte var z13307 [1 << 17]byte var z13308 [1 << 17]byte var z13309 [1 << 17]byte var z13310 [1 << 17]byte var z13311 [1 << 17]byte var z13312 [1 << 17]byte var z13313 [1 << 17]byte var z13314 [1 << 17]byte var z13315 [1 << 17]byte var z13316 [1 << 17]byte var z13317 [1 << 17]byte var z13318 [1 << 17]byte var z13319 [1 << 17]byte var z13320 [1 << 17]byte var z13321 [1 << 17]byte var z13322 [1 << 17]byte var z13323 [1 << 17]byte var z13324 [1 << 17]byte var z13325 [1 << 17]byte var z13326 [1 << 17]byte var z13327 [1 << 17]byte var z13328 [1 << 17]byte var z13329 [1 << 17]byte var z13330 [1 << 17]byte var z13331 [1 << 17]byte var z13332 [1 << 17]byte var z13333 [1 << 17]byte var z13334 [1 << 17]byte var z13335 [1 << 17]byte var z13336 [1 << 17]byte var z13337 [1 << 17]byte var z13338 [1 << 17]byte var z13339 [1 << 17]byte var z13340 [1 << 17]byte var z13341 [1 << 17]byte var z13342 [1 << 17]byte var z13343 [1 << 17]byte var z13344 [1 << 17]byte var z13345 [1 << 17]byte var z13346 [1 << 17]byte var z13347 [1 << 17]byte var z13348 [1 << 17]byte var z13349 [1 << 17]byte var z13350 [1 << 17]byte var z13351 [1 << 17]byte var z13352 [1 << 17]byte var z13353 [1 << 17]byte var z13354 [1 << 17]byte var z13355 [1 << 17]byte var z13356 [1 << 17]byte var z13357 [1 << 17]byte var z13358 [1 << 17]byte var z13359 [1 << 17]byte var z13360 [1 << 17]byte var z13361 [1 << 17]byte var z13362 [1 << 17]byte var z13363 [1 << 17]byte var z13364 [1 << 17]byte var z13365 [1 << 17]byte var z13366 [1 << 17]byte var z13367 [1 << 17]byte var z13368 [1 << 17]byte var z13369 [1 << 17]byte var z13370 [1 << 17]byte var z13371 [1 << 17]byte var z13372 [1 << 17]byte var z13373 [1 << 17]byte var z13374 [1 << 17]byte var z13375 [1 << 17]byte var z13376 [1 << 17]byte var z13377 [1 << 17]byte var z13378 [1 << 17]byte var z13379 [1 << 17]byte var z13380 [1 << 17]byte var z13381 [1 << 17]byte var z13382 [1 << 17]byte var z13383 [1 << 17]byte var z13384 [1 << 17]byte var z13385 [1 << 17]byte var z13386 [1 << 17]byte var z13387 [1 << 17]byte var z13388 [1 << 17]byte var z13389 [1 << 17]byte var z13390 [1 << 17]byte var z13391 [1 << 17]byte var z13392 [1 << 17]byte var z13393 [1 << 17]byte var z13394 [1 << 17]byte var z13395 [1 << 17]byte var z13396 [1 << 17]byte var z13397 [1 << 17]byte var z13398 [1 << 17]byte var z13399 [1 << 17]byte var z13400 [1 << 17]byte var z13401 [1 << 17]byte var z13402 [1 << 17]byte var z13403 [1 << 17]byte var z13404 [1 << 17]byte var z13405 [1 << 17]byte var z13406 [1 << 17]byte var z13407 [1 << 17]byte var z13408 [1 << 17]byte var z13409 [1 << 17]byte var z13410 [1 << 17]byte var z13411 [1 << 17]byte var z13412 [1 << 17]byte var z13413 [1 << 17]byte var z13414 [1 << 17]byte var z13415 [1 << 17]byte var z13416 [1 << 17]byte var z13417 [1 << 17]byte var z13418 [1 << 17]byte var z13419 [1 << 17]byte var z13420 [1 << 17]byte var z13421 [1 << 17]byte var z13422 [1 << 17]byte var z13423 [1 << 17]byte var z13424 [1 << 17]byte var z13425 [1 << 17]byte var z13426 [1 << 17]byte var z13427 [1 << 17]byte var z13428 [1 << 17]byte var z13429 [1 << 17]byte var z13430 [1 << 17]byte var z13431 [1 << 17]byte var z13432 [1 << 17]byte var z13433 [1 << 17]byte var z13434 [1 << 17]byte var z13435 [1 << 17]byte var z13436 [1 << 17]byte var z13437 [1 << 17]byte var z13438 [1 << 17]byte var z13439 [1 << 17]byte var z13440 [1 << 17]byte var z13441 [1 << 17]byte var z13442 [1 << 17]byte var z13443 [1 << 17]byte var z13444 [1 << 17]byte var z13445 [1 << 17]byte var z13446 [1 << 17]byte var z13447 [1 << 17]byte var z13448 [1 << 17]byte var z13449 [1 << 17]byte var z13450 [1 << 17]byte var z13451 [1 << 17]byte var z13452 [1 << 17]byte var z13453 [1 << 17]byte var z13454 [1 << 17]byte var z13455 [1 << 17]byte var z13456 [1 << 17]byte var z13457 [1 << 17]byte var z13458 [1 << 17]byte var z13459 [1 << 17]byte var z13460 [1 << 17]byte var z13461 [1 << 17]byte var z13462 [1 << 17]byte var z13463 [1 << 17]byte var z13464 [1 << 17]byte var z13465 [1 << 17]byte var z13466 [1 << 17]byte var z13467 [1 << 17]byte var z13468 [1 << 17]byte var z13469 [1 << 17]byte var z13470 [1 << 17]byte var z13471 [1 << 17]byte var z13472 [1 << 17]byte var z13473 [1 << 17]byte var z13474 [1 << 17]byte var z13475 [1 << 17]byte var z13476 [1 << 17]byte var z13477 [1 << 17]byte var z13478 [1 << 17]byte var z13479 [1 << 17]byte var z13480 [1 << 17]byte var z13481 [1 << 17]byte var z13482 [1 << 17]byte var z13483 [1 << 17]byte var z13484 [1 << 17]byte var z13485 [1 << 17]byte var z13486 [1 << 17]byte var z13487 [1 << 17]byte var z13488 [1 << 17]byte var z13489 [1 << 17]byte var z13490 [1 << 17]byte var z13491 [1 << 17]byte var z13492 [1 << 17]byte var z13493 [1 << 17]byte var z13494 [1 << 17]byte var z13495 [1 << 17]byte var z13496 [1 << 17]byte var z13497 [1 << 17]byte var z13498 [1 << 17]byte var z13499 [1 << 17]byte var z13500 [1 << 17]byte var z13501 [1 << 17]byte var z13502 [1 << 17]byte var z13503 [1 << 17]byte var z13504 [1 << 17]byte var z13505 [1 << 17]byte var z13506 [1 << 17]byte var z13507 [1 << 17]byte var z13508 [1 << 17]byte var z13509 [1 << 17]byte var z13510 [1 << 17]byte var z13511 [1 << 17]byte var z13512 [1 << 17]byte var z13513 [1 << 17]byte var z13514 [1 << 17]byte var z13515 [1 << 17]byte var z13516 [1 << 17]byte var z13517 [1 << 17]byte var z13518 [1 << 17]byte var z13519 [1 << 17]byte var z13520 [1 << 17]byte var z13521 [1 << 17]byte var z13522 [1 << 17]byte var z13523 [1 << 17]byte var z13524 [1 << 17]byte var z13525 [1 << 17]byte var z13526 [1 << 17]byte var z13527 [1 << 17]byte var z13528 [1 << 17]byte var z13529 [1 << 17]byte var z13530 [1 << 17]byte var z13531 [1 << 17]byte var z13532 [1 << 17]byte var z13533 [1 << 17]byte var z13534 [1 << 17]byte var z13535 [1 << 17]byte var z13536 [1 << 17]byte var z13537 [1 << 17]byte var z13538 [1 << 17]byte var z13539 [1 << 17]byte var z13540 [1 << 17]byte var z13541 [1 << 17]byte var z13542 [1 << 17]byte var z13543 [1 << 17]byte var z13544 [1 << 17]byte var z13545 [1 << 17]byte var z13546 [1 << 17]byte var z13547 [1 << 17]byte var z13548 [1 << 17]byte var z13549 [1 << 17]byte var z13550 [1 << 17]byte var z13551 [1 << 17]byte var z13552 [1 << 17]byte var z13553 [1 << 17]byte var z13554 [1 << 17]byte var z13555 [1 << 17]byte var z13556 [1 << 17]byte var z13557 [1 << 17]byte var z13558 [1 << 17]byte var z13559 [1 << 17]byte var z13560 [1 << 17]byte var z13561 [1 << 17]byte var z13562 [1 << 17]byte var z13563 [1 << 17]byte var z13564 [1 << 17]byte var z13565 [1 << 17]byte var z13566 [1 << 17]byte var z13567 [1 << 17]byte var z13568 [1 << 17]byte var z13569 [1 << 17]byte var z13570 [1 << 17]byte var z13571 [1 << 17]byte var z13572 [1 << 17]byte var z13573 [1 << 17]byte var z13574 [1 << 17]byte var z13575 [1 << 17]byte var z13576 [1 << 17]byte var z13577 [1 << 17]byte var z13578 [1 << 17]byte var z13579 [1 << 17]byte var z13580 [1 << 17]byte var z13581 [1 << 17]byte var z13582 [1 << 17]byte var z13583 [1 << 17]byte var z13584 [1 << 17]byte var z13585 [1 << 17]byte var z13586 [1 << 17]byte var z13587 [1 << 17]byte var z13588 [1 << 17]byte var z13589 [1 << 17]byte var z13590 [1 << 17]byte var z13591 [1 << 17]byte var z13592 [1 << 17]byte var z13593 [1 << 17]byte var z13594 [1 << 17]byte var z13595 [1 << 17]byte var z13596 [1 << 17]byte var z13597 [1 << 17]byte var z13598 [1 << 17]byte var z13599 [1 << 17]byte var z13600 [1 << 17]byte var z13601 [1 << 17]byte var z13602 [1 << 17]byte var z13603 [1 << 17]byte var z13604 [1 << 17]byte var z13605 [1 << 17]byte var z13606 [1 << 17]byte var z13607 [1 << 17]byte var z13608 [1 << 17]byte var z13609 [1 << 17]byte var z13610 [1 << 17]byte var z13611 [1 << 17]byte var z13612 [1 << 17]byte var z13613 [1 << 17]byte var z13614 [1 << 17]byte var z13615 [1 << 17]byte var z13616 [1 << 17]byte var z13617 [1 << 17]byte var z13618 [1 << 17]byte var z13619 [1 << 17]byte var z13620 [1 << 17]byte var z13621 [1 << 17]byte var z13622 [1 << 17]byte var z13623 [1 << 17]byte var z13624 [1 << 17]byte var z13625 [1 << 17]byte var z13626 [1 << 17]byte var z13627 [1 << 17]byte var z13628 [1 << 17]byte var z13629 [1 << 17]byte var z13630 [1 << 17]byte var z13631 [1 << 17]byte var z13632 [1 << 17]byte var z13633 [1 << 17]byte var z13634 [1 << 17]byte var z13635 [1 << 17]byte var z13636 [1 << 17]byte var z13637 [1 << 17]byte var z13638 [1 << 17]byte var z13639 [1 << 17]byte var z13640 [1 << 17]byte var z13641 [1 << 17]byte var z13642 [1 << 17]byte var z13643 [1 << 17]byte var z13644 [1 << 17]byte var z13645 [1 << 17]byte var z13646 [1 << 17]byte var z13647 [1 << 17]byte var z13648 [1 << 17]byte var z13649 [1 << 17]byte var z13650 [1 << 17]byte var z13651 [1 << 17]byte var z13652 [1 << 17]byte var z13653 [1 << 17]byte var z13654 [1 << 17]byte var z13655 [1 << 17]byte var z13656 [1 << 17]byte var z13657 [1 << 17]byte var z13658 [1 << 17]byte var z13659 [1 << 17]byte var z13660 [1 << 17]byte var z13661 [1 << 17]byte var z13662 [1 << 17]byte var z13663 [1 << 17]byte var z13664 [1 << 17]byte var z13665 [1 << 17]byte var z13666 [1 << 17]byte var z13667 [1 << 17]byte var z13668 [1 << 17]byte var z13669 [1 << 17]byte var z13670 [1 << 17]byte var z13671 [1 << 17]byte var z13672 [1 << 17]byte var z13673 [1 << 17]byte var z13674 [1 << 17]byte var z13675 [1 << 17]byte var z13676 [1 << 17]byte var z13677 [1 << 17]byte var z13678 [1 << 17]byte var z13679 [1 << 17]byte var z13680 [1 << 17]byte var z13681 [1 << 17]byte var z13682 [1 << 17]byte var z13683 [1 << 17]byte var z13684 [1 << 17]byte var z13685 [1 << 17]byte var z13686 [1 << 17]byte var z13687 [1 << 17]byte var z13688 [1 << 17]byte var z13689 [1 << 17]byte var z13690 [1 << 17]byte var z13691 [1 << 17]byte var z13692 [1 << 17]byte var z13693 [1 << 17]byte var z13694 [1 << 17]byte var z13695 [1 << 17]byte var z13696 [1 << 17]byte var z13697 [1 << 17]byte var z13698 [1 << 17]byte var z13699 [1 << 17]byte var z13700 [1 << 17]byte var z13701 [1 << 17]byte var z13702 [1 << 17]byte var z13703 [1 << 17]byte var z13704 [1 << 17]byte var z13705 [1 << 17]byte var z13706 [1 << 17]byte var z13707 [1 << 17]byte var z13708 [1 << 17]byte var z13709 [1 << 17]byte var z13710 [1 << 17]byte var z13711 [1 << 17]byte var z13712 [1 << 17]byte var z13713 [1 << 17]byte var z13714 [1 << 17]byte var z13715 [1 << 17]byte var z13716 [1 << 17]byte var z13717 [1 << 17]byte var z13718 [1 << 17]byte var z13719 [1 << 17]byte var z13720 [1 << 17]byte var z13721 [1 << 17]byte var z13722 [1 << 17]byte var z13723 [1 << 17]byte var z13724 [1 << 17]byte var z13725 [1 << 17]byte var z13726 [1 << 17]byte var z13727 [1 << 17]byte var z13728 [1 << 17]byte var z13729 [1 << 17]byte var z13730 [1 << 17]byte var z13731 [1 << 17]byte var z13732 [1 << 17]byte var z13733 [1 << 17]byte var z13734 [1 << 17]byte var z13735 [1 << 17]byte var z13736 [1 << 17]byte var z13737 [1 << 17]byte var z13738 [1 << 17]byte var z13739 [1 << 17]byte var z13740 [1 << 17]byte var z13741 [1 << 17]byte var z13742 [1 << 17]byte var z13743 [1 << 17]byte var z13744 [1 << 17]byte var z13745 [1 << 17]byte var z13746 [1 << 17]byte var z13747 [1 << 17]byte var z13748 [1 << 17]byte var z13749 [1 << 17]byte var z13750 [1 << 17]byte var z13751 [1 << 17]byte var z13752 [1 << 17]byte var z13753 [1 << 17]byte var z13754 [1 << 17]byte var z13755 [1 << 17]byte var z13756 [1 << 17]byte var z13757 [1 << 17]byte var z13758 [1 << 17]byte var z13759 [1 << 17]byte var z13760 [1 << 17]byte var z13761 [1 << 17]byte var z13762 [1 << 17]byte var z13763 [1 << 17]byte var z13764 [1 << 17]byte var z13765 [1 << 17]byte var z13766 [1 << 17]byte var z13767 [1 << 17]byte var z13768 [1 << 17]byte var z13769 [1 << 17]byte var z13770 [1 << 17]byte var z13771 [1 << 17]byte var z13772 [1 << 17]byte var z13773 [1 << 17]byte var z13774 [1 << 17]byte var z13775 [1 << 17]byte var z13776 [1 << 17]byte var z13777 [1 << 17]byte var z13778 [1 << 17]byte var z13779 [1 << 17]byte var z13780 [1 << 17]byte var z13781 [1 << 17]byte var z13782 [1 << 17]byte var z13783 [1 << 17]byte var z13784 [1 << 17]byte var z13785 [1 << 17]byte var z13786 [1 << 17]byte var z13787 [1 << 17]byte var z13788 [1 << 17]byte var z13789 [1 << 17]byte var z13790 [1 << 17]byte var z13791 [1 << 17]byte var z13792 [1 << 17]byte var z13793 [1 << 17]byte var z13794 [1 << 17]byte var z13795 [1 << 17]byte var z13796 [1 << 17]byte var z13797 [1 << 17]byte var z13798 [1 << 17]byte var z13799 [1 << 17]byte var z13800 [1 << 17]byte var z13801 [1 << 17]byte var z13802 [1 << 17]byte var z13803 [1 << 17]byte var z13804 [1 << 17]byte var z13805 [1 << 17]byte var z13806 [1 << 17]byte var z13807 [1 << 17]byte var z13808 [1 << 17]byte var z13809 [1 << 17]byte var z13810 [1 << 17]byte var z13811 [1 << 17]byte var z13812 [1 << 17]byte var z13813 [1 << 17]byte var z13814 [1 << 17]byte var z13815 [1 << 17]byte var z13816 [1 << 17]byte var z13817 [1 << 17]byte var z13818 [1 << 17]byte var z13819 [1 << 17]byte var z13820 [1 << 17]byte var z13821 [1 << 17]byte var z13822 [1 << 17]byte var z13823 [1 << 17]byte var z13824 [1 << 17]byte var z13825 [1 << 17]byte var z13826 [1 << 17]byte var z13827 [1 << 17]byte var z13828 [1 << 17]byte var z13829 [1 << 17]byte var z13830 [1 << 17]byte var z13831 [1 << 17]byte var z13832 [1 << 17]byte var z13833 [1 << 17]byte var z13834 [1 << 17]byte var z13835 [1 << 17]byte var z13836 [1 << 17]byte var z13837 [1 << 17]byte var z13838 [1 << 17]byte var z13839 [1 << 17]byte var z13840 [1 << 17]byte var z13841 [1 << 17]byte var z13842 [1 << 17]byte var z13843 [1 << 17]byte var z13844 [1 << 17]byte var z13845 [1 << 17]byte var z13846 [1 << 17]byte var z13847 [1 << 17]byte var z13848 [1 << 17]byte var z13849 [1 << 17]byte var z13850 [1 << 17]byte var z13851 [1 << 17]byte var z13852 [1 << 17]byte var z13853 [1 << 17]byte var z13854 [1 << 17]byte var z13855 [1 << 17]byte var z13856 [1 << 17]byte var z13857 [1 << 17]byte var z13858 [1 << 17]byte var z13859 [1 << 17]byte var z13860 [1 << 17]byte var z13861 [1 << 17]byte var z13862 [1 << 17]byte var z13863 [1 << 17]byte var z13864 [1 << 17]byte var z13865 [1 << 17]byte var z13866 [1 << 17]byte var z13867 [1 << 17]byte var z13868 [1 << 17]byte var z13869 [1 << 17]byte var z13870 [1 << 17]byte var z13871 [1 << 17]byte var z13872 [1 << 17]byte var z13873 [1 << 17]byte var z13874 [1 << 17]byte var z13875 [1 << 17]byte var z13876 [1 << 17]byte var z13877 [1 << 17]byte var z13878 [1 << 17]byte var z13879 [1 << 17]byte var z13880 [1 << 17]byte var z13881 [1 << 17]byte var z13882 [1 << 17]byte var z13883 [1 << 17]byte var z13884 [1 << 17]byte var z13885 [1 << 17]byte var z13886 [1 << 17]byte var z13887 [1 << 17]byte var z13888 [1 << 17]byte var z13889 [1 << 17]byte var z13890 [1 << 17]byte var z13891 [1 << 17]byte var z13892 [1 << 17]byte var z13893 [1 << 17]byte var z13894 [1 << 17]byte var z13895 [1 << 17]byte var z13896 [1 << 17]byte var z13897 [1 << 17]byte var z13898 [1 << 17]byte var z13899 [1 << 17]byte var z13900 [1 << 17]byte var z13901 [1 << 17]byte var z13902 [1 << 17]byte var z13903 [1 << 17]byte var z13904 [1 << 17]byte var z13905 [1 << 17]byte var z13906 [1 << 17]byte var z13907 [1 << 17]byte var z13908 [1 << 17]byte var z13909 [1 << 17]byte var z13910 [1 << 17]byte var z13911 [1 << 17]byte var z13912 [1 << 17]byte var z13913 [1 << 17]byte var z13914 [1 << 17]byte var z13915 [1 << 17]byte var z13916 [1 << 17]byte var z13917 [1 << 17]byte var z13918 [1 << 17]byte var z13919 [1 << 17]byte var z13920 [1 << 17]byte var z13921 [1 << 17]byte var z13922 [1 << 17]byte var z13923 [1 << 17]byte var z13924 [1 << 17]byte var z13925 [1 << 17]byte var z13926 [1 << 17]byte var z13927 [1 << 17]byte var z13928 [1 << 17]byte var z13929 [1 << 17]byte var z13930 [1 << 17]byte var z13931 [1 << 17]byte var z13932 [1 << 17]byte var z13933 [1 << 17]byte var z13934 [1 << 17]byte var z13935 [1 << 17]byte var z13936 [1 << 17]byte var z13937 [1 << 17]byte var z13938 [1 << 17]byte var z13939 [1 << 17]byte var z13940 [1 << 17]byte var z13941 [1 << 17]byte var z13942 [1 << 17]byte var z13943 [1 << 17]byte var z13944 [1 << 17]byte var z13945 [1 << 17]byte var z13946 [1 << 17]byte var z13947 [1 << 17]byte var z13948 [1 << 17]byte var z13949 [1 << 17]byte var z13950 [1 << 17]byte var z13951 [1 << 17]byte var z13952 [1 << 17]byte var z13953 [1 << 17]byte var z13954 [1 << 17]byte var z13955 [1 << 17]byte var z13956 [1 << 17]byte var z13957 [1 << 17]byte var z13958 [1 << 17]byte var z13959 [1 << 17]byte var z13960 [1 << 17]byte var z13961 [1 << 17]byte var z13962 [1 << 17]byte var z13963 [1 << 17]byte var z13964 [1 << 17]byte var z13965 [1 << 17]byte var z13966 [1 << 17]byte var z13967 [1 << 17]byte var z13968 [1 << 17]byte var z13969 [1 << 17]byte var z13970 [1 << 17]byte var z13971 [1 << 17]byte var z13972 [1 << 17]byte var z13973 [1 << 17]byte var z13974 [1 << 17]byte var z13975 [1 << 17]byte var z13976 [1 << 17]byte var z13977 [1 << 17]byte var z13978 [1 << 17]byte var z13979 [1 << 17]byte var z13980 [1 << 17]byte var z13981 [1 << 17]byte var z13982 [1 << 17]byte var z13983 [1 << 17]byte var z13984 [1 << 17]byte var z13985 [1 << 17]byte var z13986 [1 << 17]byte var z13987 [1 << 17]byte var z13988 [1 << 17]byte var z13989 [1 << 17]byte var z13990 [1 << 17]byte var z13991 [1 << 17]byte var z13992 [1 << 17]byte var z13993 [1 << 17]byte var z13994 [1 << 17]byte var z13995 [1 << 17]byte var z13996 [1 << 17]byte var z13997 [1 << 17]byte var z13998 [1 << 17]byte var z13999 [1 << 17]byte var z14000 [1 << 17]byte var z14001 [1 << 17]byte var z14002 [1 << 17]byte var z14003 [1 << 17]byte var z14004 [1 << 17]byte var z14005 [1 << 17]byte var z14006 [1 << 17]byte var z14007 [1 << 17]byte var z14008 [1 << 17]byte var z14009 [1 << 17]byte var z14010 [1 << 17]byte var z14011 [1 << 17]byte var z14012 [1 << 17]byte var z14013 [1 << 17]byte var z14014 [1 << 17]byte var z14015 [1 << 17]byte var z14016 [1 << 17]byte var z14017 [1 << 17]byte var z14018 [1 << 17]byte var z14019 [1 << 17]byte var z14020 [1 << 17]byte var z14021 [1 << 17]byte var z14022 [1 << 17]byte var z14023 [1 << 17]byte var z14024 [1 << 17]byte var z14025 [1 << 17]byte var z14026 [1 << 17]byte var z14027 [1 << 17]byte var z14028 [1 << 17]byte var z14029 [1 << 17]byte var z14030 [1 << 17]byte var z14031 [1 << 17]byte var z14032 [1 << 17]byte var z14033 [1 << 17]byte var z14034 [1 << 17]byte var z14035 [1 << 17]byte var z14036 [1 << 17]byte var z14037 [1 << 17]byte var z14038 [1 << 17]byte var z14039 [1 << 17]byte var z14040 [1 << 17]byte var z14041 [1 << 17]byte var z14042 [1 << 17]byte var z14043 [1 << 17]byte var z14044 [1 << 17]byte var z14045 [1 << 17]byte var z14046 [1 << 17]byte var z14047 [1 << 17]byte var z14048 [1 << 17]byte var z14049 [1 << 17]byte var z14050 [1 << 17]byte var z14051 [1 << 17]byte var z14052 [1 << 17]byte var z14053 [1 << 17]byte var z14054 [1 << 17]byte var z14055 [1 << 17]byte var z14056 [1 << 17]byte var z14057 [1 << 17]byte var z14058 [1 << 17]byte var z14059 [1 << 17]byte var z14060 [1 << 17]byte var z14061 [1 << 17]byte var z14062 [1 << 17]byte var z14063 [1 << 17]byte var z14064 [1 << 17]byte var z14065 [1 << 17]byte var z14066 [1 << 17]byte var z14067 [1 << 17]byte var z14068 [1 << 17]byte var z14069 [1 << 17]byte var z14070 [1 << 17]byte var z14071 [1 << 17]byte var z14072 [1 << 17]byte var z14073 [1 << 17]byte var z14074 [1 << 17]byte var z14075 [1 << 17]byte var z14076 [1 << 17]byte var z14077 [1 << 17]byte var z14078 [1 << 17]byte var z14079 [1 << 17]byte var z14080 [1 << 17]byte var z14081 [1 << 17]byte var z14082 [1 << 17]byte var z14083 [1 << 17]byte var z14084 [1 << 17]byte var z14085 [1 << 17]byte var z14086 [1 << 17]byte var z14087 [1 << 17]byte var z14088 [1 << 17]byte var z14089 [1 << 17]byte var z14090 [1 << 17]byte var z14091 [1 << 17]byte var z14092 [1 << 17]byte var z14093 [1 << 17]byte var z14094 [1 << 17]byte var z14095 [1 << 17]byte var z14096 [1 << 17]byte var z14097 [1 << 17]byte var z14098 [1 << 17]byte var z14099 [1 << 17]byte var z14100 [1 << 17]byte var z14101 [1 << 17]byte var z14102 [1 << 17]byte var z14103 [1 << 17]byte var z14104 [1 << 17]byte var z14105 [1 << 17]byte var z14106 [1 << 17]byte var z14107 [1 << 17]byte var z14108 [1 << 17]byte var z14109 [1 << 17]byte var z14110 [1 << 17]byte var z14111 [1 << 17]byte var z14112 [1 << 17]byte var z14113 [1 << 17]byte var z14114 [1 << 17]byte var z14115 [1 << 17]byte var z14116 [1 << 17]byte var z14117 [1 << 17]byte var z14118 [1 << 17]byte var z14119 [1 << 17]byte var z14120 [1 << 17]byte var z14121 [1 << 17]byte var z14122 [1 << 17]byte var z14123 [1 << 17]byte var z14124 [1 << 17]byte var z14125 [1 << 17]byte var z14126 [1 << 17]byte var z14127 [1 << 17]byte var z14128 [1 << 17]byte var z14129 [1 << 17]byte var z14130 [1 << 17]byte var z14131 [1 << 17]byte var z14132 [1 << 17]byte var z14133 [1 << 17]byte var z14134 [1 << 17]byte var z14135 [1 << 17]byte var z14136 [1 << 17]byte var z14137 [1 << 17]byte var z14138 [1 << 17]byte var z14139 [1 << 17]byte var z14140 [1 << 17]byte var z14141 [1 << 17]byte var z14142 [1 << 17]byte var z14143 [1 << 17]byte var z14144 [1 << 17]byte var z14145 [1 << 17]byte var z14146 [1 << 17]byte var z14147 [1 << 17]byte var z14148 [1 << 17]byte var z14149 [1 << 17]byte var z14150 [1 << 17]byte var z14151 [1 << 17]byte var z14152 [1 << 17]byte var z14153 [1 << 17]byte var z14154 [1 << 17]byte var z14155 [1 << 17]byte var z14156 [1 << 17]byte var z14157 [1 << 17]byte var z14158 [1 << 17]byte var z14159 [1 << 17]byte var z14160 [1 << 17]byte var z14161 [1 << 17]byte var z14162 [1 << 17]byte var z14163 [1 << 17]byte var z14164 [1 << 17]byte var z14165 [1 << 17]byte var z14166 [1 << 17]byte var z14167 [1 << 17]byte var z14168 [1 << 17]byte var z14169 [1 << 17]byte var z14170 [1 << 17]byte var z14171 [1 << 17]byte var z14172 [1 << 17]byte var z14173 [1 << 17]byte var z14174 [1 << 17]byte var z14175 [1 << 17]byte var z14176 [1 << 17]byte var z14177 [1 << 17]byte var z14178 [1 << 17]byte var z14179 [1 << 17]byte var z14180 [1 << 17]byte var z14181 [1 << 17]byte var z14182 [1 << 17]byte var z14183 [1 << 17]byte var z14184 [1 << 17]byte var z14185 [1 << 17]byte var z14186 [1 << 17]byte var z14187 [1 << 17]byte var z14188 [1 << 17]byte var z14189 [1 << 17]byte var z14190 [1 << 17]byte var z14191 [1 << 17]byte var z14192 [1 << 17]byte var z14193 [1 << 17]byte var z14194 [1 << 17]byte var z14195 [1 << 17]byte var z14196 [1 << 17]byte var z14197 [1 << 17]byte var z14198 [1 << 17]byte var z14199 [1 << 17]byte var z14200 [1 << 17]byte var z14201 [1 << 17]byte var z14202 [1 << 17]byte var z14203 [1 << 17]byte var z14204 [1 << 17]byte var z14205 [1 << 17]byte var z14206 [1 << 17]byte var z14207 [1 << 17]byte var z14208 [1 << 17]byte var z14209 [1 << 17]byte var z14210 [1 << 17]byte var z14211 [1 << 17]byte var z14212 [1 << 17]byte var z14213 [1 << 17]byte var z14214 [1 << 17]byte var z14215 [1 << 17]byte var z14216 [1 << 17]byte var z14217 [1 << 17]byte var z14218 [1 << 17]byte var z14219 [1 << 17]byte var z14220 [1 << 17]byte var z14221 [1 << 17]byte var z14222 [1 << 17]byte var z14223 [1 << 17]byte var z14224 [1 << 17]byte var z14225 [1 << 17]byte var z14226 [1 << 17]byte var z14227 [1 << 17]byte var z14228 [1 << 17]byte var z14229 [1 << 17]byte var z14230 [1 << 17]byte var z14231 [1 << 17]byte var z14232 [1 << 17]byte var z14233 [1 << 17]byte var z14234 [1 << 17]byte var z14235 [1 << 17]byte var z14236 [1 << 17]byte var z14237 [1 << 17]byte var z14238 [1 << 17]byte var z14239 [1 << 17]byte var z14240 [1 << 17]byte var z14241 [1 << 17]byte var z14242 [1 << 17]byte var z14243 [1 << 17]byte var z14244 [1 << 17]byte var z14245 [1 << 17]byte var z14246 [1 << 17]byte var z14247 [1 << 17]byte var z14248 [1 << 17]byte var z14249 [1 << 17]byte var z14250 [1 << 17]byte var z14251 [1 << 17]byte var z14252 [1 << 17]byte var z14253 [1 << 17]byte var z14254 [1 << 17]byte var z14255 [1 << 17]byte var z14256 [1 << 17]byte var z14257 [1 << 17]byte var z14258 [1 << 17]byte var z14259 [1 << 17]byte var z14260 [1 << 17]byte var z14261 [1 << 17]byte var z14262 [1 << 17]byte var z14263 [1 << 17]byte var z14264 [1 << 17]byte var z14265 [1 << 17]byte var z14266 [1 << 17]byte var z14267 [1 << 17]byte var z14268 [1 << 17]byte var z14269 [1 << 17]byte var z14270 [1 << 17]byte var z14271 [1 << 17]byte var z14272 [1 << 17]byte var z14273 [1 << 17]byte var z14274 [1 << 17]byte var z14275 [1 << 17]byte var z14276 [1 << 17]byte var z14277 [1 << 17]byte var z14278 [1 << 17]byte var z14279 [1 << 17]byte var z14280 [1 << 17]byte var z14281 [1 << 17]byte var z14282 [1 << 17]byte var z14283 [1 << 17]byte var z14284 [1 << 17]byte var z14285 [1 << 17]byte var z14286 [1 << 17]byte var z14287 [1 << 17]byte var z14288 [1 << 17]byte var z14289 [1 << 17]byte var z14290 [1 << 17]byte var z14291 [1 << 17]byte var z14292 [1 << 17]byte var z14293 [1 << 17]byte var z14294 [1 << 17]byte var z14295 [1 << 17]byte var z14296 [1 << 17]byte var z14297 [1 << 17]byte var z14298 [1 << 17]byte var z14299 [1 << 17]byte var z14300 [1 << 17]byte var z14301 [1 << 17]byte var z14302 [1 << 17]byte var z14303 [1 << 17]byte var z14304 [1 << 17]byte var z14305 [1 << 17]byte var z14306 [1 << 17]byte var z14307 [1 << 17]byte var z14308 [1 << 17]byte var z14309 [1 << 17]byte var z14310 [1 << 17]byte var z14311 [1 << 17]byte var z14312 [1 << 17]byte var z14313 [1 << 17]byte var z14314 [1 << 17]byte var z14315 [1 << 17]byte var z14316 [1 << 17]byte var z14317 [1 << 17]byte var z14318 [1 << 17]byte var z14319 [1 << 17]byte var z14320 [1 << 17]byte var z14321 [1 << 17]byte var z14322 [1 << 17]byte var z14323 [1 << 17]byte var z14324 [1 << 17]byte var z14325 [1 << 17]byte var z14326 [1 << 17]byte var z14327 [1 << 17]byte var z14328 [1 << 17]byte var z14329 [1 << 17]byte var z14330 [1 << 17]byte var z14331 [1 << 17]byte var z14332 [1 << 17]byte var z14333 [1 << 17]byte var z14334 [1 << 17]byte var z14335 [1 << 17]byte var z14336 [1 << 17]byte var z14337 [1 << 17]byte var z14338 [1 << 17]byte var z14339 [1 << 17]byte var z14340 [1 << 17]byte var z14341 [1 << 17]byte var z14342 [1 << 17]byte var z14343 [1 << 17]byte var z14344 [1 << 17]byte var z14345 [1 << 17]byte var z14346 [1 << 17]byte var z14347 [1 << 17]byte var z14348 [1 << 17]byte var z14349 [1 << 17]byte var z14350 [1 << 17]byte var z14351 [1 << 17]byte var z14352 [1 << 17]byte var z14353 [1 << 17]byte var z14354 [1 << 17]byte var z14355 [1 << 17]byte var z14356 [1 << 17]byte var z14357 [1 << 17]byte var z14358 [1 << 17]byte var z14359 [1 << 17]byte var z14360 [1 << 17]byte var z14361 [1 << 17]byte var z14362 [1 << 17]byte var z14363 [1 << 17]byte var z14364 [1 << 17]byte var z14365 [1 << 17]byte var z14366 [1 << 17]byte var z14367 [1 << 17]byte var z14368 [1 << 17]byte var z14369 [1 << 17]byte var z14370 [1 << 17]byte var z14371 [1 << 17]byte var z14372 [1 << 17]byte var z14373 [1 << 17]byte var z14374 [1 << 17]byte var z14375 [1 << 17]byte var z14376 [1 << 17]byte var z14377 [1 << 17]byte var z14378 [1 << 17]byte var z14379 [1 << 17]byte var z14380 [1 << 17]byte var z14381 [1 << 17]byte var z14382 [1 << 17]byte var z14383 [1 << 17]byte var z14384 [1 << 17]byte var z14385 [1 << 17]byte var z14386 [1 << 17]byte var z14387 [1 << 17]byte var z14388 [1 << 17]byte var z14389 [1 << 17]byte var z14390 [1 << 17]byte var z14391 [1 << 17]byte var z14392 [1 << 17]byte var z14393 [1 << 17]byte var z14394 [1 << 17]byte var z14395 [1 << 17]byte var z14396 [1 << 17]byte var z14397 [1 << 17]byte var z14398 [1 << 17]byte var z14399 [1 << 17]byte var z14400 [1 << 17]byte var z14401 [1 << 17]byte var z14402 [1 << 17]byte var z14403 [1 << 17]byte var z14404 [1 << 17]byte var z14405 [1 << 17]byte var z14406 [1 << 17]byte var z14407 [1 << 17]byte var z14408 [1 << 17]byte var z14409 [1 << 17]byte var z14410 [1 << 17]byte var z14411 [1 << 17]byte var z14412 [1 << 17]byte var z14413 [1 << 17]byte var z14414 [1 << 17]byte var z14415 [1 << 17]byte var z14416 [1 << 17]byte var z14417 [1 << 17]byte var z14418 [1 << 17]byte var z14419 [1 << 17]byte var z14420 [1 << 17]byte var z14421 [1 << 17]byte var z14422 [1 << 17]byte var z14423 [1 << 17]byte var z14424 [1 << 17]byte var z14425 [1 << 17]byte var z14426 [1 << 17]byte var z14427 [1 << 17]byte var z14428 [1 << 17]byte var z14429 [1 << 17]byte var z14430 [1 << 17]byte var z14431 [1 << 17]byte var z14432 [1 << 17]byte var z14433 [1 << 17]byte var z14434 [1 << 17]byte var z14435 [1 << 17]byte var z14436 [1 << 17]byte var z14437 [1 << 17]byte var z14438 [1 << 17]byte var z14439 [1 << 17]byte var z14440 [1 << 17]byte var z14441 [1 << 17]byte var z14442 [1 << 17]byte var z14443 [1 << 17]byte var z14444 [1 << 17]byte var z14445 [1 << 17]byte var z14446 [1 << 17]byte var z14447 [1 << 17]byte var z14448 [1 << 17]byte var z14449 [1 << 17]byte var z14450 [1 << 17]byte var z14451 [1 << 17]byte var z14452 [1 << 17]byte var z14453 [1 << 17]byte var z14454 [1 << 17]byte var z14455 [1 << 17]byte var z14456 [1 << 17]byte var z14457 [1 << 17]byte var z14458 [1 << 17]byte var z14459 [1 << 17]byte var z14460 [1 << 17]byte var z14461 [1 << 17]byte var z14462 [1 << 17]byte var z14463 [1 << 17]byte var z14464 [1 << 17]byte var z14465 [1 << 17]byte var z14466 [1 << 17]byte var z14467 [1 << 17]byte var z14468 [1 << 17]byte var z14469 [1 << 17]byte var z14470 [1 << 17]byte var z14471 [1 << 17]byte var z14472 [1 << 17]byte var z14473 [1 << 17]byte var z14474 [1 << 17]byte var z14475 [1 << 17]byte var z14476 [1 << 17]byte var z14477 [1 << 17]byte var z14478 [1 << 17]byte var z14479 [1 << 17]byte var z14480 [1 << 17]byte var z14481 [1 << 17]byte var z14482 [1 << 17]byte var z14483 [1 << 17]byte var z14484 [1 << 17]byte var z14485 [1 << 17]byte var z14486 [1 << 17]byte var z14487 [1 << 17]byte var z14488 [1 << 17]byte var z14489 [1 << 17]byte var z14490 [1 << 17]byte var z14491 [1 << 17]byte var z14492 [1 << 17]byte var z14493 [1 << 17]byte var z14494 [1 << 17]byte var z14495 [1 << 17]byte var z14496 [1 << 17]byte var z14497 [1 << 17]byte var z14498 [1 << 17]byte var z14499 [1 << 17]byte var z14500 [1 << 17]byte var z14501 [1 << 17]byte var z14502 [1 << 17]byte var z14503 [1 << 17]byte var z14504 [1 << 17]byte var z14505 [1 << 17]byte var z14506 [1 << 17]byte var z14507 [1 << 17]byte var z14508 [1 << 17]byte var z14509 [1 << 17]byte var z14510 [1 << 17]byte var z14511 [1 << 17]byte var z14512 [1 << 17]byte var z14513 [1 << 17]byte var z14514 [1 << 17]byte var z14515 [1 << 17]byte var z14516 [1 << 17]byte var z14517 [1 << 17]byte var z14518 [1 << 17]byte var z14519 [1 << 17]byte var z14520 [1 << 17]byte var z14521 [1 << 17]byte var z14522 [1 << 17]byte var z14523 [1 << 17]byte var z14524 [1 << 17]byte var z14525 [1 << 17]byte var z14526 [1 << 17]byte var z14527 [1 << 17]byte var z14528 [1 << 17]byte var z14529 [1 << 17]byte var z14530 [1 << 17]byte var z14531 [1 << 17]byte var z14532 [1 << 17]byte var z14533 [1 << 17]byte var z14534 [1 << 17]byte var z14535 [1 << 17]byte var z14536 [1 << 17]byte var z14537 [1 << 17]byte var z14538 [1 << 17]byte var z14539 [1 << 17]byte var z14540 [1 << 17]byte var z14541 [1 << 17]byte var z14542 [1 << 17]byte var z14543 [1 << 17]byte var z14544 [1 << 17]byte var z14545 [1 << 17]byte var z14546 [1 << 17]byte var z14547 [1 << 17]byte var z14548 [1 << 17]byte var z14549 [1 << 17]byte var z14550 [1 << 17]byte var z14551 [1 << 17]byte var z14552 [1 << 17]byte var z14553 [1 << 17]byte var z14554 [1 << 17]byte var z14555 [1 << 17]byte var z14556 [1 << 17]byte var z14557 [1 << 17]byte var z14558 [1 << 17]byte var z14559 [1 << 17]byte var z14560 [1 << 17]byte var z14561 [1 << 17]byte var z14562 [1 << 17]byte var z14563 [1 << 17]byte var z14564 [1 << 17]byte var z14565 [1 << 17]byte var z14566 [1 << 17]byte var z14567 [1 << 17]byte var z14568 [1 << 17]byte var z14569 [1 << 17]byte var z14570 [1 << 17]byte var z14571 [1 << 17]byte var z14572 [1 << 17]byte var z14573 [1 << 17]byte var z14574 [1 << 17]byte var z14575 [1 << 17]byte var z14576 [1 << 17]byte var z14577 [1 << 17]byte var z14578 [1 << 17]byte var z14579 [1 << 17]byte var z14580 [1 << 17]byte var z14581 [1 << 17]byte var z14582 [1 << 17]byte var z14583 [1 << 17]byte var z14584 [1 << 17]byte var z14585 [1 << 17]byte var z14586 [1 << 17]byte var z14587 [1 << 17]byte var z14588 [1 << 17]byte var z14589 [1 << 17]byte var z14590 [1 << 17]byte var z14591 [1 << 17]byte var z14592 [1 << 17]byte var z14593 [1 << 17]byte var z14594 [1 << 17]byte var z14595 [1 << 17]byte var z14596 [1 << 17]byte var z14597 [1 << 17]byte var z14598 [1 << 17]byte var z14599 [1 << 17]byte var z14600 [1 << 17]byte var z14601 [1 << 17]byte var z14602 [1 << 17]byte var z14603 [1 << 17]byte var z14604 [1 << 17]byte var z14605 [1 << 17]byte var z14606 [1 << 17]byte var z14607 [1 << 17]byte var z14608 [1 << 17]byte var z14609 [1 << 17]byte var z14610 [1 << 17]byte var z14611 [1 << 17]byte var z14612 [1 << 17]byte var z14613 [1 << 17]byte var z14614 [1 << 17]byte var z14615 [1 << 17]byte var z14616 [1 << 17]byte var z14617 [1 << 17]byte var z14618 [1 << 17]byte var z14619 [1 << 17]byte var z14620 [1 << 17]byte var z14621 [1 << 17]byte var z14622 [1 << 17]byte var z14623 [1 << 17]byte var z14624 [1 << 17]byte var z14625 [1 << 17]byte var z14626 [1 << 17]byte var z14627 [1 << 17]byte var z14628 [1 << 17]byte var z14629 [1 << 17]byte var z14630 [1 << 17]byte var z14631 [1 << 17]byte var z14632 [1 << 17]byte var z14633 [1 << 17]byte var z14634 [1 << 17]byte var z14635 [1 << 17]byte var z14636 [1 << 17]byte var z14637 [1 << 17]byte var z14638 [1 << 17]byte var z14639 [1 << 17]byte var z14640 [1 << 17]byte var z14641 [1 << 17]byte var z14642 [1 << 17]byte var z14643 [1 << 17]byte var z14644 [1 << 17]byte var z14645 [1 << 17]byte var z14646 [1 << 17]byte var z14647 [1 << 17]byte var z14648 [1 << 17]byte var z14649 [1 << 17]byte var z14650 [1 << 17]byte var z14651 [1 << 17]byte var z14652 [1 << 17]byte var z14653 [1 << 17]byte var z14654 [1 << 17]byte var z14655 [1 << 17]byte var z14656 [1 << 17]byte var z14657 [1 << 17]byte var z14658 [1 << 17]byte var z14659 [1 << 17]byte var z14660 [1 << 17]byte var z14661 [1 << 17]byte var z14662 [1 << 17]byte var z14663 [1 << 17]byte var z14664 [1 << 17]byte var z14665 [1 << 17]byte var z14666 [1 << 17]byte var z14667 [1 << 17]byte var z14668 [1 << 17]byte var z14669 [1 << 17]byte var z14670 [1 << 17]byte var z14671 [1 << 17]byte var z14672 [1 << 17]byte var z14673 [1 << 17]byte var z14674 [1 << 17]byte var z14675 [1 << 17]byte var z14676 [1 << 17]byte var z14677 [1 << 17]byte var z14678 [1 << 17]byte var z14679 [1 << 17]byte var z14680 [1 << 17]byte var z14681 [1 << 17]byte var z14682 [1 << 17]byte var z14683 [1 << 17]byte var z14684 [1 << 17]byte var z14685 [1 << 17]byte var z14686 [1 << 17]byte var z14687 [1 << 17]byte var z14688 [1 << 17]byte var z14689 [1 << 17]byte var z14690 [1 << 17]byte var z14691 [1 << 17]byte var z14692 [1 << 17]byte var z14693 [1 << 17]byte var z14694 [1 << 17]byte var z14695 [1 << 17]byte var z14696 [1 << 17]byte var z14697 [1 << 17]byte var z14698 [1 << 17]byte var z14699 [1 << 17]byte var z14700 [1 << 17]byte var z14701 [1 << 17]byte var z14702 [1 << 17]byte var z14703 [1 << 17]byte var z14704 [1 << 17]byte var z14705 [1 << 17]byte var z14706 [1 << 17]byte var z14707 [1 << 17]byte var z14708 [1 << 17]byte var z14709 [1 << 17]byte var z14710 [1 << 17]byte var z14711 [1 << 17]byte var z14712 [1 << 17]byte var z14713 [1 << 17]byte var z14714 [1 << 17]byte var z14715 [1 << 17]byte var z14716 [1 << 17]byte var z14717 [1 << 17]byte var z14718 [1 << 17]byte var z14719 [1 << 17]byte var z14720 [1 << 17]byte var z14721 [1 << 17]byte var z14722 [1 << 17]byte var z14723 [1 << 17]byte var z14724 [1 << 17]byte var z14725 [1 << 17]byte var z14726 [1 << 17]byte var z14727 [1 << 17]byte var z14728 [1 << 17]byte var z14729 [1 << 17]byte var z14730 [1 << 17]byte var z14731 [1 << 17]byte var z14732 [1 << 17]byte var z14733 [1 << 17]byte var z14734 [1 << 17]byte var z14735 [1 << 17]byte var z14736 [1 << 17]byte var z14737 [1 << 17]byte var z14738 [1 << 17]byte var z14739 [1 << 17]byte var z14740 [1 << 17]byte var z14741 [1 << 17]byte var z14742 [1 << 17]byte var z14743 [1 << 17]byte var z14744 [1 << 17]byte var z14745 [1 << 17]byte var z14746 [1 << 17]byte var z14747 [1 << 17]byte var z14748 [1 << 17]byte var z14749 [1 << 17]byte var z14750 [1 << 17]byte var z14751 [1 << 17]byte var z14752 [1 << 17]byte var z14753 [1 << 17]byte var z14754 [1 << 17]byte var z14755 [1 << 17]byte var z14756 [1 << 17]byte var z14757 [1 << 17]byte var z14758 [1 << 17]byte var z14759 [1 << 17]byte var z14760 [1 << 17]byte var z14761 [1 << 17]byte var z14762 [1 << 17]byte var z14763 [1 << 17]byte var z14764 [1 << 17]byte var z14765 [1 << 17]byte var z14766 [1 << 17]byte var z14767 [1 << 17]byte var z14768 [1 << 17]byte var z14769 [1 << 17]byte var z14770 [1 << 17]byte var z14771 [1 << 17]byte var z14772 [1 << 17]byte var z14773 [1 << 17]byte var z14774 [1 << 17]byte var z14775 [1 << 17]byte var z14776 [1 << 17]byte var z14777 [1 << 17]byte var z14778 [1 << 17]byte var z14779 [1 << 17]byte var z14780 [1 << 17]byte var z14781 [1 << 17]byte var z14782 [1 << 17]byte var z14783 [1 << 17]byte var z14784 [1 << 17]byte var z14785 [1 << 17]byte var z14786 [1 << 17]byte var z14787 [1 << 17]byte var z14788 [1 << 17]byte var z14789 [1 << 17]byte var z14790 [1 << 17]byte var z14791 [1 << 17]byte var z14792 [1 << 17]byte var z14793 [1 << 17]byte var z14794 [1 << 17]byte var z14795 [1 << 17]byte var z14796 [1 << 17]byte var z14797 [1 << 17]byte var z14798 [1 << 17]byte var z14799 [1 << 17]byte var z14800 [1 << 17]byte var z14801 [1 << 17]byte var z14802 [1 << 17]byte var z14803 [1 << 17]byte var z14804 [1 << 17]byte var z14805 [1 << 17]byte var z14806 [1 << 17]byte var z14807 [1 << 17]byte var z14808 [1 << 17]byte var z14809 [1 << 17]byte var z14810 [1 << 17]byte var z14811 [1 << 17]byte var z14812 [1 << 17]byte var z14813 [1 << 17]byte var z14814 [1 << 17]byte var z14815 [1 << 17]byte var z14816 [1 << 17]byte var z14817 [1 << 17]byte var z14818 [1 << 17]byte var z14819 [1 << 17]byte var z14820 [1 << 17]byte var z14821 [1 << 17]byte var z14822 [1 << 17]byte var z14823 [1 << 17]byte var z14824 [1 << 17]byte var z14825 [1 << 17]byte var z14826 [1 << 17]byte var z14827 [1 << 17]byte var z14828 [1 << 17]byte var z14829 [1 << 17]byte var z14830 [1 << 17]byte var z14831 [1 << 17]byte var z14832 [1 << 17]byte var z14833 [1 << 17]byte var z14834 [1 << 17]byte var z14835 [1 << 17]byte var z14836 [1 << 17]byte var z14837 [1 << 17]byte var z14838 [1 << 17]byte var z14839 [1 << 17]byte var z14840 [1 << 17]byte var z14841 [1 << 17]byte var z14842 [1 << 17]byte var z14843 [1 << 17]byte var z14844 [1 << 17]byte var z14845 [1 << 17]byte var z14846 [1 << 17]byte var z14847 [1 << 17]byte var z14848 [1 << 17]byte var z14849 [1 << 17]byte var z14850 [1 << 17]byte var z14851 [1 << 17]byte var z14852 [1 << 17]byte var z14853 [1 << 17]byte var z14854 [1 << 17]byte var z14855 [1 << 17]byte var z14856 [1 << 17]byte var z14857 [1 << 17]byte var z14858 [1 << 17]byte var z14859 [1 << 17]byte var z14860 [1 << 17]byte var z14861 [1 << 17]byte var z14862 [1 << 17]byte var z14863 [1 << 17]byte var z14864 [1 << 17]byte var z14865 [1 << 17]byte var z14866 [1 << 17]byte var z14867 [1 << 17]byte var z14868 [1 << 17]byte var z14869 [1 << 17]byte var z14870 [1 << 17]byte var z14871 [1 << 17]byte var z14872 [1 << 17]byte var z14873 [1 << 17]byte var z14874 [1 << 17]byte var z14875 [1 << 17]byte var z14876 [1 << 17]byte var z14877 [1 << 17]byte var z14878 [1 << 17]byte var z14879 [1 << 17]byte var z14880 [1 << 17]byte var z14881 [1 << 17]byte var z14882 [1 << 17]byte var z14883 [1 << 17]byte var z14884 [1 << 17]byte var z14885 [1 << 17]byte var z14886 [1 << 17]byte var z14887 [1 << 17]byte var z14888 [1 << 17]byte var z14889 [1 << 17]byte var z14890 [1 << 17]byte var z14891 [1 << 17]byte var z14892 [1 << 17]byte var z14893 [1 << 17]byte var z14894 [1 << 17]byte var z14895 [1 << 17]byte var z14896 [1 << 17]byte var z14897 [1 << 17]byte var z14898 [1 << 17]byte var z14899 [1 << 17]byte var z14900 [1 << 17]byte var z14901 [1 << 17]byte var z14902 [1 << 17]byte var z14903 [1 << 17]byte var z14904 [1 << 17]byte var z14905 [1 << 17]byte var z14906 [1 << 17]byte var z14907 [1 << 17]byte var z14908 [1 << 17]byte var z14909 [1 << 17]byte var z14910 [1 << 17]byte var z14911 [1 << 17]byte var z14912 [1 << 17]byte var z14913 [1 << 17]byte var z14914 [1 << 17]byte var z14915 [1 << 17]byte var z14916 [1 << 17]byte var z14917 [1 << 17]byte var z14918 [1 << 17]byte var z14919 [1 << 17]byte var z14920 [1 << 17]byte var z14921 [1 << 17]byte var z14922 [1 << 17]byte var z14923 [1 << 17]byte var z14924 [1 << 17]byte var z14925 [1 << 17]byte var z14926 [1 << 17]byte var z14927 [1 << 17]byte var z14928 [1 << 17]byte var z14929 [1 << 17]byte var z14930 [1 << 17]byte var z14931 [1 << 17]byte var z14932 [1 << 17]byte var z14933 [1 << 17]byte var z14934 [1 << 17]byte var z14935 [1 << 17]byte var z14936 [1 << 17]byte var z14937 [1 << 17]byte var z14938 [1 << 17]byte var z14939 [1 << 17]byte var z14940 [1 << 17]byte var z14941 [1 << 17]byte var z14942 [1 << 17]byte var z14943 [1 << 17]byte var z14944 [1 << 17]byte var z14945 [1 << 17]byte var z14946 [1 << 17]byte var z14947 [1 << 17]byte var z14948 [1 << 17]byte var z14949 [1 << 17]byte var z14950 [1 << 17]byte var z14951 [1 << 17]byte var z14952 [1 << 17]byte var z14953 [1 << 17]byte var z14954 [1 << 17]byte var z14955 [1 << 17]byte var z14956 [1 << 17]byte var z14957 [1 << 17]byte var z14958 [1 << 17]byte var z14959 [1 << 17]byte var z14960 [1 << 17]byte var z14961 [1 << 17]byte var z14962 [1 << 17]byte var z14963 [1 << 17]byte var z14964 [1 << 17]byte var z14965 [1 << 17]byte var z14966 [1 << 17]byte var z14967 [1 << 17]byte var z14968 [1 << 17]byte var z14969 [1 << 17]byte var z14970 [1 << 17]byte var z14971 [1 << 17]byte var z14972 [1 << 17]byte var z14973 [1 << 17]byte var z14974 [1 << 17]byte var z14975 [1 << 17]byte var z14976 [1 << 17]byte var z14977 [1 << 17]byte var z14978 [1 << 17]byte var z14979 [1 << 17]byte var z14980 [1 << 17]byte var z14981 [1 << 17]byte var z14982 [1 << 17]byte var z14983 [1 << 17]byte var z14984 [1 << 17]byte var z14985 [1 << 17]byte var z14986 [1 << 17]byte var z14987 [1 << 17]byte var z14988 [1 << 17]byte var z14989 [1 << 17]byte var z14990 [1 << 17]byte var z14991 [1 << 17]byte var z14992 [1 << 17]byte var z14993 [1 << 17]byte var z14994 [1 << 17]byte var z14995 [1 << 17]byte var z14996 [1 << 17]byte var z14997 [1 << 17]byte var z14998 [1 << 17]byte var z14999 [1 << 17]byte var z15000 [1 << 17]byte var z15001 [1 << 17]byte var z15002 [1 << 17]byte var z15003 [1 << 17]byte var z15004 [1 << 17]byte var z15005 [1 << 17]byte var z15006 [1 << 17]byte var z15007 [1 << 17]byte var z15008 [1 << 17]byte var z15009 [1 << 17]byte var z15010 [1 << 17]byte var z15011 [1 << 17]byte var z15012 [1 << 17]byte var z15013 [1 << 17]byte var z15014 [1 << 17]byte var z15015 [1 << 17]byte var z15016 [1 << 17]byte var z15017 [1 << 17]byte var z15018 [1 << 17]byte var z15019 [1 << 17]byte var z15020 [1 << 17]byte var z15021 [1 << 17]byte var z15022 [1 << 17]byte var z15023 [1 << 17]byte var z15024 [1 << 17]byte var z15025 [1 << 17]byte var z15026 [1 << 17]byte var z15027 [1 << 17]byte var z15028 [1 << 17]byte var z15029 [1 << 17]byte var z15030 [1 << 17]byte var z15031 [1 << 17]byte var z15032 [1 << 17]byte var z15033 [1 << 17]byte var z15034 [1 << 17]byte var z15035 [1 << 17]byte var z15036 [1 << 17]byte var z15037 [1 << 17]byte var z15038 [1 << 17]byte var z15039 [1 << 17]byte var z15040 [1 << 17]byte var z15041 [1 << 17]byte var z15042 [1 << 17]byte var z15043 [1 << 17]byte var z15044 [1 << 17]byte var z15045 [1 << 17]byte var z15046 [1 << 17]byte var z15047 [1 << 17]byte var z15048 [1 << 17]byte var z15049 [1 << 17]byte var z15050 [1 << 17]byte var z15051 [1 << 17]byte var z15052 [1 << 17]byte var z15053 [1 << 17]byte var z15054 [1 << 17]byte var z15055 [1 << 17]byte var z15056 [1 << 17]byte var z15057 [1 << 17]byte var z15058 [1 << 17]byte var z15059 [1 << 17]byte var z15060 [1 << 17]byte var z15061 [1 << 17]byte var z15062 [1 << 17]byte var z15063 [1 << 17]byte var z15064 [1 << 17]byte var z15065 [1 << 17]byte var z15066 [1 << 17]byte var z15067 [1 << 17]byte var z15068 [1 << 17]byte var z15069 [1 << 17]byte var z15070 [1 << 17]byte var z15071 [1 << 17]byte var z15072 [1 << 17]byte var z15073 [1 << 17]byte var z15074 [1 << 17]byte var z15075 [1 << 17]byte var z15076 [1 << 17]byte var z15077 [1 << 17]byte var z15078 [1 << 17]byte var z15079 [1 << 17]byte var z15080 [1 << 17]byte var z15081 [1 << 17]byte var z15082 [1 << 17]byte var z15083 [1 << 17]byte var z15084 [1 << 17]byte var z15085 [1 << 17]byte var z15086 [1 << 17]byte var z15087 [1 << 17]byte var z15088 [1 << 17]byte var z15089 [1 << 17]byte var z15090 [1 << 17]byte var z15091 [1 << 17]byte var z15092 [1 << 17]byte var z15093 [1 << 17]byte var z15094 [1 << 17]byte var z15095 [1 << 17]byte var z15096 [1 << 17]byte var z15097 [1 << 17]byte var z15098 [1 << 17]byte var z15099 [1 << 17]byte var z15100 [1 << 17]byte var z15101 [1 << 17]byte var z15102 [1 << 17]byte var z15103 [1 << 17]byte var z15104 [1 << 17]byte var z15105 [1 << 17]byte var z15106 [1 << 17]byte var z15107 [1 << 17]byte var z15108 [1 << 17]byte var z15109 [1 << 17]byte var z15110 [1 << 17]byte var z15111 [1 << 17]byte var z15112 [1 << 17]byte var z15113 [1 << 17]byte var z15114 [1 << 17]byte var z15115 [1 << 17]byte var z15116 [1 << 17]byte var z15117 [1 << 17]byte var z15118 [1 << 17]byte var z15119 [1 << 17]byte var z15120 [1 << 17]byte var z15121 [1 << 17]byte var z15122 [1 << 17]byte var z15123 [1 << 17]byte var z15124 [1 << 17]byte var z15125 [1 << 17]byte var z15126 [1 << 17]byte var z15127 [1 << 17]byte var z15128 [1 << 17]byte var z15129 [1 << 17]byte var z15130 [1 << 17]byte var z15131 [1 << 17]byte var z15132 [1 << 17]byte var z15133 [1 << 17]byte var z15134 [1 << 17]byte var z15135 [1 << 17]byte var z15136 [1 << 17]byte var z15137 [1 << 17]byte var z15138 [1 << 17]byte var z15139 [1 << 17]byte var z15140 [1 << 17]byte var z15141 [1 << 17]byte var z15142 [1 << 17]byte var z15143 [1 << 17]byte var z15144 [1 << 17]byte var z15145 [1 << 17]byte var z15146 [1 << 17]byte var z15147 [1 << 17]byte var z15148 [1 << 17]byte var z15149 [1 << 17]byte var z15150 [1 << 17]byte var z15151 [1 << 17]byte var z15152 [1 << 17]byte var z15153 [1 << 17]byte var z15154 [1 << 17]byte var z15155 [1 << 17]byte var z15156 [1 << 17]byte var z15157 [1 << 17]byte var z15158 [1 << 17]byte var z15159 [1 << 17]byte var z15160 [1 << 17]byte var z15161 [1 << 17]byte var z15162 [1 << 17]byte var z15163 [1 << 17]byte var z15164 [1 << 17]byte var z15165 [1 << 17]byte var z15166 [1 << 17]byte var z15167 [1 << 17]byte var z15168 [1 << 17]byte var z15169 [1 << 17]byte var z15170 [1 << 17]byte var z15171 [1 << 17]byte var z15172 [1 << 17]byte var z15173 [1 << 17]byte var z15174 [1 << 17]byte var z15175 [1 << 17]byte var z15176 [1 << 17]byte var z15177 [1 << 17]byte var z15178 [1 << 17]byte var z15179 [1 << 17]byte var z15180 [1 << 17]byte var z15181 [1 << 17]byte var z15182 [1 << 17]byte var z15183 [1 << 17]byte var z15184 [1 << 17]byte var z15185 [1 << 17]byte var z15186 [1 << 17]byte var z15187 [1 << 17]byte var z15188 [1 << 17]byte var z15189 [1 << 17]byte var z15190 [1 << 17]byte var z15191 [1 << 17]byte var z15192 [1 << 17]byte var z15193 [1 << 17]byte var z15194 [1 << 17]byte var z15195 [1 << 17]byte var z15196 [1 << 17]byte var z15197 [1 << 17]byte var z15198 [1 << 17]byte var z15199 [1 << 17]byte var z15200 [1 << 17]byte var z15201 [1 << 17]byte var z15202 [1 << 17]byte var z15203 [1 << 17]byte var z15204 [1 << 17]byte var z15205 [1 << 17]byte var z15206 [1 << 17]byte var z15207 [1 << 17]byte var z15208 [1 << 17]byte var z15209 [1 << 17]byte var z15210 [1 << 17]byte var z15211 [1 << 17]byte var z15212 [1 << 17]byte var z15213 [1 << 17]byte var z15214 [1 << 17]byte var z15215 [1 << 17]byte var z15216 [1 << 17]byte var z15217 [1 << 17]byte var z15218 [1 << 17]byte var z15219 [1 << 17]byte var z15220 [1 << 17]byte var z15221 [1 << 17]byte var z15222 [1 << 17]byte var z15223 [1 << 17]byte var z15224 [1 << 17]byte var z15225 [1 << 17]byte var z15226 [1 << 17]byte var z15227 [1 << 17]byte var z15228 [1 << 17]byte var z15229 [1 << 17]byte var z15230 [1 << 17]byte var z15231 [1 << 17]byte var z15232 [1 << 17]byte var z15233 [1 << 17]byte var z15234 [1 << 17]byte var z15235 [1 << 17]byte var z15236 [1 << 17]byte var z15237 [1 << 17]byte var z15238 [1 << 17]byte var z15239 [1 << 17]byte var z15240 [1 << 17]byte var z15241 [1 << 17]byte var z15242 [1 << 17]byte var z15243 [1 << 17]byte var z15244 [1 << 17]byte var z15245 [1 << 17]byte var z15246 [1 << 17]byte var z15247 [1 << 17]byte var z15248 [1 << 17]byte var z15249 [1 << 17]byte var z15250 [1 << 17]byte var z15251 [1 << 17]byte var z15252 [1 << 17]byte var z15253 [1 << 17]byte var z15254 [1 << 17]byte var z15255 [1 << 17]byte var z15256 [1 << 17]byte var z15257 [1 << 17]byte var z15258 [1 << 17]byte var z15259 [1 << 17]byte var z15260 [1 << 17]byte var z15261 [1 << 17]byte var z15262 [1 << 17]byte var z15263 [1 << 17]byte var z15264 [1 << 17]byte var z15265 [1 << 17]byte var z15266 [1 << 17]byte var z15267 [1 << 17]byte var z15268 [1 << 17]byte var z15269 [1 << 17]byte var z15270 [1 << 17]byte var z15271 [1 << 17]byte var z15272 [1 << 17]byte var z15273 [1 << 17]byte var z15274 [1 << 17]byte var z15275 [1 << 17]byte var z15276 [1 << 17]byte var z15277 [1 << 17]byte var z15278 [1 << 17]byte var z15279 [1 << 17]byte var z15280 [1 << 17]byte var z15281 [1 << 17]byte var z15282 [1 << 17]byte var z15283 [1 << 17]byte var z15284 [1 << 17]byte var z15285 [1 << 17]byte var z15286 [1 << 17]byte var z15287 [1 << 17]byte var z15288 [1 << 17]byte var z15289 [1 << 17]byte var z15290 [1 << 17]byte var z15291 [1 << 17]byte var z15292 [1 << 17]byte var z15293 [1 << 17]byte var z15294 [1 << 17]byte var z15295 [1 << 17]byte var z15296 [1 << 17]byte var z15297 [1 << 17]byte var z15298 [1 << 17]byte var z15299 [1 << 17]byte var z15300 [1 << 17]byte var z15301 [1 << 17]byte var z15302 [1 << 17]byte var z15303 [1 << 17]byte var z15304 [1 << 17]byte var z15305 [1 << 17]byte var z15306 [1 << 17]byte var z15307 [1 << 17]byte var z15308 [1 << 17]byte var z15309 [1 << 17]byte var z15310 [1 << 17]byte var z15311 [1 << 17]byte var z15312 [1 << 17]byte var z15313 [1 << 17]byte var z15314 [1 << 17]byte var z15315 [1 << 17]byte var z15316 [1 << 17]byte var z15317 [1 << 17]byte var z15318 [1 << 17]byte var z15319 [1 << 17]byte var z15320 [1 << 17]byte var z15321 [1 << 17]byte var z15322 [1 << 17]byte var z15323 [1 << 17]byte var z15324 [1 << 17]byte var z15325 [1 << 17]byte var z15326 [1 << 17]byte var z15327 [1 << 17]byte var z15328 [1 << 17]byte var z15329 [1 << 17]byte var z15330 [1 << 17]byte var z15331 [1 << 17]byte var z15332 [1 << 17]byte var z15333 [1 << 17]byte var z15334 [1 << 17]byte var z15335 [1 << 17]byte var z15336 [1 << 17]byte var z15337 [1 << 17]byte var z15338 [1 << 17]byte var z15339 [1 << 17]byte var z15340 [1 << 17]byte var z15341 [1 << 17]byte var z15342 [1 << 17]byte var z15343 [1 << 17]byte var z15344 [1 << 17]byte var z15345 [1 << 17]byte var z15346 [1 << 17]byte var z15347 [1 << 17]byte var z15348 [1 << 17]byte var z15349 [1 << 17]byte var z15350 [1 << 17]byte var z15351 [1 << 17]byte var z15352 [1 << 17]byte var z15353 [1 << 17]byte var z15354 [1 << 17]byte var z15355 [1 << 17]byte var z15356 [1 << 17]byte var z15357 [1 << 17]byte var z15358 [1 << 17]byte var z15359 [1 << 17]byte var z15360 [1 << 17]byte var z15361 [1 << 17]byte var z15362 [1 << 17]byte var z15363 [1 << 17]byte var z15364 [1 << 17]byte var z15365 [1 << 17]byte var z15366 [1 << 17]byte var z15367 [1 << 17]byte var z15368 [1 << 17]byte var z15369 [1 << 17]byte var z15370 [1 << 17]byte var z15371 [1 << 17]byte var z15372 [1 << 17]byte var z15373 [1 << 17]byte var z15374 [1 << 17]byte var z15375 [1 << 17]byte var z15376 [1 << 17]byte var z15377 [1 << 17]byte var z15378 [1 << 17]byte var z15379 [1 << 17]byte var z15380 [1 << 17]byte var z15381 [1 << 17]byte var z15382 [1 << 17]byte var z15383 [1 << 17]byte var z15384 [1 << 17]byte var z15385 [1 << 17]byte var z15386 [1 << 17]byte var z15387 [1 << 17]byte var z15388 [1 << 17]byte var z15389 [1 << 17]byte var z15390 [1 << 17]byte var z15391 [1 << 17]byte var z15392 [1 << 17]byte var z15393 [1 << 17]byte var z15394 [1 << 17]byte var z15395 [1 << 17]byte var z15396 [1 << 17]byte var z15397 [1 << 17]byte var z15398 [1 << 17]byte var z15399 [1 << 17]byte var z15400 [1 << 17]byte var z15401 [1 << 17]byte var z15402 [1 << 17]byte var z15403 [1 << 17]byte var z15404 [1 << 17]byte var z15405 [1 << 17]byte var z15406 [1 << 17]byte var z15407 [1 << 17]byte var z15408 [1 << 17]byte var z15409 [1 << 17]byte var z15410 [1 << 17]byte var z15411 [1 << 17]byte var z15412 [1 << 17]byte var z15413 [1 << 17]byte var z15414 [1 << 17]byte var z15415 [1 << 17]byte var z15416 [1 << 17]byte var z15417 [1 << 17]byte var z15418 [1 << 17]byte var z15419 [1 << 17]byte var z15420 [1 << 17]byte var z15421 [1 << 17]byte var z15422 [1 << 17]byte var z15423 [1 << 17]byte var z15424 [1 << 17]byte var z15425 [1 << 17]byte var z15426 [1 << 17]byte var z15427 [1 << 17]byte var z15428 [1 << 17]byte var z15429 [1 << 17]byte var z15430 [1 << 17]byte var z15431 [1 << 17]byte var z15432 [1 << 17]byte var z15433 [1 << 17]byte var z15434 [1 << 17]byte var z15435 [1 << 17]byte var z15436 [1 << 17]byte var z15437 [1 << 17]byte var z15438 [1 << 17]byte var z15439 [1 << 17]byte var z15440 [1 << 17]byte var z15441 [1 << 17]byte var z15442 [1 << 17]byte var z15443 [1 << 17]byte var z15444 [1 << 17]byte var z15445 [1 << 17]byte var z15446 [1 << 17]byte var z15447 [1 << 17]byte var z15448 [1 << 17]byte var z15449 [1 << 17]byte var z15450 [1 << 17]byte var z15451 [1 << 17]byte var z15452 [1 << 17]byte var z15453 [1 << 17]byte var z15454 [1 << 17]byte var z15455 [1 << 17]byte var z15456 [1 << 17]byte var z15457 [1 << 17]byte var z15458 [1 << 17]byte var z15459 [1 << 17]byte var z15460 [1 << 17]byte var z15461 [1 << 17]byte var z15462 [1 << 17]byte var z15463 [1 << 17]byte var z15464 [1 << 17]byte var z15465 [1 << 17]byte var z15466 [1 << 17]byte var z15467 [1 << 17]byte var z15468 [1 << 17]byte var z15469 [1 << 17]byte var z15470 [1 << 17]byte var z15471 [1 << 17]byte var z15472 [1 << 17]byte var z15473 [1 << 17]byte var z15474 [1 << 17]byte var z15475 [1 << 17]byte var z15476 [1 << 17]byte var z15477 [1 << 17]byte var z15478 [1 << 17]byte var z15479 [1 << 17]byte var z15480 [1 << 17]byte var z15481 [1 << 17]byte var z15482 [1 << 17]byte var z15483 [1 << 17]byte var z15484 [1 << 17]byte var z15485 [1 << 17]byte var z15486 [1 << 17]byte var z15487 [1 << 17]byte var z15488 [1 << 17]byte var z15489 [1 << 17]byte var z15490 [1 << 17]byte var z15491 [1 << 17]byte var z15492 [1 << 17]byte var z15493 [1 << 17]byte var z15494 [1 << 17]byte var z15495 [1 << 17]byte var z15496 [1 << 17]byte var z15497 [1 << 17]byte var z15498 [1 << 17]byte var z15499 [1 << 17]byte var z15500 [1 << 17]byte var z15501 [1 << 17]byte var z15502 [1 << 17]byte var z15503 [1 << 17]byte var z15504 [1 << 17]byte var z15505 [1 << 17]byte var z15506 [1 << 17]byte var z15507 [1 << 17]byte var z15508 [1 << 17]byte var z15509 [1 << 17]byte var z15510 [1 << 17]byte var z15511 [1 << 17]byte var z15512 [1 << 17]byte var z15513 [1 << 17]byte var z15514 [1 << 17]byte var z15515 [1 << 17]byte var z15516 [1 << 17]byte var z15517 [1 << 17]byte var z15518 [1 << 17]byte var z15519 [1 << 17]byte var z15520 [1 << 17]byte var z15521 [1 << 17]byte var z15522 [1 << 17]byte var z15523 [1 << 17]byte var z15524 [1 << 17]byte var z15525 [1 << 17]byte var z15526 [1 << 17]byte var z15527 [1 << 17]byte var z15528 [1 << 17]byte var z15529 [1 << 17]byte var z15530 [1 << 17]byte var z15531 [1 << 17]byte var z15532 [1 << 17]byte var z15533 [1 << 17]byte var z15534 [1 << 17]byte var z15535 [1 << 17]byte var z15536 [1 << 17]byte var z15537 [1 << 17]byte var z15538 [1 << 17]byte var z15539 [1 << 17]byte var z15540 [1 << 17]byte var z15541 [1 << 17]byte var z15542 [1 << 17]byte var z15543 [1 << 17]byte var z15544 [1 << 17]byte var z15545 [1 << 17]byte var z15546 [1 << 17]byte var z15547 [1 << 17]byte var z15548 [1 << 17]byte var z15549 [1 << 17]byte var z15550 [1 << 17]byte var z15551 [1 << 17]byte var z15552 [1 << 17]byte var z15553 [1 << 17]byte var z15554 [1 << 17]byte var z15555 [1 << 17]byte var z15556 [1 << 17]byte var z15557 [1 << 17]byte var z15558 [1 << 17]byte var z15559 [1 << 17]byte var z15560 [1 << 17]byte var z15561 [1 << 17]byte var z15562 [1 << 17]byte var z15563 [1 << 17]byte var z15564 [1 << 17]byte var z15565 [1 << 17]byte var z15566 [1 << 17]byte var z15567 [1 << 17]byte var z15568 [1 << 17]byte var z15569 [1 << 17]byte var z15570 [1 << 17]byte var z15571 [1 << 17]byte var z15572 [1 << 17]byte var z15573 [1 << 17]byte var z15574 [1 << 17]byte var z15575 [1 << 17]byte var z15576 [1 << 17]byte var z15577 [1 << 17]byte var z15578 [1 << 17]byte var z15579 [1 << 17]byte var z15580 [1 << 17]byte var z15581 [1 << 17]byte var z15582 [1 << 17]byte var z15583 [1 << 17]byte var z15584 [1 << 17]byte var z15585 [1 << 17]byte var z15586 [1 << 17]byte var z15587 [1 << 17]byte var z15588 [1 << 17]byte var z15589 [1 << 17]byte var z15590 [1 << 17]byte var z15591 [1 << 17]byte var z15592 [1 << 17]byte var z15593 [1 << 17]byte var z15594 [1 << 17]byte var z15595 [1 << 17]byte var z15596 [1 << 17]byte var z15597 [1 << 17]byte var z15598 [1 << 17]byte var z15599 [1 << 17]byte var z15600 [1 << 17]byte var z15601 [1 << 17]byte var z15602 [1 << 17]byte var z15603 [1 << 17]byte var z15604 [1 << 17]byte var z15605 [1 << 17]byte var z15606 [1 << 17]byte var z15607 [1 << 17]byte var z15608 [1 << 17]byte var z15609 [1 << 17]byte var z15610 [1 << 17]byte var z15611 [1 << 17]byte var z15612 [1 << 17]byte var z15613 [1 << 17]byte var z15614 [1 << 17]byte var z15615 [1 << 17]byte var z15616 [1 << 17]byte var z15617 [1 << 17]byte var z15618 [1 << 17]byte var z15619 [1 << 17]byte var z15620 [1 << 17]byte var z15621 [1 << 17]byte var z15622 [1 << 17]byte var z15623 [1 << 17]byte var z15624 [1 << 17]byte var z15625 [1 << 17]byte var z15626 [1 << 17]byte var z15627 [1 << 17]byte var z15628 [1 << 17]byte var z15629 [1 << 17]byte var z15630 [1 << 17]byte var z15631 [1 << 17]byte var z15632 [1 << 17]byte var z15633 [1 << 17]byte var z15634 [1 << 17]byte var z15635 [1 << 17]byte var z15636 [1 << 17]byte var z15637 [1 << 17]byte var z15638 [1 << 17]byte var z15639 [1 << 17]byte var z15640 [1 << 17]byte var z15641 [1 << 17]byte var z15642 [1 << 17]byte var z15643 [1 << 17]byte var z15644 [1 << 17]byte var z15645 [1 << 17]byte var z15646 [1 << 17]byte var z15647 [1 << 17]byte var z15648 [1 << 17]byte var z15649 [1 << 17]byte var z15650 [1 << 17]byte var z15651 [1 << 17]byte var z15652 [1 << 17]byte var z15653 [1 << 17]byte var z15654 [1 << 17]byte var z15655 [1 << 17]byte var z15656 [1 << 17]byte var z15657 [1 << 17]byte var z15658 [1 << 17]byte var z15659 [1 << 17]byte var z15660 [1 << 17]byte var z15661 [1 << 17]byte var z15662 [1 << 17]byte var z15663 [1 << 17]byte var z15664 [1 << 17]byte var z15665 [1 << 17]byte var z15666 [1 << 17]byte var z15667 [1 << 17]byte var z15668 [1 << 17]byte var z15669 [1 << 17]byte var z15670 [1 << 17]byte var z15671 [1 << 17]byte var z15672 [1 << 17]byte var z15673 [1 << 17]byte var z15674 [1 << 17]byte var z15675 [1 << 17]byte var z15676 [1 << 17]byte var z15677 [1 << 17]byte var z15678 [1 << 17]byte var z15679 [1 << 17]byte var z15680 [1 << 17]byte var z15681 [1 << 17]byte var z15682 [1 << 17]byte var z15683 [1 << 17]byte var z15684 [1 << 17]byte var z15685 [1 << 17]byte var z15686 [1 << 17]byte var z15687 [1 << 17]byte var z15688 [1 << 17]byte var z15689 [1 << 17]byte var z15690 [1 << 17]byte var z15691 [1 << 17]byte var z15692 [1 << 17]byte var z15693 [1 << 17]byte var z15694 [1 << 17]byte var z15695 [1 << 17]byte var z15696 [1 << 17]byte var z15697 [1 << 17]byte var z15698 [1 << 17]byte var z15699 [1 << 17]byte var z15700 [1 << 17]byte var z15701 [1 << 17]byte var z15702 [1 << 17]byte var z15703 [1 << 17]byte var z15704 [1 << 17]byte var z15705 [1 << 17]byte var z15706 [1 << 17]byte var z15707 [1 << 17]byte var z15708 [1 << 17]byte var z15709 [1 << 17]byte var z15710 [1 << 17]byte var z15711 [1 << 17]byte var z15712 [1 << 17]byte var z15713 [1 << 17]byte var z15714 [1 << 17]byte var z15715 [1 << 17]byte var z15716 [1 << 17]byte var z15717 [1 << 17]byte var z15718 [1 << 17]byte var z15719 [1 << 17]byte var z15720 [1 << 17]byte var z15721 [1 << 17]byte var z15722 [1 << 17]byte var z15723 [1 << 17]byte var z15724 [1 << 17]byte var z15725 [1 << 17]byte var z15726 [1 << 17]byte var z15727 [1 << 17]byte var z15728 [1 << 17]byte var z15729 [1 << 17]byte var z15730 [1 << 17]byte var z15731 [1 << 17]byte var z15732 [1 << 17]byte var z15733 [1 << 17]byte var z15734 [1 << 17]byte var z15735 [1 << 17]byte var z15736 [1 << 17]byte var z15737 [1 << 17]byte var z15738 [1 << 17]byte var z15739 [1 << 17]byte var z15740 [1 << 17]byte var z15741 [1 << 17]byte var z15742 [1 << 17]byte var z15743 [1 << 17]byte var z15744 [1 << 17]byte var z15745 [1 << 17]byte var z15746 [1 << 17]byte var z15747 [1 << 17]byte var z15748 [1 << 17]byte var z15749 [1 << 17]byte var z15750 [1 << 17]byte var z15751 [1 << 17]byte var z15752 [1 << 17]byte var z15753 [1 << 17]byte var z15754 [1 << 17]byte var z15755 [1 << 17]byte var z15756 [1 << 17]byte var z15757 [1 << 17]byte var z15758 [1 << 17]byte var z15759 [1 << 17]byte var z15760 [1 << 17]byte var z15761 [1 << 17]byte var z15762 [1 << 17]byte var z15763 [1 << 17]byte var z15764 [1 << 17]byte var z15765 [1 << 17]byte var z15766 [1 << 17]byte var z15767 [1 << 17]byte var z15768 [1 << 17]byte var z15769 [1 << 17]byte var z15770 [1 << 17]byte var z15771 [1 << 17]byte var z15772 [1 << 17]byte var z15773 [1 << 17]byte var z15774 [1 << 17]byte var z15775 [1 << 17]byte var z15776 [1 << 17]byte var z15777 [1 << 17]byte var z15778 [1 << 17]byte var z15779 [1 << 17]byte var z15780 [1 << 17]byte var z15781 [1 << 17]byte var z15782 [1 << 17]byte var z15783 [1 << 17]byte var z15784 [1 << 17]byte var z15785 [1 << 17]byte var z15786 [1 << 17]byte var z15787 [1 << 17]byte var z15788 [1 << 17]byte var z15789 [1 << 17]byte var z15790 [1 << 17]byte var z15791 [1 << 17]byte var z15792 [1 << 17]byte var z15793 [1 << 17]byte var z15794 [1 << 17]byte var z15795 [1 << 17]byte var z15796 [1 << 17]byte var z15797 [1 << 17]byte var z15798 [1 << 17]byte var z15799 [1 << 17]byte var z15800 [1 << 17]byte var z15801 [1 << 17]byte var z15802 [1 << 17]byte var z15803 [1 << 17]byte var z15804 [1 << 17]byte var z15805 [1 << 17]byte var z15806 [1 << 17]byte var z15807 [1 << 17]byte var z15808 [1 << 17]byte var z15809 [1 << 17]byte var z15810 [1 << 17]byte var z15811 [1 << 17]byte var z15812 [1 << 17]byte var z15813 [1 << 17]byte var z15814 [1 << 17]byte var z15815 [1 << 17]byte var z15816 [1 << 17]byte var z15817 [1 << 17]byte var z15818 [1 << 17]byte var z15819 [1 << 17]byte var z15820 [1 << 17]byte var z15821 [1 << 17]byte var z15822 [1 << 17]byte var z15823 [1 << 17]byte var z15824 [1 << 17]byte var z15825 [1 << 17]byte var z15826 [1 << 17]byte var z15827 [1 << 17]byte var z15828 [1 << 17]byte var z15829 [1 << 17]byte var z15830 [1 << 17]byte var z15831 [1 << 17]byte var z15832 [1 << 17]byte var z15833 [1 << 17]byte var z15834 [1 << 17]byte var z15835 [1 << 17]byte var z15836 [1 << 17]byte var z15837 [1 << 17]byte var z15838 [1 << 17]byte var z15839 [1 << 17]byte var z15840 [1 << 17]byte var z15841 [1 << 17]byte var z15842 [1 << 17]byte var z15843 [1 << 17]byte var z15844 [1 << 17]byte var z15845 [1 << 17]byte var z15846 [1 << 17]byte var z15847 [1 << 17]byte var z15848 [1 << 17]byte var z15849 [1 << 17]byte var z15850 [1 << 17]byte var z15851 [1 << 17]byte var z15852 [1 << 17]byte var z15853 [1 << 17]byte var z15854 [1 << 17]byte var z15855 [1 << 17]byte var z15856 [1 << 17]byte var z15857 [1 << 17]byte var z15858 [1 << 17]byte var z15859 [1 << 17]byte var z15860 [1 << 17]byte var z15861 [1 << 17]byte var z15862 [1 << 17]byte var z15863 [1 << 17]byte var z15864 [1 << 17]byte var z15865 [1 << 17]byte var z15866 [1 << 17]byte var z15867 [1 << 17]byte var z15868 [1 << 17]byte var z15869 [1 << 17]byte var z15870 [1 << 17]byte var z15871 [1 << 17]byte var z15872 [1 << 17]byte var z15873 [1 << 17]byte var z15874 [1 << 17]byte var z15875 [1 << 17]byte var z15876 [1 << 17]byte var z15877 [1 << 17]byte var z15878 [1 << 17]byte var z15879 [1 << 17]byte var z15880 [1 << 17]byte var z15881 [1 << 17]byte var z15882 [1 << 17]byte var z15883 [1 << 17]byte var z15884 [1 << 17]byte var z15885 [1 << 17]byte var z15886 [1 << 17]byte var z15887 [1 << 17]byte var z15888 [1 << 17]byte var z15889 [1 << 17]byte var z15890 [1 << 17]byte var z15891 [1 << 17]byte var z15892 [1 << 17]byte var z15893 [1 << 17]byte var z15894 [1 << 17]byte var z15895 [1 << 17]byte var z15896 [1 << 17]byte var z15897 [1 << 17]byte var z15898 [1 << 17]byte var z15899 [1 << 17]byte var z15900 [1 << 17]byte var z15901 [1 << 17]byte var z15902 [1 << 17]byte var z15903 [1 << 17]byte var z15904 [1 << 17]byte var z15905 [1 << 17]byte var z15906 [1 << 17]byte var z15907 [1 << 17]byte var z15908 [1 << 17]byte var z15909 [1 << 17]byte var z15910 [1 << 17]byte var z15911 [1 << 17]byte var z15912 [1 << 17]byte var z15913 [1 << 17]byte var z15914 [1 << 17]byte var z15915 [1 << 17]byte var z15916 [1 << 17]byte var z15917 [1 << 17]byte var z15918 [1 << 17]byte var z15919 [1 << 17]byte var z15920 [1 << 17]byte var z15921 [1 << 17]byte var z15922 [1 << 17]byte var z15923 [1 << 17]byte var z15924 [1 << 17]byte var z15925 [1 << 17]byte var z15926 [1 << 17]byte var z15927 [1 << 17]byte var z15928 [1 << 17]byte var z15929 [1 << 17]byte var z15930 [1 << 17]byte var z15931 [1 << 17]byte var z15932 [1 << 17]byte var z15933 [1 << 17]byte var z15934 [1 << 17]byte var z15935 [1 << 17]byte var z15936 [1 << 17]byte var z15937 [1 << 17]byte var z15938 [1 << 17]byte var z15939 [1 << 17]byte var z15940 [1 << 17]byte var z15941 [1 << 17]byte var z15942 [1 << 17]byte var z15943 [1 << 17]byte var z15944 [1 << 17]byte var z15945 [1 << 17]byte var z15946 [1 << 17]byte var z15947 [1 << 17]byte var z15948 [1 << 17]byte var z15949 [1 << 17]byte var z15950 [1 << 17]byte var z15951 [1 << 17]byte var z15952 [1 << 17]byte var z15953 [1 << 17]byte var z15954 [1 << 17]byte var z15955 [1 << 17]byte var z15956 [1 << 17]byte var z15957 [1 << 17]byte var z15958 [1 << 17]byte var z15959 [1 << 17]byte var z15960 [1 << 17]byte var z15961 [1 << 17]byte var z15962 [1 << 17]byte var z15963 [1 << 17]byte var z15964 [1 << 17]byte var z15965 [1 << 17]byte var z15966 [1 << 17]byte var z15967 [1 << 17]byte var z15968 [1 << 17]byte var z15969 [1 << 17]byte var z15970 [1 << 17]byte var z15971 [1 << 17]byte var z15972 [1 << 17]byte var z15973 [1 << 17]byte var z15974 [1 << 17]byte var z15975 [1 << 17]byte var z15976 [1 << 17]byte var z15977 [1 << 17]byte var z15978 [1 << 17]byte var z15979 [1 << 17]byte var z15980 [1 << 17]byte var z15981 [1 << 17]byte var z15982 [1 << 17]byte var z15983 [1 << 17]byte var z15984 [1 << 17]byte var z15985 [1 << 17]byte var z15986 [1 << 17]byte var z15987 [1 << 17]byte var z15988 [1 << 17]byte var z15989 [1 << 17]byte var z15990 [1 << 17]byte var z15991 [1 << 17]byte var z15992 [1 << 17]byte var z15993 [1 << 17]byte var z15994 [1 << 17]byte var z15995 [1 << 17]byte var z15996 [1 << 17]byte var z15997 [1 << 17]byte var z15998 [1 << 17]byte var z15999 [1 << 17]byte var z16000 [1 << 17]byte var z16001 [1 << 17]byte var z16002 [1 << 17]byte var z16003 [1 << 17]byte var z16004 [1 << 17]byte var z16005 [1 << 17]byte var z16006 [1 << 17]byte var z16007 [1 << 17]byte var z16008 [1 << 17]byte var z16009 [1 << 17]byte var z16010 [1 << 17]byte var z16011 [1 << 17]byte var z16012 [1 << 17]byte var z16013 [1 << 17]byte var z16014 [1 << 17]byte var z16015 [1 << 17]byte var z16016 [1 << 17]byte var z16017 [1 << 17]byte var z16018 [1 << 17]byte var z16019 [1 << 17]byte var z16020 [1 << 17]byte var z16021 [1 << 17]byte var z16022 [1 << 17]byte var z16023 [1 << 17]byte var z16024 [1 << 17]byte var z16025 [1 << 17]byte var z16026 [1 << 17]byte var z16027 [1 << 17]byte var z16028 [1 << 17]byte var z16029 [1 << 17]byte var z16030 [1 << 17]byte var z16031 [1 << 17]byte var z16032 [1 << 17]byte var z16033 [1 << 17]byte var z16034 [1 << 17]byte var z16035 [1 << 17]byte var z16036 [1 << 17]byte var z16037 [1 << 17]byte var z16038 [1 << 17]byte var z16039 [1 << 17]byte var z16040 [1 << 17]byte var z16041 [1 << 17]byte var z16042 [1 << 17]byte var z16043 [1 << 17]byte var z16044 [1 << 17]byte var z16045 [1 << 17]byte var z16046 [1 << 17]byte var z16047 [1 << 17]byte var z16048 [1 << 17]byte var z16049 [1 << 17]byte var z16050 [1 << 17]byte var z16051 [1 << 17]byte var z16052 [1 << 17]byte var z16053 [1 << 17]byte var z16054 [1 << 17]byte var z16055 [1 << 17]byte var z16056 [1 << 17]byte var z16057 [1 << 17]byte var z16058 [1 << 17]byte var z16059 [1 << 17]byte var z16060 [1 << 17]byte var z16061 [1 << 17]byte var z16062 [1 << 17]byte var z16063 [1 << 17]byte var z16064 [1 << 17]byte var z16065 [1 << 17]byte var z16066 [1 << 17]byte var z16067 [1 << 17]byte var z16068 [1 << 17]byte var z16069 [1 << 17]byte var z16070 [1 << 17]byte var z16071 [1 << 17]byte var z16072 [1 << 17]byte var z16073 [1 << 17]byte var z16074 [1 << 17]byte var z16075 [1 << 17]byte var z16076 [1 << 17]byte var z16077 [1 << 17]byte var z16078 [1 << 17]byte var z16079 [1 << 17]byte var z16080 [1 << 17]byte var z16081 [1 << 17]byte var z16082 [1 << 17]byte var z16083 [1 << 17]byte var z16084 [1 << 17]byte var z16085 [1 << 17]byte var z16086 [1 << 17]byte var z16087 [1 << 17]byte var z16088 [1 << 17]byte var z16089 [1 << 17]byte var z16090 [1 << 17]byte var z16091 [1 << 17]byte var z16092 [1 << 17]byte var z16093 [1 << 17]byte var z16094 [1 << 17]byte var z16095 [1 << 17]byte var z16096 [1 << 17]byte var z16097 [1 << 17]byte var z16098 [1 << 17]byte var z16099 [1 << 17]byte var z16100 [1 << 17]byte var z16101 [1 << 17]byte var z16102 [1 << 17]byte var z16103 [1 << 17]byte var z16104 [1 << 17]byte var z16105 [1 << 17]byte var z16106 [1 << 17]byte var z16107 [1 << 17]byte var z16108 [1 << 17]byte var z16109 [1 << 17]byte var z16110 [1 << 17]byte var z16111 [1 << 17]byte var z16112 [1 << 17]byte var z16113 [1 << 17]byte var z16114 [1 << 17]byte var z16115 [1 << 17]byte var z16116 [1 << 17]byte var z16117 [1 << 17]byte var z16118 [1 << 17]byte var z16119 [1 << 17]byte var z16120 [1 << 17]byte var z16121 [1 << 17]byte var z16122 [1 << 17]byte var z16123 [1 << 17]byte var z16124 [1 << 17]byte var z16125 [1 << 17]byte var z16126 [1 << 17]byte var z16127 [1 << 17]byte var z16128 [1 << 17]byte var z16129 [1 << 17]byte var z16130 [1 << 17]byte var z16131 [1 << 17]byte var z16132 [1 << 17]byte var z16133 [1 << 17]byte var z16134 [1 << 17]byte var z16135 [1 << 17]byte var z16136 [1 << 17]byte var z16137 [1 << 17]byte var z16138 [1 << 17]byte var z16139 [1 << 17]byte var z16140 [1 << 17]byte var z16141 [1 << 17]byte var z16142 [1 << 17]byte var z16143 [1 << 17]byte var z16144 [1 << 17]byte var z16145 [1 << 17]byte var z16146 [1 << 17]byte var z16147 [1 << 17]byte var z16148 [1 << 17]byte var z16149 [1 << 17]byte var z16150 [1 << 17]byte var z16151 [1 << 17]byte var z16152 [1 << 17]byte var z16153 [1 << 17]byte var z16154 [1 << 17]byte var z16155 [1 << 17]byte var z16156 [1 << 17]byte var z16157 [1 << 17]byte var z16158 [1 << 17]byte var z16159 [1 << 17]byte var z16160 [1 << 17]byte var z16161 [1 << 17]byte var z16162 [1 << 17]byte var z16163 [1 << 17]byte var z16164 [1 << 17]byte var z16165 [1 << 17]byte var z16166 [1 << 17]byte var z16167 [1 << 17]byte var z16168 [1 << 17]byte var z16169 [1 << 17]byte var z16170 [1 << 17]byte var z16171 [1 << 17]byte var z16172 [1 << 17]byte var z16173 [1 << 17]byte var z16174 [1 << 17]byte var z16175 [1 << 17]byte var z16176 [1 << 17]byte var z16177 [1 << 17]byte var z16178 [1 << 17]byte var z16179 [1 << 17]byte var z16180 [1 << 17]byte var z16181 [1 << 17]byte var z16182 [1 << 17]byte var z16183 [1 << 17]byte var z16184 [1 << 17]byte var z16185 [1 << 17]byte var z16186 [1 << 17]byte var z16187 [1 << 17]byte var z16188 [1 << 17]byte var z16189 [1 << 17]byte var z16190 [1 << 17]byte var z16191 [1 << 17]byte var z16192 [1 << 17]byte var z16193 [1 << 17]byte var z16194 [1 << 17]byte var z16195 [1 << 17]byte var z16196 [1 << 17]byte var z16197 [1 << 17]byte var z16198 [1 << 17]byte var z16199 [1 << 17]byte var z16200 [1 << 17]byte var z16201 [1 << 17]byte var z16202 [1 << 17]byte var z16203 [1 << 17]byte var z16204 [1 << 17]byte var z16205 [1 << 17]byte var z16206 [1 << 17]byte var z16207 [1 << 17]byte var z16208 [1 << 17]byte var z16209 [1 << 17]byte var z16210 [1 << 17]byte var z16211 [1 << 17]byte var z16212 [1 << 17]byte var z16213 [1 << 17]byte var z16214 [1 << 17]byte var z16215 [1 << 17]byte var z16216 [1 << 17]byte var z16217 [1 << 17]byte var z16218 [1 << 17]byte var z16219 [1 << 17]byte var z16220 [1 << 17]byte var z16221 [1 << 17]byte var z16222 [1 << 17]byte var z16223 [1 << 17]byte var z16224 [1 << 17]byte var z16225 [1 << 17]byte var z16226 [1 << 17]byte var z16227 [1 << 17]byte var z16228 [1 << 17]byte var z16229 [1 << 17]byte var z16230 [1 << 17]byte var z16231 [1 << 17]byte var z16232 [1 << 17]byte var z16233 [1 << 17]byte var z16234 [1 << 17]byte var z16235 [1 << 17]byte var z16236 [1 << 17]byte var z16237 [1 << 17]byte var z16238 [1 << 17]byte var z16239 [1 << 17]byte var z16240 [1 << 17]byte var z16241 [1 << 17]byte var z16242 [1 << 17]byte var z16243 [1 << 17]byte var z16244 [1 << 17]byte var z16245 [1 << 17]byte var z16246 [1 << 17]byte var z16247 [1 << 17]byte var z16248 [1 << 17]byte var z16249 [1 << 17]byte var z16250 [1 << 17]byte var z16251 [1 << 17]byte var z16252 [1 << 17]byte var z16253 [1 << 17]byte var z16254 [1 << 17]byte var z16255 [1 << 17]byte var z16256 [1 << 17]byte var z16257 [1 << 17]byte var z16258 [1 << 17]byte var z16259 [1 << 17]byte var z16260 [1 << 17]byte var z16261 [1 << 17]byte var z16262 [1 << 17]byte var z16263 [1 << 17]byte var z16264 [1 << 17]byte var z16265 [1 << 17]byte var z16266 [1 << 17]byte var z16267 [1 << 17]byte var z16268 [1 << 17]byte var z16269 [1 << 17]byte var z16270 [1 << 17]byte var z16271 [1 << 17]byte var z16272 [1 << 17]byte var z16273 [1 << 17]byte var z16274 [1 << 17]byte var z16275 [1 << 17]byte var z16276 [1 << 17]byte var z16277 [1 << 17]byte var z16278 [1 << 17]byte var z16279 [1 << 17]byte var z16280 [1 << 17]byte var z16281 [1 << 17]byte var z16282 [1 << 17]byte var z16283 [1 << 17]byte var z16284 [1 << 17]byte var z16285 [1 << 17]byte var z16286 [1 << 17]byte var z16287 [1 << 17]byte var z16288 [1 << 17]byte var z16289 [1 << 17]byte var z16290 [1 << 17]byte var z16291 [1 << 17]byte var z16292 [1 << 17]byte var z16293 [1 << 17]byte var z16294 [1 << 17]byte var z16295 [1 << 17]byte var z16296 [1 << 17]byte var z16297 [1 << 17]byte var z16298 [1 << 17]byte var z16299 [1 << 17]byte var z16300 [1 << 17]byte var z16301 [1 << 17]byte var z16302 [1 << 17]byte var z16303 [1 << 17]byte var z16304 [1 << 17]byte var z16305 [1 << 17]byte var z16306 [1 << 17]byte var z16307 [1 << 17]byte var z16308 [1 << 17]byte var z16309 [1 << 17]byte var z16310 [1 << 17]byte var z16311 [1 << 17]byte var z16312 [1 << 17]byte var z16313 [1 << 17]byte var z16314 [1 << 17]byte var z16315 [1 << 17]byte var z16316 [1 << 17]byte var z16317 [1 << 17]byte var z16318 [1 << 17]byte var z16319 [1 << 17]byte var z16320 [1 << 17]byte var z16321 [1 << 17]byte var z16322 [1 << 17]byte var z16323 [1 << 17]byte var z16324 [1 << 17]byte var z16325 [1 << 17]byte var z16326 [1 << 17]byte var z16327 [1 << 17]byte var z16328 [1 << 17]byte var z16329 [1 << 17]byte var z16330 [1 << 17]byte var z16331 [1 << 17]byte var z16332 [1 << 17]byte var z16333 [1 << 17]byte var z16334 [1 << 17]byte var z16335 [1 << 17]byte var z16336 [1 << 17]byte var z16337 [1 << 17]byte var z16338 [1 << 17]byte var z16339 [1 << 17]byte var z16340 [1 << 17]byte var z16341 [1 << 17]byte var z16342 [1 << 17]byte var z16343 [1 << 17]byte var z16344 [1 << 17]byte var z16345 [1 << 17]byte var z16346 [1 << 17]byte var z16347 [1 << 17]byte var z16348 [1 << 17]byte var z16349 [1 << 17]byte var z16350 [1 << 17]byte var z16351 [1 << 17]byte var z16352 [1 << 17]byte var z16353 [1 << 17]byte var z16354 [1 << 17]byte var z16355 [1 << 17]byte var z16356 [1 << 17]byte var z16357 [1 << 17]byte var z16358 [1 << 17]byte var z16359 [1 << 17]byte var z16360 [1 << 17]byte var z16361 [1 << 17]byte var z16362 [1 << 17]byte var z16363 [1 << 17]byte var z16364 [1 << 17]byte var z16365 [1 << 17]byte var z16366 [1 << 17]byte var z16367 [1 << 17]byte var z16368 [1 << 17]byte var z16369 [1 << 17]byte var z16370 [1 << 17]byte var z16371 [1 << 17]byte var z16372 [1 << 17]byte var z16373 [1 << 17]byte var z16374 [1 << 17]byte var z16375 [1 << 17]byte var z16376 [1 << 17]byte var z16377 [1 << 17]byte var z16378 [1 << 17]byte var z16379 [1 << 17]byte var z16380 [1 << 17]byte var z16381 [1 << 17]byte var z16382 [1 << 17]byte var z16383 [1 << 17]byte var z16384 [1 << 17]byte var z16385 [1 << 17]byte var z16386 [1 << 17]byte var z16387 [1 << 17]byte var z16388 [1 << 17]byte var z16389 [1 << 17]byte var z16390 [1 << 17]byte var z16391 [1 << 17]byte var z16392 [1 << 17]byte var z16393 [1 << 17]byte var z16394 [1 << 17]byte var z16395 [1 << 17]byte var z16396 [1 << 17]byte var z16397 [1 << 17]byte var z16398 [1 << 17]byte var z16399 [1 << 17]byte var z16400 [1 << 17]byte var z16401 [1 << 17]byte var z16402 [1 << 17]byte var z16403 [1 << 17]byte var z16404 [1 << 17]byte var z16405 [1 << 17]byte var z16406 [1 << 17]byte var z16407 [1 << 17]byte var z16408 [1 << 17]byte var z16409 [1 << 17]byte var z16410 [1 << 17]byte var z16411 [1 << 17]byte var z16412 [1 << 17]byte var z16413 [1 << 17]byte var z16414 [1 << 17]byte var z16415 [1 << 17]byte var z16416 [1 << 17]byte var z16417 [1 << 17]byte var z16418 [1 << 17]byte var z16419 [1 << 17]byte var z16420 [1 << 17]byte var z16421 [1 << 17]byte var z16422 [1 << 17]byte var z16423 [1 << 17]byte var z16424 [1 << 17]byte var z16425 [1 << 17]byte var z16426 [1 << 17]byte var z16427 [1 << 17]byte var z16428 [1 << 17]byte var z16429 [1 << 17]byte var z16430 [1 << 17]byte var z16431 [1 << 17]byte var z16432 [1 << 17]byte var z16433 [1 << 17]byte var z16434 [1 << 17]byte var z16435 [1 << 17]byte var z16436 [1 << 17]byte var z16437 [1 << 17]byte var z16438 [1 << 17]byte var z16439 [1 << 17]byte var z16440 [1 << 17]byte var z16441 [1 << 17]byte var z16442 [1 << 17]byte var z16443 [1 << 17]byte var z16444 [1 << 17]byte var z16445 [1 << 17]byte var z16446 [1 << 17]byte var z16447 [1 << 17]byte var z16448 [1 << 17]byte var z16449 [1 << 17]byte var z16450 [1 << 17]byte var z16451 [1 << 17]byte var z16452 [1 << 17]byte var z16453 [1 << 17]byte var z16454 [1 << 17]byte var z16455 [1 << 17]byte var z16456 [1 << 17]byte var z16457 [1 << 17]byte var z16458 [1 << 17]byte var z16459 [1 << 17]byte var z16460 [1 << 17]byte var z16461 [1 << 17]byte var z16462 [1 << 17]byte var z16463 [1 << 17]byte var z16464 [1 << 17]byte var z16465 [1 << 17]byte var z16466 [1 << 17]byte var z16467 [1 << 17]byte var z16468 [1 << 17]byte var z16469 [1 << 17]byte var z16470 [1 << 17]byte var z16471 [1 << 17]byte var z16472 [1 << 17]byte var z16473 [1 << 17]byte var z16474 [1 << 17]byte var z16475 [1 << 17]byte var z16476 [1 << 17]byte var z16477 [1 << 17]byte var z16478 [1 << 17]byte var z16479 [1 << 17]byte var z16480 [1 << 17]byte func main() { // GC_ERROR "stack frame too large" // seq 1 16480 | sed 's/.*/ var x& [1 << 17]byte/' // seq 1 16480 | sed 's/.*/ z& = x&/' var x1 [1 << 17]byte var x2 [1 << 17]byte var x3 [1 << 17]byte var x4 [1 << 17]byte var x5 [1 << 17]byte var x6 [1 << 17]byte var x7 [1 << 17]byte var x8 [1 << 17]byte var x9 [1 << 17]byte var x10 [1 << 17]byte var x11 [1 << 17]byte var x12 [1 << 17]byte var x13 [1 << 17]byte var x14 [1 << 17]byte var x15 [1 << 17]byte var x16 [1 << 17]byte var x17 [1 << 17]byte var x18 [1 << 17]byte var x19 [1 << 17]byte var x20 [1 << 17]byte var x21 [1 << 17]byte var x22 [1 << 17]byte var x23 [1 << 17]byte var x24 [1 << 17]byte var x25 [1 << 17]byte var x26 [1 << 17]byte var x27 [1 << 17]byte var x28 [1 << 17]byte var x29 [1 << 17]byte var x30 [1 << 17]byte var x31 [1 << 17]byte var x32 [1 << 17]byte var x33 [1 << 17]byte var x34 [1 << 17]byte var x35 [1 << 17]byte var x36 [1 << 17]byte var x37 [1 << 17]byte var x38 [1 << 17]byte var x39 [1 << 17]byte var x40 [1 << 17]byte var x41 [1 << 17]byte var x42 [1 << 17]byte var x43 [1 << 17]byte var x44 [1 << 17]byte var x45 [1 << 17]byte var x46 [1 << 17]byte var x47 [1 << 17]byte var x48 [1 << 17]byte var x49 [1 << 17]byte var x50 [1 << 17]byte var x51 [1 << 17]byte var x52 [1 << 17]byte var x53 [1 << 17]byte var x54 [1 << 17]byte var x55 [1 << 17]byte var x56 [1 << 17]byte var x57 [1 << 17]byte var x58 [1 << 17]byte var x59 [1 << 17]byte var x60 [1 << 17]byte var x61 [1 << 17]byte var x62 [1 << 17]byte var x63 [1 << 17]byte var x64 [1 << 17]byte var x65 [1 << 17]byte var x66 [1 << 17]byte var x67 [1 << 17]byte var x68 [1 << 17]byte var x69 [1 << 17]byte var x70 [1 << 17]byte var x71 [1 << 17]byte var x72 [1 << 17]byte var x73 [1 << 17]byte var x74 [1 << 17]byte var x75 [1 << 17]byte var x76 [1 << 17]byte var x77 [1 << 17]byte var x78 [1 << 17]byte var x79 [1 << 17]byte var x80 [1 << 17]byte var x81 [1 << 17]byte var x82 [1 << 17]byte var x83 [1 << 17]byte var x84 [1 << 17]byte var x85 [1 << 17]byte var x86 [1 << 17]byte var x87 [1 << 17]byte var x88 [1 << 17]byte var x89 [1 << 17]byte var x90 [1 << 17]byte var x91 [1 << 17]byte var x92 [1 << 17]byte var x93 [1 << 17]byte var x94 [1 << 17]byte var x95 [1 << 17]byte var x96 [1 << 17]byte var x97 [1 << 17]byte var x98 [1 << 17]byte var x99 [1 << 17]byte var x100 [1 << 17]byte var x101 [1 << 17]byte var x102 [1 << 17]byte var x103 [1 << 17]byte var x104 [1 << 17]byte var x105 [1 << 17]byte var x106 [1 << 17]byte var x107 [1 << 17]byte var x108 [1 << 17]byte var x109 [1 << 17]byte var x110 [1 << 17]byte var x111 [1 << 17]byte var x112 [1 << 17]byte var x113 [1 << 17]byte var x114 [1 << 17]byte var x115 [1 << 17]byte var x116 [1 << 17]byte var x117 [1 << 17]byte var x118 [1 << 17]byte var x119 [1 << 17]byte var x120 [1 << 17]byte var x121 [1 << 17]byte var x122 [1 << 17]byte var x123 [1 << 17]byte var x124 [1 << 17]byte var x125 [1 << 17]byte var x126 [1 << 17]byte var x127 [1 << 17]byte var x128 [1 << 17]byte var x129 [1 << 17]byte var x130 [1 << 17]byte var x131 [1 << 17]byte var x132 [1 << 17]byte var x133 [1 << 17]byte var x134 [1 << 17]byte var x135 [1 << 17]byte var x136 [1 << 17]byte var x137 [1 << 17]byte var x138 [1 << 17]byte var x139 [1 << 17]byte var x140 [1 << 17]byte var x141 [1 << 17]byte var x142 [1 << 17]byte var x143 [1 << 17]byte var x144 [1 << 17]byte var x145 [1 << 17]byte var x146 [1 << 17]byte var x147 [1 << 17]byte var x148 [1 << 17]byte var x149 [1 << 17]byte var x150 [1 << 17]byte var x151 [1 << 17]byte var x152 [1 << 17]byte var x153 [1 << 17]byte var x154 [1 << 17]byte var x155 [1 << 17]byte var x156 [1 << 17]byte var x157 [1 << 17]byte var x158 [1 << 17]byte var x159 [1 << 17]byte var x160 [1 << 17]byte var x161 [1 << 17]byte var x162 [1 << 17]byte var x163 [1 << 17]byte var x164 [1 << 17]byte var x165 [1 << 17]byte var x166 [1 << 17]byte var x167 [1 << 17]byte var x168 [1 << 17]byte var x169 [1 << 17]byte var x170 [1 << 17]byte var x171 [1 << 17]byte var x172 [1 << 17]byte var x173 [1 << 17]byte var x174 [1 << 17]byte var x175 [1 << 17]byte var x176 [1 << 17]byte var x177 [1 << 17]byte var x178 [1 << 17]byte var x179 [1 << 17]byte var x180 [1 << 17]byte var x181 [1 << 17]byte var x182 [1 << 17]byte var x183 [1 << 17]byte var x184 [1 << 17]byte var x185 [1 << 17]byte var x186 [1 << 17]byte var x187 [1 << 17]byte var x188 [1 << 17]byte var x189 [1 << 17]byte var x190 [1 << 17]byte var x191 [1 << 17]byte var x192 [1 << 17]byte var x193 [1 << 17]byte var x194 [1 << 17]byte var x195 [1 << 17]byte var x196 [1 << 17]byte var x197 [1 << 17]byte var x198 [1 << 17]byte var x199 [1 << 17]byte var x200 [1 << 17]byte var x201 [1 << 17]byte var x202 [1 << 17]byte var x203 [1 << 17]byte var x204 [1 << 17]byte var x205 [1 << 17]byte var x206 [1 << 17]byte var x207 [1 << 17]byte var x208 [1 << 17]byte var x209 [1 << 17]byte var x210 [1 << 17]byte var x211 [1 << 17]byte var x212 [1 << 17]byte var x213 [1 << 17]byte var x214 [1 << 17]byte var x215 [1 << 17]byte var x216 [1 << 17]byte var x217 [1 << 17]byte var x218 [1 << 17]byte var x219 [1 << 17]byte var x220 [1 << 17]byte var x221 [1 << 17]byte var x222 [1 << 17]byte var x223 [1 << 17]byte var x224 [1 << 17]byte var x225 [1 << 17]byte var x226 [1 << 17]byte var x227 [1 << 17]byte var x228 [1 << 17]byte var x229 [1 << 17]byte var x230 [1 << 17]byte var x231 [1 << 17]byte var x232 [1 << 17]byte var x233 [1 << 17]byte var x234 [1 << 17]byte var x235 [1 << 17]byte var x236 [1 << 17]byte var x237 [1 << 17]byte var x238 [1 << 17]byte var x239 [1 << 17]byte var x240 [1 << 17]byte var x241 [1 << 17]byte var x242 [1 << 17]byte var x243 [1 << 17]byte var x244 [1 << 17]byte var x245 [1 << 17]byte var x246 [1 << 17]byte var x247 [1 << 17]byte var x248 [1 << 17]byte var x249 [1 << 17]byte var x250 [1 << 17]byte var x251 [1 << 17]byte var x252 [1 << 17]byte var x253 [1 << 17]byte var x254 [1 << 17]byte var x255 [1 << 17]byte var x256 [1 << 17]byte var x257 [1 << 17]byte var x258 [1 << 17]byte var x259 [1 << 17]byte var x260 [1 << 17]byte var x261 [1 << 17]byte var x262 [1 << 17]byte var x263 [1 << 17]byte var x264 [1 << 17]byte var x265 [1 << 17]byte var x266 [1 << 17]byte var x267 [1 << 17]byte var x268 [1 << 17]byte var x269 [1 << 17]byte var x270 [1 << 17]byte var x271 [1 << 17]byte var x272 [1 << 17]byte var x273 [1 << 17]byte var x274 [1 << 17]byte var x275 [1 << 17]byte var x276 [1 << 17]byte var x277 [1 << 17]byte var x278 [1 << 17]byte var x279 [1 << 17]byte var x280 [1 << 17]byte var x281 [1 << 17]byte var x282 [1 << 17]byte var x283 [1 << 17]byte var x284 [1 << 17]byte var x285 [1 << 17]byte var x286 [1 << 17]byte var x287 [1 << 17]byte var x288 [1 << 17]byte var x289 [1 << 17]byte var x290 [1 << 17]byte var x291 [1 << 17]byte var x292 [1 << 17]byte var x293 [1 << 17]byte var x294 [1 << 17]byte var x295 [1 << 17]byte var x296 [1 << 17]byte var x297 [1 << 17]byte var x298 [1 << 17]byte var x299 [1 << 17]byte var x300 [1 << 17]byte var x301 [1 << 17]byte var x302 [1 << 17]byte var x303 [1 << 17]byte var x304 [1 << 17]byte var x305 [1 << 17]byte var x306 [1 << 17]byte var x307 [1 << 17]byte var x308 [1 << 17]byte var x309 [1 << 17]byte var x310 [1 << 17]byte var x311 [1 << 17]byte var x312 [1 << 17]byte var x313 [1 << 17]byte var x314 [1 << 17]byte var x315 [1 << 17]byte var x316 [1 << 17]byte var x317 [1 << 17]byte var x318 [1 << 17]byte var x319 [1 << 17]byte var x320 [1 << 17]byte var x321 [1 << 17]byte var x322 [1 << 17]byte var x323 [1 << 17]byte var x324 [1 << 17]byte var x325 [1 << 17]byte var x326 [1 << 17]byte var x327 [1 << 17]byte var x328 [1 << 17]byte var x329 [1 << 17]byte var x330 [1 << 17]byte var x331 [1 << 17]byte var x332 [1 << 17]byte var x333 [1 << 17]byte var x334 [1 << 17]byte var x335 [1 << 17]byte var x336 [1 << 17]byte var x337 [1 << 17]byte var x338 [1 << 17]byte var x339 [1 << 17]byte var x340 [1 << 17]byte var x341 [1 << 17]byte var x342 [1 << 17]byte var x343 [1 << 17]byte var x344 [1 << 17]byte var x345 [1 << 17]byte var x346 [1 << 17]byte var x347 [1 << 17]byte var x348 [1 << 17]byte var x349 [1 << 17]byte var x350 [1 << 17]byte var x351 [1 << 17]byte var x352 [1 << 17]byte var x353 [1 << 17]byte var x354 [1 << 17]byte var x355 [1 << 17]byte var x356 [1 << 17]byte var x357 [1 << 17]byte var x358 [1 << 17]byte var x359 [1 << 17]byte var x360 [1 << 17]byte var x361 [1 << 17]byte var x362 [1 << 17]byte var x363 [1 << 17]byte var x364 [1 << 17]byte var x365 [1 << 17]byte var x366 [1 << 17]byte var x367 [1 << 17]byte var x368 [1 << 17]byte var x369 [1 << 17]byte var x370 [1 << 17]byte var x371 [1 << 17]byte var x372 [1 << 17]byte var x373 [1 << 17]byte var x374 [1 << 17]byte var x375 [1 << 17]byte var x376 [1 << 17]byte var x377 [1 << 17]byte var x378 [1 << 17]byte var x379 [1 << 17]byte var x380 [1 << 17]byte var x381 [1 << 17]byte var x382 [1 << 17]byte var x383 [1 << 17]byte var x384 [1 << 17]byte var x385 [1 << 17]byte var x386 [1 << 17]byte var x387 [1 << 17]byte var x388 [1 << 17]byte var x389 [1 << 17]byte var x390 [1 << 17]byte var x391 [1 << 17]byte var x392 [1 << 17]byte var x393 [1 << 17]byte var x394 [1 << 17]byte var x395 [1 << 17]byte var x396 [1 << 17]byte var x397 [1 << 17]byte var x398 [1 << 17]byte var x399 [1 << 17]byte var x400 [1 << 17]byte var x401 [1 << 17]byte var x402 [1 << 17]byte var x403 [1 << 17]byte var x404 [1 << 17]byte var x405 [1 << 17]byte var x406 [1 << 17]byte var x407 [1 << 17]byte var x408 [1 << 17]byte var x409 [1 << 17]byte var x410 [1 << 17]byte var x411 [1 << 17]byte var x412 [1 << 17]byte var x413 [1 << 17]byte var x414 [1 << 17]byte var x415 [1 << 17]byte var x416 [1 << 17]byte var x417 [1 << 17]byte var x418 [1 << 17]byte var x419 [1 << 17]byte var x420 [1 << 17]byte var x421 [1 << 17]byte var x422 [1 << 17]byte var x423 [1 << 17]byte var x424 [1 << 17]byte var x425 [1 << 17]byte var x426 [1 << 17]byte var x427 [1 << 17]byte var x428 [1 << 17]byte var x429 [1 << 17]byte var x430 [1 << 17]byte var x431 [1 << 17]byte var x432 [1 << 17]byte var x433 [1 << 17]byte var x434 [1 << 17]byte var x435 [1 << 17]byte var x436 [1 << 17]byte var x437 [1 << 17]byte var x438 [1 << 17]byte var x439 [1 << 17]byte var x440 [1 << 17]byte var x441 [1 << 17]byte var x442 [1 << 17]byte var x443 [1 << 17]byte var x444 [1 << 17]byte var x445 [1 << 17]byte var x446 [1 << 17]byte var x447 [1 << 17]byte var x448 [1 << 17]byte var x449 [1 << 17]byte var x450 [1 << 17]byte var x451 [1 << 17]byte var x452 [1 << 17]byte var x453 [1 << 17]byte var x454 [1 << 17]byte var x455 [1 << 17]byte var x456 [1 << 17]byte var x457 [1 << 17]byte var x458 [1 << 17]byte var x459 [1 << 17]byte var x460 [1 << 17]byte var x461 [1 << 17]byte var x462 [1 << 17]byte var x463 [1 << 17]byte var x464 [1 << 17]byte var x465 [1 << 17]byte var x466 [1 << 17]byte var x467 [1 << 17]byte var x468 [1 << 17]byte var x469 [1 << 17]byte var x470 [1 << 17]byte var x471 [1 << 17]byte var x472 [1 << 17]byte var x473 [1 << 17]byte var x474 [1 << 17]byte var x475 [1 << 17]byte var x476 [1 << 17]byte var x477 [1 << 17]byte var x478 [1 << 17]byte var x479 [1 << 17]byte var x480 [1 << 17]byte var x481 [1 << 17]byte var x482 [1 << 17]byte var x483 [1 << 17]byte var x484 [1 << 17]byte var x485 [1 << 17]byte var x486 [1 << 17]byte var x487 [1 << 17]byte var x488 [1 << 17]byte var x489 [1 << 17]byte var x490 [1 << 17]byte var x491 [1 << 17]byte var x492 [1 << 17]byte var x493 [1 << 17]byte var x494 [1 << 17]byte var x495 [1 << 17]byte var x496 [1 << 17]byte var x497 [1 << 17]byte var x498 [1 << 17]byte var x499 [1 << 17]byte var x500 [1 << 17]byte var x501 [1 << 17]byte var x502 [1 << 17]byte var x503 [1 << 17]byte var x504 [1 << 17]byte var x505 [1 << 17]byte var x506 [1 << 17]byte var x507 [1 << 17]byte var x508 [1 << 17]byte var x509 [1 << 17]byte var x510 [1 << 17]byte var x511 [1 << 17]byte var x512 [1 << 17]byte var x513 [1 << 17]byte var x514 [1 << 17]byte var x515 [1 << 17]byte var x516 [1 << 17]byte var x517 [1 << 17]byte var x518 [1 << 17]byte var x519 [1 << 17]byte var x520 [1 << 17]byte var x521 [1 << 17]byte var x522 [1 << 17]byte var x523 [1 << 17]byte var x524 [1 << 17]byte var x525 [1 << 17]byte var x526 [1 << 17]byte var x527 [1 << 17]byte var x528 [1 << 17]byte var x529 [1 << 17]byte var x530 [1 << 17]byte var x531 [1 << 17]byte var x532 [1 << 17]byte var x533 [1 << 17]byte var x534 [1 << 17]byte var x535 [1 << 17]byte var x536 [1 << 17]byte var x537 [1 << 17]byte var x538 [1 << 17]byte var x539 [1 << 17]byte var x540 [1 << 17]byte var x541 [1 << 17]byte var x542 [1 << 17]byte var x543 [1 << 17]byte var x544 [1 << 17]byte var x545 [1 << 17]byte var x546 [1 << 17]byte var x547 [1 << 17]byte var x548 [1 << 17]byte var x549 [1 << 17]byte var x550 [1 << 17]byte var x551 [1 << 17]byte var x552 [1 << 17]byte var x553 [1 << 17]byte var x554 [1 << 17]byte var x555 [1 << 17]byte var x556 [1 << 17]byte var x557 [1 << 17]byte var x558 [1 << 17]byte var x559 [1 << 17]byte var x560 [1 << 17]byte var x561 [1 << 17]byte var x562 [1 << 17]byte var x563 [1 << 17]byte var x564 [1 << 17]byte var x565 [1 << 17]byte var x566 [1 << 17]byte var x567 [1 << 17]byte var x568 [1 << 17]byte var x569 [1 << 17]byte var x570 [1 << 17]byte var x571 [1 << 17]byte var x572 [1 << 17]byte var x573 [1 << 17]byte var x574 [1 << 17]byte var x575 [1 << 17]byte var x576 [1 << 17]byte var x577 [1 << 17]byte var x578 [1 << 17]byte var x579 [1 << 17]byte var x580 [1 << 17]byte var x581 [1 << 17]byte var x582 [1 << 17]byte var x583 [1 << 17]byte var x584 [1 << 17]byte var x585 [1 << 17]byte var x586 [1 << 17]byte var x587 [1 << 17]byte var x588 [1 << 17]byte var x589 [1 << 17]byte var x590 [1 << 17]byte var x591 [1 << 17]byte var x592 [1 << 17]byte var x593 [1 << 17]byte var x594 [1 << 17]byte var x595 [1 << 17]byte var x596 [1 << 17]byte var x597 [1 << 17]byte var x598 [1 << 17]byte var x599 [1 << 17]byte var x600 [1 << 17]byte var x601 [1 << 17]byte var x602 [1 << 17]byte var x603 [1 << 17]byte var x604 [1 << 17]byte var x605 [1 << 17]byte var x606 [1 << 17]byte var x607 [1 << 17]byte var x608 [1 << 17]byte var x609 [1 << 17]byte var x610 [1 << 17]byte var x611 [1 << 17]byte var x612 [1 << 17]byte var x613 [1 << 17]byte var x614 [1 << 17]byte var x615 [1 << 17]byte var x616 [1 << 17]byte var x617 [1 << 17]byte var x618 [1 << 17]byte var x619 [1 << 17]byte var x620 [1 << 17]byte var x621 [1 << 17]byte var x622 [1 << 17]byte var x623 [1 << 17]byte var x624 [1 << 17]byte var x625 [1 << 17]byte var x626 [1 << 17]byte var x627 [1 << 17]byte var x628 [1 << 17]byte var x629 [1 << 17]byte var x630 [1 << 17]byte var x631 [1 << 17]byte var x632 [1 << 17]byte var x633 [1 << 17]byte var x634 [1 << 17]byte var x635 [1 << 17]byte var x636 [1 << 17]byte var x637 [1 << 17]byte var x638 [1 << 17]byte var x639 [1 << 17]byte var x640 [1 << 17]byte var x641 [1 << 17]byte var x642 [1 << 17]byte var x643 [1 << 17]byte var x644 [1 << 17]byte var x645 [1 << 17]byte var x646 [1 << 17]byte var x647 [1 << 17]byte var x648 [1 << 17]byte var x649 [1 << 17]byte var x650 [1 << 17]byte var x651 [1 << 17]byte var x652 [1 << 17]byte var x653 [1 << 17]byte var x654 [1 << 17]byte var x655 [1 << 17]byte var x656 [1 << 17]byte var x657 [1 << 17]byte var x658 [1 << 17]byte var x659 [1 << 17]byte var x660 [1 << 17]byte var x661 [1 << 17]byte var x662 [1 << 17]byte var x663 [1 << 17]byte var x664 [1 << 17]byte var x665 [1 << 17]byte var x666 [1 << 17]byte var x667 [1 << 17]byte var x668 [1 << 17]byte var x669 [1 << 17]byte var x670 [1 << 17]byte var x671 [1 << 17]byte var x672 [1 << 17]byte var x673 [1 << 17]byte var x674 [1 << 17]byte var x675 [1 << 17]byte var x676 [1 << 17]byte var x677 [1 << 17]byte var x678 [1 << 17]byte var x679 [1 << 17]byte var x680 [1 << 17]byte var x681 [1 << 17]byte var x682 [1 << 17]byte var x683 [1 << 17]byte var x684 [1 << 17]byte var x685 [1 << 17]byte var x686 [1 << 17]byte var x687 [1 << 17]byte var x688 [1 << 17]byte var x689 [1 << 17]byte var x690 [1 << 17]byte var x691 [1 << 17]byte var x692 [1 << 17]byte var x693 [1 << 17]byte var x694 [1 << 17]byte var x695 [1 << 17]byte var x696 [1 << 17]byte var x697 [1 << 17]byte var x698 [1 << 17]byte var x699 [1 << 17]byte var x700 [1 << 17]byte var x701 [1 << 17]byte var x702 [1 << 17]byte var x703 [1 << 17]byte var x704 [1 << 17]byte var x705 [1 << 17]byte var x706 [1 << 17]byte var x707 [1 << 17]byte var x708 [1 << 17]byte var x709 [1 << 17]byte var x710 [1 << 17]byte var x711 [1 << 17]byte var x712 [1 << 17]byte var x713 [1 << 17]byte var x714 [1 << 17]byte var x715 [1 << 17]byte var x716 [1 << 17]byte var x717 [1 << 17]byte var x718 [1 << 17]byte var x719 [1 << 17]byte var x720 [1 << 17]byte var x721 [1 << 17]byte var x722 [1 << 17]byte var x723 [1 << 17]byte var x724 [1 << 17]byte var x725 [1 << 17]byte var x726 [1 << 17]byte var x727 [1 << 17]byte var x728 [1 << 17]byte var x729 [1 << 17]byte var x730 [1 << 17]byte var x731 [1 << 17]byte var x732 [1 << 17]byte var x733 [1 << 17]byte var x734 [1 << 17]byte var x735 [1 << 17]byte var x736 [1 << 17]byte var x737 [1 << 17]byte var x738 [1 << 17]byte var x739 [1 << 17]byte var x740 [1 << 17]byte var x741 [1 << 17]byte var x742 [1 << 17]byte var x743 [1 << 17]byte var x744 [1 << 17]byte var x745 [1 << 17]byte var x746 [1 << 17]byte var x747 [1 << 17]byte var x748 [1 << 17]byte var x749 [1 << 17]byte var x750 [1 << 17]byte var x751 [1 << 17]byte var x752 [1 << 17]byte var x753 [1 << 17]byte var x754 [1 << 17]byte var x755 [1 << 17]byte var x756 [1 << 17]byte var x757 [1 << 17]byte var x758 [1 << 17]byte var x759 [1 << 17]byte var x760 [1 << 17]byte var x761 [1 << 17]byte var x762 [1 << 17]byte var x763 [1 << 17]byte var x764 [1 << 17]byte var x765 [1 << 17]byte var x766 [1 << 17]byte var x767 [1 << 17]byte var x768 [1 << 17]byte var x769 [1 << 17]byte var x770 [1 << 17]byte var x771 [1 << 17]byte var x772 [1 << 17]byte var x773 [1 << 17]byte var x774 [1 << 17]byte var x775 [1 << 17]byte var x776 [1 << 17]byte var x777 [1 << 17]byte var x778 [1 << 17]byte var x779 [1 << 17]byte var x780 [1 << 17]byte var x781 [1 << 17]byte var x782 [1 << 17]byte var x783 [1 << 17]byte var x784 [1 << 17]byte var x785 [1 << 17]byte var x786 [1 << 17]byte var x787 [1 << 17]byte var x788 [1 << 17]byte var x789 [1 << 17]byte var x790 [1 << 17]byte var x791 [1 << 17]byte var x792 [1 << 17]byte var x793 [1 << 17]byte var x794 [1 << 17]byte var x795 [1 << 17]byte var x796 [1 << 17]byte var x797 [1 << 17]byte var x798 [1 << 17]byte var x799 [1 << 17]byte var x800 [1 << 17]byte var x801 [1 << 17]byte var x802 [1 << 17]byte var x803 [1 << 17]byte var x804 [1 << 17]byte var x805 [1 << 17]byte var x806 [1 << 17]byte var x807 [1 << 17]byte var x808 [1 << 17]byte var x809 [1 << 17]byte var x810 [1 << 17]byte var x811 [1 << 17]byte var x812 [1 << 17]byte var x813 [1 << 17]byte var x814 [1 << 17]byte var x815 [1 << 17]byte var x816 [1 << 17]byte var x817 [1 << 17]byte var x818 [1 << 17]byte var x819 [1 << 17]byte var x820 [1 << 17]byte var x821 [1 << 17]byte var x822 [1 << 17]byte var x823 [1 << 17]byte var x824 [1 << 17]byte var x825 [1 << 17]byte var x826 [1 << 17]byte var x827 [1 << 17]byte var x828 [1 << 17]byte var x829 [1 << 17]byte var x830 [1 << 17]byte var x831 [1 << 17]byte var x832 [1 << 17]byte var x833 [1 << 17]byte var x834 [1 << 17]byte var x835 [1 << 17]byte var x836 [1 << 17]byte var x837 [1 << 17]byte var x838 [1 << 17]byte var x839 [1 << 17]byte var x840 [1 << 17]byte var x841 [1 << 17]byte var x842 [1 << 17]byte var x843 [1 << 17]byte var x844 [1 << 17]byte var x845 [1 << 17]byte var x846 [1 << 17]byte var x847 [1 << 17]byte var x848 [1 << 17]byte var x849 [1 << 17]byte var x850 [1 << 17]byte var x851 [1 << 17]byte var x852 [1 << 17]byte var x853 [1 << 17]byte var x854 [1 << 17]byte var x855 [1 << 17]byte var x856 [1 << 17]byte var x857 [1 << 17]byte var x858 [1 << 17]byte var x859 [1 << 17]byte var x860 [1 << 17]byte var x861 [1 << 17]byte var x862 [1 << 17]byte var x863 [1 << 17]byte var x864 [1 << 17]byte var x865 [1 << 17]byte var x866 [1 << 17]byte var x867 [1 << 17]byte var x868 [1 << 17]byte var x869 [1 << 17]byte var x870 [1 << 17]byte var x871 [1 << 17]byte var x872 [1 << 17]byte var x873 [1 << 17]byte var x874 [1 << 17]byte var x875 [1 << 17]byte var x876 [1 << 17]byte var x877 [1 << 17]byte var x878 [1 << 17]byte var x879 [1 << 17]byte var x880 [1 << 17]byte var x881 [1 << 17]byte var x882 [1 << 17]byte var x883 [1 << 17]byte var x884 [1 << 17]byte var x885 [1 << 17]byte var x886 [1 << 17]byte var x887 [1 << 17]byte var x888 [1 << 17]byte var x889 [1 << 17]byte var x890 [1 << 17]byte var x891 [1 << 17]byte var x892 [1 << 17]byte var x893 [1 << 17]byte var x894 [1 << 17]byte var x895 [1 << 17]byte var x896 [1 << 17]byte var x897 [1 << 17]byte var x898 [1 << 17]byte var x899 [1 << 17]byte var x900 [1 << 17]byte var x901 [1 << 17]byte var x902 [1 << 17]byte var x903 [1 << 17]byte var x904 [1 << 17]byte var x905 [1 << 17]byte var x906 [1 << 17]byte var x907 [1 << 17]byte var x908 [1 << 17]byte var x909 [1 << 17]byte var x910 [1 << 17]byte var x911 [1 << 17]byte var x912 [1 << 17]byte var x913 [1 << 17]byte var x914 [1 << 17]byte var x915 [1 << 17]byte var x916 [1 << 17]byte var x917 [1 << 17]byte var x918 [1 << 17]byte var x919 [1 << 17]byte var x920 [1 << 17]byte var x921 [1 << 17]byte var x922 [1 << 17]byte var x923 [1 << 17]byte var x924 [1 << 17]byte var x925 [1 << 17]byte var x926 [1 << 17]byte var x927 [1 << 17]byte var x928 [1 << 17]byte var x929 [1 << 17]byte var x930 [1 << 17]byte var x931 [1 << 17]byte var x932 [1 << 17]byte var x933 [1 << 17]byte var x934 [1 << 17]byte var x935 [1 << 17]byte var x936 [1 << 17]byte var x937 [1 << 17]byte var x938 [1 << 17]byte var x939 [1 << 17]byte var x940 [1 << 17]byte var x941 [1 << 17]byte var x942 [1 << 17]byte var x943 [1 << 17]byte var x944 [1 << 17]byte var x945 [1 << 17]byte var x946 [1 << 17]byte var x947 [1 << 17]byte var x948 [1 << 17]byte var x949 [1 << 17]byte var x950 [1 << 17]byte var x951 [1 << 17]byte var x952 [1 << 17]byte var x953 [1 << 17]byte var x954 [1 << 17]byte var x955 [1 << 17]byte var x956 [1 << 17]byte var x957 [1 << 17]byte var x958 [1 << 17]byte var x959 [1 << 17]byte var x960 [1 << 17]byte var x961 [1 << 17]byte var x962 [1 << 17]byte var x963 [1 << 17]byte var x964 [1 << 17]byte var x965 [1 << 17]byte var x966 [1 << 17]byte var x967 [1 << 17]byte var x968 [1 << 17]byte var x969 [1 << 17]byte var x970 [1 << 17]byte var x971 [1 << 17]byte var x972 [1 << 17]byte var x973 [1 << 17]byte var x974 [1 << 17]byte var x975 [1 << 17]byte var x976 [1 << 17]byte var x977 [1 << 17]byte var x978 [1 << 17]byte var x979 [1 << 17]byte var x980 [1 << 17]byte var x981 [1 << 17]byte var x982 [1 << 17]byte var x983 [1 << 17]byte var x984 [1 << 17]byte var x985 [1 << 17]byte var x986 [1 << 17]byte var x987 [1 << 17]byte var x988 [1 << 17]byte var x989 [1 << 17]byte var x990 [1 << 17]byte var x991 [1 << 17]byte var x992 [1 << 17]byte var x993 [1 << 17]byte var x994 [1 << 17]byte var x995 [1 << 17]byte var x996 [1 << 17]byte var x997 [1 << 17]byte var x998 [1 << 17]byte var x999 [1 << 17]byte var x1000 [1 << 17]byte var x1001 [1 << 17]byte var x1002 [1 << 17]byte var x1003 [1 << 17]byte var x1004 [1 << 17]byte var x1005 [1 << 17]byte var x1006 [1 << 17]byte var x1007 [1 << 17]byte var x1008 [1 << 17]byte var x1009 [1 << 17]byte var x1010 [1 << 17]byte var x1011 [1 << 17]byte var x1012 [1 << 17]byte var x1013 [1 << 17]byte var x1014 [1 << 17]byte var x1015 [1 << 17]byte var x1016 [1 << 17]byte var x1017 [1 << 17]byte var x1018 [1 << 17]byte var x1019 [1 << 17]byte var x1020 [1 << 17]byte var x1021 [1 << 17]byte var x1022 [1 << 17]byte var x1023 [1 << 17]byte var x1024 [1 << 17]byte var x1025 [1 << 17]byte var x1026 [1 << 17]byte var x1027 [1 << 17]byte var x1028 [1 << 17]byte var x1029 [1 << 17]byte var x1030 [1 << 17]byte var x1031 [1 << 17]byte var x1032 [1 << 17]byte var x1033 [1 << 17]byte var x1034 [1 << 17]byte var x1035 [1 << 17]byte var x1036 [1 << 17]byte var x1037 [1 << 17]byte var x1038 [1 << 17]byte var x1039 [1 << 17]byte var x1040 [1 << 17]byte var x1041 [1 << 17]byte var x1042 [1 << 17]byte var x1043 [1 << 17]byte var x1044 [1 << 17]byte var x1045 [1 << 17]byte var x1046 [1 << 17]byte var x1047 [1 << 17]byte var x1048 [1 << 17]byte var x1049 [1 << 17]byte var x1050 [1 << 17]byte var x1051 [1 << 17]byte var x1052 [1 << 17]byte var x1053 [1 << 17]byte var x1054 [1 << 17]byte var x1055 [1 << 17]byte var x1056 [1 << 17]byte var x1057 [1 << 17]byte var x1058 [1 << 17]byte var x1059 [1 << 17]byte var x1060 [1 << 17]byte var x1061 [1 << 17]byte var x1062 [1 << 17]byte var x1063 [1 << 17]byte var x1064 [1 << 17]byte var x1065 [1 << 17]byte var x1066 [1 << 17]byte var x1067 [1 << 17]byte var x1068 [1 << 17]byte var x1069 [1 << 17]byte var x1070 [1 << 17]byte var x1071 [1 << 17]byte var x1072 [1 << 17]byte var x1073 [1 << 17]byte var x1074 [1 << 17]byte var x1075 [1 << 17]byte var x1076 [1 << 17]byte var x1077 [1 << 17]byte var x1078 [1 << 17]byte var x1079 [1 << 17]byte var x1080 [1 << 17]byte var x1081 [1 << 17]byte var x1082 [1 << 17]byte var x1083 [1 << 17]byte var x1084 [1 << 17]byte var x1085 [1 << 17]byte var x1086 [1 << 17]byte var x1087 [1 << 17]byte var x1088 [1 << 17]byte var x1089 [1 << 17]byte var x1090 [1 << 17]byte var x1091 [1 << 17]byte var x1092 [1 << 17]byte var x1093 [1 << 17]byte var x1094 [1 << 17]byte var x1095 [1 << 17]byte var x1096 [1 << 17]byte var x1097 [1 << 17]byte var x1098 [1 << 17]byte var x1099 [1 << 17]byte var x1100 [1 << 17]byte var x1101 [1 << 17]byte var x1102 [1 << 17]byte var x1103 [1 << 17]byte var x1104 [1 << 17]byte var x1105 [1 << 17]byte var x1106 [1 << 17]byte var x1107 [1 << 17]byte var x1108 [1 << 17]byte var x1109 [1 << 17]byte var x1110 [1 << 17]byte var x1111 [1 << 17]byte var x1112 [1 << 17]byte var x1113 [1 << 17]byte var x1114 [1 << 17]byte var x1115 [1 << 17]byte var x1116 [1 << 17]byte var x1117 [1 << 17]byte var x1118 [1 << 17]byte var x1119 [1 << 17]byte var x1120 [1 << 17]byte var x1121 [1 << 17]byte var x1122 [1 << 17]byte var x1123 [1 << 17]byte var x1124 [1 << 17]byte var x1125 [1 << 17]byte var x1126 [1 << 17]byte var x1127 [1 << 17]byte var x1128 [1 << 17]byte var x1129 [1 << 17]byte var x1130 [1 << 17]byte var x1131 [1 << 17]byte var x1132 [1 << 17]byte var x1133 [1 << 17]byte var x1134 [1 << 17]byte var x1135 [1 << 17]byte var x1136 [1 << 17]byte var x1137 [1 << 17]byte var x1138 [1 << 17]byte var x1139 [1 << 17]byte var x1140 [1 << 17]byte var x1141 [1 << 17]byte var x1142 [1 << 17]byte var x1143 [1 << 17]byte var x1144 [1 << 17]byte var x1145 [1 << 17]byte var x1146 [1 << 17]byte var x1147 [1 << 17]byte var x1148 [1 << 17]byte var x1149 [1 << 17]byte var x1150 [1 << 17]byte var x1151 [1 << 17]byte var x1152 [1 << 17]byte var x1153 [1 << 17]byte var x1154 [1 << 17]byte var x1155 [1 << 17]byte var x1156 [1 << 17]byte var x1157 [1 << 17]byte var x1158 [1 << 17]byte var x1159 [1 << 17]byte var x1160 [1 << 17]byte var x1161 [1 << 17]byte var x1162 [1 << 17]byte var x1163 [1 << 17]byte var x1164 [1 << 17]byte var x1165 [1 << 17]byte var x1166 [1 << 17]byte var x1167 [1 << 17]byte var x1168 [1 << 17]byte var x1169 [1 << 17]byte var x1170 [1 << 17]byte var x1171 [1 << 17]byte var x1172 [1 << 17]byte var x1173 [1 << 17]byte var x1174 [1 << 17]byte var x1175 [1 << 17]byte var x1176 [1 << 17]byte var x1177 [1 << 17]byte var x1178 [1 << 17]byte var x1179 [1 << 17]byte var x1180 [1 << 17]byte var x1181 [1 << 17]byte var x1182 [1 << 17]byte var x1183 [1 << 17]byte var x1184 [1 << 17]byte var x1185 [1 << 17]byte var x1186 [1 << 17]byte var x1187 [1 << 17]byte var x1188 [1 << 17]byte var x1189 [1 << 17]byte var x1190 [1 << 17]byte var x1191 [1 << 17]byte var x1192 [1 << 17]byte var x1193 [1 << 17]byte var x1194 [1 << 17]byte var x1195 [1 << 17]byte var x1196 [1 << 17]byte var x1197 [1 << 17]byte var x1198 [1 << 17]byte var x1199 [1 << 17]byte var x1200 [1 << 17]byte var x1201 [1 << 17]byte var x1202 [1 << 17]byte var x1203 [1 << 17]byte var x1204 [1 << 17]byte var x1205 [1 << 17]byte var x1206 [1 << 17]byte var x1207 [1 << 17]byte var x1208 [1 << 17]byte var x1209 [1 << 17]byte var x1210 [1 << 17]byte var x1211 [1 << 17]byte var x1212 [1 << 17]byte var x1213 [1 << 17]byte var x1214 [1 << 17]byte var x1215 [1 << 17]byte var x1216 [1 << 17]byte var x1217 [1 << 17]byte var x1218 [1 << 17]byte var x1219 [1 << 17]byte var x1220 [1 << 17]byte var x1221 [1 << 17]byte var x1222 [1 << 17]byte var x1223 [1 << 17]byte var x1224 [1 << 17]byte var x1225 [1 << 17]byte var x1226 [1 << 17]byte var x1227 [1 << 17]byte var x1228 [1 << 17]byte var x1229 [1 << 17]byte var x1230 [1 << 17]byte var x1231 [1 << 17]byte var x1232 [1 << 17]byte var x1233 [1 << 17]byte var x1234 [1 << 17]byte var x1235 [1 << 17]byte var x1236 [1 << 17]byte var x1237 [1 << 17]byte var x1238 [1 << 17]byte var x1239 [1 << 17]byte var x1240 [1 << 17]byte var x1241 [1 << 17]byte var x1242 [1 << 17]byte var x1243 [1 << 17]byte var x1244 [1 << 17]byte var x1245 [1 << 17]byte var x1246 [1 << 17]byte var x1247 [1 << 17]byte var x1248 [1 << 17]byte var x1249 [1 << 17]byte var x1250 [1 << 17]byte var x1251 [1 << 17]byte var x1252 [1 << 17]byte var x1253 [1 << 17]byte var x1254 [1 << 17]byte var x1255 [1 << 17]byte var x1256 [1 << 17]byte var x1257 [1 << 17]byte var x1258 [1 << 17]byte var x1259 [1 << 17]byte var x1260 [1 << 17]byte var x1261 [1 << 17]byte var x1262 [1 << 17]byte var x1263 [1 << 17]byte var x1264 [1 << 17]byte var x1265 [1 << 17]byte var x1266 [1 << 17]byte var x1267 [1 << 17]byte var x1268 [1 << 17]byte var x1269 [1 << 17]byte var x1270 [1 << 17]byte var x1271 [1 << 17]byte var x1272 [1 << 17]byte var x1273 [1 << 17]byte var x1274 [1 << 17]byte var x1275 [1 << 17]byte var x1276 [1 << 17]byte var x1277 [1 << 17]byte var x1278 [1 << 17]byte var x1279 [1 << 17]byte var x1280 [1 << 17]byte var x1281 [1 << 17]byte var x1282 [1 << 17]byte var x1283 [1 << 17]byte var x1284 [1 << 17]byte var x1285 [1 << 17]byte var x1286 [1 << 17]byte var x1287 [1 << 17]byte var x1288 [1 << 17]byte var x1289 [1 << 17]byte var x1290 [1 << 17]byte var x1291 [1 << 17]byte var x1292 [1 << 17]byte var x1293 [1 << 17]byte var x1294 [1 << 17]byte var x1295 [1 << 17]byte var x1296 [1 << 17]byte var x1297 [1 << 17]byte var x1298 [1 << 17]byte var x1299 [1 << 17]byte var x1300 [1 << 17]byte var x1301 [1 << 17]byte var x1302 [1 << 17]byte var x1303 [1 << 17]byte var x1304 [1 << 17]byte var x1305 [1 << 17]byte var x1306 [1 << 17]byte var x1307 [1 << 17]byte var x1308 [1 << 17]byte var x1309 [1 << 17]byte var x1310 [1 << 17]byte var x1311 [1 << 17]byte var x1312 [1 << 17]byte var x1313 [1 << 17]byte var x1314 [1 << 17]byte var x1315 [1 << 17]byte var x1316 [1 << 17]byte var x1317 [1 << 17]byte var x1318 [1 << 17]byte var x1319 [1 << 17]byte var x1320 [1 << 17]byte var x1321 [1 << 17]byte var x1322 [1 << 17]byte var x1323 [1 << 17]byte var x1324 [1 << 17]byte var x1325 [1 << 17]byte var x1326 [1 << 17]byte var x1327 [1 << 17]byte var x1328 [1 << 17]byte var x1329 [1 << 17]byte var x1330 [1 << 17]byte var x1331 [1 << 17]byte var x1332 [1 << 17]byte var x1333 [1 << 17]byte var x1334 [1 << 17]byte var x1335 [1 << 17]byte var x1336 [1 << 17]byte var x1337 [1 << 17]byte var x1338 [1 << 17]byte var x1339 [1 << 17]byte var x1340 [1 << 17]byte var x1341 [1 << 17]byte var x1342 [1 << 17]byte var x1343 [1 << 17]byte var x1344 [1 << 17]byte var x1345 [1 << 17]byte var x1346 [1 << 17]byte var x1347 [1 << 17]byte var x1348 [1 << 17]byte var x1349 [1 << 17]byte var x1350 [1 << 17]byte var x1351 [1 << 17]byte var x1352 [1 << 17]byte var x1353 [1 << 17]byte var x1354 [1 << 17]byte var x1355 [1 << 17]byte var x1356 [1 << 17]byte var x1357 [1 << 17]byte var x1358 [1 << 17]byte var x1359 [1 << 17]byte var x1360 [1 << 17]byte var x1361 [1 << 17]byte var x1362 [1 << 17]byte var x1363 [1 << 17]byte var x1364 [1 << 17]byte var x1365 [1 << 17]byte var x1366 [1 << 17]byte var x1367 [1 << 17]byte var x1368 [1 << 17]byte var x1369 [1 << 17]byte var x1370 [1 << 17]byte var x1371 [1 << 17]byte var x1372 [1 << 17]byte var x1373 [1 << 17]byte var x1374 [1 << 17]byte var x1375 [1 << 17]byte var x1376 [1 << 17]byte var x1377 [1 << 17]byte var x1378 [1 << 17]byte var x1379 [1 << 17]byte var x1380 [1 << 17]byte var x1381 [1 << 17]byte var x1382 [1 << 17]byte var x1383 [1 << 17]byte var x1384 [1 << 17]byte var x1385 [1 << 17]byte var x1386 [1 << 17]byte var x1387 [1 << 17]byte var x1388 [1 << 17]byte var x1389 [1 << 17]byte var x1390 [1 << 17]byte var x1391 [1 << 17]byte var x1392 [1 << 17]byte var x1393 [1 << 17]byte var x1394 [1 << 17]byte var x1395 [1 << 17]byte var x1396 [1 << 17]byte var x1397 [1 << 17]byte var x1398 [1 << 17]byte var x1399 [1 << 17]byte var x1400 [1 << 17]byte var x1401 [1 << 17]byte var x1402 [1 << 17]byte var x1403 [1 << 17]byte var x1404 [1 << 17]byte var x1405 [1 << 17]byte var x1406 [1 << 17]byte var x1407 [1 << 17]byte var x1408 [1 << 17]byte var x1409 [1 << 17]byte var x1410 [1 << 17]byte var x1411 [1 << 17]byte var x1412 [1 << 17]byte var x1413 [1 << 17]byte var x1414 [1 << 17]byte var x1415 [1 << 17]byte var x1416 [1 << 17]byte var x1417 [1 << 17]byte var x1418 [1 << 17]byte var x1419 [1 << 17]byte var x1420 [1 << 17]byte var x1421 [1 << 17]byte var x1422 [1 << 17]byte var x1423 [1 << 17]byte var x1424 [1 << 17]byte var x1425 [1 << 17]byte var x1426 [1 << 17]byte var x1427 [1 << 17]byte var x1428 [1 << 17]byte var x1429 [1 << 17]byte var x1430 [1 << 17]byte var x1431 [1 << 17]byte var x1432 [1 << 17]byte var x1433 [1 << 17]byte var x1434 [1 << 17]byte var x1435 [1 << 17]byte var x1436 [1 << 17]byte var x1437 [1 << 17]byte var x1438 [1 << 17]byte var x1439 [1 << 17]byte var x1440 [1 << 17]byte var x1441 [1 << 17]byte var x1442 [1 << 17]byte var x1443 [1 << 17]byte var x1444 [1 << 17]byte var x1445 [1 << 17]byte var x1446 [1 << 17]byte var x1447 [1 << 17]byte var x1448 [1 << 17]byte var x1449 [1 << 17]byte var x1450 [1 << 17]byte var x1451 [1 << 17]byte var x1452 [1 << 17]byte var x1453 [1 << 17]byte var x1454 [1 << 17]byte var x1455 [1 << 17]byte var x1456 [1 << 17]byte var x1457 [1 << 17]byte var x1458 [1 << 17]byte var x1459 [1 << 17]byte var x1460 [1 << 17]byte var x1461 [1 << 17]byte var x1462 [1 << 17]byte var x1463 [1 << 17]byte var x1464 [1 << 17]byte var x1465 [1 << 17]byte var x1466 [1 << 17]byte var x1467 [1 << 17]byte var x1468 [1 << 17]byte var x1469 [1 << 17]byte var x1470 [1 << 17]byte var x1471 [1 << 17]byte var x1472 [1 << 17]byte var x1473 [1 << 17]byte var x1474 [1 << 17]byte var x1475 [1 << 17]byte var x1476 [1 << 17]byte var x1477 [1 << 17]byte var x1478 [1 << 17]byte var x1479 [1 << 17]byte var x1480 [1 << 17]byte var x1481 [1 << 17]byte var x1482 [1 << 17]byte var x1483 [1 << 17]byte var x1484 [1 << 17]byte var x1485 [1 << 17]byte var x1486 [1 << 17]byte var x1487 [1 << 17]byte var x1488 [1 << 17]byte var x1489 [1 << 17]byte var x1490 [1 << 17]byte var x1491 [1 << 17]byte var x1492 [1 << 17]byte var x1493 [1 << 17]byte var x1494 [1 << 17]byte var x1495 [1 << 17]byte var x1496 [1 << 17]byte var x1497 [1 << 17]byte var x1498 [1 << 17]byte var x1499 [1 << 17]byte var x1500 [1 << 17]byte var x1501 [1 << 17]byte var x1502 [1 << 17]byte var x1503 [1 << 17]byte var x1504 [1 << 17]byte var x1505 [1 << 17]byte var x1506 [1 << 17]byte var x1507 [1 << 17]byte var x1508 [1 << 17]byte var x1509 [1 << 17]byte var x1510 [1 << 17]byte var x1511 [1 << 17]byte var x1512 [1 << 17]byte var x1513 [1 << 17]byte var x1514 [1 << 17]byte var x1515 [1 << 17]byte var x1516 [1 << 17]byte var x1517 [1 << 17]byte var x1518 [1 << 17]byte var x1519 [1 << 17]byte var x1520 [1 << 17]byte var x1521 [1 << 17]byte var x1522 [1 << 17]byte var x1523 [1 << 17]byte var x1524 [1 << 17]byte var x1525 [1 << 17]byte var x1526 [1 << 17]byte var x1527 [1 << 17]byte var x1528 [1 << 17]byte var x1529 [1 << 17]byte var x1530 [1 << 17]byte var x1531 [1 << 17]byte var x1532 [1 << 17]byte var x1533 [1 << 17]byte var x1534 [1 << 17]byte var x1535 [1 << 17]byte var x1536 [1 << 17]byte var x1537 [1 << 17]byte var x1538 [1 << 17]byte var x1539 [1 << 17]byte var x1540 [1 << 17]byte var x1541 [1 << 17]byte var x1542 [1 << 17]byte var x1543 [1 << 17]byte var x1544 [1 << 17]byte var x1545 [1 << 17]byte var x1546 [1 << 17]byte var x1547 [1 << 17]byte var x1548 [1 << 17]byte var x1549 [1 << 17]byte var x1550 [1 << 17]byte var x1551 [1 << 17]byte var x1552 [1 << 17]byte var x1553 [1 << 17]byte var x1554 [1 << 17]byte var x1555 [1 << 17]byte var x1556 [1 << 17]byte var x1557 [1 << 17]byte var x1558 [1 << 17]byte var x1559 [1 << 17]byte var x1560 [1 << 17]byte var x1561 [1 << 17]byte var x1562 [1 << 17]byte var x1563 [1 << 17]byte var x1564 [1 << 17]byte var x1565 [1 << 17]byte var x1566 [1 << 17]byte var x1567 [1 << 17]byte var x1568 [1 << 17]byte var x1569 [1 << 17]byte var x1570 [1 << 17]byte var x1571 [1 << 17]byte var x1572 [1 << 17]byte var x1573 [1 << 17]byte var x1574 [1 << 17]byte var x1575 [1 << 17]byte var x1576 [1 << 17]byte var x1577 [1 << 17]byte var x1578 [1 << 17]byte var x1579 [1 << 17]byte var x1580 [1 << 17]byte var x1581 [1 << 17]byte var x1582 [1 << 17]byte var x1583 [1 << 17]byte var x1584 [1 << 17]byte var x1585 [1 << 17]byte var x1586 [1 << 17]byte var x1587 [1 << 17]byte var x1588 [1 << 17]byte var x1589 [1 << 17]byte var x1590 [1 << 17]byte var x1591 [1 << 17]byte var x1592 [1 << 17]byte var x1593 [1 << 17]byte var x1594 [1 << 17]byte var x1595 [1 << 17]byte var x1596 [1 << 17]byte var x1597 [1 << 17]byte var x1598 [1 << 17]byte var x1599 [1 << 17]byte var x1600 [1 << 17]byte var x1601 [1 << 17]byte var x1602 [1 << 17]byte var x1603 [1 << 17]byte var x1604 [1 << 17]byte var x1605 [1 << 17]byte var x1606 [1 << 17]byte var x1607 [1 << 17]byte var x1608 [1 << 17]byte var x1609 [1 << 17]byte var x1610 [1 << 17]byte var x1611 [1 << 17]byte var x1612 [1 << 17]byte var x1613 [1 << 17]byte var x1614 [1 << 17]byte var x1615 [1 << 17]byte var x1616 [1 << 17]byte var x1617 [1 << 17]byte var x1618 [1 << 17]byte var x1619 [1 << 17]byte var x1620 [1 << 17]byte var x1621 [1 << 17]byte var x1622 [1 << 17]byte var x1623 [1 << 17]byte var x1624 [1 << 17]byte var x1625 [1 << 17]byte var x1626 [1 << 17]byte var x1627 [1 << 17]byte var x1628 [1 << 17]byte var x1629 [1 << 17]byte var x1630 [1 << 17]byte var x1631 [1 << 17]byte var x1632 [1 << 17]byte var x1633 [1 << 17]byte var x1634 [1 << 17]byte var x1635 [1 << 17]byte var x1636 [1 << 17]byte var x1637 [1 << 17]byte var x1638 [1 << 17]byte var x1639 [1 << 17]byte var x1640 [1 << 17]byte var x1641 [1 << 17]byte var x1642 [1 << 17]byte var x1643 [1 << 17]byte var x1644 [1 << 17]byte var x1645 [1 << 17]byte var x1646 [1 << 17]byte var x1647 [1 << 17]byte var x1648 [1 << 17]byte var x1649 [1 << 17]byte var x1650 [1 << 17]byte var x1651 [1 << 17]byte var x1652 [1 << 17]byte var x1653 [1 << 17]byte var x1654 [1 << 17]byte var x1655 [1 << 17]byte var x1656 [1 << 17]byte var x1657 [1 << 17]byte var x1658 [1 << 17]byte var x1659 [1 << 17]byte var x1660 [1 << 17]byte var x1661 [1 << 17]byte var x1662 [1 << 17]byte var x1663 [1 << 17]byte var x1664 [1 << 17]byte var x1665 [1 << 17]byte var x1666 [1 << 17]byte var x1667 [1 << 17]byte var x1668 [1 << 17]byte var x1669 [1 << 17]byte var x1670 [1 << 17]byte var x1671 [1 << 17]byte var x1672 [1 << 17]byte var x1673 [1 << 17]byte var x1674 [1 << 17]byte var x1675 [1 << 17]byte var x1676 [1 << 17]byte var x1677 [1 << 17]byte var x1678 [1 << 17]byte var x1679 [1 << 17]byte var x1680 [1 << 17]byte var x1681 [1 << 17]byte var x1682 [1 << 17]byte var x1683 [1 << 17]byte var x1684 [1 << 17]byte var x1685 [1 << 17]byte var x1686 [1 << 17]byte var x1687 [1 << 17]byte var x1688 [1 << 17]byte var x1689 [1 << 17]byte var x1690 [1 << 17]byte var x1691 [1 << 17]byte var x1692 [1 << 17]byte var x1693 [1 << 17]byte var x1694 [1 << 17]byte var x1695 [1 << 17]byte var x1696 [1 << 17]byte var x1697 [1 << 17]byte var x1698 [1 << 17]byte var x1699 [1 << 17]byte var x1700 [1 << 17]byte var x1701 [1 << 17]byte var x1702 [1 << 17]byte var x1703 [1 << 17]byte var x1704 [1 << 17]byte var x1705 [1 << 17]byte var x1706 [1 << 17]byte var x1707 [1 << 17]byte var x1708 [1 << 17]byte var x1709 [1 << 17]byte var x1710 [1 << 17]byte var x1711 [1 << 17]byte var x1712 [1 << 17]byte var x1713 [1 << 17]byte var x1714 [1 << 17]byte var x1715 [1 << 17]byte var x1716 [1 << 17]byte var x1717 [1 << 17]byte var x1718 [1 << 17]byte var x1719 [1 << 17]byte var x1720 [1 << 17]byte var x1721 [1 << 17]byte var x1722 [1 << 17]byte var x1723 [1 << 17]byte var x1724 [1 << 17]byte var x1725 [1 << 17]byte var x1726 [1 << 17]byte var x1727 [1 << 17]byte var x1728 [1 << 17]byte var x1729 [1 << 17]byte var x1730 [1 << 17]byte var x1731 [1 << 17]byte var x1732 [1 << 17]byte var x1733 [1 << 17]byte var x1734 [1 << 17]byte var x1735 [1 << 17]byte var x1736 [1 << 17]byte var x1737 [1 << 17]byte var x1738 [1 << 17]byte var x1739 [1 << 17]byte var x1740 [1 << 17]byte var x1741 [1 << 17]byte var x1742 [1 << 17]byte var x1743 [1 << 17]byte var x1744 [1 << 17]byte var x1745 [1 << 17]byte var x1746 [1 << 17]byte var x1747 [1 << 17]byte var x1748 [1 << 17]byte var x1749 [1 << 17]byte var x1750 [1 << 17]byte var x1751 [1 << 17]byte var x1752 [1 << 17]byte var x1753 [1 << 17]byte var x1754 [1 << 17]byte var x1755 [1 << 17]byte var x1756 [1 << 17]byte var x1757 [1 << 17]byte var x1758 [1 << 17]byte var x1759 [1 << 17]byte var x1760 [1 << 17]byte var x1761 [1 << 17]byte var x1762 [1 << 17]byte var x1763 [1 << 17]byte var x1764 [1 << 17]byte var x1765 [1 << 17]byte var x1766 [1 << 17]byte var x1767 [1 << 17]byte var x1768 [1 << 17]byte var x1769 [1 << 17]byte var x1770 [1 << 17]byte var x1771 [1 << 17]byte var x1772 [1 << 17]byte var x1773 [1 << 17]byte var x1774 [1 << 17]byte var x1775 [1 << 17]byte var x1776 [1 << 17]byte var x1777 [1 << 17]byte var x1778 [1 << 17]byte var x1779 [1 << 17]byte var x1780 [1 << 17]byte var x1781 [1 << 17]byte var x1782 [1 << 17]byte var x1783 [1 << 17]byte var x1784 [1 << 17]byte var x1785 [1 << 17]byte var x1786 [1 << 17]byte var x1787 [1 << 17]byte var x1788 [1 << 17]byte var x1789 [1 << 17]byte var x1790 [1 << 17]byte var x1791 [1 << 17]byte var x1792 [1 << 17]byte var x1793 [1 << 17]byte var x1794 [1 << 17]byte var x1795 [1 << 17]byte var x1796 [1 << 17]byte var x1797 [1 << 17]byte var x1798 [1 << 17]byte var x1799 [1 << 17]byte var x1800 [1 << 17]byte var x1801 [1 << 17]byte var x1802 [1 << 17]byte var x1803 [1 << 17]byte var x1804 [1 << 17]byte var x1805 [1 << 17]byte var x1806 [1 << 17]byte var x1807 [1 << 17]byte var x1808 [1 << 17]byte var x1809 [1 << 17]byte var x1810 [1 << 17]byte var x1811 [1 << 17]byte var x1812 [1 << 17]byte var x1813 [1 << 17]byte var x1814 [1 << 17]byte var x1815 [1 << 17]byte var x1816 [1 << 17]byte var x1817 [1 << 17]byte var x1818 [1 << 17]byte var x1819 [1 << 17]byte var x1820 [1 << 17]byte var x1821 [1 << 17]byte var x1822 [1 << 17]byte var x1823 [1 << 17]byte var x1824 [1 << 17]byte var x1825 [1 << 17]byte var x1826 [1 << 17]byte var x1827 [1 << 17]byte var x1828 [1 << 17]byte var x1829 [1 << 17]byte var x1830 [1 << 17]byte var x1831 [1 << 17]byte var x1832 [1 << 17]byte var x1833 [1 << 17]byte var x1834 [1 << 17]byte var x1835 [1 << 17]byte var x1836 [1 << 17]byte var x1837 [1 << 17]byte var x1838 [1 << 17]byte var x1839 [1 << 17]byte var x1840 [1 << 17]byte var x1841 [1 << 17]byte var x1842 [1 << 17]byte var x1843 [1 << 17]byte var x1844 [1 << 17]byte var x1845 [1 << 17]byte var x1846 [1 << 17]byte var x1847 [1 << 17]byte var x1848 [1 << 17]byte var x1849 [1 << 17]byte var x1850 [1 << 17]byte var x1851 [1 << 17]byte var x1852 [1 << 17]byte var x1853 [1 << 17]byte var x1854 [1 << 17]byte var x1855 [1 << 17]byte var x1856 [1 << 17]byte var x1857 [1 << 17]byte var x1858 [1 << 17]byte var x1859 [1 << 17]byte var x1860 [1 << 17]byte var x1861 [1 << 17]byte var x1862 [1 << 17]byte var x1863 [1 << 17]byte var x1864 [1 << 17]byte var x1865 [1 << 17]byte var x1866 [1 << 17]byte var x1867 [1 << 17]byte var x1868 [1 << 17]byte var x1869 [1 << 17]byte var x1870 [1 << 17]byte var x1871 [1 << 17]byte var x1872 [1 << 17]byte var x1873 [1 << 17]byte var x1874 [1 << 17]byte var x1875 [1 << 17]byte var x1876 [1 << 17]byte var x1877 [1 << 17]byte var x1878 [1 << 17]byte var x1879 [1 << 17]byte var x1880 [1 << 17]byte var x1881 [1 << 17]byte var x1882 [1 << 17]byte var x1883 [1 << 17]byte var x1884 [1 << 17]byte var x1885 [1 << 17]byte var x1886 [1 << 17]byte var x1887 [1 << 17]byte var x1888 [1 << 17]byte var x1889 [1 << 17]byte var x1890 [1 << 17]byte var x1891 [1 << 17]byte var x1892 [1 << 17]byte var x1893 [1 << 17]byte var x1894 [1 << 17]byte var x1895 [1 << 17]byte var x1896 [1 << 17]byte var x1897 [1 << 17]byte var x1898 [1 << 17]byte var x1899 [1 << 17]byte var x1900 [1 << 17]byte var x1901 [1 << 17]byte var x1902 [1 << 17]byte var x1903 [1 << 17]byte var x1904 [1 << 17]byte var x1905 [1 << 17]byte var x1906 [1 << 17]byte var x1907 [1 << 17]byte var x1908 [1 << 17]byte var x1909 [1 << 17]byte var x1910 [1 << 17]byte var x1911 [1 << 17]byte var x1912 [1 << 17]byte var x1913 [1 << 17]byte var x1914 [1 << 17]byte var x1915 [1 << 17]byte var x1916 [1 << 17]byte var x1917 [1 << 17]byte var x1918 [1 << 17]byte var x1919 [1 << 17]byte var x1920 [1 << 17]byte var x1921 [1 << 17]byte var x1922 [1 << 17]byte var x1923 [1 << 17]byte var x1924 [1 << 17]byte var x1925 [1 << 17]byte var x1926 [1 << 17]byte var x1927 [1 << 17]byte var x1928 [1 << 17]byte var x1929 [1 << 17]byte var x1930 [1 << 17]byte var x1931 [1 << 17]byte var x1932 [1 << 17]byte var x1933 [1 << 17]byte var x1934 [1 << 17]byte var x1935 [1 << 17]byte var x1936 [1 << 17]byte var x1937 [1 << 17]byte var x1938 [1 << 17]byte var x1939 [1 << 17]byte var x1940 [1 << 17]byte var x1941 [1 << 17]byte var x1942 [1 << 17]byte var x1943 [1 << 17]byte var x1944 [1 << 17]byte var x1945 [1 << 17]byte var x1946 [1 << 17]byte var x1947 [1 << 17]byte var x1948 [1 << 17]byte var x1949 [1 << 17]byte var x1950 [1 << 17]byte var x1951 [1 << 17]byte var x1952 [1 << 17]byte var x1953 [1 << 17]byte var x1954 [1 << 17]byte var x1955 [1 << 17]byte var x1956 [1 << 17]byte var x1957 [1 << 17]byte var x1958 [1 << 17]byte var x1959 [1 << 17]byte var x1960 [1 << 17]byte var x1961 [1 << 17]byte var x1962 [1 << 17]byte var x1963 [1 << 17]byte var x1964 [1 << 17]byte var x1965 [1 << 17]byte var x1966 [1 << 17]byte var x1967 [1 << 17]byte var x1968 [1 << 17]byte var x1969 [1 << 17]byte var x1970 [1 << 17]byte var x1971 [1 << 17]byte var x1972 [1 << 17]byte var x1973 [1 << 17]byte var x1974 [1 << 17]byte var x1975 [1 << 17]byte var x1976 [1 << 17]byte var x1977 [1 << 17]byte var x1978 [1 << 17]byte var x1979 [1 << 17]byte var x1980 [1 << 17]byte var x1981 [1 << 17]byte var x1982 [1 << 17]byte var x1983 [1 << 17]byte var x1984 [1 << 17]byte var x1985 [1 << 17]byte var x1986 [1 << 17]byte var x1987 [1 << 17]byte var x1988 [1 << 17]byte var x1989 [1 << 17]byte var x1990 [1 << 17]byte var x1991 [1 << 17]byte var x1992 [1 << 17]byte var x1993 [1 << 17]byte var x1994 [1 << 17]byte var x1995 [1 << 17]byte var x1996 [1 << 17]byte var x1997 [1 << 17]byte var x1998 [1 << 17]byte var x1999 [1 << 17]byte var x2000 [1 << 17]byte var x2001 [1 << 17]byte var x2002 [1 << 17]byte var x2003 [1 << 17]byte var x2004 [1 << 17]byte var x2005 [1 << 17]byte var x2006 [1 << 17]byte var x2007 [1 << 17]byte var x2008 [1 << 17]byte var x2009 [1 << 17]byte var x2010 [1 << 17]byte var x2011 [1 << 17]byte var x2012 [1 << 17]byte var x2013 [1 << 17]byte var x2014 [1 << 17]byte var x2015 [1 << 17]byte var x2016 [1 << 17]byte var x2017 [1 << 17]byte var x2018 [1 << 17]byte var x2019 [1 << 17]byte var x2020 [1 << 17]byte var x2021 [1 << 17]byte var x2022 [1 << 17]byte var x2023 [1 << 17]byte var x2024 [1 << 17]byte var x2025 [1 << 17]byte var x2026 [1 << 17]byte var x2027 [1 << 17]byte var x2028 [1 << 17]byte var x2029 [1 << 17]byte var x2030 [1 << 17]byte var x2031 [1 << 17]byte var x2032 [1 << 17]byte var x2033 [1 << 17]byte var x2034 [1 << 17]byte var x2035 [1 << 17]byte var x2036 [1 << 17]byte var x2037 [1 << 17]byte var x2038 [1 << 17]byte var x2039 [1 << 17]byte var x2040 [1 << 17]byte var x2041 [1 << 17]byte var x2042 [1 << 17]byte var x2043 [1 << 17]byte var x2044 [1 << 17]byte var x2045 [1 << 17]byte var x2046 [1 << 17]byte var x2047 [1 << 17]byte var x2048 [1 << 17]byte var x2049 [1 << 17]byte var x2050 [1 << 17]byte var x2051 [1 << 17]byte var x2052 [1 << 17]byte var x2053 [1 << 17]byte var x2054 [1 << 17]byte var x2055 [1 << 17]byte var x2056 [1 << 17]byte var x2057 [1 << 17]byte var x2058 [1 << 17]byte var x2059 [1 << 17]byte var x2060 [1 << 17]byte var x2061 [1 << 17]byte var x2062 [1 << 17]byte var x2063 [1 << 17]byte var x2064 [1 << 17]byte var x2065 [1 << 17]byte var x2066 [1 << 17]byte var x2067 [1 << 17]byte var x2068 [1 << 17]byte var x2069 [1 << 17]byte var x2070 [1 << 17]byte var x2071 [1 << 17]byte var x2072 [1 << 17]byte var x2073 [1 << 17]byte var x2074 [1 << 17]byte var x2075 [1 << 17]byte var x2076 [1 << 17]byte var x2077 [1 << 17]byte var x2078 [1 << 17]byte var x2079 [1 << 17]byte var x2080 [1 << 17]byte var x2081 [1 << 17]byte var x2082 [1 << 17]byte var x2083 [1 << 17]byte var x2084 [1 << 17]byte var x2085 [1 << 17]byte var x2086 [1 << 17]byte var x2087 [1 << 17]byte var x2088 [1 << 17]byte var x2089 [1 << 17]byte var x2090 [1 << 17]byte var x2091 [1 << 17]byte var x2092 [1 << 17]byte var x2093 [1 << 17]byte var x2094 [1 << 17]byte var x2095 [1 << 17]byte var x2096 [1 << 17]byte var x2097 [1 << 17]byte var x2098 [1 << 17]byte var x2099 [1 << 17]byte var x2100 [1 << 17]byte var x2101 [1 << 17]byte var x2102 [1 << 17]byte var x2103 [1 << 17]byte var x2104 [1 << 17]byte var x2105 [1 << 17]byte var x2106 [1 << 17]byte var x2107 [1 << 17]byte var x2108 [1 << 17]byte var x2109 [1 << 17]byte var x2110 [1 << 17]byte var x2111 [1 << 17]byte var x2112 [1 << 17]byte var x2113 [1 << 17]byte var x2114 [1 << 17]byte var x2115 [1 << 17]byte var x2116 [1 << 17]byte var x2117 [1 << 17]byte var x2118 [1 << 17]byte var x2119 [1 << 17]byte var x2120 [1 << 17]byte var x2121 [1 << 17]byte var x2122 [1 << 17]byte var x2123 [1 << 17]byte var x2124 [1 << 17]byte var x2125 [1 << 17]byte var x2126 [1 << 17]byte var x2127 [1 << 17]byte var x2128 [1 << 17]byte var x2129 [1 << 17]byte var x2130 [1 << 17]byte var x2131 [1 << 17]byte var x2132 [1 << 17]byte var x2133 [1 << 17]byte var x2134 [1 << 17]byte var x2135 [1 << 17]byte var x2136 [1 << 17]byte var x2137 [1 << 17]byte var x2138 [1 << 17]byte var x2139 [1 << 17]byte var x2140 [1 << 17]byte var x2141 [1 << 17]byte var x2142 [1 << 17]byte var x2143 [1 << 17]byte var x2144 [1 << 17]byte var x2145 [1 << 17]byte var x2146 [1 << 17]byte var x2147 [1 << 17]byte var x2148 [1 << 17]byte var x2149 [1 << 17]byte var x2150 [1 << 17]byte var x2151 [1 << 17]byte var x2152 [1 << 17]byte var x2153 [1 << 17]byte var x2154 [1 << 17]byte var x2155 [1 << 17]byte var x2156 [1 << 17]byte var x2157 [1 << 17]byte var x2158 [1 << 17]byte var x2159 [1 << 17]byte var x2160 [1 << 17]byte var x2161 [1 << 17]byte var x2162 [1 << 17]byte var x2163 [1 << 17]byte var x2164 [1 << 17]byte var x2165 [1 << 17]byte var x2166 [1 << 17]byte var x2167 [1 << 17]byte var x2168 [1 << 17]byte var x2169 [1 << 17]byte var x2170 [1 << 17]byte var x2171 [1 << 17]byte var x2172 [1 << 17]byte var x2173 [1 << 17]byte var x2174 [1 << 17]byte var x2175 [1 << 17]byte var x2176 [1 << 17]byte var x2177 [1 << 17]byte var x2178 [1 << 17]byte var x2179 [1 << 17]byte var x2180 [1 << 17]byte var x2181 [1 << 17]byte var x2182 [1 << 17]byte var x2183 [1 << 17]byte var x2184 [1 << 17]byte var x2185 [1 << 17]byte var x2186 [1 << 17]byte var x2187 [1 << 17]byte var x2188 [1 << 17]byte var x2189 [1 << 17]byte var x2190 [1 << 17]byte var x2191 [1 << 17]byte var x2192 [1 << 17]byte var x2193 [1 << 17]byte var x2194 [1 << 17]byte var x2195 [1 << 17]byte var x2196 [1 << 17]byte var x2197 [1 << 17]byte var x2198 [1 << 17]byte var x2199 [1 << 17]byte var x2200 [1 << 17]byte var x2201 [1 << 17]byte var x2202 [1 << 17]byte var x2203 [1 << 17]byte var x2204 [1 << 17]byte var x2205 [1 << 17]byte var x2206 [1 << 17]byte var x2207 [1 << 17]byte var x2208 [1 << 17]byte var x2209 [1 << 17]byte var x2210 [1 << 17]byte var x2211 [1 << 17]byte var x2212 [1 << 17]byte var x2213 [1 << 17]byte var x2214 [1 << 17]byte var x2215 [1 << 17]byte var x2216 [1 << 17]byte var x2217 [1 << 17]byte var x2218 [1 << 17]byte var x2219 [1 << 17]byte var x2220 [1 << 17]byte var x2221 [1 << 17]byte var x2222 [1 << 17]byte var x2223 [1 << 17]byte var x2224 [1 << 17]byte var x2225 [1 << 17]byte var x2226 [1 << 17]byte var x2227 [1 << 17]byte var x2228 [1 << 17]byte var x2229 [1 << 17]byte var x2230 [1 << 17]byte var x2231 [1 << 17]byte var x2232 [1 << 17]byte var x2233 [1 << 17]byte var x2234 [1 << 17]byte var x2235 [1 << 17]byte var x2236 [1 << 17]byte var x2237 [1 << 17]byte var x2238 [1 << 17]byte var x2239 [1 << 17]byte var x2240 [1 << 17]byte var x2241 [1 << 17]byte var x2242 [1 << 17]byte var x2243 [1 << 17]byte var x2244 [1 << 17]byte var x2245 [1 << 17]byte var x2246 [1 << 17]byte var x2247 [1 << 17]byte var x2248 [1 << 17]byte var x2249 [1 << 17]byte var x2250 [1 << 17]byte var x2251 [1 << 17]byte var x2252 [1 << 17]byte var x2253 [1 << 17]byte var x2254 [1 << 17]byte var x2255 [1 << 17]byte var x2256 [1 << 17]byte var x2257 [1 << 17]byte var x2258 [1 << 17]byte var x2259 [1 << 17]byte var x2260 [1 << 17]byte var x2261 [1 << 17]byte var x2262 [1 << 17]byte var x2263 [1 << 17]byte var x2264 [1 << 17]byte var x2265 [1 << 17]byte var x2266 [1 << 17]byte var x2267 [1 << 17]byte var x2268 [1 << 17]byte var x2269 [1 << 17]byte var x2270 [1 << 17]byte var x2271 [1 << 17]byte var x2272 [1 << 17]byte var x2273 [1 << 17]byte var x2274 [1 << 17]byte var x2275 [1 << 17]byte var x2276 [1 << 17]byte var x2277 [1 << 17]byte var x2278 [1 << 17]byte var x2279 [1 << 17]byte var x2280 [1 << 17]byte var x2281 [1 << 17]byte var x2282 [1 << 17]byte var x2283 [1 << 17]byte var x2284 [1 << 17]byte var x2285 [1 << 17]byte var x2286 [1 << 17]byte var x2287 [1 << 17]byte var x2288 [1 << 17]byte var x2289 [1 << 17]byte var x2290 [1 << 17]byte var x2291 [1 << 17]byte var x2292 [1 << 17]byte var x2293 [1 << 17]byte var x2294 [1 << 17]byte var x2295 [1 << 17]byte var x2296 [1 << 17]byte var x2297 [1 << 17]byte var x2298 [1 << 17]byte var x2299 [1 << 17]byte var x2300 [1 << 17]byte var x2301 [1 << 17]byte var x2302 [1 << 17]byte var x2303 [1 << 17]byte var x2304 [1 << 17]byte var x2305 [1 << 17]byte var x2306 [1 << 17]byte var x2307 [1 << 17]byte var x2308 [1 << 17]byte var x2309 [1 << 17]byte var x2310 [1 << 17]byte var x2311 [1 << 17]byte var x2312 [1 << 17]byte var x2313 [1 << 17]byte var x2314 [1 << 17]byte var x2315 [1 << 17]byte var x2316 [1 << 17]byte var x2317 [1 << 17]byte var x2318 [1 << 17]byte var x2319 [1 << 17]byte var x2320 [1 << 17]byte var x2321 [1 << 17]byte var x2322 [1 << 17]byte var x2323 [1 << 17]byte var x2324 [1 << 17]byte var x2325 [1 << 17]byte var x2326 [1 << 17]byte var x2327 [1 << 17]byte var x2328 [1 << 17]byte var x2329 [1 << 17]byte var x2330 [1 << 17]byte var x2331 [1 << 17]byte var x2332 [1 << 17]byte var x2333 [1 << 17]byte var x2334 [1 << 17]byte var x2335 [1 << 17]byte var x2336 [1 << 17]byte var x2337 [1 << 17]byte var x2338 [1 << 17]byte var x2339 [1 << 17]byte var x2340 [1 << 17]byte var x2341 [1 << 17]byte var x2342 [1 << 17]byte var x2343 [1 << 17]byte var x2344 [1 << 17]byte var x2345 [1 << 17]byte var x2346 [1 << 17]byte var x2347 [1 << 17]byte var x2348 [1 << 17]byte var x2349 [1 << 17]byte var x2350 [1 << 17]byte var x2351 [1 << 17]byte var x2352 [1 << 17]byte var x2353 [1 << 17]byte var x2354 [1 << 17]byte var x2355 [1 << 17]byte var x2356 [1 << 17]byte var x2357 [1 << 17]byte var x2358 [1 << 17]byte var x2359 [1 << 17]byte var x2360 [1 << 17]byte var x2361 [1 << 17]byte var x2362 [1 << 17]byte var x2363 [1 << 17]byte var x2364 [1 << 17]byte var x2365 [1 << 17]byte var x2366 [1 << 17]byte var x2367 [1 << 17]byte var x2368 [1 << 17]byte var x2369 [1 << 17]byte var x2370 [1 << 17]byte var x2371 [1 << 17]byte var x2372 [1 << 17]byte var x2373 [1 << 17]byte var x2374 [1 << 17]byte var x2375 [1 << 17]byte var x2376 [1 << 17]byte var x2377 [1 << 17]byte var x2378 [1 << 17]byte var x2379 [1 << 17]byte var x2380 [1 << 17]byte var x2381 [1 << 17]byte var x2382 [1 << 17]byte var x2383 [1 << 17]byte var x2384 [1 << 17]byte var x2385 [1 << 17]byte var x2386 [1 << 17]byte var x2387 [1 << 17]byte var x2388 [1 << 17]byte var x2389 [1 << 17]byte var x2390 [1 << 17]byte var x2391 [1 << 17]byte var x2392 [1 << 17]byte var x2393 [1 << 17]byte var x2394 [1 << 17]byte var x2395 [1 << 17]byte var x2396 [1 << 17]byte var x2397 [1 << 17]byte var x2398 [1 << 17]byte var x2399 [1 << 17]byte var x2400 [1 << 17]byte var x2401 [1 << 17]byte var x2402 [1 << 17]byte var x2403 [1 << 17]byte var x2404 [1 << 17]byte var x2405 [1 << 17]byte var x2406 [1 << 17]byte var x2407 [1 << 17]byte var x2408 [1 << 17]byte var x2409 [1 << 17]byte var x2410 [1 << 17]byte var x2411 [1 << 17]byte var x2412 [1 << 17]byte var x2413 [1 << 17]byte var x2414 [1 << 17]byte var x2415 [1 << 17]byte var x2416 [1 << 17]byte var x2417 [1 << 17]byte var x2418 [1 << 17]byte var x2419 [1 << 17]byte var x2420 [1 << 17]byte var x2421 [1 << 17]byte var x2422 [1 << 17]byte var x2423 [1 << 17]byte var x2424 [1 << 17]byte var x2425 [1 << 17]byte var x2426 [1 << 17]byte var x2427 [1 << 17]byte var x2428 [1 << 17]byte var x2429 [1 << 17]byte var x2430 [1 << 17]byte var x2431 [1 << 17]byte var x2432 [1 << 17]byte var x2433 [1 << 17]byte var x2434 [1 << 17]byte var x2435 [1 << 17]byte var x2436 [1 << 17]byte var x2437 [1 << 17]byte var x2438 [1 << 17]byte var x2439 [1 << 17]byte var x2440 [1 << 17]byte var x2441 [1 << 17]byte var x2442 [1 << 17]byte var x2443 [1 << 17]byte var x2444 [1 << 17]byte var x2445 [1 << 17]byte var x2446 [1 << 17]byte var x2447 [1 << 17]byte var x2448 [1 << 17]byte var x2449 [1 << 17]byte var x2450 [1 << 17]byte var x2451 [1 << 17]byte var x2452 [1 << 17]byte var x2453 [1 << 17]byte var x2454 [1 << 17]byte var x2455 [1 << 17]byte var x2456 [1 << 17]byte var x2457 [1 << 17]byte var x2458 [1 << 17]byte var x2459 [1 << 17]byte var x2460 [1 << 17]byte var x2461 [1 << 17]byte var x2462 [1 << 17]byte var x2463 [1 << 17]byte var x2464 [1 << 17]byte var x2465 [1 << 17]byte var x2466 [1 << 17]byte var x2467 [1 << 17]byte var x2468 [1 << 17]byte var x2469 [1 << 17]byte var x2470 [1 << 17]byte var x2471 [1 << 17]byte var x2472 [1 << 17]byte var x2473 [1 << 17]byte var x2474 [1 << 17]byte var x2475 [1 << 17]byte var x2476 [1 << 17]byte var x2477 [1 << 17]byte var x2478 [1 << 17]byte var x2479 [1 << 17]byte var x2480 [1 << 17]byte var x2481 [1 << 17]byte var x2482 [1 << 17]byte var x2483 [1 << 17]byte var x2484 [1 << 17]byte var x2485 [1 << 17]byte var x2486 [1 << 17]byte var x2487 [1 << 17]byte var x2488 [1 << 17]byte var x2489 [1 << 17]byte var x2490 [1 << 17]byte var x2491 [1 << 17]byte var x2492 [1 << 17]byte var x2493 [1 << 17]byte var x2494 [1 << 17]byte var x2495 [1 << 17]byte var x2496 [1 << 17]byte var x2497 [1 << 17]byte var x2498 [1 << 17]byte var x2499 [1 << 17]byte var x2500 [1 << 17]byte var x2501 [1 << 17]byte var x2502 [1 << 17]byte var x2503 [1 << 17]byte var x2504 [1 << 17]byte var x2505 [1 << 17]byte var x2506 [1 << 17]byte var x2507 [1 << 17]byte var x2508 [1 << 17]byte var x2509 [1 << 17]byte var x2510 [1 << 17]byte var x2511 [1 << 17]byte var x2512 [1 << 17]byte var x2513 [1 << 17]byte var x2514 [1 << 17]byte var x2515 [1 << 17]byte var x2516 [1 << 17]byte var x2517 [1 << 17]byte var x2518 [1 << 17]byte var x2519 [1 << 17]byte var x2520 [1 << 17]byte var x2521 [1 << 17]byte var x2522 [1 << 17]byte var x2523 [1 << 17]byte var x2524 [1 << 17]byte var x2525 [1 << 17]byte var x2526 [1 << 17]byte var x2527 [1 << 17]byte var x2528 [1 << 17]byte var x2529 [1 << 17]byte var x2530 [1 << 17]byte var x2531 [1 << 17]byte var x2532 [1 << 17]byte var x2533 [1 << 17]byte var x2534 [1 << 17]byte var x2535 [1 << 17]byte var x2536 [1 << 17]byte var x2537 [1 << 17]byte var x2538 [1 << 17]byte var x2539 [1 << 17]byte var x2540 [1 << 17]byte var x2541 [1 << 17]byte var x2542 [1 << 17]byte var x2543 [1 << 17]byte var x2544 [1 << 17]byte var x2545 [1 << 17]byte var x2546 [1 << 17]byte var x2547 [1 << 17]byte var x2548 [1 << 17]byte var x2549 [1 << 17]byte var x2550 [1 << 17]byte var x2551 [1 << 17]byte var x2552 [1 << 17]byte var x2553 [1 << 17]byte var x2554 [1 << 17]byte var x2555 [1 << 17]byte var x2556 [1 << 17]byte var x2557 [1 << 17]byte var x2558 [1 << 17]byte var x2559 [1 << 17]byte var x2560 [1 << 17]byte var x2561 [1 << 17]byte var x2562 [1 << 17]byte var x2563 [1 << 17]byte var x2564 [1 << 17]byte var x2565 [1 << 17]byte var x2566 [1 << 17]byte var x2567 [1 << 17]byte var x2568 [1 << 17]byte var x2569 [1 << 17]byte var x2570 [1 << 17]byte var x2571 [1 << 17]byte var x2572 [1 << 17]byte var x2573 [1 << 17]byte var x2574 [1 << 17]byte var x2575 [1 << 17]byte var x2576 [1 << 17]byte var x2577 [1 << 17]byte var x2578 [1 << 17]byte var x2579 [1 << 17]byte var x2580 [1 << 17]byte var x2581 [1 << 17]byte var x2582 [1 << 17]byte var x2583 [1 << 17]byte var x2584 [1 << 17]byte var x2585 [1 << 17]byte var x2586 [1 << 17]byte var x2587 [1 << 17]byte var x2588 [1 << 17]byte var x2589 [1 << 17]byte var x2590 [1 << 17]byte var x2591 [1 << 17]byte var x2592 [1 << 17]byte var x2593 [1 << 17]byte var x2594 [1 << 17]byte var x2595 [1 << 17]byte var x2596 [1 << 17]byte var x2597 [1 << 17]byte var x2598 [1 << 17]byte var x2599 [1 << 17]byte var x2600 [1 << 17]byte var x2601 [1 << 17]byte var x2602 [1 << 17]byte var x2603 [1 << 17]byte var x2604 [1 << 17]byte var x2605 [1 << 17]byte var x2606 [1 << 17]byte var x2607 [1 << 17]byte var x2608 [1 << 17]byte var x2609 [1 << 17]byte var x2610 [1 << 17]byte var x2611 [1 << 17]byte var x2612 [1 << 17]byte var x2613 [1 << 17]byte var x2614 [1 << 17]byte var x2615 [1 << 17]byte var x2616 [1 << 17]byte var x2617 [1 << 17]byte var x2618 [1 << 17]byte var x2619 [1 << 17]byte var x2620 [1 << 17]byte var x2621 [1 << 17]byte var x2622 [1 << 17]byte var x2623 [1 << 17]byte var x2624 [1 << 17]byte var x2625 [1 << 17]byte var x2626 [1 << 17]byte var x2627 [1 << 17]byte var x2628 [1 << 17]byte var x2629 [1 << 17]byte var x2630 [1 << 17]byte var x2631 [1 << 17]byte var x2632 [1 << 17]byte var x2633 [1 << 17]byte var x2634 [1 << 17]byte var x2635 [1 << 17]byte var x2636 [1 << 17]byte var x2637 [1 << 17]byte var x2638 [1 << 17]byte var x2639 [1 << 17]byte var x2640 [1 << 17]byte var x2641 [1 << 17]byte var x2642 [1 << 17]byte var x2643 [1 << 17]byte var x2644 [1 << 17]byte var x2645 [1 << 17]byte var x2646 [1 << 17]byte var x2647 [1 << 17]byte var x2648 [1 << 17]byte var x2649 [1 << 17]byte var x2650 [1 << 17]byte var x2651 [1 << 17]byte var x2652 [1 << 17]byte var x2653 [1 << 17]byte var x2654 [1 << 17]byte var x2655 [1 << 17]byte var x2656 [1 << 17]byte var x2657 [1 << 17]byte var x2658 [1 << 17]byte var x2659 [1 << 17]byte var x2660 [1 << 17]byte var x2661 [1 << 17]byte var x2662 [1 << 17]byte var x2663 [1 << 17]byte var x2664 [1 << 17]byte var x2665 [1 << 17]byte var x2666 [1 << 17]byte var x2667 [1 << 17]byte var x2668 [1 << 17]byte var x2669 [1 << 17]byte var x2670 [1 << 17]byte var x2671 [1 << 17]byte var x2672 [1 << 17]byte var x2673 [1 << 17]byte var x2674 [1 << 17]byte var x2675 [1 << 17]byte var x2676 [1 << 17]byte var x2677 [1 << 17]byte var x2678 [1 << 17]byte var x2679 [1 << 17]byte var x2680 [1 << 17]byte var x2681 [1 << 17]byte var x2682 [1 << 17]byte var x2683 [1 << 17]byte var x2684 [1 << 17]byte var x2685 [1 << 17]byte var x2686 [1 << 17]byte var x2687 [1 << 17]byte var x2688 [1 << 17]byte var x2689 [1 << 17]byte var x2690 [1 << 17]byte var x2691 [1 << 17]byte var x2692 [1 << 17]byte var x2693 [1 << 17]byte var x2694 [1 << 17]byte var x2695 [1 << 17]byte var x2696 [1 << 17]byte var x2697 [1 << 17]byte var x2698 [1 << 17]byte var x2699 [1 << 17]byte var x2700 [1 << 17]byte var x2701 [1 << 17]byte var x2702 [1 << 17]byte var x2703 [1 << 17]byte var x2704 [1 << 17]byte var x2705 [1 << 17]byte var x2706 [1 << 17]byte var x2707 [1 << 17]byte var x2708 [1 << 17]byte var x2709 [1 << 17]byte var x2710 [1 << 17]byte var x2711 [1 << 17]byte var x2712 [1 << 17]byte var x2713 [1 << 17]byte var x2714 [1 << 17]byte var x2715 [1 << 17]byte var x2716 [1 << 17]byte var x2717 [1 << 17]byte var x2718 [1 << 17]byte var x2719 [1 << 17]byte var x2720 [1 << 17]byte var x2721 [1 << 17]byte var x2722 [1 << 17]byte var x2723 [1 << 17]byte var x2724 [1 << 17]byte var x2725 [1 << 17]byte var x2726 [1 << 17]byte var x2727 [1 << 17]byte var x2728 [1 << 17]byte var x2729 [1 << 17]byte var x2730 [1 << 17]byte var x2731 [1 << 17]byte var x2732 [1 << 17]byte var x2733 [1 << 17]byte var x2734 [1 << 17]byte var x2735 [1 << 17]byte var x2736 [1 << 17]byte var x2737 [1 << 17]byte var x2738 [1 << 17]byte var x2739 [1 << 17]byte var x2740 [1 << 17]byte var x2741 [1 << 17]byte var x2742 [1 << 17]byte var x2743 [1 << 17]byte var x2744 [1 << 17]byte var x2745 [1 << 17]byte var x2746 [1 << 17]byte var x2747 [1 << 17]byte var x2748 [1 << 17]byte var x2749 [1 << 17]byte var x2750 [1 << 17]byte var x2751 [1 << 17]byte var x2752 [1 << 17]byte var x2753 [1 << 17]byte var x2754 [1 << 17]byte var x2755 [1 << 17]byte var x2756 [1 << 17]byte var x2757 [1 << 17]byte var x2758 [1 << 17]byte var x2759 [1 << 17]byte var x2760 [1 << 17]byte var x2761 [1 << 17]byte var x2762 [1 << 17]byte var x2763 [1 << 17]byte var x2764 [1 << 17]byte var x2765 [1 << 17]byte var x2766 [1 << 17]byte var x2767 [1 << 17]byte var x2768 [1 << 17]byte var x2769 [1 << 17]byte var x2770 [1 << 17]byte var x2771 [1 << 17]byte var x2772 [1 << 17]byte var x2773 [1 << 17]byte var x2774 [1 << 17]byte var x2775 [1 << 17]byte var x2776 [1 << 17]byte var x2777 [1 << 17]byte var x2778 [1 << 17]byte var x2779 [1 << 17]byte var x2780 [1 << 17]byte var x2781 [1 << 17]byte var x2782 [1 << 17]byte var x2783 [1 << 17]byte var x2784 [1 << 17]byte var x2785 [1 << 17]byte var x2786 [1 << 17]byte var x2787 [1 << 17]byte var x2788 [1 << 17]byte var x2789 [1 << 17]byte var x2790 [1 << 17]byte var x2791 [1 << 17]byte var x2792 [1 << 17]byte var x2793 [1 << 17]byte var x2794 [1 << 17]byte var x2795 [1 << 17]byte var x2796 [1 << 17]byte var x2797 [1 << 17]byte var x2798 [1 << 17]byte var x2799 [1 << 17]byte var x2800 [1 << 17]byte var x2801 [1 << 17]byte var x2802 [1 << 17]byte var x2803 [1 << 17]byte var x2804 [1 << 17]byte var x2805 [1 << 17]byte var x2806 [1 << 17]byte var x2807 [1 << 17]byte var x2808 [1 << 17]byte var x2809 [1 << 17]byte var x2810 [1 << 17]byte var x2811 [1 << 17]byte var x2812 [1 << 17]byte var x2813 [1 << 17]byte var x2814 [1 << 17]byte var x2815 [1 << 17]byte var x2816 [1 << 17]byte var x2817 [1 << 17]byte var x2818 [1 << 17]byte var x2819 [1 << 17]byte var x2820 [1 << 17]byte var x2821 [1 << 17]byte var x2822 [1 << 17]byte var x2823 [1 << 17]byte var x2824 [1 << 17]byte var x2825 [1 << 17]byte var x2826 [1 << 17]byte var x2827 [1 << 17]byte var x2828 [1 << 17]byte var x2829 [1 << 17]byte var x2830 [1 << 17]byte var x2831 [1 << 17]byte var x2832 [1 << 17]byte var x2833 [1 << 17]byte var x2834 [1 << 17]byte var x2835 [1 << 17]byte var x2836 [1 << 17]byte var x2837 [1 << 17]byte var x2838 [1 << 17]byte var x2839 [1 << 17]byte var x2840 [1 << 17]byte var x2841 [1 << 17]byte var x2842 [1 << 17]byte var x2843 [1 << 17]byte var x2844 [1 << 17]byte var x2845 [1 << 17]byte var x2846 [1 << 17]byte var x2847 [1 << 17]byte var x2848 [1 << 17]byte var x2849 [1 << 17]byte var x2850 [1 << 17]byte var x2851 [1 << 17]byte var x2852 [1 << 17]byte var x2853 [1 << 17]byte var x2854 [1 << 17]byte var x2855 [1 << 17]byte var x2856 [1 << 17]byte var x2857 [1 << 17]byte var x2858 [1 << 17]byte var x2859 [1 << 17]byte var x2860 [1 << 17]byte var x2861 [1 << 17]byte var x2862 [1 << 17]byte var x2863 [1 << 17]byte var x2864 [1 << 17]byte var x2865 [1 << 17]byte var x2866 [1 << 17]byte var x2867 [1 << 17]byte var x2868 [1 << 17]byte var x2869 [1 << 17]byte var x2870 [1 << 17]byte var x2871 [1 << 17]byte var x2872 [1 << 17]byte var x2873 [1 << 17]byte var x2874 [1 << 17]byte var x2875 [1 << 17]byte var x2876 [1 << 17]byte var x2877 [1 << 17]byte var x2878 [1 << 17]byte var x2879 [1 << 17]byte var x2880 [1 << 17]byte var x2881 [1 << 17]byte var x2882 [1 << 17]byte var x2883 [1 << 17]byte var x2884 [1 << 17]byte var x2885 [1 << 17]byte var x2886 [1 << 17]byte var x2887 [1 << 17]byte var x2888 [1 << 17]byte var x2889 [1 << 17]byte var x2890 [1 << 17]byte var x2891 [1 << 17]byte var x2892 [1 << 17]byte var x2893 [1 << 17]byte var x2894 [1 << 17]byte var x2895 [1 << 17]byte var x2896 [1 << 17]byte var x2897 [1 << 17]byte var x2898 [1 << 17]byte var x2899 [1 << 17]byte var x2900 [1 << 17]byte var x2901 [1 << 17]byte var x2902 [1 << 17]byte var x2903 [1 << 17]byte var x2904 [1 << 17]byte var x2905 [1 << 17]byte var x2906 [1 << 17]byte var x2907 [1 << 17]byte var x2908 [1 << 17]byte var x2909 [1 << 17]byte var x2910 [1 << 17]byte var x2911 [1 << 17]byte var x2912 [1 << 17]byte var x2913 [1 << 17]byte var x2914 [1 << 17]byte var x2915 [1 << 17]byte var x2916 [1 << 17]byte var x2917 [1 << 17]byte var x2918 [1 << 17]byte var x2919 [1 << 17]byte var x2920 [1 << 17]byte var x2921 [1 << 17]byte var x2922 [1 << 17]byte var x2923 [1 << 17]byte var x2924 [1 << 17]byte var x2925 [1 << 17]byte var x2926 [1 << 17]byte var x2927 [1 << 17]byte var x2928 [1 << 17]byte var x2929 [1 << 17]byte var x2930 [1 << 17]byte var x2931 [1 << 17]byte var x2932 [1 << 17]byte var x2933 [1 << 17]byte var x2934 [1 << 17]byte var x2935 [1 << 17]byte var x2936 [1 << 17]byte var x2937 [1 << 17]byte var x2938 [1 << 17]byte var x2939 [1 << 17]byte var x2940 [1 << 17]byte var x2941 [1 << 17]byte var x2942 [1 << 17]byte var x2943 [1 << 17]byte var x2944 [1 << 17]byte var x2945 [1 << 17]byte var x2946 [1 << 17]byte var x2947 [1 << 17]byte var x2948 [1 << 17]byte var x2949 [1 << 17]byte var x2950 [1 << 17]byte var x2951 [1 << 17]byte var x2952 [1 << 17]byte var x2953 [1 << 17]byte var x2954 [1 << 17]byte var x2955 [1 << 17]byte var x2956 [1 << 17]byte var x2957 [1 << 17]byte var x2958 [1 << 17]byte var x2959 [1 << 17]byte var x2960 [1 << 17]byte var x2961 [1 << 17]byte var x2962 [1 << 17]byte var x2963 [1 << 17]byte var x2964 [1 << 17]byte var x2965 [1 << 17]byte var x2966 [1 << 17]byte var x2967 [1 << 17]byte var x2968 [1 << 17]byte var x2969 [1 << 17]byte var x2970 [1 << 17]byte var x2971 [1 << 17]byte var x2972 [1 << 17]byte var x2973 [1 << 17]byte var x2974 [1 << 17]byte var x2975 [1 << 17]byte var x2976 [1 << 17]byte var x2977 [1 << 17]byte var x2978 [1 << 17]byte var x2979 [1 << 17]byte var x2980 [1 << 17]byte var x2981 [1 << 17]byte var x2982 [1 << 17]byte var x2983 [1 << 17]byte var x2984 [1 << 17]byte var x2985 [1 << 17]byte var x2986 [1 << 17]byte var x2987 [1 << 17]byte var x2988 [1 << 17]byte var x2989 [1 << 17]byte var x2990 [1 << 17]byte var x2991 [1 << 17]byte var x2992 [1 << 17]byte var x2993 [1 << 17]byte var x2994 [1 << 17]byte var x2995 [1 << 17]byte var x2996 [1 << 17]byte var x2997 [1 << 17]byte var x2998 [1 << 17]byte var x2999 [1 << 17]byte var x3000 [1 << 17]byte var x3001 [1 << 17]byte var x3002 [1 << 17]byte var x3003 [1 << 17]byte var x3004 [1 << 17]byte var x3005 [1 << 17]byte var x3006 [1 << 17]byte var x3007 [1 << 17]byte var x3008 [1 << 17]byte var x3009 [1 << 17]byte var x3010 [1 << 17]byte var x3011 [1 << 17]byte var x3012 [1 << 17]byte var x3013 [1 << 17]byte var x3014 [1 << 17]byte var x3015 [1 << 17]byte var x3016 [1 << 17]byte var x3017 [1 << 17]byte var x3018 [1 << 17]byte var x3019 [1 << 17]byte var x3020 [1 << 17]byte var x3021 [1 << 17]byte var x3022 [1 << 17]byte var x3023 [1 << 17]byte var x3024 [1 << 17]byte var x3025 [1 << 17]byte var x3026 [1 << 17]byte var x3027 [1 << 17]byte var x3028 [1 << 17]byte var x3029 [1 << 17]byte var x3030 [1 << 17]byte var x3031 [1 << 17]byte var x3032 [1 << 17]byte var x3033 [1 << 17]byte var x3034 [1 << 17]byte var x3035 [1 << 17]byte var x3036 [1 << 17]byte var x3037 [1 << 17]byte var x3038 [1 << 17]byte var x3039 [1 << 17]byte var x3040 [1 << 17]byte var x3041 [1 << 17]byte var x3042 [1 << 17]byte var x3043 [1 << 17]byte var x3044 [1 << 17]byte var x3045 [1 << 17]byte var x3046 [1 << 17]byte var x3047 [1 << 17]byte var x3048 [1 << 17]byte var x3049 [1 << 17]byte var x3050 [1 << 17]byte var x3051 [1 << 17]byte var x3052 [1 << 17]byte var x3053 [1 << 17]byte var x3054 [1 << 17]byte var x3055 [1 << 17]byte var x3056 [1 << 17]byte var x3057 [1 << 17]byte var x3058 [1 << 17]byte var x3059 [1 << 17]byte var x3060 [1 << 17]byte var x3061 [1 << 17]byte var x3062 [1 << 17]byte var x3063 [1 << 17]byte var x3064 [1 << 17]byte var x3065 [1 << 17]byte var x3066 [1 << 17]byte var x3067 [1 << 17]byte var x3068 [1 << 17]byte var x3069 [1 << 17]byte var x3070 [1 << 17]byte var x3071 [1 << 17]byte var x3072 [1 << 17]byte var x3073 [1 << 17]byte var x3074 [1 << 17]byte var x3075 [1 << 17]byte var x3076 [1 << 17]byte var x3077 [1 << 17]byte var x3078 [1 << 17]byte var x3079 [1 << 17]byte var x3080 [1 << 17]byte var x3081 [1 << 17]byte var x3082 [1 << 17]byte var x3083 [1 << 17]byte var x3084 [1 << 17]byte var x3085 [1 << 17]byte var x3086 [1 << 17]byte var x3087 [1 << 17]byte var x3088 [1 << 17]byte var x3089 [1 << 17]byte var x3090 [1 << 17]byte var x3091 [1 << 17]byte var x3092 [1 << 17]byte var x3093 [1 << 17]byte var x3094 [1 << 17]byte var x3095 [1 << 17]byte var x3096 [1 << 17]byte var x3097 [1 << 17]byte var x3098 [1 << 17]byte var x3099 [1 << 17]byte var x3100 [1 << 17]byte var x3101 [1 << 17]byte var x3102 [1 << 17]byte var x3103 [1 << 17]byte var x3104 [1 << 17]byte var x3105 [1 << 17]byte var x3106 [1 << 17]byte var x3107 [1 << 17]byte var x3108 [1 << 17]byte var x3109 [1 << 17]byte var x3110 [1 << 17]byte var x3111 [1 << 17]byte var x3112 [1 << 17]byte var x3113 [1 << 17]byte var x3114 [1 << 17]byte var x3115 [1 << 17]byte var x3116 [1 << 17]byte var x3117 [1 << 17]byte var x3118 [1 << 17]byte var x3119 [1 << 17]byte var x3120 [1 << 17]byte var x3121 [1 << 17]byte var x3122 [1 << 17]byte var x3123 [1 << 17]byte var x3124 [1 << 17]byte var x3125 [1 << 17]byte var x3126 [1 << 17]byte var x3127 [1 << 17]byte var x3128 [1 << 17]byte var x3129 [1 << 17]byte var x3130 [1 << 17]byte var x3131 [1 << 17]byte var x3132 [1 << 17]byte var x3133 [1 << 17]byte var x3134 [1 << 17]byte var x3135 [1 << 17]byte var x3136 [1 << 17]byte var x3137 [1 << 17]byte var x3138 [1 << 17]byte var x3139 [1 << 17]byte var x3140 [1 << 17]byte var x3141 [1 << 17]byte var x3142 [1 << 17]byte var x3143 [1 << 17]byte var x3144 [1 << 17]byte var x3145 [1 << 17]byte var x3146 [1 << 17]byte var x3147 [1 << 17]byte var x3148 [1 << 17]byte var x3149 [1 << 17]byte var x3150 [1 << 17]byte var x3151 [1 << 17]byte var x3152 [1 << 17]byte var x3153 [1 << 17]byte var x3154 [1 << 17]byte var x3155 [1 << 17]byte var x3156 [1 << 17]byte var x3157 [1 << 17]byte var x3158 [1 << 17]byte var x3159 [1 << 17]byte var x3160 [1 << 17]byte var x3161 [1 << 17]byte var x3162 [1 << 17]byte var x3163 [1 << 17]byte var x3164 [1 << 17]byte var x3165 [1 << 17]byte var x3166 [1 << 17]byte var x3167 [1 << 17]byte var x3168 [1 << 17]byte var x3169 [1 << 17]byte var x3170 [1 << 17]byte var x3171 [1 << 17]byte var x3172 [1 << 17]byte var x3173 [1 << 17]byte var x3174 [1 << 17]byte var x3175 [1 << 17]byte var x3176 [1 << 17]byte var x3177 [1 << 17]byte var x3178 [1 << 17]byte var x3179 [1 << 17]byte var x3180 [1 << 17]byte var x3181 [1 << 17]byte var x3182 [1 << 17]byte var x3183 [1 << 17]byte var x3184 [1 << 17]byte var x3185 [1 << 17]byte var x3186 [1 << 17]byte var x3187 [1 << 17]byte var x3188 [1 << 17]byte var x3189 [1 << 17]byte var x3190 [1 << 17]byte var x3191 [1 << 17]byte var x3192 [1 << 17]byte var x3193 [1 << 17]byte var x3194 [1 << 17]byte var x3195 [1 << 17]byte var x3196 [1 << 17]byte var x3197 [1 << 17]byte var x3198 [1 << 17]byte var x3199 [1 << 17]byte var x3200 [1 << 17]byte var x3201 [1 << 17]byte var x3202 [1 << 17]byte var x3203 [1 << 17]byte var x3204 [1 << 17]byte var x3205 [1 << 17]byte var x3206 [1 << 17]byte var x3207 [1 << 17]byte var x3208 [1 << 17]byte var x3209 [1 << 17]byte var x3210 [1 << 17]byte var x3211 [1 << 17]byte var x3212 [1 << 17]byte var x3213 [1 << 17]byte var x3214 [1 << 17]byte var x3215 [1 << 17]byte var x3216 [1 << 17]byte var x3217 [1 << 17]byte var x3218 [1 << 17]byte var x3219 [1 << 17]byte var x3220 [1 << 17]byte var x3221 [1 << 17]byte var x3222 [1 << 17]byte var x3223 [1 << 17]byte var x3224 [1 << 17]byte var x3225 [1 << 17]byte var x3226 [1 << 17]byte var x3227 [1 << 17]byte var x3228 [1 << 17]byte var x3229 [1 << 17]byte var x3230 [1 << 17]byte var x3231 [1 << 17]byte var x3232 [1 << 17]byte var x3233 [1 << 17]byte var x3234 [1 << 17]byte var x3235 [1 << 17]byte var x3236 [1 << 17]byte var x3237 [1 << 17]byte var x3238 [1 << 17]byte var x3239 [1 << 17]byte var x3240 [1 << 17]byte var x3241 [1 << 17]byte var x3242 [1 << 17]byte var x3243 [1 << 17]byte var x3244 [1 << 17]byte var x3245 [1 << 17]byte var x3246 [1 << 17]byte var x3247 [1 << 17]byte var x3248 [1 << 17]byte var x3249 [1 << 17]byte var x3250 [1 << 17]byte var x3251 [1 << 17]byte var x3252 [1 << 17]byte var x3253 [1 << 17]byte var x3254 [1 << 17]byte var x3255 [1 << 17]byte var x3256 [1 << 17]byte var x3257 [1 << 17]byte var x3258 [1 << 17]byte var x3259 [1 << 17]byte var x3260 [1 << 17]byte var x3261 [1 << 17]byte var x3262 [1 << 17]byte var x3263 [1 << 17]byte var x3264 [1 << 17]byte var x3265 [1 << 17]byte var x3266 [1 << 17]byte var x3267 [1 << 17]byte var x3268 [1 << 17]byte var x3269 [1 << 17]byte var x3270 [1 << 17]byte var x3271 [1 << 17]byte var x3272 [1 << 17]byte var x3273 [1 << 17]byte var x3274 [1 << 17]byte var x3275 [1 << 17]byte var x3276 [1 << 17]byte var x3277 [1 << 17]byte var x3278 [1 << 17]byte var x3279 [1 << 17]byte var x3280 [1 << 17]byte var x3281 [1 << 17]byte var x3282 [1 << 17]byte var x3283 [1 << 17]byte var x3284 [1 << 17]byte var x3285 [1 << 17]byte var x3286 [1 << 17]byte var x3287 [1 << 17]byte var x3288 [1 << 17]byte var x3289 [1 << 17]byte var x3290 [1 << 17]byte var x3291 [1 << 17]byte var x3292 [1 << 17]byte var x3293 [1 << 17]byte var x3294 [1 << 17]byte var x3295 [1 << 17]byte var x3296 [1 << 17]byte var x3297 [1 << 17]byte var x3298 [1 << 17]byte var x3299 [1 << 17]byte var x3300 [1 << 17]byte var x3301 [1 << 17]byte var x3302 [1 << 17]byte var x3303 [1 << 17]byte var x3304 [1 << 17]byte var x3305 [1 << 17]byte var x3306 [1 << 17]byte var x3307 [1 << 17]byte var x3308 [1 << 17]byte var x3309 [1 << 17]byte var x3310 [1 << 17]byte var x3311 [1 << 17]byte var x3312 [1 << 17]byte var x3313 [1 << 17]byte var x3314 [1 << 17]byte var x3315 [1 << 17]byte var x3316 [1 << 17]byte var x3317 [1 << 17]byte var x3318 [1 << 17]byte var x3319 [1 << 17]byte var x3320 [1 << 17]byte var x3321 [1 << 17]byte var x3322 [1 << 17]byte var x3323 [1 << 17]byte var x3324 [1 << 17]byte var x3325 [1 << 17]byte var x3326 [1 << 17]byte var x3327 [1 << 17]byte var x3328 [1 << 17]byte var x3329 [1 << 17]byte var x3330 [1 << 17]byte var x3331 [1 << 17]byte var x3332 [1 << 17]byte var x3333 [1 << 17]byte var x3334 [1 << 17]byte var x3335 [1 << 17]byte var x3336 [1 << 17]byte var x3337 [1 << 17]byte var x3338 [1 << 17]byte var x3339 [1 << 17]byte var x3340 [1 << 17]byte var x3341 [1 << 17]byte var x3342 [1 << 17]byte var x3343 [1 << 17]byte var x3344 [1 << 17]byte var x3345 [1 << 17]byte var x3346 [1 << 17]byte var x3347 [1 << 17]byte var x3348 [1 << 17]byte var x3349 [1 << 17]byte var x3350 [1 << 17]byte var x3351 [1 << 17]byte var x3352 [1 << 17]byte var x3353 [1 << 17]byte var x3354 [1 << 17]byte var x3355 [1 << 17]byte var x3356 [1 << 17]byte var x3357 [1 << 17]byte var x3358 [1 << 17]byte var x3359 [1 << 17]byte var x3360 [1 << 17]byte var x3361 [1 << 17]byte var x3362 [1 << 17]byte var x3363 [1 << 17]byte var x3364 [1 << 17]byte var x3365 [1 << 17]byte var x3366 [1 << 17]byte var x3367 [1 << 17]byte var x3368 [1 << 17]byte var x3369 [1 << 17]byte var x3370 [1 << 17]byte var x3371 [1 << 17]byte var x3372 [1 << 17]byte var x3373 [1 << 17]byte var x3374 [1 << 17]byte var x3375 [1 << 17]byte var x3376 [1 << 17]byte var x3377 [1 << 17]byte var x3378 [1 << 17]byte var x3379 [1 << 17]byte var x3380 [1 << 17]byte var x3381 [1 << 17]byte var x3382 [1 << 17]byte var x3383 [1 << 17]byte var x3384 [1 << 17]byte var x3385 [1 << 17]byte var x3386 [1 << 17]byte var x3387 [1 << 17]byte var x3388 [1 << 17]byte var x3389 [1 << 17]byte var x3390 [1 << 17]byte var x3391 [1 << 17]byte var x3392 [1 << 17]byte var x3393 [1 << 17]byte var x3394 [1 << 17]byte var x3395 [1 << 17]byte var x3396 [1 << 17]byte var x3397 [1 << 17]byte var x3398 [1 << 17]byte var x3399 [1 << 17]byte var x3400 [1 << 17]byte var x3401 [1 << 17]byte var x3402 [1 << 17]byte var x3403 [1 << 17]byte var x3404 [1 << 17]byte var x3405 [1 << 17]byte var x3406 [1 << 17]byte var x3407 [1 << 17]byte var x3408 [1 << 17]byte var x3409 [1 << 17]byte var x3410 [1 << 17]byte var x3411 [1 << 17]byte var x3412 [1 << 17]byte var x3413 [1 << 17]byte var x3414 [1 << 17]byte var x3415 [1 << 17]byte var x3416 [1 << 17]byte var x3417 [1 << 17]byte var x3418 [1 << 17]byte var x3419 [1 << 17]byte var x3420 [1 << 17]byte var x3421 [1 << 17]byte var x3422 [1 << 17]byte var x3423 [1 << 17]byte var x3424 [1 << 17]byte var x3425 [1 << 17]byte var x3426 [1 << 17]byte var x3427 [1 << 17]byte var x3428 [1 << 17]byte var x3429 [1 << 17]byte var x3430 [1 << 17]byte var x3431 [1 << 17]byte var x3432 [1 << 17]byte var x3433 [1 << 17]byte var x3434 [1 << 17]byte var x3435 [1 << 17]byte var x3436 [1 << 17]byte var x3437 [1 << 17]byte var x3438 [1 << 17]byte var x3439 [1 << 17]byte var x3440 [1 << 17]byte var x3441 [1 << 17]byte var x3442 [1 << 17]byte var x3443 [1 << 17]byte var x3444 [1 << 17]byte var x3445 [1 << 17]byte var x3446 [1 << 17]byte var x3447 [1 << 17]byte var x3448 [1 << 17]byte var x3449 [1 << 17]byte var x3450 [1 << 17]byte var x3451 [1 << 17]byte var x3452 [1 << 17]byte var x3453 [1 << 17]byte var x3454 [1 << 17]byte var x3455 [1 << 17]byte var x3456 [1 << 17]byte var x3457 [1 << 17]byte var x3458 [1 << 17]byte var x3459 [1 << 17]byte var x3460 [1 << 17]byte var x3461 [1 << 17]byte var x3462 [1 << 17]byte var x3463 [1 << 17]byte var x3464 [1 << 17]byte var x3465 [1 << 17]byte var x3466 [1 << 17]byte var x3467 [1 << 17]byte var x3468 [1 << 17]byte var x3469 [1 << 17]byte var x3470 [1 << 17]byte var x3471 [1 << 17]byte var x3472 [1 << 17]byte var x3473 [1 << 17]byte var x3474 [1 << 17]byte var x3475 [1 << 17]byte var x3476 [1 << 17]byte var x3477 [1 << 17]byte var x3478 [1 << 17]byte var x3479 [1 << 17]byte var x3480 [1 << 17]byte var x3481 [1 << 17]byte var x3482 [1 << 17]byte var x3483 [1 << 17]byte var x3484 [1 << 17]byte var x3485 [1 << 17]byte var x3486 [1 << 17]byte var x3487 [1 << 17]byte var x3488 [1 << 17]byte var x3489 [1 << 17]byte var x3490 [1 << 17]byte var x3491 [1 << 17]byte var x3492 [1 << 17]byte var x3493 [1 << 17]byte var x3494 [1 << 17]byte var x3495 [1 << 17]byte var x3496 [1 << 17]byte var x3497 [1 << 17]byte var x3498 [1 << 17]byte var x3499 [1 << 17]byte var x3500 [1 << 17]byte var x3501 [1 << 17]byte var x3502 [1 << 17]byte var x3503 [1 << 17]byte var x3504 [1 << 17]byte var x3505 [1 << 17]byte var x3506 [1 << 17]byte var x3507 [1 << 17]byte var x3508 [1 << 17]byte var x3509 [1 << 17]byte var x3510 [1 << 17]byte var x3511 [1 << 17]byte var x3512 [1 << 17]byte var x3513 [1 << 17]byte var x3514 [1 << 17]byte var x3515 [1 << 17]byte var x3516 [1 << 17]byte var x3517 [1 << 17]byte var x3518 [1 << 17]byte var x3519 [1 << 17]byte var x3520 [1 << 17]byte var x3521 [1 << 17]byte var x3522 [1 << 17]byte var x3523 [1 << 17]byte var x3524 [1 << 17]byte var x3525 [1 << 17]byte var x3526 [1 << 17]byte var x3527 [1 << 17]byte var x3528 [1 << 17]byte var x3529 [1 << 17]byte var x3530 [1 << 17]byte var x3531 [1 << 17]byte var x3532 [1 << 17]byte var x3533 [1 << 17]byte var x3534 [1 << 17]byte var x3535 [1 << 17]byte var x3536 [1 << 17]byte var x3537 [1 << 17]byte var x3538 [1 << 17]byte var x3539 [1 << 17]byte var x3540 [1 << 17]byte var x3541 [1 << 17]byte var x3542 [1 << 17]byte var x3543 [1 << 17]byte var x3544 [1 << 17]byte var x3545 [1 << 17]byte var x3546 [1 << 17]byte var x3547 [1 << 17]byte var x3548 [1 << 17]byte var x3549 [1 << 17]byte var x3550 [1 << 17]byte var x3551 [1 << 17]byte var x3552 [1 << 17]byte var x3553 [1 << 17]byte var x3554 [1 << 17]byte var x3555 [1 << 17]byte var x3556 [1 << 17]byte var x3557 [1 << 17]byte var x3558 [1 << 17]byte var x3559 [1 << 17]byte var x3560 [1 << 17]byte var x3561 [1 << 17]byte var x3562 [1 << 17]byte var x3563 [1 << 17]byte var x3564 [1 << 17]byte var x3565 [1 << 17]byte var x3566 [1 << 17]byte var x3567 [1 << 17]byte var x3568 [1 << 17]byte var x3569 [1 << 17]byte var x3570 [1 << 17]byte var x3571 [1 << 17]byte var x3572 [1 << 17]byte var x3573 [1 << 17]byte var x3574 [1 << 17]byte var x3575 [1 << 17]byte var x3576 [1 << 17]byte var x3577 [1 << 17]byte var x3578 [1 << 17]byte var x3579 [1 << 17]byte var x3580 [1 << 17]byte var x3581 [1 << 17]byte var x3582 [1 << 17]byte var x3583 [1 << 17]byte var x3584 [1 << 17]byte var x3585 [1 << 17]byte var x3586 [1 << 17]byte var x3587 [1 << 17]byte var x3588 [1 << 17]byte var x3589 [1 << 17]byte var x3590 [1 << 17]byte var x3591 [1 << 17]byte var x3592 [1 << 17]byte var x3593 [1 << 17]byte var x3594 [1 << 17]byte var x3595 [1 << 17]byte var x3596 [1 << 17]byte var x3597 [1 << 17]byte var x3598 [1 << 17]byte var x3599 [1 << 17]byte var x3600 [1 << 17]byte var x3601 [1 << 17]byte var x3602 [1 << 17]byte var x3603 [1 << 17]byte var x3604 [1 << 17]byte var x3605 [1 << 17]byte var x3606 [1 << 17]byte var x3607 [1 << 17]byte var x3608 [1 << 17]byte var x3609 [1 << 17]byte var x3610 [1 << 17]byte var x3611 [1 << 17]byte var x3612 [1 << 17]byte var x3613 [1 << 17]byte var x3614 [1 << 17]byte var x3615 [1 << 17]byte var x3616 [1 << 17]byte var x3617 [1 << 17]byte var x3618 [1 << 17]byte var x3619 [1 << 17]byte var x3620 [1 << 17]byte var x3621 [1 << 17]byte var x3622 [1 << 17]byte var x3623 [1 << 17]byte var x3624 [1 << 17]byte var x3625 [1 << 17]byte var x3626 [1 << 17]byte var x3627 [1 << 17]byte var x3628 [1 << 17]byte var x3629 [1 << 17]byte var x3630 [1 << 17]byte var x3631 [1 << 17]byte var x3632 [1 << 17]byte var x3633 [1 << 17]byte var x3634 [1 << 17]byte var x3635 [1 << 17]byte var x3636 [1 << 17]byte var x3637 [1 << 17]byte var x3638 [1 << 17]byte var x3639 [1 << 17]byte var x3640 [1 << 17]byte var x3641 [1 << 17]byte var x3642 [1 << 17]byte var x3643 [1 << 17]byte var x3644 [1 << 17]byte var x3645 [1 << 17]byte var x3646 [1 << 17]byte var x3647 [1 << 17]byte var x3648 [1 << 17]byte var x3649 [1 << 17]byte var x3650 [1 << 17]byte var x3651 [1 << 17]byte var x3652 [1 << 17]byte var x3653 [1 << 17]byte var x3654 [1 << 17]byte var x3655 [1 << 17]byte var x3656 [1 << 17]byte var x3657 [1 << 17]byte var x3658 [1 << 17]byte var x3659 [1 << 17]byte var x3660 [1 << 17]byte var x3661 [1 << 17]byte var x3662 [1 << 17]byte var x3663 [1 << 17]byte var x3664 [1 << 17]byte var x3665 [1 << 17]byte var x3666 [1 << 17]byte var x3667 [1 << 17]byte var x3668 [1 << 17]byte var x3669 [1 << 17]byte var x3670 [1 << 17]byte var x3671 [1 << 17]byte var x3672 [1 << 17]byte var x3673 [1 << 17]byte var x3674 [1 << 17]byte var x3675 [1 << 17]byte var x3676 [1 << 17]byte var x3677 [1 << 17]byte var x3678 [1 << 17]byte var x3679 [1 << 17]byte var x3680 [1 << 17]byte var x3681 [1 << 17]byte var x3682 [1 << 17]byte var x3683 [1 << 17]byte var x3684 [1 << 17]byte var x3685 [1 << 17]byte var x3686 [1 << 17]byte var x3687 [1 << 17]byte var x3688 [1 << 17]byte var x3689 [1 << 17]byte var x3690 [1 << 17]byte var x3691 [1 << 17]byte var x3692 [1 << 17]byte var x3693 [1 << 17]byte var x3694 [1 << 17]byte var x3695 [1 << 17]byte var x3696 [1 << 17]byte var x3697 [1 << 17]byte var x3698 [1 << 17]byte var x3699 [1 << 17]byte var x3700 [1 << 17]byte var x3701 [1 << 17]byte var x3702 [1 << 17]byte var x3703 [1 << 17]byte var x3704 [1 << 17]byte var x3705 [1 << 17]byte var x3706 [1 << 17]byte var x3707 [1 << 17]byte var x3708 [1 << 17]byte var x3709 [1 << 17]byte var x3710 [1 << 17]byte var x3711 [1 << 17]byte var x3712 [1 << 17]byte var x3713 [1 << 17]byte var x3714 [1 << 17]byte var x3715 [1 << 17]byte var x3716 [1 << 17]byte var x3717 [1 << 17]byte var x3718 [1 << 17]byte var x3719 [1 << 17]byte var x3720 [1 << 17]byte var x3721 [1 << 17]byte var x3722 [1 << 17]byte var x3723 [1 << 17]byte var x3724 [1 << 17]byte var x3725 [1 << 17]byte var x3726 [1 << 17]byte var x3727 [1 << 17]byte var x3728 [1 << 17]byte var x3729 [1 << 17]byte var x3730 [1 << 17]byte var x3731 [1 << 17]byte var x3732 [1 << 17]byte var x3733 [1 << 17]byte var x3734 [1 << 17]byte var x3735 [1 << 17]byte var x3736 [1 << 17]byte var x3737 [1 << 17]byte var x3738 [1 << 17]byte var x3739 [1 << 17]byte var x3740 [1 << 17]byte var x3741 [1 << 17]byte var x3742 [1 << 17]byte var x3743 [1 << 17]byte var x3744 [1 << 17]byte var x3745 [1 << 17]byte var x3746 [1 << 17]byte var x3747 [1 << 17]byte var x3748 [1 << 17]byte var x3749 [1 << 17]byte var x3750 [1 << 17]byte var x3751 [1 << 17]byte var x3752 [1 << 17]byte var x3753 [1 << 17]byte var x3754 [1 << 17]byte var x3755 [1 << 17]byte var x3756 [1 << 17]byte var x3757 [1 << 17]byte var x3758 [1 << 17]byte var x3759 [1 << 17]byte var x3760 [1 << 17]byte var x3761 [1 << 17]byte var x3762 [1 << 17]byte var x3763 [1 << 17]byte var x3764 [1 << 17]byte var x3765 [1 << 17]byte var x3766 [1 << 17]byte var x3767 [1 << 17]byte var x3768 [1 << 17]byte var x3769 [1 << 17]byte var x3770 [1 << 17]byte var x3771 [1 << 17]byte var x3772 [1 << 17]byte var x3773 [1 << 17]byte var x3774 [1 << 17]byte var x3775 [1 << 17]byte var x3776 [1 << 17]byte var x3777 [1 << 17]byte var x3778 [1 << 17]byte var x3779 [1 << 17]byte var x3780 [1 << 17]byte var x3781 [1 << 17]byte var x3782 [1 << 17]byte var x3783 [1 << 17]byte var x3784 [1 << 17]byte var x3785 [1 << 17]byte var x3786 [1 << 17]byte var x3787 [1 << 17]byte var x3788 [1 << 17]byte var x3789 [1 << 17]byte var x3790 [1 << 17]byte var x3791 [1 << 17]byte var x3792 [1 << 17]byte var x3793 [1 << 17]byte var x3794 [1 << 17]byte var x3795 [1 << 17]byte var x3796 [1 << 17]byte var x3797 [1 << 17]byte var x3798 [1 << 17]byte var x3799 [1 << 17]byte var x3800 [1 << 17]byte var x3801 [1 << 17]byte var x3802 [1 << 17]byte var x3803 [1 << 17]byte var x3804 [1 << 17]byte var x3805 [1 << 17]byte var x3806 [1 << 17]byte var x3807 [1 << 17]byte var x3808 [1 << 17]byte var x3809 [1 << 17]byte var x3810 [1 << 17]byte var x3811 [1 << 17]byte var x3812 [1 << 17]byte var x3813 [1 << 17]byte var x3814 [1 << 17]byte var x3815 [1 << 17]byte var x3816 [1 << 17]byte var x3817 [1 << 17]byte var x3818 [1 << 17]byte var x3819 [1 << 17]byte var x3820 [1 << 17]byte var x3821 [1 << 17]byte var x3822 [1 << 17]byte var x3823 [1 << 17]byte var x3824 [1 << 17]byte var x3825 [1 << 17]byte var x3826 [1 << 17]byte var x3827 [1 << 17]byte var x3828 [1 << 17]byte var x3829 [1 << 17]byte var x3830 [1 << 17]byte var x3831 [1 << 17]byte var x3832 [1 << 17]byte var x3833 [1 << 17]byte var x3834 [1 << 17]byte var x3835 [1 << 17]byte var x3836 [1 << 17]byte var x3837 [1 << 17]byte var x3838 [1 << 17]byte var x3839 [1 << 17]byte var x3840 [1 << 17]byte var x3841 [1 << 17]byte var x3842 [1 << 17]byte var x3843 [1 << 17]byte var x3844 [1 << 17]byte var x3845 [1 << 17]byte var x3846 [1 << 17]byte var x3847 [1 << 17]byte var x3848 [1 << 17]byte var x3849 [1 << 17]byte var x3850 [1 << 17]byte var x3851 [1 << 17]byte var x3852 [1 << 17]byte var x3853 [1 << 17]byte var x3854 [1 << 17]byte var x3855 [1 << 17]byte var x3856 [1 << 17]byte var x3857 [1 << 17]byte var x3858 [1 << 17]byte var x3859 [1 << 17]byte var x3860 [1 << 17]byte var x3861 [1 << 17]byte var x3862 [1 << 17]byte var x3863 [1 << 17]byte var x3864 [1 << 17]byte var x3865 [1 << 17]byte var x3866 [1 << 17]byte var x3867 [1 << 17]byte var x3868 [1 << 17]byte var x3869 [1 << 17]byte var x3870 [1 << 17]byte var x3871 [1 << 17]byte var x3872 [1 << 17]byte var x3873 [1 << 17]byte var x3874 [1 << 17]byte var x3875 [1 << 17]byte var x3876 [1 << 17]byte var x3877 [1 << 17]byte var x3878 [1 << 17]byte var x3879 [1 << 17]byte var x3880 [1 << 17]byte var x3881 [1 << 17]byte var x3882 [1 << 17]byte var x3883 [1 << 17]byte var x3884 [1 << 17]byte var x3885 [1 << 17]byte var x3886 [1 << 17]byte var x3887 [1 << 17]byte var x3888 [1 << 17]byte var x3889 [1 << 17]byte var x3890 [1 << 17]byte var x3891 [1 << 17]byte var x3892 [1 << 17]byte var x3893 [1 << 17]byte var x3894 [1 << 17]byte var x3895 [1 << 17]byte var x3896 [1 << 17]byte var x3897 [1 << 17]byte var x3898 [1 << 17]byte var x3899 [1 << 17]byte var x3900 [1 << 17]byte var x3901 [1 << 17]byte var x3902 [1 << 17]byte var x3903 [1 << 17]byte var x3904 [1 << 17]byte var x3905 [1 << 17]byte var x3906 [1 << 17]byte var x3907 [1 << 17]byte var x3908 [1 << 17]byte var x3909 [1 << 17]byte var x3910 [1 << 17]byte var x3911 [1 << 17]byte var x3912 [1 << 17]byte var x3913 [1 << 17]byte var x3914 [1 << 17]byte var x3915 [1 << 17]byte var x3916 [1 << 17]byte var x3917 [1 << 17]byte var x3918 [1 << 17]byte var x3919 [1 << 17]byte var x3920 [1 << 17]byte var x3921 [1 << 17]byte var x3922 [1 << 17]byte var x3923 [1 << 17]byte var x3924 [1 << 17]byte var x3925 [1 << 17]byte var x3926 [1 << 17]byte var x3927 [1 << 17]byte var x3928 [1 << 17]byte var x3929 [1 << 17]byte var x3930 [1 << 17]byte var x3931 [1 << 17]byte var x3932 [1 << 17]byte var x3933 [1 << 17]byte var x3934 [1 << 17]byte var x3935 [1 << 17]byte var x3936 [1 << 17]byte var x3937 [1 << 17]byte var x3938 [1 << 17]byte var x3939 [1 << 17]byte var x3940 [1 << 17]byte var x3941 [1 << 17]byte var x3942 [1 << 17]byte var x3943 [1 << 17]byte var x3944 [1 << 17]byte var x3945 [1 << 17]byte var x3946 [1 << 17]byte var x3947 [1 << 17]byte var x3948 [1 << 17]byte var x3949 [1 << 17]byte var x3950 [1 << 17]byte var x3951 [1 << 17]byte var x3952 [1 << 17]byte var x3953 [1 << 17]byte var x3954 [1 << 17]byte var x3955 [1 << 17]byte var x3956 [1 << 17]byte var x3957 [1 << 17]byte var x3958 [1 << 17]byte var x3959 [1 << 17]byte var x3960 [1 << 17]byte var x3961 [1 << 17]byte var x3962 [1 << 17]byte var x3963 [1 << 17]byte var x3964 [1 << 17]byte var x3965 [1 << 17]byte var x3966 [1 << 17]byte var x3967 [1 << 17]byte var x3968 [1 << 17]byte var x3969 [1 << 17]byte var x3970 [1 << 17]byte var x3971 [1 << 17]byte var x3972 [1 << 17]byte var x3973 [1 << 17]byte var x3974 [1 << 17]byte var x3975 [1 << 17]byte var x3976 [1 << 17]byte var x3977 [1 << 17]byte var x3978 [1 << 17]byte var x3979 [1 << 17]byte var x3980 [1 << 17]byte var x3981 [1 << 17]byte var x3982 [1 << 17]byte var x3983 [1 << 17]byte var x3984 [1 << 17]byte var x3985 [1 << 17]byte var x3986 [1 << 17]byte var x3987 [1 << 17]byte var x3988 [1 << 17]byte var x3989 [1 << 17]byte var x3990 [1 << 17]byte var x3991 [1 << 17]byte var x3992 [1 << 17]byte var x3993 [1 << 17]byte var x3994 [1 << 17]byte var x3995 [1 << 17]byte var x3996 [1 << 17]byte var x3997 [1 << 17]byte var x3998 [1 << 17]byte var x3999 [1 << 17]byte var x4000 [1 << 17]byte var x4001 [1 << 17]byte var x4002 [1 << 17]byte var x4003 [1 << 17]byte var x4004 [1 << 17]byte var x4005 [1 << 17]byte var x4006 [1 << 17]byte var x4007 [1 << 17]byte var x4008 [1 << 17]byte var x4009 [1 << 17]byte var x4010 [1 << 17]byte var x4011 [1 << 17]byte var x4012 [1 << 17]byte var x4013 [1 << 17]byte var x4014 [1 << 17]byte var x4015 [1 << 17]byte var x4016 [1 << 17]byte var x4017 [1 << 17]byte var x4018 [1 << 17]byte var x4019 [1 << 17]byte var x4020 [1 << 17]byte var x4021 [1 << 17]byte var x4022 [1 << 17]byte var x4023 [1 << 17]byte var x4024 [1 << 17]byte var x4025 [1 << 17]byte var x4026 [1 << 17]byte var x4027 [1 << 17]byte var x4028 [1 << 17]byte var x4029 [1 << 17]byte var x4030 [1 << 17]byte var x4031 [1 << 17]byte var x4032 [1 << 17]byte var x4033 [1 << 17]byte var x4034 [1 << 17]byte var x4035 [1 << 17]byte var x4036 [1 << 17]byte var x4037 [1 << 17]byte var x4038 [1 << 17]byte var x4039 [1 << 17]byte var x4040 [1 << 17]byte var x4041 [1 << 17]byte var x4042 [1 << 17]byte var x4043 [1 << 17]byte var x4044 [1 << 17]byte var x4045 [1 << 17]byte var x4046 [1 << 17]byte var x4047 [1 << 17]byte var x4048 [1 << 17]byte var x4049 [1 << 17]byte var x4050 [1 << 17]byte var x4051 [1 << 17]byte var x4052 [1 << 17]byte var x4053 [1 << 17]byte var x4054 [1 << 17]byte var x4055 [1 << 17]byte var x4056 [1 << 17]byte var x4057 [1 << 17]byte var x4058 [1 << 17]byte var x4059 [1 << 17]byte var x4060 [1 << 17]byte var x4061 [1 << 17]byte var x4062 [1 << 17]byte var x4063 [1 << 17]byte var x4064 [1 << 17]byte var x4065 [1 << 17]byte var x4066 [1 << 17]byte var x4067 [1 << 17]byte var x4068 [1 << 17]byte var x4069 [1 << 17]byte var x4070 [1 << 17]byte var x4071 [1 << 17]byte var x4072 [1 << 17]byte var x4073 [1 << 17]byte var x4074 [1 << 17]byte var x4075 [1 << 17]byte var x4076 [1 << 17]byte var x4077 [1 << 17]byte var x4078 [1 << 17]byte var x4079 [1 << 17]byte var x4080 [1 << 17]byte var x4081 [1 << 17]byte var x4082 [1 << 17]byte var x4083 [1 << 17]byte var x4084 [1 << 17]byte var x4085 [1 << 17]byte var x4086 [1 << 17]byte var x4087 [1 << 17]byte var x4088 [1 << 17]byte var x4089 [1 << 17]byte var x4090 [1 << 17]byte var x4091 [1 << 17]byte var x4092 [1 << 17]byte var x4093 [1 << 17]byte var x4094 [1 << 17]byte var x4095 [1 << 17]byte var x4096 [1 << 17]byte var x4097 [1 << 17]byte var x4098 [1 << 17]byte var x4099 [1 << 17]byte var x4100 [1 << 17]byte var x4101 [1 << 17]byte var x4102 [1 << 17]byte var x4103 [1 << 17]byte var x4104 [1 << 17]byte var x4105 [1 << 17]byte var x4106 [1 << 17]byte var x4107 [1 << 17]byte var x4108 [1 << 17]byte var x4109 [1 << 17]byte var x4110 [1 << 17]byte var x4111 [1 << 17]byte var x4112 [1 << 17]byte var x4113 [1 << 17]byte var x4114 [1 << 17]byte var x4115 [1 << 17]byte var x4116 [1 << 17]byte var x4117 [1 << 17]byte var x4118 [1 << 17]byte var x4119 [1 << 17]byte var x4120 [1 << 17]byte var x4121 [1 << 17]byte var x4122 [1 << 17]byte var x4123 [1 << 17]byte var x4124 [1 << 17]byte var x4125 [1 << 17]byte var x4126 [1 << 17]byte var x4127 [1 << 17]byte var x4128 [1 << 17]byte var x4129 [1 << 17]byte var x4130 [1 << 17]byte var x4131 [1 << 17]byte var x4132 [1 << 17]byte var x4133 [1 << 17]byte var x4134 [1 << 17]byte var x4135 [1 << 17]byte var x4136 [1 << 17]byte var x4137 [1 << 17]byte var x4138 [1 << 17]byte var x4139 [1 << 17]byte var x4140 [1 << 17]byte var x4141 [1 << 17]byte var x4142 [1 << 17]byte var x4143 [1 << 17]byte var x4144 [1 << 17]byte var x4145 [1 << 17]byte var x4146 [1 << 17]byte var x4147 [1 << 17]byte var x4148 [1 << 17]byte var x4149 [1 << 17]byte var x4150 [1 << 17]byte var x4151 [1 << 17]byte var x4152 [1 << 17]byte var x4153 [1 << 17]byte var x4154 [1 << 17]byte var x4155 [1 << 17]byte var x4156 [1 << 17]byte var x4157 [1 << 17]byte var x4158 [1 << 17]byte var x4159 [1 << 17]byte var x4160 [1 << 17]byte var x4161 [1 << 17]byte var x4162 [1 << 17]byte var x4163 [1 << 17]byte var x4164 [1 << 17]byte var x4165 [1 << 17]byte var x4166 [1 << 17]byte var x4167 [1 << 17]byte var x4168 [1 << 17]byte var x4169 [1 << 17]byte var x4170 [1 << 17]byte var x4171 [1 << 17]byte var x4172 [1 << 17]byte var x4173 [1 << 17]byte var x4174 [1 << 17]byte var x4175 [1 << 17]byte var x4176 [1 << 17]byte var x4177 [1 << 17]byte var x4178 [1 << 17]byte var x4179 [1 << 17]byte var x4180 [1 << 17]byte var x4181 [1 << 17]byte var x4182 [1 << 17]byte var x4183 [1 << 17]byte var x4184 [1 << 17]byte var x4185 [1 << 17]byte var x4186 [1 << 17]byte var x4187 [1 << 17]byte var x4188 [1 << 17]byte var x4189 [1 << 17]byte var x4190 [1 << 17]byte var x4191 [1 << 17]byte var x4192 [1 << 17]byte var x4193 [1 << 17]byte var x4194 [1 << 17]byte var x4195 [1 << 17]byte var x4196 [1 << 17]byte var x4197 [1 << 17]byte var x4198 [1 << 17]byte var x4199 [1 << 17]byte var x4200 [1 << 17]byte var x4201 [1 << 17]byte var x4202 [1 << 17]byte var x4203 [1 << 17]byte var x4204 [1 << 17]byte var x4205 [1 << 17]byte var x4206 [1 << 17]byte var x4207 [1 << 17]byte var x4208 [1 << 17]byte var x4209 [1 << 17]byte var x4210 [1 << 17]byte var x4211 [1 << 17]byte var x4212 [1 << 17]byte var x4213 [1 << 17]byte var x4214 [1 << 17]byte var x4215 [1 << 17]byte var x4216 [1 << 17]byte var x4217 [1 << 17]byte var x4218 [1 << 17]byte var x4219 [1 << 17]byte var x4220 [1 << 17]byte var x4221 [1 << 17]byte var x4222 [1 << 17]byte var x4223 [1 << 17]byte var x4224 [1 << 17]byte var x4225 [1 << 17]byte var x4226 [1 << 17]byte var x4227 [1 << 17]byte var x4228 [1 << 17]byte var x4229 [1 << 17]byte var x4230 [1 << 17]byte var x4231 [1 << 17]byte var x4232 [1 << 17]byte var x4233 [1 << 17]byte var x4234 [1 << 17]byte var x4235 [1 << 17]byte var x4236 [1 << 17]byte var x4237 [1 << 17]byte var x4238 [1 << 17]byte var x4239 [1 << 17]byte var x4240 [1 << 17]byte var x4241 [1 << 17]byte var x4242 [1 << 17]byte var x4243 [1 << 17]byte var x4244 [1 << 17]byte var x4245 [1 << 17]byte var x4246 [1 << 17]byte var x4247 [1 << 17]byte var x4248 [1 << 17]byte var x4249 [1 << 17]byte var x4250 [1 << 17]byte var x4251 [1 << 17]byte var x4252 [1 << 17]byte var x4253 [1 << 17]byte var x4254 [1 << 17]byte var x4255 [1 << 17]byte var x4256 [1 << 17]byte var x4257 [1 << 17]byte var x4258 [1 << 17]byte var x4259 [1 << 17]byte var x4260 [1 << 17]byte var x4261 [1 << 17]byte var x4262 [1 << 17]byte var x4263 [1 << 17]byte var x4264 [1 << 17]byte var x4265 [1 << 17]byte var x4266 [1 << 17]byte var x4267 [1 << 17]byte var x4268 [1 << 17]byte var x4269 [1 << 17]byte var x4270 [1 << 17]byte var x4271 [1 << 17]byte var x4272 [1 << 17]byte var x4273 [1 << 17]byte var x4274 [1 << 17]byte var x4275 [1 << 17]byte var x4276 [1 << 17]byte var x4277 [1 << 17]byte var x4278 [1 << 17]byte var x4279 [1 << 17]byte var x4280 [1 << 17]byte var x4281 [1 << 17]byte var x4282 [1 << 17]byte var x4283 [1 << 17]byte var x4284 [1 << 17]byte var x4285 [1 << 17]byte var x4286 [1 << 17]byte var x4287 [1 << 17]byte var x4288 [1 << 17]byte var x4289 [1 << 17]byte var x4290 [1 << 17]byte var x4291 [1 << 17]byte var x4292 [1 << 17]byte var x4293 [1 << 17]byte var x4294 [1 << 17]byte var x4295 [1 << 17]byte var x4296 [1 << 17]byte var x4297 [1 << 17]byte var x4298 [1 << 17]byte var x4299 [1 << 17]byte var x4300 [1 << 17]byte var x4301 [1 << 17]byte var x4302 [1 << 17]byte var x4303 [1 << 17]byte var x4304 [1 << 17]byte var x4305 [1 << 17]byte var x4306 [1 << 17]byte var x4307 [1 << 17]byte var x4308 [1 << 17]byte var x4309 [1 << 17]byte var x4310 [1 << 17]byte var x4311 [1 << 17]byte var x4312 [1 << 17]byte var x4313 [1 << 17]byte var x4314 [1 << 17]byte var x4315 [1 << 17]byte var x4316 [1 << 17]byte var x4317 [1 << 17]byte var x4318 [1 << 17]byte var x4319 [1 << 17]byte var x4320 [1 << 17]byte var x4321 [1 << 17]byte var x4322 [1 << 17]byte var x4323 [1 << 17]byte var x4324 [1 << 17]byte var x4325 [1 << 17]byte var x4326 [1 << 17]byte var x4327 [1 << 17]byte var x4328 [1 << 17]byte var x4329 [1 << 17]byte var x4330 [1 << 17]byte var x4331 [1 << 17]byte var x4332 [1 << 17]byte var x4333 [1 << 17]byte var x4334 [1 << 17]byte var x4335 [1 << 17]byte var x4336 [1 << 17]byte var x4337 [1 << 17]byte var x4338 [1 << 17]byte var x4339 [1 << 17]byte var x4340 [1 << 17]byte var x4341 [1 << 17]byte var x4342 [1 << 17]byte var x4343 [1 << 17]byte var x4344 [1 << 17]byte var x4345 [1 << 17]byte var x4346 [1 << 17]byte var x4347 [1 << 17]byte var x4348 [1 << 17]byte var x4349 [1 << 17]byte var x4350 [1 << 17]byte var x4351 [1 << 17]byte var x4352 [1 << 17]byte var x4353 [1 << 17]byte var x4354 [1 << 17]byte var x4355 [1 << 17]byte var x4356 [1 << 17]byte var x4357 [1 << 17]byte var x4358 [1 << 17]byte var x4359 [1 << 17]byte var x4360 [1 << 17]byte var x4361 [1 << 17]byte var x4362 [1 << 17]byte var x4363 [1 << 17]byte var x4364 [1 << 17]byte var x4365 [1 << 17]byte var x4366 [1 << 17]byte var x4367 [1 << 17]byte var x4368 [1 << 17]byte var x4369 [1 << 17]byte var x4370 [1 << 17]byte var x4371 [1 << 17]byte var x4372 [1 << 17]byte var x4373 [1 << 17]byte var x4374 [1 << 17]byte var x4375 [1 << 17]byte var x4376 [1 << 17]byte var x4377 [1 << 17]byte var x4378 [1 << 17]byte var x4379 [1 << 17]byte var x4380 [1 << 17]byte var x4381 [1 << 17]byte var x4382 [1 << 17]byte var x4383 [1 << 17]byte var x4384 [1 << 17]byte var x4385 [1 << 17]byte var x4386 [1 << 17]byte var x4387 [1 << 17]byte var x4388 [1 << 17]byte var x4389 [1 << 17]byte var x4390 [1 << 17]byte var x4391 [1 << 17]byte var x4392 [1 << 17]byte var x4393 [1 << 17]byte var x4394 [1 << 17]byte var x4395 [1 << 17]byte var x4396 [1 << 17]byte var x4397 [1 << 17]byte var x4398 [1 << 17]byte var x4399 [1 << 17]byte var x4400 [1 << 17]byte var x4401 [1 << 17]byte var x4402 [1 << 17]byte var x4403 [1 << 17]byte var x4404 [1 << 17]byte var x4405 [1 << 17]byte var x4406 [1 << 17]byte var x4407 [1 << 17]byte var x4408 [1 << 17]byte var x4409 [1 << 17]byte var x4410 [1 << 17]byte var x4411 [1 << 17]byte var x4412 [1 << 17]byte var x4413 [1 << 17]byte var x4414 [1 << 17]byte var x4415 [1 << 17]byte var x4416 [1 << 17]byte var x4417 [1 << 17]byte var x4418 [1 << 17]byte var x4419 [1 << 17]byte var x4420 [1 << 17]byte var x4421 [1 << 17]byte var x4422 [1 << 17]byte var x4423 [1 << 17]byte var x4424 [1 << 17]byte var x4425 [1 << 17]byte var x4426 [1 << 17]byte var x4427 [1 << 17]byte var x4428 [1 << 17]byte var x4429 [1 << 17]byte var x4430 [1 << 17]byte var x4431 [1 << 17]byte var x4432 [1 << 17]byte var x4433 [1 << 17]byte var x4434 [1 << 17]byte var x4435 [1 << 17]byte var x4436 [1 << 17]byte var x4437 [1 << 17]byte var x4438 [1 << 17]byte var x4439 [1 << 17]byte var x4440 [1 << 17]byte var x4441 [1 << 17]byte var x4442 [1 << 17]byte var x4443 [1 << 17]byte var x4444 [1 << 17]byte var x4445 [1 << 17]byte var x4446 [1 << 17]byte var x4447 [1 << 17]byte var x4448 [1 << 17]byte var x4449 [1 << 17]byte var x4450 [1 << 17]byte var x4451 [1 << 17]byte var x4452 [1 << 17]byte var x4453 [1 << 17]byte var x4454 [1 << 17]byte var x4455 [1 << 17]byte var x4456 [1 << 17]byte var x4457 [1 << 17]byte var x4458 [1 << 17]byte var x4459 [1 << 17]byte var x4460 [1 << 17]byte var x4461 [1 << 17]byte var x4462 [1 << 17]byte var x4463 [1 << 17]byte var x4464 [1 << 17]byte var x4465 [1 << 17]byte var x4466 [1 << 17]byte var x4467 [1 << 17]byte var x4468 [1 << 17]byte var x4469 [1 << 17]byte var x4470 [1 << 17]byte var x4471 [1 << 17]byte var x4472 [1 << 17]byte var x4473 [1 << 17]byte var x4474 [1 << 17]byte var x4475 [1 << 17]byte var x4476 [1 << 17]byte var x4477 [1 << 17]byte var x4478 [1 << 17]byte var x4479 [1 << 17]byte var x4480 [1 << 17]byte var x4481 [1 << 17]byte var x4482 [1 << 17]byte var x4483 [1 << 17]byte var x4484 [1 << 17]byte var x4485 [1 << 17]byte var x4486 [1 << 17]byte var x4487 [1 << 17]byte var x4488 [1 << 17]byte var x4489 [1 << 17]byte var x4490 [1 << 17]byte var x4491 [1 << 17]byte var x4492 [1 << 17]byte var x4493 [1 << 17]byte var x4494 [1 << 17]byte var x4495 [1 << 17]byte var x4496 [1 << 17]byte var x4497 [1 << 17]byte var x4498 [1 << 17]byte var x4499 [1 << 17]byte var x4500 [1 << 17]byte var x4501 [1 << 17]byte var x4502 [1 << 17]byte var x4503 [1 << 17]byte var x4504 [1 << 17]byte var x4505 [1 << 17]byte var x4506 [1 << 17]byte var x4507 [1 << 17]byte var x4508 [1 << 17]byte var x4509 [1 << 17]byte var x4510 [1 << 17]byte var x4511 [1 << 17]byte var x4512 [1 << 17]byte var x4513 [1 << 17]byte var x4514 [1 << 17]byte var x4515 [1 << 17]byte var x4516 [1 << 17]byte var x4517 [1 << 17]byte var x4518 [1 << 17]byte var x4519 [1 << 17]byte var x4520 [1 << 17]byte var x4521 [1 << 17]byte var x4522 [1 << 17]byte var x4523 [1 << 17]byte var x4524 [1 << 17]byte var x4525 [1 << 17]byte var x4526 [1 << 17]byte var x4527 [1 << 17]byte var x4528 [1 << 17]byte var x4529 [1 << 17]byte var x4530 [1 << 17]byte var x4531 [1 << 17]byte var x4532 [1 << 17]byte var x4533 [1 << 17]byte var x4534 [1 << 17]byte var x4535 [1 << 17]byte var x4536 [1 << 17]byte var x4537 [1 << 17]byte var x4538 [1 << 17]byte var x4539 [1 << 17]byte var x4540 [1 << 17]byte var x4541 [1 << 17]byte var x4542 [1 << 17]byte var x4543 [1 << 17]byte var x4544 [1 << 17]byte var x4545 [1 << 17]byte var x4546 [1 << 17]byte var x4547 [1 << 17]byte var x4548 [1 << 17]byte var x4549 [1 << 17]byte var x4550 [1 << 17]byte var x4551 [1 << 17]byte var x4552 [1 << 17]byte var x4553 [1 << 17]byte var x4554 [1 << 17]byte var x4555 [1 << 17]byte var x4556 [1 << 17]byte var x4557 [1 << 17]byte var x4558 [1 << 17]byte var x4559 [1 << 17]byte var x4560 [1 << 17]byte var x4561 [1 << 17]byte var x4562 [1 << 17]byte var x4563 [1 << 17]byte var x4564 [1 << 17]byte var x4565 [1 << 17]byte var x4566 [1 << 17]byte var x4567 [1 << 17]byte var x4568 [1 << 17]byte var x4569 [1 << 17]byte var x4570 [1 << 17]byte var x4571 [1 << 17]byte var x4572 [1 << 17]byte var x4573 [1 << 17]byte var x4574 [1 << 17]byte var x4575 [1 << 17]byte var x4576 [1 << 17]byte var x4577 [1 << 17]byte var x4578 [1 << 17]byte var x4579 [1 << 17]byte var x4580 [1 << 17]byte var x4581 [1 << 17]byte var x4582 [1 << 17]byte var x4583 [1 << 17]byte var x4584 [1 << 17]byte var x4585 [1 << 17]byte var x4586 [1 << 17]byte var x4587 [1 << 17]byte var x4588 [1 << 17]byte var x4589 [1 << 17]byte var x4590 [1 << 17]byte var x4591 [1 << 17]byte var x4592 [1 << 17]byte var x4593 [1 << 17]byte var x4594 [1 << 17]byte var x4595 [1 << 17]byte var x4596 [1 << 17]byte var x4597 [1 << 17]byte var x4598 [1 << 17]byte var x4599 [1 << 17]byte var x4600 [1 << 17]byte var x4601 [1 << 17]byte var x4602 [1 << 17]byte var x4603 [1 << 17]byte var x4604 [1 << 17]byte var x4605 [1 << 17]byte var x4606 [1 << 17]byte var x4607 [1 << 17]byte var x4608 [1 << 17]byte var x4609 [1 << 17]byte var x4610 [1 << 17]byte var x4611 [1 << 17]byte var x4612 [1 << 17]byte var x4613 [1 << 17]byte var x4614 [1 << 17]byte var x4615 [1 << 17]byte var x4616 [1 << 17]byte var x4617 [1 << 17]byte var x4618 [1 << 17]byte var x4619 [1 << 17]byte var x4620 [1 << 17]byte var x4621 [1 << 17]byte var x4622 [1 << 17]byte var x4623 [1 << 17]byte var x4624 [1 << 17]byte var x4625 [1 << 17]byte var x4626 [1 << 17]byte var x4627 [1 << 17]byte var x4628 [1 << 17]byte var x4629 [1 << 17]byte var x4630 [1 << 17]byte var x4631 [1 << 17]byte var x4632 [1 << 17]byte var x4633 [1 << 17]byte var x4634 [1 << 17]byte var x4635 [1 << 17]byte var x4636 [1 << 17]byte var x4637 [1 << 17]byte var x4638 [1 << 17]byte var x4639 [1 << 17]byte var x4640 [1 << 17]byte var x4641 [1 << 17]byte var x4642 [1 << 17]byte var x4643 [1 << 17]byte var x4644 [1 << 17]byte var x4645 [1 << 17]byte var x4646 [1 << 17]byte var x4647 [1 << 17]byte var x4648 [1 << 17]byte var x4649 [1 << 17]byte var x4650 [1 << 17]byte var x4651 [1 << 17]byte var x4652 [1 << 17]byte var x4653 [1 << 17]byte var x4654 [1 << 17]byte var x4655 [1 << 17]byte var x4656 [1 << 17]byte var x4657 [1 << 17]byte var x4658 [1 << 17]byte var x4659 [1 << 17]byte var x4660 [1 << 17]byte var x4661 [1 << 17]byte var x4662 [1 << 17]byte var x4663 [1 << 17]byte var x4664 [1 << 17]byte var x4665 [1 << 17]byte var x4666 [1 << 17]byte var x4667 [1 << 17]byte var x4668 [1 << 17]byte var x4669 [1 << 17]byte var x4670 [1 << 17]byte var x4671 [1 << 17]byte var x4672 [1 << 17]byte var x4673 [1 << 17]byte var x4674 [1 << 17]byte var x4675 [1 << 17]byte var x4676 [1 << 17]byte var x4677 [1 << 17]byte var x4678 [1 << 17]byte var x4679 [1 << 17]byte var x4680 [1 << 17]byte var x4681 [1 << 17]byte var x4682 [1 << 17]byte var x4683 [1 << 17]byte var x4684 [1 << 17]byte var x4685 [1 << 17]byte var x4686 [1 << 17]byte var x4687 [1 << 17]byte var x4688 [1 << 17]byte var x4689 [1 << 17]byte var x4690 [1 << 17]byte var x4691 [1 << 17]byte var x4692 [1 << 17]byte var x4693 [1 << 17]byte var x4694 [1 << 17]byte var x4695 [1 << 17]byte var x4696 [1 << 17]byte var x4697 [1 << 17]byte var x4698 [1 << 17]byte var x4699 [1 << 17]byte var x4700 [1 << 17]byte var x4701 [1 << 17]byte var x4702 [1 << 17]byte var x4703 [1 << 17]byte var x4704 [1 << 17]byte var x4705 [1 << 17]byte var x4706 [1 << 17]byte var x4707 [1 << 17]byte var x4708 [1 << 17]byte var x4709 [1 << 17]byte var x4710 [1 << 17]byte var x4711 [1 << 17]byte var x4712 [1 << 17]byte var x4713 [1 << 17]byte var x4714 [1 << 17]byte var x4715 [1 << 17]byte var x4716 [1 << 17]byte var x4717 [1 << 17]byte var x4718 [1 << 17]byte var x4719 [1 << 17]byte var x4720 [1 << 17]byte var x4721 [1 << 17]byte var x4722 [1 << 17]byte var x4723 [1 << 17]byte var x4724 [1 << 17]byte var x4725 [1 << 17]byte var x4726 [1 << 17]byte var x4727 [1 << 17]byte var x4728 [1 << 17]byte var x4729 [1 << 17]byte var x4730 [1 << 17]byte var x4731 [1 << 17]byte var x4732 [1 << 17]byte var x4733 [1 << 17]byte var x4734 [1 << 17]byte var x4735 [1 << 17]byte var x4736 [1 << 17]byte var x4737 [1 << 17]byte var x4738 [1 << 17]byte var x4739 [1 << 17]byte var x4740 [1 << 17]byte var x4741 [1 << 17]byte var x4742 [1 << 17]byte var x4743 [1 << 17]byte var x4744 [1 << 17]byte var x4745 [1 << 17]byte var x4746 [1 << 17]byte var x4747 [1 << 17]byte var x4748 [1 << 17]byte var x4749 [1 << 17]byte var x4750 [1 << 17]byte var x4751 [1 << 17]byte var x4752 [1 << 17]byte var x4753 [1 << 17]byte var x4754 [1 << 17]byte var x4755 [1 << 17]byte var x4756 [1 << 17]byte var x4757 [1 << 17]byte var x4758 [1 << 17]byte var x4759 [1 << 17]byte var x4760 [1 << 17]byte var x4761 [1 << 17]byte var x4762 [1 << 17]byte var x4763 [1 << 17]byte var x4764 [1 << 17]byte var x4765 [1 << 17]byte var x4766 [1 << 17]byte var x4767 [1 << 17]byte var x4768 [1 << 17]byte var x4769 [1 << 17]byte var x4770 [1 << 17]byte var x4771 [1 << 17]byte var x4772 [1 << 17]byte var x4773 [1 << 17]byte var x4774 [1 << 17]byte var x4775 [1 << 17]byte var x4776 [1 << 17]byte var x4777 [1 << 17]byte var x4778 [1 << 17]byte var x4779 [1 << 17]byte var x4780 [1 << 17]byte var x4781 [1 << 17]byte var x4782 [1 << 17]byte var x4783 [1 << 17]byte var x4784 [1 << 17]byte var x4785 [1 << 17]byte var x4786 [1 << 17]byte var x4787 [1 << 17]byte var x4788 [1 << 17]byte var x4789 [1 << 17]byte var x4790 [1 << 17]byte var x4791 [1 << 17]byte var x4792 [1 << 17]byte var x4793 [1 << 17]byte var x4794 [1 << 17]byte var x4795 [1 << 17]byte var x4796 [1 << 17]byte var x4797 [1 << 17]byte var x4798 [1 << 17]byte var x4799 [1 << 17]byte var x4800 [1 << 17]byte var x4801 [1 << 17]byte var x4802 [1 << 17]byte var x4803 [1 << 17]byte var x4804 [1 << 17]byte var x4805 [1 << 17]byte var x4806 [1 << 17]byte var x4807 [1 << 17]byte var x4808 [1 << 17]byte var x4809 [1 << 17]byte var x4810 [1 << 17]byte var x4811 [1 << 17]byte var x4812 [1 << 17]byte var x4813 [1 << 17]byte var x4814 [1 << 17]byte var x4815 [1 << 17]byte var x4816 [1 << 17]byte var x4817 [1 << 17]byte var x4818 [1 << 17]byte var x4819 [1 << 17]byte var x4820 [1 << 17]byte var x4821 [1 << 17]byte var x4822 [1 << 17]byte var x4823 [1 << 17]byte var x4824 [1 << 17]byte var x4825 [1 << 17]byte var x4826 [1 << 17]byte var x4827 [1 << 17]byte var x4828 [1 << 17]byte var x4829 [1 << 17]byte var x4830 [1 << 17]byte var x4831 [1 << 17]byte var x4832 [1 << 17]byte var x4833 [1 << 17]byte var x4834 [1 << 17]byte var x4835 [1 << 17]byte var x4836 [1 << 17]byte var x4837 [1 << 17]byte var x4838 [1 << 17]byte var x4839 [1 << 17]byte var x4840 [1 << 17]byte var x4841 [1 << 17]byte var x4842 [1 << 17]byte var x4843 [1 << 17]byte var x4844 [1 << 17]byte var x4845 [1 << 17]byte var x4846 [1 << 17]byte var x4847 [1 << 17]byte var x4848 [1 << 17]byte var x4849 [1 << 17]byte var x4850 [1 << 17]byte var x4851 [1 << 17]byte var x4852 [1 << 17]byte var x4853 [1 << 17]byte var x4854 [1 << 17]byte var x4855 [1 << 17]byte var x4856 [1 << 17]byte var x4857 [1 << 17]byte var x4858 [1 << 17]byte var x4859 [1 << 17]byte var x4860 [1 << 17]byte var x4861 [1 << 17]byte var x4862 [1 << 17]byte var x4863 [1 << 17]byte var x4864 [1 << 17]byte var x4865 [1 << 17]byte var x4866 [1 << 17]byte var x4867 [1 << 17]byte var x4868 [1 << 17]byte var x4869 [1 << 17]byte var x4870 [1 << 17]byte var x4871 [1 << 17]byte var x4872 [1 << 17]byte var x4873 [1 << 17]byte var x4874 [1 << 17]byte var x4875 [1 << 17]byte var x4876 [1 << 17]byte var x4877 [1 << 17]byte var x4878 [1 << 17]byte var x4879 [1 << 17]byte var x4880 [1 << 17]byte var x4881 [1 << 17]byte var x4882 [1 << 17]byte var x4883 [1 << 17]byte var x4884 [1 << 17]byte var x4885 [1 << 17]byte var x4886 [1 << 17]byte var x4887 [1 << 17]byte var x4888 [1 << 17]byte var x4889 [1 << 17]byte var x4890 [1 << 17]byte var x4891 [1 << 17]byte var x4892 [1 << 17]byte var x4893 [1 << 17]byte var x4894 [1 << 17]byte var x4895 [1 << 17]byte var x4896 [1 << 17]byte var x4897 [1 << 17]byte var x4898 [1 << 17]byte var x4899 [1 << 17]byte var x4900 [1 << 17]byte var x4901 [1 << 17]byte var x4902 [1 << 17]byte var x4903 [1 << 17]byte var x4904 [1 << 17]byte var x4905 [1 << 17]byte var x4906 [1 << 17]byte var x4907 [1 << 17]byte var x4908 [1 << 17]byte var x4909 [1 << 17]byte var x4910 [1 << 17]byte var x4911 [1 << 17]byte var x4912 [1 << 17]byte var x4913 [1 << 17]byte var x4914 [1 << 17]byte var x4915 [1 << 17]byte var x4916 [1 << 17]byte var x4917 [1 << 17]byte var x4918 [1 << 17]byte var x4919 [1 << 17]byte var x4920 [1 << 17]byte var x4921 [1 << 17]byte var x4922 [1 << 17]byte var x4923 [1 << 17]byte var x4924 [1 << 17]byte var x4925 [1 << 17]byte var x4926 [1 << 17]byte var x4927 [1 << 17]byte var x4928 [1 << 17]byte var x4929 [1 << 17]byte var x4930 [1 << 17]byte var x4931 [1 << 17]byte var x4932 [1 << 17]byte var x4933 [1 << 17]byte var x4934 [1 << 17]byte var x4935 [1 << 17]byte var x4936 [1 << 17]byte var x4937 [1 << 17]byte var x4938 [1 << 17]byte var x4939 [1 << 17]byte var x4940 [1 << 17]byte var x4941 [1 << 17]byte var x4942 [1 << 17]byte var x4943 [1 << 17]byte var x4944 [1 << 17]byte var x4945 [1 << 17]byte var x4946 [1 << 17]byte var x4947 [1 << 17]byte var x4948 [1 << 17]byte var x4949 [1 << 17]byte var x4950 [1 << 17]byte var x4951 [1 << 17]byte var x4952 [1 << 17]byte var x4953 [1 << 17]byte var x4954 [1 << 17]byte var x4955 [1 << 17]byte var x4956 [1 << 17]byte var x4957 [1 << 17]byte var x4958 [1 << 17]byte var x4959 [1 << 17]byte var x4960 [1 << 17]byte var x4961 [1 << 17]byte var x4962 [1 << 17]byte var x4963 [1 << 17]byte var x4964 [1 << 17]byte var x4965 [1 << 17]byte var x4966 [1 << 17]byte var x4967 [1 << 17]byte var x4968 [1 << 17]byte var x4969 [1 << 17]byte var x4970 [1 << 17]byte var x4971 [1 << 17]byte var x4972 [1 << 17]byte var x4973 [1 << 17]byte var x4974 [1 << 17]byte var x4975 [1 << 17]byte var x4976 [1 << 17]byte var x4977 [1 << 17]byte var x4978 [1 << 17]byte var x4979 [1 << 17]byte var x4980 [1 << 17]byte var x4981 [1 << 17]byte var x4982 [1 << 17]byte var x4983 [1 << 17]byte var x4984 [1 << 17]byte var x4985 [1 << 17]byte var x4986 [1 << 17]byte var x4987 [1 << 17]byte var x4988 [1 << 17]byte var x4989 [1 << 17]byte var x4990 [1 << 17]byte var x4991 [1 << 17]byte var x4992 [1 << 17]byte var x4993 [1 << 17]byte var x4994 [1 << 17]byte var x4995 [1 << 17]byte var x4996 [1 << 17]byte var x4997 [1 << 17]byte var x4998 [1 << 17]byte var x4999 [1 << 17]byte var x5000 [1 << 17]byte var x5001 [1 << 17]byte var x5002 [1 << 17]byte var x5003 [1 << 17]byte var x5004 [1 << 17]byte var x5005 [1 << 17]byte var x5006 [1 << 17]byte var x5007 [1 << 17]byte var x5008 [1 << 17]byte var x5009 [1 << 17]byte var x5010 [1 << 17]byte var x5011 [1 << 17]byte var x5012 [1 << 17]byte var x5013 [1 << 17]byte var x5014 [1 << 17]byte var x5015 [1 << 17]byte var x5016 [1 << 17]byte var x5017 [1 << 17]byte var x5018 [1 << 17]byte var x5019 [1 << 17]byte var x5020 [1 << 17]byte var x5021 [1 << 17]byte var x5022 [1 << 17]byte var x5023 [1 << 17]byte var x5024 [1 << 17]byte var x5025 [1 << 17]byte var x5026 [1 << 17]byte var x5027 [1 << 17]byte var x5028 [1 << 17]byte var x5029 [1 << 17]byte var x5030 [1 << 17]byte var x5031 [1 << 17]byte var x5032 [1 << 17]byte var x5033 [1 << 17]byte var x5034 [1 << 17]byte var x5035 [1 << 17]byte var x5036 [1 << 17]byte var x5037 [1 << 17]byte var x5038 [1 << 17]byte var x5039 [1 << 17]byte var x5040 [1 << 17]byte var x5041 [1 << 17]byte var x5042 [1 << 17]byte var x5043 [1 << 17]byte var x5044 [1 << 17]byte var x5045 [1 << 17]byte var x5046 [1 << 17]byte var x5047 [1 << 17]byte var x5048 [1 << 17]byte var x5049 [1 << 17]byte var x5050 [1 << 17]byte var x5051 [1 << 17]byte var x5052 [1 << 17]byte var x5053 [1 << 17]byte var x5054 [1 << 17]byte var x5055 [1 << 17]byte var x5056 [1 << 17]byte var x5057 [1 << 17]byte var x5058 [1 << 17]byte var x5059 [1 << 17]byte var x5060 [1 << 17]byte var x5061 [1 << 17]byte var x5062 [1 << 17]byte var x5063 [1 << 17]byte var x5064 [1 << 17]byte var x5065 [1 << 17]byte var x5066 [1 << 17]byte var x5067 [1 << 17]byte var x5068 [1 << 17]byte var x5069 [1 << 17]byte var x5070 [1 << 17]byte var x5071 [1 << 17]byte var x5072 [1 << 17]byte var x5073 [1 << 17]byte var x5074 [1 << 17]byte var x5075 [1 << 17]byte var x5076 [1 << 17]byte var x5077 [1 << 17]byte var x5078 [1 << 17]byte var x5079 [1 << 17]byte var x5080 [1 << 17]byte var x5081 [1 << 17]byte var x5082 [1 << 17]byte var x5083 [1 << 17]byte var x5084 [1 << 17]byte var x5085 [1 << 17]byte var x5086 [1 << 17]byte var x5087 [1 << 17]byte var x5088 [1 << 17]byte var x5089 [1 << 17]byte var x5090 [1 << 17]byte var x5091 [1 << 17]byte var x5092 [1 << 17]byte var x5093 [1 << 17]byte var x5094 [1 << 17]byte var x5095 [1 << 17]byte var x5096 [1 << 17]byte var x5097 [1 << 17]byte var x5098 [1 << 17]byte var x5099 [1 << 17]byte var x5100 [1 << 17]byte var x5101 [1 << 17]byte var x5102 [1 << 17]byte var x5103 [1 << 17]byte var x5104 [1 << 17]byte var x5105 [1 << 17]byte var x5106 [1 << 17]byte var x5107 [1 << 17]byte var x5108 [1 << 17]byte var x5109 [1 << 17]byte var x5110 [1 << 17]byte var x5111 [1 << 17]byte var x5112 [1 << 17]byte var x5113 [1 << 17]byte var x5114 [1 << 17]byte var x5115 [1 << 17]byte var x5116 [1 << 17]byte var x5117 [1 << 17]byte var x5118 [1 << 17]byte var x5119 [1 << 17]byte var x5120 [1 << 17]byte var x5121 [1 << 17]byte var x5122 [1 << 17]byte var x5123 [1 << 17]byte var x5124 [1 << 17]byte var x5125 [1 << 17]byte var x5126 [1 << 17]byte var x5127 [1 << 17]byte var x5128 [1 << 17]byte var x5129 [1 << 17]byte var x5130 [1 << 17]byte var x5131 [1 << 17]byte var x5132 [1 << 17]byte var x5133 [1 << 17]byte var x5134 [1 << 17]byte var x5135 [1 << 17]byte var x5136 [1 << 17]byte var x5137 [1 << 17]byte var x5138 [1 << 17]byte var x5139 [1 << 17]byte var x5140 [1 << 17]byte var x5141 [1 << 17]byte var x5142 [1 << 17]byte var x5143 [1 << 17]byte var x5144 [1 << 17]byte var x5145 [1 << 17]byte var x5146 [1 << 17]byte var x5147 [1 << 17]byte var x5148 [1 << 17]byte var x5149 [1 << 17]byte var x5150 [1 << 17]byte var x5151 [1 << 17]byte var x5152 [1 << 17]byte var x5153 [1 << 17]byte var x5154 [1 << 17]byte var x5155 [1 << 17]byte var x5156 [1 << 17]byte var x5157 [1 << 17]byte var x5158 [1 << 17]byte var x5159 [1 << 17]byte var x5160 [1 << 17]byte var x5161 [1 << 17]byte var x5162 [1 << 17]byte var x5163 [1 << 17]byte var x5164 [1 << 17]byte var x5165 [1 << 17]byte var x5166 [1 << 17]byte var x5167 [1 << 17]byte var x5168 [1 << 17]byte var x5169 [1 << 17]byte var x5170 [1 << 17]byte var x5171 [1 << 17]byte var x5172 [1 << 17]byte var x5173 [1 << 17]byte var x5174 [1 << 17]byte var x5175 [1 << 17]byte var x5176 [1 << 17]byte var x5177 [1 << 17]byte var x5178 [1 << 17]byte var x5179 [1 << 17]byte var x5180 [1 << 17]byte var x5181 [1 << 17]byte var x5182 [1 << 17]byte var x5183 [1 << 17]byte var x5184 [1 << 17]byte var x5185 [1 << 17]byte var x5186 [1 << 17]byte var x5187 [1 << 17]byte var x5188 [1 << 17]byte var x5189 [1 << 17]byte var x5190 [1 << 17]byte var x5191 [1 << 17]byte var x5192 [1 << 17]byte var x5193 [1 << 17]byte var x5194 [1 << 17]byte var x5195 [1 << 17]byte var x5196 [1 << 17]byte var x5197 [1 << 17]byte var x5198 [1 << 17]byte var x5199 [1 << 17]byte var x5200 [1 << 17]byte var x5201 [1 << 17]byte var x5202 [1 << 17]byte var x5203 [1 << 17]byte var x5204 [1 << 17]byte var x5205 [1 << 17]byte var x5206 [1 << 17]byte var x5207 [1 << 17]byte var x5208 [1 << 17]byte var x5209 [1 << 17]byte var x5210 [1 << 17]byte var x5211 [1 << 17]byte var x5212 [1 << 17]byte var x5213 [1 << 17]byte var x5214 [1 << 17]byte var x5215 [1 << 17]byte var x5216 [1 << 17]byte var x5217 [1 << 17]byte var x5218 [1 << 17]byte var x5219 [1 << 17]byte var x5220 [1 << 17]byte var x5221 [1 << 17]byte var x5222 [1 << 17]byte var x5223 [1 << 17]byte var x5224 [1 << 17]byte var x5225 [1 << 17]byte var x5226 [1 << 17]byte var x5227 [1 << 17]byte var x5228 [1 << 17]byte var x5229 [1 << 17]byte var x5230 [1 << 17]byte var x5231 [1 << 17]byte var x5232 [1 << 17]byte var x5233 [1 << 17]byte var x5234 [1 << 17]byte var x5235 [1 << 17]byte var x5236 [1 << 17]byte var x5237 [1 << 17]byte var x5238 [1 << 17]byte var x5239 [1 << 17]byte var x5240 [1 << 17]byte var x5241 [1 << 17]byte var x5242 [1 << 17]byte var x5243 [1 << 17]byte var x5244 [1 << 17]byte var x5245 [1 << 17]byte var x5246 [1 << 17]byte var x5247 [1 << 17]byte var x5248 [1 << 17]byte var x5249 [1 << 17]byte var x5250 [1 << 17]byte var x5251 [1 << 17]byte var x5252 [1 << 17]byte var x5253 [1 << 17]byte var x5254 [1 << 17]byte var x5255 [1 << 17]byte var x5256 [1 << 17]byte var x5257 [1 << 17]byte var x5258 [1 << 17]byte var x5259 [1 << 17]byte var x5260 [1 << 17]byte var x5261 [1 << 17]byte var x5262 [1 << 17]byte var x5263 [1 << 17]byte var x5264 [1 << 17]byte var x5265 [1 << 17]byte var x5266 [1 << 17]byte var x5267 [1 << 17]byte var x5268 [1 << 17]byte var x5269 [1 << 17]byte var x5270 [1 << 17]byte var x5271 [1 << 17]byte var x5272 [1 << 17]byte var x5273 [1 << 17]byte var x5274 [1 << 17]byte var x5275 [1 << 17]byte var x5276 [1 << 17]byte var x5277 [1 << 17]byte var x5278 [1 << 17]byte var x5279 [1 << 17]byte var x5280 [1 << 17]byte var x5281 [1 << 17]byte var x5282 [1 << 17]byte var x5283 [1 << 17]byte var x5284 [1 << 17]byte var x5285 [1 << 17]byte var x5286 [1 << 17]byte var x5287 [1 << 17]byte var x5288 [1 << 17]byte var x5289 [1 << 17]byte var x5290 [1 << 17]byte var x5291 [1 << 17]byte var x5292 [1 << 17]byte var x5293 [1 << 17]byte var x5294 [1 << 17]byte var x5295 [1 << 17]byte var x5296 [1 << 17]byte var x5297 [1 << 17]byte var x5298 [1 << 17]byte var x5299 [1 << 17]byte var x5300 [1 << 17]byte var x5301 [1 << 17]byte var x5302 [1 << 17]byte var x5303 [1 << 17]byte var x5304 [1 << 17]byte var x5305 [1 << 17]byte var x5306 [1 << 17]byte var x5307 [1 << 17]byte var x5308 [1 << 17]byte var x5309 [1 << 17]byte var x5310 [1 << 17]byte var x5311 [1 << 17]byte var x5312 [1 << 17]byte var x5313 [1 << 17]byte var x5314 [1 << 17]byte var x5315 [1 << 17]byte var x5316 [1 << 17]byte var x5317 [1 << 17]byte var x5318 [1 << 17]byte var x5319 [1 << 17]byte var x5320 [1 << 17]byte var x5321 [1 << 17]byte var x5322 [1 << 17]byte var x5323 [1 << 17]byte var x5324 [1 << 17]byte var x5325 [1 << 17]byte var x5326 [1 << 17]byte var x5327 [1 << 17]byte var x5328 [1 << 17]byte var x5329 [1 << 17]byte var x5330 [1 << 17]byte var x5331 [1 << 17]byte var x5332 [1 << 17]byte var x5333 [1 << 17]byte var x5334 [1 << 17]byte var x5335 [1 << 17]byte var x5336 [1 << 17]byte var x5337 [1 << 17]byte var x5338 [1 << 17]byte var x5339 [1 << 17]byte var x5340 [1 << 17]byte var x5341 [1 << 17]byte var x5342 [1 << 17]byte var x5343 [1 << 17]byte var x5344 [1 << 17]byte var x5345 [1 << 17]byte var x5346 [1 << 17]byte var x5347 [1 << 17]byte var x5348 [1 << 17]byte var x5349 [1 << 17]byte var x5350 [1 << 17]byte var x5351 [1 << 17]byte var x5352 [1 << 17]byte var x5353 [1 << 17]byte var x5354 [1 << 17]byte var x5355 [1 << 17]byte var x5356 [1 << 17]byte var x5357 [1 << 17]byte var x5358 [1 << 17]byte var x5359 [1 << 17]byte var x5360 [1 << 17]byte var x5361 [1 << 17]byte var x5362 [1 << 17]byte var x5363 [1 << 17]byte var x5364 [1 << 17]byte var x5365 [1 << 17]byte var x5366 [1 << 17]byte var x5367 [1 << 17]byte var x5368 [1 << 17]byte var x5369 [1 << 17]byte var x5370 [1 << 17]byte var x5371 [1 << 17]byte var x5372 [1 << 17]byte var x5373 [1 << 17]byte var x5374 [1 << 17]byte var x5375 [1 << 17]byte var x5376 [1 << 17]byte var x5377 [1 << 17]byte var x5378 [1 << 17]byte var x5379 [1 << 17]byte var x5380 [1 << 17]byte var x5381 [1 << 17]byte var x5382 [1 << 17]byte var x5383 [1 << 17]byte var x5384 [1 << 17]byte var x5385 [1 << 17]byte var x5386 [1 << 17]byte var x5387 [1 << 17]byte var x5388 [1 << 17]byte var x5389 [1 << 17]byte var x5390 [1 << 17]byte var x5391 [1 << 17]byte var x5392 [1 << 17]byte var x5393 [1 << 17]byte var x5394 [1 << 17]byte var x5395 [1 << 17]byte var x5396 [1 << 17]byte var x5397 [1 << 17]byte var x5398 [1 << 17]byte var x5399 [1 << 17]byte var x5400 [1 << 17]byte var x5401 [1 << 17]byte var x5402 [1 << 17]byte var x5403 [1 << 17]byte var x5404 [1 << 17]byte var x5405 [1 << 17]byte var x5406 [1 << 17]byte var x5407 [1 << 17]byte var x5408 [1 << 17]byte var x5409 [1 << 17]byte var x5410 [1 << 17]byte var x5411 [1 << 17]byte var x5412 [1 << 17]byte var x5413 [1 << 17]byte var x5414 [1 << 17]byte var x5415 [1 << 17]byte var x5416 [1 << 17]byte var x5417 [1 << 17]byte var x5418 [1 << 17]byte var x5419 [1 << 17]byte var x5420 [1 << 17]byte var x5421 [1 << 17]byte var x5422 [1 << 17]byte var x5423 [1 << 17]byte var x5424 [1 << 17]byte var x5425 [1 << 17]byte var x5426 [1 << 17]byte var x5427 [1 << 17]byte var x5428 [1 << 17]byte var x5429 [1 << 17]byte var x5430 [1 << 17]byte var x5431 [1 << 17]byte var x5432 [1 << 17]byte var x5433 [1 << 17]byte var x5434 [1 << 17]byte var x5435 [1 << 17]byte var x5436 [1 << 17]byte var x5437 [1 << 17]byte var x5438 [1 << 17]byte var x5439 [1 << 17]byte var x5440 [1 << 17]byte var x5441 [1 << 17]byte var x5442 [1 << 17]byte var x5443 [1 << 17]byte var x5444 [1 << 17]byte var x5445 [1 << 17]byte var x5446 [1 << 17]byte var x5447 [1 << 17]byte var x5448 [1 << 17]byte var x5449 [1 << 17]byte var x5450 [1 << 17]byte var x5451 [1 << 17]byte var x5452 [1 << 17]byte var x5453 [1 << 17]byte var x5454 [1 << 17]byte var x5455 [1 << 17]byte var x5456 [1 << 17]byte var x5457 [1 << 17]byte var x5458 [1 << 17]byte var x5459 [1 << 17]byte var x5460 [1 << 17]byte var x5461 [1 << 17]byte var x5462 [1 << 17]byte var x5463 [1 << 17]byte var x5464 [1 << 17]byte var x5465 [1 << 17]byte var x5466 [1 << 17]byte var x5467 [1 << 17]byte var x5468 [1 << 17]byte var x5469 [1 << 17]byte var x5470 [1 << 17]byte var x5471 [1 << 17]byte var x5472 [1 << 17]byte var x5473 [1 << 17]byte var x5474 [1 << 17]byte var x5475 [1 << 17]byte var x5476 [1 << 17]byte var x5477 [1 << 17]byte var x5478 [1 << 17]byte var x5479 [1 << 17]byte var x5480 [1 << 17]byte var x5481 [1 << 17]byte var x5482 [1 << 17]byte var x5483 [1 << 17]byte var x5484 [1 << 17]byte var x5485 [1 << 17]byte var x5486 [1 << 17]byte var x5487 [1 << 17]byte var x5488 [1 << 17]byte var x5489 [1 << 17]byte var x5490 [1 << 17]byte var x5491 [1 << 17]byte var x5492 [1 << 17]byte var x5493 [1 << 17]byte var x5494 [1 << 17]byte var x5495 [1 << 17]byte var x5496 [1 << 17]byte var x5497 [1 << 17]byte var x5498 [1 << 17]byte var x5499 [1 << 17]byte var x5500 [1 << 17]byte var x5501 [1 << 17]byte var x5502 [1 << 17]byte var x5503 [1 << 17]byte var x5504 [1 << 17]byte var x5505 [1 << 17]byte var x5506 [1 << 17]byte var x5507 [1 << 17]byte var x5508 [1 << 17]byte var x5509 [1 << 17]byte var x5510 [1 << 17]byte var x5511 [1 << 17]byte var x5512 [1 << 17]byte var x5513 [1 << 17]byte var x5514 [1 << 17]byte var x5515 [1 << 17]byte var x5516 [1 << 17]byte var x5517 [1 << 17]byte var x5518 [1 << 17]byte var x5519 [1 << 17]byte var x5520 [1 << 17]byte var x5521 [1 << 17]byte var x5522 [1 << 17]byte var x5523 [1 << 17]byte var x5524 [1 << 17]byte var x5525 [1 << 17]byte var x5526 [1 << 17]byte var x5527 [1 << 17]byte var x5528 [1 << 17]byte var x5529 [1 << 17]byte var x5530 [1 << 17]byte var x5531 [1 << 17]byte var x5532 [1 << 17]byte var x5533 [1 << 17]byte var x5534 [1 << 17]byte var x5535 [1 << 17]byte var x5536 [1 << 17]byte var x5537 [1 << 17]byte var x5538 [1 << 17]byte var x5539 [1 << 17]byte var x5540 [1 << 17]byte var x5541 [1 << 17]byte var x5542 [1 << 17]byte var x5543 [1 << 17]byte var x5544 [1 << 17]byte var x5545 [1 << 17]byte var x5546 [1 << 17]byte var x5547 [1 << 17]byte var x5548 [1 << 17]byte var x5549 [1 << 17]byte var x5550 [1 << 17]byte var x5551 [1 << 17]byte var x5552 [1 << 17]byte var x5553 [1 << 17]byte var x5554 [1 << 17]byte var x5555 [1 << 17]byte var x5556 [1 << 17]byte var x5557 [1 << 17]byte var x5558 [1 << 17]byte var x5559 [1 << 17]byte var x5560 [1 << 17]byte var x5561 [1 << 17]byte var x5562 [1 << 17]byte var x5563 [1 << 17]byte var x5564 [1 << 17]byte var x5565 [1 << 17]byte var x5566 [1 << 17]byte var x5567 [1 << 17]byte var x5568 [1 << 17]byte var x5569 [1 << 17]byte var x5570 [1 << 17]byte var x5571 [1 << 17]byte var x5572 [1 << 17]byte var x5573 [1 << 17]byte var x5574 [1 << 17]byte var x5575 [1 << 17]byte var x5576 [1 << 17]byte var x5577 [1 << 17]byte var x5578 [1 << 17]byte var x5579 [1 << 17]byte var x5580 [1 << 17]byte var x5581 [1 << 17]byte var x5582 [1 << 17]byte var x5583 [1 << 17]byte var x5584 [1 << 17]byte var x5585 [1 << 17]byte var x5586 [1 << 17]byte var x5587 [1 << 17]byte var x5588 [1 << 17]byte var x5589 [1 << 17]byte var x5590 [1 << 17]byte var x5591 [1 << 17]byte var x5592 [1 << 17]byte var x5593 [1 << 17]byte var x5594 [1 << 17]byte var x5595 [1 << 17]byte var x5596 [1 << 17]byte var x5597 [1 << 17]byte var x5598 [1 << 17]byte var x5599 [1 << 17]byte var x5600 [1 << 17]byte var x5601 [1 << 17]byte var x5602 [1 << 17]byte var x5603 [1 << 17]byte var x5604 [1 << 17]byte var x5605 [1 << 17]byte var x5606 [1 << 17]byte var x5607 [1 << 17]byte var x5608 [1 << 17]byte var x5609 [1 << 17]byte var x5610 [1 << 17]byte var x5611 [1 << 17]byte var x5612 [1 << 17]byte var x5613 [1 << 17]byte var x5614 [1 << 17]byte var x5615 [1 << 17]byte var x5616 [1 << 17]byte var x5617 [1 << 17]byte var x5618 [1 << 17]byte var x5619 [1 << 17]byte var x5620 [1 << 17]byte var x5621 [1 << 17]byte var x5622 [1 << 17]byte var x5623 [1 << 17]byte var x5624 [1 << 17]byte var x5625 [1 << 17]byte var x5626 [1 << 17]byte var x5627 [1 << 17]byte var x5628 [1 << 17]byte var x5629 [1 << 17]byte var x5630 [1 << 17]byte var x5631 [1 << 17]byte var x5632 [1 << 17]byte var x5633 [1 << 17]byte var x5634 [1 << 17]byte var x5635 [1 << 17]byte var x5636 [1 << 17]byte var x5637 [1 << 17]byte var x5638 [1 << 17]byte var x5639 [1 << 17]byte var x5640 [1 << 17]byte var x5641 [1 << 17]byte var x5642 [1 << 17]byte var x5643 [1 << 17]byte var x5644 [1 << 17]byte var x5645 [1 << 17]byte var x5646 [1 << 17]byte var x5647 [1 << 17]byte var x5648 [1 << 17]byte var x5649 [1 << 17]byte var x5650 [1 << 17]byte var x5651 [1 << 17]byte var x5652 [1 << 17]byte var x5653 [1 << 17]byte var x5654 [1 << 17]byte var x5655 [1 << 17]byte var x5656 [1 << 17]byte var x5657 [1 << 17]byte var x5658 [1 << 17]byte var x5659 [1 << 17]byte var x5660 [1 << 17]byte var x5661 [1 << 17]byte var x5662 [1 << 17]byte var x5663 [1 << 17]byte var x5664 [1 << 17]byte var x5665 [1 << 17]byte var x5666 [1 << 17]byte var x5667 [1 << 17]byte var x5668 [1 << 17]byte var x5669 [1 << 17]byte var x5670 [1 << 17]byte var x5671 [1 << 17]byte var x5672 [1 << 17]byte var x5673 [1 << 17]byte var x5674 [1 << 17]byte var x5675 [1 << 17]byte var x5676 [1 << 17]byte var x5677 [1 << 17]byte var x5678 [1 << 17]byte var x5679 [1 << 17]byte var x5680 [1 << 17]byte var x5681 [1 << 17]byte var x5682 [1 << 17]byte var x5683 [1 << 17]byte var x5684 [1 << 17]byte var x5685 [1 << 17]byte var x5686 [1 << 17]byte var x5687 [1 << 17]byte var x5688 [1 << 17]byte var x5689 [1 << 17]byte var x5690 [1 << 17]byte var x5691 [1 << 17]byte var x5692 [1 << 17]byte var x5693 [1 << 17]byte var x5694 [1 << 17]byte var x5695 [1 << 17]byte var x5696 [1 << 17]byte var x5697 [1 << 17]byte var x5698 [1 << 17]byte var x5699 [1 << 17]byte var x5700 [1 << 17]byte var x5701 [1 << 17]byte var x5702 [1 << 17]byte var x5703 [1 << 17]byte var x5704 [1 << 17]byte var x5705 [1 << 17]byte var x5706 [1 << 17]byte var x5707 [1 << 17]byte var x5708 [1 << 17]byte var x5709 [1 << 17]byte var x5710 [1 << 17]byte var x5711 [1 << 17]byte var x5712 [1 << 17]byte var x5713 [1 << 17]byte var x5714 [1 << 17]byte var x5715 [1 << 17]byte var x5716 [1 << 17]byte var x5717 [1 << 17]byte var x5718 [1 << 17]byte var x5719 [1 << 17]byte var x5720 [1 << 17]byte var x5721 [1 << 17]byte var x5722 [1 << 17]byte var x5723 [1 << 17]byte var x5724 [1 << 17]byte var x5725 [1 << 17]byte var x5726 [1 << 17]byte var x5727 [1 << 17]byte var x5728 [1 << 17]byte var x5729 [1 << 17]byte var x5730 [1 << 17]byte var x5731 [1 << 17]byte var x5732 [1 << 17]byte var x5733 [1 << 17]byte var x5734 [1 << 17]byte var x5735 [1 << 17]byte var x5736 [1 << 17]byte var x5737 [1 << 17]byte var x5738 [1 << 17]byte var x5739 [1 << 17]byte var x5740 [1 << 17]byte var x5741 [1 << 17]byte var x5742 [1 << 17]byte var x5743 [1 << 17]byte var x5744 [1 << 17]byte var x5745 [1 << 17]byte var x5746 [1 << 17]byte var x5747 [1 << 17]byte var x5748 [1 << 17]byte var x5749 [1 << 17]byte var x5750 [1 << 17]byte var x5751 [1 << 17]byte var x5752 [1 << 17]byte var x5753 [1 << 17]byte var x5754 [1 << 17]byte var x5755 [1 << 17]byte var x5756 [1 << 17]byte var x5757 [1 << 17]byte var x5758 [1 << 17]byte var x5759 [1 << 17]byte var x5760 [1 << 17]byte var x5761 [1 << 17]byte var x5762 [1 << 17]byte var x5763 [1 << 17]byte var x5764 [1 << 17]byte var x5765 [1 << 17]byte var x5766 [1 << 17]byte var x5767 [1 << 17]byte var x5768 [1 << 17]byte var x5769 [1 << 17]byte var x5770 [1 << 17]byte var x5771 [1 << 17]byte var x5772 [1 << 17]byte var x5773 [1 << 17]byte var x5774 [1 << 17]byte var x5775 [1 << 17]byte var x5776 [1 << 17]byte var x5777 [1 << 17]byte var x5778 [1 << 17]byte var x5779 [1 << 17]byte var x5780 [1 << 17]byte var x5781 [1 << 17]byte var x5782 [1 << 17]byte var x5783 [1 << 17]byte var x5784 [1 << 17]byte var x5785 [1 << 17]byte var x5786 [1 << 17]byte var x5787 [1 << 17]byte var x5788 [1 << 17]byte var x5789 [1 << 17]byte var x5790 [1 << 17]byte var x5791 [1 << 17]byte var x5792 [1 << 17]byte var x5793 [1 << 17]byte var x5794 [1 << 17]byte var x5795 [1 << 17]byte var x5796 [1 << 17]byte var x5797 [1 << 17]byte var x5798 [1 << 17]byte var x5799 [1 << 17]byte var x5800 [1 << 17]byte var x5801 [1 << 17]byte var x5802 [1 << 17]byte var x5803 [1 << 17]byte var x5804 [1 << 17]byte var x5805 [1 << 17]byte var x5806 [1 << 17]byte var x5807 [1 << 17]byte var x5808 [1 << 17]byte var x5809 [1 << 17]byte var x5810 [1 << 17]byte var x5811 [1 << 17]byte var x5812 [1 << 17]byte var x5813 [1 << 17]byte var x5814 [1 << 17]byte var x5815 [1 << 17]byte var x5816 [1 << 17]byte var x5817 [1 << 17]byte var x5818 [1 << 17]byte var x5819 [1 << 17]byte var x5820 [1 << 17]byte var x5821 [1 << 17]byte var x5822 [1 << 17]byte var x5823 [1 << 17]byte var x5824 [1 << 17]byte var x5825 [1 << 17]byte var x5826 [1 << 17]byte var x5827 [1 << 17]byte var x5828 [1 << 17]byte var x5829 [1 << 17]byte var x5830 [1 << 17]byte var x5831 [1 << 17]byte var x5832 [1 << 17]byte var x5833 [1 << 17]byte var x5834 [1 << 17]byte var x5835 [1 << 17]byte var x5836 [1 << 17]byte var x5837 [1 << 17]byte var x5838 [1 << 17]byte var x5839 [1 << 17]byte var x5840 [1 << 17]byte var x5841 [1 << 17]byte var x5842 [1 << 17]byte var x5843 [1 << 17]byte var x5844 [1 << 17]byte var x5845 [1 << 17]byte var x5846 [1 << 17]byte var x5847 [1 << 17]byte var x5848 [1 << 17]byte var x5849 [1 << 17]byte var x5850 [1 << 17]byte var x5851 [1 << 17]byte var x5852 [1 << 17]byte var x5853 [1 << 17]byte var x5854 [1 << 17]byte var x5855 [1 << 17]byte var x5856 [1 << 17]byte var x5857 [1 << 17]byte var x5858 [1 << 17]byte var x5859 [1 << 17]byte var x5860 [1 << 17]byte var x5861 [1 << 17]byte var x5862 [1 << 17]byte var x5863 [1 << 17]byte var x5864 [1 << 17]byte var x5865 [1 << 17]byte var x5866 [1 << 17]byte var x5867 [1 << 17]byte var x5868 [1 << 17]byte var x5869 [1 << 17]byte var x5870 [1 << 17]byte var x5871 [1 << 17]byte var x5872 [1 << 17]byte var x5873 [1 << 17]byte var x5874 [1 << 17]byte var x5875 [1 << 17]byte var x5876 [1 << 17]byte var x5877 [1 << 17]byte var x5878 [1 << 17]byte var x5879 [1 << 17]byte var x5880 [1 << 17]byte var x5881 [1 << 17]byte var x5882 [1 << 17]byte var x5883 [1 << 17]byte var x5884 [1 << 17]byte var x5885 [1 << 17]byte var x5886 [1 << 17]byte var x5887 [1 << 17]byte var x5888 [1 << 17]byte var x5889 [1 << 17]byte var x5890 [1 << 17]byte var x5891 [1 << 17]byte var x5892 [1 << 17]byte var x5893 [1 << 17]byte var x5894 [1 << 17]byte var x5895 [1 << 17]byte var x5896 [1 << 17]byte var x5897 [1 << 17]byte var x5898 [1 << 17]byte var x5899 [1 << 17]byte var x5900 [1 << 17]byte var x5901 [1 << 17]byte var x5902 [1 << 17]byte var x5903 [1 << 17]byte var x5904 [1 << 17]byte var x5905 [1 << 17]byte var x5906 [1 << 17]byte var x5907 [1 << 17]byte var x5908 [1 << 17]byte var x5909 [1 << 17]byte var x5910 [1 << 17]byte var x5911 [1 << 17]byte var x5912 [1 << 17]byte var x5913 [1 << 17]byte var x5914 [1 << 17]byte var x5915 [1 << 17]byte var x5916 [1 << 17]byte var x5917 [1 << 17]byte var x5918 [1 << 17]byte var x5919 [1 << 17]byte var x5920 [1 << 17]byte var x5921 [1 << 17]byte var x5922 [1 << 17]byte var x5923 [1 << 17]byte var x5924 [1 << 17]byte var x5925 [1 << 17]byte var x5926 [1 << 17]byte var x5927 [1 << 17]byte var x5928 [1 << 17]byte var x5929 [1 << 17]byte var x5930 [1 << 17]byte var x5931 [1 << 17]byte var x5932 [1 << 17]byte var x5933 [1 << 17]byte var x5934 [1 << 17]byte var x5935 [1 << 17]byte var x5936 [1 << 17]byte var x5937 [1 << 17]byte var x5938 [1 << 17]byte var x5939 [1 << 17]byte var x5940 [1 << 17]byte var x5941 [1 << 17]byte var x5942 [1 << 17]byte var x5943 [1 << 17]byte var x5944 [1 << 17]byte var x5945 [1 << 17]byte var x5946 [1 << 17]byte var x5947 [1 << 17]byte var x5948 [1 << 17]byte var x5949 [1 << 17]byte var x5950 [1 << 17]byte var x5951 [1 << 17]byte var x5952 [1 << 17]byte var x5953 [1 << 17]byte var x5954 [1 << 17]byte var x5955 [1 << 17]byte var x5956 [1 << 17]byte var x5957 [1 << 17]byte var x5958 [1 << 17]byte var x5959 [1 << 17]byte var x5960 [1 << 17]byte var x5961 [1 << 17]byte var x5962 [1 << 17]byte var x5963 [1 << 17]byte var x5964 [1 << 17]byte var x5965 [1 << 17]byte var x5966 [1 << 17]byte var x5967 [1 << 17]byte var x5968 [1 << 17]byte var x5969 [1 << 17]byte var x5970 [1 << 17]byte var x5971 [1 << 17]byte var x5972 [1 << 17]byte var x5973 [1 << 17]byte var x5974 [1 << 17]byte var x5975 [1 << 17]byte var x5976 [1 << 17]byte var x5977 [1 << 17]byte var x5978 [1 << 17]byte var x5979 [1 << 17]byte var x5980 [1 << 17]byte var x5981 [1 << 17]byte var x5982 [1 << 17]byte var x5983 [1 << 17]byte var x5984 [1 << 17]byte var x5985 [1 << 17]byte var x5986 [1 << 17]byte var x5987 [1 << 17]byte var x5988 [1 << 17]byte var x5989 [1 << 17]byte var x5990 [1 << 17]byte var x5991 [1 << 17]byte var x5992 [1 << 17]byte var x5993 [1 << 17]byte var x5994 [1 << 17]byte var x5995 [1 << 17]byte var x5996 [1 << 17]byte var x5997 [1 << 17]byte var x5998 [1 << 17]byte var x5999 [1 << 17]byte var x6000 [1 << 17]byte var x6001 [1 << 17]byte var x6002 [1 << 17]byte var x6003 [1 << 17]byte var x6004 [1 << 17]byte var x6005 [1 << 17]byte var x6006 [1 << 17]byte var x6007 [1 << 17]byte var x6008 [1 << 17]byte var x6009 [1 << 17]byte var x6010 [1 << 17]byte var x6011 [1 << 17]byte var x6012 [1 << 17]byte var x6013 [1 << 17]byte var x6014 [1 << 17]byte var x6015 [1 << 17]byte var x6016 [1 << 17]byte var x6017 [1 << 17]byte var x6018 [1 << 17]byte var x6019 [1 << 17]byte var x6020 [1 << 17]byte var x6021 [1 << 17]byte var x6022 [1 << 17]byte var x6023 [1 << 17]byte var x6024 [1 << 17]byte var x6025 [1 << 17]byte var x6026 [1 << 17]byte var x6027 [1 << 17]byte var x6028 [1 << 17]byte var x6029 [1 << 17]byte var x6030 [1 << 17]byte var x6031 [1 << 17]byte var x6032 [1 << 17]byte var x6033 [1 << 17]byte var x6034 [1 << 17]byte var x6035 [1 << 17]byte var x6036 [1 << 17]byte var x6037 [1 << 17]byte var x6038 [1 << 17]byte var x6039 [1 << 17]byte var x6040 [1 << 17]byte var x6041 [1 << 17]byte var x6042 [1 << 17]byte var x6043 [1 << 17]byte var x6044 [1 << 17]byte var x6045 [1 << 17]byte var x6046 [1 << 17]byte var x6047 [1 << 17]byte var x6048 [1 << 17]byte var x6049 [1 << 17]byte var x6050 [1 << 17]byte var x6051 [1 << 17]byte var x6052 [1 << 17]byte var x6053 [1 << 17]byte var x6054 [1 << 17]byte var x6055 [1 << 17]byte var x6056 [1 << 17]byte var x6057 [1 << 17]byte var x6058 [1 << 17]byte var x6059 [1 << 17]byte var x6060 [1 << 17]byte var x6061 [1 << 17]byte var x6062 [1 << 17]byte var x6063 [1 << 17]byte var x6064 [1 << 17]byte var x6065 [1 << 17]byte var x6066 [1 << 17]byte var x6067 [1 << 17]byte var x6068 [1 << 17]byte var x6069 [1 << 17]byte var x6070 [1 << 17]byte var x6071 [1 << 17]byte var x6072 [1 << 17]byte var x6073 [1 << 17]byte var x6074 [1 << 17]byte var x6075 [1 << 17]byte var x6076 [1 << 17]byte var x6077 [1 << 17]byte var x6078 [1 << 17]byte var x6079 [1 << 17]byte var x6080 [1 << 17]byte var x6081 [1 << 17]byte var x6082 [1 << 17]byte var x6083 [1 << 17]byte var x6084 [1 << 17]byte var x6085 [1 << 17]byte var x6086 [1 << 17]byte var x6087 [1 << 17]byte var x6088 [1 << 17]byte var x6089 [1 << 17]byte var x6090 [1 << 17]byte var x6091 [1 << 17]byte var x6092 [1 << 17]byte var x6093 [1 << 17]byte var x6094 [1 << 17]byte var x6095 [1 << 17]byte var x6096 [1 << 17]byte var x6097 [1 << 17]byte var x6098 [1 << 17]byte var x6099 [1 << 17]byte var x6100 [1 << 17]byte var x6101 [1 << 17]byte var x6102 [1 << 17]byte var x6103 [1 << 17]byte var x6104 [1 << 17]byte var x6105 [1 << 17]byte var x6106 [1 << 17]byte var x6107 [1 << 17]byte var x6108 [1 << 17]byte var x6109 [1 << 17]byte var x6110 [1 << 17]byte var x6111 [1 << 17]byte var x6112 [1 << 17]byte var x6113 [1 << 17]byte var x6114 [1 << 17]byte var x6115 [1 << 17]byte var x6116 [1 << 17]byte var x6117 [1 << 17]byte var x6118 [1 << 17]byte var x6119 [1 << 17]byte var x6120 [1 << 17]byte var x6121 [1 << 17]byte var x6122 [1 << 17]byte var x6123 [1 << 17]byte var x6124 [1 << 17]byte var x6125 [1 << 17]byte var x6126 [1 << 17]byte var x6127 [1 << 17]byte var x6128 [1 << 17]byte var x6129 [1 << 17]byte var x6130 [1 << 17]byte var x6131 [1 << 17]byte var x6132 [1 << 17]byte var x6133 [1 << 17]byte var x6134 [1 << 17]byte var x6135 [1 << 17]byte var x6136 [1 << 17]byte var x6137 [1 << 17]byte var x6138 [1 << 17]byte var x6139 [1 << 17]byte var x6140 [1 << 17]byte var x6141 [1 << 17]byte var x6142 [1 << 17]byte var x6143 [1 << 17]byte var x6144 [1 << 17]byte var x6145 [1 << 17]byte var x6146 [1 << 17]byte var x6147 [1 << 17]byte var x6148 [1 << 17]byte var x6149 [1 << 17]byte var x6150 [1 << 17]byte var x6151 [1 << 17]byte var x6152 [1 << 17]byte var x6153 [1 << 17]byte var x6154 [1 << 17]byte var x6155 [1 << 17]byte var x6156 [1 << 17]byte var x6157 [1 << 17]byte var x6158 [1 << 17]byte var x6159 [1 << 17]byte var x6160 [1 << 17]byte var x6161 [1 << 17]byte var x6162 [1 << 17]byte var x6163 [1 << 17]byte var x6164 [1 << 17]byte var x6165 [1 << 17]byte var x6166 [1 << 17]byte var x6167 [1 << 17]byte var x6168 [1 << 17]byte var x6169 [1 << 17]byte var x6170 [1 << 17]byte var x6171 [1 << 17]byte var x6172 [1 << 17]byte var x6173 [1 << 17]byte var x6174 [1 << 17]byte var x6175 [1 << 17]byte var x6176 [1 << 17]byte var x6177 [1 << 17]byte var x6178 [1 << 17]byte var x6179 [1 << 17]byte var x6180 [1 << 17]byte var x6181 [1 << 17]byte var x6182 [1 << 17]byte var x6183 [1 << 17]byte var x6184 [1 << 17]byte var x6185 [1 << 17]byte var x6186 [1 << 17]byte var x6187 [1 << 17]byte var x6188 [1 << 17]byte var x6189 [1 << 17]byte var x6190 [1 << 17]byte var x6191 [1 << 17]byte var x6192 [1 << 17]byte var x6193 [1 << 17]byte var x6194 [1 << 17]byte var x6195 [1 << 17]byte var x6196 [1 << 17]byte var x6197 [1 << 17]byte var x6198 [1 << 17]byte var x6199 [1 << 17]byte var x6200 [1 << 17]byte var x6201 [1 << 17]byte var x6202 [1 << 17]byte var x6203 [1 << 17]byte var x6204 [1 << 17]byte var x6205 [1 << 17]byte var x6206 [1 << 17]byte var x6207 [1 << 17]byte var x6208 [1 << 17]byte var x6209 [1 << 17]byte var x6210 [1 << 17]byte var x6211 [1 << 17]byte var x6212 [1 << 17]byte var x6213 [1 << 17]byte var x6214 [1 << 17]byte var x6215 [1 << 17]byte var x6216 [1 << 17]byte var x6217 [1 << 17]byte var x6218 [1 << 17]byte var x6219 [1 << 17]byte var x6220 [1 << 17]byte var x6221 [1 << 17]byte var x6222 [1 << 17]byte var x6223 [1 << 17]byte var x6224 [1 << 17]byte var x6225 [1 << 17]byte var x6226 [1 << 17]byte var x6227 [1 << 17]byte var x6228 [1 << 17]byte var x6229 [1 << 17]byte var x6230 [1 << 17]byte var x6231 [1 << 17]byte var x6232 [1 << 17]byte var x6233 [1 << 17]byte var x6234 [1 << 17]byte var x6235 [1 << 17]byte var x6236 [1 << 17]byte var x6237 [1 << 17]byte var x6238 [1 << 17]byte var x6239 [1 << 17]byte var x6240 [1 << 17]byte var x6241 [1 << 17]byte var x6242 [1 << 17]byte var x6243 [1 << 17]byte var x6244 [1 << 17]byte var x6245 [1 << 17]byte var x6246 [1 << 17]byte var x6247 [1 << 17]byte var x6248 [1 << 17]byte var x6249 [1 << 17]byte var x6250 [1 << 17]byte var x6251 [1 << 17]byte var x6252 [1 << 17]byte var x6253 [1 << 17]byte var x6254 [1 << 17]byte var x6255 [1 << 17]byte var x6256 [1 << 17]byte var x6257 [1 << 17]byte var x6258 [1 << 17]byte var x6259 [1 << 17]byte var x6260 [1 << 17]byte var x6261 [1 << 17]byte var x6262 [1 << 17]byte var x6263 [1 << 17]byte var x6264 [1 << 17]byte var x6265 [1 << 17]byte var x6266 [1 << 17]byte var x6267 [1 << 17]byte var x6268 [1 << 17]byte var x6269 [1 << 17]byte var x6270 [1 << 17]byte var x6271 [1 << 17]byte var x6272 [1 << 17]byte var x6273 [1 << 17]byte var x6274 [1 << 17]byte var x6275 [1 << 17]byte var x6276 [1 << 17]byte var x6277 [1 << 17]byte var x6278 [1 << 17]byte var x6279 [1 << 17]byte var x6280 [1 << 17]byte var x6281 [1 << 17]byte var x6282 [1 << 17]byte var x6283 [1 << 17]byte var x6284 [1 << 17]byte var x6285 [1 << 17]byte var x6286 [1 << 17]byte var x6287 [1 << 17]byte var x6288 [1 << 17]byte var x6289 [1 << 17]byte var x6290 [1 << 17]byte var x6291 [1 << 17]byte var x6292 [1 << 17]byte var x6293 [1 << 17]byte var x6294 [1 << 17]byte var x6295 [1 << 17]byte var x6296 [1 << 17]byte var x6297 [1 << 17]byte var x6298 [1 << 17]byte var x6299 [1 << 17]byte var x6300 [1 << 17]byte var x6301 [1 << 17]byte var x6302 [1 << 17]byte var x6303 [1 << 17]byte var x6304 [1 << 17]byte var x6305 [1 << 17]byte var x6306 [1 << 17]byte var x6307 [1 << 17]byte var x6308 [1 << 17]byte var x6309 [1 << 17]byte var x6310 [1 << 17]byte var x6311 [1 << 17]byte var x6312 [1 << 17]byte var x6313 [1 << 17]byte var x6314 [1 << 17]byte var x6315 [1 << 17]byte var x6316 [1 << 17]byte var x6317 [1 << 17]byte var x6318 [1 << 17]byte var x6319 [1 << 17]byte var x6320 [1 << 17]byte var x6321 [1 << 17]byte var x6322 [1 << 17]byte var x6323 [1 << 17]byte var x6324 [1 << 17]byte var x6325 [1 << 17]byte var x6326 [1 << 17]byte var x6327 [1 << 17]byte var x6328 [1 << 17]byte var x6329 [1 << 17]byte var x6330 [1 << 17]byte var x6331 [1 << 17]byte var x6332 [1 << 17]byte var x6333 [1 << 17]byte var x6334 [1 << 17]byte var x6335 [1 << 17]byte var x6336 [1 << 17]byte var x6337 [1 << 17]byte var x6338 [1 << 17]byte var x6339 [1 << 17]byte var x6340 [1 << 17]byte var x6341 [1 << 17]byte var x6342 [1 << 17]byte var x6343 [1 << 17]byte var x6344 [1 << 17]byte var x6345 [1 << 17]byte var x6346 [1 << 17]byte var x6347 [1 << 17]byte var x6348 [1 << 17]byte var x6349 [1 << 17]byte var x6350 [1 << 17]byte var x6351 [1 << 17]byte var x6352 [1 << 17]byte var x6353 [1 << 17]byte var x6354 [1 << 17]byte var x6355 [1 << 17]byte var x6356 [1 << 17]byte var x6357 [1 << 17]byte var x6358 [1 << 17]byte var x6359 [1 << 17]byte var x6360 [1 << 17]byte var x6361 [1 << 17]byte var x6362 [1 << 17]byte var x6363 [1 << 17]byte var x6364 [1 << 17]byte var x6365 [1 << 17]byte var x6366 [1 << 17]byte var x6367 [1 << 17]byte var x6368 [1 << 17]byte var x6369 [1 << 17]byte var x6370 [1 << 17]byte var x6371 [1 << 17]byte var x6372 [1 << 17]byte var x6373 [1 << 17]byte var x6374 [1 << 17]byte var x6375 [1 << 17]byte var x6376 [1 << 17]byte var x6377 [1 << 17]byte var x6378 [1 << 17]byte var x6379 [1 << 17]byte var x6380 [1 << 17]byte var x6381 [1 << 17]byte var x6382 [1 << 17]byte var x6383 [1 << 17]byte var x6384 [1 << 17]byte var x6385 [1 << 17]byte var x6386 [1 << 17]byte var x6387 [1 << 17]byte var x6388 [1 << 17]byte var x6389 [1 << 17]byte var x6390 [1 << 17]byte var x6391 [1 << 17]byte var x6392 [1 << 17]byte var x6393 [1 << 17]byte var x6394 [1 << 17]byte var x6395 [1 << 17]byte var x6396 [1 << 17]byte var x6397 [1 << 17]byte var x6398 [1 << 17]byte var x6399 [1 << 17]byte var x6400 [1 << 17]byte var x6401 [1 << 17]byte var x6402 [1 << 17]byte var x6403 [1 << 17]byte var x6404 [1 << 17]byte var x6405 [1 << 17]byte var x6406 [1 << 17]byte var x6407 [1 << 17]byte var x6408 [1 << 17]byte var x6409 [1 << 17]byte var x6410 [1 << 17]byte var x6411 [1 << 17]byte var x6412 [1 << 17]byte var x6413 [1 << 17]byte var x6414 [1 << 17]byte var x6415 [1 << 17]byte var x6416 [1 << 17]byte var x6417 [1 << 17]byte var x6418 [1 << 17]byte var x6419 [1 << 17]byte var x6420 [1 << 17]byte var x6421 [1 << 17]byte var x6422 [1 << 17]byte var x6423 [1 << 17]byte var x6424 [1 << 17]byte var x6425 [1 << 17]byte var x6426 [1 << 17]byte var x6427 [1 << 17]byte var x6428 [1 << 17]byte var x6429 [1 << 17]byte var x6430 [1 << 17]byte var x6431 [1 << 17]byte var x6432 [1 << 17]byte var x6433 [1 << 17]byte var x6434 [1 << 17]byte var x6435 [1 << 17]byte var x6436 [1 << 17]byte var x6437 [1 << 17]byte var x6438 [1 << 17]byte var x6439 [1 << 17]byte var x6440 [1 << 17]byte var x6441 [1 << 17]byte var x6442 [1 << 17]byte var x6443 [1 << 17]byte var x6444 [1 << 17]byte var x6445 [1 << 17]byte var x6446 [1 << 17]byte var x6447 [1 << 17]byte var x6448 [1 << 17]byte var x6449 [1 << 17]byte var x6450 [1 << 17]byte var x6451 [1 << 17]byte var x6452 [1 << 17]byte var x6453 [1 << 17]byte var x6454 [1 << 17]byte var x6455 [1 << 17]byte var x6456 [1 << 17]byte var x6457 [1 << 17]byte var x6458 [1 << 17]byte var x6459 [1 << 17]byte var x6460 [1 << 17]byte var x6461 [1 << 17]byte var x6462 [1 << 17]byte var x6463 [1 << 17]byte var x6464 [1 << 17]byte var x6465 [1 << 17]byte var x6466 [1 << 17]byte var x6467 [1 << 17]byte var x6468 [1 << 17]byte var x6469 [1 << 17]byte var x6470 [1 << 17]byte var x6471 [1 << 17]byte var x6472 [1 << 17]byte var x6473 [1 << 17]byte var x6474 [1 << 17]byte var x6475 [1 << 17]byte var x6476 [1 << 17]byte var x6477 [1 << 17]byte var x6478 [1 << 17]byte var x6479 [1 << 17]byte var x6480 [1 << 17]byte var x6481 [1 << 17]byte var x6482 [1 << 17]byte var x6483 [1 << 17]byte var x6484 [1 << 17]byte var x6485 [1 << 17]byte var x6486 [1 << 17]byte var x6487 [1 << 17]byte var x6488 [1 << 17]byte var x6489 [1 << 17]byte var x6490 [1 << 17]byte var x6491 [1 << 17]byte var x6492 [1 << 17]byte var x6493 [1 << 17]byte var x6494 [1 << 17]byte var x6495 [1 << 17]byte var x6496 [1 << 17]byte var x6497 [1 << 17]byte var x6498 [1 << 17]byte var x6499 [1 << 17]byte var x6500 [1 << 17]byte var x6501 [1 << 17]byte var x6502 [1 << 17]byte var x6503 [1 << 17]byte var x6504 [1 << 17]byte var x6505 [1 << 17]byte var x6506 [1 << 17]byte var x6507 [1 << 17]byte var x6508 [1 << 17]byte var x6509 [1 << 17]byte var x6510 [1 << 17]byte var x6511 [1 << 17]byte var x6512 [1 << 17]byte var x6513 [1 << 17]byte var x6514 [1 << 17]byte var x6515 [1 << 17]byte var x6516 [1 << 17]byte var x6517 [1 << 17]byte var x6518 [1 << 17]byte var x6519 [1 << 17]byte var x6520 [1 << 17]byte var x6521 [1 << 17]byte var x6522 [1 << 17]byte var x6523 [1 << 17]byte var x6524 [1 << 17]byte var x6525 [1 << 17]byte var x6526 [1 << 17]byte var x6527 [1 << 17]byte var x6528 [1 << 17]byte var x6529 [1 << 17]byte var x6530 [1 << 17]byte var x6531 [1 << 17]byte var x6532 [1 << 17]byte var x6533 [1 << 17]byte var x6534 [1 << 17]byte var x6535 [1 << 17]byte var x6536 [1 << 17]byte var x6537 [1 << 17]byte var x6538 [1 << 17]byte var x6539 [1 << 17]byte var x6540 [1 << 17]byte var x6541 [1 << 17]byte var x6542 [1 << 17]byte var x6543 [1 << 17]byte var x6544 [1 << 17]byte var x6545 [1 << 17]byte var x6546 [1 << 17]byte var x6547 [1 << 17]byte var x6548 [1 << 17]byte var x6549 [1 << 17]byte var x6550 [1 << 17]byte var x6551 [1 << 17]byte var x6552 [1 << 17]byte var x6553 [1 << 17]byte var x6554 [1 << 17]byte var x6555 [1 << 17]byte var x6556 [1 << 17]byte var x6557 [1 << 17]byte var x6558 [1 << 17]byte var x6559 [1 << 17]byte var x6560 [1 << 17]byte var x6561 [1 << 17]byte var x6562 [1 << 17]byte var x6563 [1 << 17]byte var x6564 [1 << 17]byte var x6565 [1 << 17]byte var x6566 [1 << 17]byte var x6567 [1 << 17]byte var x6568 [1 << 17]byte var x6569 [1 << 17]byte var x6570 [1 << 17]byte var x6571 [1 << 17]byte var x6572 [1 << 17]byte var x6573 [1 << 17]byte var x6574 [1 << 17]byte var x6575 [1 << 17]byte var x6576 [1 << 17]byte var x6577 [1 << 17]byte var x6578 [1 << 17]byte var x6579 [1 << 17]byte var x6580 [1 << 17]byte var x6581 [1 << 17]byte var x6582 [1 << 17]byte var x6583 [1 << 17]byte var x6584 [1 << 17]byte var x6585 [1 << 17]byte var x6586 [1 << 17]byte var x6587 [1 << 17]byte var x6588 [1 << 17]byte var x6589 [1 << 17]byte var x6590 [1 << 17]byte var x6591 [1 << 17]byte var x6592 [1 << 17]byte var x6593 [1 << 17]byte var x6594 [1 << 17]byte var x6595 [1 << 17]byte var x6596 [1 << 17]byte var x6597 [1 << 17]byte var x6598 [1 << 17]byte var x6599 [1 << 17]byte var x6600 [1 << 17]byte var x6601 [1 << 17]byte var x6602 [1 << 17]byte var x6603 [1 << 17]byte var x6604 [1 << 17]byte var x6605 [1 << 17]byte var x6606 [1 << 17]byte var x6607 [1 << 17]byte var x6608 [1 << 17]byte var x6609 [1 << 17]byte var x6610 [1 << 17]byte var x6611 [1 << 17]byte var x6612 [1 << 17]byte var x6613 [1 << 17]byte var x6614 [1 << 17]byte var x6615 [1 << 17]byte var x6616 [1 << 17]byte var x6617 [1 << 17]byte var x6618 [1 << 17]byte var x6619 [1 << 17]byte var x6620 [1 << 17]byte var x6621 [1 << 17]byte var x6622 [1 << 17]byte var x6623 [1 << 17]byte var x6624 [1 << 17]byte var x6625 [1 << 17]byte var x6626 [1 << 17]byte var x6627 [1 << 17]byte var x6628 [1 << 17]byte var x6629 [1 << 17]byte var x6630 [1 << 17]byte var x6631 [1 << 17]byte var x6632 [1 << 17]byte var x6633 [1 << 17]byte var x6634 [1 << 17]byte var x6635 [1 << 17]byte var x6636 [1 << 17]byte var x6637 [1 << 17]byte var x6638 [1 << 17]byte var x6639 [1 << 17]byte var x6640 [1 << 17]byte var x6641 [1 << 17]byte var x6642 [1 << 17]byte var x6643 [1 << 17]byte var x6644 [1 << 17]byte var x6645 [1 << 17]byte var x6646 [1 << 17]byte var x6647 [1 << 17]byte var x6648 [1 << 17]byte var x6649 [1 << 17]byte var x6650 [1 << 17]byte var x6651 [1 << 17]byte var x6652 [1 << 17]byte var x6653 [1 << 17]byte var x6654 [1 << 17]byte var x6655 [1 << 17]byte var x6656 [1 << 17]byte var x6657 [1 << 17]byte var x6658 [1 << 17]byte var x6659 [1 << 17]byte var x6660 [1 << 17]byte var x6661 [1 << 17]byte var x6662 [1 << 17]byte var x6663 [1 << 17]byte var x6664 [1 << 17]byte var x6665 [1 << 17]byte var x6666 [1 << 17]byte var x6667 [1 << 17]byte var x6668 [1 << 17]byte var x6669 [1 << 17]byte var x6670 [1 << 17]byte var x6671 [1 << 17]byte var x6672 [1 << 17]byte var x6673 [1 << 17]byte var x6674 [1 << 17]byte var x6675 [1 << 17]byte var x6676 [1 << 17]byte var x6677 [1 << 17]byte var x6678 [1 << 17]byte var x6679 [1 << 17]byte var x6680 [1 << 17]byte var x6681 [1 << 17]byte var x6682 [1 << 17]byte var x6683 [1 << 17]byte var x6684 [1 << 17]byte var x6685 [1 << 17]byte var x6686 [1 << 17]byte var x6687 [1 << 17]byte var x6688 [1 << 17]byte var x6689 [1 << 17]byte var x6690 [1 << 17]byte var x6691 [1 << 17]byte var x6692 [1 << 17]byte var x6693 [1 << 17]byte var x6694 [1 << 17]byte var x6695 [1 << 17]byte var x6696 [1 << 17]byte var x6697 [1 << 17]byte var x6698 [1 << 17]byte var x6699 [1 << 17]byte var x6700 [1 << 17]byte var x6701 [1 << 17]byte var x6702 [1 << 17]byte var x6703 [1 << 17]byte var x6704 [1 << 17]byte var x6705 [1 << 17]byte var x6706 [1 << 17]byte var x6707 [1 << 17]byte var x6708 [1 << 17]byte var x6709 [1 << 17]byte var x6710 [1 << 17]byte var x6711 [1 << 17]byte var x6712 [1 << 17]byte var x6713 [1 << 17]byte var x6714 [1 << 17]byte var x6715 [1 << 17]byte var x6716 [1 << 17]byte var x6717 [1 << 17]byte var x6718 [1 << 17]byte var x6719 [1 << 17]byte var x6720 [1 << 17]byte var x6721 [1 << 17]byte var x6722 [1 << 17]byte var x6723 [1 << 17]byte var x6724 [1 << 17]byte var x6725 [1 << 17]byte var x6726 [1 << 17]byte var x6727 [1 << 17]byte var x6728 [1 << 17]byte var x6729 [1 << 17]byte var x6730 [1 << 17]byte var x6731 [1 << 17]byte var x6732 [1 << 17]byte var x6733 [1 << 17]byte var x6734 [1 << 17]byte var x6735 [1 << 17]byte var x6736 [1 << 17]byte var x6737 [1 << 17]byte var x6738 [1 << 17]byte var x6739 [1 << 17]byte var x6740 [1 << 17]byte var x6741 [1 << 17]byte var x6742 [1 << 17]byte var x6743 [1 << 17]byte var x6744 [1 << 17]byte var x6745 [1 << 17]byte var x6746 [1 << 17]byte var x6747 [1 << 17]byte var x6748 [1 << 17]byte var x6749 [1 << 17]byte var x6750 [1 << 17]byte var x6751 [1 << 17]byte var x6752 [1 << 17]byte var x6753 [1 << 17]byte var x6754 [1 << 17]byte var x6755 [1 << 17]byte var x6756 [1 << 17]byte var x6757 [1 << 17]byte var x6758 [1 << 17]byte var x6759 [1 << 17]byte var x6760 [1 << 17]byte var x6761 [1 << 17]byte var x6762 [1 << 17]byte var x6763 [1 << 17]byte var x6764 [1 << 17]byte var x6765 [1 << 17]byte var x6766 [1 << 17]byte var x6767 [1 << 17]byte var x6768 [1 << 17]byte var x6769 [1 << 17]byte var x6770 [1 << 17]byte var x6771 [1 << 17]byte var x6772 [1 << 17]byte var x6773 [1 << 17]byte var x6774 [1 << 17]byte var x6775 [1 << 17]byte var x6776 [1 << 17]byte var x6777 [1 << 17]byte var x6778 [1 << 17]byte var x6779 [1 << 17]byte var x6780 [1 << 17]byte var x6781 [1 << 17]byte var x6782 [1 << 17]byte var x6783 [1 << 17]byte var x6784 [1 << 17]byte var x6785 [1 << 17]byte var x6786 [1 << 17]byte var x6787 [1 << 17]byte var x6788 [1 << 17]byte var x6789 [1 << 17]byte var x6790 [1 << 17]byte var x6791 [1 << 17]byte var x6792 [1 << 17]byte var x6793 [1 << 17]byte var x6794 [1 << 17]byte var x6795 [1 << 17]byte var x6796 [1 << 17]byte var x6797 [1 << 17]byte var x6798 [1 << 17]byte var x6799 [1 << 17]byte var x6800 [1 << 17]byte var x6801 [1 << 17]byte var x6802 [1 << 17]byte var x6803 [1 << 17]byte var x6804 [1 << 17]byte var x6805 [1 << 17]byte var x6806 [1 << 17]byte var x6807 [1 << 17]byte var x6808 [1 << 17]byte var x6809 [1 << 17]byte var x6810 [1 << 17]byte var x6811 [1 << 17]byte var x6812 [1 << 17]byte var x6813 [1 << 17]byte var x6814 [1 << 17]byte var x6815 [1 << 17]byte var x6816 [1 << 17]byte var x6817 [1 << 17]byte var x6818 [1 << 17]byte var x6819 [1 << 17]byte var x6820 [1 << 17]byte var x6821 [1 << 17]byte var x6822 [1 << 17]byte var x6823 [1 << 17]byte var x6824 [1 << 17]byte var x6825 [1 << 17]byte var x6826 [1 << 17]byte var x6827 [1 << 17]byte var x6828 [1 << 17]byte var x6829 [1 << 17]byte var x6830 [1 << 17]byte var x6831 [1 << 17]byte var x6832 [1 << 17]byte var x6833 [1 << 17]byte var x6834 [1 << 17]byte var x6835 [1 << 17]byte var x6836 [1 << 17]byte var x6837 [1 << 17]byte var x6838 [1 << 17]byte var x6839 [1 << 17]byte var x6840 [1 << 17]byte var x6841 [1 << 17]byte var x6842 [1 << 17]byte var x6843 [1 << 17]byte var x6844 [1 << 17]byte var x6845 [1 << 17]byte var x6846 [1 << 17]byte var x6847 [1 << 17]byte var x6848 [1 << 17]byte var x6849 [1 << 17]byte var x6850 [1 << 17]byte var x6851 [1 << 17]byte var x6852 [1 << 17]byte var x6853 [1 << 17]byte var x6854 [1 << 17]byte var x6855 [1 << 17]byte var x6856 [1 << 17]byte var x6857 [1 << 17]byte var x6858 [1 << 17]byte var x6859 [1 << 17]byte var x6860 [1 << 17]byte var x6861 [1 << 17]byte var x6862 [1 << 17]byte var x6863 [1 << 17]byte var x6864 [1 << 17]byte var x6865 [1 << 17]byte var x6866 [1 << 17]byte var x6867 [1 << 17]byte var x6868 [1 << 17]byte var x6869 [1 << 17]byte var x6870 [1 << 17]byte var x6871 [1 << 17]byte var x6872 [1 << 17]byte var x6873 [1 << 17]byte var x6874 [1 << 17]byte var x6875 [1 << 17]byte var x6876 [1 << 17]byte var x6877 [1 << 17]byte var x6878 [1 << 17]byte var x6879 [1 << 17]byte var x6880 [1 << 17]byte var x6881 [1 << 17]byte var x6882 [1 << 17]byte var x6883 [1 << 17]byte var x6884 [1 << 17]byte var x6885 [1 << 17]byte var x6886 [1 << 17]byte var x6887 [1 << 17]byte var x6888 [1 << 17]byte var x6889 [1 << 17]byte var x6890 [1 << 17]byte var x6891 [1 << 17]byte var x6892 [1 << 17]byte var x6893 [1 << 17]byte var x6894 [1 << 17]byte var x6895 [1 << 17]byte var x6896 [1 << 17]byte var x6897 [1 << 17]byte var x6898 [1 << 17]byte var x6899 [1 << 17]byte var x6900 [1 << 17]byte var x6901 [1 << 17]byte var x6902 [1 << 17]byte var x6903 [1 << 17]byte var x6904 [1 << 17]byte var x6905 [1 << 17]byte var x6906 [1 << 17]byte var x6907 [1 << 17]byte var x6908 [1 << 17]byte var x6909 [1 << 17]byte var x6910 [1 << 17]byte var x6911 [1 << 17]byte var x6912 [1 << 17]byte var x6913 [1 << 17]byte var x6914 [1 << 17]byte var x6915 [1 << 17]byte var x6916 [1 << 17]byte var x6917 [1 << 17]byte var x6918 [1 << 17]byte var x6919 [1 << 17]byte var x6920 [1 << 17]byte var x6921 [1 << 17]byte var x6922 [1 << 17]byte var x6923 [1 << 17]byte var x6924 [1 << 17]byte var x6925 [1 << 17]byte var x6926 [1 << 17]byte var x6927 [1 << 17]byte var x6928 [1 << 17]byte var x6929 [1 << 17]byte var x6930 [1 << 17]byte var x6931 [1 << 17]byte var x6932 [1 << 17]byte var x6933 [1 << 17]byte var x6934 [1 << 17]byte var x6935 [1 << 17]byte var x6936 [1 << 17]byte var x6937 [1 << 17]byte var x6938 [1 << 17]byte var x6939 [1 << 17]byte var x6940 [1 << 17]byte var x6941 [1 << 17]byte var x6942 [1 << 17]byte var x6943 [1 << 17]byte var x6944 [1 << 17]byte var x6945 [1 << 17]byte var x6946 [1 << 17]byte var x6947 [1 << 17]byte var x6948 [1 << 17]byte var x6949 [1 << 17]byte var x6950 [1 << 17]byte var x6951 [1 << 17]byte var x6952 [1 << 17]byte var x6953 [1 << 17]byte var x6954 [1 << 17]byte var x6955 [1 << 17]byte var x6956 [1 << 17]byte var x6957 [1 << 17]byte var x6958 [1 << 17]byte var x6959 [1 << 17]byte var x6960 [1 << 17]byte var x6961 [1 << 17]byte var x6962 [1 << 17]byte var x6963 [1 << 17]byte var x6964 [1 << 17]byte var x6965 [1 << 17]byte var x6966 [1 << 17]byte var x6967 [1 << 17]byte var x6968 [1 << 17]byte var x6969 [1 << 17]byte var x6970 [1 << 17]byte var x6971 [1 << 17]byte var x6972 [1 << 17]byte var x6973 [1 << 17]byte var x6974 [1 << 17]byte var x6975 [1 << 17]byte var x6976 [1 << 17]byte var x6977 [1 << 17]byte var x6978 [1 << 17]byte var x6979 [1 << 17]byte var x6980 [1 << 17]byte var x6981 [1 << 17]byte var x6982 [1 << 17]byte var x6983 [1 << 17]byte var x6984 [1 << 17]byte var x6985 [1 << 17]byte var x6986 [1 << 17]byte var x6987 [1 << 17]byte var x6988 [1 << 17]byte var x6989 [1 << 17]byte var x6990 [1 << 17]byte var x6991 [1 << 17]byte var x6992 [1 << 17]byte var x6993 [1 << 17]byte var x6994 [1 << 17]byte var x6995 [1 << 17]byte var x6996 [1 << 17]byte var x6997 [1 << 17]byte var x6998 [1 << 17]byte var x6999 [1 << 17]byte var x7000 [1 << 17]byte var x7001 [1 << 17]byte var x7002 [1 << 17]byte var x7003 [1 << 17]byte var x7004 [1 << 17]byte var x7005 [1 << 17]byte var x7006 [1 << 17]byte var x7007 [1 << 17]byte var x7008 [1 << 17]byte var x7009 [1 << 17]byte var x7010 [1 << 17]byte var x7011 [1 << 17]byte var x7012 [1 << 17]byte var x7013 [1 << 17]byte var x7014 [1 << 17]byte var x7015 [1 << 17]byte var x7016 [1 << 17]byte var x7017 [1 << 17]byte var x7018 [1 << 17]byte var x7019 [1 << 17]byte var x7020 [1 << 17]byte var x7021 [1 << 17]byte var x7022 [1 << 17]byte var x7023 [1 << 17]byte var x7024 [1 << 17]byte var x7025 [1 << 17]byte var x7026 [1 << 17]byte var x7027 [1 << 17]byte var x7028 [1 << 17]byte var x7029 [1 << 17]byte var x7030 [1 << 17]byte var x7031 [1 << 17]byte var x7032 [1 << 17]byte var x7033 [1 << 17]byte var x7034 [1 << 17]byte var x7035 [1 << 17]byte var x7036 [1 << 17]byte var x7037 [1 << 17]byte var x7038 [1 << 17]byte var x7039 [1 << 17]byte var x7040 [1 << 17]byte var x7041 [1 << 17]byte var x7042 [1 << 17]byte var x7043 [1 << 17]byte var x7044 [1 << 17]byte var x7045 [1 << 17]byte var x7046 [1 << 17]byte var x7047 [1 << 17]byte var x7048 [1 << 17]byte var x7049 [1 << 17]byte var x7050 [1 << 17]byte var x7051 [1 << 17]byte var x7052 [1 << 17]byte var x7053 [1 << 17]byte var x7054 [1 << 17]byte var x7055 [1 << 17]byte var x7056 [1 << 17]byte var x7057 [1 << 17]byte var x7058 [1 << 17]byte var x7059 [1 << 17]byte var x7060 [1 << 17]byte var x7061 [1 << 17]byte var x7062 [1 << 17]byte var x7063 [1 << 17]byte var x7064 [1 << 17]byte var x7065 [1 << 17]byte var x7066 [1 << 17]byte var x7067 [1 << 17]byte var x7068 [1 << 17]byte var x7069 [1 << 17]byte var x7070 [1 << 17]byte var x7071 [1 << 17]byte var x7072 [1 << 17]byte var x7073 [1 << 17]byte var x7074 [1 << 17]byte var x7075 [1 << 17]byte var x7076 [1 << 17]byte var x7077 [1 << 17]byte var x7078 [1 << 17]byte var x7079 [1 << 17]byte var x7080 [1 << 17]byte var x7081 [1 << 17]byte var x7082 [1 << 17]byte var x7083 [1 << 17]byte var x7084 [1 << 17]byte var x7085 [1 << 17]byte var x7086 [1 << 17]byte var x7087 [1 << 17]byte var x7088 [1 << 17]byte var x7089 [1 << 17]byte var x7090 [1 << 17]byte var x7091 [1 << 17]byte var x7092 [1 << 17]byte var x7093 [1 << 17]byte var x7094 [1 << 17]byte var x7095 [1 << 17]byte var x7096 [1 << 17]byte var x7097 [1 << 17]byte var x7098 [1 << 17]byte var x7099 [1 << 17]byte var x7100 [1 << 17]byte var x7101 [1 << 17]byte var x7102 [1 << 17]byte var x7103 [1 << 17]byte var x7104 [1 << 17]byte var x7105 [1 << 17]byte var x7106 [1 << 17]byte var x7107 [1 << 17]byte var x7108 [1 << 17]byte var x7109 [1 << 17]byte var x7110 [1 << 17]byte var x7111 [1 << 17]byte var x7112 [1 << 17]byte var x7113 [1 << 17]byte var x7114 [1 << 17]byte var x7115 [1 << 17]byte var x7116 [1 << 17]byte var x7117 [1 << 17]byte var x7118 [1 << 17]byte var x7119 [1 << 17]byte var x7120 [1 << 17]byte var x7121 [1 << 17]byte var x7122 [1 << 17]byte var x7123 [1 << 17]byte var x7124 [1 << 17]byte var x7125 [1 << 17]byte var x7126 [1 << 17]byte var x7127 [1 << 17]byte var x7128 [1 << 17]byte var x7129 [1 << 17]byte var x7130 [1 << 17]byte var x7131 [1 << 17]byte var x7132 [1 << 17]byte var x7133 [1 << 17]byte var x7134 [1 << 17]byte var x7135 [1 << 17]byte var x7136 [1 << 17]byte var x7137 [1 << 17]byte var x7138 [1 << 17]byte var x7139 [1 << 17]byte var x7140 [1 << 17]byte var x7141 [1 << 17]byte var x7142 [1 << 17]byte var x7143 [1 << 17]byte var x7144 [1 << 17]byte var x7145 [1 << 17]byte var x7146 [1 << 17]byte var x7147 [1 << 17]byte var x7148 [1 << 17]byte var x7149 [1 << 17]byte var x7150 [1 << 17]byte var x7151 [1 << 17]byte var x7152 [1 << 17]byte var x7153 [1 << 17]byte var x7154 [1 << 17]byte var x7155 [1 << 17]byte var x7156 [1 << 17]byte var x7157 [1 << 17]byte var x7158 [1 << 17]byte var x7159 [1 << 17]byte var x7160 [1 << 17]byte var x7161 [1 << 17]byte var x7162 [1 << 17]byte var x7163 [1 << 17]byte var x7164 [1 << 17]byte var x7165 [1 << 17]byte var x7166 [1 << 17]byte var x7167 [1 << 17]byte var x7168 [1 << 17]byte var x7169 [1 << 17]byte var x7170 [1 << 17]byte var x7171 [1 << 17]byte var x7172 [1 << 17]byte var x7173 [1 << 17]byte var x7174 [1 << 17]byte var x7175 [1 << 17]byte var x7176 [1 << 17]byte var x7177 [1 << 17]byte var x7178 [1 << 17]byte var x7179 [1 << 17]byte var x7180 [1 << 17]byte var x7181 [1 << 17]byte var x7182 [1 << 17]byte var x7183 [1 << 17]byte var x7184 [1 << 17]byte var x7185 [1 << 17]byte var x7186 [1 << 17]byte var x7187 [1 << 17]byte var x7188 [1 << 17]byte var x7189 [1 << 17]byte var x7190 [1 << 17]byte var x7191 [1 << 17]byte var x7192 [1 << 17]byte var x7193 [1 << 17]byte var x7194 [1 << 17]byte var x7195 [1 << 17]byte var x7196 [1 << 17]byte var x7197 [1 << 17]byte var x7198 [1 << 17]byte var x7199 [1 << 17]byte var x7200 [1 << 17]byte var x7201 [1 << 17]byte var x7202 [1 << 17]byte var x7203 [1 << 17]byte var x7204 [1 << 17]byte var x7205 [1 << 17]byte var x7206 [1 << 17]byte var x7207 [1 << 17]byte var x7208 [1 << 17]byte var x7209 [1 << 17]byte var x7210 [1 << 17]byte var x7211 [1 << 17]byte var x7212 [1 << 17]byte var x7213 [1 << 17]byte var x7214 [1 << 17]byte var x7215 [1 << 17]byte var x7216 [1 << 17]byte var x7217 [1 << 17]byte var x7218 [1 << 17]byte var x7219 [1 << 17]byte var x7220 [1 << 17]byte var x7221 [1 << 17]byte var x7222 [1 << 17]byte var x7223 [1 << 17]byte var x7224 [1 << 17]byte var x7225 [1 << 17]byte var x7226 [1 << 17]byte var x7227 [1 << 17]byte var x7228 [1 << 17]byte var x7229 [1 << 17]byte var x7230 [1 << 17]byte var x7231 [1 << 17]byte var x7232 [1 << 17]byte var x7233 [1 << 17]byte var x7234 [1 << 17]byte var x7235 [1 << 17]byte var x7236 [1 << 17]byte var x7237 [1 << 17]byte var x7238 [1 << 17]byte var x7239 [1 << 17]byte var x7240 [1 << 17]byte var x7241 [1 << 17]byte var x7242 [1 << 17]byte var x7243 [1 << 17]byte var x7244 [1 << 17]byte var x7245 [1 << 17]byte var x7246 [1 << 17]byte var x7247 [1 << 17]byte var x7248 [1 << 17]byte var x7249 [1 << 17]byte var x7250 [1 << 17]byte var x7251 [1 << 17]byte var x7252 [1 << 17]byte var x7253 [1 << 17]byte var x7254 [1 << 17]byte var x7255 [1 << 17]byte var x7256 [1 << 17]byte var x7257 [1 << 17]byte var x7258 [1 << 17]byte var x7259 [1 << 17]byte var x7260 [1 << 17]byte var x7261 [1 << 17]byte var x7262 [1 << 17]byte var x7263 [1 << 17]byte var x7264 [1 << 17]byte var x7265 [1 << 17]byte var x7266 [1 << 17]byte var x7267 [1 << 17]byte var x7268 [1 << 17]byte var x7269 [1 << 17]byte var x7270 [1 << 17]byte var x7271 [1 << 17]byte var x7272 [1 << 17]byte var x7273 [1 << 17]byte var x7274 [1 << 17]byte var x7275 [1 << 17]byte var x7276 [1 << 17]byte var x7277 [1 << 17]byte var x7278 [1 << 17]byte var x7279 [1 << 17]byte var x7280 [1 << 17]byte var x7281 [1 << 17]byte var x7282 [1 << 17]byte var x7283 [1 << 17]byte var x7284 [1 << 17]byte var x7285 [1 << 17]byte var x7286 [1 << 17]byte var x7287 [1 << 17]byte var x7288 [1 << 17]byte var x7289 [1 << 17]byte var x7290 [1 << 17]byte var x7291 [1 << 17]byte var x7292 [1 << 17]byte var x7293 [1 << 17]byte var x7294 [1 << 17]byte var x7295 [1 << 17]byte var x7296 [1 << 17]byte var x7297 [1 << 17]byte var x7298 [1 << 17]byte var x7299 [1 << 17]byte var x7300 [1 << 17]byte var x7301 [1 << 17]byte var x7302 [1 << 17]byte var x7303 [1 << 17]byte var x7304 [1 << 17]byte var x7305 [1 << 17]byte var x7306 [1 << 17]byte var x7307 [1 << 17]byte var x7308 [1 << 17]byte var x7309 [1 << 17]byte var x7310 [1 << 17]byte var x7311 [1 << 17]byte var x7312 [1 << 17]byte var x7313 [1 << 17]byte var x7314 [1 << 17]byte var x7315 [1 << 17]byte var x7316 [1 << 17]byte var x7317 [1 << 17]byte var x7318 [1 << 17]byte var x7319 [1 << 17]byte var x7320 [1 << 17]byte var x7321 [1 << 17]byte var x7322 [1 << 17]byte var x7323 [1 << 17]byte var x7324 [1 << 17]byte var x7325 [1 << 17]byte var x7326 [1 << 17]byte var x7327 [1 << 17]byte var x7328 [1 << 17]byte var x7329 [1 << 17]byte var x7330 [1 << 17]byte var x7331 [1 << 17]byte var x7332 [1 << 17]byte var x7333 [1 << 17]byte var x7334 [1 << 17]byte var x7335 [1 << 17]byte var x7336 [1 << 17]byte var x7337 [1 << 17]byte var x7338 [1 << 17]byte var x7339 [1 << 17]byte var x7340 [1 << 17]byte var x7341 [1 << 17]byte var x7342 [1 << 17]byte var x7343 [1 << 17]byte var x7344 [1 << 17]byte var x7345 [1 << 17]byte var x7346 [1 << 17]byte var x7347 [1 << 17]byte var x7348 [1 << 17]byte var x7349 [1 << 17]byte var x7350 [1 << 17]byte var x7351 [1 << 17]byte var x7352 [1 << 17]byte var x7353 [1 << 17]byte var x7354 [1 << 17]byte var x7355 [1 << 17]byte var x7356 [1 << 17]byte var x7357 [1 << 17]byte var x7358 [1 << 17]byte var x7359 [1 << 17]byte var x7360 [1 << 17]byte var x7361 [1 << 17]byte var x7362 [1 << 17]byte var x7363 [1 << 17]byte var x7364 [1 << 17]byte var x7365 [1 << 17]byte var x7366 [1 << 17]byte var x7367 [1 << 17]byte var x7368 [1 << 17]byte var x7369 [1 << 17]byte var x7370 [1 << 17]byte var x7371 [1 << 17]byte var x7372 [1 << 17]byte var x7373 [1 << 17]byte var x7374 [1 << 17]byte var x7375 [1 << 17]byte var x7376 [1 << 17]byte var x7377 [1 << 17]byte var x7378 [1 << 17]byte var x7379 [1 << 17]byte var x7380 [1 << 17]byte var x7381 [1 << 17]byte var x7382 [1 << 17]byte var x7383 [1 << 17]byte var x7384 [1 << 17]byte var x7385 [1 << 17]byte var x7386 [1 << 17]byte var x7387 [1 << 17]byte var x7388 [1 << 17]byte var x7389 [1 << 17]byte var x7390 [1 << 17]byte var x7391 [1 << 17]byte var x7392 [1 << 17]byte var x7393 [1 << 17]byte var x7394 [1 << 17]byte var x7395 [1 << 17]byte var x7396 [1 << 17]byte var x7397 [1 << 17]byte var x7398 [1 << 17]byte var x7399 [1 << 17]byte var x7400 [1 << 17]byte var x7401 [1 << 17]byte var x7402 [1 << 17]byte var x7403 [1 << 17]byte var x7404 [1 << 17]byte var x7405 [1 << 17]byte var x7406 [1 << 17]byte var x7407 [1 << 17]byte var x7408 [1 << 17]byte var x7409 [1 << 17]byte var x7410 [1 << 17]byte var x7411 [1 << 17]byte var x7412 [1 << 17]byte var x7413 [1 << 17]byte var x7414 [1 << 17]byte var x7415 [1 << 17]byte var x7416 [1 << 17]byte var x7417 [1 << 17]byte var x7418 [1 << 17]byte var x7419 [1 << 17]byte var x7420 [1 << 17]byte var x7421 [1 << 17]byte var x7422 [1 << 17]byte var x7423 [1 << 17]byte var x7424 [1 << 17]byte var x7425 [1 << 17]byte var x7426 [1 << 17]byte var x7427 [1 << 17]byte var x7428 [1 << 17]byte var x7429 [1 << 17]byte var x7430 [1 << 17]byte var x7431 [1 << 17]byte var x7432 [1 << 17]byte var x7433 [1 << 17]byte var x7434 [1 << 17]byte var x7435 [1 << 17]byte var x7436 [1 << 17]byte var x7437 [1 << 17]byte var x7438 [1 << 17]byte var x7439 [1 << 17]byte var x7440 [1 << 17]byte var x7441 [1 << 17]byte var x7442 [1 << 17]byte var x7443 [1 << 17]byte var x7444 [1 << 17]byte var x7445 [1 << 17]byte var x7446 [1 << 17]byte var x7447 [1 << 17]byte var x7448 [1 << 17]byte var x7449 [1 << 17]byte var x7450 [1 << 17]byte var x7451 [1 << 17]byte var x7452 [1 << 17]byte var x7453 [1 << 17]byte var x7454 [1 << 17]byte var x7455 [1 << 17]byte var x7456 [1 << 17]byte var x7457 [1 << 17]byte var x7458 [1 << 17]byte var x7459 [1 << 17]byte var x7460 [1 << 17]byte var x7461 [1 << 17]byte var x7462 [1 << 17]byte var x7463 [1 << 17]byte var x7464 [1 << 17]byte var x7465 [1 << 17]byte var x7466 [1 << 17]byte var x7467 [1 << 17]byte var x7468 [1 << 17]byte var x7469 [1 << 17]byte var x7470 [1 << 17]byte var x7471 [1 << 17]byte var x7472 [1 << 17]byte var x7473 [1 << 17]byte var x7474 [1 << 17]byte var x7475 [1 << 17]byte var x7476 [1 << 17]byte var x7477 [1 << 17]byte var x7478 [1 << 17]byte var x7479 [1 << 17]byte var x7480 [1 << 17]byte var x7481 [1 << 17]byte var x7482 [1 << 17]byte var x7483 [1 << 17]byte var x7484 [1 << 17]byte var x7485 [1 << 17]byte var x7486 [1 << 17]byte var x7487 [1 << 17]byte var x7488 [1 << 17]byte var x7489 [1 << 17]byte var x7490 [1 << 17]byte var x7491 [1 << 17]byte var x7492 [1 << 17]byte var x7493 [1 << 17]byte var x7494 [1 << 17]byte var x7495 [1 << 17]byte var x7496 [1 << 17]byte var x7497 [1 << 17]byte var x7498 [1 << 17]byte var x7499 [1 << 17]byte var x7500 [1 << 17]byte var x7501 [1 << 17]byte var x7502 [1 << 17]byte var x7503 [1 << 17]byte var x7504 [1 << 17]byte var x7505 [1 << 17]byte var x7506 [1 << 17]byte var x7507 [1 << 17]byte var x7508 [1 << 17]byte var x7509 [1 << 17]byte var x7510 [1 << 17]byte var x7511 [1 << 17]byte var x7512 [1 << 17]byte var x7513 [1 << 17]byte var x7514 [1 << 17]byte var x7515 [1 << 17]byte var x7516 [1 << 17]byte var x7517 [1 << 17]byte var x7518 [1 << 17]byte var x7519 [1 << 17]byte var x7520 [1 << 17]byte var x7521 [1 << 17]byte var x7522 [1 << 17]byte var x7523 [1 << 17]byte var x7524 [1 << 17]byte var x7525 [1 << 17]byte var x7526 [1 << 17]byte var x7527 [1 << 17]byte var x7528 [1 << 17]byte var x7529 [1 << 17]byte var x7530 [1 << 17]byte var x7531 [1 << 17]byte var x7532 [1 << 17]byte var x7533 [1 << 17]byte var x7534 [1 << 17]byte var x7535 [1 << 17]byte var x7536 [1 << 17]byte var x7537 [1 << 17]byte var x7538 [1 << 17]byte var x7539 [1 << 17]byte var x7540 [1 << 17]byte var x7541 [1 << 17]byte var x7542 [1 << 17]byte var x7543 [1 << 17]byte var x7544 [1 << 17]byte var x7545 [1 << 17]byte var x7546 [1 << 17]byte var x7547 [1 << 17]byte var x7548 [1 << 17]byte var x7549 [1 << 17]byte var x7550 [1 << 17]byte var x7551 [1 << 17]byte var x7552 [1 << 17]byte var x7553 [1 << 17]byte var x7554 [1 << 17]byte var x7555 [1 << 17]byte var x7556 [1 << 17]byte var x7557 [1 << 17]byte var x7558 [1 << 17]byte var x7559 [1 << 17]byte var x7560 [1 << 17]byte var x7561 [1 << 17]byte var x7562 [1 << 17]byte var x7563 [1 << 17]byte var x7564 [1 << 17]byte var x7565 [1 << 17]byte var x7566 [1 << 17]byte var x7567 [1 << 17]byte var x7568 [1 << 17]byte var x7569 [1 << 17]byte var x7570 [1 << 17]byte var x7571 [1 << 17]byte var x7572 [1 << 17]byte var x7573 [1 << 17]byte var x7574 [1 << 17]byte var x7575 [1 << 17]byte var x7576 [1 << 17]byte var x7577 [1 << 17]byte var x7578 [1 << 17]byte var x7579 [1 << 17]byte var x7580 [1 << 17]byte var x7581 [1 << 17]byte var x7582 [1 << 17]byte var x7583 [1 << 17]byte var x7584 [1 << 17]byte var x7585 [1 << 17]byte var x7586 [1 << 17]byte var x7587 [1 << 17]byte var x7588 [1 << 17]byte var x7589 [1 << 17]byte var x7590 [1 << 17]byte var x7591 [1 << 17]byte var x7592 [1 << 17]byte var x7593 [1 << 17]byte var x7594 [1 << 17]byte var x7595 [1 << 17]byte var x7596 [1 << 17]byte var x7597 [1 << 17]byte var x7598 [1 << 17]byte var x7599 [1 << 17]byte var x7600 [1 << 17]byte var x7601 [1 << 17]byte var x7602 [1 << 17]byte var x7603 [1 << 17]byte var x7604 [1 << 17]byte var x7605 [1 << 17]byte var x7606 [1 << 17]byte var x7607 [1 << 17]byte var x7608 [1 << 17]byte var x7609 [1 << 17]byte var x7610 [1 << 17]byte var x7611 [1 << 17]byte var x7612 [1 << 17]byte var x7613 [1 << 17]byte var x7614 [1 << 17]byte var x7615 [1 << 17]byte var x7616 [1 << 17]byte var x7617 [1 << 17]byte var x7618 [1 << 17]byte var x7619 [1 << 17]byte var x7620 [1 << 17]byte var x7621 [1 << 17]byte var x7622 [1 << 17]byte var x7623 [1 << 17]byte var x7624 [1 << 17]byte var x7625 [1 << 17]byte var x7626 [1 << 17]byte var x7627 [1 << 17]byte var x7628 [1 << 17]byte var x7629 [1 << 17]byte var x7630 [1 << 17]byte var x7631 [1 << 17]byte var x7632 [1 << 17]byte var x7633 [1 << 17]byte var x7634 [1 << 17]byte var x7635 [1 << 17]byte var x7636 [1 << 17]byte var x7637 [1 << 17]byte var x7638 [1 << 17]byte var x7639 [1 << 17]byte var x7640 [1 << 17]byte var x7641 [1 << 17]byte var x7642 [1 << 17]byte var x7643 [1 << 17]byte var x7644 [1 << 17]byte var x7645 [1 << 17]byte var x7646 [1 << 17]byte var x7647 [1 << 17]byte var x7648 [1 << 17]byte var x7649 [1 << 17]byte var x7650 [1 << 17]byte var x7651 [1 << 17]byte var x7652 [1 << 17]byte var x7653 [1 << 17]byte var x7654 [1 << 17]byte var x7655 [1 << 17]byte var x7656 [1 << 17]byte var x7657 [1 << 17]byte var x7658 [1 << 17]byte var x7659 [1 << 17]byte var x7660 [1 << 17]byte var x7661 [1 << 17]byte var x7662 [1 << 17]byte var x7663 [1 << 17]byte var x7664 [1 << 17]byte var x7665 [1 << 17]byte var x7666 [1 << 17]byte var x7667 [1 << 17]byte var x7668 [1 << 17]byte var x7669 [1 << 17]byte var x7670 [1 << 17]byte var x7671 [1 << 17]byte var x7672 [1 << 17]byte var x7673 [1 << 17]byte var x7674 [1 << 17]byte var x7675 [1 << 17]byte var x7676 [1 << 17]byte var x7677 [1 << 17]byte var x7678 [1 << 17]byte var x7679 [1 << 17]byte var x7680 [1 << 17]byte var x7681 [1 << 17]byte var x7682 [1 << 17]byte var x7683 [1 << 17]byte var x7684 [1 << 17]byte var x7685 [1 << 17]byte var x7686 [1 << 17]byte var x7687 [1 << 17]byte var x7688 [1 << 17]byte var x7689 [1 << 17]byte var x7690 [1 << 17]byte var x7691 [1 << 17]byte var x7692 [1 << 17]byte var x7693 [1 << 17]byte var x7694 [1 << 17]byte var x7695 [1 << 17]byte var x7696 [1 << 17]byte var x7697 [1 << 17]byte var x7698 [1 << 17]byte var x7699 [1 << 17]byte var x7700 [1 << 17]byte var x7701 [1 << 17]byte var x7702 [1 << 17]byte var x7703 [1 << 17]byte var x7704 [1 << 17]byte var x7705 [1 << 17]byte var x7706 [1 << 17]byte var x7707 [1 << 17]byte var x7708 [1 << 17]byte var x7709 [1 << 17]byte var x7710 [1 << 17]byte var x7711 [1 << 17]byte var x7712 [1 << 17]byte var x7713 [1 << 17]byte var x7714 [1 << 17]byte var x7715 [1 << 17]byte var x7716 [1 << 17]byte var x7717 [1 << 17]byte var x7718 [1 << 17]byte var x7719 [1 << 17]byte var x7720 [1 << 17]byte var x7721 [1 << 17]byte var x7722 [1 << 17]byte var x7723 [1 << 17]byte var x7724 [1 << 17]byte var x7725 [1 << 17]byte var x7726 [1 << 17]byte var x7727 [1 << 17]byte var x7728 [1 << 17]byte var x7729 [1 << 17]byte var x7730 [1 << 17]byte var x7731 [1 << 17]byte var x7732 [1 << 17]byte var x7733 [1 << 17]byte var x7734 [1 << 17]byte var x7735 [1 << 17]byte var x7736 [1 << 17]byte var x7737 [1 << 17]byte var x7738 [1 << 17]byte var x7739 [1 << 17]byte var x7740 [1 << 17]byte var x7741 [1 << 17]byte var x7742 [1 << 17]byte var x7743 [1 << 17]byte var x7744 [1 << 17]byte var x7745 [1 << 17]byte var x7746 [1 << 17]byte var x7747 [1 << 17]byte var x7748 [1 << 17]byte var x7749 [1 << 17]byte var x7750 [1 << 17]byte var x7751 [1 << 17]byte var x7752 [1 << 17]byte var x7753 [1 << 17]byte var x7754 [1 << 17]byte var x7755 [1 << 17]byte var x7756 [1 << 17]byte var x7757 [1 << 17]byte var x7758 [1 << 17]byte var x7759 [1 << 17]byte var x7760 [1 << 17]byte var x7761 [1 << 17]byte var x7762 [1 << 17]byte var x7763 [1 << 17]byte var x7764 [1 << 17]byte var x7765 [1 << 17]byte var x7766 [1 << 17]byte var x7767 [1 << 17]byte var x7768 [1 << 17]byte var x7769 [1 << 17]byte var x7770 [1 << 17]byte var x7771 [1 << 17]byte var x7772 [1 << 17]byte var x7773 [1 << 17]byte var x7774 [1 << 17]byte var x7775 [1 << 17]byte var x7776 [1 << 17]byte var x7777 [1 << 17]byte var x7778 [1 << 17]byte var x7779 [1 << 17]byte var x7780 [1 << 17]byte var x7781 [1 << 17]byte var x7782 [1 << 17]byte var x7783 [1 << 17]byte var x7784 [1 << 17]byte var x7785 [1 << 17]byte var x7786 [1 << 17]byte var x7787 [1 << 17]byte var x7788 [1 << 17]byte var x7789 [1 << 17]byte var x7790 [1 << 17]byte var x7791 [1 << 17]byte var x7792 [1 << 17]byte var x7793 [1 << 17]byte var x7794 [1 << 17]byte var x7795 [1 << 17]byte var x7796 [1 << 17]byte var x7797 [1 << 17]byte var x7798 [1 << 17]byte var x7799 [1 << 17]byte var x7800 [1 << 17]byte var x7801 [1 << 17]byte var x7802 [1 << 17]byte var x7803 [1 << 17]byte var x7804 [1 << 17]byte var x7805 [1 << 17]byte var x7806 [1 << 17]byte var x7807 [1 << 17]byte var x7808 [1 << 17]byte var x7809 [1 << 17]byte var x7810 [1 << 17]byte var x7811 [1 << 17]byte var x7812 [1 << 17]byte var x7813 [1 << 17]byte var x7814 [1 << 17]byte var x7815 [1 << 17]byte var x7816 [1 << 17]byte var x7817 [1 << 17]byte var x7818 [1 << 17]byte var x7819 [1 << 17]byte var x7820 [1 << 17]byte var x7821 [1 << 17]byte var x7822 [1 << 17]byte var x7823 [1 << 17]byte var x7824 [1 << 17]byte var x7825 [1 << 17]byte var x7826 [1 << 17]byte var x7827 [1 << 17]byte var x7828 [1 << 17]byte var x7829 [1 << 17]byte var x7830 [1 << 17]byte var x7831 [1 << 17]byte var x7832 [1 << 17]byte var x7833 [1 << 17]byte var x7834 [1 << 17]byte var x7835 [1 << 17]byte var x7836 [1 << 17]byte var x7837 [1 << 17]byte var x7838 [1 << 17]byte var x7839 [1 << 17]byte var x7840 [1 << 17]byte var x7841 [1 << 17]byte var x7842 [1 << 17]byte var x7843 [1 << 17]byte var x7844 [1 << 17]byte var x7845 [1 << 17]byte var x7846 [1 << 17]byte var x7847 [1 << 17]byte var x7848 [1 << 17]byte var x7849 [1 << 17]byte var x7850 [1 << 17]byte var x7851 [1 << 17]byte var x7852 [1 << 17]byte var x7853 [1 << 17]byte var x7854 [1 << 17]byte var x7855 [1 << 17]byte var x7856 [1 << 17]byte var x7857 [1 << 17]byte var x7858 [1 << 17]byte var x7859 [1 << 17]byte var x7860 [1 << 17]byte var x7861 [1 << 17]byte var x7862 [1 << 17]byte var x7863 [1 << 17]byte var x7864 [1 << 17]byte var x7865 [1 << 17]byte var x7866 [1 << 17]byte var x7867 [1 << 17]byte var x7868 [1 << 17]byte var x7869 [1 << 17]byte var x7870 [1 << 17]byte var x7871 [1 << 17]byte var x7872 [1 << 17]byte var x7873 [1 << 17]byte var x7874 [1 << 17]byte var x7875 [1 << 17]byte var x7876 [1 << 17]byte var x7877 [1 << 17]byte var x7878 [1 << 17]byte var x7879 [1 << 17]byte var x7880 [1 << 17]byte var x7881 [1 << 17]byte var x7882 [1 << 17]byte var x7883 [1 << 17]byte var x7884 [1 << 17]byte var x7885 [1 << 17]byte var x7886 [1 << 17]byte var x7887 [1 << 17]byte var x7888 [1 << 17]byte var x7889 [1 << 17]byte var x7890 [1 << 17]byte var x7891 [1 << 17]byte var x7892 [1 << 17]byte var x7893 [1 << 17]byte var x7894 [1 << 17]byte var x7895 [1 << 17]byte var x7896 [1 << 17]byte var x7897 [1 << 17]byte var x7898 [1 << 17]byte var x7899 [1 << 17]byte var x7900 [1 << 17]byte var x7901 [1 << 17]byte var x7902 [1 << 17]byte var x7903 [1 << 17]byte var x7904 [1 << 17]byte var x7905 [1 << 17]byte var x7906 [1 << 17]byte var x7907 [1 << 17]byte var x7908 [1 << 17]byte var x7909 [1 << 17]byte var x7910 [1 << 17]byte var x7911 [1 << 17]byte var x7912 [1 << 17]byte var x7913 [1 << 17]byte var x7914 [1 << 17]byte var x7915 [1 << 17]byte var x7916 [1 << 17]byte var x7917 [1 << 17]byte var x7918 [1 << 17]byte var x7919 [1 << 17]byte var x7920 [1 << 17]byte var x7921 [1 << 17]byte var x7922 [1 << 17]byte var x7923 [1 << 17]byte var x7924 [1 << 17]byte var x7925 [1 << 17]byte var x7926 [1 << 17]byte var x7927 [1 << 17]byte var x7928 [1 << 17]byte var x7929 [1 << 17]byte var x7930 [1 << 17]byte var x7931 [1 << 17]byte var x7932 [1 << 17]byte var x7933 [1 << 17]byte var x7934 [1 << 17]byte var x7935 [1 << 17]byte var x7936 [1 << 17]byte var x7937 [1 << 17]byte var x7938 [1 << 17]byte var x7939 [1 << 17]byte var x7940 [1 << 17]byte var x7941 [1 << 17]byte var x7942 [1 << 17]byte var x7943 [1 << 17]byte var x7944 [1 << 17]byte var x7945 [1 << 17]byte var x7946 [1 << 17]byte var x7947 [1 << 17]byte var x7948 [1 << 17]byte var x7949 [1 << 17]byte var x7950 [1 << 17]byte var x7951 [1 << 17]byte var x7952 [1 << 17]byte var x7953 [1 << 17]byte var x7954 [1 << 17]byte var x7955 [1 << 17]byte var x7956 [1 << 17]byte var x7957 [1 << 17]byte var x7958 [1 << 17]byte var x7959 [1 << 17]byte var x7960 [1 << 17]byte var x7961 [1 << 17]byte var x7962 [1 << 17]byte var x7963 [1 << 17]byte var x7964 [1 << 17]byte var x7965 [1 << 17]byte var x7966 [1 << 17]byte var x7967 [1 << 17]byte var x7968 [1 << 17]byte var x7969 [1 << 17]byte var x7970 [1 << 17]byte var x7971 [1 << 17]byte var x7972 [1 << 17]byte var x7973 [1 << 17]byte var x7974 [1 << 17]byte var x7975 [1 << 17]byte var x7976 [1 << 17]byte var x7977 [1 << 17]byte var x7978 [1 << 17]byte var x7979 [1 << 17]byte var x7980 [1 << 17]byte var x7981 [1 << 17]byte var x7982 [1 << 17]byte var x7983 [1 << 17]byte var x7984 [1 << 17]byte var x7985 [1 << 17]byte var x7986 [1 << 17]byte var x7987 [1 << 17]byte var x7988 [1 << 17]byte var x7989 [1 << 17]byte var x7990 [1 << 17]byte var x7991 [1 << 17]byte var x7992 [1 << 17]byte var x7993 [1 << 17]byte var x7994 [1 << 17]byte var x7995 [1 << 17]byte var x7996 [1 << 17]byte var x7997 [1 << 17]byte var x7998 [1 << 17]byte var x7999 [1 << 17]byte var x8000 [1 << 17]byte var x8001 [1 << 17]byte var x8002 [1 << 17]byte var x8003 [1 << 17]byte var x8004 [1 << 17]byte var x8005 [1 << 17]byte var x8006 [1 << 17]byte var x8007 [1 << 17]byte var x8008 [1 << 17]byte var x8009 [1 << 17]byte var x8010 [1 << 17]byte var x8011 [1 << 17]byte var x8012 [1 << 17]byte var x8013 [1 << 17]byte var x8014 [1 << 17]byte var x8015 [1 << 17]byte var x8016 [1 << 17]byte var x8017 [1 << 17]byte var x8018 [1 << 17]byte var x8019 [1 << 17]byte var x8020 [1 << 17]byte var x8021 [1 << 17]byte var x8022 [1 << 17]byte var x8023 [1 << 17]byte var x8024 [1 << 17]byte var x8025 [1 << 17]byte var x8026 [1 << 17]byte var x8027 [1 << 17]byte var x8028 [1 << 17]byte var x8029 [1 << 17]byte var x8030 [1 << 17]byte var x8031 [1 << 17]byte var x8032 [1 << 17]byte var x8033 [1 << 17]byte var x8034 [1 << 17]byte var x8035 [1 << 17]byte var x8036 [1 << 17]byte var x8037 [1 << 17]byte var x8038 [1 << 17]byte var x8039 [1 << 17]byte var x8040 [1 << 17]byte var x8041 [1 << 17]byte var x8042 [1 << 17]byte var x8043 [1 << 17]byte var x8044 [1 << 17]byte var x8045 [1 << 17]byte var x8046 [1 << 17]byte var x8047 [1 << 17]byte var x8048 [1 << 17]byte var x8049 [1 << 17]byte var x8050 [1 << 17]byte var x8051 [1 << 17]byte var x8052 [1 << 17]byte var x8053 [1 << 17]byte var x8054 [1 << 17]byte var x8055 [1 << 17]byte var x8056 [1 << 17]byte var x8057 [1 << 17]byte var x8058 [1 << 17]byte var x8059 [1 << 17]byte var x8060 [1 << 17]byte var x8061 [1 << 17]byte var x8062 [1 << 17]byte var x8063 [1 << 17]byte var x8064 [1 << 17]byte var x8065 [1 << 17]byte var x8066 [1 << 17]byte var x8067 [1 << 17]byte var x8068 [1 << 17]byte var x8069 [1 << 17]byte var x8070 [1 << 17]byte var x8071 [1 << 17]byte var x8072 [1 << 17]byte var x8073 [1 << 17]byte var x8074 [1 << 17]byte var x8075 [1 << 17]byte var x8076 [1 << 17]byte var x8077 [1 << 17]byte var x8078 [1 << 17]byte var x8079 [1 << 17]byte var x8080 [1 << 17]byte var x8081 [1 << 17]byte var x8082 [1 << 17]byte var x8083 [1 << 17]byte var x8084 [1 << 17]byte var x8085 [1 << 17]byte var x8086 [1 << 17]byte var x8087 [1 << 17]byte var x8088 [1 << 17]byte var x8089 [1 << 17]byte var x8090 [1 << 17]byte var x8091 [1 << 17]byte var x8092 [1 << 17]byte var x8093 [1 << 17]byte var x8094 [1 << 17]byte var x8095 [1 << 17]byte var x8096 [1 << 17]byte var x8097 [1 << 17]byte var x8098 [1 << 17]byte var x8099 [1 << 17]byte var x8100 [1 << 17]byte var x8101 [1 << 17]byte var x8102 [1 << 17]byte var x8103 [1 << 17]byte var x8104 [1 << 17]byte var x8105 [1 << 17]byte var x8106 [1 << 17]byte var x8107 [1 << 17]byte var x8108 [1 << 17]byte var x8109 [1 << 17]byte var x8110 [1 << 17]byte var x8111 [1 << 17]byte var x8112 [1 << 17]byte var x8113 [1 << 17]byte var x8114 [1 << 17]byte var x8115 [1 << 17]byte var x8116 [1 << 17]byte var x8117 [1 << 17]byte var x8118 [1 << 17]byte var x8119 [1 << 17]byte var x8120 [1 << 17]byte var x8121 [1 << 17]byte var x8122 [1 << 17]byte var x8123 [1 << 17]byte var x8124 [1 << 17]byte var x8125 [1 << 17]byte var x8126 [1 << 17]byte var x8127 [1 << 17]byte var x8128 [1 << 17]byte var x8129 [1 << 17]byte var x8130 [1 << 17]byte var x8131 [1 << 17]byte var x8132 [1 << 17]byte var x8133 [1 << 17]byte var x8134 [1 << 17]byte var x8135 [1 << 17]byte var x8136 [1 << 17]byte var x8137 [1 << 17]byte var x8138 [1 << 17]byte var x8139 [1 << 17]byte var x8140 [1 << 17]byte var x8141 [1 << 17]byte var x8142 [1 << 17]byte var x8143 [1 << 17]byte var x8144 [1 << 17]byte var x8145 [1 << 17]byte var x8146 [1 << 17]byte var x8147 [1 << 17]byte var x8148 [1 << 17]byte var x8149 [1 << 17]byte var x8150 [1 << 17]byte var x8151 [1 << 17]byte var x8152 [1 << 17]byte var x8153 [1 << 17]byte var x8154 [1 << 17]byte var x8155 [1 << 17]byte var x8156 [1 << 17]byte var x8157 [1 << 17]byte var x8158 [1 << 17]byte var x8159 [1 << 17]byte var x8160 [1 << 17]byte var x8161 [1 << 17]byte var x8162 [1 << 17]byte var x8163 [1 << 17]byte var x8164 [1 << 17]byte var x8165 [1 << 17]byte var x8166 [1 << 17]byte var x8167 [1 << 17]byte var x8168 [1 << 17]byte var x8169 [1 << 17]byte var x8170 [1 << 17]byte var x8171 [1 << 17]byte var x8172 [1 << 17]byte var x8173 [1 << 17]byte var x8174 [1 << 17]byte var x8175 [1 << 17]byte var x8176 [1 << 17]byte var x8177 [1 << 17]byte var x8178 [1 << 17]byte var x8179 [1 << 17]byte var x8180 [1 << 17]byte var x8181 [1 << 17]byte var x8182 [1 << 17]byte var x8183 [1 << 17]byte var x8184 [1 << 17]byte var x8185 [1 << 17]byte var x8186 [1 << 17]byte var x8187 [1 << 17]byte var x8188 [1 << 17]byte var x8189 [1 << 17]byte var x8190 [1 << 17]byte var x8191 [1 << 17]byte var x8192 [1 << 17]byte var x8193 [1 << 17]byte var x8194 [1 << 17]byte var x8195 [1 << 17]byte var x8196 [1 << 17]byte var x8197 [1 << 17]byte var x8198 [1 << 17]byte var x8199 [1 << 17]byte var x8200 [1 << 17]byte var x8201 [1 << 17]byte var x8202 [1 << 17]byte var x8203 [1 << 17]byte var x8204 [1 << 17]byte var x8205 [1 << 17]byte var x8206 [1 << 17]byte var x8207 [1 << 17]byte var x8208 [1 << 17]byte var x8209 [1 << 17]byte var x8210 [1 << 17]byte var x8211 [1 << 17]byte var x8212 [1 << 17]byte var x8213 [1 << 17]byte var x8214 [1 << 17]byte var x8215 [1 << 17]byte var x8216 [1 << 17]byte var x8217 [1 << 17]byte var x8218 [1 << 17]byte var x8219 [1 << 17]byte var x8220 [1 << 17]byte var x8221 [1 << 17]byte var x8222 [1 << 17]byte var x8223 [1 << 17]byte var x8224 [1 << 17]byte var x8225 [1 << 17]byte var x8226 [1 << 17]byte var x8227 [1 << 17]byte var x8228 [1 << 17]byte var x8229 [1 << 17]byte var x8230 [1 << 17]byte var x8231 [1 << 17]byte var x8232 [1 << 17]byte var x8233 [1 << 17]byte var x8234 [1 << 17]byte var x8235 [1 << 17]byte var x8236 [1 << 17]byte var x8237 [1 << 17]byte var x8238 [1 << 17]byte var x8239 [1 << 17]byte var x8240 [1 << 17]byte var x8241 [1 << 17]byte var x8242 [1 << 17]byte var x8243 [1 << 17]byte var x8244 [1 << 17]byte var x8245 [1 << 17]byte var x8246 [1 << 17]byte var x8247 [1 << 17]byte var x8248 [1 << 17]byte var x8249 [1 << 17]byte var x8250 [1 << 17]byte var x8251 [1 << 17]byte var x8252 [1 << 17]byte var x8253 [1 << 17]byte var x8254 [1 << 17]byte var x8255 [1 << 17]byte var x8256 [1 << 17]byte var x8257 [1 << 17]byte var x8258 [1 << 17]byte var x8259 [1 << 17]byte var x8260 [1 << 17]byte var x8261 [1 << 17]byte var x8262 [1 << 17]byte var x8263 [1 << 17]byte var x8264 [1 << 17]byte var x8265 [1 << 17]byte var x8266 [1 << 17]byte var x8267 [1 << 17]byte var x8268 [1 << 17]byte var x8269 [1 << 17]byte var x8270 [1 << 17]byte var x8271 [1 << 17]byte var x8272 [1 << 17]byte var x8273 [1 << 17]byte var x8274 [1 << 17]byte var x8275 [1 << 17]byte var x8276 [1 << 17]byte var x8277 [1 << 17]byte var x8278 [1 << 17]byte var x8279 [1 << 17]byte var x8280 [1 << 17]byte var x8281 [1 << 17]byte var x8282 [1 << 17]byte var x8283 [1 << 17]byte var x8284 [1 << 17]byte var x8285 [1 << 17]byte var x8286 [1 << 17]byte var x8287 [1 << 17]byte var x8288 [1 << 17]byte var x8289 [1 << 17]byte var x8290 [1 << 17]byte var x8291 [1 << 17]byte var x8292 [1 << 17]byte var x8293 [1 << 17]byte var x8294 [1 << 17]byte var x8295 [1 << 17]byte var x8296 [1 << 17]byte var x8297 [1 << 17]byte var x8298 [1 << 17]byte var x8299 [1 << 17]byte var x8300 [1 << 17]byte var x8301 [1 << 17]byte var x8302 [1 << 17]byte var x8303 [1 << 17]byte var x8304 [1 << 17]byte var x8305 [1 << 17]byte var x8306 [1 << 17]byte var x8307 [1 << 17]byte var x8308 [1 << 17]byte var x8309 [1 << 17]byte var x8310 [1 << 17]byte var x8311 [1 << 17]byte var x8312 [1 << 17]byte var x8313 [1 << 17]byte var x8314 [1 << 17]byte var x8315 [1 << 17]byte var x8316 [1 << 17]byte var x8317 [1 << 17]byte var x8318 [1 << 17]byte var x8319 [1 << 17]byte var x8320 [1 << 17]byte var x8321 [1 << 17]byte var x8322 [1 << 17]byte var x8323 [1 << 17]byte var x8324 [1 << 17]byte var x8325 [1 << 17]byte var x8326 [1 << 17]byte var x8327 [1 << 17]byte var x8328 [1 << 17]byte var x8329 [1 << 17]byte var x8330 [1 << 17]byte var x8331 [1 << 17]byte var x8332 [1 << 17]byte var x8333 [1 << 17]byte var x8334 [1 << 17]byte var x8335 [1 << 17]byte var x8336 [1 << 17]byte var x8337 [1 << 17]byte var x8338 [1 << 17]byte var x8339 [1 << 17]byte var x8340 [1 << 17]byte var x8341 [1 << 17]byte var x8342 [1 << 17]byte var x8343 [1 << 17]byte var x8344 [1 << 17]byte var x8345 [1 << 17]byte var x8346 [1 << 17]byte var x8347 [1 << 17]byte var x8348 [1 << 17]byte var x8349 [1 << 17]byte var x8350 [1 << 17]byte var x8351 [1 << 17]byte var x8352 [1 << 17]byte var x8353 [1 << 17]byte var x8354 [1 << 17]byte var x8355 [1 << 17]byte var x8356 [1 << 17]byte var x8357 [1 << 17]byte var x8358 [1 << 17]byte var x8359 [1 << 17]byte var x8360 [1 << 17]byte var x8361 [1 << 17]byte var x8362 [1 << 17]byte var x8363 [1 << 17]byte var x8364 [1 << 17]byte var x8365 [1 << 17]byte var x8366 [1 << 17]byte var x8367 [1 << 17]byte var x8368 [1 << 17]byte var x8369 [1 << 17]byte var x8370 [1 << 17]byte var x8371 [1 << 17]byte var x8372 [1 << 17]byte var x8373 [1 << 17]byte var x8374 [1 << 17]byte var x8375 [1 << 17]byte var x8376 [1 << 17]byte var x8377 [1 << 17]byte var x8378 [1 << 17]byte var x8379 [1 << 17]byte var x8380 [1 << 17]byte var x8381 [1 << 17]byte var x8382 [1 << 17]byte var x8383 [1 << 17]byte var x8384 [1 << 17]byte var x8385 [1 << 17]byte var x8386 [1 << 17]byte var x8387 [1 << 17]byte var x8388 [1 << 17]byte var x8389 [1 << 17]byte var x8390 [1 << 17]byte var x8391 [1 << 17]byte var x8392 [1 << 17]byte var x8393 [1 << 17]byte var x8394 [1 << 17]byte var x8395 [1 << 17]byte var x8396 [1 << 17]byte var x8397 [1 << 17]byte var x8398 [1 << 17]byte var x8399 [1 << 17]byte var x8400 [1 << 17]byte var x8401 [1 << 17]byte var x8402 [1 << 17]byte var x8403 [1 << 17]byte var x8404 [1 << 17]byte var x8405 [1 << 17]byte var x8406 [1 << 17]byte var x8407 [1 << 17]byte var x8408 [1 << 17]byte var x8409 [1 << 17]byte var x8410 [1 << 17]byte var x8411 [1 << 17]byte var x8412 [1 << 17]byte var x8413 [1 << 17]byte var x8414 [1 << 17]byte var x8415 [1 << 17]byte var x8416 [1 << 17]byte var x8417 [1 << 17]byte var x8418 [1 << 17]byte var x8419 [1 << 17]byte var x8420 [1 << 17]byte var x8421 [1 << 17]byte var x8422 [1 << 17]byte var x8423 [1 << 17]byte var x8424 [1 << 17]byte var x8425 [1 << 17]byte var x8426 [1 << 17]byte var x8427 [1 << 17]byte var x8428 [1 << 17]byte var x8429 [1 << 17]byte var x8430 [1 << 17]byte var x8431 [1 << 17]byte var x8432 [1 << 17]byte var x8433 [1 << 17]byte var x8434 [1 << 17]byte var x8435 [1 << 17]byte var x8436 [1 << 17]byte var x8437 [1 << 17]byte var x8438 [1 << 17]byte var x8439 [1 << 17]byte var x8440 [1 << 17]byte var x8441 [1 << 17]byte var x8442 [1 << 17]byte var x8443 [1 << 17]byte var x8444 [1 << 17]byte var x8445 [1 << 17]byte var x8446 [1 << 17]byte var x8447 [1 << 17]byte var x8448 [1 << 17]byte var x8449 [1 << 17]byte var x8450 [1 << 17]byte var x8451 [1 << 17]byte var x8452 [1 << 17]byte var x8453 [1 << 17]byte var x8454 [1 << 17]byte var x8455 [1 << 17]byte var x8456 [1 << 17]byte var x8457 [1 << 17]byte var x8458 [1 << 17]byte var x8459 [1 << 17]byte var x8460 [1 << 17]byte var x8461 [1 << 17]byte var x8462 [1 << 17]byte var x8463 [1 << 17]byte var x8464 [1 << 17]byte var x8465 [1 << 17]byte var x8466 [1 << 17]byte var x8467 [1 << 17]byte var x8468 [1 << 17]byte var x8469 [1 << 17]byte var x8470 [1 << 17]byte var x8471 [1 << 17]byte var x8472 [1 << 17]byte var x8473 [1 << 17]byte var x8474 [1 << 17]byte var x8475 [1 << 17]byte var x8476 [1 << 17]byte var x8477 [1 << 17]byte var x8478 [1 << 17]byte var x8479 [1 << 17]byte var x8480 [1 << 17]byte var x8481 [1 << 17]byte var x8482 [1 << 17]byte var x8483 [1 << 17]byte var x8484 [1 << 17]byte var x8485 [1 << 17]byte var x8486 [1 << 17]byte var x8487 [1 << 17]byte var x8488 [1 << 17]byte var x8489 [1 << 17]byte var x8490 [1 << 17]byte var x8491 [1 << 17]byte var x8492 [1 << 17]byte var x8493 [1 << 17]byte var x8494 [1 << 17]byte var x8495 [1 << 17]byte var x8496 [1 << 17]byte var x8497 [1 << 17]byte var x8498 [1 << 17]byte var x8499 [1 << 17]byte var x8500 [1 << 17]byte var x8501 [1 << 17]byte var x8502 [1 << 17]byte var x8503 [1 << 17]byte var x8504 [1 << 17]byte var x8505 [1 << 17]byte var x8506 [1 << 17]byte var x8507 [1 << 17]byte var x8508 [1 << 17]byte var x8509 [1 << 17]byte var x8510 [1 << 17]byte var x8511 [1 << 17]byte var x8512 [1 << 17]byte var x8513 [1 << 17]byte var x8514 [1 << 17]byte var x8515 [1 << 17]byte var x8516 [1 << 17]byte var x8517 [1 << 17]byte var x8518 [1 << 17]byte var x8519 [1 << 17]byte var x8520 [1 << 17]byte var x8521 [1 << 17]byte var x8522 [1 << 17]byte var x8523 [1 << 17]byte var x8524 [1 << 17]byte var x8525 [1 << 17]byte var x8526 [1 << 17]byte var x8527 [1 << 17]byte var x8528 [1 << 17]byte var x8529 [1 << 17]byte var x8530 [1 << 17]byte var x8531 [1 << 17]byte var x8532 [1 << 17]byte var x8533 [1 << 17]byte var x8534 [1 << 17]byte var x8535 [1 << 17]byte var x8536 [1 << 17]byte var x8537 [1 << 17]byte var x8538 [1 << 17]byte var x8539 [1 << 17]byte var x8540 [1 << 17]byte var x8541 [1 << 17]byte var x8542 [1 << 17]byte var x8543 [1 << 17]byte var x8544 [1 << 17]byte var x8545 [1 << 17]byte var x8546 [1 << 17]byte var x8547 [1 << 17]byte var x8548 [1 << 17]byte var x8549 [1 << 17]byte var x8550 [1 << 17]byte var x8551 [1 << 17]byte var x8552 [1 << 17]byte var x8553 [1 << 17]byte var x8554 [1 << 17]byte var x8555 [1 << 17]byte var x8556 [1 << 17]byte var x8557 [1 << 17]byte var x8558 [1 << 17]byte var x8559 [1 << 17]byte var x8560 [1 << 17]byte var x8561 [1 << 17]byte var x8562 [1 << 17]byte var x8563 [1 << 17]byte var x8564 [1 << 17]byte var x8565 [1 << 17]byte var x8566 [1 << 17]byte var x8567 [1 << 17]byte var x8568 [1 << 17]byte var x8569 [1 << 17]byte var x8570 [1 << 17]byte var x8571 [1 << 17]byte var x8572 [1 << 17]byte var x8573 [1 << 17]byte var x8574 [1 << 17]byte var x8575 [1 << 17]byte var x8576 [1 << 17]byte var x8577 [1 << 17]byte var x8578 [1 << 17]byte var x8579 [1 << 17]byte var x8580 [1 << 17]byte var x8581 [1 << 17]byte var x8582 [1 << 17]byte var x8583 [1 << 17]byte var x8584 [1 << 17]byte var x8585 [1 << 17]byte var x8586 [1 << 17]byte var x8587 [1 << 17]byte var x8588 [1 << 17]byte var x8589 [1 << 17]byte var x8590 [1 << 17]byte var x8591 [1 << 17]byte var x8592 [1 << 17]byte var x8593 [1 << 17]byte var x8594 [1 << 17]byte var x8595 [1 << 17]byte var x8596 [1 << 17]byte var x8597 [1 << 17]byte var x8598 [1 << 17]byte var x8599 [1 << 17]byte var x8600 [1 << 17]byte var x8601 [1 << 17]byte var x8602 [1 << 17]byte var x8603 [1 << 17]byte var x8604 [1 << 17]byte var x8605 [1 << 17]byte var x8606 [1 << 17]byte var x8607 [1 << 17]byte var x8608 [1 << 17]byte var x8609 [1 << 17]byte var x8610 [1 << 17]byte var x8611 [1 << 17]byte var x8612 [1 << 17]byte var x8613 [1 << 17]byte var x8614 [1 << 17]byte var x8615 [1 << 17]byte var x8616 [1 << 17]byte var x8617 [1 << 17]byte var x8618 [1 << 17]byte var x8619 [1 << 17]byte var x8620 [1 << 17]byte var x8621 [1 << 17]byte var x8622 [1 << 17]byte var x8623 [1 << 17]byte var x8624 [1 << 17]byte var x8625 [1 << 17]byte var x8626 [1 << 17]byte var x8627 [1 << 17]byte var x8628 [1 << 17]byte var x8629 [1 << 17]byte var x8630 [1 << 17]byte var x8631 [1 << 17]byte var x8632 [1 << 17]byte var x8633 [1 << 17]byte var x8634 [1 << 17]byte var x8635 [1 << 17]byte var x8636 [1 << 17]byte var x8637 [1 << 17]byte var x8638 [1 << 17]byte var x8639 [1 << 17]byte var x8640 [1 << 17]byte var x8641 [1 << 17]byte var x8642 [1 << 17]byte var x8643 [1 << 17]byte var x8644 [1 << 17]byte var x8645 [1 << 17]byte var x8646 [1 << 17]byte var x8647 [1 << 17]byte var x8648 [1 << 17]byte var x8649 [1 << 17]byte var x8650 [1 << 17]byte var x8651 [1 << 17]byte var x8652 [1 << 17]byte var x8653 [1 << 17]byte var x8654 [1 << 17]byte var x8655 [1 << 17]byte var x8656 [1 << 17]byte var x8657 [1 << 17]byte var x8658 [1 << 17]byte var x8659 [1 << 17]byte var x8660 [1 << 17]byte var x8661 [1 << 17]byte var x8662 [1 << 17]byte var x8663 [1 << 17]byte var x8664 [1 << 17]byte var x8665 [1 << 17]byte var x8666 [1 << 17]byte var x8667 [1 << 17]byte var x8668 [1 << 17]byte var x8669 [1 << 17]byte var x8670 [1 << 17]byte var x8671 [1 << 17]byte var x8672 [1 << 17]byte var x8673 [1 << 17]byte var x8674 [1 << 17]byte var x8675 [1 << 17]byte var x8676 [1 << 17]byte var x8677 [1 << 17]byte var x8678 [1 << 17]byte var x8679 [1 << 17]byte var x8680 [1 << 17]byte var x8681 [1 << 17]byte var x8682 [1 << 17]byte var x8683 [1 << 17]byte var x8684 [1 << 17]byte var x8685 [1 << 17]byte var x8686 [1 << 17]byte var x8687 [1 << 17]byte var x8688 [1 << 17]byte var x8689 [1 << 17]byte var x8690 [1 << 17]byte var x8691 [1 << 17]byte var x8692 [1 << 17]byte var x8693 [1 << 17]byte var x8694 [1 << 17]byte var x8695 [1 << 17]byte var x8696 [1 << 17]byte var x8697 [1 << 17]byte var x8698 [1 << 17]byte var x8699 [1 << 17]byte var x8700 [1 << 17]byte var x8701 [1 << 17]byte var x8702 [1 << 17]byte var x8703 [1 << 17]byte var x8704 [1 << 17]byte var x8705 [1 << 17]byte var x8706 [1 << 17]byte var x8707 [1 << 17]byte var x8708 [1 << 17]byte var x8709 [1 << 17]byte var x8710 [1 << 17]byte var x8711 [1 << 17]byte var x8712 [1 << 17]byte var x8713 [1 << 17]byte var x8714 [1 << 17]byte var x8715 [1 << 17]byte var x8716 [1 << 17]byte var x8717 [1 << 17]byte var x8718 [1 << 17]byte var x8719 [1 << 17]byte var x8720 [1 << 17]byte var x8721 [1 << 17]byte var x8722 [1 << 17]byte var x8723 [1 << 17]byte var x8724 [1 << 17]byte var x8725 [1 << 17]byte var x8726 [1 << 17]byte var x8727 [1 << 17]byte var x8728 [1 << 17]byte var x8729 [1 << 17]byte var x8730 [1 << 17]byte var x8731 [1 << 17]byte var x8732 [1 << 17]byte var x8733 [1 << 17]byte var x8734 [1 << 17]byte var x8735 [1 << 17]byte var x8736 [1 << 17]byte var x8737 [1 << 17]byte var x8738 [1 << 17]byte var x8739 [1 << 17]byte var x8740 [1 << 17]byte var x8741 [1 << 17]byte var x8742 [1 << 17]byte var x8743 [1 << 17]byte var x8744 [1 << 17]byte var x8745 [1 << 17]byte var x8746 [1 << 17]byte var x8747 [1 << 17]byte var x8748 [1 << 17]byte var x8749 [1 << 17]byte var x8750 [1 << 17]byte var x8751 [1 << 17]byte var x8752 [1 << 17]byte var x8753 [1 << 17]byte var x8754 [1 << 17]byte var x8755 [1 << 17]byte var x8756 [1 << 17]byte var x8757 [1 << 17]byte var x8758 [1 << 17]byte var x8759 [1 << 17]byte var x8760 [1 << 17]byte var x8761 [1 << 17]byte var x8762 [1 << 17]byte var x8763 [1 << 17]byte var x8764 [1 << 17]byte var x8765 [1 << 17]byte var x8766 [1 << 17]byte var x8767 [1 << 17]byte var x8768 [1 << 17]byte var x8769 [1 << 17]byte var x8770 [1 << 17]byte var x8771 [1 << 17]byte var x8772 [1 << 17]byte var x8773 [1 << 17]byte var x8774 [1 << 17]byte var x8775 [1 << 17]byte var x8776 [1 << 17]byte var x8777 [1 << 17]byte var x8778 [1 << 17]byte var x8779 [1 << 17]byte var x8780 [1 << 17]byte var x8781 [1 << 17]byte var x8782 [1 << 17]byte var x8783 [1 << 17]byte var x8784 [1 << 17]byte var x8785 [1 << 17]byte var x8786 [1 << 17]byte var x8787 [1 << 17]byte var x8788 [1 << 17]byte var x8789 [1 << 17]byte var x8790 [1 << 17]byte var x8791 [1 << 17]byte var x8792 [1 << 17]byte var x8793 [1 << 17]byte var x8794 [1 << 17]byte var x8795 [1 << 17]byte var x8796 [1 << 17]byte var x8797 [1 << 17]byte var x8798 [1 << 17]byte var x8799 [1 << 17]byte var x8800 [1 << 17]byte var x8801 [1 << 17]byte var x8802 [1 << 17]byte var x8803 [1 << 17]byte var x8804 [1 << 17]byte var x8805 [1 << 17]byte var x8806 [1 << 17]byte var x8807 [1 << 17]byte var x8808 [1 << 17]byte var x8809 [1 << 17]byte var x8810 [1 << 17]byte var x8811 [1 << 17]byte var x8812 [1 << 17]byte var x8813 [1 << 17]byte var x8814 [1 << 17]byte var x8815 [1 << 17]byte var x8816 [1 << 17]byte var x8817 [1 << 17]byte var x8818 [1 << 17]byte var x8819 [1 << 17]byte var x8820 [1 << 17]byte var x8821 [1 << 17]byte var x8822 [1 << 17]byte var x8823 [1 << 17]byte var x8824 [1 << 17]byte var x8825 [1 << 17]byte var x8826 [1 << 17]byte var x8827 [1 << 17]byte var x8828 [1 << 17]byte var x8829 [1 << 17]byte var x8830 [1 << 17]byte var x8831 [1 << 17]byte var x8832 [1 << 17]byte var x8833 [1 << 17]byte var x8834 [1 << 17]byte var x8835 [1 << 17]byte var x8836 [1 << 17]byte var x8837 [1 << 17]byte var x8838 [1 << 17]byte var x8839 [1 << 17]byte var x8840 [1 << 17]byte var x8841 [1 << 17]byte var x8842 [1 << 17]byte var x8843 [1 << 17]byte var x8844 [1 << 17]byte var x8845 [1 << 17]byte var x8846 [1 << 17]byte var x8847 [1 << 17]byte var x8848 [1 << 17]byte var x8849 [1 << 17]byte var x8850 [1 << 17]byte var x8851 [1 << 17]byte var x8852 [1 << 17]byte var x8853 [1 << 17]byte var x8854 [1 << 17]byte var x8855 [1 << 17]byte var x8856 [1 << 17]byte var x8857 [1 << 17]byte var x8858 [1 << 17]byte var x8859 [1 << 17]byte var x8860 [1 << 17]byte var x8861 [1 << 17]byte var x8862 [1 << 17]byte var x8863 [1 << 17]byte var x8864 [1 << 17]byte var x8865 [1 << 17]byte var x8866 [1 << 17]byte var x8867 [1 << 17]byte var x8868 [1 << 17]byte var x8869 [1 << 17]byte var x8870 [1 << 17]byte var x8871 [1 << 17]byte var x8872 [1 << 17]byte var x8873 [1 << 17]byte var x8874 [1 << 17]byte var x8875 [1 << 17]byte var x8876 [1 << 17]byte var x8877 [1 << 17]byte var x8878 [1 << 17]byte var x8879 [1 << 17]byte var x8880 [1 << 17]byte var x8881 [1 << 17]byte var x8882 [1 << 17]byte var x8883 [1 << 17]byte var x8884 [1 << 17]byte var x8885 [1 << 17]byte var x8886 [1 << 17]byte var x8887 [1 << 17]byte var x8888 [1 << 17]byte var x8889 [1 << 17]byte var x8890 [1 << 17]byte var x8891 [1 << 17]byte var x8892 [1 << 17]byte var x8893 [1 << 17]byte var x8894 [1 << 17]byte var x8895 [1 << 17]byte var x8896 [1 << 17]byte var x8897 [1 << 17]byte var x8898 [1 << 17]byte var x8899 [1 << 17]byte var x8900 [1 << 17]byte var x8901 [1 << 17]byte var x8902 [1 << 17]byte var x8903 [1 << 17]byte var x8904 [1 << 17]byte var x8905 [1 << 17]byte var x8906 [1 << 17]byte var x8907 [1 << 17]byte var x8908 [1 << 17]byte var x8909 [1 << 17]byte var x8910 [1 << 17]byte var x8911 [1 << 17]byte var x8912 [1 << 17]byte var x8913 [1 << 17]byte var x8914 [1 << 17]byte var x8915 [1 << 17]byte var x8916 [1 << 17]byte var x8917 [1 << 17]byte var x8918 [1 << 17]byte var x8919 [1 << 17]byte var x8920 [1 << 17]byte var x8921 [1 << 17]byte var x8922 [1 << 17]byte var x8923 [1 << 17]byte var x8924 [1 << 17]byte var x8925 [1 << 17]byte var x8926 [1 << 17]byte var x8927 [1 << 17]byte var x8928 [1 << 17]byte var x8929 [1 << 17]byte var x8930 [1 << 17]byte var x8931 [1 << 17]byte var x8932 [1 << 17]byte var x8933 [1 << 17]byte var x8934 [1 << 17]byte var x8935 [1 << 17]byte var x8936 [1 << 17]byte var x8937 [1 << 17]byte var x8938 [1 << 17]byte var x8939 [1 << 17]byte var x8940 [1 << 17]byte var x8941 [1 << 17]byte var x8942 [1 << 17]byte var x8943 [1 << 17]byte var x8944 [1 << 17]byte var x8945 [1 << 17]byte var x8946 [1 << 17]byte var x8947 [1 << 17]byte var x8948 [1 << 17]byte var x8949 [1 << 17]byte var x8950 [1 << 17]byte var x8951 [1 << 17]byte var x8952 [1 << 17]byte var x8953 [1 << 17]byte var x8954 [1 << 17]byte var x8955 [1 << 17]byte var x8956 [1 << 17]byte var x8957 [1 << 17]byte var x8958 [1 << 17]byte var x8959 [1 << 17]byte var x8960 [1 << 17]byte var x8961 [1 << 17]byte var x8962 [1 << 17]byte var x8963 [1 << 17]byte var x8964 [1 << 17]byte var x8965 [1 << 17]byte var x8966 [1 << 17]byte var x8967 [1 << 17]byte var x8968 [1 << 17]byte var x8969 [1 << 17]byte var x8970 [1 << 17]byte var x8971 [1 << 17]byte var x8972 [1 << 17]byte var x8973 [1 << 17]byte var x8974 [1 << 17]byte var x8975 [1 << 17]byte var x8976 [1 << 17]byte var x8977 [1 << 17]byte var x8978 [1 << 17]byte var x8979 [1 << 17]byte var x8980 [1 << 17]byte var x8981 [1 << 17]byte var x8982 [1 << 17]byte var x8983 [1 << 17]byte var x8984 [1 << 17]byte var x8985 [1 << 17]byte var x8986 [1 << 17]byte var x8987 [1 << 17]byte var x8988 [1 << 17]byte var x8989 [1 << 17]byte var x8990 [1 << 17]byte var x8991 [1 << 17]byte var x8992 [1 << 17]byte var x8993 [1 << 17]byte var x8994 [1 << 17]byte var x8995 [1 << 17]byte var x8996 [1 << 17]byte var x8997 [1 << 17]byte var x8998 [1 << 17]byte var x8999 [1 << 17]byte var x9000 [1 << 17]byte var x9001 [1 << 17]byte var x9002 [1 << 17]byte var x9003 [1 << 17]byte var x9004 [1 << 17]byte var x9005 [1 << 17]byte var x9006 [1 << 17]byte var x9007 [1 << 17]byte var x9008 [1 << 17]byte var x9009 [1 << 17]byte var x9010 [1 << 17]byte var x9011 [1 << 17]byte var x9012 [1 << 17]byte var x9013 [1 << 17]byte var x9014 [1 << 17]byte var x9015 [1 << 17]byte var x9016 [1 << 17]byte var x9017 [1 << 17]byte var x9018 [1 << 17]byte var x9019 [1 << 17]byte var x9020 [1 << 17]byte var x9021 [1 << 17]byte var x9022 [1 << 17]byte var x9023 [1 << 17]byte var x9024 [1 << 17]byte var x9025 [1 << 17]byte var x9026 [1 << 17]byte var x9027 [1 << 17]byte var x9028 [1 << 17]byte var x9029 [1 << 17]byte var x9030 [1 << 17]byte var x9031 [1 << 17]byte var x9032 [1 << 17]byte var x9033 [1 << 17]byte var x9034 [1 << 17]byte var x9035 [1 << 17]byte var x9036 [1 << 17]byte var x9037 [1 << 17]byte var x9038 [1 << 17]byte var x9039 [1 << 17]byte var x9040 [1 << 17]byte var x9041 [1 << 17]byte var x9042 [1 << 17]byte var x9043 [1 << 17]byte var x9044 [1 << 17]byte var x9045 [1 << 17]byte var x9046 [1 << 17]byte var x9047 [1 << 17]byte var x9048 [1 << 17]byte var x9049 [1 << 17]byte var x9050 [1 << 17]byte var x9051 [1 << 17]byte var x9052 [1 << 17]byte var x9053 [1 << 17]byte var x9054 [1 << 17]byte var x9055 [1 << 17]byte var x9056 [1 << 17]byte var x9057 [1 << 17]byte var x9058 [1 << 17]byte var x9059 [1 << 17]byte var x9060 [1 << 17]byte var x9061 [1 << 17]byte var x9062 [1 << 17]byte var x9063 [1 << 17]byte var x9064 [1 << 17]byte var x9065 [1 << 17]byte var x9066 [1 << 17]byte var x9067 [1 << 17]byte var x9068 [1 << 17]byte var x9069 [1 << 17]byte var x9070 [1 << 17]byte var x9071 [1 << 17]byte var x9072 [1 << 17]byte var x9073 [1 << 17]byte var x9074 [1 << 17]byte var x9075 [1 << 17]byte var x9076 [1 << 17]byte var x9077 [1 << 17]byte var x9078 [1 << 17]byte var x9079 [1 << 17]byte var x9080 [1 << 17]byte var x9081 [1 << 17]byte var x9082 [1 << 17]byte var x9083 [1 << 17]byte var x9084 [1 << 17]byte var x9085 [1 << 17]byte var x9086 [1 << 17]byte var x9087 [1 << 17]byte var x9088 [1 << 17]byte var x9089 [1 << 17]byte var x9090 [1 << 17]byte var x9091 [1 << 17]byte var x9092 [1 << 17]byte var x9093 [1 << 17]byte var x9094 [1 << 17]byte var x9095 [1 << 17]byte var x9096 [1 << 17]byte var x9097 [1 << 17]byte var x9098 [1 << 17]byte var x9099 [1 << 17]byte var x9100 [1 << 17]byte var x9101 [1 << 17]byte var x9102 [1 << 17]byte var x9103 [1 << 17]byte var x9104 [1 << 17]byte var x9105 [1 << 17]byte var x9106 [1 << 17]byte var x9107 [1 << 17]byte var x9108 [1 << 17]byte var x9109 [1 << 17]byte var x9110 [1 << 17]byte var x9111 [1 << 17]byte var x9112 [1 << 17]byte var x9113 [1 << 17]byte var x9114 [1 << 17]byte var x9115 [1 << 17]byte var x9116 [1 << 17]byte var x9117 [1 << 17]byte var x9118 [1 << 17]byte var x9119 [1 << 17]byte var x9120 [1 << 17]byte var x9121 [1 << 17]byte var x9122 [1 << 17]byte var x9123 [1 << 17]byte var x9124 [1 << 17]byte var x9125 [1 << 17]byte var x9126 [1 << 17]byte var x9127 [1 << 17]byte var x9128 [1 << 17]byte var x9129 [1 << 17]byte var x9130 [1 << 17]byte var x9131 [1 << 17]byte var x9132 [1 << 17]byte var x9133 [1 << 17]byte var x9134 [1 << 17]byte var x9135 [1 << 17]byte var x9136 [1 << 17]byte var x9137 [1 << 17]byte var x9138 [1 << 17]byte var x9139 [1 << 17]byte var x9140 [1 << 17]byte var x9141 [1 << 17]byte var x9142 [1 << 17]byte var x9143 [1 << 17]byte var x9144 [1 << 17]byte var x9145 [1 << 17]byte var x9146 [1 << 17]byte var x9147 [1 << 17]byte var x9148 [1 << 17]byte var x9149 [1 << 17]byte var x9150 [1 << 17]byte var x9151 [1 << 17]byte var x9152 [1 << 17]byte var x9153 [1 << 17]byte var x9154 [1 << 17]byte var x9155 [1 << 17]byte var x9156 [1 << 17]byte var x9157 [1 << 17]byte var x9158 [1 << 17]byte var x9159 [1 << 17]byte var x9160 [1 << 17]byte var x9161 [1 << 17]byte var x9162 [1 << 17]byte var x9163 [1 << 17]byte var x9164 [1 << 17]byte var x9165 [1 << 17]byte var x9166 [1 << 17]byte var x9167 [1 << 17]byte var x9168 [1 << 17]byte var x9169 [1 << 17]byte var x9170 [1 << 17]byte var x9171 [1 << 17]byte var x9172 [1 << 17]byte var x9173 [1 << 17]byte var x9174 [1 << 17]byte var x9175 [1 << 17]byte var x9176 [1 << 17]byte var x9177 [1 << 17]byte var x9178 [1 << 17]byte var x9179 [1 << 17]byte var x9180 [1 << 17]byte var x9181 [1 << 17]byte var x9182 [1 << 17]byte var x9183 [1 << 17]byte var x9184 [1 << 17]byte var x9185 [1 << 17]byte var x9186 [1 << 17]byte var x9187 [1 << 17]byte var x9188 [1 << 17]byte var x9189 [1 << 17]byte var x9190 [1 << 17]byte var x9191 [1 << 17]byte var x9192 [1 << 17]byte var x9193 [1 << 17]byte var x9194 [1 << 17]byte var x9195 [1 << 17]byte var x9196 [1 << 17]byte var x9197 [1 << 17]byte var x9198 [1 << 17]byte var x9199 [1 << 17]byte var x9200 [1 << 17]byte var x9201 [1 << 17]byte var x9202 [1 << 17]byte var x9203 [1 << 17]byte var x9204 [1 << 17]byte var x9205 [1 << 17]byte var x9206 [1 << 17]byte var x9207 [1 << 17]byte var x9208 [1 << 17]byte var x9209 [1 << 17]byte var x9210 [1 << 17]byte var x9211 [1 << 17]byte var x9212 [1 << 17]byte var x9213 [1 << 17]byte var x9214 [1 << 17]byte var x9215 [1 << 17]byte var x9216 [1 << 17]byte var x9217 [1 << 17]byte var x9218 [1 << 17]byte var x9219 [1 << 17]byte var x9220 [1 << 17]byte var x9221 [1 << 17]byte var x9222 [1 << 17]byte var x9223 [1 << 17]byte var x9224 [1 << 17]byte var x9225 [1 << 17]byte var x9226 [1 << 17]byte var x9227 [1 << 17]byte var x9228 [1 << 17]byte var x9229 [1 << 17]byte var x9230 [1 << 17]byte var x9231 [1 << 17]byte var x9232 [1 << 17]byte var x9233 [1 << 17]byte var x9234 [1 << 17]byte var x9235 [1 << 17]byte var x9236 [1 << 17]byte var x9237 [1 << 17]byte var x9238 [1 << 17]byte var x9239 [1 << 17]byte var x9240 [1 << 17]byte var x9241 [1 << 17]byte var x9242 [1 << 17]byte var x9243 [1 << 17]byte var x9244 [1 << 17]byte var x9245 [1 << 17]byte var x9246 [1 << 17]byte var x9247 [1 << 17]byte var x9248 [1 << 17]byte var x9249 [1 << 17]byte var x9250 [1 << 17]byte var x9251 [1 << 17]byte var x9252 [1 << 17]byte var x9253 [1 << 17]byte var x9254 [1 << 17]byte var x9255 [1 << 17]byte var x9256 [1 << 17]byte var x9257 [1 << 17]byte var x9258 [1 << 17]byte var x9259 [1 << 17]byte var x9260 [1 << 17]byte var x9261 [1 << 17]byte var x9262 [1 << 17]byte var x9263 [1 << 17]byte var x9264 [1 << 17]byte var x9265 [1 << 17]byte var x9266 [1 << 17]byte var x9267 [1 << 17]byte var x9268 [1 << 17]byte var x9269 [1 << 17]byte var x9270 [1 << 17]byte var x9271 [1 << 17]byte var x9272 [1 << 17]byte var x9273 [1 << 17]byte var x9274 [1 << 17]byte var x9275 [1 << 17]byte var x9276 [1 << 17]byte var x9277 [1 << 17]byte var x9278 [1 << 17]byte var x9279 [1 << 17]byte var x9280 [1 << 17]byte var x9281 [1 << 17]byte var x9282 [1 << 17]byte var x9283 [1 << 17]byte var x9284 [1 << 17]byte var x9285 [1 << 17]byte var x9286 [1 << 17]byte var x9287 [1 << 17]byte var x9288 [1 << 17]byte var x9289 [1 << 17]byte var x9290 [1 << 17]byte var x9291 [1 << 17]byte var x9292 [1 << 17]byte var x9293 [1 << 17]byte var x9294 [1 << 17]byte var x9295 [1 << 17]byte var x9296 [1 << 17]byte var x9297 [1 << 17]byte var x9298 [1 << 17]byte var x9299 [1 << 17]byte var x9300 [1 << 17]byte var x9301 [1 << 17]byte var x9302 [1 << 17]byte var x9303 [1 << 17]byte var x9304 [1 << 17]byte var x9305 [1 << 17]byte var x9306 [1 << 17]byte var x9307 [1 << 17]byte var x9308 [1 << 17]byte var x9309 [1 << 17]byte var x9310 [1 << 17]byte var x9311 [1 << 17]byte var x9312 [1 << 17]byte var x9313 [1 << 17]byte var x9314 [1 << 17]byte var x9315 [1 << 17]byte var x9316 [1 << 17]byte var x9317 [1 << 17]byte var x9318 [1 << 17]byte var x9319 [1 << 17]byte var x9320 [1 << 17]byte var x9321 [1 << 17]byte var x9322 [1 << 17]byte var x9323 [1 << 17]byte var x9324 [1 << 17]byte var x9325 [1 << 17]byte var x9326 [1 << 17]byte var x9327 [1 << 17]byte var x9328 [1 << 17]byte var x9329 [1 << 17]byte var x9330 [1 << 17]byte var x9331 [1 << 17]byte var x9332 [1 << 17]byte var x9333 [1 << 17]byte var x9334 [1 << 17]byte var x9335 [1 << 17]byte var x9336 [1 << 17]byte var x9337 [1 << 17]byte var x9338 [1 << 17]byte var x9339 [1 << 17]byte var x9340 [1 << 17]byte var x9341 [1 << 17]byte var x9342 [1 << 17]byte var x9343 [1 << 17]byte var x9344 [1 << 17]byte var x9345 [1 << 17]byte var x9346 [1 << 17]byte var x9347 [1 << 17]byte var x9348 [1 << 17]byte var x9349 [1 << 17]byte var x9350 [1 << 17]byte var x9351 [1 << 17]byte var x9352 [1 << 17]byte var x9353 [1 << 17]byte var x9354 [1 << 17]byte var x9355 [1 << 17]byte var x9356 [1 << 17]byte var x9357 [1 << 17]byte var x9358 [1 << 17]byte var x9359 [1 << 17]byte var x9360 [1 << 17]byte var x9361 [1 << 17]byte var x9362 [1 << 17]byte var x9363 [1 << 17]byte var x9364 [1 << 17]byte var x9365 [1 << 17]byte var x9366 [1 << 17]byte var x9367 [1 << 17]byte var x9368 [1 << 17]byte var x9369 [1 << 17]byte var x9370 [1 << 17]byte var x9371 [1 << 17]byte var x9372 [1 << 17]byte var x9373 [1 << 17]byte var x9374 [1 << 17]byte var x9375 [1 << 17]byte var x9376 [1 << 17]byte var x9377 [1 << 17]byte var x9378 [1 << 17]byte var x9379 [1 << 17]byte var x9380 [1 << 17]byte var x9381 [1 << 17]byte var x9382 [1 << 17]byte var x9383 [1 << 17]byte var x9384 [1 << 17]byte var x9385 [1 << 17]byte var x9386 [1 << 17]byte var x9387 [1 << 17]byte var x9388 [1 << 17]byte var x9389 [1 << 17]byte var x9390 [1 << 17]byte var x9391 [1 << 17]byte var x9392 [1 << 17]byte var x9393 [1 << 17]byte var x9394 [1 << 17]byte var x9395 [1 << 17]byte var x9396 [1 << 17]byte var x9397 [1 << 17]byte var x9398 [1 << 17]byte var x9399 [1 << 17]byte var x9400 [1 << 17]byte var x9401 [1 << 17]byte var x9402 [1 << 17]byte var x9403 [1 << 17]byte var x9404 [1 << 17]byte var x9405 [1 << 17]byte var x9406 [1 << 17]byte var x9407 [1 << 17]byte var x9408 [1 << 17]byte var x9409 [1 << 17]byte var x9410 [1 << 17]byte var x9411 [1 << 17]byte var x9412 [1 << 17]byte var x9413 [1 << 17]byte var x9414 [1 << 17]byte var x9415 [1 << 17]byte var x9416 [1 << 17]byte var x9417 [1 << 17]byte var x9418 [1 << 17]byte var x9419 [1 << 17]byte var x9420 [1 << 17]byte var x9421 [1 << 17]byte var x9422 [1 << 17]byte var x9423 [1 << 17]byte var x9424 [1 << 17]byte var x9425 [1 << 17]byte var x9426 [1 << 17]byte var x9427 [1 << 17]byte var x9428 [1 << 17]byte var x9429 [1 << 17]byte var x9430 [1 << 17]byte var x9431 [1 << 17]byte var x9432 [1 << 17]byte var x9433 [1 << 17]byte var x9434 [1 << 17]byte var x9435 [1 << 17]byte var x9436 [1 << 17]byte var x9437 [1 << 17]byte var x9438 [1 << 17]byte var x9439 [1 << 17]byte var x9440 [1 << 17]byte var x9441 [1 << 17]byte var x9442 [1 << 17]byte var x9443 [1 << 17]byte var x9444 [1 << 17]byte var x9445 [1 << 17]byte var x9446 [1 << 17]byte var x9447 [1 << 17]byte var x9448 [1 << 17]byte var x9449 [1 << 17]byte var x9450 [1 << 17]byte var x9451 [1 << 17]byte var x9452 [1 << 17]byte var x9453 [1 << 17]byte var x9454 [1 << 17]byte var x9455 [1 << 17]byte var x9456 [1 << 17]byte var x9457 [1 << 17]byte var x9458 [1 << 17]byte var x9459 [1 << 17]byte var x9460 [1 << 17]byte var x9461 [1 << 17]byte var x9462 [1 << 17]byte var x9463 [1 << 17]byte var x9464 [1 << 17]byte var x9465 [1 << 17]byte var x9466 [1 << 17]byte var x9467 [1 << 17]byte var x9468 [1 << 17]byte var x9469 [1 << 17]byte var x9470 [1 << 17]byte var x9471 [1 << 17]byte var x9472 [1 << 17]byte var x9473 [1 << 17]byte var x9474 [1 << 17]byte var x9475 [1 << 17]byte var x9476 [1 << 17]byte var x9477 [1 << 17]byte var x9478 [1 << 17]byte var x9479 [1 << 17]byte var x9480 [1 << 17]byte var x9481 [1 << 17]byte var x9482 [1 << 17]byte var x9483 [1 << 17]byte var x9484 [1 << 17]byte var x9485 [1 << 17]byte var x9486 [1 << 17]byte var x9487 [1 << 17]byte var x9488 [1 << 17]byte var x9489 [1 << 17]byte var x9490 [1 << 17]byte var x9491 [1 << 17]byte var x9492 [1 << 17]byte var x9493 [1 << 17]byte var x9494 [1 << 17]byte var x9495 [1 << 17]byte var x9496 [1 << 17]byte var x9497 [1 << 17]byte var x9498 [1 << 17]byte var x9499 [1 << 17]byte var x9500 [1 << 17]byte var x9501 [1 << 17]byte var x9502 [1 << 17]byte var x9503 [1 << 17]byte var x9504 [1 << 17]byte var x9505 [1 << 17]byte var x9506 [1 << 17]byte var x9507 [1 << 17]byte var x9508 [1 << 17]byte var x9509 [1 << 17]byte var x9510 [1 << 17]byte var x9511 [1 << 17]byte var x9512 [1 << 17]byte var x9513 [1 << 17]byte var x9514 [1 << 17]byte var x9515 [1 << 17]byte var x9516 [1 << 17]byte var x9517 [1 << 17]byte var x9518 [1 << 17]byte var x9519 [1 << 17]byte var x9520 [1 << 17]byte var x9521 [1 << 17]byte var x9522 [1 << 17]byte var x9523 [1 << 17]byte var x9524 [1 << 17]byte var x9525 [1 << 17]byte var x9526 [1 << 17]byte var x9527 [1 << 17]byte var x9528 [1 << 17]byte var x9529 [1 << 17]byte var x9530 [1 << 17]byte var x9531 [1 << 17]byte var x9532 [1 << 17]byte var x9533 [1 << 17]byte var x9534 [1 << 17]byte var x9535 [1 << 17]byte var x9536 [1 << 17]byte var x9537 [1 << 17]byte var x9538 [1 << 17]byte var x9539 [1 << 17]byte var x9540 [1 << 17]byte var x9541 [1 << 17]byte var x9542 [1 << 17]byte var x9543 [1 << 17]byte var x9544 [1 << 17]byte var x9545 [1 << 17]byte var x9546 [1 << 17]byte var x9547 [1 << 17]byte var x9548 [1 << 17]byte var x9549 [1 << 17]byte var x9550 [1 << 17]byte var x9551 [1 << 17]byte var x9552 [1 << 17]byte var x9553 [1 << 17]byte var x9554 [1 << 17]byte var x9555 [1 << 17]byte var x9556 [1 << 17]byte var x9557 [1 << 17]byte var x9558 [1 << 17]byte var x9559 [1 << 17]byte var x9560 [1 << 17]byte var x9561 [1 << 17]byte var x9562 [1 << 17]byte var x9563 [1 << 17]byte var x9564 [1 << 17]byte var x9565 [1 << 17]byte var x9566 [1 << 17]byte var x9567 [1 << 17]byte var x9568 [1 << 17]byte var x9569 [1 << 17]byte var x9570 [1 << 17]byte var x9571 [1 << 17]byte var x9572 [1 << 17]byte var x9573 [1 << 17]byte var x9574 [1 << 17]byte var x9575 [1 << 17]byte var x9576 [1 << 17]byte var x9577 [1 << 17]byte var x9578 [1 << 17]byte var x9579 [1 << 17]byte var x9580 [1 << 17]byte var x9581 [1 << 17]byte var x9582 [1 << 17]byte var x9583 [1 << 17]byte var x9584 [1 << 17]byte var x9585 [1 << 17]byte var x9586 [1 << 17]byte var x9587 [1 << 17]byte var x9588 [1 << 17]byte var x9589 [1 << 17]byte var x9590 [1 << 17]byte var x9591 [1 << 17]byte var x9592 [1 << 17]byte var x9593 [1 << 17]byte var x9594 [1 << 17]byte var x9595 [1 << 17]byte var x9596 [1 << 17]byte var x9597 [1 << 17]byte var x9598 [1 << 17]byte var x9599 [1 << 17]byte var x9600 [1 << 17]byte var x9601 [1 << 17]byte var x9602 [1 << 17]byte var x9603 [1 << 17]byte var x9604 [1 << 17]byte var x9605 [1 << 17]byte var x9606 [1 << 17]byte var x9607 [1 << 17]byte var x9608 [1 << 17]byte var x9609 [1 << 17]byte var x9610 [1 << 17]byte var x9611 [1 << 17]byte var x9612 [1 << 17]byte var x9613 [1 << 17]byte var x9614 [1 << 17]byte var x9615 [1 << 17]byte var x9616 [1 << 17]byte var x9617 [1 << 17]byte var x9618 [1 << 17]byte var x9619 [1 << 17]byte var x9620 [1 << 17]byte var x9621 [1 << 17]byte var x9622 [1 << 17]byte var x9623 [1 << 17]byte var x9624 [1 << 17]byte var x9625 [1 << 17]byte var x9626 [1 << 17]byte var x9627 [1 << 17]byte var x9628 [1 << 17]byte var x9629 [1 << 17]byte var x9630 [1 << 17]byte var x9631 [1 << 17]byte var x9632 [1 << 17]byte var x9633 [1 << 17]byte var x9634 [1 << 17]byte var x9635 [1 << 17]byte var x9636 [1 << 17]byte var x9637 [1 << 17]byte var x9638 [1 << 17]byte var x9639 [1 << 17]byte var x9640 [1 << 17]byte var x9641 [1 << 17]byte var x9642 [1 << 17]byte var x9643 [1 << 17]byte var x9644 [1 << 17]byte var x9645 [1 << 17]byte var x9646 [1 << 17]byte var x9647 [1 << 17]byte var x9648 [1 << 17]byte var x9649 [1 << 17]byte var x9650 [1 << 17]byte var x9651 [1 << 17]byte var x9652 [1 << 17]byte var x9653 [1 << 17]byte var x9654 [1 << 17]byte var x9655 [1 << 17]byte var x9656 [1 << 17]byte var x9657 [1 << 17]byte var x9658 [1 << 17]byte var x9659 [1 << 17]byte var x9660 [1 << 17]byte var x9661 [1 << 17]byte var x9662 [1 << 17]byte var x9663 [1 << 17]byte var x9664 [1 << 17]byte var x9665 [1 << 17]byte var x9666 [1 << 17]byte var x9667 [1 << 17]byte var x9668 [1 << 17]byte var x9669 [1 << 17]byte var x9670 [1 << 17]byte var x9671 [1 << 17]byte var x9672 [1 << 17]byte var x9673 [1 << 17]byte var x9674 [1 << 17]byte var x9675 [1 << 17]byte var x9676 [1 << 17]byte var x9677 [1 << 17]byte var x9678 [1 << 17]byte var x9679 [1 << 17]byte var x9680 [1 << 17]byte var x9681 [1 << 17]byte var x9682 [1 << 17]byte var x9683 [1 << 17]byte var x9684 [1 << 17]byte var x9685 [1 << 17]byte var x9686 [1 << 17]byte var x9687 [1 << 17]byte var x9688 [1 << 17]byte var x9689 [1 << 17]byte var x9690 [1 << 17]byte var x9691 [1 << 17]byte var x9692 [1 << 17]byte var x9693 [1 << 17]byte var x9694 [1 << 17]byte var x9695 [1 << 17]byte var x9696 [1 << 17]byte var x9697 [1 << 17]byte var x9698 [1 << 17]byte var x9699 [1 << 17]byte var x9700 [1 << 17]byte var x9701 [1 << 17]byte var x9702 [1 << 17]byte var x9703 [1 << 17]byte var x9704 [1 << 17]byte var x9705 [1 << 17]byte var x9706 [1 << 17]byte var x9707 [1 << 17]byte var x9708 [1 << 17]byte var x9709 [1 << 17]byte var x9710 [1 << 17]byte var x9711 [1 << 17]byte var x9712 [1 << 17]byte var x9713 [1 << 17]byte var x9714 [1 << 17]byte var x9715 [1 << 17]byte var x9716 [1 << 17]byte var x9717 [1 << 17]byte var x9718 [1 << 17]byte var x9719 [1 << 17]byte var x9720 [1 << 17]byte var x9721 [1 << 17]byte var x9722 [1 << 17]byte var x9723 [1 << 17]byte var x9724 [1 << 17]byte var x9725 [1 << 17]byte var x9726 [1 << 17]byte var x9727 [1 << 17]byte var x9728 [1 << 17]byte var x9729 [1 << 17]byte var x9730 [1 << 17]byte var x9731 [1 << 17]byte var x9732 [1 << 17]byte var x9733 [1 << 17]byte var x9734 [1 << 17]byte var x9735 [1 << 17]byte var x9736 [1 << 17]byte var x9737 [1 << 17]byte var x9738 [1 << 17]byte var x9739 [1 << 17]byte var x9740 [1 << 17]byte var x9741 [1 << 17]byte var x9742 [1 << 17]byte var x9743 [1 << 17]byte var x9744 [1 << 17]byte var x9745 [1 << 17]byte var x9746 [1 << 17]byte var x9747 [1 << 17]byte var x9748 [1 << 17]byte var x9749 [1 << 17]byte var x9750 [1 << 17]byte var x9751 [1 << 17]byte var x9752 [1 << 17]byte var x9753 [1 << 17]byte var x9754 [1 << 17]byte var x9755 [1 << 17]byte var x9756 [1 << 17]byte var x9757 [1 << 17]byte var x9758 [1 << 17]byte var x9759 [1 << 17]byte var x9760 [1 << 17]byte var x9761 [1 << 17]byte var x9762 [1 << 17]byte var x9763 [1 << 17]byte var x9764 [1 << 17]byte var x9765 [1 << 17]byte var x9766 [1 << 17]byte var x9767 [1 << 17]byte var x9768 [1 << 17]byte var x9769 [1 << 17]byte var x9770 [1 << 17]byte var x9771 [1 << 17]byte var x9772 [1 << 17]byte var x9773 [1 << 17]byte var x9774 [1 << 17]byte var x9775 [1 << 17]byte var x9776 [1 << 17]byte var x9777 [1 << 17]byte var x9778 [1 << 17]byte var x9779 [1 << 17]byte var x9780 [1 << 17]byte var x9781 [1 << 17]byte var x9782 [1 << 17]byte var x9783 [1 << 17]byte var x9784 [1 << 17]byte var x9785 [1 << 17]byte var x9786 [1 << 17]byte var x9787 [1 << 17]byte var x9788 [1 << 17]byte var x9789 [1 << 17]byte var x9790 [1 << 17]byte var x9791 [1 << 17]byte var x9792 [1 << 17]byte var x9793 [1 << 17]byte var x9794 [1 << 17]byte var x9795 [1 << 17]byte var x9796 [1 << 17]byte var x9797 [1 << 17]byte var x9798 [1 << 17]byte var x9799 [1 << 17]byte var x9800 [1 << 17]byte var x9801 [1 << 17]byte var x9802 [1 << 17]byte var x9803 [1 << 17]byte var x9804 [1 << 17]byte var x9805 [1 << 17]byte var x9806 [1 << 17]byte var x9807 [1 << 17]byte var x9808 [1 << 17]byte var x9809 [1 << 17]byte var x9810 [1 << 17]byte var x9811 [1 << 17]byte var x9812 [1 << 17]byte var x9813 [1 << 17]byte var x9814 [1 << 17]byte var x9815 [1 << 17]byte var x9816 [1 << 17]byte var x9817 [1 << 17]byte var x9818 [1 << 17]byte var x9819 [1 << 17]byte var x9820 [1 << 17]byte var x9821 [1 << 17]byte var x9822 [1 << 17]byte var x9823 [1 << 17]byte var x9824 [1 << 17]byte var x9825 [1 << 17]byte var x9826 [1 << 17]byte var x9827 [1 << 17]byte var x9828 [1 << 17]byte var x9829 [1 << 17]byte var x9830 [1 << 17]byte var x9831 [1 << 17]byte var x9832 [1 << 17]byte var x9833 [1 << 17]byte var x9834 [1 << 17]byte var x9835 [1 << 17]byte var x9836 [1 << 17]byte var x9837 [1 << 17]byte var x9838 [1 << 17]byte var x9839 [1 << 17]byte var x9840 [1 << 17]byte var x9841 [1 << 17]byte var x9842 [1 << 17]byte var x9843 [1 << 17]byte var x9844 [1 << 17]byte var x9845 [1 << 17]byte var x9846 [1 << 17]byte var x9847 [1 << 17]byte var x9848 [1 << 17]byte var x9849 [1 << 17]byte var x9850 [1 << 17]byte var x9851 [1 << 17]byte var x9852 [1 << 17]byte var x9853 [1 << 17]byte var x9854 [1 << 17]byte var x9855 [1 << 17]byte var x9856 [1 << 17]byte var x9857 [1 << 17]byte var x9858 [1 << 17]byte var x9859 [1 << 17]byte var x9860 [1 << 17]byte var x9861 [1 << 17]byte var x9862 [1 << 17]byte var x9863 [1 << 17]byte var x9864 [1 << 17]byte var x9865 [1 << 17]byte var x9866 [1 << 17]byte var x9867 [1 << 17]byte var x9868 [1 << 17]byte var x9869 [1 << 17]byte var x9870 [1 << 17]byte var x9871 [1 << 17]byte var x9872 [1 << 17]byte var x9873 [1 << 17]byte var x9874 [1 << 17]byte var x9875 [1 << 17]byte var x9876 [1 << 17]byte var x9877 [1 << 17]byte var x9878 [1 << 17]byte var x9879 [1 << 17]byte var x9880 [1 << 17]byte var x9881 [1 << 17]byte var x9882 [1 << 17]byte var x9883 [1 << 17]byte var x9884 [1 << 17]byte var x9885 [1 << 17]byte var x9886 [1 << 17]byte var x9887 [1 << 17]byte var x9888 [1 << 17]byte var x9889 [1 << 17]byte var x9890 [1 << 17]byte var x9891 [1 << 17]byte var x9892 [1 << 17]byte var x9893 [1 << 17]byte var x9894 [1 << 17]byte var x9895 [1 << 17]byte var x9896 [1 << 17]byte var x9897 [1 << 17]byte var x9898 [1 << 17]byte var x9899 [1 << 17]byte var x9900 [1 << 17]byte var x9901 [1 << 17]byte var x9902 [1 << 17]byte var x9903 [1 << 17]byte var x9904 [1 << 17]byte var x9905 [1 << 17]byte var x9906 [1 << 17]byte var x9907 [1 << 17]byte var x9908 [1 << 17]byte var x9909 [1 << 17]byte var x9910 [1 << 17]byte var x9911 [1 << 17]byte var x9912 [1 << 17]byte var x9913 [1 << 17]byte var x9914 [1 << 17]byte var x9915 [1 << 17]byte var x9916 [1 << 17]byte var x9917 [1 << 17]byte var x9918 [1 << 17]byte var x9919 [1 << 17]byte var x9920 [1 << 17]byte var x9921 [1 << 17]byte var x9922 [1 << 17]byte var x9923 [1 << 17]byte var x9924 [1 << 17]byte var x9925 [1 << 17]byte var x9926 [1 << 17]byte var x9927 [1 << 17]byte var x9928 [1 << 17]byte var x9929 [1 << 17]byte var x9930 [1 << 17]byte var x9931 [1 << 17]byte var x9932 [1 << 17]byte var x9933 [1 << 17]byte var x9934 [1 << 17]byte var x9935 [1 << 17]byte var x9936 [1 << 17]byte var x9937 [1 << 17]byte var x9938 [1 << 17]byte var x9939 [1 << 17]byte var x9940 [1 << 17]byte var x9941 [1 << 17]byte var x9942 [1 << 17]byte var x9943 [1 << 17]byte var x9944 [1 << 17]byte var x9945 [1 << 17]byte var x9946 [1 << 17]byte var x9947 [1 << 17]byte var x9948 [1 << 17]byte var x9949 [1 << 17]byte var x9950 [1 << 17]byte var x9951 [1 << 17]byte var x9952 [1 << 17]byte var x9953 [1 << 17]byte var x9954 [1 << 17]byte var x9955 [1 << 17]byte var x9956 [1 << 17]byte var x9957 [1 << 17]byte var x9958 [1 << 17]byte var x9959 [1 << 17]byte var x9960 [1 << 17]byte var x9961 [1 << 17]byte var x9962 [1 << 17]byte var x9963 [1 << 17]byte var x9964 [1 << 17]byte var x9965 [1 << 17]byte var x9966 [1 << 17]byte var x9967 [1 << 17]byte var x9968 [1 << 17]byte var x9969 [1 << 17]byte var x9970 [1 << 17]byte var x9971 [1 << 17]byte var x9972 [1 << 17]byte var x9973 [1 << 17]byte var x9974 [1 << 17]byte var x9975 [1 << 17]byte var x9976 [1 << 17]byte var x9977 [1 << 17]byte var x9978 [1 << 17]byte var x9979 [1 << 17]byte var x9980 [1 << 17]byte var x9981 [1 << 17]byte var x9982 [1 << 17]byte var x9983 [1 << 17]byte var x9984 [1 << 17]byte var x9985 [1 << 17]byte var x9986 [1 << 17]byte var x9987 [1 << 17]byte var x9988 [1 << 17]byte var x9989 [1 << 17]byte var x9990 [1 << 17]byte var x9991 [1 << 17]byte var x9992 [1 << 17]byte var x9993 [1 << 17]byte var x9994 [1 << 17]byte var x9995 [1 << 17]byte var x9996 [1 << 17]byte var x9997 [1 << 17]byte var x9998 [1 << 17]byte var x9999 [1 << 17]byte var x10000 [1 << 17]byte var x10001 [1 << 17]byte var x10002 [1 << 17]byte var x10003 [1 << 17]byte var x10004 [1 << 17]byte var x10005 [1 << 17]byte var x10006 [1 << 17]byte var x10007 [1 << 17]byte var x10008 [1 << 17]byte var x10009 [1 << 17]byte var x10010 [1 << 17]byte var x10011 [1 << 17]byte var x10012 [1 << 17]byte var x10013 [1 << 17]byte var x10014 [1 << 17]byte var x10015 [1 << 17]byte var x10016 [1 << 17]byte var x10017 [1 << 17]byte var x10018 [1 << 17]byte var x10019 [1 << 17]byte var x10020 [1 << 17]byte var x10021 [1 << 17]byte var x10022 [1 << 17]byte var x10023 [1 << 17]byte var x10024 [1 << 17]byte var x10025 [1 << 17]byte var x10026 [1 << 17]byte var x10027 [1 << 17]byte var x10028 [1 << 17]byte var x10029 [1 << 17]byte var x10030 [1 << 17]byte var x10031 [1 << 17]byte var x10032 [1 << 17]byte var x10033 [1 << 17]byte var x10034 [1 << 17]byte var x10035 [1 << 17]byte var x10036 [1 << 17]byte var x10037 [1 << 17]byte var x10038 [1 << 17]byte var x10039 [1 << 17]byte var x10040 [1 << 17]byte var x10041 [1 << 17]byte var x10042 [1 << 17]byte var x10043 [1 << 17]byte var x10044 [1 << 17]byte var x10045 [1 << 17]byte var x10046 [1 << 17]byte var x10047 [1 << 17]byte var x10048 [1 << 17]byte var x10049 [1 << 17]byte var x10050 [1 << 17]byte var x10051 [1 << 17]byte var x10052 [1 << 17]byte var x10053 [1 << 17]byte var x10054 [1 << 17]byte var x10055 [1 << 17]byte var x10056 [1 << 17]byte var x10057 [1 << 17]byte var x10058 [1 << 17]byte var x10059 [1 << 17]byte var x10060 [1 << 17]byte var x10061 [1 << 17]byte var x10062 [1 << 17]byte var x10063 [1 << 17]byte var x10064 [1 << 17]byte var x10065 [1 << 17]byte var x10066 [1 << 17]byte var x10067 [1 << 17]byte var x10068 [1 << 17]byte var x10069 [1 << 17]byte var x10070 [1 << 17]byte var x10071 [1 << 17]byte var x10072 [1 << 17]byte var x10073 [1 << 17]byte var x10074 [1 << 17]byte var x10075 [1 << 17]byte var x10076 [1 << 17]byte var x10077 [1 << 17]byte var x10078 [1 << 17]byte var x10079 [1 << 17]byte var x10080 [1 << 17]byte var x10081 [1 << 17]byte var x10082 [1 << 17]byte var x10083 [1 << 17]byte var x10084 [1 << 17]byte var x10085 [1 << 17]byte var x10086 [1 << 17]byte var x10087 [1 << 17]byte var x10088 [1 << 17]byte var x10089 [1 << 17]byte var x10090 [1 << 17]byte var x10091 [1 << 17]byte var x10092 [1 << 17]byte var x10093 [1 << 17]byte var x10094 [1 << 17]byte var x10095 [1 << 17]byte var x10096 [1 << 17]byte var x10097 [1 << 17]byte var x10098 [1 << 17]byte var x10099 [1 << 17]byte var x10100 [1 << 17]byte var x10101 [1 << 17]byte var x10102 [1 << 17]byte var x10103 [1 << 17]byte var x10104 [1 << 17]byte var x10105 [1 << 17]byte var x10106 [1 << 17]byte var x10107 [1 << 17]byte var x10108 [1 << 17]byte var x10109 [1 << 17]byte var x10110 [1 << 17]byte var x10111 [1 << 17]byte var x10112 [1 << 17]byte var x10113 [1 << 17]byte var x10114 [1 << 17]byte var x10115 [1 << 17]byte var x10116 [1 << 17]byte var x10117 [1 << 17]byte var x10118 [1 << 17]byte var x10119 [1 << 17]byte var x10120 [1 << 17]byte var x10121 [1 << 17]byte var x10122 [1 << 17]byte var x10123 [1 << 17]byte var x10124 [1 << 17]byte var x10125 [1 << 17]byte var x10126 [1 << 17]byte var x10127 [1 << 17]byte var x10128 [1 << 17]byte var x10129 [1 << 17]byte var x10130 [1 << 17]byte var x10131 [1 << 17]byte var x10132 [1 << 17]byte var x10133 [1 << 17]byte var x10134 [1 << 17]byte var x10135 [1 << 17]byte var x10136 [1 << 17]byte var x10137 [1 << 17]byte var x10138 [1 << 17]byte var x10139 [1 << 17]byte var x10140 [1 << 17]byte var x10141 [1 << 17]byte var x10142 [1 << 17]byte var x10143 [1 << 17]byte var x10144 [1 << 17]byte var x10145 [1 << 17]byte var x10146 [1 << 17]byte var x10147 [1 << 17]byte var x10148 [1 << 17]byte var x10149 [1 << 17]byte var x10150 [1 << 17]byte var x10151 [1 << 17]byte var x10152 [1 << 17]byte var x10153 [1 << 17]byte var x10154 [1 << 17]byte var x10155 [1 << 17]byte var x10156 [1 << 17]byte var x10157 [1 << 17]byte var x10158 [1 << 17]byte var x10159 [1 << 17]byte var x10160 [1 << 17]byte var x10161 [1 << 17]byte var x10162 [1 << 17]byte var x10163 [1 << 17]byte var x10164 [1 << 17]byte var x10165 [1 << 17]byte var x10166 [1 << 17]byte var x10167 [1 << 17]byte var x10168 [1 << 17]byte var x10169 [1 << 17]byte var x10170 [1 << 17]byte var x10171 [1 << 17]byte var x10172 [1 << 17]byte var x10173 [1 << 17]byte var x10174 [1 << 17]byte var x10175 [1 << 17]byte var x10176 [1 << 17]byte var x10177 [1 << 17]byte var x10178 [1 << 17]byte var x10179 [1 << 17]byte var x10180 [1 << 17]byte var x10181 [1 << 17]byte var x10182 [1 << 17]byte var x10183 [1 << 17]byte var x10184 [1 << 17]byte var x10185 [1 << 17]byte var x10186 [1 << 17]byte var x10187 [1 << 17]byte var x10188 [1 << 17]byte var x10189 [1 << 17]byte var x10190 [1 << 17]byte var x10191 [1 << 17]byte var x10192 [1 << 17]byte var x10193 [1 << 17]byte var x10194 [1 << 17]byte var x10195 [1 << 17]byte var x10196 [1 << 17]byte var x10197 [1 << 17]byte var x10198 [1 << 17]byte var x10199 [1 << 17]byte var x10200 [1 << 17]byte var x10201 [1 << 17]byte var x10202 [1 << 17]byte var x10203 [1 << 17]byte var x10204 [1 << 17]byte var x10205 [1 << 17]byte var x10206 [1 << 17]byte var x10207 [1 << 17]byte var x10208 [1 << 17]byte var x10209 [1 << 17]byte var x10210 [1 << 17]byte var x10211 [1 << 17]byte var x10212 [1 << 17]byte var x10213 [1 << 17]byte var x10214 [1 << 17]byte var x10215 [1 << 17]byte var x10216 [1 << 17]byte var x10217 [1 << 17]byte var x10218 [1 << 17]byte var x10219 [1 << 17]byte var x10220 [1 << 17]byte var x10221 [1 << 17]byte var x10222 [1 << 17]byte var x10223 [1 << 17]byte var x10224 [1 << 17]byte var x10225 [1 << 17]byte var x10226 [1 << 17]byte var x10227 [1 << 17]byte var x10228 [1 << 17]byte var x10229 [1 << 17]byte var x10230 [1 << 17]byte var x10231 [1 << 17]byte var x10232 [1 << 17]byte var x10233 [1 << 17]byte var x10234 [1 << 17]byte var x10235 [1 << 17]byte var x10236 [1 << 17]byte var x10237 [1 << 17]byte var x10238 [1 << 17]byte var x10239 [1 << 17]byte var x10240 [1 << 17]byte var x10241 [1 << 17]byte var x10242 [1 << 17]byte var x10243 [1 << 17]byte var x10244 [1 << 17]byte var x10245 [1 << 17]byte var x10246 [1 << 17]byte var x10247 [1 << 17]byte var x10248 [1 << 17]byte var x10249 [1 << 17]byte var x10250 [1 << 17]byte var x10251 [1 << 17]byte var x10252 [1 << 17]byte var x10253 [1 << 17]byte var x10254 [1 << 17]byte var x10255 [1 << 17]byte var x10256 [1 << 17]byte var x10257 [1 << 17]byte var x10258 [1 << 17]byte var x10259 [1 << 17]byte var x10260 [1 << 17]byte var x10261 [1 << 17]byte var x10262 [1 << 17]byte var x10263 [1 << 17]byte var x10264 [1 << 17]byte var x10265 [1 << 17]byte var x10266 [1 << 17]byte var x10267 [1 << 17]byte var x10268 [1 << 17]byte var x10269 [1 << 17]byte var x10270 [1 << 17]byte var x10271 [1 << 17]byte var x10272 [1 << 17]byte var x10273 [1 << 17]byte var x10274 [1 << 17]byte var x10275 [1 << 17]byte var x10276 [1 << 17]byte var x10277 [1 << 17]byte var x10278 [1 << 17]byte var x10279 [1 << 17]byte var x10280 [1 << 17]byte var x10281 [1 << 17]byte var x10282 [1 << 17]byte var x10283 [1 << 17]byte var x10284 [1 << 17]byte var x10285 [1 << 17]byte var x10286 [1 << 17]byte var x10287 [1 << 17]byte var x10288 [1 << 17]byte var x10289 [1 << 17]byte var x10290 [1 << 17]byte var x10291 [1 << 17]byte var x10292 [1 << 17]byte var x10293 [1 << 17]byte var x10294 [1 << 17]byte var x10295 [1 << 17]byte var x10296 [1 << 17]byte var x10297 [1 << 17]byte var x10298 [1 << 17]byte var x10299 [1 << 17]byte var x10300 [1 << 17]byte var x10301 [1 << 17]byte var x10302 [1 << 17]byte var x10303 [1 << 17]byte var x10304 [1 << 17]byte var x10305 [1 << 17]byte var x10306 [1 << 17]byte var x10307 [1 << 17]byte var x10308 [1 << 17]byte var x10309 [1 << 17]byte var x10310 [1 << 17]byte var x10311 [1 << 17]byte var x10312 [1 << 17]byte var x10313 [1 << 17]byte var x10314 [1 << 17]byte var x10315 [1 << 17]byte var x10316 [1 << 17]byte var x10317 [1 << 17]byte var x10318 [1 << 17]byte var x10319 [1 << 17]byte var x10320 [1 << 17]byte var x10321 [1 << 17]byte var x10322 [1 << 17]byte var x10323 [1 << 17]byte var x10324 [1 << 17]byte var x10325 [1 << 17]byte var x10326 [1 << 17]byte var x10327 [1 << 17]byte var x10328 [1 << 17]byte var x10329 [1 << 17]byte var x10330 [1 << 17]byte var x10331 [1 << 17]byte var x10332 [1 << 17]byte var x10333 [1 << 17]byte var x10334 [1 << 17]byte var x10335 [1 << 17]byte var x10336 [1 << 17]byte var x10337 [1 << 17]byte var x10338 [1 << 17]byte var x10339 [1 << 17]byte var x10340 [1 << 17]byte var x10341 [1 << 17]byte var x10342 [1 << 17]byte var x10343 [1 << 17]byte var x10344 [1 << 17]byte var x10345 [1 << 17]byte var x10346 [1 << 17]byte var x10347 [1 << 17]byte var x10348 [1 << 17]byte var x10349 [1 << 17]byte var x10350 [1 << 17]byte var x10351 [1 << 17]byte var x10352 [1 << 17]byte var x10353 [1 << 17]byte var x10354 [1 << 17]byte var x10355 [1 << 17]byte var x10356 [1 << 17]byte var x10357 [1 << 17]byte var x10358 [1 << 17]byte var x10359 [1 << 17]byte var x10360 [1 << 17]byte var x10361 [1 << 17]byte var x10362 [1 << 17]byte var x10363 [1 << 17]byte var x10364 [1 << 17]byte var x10365 [1 << 17]byte var x10366 [1 << 17]byte var x10367 [1 << 17]byte var x10368 [1 << 17]byte var x10369 [1 << 17]byte var x10370 [1 << 17]byte var x10371 [1 << 17]byte var x10372 [1 << 17]byte var x10373 [1 << 17]byte var x10374 [1 << 17]byte var x10375 [1 << 17]byte var x10376 [1 << 17]byte var x10377 [1 << 17]byte var x10378 [1 << 17]byte var x10379 [1 << 17]byte var x10380 [1 << 17]byte var x10381 [1 << 17]byte var x10382 [1 << 17]byte var x10383 [1 << 17]byte var x10384 [1 << 17]byte var x10385 [1 << 17]byte var x10386 [1 << 17]byte var x10387 [1 << 17]byte var x10388 [1 << 17]byte var x10389 [1 << 17]byte var x10390 [1 << 17]byte var x10391 [1 << 17]byte var x10392 [1 << 17]byte var x10393 [1 << 17]byte var x10394 [1 << 17]byte var x10395 [1 << 17]byte var x10396 [1 << 17]byte var x10397 [1 << 17]byte var x10398 [1 << 17]byte var x10399 [1 << 17]byte var x10400 [1 << 17]byte var x10401 [1 << 17]byte var x10402 [1 << 17]byte var x10403 [1 << 17]byte var x10404 [1 << 17]byte var x10405 [1 << 17]byte var x10406 [1 << 17]byte var x10407 [1 << 17]byte var x10408 [1 << 17]byte var x10409 [1 << 17]byte var x10410 [1 << 17]byte var x10411 [1 << 17]byte var x10412 [1 << 17]byte var x10413 [1 << 17]byte var x10414 [1 << 17]byte var x10415 [1 << 17]byte var x10416 [1 << 17]byte var x10417 [1 << 17]byte var x10418 [1 << 17]byte var x10419 [1 << 17]byte var x10420 [1 << 17]byte var x10421 [1 << 17]byte var x10422 [1 << 17]byte var x10423 [1 << 17]byte var x10424 [1 << 17]byte var x10425 [1 << 17]byte var x10426 [1 << 17]byte var x10427 [1 << 17]byte var x10428 [1 << 17]byte var x10429 [1 << 17]byte var x10430 [1 << 17]byte var x10431 [1 << 17]byte var x10432 [1 << 17]byte var x10433 [1 << 17]byte var x10434 [1 << 17]byte var x10435 [1 << 17]byte var x10436 [1 << 17]byte var x10437 [1 << 17]byte var x10438 [1 << 17]byte var x10439 [1 << 17]byte var x10440 [1 << 17]byte var x10441 [1 << 17]byte var x10442 [1 << 17]byte var x10443 [1 << 17]byte var x10444 [1 << 17]byte var x10445 [1 << 17]byte var x10446 [1 << 17]byte var x10447 [1 << 17]byte var x10448 [1 << 17]byte var x10449 [1 << 17]byte var x10450 [1 << 17]byte var x10451 [1 << 17]byte var x10452 [1 << 17]byte var x10453 [1 << 17]byte var x10454 [1 << 17]byte var x10455 [1 << 17]byte var x10456 [1 << 17]byte var x10457 [1 << 17]byte var x10458 [1 << 17]byte var x10459 [1 << 17]byte var x10460 [1 << 17]byte var x10461 [1 << 17]byte var x10462 [1 << 17]byte var x10463 [1 << 17]byte var x10464 [1 << 17]byte var x10465 [1 << 17]byte var x10466 [1 << 17]byte var x10467 [1 << 17]byte var x10468 [1 << 17]byte var x10469 [1 << 17]byte var x10470 [1 << 17]byte var x10471 [1 << 17]byte var x10472 [1 << 17]byte var x10473 [1 << 17]byte var x10474 [1 << 17]byte var x10475 [1 << 17]byte var x10476 [1 << 17]byte var x10477 [1 << 17]byte var x10478 [1 << 17]byte var x10479 [1 << 17]byte var x10480 [1 << 17]byte var x10481 [1 << 17]byte var x10482 [1 << 17]byte var x10483 [1 << 17]byte var x10484 [1 << 17]byte var x10485 [1 << 17]byte var x10486 [1 << 17]byte var x10487 [1 << 17]byte var x10488 [1 << 17]byte var x10489 [1 << 17]byte var x10490 [1 << 17]byte var x10491 [1 << 17]byte var x10492 [1 << 17]byte var x10493 [1 << 17]byte var x10494 [1 << 17]byte var x10495 [1 << 17]byte var x10496 [1 << 17]byte var x10497 [1 << 17]byte var x10498 [1 << 17]byte var x10499 [1 << 17]byte var x10500 [1 << 17]byte var x10501 [1 << 17]byte var x10502 [1 << 17]byte var x10503 [1 << 17]byte var x10504 [1 << 17]byte var x10505 [1 << 17]byte var x10506 [1 << 17]byte var x10507 [1 << 17]byte var x10508 [1 << 17]byte var x10509 [1 << 17]byte var x10510 [1 << 17]byte var x10511 [1 << 17]byte var x10512 [1 << 17]byte var x10513 [1 << 17]byte var x10514 [1 << 17]byte var x10515 [1 << 17]byte var x10516 [1 << 17]byte var x10517 [1 << 17]byte var x10518 [1 << 17]byte var x10519 [1 << 17]byte var x10520 [1 << 17]byte var x10521 [1 << 17]byte var x10522 [1 << 17]byte var x10523 [1 << 17]byte var x10524 [1 << 17]byte var x10525 [1 << 17]byte var x10526 [1 << 17]byte var x10527 [1 << 17]byte var x10528 [1 << 17]byte var x10529 [1 << 17]byte var x10530 [1 << 17]byte var x10531 [1 << 17]byte var x10532 [1 << 17]byte var x10533 [1 << 17]byte var x10534 [1 << 17]byte var x10535 [1 << 17]byte var x10536 [1 << 17]byte var x10537 [1 << 17]byte var x10538 [1 << 17]byte var x10539 [1 << 17]byte var x10540 [1 << 17]byte var x10541 [1 << 17]byte var x10542 [1 << 17]byte var x10543 [1 << 17]byte var x10544 [1 << 17]byte var x10545 [1 << 17]byte var x10546 [1 << 17]byte var x10547 [1 << 17]byte var x10548 [1 << 17]byte var x10549 [1 << 17]byte var x10550 [1 << 17]byte var x10551 [1 << 17]byte var x10552 [1 << 17]byte var x10553 [1 << 17]byte var x10554 [1 << 17]byte var x10555 [1 << 17]byte var x10556 [1 << 17]byte var x10557 [1 << 17]byte var x10558 [1 << 17]byte var x10559 [1 << 17]byte var x10560 [1 << 17]byte var x10561 [1 << 17]byte var x10562 [1 << 17]byte var x10563 [1 << 17]byte var x10564 [1 << 17]byte var x10565 [1 << 17]byte var x10566 [1 << 17]byte var x10567 [1 << 17]byte var x10568 [1 << 17]byte var x10569 [1 << 17]byte var x10570 [1 << 17]byte var x10571 [1 << 17]byte var x10572 [1 << 17]byte var x10573 [1 << 17]byte var x10574 [1 << 17]byte var x10575 [1 << 17]byte var x10576 [1 << 17]byte var x10577 [1 << 17]byte var x10578 [1 << 17]byte var x10579 [1 << 17]byte var x10580 [1 << 17]byte var x10581 [1 << 17]byte var x10582 [1 << 17]byte var x10583 [1 << 17]byte var x10584 [1 << 17]byte var x10585 [1 << 17]byte var x10586 [1 << 17]byte var x10587 [1 << 17]byte var x10588 [1 << 17]byte var x10589 [1 << 17]byte var x10590 [1 << 17]byte var x10591 [1 << 17]byte var x10592 [1 << 17]byte var x10593 [1 << 17]byte var x10594 [1 << 17]byte var x10595 [1 << 17]byte var x10596 [1 << 17]byte var x10597 [1 << 17]byte var x10598 [1 << 17]byte var x10599 [1 << 17]byte var x10600 [1 << 17]byte var x10601 [1 << 17]byte var x10602 [1 << 17]byte var x10603 [1 << 17]byte var x10604 [1 << 17]byte var x10605 [1 << 17]byte var x10606 [1 << 17]byte var x10607 [1 << 17]byte var x10608 [1 << 17]byte var x10609 [1 << 17]byte var x10610 [1 << 17]byte var x10611 [1 << 17]byte var x10612 [1 << 17]byte var x10613 [1 << 17]byte var x10614 [1 << 17]byte var x10615 [1 << 17]byte var x10616 [1 << 17]byte var x10617 [1 << 17]byte var x10618 [1 << 17]byte var x10619 [1 << 17]byte var x10620 [1 << 17]byte var x10621 [1 << 17]byte var x10622 [1 << 17]byte var x10623 [1 << 17]byte var x10624 [1 << 17]byte var x10625 [1 << 17]byte var x10626 [1 << 17]byte var x10627 [1 << 17]byte var x10628 [1 << 17]byte var x10629 [1 << 17]byte var x10630 [1 << 17]byte var x10631 [1 << 17]byte var x10632 [1 << 17]byte var x10633 [1 << 17]byte var x10634 [1 << 17]byte var x10635 [1 << 17]byte var x10636 [1 << 17]byte var x10637 [1 << 17]byte var x10638 [1 << 17]byte var x10639 [1 << 17]byte var x10640 [1 << 17]byte var x10641 [1 << 17]byte var x10642 [1 << 17]byte var x10643 [1 << 17]byte var x10644 [1 << 17]byte var x10645 [1 << 17]byte var x10646 [1 << 17]byte var x10647 [1 << 17]byte var x10648 [1 << 17]byte var x10649 [1 << 17]byte var x10650 [1 << 17]byte var x10651 [1 << 17]byte var x10652 [1 << 17]byte var x10653 [1 << 17]byte var x10654 [1 << 17]byte var x10655 [1 << 17]byte var x10656 [1 << 17]byte var x10657 [1 << 17]byte var x10658 [1 << 17]byte var x10659 [1 << 17]byte var x10660 [1 << 17]byte var x10661 [1 << 17]byte var x10662 [1 << 17]byte var x10663 [1 << 17]byte var x10664 [1 << 17]byte var x10665 [1 << 17]byte var x10666 [1 << 17]byte var x10667 [1 << 17]byte var x10668 [1 << 17]byte var x10669 [1 << 17]byte var x10670 [1 << 17]byte var x10671 [1 << 17]byte var x10672 [1 << 17]byte var x10673 [1 << 17]byte var x10674 [1 << 17]byte var x10675 [1 << 17]byte var x10676 [1 << 17]byte var x10677 [1 << 17]byte var x10678 [1 << 17]byte var x10679 [1 << 17]byte var x10680 [1 << 17]byte var x10681 [1 << 17]byte var x10682 [1 << 17]byte var x10683 [1 << 17]byte var x10684 [1 << 17]byte var x10685 [1 << 17]byte var x10686 [1 << 17]byte var x10687 [1 << 17]byte var x10688 [1 << 17]byte var x10689 [1 << 17]byte var x10690 [1 << 17]byte var x10691 [1 << 17]byte var x10692 [1 << 17]byte var x10693 [1 << 17]byte var x10694 [1 << 17]byte var x10695 [1 << 17]byte var x10696 [1 << 17]byte var x10697 [1 << 17]byte var x10698 [1 << 17]byte var x10699 [1 << 17]byte var x10700 [1 << 17]byte var x10701 [1 << 17]byte var x10702 [1 << 17]byte var x10703 [1 << 17]byte var x10704 [1 << 17]byte var x10705 [1 << 17]byte var x10706 [1 << 17]byte var x10707 [1 << 17]byte var x10708 [1 << 17]byte var x10709 [1 << 17]byte var x10710 [1 << 17]byte var x10711 [1 << 17]byte var x10712 [1 << 17]byte var x10713 [1 << 17]byte var x10714 [1 << 17]byte var x10715 [1 << 17]byte var x10716 [1 << 17]byte var x10717 [1 << 17]byte var x10718 [1 << 17]byte var x10719 [1 << 17]byte var x10720 [1 << 17]byte var x10721 [1 << 17]byte var x10722 [1 << 17]byte var x10723 [1 << 17]byte var x10724 [1 << 17]byte var x10725 [1 << 17]byte var x10726 [1 << 17]byte var x10727 [1 << 17]byte var x10728 [1 << 17]byte var x10729 [1 << 17]byte var x10730 [1 << 17]byte var x10731 [1 << 17]byte var x10732 [1 << 17]byte var x10733 [1 << 17]byte var x10734 [1 << 17]byte var x10735 [1 << 17]byte var x10736 [1 << 17]byte var x10737 [1 << 17]byte var x10738 [1 << 17]byte var x10739 [1 << 17]byte var x10740 [1 << 17]byte var x10741 [1 << 17]byte var x10742 [1 << 17]byte var x10743 [1 << 17]byte var x10744 [1 << 17]byte var x10745 [1 << 17]byte var x10746 [1 << 17]byte var x10747 [1 << 17]byte var x10748 [1 << 17]byte var x10749 [1 << 17]byte var x10750 [1 << 17]byte var x10751 [1 << 17]byte var x10752 [1 << 17]byte var x10753 [1 << 17]byte var x10754 [1 << 17]byte var x10755 [1 << 17]byte var x10756 [1 << 17]byte var x10757 [1 << 17]byte var x10758 [1 << 17]byte var x10759 [1 << 17]byte var x10760 [1 << 17]byte var x10761 [1 << 17]byte var x10762 [1 << 17]byte var x10763 [1 << 17]byte var x10764 [1 << 17]byte var x10765 [1 << 17]byte var x10766 [1 << 17]byte var x10767 [1 << 17]byte var x10768 [1 << 17]byte var x10769 [1 << 17]byte var x10770 [1 << 17]byte var x10771 [1 << 17]byte var x10772 [1 << 17]byte var x10773 [1 << 17]byte var x10774 [1 << 17]byte var x10775 [1 << 17]byte var x10776 [1 << 17]byte var x10777 [1 << 17]byte var x10778 [1 << 17]byte var x10779 [1 << 17]byte var x10780 [1 << 17]byte var x10781 [1 << 17]byte var x10782 [1 << 17]byte var x10783 [1 << 17]byte var x10784 [1 << 17]byte var x10785 [1 << 17]byte var x10786 [1 << 17]byte var x10787 [1 << 17]byte var x10788 [1 << 17]byte var x10789 [1 << 17]byte var x10790 [1 << 17]byte var x10791 [1 << 17]byte var x10792 [1 << 17]byte var x10793 [1 << 17]byte var x10794 [1 << 17]byte var x10795 [1 << 17]byte var x10796 [1 << 17]byte var x10797 [1 << 17]byte var x10798 [1 << 17]byte var x10799 [1 << 17]byte var x10800 [1 << 17]byte var x10801 [1 << 17]byte var x10802 [1 << 17]byte var x10803 [1 << 17]byte var x10804 [1 << 17]byte var x10805 [1 << 17]byte var x10806 [1 << 17]byte var x10807 [1 << 17]byte var x10808 [1 << 17]byte var x10809 [1 << 17]byte var x10810 [1 << 17]byte var x10811 [1 << 17]byte var x10812 [1 << 17]byte var x10813 [1 << 17]byte var x10814 [1 << 17]byte var x10815 [1 << 17]byte var x10816 [1 << 17]byte var x10817 [1 << 17]byte var x10818 [1 << 17]byte var x10819 [1 << 17]byte var x10820 [1 << 17]byte var x10821 [1 << 17]byte var x10822 [1 << 17]byte var x10823 [1 << 17]byte var x10824 [1 << 17]byte var x10825 [1 << 17]byte var x10826 [1 << 17]byte var x10827 [1 << 17]byte var x10828 [1 << 17]byte var x10829 [1 << 17]byte var x10830 [1 << 17]byte var x10831 [1 << 17]byte var x10832 [1 << 17]byte var x10833 [1 << 17]byte var x10834 [1 << 17]byte var x10835 [1 << 17]byte var x10836 [1 << 17]byte var x10837 [1 << 17]byte var x10838 [1 << 17]byte var x10839 [1 << 17]byte var x10840 [1 << 17]byte var x10841 [1 << 17]byte var x10842 [1 << 17]byte var x10843 [1 << 17]byte var x10844 [1 << 17]byte var x10845 [1 << 17]byte var x10846 [1 << 17]byte var x10847 [1 << 17]byte var x10848 [1 << 17]byte var x10849 [1 << 17]byte var x10850 [1 << 17]byte var x10851 [1 << 17]byte var x10852 [1 << 17]byte var x10853 [1 << 17]byte var x10854 [1 << 17]byte var x10855 [1 << 17]byte var x10856 [1 << 17]byte var x10857 [1 << 17]byte var x10858 [1 << 17]byte var x10859 [1 << 17]byte var x10860 [1 << 17]byte var x10861 [1 << 17]byte var x10862 [1 << 17]byte var x10863 [1 << 17]byte var x10864 [1 << 17]byte var x10865 [1 << 17]byte var x10866 [1 << 17]byte var x10867 [1 << 17]byte var x10868 [1 << 17]byte var x10869 [1 << 17]byte var x10870 [1 << 17]byte var x10871 [1 << 17]byte var x10872 [1 << 17]byte var x10873 [1 << 17]byte var x10874 [1 << 17]byte var x10875 [1 << 17]byte var x10876 [1 << 17]byte var x10877 [1 << 17]byte var x10878 [1 << 17]byte var x10879 [1 << 17]byte var x10880 [1 << 17]byte var x10881 [1 << 17]byte var x10882 [1 << 17]byte var x10883 [1 << 17]byte var x10884 [1 << 17]byte var x10885 [1 << 17]byte var x10886 [1 << 17]byte var x10887 [1 << 17]byte var x10888 [1 << 17]byte var x10889 [1 << 17]byte var x10890 [1 << 17]byte var x10891 [1 << 17]byte var x10892 [1 << 17]byte var x10893 [1 << 17]byte var x10894 [1 << 17]byte var x10895 [1 << 17]byte var x10896 [1 << 17]byte var x10897 [1 << 17]byte var x10898 [1 << 17]byte var x10899 [1 << 17]byte var x10900 [1 << 17]byte var x10901 [1 << 17]byte var x10902 [1 << 17]byte var x10903 [1 << 17]byte var x10904 [1 << 17]byte var x10905 [1 << 17]byte var x10906 [1 << 17]byte var x10907 [1 << 17]byte var x10908 [1 << 17]byte var x10909 [1 << 17]byte var x10910 [1 << 17]byte var x10911 [1 << 17]byte var x10912 [1 << 17]byte var x10913 [1 << 17]byte var x10914 [1 << 17]byte var x10915 [1 << 17]byte var x10916 [1 << 17]byte var x10917 [1 << 17]byte var x10918 [1 << 17]byte var x10919 [1 << 17]byte var x10920 [1 << 17]byte var x10921 [1 << 17]byte var x10922 [1 << 17]byte var x10923 [1 << 17]byte var x10924 [1 << 17]byte var x10925 [1 << 17]byte var x10926 [1 << 17]byte var x10927 [1 << 17]byte var x10928 [1 << 17]byte var x10929 [1 << 17]byte var x10930 [1 << 17]byte var x10931 [1 << 17]byte var x10932 [1 << 17]byte var x10933 [1 << 17]byte var x10934 [1 << 17]byte var x10935 [1 << 17]byte var x10936 [1 << 17]byte var x10937 [1 << 17]byte var x10938 [1 << 17]byte var x10939 [1 << 17]byte var x10940 [1 << 17]byte var x10941 [1 << 17]byte var x10942 [1 << 17]byte var x10943 [1 << 17]byte var x10944 [1 << 17]byte var x10945 [1 << 17]byte var x10946 [1 << 17]byte var x10947 [1 << 17]byte var x10948 [1 << 17]byte var x10949 [1 << 17]byte var x10950 [1 << 17]byte var x10951 [1 << 17]byte var x10952 [1 << 17]byte var x10953 [1 << 17]byte var x10954 [1 << 17]byte var x10955 [1 << 17]byte var x10956 [1 << 17]byte var x10957 [1 << 17]byte var x10958 [1 << 17]byte var x10959 [1 << 17]byte var x10960 [1 << 17]byte var x10961 [1 << 17]byte var x10962 [1 << 17]byte var x10963 [1 << 17]byte var x10964 [1 << 17]byte var x10965 [1 << 17]byte var x10966 [1 << 17]byte var x10967 [1 << 17]byte var x10968 [1 << 17]byte var x10969 [1 << 17]byte var x10970 [1 << 17]byte var x10971 [1 << 17]byte var x10972 [1 << 17]byte var x10973 [1 << 17]byte var x10974 [1 << 17]byte var x10975 [1 << 17]byte var x10976 [1 << 17]byte var x10977 [1 << 17]byte var x10978 [1 << 17]byte var x10979 [1 << 17]byte var x10980 [1 << 17]byte var x10981 [1 << 17]byte var x10982 [1 << 17]byte var x10983 [1 << 17]byte var x10984 [1 << 17]byte var x10985 [1 << 17]byte var x10986 [1 << 17]byte var x10987 [1 << 17]byte var x10988 [1 << 17]byte var x10989 [1 << 17]byte var x10990 [1 << 17]byte var x10991 [1 << 17]byte var x10992 [1 << 17]byte var x10993 [1 << 17]byte var x10994 [1 << 17]byte var x10995 [1 << 17]byte var x10996 [1 << 17]byte var x10997 [1 << 17]byte var x10998 [1 << 17]byte var x10999 [1 << 17]byte var x11000 [1 << 17]byte var x11001 [1 << 17]byte var x11002 [1 << 17]byte var x11003 [1 << 17]byte var x11004 [1 << 17]byte var x11005 [1 << 17]byte var x11006 [1 << 17]byte var x11007 [1 << 17]byte var x11008 [1 << 17]byte var x11009 [1 << 17]byte var x11010 [1 << 17]byte var x11011 [1 << 17]byte var x11012 [1 << 17]byte var x11013 [1 << 17]byte var x11014 [1 << 17]byte var x11015 [1 << 17]byte var x11016 [1 << 17]byte var x11017 [1 << 17]byte var x11018 [1 << 17]byte var x11019 [1 << 17]byte var x11020 [1 << 17]byte var x11021 [1 << 17]byte var x11022 [1 << 17]byte var x11023 [1 << 17]byte var x11024 [1 << 17]byte var x11025 [1 << 17]byte var x11026 [1 << 17]byte var x11027 [1 << 17]byte var x11028 [1 << 17]byte var x11029 [1 << 17]byte var x11030 [1 << 17]byte var x11031 [1 << 17]byte var x11032 [1 << 17]byte var x11033 [1 << 17]byte var x11034 [1 << 17]byte var x11035 [1 << 17]byte var x11036 [1 << 17]byte var x11037 [1 << 17]byte var x11038 [1 << 17]byte var x11039 [1 << 17]byte var x11040 [1 << 17]byte var x11041 [1 << 17]byte var x11042 [1 << 17]byte var x11043 [1 << 17]byte var x11044 [1 << 17]byte var x11045 [1 << 17]byte var x11046 [1 << 17]byte var x11047 [1 << 17]byte var x11048 [1 << 17]byte var x11049 [1 << 17]byte var x11050 [1 << 17]byte var x11051 [1 << 17]byte var x11052 [1 << 17]byte var x11053 [1 << 17]byte var x11054 [1 << 17]byte var x11055 [1 << 17]byte var x11056 [1 << 17]byte var x11057 [1 << 17]byte var x11058 [1 << 17]byte var x11059 [1 << 17]byte var x11060 [1 << 17]byte var x11061 [1 << 17]byte var x11062 [1 << 17]byte var x11063 [1 << 17]byte var x11064 [1 << 17]byte var x11065 [1 << 17]byte var x11066 [1 << 17]byte var x11067 [1 << 17]byte var x11068 [1 << 17]byte var x11069 [1 << 17]byte var x11070 [1 << 17]byte var x11071 [1 << 17]byte var x11072 [1 << 17]byte var x11073 [1 << 17]byte var x11074 [1 << 17]byte var x11075 [1 << 17]byte var x11076 [1 << 17]byte var x11077 [1 << 17]byte var x11078 [1 << 17]byte var x11079 [1 << 17]byte var x11080 [1 << 17]byte var x11081 [1 << 17]byte var x11082 [1 << 17]byte var x11083 [1 << 17]byte var x11084 [1 << 17]byte var x11085 [1 << 17]byte var x11086 [1 << 17]byte var x11087 [1 << 17]byte var x11088 [1 << 17]byte var x11089 [1 << 17]byte var x11090 [1 << 17]byte var x11091 [1 << 17]byte var x11092 [1 << 17]byte var x11093 [1 << 17]byte var x11094 [1 << 17]byte var x11095 [1 << 17]byte var x11096 [1 << 17]byte var x11097 [1 << 17]byte var x11098 [1 << 17]byte var x11099 [1 << 17]byte var x11100 [1 << 17]byte var x11101 [1 << 17]byte var x11102 [1 << 17]byte var x11103 [1 << 17]byte var x11104 [1 << 17]byte var x11105 [1 << 17]byte var x11106 [1 << 17]byte var x11107 [1 << 17]byte var x11108 [1 << 17]byte var x11109 [1 << 17]byte var x11110 [1 << 17]byte var x11111 [1 << 17]byte var x11112 [1 << 17]byte var x11113 [1 << 17]byte var x11114 [1 << 17]byte var x11115 [1 << 17]byte var x11116 [1 << 17]byte var x11117 [1 << 17]byte var x11118 [1 << 17]byte var x11119 [1 << 17]byte var x11120 [1 << 17]byte var x11121 [1 << 17]byte var x11122 [1 << 17]byte var x11123 [1 << 17]byte var x11124 [1 << 17]byte var x11125 [1 << 17]byte var x11126 [1 << 17]byte var x11127 [1 << 17]byte var x11128 [1 << 17]byte var x11129 [1 << 17]byte var x11130 [1 << 17]byte var x11131 [1 << 17]byte var x11132 [1 << 17]byte var x11133 [1 << 17]byte var x11134 [1 << 17]byte var x11135 [1 << 17]byte var x11136 [1 << 17]byte var x11137 [1 << 17]byte var x11138 [1 << 17]byte var x11139 [1 << 17]byte var x11140 [1 << 17]byte var x11141 [1 << 17]byte var x11142 [1 << 17]byte var x11143 [1 << 17]byte var x11144 [1 << 17]byte var x11145 [1 << 17]byte var x11146 [1 << 17]byte var x11147 [1 << 17]byte var x11148 [1 << 17]byte var x11149 [1 << 17]byte var x11150 [1 << 17]byte var x11151 [1 << 17]byte var x11152 [1 << 17]byte var x11153 [1 << 17]byte var x11154 [1 << 17]byte var x11155 [1 << 17]byte var x11156 [1 << 17]byte var x11157 [1 << 17]byte var x11158 [1 << 17]byte var x11159 [1 << 17]byte var x11160 [1 << 17]byte var x11161 [1 << 17]byte var x11162 [1 << 17]byte var x11163 [1 << 17]byte var x11164 [1 << 17]byte var x11165 [1 << 17]byte var x11166 [1 << 17]byte var x11167 [1 << 17]byte var x11168 [1 << 17]byte var x11169 [1 << 17]byte var x11170 [1 << 17]byte var x11171 [1 << 17]byte var x11172 [1 << 17]byte var x11173 [1 << 17]byte var x11174 [1 << 17]byte var x11175 [1 << 17]byte var x11176 [1 << 17]byte var x11177 [1 << 17]byte var x11178 [1 << 17]byte var x11179 [1 << 17]byte var x11180 [1 << 17]byte var x11181 [1 << 17]byte var x11182 [1 << 17]byte var x11183 [1 << 17]byte var x11184 [1 << 17]byte var x11185 [1 << 17]byte var x11186 [1 << 17]byte var x11187 [1 << 17]byte var x11188 [1 << 17]byte var x11189 [1 << 17]byte var x11190 [1 << 17]byte var x11191 [1 << 17]byte var x11192 [1 << 17]byte var x11193 [1 << 17]byte var x11194 [1 << 17]byte var x11195 [1 << 17]byte var x11196 [1 << 17]byte var x11197 [1 << 17]byte var x11198 [1 << 17]byte var x11199 [1 << 17]byte var x11200 [1 << 17]byte var x11201 [1 << 17]byte var x11202 [1 << 17]byte var x11203 [1 << 17]byte var x11204 [1 << 17]byte var x11205 [1 << 17]byte var x11206 [1 << 17]byte var x11207 [1 << 17]byte var x11208 [1 << 17]byte var x11209 [1 << 17]byte var x11210 [1 << 17]byte var x11211 [1 << 17]byte var x11212 [1 << 17]byte var x11213 [1 << 17]byte var x11214 [1 << 17]byte var x11215 [1 << 17]byte var x11216 [1 << 17]byte var x11217 [1 << 17]byte var x11218 [1 << 17]byte var x11219 [1 << 17]byte var x11220 [1 << 17]byte var x11221 [1 << 17]byte var x11222 [1 << 17]byte var x11223 [1 << 17]byte var x11224 [1 << 17]byte var x11225 [1 << 17]byte var x11226 [1 << 17]byte var x11227 [1 << 17]byte var x11228 [1 << 17]byte var x11229 [1 << 17]byte var x11230 [1 << 17]byte var x11231 [1 << 17]byte var x11232 [1 << 17]byte var x11233 [1 << 17]byte var x11234 [1 << 17]byte var x11235 [1 << 17]byte var x11236 [1 << 17]byte var x11237 [1 << 17]byte var x11238 [1 << 17]byte var x11239 [1 << 17]byte var x11240 [1 << 17]byte var x11241 [1 << 17]byte var x11242 [1 << 17]byte var x11243 [1 << 17]byte var x11244 [1 << 17]byte var x11245 [1 << 17]byte var x11246 [1 << 17]byte var x11247 [1 << 17]byte var x11248 [1 << 17]byte var x11249 [1 << 17]byte var x11250 [1 << 17]byte var x11251 [1 << 17]byte var x11252 [1 << 17]byte var x11253 [1 << 17]byte var x11254 [1 << 17]byte var x11255 [1 << 17]byte var x11256 [1 << 17]byte var x11257 [1 << 17]byte var x11258 [1 << 17]byte var x11259 [1 << 17]byte var x11260 [1 << 17]byte var x11261 [1 << 17]byte var x11262 [1 << 17]byte var x11263 [1 << 17]byte var x11264 [1 << 17]byte var x11265 [1 << 17]byte var x11266 [1 << 17]byte var x11267 [1 << 17]byte var x11268 [1 << 17]byte var x11269 [1 << 17]byte var x11270 [1 << 17]byte var x11271 [1 << 17]byte var x11272 [1 << 17]byte var x11273 [1 << 17]byte var x11274 [1 << 17]byte var x11275 [1 << 17]byte var x11276 [1 << 17]byte var x11277 [1 << 17]byte var x11278 [1 << 17]byte var x11279 [1 << 17]byte var x11280 [1 << 17]byte var x11281 [1 << 17]byte var x11282 [1 << 17]byte var x11283 [1 << 17]byte var x11284 [1 << 17]byte var x11285 [1 << 17]byte var x11286 [1 << 17]byte var x11287 [1 << 17]byte var x11288 [1 << 17]byte var x11289 [1 << 17]byte var x11290 [1 << 17]byte var x11291 [1 << 17]byte var x11292 [1 << 17]byte var x11293 [1 << 17]byte var x11294 [1 << 17]byte var x11295 [1 << 17]byte var x11296 [1 << 17]byte var x11297 [1 << 17]byte var x11298 [1 << 17]byte var x11299 [1 << 17]byte var x11300 [1 << 17]byte var x11301 [1 << 17]byte var x11302 [1 << 17]byte var x11303 [1 << 17]byte var x11304 [1 << 17]byte var x11305 [1 << 17]byte var x11306 [1 << 17]byte var x11307 [1 << 17]byte var x11308 [1 << 17]byte var x11309 [1 << 17]byte var x11310 [1 << 17]byte var x11311 [1 << 17]byte var x11312 [1 << 17]byte var x11313 [1 << 17]byte var x11314 [1 << 17]byte var x11315 [1 << 17]byte var x11316 [1 << 17]byte var x11317 [1 << 17]byte var x11318 [1 << 17]byte var x11319 [1 << 17]byte var x11320 [1 << 17]byte var x11321 [1 << 17]byte var x11322 [1 << 17]byte var x11323 [1 << 17]byte var x11324 [1 << 17]byte var x11325 [1 << 17]byte var x11326 [1 << 17]byte var x11327 [1 << 17]byte var x11328 [1 << 17]byte var x11329 [1 << 17]byte var x11330 [1 << 17]byte var x11331 [1 << 17]byte var x11332 [1 << 17]byte var x11333 [1 << 17]byte var x11334 [1 << 17]byte var x11335 [1 << 17]byte var x11336 [1 << 17]byte var x11337 [1 << 17]byte var x11338 [1 << 17]byte var x11339 [1 << 17]byte var x11340 [1 << 17]byte var x11341 [1 << 17]byte var x11342 [1 << 17]byte var x11343 [1 << 17]byte var x11344 [1 << 17]byte var x11345 [1 << 17]byte var x11346 [1 << 17]byte var x11347 [1 << 17]byte var x11348 [1 << 17]byte var x11349 [1 << 17]byte var x11350 [1 << 17]byte var x11351 [1 << 17]byte var x11352 [1 << 17]byte var x11353 [1 << 17]byte var x11354 [1 << 17]byte var x11355 [1 << 17]byte var x11356 [1 << 17]byte var x11357 [1 << 17]byte var x11358 [1 << 17]byte var x11359 [1 << 17]byte var x11360 [1 << 17]byte var x11361 [1 << 17]byte var x11362 [1 << 17]byte var x11363 [1 << 17]byte var x11364 [1 << 17]byte var x11365 [1 << 17]byte var x11366 [1 << 17]byte var x11367 [1 << 17]byte var x11368 [1 << 17]byte var x11369 [1 << 17]byte var x11370 [1 << 17]byte var x11371 [1 << 17]byte var x11372 [1 << 17]byte var x11373 [1 << 17]byte var x11374 [1 << 17]byte var x11375 [1 << 17]byte var x11376 [1 << 17]byte var x11377 [1 << 17]byte var x11378 [1 << 17]byte var x11379 [1 << 17]byte var x11380 [1 << 17]byte var x11381 [1 << 17]byte var x11382 [1 << 17]byte var x11383 [1 << 17]byte var x11384 [1 << 17]byte var x11385 [1 << 17]byte var x11386 [1 << 17]byte var x11387 [1 << 17]byte var x11388 [1 << 17]byte var x11389 [1 << 17]byte var x11390 [1 << 17]byte var x11391 [1 << 17]byte var x11392 [1 << 17]byte var x11393 [1 << 17]byte var x11394 [1 << 17]byte var x11395 [1 << 17]byte var x11396 [1 << 17]byte var x11397 [1 << 17]byte var x11398 [1 << 17]byte var x11399 [1 << 17]byte var x11400 [1 << 17]byte var x11401 [1 << 17]byte var x11402 [1 << 17]byte var x11403 [1 << 17]byte var x11404 [1 << 17]byte var x11405 [1 << 17]byte var x11406 [1 << 17]byte var x11407 [1 << 17]byte var x11408 [1 << 17]byte var x11409 [1 << 17]byte var x11410 [1 << 17]byte var x11411 [1 << 17]byte var x11412 [1 << 17]byte var x11413 [1 << 17]byte var x11414 [1 << 17]byte var x11415 [1 << 17]byte var x11416 [1 << 17]byte var x11417 [1 << 17]byte var x11418 [1 << 17]byte var x11419 [1 << 17]byte var x11420 [1 << 17]byte var x11421 [1 << 17]byte var x11422 [1 << 17]byte var x11423 [1 << 17]byte var x11424 [1 << 17]byte var x11425 [1 << 17]byte var x11426 [1 << 17]byte var x11427 [1 << 17]byte var x11428 [1 << 17]byte var x11429 [1 << 17]byte var x11430 [1 << 17]byte var x11431 [1 << 17]byte var x11432 [1 << 17]byte var x11433 [1 << 17]byte var x11434 [1 << 17]byte var x11435 [1 << 17]byte var x11436 [1 << 17]byte var x11437 [1 << 17]byte var x11438 [1 << 17]byte var x11439 [1 << 17]byte var x11440 [1 << 17]byte var x11441 [1 << 17]byte var x11442 [1 << 17]byte var x11443 [1 << 17]byte var x11444 [1 << 17]byte var x11445 [1 << 17]byte var x11446 [1 << 17]byte var x11447 [1 << 17]byte var x11448 [1 << 17]byte var x11449 [1 << 17]byte var x11450 [1 << 17]byte var x11451 [1 << 17]byte var x11452 [1 << 17]byte var x11453 [1 << 17]byte var x11454 [1 << 17]byte var x11455 [1 << 17]byte var x11456 [1 << 17]byte var x11457 [1 << 17]byte var x11458 [1 << 17]byte var x11459 [1 << 17]byte var x11460 [1 << 17]byte var x11461 [1 << 17]byte var x11462 [1 << 17]byte var x11463 [1 << 17]byte var x11464 [1 << 17]byte var x11465 [1 << 17]byte var x11466 [1 << 17]byte var x11467 [1 << 17]byte var x11468 [1 << 17]byte var x11469 [1 << 17]byte var x11470 [1 << 17]byte var x11471 [1 << 17]byte var x11472 [1 << 17]byte var x11473 [1 << 17]byte var x11474 [1 << 17]byte var x11475 [1 << 17]byte var x11476 [1 << 17]byte var x11477 [1 << 17]byte var x11478 [1 << 17]byte var x11479 [1 << 17]byte var x11480 [1 << 17]byte var x11481 [1 << 17]byte var x11482 [1 << 17]byte var x11483 [1 << 17]byte var x11484 [1 << 17]byte var x11485 [1 << 17]byte var x11486 [1 << 17]byte var x11487 [1 << 17]byte var x11488 [1 << 17]byte var x11489 [1 << 17]byte var x11490 [1 << 17]byte var x11491 [1 << 17]byte var x11492 [1 << 17]byte var x11493 [1 << 17]byte var x11494 [1 << 17]byte var x11495 [1 << 17]byte var x11496 [1 << 17]byte var x11497 [1 << 17]byte var x11498 [1 << 17]byte var x11499 [1 << 17]byte var x11500 [1 << 17]byte var x11501 [1 << 17]byte var x11502 [1 << 17]byte var x11503 [1 << 17]byte var x11504 [1 << 17]byte var x11505 [1 << 17]byte var x11506 [1 << 17]byte var x11507 [1 << 17]byte var x11508 [1 << 17]byte var x11509 [1 << 17]byte var x11510 [1 << 17]byte var x11511 [1 << 17]byte var x11512 [1 << 17]byte var x11513 [1 << 17]byte var x11514 [1 << 17]byte var x11515 [1 << 17]byte var x11516 [1 << 17]byte var x11517 [1 << 17]byte var x11518 [1 << 17]byte var x11519 [1 << 17]byte var x11520 [1 << 17]byte var x11521 [1 << 17]byte var x11522 [1 << 17]byte var x11523 [1 << 17]byte var x11524 [1 << 17]byte var x11525 [1 << 17]byte var x11526 [1 << 17]byte var x11527 [1 << 17]byte var x11528 [1 << 17]byte var x11529 [1 << 17]byte var x11530 [1 << 17]byte var x11531 [1 << 17]byte var x11532 [1 << 17]byte var x11533 [1 << 17]byte var x11534 [1 << 17]byte var x11535 [1 << 17]byte var x11536 [1 << 17]byte var x11537 [1 << 17]byte var x11538 [1 << 17]byte var x11539 [1 << 17]byte var x11540 [1 << 17]byte var x11541 [1 << 17]byte var x11542 [1 << 17]byte var x11543 [1 << 17]byte var x11544 [1 << 17]byte var x11545 [1 << 17]byte var x11546 [1 << 17]byte var x11547 [1 << 17]byte var x11548 [1 << 17]byte var x11549 [1 << 17]byte var x11550 [1 << 17]byte var x11551 [1 << 17]byte var x11552 [1 << 17]byte var x11553 [1 << 17]byte var x11554 [1 << 17]byte var x11555 [1 << 17]byte var x11556 [1 << 17]byte var x11557 [1 << 17]byte var x11558 [1 << 17]byte var x11559 [1 << 17]byte var x11560 [1 << 17]byte var x11561 [1 << 17]byte var x11562 [1 << 17]byte var x11563 [1 << 17]byte var x11564 [1 << 17]byte var x11565 [1 << 17]byte var x11566 [1 << 17]byte var x11567 [1 << 17]byte var x11568 [1 << 17]byte var x11569 [1 << 17]byte var x11570 [1 << 17]byte var x11571 [1 << 17]byte var x11572 [1 << 17]byte var x11573 [1 << 17]byte var x11574 [1 << 17]byte var x11575 [1 << 17]byte var x11576 [1 << 17]byte var x11577 [1 << 17]byte var x11578 [1 << 17]byte var x11579 [1 << 17]byte var x11580 [1 << 17]byte var x11581 [1 << 17]byte var x11582 [1 << 17]byte var x11583 [1 << 17]byte var x11584 [1 << 17]byte var x11585 [1 << 17]byte var x11586 [1 << 17]byte var x11587 [1 << 17]byte var x11588 [1 << 17]byte var x11589 [1 << 17]byte var x11590 [1 << 17]byte var x11591 [1 << 17]byte var x11592 [1 << 17]byte var x11593 [1 << 17]byte var x11594 [1 << 17]byte var x11595 [1 << 17]byte var x11596 [1 << 17]byte var x11597 [1 << 17]byte var x11598 [1 << 17]byte var x11599 [1 << 17]byte var x11600 [1 << 17]byte var x11601 [1 << 17]byte var x11602 [1 << 17]byte var x11603 [1 << 17]byte var x11604 [1 << 17]byte var x11605 [1 << 17]byte var x11606 [1 << 17]byte var x11607 [1 << 17]byte var x11608 [1 << 17]byte var x11609 [1 << 17]byte var x11610 [1 << 17]byte var x11611 [1 << 17]byte var x11612 [1 << 17]byte var x11613 [1 << 17]byte var x11614 [1 << 17]byte var x11615 [1 << 17]byte var x11616 [1 << 17]byte var x11617 [1 << 17]byte var x11618 [1 << 17]byte var x11619 [1 << 17]byte var x11620 [1 << 17]byte var x11621 [1 << 17]byte var x11622 [1 << 17]byte var x11623 [1 << 17]byte var x11624 [1 << 17]byte var x11625 [1 << 17]byte var x11626 [1 << 17]byte var x11627 [1 << 17]byte var x11628 [1 << 17]byte var x11629 [1 << 17]byte var x11630 [1 << 17]byte var x11631 [1 << 17]byte var x11632 [1 << 17]byte var x11633 [1 << 17]byte var x11634 [1 << 17]byte var x11635 [1 << 17]byte var x11636 [1 << 17]byte var x11637 [1 << 17]byte var x11638 [1 << 17]byte var x11639 [1 << 17]byte var x11640 [1 << 17]byte var x11641 [1 << 17]byte var x11642 [1 << 17]byte var x11643 [1 << 17]byte var x11644 [1 << 17]byte var x11645 [1 << 17]byte var x11646 [1 << 17]byte var x11647 [1 << 17]byte var x11648 [1 << 17]byte var x11649 [1 << 17]byte var x11650 [1 << 17]byte var x11651 [1 << 17]byte var x11652 [1 << 17]byte var x11653 [1 << 17]byte var x11654 [1 << 17]byte var x11655 [1 << 17]byte var x11656 [1 << 17]byte var x11657 [1 << 17]byte var x11658 [1 << 17]byte var x11659 [1 << 17]byte var x11660 [1 << 17]byte var x11661 [1 << 17]byte var x11662 [1 << 17]byte var x11663 [1 << 17]byte var x11664 [1 << 17]byte var x11665 [1 << 17]byte var x11666 [1 << 17]byte var x11667 [1 << 17]byte var x11668 [1 << 17]byte var x11669 [1 << 17]byte var x11670 [1 << 17]byte var x11671 [1 << 17]byte var x11672 [1 << 17]byte var x11673 [1 << 17]byte var x11674 [1 << 17]byte var x11675 [1 << 17]byte var x11676 [1 << 17]byte var x11677 [1 << 17]byte var x11678 [1 << 17]byte var x11679 [1 << 17]byte var x11680 [1 << 17]byte var x11681 [1 << 17]byte var x11682 [1 << 17]byte var x11683 [1 << 17]byte var x11684 [1 << 17]byte var x11685 [1 << 17]byte var x11686 [1 << 17]byte var x11687 [1 << 17]byte var x11688 [1 << 17]byte var x11689 [1 << 17]byte var x11690 [1 << 17]byte var x11691 [1 << 17]byte var x11692 [1 << 17]byte var x11693 [1 << 17]byte var x11694 [1 << 17]byte var x11695 [1 << 17]byte var x11696 [1 << 17]byte var x11697 [1 << 17]byte var x11698 [1 << 17]byte var x11699 [1 << 17]byte var x11700 [1 << 17]byte var x11701 [1 << 17]byte var x11702 [1 << 17]byte var x11703 [1 << 17]byte var x11704 [1 << 17]byte var x11705 [1 << 17]byte var x11706 [1 << 17]byte var x11707 [1 << 17]byte var x11708 [1 << 17]byte var x11709 [1 << 17]byte var x11710 [1 << 17]byte var x11711 [1 << 17]byte var x11712 [1 << 17]byte var x11713 [1 << 17]byte var x11714 [1 << 17]byte var x11715 [1 << 17]byte var x11716 [1 << 17]byte var x11717 [1 << 17]byte var x11718 [1 << 17]byte var x11719 [1 << 17]byte var x11720 [1 << 17]byte var x11721 [1 << 17]byte var x11722 [1 << 17]byte var x11723 [1 << 17]byte var x11724 [1 << 17]byte var x11725 [1 << 17]byte var x11726 [1 << 17]byte var x11727 [1 << 17]byte var x11728 [1 << 17]byte var x11729 [1 << 17]byte var x11730 [1 << 17]byte var x11731 [1 << 17]byte var x11732 [1 << 17]byte var x11733 [1 << 17]byte var x11734 [1 << 17]byte var x11735 [1 << 17]byte var x11736 [1 << 17]byte var x11737 [1 << 17]byte var x11738 [1 << 17]byte var x11739 [1 << 17]byte var x11740 [1 << 17]byte var x11741 [1 << 17]byte var x11742 [1 << 17]byte var x11743 [1 << 17]byte var x11744 [1 << 17]byte var x11745 [1 << 17]byte var x11746 [1 << 17]byte var x11747 [1 << 17]byte var x11748 [1 << 17]byte var x11749 [1 << 17]byte var x11750 [1 << 17]byte var x11751 [1 << 17]byte var x11752 [1 << 17]byte var x11753 [1 << 17]byte var x11754 [1 << 17]byte var x11755 [1 << 17]byte var x11756 [1 << 17]byte var x11757 [1 << 17]byte var x11758 [1 << 17]byte var x11759 [1 << 17]byte var x11760 [1 << 17]byte var x11761 [1 << 17]byte var x11762 [1 << 17]byte var x11763 [1 << 17]byte var x11764 [1 << 17]byte var x11765 [1 << 17]byte var x11766 [1 << 17]byte var x11767 [1 << 17]byte var x11768 [1 << 17]byte var x11769 [1 << 17]byte var x11770 [1 << 17]byte var x11771 [1 << 17]byte var x11772 [1 << 17]byte var x11773 [1 << 17]byte var x11774 [1 << 17]byte var x11775 [1 << 17]byte var x11776 [1 << 17]byte var x11777 [1 << 17]byte var x11778 [1 << 17]byte var x11779 [1 << 17]byte var x11780 [1 << 17]byte var x11781 [1 << 17]byte var x11782 [1 << 17]byte var x11783 [1 << 17]byte var x11784 [1 << 17]byte var x11785 [1 << 17]byte var x11786 [1 << 17]byte var x11787 [1 << 17]byte var x11788 [1 << 17]byte var x11789 [1 << 17]byte var x11790 [1 << 17]byte var x11791 [1 << 17]byte var x11792 [1 << 17]byte var x11793 [1 << 17]byte var x11794 [1 << 17]byte var x11795 [1 << 17]byte var x11796 [1 << 17]byte var x11797 [1 << 17]byte var x11798 [1 << 17]byte var x11799 [1 << 17]byte var x11800 [1 << 17]byte var x11801 [1 << 17]byte var x11802 [1 << 17]byte var x11803 [1 << 17]byte var x11804 [1 << 17]byte var x11805 [1 << 17]byte var x11806 [1 << 17]byte var x11807 [1 << 17]byte var x11808 [1 << 17]byte var x11809 [1 << 17]byte var x11810 [1 << 17]byte var x11811 [1 << 17]byte var x11812 [1 << 17]byte var x11813 [1 << 17]byte var x11814 [1 << 17]byte var x11815 [1 << 17]byte var x11816 [1 << 17]byte var x11817 [1 << 17]byte var x11818 [1 << 17]byte var x11819 [1 << 17]byte var x11820 [1 << 17]byte var x11821 [1 << 17]byte var x11822 [1 << 17]byte var x11823 [1 << 17]byte var x11824 [1 << 17]byte var x11825 [1 << 17]byte var x11826 [1 << 17]byte var x11827 [1 << 17]byte var x11828 [1 << 17]byte var x11829 [1 << 17]byte var x11830 [1 << 17]byte var x11831 [1 << 17]byte var x11832 [1 << 17]byte var x11833 [1 << 17]byte var x11834 [1 << 17]byte var x11835 [1 << 17]byte var x11836 [1 << 17]byte var x11837 [1 << 17]byte var x11838 [1 << 17]byte var x11839 [1 << 17]byte var x11840 [1 << 17]byte var x11841 [1 << 17]byte var x11842 [1 << 17]byte var x11843 [1 << 17]byte var x11844 [1 << 17]byte var x11845 [1 << 17]byte var x11846 [1 << 17]byte var x11847 [1 << 17]byte var x11848 [1 << 17]byte var x11849 [1 << 17]byte var x11850 [1 << 17]byte var x11851 [1 << 17]byte var x11852 [1 << 17]byte var x11853 [1 << 17]byte var x11854 [1 << 17]byte var x11855 [1 << 17]byte var x11856 [1 << 17]byte var x11857 [1 << 17]byte var x11858 [1 << 17]byte var x11859 [1 << 17]byte var x11860 [1 << 17]byte var x11861 [1 << 17]byte var x11862 [1 << 17]byte var x11863 [1 << 17]byte var x11864 [1 << 17]byte var x11865 [1 << 17]byte var x11866 [1 << 17]byte var x11867 [1 << 17]byte var x11868 [1 << 17]byte var x11869 [1 << 17]byte var x11870 [1 << 17]byte var x11871 [1 << 17]byte var x11872 [1 << 17]byte var x11873 [1 << 17]byte var x11874 [1 << 17]byte var x11875 [1 << 17]byte var x11876 [1 << 17]byte var x11877 [1 << 17]byte var x11878 [1 << 17]byte var x11879 [1 << 17]byte var x11880 [1 << 17]byte var x11881 [1 << 17]byte var x11882 [1 << 17]byte var x11883 [1 << 17]byte var x11884 [1 << 17]byte var x11885 [1 << 17]byte var x11886 [1 << 17]byte var x11887 [1 << 17]byte var x11888 [1 << 17]byte var x11889 [1 << 17]byte var x11890 [1 << 17]byte var x11891 [1 << 17]byte var x11892 [1 << 17]byte var x11893 [1 << 17]byte var x11894 [1 << 17]byte var x11895 [1 << 17]byte var x11896 [1 << 17]byte var x11897 [1 << 17]byte var x11898 [1 << 17]byte var x11899 [1 << 17]byte var x11900 [1 << 17]byte var x11901 [1 << 17]byte var x11902 [1 << 17]byte var x11903 [1 << 17]byte var x11904 [1 << 17]byte var x11905 [1 << 17]byte var x11906 [1 << 17]byte var x11907 [1 << 17]byte var x11908 [1 << 17]byte var x11909 [1 << 17]byte var x11910 [1 << 17]byte var x11911 [1 << 17]byte var x11912 [1 << 17]byte var x11913 [1 << 17]byte var x11914 [1 << 17]byte var x11915 [1 << 17]byte var x11916 [1 << 17]byte var x11917 [1 << 17]byte var x11918 [1 << 17]byte var x11919 [1 << 17]byte var x11920 [1 << 17]byte var x11921 [1 << 17]byte var x11922 [1 << 17]byte var x11923 [1 << 17]byte var x11924 [1 << 17]byte var x11925 [1 << 17]byte var x11926 [1 << 17]byte var x11927 [1 << 17]byte var x11928 [1 << 17]byte var x11929 [1 << 17]byte var x11930 [1 << 17]byte var x11931 [1 << 17]byte var x11932 [1 << 17]byte var x11933 [1 << 17]byte var x11934 [1 << 17]byte var x11935 [1 << 17]byte var x11936 [1 << 17]byte var x11937 [1 << 17]byte var x11938 [1 << 17]byte var x11939 [1 << 17]byte var x11940 [1 << 17]byte var x11941 [1 << 17]byte var x11942 [1 << 17]byte var x11943 [1 << 17]byte var x11944 [1 << 17]byte var x11945 [1 << 17]byte var x11946 [1 << 17]byte var x11947 [1 << 17]byte var x11948 [1 << 17]byte var x11949 [1 << 17]byte var x11950 [1 << 17]byte var x11951 [1 << 17]byte var x11952 [1 << 17]byte var x11953 [1 << 17]byte var x11954 [1 << 17]byte var x11955 [1 << 17]byte var x11956 [1 << 17]byte var x11957 [1 << 17]byte var x11958 [1 << 17]byte var x11959 [1 << 17]byte var x11960 [1 << 17]byte var x11961 [1 << 17]byte var x11962 [1 << 17]byte var x11963 [1 << 17]byte var x11964 [1 << 17]byte var x11965 [1 << 17]byte var x11966 [1 << 17]byte var x11967 [1 << 17]byte var x11968 [1 << 17]byte var x11969 [1 << 17]byte var x11970 [1 << 17]byte var x11971 [1 << 17]byte var x11972 [1 << 17]byte var x11973 [1 << 17]byte var x11974 [1 << 17]byte var x11975 [1 << 17]byte var x11976 [1 << 17]byte var x11977 [1 << 17]byte var x11978 [1 << 17]byte var x11979 [1 << 17]byte var x11980 [1 << 17]byte var x11981 [1 << 17]byte var x11982 [1 << 17]byte var x11983 [1 << 17]byte var x11984 [1 << 17]byte var x11985 [1 << 17]byte var x11986 [1 << 17]byte var x11987 [1 << 17]byte var x11988 [1 << 17]byte var x11989 [1 << 17]byte var x11990 [1 << 17]byte var x11991 [1 << 17]byte var x11992 [1 << 17]byte var x11993 [1 << 17]byte var x11994 [1 << 17]byte var x11995 [1 << 17]byte var x11996 [1 << 17]byte var x11997 [1 << 17]byte var x11998 [1 << 17]byte var x11999 [1 << 17]byte var x12000 [1 << 17]byte var x12001 [1 << 17]byte var x12002 [1 << 17]byte var x12003 [1 << 17]byte var x12004 [1 << 17]byte var x12005 [1 << 17]byte var x12006 [1 << 17]byte var x12007 [1 << 17]byte var x12008 [1 << 17]byte var x12009 [1 << 17]byte var x12010 [1 << 17]byte var x12011 [1 << 17]byte var x12012 [1 << 17]byte var x12013 [1 << 17]byte var x12014 [1 << 17]byte var x12015 [1 << 17]byte var x12016 [1 << 17]byte var x12017 [1 << 17]byte var x12018 [1 << 17]byte var x12019 [1 << 17]byte var x12020 [1 << 17]byte var x12021 [1 << 17]byte var x12022 [1 << 17]byte var x12023 [1 << 17]byte var x12024 [1 << 17]byte var x12025 [1 << 17]byte var x12026 [1 << 17]byte var x12027 [1 << 17]byte var x12028 [1 << 17]byte var x12029 [1 << 17]byte var x12030 [1 << 17]byte var x12031 [1 << 17]byte var x12032 [1 << 17]byte var x12033 [1 << 17]byte var x12034 [1 << 17]byte var x12035 [1 << 17]byte var x12036 [1 << 17]byte var x12037 [1 << 17]byte var x12038 [1 << 17]byte var x12039 [1 << 17]byte var x12040 [1 << 17]byte var x12041 [1 << 17]byte var x12042 [1 << 17]byte var x12043 [1 << 17]byte var x12044 [1 << 17]byte var x12045 [1 << 17]byte var x12046 [1 << 17]byte var x12047 [1 << 17]byte var x12048 [1 << 17]byte var x12049 [1 << 17]byte var x12050 [1 << 17]byte var x12051 [1 << 17]byte var x12052 [1 << 17]byte var x12053 [1 << 17]byte var x12054 [1 << 17]byte var x12055 [1 << 17]byte var x12056 [1 << 17]byte var x12057 [1 << 17]byte var x12058 [1 << 17]byte var x12059 [1 << 17]byte var x12060 [1 << 17]byte var x12061 [1 << 17]byte var x12062 [1 << 17]byte var x12063 [1 << 17]byte var x12064 [1 << 17]byte var x12065 [1 << 17]byte var x12066 [1 << 17]byte var x12067 [1 << 17]byte var x12068 [1 << 17]byte var x12069 [1 << 17]byte var x12070 [1 << 17]byte var x12071 [1 << 17]byte var x12072 [1 << 17]byte var x12073 [1 << 17]byte var x12074 [1 << 17]byte var x12075 [1 << 17]byte var x12076 [1 << 17]byte var x12077 [1 << 17]byte var x12078 [1 << 17]byte var x12079 [1 << 17]byte var x12080 [1 << 17]byte var x12081 [1 << 17]byte var x12082 [1 << 17]byte var x12083 [1 << 17]byte var x12084 [1 << 17]byte var x12085 [1 << 17]byte var x12086 [1 << 17]byte var x12087 [1 << 17]byte var x12088 [1 << 17]byte var x12089 [1 << 17]byte var x12090 [1 << 17]byte var x12091 [1 << 17]byte var x12092 [1 << 17]byte var x12093 [1 << 17]byte var x12094 [1 << 17]byte var x12095 [1 << 17]byte var x12096 [1 << 17]byte var x12097 [1 << 17]byte var x12098 [1 << 17]byte var x12099 [1 << 17]byte var x12100 [1 << 17]byte var x12101 [1 << 17]byte var x12102 [1 << 17]byte var x12103 [1 << 17]byte var x12104 [1 << 17]byte var x12105 [1 << 17]byte var x12106 [1 << 17]byte var x12107 [1 << 17]byte var x12108 [1 << 17]byte var x12109 [1 << 17]byte var x12110 [1 << 17]byte var x12111 [1 << 17]byte var x12112 [1 << 17]byte var x12113 [1 << 17]byte var x12114 [1 << 17]byte var x12115 [1 << 17]byte var x12116 [1 << 17]byte var x12117 [1 << 17]byte var x12118 [1 << 17]byte var x12119 [1 << 17]byte var x12120 [1 << 17]byte var x12121 [1 << 17]byte var x12122 [1 << 17]byte var x12123 [1 << 17]byte var x12124 [1 << 17]byte var x12125 [1 << 17]byte var x12126 [1 << 17]byte var x12127 [1 << 17]byte var x12128 [1 << 17]byte var x12129 [1 << 17]byte var x12130 [1 << 17]byte var x12131 [1 << 17]byte var x12132 [1 << 17]byte var x12133 [1 << 17]byte var x12134 [1 << 17]byte var x12135 [1 << 17]byte var x12136 [1 << 17]byte var x12137 [1 << 17]byte var x12138 [1 << 17]byte var x12139 [1 << 17]byte var x12140 [1 << 17]byte var x12141 [1 << 17]byte var x12142 [1 << 17]byte var x12143 [1 << 17]byte var x12144 [1 << 17]byte var x12145 [1 << 17]byte var x12146 [1 << 17]byte var x12147 [1 << 17]byte var x12148 [1 << 17]byte var x12149 [1 << 17]byte var x12150 [1 << 17]byte var x12151 [1 << 17]byte var x12152 [1 << 17]byte var x12153 [1 << 17]byte var x12154 [1 << 17]byte var x12155 [1 << 17]byte var x12156 [1 << 17]byte var x12157 [1 << 17]byte var x12158 [1 << 17]byte var x12159 [1 << 17]byte var x12160 [1 << 17]byte var x12161 [1 << 17]byte var x12162 [1 << 17]byte var x12163 [1 << 17]byte var x12164 [1 << 17]byte var x12165 [1 << 17]byte var x12166 [1 << 17]byte var x12167 [1 << 17]byte var x12168 [1 << 17]byte var x12169 [1 << 17]byte var x12170 [1 << 17]byte var x12171 [1 << 17]byte var x12172 [1 << 17]byte var x12173 [1 << 17]byte var x12174 [1 << 17]byte var x12175 [1 << 17]byte var x12176 [1 << 17]byte var x12177 [1 << 17]byte var x12178 [1 << 17]byte var x12179 [1 << 17]byte var x12180 [1 << 17]byte var x12181 [1 << 17]byte var x12182 [1 << 17]byte var x12183 [1 << 17]byte var x12184 [1 << 17]byte var x12185 [1 << 17]byte var x12186 [1 << 17]byte var x12187 [1 << 17]byte var x12188 [1 << 17]byte var x12189 [1 << 17]byte var x12190 [1 << 17]byte var x12191 [1 << 17]byte var x12192 [1 << 17]byte var x12193 [1 << 17]byte var x12194 [1 << 17]byte var x12195 [1 << 17]byte var x12196 [1 << 17]byte var x12197 [1 << 17]byte var x12198 [1 << 17]byte var x12199 [1 << 17]byte var x12200 [1 << 17]byte var x12201 [1 << 17]byte var x12202 [1 << 17]byte var x12203 [1 << 17]byte var x12204 [1 << 17]byte var x12205 [1 << 17]byte var x12206 [1 << 17]byte var x12207 [1 << 17]byte var x12208 [1 << 17]byte var x12209 [1 << 17]byte var x12210 [1 << 17]byte var x12211 [1 << 17]byte var x12212 [1 << 17]byte var x12213 [1 << 17]byte var x12214 [1 << 17]byte var x12215 [1 << 17]byte var x12216 [1 << 17]byte var x12217 [1 << 17]byte var x12218 [1 << 17]byte var x12219 [1 << 17]byte var x12220 [1 << 17]byte var x12221 [1 << 17]byte var x12222 [1 << 17]byte var x12223 [1 << 17]byte var x12224 [1 << 17]byte var x12225 [1 << 17]byte var x12226 [1 << 17]byte var x12227 [1 << 17]byte var x12228 [1 << 17]byte var x12229 [1 << 17]byte var x12230 [1 << 17]byte var x12231 [1 << 17]byte var x12232 [1 << 17]byte var x12233 [1 << 17]byte var x12234 [1 << 17]byte var x12235 [1 << 17]byte var x12236 [1 << 17]byte var x12237 [1 << 17]byte var x12238 [1 << 17]byte var x12239 [1 << 17]byte var x12240 [1 << 17]byte var x12241 [1 << 17]byte var x12242 [1 << 17]byte var x12243 [1 << 17]byte var x12244 [1 << 17]byte var x12245 [1 << 17]byte var x12246 [1 << 17]byte var x12247 [1 << 17]byte var x12248 [1 << 17]byte var x12249 [1 << 17]byte var x12250 [1 << 17]byte var x12251 [1 << 17]byte var x12252 [1 << 17]byte var x12253 [1 << 17]byte var x12254 [1 << 17]byte var x12255 [1 << 17]byte var x12256 [1 << 17]byte var x12257 [1 << 17]byte var x12258 [1 << 17]byte var x12259 [1 << 17]byte var x12260 [1 << 17]byte var x12261 [1 << 17]byte var x12262 [1 << 17]byte var x12263 [1 << 17]byte var x12264 [1 << 17]byte var x12265 [1 << 17]byte var x12266 [1 << 17]byte var x12267 [1 << 17]byte var x12268 [1 << 17]byte var x12269 [1 << 17]byte var x12270 [1 << 17]byte var x12271 [1 << 17]byte var x12272 [1 << 17]byte var x12273 [1 << 17]byte var x12274 [1 << 17]byte var x12275 [1 << 17]byte var x12276 [1 << 17]byte var x12277 [1 << 17]byte var x12278 [1 << 17]byte var x12279 [1 << 17]byte var x12280 [1 << 17]byte var x12281 [1 << 17]byte var x12282 [1 << 17]byte var x12283 [1 << 17]byte var x12284 [1 << 17]byte var x12285 [1 << 17]byte var x12286 [1 << 17]byte var x12287 [1 << 17]byte var x12288 [1 << 17]byte var x12289 [1 << 17]byte var x12290 [1 << 17]byte var x12291 [1 << 17]byte var x12292 [1 << 17]byte var x12293 [1 << 17]byte var x12294 [1 << 17]byte var x12295 [1 << 17]byte var x12296 [1 << 17]byte var x12297 [1 << 17]byte var x12298 [1 << 17]byte var x12299 [1 << 17]byte var x12300 [1 << 17]byte var x12301 [1 << 17]byte var x12302 [1 << 17]byte var x12303 [1 << 17]byte var x12304 [1 << 17]byte var x12305 [1 << 17]byte var x12306 [1 << 17]byte var x12307 [1 << 17]byte var x12308 [1 << 17]byte var x12309 [1 << 17]byte var x12310 [1 << 17]byte var x12311 [1 << 17]byte var x12312 [1 << 17]byte var x12313 [1 << 17]byte var x12314 [1 << 17]byte var x12315 [1 << 17]byte var x12316 [1 << 17]byte var x12317 [1 << 17]byte var x12318 [1 << 17]byte var x12319 [1 << 17]byte var x12320 [1 << 17]byte var x12321 [1 << 17]byte var x12322 [1 << 17]byte var x12323 [1 << 17]byte var x12324 [1 << 17]byte var x12325 [1 << 17]byte var x12326 [1 << 17]byte var x12327 [1 << 17]byte var x12328 [1 << 17]byte var x12329 [1 << 17]byte var x12330 [1 << 17]byte var x12331 [1 << 17]byte var x12332 [1 << 17]byte var x12333 [1 << 17]byte var x12334 [1 << 17]byte var x12335 [1 << 17]byte var x12336 [1 << 17]byte var x12337 [1 << 17]byte var x12338 [1 << 17]byte var x12339 [1 << 17]byte var x12340 [1 << 17]byte var x12341 [1 << 17]byte var x12342 [1 << 17]byte var x12343 [1 << 17]byte var x12344 [1 << 17]byte var x12345 [1 << 17]byte var x12346 [1 << 17]byte var x12347 [1 << 17]byte var x12348 [1 << 17]byte var x12349 [1 << 17]byte var x12350 [1 << 17]byte var x12351 [1 << 17]byte var x12352 [1 << 17]byte var x12353 [1 << 17]byte var x12354 [1 << 17]byte var x12355 [1 << 17]byte var x12356 [1 << 17]byte var x12357 [1 << 17]byte var x12358 [1 << 17]byte var x12359 [1 << 17]byte var x12360 [1 << 17]byte var x12361 [1 << 17]byte var x12362 [1 << 17]byte var x12363 [1 << 17]byte var x12364 [1 << 17]byte var x12365 [1 << 17]byte var x12366 [1 << 17]byte var x12367 [1 << 17]byte var x12368 [1 << 17]byte var x12369 [1 << 17]byte var x12370 [1 << 17]byte var x12371 [1 << 17]byte var x12372 [1 << 17]byte var x12373 [1 << 17]byte var x12374 [1 << 17]byte var x12375 [1 << 17]byte var x12376 [1 << 17]byte var x12377 [1 << 17]byte var x12378 [1 << 17]byte var x12379 [1 << 17]byte var x12380 [1 << 17]byte var x12381 [1 << 17]byte var x12382 [1 << 17]byte var x12383 [1 << 17]byte var x12384 [1 << 17]byte var x12385 [1 << 17]byte var x12386 [1 << 17]byte var x12387 [1 << 17]byte var x12388 [1 << 17]byte var x12389 [1 << 17]byte var x12390 [1 << 17]byte var x12391 [1 << 17]byte var x12392 [1 << 17]byte var x12393 [1 << 17]byte var x12394 [1 << 17]byte var x12395 [1 << 17]byte var x12396 [1 << 17]byte var x12397 [1 << 17]byte var x12398 [1 << 17]byte var x12399 [1 << 17]byte var x12400 [1 << 17]byte var x12401 [1 << 17]byte var x12402 [1 << 17]byte var x12403 [1 << 17]byte var x12404 [1 << 17]byte var x12405 [1 << 17]byte var x12406 [1 << 17]byte var x12407 [1 << 17]byte var x12408 [1 << 17]byte var x12409 [1 << 17]byte var x12410 [1 << 17]byte var x12411 [1 << 17]byte var x12412 [1 << 17]byte var x12413 [1 << 17]byte var x12414 [1 << 17]byte var x12415 [1 << 17]byte var x12416 [1 << 17]byte var x12417 [1 << 17]byte var x12418 [1 << 17]byte var x12419 [1 << 17]byte var x12420 [1 << 17]byte var x12421 [1 << 17]byte var x12422 [1 << 17]byte var x12423 [1 << 17]byte var x12424 [1 << 17]byte var x12425 [1 << 17]byte var x12426 [1 << 17]byte var x12427 [1 << 17]byte var x12428 [1 << 17]byte var x12429 [1 << 17]byte var x12430 [1 << 17]byte var x12431 [1 << 17]byte var x12432 [1 << 17]byte var x12433 [1 << 17]byte var x12434 [1 << 17]byte var x12435 [1 << 17]byte var x12436 [1 << 17]byte var x12437 [1 << 17]byte var x12438 [1 << 17]byte var x12439 [1 << 17]byte var x12440 [1 << 17]byte var x12441 [1 << 17]byte var x12442 [1 << 17]byte var x12443 [1 << 17]byte var x12444 [1 << 17]byte var x12445 [1 << 17]byte var x12446 [1 << 17]byte var x12447 [1 << 17]byte var x12448 [1 << 17]byte var x12449 [1 << 17]byte var x12450 [1 << 17]byte var x12451 [1 << 17]byte var x12452 [1 << 17]byte var x12453 [1 << 17]byte var x12454 [1 << 17]byte var x12455 [1 << 17]byte var x12456 [1 << 17]byte var x12457 [1 << 17]byte var x12458 [1 << 17]byte var x12459 [1 << 17]byte var x12460 [1 << 17]byte var x12461 [1 << 17]byte var x12462 [1 << 17]byte var x12463 [1 << 17]byte var x12464 [1 << 17]byte var x12465 [1 << 17]byte var x12466 [1 << 17]byte var x12467 [1 << 17]byte var x12468 [1 << 17]byte var x12469 [1 << 17]byte var x12470 [1 << 17]byte var x12471 [1 << 17]byte var x12472 [1 << 17]byte var x12473 [1 << 17]byte var x12474 [1 << 17]byte var x12475 [1 << 17]byte var x12476 [1 << 17]byte var x12477 [1 << 17]byte var x12478 [1 << 17]byte var x12479 [1 << 17]byte var x12480 [1 << 17]byte var x12481 [1 << 17]byte var x12482 [1 << 17]byte var x12483 [1 << 17]byte var x12484 [1 << 17]byte var x12485 [1 << 17]byte var x12486 [1 << 17]byte var x12487 [1 << 17]byte var x12488 [1 << 17]byte var x12489 [1 << 17]byte var x12490 [1 << 17]byte var x12491 [1 << 17]byte var x12492 [1 << 17]byte var x12493 [1 << 17]byte var x12494 [1 << 17]byte var x12495 [1 << 17]byte var x12496 [1 << 17]byte var x12497 [1 << 17]byte var x12498 [1 << 17]byte var x12499 [1 << 17]byte var x12500 [1 << 17]byte var x12501 [1 << 17]byte var x12502 [1 << 17]byte var x12503 [1 << 17]byte var x12504 [1 << 17]byte var x12505 [1 << 17]byte var x12506 [1 << 17]byte var x12507 [1 << 17]byte var x12508 [1 << 17]byte var x12509 [1 << 17]byte var x12510 [1 << 17]byte var x12511 [1 << 17]byte var x12512 [1 << 17]byte var x12513 [1 << 17]byte var x12514 [1 << 17]byte var x12515 [1 << 17]byte var x12516 [1 << 17]byte var x12517 [1 << 17]byte var x12518 [1 << 17]byte var x12519 [1 << 17]byte var x12520 [1 << 17]byte var x12521 [1 << 17]byte var x12522 [1 << 17]byte var x12523 [1 << 17]byte var x12524 [1 << 17]byte var x12525 [1 << 17]byte var x12526 [1 << 17]byte var x12527 [1 << 17]byte var x12528 [1 << 17]byte var x12529 [1 << 17]byte var x12530 [1 << 17]byte var x12531 [1 << 17]byte var x12532 [1 << 17]byte var x12533 [1 << 17]byte var x12534 [1 << 17]byte var x12535 [1 << 17]byte var x12536 [1 << 17]byte var x12537 [1 << 17]byte var x12538 [1 << 17]byte var x12539 [1 << 17]byte var x12540 [1 << 17]byte var x12541 [1 << 17]byte var x12542 [1 << 17]byte var x12543 [1 << 17]byte var x12544 [1 << 17]byte var x12545 [1 << 17]byte var x12546 [1 << 17]byte var x12547 [1 << 17]byte var x12548 [1 << 17]byte var x12549 [1 << 17]byte var x12550 [1 << 17]byte var x12551 [1 << 17]byte var x12552 [1 << 17]byte var x12553 [1 << 17]byte var x12554 [1 << 17]byte var x12555 [1 << 17]byte var x12556 [1 << 17]byte var x12557 [1 << 17]byte var x12558 [1 << 17]byte var x12559 [1 << 17]byte var x12560 [1 << 17]byte var x12561 [1 << 17]byte var x12562 [1 << 17]byte var x12563 [1 << 17]byte var x12564 [1 << 17]byte var x12565 [1 << 17]byte var x12566 [1 << 17]byte var x12567 [1 << 17]byte var x12568 [1 << 17]byte var x12569 [1 << 17]byte var x12570 [1 << 17]byte var x12571 [1 << 17]byte var x12572 [1 << 17]byte var x12573 [1 << 17]byte var x12574 [1 << 17]byte var x12575 [1 << 17]byte var x12576 [1 << 17]byte var x12577 [1 << 17]byte var x12578 [1 << 17]byte var x12579 [1 << 17]byte var x12580 [1 << 17]byte var x12581 [1 << 17]byte var x12582 [1 << 17]byte var x12583 [1 << 17]byte var x12584 [1 << 17]byte var x12585 [1 << 17]byte var x12586 [1 << 17]byte var x12587 [1 << 17]byte var x12588 [1 << 17]byte var x12589 [1 << 17]byte var x12590 [1 << 17]byte var x12591 [1 << 17]byte var x12592 [1 << 17]byte var x12593 [1 << 17]byte var x12594 [1 << 17]byte var x12595 [1 << 17]byte var x12596 [1 << 17]byte var x12597 [1 << 17]byte var x12598 [1 << 17]byte var x12599 [1 << 17]byte var x12600 [1 << 17]byte var x12601 [1 << 17]byte var x12602 [1 << 17]byte var x12603 [1 << 17]byte var x12604 [1 << 17]byte var x12605 [1 << 17]byte var x12606 [1 << 17]byte var x12607 [1 << 17]byte var x12608 [1 << 17]byte var x12609 [1 << 17]byte var x12610 [1 << 17]byte var x12611 [1 << 17]byte var x12612 [1 << 17]byte var x12613 [1 << 17]byte var x12614 [1 << 17]byte var x12615 [1 << 17]byte var x12616 [1 << 17]byte var x12617 [1 << 17]byte var x12618 [1 << 17]byte var x12619 [1 << 17]byte var x12620 [1 << 17]byte var x12621 [1 << 17]byte var x12622 [1 << 17]byte var x12623 [1 << 17]byte var x12624 [1 << 17]byte var x12625 [1 << 17]byte var x12626 [1 << 17]byte var x12627 [1 << 17]byte var x12628 [1 << 17]byte var x12629 [1 << 17]byte var x12630 [1 << 17]byte var x12631 [1 << 17]byte var x12632 [1 << 17]byte var x12633 [1 << 17]byte var x12634 [1 << 17]byte var x12635 [1 << 17]byte var x12636 [1 << 17]byte var x12637 [1 << 17]byte var x12638 [1 << 17]byte var x12639 [1 << 17]byte var x12640 [1 << 17]byte var x12641 [1 << 17]byte var x12642 [1 << 17]byte var x12643 [1 << 17]byte var x12644 [1 << 17]byte var x12645 [1 << 17]byte var x12646 [1 << 17]byte var x12647 [1 << 17]byte var x12648 [1 << 17]byte var x12649 [1 << 17]byte var x12650 [1 << 17]byte var x12651 [1 << 17]byte var x12652 [1 << 17]byte var x12653 [1 << 17]byte var x12654 [1 << 17]byte var x12655 [1 << 17]byte var x12656 [1 << 17]byte var x12657 [1 << 17]byte var x12658 [1 << 17]byte var x12659 [1 << 17]byte var x12660 [1 << 17]byte var x12661 [1 << 17]byte var x12662 [1 << 17]byte var x12663 [1 << 17]byte var x12664 [1 << 17]byte var x12665 [1 << 17]byte var x12666 [1 << 17]byte var x12667 [1 << 17]byte var x12668 [1 << 17]byte var x12669 [1 << 17]byte var x12670 [1 << 17]byte var x12671 [1 << 17]byte var x12672 [1 << 17]byte var x12673 [1 << 17]byte var x12674 [1 << 17]byte var x12675 [1 << 17]byte var x12676 [1 << 17]byte var x12677 [1 << 17]byte var x12678 [1 << 17]byte var x12679 [1 << 17]byte var x12680 [1 << 17]byte var x12681 [1 << 17]byte var x12682 [1 << 17]byte var x12683 [1 << 17]byte var x12684 [1 << 17]byte var x12685 [1 << 17]byte var x12686 [1 << 17]byte var x12687 [1 << 17]byte var x12688 [1 << 17]byte var x12689 [1 << 17]byte var x12690 [1 << 17]byte var x12691 [1 << 17]byte var x12692 [1 << 17]byte var x12693 [1 << 17]byte var x12694 [1 << 17]byte var x12695 [1 << 17]byte var x12696 [1 << 17]byte var x12697 [1 << 17]byte var x12698 [1 << 17]byte var x12699 [1 << 17]byte var x12700 [1 << 17]byte var x12701 [1 << 17]byte var x12702 [1 << 17]byte var x12703 [1 << 17]byte var x12704 [1 << 17]byte var x12705 [1 << 17]byte var x12706 [1 << 17]byte var x12707 [1 << 17]byte var x12708 [1 << 17]byte var x12709 [1 << 17]byte var x12710 [1 << 17]byte var x12711 [1 << 17]byte var x12712 [1 << 17]byte var x12713 [1 << 17]byte var x12714 [1 << 17]byte var x12715 [1 << 17]byte var x12716 [1 << 17]byte var x12717 [1 << 17]byte var x12718 [1 << 17]byte var x12719 [1 << 17]byte var x12720 [1 << 17]byte var x12721 [1 << 17]byte var x12722 [1 << 17]byte var x12723 [1 << 17]byte var x12724 [1 << 17]byte var x12725 [1 << 17]byte var x12726 [1 << 17]byte var x12727 [1 << 17]byte var x12728 [1 << 17]byte var x12729 [1 << 17]byte var x12730 [1 << 17]byte var x12731 [1 << 17]byte var x12732 [1 << 17]byte var x12733 [1 << 17]byte var x12734 [1 << 17]byte var x12735 [1 << 17]byte var x12736 [1 << 17]byte var x12737 [1 << 17]byte var x12738 [1 << 17]byte var x12739 [1 << 17]byte var x12740 [1 << 17]byte var x12741 [1 << 17]byte var x12742 [1 << 17]byte var x12743 [1 << 17]byte var x12744 [1 << 17]byte var x12745 [1 << 17]byte var x12746 [1 << 17]byte var x12747 [1 << 17]byte var x12748 [1 << 17]byte var x12749 [1 << 17]byte var x12750 [1 << 17]byte var x12751 [1 << 17]byte var x12752 [1 << 17]byte var x12753 [1 << 17]byte var x12754 [1 << 17]byte var x12755 [1 << 17]byte var x12756 [1 << 17]byte var x12757 [1 << 17]byte var x12758 [1 << 17]byte var x12759 [1 << 17]byte var x12760 [1 << 17]byte var x12761 [1 << 17]byte var x12762 [1 << 17]byte var x12763 [1 << 17]byte var x12764 [1 << 17]byte var x12765 [1 << 17]byte var x12766 [1 << 17]byte var x12767 [1 << 17]byte var x12768 [1 << 17]byte var x12769 [1 << 17]byte var x12770 [1 << 17]byte var x12771 [1 << 17]byte var x12772 [1 << 17]byte var x12773 [1 << 17]byte var x12774 [1 << 17]byte var x12775 [1 << 17]byte var x12776 [1 << 17]byte var x12777 [1 << 17]byte var x12778 [1 << 17]byte var x12779 [1 << 17]byte var x12780 [1 << 17]byte var x12781 [1 << 17]byte var x12782 [1 << 17]byte var x12783 [1 << 17]byte var x12784 [1 << 17]byte var x12785 [1 << 17]byte var x12786 [1 << 17]byte var x12787 [1 << 17]byte var x12788 [1 << 17]byte var x12789 [1 << 17]byte var x12790 [1 << 17]byte var x12791 [1 << 17]byte var x12792 [1 << 17]byte var x12793 [1 << 17]byte var x12794 [1 << 17]byte var x12795 [1 << 17]byte var x12796 [1 << 17]byte var x12797 [1 << 17]byte var x12798 [1 << 17]byte var x12799 [1 << 17]byte var x12800 [1 << 17]byte var x12801 [1 << 17]byte var x12802 [1 << 17]byte var x12803 [1 << 17]byte var x12804 [1 << 17]byte var x12805 [1 << 17]byte var x12806 [1 << 17]byte var x12807 [1 << 17]byte var x12808 [1 << 17]byte var x12809 [1 << 17]byte var x12810 [1 << 17]byte var x12811 [1 << 17]byte var x12812 [1 << 17]byte var x12813 [1 << 17]byte var x12814 [1 << 17]byte var x12815 [1 << 17]byte var x12816 [1 << 17]byte var x12817 [1 << 17]byte var x12818 [1 << 17]byte var x12819 [1 << 17]byte var x12820 [1 << 17]byte var x12821 [1 << 17]byte var x12822 [1 << 17]byte var x12823 [1 << 17]byte var x12824 [1 << 17]byte var x12825 [1 << 17]byte var x12826 [1 << 17]byte var x12827 [1 << 17]byte var x12828 [1 << 17]byte var x12829 [1 << 17]byte var x12830 [1 << 17]byte var x12831 [1 << 17]byte var x12832 [1 << 17]byte var x12833 [1 << 17]byte var x12834 [1 << 17]byte var x12835 [1 << 17]byte var x12836 [1 << 17]byte var x12837 [1 << 17]byte var x12838 [1 << 17]byte var x12839 [1 << 17]byte var x12840 [1 << 17]byte var x12841 [1 << 17]byte var x12842 [1 << 17]byte var x12843 [1 << 17]byte var x12844 [1 << 17]byte var x12845 [1 << 17]byte var x12846 [1 << 17]byte var x12847 [1 << 17]byte var x12848 [1 << 17]byte var x12849 [1 << 17]byte var x12850 [1 << 17]byte var x12851 [1 << 17]byte var x12852 [1 << 17]byte var x12853 [1 << 17]byte var x12854 [1 << 17]byte var x12855 [1 << 17]byte var x12856 [1 << 17]byte var x12857 [1 << 17]byte var x12858 [1 << 17]byte var x12859 [1 << 17]byte var x12860 [1 << 17]byte var x12861 [1 << 17]byte var x12862 [1 << 17]byte var x12863 [1 << 17]byte var x12864 [1 << 17]byte var x12865 [1 << 17]byte var x12866 [1 << 17]byte var x12867 [1 << 17]byte var x12868 [1 << 17]byte var x12869 [1 << 17]byte var x12870 [1 << 17]byte var x12871 [1 << 17]byte var x12872 [1 << 17]byte var x12873 [1 << 17]byte var x12874 [1 << 17]byte var x12875 [1 << 17]byte var x12876 [1 << 17]byte var x12877 [1 << 17]byte var x12878 [1 << 17]byte var x12879 [1 << 17]byte var x12880 [1 << 17]byte var x12881 [1 << 17]byte var x12882 [1 << 17]byte var x12883 [1 << 17]byte var x12884 [1 << 17]byte var x12885 [1 << 17]byte var x12886 [1 << 17]byte var x12887 [1 << 17]byte var x12888 [1 << 17]byte var x12889 [1 << 17]byte var x12890 [1 << 17]byte var x12891 [1 << 17]byte var x12892 [1 << 17]byte var x12893 [1 << 17]byte var x12894 [1 << 17]byte var x12895 [1 << 17]byte var x12896 [1 << 17]byte var x12897 [1 << 17]byte var x12898 [1 << 17]byte var x12899 [1 << 17]byte var x12900 [1 << 17]byte var x12901 [1 << 17]byte var x12902 [1 << 17]byte var x12903 [1 << 17]byte var x12904 [1 << 17]byte var x12905 [1 << 17]byte var x12906 [1 << 17]byte var x12907 [1 << 17]byte var x12908 [1 << 17]byte var x12909 [1 << 17]byte var x12910 [1 << 17]byte var x12911 [1 << 17]byte var x12912 [1 << 17]byte var x12913 [1 << 17]byte var x12914 [1 << 17]byte var x12915 [1 << 17]byte var x12916 [1 << 17]byte var x12917 [1 << 17]byte var x12918 [1 << 17]byte var x12919 [1 << 17]byte var x12920 [1 << 17]byte var x12921 [1 << 17]byte var x12922 [1 << 17]byte var x12923 [1 << 17]byte var x12924 [1 << 17]byte var x12925 [1 << 17]byte var x12926 [1 << 17]byte var x12927 [1 << 17]byte var x12928 [1 << 17]byte var x12929 [1 << 17]byte var x12930 [1 << 17]byte var x12931 [1 << 17]byte var x12932 [1 << 17]byte var x12933 [1 << 17]byte var x12934 [1 << 17]byte var x12935 [1 << 17]byte var x12936 [1 << 17]byte var x12937 [1 << 17]byte var x12938 [1 << 17]byte var x12939 [1 << 17]byte var x12940 [1 << 17]byte var x12941 [1 << 17]byte var x12942 [1 << 17]byte var x12943 [1 << 17]byte var x12944 [1 << 17]byte var x12945 [1 << 17]byte var x12946 [1 << 17]byte var x12947 [1 << 17]byte var x12948 [1 << 17]byte var x12949 [1 << 17]byte var x12950 [1 << 17]byte var x12951 [1 << 17]byte var x12952 [1 << 17]byte var x12953 [1 << 17]byte var x12954 [1 << 17]byte var x12955 [1 << 17]byte var x12956 [1 << 17]byte var x12957 [1 << 17]byte var x12958 [1 << 17]byte var x12959 [1 << 17]byte var x12960 [1 << 17]byte var x12961 [1 << 17]byte var x12962 [1 << 17]byte var x12963 [1 << 17]byte var x12964 [1 << 17]byte var x12965 [1 << 17]byte var x12966 [1 << 17]byte var x12967 [1 << 17]byte var x12968 [1 << 17]byte var x12969 [1 << 17]byte var x12970 [1 << 17]byte var x12971 [1 << 17]byte var x12972 [1 << 17]byte var x12973 [1 << 17]byte var x12974 [1 << 17]byte var x12975 [1 << 17]byte var x12976 [1 << 17]byte var x12977 [1 << 17]byte var x12978 [1 << 17]byte var x12979 [1 << 17]byte var x12980 [1 << 17]byte var x12981 [1 << 17]byte var x12982 [1 << 17]byte var x12983 [1 << 17]byte var x12984 [1 << 17]byte var x12985 [1 << 17]byte var x12986 [1 << 17]byte var x12987 [1 << 17]byte var x12988 [1 << 17]byte var x12989 [1 << 17]byte var x12990 [1 << 17]byte var x12991 [1 << 17]byte var x12992 [1 << 17]byte var x12993 [1 << 17]byte var x12994 [1 << 17]byte var x12995 [1 << 17]byte var x12996 [1 << 17]byte var x12997 [1 << 17]byte var x12998 [1 << 17]byte var x12999 [1 << 17]byte var x13000 [1 << 17]byte var x13001 [1 << 17]byte var x13002 [1 << 17]byte var x13003 [1 << 17]byte var x13004 [1 << 17]byte var x13005 [1 << 17]byte var x13006 [1 << 17]byte var x13007 [1 << 17]byte var x13008 [1 << 17]byte var x13009 [1 << 17]byte var x13010 [1 << 17]byte var x13011 [1 << 17]byte var x13012 [1 << 17]byte var x13013 [1 << 17]byte var x13014 [1 << 17]byte var x13015 [1 << 17]byte var x13016 [1 << 17]byte var x13017 [1 << 17]byte var x13018 [1 << 17]byte var x13019 [1 << 17]byte var x13020 [1 << 17]byte var x13021 [1 << 17]byte var x13022 [1 << 17]byte var x13023 [1 << 17]byte var x13024 [1 << 17]byte var x13025 [1 << 17]byte var x13026 [1 << 17]byte var x13027 [1 << 17]byte var x13028 [1 << 17]byte var x13029 [1 << 17]byte var x13030 [1 << 17]byte var x13031 [1 << 17]byte var x13032 [1 << 17]byte var x13033 [1 << 17]byte var x13034 [1 << 17]byte var x13035 [1 << 17]byte var x13036 [1 << 17]byte var x13037 [1 << 17]byte var x13038 [1 << 17]byte var x13039 [1 << 17]byte var x13040 [1 << 17]byte var x13041 [1 << 17]byte var x13042 [1 << 17]byte var x13043 [1 << 17]byte var x13044 [1 << 17]byte var x13045 [1 << 17]byte var x13046 [1 << 17]byte var x13047 [1 << 17]byte var x13048 [1 << 17]byte var x13049 [1 << 17]byte var x13050 [1 << 17]byte var x13051 [1 << 17]byte var x13052 [1 << 17]byte var x13053 [1 << 17]byte var x13054 [1 << 17]byte var x13055 [1 << 17]byte var x13056 [1 << 17]byte var x13057 [1 << 17]byte var x13058 [1 << 17]byte var x13059 [1 << 17]byte var x13060 [1 << 17]byte var x13061 [1 << 17]byte var x13062 [1 << 17]byte var x13063 [1 << 17]byte var x13064 [1 << 17]byte var x13065 [1 << 17]byte var x13066 [1 << 17]byte var x13067 [1 << 17]byte var x13068 [1 << 17]byte var x13069 [1 << 17]byte var x13070 [1 << 17]byte var x13071 [1 << 17]byte var x13072 [1 << 17]byte var x13073 [1 << 17]byte var x13074 [1 << 17]byte var x13075 [1 << 17]byte var x13076 [1 << 17]byte var x13077 [1 << 17]byte var x13078 [1 << 17]byte var x13079 [1 << 17]byte var x13080 [1 << 17]byte var x13081 [1 << 17]byte var x13082 [1 << 17]byte var x13083 [1 << 17]byte var x13084 [1 << 17]byte var x13085 [1 << 17]byte var x13086 [1 << 17]byte var x13087 [1 << 17]byte var x13088 [1 << 17]byte var x13089 [1 << 17]byte var x13090 [1 << 17]byte var x13091 [1 << 17]byte var x13092 [1 << 17]byte var x13093 [1 << 17]byte var x13094 [1 << 17]byte var x13095 [1 << 17]byte var x13096 [1 << 17]byte var x13097 [1 << 17]byte var x13098 [1 << 17]byte var x13099 [1 << 17]byte var x13100 [1 << 17]byte var x13101 [1 << 17]byte var x13102 [1 << 17]byte var x13103 [1 << 17]byte var x13104 [1 << 17]byte var x13105 [1 << 17]byte var x13106 [1 << 17]byte var x13107 [1 << 17]byte var x13108 [1 << 17]byte var x13109 [1 << 17]byte var x13110 [1 << 17]byte var x13111 [1 << 17]byte var x13112 [1 << 17]byte var x13113 [1 << 17]byte var x13114 [1 << 17]byte var x13115 [1 << 17]byte var x13116 [1 << 17]byte var x13117 [1 << 17]byte var x13118 [1 << 17]byte var x13119 [1 << 17]byte var x13120 [1 << 17]byte var x13121 [1 << 17]byte var x13122 [1 << 17]byte var x13123 [1 << 17]byte var x13124 [1 << 17]byte var x13125 [1 << 17]byte var x13126 [1 << 17]byte var x13127 [1 << 17]byte var x13128 [1 << 17]byte var x13129 [1 << 17]byte var x13130 [1 << 17]byte var x13131 [1 << 17]byte var x13132 [1 << 17]byte var x13133 [1 << 17]byte var x13134 [1 << 17]byte var x13135 [1 << 17]byte var x13136 [1 << 17]byte var x13137 [1 << 17]byte var x13138 [1 << 17]byte var x13139 [1 << 17]byte var x13140 [1 << 17]byte var x13141 [1 << 17]byte var x13142 [1 << 17]byte var x13143 [1 << 17]byte var x13144 [1 << 17]byte var x13145 [1 << 17]byte var x13146 [1 << 17]byte var x13147 [1 << 17]byte var x13148 [1 << 17]byte var x13149 [1 << 17]byte var x13150 [1 << 17]byte var x13151 [1 << 17]byte var x13152 [1 << 17]byte var x13153 [1 << 17]byte var x13154 [1 << 17]byte var x13155 [1 << 17]byte var x13156 [1 << 17]byte var x13157 [1 << 17]byte var x13158 [1 << 17]byte var x13159 [1 << 17]byte var x13160 [1 << 17]byte var x13161 [1 << 17]byte var x13162 [1 << 17]byte var x13163 [1 << 17]byte var x13164 [1 << 17]byte var x13165 [1 << 17]byte var x13166 [1 << 17]byte var x13167 [1 << 17]byte var x13168 [1 << 17]byte var x13169 [1 << 17]byte var x13170 [1 << 17]byte var x13171 [1 << 17]byte var x13172 [1 << 17]byte var x13173 [1 << 17]byte var x13174 [1 << 17]byte var x13175 [1 << 17]byte var x13176 [1 << 17]byte var x13177 [1 << 17]byte var x13178 [1 << 17]byte var x13179 [1 << 17]byte var x13180 [1 << 17]byte var x13181 [1 << 17]byte var x13182 [1 << 17]byte var x13183 [1 << 17]byte var x13184 [1 << 17]byte var x13185 [1 << 17]byte var x13186 [1 << 17]byte var x13187 [1 << 17]byte var x13188 [1 << 17]byte var x13189 [1 << 17]byte var x13190 [1 << 17]byte var x13191 [1 << 17]byte var x13192 [1 << 17]byte var x13193 [1 << 17]byte var x13194 [1 << 17]byte var x13195 [1 << 17]byte var x13196 [1 << 17]byte var x13197 [1 << 17]byte var x13198 [1 << 17]byte var x13199 [1 << 17]byte var x13200 [1 << 17]byte var x13201 [1 << 17]byte var x13202 [1 << 17]byte var x13203 [1 << 17]byte var x13204 [1 << 17]byte var x13205 [1 << 17]byte var x13206 [1 << 17]byte var x13207 [1 << 17]byte var x13208 [1 << 17]byte var x13209 [1 << 17]byte var x13210 [1 << 17]byte var x13211 [1 << 17]byte var x13212 [1 << 17]byte var x13213 [1 << 17]byte var x13214 [1 << 17]byte var x13215 [1 << 17]byte var x13216 [1 << 17]byte var x13217 [1 << 17]byte var x13218 [1 << 17]byte var x13219 [1 << 17]byte var x13220 [1 << 17]byte var x13221 [1 << 17]byte var x13222 [1 << 17]byte var x13223 [1 << 17]byte var x13224 [1 << 17]byte var x13225 [1 << 17]byte var x13226 [1 << 17]byte var x13227 [1 << 17]byte var x13228 [1 << 17]byte var x13229 [1 << 17]byte var x13230 [1 << 17]byte var x13231 [1 << 17]byte var x13232 [1 << 17]byte var x13233 [1 << 17]byte var x13234 [1 << 17]byte var x13235 [1 << 17]byte var x13236 [1 << 17]byte var x13237 [1 << 17]byte var x13238 [1 << 17]byte var x13239 [1 << 17]byte var x13240 [1 << 17]byte var x13241 [1 << 17]byte var x13242 [1 << 17]byte var x13243 [1 << 17]byte var x13244 [1 << 17]byte var x13245 [1 << 17]byte var x13246 [1 << 17]byte var x13247 [1 << 17]byte var x13248 [1 << 17]byte var x13249 [1 << 17]byte var x13250 [1 << 17]byte var x13251 [1 << 17]byte var x13252 [1 << 17]byte var x13253 [1 << 17]byte var x13254 [1 << 17]byte var x13255 [1 << 17]byte var x13256 [1 << 17]byte var x13257 [1 << 17]byte var x13258 [1 << 17]byte var x13259 [1 << 17]byte var x13260 [1 << 17]byte var x13261 [1 << 17]byte var x13262 [1 << 17]byte var x13263 [1 << 17]byte var x13264 [1 << 17]byte var x13265 [1 << 17]byte var x13266 [1 << 17]byte var x13267 [1 << 17]byte var x13268 [1 << 17]byte var x13269 [1 << 17]byte var x13270 [1 << 17]byte var x13271 [1 << 17]byte var x13272 [1 << 17]byte var x13273 [1 << 17]byte var x13274 [1 << 17]byte var x13275 [1 << 17]byte var x13276 [1 << 17]byte var x13277 [1 << 17]byte var x13278 [1 << 17]byte var x13279 [1 << 17]byte var x13280 [1 << 17]byte var x13281 [1 << 17]byte var x13282 [1 << 17]byte var x13283 [1 << 17]byte var x13284 [1 << 17]byte var x13285 [1 << 17]byte var x13286 [1 << 17]byte var x13287 [1 << 17]byte var x13288 [1 << 17]byte var x13289 [1 << 17]byte var x13290 [1 << 17]byte var x13291 [1 << 17]byte var x13292 [1 << 17]byte var x13293 [1 << 17]byte var x13294 [1 << 17]byte var x13295 [1 << 17]byte var x13296 [1 << 17]byte var x13297 [1 << 17]byte var x13298 [1 << 17]byte var x13299 [1 << 17]byte var x13300 [1 << 17]byte var x13301 [1 << 17]byte var x13302 [1 << 17]byte var x13303 [1 << 17]byte var x13304 [1 << 17]byte var x13305 [1 << 17]byte var x13306 [1 << 17]byte var x13307 [1 << 17]byte var x13308 [1 << 17]byte var x13309 [1 << 17]byte var x13310 [1 << 17]byte var x13311 [1 << 17]byte var x13312 [1 << 17]byte var x13313 [1 << 17]byte var x13314 [1 << 17]byte var x13315 [1 << 17]byte var x13316 [1 << 17]byte var x13317 [1 << 17]byte var x13318 [1 << 17]byte var x13319 [1 << 17]byte var x13320 [1 << 17]byte var x13321 [1 << 17]byte var x13322 [1 << 17]byte var x13323 [1 << 17]byte var x13324 [1 << 17]byte var x13325 [1 << 17]byte var x13326 [1 << 17]byte var x13327 [1 << 17]byte var x13328 [1 << 17]byte var x13329 [1 << 17]byte var x13330 [1 << 17]byte var x13331 [1 << 17]byte var x13332 [1 << 17]byte var x13333 [1 << 17]byte var x13334 [1 << 17]byte var x13335 [1 << 17]byte var x13336 [1 << 17]byte var x13337 [1 << 17]byte var x13338 [1 << 17]byte var x13339 [1 << 17]byte var x13340 [1 << 17]byte var x13341 [1 << 17]byte var x13342 [1 << 17]byte var x13343 [1 << 17]byte var x13344 [1 << 17]byte var x13345 [1 << 17]byte var x13346 [1 << 17]byte var x13347 [1 << 17]byte var x13348 [1 << 17]byte var x13349 [1 << 17]byte var x13350 [1 << 17]byte var x13351 [1 << 17]byte var x13352 [1 << 17]byte var x13353 [1 << 17]byte var x13354 [1 << 17]byte var x13355 [1 << 17]byte var x13356 [1 << 17]byte var x13357 [1 << 17]byte var x13358 [1 << 17]byte var x13359 [1 << 17]byte var x13360 [1 << 17]byte var x13361 [1 << 17]byte var x13362 [1 << 17]byte var x13363 [1 << 17]byte var x13364 [1 << 17]byte var x13365 [1 << 17]byte var x13366 [1 << 17]byte var x13367 [1 << 17]byte var x13368 [1 << 17]byte var x13369 [1 << 17]byte var x13370 [1 << 17]byte var x13371 [1 << 17]byte var x13372 [1 << 17]byte var x13373 [1 << 17]byte var x13374 [1 << 17]byte var x13375 [1 << 17]byte var x13376 [1 << 17]byte var x13377 [1 << 17]byte var x13378 [1 << 17]byte var x13379 [1 << 17]byte var x13380 [1 << 17]byte var x13381 [1 << 17]byte var x13382 [1 << 17]byte var x13383 [1 << 17]byte var x13384 [1 << 17]byte var x13385 [1 << 17]byte var x13386 [1 << 17]byte var x13387 [1 << 17]byte var x13388 [1 << 17]byte var x13389 [1 << 17]byte var x13390 [1 << 17]byte var x13391 [1 << 17]byte var x13392 [1 << 17]byte var x13393 [1 << 17]byte var x13394 [1 << 17]byte var x13395 [1 << 17]byte var x13396 [1 << 17]byte var x13397 [1 << 17]byte var x13398 [1 << 17]byte var x13399 [1 << 17]byte var x13400 [1 << 17]byte var x13401 [1 << 17]byte var x13402 [1 << 17]byte var x13403 [1 << 17]byte var x13404 [1 << 17]byte var x13405 [1 << 17]byte var x13406 [1 << 17]byte var x13407 [1 << 17]byte var x13408 [1 << 17]byte var x13409 [1 << 17]byte var x13410 [1 << 17]byte var x13411 [1 << 17]byte var x13412 [1 << 17]byte var x13413 [1 << 17]byte var x13414 [1 << 17]byte var x13415 [1 << 17]byte var x13416 [1 << 17]byte var x13417 [1 << 17]byte var x13418 [1 << 17]byte var x13419 [1 << 17]byte var x13420 [1 << 17]byte var x13421 [1 << 17]byte var x13422 [1 << 17]byte var x13423 [1 << 17]byte var x13424 [1 << 17]byte var x13425 [1 << 17]byte var x13426 [1 << 17]byte var x13427 [1 << 17]byte var x13428 [1 << 17]byte var x13429 [1 << 17]byte var x13430 [1 << 17]byte var x13431 [1 << 17]byte var x13432 [1 << 17]byte var x13433 [1 << 17]byte var x13434 [1 << 17]byte var x13435 [1 << 17]byte var x13436 [1 << 17]byte var x13437 [1 << 17]byte var x13438 [1 << 17]byte var x13439 [1 << 17]byte var x13440 [1 << 17]byte var x13441 [1 << 17]byte var x13442 [1 << 17]byte var x13443 [1 << 17]byte var x13444 [1 << 17]byte var x13445 [1 << 17]byte var x13446 [1 << 17]byte var x13447 [1 << 17]byte var x13448 [1 << 17]byte var x13449 [1 << 17]byte var x13450 [1 << 17]byte var x13451 [1 << 17]byte var x13452 [1 << 17]byte var x13453 [1 << 17]byte var x13454 [1 << 17]byte var x13455 [1 << 17]byte var x13456 [1 << 17]byte var x13457 [1 << 17]byte var x13458 [1 << 17]byte var x13459 [1 << 17]byte var x13460 [1 << 17]byte var x13461 [1 << 17]byte var x13462 [1 << 17]byte var x13463 [1 << 17]byte var x13464 [1 << 17]byte var x13465 [1 << 17]byte var x13466 [1 << 17]byte var x13467 [1 << 17]byte var x13468 [1 << 17]byte var x13469 [1 << 17]byte var x13470 [1 << 17]byte var x13471 [1 << 17]byte var x13472 [1 << 17]byte var x13473 [1 << 17]byte var x13474 [1 << 17]byte var x13475 [1 << 17]byte var x13476 [1 << 17]byte var x13477 [1 << 17]byte var x13478 [1 << 17]byte var x13479 [1 << 17]byte var x13480 [1 << 17]byte var x13481 [1 << 17]byte var x13482 [1 << 17]byte var x13483 [1 << 17]byte var x13484 [1 << 17]byte var x13485 [1 << 17]byte var x13486 [1 << 17]byte var x13487 [1 << 17]byte var x13488 [1 << 17]byte var x13489 [1 << 17]byte var x13490 [1 << 17]byte var x13491 [1 << 17]byte var x13492 [1 << 17]byte var x13493 [1 << 17]byte var x13494 [1 << 17]byte var x13495 [1 << 17]byte var x13496 [1 << 17]byte var x13497 [1 << 17]byte var x13498 [1 << 17]byte var x13499 [1 << 17]byte var x13500 [1 << 17]byte var x13501 [1 << 17]byte var x13502 [1 << 17]byte var x13503 [1 << 17]byte var x13504 [1 << 17]byte var x13505 [1 << 17]byte var x13506 [1 << 17]byte var x13507 [1 << 17]byte var x13508 [1 << 17]byte var x13509 [1 << 17]byte var x13510 [1 << 17]byte var x13511 [1 << 17]byte var x13512 [1 << 17]byte var x13513 [1 << 17]byte var x13514 [1 << 17]byte var x13515 [1 << 17]byte var x13516 [1 << 17]byte var x13517 [1 << 17]byte var x13518 [1 << 17]byte var x13519 [1 << 17]byte var x13520 [1 << 17]byte var x13521 [1 << 17]byte var x13522 [1 << 17]byte var x13523 [1 << 17]byte var x13524 [1 << 17]byte var x13525 [1 << 17]byte var x13526 [1 << 17]byte var x13527 [1 << 17]byte var x13528 [1 << 17]byte var x13529 [1 << 17]byte var x13530 [1 << 17]byte var x13531 [1 << 17]byte var x13532 [1 << 17]byte var x13533 [1 << 17]byte var x13534 [1 << 17]byte var x13535 [1 << 17]byte var x13536 [1 << 17]byte var x13537 [1 << 17]byte var x13538 [1 << 17]byte var x13539 [1 << 17]byte var x13540 [1 << 17]byte var x13541 [1 << 17]byte var x13542 [1 << 17]byte var x13543 [1 << 17]byte var x13544 [1 << 17]byte var x13545 [1 << 17]byte var x13546 [1 << 17]byte var x13547 [1 << 17]byte var x13548 [1 << 17]byte var x13549 [1 << 17]byte var x13550 [1 << 17]byte var x13551 [1 << 17]byte var x13552 [1 << 17]byte var x13553 [1 << 17]byte var x13554 [1 << 17]byte var x13555 [1 << 17]byte var x13556 [1 << 17]byte var x13557 [1 << 17]byte var x13558 [1 << 17]byte var x13559 [1 << 17]byte var x13560 [1 << 17]byte var x13561 [1 << 17]byte var x13562 [1 << 17]byte var x13563 [1 << 17]byte var x13564 [1 << 17]byte var x13565 [1 << 17]byte var x13566 [1 << 17]byte var x13567 [1 << 17]byte var x13568 [1 << 17]byte var x13569 [1 << 17]byte var x13570 [1 << 17]byte var x13571 [1 << 17]byte var x13572 [1 << 17]byte var x13573 [1 << 17]byte var x13574 [1 << 17]byte var x13575 [1 << 17]byte var x13576 [1 << 17]byte var x13577 [1 << 17]byte var x13578 [1 << 17]byte var x13579 [1 << 17]byte var x13580 [1 << 17]byte var x13581 [1 << 17]byte var x13582 [1 << 17]byte var x13583 [1 << 17]byte var x13584 [1 << 17]byte var x13585 [1 << 17]byte var x13586 [1 << 17]byte var x13587 [1 << 17]byte var x13588 [1 << 17]byte var x13589 [1 << 17]byte var x13590 [1 << 17]byte var x13591 [1 << 17]byte var x13592 [1 << 17]byte var x13593 [1 << 17]byte var x13594 [1 << 17]byte var x13595 [1 << 17]byte var x13596 [1 << 17]byte var x13597 [1 << 17]byte var x13598 [1 << 17]byte var x13599 [1 << 17]byte var x13600 [1 << 17]byte var x13601 [1 << 17]byte var x13602 [1 << 17]byte var x13603 [1 << 17]byte var x13604 [1 << 17]byte var x13605 [1 << 17]byte var x13606 [1 << 17]byte var x13607 [1 << 17]byte var x13608 [1 << 17]byte var x13609 [1 << 17]byte var x13610 [1 << 17]byte var x13611 [1 << 17]byte var x13612 [1 << 17]byte var x13613 [1 << 17]byte var x13614 [1 << 17]byte var x13615 [1 << 17]byte var x13616 [1 << 17]byte var x13617 [1 << 17]byte var x13618 [1 << 17]byte var x13619 [1 << 17]byte var x13620 [1 << 17]byte var x13621 [1 << 17]byte var x13622 [1 << 17]byte var x13623 [1 << 17]byte var x13624 [1 << 17]byte var x13625 [1 << 17]byte var x13626 [1 << 17]byte var x13627 [1 << 17]byte var x13628 [1 << 17]byte var x13629 [1 << 17]byte var x13630 [1 << 17]byte var x13631 [1 << 17]byte var x13632 [1 << 17]byte var x13633 [1 << 17]byte var x13634 [1 << 17]byte var x13635 [1 << 17]byte var x13636 [1 << 17]byte var x13637 [1 << 17]byte var x13638 [1 << 17]byte var x13639 [1 << 17]byte var x13640 [1 << 17]byte var x13641 [1 << 17]byte var x13642 [1 << 17]byte var x13643 [1 << 17]byte var x13644 [1 << 17]byte var x13645 [1 << 17]byte var x13646 [1 << 17]byte var x13647 [1 << 17]byte var x13648 [1 << 17]byte var x13649 [1 << 17]byte var x13650 [1 << 17]byte var x13651 [1 << 17]byte var x13652 [1 << 17]byte var x13653 [1 << 17]byte var x13654 [1 << 17]byte var x13655 [1 << 17]byte var x13656 [1 << 17]byte var x13657 [1 << 17]byte var x13658 [1 << 17]byte var x13659 [1 << 17]byte var x13660 [1 << 17]byte var x13661 [1 << 17]byte var x13662 [1 << 17]byte var x13663 [1 << 17]byte var x13664 [1 << 17]byte var x13665 [1 << 17]byte var x13666 [1 << 17]byte var x13667 [1 << 17]byte var x13668 [1 << 17]byte var x13669 [1 << 17]byte var x13670 [1 << 17]byte var x13671 [1 << 17]byte var x13672 [1 << 17]byte var x13673 [1 << 17]byte var x13674 [1 << 17]byte var x13675 [1 << 17]byte var x13676 [1 << 17]byte var x13677 [1 << 17]byte var x13678 [1 << 17]byte var x13679 [1 << 17]byte var x13680 [1 << 17]byte var x13681 [1 << 17]byte var x13682 [1 << 17]byte var x13683 [1 << 17]byte var x13684 [1 << 17]byte var x13685 [1 << 17]byte var x13686 [1 << 17]byte var x13687 [1 << 17]byte var x13688 [1 << 17]byte var x13689 [1 << 17]byte var x13690 [1 << 17]byte var x13691 [1 << 17]byte var x13692 [1 << 17]byte var x13693 [1 << 17]byte var x13694 [1 << 17]byte var x13695 [1 << 17]byte var x13696 [1 << 17]byte var x13697 [1 << 17]byte var x13698 [1 << 17]byte var x13699 [1 << 17]byte var x13700 [1 << 17]byte var x13701 [1 << 17]byte var x13702 [1 << 17]byte var x13703 [1 << 17]byte var x13704 [1 << 17]byte var x13705 [1 << 17]byte var x13706 [1 << 17]byte var x13707 [1 << 17]byte var x13708 [1 << 17]byte var x13709 [1 << 17]byte var x13710 [1 << 17]byte var x13711 [1 << 17]byte var x13712 [1 << 17]byte var x13713 [1 << 17]byte var x13714 [1 << 17]byte var x13715 [1 << 17]byte var x13716 [1 << 17]byte var x13717 [1 << 17]byte var x13718 [1 << 17]byte var x13719 [1 << 17]byte var x13720 [1 << 17]byte var x13721 [1 << 17]byte var x13722 [1 << 17]byte var x13723 [1 << 17]byte var x13724 [1 << 17]byte var x13725 [1 << 17]byte var x13726 [1 << 17]byte var x13727 [1 << 17]byte var x13728 [1 << 17]byte var x13729 [1 << 17]byte var x13730 [1 << 17]byte var x13731 [1 << 17]byte var x13732 [1 << 17]byte var x13733 [1 << 17]byte var x13734 [1 << 17]byte var x13735 [1 << 17]byte var x13736 [1 << 17]byte var x13737 [1 << 17]byte var x13738 [1 << 17]byte var x13739 [1 << 17]byte var x13740 [1 << 17]byte var x13741 [1 << 17]byte var x13742 [1 << 17]byte var x13743 [1 << 17]byte var x13744 [1 << 17]byte var x13745 [1 << 17]byte var x13746 [1 << 17]byte var x13747 [1 << 17]byte var x13748 [1 << 17]byte var x13749 [1 << 17]byte var x13750 [1 << 17]byte var x13751 [1 << 17]byte var x13752 [1 << 17]byte var x13753 [1 << 17]byte var x13754 [1 << 17]byte var x13755 [1 << 17]byte var x13756 [1 << 17]byte var x13757 [1 << 17]byte var x13758 [1 << 17]byte var x13759 [1 << 17]byte var x13760 [1 << 17]byte var x13761 [1 << 17]byte var x13762 [1 << 17]byte var x13763 [1 << 17]byte var x13764 [1 << 17]byte var x13765 [1 << 17]byte var x13766 [1 << 17]byte var x13767 [1 << 17]byte var x13768 [1 << 17]byte var x13769 [1 << 17]byte var x13770 [1 << 17]byte var x13771 [1 << 17]byte var x13772 [1 << 17]byte var x13773 [1 << 17]byte var x13774 [1 << 17]byte var x13775 [1 << 17]byte var x13776 [1 << 17]byte var x13777 [1 << 17]byte var x13778 [1 << 17]byte var x13779 [1 << 17]byte var x13780 [1 << 17]byte var x13781 [1 << 17]byte var x13782 [1 << 17]byte var x13783 [1 << 17]byte var x13784 [1 << 17]byte var x13785 [1 << 17]byte var x13786 [1 << 17]byte var x13787 [1 << 17]byte var x13788 [1 << 17]byte var x13789 [1 << 17]byte var x13790 [1 << 17]byte var x13791 [1 << 17]byte var x13792 [1 << 17]byte var x13793 [1 << 17]byte var x13794 [1 << 17]byte var x13795 [1 << 17]byte var x13796 [1 << 17]byte var x13797 [1 << 17]byte var x13798 [1 << 17]byte var x13799 [1 << 17]byte var x13800 [1 << 17]byte var x13801 [1 << 17]byte var x13802 [1 << 17]byte var x13803 [1 << 17]byte var x13804 [1 << 17]byte var x13805 [1 << 17]byte var x13806 [1 << 17]byte var x13807 [1 << 17]byte var x13808 [1 << 17]byte var x13809 [1 << 17]byte var x13810 [1 << 17]byte var x13811 [1 << 17]byte var x13812 [1 << 17]byte var x13813 [1 << 17]byte var x13814 [1 << 17]byte var x13815 [1 << 17]byte var x13816 [1 << 17]byte var x13817 [1 << 17]byte var x13818 [1 << 17]byte var x13819 [1 << 17]byte var x13820 [1 << 17]byte var x13821 [1 << 17]byte var x13822 [1 << 17]byte var x13823 [1 << 17]byte var x13824 [1 << 17]byte var x13825 [1 << 17]byte var x13826 [1 << 17]byte var x13827 [1 << 17]byte var x13828 [1 << 17]byte var x13829 [1 << 17]byte var x13830 [1 << 17]byte var x13831 [1 << 17]byte var x13832 [1 << 17]byte var x13833 [1 << 17]byte var x13834 [1 << 17]byte var x13835 [1 << 17]byte var x13836 [1 << 17]byte var x13837 [1 << 17]byte var x13838 [1 << 17]byte var x13839 [1 << 17]byte var x13840 [1 << 17]byte var x13841 [1 << 17]byte var x13842 [1 << 17]byte var x13843 [1 << 17]byte var x13844 [1 << 17]byte var x13845 [1 << 17]byte var x13846 [1 << 17]byte var x13847 [1 << 17]byte var x13848 [1 << 17]byte var x13849 [1 << 17]byte var x13850 [1 << 17]byte var x13851 [1 << 17]byte var x13852 [1 << 17]byte var x13853 [1 << 17]byte var x13854 [1 << 17]byte var x13855 [1 << 17]byte var x13856 [1 << 17]byte var x13857 [1 << 17]byte var x13858 [1 << 17]byte var x13859 [1 << 17]byte var x13860 [1 << 17]byte var x13861 [1 << 17]byte var x13862 [1 << 17]byte var x13863 [1 << 17]byte var x13864 [1 << 17]byte var x13865 [1 << 17]byte var x13866 [1 << 17]byte var x13867 [1 << 17]byte var x13868 [1 << 17]byte var x13869 [1 << 17]byte var x13870 [1 << 17]byte var x13871 [1 << 17]byte var x13872 [1 << 17]byte var x13873 [1 << 17]byte var x13874 [1 << 17]byte var x13875 [1 << 17]byte var x13876 [1 << 17]byte var x13877 [1 << 17]byte var x13878 [1 << 17]byte var x13879 [1 << 17]byte var x13880 [1 << 17]byte var x13881 [1 << 17]byte var x13882 [1 << 17]byte var x13883 [1 << 17]byte var x13884 [1 << 17]byte var x13885 [1 << 17]byte var x13886 [1 << 17]byte var x13887 [1 << 17]byte var x13888 [1 << 17]byte var x13889 [1 << 17]byte var x13890 [1 << 17]byte var x13891 [1 << 17]byte var x13892 [1 << 17]byte var x13893 [1 << 17]byte var x13894 [1 << 17]byte var x13895 [1 << 17]byte var x13896 [1 << 17]byte var x13897 [1 << 17]byte var x13898 [1 << 17]byte var x13899 [1 << 17]byte var x13900 [1 << 17]byte var x13901 [1 << 17]byte var x13902 [1 << 17]byte var x13903 [1 << 17]byte var x13904 [1 << 17]byte var x13905 [1 << 17]byte var x13906 [1 << 17]byte var x13907 [1 << 17]byte var x13908 [1 << 17]byte var x13909 [1 << 17]byte var x13910 [1 << 17]byte var x13911 [1 << 17]byte var x13912 [1 << 17]byte var x13913 [1 << 17]byte var x13914 [1 << 17]byte var x13915 [1 << 17]byte var x13916 [1 << 17]byte var x13917 [1 << 17]byte var x13918 [1 << 17]byte var x13919 [1 << 17]byte var x13920 [1 << 17]byte var x13921 [1 << 17]byte var x13922 [1 << 17]byte var x13923 [1 << 17]byte var x13924 [1 << 17]byte var x13925 [1 << 17]byte var x13926 [1 << 17]byte var x13927 [1 << 17]byte var x13928 [1 << 17]byte var x13929 [1 << 17]byte var x13930 [1 << 17]byte var x13931 [1 << 17]byte var x13932 [1 << 17]byte var x13933 [1 << 17]byte var x13934 [1 << 17]byte var x13935 [1 << 17]byte var x13936 [1 << 17]byte var x13937 [1 << 17]byte var x13938 [1 << 17]byte var x13939 [1 << 17]byte var x13940 [1 << 17]byte var x13941 [1 << 17]byte var x13942 [1 << 17]byte var x13943 [1 << 17]byte var x13944 [1 << 17]byte var x13945 [1 << 17]byte var x13946 [1 << 17]byte var x13947 [1 << 17]byte var x13948 [1 << 17]byte var x13949 [1 << 17]byte var x13950 [1 << 17]byte var x13951 [1 << 17]byte var x13952 [1 << 17]byte var x13953 [1 << 17]byte var x13954 [1 << 17]byte var x13955 [1 << 17]byte var x13956 [1 << 17]byte var x13957 [1 << 17]byte var x13958 [1 << 17]byte var x13959 [1 << 17]byte var x13960 [1 << 17]byte var x13961 [1 << 17]byte var x13962 [1 << 17]byte var x13963 [1 << 17]byte var x13964 [1 << 17]byte var x13965 [1 << 17]byte var x13966 [1 << 17]byte var x13967 [1 << 17]byte var x13968 [1 << 17]byte var x13969 [1 << 17]byte var x13970 [1 << 17]byte var x13971 [1 << 17]byte var x13972 [1 << 17]byte var x13973 [1 << 17]byte var x13974 [1 << 17]byte var x13975 [1 << 17]byte var x13976 [1 << 17]byte var x13977 [1 << 17]byte var x13978 [1 << 17]byte var x13979 [1 << 17]byte var x13980 [1 << 17]byte var x13981 [1 << 17]byte var x13982 [1 << 17]byte var x13983 [1 << 17]byte var x13984 [1 << 17]byte var x13985 [1 << 17]byte var x13986 [1 << 17]byte var x13987 [1 << 17]byte var x13988 [1 << 17]byte var x13989 [1 << 17]byte var x13990 [1 << 17]byte var x13991 [1 << 17]byte var x13992 [1 << 17]byte var x13993 [1 << 17]byte var x13994 [1 << 17]byte var x13995 [1 << 17]byte var x13996 [1 << 17]byte var x13997 [1 << 17]byte var x13998 [1 << 17]byte var x13999 [1 << 17]byte var x14000 [1 << 17]byte var x14001 [1 << 17]byte var x14002 [1 << 17]byte var x14003 [1 << 17]byte var x14004 [1 << 17]byte var x14005 [1 << 17]byte var x14006 [1 << 17]byte var x14007 [1 << 17]byte var x14008 [1 << 17]byte var x14009 [1 << 17]byte var x14010 [1 << 17]byte var x14011 [1 << 17]byte var x14012 [1 << 17]byte var x14013 [1 << 17]byte var x14014 [1 << 17]byte var x14015 [1 << 17]byte var x14016 [1 << 17]byte var x14017 [1 << 17]byte var x14018 [1 << 17]byte var x14019 [1 << 17]byte var x14020 [1 << 17]byte var x14021 [1 << 17]byte var x14022 [1 << 17]byte var x14023 [1 << 17]byte var x14024 [1 << 17]byte var x14025 [1 << 17]byte var x14026 [1 << 17]byte var x14027 [1 << 17]byte var x14028 [1 << 17]byte var x14029 [1 << 17]byte var x14030 [1 << 17]byte var x14031 [1 << 17]byte var x14032 [1 << 17]byte var x14033 [1 << 17]byte var x14034 [1 << 17]byte var x14035 [1 << 17]byte var x14036 [1 << 17]byte var x14037 [1 << 17]byte var x14038 [1 << 17]byte var x14039 [1 << 17]byte var x14040 [1 << 17]byte var x14041 [1 << 17]byte var x14042 [1 << 17]byte var x14043 [1 << 17]byte var x14044 [1 << 17]byte var x14045 [1 << 17]byte var x14046 [1 << 17]byte var x14047 [1 << 17]byte var x14048 [1 << 17]byte var x14049 [1 << 17]byte var x14050 [1 << 17]byte var x14051 [1 << 17]byte var x14052 [1 << 17]byte var x14053 [1 << 17]byte var x14054 [1 << 17]byte var x14055 [1 << 17]byte var x14056 [1 << 17]byte var x14057 [1 << 17]byte var x14058 [1 << 17]byte var x14059 [1 << 17]byte var x14060 [1 << 17]byte var x14061 [1 << 17]byte var x14062 [1 << 17]byte var x14063 [1 << 17]byte var x14064 [1 << 17]byte var x14065 [1 << 17]byte var x14066 [1 << 17]byte var x14067 [1 << 17]byte var x14068 [1 << 17]byte var x14069 [1 << 17]byte var x14070 [1 << 17]byte var x14071 [1 << 17]byte var x14072 [1 << 17]byte var x14073 [1 << 17]byte var x14074 [1 << 17]byte var x14075 [1 << 17]byte var x14076 [1 << 17]byte var x14077 [1 << 17]byte var x14078 [1 << 17]byte var x14079 [1 << 17]byte var x14080 [1 << 17]byte var x14081 [1 << 17]byte var x14082 [1 << 17]byte var x14083 [1 << 17]byte var x14084 [1 << 17]byte var x14085 [1 << 17]byte var x14086 [1 << 17]byte var x14087 [1 << 17]byte var x14088 [1 << 17]byte var x14089 [1 << 17]byte var x14090 [1 << 17]byte var x14091 [1 << 17]byte var x14092 [1 << 17]byte var x14093 [1 << 17]byte var x14094 [1 << 17]byte var x14095 [1 << 17]byte var x14096 [1 << 17]byte var x14097 [1 << 17]byte var x14098 [1 << 17]byte var x14099 [1 << 17]byte var x14100 [1 << 17]byte var x14101 [1 << 17]byte var x14102 [1 << 17]byte var x14103 [1 << 17]byte var x14104 [1 << 17]byte var x14105 [1 << 17]byte var x14106 [1 << 17]byte var x14107 [1 << 17]byte var x14108 [1 << 17]byte var x14109 [1 << 17]byte var x14110 [1 << 17]byte var x14111 [1 << 17]byte var x14112 [1 << 17]byte var x14113 [1 << 17]byte var x14114 [1 << 17]byte var x14115 [1 << 17]byte var x14116 [1 << 17]byte var x14117 [1 << 17]byte var x14118 [1 << 17]byte var x14119 [1 << 17]byte var x14120 [1 << 17]byte var x14121 [1 << 17]byte var x14122 [1 << 17]byte var x14123 [1 << 17]byte var x14124 [1 << 17]byte var x14125 [1 << 17]byte var x14126 [1 << 17]byte var x14127 [1 << 17]byte var x14128 [1 << 17]byte var x14129 [1 << 17]byte var x14130 [1 << 17]byte var x14131 [1 << 17]byte var x14132 [1 << 17]byte var x14133 [1 << 17]byte var x14134 [1 << 17]byte var x14135 [1 << 17]byte var x14136 [1 << 17]byte var x14137 [1 << 17]byte var x14138 [1 << 17]byte var x14139 [1 << 17]byte var x14140 [1 << 17]byte var x14141 [1 << 17]byte var x14142 [1 << 17]byte var x14143 [1 << 17]byte var x14144 [1 << 17]byte var x14145 [1 << 17]byte var x14146 [1 << 17]byte var x14147 [1 << 17]byte var x14148 [1 << 17]byte var x14149 [1 << 17]byte var x14150 [1 << 17]byte var x14151 [1 << 17]byte var x14152 [1 << 17]byte var x14153 [1 << 17]byte var x14154 [1 << 17]byte var x14155 [1 << 17]byte var x14156 [1 << 17]byte var x14157 [1 << 17]byte var x14158 [1 << 17]byte var x14159 [1 << 17]byte var x14160 [1 << 17]byte var x14161 [1 << 17]byte var x14162 [1 << 17]byte var x14163 [1 << 17]byte var x14164 [1 << 17]byte var x14165 [1 << 17]byte var x14166 [1 << 17]byte var x14167 [1 << 17]byte var x14168 [1 << 17]byte var x14169 [1 << 17]byte var x14170 [1 << 17]byte var x14171 [1 << 17]byte var x14172 [1 << 17]byte var x14173 [1 << 17]byte var x14174 [1 << 17]byte var x14175 [1 << 17]byte var x14176 [1 << 17]byte var x14177 [1 << 17]byte var x14178 [1 << 17]byte var x14179 [1 << 17]byte var x14180 [1 << 17]byte var x14181 [1 << 17]byte var x14182 [1 << 17]byte var x14183 [1 << 17]byte var x14184 [1 << 17]byte var x14185 [1 << 17]byte var x14186 [1 << 17]byte var x14187 [1 << 17]byte var x14188 [1 << 17]byte var x14189 [1 << 17]byte var x14190 [1 << 17]byte var x14191 [1 << 17]byte var x14192 [1 << 17]byte var x14193 [1 << 17]byte var x14194 [1 << 17]byte var x14195 [1 << 17]byte var x14196 [1 << 17]byte var x14197 [1 << 17]byte var x14198 [1 << 17]byte var x14199 [1 << 17]byte var x14200 [1 << 17]byte var x14201 [1 << 17]byte var x14202 [1 << 17]byte var x14203 [1 << 17]byte var x14204 [1 << 17]byte var x14205 [1 << 17]byte var x14206 [1 << 17]byte var x14207 [1 << 17]byte var x14208 [1 << 17]byte var x14209 [1 << 17]byte var x14210 [1 << 17]byte var x14211 [1 << 17]byte var x14212 [1 << 17]byte var x14213 [1 << 17]byte var x14214 [1 << 17]byte var x14215 [1 << 17]byte var x14216 [1 << 17]byte var x14217 [1 << 17]byte var x14218 [1 << 17]byte var x14219 [1 << 17]byte var x14220 [1 << 17]byte var x14221 [1 << 17]byte var x14222 [1 << 17]byte var x14223 [1 << 17]byte var x14224 [1 << 17]byte var x14225 [1 << 17]byte var x14226 [1 << 17]byte var x14227 [1 << 17]byte var x14228 [1 << 17]byte var x14229 [1 << 17]byte var x14230 [1 << 17]byte var x14231 [1 << 17]byte var x14232 [1 << 17]byte var x14233 [1 << 17]byte var x14234 [1 << 17]byte var x14235 [1 << 17]byte var x14236 [1 << 17]byte var x14237 [1 << 17]byte var x14238 [1 << 17]byte var x14239 [1 << 17]byte var x14240 [1 << 17]byte var x14241 [1 << 17]byte var x14242 [1 << 17]byte var x14243 [1 << 17]byte var x14244 [1 << 17]byte var x14245 [1 << 17]byte var x14246 [1 << 17]byte var x14247 [1 << 17]byte var x14248 [1 << 17]byte var x14249 [1 << 17]byte var x14250 [1 << 17]byte var x14251 [1 << 17]byte var x14252 [1 << 17]byte var x14253 [1 << 17]byte var x14254 [1 << 17]byte var x14255 [1 << 17]byte var x14256 [1 << 17]byte var x14257 [1 << 17]byte var x14258 [1 << 17]byte var x14259 [1 << 17]byte var x14260 [1 << 17]byte var x14261 [1 << 17]byte var x14262 [1 << 17]byte var x14263 [1 << 17]byte var x14264 [1 << 17]byte var x14265 [1 << 17]byte var x14266 [1 << 17]byte var x14267 [1 << 17]byte var x14268 [1 << 17]byte var x14269 [1 << 17]byte var x14270 [1 << 17]byte var x14271 [1 << 17]byte var x14272 [1 << 17]byte var x14273 [1 << 17]byte var x14274 [1 << 17]byte var x14275 [1 << 17]byte var x14276 [1 << 17]byte var x14277 [1 << 17]byte var x14278 [1 << 17]byte var x14279 [1 << 17]byte var x14280 [1 << 17]byte var x14281 [1 << 17]byte var x14282 [1 << 17]byte var x14283 [1 << 17]byte var x14284 [1 << 17]byte var x14285 [1 << 17]byte var x14286 [1 << 17]byte var x14287 [1 << 17]byte var x14288 [1 << 17]byte var x14289 [1 << 17]byte var x14290 [1 << 17]byte var x14291 [1 << 17]byte var x14292 [1 << 17]byte var x14293 [1 << 17]byte var x14294 [1 << 17]byte var x14295 [1 << 17]byte var x14296 [1 << 17]byte var x14297 [1 << 17]byte var x14298 [1 << 17]byte var x14299 [1 << 17]byte var x14300 [1 << 17]byte var x14301 [1 << 17]byte var x14302 [1 << 17]byte var x14303 [1 << 17]byte var x14304 [1 << 17]byte var x14305 [1 << 17]byte var x14306 [1 << 17]byte var x14307 [1 << 17]byte var x14308 [1 << 17]byte var x14309 [1 << 17]byte var x14310 [1 << 17]byte var x14311 [1 << 17]byte var x14312 [1 << 17]byte var x14313 [1 << 17]byte var x14314 [1 << 17]byte var x14315 [1 << 17]byte var x14316 [1 << 17]byte var x14317 [1 << 17]byte var x14318 [1 << 17]byte var x14319 [1 << 17]byte var x14320 [1 << 17]byte var x14321 [1 << 17]byte var x14322 [1 << 17]byte var x14323 [1 << 17]byte var x14324 [1 << 17]byte var x14325 [1 << 17]byte var x14326 [1 << 17]byte var x14327 [1 << 17]byte var x14328 [1 << 17]byte var x14329 [1 << 17]byte var x14330 [1 << 17]byte var x14331 [1 << 17]byte var x14332 [1 << 17]byte var x14333 [1 << 17]byte var x14334 [1 << 17]byte var x14335 [1 << 17]byte var x14336 [1 << 17]byte var x14337 [1 << 17]byte var x14338 [1 << 17]byte var x14339 [1 << 17]byte var x14340 [1 << 17]byte var x14341 [1 << 17]byte var x14342 [1 << 17]byte var x14343 [1 << 17]byte var x14344 [1 << 17]byte var x14345 [1 << 17]byte var x14346 [1 << 17]byte var x14347 [1 << 17]byte var x14348 [1 << 17]byte var x14349 [1 << 17]byte var x14350 [1 << 17]byte var x14351 [1 << 17]byte var x14352 [1 << 17]byte var x14353 [1 << 17]byte var x14354 [1 << 17]byte var x14355 [1 << 17]byte var x14356 [1 << 17]byte var x14357 [1 << 17]byte var x14358 [1 << 17]byte var x14359 [1 << 17]byte var x14360 [1 << 17]byte var x14361 [1 << 17]byte var x14362 [1 << 17]byte var x14363 [1 << 17]byte var x14364 [1 << 17]byte var x14365 [1 << 17]byte var x14366 [1 << 17]byte var x14367 [1 << 17]byte var x14368 [1 << 17]byte var x14369 [1 << 17]byte var x14370 [1 << 17]byte var x14371 [1 << 17]byte var x14372 [1 << 17]byte var x14373 [1 << 17]byte var x14374 [1 << 17]byte var x14375 [1 << 17]byte var x14376 [1 << 17]byte var x14377 [1 << 17]byte var x14378 [1 << 17]byte var x14379 [1 << 17]byte var x14380 [1 << 17]byte var x14381 [1 << 17]byte var x14382 [1 << 17]byte var x14383 [1 << 17]byte var x14384 [1 << 17]byte var x14385 [1 << 17]byte var x14386 [1 << 17]byte var x14387 [1 << 17]byte var x14388 [1 << 17]byte var x14389 [1 << 17]byte var x14390 [1 << 17]byte var x14391 [1 << 17]byte var x14392 [1 << 17]byte var x14393 [1 << 17]byte var x14394 [1 << 17]byte var x14395 [1 << 17]byte var x14396 [1 << 17]byte var x14397 [1 << 17]byte var x14398 [1 << 17]byte var x14399 [1 << 17]byte var x14400 [1 << 17]byte var x14401 [1 << 17]byte var x14402 [1 << 17]byte var x14403 [1 << 17]byte var x14404 [1 << 17]byte var x14405 [1 << 17]byte var x14406 [1 << 17]byte var x14407 [1 << 17]byte var x14408 [1 << 17]byte var x14409 [1 << 17]byte var x14410 [1 << 17]byte var x14411 [1 << 17]byte var x14412 [1 << 17]byte var x14413 [1 << 17]byte var x14414 [1 << 17]byte var x14415 [1 << 17]byte var x14416 [1 << 17]byte var x14417 [1 << 17]byte var x14418 [1 << 17]byte var x14419 [1 << 17]byte var x14420 [1 << 17]byte var x14421 [1 << 17]byte var x14422 [1 << 17]byte var x14423 [1 << 17]byte var x14424 [1 << 17]byte var x14425 [1 << 17]byte var x14426 [1 << 17]byte var x14427 [1 << 17]byte var x14428 [1 << 17]byte var x14429 [1 << 17]byte var x14430 [1 << 17]byte var x14431 [1 << 17]byte var x14432 [1 << 17]byte var x14433 [1 << 17]byte var x14434 [1 << 17]byte var x14435 [1 << 17]byte var x14436 [1 << 17]byte var x14437 [1 << 17]byte var x14438 [1 << 17]byte var x14439 [1 << 17]byte var x14440 [1 << 17]byte var x14441 [1 << 17]byte var x14442 [1 << 17]byte var x14443 [1 << 17]byte var x14444 [1 << 17]byte var x14445 [1 << 17]byte var x14446 [1 << 17]byte var x14447 [1 << 17]byte var x14448 [1 << 17]byte var x14449 [1 << 17]byte var x14450 [1 << 17]byte var x14451 [1 << 17]byte var x14452 [1 << 17]byte var x14453 [1 << 17]byte var x14454 [1 << 17]byte var x14455 [1 << 17]byte var x14456 [1 << 17]byte var x14457 [1 << 17]byte var x14458 [1 << 17]byte var x14459 [1 << 17]byte var x14460 [1 << 17]byte var x14461 [1 << 17]byte var x14462 [1 << 17]byte var x14463 [1 << 17]byte var x14464 [1 << 17]byte var x14465 [1 << 17]byte var x14466 [1 << 17]byte var x14467 [1 << 17]byte var x14468 [1 << 17]byte var x14469 [1 << 17]byte var x14470 [1 << 17]byte var x14471 [1 << 17]byte var x14472 [1 << 17]byte var x14473 [1 << 17]byte var x14474 [1 << 17]byte var x14475 [1 << 17]byte var x14476 [1 << 17]byte var x14477 [1 << 17]byte var x14478 [1 << 17]byte var x14479 [1 << 17]byte var x14480 [1 << 17]byte var x14481 [1 << 17]byte var x14482 [1 << 17]byte var x14483 [1 << 17]byte var x14484 [1 << 17]byte var x14485 [1 << 17]byte var x14486 [1 << 17]byte var x14487 [1 << 17]byte var x14488 [1 << 17]byte var x14489 [1 << 17]byte var x14490 [1 << 17]byte var x14491 [1 << 17]byte var x14492 [1 << 17]byte var x14493 [1 << 17]byte var x14494 [1 << 17]byte var x14495 [1 << 17]byte var x14496 [1 << 17]byte var x14497 [1 << 17]byte var x14498 [1 << 17]byte var x14499 [1 << 17]byte var x14500 [1 << 17]byte var x14501 [1 << 17]byte var x14502 [1 << 17]byte var x14503 [1 << 17]byte var x14504 [1 << 17]byte var x14505 [1 << 17]byte var x14506 [1 << 17]byte var x14507 [1 << 17]byte var x14508 [1 << 17]byte var x14509 [1 << 17]byte var x14510 [1 << 17]byte var x14511 [1 << 17]byte var x14512 [1 << 17]byte var x14513 [1 << 17]byte var x14514 [1 << 17]byte var x14515 [1 << 17]byte var x14516 [1 << 17]byte var x14517 [1 << 17]byte var x14518 [1 << 17]byte var x14519 [1 << 17]byte var x14520 [1 << 17]byte var x14521 [1 << 17]byte var x14522 [1 << 17]byte var x14523 [1 << 17]byte var x14524 [1 << 17]byte var x14525 [1 << 17]byte var x14526 [1 << 17]byte var x14527 [1 << 17]byte var x14528 [1 << 17]byte var x14529 [1 << 17]byte var x14530 [1 << 17]byte var x14531 [1 << 17]byte var x14532 [1 << 17]byte var x14533 [1 << 17]byte var x14534 [1 << 17]byte var x14535 [1 << 17]byte var x14536 [1 << 17]byte var x14537 [1 << 17]byte var x14538 [1 << 17]byte var x14539 [1 << 17]byte var x14540 [1 << 17]byte var x14541 [1 << 17]byte var x14542 [1 << 17]byte var x14543 [1 << 17]byte var x14544 [1 << 17]byte var x14545 [1 << 17]byte var x14546 [1 << 17]byte var x14547 [1 << 17]byte var x14548 [1 << 17]byte var x14549 [1 << 17]byte var x14550 [1 << 17]byte var x14551 [1 << 17]byte var x14552 [1 << 17]byte var x14553 [1 << 17]byte var x14554 [1 << 17]byte var x14555 [1 << 17]byte var x14556 [1 << 17]byte var x14557 [1 << 17]byte var x14558 [1 << 17]byte var x14559 [1 << 17]byte var x14560 [1 << 17]byte var x14561 [1 << 17]byte var x14562 [1 << 17]byte var x14563 [1 << 17]byte var x14564 [1 << 17]byte var x14565 [1 << 17]byte var x14566 [1 << 17]byte var x14567 [1 << 17]byte var x14568 [1 << 17]byte var x14569 [1 << 17]byte var x14570 [1 << 17]byte var x14571 [1 << 17]byte var x14572 [1 << 17]byte var x14573 [1 << 17]byte var x14574 [1 << 17]byte var x14575 [1 << 17]byte var x14576 [1 << 17]byte var x14577 [1 << 17]byte var x14578 [1 << 17]byte var x14579 [1 << 17]byte var x14580 [1 << 17]byte var x14581 [1 << 17]byte var x14582 [1 << 17]byte var x14583 [1 << 17]byte var x14584 [1 << 17]byte var x14585 [1 << 17]byte var x14586 [1 << 17]byte var x14587 [1 << 17]byte var x14588 [1 << 17]byte var x14589 [1 << 17]byte var x14590 [1 << 17]byte var x14591 [1 << 17]byte var x14592 [1 << 17]byte var x14593 [1 << 17]byte var x14594 [1 << 17]byte var x14595 [1 << 17]byte var x14596 [1 << 17]byte var x14597 [1 << 17]byte var x14598 [1 << 17]byte var x14599 [1 << 17]byte var x14600 [1 << 17]byte var x14601 [1 << 17]byte var x14602 [1 << 17]byte var x14603 [1 << 17]byte var x14604 [1 << 17]byte var x14605 [1 << 17]byte var x14606 [1 << 17]byte var x14607 [1 << 17]byte var x14608 [1 << 17]byte var x14609 [1 << 17]byte var x14610 [1 << 17]byte var x14611 [1 << 17]byte var x14612 [1 << 17]byte var x14613 [1 << 17]byte var x14614 [1 << 17]byte var x14615 [1 << 17]byte var x14616 [1 << 17]byte var x14617 [1 << 17]byte var x14618 [1 << 17]byte var x14619 [1 << 17]byte var x14620 [1 << 17]byte var x14621 [1 << 17]byte var x14622 [1 << 17]byte var x14623 [1 << 17]byte var x14624 [1 << 17]byte var x14625 [1 << 17]byte var x14626 [1 << 17]byte var x14627 [1 << 17]byte var x14628 [1 << 17]byte var x14629 [1 << 17]byte var x14630 [1 << 17]byte var x14631 [1 << 17]byte var x14632 [1 << 17]byte var x14633 [1 << 17]byte var x14634 [1 << 17]byte var x14635 [1 << 17]byte var x14636 [1 << 17]byte var x14637 [1 << 17]byte var x14638 [1 << 17]byte var x14639 [1 << 17]byte var x14640 [1 << 17]byte var x14641 [1 << 17]byte var x14642 [1 << 17]byte var x14643 [1 << 17]byte var x14644 [1 << 17]byte var x14645 [1 << 17]byte var x14646 [1 << 17]byte var x14647 [1 << 17]byte var x14648 [1 << 17]byte var x14649 [1 << 17]byte var x14650 [1 << 17]byte var x14651 [1 << 17]byte var x14652 [1 << 17]byte var x14653 [1 << 17]byte var x14654 [1 << 17]byte var x14655 [1 << 17]byte var x14656 [1 << 17]byte var x14657 [1 << 17]byte var x14658 [1 << 17]byte var x14659 [1 << 17]byte var x14660 [1 << 17]byte var x14661 [1 << 17]byte var x14662 [1 << 17]byte var x14663 [1 << 17]byte var x14664 [1 << 17]byte var x14665 [1 << 17]byte var x14666 [1 << 17]byte var x14667 [1 << 17]byte var x14668 [1 << 17]byte var x14669 [1 << 17]byte var x14670 [1 << 17]byte var x14671 [1 << 17]byte var x14672 [1 << 17]byte var x14673 [1 << 17]byte var x14674 [1 << 17]byte var x14675 [1 << 17]byte var x14676 [1 << 17]byte var x14677 [1 << 17]byte var x14678 [1 << 17]byte var x14679 [1 << 17]byte var x14680 [1 << 17]byte var x14681 [1 << 17]byte var x14682 [1 << 17]byte var x14683 [1 << 17]byte var x14684 [1 << 17]byte var x14685 [1 << 17]byte var x14686 [1 << 17]byte var x14687 [1 << 17]byte var x14688 [1 << 17]byte var x14689 [1 << 17]byte var x14690 [1 << 17]byte var x14691 [1 << 17]byte var x14692 [1 << 17]byte var x14693 [1 << 17]byte var x14694 [1 << 17]byte var x14695 [1 << 17]byte var x14696 [1 << 17]byte var x14697 [1 << 17]byte var x14698 [1 << 17]byte var x14699 [1 << 17]byte var x14700 [1 << 17]byte var x14701 [1 << 17]byte var x14702 [1 << 17]byte var x14703 [1 << 17]byte var x14704 [1 << 17]byte var x14705 [1 << 17]byte var x14706 [1 << 17]byte var x14707 [1 << 17]byte var x14708 [1 << 17]byte var x14709 [1 << 17]byte var x14710 [1 << 17]byte var x14711 [1 << 17]byte var x14712 [1 << 17]byte var x14713 [1 << 17]byte var x14714 [1 << 17]byte var x14715 [1 << 17]byte var x14716 [1 << 17]byte var x14717 [1 << 17]byte var x14718 [1 << 17]byte var x14719 [1 << 17]byte var x14720 [1 << 17]byte var x14721 [1 << 17]byte var x14722 [1 << 17]byte var x14723 [1 << 17]byte var x14724 [1 << 17]byte var x14725 [1 << 17]byte var x14726 [1 << 17]byte var x14727 [1 << 17]byte var x14728 [1 << 17]byte var x14729 [1 << 17]byte var x14730 [1 << 17]byte var x14731 [1 << 17]byte var x14732 [1 << 17]byte var x14733 [1 << 17]byte var x14734 [1 << 17]byte var x14735 [1 << 17]byte var x14736 [1 << 17]byte var x14737 [1 << 17]byte var x14738 [1 << 17]byte var x14739 [1 << 17]byte var x14740 [1 << 17]byte var x14741 [1 << 17]byte var x14742 [1 << 17]byte var x14743 [1 << 17]byte var x14744 [1 << 17]byte var x14745 [1 << 17]byte var x14746 [1 << 17]byte var x14747 [1 << 17]byte var x14748 [1 << 17]byte var x14749 [1 << 17]byte var x14750 [1 << 17]byte var x14751 [1 << 17]byte var x14752 [1 << 17]byte var x14753 [1 << 17]byte var x14754 [1 << 17]byte var x14755 [1 << 17]byte var x14756 [1 << 17]byte var x14757 [1 << 17]byte var x14758 [1 << 17]byte var x14759 [1 << 17]byte var x14760 [1 << 17]byte var x14761 [1 << 17]byte var x14762 [1 << 17]byte var x14763 [1 << 17]byte var x14764 [1 << 17]byte var x14765 [1 << 17]byte var x14766 [1 << 17]byte var x14767 [1 << 17]byte var x14768 [1 << 17]byte var x14769 [1 << 17]byte var x14770 [1 << 17]byte var x14771 [1 << 17]byte var x14772 [1 << 17]byte var x14773 [1 << 17]byte var x14774 [1 << 17]byte var x14775 [1 << 17]byte var x14776 [1 << 17]byte var x14777 [1 << 17]byte var x14778 [1 << 17]byte var x14779 [1 << 17]byte var x14780 [1 << 17]byte var x14781 [1 << 17]byte var x14782 [1 << 17]byte var x14783 [1 << 17]byte var x14784 [1 << 17]byte var x14785 [1 << 17]byte var x14786 [1 << 17]byte var x14787 [1 << 17]byte var x14788 [1 << 17]byte var x14789 [1 << 17]byte var x14790 [1 << 17]byte var x14791 [1 << 17]byte var x14792 [1 << 17]byte var x14793 [1 << 17]byte var x14794 [1 << 17]byte var x14795 [1 << 17]byte var x14796 [1 << 17]byte var x14797 [1 << 17]byte var x14798 [1 << 17]byte var x14799 [1 << 17]byte var x14800 [1 << 17]byte var x14801 [1 << 17]byte var x14802 [1 << 17]byte var x14803 [1 << 17]byte var x14804 [1 << 17]byte var x14805 [1 << 17]byte var x14806 [1 << 17]byte var x14807 [1 << 17]byte var x14808 [1 << 17]byte var x14809 [1 << 17]byte var x14810 [1 << 17]byte var x14811 [1 << 17]byte var x14812 [1 << 17]byte var x14813 [1 << 17]byte var x14814 [1 << 17]byte var x14815 [1 << 17]byte var x14816 [1 << 17]byte var x14817 [1 << 17]byte var x14818 [1 << 17]byte var x14819 [1 << 17]byte var x14820 [1 << 17]byte var x14821 [1 << 17]byte var x14822 [1 << 17]byte var x14823 [1 << 17]byte var x14824 [1 << 17]byte var x14825 [1 << 17]byte var x14826 [1 << 17]byte var x14827 [1 << 17]byte var x14828 [1 << 17]byte var x14829 [1 << 17]byte var x14830 [1 << 17]byte var x14831 [1 << 17]byte var x14832 [1 << 17]byte var x14833 [1 << 17]byte var x14834 [1 << 17]byte var x14835 [1 << 17]byte var x14836 [1 << 17]byte var x14837 [1 << 17]byte var x14838 [1 << 17]byte var x14839 [1 << 17]byte var x14840 [1 << 17]byte var x14841 [1 << 17]byte var x14842 [1 << 17]byte var x14843 [1 << 17]byte var x14844 [1 << 17]byte var x14845 [1 << 17]byte var x14846 [1 << 17]byte var x14847 [1 << 17]byte var x14848 [1 << 17]byte var x14849 [1 << 17]byte var x14850 [1 << 17]byte var x14851 [1 << 17]byte var x14852 [1 << 17]byte var x14853 [1 << 17]byte var x14854 [1 << 17]byte var x14855 [1 << 17]byte var x14856 [1 << 17]byte var x14857 [1 << 17]byte var x14858 [1 << 17]byte var x14859 [1 << 17]byte var x14860 [1 << 17]byte var x14861 [1 << 17]byte var x14862 [1 << 17]byte var x14863 [1 << 17]byte var x14864 [1 << 17]byte var x14865 [1 << 17]byte var x14866 [1 << 17]byte var x14867 [1 << 17]byte var x14868 [1 << 17]byte var x14869 [1 << 17]byte var x14870 [1 << 17]byte var x14871 [1 << 17]byte var x14872 [1 << 17]byte var x14873 [1 << 17]byte var x14874 [1 << 17]byte var x14875 [1 << 17]byte var x14876 [1 << 17]byte var x14877 [1 << 17]byte var x14878 [1 << 17]byte var x14879 [1 << 17]byte var x14880 [1 << 17]byte var x14881 [1 << 17]byte var x14882 [1 << 17]byte var x14883 [1 << 17]byte var x14884 [1 << 17]byte var x14885 [1 << 17]byte var x14886 [1 << 17]byte var x14887 [1 << 17]byte var x14888 [1 << 17]byte var x14889 [1 << 17]byte var x14890 [1 << 17]byte var x14891 [1 << 17]byte var x14892 [1 << 17]byte var x14893 [1 << 17]byte var x14894 [1 << 17]byte var x14895 [1 << 17]byte var x14896 [1 << 17]byte var x14897 [1 << 17]byte var x14898 [1 << 17]byte var x14899 [1 << 17]byte var x14900 [1 << 17]byte var x14901 [1 << 17]byte var x14902 [1 << 17]byte var x14903 [1 << 17]byte var x14904 [1 << 17]byte var x14905 [1 << 17]byte var x14906 [1 << 17]byte var x14907 [1 << 17]byte var x14908 [1 << 17]byte var x14909 [1 << 17]byte var x14910 [1 << 17]byte var x14911 [1 << 17]byte var x14912 [1 << 17]byte var x14913 [1 << 17]byte var x14914 [1 << 17]byte var x14915 [1 << 17]byte var x14916 [1 << 17]byte var x14917 [1 << 17]byte var x14918 [1 << 17]byte var x14919 [1 << 17]byte var x14920 [1 << 17]byte var x14921 [1 << 17]byte var x14922 [1 << 17]byte var x14923 [1 << 17]byte var x14924 [1 << 17]byte var x14925 [1 << 17]byte var x14926 [1 << 17]byte var x14927 [1 << 17]byte var x14928 [1 << 17]byte var x14929 [1 << 17]byte var x14930 [1 << 17]byte var x14931 [1 << 17]byte var x14932 [1 << 17]byte var x14933 [1 << 17]byte var x14934 [1 << 17]byte var x14935 [1 << 17]byte var x14936 [1 << 17]byte var x14937 [1 << 17]byte var x14938 [1 << 17]byte var x14939 [1 << 17]byte var x14940 [1 << 17]byte var x14941 [1 << 17]byte var x14942 [1 << 17]byte var x14943 [1 << 17]byte var x14944 [1 << 17]byte var x14945 [1 << 17]byte var x14946 [1 << 17]byte var x14947 [1 << 17]byte var x14948 [1 << 17]byte var x14949 [1 << 17]byte var x14950 [1 << 17]byte var x14951 [1 << 17]byte var x14952 [1 << 17]byte var x14953 [1 << 17]byte var x14954 [1 << 17]byte var x14955 [1 << 17]byte var x14956 [1 << 17]byte var x14957 [1 << 17]byte var x14958 [1 << 17]byte var x14959 [1 << 17]byte var x14960 [1 << 17]byte var x14961 [1 << 17]byte var x14962 [1 << 17]byte var x14963 [1 << 17]byte var x14964 [1 << 17]byte var x14965 [1 << 17]byte var x14966 [1 << 17]byte var x14967 [1 << 17]byte var x14968 [1 << 17]byte var x14969 [1 << 17]byte var x14970 [1 << 17]byte var x14971 [1 << 17]byte var x14972 [1 << 17]byte var x14973 [1 << 17]byte var x14974 [1 << 17]byte var x14975 [1 << 17]byte var x14976 [1 << 17]byte var x14977 [1 << 17]byte var x14978 [1 << 17]byte var x14979 [1 << 17]byte var x14980 [1 << 17]byte var x14981 [1 << 17]byte var x14982 [1 << 17]byte var x14983 [1 << 17]byte var x14984 [1 << 17]byte var x14985 [1 << 17]byte var x14986 [1 << 17]byte var x14987 [1 << 17]byte var x14988 [1 << 17]byte var x14989 [1 << 17]byte var x14990 [1 << 17]byte var x14991 [1 << 17]byte var x14992 [1 << 17]byte var x14993 [1 << 17]byte var x14994 [1 << 17]byte var x14995 [1 << 17]byte var x14996 [1 << 17]byte var x14997 [1 << 17]byte var x14998 [1 << 17]byte var x14999 [1 << 17]byte var x15000 [1 << 17]byte var x15001 [1 << 17]byte var x15002 [1 << 17]byte var x15003 [1 << 17]byte var x15004 [1 << 17]byte var x15005 [1 << 17]byte var x15006 [1 << 17]byte var x15007 [1 << 17]byte var x15008 [1 << 17]byte var x15009 [1 << 17]byte var x15010 [1 << 17]byte var x15011 [1 << 17]byte var x15012 [1 << 17]byte var x15013 [1 << 17]byte var x15014 [1 << 17]byte var x15015 [1 << 17]byte var x15016 [1 << 17]byte var x15017 [1 << 17]byte var x15018 [1 << 17]byte var x15019 [1 << 17]byte var x15020 [1 << 17]byte var x15021 [1 << 17]byte var x15022 [1 << 17]byte var x15023 [1 << 17]byte var x15024 [1 << 17]byte var x15025 [1 << 17]byte var x15026 [1 << 17]byte var x15027 [1 << 17]byte var x15028 [1 << 17]byte var x15029 [1 << 17]byte var x15030 [1 << 17]byte var x15031 [1 << 17]byte var x15032 [1 << 17]byte var x15033 [1 << 17]byte var x15034 [1 << 17]byte var x15035 [1 << 17]byte var x15036 [1 << 17]byte var x15037 [1 << 17]byte var x15038 [1 << 17]byte var x15039 [1 << 17]byte var x15040 [1 << 17]byte var x15041 [1 << 17]byte var x15042 [1 << 17]byte var x15043 [1 << 17]byte var x15044 [1 << 17]byte var x15045 [1 << 17]byte var x15046 [1 << 17]byte var x15047 [1 << 17]byte var x15048 [1 << 17]byte var x15049 [1 << 17]byte var x15050 [1 << 17]byte var x15051 [1 << 17]byte var x15052 [1 << 17]byte var x15053 [1 << 17]byte var x15054 [1 << 17]byte var x15055 [1 << 17]byte var x15056 [1 << 17]byte var x15057 [1 << 17]byte var x15058 [1 << 17]byte var x15059 [1 << 17]byte var x15060 [1 << 17]byte var x15061 [1 << 17]byte var x15062 [1 << 17]byte var x15063 [1 << 17]byte var x15064 [1 << 17]byte var x15065 [1 << 17]byte var x15066 [1 << 17]byte var x15067 [1 << 17]byte var x15068 [1 << 17]byte var x15069 [1 << 17]byte var x15070 [1 << 17]byte var x15071 [1 << 17]byte var x15072 [1 << 17]byte var x15073 [1 << 17]byte var x15074 [1 << 17]byte var x15075 [1 << 17]byte var x15076 [1 << 17]byte var x15077 [1 << 17]byte var x15078 [1 << 17]byte var x15079 [1 << 17]byte var x15080 [1 << 17]byte var x15081 [1 << 17]byte var x15082 [1 << 17]byte var x15083 [1 << 17]byte var x15084 [1 << 17]byte var x15085 [1 << 17]byte var x15086 [1 << 17]byte var x15087 [1 << 17]byte var x15088 [1 << 17]byte var x15089 [1 << 17]byte var x15090 [1 << 17]byte var x15091 [1 << 17]byte var x15092 [1 << 17]byte var x15093 [1 << 17]byte var x15094 [1 << 17]byte var x15095 [1 << 17]byte var x15096 [1 << 17]byte var x15097 [1 << 17]byte var x15098 [1 << 17]byte var x15099 [1 << 17]byte var x15100 [1 << 17]byte var x15101 [1 << 17]byte var x15102 [1 << 17]byte var x15103 [1 << 17]byte var x15104 [1 << 17]byte var x15105 [1 << 17]byte var x15106 [1 << 17]byte var x15107 [1 << 17]byte var x15108 [1 << 17]byte var x15109 [1 << 17]byte var x15110 [1 << 17]byte var x15111 [1 << 17]byte var x15112 [1 << 17]byte var x15113 [1 << 17]byte var x15114 [1 << 17]byte var x15115 [1 << 17]byte var x15116 [1 << 17]byte var x15117 [1 << 17]byte var x15118 [1 << 17]byte var x15119 [1 << 17]byte var x15120 [1 << 17]byte var x15121 [1 << 17]byte var x15122 [1 << 17]byte var x15123 [1 << 17]byte var x15124 [1 << 17]byte var x15125 [1 << 17]byte var x15126 [1 << 17]byte var x15127 [1 << 17]byte var x15128 [1 << 17]byte var x15129 [1 << 17]byte var x15130 [1 << 17]byte var x15131 [1 << 17]byte var x15132 [1 << 17]byte var x15133 [1 << 17]byte var x15134 [1 << 17]byte var x15135 [1 << 17]byte var x15136 [1 << 17]byte var x15137 [1 << 17]byte var x15138 [1 << 17]byte var x15139 [1 << 17]byte var x15140 [1 << 17]byte var x15141 [1 << 17]byte var x15142 [1 << 17]byte var x15143 [1 << 17]byte var x15144 [1 << 17]byte var x15145 [1 << 17]byte var x15146 [1 << 17]byte var x15147 [1 << 17]byte var x15148 [1 << 17]byte var x15149 [1 << 17]byte var x15150 [1 << 17]byte var x15151 [1 << 17]byte var x15152 [1 << 17]byte var x15153 [1 << 17]byte var x15154 [1 << 17]byte var x15155 [1 << 17]byte var x15156 [1 << 17]byte var x15157 [1 << 17]byte var x15158 [1 << 17]byte var x15159 [1 << 17]byte var x15160 [1 << 17]byte var x15161 [1 << 17]byte var x15162 [1 << 17]byte var x15163 [1 << 17]byte var x15164 [1 << 17]byte var x15165 [1 << 17]byte var x15166 [1 << 17]byte var x15167 [1 << 17]byte var x15168 [1 << 17]byte var x15169 [1 << 17]byte var x15170 [1 << 17]byte var x15171 [1 << 17]byte var x15172 [1 << 17]byte var x15173 [1 << 17]byte var x15174 [1 << 17]byte var x15175 [1 << 17]byte var x15176 [1 << 17]byte var x15177 [1 << 17]byte var x15178 [1 << 17]byte var x15179 [1 << 17]byte var x15180 [1 << 17]byte var x15181 [1 << 17]byte var x15182 [1 << 17]byte var x15183 [1 << 17]byte var x15184 [1 << 17]byte var x15185 [1 << 17]byte var x15186 [1 << 17]byte var x15187 [1 << 17]byte var x15188 [1 << 17]byte var x15189 [1 << 17]byte var x15190 [1 << 17]byte var x15191 [1 << 17]byte var x15192 [1 << 17]byte var x15193 [1 << 17]byte var x15194 [1 << 17]byte var x15195 [1 << 17]byte var x15196 [1 << 17]byte var x15197 [1 << 17]byte var x15198 [1 << 17]byte var x15199 [1 << 17]byte var x15200 [1 << 17]byte var x15201 [1 << 17]byte var x15202 [1 << 17]byte var x15203 [1 << 17]byte var x15204 [1 << 17]byte var x15205 [1 << 17]byte var x15206 [1 << 17]byte var x15207 [1 << 17]byte var x15208 [1 << 17]byte var x15209 [1 << 17]byte var x15210 [1 << 17]byte var x15211 [1 << 17]byte var x15212 [1 << 17]byte var x15213 [1 << 17]byte var x15214 [1 << 17]byte var x15215 [1 << 17]byte var x15216 [1 << 17]byte var x15217 [1 << 17]byte var x15218 [1 << 17]byte var x15219 [1 << 17]byte var x15220 [1 << 17]byte var x15221 [1 << 17]byte var x15222 [1 << 17]byte var x15223 [1 << 17]byte var x15224 [1 << 17]byte var x15225 [1 << 17]byte var x15226 [1 << 17]byte var x15227 [1 << 17]byte var x15228 [1 << 17]byte var x15229 [1 << 17]byte var x15230 [1 << 17]byte var x15231 [1 << 17]byte var x15232 [1 << 17]byte var x15233 [1 << 17]byte var x15234 [1 << 17]byte var x15235 [1 << 17]byte var x15236 [1 << 17]byte var x15237 [1 << 17]byte var x15238 [1 << 17]byte var x15239 [1 << 17]byte var x15240 [1 << 17]byte var x15241 [1 << 17]byte var x15242 [1 << 17]byte var x15243 [1 << 17]byte var x15244 [1 << 17]byte var x15245 [1 << 17]byte var x15246 [1 << 17]byte var x15247 [1 << 17]byte var x15248 [1 << 17]byte var x15249 [1 << 17]byte var x15250 [1 << 17]byte var x15251 [1 << 17]byte var x15252 [1 << 17]byte var x15253 [1 << 17]byte var x15254 [1 << 17]byte var x15255 [1 << 17]byte var x15256 [1 << 17]byte var x15257 [1 << 17]byte var x15258 [1 << 17]byte var x15259 [1 << 17]byte var x15260 [1 << 17]byte var x15261 [1 << 17]byte var x15262 [1 << 17]byte var x15263 [1 << 17]byte var x15264 [1 << 17]byte var x15265 [1 << 17]byte var x15266 [1 << 17]byte var x15267 [1 << 17]byte var x15268 [1 << 17]byte var x15269 [1 << 17]byte var x15270 [1 << 17]byte var x15271 [1 << 17]byte var x15272 [1 << 17]byte var x15273 [1 << 17]byte var x15274 [1 << 17]byte var x15275 [1 << 17]byte var x15276 [1 << 17]byte var x15277 [1 << 17]byte var x15278 [1 << 17]byte var x15279 [1 << 17]byte var x15280 [1 << 17]byte var x15281 [1 << 17]byte var x15282 [1 << 17]byte var x15283 [1 << 17]byte var x15284 [1 << 17]byte var x15285 [1 << 17]byte var x15286 [1 << 17]byte var x15287 [1 << 17]byte var x15288 [1 << 17]byte var x15289 [1 << 17]byte var x15290 [1 << 17]byte var x15291 [1 << 17]byte var x15292 [1 << 17]byte var x15293 [1 << 17]byte var x15294 [1 << 17]byte var x15295 [1 << 17]byte var x15296 [1 << 17]byte var x15297 [1 << 17]byte var x15298 [1 << 17]byte var x15299 [1 << 17]byte var x15300 [1 << 17]byte var x15301 [1 << 17]byte var x15302 [1 << 17]byte var x15303 [1 << 17]byte var x15304 [1 << 17]byte var x15305 [1 << 17]byte var x15306 [1 << 17]byte var x15307 [1 << 17]byte var x15308 [1 << 17]byte var x15309 [1 << 17]byte var x15310 [1 << 17]byte var x15311 [1 << 17]byte var x15312 [1 << 17]byte var x15313 [1 << 17]byte var x15314 [1 << 17]byte var x15315 [1 << 17]byte var x15316 [1 << 17]byte var x15317 [1 << 17]byte var x15318 [1 << 17]byte var x15319 [1 << 17]byte var x15320 [1 << 17]byte var x15321 [1 << 17]byte var x15322 [1 << 17]byte var x15323 [1 << 17]byte var x15324 [1 << 17]byte var x15325 [1 << 17]byte var x15326 [1 << 17]byte var x15327 [1 << 17]byte var x15328 [1 << 17]byte var x15329 [1 << 17]byte var x15330 [1 << 17]byte var x15331 [1 << 17]byte var x15332 [1 << 17]byte var x15333 [1 << 17]byte var x15334 [1 << 17]byte var x15335 [1 << 17]byte var x15336 [1 << 17]byte var x15337 [1 << 17]byte var x15338 [1 << 17]byte var x15339 [1 << 17]byte var x15340 [1 << 17]byte var x15341 [1 << 17]byte var x15342 [1 << 17]byte var x15343 [1 << 17]byte var x15344 [1 << 17]byte var x15345 [1 << 17]byte var x15346 [1 << 17]byte var x15347 [1 << 17]byte var x15348 [1 << 17]byte var x15349 [1 << 17]byte var x15350 [1 << 17]byte var x15351 [1 << 17]byte var x15352 [1 << 17]byte var x15353 [1 << 17]byte var x15354 [1 << 17]byte var x15355 [1 << 17]byte var x15356 [1 << 17]byte var x15357 [1 << 17]byte var x15358 [1 << 17]byte var x15359 [1 << 17]byte var x15360 [1 << 17]byte var x15361 [1 << 17]byte var x15362 [1 << 17]byte var x15363 [1 << 17]byte var x15364 [1 << 17]byte var x15365 [1 << 17]byte var x15366 [1 << 17]byte var x15367 [1 << 17]byte var x15368 [1 << 17]byte var x15369 [1 << 17]byte var x15370 [1 << 17]byte var x15371 [1 << 17]byte var x15372 [1 << 17]byte var x15373 [1 << 17]byte var x15374 [1 << 17]byte var x15375 [1 << 17]byte var x15376 [1 << 17]byte var x15377 [1 << 17]byte var x15378 [1 << 17]byte var x15379 [1 << 17]byte var x15380 [1 << 17]byte var x15381 [1 << 17]byte var x15382 [1 << 17]byte var x15383 [1 << 17]byte var x15384 [1 << 17]byte var x15385 [1 << 17]byte var x15386 [1 << 17]byte var x15387 [1 << 17]byte var x15388 [1 << 17]byte var x15389 [1 << 17]byte var x15390 [1 << 17]byte var x15391 [1 << 17]byte var x15392 [1 << 17]byte var x15393 [1 << 17]byte var x15394 [1 << 17]byte var x15395 [1 << 17]byte var x15396 [1 << 17]byte var x15397 [1 << 17]byte var x15398 [1 << 17]byte var x15399 [1 << 17]byte var x15400 [1 << 17]byte var x15401 [1 << 17]byte var x15402 [1 << 17]byte var x15403 [1 << 17]byte var x15404 [1 << 17]byte var x15405 [1 << 17]byte var x15406 [1 << 17]byte var x15407 [1 << 17]byte var x15408 [1 << 17]byte var x15409 [1 << 17]byte var x15410 [1 << 17]byte var x15411 [1 << 17]byte var x15412 [1 << 17]byte var x15413 [1 << 17]byte var x15414 [1 << 17]byte var x15415 [1 << 17]byte var x15416 [1 << 17]byte var x15417 [1 << 17]byte var x15418 [1 << 17]byte var x15419 [1 << 17]byte var x15420 [1 << 17]byte var x15421 [1 << 17]byte var x15422 [1 << 17]byte var x15423 [1 << 17]byte var x15424 [1 << 17]byte var x15425 [1 << 17]byte var x15426 [1 << 17]byte var x15427 [1 << 17]byte var x15428 [1 << 17]byte var x15429 [1 << 17]byte var x15430 [1 << 17]byte var x15431 [1 << 17]byte var x15432 [1 << 17]byte var x15433 [1 << 17]byte var x15434 [1 << 17]byte var x15435 [1 << 17]byte var x15436 [1 << 17]byte var x15437 [1 << 17]byte var x15438 [1 << 17]byte var x15439 [1 << 17]byte var x15440 [1 << 17]byte var x15441 [1 << 17]byte var x15442 [1 << 17]byte var x15443 [1 << 17]byte var x15444 [1 << 17]byte var x15445 [1 << 17]byte var x15446 [1 << 17]byte var x15447 [1 << 17]byte var x15448 [1 << 17]byte var x15449 [1 << 17]byte var x15450 [1 << 17]byte var x15451 [1 << 17]byte var x15452 [1 << 17]byte var x15453 [1 << 17]byte var x15454 [1 << 17]byte var x15455 [1 << 17]byte var x15456 [1 << 17]byte var x15457 [1 << 17]byte var x15458 [1 << 17]byte var x15459 [1 << 17]byte var x15460 [1 << 17]byte var x15461 [1 << 17]byte var x15462 [1 << 17]byte var x15463 [1 << 17]byte var x15464 [1 << 17]byte var x15465 [1 << 17]byte var x15466 [1 << 17]byte var x15467 [1 << 17]byte var x15468 [1 << 17]byte var x15469 [1 << 17]byte var x15470 [1 << 17]byte var x15471 [1 << 17]byte var x15472 [1 << 17]byte var x15473 [1 << 17]byte var x15474 [1 << 17]byte var x15475 [1 << 17]byte var x15476 [1 << 17]byte var x15477 [1 << 17]byte var x15478 [1 << 17]byte var x15479 [1 << 17]byte var x15480 [1 << 17]byte var x15481 [1 << 17]byte var x15482 [1 << 17]byte var x15483 [1 << 17]byte var x15484 [1 << 17]byte var x15485 [1 << 17]byte var x15486 [1 << 17]byte var x15487 [1 << 17]byte var x15488 [1 << 17]byte var x15489 [1 << 17]byte var x15490 [1 << 17]byte var x15491 [1 << 17]byte var x15492 [1 << 17]byte var x15493 [1 << 17]byte var x15494 [1 << 17]byte var x15495 [1 << 17]byte var x15496 [1 << 17]byte var x15497 [1 << 17]byte var x15498 [1 << 17]byte var x15499 [1 << 17]byte var x15500 [1 << 17]byte var x15501 [1 << 17]byte var x15502 [1 << 17]byte var x15503 [1 << 17]byte var x15504 [1 << 17]byte var x15505 [1 << 17]byte var x15506 [1 << 17]byte var x15507 [1 << 17]byte var x15508 [1 << 17]byte var x15509 [1 << 17]byte var x15510 [1 << 17]byte var x15511 [1 << 17]byte var x15512 [1 << 17]byte var x15513 [1 << 17]byte var x15514 [1 << 17]byte var x15515 [1 << 17]byte var x15516 [1 << 17]byte var x15517 [1 << 17]byte var x15518 [1 << 17]byte var x15519 [1 << 17]byte var x15520 [1 << 17]byte var x15521 [1 << 17]byte var x15522 [1 << 17]byte var x15523 [1 << 17]byte var x15524 [1 << 17]byte var x15525 [1 << 17]byte var x15526 [1 << 17]byte var x15527 [1 << 17]byte var x15528 [1 << 17]byte var x15529 [1 << 17]byte var x15530 [1 << 17]byte var x15531 [1 << 17]byte var x15532 [1 << 17]byte var x15533 [1 << 17]byte var x15534 [1 << 17]byte var x15535 [1 << 17]byte var x15536 [1 << 17]byte var x15537 [1 << 17]byte var x15538 [1 << 17]byte var x15539 [1 << 17]byte var x15540 [1 << 17]byte var x15541 [1 << 17]byte var x15542 [1 << 17]byte var x15543 [1 << 17]byte var x15544 [1 << 17]byte var x15545 [1 << 17]byte var x15546 [1 << 17]byte var x15547 [1 << 17]byte var x15548 [1 << 17]byte var x15549 [1 << 17]byte var x15550 [1 << 17]byte var x15551 [1 << 17]byte var x15552 [1 << 17]byte var x15553 [1 << 17]byte var x15554 [1 << 17]byte var x15555 [1 << 17]byte var x15556 [1 << 17]byte var x15557 [1 << 17]byte var x15558 [1 << 17]byte var x15559 [1 << 17]byte var x15560 [1 << 17]byte var x15561 [1 << 17]byte var x15562 [1 << 17]byte var x15563 [1 << 17]byte var x15564 [1 << 17]byte var x15565 [1 << 17]byte var x15566 [1 << 17]byte var x15567 [1 << 17]byte var x15568 [1 << 17]byte var x15569 [1 << 17]byte var x15570 [1 << 17]byte var x15571 [1 << 17]byte var x15572 [1 << 17]byte var x15573 [1 << 17]byte var x15574 [1 << 17]byte var x15575 [1 << 17]byte var x15576 [1 << 17]byte var x15577 [1 << 17]byte var x15578 [1 << 17]byte var x15579 [1 << 17]byte var x15580 [1 << 17]byte var x15581 [1 << 17]byte var x15582 [1 << 17]byte var x15583 [1 << 17]byte var x15584 [1 << 17]byte var x15585 [1 << 17]byte var x15586 [1 << 17]byte var x15587 [1 << 17]byte var x15588 [1 << 17]byte var x15589 [1 << 17]byte var x15590 [1 << 17]byte var x15591 [1 << 17]byte var x15592 [1 << 17]byte var x15593 [1 << 17]byte var x15594 [1 << 17]byte var x15595 [1 << 17]byte var x15596 [1 << 17]byte var x15597 [1 << 17]byte var x15598 [1 << 17]byte var x15599 [1 << 17]byte var x15600 [1 << 17]byte var x15601 [1 << 17]byte var x15602 [1 << 17]byte var x15603 [1 << 17]byte var x15604 [1 << 17]byte var x15605 [1 << 17]byte var x15606 [1 << 17]byte var x15607 [1 << 17]byte var x15608 [1 << 17]byte var x15609 [1 << 17]byte var x15610 [1 << 17]byte var x15611 [1 << 17]byte var x15612 [1 << 17]byte var x15613 [1 << 17]byte var x15614 [1 << 17]byte var x15615 [1 << 17]byte var x15616 [1 << 17]byte var x15617 [1 << 17]byte var x15618 [1 << 17]byte var x15619 [1 << 17]byte var x15620 [1 << 17]byte var x15621 [1 << 17]byte var x15622 [1 << 17]byte var x15623 [1 << 17]byte var x15624 [1 << 17]byte var x15625 [1 << 17]byte var x15626 [1 << 17]byte var x15627 [1 << 17]byte var x15628 [1 << 17]byte var x15629 [1 << 17]byte var x15630 [1 << 17]byte var x15631 [1 << 17]byte var x15632 [1 << 17]byte var x15633 [1 << 17]byte var x15634 [1 << 17]byte var x15635 [1 << 17]byte var x15636 [1 << 17]byte var x15637 [1 << 17]byte var x15638 [1 << 17]byte var x15639 [1 << 17]byte var x15640 [1 << 17]byte var x15641 [1 << 17]byte var x15642 [1 << 17]byte var x15643 [1 << 17]byte var x15644 [1 << 17]byte var x15645 [1 << 17]byte var x15646 [1 << 17]byte var x15647 [1 << 17]byte var x15648 [1 << 17]byte var x15649 [1 << 17]byte var x15650 [1 << 17]byte var x15651 [1 << 17]byte var x15652 [1 << 17]byte var x15653 [1 << 17]byte var x15654 [1 << 17]byte var x15655 [1 << 17]byte var x15656 [1 << 17]byte var x15657 [1 << 17]byte var x15658 [1 << 17]byte var x15659 [1 << 17]byte var x15660 [1 << 17]byte var x15661 [1 << 17]byte var x15662 [1 << 17]byte var x15663 [1 << 17]byte var x15664 [1 << 17]byte var x15665 [1 << 17]byte var x15666 [1 << 17]byte var x15667 [1 << 17]byte var x15668 [1 << 17]byte var x15669 [1 << 17]byte var x15670 [1 << 17]byte var x15671 [1 << 17]byte var x15672 [1 << 17]byte var x15673 [1 << 17]byte var x15674 [1 << 17]byte var x15675 [1 << 17]byte var x15676 [1 << 17]byte var x15677 [1 << 17]byte var x15678 [1 << 17]byte var x15679 [1 << 17]byte var x15680 [1 << 17]byte var x15681 [1 << 17]byte var x15682 [1 << 17]byte var x15683 [1 << 17]byte var x15684 [1 << 17]byte var x15685 [1 << 17]byte var x15686 [1 << 17]byte var x15687 [1 << 17]byte var x15688 [1 << 17]byte var x15689 [1 << 17]byte var x15690 [1 << 17]byte var x15691 [1 << 17]byte var x15692 [1 << 17]byte var x15693 [1 << 17]byte var x15694 [1 << 17]byte var x15695 [1 << 17]byte var x15696 [1 << 17]byte var x15697 [1 << 17]byte var x15698 [1 << 17]byte var x15699 [1 << 17]byte var x15700 [1 << 17]byte var x15701 [1 << 17]byte var x15702 [1 << 17]byte var x15703 [1 << 17]byte var x15704 [1 << 17]byte var x15705 [1 << 17]byte var x15706 [1 << 17]byte var x15707 [1 << 17]byte var x15708 [1 << 17]byte var x15709 [1 << 17]byte var x15710 [1 << 17]byte var x15711 [1 << 17]byte var x15712 [1 << 17]byte var x15713 [1 << 17]byte var x15714 [1 << 17]byte var x15715 [1 << 17]byte var x15716 [1 << 17]byte var x15717 [1 << 17]byte var x15718 [1 << 17]byte var x15719 [1 << 17]byte var x15720 [1 << 17]byte var x15721 [1 << 17]byte var x15722 [1 << 17]byte var x15723 [1 << 17]byte var x15724 [1 << 17]byte var x15725 [1 << 17]byte var x15726 [1 << 17]byte var x15727 [1 << 17]byte var x15728 [1 << 17]byte var x15729 [1 << 17]byte var x15730 [1 << 17]byte var x15731 [1 << 17]byte var x15732 [1 << 17]byte var x15733 [1 << 17]byte var x15734 [1 << 17]byte var x15735 [1 << 17]byte var x15736 [1 << 17]byte var x15737 [1 << 17]byte var x15738 [1 << 17]byte var x15739 [1 << 17]byte var x15740 [1 << 17]byte var x15741 [1 << 17]byte var x15742 [1 << 17]byte var x15743 [1 << 17]byte var x15744 [1 << 17]byte var x15745 [1 << 17]byte var x15746 [1 << 17]byte var x15747 [1 << 17]byte var x15748 [1 << 17]byte var x15749 [1 << 17]byte var x15750 [1 << 17]byte var x15751 [1 << 17]byte var x15752 [1 << 17]byte var x15753 [1 << 17]byte var x15754 [1 << 17]byte var x15755 [1 << 17]byte var x15756 [1 << 17]byte var x15757 [1 << 17]byte var x15758 [1 << 17]byte var x15759 [1 << 17]byte var x15760 [1 << 17]byte var x15761 [1 << 17]byte var x15762 [1 << 17]byte var x15763 [1 << 17]byte var x15764 [1 << 17]byte var x15765 [1 << 17]byte var x15766 [1 << 17]byte var x15767 [1 << 17]byte var x15768 [1 << 17]byte var x15769 [1 << 17]byte var x15770 [1 << 17]byte var x15771 [1 << 17]byte var x15772 [1 << 17]byte var x15773 [1 << 17]byte var x15774 [1 << 17]byte var x15775 [1 << 17]byte var x15776 [1 << 17]byte var x15777 [1 << 17]byte var x15778 [1 << 17]byte var x15779 [1 << 17]byte var x15780 [1 << 17]byte var x15781 [1 << 17]byte var x15782 [1 << 17]byte var x15783 [1 << 17]byte var x15784 [1 << 17]byte var x15785 [1 << 17]byte var x15786 [1 << 17]byte var x15787 [1 << 17]byte var x15788 [1 << 17]byte var x15789 [1 << 17]byte var x15790 [1 << 17]byte var x15791 [1 << 17]byte var x15792 [1 << 17]byte var x15793 [1 << 17]byte var x15794 [1 << 17]byte var x15795 [1 << 17]byte var x15796 [1 << 17]byte var x15797 [1 << 17]byte var x15798 [1 << 17]byte var x15799 [1 << 17]byte var x15800 [1 << 17]byte var x15801 [1 << 17]byte var x15802 [1 << 17]byte var x15803 [1 << 17]byte var x15804 [1 << 17]byte var x15805 [1 << 17]byte var x15806 [1 << 17]byte var x15807 [1 << 17]byte var x15808 [1 << 17]byte var x15809 [1 << 17]byte var x15810 [1 << 17]byte var x15811 [1 << 17]byte var x15812 [1 << 17]byte var x15813 [1 << 17]byte var x15814 [1 << 17]byte var x15815 [1 << 17]byte var x15816 [1 << 17]byte var x15817 [1 << 17]byte var x15818 [1 << 17]byte var x15819 [1 << 17]byte var x15820 [1 << 17]byte var x15821 [1 << 17]byte var x15822 [1 << 17]byte var x15823 [1 << 17]byte var x15824 [1 << 17]byte var x15825 [1 << 17]byte var x15826 [1 << 17]byte var x15827 [1 << 17]byte var x15828 [1 << 17]byte var x15829 [1 << 17]byte var x15830 [1 << 17]byte var x15831 [1 << 17]byte var x15832 [1 << 17]byte var x15833 [1 << 17]byte var x15834 [1 << 17]byte var x15835 [1 << 17]byte var x15836 [1 << 17]byte var x15837 [1 << 17]byte var x15838 [1 << 17]byte var x15839 [1 << 17]byte var x15840 [1 << 17]byte var x15841 [1 << 17]byte var x15842 [1 << 17]byte var x15843 [1 << 17]byte var x15844 [1 << 17]byte var x15845 [1 << 17]byte var x15846 [1 << 17]byte var x15847 [1 << 17]byte var x15848 [1 << 17]byte var x15849 [1 << 17]byte var x15850 [1 << 17]byte var x15851 [1 << 17]byte var x15852 [1 << 17]byte var x15853 [1 << 17]byte var x15854 [1 << 17]byte var x15855 [1 << 17]byte var x15856 [1 << 17]byte var x15857 [1 << 17]byte var x15858 [1 << 17]byte var x15859 [1 << 17]byte var x15860 [1 << 17]byte var x15861 [1 << 17]byte var x15862 [1 << 17]byte var x15863 [1 << 17]byte var x15864 [1 << 17]byte var x15865 [1 << 17]byte var x15866 [1 << 17]byte var x15867 [1 << 17]byte var x15868 [1 << 17]byte var x15869 [1 << 17]byte var x15870 [1 << 17]byte var x15871 [1 << 17]byte var x15872 [1 << 17]byte var x15873 [1 << 17]byte var x15874 [1 << 17]byte var x15875 [1 << 17]byte var x15876 [1 << 17]byte var x15877 [1 << 17]byte var x15878 [1 << 17]byte var x15879 [1 << 17]byte var x15880 [1 << 17]byte var x15881 [1 << 17]byte var x15882 [1 << 17]byte var x15883 [1 << 17]byte var x15884 [1 << 17]byte var x15885 [1 << 17]byte var x15886 [1 << 17]byte var x15887 [1 << 17]byte var x15888 [1 << 17]byte var x15889 [1 << 17]byte var x15890 [1 << 17]byte var x15891 [1 << 17]byte var x15892 [1 << 17]byte var x15893 [1 << 17]byte var x15894 [1 << 17]byte var x15895 [1 << 17]byte var x15896 [1 << 17]byte var x15897 [1 << 17]byte var x15898 [1 << 17]byte var x15899 [1 << 17]byte var x15900 [1 << 17]byte var x15901 [1 << 17]byte var x15902 [1 << 17]byte var x15903 [1 << 17]byte var x15904 [1 << 17]byte var x15905 [1 << 17]byte var x15906 [1 << 17]byte var x15907 [1 << 17]byte var x15908 [1 << 17]byte var x15909 [1 << 17]byte var x15910 [1 << 17]byte var x15911 [1 << 17]byte var x15912 [1 << 17]byte var x15913 [1 << 17]byte var x15914 [1 << 17]byte var x15915 [1 << 17]byte var x15916 [1 << 17]byte var x15917 [1 << 17]byte var x15918 [1 << 17]byte var x15919 [1 << 17]byte var x15920 [1 << 17]byte var x15921 [1 << 17]byte var x15922 [1 << 17]byte var x15923 [1 << 17]byte var x15924 [1 << 17]byte var x15925 [1 << 17]byte var x15926 [1 << 17]byte var x15927 [1 << 17]byte var x15928 [1 << 17]byte var x15929 [1 << 17]byte var x15930 [1 << 17]byte var x15931 [1 << 17]byte var x15932 [1 << 17]byte var x15933 [1 << 17]byte var x15934 [1 << 17]byte var x15935 [1 << 17]byte var x15936 [1 << 17]byte var x15937 [1 << 17]byte var x15938 [1 << 17]byte var x15939 [1 << 17]byte var x15940 [1 << 17]byte var x15941 [1 << 17]byte var x15942 [1 << 17]byte var x15943 [1 << 17]byte var x15944 [1 << 17]byte var x15945 [1 << 17]byte var x15946 [1 << 17]byte var x15947 [1 << 17]byte var x15948 [1 << 17]byte var x15949 [1 << 17]byte var x15950 [1 << 17]byte var x15951 [1 << 17]byte var x15952 [1 << 17]byte var x15953 [1 << 17]byte var x15954 [1 << 17]byte var x15955 [1 << 17]byte var x15956 [1 << 17]byte var x15957 [1 << 17]byte var x15958 [1 << 17]byte var x15959 [1 << 17]byte var x15960 [1 << 17]byte var x15961 [1 << 17]byte var x15962 [1 << 17]byte var x15963 [1 << 17]byte var x15964 [1 << 17]byte var x15965 [1 << 17]byte var x15966 [1 << 17]byte var x15967 [1 << 17]byte var x15968 [1 << 17]byte var x15969 [1 << 17]byte var x15970 [1 << 17]byte var x15971 [1 << 17]byte var x15972 [1 << 17]byte var x15973 [1 << 17]byte var x15974 [1 << 17]byte var x15975 [1 << 17]byte var x15976 [1 << 17]byte var x15977 [1 << 17]byte var x15978 [1 << 17]byte var x15979 [1 << 17]byte var x15980 [1 << 17]byte var x15981 [1 << 17]byte var x15982 [1 << 17]byte var x15983 [1 << 17]byte var x15984 [1 << 17]byte var x15985 [1 << 17]byte var x15986 [1 << 17]byte var x15987 [1 << 17]byte var x15988 [1 << 17]byte var x15989 [1 << 17]byte var x15990 [1 << 17]byte var x15991 [1 << 17]byte var x15992 [1 << 17]byte var x15993 [1 << 17]byte var x15994 [1 << 17]byte var x15995 [1 << 17]byte var x15996 [1 << 17]byte var x15997 [1 << 17]byte var x15998 [1 << 17]byte var x15999 [1 << 17]byte var x16000 [1 << 17]byte var x16001 [1 << 17]byte var x16002 [1 << 17]byte var x16003 [1 << 17]byte var x16004 [1 << 17]byte var x16005 [1 << 17]byte var x16006 [1 << 17]byte var x16007 [1 << 17]byte var x16008 [1 << 17]byte var x16009 [1 << 17]byte var x16010 [1 << 17]byte var x16011 [1 << 17]byte var x16012 [1 << 17]byte var x16013 [1 << 17]byte var x16014 [1 << 17]byte var x16015 [1 << 17]byte var x16016 [1 << 17]byte var x16017 [1 << 17]byte var x16018 [1 << 17]byte var x16019 [1 << 17]byte var x16020 [1 << 17]byte var x16021 [1 << 17]byte var x16022 [1 << 17]byte var x16023 [1 << 17]byte var x16024 [1 << 17]byte var x16025 [1 << 17]byte var x16026 [1 << 17]byte var x16027 [1 << 17]byte var x16028 [1 << 17]byte var x16029 [1 << 17]byte var x16030 [1 << 17]byte var x16031 [1 << 17]byte var x16032 [1 << 17]byte var x16033 [1 << 17]byte var x16034 [1 << 17]byte var x16035 [1 << 17]byte var x16036 [1 << 17]byte var x16037 [1 << 17]byte var x16038 [1 << 17]byte var x16039 [1 << 17]byte var x16040 [1 << 17]byte var x16041 [1 << 17]byte var x16042 [1 << 17]byte var x16043 [1 << 17]byte var x16044 [1 << 17]byte var x16045 [1 << 17]byte var x16046 [1 << 17]byte var x16047 [1 << 17]byte var x16048 [1 << 17]byte var x16049 [1 << 17]byte var x16050 [1 << 17]byte var x16051 [1 << 17]byte var x16052 [1 << 17]byte var x16053 [1 << 17]byte var x16054 [1 << 17]byte var x16055 [1 << 17]byte var x16056 [1 << 17]byte var x16057 [1 << 17]byte var x16058 [1 << 17]byte var x16059 [1 << 17]byte var x16060 [1 << 17]byte var x16061 [1 << 17]byte var x16062 [1 << 17]byte var x16063 [1 << 17]byte var x16064 [1 << 17]byte var x16065 [1 << 17]byte var x16066 [1 << 17]byte var x16067 [1 << 17]byte var x16068 [1 << 17]byte var x16069 [1 << 17]byte var x16070 [1 << 17]byte var x16071 [1 << 17]byte var x16072 [1 << 17]byte var x16073 [1 << 17]byte var x16074 [1 << 17]byte var x16075 [1 << 17]byte var x16076 [1 << 17]byte var x16077 [1 << 17]byte var x16078 [1 << 17]byte var x16079 [1 << 17]byte var x16080 [1 << 17]byte var x16081 [1 << 17]byte var x16082 [1 << 17]byte var x16083 [1 << 17]byte var x16084 [1 << 17]byte var x16085 [1 << 17]byte var x16086 [1 << 17]byte var x16087 [1 << 17]byte var x16088 [1 << 17]byte var x16089 [1 << 17]byte var x16090 [1 << 17]byte var x16091 [1 << 17]byte var x16092 [1 << 17]byte var x16093 [1 << 17]byte var x16094 [1 << 17]byte var x16095 [1 << 17]byte var x16096 [1 << 17]byte var x16097 [1 << 17]byte var x16098 [1 << 17]byte var x16099 [1 << 17]byte var x16100 [1 << 17]byte var x16101 [1 << 17]byte var x16102 [1 << 17]byte var x16103 [1 << 17]byte var x16104 [1 << 17]byte var x16105 [1 << 17]byte var x16106 [1 << 17]byte var x16107 [1 << 17]byte var x16108 [1 << 17]byte var x16109 [1 << 17]byte var x16110 [1 << 17]byte var x16111 [1 << 17]byte var x16112 [1 << 17]byte var x16113 [1 << 17]byte var x16114 [1 << 17]byte var x16115 [1 << 17]byte var x16116 [1 << 17]byte var x16117 [1 << 17]byte var x16118 [1 << 17]byte var x16119 [1 << 17]byte var x16120 [1 << 17]byte var x16121 [1 << 17]byte var x16122 [1 << 17]byte var x16123 [1 << 17]byte var x16124 [1 << 17]byte var x16125 [1 << 17]byte var x16126 [1 << 17]byte var x16127 [1 << 17]byte var x16128 [1 << 17]byte var x16129 [1 << 17]byte var x16130 [1 << 17]byte var x16131 [1 << 17]byte var x16132 [1 << 17]byte var x16133 [1 << 17]byte var x16134 [1 << 17]byte var x16135 [1 << 17]byte var x16136 [1 << 17]byte var x16137 [1 << 17]byte var x16138 [1 << 17]byte var x16139 [1 << 17]byte var x16140 [1 << 17]byte var x16141 [1 << 17]byte var x16142 [1 << 17]byte var x16143 [1 << 17]byte var x16144 [1 << 17]byte var x16145 [1 << 17]byte var x16146 [1 << 17]byte var x16147 [1 << 17]byte var x16148 [1 << 17]byte var x16149 [1 << 17]byte var x16150 [1 << 17]byte var x16151 [1 << 17]byte var x16152 [1 << 17]byte var x16153 [1 << 17]byte var x16154 [1 << 17]byte var x16155 [1 << 17]byte var x16156 [1 << 17]byte var x16157 [1 << 17]byte var x16158 [1 << 17]byte var x16159 [1 << 17]byte var x16160 [1 << 17]byte var x16161 [1 << 17]byte var x16162 [1 << 17]byte var x16163 [1 << 17]byte var x16164 [1 << 17]byte var x16165 [1 << 17]byte var x16166 [1 << 17]byte var x16167 [1 << 17]byte var x16168 [1 << 17]byte var x16169 [1 << 17]byte var x16170 [1 << 17]byte var x16171 [1 << 17]byte var x16172 [1 << 17]byte var x16173 [1 << 17]byte var x16174 [1 << 17]byte var x16175 [1 << 17]byte var x16176 [1 << 17]byte var x16177 [1 << 17]byte var x16178 [1 << 17]byte var x16179 [1 << 17]byte var x16180 [1 << 17]byte var x16181 [1 << 17]byte var x16182 [1 << 17]byte var x16183 [1 << 17]byte var x16184 [1 << 17]byte var x16185 [1 << 17]byte var x16186 [1 << 17]byte var x16187 [1 << 17]byte var x16188 [1 << 17]byte var x16189 [1 << 17]byte var x16190 [1 << 17]byte var x16191 [1 << 17]byte var x16192 [1 << 17]byte var x16193 [1 << 17]byte var x16194 [1 << 17]byte var x16195 [1 << 17]byte var x16196 [1 << 17]byte var x16197 [1 << 17]byte var x16198 [1 << 17]byte var x16199 [1 << 17]byte var x16200 [1 << 17]byte var x16201 [1 << 17]byte var x16202 [1 << 17]byte var x16203 [1 << 17]byte var x16204 [1 << 17]byte var x16205 [1 << 17]byte var x16206 [1 << 17]byte var x16207 [1 << 17]byte var x16208 [1 << 17]byte var x16209 [1 << 17]byte var x16210 [1 << 17]byte var x16211 [1 << 17]byte var x16212 [1 << 17]byte var x16213 [1 << 17]byte var x16214 [1 << 17]byte var x16215 [1 << 17]byte var x16216 [1 << 17]byte var x16217 [1 << 17]byte var x16218 [1 << 17]byte var x16219 [1 << 17]byte var x16220 [1 << 17]byte var x16221 [1 << 17]byte var x16222 [1 << 17]byte var x16223 [1 << 17]byte var x16224 [1 << 17]byte var x16225 [1 << 17]byte var x16226 [1 << 17]byte var x16227 [1 << 17]byte var x16228 [1 << 17]byte var x16229 [1 << 17]byte var x16230 [1 << 17]byte var x16231 [1 << 17]byte var x16232 [1 << 17]byte var x16233 [1 << 17]byte var x16234 [1 << 17]byte var x16235 [1 << 17]byte var x16236 [1 << 17]byte var x16237 [1 << 17]byte var x16238 [1 << 17]byte var x16239 [1 << 17]byte var x16240 [1 << 17]byte var x16241 [1 << 17]byte var x16242 [1 << 17]byte var x16243 [1 << 17]byte var x16244 [1 << 17]byte var x16245 [1 << 17]byte var x16246 [1 << 17]byte var x16247 [1 << 17]byte var x16248 [1 << 17]byte var x16249 [1 << 17]byte var x16250 [1 << 17]byte var x16251 [1 << 17]byte var x16252 [1 << 17]byte var x16253 [1 << 17]byte var x16254 [1 << 17]byte var x16255 [1 << 17]byte var x16256 [1 << 17]byte var x16257 [1 << 17]byte var x16258 [1 << 17]byte var x16259 [1 << 17]byte var x16260 [1 << 17]byte var x16261 [1 << 17]byte var x16262 [1 << 17]byte var x16263 [1 << 17]byte var x16264 [1 << 17]byte var x16265 [1 << 17]byte var x16266 [1 << 17]byte var x16267 [1 << 17]byte var x16268 [1 << 17]byte var x16269 [1 << 17]byte var x16270 [1 << 17]byte var x16271 [1 << 17]byte var x16272 [1 << 17]byte var x16273 [1 << 17]byte var x16274 [1 << 17]byte var x16275 [1 << 17]byte var x16276 [1 << 17]byte var x16277 [1 << 17]byte var x16278 [1 << 17]byte var x16279 [1 << 17]byte var x16280 [1 << 17]byte var x16281 [1 << 17]byte var x16282 [1 << 17]byte var x16283 [1 << 17]byte var x16284 [1 << 17]byte var x16285 [1 << 17]byte var x16286 [1 << 17]byte var x16287 [1 << 17]byte var x16288 [1 << 17]byte var x16289 [1 << 17]byte var x16290 [1 << 17]byte var x16291 [1 << 17]byte var x16292 [1 << 17]byte var x16293 [1 << 17]byte var x16294 [1 << 17]byte var x16295 [1 << 17]byte var x16296 [1 << 17]byte var x16297 [1 << 17]byte var x16298 [1 << 17]byte var x16299 [1 << 17]byte var x16300 [1 << 17]byte var x16301 [1 << 17]byte var x16302 [1 << 17]byte var x16303 [1 << 17]byte var x16304 [1 << 17]byte var x16305 [1 << 17]byte var x16306 [1 << 17]byte var x16307 [1 << 17]byte var x16308 [1 << 17]byte var x16309 [1 << 17]byte var x16310 [1 << 17]byte var x16311 [1 << 17]byte var x16312 [1 << 17]byte var x16313 [1 << 17]byte var x16314 [1 << 17]byte var x16315 [1 << 17]byte var x16316 [1 << 17]byte var x16317 [1 << 17]byte var x16318 [1 << 17]byte var x16319 [1 << 17]byte var x16320 [1 << 17]byte var x16321 [1 << 17]byte var x16322 [1 << 17]byte var x16323 [1 << 17]byte var x16324 [1 << 17]byte var x16325 [1 << 17]byte var x16326 [1 << 17]byte var x16327 [1 << 17]byte var x16328 [1 << 17]byte var x16329 [1 << 17]byte var x16330 [1 << 17]byte var x16331 [1 << 17]byte var x16332 [1 << 17]byte var x16333 [1 << 17]byte var x16334 [1 << 17]byte var x16335 [1 << 17]byte var x16336 [1 << 17]byte var x16337 [1 << 17]byte var x16338 [1 << 17]byte var x16339 [1 << 17]byte var x16340 [1 << 17]byte var x16341 [1 << 17]byte var x16342 [1 << 17]byte var x16343 [1 << 17]byte var x16344 [1 << 17]byte var x16345 [1 << 17]byte var x16346 [1 << 17]byte var x16347 [1 << 17]byte var x16348 [1 << 17]byte var x16349 [1 << 17]byte var x16350 [1 << 17]byte var x16351 [1 << 17]byte var x16352 [1 << 17]byte var x16353 [1 << 17]byte var x16354 [1 << 17]byte var x16355 [1 << 17]byte var x16356 [1 << 17]byte var x16357 [1 << 17]byte var x16358 [1 << 17]byte var x16359 [1 << 17]byte var x16360 [1 << 17]byte var x16361 [1 << 17]byte var x16362 [1 << 17]byte var x16363 [1 << 17]byte var x16364 [1 << 17]byte var x16365 [1 << 17]byte var x16366 [1 << 17]byte var x16367 [1 << 17]byte var x16368 [1 << 17]byte var x16369 [1 << 17]byte var x16370 [1 << 17]byte var x16371 [1 << 17]byte var x16372 [1 << 17]byte var x16373 [1 << 17]byte var x16374 [1 << 17]byte var x16375 [1 << 17]byte var x16376 [1 << 17]byte var x16377 [1 << 17]byte var x16378 [1 << 17]byte var x16379 [1 << 17]byte var x16380 [1 << 17]byte var x16381 [1 << 17]byte var x16382 [1 << 17]byte var x16383 [1 << 17]byte var x16384 [1 << 17]byte var x16385 [1 << 17]byte var x16386 [1 << 17]byte var x16387 [1 << 17]byte var x16388 [1 << 17]byte var x16389 [1 << 17]byte var x16390 [1 << 17]byte var x16391 [1 << 17]byte var x16392 [1 << 17]byte var x16393 [1 << 17]byte var x16394 [1 << 17]byte var x16395 [1 << 17]byte var x16396 [1 << 17]byte var x16397 [1 << 17]byte var x16398 [1 << 17]byte var x16399 [1 << 17]byte var x16400 [1 << 17]byte var x16401 [1 << 17]byte var x16402 [1 << 17]byte var x16403 [1 << 17]byte var x16404 [1 << 17]byte var x16405 [1 << 17]byte var x16406 [1 << 17]byte var x16407 [1 << 17]byte var x16408 [1 << 17]byte var x16409 [1 << 17]byte var x16410 [1 << 17]byte var x16411 [1 << 17]byte var x16412 [1 << 17]byte var x16413 [1 << 17]byte var x16414 [1 << 17]byte var x16415 [1 << 17]byte var x16416 [1 << 17]byte var x16417 [1 << 17]byte var x16418 [1 << 17]byte var x16419 [1 << 17]byte var x16420 [1 << 17]byte var x16421 [1 << 17]byte var x16422 [1 << 17]byte var x16423 [1 << 17]byte var x16424 [1 << 17]byte var x16425 [1 << 17]byte var x16426 [1 << 17]byte var x16427 [1 << 17]byte var x16428 [1 << 17]byte var x16429 [1 << 17]byte var x16430 [1 << 17]byte var x16431 [1 << 17]byte var x16432 [1 << 17]byte var x16433 [1 << 17]byte var x16434 [1 << 17]byte var x16435 [1 << 17]byte var x16436 [1 << 17]byte var x16437 [1 << 17]byte var x16438 [1 << 17]byte var x16439 [1 << 17]byte var x16440 [1 << 17]byte var x16441 [1 << 17]byte var x16442 [1 << 17]byte var x16443 [1 << 17]byte var x16444 [1 << 17]byte var x16445 [1 << 17]byte var x16446 [1 << 17]byte var x16447 [1 << 17]byte var x16448 [1 << 17]byte var x16449 [1 << 17]byte var x16450 [1 << 17]byte var x16451 [1 << 17]byte var x16452 [1 << 17]byte var x16453 [1 << 17]byte var x16454 [1 << 17]byte var x16455 [1 << 17]byte var x16456 [1 << 17]byte var x16457 [1 << 17]byte var x16458 [1 << 17]byte var x16459 [1 << 17]byte var x16460 [1 << 17]byte var x16461 [1 << 17]byte var x16462 [1 << 17]byte var x16463 [1 << 17]byte var x16464 [1 << 17]byte var x16465 [1 << 17]byte var x16466 [1 << 17]byte var x16467 [1 << 17]byte var x16468 [1 << 17]byte var x16469 [1 << 17]byte var x16470 [1 << 17]byte var x16471 [1 << 17]byte var x16472 [1 << 17]byte var x16473 [1 << 17]byte var x16474 [1 << 17]byte var x16475 [1 << 17]byte var x16476 [1 << 17]byte var x16477 [1 << 17]byte var x16478 [1 << 17]byte var x16479 [1 << 17]byte var x16480 [1 << 17]byte z1 = x1 z2 = x2 z3 = x3 z4 = x4 z5 = x5 z6 = x6 z7 = x7 z8 = x8 z9 = x9 z10 = x10 z11 = x11 z12 = x12 z13 = x13 z14 = x14 z15 = x15 z16 = x16 z17 = x17 z18 = x18 z19 = x19 z20 = x20 z21 = x21 z22 = x22 z23 = x23 z24 = x24 z25 = x25 z26 = x26 z27 = x27 z28 = x28 z29 = x29 z30 = x30 z31 = x31 z32 = x32 z33 = x33 z34 = x34 z35 = x35 z36 = x36 z37 = x37 z38 = x38 z39 = x39 z40 = x40 z41 = x41 z42 = x42 z43 = x43 z44 = x44 z45 = x45 z46 = x46 z47 = x47 z48 = x48 z49 = x49 z50 = x50 z51 = x51 z52 = x52 z53 = x53 z54 = x54 z55 = x55 z56 = x56 z57 = x57 z58 = x58 z59 = x59 z60 = x60 z61 = x61 z62 = x62 z63 = x63 z64 = x64 z65 = x65 z66 = x66 z67 = x67 z68 = x68 z69 = x69 z70 = x70 z71 = x71 z72 = x72 z73 = x73 z74 = x74 z75 = x75 z76 = x76 z77 = x77 z78 = x78 z79 = x79 z80 = x80 z81 = x81 z82 = x82 z83 = x83 z84 = x84 z85 = x85 z86 = x86 z87 = x87 z88 = x88 z89 = x89 z90 = x90 z91 = x91 z92 = x92 z93 = x93 z94 = x94 z95 = x95 z96 = x96 z97 = x97 z98 = x98 z99 = x99 z100 = x100 z101 = x101 z102 = x102 z103 = x103 z104 = x104 z105 = x105 z106 = x106 z107 = x107 z108 = x108 z109 = x109 z110 = x110 z111 = x111 z112 = x112 z113 = x113 z114 = x114 z115 = x115 z116 = x116 z117 = x117 z118 = x118 z119 = x119 z120 = x120 z121 = x121 z122 = x122 z123 = x123 z124 = x124 z125 = x125 z126 = x126 z127 = x127 z128 = x128 z129 = x129 z130 = x130 z131 = x131 z132 = x132 z133 = x133 z134 = x134 z135 = x135 z136 = x136 z137 = x137 z138 = x138 z139 = x139 z140 = x140 z141 = x141 z142 = x142 z143 = x143 z144 = x144 z145 = x145 z146 = x146 z147 = x147 z148 = x148 z149 = x149 z150 = x150 z151 = x151 z152 = x152 z153 = x153 z154 = x154 z155 = x155 z156 = x156 z157 = x157 z158 = x158 z159 = x159 z160 = x160 z161 = x161 z162 = x162 z163 = x163 z164 = x164 z165 = x165 z166 = x166 z167 = x167 z168 = x168 z169 = x169 z170 = x170 z171 = x171 z172 = x172 z173 = x173 z174 = x174 z175 = x175 z176 = x176 z177 = x177 z178 = x178 z179 = x179 z180 = x180 z181 = x181 z182 = x182 z183 = x183 z184 = x184 z185 = x185 z186 = x186 z187 = x187 z188 = x188 z189 = x189 z190 = x190 z191 = x191 z192 = x192 z193 = x193 z194 = x194 z195 = x195 z196 = x196 z197 = x197 z198 = x198 z199 = x199 z200 = x200 z201 = x201 z202 = x202 z203 = x203 z204 = x204 z205 = x205 z206 = x206 z207 = x207 z208 = x208 z209 = x209 z210 = x210 z211 = x211 z212 = x212 z213 = x213 z214 = x214 z215 = x215 z216 = x216 z217 = x217 z218 = x218 z219 = x219 z220 = x220 z221 = x221 z222 = x222 z223 = x223 z224 = x224 z225 = x225 z226 = x226 z227 = x227 z228 = x228 z229 = x229 z230 = x230 z231 = x231 z232 = x232 z233 = x233 z234 = x234 z235 = x235 z236 = x236 z237 = x237 z238 = x238 z239 = x239 z240 = x240 z241 = x241 z242 = x242 z243 = x243 z244 = x244 z245 = x245 z246 = x246 z247 = x247 z248 = x248 z249 = x249 z250 = x250 z251 = x251 z252 = x252 z253 = x253 z254 = x254 z255 = x255 z256 = x256 z257 = x257 z258 = x258 z259 = x259 z260 = x260 z261 = x261 z262 = x262 z263 = x263 z264 = x264 z265 = x265 z266 = x266 z267 = x267 z268 = x268 z269 = x269 z270 = x270 z271 = x271 z272 = x272 z273 = x273 z274 = x274 z275 = x275 z276 = x276 z277 = x277 z278 = x278 z279 = x279 z280 = x280 z281 = x281 z282 = x282 z283 = x283 z284 = x284 z285 = x285 z286 = x286 z287 = x287 z288 = x288 z289 = x289 z290 = x290 z291 = x291 z292 = x292 z293 = x293 z294 = x294 z295 = x295 z296 = x296 z297 = x297 z298 = x298 z299 = x299 z300 = x300 z301 = x301 z302 = x302 z303 = x303 z304 = x304 z305 = x305 z306 = x306 z307 = x307 z308 = x308 z309 = x309 z310 = x310 z311 = x311 z312 = x312 z313 = x313 z314 = x314 z315 = x315 z316 = x316 z317 = x317 z318 = x318 z319 = x319 z320 = x320 z321 = x321 z322 = x322 z323 = x323 z324 = x324 z325 = x325 z326 = x326 z327 = x327 z328 = x328 z329 = x329 z330 = x330 z331 = x331 z332 = x332 z333 = x333 z334 = x334 z335 = x335 z336 = x336 z337 = x337 z338 = x338 z339 = x339 z340 = x340 z341 = x341 z342 = x342 z343 = x343 z344 = x344 z345 = x345 z346 = x346 z347 = x347 z348 = x348 z349 = x349 z350 = x350 z351 = x351 z352 = x352 z353 = x353 z354 = x354 z355 = x355 z356 = x356 z357 = x357 z358 = x358 z359 = x359 z360 = x360 z361 = x361 z362 = x362 z363 = x363 z364 = x364 z365 = x365 z366 = x366 z367 = x367 z368 = x368 z369 = x369 z370 = x370 z371 = x371 z372 = x372 z373 = x373 z374 = x374 z375 = x375 z376 = x376 z377 = x377 z378 = x378 z379 = x379 z380 = x380 z381 = x381 z382 = x382 z383 = x383 z384 = x384 z385 = x385 z386 = x386 z387 = x387 z388 = x388 z389 = x389 z390 = x390 z391 = x391 z392 = x392 z393 = x393 z394 = x394 z395 = x395 z396 = x396 z397 = x397 z398 = x398 z399 = x399 z400 = x400 z401 = x401 z402 = x402 z403 = x403 z404 = x404 z405 = x405 z406 = x406 z407 = x407 z408 = x408 z409 = x409 z410 = x410 z411 = x411 z412 = x412 z413 = x413 z414 = x414 z415 = x415 z416 = x416 z417 = x417 z418 = x418 z419 = x419 z420 = x420 z421 = x421 z422 = x422 z423 = x423 z424 = x424 z425 = x425 z426 = x426 z427 = x427 z428 = x428 z429 = x429 z430 = x430 z431 = x431 z432 = x432 z433 = x433 z434 = x434 z435 = x435 z436 = x436 z437 = x437 z438 = x438 z439 = x439 z440 = x440 z441 = x441 z442 = x442 z443 = x443 z444 = x444 z445 = x445 z446 = x446 z447 = x447 z448 = x448 z449 = x449 z450 = x450 z451 = x451 z452 = x452 z453 = x453 z454 = x454 z455 = x455 z456 = x456 z457 = x457 z458 = x458 z459 = x459 z460 = x460 z461 = x461 z462 = x462 z463 = x463 z464 = x464 z465 = x465 z466 = x466 z467 = x467 z468 = x468 z469 = x469 z470 = x470 z471 = x471 z472 = x472 z473 = x473 z474 = x474 z475 = x475 z476 = x476 z477 = x477 z478 = x478 z479 = x479 z480 = x480 z481 = x481 z482 = x482 z483 = x483 z484 = x484 z485 = x485 z486 = x486 z487 = x487 z488 = x488 z489 = x489 z490 = x490 z491 = x491 z492 = x492 z493 = x493 z494 = x494 z495 = x495 z496 = x496 z497 = x497 z498 = x498 z499 = x499 z500 = x500 z501 = x501 z502 = x502 z503 = x503 z504 = x504 z505 = x505 z506 = x506 z507 = x507 z508 = x508 z509 = x509 z510 = x510 z511 = x511 z512 = x512 z513 = x513 z514 = x514 z515 = x515 z516 = x516 z517 = x517 z518 = x518 z519 = x519 z520 = x520 z521 = x521 z522 = x522 z523 = x523 z524 = x524 z525 = x525 z526 = x526 z527 = x527 z528 = x528 z529 = x529 z530 = x530 z531 = x531 z532 = x532 z533 = x533 z534 = x534 z535 = x535 z536 = x536 z537 = x537 z538 = x538 z539 = x539 z540 = x540 z541 = x541 z542 = x542 z543 = x543 z544 = x544 z545 = x545 z546 = x546 z547 = x547 z548 = x548 z549 = x549 z550 = x550 z551 = x551 z552 = x552 z553 = x553 z554 = x554 z555 = x555 z556 = x556 z557 = x557 z558 = x558 z559 = x559 z560 = x560 z561 = x561 z562 = x562 z563 = x563 z564 = x564 z565 = x565 z566 = x566 z567 = x567 z568 = x568 z569 = x569 z570 = x570 z571 = x571 z572 = x572 z573 = x573 z574 = x574 z575 = x575 z576 = x576 z577 = x577 z578 = x578 z579 = x579 z580 = x580 z581 = x581 z582 = x582 z583 = x583 z584 = x584 z585 = x585 z586 = x586 z587 = x587 z588 = x588 z589 = x589 z590 = x590 z591 = x591 z592 = x592 z593 = x593 z594 = x594 z595 = x595 z596 = x596 z597 = x597 z598 = x598 z599 = x599 z600 = x600 z601 = x601 z602 = x602 z603 = x603 z604 = x604 z605 = x605 z606 = x606 z607 = x607 z608 = x608 z609 = x609 z610 = x610 z611 = x611 z612 = x612 z613 = x613 z614 = x614 z615 = x615 z616 = x616 z617 = x617 z618 = x618 z619 = x619 z620 = x620 z621 = x621 z622 = x622 z623 = x623 z624 = x624 z625 = x625 z626 = x626 z627 = x627 z628 = x628 z629 = x629 z630 = x630 z631 = x631 z632 = x632 z633 = x633 z634 = x634 z635 = x635 z636 = x636 z637 = x637 z638 = x638 z639 = x639 z640 = x640 z641 = x641 z642 = x642 z643 = x643 z644 = x644 z645 = x645 z646 = x646 z647 = x647 z648 = x648 z649 = x649 z650 = x650 z651 = x651 z652 = x652 z653 = x653 z654 = x654 z655 = x655 z656 = x656 z657 = x657 z658 = x658 z659 = x659 z660 = x660 z661 = x661 z662 = x662 z663 = x663 z664 = x664 z665 = x665 z666 = x666 z667 = x667 z668 = x668 z669 = x669 z670 = x670 z671 = x671 z672 = x672 z673 = x673 z674 = x674 z675 = x675 z676 = x676 z677 = x677 z678 = x678 z679 = x679 z680 = x680 z681 = x681 z682 = x682 z683 = x683 z684 = x684 z685 = x685 z686 = x686 z687 = x687 z688 = x688 z689 = x689 z690 = x690 z691 = x691 z692 = x692 z693 = x693 z694 = x694 z695 = x695 z696 = x696 z697 = x697 z698 = x698 z699 = x699 z700 = x700 z701 = x701 z702 = x702 z703 = x703 z704 = x704 z705 = x705 z706 = x706 z707 = x707 z708 = x708 z709 = x709 z710 = x710 z711 = x711 z712 = x712 z713 = x713 z714 = x714 z715 = x715 z716 = x716 z717 = x717 z718 = x718 z719 = x719 z720 = x720 z721 = x721 z722 = x722 z723 = x723 z724 = x724 z725 = x725 z726 = x726 z727 = x727 z728 = x728 z729 = x729 z730 = x730 z731 = x731 z732 = x732 z733 = x733 z734 = x734 z735 = x735 z736 = x736 z737 = x737 z738 = x738 z739 = x739 z740 = x740 z741 = x741 z742 = x742 z743 = x743 z744 = x744 z745 = x745 z746 = x746 z747 = x747 z748 = x748 z749 = x749 z750 = x750 z751 = x751 z752 = x752 z753 = x753 z754 = x754 z755 = x755 z756 = x756 z757 = x757 z758 = x758 z759 = x759 z760 = x760 z761 = x761 z762 = x762 z763 = x763 z764 = x764 z765 = x765 z766 = x766 z767 = x767 z768 = x768 z769 = x769 z770 = x770 z771 = x771 z772 = x772 z773 = x773 z774 = x774 z775 = x775 z776 = x776 z777 = x777 z778 = x778 z779 = x779 z780 = x780 z781 = x781 z782 = x782 z783 = x783 z784 = x784 z785 = x785 z786 = x786 z787 = x787 z788 = x788 z789 = x789 z790 = x790 z791 = x791 z792 = x792 z793 = x793 z794 = x794 z795 = x795 z796 = x796 z797 = x797 z798 = x798 z799 = x799 z800 = x800 z801 = x801 z802 = x802 z803 = x803 z804 = x804 z805 = x805 z806 = x806 z807 = x807 z808 = x808 z809 = x809 z810 = x810 z811 = x811 z812 = x812 z813 = x813 z814 = x814 z815 = x815 z816 = x816 z817 = x817 z818 = x818 z819 = x819 z820 = x820 z821 = x821 z822 = x822 z823 = x823 z824 = x824 z825 = x825 z826 = x826 z827 = x827 z828 = x828 z829 = x829 z830 = x830 z831 = x831 z832 = x832 z833 = x833 z834 = x834 z835 = x835 z836 = x836 z837 = x837 z838 = x838 z839 = x839 z840 = x840 z841 = x841 z842 = x842 z843 = x843 z844 = x844 z845 = x845 z846 = x846 z847 = x847 z848 = x848 z849 = x849 z850 = x850 z851 = x851 z852 = x852 z853 = x853 z854 = x854 z855 = x855 z856 = x856 z857 = x857 z858 = x858 z859 = x859 z860 = x860 z861 = x861 z862 = x862 z863 = x863 z864 = x864 z865 = x865 z866 = x866 z867 = x867 z868 = x868 z869 = x869 z870 = x870 z871 = x871 z872 = x872 z873 = x873 z874 = x874 z875 = x875 z876 = x876 z877 = x877 z878 = x878 z879 = x879 z880 = x880 z881 = x881 z882 = x882 z883 = x883 z884 = x884 z885 = x885 z886 = x886 z887 = x887 z888 = x888 z889 = x889 z890 = x890 z891 = x891 z892 = x892 z893 = x893 z894 = x894 z895 = x895 z896 = x896 z897 = x897 z898 = x898 z899 = x899 z900 = x900 z901 = x901 z902 = x902 z903 = x903 z904 = x904 z905 = x905 z906 = x906 z907 = x907 z908 = x908 z909 = x909 z910 = x910 z911 = x911 z912 = x912 z913 = x913 z914 = x914 z915 = x915 z916 = x916 z917 = x917 z918 = x918 z919 = x919 z920 = x920 z921 = x921 z922 = x922 z923 = x923 z924 = x924 z925 = x925 z926 = x926 z927 = x927 z928 = x928 z929 = x929 z930 = x930 z931 = x931 z932 = x932 z933 = x933 z934 = x934 z935 = x935 z936 = x936 z937 = x937 z938 = x938 z939 = x939 z940 = x940 z941 = x941 z942 = x942 z943 = x943 z944 = x944 z945 = x945 z946 = x946 z947 = x947 z948 = x948 z949 = x949 z950 = x950 z951 = x951 z952 = x952 z953 = x953 z954 = x954 z955 = x955 z956 = x956 z957 = x957 z958 = x958 z959 = x959 z960 = x960 z961 = x961 z962 = x962 z963 = x963 z964 = x964 z965 = x965 z966 = x966 z967 = x967 z968 = x968 z969 = x969 z970 = x970 z971 = x971 z972 = x972 z973 = x973 z974 = x974 z975 = x975 z976 = x976 z977 = x977 z978 = x978 z979 = x979 z980 = x980 z981 = x981 z982 = x982 z983 = x983 z984 = x984 z985 = x985 z986 = x986 z987 = x987 z988 = x988 z989 = x989 z990 = x990 z991 = x991 z992 = x992 z993 = x993 z994 = x994 z995 = x995 z996 = x996 z997 = x997 z998 = x998 z999 = x999 z1000 = x1000 z1001 = x1001 z1002 = x1002 z1003 = x1003 z1004 = x1004 z1005 = x1005 z1006 = x1006 z1007 = x1007 z1008 = x1008 z1009 = x1009 z1010 = x1010 z1011 = x1011 z1012 = x1012 z1013 = x1013 z1014 = x1014 z1015 = x1015 z1016 = x1016 z1017 = x1017 z1018 = x1018 z1019 = x1019 z1020 = x1020 z1021 = x1021 z1022 = x1022 z1023 = x1023 z1024 = x1024 z1025 = x1025 z1026 = x1026 z1027 = x1027 z1028 = x1028 z1029 = x1029 z1030 = x1030 z1031 = x1031 z1032 = x1032 z1033 = x1033 z1034 = x1034 z1035 = x1035 z1036 = x1036 z1037 = x1037 z1038 = x1038 z1039 = x1039 z1040 = x1040 z1041 = x1041 z1042 = x1042 z1043 = x1043 z1044 = x1044 z1045 = x1045 z1046 = x1046 z1047 = x1047 z1048 = x1048 z1049 = x1049 z1050 = x1050 z1051 = x1051 z1052 = x1052 z1053 = x1053 z1054 = x1054 z1055 = x1055 z1056 = x1056 z1057 = x1057 z1058 = x1058 z1059 = x1059 z1060 = x1060 z1061 = x1061 z1062 = x1062 z1063 = x1063 z1064 = x1064 z1065 = x1065 z1066 = x1066 z1067 = x1067 z1068 = x1068 z1069 = x1069 z1070 = x1070 z1071 = x1071 z1072 = x1072 z1073 = x1073 z1074 = x1074 z1075 = x1075 z1076 = x1076 z1077 = x1077 z1078 = x1078 z1079 = x1079 z1080 = x1080 z1081 = x1081 z1082 = x1082 z1083 = x1083 z1084 = x1084 z1085 = x1085 z1086 = x1086 z1087 = x1087 z1088 = x1088 z1089 = x1089 z1090 = x1090 z1091 = x1091 z1092 = x1092 z1093 = x1093 z1094 = x1094 z1095 = x1095 z1096 = x1096 z1097 = x1097 z1098 = x1098 z1099 = x1099 z1100 = x1100 z1101 = x1101 z1102 = x1102 z1103 = x1103 z1104 = x1104 z1105 = x1105 z1106 = x1106 z1107 = x1107 z1108 = x1108 z1109 = x1109 z1110 = x1110 z1111 = x1111 z1112 = x1112 z1113 = x1113 z1114 = x1114 z1115 = x1115 z1116 = x1116 z1117 = x1117 z1118 = x1118 z1119 = x1119 z1120 = x1120 z1121 = x1121 z1122 = x1122 z1123 = x1123 z1124 = x1124 z1125 = x1125 z1126 = x1126 z1127 = x1127 z1128 = x1128 z1129 = x1129 z1130 = x1130 z1131 = x1131 z1132 = x1132 z1133 = x1133 z1134 = x1134 z1135 = x1135 z1136 = x1136 z1137 = x1137 z1138 = x1138 z1139 = x1139 z1140 = x1140 z1141 = x1141 z1142 = x1142 z1143 = x1143 z1144 = x1144 z1145 = x1145 z1146 = x1146 z1147 = x1147 z1148 = x1148 z1149 = x1149 z1150 = x1150 z1151 = x1151 z1152 = x1152 z1153 = x1153 z1154 = x1154 z1155 = x1155 z1156 = x1156 z1157 = x1157 z1158 = x1158 z1159 = x1159 z1160 = x1160 z1161 = x1161 z1162 = x1162 z1163 = x1163 z1164 = x1164 z1165 = x1165 z1166 = x1166 z1167 = x1167 z1168 = x1168 z1169 = x1169 z1170 = x1170 z1171 = x1171 z1172 = x1172 z1173 = x1173 z1174 = x1174 z1175 = x1175 z1176 = x1176 z1177 = x1177 z1178 = x1178 z1179 = x1179 z1180 = x1180 z1181 = x1181 z1182 = x1182 z1183 = x1183 z1184 = x1184 z1185 = x1185 z1186 = x1186 z1187 = x1187 z1188 = x1188 z1189 = x1189 z1190 = x1190 z1191 = x1191 z1192 = x1192 z1193 = x1193 z1194 = x1194 z1195 = x1195 z1196 = x1196 z1197 = x1197 z1198 = x1198 z1199 = x1199 z1200 = x1200 z1201 = x1201 z1202 = x1202 z1203 = x1203 z1204 = x1204 z1205 = x1205 z1206 = x1206 z1207 = x1207 z1208 = x1208 z1209 = x1209 z1210 = x1210 z1211 = x1211 z1212 = x1212 z1213 = x1213 z1214 = x1214 z1215 = x1215 z1216 = x1216 z1217 = x1217 z1218 = x1218 z1219 = x1219 z1220 = x1220 z1221 = x1221 z1222 = x1222 z1223 = x1223 z1224 = x1224 z1225 = x1225 z1226 = x1226 z1227 = x1227 z1228 = x1228 z1229 = x1229 z1230 = x1230 z1231 = x1231 z1232 = x1232 z1233 = x1233 z1234 = x1234 z1235 = x1235 z1236 = x1236 z1237 = x1237 z1238 = x1238 z1239 = x1239 z1240 = x1240 z1241 = x1241 z1242 = x1242 z1243 = x1243 z1244 = x1244 z1245 = x1245 z1246 = x1246 z1247 = x1247 z1248 = x1248 z1249 = x1249 z1250 = x1250 z1251 = x1251 z1252 = x1252 z1253 = x1253 z1254 = x1254 z1255 = x1255 z1256 = x1256 z1257 = x1257 z1258 = x1258 z1259 = x1259 z1260 = x1260 z1261 = x1261 z1262 = x1262 z1263 = x1263 z1264 = x1264 z1265 = x1265 z1266 = x1266 z1267 = x1267 z1268 = x1268 z1269 = x1269 z1270 = x1270 z1271 = x1271 z1272 = x1272 z1273 = x1273 z1274 = x1274 z1275 = x1275 z1276 = x1276 z1277 = x1277 z1278 = x1278 z1279 = x1279 z1280 = x1280 z1281 = x1281 z1282 = x1282 z1283 = x1283 z1284 = x1284 z1285 = x1285 z1286 = x1286 z1287 = x1287 z1288 = x1288 z1289 = x1289 z1290 = x1290 z1291 = x1291 z1292 = x1292 z1293 = x1293 z1294 = x1294 z1295 = x1295 z1296 = x1296 z1297 = x1297 z1298 = x1298 z1299 = x1299 z1300 = x1300 z1301 = x1301 z1302 = x1302 z1303 = x1303 z1304 = x1304 z1305 = x1305 z1306 = x1306 z1307 = x1307 z1308 = x1308 z1309 = x1309 z1310 = x1310 z1311 = x1311 z1312 = x1312 z1313 = x1313 z1314 = x1314 z1315 = x1315 z1316 = x1316 z1317 = x1317 z1318 = x1318 z1319 = x1319 z1320 = x1320 z1321 = x1321 z1322 = x1322 z1323 = x1323 z1324 = x1324 z1325 = x1325 z1326 = x1326 z1327 = x1327 z1328 = x1328 z1329 = x1329 z1330 = x1330 z1331 = x1331 z1332 = x1332 z1333 = x1333 z1334 = x1334 z1335 = x1335 z1336 = x1336 z1337 = x1337 z1338 = x1338 z1339 = x1339 z1340 = x1340 z1341 = x1341 z1342 = x1342 z1343 = x1343 z1344 = x1344 z1345 = x1345 z1346 = x1346 z1347 = x1347 z1348 = x1348 z1349 = x1349 z1350 = x1350 z1351 = x1351 z1352 = x1352 z1353 = x1353 z1354 = x1354 z1355 = x1355 z1356 = x1356 z1357 = x1357 z1358 = x1358 z1359 = x1359 z1360 = x1360 z1361 = x1361 z1362 = x1362 z1363 = x1363 z1364 = x1364 z1365 = x1365 z1366 = x1366 z1367 = x1367 z1368 = x1368 z1369 = x1369 z1370 = x1370 z1371 = x1371 z1372 = x1372 z1373 = x1373 z1374 = x1374 z1375 = x1375 z1376 = x1376 z1377 = x1377 z1378 = x1378 z1379 = x1379 z1380 = x1380 z1381 = x1381 z1382 = x1382 z1383 = x1383 z1384 = x1384 z1385 = x1385 z1386 = x1386 z1387 = x1387 z1388 = x1388 z1389 = x1389 z1390 = x1390 z1391 = x1391 z1392 = x1392 z1393 = x1393 z1394 = x1394 z1395 = x1395 z1396 = x1396 z1397 = x1397 z1398 = x1398 z1399 = x1399 z1400 = x1400 z1401 = x1401 z1402 = x1402 z1403 = x1403 z1404 = x1404 z1405 = x1405 z1406 = x1406 z1407 = x1407 z1408 = x1408 z1409 = x1409 z1410 = x1410 z1411 = x1411 z1412 = x1412 z1413 = x1413 z1414 = x1414 z1415 = x1415 z1416 = x1416 z1417 = x1417 z1418 = x1418 z1419 = x1419 z1420 = x1420 z1421 = x1421 z1422 = x1422 z1423 = x1423 z1424 = x1424 z1425 = x1425 z1426 = x1426 z1427 = x1427 z1428 = x1428 z1429 = x1429 z1430 = x1430 z1431 = x1431 z1432 = x1432 z1433 = x1433 z1434 = x1434 z1435 = x1435 z1436 = x1436 z1437 = x1437 z1438 = x1438 z1439 = x1439 z1440 = x1440 z1441 = x1441 z1442 = x1442 z1443 = x1443 z1444 = x1444 z1445 = x1445 z1446 = x1446 z1447 = x1447 z1448 = x1448 z1449 = x1449 z1450 = x1450 z1451 = x1451 z1452 = x1452 z1453 = x1453 z1454 = x1454 z1455 = x1455 z1456 = x1456 z1457 = x1457 z1458 = x1458 z1459 = x1459 z1460 = x1460 z1461 = x1461 z1462 = x1462 z1463 = x1463 z1464 = x1464 z1465 = x1465 z1466 = x1466 z1467 = x1467 z1468 = x1468 z1469 = x1469 z1470 = x1470 z1471 = x1471 z1472 = x1472 z1473 = x1473 z1474 = x1474 z1475 = x1475 z1476 = x1476 z1477 = x1477 z1478 = x1478 z1479 = x1479 z1480 = x1480 z1481 = x1481 z1482 = x1482 z1483 = x1483 z1484 = x1484 z1485 = x1485 z1486 = x1486 z1487 = x1487 z1488 = x1488 z1489 = x1489 z1490 = x1490 z1491 = x1491 z1492 = x1492 z1493 = x1493 z1494 = x1494 z1495 = x1495 z1496 = x1496 z1497 = x1497 z1498 = x1498 z1499 = x1499 z1500 = x1500 z1501 = x1501 z1502 = x1502 z1503 = x1503 z1504 = x1504 z1505 = x1505 z1506 = x1506 z1507 = x1507 z1508 = x1508 z1509 = x1509 z1510 = x1510 z1511 = x1511 z1512 = x1512 z1513 = x1513 z1514 = x1514 z1515 = x1515 z1516 = x1516 z1517 = x1517 z1518 = x1518 z1519 = x1519 z1520 = x1520 z1521 = x1521 z1522 = x1522 z1523 = x1523 z1524 = x1524 z1525 = x1525 z1526 = x1526 z1527 = x1527 z1528 = x1528 z1529 = x1529 z1530 = x1530 z1531 = x1531 z1532 = x1532 z1533 = x1533 z1534 = x1534 z1535 = x1535 z1536 = x1536 z1537 = x1537 z1538 = x1538 z1539 = x1539 z1540 = x1540 z1541 = x1541 z1542 = x1542 z1543 = x1543 z1544 = x1544 z1545 = x1545 z1546 = x1546 z1547 = x1547 z1548 = x1548 z1549 = x1549 z1550 = x1550 z1551 = x1551 z1552 = x1552 z1553 = x1553 z1554 = x1554 z1555 = x1555 z1556 = x1556 z1557 = x1557 z1558 = x1558 z1559 = x1559 z1560 = x1560 z1561 = x1561 z1562 = x1562 z1563 = x1563 z1564 = x1564 z1565 = x1565 z1566 = x1566 z1567 = x1567 z1568 = x1568 z1569 = x1569 z1570 = x1570 z1571 = x1571 z1572 = x1572 z1573 = x1573 z1574 = x1574 z1575 = x1575 z1576 = x1576 z1577 = x1577 z1578 = x1578 z1579 = x1579 z1580 = x1580 z1581 = x1581 z1582 = x1582 z1583 = x1583 z1584 = x1584 z1585 = x1585 z1586 = x1586 z1587 = x1587 z1588 = x1588 z1589 = x1589 z1590 = x1590 z1591 = x1591 z1592 = x1592 z1593 = x1593 z1594 = x1594 z1595 = x1595 z1596 = x1596 z1597 = x1597 z1598 = x1598 z1599 = x1599 z1600 = x1600 z1601 = x1601 z1602 = x1602 z1603 = x1603 z1604 = x1604 z1605 = x1605 z1606 = x1606 z1607 = x1607 z1608 = x1608 z1609 = x1609 z1610 = x1610 z1611 = x1611 z1612 = x1612 z1613 = x1613 z1614 = x1614 z1615 = x1615 z1616 = x1616 z1617 = x1617 z1618 = x1618 z1619 = x1619 z1620 = x1620 z1621 = x1621 z1622 = x1622 z1623 = x1623 z1624 = x1624 z1625 = x1625 z1626 = x1626 z1627 = x1627 z1628 = x1628 z1629 = x1629 z1630 = x1630 z1631 = x1631 z1632 = x1632 z1633 = x1633 z1634 = x1634 z1635 = x1635 z1636 = x1636 z1637 = x1637 z1638 = x1638 z1639 = x1639 z1640 = x1640 z1641 = x1641 z1642 = x1642 z1643 = x1643 z1644 = x1644 z1645 = x1645 z1646 = x1646 z1647 = x1647 z1648 = x1648 z1649 = x1649 z1650 = x1650 z1651 = x1651 z1652 = x1652 z1653 = x1653 z1654 = x1654 z1655 = x1655 z1656 = x1656 z1657 = x1657 z1658 = x1658 z1659 = x1659 z1660 = x1660 z1661 = x1661 z1662 = x1662 z1663 = x1663 z1664 = x1664 z1665 = x1665 z1666 = x1666 z1667 = x1667 z1668 = x1668 z1669 = x1669 z1670 = x1670 z1671 = x1671 z1672 = x1672 z1673 = x1673 z1674 = x1674 z1675 = x1675 z1676 = x1676 z1677 = x1677 z1678 = x1678 z1679 = x1679 z1680 = x1680 z1681 = x1681 z1682 = x1682 z1683 = x1683 z1684 = x1684 z1685 = x1685 z1686 = x1686 z1687 = x1687 z1688 = x1688 z1689 = x1689 z1690 = x1690 z1691 = x1691 z1692 = x1692 z1693 = x1693 z1694 = x1694 z1695 = x1695 z1696 = x1696 z1697 = x1697 z1698 = x1698 z1699 = x1699 z1700 = x1700 z1701 = x1701 z1702 = x1702 z1703 = x1703 z1704 = x1704 z1705 = x1705 z1706 = x1706 z1707 = x1707 z1708 = x1708 z1709 = x1709 z1710 = x1710 z1711 = x1711 z1712 = x1712 z1713 = x1713 z1714 = x1714 z1715 = x1715 z1716 = x1716 z1717 = x1717 z1718 = x1718 z1719 = x1719 z1720 = x1720 z1721 = x1721 z1722 = x1722 z1723 = x1723 z1724 = x1724 z1725 = x1725 z1726 = x1726 z1727 = x1727 z1728 = x1728 z1729 = x1729 z1730 = x1730 z1731 = x1731 z1732 = x1732 z1733 = x1733 z1734 = x1734 z1735 = x1735 z1736 = x1736 z1737 = x1737 z1738 = x1738 z1739 = x1739 z1740 = x1740 z1741 = x1741 z1742 = x1742 z1743 = x1743 z1744 = x1744 z1745 = x1745 z1746 = x1746 z1747 = x1747 z1748 = x1748 z1749 = x1749 z1750 = x1750 z1751 = x1751 z1752 = x1752 z1753 = x1753 z1754 = x1754 z1755 = x1755 z1756 = x1756 z1757 = x1757 z1758 = x1758 z1759 = x1759 z1760 = x1760 z1761 = x1761 z1762 = x1762 z1763 = x1763 z1764 = x1764 z1765 = x1765 z1766 = x1766 z1767 = x1767 z1768 = x1768 z1769 = x1769 z1770 = x1770 z1771 = x1771 z1772 = x1772 z1773 = x1773 z1774 = x1774 z1775 = x1775 z1776 = x1776 z1777 = x1777 z1778 = x1778 z1779 = x1779 z1780 = x1780 z1781 = x1781 z1782 = x1782 z1783 = x1783 z1784 = x1784 z1785 = x1785 z1786 = x1786 z1787 = x1787 z1788 = x1788 z1789 = x1789 z1790 = x1790 z1791 = x1791 z1792 = x1792 z1793 = x1793 z1794 = x1794 z1795 = x1795 z1796 = x1796 z1797 = x1797 z1798 = x1798 z1799 = x1799 z1800 = x1800 z1801 = x1801 z1802 = x1802 z1803 = x1803 z1804 = x1804 z1805 = x1805 z1806 = x1806 z1807 = x1807 z1808 = x1808 z1809 = x1809 z1810 = x1810 z1811 = x1811 z1812 = x1812 z1813 = x1813 z1814 = x1814 z1815 = x1815 z1816 = x1816 z1817 = x1817 z1818 = x1818 z1819 = x1819 z1820 = x1820 z1821 = x1821 z1822 = x1822 z1823 = x1823 z1824 = x1824 z1825 = x1825 z1826 = x1826 z1827 = x1827 z1828 = x1828 z1829 = x1829 z1830 = x1830 z1831 = x1831 z1832 = x1832 z1833 = x1833 z1834 = x1834 z1835 = x1835 z1836 = x1836 z1837 = x1837 z1838 = x1838 z1839 = x1839 z1840 = x1840 z1841 = x1841 z1842 = x1842 z1843 = x1843 z1844 = x1844 z1845 = x1845 z1846 = x1846 z1847 = x1847 z1848 = x1848 z1849 = x1849 z1850 = x1850 z1851 = x1851 z1852 = x1852 z1853 = x1853 z1854 = x1854 z1855 = x1855 z1856 = x1856 z1857 = x1857 z1858 = x1858 z1859 = x1859 z1860 = x1860 z1861 = x1861 z1862 = x1862 z1863 = x1863 z1864 = x1864 z1865 = x1865 z1866 = x1866 z1867 = x1867 z1868 = x1868 z1869 = x1869 z1870 = x1870 z1871 = x1871 z1872 = x1872 z1873 = x1873 z1874 = x1874 z1875 = x1875 z1876 = x1876 z1877 = x1877 z1878 = x1878 z1879 = x1879 z1880 = x1880 z1881 = x1881 z1882 = x1882 z1883 = x1883 z1884 = x1884 z1885 = x1885 z1886 = x1886 z1887 = x1887 z1888 = x1888 z1889 = x1889 z1890 = x1890 z1891 = x1891 z1892 = x1892 z1893 = x1893 z1894 = x1894 z1895 = x1895 z1896 = x1896 z1897 = x1897 z1898 = x1898 z1899 = x1899 z1900 = x1900 z1901 = x1901 z1902 = x1902 z1903 = x1903 z1904 = x1904 z1905 = x1905 z1906 = x1906 z1907 = x1907 z1908 = x1908 z1909 = x1909 z1910 = x1910 z1911 = x1911 z1912 = x1912 z1913 = x1913 z1914 = x1914 z1915 = x1915 z1916 = x1916 z1917 = x1917 z1918 = x1918 z1919 = x1919 z1920 = x1920 z1921 = x1921 z1922 = x1922 z1923 = x1923 z1924 = x1924 z1925 = x1925 z1926 = x1926 z1927 = x1927 z1928 = x1928 z1929 = x1929 z1930 = x1930 z1931 = x1931 z1932 = x1932 z1933 = x1933 z1934 = x1934 z1935 = x1935 z1936 = x1936 z1937 = x1937 z1938 = x1938 z1939 = x1939 z1940 = x1940 z1941 = x1941 z1942 = x1942 z1943 = x1943 z1944 = x1944 z1945 = x1945 z1946 = x1946 z1947 = x1947 z1948 = x1948 z1949 = x1949 z1950 = x1950 z1951 = x1951 z1952 = x1952 z1953 = x1953 z1954 = x1954 z1955 = x1955 z1956 = x1956 z1957 = x1957 z1958 = x1958 z1959 = x1959 z1960 = x1960 z1961 = x1961 z1962 = x1962 z1963 = x1963 z1964 = x1964 z1965 = x1965 z1966 = x1966 z1967 = x1967 z1968 = x1968 z1969 = x1969 z1970 = x1970 z1971 = x1971 z1972 = x1972 z1973 = x1973 z1974 = x1974 z1975 = x1975 z1976 = x1976 z1977 = x1977 z1978 = x1978 z1979 = x1979 z1980 = x1980 z1981 = x1981 z1982 = x1982 z1983 = x1983 z1984 = x1984 z1985 = x1985 z1986 = x1986 z1987 = x1987 z1988 = x1988 z1989 = x1989 z1990 = x1990 z1991 = x1991 z1992 = x1992 z1993 = x1993 z1994 = x1994 z1995 = x1995 z1996 = x1996 z1997 = x1997 z1998 = x1998 z1999 = x1999 z2000 = x2000 z2001 = x2001 z2002 = x2002 z2003 = x2003 z2004 = x2004 z2005 = x2005 z2006 = x2006 z2007 = x2007 z2008 = x2008 z2009 = x2009 z2010 = x2010 z2011 = x2011 z2012 = x2012 z2013 = x2013 z2014 = x2014 z2015 = x2015 z2016 = x2016 z2017 = x2017 z2018 = x2018 z2019 = x2019 z2020 = x2020 z2021 = x2021 z2022 = x2022 z2023 = x2023 z2024 = x2024 z2025 = x2025 z2026 = x2026 z2027 = x2027 z2028 = x2028 z2029 = x2029 z2030 = x2030 z2031 = x2031 z2032 = x2032 z2033 = x2033 z2034 = x2034 z2035 = x2035 z2036 = x2036 z2037 = x2037 z2038 = x2038 z2039 = x2039 z2040 = x2040 z2041 = x2041 z2042 = x2042 z2043 = x2043 z2044 = x2044 z2045 = x2045 z2046 = x2046 z2047 = x2047 z2048 = x2048 z2049 = x2049 z2050 = x2050 z2051 = x2051 z2052 = x2052 z2053 = x2053 z2054 = x2054 z2055 = x2055 z2056 = x2056 z2057 = x2057 z2058 = x2058 z2059 = x2059 z2060 = x2060 z2061 = x2061 z2062 = x2062 z2063 = x2063 z2064 = x2064 z2065 = x2065 z2066 = x2066 z2067 = x2067 z2068 = x2068 z2069 = x2069 z2070 = x2070 z2071 = x2071 z2072 = x2072 z2073 = x2073 z2074 = x2074 z2075 = x2075 z2076 = x2076 z2077 = x2077 z2078 = x2078 z2079 = x2079 z2080 = x2080 z2081 = x2081 z2082 = x2082 z2083 = x2083 z2084 = x2084 z2085 = x2085 z2086 = x2086 z2087 = x2087 z2088 = x2088 z2089 = x2089 z2090 = x2090 z2091 = x2091 z2092 = x2092 z2093 = x2093 z2094 = x2094 z2095 = x2095 z2096 = x2096 z2097 = x2097 z2098 = x2098 z2099 = x2099 z2100 = x2100 z2101 = x2101 z2102 = x2102 z2103 = x2103 z2104 = x2104 z2105 = x2105 z2106 = x2106 z2107 = x2107 z2108 = x2108 z2109 = x2109 z2110 = x2110 z2111 = x2111 z2112 = x2112 z2113 = x2113 z2114 = x2114 z2115 = x2115 z2116 = x2116 z2117 = x2117 z2118 = x2118 z2119 = x2119 z2120 = x2120 z2121 = x2121 z2122 = x2122 z2123 = x2123 z2124 = x2124 z2125 = x2125 z2126 = x2126 z2127 = x2127 z2128 = x2128 z2129 = x2129 z2130 = x2130 z2131 = x2131 z2132 = x2132 z2133 = x2133 z2134 = x2134 z2135 = x2135 z2136 = x2136 z2137 = x2137 z2138 = x2138 z2139 = x2139 z2140 = x2140 z2141 = x2141 z2142 = x2142 z2143 = x2143 z2144 = x2144 z2145 = x2145 z2146 = x2146 z2147 = x2147 z2148 = x2148 z2149 = x2149 z2150 = x2150 z2151 = x2151 z2152 = x2152 z2153 = x2153 z2154 = x2154 z2155 = x2155 z2156 = x2156 z2157 = x2157 z2158 = x2158 z2159 = x2159 z2160 = x2160 z2161 = x2161 z2162 = x2162 z2163 = x2163 z2164 = x2164 z2165 = x2165 z2166 = x2166 z2167 = x2167 z2168 = x2168 z2169 = x2169 z2170 = x2170 z2171 = x2171 z2172 = x2172 z2173 = x2173 z2174 = x2174 z2175 = x2175 z2176 = x2176 z2177 = x2177 z2178 = x2178 z2179 = x2179 z2180 = x2180 z2181 = x2181 z2182 = x2182 z2183 = x2183 z2184 = x2184 z2185 = x2185 z2186 = x2186 z2187 = x2187 z2188 = x2188 z2189 = x2189 z2190 = x2190 z2191 = x2191 z2192 = x2192 z2193 = x2193 z2194 = x2194 z2195 = x2195 z2196 = x2196 z2197 = x2197 z2198 = x2198 z2199 = x2199 z2200 = x2200 z2201 = x2201 z2202 = x2202 z2203 = x2203 z2204 = x2204 z2205 = x2205 z2206 = x2206 z2207 = x2207 z2208 = x2208 z2209 = x2209 z2210 = x2210 z2211 = x2211 z2212 = x2212 z2213 = x2213 z2214 = x2214 z2215 = x2215 z2216 = x2216 z2217 = x2217 z2218 = x2218 z2219 = x2219 z2220 = x2220 z2221 = x2221 z2222 = x2222 z2223 = x2223 z2224 = x2224 z2225 = x2225 z2226 = x2226 z2227 = x2227 z2228 = x2228 z2229 = x2229 z2230 = x2230 z2231 = x2231 z2232 = x2232 z2233 = x2233 z2234 = x2234 z2235 = x2235 z2236 = x2236 z2237 = x2237 z2238 = x2238 z2239 = x2239 z2240 = x2240 z2241 = x2241 z2242 = x2242 z2243 = x2243 z2244 = x2244 z2245 = x2245 z2246 = x2246 z2247 = x2247 z2248 = x2248 z2249 = x2249 z2250 = x2250 z2251 = x2251 z2252 = x2252 z2253 = x2253 z2254 = x2254 z2255 = x2255 z2256 = x2256 z2257 = x2257 z2258 = x2258 z2259 = x2259 z2260 = x2260 z2261 = x2261 z2262 = x2262 z2263 = x2263 z2264 = x2264 z2265 = x2265 z2266 = x2266 z2267 = x2267 z2268 = x2268 z2269 = x2269 z2270 = x2270 z2271 = x2271 z2272 = x2272 z2273 = x2273 z2274 = x2274 z2275 = x2275 z2276 = x2276 z2277 = x2277 z2278 = x2278 z2279 = x2279 z2280 = x2280 z2281 = x2281 z2282 = x2282 z2283 = x2283 z2284 = x2284 z2285 = x2285 z2286 = x2286 z2287 = x2287 z2288 = x2288 z2289 = x2289 z2290 = x2290 z2291 = x2291 z2292 = x2292 z2293 = x2293 z2294 = x2294 z2295 = x2295 z2296 = x2296 z2297 = x2297 z2298 = x2298 z2299 = x2299 z2300 = x2300 z2301 = x2301 z2302 = x2302 z2303 = x2303 z2304 = x2304 z2305 = x2305 z2306 = x2306 z2307 = x2307 z2308 = x2308 z2309 = x2309 z2310 = x2310 z2311 = x2311 z2312 = x2312 z2313 = x2313 z2314 = x2314 z2315 = x2315 z2316 = x2316 z2317 = x2317 z2318 = x2318 z2319 = x2319 z2320 = x2320 z2321 = x2321 z2322 = x2322 z2323 = x2323 z2324 = x2324 z2325 = x2325 z2326 = x2326 z2327 = x2327 z2328 = x2328 z2329 = x2329 z2330 = x2330 z2331 = x2331 z2332 = x2332 z2333 = x2333 z2334 = x2334 z2335 = x2335 z2336 = x2336 z2337 = x2337 z2338 = x2338 z2339 = x2339 z2340 = x2340 z2341 = x2341 z2342 = x2342 z2343 = x2343 z2344 = x2344 z2345 = x2345 z2346 = x2346 z2347 = x2347 z2348 = x2348 z2349 = x2349 z2350 = x2350 z2351 = x2351 z2352 = x2352 z2353 = x2353 z2354 = x2354 z2355 = x2355 z2356 = x2356 z2357 = x2357 z2358 = x2358 z2359 = x2359 z2360 = x2360 z2361 = x2361 z2362 = x2362 z2363 = x2363 z2364 = x2364 z2365 = x2365 z2366 = x2366 z2367 = x2367 z2368 = x2368 z2369 = x2369 z2370 = x2370 z2371 = x2371 z2372 = x2372 z2373 = x2373 z2374 = x2374 z2375 = x2375 z2376 = x2376 z2377 = x2377 z2378 = x2378 z2379 = x2379 z2380 = x2380 z2381 = x2381 z2382 = x2382 z2383 = x2383 z2384 = x2384 z2385 = x2385 z2386 = x2386 z2387 = x2387 z2388 = x2388 z2389 = x2389 z2390 = x2390 z2391 = x2391 z2392 = x2392 z2393 = x2393 z2394 = x2394 z2395 = x2395 z2396 = x2396 z2397 = x2397 z2398 = x2398 z2399 = x2399 z2400 = x2400 z2401 = x2401 z2402 = x2402 z2403 = x2403 z2404 = x2404 z2405 = x2405 z2406 = x2406 z2407 = x2407 z2408 = x2408 z2409 = x2409 z2410 = x2410 z2411 = x2411 z2412 = x2412 z2413 = x2413 z2414 = x2414 z2415 = x2415 z2416 = x2416 z2417 = x2417 z2418 = x2418 z2419 = x2419 z2420 = x2420 z2421 = x2421 z2422 = x2422 z2423 = x2423 z2424 = x2424 z2425 = x2425 z2426 = x2426 z2427 = x2427 z2428 = x2428 z2429 = x2429 z2430 = x2430 z2431 = x2431 z2432 = x2432 z2433 = x2433 z2434 = x2434 z2435 = x2435 z2436 = x2436 z2437 = x2437 z2438 = x2438 z2439 = x2439 z2440 = x2440 z2441 = x2441 z2442 = x2442 z2443 = x2443 z2444 = x2444 z2445 = x2445 z2446 = x2446 z2447 = x2447 z2448 = x2448 z2449 = x2449 z2450 = x2450 z2451 = x2451 z2452 = x2452 z2453 = x2453 z2454 = x2454 z2455 = x2455 z2456 = x2456 z2457 = x2457 z2458 = x2458 z2459 = x2459 z2460 = x2460 z2461 = x2461 z2462 = x2462 z2463 = x2463 z2464 = x2464 z2465 = x2465 z2466 = x2466 z2467 = x2467 z2468 = x2468 z2469 = x2469 z2470 = x2470 z2471 = x2471 z2472 = x2472 z2473 = x2473 z2474 = x2474 z2475 = x2475 z2476 = x2476 z2477 = x2477 z2478 = x2478 z2479 = x2479 z2480 = x2480 z2481 = x2481 z2482 = x2482 z2483 = x2483 z2484 = x2484 z2485 = x2485 z2486 = x2486 z2487 = x2487 z2488 = x2488 z2489 = x2489 z2490 = x2490 z2491 = x2491 z2492 = x2492 z2493 = x2493 z2494 = x2494 z2495 = x2495 z2496 = x2496 z2497 = x2497 z2498 = x2498 z2499 = x2499 z2500 = x2500 z2501 = x2501 z2502 = x2502 z2503 = x2503 z2504 = x2504 z2505 = x2505 z2506 = x2506 z2507 = x2507 z2508 = x2508 z2509 = x2509 z2510 = x2510 z2511 = x2511 z2512 = x2512 z2513 = x2513 z2514 = x2514 z2515 = x2515 z2516 = x2516 z2517 = x2517 z2518 = x2518 z2519 = x2519 z2520 = x2520 z2521 = x2521 z2522 = x2522 z2523 = x2523 z2524 = x2524 z2525 = x2525 z2526 = x2526 z2527 = x2527 z2528 = x2528 z2529 = x2529 z2530 = x2530 z2531 = x2531 z2532 = x2532 z2533 = x2533 z2534 = x2534 z2535 = x2535 z2536 = x2536 z2537 = x2537 z2538 = x2538 z2539 = x2539 z2540 = x2540 z2541 = x2541 z2542 = x2542 z2543 = x2543 z2544 = x2544 z2545 = x2545 z2546 = x2546 z2547 = x2547 z2548 = x2548 z2549 = x2549 z2550 = x2550 z2551 = x2551 z2552 = x2552 z2553 = x2553 z2554 = x2554 z2555 = x2555 z2556 = x2556 z2557 = x2557 z2558 = x2558 z2559 = x2559 z2560 = x2560 z2561 = x2561 z2562 = x2562 z2563 = x2563 z2564 = x2564 z2565 = x2565 z2566 = x2566 z2567 = x2567 z2568 = x2568 z2569 = x2569 z2570 = x2570 z2571 = x2571 z2572 = x2572 z2573 = x2573 z2574 = x2574 z2575 = x2575 z2576 = x2576 z2577 = x2577 z2578 = x2578 z2579 = x2579 z2580 = x2580 z2581 = x2581 z2582 = x2582 z2583 = x2583 z2584 = x2584 z2585 = x2585 z2586 = x2586 z2587 = x2587 z2588 = x2588 z2589 = x2589 z2590 = x2590 z2591 = x2591 z2592 = x2592 z2593 = x2593 z2594 = x2594 z2595 = x2595 z2596 = x2596 z2597 = x2597 z2598 = x2598 z2599 = x2599 z2600 = x2600 z2601 = x2601 z2602 = x2602 z2603 = x2603 z2604 = x2604 z2605 = x2605 z2606 = x2606 z2607 = x2607 z2608 = x2608 z2609 = x2609 z2610 = x2610 z2611 = x2611 z2612 = x2612 z2613 = x2613 z2614 = x2614 z2615 = x2615 z2616 = x2616 z2617 = x2617 z2618 = x2618 z2619 = x2619 z2620 = x2620 z2621 = x2621 z2622 = x2622 z2623 = x2623 z2624 = x2624 z2625 = x2625 z2626 = x2626 z2627 = x2627 z2628 = x2628 z2629 = x2629 z2630 = x2630 z2631 = x2631 z2632 = x2632 z2633 = x2633 z2634 = x2634 z2635 = x2635 z2636 = x2636 z2637 = x2637 z2638 = x2638 z2639 = x2639 z2640 = x2640 z2641 = x2641 z2642 = x2642 z2643 = x2643 z2644 = x2644 z2645 = x2645 z2646 = x2646 z2647 = x2647 z2648 = x2648 z2649 = x2649 z2650 = x2650 z2651 = x2651 z2652 = x2652 z2653 = x2653 z2654 = x2654 z2655 = x2655 z2656 = x2656 z2657 = x2657 z2658 = x2658 z2659 = x2659 z2660 = x2660 z2661 = x2661 z2662 = x2662 z2663 = x2663 z2664 = x2664 z2665 = x2665 z2666 = x2666 z2667 = x2667 z2668 = x2668 z2669 = x2669 z2670 = x2670 z2671 = x2671 z2672 = x2672 z2673 = x2673 z2674 = x2674 z2675 = x2675 z2676 = x2676 z2677 = x2677 z2678 = x2678 z2679 = x2679 z2680 = x2680 z2681 = x2681 z2682 = x2682 z2683 = x2683 z2684 = x2684 z2685 = x2685 z2686 = x2686 z2687 = x2687 z2688 = x2688 z2689 = x2689 z2690 = x2690 z2691 = x2691 z2692 = x2692 z2693 = x2693 z2694 = x2694 z2695 = x2695 z2696 = x2696 z2697 = x2697 z2698 = x2698 z2699 = x2699 z2700 = x2700 z2701 = x2701 z2702 = x2702 z2703 = x2703 z2704 = x2704 z2705 = x2705 z2706 = x2706 z2707 = x2707 z2708 = x2708 z2709 = x2709 z2710 = x2710 z2711 = x2711 z2712 = x2712 z2713 = x2713 z2714 = x2714 z2715 = x2715 z2716 = x2716 z2717 = x2717 z2718 = x2718 z2719 = x2719 z2720 = x2720 z2721 = x2721 z2722 = x2722 z2723 = x2723 z2724 = x2724 z2725 = x2725 z2726 = x2726 z2727 = x2727 z2728 = x2728 z2729 = x2729 z2730 = x2730 z2731 = x2731 z2732 = x2732 z2733 = x2733 z2734 = x2734 z2735 = x2735 z2736 = x2736 z2737 = x2737 z2738 = x2738 z2739 = x2739 z2740 = x2740 z2741 = x2741 z2742 = x2742 z2743 = x2743 z2744 = x2744 z2745 = x2745 z2746 = x2746 z2747 = x2747 z2748 = x2748 z2749 = x2749 z2750 = x2750 z2751 = x2751 z2752 = x2752 z2753 = x2753 z2754 = x2754 z2755 = x2755 z2756 = x2756 z2757 = x2757 z2758 = x2758 z2759 = x2759 z2760 = x2760 z2761 = x2761 z2762 = x2762 z2763 = x2763 z2764 = x2764 z2765 = x2765 z2766 = x2766 z2767 = x2767 z2768 = x2768 z2769 = x2769 z2770 = x2770 z2771 = x2771 z2772 = x2772 z2773 = x2773 z2774 = x2774 z2775 = x2775 z2776 = x2776 z2777 = x2777 z2778 = x2778 z2779 = x2779 z2780 = x2780 z2781 = x2781 z2782 = x2782 z2783 = x2783 z2784 = x2784 z2785 = x2785 z2786 = x2786 z2787 = x2787 z2788 = x2788 z2789 = x2789 z2790 = x2790 z2791 = x2791 z2792 = x2792 z2793 = x2793 z2794 = x2794 z2795 = x2795 z2796 = x2796 z2797 = x2797 z2798 = x2798 z2799 = x2799 z2800 = x2800 z2801 = x2801 z2802 = x2802 z2803 = x2803 z2804 = x2804 z2805 = x2805 z2806 = x2806 z2807 = x2807 z2808 = x2808 z2809 = x2809 z2810 = x2810 z2811 = x2811 z2812 = x2812 z2813 = x2813 z2814 = x2814 z2815 = x2815 z2816 = x2816 z2817 = x2817 z2818 = x2818 z2819 = x2819 z2820 = x2820 z2821 = x2821 z2822 = x2822 z2823 = x2823 z2824 = x2824 z2825 = x2825 z2826 = x2826 z2827 = x2827 z2828 = x2828 z2829 = x2829 z2830 = x2830 z2831 = x2831 z2832 = x2832 z2833 = x2833 z2834 = x2834 z2835 = x2835 z2836 = x2836 z2837 = x2837 z2838 = x2838 z2839 = x2839 z2840 = x2840 z2841 = x2841 z2842 = x2842 z2843 = x2843 z2844 = x2844 z2845 = x2845 z2846 = x2846 z2847 = x2847 z2848 = x2848 z2849 = x2849 z2850 = x2850 z2851 = x2851 z2852 = x2852 z2853 = x2853 z2854 = x2854 z2855 = x2855 z2856 = x2856 z2857 = x2857 z2858 = x2858 z2859 = x2859 z2860 = x2860 z2861 = x2861 z2862 = x2862 z2863 = x2863 z2864 = x2864 z2865 = x2865 z2866 = x2866 z2867 = x2867 z2868 = x2868 z2869 = x2869 z2870 = x2870 z2871 = x2871 z2872 = x2872 z2873 = x2873 z2874 = x2874 z2875 = x2875 z2876 = x2876 z2877 = x2877 z2878 = x2878 z2879 = x2879 z2880 = x2880 z2881 = x2881 z2882 = x2882 z2883 = x2883 z2884 = x2884 z2885 = x2885 z2886 = x2886 z2887 = x2887 z2888 = x2888 z2889 = x2889 z2890 = x2890 z2891 = x2891 z2892 = x2892 z2893 = x2893 z2894 = x2894 z2895 = x2895 z2896 = x2896 z2897 = x2897 z2898 = x2898 z2899 = x2899 z2900 = x2900 z2901 = x2901 z2902 = x2902 z2903 = x2903 z2904 = x2904 z2905 = x2905 z2906 = x2906 z2907 = x2907 z2908 = x2908 z2909 = x2909 z2910 = x2910 z2911 = x2911 z2912 = x2912 z2913 = x2913 z2914 = x2914 z2915 = x2915 z2916 = x2916 z2917 = x2917 z2918 = x2918 z2919 = x2919 z2920 = x2920 z2921 = x2921 z2922 = x2922 z2923 = x2923 z2924 = x2924 z2925 = x2925 z2926 = x2926 z2927 = x2927 z2928 = x2928 z2929 = x2929 z2930 = x2930 z2931 = x2931 z2932 = x2932 z2933 = x2933 z2934 = x2934 z2935 = x2935 z2936 = x2936 z2937 = x2937 z2938 = x2938 z2939 = x2939 z2940 = x2940 z2941 = x2941 z2942 = x2942 z2943 = x2943 z2944 = x2944 z2945 = x2945 z2946 = x2946 z2947 = x2947 z2948 = x2948 z2949 = x2949 z2950 = x2950 z2951 = x2951 z2952 = x2952 z2953 = x2953 z2954 = x2954 z2955 = x2955 z2956 = x2956 z2957 = x2957 z2958 = x2958 z2959 = x2959 z2960 = x2960 z2961 = x2961 z2962 = x2962 z2963 = x2963 z2964 = x2964 z2965 = x2965 z2966 = x2966 z2967 = x2967 z2968 = x2968 z2969 = x2969 z2970 = x2970 z2971 = x2971 z2972 = x2972 z2973 = x2973 z2974 = x2974 z2975 = x2975 z2976 = x2976 z2977 = x2977 z2978 = x2978 z2979 = x2979 z2980 = x2980 z2981 = x2981 z2982 = x2982 z2983 = x2983 z2984 = x2984 z2985 = x2985 z2986 = x2986 z2987 = x2987 z2988 = x2988 z2989 = x2989 z2990 = x2990 z2991 = x2991 z2992 = x2992 z2993 = x2993 z2994 = x2994 z2995 = x2995 z2996 = x2996 z2997 = x2997 z2998 = x2998 z2999 = x2999 z3000 = x3000 z3001 = x3001 z3002 = x3002 z3003 = x3003 z3004 = x3004 z3005 = x3005 z3006 = x3006 z3007 = x3007 z3008 = x3008 z3009 = x3009 z3010 = x3010 z3011 = x3011 z3012 = x3012 z3013 = x3013 z3014 = x3014 z3015 = x3015 z3016 = x3016 z3017 = x3017 z3018 = x3018 z3019 = x3019 z3020 = x3020 z3021 = x3021 z3022 = x3022 z3023 = x3023 z3024 = x3024 z3025 = x3025 z3026 = x3026 z3027 = x3027 z3028 = x3028 z3029 = x3029 z3030 = x3030 z3031 = x3031 z3032 = x3032 z3033 = x3033 z3034 = x3034 z3035 = x3035 z3036 = x3036 z3037 = x3037 z3038 = x3038 z3039 = x3039 z3040 = x3040 z3041 = x3041 z3042 = x3042 z3043 = x3043 z3044 = x3044 z3045 = x3045 z3046 = x3046 z3047 = x3047 z3048 = x3048 z3049 = x3049 z3050 = x3050 z3051 = x3051 z3052 = x3052 z3053 = x3053 z3054 = x3054 z3055 = x3055 z3056 = x3056 z3057 = x3057 z3058 = x3058 z3059 = x3059 z3060 = x3060 z3061 = x3061 z3062 = x3062 z3063 = x3063 z3064 = x3064 z3065 = x3065 z3066 = x3066 z3067 = x3067 z3068 = x3068 z3069 = x3069 z3070 = x3070 z3071 = x3071 z3072 = x3072 z3073 = x3073 z3074 = x3074 z3075 = x3075 z3076 = x3076 z3077 = x3077 z3078 = x3078 z3079 = x3079 z3080 = x3080 z3081 = x3081 z3082 = x3082 z3083 = x3083 z3084 = x3084 z3085 = x3085 z3086 = x3086 z3087 = x3087 z3088 = x3088 z3089 = x3089 z3090 = x3090 z3091 = x3091 z3092 = x3092 z3093 = x3093 z3094 = x3094 z3095 = x3095 z3096 = x3096 z3097 = x3097 z3098 = x3098 z3099 = x3099 z3100 = x3100 z3101 = x3101 z3102 = x3102 z3103 = x3103 z3104 = x3104 z3105 = x3105 z3106 = x3106 z3107 = x3107 z3108 = x3108 z3109 = x3109 z3110 = x3110 z3111 = x3111 z3112 = x3112 z3113 = x3113 z3114 = x3114 z3115 = x3115 z3116 = x3116 z3117 = x3117 z3118 = x3118 z3119 = x3119 z3120 = x3120 z3121 = x3121 z3122 = x3122 z3123 = x3123 z3124 = x3124 z3125 = x3125 z3126 = x3126 z3127 = x3127 z3128 = x3128 z3129 = x3129 z3130 = x3130 z3131 = x3131 z3132 = x3132 z3133 = x3133 z3134 = x3134 z3135 = x3135 z3136 = x3136 z3137 = x3137 z3138 = x3138 z3139 = x3139 z3140 = x3140 z3141 = x3141 z3142 = x3142 z3143 = x3143 z3144 = x3144 z3145 = x3145 z3146 = x3146 z3147 = x3147 z3148 = x3148 z3149 = x3149 z3150 = x3150 z3151 = x3151 z3152 = x3152 z3153 = x3153 z3154 = x3154 z3155 = x3155 z3156 = x3156 z3157 = x3157 z3158 = x3158 z3159 = x3159 z3160 = x3160 z3161 = x3161 z3162 = x3162 z3163 = x3163 z3164 = x3164 z3165 = x3165 z3166 = x3166 z3167 = x3167 z3168 = x3168 z3169 = x3169 z3170 = x3170 z3171 = x3171 z3172 = x3172 z3173 = x3173 z3174 = x3174 z3175 = x3175 z3176 = x3176 z3177 = x3177 z3178 = x3178 z3179 = x3179 z3180 = x3180 z3181 = x3181 z3182 = x3182 z3183 = x3183 z3184 = x3184 z3185 = x3185 z3186 = x3186 z3187 = x3187 z3188 = x3188 z3189 = x3189 z3190 = x3190 z3191 = x3191 z3192 = x3192 z3193 = x3193 z3194 = x3194 z3195 = x3195 z3196 = x3196 z3197 = x3197 z3198 = x3198 z3199 = x3199 z3200 = x3200 z3201 = x3201 z3202 = x3202 z3203 = x3203 z3204 = x3204 z3205 = x3205 z3206 = x3206 z3207 = x3207 z3208 = x3208 z3209 = x3209 z3210 = x3210 z3211 = x3211 z3212 = x3212 z3213 = x3213 z3214 = x3214 z3215 = x3215 z3216 = x3216 z3217 = x3217 z3218 = x3218 z3219 = x3219 z3220 = x3220 z3221 = x3221 z3222 = x3222 z3223 = x3223 z3224 = x3224 z3225 = x3225 z3226 = x3226 z3227 = x3227 z3228 = x3228 z3229 = x3229 z3230 = x3230 z3231 = x3231 z3232 = x3232 z3233 = x3233 z3234 = x3234 z3235 = x3235 z3236 = x3236 z3237 = x3237 z3238 = x3238 z3239 = x3239 z3240 = x3240 z3241 = x3241 z3242 = x3242 z3243 = x3243 z3244 = x3244 z3245 = x3245 z3246 = x3246 z3247 = x3247 z3248 = x3248 z3249 = x3249 z3250 = x3250 z3251 = x3251 z3252 = x3252 z3253 = x3253 z3254 = x3254 z3255 = x3255 z3256 = x3256 z3257 = x3257 z3258 = x3258 z3259 = x3259 z3260 = x3260 z3261 = x3261 z3262 = x3262 z3263 = x3263 z3264 = x3264 z3265 = x3265 z3266 = x3266 z3267 = x3267 z3268 = x3268 z3269 = x3269 z3270 = x3270 z3271 = x3271 z3272 = x3272 z3273 = x3273 z3274 = x3274 z3275 = x3275 z3276 = x3276 z3277 = x3277 z3278 = x3278 z3279 = x3279 z3280 = x3280 z3281 = x3281 z3282 = x3282 z3283 = x3283 z3284 = x3284 z3285 = x3285 z3286 = x3286 z3287 = x3287 z3288 = x3288 z3289 = x3289 z3290 = x3290 z3291 = x3291 z3292 = x3292 z3293 = x3293 z3294 = x3294 z3295 = x3295 z3296 = x3296 z3297 = x3297 z3298 = x3298 z3299 = x3299 z3300 = x3300 z3301 = x3301 z3302 = x3302 z3303 = x3303 z3304 = x3304 z3305 = x3305 z3306 = x3306 z3307 = x3307 z3308 = x3308 z3309 = x3309 z3310 = x3310 z3311 = x3311 z3312 = x3312 z3313 = x3313 z3314 = x3314 z3315 = x3315 z3316 = x3316 z3317 = x3317 z3318 = x3318 z3319 = x3319 z3320 = x3320 z3321 = x3321 z3322 = x3322 z3323 = x3323 z3324 = x3324 z3325 = x3325 z3326 = x3326 z3327 = x3327 z3328 = x3328 z3329 = x3329 z3330 = x3330 z3331 = x3331 z3332 = x3332 z3333 = x3333 z3334 = x3334 z3335 = x3335 z3336 = x3336 z3337 = x3337 z3338 = x3338 z3339 = x3339 z3340 = x3340 z3341 = x3341 z3342 = x3342 z3343 = x3343 z3344 = x3344 z3345 = x3345 z3346 = x3346 z3347 = x3347 z3348 = x3348 z3349 = x3349 z3350 = x3350 z3351 = x3351 z3352 = x3352 z3353 = x3353 z3354 = x3354 z3355 = x3355 z3356 = x3356 z3357 = x3357 z3358 = x3358 z3359 = x3359 z3360 = x3360 z3361 = x3361 z3362 = x3362 z3363 = x3363 z3364 = x3364 z3365 = x3365 z3366 = x3366 z3367 = x3367 z3368 = x3368 z3369 = x3369 z3370 = x3370 z3371 = x3371 z3372 = x3372 z3373 = x3373 z3374 = x3374 z3375 = x3375 z3376 = x3376 z3377 = x3377 z3378 = x3378 z3379 = x3379 z3380 = x3380 z3381 = x3381 z3382 = x3382 z3383 = x3383 z3384 = x3384 z3385 = x3385 z3386 = x3386 z3387 = x3387 z3388 = x3388 z3389 = x3389 z3390 = x3390 z3391 = x3391 z3392 = x3392 z3393 = x3393 z3394 = x3394 z3395 = x3395 z3396 = x3396 z3397 = x3397 z3398 = x3398 z3399 = x3399 z3400 = x3400 z3401 = x3401 z3402 = x3402 z3403 = x3403 z3404 = x3404 z3405 = x3405 z3406 = x3406 z3407 = x3407 z3408 = x3408 z3409 = x3409 z3410 = x3410 z3411 = x3411 z3412 = x3412 z3413 = x3413 z3414 = x3414 z3415 = x3415 z3416 = x3416 z3417 = x3417 z3418 = x3418 z3419 = x3419 z3420 = x3420 z3421 = x3421 z3422 = x3422 z3423 = x3423 z3424 = x3424 z3425 = x3425 z3426 = x3426 z3427 = x3427 z3428 = x3428 z3429 = x3429 z3430 = x3430 z3431 = x3431 z3432 = x3432 z3433 = x3433 z3434 = x3434 z3435 = x3435 z3436 = x3436 z3437 = x3437 z3438 = x3438 z3439 = x3439 z3440 = x3440 z3441 = x3441 z3442 = x3442 z3443 = x3443 z3444 = x3444 z3445 = x3445 z3446 = x3446 z3447 = x3447 z3448 = x3448 z3449 = x3449 z3450 = x3450 z3451 = x3451 z3452 = x3452 z3453 = x3453 z3454 = x3454 z3455 = x3455 z3456 = x3456 z3457 = x3457 z3458 = x3458 z3459 = x3459 z3460 = x3460 z3461 = x3461 z3462 = x3462 z3463 = x3463 z3464 = x3464 z3465 = x3465 z3466 = x3466 z3467 = x3467 z3468 = x3468 z3469 = x3469 z3470 = x3470 z3471 = x3471 z3472 = x3472 z3473 = x3473 z3474 = x3474 z3475 = x3475 z3476 = x3476 z3477 = x3477 z3478 = x3478 z3479 = x3479 z3480 = x3480 z3481 = x3481 z3482 = x3482 z3483 = x3483 z3484 = x3484 z3485 = x3485 z3486 = x3486 z3487 = x3487 z3488 = x3488 z3489 = x3489 z3490 = x3490 z3491 = x3491 z3492 = x3492 z3493 = x3493 z3494 = x3494 z3495 = x3495 z3496 = x3496 z3497 = x3497 z3498 = x3498 z3499 = x3499 z3500 = x3500 z3501 = x3501 z3502 = x3502 z3503 = x3503 z3504 = x3504 z3505 = x3505 z3506 = x3506 z3507 = x3507 z3508 = x3508 z3509 = x3509 z3510 = x3510 z3511 = x3511 z3512 = x3512 z3513 = x3513 z3514 = x3514 z3515 = x3515 z3516 = x3516 z3517 = x3517 z3518 = x3518 z3519 = x3519 z3520 = x3520 z3521 = x3521 z3522 = x3522 z3523 = x3523 z3524 = x3524 z3525 = x3525 z3526 = x3526 z3527 = x3527 z3528 = x3528 z3529 = x3529 z3530 = x3530 z3531 = x3531 z3532 = x3532 z3533 = x3533 z3534 = x3534 z3535 = x3535 z3536 = x3536 z3537 = x3537 z3538 = x3538 z3539 = x3539 z3540 = x3540 z3541 = x3541 z3542 = x3542 z3543 = x3543 z3544 = x3544 z3545 = x3545 z3546 = x3546 z3547 = x3547 z3548 = x3548 z3549 = x3549 z3550 = x3550 z3551 = x3551 z3552 = x3552 z3553 = x3553 z3554 = x3554 z3555 = x3555 z3556 = x3556 z3557 = x3557 z3558 = x3558 z3559 = x3559 z3560 = x3560 z3561 = x3561 z3562 = x3562 z3563 = x3563 z3564 = x3564 z3565 = x3565 z3566 = x3566 z3567 = x3567 z3568 = x3568 z3569 = x3569 z3570 = x3570 z3571 = x3571 z3572 = x3572 z3573 = x3573 z3574 = x3574 z3575 = x3575 z3576 = x3576 z3577 = x3577 z3578 = x3578 z3579 = x3579 z3580 = x3580 z3581 = x3581 z3582 = x3582 z3583 = x3583 z3584 = x3584 z3585 = x3585 z3586 = x3586 z3587 = x3587 z3588 = x3588 z3589 = x3589 z3590 = x3590 z3591 = x3591 z3592 = x3592 z3593 = x3593 z3594 = x3594 z3595 = x3595 z3596 = x3596 z3597 = x3597 z3598 = x3598 z3599 = x3599 z3600 = x3600 z3601 = x3601 z3602 = x3602 z3603 = x3603 z3604 = x3604 z3605 = x3605 z3606 = x3606 z3607 = x3607 z3608 = x3608 z3609 = x3609 z3610 = x3610 z3611 = x3611 z3612 = x3612 z3613 = x3613 z3614 = x3614 z3615 = x3615 z3616 = x3616 z3617 = x3617 z3618 = x3618 z3619 = x3619 z3620 = x3620 z3621 = x3621 z3622 = x3622 z3623 = x3623 z3624 = x3624 z3625 = x3625 z3626 = x3626 z3627 = x3627 z3628 = x3628 z3629 = x3629 z3630 = x3630 z3631 = x3631 z3632 = x3632 z3633 = x3633 z3634 = x3634 z3635 = x3635 z3636 = x3636 z3637 = x3637 z3638 = x3638 z3639 = x3639 z3640 = x3640 z3641 = x3641 z3642 = x3642 z3643 = x3643 z3644 = x3644 z3645 = x3645 z3646 = x3646 z3647 = x3647 z3648 = x3648 z3649 = x3649 z3650 = x3650 z3651 = x3651 z3652 = x3652 z3653 = x3653 z3654 = x3654 z3655 = x3655 z3656 = x3656 z3657 = x3657 z3658 = x3658 z3659 = x3659 z3660 = x3660 z3661 = x3661 z3662 = x3662 z3663 = x3663 z3664 = x3664 z3665 = x3665 z3666 = x3666 z3667 = x3667 z3668 = x3668 z3669 = x3669 z3670 = x3670 z3671 = x3671 z3672 = x3672 z3673 = x3673 z3674 = x3674 z3675 = x3675 z3676 = x3676 z3677 = x3677 z3678 = x3678 z3679 = x3679 z3680 = x3680 z3681 = x3681 z3682 = x3682 z3683 = x3683 z3684 = x3684 z3685 = x3685 z3686 = x3686 z3687 = x3687 z3688 = x3688 z3689 = x3689 z3690 = x3690 z3691 = x3691 z3692 = x3692 z3693 = x3693 z3694 = x3694 z3695 = x3695 z3696 = x3696 z3697 = x3697 z3698 = x3698 z3699 = x3699 z3700 = x3700 z3701 = x3701 z3702 = x3702 z3703 = x3703 z3704 = x3704 z3705 = x3705 z3706 = x3706 z3707 = x3707 z3708 = x3708 z3709 = x3709 z3710 = x3710 z3711 = x3711 z3712 = x3712 z3713 = x3713 z3714 = x3714 z3715 = x3715 z3716 = x3716 z3717 = x3717 z3718 = x3718 z3719 = x3719 z3720 = x3720 z3721 = x3721 z3722 = x3722 z3723 = x3723 z3724 = x3724 z3725 = x3725 z3726 = x3726 z3727 = x3727 z3728 = x3728 z3729 = x3729 z3730 = x3730 z3731 = x3731 z3732 = x3732 z3733 = x3733 z3734 = x3734 z3735 = x3735 z3736 = x3736 z3737 = x3737 z3738 = x3738 z3739 = x3739 z3740 = x3740 z3741 = x3741 z3742 = x3742 z3743 = x3743 z3744 = x3744 z3745 = x3745 z3746 = x3746 z3747 = x3747 z3748 = x3748 z3749 = x3749 z3750 = x3750 z3751 = x3751 z3752 = x3752 z3753 = x3753 z3754 = x3754 z3755 = x3755 z3756 = x3756 z3757 = x3757 z3758 = x3758 z3759 = x3759 z3760 = x3760 z3761 = x3761 z3762 = x3762 z3763 = x3763 z3764 = x3764 z3765 = x3765 z3766 = x3766 z3767 = x3767 z3768 = x3768 z3769 = x3769 z3770 = x3770 z3771 = x3771 z3772 = x3772 z3773 = x3773 z3774 = x3774 z3775 = x3775 z3776 = x3776 z3777 = x3777 z3778 = x3778 z3779 = x3779 z3780 = x3780 z3781 = x3781 z3782 = x3782 z3783 = x3783 z3784 = x3784 z3785 = x3785 z3786 = x3786 z3787 = x3787 z3788 = x3788 z3789 = x3789 z3790 = x3790 z3791 = x3791 z3792 = x3792 z3793 = x3793 z3794 = x3794 z3795 = x3795 z3796 = x3796 z3797 = x3797 z3798 = x3798 z3799 = x3799 z3800 = x3800 z3801 = x3801 z3802 = x3802 z3803 = x3803 z3804 = x3804 z3805 = x3805 z3806 = x3806 z3807 = x3807 z3808 = x3808 z3809 = x3809 z3810 = x3810 z3811 = x3811 z3812 = x3812 z3813 = x3813 z3814 = x3814 z3815 = x3815 z3816 = x3816 z3817 = x3817 z3818 = x3818 z3819 = x3819 z3820 = x3820 z3821 = x3821 z3822 = x3822 z3823 = x3823 z3824 = x3824 z3825 = x3825 z3826 = x3826 z3827 = x3827 z3828 = x3828 z3829 = x3829 z3830 = x3830 z3831 = x3831 z3832 = x3832 z3833 = x3833 z3834 = x3834 z3835 = x3835 z3836 = x3836 z3837 = x3837 z3838 = x3838 z3839 = x3839 z3840 = x3840 z3841 = x3841 z3842 = x3842 z3843 = x3843 z3844 = x3844 z3845 = x3845 z3846 = x3846 z3847 = x3847 z3848 = x3848 z3849 = x3849 z3850 = x3850 z3851 = x3851 z3852 = x3852 z3853 = x3853 z3854 = x3854 z3855 = x3855 z3856 = x3856 z3857 = x3857 z3858 = x3858 z3859 = x3859 z3860 = x3860 z3861 = x3861 z3862 = x3862 z3863 = x3863 z3864 = x3864 z3865 = x3865 z3866 = x3866 z3867 = x3867 z3868 = x3868 z3869 = x3869 z3870 = x3870 z3871 = x3871 z3872 = x3872 z3873 = x3873 z3874 = x3874 z3875 = x3875 z3876 = x3876 z3877 = x3877 z3878 = x3878 z3879 = x3879 z3880 = x3880 z3881 = x3881 z3882 = x3882 z3883 = x3883 z3884 = x3884 z3885 = x3885 z3886 = x3886 z3887 = x3887 z3888 = x3888 z3889 = x3889 z3890 = x3890 z3891 = x3891 z3892 = x3892 z3893 = x3893 z3894 = x3894 z3895 = x3895 z3896 = x3896 z3897 = x3897 z3898 = x3898 z3899 = x3899 z3900 = x3900 z3901 = x3901 z3902 = x3902 z3903 = x3903 z3904 = x3904 z3905 = x3905 z3906 = x3906 z3907 = x3907 z3908 = x3908 z3909 = x3909 z3910 = x3910 z3911 = x3911 z3912 = x3912 z3913 = x3913 z3914 = x3914 z3915 = x3915 z3916 = x3916 z3917 = x3917 z3918 = x3918 z3919 = x3919 z3920 = x3920 z3921 = x3921 z3922 = x3922 z3923 = x3923 z3924 = x3924 z3925 = x3925 z3926 = x3926 z3927 = x3927 z3928 = x3928 z3929 = x3929 z3930 = x3930 z3931 = x3931 z3932 = x3932 z3933 = x3933 z3934 = x3934 z3935 = x3935 z3936 = x3936 z3937 = x3937 z3938 = x3938 z3939 = x3939 z3940 = x3940 z3941 = x3941 z3942 = x3942 z3943 = x3943 z3944 = x3944 z3945 = x3945 z3946 = x3946 z3947 = x3947 z3948 = x3948 z3949 = x3949 z3950 = x3950 z3951 = x3951 z3952 = x3952 z3953 = x3953 z3954 = x3954 z3955 = x3955 z3956 = x3956 z3957 = x3957 z3958 = x3958 z3959 = x3959 z3960 = x3960 z3961 = x3961 z3962 = x3962 z3963 = x3963 z3964 = x3964 z3965 = x3965 z3966 = x3966 z3967 = x3967 z3968 = x3968 z3969 = x3969 z3970 = x3970 z3971 = x3971 z3972 = x3972 z3973 = x3973 z3974 = x3974 z3975 = x3975 z3976 = x3976 z3977 = x3977 z3978 = x3978 z3979 = x3979 z3980 = x3980 z3981 = x3981 z3982 = x3982 z3983 = x3983 z3984 = x3984 z3985 = x3985 z3986 = x3986 z3987 = x3987 z3988 = x3988 z3989 = x3989 z3990 = x3990 z3991 = x3991 z3992 = x3992 z3993 = x3993 z3994 = x3994 z3995 = x3995 z3996 = x3996 z3997 = x3997 z3998 = x3998 z3999 = x3999 z4000 = x4000 z4001 = x4001 z4002 = x4002 z4003 = x4003 z4004 = x4004 z4005 = x4005 z4006 = x4006 z4007 = x4007 z4008 = x4008 z4009 = x4009 z4010 = x4010 z4011 = x4011 z4012 = x4012 z4013 = x4013 z4014 = x4014 z4015 = x4015 z4016 = x4016 z4017 = x4017 z4018 = x4018 z4019 = x4019 z4020 = x4020 z4021 = x4021 z4022 = x4022 z4023 = x4023 z4024 = x4024 z4025 = x4025 z4026 = x4026 z4027 = x4027 z4028 = x4028 z4029 = x4029 z4030 = x4030 z4031 = x4031 z4032 = x4032 z4033 = x4033 z4034 = x4034 z4035 = x4035 z4036 = x4036 z4037 = x4037 z4038 = x4038 z4039 = x4039 z4040 = x4040 z4041 = x4041 z4042 = x4042 z4043 = x4043 z4044 = x4044 z4045 = x4045 z4046 = x4046 z4047 = x4047 z4048 = x4048 z4049 = x4049 z4050 = x4050 z4051 = x4051 z4052 = x4052 z4053 = x4053 z4054 = x4054 z4055 = x4055 z4056 = x4056 z4057 = x4057 z4058 = x4058 z4059 = x4059 z4060 = x4060 z4061 = x4061 z4062 = x4062 z4063 = x4063 z4064 = x4064 z4065 = x4065 z4066 = x4066 z4067 = x4067 z4068 = x4068 z4069 = x4069 z4070 = x4070 z4071 = x4071 z4072 = x4072 z4073 = x4073 z4074 = x4074 z4075 = x4075 z4076 = x4076 z4077 = x4077 z4078 = x4078 z4079 = x4079 z4080 = x4080 z4081 = x4081 z4082 = x4082 z4083 = x4083 z4084 = x4084 z4085 = x4085 z4086 = x4086 z4087 = x4087 z4088 = x4088 z4089 = x4089 z4090 = x4090 z4091 = x4091 z4092 = x4092 z4093 = x4093 z4094 = x4094 z4095 = x4095 z4096 = x4096 z4097 = x4097 z4098 = x4098 z4099 = x4099 z4100 = x4100 z4101 = x4101 z4102 = x4102 z4103 = x4103 z4104 = x4104 z4105 = x4105 z4106 = x4106 z4107 = x4107 z4108 = x4108 z4109 = x4109 z4110 = x4110 z4111 = x4111 z4112 = x4112 z4113 = x4113 z4114 = x4114 z4115 = x4115 z4116 = x4116 z4117 = x4117 z4118 = x4118 z4119 = x4119 z4120 = x4120 z4121 = x4121 z4122 = x4122 z4123 = x4123 z4124 = x4124 z4125 = x4125 z4126 = x4126 z4127 = x4127 z4128 = x4128 z4129 = x4129 z4130 = x4130 z4131 = x4131 z4132 = x4132 z4133 = x4133 z4134 = x4134 z4135 = x4135 z4136 = x4136 z4137 = x4137 z4138 = x4138 z4139 = x4139 z4140 = x4140 z4141 = x4141 z4142 = x4142 z4143 = x4143 z4144 = x4144 z4145 = x4145 z4146 = x4146 z4147 = x4147 z4148 = x4148 z4149 = x4149 z4150 = x4150 z4151 = x4151 z4152 = x4152 z4153 = x4153 z4154 = x4154 z4155 = x4155 z4156 = x4156 z4157 = x4157 z4158 = x4158 z4159 = x4159 z4160 = x4160 z4161 = x4161 z4162 = x4162 z4163 = x4163 z4164 = x4164 z4165 = x4165 z4166 = x4166 z4167 = x4167 z4168 = x4168 z4169 = x4169 z4170 = x4170 z4171 = x4171 z4172 = x4172 z4173 = x4173 z4174 = x4174 z4175 = x4175 z4176 = x4176 z4177 = x4177 z4178 = x4178 z4179 = x4179 z4180 = x4180 z4181 = x4181 z4182 = x4182 z4183 = x4183 z4184 = x4184 z4185 = x4185 z4186 = x4186 z4187 = x4187 z4188 = x4188 z4189 = x4189 z4190 = x4190 z4191 = x4191 z4192 = x4192 z4193 = x4193 z4194 = x4194 z4195 = x4195 z4196 = x4196 z4197 = x4197 z4198 = x4198 z4199 = x4199 z4200 = x4200 z4201 = x4201 z4202 = x4202 z4203 = x4203 z4204 = x4204 z4205 = x4205 z4206 = x4206 z4207 = x4207 z4208 = x4208 z4209 = x4209 z4210 = x4210 z4211 = x4211 z4212 = x4212 z4213 = x4213 z4214 = x4214 z4215 = x4215 z4216 = x4216 z4217 = x4217 z4218 = x4218 z4219 = x4219 z4220 = x4220 z4221 = x4221 z4222 = x4222 z4223 = x4223 z4224 = x4224 z4225 = x4225 z4226 = x4226 z4227 = x4227 z4228 = x4228 z4229 = x4229 z4230 = x4230 z4231 = x4231 z4232 = x4232 z4233 = x4233 z4234 = x4234 z4235 = x4235 z4236 = x4236 z4237 = x4237 z4238 = x4238 z4239 = x4239 z4240 = x4240 z4241 = x4241 z4242 = x4242 z4243 = x4243 z4244 = x4244 z4245 = x4245 z4246 = x4246 z4247 = x4247 z4248 = x4248 z4249 = x4249 z4250 = x4250 z4251 = x4251 z4252 = x4252 z4253 = x4253 z4254 = x4254 z4255 = x4255 z4256 = x4256 z4257 = x4257 z4258 = x4258 z4259 = x4259 z4260 = x4260 z4261 = x4261 z4262 = x4262 z4263 = x4263 z4264 = x4264 z4265 = x4265 z4266 = x4266 z4267 = x4267 z4268 = x4268 z4269 = x4269 z4270 = x4270 z4271 = x4271 z4272 = x4272 z4273 = x4273 z4274 = x4274 z4275 = x4275 z4276 = x4276 z4277 = x4277 z4278 = x4278 z4279 = x4279 z4280 = x4280 z4281 = x4281 z4282 = x4282 z4283 = x4283 z4284 = x4284 z4285 = x4285 z4286 = x4286 z4287 = x4287 z4288 = x4288 z4289 = x4289 z4290 = x4290 z4291 = x4291 z4292 = x4292 z4293 = x4293 z4294 = x4294 z4295 = x4295 z4296 = x4296 z4297 = x4297 z4298 = x4298 z4299 = x4299 z4300 = x4300 z4301 = x4301 z4302 = x4302 z4303 = x4303 z4304 = x4304 z4305 = x4305 z4306 = x4306 z4307 = x4307 z4308 = x4308 z4309 = x4309 z4310 = x4310 z4311 = x4311 z4312 = x4312 z4313 = x4313 z4314 = x4314 z4315 = x4315 z4316 = x4316 z4317 = x4317 z4318 = x4318 z4319 = x4319 z4320 = x4320 z4321 = x4321 z4322 = x4322 z4323 = x4323 z4324 = x4324 z4325 = x4325 z4326 = x4326 z4327 = x4327 z4328 = x4328 z4329 = x4329 z4330 = x4330 z4331 = x4331 z4332 = x4332 z4333 = x4333 z4334 = x4334 z4335 = x4335 z4336 = x4336 z4337 = x4337 z4338 = x4338 z4339 = x4339 z4340 = x4340 z4341 = x4341 z4342 = x4342 z4343 = x4343 z4344 = x4344 z4345 = x4345 z4346 = x4346 z4347 = x4347 z4348 = x4348 z4349 = x4349 z4350 = x4350 z4351 = x4351 z4352 = x4352 z4353 = x4353 z4354 = x4354 z4355 = x4355 z4356 = x4356 z4357 = x4357 z4358 = x4358 z4359 = x4359 z4360 = x4360 z4361 = x4361 z4362 = x4362 z4363 = x4363 z4364 = x4364 z4365 = x4365 z4366 = x4366 z4367 = x4367 z4368 = x4368 z4369 = x4369 z4370 = x4370 z4371 = x4371 z4372 = x4372 z4373 = x4373 z4374 = x4374 z4375 = x4375 z4376 = x4376 z4377 = x4377 z4378 = x4378 z4379 = x4379 z4380 = x4380 z4381 = x4381 z4382 = x4382 z4383 = x4383 z4384 = x4384 z4385 = x4385 z4386 = x4386 z4387 = x4387 z4388 = x4388 z4389 = x4389 z4390 = x4390 z4391 = x4391 z4392 = x4392 z4393 = x4393 z4394 = x4394 z4395 = x4395 z4396 = x4396 z4397 = x4397 z4398 = x4398 z4399 = x4399 z4400 = x4400 z4401 = x4401 z4402 = x4402 z4403 = x4403 z4404 = x4404 z4405 = x4405 z4406 = x4406 z4407 = x4407 z4408 = x4408 z4409 = x4409 z4410 = x4410 z4411 = x4411 z4412 = x4412 z4413 = x4413 z4414 = x4414 z4415 = x4415 z4416 = x4416 z4417 = x4417 z4418 = x4418 z4419 = x4419 z4420 = x4420 z4421 = x4421 z4422 = x4422 z4423 = x4423 z4424 = x4424 z4425 = x4425 z4426 = x4426 z4427 = x4427 z4428 = x4428 z4429 = x4429 z4430 = x4430 z4431 = x4431 z4432 = x4432 z4433 = x4433 z4434 = x4434 z4435 = x4435 z4436 = x4436 z4437 = x4437 z4438 = x4438 z4439 = x4439 z4440 = x4440 z4441 = x4441 z4442 = x4442 z4443 = x4443 z4444 = x4444 z4445 = x4445 z4446 = x4446 z4447 = x4447 z4448 = x4448 z4449 = x4449 z4450 = x4450 z4451 = x4451 z4452 = x4452 z4453 = x4453 z4454 = x4454 z4455 = x4455 z4456 = x4456 z4457 = x4457 z4458 = x4458 z4459 = x4459 z4460 = x4460 z4461 = x4461 z4462 = x4462 z4463 = x4463 z4464 = x4464 z4465 = x4465 z4466 = x4466 z4467 = x4467 z4468 = x4468 z4469 = x4469 z4470 = x4470 z4471 = x4471 z4472 = x4472 z4473 = x4473 z4474 = x4474 z4475 = x4475 z4476 = x4476 z4477 = x4477 z4478 = x4478 z4479 = x4479 z4480 = x4480 z4481 = x4481 z4482 = x4482 z4483 = x4483 z4484 = x4484 z4485 = x4485 z4486 = x4486 z4487 = x4487 z4488 = x4488 z4489 = x4489 z4490 = x4490 z4491 = x4491 z4492 = x4492 z4493 = x4493 z4494 = x4494 z4495 = x4495 z4496 = x4496 z4497 = x4497 z4498 = x4498 z4499 = x4499 z4500 = x4500 z4501 = x4501 z4502 = x4502 z4503 = x4503 z4504 = x4504 z4505 = x4505 z4506 = x4506 z4507 = x4507 z4508 = x4508 z4509 = x4509 z4510 = x4510 z4511 = x4511 z4512 = x4512 z4513 = x4513 z4514 = x4514 z4515 = x4515 z4516 = x4516 z4517 = x4517 z4518 = x4518 z4519 = x4519 z4520 = x4520 z4521 = x4521 z4522 = x4522 z4523 = x4523 z4524 = x4524 z4525 = x4525 z4526 = x4526 z4527 = x4527 z4528 = x4528 z4529 = x4529 z4530 = x4530 z4531 = x4531 z4532 = x4532 z4533 = x4533 z4534 = x4534 z4535 = x4535 z4536 = x4536 z4537 = x4537 z4538 = x4538 z4539 = x4539 z4540 = x4540 z4541 = x4541 z4542 = x4542 z4543 = x4543 z4544 = x4544 z4545 = x4545 z4546 = x4546 z4547 = x4547 z4548 = x4548 z4549 = x4549 z4550 = x4550 z4551 = x4551 z4552 = x4552 z4553 = x4553 z4554 = x4554 z4555 = x4555 z4556 = x4556 z4557 = x4557 z4558 = x4558 z4559 = x4559 z4560 = x4560 z4561 = x4561 z4562 = x4562 z4563 = x4563 z4564 = x4564 z4565 = x4565 z4566 = x4566 z4567 = x4567 z4568 = x4568 z4569 = x4569 z4570 = x4570 z4571 = x4571 z4572 = x4572 z4573 = x4573 z4574 = x4574 z4575 = x4575 z4576 = x4576 z4577 = x4577 z4578 = x4578 z4579 = x4579 z4580 = x4580 z4581 = x4581 z4582 = x4582 z4583 = x4583 z4584 = x4584 z4585 = x4585 z4586 = x4586 z4587 = x4587 z4588 = x4588 z4589 = x4589 z4590 = x4590 z4591 = x4591 z4592 = x4592 z4593 = x4593 z4594 = x4594 z4595 = x4595 z4596 = x4596 z4597 = x4597 z4598 = x4598 z4599 = x4599 z4600 = x4600 z4601 = x4601 z4602 = x4602 z4603 = x4603 z4604 = x4604 z4605 = x4605 z4606 = x4606 z4607 = x4607 z4608 = x4608 z4609 = x4609 z4610 = x4610 z4611 = x4611 z4612 = x4612 z4613 = x4613 z4614 = x4614 z4615 = x4615 z4616 = x4616 z4617 = x4617 z4618 = x4618 z4619 = x4619 z4620 = x4620 z4621 = x4621 z4622 = x4622 z4623 = x4623 z4624 = x4624 z4625 = x4625 z4626 = x4626 z4627 = x4627 z4628 = x4628 z4629 = x4629 z4630 = x4630 z4631 = x4631 z4632 = x4632 z4633 = x4633 z4634 = x4634 z4635 = x4635 z4636 = x4636 z4637 = x4637 z4638 = x4638 z4639 = x4639 z4640 = x4640 z4641 = x4641 z4642 = x4642 z4643 = x4643 z4644 = x4644 z4645 = x4645 z4646 = x4646 z4647 = x4647 z4648 = x4648 z4649 = x4649 z4650 = x4650 z4651 = x4651 z4652 = x4652 z4653 = x4653 z4654 = x4654 z4655 = x4655 z4656 = x4656 z4657 = x4657 z4658 = x4658 z4659 = x4659 z4660 = x4660 z4661 = x4661 z4662 = x4662 z4663 = x4663 z4664 = x4664 z4665 = x4665 z4666 = x4666 z4667 = x4667 z4668 = x4668 z4669 = x4669 z4670 = x4670 z4671 = x4671 z4672 = x4672 z4673 = x4673 z4674 = x4674 z4675 = x4675 z4676 = x4676 z4677 = x4677 z4678 = x4678 z4679 = x4679 z4680 = x4680 z4681 = x4681 z4682 = x4682 z4683 = x4683 z4684 = x4684 z4685 = x4685 z4686 = x4686 z4687 = x4687 z4688 = x4688 z4689 = x4689 z4690 = x4690 z4691 = x4691 z4692 = x4692 z4693 = x4693 z4694 = x4694 z4695 = x4695 z4696 = x4696 z4697 = x4697 z4698 = x4698 z4699 = x4699 z4700 = x4700 z4701 = x4701 z4702 = x4702 z4703 = x4703 z4704 = x4704 z4705 = x4705 z4706 = x4706 z4707 = x4707 z4708 = x4708 z4709 = x4709 z4710 = x4710 z4711 = x4711 z4712 = x4712 z4713 = x4713 z4714 = x4714 z4715 = x4715 z4716 = x4716 z4717 = x4717 z4718 = x4718 z4719 = x4719 z4720 = x4720 z4721 = x4721 z4722 = x4722 z4723 = x4723 z4724 = x4724 z4725 = x4725 z4726 = x4726 z4727 = x4727 z4728 = x4728 z4729 = x4729 z4730 = x4730 z4731 = x4731 z4732 = x4732 z4733 = x4733 z4734 = x4734 z4735 = x4735 z4736 = x4736 z4737 = x4737 z4738 = x4738 z4739 = x4739 z4740 = x4740 z4741 = x4741 z4742 = x4742 z4743 = x4743 z4744 = x4744 z4745 = x4745 z4746 = x4746 z4747 = x4747 z4748 = x4748 z4749 = x4749 z4750 = x4750 z4751 = x4751 z4752 = x4752 z4753 = x4753 z4754 = x4754 z4755 = x4755 z4756 = x4756 z4757 = x4757 z4758 = x4758 z4759 = x4759 z4760 = x4760 z4761 = x4761 z4762 = x4762 z4763 = x4763 z4764 = x4764 z4765 = x4765 z4766 = x4766 z4767 = x4767 z4768 = x4768 z4769 = x4769 z4770 = x4770 z4771 = x4771 z4772 = x4772 z4773 = x4773 z4774 = x4774 z4775 = x4775 z4776 = x4776 z4777 = x4777 z4778 = x4778 z4779 = x4779 z4780 = x4780 z4781 = x4781 z4782 = x4782 z4783 = x4783 z4784 = x4784 z4785 = x4785 z4786 = x4786 z4787 = x4787 z4788 = x4788 z4789 = x4789 z4790 = x4790 z4791 = x4791 z4792 = x4792 z4793 = x4793 z4794 = x4794 z4795 = x4795 z4796 = x4796 z4797 = x4797 z4798 = x4798 z4799 = x4799 z4800 = x4800 z4801 = x4801 z4802 = x4802 z4803 = x4803 z4804 = x4804 z4805 = x4805 z4806 = x4806 z4807 = x4807 z4808 = x4808 z4809 = x4809 z4810 = x4810 z4811 = x4811 z4812 = x4812 z4813 = x4813 z4814 = x4814 z4815 = x4815 z4816 = x4816 z4817 = x4817 z4818 = x4818 z4819 = x4819 z4820 = x4820 z4821 = x4821 z4822 = x4822 z4823 = x4823 z4824 = x4824 z4825 = x4825 z4826 = x4826 z4827 = x4827 z4828 = x4828 z4829 = x4829 z4830 = x4830 z4831 = x4831 z4832 = x4832 z4833 = x4833 z4834 = x4834 z4835 = x4835 z4836 = x4836 z4837 = x4837 z4838 = x4838 z4839 = x4839 z4840 = x4840 z4841 = x4841 z4842 = x4842 z4843 = x4843 z4844 = x4844 z4845 = x4845 z4846 = x4846 z4847 = x4847 z4848 = x4848 z4849 = x4849 z4850 = x4850 z4851 = x4851 z4852 = x4852 z4853 = x4853 z4854 = x4854 z4855 = x4855 z4856 = x4856 z4857 = x4857 z4858 = x4858 z4859 = x4859 z4860 = x4860 z4861 = x4861 z4862 = x4862 z4863 = x4863 z4864 = x4864 z4865 = x4865 z4866 = x4866 z4867 = x4867 z4868 = x4868 z4869 = x4869 z4870 = x4870 z4871 = x4871 z4872 = x4872 z4873 = x4873 z4874 = x4874 z4875 = x4875 z4876 = x4876 z4877 = x4877 z4878 = x4878 z4879 = x4879 z4880 = x4880 z4881 = x4881 z4882 = x4882 z4883 = x4883 z4884 = x4884 z4885 = x4885 z4886 = x4886 z4887 = x4887 z4888 = x4888 z4889 = x4889 z4890 = x4890 z4891 = x4891 z4892 = x4892 z4893 = x4893 z4894 = x4894 z4895 = x4895 z4896 = x4896 z4897 = x4897 z4898 = x4898 z4899 = x4899 z4900 = x4900 z4901 = x4901 z4902 = x4902 z4903 = x4903 z4904 = x4904 z4905 = x4905 z4906 = x4906 z4907 = x4907 z4908 = x4908 z4909 = x4909 z4910 = x4910 z4911 = x4911 z4912 = x4912 z4913 = x4913 z4914 = x4914 z4915 = x4915 z4916 = x4916 z4917 = x4917 z4918 = x4918 z4919 = x4919 z4920 = x4920 z4921 = x4921 z4922 = x4922 z4923 = x4923 z4924 = x4924 z4925 = x4925 z4926 = x4926 z4927 = x4927 z4928 = x4928 z4929 = x4929 z4930 = x4930 z4931 = x4931 z4932 = x4932 z4933 = x4933 z4934 = x4934 z4935 = x4935 z4936 = x4936 z4937 = x4937 z4938 = x4938 z4939 = x4939 z4940 = x4940 z4941 = x4941 z4942 = x4942 z4943 = x4943 z4944 = x4944 z4945 = x4945 z4946 = x4946 z4947 = x4947 z4948 = x4948 z4949 = x4949 z4950 = x4950 z4951 = x4951 z4952 = x4952 z4953 = x4953 z4954 = x4954 z4955 = x4955 z4956 = x4956 z4957 = x4957 z4958 = x4958 z4959 = x4959 z4960 = x4960 z4961 = x4961 z4962 = x4962 z4963 = x4963 z4964 = x4964 z4965 = x4965 z4966 = x4966 z4967 = x4967 z4968 = x4968 z4969 = x4969 z4970 = x4970 z4971 = x4971 z4972 = x4972 z4973 = x4973 z4974 = x4974 z4975 = x4975 z4976 = x4976 z4977 = x4977 z4978 = x4978 z4979 = x4979 z4980 = x4980 z4981 = x4981 z4982 = x4982 z4983 = x4983 z4984 = x4984 z4985 = x4985 z4986 = x4986 z4987 = x4987 z4988 = x4988 z4989 = x4989 z4990 = x4990 z4991 = x4991 z4992 = x4992 z4993 = x4993 z4994 = x4994 z4995 = x4995 z4996 = x4996 z4997 = x4997 z4998 = x4998 z4999 = x4999 z5000 = x5000 z5001 = x5001 z5002 = x5002 z5003 = x5003 z5004 = x5004 z5005 = x5005 z5006 = x5006 z5007 = x5007 z5008 = x5008 z5009 = x5009 z5010 = x5010 z5011 = x5011 z5012 = x5012 z5013 = x5013 z5014 = x5014 z5015 = x5015 z5016 = x5016 z5017 = x5017 z5018 = x5018 z5019 = x5019 z5020 = x5020 z5021 = x5021 z5022 = x5022 z5023 = x5023 z5024 = x5024 z5025 = x5025 z5026 = x5026 z5027 = x5027 z5028 = x5028 z5029 = x5029 z5030 = x5030 z5031 = x5031 z5032 = x5032 z5033 = x5033 z5034 = x5034 z5035 = x5035 z5036 = x5036 z5037 = x5037 z5038 = x5038 z5039 = x5039 z5040 = x5040 z5041 = x5041 z5042 = x5042 z5043 = x5043 z5044 = x5044 z5045 = x5045 z5046 = x5046 z5047 = x5047 z5048 = x5048 z5049 = x5049 z5050 = x5050 z5051 = x5051 z5052 = x5052 z5053 = x5053 z5054 = x5054 z5055 = x5055 z5056 = x5056 z5057 = x5057 z5058 = x5058 z5059 = x5059 z5060 = x5060 z5061 = x5061 z5062 = x5062 z5063 = x5063 z5064 = x5064 z5065 = x5065 z5066 = x5066 z5067 = x5067 z5068 = x5068 z5069 = x5069 z5070 = x5070 z5071 = x5071 z5072 = x5072 z5073 = x5073 z5074 = x5074 z5075 = x5075 z5076 = x5076 z5077 = x5077 z5078 = x5078 z5079 = x5079 z5080 = x5080 z5081 = x5081 z5082 = x5082 z5083 = x5083 z5084 = x5084 z5085 = x5085 z5086 = x5086 z5087 = x5087 z5088 = x5088 z5089 = x5089 z5090 = x5090 z5091 = x5091 z5092 = x5092 z5093 = x5093 z5094 = x5094 z5095 = x5095 z5096 = x5096 z5097 = x5097 z5098 = x5098 z5099 = x5099 z5100 = x5100 z5101 = x5101 z5102 = x5102 z5103 = x5103 z5104 = x5104 z5105 = x5105 z5106 = x5106 z5107 = x5107 z5108 = x5108 z5109 = x5109 z5110 = x5110 z5111 = x5111 z5112 = x5112 z5113 = x5113 z5114 = x5114 z5115 = x5115 z5116 = x5116 z5117 = x5117 z5118 = x5118 z5119 = x5119 z5120 = x5120 z5121 = x5121 z5122 = x5122 z5123 = x5123 z5124 = x5124 z5125 = x5125 z5126 = x5126 z5127 = x5127 z5128 = x5128 z5129 = x5129 z5130 = x5130 z5131 = x5131 z5132 = x5132 z5133 = x5133 z5134 = x5134 z5135 = x5135 z5136 = x5136 z5137 = x5137 z5138 = x5138 z5139 = x5139 z5140 = x5140 z5141 = x5141 z5142 = x5142 z5143 = x5143 z5144 = x5144 z5145 = x5145 z5146 = x5146 z5147 = x5147 z5148 = x5148 z5149 = x5149 z5150 = x5150 z5151 = x5151 z5152 = x5152 z5153 = x5153 z5154 = x5154 z5155 = x5155 z5156 = x5156 z5157 = x5157 z5158 = x5158 z5159 = x5159 z5160 = x5160 z5161 = x5161 z5162 = x5162 z5163 = x5163 z5164 = x5164 z5165 = x5165 z5166 = x5166 z5167 = x5167 z5168 = x5168 z5169 = x5169 z5170 = x5170 z5171 = x5171 z5172 = x5172 z5173 = x5173 z5174 = x5174 z5175 = x5175 z5176 = x5176 z5177 = x5177 z5178 = x5178 z5179 = x5179 z5180 = x5180 z5181 = x5181 z5182 = x5182 z5183 = x5183 z5184 = x5184 z5185 = x5185 z5186 = x5186 z5187 = x5187 z5188 = x5188 z5189 = x5189 z5190 = x5190 z5191 = x5191 z5192 = x5192 z5193 = x5193 z5194 = x5194 z5195 = x5195 z5196 = x5196 z5197 = x5197 z5198 = x5198 z5199 = x5199 z5200 = x5200 z5201 = x5201 z5202 = x5202 z5203 = x5203 z5204 = x5204 z5205 = x5205 z5206 = x5206 z5207 = x5207 z5208 = x5208 z5209 = x5209 z5210 = x5210 z5211 = x5211 z5212 = x5212 z5213 = x5213 z5214 = x5214 z5215 = x5215 z5216 = x5216 z5217 = x5217 z5218 = x5218 z5219 = x5219 z5220 = x5220 z5221 = x5221 z5222 = x5222 z5223 = x5223 z5224 = x5224 z5225 = x5225 z5226 = x5226 z5227 = x5227 z5228 = x5228 z5229 = x5229 z5230 = x5230 z5231 = x5231 z5232 = x5232 z5233 = x5233 z5234 = x5234 z5235 = x5235 z5236 = x5236 z5237 = x5237 z5238 = x5238 z5239 = x5239 z5240 = x5240 z5241 = x5241 z5242 = x5242 z5243 = x5243 z5244 = x5244 z5245 = x5245 z5246 = x5246 z5247 = x5247 z5248 = x5248 z5249 = x5249 z5250 = x5250 z5251 = x5251 z5252 = x5252 z5253 = x5253 z5254 = x5254 z5255 = x5255 z5256 = x5256 z5257 = x5257 z5258 = x5258 z5259 = x5259 z5260 = x5260 z5261 = x5261 z5262 = x5262 z5263 = x5263 z5264 = x5264 z5265 = x5265 z5266 = x5266 z5267 = x5267 z5268 = x5268 z5269 = x5269 z5270 = x5270 z5271 = x5271 z5272 = x5272 z5273 = x5273 z5274 = x5274 z5275 = x5275 z5276 = x5276 z5277 = x5277 z5278 = x5278 z5279 = x5279 z5280 = x5280 z5281 = x5281 z5282 = x5282 z5283 = x5283 z5284 = x5284 z5285 = x5285 z5286 = x5286 z5287 = x5287 z5288 = x5288 z5289 = x5289 z5290 = x5290 z5291 = x5291 z5292 = x5292 z5293 = x5293 z5294 = x5294 z5295 = x5295 z5296 = x5296 z5297 = x5297 z5298 = x5298 z5299 = x5299 z5300 = x5300 z5301 = x5301 z5302 = x5302 z5303 = x5303 z5304 = x5304 z5305 = x5305 z5306 = x5306 z5307 = x5307 z5308 = x5308 z5309 = x5309 z5310 = x5310 z5311 = x5311 z5312 = x5312 z5313 = x5313 z5314 = x5314 z5315 = x5315 z5316 = x5316 z5317 = x5317 z5318 = x5318 z5319 = x5319 z5320 = x5320 z5321 = x5321 z5322 = x5322 z5323 = x5323 z5324 = x5324 z5325 = x5325 z5326 = x5326 z5327 = x5327 z5328 = x5328 z5329 = x5329 z5330 = x5330 z5331 = x5331 z5332 = x5332 z5333 = x5333 z5334 = x5334 z5335 = x5335 z5336 = x5336 z5337 = x5337 z5338 = x5338 z5339 = x5339 z5340 = x5340 z5341 = x5341 z5342 = x5342 z5343 = x5343 z5344 = x5344 z5345 = x5345 z5346 = x5346 z5347 = x5347 z5348 = x5348 z5349 = x5349 z5350 = x5350 z5351 = x5351 z5352 = x5352 z5353 = x5353 z5354 = x5354 z5355 = x5355 z5356 = x5356 z5357 = x5357 z5358 = x5358 z5359 = x5359 z5360 = x5360 z5361 = x5361 z5362 = x5362 z5363 = x5363 z5364 = x5364 z5365 = x5365 z5366 = x5366 z5367 = x5367 z5368 = x5368 z5369 = x5369 z5370 = x5370 z5371 = x5371 z5372 = x5372 z5373 = x5373 z5374 = x5374 z5375 = x5375 z5376 = x5376 z5377 = x5377 z5378 = x5378 z5379 = x5379 z5380 = x5380 z5381 = x5381 z5382 = x5382 z5383 = x5383 z5384 = x5384 z5385 = x5385 z5386 = x5386 z5387 = x5387 z5388 = x5388 z5389 = x5389 z5390 = x5390 z5391 = x5391 z5392 = x5392 z5393 = x5393 z5394 = x5394 z5395 = x5395 z5396 = x5396 z5397 = x5397 z5398 = x5398 z5399 = x5399 z5400 = x5400 z5401 = x5401 z5402 = x5402 z5403 = x5403 z5404 = x5404 z5405 = x5405 z5406 = x5406 z5407 = x5407 z5408 = x5408 z5409 = x5409 z5410 = x5410 z5411 = x5411 z5412 = x5412 z5413 = x5413 z5414 = x5414 z5415 = x5415 z5416 = x5416 z5417 = x5417 z5418 = x5418 z5419 = x5419 z5420 = x5420 z5421 = x5421 z5422 = x5422 z5423 = x5423 z5424 = x5424 z5425 = x5425 z5426 = x5426 z5427 = x5427 z5428 = x5428 z5429 = x5429 z5430 = x5430 z5431 = x5431 z5432 = x5432 z5433 = x5433 z5434 = x5434 z5435 = x5435 z5436 = x5436 z5437 = x5437 z5438 = x5438 z5439 = x5439 z5440 = x5440 z5441 = x5441 z5442 = x5442 z5443 = x5443 z5444 = x5444 z5445 = x5445 z5446 = x5446 z5447 = x5447 z5448 = x5448 z5449 = x5449 z5450 = x5450 z5451 = x5451 z5452 = x5452 z5453 = x5453 z5454 = x5454 z5455 = x5455 z5456 = x5456 z5457 = x5457 z5458 = x5458 z5459 = x5459 z5460 = x5460 z5461 = x5461 z5462 = x5462 z5463 = x5463 z5464 = x5464 z5465 = x5465 z5466 = x5466 z5467 = x5467 z5468 = x5468 z5469 = x5469 z5470 = x5470 z5471 = x5471 z5472 = x5472 z5473 = x5473 z5474 = x5474 z5475 = x5475 z5476 = x5476 z5477 = x5477 z5478 = x5478 z5479 = x5479 z5480 = x5480 z5481 = x5481 z5482 = x5482 z5483 = x5483 z5484 = x5484 z5485 = x5485 z5486 = x5486 z5487 = x5487 z5488 = x5488 z5489 = x5489 z5490 = x5490 z5491 = x5491 z5492 = x5492 z5493 = x5493 z5494 = x5494 z5495 = x5495 z5496 = x5496 z5497 = x5497 z5498 = x5498 z5499 = x5499 z5500 = x5500 z5501 = x5501 z5502 = x5502 z5503 = x5503 z5504 = x5504 z5505 = x5505 z5506 = x5506 z5507 = x5507 z5508 = x5508 z5509 = x5509 z5510 = x5510 z5511 = x5511 z5512 = x5512 z5513 = x5513 z5514 = x5514 z5515 = x5515 z5516 = x5516 z5517 = x5517 z5518 = x5518 z5519 = x5519 z5520 = x5520 z5521 = x5521 z5522 = x5522 z5523 = x5523 z5524 = x5524 z5525 = x5525 z5526 = x5526 z5527 = x5527 z5528 = x5528 z5529 = x5529 z5530 = x5530 z5531 = x5531 z5532 = x5532 z5533 = x5533 z5534 = x5534 z5535 = x5535 z5536 = x5536 z5537 = x5537 z5538 = x5538 z5539 = x5539 z5540 = x5540 z5541 = x5541 z5542 = x5542 z5543 = x5543 z5544 = x5544 z5545 = x5545 z5546 = x5546 z5547 = x5547 z5548 = x5548 z5549 = x5549 z5550 = x5550 z5551 = x5551 z5552 = x5552 z5553 = x5553 z5554 = x5554 z5555 = x5555 z5556 = x5556 z5557 = x5557 z5558 = x5558 z5559 = x5559 z5560 = x5560 z5561 = x5561 z5562 = x5562 z5563 = x5563 z5564 = x5564 z5565 = x5565 z5566 = x5566 z5567 = x5567 z5568 = x5568 z5569 = x5569 z5570 = x5570 z5571 = x5571 z5572 = x5572 z5573 = x5573 z5574 = x5574 z5575 = x5575 z5576 = x5576 z5577 = x5577 z5578 = x5578 z5579 = x5579 z5580 = x5580 z5581 = x5581 z5582 = x5582 z5583 = x5583 z5584 = x5584 z5585 = x5585 z5586 = x5586 z5587 = x5587 z5588 = x5588 z5589 = x5589 z5590 = x5590 z5591 = x5591 z5592 = x5592 z5593 = x5593 z5594 = x5594 z5595 = x5595 z5596 = x5596 z5597 = x5597 z5598 = x5598 z5599 = x5599 z5600 = x5600 z5601 = x5601 z5602 = x5602 z5603 = x5603 z5604 = x5604 z5605 = x5605 z5606 = x5606 z5607 = x5607 z5608 = x5608 z5609 = x5609 z5610 = x5610 z5611 = x5611 z5612 = x5612 z5613 = x5613 z5614 = x5614 z5615 = x5615 z5616 = x5616 z5617 = x5617 z5618 = x5618 z5619 = x5619 z5620 = x5620 z5621 = x5621 z5622 = x5622 z5623 = x5623 z5624 = x5624 z5625 = x5625 z5626 = x5626 z5627 = x5627 z5628 = x5628 z5629 = x5629 z5630 = x5630 z5631 = x5631 z5632 = x5632 z5633 = x5633 z5634 = x5634 z5635 = x5635 z5636 = x5636 z5637 = x5637 z5638 = x5638 z5639 = x5639 z5640 = x5640 z5641 = x5641 z5642 = x5642 z5643 = x5643 z5644 = x5644 z5645 = x5645 z5646 = x5646 z5647 = x5647 z5648 = x5648 z5649 = x5649 z5650 = x5650 z5651 = x5651 z5652 = x5652 z5653 = x5653 z5654 = x5654 z5655 = x5655 z5656 = x5656 z5657 = x5657 z5658 = x5658 z5659 = x5659 z5660 = x5660 z5661 = x5661 z5662 = x5662 z5663 = x5663 z5664 = x5664 z5665 = x5665 z5666 = x5666 z5667 = x5667 z5668 = x5668 z5669 = x5669 z5670 = x5670 z5671 = x5671 z5672 = x5672 z5673 = x5673 z5674 = x5674 z5675 = x5675 z5676 = x5676 z5677 = x5677 z5678 = x5678 z5679 = x5679 z5680 = x5680 z5681 = x5681 z5682 = x5682 z5683 = x5683 z5684 = x5684 z5685 = x5685 z5686 = x5686 z5687 = x5687 z5688 = x5688 z5689 = x5689 z5690 = x5690 z5691 = x5691 z5692 = x5692 z5693 = x5693 z5694 = x5694 z5695 = x5695 z5696 = x5696 z5697 = x5697 z5698 = x5698 z5699 = x5699 z5700 = x5700 z5701 = x5701 z5702 = x5702 z5703 = x5703 z5704 = x5704 z5705 = x5705 z5706 = x5706 z5707 = x5707 z5708 = x5708 z5709 = x5709 z5710 = x5710 z5711 = x5711 z5712 = x5712 z5713 = x5713 z5714 = x5714 z5715 = x5715 z5716 = x5716 z5717 = x5717 z5718 = x5718 z5719 = x5719 z5720 = x5720 z5721 = x5721 z5722 = x5722 z5723 = x5723 z5724 = x5724 z5725 = x5725 z5726 = x5726 z5727 = x5727 z5728 = x5728 z5729 = x5729 z5730 = x5730 z5731 = x5731 z5732 = x5732 z5733 = x5733 z5734 = x5734 z5735 = x5735 z5736 = x5736 z5737 = x5737 z5738 = x5738 z5739 = x5739 z5740 = x5740 z5741 = x5741 z5742 = x5742 z5743 = x5743 z5744 = x5744 z5745 = x5745 z5746 = x5746 z5747 = x5747 z5748 = x5748 z5749 = x5749 z5750 = x5750 z5751 = x5751 z5752 = x5752 z5753 = x5753 z5754 = x5754 z5755 = x5755 z5756 = x5756 z5757 = x5757 z5758 = x5758 z5759 = x5759 z5760 = x5760 z5761 = x5761 z5762 = x5762 z5763 = x5763 z5764 = x5764 z5765 = x5765 z5766 = x5766 z5767 = x5767 z5768 = x5768 z5769 = x5769 z5770 = x5770 z5771 = x5771 z5772 = x5772 z5773 = x5773 z5774 = x5774 z5775 = x5775 z5776 = x5776 z5777 = x5777 z5778 = x5778 z5779 = x5779 z5780 = x5780 z5781 = x5781 z5782 = x5782 z5783 = x5783 z5784 = x5784 z5785 = x5785 z5786 = x5786 z5787 = x5787 z5788 = x5788 z5789 = x5789 z5790 = x5790 z5791 = x5791 z5792 = x5792 z5793 = x5793 z5794 = x5794 z5795 = x5795 z5796 = x5796 z5797 = x5797 z5798 = x5798 z5799 = x5799 z5800 = x5800 z5801 = x5801 z5802 = x5802 z5803 = x5803 z5804 = x5804 z5805 = x5805 z5806 = x5806 z5807 = x5807 z5808 = x5808 z5809 = x5809 z5810 = x5810 z5811 = x5811 z5812 = x5812 z5813 = x5813 z5814 = x5814 z5815 = x5815 z5816 = x5816 z5817 = x5817 z5818 = x5818 z5819 = x5819 z5820 = x5820 z5821 = x5821 z5822 = x5822 z5823 = x5823 z5824 = x5824 z5825 = x5825 z5826 = x5826 z5827 = x5827 z5828 = x5828 z5829 = x5829 z5830 = x5830 z5831 = x5831 z5832 = x5832 z5833 = x5833 z5834 = x5834 z5835 = x5835 z5836 = x5836 z5837 = x5837 z5838 = x5838 z5839 = x5839 z5840 = x5840 z5841 = x5841 z5842 = x5842 z5843 = x5843 z5844 = x5844 z5845 = x5845 z5846 = x5846 z5847 = x5847 z5848 = x5848 z5849 = x5849 z5850 = x5850 z5851 = x5851 z5852 = x5852 z5853 = x5853 z5854 = x5854 z5855 = x5855 z5856 = x5856 z5857 = x5857 z5858 = x5858 z5859 = x5859 z5860 = x5860 z5861 = x5861 z5862 = x5862 z5863 = x5863 z5864 = x5864 z5865 = x5865 z5866 = x5866 z5867 = x5867 z5868 = x5868 z5869 = x5869 z5870 = x5870 z5871 = x5871 z5872 = x5872 z5873 = x5873 z5874 = x5874 z5875 = x5875 z5876 = x5876 z5877 = x5877 z5878 = x5878 z5879 = x5879 z5880 = x5880 z5881 = x5881 z5882 = x5882 z5883 = x5883 z5884 = x5884 z5885 = x5885 z5886 = x5886 z5887 = x5887 z5888 = x5888 z5889 = x5889 z5890 = x5890 z5891 = x5891 z5892 = x5892 z5893 = x5893 z5894 = x5894 z5895 = x5895 z5896 = x5896 z5897 = x5897 z5898 = x5898 z5899 = x5899 z5900 = x5900 z5901 = x5901 z5902 = x5902 z5903 = x5903 z5904 = x5904 z5905 = x5905 z5906 = x5906 z5907 = x5907 z5908 = x5908 z5909 = x5909 z5910 = x5910 z5911 = x5911 z5912 = x5912 z5913 = x5913 z5914 = x5914 z5915 = x5915 z5916 = x5916 z5917 = x5917 z5918 = x5918 z5919 = x5919 z5920 = x5920 z5921 = x5921 z5922 = x5922 z5923 = x5923 z5924 = x5924 z5925 = x5925 z5926 = x5926 z5927 = x5927 z5928 = x5928 z5929 = x5929 z5930 = x5930 z5931 = x5931 z5932 = x5932 z5933 = x5933 z5934 = x5934 z5935 = x5935 z5936 = x5936 z5937 = x5937 z5938 = x5938 z5939 = x5939 z5940 = x5940 z5941 = x5941 z5942 = x5942 z5943 = x5943 z5944 = x5944 z5945 = x5945 z5946 = x5946 z5947 = x5947 z5948 = x5948 z5949 = x5949 z5950 = x5950 z5951 = x5951 z5952 = x5952 z5953 = x5953 z5954 = x5954 z5955 = x5955 z5956 = x5956 z5957 = x5957 z5958 = x5958 z5959 = x5959 z5960 = x5960 z5961 = x5961 z5962 = x5962 z5963 = x5963 z5964 = x5964 z5965 = x5965 z5966 = x5966 z5967 = x5967 z5968 = x5968 z5969 = x5969 z5970 = x5970 z5971 = x5971 z5972 = x5972 z5973 = x5973 z5974 = x5974 z5975 = x5975 z5976 = x5976 z5977 = x5977 z5978 = x5978 z5979 = x5979 z5980 = x5980 z5981 = x5981 z5982 = x5982 z5983 = x5983 z5984 = x5984 z5985 = x5985 z5986 = x5986 z5987 = x5987 z5988 = x5988 z5989 = x5989 z5990 = x5990 z5991 = x5991 z5992 = x5992 z5993 = x5993 z5994 = x5994 z5995 = x5995 z5996 = x5996 z5997 = x5997 z5998 = x5998 z5999 = x5999 z6000 = x6000 z6001 = x6001 z6002 = x6002 z6003 = x6003 z6004 = x6004 z6005 = x6005 z6006 = x6006 z6007 = x6007 z6008 = x6008 z6009 = x6009 z6010 = x6010 z6011 = x6011 z6012 = x6012 z6013 = x6013 z6014 = x6014 z6015 = x6015 z6016 = x6016 z6017 = x6017 z6018 = x6018 z6019 = x6019 z6020 = x6020 z6021 = x6021 z6022 = x6022 z6023 = x6023 z6024 = x6024 z6025 = x6025 z6026 = x6026 z6027 = x6027 z6028 = x6028 z6029 = x6029 z6030 = x6030 z6031 = x6031 z6032 = x6032 z6033 = x6033 z6034 = x6034 z6035 = x6035 z6036 = x6036 z6037 = x6037 z6038 = x6038 z6039 = x6039 z6040 = x6040 z6041 = x6041 z6042 = x6042 z6043 = x6043 z6044 = x6044 z6045 = x6045 z6046 = x6046 z6047 = x6047 z6048 = x6048 z6049 = x6049 z6050 = x6050 z6051 = x6051 z6052 = x6052 z6053 = x6053 z6054 = x6054 z6055 = x6055 z6056 = x6056 z6057 = x6057 z6058 = x6058 z6059 = x6059 z6060 = x6060 z6061 = x6061 z6062 = x6062 z6063 = x6063 z6064 = x6064 z6065 = x6065 z6066 = x6066 z6067 = x6067 z6068 = x6068 z6069 = x6069 z6070 = x6070 z6071 = x6071 z6072 = x6072 z6073 = x6073 z6074 = x6074 z6075 = x6075 z6076 = x6076 z6077 = x6077 z6078 = x6078 z6079 = x6079 z6080 = x6080 z6081 = x6081 z6082 = x6082 z6083 = x6083 z6084 = x6084 z6085 = x6085 z6086 = x6086 z6087 = x6087 z6088 = x6088 z6089 = x6089 z6090 = x6090 z6091 = x6091 z6092 = x6092 z6093 = x6093 z6094 = x6094 z6095 = x6095 z6096 = x6096 z6097 = x6097 z6098 = x6098 z6099 = x6099 z6100 = x6100 z6101 = x6101 z6102 = x6102 z6103 = x6103 z6104 = x6104 z6105 = x6105 z6106 = x6106 z6107 = x6107 z6108 = x6108 z6109 = x6109 z6110 = x6110 z6111 = x6111 z6112 = x6112 z6113 = x6113 z6114 = x6114 z6115 = x6115 z6116 = x6116 z6117 = x6117 z6118 = x6118 z6119 = x6119 z6120 = x6120 z6121 = x6121 z6122 = x6122 z6123 = x6123 z6124 = x6124 z6125 = x6125 z6126 = x6126 z6127 = x6127 z6128 = x6128 z6129 = x6129 z6130 = x6130 z6131 = x6131 z6132 = x6132 z6133 = x6133 z6134 = x6134 z6135 = x6135 z6136 = x6136 z6137 = x6137 z6138 = x6138 z6139 = x6139 z6140 = x6140 z6141 = x6141 z6142 = x6142 z6143 = x6143 z6144 = x6144 z6145 = x6145 z6146 = x6146 z6147 = x6147 z6148 = x6148 z6149 = x6149 z6150 = x6150 z6151 = x6151 z6152 = x6152 z6153 = x6153 z6154 = x6154 z6155 = x6155 z6156 = x6156 z6157 = x6157 z6158 = x6158 z6159 = x6159 z6160 = x6160 z6161 = x6161 z6162 = x6162 z6163 = x6163 z6164 = x6164 z6165 = x6165 z6166 = x6166 z6167 = x6167 z6168 = x6168 z6169 = x6169 z6170 = x6170 z6171 = x6171 z6172 = x6172 z6173 = x6173 z6174 = x6174 z6175 = x6175 z6176 = x6176 z6177 = x6177 z6178 = x6178 z6179 = x6179 z6180 = x6180 z6181 = x6181 z6182 = x6182 z6183 = x6183 z6184 = x6184 z6185 = x6185 z6186 = x6186 z6187 = x6187 z6188 = x6188 z6189 = x6189 z6190 = x6190 z6191 = x6191 z6192 = x6192 z6193 = x6193 z6194 = x6194 z6195 = x6195 z6196 = x6196 z6197 = x6197 z6198 = x6198 z6199 = x6199 z6200 = x6200 z6201 = x6201 z6202 = x6202 z6203 = x6203 z6204 = x6204 z6205 = x6205 z6206 = x6206 z6207 = x6207 z6208 = x6208 z6209 = x6209 z6210 = x6210 z6211 = x6211 z6212 = x6212 z6213 = x6213 z6214 = x6214 z6215 = x6215 z6216 = x6216 z6217 = x6217 z6218 = x6218 z6219 = x6219 z6220 = x6220 z6221 = x6221 z6222 = x6222 z6223 = x6223 z6224 = x6224 z6225 = x6225 z6226 = x6226 z6227 = x6227 z6228 = x6228 z6229 = x6229 z6230 = x6230 z6231 = x6231 z6232 = x6232 z6233 = x6233 z6234 = x6234 z6235 = x6235 z6236 = x6236 z6237 = x6237 z6238 = x6238 z6239 = x6239 z6240 = x6240 z6241 = x6241 z6242 = x6242 z6243 = x6243 z6244 = x6244 z6245 = x6245 z6246 = x6246 z6247 = x6247 z6248 = x6248 z6249 = x6249 z6250 = x6250 z6251 = x6251 z6252 = x6252 z6253 = x6253 z6254 = x6254 z6255 = x6255 z6256 = x6256 z6257 = x6257 z6258 = x6258 z6259 = x6259 z6260 = x6260 z6261 = x6261 z6262 = x6262 z6263 = x6263 z6264 = x6264 z6265 = x6265 z6266 = x6266 z6267 = x6267 z6268 = x6268 z6269 = x6269 z6270 = x6270 z6271 = x6271 z6272 = x6272 z6273 = x6273 z6274 = x6274 z6275 = x6275 z6276 = x6276 z6277 = x6277 z6278 = x6278 z6279 = x6279 z6280 = x6280 z6281 = x6281 z6282 = x6282 z6283 = x6283 z6284 = x6284 z6285 = x6285 z6286 = x6286 z6287 = x6287 z6288 = x6288 z6289 = x6289 z6290 = x6290 z6291 = x6291 z6292 = x6292 z6293 = x6293 z6294 = x6294 z6295 = x6295 z6296 = x6296 z6297 = x6297 z6298 = x6298 z6299 = x6299 z6300 = x6300 z6301 = x6301 z6302 = x6302 z6303 = x6303 z6304 = x6304 z6305 = x6305 z6306 = x6306 z6307 = x6307 z6308 = x6308 z6309 = x6309 z6310 = x6310 z6311 = x6311 z6312 = x6312 z6313 = x6313 z6314 = x6314 z6315 = x6315 z6316 = x6316 z6317 = x6317 z6318 = x6318 z6319 = x6319 z6320 = x6320 z6321 = x6321 z6322 = x6322 z6323 = x6323 z6324 = x6324 z6325 = x6325 z6326 = x6326 z6327 = x6327 z6328 = x6328 z6329 = x6329 z6330 = x6330 z6331 = x6331 z6332 = x6332 z6333 = x6333 z6334 = x6334 z6335 = x6335 z6336 = x6336 z6337 = x6337 z6338 = x6338 z6339 = x6339 z6340 = x6340 z6341 = x6341 z6342 = x6342 z6343 = x6343 z6344 = x6344 z6345 = x6345 z6346 = x6346 z6347 = x6347 z6348 = x6348 z6349 = x6349 z6350 = x6350 z6351 = x6351 z6352 = x6352 z6353 = x6353 z6354 = x6354 z6355 = x6355 z6356 = x6356 z6357 = x6357 z6358 = x6358 z6359 = x6359 z6360 = x6360 z6361 = x6361 z6362 = x6362 z6363 = x6363 z6364 = x6364 z6365 = x6365 z6366 = x6366 z6367 = x6367 z6368 = x6368 z6369 = x6369 z6370 = x6370 z6371 = x6371 z6372 = x6372 z6373 = x6373 z6374 = x6374 z6375 = x6375 z6376 = x6376 z6377 = x6377 z6378 = x6378 z6379 = x6379 z6380 = x6380 z6381 = x6381 z6382 = x6382 z6383 = x6383 z6384 = x6384 z6385 = x6385 z6386 = x6386 z6387 = x6387 z6388 = x6388 z6389 = x6389 z6390 = x6390 z6391 = x6391 z6392 = x6392 z6393 = x6393 z6394 = x6394 z6395 = x6395 z6396 = x6396 z6397 = x6397 z6398 = x6398 z6399 = x6399 z6400 = x6400 z6401 = x6401 z6402 = x6402 z6403 = x6403 z6404 = x6404 z6405 = x6405 z6406 = x6406 z6407 = x6407 z6408 = x6408 z6409 = x6409 z6410 = x6410 z6411 = x6411 z6412 = x6412 z6413 = x6413 z6414 = x6414 z6415 = x6415 z6416 = x6416 z6417 = x6417 z6418 = x6418 z6419 = x6419 z6420 = x6420 z6421 = x6421 z6422 = x6422 z6423 = x6423 z6424 = x6424 z6425 = x6425 z6426 = x6426 z6427 = x6427 z6428 = x6428 z6429 = x6429 z6430 = x6430 z6431 = x6431 z6432 = x6432 z6433 = x6433 z6434 = x6434 z6435 = x6435 z6436 = x6436 z6437 = x6437 z6438 = x6438 z6439 = x6439 z6440 = x6440 z6441 = x6441 z6442 = x6442 z6443 = x6443 z6444 = x6444 z6445 = x6445 z6446 = x6446 z6447 = x6447 z6448 = x6448 z6449 = x6449 z6450 = x6450 z6451 = x6451 z6452 = x6452 z6453 = x6453 z6454 = x6454 z6455 = x6455 z6456 = x6456 z6457 = x6457 z6458 = x6458 z6459 = x6459 z6460 = x6460 z6461 = x6461 z6462 = x6462 z6463 = x6463 z6464 = x6464 z6465 = x6465 z6466 = x6466 z6467 = x6467 z6468 = x6468 z6469 = x6469 z6470 = x6470 z6471 = x6471 z6472 = x6472 z6473 = x6473 z6474 = x6474 z6475 = x6475 z6476 = x6476 z6477 = x6477 z6478 = x6478 z6479 = x6479 z6480 = x6480 z6481 = x6481 z6482 = x6482 z6483 = x6483 z6484 = x6484 z6485 = x6485 z6486 = x6486 z6487 = x6487 z6488 = x6488 z6489 = x6489 z6490 = x6490 z6491 = x6491 z6492 = x6492 z6493 = x6493 z6494 = x6494 z6495 = x6495 z6496 = x6496 z6497 = x6497 z6498 = x6498 z6499 = x6499 z6500 = x6500 z6501 = x6501 z6502 = x6502 z6503 = x6503 z6504 = x6504 z6505 = x6505 z6506 = x6506 z6507 = x6507 z6508 = x6508 z6509 = x6509 z6510 = x6510 z6511 = x6511 z6512 = x6512 z6513 = x6513 z6514 = x6514 z6515 = x6515 z6516 = x6516 z6517 = x6517 z6518 = x6518 z6519 = x6519 z6520 = x6520 z6521 = x6521 z6522 = x6522 z6523 = x6523 z6524 = x6524 z6525 = x6525 z6526 = x6526 z6527 = x6527 z6528 = x6528 z6529 = x6529 z6530 = x6530 z6531 = x6531 z6532 = x6532 z6533 = x6533 z6534 = x6534 z6535 = x6535 z6536 = x6536 z6537 = x6537 z6538 = x6538 z6539 = x6539 z6540 = x6540 z6541 = x6541 z6542 = x6542 z6543 = x6543 z6544 = x6544 z6545 = x6545 z6546 = x6546 z6547 = x6547 z6548 = x6548 z6549 = x6549 z6550 = x6550 z6551 = x6551 z6552 = x6552 z6553 = x6553 z6554 = x6554 z6555 = x6555 z6556 = x6556 z6557 = x6557 z6558 = x6558 z6559 = x6559 z6560 = x6560 z6561 = x6561 z6562 = x6562 z6563 = x6563 z6564 = x6564 z6565 = x6565 z6566 = x6566 z6567 = x6567 z6568 = x6568 z6569 = x6569 z6570 = x6570 z6571 = x6571 z6572 = x6572 z6573 = x6573 z6574 = x6574 z6575 = x6575 z6576 = x6576 z6577 = x6577 z6578 = x6578 z6579 = x6579 z6580 = x6580 z6581 = x6581 z6582 = x6582 z6583 = x6583 z6584 = x6584 z6585 = x6585 z6586 = x6586 z6587 = x6587 z6588 = x6588 z6589 = x6589 z6590 = x6590 z6591 = x6591 z6592 = x6592 z6593 = x6593 z6594 = x6594 z6595 = x6595 z6596 = x6596 z6597 = x6597 z6598 = x6598 z6599 = x6599 z6600 = x6600 z6601 = x6601 z6602 = x6602 z6603 = x6603 z6604 = x6604 z6605 = x6605 z6606 = x6606 z6607 = x6607 z6608 = x6608 z6609 = x6609 z6610 = x6610 z6611 = x6611 z6612 = x6612 z6613 = x6613 z6614 = x6614 z6615 = x6615 z6616 = x6616 z6617 = x6617 z6618 = x6618 z6619 = x6619 z6620 = x6620 z6621 = x6621 z6622 = x6622 z6623 = x6623 z6624 = x6624 z6625 = x6625 z6626 = x6626 z6627 = x6627 z6628 = x6628 z6629 = x6629 z6630 = x6630 z6631 = x6631 z6632 = x6632 z6633 = x6633 z6634 = x6634 z6635 = x6635 z6636 = x6636 z6637 = x6637 z6638 = x6638 z6639 = x6639 z6640 = x6640 z6641 = x6641 z6642 = x6642 z6643 = x6643 z6644 = x6644 z6645 = x6645 z6646 = x6646 z6647 = x6647 z6648 = x6648 z6649 = x6649 z6650 = x6650 z6651 = x6651 z6652 = x6652 z6653 = x6653 z6654 = x6654 z6655 = x6655 z6656 = x6656 z6657 = x6657 z6658 = x6658 z6659 = x6659 z6660 = x6660 z6661 = x6661 z6662 = x6662 z6663 = x6663 z6664 = x6664 z6665 = x6665 z6666 = x6666 z6667 = x6667 z6668 = x6668 z6669 = x6669 z6670 = x6670 z6671 = x6671 z6672 = x6672 z6673 = x6673 z6674 = x6674 z6675 = x6675 z6676 = x6676 z6677 = x6677 z6678 = x6678 z6679 = x6679 z6680 = x6680 z6681 = x6681 z6682 = x6682 z6683 = x6683 z6684 = x6684 z6685 = x6685 z6686 = x6686 z6687 = x6687 z6688 = x6688 z6689 = x6689 z6690 = x6690 z6691 = x6691 z6692 = x6692 z6693 = x6693 z6694 = x6694 z6695 = x6695 z6696 = x6696 z6697 = x6697 z6698 = x6698 z6699 = x6699 z6700 = x6700 z6701 = x6701 z6702 = x6702 z6703 = x6703 z6704 = x6704 z6705 = x6705 z6706 = x6706 z6707 = x6707 z6708 = x6708 z6709 = x6709 z6710 = x6710 z6711 = x6711 z6712 = x6712 z6713 = x6713 z6714 = x6714 z6715 = x6715 z6716 = x6716 z6717 = x6717 z6718 = x6718 z6719 = x6719 z6720 = x6720 z6721 = x6721 z6722 = x6722 z6723 = x6723 z6724 = x6724 z6725 = x6725 z6726 = x6726 z6727 = x6727 z6728 = x6728 z6729 = x6729 z6730 = x6730 z6731 = x6731 z6732 = x6732 z6733 = x6733 z6734 = x6734 z6735 = x6735 z6736 = x6736 z6737 = x6737 z6738 = x6738 z6739 = x6739 z6740 = x6740 z6741 = x6741 z6742 = x6742 z6743 = x6743 z6744 = x6744 z6745 = x6745 z6746 = x6746 z6747 = x6747 z6748 = x6748 z6749 = x6749 z6750 = x6750 z6751 = x6751 z6752 = x6752 z6753 = x6753 z6754 = x6754 z6755 = x6755 z6756 = x6756 z6757 = x6757 z6758 = x6758 z6759 = x6759 z6760 = x6760 z6761 = x6761 z6762 = x6762 z6763 = x6763 z6764 = x6764 z6765 = x6765 z6766 = x6766 z6767 = x6767 z6768 = x6768 z6769 = x6769 z6770 = x6770 z6771 = x6771 z6772 = x6772 z6773 = x6773 z6774 = x6774 z6775 = x6775 z6776 = x6776 z6777 = x6777 z6778 = x6778 z6779 = x6779 z6780 = x6780 z6781 = x6781 z6782 = x6782 z6783 = x6783 z6784 = x6784 z6785 = x6785 z6786 = x6786 z6787 = x6787 z6788 = x6788 z6789 = x6789 z6790 = x6790 z6791 = x6791 z6792 = x6792 z6793 = x6793 z6794 = x6794 z6795 = x6795 z6796 = x6796 z6797 = x6797 z6798 = x6798 z6799 = x6799 z6800 = x6800 z6801 = x6801 z6802 = x6802 z6803 = x6803 z6804 = x6804 z6805 = x6805 z6806 = x6806 z6807 = x6807 z6808 = x6808 z6809 = x6809 z6810 = x6810 z6811 = x6811 z6812 = x6812 z6813 = x6813 z6814 = x6814 z6815 = x6815 z6816 = x6816 z6817 = x6817 z6818 = x6818 z6819 = x6819 z6820 = x6820 z6821 = x6821 z6822 = x6822 z6823 = x6823 z6824 = x6824 z6825 = x6825 z6826 = x6826 z6827 = x6827 z6828 = x6828 z6829 = x6829 z6830 = x6830 z6831 = x6831 z6832 = x6832 z6833 = x6833 z6834 = x6834 z6835 = x6835 z6836 = x6836 z6837 = x6837 z6838 = x6838 z6839 = x6839 z6840 = x6840 z6841 = x6841 z6842 = x6842 z6843 = x6843 z6844 = x6844 z6845 = x6845 z6846 = x6846 z6847 = x6847 z6848 = x6848 z6849 = x6849 z6850 = x6850 z6851 = x6851 z6852 = x6852 z6853 = x6853 z6854 = x6854 z6855 = x6855 z6856 = x6856 z6857 = x6857 z6858 = x6858 z6859 = x6859 z6860 = x6860 z6861 = x6861 z6862 = x6862 z6863 = x6863 z6864 = x6864 z6865 = x6865 z6866 = x6866 z6867 = x6867 z6868 = x6868 z6869 = x6869 z6870 = x6870 z6871 = x6871 z6872 = x6872 z6873 = x6873 z6874 = x6874 z6875 = x6875 z6876 = x6876 z6877 = x6877 z6878 = x6878 z6879 = x6879 z6880 = x6880 z6881 = x6881 z6882 = x6882 z6883 = x6883 z6884 = x6884 z6885 = x6885 z6886 = x6886 z6887 = x6887 z6888 = x6888 z6889 = x6889 z6890 = x6890 z6891 = x6891 z6892 = x6892 z6893 = x6893 z6894 = x6894 z6895 = x6895 z6896 = x6896 z6897 = x6897 z6898 = x6898 z6899 = x6899 z6900 = x6900 z6901 = x6901 z6902 = x6902 z6903 = x6903 z6904 = x6904 z6905 = x6905 z6906 = x6906 z6907 = x6907 z6908 = x6908 z6909 = x6909 z6910 = x6910 z6911 = x6911 z6912 = x6912 z6913 = x6913 z6914 = x6914 z6915 = x6915 z6916 = x6916 z6917 = x6917 z6918 = x6918 z6919 = x6919 z6920 = x6920 z6921 = x6921 z6922 = x6922 z6923 = x6923 z6924 = x6924 z6925 = x6925 z6926 = x6926 z6927 = x6927 z6928 = x6928 z6929 = x6929 z6930 = x6930 z6931 = x6931 z6932 = x6932 z6933 = x6933 z6934 = x6934 z6935 = x6935 z6936 = x6936 z6937 = x6937 z6938 = x6938 z6939 = x6939 z6940 = x6940 z6941 = x6941 z6942 = x6942 z6943 = x6943 z6944 = x6944 z6945 = x6945 z6946 = x6946 z6947 = x6947 z6948 = x6948 z6949 = x6949 z6950 = x6950 z6951 = x6951 z6952 = x6952 z6953 = x6953 z6954 = x6954 z6955 = x6955 z6956 = x6956 z6957 = x6957 z6958 = x6958 z6959 = x6959 z6960 = x6960 z6961 = x6961 z6962 = x6962 z6963 = x6963 z6964 = x6964 z6965 = x6965 z6966 = x6966 z6967 = x6967 z6968 = x6968 z6969 = x6969 z6970 = x6970 z6971 = x6971 z6972 = x6972 z6973 = x6973 z6974 = x6974 z6975 = x6975 z6976 = x6976 z6977 = x6977 z6978 = x6978 z6979 = x6979 z6980 = x6980 z6981 = x6981 z6982 = x6982 z6983 = x6983 z6984 = x6984 z6985 = x6985 z6986 = x6986 z6987 = x6987 z6988 = x6988 z6989 = x6989 z6990 = x6990 z6991 = x6991 z6992 = x6992 z6993 = x6993 z6994 = x6994 z6995 = x6995 z6996 = x6996 z6997 = x6997 z6998 = x6998 z6999 = x6999 z7000 = x7000 z7001 = x7001 z7002 = x7002 z7003 = x7003 z7004 = x7004 z7005 = x7005 z7006 = x7006 z7007 = x7007 z7008 = x7008 z7009 = x7009 z7010 = x7010 z7011 = x7011 z7012 = x7012 z7013 = x7013 z7014 = x7014 z7015 = x7015 z7016 = x7016 z7017 = x7017 z7018 = x7018 z7019 = x7019 z7020 = x7020 z7021 = x7021 z7022 = x7022 z7023 = x7023 z7024 = x7024 z7025 = x7025 z7026 = x7026 z7027 = x7027 z7028 = x7028 z7029 = x7029 z7030 = x7030 z7031 = x7031 z7032 = x7032 z7033 = x7033 z7034 = x7034 z7035 = x7035 z7036 = x7036 z7037 = x7037 z7038 = x7038 z7039 = x7039 z7040 = x7040 z7041 = x7041 z7042 = x7042 z7043 = x7043 z7044 = x7044 z7045 = x7045 z7046 = x7046 z7047 = x7047 z7048 = x7048 z7049 = x7049 z7050 = x7050 z7051 = x7051 z7052 = x7052 z7053 = x7053 z7054 = x7054 z7055 = x7055 z7056 = x7056 z7057 = x7057 z7058 = x7058 z7059 = x7059 z7060 = x7060 z7061 = x7061 z7062 = x7062 z7063 = x7063 z7064 = x7064 z7065 = x7065 z7066 = x7066 z7067 = x7067 z7068 = x7068 z7069 = x7069 z7070 = x7070 z7071 = x7071 z7072 = x7072 z7073 = x7073 z7074 = x7074 z7075 = x7075 z7076 = x7076 z7077 = x7077 z7078 = x7078 z7079 = x7079 z7080 = x7080 z7081 = x7081 z7082 = x7082 z7083 = x7083 z7084 = x7084 z7085 = x7085 z7086 = x7086 z7087 = x7087 z7088 = x7088 z7089 = x7089 z7090 = x7090 z7091 = x7091 z7092 = x7092 z7093 = x7093 z7094 = x7094 z7095 = x7095 z7096 = x7096 z7097 = x7097 z7098 = x7098 z7099 = x7099 z7100 = x7100 z7101 = x7101 z7102 = x7102 z7103 = x7103 z7104 = x7104 z7105 = x7105 z7106 = x7106 z7107 = x7107 z7108 = x7108 z7109 = x7109 z7110 = x7110 z7111 = x7111 z7112 = x7112 z7113 = x7113 z7114 = x7114 z7115 = x7115 z7116 = x7116 z7117 = x7117 z7118 = x7118 z7119 = x7119 z7120 = x7120 z7121 = x7121 z7122 = x7122 z7123 = x7123 z7124 = x7124 z7125 = x7125 z7126 = x7126 z7127 = x7127 z7128 = x7128 z7129 = x7129 z7130 = x7130 z7131 = x7131 z7132 = x7132 z7133 = x7133 z7134 = x7134 z7135 = x7135 z7136 = x7136 z7137 = x7137 z7138 = x7138 z7139 = x7139 z7140 = x7140 z7141 = x7141 z7142 = x7142 z7143 = x7143 z7144 = x7144 z7145 = x7145 z7146 = x7146 z7147 = x7147 z7148 = x7148 z7149 = x7149 z7150 = x7150 z7151 = x7151 z7152 = x7152 z7153 = x7153 z7154 = x7154 z7155 = x7155 z7156 = x7156 z7157 = x7157 z7158 = x7158 z7159 = x7159 z7160 = x7160 z7161 = x7161 z7162 = x7162 z7163 = x7163 z7164 = x7164 z7165 = x7165 z7166 = x7166 z7167 = x7167 z7168 = x7168 z7169 = x7169 z7170 = x7170 z7171 = x7171 z7172 = x7172 z7173 = x7173 z7174 = x7174 z7175 = x7175 z7176 = x7176 z7177 = x7177 z7178 = x7178 z7179 = x7179 z7180 = x7180 z7181 = x7181 z7182 = x7182 z7183 = x7183 z7184 = x7184 z7185 = x7185 z7186 = x7186 z7187 = x7187 z7188 = x7188 z7189 = x7189 z7190 = x7190 z7191 = x7191 z7192 = x7192 z7193 = x7193 z7194 = x7194 z7195 = x7195 z7196 = x7196 z7197 = x7197 z7198 = x7198 z7199 = x7199 z7200 = x7200 z7201 = x7201 z7202 = x7202 z7203 = x7203 z7204 = x7204 z7205 = x7205 z7206 = x7206 z7207 = x7207 z7208 = x7208 z7209 = x7209 z7210 = x7210 z7211 = x7211 z7212 = x7212 z7213 = x7213 z7214 = x7214 z7215 = x7215 z7216 = x7216 z7217 = x7217 z7218 = x7218 z7219 = x7219 z7220 = x7220 z7221 = x7221 z7222 = x7222 z7223 = x7223 z7224 = x7224 z7225 = x7225 z7226 = x7226 z7227 = x7227 z7228 = x7228 z7229 = x7229 z7230 = x7230 z7231 = x7231 z7232 = x7232 z7233 = x7233 z7234 = x7234 z7235 = x7235 z7236 = x7236 z7237 = x7237 z7238 = x7238 z7239 = x7239 z7240 = x7240 z7241 = x7241 z7242 = x7242 z7243 = x7243 z7244 = x7244 z7245 = x7245 z7246 = x7246 z7247 = x7247 z7248 = x7248 z7249 = x7249 z7250 = x7250 z7251 = x7251 z7252 = x7252 z7253 = x7253 z7254 = x7254 z7255 = x7255 z7256 = x7256 z7257 = x7257 z7258 = x7258 z7259 = x7259 z7260 = x7260 z7261 = x7261 z7262 = x7262 z7263 = x7263 z7264 = x7264 z7265 = x7265 z7266 = x7266 z7267 = x7267 z7268 = x7268 z7269 = x7269 z7270 = x7270 z7271 = x7271 z7272 = x7272 z7273 = x7273 z7274 = x7274 z7275 = x7275 z7276 = x7276 z7277 = x7277 z7278 = x7278 z7279 = x7279 z7280 = x7280 z7281 = x7281 z7282 = x7282 z7283 = x7283 z7284 = x7284 z7285 = x7285 z7286 = x7286 z7287 = x7287 z7288 = x7288 z7289 = x7289 z7290 = x7290 z7291 = x7291 z7292 = x7292 z7293 = x7293 z7294 = x7294 z7295 = x7295 z7296 = x7296 z7297 = x7297 z7298 = x7298 z7299 = x7299 z7300 = x7300 z7301 = x7301 z7302 = x7302 z7303 = x7303 z7304 = x7304 z7305 = x7305 z7306 = x7306 z7307 = x7307 z7308 = x7308 z7309 = x7309 z7310 = x7310 z7311 = x7311 z7312 = x7312 z7313 = x7313 z7314 = x7314 z7315 = x7315 z7316 = x7316 z7317 = x7317 z7318 = x7318 z7319 = x7319 z7320 = x7320 z7321 = x7321 z7322 = x7322 z7323 = x7323 z7324 = x7324 z7325 = x7325 z7326 = x7326 z7327 = x7327 z7328 = x7328 z7329 = x7329 z7330 = x7330 z7331 = x7331 z7332 = x7332 z7333 = x7333 z7334 = x7334 z7335 = x7335 z7336 = x7336 z7337 = x7337 z7338 = x7338 z7339 = x7339 z7340 = x7340 z7341 = x7341 z7342 = x7342 z7343 = x7343 z7344 = x7344 z7345 = x7345 z7346 = x7346 z7347 = x7347 z7348 = x7348 z7349 = x7349 z7350 = x7350 z7351 = x7351 z7352 = x7352 z7353 = x7353 z7354 = x7354 z7355 = x7355 z7356 = x7356 z7357 = x7357 z7358 = x7358 z7359 = x7359 z7360 = x7360 z7361 = x7361 z7362 = x7362 z7363 = x7363 z7364 = x7364 z7365 = x7365 z7366 = x7366 z7367 = x7367 z7368 = x7368 z7369 = x7369 z7370 = x7370 z7371 = x7371 z7372 = x7372 z7373 = x7373 z7374 = x7374 z7375 = x7375 z7376 = x7376 z7377 = x7377 z7378 = x7378 z7379 = x7379 z7380 = x7380 z7381 = x7381 z7382 = x7382 z7383 = x7383 z7384 = x7384 z7385 = x7385 z7386 = x7386 z7387 = x7387 z7388 = x7388 z7389 = x7389 z7390 = x7390 z7391 = x7391 z7392 = x7392 z7393 = x7393 z7394 = x7394 z7395 = x7395 z7396 = x7396 z7397 = x7397 z7398 = x7398 z7399 = x7399 z7400 = x7400 z7401 = x7401 z7402 = x7402 z7403 = x7403 z7404 = x7404 z7405 = x7405 z7406 = x7406 z7407 = x7407 z7408 = x7408 z7409 = x7409 z7410 = x7410 z7411 = x7411 z7412 = x7412 z7413 = x7413 z7414 = x7414 z7415 = x7415 z7416 = x7416 z7417 = x7417 z7418 = x7418 z7419 = x7419 z7420 = x7420 z7421 = x7421 z7422 = x7422 z7423 = x7423 z7424 = x7424 z7425 = x7425 z7426 = x7426 z7427 = x7427 z7428 = x7428 z7429 = x7429 z7430 = x7430 z7431 = x7431 z7432 = x7432 z7433 = x7433 z7434 = x7434 z7435 = x7435 z7436 = x7436 z7437 = x7437 z7438 = x7438 z7439 = x7439 z7440 = x7440 z7441 = x7441 z7442 = x7442 z7443 = x7443 z7444 = x7444 z7445 = x7445 z7446 = x7446 z7447 = x7447 z7448 = x7448 z7449 = x7449 z7450 = x7450 z7451 = x7451 z7452 = x7452 z7453 = x7453 z7454 = x7454 z7455 = x7455 z7456 = x7456 z7457 = x7457 z7458 = x7458 z7459 = x7459 z7460 = x7460 z7461 = x7461 z7462 = x7462 z7463 = x7463 z7464 = x7464 z7465 = x7465 z7466 = x7466 z7467 = x7467 z7468 = x7468 z7469 = x7469 z7470 = x7470 z7471 = x7471 z7472 = x7472 z7473 = x7473 z7474 = x7474 z7475 = x7475 z7476 = x7476 z7477 = x7477 z7478 = x7478 z7479 = x7479 z7480 = x7480 z7481 = x7481 z7482 = x7482 z7483 = x7483 z7484 = x7484 z7485 = x7485 z7486 = x7486 z7487 = x7487 z7488 = x7488 z7489 = x7489 z7490 = x7490 z7491 = x7491 z7492 = x7492 z7493 = x7493 z7494 = x7494 z7495 = x7495 z7496 = x7496 z7497 = x7497 z7498 = x7498 z7499 = x7499 z7500 = x7500 z7501 = x7501 z7502 = x7502 z7503 = x7503 z7504 = x7504 z7505 = x7505 z7506 = x7506 z7507 = x7507 z7508 = x7508 z7509 = x7509 z7510 = x7510 z7511 = x7511 z7512 = x7512 z7513 = x7513 z7514 = x7514 z7515 = x7515 z7516 = x7516 z7517 = x7517 z7518 = x7518 z7519 = x7519 z7520 = x7520 z7521 = x7521 z7522 = x7522 z7523 = x7523 z7524 = x7524 z7525 = x7525 z7526 = x7526 z7527 = x7527 z7528 = x7528 z7529 = x7529 z7530 = x7530 z7531 = x7531 z7532 = x7532 z7533 = x7533 z7534 = x7534 z7535 = x7535 z7536 = x7536 z7537 = x7537 z7538 = x7538 z7539 = x7539 z7540 = x7540 z7541 = x7541 z7542 = x7542 z7543 = x7543 z7544 = x7544 z7545 = x7545 z7546 = x7546 z7547 = x7547 z7548 = x7548 z7549 = x7549 z7550 = x7550 z7551 = x7551 z7552 = x7552 z7553 = x7553 z7554 = x7554 z7555 = x7555 z7556 = x7556 z7557 = x7557 z7558 = x7558 z7559 = x7559 z7560 = x7560 z7561 = x7561 z7562 = x7562 z7563 = x7563 z7564 = x7564 z7565 = x7565 z7566 = x7566 z7567 = x7567 z7568 = x7568 z7569 = x7569 z7570 = x7570 z7571 = x7571 z7572 = x7572 z7573 = x7573 z7574 = x7574 z7575 = x7575 z7576 = x7576 z7577 = x7577 z7578 = x7578 z7579 = x7579 z7580 = x7580 z7581 = x7581 z7582 = x7582 z7583 = x7583 z7584 = x7584 z7585 = x7585 z7586 = x7586 z7587 = x7587 z7588 = x7588 z7589 = x7589 z7590 = x7590 z7591 = x7591 z7592 = x7592 z7593 = x7593 z7594 = x7594 z7595 = x7595 z7596 = x7596 z7597 = x7597 z7598 = x7598 z7599 = x7599 z7600 = x7600 z7601 = x7601 z7602 = x7602 z7603 = x7603 z7604 = x7604 z7605 = x7605 z7606 = x7606 z7607 = x7607 z7608 = x7608 z7609 = x7609 z7610 = x7610 z7611 = x7611 z7612 = x7612 z7613 = x7613 z7614 = x7614 z7615 = x7615 z7616 = x7616 z7617 = x7617 z7618 = x7618 z7619 = x7619 z7620 = x7620 z7621 = x7621 z7622 = x7622 z7623 = x7623 z7624 = x7624 z7625 = x7625 z7626 = x7626 z7627 = x7627 z7628 = x7628 z7629 = x7629 z7630 = x7630 z7631 = x7631 z7632 = x7632 z7633 = x7633 z7634 = x7634 z7635 = x7635 z7636 = x7636 z7637 = x7637 z7638 = x7638 z7639 = x7639 z7640 = x7640 z7641 = x7641 z7642 = x7642 z7643 = x7643 z7644 = x7644 z7645 = x7645 z7646 = x7646 z7647 = x7647 z7648 = x7648 z7649 = x7649 z7650 = x7650 z7651 = x7651 z7652 = x7652 z7653 = x7653 z7654 = x7654 z7655 = x7655 z7656 = x7656 z7657 = x7657 z7658 = x7658 z7659 = x7659 z7660 = x7660 z7661 = x7661 z7662 = x7662 z7663 = x7663 z7664 = x7664 z7665 = x7665 z7666 = x7666 z7667 = x7667 z7668 = x7668 z7669 = x7669 z7670 = x7670 z7671 = x7671 z7672 = x7672 z7673 = x7673 z7674 = x7674 z7675 = x7675 z7676 = x7676 z7677 = x7677 z7678 = x7678 z7679 = x7679 z7680 = x7680 z7681 = x7681 z7682 = x7682 z7683 = x7683 z7684 = x7684 z7685 = x7685 z7686 = x7686 z7687 = x7687 z7688 = x7688 z7689 = x7689 z7690 = x7690 z7691 = x7691 z7692 = x7692 z7693 = x7693 z7694 = x7694 z7695 = x7695 z7696 = x7696 z7697 = x7697 z7698 = x7698 z7699 = x7699 z7700 = x7700 z7701 = x7701 z7702 = x7702 z7703 = x7703 z7704 = x7704 z7705 = x7705 z7706 = x7706 z7707 = x7707 z7708 = x7708 z7709 = x7709 z7710 = x7710 z7711 = x7711 z7712 = x7712 z7713 = x7713 z7714 = x7714 z7715 = x7715 z7716 = x7716 z7717 = x7717 z7718 = x7718 z7719 = x7719 z7720 = x7720 z7721 = x7721 z7722 = x7722 z7723 = x7723 z7724 = x7724 z7725 = x7725 z7726 = x7726 z7727 = x7727 z7728 = x7728 z7729 = x7729 z7730 = x7730 z7731 = x7731 z7732 = x7732 z7733 = x7733 z7734 = x7734 z7735 = x7735 z7736 = x7736 z7737 = x7737 z7738 = x7738 z7739 = x7739 z7740 = x7740 z7741 = x7741 z7742 = x7742 z7743 = x7743 z7744 = x7744 z7745 = x7745 z7746 = x7746 z7747 = x7747 z7748 = x7748 z7749 = x7749 z7750 = x7750 z7751 = x7751 z7752 = x7752 z7753 = x7753 z7754 = x7754 z7755 = x7755 z7756 = x7756 z7757 = x7757 z7758 = x7758 z7759 = x7759 z7760 = x7760 z7761 = x7761 z7762 = x7762 z7763 = x7763 z7764 = x7764 z7765 = x7765 z7766 = x7766 z7767 = x7767 z7768 = x7768 z7769 = x7769 z7770 = x7770 z7771 = x7771 z7772 = x7772 z7773 = x7773 z7774 = x7774 z7775 = x7775 z7776 = x7776 z7777 = x7777 z7778 = x7778 z7779 = x7779 z7780 = x7780 z7781 = x7781 z7782 = x7782 z7783 = x7783 z7784 = x7784 z7785 = x7785 z7786 = x7786 z7787 = x7787 z7788 = x7788 z7789 = x7789 z7790 = x7790 z7791 = x7791 z7792 = x7792 z7793 = x7793 z7794 = x7794 z7795 = x7795 z7796 = x7796 z7797 = x7797 z7798 = x7798 z7799 = x7799 z7800 = x7800 z7801 = x7801 z7802 = x7802 z7803 = x7803 z7804 = x7804 z7805 = x7805 z7806 = x7806 z7807 = x7807 z7808 = x7808 z7809 = x7809 z7810 = x7810 z7811 = x7811 z7812 = x7812 z7813 = x7813 z7814 = x7814 z7815 = x7815 z7816 = x7816 z7817 = x7817 z7818 = x7818 z7819 = x7819 z7820 = x7820 z7821 = x7821 z7822 = x7822 z7823 = x7823 z7824 = x7824 z7825 = x7825 z7826 = x7826 z7827 = x7827 z7828 = x7828 z7829 = x7829 z7830 = x7830 z7831 = x7831 z7832 = x7832 z7833 = x7833 z7834 = x7834 z7835 = x7835 z7836 = x7836 z7837 = x7837 z7838 = x7838 z7839 = x7839 z7840 = x7840 z7841 = x7841 z7842 = x7842 z7843 = x7843 z7844 = x7844 z7845 = x7845 z7846 = x7846 z7847 = x7847 z7848 = x7848 z7849 = x7849 z7850 = x7850 z7851 = x7851 z7852 = x7852 z7853 = x7853 z7854 = x7854 z7855 = x7855 z7856 = x7856 z7857 = x7857 z7858 = x7858 z7859 = x7859 z7860 = x7860 z7861 = x7861 z7862 = x7862 z7863 = x7863 z7864 = x7864 z7865 = x7865 z7866 = x7866 z7867 = x7867 z7868 = x7868 z7869 = x7869 z7870 = x7870 z7871 = x7871 z7872 = x7872 z7873 = x7873 z7874 = x7874 z7875 = x7875 z7876 = x7876 z7877 = x7877 z7878 = x7878 z7879 = x7879 z7880 = x7880 z7881 = x7881 z7882 = x7882 z7883 = x7883 z7884 = x7884 z7885 = x7885 z7886 = x7886 z7887 = x7887 z7888 = x7888 z7889 = x7889 z7890 = x7890 z7891 = x7891 z7892 = x7892 z7893 = x7893 z7894 = x7894 z7895 = x7895 z7896 = x7896 z7897 = x7897 z7898 = x7898 z7899 = x7899 z7900 = x7900 z7901 = x7901 z7902 = x7902 z7903 = x7903 z7904 = x7904 z7905 = x7905 z7906 = x7906 z7907 = x7907 z7908 = x7908 z7909 = x7909 z7910 = x7910 z7911 = x7911 z7912 = x7912 z7913 = x7913 z7914 = x7914 z7915 = x7915 z7916 = x7916 z7917 = x7917 z7918 = x7918 z7919 = x7919 z7920 = x7920 z7921 = x7921 z7922 = x7922 z7923 = x7923 z7924 = x7924 z7925 = x7925 z7926 = x7926 z7927 = x7927 z7928 = x7928 z7929 = x7929 z7930 = x7930 z7931 = x7931 z7932 = x7932 z7933 = x7933 z7934 = x7934 z7935 = x7935 z7936 = x7936 z7937 = x7937 z7938 = x7938 z7939 = x7939 z7940 = x7940 z7941 = x7941 z7942 = x7942 z7943 = x7943 z7944 = x7944 z7945 = x7945 z7946 = x7946 z7947 = x7947 z7948 = x7948 z7949 = x7949 z7950 = x7950 z7951 = x7951 z7952 = x7952 z7953 = x7953 z7954 = x7954 z7955 = x7955 z7956 = x7956 z7957 = x7957 z7958 = x7958 z7959 = x7959 z7960 = x7960 z7961 = x7961 z7962 = x7962 z7963 = x7963 z7964 = x7964 z7965 = x7965 z7966 = x7966 z7967 = x7967 z7968 = x7968 z7969 = x7969 z7970 = x7970 z7971 = x7971 z7972 = x7972 z7973 = x7973 z7974 = x7974 z7975 = x7975 z7976 = x7976 z7977 = x7977 z7978 = x7978 z7979 = x7979 z7980 = x7980 z7981 = x7981 z7982 = x7982 z7983 = x7983 z7984 = x7984 z7985 = x7985 z7986 = x7986 z7987 = x7987 z7988 = x7988 z7989 = x7989 z7990 = x7990 z7991 = x7991 z7992 = x7992 z7993 = x7993 z7994 = x7994 z7995 = x7995 z7996 = x7996 z7997 = x7997 z7998 = x7998 z7999 = x7999 z8000 = x8000 z8001 = x8001 z8002 = x8002 z8003 = x8003 z8004 = x8004 z8005 = x8005 z8006 = x8006 z8007 = x8007 z8008 = x8008 z8009 = x8009 z8010 = x8010 z8011 = x8011 z8012 = x8012 z8013 = x8013 z8014 = x8014 z8015 = x8015 z8016 = x8016 z8017 = x8017 z8018 = x8018 z8019 = x8019 z8020 = x8020 z8021 = x8021 z8022 = x8022 z8023 = x8023 z8024 = x8024 z8025 = x8025 z8026 = x8026 z8027 = x8027 z8028 = x8028 z8029 = x8029 z8030 = x8030 z8031 = x8031 z8032 = x8032 z8033 = x8033 z8034 = x8034 z8035 = x8035 z8036 = x8036 z8037 = x8037 z8038 = x8038 z8039 = x8039 z8040 = x8040 z8041 = x8041 z8042 = x8042 z8043 = x8043 z8044 = x8044 z8045 = x8045 z8046 = x8046 z8047 = x8047 z8048 = x8048 z8049 = x8049 z8050 = x8050 z8051 = x8051 z8052 = x8052 z8053 = x8053 z8054 = x8054 z8055 = x8055 z8056 = x8056 z8057 = x8057 z8058 = x8058 z8059 = x8059 z8060 = x8060 z8061 = x8061 z8062 = x8062 z8063 = x8063 z8064 = x8064 z8065 = x8065 z8066 = x8066 z8067 = x8067 z8068 = x8068 z8069 = x8069 z8070 = x8070 z8071 = x8071 z8072 = x8072 z8073 = x8073 z8074 = x8074 z8075 = x8075 z8076 = x8076 z8077 = x8077 z8078 = x8078 z8079 = x8079 z8080 = x8080 z8081 = x8081 z8082 = x8082 z8083 = x8083 z8084 = x8084 z8085 = x8085 z8086 = x8086 z8087 = x8087 z8088 = x8088 z8089 = x8089 z8090 = x8090 z8091 = x8091 z8092 = x8092 z8093 = x8093 z8094 = x8094 z8095 = x8095 z8096 = x8096 z8097 = x8097 z8098 = x8098 z8099 = x8099 z8100 = x8100 z8101 = x8101 z8102 = x8102 z8103 = x8103 z8104 = x8104 z8105 = x8105 z8106 = x8106 z8107 = x8107 z8108 = x8108 z8109 = x8109 z8110 = x8110 z8111 = x8111 z8112 = x8112 z8113 = x8113 z8114 = x8114 z8115 = x8115 z8116 = x8116 z8117 = x8117 z8118 = x8118 z8119 = x8119 z8120 = x8120 z8121 = x8121 z8122 = x8122 z8123 = x8123 z8124 = x8124 z8125 = x8125 z8126 = x8126 z8127 = x8127 z8128 = x8128 z8129 = x8129 z8130 = x8130 z8131 = x8131 z8132 = x8132 z8133 = x8133 z8134 = x8134 z8135 = x8135 z8136 = x8136 z8137 = x8137 z8138 = x8138 z8139 = x8139 z8140 = x8140 z8141 = x8141 z8142 = x8142 z8143 = x8143 z8144 = x8144 z8145 = x8145 z8146 = x8146 z8147 = x8147 z8148 = x8148 z8149 = x8149 z8150 = x8150 z8151 = x8151 z8152 = x8152 z8153 = x8153 z8154 = x8154 z8155 = x8155 z8156 = x8156 z8157 = x8157 z8158 = x8158 z8159 = x8159 z8160 = x8160 z8161 = x8161 z8162 = x8162 z8163 = x8163 z8164 = x8164 z8165 = x8165 z8166 = x8166 z8167 = x8167 z8168 = x8168 z8169 = x8169 z8170 = x8170 z8171 = x8171 z8172 = x8172 z8173 = x8173 z8174 = x8174 z8175 = x8175 z8176 = x8176 z8177 = x8177 z8178 = x8178 z8179 = x8179 z8180 = x8180 z8181 = x8181 z8182 = x8182 z8183 = x8183 z8184 = x8184 z8185 = x8185 z8186 = x8186 z8187 = x8187 z8188 = x8188 z8189 = x8189 z8190 = x8190 z8191 = x8191 z8192 = x8192 z8193 = x8193 z8194 = x8194 z8195 = x8195 z8196 = x8196 z8197 = x8197 z8198 = x8198 z8199 = x8199 z8200 = x8200 z8201 = x8201 z8202 = x8202 z8203 = x8203 z8204 = x8204 z8205 = x8205 z8206 = x8206 z8207 = x8207 z8208 = x8208 z8209 = x8209 z8210 = x8210 z8211 = x8211 z8212 = x8212 z8213 = x8213 z8214 = x8214 z8215 = x8215 z8216 = x8216 z8217 = x8217 z8218 = x8218 z8219 = x8219 z8220 = x8220 z8221 = x8221 z8222 = x8222 z8223 = x8223 z8224 = x8224 z8225 = x8225 z8226 = x8226 z8227 = x8227 z8228 = x8228 z8229 = x8229 z8230 = x8230 z8231 = x8231 z8232 = x8232 z8233 = x8233 z8234 = x8234 z8235 = x8235 z8236 = x8236 z8237 = x8237 z8238 = x8238 z8239 = x8239 z8240 = x8240 z8241 = x8241 z8242 = x8242 z8243 = x8243 z8244 = x8244 z8245 = x8245 z8246 = x8246 z8247 = x8247 z8248 = x8248 z8249 = x8249 z8250 = x8250 z8251 = x8251 z8252 = x8252 z8253 = x8253 z8254 = x8254 z8255 = x8255 z8256 = x8256 z8257 = x8257 z8258 = x8258 z8259 = x8259 z8260 = x8260 z8261 = x8261 z8262 = x8262 z8263 = x8263 z8264 = x8264 z8265 = x8265 z8266 = x8266 z8267 = x8267 z8268 = x8268 z8269 = x8269 z8270 = x8270 z8271 = x8271 z8272 = x8272 z8273 = x8273 z8274 = x8274 z8275 = x8275 z8276 = x8276 z8277 = x8277 z8278 = x8278 z8279 = x8279 z8280 = x8280 z8281 = x8281 z8282 = x8282 z8283 = x8283 z8284 = x8284 z8285 = x8285 z8286 = x8286 z8287 = x8287 z8288 = x8288 z8289 = x8289 z8290 = x8290 z8291 = x8291 z8292 = x8292 z8293 = x8293 z8294 = x8294 z8295 = x8295 z8296 = x8296 z8297 = x8297 z8298 = x8298 z8299 = x8299 z8300 = x8300 z8301 = x8301 z8302 = x8302 z8303 = x8303 z8304 = x8304 z8305 = x8305 z8306 = x8306 z8307 = x8307 z8308 = x8308 z8309 = x8309 z8310 = x8310 z8311 = x8311 z8312 = x8312 z8313 = x8313 z8314 = x8314 z8315 = x8315 z8316 = x8316 z8317 = x8317 z8318 = x8318 z8319 = x8319 z8320 = x8320 z8321 = x8321 z8322 = x8322 z8323 = x8323 z8324 = x8324 z8325 = x8325 z8326 = x8326 z8327 = x8327 z8328 = x8328 z8329 = x8329 z8330 = x8330 z8331 = x8331 z8332 = x8332 z8333 = x8333 z8334 = x8334 z8335 = x8335 z8336 = x8336 z8337 = x8337 z8338 = x8338 z8339 = x8339 z8340 = x8340 z8341 = x8341 z8342 = x8342 z8343 = x8343 z8344 = x8344 z8345 = x8345 z8346 = x8346 z8347 = x8347 z8348 = x8348 z8349 = x8349 z8350 = x8350 z8351 = x8351 z8352 = x8352 z8353 = x8353 z8354 = x8354 z8355 = x8355 z8356 = x8356 z8357 = x8357 z8358 = x8358 z8359 = x8359 z8360 = x8360 z8361 = x8361 z8362 = x8362 z8363 = x8363 z8364 = x8364 z8365 = x8365 z8366 = x8366 z8367 = x8367 z8368 = x8368 z8369 = x8369 z8370 = x8370 z8371 = x8371 z8372 = x8372 z8373 = x8373 z8374 = x8374 z8375 = x8375 z8376 = x8376 z8377 = x8377 z8378 = x8378 z8379 = x8379 z8380 = x8380 z8381 = x8381 z8382 = x8382 z8383 = x8383 z8384 = x8384 z8385 = x8385 z8386 = x8386 z8387 = x8387 z8388 = x8388 z8389 = x8389 z8390 = x8390 z8391 = x8391 z8392 = x8392 z8393 = x8393 z8394 = x8394 z8395 = x8395 z8396 = x8396 z8397 = x8397 z8398 = x8398 z8399 = x8399 z8400 = x8400 z8401 = x8401 z8402 = x8402 z8403 = x8403 z8404 = x8404 z8405 = x8405 z8406 = x8406 z8407 = x8407 z8408 = x8408 z8409 = x8409 z8410 = x8410 z8411 = x8411 z8412 = x8412 z8413 = x8413 z8414 = x8414 z8415 = x8415 z8416 = x8416 z8417 = x8417 z8418 = x8418 z8419 = x8419 z8420 = x8420 z8421 = x8421 z8422 = x8422 z8423 = x8423 z8424 = x8424 z8425 = x8425 z8426 = x8426 z8427 = x8427 z8428 = x8428 z8429 = x8429 z8430 = x8430 z8431 = x8431 z8432 = x8432 z8433 = x8433 z8434 = x8434 z8435 = x8435 z8436 = x8436 z8437 = x8437 z8438 = x8438 z8439 = x8439 z8440 = x8440 z8441 = x8441 z8442 = x8442 z8443 = x8443 z8444 = x8444 z8445 = x8445 z8446 = x8446 z8447 = x8447 z8448 = x8448 z8449 = x8449 z8450 = x8450 z8451 = x8451 z8452 = x8452 z8453 = x8453 z8454 = x8454 z8455 = x8455 z8456 = x8456 z8457 = x8457 z8458 = x8458 z8459 = x8459 z8460 = x8460 z8461 = x8461 z8462 = x8462 z8463 = x8463 z8464 = x8464 z8465 = x8465 z8466 = x8466 z8467 = x8467 z8468 = x8468 z8469 = x8469 z8470 = x8470 z8471 = x8471 z8472 = x8472 z8473 = x8473 z8474 = x8474 z8475 = x8475 z8476 = x8476 z8477 = x8477 z8478 = x8478 z8479 = x8479 z8480 = x8480 z8481 = x8481 z8482 = x8482 z8483 = x8483 z8484 = x8484 z8485 = x8485 z8486 = x8486 z8487 = x8487 z8488 = x8488 z8489 = x8489 z8490 = x8490 z8491 = x8491 z8492 = x8492 z8493 = x8493 z8494 = x8494 z8495 = x8495 z8496 = x8496 z8497 = x8497 z8498 = x8498 z8499 = x8499 z8500 = x8500 z8501 = x8501 z8502 = x8502 z8503 = x8503 z8504 = x8504 z8505 = x8505 z8506 = x8506 z8507 = x8507 z8508 = x8508 z8509 = x8509 z8510 = x8510 z8511 = x8511 z8512 = x8512 z8513 = x8513 z8514 = x8514 z8515 = x8515 z8516 = x8516 z8517 = x8517 z8518 = x8518 z8519 = x8519 z8520 = x8520 z8521 = x8521 z8522 = x8522 z8523 = x8523 z8524 = x8524 z8525 = x8525 z8526 = x8526 z8527 = x8527 z8528 = x8528 z8529 = x8529 z8530 = x8530 z8531 = x8531 z8532 = x8532 z8533 = x8533 z8534 = x8534 z8535 = x8535 z8536 = x8536 z8537 = x8537 z8538 = x8538 z8539 = x8539 z8540 = x8540 z8541 = x8541 z8542 = x8542 z8543 = x8543 z8544 = x8544 z8545 = x8545 z8546 = x8546 z8547 = x8547 z8548 = x8548 z8549 = x8549 z8550 = x8550 z8551 = x8551 z8552 = x8552 z8553 = x8553 z8554 = x8554 z8555 = x8555 z8556 = x8556 z8557 = x8557 z8558 = x8558 z8559 = x8559 z8560 = x8560 z8561 = x8561 z8562 = x8562 z8563 = x8563 z8564 = x8564 z8565 = x8565 z8566 = x8566 z8567 = x8567 z8568 = x8568 z8569 = x8569 z8570 = x8570 z8571 = x8571 z8572 = x8572 z8573 = x8573 z8574 = x8574 z8575 = x8575 z8576 = x8576 z8577 = x8577 z8578 = x8578 z8579 = x8579 z8580 = x8580 z8581 = x8581 z8582 = x8582 z8583 = x8583 z8584 = x8584 z8585 = x8585 z8586 = x8586 z8587 = x8587 z8588 = x8588 z8589 = x8589 z8590 = x8590 z8591 = x8591 z8592 = x8592 z8593 = x8593 z8594 = x8594 z8595 = x8595 z8596 = x8596 z8597 = x8597 z8598 = x8598 z8599 = x8599 z8600 = x8600 z8601 = x8601 z8602 = x8602 z8603 = x8603 z8604 = x8604 z8605 = x8605 z8606 = x8606 z8607 = x8607 z8608 = x8608 z8609 = x8609 z8610 = x8610 z8611 = x8611 z8612 = x8612 z8613 = x8613 z8614 = x8614 z8615 = x8615 z8616 = x8616 z8617 = x8617 z8618 = x8618 z8619 = x8619 z8620 = x8620 z8621 = x8621 z8622 = x8622 z8623 = x8623 z8624 = x8624 z8625 = x8625 z8626 = x8626 z8627 = x8627 z8628 = x8628 z8629 = x8629 z8630 = x8630 z8631 = x8631 z8632 = x8632 z8633 = x8633 z8634 = x8634 z8635 = x8635 z8636 = x8636 z8637 = x8637 z8638 = x8638 z8639 = x8639 z8640 = x8640 z8641 = x8641 z8642 = x8642 z8643 = x8643 z8644 = x8644 z8645 = x8645 z8646 = x8646 z8647 = x8647 z8648 = x8648 z8649 = x8649 z8650 = x8650 z8651 = x8651 z8652 = x8652 z8653 = x8653 z8654 = x8654 z8655 = x8655 z8656 = x8656 z8657 = x8657 z8658 = x8658 z8659 = x8659 z8660 = x8660 z8661 = x8661 z8662 = x8662 z8663 = x8663 z8664 = x8664 z8665 = x8665 z8666 = x8666 z8667 = x8667 z8668 = x8668 z8669 = x8669 z8670 = x8670 z8671 = x8671 z8672 = x8672 z8673 = x8673 z8674 = x8674 z8675 = x8675 z8676 = x8676 z8677 = x8677 z8678 = x8678 z8679 = x8679 z8680 = x8680 z8681 = x8681 z8682 = x8682 z8683 = x8683 z8684 = x8684 z8685 = x8685 z8686 = x8686 z8687 = x8687 z8688 = x8688 z8689 = x8689 z8690 = x8690 z8691 = x8691 z8692 = x8692 z8693 = x8693 z8694 = x8694 z8695 = x8695 z8696 = x8696 z8697 = x8697 z8698 = x8698 z8699 = x8699 z8700 = x8700 z8701 = x8701 z8702 = x8702 z8703 = x8703 z8704 = x8704 z8705 = x8705 z8706 = x8706 z8707 = x8707 z8708 = x8708 z8709 = x8709 z8710 = x8710 z8711 = x8711 z8712 = x8712 z8713 = x8713 z8714 = x8714 z8715 = x8715 z8716 = x8716 z8717 = x8717 z8718 = x8718 z8719 = x8719 z8720 = x8720 z8721 = x8721 z8722 = x8722 z8723 = x8723 z8724 = x8724 z8725 = x8725 z8726 = x8726 z8727 = x8727 z8728 = x8728 z8729 = x8729 z8730 = x8730 z8731 = x8731 z8732 = x8732 z8733 = x8733 z8734 = x8734 z8735 = x8735 z8736 = x8736 z8737 = x8737 z8738 = x8738 z8739 = x8739 z8740 = x8740 z8741 = x8741 z8742 = x8742 z8743 = x8743 z8744 = x8744 z8745 = x8745 z8746 = x8746 z8747 = x8747 z8748 = x8748 z8749 = x8749 z8750 = x8750 z8751 = x8751 z8752 = x8752 z8753 = x8753 z8754 = x8754 z8755 = x8755 z8756 = x8756 z8757 = x8757 z8758 = x8758 z8759 = x8759 z8760 = x8760 z8761 = x8761 z8762 = x8762 z8763 = x8763 z8764 = x8764 z8765 = x8765 z8766 = x8766 z8767 = x8767 z8768 = x8768 z8769 = x8769 z8770 = x8770 z8771 = x8771 z8772 = x8772 z8773 = x8773 z8774 = x8774 z8775 = x8775 z8776 = x8776 z8777 = x8777 z8778 = x8778 z8779 = x8779 z8780 = x8780 z8781 = x8781 z8782 = x8782 z8783 = x8783 z8784 = x8784 z8785 = x8785 z8786 = x8786 z8787 = x8787 z8788 = x8788 z8789 = x8789 z8790 = x8790 z8791 = x8791 z8792 = x8792 z8793 = x8793 z8794 = x8794 z8795 = x8795 z8796 = x8796 z8797 = x8797 z8798 = x8798 z8799 = x8799 z8800 = x8800 z8801 = x8801 z8802 = x8802 z8803 = x8803 z8804 = x8804 z8805 = x8805 z8806 = x8806 z8807 = x8807 z8808 = x8808 z8809 = x8809 z8810 = x8810 z8811 = x8811 z8812 = x8812 z8813 = x8813 z8814 = x8814 z8815 = x8815 z8816 = x8816 z8817 = x8817 z8818 = x8818 z8819 = x8819 z8820 = x8820 z8821 = x8821 z8822 = x8822 z8823 = x8823 z8824 = x8824 z8825 = x8825 z8826 = x8826 z8827 = x8827 z8828 = x8828 z8829 = x8829 z8830 = x8830 z8831 = x8831 z8832 = x8832 z8833 = x8833 z8834 = x8834 z8835 = x8835 z8836 = x8836 z8837 = x8837 z8838 = x8838 z8839 = x8839 z8840 = x8840 z8841 = x8841 z8842 = x8842 z8843 = x8843 z8844 = x8844 z8845 = x8845 z8846 = x8846 z8847 = x8847 z8848 = x8848 z8849 = x8849 z8850 = x8850 z8851 = x8851 z8852 = x8852 z8853 = x8853 z8854 = x8854 z8855 = x8855 z8856 = x8856 z8857 = x8857 z8858 = x8858 z8859 = x8859 z8860 = x8860 z8861 = x8861 z8862 = x8862 z8863 = x8863 z8864 = x8864 z8865 = x8865 z8866 = x8866 z8867 = x8867 z8868 = x8868 z8869 = x8869 z8870 = x8870 z8871 = x8871 z8872 = x8872 z8873 = x8873 z8874 = x8874 z8875 = x8875 z8876 = x8876 z8877 = x8877 z8878 = x8878 z8879 = x8879 z8880 = x8880 z8881 = x8881 z8882 = x8882 z8883 = x8883 z8884 = x8884 z8885 = x8885 z8886 = x8886 z8887 = x8887 z8888 = x8888 z8889 = x8889 z8890 = x8890 z8891 = x8891 z8892 = x8892 z8893 = x8893 z8894 = x8894 z8895 = x8895 z8896 = x8896 z8897 = x8897 z8898 = x8898 z8899 = x8899 z8900 = x8900 z8901 = x8901 z8902 = x8902 z8903 = x8903 z8904 = x8904 z8905 = x8905 z8906 = x8906 z8907 = x8907 z8908 = x8908 z8909 = x8909 z8910 = x8910 z8911 = x8911 z8912 = x8912 z8913 = x8913 z8914 = x8914 z8915 = x8915 z8916 = x8916 z8917 = x8917 z8918 = x8918 z8919 = x8919 z8920 = x8920 z8921 = x8921 z8922 = x8922 z8923 = x8923 z8924 = x8924 z8925 = x8925 z8926 = x8926 z8927 = x8927 z8928 = x8928 z8929 = x8929 z8930 = x8930 z8931 = x8931 z8932 = x8932 z8933 = x8933 z8934 = x8934 z8935 = x8935 z8936 = x8936 z8937 = x8937 z8938 = x8938 z8939 = x8939 z8940 = x8940 z8941 = x8941 z8942 = x8942 z8943 = x8943 z8944 = x8944 z8945 = x8945 z8946 = x8946 z8947 = x8947 z8948 = x8948 z8949 = x8949 z8950 = x8950 z8951 = x8951 z8952 = x8952 z8953 = x8953 z8954 = x8954 z8955 = x8955 z8956 = x8956 z8957 = x8957 z8958 = x8958 z8959 = x8959 z8960 = x8960 z8961 = x8961 z8962 = x8962 z8963 = x8963 z8964 = x8964 z8965 = x8965 z8966 = x8966 z8967 = x8967 z8968 = x8968 z8969 = x8969 z8970 = x8970 z8971 = x8971 z8972 = x8972 z8973 = x8973 z8974 = x8974 z8975 = x8975 z8976 = x8976 z8977 = x8977 z8978 = x8978 z8979 = x8979 z8980 = x8980 z8981 = x8981 z8982 = x8982 z8983 = x8983 z8984 = x8984 z8985 = x8985 z8986 = x8986 z8987 = x8987 z8988 = x8988 z8989 = x8989 z8990 = x8990 z8991 = x8991 z8992 = x8992 z8993 = x8993 z8994 = x8994 z8995 = x8995 z8996 = x8996 z8997 = x8997 z8998 = x8998 z8999 = x8999 z9000 = x9000 z9001 = x9001 z9002 = x9002 z9003 = x9003 z9004 = x9004 z9005 = x9005 z9006 = x9006 z9007 = x9007 z9008 = x9008 z9009 = x9009 z9010 = x9010 z9011 = x9011 z9012 = x9012 z9013 = x9013 z9014 = x9014 z9015 = x9015 z9016 = x9016 z9017 = x9017 z9018 = x9018 z9019 = x9019 z9020 = x9020 z9021 = x9021 z9022 = x9022 z9023 = x9023 z9024 = x9024 z9025 = x9025 z9026 = x9026 z9027 = x9027 z9028 = x9028 z9029 = x9029 z9030 = x9030 z9031 = x9031 z9032 = x9032 z9033 = x9033 z9034 = x9034 z9035 = x9035 z9036 = x9036 z9037 = x9037 z9038 = x9038 z9039 = x9039 z9040 = x9040 z9041 = x9041 z9042 = x9042 z9043 = x9043 z9044 = x9044 z9045 = x9045 z9046 = x9046 z9047 = x9047 z9048 = x9048 z9049 = x9049 z9050 = x9050 z9051 = x9051 z9052 = x9052 z9053 = x9053 z9054 = x9054 z9055 = x9055 z9056 = x9056 z9057 = x9057 z9058 = x9058 z9059 = x9059 z9060 = x9060 z9061 = x9061 z9062 = x9062 z9063 = x9063 z9064 = x9064 z9065 = x9065 z9066 = x9066 z9067 = x9067 z9068 = x9068 z9069 = x9069 z9070 = x9070 z9071 = x9071 z9072 = x9072 z9073 = x9073 z9074 = x9074 z9075 = x9075 z9076 = x9076 z9077 = x9077 z9078 = x9078 z9079 = x9079 z9080 = x9080 z9081 = x9081 z9082 = x9082 z9083 = x9083 z9084 = x9084 z9085 = x9085 z9086 = x9086 z9087 = x9087 z9088 = x9088 z9089 = x9089 z9090 = x9090 z9091 = x9091 z9092 = x9092 z9093 = x9093 z9094 = x9094 z9095 = x9095 z9096 = x9096 z9097 = x9097 z9098 = x9098 z9099 = x9099 z9100 = x9100 z9101 = x9101 z9102 = x9102 z9103 = x9103 z9104 = x9104 z9105 = x9105 z9106 = x9106 z9107 = x9107 z9108 = x9108 z9109 = x9109 z9110 = x9110 z9111 = x9111 z9112 = x9112 z9113 = x9113 z9114 = x9114 z9115 = x9115 z9116 = x9116 z9117 = x9117 z9118 = x9118 z9119 = x9119 z9120 = x9120 z9121 = x9121 z9122 = x9122 z9123 = x9123 z9124 = x9124 z9125 = x9125 z9126 = x9126 z9127 = x9127 z9128 = x9128 z9129 = x9129 z9130 = x9130 z9131 = x9131 z9132 = x9132 z9133 = x9133 z9134 = x9134 z9135 = x9135 z9136 = x9136 z9137 = x9137 z9138 = x9138 z9139 = x9139 z9140 = x9140 z9141 = x9141 z9142 = x9142 z9143 = x9143 z9144 = x9144 z9145 = x9145 z9146 = x9146 z9147 = x9147 z9148 = x9148 z9149 = x9149 z9150 = x9150 z9151 = x9151 z9152 = x9152 z9153 = x9153 z9154 = x9154 z9155 = x9155 z9156 = x9156 z9157 = x9157 z9158 = x9158 z9159 = x9159 z9160 = x9160 z9161 = x9161 z9162 = x9162 z9163 = x9163 z9164 = x9164 z9165 = x9165 z9166 = x9166 z9167 = x9167 z9168 = x9168 z9169 = x9169 z9170 = x9170 z9171 = x9171 z9172 = x9172 z9173 = x9173 z9174 = x9174 z9175 = x9175 z9176 = x9176 z9177 = x9177 z9178 = x9178 z9179 = x9179 z9180 = x9180 z9181 = x9181 z9182 = x9182 z9183 = x9183 z9184 = x9184 z9185 = x9185 z9186 = x9186 z9187 = x9187 z9188 = x9188 z9189 = x9189 z9190 = x9190 z9191 = x9191 z9192 = x9192 z9193 = x9193 z9194 = x9194 z9195 = x9195 z9196 = x9196 z9197 = x9197 z9198 = x9198 z9199 = x9199 z9200 = x9200 z9201 = x9201 z9202 = x9202 z9203 = x9203 z9204 = x9204 z9205 = x9205 z9206 = x9206 z9207 = x9207 z9208 = x9208 z9209 = x9209 z9210 = x9210 z9211 = x9211 z9212 = x9212 z9213 = x9213 z9214 = x9214 z9215 = x9215 z9216 = x9216 z9217 = x9217 z9218 = x9218 z9219 = x9219 z9220 = x9220 z9221 = x9221 z9222 = x9222 z9223 = x9223 z9224 = x9224 z9225 = x9225 z9226 = x9226 z9227 = x9227 z9228 = x9228 z9229 = x9229 z9230 = x9230 z9231 = x9231 z9232 = x9232 z9233 = x9233 z9234 = x9234 z9235 = x9235 z9236 = x9236 z9237 = x9237 z9238 = x9238 z9239 = x9239 z9240 = x9240 z9241 = x9241 z9242 = x9242 z9243 = x9243 z9244 = x9244 z9245 = x9245 z9246 = x9246 z9247 = x9247 z9248 = x9248 z9249 = x9249 z9250 = x9250 z9251 = x9251 z9252 = x9252 z9253 = x9253 z9254 = x9254 z9255 = x9255 z9256 = x9256 z9257 = x9257 z9258 = x9258 z9259 = x9259 z9260 = x9260 z9261 = x9261 z9262 = x9262 z9263 = x9263 z9264 = x9264 z9265 = x9265 z9266 = x9266 z9267 = x9267 z9268 = x9268 z9269 = x9269 z9270 = x9270 z9271 = x9271 z9272 = x9272 z9273 = x9273 z9274 = x9274 z9275 = x9275 z9276 = x9276 z9277 = x9277 z9278 = x9278 z9279 = x9279 z9280 = x9280 z9281 = x9281 z9282 = x9282 z9283 = x9283 z9284 = x9284 z9285 = x9285 z9286 = x9286 z9287 = x9287 z9288 = x9288 z9289 = x9289 z9290 = x9290 z9291 = x9291 z9292 = x9292 z9293 = x9293 z9294 = x9294 z9295 = x9295 z9296 = x9296 z9297 = x9297 z9298 = x9298 z9299 = x9299 z9300 = x9300 z9301 = x9301 z9302 = x9302 z9303 = x9303 z9304 = x9304 z9305 = x9305 z9306 = x9306 z9307 = x9307 z9308 = x9308 z9309 = x9309 z9310 = x9310 z9311 = x9311 z9312 = x9312 z9313 = x9313 z9314 = x9314 z9315 = x9315 z9316 = x9316 z9317 = x9317 z9318 = x9318 z9319 = x9319 z9320 = x9320 z9321 = x9321 z9322 = x9322 z9323 = x9323 z9324 = x9324 z9325 = x9325 z9326 = x9326 z9327 = x9327 z9328 = x9328 z9329 = x9329 z9330 = x9330 z9331 = x9331 z9332 = x9332 z9333 = x9333 z9334 = x9334 z9335 = x9335 z9336 = x9336 z9337 = x9337 z9338 = x9338 z9339 = x9339 z9340 = x9340 z9341 = x9341 z9342 = x9342 z9343 = x9343 z9344 = x9344 z9345 = x9345 z9346 = x9346 z9347 = x9347 z9348 = x9348 z9349 = x9349 z9350 = x9350 z9351 = x9351 z9352 = x9352 z9353 = x9353 z9354 = x9354 z9355 = x9355 z9356 = x9356 z9357 = x9357 z9358 = x9358 z9359 = x9359 z9360 = x9360 z9361 = x9361 z9362 = x9362 z9363 = x9363 z9364 = x9364 z9365 = x9365 z9366 = x9366 z9367 = x9367 z9368 = x9368 z9369 = x9369 z9370 = x9370 z9371 = x9371 z9372 = x9372 z9373 = x9373 z9374 = x9374 z9375 = x9375 z9376 = x9376 z9377 = x9377 z9378 = x9378 z9379 = x9379 z9380 = x9380 z9381 = x9381 z9382 = x9382 z9383 = x9383 z9384 = x9384 z9385 = x9385 z9386 = x9386 z9387 = x9387 z9388 = x9388 z9389 = x9389 z9390 = x9390 z9391 = x9391 z9392 = x9392 z9393 = x9393 z9394 = x9394 z9395 = x9395 z9396 = x9396 z9397 = x9397 z9398 = x9398 z9399 = x9399 z9400 = x9400 z9401 = x9401 z9402 = x9402 z9403 = x9403 z9404 = x9404 z9405 = x9405 z9406 = x9406 z9407 = x9407 z9408 = x9408 z9409 = x9409 z9410 = x9410 z9411 = x9411 z9412 = x9412 z9413 = x9413 z9414 = x9414 z9415 = x9415 z9416 = x9416 z9417 = x9417 z9418 = x9418 z9419 = x9419 z9420 = x9420 z9421 = x9421 z9422 = x9422 z9423 = x9423 z9424 = x9424 z9425 = x9425 z9426 = x9426 z9427 = x9427 z9428 = x9428 z9429 = x9429 z9430 = x9430 z9431 = x9431 z9432 = x9432 z9433 = x9433 z9434 = x9434 z9435 = x9435 z9436 = x9436 z9437 = x9437 z9438 = x9438 z9439 = x9439 z9440 = x9440 z9441 = x9441 z9442 = x9442 z9443 = x9443 z9444 = x9444 z9445 = x9445 z9446 = x9446 z9447 = x9447 z9448 = x9448 z9449 = x9449 z9450 = x9450 z9451 = x9451 z9452 = x9452 z9453 = x9453 z9454 = x9454 z9455 = x9455 z9456 = x9456 z9457 = x9457 z9458 = x9458 z9459 = x9459 z9460 = x9460 z9461 = x9461 z9462 = x9462 z9463 = x9463 z9464 = x9464 z9465 = x9465 z9466 = x9466 z9467 = x9467 z9468 = x9468 z9469 = x9469 z9470 = x9470 z9471 = x9471 z9472 = x9472 z9473 = x9473 z9474 = x9474 z9475 = x9475 z9476 = x9476 z9477 = x9477 z9478 = x9478 z9479 = x9479 z9480 = x9480 z9481 = x9481 z9482 = x9482 z9483 = x9483 z9484 = x9484 z9485 = x9485 z9486 = x9486 z9487 = x9487 z9488 = x9488 z9489 = x9489 z9490 = x9490 z9491 = x9491 z9492 = x9492 z9493 = x9493 z9494 = x9494 z9495 = x9495 z9496 = x9496 z9497 = x9497 z9498 = x9498 z9499 = x9499 z9500 = x9500 z9501 = x9501 z9502 = x9502 z9503 = x9503 z9504 = x9504 z9505 = x9505 z9506 = x9506 z9507 = x9507 z9508 = x9508 z9509 = x9509 z9510 = x9510 z9511 = x9511 z9512 = x9512 z9513 = x9513 z9514 = x9514 z9515 = x9515 z9516 = x9516 z9517 = x9517 z9518 = x9518 z9519 = x9519 z9520 = x9520 z9521 = x9521 z9522 = x9522 z9523 = x9523 z9524 = x9524 z9525 = x9525 z9526 = x9526 z9527 = x9527 z9528 = x9528 z9529 = x9529 z9530 = x9530 z9531 = x9531 z9532 = x9532 z9533 = x9533 z9534 = x9534 z9535 = x9535 z9536 = x9536 z9537 = x9537 z9538 = x9538 z9539 = x9539 z9540 = x9540 z9541 = x9541 z9542 = x9542 z9543 = x9543 z9544 = x9544 z9545 = x9545 z9546 = x9546 z9547 = x9547 z9548 = x9548 z9549 = x9549 z9550 = x9550 z9551 = x9551 z9552 = x9552 z9553 = x9553 z9554 = x9554 z9555 = x9555 z9556 = x9556 z9557 = x9557 z9558 = x9558 z9559 = x9559 z9560 = x9560 z9561 = x9561 z9562 = x9562 z9563 = x9563 z9564 = x9564 z9565 = x9565 z9566 = x9566 z9567 = x9567 z9568 = x9568 z9569 = x9569 z9570 = x9570 z9571 = x9571 z9572 = x9572 z9573 = x9573 z9574 = x9574 z9575 = x9575 z9576 = x9576 z9577 = x9577 z9578 = x9578 z9579 = x9579 z9580 = x9580 z9581 = x9581 z9582 = x9582 z9583 = x9583 z9584 = x9584 z9585 = x9585 z9586 = x9586 z9587 = x9587 z9588 = x9588 z9589 = x9589 z9590 = x9590 z9591 = x9591 z9592 = x9592 z9593 = x9593 z9594 = x9594 z9595 = x9595 z9596 = x9596 z9597 = x9597 z9598 = x9598 z9599 = x9599 z9600 = x9600 z9601 = x9601 z9602 = x9602 z9603 = x9603 z9604 = x9604 z9605 = x9605 z9606 = x9606 z9607 = x9607 z9608 = x9608 z9609 = x9609 z9610 = x9610 z9611 = x9611 z9612 = x9612 z9613 = x9613 z9614 = x9614 z9615 = x9615 z9616 = x9616 z9617 = x9617 z9618 = x9618 z9619 = x9619 z9620 = x9620 z9621 = x9621 z9622 = x9622 z9623 = x9623 z9624 = x9624 z9625 = x9625 z9626 = x9626 z9627 = x9627 z9628 = x9628 z9629 = x9629 z9630 = x9630 z9631 = x9631 z9632 = x9632 z9633 = x9633 z9634 = x9634 z9635 = x9635 z9636 = x9636 z9637 = x9637 z9638 = x9638 z9639 = x9639 z9640 = x9640 z9641 = x9641 z9642 = x9642 z9643 = x9643 z9644 = x9644 z9645 = x9645 z9646 = x9646 z9647 = x9647 z9648 = x9648 z9649 = x9649 z9650 = x9650 z9651 = x9651 z9652 = x9652 z9653 = x9653 z9654 = x9654 z9655 = x9655 z9656 = x9656 z9657 = x9657 z9658 = x9658 z9659 = x9659 z9660 = x9660 z9661 = x9661 z9662 = x9662 z9663 = x9663 z9664 = x9664 z9665 = x9665 z9666 = x9666 z9667 = x9667 z9668 = x9668 z9669 = x9669 z9670 = x9670 z9671 = x9671 z9672 = x9672 z9673 = x9673 z9674 = x9674 z9675 = x9675 z9676 = x9676 z9677 = x9677 z9678 = x9678 z9679 = x9679 z9680 = x9680 z9681 = x9681 z9682 = x9682 z9683 = x9683 z9684 = x9684 z9685 = x9685 z9686 = x9686 z9687 = x9687 z9688 = x9688 z9689 = x9689 z9690 = x9690 z9691 = x9691 z9692 = x9692 z9693 = x9693 z9694 = x9694 z9695 = x9695 z9696 = x9696 z9697 = x9697 z9698 = x9698 z9699 = x9699 z9700 = x9700 z9701 = x9701 z9702 = x9702 z9703 = x9703 z9704 = x9704 z9705 = x9705 z9706 = x9706 z9707 = x9707 z9708 = x9708 z9709 = x9709 z9710 = x9710 z9711 = x9711 z9712 = x9712 z9713 = x9713 z9714 = x9714 z9715 = x9715 z9716 = x9716 z9717 = x9717 z9718 = x9718 z9719 = x9719 z9720 = x9720 z9721 = x9721 z9722 = x9722 z9723 = x9723 z9724 = x9724 z9725 = x9725 z9726 = x9726 z9727 = x9727 z9728 = x9728 z9729 = x9729 z9730 = x9730 z9731 = x9731 z9732 = x9732 z9733 = x9733 z9734 = x9734 z9735 = x9735 z9736 = x9736 z9737 = x9737 z9738 = x9738 z9739 = x9739 z9740 = x9740 z9741 = x9741 z9742 = x9742 z9743 = x9743 z9744 = x9744 z9745 = x9745 z9746 = x9746 z9747 = x9747 z9748 = x9748 z9749 = x9749 z9750 = x9750 z9751 = x9751 z9752 = x9752 z9753 = x9753 z9754 = x9754 z9755 = x9755 z9756 = x9756 z9757 = x9757 z9758 = x9758 z9759 = x9759 z9760 = x9760 z9761 = x9761 z9762 = x9762 z9763 = x9763 z9764 = x9764 z9765 = x9765 z9766 = x9766 z9767 = x9767 z9768 = x9768 z9769 = x9769 z9770 = x9770 z9771 = x9771 z9772 = x9772 z9773 = x9773 z9774 = x9774 z9775 = x9775 z9776 = x9776 z9777 = x9777 z9778 = x9778 z9779 = x9779 z9780 = x9780 z9781 = x9781 z9782 = x9782 z9783 = x9783 z9784 = x9784 z9785 = x9785 z9786 = x9786 z9787 = x9787 z9788 = x9788 z9789 = x9789 z9790 = x9790 z9791 = x9791 z9792 = x9792 z9793 = x9793 z9794 = x9794 z9795 = x9795 z9796 = x9796 z9797 = x9797 z9798 = x9798 z9799 = x9799 z9800 = x9800 z9801 = x9801 z9802 = x9802 z9803 = x9803 z9804 = x9804 z9805 = x9805 z9806 = x9806 z9807 = x9807 z9808 = x9808 z9809 = x9809 z9810 = x9810 z9811 = x9811 z9812 = x9812 z9813 = x9813 z9814 = x9814 z9815 = x9815 z9816 = x9816 z9817 = x9817 z9818 = x9818 z9819 = x9819 z9820 = x9820 z9821 = x9821 z9822 = x9822 z9823 = x9823 z9824 = x9824 z9825 = x9825 z9826 = x9826 z9827 = x9827 z9828 = x9828 z9829 = x9829 z9830 = x9830 z9831 = x9831 z9832 = x9832 z9833 = x9833 z9834 = x9834 z9835 = x9835 z9836 = x9836 z9837 = x9837 z9838 = x9838 z9839 = x9839 z9840 = x9840 z9841 = x9841 z9842 = x9842 z9843 = x9843 z9844 = x9844 z9845 = x9845 z9846 = x9846 z9847 = x9847 z9848 = x9848 z9849 = x9849 z9850 = x9850 z9851 = x9851 z9852 = x9852 z9853 = x9853 z9854 = x9854 z9855 = x9855 z9856 = x9856 z9857 = x9857 z9858 = x9858 z9859 = x9859 z9860 = x9860 z9861 = x9861 z9862 = x9862 z9863 = x9863 z9864 = x9864 z9865 = x9865 z9866 = x9866 z9867 = x9867 z9868 = x9868 z9869 = x9869 z9870 = x9870 z9871 = x9871 z9872 = x9872 z9873 = x9873 z9874 = x9874 z9875 = x9875 z9876 = x9876 z9877 = x9877 z9878 = x9878 z9879 = x9879 z9880 = x9880 z9881 = x9881 z9882 = x9882 z9883 = x9883 z9884 = x9884 z9885 = x9885 z9886 = x9886 z9887 = x9887 z9888 = x9888 z9889 = x9889 z9890 = x9890 z9891 = x9891 z9892 = x9892 z9893 = x9893 z9894 = x9894 z9895 = x9895 z9896 = x9896 z9897 = x9897 z9898 = x9898 z9899 = x9899 z9900 = x9900 z9901 = x9901 z9902 = x9902 z9903 = x9903 z9904 = x9904 z9905 = x9905 z9906 = x9906 z9907 = x9907 z9908 = x9908 z9909 = x9909 z9910 = x9910 z9911 = x9911 z9912 = x9912 z9913 = x9913 z9914 = x9914 z9915 = x9915 z9916 = x9916 z9917 = x9917 z9918 = x9918 z9919 = x9919 z9920 = x9920 z9921 = x9921 z9922 = x9922 z9923 = x9923 z9924 = x9924 z9925 = x9925 z9926 = x9926 z9927 = x9927 z9928 = x9928 z9929 = x9929 z9930 = x9930 z9931 = x9931 z9932 = x9932 z9933 = x9933 z9934 = x9934 z9935 = x9935 z9936 = x9936 z9937 = x9937 z9938 = x9938 z9939 = x9939 z9940 = x9940 z9941 = x9941 z9942 = x9942 z9943 = x9943 z9944 = x9944 z9945 = x9945 z9946 = x9946 z9947 = x9947 z9948 = x9948 z9949 = x9949 z9950 = x9950 z9951 = x9951 z9952 = x9952 z9953 = x9953 z9954 = x9954 z9955 = x9955 z9956 = x9956 z9957 = x9957 z9958 = x9958 z9959 = x9959 z9960 = x9960 z9961 = x9961 z9962 = x9962 z9963 = x9963 z9964 = x9964 z9965 = x9965 z9966 = x9966 z9967 = x9967 z9968 = x9968 z9969 = x9969 z9970 = x9970 z9971 = x9971 z9972 = x9972 z9973 = x9973 z9974 = x9974 z9975 = x9975 z9976 = x9976 z9977 = x9977 z9978 = x9978 z9979 = x9979 z9980 = x9980 z9981 = x9981 z9982 = x9982 z9983 = x9983 z9984 = x9984 z9985 = x9985 z9986 = x9986 z9987 = x9987 z9988 = x9988 z9989 = x9989 z9990 = x9990 z9991 = x9991 z9992 = x9992 z9993 = x9993 z9994 = x9994 z9995 = x9995 z9996 = x9996 z9997 = x9997 z9998 = x9998 z9999 = x9999 z10000 = x10000 z10001 = x10001 z10002 = x10002 z10003 = x10003 z10004 = x10004 z10005 = x10005 z10006 = x10006 z10007 = x10007 z10008 = x10008 z10009 = x10009 z10010 = x10010 z10011 = x10011 z10012 = x10012 z10013 = x10013 z10014 = x10014 z10015 = x10015 z10016 = x10016 z10017 = x10017 z10018 = x10018 z10019 = x10019 z10020 = x10020 z10021 = x10021 z10022 = x10022 z10023 = x10023 z10024 = x10024 z10025 = x10025 z10026 = x10026 z10027 = x10027 z10028 = x10028 z10029 = x10029 z10030 = x10030 z10031 = x10031 z10032 = x10032 z10033 = x10033 z10034 = x10034 z10035 = x10035 z10036 = x10036 z10037 = x10037 z10038 = x10038 z10039 = x10039 z10040 = x10040 z10041 = x10041 z10042 = x10042 z10043 = x10043 z10044 = x10044 z10045 = x10045 z10046 = x10046 z10047 = x10047 z10048 = x10048 z10049 = x10049 z10050 = x10050 z10051 = x10051 z10052 = x10052 z10053 = x10053 z10054 = x10054 z10055 = x10055 z10056 = x10056 z10057 = x10057 z10058 = x10058 z10059 = x10059 z10060 = x10060 z10061 = x10061 z10062 = x10062 z10063 = x10063 z10064 = x10064 z10065 = x10065 z10066 = x10066 z10067 = x10067 z10068 = x10068 z10069 = x10069 z10070 = x10070 z10071 = x10071 z10072 = x10072 z10073 = x10073 z10074 = x10074 z10075 = x10075 z10076 = x10076 z10077 = x10077 z10078 = x10078 z10079 = x10079 z10080 = x10080 z10081 = x10081 z10082 = x10082 z10083 = x10083 z10084 = x10084 z10085 = x10085 z10086 = x10086 z10087 = x10087 z10088 = x10088 z10089 = x10089 z10090 = x10090 z10091 = x10091 z10092 = x10092 z10093 = x10093 z10094 = x10094 z10095 = x10095 z10096 = x10096 z10097 = x10097 z10098 = x10098 z10099 = x10099 z10100 = x10100 z10101 = x10101 z10102 = x10102 z10103 = x10103 z10104 = x10104 z10105 = x10105 z10106 = x10106 z10107 = x10107 z10108 = x10108 z10109 = x10109 z10110 = x10110 z10111 = x10111 z10112 = x10112 z10113 = x10113 z10114 = x10114 z10115 = x10115 z10116 = x10116 z10117 = x10117 z10118 = x10118 z10119 = x10119 z10120 = x10120 z10121 = x10121 z10122 = x10122 z10123 = x10123 z10124 = x10124 z10125 = x10125 z10126 = x10126 z10127 = x10127 z10128 = x10128 z10129 = x10129 z10130 = x10130 z10131 = x10131 z10132 = x10132 z10133 = x10133 z10134 = x10134 z10135 = x10135 z10136 = x10136 z10137 = x10137 z10138 = x10138 z10139 = x10139 z10140 = x10140 z10141 = x10141 z10142 = x10142 z10143 = x10143 z10144 = x10144 z10145 = x10145 z10146 = x10146 z10147 = x10147 z10148 = x10148 z10149 = x10149 z10150 = x10150 z10151 = x10151 z10152 = x10152 z10153 = x10153 z10154 = x10154 z10155 = x10155 z10156 = x10156 z10157 = x10157 z10158 = x10158 z10159 = x10159 z10160 = x10160 z10161 = x10161 z10162 = x10162 z10163 = x10163 z10164 = x10164 z10165 = x10165 z10166 = x10166 z10167 = x10167 z10168 = x10168 z10169 = x10169 z10170 = x10170 z10171 = x10171 z10172 = x10172 z10173 = x10173 z10174 = x10174 z10175 = x10175 z10176 = x10176 z10177 = x10177 z10178 = x10178 z10179 = x10179 z10180 = x10180 z10181 = x10181 z10182 = x10182 z10183 = x10183 z10184 = x10184 z10185 = x10185 z10186 = x10186 z10187 = x10187 z10188 = x10188 z10189 = x10189 z10190 = x10190 z10191 = x10191 z10192 = x10192 z10193 = x10193 z10194 = x10194 z10195 = x10195 z10196 = x10196 z10197 = x10197 z10198 = x10198 z10199 = x10199 z10200 = x10200 z10201 = x10201 z10202 = x10202 z10203 = x10203 z10204 = x10204 z10205 = x10205 z10206 = x10206 z10207 = x10207 z10208 = x10208 z10209 = x10209 z10210 = x10210 z10211 = x10211 z10212 = x10212 z10213 = x10213 z10214 = x10214 z10215 = x10215 z10216 = x10216 z10217 = x10217 z10218 = x10218 z10219 = x10219 z10220 = x10220 z10221 = x10221 z10222 = x10222 z10223 = x10223 z10224 = x10224 z10225 = x10225 z10226 = x10226 z10227 = x10227 z10228 = x10228 z10229 = x10229 z10230 = x10230 z10231 = x10231 z10232 = x10232 z10233 = x10233 z10234 = x10234 z10235 = x10235 z10236 = x10236 z10237 = x10237 z10238 = x10238 z10239 = x10239 z10240 = x10240 z10241 = x10241 z10242 = x10242 z10243 = x10243 z10244 = x10244 z10245 = x10245 z10246 = x10246 z10247 = x10247 z10248 = x10248 z10249 = x10249 z10250 = x10250 z10251 = x10251 z10252 = x10252 z10253 = x10253 z10254 = x10254 z10255 = x10255 z10256 = x10256 z10257 = x10257 z10258 = x10258 z10259 = x10259 z10260 = x10260 z10261 = x10261 z10262 = x10262 z10263 = x10263 z10264 = x10264 z10265 = x10265 z10266 = x10266 z10267 = x10267 z10268 = x10268 z10269 = x10269 z10270 = x10270 z10271 = x10271 z10272 = x10272 z10273 = x10273 z10274 = x10274 z10275 = x10275 z10276 = x10276 z10277 = x10277 z10278 = x10278 z10279 = x10279 z10280 = x10280 z10281 = x10281 z10282 = x10282 z10283 = x10283 z10284 = x10284 z10285 = x10285 z10286 = x10286 z10287 = x10287 z10288 = x10288 z10289 = x10289 z10290 = x10290 z10291 = x10291 z10292 = x10292 z10293 = x10293 z10294 = x10294 z10295 = x10295 z10296 = x10296 z10297 = x10297 z10298 = x10298 z10299 = x10299 z10300 = x10300 z10301 = x10301 z10302 = x10302 z10303 = x10303 z10304 = x10304 z10305 = x10305 z10306 = x10306 z10307 = x10307 z10308 = x10308 z10309 = x10309 z10310 = x10310 z10311 = x10311 z10312 = x10312 z10313 = x10313 z10314 = x10314 z10315 = x10315 z10316 = x10316 z10317 = x10317 z10318 = x10318 z10319 = x10319 z10320 = x10320 z10321 = x10321 z10322 = x10322 z10323 = x10323 z10324 = x10324 z10325 = x10325 z10326 = x10326 z10327 = x10327 z10328 = x10328 z10329 = x10329 z10330 = x10330 z10331 = x10331 z10332 = x10332 z10333 = x10333 z10334 = x10334 z10335 = x10335 z10336 = x10336 z10337 = x10337 z10338 = x10338 z10339 = x10339 z10340 = x10340 z10341 = x10341 z10342 = x10342 z10343 = x10343 z10344 = x10344 z10345 = x10345 z10346 = x10346 z10347 = x10347 z10348 = x10348 z10349 = x10349 z10350 = x10350 z10351 = x10351 z10352 = x10352 z10353 = x10353 z10354 = x10354 z10355 = x10355 z10356 = x10356 z10357 = x10357 z10358 = x10358 z10359 = x10359 z10360 = x10360 z10361 = x10361 z10362 = x10362 z10363 = x10363 z10364 = x10364 z10365 = x10365 z10366 = x10366 z10367 = x10367 z10368 = x10368 z10369 = x10369 z10370 = x10370 z10371 = x10371 z10372 = x10372 z10373 = x10373 z10374 = x10374 z10375 = x10375 z10376 = x10376 z10377 = x10377 z10378 = x10378 z10379 = x10379 z10380 = x10380 z10381 = x10381 z10382 = x10382 z10383 = x10383 z10384 = x10384 z10385 = x10385 z10386 = x10386 z10387 = x10387 z10388 = x10388 z10389 = x10389 z10390 = x10390 z10391 = x10391 z10392 = x10392 z10393 = x10393 z10394 = x10394 z10395 = x10395 z10396 = x10396 z10397 = x10397 z10398 = x10398 z10399 = x10399 z10400 = x10400 z10401 = x10401 z10402 = x10402 z10403 = x10403 z10404 = x10404 z10405 = x10405 z10406 = x10406 z10407 = x10407 z10408 = x10408 z10409 = x10409 z10410 = x10410 z10411 = x10411 z10412 = x10412 z10413 = x10413 z10414 = x10414 z10415 = x10415 z10416 = x10416 z10417 = x10417 z10418 = x10418 z10419 = x10419 z10420 = x10420 z10421 = x10421 z10422 = x10422 z10423 = x10423 z10424 = x10424 z10425 = x10425 z10426 = x10426 z10427 = x10427 z10428 = x10428 z10429 = x10429 z10430 = x10430 z10431 = x10431 z10432 = x10432 z10433 = x10433 z10434 = x10434 z10435 = x10435 z10436 = x10436 z10437 = x10437 z10438 = x10438 z10439 = x10439 z10440 = x10440 z10441 = x10441 z10442 = x10442 z10443 = x10443 z10444 = x10444 z10445 = x10445 z10446 = x10446 z10447 = x10447 z10448 = x10448 z10449 = x10449 z10450 = x10450 z10451 = x10451 z10452 = x10452 z10453 = x10453 z10454 = x10454 z10455 = x10455 z10456 = x10456 z10457 = x10457 z10458 = x10458 z10459 = x10459 z10460 = x10460 z10461 = x10461 z10462 = x10462 z10463 = x10463 z10464 = x10464 z10465 = x10465 z10466 = x10466 z10467 = x10467 z10468 = x10468 z10469 = x10469 z10470 = x10470 z10471 = x10471 z10472 = x10472 z10473 = x10473 z10474 = x10474 z10475 = x10475 z10476 = x10476 z10477 = x10477 z10478 = x10478 z10479 = x10479 z10480 = x10480 z10481 = x10481 z10482 = x10482 z10483 = x10483 z10484 = x10484 z10485 = x10485 z10486 = x10486 z10487 = x10487 z10488 = x10488 z10489 = x10489 z10490 = x10490 z10491 = x10491 z10492 = x10492 z10493 = x10493 z10494 = x10494 z10495 = x10495 z10496 = x10496 z10497 = x10497 z10498 = x10498 z10499 = x10499 z10500 = x10500 z10501 = x10501 z10502 = x10502 z10503 = x10503 z10504 = x10504 z10505 = x10505 z10506 = x10506 z10507 = x10507 z10508 = x10508 z10509 = x10509 z10510 = x10510 z10511 = x10511 z10512 = x10512 z10513 = x10513 z10514 = x10514 z10515 = x10515 z10516 = x10516 z10517 = x10517 z10518 = x10518 z10519 = x10519 z10520 = x10520 z10521 = x10521 z10522 = x10522 z10523 = x10523 z10524 = x10524 z10525 = x10525 z10526 = x10526 z10527 = x10527 z10528 = x10528 z10529 = x10529 z10530 = x10530 z10531 = x10531 z10532 = x10532 z10533 = x10533 z10534 = x10534 z10535 = x10535 z10536 = x10536 z10537 = x10537 z10538 = x10538 z10539 = x10539 z10540 = x10540 z10541 = x10541 z10542 = x10542 z10543 = x10543 z10544 = x10544 z10545 = x10545 z10546 = x10546 z10547 = x10547 z10548 = x10548 z10549 = x10549 z10550 = x10550 z10551 = x10551 z10552 = x10552 z10553 = x10553 z10554 = x10554 z10555 = x10555 z10556 = x10556 z10557 = x10557 z10558 = x10558 z10559 = x10559 z10560 = x10560 z10561 = x10561 z10562 = x10562 z10563 = x10563 z10564 = x10564 z10565 = x10565 z10566 = x10566 z10567 = x10567 z10568 = x10568 z10569 = x10569 z10570 = x10570 z10571 = x10571 z10572 = x10572 z10573 = x10573 z10574 = x10574 z10575 = x10575 z10576 = x10576 z10577 = x10577 z10578 = x10578 z10579 = x10579 z10580 = x10580 z10581 = x10581 z10582 = x10582 z10583 = x10583 z10584 = x10584 z10585 = x10585 z10586 = x10586 z10587 = x10587 z10588 = x10588 z10589 = x10589 z10590 = x10590 z10591 = x10591 z10592 = x10592 z10593 = x10593 z10594 = x10594 z10595 = x10595 z10596 = x10596 z10597 = x10597 z10598 = x10598 z10599 = x10599 z10600 = x10600 z10601 = x10601 z10602 = x10602 z10603 = x10603 z10604 = x10604 z10605 = x10605 z10606 = x10606 z10607 = x10607 z10608 = x10608 z10609 = x10609 z10610 = x10610 z10611 = x10611 z10612 = x10612 z10613 = x10613 z10614 = x10614 z10615 = x10615 z10616 = x10616 z10617 = x10617 z10618 = x10618 z10619 = x10619 z10620 = x10620 z10621 = x10621 z10622 = x10622 z10623 = x10623 z10624 = x10624 z10625 = x10625 z10626 = x10626 z10627 = x10627 z10628 = x10628 z10629 = x10629 z10630 = x10630 z10631 = x10631 z10632 = x10632 z10633 = x10633 z10634 = x10634 z10635 = x10635 z10636 = x10636 z10637 = x10637 z10638 = x10638 z10639 = x10639 z10640 = x10640 z10641 = x10641 z10642 = x10642 z10643 = x10643 z10644 = x10644 z10645 = x10645 z10646 = x10646 z10647 = x10647 z10648 = x10648 z10649 = x10649 z10650 = x10650 z10651 = x10651 z10652 = x10652 z10653 = x10653 z10654 = x10654 z10655 = x10655 z10656 = x10656 z10657 = x10657 z10658 = x10658 z10659 = x10659 z10660 = x10660 z10661 = x10661 z10662 = x10662 z10663 = x10663 z10664 = x10664 z10665 = x10665 z10666 = x10666 z10667 = x10667 z10668 = x10668 z10669 = x10669 z10670 = x10670 z10671 = x10671 z10672 = x10672 z10673 = x10673 z10674 = x10674 z10675 = x10675 z10676 = x10676 z10677 = x10677 z10678 = x10678 z10679 = x10679 z10680 = x10680 z10681 = x10681 z10682 = x10682 z10683 = x10683 z10684 = x10684 z10685 = x10685 z10686 = x10686 z10687 = x10687 z10688 = x10688 z10689 = x10689 z10690 = x10690 z10691 = x10691 z10692 = x10692 z10693 = x10693 z10694 = x10694 z10695 = x10695 z10696 = x10696 z10697 = x10697 z10698 = x10698 z10699 = x10699 z10700 = x10700 z10701 = x10701 z10702 = x10702 z10703 = x10703 z10704 = x10704 z10705 = x10705 z10706 = x10706 z10707 = x10707 z10708 = x10708 z10709 = x10709 z10710 = x10710 z10711 = x10711 z10712 = x10712 z10713 = x10713 z10714 = x10714 z10715 = x10715 z10716 = x10716 z10717 = x10717 z10718 = x10718 z10719 = x10719 z10720 = x10720 z10721 = x10721 z10722 = x10722 z10723 = x10723 z10724 = x10724 z10725 = x10725 z10726 = x10726 z10727 = x10727 z10728 = x10728 z10729 = x10729 z10730 = x10730 z10731 = x10731 z10732 = x10732 z10733 = x10733 z10734 = x10734 z10735 = x10735 z10736 = x10736 z10737 = x10737 z10738 = x10738 z10739 = x10739 z10740 = x10740 z10741 = x10741 z10742 = x10742 z10743 = x10743 z10744 = x10744 z10745 = x10745 z10746 = x10746 z10747 = x10747 z10748 = x10748 z10749 = x10749 z10750 = x10750 z10751 = x10751 z10752 = x10752 z10753 = x10753 z10754 = x10754 z10755 = x10755 z10756 = x10756 z10757 = x10757 z10758 = x10758 z10759 = x10759 z10760 = x10760 z10761 = x10761 z10762 = x10762 z10763 = x10763 z10764 = x10764 z10765 = x10765 z10766 = x10766 z10767 = x10767 z10768 = x10768 z10769 = x10769 z10770 = x10770 z10771 = x10771 z10772 = x10772 z10773 = x10773 z10774 = x10774 z10775 = x10775 z10776 = x10776 z10777 = x10777 z10778 = x10778 z10779 = x10779 z10780 = x10780 z10781 = x10781 z10782 = x10782 z10783 = x10783 z10784 = x10784 z10785 = x10785 z10786 = x10786 z10787 = x10787 z10788 = x10788 z10789 = x10789 z10790 = x10790 z10791 = x10791 z10792 = x10792 z10793 = x10793 z10794 = x10794 z10795 = x10795 z10796 = x10796 z10797 = x10797 z10798 = x10798 z10799 = x10799 z10800 = x10800 z10801 = x10801 z10802 = x10802 z10803 = x10803 z10804 = x10804 z10805 = x10805 z10806 = x10806 z10807 = x10807 z10808 = x10808 z10809 = x10809 z10810 = x10810 z10811 = x10811 z10812 = x10812 z10813 = x10813 z10814 = x10814 z10815 = x10815 z10816 = x10816 z10817 = x10817 z10818 = x10818 z10819 = x10819 z10820 = x10820 z10821 = x10821 z10822 = x10822 z10823 = x10823 z10824 = x10824 z10825 = x10825 z10826 = x10826 z10827 = x10827 z10828 = x10828 z10829 = x10829 z10830 = x10830 z10831 = x10831 z10832 = x10832 z10833 = x10833 z10834 = x10834 z10835 = x10835 z10836 = x10836 z10837 = x10837 z10838 = x10838 z10839 = x10839 z10840 = x10840 z10841 = x10841 z10842 = x10842 z10843 = x10843 z10844 = x10844 z10845 = x10845 z10846 = x10846 z10847 = x10847 z10848 = x10848 z10849 = x10849 z10850 = x10850 z10851 = x10851 z10852 = x10852 z10853 = x10853 z10854 = x10854 z10855 = x10855 z10856 = x10856 z10857 = x10857 z10858 = x10858 z10859 = x10859 z10860 = x10860 z10861 = x10861 z10862 = x10862 z10863 = x10863 z10864 = x10864 z10865 = x10865 z10866 = x10866 z10867 = x10867 z10868 = x10868 z10869 = x10869 z10870 = x10870 z10871 = x10871 z10872 = x10872 z10873 = x10873 z10874 = x10874 z10875 = x10875 z10876 = x10876 z10877 = x10877 z10878 = x10878 z10879 = x10879 z10880 = x10880 z10881 = x10881 z10882 = x10882 z10883 = x10883 z10884 = x10884 z10885 = x10885 z10886 = x10886 z10887 = x10887 z10888 = x10888 z10889 = x10889 z10890 = x10890 z10891 = x10891 z10892 = x10892 z10893 = x10893 z10894 = x10894 z10895 = x10895 z10896 = x10896 z10897 = x10897 z10898 = x10898 z10899 = x10899 z10900 = x10900 z10901 = x10901 z10902 = x10902 z10903 = x10903 z10904 = x10904 z10905 = x10905 z10906 = x10906 z10907 = x10907 z10908 = x10908 z10909 = x10909 z10910 = x10910 z10911 = x10911 z10912 = x10912 z10913 = x10913 z10914 = x10914 z10915 = x10915 z10916 = x10916 z10917 = x10917 z10918 = x10918 z10919 = x10919 z10920 = x10920 z10921 = x10921 z10922 = x10922 z10923 = x10923 z10924 = x10924 z10925 = x10925 z10926 = x10926 z10927 = x10927 z10928 = x10928 z10929 = x10929 z10930 = x10930 z10931 = x10931 z10932 = x10932 z10933 = x10933 z10934 = x10934 z10935 = x10935 z10936 = x10936 z10937 = x10937 z10938 = x10938 z10939 = x10939 z10940 = x10940 z10941 = x10941 z10942 = x10942 z10943 = x10943 z10944 = x10944 z10945 = x10945 z10946 = x10946 z10947 = x10947 z10948 = x10948 z10949 = x10949 z10950 = x10950 z10951 = x10951 z10952 = x10952 z10953 = x10953 z10954 = x10954 z10955 = x10955 z10956 = x10956 z10957 = x10957 z10958 = x10958 z10959 = x10959 z10960 = x10960 z10961 = x10961 z10962 = x10962 z10963 = x10963 z10964 = x10964 z10965 = x10965 z10966 = x10966 z10967 = x10967 z10968 = x10968 z10969 = x10969 z10970 = x10970 z10971 = x10971 z10972 = x10972 z10973 = x10973 z10974 = x10974 z10975 = x10975 z10976 = x10976 z10977 = x10977 z10978 = x10978 z10979 = x10979 z10980 = x10980 z10981 = x10981 z10982 = x10982 z10983 = x10983 z10984 = x10984 z10985 = x10985 z10986 = x10986 z10987 = x10987 z10988 = x10988 z10989 = x10989 z10990 = x10990 z10991 = x10991 z10992 = x10992 z10993 = x10993 z10994 = x10994 z10995 = x10995 z10996 = x10996 z10997 = x10997 z10998 = x10998 z10999 = x10999 z11000 = x11000 z11001 = x11001 z11002 = x11002 z11003 = x11003 z11004 = x11004 z11005 = x11005 z11006 = x11006 z11007 = x11007 z11008 = x11008 z11009 = x11009 z11010 = x11010 z11011 = x11011 z11012 = x11012 z11013 = x11013 z11014 = x11014 z11015 = x11015 z11016 = x11016 z11017 = x11017 z11018 = x11018 z11019 = x11019 z11020 = x11020 z11021 = x11021 z11022 = x11022 z11023 = x11023 z11024 = x11024 z11025 = x11025 z11026 = x11026 z11027 = x11027 z11028 = x11028 z11029 = x11029 z11030 = x11030 z11031 = x11031 z11032 = x11032 z11033 = x11033 z11034 = x11034 z11035 = x11035 z11036 = x11036 z11037 = x11037 z11038 = x11038 z11039 = x11039 z11040 = x11040 z11041 = x11041 z11042 = x11042 z11043 = x11043 z11044 = x11044 z11045 = x11045 z11046 = x11046 z11047 = x11047 z11048 = x11048 z11049 = x11049 z11050 = x11050 z11051 = x11051 z11052 = x11052 z11053 = x11053 z11054 = x11054 z11055 = x11055 z11056 = x11056 z11057 = x11057 z11058 = x11058 z11059 = x11059 z11060 = x11060 z11061 = x11061 z11062 = x11062 z11063 = x11063 z11064 = x11064 z11065 = x11065 z11066 = x11066 z11067 = x11067 z11068 = x11068 z11069 = x11069 z11070 = x11070 z11071 = x11071 z11072 = x11072 z11073 = x11073 z11074 = x11074 z11075 = x11075 z11076 = x11076 z11077 = x11077 z11078 = x11078 z11079 = x11079 z11080 = x11080 z11081 = x11081 z11082 = x11082 z11083 = x11083 z11084 = x11084 z11085 = x11085 z11086 = x11086 z11087 = x11087 z11088 = x11088 z11089 = x11089 z11090 = x11090 z11091 = x11091 z11092 = x11092 z11093 = x11093 z11094 = x11094 z11095 = x11095 z11096 = x11096 z11097 = x11097 z11098 = x11098 z11099 = x11099 z11100 = x11100 z11101 = x11101 z11102 = x11102 z11103 = x11103 z11104 = x11104 z11105 = x11105 z11106 = x11106 z11107 = x11107 z11108 = x11108 z11109 = x11109 z11110 = x11110 z11111 = x11111 z11112 = x11112 z11113 = x11113 z11114 = x11114 z11115 = x11115 z11116 = x11116 z11117 = x11117 z11118 = x11118 z11119 = x11119 z11120 = x11120 z11121 = x11121 z11122 = x11122 z11123 = x11123 z11124 = x11124 z11125 = x11125 z11126 = x11126 z11127 = x11127 z11128 = x11128 z11129 = x11129 z11130 = x11130 z11131 = x11131 z11132 = x11132 z11133 = x11133 z11134 = x11134 z11135 = x11135 z11136 = x11136 z11137 = x11137 z11138 = x11138 z11139 = x11139 z11140 = x11140 z11141 = x11141 z11142 = x11142 z11143 = x11143 z11144 = x11144 z11145 = x11145 z11146 = x11146 z11147 = x11147 z11148 = x11148 z11149 = x11149 z11150 = x11150 z11151 = x11151 z11152 = x11152 z11153 = x11153 z11154 = x11154 z11155 = x11155 z11156 = x11156 z11157 = x11157 z11158 = x11158 z11159 = x11159 z11160 = x11160 z11161 = x11161 z11162 = x11162 z11163 = x11163 z11164 = x11164 z11165 = x11165 z11166 = x11166 z11167 = x11167 z11168 = x11168 z11169 = x11169 z11170 = x11170 z11171 = x11171 z11172 = x11172 z11173 = x11173 z11174 = x11174 z11175 = x11175 z11176 = x11176 z11177 = x11177 z11178 = x11178 z11179 = x11179 z11180 = x11180 z11181 = x11181 z11182 = x11182 z11183 = x11183 z11184 = x11184 z11185 = x11185 z11186 = x11186 z11187 = x11187 z11188 = x11188 z11189 = x11189 z11190 = x11190 z11191 = x11191 z11192 = x11192 z11193 = x11193 z11194 = x11194 z11195 = x11195 z11196 = x11196 z11197 = x11197 z11198 = x11198 z11199 = x11199 z11200 = x11200 z11201 = x11201 z11202 = x11202 z11203 = x11203 z11204 = x11204 z11205 = x11205 z11206 = x11206 z11207 = x11207 z11208 = x11208 z11209 = x11209 z11210 = x11210 z11211 = x11211 z11212 = x11212 z11213 = x11213 z11214 = x11214 z11215 = x11215 z11216 = x11216 z11217 = x11217 z11218 = x11218 z11219 = x11219 z11220 = x11220 z11221 = x11221 z11222 = x11222 z11223 = x11223 z11224 = x11224 z11225 = x11225 z11226 = x11226 z11227 = x11227 z11228 = x11228 z11229 = x11229 z11230 = x11230 z11231 = x11231 z11232 = x11232 z11233 = x11233 z11234 = x11234 z11235 = x11235 z11236 = x11236 z11237 = x11237 z11238 = x11238 z11239 = x11239 z11240 = x11240 z11241 = x11241 z11242 = x11242 z11243 = x11243 z11244 = x11244 z11245 = x11245 z11246 = x11246 z11247 = x11247 z11248 = x11248 z11249 = x11249 z11250 = x11250 z11251 = x11251 z11252 = x11252 z11253 = x11253 z11254 = x11254 z11255 = x11255 z11256 = x11256 z11257 = x11257 z11258 = x11258 z11259 = x11259 z11260 = x11260 z11261 = x11261 z11262 = x11262 z11263 = x11263 z11264 = x11264 z11265 = x11265 z11266 = x11266 z11267 = x11267 z11268 = x11268 z11269 = x11269 z11270 = x11270 z11271 = x11271 z11272 = x11272 z11273 = x11273 z11274 = x11274 z11275 = x11275 z11276 = x11276 z11277 = x11277 z11278 = x11278 z11279 = x11279 z11280 = x11280 z11281 = x11281 z11282 = x11282 z11283 = x11283 z11284 = x11284 z11285 = x11285 z11286 = x11286 z11287 = x11287 z11288 = x11288 z11289 = x11289 z11290 = x11290 z11291 = x11291 z11292 = x11292 z11293 = x11293 z11294 = x11294 z11295 = x11295 z11296 = x11296 z11297 = x11297 z11298 = x11298 z11299 = x11299 z11300 = x11300 z11301 = x11301 z11302 = x11302 z11303 = x11303 z11304 = x11304 z11305 = x11305 z11306 = x11306 z11307 = x11307 z11308 = x11308 z11309 = x11309 z11310 = x11310 z11311 = x11311 z11312 = x11312 z11313 = x11313 z11314 = x11314 z11315 = x11315 z11316 = x11316 z11317 = x11317 z11318 = x11318 z11319 = x11319 z11320 = x11320 z11321 = x11321 z11322 = x11322 z11323 = x11323 z11324 = x11324 z11325 = x11325 z11326 = x11326 z11327 = x11327 z11328 = x11328 z11329 = x11329 z11330 = x11330 z11331 = x11331 z11332 = x11332 z11333 = x11333 z11334 = x11334 z11335 = x11335 z11336 = x11336 z11337 = x11337 z11338 = x11338 z11339 = x11339 z11340 = x11340 z11341 = x11341 z11342 = x11342 z11343 = x11343 z11344 = x11344 z11345 = x11345 z11346 = x11346 z11347 = x11347 z11348 = x11348 z11349 = x11349 z11350 = x11350 z11351 = x11351 z11352 = x11352 z11353 = x11353 z11354 = x11354 z11355 = x11355 z11356 = x11356 z11357 = x11357 z11358 = x11358 z11359 = x11359 z11360 = x11360 z11361 = x11361 z11362 = x11362 z11363 = x11363 z11364 = x11364 z11365 = x11365 z11366 = x11366 z11367 = x11367 z11368 = x11368 z11369 = x11369 z11370 = x11370 z11371 = x11371 z11372 = x11372 z11373 = x11373 z11374 = x11374 z11375 = x11375 z11376 = x11376 z11377 = x11377 z11378 = x11378 z11379 = x11379 z11380 = x11380 z11381 = x11381 z11382 = x11382 z11383 = x11383 z11384 = x11384 z11385 = x11385 z11386 = x11386 z11387 = x11387 z11388 = x11388 z11389 = x11389 z11390 = x11390 z11391 = x11391 z11392 = x11392 z11393 = x11393 z11394 = x11394 z11395 = x11395 z11396 = x11396 z11397 = x11397 z11398 = x11398 z11399 = x11399 z11400 = x11400 z11401 = x11401 z11402 = x11402 z11403 = x11403 z11404 = x11404 z11405 = x11405 z11406 = x11406 z11407 = x11407 z11408 = x11408 z11409 = x11409 z11410 = x11410 z11411 = x11411 z11412 = x11412 z11413 = x11413 z11414 = x11414 z11415 = x11415 z11416 = x11416 z11417 = x11417 z11418 = x11418 z11419 = x11419 z11420 = x11420 z11421 = x11421 z11422 = x11422 z11423 = x11423 z11424 = x11424 z11425 = x11425 z11426 = x11426 z11427 = x11427 z11428 = x11428 z11429 = x11429 z11430 = x11430 z11431 = x11431 z11432 = x11432 z11433 = x11433 z11434 = x11434 z11435 = x11435 z11436 = x11436 z11437 = x11437 z11438 = x11438 z11439 = x11439 z11440 = x11440 z11441 = x11441 z11442 = x11442 z11443 = x11443 z11444 = x11444 z11445 = x11445 z11446 = x11446 z11447 = x11447 z11448 = x11448 z11449 = x11449 z11450 = x11450 z11451 = x11451 z11452 = x11452 z11453 = x11453 z11454 = x11454 z11455 = x11455 z11456 = x11456 z11457 = x11457 z11458 = x11458 z11459 = x11459 z11460 = x11460 z11461 = x11461 z11462 = x11462 z11463 = x11463 z11464 = x11464 z11465 = x11465 z11466 = x11466 z11467 = x11467 z11468 = x11468 z11469 = x11469 z11470 = x11470 z11471 = x11471 z11472 = x11472 z11473 = x11473 z11474 = x11474 z11475 = x11475 z11476 = x11476 z11477 = x11477 z11478 = x11478 z11479 = x11479 z11480 = x11480 z11481 = x11481 z11482 = x11482 z11483 = x11483 z11484 = x11484 z11485 = x11485 z11486 = x11486 z11487 = x11487 z11488 = x11488 z11489 = x11489 z11490 = x11490 z11491 = x11491 z11492 = x11492 z11493 = x11493 z11494 = x11494 z11495 = x11495 z11496 = x11496 z11497 = x11497 z11498 = x11498 z11499 = x11499 z11500 = x11500 z11501 = x11501 z11502 = x11502 z11503 = x11503 z11504 = x11504 z11505 = x11505 z11506 = x11506 z11507 = x11507 z11508 = x11508 z11509 = x11509 z11510 = x11510 z11511 = x11511 z11512 = x11512 z11513 = x11513 z11514 = x11514 z11515 = x11515 z11516 = x11516 z11517 = x11517 z11518 = x11518 z11519 = x11519 z11520 = x11520 z11521 = x11521 z11522 = x11522 z11523 = x11523 z11524 = x11524 z11525 = x11525 z11526 = x11526 z11527 = x11527 z11528 = x11528 z11529 = x11529 z11530 = x11530 z11531 = x11531 z11532 = x11532 z11533 = x11533 z11534 = x11534 z11535 = x11535 z11536 = x11536 z11537 = x11537 z11538 = x11538 z11539 = x11539 z11540 = x11540 z11541 = x11541 z11542 = x11542 z11543 = x11543 z11544 = x11544 z11545 = x11545 z11546 = x11546 z11547 = x11547 z11548 = x11548 z11549 = x11549 z11550 = x11550 z11551 = x11551 z11552 = x11552 z11553 = x11553 z11554 = x11554 z11555 = x11555 z11556 = x11556 z11557 = x11557 z11558 = x11558 z11559 = x11559 z11560 = x11560 z11561 = x11561 z11562 = x11562 z11563 = x11563 z11564 = x11564 z11565 = x11565 z11566 = x11566 z11567 = x11567 z11568 = x11568 z11569 = x11569 z11570 = x11570 z11571 = x11571 z11572 = x11572 z11573 = x11573 z11574 = x11574 z11575 = x11575 z11576 = x11576 z11577 = x11577 z11578 = x11578 z11579 = x11579 z11580 = x11580 z11581 = x11581 z11582 = x11582 z11583 = x11583 z11584 = x11584 z11585 = x11585 z11586 = x11586 z11587 = x11587 z11588 = x11588 z11589 = x11589 z11590 = x11590 z11591 = x11591 z11592 = x11592 z11593 = x11593 z11594 = x11594 z11595 = x11595 z11596 = x11596 z11597 = x11597 z11598 = x11598 z11599 = x11599 z11600 = x11600 z11601 = x11601 z11602 = x11602 z11603 = x11603 z11604 = x11604 z11605 = x11605 z11606 = x11606 z11607 = x11607 z11608 = x11608 z11609 = x11609 z11610 = x11610 z11611 = x11611 z11612 = x11612 z11613 = x11613 z11614 = x11614 z11615 = x11615 z11616 = x11616 z11617 = x11617 z11618 = x11618 z11619 = x11619 z11620 = x11620 z11621 = x11621 z11622 = x11622 z11623 = x11623 z11624 = x11624 z11625 = x11625 z11626 = x11626 z11627 = x11627 z11628 = x11628 z11629 = x11629 z11630 = x11630 z11631 = x11631 z11632 = x11632 z11633 = x11633 z11634 = x11634 z11635 = x11635 z11636 = x11636 z11637 = x11637 z11638 = x11638 z11639 = x11639 z11640 = x11640 z11641 = x11641 z11642 = x11642 z11643 = x11643 z11644 = x11644 z11645 = x11645 z11646 = x11646 z11647 = x11647 z11648 = x11648 z11649 = x11649 z11650 = x11650 z11651 = x11651 z11652 = x11652 z11653 = x11653 z11654 = x11654 z11655 = x11655 z11656 = x11656 z11657 = x11657 z11658 = x11658 z11659 = x11659 z11660 = x11660 z11661 = x11661 z11662 = x11662 z11663 = x11663 z11664 = x11664 z11665 = x11665 z11666 = x11666 z11667 = x11667 z11668 = x11668 z11669 = x11669 z11670 = x11670 z11671 = x11671 z11672 = x11672 z11673 = x11673 z11674 = x11674 z11675 = x11675 z11676 = x11676 z11677 = x11677 z11678 = x11678 z11679 = x11679 z11680 = x11680 z11681 = x11681 z11682 = x11682 z11683 = x11683 z11684 = x11684 z11685 = x11685 z11686 = x11686 z11687 = x11687 z11688 = x11688 z11689 = x11689 z11690 = x11690 z11691 = x11691 z11692 = x11692 z11693 = x11693 z11694 = x11694 z11695 = x11695 z11696 = x11696 z11697 = x11697 z11698 = x11698 z11699 = x11699 z11700 = x11700 z11701 = x11701 z11702 = x11702 z11703 = x11703 z11704 = x11704 z11705 = x11705 z11706 = x11706 z11707 = x11707 z11708 = x11708 z11709 = x11709 z11710 = x11710 z11711 = x11711 z11712 = x11712 z11713 = x11713 z11714 = x11714 z11715 = x11715 z11716 = x11716 z11717 = x11717 z11718 = x11718 z11719 = x11719 z11720 = x11720 z11721 = x11721 z11722 = x11722 z11723 = x11723 z11724 = x11724 z11725 = x11725 z11726 = x11726 z11727 = x11727 z11728 = x11728 z11729 = x11729 z11730 = x11730 z11731 = x11731 z11732 = x11732 z11733 = x11733 z11734 = x11734 z11735 = x11735 z11736 = x11736 z11737 = x11737 z11738 = x11738 z11739 = x11739 z11740 = x11740 z11741 = x11741 z11742 = x11742 z11743 = x11743 z11744 = x11744 z11745 = x11745 z11746 = x11746 z11747 = x11747 z11748 = x11748 z11749 = x11749 z11750 = x11750 z11751 = x11751 z11752 = x11752 z11753 = x11753 z11754 = x11754 z11755 = x11755 z11756 = x11756 z11757 = x11757 z11758 = x11758 z11759 = x11759 z11760 = x11760 z11761 = x11761 z11762 = x11762 z11763 = x11763 z11764 = x11764 z11765 = x11765 z11766 = x11766 z11767 = x11767 z11768 = x11768 z11769 = x11769 z11770 = x11770 z11771 = x11771 z11772 = x11772 z11773 = x11773 z11774 = x11774 z11775 = x11775 z11776 = x11776 z11777 = x11777 z11778 = x11778 z11779 = x11779 z11780 = x11780 z11781 = x11781 z11782 = x11782 z11783 = x11783 z11784 = x11784 z11785 = x11785 z11786 = x11786 z11787 = x11787 z11788 = x11788 z11789 = x11789 z11790 = x11790 z11791 = x11791 z11792 = x11792 z11793 = x11793 z11794 = x11794 z11795 = x11795 z11796 = x11796 z11797 = x11797 z11798 = x11798 z11799 = x11799 z11800 = x11800 z11801 = x11801 z11802 = x11802 z11803 = x11803 z11804 = x11804 z11805 = x11805 z11806 = x11806 z11807 = x11807 z11808 = x11808 z11809 = x11809 z11810 = x11810 z11811 = x11811 z11812 = x11812 z11813 = x11813 z11814 = x11814 z11815 = x11815 z11816 = x11816 z11817 = x11817 z11818 = x11818 z11819 = x11819 z11820 = x11820 z11821 = x11821 z11822 = x11822 z11823 = x11823 z11824 = x11824 z11825 = x11825 z11826 = x11826 z11827 = x11827 z11828 = x11828 z11829 = x11829 z11830 = x11830 z11831 = x11831 z11832 = x11832 z11833 = x11833 z11834 = x11834 z11835 = x11835 z11836 = x11836 z11837 = x11837 z11838 = x11838 z11839 = x11839 z11840 = x11840 z11841 = x11841 z11842 = x11842 z11843 = x11843 z11844 = x11844 z11845 = x11845 z11846 = x11846 z11847 = x11847 z11848 = x11848 z11849 = x11849 z11850 = x11850 z11851 = x11851 z11852 = x11852 z11853 = x11853 z11854 = x11854 z11855 = x11855 z11856 = x11856 z11857 = x11857 z11858 = x11858 z11859 = x11859 z11860 = x11860 z11861 = x11861 z11862 = x11862 z11863 = x11863 z11864 = x11864 z11865 = x11865 z11866 = x11866 z11867 = x11867 z11868 = x11868 z11869 = x11869 z11870 = x11870 z11871 = x11871 z11872 = x11872 z11873 = x11873 z11874 = x11874 z11875 = x11875 z11876 = x11876 z11877 = x11877 z11878 = x11878 z11879 = x11879 z11880 = x11880 z11881 = x11881 z11882 = x11882 z11883 = x11883 z11884 = x11884 z11885 = x11885 z11886 = x11886 z11887 = x11887 z11888 = x11888 z11889 = x11889 z11890 = x11890 z11891 = x11891 z11892 = x11892 z11893 = x11893 z11894 = x11894 z11895 = x11895 z11896 = x11896 z11897 = x11897 z11898 = x11898 z11899 = x11899 z11900 = x11900 z11901 = x11901 z11902 = x11902 z11903 = x11903 z11904 = x11904 z11905 = x11905 z11906 = x11906 z11907 = x11907 z11908 = x11908 z11909 = x11909 z11910 = x11910 z11911 = x11911 z11912 = x11912 z11913 = x11913 z11914 = x11914 z11915 = x11915 z11916 = x11916 z11917 = x11917 z11918 = x11918 z11919 = x11919 z11920 = x11920 z11921 = x11921 z11922 = x11922 z11923 = x11923 z11924 = x11924 z11925 = x11925 z11926 = x11926 z11927 = x11927 z11928 = x11928 z11929 = x11929 z11930 = x11930 z11931 = x11931 z11932 = x11932 z11933 = x11933 z11934 = x11934 z11935 = x11935 z11936 = x11936 z11937 = x11937 z11938 = x11938 z11939 = x11939 z11940 = x11940 z11941 = x11941 z11942 = x11942 z11943 = x11943 z11944 = x11944 z11945 = x11945 z11946 = x11946 z11947 = x11947 z11948 = x11948 z11949 = x11949 z11950 = x11950 z11951 = x11951 z11952 = x11952 z11953 = x11953 z11954 = x11954 z11955 = x11955 z11956 = x11956 z11957 = x11957 z11958 = x11958 z11959 = x11959 z11960 = x11960 z11961 = x11961 z11962 = x11962 z11963 = x11963 z11964 = x11964 z11965 = x11965 z11966 = x11966 z11967 = x11967 z11968 = x11968 z11969 = x11969 z11970 = x11970 z11971 = x11971 z11972 = x11972 z11973 = x11973 z11974 = x11974 z11975 = x11975 z11976 = x11976 z11977 = x11977 z11978 = x11978 z11979 = x11979 z11980 = x11980 z11981 = x11981 z11982 = x11982 z11983 = x11983 z11984 = x11984 z11985 = x11985 z11986 = x11986 z11987 = x11987 z11988 = x11988 z11989 = x11989 z11990 = x11990 z11991 = x11991 z11992 = x11992 z11993 = x11993 z11994 = x11994 z11995 = x11995 z11996 = x11996 z11997 = x11997 z11998 = x11998 z11999 = x11999 z12000 = x12000 z12001 = x12001 z12002 = x12002 z12003 = x12003 z12004 = x12004 z12005 = x12005 z12006 = x12006 z12007 = x12007 z12008 = x12008 z12009 = x12009 z12010 = x12010 z12011 = x12011 z12012 = x12012 z12013 = x12013 z12014 = x12014 z12015 = x12015 z12016 = x12016 z12017 = x12017 z12018 = x12018 z12019 = x12019 z12020 = x12020 z12021 = x12021 z12022 = x12022 z12023 = x12023 z12024 = x12024 z12025 = x12025 z12026 = x12026 z12027 = x12027 z12028 = x12028 z12029 = x12029 z12030 = x12030 z12031 = x12031 z12032 = x12032 z12033 = x12033 z12034 = x12034 z12035 = x12035 z12036 = x12036 z12037 = x12037 z12038 = x12038 z12039 = x12039 z12040 = x12040 z12041 = x12041 z12042 = x12042 z12043 = x12043 z12044 = x12044 z12045 = x12045 z12046 = x12046 z12047 = x12047 z12048 = x12048 z12049 = x12049 z12050 = x12050 z12051 = x12051 z12052 = x12052 z12053 = x12053 z12054 = x12054 z12055 = x12055 z12056 = x12056 z12057 = x12057 z12058 = x12058 z12059 = x12059 z12060 = x12060 z12061 = x12061 z12062 = x12062 z12063 = x12063 z12064 = x12064 z12065 = x12065 z12066 = x12066 z12067 = x12067 z12068 = x12068 z12069 = x12069 z12070 = x12070 z12071 = x12071 z12072 = x12072 z12073 = x12073 z12074 = x12074 z12075 = x12075 z12076 = x12076 z12077 = x12077 z12078 = x12078 z12079 = x12079 z12080 = x12080 z12081 = x12081 z12082 = x12082 z12083 = x12083 z12084 = x12084 z12085 = x12085 z12086 = x12086 z12087 = x12087 z12088 = x12088 z12089 = x12089 z12090 = x12090 z12091 = x12091 z12092 = x12092 z12093 = x12093 z12094 = x12094 z12095 = x12095 z12096 = x12096 z12097 = x12097 z12098 = x12098 z12099 = x12099 z12100 = x12100 z12101 = x12101 z12102 = x12102 z12103 = x12103 z12104 = x12104 z12105 = x12105 z12106 = x12106 z12107 = x12107 z12108 = x12108 z12109 = x12109 z12110 = x12110 z12111 = x12111 z12112 = x12112 z12113 = x12113 z12114 = x12114 z12115 = x12115 z12116 = x12116 z12117 = x12117 z12118 = x12118 z12119 = x12119 z12120 = x12120 z12121 = x12121 z12122 = x12122 z12123 = x12123 z12124 = x12124 z12125 = x12125 z12126 = x12126 z12127 = x12127 z12128 = x12128 z12129 = x12129 z12130 = x12130 z12131 = x12131 z12132 = x12132 z12133 = x12133 z12134 = x12134 z12135 = x12135 z12136 = x12136 z12137 = x12137 z12138 = x12138 z12139 = x12139 z12140 = x12140 z12141 = x12141 z12142 = x12142 z12143 = x12143 z12144 = x12144 z12145 = x12145 z12146 = x12146 z12147 = x12147 z12148 = x12148 z12149 = x12149 z12150 = x12150 z12151 = x12151 z12152 = x12152 z12153 = x12153 z12154 = x12154 z12155 = x12155 z12156 = x12156 z12157 = x12157 z12158 = x12158 z12159 = x12159 z12160 = x12160 z12161 = x12161 z12162 = x12162 z12163 = x12163 z12164 = x12164 z12165 = x12165 z12166 = x12166 z12167 = x12167 z12168 = x12168 z12169 = x12169 z12170 = x12170 z12171 = x12171 z12172 = x12172 z12173 = x12173 z12174 = x12174 z12175 = x12175 z12176 = x12176 z12177 = x12177 z12178 = x12178 z12179 = x12179 z12180 = x12180 z12181 = x12181 z12182 = x12182 z12183 = x12183 z12184 = x12184 z12185 = x12185 z12186 = x12186 z12187 = x12187 z12188 = x12188 z12189 = x12189 z12190 = x12190 z12191 = x12191 z12192 = x12192 z12193 = x12193 z12194 = x12194 z12195 = x12195 z12196 = x12196 z12197 = x12197 z12198 = x12198 z12199 = x12199 z12200 = x12200 z12201 = x12201 z12202 = x12202 z12203 = x12203 z12204 = x12204 z12205 = x12205 z12206 = x12206 z12207 = x12207 z12208 = x12208 z12209 = x12209 z12210 = x12210 z12211 = x12211 z12212 = x12212 z12213 = x12213 z12214 = x12214 z12215 = x12215 z12216 = x12216 z12217 = x12217 z12218 = x12218 z12219 = x12219 z12220 = x12220 z12221 = x12221 z12222 = x12222 z12223 = x12223 z12224 = x12224 z12225 = x12225 z12226 = x12226 z12227 = x12227 z12228 = x12228 z12229 = x12229 z12230 = x12230 z12231 = x12231 z12232 = x12232 z12233 = x12233 z12234 = x12234 z12235 = x12235 z12236 = x12236 z12237 = x12237 z12238 = x12238 z12239 = x12239 z12240 = x12240 z12241 = x12241 z12242 = x12242 z12243 = x12243 z12244 = x12244 z12245 = x12245 z12246 = x12246 z12247 = x12247 z12248 = x12248 z12249 = x12249 z12250 = x12250 z12251 = x12251 z12252 = x12252 z12253 = x12253 z12254 = x12254 z12255 = x12255 z12256 = x12256 z12257 = x12257 z12258 = x12258 z12259 = x12259 z12260 = x12260 z12261 = x12261 z12262 = x12262 z12263 = x12263 z12264 = x12264 z12265 = x12265 z12266 = x12266 z12267 = x12267 z12268 = x12268 z12269 = x12269 z12270 = x12270 z12271 = x12271 z12272 = x12272 z12273 = x12273 z12274 = x12274 z12275 = x12275 z12276 = x12276 z12277 = x12277 z12278 = x12278 z12279 = x12279 z12280 = x12280 z12281 = x12281 z12282 = x12282 z12283 = x12283 z12284 = x12284 z12285 = x12285 z12286 = x12286 z12287 = x12287 z12288 = x12288 z12289 = x12289 z12290 = x12290 z12291 = x12291 z12292 = x12292 z12293 = x12293 z12294 = x12294 z12295 = x12295 z12296 = x12296 z12297 = x12297 z12298 = x12298 z12299 = x12299 z12300 = x12300 z12301 = x12301 z12302 = x12302 z12303 = x12303 z12304 = x12304 z12305 = x12305 z12306 = x12306 z12307 = x12307 z12308 = x12308 z12309 = x12309 z12310 = x12310 z12311 = x12311 z12312 = x12312 z12313 = x12313 z12314 = x12314 z12315 = x12315 z12316 = x12316 z12317 = x12317 z12318 = x12318 z12319 = x12319 z12320 = x12320 z12321 = x12321 z12322 = x12322 z12323 = x12323 z12324 = x12324 z12325 = x12325 z12326 = x12326 z12327 = x12327 z12328 = x12328 z12329 = x12329 z12330 = x12330 z12331 = x12331 z12332 = x12332 z12333 = x12333 z12334 = x12334 z12335 = x12335 z12336 = x12336 z12337 = x12337 z12338 = x12338 z12339 = x12339 z12340 = x12340 z12341 = x12341 z12342 = x12342 z12343 = x12343 z12344 = x12344 z12345 = x12345 z12346 = x12346 z12347 = x12347 z12348 = x12348 z12349 = x12349 z12350 = x12350 z12351 = x12351 z12352 = x12352 z12353 = x12353 z12354 = x12354 z12355 = x12355 z12356 = x12356 z12357 = x12357 z12358 = x12358 z12359 = x12359 z12360 = x12360 z12361 = x12361 z12362 = x12362 z12363 = x12363 z12364 = x12364 z12365 = x12365 z12366 = x12366 z12367 = x12367 z12368 = x12368 z12369 = x12369 z12370 = x12370 z12371 = x12371 z12372 = x12372 z12373 = x12373 z12374 = x12374 z12375 = x12375 z12376 = x12376 z12377 = x12377 z12378 = x12378 z12379 = x12379 z12380 = x12380 z12381 = x12381 z12382 = x12382 z12383 = x12383 z12384 = x12384 z12385 = x12385 z12386 = x12386 z12387 = x12387 z12388 = x12388 z12389 = x12389 z12390 = x12390 z12391 = x12391 z12392 = x12392 z12393 = x12393 z12394 = x12394 z12395 = x12395 z12396 = x12396 z12397 = x12397 z12398 = x12398 z12399 = x12399 z12400 = x12400 z12401 = x12401 z12402 = x12402 z12403 = x12403 z12404 = x12404 z12405 = x12405 z12406 = x12406 z12407 = x12407 z12408 = x12408 z12409 = x12409 z12410 = x12410 z12411 = x12411 z12412 = x12412 z12413 = x12413 z12414 = x12414 z12415 = x12415 z12416 = x12416 z12417 = x12417 z12418 = x12418 z12419 = x12419 z12420 = x12420 z12421 = x12421 z12422 = x12422 z12423 = x12423 z12424 = x12424 z12425 = x12425 z12426 = x12426 z12427 = x12427 z12428 = x12428 z12429 = x12429 z12430 = x12430 z12431 = x12431 z12432 = x12432 z12433 = x12433 z12434 = x12434 z12435 = x12435 z12436 = x12436 z12437 = x12437 z12438 = x12438 z12439 = x12439 z12440 = x12440 z12441 = x12441 z12442 = x12442 z12443 = x12443 z12444 = x12444 z12445 = x12445 z12446 = x12446 z12447 = x12447 z12448 = x12448 z12449 = x12449 z12450 = x12450 z12451 = x12451 z12452 = x12452 z12453 = x12453 z12454 = x12454 z12455 = x12455 z12456 = x12456 z12457 = x12457 z12458 = x12458 z12459 = x12459 z12460 = x12460 z12461 = x12461 z12462 = x12462 z12463 = x12463 z12464 = x12464 z12465 = x12465 z12466 = x12466 z12467 = x12467 z12468 = x12468 z12469 = x12469 z12470 = x12470 z12471 = x12471 z12472 = x12472 z12473 = x12473 z12474 = x12474 z12475 = x12475 z12476 = x12476 z12477 = x12477 z12478 = x12478 z12479 = x12479 z12480 = x12480 z12481 = x12481 z12482 = x12482 z12483 = x12483 z12484 = x12484 z12485 = x12485 z12486 = x12486 z12487 = x12487 z12488 = x12488 z12489 = x12489 z12490 = x12490 z12491 = x12491 z12492 = x12492 z12493 = x12493 z12494 = x12494 z12495 = x12495 z12496 = x12496 z12497 = x12497 z12498 = x12498 z12499 = x12499 z12500 = x12500 z12501 = x12501 z12502 = x12502 z12503 = x12503 z12504 = x12504 z12505 = x12505 z12506 = x12506 z12507 = x12507 z12508 = x12508 z12509 = x12509 z12510 = x12510 z12511 = x12511 z12512 = x12512 z12513 = x12513 z12514 = x12514 z12515 = x12515 z12516 = x12516 z12517 = x12517 z12518 = x12518 z12519 = x12519 z12520 = x12520 z12521 = x12521 z12522 = x12522 z12523 = x12523 z12524 = x12524 z12525 = x12525 z12526 = x12526 z12527 = x12527 z12528 = x12528 z12529 = x12529 z12530 = x12530 z12531 = x12531 z12532 = x12532 z12533 = x12533 z12534 = x12534 z12535 = x12535 z12536 = x12536 z12537 = x12537 z12538 = x12538 z12539 = x12539 z12540 = x12540 z12541 = x12541 z12542 = x12542 z12543 = x12543 z12544 = x12544 z12545 = x12545 z12546 = x12546 z12547 = x12547 z12548 = x12548 z12549 = x12549 z12550 = x12550 z12551 = x12551 z12552 = x12552 z12553 = x12553 z12554 = x12554 z12555 = x12555 z12556 = x12556 z12557 = x12557 z12558 = x12558 z12559 = x12559 z12560 = x12560 z12561 = x12561 z12562 = x12562 z12563 = x12563 z12564 = x12564 z12565 = x12565 z12566 = x12566 z12567 = x12567 z12568 = x12568 z12569 = x12569 z12570 = x12570 z12571 = x12571 z12572 = x12572 z12573 = x12573 z12574 = x12574 z12575 = x12575 z12576 = x12576 z12577 = x12577 z12578 = x12578 z12579 = x12579 z12580 = x12580 z12581 = x12581 z12582 = x12582 z12583 = x12583 z12584 = x12584 z12585 = x12585 z12586 = x12586 z12587 = x12587 z12588 = x12588 z12589 = x12589 z12590 = x12590 z12591 = x12591 z12592 = x12592 z12593 = x12593 z12594 = x12594 z12595 = x12595 z12596 = x12596 z12597 = x12597 z12598 = x12598 z12599 = x12599 z12600 = x12600 z12601 = x12601 z12602 = x12602 z12603 = x12603 z12604 = x12604 z12605 = x12605 z12606 = x12606 z12607 = x12607 z12608 = x12608 z12609 = x12609 z12610 = x12610 z12611 = x12611 z12612 = x12612 z12613 = x12613 z12614 = x12614 z12615 = x12615 z12616 = x12616 z12617 = x12617 z12618 = x12618 z12619 = x12619 z12620 = x12620 z12621 = x12621 z12622 = x12622 z12623 = x12623 z12624 = x12624 z12625 = x12625 z12626 = x12626 z12627 = x12627 z12628 = x12628 z12629 = x12629 z12630 = x12630 z12631 = x12631 z12632 = x12632 z12633 = x12633 z12634 = x12634 z12635 = x12635 z12636 = x12636 z12637 = x12637 z12638 = x12638 z12639 = x12639 z12640 = x12640 z12641 = x12641 z12642 = x12642 z12643 = x12643 z12644 = x12644 z12645 = x12645 z12646 = x12646 z12647 = x12647 z12648 = x12648 z12649 = x12649 z12650 = x12650 z12651 = x12651 z12652 = x12652 z12653 = x12653 z12654 = x12654 z12655 = x12655 z12656 = x12656 z12657 = x12657 z12658 = x12658 z12659 = x12659 z12660 = x12660 z12661 = x12661 z12662 = x12662 z12663 = x12663 z12664 = x12664 z12665 = x12665 z12666 = x12666 z12667 = x12667 z12668 = x12668 z12669 = x12669 z12670 = x12670 z12671 = x12671 z12672 = x12672 z12673 = x12673 z12674 = x12674 z12675 = x12675 z12676 = x12676 z12677 = x12677 z12678 = x12678 z12679 = x12679 z12680 = x12680 z12681 = x12681 z12682 = x12682 z12683 = x12683 z12684 = x12684 z12685 = x12685 z12686 = x12686 z12687 = x12687 z12688 = x12688 z12689 = x12689 z12690 = x12690 z12691 = x12691 z12692 = x12692 z12693 = x12693 z12694 = x12694 z12695 = x12695 z12696 = x12696 z12697 = x12697 z12698 = x12698 z12699 = x12699 z12700 = x12700 z12701 = x12701 z12702 = x12702 z12703 = x12703 z12704 = x12704 z12705 = x12705 z12706 = x12706 z12707 = x12707 z12708 = x12708 z12709 = x12709 z12710 = x12710 z12711 = x12711 z12712 = x12712 z12713 = x12713 z12714 = x12714 z12715 = x12715 z12716 = x12716 z12717 = x12717 z12718 = x12718 z12719 = x12719 z12720 = x12720 z12721 = x12721 z12722 = x12722 z12723 = x12723 z12724 = x12724 z12725 = x12725 z12726 = x12726 z12727 = x12727 z12728 = x12728 z12729 = x12729 z12730 = x12730 z12731 = x12731 z12732 = x12732 z12733 = x12733 z12734 = x12734 z12735 = x12735 z12736 = x12736 z12737 = x12737 z12738 = x12738 z12739 = x12739 z12740 = x12740 z12741 = x12741 z12742 = x12742 z12743 = x12743 z12744 = x12744 z12745 = x12745 z12746 = x12746 z12747 = x12747 z12748 = x12748 z12749 = x12749 z12750 = x12750 z12751 = x12751 z12752 = x12752 z12753 = x12753 z12754 = x12754 z12755 = x12755 z12756 = x12756 z12757 = x12757 z12758 = x12758 z12759 = x12759 z12760 = x12760 z12761 = x12761 z12762 = x12762 z12763 = x12763 z12764 = x12764 z12765 = x12765 z12766 = x12766 z12767 = x12767 z12768 = x12768 z12769 = x12769 z12770 = x12770 z12771 = x12771 z12772 = x12772 z12773 = x12773 z12774 = x12774 z12775 = x12775 z12776 = x12776 z12777 = x12777 z12778 = x12778 z12779 = x12779 z12780 = x12780 z12781 = x12781 z12782 = x12782 z12783 = x12783 z12784 = x12784 z12785 = x12785 z12786 = x12786 z12787 = x12787 z12788 = x12788 z12789 = x12789 z12790 = x12790 z12791 = x12791 z12792 = x12792 z12793 = x12793 z12794 = x12794 z12795 = x12795 z12796 = x12796 z12797 = x12797 z12798 = x12798 z12799 = x12799 z12800 = x12800 z12801 = x12801 z12802 = x12802 z12803 = x12803 z12804 = x12804 z12805 = x12805 z12806 = x12806 z12807 = x12807 z12808 = x12808 z12809 = x12809 z12810 = x12810 z12811 = x12811 z12812 = x12812 z12813 = x12813 z12814 = x12814 z12815 = x12815 z12816 = x12816 z12817 = x12817 z12818 = x12818 z12819 = x12819 z12820 = x12820 z12821 = x12821 z12822 = x12822 z12823 = x12823 z12824 = x12824 z12825 = x12825 z12826 = x12826 z12827 = x12827 z12828 = x12828 z12829 = x12829 z12830 = x12830 z12831 = x12831 z12832 = x12832 z12833 = x12833 z12834 = x12834 z12835 = x12835 z12836 = x12836 z12837 = x12837 z12838 = x12838 z12839 = x12839 z12840 = x12840 z12841 = x12841 z12842 = x12842 z12843 = x12843 z12844 = x12844 z12845 = x12845 z12846 = x12846 z12847 = x12847 z12848 = x12848 z12849 = x12849 z12850 = x12850 z12851 = x12851 z12852 = x12852 z12853 = x12853 z12854 = x12854 z12855 = x12855 z12856 = x12856 z12857 = x12857 z12858 = x12858 z12859 = x12859 z12860 = x12860 z12861 = x12861 z12862 = x12862 z12863 = x12863 z12864 = x12864 z12865 = x12865 z12866 = x12866 z12867 = x12867 z12868 = x12868 z12869 = x12869 z12870 = x12870 z12871 = x12871 z12872 = x12872 z12873 = x12873 z12874 = x12874 z12875 = x12875 z12876 = x12876 z12877 = x12877 z12878 = x12878 z12879 = x12879 z12880 = x12880 z12881 = x12881 z12882 = x12882 z12883 = x12883 z12884 = x12884 z12885 = x12885 z12886 = x12886 z12887 = x12887 z12888 = x12888 z12889 = x12889 z12890 = x12890 z12891 = x12891 z12892 = x12892 z12893 = x12893 z12894 = x12894 z12895 = x12895 z12896 = x12896 z12897 = x12897 z12898 = x12898 z12899 = x12899 z12900 = x12900 z12901 = x12901 z12902 = x12902 z12903 = x12903 z12904 = x12904 z12905 = x12905 z12906 = x12906 z12907 = x12907 z12908 = x12908 z12909 = x12909 z12910 = x12910 z12911 = x12911 z12912 = x12912 z12913 = x12913 z12914 = x12914 z12915 = x12915 z12916 = x12916 z12917 = x12917 z12918 = x12918 z12919 = x12919 z12920 = x12920 z12921 = x12921 z12922 = x12922 z12923 = x12923 z12924 = x12924 z12925 = x12925 z12926 = x12926 z12927 = x12927 z12928 = x12928 z12929 = x12929 z12930 = x12930 z12931 = x12931 z12932 = x12932 z12933 = x12933 z12934 = x12934 z12935 = x12935 z12936 = x12936 z12937 = x12937 z12938 = x12938 z12939 = x12939 z12940 = x12940 z12941 = x12941 z12942 = x12942 z12943 = x12943 z12944 = x12944 z12945 = x12945 z12946 = x12946 z12947 = x12947 z12948 = x12948 z12949 = x12949 z12950 = x12950 z12951 = x12951 z12952 = x12952 z12953 = x12953 z12954 = x12954 z12955 = x12955 z12956 = x12956 z12957 = x12957 z12958 = x12958 z12959 = x12959 z12960 = x12960 z12961 = x12961 z12962 = x12962 z12963 = x12963 z12964 = x12964 z12965 = x12965 z12966 = x12966 z12967 = x12967 z12968 = x12968 z12969 = x12969 z12970 = x12970 z12971 = x12971 z12972 = x12972 z12973 = x12973 z12974 = x12974 z12975 = x12975 z12976 = x12976 z12977 = x12977 z12978 = x12978 z12979 = x12979 z12980 = x12980 z12981 = x12981 z12982 = x12982 z12983 = x12983 z12984 = x12984 z12985 = x12985 z12986 = x12986 z12987 = x12987 z12988 = x12988 z12989 = x12989 z12990 = x12990 z12991 = x12991 z12992 = x12992 z12993 = x12993 z12994 = x12994 z12995 = x12995 z12996 = x12996 z12997 = x12997 z12998 = x12998 z12999 = x12999 z13000 = x13000 z13001 = x13001 z13002 = x13002 z13003 = x13003 z13004 = x13004 z13005 = x13005 z13006 = x13006 z13007 = x13007 z13008 = x13008 z13009 = x13009 z13010 = x13010 z13011 = x13011 z13012 = x13012 z13013 = x13013 z13014 = x13014 z13015 = x13015 z13016 = x13016 z13017 = x13017 z13018 = x13018 z13019 = x13019 z13020 = x13020 z13021 = x13021 z13022 = x13022 z13023 = x13023 z13024 = x13024 z13025 = x13025 z13026 = x13026 z13027 = x13027 z13028 = x13028 z13029 = x13029 z13030 = x13030 z13031 = x13031 z13032 = x13032 z13033 = x13033 z13034 = x13034 z13035 = x13035 z13036 = x13036 z13037 = x13037 z13038 = x13038 z13039 = x13039 z13040 = x13040 z13041 = x13041 z13042 = x13042 z13043 = x13043 z13044 = x13044 z13045 = x13045 z13046 = x13046 z13047 = x13047 z13048 = x13048 z13049 = x13049 z13050 = x13050 z13051 = x13051 z13052 = x13052 z13053 = x13053 z13054 = x13054 z13055 = x13055 z13056 = x13056 z13057 = x13057 z13058 = x13058 z13059 = x13059 z13060 = x13060 z13061 = x13061 z13062 = x13062 z13063 = x13063 z13064 = x13064 z13065 = x13065 z13066 = x13066 z13067 = x13067 z13068 = x13068 z13069 = x13069 z13070 = x13070 z13071 = x13071 z13072 = x13072 z13073 = x13073 z13074 = x13074 z13075 = x13075 z13076 = x13076 z13077 = x13077 z13078 = x13078 z13079 = x13079 z13080 = x13080 z13081 = x13081 z13082 = x13082 z13083 = x13083 z13084 = x13084 z13085 = x13085 z13086 = x13086 z13087 = x13087 z13088 = x13088 z13089 = x13089 z13090 = x13090 z13091 = x13091 z13092 = x13092 z13093 = x13093 z13094 = x13094 z13095 = x13095 z13096 = x13096 z13097 = x13097 z13098 = x13098 z13099 = x13099 z13100 = x13100 z13101 = x13101 z13102 = x13102 z13103 = x13103 z13104 = x13104 z13105 = x13105 z13106 = x13106 z13107 = x13107 z13108 = x13108 z13109 = x13109 z13110 = x13110 z13111 = x13111 z13112 = x13112 z13113 = x13113 z13114 = x13114 z13115 = x13115 z13116 = x13116 z13117 = x13117 z13118 = x13118 z13119 = x13119 z13120 = x13120 z13121 = x13121 z13122 = x13122 z13123 = x13123 z13124 = x13124 z13125 = x13125 z13126 = x13126 z13127 = x13127 z13128 = x13128 z13129 = x13129 z13130 = x13130 z13131 = x13131 z13132 = x13132 z13133 = x13133 z13134 = x13134 z13135 = x13135 z13136 = x13136 z13137 = x13137 z13138 = x13138 z13139 = x13139 z13140 = x13140 z13141 = x13141 z13142 = x13142 z13143 = x13143 z13144 = x13144 z13145 = x13145 z13146 = x13146 z13147 = x13147 z13148 = x13148 z13149 = x13149 z13150 = x13150 z13151 = x13151 z13152 = x13152 z13153 = x13153 z13154 = x13154 z13155 = x13155 z13156 = x13156 z13157 = x13157 z13158 = x13158 z13159 = x13159 z13160 = x13160 z13161 = x13161 z13162 = x13162 z13163 = x13163 z13164 = x13164 z13165 = x13165 z13166 = x13166 z13167 = x13167 z13168 = x13168 z13169 = x13169 z13170 = x13170 z13171 = x13171 z13172 = x13172 z13173 = x13173 z13174 = x13174 z13175 = x13175 z13176 = x13176 z13177 = x13177 z13178 = x13178 z13179 = x13179 z13180 = x13180 z13181 = x13181 z13182 = x13182 z13183 = x13183 z13184 = x13184 z13185 = x13185 z13186 = x13186 z13187 = x13187 z13188 = x13188 z13189 = x13189 z13190 = x13190 z13191 = x13191 z13192 = x13192 z13193 = x13193 z13194 = x13194 z13195 = x13195 z13196 = x13196 z13197 = x13197 z13198 = x13198 z13199 = x13199 z13200 = x13200 z13201 = x13201 z13202 = x13202 z13203 = x13203 z13204 = x13204 z13205 = x13205 z13206 = x13206 z13207 = x13207 z13208 = x13208 z13209 = x13209 z13210 = x13210 z13211 = x13211 z13212 = x13212 z13213 = x13213 z13214 = x13214 z13215 = x13215 z13216 = x13216 z13217 = x13217 z13218 = x13218 z13219 = x13219 z13220 = x13220 z13221 = x13221 z13222 = x13222 z13223 = x13223 z13224 = x13224 z13225 = x13225 z13226 = x13226 z13227 = x13227 z13228 = x13228 z13229 = x13229 z13230 = x13230 z13231 = x13231 z13232 = x13232 z13233 = x13233 z13234 = x13234 z13235 = x13235 z13236 = x13236 z13237 = x13237 z13238 = x13238 z13239 = x13239 z13240 = x13240 z13241 = x13241 z13242 = x13242 z13243 = x13243 z13244 = x13244 z13245 = x13245 z13246 = x13246 z13247 = x13247 z13248 = x13248 z13249 = x13249 z13250 = x13250 z13251 = x13251 z13252 = x13252 z13253 = x13253 z13254 = x13254 z13255 = x13255 z13256 = x13256 z13257 = x13257 z13258 = x13258 z13259 = x13259 z13260 = x13260 z13261 = x13261 z13262 = x13262 z13263 = x13263 z13264 = x13264 z13265 = x13265 z13266 = x13266 z13267 = x13267 z13268 = x13268 z13269 = x13269 z13270 = x13270 z13271 = x13271 z13272 = x13272 z13273 = x13273 z13274 = x13274 z13275 = x13275 z13276 = x13276 z13277 = x13277 z13278 = x13278 z13279 = x13279 z13280 = x13280 z13281 = x13281 z13282 = x13282 z13283 = x13283 z13284 = x13284 z13285 = x13285 z13286 = x13286 z13287 = x13287 z13288 = x13288 z13289 = x13289 z13290 = x13290 z13291 = x13291 z13292 = x13292 z13293 = x13293 z13294 = x13294 z13295 = x13295 z13296 = x13296 z13297 = x13297 z13298 = x13298 z13299 = x13299 z13300 = x13300 z13301 = x13301 z13302 = x13302 z13303 = x13303 z13304 = x13304 z13305 = x13305 z13306 = x13306 z13307 = x13307 z13308 = x13308 z13309 = x13309 z13310 = x13310 z13311 = x13311 z13312 = x13312 z13313 = x13313 z13314 = x13314 z13315 = x13315 z13316 = x13316 z13317 = x13317 z13318 = x13318 z13319 = x13319 z13320 = x13320 z13321 = x13321 z13322 = x13322 z13323 = x13323 z13324 = x13324 z13325 = x13325 z13326 = x13326 z13327 = x13327 z13328 = x13328 z13329 = x13329 z13330 = x13330 z13331 = x13331 z13332 = x13332 z13333 = x13333 z13334 = x13334 z13335 = x13335 z13336 = x13336 z13337 = x13337 z13338 = x13338 z13339 = x13339 z13340 = x13340 z13341 = x13341 z13342 = x13342 z13343 = x13343 z13344 = x13344 z13345 = x13345 z13346 = x13346 z13347 = x13347 z13348 = x13348 z13349 = x13349 z13350 = x13350 z13351 = x13351 z13352 = x13352 z13353 = x13353 z13354 = x13354 z13355 = x13355 z13356 = x13356 z13357 = x13357 z13358 = x13358 z13359 = x13359 z13360 = x13360 z13361 = x13361 z13362 = x13362 z13363 = x13363 z13364 = x13364 z13365 = x13365 z13366 = x13366 z13367 = x13367 z13368 = x13368 z13369 = x13369 z13370 = x13370 z13371 = x13371 z13372 = x13372 z13373 = x13373 z13374 = x13374 z13375 = x13375 z13376 = x13376 z13377 = x13377 z13378 = x13378 z13379 = x13379 z13380 = x13380 z13381 = x13381 z13382 = x13382 z13383 = x13383 z13384 = x13384 z13385 = x13385 z13386 = x13386 z13387 = x13387 z13388 = x13388 z13389 = x13389 z13390 = x13390 z13391 = x13391 z13392 = x13392 z13393 = x13393 z13394 = x13394 z13395 = x13395 z13396 = x13396 z13397 = x13397 z13398 = x13398 z13399 = x13399 z13400 = x13400 z13401 = x13401 z13402 = x13402 z13403 = x13403 z13404 = x13404 z13405 = x13405 z13406 = x13406 z13407 = x13407 z13408 = x13408 z13409 = x13409 z13410 = x13410 z13411 = x13411 z13412 = x13412 z13413 = x13413 z13414 = x13414 z13415 = x13415 z13416 = x13416 z13417 = x13417 z13418 = x13418 z13419 = x13419 z13420 = x13420 z13421 = x13421 z13422 = x13422 z13423 = x13423 z13424 = x13424 z13425 = x13425 z13426 = x13426 z13427 = x13427 z13428 = x13428 z13429 = x13429 z13430 = x13430 z13431 = x13431 z13432 = x13432 z13433 = x13433 z13434 = x13434 z13435 = x13435 z13436 = x13436 z13437 = x13437 z13438 = x13438 z13439 = x13439 z13440 = x13440 z13441 = x13441 z13442 = x13442 z13443 = x13443 z13444 = x13444 z13445 = x13445 z13446 = x13446 z13447 = x13447 z13448 = x13448 z13449 = x13449 z13450 = x13450 z13451 = x13451 z13452 = x13452 z13453 = x13453 z13454 = x13454 z13455 = x13455 z13456 = x13456 z13457 = x13457 z13458 = x13458 z13459 = x13459 z13460 = x13460 z13461 = x13461 z13462 = x13462 z13463 = x13463 z13464 = x13464 z13465 = x13465 z13466 = x13466 z13467 = x13467 z13468 = x13468 z13469 = x13469 z13470 = x13470 z13471 = x13471 z13472 = x13472 z13473 = x13473 z13474 = x13474 z13475 = x13475 z13476 = x13476 z13477 = x13477 z13478 = x13478 z13479 = x13479 z13480 = x13480 z13481 = x13481 z13482 = x13482 z13483 = x13483 z13484 = x13484 z13485 = x13485 z13486 = x13486 z13487 = x13487 z13488 = x13488 z13489 = x13489 z13490 = x13490 z13491 = x13491 z13492 = x13492 z13493 = x13493 z13494 = x13494 z13495 = x13495 z13496 = x13496 z13497 = x13497 z13498 = x13498 z13499 = x13499 z13500 = x13500 z13501 = x13501 z13502 = x13502 z13503 = x13503 z13504 = x13504 z13505 = x13505 z13506 = x13506 z13507 = x13507 z13508 = x13508 z13509 = x13509 z13510 = x13510 z13511 = x13511 z13512 = x13512 z13513 = x13513 z13514 = x13514 z13515 = x13515 z13516 = x13516 z13517 = x13517 z13518 = x13518 z13519 = x13519 z13520 = x13520 z13521 = x13521 z13522 = x13522 z13523 = x13523 z13524 = x13524 z13525 = x13525 z13526 = x13526 z13527 = x13527 z13528 = x13528 z13529 = x13529 z13530 = x13530 z13531 = x13531 z13532 = x13532 z13533 = x13533 z13534 = x13534 z13535 = x13535 z13536 = x13536 z13537 = x13537 z13538 = x13538 z13539 = x13539 z13540 = x13540 z13541 = x13541 z13542 = x13542 z13543 = x13543 z13544 = x13544 z13545 = x13545 z13546 = x13546 z13547 = x13547 z13548 = x13548 z13549 = x13549 z13550 = x13550 z13551 = x13551 z13552 = x13552 z13553 = x13553 z13554 = x13554 z13555 = x13555 z13556 = x13556 z13557 = x13557 z13558 = x13558 z13559 = x13559 z13560 = x13560 z13561 = x13561 z13562 = x13562 z13563 = x13563 z13564 = x13564 z13565 = x13565 z13566 = x13566 z13567 = x13567 z13568 = x13568 z13569 = x13569 z13570 = x13570 z13571 = x13571 z13572 = x13572 z13573 = x13573 z13574 = x13574 z13575 = x13575 z13576 = x13576 z13577 = x13577 z13578 = x13578 z13579 = x13579 z13580 = x13580 z13581 = x13581 z13582 = x13582 z13583 = x13583 z13584 = x13584 z13585 = x13585 z13586 = x13586 z13587 = x13587 z13588 = x13588 z13589 = x13589 z13590 = x13590 z13591 = x13591 z13592 = x13592 z13593 = x13593 z13594 = x13594 z13595 = x13595 z13596 = x13596 z13597 = x13597 z13598 = x13598 z13599 = x13599 z13600 = x13600 z13601 = x13601 z13602 = x13602 z13603 = x13603 z13604 = x13604 z13605 = x13605 z13606 = x13606 z13607 = x13607 z13608 = x13608 z13609 = x13609 z13610 = x13610 z13611 = x13611 z13612 = x13612 z13613 = x13613 z13614 = x13614 z13615 = x13615 z13616 = x13616 z13617 = x13617 z13618 = x13618 z13619 = x13619 z13620 = x13620 z13621 = x13621 z13622 = x13622 z13623 = x13623 z13624 = x13624 z13625 = x13625 z13626 = x13626 z13627 = x13627 z13628 = x13628 z13629 = x13629 z13630 = x13630 z13631 = x13631 z13632 = x13632 z13633 = x13633 z13634 = x13634 z13635 = x13635 z13636 = x13636 z13637 = x13637 z13638 = x13638 z13639 = x13639 z13640 = x13640 z13641 = x13641 z13642 = x13642 z13643 = x13643 z13644 = x13644 z13645 = x13645 z13646 = x13646 z13647 = x13647 z13648 = x13648 z13649 = x13649 z13650 = x13650 z13651 = x13651 z13652 = x13652 z13653 = x13653 z13654 = x13654 z13655 = x13655 z13656 = x13656 z13657 = x13657 z13658 = x13658 z13659 = x13659 z13660 = x13660 z13661 = x13661 z13662 = x13662 z13663 = x13663 z13664 = x13664 z13665 = x13665 z13666 = x13666 z13667 = x13667 z13668 = x13668 z13669 = x13669 z13670 = x13670 z13671 = x13671 z13672 = x13672 z13673 = x13673 z13674 = x13674 z13675 = x13675 z13676 = x13676 z13677 = x13677 z13678 = x13678 z13679 = x13679 z13680 = x13680 z13681 = x13681 z13682 = x13682 z13683 = x13683 z13684 = x13684 z13685 = x13685 z13686 = x13686 z13687 = x13687 z13688 = x13688 z13689 = x13689 z13690 = x13690 z13691 = x13691 z13692 = x13692 z13693 = x13693 z13694 = x13694 z13695 = x13695 z13696 = x13696 z13697 = x13697 z13698 = x13698 z13699 = x13699 z13700 = x13700 z13701 = x13701 z13702 = x13702 z13703 = x13703 z13704 = x13704 z13705 = x13705 z13706 = x13706 z13707 = x13707 z13708 = x13708 z13709 = x13709 z13710 = x13710 z13711 = x13711 z13712 = x13712 z13713 = x13713 z13714 = x13714 z13715 = x13715 z13716 = x13716 z13717 = x13717 z13718 = x13718 z13719 = x13719 z13720 = x13720 z13721 = x13721 z13722 = x13722 z13723 = x13723 z13724 = x13724 z13725 = x13725 z13726 = x13726 z13727 = x13727 z13728 = x13728 z13729 = x13729 z13730 = x13730 z13731 = x13731 z13732 = x13732 z13733 = x13733 z13734 = x13734 z13735 = x13735 z13736 = x13736 z13737 = x13737 z13738 = x13738 z13739 = x13739 z13740 = x13740 z13741 = x13741 z13742 = x13742 z13743 = x13743 z13744 = x13744 z13745 = x13745 z13746 = x13746 z13747 = x13747 z13748 = x13748 z13749 = x13749 z13750 = x13750 z13751 = x13751 z13752 = x13752 z13753 = x13753 z13754 = x13754 z13755 = x13755 z13756 = x13756 z13757 = x13757 z13758 = x13758 z13759 = x13759 z13760 = x13760 z13761 = x13761 z13762 = x13762 z13763 = x13763 z13764 = x13764 z13765 = x13765 z13766 = x13766 z13767 = x13767 z13768 = x13768 z13769 = x13769 z13770 = x13770 z13771 = x13771 z13772 = x13772 z13773 = x13773 z13774 = x13774 z13775 = x13775 z13776 = x13776 z13777 = x13777 z13778 = x13778 z13779 = x13779 z13780 = x13780 z13781 = x13781 z13782 = x13782 z13783 = x13783 z13784 = x13784 z13785 = x13785 z13786 = x13786 z13787 = x13787 z13788 = x13788 z13789 = x13789 z13790 = x13790 z13791 = x13791 z13792 = x13792 z13793 = x13793 z13794 = x13794 z13795 = x13795 z13796 = x13796 z13797 = x13797 z13798 = x13798 z13799 = x13799 z13800 = x13800 z13801 = x13801 z13802 = x13802 z13803 = x13803 z13804 = x13804 z13805 = x13805 z13806 = x13806 z13807 = x13807 z13808 = x13808 z13809 = x13809 z13810 = x13810 z13811 = x13811 z13812 = x13812 z13813 = x13813 z13814 = x13814 z13815 = x13815 z13816 = x13816 z13817 = x13817 z13818 = x13818 z13819 = x13819 z13820 = x13820 z13821 = x13821 z13822 = x13822 z13823 = x13823 z13824 = x13824 z13825 = x13825 z13826 = x13826 z13827 = x13827 z13828 = x13828 z13829 = x13829 z13830 = x13830 z13831 = x13831 z13832 = x13832 z13833 = x13833 z13834 = x13834 z13835 = x13835 z13836 = x13836 z13837 = x13837 z13838 = x13838 z13839 = x13839 z13840 = x13840 z13841 = x13841 z13842 = x13842 z13843 = x13843 z13844 = x13844 z13845 = x13845 z13846 = x13846 z13847 = x13847 z13848 = x13848 z13849 = x13849 z13850 = x13850 z13851 = x13851 z13852 = x13852 z13853 = x13853 z13854 = x13854 z13855 = x13855 z13856 = x13856 z13857 = x13857 z13858 = x13858 z13859 = x13859 z13860 = x13860 z13861 = x13861 z13862 = x13862 z13863 = x13863 z13864 = x13864 z13865 = x13865 z13866 = x13866 z13867 = x13867 z13868 = x13868 z13869 = x13869 z13870 = x13870 z13871 = x13871 z13872 = x13872 z13873 = x13873 z13874 = x13874 z13875 = x13875 z13876 = x13876 z13877 = x13877 z13878 = x13878 z13879 = x13879 z13880 = x13880 z13881 = x13881 z13882 = x13882 z13883 = x13883 z13884 = x13884 z13885 = x13885 z13886 = x13886 z13887 = x13887 z13888 = x13888 z13889 = x13889 z13890 = x13890 z13891 = x13891 z13892 = x13892 z13893 = x13893 z13894 = x13894 z13895 = x13895 z13896 = x13896 z13897 = x13897 z13898 = x13898 z13899 = x13899 z13900 = x13900 z13901 = x13901 z13902 = x13902 z13903 = x13903 z13904 = x13904 z13905 = x13905 z13906 = x13906 z13907 = x13907 z13908 = x13908 z13909 = x13909 z13910 = x13910 z13911 = x13911 z13912 = x13912 z13913 = x13913 z13914 = x13914 z13915 = x13915 z13916 = x13916 z13917 = x13917 z13918 = x13918 z13919 = x13919 z13920 = x13920 z13921 = x13921 z13922 = x13922 z13923 = x13923 z13924 = x13924 z13925 = x13925 z13926 = x13926 z13927 = x13927 z13928 = x13928 z13929 = x13929 z13930 = x13930 z13931 = x13931 z13932 = x13932 z13933 = x13933 z13934 = x13934 z13935 = x13935 z13936 = x13936 z13937 = x13937 z13938 = x13938 z13939 = x13939 z13940 = x13940 z13941 = x13941 z13942 = x13942 z13943 = x13943 z13944 = x13944 z13945 = x13945 z13946 = x13946 z13947 = x13947 z13948 = x13948 z13949 = x13949 z13950 = x13950 z13951 = x13951 z13952 = x13952 z13953 = x13953 z13954 = x13954 z13955 = x13955 z13956 = x13956 z13957 = x13957 z13958 = x13958 z13959 = x13959 z13960 = x13960 z13961 = x13961 z13962 = x13962 z13963 = x13963 z13964 = x13964 z13965 = x13965 z13966 = x13966 z13967 = x13967 z13968 = x13968 z13969 = x13969 z13970 = x13970 z13971 = x13971 z13972 = x13972 z13973 = x13973 z13974 = x13974 z13975 = x13975 z13976 = x13976 z13977 = x13977 z13978 = x13978 z13979 = x13979 z13980 = x13980 z13981 = x13981 z13982 = x13982 z13983 = x13983 z13984 = x13984 z13985 = x13985 z13986 = x13986 z13987 = x13987 z13988 = x13988 z13989 = x13989 z13990 = x13990 z13991 = x13991 z13992 = x13992 z13993 = x13993 z13994 = x13994 z13995 = x13995 z13996 = x13996 z13997 = x13997 z13998 = x13998 z13999 = x13999 z14000 = x14000 z14001 = x14001 z14002 = x14002 z14003 = x14003 z14004 = x14004 z14005 = x14005 z14006 = x14006 z14007 = x14007 z14008 = x14008 z14009 = x14009 z14010 = x14010 z14011 = x14011 z14012 = x14012 z14013 = x14013 z14014 = x14014 z14015 = x14015 z14016 = x14016 z14017 = x14017 z14018 = x14018 z14019 = x14019 z14020 = x14020 z14021 = x14021 z14022 = x14022 z14023 = x14023 z14024 = x14024 z14025 = x14025 z14026 = x14026 z14027 = x14027 z14028 = x14028 z14029 = x14029 z14030 = x14030 z14031 = x14031 z14032 = x14032 z14033 = x14033 z14034 = x14034 z14035 = x14035 z14036 = x14036 z14037 = x14037 z14038 = x14038 z14039 = x14039 z14040 = x14040 z14041 = x14041 z14042 = x14042 z14043 = x14043 z14044 = x14044 z14045 = x14045 z14046 = x14046 z14047 = x14047 z14048 = x14048 z14049 = x14049 z14050 = x14050 z14051 = x14051 z14052 = x14052 z14053 = x14053 z14054 = x14054 z14055 = x14055 z14056 = x14056 z14057 = x14057 z14058 = x14058 z14059 = x14059 z14060 = x14060 z14061 = x14061 z14062 = x14062 z14063 = x14063 z14064 = x14064 z14065 = x14065 z14066 = x14066 z14067 = x14067 z14068 = x14068 z14069 = x14069 z14070 = x14070 z14071 = x14071 z14072 = x14072 z14073 = x14073 z14074 = x14074 z14075 = x14075 z14076 = x14076 z14077 = x14077 z14078 = x14078 z14079 = x14079 z14080 = x14080 z14081 = x14081 z14082 = x14082 z14083 = x14083 z14084 = x14084 z14085 = x14085 z14086 = x14086 z14087 = x14087 z14088 = x14088 z14089 = x14089 z14090 = x14090 z14091 = x14091 z14092 = x14092 z14093 = x14093 z14094 = x14094 z14095 = x14095 z14096 = x14096 z14097 = x14097 z14098 = x14098 z14099 = x14099 z14100 = x14100 z14101 = x14101 z14102 = x14102 z14103 = x14103 z14104 = x14104 z14105 = x14105 z14106 = x14106 z14107 = x14107 z14108 = x14108 z14109 = x14109 z14110 = x14110 z14111 = x14111 z14112 = x14112 z14113 = x14113 z14114 = x14114 z14115 = x14115 z14116 = x14116 z14117 = x14117 z14118 = x14118 z14119 = x14119 z14120 = x14120 z14121 = x14121 z14122 = x14122 z14123 = x14123 z14124 = x14124 z14125 = x14125 z14126 = x14126 z14127 = x14127 z14128 = x14128 z14129 = x14129 z14130 = x14130 z14131 = x14131 z14132 = x14132 z14133 = x14133 z14134 = x14134 z14135 = x14135 z14136 = x14136 z14137 = x14137 z14138 = x14138 z14139 = x14139 z14140 = x14140 z14141 = x14141 z14142 = x14142 z14143 = x14143 z14144 = x14144 z14145 = x14145 z14146 = x14146 z14147 = x14147 z14148 = x14148 z14149 = x14149 z14150 = x14150 z14151 = x14151 z14152 = x14152 z14153 = x14153 z14154 = x14154 z14155 = x14155 z14156 = x14156 z14157 = x14157 z14158 = x14158 z14159 = x14159 z14160 = x14160 z14161 = x14161 z14162 = x14162 z14163 = x14163 z14164 = x14164 z14165 = x14165 z14166 = x14166 z14167 = x14167 z14168 = x14168 z14169 = x14169 z14170 = x14170 z14171 = x14171 z14172 = x14172 z14173 = x14173 z14174 = x14174 z14175 = x14175 z14176 = x14176 z14177 = x14177 z14178 = x14178 z14179 = x14179 z14180 = x14180 z14181 = x14181 z14182 = x14182 z14183 = x14183 z14184 = x14184 z14185 = x14185 z14186 = x14186 z14187 = x14187 z14188 = x14188 z14189 = x14189 z14190 = x14190 z14191 = x14191 z14192 = x14192 z14193 = x14193 z14194 = x14194 z14195 = x14195 z14196 = x14196 z14197 = x14197 z14198 = x14198 z14199 = x14199 z14200 = x14200 z14201 = x14201 z14202 = x14202 z14203 = x14203 z14204 = x14204 z14205 = x14205 z14206 = x14206 z14207 = x14207 z14208 = x14208 z14209 = x14209 z14210 = x14210 z14211 = x14211 z14212 = x14212 z14213 = x14213 z14214 = x14214 z14215 = x14215 z14216 = x14216 z14217 = x14217 z14218 = x14218 z14219 = x14219 z14220 = x14220 z14221 = x14221 z14222 = x14222 z14223 = x14223 z14224 = x14224 z14225 = x14225 z14226 = x14226 z14227 = x14227 z14228 = x14228 z14229 = x14229 z14230 = x14230 z14231 = x14231 z14232 = x14232 z14233 = x14233 z14234 = x14234 z14235 = x14235 z14236 = x14236 z14237 = x14237 z14238 = x14238 z14239 = x14239 z14240 = x14240 z14241 = x14241 z14242 = x14242 z14243 = x14243 z14244 = x14244 z14245 = x14245 z14246 = x14246 z14247 = x14247 z14248 = x14248 z14249 = x14249 z14250 = x14250 z14251 = x14251 z14252 = x14252 z14253 = x14253 z14254 = x14254 z14255 = x14255 z14256 = x14256 z14257 = x14257 z14258 = x14258 z14259 = x14259 z14260 = x14260 z14261 = x14261 z14262 = x14262 z14263 = x14263 z14264 = x14264 z14265 = x14265 z14266 = x14266 z14267 = x14267 z14268 = x14268 z14269 = x14269 z14270 = x14270 z14271 = x14271 z14272 = x14272 z14273 = x14273 z14274 = x14274 z14275 = x14275 z14276 = x14276 z14277 = x14277 z14278 = x14278 z14279 = x14279 z14280 = x14280 z14281 = x14281 z14282 = x14282 z14283 = x14283 z14284 = x14284 z14285 = x14285 z14286 = x14286 z14287 = x14287 z14288 = x14288 z14289 = x14289 z14290 = x14290 z14291 = x14291 z14292 = x14292 z14293 = x14293 z14294 = x14294 z14295 = x14295 z14296 = x14296 z14297 = x14297 z14298 = x14298 z14299 = x14299 z14300 = x14300 z14301 = x14301 z14302 = x14302 z14303 = x14303 z14304 = x14304 z14305 = x14305 z14306 = x14306 z14307 = x14307 z14308 = x14308 z14309 = x14309 z14310 = x14310 z14311 = x14311 z14312 = x14312 z14313 = x14313 z14314 = x14314 z14315 = x14315 z14316 = x14316 z14317 = x14317 z14318 = x14318 z14319 = x14319 z14320 = x14320 z14321 = x14321 z14322 = x14322 z14323 = x14323 z14324 = x14324 z14325 = x14325 z14326 = x14326 z14327 = x14327 z14328 = x14328 z14329 = x14329 z14330 = x14330 z14331 = x14331 z14332 = x14332 z14333 = x14333 z14334 = x14334 z14335 = x14335 z14336 = x14336 z14337 = x14337 z14338 = x14338 z14339 = x14339 z14340 = x14340 z14341 = x14341 z14342 = x14342 z14343 = x14343 z14344 = x14344 z14345 = x14345 z14346 = x14346 z14347 = x14347 z14348 = x14348 z14349 = x14349 z14350 = x14350 z14351 = x14351 z14352 = x14352 z14353 = x14353 z14354 = x14354 z14355 = x14355 z14356 = x14356 z14357 = x14357 z14358 = x14358 z14359 = x14359 z14360 = x14360 z14361 = x14361 z14362 = x14362 z14363 = x14363 z14364 = x14364 z14365 = x14365 z14366 = x14366 z14367 = x14367 z14368 = x14368 z14369 = x14369 z14370 = x14370 z14371 = x14371 z14372 = x14372 z14373 = x14373 z14374 = x14374 z14375 = x14375 z14376 = x14376 z14377 = x14377 z14378 = x14378 z14379 = x14379 z14380 = x14380 z14381 = x14381 z14382 = x14382 z14383 = x14383 z14384 = x14384 z14385 = x14385 z14386 = x14386 z14387 = x14387 z14388 = x14388 z14389 = x14389 z14390 = x14390 z14391 = x14391 z14392 = x14392 z14393 = x14393 z14394 = x14394 z14395 = x14395 z14396 = x14396 z14397 = x14397 z14398 = x14398 z14399 = x14399 z14400 = x14400 z14401 = x14401 z14402 = x14402 z14403 = x14403 z14404 = x14404 z14405 = x14405 z14406 = x14406 z14407 = x14407 z14408 = x14408 z14409 = x14409 z14410 = x14410 z14411 = x14411 z14412 = x14412 z14413 = x14413 z14414 = x14414 z14415 = x14415 z14416 = x14416 z14417 = x14417 z14418 = x14418 z14419 = x14419 z14420 = x14420 z14421 = x14421 z14422 = x14422 z14423 = x14423 z14424 = x14424 z14425 = x14425 z14426 = x14426 z14427 = x14427 z14428 = x14428 z14429 = x14429 z14430 = x14430 z14431 = x14431 z14432 = x14432 z14433 = x14433 z14434 = x14434 z14435 = x14435 z14436 = x14436 z14437 = x14437 z14438 = x14438 z14439 = x14439 z14440 = x14440 z14441 = x14441 z14442 = x14442 z14443 = x14443 z14444 = x14444 z14445 = x14445 z14446 = x14446 z14447 = x14447 z14448 = x14448 z14449 = x14449 z14450 = x14450 z14451 = x14451 z14452 = x14452 z14453 = x14453 z14454 = x14454 z14455 = x14455 z14456 = x14456 z14457 = x14457 z14458 = x14458 z14459 = x14459 z14460 = x14460 z14461 = x14461 z14462 = x14462 z14463 = x14463 z14464 = x14464 z14465 = x14465 z14466 = x14466 z14467 = x14467 z14468 = x14468 z14469 = x14469 z14470 = x14470 z14471 = x14471 z14472 = x14472 z14473 = x14473 z14474 = x14474 z14475 = x14475 z14476 = x14476 z14477 = x14477 z14478 = x14478 z14479 = x14479 z14480 = x14480 z14481 = x14481 z14482 = x14482 z14483 = x14483 z14484 = x14484 z14485 = x14485 z14486 = x14486 z14487 = x14487 z14488 = x14488 z14489 = x14489 z14490 = x14490 z14491 = x14491 z14492 = x14492 z14493 = x14493 z14494 = x14494 z14495 = x14495 z14496 = x14496 z14497 = x14497 z14498 = x14498 z14499 = x14499 z14500 = x14500 z14501 = x14501 z14502 = x14502 z14503 = x14503 z14504 = x14504 z14505 = x14505 z14506 = x14506 z14507 = x14507 z14508 = x14508 z14509 = x14509 z14510 = x14510 z14511 = x14511 z14512 = x14512 z14513 = x14513 z14514 = x14514 z14515 = x14515 z14516 = x14516 z14517 = x14517 z14518 = x14518 z14519 = x14519 z14520 = x14520 z14521 = x14521 z14522 = x14522 z14523 = x14523 z14524 = x14524 z14525 = x14525 z14526 = x14526 z14527 = x14527 z14528 = x14528 z14529 = x14529 z14530 = x14530 z14531 = x14531 z14532 = x14532 z14533 = x14533 z14534 = x14534 z14535 = x14535 z14536 = x14536 z14537 = x14537 z14538 = x14538 z14539 = x14539 z14540 = x14540 z14541 = x14541 z14542 = x14542 z14543 = x14543 z14544 = x14544 z14545 = x14545 z14546 = x14546 z14547 = x14547 z14548 = x14548 z14549 = x14549 z14550 = x14550 z14551 = x14551 z14552 = x14552 z14553 = x14553 z14554 = x14554 z14555 = x14555 z14556 = x14556 z14557 = x14557 z14558 = x14558 z14559 = x14559 z14560 = x14560 z14561 = x14561 z14562 = x14562 z14563 = x14563 z14564 = x14564 z14565 = x14565 z14566 = x14566 z14567 = x14567 z14568 = x14568 z14569 = x14569 z14570 = x14570 z14571 = x14571 z14572 = x14572 z14573 = x14573 z14574 = x14574 z14575 = x14575 z14576 = x14576 z14577 = x14577 z14578 = x14578 z14579 = x14579 z14580 = x14580 z14581 = x14581 z14582 = x14582 z14583 = x14583 z14584 = x14584 z14585 = x14585 z14586 = x14586 z14587 = x14587 z14588 = x14588 z14589 = x14589 z14590 = x14590 z14591 = x14591 z14592 = x14592 z14593 = x14593 z14594 = x14594 z14595 = x14595 z14596 = x14596 z14597 = x14597 z14598 = x14598 z14599 = x14599 z14600 = x14600 z14601 = x14601 z14602 = x14602 z14603 = x14603 z14604 = x14604 z14605 = x14605 z14606 = x14606 z14607 = x14607 z14608 = x14608 z14609 = x14609 z14610 = x14610 z14611 = x14611 z14612 = x14612 z14613 = x14613 z14614 = x14614 z14615 = x14615 z14616 = x14616 z14617 = x14617 z14618 = x14618 z14619 = x14619 z14620 = x14620 z14621 = x14621 z14622 = x14622 z14623 = x14623 z14624 = x14624 z14625 = x14625 z14626 = x14626 z14627 = x14627 z14628 = x14628 z14629 = x14629 z14630 = x14630 z14631 = x14631 z14632 = x14632 z14633 = x14633 z14634 = x14634 z14635 = x14635 z14636 = x14636 z14637 = x14637 z14638 = x14638 z14639 = x14639 z14640 = x14640 z14641 = x14641 z14642 = x14642 z14643 = x14643 z14644 = x14644 z14645 = x14645 z14646 = x14646 z14647 = x14647 z14648 = x14648 z14649 = x14649 z14650 = x14650 z14651 = x14651 z14652 = x14652 z14653 = x14653 z14654 = x14654 z14655 = x14655 z14656 = x14656 z14657 = x14657 z14658 = x14658 z14659 = x14659 z14660 = x14660 z14661 = x14661 z14662 = x14662 z14663 = x14663 z14664 = x14664 z14665 = x14665 z14666 = x14666 z14667 = x14667 z14668 = x14668 z14669 = x14669 z14670 = x14670 z14671 = x14671 z14672 = x14672 z14673 = x14673 z14674 = x14674 z14675 = x14675 z14676 = x14676 z14677 = x14677 z14678 = x14678 z14679 = x14679 z14680 = x14680 z14681 = x14681 z14682 = x14682 z14683 = x14683 z14684 = x14684 z14685 = x14685 z14686 = x14686 z14687 = x14687 z14688 = x14688 z14689 = x14689 z14690 = x14690 z14691 = x14691 z14692 = x14692 z14693 = x14693 z14694 = x14694 z14695 = x14695 z14696 = x14696 z14697 = x14697 z14698 = x14698 z14699 = x14699 z14700 = x14700 z14701 = x14701 z14702 = x14702 z14703 = x14703 z14704 = x14704 z14705 = x14705 z14706 = x14706 z14707 = x14707 z14708 = x14708 z14709 = x14709 z14710 = x14710 z14711 = x14711 z14712 = x14712 z14713 = x14713 z14714 = x14714 z14715 = x14715 z14716 = x14716 z14717 = x14717 z14718 = x14718 z14719 = x14719 z14720 = x14720 z14721 = x14721 z14722 = x14722 z14723 = x14723 z14724 = x14724 z14725 = x14725 z14726 = x14726 z14727 = x14727 z14728 = x14728 z14729 = x14729 z14730 = x14730 z14731 = x14731 z14732 = x14732 z14733 = x14733 z14734 = x14734 z14735 = x14735 z14736 = x14736 z14737 = x14737 z14738 = x14738 z14739 = x14739 z14740 = x14740 z14741 = x14741 z14742 = x14742 z14743 = x14743 z14744 = x14744 z14745 = x14745 z14746 = x14746 z14747 = x14747 z14748 = x14748 z14749 = x14749 z14750 = x14750 z14751 = x14751 z14752 = x14752 z14753 = x14753 z14754 = x14754 z14755 = x14755 z14756 = x14756 z14757 = x14757 z14758 = x14758 z14759 = x14759 z14760 = x14760 z14761 = x14761 z14762 = x14762 z14763 = x14763 z14764 = x14764 z14765 = x14765 z14766 = x14766 z14767 = x14767 z14768 = x14768 z14769 = x14769 z14770 = x14770 z14771 = x14771 z14772 = x14772 z14773 = x14773 z14774 = x14774 z14775 = x14775 z14776 = x14776 z14777 = x14777 z14778 = x14778 z14779 = x14779 z14780 = x14780 z14781 = x14781 z14782 = x14782 z14783 = x14783 z14784 = x14784 z14785 = x14785 z14786 = x14786 z14787 = x14787 z14788 = x14788 z14789 = x14789 z14790 = x14790 z14791 = x14791 z14792 = x14792 z14793 = x14793 z14794 = x14794 z14795 = x14795 z14796 = x14796 z14797 = x14797 z14798 = x14798 z14799 = x14799 z14800 = x14800 z14801 = x14801 z14802 = x14802 z14803 = x14803 z14804 = x14804 z14805 = x14805 z14806 = x14806 z14807 = x14807 z14808 = x14808 z14809 = x14809 z14810 = x14810 z14811 = x14811 z14812 = x14812 z14813 = x14813 z14814 = x14814 z14815 = x14815 z14816 = x14816 z14817 = x14817 z14818 = x14818 z14819 = x14819 z14820 = x14820 z14821 = x14821 z14822 = x14822 z14823 = x14823 z14824 = x14824 z14825 = x14825 z14826 = x14826 z14827 = x14827 z14828 = x14828 z14829 = x14829 z14830 = x14830 z14831 = x14831 z14832 = x14832 z14833 = x14833 z14834 = x14834 z14835 = x14835 z14836 = x14836 z14837 = x14837 z14838 = x14838 z14839 = x14839 z14840 = x14840 z14841 = x14841 z14842 = x14842 z14843 = x14843 z14844 = x14844 z14845 = x14845 z14846 = x14846 z14847 = x14847 z14848 = x14848 z14849 = x14849 z14850 = x14850 z14851 = x14851 z14852 = x14852 z14853 = x14853 z14854 = x14854 z14855 = x14855 z14856 = x14856 z14857 = x14857 z14858 = x14858 z14859 = x14859 z14860 = x14860 z14861 = x14861 z14862 = x14862 z14863 = x14863 z14864 = x14864 z14865 = x14865 z14866 = x14866 z14867 = x14867 z14868 = x14868 z14869 = x14869 z14870 = x14870 z14871 = x14871 z14872 = x14872 z14873 = x14873 z14874 = x14874 z14875 = x14875 z14876 = x14876 z14877 = x14877 z14878 = x14878 z14879 = x14879 z14880 = x14880 z14881 = x14881 z14882 = x14882 z14883 = x14883 z14884 = x14884 z14885 = x14885 z14886 = x14886 z14887 = x14887 z14888 = x14888 z14889 = x14889 z14890 = x14890 z14891 = x14891 z14892 = x14892 z14893 = x14893 z14894 = x14894 z14895 = x14895 z14896 = x14896 z14897 = x14897 z14898 = x14898 z14899 = x14899 z14900 = x14900 z14901 = x14901 z14902 = x14902 z14903 = x14903 z14904 = x14904 z14905 = x14905 z14906 = x14906 z14907 = x14907 z14908 = x14908 z14909 = x14909 z14910 = x14910 z14911 = x14911 z14912 = x14912 z14913 = x14913 z14914 = x14914 z14915 = x14915 z14916 = x14916 z14917 = x14917 z14918 = x14918 z14919 = x14919 z14920 = x14920 z14921 = x14921 z14922 = x14922 z14923 = x14923 z14924 = x14924 z14925 = x14925 z14926 = x14926 z14927 = x14927 z14928 = x14928 z14929 = x14929 z14930 = x14930 z14931 = x14931 z14932 = x14932 z14933 = x14933 z14934 = x14934 z14935 = x14935 z14936 = x14936 z14937 = x14937 z14938 = x14938 z14939 = x14939 z14940 = x14940 z14941 = x14941 z14942 = x14942 z14943 = x14943 z14944 = x14944 z14945 = x14945 z14946 = x14946 z14947 = x14947 z14948 = x14948 z14949 = x14949 z14950 = x14950 z14951 = x14951 z14952 = x14952 z14953 = x14953 z14954 = x14954 z14955 = x14955 z14956 = x14956 z14957 = x14957 z14958 = x14958 z14959 = x14959 z14960 = x14960 z14961 = x14961 z14962 = x14962 z14963 = x14963 z14964 = x14964 z14965 = x14965 z14966 = x14966 z14967 = x14967 z14968 = x14968 z14969 = x14969 z14970 = x14970 z14971 = x14971 z14972 = x14972 z14973 = x14973 z14974 = x14974 z14975 = x14975 z14976 = x14976 z14977 = x14977 z14978 = x14978 z14979 = x14979 z14980 = x14980 z14981 = x14981 z14982 = x14982 z14983 = x14983 z14984 = x14984 z14985 = x14985 z14986 = x14986 z14987 = x14987 z14988 = x14988 z14989 = x14989 z14990 = x14990 z14991 = x14991 z14992 = x14992 z14993 = x14993 z14994 = x14994 z14995 = x14995 z14996 = x14996 z14997 = x14997 z14998 = x14998 z14999 = x14999 z15000 = x15000 z15001 = x15001 z15002 = x15002 z15003 = x15003 z15004 = x15004 z15005 = x15005 z15006 = x15006 z15007 = x15007 z15008 = x15008 z15009 = x15009 z15010 = x15010 z15011 = x15011 z15012 = x15012 z15013 = x15013 z15014 = x15014 z15015 = x15015 z15016 = x15016 z15017 = x15017 z15018 = x15018 z15019 = x15019 z15020 = x15020 z15021 = x15021 z15022 = x15022 z15023 = x15023 z15024 = x15024 z15025 = x15025 z15026 = x15026 z15027 = x15027 z15028 = x15028 z15029 = x15029 z15030 = x15030 z15031 = x15031 z15032 = x15032 z15033 = x15033 z15034 = x15034 z15035 = x15035 z15036 = x15036 z15037 = x15037 z15038 = x15038 z15039 = x15039 z15040 = x15040 z15041 = x15041 z15042 = x15042 z15043 = x15043 z15044 = x15044 z15045 = x15045 z15046 = x15046 z15047 = x15047 z15048 = x15048 z15049 = x15049 z15050 = x15050 z15051 = x15051 z15052 = x15052 z15053 = x15053 z15054 = x15054 z15055 = x15055 z15056 = x15056 z15057 = x15057 z15058 = x15058 z15059 = x15059 z15060 = x15060 z15061 = x15061 z15062 = x15062 z15063 = x15063 z15064 = x15064 z15065 = x15065 z15066 = x15066 z15067 = x15067 z15068 = x15068 z15069 = x15069 z15070 = x15070 z15071 = x15071 z15072 = x15072 z15073 = x15073 z15074 = x15074 z15075 = x15075 z15076 = x15076 z15077 = x15077 z15078 = x15078 z15079 = x15079 z15080 = x15080 z15081 = x15081 z15082 = x15082 z15083 = x15083 z15084 = x15084 z15085 = x15085 z15086 = x15086 z15087 = x15087 z15088 = x15088 z15089 = x15089 z15090 = x15090 z15091 = x15091 z15092 = x15092 z15093 = x15093 z15094 = x15094 z15095 = x15095 z15096 = x15096 z15097 = x15097 z15098 = x15098 z15099 = x15099 z15100 = x15100 z15101 = x15101 z15102 = x15102 z15103 = x15103 z15104 = x15104 z15105 = x15105 z15106 = x15106 z15107 = x15107 z15108 = x15108 z15109 = x15109 z15110 = x15110 z15111 = x15111 z15112 = x15112 z15113 = x15113 z15114 = x15114 z15115 = x15115 z15116 = x15116 z15117 = x15117 z15118 = x15118 z15119 = x15119 z15120 = x15120 z15121 = x15121 z15122 = x15122 z15123 = x15123 z15124 = x15124 z15125 = x15125 z15126 = x15126 z15127 = x15127 z15128 = x15128 z15129 = x15129 z15130 = x15130 z15131 = x15131 z15132 = x15132 z15133 = x15133 z15134 = x15134 z15135 = x15135 z15136 = x15136 z15137 = x15137 z15138 = x15138 z15139 = x15139 z15140 = x15140 z15141 = x15141 z15142 = x15142 z15143 = x15143 z15144 = x15144 z15145 = x15145 z15146 = x15146 z15147 = x15147 z15148 = x15148 z15149 = x15149 z15150 = x15150 z15151 = x15151 z15152 = x15152 z15153 = x15153 z15154 = x15154 z15155 = x15155 z15156 = x15156 z15157 = x15157 z15158 = x15158 z15159 = x15159 z15160 = x15160 z15161 = x15161 z15162 = x15162 z15163 = x15163 z15164 = x15164 z15165 = x15165 z15166 = x15166 z15167 = x15167 z15168 = x15168 z15169 = x15169 z15170 = x15170 z15171 = x15171 z15172 = x15172 z15173 = x15173 z15174 = x15174 z15175 = x15175 z15176 = x15176 z15177 = x15177 z15178 = x15178 z15179 = x15179 z15180 = x15180 z15181 = x15181 z15182 = x15182 z15183 = x15183 z15184 = x15184 z15185 = x15185 z15186 = x15186 z15187 = x15187 z15188 = x15188 z15189 = x15189 z15190 = x15190 z15191 = x15191 z15192 = x15192 z15193 = x15193 z15194 = x15194 z15195 = x15195 z15196 = x15196 z15197 = x15197 z15198 = x15198 z15199 = x15199 z15200 = x15200 z15201 = x15201 z15202 = x15202 z15203 = x15203 z15204 = x15204 z15205 = x15205 z15206 = x15206 z15207 = x15207 z15208 = x15208 z15209 = x15209 z15210 = x15210 z15211 = x15211 z15212 = x15212 z15213 = x15213 z15214 = x15214 z15215 = x15215 z15216 = x15216 z15217 = x15217 z15218 = x15218 z15219 = x15219 z15220 = x15220 z15221 = x15221 z15222 = x15222 z15223 = x15223 z15224 = x15224 z15225 = x15225 z15226 = x15226 z15227 = x15227 z15228 = x15228 z15229 = x15229 z15230 = x15230 z15231 = x15231 z15232 = x15232 z15233 = x15233 z15234 = x15234 z15235 = x15235 z15236 = x15236 z15237 = x15237 z15238 = x15238 z15239 = x15239 z15240 = x15240 z15241 = x15241 z15242 = x15242 z15243 = x15243 z15244 = x15244 z15245 = x15245 z15246 = x15246 z15247 = x15247 z15248 = x15248 z15249 = x15249 z15250 = x15250 z15251 = x15251 z15252 = x15252 z15253 = x15253 z15254 = x15254 z15255 = x15255 z15256 = x15256 z15257 = x15257 z15258 = x15258 z15259 = x15259 z15260 = x15260 z15261 = x15261 z15262 = x15262 z15263 = x15263 z15264 = x15264 z15265 = x15265 z15266 = x15266 z15267 = x15267 z15268 = x15268 z15269 = x15269 z15270 = x15270 z15271 = x15271 z15272 = x15272 z15273 = x15273 z15274 = x15274 z15275 = x15275 z15276 = x15276 z15277 = x15277 z15278 = x15278 z15279 = x15279 z15280 = x15280 z15281 = x15281 z15282 = x15282 z15283 = x15283 z15284 = x15284 z15285 = x15285 z15286 = x15286 z15287 = x15287 z15288 = x15288 z15289 = x15289 z15290 = x15290 z15291 = x15291 z15292 = x15292 z15293 = x15293 z15294 = x15294 z15295 = x15295 z15296 = x15296 z15297 = x15297 z15298 = x15298 z15299 = x15299 z15300 = x15300 z15301 = x15301 z15302 = x15302 z15303 = x15303 z15304 = x15304 z15305 = x15305 z15306 = x15306 z15307 = x15307 z15308 = x15308 z15309 = x15309 z15310 = x15310 z15311 = x15311 z15312 = x15312 z15313 = x15313 z15314 = x15314 z15315 = x15315 z15316 = x15316 z15317 = x15317 z15318 = x15318 z15319 = x15319 z15320 = x15320 z15321 = x15321 z15322 = x15322 z15323 = x15323 z15324 = x15324 z15325 = x15325 z15326 = x15326 z15327 = x15327 z15328 = x15328 z15329 = x15329 z15330 = x15330 z15331 = x15331 z15332 = x15332 z15333 = x15333 z15334 = x15334 z15335 = x15335 z15336 = x15336 z15337 = x15337 z15338 = x15338 z15339 = x15339 z15340 = x15340 z15341 = x15341 z15342 = x15342 z15343 = x15343 z15344 = x15344 z15345 = x15345 z15346 = x15346 z15347 = x15347 z15348 = x15348 z15349 = x15349 z15350 = x15350 z15351 = x15351 z15352 = x15352 z15353 = x15353 z15354 = x15354 z15355 = x15355 z15356 = x15356 z15357 = x15357 z15358 = x15358 z15359 = x15359 z15360 = x15360 z15361 = x15361 z15362 = x15362 z15363 = x15363 z15364 = x15364 z15365 = x15365 z15366 = x15366 z15367 = x15367 z15368 = x15368 z15369 = x15369 z15370 = x15370 z15371 = x15371 z15372 = x15372 z15373 = x15373 z15374 = x15374 z15375 = x15375 z15376 = x15376 z15377 = x15377 z15378 = x15378 z15379 = x15379 z15380 = x15380 z15381 = x15381 z15382 = x15382 z15383 = x15383 z15384 = x15384 z15385 = x15385 z15386 = x15386 z15387 = x15387 z15388 = x15388 z15389 = x15389 z15390 = x15390 z15391 = x15391 z15392 = x15392 z15393 = x15393 z15394 = x15394 z15395 = x15395 z15396 = x15396 z15397 = x15397 z15398 = x15398 z15399 = x15399 z15400 = x15400 z15401 = x15401 z15402 = x15402 z15403 = x15403 z15404 = x15404 z15405 = x15405 z15406 = x15406 z15407 = x15407 z15408 = x15408 z15409 = x15409 z15410 = x15410 z15411 = x15411 z15412 = x15412 z15413 = x15413 z15414 = x15414 z15415 = x15415 z15416 = x15416 z15417 = x15417 z15418 = x15418 z15419 = x15419 z15420 = x15420 z15421 = x15421 z15422 = x15422 z15423 = x15423 z15424 = x15424 z15425 = x15425 z15426 = x15426 z15427 = x15427 z15428 = x15428 z15429 = x15429 z15430 = x15430 z15431 = x15431 z15432 = x15432 z15433 = x15433 z15434 = x15434 z15435 = x15435 z15436 = x15436 z15437 = x15437 z15438 = x15438 z15439 = x15439 z15440 = x15440 z15441 = x15441 z15442 = x15442 z15443 = x15443 z15444 = x15444 z15445 = x15445 z15446 = x15446 z15447 = x15447 z15448 = x15448 z15449 = x15449 z15450 = x15450 z15451 = x15451 z15452 = x15452 z15453 = x15453 z15454 = x15454 z15455 = x15455 z15456 = x15456 z15457 = x15457 z15458 = x15458 z15459 = x15459 z15460 = x15460 z15461 = x15461 z15462 = x15462 z15463 = x15463 z15464 = x15464 z15465 = x15465 z15466 = x15466 z15467 = x15467 z15468 = x15468 z15469 = x15469 z15470 = x15470 z15471 = x15471 z15472 = x15472 z15473 = x15473 z15474 = x15474 z15475 = x15475 z15476 = x15476 z15477 = x15477 z15478 = x15478 z15479 = x15479 z15480 = x15480 z15481 = x15481 z15482 = x15482 z15483 = x15483 z15484 = x15484 z15485 = x15485 z15486 = x15486 z15487 = x15487 z15488 = x15488 z15489 = x15489 z15490 = x15490 z15491 = x15491 z15492 = x15492 z15493 = x15493 z15494 = x15494 z15495 = x15495 z15496 = x15496 z15497 = x15497 z15498 = x15498 z15499 = x15499 z15500 = x15500 z15501 = x15501 z15502 = x15502 z15503 = x15503 z15504 = x15504 z15505 = x15505 z15506 = x15506 z15507 = x15507 z15508 = x15508 z15509 = x15509 z15510 = x15510 z15511 = x15511 z15512 = x15512 z15513 = x15513 z15514 = x15514 z15515 = x15515 z15516 = x15516 z15517 = x15517 z15518 = x15518 z15519 = x15519 z15520 = x15520 z15521 = x15521 z15522 = x15522 z15523 = x15523 z15524 = x15524 z15525 = x15525 z15526 = x15526 z15527 = x15527 z15528 = x15528 z15529 = x15529 z15530 = x15530 z15531 = x15531 z15532 = x15532 z15533 = x15533 z15534 = x15534 z15535 = x15535 z15536 = x15536 z15537 = x15537 z15538 = x15538 z15539 = x15539 z15540 = x15540 z15541 = x15541 z15542 = x15542 z15543 = x15543 z15544 = x15544 z15545 = x15545 z15546 = x15546 z15547 = x15547 z15548 = x15548 z15549 = x15549 z15550 = x15550 z15551 = x15551 z15552 = x15552 z15553 = x15553 z15554 = x15554 z15555 = x15555 z15556 = x15556 z15557 = x15557 z15558 = x15558 z15559 = x15559 z15560 = x15560 z15561 = x15561 z15562 = x15562 z15563 = x15563 z15564 = x15564 z15565 = x15565 z15566 = x15566 z15567 = x15567 z15568 = x15568 z15569 = x15569 z15570 = x15570 z15571 = x15571 z15572 = x15572 z15573 = x15573 z15574 = x15574 z15575 = x15575 z15576 = x15576 z15577 = x15577 z15578 = x15578 z15579 = x15579 z15580 = x15580 z15581 = x15581 z15582 = x15582 z15583 = x15583 z15584 = x15584 z15585 = x15585 z15586 = x15586 z15587 = x15587 z15588 = x15588 z15589 = x15589 z15590 = x15590 z15591 = x15591 z15592 = x15592 z15593 = x15593 z15594 = x15594 z15595 = x15595 z15596 = x15596 z15597 = x15597 z15598 = x15598 z15599 = x15599 z15600 = x15600 z15601 = x15601 z15602 = x15602 z15603 = x15603 z15604 = x15604 z15605 = x15605 z15606 = x15606 z15607 = x15607 z15608 = x15608 z15609 = x15609 z15610 = x15610 z15611 = x15611 z15612 = x15612 z15613 = x15613 z15614 = x15614 z15615 = x15615 z15616 = x15616 z15617 = x15617 z15618 = x15618 z15619 = x15619 z15620 = x15620 z15621 = x15621 z15622 = x15622 z15623 = x15623 z15624 = x15624 z15625 = x15625 z15626 = x15626 z15627 = x15627 z15628 = x15628 z15629 = x15629 z15630 = x15630 z15631 = x15631 z15632 = x15632 z15633 = x15633 z15634 = x15634 z15635 = x15635 z15636 = x15636 z15637 = x15637 z15638 = x15638 z15639 = x15639 z15640 = x15640 z15641 = x15641 z15642 = x15642 z15643 = x15643 z15644 = x15644 z15645 = x15645 z15646 = x15646 z15647 = x15647 z15648 = x15648 z15649 = x15649 z15650 = x15650 z15651 = x15651 z15652 = x15652 z15653 = x15653 z15654 = x15654 z15655 = x15655 z15656 = x15656 z15657 = x15657 z15658 = x15658 z15659 = x15659 z15660 = x15660 z15661 = x15661 z15662 = x15662 z15663 = x15663 z15664 = x15664 z15665 = x15665 z15666 = x15666 z15667 = x15667 z15668 = x15668 z15669 = x15669 z15670 = x15670 z15671 = x15671 z15672 = x15672 z15673 = x15673 z15674 = x15674 z15675 = x15675 z15676 = x15676 z15677 = x15677 z15678 = x15678 z15679 = x15679 z15680 = x15680 z15681 = x15681 z15682 = x15682 z15683 = x15683 z15684 = x15684 z15685 = x15685 z15686 = x15686 z15687 = x15687 z15688 = x15688 z15689 = x15689 z15690 = x15690 z15691 = x15691 z15692 = x15692 z15693 = x15693 z15694 = x15694 z15695 = x15695 z15696 = x15696 z15697 = x15697 z15698 = x15698 z15699 = x15699 z15700 = x15700 z15701 = x15701 z15702 = x15702 z15703 = x15703 z15704 = x15704 z15705 = x15705 z15706 = x15706 z15707 = x15707 z15708 = x15708 z15709 = x15709 z15710 = x15710 z15711 = x15711 z15712 = x15712 z15713 = x15713 z15714 = x15714 z15715 = x15715 z15716 = x15716 z15717 = x15717 z15718 = x15718 z15719 = x15719 z15720 = x15720 z15721 = x15721 z15722 = x15722 z15723 = x15723 z15724 = x15724 z15725 = x15725 z15726 = x15726 z15727 = x15727 z15728 = x15728 z15729 = x15729 z15730 = x15730 z15731 = x15731 z15732 = x15732 z15733 = x15733 z15734 = x15734 z15735 = x15735 z15736 = x15736 z15737 = x15737 z15738 = x15738 z15739 = x15739 z15740 = x15740 z15741 = x15741 z15742 = x15742 z15743 = x15743 z15744 = x15744 z15745 = x15745 z15746 = x15746 z15747 = x15747 z15748 = x15748 z15749 = x15749 z15750 = x15750 z15751 = x15751 z15752 = x15752 z15753 = x15753 z15754 = x15754 z15755 = x15755 z15756 = x15756 z15757 = x15757 z15758 = x15758 z15759 = x15759 z15760 = x15760 z15761 = x15761 z15762 = x15762 z15763 = x15763 z15764 = x15764 z15765 = x15765 z15766 = x15766 z15767 = x15767 z15768 = x15768 z15769 = x15769 z15770 = x15770 z15771 = x15771 z15772 = x15772 z15773 = x15773 z15774 = x15774 z15775 = x15775 z15776 = x15776 z15777 = x15777 z15778 = x15778 z15779 = x15779 z15780 = x15780 z15781 = x15781 z15782 = x15782 z15783 = x15783 z15784 = x15784 z15785 = x15785 z15786 = x15786 z15787 = x15787 z15788 = x15788 z15789 = x15789 z15790 = x15790 z15791 = x15791 z15792 = x15792 z15793 = x15793 z15794 = x15794 z15795 = x15795 z15796 = x15796 z15797 = x15797 z15798 = x15798 z15799 = x15799 z15800 = x15800 z15801 = x15801 z15802 = x15802 z15803 = x15803 z15804 = x15804 z15805 = x15805 z15806 = x15806 z15807 = x15807 z15808 = x15808 z15809 = x15809 z15810 = x15810 z15811 = x15811 z15812 = x15812 z15813 = x15813 z15814 = x15814 z15815 = x15815 z15816 = x15816 z15817 = x15817 z15818 = x15818 z15819 = x15819 z15820 = x15820 z15821 = x15821 z15822 = x15822 z15823 = x15823 z15824 = x15824 z15825 = x15825 z15826 = x15826 z15827 = x15827 z15828 = x15828 z15829 = x15829 z15830 = x15830 z15831 = x15831 z15832 = x15832 z15833 = x15833 z15834 = x15834 z15835 = x15835 z15836 = x15836 z15837 = x15837 z15838 = x15838 z15839 = x15839 z15840 = x15840 z15841 = x15841 z15842 = x15842 z15843 = x15843 z15844 = x15844 z15845 = x15845 z15846 = x15846 z15847 = x15847 z15848 = x15848 z15849 = x15849 z15850 = x15850 z15851 = x15851 z15852 = x15852 z15853 = x15853 z15854 = x15854 z15855 = x15855 z15856 = x15856 z15857 = x15857 z15858 = x15858 z15859 = x15859 z15860 = x15860 z15861 = x15861 z15862 = x15862 z15863 = x15863 z15864 = x15864 z15865 = x15865 z15866 = x15866 z15867 = x15867 z15868 = x15868 z15869 = x15869 z15870 = x15870 z15871 = x15871 z15872 = x15872 z15873 = x15873 z15874 = x15874 z15875 = x15875 z15876 = x15876 z15877 = x15877 z15878 = x15878 z15879 = x15879 z15880 = x15880 z15881 = x15881 z15882 = x15882 z15883 = x15883 z15884 = x15884 z15885 = x15885 z15886 = x15886 z15887 = x15887 z15888 = x15888 z15889 = x15889 z15890 = x15890 z15891 = x15891 z15892 = x15892 z15893 = x15893 z15894 = x15894 z15895 = x15895 z15896 = x15896 z15897 = x15897 z15898 = x15898 z15899 = x15899 z15900 = x15900 z15901 = x15901 z15902 = x15902 z15903 = x15903 z15904 = x15904 z15905 = x15905 z15906 = x15906 z15907 = x15907 z15908 = x15908 z15909 = x15909 z15910 = x15910 z15911 = x15911 z15912 = x15912 z15913 = x15913 z15914 = x15914 z15915 = x15915 z15916 = x15916 z15917 = x15917 z15918 = x15918 z15919 = x15919 z15920 = x15920 z15921 = x15921 z15922 = x15922 z15923 = x15923 z15924 = x15924 z15925 = x15925 z15926 = x15926 z15927 = x15927 z15928 = x15928 z15929 = x15929 z15930 = x15930 z15931 = x15931 z15932 = x15932 z15933 = x15933 z15934 = x15934 z15935 = x15935 z15936 = x15936 z15937 = x15937 z15938 = x15938 z15939 = x15939 z15940 = x15940 z15941 = x15941 z15942 = x15942 z15943 = x15943 z15944 = x15944 z15945 = x15945 z15946 = x15946 z15947 = x15947 z15948 = x15948 z15949 = x15949 z15950 = x15950 z15951 = x15951 z15952 = x15952 z15953 = x15953 z15954 = x15954 z15955 = x15955 z15956 = x15956 z15957 = x15957 z15958 = x15958 z15959 = x15959 z15960 = x15960 z15961 = x15961 z15962 = x15962 z15963 = x15963 z15964 = x15964 z15965 = x15965 z15966 = x15966 z15967 = x15967 z15968 = x15968 z15969 = x15969 z15970 = x15970 z15971 = x15971 z15972 = x15972 z15973 = x15973 z15974 = x15974 z15975 = x15975 z15976 = x15976 z15977 = x15977 z15978 = x15978 z15979 = x15979 z15980 = x15980 z15981 = x15981 z15982 = x15982 z15983 = x15983 z15984 = x15984 z15985 = x15985 z15986 = x15986 z15987 = x15987 z15988 = x15988 z15989 = x15989 z15990 = x15990 z15991 = x15991 z15992 = x15992 z15993 = x15993 z15994 = x15994 z15995 = x15995 z15996 = x15996 z15997 = x15997 z15998 = x15998 z15999 = x15999 z16000 = x16000 z16001 = x16001 z16002 = x16002 z16003 = x16003 z16004 = x16004 z16005 = x16005 z16006 = x16006 z16007 = x16007 z16008 = x16008 z16009 = x16009 z16010 = x16010 z16011 = x16011 z16012 = x16012 z16013 = x16013 z16014 = x16014 z16015 = x16015 z16016 = x16016 z16017 = x16017 z16018 = x16018 z16019 = x16019 z16020 = x16020 z16021 = x16021 z16022 = x16022 z16023 = x16023 z16024 = x16024 z16025 = x16025 z16026 = x16026 z16027 = x16027 z16028 = x16028 z16029 = x16029 z16030 = x16030 z16031 = x16031 z16032 = x16032 z16033 = x16033 z16034 = x16034 z16035 = x16035 z16036 = x16036 z16037 = x16037 z16038 = x16038 z16039 = x16039 z16040 = x16040 z16041 = x16041 z16042 = x16042 z16043 = x16043 z16044 = x16044 z16045 = x16045 z16046 = x16046 z16047 = x16047 z16048 = x16048 z16049 = x16049 z16050 = x16050 z16051 = x16051 z16052 = x16052 z16053 = x16053 z16054 = x16054 z16055 = x16055 z16056 = x16056 z16057 = x16057 z16058 = x16058 z16059 = x16059 z16060 = x16060 z16061 = x16061 z16062 = x16062 z16063 = x16063 z16064 = x16064 z16065 = x16065 z16066 = x16066 z16067 = x16067 z16068 = x16068 z16069 = x16069 z16070 = x16070 z16071 = x16071 z16072 = x16072 z16073 = x16073 z16074 = x16074 z16075 = x16075 z16076 = x16076 z16077 = x16077 z16078 = x16078 z16079 = x16079 z16080 = x16080 z16081 = x16081 z16082 = x16082 z16083 = x16083 z16084 = x16084 z16085 = x16085 z16086 = x16086 z16087 = x16087 z16088 = x16088 z16089 = x16089 z16090 = x16090 z16091 = x16091 z16092 = x16092 z16093 = x16093 z16094 = x16094 z16095 = x16095 z16096 = x16096 z16097 = x16097 z16098 = x16098 z16099 = x16099 z16100 = x16100 z16101 = x16101 z16102 = x16102 z16103 = x16103 z16104 = x16104 z16105 = x16105 z16106 = x16106 z16107 = x16107 z16108 = x16108 z16109 = x16109 z16110 = x16110 z16111 = x16111 z16112 = x16112 z16113 = x16113 z16114 = x16114 z16115 = x16115 z16116 = x16116 z16117 = x16117 z16118 = x16118 z16119 = x16119 z16120 = x16120 z16121 = x16121 z16122 = x16122 z16123 = x16123 z16124 = x16124 z16125 = x16125 z16126 = x16126 z16127 = x16127 z16128 = x16128 z16129 = x16129 z16130 = x16130 z16131 = x16131 z16132 = x16132 z16133 = x16133 z16134 = x16134 z16135 = x16135 z16136 = x16136 z16137 = x16137 z16138 = x16138 z16139 = x16139 z16140 = x16140 z16141 = x16141 z16142 = x16142 z16143 = x16143 z16144 = x16144 z16145 = x16145 z16146 = x16146 z16147 = x16147 z16148 = x16148 z16149 = x16149 z16150 = x16150 z16151 = x16151 z16152 = x16152 z16153 = x16153 z16154 = x16154 z16155 = x16155 z16156 = x16156 z16157 = x16157 z16158 = x16158 z16159 = x16159 z16160 = x16160 z16161 = x16161 z16162 = x16162 z16163 = x16163 z16164 = x16164 z16165 = x16165 z16166 = x16166 z16167 = x16167 z16168 = x16168 z16169 = x16169 z16170 = x16170 z16171 = x16171 z16172 = x16172 z16173 = x16173 z16174 = x16174 z16175 = x16175 z16176 = x16176 z16177 = x16177 z16178 = x16178 z16179 = x16179 z16180 = x16180 z16181 = x16181 z16182 = x16182 z16183 = x16183 z16184 = x16184 z16185 = x16185 z16186 = x16186 z16187 = x16187 z16188 = x16188 z16189 = x16189 z16190 = x16190 z16191 = x16191 z16192 = x16192 z16193 = x16193 z16194 = x16194 z16195 = x16195 z16196 = x16196 z16197 = x16197 z16198 = x16198 z16199 = x16199 z16200 = x16200 z16201 = x16201 z16202 = x16202 z16203 = x16203 z16204 = x16204 z16205 = x16205 z16206 = x16206 z16207 = x16207 z16208 = x16208 z16209 = x16209 z16210 = x16210 z16211 = x16211 z16212 = x16212 z16213 = x16213 z16214 = x16214 z16215 = x16215 z16216 = x16216 z16217 = x16217 z16218 = x16218 z16219 = x16219 z16220 = x16220 z16221 = x16221 z16222 = x16222 z16223 = x16223 z16224 = x16224 z16225 = x16225 z16226 = x16226 z16227 = x16227 z16228 = x16228 z16229 = x16229 z16230 = x16230 z16231 = x16231 z16232 = x16232 z16233 = x16233 z16234 = x16234 z16235 = x16235 z16236 = x16236 z16237 = x16237 z16238 = x16238 z16239 = x16239 z16240 = x16240 z16241 = x16241 z16242 = x16242 z16243 = x16243 z16244 = x16244 z16245 = x16245 z16246 = x16246 z16247 = x16247 z16248 = x16248 z16249 = x16249 z16250 = x16250 z16251 = x16251 z16252 = x16252 z16253 = x16253 z16254 = x16254 z16255 = x16255 z16256 = x16256 z16257 = x16257 z16258 = x16258 z16259 = x16259 z16260 = x16260 z16261 = x16261 z16262 = x16262 z16263 = x16263 z16264 = x16264 z16265 = x16265 z16266 = x16266 z16267 = x16267 z16268 = x16268 z16269 = x16269 z16270 = x16270 z16271 = x16271 z16272 = x16272 z16273 = x16273 z16274 = x16274 z16275 = x16275 z16276 = x16276 z16277 = x16277 z16278 = x16278 z16279 = x16279 z16280 = x16280 z16281 = x16281 z16282 = x16282 z16283 = x16283 z16284 = x16284 z16285 = x16285 z16286 = x16286 z16287 = x16287 z16288 = x16288 z16289 = x16289 z16290 = x16290 z16291 = x16291 z16292 = x16292 z16293 = x16293 z16294 = x16294 z16295 = x16295 z16296 = x16296 z16297 = x16297 z16298 = x16298 z16299 = x16299 z16300 = x16300 z16301 = x16301 z16302 = x16302 z16303 = x16303 z16304 = x16304 z16305 = x16305 z16306 = x16306 z16307 = x16307 z16308 = x16308 z16309 = x16309 z16310 = x16310 z16311 = x16311 z16312 = x16312 z16313 = x16313 z16314 = x16314 z16315 = x16315 z16316 = x16316 z16317 = x16317 z16318 = x16318 z16319 = x16319 z16320 = x16320 z16321 = x16321 z16322 = x16322 z16323 = x16323 z16324 = x16324 z16325 = x16325 z16326 = x16326 z16327 = x16327 z16328 = x16328 z16329 = x16329 z16330 = x16330 z16331 = x16331 z16332 = x16332 z16333 = x16333 z16334 = x16334 z16335 = x16335 z16336 = x16336 z16337 = x16337 z16338 = x16338 z16339 = x16339 z16340 = x16340 z16341 = x16341 z16342 = x16342 z16343 = x16343 z16344 = x16344 z16345 = x16345 z16346 = x16346 z16347 = x16347 z16348 = x16348 z16349 = x16349 z16350 = x16350 z16351 = x16351 z16352 = x16352 z16353 = x16353 z16354 = x16354 z16355 = x16355 z16356 = x16356 z16357 = x16357 z16358 = x16358 z16359 = x16359 z16360 = x16360 z16361 = x16361 z16362 = x16362 z16363 = x16363 z16364 = x16364 z16365 = x16365 z16366 = x16366 z16367 = x16367 z16368 = x16368 z16369 = x16369 z16370 = x16370 z16371 = x16371 z16372 = x16372 z16373 = x16373 z16374 = x16374 z16375 = x16375 z16376 = x16376 z16377 = x16377 z16378 = x16378 z16379 = x16379 z16380 = x16380 z16381 = x16381 z16382 = x16382 z16383 = x16383 z16384 = x16384 z16385 = x16385 z16386 = x16386 z16387 = x16387 z16388 = x16388 z16389 = x16389 z16390 = x16390 z16391 = x16391 z16392 = x16392 z16393 = x16393 z16394 = x16394 z16395 = x16395 z16396 = x16396 z16397 = x16397 z16398 = x16398 z16399 = x16399 z16400 = x16400 z16401 = x16401 z16402 = x16402 z16403 = x16403 z16404 = x16404 z16405 = x16405 z16406 = x16406 z16407 = x16407 z16408 = x16408 z16409 = x16409 z16410 = x16410 z16411 = x16411 z16412 = x16412 z16413 = x16413 z16414 = x16414 z16415 = x16415 z16416 = x16416 z16417 = x16417 z16418 = x16418 z16419 = x16419 z16420 = x16420 z16421 = x16421 z16422 = x16422 z16423 = x16423 z16424 = x16424 z16425 = x16425 z16426 = x16426 z16427 = x16427 z16428 = x16428 z16429 = x16429 z16430 = x16430 z16431 = x16431 z16432 = x16432 z16433 = x16433 z16434 = x16434 z16435 = x16435 z16436 = x16436 z16437 = x16437 z16438 = x16438 z16439 = x16439 z16440 = x16440 z16441 = x16441 z16442 = x16442 z16443 = x16443 z16444 = x16444 z16445 = x16445 z16446 = x16446 z16447 = x16447 z16448 = x16448 z16449 = x16449 z16450 = x16450 z16451 = x16451 z16452 = x16452 z16453 = x16453 z16454 = x16454 z16455 = x16455 z16456 = x16456 z16457 = x16457 z16458 = x16458 z16459 = x16459 z16460 = x16460 z16461 = x16461 z16462 = x16462 z16463 = x16463 z16464 = x16464 z16465 = x16465 z16466 = x16466 z16467 = x16467 z16468 = x16468 z16469 = x16469 z16470 = x16470 z16471 = x16471 z16472 = x16472 z16473 = x16473 z16474 = x16474 z16475 = x16475 z16476 = x16476 z16477 = x16477 z16478 = x16478 z16479 = x16479 z16480 = x16480 } -- diff -- @@ -11,11 +11,16491 @@ package main -var z [1 << 17]byte +// seq 1 16480 | sed 's/.*/var z& [1 << 17]byte/' +var z1 [1 << 17]byte +var z2 [1 << 17]byte +var z3 [1 << 17]byte +var z4 [1 << 17]byte +var z5 [1 << 17]byte +var z6 [1 << 17]byte +var z7 [1 << 17]byte +var z8 [1 << 17]byte +var z9 [1 << 17]byte +var z10 [1 << 17]byte +var z11 [1 << 17]byte +var z12 [1 << 17]byte +var z13 [1 << 17]byte +var z14 [1 << 17]byte +var z15 [1 << 17]byte +var z16 [1 << 17]byte +var z17 [1 << 17]byte +var z18 [1 << 17]byte +var z19 [1 << 17]byte +var z20 [1 << 17]byte +var z21 [1 << 17]byte +var z22 [1 << 17]byte +var z23 [1 << 17]byte +var z24 [1 << 17]byte +var z25 [1 << 17]byte +var z26 [1 << 17]byte +var z27 [1 << 17]byte +var z28 [1 << 17]byte +var z29 [1 << 17]byte +var z30 [1 << 17]byte +var z31 [1 << 17]byte +var z32 [1 << 17]byte +var z33 [1 << 17]byte +var z34 [1 << 17]byte +var z35 [1 << 17]byte +var z36 [1 << 17]byte +var z37 [1 << 17]byte +var z38 [1 << 17]byte +var z39 [1 << 17]byte +var z40 [1 << 17]byte +var z41 [1 << 17]byte +var z42 [1 << 17]byte +var z43 [1 << 17]byte +var z44 [1 << 17]byte +var z45 [1 << 17]byte +var z46 [1 << 17]byte +var z47 [1 << 17]byte +var z48 [1 << 17]byte +var z49 [1 << 17]byte +var z50 [1 << 17]byte +var z51 [1 << 17]byte +var z52 [1 << 17]byte +var z53 [1 << 17]byte +var z54 [1 << 17]byte +var z55 [1 << 17]byte +var z56 [1 << 17]byte +var z57 [1 << 17]byte +var z58 [1 << 17]byte +var z59 [1 << 17]byte +var z60 [1 << 17]byte +var z61 [1 << 17]byte +var z62 [1 << 17]byte +var z63 [1 << 17]byte +var z64 [1 << 17]byte +var z65 [1 << 17]byte +var z66 [1 << 17]byte +var z67 [1 << 17]byte +var z68 [1 << 17]byte +var z69 [1 << 17]byte +var z70 [1 << 17]byte +var z71 [1 << 17]byte +var z72 [1 << 17]byte +var z73 [1 << 17]byte +var z74 [1 << 17]byte +var z75 [1 << 17]byte +var z76 [1 << 17]byte +var z77 [1 << 17]byte +var z78 [1 << 17]byte +var z79 [1 << 17]byte +var z80 [1 << 17]byte +var z81 [1 << 17]byte +var z82 [1 << 17]byte +var z83 [1 << 17]byte +var z84 [1 << 17]byte +var z85 [1 << 17]byte +var z86 [1 << 17]byte +var z87 [1 << 17]byte +var z88 [1 << 17]byte +var z89 [1 << 17]byte +var z90 [1 << 17]byte +var z91 [1 << 17]byte +var z92 [1 << 17]byte +var z93 [1 << 17]byte +var z94 [1 << 17]byte +var z95 [1 << 17]byte +var z96 [1 << 17]byte +var z97 [1 << 17]byte +var z98 [1 << 17]byte +var z99 [1 << 17]byte +var z100 [1 << 17]byte +var z101 [1 << 17]byte +var z102 [1 << 17]byte +var z103 [1 << 17]byte +var z104 [1 << 17]byte +var z105 [1 << 17]byte +var z106 [1 << 17]byte +var z107 [1 << 17]byte +var z108 [1 << 17]byte +var z109 [1 << 17]byte +var z110 [1 << 17]byte +var z111 [1 << 17]byte +var z112 [1 << 17]byte +var z113 [1 << 17]byte +var z114 [1 << 17]byte +var z115 [1 << 17]byte +var z116 [1 << 17]byte +var z117 [1 << 17]byte +var z118 [1 << 17]byte +var z119 [1 << 17]byte +var z120 [1 << 17]byte +var z121 [1 << 17]byte +var z122 [1 << 17]byte +var z123 [1 << 17]byte +var z124 [1 << 17]byte +var z125 [1 << 17]byte +var z126 [1 << 17]byte +var z127 [1 << 17]byte +var z128 [1 << 17]byte +var z129 [1 << 17]byte +var z130 [1 << 17]byte +var z131 [1 << 17]byte +var z132 [1 << 17]byte +var z133 [1 << 17]byte +var z134 [1 << 17]byte +var z135 [1 << 17]byte +var z136 [1 << 17]byte +var z137 [1 << 17]byte +var z138 [1 << 17]byte +var z139 [1 << 17]byte +var z140 [1 << 17]byte +var z141 [1 << 17]byte +var z142 [1 << 17]byte +var z143 [1 << 17]byte +var z144 [1 << 17]byte +var z145 [1 << 17]byte +var z146 [1 << 17]byte +var z147 [1 << 17]byte +var z148 [1 << 17]byte +var z149 [1 << 17]byte +var z150 [1 << 17]byte +var z151 [1 << 17]byte +var z152 [1 << 17]byte +var z153 [1 << 17]byte +var z154 [1 << 17]byte +var z155 [1 << 17]byte +var z156 [1 << 17]byte +var z157 [1 << 17]byte +var z158 [1 << 17]byte +var z159 [1 << 17]byte +var z160 [1 << 17]byte +var z161 [1 << 17]byte +var z162 [1 << 17]byte +var z163 [1 << 17]byte +var z164 [1 << 17]byte +var z165 [1 << 17]byte +var z166 [1 << 17]byte +var z167 [1 << 17]byte +var z168 [1 << 17]byte +var z169 [1 << 17]byte +var z170 [1 << 17]byte +var z171 [1 << 17]byte +var z172 [1 << 17]byte +var z173 [1 << 17]byte +var z174 [1 << 17]byte +var z175 [1 << 17]byte +var z176 [1 << 17]byte +var z177 [1 << 17]byte +var z178 [1 << 17]byte +var z179 [1 << 17]byte +var z180 [1 << 17]byte +var z181 [1 << 17]byte +var z182 [1 << 17]byte +var z183 [1 << 17]byte +var z184 [1 << 17]byte +var z185 [1 << 17]byte +var z186 [1 << 17]byte +var z187 [1 << 17]byte +var z188 [1 << 17]byte +var z189 [1 << 17]byte +var z190 [1 << 17]byte +var z191 [1 << 17]byte +var z192 [1 << 17]byte +var z193 [1 << 17]byte +var z194 [1 << 17]byte +var z195 [1 << 17]byte +var z196 [1 << 17]byte +var z197 [1 << 17]byte +var z198 [1 << 17]byte +var z199 [1 << 17]byte +var z200 [1 << 17]byte +var z201 [1 << 17]byte +var z202 [1 << 17]byte +var z203 [1 << 17]byte +var z204 [1 << 17]byte +var z205 [1 << 17]byte +var z206 [1 << 17]byte +var z207 [1 << 17]byte +var z208 [1 << 17]byte +var z209 [1 << 17]byte +var z210 [1 << 17]byte +var z211 [1 << 17]byte +var z212 [1 << 17]byte +var z213 [1 << 17]byte +var z214 [1 << 17]byte +var z215 [1 << 17]byte +var z216 [1 << 17]byte +var z217 [1 << 17]byte +var z218 [1 << 17]byte +var z219 [1 << 17]byte +var z220 [1 << 17]byte +var z221 [1 << 17]byte +var z222 [1 << 17]byte +var z223 [1 << 17]byte +var z224 [1 << 17]byte +var z225 [1 << 17]byte +var z226 [1 << 17]byte +var z227 [1 << 17]byte +var z228 [1 << 17]byte +var z229 [1 << 17]byte +var z230 [1 << 17]byte +var z231 [1 << 17]byte +var z232 [1 << 17]byte +var z233 [1 << 17]byte +var z234 [1 << 17]byte +var z235 [1 << 17]byte +var z236 [1 << 17]byte +var z237 [1 << 17]byte +var z238 [1 << 17]byte +var z239 [1 << 17]byte +var z240 [1 << 17]byte +var z241 [1 << 17]byte +var z242 [1 << 17]byte +var z243 [1 << 17]byte +var z244 [1 << 17]byte +var z245 [1 << 17]byte +var z246 [1 << 17]byte +var z247 [1 << 17]byte +var z248 [1 << 17]byte +var z249 [1 << 17]byte +var z250 [1 << 17]byte +var z251 [1 << 17]byte +var z252 [1 << 17]byte +var z253 [1 << 17]byte +var z254 [1 << 17]byte +var z255 [1 << 17]byte +var z256 [1 << 17]byte +var z257 [1 << 17]byte +var z258 [1 << 17]byte +var z259 [1 << 17]byte +var z260 [1 << 17]byte +var z261 [1 << 17]byte +var z262 [1 << 17]byte +var z263 [1 << 17]byte +var z264 [1 << 17]byte +var z265 [1 << 17]byte +var z266 [1 << 17]byte +var z267 [1 << 17]byte +var z268 [1 << 17]byte +var z269 [1 << 17]byte +var z270 [1 << 17]byte +var z271 [1 << 17]byte +var z272 [1 << 17]byte +var z273 [1 << 17]byte +var z274 [1 << 17]byte +var z275 [1 << 17]byte +var z276 [1 << 17]byte +var z277 [1 << 17]byte +var z278 [1 << 17]byte +var z279 [1 << 17]byte +var z280 [1 << 17]byte +var z281 [1 << 17]byte +var z282 [1 << 17]byte +var z283 [1 << 17]byte +var z284 [1 << 17]byte +var z285 [1 << 17]byte +var z286 [1 << 17]byte +var z287 [1 << 17]byte +var z288 [1 << 17]byte +var z289 [1 << 17]byte +var z290 [1 << 17]byte +var z291 [1 << 17]byte +var z292 [1 << 17]byte +var z293 [1 << 17]byte +var z294 [1 << 17]byte +var z295 [1 << 17]byte +var z296 [1 << 17]byte +var z297 [1 << 17]byte +var z298 [1 << 17]byte +var z299 [1 << 17]byte +var z300 [1 << 17]byte +var z301 [1 << 17]byte +var z302 [1 << 17]byte +var z303 [1 << 17]byte +var z304 [1 << 17]byte +var z305 [1 << 17]byte +var z306 [1 << 17]byte +var z307 [1 << 17]byte +var z308 [1 << 17]byte +var z309 [1 << 17]byte +var z310 [1 << 17]byte +var z311 [1 << 17]byte +var z312 [1 << 17]byte +var z313 [1 << 17]byte +var z314 [1 << 17]byte +var z315 [1 << 17]byte +var z316 [1 << 17]byte +var z317 [1 << 17]byte +var z318 [1 << 17]byte +var z319 [1 << 17]byte +var z320 [1 << 17]byte +var z321 [1 << 17]byte +var z322 [1 << 17]byte +var z323 [1 << 17]byte +var z324 [1 << 17]byte +var z325 [1 << 17]byte +var z326 [1 << 17]byte +var z327 [1 << 17]byte +var z328 [1 << 17]byte +var z329 [1 << 17]byte +var z330 [1 << 17]byte +var z331 [1 << 17]byte +var z332 [1 << 17]byte +var z333 [1 << 17]byte +var z334 [1 << 17]byte +var z335 [1 << 17]byte +var z336 [1 << 17]byte +var z337 [1 << 17]byte +var z338 [1 << 17]byte +var z339 [1 << 17]byte +var z340 [1 << 17]byte +var z341 [1 << 17]byte +var z342 [1 << 17]byte +var z343 [1 << 17]byte +var z344 [1 << 17]byte +var z345 [1 << 17]byte +var z346 [1 << 17]byte +var z347 [1 << 17]byte +var z348 [1 << 17]byte +var z349 [1 << 17]byte +var z350 [1 << 17]byte +var z351 [1 << 17]byte +var z352 [1 << 17]byte +var z353 [1 << 17]byte +var z354 [1 << 17]byte +var z355 [1 << 17]byte +var z356 [1 << 17]byte +var z357 [1 << 17]byte +var z358 [1 << 17]byte +var z359 [1 << 17]byte +var z360 [1 << 17]byte +var z361 [1 << 17]byte +var z362 [1 << 17]byte +var z363 [1 << 17]byte +var z364 [1 << 17]byte +var z365 [1 << 17]byte +var z366 [1 << 17]byte +var z367 [1 << 17]byte +var z368 [1 << 17]byte +var z369 [1 << 17]byte +var z370 [1 << 17]byte +var z371 [1 << 17]byte +var z372 [1 << 17]byte +var z373 [1 << 17]byte +var z374 [1 << 17]byte +var z375 [1 << 17]byte +var z376 [1 << 17]byte +var z377 [1 << 17]byte +var z378 [1 << 17]byte +var z379 [1 << 17]byte +var z380 [1 << 17]byte +var z381 [1 << 17]byte +var z382 [1 << 17]byte +var z383 [1 << 17]byte +var z384 [1 << 17]byte +var z385 [1 << 17]byte +var z386 [1 << 17]byte +var z387 [1 << 17]byte +var z388 [1 << 17]byte +var z389 [1 << 17]byte +var z390 [1 << 17]byte +var z391 [1 << 17]byte +var z392 [1 << 17]byte +var z393 [1 << 17]byte +var z394 [1 << 17]byte +var z395 [1 << 17]byte +var z396 [1 << 17]byte +var z397 [1 << 17]byte +var z398 [1 << 17]byte +var z399 [1 << 17]byte +var z400 [1 << 17]byte +var z401 [1 << 17]byte +var z402 [1 << 17]byte +var z403 [1 << 17]byte +var z404 [1 << 17]byte +var z405 [1 << 17]byte +var z406 [1 << 17]byte +var z407 [1 << 17]byte +var z408 [1 << 17]byte +var z409 [1 << 17]byte +var z410 [1 << 17]byte +var z411 [1 << 17]byte +var z412 [1 << 17]byte +var z413 [1 << 17]byte +var z414 [1 << 17]byte +var z415 [1 << 17]byte +var z416 [1 << 17]byte +var z417 [1 << 17]byte +var z418 [1 << 17]byte +var z419 [1 << 17]byte +var z420 [1 << 17]byte +var z421 [1 << 17]byte +var z422 [1 << 17]byte +var z423 [1 << 17]byte +var z424 [1 << 17]byte +var z425 [1 << 17]byte +var z426 [1 << 17]byte +var z427 [1 << 17]byte +var z428 [1 << 17]byte +var z429 [1 << 17]byte +var z430 [1 << 17]byte +var z431 [1 << 17]byte +var z432 [1 << 17]byte +var z433 [1 << 17]byte +var z434 [1 << 17]byte +var z435 [1 << 17]byte +var z436 [1 << 17]byte +var z437 [1 << 17]byte +var z438 [1 << 17]byte +var z439 [1 << 17]byte +var z440 [1 << 17]byte +var z441 [1 << 17]byte +var z442 [1 << 17]byte +var z443 [1 << 17]byte +var z444 [1 << 17]byte +var z445 [1 << 17]byte +var z446 [1 << 17]byte +var z447 [1 << 17]byte +var z448 [1 << 17]byte +var z449 [1 << 17]byte +var z450 [1 << 17]byte +var z451 [1 << 17]byte +var z452 [1 << 17]byte +var z453 [1 << 17]byte +var z454 [1 << 17]byte +var z455 [1 << 17]byte +var z456 [1 << 17]byte +var z457 [1 << 17]byte +var z458 [1 << 17]byte +var z459 [1 << 17]byte +var z460 [1 << 17]byte +var z461 [1 << 17]byte +var z462 [1 << 17]byte +var z463 [1 << 17]byte +var z464 [1 << 17]byte +var z465 [1 << 17]byte +var z466 [1 << 17]byte +var z467 [1 << 17]byte +var z468 [1 << 17]byte +var z469 [1 << 17]byte +var z470 [1 << 17]byte +var z471 [1 << 17]byte +var z472 [1 << 17]byte +var z473 [1 << 17]byte +var z474 [1 << 17]byte +var z475 [1 << 17]byte +var z476 [1 << 17]byte +var z477 [1 << 17]byte +var z478 [1 << 17]byte +var z479 [1 << 17]byte +var z480 [1 << 17]byte +var z481 [1 << 17]byte +var z482 [1 << 17]byte +var z483 [1 << 17]byte +var z484 [1 << 17]byte +var z485 [1 << 17]byte +var z486 [1 << 17]byte +var z487 [1 << 17]byte +var z488 [1 << 17]byte +var z489 [1 << 17]byte +var z490 [1 << 17]byte +var z491 [1 << 17]byte +var z492 [1 << 17]byte +var z493 [1 << 17]byte +var z494 [1 << 17]byte +var z495 [1 << 17]byte +var z496 [1 << 17]byte +var z497 [1 << 17]byte +var z498 [1 << 17]byte +var z499 [1 << 17]byte +var z500 [1 << 17]byte +var z501 [1 << 17]byte +var z502 [1 << 17]byte +var z503 [1 << 17]byte +var z504 [1 << 17]byte +var z505 [1 << 17]byte +var z506 [1 << 17]byte +var z507 [1 << 17]byte +var z508 [1 << 17]byte +var z509 [1 << 17]byte +var z510 [1 << 17]byte +var z511 [1 << 17]byte +var z512 [1 << 17]byte +var z513 [1 << 17]byte +var z514 [1 << 17]byte +var z515 [1 << 17]byte +var z516 [1 << 17]byte +var z517 [1 << 17]byte +var z518 [1 << 17]byte +var z519 [1 << 17]byte +var z520 [1 << 17]byte +var z521 [1 << 17]byte +var z522 [1 << 17]byte +var z523 [1 << 17]byte +var z524 [1 << 17]byte +var z525 [1 << 17]byte +var z526 [1 << 17]byte +var z527 [1 << 17]byte +var z528 [1 << 17]byte +var z529 [1 << 17]byte +var z530 [1 << 17]byte +var z531 [1 << 17]byte +var z532 [1 << 17]byte +var z533 [1 << 17]byte +var z534 [1 << 17]byte +var z535 [1 << 17]byte +var z536 [1 << 17]byte +var z537 [1 << 17]byte +var z538 [1 << 17]byte +var z539 [1 << 17]byte +var z540 [1 << 17]byte +var z541 [1 << 17]byte +var z542 [1 << 17]byte +var z543 [1 << 17]byte +var z544 [1 << 17]byte +var z545 [1 << 17]byte +var z546 [1 << 17]byte +var z547 [1 << 17]byte +var z548 [1 << 17]byte +var z549 [1 << 17]byte +var z550 [1 << 17]byte +var z551 [1 << 17]byte +var z552 [1 << 17]byte +var z553 [1 << 17]byte +var z554 [1 << 17]byte +var z555 [1 << 17]byte +var z556 [1 << 17]byte +var z557 [1 << 17]byte +var z558 [1 << 17]byte +var z559 [1 << 17]byte +var z560 [1 << 17]byte +var z561 [1 << 17]byte +var z562 [1 << 17]byte +var z563 [1 << 17]byte +var z564 [1 << 17]byte +var z565 [1 << 17]byte +var z566 [1 << 17]byte +var z567 [1 << 17]byte +var z568 [1 << 17]byte +var z569 [1 << 17]byte +var z570 [1 << 17]byte +var z571 [1 << 17]byte +var z572 [1 << 17]byte +var z573 [1 << 17]byte +var z574 [1 << 17]byte +var z575 [1 << 17]byte +var z576 [1 << 17]byte +var z577 [1 << 17]byte +var z578 [1 << 17]byte +var z579 [1 << 17]byte +var z580 [1 << 17]byte +var z581 [1 << 17]byte +var z582 [1 << 17]byte +var z583 [1 << 17]byte +var z584 [1 << 17]byte +var z585 [1 << 17]byte +var z586 [1 << 17]byte +var z587 [1 << 17]byte +var z588 [1 << 17]byte +var z589 [1 << 17]byte +var z590 [1 << 17]byte +var z591 [1 << 17]byte +var z592 [1 << 17]byte +var z593 [1 << 17]byte +var z594 [1 << 17]byte +var z595 [1 << 17]byte +var z596 [1 << 17]byte +var z597 [1 << 17]byte +var z598 [1 << 17]byte +var z599 [1 << 17]byte +var z600 [1 << 17]byte +var z601 [1 << 17]byte +var z602 [1 << 17]byte +var z603 [1 << 17]byte +var z604 [1 << 17]byte +var z605 [1 << 17]byte +var z606 [1 << 17]byte +var z607 [1 << 17]byte +var z608 [1 << 17]byte +var z609 [1 << 17]byte +var z610 [1 << 17]byte +var z611 [1 << 17]byte +var z612 [1 << 17]byte +var z613 [1 << 17]byte +var z614 [1 << 17]byte +var z615 [1 << 17]byte +var z616 [1 << 17]byte +var z617 [1 << 17]byte +var z618 [1 << 17]byte +var z619 [1 << 17]byte +var z620 [1 << 17]byte +var z621 [1 << 17]byte +var z622 [1 << 17]byte +var z623 [1 << 17]byte +var z624 [1 << 17]byte +var z625 [1 << 17]byte +var z626 [1 << 17]byte +var z627 [1 << 17]byte +var z628 [1 << 17]byte +var z629 [1 << 17]byte +var z630 [1 << 17]byte +var z631 [1 << 17]byte +var z632 [1 << 17]byte +var z633 [1 << 17]byte +var z634 [1 << 17]byte +var z635 [1 << 17]byte +var z636 [1 << 17]byte +var z637 [1 << 17]byte +var z638 [1 << 17]byte +var z639 [1 << 17]byte +var z640 [1 << 17]byte +var z641 [1 << 17]byte +var z642 [1 << 17]byte +var z643 [1 << 17]byte +var z644 [1 << 17]byte +var z645 [1 << 17]byte +var z646 [1 << 17]byte +var z647 [1 << 17]byte +var z648 [1 << 17]byte +var z649 [1 << 17]byte +var z650 [1 << 17]byte +var z651 [1 << 17]byte +var z652 [1 << 17]byte +var z653 [1 << 17]byte +var z654 [1 << 17]byte +var z655 [1 << 17]byte +var z656 [1 << 17]byte +var z657 [1 << 17]byte +var z658 [1 << 17]byte +var z659 [1 << 17]byte +var z660 [1 << 17]byte +var z661 [1 << 17]byte +var z662 [1 << 17]byte +var z663 [1 << 17]byte +var z664 [1 << 17]byte +var z665 [1 << 17]byte +var z666 [1 << 17]byte +var z667 [1 << 17]byte +var z668 [1 << 17]byte +var z669 [1 << 17]byte +var z670 [1 << 17]byte +var z671 [1 << 17]byte +var z672 [1 << 17]byte +var z673 [1 << 17]byte +var z674 [1 << 17]byte +var z675 [1 << 17]byte +var z676 [1 << 17]byte +var z677 [1 << 17]byte +var z678 [1 << 17]byte +var z679 [1 << 17]byte +var z680 [1 << 17]byte +var z681 [1 << 17]byte +var z682 [1 << 17]byte +var z683 [1 << 17]byte +var z684 [1 << 17]byte +var z685 [1 << 17]byte +var z686 [1 << 17]byte +var z687 [1 << 17]byte +var z688 [1 << 17]byte +var z689 [1 << 17]byte +var z690 [1 << 17]byte +var z691 [1 << 17]byte +var z692 [1 << 17]byte +var z693 [1 << 17]byte +var z694 [1 << 17]byte +var z695 [1 << 17]byte +var z696 [1 << 17]byte +var z697 [1 << 17]byte +var z698 [1 << 17]byte +var z699 [1 << 17]byte +var z700 [1 << 17]byte +var z701 [1 << 17]byte +var z702 [1 << 17]byte +var z703 [1 << 17]byte +var z704 [1 << 17]byte +var z705 [1 << 17]byte +var z706 [1 << 17]byte +var z707 [1 << 17]byte +var z708 [1 << 17]byte +var z709 [1 << 17]byte +var z710 [1 << 17]byte +var z711 [1 << 17]byte +var z712 [1 << 17]byte +var z713 [1 << 17]byte +var z714 [1 << 17]byte +var z715 [1 << 17]byte +var z716 [1 << 17]byte +var z717 [1 << 17]byte +var z718 [1 << 17]byte +var z719 [1 << 17]byte +var z720 [1 << 17]byte +var z721 [1 << 17]byte +var z722 [1 << 17]byte +var z723 [1 << 17]byte +var z724 [1 << 17]byte +var z725 [1 << 17]byte +var z726 [1 << 17]byte +var z727 [1 << 17]byte +var z728 [1 << 17]byte +var z729 [1 << 17]byte +var z730 [1 << 17]byte +var z731 [1 << 17]byte +var z732 [1 << 17]byte +var z733 [1 << 17]byte +var z734 [1 << 17]byte +var z735 [1 << 17]byte +var z736 [1 << 17]byte +var z737 [1 << 17]byte +var z738 [1 << 17]byte +var z739 [1 << 17]byte +var z740 [1 << 17]byte +var z741 [1 << 17]byte +var z742 [1 << 17]byte +var z743 [1 << 17]byte +var z744 [1 << 17]byte +var z745 [1 << 17]byte +var z746 [1 << 17]byte +var z747 [1 << 17]byte +var z748 [1 << 17]byte +var z749 [1 << 17]byte +var z750 [1 << 17]byte +var z751 [1 << 17]byte +var z752 [1 << 17]byte +var z753 [1 << 17]byte +var z754 [1 << 17]byte +var z755 [1 << 17]byte +var z756 [1 << 17]byte +var z757 [1 << 17]byte +var z758 [1 << 17]byte +var z759 [1 << 17]byte +var z760 [1 << 17]byte +var z761 [1 << 17]byte +var z762 [1 << 17]byte +var z763 [1 << 17]byte +var z764 [1 << 17]byte +var z765 [1 << 17]byte +var z766 [1 << 17]byte +var z767 [1 << 17]byte +var z768 [1 << 17]byte +var z769 [1 << 17]byte +var z770 [1 << 17]byte +var z771 [1 << 17]byte +var z772 [1 << 17]byte +var z773 [1 << 17]byte +var z774 [1 << 17]byte +var z775 [1 << 17]byte +var z776 [1 << 17]byte +var z777 [1 << 17]byte +var z778 [1 << 17]byte +var z779 [1 << 17]byte +var z780 [1 << 17]byte +var z781 [1 << 17]byte +var z782 [1 << 17]byte +var z783 [1 << 17]byte +var z784 [1 << 17]byte +var z785 [1 << 17]byte +var z786 [1 << 17]byte +var z787 [1 << 17]byte +var z788 [1 << 17]byte +var z789 [1 << 17]byte +var z790 [1 << 17]byte +var z791 [1 << 17]byte +var z792 [1 << 17]byte +var z793 [1 << 17]byte +var z794 [1 << 17]byte +var z795 [1 << 17]byte +var z796 [1 << 17]byte +var z797 [1 << 17]byte +var z798 [1 << 17]byte +var z799 [1 << 17]byte +var z800 [1 << 17]byte +var z801 [1 << 17]byte +var z802 [1 << 17]byte +var z803 [1 << 17]byte +var z804 [1 << 17]byte +var z805 [1 << 17]byte +var z806 [1 << 17]byte +var z807 [1 << 17]byte +var z808 [1 << 17]byte +var z809 [1 << 17]byte +var z810 [1 << 17]byte +var z811 [1 << 17]byte +var z812 [1 << 17]byte +var z813 [1 << 17]byte +var z814 [1 << 17]byte +var z815 [1 << 17]byte +var z816 [1 << 17]byte +var z817 [1 << 17]byte +var z818 [1 << 17]byte +var z819 [1 << 17]byte +var z820 [1 << 17]byte +var z821 [1 << 17]byte +var z822 [1 << 17]byte +var z823 [1 << 17]byte +var z824 [1 << 17]byte +var z825 [1 << 17]byte +var z826 [1 << 17]byte +var z827 [1 << 17]byte +var z828 [1 << 17]byte +var z829 [1 << 17]byte +var z830 [1 << 17]byte +var z831 [1 << 17]byte +var z832 [1 << 17]byte +var z833 [1 << 17]byte +var z834 [1 << 17]byte +var z835 [1 << 17]byte +var z836 [1 << 17]byte +var z837 [1 << 17]byte +var z838 [1 << 17]byte +var z839 [1 << 17]byte +var z840 [1 << 17]byte +var z841 [1 << 17]byte +var z842 [1 << 17]byte +var z843 [1 << 17]byte +var z844 [1 << 17]byte +var z845 [1 << 17]byte +var z846 [1 << 17]byte +var z847 [1 << 17]byte +var z848 [1 << 17]byte +var z849 [1 << 17]byte +var z850 [1 << 17]byte +var z851 [1 << 17]byte +var z852 [1 << 17]byte +var z853 [1 << 17]byte +var z854 [1 << 17]byte +var z855 [1 << 17]byte +var z856 [1 << 17]byte +var z857 [1 << 17]byte +var z858 [1 << 17]byte +var z859 [1 << 17]byte +var z860 [1 << 17]byte +var z861 [1 << 17]byte +var z862 [1 << 17]byte +var z863 [1 << 17]byte +var z864 [1 << 17]byte +var z865 [1 << 17]byte +var z866 [1 << 17]byte +var z867 [1 << 17]byte +var z868 [1 << 17]byte +var z869 [1 << 17]byte +var z870 [1 << 17]byte +var z871 [1 << 17]byte +var z872 [1 << 17]byte +var z873 [1 << 17]byte +var z874 [1 << 17]byte +var z875 [1 << 17]byte +var z876 [1 << 17]byte +var z877 [1 << 17]byte +var z878 [1 << 17]byte +var z879 [1 << 17]byte +var z880 [1 << 17]byte +var z881 [1 << 17]byte +var z882 [1 << 17]byte +var z883 [1 << 17]byte +var z884 [1 << 17]byte +var z885 [1 << 17]byte +var z886 [1 << 17]byte +var z887 [1 << 17]byte +var z888 [1 << 17]byte +var z889 [1 << 17]byte +var z890 [1 << 17]byte +var z891 [1 << 17]byte +var z892 [1 << 17]byte +var z893 [1 << 17]byte +var z894 [1 << 17]byte +var z895 [1 << 17]byte +var z896 [1 << 17]byte +var z897 [1 << 17]byte +var z898 [1 << 17]byte +var z899 [1 << 17]byte +var z900 [1 << 17]byte +var z901 [1 << 17]byte +var z902 [1 << 17]byte +var z903 [1 << 17]byte +var z904 [1 << 17]byte +var z905 [1 << 17]byte +var z906 [1 << 17]byte +var z907 [1 << 17]byte +var z908 [1 << 17]byte +var z909 [1 << 17]byte +var z910 [1 << 17]byte +var z911 [1 << 17]byte +var z912 [1 << 17]byte +var z913 [1 << 17]byte +var z914 [1 << 17]byte +var z915 [1 << 17]byte +var z916 [1 << 17]byte +var z917 [1 << 17]byte +var z918 [1 << 17]byte +var z919 [1 << 17]byte +var z920 [1 << 17]byte +var z921 [1 << 17]byte +var z922 [1 << 17]byte +var z923 [1 << 17]byte +var z924 [1 << 17]byte +var z925 [1 << 17]byte +var z926 [1 << 17]byte +var z927 [1 << 17]byte +var z928 [1 << 17]byte +var z929 [1 << 17]byte +var z930 [1 << 17]byte +var z931 [1 << 17]byte +var z932 [1 << 17]byte +var z933 [1 << 17]byte +var z934 [1 << 17]byte +var z935 [1 << 17]byte +var z936 [1 << 17]byte +var z937 [1 << 17]byte +var z938 [1 << 17]byte +var z939 [1 << 17]byte +var z940 [1 << 17]byte +var z941 [1 << 17]byte +var z942 [1 << 17]byte +var z943 [1 << 17]byte +var z944 [1 << 17]byte +var z945 [1 << 17]byte +var z946 [1 << 17]byte +var z947 [1 << 17]byte +var z948 [1 << 17]byte +var z949 [1 << 17]byte +var z950 [1 << 17]byte +var z951 [1 << 17]byte +var z952 [1 << 17]byte +var z953 [1 << 17]byte +var z954 [1 << 17]byte +var z955 [1 << 17]byte +var z956 [1 << 17]byte +var z957 [1 << 17]byte +var z958 [1 << 17]byte +var z959 [1 << 17]byte +var z960 [1 << 17]byte +var z961 [1 << 17]byte +var z962 [1 << 17]byte +var z963 [1 << 17]byte +var z964 [1 << 17]byte +var z965 [1 << 17]byte +var z966 [1 << 17]byte +var z967 [1 << 17]byte +var z968 [1 << 17]byte +var z969 [1 << 17]byte +var z970 [1 << 17]byte +var z971 [1 << 17]byte +var z972 [1 << 17]byte +var z973 [1 << 17]byte +var z974 [1 << 17]byte +var z975 [1 << 17]byte +var z976 [1 << 17]byte +var z977 [1 << 17]byte +var z978 [1 << 17]byte +var z979 [1 << 17]byte +var z980 [1 << 17]byte +var z981 [1 << 17]byte +var z982 [1 << 17]byte +var z983 [1 << 17]byte +var z984 [1 << 17]byte +var z985 [1 << 17]byte +var z986 [1 << 17]byte +var z987 [1 << 17]byte +var z988 [1 << 17]byte +var z989 [1 << 17]byte +var z990 [1 << 17]byte +var z991 [1 << 17]byte +var z992 [1 << 17]byte +var z993 [1 << 17]byte +var z994 [1 << 17]byte +var z995 [1 << 17]byte +var z996 [1 << 17]byte +var z997 [1 << 17]byte +var z998 [1 << 17]byte +var z999 [1 << 17]byte +var z1000 [1 << 17]byte +var z1001 [1 << 17]byte +var z1002 [1 << 17]byte +var z1003 [1 << 17]byte +var z1004 [1 << 17]byte +var z1005 [1 << 17]byte +var z1006 [1 << 17]byte +var z1007 [1 << 17]byte +var z1008 [1 << 17]byte +var z1009 [1 << 17]byte +var z1010 [1 << 17]byte +var z1011 [1 << 17]byte +var z1012 [1 << 17]byte +var z1013 [1 << 17]byte +var z1014 [1 << 17]byte +var z1015 [1 << 17]byte +var z1016 [1 << 17]byte +var z1017 [1 << 17]byte +var z1018 [1 << 17]byte +var z1019 [1 << 17]byte +var z1020 [1 << 17]byte +var z1021 [1 << 17]byte +var z1022 [1 << 17]byte +var z1023 [1 << 17]byte +var z1024 [1 << 17]byte +var z1025 [1 << 17]byte +var z1026 [1 << 17]byte +var z1027 [1 << 17]byte +var z1028 [1 << 17]byte +var z1029 [1 << 17]byte +var z1030 [1 << 17]byte +var z1031 [1 << 17]byte +var z1032 [1 << 17]byte +var z1033 [1 << 17]byte +var z1034 [1 << 17]byte +var z1035 [1 << 17]byte +var z1036 [1 << 17]byte +var z1037 [1 << 17]byte +var z1038 [1 << 17]byte +var z1039 [1 << 17]byte +var z1040 [1 << 17]byte +var z1041 [1 << 17]byte +var z1042 [1 << 17]byte +var z1043 [1 << 17]byte +var z1044 [1 << 17]byte +var z1045 [1 << 17]byte +var z1046 [1 << 17]byte +var z1047 [1 << 17]byte +var z1048 [1 << 17]byte +var z1049 [1 << 17]byte +var z1050 [1 << 17]byte +var z1051 [1 << 17]byte +var z1052 [1 << 17]byte +var z1053 [1 << 17]byte +var z1054 [1 << 17]byte +var z1055 [1 << 17]byte +var z1056 [1 << 17]byte +var z1057 [1 << 17]byte +var z1058 [1 << 17]byte +var z1059 [1 << 17]byte +var z1060 [1 << 17]byte +var z1061 [1 << 17]byte +var z1062 [1 << 17]byte +var z1063 [1 << 17]byte +var z1064 [1 << 17]byte +var z1065 [1 << 17]byte +var z1066 [1 << 17]byte +var z1067 [1 << 17]byte +var z1068 [1 << 17]byte +var z1069 [1 << 17]byte +var z1070 [1 << 17]byte +var z1071 [1 << 17]byte +var z1072 [1 << 17]byte +var z1073 [1 << 17]byte +var z1074 [1 << 17]byte +var z1075 [1 << 17]byte +var z1076 [1 << 17]byte +var z1077 [1 << 17]byte +var z1078 [1 << 17]byte +var z1079 [1 << 17]byte +var z1080 [1 << 17]byte +var z1081 [1 << 17]byte +var z1082 [1 << 17]byte +var z1083 [1 << 17]byte +var z1084 [1 << 17]byte +var z1085 [1 << 17]byte +var z1086 [1 << 17]byte +var z1087 [1 << 17]byte +var z1088 [1 << 17]byte +var z1089 [1 << 17]byte +var z1090 [1 << 17]byte +var z1091 [1 << 17]byte +var z1092 [1 << 17]byte +var z1093 [1 << 17]byte +var z1094 [1 << 17]byte +var z1095 [1 << 17]byte +var z1096 [1 << 17]byte +var z1097 [1 << 17]byte +var z1098 [1 << 17]byte +var z1099 [1 << 17]byte +var z1100 [1 << 17]byte +var z1101 [1 << 17]byte +var z1102 [1 << 17]byte +var z1103 [1 << 17]byte +var z1104 [1 << 17]byte +var z1105 [1 << 17]byte +var z1106 [1 << 17]byte +var z1107 [1 << 17]byte +var z1108 [1 << 17]byte +var z1109 [1 << 17]byte +var z1110 [1 << 17]byte +var z1111 [1 << 17]byte +var z1112 [1 << 17]byte +var z1113 [1 << 17]byte +var z1114 [1 << 17]byte +var z1115 [1 << 17]byte +var z1116 [1 << 17]byte +var z1117 [1 << 17]byte +var z1118 [1 << 17]byte +var z1119 [1 << 17]byte +var z1120 [1 << 17]byte +var z1121 [1 << 17]byte +var z1122 [1 << 17]byte +var z1123 [1 << 17]byte +var z1124 [1 << 17]byte +var z1125 [1 << 17]byte +var z1126 [1 << 17]byte +var z1127 [1 << 17]byte +var z1128 [1 << 17]byte +var z1129 [1 << 17]byte +var z1130 [1 << 17]byte +var z1131 [1 << 17]byte +var z1132 [1 << 17]byte +var z1133 [1 << 17]byte +var z1134 [1 << 17]byte +var z1135 [1 << 17]byte +var z1136 [1 << 17]byte +var z1137 [1 << 17]byte +var z1138 [1 << 17]byte +var z1139 [1 << 17]byte +var z1140 [1 << 17]byte +var z1141 [1 << 17]byte +var z1142 [1 << 17]byte +var z1143 [1 << 17]byte +var z1144 [1 << 17]byte +var z1145 [1 << 17]byte +var z1146 [1 << 17]byte +var z1147 [1 << 17]byte +var z1148 [1 << 17]byte +var z1149 [1 << 17]byte +var z1150 [1 << 17]byte +var z1151 [1 << 17]byte +var z1152 [1 << 17]byte +var z1153 [1 << 17]byte +var z1154 [1 << 17]byte +var z1155 [1 << 17]byte +var z1156 [1 << 17]byte +var z1157 [1 << 17]byte +var z1158 [1 << 17]byte +var z1159 [1 << 17]byte +var z1160 [1 << 17]byte +var z1161 [1 << 17]byte +var z1162 [1 << 17]byte +var z1163 [1 << 17]byte +var z1164 [1 << 17]byte +var z1165 [1 << 17]byte +var z1166 [1 << 17]byte +var z1167 [1 << 17]byte +var z1168 [1 << 17]byte +var z1169 [1 << 17]byte +var z1170 [1 << 17]byte +var z1171 [1 << 17]byte +var z1172 [1 << 17]byte +var z1173 [1 << 17]byte +var z1174 [1 << 17]byte +var z1175 [1 << 17]byte +var z1176 [1 << 17]byte +var z1177 [1 << 17]byte +var z1178 [1 << 17]byte +var z1179 [1 << 17]byte +var z1180 [1 << 17]byte +var z1181 [1 << 17]byte +var z1182 [1 << 17]byte +var z1183 [1 << 17]byte +var z1184 [1 << 17]byte +var z1185 [1 << 17]byte +var z1186 [1 << 17]byte +var z1187 [1 << 17]byte +var z1188 [1 << 17]byte +var z1189 [1 << 17]byte +var z1190 [1 << 17]byte +var z1191 [1 << 17]byte +var z1192 [1 << 17]byte +var z1193 [1 << 17]byte +var z1194 [1 << 17]byte +var z1195 [1 << 17]byte +var z1196 [1 << 17]byte +var z1197 [1 << 17]byte +var z1198 [1 << 17]byte +var z1199 [1 << 17]byte +var z1200 [1 << 17]byte +var z1201 [1 << 17]byte +var z1202 [1 << 17]byte +var z1203 [1 << 17]byte +var z1204 [1 << 17]byte +var z1205 [1 << 17]byte +var z1206 [1 << 17]byte +var z1207 [1 << 17]byte +var z1208 [1 << 17]byte +var z1209 [1 << 17]byte +var z1210 [1 << 17]byte +var z1211 [1 << 17]byte +var z1212 [1 << 17]byte +var z1213 [1 << 17]byte +var z1214 [1 << 17]byte +var z1215 [1 << 17]byte +var z1216 [1 << 17]byte +var z1217 [1 << 17]byte +var z1218 [1 << 17]byte +var z1219 [1 << 17]byte +var z1220 [1 << 17]byte +var z1221 [1 << 17]byte +var z1222 [1 << 17]byte +var z1223 [1 << 17]byte +var z1224 [1 << 17]byte +var z1225 [1 << 17]byte +var z1226 [1 << 17]byte +var z1227 [1 << 17]byte +var z1228 [1 << 17]byte +var z1229 [1 << 17]byte +var z1230 [1 << 17]byte +var z1231 [1 << 17]byte +var z1232 [1 << 17]byte +var z1233 [1 << 17]byte +var z1234 [1 << 17]byte +var z1235 [1 << 17]byte +var z1236 [1 << 17]byte +var z1237 [1 << 17]byte +var z1238 [1 << 17]byte +var z1239 [1 << 17]byte +var z1240 [1 << 17]byte +var z1241 [1 << 17]byte +var z1242 [1 << 17]byte +var z1243 [1 << 17]byte +var z1244 [1 << 17]byte +var z1245 [1 << 17]byte +var z1246 [1 << 17]byte +var z1247 [1 << 17]byte +var z1248 [1 << 17]byte +var z1249 [1 << 17]byte +var z1250 [1 << 17]byte +var z1251 [1 << 17]byte +var z1252 [1 << 17]byte +var z1253 [1 << 17]byte +var z1254 [1 << 17]byte +var z1255 [1 << 17]byte +var z1256 [1 << 17]byte +var z1257 [1 << 17]byte +var z1258 [1 << 17]byte +var z1259 [1 << 17]byte +var z1260 [1 << 17]byte +var z1261 [1 << 17]byte +var z1262 [1 << 17]byte +var z1263 [1 << 17]byte +var z1264 [1 << 17]byte +var z1265 [1 << 17]byte +var z1266 [1 << 17]byte +var z1267 [1 << 17]byte +var z1268 [1 << 17]byte +var z1269 [1 << 17]byte +var z1270 [1 << 17]byte +var z1271 [1 << 17]byte +var z1272 [1 << 17]byte +var z1273 [1 << 17]byte +var z1274 [1 << 17]byte +var z1275 [1 << 17]byte +var z1276 [1 << 17]byte +var z1277 [1 << 17]byte +var z1278 [1 << 17]byte +var z1279 [1 << 17]byte +var z1280 [1 << 17]byte +var z1281 [1 << 17]byte +var z1282 [1 << 17]byte +var z1283 [1 << 17]byte +var z1284 [1 << 17]byte +var z1285 [1 << 17]byte +var z1286 [1 << 17]byte +var z1287 [1 << 17]byte +var z1288 [1 << 17]byte +var z1289 [1 << 17]byte +var z1290 [1 << 17]byte +var z1291 [1 << 17]byte +var z1292 [1 << 17]byte +var z1293 [1 << 17]byte +var z1294 [1 << 17]byte +var z1295 [1 << 17]byte +var z1296 [1 << 17]byte +var z1297 [1 << 17]byte +var z1298 [1 << 17]byte +var z1299 [1 << 17]byte +var z1300 [1 << 17]byte +var z1301 [1 << 17]byte +var z1302 [1 << 17]byte +var z1303 [1 << 17]byte +var z1304 [1 << 17]byte +var z1305 [1 << 17]byte +var z1306 [1 << 17]byte +var z1307 [1 << 17]byte +var z1308 [1 << 17]byte +var z1309 [1 << 17]byte +var z1310 [1 << 17]byte +var z1311 [1 << 17]byte +var z1312 [1 << 17]byte +var z1313 [1 << 17]byte +var z1314 [1 << 17]byte +var z1315 [1 << 17]byte +var z1316 [1 << 17]byte +var z1317 [1 << 17]byte +var z1318 [1 << 17]byte +var z1319 [1 << 17]byte +var z1320 [1 << 17]byte +var z1321 [1 << 17]byte +var z1322 [1 << 17]byte +var z1323 [1 << 17]byte +var z1324 [1 << 17]byte +var z1325 [1 << 17]byte +var z1326 [1 << 17]byte +var z1327 [1 << 17]byte +var z1328 [1 << 17]byte +var z1329 [1 << 17]byte +var z1330 [1 << 17]byte +var z1331 [1 << 17]byte +var z1332 [1 << 17]byte +var z1333 [1 << 17]byte +var z1334 [1 << 17]byte +var z1335 [1 << 17]byte +var z1336 [1 << 17]byte +var z1337 [1 << 17]byte +var z1338 [1 << 17]byte +var z1339 [1 << 17]byte +var z1340 [1 << 17]byte +var z1341 [1 << 17]byte +var z1342 [1 << 17]byte +var z1343 [1 << 17]byte +var z1344 [1 << 17]byte +var z1345 [1 << 17]byte +var z1346 [1 << 17]byte +var z1347 [1 << 17]byte +var z1348 [1 << 17]byte +var z1349 [1 << 17]byte +var z1350 [1 << 17]byte +var z1351 [1 << 17]byte +var z1352 [1 << 17]byte +var z1353 [1 << 17]byte +var z1354 [1 << 17]byte +var z1355 [1 << 17]byte +var z1356 [1 << 17]byte +var z1357 [1 << 17]byte +var z1358 [1 << 17]byte +var z1359 [1 << 17]byte +var z1360 [1 << 17]byte +var z1361 [1 << 17]byte +var z1362 [1 << 17]byte +var z1363 [1 << 17]byte +var z1364 [1 << 17]byte +var z1365 [1 << 17]byte +var z1366 [1 << 17]byte +var z1367 [1 << 17]byte +var z1368 [1 << 17]byte +var z1369 [1 << 17]byte +var z1370 [1 << 17]byte +var z1371 [1 << 17]byte +var z1372 [1 << 17]byte +var z1373 [1 << 17]byte +var z1374 [1 << 17]byte +var z1375 [1 << 17]byte +var z1376 [1 << 17]byte +var z1377 [1 << 17]byte +var z1378 [1 << 17]byte +var z1379 [1 << 17]byte +var z1380 [1 << 17]byte +var z1381 [1 << 17]byte +var z1382 [1 << 17]byte +var z1383 [1 << 17]byte +var z1384 [1 << 17]byte +var z1385 [1 << 17]byte +var z1386 [1 << 17]byte +var z1387 [1 << 17]byte +var z1388 [1 << 17]byte +var z1389 [1 << 17]byte +var z1390 [1 << 17]byte +var z1391 [1 << 17]byte +var z1392 [1 << 17]byte +var z1393 [1 << 17]byte +var z1394 [1 << 17]byte +var z1395 [1 << 17]byte +var z1396 [1 << 17]byte +var z1397 [1 << 17]byte +var z1398 [1 << 17]byte +var z1399 [1 << 17]byte +var z1400 [1 << 17]byte +var z1401 [1 << 17]byte +var z1402 [1 << 17]byte +var z1403 [1 << 17]byte +var z1404 [1 << 17]byte +var z1405 [1 << 17]byte +var z1406 [1 << 17]byte +var z1407 [1 << 17]byte +var z1408 [1 << 17]byte +var z1409 [1 << 17]byte +var z1410 [1 << 17]byte +var z1411 [1 << 17]byte +var z1412 [1 << 17]byte +var z1413 [1 << 17]byte +var z1414 [1 << 17]byte +var z1415 [1 << 17]byte +var z1416 [1 << 17]byte +var z1417 [1 << 17]byte +var z1418 [1 << 17]byte +var z1419 [1 << 17]byte +var z1420 [1 << 17]byte +var z1421 [1 << 17]byte +var z1422 [1 << 17]byte +var z1423 [1 << 17]byte +var z1424 [1 << 17]byte +var z1425 [1 << 17]byte +var z1426 [1 << 17]byte +var z1427 [1 << 17]byte +var z1428 [1 << 17]byte +var z1429 [1 << 17]byte +var z1430 [1 << 17]byte +var z1431 [1 << 17]byte +var z1432 [1 << 17]byte +var z1433 [1 << 17]byte +var z1434 [1 << 17]byte +var z1435 [1 << 17]byte +var z1436 [1 << 17]byte +var z1437 [1 << 17]byte +var z1438 [1 << 17]byte +var z1439 [1 << 17]byte +var z1440 [1 << 17]byte +var z1441 [1 << 17]byte +var z1442 [1 << 17]byte +var z1443 [1 << 17]byte +var z1444 [1 << 17]byte +var z1445 [1 << 17]byte +var z1446 [1 << 17]byte +var z1447 [1 << 17]byte +var z1448 [1 << 17]byte +var z1449 [1 << 17]byte +var z1450 [1 << 17]byte +var z1451 [1 << 17]byte +var z1452 [1 << 17]byte +var z1453 [1 << 17]byte +var z1454 [1 << 17]byte +var z1455 [1 << 17]byte +var z1456 [1 << 17]byte +var z1457 [1 << 17]byte +var z1458 [1 << 17]byte +var z1459 [1 << 17]byte +var z1460 [1 << 17]byte +var z1461 [1 << 17]byte +var z1462 [1 << 17]byte +var z1463 [1 << 17]byte +var z1464 [1 << 17]byte +var z1465 [1 << 17]byte +var z1466 [1 << 17]byte +var z1467 [1 << 17]byte +var z1468 [1 << 17]byte +var z1469 [1 << 17]byte +var z1470 [1 << 17]byte +var z1471 [1 << 17]byte +var z1472 [1 << 17]byte +var z1473 [1 << 17]byte +var z1474 [1 << 17]byte +var z1475 [1 << 17]byte +var z1476 [1 << 17]byte +var z1477 [1 << 17]byte +var z1478 [1 << 17]byte +var z1479 [1 << 17]byte +var z1480 [1 << 17]byte +var z1481 [1 << 17]byte +var z1482 [1 << 17]byte +var z1483 [1 << 17]byte +var z1484 [1 << 17]byte +var z1485 [1 << 17]byte +var z1486 [1 << 17]byte +var z1487 [1 << 17]byte +var z1488 [1 << 17]byte +var z1489 [1 << 17]byte +var z1490 [1 << 17]byte +var z1491 [1 << 17]byte +var z1492 [1 << 17]byte +var z1493 [1 << 17]byte +var z1494 [1 << 17]byte +var z1495 [1 << 17]byte +var z1496 [1 << 17]byte +var z1497 [1 << 17]byte +var z1498 [1 << 17]byte +var z1499 [1 << 17]byte +var z1500 [1 << 17]byte +var z1501 [1 << 17]byte +var z1502 [1 << 17]byte +var z1503 [1 << 17]byte +var z1504 [1 << 17]byte +var z1505 [1 << 17]byte +var z1506 [1 << 17]byte +var z1507 [1 << 17]byte +var z1508 [1 << 17]byte +var z1509 [1 << 17]byte +var z1510 [1 << 17]byte +var z1511 [1 << 17]byte +var z1512 [1 << 17]byte +var z1513 [1 << 17]byte +var z1514 [1 << 17]byte +var z1515 [1 << 17]byte +var z1516 [1 << 17]byte +var z1517 [1 << 17]byte +var z1518 [1 << 17]byte +var z1519 [1 << 17]byte +var z1520 [1 << 17]byte +var z1521 [1 << 17]byte +var z1522 [1 << 17]byte +var z1523 [1 << 17]byte +var z1524 [1 << 17]byte +var z1525 [1 << 17]byte +var z1526 [1 << 17]byte +var z1527 [1 << 17]byte +var z1528 [1 << 17]byte +var z1529 [1 << 17]byte +var z1530 [1 << 17]byte +var z1531 [1 << 17]byte +var z1532 [1 << 17]byte +var z1533 [1 << 17]byte +var z1534 [1 << 17]byte +var z1535 [1 << 17]byte +var z1536 [1 << 17]byte +var z1537 [1 << 17]byte +var z1538 [1 << 17]byte +var z1539 [1 << 17]byte +var z1540 [1 << 17]byte +var z1541 [1 << 17]byte +var z1542 [1 << 17]byte +var z1543 [1 << 17]byte +var z1544 [1 << 17]byte +var z1545 [1 << 17]byte +var z1546 [1 << 17]byte +var z1547 [1 << 17]byte +var z1548 [1 << 17]byte +var z1549 [1 << 17]byte +var z1550 [1 << 17]byte +var z1551 [1 << 17]byte +var z1552 [1 << 17]byte +var z1553 [1 << 17]byte +var z1554 [1 << 17]byte +var z1555 [1 << 17]byte +var z1556 [1 << 17]byte +var z1557 [1 << 17]byte +var z1558 [1 << 17]byte +var z1559 [1 << 17]byte +var z1560 [1 << 17]byte +var z1561 [1 << 17]byte +var z1562 [1 << 17]byte +var z1563 [1 << 17]byte +var z1564 [1 << 17]byte +var z1565 [1 << 17]byte +var z1566 [1 << 17]byte +var z1567 [1 << 17]byte +var z1568 [1 << 17]byte +var z1569 [1 << 17]byte +var z1570 [1 << 17]byte +var z1571 [1 << 17]byte +var z1572 [1 << 17]byte +var z1573 [1 << 17]byte +var z1574 [1 << 17]byte +var z1575 [1 << 17]byte +var z1576 [1 << 17]byte +var z1577 [1 << 17]byte +var z1578 [1 << 17]byte +var z1579 [1 << 17]byte +var z1580 [1 << 17]byte +var z1581 [1 << 17]byte +var z1582 [1 << 17]byte +var z1583 [1 << 17]byte +var z1584 [1 << 17]byte +var z1585 [1 << 17]byte +var z1586 [1 << 17]byte +var z1587 [1 << 17]byte +var z1588 [1 << 17]byte +var z1589 [1 << 17]byte +var z1590 [1 << 17]byte +var z1591 [1 << 17]byte +var z1592 [1 << 17]byte +var z1593 [1 << 17]byte +var z1594 [1 << 17]byte +var z1595 [1 << 17]byte +var z1596 [1 << 17]byte +var z1597 [1 << 17]byte +var z1598 [1 << 17]byte +var z1599 [1 << 17]byte +var z1600 [1 << 17]byte +var z1601 [1 << 17]byte +var z1602 [1 << 17]byte +var z1603 [1 << 17]byte +var z1604 [1 << 17]byte +var z1605 [1 << 17]byte +var z1606 [1 << 17]byte +var z1607 [1 << 17]byte +var z1608 [1 << 17]byte +var z1609 [1 << 17]byte +var z1610 [1 << 17]byte +var z1611 [1 << 17]byte +var z1612 [1 << 17]byte +var z1613 [1 << 17]byte +var z1614 [1 << 17]byte +var z1615 [1 << 17]byte +var z1616 [1 << 17]byte +var z1617 [1 << 17]byte +var z1618 [1 << 17]byte +var z1619 [1 << 17]byte +var z1620 [1 << 17]byte +var z1621 [1 << 17]byte +var z1622 [1 << 17]byte +var z1623 [1 << 17]byte +var z1624 [1 << 17]byte +var z1625 [1 << 17]byte +var z1626 [1 << 17]byte +var z1627 [1 << 17]byte +var z1628 [1 << 17]byte +var z1629 [1 << 17]byte +var z1630 [1 << 17]byte +var z1631 [1 << 17]byte +var z1632 [1 << 17]byte +var z1633 [1 << 17]byte +var z1634 [1 << 17]byte +var z1635 [1 << 17]byte +var z1636 [1 << 17]byte +var z1637 [1 << 17]byte +var z1638 [1 << 17]byte +var z1639 [1 << 17]byte +var z1640 [1 << 17]byte +var z1641 [1 << 17]byte +var z1642 [1 << 17]byte +var z1643 [1 << 17]byte +var z1644 [1 << 17]byte +var z1645 [1 << 17]byte +var z1646 [1 << 17]byte +var z1647 [1 << 17]byte +var z1648 [1 << 17]byte +var z1649 [1 << 17]byte +var z1650 [1 << 17]byte +var z1651 [1 << 17]byte +var z1652 [1 << 17]byte +var z1653 [1 << 17]byte +var z1654 [1 << 17]byte +var z1655 [1 << 17]byte +var z1656 [1 << 17]byte +var z1657 [1 << 17]byte +var z1658 [1 << 17]byte +var z1659 [1 << 17]byte +var z1660 [1 << 17]byte +var z1661 [1 << 17]byte +var z1662 [1 << 17]byte +var z1663 [1 << 17]byte +var z1664 [1 << 17]byte +var z1665 [1 << 17]byte +var z1666 [1 << 17]byte +var z1667 [1 << 17]byte +var z1668 [1 << 17]byte +var z1669 [1 << 17]byte +var z1670 [1 << 17]byte +var z1671 [1 << 17]byte +var z1672 [1 << 17]byte +var z1673 [1 << 17]byte +var z1674 [1 << 17]byte +var z1675 [1 << 17]byte +var z1676 [1 << 17]byte +var z1677 [1 << 17]byte +var z1678 [1 << 17]byte +var z1679 [1 << 17]byte +var z1680 [1 << 17]byte +var z1681 [1 << 17]byte +var z1682 [1 << 17]byte +var z1683 [1 << 17]byte +var z1684 [1 << 17]byte +var z1685 [1 << 17]byte +var z1686 [1 << 17]byte +var z1687 [1 << 17]byte +var z1688 [1 << 17]byte +var z1689 [1 << 17]byte +var z1690 [1 << 17]byte +var z1691 [1 << 17]byte +var z1692 [1 << 17]byte +var z1693 [1 << 17]byte +var z1694 [1 << 17]byte +var z1695 [1 << 17]byte +var z1696 [1 << 17]byte +var z1697 [1 << 17]byte +var z1698 [1 << 17]byte +var z1699 [1 << 17]byte +var z1700 [1 << 17]byte +var z1701 [1 << 17]byte +var z1702 [1 << 17]byte +var z1703 [1 << 17]byte +var z1704 [1 << 17]byte +var z1705 [1 << 17]byte +var z1706 [1 << 17]byte +var z1707 [1 << 17]byte +var z1708 [1 << 17]byte +var z1709 [1 << 17]byte +var z1710 [1 << 17]byte +var z1711 [1 << 17]byte +var z1712 [1 << 17]byte +var z1713 [1 << 17]byte +var z1714 [1 << 17]byte +var z1715 [1 << 17]byte +var z1716 [1 << 17]byte +var z1717 [1 << 17]byte +var z1718 [1 << 17]byte +var z1719 [1 << 17]byte +var z1720 [1 << 17]byte +var z1721 [1 << 17]byte +var z1722 [1 << 17]byte +var z1723 [1 << 17]byte +var z1724 [1 << 17]byte +var z1725 [1 << 17]byte +var z1726 [1 << 17]byte +var z1727 [1 << 17]byte +var z1728 [1 << 17]byte +var z1729 [1 << 17]byte +var z1730 [1 << 17]byte +var z1731 [1 << 17]byte +var z1732 [1 << 17]byte +var z1733 [1 << 17]byte +var z1734 [1 << 17]byte +var z1735 [1 << 17]byte +var z1736 [1 << 17]byte +var z1737 [1 << 17]byte +var z1738 [1 << 17]byte +var z1739 [1 << 17]byte +var z1740 [1 << 17]byte +var z1741 [1 << 17]byte +var z1742 [1 << 17]byte +var z1743 [1 << 17]byte +var z1744 [1 << 17]byte +var z1745 [1 << 17]byte +var z1746 [1 << 17]byte +var z1747 [1 << 17]byte +var z1748 [1 << 17]byte +var z1749 [1 << 17]byte +var z1750 [1 << 17]byte +var z1751 [1 << 17]byte +var z1752 [1 << 17]byte +var z1753 [1 << 17]byte +var z1754 [1 << 17]byte +var z1755 [1 << 17]byte +var z1756 [1 << 17]byte +var z1757 [1 << 17]byte +var z1758 [1 << 17]byte +var z1759 [1 << 17]byte +var z1760 [1 << 17]byte +var z1761 [1 << 17]byte +var z1762 [1 << 17]byte +var z1763 [1 << 17]byte +var z1764 [1 << 17]byte +var z1765 [1 << 17]byte +var z1766 [1 << 17]byte +var z1767 [1 << 17]byte +var z1768 [1 << 17]byte +var z1769 [1 << 17]byte +var z1770 [1 << 17]byte +var z1771 [1 << 17]byte +var z1772 [1 << 17]byte +var z1773 [1 << 17]byte +var z1774 [1 << 17]byte +var z1775 [1 << 17]byte +var z1776 [1 << 17]byte +var z1777 [1 << 17]byte +var z1778 [1 << 17]byte +var z1779 [1 << 17]byte +var z1780 [1 << 17]byte +var z1781 [1 << 17]byte +var z1782 [1 << 17]byte +var z1783 [1 << 17]byte +var z1784 [1 << 17]byte +var z1785 [1 << 17]byte +var z1786 [1 << 17]byte +var z1787 [1 << 17]byte +var z1788 [1 << 17]byte +var z1789 [1 << 17]byte +var z1790 [1 << 17]byte +var z1791 [1 << 17]byte +var z1792 [1 << 17]byte +var z1793 [1 << 17]byte +var z1794 [1 << 17]byte +var z1795 [1 << 17]byte +var z1796 [1 << 17]byte +var z1797 [1 << 17]byte +var z1798 [1 << 17]byte +var z1799 [1 << 17]byte +var z1800 [1 << 17]byte +var z1801 [1 << 17]byte +var z1802 [1 << 17]byte +var z1803 [1 << 17]byte +var z1804 [1 << 17]byte +var z1805 [1 << 17]byte +var z1806 [1 << 17]byte +var z1807 [1 << 17]byte +var z1808 [1 << 17]byte +var z1809 [1 << 17]byte +var z1810 [1 << 17]byte +var z1811 [1 << 17]byte +var z1812 [1 << 17]byte +var z1813 [1 << 17]byte +var z1814 [1 << 17]byte +var z1815 [1 << 17]byte +var z1816 [1 << 17]byte +var z1817 [1 << 17]byte +var z1818 [1 << 17]byte +var z1819 [1 << 17]byte +var z1820 [1 << 17]byte +var z1821 [1 << 17]byte +var z1822 [1 << 17]byte +var z1823 [1 << 17]byte +var z1824 [1 << 17]byte +var z1825 [1 << 17]byte +var z1826 [1 << 17]byte +var z1827 [1 << 17]byte +var z1828 [1 << 17]byte +var z1829 [1 << 17]byte +var z1830 [1 << 17]byte +var z1831 [1 << 17]byte +var z1832 [1 << 17]byte +var z1833 [1 << 17]byte +var z1834 [1 << 17]byte +var z1835 [1 << 17]byte +var z1836 [1 << 17]byte +var z1837 [1 << 17]byte +var z1838 [1 << 17]byte +var z1839 [1 << 17]byte +var z1840 [1 << 17]byte +var z1841 [1 << 17]byte +var z1842 [1 << 17]byte +var z1843 [1 << 17]byte +var z1844 [1 << 17]byte +var z1845 [1 << 17]byte +var z1846 [1 << 17]byte +var z1847 [1 << 17]byte +var z1848 [1 << 17]byte +var z1849 [1 << 17]byte +var z1850 [1 << 17]byte +var z1851 [1 << 17]byte +var z1852 [1 << 17]byte +var z1853 [1 << 17]byte +var z1854 [1 << 17]byte +var z1855 [1 << 17]byte +var z1856 [1 << 17]byte +var z1857 [1 << 17]byte +var z1858 [1 << 17]byte +var z1859 [1 << 17]byte +var z1860 [1 << 17]byte +var z1861 [1 << 17]byte +var z1862 [1 << 17]byte +var z1863 [1 << 17]byte +var z1864 [1 << 17]byte +var z1865 [1 << 17]byte +var z1866 [1 << 17]byte +var z1867 [1 << 17]byte +var z1868 [1 << 17]byte +var z1869 [1 << 17]byte +var z1870 [1 << 17]byte +var z1871 [1 << 17]byte +var z1872 [1 << 17]byte +var z1873 [1 << 17]byte +var z1874 [1 << 17]byte +var z1875 [1 << 17]byte +var z1876 [1 << 17]byte +var z1877 [1 << 17]byte +var z1878 [1 << 17]byte +var z1879 [1 << 17]byte +var z1880 [1 << 17]byte +var z1881 [1 << 17]byte +var z1882 [1 << 17]byte +var z1883 [1 << 17]byte +var z1884 [1 << 17]byte +var z1885 [1 << 17]byte +var z1886 [1 << 17]byte +var z1887 [1 << 17]byte +var z1888 [1 << 17]byte +var z1889 [1 << 17]byte +var z1890 [1 << 17]byte +var z1891 [1 << 17]byte +var z1892 [1 << 17]byte +var z1893 [1 << 17]byte +var z1894 [1 << 17]byte +var z1895 [1 << 17]byte +var z1896 [1 << 17]byte +var z1897 [1 << 17]byte +var z1898 [1 << 17]byte +var z1899 [1 << 17]byte +var z1900 [1 << 17]byte +var z1901 [1 << 17]byte +var z1902 [1 << 17]byte +var z1903 [1 << 17]byte +var z1904 [1 << 17]byte +var z1905 [1 << 17]byte +var z1906 [1 << 17]byte +var z1907 [1 << 17]byte +var z1908 [1 << 17]byte +var z1909 [1 << 17]byte +var z1910 [1 << 17]byte +var z1911 [1 << 17]byte +var z1912 [1 << 17]byte +var z1913 [1 << 17]byte +var z1914 [1 << 17]byte +var z1915 [1 << 17]byte +var z1916 [1 << 17]byte +var z1917 [1 << 17]byte +var z1918 [1 << 17]byte +var z1919 [1 << 17]byte +var z1920 [1 << 17]byte +var z1921 [1 << 17]byte +var z1922 [1 << 17]byte +var z1923 [1 << 17]byte +var z1924 [1 << 17]byte +var z1925 [1 << 17]byte +var z1926 [1 << 17]byte +var z1927 [1 << 17]byte +var z1928 [1 << 17]byte +var z1929 [1 << 17]byte +var z1930 [1 << 17]byte +var z1931 [1 << 17]byte +var z1932 [1 << 17]byte +var z1933 [1 << 17]byte +var z1934 [1 << 17]byte +var z1935 [1 << 17]byte +var z1936 [1 << 17]byte +var z1937 [1 << 17]byte +var z1938 [1 << 17]byte +var z1939 [1 << 17]byte +var z1940 [1 << 17]byte +var z1941 [1 << 17]byte +var z1942 [1 << 17]byte +var z1943 [1 << 17]byte +var z1944 [1 << 17]byte +var z1945 [1 << 17]byte +var z1946 [1 << 17]byte +var z1947 [1 << 17]byte +var z1948 [1 << 17]byte +var z1949 [1 << 17]byte +var z1950 [1 << 17]byte +var z1951 [1 << 17]byte +var z1952 [1 << 17]byte +var z1953 [1 << 17]byte +var z1954 [1 << 17]byte +var z1955 [1 << 17]byte +var z1956 [1 << 17]byte +var z1957 [1 << 17]byte +var z1958 [1 << 17]byte +var z1959 [1 << 17]byte +var z1960 [1 << 17]byte +var z1961 [1 << 17]byte +var z1962 [1 << 17]byte +var z1963 [1 << 17]byte +var z1964 [1 << 17]byte +var z1965 [1 << 17]byte +var z1966 [1 << 17]byte +var z1967 [1 << 17]byte +var z1968 [1 << 17]byte +var z1969 [1 << 17]byte +var z1970 [1 << 17]byte +var z1971 [1 << 17]byte +var z1972 [1 << 17]byte +var z1973 [1 << 17]byte +var z1974 [1 << 17]byte +var z1975 [1 << 17]byte +var z1976 [1 << 17]byte +var z1977 [1 << 17]byte +var z1978 [1 << 17]byte +var z1979 [1 << 17]byte +var z1980 [1 << 17]byte +var z1981 [1 << 17]byte +var z1982 [1 << 17]byte +var z1983 [1 << 17]byte +var z1984 [1 << 17]byte +var z1985 [1 << 17]byte +var z1986 [1 << 17]byte +var z1987 [1 << 17]byte +var z1988 [1 << 17]byte +var z1989 [1 << 17]byte +var z1990 [1 << 17]byte +var z1991 [1 << 17]byte +var z1992 [1 << 17]byte +var z1993 [1 << 17]byte +var z1994 [1 << 17]byte +var z1995 [1 << 17]byte +var z1996 [1 << 17]byte +var z1997 [1 << 17]byte +var z1998 [1 << 17]byte +var z1999 [1 << 17]byte +var z2000 [1 << 17]byte +var z2001 [1 << 17]byte +var z2002 [1 << 17]byte +var z2003 [1 << 17]byte +var z2004 [1 << 17]byte +var z2005 [1 << 17]byte +var z2006 [1 << 17]byte +var z2007 [1 << 17]byte +var z2008 [1 << 17]byte +var z2009 [1 << 17]byte +var z2010 [1 << 17]byte +var z2011 [1 << 17]byte +var z2012 [1 << 17]byte +var z2013 [1 << 17]byte +var z2014 [1 << 17]byte +var z2015 [1 << 17]byte +var z2016 [1 << 17]byte +var z2017 [1 << 17]byte +var z2018 [1 << 17]byte +var z2019 [1 << 17]byte +var z2020 [1 << 17]byte +var z2021 [1 << 17]byte +var z2022 [1 << 17]byte +var z2023 [1 << 17]byte +var z2024 [1 << 17]byte +var z2025 [1 << 17]byte +var z2026 [1 << 17]byte +var z2027 [1 << 17]byte +var z2028 [1 << 17]byte +var z2029 [1 << 17]byte +var z2030 [1 << 17]byte +var z2031 [1 << 17]byte +var z2032 [1 << 17]byte +var z2033 [1 << 17]byte +var z2034 [1 << 17]byte +var z2035 [1 << 17]byte +var z2036 [1 << 17]byte +var z2037 [1 << 17]byte +var z2038 [1 << 17]byte +var z2039 [1 << 17]byte +var z2040 [1 << 17]byte +var z2041 [1 << 17]byte +var z2042 [1 << 17]byte +var z2043 [1 << 17]byte +var z2044 [1 << 17]byte +var z2045 [1 << 17]byte +var z2046 [1 << 17]byte +var z2047 [1 << 17]byte +var z2048 [1 << 17]byte +var z2049 [1 << 17]byte +var z2050 [1 << 17]byte +var z2051 [1 << 17]byte +var z2052 [1 << 17]byte +var z2053 [1 << 17]byte +var z2054 [1 << 17]byte +var z2055 [1 << 17]byte +var z2056 [1 << 17]byte +var z2057 [1 << 17]byte +var z2058 [1 << 17]byte +var z2059 [1 << 17]byte +var z2060 [1 << 17]byte +var z2061 [1 << 17]byte +var z2062 [1 << 17]byte +var z2063 [1 << 17]byte +var z2064 [1 << 17]byte +var z2065 [1 << 17]byte +var z2066 [1 << 17]byte +var z2067 [1 << 17]byte +var z2068 [1 << 17]byte +var z2069 [1 << 17]byte +var z2070 [1 << 17]byte +var z2071 [1 << 17]byte +var z2072 [1 << 17]byte +var z2073 [1 << 17]byte +var z2074 [1 << 17]byte +var z2075 [1 << 17]byte +var z2076 [1 << 17]byte +var z2077 [1 << 17]byte +var z2078 [1 << 17]byte +var z2079 [1 << 17]byte +var z2080 [1 << 17]byte +var z2081 [1 << 17]byte +var z2082 [1 << 17]byte +var z2083 [1 << 17]byte +var z2084 [1 << 17]byte +var z2085 [1 << 17]byte +var z2086 [1 << 17]byte +var z2087 [1 << 17]byte +var z2088 [1 << 17]byte +var z2089 [1 << 17]byte +var z2090 [1 << 17]byte +var z2091 [1 << 17]byte +var z2092 [1 << 17]byte +var z2093 [1 << 17]byte +var z2094 [1 << 17]byte +var z2095 [1 << 17]byte +var z2096 [1 << 17]byte +var z2097 [1 << 17]byte +var z2098 [1 << 17]byte +var z2099 [1 << 17]byte +var z2100 [1 << 17]byte +var z2101 [1 << 17]byte +var z2102 [1 << 17]byte +var z2103 [1 << 17]byte +var z2104 [1 << 17]byte +var z2105 [1 << 17]byte +var z2106 [1 << 17]byte +var z2107 [1 << 17]byte +var z2108 [1 << 17]byte +var z2109 [1 << 17]byte +var z2110 [1 << 17]byte +var z2111 [1 << 17]byte +var z2112 [1 << 17]byte +var z2113 [1 << 17]byte +var z2114 [1 << 17]byte +var z2115 [1 << 17]byte +var z2116 [1 << 17]byte +var z2117 [1 << 17]byte +var z2118 [1 << 17]byte +var z2119 [1 << 17]byte +var z2120 [1 << 17]byte +var z2121 [1 << 17]byte +var z2122 [1 << 17]byte +var z2123 [1 << 17]byte +var z2124 [1 << 17]byte +var z2125 [1 << 17]byte +var z2126 [1 << 17]byte +var z2127 [1 << 17]byte +var z2128 [1 << 17]byte +var z2129 [1 << 17]byte +var z2130 [1 << 17]byte +var z2131 [1 << 17]byte +var z2132 [1 << 17]byte +var z2133 [1 << 17]byte +var z2134 [1 << 17]byte +var z2135 [1 << 17]byte +var z2136 [1 << 17]byte +var z2137 [1 << 17]byte +var z2138 [1 << 17]byte +var z2139 [1 << 17]byte +var z2140 [1 << 17]byte +var z2141 [1 << 17]byte +var z2142 [1 << 17]byte +var z2143 [1 << 17]byte +var z2144 [1 << 17]byte +var z2145 [1 << 17]byte +var z2146 [1 << 17]byte +var z2147 [1 << 17]byte +var z2148 [1 << 17]byte +var z2149 [1 << 17]byte +var z2150 [1 << 17]byte +var z2151 [1 << 17]byte +var z2152 [1 << 17]byte +var z2153 [1 << 17]byte +var z2154 [1 << 17]byte +var z2155 [1 << 17]byte +var z2156 [1 << 17]byte +var z2157 [1 << 17]byte +var z2158 [1 << 17]byte +var z2159 [1 << 17]byte +var z2160 [1 << 17]byte +var z2161 [1 << 17]byte +var z2162 [1 << 17]byte +var z2163 [1 << 17]byte +var z2164 [1 << 17]byte +var z2165 [1 << 17]byte +var z2166 [1 << 17]byte +var z2167 [1 << 17]byte +var z2168 [1 << 17]byte +var z2169 [1 << 17]byte +var z2170 [1 << 17]byte +var z2171 [1 << 17]byte +var z2172 [1 << 17]byte +var z2173 [1 << 17]byte +var z2174 [1 << 17]byte +var z2175 [1 << 17]byte +var z2176 [1 << 17]byte +var z2177 [1 << 17]byte +var z2178 [1 << 17]byte +var z2179 [1 << 17]byte +var z2180 [1 << 17]byte +var z2181 [1 << 17]byte +var z2182 [1 << 17]byte +var z2183 [1 << 17]byte +var z2184 [1 << 17]byte +var z2185 [1 << 17]byte +var z2186 [1 << 17]byte +var z2187 [1 << 17]byte +var z2188 [1 << 17]byte +var z2189 [1 << 17]byte +var z2190 [1 << 17]byte +var z2191 [1 << 17]byte +var z2192 [1 << 17]byte +var z2193 [1 << 17]byte +var z2194 [1 << 17]byte +var z2195 [1 << 17]byte +var z2196 [1 << 17]byte +var z2197 [1 << 17]byte +var z2198 [1 << 17]byte +var z2199 [1 << 17]byte +var z2200 [1 << 17]byte +var z2201 [1 << 17]byte +var z2202 [1 << 17]byte +var z2203 [1 << 17]byte +var z2204 [1 << 17]byte +var z2205 [1 << 17]byte +var z2206 [1 << 17]byte +var z2207 [1 << 17]byte +var z2208 [1 << 17]byte +var z2209 [1 << 17]byte +var z2210 [1 << 17]byte +var z2211 [1 << 17]byte +var z2212 [1 << 17]byte +var z2213 [1 << 17]byte +var z2214 [1 << 17]byte +var z2215 [1 << 17]byte +var z2216 [1 << 17]byte +var z2217 [1 << 17]byte +var z2218 [1 << 17]byte +var z2219 [1 << 17]byte +var z2220 [1 << 17]byte +var z2221 [1 << 17]byte +var z2222 [1 << 17]byte +var z2223 [1 << 17]byte +var z2224 [1 << 17]byte +var z2225 [1 << 17]byte +var z2226 [1 << 17]byte +var z2227 [1 << 17]byte +var z2228 [1 << 17]byte +var z2229 [1 << 17]byte +var z2230 [1 << 17]byte +var z2231 [1 << 17]byte +var z2232 [1 << 17]byte +var z2233 [1 << 17]byte +var z2234 [1 << 17]byte +var z2235 [1 << 17]byte +var z2236 [1 << 17]byte +var z2237 [1 << 17]byte +var z2238 [1 << 17]byte +var z2239 [1 << 17]byte +var z2240 [1 << 17]byte +var z2241 [1 << 17]byte +var z2242 [1 << 17]byte +var z2243 [1 << 17]byte +var z2244 [1 << 17]byte +var z2245 [1 << 17]byte +var z2246 [1 << 17]byte +var z2247 [1 << 17]byte +var z2248 [1 << 17]byte +var z2249 [1 << 17]byte +var z2250 [1 << 17]byte +var z2251 [1 << 17]byte +var z2252 [1 << 17]byte +var z2253 [1 << 17]byte +var z2254 [1 << 17]byte +var z2255 [1 << 17]byte +var z2256 [1 << 17]byte +var z2257 [1 << 17]byte +var z2258 [1 << 17]byte +var z2259 [1 << 17]byte +var z2260 [1 << 17]byte +var z2261 [1 << 17]byte +var z2262 [1 << 17]byte +var z2263 [1 << 17]byte +var z2264 [1 << 17]byte +var z2265 [1 << 17]byte +var z2266 [1 << 17]byte +var z2267 [1 << 17]byte +var z2268 [1 << 17]byte +var z2269 [1 << 17]byte +var z2270 [1 << 17]byte +var z2271 [1 << 17]byte +var z2272 [1 << 17]byte +var z2273 [1 << 17]byte +var z2274 [1 << 17]byte +var z2275 [1 << 17]byte +var z2276 [1 << 17]byte +var z2277 [1 << 17]byte +var z2278 [1 << 17]byte +var z2279 [1 << 17]byte +var z2280 [1 << 17]byte +var z2281 [1 << 17]byte +var z2282 [1 << 17]byte +var z2283 [1 << 17]byte +var z2284 [1 << 17]byte +var z2285 [1 << 17]byte +var z2286 [1 << 17]byte +var z2287 [1 << 17]byte +var z2288 [1 << 17]byte +var z2289 [1 << 17]byte +var z2290 [1 << 17]byte +var z2291 [1 << 17]byte +var z2292 [1 << 17]byte +var z2293 [1 << 17]byte +var z2294 [1 << 17]byte +var z2295 [1 << 17]byte +var z2296 [1 << 17]byte +var z2297 [1 << 17]byte +var z2298 [1 << 17]byte +var z2299 [1 << 17]byte +var z2300 [1 << 17]byte +var z2301 [1 << 17]byte +var z2302 [1 << 17]byte +var z2303 [1 << 17]byte +var z2304 [1 << 17]byte +var z2305 [1 << 17]byte +var z2306 [1 << 17]byte +var z2307 [1 << 17]byte +var z2308 [1 << 17]byte +var z2309 [1 << 17]byte +var z2310 [1 << 17]byte +var z2311 [1 << 17]byte +var z2312 [1 << 17]byte +var z2313 [1 << 17]byte +var z2314 [1 << 17]byte +var z2315 [1 << 17]byte +var z2316 [1 << 17]byte +var z2317 [1 << 17]byte +var z2318 [1 << 17]byte +var z2319 [1 << 17]byte +var z2320 [1 << 17]byte +var z2321 [1 << 17]byte +var z2322 [1 << 17]byte +var z2323 [1 << 17]byte +var z2324 [1 << 17]byte +var z2325 [1 << 17]byte +var z2326 [1 << 17]byte +var z2327 [1 << 17]byte +var z2328 [1 << 17]byte +var z2329 [1 << 17]byte +var z2330 [1 << 17]byte +var z2331 [1 << 17]byte +var z2332 [1 << 17]byte +var z2333 [1 << 17]byte +var z2334 [1 << 17]byte +var z2335 [1 << 17]byte +var z2336 [1 << 17]byte +var z2337 [1 << 17]byte +var z2338 [1 << 17]byte +var z2339 [1 << 17]byte +var z2340 [1 << 17]byte +var z2341 [1 << 17]byte +var z2342 [1 << 17]byte +var z2343 [1 << 17]byte +var z2344 [1 << 17]byte +var z2345 [1 << 17]byte +var z2346 [1 << 17]byte +var z2347 [1 << 17]byte +var z2348 [1 << 17]byte +var z2349 [1 << 17]byte +var z2350 [1 << 17]byte +var z2351 [1 << 17]byte +var z2352 [1 << 17]byte +var z2353 [1 << 17]byte +var z2354 [1 << 17]byte +var z2355 [1 << 17]byte +var z2356 [1 << 17]byte +var z2357 [1 << 17]byte +var z2358 [1 << 17]byte +var z2359 [1 << 17]byte +var z2360 [1 << 17]byte +var z2361 [1 << 17]byte +var z2362 [1 << 17]byte +var z2363 [1 << 17]byte +var z2364 [1 << 17]byte +var z2365 [1 << 17]byte +var z2366 [1 << 17]byte +var z2367 [1 << 17]byte +var z2368 [1 << 17]byte +var z2369 [1 << 17]byte +var z2370 [1 << 17]byte +var z2371 [1 << 17]byte +var z2372 [1 << 17]byte +var z2373 [1 << 17]byte +var z2374 [1 << 17]byte +var z2375 [1 << 17]byte +var z2376 [1 << 17]byte +var z2377 [1 << 17]byte +var z2378 [1 << 17]byte +var z2379 [1 << 17]byte +var z2380 [1 << 17]byte +var z2381 [1 << 17]byte +var z2382 [1 << 17]byte +var z2383 [1 << 17]byte +var z2384 [1 << 17]byte +var z2385 [1 << 17]byte +var z2386 [1 << 17]byte +var z2387 [1 << 17]byte +var z2388 [1 << 17]byte +var z2389 [1 << 17]byte +var z2390 [1 << 17]byte +var z2391 [1 << 17]byte +var z2392 [1 << 17]byte +var z2393 [1 << 17]byte +var z2394 [1 << 17]byte +var z2395 [1 << 17]byte +var z2396 [1 << 17]byte +var z2397 [1 << 17]byte +var z2398 [1 << 17]byte +var z2399 [1 << 17]byte +var z2400 [1 << 17]byte +var z2401 [1 << 17]byte +var z2402 [1 << 17]byte +var z2403 [1 << 17]byte +var z2404 [1 << 17]byte +var z2405 [1 << 17]byte +var z2406 [1 << 17]byte +var z2407 [1 << 17]byte +var z2408 [1 << 17]byte +var z2409 [1 << 17]byte +var z2410 [1 << 17]byte +var z2411 [1 << 17]byte +var z2412 [1 << 17]byte +var z2413 [1 << 17]byte +var z2414 [1 << 17]byte +var z2415 [1 << 17]byte +var z2416 [1 << 17]byte +var z2417 [1 << 17]byte +var z2418 [1 << 17]byte +var z2419 [1 << 17]byte +var z2420 [1 << 17]byte +var z2421 [1 << 17]byte +var z2422 [1 << 17]byte +var z2423 [1 << 17]byte +var z2424 [1 << 17]byte +var z2425 [1 << 17]byte +var z2426 [1 << 17]byte +var z2427 [1 << 17]byte +var z2428 [1 << 17]byte +var z2429 [1 << 17]byte +var z2430 [1 << 17]byte +var z2431 [1 << 17]byte +var z2432 [1 << 17]byte +var z2433 [1 << 17]byte +var z2434 [1 << 17]byte +var z2435 [1 << 17]byte +var z2436 [1 << 17]byte +var z2437 [1 << 17]byte +var z2438 [1 << 17]byte +var z2439 [1 << 17]byte +var z2440 [1 << 17]byte +var z2441 [1 << 17]byte +var z2442 [1 << 17]byte +var z2443 [1 << 17]byte +var z2444 [1 << 17]byte +var z2445 [1 << 17]byte +var z2446 [1 << 17]byte +var z2447 [1 << 17]byte +var z2448 [1 << 17]byte +var z2449 [1 << 17]byte +var z2450 [1 << 17]byte +var z2451 [1 << 17]byte +var z2452 [1 << 17]byte +var z2453 [1 << 17]byte +var z2454 [1 << 17]byte +var z2455 [1 << 17]byte +var z2456 [1 << 17]byte +var z2457 [1 << 17]byte +var z2458 [1 << 17]byte +var z2459 [1 << 17]byte +var z2460 [1 << 17]byte +var z2461 [1 << 17]byte +var z2462 [1 << 17]byte +var z2463 [1 << 17]byte +var z2464 [1 << 17]byte +var z2465 [1 << 17]byte +var z2466 [1 << 17]byte +var z2467 [1 << 17]byte +var z2468 [1 << 17]byte +var z2469 [1 << 17]byte +var z2470 [1 << 17]byte +var z2471 [1 << 17]byte +var z2472 [1 << 17]byte +var z2473 [1 << 17]byte +var z2474 [1 << 17]byte +var z2475 [1 << 17]byte +var z2476 [1 << 17]byte +var z2477 [1 << 17]byte +var z2478 [1 << 17]byte +var z2479 [1 << 17]byte +var z2480 [1 << 17]byte +var z2481 [1 << 17]byte +var z2482 [1 << 17]byte +var z2483 [1 << 17]byte +var z2484 [1 << 17]byte +var z2485 [1 << 17]byte +var z2486 [1 << 17]byte +var z2487 [1 << 17]byte +var z2488 [1 << 17]byte +var z2489 [1 << 17]byte +var z2490 [1 << 17]byte +var z2491 [1 << 17]byte +var z2492 [1 << 17]byte +var z2493 [1 << 17]byte +var z2494 [1 << 17]byte +var z2495 [1 << 17]byte +var z2496 [1 << 17]byte +var z2497 [1 << 17]byte +var z2498 [1 << 17]byte +var z2499 [1 << 17]byte +var z2500 [1 << 17]byte +var z2501 [1 << 17]byte +var z2502 [1 << 17]byte +var z2503 [1 << 17]byte +var z2504 [1 << 17]byte +var z2505 [1 << 17]byte +var z2506 [1 << 17]byte +var z2507 [1 << 17]byte +var z2508 [1 << 17]byte +var z2509 [1 << 17]byte +var z2510 [1 << 17]byte +var z2511 [1 << 17]byte +var z2512 [1 << 17]byte +var z2513 [1 << 17]byte +var z2514 [1 << 17]byte +var z2515 [1 << 17]byte +var z2516 [1 << 17]byte +var z2517 [1 << 17]byte +var z2518 [1 << 17]byte +var z2519 [1 << 17]byte +var z2520 [1 << 17]byte +var z2521 [1 << 17]byte +var z2522 [1 << 17]byte +var z2523 [1 << 17]byte +var z2524 [1 << 17]byte +var z2525 [1 << 17]byte +var z2526 [1 << 17]byte +var z2527 [1 << 17]byte +var z2528 [1 << 17]byte +var z2529 [1 << 17]byte +var z2530 [1 << 17]byte +var z2531 [1 << 17]byte +var z2532 [1 << 17]byte +var z2533 [1 << 17]byte +var z2534 [1 << 17]byte +var z2535 [1 << 17]byte +var z2536 [1 << 17]byte +var z2537 [1 << 17]byte +var z2538 [1 << 17]byte +var z2539 [1 << 17]byte +var z2540 [1 << 17]byte +var z2541 [1 << 17]byte +var z2542 [1 << 17]byte +var z2543 [1 << 17]byte +var z2544 [1 << 17]byte +var z2545 [1 << 17]byte +var z2546 [1 << 17]byte +var z2547 [1 << 17]byte +var z2548 [1 << 17]byte +var z2549 [1 << 17]byte +var z2550 [1 << 17]byte +var z2551 [1 << 17]byte +var z2552 [1 << 17]byte +var z2553 [1 << 17]byte +var z2554 [1 << 17]byte +var z2555 [1 << 17]byte +var z2556 [1 << 17]byte +var z2557 [1 << 17]byte +var z2558 [1 << 17]byte +var z2559 [1 << 17]byte +var z2560 [1 << 17]byte +var z2561 [1 << 17]byte +var z2562 [1 << 17]byte +var z2563 [1 << 17]byte +var z2564 [1 << 17]byte +var z2565 [1 << 17]byte +var z2566 [1 << 17]byte +var z2567 [1 << 17]byte +var z2568 [1 << 17]byte +var z2569 [1 << 17]byte +var z2570 [1 << 17]byte +var z2571 [1 << 17]byte +var z2572 [1 << 17]byte +var z2573 [1 << 17]byte +var z2574 [1 << 17]byte +var z2575 [1 << 17]byte +var z2576 [1 << 17]byte +var z2577 [1 << 17]byte +var z2578 [1 << 17]byte +var z2579 [1 << 17]byte +var z2580 [1 << 17]byte +var z2581 [1 << 17]byte +var z2582 [1 << 17]byte +var z2583 [1 << 17]byte +var z2584 [1 << 17]byte +var z2585 [1 << 17]byte +var z2586 [1 << 17]byte +var z2587 [1 << 17]byte +var z2588 [1 << 17]byte +var z2589 [1 << 17]byte +var z2590 [1 << 17]byte +var z2591 [1 << 17]byte +var z2592 [1 << 17]byte +var z2593 [1 << 17]byte +var z2594 [1 << 17]byte +var z2595 [1 << 17]byte +var z2596 [1 << 17]byte +var z2597 [1 << 17]byte +var z2598 [1 << 17]byte +var z2599 [1 << 17]byte +var z2600 [1 << 17]byte +var z2601 [1 << 17]byte +var z2602 [1 << 17]byte +var z2603 [1 << 17]byte +var z2604 [1 << 17]byte +var z2605 [1 << 17]byte +var z2606 [1 << 17]byte +var z2607 [1 << 17]byte +var z2608 [1 << 17]byte +var z2609 [1 << 17]byte +var z2610 [1 << 17]byte +var z2611 [1 << 17]byte +var z2612 [1 << 17]byte +var z2613 [1 << 17]byte +var z2614 [1 << 17]byte +var z2615 [1 << 17]byte +var z2616 [1 << 17]byte +var z2617 [1 << 17]byte +var z2618 [1 << 17]byte +var z2619 [1 << 17]byte +var z2620 [1 << 17]byte +var z2621 [1 << 17]byte +var z2622 [1 << 17]byte +var z2623 [1 << 17]byte +var z2624 [1 << 17]byte +var z2625 [1 << 17]byte +var z2626 [1 << 17]byte +var z2627 [1 << 17]byte +var z2628 [1 << 17]byte +var z2629 [1 << 17]byte +var z2630 [1 << 17]byte +var z2631 [1 << 17]byte +var z2632 [1 << 17]byte +var z2633 [1 << 17]byte +var z2634 [1 << 17]byte +var z2635 [1 << 17]byte +var z2636 [1 << 17]byte +var z2637 [1 << 17]byte +var z2638 [1 << 17]byte +var z2639 [1 << 17]byte +var z2640 [1 << 17]byte +var z2641 [1 << 17]byte +var z2642 [1 << 17]byte +var z2643 [1 << 17]byte +var z2644 [1 << 17]byte +var z2645 [1 << 17]byte +var z2646 [1 << 17]byte +var z2647 [1 << 17]byte +var z2648 [1 << 17]byte +var z2649 [1 << 17]byte +var z2650 [1 << 17]byte +var z2651 [1 << 17]byte +var z2652 [1 << 17]byte +var z2653 [1 << 17]byte +var z2654 [1 << 17]byte +var z2655 [1 << 17]byte +var z2656 [1 << 17]byte +var z2657 [1 << 17]byte +var z2658 [1 << 17]byte +var z2659 [1 << 17]byte +var z2660 [1 << 17]byte +var z2661 [1 << 17]byte +var z2662 [1 << 17]byte +var z2663 [1 << 17]byte +var z2664 [1 << 17]byte +var z2665 [1 << 17]byte +var z2666 [1 << 17]byte +var z2667 [1 << 17]byte +var z2668 [1 << 17]byte +var z2669 [1 << 17]byte +var z2670 [1 << 17]byte +var z2671 [1 << 17]byte +var z2672 [1 << 17]byte +var z2673 [1 << 17]byte +var z2674 [1 << 17]byte +var z2675 [1 << 17]byte +var z2676 [1 << 17]byte +var z2677 [1 << 17]byte +var z2678 [1 << 17]byte +var z2679 [1 << 17]byte +var z2680 [1 << 17]byte +var z2681 [1 << 17]byte +var z2682 [1 << 17]byte +var z2683 [1 << 17]byte +var z2684 [1 << 17]byte +var z2685 [1 << 17]byte +var z2686 [1 << 17]byte +var z2687 [1 << 17]byte +var z2688 [1 << 17]byte +var z2689 [1 << 17]byte +var z2690 [1 << 17]byte +var z2691 [1 << 17]byte +var z2692 [1 << 17]byte +var z2693 [1 << 17]byte +var z2694 [1 << 17]byte +var z2695 [1 << 17]byte +var z2696 [1 << 17]byte +var z2697 [1 << 17]byte +var z2698 [1 << 17]byte +var z2699 [1 << 17]byte +var z2700 [1 << 17]byte +var z2701 [1 << 17]byte +var z2702 [1 << 17]byte +var z2703 [1 << 17]byte +var z2704 [1 << 17]byte +var z2705 [1 << 17]byte +var z2706 [1 << 17]byte +var z2707 [1 << 17]byte +var z2708 [1 << 17]byte +var z2709 [1 << 17]byte +var z2710 [1 << 17]byte +var z2711 [1 << 17]byte +var z2712 [1 << 17]byte +var z2713 [1 << 17]byte +var z2714 [1 << 17]byte +var z2715 [1 << 17]byte +var z2716 [1 << 17]byte +var z2717 [1 << 17]byte +var z2718 [1 << 17]byte +var z2719 [1 << 17]byte +var z2720 [1 << 17]byte +var z2721 [1 << 17]byte +var z2722 [1 << 17]byte +var z2723 [1 << 17]byte +var z2724 [1 << 17]byte +var z2725 [1 << 17]byte +var z2726 [1 << 17]byte +var z2727 [1 << 17]byte +var z2728 [1 << 17]byte +var z2729 [1 << 17]byte +var z2730 [1 << 17]byte +var z2731 [1 << 17]byte +var z2732 [1 << 17]byte +var z2733 [1 << 17]byte +var z2734 [1 << 17]byte +var z2735 [1 << 17]byte +var z2736 [1 << 17]byte +var z2737 [1 << 17]byte +var z2738 [1 << 17]byte +var z2739 [1 << 17]byte +var z2740 [1 << 17]byte +var z2741 [1 << 17]byte +var z2742 [1 << 17]byte +var z2743 [1 << 17]byte +var z2744 [1 << 17]byte +var z2745 [1 << 17]byte +var z2746 [1 << 17]byte +var z2747 [1 << 17]byte +var z2748 [1 << 17]byte +var z2749 [1 << 17]byte +var z2750 [1 << 17]byte +var z2751 [1 << 17]byte +var z2752 [1 << 17]byte +var z2753 [1 << 17]byte +var z2754 [1 << 17]byte +var z2755 [1 << 17]byte +var z2756 [1 << 17]byte +var z2757 [1 << 17]byte +var z2758 [1 << 17]byte +var z2759 [1 << 17]byte +var z2760 [1 << 17]byte +var z2761 [1 << 17]byte +var z2762 [1 << 17]byte +var z2763 [1 << 17]byte +var z2764 [1 << 17]byte +var z2765 [1 << 17]byte +var z2766 [1 << 17]byte +var z2767 [1 << 17]byte +var z2768 [1 << 17]byte +var z2769 [1 << 17]byte +var z2770 [1 << 17]byte +var z2771 [1 << 17]byte +var z2772 [1 << 17]byte +var z2773 [1 << 17]byte +var z2774 [1 << 17]byte +var z2775 [1 << 17]byte +var z2776 [1 << 17]byte +var z2777 [1 << 17]byte +var z2778 [1 << 17]byte +var z2779 [1 << 17]byte +var z2780 [1 << 17]byte +var z2781 [1 << 17]byte +var z2782 [1 << 17]byte +var z2783 [1 << 17]byte +var z2784 [1 << 17]byte +var z2785 [1 << 17]byte +var z2786 [1 << 17]byte +var z2787 [1 << 17]byte +var z2788 [1 << 17]byte +var z2789 [1 << 17]byte +var z2790 [1 << 17]byte +var z2791 [1 << 17]byte +var z2792 [1 << 17]byte +var z2793 [1 << 17]byte +var z2794 [1 << 17]byte +var z2795 [1 << 17]byte +var z2796 [1 << 17]byte +var z2797 [1 << 17]byte +var z2798 [1 << 17]byte +var z2799 [1 << 17]byte +var z2800 [1 << 17]byte +var z2801 [1 << 17]byte +var z2802 [1 << 17]byte +var z2803 [1 << 17]byte +var z2804 [1 << 17]byte +var z2805 [1 << 17]byte +var z2806 [1 << 17]byte +var z2807 [1 << 17]byte +var z2808 [1 << 17]byte +var z2809 [1 << 17]byte +var z2810 [1 << 17]byte +var z2811 [1 << 17]byte +var z2812 [1 << 17]byte +var z2813 [1 << 17]byte +var z2814 [1 << 17]byte +var z2815 [1 << 17]byte +var z2816 [1 << 17]byte +var z2817 [1 << 17]byte +var z2818 [1 << 17]byte +var z2819 [1 << 17]byte +var z2820 [1 << 17]byte +var z2821 [1 << 17]byte +var z2822 [1 << 17]byte +var z2823 [1 << 17]byte +var z2824 [1 << 17]byte +var z2825 [1 << 17]byte +var z2826 [1 << 17]byte +var z2827 [1 << 17]byte +var z2828 [1 << 17]byte +var z2829 [1 << 17]byte +var z2830 [1 << 17]byte +var z2831 [1 << 17]byte +var z2832 [1 << 17]byte +var z2833 [1 << 17]byte +var z2834 [1 << 17]byte +var z2835 [1 << 17]byte +var z2836 [1 << 17]byte +var z2837 [1 << 17]byte +var z2838 [1 << 17]byte +var z2839 [1 << 17]byte +var z2840 [1 << 17]byte +var z2841 [1 << 17]byte +var z2842 [1 << 17]byte +var z2843 [1 << 17]byte +var z2844 [1 << 17]byte +var z2845 [1 << 17]byte +var z2846 [1 << 17]byte +var z2847 [1 << 17]byte +var z2848 [1 << 17]byte +var z2849 [1 << 17]byte +var z2850 [1 << 17]byte +var z2851 [1 << 17]byte +var z2852 [1 << 17]byte +var z2853 [1 << 17]byte +var z2854 [1 << 17]byte +var z2855 [1 << 17]byte +var z2856 [1 << 17]byte +var z2857 [1 << 17]byte +var z2858 [1 << 17]byte +var z2859 [1 << 17]byte +var z2860 [1 << 17]byte +var z2861 [1 << 17]byte +var z2862 [1 << 17]byte +var z2863 [1 << 17]byte +var z2864 [1 << 17]byte +var z2865 [1 << 17]byte +var z2866 [1 << 17]byte +var z2867 [1 << 17]byte +var z2868 [1 << 17]byte +var z2869 [1 << 17]byte +var z2870 [1 << 17]byte +var z2871 [1 << 17]byte +var z2872 [1 << 17]byte +var z2873 [1 << 17]byte +var z2874 [1 << 17]byte +var z2875 [1 << 17]byte +var z2876 [1 << 17]byte +var z2877 [1 << 17]byte +var z2878 [1 << 17]byte +var z2879 [1 << 17]byte +var z2880 [1 << 17]byte +var z2881 [1 << 17]byte +var z2882 [1 << 17]byte +var z2883 [1 << 17]byte +var z2884 [1 << 17]byte +var z2885 [1 << 17]byte +var z2886 [1 << 17]byte +var z2887 [1 << 17]byte +var z2888 [1 << 17]byte +var z2889 [1 << 17]byte +var z2890 [1 << 17]byte +var z2891 [1 << 17]byte +var z2892 [1 << 17]byte +var z2893 [1 << 17]byte +var z2894 [1 << 17]byte +var z2895 [1 << 17]byte +var z2896 [1 << 17]byte +var z2897 [1 << 17]byte +var z2898 [1 << 17]byte +var z2899 [1 << 17]byte +var z2900 [1 << 17]byte +var z2901 [1 << 17]byte +var z2902 [1 << 17]byte +var z2903 [1 << 17]byte +var z2904 [1 << 17]byte +var z2905 [1 << 17]byte +var z2906 [1 << 17]byte +var z2907 [1 << 17]byte +var z2908 [1 << 17]byte +var z2909 [1 << 17]byte +var z2910 [1 << 17]byte +var z2911 [1 << 17]byte +var z2912 [1 << 17]byte +var z2913 [1 << 17]byte +var z2914 [1 << 17]byte +var z2915 [1 << 17]byte +var z2916 [1 << 17]byte +var z2917 [1 << 17]byte +var z2918 [1 << 17]byte +var z2919 [1 << 17]byte +var z2920 [1 << 17]byte +var z2921 [1 << 17]byte +var z2922 [1 << 17]byte +var z2923 [1 << 17]byte +var z2924 [1 << 17]byte +var z2925 [1 << 17]byte +var z2926 [1 << 17]byte +var z2927 [1 << 17]byte +var z2928 [1 << 17]byte +var z2929 [1 << 17]byte +var z2930 [1 << 17]byte +var z2931 [1 << 17]byte +var z2932 [1 << 17]byte +var z2933 [1 << 17]byte +var z2934 [1 << 17]byte +var z2935 [1 << 17]byte +var z2936 [1 << 17]byte +var z2937 [1 << 17]byte +var z2938 [1 << 17]byte +var z2939 [1 << 17]byte +var z2940 [1 << 17]byte +var z2941 [1 << 17]byte +var z2942 [1 << 17]byte +var z2943 [1 << 17]byte +var z2944 [1 << 17]byte +var z2945 [1 << 17]byte +var z2946 [1 << 17]byte +var z2947 [1 << 17]byte +var z2948 [1 << 17]byte +var z2949 [1 << 17]byte +var z2950 [1 << 17]byte +var z2951 [1 << 17]byte +var z2952 [1 << 17]byte +var z2953 [1 << 17]byte +var z2954 [1 << 17]byte +var z2955 [1 << 17]byte +var z2956 [1 << 17]byte +var z2957 [1 << 17]byte +var z2958 [1 << 17]byte +var z2959 [1 << 17]byte +var z2960 [1 << 17]byte +var z2961 [1 << 17]byte +var z2962 [1 << 17]byte +var z2963 [1 << 17]byte +var z2964 [1 << 17]byte +var z2965 [1 << 17]byte +var z2966 [1 << 17]byte +var z2967 [1 << 17]byte +var z2968 [1 << 17]byte +var z2969 [1 << 17]byte +var z2970 [1 << 17]byte +var z2971 [1 << 17]byte +var z2972 [1 << 17]byte +var z2973 [1 << 17]byte +var z2974 [1 << 17]byte +var z2975 [1 << 17]byte +var z2976 [1 << 17]byte +var z2977 [1 << 17]byte +var z2978 [1 << 17]byte +var z2979 [1 << 17]byte +var z2980 [1 << 17]byte +var z2981 [1 << 17]byte +var z2982 [1 << 17]byte +var z2983 [1 << 17]byte +var z2984 [1 << 17]byte +var z2985 [1 << 17]byte +var z2986 [1 << 17]byte +var z2987 [1 << 17]byte +var z2988 [1 << 17]byte +var z2989 [1 << 17]byte +var z2990 [1 << 17]byte +var z2991 [1 << 17]byte +var z2992 [1 << 17]byte +var z2993 [1 << 17]byte +var z2994 [1 << 17]byte +var z2995 [1 << 17]byte +var z2996 [1 << 17]byte +var z2997 [1 << 17]byte +var z2998 [1 << 17]byte +var z2999 [1 << 17]byte +var z3000 [1 << 17]byte +var z3001 [1 << 17]byte +var z3002 [1 << 17]byte +var z3003 [1 << 17]byte +var z3004 [1 << 17]byte +var z3005 [1 << 17]byte +var z3006 [1 << 17]byte +var z3007 [1 << 17]byte +var z3008 [1 << 17]byte +var z3009 [1 << 17]byte +var z3010 [1 << 17]byte +var z3011 [1 << 17]byte +var z3012 [1 << 17]byte +var z3013 [1 << 17]byte +var z3014 [1 << 17]byte +var z3015 [1 << 17]byte +var z3016 [1 << 17]byte +var z3017 [1 << 17]byte +var z3018 [1 << 17]byte +var z3019 [1 << 17]byte +var z3020 [1 << 17]byte +var z3021 [1 << 17]byte +var z3022 [1 << 17]byte +var z3023 [1 << 17]byte +var z3024 [1 << 17]byte +var z3025 [1 << 17]byte +var z3026 [1 << 17]byte +var z3027 [1 << 17]byte +var z3028 [1 << 17]byte +var z3029 [1 << 17]byte +var z3030 [1 << 17]byte +var z3031 [1 << 17]byte +var z3032 [1 << 17]byte +var z3033 [1 << 17]byte +var z3034 [1 << 17]byte +var z3035 [1 << 17]byte +var z3036 [1 << 17]byte +var z3037 [1 << 17]byte +var z3038 [1 << 17]byte +var z3039 [1 << 17]byte +var z3040 [1 << 17]byte +var z3041 [1 << 17]byte +var z3042 [1 << 17]byte +var z3043 [1 << 17]byte +var z3044 [1 << 17]byte +var z3045 [1 << 17]byte +var z3046 [1 << 17]byte +var z3047 [1 << 17]byte +var z3048 [1 << 17]byte +var z3049 [1 << 17]byte +var z3050 [1 << 17]byte +var z3051 [1 << 17]byte +var z3052 [1 << 17]byte +var z3053 [1 << 17]byte +var z3054 [1 << 17]byte +var z3055 [1 << 17]byte +var z3056 [1 << 17]byte +var z3057 [1 << 17]byte +var z3058 [1 << 17]byte +var z3059 [1 << 17]byte +var z3060 [1 << 17]byte +var z3061 [1 << 17]byte +var z3062 [1 << 17]byte +var z3063 [1 << 17]byte +var z3064 [1 << 17]byte +var z3065 [1 << 17]byte +var z3066 [1 << 17]byte +var z3067 [1 << 17]byte +var z3068 [1 << 17]byte +var z3069 [1 << 17]byte +var z3070 [1 << 17]byte +var z3071 [1 << 17]byte +var z3072 [1 << 17]byte +var z3073 [1 << 17]byte +var z3074 [1 << 17]byte +var z3075 [1 << 17]byte +var z3076 [1 << 17]byte +var z3077 [1 << 17]byte +var z3078 [1 << 17]byte +var z3079 [1 << 17]byte +var z3080 [1 << 17]byte +var z3081 [1 << 17]byte +var z3082 [1 << 17]byte +var z3083 [1 << 17]byte +var z3084 [1 << 17]byte +var z3085 [1 << 17]byte +var z3086 [1 << 17]byte +var z3087 [1 << 17]byte +var z3088 [1 << 17]byte +var z3089 [1 << 17]byte +var z3090 [1 << 17]byte +var z3091 [1 << 17]byte +var z3092 [1 << 17]byte +var z3093 [1 << 17]byte +var z3094 [1 << 17]byte +var z3095 [1 << 17]byte +var z3096 [1 << 17]byte +var z3097 [1 << 17]byte +var z3098 [1 << 17]byte +var z3099 [1 << 17]byte +var z3100 [1 << 17]byte +var z3101 [1 << 17]byte +var z3102 [1 << 17]byte +var z3103 [1 << 17]byte +var z3104 [1 << 17]byte +var z3105 [1 << 17]byte +var z3106 [1 << 17]byte +var z3107 [1 << 17]byte +var z3108 [1 << 17]byte +var z3109 [1 << 17]byte +var z3110 [1 << 17]byte +var z3111 [1 << 17]byte +var z3112 [1 << 17]byte +var z3113 [1 << 17]byte +var z3114 [1 << 17]byte +var z3115 [1 << 17]byte +var z3116 [1 << 17]byte +var z3117 [1 << 17]byte +var z3118 [1 << 17]byte +var z3119 [1 << 17]byte +var z3120 [1 << 17]byte +var z3121 [1 << 17]byte +var z3122 [1 << 17]byte +var z3123 [1 << 17]byte +var z3124 [1 << 17]byte +var z3125 [1 << 17]byte +var z3126 [1 << 17]byte +var z3127 [1 << 17]byte +var z3128 [1 << 17]byte +var z3129 [1 << 17]byte +var z3130 [1 << 17]byte +var z3131 [1 << 17]byte +var z3132 [1 << 17]byte +var z3133 [1 << 17]byte +var z3134 [1 << 17]byte +var z3135 [1 << 17]byte +var z3136 [1 << 17]byte +var z3137 [1 << 17]byte +var z3138 [1 << 17]byte +var z3139 [1 << 17]byte +var z3140 [1 << 17]byte +var z3141 [1 << 17]byte +var z3142 [1 << 17]byte +var z3143 [1 << 17]byte +var z3144 [1 << 17]byte +var z3145 [1 << 17]byte +var z3146 [1 << 17]byte +var z3147 [1 << 17]byte +var z3148 [1 << 17]byte +var z3149 [1 << 17]byte +var z3150 [1 << 17]byte +var z3151 [1 << 17]byte +var z3152 [1 << 17]byte +var z3153 [1 << 17]byte +var z3154 [1 << 17]byte +var z3155 [1 << 17]byte +var z3156 [1 << 17]byte +var z3157 [1 << 17]byte +var z3158 [1 << 17]byte +var z3159 [1 << 17]byte +var z3160 [1 << 17]byte +var z3161 [1 << 17]byte +var z3162 [1 << 17]byte +var z3163 [1 << 17]byte +var z3164 [1 << 17]byte +var z3165 [1 << 17]byte +var z3166 [1 << 17]byte +var z3167 [1 << 17]byte +var z3168 [1 << 17]byte +var z3169 [1 << 17]byte +var z3170 [1 << 17]byte +var z3171 [1 << 17]byte +var z3172 [1 << 17]byte +var z3173 [1 << 17]byte +var z3174 [1 << 17]byte +var z3175 [1 << 17]byte +var z3176 [1 << 17]byte +var z3177 [1 << 17]byte +var z3178 [1 << 17]byte +var z3179 [1 << 17]byte +var z3180 [1 << 17]byte +var z3181 [1 << 17]byte +var z3182 [1 << 17]byte +var z3183 [1 << 17]byte +var z3184 [1 << 17]byte +var z3185 [1 << 17]byte +var z3186 [1 << 17]byte +var z3187 [1 << 17]byte +var z3188 [1 << 17]byte +var z3189 [1 << 17]byte +var z3190 [1 << 17]byte +var z3191 [1 << 17]byte +var z3192 [1 << 17]byte +var z3193 [1 << 17]byte +var z3194 [1 << 17]byte +var z3195 [1 << 17]byte +var z3196 [1 << 17]byte +var z3197 [1 << 17]byte +var z3198 [1 << 17]byte +var z3199 [1 << 17]byte +var z3200 [1 << 17]byte +var z3201 [1 << 17]byte +var z3202 [1 << 17]byte +var z3203 [1 << 17]byte +var z3204 [1 << 17]byte +var z3205 [1 << 17]byte +var z3206 [1 << 17]byte +var z3207 [1 << 17]byte +var z3208 [1 << 17]byte +var z3209 [1 << 17]byte +var z3210 [1 << 17]byte +var z3211 [1 << 17]byte +var z3212 [1 << 17]byte +var z3213 [1 << 17]byte +var z3214 [1 << 17]byte +var z3215 [1 << 17]byte +var z3216 [1 << 17]byte +var z3217 [1 << 17]byte +var z3218 [1 << 17]byte +var z3219 [1 << 17]byte +var z3220 [1 << 17]byte +var z3221 [1 << 17]byte +var z3222 [1 << 17]byte +var z3223 [1 << 17]byte +var z3224 [1 << 17]byte +var z3225 [1 << 17]byte +var z3226 [1 << 17]byte +var z3227 [1 << 17]byte +var z3228 [1 << 17]byte +var z3229 [1 << 17]byte +var z3230 [1 << 17]byte +var z3231 [1 << 17]byte +var z3232 [1 << 17]byte +var z3233 [1 << 17]byte +var z3234 [1 << 17]byte +var z3235 [1 << 17]byte +var z3236 [1 << 17]byte +var z3237 [1 << 17]byte +var z3238 [1 << 17]byte +var z3239 [1 << 17]byte +var z3240 [1 << 17]byte +var z3241 [1 << 17]byte +var z3242 [1 << 17]byte +var z3243 [1 << 17]byte +var z3244 [1 << 17]byte +var z3245 [1 << 17]byte +var z3246 [1 << 17]byte +var z3247 [1 << 17]byte +var z3248 [1 << 17]byte +var z3249 [1 << 17]byte +var z3250 [1 << 17]byte +var z3251 [1 << 17]byte +var z3252 [1 << 17]byte +var z3253 [1 << 17]byte +var z3254 [1 << 17]byte +var z3255 [1 << 17]byte +var z3256 [1 << 17]byte +var z3257 [1 << 17]byte +var z3258 [1 << 17]byte +var z3259 [1 << 17]byte +var z3260 [1 << 17]byte +var z3261 [1 << 17]byte +var z3262 [1 << 17]byte +var z3263 [1 << 17]byte +var z3264 [1 << 17]byte +var z3265 [1 << 17]byte +var z3266 [1 << 17]byte +var z3267 [1 << 17]byte +var z3268 [1 << 17]byte +var z3269 [1 << 17]byte +var z3270 [1 << 17]byte +var z3271 [1 << 17]byte +var z3272 [1 << 17]byte +var z3273 [1 << 17]byte +var z3274 [1 << 17]byte +var z3275 [1 << 17]byte +var z3276 [1 << 17]byte +var z3277 [1 << 17]byte +var z3278 [1 << 17]byte +var z3279 [1 << 17]byte +var z3280 [1 << 17]byte +var z3281 [1 << 17]byte +var z3282 [1 << 17]byte +var z3283 [1 << 17]byte +var z3284 [1 << 17]byte +var z3285 [1 << 17]byte +var z3286 [1 << 17]byte +var z3287 [1 << 17]byte +var z3288 [1 << 17]byte +var z3289 [1 << 17]byte +var z3290 [1 << 17]byte +var z3291 [1 << 17]byte +var z3292 [1 << 17]byte +var z3293 [1 << 17]byte +var z3294 [1 << 17]byte +var z3295 [1 << 17]byte +var z3296 [1 << 17]byte +var z3297 [1 << 17]byte +var z3298 [1 << 17]byte +var z3299 [1 << 17]byte +var z3300 [1 << 17]byte +var z3301 [1 << 17]byte +var z3302 [1 << 17]byte +var z3303 [1 << 17]byte +var z3304 [1 << 17]byte +var z3305 [1 << 17]byte +var z3306 [1 << 17]byte +var z3307 [1 << 17]byte +var z3308 [1 << 17]byte +var z3309 [1 << 17]byte +var z3310 [1 << 17]byte +var z3311 [1 << 17]byte +var z3312 [1 << 17]byte +var z3313 [1 << 17]byte +var z3314 [1 << 17]byte +var z3315 [1 << 17]byte +var z3316 [1 << 17]byte +var z3317 [1 << 17]byte +var z3318 [1 << 17]byte +var z3319 [1 << 17]byte +var z3320 [1 << 17]byte +var z3321 [1 << 17]byte +var z3322 [1 << 17]byte +var z3323 [1 << 17]byte +var z3324 [1 << 17]byte +var z3325 [1 << 17]byte +var z3326 [1 << 17]byte +var z3327 [1 << 17]byte +var z3328 [1 << 17]byte +var z3329 [1 << 17]byte +var z3330 [1 << 17]byte +var z3331 [1 << 17]byte +var z3332 [1 << 17]byte +var z3333 [1 << 17]byte +var z3334 [1 << 17]byte +var z3335 [1 << 17]byte +var z3336 [1 << 17]byte +var z3337 [1 << 17]byte +var z3338 [1 << 17]byte +var z3339 [1 << 17]byte +var z3340 [1 << 17]byte +var z3341 [1 << 17]byte +var z3342 [1 << 17]byte +var z3343 [1 << 17]byte +var z3344 [1 << 17]byte +var z3345 [1 << 17]byte +var z3346 [1 << 17]byte +var z3347 [1 << 17]byte +var z3348 [1 << 17]byte +var z3349 [1 << 17]byte +var z3350 [1 << 17]byte +var z3351 [1 << 17]byte +var z3352 [1 << 17]byte +var z3353 [1 << 17]byte +var z3354 [1 << 17]byte +var z3355 [1 << 17]byte +var z3356 [1 << 17]byte +var z3357 [1 << 17]byte +var z3358 [1 << 17]byte +var z3359 [1 << 17]byte +var z3360 [1 << 17]byte +var z3361 [1 << 17]byte +var z3362 [1 << 17]byte +var z3363 [1 << 17]byte +var z3364 [1 << 17]byte +var z3365 [1 << 17]byte +var z3366 [1 << 17]byte +var z3367 [1 << 17]byte +var z3368 [1 << 17]byte +var z3369 [1 << 17]byte +var z3370 [1 << 17]byte +var z3371 [1 << 17]byte +var z3372 [1 << 17]byte +var z3373 [1 << 17]byte +var z3374 [1 << 17]byte +var z3375 [1 << 17]byte +var z3376 [1 << 17]byte +var z3377 [1 << 17]byte +var z3378 [1 << 17]byte +var z3379 [1 << 17]byte +var z3380 [1 << 17]byte +var z3381 [1 << 17]byte +var z3382 [1 << 17]byte +var z3383 [1 << 17]byte +var z3384 [1 << 17]byte +var z3385 [1 << 17]byte +var z3386 [1 << 17]byte +var z3387 [1 << 17]byte +var z3388 [1 << 17]byte +var z3389 [1 << 17]byte +var z3390 [1 << 17]byte +var z3391 [1 << 17]byte +var z3392 [1 << 17]byte +var z3393 [1 << 17]byte +var z3394 [1 << 17]byte +var z3395 [1 << 17]byte +var z3396 [1 << 17]byte +var z3397 [1 << 17]byte +var z3398 [1 << 17]byte +var z3399 [1 << 17]byte +var z3400 [1 << 17]byte +var z3401 [1 << 17]byte +var z3402 [1 << 17]byte +var z3403 [1 << 17]byte +var z3404 [1 << 17]byte +var z3405 [1 << 17]byte +var z3406 [1 << 17]byte +var z3407 [1 << 17]byte +var z3408 [1 << 17]byte +var z3409 [1 << 17]byte +var z3410 [1 << 17]byte +var z3411 [1 << 17]byte +var z3412 [1 << 17]byte +var z3413 [1 << 17]byte +var z3414 [1 << 17]byte +var z3415 [1 << 17]byte +var z3416 [1 << 17]byte +var z3417 [1 << 17]byte +var z3418 [1 << 17]byte +var z3419 [1 << 17]byte +var z3420 [1 << 17]byte +var z3421 [1 << 17]byte +var z3422 [1 << 17]byte +var z3423 [1 << 17]byte +var z3424 [1 << 17]byte +var z3425 [1 << 17]byte +var z3426 [1 << 17]byte +var z3427 [1 << 17]byte +var z3428 [1 << 17]byte +var z3429 [1 << 17]byte +var z3430 [1 << 17]byte +var z3431 [1 << 17]byte +var z3432 [1 << 17]byte +var z3433 [1 << 17]byte +var z3434 [1 << 17]byte +var z3435 [1 << 17]byte +var z3436 [1 << 17]byte +var z3437 [1 << 17]byte +var z3438 [1 << 17]byte +var z3439 [1 << 17]byte +var z3440 [1 << 17]byte +var z3441 [1 << 17]byte +var z3442 [1 << 17]byte +var z3443 [1 << 17]byte +var z3444 [1 << 17]byte +var z3445 [1 << 17]byte +var z3446 [1 << 17]byte +var z3447 [1 << 17]byte +var z3448 [1 << 17]byte +var z3449 [1 << 17]byte +var z3450 [1 << 17]byte +var z3451 [1 << 17]byte +var z3452 [1 << 17]byte +var z3453 [1 << 17]byte +var z3454 [1 << 17]byte +var z3455 [1 << 17]byte +var z3456 [1 << 17]byte +var z3457 [1 << 17]byte +var z3458 [1 << 17]byte +var z3459 [1 << 17]byte +var z3460 [1 << 17]byte +var z3461 [1 << 17]byte +var z3462 [1 << 17]byte +var z3463 [1 << 17]byte +var z3464 [1 << 17]byte +var z3465 [1 << 17]byte +var z3466 [1 << 17]byte +var z3467 [1 << 17]byte +var z3468 [1 << 17]byte +var z3469 [1 << 17]byte +var z3470 [1 << 17]byte +var z3471 [1 << 17]byte +var z3472 [1 << 17]byte +var z3473 [1 << 17]byte +var z3474 [1 << 17]byte +var z3475 [1 << 17]byte +var z3476 [1 << 17]byte +var z3477 [1 << 17]byte +var z3478 [1 << 17]byte +var z3479 [1 << 17]byte +var z3480 [1 << 17]byte +var z3481 [1 << 17]byte +var z3482 [1 << 17]byte +var z3483 [1 << 17]byte +var z3484 [1 << 17]byte +var z3485 [1 << 17]byte +var z3486 [1 << 17]byte +var z3487 [1 << 17]byte +var z3488 [1 << 17]byte +var z3489 [1 << 17]byte +var z3490 [1 << 17]byte +var z3491 [1 << 17]byte +var z3492 [1 << 17]byte +var z3493 [1 << 17]byte +var z3494 [1 << 17]byte +var z3495 [1 << 17]byte +var z3496 [1 << 17]byte +var z3497 [1 << 17]byte +var z3498 [1 << 17]byte +var z3499 [1 << 17]byte +var z3500 [1 << 17]byte +var z3501 [1 << 17]byte +var z3502 [1 << 17]byte +var z3503 [1 << 17]byte +var z3504 [1 << 17]byte +var z3505 [1 << 17]byte +var z3506 [1 << 17]byte +var z3507 [1 << 17]byte +var z3508 [1 << 17]byte +var z3509 [1 << 17]byte +var z3510 [1 << 17]byte +var z3511 [1 << 17]byte +var z3512 [1 << 17]byte +var z3513 [1 << 17]byte +var z3514 [1 << 17]byte +var z3515 [1 << 17]byte +var z3516 [1 << 17]byte +var z3517 [1 << 17]byte +var z3518 [1 << 17]byte +var z3519 [1 << 17]byte +var z3520 [1 << 17]byte +var z3521 [1 << 17]byte +var z3522 [1 << 17]byte +var z3523 [1 << 17]byte +var z3524 [1 << 17]byte +var z3525 [1 << 17]byte +var z3526 [1 << 17]byte +var z3527 [1 << 17]byte +var z3528 [1 << 17]byte +var z3529 [1 << 17]byte +var z3530 [1 << 17]byte +var z3531 [1 << 17]byte +var z3532 [1 << 17]byte +var z3533 [1 << 17]byte +var z3534 [1 << 17]byte +var z3535 [1 << 17]byte +var z3536 [1 << 17]byte +var z3537 [1 << 17]byte +var z3538 [1 << 17]byte +var z3539 [1 << 17]byte +var z3540 [1 << 17]byte +var z3541 [1 << 17]byte +var z3542 [1 << 17]byte +var z3543 [1 << 17]byte +var z3544 [1 << 17]byte +var z3545 [1 << 17]byte +var z3546 [1 << 17]byte +var z3547 [1 << 17]byte +var z3548 [1 << 17]byte +var z3549 [1 << 17]byte +var z3550 [1 << 17]byte +var z3551 [1 << 17]byte +var z3552 [1 << 17]byte +var z3553 [1 << 17]byte +var z3554 [1 << 17]byte +var z3555 [1 << 17]byte +var z3556 [1 << 17]byte +var z3557 [1 << 17]byte +var z3558 [1 << 17]byte +var z3559 [1 << 17]byte +var z3560 [1 << 17]byte +var z3561 [1 << 17]byte +var z3562 [1 << 17]byte +var z3563 [1 << 17]byte +var z3564 [1 << 17]byte +var z3565 [1 << 17]byte +var z3566 [1 << 17]byte +var z3567 [1 << 17]byte +var z3568 [1 << 17]byte +var z3569 [1 << 17]byte +var z3570 [1 << 17]byte +var z3571 [1 << 17]byte +var z3572 [1 << 17]byte +var z3573 [1 << 17]byte +var z3574 [1 << 17]byte +var z3575 [1 << 17]byte +var z3576 [1 << 17]byte +var z3577 [1 << 17]byte +var z3578 [1 << 17]byte +var z3579 [1 << 17]byte +var z3580 [1 << 17]byte +var z3581 [1 << 17]byte +var z3582 [1 << 17]byte +var z3583 [1 << 17]byte +var z3584 [1 << 17]byte +var z3585 [1 << 17]byte +var z3586 [1 << 17]byte +var z3587 [1 << 17]byte +var z3588 [1 << 17]byte +var z3589 [1 << 17]byte +var z3590 [1 << 17]byte +var z3591 [1 << 17]byte +var z3592 [1 << 17]byte +var z3593 [1 << 17]byte +var z3594 [1 << 17]byte +var z3595 [1 << 17]byte +var z3596 [1 << 17]byte +var z3597 [1 << 17]byte +var z3598 [1 << 17]byte +var z3599 [1 << 17]byte +var z3600 [1 << 17]byte +var z3601 [1 << 17]byte +var z3602 [1 << 17]byte +var z3603 [1 << 17]byte +var z3604 [1 << 17]byte +var z3605 [1 << 17]byte +var z3606 [1 << 17]byte +var z3607 [1 << 17]byte +var z3608 [1 << 17]byte +var z3609 [1 << 17]byte +var z3610 [1 << 17]byte +var z3611 [1 << 17]byte +var z3612 [1 << 17]byte +var z3613 [1 << 17]byte +var z3614 [1 << 17]byte +var z3615 [1 << 17]byte +var z3616 [1 << 17]byte +var z3617 [1 << 17]byte +var z3618 [1 << 17]byte +var z3619 [1 << 17]byte +var z3620 [1 << 17]byte +var z3621 [1 << 17]byte +var z3622 [1 << 17]byte +var z3623 [1 << 17]byte +var z3624 [1 << 17]byte +var z3625 [1 << 17]byte +var z3626 [1 << 17]byte +var z3627 [1 << 17]byte +var z3628 [1 << 17]byte +var z3629 [1 << 17]byte +var z3630 [1 << 17]byte +var z3631 [1 << 17]byte +var z3632 [1 << 17]byte +var z3633 [1 << 17]byte +var z3634 [1 << 17]byte +var z3635 [1 << 17]byte +var z3636 [1 << 17]byte +var z3637 [1 << 17]byte +var z3638 [1 << 17]byte +var z3639 [1 << 17]byte +var z3640 [1 << 17]byte +var z3641 [1 << 17]byte +var z3642 [1 << 17]byte +var z3643 [1 << 17]byte +var z3644 [1 << 17]byte +var z3645 [1 << 17]byte +var z3646 [1 << 17]byte +var z3647 [1 << 17]byte +var z3648 [1 << 17]byte +var z3649 [1 << 17]byte +var z3650 [1 << 17]byte +var z3651 [1 << 17]byte +var z3652 [1 << 17]byte +var z3653 [1 << 17]byte +var z3654 [1 << 17]byte +var z3655 [1 << 17]byte +var z3656 [1 << 17]byte +var z3657 [1 << 17]byte +var z3658 [1 << 17]byte +var z3659 [1 << 17]byte +var z3660 [1 << 17]byte +var z3661 [1 << 17]byte +var z3662 [1 << 17]byte +var z3663 [1 << 17]byte +var z3664 [1 << 17]byte +var z3665 [1 << 17]byte +var z3666 [1 << 17]byte +var z3667 [1 << 17]byte +var z3668 [1 << 17]byte +var z3669 [1 << 17]byte +var z3670 [1 << 17]byte +var z3671 [1 << 17]byte +var z3672 [1 << 17]byte +var z3673 [1 << 17]byte +var z3674 [1 << 17]byte +var z3675 [1 << 17]byte +var z3676 [1 << 17]byte +var z3677 [1 << 17]byte +var z3678 [1 << 17]byte +var z3679 [1 << 17]byte +var z3680 [1 << 17]byte +var z3681 [1 << 17]byte +var z3682 [1 << 17]byte +var z3683 [1 << 17]byte +var z3684 [1 << 17]byte +var z3685 [1 << 17]byte +var z3686 [1 << 17]byte +var z3687 [1 << 17]byte +var z3688 [1 << 17]byte +var z3689 [1 << 17]byte +var z3690 [1 << 17]byte +var z3691 [1 << 17]byte +var z3692 [1 << 17]byte +var z3693 [1 << 17]byte +var z3694 [1 << 17]byte +var z3695 [1 << 17]byte +var z3696 [1 << 17]byte +var z3697 [1 << 17]byte +var z3698 [1 << 17]byte +var z3699 [1 << 17]byte +var z3700 [1 << 17]byte +var z3701 [1 << 17]byte +var z3702 [1 << 17]byte +var z3703 [1 << 17]byte +var z3704 [1 << 17]byte +var z3705 [1 << 17]byte +var z3706 [1 << 17]byte +var z3707 [1 << 17]byte +var z3708 [1 << 17]byte +var z3709 [1 << 17]byte +var z3710 [1 << 17]byte +var z3711 [1 << 17]byte +var z3712 [1 << 17]byte +var z3713 [1 << 17]byte +var z3714 [1 << 17]byte +var z3715 [1 << 17]byte +var z3716 [1 << 17]byte +var z3717 [1 << 17]byte +var z3718 [1 << 17]byte +var z3719 [1 << 17]byte +var z3720 [1 << 17]byte +var z3721 [1 << 17]byte +var z3722 [1 << 17]byte +var z3723 [1 << 17]byte +var z3724 [1 << 17]byte +var z3725 [1 << 17]byte +var z3726 [1 << 17]byte +var z3727 [1 << 17]byte +var z3728 [1 << 17]byte +var z3729 [1 << 17]byte +var z3730 [1 << 17]byte +var z3731 [1 << 17]byte +var z3732 [1 << 17]byte +var z3733 [1 << 17]byte +var z3734 [1 << 17]byte +var z3735 [1 << 17]byte +var z3736 [1 << 17]byte +var z3737 [1 << 17]byte +var z3738 [1 << 17]byte +var z3739 [1 << 17]byte +var z3740 [1 << 17]byte +var z3741 [1 << 17]byte +var z3742 [1 << 17]byte +var z3743 [1 << 17]byte +var z3744 [1 << 17]byte +var z3745 [1 << 17]byte +var z3746 [1 << 17]byte +var z3747 [1 << 17]byte +var z3748 [1 << 17]byte +var z3749 [1 << 17]byte +var z3750 [1 << 17]byte +var z3751 [1 << 17]byte +var z3752 [1 << 17]byte +var z3753 [1 << 17]byte +var z3754 [1 << 17]byte +var z3755 [1 << 17]byte +var z3756 [1 << 17]byte +var z3757 [1 << 17]byte +var z3758 [1 << 17]byte +var z3759 [1 << 17]byte +var z3760 [1 << 17]byte +var z3761 [1 << 17]byte +var z3762 [1 << 17]byte +var z3763 [1 << 17]byte +var z3764 [1 << 17]byte +var z3765 [1 << 17]byte +var z3766 [1 << 17]byte +var z3767 [1 << 17]byte +var z3768 [1 << 17]byte +var z3769 [1 << 17]byte +var z3770 [1 << 17]byte +var z3771 [1 << 17]byte +var z3772 [1 << 17]byte +var z3773 [1 << 17]byte +var z3774 [1 << 17]byte +var z3775 [1 << 17]byte +var z3776 [1 << 17]byte +var z3777 [1 << 17]byte +var z3778 [1 << 17]byte +var z3779 [1 << 17]byte +var z3780 [1 << 17]byte +var z3781 [1 << 17]byte +var z3782 [1 << 17]byte +var z3783 [1 << 17]byte +var z3784 [1 << 17]byte +var z3785 [1 << 17]byte +var z3786 [1 << 17]byte +var z3787 [1 << 17]byte +var z3788 [1 << 17]byte +var z3789 [1 << 17]byte +var z3790 [1 << 17]byte +var z3791 [1 << 17]byte +var z3792 [1 << 17]byte +var z3793 [1 << 17]byte +var z3794 [1 << 17]byte +var z3795 [1 << 17]byte +var z3796 [1 << 17]byte +var z3797 [1 << 17]byte +var z3798 [1 << 17]byte +var z3799 [1 << 17]byte +var z3800 [1 << 17]byte +var z3801 [1 << 17]byte +var z3802 [1 << 17]byte +var z3803 [1 << 17]byte +var z3804 [1 << 17]byte +var z3805 [1 << 17]byte +var z3806 [1 << 17]byte +var z3807 [1 << 17]byte +var z3808 [1 << 17]byte +var z3809 [1 << 17]byte +var z3810 [1 << 17]byte +var z3811 [1 << 17]byte +var z3812 [1 << 17]byte +var z3813 [1 << 17]byte +var z3814 [1 << 17]byte +var z3815 [1 << 17]byte +var z3816 [1 << 17]byte +var z3817 [1 << 17]byte +var z3818 [1 << 17]byte +var z3819 [1 << 17]byte +var z3820 [1 << 17]byte +var z3821 [1 << 17]byte +var z3822 [1 << 17]byte +var z3823 [1 << 17]byte +var z3824 [1 << 17]byte +var z3825 [1 << 17]byte +var z3826 [1 << 17]byte +var z3827 [1 << 17]byte +var z3828 [1 << 17]byte +var z3829 [1 << 17]byte +var z3830 [1 << 17]byte +var z3831 [1 << 17]byte +var z3832 [1 << 17]byte +var z3833 [1 << 17]byte +var z3834 [1 << 17]byte +var z3835 [1 << 17]byte +var z3836 [1 << 17]byte +var z3837 [1 << 17]byte +var z3838 [1 << 17]byte +var z3839 [1 << 17]byte +var z3840 [1 << 17]byte +var z3841 [1 << 17]byte +var z3842 [1 << 17]byte +var z3843 [1 << 17]byte +var z3844 [1 << 17]byte +var z3845 [1 << 17]byte +var z3846 [1 << 17]byte +var z3847 [1 << 17]byte +var z3848 [1 << 17]byte +var z3849 [1 << 17]byte +var z3850 [1 << 17]byte +var z3851 [1 << 17]byte +var z3852 [1 << 17]byte +var z3853 [1 << 17]byte +var z3854 [1 << 17]byte +var z3855 [1 << 17]byte +var z3856 [1 << 17]byte +var z3857 [1 << 17]byte +var z3858 [1 << 17]byte +var z3859 [1 << 17]byte +var z3860 [1 << 17]byte +var z3861 [1 << 17]byte +var z3862 [1 << 17]byte +var z3863 [1 << 17]byte +var z3864 [1 << 17]byte +var z3865 [1 << 17]byte +var z3866 [1 << 17]byte +var z3867 [1 << 17]byte +var z3868 [1 << 17]byte +var z3869 [1 << 17]byte +var z3870 [1 << 17]byte +var z3871 [1 << 17]byte +var z3872 [1 << 17]byte +var z3873 [1 << 17]byte +var z3874 [1 << 17]byte +var z3875 [1 << 17]byte +var z3876 [1 << 17]byte +var z3877 [1 << 17]byte +var z3878 [1 << 17]byte +var z3879 [1 << 17]byte +var z3880 [1 << 17]byte +var z3881 [1 << 17]byte +var z3882 [1 << 17]byte +var z3883 [1 << 17]byte +var z3884 [1 << 17]byte +var z3885 [1 << 17]byte +var z3886 [1 << 17]byte +var z3887 [1 << 17]byte +var z3888 [1 << 17]byte +var z3889 [1 << 17]byte +var z3890 [1 << 17]byte +var z3891 [1 << 17]byte +var z3892 [1 << 17]byte +var z3893 [1 << 17]byte +var z3894 [1 << 17]byte +var z3895 [1 << 17]byte +var z3896 [1 << 17]byte +var z3897 [1 << 17]byte +var z3898 [1 << 17]byte +var z3899 [1 << 17]byte +var z3900 [1 << 17]byte +var z3901 [1 << 17]byte +var z3902 [1 << 17]byte +var z3903 [1 << 17]byte +var z3904 [1 << 17]byte +var z3905 [1 << 17]byte +var z3906 [1 << 17]byte +var z3907 [1 << 17]byte +var z3908 [1 << 17]byte +var z3909 [1 << 17]byte +var z3910 [1 << 17]byte +var z3911 [1 << 17]byte +var z3912 [1 << 17]byte +var z3913 [1 << 17]byte +var z3914 [1 << 17]byte +var z3915 [1 << 17]byte +var z3916 [1 << 17]byte +var z3917 [1 << 17]byte +var z3918 [1 << 17]byte +var z3919 [1 << 17]byte +var z3920 [1 << 17]byte +var z3921 [1 << 17]byte +var z3922 [1 << 17]byte +var z3923 [1 << 17]byte +var z3924 [1 << 17]byte +var z3925 [1 << 17]byte +var z3926 [1 << 17]byte +var z3927 [1 << 17]byte +var z3928 [1 << 17]byte +var z3929 [1 << 17]byte +var z3930 [1 << 17]byte +var z3931 [1 << 17]byte +var z3932 [1 << 17]byte +var z3933 [1 << 17]byte +var z3934 [1 << 17]byte +var z3935 [1 << 17]byte +var z3936 [1 << 17]byte +var z3937 [1 << 17]byte +var z3938 [1 << 17]byte +var z3939 [1 << 17]byte +var z3940 [1 << 17]byte +var z3941 [1 << 17]byte +var z3942 [1 << 17]byte +var z3943 [1 << 17]byte +var z3944 [1 << 17]byte +var z3945 [1 << 17]byte +var z3946 [1 << 17]byte +var z3947 [1 << 17]byte +var z3948 [1 << 17]byte +var z3949 [1 << 17]byte +var z3950 [1 << 17]byte +var z3951 [1 << 17]byte +var z3952 [1 << 17]byte +var z3953 [1 << 17]byte +var z3954 [1 << 17]byte +var z3955 [1 << 17]byte +var z3956 [1 << 17]byte +var z3957 [1 << 17]byte +var z3958 [1 << 17]byte +var z3959 [1 << 17]byte +var z3960 [1 << 17]byte +var z3961 [1 << 17]byte +var z3962 [1 << 17]byte +var z3963 [1 << 17]byte +var z3964 [1 << 17]byte +var z3965 [1 << 17]byte +var z3966 [1 << 17]byte +var z3967 [1 << 17]byte +var z3968 [1 << 17]byte +var z3969 [1 << 17]byte +var z3970 [1 << 17]byte +var z3971 [1 << 17]byte +var z3972 [1 << 17]byte +var z3973 [1 << 17]byte +var z3974 [1 << 17]byte +var z3975 [1 << 17]byte +var z3976 [1 << 17]byte +var z3977 [1 << 17]byte +var z3978 [1 << 17]byte +var z3979 [1 << 17]byte +var z3980 [1 << 17]byte +var z3981 [1 << 17]byte +var z3982 [1 << 17]byte +var z3983 [1 << 17]byte +var z3984 [1 << 17]byte +var z3985 [1 << 17]byte +var z3986 [1 << 17]byte +var z3987 [1 << 17]byte +var z3988 [1 << 17]byte +var z3989 [1 << 17]byte +var z3990 [1 << 17]byte +var z3991 [1 << 17]byte +var z3992 [1 << 17]byte +var z3993 [1 << 17]byte +var z3994 [1 << 17]byte +var z3995 [1 << 17]byte +var z3996 [1 << 17]byte +var z3997 [1 << 17]byte +var z3998 [1 << 17]byte +var z3999 [1 << 17]byte +var z4000 [1 << 17]byte +var z4001 [1 << 17]byte +var z4002 [1 << 17]byte +var z4003 [1 << 17]byte +var z4004 [1 << 17]byte +var z4005 [1 << 17]byte +var z4006 [1 << 17]byte +var z4007 [1 << 17]byte +var z4008 [1 << 17]byte +var z4009 [1 << 17]byte +var z4010 [1 << 17]byte +var z4011 [1 << 17]byte +var z4012 [1 << 17]byte +var z4013 [1 << 17]byte +var z4014 [1 << 17]byte +var z4015 [1 << 17]byte +var z4016 [1 << 17]byte +var z4017 [1 << 17]byte +var z4018 [1 << 17]byte +var z4019 [1 << 17]byte +var z4020 [1 << 17]byte +var z4021 [1 << 17]byte +var z4022 [1 << 17]byte +var z4023 [1 << 17]byte +var z4024 [1 << 17]byte +var z4025 [1 << 17]byte +var z4026 [1 << 17]byte +var z4027 [1 << 17]byte +var z4028 [1 << 17]byte +var z4029 [1 << 17]byte +var z4030 [1 << 17]byte +var z4031 [1 << 17]byte +var z4032 [1 << 17]byte +var z4033 [1 << 17]byte +var z4034 [1 << 17]byte +var z4035 [1 << 17]byte +var z4036 [1 << 17]byte +var z4037 [1 << 17]byte +var z4038 [1 << 17]byte +var z4039 [1 << 17]byte +var z4040 [1 << 17]byte +var z4041 [1 << 17]byte +var z4042 [1 << 17]byte +var z4043 [1 << 17]byte +var z4044 [1 << 17]byte +var z4045 [1 << 17]byte +var z4046 [1 << 17]byte +var z4047 [1 << 17]byte +var z4048 [1 << 17]byte +var z4049 [1 << 17]byte +var z4050 [1 << 17]byte +var z4051 [1 << 17]byte +var z4052 [1 << 17]byte +var z4053 [1 << 17]byte +var z4054 [1 << 17]byte +var z4055 [1 << 17]byte +var z4056 [1 << 17]byte +var z4057 [1 << 17]byte +var z4058 [1 << 17]byte +var z4059 [1 << 17]byte +var z4060 [1 << 17]byte +var z4061 [1 << 17]byte +var z4062 [1 << 17]byte +var z4063 [1 << 17]byte +var z4064 [1 << 17]byte +var z4065 [1 << 17]byte +var z4066 [1 << 17]byte +var z4067 [1 << 17]byte +var z4068 [1 << 17]byte +var z4069 [1 << 17]byte +var z4070 [1 << 17]byte +var z4071 [1 << 17]byte +var z4072 [1 << 17]byte +var z4073 [1 << 17]byte +var z4074 [1 << 17]byte +var z4075 [1 << 17]byte +var z4076 [1 << 17]byte +var z4077 [1 << 17]byte +var z4078 [1 << 17]byte +var z4079 [1 << 17]byte +var z4080 [1 << 17]byte +var z4081 [1 << 17]byte +var z4082 [1 << 17]byte +var z4083 [1 << 17]byte +var z4084 [1 << 17]byte +var z4085 [1 << 17]byte +var z4086 [1 << 17]byte +var z4087 [1 << 17]byte +var z4088 [1 << 17]byte +var z4089 [1 << 17]byte +var z4090 [1 << 17]byte +var z4091 [1 << 17]byte +var z4092 [1 << 17]byte +var z4093 [1 << 17]byte +var z4094 [1 << 17]byte +var z4095 [1 << 17]byte +var z4096 [1 << 17]byte +var z4097 [1 << 17]byte +var z4098 [1 << 17]byte +var z4099 [1 << 17]byte +var z4100 [1 << 17]byte +var z4101 [1 << 17]byte +var z4102 [1 << 17]byte +var z4103 [1 << 17]byte +var z4104 [1 << 17]byte +var z4105 [1 << 17]byte +var z4106 [1 << 17]byte +var z4107 [1 << 17]byte +var z4108 [1 << 17]byte +var z4109 [1 << 17]byte +var z4110 [1 << 17]byte +var z4111 [1 << 17]byte +var z4112 [1 << 17]byte +var z4113 [1 << 17]byte +var z4114 [1 << 17]byte +var z4115 [1 << 17]byte +var z4116 [1 << 17]byte +var z4117 [1 << 17]byte +var z4118 [1 << 17]byte +var z4119 [1 << 17]byte +var z4120 [1 << 17]byte +var z4121 [1 << 17]byte +var z4122 [1 << 17]byte +var z4123 [1 << 17]byte +var z4124 [1 << 17]byte +var z4125 [1 << 17]byte +var z4126 [1 << 17]byte +var z4127 [1 << 17]byte +var z4128 [1 << 17]byte +var z4129 [1 << 17]byte +var z4130 [1 << 17]byte +var z4131 [1 << 17]byte +var z4132 [1 << 17]byte +var z4133 [1 << 17]byte +var z4134 [1 << 17]byte +var z4135 [1 << 17]byte +var z4136 [1 << 17]byte +var z4137 [1 << 17]byte +var z4138 [1 << 17]byte +var z4139 [1 << 17]byte +var z4140 [1 << 17]byte +var z4141 [1 << 17]byte +var z4142 [1 << 17]byte +var z4143 [1 << 17]byte +var z4144 [1 << 17]byte +var z4145 [1 << 17]byte +var z4146 [1 << 17]byte +var z4147 [1 << 17]byte +var z4148 [1 << 17]byte +var z4149 [1 << 17]byte +var z4150 [1 << 17]byte +var z4151 [1 << 17]byte +var z4152 [1 << 17]byte +var z4153 [1 << 17]byte +var z4154 [1 << 17]byte +var z4155 [1 << 17]byte +var z4156 [1 << 17]byte +var z4157 [1 << 17]byte +var z4158 [1 << 17]byte +var z4159 [1 << 17]byte +var z4160 [1 << 17]byte +var z4161 [1 << 17]byte +var z4162 [1 << 17]byte +var z4163 [1 << 17]byte +var z4164 [1 << 17]byte +var z4165 [1 << 17]byte +var z4166 [1 << 17]byte +var z4167 [1 << 17]byte +var z4168 [1 << 17]byte +var z4169 [1 << 17]byte +var z4170 [1 << 17]byte +var z4171 [1 << 17]byte +var z4172 [1 << 17]byte +var z4173 [1 << 17]byte +var z4174 [1 << 17]byte +var z4175 [1 << 17]byte +var z4176 [1 << 17]byte +var z4177 [1 << 17]byte +var z4178 [1 << 17]byte +var z4179 [1 << 17]byte +var z4180 [1 << 17]byte +var z4181 [1 << 17]byte +var z4182 [1 << 17]byte +var z4183 [1 << 17]byte +var z4184 [1 << 17]byte +var z4185 [1 << 17]byte +var z4186 [1 << 17]byte +var z4187 [1 << 17]byte +var z4188 [1 << 17]byte +var z4189 [1 << 17]byte +var z4190 [1 << 17]byte +var z4191 [1 << 17]byte +var z4192 [1 << 17]byte +var z4193 [1 << 17]byte +var z4194 [1 << 17]byte +var z4195 [1 << 17]byte +var z4196 [1 << 17]byte +var z4197 [1 << 17]byte +var z4198 [1 << 17]byte +var z4199 [1 << 17]byte +var z4200 [1 << 17]byte +var z4201 [1 << 17]byte +var z4202 [1 << 17]byte +var z4203 [1 << 17]byte +var z4204 [1 << 17]byte +var z4205 [1 << 17]byte +var z4206 [1 << 17]byte +var z4207 [1 << 17]byte +var z4208 [1 << 17]byte +var z4209 [1 << 17]byte +var z4210 [1 << 17]byte +var z4211 [1 << 17]byte +var z4212 [1 << 17]byte +var z4213 [1 << 17]byte +var z4214 [1 << 17]byte +var z4215 [1 << 17]byte +var z4216 [1 << 17]byte +var z4217 [1 << 17]byte +var z4218 [1 << 17]byte +var z4219 [1 << 17]byte +var z4220 [1 << 17]byte +var z4221 [1 << 17]byte +var z4222 [1 << 17]byte +var z4223 [1 << 17]byte +var z4224 [1 << 17]byte +var z4225 [1 << 17]byte +var z4226 [1 << 17]byte +var z4227 [1 << 17]byte +var z4228 [1 << 17]byte +var z4229 [1 << 17]byte +var z4230 [1 << 17]byte +var z4231 [1 << 17]byte +var z4232 [1 << 17]byte +var z4233 [1 << 17]byte +var z4234 [1 << 17]byte +var z4235 [1 << 17]byte +var z4236 [1 << 17]byte +var z4237 [1 << 17]byte +var z4238 [1 << 17]byte +var z4239 [1 << 17]byte +var z4240 [1 << 17]byte +var z4241 [1 << 17]byte +var z4242 [1 << 17]byte +var z4243 [1 << 17]byte +var z4244 [1 << 17]byte +var z4245 [1 << 17]byte +var z4246 [1 << 17]byte +var z4247 [1 << 17]byte +var z4248 [1 << 17]byte +var z4249 [1 << 17]byte +var z4250 [1 << 17]byte +var z4251 [1 << 17]byte +var z4252 [1 << 17]byte +var z4253 [1 << 17]byte +var z4254 [1 << 17]byte +var z4255 [1 << 17]byte +var z4256 [1 << 17]byte +var z4257 [1 << 17]byte +var z4258 [1 << 17]byte +var z4259 [1 << 17]byte +var z4260 [1 << 17]byte +var z4261 [1 << 17]byte +var z4262 [1 << 17]byte +var z4263 [1 << 17]byte +var z4264 [1 << 17]byte +var z4265 [1 << 17]byte +var z4266 [1 << 17]byte +var z4267 [1 << 17]byte +var z4268 [1 << 17]byte +var z4269 [1 << 17]byte +var z4270 [1 << 17]byte +var z4271 [1 << 17]byte +var z4272 [1 << 17]byte +var z4273 [1 << 17]byte +var z4274 [1 << 17]byte +var z4275 [1 << 17]byte +var z4276 [1 << 17]byte +var z4277 [1 << 17]byte +var z4278 [1 << 17]byte +var z4279 [1 << 17]byte +var z4280 [1 << 17]byte +var z4281 [1 << 17]byte +var z4282 [1 << 17]byte +var z4283 [1 << 17]byte +var z4284 [1 << 17]byte +var z4285 [1 << 17]byte +var z4286 [1 << 17]byte +var z4287 [1 << 17]byte +var z4288 [1 << 17]byte +var z4289 [1 << 17]byte +var z4290 [1 << 17]byte +var z4291 [1 << 17]byte +var z4292 [1 << 17]byte +var z4293 [1 << 17]byte +var z4294 [1 << 17]byte +var z4295 [1 << 17]byte +var z4296 [1 << 17]byte +var z4297 [1 << 17]byte +var z4298 [1 << 17]byte +var z4299 [1 << 17]byte +var z4300 [1 << 17]byte +var z4301 [1 << 17]byte +var z4302 [1 << 17]byte +var z4303 [1 << 17]byte +var z4304 [1 << 17]byte +var z4305 [1 << 17]byte +var z4306 [1 << 17]byte +var z4307 [1 << 17]byte +var z4308 [1 << 17]byte +var z4309 [1 << 17]byte +var z4310 [1 << 17]byte +var z4311 [1 << 17]byte +var z4312 [1 << 17]byte +var z4313 [1 << 17]byte +var z4314 [1 << 17]byte +var z4315 [1 << 17]byte +var z4316 [1 << 17]byte +var z4317 [1 << 17]byte +var z4318 [1 << 17]byte +var z4319 [1 << 17]byte +var z4320 [1 << 17]byte +var z4321 [1 << 17]byte +var z4322 [1 << 17]byte +var z4323 [1 << 17]byte +var z4324 [1 << 17]byte +var z4325 [1 << 17]byte +var z4326 [1 << 17]byte +var z4327 [1 << 17]byte +var z4328 [1 << 17]byte +var z4329 [1 << 17]byte +var z4330 [1 << 17]byte +var z4331 [1 << 17]byte +var z4332 [1 << 17]byte +var z4333 [1 << 17]byte +var z4334 [1 << 17]byte +var z4335 [1 << 17]byte +var z4336 [1 << 17]byte +var z4337 [1 << 17]byte +var z4338 [1 << 17]byte +var z4339 [1 << 17]byte +var z4340 [1 << 17]byte +var z4341 [1 << 17]byte +var z4342 [1 << 17]byte +var z4343 [1 << 17]byte +var z4344 [1 << 17]byte +var z4345 [1 << 17]byte +var z4346 [1 << 17]byte +var z4347 [1 << 17]byte +var z4348 [1 << 17]byte +var z4349 [1 << 17]byte +var z4350 [1 << 17]byte +var z4351 [1 << 17]byte +var z4352 [1 << 17]byte +var z4353 [1 << 17]byte +var z4354 [1 << 17]byte +var z4355 [1 << 17]byte +var z4356 [1 << 17]byte +var z4357 [1 << 17]byte +var z4358 [1 << 17]byte +var z4359 [1 << 17]byte +var z4360 [1 << 17]byte +var z4361 [1 << 17]byte +var z4362 [1 << 17]byte +var z4363 [1 << 17]byte +var z4364 [1 << 17]byte +var z4365 [1 << 17]byte +var z4366 [1 << 17]byte +var z4367 [1 << 17]byte +var z4368 [1 << 17]byte +var z4369 [1 << 17]byte +var z4370 [1 << 17]byte +var z4371 [1 << 17]byte +var z4372 [1 << 17]byte +var z4373 [1 << 17]byte +var z4374 [1 << 17]byte +var z4375 [1 << 17]byte +var z4376 [1 << 17]byte +var z4377 [1 << 17]byte +var z4378 [1 << 17]byte +var z4379 [1 << 17]byte +var z4380 [1 << 17]byte +var z4381 [1 << 17]byte +var z4382 [1 << 17]byte +var z4383 [1 << 17]byte +var z4384 [1 << 17]byte +var z4385 [1 << 17]byte +var z4386 [1 << 17]byte +var z4387 [1 << 17]byte +var z4388 [1 << 17]byte +var z4389 [1 << 17]byte +var z4390 [1 << 17]byte +var z4391 [1 << 17]byte +var z4392 [1 << 17]byte +var z4393 [1 << 17]byte +var z4394 [1 << 17]byte +var z4395 [1 << 17]byte +var z4396 [1 << 17]byte +var z4397 [1 << 17]byte +var z4398 [1 << 17]byte +var z4399 [1 << 17]byte +var z4400 [1 << 17]byte +var z4401 [1 << 17]byte +var z4402 [1 << 17]byte +var z4403 [1 << 17]byte +var z4404 [1 << 17]byte +var z4405 [1 << 17]byte +var z4406 [1 << 17]byte +var z4407 [1 << 17]byte +var z4408 [1 << 17]byte +var z4409 [1 << 17]byte +var z4410 [1 << 17]byte +var z4411 [1 << 17]byte +var z4412 [1 << 17]byte +var z4413 [1 << 17]byte +var z4414 [1 << 17]byte +var z4415 [1 << 17]byte +var z4416 [1 << 17]byte +var z4417 [1 << 17]byte +var z4418 [1 << 17]byte +var z4419 [1 << 17]byte +var z4420 [1 << 17]byte +var z4421 [1 << 17]byte +var z4422 [1 << 17]byte +var z4423 [1 << 17]byte +var z4424 [1 << 17]byte +var z4425 [1 << 17]byte +var z4426 [1 << 17]byte +var z4427 [1 << 17]byte +var z4428 [1 << 17]byte +var z4429 [1 << 17]byte +var z4430 [1 << 17]byte +var z4431 [1 << 17]byte +var z4432 [1 << 17]byte +var z4433 [1 << 17]byte +var z4434 [1 << 17]byte +var z4435 [1 << 17]byte +var z4436 [1 << 17]byte +var z4437 [1 << 17]byte +var z4438 [1 << 17]byte +var z4439 [1 << 17]byte +var z4440 [1 << 17]byte +var z4441 [1 << 17]byte +var z4442 [1 << 17]byte +var z4443 [1 << 17]byte +var z4444 [1 << 17]byte +var z4445 [1 << 17]byte +var z4446 [1 << 17]byte +var z4447 [1 << 17]byte +var z4448 [1 << 17]byte +var z4449 [1 << 17]byte +var z4450 [1 << 17]byte +var z4451 [1 << 17]byte +var z4452 [1 << 17]byte +var z4453 [1 << 17]byte +var z4454 [1 << 17]byte +var z4455 [1 << 17]byte +var z4456 [1 << 17]byte +var z4457 [1 << 17]byte +var z4458 [1 << 17]byte +var z4459 [1 << 17]byte +var z4460 [1 << 17]byte +var z4461 [1 << 17]byte +var z4462 [1 << 17]byte +var z4463 [1 << 17]byte +var z4464 [1 << 17]byte +var z4465 [1 << 17]byte +var z4466 [1 << 17]byte +var z4467 [1 << 17]byte +var z4468 [1 << 17]byte +var z4469 [1 << 17]byte +var z4470 [1 << 17]byte +var z4471 [1 << 17]byte +var z4472 [1 << 17]byte +var z4473 [1 << 17]byte +var z4474 [1 << 17]byte +var z4475 [1 << 17]byte +var z4476 [1 << 17]byte +var z4477 [1 << 17]byte +var z4478 [1 << 17]byte +var z4479 [1 << 17]byte +var z4480 [1 << 17]byte +var z4481 [1 << 17]byte +var z4482 [1 << 17]byte +var z4483 [1 << 17]byte +var z4484 [1 << 17]byte +var z4485 [1 << 17]byte +var z4486 [1 << 17]byte +var z4487 [1 << 17]byte +var z4488 [1 << 17]byte +var z4489 [1 << 17]byte +var z4490 [1 << 17]byte +var z4491 [1 << 17]byte +var z4492 [1 << 17]byte +var z4493 [1 << 17]byte +var z4494 [1 << 17]byte +var z4495 [1 << 17]byte +var z4496 [1 << 17]byte +var z4497 [1 << 17]byte +var z4498 [1 << 17]byte +var z4499 [1 << 17]byte +var z4500 [1 << 17]byte +var z4501 [1 << 17]byte +var z4502 [1 << 17]byte +var z4503 [1 << 17]byte +var z4504 [1 << 17]byte +var z4505 [1 << 17]byte +var z4506 [1 << 17]byte +var z4507 [1 << 17]byte +var z4508 [1 << 17]byte +var z4509 [1 << 17]byte +var z4510 [1 << 17]byte +var z4511 [1 << 17]byte +var z4512 [1 << 17]byte +var z4513 [1 << 17]byte +var z4514 [1 << 17]byte +var z4515 [1 << 17]byte +var z4516 [1 << 17]byte +var z4517 [1 << 17]byte +var z4518 [1 << 17]byte +var z4519 [1 << 17]byte +var z4520 [1 << 17]byte +var z4521 [1 << 17]byte +var z4522 [1 << 17]byte +var z4523 [1 << 17]byte +var z4524 [1 << 17]byte +var z4525 [1 << 17]byte +var z4526 [1 << 17]byte +var z4527 [1 << 17]byte +var z4528 [1 << 17]byte +var z4529 [1 << 17]byte +var z4530 [1 << 17]byte +var z4531 [1 << 17]byte +var z4532 [1 << 17]byte +var z4533 [1 << 17]byte +var z4534 [1 << 17]byte +var z4535 [1 << 17]byte +var z4536 [1 << 17]byte +var z4537 [1 << 17]byte +var z4538 [1 << 17]byte +var z4539 [1 << 17]byte +var z4540 [1 << 17]byte +var z4541 [1 << 17]byte +var z4542 [1 << 17]byte +var z4543 [1 << 17]byte +var z4544 [1 << 17]byte +var z4545 [1 << 17]byte +var z4546 [1 << 17]byte +var z4547 [1 << 17]byte +var z4548 [1 << 17]byte +var z4549 [1 << 17]byte +var z4550 [1 << 17]byte +var z4551 [1 << 17]byte +var z4552 [1 << 17]byte +var z4553 [1 << 17]byte +var z4554 [1 << 17]byte +var z4555 [1 << 17]byte +var z4556 [1 << 17]byte +var z4557 [1 << 17]byte +var z4558 [1 << 17]byte +var z4559 [1 << 17]byte +var z4560 [1 << 17]byte +var z4561 [1 << 17]byte +var z4562 [1 << 17]byte +var z4563 [1 << 17]byte +var z4564 [1 << 17]byte +var z4565 [1 << 17]byte +var z4566 [1 << 17]byte +var z4567 [1 << 17]byte +var z4568 [1 << 17]byte +var z4569 [1 << 17]byte +var z4570 [1 << 17]byte +var z4571 [1 << 17]byte +var z4572 [1 << 17]byte +var z4573 [1 << 17]byte +var z4574 [1 << 17]byte +var z4575 [1 << 17]byte +var z4576 [1 << 17]byte +var z4577 [1 << 17]byte +var z4578 [1 << 17]byte +var z4579 [1 << 17]byte +var z4580 [1 << 17]byte +var z4581 [1 << 17]byte +var z4582 [1 << 17]byte +var z4583 [1 << 17]byte +var z4584 [1 << 17]byte +var z4585 [1 << 17]byte +var z4586 [1 << 17]byte +var z4587 [1 << 17]byte +var z4588 [1 << 17]byte +var z4589 [1 << 17]byte +var z4590 [1 << 17]byte +var z4591 [1 << 17]byte +var z4592 [1 << 17]byte +var z4593 [1 << 17]byte +var z4594 [1 << 17]byte +var z4595 [1 << 17]byte +var z4596 [1 << 17]byte +var z4597 [1 << 17]byte +var z4598 [1 << 17]byte +var z4599 [1 << 17]byte +var z4600 [1 << 17]byte +var z4601 [1 << 17]byte +var z4602 [1 << 17]byte +var z4603 [1 << 17]byte +var z4604 [1 << 17]byte +var z4605 [1 << 17]byte +var z4606 [1 << 17]byte +var z4607 [1 << 17]byte +var z4608 [1 << 17]byte +var z4609 [1 << 17]byte +var z4610 [1 << 17]byte +var z4611 [1 << 17]byte +var z4612 [1 << 17]byte +var z4613 [1 << 17]byte +var z4614 [1 << 17]byte +var z4615 [1 << 17]byte +var z4616 [1 << 17]byte +var z4617 [1 << 17]byte +var z4618 [1 << 17]byte +var z4619 [1 << 17]byte +var z4620 [1 << 17]byte +var z4621 [1 << 17]byte +var z4622 [1 << 17]byte +var z4623 [1 << 17]byte +var z4624 [1 << 17]byte +var z4625 [1 << 17]byte +var z4626 [1 << 17]byte +var z4627 [1 << 17]byte +var z4628 [1 << 17]byte +var z4629 [1 << 17]byte +var z4630 [1 << 17]byte +var z4631 [1 << 17]byte +var z4632 [1 << 17]byte +var z4633 [1 << 17]byte +var z4634 [1 << 17]byte +var z4635 [1 << 17]byte +var z4636 [1 << 17]byte +var z4637 [1 << 17]byte +var z4638 [1 << 17]byte +var z4639 [1 << 17]byte +var z4640 [1 << 17]byte +var z4641 [1 << 17]byte +var z4642 [1 << 17]byte +var z4643 [1 << 17]byte +var z4644 [1 << 17]byte +var z4645 [1 << 17]byte +var z4646 [1 << 17]byte +var z4647 [1 << 17]byte +var z4648 [1 << 17]byte +var z4649 [1 << 17]byte +var z4650 [1 << 17]byte +var z4651 [1 << 17]byte +var z4652 [1 << 17]byte +var z4653 [1 << 17]byte +var z4654 [1 << 17]byte +var z4655 [1 << 17]byte +var z4656 [1 << 17]byte +var z4657 [1 << 17]byte +var z4658 [1 << 17]byte +var z4659 [1 << 17]byte +var z4660 [1 << 17]byte +var z4661 [1 << 17]byte +var z4662 [1 << 17]byte +var z4663 [1 << 17]byte +var z4664 [1 << 17]byte +var z4665 [1 << 17]byte +var z4666 [1 << 17]byte +var z4667 [1 << 17]byte +var z4668 [1 << 17]byte +var z4669 [1 << 17]byte +var z4670 [1 << 17]byte +var z4671 [1 << 17]byte +var z4672 [1 << 17]byte +var z4673 [1 << 17]byte +var z4674 [1 << 17]byte +var z4675 [1 << 17]byte +var z4676 [1 << 17]byte +var z4677 [1 << 17]byte +var z4678 [1 << 17]byte +var z4679 [1 << 17]byte +var z4680 [1 << 17]byte +var z4681 [1 << 17]byte +var z4682 [1 << 17]byte +var z4683 [1 << 17]byte +var z4684 [1 << 17]byte +var z4685 [1 << 17]byte +var z4686 [1 << 17]byte +var z4687 [1 << 17]byte +var z4688 [1 << 17]byte +var z4689 [1 << 17]byte +var z4690 [1 << 17]byte +var z4691 [1 << 17]byte +var z4692 [1 << 17]byte +var z4693 [1 << 17]byte +var z4694 [1 << 17]byte +var z4695 [1 << 17]byte +var z4696 [1 << 17]byte +var z4697 [1 << 17]byte +var z4698 [1 << 17]byte +var z4699 [1 << 17]byte +var z4700 [1 << 17]byte +var z4701 [1 << 17]byte +var z4702 [1 << 17]byte +var z4703 [1 << 17]byte +var z4704 [1 << 17]byte +var z4705 [1 << 17]byte +var z4706 [1 << 17]byte +var z4707 [1 << 17]byte +var z4708 [1 << 17]byte +var z4709 [1 << 17]byte +var z4710 [1 << 17]byte +var z4711 [1 << 17]byte +var z4712 [1 << 17]byte +var z4713 [1 << 17]byte +var z4714 [1 << 17]byte +var z4715 [1 << 17]byte +var z4716 [1 << 17]byte +var z4717 [1 << 17]byte +var z4718 [1 << 17]byte +var z4719 [1 << 17]byte +var z4720 [1 << 17]byte +var z4721 [1 << 17]byte +var z4722 [1 << 17]byte +var z4723 [1 << 17]byte +var z4724 [1 << 17]byte +var z4725 [1 << 17]byte +var z4726 [1 << 17]byte +var z4727 [1 << 17]byte +var z4728 [1 << 17]byte +var z4729 [1 << 17]byte +var z4730 [1 << 17]byte +var z4731 [1 << 17]byte +var z4732 [1 << 17]byte +var z4733 [1 << 17]byte +var z4734 [1 << 17]byte +var z4735 [1 << 17]byte +var z4736 [1 << 17]byte +var z4737 [1 << 17]byte +var z4738 [1 << 17]byte +var z4739 [1 << 17]byte +var z4740 [1 << 17]byte +var z4741 [1 << 17]byte +var z4742 [1 << 17]byte +var z4743 [1 << 17]byte +var z4744 [1 << 17]byte +var z4745 [1 << 17]byte +var z4746 [1 << 17]byte +var z4747 [1 << 17]byte +var z4748 [1 << 17]byte +var z4749 [1 << 17]byte +var z4750 [1 << 17]byte +var z4751 [1 << 17]byte +var z4752 [1 << 17]byte +var z4753 [1 << 17]byte +var z4754 [1 << 17]byte +var z4755 [1 << 17]byte +var z4756 [1 << 17]byte +var z4757 [1 << 17]byte +var z4758 [1 << 17]byte +var z4759 [1 << 17]byte +var z4760 [1 << 17]byte +var z4761 [1 << 17]byte +var z4762 [1 << 17]byte +var z4763 [1 << 17]byte +var z4764 [1 << 17]byte +var z4765 [1 << 17]byte +var z4766 [1 << 17]byte +var z4767 [1 << 17]byte +var z4768 [1 << 17]byte +var z4769 [1 << 17]byte +var z4770 [1 << 17]byte +var z4771 [1 << 17]byte +var z4772 [1 << 17]byte +var z4773 [1 << 17]byte +var z4774 [1 << 17]byte +var z4775 [1 << 17]byte +var z4776 [1 << 17]byte +var z4777 [1 << 17]byte +var z4778 [1 << 17]byte +var z4779 [1 << 17]byte +var z4780 [1 << 17]byte +var z4781 [1 << 17]byte +var z4782 [1 << 17]byte +var z4783 [1 << 17]byte +var z4784 [1 << 17]byte +var z4785 [1 << 17]byte +var z4786 [1 << 17]byte +var z4787 [1 << 17]byte +var z4788 [1 << 17]byte +var z4789 [1 << 17]byte +var z4790 [1 << 17]byte +var z4791 [1 << 17]byte +var z4792 [1 << 17]byte +var z4793 [1 << 17]byte +var z4794 [1 << 17]byte +var z4795 [1 << 17]byte +var z4796 [1 << 17]byte +var z4797 [1 << 17]byte +var z4798 [1 << 17]byte +var z4799 [1 << 17]byte +var z4800 [1 << 17]byte +var z4801 [1 << 17]byte +var z4802 [1 << 17]byte +var z4803 [1 << 17]byte +var z4804 [1 << 17]byte +var z4805 [1 << 17]byte +var z4806 [1 << 17]byte +var z4807 [1 << 17]byte +var z4808 [1 << 17]byte +var z4809 [1 << 17]byte +var z4810 [1 << 17]byte +var z4811 [1 << 17]byte +var z4812 [1 << 17]byte +var z4813 [1 << 17]byte +var z4814 [1 << 17]byte +var z4815 [1 << 17]byte +var z4816 [1 << 17]byte +var z4817 [1 << 17]byte +var z4818 [1 << 17]byte +var z4819 [1 << 17]byte +var z4820 [1 << 17]byte +var z4821 [1 << 17]byte +var z4822 [1 << 17]byte +var z4823 [1 << 17]byte +var z4824 [1 << 17]byte +var z4825 [1 << 17]byte +var z4826 [1 << 17]byte +var z4827 [1 << 17]byte +var z4828 [1 << 17]byte +var z4829 [1 << 17]byte +var z4830 [1 << 17]byte +var z4831 [1 << 17]byte +var z4832 [1 << 17]byte +var z4833 [1 << 17]byte +var z4834 [1 << 17]byte +var z4835 [1 << 17]byte +var z4836 [1 << 17]byte +var z4837 [1 << 17]byte +var z4838 [1 << 17]byte +var z4839 [1 << 17]byte +var z4840 [1 << 17]byte +var z4841 [1 << 17]byte +var z4842 [1 << 17]byte +var z4843 [1 << 17]byte +var z4844 [1 << 17]byte +var z4845 [1 << 17]byte +var z4846 [1 << 17]byte +var z4847 [1 << 17]byte +var z4848 [1 << 17]byte +var z4849 [1 << 17]byte +var z4850 [1 << 17]byte +var z4851 [1 << 17]byte +var z4852 [1 << 17]byte +var z4853 [1 << 17]byte +var z4854 [1 << 17]byte +var z4855 [1 << 17]byte +var z4856 [1 << 17]byte +var z4857 [1 << 17]byte +var z4858 [1 << 17]byte +var z4859 [1 << 17]byte +var z4860 [1 << 17]byte +var z4861 [1 << 17]byte +var z4862 [1 << 17]byte +var z4863 [1 << 17]byte +var z4864 [1 << 17]byte +var z4865 [1 << 17]byte +var z4866 [1 << 17]byte +var z4867 [1 << 17]byte +var z4868 [1 << 17]byte +var z4869 [1 << 17]byte +var z4870 [1 << 17]byte +var z4871 [1 << 17]byte +var z4872 [1 << 17]byte +var z4873 [1 << 17]byte +var z4874 [1 << 17]byte +var z4875 [1 << 17]byte +var z4876 [1 << 17]byte +var z4877 [1 << 17]byte +var z4878 [1 << 17]byte +var z4879 [1 << 17]byte +var z4880 [1 << 17]byte +var z4881 [1 << 17]byte +var z4882 [1 << 17]byte +var z4883 [1 << 17]byte +var z4884 [1 << 17]byte +var z4885 [1 << 17]byte +var z4886 [1 << 17]byte +var z4887 [1 << 17]byte +var z4888 [1 << 17]byte +var z4889 [1 << 17]byte +var z4890 [1 << 17]byte +var z4891 [1 << 17]byte +var z4892 [1 << 17]byte +var z4893 [1 << 17]byte +var z4894 [1 << 17]byte +var z4895 [1 << 17]byte +var z4896 [1 << 17]byte +var z4897 [1 << 17]byte +var z4898 [1 << 17]byte +var z4899 [1 << 17]byte +var z4900 [1 << 17]byte +var z4901 [1 << 17]byte +var z4902 [1 << 17]byte +var z4903 [1 << 17]byte +var z4904 [1 << 17]byte +var z4905 [1 << 17]byte +var z4906 [1 << 17]byte +var z4907 [1 << 17]byte +var z4908 [1 << 17]byte +var z4909 [1 << 17]byte +var z4910 [1 << 17]byte +var z4911 [1 << 17]byte +var z4912 [1 << 17]byte +var z4913 [1 << 17]byte +var z4914 [1 << 17]byte +var z4915 [1 << 17]byte +var z4916 [1 << 17]byte +var z4917 [1 << 17]byte +var z4918 [1 << 17]byte +var z4919 [1 << 17]byte +var z4920 [1 << 17]byte +var z4921 [1 << 17]byte +var z4922 [1 << 17]byte +var z4923 [1 << 17]byte +var z4924 [1 << 17]byte +var z4925 [1 << 17]byte +var z4926 [1 << 17]byte +var z4927 [1 << 17]byte +var z4928 [1 << 17]byte +var z4929 [1 << 17]byte +var z4930 [1 << 17]byte +var z4931 [1 << 17]byte +var z4932 [1 << 17]byte +var z4933 [1 << 17]byte +var z4934 [1 << 17]byte +var z4935 [1 << 17]byte +var z4936 [1 << 17]byte +var z4937 [1 << 17]byte +var z4938 [1 << 17]byte +var z4939 [1 << 17]byte +var z4940 [1 << 17]byte +var z4941 [1 << 17]byte +var z4942 [1 << 17]byte +var z4943 [1 << 17]byte +var z4944 [1 << 17]byte +var z4945 [1 << 17]byte +var z4946 [1 << 17]byte +var z4947 [1 << 17]byte +var z4948 [1 << 17]byte +var z4949 [1 << 17]byte +var z4950 [1 << 17]byte +var z4951 [1 << 17]byte +var z4952 [1 << 17]byte +var z4953 [1 << 17]byte +var z4954 [1 << 17]byte +var z4955 [1 << 17]byte +var z4956 [1 << 17]byte +var z4957 [1 << 17]byte +var z4958 [1 << 17]byte +var z4959 [1 << 17]byte +var z4960 [1 << 17]byte +var z4961 [1 << 17]byte +var z4962 [1 << 17]byte +var z4963 [1 << 17]byte +var z4964 [1 << 17]byte +var z4965 [1 << 17]byte +var z4966 [1 << 17]byte +var z4967 [1 << 17]byte +var z4968 [1 << 17]byte +var z4969 [1 << 17]byte +var z4970 [1 << 17]byte +var z4971 [1 << 17]byte +var z4972 [1 << 17]byte +var z4973 [1 << 17]byte +var z4974 [1 << 17]byte +var z4975 [1 << 17]byte +var z4976 [1 << 17]byte +var z4977 [1 << 17]byte +var z4978 [1 << 17]byte +var z4979 [1 << 17]byte +var z4980 [1 << 17]byte +var z4981 [1 << 17]byte +var z4982 [1 << 17]byte +var z4983 [1 << 17]byte +var z4984 [1 << 17]byte +var z4985 [1 << 17]byte +var z4986 [1 << 17]byte +var z4987 [1 << 17]byte +var z4988 [1 << 17]byte +var z4989 [1 << 17]byte +var z4990 [1 << 17]byte +var z4991 [1 << 17]byte +var z4992 [1 << 17]byte +var z4993 [1 << 17]byte +var z4994 [1 << 17]byte +var z4995 [1 << 17]byte +var z4996 [1 << 17]byte +var z4997 [1 << 17]byte +var z4998 [1 << 17]byte +var z4999 [1 << 17]byte +var z5000 [1 << 17]byte +var z5001 [1 << 17]byte +var z5002 [1 << 17]byte +var z5003 [1 << 17]byte +var z5004 [1 << 17]byte +var z5005 [1 << 17]byte +var z5006 [1 << 17]byte +var z5007 [1 << 17]byte +var z5008 [1 << 17]byte +var z5009 [1 << 17]byte +var z5010 [1 << 17]byte +var z5011 [1 << 17]byte +var z5012 [1 << 17]byte +var z5013 [1 << 17]byte +var z5014 [1 << 17]byte +var z5015 [1 << 17]byte +var z5016 [1 << 17]byte +var z5017 [1 << 17]byte +var z5018 [1 << 17]byte +var z5019 [1 << 17]byte +var z5020 [1 << 17]byte +var z5021 [1 << 17]byte +var z5022 [1 << 17]byte +var z5023 [1 << 17]byte +var z5024 [1 << 17]byte +var z5025 [1 << 17]byte +var z5026 [1 << 17]byte +var z5027 [1 << 17]byte +var z5028 [1 << 17]byte +var z5029 [1 << 17]byte +var z5030 [1 << 17]byte +var z5031 [1 << 17]byte +var z5032 [1 << 17]byte +var z5033 [1 << 17]byte +var z5034 [1 << 17]byte +var z5035 [1 << 17]byte +var z5036 [1 << 17]byte +var z5037 [1 << 17]byte +var z5038 [1 << 17]byte +var z5039 [1 << 17]byte +var z5040 [1 << 17]byte +var z5041 [1 << 17]byte +var z5042 [1 << 17]byte +var z5043 [1 << 17]byte +var z5044 [1 << 17]byte +var z5045 [1 << 17]byte +var z5046 [1 << 17]byte +var z5047 [1 << 17]byte +var z5048 [1 << 17]byte +var z5049 [1 << 17]byte +var z5050 [1 << 17]byte +var z5051 [1 << 17]byte +var z5052 [1 << 17]byte +var z5053 [1 << 17]byte +var z5054 [1 << 17]byte +var z5055 [1 << 17]byte +var z5056 [1 << 17]byte +var z5057 [1 << 17]byte +var z5058 [1 << 17]byte +var z5059 [1 << 17]byte +var z5060 [1 << 17]byte +var z5061 [1 << 17]byte +var z5062 [1 << 17]byte +var z5063 [1 << 17]byte +var z5064 [1 << 17]byte +var z5065 [1 << 17]byte +var z5066 [1 << 17]byte +var z5067 [1 << 17]byte +var z5068 [1 << 17]byte +var z5069 [1 << 17]byte +var z5070 [1 << 17]byte +var z5071 [1 << 17]byte +var z5072 [1 << 17]byte +var z5073 [1 << 17]byte +var z5074 [1 << 17]byte +var z5075 [1 << 17]byte +var z5076 [1 << 17]byte +var z5077 [1 << 17]byte +var z5078 [1 << 17]byte +var z5079 [1 << 17]byte +var z5080 [1 << 17]byte +var z5081 [1 << 17]byte +var z5082 [1 << 17]byte +var z5083 [1 << 17]byte +var z5084 [1 << 17]byte +var z5085 [1 << 17]byte +var z5086 [1 << 17]byte +var z5087 [1 << 17]byte +var z5088 [1 << 17]byte +var z5089 [1 << 17]byte +var z5090 [1 << 17]byte +var z5091 [1 << 17]byte +var z5092 [1 << 17]byte +var z5093 [1 << 17]byte +var z5094 [1 << 17]byte +var z5095 [1 << 17]byte +var z5096 [1 << 17]byte +var z5097 [1 << 17]byte +var z5098 [1 << 17]byte +var z5099 [1 << 17]byte +var z5100 [1 << 17]byte +var z5101 [1 << 17]byte +var z5102 [1 << 17]byte +var z5103 [1 << 17]byte +var z5104 [1 << 17]byte +var z5105 [1 << 17]byte +var z5106 [1 << 17]byte +var z5107 [1 << 17]byte +var z5108 [1 << 17]byte +var z5109 [1 << 17]byte +var z5110 [1 << 17]byte +var z5111 [1 << 17]byte +var z5112 [1 << 17]byte +var z5113 [1 << 17]byte +var z5114 [1 << 17]byte +var z5115 [1 << 17]byte +var z5116 [1 << 17]byte +var z5117 [1 << 17]byte +var z5118 [1 << 17]byte +var z5119 [1 << 17]byte +var z5120 [1 << 17]byte +var z5121 [1 << 17]byte +var z5122 [1 << 17]byte +var z5123 [1 << 17]byte +var z5124 [1 << 17]byte +var z5125 [1 << 17]byte +var z5126 [1 << 17]byte +var z5127 [1 << 17]byte +var z5128 [1 << 17]byte +var z5129 [1 << 17]byte +var z5130 [1 << 17]byte +var z5131 [1 << 17]byte +var z5132 [1 << 17]byte +var z5133 [1 << 17]byte +var z5134 [1 << 17]byte +var z5135 [1 << 17]byte +var z5136 [1 << 17]byte +var z5137 [1 << 17]byte +var z5138 [1 << 17]byte +var z5139 [1 << 17]byte +var z5140 [1 << 17]byte +var z5141 [1 << 17]byte +var z5142 [1 << 17]byte +var z5143 [1 << 17]byte +var z5144 [1 << 17]byte +var z5145 [1 << 17]byte +var z5146 [1 << 17]byte +var z5147 [1 << 17]byte +var z5148 [1 << 17]byte +var z5149 [1 << 17]byte +var z5150 [1 << 17]byte +var z5151 [1 << 17]byte +var z5152 [1 << 17]byte +var z5153 [1 << 17]byte +var z5154 [1 << 17]byte +var z5155 [1 << 17]byte +var z5156 [1 << 17]byte +var z5157 [1 << 17]byte +var z5158 [1 << 17]byte +var z5159 [1 << 17]byte +var z5160 [1 << 17]byte +var z5161 [1 << 17]byte +var z5162 [1 << 17]byte +var z5163 [1 << 17]byte +var z5164 [1 << 17]byte +var z5165 [1 << 17]byte +var z5166 [1 << 17]byte +var z5167 [1 << 17]byte +var z5168 [1 << 17]byte +var z5169 [1 << 17]byte +var z5170 [1 << 17]byte +var z5171 [1 << 17]byte +var z5172 [1 << 17]byte +var z5173 [1 << 17]byte +var z5174 [1 << 17]byte +var z5175 [1 << 17]byte +var z5176 [1 << 17]byte +var z5177 [1 << 17]byte +var z5178 [1 << 17]byte +var z5179 [1 << 17]byte +var z5180 [1 << 17]byte +var z5181 [1 << 17]byte +var z5182 [1 << 17]byte +var z5183 [1 << 17]byte +var z5184 [1 << 17]byte +var z5185 [1 << 17]byte +var z5186 [1 << 17]byte +var z5187 [1 << 17]byte +var z5188 [1 << 17]byte +var z5189 [1 << 17]byte +var z5190 [1 << 17]byte +var z5191 [1 << 17]byte +var z5192 [1 << 17]byte +var z5193 [1 << 17]byte +var z5194 [1 << 17]byte +var z5195 [1 << 17]byte +var z5196 [1 << 17]byte +var z5197 [1 << 17]byte +var z5198 [1 << 17]byte +var z5199 [1 << 17]byte +var z5200 [1 << 17]byte +var z5201 [1 << 17]byte +var z5202 [1 << 17]byte +var z5203 [1 << 17]byte +var z5204 [1 << 17]byte +var z5205 [1 << 17]byte +var z5206 [1 << 17]byte +var z5207 [1 << 17]byte +var z5208 [1 << 17]byte +var z5209 [1 << 17]byte +var z5210 [1 << 17]byte +var z5211 [1 << 17]byte +var z5212 [1 << 17]byte +var z5213 [1 << 17]byte +var z5214 [1 << 17]byte +var z5215 [1 << 17]byte +var z5216 [1 << 17]byte +var z5217 [1 << 17]byte +var z5218 [1 << 17]byte +var z5219 [1 << 17]byte +var z5220 [1 << 17]byte +var z5221 [1 << 17]byte +var z5222 [1 << 17]byte +var z5223 [1 << 17]byte +var z5224 [1 << 17]byte +var z5225 [1 << 17]byte +var z5226 [1 << 17]byte +var z5227 [1 << 17]byte +var z5228 [1 << 17]byte +var z5229 [1 << 17]byte +var z5230 [1 << 17]byte +var z5231 [1 << 17]byte +var z5232 [1 << 17]byte +var z5233 [1 << 17]byte +var z5234 [1 << 17]byte +var z5235 [1 << 17]byte +var z5236 [1 << 17]byte +var z5237 [1 << 17]byte +var z5238 [1 << 17]byte +var z5239 [1 << 17]byte +var z5240 [1 << 17]byte +var z5241 [1 << 17]byte +var z5242 [1 << 17]byte +var z5243 [1 << 17]byte +var z5244 [1 << 17]byte +var z5245 [1 << 17]byte +var z5246 [1 << 17]byte +var z5247 [1 << 17]byte +var z5248 [1 << 17]byte +var z5249 [1 << 17]byte +var z5250 [1 << 17]byte +var z5251 [1 << 17]byte +var z5252 [1 << 17]byte +var z5253 [1 << 17]byte +var z5254 [1 << 17]byte +var z5255 [1 << 17]byte +var z5256 [1 << 17]byte +var z5257 [1 << 17]byte +var z5258 [1 << 17]byte +var z5259 [1 << 17]byte +var z5260 [1 << 17]byte +var z5261 [1 << 17]byte +var z5262 [1 << 17]byte +var z5263 [1 << 17]byte +var z5264 [1 << 17]byte +var z5265 [1 << 17]byte +var z5266 [1 << 17]byte +var z5267 [1 << 17]byte +var z5268 [1 << 17]byte +var z5269 [1 << 17]byte +var z5270 [1 << 17]byte +var z5271 [1 << 17]byte +var z5272 [1 << 17]byte +var z5273 [1 << 17]byte +var z5274 [1 << 17]byte +var z5275 [1 << 17]byte +var z5276 [1 << 17]byte +var z5277 [1 << 17]byte +var z5278 [1 << 17]byte +var z5279 [1 << 17]byte +var z5280 [1 << 17]byte +var z5281 [1 << 17]byte +var z5282 [1 << 17]byte +var z5283 [1 << 17]byte +var z5284 [1 << 17]byte +var z5285 [1 << 17]byte +var z5286 [1 << 17]byte +var z5287 [1 << 17]byte +var z5288 [1 << 17]byte +var z5289 [1 << 17]byte +var z5290 [1 << 17]byte +var z5291 [1 << 17]byte +var z5292 [1 << 17]byte +var z5293 [1 << 17]byte +var z5294 [1 << 17]byte +var z5295 [1 << 17]byte +var z5296 [1 << 17]byte +var z5297 [1 << 17]byte +var z5298 [1 << 17]byte +var z5299 [1 << 17]byte +var z5300 [1 << 17]byte +var z5301 [1 << 17]byte +var z5302 [1 << 17]byte +var z5303 [1 << 17]byte +var z5304 [1 << 17]byte +var z5305 [1 << 17]byte +var z5306 [1 << 17]byte +var z5307 [1 << 17]byte +var z5308 [1 << 17]byte +var z5309 [1 << 17]byte +var z5310 [1 << 17]byte +var z5311 [1 << 17]byte +var z5312 [1 << 17]byte +var z5313 [1 << 17]byte +var z5314 [1 << 17]byte +var z5315 [1 << 17]byte +var z5316 [1 << 17]byte +var z5317 [1 << 17]byte +var z5318 [1 << 17]byte +var z5319 [1 << 17]byte +var z5320 [1 << 17]byte +var z5321 [1 << 17]byte +var z5322 [1 << 17]byte +var z5323 [1 << 17]byte +var z5324 [1 << 17]byte +var z5325 [1 << 17]byte +var z5326 [1 << 17]byte +var z5327 [1 << 17]byte +var z5328 [1 << 17]byte +var z5329 [1 << 17]byte +var z5330 [1 << 17]byte +var z5331 [1 << 17]byte +var z5332 [1 << 17]byte +var z5333 [1 << 17]byte +var z5334 [1 << 17]byte +var z5335 [1 << 17]byte +var z5336 [1 << 17]byte +var z5337 [1 << 17]byte +var z5338 [1 << 17]byte +var z5339 [1 << 17]byte +var z5340 [1 << 17]byte +var z5341 [1 << 17]byte +var z5342 [1 << 17]byte +var z5343 [1 << 17]byte +var z5344 [1 << 17]byte +var z5345 [1 << 17]byte +var z5346 [1 << 17]byte +var z5347 [1 << 17]byte +var z5348 [1 << 17]byte +var z5349 [1 << 17]byte +var z5350 [1 << 17]byte +var z5351 [1 << 17]byte +var z5352 [1 << 17]byte +var z5353 [1 << 17]byte +var z5354 [1 << 17]byte +var z5355 [1 << 17]byte +var z5356 [1 << 17]byte +var z5357 [1 << 17]byte +var z5358 [1 << 17]byte +var z5359 [1 << 17]byte +var z5360 [1 << 17]byte +var z5361 [1 << 17]byte +var z5362 [1 << 17]byte +var z5363 [1 << 17]byte +var z5364 [1 << 17]byte +var z5365 [1 << 17]byte +var z5366 [1 << 17]byte +var z5367 [1 << 17]byte +var z5368 [1 << 17]byte +var z5369 [1 << 17]byte +var z5370 [1 << 17]byte +var z5371 [1 << 17]byte +var z5372 [1 << 17]byte +var z5373 [1 << 17]byte +var z5374 [1 << 17]byte +var z5375 [1 << 17]byte +var z5376 [1 << 17]byte +var z5377 [1 << 17]byte +var z5378 [1 << 17]byte +var z5379 [1 << 17]byte +var z5380 [1 << 17]byte +var z5381 [1 << 17]byte +var z5382 [1 << 17]byte +var z5383 [1 << 17]byte +var z5384 [1 << 17]byte +var z5385 [1 << 17]byte +var z5386 [1 << 17]byte +var z5387 [1 << 17]byte +var z5388 [1 << 17]byte +var z5389 [1 << 17]byte +var z5390 [1 << 17]byte +var z5391 [1 << 17]byte +var z5392 [1 << 17]byte +var z5393 [1 << 17]byte +var z5394 [1 << 17]byte +var z5395 [1 << 17]byte +var z5396 [1 << 17]byte +var z5397 [1 << 17]byte +var z5398 [1 << 17]byte +var z5399 [1 << 17]byte +var z5400 [1 << 17]byte +var z5401 [1 << 17]byte +var z5402 [1 << 17]byte +var z5403 [1 << 17]byte +var z5404 [1 << 17]byte +var z5405 [1 << 17]byte +var z5406 [1 << 17]byte +var z5407 [1 << 17]byte +var z5408 [1 << 17]byte +var z5409 [1 << 17]byte +var z5410 [1 << 17]byte +var z5411 [1 << 17]byte +var z5412 [1 << 17]byte +var z5413 [1 << 17]byte +var z5414 [1 << 17]byte +var z5415 [1 << 17]byte +var z5416 [1 << 17]byte +var z5417 [1 << 17]byte +var z5418 [1 << 17]byte +var z5419 [1 << 17]byte +var z5420 [1 << 17]byte +var z5421 [1 << 17]byte +var z5422 [1 << 17]byte +var z5423 [1 << 17]byte +var z5424 [1 << 17]byte +var z5425 [1 << 17]byte +var z5426 [1 << 17]byte +var z5427 [1 << 17]byte +var z5428 [1 << 17]byte +var z5429 [1 << 17]byte +var z5430 [1 << 17]byte +var z5431 [1 << 17]byte +var z5432 [1 << 17]byte +var z5433 [1 << 17]byte +var z5434 [1 << 17]byte +var z5435 [1 << 17]byte +var z5436 [1 << 17]byte +var z5437 [1 << 17]byte +var z5438 [1 << 17]byte +var z5439 [1 << 17]byte +var z5440 [1 << 17]byte +var z5441 [1 << 17]byte +var z5442 [1 << 17]byte +var z5443 [1 << 17]byte +var z5444 [1 << 17]byte +var z5445 [1 << 17]byte +var z5446 [1 << 17]byte +var z5447 [1 << 17]byte +var z5448 [1 << 17]byte +var z5449 [1 << 17]byte +var z5450 [1 << 17]byte +var z5451 [1 << 17]byte +var z5452 [1 << 17]byte +var z5453 [1 << 17]byte +var z5454 [1 << 17]byte +var z5455 [1 << 17]byte +var z5456 [1 << 17]byte +var z5457 [1 << 17]byte +var z5458 [1 << 17]byte +var z5459 [1 << 17]byte +var z5460 [1 << 17]byte +var z5461 [1 << 17]byte +var z5462 [1 << 17]byte +var z5463 [1 << 17]byte +var z5464 [1 << 17]byte +var z5465 [1 << 17]byte +var z5466 [1 << 17]byte +var z5467 [1 << 17]byte +var z5468 [1 << 17]byte +var z5469 [1 << 17]byte +var z5470 [1 << 17]byte +var z5471 [1 << 17]byte +var z5472 [1 << 17]byte +var z5473 [1 << 17]byte +var z5474 [1 << 17]byte +var z5475 [1 << 17]byte +var z5476 [1 << 17]byte +var z5477 [1 << 17]byte +var z5478 [1 << 17]byte +var z5479 [1 << 17]byte +var z5480 [1 << 17]byte +var z5481 [1 << 17]byte +var z5482 [1 << 17]byte +var z5483 [1 << 17]byte +var z5484 [1 << 17]byte +var z5485 [1 << 17]byte +var z5486 [1 << 17]byte +var z5487 [1 << 17]byte +var z5488 [1 << 17]byte +var z5489 [1 << 17]byte +var z5490 [1 << 17]byte +var z5491 [1 << 17]byte +var z5492 [1 << 17]byte +var z5493 [1 << 17]byte +var z5494 [1 << 17]byte +var z5495 [1 << 17]byte +var z5496 [1 << 17]byte +var z5497 [1 << 17]byte +var z5498 [1 << 17]byte +var z5499 [1 << 17]byte +var z5500 [1 << 17]byte +var z5501 [1 << 17]byte +var z5502 [1 << 17]byte +var z5503 [1 << 17]byte +var z5504 [1 << 17]byte +var z5505 [1 << 17]byte +var z5506 [1 << 17]byte +var z5507 [1 << 17]byte +var z5508 [1 << 17]byte +var z5509 [1 << 17]byte +var z5510 [1 << 17]byte +var z5511 [1 << 17]byte +var z5512 [1 << 17]byte +var z5513 [1 << 17]byte +var z5514 [1 << 17]byte +var z5515 [1 << 17]byte +var z5516 [1 << 17]byte +var z5517 [1 << 17]byte +var z5518 [1 << 17]byte +var z5519 [1 << 17]byte +var z5520 [1 << 17]byte +var z5521 [1 << 17]byte +var z5522 [1 << 17]byte +var z5523 [1 << 17]byte +var z5524 [1 << 17]byte +var z5525 [1 << 17]byte +var z5526 [1 << 17]byte +var z5527 [1 << 17]byte +var z5528 [1 << 17]byte +var z5529 [1 << 17]byte +var z5530 [1 << 17]byte +var z5531 [1 << 17]byte +var z5532 [1 << 17]byte +var z5533 [1 << 17]byte +var z5534 [1 << 17]byte +var z5535 [1 << 17]byte +var z5536 [1 << 17]byte +var z5537 [1 << 17]byte +var z5538 [1 << 17]byte +var z5539 [1 << 17]byte +var z5540 [1 << 17]byte +var z5541 [1 << 17]byte +var z5542 [1 << 17]byte +var z5543 [1 << 17]byte +var z5544 [1 << 17]byte +var z5545 [1 << 17]byte +var z5546 [1 << 17]byte +var z5547 [1 << 17]byte +var z5548 [1 << 17]byte +var z5549 [1 << 17]byte +var z5550 [1 << 17]byte +var z5551 [1 << 17]byte +var z5552 [1 << 17]byte +var z5553 [1 << 17]byte +var z5554 [1 << 17]byte +var z5555 [1 << 17]byte +var z5556 [1 << 17]byte +var z5557 [1 << 17]byte +var z5558 [1 << 17]byte +var z5559 [1 << 17]byte +var z5560 [1 << 17]byte +var z5561 [1 << 17]byte +var z5562 [1 << 17]byte +var z5563 [1 << 17]byte +var z5564 [1 << 17]byte +var z5565 [1 << 17]byte +var z5566 [1 << 17]byte +var z5567 [1 << 17]byte +var z5568 [1 << 17]byte +var z5569 [1 << 17]byte +var z5570 [1 << 17]byte +var z5571 [1 << 17]byte +var z5572 [1 << 17]byte +var z5573 [1 << 17]byte +var z5574 [1 << 17]byte +var z5575 [1 << 17]byte +var z5576 [1 << 17]byte +var z5577 [1 << 17]byte +var z5578 [1 << 17]byte +var z5579 [1 << 17]byte +var z5580 [1 << 17]byte +var z5581 [1 << 17]byte +var z5582 [1 << 17]byte +var z5583 [1 << 17]byte +var z5584 [1 << 17]byte +var z5585 [1 << 17]byte +var z5586 [1 << 17]byte +var z5587 [1 << 17]byte +var z5588 [1 << 17]byte +var z5589 [1 << 17]byte +var z5590 [1 << 17]byte +var z5591 [1 << 17]byte +var z5592 [1 << 17]byte +var z5593 [1 << 17]byte +var z5594 [1 << 17]byte +var z5595 [1 << 17]byte +var z5596 [1 << 17]byte +var z5597 [1 << 17]byte +var z5598 [1 << 17]byte +var z5599 [1 << 17]byte +var z5600 [1 << 17]byte +var z5601 [1 << 17]byte +var z5602 [1 << 17]byte +var z5603 [1 << 17]byte +var z5604 [1 << 17]byte +var z5605 [1 << 17]byte +var z5606 [1 << 17]byte +var z5607 [1 << 17]byte +var z5608 [1 << 17]byte +var z5609 [1 << 17]byte +var z5610 [1 << 17]byte +var z5611 [1 << 17]byte +var z5612 [1 << 17]byte +var z5613 [1 << 17]byte +var z5614 [1 << 17]byte +var z5615 [1 << 17]byte +var z5616 [1 << 17]byte +var z5617 [1 << 17]byte +var z5618 [1 << 17]byte +var z5619 [1 << 17]byte +var z5620 [1 << 17]byte +var z5621 [1 << 17]byte +var z5622 [1 << 17]byte +var z5623 [1 << 17]byte +var z5624 [1 << 17]byte +var z5625 [1 << 17]byte +var z5626 [1 << 17]byte +var z5627 [1 << 17]byte +var z5628 [1 << 17]byte +var z5629 [1 << 17]byte +var z5630 [1 << 17]byte +var z5631 [1 << 17]byte +var z5632 [1 << 17]byte +var z5633 [1 << 17]byte +var z5634 [1 << 17]byte +var z5635 [1 << 17]byte +var z5636 [1 << 17]byte +var z5637 [1 << 17]byte +var z5638 [1 << 17]byte +var z5639 [1 << 17]byte +var z5640 [1 << 17]byte +var z5641 [1 << 17]byte +var z5642 [1 << 17]byte +var z5643 [1 << 17]byte +var z5644 [1 << 17]byte +var z5645 [1 << 17]byte +var z5646 [1 << 17]byte +var z5647 [1 << 17]byte +var z5648 [1 << 17]byte +var z5649 [1 << 17]byte +var z5650 [1 << 17]byte +var z5651 [1 << 17]byte +var z5652 [1 << 17]byte +var z5653 [1 << 17]byte +var z5654 [1 << 17]byte +var z5655 [1 << 17]byte +var z5656 [1 << 17]byte +var z5657 [1 << 17]byte +var z5658 [1 << 17]byte +var z5659 [1 << 17]byte +var z5660 [1 << 17]byte +var z5661 [1 << 17]byte +var z5662 [1 << 17]byte +var z5663 [1 << 17]byte +var z5664 [1 << 17]byte +var z5665 [1 << 17]byte +var z5666 [1 << 17]byte +var z5667 [1 << 17]byte +var z5668 [1 << 17]byte +var z5669 [1 << 17]byte +var z5670 [1 << 17]byte +var z5671 [1 << 17]byte +var z5672 [1 << 17]byte +var z5673 [1 << 17]byte +var z5674 [1 << 17]byte +var z5675 [1 << 17]byte +var z5676 [1 << 17]byte +var z5677 [1 << 17]byte +var z5678 [1 << 17]byte +var z5679 [1 << 17]byte +var z5680 [1 << 17]byte +var z5681 [1 << 17]byte +var z5682 [1 << 17]byte +var z5683 [1 << 17]byte +var z5684 [1 << 17]byte +var z5685 [1 << 17]byte +var z5686 [1 << 17]byte +var z5687 [1 << 17]byte +var z5688 [1 << 17]byte +var z5689 [1 << 17]byte +var z5690 [1 << 17]byte +var z5691 [1 << 17]byte +var z5692 [1 << 17]byte +var z5693 [1 << 17]byte +var z5694 [1 << 17]byte +var z5695 [1 << 17]byte +var z5696 [1 << 17]byte +var z5697 [1 << 17]byte +var z5698 [1 << 17]byte +var z5699 [1 << 17]byte +var z5700 [1 << 17]byte +var z5701 [1 << 17]byte +var z5702 [1 << 17]byte +var z5703 [1 << 17]byte +var z5704 [1 << 17]byte +var z5705 [1 << 17]byte +var z5706 [1 << 17]byte +var z5707 [1 << 17]byte +var z5708 [1 << 17]byte +var z5709 [1 << 17]byte +var z5710 [1 << 17]byte +var z5711 [1 << 17]byte +var z5712 [1 << 17]byte +var z5713 [1 << 17]byte +var z5714 [1 << 17]byte +var z5715 [1 << 17]byte +var z5716 [1 << 17]byte +var z5717 [1 << 17]byte +var z5718 [1 << 17]byte +var z5719 [1 << 17]byte +var z5720 [1 << 17]byte +var z5721 [1 << 17]byte +var z5722 [1 << 17]byte +var z5723 [1 << 17]byte +var z5724 [1 << 17]byte +var z5725 [1 << 17]byte +var z5726 [1 << 17]byte +var z5727 [1 << 17]byte +var z5728 [1 << 17]byte +var z5729 [1 << 17]byte +var z5730 [1 << 17]byte +var z5731 [1 << 17]byte +var z5732 [1 << 17]byte +var z5733 [1 << 17]byte +var z5734 [1 << 17]byte +var z5735 [1 << 17]byte +var z5736 [1 << 17]byte +var z5737 [1 << 17]byte +var z5738 [1 << 17]byte +var z5739 [1 << 17]byte +var z5740 [1 << 17]byte +var z5741 [1 << 17]byte +var z5742 [1 << 17]byte +var z5743 [1 << 17]byte +var z5744 [1 << 17]byte +var z5745 [1 << 17]byte +var z5746 [1 << 17]byte +var z5747 [1 << 17]byte +var z5748 [1 << 17]byte +var z5749 [1 << 17]byte +var z5750 [1 << 17]byte +var z5751 [1 << 17]byte +var z5752 [1 << 17]byte +var z5753 [1 << 17]byte +var z5754 [1 << 17]byte +var z5755 [1 << 17]byte +var z5756 [1 << 17]byte +var z5757 [1 << 17]byte +var z5758 [1 << 17]byte +var z5759 [1 << 17]byte +var z5760 [1 << 17]byte +var z5761 [1 << 17]byte +var z5762 [1 << 17]byte +var z5763 [1 << 17]byte +var z5764 [1 << 17]byte +var z5765 [1 << 17]byte +var z5766 [1 << 17]byte +var z5767 [1 << 17]byte +var z5768 [1 << 17]byte +var z5769 [1 << 17]byte +var z5770 [1 << 17]byte +var z5771 [1 << 17]byte +var z5772 [1 << 17]byte +var z5773 [1 << 17]byte +var z5774 [1 << 17]byte +var z5775 [1 << 17]byte +var z5776 [1 << 17]byte +var z5777 [1 << 17]byte +var z5778 [1 << 17]byte +var z5779 [1 << 17]byte +var z5780 [1 << 17]byte +var z5781 [1 << 17]byte +var z5782 [1 << 17]byte +var z5783 [1 << 17]byte +var z5784 [1 << 17]byte +var z5785 [1 << 17]byte +var z5786 [1 << 17]byte +var z5787 [1 << 17]byte +var z5788 [1 << 17]byte +var z5789 [1 << 17]byte +var z5790 [1 << 17]byte +var z5791 [1 << 17]byte +var z5792 [1 << 17]byte +var z5793 [1 << 17]byte +var z5794 [1 << 17]byte +var z5795 [1 << 17]byte +var z5796 [1 << 17]byte +var z5797 [1 << 17]byte +var z5798 [1 << 17]byte +var z5799 [1 << 17]byte +var z5800 [1 << 17]byte +var z5801 [1 << 17]byte +var z5802 [1 << 17]byte +var z5803 [1 << 17]byte +var z5804 [1 << 17]byte +var z5805 [1 << 17]byte +var z5806 [1 << 17]byte +var z5807 [1 << 17]byte +var z5808 [1 << 17]byte +var z5809 [1 << 17]byte +var z5810 [1 << 17]byte +var z5811 [1 << 17]byte +var z5812 [1 << 17]byte +var z5813 [1 << 17]byte +var z5814 [1 << 17]byte +var z5815 [1 << 17]byte +var z5816 [1 << 17]byte +var z5817 [1 << 17]byte +var z5818 [1 << 17]byte +var z5819 [1 << 17]byte +var z5820 [1 << 17]byte +var z5821 [1 << 17]byte +var z5822 [1 << 17]byte +var z5823 [1 << 17]byte +var z5824 [1 << 17]byte +var z5825 [1 << 17]byte +var z5826 [1 << 17]byte +var z5827 [1 << 17]byte +var z5828 [1 << 17]byte +var z5829 [1 << 17]byte +var z5830 [1 << 17]byte +var z5831 [1 << 17]byte +var z5832 [1 << 17]byte +var z5833 [1 << 17]byte +var z5834 [1 << 17]byte +var z5835 [1 << 17]byte +var z5836 [1 << 17]byte +var z5837 [1 << 17]byte +var z5838 [1 << 17]byte +var z5839 [1 << 17]byte +var z5840 [1 << 17]byte +var z5841 [1 << 17]byte +var z5842 [1 << 17]byte +var z5843 [1 << 17]byte +var z5844 [1 << 17]byte +var z5845 [1 << 17]byte +var z5846 [1 << 17]byte +var z5847 [1 << 17]byte +var z5848 [1 << 17]byte +var z5849 [1 << 17]byte +var z5850 [1 << 17]byte +var z5851 [1 << 17]byte +var z5852 [1 << 17]byte +var z5853 [1 << 17]byte +var z5854 [1 << 17]byte +var z5855 [1 << 17]byte +var z5856 [1 << 17]byte +var z5857 [1 << 17]byte +var z5858 [1 << 17]byte +var z5859 [1 << 17]byte +var z5860 [1 << 17]byte +var z5861 [1 << 17]byte +var z5862 [1 << 17]byte +var z5863 [1 << 17]byte +var z5864 [1 << 17]byte +var z5865 [1 << 17]byte +var z5866 [1 << 17]byte +var z5867 [1 << 17]byte +var z5868 [1 << 17]byte +var z5869 [1 << 17]byte +var z5870 [1 << 17]byte +var z5871 [1 << 17]byte +var z5872 [1 << 17]byte +var z5873 [1 << 17]byte +var z5874 [1 << 17]byte +var z5875 [1 << 17]byte +var z5876 [1 << 17]byte +var z5877 [1 << 17]byte +var z5878 [1 << 17]byte +var z5879 [1 << 17]byte +var z5880 [1 << 17]byte +var z5881 [1 << 17]byte +var z5882 [1 << 17]byte +var z5883 [1 << 17]byte +var z5884 [1 << 17]byte +var z5885 [1 << 17]byte +var z5886 [1 << 17]byte +var z5887 [1 << 17]byte +var z5888 [1 << 17]byte +var z5889 [1 << 17]byte +var z5890 [1 << 17]byte +var z5891 [1 << 17]byte +var z5892 [1 << 17]byte +var z5893 [1 << 17]byte +var z5894 [1 << 17]byte +var z5895 [1 << 17]byte +var z5896 [1 << 17]byte +var z5897 [1 << 17]byte +var z5898 [1 << 17]byte +var z5899 [1 << 17]byte +var z5900 [1 << 17]byte +var z5901 [1 << 17]byte +var z5902 [1 << 17]byte +var z5903 [1 << 17]byte +var z5904 [1 << 17]byte +var z5905 [1 << 17]byte +var z5906 [1 << 17]byte +var z5907 [1 << 17]byte +var z5908 [1 << 17]byte +var z5909 [1 << 17]byte +var z5910 [1 << 17]byte +var z5911 [1 << 17]byte +var z5912 [1 << 17]byte +var z5913 [1 << 17]byte +var z5914 [1 << 17]byte +var z5915 [1 << 17]byte +var z5916 [1 << 17]byte +var z5917 [1 << 17]byte +var z5918 [1 << 17]byte +var z5919 [1 << 17]byte +var z5920 [1 << 17]byte +var z5921 [1 << 17]byte +var z5922 [1 << 17]byte +var z5923 [1 << 17]byte +var z5924 [1 << 17]byte +var z5925 [1 << 17]byte +var z5926 [1 << 17]byte +var z5927 [1 << 17]byte +var z5928 [1 << 17]byte +var z5929 [1 << 17]byte +var z5930 [1 << 17]byte +var z5931 [1 << 17]byte +var z5932 [1 << 17]byte +var z5933 [1 << 17]byte +var z5934 [1 << 17]byte +var z5935 [1 << 17]byte +var z5936 [1 << 17]byte +var z5937 [1 << 17]byte +var z5938 [1 << 17]byte +var z5939 [1 << 17]byte +var z5940 [1 << 17]byte +var z5941 [1 << 17]byte +var z5942 [1 << 17]byte +var z5943 [1 << 17]byte +var z5944 [1 << 17]byte +var z5945 [1 << 17]byte +var z5946 [1 << 17]byte +var z5947 [1 << 17]byte +var z5948 [1 << 17]byte +var z5949 [1 << 17]byte +var z5950 [1 << 17]byte +var z5951 [1 << 17]byte +var z5952 [1 << 17]byte +var z5953 [1 << 17]byte +var z5954 [1 << 17]byte +var z5955 [1 << 17]byte +var z5956 [1 << 17]byte +var z5957 [1 << 17]byte +var z5958 [1 << 17]byte +var z5959 [1 << 17]byte +var z5960 [1 << 17]byte +var z5961 [1 << 17]byte +var z5962 [1 << 17]byte +var z5963 [1 << 17]byte +var z5964 [1 << 17]byte +var z5965 [1 << 17]byte +var z5966 [1 << 17]byte +var z5967 [1 << 17]byte +var z5968 [1 << 17]byte +var z5969 [1 << 17]byte +var z5970 [1 << 17]byte +var z5971 [1 << 17]byte +var z5972 [1 << 17]byte +var z5973 [1 << 17]byte +var z5974 [1 << 17]byte +var z5975 [1 << 17]byte +var z5976 [1 << 17]byte +var z5977 [1 << 17]byte +var z5978 [1 << 17]byte +var z5979 [1 << 17]byte +var z5980 [1 << 17]byte +var z5981 [1 << 17]byte +var z5982 [1 << 17]byte +var z5983 [1 << 17]byte +var z5984 [1 << 17]byte +var z5985 [1 << 17]byte +var z5986 [1 << 17]byte +var z5987 [1 << 17]byte +var z5988 [1 << 17]byte +var z5989 [1 << 17]byte +var z5990 [1 << 17]byte +var z5991 [1 << 17]byte +var z5992 [1 << 17]byte +var z5993 [1 << 17]byte +var z5994 [1 << 17]byte +var z5995 [1 << 17]byte +var z5996 [1 << 17]byte +var z5997 [1 << 17]byte +var z5998 [1 << 17]byte +var z5999 [1 << 17]byte +var z6000 [1 << 17]byte +var z6001 [1 << 17]byte +var z6002 [1 << 17]byte +var z6003 [1 << 17]byte +var z6004 [1 << 17]byte +var z6005 [1 << 17]byte +var z6006 [1 << 17]byte +var z6007 [1 << 17]byte +var z6008 [1 << 17]byte +var z6009 [1 << 17]byte +var z6010 [1 << 17]byte +var z6011 [1 << 17]byte +var z6012 [1 << 17]byte +var z6013 [1 << 17]byte +var z6014 [1 << 17]byte +var z6015 [1 << 17]byte +var z6016 [1 << 17]byte +var z6017 [1 << 17]byte +var z6018 [1 << 17]byte +var z6019 [1 << 17]byte +var z6020 [1 << 17]byte +var z6021 [1 << 17]byte +var z6022 [1 << 17]byte +var z6023 [1 << 17]byte +var z6024 [1 << 17]byte +var z6025 [1 << 17]byte +var z6026 [1 << 17]byte +var z6027 [1 << 17]byte +var z6028 [1 << 17]byte +var z6029 [1 << 17]byte +var z6030 [1 << 17]byte +var z6031 [1 << 17]byte +var z6032 [1 << 17]byte +var z6033 [1 << 17]byte +var z6034 [1 << 17]byte +var z6035 [1 << 17]byte +var z6036 [1 << 17]byte +var z6037 [1 << 17]byte +var z6038 [1 << 17]byte +var z6039 [1 << 17]byte +var z6040 [1 << 17]byte +var z6041 [1 << 17]byte +var z6042 [1 << 17]byte +var z6043 [1 << 17]byte +var z6044 [1 << 17]byte +var z6045 [1 << 17]byte +var z6046 [1 << 17]byte +var z6047 [1 << 17]byte +var z6048 [1 << 17]byte +var z6049 [1 << 17]byte +var z6050 [1 << 17]byte +var z6051 [1 << 17]byte +var z6052 [1 << 17]byte +var z6053 [1 << 17]byte +var z6054 [1 << 17]byte +var z6055 [1 << 17]byte +var z6056 [1 << 17]byte +var z6057 [1 << 17]byte +var z6058 [1 << 17]byte +var z6059 [1 << 17]byte +var z6060 [1 << 17]byte +var z6061 [1 << 17]byte +var z6062 [1 << 17]byte +var z6063 [1 << 17]byte +var z6064 [1 << 17]byte +var z6065 [1 << 17]byte +var z6066 [1 << 17]byte +var z6067 [1 << 17]byte +var z6068 [1 << 17]byte +var z6069 [1 << 17]byte +var z6070 [1 << 17]byte +var z6071 [1 << 17]byte +var z6072 [1 << 17]byte +var z6073 [1 << 17]byte +var z6074 [1 << 17]byte +var z6075 [1 << 17]byte +var z6076 [1 << 17]byte +var z6077 [1 << 17]byte +var z6078 [1 << 17]byte +var z6079 [1 << 17]byte +var z6080 [1 << 17]byte +var z6081 [1 << 17]byte +var z6082 [1 << 17]byte +var z6083 [1 << 17]byte +var z6084 [1 << 17]byte +var z6085 [1 << 17]byte +var z6086 [1 << 17]byte +var z6087 [1 << 17]byte +var z6088 [1 << 17]byte +var z6089 [1 << 17]byte +var z6090 [1 << 17]byte +var z6091 [1 << 17]byte +var z6092 [1 << 17]byte +var z6093 [1 << 17]byte +var z6094 [1 << 17]byte +var z6095 [1 << 17]byte +var z6096 [1 << 17]byte +var z6097 [1 << 17]byte +var z6098 [1 << 17]byte +var z6099 [1 << 17]byte +var z6100 [1 << 17]byte +var z6101 [1 << 17]byte +var z6102 [1 << 17]byte +var z6103 [1 << 17]byte +var z6104 [1 << 17]byte +var z6105 [1 << 17]byte +var z6106 [1 << 17]byte +var z6107 [1 << 17]byte +var z6108 [1 << 17]byte +var z6109 [1 << 17]byte +var z6110 [1 << 17]byte +var z6111 [1 << 17]byte +var z6112 [1 << 17]byte +var z6113 [1 << 17]byte +var z6114 [1 << 17]byte +var z6115 [1 << 17]byte +var z6116 [1 << 17]byte +var z6117 [1 << 17]byte +var z6118 [1 << 17]byte +var z6119 [1 << 17]byte +var z6120 [1 << 17]byte +var z6121 [1 << 17]byte +var z6122 [1 << 17]byte +var z6123 [1 << 17]byte +var z6124 [1 << 17]byte +var z6125 [1 << 17]byte +var z6126 [1 << 17]byte +var z6127 [1 << 17]byte +var z6128 [1 << 17]byte +var z6129 [1 << 17]byte +var z6130 [1 << 17]byte +var z6131 [1 << 17]byte +var z6132 [1 << 17]byte +var z6133 [1 << 17]byte +var z6134 [1 << 17]byte +var z6135 [1 << 17]byte +var z6136 [1 << 17]byte +var z6137 [1 << 17]byte +var z6138 [1 << 17]byte +var z6139 [1 << 17]byte +var z6140 [1 << 17]byte +var z6141 [1 << 17]byte +var z6142 [1 << 17]byte +var z6143 [1 << 17]byte +var z6144 [1 << 17]byte +var z6145 [1 << 17]byte +var z6146 [1 << 17]byte +var z6147 [1 << 17]byte +var z6148 [1 << 17]byte +var z6149 [1 << 17]byte +var z6150 [1 << 17]byte +var z6151 [1 << 17]byte +var z6152 [1 << 17]byte +var z6153 [1 << 17]byte +var z6154 [1 << 17]byte +var z6155 [1 << 17]byte +var z6156 [1 << 17]byte +var z6157 [1 << 17]byte +var z6158 [1 << 17]byte +var z6159 [1 << 17]byte +var z6160 [1 << 17]byte +var z6161 [1 << 17]byte +var z6162 [1 << 17]byte +var z6163 [1 << 17]byte +var z6164 [1 << 17]byte +var z6165 [1 << 17]byte +var z6166 [1 << 17]byte +var z6167 [1 << 17]byte +var z6168 [1 << 17]byte +var z6169 [1 << 17]byte +var z6170 [1 << 17]byte +var z6171 [1 << 17]byte +var z6172 [1 << 17]byte +var z6173 [1 << 17]byte +var z6174 [1 << 17]byte +var z6175 [1 << 17]byte +var z6176 [1 << 17]byte +var z6177 [1 << 17]byte +var z6178 [1 << 17]byte +var z6179 [1 << 17]byte +var z6180 [1 << 17]byte +var z6181 [1 << 17]byte +var z6182 [1 << 17]byte +var z6183 [1 << 17]byte +var z6184 [1 << 17]byte +var z6185 [1 << 17]byte +var z6186 [1 << 17]byte +var z6187 [1 << 17]byte +var z6188 [1 << 17]byte +var z6189 [1 << 17]byte +var z6190 [1 << 17]byte +var z6191 [1 << 17]byte +var z6192 [1 << 17]byte +var z6193 [1 << 17]byte +var z6194 [1 << 17]byte +var z6195 [1 << 17]byte +var z6196 [1 << 17]byte +var z6197 [1 << 17]byte +var z6198 [1 << 17]byte +var z6199 [1 << 17]byte +var z6200 [1 << 17]byte +var z6201 [1 << 17]byte +var z6202 [1 << 17]byte +var z6203 [1 << 17]byte +var z6204 [1 << 17]byte +var z6205 [1 << 17]byte +var z6206 [1 << 17]byte +var z6207 [1 << 17]byte +var z6208 [1 << 17]byte +var z6209 [1 << 17]byte +var z6210 [1 << 17]byte +var z6211 [1 << 17]byte +var z6212 [1 << 17]byte +var z6213 [1 << 17]byte +var z6214 [1 << 17]byte +var z6215 [1 << 17]byte +var z6216 [1 << 17]byte +var z6217 [1 << 17]byte +var z6218 [1 << 17]byte +var z6219 [1 << 17]byte +var z6220 [1 << 17]byte +var z6221 [1 << 17]byte +var z6222 [1 << 17]byte +var z6223 [1 << 17]byte +var z6224 [1 << 17]byte +var z6225 [1 << 17]byte +var z6226 [1 << 17]byte +var z6227 [1 << 17]byte +var z6228 [1 << 17]byte +var z6229 [1 << 17]byte +var z6230 [1 << 17]byte +var z6231 [1 << 17]byte +var z6232 [1 << 17]byte +var z6233 [1 << 17]byte +var z6234 [1 << 17]byte +var z6235 [1 << 17]byte +var z6236 [1 << 17]byte +var z6237 [1 << 17]byte +var z6238 [1 << 17]byte +var z6239 [1 << 17]byte +var z6240 [1 << 17]byte +var z6241 [1 << 17]byte +var z6242 [1 << 17]byte +var z6243 [1 << 17]byte +var z6244 [1 << 17]byte +var z6245 [1 << 17]byte +var z6246 [1 << 17]byte +var z6247 [1 << 17]byte +var z6248 [1 << 17]byte +var z6249 [1 << 17]byte +var z6250 [1 << 17]byte +var z6251 [1 << 17]byte +var z6252 [1 << 17]byte +var z6253 [1 << 17]byte +var z6254 [1 << 17]byte +var z6255 [1 << 17]byte +var z6256 [1 << 17]byte +var z6257 [1 << 17]byte +var z6258 [1 << 17]byte +var z6259 [1 << 17]byte +var z6260 [1 << 17]byte +var z6261 [1 << 17]byte +var z6262 [1 << 17]byte +var z6263 [1 << 17]byte +var z6264 [1 << 17]byte +var z6265 [1 << 17]byte +var z6266 [1 << 17]byte +var z6267 [1 << 17]byte +var z6268 [1 << 17]byte +var z6269 [1 << 17]byte +var z6270 [1 << 17]byte +var z6271 [1 << 17]byte +var z6272 [1 << 17]byte +var z6273 [1 << 17]byte +var z6274 [1 << 17]byte +var z6275 [1 << 17]byte +var z6276 [1 << 17]byte +var z6277 [1 << 17]byte +var z6278 [1 << 17]byte +var z6279 [1 << 17]byte +var z6280 [1 << 17]byte +var z6281 [1 << 17]byte +var z6282 [1 << 17]byte +var z6283 [1 << 17]byte +var z6284 [1 << 17]byte +var z6285 [1 << 17]byte +var z6286 [1 << 17]byte +var z6287 [1 << 17]byte +var z6288 [1 << 17]byte +var z6289 [1 << 17]byte +var z6290 [1 << 17]byte +var z6291 [1 << 17]byte +var z6292 [1 << 17]byte +var z6293 [1 << 17]byte +var z6294 [1 << 17]byte +var z6295 [1 << 17]byte +var z6296 [1 << 17]byte +var z6297 [1 << 17]byte +var z6298 [1 << 17]byte +var z6299 [1 << 17]byte +var z6300 [1 << 17]byte +var z6301 [1 << 17]byte +var z6302 [1 << 17]byte +var z6303 [1 << 17]byte +var z6304 [1 << 17]byte +var z6305 [1 << 17]byte +var z6306 [1 << 17]byte +var z6307 [1 << 17]byte +var z6308 [1 << 17]byte +var z6309 [1 << 17]byte +var z6310 [1 << 17]byte +var z6311 [1 << 17]byte +var z6312 [1 << 17]byte +var z6313 [1 << 17]byte +var z6314 [1 << 17]byte +var z6315 [1 << 17]byte +var z6316 [1 << 17]byte +var z6317 [1 << 17]byte +var z6318 [1 << 17]byte +var z6319 [1 << 17]byte +var z6320 [1 << 17]byte +var z6321 [1 << 17]byte +var z6322 [1 << 17]byte +var z6323 [1 << 17]byte +var z6324 [1 << 17]byte +var z6325 [1 << 17]byte +var z6326 [1 << 17]byte +var z6327 [1 << 17]byte +var z6328 [1 << 17]byte +var z6329 [1 << 17]byte +var z6330 [1 << 17]byte +var z6331 [1 << 17]byte +var z6332 [1 << 17]byte +var z6333 [1 << 17]byte +var z6334 [1 << 17]byte +var z6335 [1 << 17]byte +var z6336 [1 << 17]byte +var z6337 [1 << 17]byte +var z6338 [1 << 17]byte +var z6339 [1 << 17]byte +var z6340 [1 << 17]byte +var z6341 [1 << 17]byte +var z6342 [1 << 17]byte +var z6343 [1 << 17]byte +var z6344 [1 << 17]byte +var z6345 [1 << 17]byte +var z6346 [1 << 17]byte +var z6347 [1 << 17]byte +var z6348 [1 << 17]byte +var z6349 [1 << 17]byte +var z6350 [1 << 17]byte +var z6351 [1 << 17]byte +var z6352 [1 << 17]byte +var z6353 [1 << 17]byte +var z6354 [1 << 17]byte +var z6355 [1 << 17]byte +var z6356 [1 << 17]byte +var z6357 [1 << 17]byte +var z6358 [1 << 17]byte +var z6359 [1 << 17]byte +var z6360 [1 << 17]byte +var z6361 [1 << 17]byte +var z6362 [1 << 17]byte +var z6363 [1 << 17]byte +var z6364 [1 << 17]byte +var z6365 [1 << 17]byte +var z6366 [1 << 17]byte +var z6367 [1 << 17]byte +var z6368 [1 << 17]byte +var z6369 [1 << 17]byte +var z6370 [1 << 17]byte +var z6371 [1 << 17]byte +var z6372 [1 << 17]byte +var z6373 [1 << 17]byte +var z6374 [1 << 17]byte +var z6375 [1 << 17]byte +var z6376 [1 << 17]byte +var z6377 [1 << 17]byte +var z6378 [1 << 17]byte +var z6379 [1 << 17]byte +var z6380 [1 << 17]byte +var z6381 [1 << 17]byte +var z6382 [1 << 17]byte +var z6383 [1 << 17]byte +var z6384 [1 << 17]byte +var z6385 [1 << 17]byte +var z6386 [1 << 17]byte +var z6387 [1 << 17]byte +var z6388 [1 << 17]byte +var z6389 [1 << 17]byte +var z6390 [1 << 17]byte +var z6391 [1 << 17]byte +var z6392 [1 << 17]byte +var z6393 [1 << 17]byte +var z6394 [1 << 17]byte +var z6395 [1 << 17]byte +var z6396 [1 << 17]byte +var z6397 [1 << 17]byte +var z6398 [1 << 17]byte +var z6399 [1 << 17]byte +var z6400 [1 << 17]byte +var z6401 [1 << 17]byte +var z6402 [1 << 17]byte +var z6403 [1 << 17]byte +var z6404 [1 << 17]byte +var z6405 [1 << 17]byte +var z6406 [1 << 17]byte +var z6407 [1 << 17]byte +var z6408 [1 << 17]byte +var z6409 [1 << 17]byte +var z6410 [1 << 17]byte +var z6411 [1 << 17]byte +var z6412 [1 << 17]byte +var z6413 [1 << 17]byte +var z6414 [1 << 17]byte +var z6415 [1 << 17]byte +var z6416 [1 << 17]byte +var z6417 [1 << 17]byte +var z6418 [1 << 17]byte +var z6419 [1 << 17]byte +var z6420 [1 << 17]byte +var z6421 [1 << 17]byte +var z6422 [1 << 17]byte +var z6423 [1 << 17]byte +var z6424 [1 << 17]byte +var z6425 [1 << 17]byte +var z6426 [1 << 17]byte +var z6427 [1 << 17]byte +var z6428 [1 << 17]byte +var z6429 [1 << 17]byte +var z6430 [1 << 17]byte +var z6431 [1 << 17]byte +var z6432 [1 << 17]byte +var z6433 [1 << 17]byte +var z6434 [1 << 17]byte +var z6435 [1 << 17]byte +var z6436 [1 << 17]byte +var z6437 [1 << 17]byte +var z6438 [1 << 17]byte +var z6439 [1 << 17]byte +var z6440 [1 << 17]byte +var z6441 [1 << 17]byte +var z6442 [1 << 17]byte +var z6443 [1 << 17]byte +var z6444 [1 << 17]byte +var z6445 [1 << 17]byte +var z6446 [1 << 17]byte +var z6447 [1 << 17]byte +var z6448 [1 << 17]byte +var z6449 [1 << 17]byte +var z6450 [1 << 17]byte +var z6451 [1 << 17]byte +var z6452 [1 << 17]byte +var z6453 [1 << 17]byte +var z6454 [1 << 17]byte +var z6455 [1 << 17]byte +var z6456 [1 << 17]byte +var z6457 [1 << 17]byte +var z6458 [1 << 17]byte +var z6459 [1 << 17]byte +var z6460 [1 << 17]byte +var z6461 [1 << 17]byte +var z6462 [1 << 17]byte +var z6463 [1 << 17]byte +var z6464 [1 << 17]byte +var z6465 [1 << 17]byte +var z6466 [1 << 17]byte +var z6467 [1 << 17]byte +var z6468 [1 << 17]byte +var z6469 [1 << 17]byte +var z6470 [1 << 17]byte +var z6471 [1 << 17]byte +var z6472 [1 << 17]byte +var z6473 [1 << 17]byte +var z6474 [1 << 17]byte +var z6475 [1 << 17]byte +var z6476 [1 << 17]byte +var z6477 [1 << 17]byte +var z6478 [1 << 17]byte +var z6479 [1 << 17]byte +var z6480 [1 << 17]byte +var z6481 [1 << 17]byte +var z6482 [1 << 17]byte +var z6483 [1 << 17]byte +var z6484 [1 << 17]byte +var z6485 [1 << 17]byte +var z6486 [1 << 17]byte +var z6487 [1 << 17]byte +var z6488 [1 << 17]byte +var z6489 [1 << 17]byte +var z6490 [1 << 17]byte +var z6491 [1 << 17]byte +var z6492 [1 << 17]byte +var z6493 [1 << 17]byte +var z6494 [1 << 17]byte +var z6495 [1 << 17]byte +var z6496 [1 << 17]byte +var z6497 [1 << 17]byte +var z6498 [1 << 17]byte +var z6499 [1 << 17]byte +var z6500 [1 << 17]byte +var z6501 [1 << 17]byte +var z6502 [1 << 17]byte +var z6503 [1 << 17]byte +var z6504 [1 << 17]byte +var z6505 [1 << 17]byte +var z6506 [1 << 17]byte +var z6507 [1 << 17]byte +var z6508 [1 << 17]byte +var z6509 [1 << 17]byte +var z6510 [1 << 17]byte +var z6511 [1 << 17]byte +var z6512 [1 << 17]byte +var z6513 [1 << 17]byte +var z6514 [1 << 17]byte +var z6515 [1 << 17]byte +var z6516 [1 << 17]byte +var z6517 [1 << 17]byte +var z6518 [1 << 17]byte +var z6519 [1 << 17]byte +var z6520 [1 << 17]byte +var z6521 [1 << 17]byte +var z6522 [1 << 17]byte +var z6523 [1 << 17]byte +var z6524 [1 << 17]byte +var z6525 [1 << 17]byte +var z6526 [1 << 17]byte +var z6527 [1 << 17]byte +var z6528 [1 << 17]byte +var z6529 [1 << 17]byte +var z6530 [1 << 17]byte +var z6531 [1 << 17]byte +var z6532 [1 << 17]byte +var z6533 [1 << 17]byte +var z6534 [1 << 17]byte +var z6535 [1 << 17]byte +var z6536 [1 << 17]byte +var z6537 [1 << 17]byte +var z6538 [1 << 17]byte +var z6539 [1 << 17]byte +var z6540 [1 << 17]byte +var z6541 [1 << 17]byte +var z6542 [1 << 17]byte +var z6543 [1 << 17]byte +var z6544 [1 << 17]byte +var z6545 [1 << 17]byte +var z6546 [1 << 17]byte +var z6547 [1 << 17]byte +var z6548 [1 << 17]byte +var z6549 [1 << 17]byte +var z6550 [1 << 17]byte +var z6551 [1 << 17]byte +var z6552 [1 << 17]byte +var z6553 [1 << 17]byte +var z6554 [1 << 17]byte +var z6555 [1 << 17]byte +var z6556 [1 << 17]byte +var z6557 [1 << 17]byte +var z6558 [1 << 17]byte +var z6559 [1 << 17]byte +var z6560 [1 << 17]byte +var z6561 [1 << 17]byte +var z6562 [1 << 17]byte +var z6563 [1 << 17]byte +var z6564 [1 << 17]byte +var z6565 [1 << 17]byte +var z6566 [1 << 17]byte +var z6567 [1 << 17]byte +var z6568 [1 << 17]byte +var z6569 [1 << 17]byte +var z6570 [1 << 17]byte +var z6571 [1 << 17]byte +var z6572 [1 << 17]byte +var z6573 [1 << 17]byte +var z6574 [1 << 17]byte +var z6575 [1 << 17]byte +var z6576 [1 << 17]byte +var z6577 [1 << 17]byte +var z6578 [1 << 17]byte +var z6579 [1 << 17]byte +var z6580 [1 << 17]byte +var z6581 [1 << 17]byte +var z6582 [1 << 17]byte +var z6583 [1 << 17]byte +var z6584 [1 << 17]byte +var z6585 [1 << 17]byte +var z6586 [1 << 17]byte +var z6587 [1 << 17]byte +var z6588 [1 << 17]byte +var z6589 [1 << 17]byte +var z6590 [1 << 17]byte +var z6591 [1 << 17]byte +var z6592 [1 << 17]byte +var z6593 [1 << 17]byte +var z6594 [1 << 17]byte +var z6595 [1 << 17]byte +var z6596 [1 << 17]byte +var z6597 [1 << 17]byte +var z6598 [1 << 17]byte +var z6599 [1 << 17]byte +var z6600 [1 << 17]byte +var z6601 [1 << 17]byte +var z6602 [1 << 17]byte +var z6603 [1 << 17]byte +var z6604 [1 << 17]byte +var z6605 [1 << 17]byte +var z6606 [1 << 17]byte +var z6607 [1 << 17]byte +var z6608 [1 << 17]byte +var z6609 [1 << 17]byte +var z6610 [1 << 17]byte +var z6611 [1 << 17]byte +var z6612 [1 << 17]byte +var z6613 [1 << 17]byte +var z6614 [1 << 17]byte +var z6615 [1 << 17]byte +var z6616 [1 << 17]byte +var z6617 [1 << 17]byte +var z6618 [1 << 17]byte +var z6619 [1 << 17]byte +var z6620 [1 << 17]byte +var z6621 [1 << 17]byte +var z6622 [1 << 17]byte +var z6623 [1 << 17]byte +var z6624 [1 << 17]byte +var z6625 [1 << 17]byte +var z6626 [1 << 17]byte +var z6627 [1 << 17]byte +var z6628 [1 << 17]byte +var z6629 [1 << 17]byte +var z6630 [1 << 17]byte +var z6631 [1 << 17]byte +var z6632 [1 << 17]byte +var z6633 [1 << 17]byte +var z6634 [1 << 17]byte +var z6635 [1 << 17]byte +var z6636 [1 << 17]byte +var z6637 [1 << 17]byte +var z6638 [1 << 17]byte +var z6639 [1 << 17]byte +var z6640 [1 << 17]byte +var z6641 [1 << 17]byte +var z6642 [1 << 17]byte +var z6643 [1 << 17]byte +var z6644 [1 << 17]byte +var z6645 [1 << 17]byte +var z6646 [1 << 17]byte +var z6647 [1 << 17]byte +var z6648 [1 << 17]byte +var z6649 [1 << 17]byte +var z6650 [1 << 17]byte +var z6651 [1 << 17]byte +var z6652 [1 << 17]byte +var z6653 [1 << 17]byte +var z6654 [1 << 17]byte +var z6655 [1 << 17]byte +var z6656 [1 << 17]byte +var z6657 [1 << 17]byte +var z6658 [1 << 17]byte +var z6659 [1 << 17]byte +var z6660 [1 << 17]byte +var z6661 [1 << 17]byte +var z6662 [1 << 17]byte +var z6663 [1 << 17]byte +var z6664 [1 << 17]byte +var z6665 [1 << 17]byte +var z6666 [1 << 17]byte +var z6667 [1 << 17]byte +var z6668 [1 << 17]byte +var z6669 [1 << 17]byte +var z6670 [1 << 17]byte +var z6671 [1 << 17]byte +var z6672 [1 << 17]byte +var z6673 [1 << 17]byte +var z6674 [1 << 17]byte +var z6675 [1 << 17]byte +var z6676 [1 << 17]byte +var z6677 [1 << 17]byte +var z6678 [1 << 17]byte +var z6679 [1 << 17]byte +var z6680 [1 << 17]byte +var z6681 [1 << 17]byte +var z6682 [1 << 17]byte +var z6683 [1 << 17]byte +var z6684 [1 << 17]byte +var z6685 [1 << 17]byte +var z6686 [1 << 17]byte +var z6687 [1 << 17]byte +var z6688 [1 << 17]byte +var z6689 [1 << 17]byte +var z6690 [1 << 17]byte +var z6691 [1 << 17]byte +var z6692 [1 << 17]byte +var z6693 [1 << 17]byte +var z6694 [1 << 17]byte +var z6695 [1 << 17]byte +var z6696 [1 << 17]byte +var z6697 [1 << 17]byte +var z6698 [1 << 17]byte +var z6699 [1 << 17]byte +var z6700 [1 << 17]byte +var z6701 [1 << 17]byte +var z6702 [1 << 17]byte +var z6703 [1 << 17]byte +var z6704 [1 << 17]byte +var z6705 [1 << 17]byte +var z6706 [1 << 17]byte +var z6707 [1 << 17]byte +var z6708 [1 << 17]byte +var z6709 [1 << 17]byte +var z6710 [1 << 17]byte +var z6711 [1 << 17]byte +var z6712 [1 << 17]byte +var z6713 [1 << 17]byte +var z6714 [1 << 17]byte +var z6715 [1 << 17]byte +var z6716 [1 << 17]byte +var z6717 [1 << 17]byte +var z6718 [1 << 17]byte +var z6719 [1 << 17]byte +var z6720 [1 << 17]byte +var z6721 [1 << 17]byte +var z6722 [1 << 17]byte +var z6723 [1 << 17]byte +var z6724 [1 << 17]byte +var z6725 [1 << 17]byte +var z6726 [1 << 17]byte +var z6727 [1 << 17]byte +var z6728 [1 << 17]byte +var z6729 [1 << 17]byte +var z6730 [1 << 17]byte +var z6731 [1 << 17]byte +var z6732 [1 << 17]byte +var z6733 [1 << 17]byte +var z6734 [1 << 17]byte +var z6735 [1 << 17]byte +var z6736 [1 << 17]byte +var z6737 [1 << 17]byte +var z6738 [1 << 17]byte +var z6739 [1 << 17]byte +var z6740 [1 << 17]byte +var z6741 [1 << 17]byte +var z6742 [1 << 17]byte +var z6743 [1 << 17]byte +var z6744 [1 << 17]byte +var z6745 [1 << 17]byte +var z6746 [1 << 17]byte +var z6747 [1 << 17]byte +var z6748 [1 << 17]byte +var z6749 [1 << 17]byte +var z6750 [1 << 17]byte +var z6751 [1 << 17]byte +var z6752 [1 << 17]byte +var z6753 [1 << 17]byte +var z6754 [1 << 17]byte +var z6755 [1 << 17]byte +var z6756 [1 << 17]byte +var z6757 [1 << 17]byte +var z6758 [1 << 17]byte +var z6759 [1 << 17]byte +var z6760 [1 << 17]byte +var z6761 [1 << 17]byte +var z6762 [1 << 17]byte +var z6763 [1 << 17]byte +var z6764 [1 << 17]byte +var z6765 [1 << 17]byte +var z6766 [1 << 17]byte +var z6767 [1 << 17]byte +var z6768 [1 << 17]byte +var z6769 [1 << 17]byte +var z6770 [1 << 17]byte +var z6771 [1 << 17]byte +var z6772 [1 << 17]byte +var z6773 [1 << 17]byte +var z6774 [1 << 17]byte +var z6775 [1 << 17]byte +var z6776 [1 << 17]byte +var z6777 [1 << 17]byte +var z6778 [1 << 17]byte +var z6779 [1 << 17]byte +var z6780 [1 << 17]byte +var z6781 [1 << 17]byte +var z6782 [1 << 17]byte +var z6783 [1 << 17]byte +var z6784 [1 << 17]byte +var z6785 [1 << 17]byte +var z6786 [1 << 17]byte +var z6787 [1 << 17]byte +var z6788 [1 << 17]byte +var z6789 [1 << 17]byte +var z6790 [1 << 17]byte +var z6791 [1 << 17]byte +var z6792 [1 << 17]byte +var z6793 [1 << 17]byte +var z6794 [1 << 17]byte +var z6795 [1 << 17]byte +var z6796 [1 << 17]byte +var z6797 [1 << 17]byte +var z6798 [1 << 17]byte +var z6799 [1 << 17]byte +var z6800 [1 << 17]byte +var z6801 [1 << 17]byte +var z6802 [1 << 17]byte +var z6803 [1 << 17]byte +var z6804 [1 << 17]byte +var z6805 [1 << 17]byte +var z6806 [1 << 17]byte +var z6807 [1 << 17]byte +var z6808 [1 << 17]byte +var z6809 [1 << 17]byte +var z6810 [1 << 17]byte +var z6811 [1 << 17]byte +var z6812 [1 << 17]byte +var z6813 [1 << 17]byte +var z6814 [1 << 17]byte +var z6815 [1 << 17]byte +var z6816 [1 << 17]byte +var z6817 [1 << 17]byte +var z6818 [1 << 17]byte +var z6819 [1 << 17]byte +var z6820 [1 << 17]byte +var z6821 [1 << 17]byte +var z6822 [1 << 17]byte +var z6823 [1 << 17]byte +var z6824 [1 << 17]byte +var z6825 [1 << 17]byte +var z6826 [1 << 17]byte +var z6827 [1 << 17]byte +var z6828 [1 << 17]byte +var z6829 [1 << 17]byte +var z6830 [1 << 17]byte +var z6831 [1 << 17]byte +var z6832 [1 << 17]byte +var z6833 [1 << 17]byte +var z6834 [1 << 17]byte +var z6835 [1 << 17]byte +var z6836 [1 << 17]byte +var z6837 [1 << 17]byte +var z6838 [1 << 17]byte +var z6839 [1 << 17]byte +var z6840 [1 << 17]byte +var z6841 [1 << 17]byte +var z6842 [1 << 17]byte +var z6843 [1 << 17]byte +var z6844 [1 << 17]byte +var z6845 [1 << 17]byte +var z6846 [1 << 17]byte +var z6847 [1 << 17]byte +var z6848 [1 << 17]byte +var z6849 [1 << 17]byte +var z6850 [1 << 17]byte +var z6851 [1 << 17]byte +var z6852 [1 << 17]byte +var z6853 [1 << 17]byte +var z6854 [1 << 17]byte +var z6855 [1 << 17]byte +var z6856 [1 << 17]byte +var z6857 [1 << 17]byte +var z6858 [1 << 17]byte +var z6859 [1 << 17]byte +var z6860 [1 << 17]byte +var z6861 [1 << 17]byte +var z6862 [1 << 17]byte +var z6863 [1 << 17]byte +var z6864 [1 << 17]byte +var z6865 [1 << 17]byte +var z6866 [1 << 17]byte +var z6867 [1 << 17]byte +var z6868 [1 << 17]byte +var z6869 [1 << 17]byte +var z6870 [1 << 17]byte +var z6871 [1 << 17]byte +var z6872 [1 << 17]byte +var z6873 [1 << 17]byte +var z6874 [1 << 17]byte +var z6875 [1 << 17]byte +var z6876 [1 << 17]byte +var z6877 [1 << 17]byte +var z6878 [1 << 17]byte +var z6879 [1 << 17]byte +var z6880 [1 << 17]byte +var z6881 [1 << 17]byte +var z6882 [1 << 17]byte +var z6883 [1 << 17]byte +var z6884 [1 << 17]byte +var z6885 [1 << 17]byte +var z6886 [1 << 17]byte +var z6887 [1 << 17]byte +var z6888 [1 << 17]byte +var z6889 [1 << 17]byte +var z6890 [1 << 17]byte +var z6891 [1 << 17]byte +var z6892 [1 << 17]byte +var z6893 [1 << 17]byte +var z6894 [1 << 17]byte +var z6895 [1 << 17]byte +var z6896 [1 << 17]byte +var z6897 [1 << 17]byte +var z6898 [1 << 17]byte +var z6899 [1 << 17]byte +var z6900 [1 << 17]byte +var z6901 [1 << 17]byte +var z6902 [1 << 17]byte +var z6903 [1 << 17]byte +var z6904 [1 << 17]byte +var z6905 [1 << 17]byte +var z6906 [1 << 17]byte +var z6907 [1 << 17]byte +var z6908 [1 << 17]byte +var z6909 [1 << 17]byte +var z6910 [1 << 17]byte +var z6911 [1 << 17]byte +var z6912 [1 << 17]byte +var z6913 [1 << 17]byte +var z6914 [1 << 17]byte +var z6915 [1 << 17]byte +var z6916 [1 << 17]byte +var z6917 [1 << 17]byte +var z6918 [1 << 17]byte +var z6919 [1 << 17]byte +var z6920 [1 << 17]byte +var z6921 [1 << 17]byte +var z6922 [1 << 17]byte +var z6923 [1 << 17]byte +var z6924 [1 << 17]byte +var z6925 [1 << 17]byte +var z6926 [1 << 17]byte +var z6927 [1 << 17]byte +var z6928 [1 << 17]byte +var z6929 [1 << 17]byte +var z6930 [1 << 17]byte +var z6931 [1 << 17]byte +var z6932 [1 << 17]byte +var z6933 [1 << 17]byte +var z6934 [1 << 17]byte +var z6935 [1 << 17]byte +var z6936 [1 << 17]byte +var z6937 [1 << 17]byte +var z6938 [1 << 17]byte +var z6939 [1 << 17]byte +var z6940 [1 << 17]byte +var z6941 [1 << 17]byte +var z6942 [1 << 17]byte +var z6943 [1 << 17]byte +var z6944 [1 << 17]byte +var z6945 [1 << 17]byte +var z6946 [1 << 17]byte +var z6947 [1 << 17]byte +var z6948 [1 << 17]byte +var z6949 [1 << 17]byte +var z6950 [1 << 17]byte +var z6951 [1 << 17]byte +var z6952 [1 << 17]byte +var z6953 [1 << 17]byte +var z6954 [1 << 17]byte +var z6955 [1 << 17]byte +var z6956 [1 << 17]byte +var z6957 [1 << 17]byte +var z6958 [1 << 17]byte +var z6959 [1 << 17]byte +var z6960 [1 << 17]byte +var z6961 [1 << 17]byte +var z6962 [1 << 17]byte +var z6963 [1 << 17]byte +var z6964 [1 << 17]byte +var z6965 [1 << 17]byte +var z6966 [1 << 17]byte +var z6967 [1 << 17]byte +var z6968 [1 << 17]byte +var z6969 [1 << 17]byte +var z6970 [1 << 17]byte +var z6971 [1 << 17]byte +var z6972 [1 << 17]byte +var z6973 [1 << 17]byte +var z6974 [1 << 17]byte +var z6975 [1 << 17]byte +var z6976 [1 << 17]byte +var z6977 [1 << 17]byte +var z6978 [1 << 17]byte +var z6979 [1 << 17]byte +var z6980 [1 << 17]byte +var z6981 [1 << 17]byte +var z6982 [1 << 17]byte +var z6983 [1 << 17]byte +var z6984 [1 << 17]byte +var z6985 [1 << 17]byte +var z6986 [1 << 17]byte +var z6987 [1 << 17]byte +var z6988 [1 << 17]byte +var z6989 [1 << 17]byte +var z6990 [1 << 17]byte +var z6991 [1 << 17]byte +var z6992 [1 << 17]byte +var z6993 [1 << 17]byte +var z6994 [1 << 17]byte +var z6995 [1 << 17]byte +var z6996 [1 << 17]byte +var z6997 [1 << 17]byte +var z6998 [1 << 17]byte +var z6999 [1 << 17]byte +var z7000 [1 << 17]byte +var z7001 [1 << 17]byte +var z7002 [1 << 17]byte +var z7003 [1 << 17]byte +var z7004 [1 << 17]byte +var z7005 [1 << 17]byte +var z7006 [1 << 17]byte +var z7007 [1 << 17]byte +var z7008 [1 << 17]byte +var z7009 [1 << 17]byte +var z7010 [1 << 17]byte +var z7011 [1 << 17]byte +var z7012 [1 << 17]byte +var z7013 [1 << 17]byte +var z7014 [1 << 17]byte +var z7015 [1 << 17]byte +var z7016 [1 << 17]byte +var z7017 [1 << 17]byte +var z7018 [1 << 17]byte +var z7019 [1 << 17]byte +var z7020 [1 << 17]byte +var z7021 [1 << 17]byte +var z7022 [1 << 17]byte +var z7023 [1 << 17]byte +var z7024 [1 << 17]byte +var z7025 [1 << 17]byte +var z7026 [1 << 17]byte +var z7027 [1 << 17]byte +var z7028 [1 << 17]byte +var z7029 [1 << 17]byte +var z7030 [1 << 17]byte +var z7031 [1 << 17]byte +var z7032 [1 << 17]byte +var z7033 [1 << 17]byte +var z7034 [1 << 17]byte +var z7035 [1 << 17]byte +var z7036 [1 << 17]byte +var z7037 [1 << 17]byte +var z7038 [1 << 17]byte +var z7039 [1 << 17]byte +var z7040 [1 << 17]byte +var z7041 [1 << 17]byte +var z7042 [1 << 17]byte +var z7043 [1 << 17]byte +var z7044 [1 << 17]byte +var z7045 [1 << 17]byte +var z7046 [1 << 17]byte +var z7047 [1 << 17]byte +var z7048 [1 << 17]byte +var z7049 [1 << 17]byte +var z7050 [1 << 17]byte +var z7051 [1 << 17]byte +var z7052 [1 << 17]byte +var z7053 [1 << 17]byte +var z7054 [1 << 17]byte +var z7055 [1 << 17]byte +var z7056 [1 << 17]byte +var z7057 [1 << 17]byte +var z7058 [1 << 17]byte +var z7059 [1 << 17]byte +var z7060 [1 << 17]byte +var z7061 [1 << 17]byte +var z7062 [1 << 17]byte +var z7063 [1 << 17]byte +var z7064 [1 << 17]byte +var z7065 [1 << 17]byte +var z7066 [1 << 17]byte +var z7067 [1 << 17]byte +var z7068 [1 << 17]byte +var z7069 [1 << 17]byte +var z7070 [1 << 17]byte +var z7071 [1 << 17]byte +var z7072 [1 << 17]byte +var z7073 [1 << 17]byte +var z7074 [1 << 17]byte +var z7075 [1 << 17]byte +var z7076 [1 << 17]byte +var z7077 [1 << 17]byte +var z7078 [1 << 17]byte +var z7079 [1 << 17]byte +var z7080 [1 << 17]byte +var z7081 [1 << 17]byte +var z7082 [1 << 17]byte +var z7083 [1 << 17]byte +var z7084 [1 << 17]byte +var z7085 [1 << 17]byte +var z7086 [1 << 17]byte +var z7087 [1 << 17]byte +var z7088 [1 << 17]byte +var z7089 [1 << 17]byte +var z7090 [1 << 17]byte +var z7091 [1 << 17]byte +var z7092 [1 << 17]byte +var z7093 [1 << 17]byte +var z7094 [1 << 17]byte +var z7095 [1 << 17]byte +var z7096 [1 << 17]byte +var z7097 [1 << 17]byte +var z7098 [1 << 17]byte +var z7099 [1 << 17]byte +var z7100 [1 << 17]byte +var z7101 [1 << 17]byte +var z7102 [1 << 17]byte +var z7103 [1 << 17]byte +var z7104 [1 << 17]byte +var z7105 [1 << 17]byte +var z7106 [1 << 17]byte +var z7107 [1 << 17]byte +var z7108 [1 << 17]byte +var z7109 [1 << 17]byte +var z7110 [1 << 17]byte +var z7111 [1 << 17]byte +var z7112 [1 << 17]byte +var z7113 [1 << 17]byte +var z7114 [1 << 17]byte +var z7115 [1 << 17]byte +var z7116 [1 << 17]byte +var z7117 [1 << 17]byte +var z7118 [1 << 17]byte +var z7119 [1 << 17]byte +var z7120 [1 << 17]byte +var z7121 [1 << 17]byte +var z7122 [1 << 17]byte +var z7123 [1 << 17]byte +var z7124 [1 << 17]byte +var z7125 [1 << 17]byte +var z7126 [1 << 17]byte +var z7127 [1 << 17]byte +var z7128 [1 << 17]byte +var z7129 [1 << 17]byte +var z7130 [1 << 17]byte +var z7131 [1 << 17]byte +var z7132 [1 << 17]byte +var z7133 [1 << 17]byte +var z7134 [1 << 17]byte +var z7135 [1 << 17]byte +var z7136 [1 << 17]byte +var z7137 [1 << 17]byte +var z7138 [1 << 17]byte +var z7139 [1 << 17]byte +var z7140 [1 << 17]byte +var z7141 [1 << 17]byte +var z7142 [1 << 17]byte +var z7143 [1 << 17]byte +var z7144 [1 << 17]byte +var z7145 [1 << 17]byte +var z7146 [1 << 17]byte +var z7147 [1 << 17]byte +var z7148 [1 << 17]byte +var z7149 [1 << 17]byte +var z7150 [1 << 17]byte +var z7151 [1 << 17]byte +var z7152 [1 << 17]byte +var z7153 [1 << 17]byte +var z7154 [1 << 17]byte +var z7155 [1 << 17]byte +var z7156 [1 << 17]byte +var z7157 [1 << 17]byte +var z7158 [1 << 17]byte +var z7159 [1 << 17]byte +var z7160 [1 << 17]byte +var z7161 [1 << 17]byte +var z7162 [1 << 17]byte +var z7163 [1 << 17]byte +var z7164 [1 << 17]byte +var z7165 [1 << 17]byte +var z7166 [1 << 17]byte +var z7167 [1 << 17]byte +var z7168 [1 << 17]byte +var z7169 [1 << 17]byte +var z7170 [1 << 17]byte +var z7171 [1 << 17]byte +var z7172 [1 << 17]byte +var z7173 [1 << 17]byte +var z7174 [1 << 17]byte +var z7175 [1 << 17]byte +var z7176 [1 << 17]byte +var z7177 [1 << 17]byte +var z7178 [1 << 17]byte +var z7179 [1 << 17]byte +var z7180 [1 << 17]byte +var z7181 [1 << 17]byte +var z7182 [1 << 17]byte +var z7183 [1 << 17]byte +var z7184 [1 << 17]byte +var z7185 [1 << 17]byte +var z7186 [1 << 17]byte +var z7187 [1 << 17]byte +var z7188 [1 << 17]byte +var z7189 [1 << 17]byte +var z7190 [1 << 17]byte +var z7191 [1 << 17]byte +var z7192 [1 << 17]byte +var z7193 [1 << 17]byte +var z7194 [1 << 17]byte +var z7195 [1 << 17]byte +var z7196 [1 << 17]byte +var z7197 [1 << 17]byte +var z7198 [1 << 17]byte +var z7199 [1 << 17]byte +var z7200 [1 << 17]byte +var z7201 [1 << 17]byte +var z7202 [1 << 17]byte +var z7203 [1 << 17]byte +var z7204 [1 << 17]byte +var z7205 [1 << 17]byte +var z7206 [1 << 17]byte +var z7207 [1 << 17]byte +var z7208 [1 << 17]byte +var z7209 [1 << 17]byte +var z7210 [1 << 17]byte +var z7211 [1 << 17]byte +var z7212 [1 << 17]byte +var z7213 [1 << 17]byte +var z7214 [1 << 17]byte +var z7215 [1 << 17]byte +var z7216 [1 << 17]byte +var z7217 [1 << 17]byte +var z7218 [1 << 17]byte +var z7219 [1 << 17]byte +var z7220 [1 << 17]byte +var z7221 [1 << 17]byte +var z7222 [1 << 17]byte +var z7223 [1 << 17]byte +var z7224 [1 << 17]byte +var z7225 [1 << 17]byte +var z7226 [1 << 17]byte +var z7227 [1 << 17]byte +var z7228 [1 << 17]byte +var z7229 [1 << 17]byte +var z7230 [1 << 17]byte +var z7231 [1 << 17]byte +var z7232 [1 << 17]byte +var z7233 [1 << 17]byte +var z7234 [1 << 17]byte +var z7235 [1 << 17]byte +var z7236 [1 << 17]byte +var z7237 [1 << 17]byte +var z7238 [1 << 17]byte +var z7239 [1 << 17]byte +var z7240 [1 << 17]byte +var z7241 [1 << 17]byte +var z7242 [1 << 17]byte +var z7243 [1 << 17]byte +var z7244 [1 << 17]byte +var z7245 [1 << 17]byte +var z7246 [1 << 17]byte +var z7247 [1 << 17]byte +var z7248 [1 << 17]byte +var z7249 [1 << 17]byte +var z7250 [1 << 17]byte +var z7251 [1 << 17]byte +var z7252 [1 << 17]byte +var z7253 [1 << 17]byte +var z7254 [1 << 17]byte +var z7255 [1 << 17]byte +var z7256 [1 << 17]byte +var z7257 [1 << 17]byte +var z7258 [1 << 17]byte +var z7259 [1 << 17]byte +var z7260 [1 << 17]byte +var z7261 [1 << 17]byte +var z7262 [1 << 17]byte +var z7263 [1 << 17]byte +var z7264 [1 << 17]byte +var z7265 [1 << 17]byte +var z7266 [1 << 17]byte +var z7267 [1 << 17]byte +var z7268 [1 << 17]byte +var z7269 [1 << 17]byte +var z7270 [1 << 17]byte +var z7271 [1 << 17]byte +var z7272 [1 << 17]byte +var z7273 [1 << 17]byte +var z7274 [1 << 17]byte +var z7275 [1 << 17]byte +var z7276 [1 << 17]byte +var z7277 [1 << 17]byte +var z7278 [1 << 17]byte +var z7279 [1 << 17]byte +var z7280 [1 << 17]byte +var z7281 [1 << 17]byte +var z7282 [1 << 17]byte +var z7283 [1 << 17]byte +var z7284 [1 << 17]byte +var z7285 [1 << 17]byte +var z7286 [1 << 17]byte +var z7287 [1 << 17]byte +var z7288 [1 << 17]byte +var z7289 [1 << 17]byte +var z7290 [1 << 17]byte +var z7291 [1 << 17]byte +var z7292 [1 << 17]byte +var z7293 [1 << 17]byte +var z7294 [1 << 17]byte +var z7295 [1 << 17]byte +var z7296 [1 << 17]byte +var z7297 [1 << 17]byte +var z7298 [1 << 17]byte +var z7299 [1 << 17]byte +var z7300 [1 << 17]byte +var z7301 [1 << 17]byte +var z7302 [1 << 17]byte +var z7303 [1 << 17]byte +var z7304 [1 << 17]byte +var z7305 [1 << 17]byte +var z7306 [1 << 17]byte +var z7307 [1 << 17]byte +var z7308 [1 << 17]byte +var z7309 [1 << 17]byte +var z7310 [1 << 17]byte +var z7311 [1 << 17]byte +var z7312 [1 << 17]byte +var z7313 [1 << 17]byte +var z7314 [1 << 17]byte +var z7315 [1 << 17]byte +var z7316 [1 << 17]byte +var z7317 [1 << 17]byte +var z7318 [1 << 17]byte +var z7319 [1 << 17]byte +var z7320 [1 << 17]byte +var z7321 [1 << 17]byte +var z7322 [1 << 17]byte +var z7323 [1 << 17]byte +var z7324 [1 << 17]byte +var z7325 [1 << 17]byte +var z7326 [1 << 17]byte +var z7327 [1 << 17]byte +var z7328 [1 << 17]byte +var z7329 [1 << 17]byte +var z7330 [1 << 17]byte +var z7331 [1 << 17]byte +var z7332 [1 << 17]byte +var z7333 [1 << 17]byte +var z7334 [1 << 17]byte +var z7335 [1 << 17]byte +var z7336 [1 << 17]byte +var z7337 [1 << 17]byte +var z7338 [1 << 17]byte +var z7339 [1 << 17]byte +var z7340 [1 << 17]byte +var z7341 [1 << 17]byte +var z7342 [1 << 17]byte +var z7343 [1 << 17]byte +var z7344 [1 << 17]byte +var z7345 [1 << 17]byte +var z7346 [1 << 17]byte +var z7347 [1 << 17]byte +var z7348 [1 << 17]byte +var z7349 [1 << 17]byte +var z7350 [1 << 17]byte +var z7351 [1 << 17]byte +var z7352 [1 << 17]byte +var z7353 [1 << 17]byte +var z7354 [1 << 17]byte +var z7355 [1 << 17]byte +var z7356 [1 << 17]byte +var z7357 [1 << 17]byte +var z7358 [1 << 17]byte +var z7359 [1 << 17]byte +var z7360 [1 << 17]byte +var z7361 [1 << 17]byte +var z7362 [1 << 17]byte +var z7363 [1 << 17]byte +var z7364 [1 << 17]byte +var z7365 [1 << 17]byte +var z7366 [1 << 17]byte +var z7367 [1 << 17]byte +var z7368 [1 << 17]byte +var z7369 [1 << 17]byte +var z7370 [1 << 17]byte +var z7371 [1 << 17]byte +var z7372 [1 << 17]byte +var z7373 [1 << 17]byte +var z7374 [1 << 17]byte +var z7375 [1 << 17]byte +var z7376 [1 << 17]byte +var z7377 [1 << 17]byte +var z7378 [1 << 17]byte +var z7379 [1 << 17]byte +var z7380 [1 << 17]byte +var z7381 [1 << 17]byte +var z7382 [1 << 17]byte +var z7383 [1 << 17]byte +var z7384 [1 << 17]byte +var z7385 [1 << 17]byte +var z7386 [1 << 17]byte +var z7387 [1 << 17]byte +var z7388 [1 << 17]byte +var z7389 [1 << 17]byte +var z7390 [1 << 17]byte +var z7391 [1 << 17]byte +var z7392 [1 << 17]byte +var z7393 [1 << 17]byte +var z7394 [1 << 17]byte +var z7395 [1 << 17]byte +var z7396 [1 << 17]byte +var z7397 [1 << 17]byte +var z7398 [1 << 17]byte +var z7399 [1 << 17]byte +var z7400 [1 << 17]byte +var z7401 [1 << 17]byte +var z7402 [1 << 17]byte +var z7403 [1 << 17]byte +var z7404 [1 << 17]byte +var z7405 [1 << 17]byte +var z7406 [1 << 17]byte +var z7407 [1 << 17]byte +var z7408 [1 << 17]byte +var z7409 [1 << 17]byte +var z7410 [1 << 17]byte +var z7411 [1 << 17]byte +var z7412 [1 << 17]byte +var z7413 [1 << 17]byte +var z7414 [1 << 17]byte +var z7415 [1 << 17]byte +var z7416 [1 << 17]byte +var z7417 [1 << 17]byte +var z7418 [1 << 17]byte +var z7419 [1 << 17]byte +var z7420 [1 << 17]byte +var z7421 [1 << 17]byte +var z7422 [1 << 17]byte +var z7423 [1 << 17]byte +var z7424 [1 << 17]byte +var z7425 [1 << 17]byte +var z7426 [1 << 17]byte +var z7427 [1 << 17]byte +var z7428 [1 << 17]byte +var z7429 [1 << 17]byte +var z7430 [1 << 17]byte +var z7431 [1 << 17]byte +var z7432 [1 << 17]byte +var z7433 [1 << 17]byte +var z7434 [1 << 17]byte +var z7435 [1 << 17]byte +var z7436 [1 << 17]byte +var z7437 [1 << 17]byte +var z7438 [1 << 17]byte +var z7439 [1 << 17]byte +var z7440 [1 << 17]byte +var z7441 [1 << 17]byte +var z7442 [1 << 17]byte +var z7443 [1 << 17]byte +var z7444 [1 << 17]byte +var z7445 [1 << 17]byte +var z7446 [1 << 17]byte +var z7447 [1 << 17]byte +var z7448 [1 << 17]byte +var z7449 [1 << 17]byte +var z7450 [1 << 17]byte +var z7451 [1 << 17]byte +var z7452 [1 << 17]byte +var z7453 [1 << 17]byte +var z7454 [1 << 17]byte +var z7455 [1 << 17]byte +var z7456 [1 << 17]byte +var z7457 [1 << 17]byte +var z7458 [1 << 17]byte +var z7459 [1 << 17]byte +var z7460 [1 << 17]byte +var z7461 [1 << 17]byte +var z7462 [1 << 17]byte +var z7463 [1 << 17]byte +var z7464 [1 << 17]byte +var z7465 [1 << 17]byte +var z7466 [1 << 17]byte +var z7467 [1 << 17]byte +var z7468 [1 << 17]byte +var z7469 [1 << 17]byte +var z7470 [1 << 17]byte +var z7471 [1 << 17]byte +var z7472 [1 << 17]byte +var z7473 [1 << 17]byte +var z7474 [1 << 17]byte +var z7475 [1 << 17]byte +var z7476 [1 << 17]byte +var z7477 [1 << 17]byte +var z7478 [1 << 17]byte +var z7479 [1 << 17]byte +var z7480 [1 << 17]byte +var z7481 [1 << 17]byte +var z7482 [1 << 17]byte +var z7483 [1 << 17]byte +var z7484 [1 << 17]byte +var z7485 [1 << 17]byte +var z7486 [1 << 17]byte +var z7487 [1 << 17]byte +var z7488 [1 << 17]byte +var z7489 [1 << 17]byte +var z7490 [1 << 17]byte +var z7491 [1 << 17]byte +var z7492 [1 << 17]byte +var z7493 [1 << 17]byte +var z7494 [1 << 17]byte +var z7495 [1 << 17]byte +var z7496 [1 << 17]byte +var z7497 [1 << 17]byte +var z7498 [1 << 17]byte +var z7499 [1 << 17]byte +var z7500 [1 << 17]byte +var z7501 [1 << 17]byte +var z7502 [1 << 17]byte +var z7503 [1 << 17]byte +var z7504 [1 << 17]byte +var z7505 [1 << 17]byte +var z7506 [1 << 17]byte +var z7507 [1 << 17]byte +var z7508 [1 << 17]byte +var z7509 [1 << 17]byte +var z7510 [1 << 17]byte +var z7511 [1 << 17]byte +var z7512 [1 << 17]byte +var z7513 [1 << 17]byte +var z7514 [1 << 17]byte +var z7515 [1 << 17]byte +var z7516 [1 << 17]byte +var z7517 [1 << 17]byte +var z7518 [1 << 17]byte +var z7519 [1 << 17]byte +var z7520 [1 << 17]byte +var z7521 [1 << 17]byte +var z7522 [1 << 17]byte +var z7523 [1 << 17]byte +var z7524 [1 << 17]byte +var z7525 [1 << 17]byte +var z7526 [1 << 17]byte +var z7527 [1 << 17]byte +var z7528 [1 << 17]byte +var z7529 [1 << 17]byte +var z7530 [1 << 17]byte +var z7531 [1 << 17]byte +var z7532 [1 << 17]byte +var z7533 [1 << 17]byte +var z7534 [1 << 17]byte +var z7535 [1 << 17]byte +var z7536 [1 << 17]byte +var z7537 [1 << 17]byte +var z7538 [1 << 17]byte +var z7539 [1 << 17]byte +var z7540 [1 << 17]byte +var z7541 [1 << 17]byte +var z7542 [1 << 17]byte +var z7543 [1 << 17]byte +var z7544 [1 << 17]byte +var z7545 [1 << 17]byte +var z7546 [1 << 17]byte +var z7547 [1 << 17]byte +var z7548 [1 << 17]byte +var z7549 [1 << 17]byte +var z7550 [1 << 17]byte +var z7551 [1 << 17]byte +var z7552 [1 << 17]byte +var z7553 [1 << 17]byte +var z7554 [1 << 17]byte +var z7555 [1 << 17]byte +var z7556 [1 << 17]byte +var z7557 [1 << 17]byte +var z7558 [1 << 17]byte +var z7559 [1 << 17]byte +var z7560 [1 << 17]byte +var z7561 [1 << 17]byte +var z7562 [1 << 17]byte +var z7563 [1 << 17]byte +var z7564 [1 << 17]byte +var z7565 [1 << 17]byte +var z7566 [1 << 17]byte +var z7567 [1 << 17]byte +var z7568 [1 << 17]byte +var z7569 [1 << 17]byte +var z7570 [1 << 17]byte +var z7571 [1 << 17]byte +var z7572 [1 << 17]byte +var z7573 [1 << 17]byte +var z7574 [1 << 17]byte +var z7575 [1 << 17]byte +var z7576 [1 << 17]byte +var z7577 [1 << 17]byte +var z7578 [1 << 17]byte +var z7579 [1 << 17]byte +var z7580 [1 << 17]byte +var z7581 [1 << 17]byte +var z7582 [1 << 17]byte +var z7583 [1 << 17]byte +var z7584 [1 << 17]byte +var z7585 [1 << 17]byte +var z7586 [1 << 17]byte +var z7587 [1 << 17]byte +var z7588 [1 << 17]byte +var z7589 [1 << 17]byte +var z7590 [1 << 17]byte +var z7591 [1 << 17]byte +var z7592 [1 << 17]byte +var z7593 [1 << 17]byte +var z7594 [1 << 17]byte +var z7595 [1 << 17]byte +var z7596 [1 << 17]byte +var z7597 [1 << 17]byte +var z7598 [1 << 17]byte +var z7599 [1 << 17]byte +var z7600 [1 << 17]byte +var z7601 [1 << 17]byte +var z7602 [1 << 17]byte +var z7603 [1 << 17]byte +var z7604 [1 << 17]byte +var z7605 [1 << 17]byte +var z7606 [1 << 17]byte +var z7607 [1 << 17]byte +var z7608 [1 << 17]byte +var z7609 [1 << 17]byte +var z7610 [1 << 17]byte +var z7611 [1 << 17]byte +var z7612 [1 << 17]byte +var z7613 [1 << 17]byte +var z7614 [1 << 17]byte +var z7615 [1 << 17]byte +var z7616 [1 << 17]byte +var z7617 [1 << 17]byte +var z7618 [1 << 17]byte +var z7619 [1 << 17]byte +var z7620 [1 << 17]byte +var z7621 [1 << 17]byte +var z7622 [1 << 17]byte +var z7623 [1 << 17]byte +var z7624 [1 << 17]byte +var z7625 [1 << 17]byte +var z7626 [1 << 17]byte +var z7627 [1 << 17]byte +var z7628 [1 << 17]byte +var z7629 [1 << 17]byte +var z7630 [1 << 17]byte +var z7631 [1 << 17]byte +var z7632 [1 << 17]byte +var z7633 [1 << 17]byte +var z7634 [1 << 17]byte +var z7635 [1 << 17]byte +var z7636 [1 << 17]byte +var z7637 [1 << 17]byte +var z7638 [1 << 17]byte +var z7639 [1 << 17]byte +var z7640 [1 << 17]byte +var z7641 [1 << 17]byte +var z7642 [1 << 17]byte +var z7643 [1 << 17]byte +var z7644 [1 << 17]byte +var z7645 [1 << 17]byte +var z7646 [1 << 17]byte +var z7647 [1 << 17]byte +var z7648 [1 << 17]byte +var z7649 [1 << 17]byte +var z7650 [1 << 17]byte +var z7651 [1 << 17]byte +var z7652 [1 << 17]byte +var z7653 [1 << 17]byte +var z7654 [1 << 17]byte +var z7655 [1 << 17]byte +var z7656 [1 << 17]byte +var z7657 [1 << 17]byte +var z7658 [1 << 17]byte +var z7659 [1 << 17]byte +var z7660 [1 << 17]byte +var z7661 [1 << 17]byte +var z7662 [1 << 17]byte +var z7663 [1 << 17]byte +var z7664 [1 << 17]byte +var z7665 [1 << 17]byte +var z7666 [1 << 17]byte +var z7667 [1 << 17]byte +var z7668 [1 << 17]byte +var z7669 [1 << 17]byte +var z7670 [1 << 17]byte +var z7671 [1 << 17]byte +var z7672 [1 << 17]byte +var z7673 [1 << 17]byte +var z7674 [1 << 17]byte +var z7675 [1 << 17]byte +var z7676 [1 << 17]byte +var z7677 [1 << 17]byte +var z7678 [1 << 17]byte +var z7679 [1 << 17]byte +var z7680 [1 << 17]byte +var z7681 [1 << 17]byte +var z7682 [1 << 17]byte +var z7683 [1 << 17]byte +var z7684 [1 << 17]byte +var z7685 [1 << 17]byte +var z7686 [1 << 17]byte +var z7687 [1 << 17]byte +var z7688 [1 << 17]byte +var z7689 [1 << 17]byte +var z7690 [1 << 17]byte +var z7691 [1 << 17]byte +var z7692 [1 << 17]byte +var z7693 [1 << 17]byte +var z7694 [1 << 17]byte +var z7695 [1 << 17]byte +var z7696 [1 << 17]byte +var z7697 [1 << 17]byte +var z7698 [1 << 17]byte +var z7699 [1 << 17]byte +var z7700 [1 << 17]byte +var z7701 [1 << 17]byte +var z7702 [1 << 17]byte +var z7703 [1 << 17]byte +var z7704 [1 << 17]byte +var z7705 [1 << 17]byte +var z7706 [1 << 17]byte +var z7707 [1 << 17]byte +var z7708 [1 << 17]byte +var z7709 [1 << 17]byte +var z7710 [1 << 17]byte +var z7711 [1 << 17]byte +var z7712 [1 << 17]byte +var z7713 [1 << 17]byte +var z7714 [1 << 17]byte +var z7715 [1 << 17]byte +var z7716 [1 << 17]byte +var z7717 [1 << 17]byte +var z7718 [1 << 17]byte +var z7719 [1 << 17]byte +var z7720 [1 << 17]byte +var z7721 [1 << 17]byte +var z7722 [1 << 17]byte +var z7723 [1 << 17]byte +var z7724 [1 << 17]byte +var z7725 [1 << 17]byte +var z7726 [1 << 17]byte +var z7727 [1 << 17]byte +var z7728 [1 << 17]byte +var z7729 [1 << 17]byte +var z7730 [1 << 17]byte +var z7731 [1 << 17]byte +var z7732 [1 << 17]byte +var z7733 [1 << 17]byte +var z7734 [1 << 17]byte +var z7735 [1 << 17]byte +var z7736 [1 << 17]byte +var z7737 [1 << 17]byte +var z7738 [1 << 17]byte +var z7739 [1 << 17]byte +var z7740 [1 << 17]byte +var z7741 [1 << 17]byte +var z7742 [1 << 17]byte +var z7743 [1 << 17]byte +var z7744 [1 << 17]byte +var z7745 [1 << 17]byte +var z7746 [1 << 17]byte +var z7747 [1 << 17]byte +var z7748 [1 << 17]byte +var z7749 [1 << 17]byte +var z7750 [1 << 17]byte +var z7751 [1 << 17]byte +var z7752 [1 << 17]byte +var z7753 [1 << 17]byte +var z7754 [1 << 17]byte +var z7755 [1 << 17]byte +var z7756 [1 << 17]byte +var z7757 [1 << 17]byte +var z7758 [1 << 17]byte +var z7759 [1 << 17]byte +var z7760 [1 << 17]byte +var z7761 [1 << 17]byte +var z7762 [1 << 17]byte +var z7763 [1 << 17]byte +var z7764 [1 << 17]byte +var z7765 [1 << 17]byte +var z7766 [1 << 17]byte +var z7767 [1 << 17]byte +var z7768 [1 << 17]byte +var z7769 [1 << 17]byte +var z7770 [1 << 17]byte +var z7771 [1 << 17]byte +var z7772 [1 << 17]byte +var z7773 [1 << 17]byte +var z7774 [1 << 17]byte +var z7775 [1 << 17]byte +var z7776 [1 << 17]byte +var z7777 [1 << 17]byte +var z7778 [1 << 17]byte +var z7779 [1 << 17]byte +var z7780 [1 << 17]byte +var z7781 [1 << 17]byte +var z7782 [1 << 17]byte +var z7783 [1 << 17]byte +var z7784 [1 << 17]byte +var z7785 [1 << 17]byte +var z7786 [1 << 17]byte +var z7787 [1 << 17]byte +var z7788 [1 << 17]byte +var z7789 [1 << 17]byte +var z7790 [1 << 17]byte +var z7791 [1 << 17]byte +var z7792 [1 << 17]byte +var z7793 [1 << 17]byte +var z7794 [1 << 17]byte +var z7795 [1 << 17]byte +var z7796 [1 << 17]byte +var z7797 [1 << 17]byte +var z7798 [1 << 17]byte +var z7799 [1 << 17]byte +var z7800 [1 << 17]byte +var z7801 [1 << 17]byte +var z7802 [1 << 17]byte +var z7803 [1 << 17]byte +var z7804 [1 << 17]byte +var z7805 [1 << 17]byte +var z7806 [1 << 17]byte +var z7807 [1 << 17]byte +var z7808 [1 << 17]byte +var z7809 [1 << 17]byte +var z7810 [1 << 17]byte +var z7811 [1 << 17]byte +var z7812 [1 << 17]byte +var z7813 [1 << 17]byte +var z7814 [1 << 17]byte +var z7815 [1 << 17]byte +var z7816 [1 << 17]byte +var z7817 [1 << 17]byte +var z7818 [1 << 17]byte +var z7819 [1 << 17]byte +var z7820 [1 << 17]byte +var z7821 [1 << 17]byte +var z7822 [1 << 17]byte +var z7823 [1 << 17]byte +var z7824 [1 << 17]byte +var z7825 [1 << 17]byte +var z7826 [1 << 17]byte +var z7827 [1 << 17]byte +var z7828 [1 << 17]byte +var z7829 [1 << 17]byte +var z7830 [1 << 17]byte +var z7831 [1 << 17]byte +var z7832 [1 << 17]byte +var z7833 [1 << 17]byte +var z7834 [1 << 17]byte +var z7835 [1 << 17]byte +var z7836 [1 << 17]byte +var z7837 [1 << 17]byte +var z7838 [1 << 17]byte +var z7839 [1 << 17]byte +var z7840 [1 << 17]byte +var z7841 [1 << 17]byte +var z7842 [1 << 17]byte +var z7843 [1 << 17]byte +var z7844 [1 << 17]byte +var z7845 [1 << 17]byte +var z7846 [1 << 17]byte +var z7847 [1 << 17]byte +var z7848 [1 << 17]byte +var z7849 [1 << 17]byte +var z7850 [1 << 17]byte +var z7851 [1 << 17]byte +var z7852 [1 << 17]byte +var z7853 [1 << 17]byte +var z7854 [1 << 17]byte +var z7855 [1 << 17]byte +var z7856 [1 << 17]byte +var z7857 [1 << 17]byte +var z7858 [1 << 17]byte +var z7859 [1 << 17]byte +var z7860 [1 << 17]byte +var z7861 [1 << 17]byte +var z7862 [1 << 17]byte +var z7863 [1 << 17]byte +var z7864 [1 << 17]byte +var z7865 [1 << 17]byte +var z7866 [1 << 17]byte +var z7867 [1 << 17]byte +var z7868 [1 << 17]byte +var z7869 [1 << 17]byte +var z7870 [1 << 17]byte +var z7871 [1 << 17]byte +var z7872 [1 << 17]byte +var z7873 [1 << 17]byte +var z7874 [1 << 17]byte +var z7875 [1 << 17]byte +var z7876 [1 << 17]byte +var z7877 [1 << 17]byte +var z7878 [1 << 17]byte +var z7879 [1 << 17]byte +var z7880 [1 << 17]byte +var z7881 [1 << 17]byte +var z7882 [1 << 17]byte +var z7883 [1 << 17]byte +var z7884 [1 << 17]byte +var z7885 [1 << 17]byte +var z7886 [1 << 17]byte +var z7887 [1 << 17]byte +var z7888 [1 << 17]byte +var z7889 [1 << 17]byte +var z7890 [1 << 17]byte +var z7891 [1 << 17]byte +var z7892 [1 << 17]byte +var z7893 [1 << 17]byte +var z7894 [1 << 17]byte +var z7895 [1 << 17]byte +var z7896 [1 << 17]byte +var z7897 [1 << 17]byte +var z7898 [1 << 17]byte +var z7899 [1 << 17]byte +var z7900 [1 << 17]byte +var z7901 [1 << 17]byte +var z7902 [1 << 17]byte +var z7903 [1 << 17]byte +var z7904 [1 << 17]byte +var z7905 [1 << 17]byte +var z7906 [1 << 17]byte +var z7907 [1 << 17]byte +var z7908 [1 << 17]byte +var z7909 [1 << 17]byte +var z7910 [1 << 17]byte +var z7911 [1 << 17]byte +var z7912 [1 << 17]byte +var z7913 [1 << 17]byte +var z7914 [1 << 17]byte +var z7915 [1 << 17]byte +var z7916 [1 << 17]byte +var z7917 [1 << 17]byte +var z7918 [1 << 17]byte +var z7919 [1 << 17]byte +var z7920 [1 << 17]byte +var z7921 [1 << 17]byte +var z7922 [1 << 17]byte +var z7923 [1 << 17]byte +var z7924 [1 << 17]byte +var z7925 [1 << 17]byte +var z7926 [1 << 17]byte +var z7927 [1 << 17]byte +var z7928 [1 << 17]byte +var z7929 [1 << 17]byte +var z7930 [1 << 17]byte +var z7931 [1 << 17]byte +var z7932 [1 << 17]byte +var z7933 [1 << 17]byte +var z7934 [1 << 17]byte +var z7935 [1 << 17]byte +var z7936 [1 << 17]byte +var z7937 [1 << 17]byte +var z7938 [1 << 17]byte +var z7939 [1 << 17]byte +var z7940 [1 << 17]byte +var z7941 [1 << 17]byte +var z7942 [1 << 17]byte +var z7943 [1 << 17]byte +var z7944 [1 << 17]byte +var z7945 [1 << 17]byte +var z7946 [1 << 17]byte +var z7947 [1 << 17]byte +var z7948 [1 << 17]byte +var z7949 [1 << 17]byte +var z7950 [1 << 17]byte +var z7951 [1 << 17]byte +var z7952 [1 << 17]byte +var z7953 [1 << 17]byte +var z7954 [1 << 17]byte +var z7955 [1 << 17]byte +var z7956 [1 << 17]byte +var z7957 [1 << 17]byte +var z7958 [1 << 17]byte +var z7959 [1 << 17]byte +var z7960 [1 << 17]byte +var z7961 [1 << 17]byte +var z7962 [1 << 17]byte +var z7963 [1 << 17]byte +var z7964 [1 << 17]byte +var z7965 [1 << 17]byte +var z7966 [1 << 17]byte +var z7967 [1 << 17]byte +var z7968 [1 << 17]byte +var z7969 [1 << 17]byte +var z7970 [1 << 17]byte +var z7971 [1 << 17]byte +var z7972 [1 << 17]byte +var z7973 [1 << 17]byte +var z7974 [1 << 17]byte +var z7975 [1 << 17]byte +var z7976 [1 << 17]byte +var z7977 [1 << 17]byte +var z7978 [1 << 17]byte +var z7979 [1 << 17]byte +var z7980 [1 << 17]byte +var z7981 [1 << 17]byte +var z7982 [1 << 17]byte +var z7983 [1 << 17]byte +var z7984 [1 << 17]byte +var z7985 [1 << 17]byte +var z7986 [1 << 17]byte +var z7987 [1 << 17]byte +var z7988 [1 << 17]byte +var z7989 [1 << 17]byte +var z7990 [1 << 17]byte +var z7991 [1 << 17]byte +var z7992 [1 << 17]byte +var z7993 [1 << 17]byte +var z7994 [1 << 17]byte +var z7995 [1 << 17]byte +var z7996 [1 << 17]byte +var z7997 [1 << 17]byte +var z7998 [1 << 17]byte +var z7999 [1 << 17]byte +var z8000 [1 << 17]byte +var z8001 [1 << 17]byte +var z8002 [1 << 17]byte +var z8003 [1 << 17]byte +var z8004 [1 << 17]byte +var z8005 [1 << 17]byte +var z8006 [1 << 17]byte +var z8007 [1 << 17]byte +var z8008 [1 << 17]byte +var z8009 [1 << 17]byte +var z8010 [1 << 17]byte +var z8011 [1 << 17]byte +var z8012 [1 << 17]byte +var z8013 [1 << 17]byte +var z8014 [1 << 17]byte +var z8015 [1 << 17]byte +var z8016 [1 << 17]byte +var z8017 [1 << 17]byte +var z8018 [1 << 17]byte +var z8019 [1 << 17]byte +var z8020 [1 << 17]byte +var z8021 [1 << 17]byte +var z8022 [1 << 17]byte +var z8023 [1 << 17]byte +var z8024 [1 << 17]byte +var z8025 [1 << 17]byte +var z8026 [1 << 17]byte +var z8027 [1 << 17]byte +var z8028 [1 << 17]byte +var z8029 [1 << 17]byte +var z8030 [1 << 17]byte +var z8031 [1 << 17]byte +var z8032 [1 << 17]byte +var z8033 [1 << 17]byte +var z8034 [1 << 17]byte +var z8035 [1 << 17]byte +var z8036 [1 << 17]byte +var z8037 [1 << 17]byte +var z8038 [1 << 17]byte +var z8039 [1 << 17]byte +var z8040 [1 << 17]byte +var z8041 [1 << 17]byte +var z8042 [1 << 17]byte +var z8043 [1 << 17]byte +var z8044 [1 << 17]byte +var z8045 [1 << 17]byte +var z8046 [1 << 17]byte +var z8047 [1 << 17]byte +var z8048 [1 << 17]byte +var z8049 [1 << 17]byte +var z8050 [1 << 17]byte +var z8051 [1 << 17]byte +var z8052 [1 << 17]byte +var z8053 [1 << 17]byte +var z8054 [1 << 17]byte +var z8055 [1 << 17]byte +var z8056 [1 << 17]byte +var z8057 [1 << 17]byte +var z8058 [1 << 17]byte +var z8059 [1 << 17]byte +var z8060 [1 << 17]byte +var z8061 [1 << 17]byte +var z8062 [1 << 17]byte +var z8063 [1 << 17]byte +var z8064 [1 << 17]byte +var z8065 [1 << 17]byte +var z8066 [1 << 17]byte +var z8067 [1 << 17]byte +var z8068 [1 << 17]byte +var z8069 [1 << 17]byte +var z8070 [1 << 17]byte +var z8071 [1 << 17]byte +var z8072 [1 << 17]byte +var z8073 [1 << 17]byte +var z8074 [1 << 17]byte +var z8075 [1 << 17]byte +var z8076 [1 << 17]byte +var z8077 [1 << 17]byte +var z8078 [1 << 17]byte +var z8079 [1 << 17]byte +var z8080 [1 << 17]byte +var z8081 [1 << 17]byte +var z8082 [1 << 17]byte +var z8083 [1 << 17]byte +var z8084 [1 << 17]byte +var z8085 [1 << 17]byte +var z8086 [1 << 17]byte +var z8087 [1 << 17]byte +var z8088 [1 << 17]byte +var z8089 [1 << 17]byte +var z8090 [1 << 17]byte +var z8091 [1 << 17]byte +var z8092 [1 << 17]byte +var z8093 [1 << 17]byte +var z8094 [1 << 17]byte +var z8095 [1 << 17]byte +var z8096 [1 << 17]byte +var z8097 [1 << 17]byte +var z8098 [1 << 17]byte +var z8099 [1 << 17]byte +var z8100 [1 << 17]byte +var z8101 [1 << 17]byte +var z8102 [1 << 17]byte +var z8103 [1 << 17]byte +var z8104 [1 << 17]byte +var z8105 [1 << 17]byte +var z8106 [1 << 17]byte +var z8107 [1 << 17]byte +var z8108 [1 << 17]byte +var z8109 [1 << 17]byte +var z8110 [1 << 17]byte +var z8111 [1 << 17]byte +var z8112 [1 << 17]byte +var z8113 [1 << 17]byte +var z8114 [1 << 17]byte +var z8115 [1 << 17]byte +var z8116 [1 << 17]byte +var z8117 [1 << 17]byte +var z8118 [1 << 17]byte +var z8119 [1 << 17]byte +var z8120 [1 << 17]byte +var z8121 [1 << 17]byte +var z8122 [1 << 17]byte +var z8123 [1 << 17]byte +var z8124 [1 << 17]byte +var z8125 [1 << 17]byte +var z8126 [1 << 17]byte +var z8127 [1 << 17]byte +var z8128 [1 << 17]byte +var z8129 [1 << 17]byte +var z8130 [1 << 17]byte +var z8131 [1 << 17]byte +var z8132 [1 << 17]byte +var z8133 [1 << 17]byte +var z8134 [1 << 17]byte +var z8135 [1 << 17]byte +var z8136 [1 << 17]byte +var z8137 [1 << 17]byte +var z8138 [1 << 17]byte +var z8139 [1 << 17]byte +var z8140 [1 << 17]byte +var z8141 [1 << 17]byte +var z8142 [1 << 17]byte +var z8143 [1 << 17]byte +var z8144 [1 << 17]byte +var z8145 [1 << 17]byte +var z8146 [1 << 17]byte +var z8147 [1 << 17]byte +var z8148 [1 << 17]byte +var z8149 [1 << 17]byte +var z8150 [1 << 17]byte +var z8151 [1 << 17]byte +var z8152 [1 << 17]byte +var z8153 [1 << 17]byte +var z8154 [1 << 17]byte +var z8155 [1 << 17]byte +var z8156 [1 << 17]byte +var z8157 [1 << 17]byte +var z8158 [1 << 17]byte +var z8159 [1 << 17]byte +var z8160 [1 << 17]byte +var z8161 [1 << 17]byte +var z8162 [1 << 17]byte +var z8163 [1 << 17]byte +var z8164 [1 << 17]byte +var z8165 [1 << 17]byte +var z8166 [1 << 17]byte +var z8167 [1 << 17]byte +var z8168 [1 << 17]byte +var z8169 [1 << 17]byte +var z8170 [1 << 17]byte +var z8171 [1 << 17]byte +var z8172 [1 << 17]byte +var z8173 [1 << 17]byte +var z8174 [1 << 17]byte +var z8175 [1 << 17]byte +var z8176 [1 << 17]byte +var z8177 [1 << 17]byte +var z8178 [1 << 17]byte +var z8179 [1 << 17]byte +var z8180 [1 << 17]byte +var z8181 [1 << 17]byte +var z8182 [1 << 17]byte +var z8183 [1 << 17]byte +var z8184 [1 << 17]byte +var z8185 [1 << 17]byte +var z8186 [1 << 17]byte +var z8187 [1 << 17]byte +var z8188 [1 << 17]byte +var z8189 [1 << 17]byte +var z8190 [1 << 17]byte +var z8191 [1 << 17]byte +var z8192 [1 << 17]byte +var z8193 [1 << 17]byte +var z8194 [1 << 17]byte +var z8195 [1 << 17]byte +var z8196 [1 << 17]byte +var z8197 [1 << 17]byte +var z8198 [1 << 17]byte +var z8199 [1 << 17]byte +var z8200 [1 << 17]byte +var z8201 [1 << 17]byte +var z8202 [1 << 17]byte +var z8203 [1 << 17]byte +var z8204 [1 << 17]byte +var z8205 [1 << 17]byte +var z8206 [1 << 17]byte +var z8207 [1 << 17]byte +var z8208 [1 << 17]byte +var z8209 [1 << 17]byte +var z8210 [1 << 17]byte +var z8211 [1 << 17]byte +var z8212 [1 << 17]byte +var z8213 [1 << 17]byte +var z8214 [1 << 17]byte +var z8215 [1 << 17]byte +var z8216 [1 << 17]byte +var z8217 [1 << 17]byte +var z8218 [1 << 17]byte +var z8219 [1 << 17]byte +var z8220 [1 << 17]byte +var z8221 [1 << 17]byte +var z8222 [1 << 17]byte +var z8223 [1 << 17]byte +var z8224 [1 << 17]byte +var z8225 [1 << 17]byte +var z8226 [1 << 17]byte +var z8227 [1 << 17]byte +var z8228 [1 << 17]byte +var z8229 [1 << 17]byte +var z8230 [1 << 17]byte +var z8231 [1 << 17]byte +var z8232 [1 << 17]byte +var z8233 [1 << 17]byte +var z8234 [1 << 17]byte +var z8235 [1 << 17]byte +var z8236 [1 << 17]byte +var z8237 [1 << 17]byte +var z8238 [1 << 17]byte +var z8239 [1 << 17]byte +var z8240 [1 << 17]byte +var z8241 [1 << 17]byte +var z8242 [1 << 17]byte +var z8243 [1 << 17]byte +var z8244 [1 << 17]byte +var z8245 [1 << 17]byte +var z8246 [1 << 17]byte +var z8247 [1 << 17]byte +var z8248 [1 << 17]byte +var z8249 [1 << 17]byte +var z8250 [1 << 17]byte +var z8251 [1 << 17]byte +var z8252 [1 << 17]byte +var z8253 [1 << 17]byte +var z8254 [1 << 17]byte +var z8255 [1 << 17]byte +var z8256 [1 << 17]byte +var z8257 [1 << 17]byte +var z8258 [1 << 17]byte +var z8259 [1 << 17]byte +var z8260 [1 << 17]byte +var z8261 [1 << 17]byte +var z8262 [1 << 17]byte +var z8263 [1 << 17]byte +var z8264 [1 << 17]byte +var z8265 [1 << 17]byte +var z8266 [1 << 17]byte +var z8267 [1 << 17]byte +var z8268 [1 << 17]byte +var z8269 [1 << 17]byte +var z8270 [1 << 17]byte +var z8271 [1 << 17]byte +var z8272 [1 << 17]byte +var z8273 [1 << 17]byte +var z8274 [1 << 17]byte +var z8275 [1 << 17]byte +var z8276 [1 << 17]byte +var z8277 [1 << 17]byte +var z8278 [1 << 17]byte +var z8279 [1 << 17]byte +var z8280 [1 << 17]byte +var z8281 [1 << 17]byte +var z8282 [1 << 17]byte +var z8283 [1 << 17]byte +var z8284 [1 << 17]byte +var z8285 [1 << 17]byte +var z8286 [1 << 17]byte +var z8287 [1 << 17]byte +var z8288 [1 << 17]byte +var z8289 [1 << 17]byte +var z8290 [1 << 17]byte +var z8291 [1 << 17]byte +var z8292 [1 << 17]byte +var z8293 [1 << 17]byte +var z8294 [1 << 17]byte +var z8295 [1 << 17]byte +var z8296 [1 << 17]byte +var z8297 [1 << 17]byte +var z8298 [1 << 17]byte +var z8299 [1 << 17]byte +var z8300 [1 << 17]byte +var z8301 [1 << 17]byte +var z8302 [1 << 17]byte +var z8303 [1 << 17]byte +var z8304 [1 << 17]byte +var z8305 [1 << 17]byte +var z8306 [1 << 17]byte +var z8307 [1 << 17]byte +var z8308 [1 << 17]byte +var z8309 [1 << 17]byte +var z8310 [1 << 17]byte +var z8311 [1 << 17]byte +var z8312 [1 << 17]byte +var z8313 [1 << 17]byte +var z8314 [1 << 17]byte +var z8315 [1 << 17]byte +var z8316 [1 << 17]byte +var z8317 [1 << 17]byte +var z8318 [1 << 17]byte +var z8319 [1 << 17]byte +var z8320 [1 << 17]byte +var z8321 [1 << 17]byte +var z8322 [1 << 17]byte +var z8323 [1 << 17]byte +var z8324 [1 << 17]byte +var z8325 [1 << 17]byte +var z8326 [1 << 17]byte +var z8327 [1 << 17]byte +var z8328 [1 << 17]byte +var z8329 [1 << 17]byte +var z8330 [1 << 17]byte +var z8331 [1 << 17]byte +var z8332 [1 << 17]byte +var z8333 [1 << 17]byte +var z8334 [1 << 17]byte +var z8335 [1 << 17]byte +var z8336 [1 << 17]byte +var z8337 [1 << 17]byte +var z8338 [1 << 17]byte +var z8339 [1 << 17]byte +var z8340 [1 << 17]byte +var z8341 [1 << 17]byte +var z8342 [1 << 17]byte +var z8343 [1 << 17]byte +var z8344 [1 << 17]byte +var z8345 [1 << 17]byte +var z8346 [1 << 17]byte +var z8347 [1 << 17]byte +var z8348 [1 << 17]byte +var z8349 [1 << 17]byte +var z8350 [1 << 17]byte +var z8351 [1 << 17]byte +var z8352 [1 << 17]byte +var z8353 [1 << 17]byte +var z8354 [1 << 17]byte +var z8355 [1 << 17]byte +var z8356 [1 << 17]byte +var z8357 [1 << 17]byte +var z8358 [1 << 17]byte +var z8359 [1 << 17]byte +var z8360 [1 << 17]byte +var z8361 [1 << 17]byte +var z8362 [1 << 17]byte +var z8363 [1 << 17]byte +var z8364 [1 << 17]byte +var z8365 [1 << 17]byte +var z8366 [1 << 17]byte +var z8367 [1 << 17]byte +var z8368 [1 << 17]byte +var z8369 [1 << 17]byte +var z8370 [1 << 17]byte +var z8371 [1 << 17]byte +var z8372 [1 << 17]byte +var z8373 [1 << 17]byte +var z8374 [1 << 17]byte +var z8375 [1 << 17]byte +var z8376 [1 << 17]byte +var z8377 [1 << 17]byte +var z8378 [1 << 17]byte +var z8379 [1 << 17]byte +var z8380 [1 << 17]byte +var z8381 [1 << 17]byte +var z8382 [1 << 17]byte +var z8383 [1 << 17]byte +var z8384 [1 << 17]byte +var z8385 [1 << 17]byte +var z8386 [1 << 17]byte +var z8387 [1 << 17]byte +var z8388 [1 << 17]byte +var z8389 [1 << 17]byte +var z8390 [1 << 17]byte +var z8391 [1 << 17]byte +var z8392 [1 << 17]byte +var z8393 [1 << 17]byte +var z8394 [1 << 17]byte +var z8395 [1 << 17]byte +var z8396 [1 << 17]byte +var z8397 [1 << 17]byte +var z8398 [1 << 17]byte +var z8399 [1 << 17]byte +var z8400 [1 << 17]byte +var z8401 [1 << 17]byte +var z8402 [1 << 17]byte +var z8403 [1 << 17]byte +var z8404 [1 << 17]byte +var z8405 [1 << 17]byte +var z8406 [1 << 17]byte +var z8407 [1 << 17]byte +var z8408 [1 << 17]byte +var z8409 [1 << 17]byte +var z8410 [1 << 17]byte +var z8411 [1 << 17]byte +var z8412 [1 << 17]byte +var z8413 [1 << 17]byte +var z8414 [1 << 17]byte +var z8415 [1 << 17]byte +var z8416 [1 << 17]byte +var z8417 [1 << 17]byte +var z8418 [1 << 17]byte +var z8419 [1 << 17]byte +var z8420 [1 << 17]byte +var z8421 [1 << 17]byte +var z8422 [1 << 17]byte +var z8423 [1 << 17]byte +var z8424 [1 << 17]byte +var z8425 [1 << 17]byte +var z8426 [1 << 17]byte +var z8427 [1 << 17]byte +var z8428 [1 << 17]byte +var z8429 [1 << 17]byte +var z8430 [1 << 17]byte +var z8431 [1 << 17]byte +var z8432 [1 << 17]byte +var z8433 [1 << 17]byte +var z8434 [1 << 17]byte +var z8435 [1 << 17]byte +var z8436 [1 << 17]byte +var z8437 [1 << 17]byte +var z8438 [1 << 17]byte +var z8439 [1 << 17]byte +var z8440 [1 << 17]byte +var z8441 [1 << 17]byte +var z8442 [1 << 17]byte +var z8443 [1 << 17]byte +var z8444 [1 << 17]byte +var z8445 [1 << 17]byte +var z8446 [1 << 17]byte +var z8447 [1 << 17]byte +var z8448 [1 << 17]byte +var z8449 [1 << 17]byte +var z8450 [1 << 17]byte +var z8451 [1 << 17]byte +var z8452 [1 << 17]byte +var z8453 [1 << 17]byte +var z8454 [1 << 17]byte +var z8455 [1 << 17]byte +var z8456 [1 << 17]byte +var z8457 [1 << 17]byte +var z8458 [1 << 17]byte +var z8459 [1 << 17]byte +var z8460 [1 << 17]byte +var z8461 [1 << 17]byte +var z8462 [1 << 17]byte +var z8463 [1 << 17]byte +var z8464 [1 << 17]byte +var z8465 [1 << 17]byte +var z8466 [1 << 17]byte +var z8467 [1 << 17]byte +var z8468 [1 << 17]byte +var z8469 [1 << 17]byte +var z8470 [1 << 17]byte +var z8471 [1 << 17]byte +var z8472 [1 << 17]byte +var z8473 [1 << 17]byte +var z8474 [1 << 17]byte +var z8475 [1 << 17]byte +var z8476 [1 << 17]byte +var z8477 [1 << 17]byte +var z8478 [1 << 17]byte +var z8479 [1 << 17]byte +var z8480 [1 << 17]byte +var z8481 [1 << 17]byte +var z8482 [1 << 17]byte +var z8483 [1 << 17]byte +var z8484 [1 << 17]byte +var z8485 [1 << 17]byte +var z8486 [1 << 17]byte +var z8487 [1 << 17]byte +var z8488 [1 << 17]byte +var z8489 [1 << 17]byte +var z8490 [1 << 17]byte +var z8491 [1 << 17]byte +var z8492 [1 << 17]byte +var z8493 [1 << 17]byte +var z8494 [1 << 17]byte +var z8495 [1 << 17]byte +var z8496 [1 << 17]byte +var z8497 [1 << 17]byte +var z8498 [1 << 17]byte +var z8499 [1 << 17]byte +var z8500 [1 << 17]byte +var z8501 [1 << 17]byte +var z8502 [1 << 17]byte +var z8503 [1 << 17]byte +var z8504 [1 << 17]byte +var z8505 [1 << 17]byte +var z8506 [1 << 17]byte +var z8507 [1 << 17]byte +var z8508 [1 << 17]byte +var z8509 [1 << 17]byte +var z8510 [1 << 17]byte +var z8511 [1 << 17]byte +var z8512 [1 << 17]byte +var z8513 [1 << 17]byte +var z8514 [1 << 17]byte +var z8515 [1 << 17]byte +var z8516 [1 << 17]byte +var z8517 [1 << 17]byte +var z8518 [1 << 17]byte +var z8519 [1 << 17]byte +var z8520 [1 << 17]byte +var z8521 [1 << 17]byte +var z8522 [1 << 17]byte +var z8523 [1 << 17]byte +var z8524 [1 << 17]byte +var z8525 [1 << 17]byte +var z8526 [1 << 17]byte +var z8527 [1 << 17]byte +var z8528 [1 << 17]byte +var z8529 [1 << 17]byte +var z8530 [1 << 17]byte +var z8531 [1 << 17]byte +var z8532 [1 << 17]byte +var z8533 [1 << 17]byte +var z8534 [1 << 17]byte +var z8535 [1 << 17]byte +var z8536 [1 << 17]byte +var z8537 [1 << 17]byte +var z8538 [1 << 17]byte +var z8539 [1 << 17]byte +var z8540 [1 << 17]byte +var z8541 [1 << 17]byte +var z8542 [1 << 17]byte +var z8543 [1 << 17]byte +var z8544 [1 << 17]byte +var z8545 [1 << 17]byte +var z8546 [1 << 17]byte +var z8547 [1 << 17]byte +var z8548 [1 << 17]byte +var z8549 [1 << 17]byte +var z8550 [1 << 17]byte +var z8551 [1 << 17]byte +var z8552 [1 << 17]byte +var z8553 [1 << 17]byte +var z8554 [1 << 17]byte +var z8555 [1 << 17]byte +var z8556 [1 << 17]byte +var z8557 [1 << 17]byte +var z8558 [1 << 17]byte +var z8559 [1 << 17]byte +var z8560 [1 << 17]byte +var z8561 [1 << 17]byte +var z8562 [1 << 17]byte +var z8563 [1 << 17]byte +var z8564 [1 << 17]byte +var z8565 [1 << 17]byte +var z8566 [1 << 17]byte +var z8567 [1 << 17]byte +var z8568 [1 << 17]byte +var z8569 [1 << 17]byte +var z8570 [1 << 17]byte +var z8571 [1 << 17]byte +var z8572 [1 << 17]byte +var z8573 [1 << 17]byte +var z8574 [1 << 17]byte +var z8575 [1 << 17]byte +var z8576 [1 << 17]byte +var z8577 [1 << 17]byte +var z8578 [1 << 17]byte +var z8579 [1 << 17]byte +var z8580 [1 << 17]byte +var z8581 [1 << 17]byte +var z8582 [1 << 17]byte +var z8583 [1 << 17]byte +var z8584 [1 << 17]byte +var z8585 [1 << 17]byte +var z8586 [1 << 17]byte +var z8587 [1 << 17]byte +var z8588 [1 << 17]byte +var z8589 [1 << 17]byte +var z8590 [1 << 17]byte +var z8591 [1 << 17]byte +var z8592 [1 << 17]byte +var z8593 [1 << 17]byte +var z8594 [1 << 17]byte +var z8595 [1 << 17]byte +var z8596 [1 << 17]byte +var z8597 [1 << 17]byte +var z8598 [1 << 17]byte +var z8599 [1 << 17]byte +var z8600 [1 << 17]byte +var z8601 [1 << 17]byte +var z8602 [1 << 17]byte +var z8603 [1 << 17]byte +var z8604 [1 << 17]byte +var z8605 [1 << 17]byte +var z8606 [1 << 17]byte +var z8607 [1 << 17]byte +var z8608 [1 << 17]byte +var z8609 [1 << 17]byte +var z8610 [1 << 17]byte +var z8611 [1 << 17]byte +var z8612 [1 << 17]byte +var z8613 [1 << 17]byte +var z8614 [1 << 17]byte +var z8615 [1 << 17]byte +var z8616 [1 << 17]byte +var z8617 [1 << 17]byte +var z8618 [1 << 17]byte +var z8619 [1 << 17]byte +var z8620 [1 << 17]byte +var z8621 [1 << 17]byte +var z8622 [1 << 17]byte +var z8623 [1 << 17]byte +var z8624 [1 << 17]byte +var z8625 [1 << 17]byte +var z8626 [1 << 17]byte +var z8627 [1 << 17]byte +var z8628 [1 << 17]byte +var z8629 [1 << 17]byte +var z8630 [1 << 17]byte +var z8631 [1 << 17]byte +var z8632 [1 << 17]byte +var z8633 [1 << 17]byte +var z8634 [1 << 17]byte +var z8635 [1 << 17]byte +var z8636 [1 << 17]byte +var z8637 [1 << 17]byte +var z8638 [1 << 17]byte +var z8639 [1 << 17]byte +var z8640 [1 << 17]byte +var z8641 [1 << 17]byte +var z8642 [1 << 17]byte +var z8643 [1 << 17]byte +var z8644 [1 << 17]byte +var z8645 [1 << 17]byte +var z8646 [1 << 17]byte +var z8647 [1 << 17]byte +var z8648 [1 << 17]byte +var z8649 [1 << 17]byte +var z8650 [1 << 17]byte +var z8651 [1 << 17]byte +var z8652 [1 << 17]byte +var z8653 [1 << 17]byte +var z8654 [1 << 17]byte +var z8655 [1 << 17]byte +var z8656 [1 << 17]byte +var z8657 [1 << 17]byte +var z8658 [1 << 17]byte +var z8659 [1 << 17]byte +var z8660 [1 << 17]byte +var z8661 [1 << 17]byte +var z8662 [1 << 17]byte +var z8663 [1 << 17]byte +var z8664 [1 << 17]byte +var z8665 [1 << 17]byte +var z8666 [1 << 17]byte +var z8667 [1 << 17]byte +var z8668 [1 << 17]byte +var z8669 [1 << 17]byte +var z8670 [1 << 17]byte +var z8671 [1 << 17]byte +var z8672 [1 << 17]byte +var z8673 [1 << 17]byte +var z8674 [1 << 17]byte +var z8675 [1 << 17]byte +var z8676 [1 << 17]byte +var z8677 [1 << 17]byte +var z8678 [1 << 17]byte +var z8679 [1 << 17]byte +var z8680 [1 << 17]byte +var z8681 [1 << 17]byte +var z8682 [1 << 17]byte +var z8683 [1 << 17]byte +var z8684 [1 << 17]byte +var z8685 [1 << 17]byte +var z8686 [1 << 17]byte +var z8687 [1 << 17]byte +var z8688 [1 << 17]byte +var z8689 [1 << 17]byte +var z8690 [1 << 17]byte +var z8691 [1 << 17]byte +var z8692 [1 << 17]byte +var z8693 [1 << 17]byte +var z8694 [1 << 17]byte +var z8695 [1 << 17]byte +var z8696 [1 << 17]byte +var z8697 [1 << 17]byte +var z8698 [1 << 17]byte +var z8699 [1 << 17]byte +var z8700 [1 << 17]byte +var z8701 [1 << 17]byte +var z8702 [1 << 17]byte +var z8703 [1 << 17]byte +var z8704 [1 << 17]byte +var z8705 [1 << 17]byte +var z8706 [1 << 17]byte +var z8707 [1 << 17]byte +var z8708 [1 << 17]byte +var z8709 [1 << 17]byte +var z8710 [1 << 17]byte +var z8711 [1 << 17]byte +var z8712 [1 << 17]byte +var z8713 [1 << 17]byte +var z8714 [1 << 17]byte +var z8715 [1 << 17]byte +var z8716 [1 << 17]byte +var z8717 [1 << 17]byte +var z8718 [1 << 17]byte +var z8719 [1 << 17]byte +var z8720 [1 << 17]byte +var z8721 [1 << 17]byte +var z8722 [1 << 17]byte +var z8723 [1 << 17]byte +var z8724 [1 << 17]byte +var z8725 [1 << 17]byte +var z8726 [1 << 17]byte +var z8727 [1 << 17]byte +var z8728 [1 << 17]byte +var z8729 [1 << 17]byte +var z8730 [1 << 17]byte +var z8731 [1 << 17]byte +var z8732 [1 << 17]byte +var z8733 [1 << 17]byte +var z8734 [1 << 17]byte +var z8735 [1 << 17]byte +var z8736 [1 << 17]byte +var z8737 [1 << 17]byte +var z8738 [1 << 17]byte +var z8739 [1 << 17]byte +var z8740 [1 << 17]byte +var z8741 [1 << 17]byte +var z8742 [1 << 17]byte +var z8743 [1 << 17]byte +var z8744 [1 << 17]byte +var z8745 [1 << 17]byte +var z8746 [1 << 17]byte +var z8747 [1 << 17]byte +var z8748 [1 << 17]byte +var z8749 [1 << 17]byte +var z8750 [1 << 17]byte +var z8751 [1 << 17]byte +var z8752 [1 << 17]byte +var z8753 [1 << 17]byte +var z8754 [1 << 17]byte +var z8755 [1 << 17]byte +var z8756 [1 << 17]byte +var z8757 [1 << 17]byte +var z8758 [1 << 17]byte +var z8759 [1 << 17]byte +var z8760 [1 << 17]byte +var z8761 [1 << 17]byte +var z8762 [1 << 17]byte +var z8763 [1 << 17]byte +var z8764 [1 << 17]byte +var z8765 [1 << 17]byte +var z8766 [1 << 17]byte +var z8767 [1 << 17]byte +var z8768 [1 << 17]byte +var z8769 [1 << 17]byte +var z8770 [1 << 17]byte +var z8771 [1 << 17]byte +var z8772 [1 << 17]byte +var z8773 [1 << 17]byte +var z8774 [1 << 17]byte +var z8775 [1 << 17]byte +var z8776 [1 << 17]byte +var z8777 [1 << 17]byte +var z8778 [1 << 17]byte +var z8779 [1 << 17]byte +var z8780 [1 << 17]byte +var z8781 [1 << 17]byte +var z8782 [1 << 17]byte +var z8783 [1 << 17]byte +var z8784 [1 << 17]byte +var z8785 [1 << 17]byte +var z8786 [1 << 17]byte +var z8787 [1 << 17]byte +var z8788 [1 << 17]byte +var z8789 [1 << 17]byte +var z8790 [1 << 17]byte +var z8791 [1 << 17]byte +var z8792 [1 << 17]byte +var z8793 [1 << 17]byte +var z8794 [1 << 17]byte +var z8795 [1 << 17]byte +var z8796 [1 << 17]byte +var z8797 [1 << 17]byte +var z8798 [1 << 17]byte +var z8799 [1 << 17]byte +var z8800 [1 << 17]byte +var z8801 [1 << 17]byte +var z8802 [1 << 17]byte +var z8803 [1 << 17]byte +var z8804 [1 << 17]byte +var z8805 [1 << 17]byte +var z8806 [1 << 17]byte +var z8807 [1 << 17]byte +var z8808 [1 << 17]byte +var z8809 [1 << 17]byte +var z8810 [1 << 17]byte +var z8811 [1 << 17]byte +var z8812 [1 << 17]byte +var z8813 [1 << 17]byte +var z8814 [1 << 17]byte +var z8815 [1 << 17]byte +var z8816 [1 << 17]byte +var z8817 [1 << 17]byte +var z8818 [1 << 17]byte +var z8819 [1 << 17]byte +var z8820 [1 << 17]byte +var z8821 [1 << 17]byte +var z8822 [1 << 17]byte +var z8823 [1 << 17]byte +var z8824 [1 << 17]byte +var z8825 [1 << 17]byte +var z8826 [1 << 17]byte +var z8827 [1 << 17]byte +var z8828 [1 << 17]byte +var z8829 [1 << 17]byte +var z8830 [1 << 17]byte +var z8831 [1 << 17]byte +var z8832 [1 << 17]byte +var z8833 [1 << 17]byte +var z8834 [1 << 17]byte +var z8835 [1 << 17]byte +var z8836 [1 << 17]byte +var z8837 [1 << 17]byte +var z8838 [1 << 17]byte +var z8839 [1 << 17]byte +var z8840 [1 << 17]byte +var z8841 [1 << 17]byte +var z8842 [1 << 17]byte +var z8843 [1 << 17]byte +var z8844 [1 << 17]byte +var z8845 [1 << 17]byte +var z8846 [1 << 17]byte +var z8847 [1 << 17]byte +var z8848 [1 << 17]byte +var z8849 [1 << 17]byte +var z8850 [1 << 17]byte +var z8851 [1 << 17]byte +var z8852 [1 << 17]byte +var z8853 [1 << 17]byte +var z8854 [1 << 17]byte +var z8855 [1 << 17]byte +var z8856 [1 << 17]byte +var z8857 [1 << 17]byte +var z8858 [1 << 17]byte +var z8859 [1 << 17]byte +var z8860 [1 << 17]byte +var z8861 [1 << 17]byte +var z8862 [1 << 17]byte +var z8863 [1 << 17]byte +var z8864 [1 << 17]byte +var z8865 [1 << 17]byte +var z8866 [1 << 17]byte +var z8867 [1 << 17]byte +var z8868 [1 << 17]byte +var z8869 [1 << 17]byte +var z8870 [1 << 17]byte +var z8871 [1 << 17]byte +var z8872 [1 << 17]byte +var z8873 [1 << 17]byte +var z8874 [1 << 17]byte +var z8875 [1 << 17]byte +var z8876 [1 << 17]byte +var z8877 [1 << 17]byte +var z8878 [1 << 17]byte +var z8879 [1 << 17]byte +var z8880 [1 << 17]byte +var z8881 [1 << 17]byte +var z8882 [1 << 17]byte +var z8883 [1 << 17]byte +var z8884 [1 << 17]byte +var z8885 [1 << 17]byte +var z8886 [1 << 17]byte +var z8887 [1 << 17]byte +var z8888 [1 << 17]byte +var z8889 [1 << 17]byte +var z8890 [1 << 17]byte +var z8891 [1 << 17]byte +var z8892 [1 << 17]byte +var z8893 [1 << 17]byte +var z8894 [1 << 17]byte +var z8895 [1 << 17]byte +var z8896 [1 << 17]byte +var z8897 [1 << 17]byte +var z8898 [1 << 17]byte +var z8899 [1 << 17]byte +var z8900 [1 << 17]byte +var z8901 [1 << 17]byte +var z8902 [1 << 17]byte +var z8903 [1 << 17]byte +var z8904 [1 << 17]byte +var z8905 [1 << 17]byte +var z8906 [1 << 17]byte +var z8907 [1 << 17]byte +var z8908 [1 << 17]byte +var z8909 [1 << 17]byte +var z8910 [1 << 17]byte +var z8911 [1 << 17]byte +var z8912 [1 << 17]byte +var z8913 [1 << 17]byte +var z8914 [1 << 17]byte +var z8915 [1 << 17]byte +var z8916 [1 << 17]byte +var z8917 [1 << 17]byte +var z8918 [1 << 17]byte +var z8919 [1 << 17]byte +var z8920 [1 << 17]byte +var z8921 [1 << 17]byte +var z8922 [1 << 17]byte +var z8923 [1 << 17]byte +var z8924 [1 << 17]byte +var z8925 [1 << 17]byte +var z8926 [1 << 17]byte +var z8927 [1 << 17]byte +var z8928 [1 << 17]byte +var z8929 [1 << 17]byte +var z8930 [1 << 17]byte +var z8931 [1 << 17]byte +var z8932 [1 << 17]byte +var z8933 [1 << 17]byte +var z8934 [1 << 17]byte +var z8935 [1 << 17]byte +var z8936 [1 << 17]byte +var z8937 [1 << 17]byte +var z8938 [1 << 17]byte +var z8939 [1 << 17]byte +var z8940 [1 << 17]byte +var z8941 [1 << 17]byte +var z8942 [1 << 17]byte +var z8943 [1 << 17]byte +var z8944 [1 << 17]byte +var z8945 [1 << 17]byte +var z8946 [1 << 17]byte +var z8947 [1 << 17]byte +var z8948 [1 << 17]byte +var z8949 [1 << 17]byte +var z8950 [1 << 17]byte +var z8951 [1 << 17]byte +var z8952 [1 << 17]byte +var z8953 [1 << 17]byte +var z8954 [1 << 17]byte +var z8955 [1 << 17]byte +var z8956 [1 << 17]byte +var z8957 [1 << 17]byte +var z8958 [1 << 17]byte +var z8959 [1 << 17]byte +var z8960 [1 << 17]byte +var z8961 [1 << 17]byte +var z8962 [1 << 17]byte +var z8963 [1 << 17]byte +var z8964 [1 << 17]byte +var z8965 [1 << 17]byte +var z8966 [1 << 17]byte +var z8967 [1 << 17]byte +var z8968 [1 << 17]byte +var z8969 [1 << 17]byte +var z8970 [1 << 17]byte +var z8971 [1 << 17]byte +var z8972 [1 << 17]byte +var z8973 [1 << 17]byte +var z8974 [1 << 17]byte +var z8975 [1 << 17]byte +var z8976 [1 << 17]byte +var z8977 [1 << 17]byte +var z8978 [1 << 17]byte +var z8979 [1 << 17]byte +var z8980 [1 << 17]byte +var z8981 [1 << 17]byte +var z8982 [1 << 17]byte +var z8983 [1 << 17]byte +var z8984 [1 << 17]byte +var z8985 [1 << 17]byte +var z8986 [1 << 17]byte +var z8987 [1 << 17]byte +var z8988 [1 << 17]byte +var z8989 [1 << 17]byte +var z8990 [1 << 17]byte +var z8991 [1 << 17]byte +var z8992 [1 << 17]byte +var z8993 [1 << 17]byte +var z8994 [1 << 17]byte +var z8995 [1 << 17]byte +var z8996 [1 << 17]byte +var z8997 [1 << 17]byte +var z8998 [1 << 17]byte +var z8999 [1 << 17]byte +var z9000 [1 << 17]byte +var z9001 [1 << 17]byte +var z9002 [1 << 17]byte +var z9003 [1 << 17]byte +var z9004 [1 << 17]byte +var z9005 [1 << 17]byte +var z9006 [1 << 17]byte +var z9007 [1 << 17]byte +var z9008 [1 << 17]byte +var z9009 [1 << 17]byte +var z9010 [1 << 17]byte +var z9011 [1 << 17]byte +var z9012 [1 << 17]byte +var z9013 [1 << 17]byte +var z9014 [1 << 17]byte +var z9015 [1 << 17]byte +var z9016 [1 << 17]byte +var z9017 [1 << 17]byte +var z9018 [1 << 17]byte +var z9019 [1 << 17]byte +var z9020 [1 << 17]byte +var z9021 [1 << 17]byte +var z9022 [1 << 17]byte +var z9023 [1 << 17]byte +var z9024 [1 << 17]byte +var z9025 [1 << 17]byte +var z9026 [1 << 17]byte +var z9027 [1 << 17]byte +var z9028 [1 << 17]byte +var z9029 [1 << 17]byte +var z9030 [1 << 17]byte +var z9031 [1 << 17]byte +var z9032 [1 << 17]byte +var z9033 [1 << 17]byte +var z9034 [1 << 17]byte +var z9035 [1 << 17]byte +var z9036 [1 << 17]byte +var z9037 [1 << 17]byte +var z9038 [1 << 17]byte +var z9039 [1 << 17]byte +var z9040 [1 << 17]byte +var z9041 [1 << 17]byte +var z9042 [1 << 17]byte +var z9043 [1 << 17]byte +var z9044 [1 << 17]byte +var z9045 [1 << 17]byte +var z9046 [1 << 17]byte +var z9047 [1 << 17]byte +var z9048 [1 << 17]byte +var z9049 [1 << 17]byte +var z9050 [1 << 17]byte +var z9051 [1 << 17]byte +var z9052 [1 << 17]byte +var z9053 [1 << 17]byte +var z9054 [1 << 17]byte +var z9055 [1 << 17]byte +var z9056 [1 << 17]byte +var z9057 [1 << 17]byte +var z9058 [1 << 17]byte +var z9059 [1 << 17]byte +var z9060 [1 << 17]byte +var z9061 [1 << 17]byte +var z9062 [1 << 17]byte +var z9063 [1 << 17]byte +var z9064 [1 << 17]byte +var z9065 [1 << 17]byte +var z9066 [1 << 17]byte +var z9067 [1 << 17]byte +var z9068 [1 << 17]byte +var z9069 [1 << 17]byte +var z9070 [1 << 17]byte +var z9071 [1 << 17]byte +var z9072 [1 << 17]byte +var z9073 [1 << 17]byte +var z9074 [1 << 17]byte +var z9075 [1 << 17]byte +var z9076 [1 << 17]byte +var z9077 [1 << 17]byte +var z9078 [1 << 17]byte +var z9079 [1 << 17]byte +var z9080 [1 << 17]byte +var z9081 [1 << 17]byte +var z9082 [1 << 17]byte +var z9083 [1 << 17]byte +var z9084 [1 << 17]byte +var z9085 [1 << 17]byte +var z9086 [1 << 17]byte +var z9087 [1 << 17]byte +var z9088 [1 << 17]byte +var z9089 [1 << 17]byte +var z9090 [1 << 17]byte +var z9091 [1 << 17]byte +var z9092 [1 << 17]byte +var z9093 [1 << 17]byte +var z9094 [1 << 17]byte +var z9095 [1 << 17]byte +var z9096 [1 << 17]byte +var z9097 [1 << 17]byte +var z9098 [1 << 17]byte +var z9099 [1 << 17]byte +var z9100 [1 << 17]byte +var z9101 [1 << 17]byte +var z9102 [1 << 17]byte +var z9103 [1 << 17]byte +var z9104 [1 << 17]byte +var z9105 [1 << 17]byte +var z9106 [1 << 17]byte +var z9107 [1 << 17]byte +var z9108 [1 << 17]byte +var z9109 [1 << 17]byte +var z9110 [1 << 17]byte +var z9111 [1 << 17]byte +var z9112 [1 << 17]byte +var z9113 [1 << 17]byte +var z9114 [1 << 17]byte +var z9115 [1 << 17]byte +var z9116 [1 << 17]byte +var z9117 [1 << 17]byte +var z9118 [1 << 17]byte +var z9119 [1 << 17]byte +var z9120 [1 << 17]byte +var z9121 [1 << 17]byte +var z9122 [1 << 17]byte +var z9123 [1 << 17]byte +var z9124 [1 << 17]byte +var z9125 [1 << 17]byte +var z9126 [1 << 17]byte +var z9127 [1 << 17]byte +var z9128 [1 << 17]byte +var z9129 [1 << 17]byte +var z9130 [1 << 17]byte +var z9131 [1 << 17]byte +var z9132 [1 << 17]byte +var z9133 [1 << 17]byte +var z9134 [1 << 17]byte +var z9135 [1 << 17]byte +var z9136 [1 << 17]byte +var z9137 [1 << 17]byte +var z9138 [1 << 17]byte +var z9139 [1 << 17]byte +var z9140 [1 << 17]byte +var z9141 [1 << 17]byte +var z9142 [1 << 17]byte +var z9143 [1 << 17]byte +var z9144 [1 << 17]byte +var z9145 [1 << 17]byte +var z9146 [1 << 17]byte +var z9147 [1 << 17]byte +var z9148 [1 << 17]byte +var z9149 [1 << 17]byte +var z9150 [1 << 17]byte +var z9151 [1 << 17]byte +var z9152 [1 << 17]byte +var z9153 [1 << 17]byte +var z9154 [1 << 17]byte +var z9155 [1 << 17]byte +var z9156 [1 << 17]byte +var z9157 [1 << 17]byte +var z9158 [1 << 17]byte +var z9159 [1 << 17]byte +var z9160 [1 << 17]byte +var z9161 [1 << 17]byte +var z9162 [1 << 17]byte +var z9163 [1 << 17]byte +var z9164 [1 << 17]byte +var z9165 [1 << 17]byte +var z9166 [1 << 17]byte +var z9167 [1 << 17]byte +var z9168 [1 << 17]byte +var z9169 [1 << 17]byte +var z9170 [1 << 17]byte +var z9171 [1 << 17]byte +var z9172 [1 << 17]byte +var z9173 [1 << 17]byte +var z9174 [1 << 17]byte +var z9175 [1 << 17]byte +var z9176 [1 << 17]byte +var z9177 [1 << 17]byte +var z9178 [1 << 17]byte +var z9179 [1 << 17]byte +var z9180 [1 << 17]byte +var z9181 [1 << 17]byte +var z9182 [1 << 17]byte +var z9183 [1 << 17]byte +var z9184 [1 << 17]byte +var z9185 [1 << 17]byte +var z9186 [1 << 17]byte +var z9187 [1 << 17]byte +var z9188 [1 << 17]byte +var z9189 [1 << 17]byte +var z9190 [1 << 17]byte +var z9191 [1 << 17]byte +var z9192 [1 << 17]byte +var z9193 [1 << 17]byte +var z9194 [1 << 17]byte +var z9195 [1 << 17]byte +var z9196 [1 << 17]byte +var z9197 [1 << 17]byte +var z9198 [1 << 17]byte +var z9199 [1 << 17]byte +var z9200 [1 << 17]byte +var z9201 [1 << 17]byte +var z9202 [1 << 17]byte +var z9203 [1 << 17]byte +var z9204 [1 << 17]byte +var z9205 [1 << 17]byte +var z9206 [1 << 17]byte +var z9207 [1 << 17]byte +var z9208 [1 << 17]byte +var z9209 [1 << 17]byte +var z9210 [1 << 17]byte +var z9211 [1 << 17]byte +var z9212 [1 << 17]byte +var z9213 [1 << 17]byte +var z9214 [1 << 17]byte +var z9215 [1 << 17]byte +var z9216 [1 << 17]byte +var z9217 [1 << 17]byte +var z9218 [1 << 17]byte +var z9219 [1 << 17]byte +var z9220 [1 << 17]byte +var z9221 [1 << 17]byte +var z9222 [1 << 17]byte +var z9223 [1 << 17]byte +var z9224 [1 << 17]byte +var z9225 [1 << 17]byte +var z9226 [1 << 17]byte +var z9227 [1 << 17]byte +var z9228 [1 << 17]byte +var z9229 [1 << 17]byte +var z9230 [1 << 17]byte +var z9231 [1 << 17]byte +var z9232 [1 << 17]byte +var z9233 [1 << 17]byte +var z9234 [1 << 17]byte +var z9235 [1 << 17]byte +var z9236 [1 << 17]byte +var z9237 [1 << 17]byte +var z9238 [1 << 17]byte +var z9239 [1 << 17]byte +var z9240 [1 << 17]byte +var z9241 [1 << 17]byte +var z9242 [1 << 17]byte +var z9243 [1 << 17]byte +var z9244 [1 << 17]byte +var z9245 [1 << 17]byte +var z9246 [1 << 17]byte +var z9247 [1 << 17]byte +var z9248 [1 << 17]byte +var z9249 [1 << 17]byte +var z9250 [1 << 17]byte +var z9251 [1 << 17]byte +var z9252 [1 << 17]byte +var z9253 [1 << 17]byte +var z9254 [1 << 17]byte +var z9255 [1 << 17]byte +var z9256 [1 << 17]byte +var z9257 [1 << 17]byte +var z9258 [1 << 17]byte +var z9259 [1 << 17]byte +var z9260 [1 << 17]byte +var z9261 [1 << 17]byte +var z9262 [1 << 17]byte +var z9263 [1 << 17]byte +var z9264 [1 << 17]byte +var z9265 [1 << 17]byte +var z9266 [1 << 17]byte +var z9267 [1 << 17]byte +var z9268 [1 << 17]byte +var z9269 [1 << 17]byte +var z9270 [1 << 17]byte +var z9271 [1 << 17]byte +var z9272 [1 << 17]byte +var z9273 [1 << 17]byte +var z9274 [1 << 17]byte +var z9275 [1 << 17]byte +var z9276 [1 << 17]byte +var z9277 [1 << 17]byte +var z9278 [1 << 17]byte +var z9279 [1 << 17]byte +var z9280 [1 << 17]byte +var z9281 [1 << 17]byte +var z9282 [1 << 17]byte +var z9283 [1 << 17]byte +var z9284 [1 << 17]byte +var z9285 [1 << 17]byte +var z9286 [1 << 17]byte +var z9287 [1 << 17]byte +var z9288 [1 << 17]byte +var z9289 [1 << 17]byte +var z9290 [1 << 17]byte +var z9291 [1 << 17]byte +var z9292 [1 << 17]byte +var z9293 [1 << 17]byte +var z9294 [1 << 17]byte +var z9295 [1 << 17]byte +var z9296 [1 << 17]byte +var z9297 [1 << 17]byte +var z9298 [1 << 17]byte +var z9299 [1 << 17]byte +var z9300 [1 << 17]byte +var z9301 [1 << 17]byte +var z9302 [1 << 17]byte +var z9303 [1 << 17]byte +var z9304 [1 << 17]byte +var z9305 [1 << 17]byte +var z9306 [1 << 17]byte +var z9307 [1 << 17]byte +var z9308 [1 << 17]byte +var z9309 [1 << 17]byte +var z9310 [1 << 17]byte +var z9311 [1 << 17]byte +var z9312 [1 << 17]byte +var z9313 [1 << 17]byte +var z9314 [1 << 17]byte +var z9315 [1 << 17]byte +var z9316 [1 << 17]byte +var z9317 [1 << 17]byte +var z9318 [1 << 17]byte +var z9319 [1 << 17]byte +var z9320 [1 << 17]byte +var z9321 [1 << 17]byte +var z9322 [1 << 17]byte +var z9323 [1 << 17]byte +var z9324 [1 << 17]byte +var z9325 [1 << 17]byte +var z9326 [1 << 17]byte +var z9327 [1 << 17]byte +var z9328 [1 << 17]byte +var z9329 [1 << 17]byte +var z9330 [1 << 17]byte +var z9331 [1 << 17]byte +var z9332 [1 << 17]byte +var z9333 [1 << 17]byte +var z9334 [1 << 17]byte +var z9335 [1 << 17]byte +var z9336 [1 << 17]byte +var z9337 [1 << 17]byte +var z9338 [1 << 17]byte +var z9339 [1 << 17]byte +var z9340 [1 << 17]byte +var z9341 [1 << 17]byte +var z9342 [1 << 17]byte +var z9343 [1 << 17]byte +var z9344 [1 << 17]byte +var z9345 [1 << 17]byte +var z9346 [1 << 17]byte +var z9347 [1 << 17]byte +var z9348 [1 << 17]byte +var z9349 [1 << 17]byte +var z9350 [1 << 17]byte +var z9351 [1 << 17]byte +var z9352 [1 << 17]byte +var z9353 [1 << 17]byte +var z9354 [1 << 17]byte +var z9355 [1 << 17]byte +var z9356 [1 << 17]byte +var z9357 [1 << 17]byte +var z9358 [1 << 17]byte +var z9359 [1 << 17]byte +var z9360 [1 << 17]byte +var z9361 [1 << 17]byte +var z9362 [1 << 17]byte +var z9363 [1 << 17]byte +var z9364 [1 << 17]byte +var z9365 [1 << 17]byte +var z9366 [1 << 17]byte +var z9367 [1 << 17]byte +var z9368 [1 << 17]byte +var z9369 [1 << 17]byte +var z9370 [1 << 17]byte +var z9371 [1 << 17]byte +var z9372 [1 << 17]byte +var z9373 [1 << 17]byte +var z9374 [1 << 17]byte +var z9375 [1 << 17]byte +var z9376 [1 << 17]byte +var z9377 [1 << 17]byte +var z9378 [1 << 17]byte +var z9379 [1 << 17]byte +var z9380 [1 << 17]byte +var z9381 [1 << 17]byte +var z9382 [1 << 17]byte +var z9383 [1 << 17]byte +var z9384 [1 << 17]byte +var z9385 [1 << 17]byte +var z9386 [1 << 17]byte +var z9387 [1 << 17]byte +var z9388 [1 << 17]byte +var z9389 [1 << 17]byte +var z9390 [1 << 17]byte +var z9391 [1 << 17]byte +var z9392 [1 << 17]byte +var z9393 [1 << 17]byte +var z9394 [1 << 17]byte +var z9395 [1 << 17]byte +var z9396 [1 << 17]byte +var z9397 [1 << 17]byte +var z9398 [1 << 17]byte +var z9399 [1 << 17]byte +var z9400 [1 << 17]byte +var z9401 [1 << 17]byte +var z9402 [1 << 17]byte +var z9403 [1 << 17]byte +var z9404 [1 << 17]byte +var z9405 [1 << 17]byte +var z9406 [1 << 17]byte +var z9407 [1 << 17]byte +var z9408 [1 << 17]byte +var z9409 [1 << 17]byte +var z9410 [1 << 17]byte +var z9411 [1 << 17]byte +var z9412 [1 << 17]byte +var z9413 [1 << 17]byte +var z9414 [1 << 17]byte +var z9415 [1 << 17]byte +var z9416 [1 << 17]byte +var z9417 [1 << 17]byte +var z9418 [1 << 17]byte +var z9419 [1 << 17]byte +var z9420 [1 << 17]byte +var z9421 [1 << 17]byte +var z9422 [1 << 17]byte +var z9423 [1 << 17]byte +var z9424 [1 << 17]byte +var z9425 [1 << 17]byte +var z9426 [1 << 17]byte +var z9427 [1 << 17]byte +var z9428 [1 << 17]byte +var z9429 [1 << 17]byte +var z9430 [1 << 17]byte +var z9431 [1 << 17]byte +var z9432 [1 << 17]byte +var z9433 [1 << 17]byte +var z9434 [1 << 17]byte +var z9435 [1 << 17]byte +var z9436 [1 << 17]byte +var z9437 [1 << 17]byte +var z9438 [1 << 17]byte +var z9439 [1 << 17]byte +var z9440 [1 << 17]byte +var z9441 [1 << 17]byte +var z9442 [1 << 17]byte +var z9443 [1 << 17]byte +var z9444 [1 << 17]byte +var z9445 [1 << 17]byte +var z9446 [1 << 17]byte +var z9447 [1 << 17]byte +var z9448 [1 << 17]byte +var z9449 [1 << 17]byte +var z9450 [1 << 17]byte +var z9451 [1 << 17]byte +var z9452 [1 << 17]byte +var z9453 [1 << 17]byte +var z9454 [1 << 17]byte +var z9455 [1 << 17]byte +var z9456 [1 << 17]byte +var z9457 [1 << 17]byte +var z9458 [1 << 17]byte +var z9459 [1 << 17]byte +var z9460 [1 << 17]byte +var z9461 [1 << 17]byte +var z9462 [1 << 17]byte +var z9463 [1 << 17]byte +var z9464 [1 << 17]byte +var z9465 [1 << 17]byte +var z9466 [1 << 17]byte +var z9467 [1 << 17]byte +var z9468 [1 << 17]byte +var z9469 [1 << 17]byte +var z9470 [1 << 17]byte +var z9471 [1 << 17]byte +var z9472 [1 << 17]byte +var z9473 [1 << 17]byte +var z9474 [1 << 17]byte +var z9475 [1 << 17]byte +var z9476 [1 << 17]byte +var z9477 [1 << 17]byte +var z9478 [1 << 17]byte +var z9479 [1 << 17]byte +var z9480 [1 << 17]byte +var z9481 [1 << 17]byte +var z9482 [1 << 17]byte +var z9483 [1 << 17]byte +var z9484 [1 << 17]byte +var z9485 [1 << 17]byte +var z9486 [1 << 17]byte +var z9487 [1 << 17]byte +var z9488 [1 << 17]byte +var z9489 [1 << 17]byte +var z9490 [1 << 17]byte +var z9491 [1 << 17]byte +var z9492 [1 << 17]byte +var z9493 [1 << 17]byte +var z9494 [1 << 17]byte +var z9495 [1 << 17]byte +var z9496 [1 << 17]byte +var z9497 [1 << 17]byte +var z9498 [1 << 17]byte +var z9499 [1 << 17]byte +var z9500 [1 << 17]byte +var z9501 [1 << 17]byte +var z9502 [1 << 17]byte +var z9503 [1 << 17]byte +var z9504 [1 << 17]byte +var z9505 [1 << 17]byte +var z9506 [1 << 17]byte +var z9507 [1 << 17]byte +var z9508 [1 << 17]byte +var z9509 [1 << 17]byte +var z9510 [1 << 17]byte +var z9511 [1 << 17]byte +var z9512 [1 << 17]byte +var z9513 [1 << 17]byte +var z9514 [1 << 17]byte +var z9515 [1 << 17]byte +var z9516 [1 << 17]byte +var z9517 [1 << 17]byte +var z9518 [1 << 17]byte +var z9519 [1 << 17]byte +var z9520 [1 << 17]byte +var z9521 [1 << 17]byte +var z9522 [1 << 17]byte +var z9523 [1 << 17]byte +var z9524 [1 << 17]byte +var z9525 [1 << 17]byte +var z9526 [1 << 17]byte +var z9527 [1 << 17]byte +var z9528 [1 << 17]byte +var z9529 [1 << 17]byte +var z9530 [1 << 17]byte +var z9531 [1 << 17]byte +var z9532 [1 << 17]byte +var z9533 [1 << 17]byte +var z9534 [1 << 17]byte +var z9535 [1 << 17]byte +var z9536 [1 << 17]byte +var z9537 [1 << 17]byte +var z9538 [1 << 17]byte +var z9539 [1 << 17]byte +var z9540 [1 << 17]byte +var z9541 [1 << 17]byte +var z9542 [1 << 17]byte +var z9543 [1 << 17]byte +var z9544 [1 << 17]byte +var z9545 [1 << 17]byte +var z9546 [1 << 17]byte +var z9547 [1 << 17]byte +var z9548 [1 << 17]byte +var z9549 [1 << 17]byte +var z9550 [1 << 17]byte +var z9551 [1 << 17]byte +var z9552 [1 << 17]byte +var z9553 [1 << 17]byte +var z9554 [1 << 17]byte +var z9555 [1 << 17]byte +var z9556 [1 << 17]byte +var z9557 [1 << 17]byte +var z9558 [1 << 17]byte +var z9559 [1 << 17]byte +var z9560 [1 << 17]byte +var z9561 [1 << 17]byte +var z9562 [1 << 17]byte +var z9563 [1 << 17]byte +var z9564 [1 << 17]byte +var z9565 [1 << 17]byte +var z9566 [1 << 17]byte +var z9567 [1 << 17]byte +var z9568 [1 << 17]byte +var z9569 [1 << 17]byte +var z9570 [1 << 17]byte +var z9571 [1 << 17]byte +var z9572 [1 << 17]byte +var z9573 [1 << 17]byte +var z9574 [1 << 17]byte +var z9575 [1 << 17]byte +var z9576 [1 << 17]byte +var z9577 [1 << 17]byte +var z9578 [1 << 17]byte +var z9579 [1 << 17]byte +var z9580 [1 << 17]byte +var z9581 [1 << 17]byte +var z9582 [1 << 17]byte +var z9583 [1 << 17]byte +var z9584 [1 << 17]byte +var z9585 [1 << 17]byte +var z9586 [1 << 17]byte +var z9587 [1 << 17]byte +var z9588 [1 << 17]byte +var z9589 [1 << 17]byte +var z9590 [1 << 17]byte +var z9591 [1 << 17]byte +var z9592 [1 << 17]byte +var z9593 [1 << 17]byte +var z9594 [1 << 17]byte +var z9595 [1 << 17]byte +var z9596 [1 << 17]byte +var z9597 [1 << 17]byte +var z9598 [1 << 17]byte +var z9599 [1 << 17]byte +var z9600 [1 << 17]byte +var z9601 [1 << 17]byte +var z9602 [1 << 17]byte +var z9603 [1 << 17]byte +var z9604 [1 << 17]byte +var z9605 [1 << 17]byte +var z9606 [1 << 17]byte +var z9607 [1 << 17]byte +var z9608 [1 << 17]byte +var z9609 [1 << 17]byte +var z9610 [1 << 17]byte +var z9611 [1 << 17]byte +var z9612 [1 << 17]byte +var z9613 [1 << 17]byte +var z9614 [1 << 17]byte +var z9615 [1 << 17]byte +var z9616 [1 << 17]byte +var z9617 [1 << 17]byte +var z9618 [1 << 17]byte +var z9619 [1 << 17]byte +var z9620 [1 << 17]byte +var z9621 [1 << 17]byte +var z9622 [1 << 17]byte +var z9623 [1 << 17]byte +var z9624 [1 << 17]byte +var z9625 [1 << 17]byte +var z9626 [1 << 17]byte +var z9627 [1 << 17]byte +var z9628 [1 << 17]byte +var z9629 [1 << 17]byte +var z9630 [1 << 17]byte +var z9631 [1 << 17]byte +var z9632 [1 << 17]byte +var z9633 [1 << 17]byte +var z9634 [1 << 17]byte +var z9635 [1 << 17]byte +var z9636 [1 << 17]byte +var z9637 [1 << 17]byte +var z9638 [1 << 17]byte +var z9639 [1 << 17]byte +var z9640 [1 << 17]byte +var z9641 [1 << 17]byte +var z9642 [1 << 17]byte +var z9643 [1 << 17]byte +var z9644 [1 << 17]byte +var z9645 [1 << 17]byte +var z9646 [1 << 17]byte +var z9647 [1 << 17]byte +var z9648 [1 << 17]byte +var z9649 [1 << 17]byte +var z9650 [1 << 17]byte +var z9651 [1 << 17]byte +var z9652 [1 << 17]byte +var z9653 [1 << 17]byte +var z9654 [1 << 17]byte +var z9655 [1 << 17]byte +var z9656 [1 << 17]byte +var z9657 [1 << 17]byte +var z9658 [1 << 17]byte +var z9659 [1 << 17]byte +var z9660 [1 << 17]byte +var z9661 [1 << 17]byte +var z9662 [1 << 17]byte +var z9663 [1 << 17]byte +var z9664 [1 << 17]byte +var z9665 [1 << 17]byte +var z9666 [1 << 17]byte +var z9667 [1 << 17]byte +var z9668 [1 << 17]byte +var z9669 [1 << 17]byte +var z9670 [1 << 17]byte +var z9671 [1 << 17]byte +var z9672 [1 << 17]byte +var z9673 [1 << 17]byte +var z9674 [1 << 17]byte +var z9675 [1 << 17]byte +var z9676 [1 << 17]byte +var z9677 [1 << 17]byte +var z9678 [1 << 17]byte +var z9679 [1 << 17]byte +var z9680 [1 << 17]byte +var z9681 [1 << 17]byte +var z9682 [1 << 17]byte +var z9683 [1 << 17]byte +var z9684 [1 << 17]byte +var z9685 [1 << 17]byte +var z9686 [1 << 17]byte +var z9687 [1 << 17]byte +var z9688 [1 << 17]byte +var z9689 [1 << 17]byte +var z9690 [1 << 17]byte +var z9691 [1 << 17]byte +var z9692 [1 << 17]byte +var z9693 [1 << 17]byte +var z9694 [1 << 17]byte +var z9695 [1 << 17]byte +var z9696 [1 << 17]byte +var z9697 [1 << 17]byte +var z9698 [1 << 17]byte +var z9699 [1 << 17]byte +var z9700 [1 << 17]byte +var z9701 [1 << 17]byte +var z9702 [1 << 17]byte +var z9703 [1 << 17]byte +var z9704 [1 << 17]byte +var z9705 [1 << 17]byte +var z9706 [1 << 17]byte +var z9707 [1 << 17]byte +var z9708 [1 << 17]byte +var z9709 [1 << 17]byte +var z9710 [1 << 17]byte +var z9711 [1 << 17]byte +var z9712 [1 << 17]byte +var z9713 [1 << 17]byte +var z9714 [1 << 17]byte +var z9715 [1 << 17]byte +var z9716 [1 << 17]byte +var z9717 [1 << 17]byte +var z9718 [1 << 17]byte +var z9719 [1 << 17]byte +var z9720 [1 << 17]byte +var z9721 [1 << 17]byte +var z9722 [1 << 17]byte +var z9723 [1 << 17]byte +var z9724 [1 << 17]byte +var z9725 [1 << 17]byte +var z9726 [1 << 17]byte +var z9727 [1 << 17]byte +var z9728 [1 << 17]byte +var z9729 [1 << 17]byte +var z9730 [1 << 17]byte +var z9731 [1 << 17]byte +var z9732 [1 << 17]byte +var z9733 [1 << 17]byte +var z9734 [1 << 17]byte +var z9735 [1 << 17]byte +var z9736 [1 << 17]byte +var z9737 [1 << 17]byte +var z9738 [1 << 17]byte +var z9739 [1 << 17]byte +var z9740 [1 << 17]byte +var z9741 [1 << 17]byte +var z9742 [1 << 17]byte +var z9743 [1 << 17]byte +var z9744 [1 << 17]byte +var z9745 [1 << 17]byte +var z9746 [1 << 17]byte +var z9747 [1 << 17]byte +var z9748 [1 << 17]byte +var z9749 [1 << 17]byte +var z9750 [1 << 17]byte +var z9751 [1 << 17]byte +var z9752 [1 << 17]byte +var z9753 [1 << 17]byte +var z9754 [1 << 17]byte +var z9755 [1 << 17]byte +var z9756 [1 << 17]byte +var z9757 [1 << 17]byte +var z9758 [1 << 17]byte +var z9759 [1 << 17]byte +var z9760 [1 << 17]byte +var z9761 [1 << 17]byte +var z9762 [1 << 17]byte +var z9763 [1 << 17]byte +var z9764 [1 << 17]byte +var z9765 [1 << 17]byte +var z9766 [1 << 17]byte +var z9767 [1 << 17]byte +var z9768 [1 << 17]byte +var z9769 [1 << 17]byte +var z9770 [1 << 17]byte +var z9771 [1 << 17]byte +var z9772 [1 << 17]byte +var z9773 [1 << 17]byte +var z9774 [1 << 17]byte +var z9775 [1 << 17]byte +var z9776 [1 << 17]byte +var z9777 [1 << 17]byte +var z9778 [1 << 17]byte +var z9779 [1 << 17]byte +var z9780 [1 << 17]byte +var z9781 [1 << 17]byte +var z9782 [1 << 17]byte +var z9783 [1 << 17]byte +var z9784 [1 << 17]byte +var z9785 [1 << 17]byte +var z9786 [1 << 17]byte +var z9787 [1 << 17]byte +var z9788 [1 << 17]byte +var z9789 [1 << 17]byte +var z9790 [1 << 17]byte +var z9791 [1 << 17]byte +var z9792 [1 << 17]byte +var z9793 [1 << 17]byte +var z9794 [1 << 17]byte +var z9795 [1 << 17]byte +var z9796 [1 << 17]byte +var z9797 [1 << 17]byte +var z9798 [1 << 17]byte +var z9799 [1 << 17]byte +var z9800 [1 << 17]byte +var z9801 [1 << 17]byte +var z9802 [1 << 17]byte +var z9803 [1 << 17]byte +var z9804 [1 << 17]byte +var z9805 [1 << 17]byte +var z9806 [1 << 17]byte +var z9807 [1 << 17]byte +var z9808 [1 << 17]byte +var z9809 [1 << 17]byte +var z9810 [1 << 17]byte +var z9811 [1 << 17]byte +var z9812 [1 << 17]byte +var z9813 [1 << 17]byte +var z9814 [1 << 17]byte +var z9815 [1 << 17]byte +var z9816 [1 << 17]byte +var z9817 [1 << 17]byte +var z9818 [1 << 17]byte +var z9819 [1 << 17]byte +var z9820 [1 << 17]byte +var z9821 [1 << 17]byte +var z9822 [1 << 17]byte +var z9823 [1 << 17]byte +var z9824 [1 << 17]byte +var z9825 [1 << 17]byte +var z9826 [1 << 17]byte +var z9827 [1 << 17]byte +var z9828 [1 << 17]byte +var z9829 [1 << 17]byte +var z9830 [1 << 17]byte +var z9831 [1 << 17]byte +var z9832 [1 << 17]byte +var z9833 [1 << 17]byte +var z9834 [1 << 17]byte +var z9835 [1 << 17]byte +var z9836 [1 << 17]byte +var z9837 [1 << 17]byte +var z9838 [1 << 17]byte +var z9839 [1 << 17]byte +var z9840 [1 << 17]byte +var z9841 [1 << 17]byte +var z9842 [1 << 17]byte +var z9843 [1 << 17]byte +var z9844 [1 << 17]byte +var z9845 [1 << 17]byte +var z9846 [1 << 17]byte +var z9847 [1 << 17]byte +var z9848 [1 << 17]byte +var z9849 [1 << 17]byte +var z9850 [1 << 17]byte +var z9851 [1 << 17]byte +var z9852 [1 << 17]byte +var z9853 [1 << 17]byte +var z9854 [1 << 17]byte +var z9855 [1 << 17]byte +var z9856 [1 << 17]byte +var z9857 [1 << 17]byte +var z9858 [1 << 17]byte +var z9859 [1 << 17]byte +var z9860 [1 << 17]byte +var z9861 [1 << 17]byte +var z9862 [1 << 17]byte +var z9863 [1 << 17]byte +var z9864 [1 << 17]byte +var z9865 [1 << 17]byte +var z9866 [1 << 17]byte +var z9867 [1 << 17]byte +var z9868 [1 << 17]byte +var z9869 [1 << 17]byte +var z9870 [1 << 17]byte +var z9871 [1 << 17]byte +var z9872 [1 << 17]byte +var z9873 [1 << 17]byte +var z9874 [1 << 17]byte +var z9875 [1 << 17]byte +var z9876 [1 << 17]byte +var z9877 [1 << 17]byte +var z9878 [1 << 17]byte +var z9879 [1 << 17]byte +var z9880 [1 << 17]byte +var z9881 [1 << 17]byte +var z9882 [1 << 17]byte +var z9883 [1 << 17]byte +var z9884 [1 << 17]byte +var z9885 [1 << 17]byte +var z9886 [1 << 17]byte +var z9887 [1 << 17]byte +var z9888 [1 << 17]byte +var z9889 [1 << 17]byte +var z9890 [1 << 17]byte +var z9891 [1 << 17]byte +var z9892 [1 << 17]byte +var z9893 [1 << 17]byte +var z9894 [1 << 17]byte +var z9895 [1 << 17]byte +var z9896 [1 << 17]byte +var z9897 [1 << 17]byte +var z9898 [1 << 17]byte +var z9899 [1 << 17]byte +var z9900 [1 << 17]byte +var z9901 [1 << 17]byte +var z9902 [1 << 17]byte +var z9903 [1 << 17]byte +var z9904 [1 << 17]byte +var z9905 [1 << 17]byte +var z9906 [1 << 17]byte +var z9907 [1 << 17]byte +var z9908 [1 << 17]byte +var z9909 [1 << 17]byte +var z9910 [1 << 17]byte +var z9911 [1 << 17]byte +var z9912 [1 << 17]byte +var z9913 [1 << 17]byte +var z9914 [1 << 17]byte +var z9915 [1 << 17]byte +var z9916 [1 << 17]byte +var z9917 [1 << 17]byte +var z9918 [1 << 17]byte +var z9919 [1 << 17]byte +var z9920 [1 << 17]byte +var z9921 [1 << 17]byte +var z9922 [1 << 17]byte +var z9923 [1 << 17]byte +var z9924 [1 << 17]byte +var z9925 [1 << 17]byte +var z9926 [1 << 17]byte +var z9927 [1 << 17]byte +var z9928 [1 << 17]byte +var z9929 [1 << 17]byte +var z9930 [1 << 17]byte +var z9931 [1 << 17]byte +var z9932 [1 << 17]byte +var z9933 [1 << 17]byte +var z9934 [1 << 17]byte +var z9935 [1 << 17]byte +var z9936 [1 << 17]byte +var z9937 [1 << 17]byte +var z9938 [1 << 17]byte +var z9939 [1 << 17]byte +var z9940 [1 << 17]byte +var z9941 [1 << 17]byte +var z9942 [1 << 17]byte +var z9943 [1 << 17]byte +var z9944 [1 << 17]byte +var z9945 [1 << 17]byte +var z9946 [1 << 17]byte +var z9947 [1 << 17]byte +var z9948 [1 << 17]byte +var z9949 [1 << 17]byte +var z9950 [1 << 17]byte +var z9951 [1 << 17]byte +var z9952 [1 << 17]byte +var z9953 [1 << 17]byte +var z9954 [1 << 17]byte +var z9955 [1 << 17]byte +var z9956 [1 << 17]byte +var z9957 [1 << 17]byte +var z9958 [1 << 17]byte +var z9959 [1 << 17]byte +var z9960 [1 << 17]byte +var z9961 [1 << 17]byte +var z9962 [1 << 17]byte +var z9963 [1 << 17]byte +var z9964 [1 << 17]byte +var z9965 [1 << 17]byte +var z9966 [1 << 17]byte +var z9967 [1 << 17]byte +var z9968 [1 << 17]byte +var z9969 [1 << 17]byte +var z9970 [1 << 17]byte +var z9971 [1 << 17]byte +var z9972 [1 << 17]byte +var z9973 [1 << 17]byte +var z9974 [1 << 17]byte +var z9975 [1 << 17]byte +var z9976 [1 << 17]byte +var z9977 [1 << 17]byte +var z9978 [1 << 17]byte +var z9979 [1 << 17]byte +var z9980 [1 << 17]byte +var z9981 [1 << 17]byte +var z9982 [1 << 17]byte +var z9983 [1 << 17]byte +var z9984 [1 << 17]byte +var z9985 [1 << 17]byte +var z9986 [1 << 17]byte +var z9987 [1 << 17]byte +var z9988 [1 << 17]byte +var z9989 [1 << 17]byte +var z9990 [1 << 17]byte +var z9991 [1 << 17]byte +var z9992 [1 << 17]byte +var z9993 [1 << 17]byte +var z9994 [1 << 17]byte +var z9995 [1 << 17]byte +var z9996 [1 << 17]byte +var z9997 [1 << 17]byte +var z9998 [1 << 17]byte +var z9999 [1 << 17]byte +var z10000 [1 << 17]byte +var z10001 [1 << 17]byte +var z10002 [1 << 17]byte +var z10003 [1 << 17]byte +var z10004 [1 << 17]byte +var z10005 [1 << 17]byte +var z10006 [1 << 17]byte +var z10007 [1 << 17]byte +var z10008 [1 << 17]byte +var z10009 [1 << 17]byte +var z10010 [1 << 17]byte +var z10011 [1 << 17]byte +var z10012 [1 << 17]byte +var z10013 [1 << 17]byte +var z10014 [1 << 17]byte +var z10015 [1 << 17]byte +var z10016 [1 << 17]byte +var z10017 [1 << 17]byte +var z10018 [1 << 17]byte +var z10019 [1 << 17]byte +var z10020 [1 << 17]byte +var z10021 [1 << 17]byte +var z10022 [1 << 17]byte +var z10023 [1 << 17]byte +var z10024 [1 << 17]byte +var z10025 [1 << 17]byte +var z10026 [1 << 17]byte +var z10027 [1 << 17]byte +var z10028 [1 << 17]byte +var z10029 [1 << 17]byte +var z10030 [1 << 17]byte +var z10031 [1 << 17]byte +var z10032 [1 << 17]byte +var z10033 [1 << 17]byte +var z10034 [1 << 17]byte +var z10035 [1 << 17]byte +var z10036 [1 << 17]byte +var z10037 [1 << 17]byte +var z10038 [1 << 17]byte +var z10039 [1 << 17]byte +var z10040 [1 << 17]byte +var z10041 [1 << 17]byte +var z10042 [1 << 17]byte +var z10043 [1 << 17]byte +var z10044 [1 << 17]byte +var z10045 [1 << 17]byte +var z10046 [1 << 17]byte +var z10047 [1 << 17]byte +var z10048 [1 << 17]byte +var z10049 [1 << 17]byte +var z10050 [1 << 17]byte +var z10051 [1 << 17]byte +var z10052 [1 << 17]byte +var z10053 [1 << 17]byte +var z10054 [1 << 17]byte +var z10055 [1 << 17]byte +var z10056 [1 << 17]byte +var z10057 [1 << 17]byte +var z10058 [1 << 17]byte +var z10059 [1 << 17]byte +var z10060 [1 << 17]byte +var z10061 [1 << 17]byte +var z10062 [1 << 17]byte +var z10063 [1 << 17]byte +var z10064 [1 << 17]byte +var z10065 [1 << 17]byte +var z10066 [1 << 17]byte +var z10067 [1 << 17]byte +var z10068 [1 << 17]byte +var z10069 [1 << 17]byte +var z10070 [1 << 17]byte +var z10071 [1 << 17]byte +var z10072 [1 << 17]byte +var z10073 [1 << 17]byte +var z10074 [1 << 17]byte +var z10075 [1 << 17]byte +var z10076 [1 << 17]byte +var z10077 [1 << 17]byte +var z10078 [1 << 17]byte +var z10079 [1 << 17]byte +var z10080 [1 << 17]byte +var z10081 [1 << 17]byte +var z10082 [1 << 17]byte +var z10083 [1 << 17]byte +var z10084 [1 << 17]byte +var z10085 [1 << 17]byte +var z10086 [1 << 17]byte +var z10087 [1 << 17]byte +var z10088 [1 << 17]byte +var z10089 [1 << 17]byte +var z10090 [1 << 17]byte +var z10091 [1 << 17]byte +var z10092 [1 << 17]byte +var z10093 [1 << 17]byte +var z10094 [1 << 17]byte +var z10095 [1 << 17]byte +var z10096 [1 << 17]byte +var z10097 [1 << 17]byte +var z10098 [1 << 17]byte +var z10099 [1 << 17]byte +var z10100 [1 << 17]byte +var z10101 [1 << 17]byte +var z10102 [1 << 17]byte +var z10103 [1 << 17]byte +var z10104 [1 << 17]byte +var z10105 [1 << 17]byte +var z10106 [1 << 17]byte +var z10107 [1 << 17]byte +var z10108 [1 << 17]byte +var z10109 [1 << 17]byte +var z10110 [1 << 17]byte +var z10111 [1 << 17]byte +var z10112 [1 << 17]byte +var z10113 [1 << 17]byte +var z10114 [1 << 17]byte +var z10115 [1 << 17]byte +var z10116 [1 << 17]byte +var z10117 [1 << 17]byte +var z10118 [1 << 17]byte +var z10119 [1 << 17]byte +var z10120 [1 << 17]byte +var z10121 [1 << 17]byte +var z10122 [1 << 17]byte +var z10123 [1 << 17]byte +var z10124 [1 << 17]byte +var z10125 [1 << 17]byte +var z10126 [1 << 17]byte +var z10127 [1 << 17]byte +var z10128 [1 << 17]byte +var z10129 [1 << 17]byte +var z10130 [1 << 17]byte +var z10131 [1 << 17]byte +var z10132 [1 << 17]byte +var z10133 [1 << 17]byte +var z10134 [1 << 17]byte +var z10135 [1 << 17]byte +var z10136 [1 << 17]byte +var z10137 [1 << 17]byte +var z10138 [1 << 17]byte +var z10139 [1 << 17]byte +var z10140 [1 << 17]byte +var z10141 [1 << 17]byte +var z10142 [1 << 17]byte +var z10143 [1 << 17]byte +var z10144 [1 << 17]byte +var z10145 [1 << 17]byte +var z10146 [1 << 17]byte +var z10147 [1 << 17]byte +var z10148 [1 << 17]byte +var z10149 [1 << 17]byte +var z10150 [1 << 17]byte +var z10151 [1 << 17]byte +var z10152 [1 << 17]byte +var z10153 [1 << 17]byte +var z10154 [1 << 17]byte +var z10155 [1 << 17]byte +var z10156 [1 << 17]byte +var z10157 [1 << 17]byte +var z10158 [1 << 17]byte +var z10159 [1 << 17]byte +var z10160 [1 << 17]byte +var z10161 [1 << 17]byte +var z10162 [1 << 17]byte +var z10163 [1 << 17]byte +var z10164 [1 << 17]byte +var z10165 [1 << 17]byte +var z10166 [1 << 17]byte +var z10167 [1 << 17]byte +var z10168 [1 << 17]byte +var z10169 [1 << 17]byte +var z10170 [1 << 17]byte +var z10171 [1 << 17]byte +var z10172 [1 << 17]byte +var z10173 [1 << 17]byte +var z10174 [1 << 17]byte +var z10175 [1 << 17]byte +var z10176 [1 << 17]byte +var z10177 [1 << 17]byte +var z10178 [1 << 17]byte +var z10179 [1 << 17]byte +var z10180 [1 << 17]byte +var z10181 [1 << 17]byte +var z10182 [1 << 17]byte +var z10183 [1 << 17]byte +var z10184 [1 << 17]byte +var z10185 [1 << 17]byte +var z10186 [1 << 17]byte +var z10187 [1 << 17]byte +var z10188 [1 << 17]byte +var z10189 [1 << 17]byte +var z10190 [1 << 17]byte +var z10191 [1 << 17]byte +var z10192 [1 << 17]byte +var z10193 [1 << 17]byte +var z10194 [1 << 17]byte +var z10195 [1 << 17]byte +var z10196 [1 << 17]byte +var z10197 [1 << 17]byte +var z10198 [1 << 17]byte +var z10199 [1 << 17]byte +var z10200 [1 << 17]byte +var z10201 [1 << 17]byte +var z10202 [1 << 17]byte +var z10203 [1 << 17]byte +var z10204 [1 << 17]byte +var z10205 [1 << 17]byte +var z10206 [1 << 17]byte +var z10207 [1 << 17]byte +var z10208 [1 << 17]byte +var z10209 [1 << 17]byte +var z10210 [1 << 17]byte +var z10211 [1 << 17]byte +var z10212 [1 << 17]byte +var z10213 [1 << 17]byte +var z10214 [1 << 17]byte +var z10215 [1 << 17]byte +var z10216 [1 << 17]byte +var z10217 [1 << 17]byte +var z10218 [1 << 17]byte +var z10219 [1 << 17]byte +var z10220 [1 << 17]byte +var z10221 [1 << 17]byte +var z10222 [1 << 17]byte +var z10223 [1 << 17]byte +var z10224 [1 << 17]byte +var z10225 [1 << 17]byte +var z10226 [1 << 17]byte +var z10227 [1 << 17]byte +var z10228 [1 << 17]byte +var z10229 [1 << 17]byte +var z10230 [1 << 17]byte +var z10231 [1 << 17]byte +var z10232 [1 << 17]byte +var z10233 [1 << 17]byte +var z10234 [1 << 17]byte +var z10235 [1 << 17]byte +var z10236 [1 << 17]byte +var z10237 [1 << 17]byte +var z10238 [1 << 17]byte +var z10239 [1 << 17]byte +var z10240 [1 << 17]byte +var z10241 [1 << 17]byte +var z10242 [1 << 17]byte +var z10243 [1 << 17]byte +var z10244 [1 << 17]byte +var z10245 [1 << 17]byte +var z10246 [1 << 17]byte +var z10247 [1 << 17]byte +var z10248 [1 << 17]byte +var z10249 [1 << 17]byte +var z10250 [1 << 17]byte +var z10251 [1 << 17]byte +var z10252 [1 << 17]byte +var z10253 [1 << 17]byte +var z10254 [1 << 17]byte +var z10255 [1 << 17]byte +var z10256 [1 << 17]byte +var z10257 [1 << 17]byte +var z10258 [1 << 17]byte +var z10259 [1 << 17]byte +var z10260 [1 << 17]byte +var z10261 [1 << 17]byte +var z10262 [1 << 17]byte +var z10263 [1 << 17]byte +var z10264 [1 << 17]byte +var z10265 [1 << 17]byte +var z10266 [1 << 17]byte +var z10267 [1 << 17]byte +var z10268 [1 << 17]byte +var z10269 [1 << 17]byte +var z10270 [1 << 17]byte +var z10271 [1 << 17]byte +var z10272 [1 << 17]byte +var z10273 [1 << 17]byte +var z10274 [1 << 17]byte +var z10275 [1 << 17]byte +var z10276 [1 << 17]byte +var z10277 [1 << 17]byte +var z10278 [1 << 17]byte +var z10279 [1 << 17]byte +var z10280 [1 << 17]byte +var z10281 [1 << 17]byte +var z10282 [1 << 17]byte +var z10283 [1 << 17]byte +var z10284 [1 << 17]byte +var z10285 [1 << 17]byte +var z10286 [1 << 17]byte +var z10287 [1 << 17]byte +var z10288 [1 << 17]byte +var z10289 [1 << 17]byte +var z10290 [1 << 17]byte +var z10291 [1 << 17]byte +var z10292 [1 << 17]byte +var z10293 [1 << 17]byte +var z10294 [1 << 17]byte +var z10295 [1 << 17]byte +var z10296 [1 << 17]byte +var z10297 [1 << 17]byte +var z10298 [1 << 17]byte +var z10299 [1 << 17]byte +var z10300 [1 << 17]byte +var z10301 [1 << 17]byte +var z10302 [1 << 17]byte +var z10303 [1 << 17]byte +var z10304 [1 << 17]byte +var z10305 [1 << 17]byte +var z10306 [1 << 17]byte +var z10307 [1 << 17]byte +var z10308 [1 << 17]byte +var z10309 [1 << 17]byte +var z10310 [1 << 17]byte +var z10311 [1 << 17]byte +var z10312 [1 << 17]byte +var z10313 [1 << 17]byte +var z10314 [1 << 17]byte +var z10315 [1 << 17]byte +var z10316 [1 << 17]byte +var z10317 [1 << 17]byte +var z10318 [1 << 17]byte +var z10319 [1 << 17]byte +var z10320 [1 << 17]byte +var z10321 [1 << 17]byte +var z10322 [1 << 17]byte +var z10323 [1 << 17]byte +var z10324 [1 << 17]byte +var z10325 [1 << 17]byte +var z10326 [1 << 17]byte +var z10327 [1 << 17]byte +var z10328 [1 << 17]byte +var z10329 [1 << 17]byte +var z10330 [1 << 17]byte +var z10331 [1 << 17]byte +var z10332 [1 << 17]byte +var z10333 [1 << 17]byte +var z10334 [1 << 17]byte +var z10335 [1 << 17]byte +var z10336 [1 << 17]byte +var z10337 [1 << 17]byte +var z10338 [1 << 17]byte +var z10339 [1 << 17]byte +var z10340 [1 << 17]byte +var z10341 [1 << 17]byte +var z10342 [1 << 17]byte +var z10343 [1 << 17]byte +var z10344 [1 << 17]byte +var z10345 [1 << 17]byte +var z10346 [1 << 17]byte +var z10347 [1 << 17]byte +var z10348 [1 << 17]byte +var z10349 [1 << 17]byte +var z10350 [1 << 17]byte +var z10351 [1 << 17]byte +var z10352 [1 << 17]byte +var z10353 [1 << 17]byte +var z10354 [1 << 17]byte +var z10355 [1 << 17]byte +var z10356 [1 << 17]byte +var z10357 [1 << 17]byte +var z10358 [1 << 17]byte +var z10359 [1 << 17]byte +var z10360 [1 << 17]byte +var z10361 [1 << 17]byte +var z10362 [1 << 17]byte +var z10363 [1 << 17]byte +var z10364 [1 << 17]byte +var z10365 [1 << 17]byte +var z10366 [1 << 17]byte +var z10367 [1 << 17]byte +var z10368 [1 << 17]byte +var z10369 [1 << 17]byte +var z10370 [1 << 17]byte +var z10371 [1 << 17]byte +var z10372 [1 << 17]byte +var z10373 [1 << 17]byte +var z10374 [1 << 17]byte +var z10375 [1 << 17]byte +var z10376 [1 << 17]byte +var z10377 [1 << 17]byte +var z10378 [1 << 17]byte +var z10379 [1 << 17]byte +var z10380 [1 << 17]byte +var z10381 [1 << 17]byte +var z10382 [1 << 17]byte +var z10383 [1 << 17]byte +var z10384 [1 << 17]byte +var z10385 [1 << 17]byte +var z10386 [1 << 17]byte +var z10387 [1 << 17]byte +var z10388 [1 << 17]byte +var z10389 [1 << 17]byte +var z10390 [1 << 17]byte +var z10391 [1 << 17]byte +var z10392 [1 << 17]byte +var z10393 [1 << 17]byte +var z10394 [1 << 17]byte +var z10395 [1 << 17]byte +var z10396 [1 << 17]byte +var z10397 [1 << 17]byte +var z10398 [1 << 17]byte +var z10399 [1 << 17]byte +var z10400 [1 << 17]byte +var z10401 [1 << 17]byte +var z10402 [1 << 17]byte +var z10403 [1 << 17]byte +var z10404 [1 << 17]byte +var z10405 [1 << 17]byte +var z10406 [1 << 17]byte +var z10407 [1 << 17]byte +var z10408 [1 << 17]byte +var z10409 [1 << 17]byte +var z10410 [1 << 17]byte +var z10411 [1 << 17]byte +var z10412 [1 << 17]byte +var z10413 [1 << 17]byte +var z10414 [1 << 17]byte +var z10415 [1 << 17]byte +var z10416 [1 << 17]byte +var z10417 [1 << 17]byte +var z10418 [1 << 17]byte +var z10419 [1 << 17]byte +var z10420 [1 << 17]byte +var z10421 [1 << 17]byte +var z10422 [1 << 17]byte +var z10423 [1 << 17]byte +var z10424 [1 << 17]byte +var z10425 [1 << 17]byte +var z10426 [1 << 17]byte +var z10427 [1 << 17]byte +var z10428 [1 << 17]byte +var z10429 [1 << 17]byte +var z10430 [1 << 17]byte +var z10431 [1 << 17]byte +var z10432 [1 << 17]byte +var z10433 [1 << 17]byte +var z10434 [1 << 17]byte +var z10435 [1 << 17]byte +var z10436 [1 << 17]byte +var z10437 [1 << 17]byte +var z10438 [1 << 17]byte +var z10439 [1 << 17]byte +var z10440 [1 << 17]byte +var z10441 [1 << 17]byte +var z10442 [1 << 17]byte +var z10443 [1 << 17]byte +var z10444 [1 << 17]byte +var z10445 [1 << 17]byte +var z10446 [1 << 17]byte +var z10447 [1 << 17]byte +var z10448 [1 << 17]byte +var z10449 [1 << 17]byte +var z10450 [1 << 17]byte +var z10451 [1 << 17]byte +var z10452 [1 << 17]byte +var z10453 [1 << 17]byte +var z10454 [1 << 17]byte +var z10455 [1 << 17]byte +var z10456 [1 << 17]byte +var z10457 [1 << 17]byte +var z10458 [1 << 17]byte +var z10459 [1 << 17]byte +var z10460 [1 << 17]byte +var z10461 [1 << 17]byte +var z10462 [1 << 17]byte +var z10463 [1 << 17]byte +var z10464 [1 << 17]byte +var z10465 [1 << 17]byte +var z10466 [1 << 17]byte +var z10467 [1 << 17]byte +var z10468 [1 << 17]byte +var z10469 [1 << 17]byte +var z10470 [1 << 17]byte +var z10471 [1 << 17]byte +var z10472 [1 << 17]byte +var z10473 [1 << 17]byte +var z10474 [1 << 17]byte +var z10475 [1 << 17]byte +var z10476 [1 << 17]byte +var z10477 [1 << 17]byte +var z10478 [1 << 17]byte +var z10479 [1 << 17]byte +var z10480 [1 << 17]byte +var z10481 [1 << 17]byte +var z10482 [1 << 17]byte +var z10483 [1 << 17]byte +var z10484 [1 << 17]byte +var z10485 [1 << 17]byte +var z10486 [1 << 17]byte +var z10487 [1 << 17]byte +var z10488 [1 << 17]byte +var z10489 [1 << 17]byte +var z10490 [1 << 17]byte +var z10491 [1 << 17]byte +var z10492 [1 << 17]byte +var z10493 [1 << 17]byte +var z10494 [1 << 17]byte +var z10495 [1 << 17]byte +var z10496 [1 << 17]byte +var z10497 [1 << 17]byte +var z10498 [1 << 17]byte +var z10499 [1 << 17]byte +var z10500 [1 << 17]byte +var z10501 [1 << 17]byte +var z10502 [1 << 17]byte +var z10503 [1 << 17]byte +var z10504 [1 << 17]byte +var z10505 [1 << 17]byte +var z10506 [1 << 17]byte +var z10507 [1 << 17]byte +var z10508 [1 << 17]byte +var z10509 [1 << 17]byte +var z10510 [1 << 17]byte +var z10511 [1 << 17]byte +var z10512 [1 << 17]byte +var z10513 [1 << 17]byte +var z10514 [1 << 17]byte +var z10515 [1 << 17]byte +var z10516 [1 << 17]byte +var z10517 [1 << 17]byte +var z10518 [1 << 17]byte +var z10519 [1 << 17]byte +var z10520 [1 << 17]byte +var z10521 [1 << 17]byte +var z10522 [1 << 17]byte +var z10523 [1 << 17]byte +var z10524 [1 << 17]byte +var z10525 [1 << 17]byte +var z10526 [1 << 17]byte +var z10527 [1 << 17]byte +var z10528 [1 << 17]byte +var z10529 [1 << 17]byte +var z10530 [1 << 17]byte +var z10531 [1 << 17]byte +var z10532 [1 << 17]byte +var z10533 [1 << 17]byte +var z10534 [1 << 17]byte +var z10535 [1 << 17]byte +var z10536 [1 << 17]byte +var z10537 [1 << 17]byte +var z10538 [1 << 17]byte +var z10539 [1 << 17]byte +var z10540 [1 << 17]byte +var z10541 [1 << 17]byte +var z10542 [1 << 17]byte +var z10543 [1 << 17]byte +var z10544 [1 << 17]byte +var z10545 [1 << 17]byte +var z10546 [1 << 17]byte +var z10547 [1 << 17]byte +var z10548 [1 << 17]byte +var z10549 [1 << 17]byte +var z10550 [1 << 17]byte +var z10551 [1 << 17]byte +var z10552 [1 << 17]byte +var z10553 [1 << 17]byte +var z10554 [1 << 17]byte +var z10555 [1 << 17]byte +var z10556 [1 << 17]byte +var z10557 [1 << 17]byte +var z10558 [1 << 17]byte +var z10559 [1 << 17]byte +var z10560 [1 << 17]byte +var z10561 [1 << 17]byte +var z10562 [1 << 17]byte +var z10563 [1 << 17]byte +var z10564 [1 << 17]byte +var z10565 [1 << 17]byte +var z10566 [1 << 17]byte +var z10567 [1 << 17]byte +var z10568 [1 << 17]byte +var z10569 [1 << 17]byte +var z10570 [1 << 17]byte +var z10571 [1 << 17]byte +var z10572 [1 << 17]byte +var z10573 [1 << 17]byte +var z10574 [1 << 17]byte +var z10575 [1 << 17]byte +var z10576 [1 << 17]byte +var z10577 [1 << 17]byte +var z10578 [1 << 17]byte +var z10579 [1 << 17]byte +var z10580 [1 << 17]byte +var z10581 [1 << 17]byte +var z10582 [1 << 17]byte +var z10583 [1 << 17]byte +var z10584 [1 << 17]byte +var z10585 [1 << 17]byte +var z10586 [1 << 17]byte +var z10587 [1 << 17]byte +var z10588 [1 << 17]byte +var z10589 [1 << 17]byte +var z10590 [1 << 17]byte +var z10591 [1 << 17]byte +var z10592 [1 << 17]byte +var z10593 [1 << 17]byte +var z10594 [1 << 17]byte +var z10595 [1 << 17]byte +var z10596 [1 << 17]byte +var z10597 [1 << 17]byte +var z10598 [1 << 17]byte +var z10599 [1 << 17]byte +var z10600 [1 << 17]byte +var z10601 [1 << 17]byte +var z10602 [1 << 17]byte +var z10603 [1 << 17]byte +var z10604 [1 << 17]byte +var z10605 [1 << 17]byte +var z10606 [1 << 17]byte +var z10607 [1 << 17]byte +var z10608 [1 << 17]byte +var z10609 [1 << 17]byte +var z10610 [1 << 17]byte +var z10611 [1 << 17]byte +var z10612 [1 << 17]byte +var z10613 [1 << 17]byte +var z10614 [1 << 17]byte +var z10615 [1 << 17]byte +var z10616 [1 << 17]byte +var z10617 [1 << 17]byte +var z10618 [1 << 17]byte +var z10619 [1 << 17]byte +var z10620 [1 << 17]byte +var z10621 [1 << 17]byte +var z10622 [1 << 17]byte +var z10623 [1 << 17]byte +var z10624 [1 << 17]byte +var z10625 [1 << 17]byte +var z10626 [1 << 17]byte +var z10627 [1 << 17]byte +var z10628 [1 << 17]byte +var z10629 [1 << 17]byte +var z10630 [1 << 17]byte +var z10631 [1 << 17]byte +var z10632 [1 << 17]byte +var z10633 [1 << 17]byte +var z10634 [1 << 17]byte +var z10635 [1 << 17]byte +var z10636 [1 << 17]byte +var z10637 [1 << 17]byte +var z10638 [1 << 17]byte +var z10639 [1 << 17]byte +var z10640 [1 << 17]byte +var z10641 [1 << 17]byte +var z10642 [1 << 17]byte +var z10643 [1 << 17]byte +var z10644 [1 << 17]byte +var z10645 [1 << 17]byte +var z10646 [1 << 17]byte +var z10647 [1 << 17]byte +var z10648 [1 << 17]byte +var z10649 [1 << 17]byte +var z10650 [1 << 17]byte +var z10651 [1 << 17]byte +var z10652 [1 << 17]byte +var z10653 [1 << 17]byte +var z10654 [1 << 17]byte +var z10655 [1 << 17]byte +var z10656 [1 << 17]byte +var z10657 [1 << 17]byte +var z10658 [1 << 17]byte +var z10659 [1 << 17]byte +var z10660 [1 << 17]byte +var z10661 [1 << 17]byte +var z10662 [1 << 17]byte +var z10663 [1 << 17]byte +var z10664 [1 << 17]byte +var z10665 [1 << 17]byte +var z10666 [1 << 17]byte +var z10667 [1 << 17]byte +var z10668 [1 << 17]byte +var z10669 [1 << 17]byte +var z10670 [1 << 17]byte +var z10671 [1 << 17]byte +var z10672 [1 << 17]byte +var z10673 [1 << 17]byte +var z10674 [1 << 17]byte +var z10675 [1 << 17]byte +var z10676 [1 << 17]byte +var z10677 [1 << 17]byte +var z10678 [1 << 17]byte +var z10679 [1 << 17]byte +var z10680 [1 << 17]byte +var z10681 [1 << 17]byte +var z10682 [1 << 17]byte +var z10683 [1 << 17]byte +var z10684 [1 << 17]byte +var z10685 [1 << 17]byte +var z10686 [1 << 17]byte +var z10687 [1 << 17]byte +var z10688 [1 << 17]byte +var z10689 [1 << 17]byte +var z10690 [1 << 17]byte +var z10691 [1 << 17]byte +var z10692 [1 << 17]byte +var z10693 [1 << 17]byte +var z10694 [1 << 17]byte +var z10695 [1 << 17]byte +var z10696 [1 << 17]byte +var z10697 [1 << 17]byte +var z10698 [1 << 17]byte +var z10699 [1 << 17]byte +var z10700 [1 << 17]byte +var z10701 [1 << 17]byte +var z10702 [1 << 17]byte +var z10703 [1 << 17]byte +var z10704 [1 << 17]byte +var z10705 [1 << 17]byte +var z10706 [1 << 17]byte +var z10707 [1 << 17]byte +var z10708 [1 << 17]byte +var z10709 [1 << 17]byte +var z10710 [1 << 17]byte +var z10711 [1 << 17]byte +var z10712 [1 << 17]byte +var z10713 [1 << 17]byte +var z10714 [1 << 17]byte +var z10715 [1 << 17]byte +var z10716 [1 << 17]byte +var z10717 [1 << 17]byte +var z10718 [1 << 17]byte +var z10719 [1 << 17]byte +var z10720 [1 << 17]byte +var z10721 [1 << 17]byte +var z10722 [1 << 17]byte +var z10723 [1 << 17]byte +var z10724 [1 << 17]byte +var z10725 [1 << 17]byte +var z10726 [1 << 17]byte +var z10727 [1 << 17]byte +var z10728 [1 << 17]byte +var z10729 [1 << 17]byte +var z10730 [1 << 17]byte +var z10731 [1 << 17]byte +var z10732 [1 << 17]byte +var z10733 [1 << 17]byte +var z10734 [1 << 17]byte +var z10735 [1 << 17]byte +var z10736 [1 << 17]byte +var z10737 [1 << 17]byte +var z10738 [1 << 17]byte +var z10739 [1 << 17]byte +var z10740 [1 << 17]byte +var z10741 [1 << 17]byte +var z10742 [1 << 17]byte +var z10743 [1 << 17]byte +var z10744 [1 << 17]byte +var z10745 [1 << 17]byte +var z10746 [1 << 17]byte +var z10747 [1 << 17]byte +var z10748 [1 << 17]byte +var z10749 [1 << 17]byte +var z10750 [1 << 17]byte +var z10751 [1 << 17]byte +var z10752 [1 << 17]byte +var z10753 [1 << 17]byte +var z10754 [1 << 17]byte +var z10755 [1 << 17]byte +var z10756 [1 << 17]byte +var z10757 [1 << 17]byte +var z10758 [1 << 17]byte +var z10759 [1 << 17]byte +var z10760 [1 << 17]byte +var z10761 [1 << 17]byte +var z10762 [1 << 17]byte +var z10763 [1 << 17]byte +var z10764 [1 << 17]byte +var z10765 [1 << 17]byte +var z10766 [1 << 17]byte +var z10767 [1 << 17]byte +var z10768 [1 << 17]byte +var z10769 [1 << 17]byte +var z10770 [1 << 17]byte +var z10771 [1 << 17]byte +var z10772 [1 << 17]byte +var z10773 [1 << 17]byte +var z10774 [1 << 17]byte +var z10775 [1 << 17]byte +var z10776 [1 << 17]byte +var z10777 [1 << 17]byte +var z10778 [1 << 17]byte +var z10779 [1 << 17]byte +var z10780 [1 << 17]byte +var z10781 [1 << 17]byte +var z10782 [1 << 17]byte +var z10783 [1 << 17]byte +var z10784 [1 << 17]byte +var z10785 [1 << 17]byte +var z10786 [1 << 17]byte +var z10787 [1 << 17]byte +var z10788 [1 << 17]byte +var z10789 [1 << 17]byte +var z10790 [1 << 17]byte +var z10791 [1 << 17]byte +var z10792 [1 << 17]byte +var z10793 [1 << 17]byte +var z10794 [1 << 17]byte +var z10795 [1 << 17]byte +var z10796 [1 << 17]byte +var z10797 [1 << 17]byte +var z10798 [1 << 17]byte +var z10799 [1 << 17]byte +var z10800 [1 << 17]byte +var z10801 [1 << 17]byte +var z10802 [1 << 17]byte +var z10803 [1 << 17]byte +var z10804 [1 << 17]byte +var z10805 [1 << 17]byte +var z10806 [1 << 17]byte +var z10807 [1 << 17]byte +var z10808 [1 << 17]byte +var z10809 [1 << 17]byte +var z10810 [1 << 17]byte +var z10811 [1 << 17]byte +var z10812 [1 << 17]byte +var z10813 [1 << 17]byte +var z10814 [1 << 17]byte +var z10815 [1 << 17]byte +var z10816 [1 << 17]byte +var z10817 [1 << 17]byte +var z10818 [1 << 17]byte +var z10819 [1 << 17]byte +var z10820 [1 << 17]byte +var z10821 [1 << 17]byte +var z10822 [1 << 17]byte +var z10823 [1 << 17]byte +var z10824 [1 << 17]byte +var z10825 [1 << 17]byte +var z10826 [1 << 17]byte +var z10827 [1 << 17]byte +var z10828 [1 << 17]byte +var z10829 [1 << 17]byte +var z10830 [1 << 17]byte +var z10831 [1 << 17]byte +var z10832 [1 << 17]byte +var z10833 [1 << 17]byte +var z10834 [1 << 17]byte +var z10835 [1 << 17]byte +var z10836 [1 << 17]byte +var z10837 [1 << 17]byte +var z10838 [1 << 17]byte +var z10839 [1 << 17]byte +var z10840 [1 << 17]byte +var z10841 [1 << 17]byte +var z10842 [1 << 17]byte +var z10843 [1 << 17]byte +var z10844 [1 << 17]byte +var z10845 [1 << 17]byte +var z10846 [1 << 17]byte +var z10847 [1 << 17]byte +var z10848 [1 << 17]byte +var z10849 [1 << 17]byte +var z10850 [1 << 17]byte +var z10851 [1 << 17]byte +var z10852 [1 << 17]byte +var z10853 [1 << 17]byte +var z10854 [1 << 17]byte +var z10855 [1 << 17]byte +var z10856 [1 << 17]byte +var z10857 [1 << 17]byte +var z10858 [1 << 17]byte +var z10859 [1 << 17]byte +var z10860 [1 << 17]byte +var z10861 [1 << 17]byte +var z10862 [1 << 17]byte +var z10863 [1 << 17]byte +var z10864 [1 << 17]byte +var z10865 [1 << 17]byte +var z10866 [1 << 17]byte +var z10867 [1 << 17]byte +var z10868 [1 << 17]byte +var z10869 [1 << 17]byte +var z10870 [1 << 17]byte +var z10871 [1 << 17]byte +var z10872 [1 << 17]byte +var z10873 [1 << 17]byte +var z10874 [1 << 17]byte +var z10875 [1 << 17]byte +var z10876 [1 << 17]byte +var z10877 [1 << 17]byte +var z10878 [1 << 17]byte +var z10879 [1 << 17]byte +var z10880 [1 << 17]byte +var z10881 [1 << 17]byte +var z10882 [1 << 17]byte +var z10883 [1 << 17]byte +var z10884 [1 << 17]byte +var z10885 [1 << 17]byte +var z10886 [1 << 17]byte +var z10887 [1 << 17]byte +var z10888 [1 << 17]byte +var z10889 [1 << 17]byte +var z10890 [1 << 17]byte +var z10891 [1 << 17]byte +var z10892 [1 << 17]byte +var z10893 [1 << 17]byte +var z10894 [1 << 17]byte +var z10895 [1 << 17]byte +var z10896 [1 << 17]byte +var z10897 [1 << 17]byte +var z10898 [1 << 17]byte +var z10899 [1 << 17]byte +var z10900 [1 << 17]byte +var z10901 [1 << 17]byte +var z10902 [1 << 17]byte +var z10903 [1 << 17]byte +var z10904 [1 << 17]byte +var z10905 [1 << 17]byte +var z10906 [1 << 17]byte +var z10907 [1 << 17]byte +var z10908 [1 << 17]byte +var z10909 [1 << 17]byte +var z10910 [1 << 17]byte +var z10911 [1 << 17]byte +var z10912 [1 << 17]byte +var z10913 [1 << 17]byte +var z10914 [1 << 17]byte +var z10915 [1 << 17]byte +var z10916 [1 << 17]byte +var z10917 [1 << 17]byte +var z10918 [1 << 17]byte +var z10919 [1 << 17]byte +var z10920 [1 << 17]byte +var z10921 [1 << 17]byte +var z10922 [1 << 17]byte +var z10923 [1 << 17]byte +var z10924 [1 << 17]byte +var z10925 [1 << 17]byte +var z10926 [1 << 17]byte +var z10927 [1 << 17]byte +var z10928 [1 << 17]byte +var z10929 [1 << 17]byte +var z10930 [1 << 17]byte +var z10931 [1 << 17]byte +var z10932 [1 << 17]byte +var z10933 [1 << 17]byte +var z10934 [1 << 17]byte +var z10935 [1 << 17]byte +var z10936 [1 << 17]byte +var z10937 [1 << 17]byte +var z10938 [1 << 17]byte +var z10939 [1 << 17]byte +var z10940 [1 << 17]byte +var z10941 [1 << 17]byte +var z10942 [1 << 17]byte +var z10943 [1 << 17]byte +var z10944 [1 << 17]byte +var z10945 [1 << 17]byte +var z10946 [1 << 17]byte +var z10947 [1 << 17]byte +var z10948 [1 << 17]byte +var z10949 [1 << 17]byte +var z10950 [1 << 17]byte +var z10951 [1 << 17]byte +var z10952 [1 << 17]byte +var z10953 [1 << 17]byte +var z10954 [1 << 17]byte +var z10955 [1 << 17]byte +var z10956 [1 << 17]byte +var z10957 [1 << 17]byte +var z10958 [1 << 17]byte +var z10959 [1 << 17]byte +var z10960 [1 << 17]byte +var z10961 [1 << 17]byte +var z10962 [1 << 17]byte +var z10963 [1 << 17]byte +var z10964 [1 << 17]byte +var z10965 [1 << 17]byte +var z10966 [1 << 17]byte +var z10967 [1 << 17]byte +var z10968 [1 << 17]byte +var z10969 [1 << 17]byte +var z10970 [1 << 17]byte +var z10971 [1 << 17]byte +var z10972 [1 << 17]byte +var z10973 [1 << 17]byte +var z10974 [1 << 17]byte +var z10975 [1 << 17]byte +var z10976 [1 << 17]byte +var z10977 [1 << 17]byte +var z10978 [1 << 17]byte +var z10979 [1 << 17]byte +var z10980 [1 << 17]byte +var z10981 [1 << 17]byte +var z10982 [1 << 17]byte +var z10983 [1 << 17]byte +var z10984 [1 << 17]byte +var z10985 [1 << 17]byte +var z10986 [1 << 17]byte +var z10987 [1 << 17]byte +var z10988 [1 << 17]byte +var z10989 [1 << 17]byte +var z10990 [1 << 17]byte +var z10991 [1 << 17]byte +var z10992 [1 << 17]byte +var z10993 [1 << 17]byte +var z10994 [1 << 17]byte +var z10995 [1 << 17]byte +var z10996 [1 << 17]byte +var z10997 [1 << 17]byte +var z10998 [1 << 17]byte +var z10999 [1 << 17]byte +var z11000 [1 << 17]byte +var z11001 [1 << 17]byte +var z11002 [1 << 17]byte +var z11003 [1 << 17]byte +var z11004 [1 << 17]byte +var z11005 [1 << 17]byte +var z11006 [1 << 17]byte +var z11007 [1 << 17]byte +var z11008 [1 << 17]byte +var z11009 [1 << 17]byte +var z11010 [1 << 17]byte +var z11011 [1 << 17]byte +var z11012 [1 << 17]byte +var z11013 [1 << 17]byte +var z11014 [1 << 17]byte +var z11015 [1 << 17]byte +var z11016 [1 << 17]byte +var z11017 [1 << 17]byte +var z11018 [1 << 17]byte +var z11019 [1 << 17]byte +var z11020 [1 << 17]byte +var z11021 [1 << 17]byte +var z11022 [1 << 17]byte +var z11023 [1 << 17]byte +var z11024 [1 << 17]byte +var z11025 [1 << 17]byte +var z11026 [1 << 17]byte +var z11027 [1 << 17]byte +var z11028 [1 << 17]byte +var z11029 [1 << 17]byte +var z11030 [1 << 17]byte +var z11031 [1 << 17]byte +var z11032 [1 << 17]byte +var z11033 [1 << 17]byte +var z11034 [1 << 17]byte +var z11035 [1 << 17]byte +var z11036 [1 << 17]byte +var z11037 [1 << 17]byte +var z11038 [1 << 17]byte +var z11039 [1 << 17]byte +var z11040 [1 << 17]byte +var z11041 [1 << 17]byte +var z11042 [1 << 17]byte +var z11043 [1 << 17]byte +var z11044 [1 << 17]byte +var z11045 [1 << 17]byte +var z11046 [1 << 17]byte +var z11047 [1 << 17]byte +var z11048 [1 << 17]byte +var z11049 [1 << 17]byte +var z11050 [1 << 17]byte +var z11051 [1 << 17]byte +var z11052 [1 << 17]byte +var z11053 [1 << 17]byte +var z11054 [1 << 17]byte +var z11055 [1 << 17]byte +var z11056 [1 << 17]byte +var z11057 [1 << 17]byte +var z11058 [1 << 17]byte +var z11059 [1 << 17]byte +var z11060 [1 << 17]byte +var z11061 [1 << 17]byte +var z11062 [1 << 17]byte +var z11063 [1 << 17]byte +var z11064 [1 << 17]byte +var z11065 [1 << 17]byte +var z11066 [1 << 17]byte +var z11067 [1 << 17]byte +var z11068 [1 << 17]byte +var z11069 [1 << 17]byte +var z11070 [1 << 17]byte +var z11071 [1 << 17]byte +var z11072 [1 << 17]byte +var z11073 [1 << 17]byte +var z11074 [1 << 17]byte +var z11075 [1 << 17]byte +var z11076 [1 << 17]byte +var z11077 [1 << 17]byte +var z11078 [1 << 17]byte +var z11079 [1 << 17]byte +var z11080 [1 << 17]byte +var z11081 [1 << 17]byte +var z11082 [1 << 17]byte +var z11083 [1 << 17]byte +var z11084 [1 << 17]byte +var z11085 [1 << 17]byte +var z11086 [1 << 17]byte +var z11087 [1 << 17]byte +var z11088 [1 << 17]byte +var z11089 [1 << 17]byte +var z11090 [1 << 17]byte +var z11091 [1 << 17]byte +var z11092 [1 << 17]byte +var z11093 [1 << 17]byte +var z11094 [1 << 17]byte +var z11095 [1 << 17]byte +var z11096 [1 << 17]byte +var z11097 [1 << 17]byte +var z11098 [1 << 17]byte +var z11099 [1 << 17]byte +var z11100 [1 << 17]byte +var z11101 [1 << 17]byte +var z11102 [1 << 17]byte +var z11103 [1 << 17]byte +var z11104 [1 << 17]byte +var z11105 [1 << 17]byte +var z11106 [1 << 17]byte +var z11107 [1 << 17]byte +var z11108 [1 << 17]byte +var z11109 [1 << 17]byte +var z11110 [1 << 17]byte +var z11111 [1 << 17]byte +var z11112 [1 << 17]byte +var z11113 [1 << 17]byte +var z11114 [1 << 17]byte +var z11115 [1 << 17]byte +var z11116 [1 << 17]byte +var z11117 [1 << 17]byte +var z11118 [1 << 17]byte +var z11119 [1 << 17]byte +var z11120 [1 << 17]byte +var z11121 [1 << 17]byte +var z11122 [1 << 17]byte +var z11123 [1 << 17]byte +var z11124 [1 << 17]byte +var z11125 [1 << 17]byte +var z11126 [1 << 17]byte +var z11127 [1 << 17]byte +var z11128 [1 << 17]byte +var z11129 [1 << 17]byte +var z11130 [1 << 17]byte +var z11131 [1 << 17]byte +var z11132 [1 << 17]byte +var z11133 [1 << 17]byte +var z11134 [1 << 17]byte +var z11135 [1 << 17]byte +var z11136 [1 << 17]byte +var z11137 [1 << 17]byte +var z11138 [1 << 17]byte +var z11139 [1 << 17]byte +var z11140 [1 << 17]byte +var z11141 [1 << 17]byte +var z11142 [1 << 17]byte +var z11143 [1 << 17]byte +var z11144 [1 << 17]byte +var z11145 [1 << 17]byte +var z11146 [1 << 17]byte +var z11147 [1 << 17]byte +var z11148 [1 << 17]byte +var z11149 [1 << 17]byte +var z11150 [1 << 17]byte +var z11151 [1 << 17]byte +var z11152 [1 << 17]byte +var z11153 [1 << 17]byte +var z11154 [1 << 17]byte +var z11155 [1 << 17]byte +var z11156 [1 << 17]byte +var z11157 [1 << 17]byte +var z11158 [1 << 17]byte +var z11159 [1 << 17]byte +var z11160 [1 << 17]byte +var z11161 [1 << 17]byte +var z11162 [1 << 17]byte +var z11163 [1 << 17]byte +var z11164 [1 << 17]byte +var z11165 [1 << 17]byte +var z11166 [1 << 17]byte +var z11167 [1 << 17]byte +var z11168 [1 << 17]byte +var z11169 [1 << 17]byte +var z11170 [1 << 17]byte +var z11171 [1 << 17]byte +var z11172 [1 << 17]byte +var z11173 [1 << 17]byte +var z11174 [1 << 17]byte +var z11175 [1 << 17]byte +var z11176 [1 << 17]byte +var z11177 [1 << 17]byte +var z11178 [1 << 17]byte +var z11179 [1 << 17]byte +var z11180 [1 << 17]byte +var z11181 [1 << 17]byte +var z11182 [1 << 17]byte +var z11183 [1 << 17]byte +var z11184 [1 << 17]byte +var z11185 [1 << 17]byte +var z11186 [1 << 17]byte +var z11187 [1 << 17]byte +var z11188 [1 << 17]byte +var z11189 [1 << 17]byte +var z11190 [1 << 17]byte +var z11191 [1 << 17]byte +var z11192 [1 << 17]byte +var z11193 [1 << 17]byte +var z11194 [1 << 17]byte +var z11195 [1 << 17]byte +var z11196 [1 << 17]byte +var z11197 [1 << 17]byte +var z11198 [1 << 17]byte +var z11199 [1 << 17]byte +var z11200 [1 << 17]byte +var z11201 [1 << 17]byte +var z11202 [1 << 17]byte +var z11203 [1 << 17]byte +var z11204 [1 << 17]byte +var z11205 [1 << 17]byte +var z11206 [1 << 17]byte +var z11207 [1 << 17]byte +var z11208 [1 << 17]byte +var z11209 [1 << 17]byte +var z11210 [1 << 17]byte +var z11211 [1 << 17]byte +var z11212 [1 << 17]byte +var z11213 [1 << 17]byte +var z11214 [1 << 17]byte +var z11215 [1 << 17]byte +var z11216 [1 << 17]byte +var z11217 [1 << 17]byte +var z11218 [1 << 17]byte +var z11219 [1 << 17]byte +var z11220 [1 << 17]byte +var z11221 [1 << 17]byte +var z11222 [1 << 17]byte +var z11223 [1 << 17]byte +var z11224 [1 << 17]byte +var z11225 [1 << 17]byte +var z11226 [1 << 17]byte +var z11227 [1 << 17]byte +var z11228 [1 << 17]byte +var z11229 [1 << 17]byte +var z11230 [1 << 17]byte +var z11231 [1 << 17]byte +var z11232 [1 << 17]byte +var z11233 [1 << 17]byte +var z11234 [1 << 17]byte +var z11235 [1 << 17]byte +var z11236 [1 << 17]byte +var z11237 [1 << 17]byte +var z11238 [1 << 17]byte +var z11239 [1 << 17]byte +var z11240 [1 << 17]byte +var z11241 [1 << 17]byte +var z11242 [1 << 17]byte +var z11243 [1 << 17]byte +var z11244 [1 << 17]byte +var z11245 [1 << 17]byte +var z11246 [1 << 17]byte +var z11247 [1 << 17]byte +var z11248 [1 << 17]byte +var z11249 [1 << 17]byte +var z11250 [1 << 17]byte +var z11251 [1 << 17]byte +var z11252 [1 << 17]byte +var z11253 [1 << 17]byte +var z11254 [1 << 17]byte +var z11255 [1 << 17]byte +var z11256 [1 << 17]byte +var z11257 [1 << 17]byte +var z11258 [1 << 17]byte +var z11259 [1 << 17]byte +var z11260 [1 << 17]byte +var z11261 [1 << 17]byte +var z11262 [1 << 17]byte +var z11263 [1 << 17]byte +var z11264 [1 << 17]byte +var z11265 [1 << 17]byte +var z11266 [1 << 17]byte +var z11267 [1 << 17]byte +var z11268 [1 << 17]byte +var z11269 [1 << 17]byte +var z11270 [1 << 17]byte +var z11271 [1 << 17]byte +var z11272 [1 << 17]byte +var z11273 [1 << 17]byte +var z11274 [1 << 17]byte +var z11275 [1 << 17]byte +var z11276 [1 << 17]byte +var z11277 [1 << 17]byte +var z11278 [1 << 17]byte +var z11279 [1 << 17]byte +var z11280 [1 << 17]byte +var z11281 [1 << 17]byte +var z11282 [1 << 17]byte +var z11283 [1 << 17]byte +var z11284 [1 << 17]byte +var z11285 [1 << 17]byte +var z11286 [1 << 17]byte +var z11287 [1 << 17]byte +var z11288 [1 << 17]byte +var z11289 [1 << 17]byte +var z11290 [1 << 17]byte +var z11291 [1 << 17]byte +var z11292 [1 << 17]byte +var z11293 [1 << 17]byte +var z11294 [1 << 17]byte +var z11295 [1 << 17]byte +var z11296 [1 << 17]byte +var z11297 [1 << 17]byte +var z11298 [1 << 17]byte +var z11299 [1 << 17]byte +var z11300 [1 << 17]byte +var z11301 [1 << 17]byte +var z11302 [1 << 17]byte +var z11303 [1 << 17]byte +var z11304 [1 << 17]byte +var z11305 [1 << 17]byte +var z11306 [1 << 17]byte +var z11307 [1 << 17]byte +var z11308 [1 << 17]byte +var z11309 [1 << 17]byte +var z11310 [1 << 17]byte +var z11311 [1 << 17]byte +var z11312 [1 << 17]byte +var z11313 [1 << 17]byte +var z11314 [1 << 17]byte +var z11315 [1 << 17]byte +var z11316 [1 << 17]byte +var z11317 [1 << 17]byte +var z11318 [1 << 17]byte +var z11319 [1 << 17]byte +var z11320 [1 << 17]byte +var z11321 [1 << 17]byte +var z11322 [1 << 17]byte +var z11323 [1 << 17]byte +var z11324 [1 << 17]byte +var z11325 [1 << 17]byte +var z11326 [1 << 17]byte +var z11327 [1 << 17]byte +var z11328 [1 << 17]byte +var z11329 [1 << 17]byte +var z11330 [1 << 17]byte +var z11331 [1 << 17]byte +var z11332 [1 << 17]byte +var z11333 [1 << 17]byte +var z11334 [1 << 17]byte +var z11335 [1 << 17]byte +var z11336 [1 << 17]byte +var z11337 [1 << 17]byte +var z11338 [1 << 17]byte +var z11339 [1 << 17]byte +var z11340 [1 << 17]byte +var z11341 [1 << 17]byte +var z11342 [1 << 17]byte +var z11343 [1 << 17]byte +var z11344 [1 << 17]byte +var z11345 [1 << 17]byte +var z11346 [1 << 17]byte +var z11347 [1 << 17]byte +var z11348 [1 << 17]byte +var z11349 [1 << 17]byte +var z11350 [1 << 17]byte +var z11351 [1 << 17]byte +var z11352 [1 << 17]byte +var z11353 [1 << 17]byte +var z11354 [1 << 17]byte +var z11355 [1 << 17]byte +var z11356 [1 << 17]byte +var z11357 [1 << 17]byte +var z11358 [1 << 17]byte +var z11359 [1 << 17]byte +var z11360 [1 << 17]byte +var z11361 [1 << 17]byte +var z11362 [1 << 17]byte +var z11363 [1 << 17]byte +var z11364 [1 << 17]byte +var z11365 [1 << 17]byte +var z11366 [1 << 17]byte +var z11367 [1 << 17]byte +var z11368 [1 << 17]byte +var z11369 [1 << 17]byte +var z11370 [1 << 17]byte +var z11371 [1 << 17]byte +var z11372 [1 << 17]byte +var z11373 [1 << 17]byte +var z11374 [1 << 17]byte +var z11375 [1 << 17]byte +var z11376 [1 << 17]byte +var z11377 [1 << 17]byte +var z11378 [1 << 17]byte +var z11379 [1 << 17]byte +var z11380 [1 << 17]byte +var z11381 [1 << 17]byte +var z11382 [1 << 17]byte +var z11383 [1 << 17]byte +var z11384 [1 << 17]byte +var z11385 [1 << 17]byte +var z11386 [1 << 17]byte +var z11387 [1 << 17]byte +var z11388 [1 << 17]byte +var z11389 [1 << 17]byte +var z11390 [1 << 17]byte +var z11391 [1 << 17]byte +var z11392 [1 << 17]byte +var z11393 [1 << 17]byte +var z11394 [1 << 17]byte +var z11395 [1 << 17]byte +var z11396 [1 << 17]byte +var z11397 [1 << 17]byte +var z11398 [1 << 17]byte +var z11399 [1 << 17]byte +var z11400 [1 << 17]byte +var z11401 [1 << 17]byte +var z11402 [1 << 17]byte +var z11403 [1 << 17]byte +var z11404 [1 << 17]byte +var z11405 [1 << 17]byte +var z11406 [1 << 17]byte +var z11407 [1 << 17]byte +var z11408 [1 << 17]byte +var z11409 [1 << 17]byte +var z11410 [1 << 17]byte +var z11411 [1 << 17]byte +var z11412 [1 << 17]byte +var z11413 [1 << 17]byte +var z11414 [1 << 17]byte +var z11415 [1 << 17]byte +var z11416 [1 << 17]byte +var z11417 [1 << 17]byte +var z11418 [1 << 17]byte +var z11419 [1 << 17]byte +var z11420 [1 << 17]byte +var z11421 [1 << 17]byte +var z11422 [1 << 17]byte +var z11423 [1 << 17]byte +var z11424 [1 << 17]byte +var z11425 [1 << 17]byte +var z11426 [1 << 17]byte +var z11427 [1 << 17]byte +var z11428 [1 << 17]byte +var z11429 [1 << 17]byte +var z11430 [1 << 17]byte +var z11431 [1 << 17]byte +var z11432 [1 << 17]byte +var z11433 [1 << 17]byte +var z11434 [1 << 17]byte +var z11435 [1 << 17]byte +var z11436 [1 << 17]byte +var z11437 [1 << 17]byte +var z11438 [1 << 17]byte +var z11439 [1 << 17]byte +var z11440 [1 << 17]byte +var z11441 [1 << 17]byte +var z11442 [1 << 17]byte +var z11443 [1 << 17]byte +var z11444 [1 << 17]byte +var z11445 [1 << 17]byte +var z11446 [1 << 17]byte +var z11447 [1 << 17]byte +var z11448 [1 << 17]byte +var z11449 [1 << 17]byte +var z11450 [1 << 17]byte +var z11451 [1 << 17]byte +var z11452 [1 << 17]byte +var z11453 [1 << 17]byte +var z11454 [1 << 17]byte +var z11455 [1 << 17]byte +var z11456 [1 << 17]byte +var z11457 [1 << 17]byte +var z11458 [1 << 17]byte +var z11459 [1 << 17]byte +var z11460 [1 << 17]byte +var z11461 [1 << 17]byte +var z11462 [1 << 17]byte +var z11463 [1 << 17]byte +var z11464 [1 << 17]byte +var z11465 [1 << 17]byte +var z11466 [1 << 17]byte +var z11467 [1 << 17]byte +var z11468 [1 << 17]byte +var z11469 [1 << 17]byte +var z11470 [1 << 17]byte +var z11471 [1 << 17]byte +var z11472 [1 << 17]byte +var z11473 [1 << 17]byte +var z11474 [1 << 17]byte +var z11475 [1 << 17]byte +var z11476 [1 << 17]byte +var z11477 [1 << 17]byte +var z11478 [1 << 17]byte +var z11479 [1 << 17]byte +var z11480 [1 << 17]byte +var z11481 [1 << 17]byte +var z11482 [1 << 17]byte +var z11483 [1 << 17]byte +var z11484 [1 << 17]byte +var z11485 [1 << 17]byte +var z11486 [1 << 17]byte +var z11487 [1 << 17]byte +var z11488 [1 << 17]byte +var z11489 [1 << 17]byte +var z11490 [1 << 17]byte +var z11491 [1 << 17]byte +var z11492 [1 << 17]byte +var z11493 [1 << 17]byte +var z11494 [1 << 17]byte +var z11495 [1 << 17]byte +var z11496 [1 << 17]byte +var z11497 [1 << 17]byte +var z11498 [1 << 17]byte +var z11499 [1 << 17]byte +var z11500 [1 << 17]byte +var z11501 [1 << 17]byte +var z11502 [1 << 17]byte +var z11503 [1 << 17]byte +var z11504 [1 << 17]byte +var z11505 [1 << 17]byte +var z11506 [1 << 17]byte +var z11507 [1 << 17]byte +var z11508 [1 << 17]byte +var z11509 [1 << 17]byte +var z11510 [1 << 17]byte +var z11511 [1 << 17]byte +var z11512 [1 << 17]byte +var z11513 [1 << 17]byte +var z11514 [1 << 17]byte +var z11515 [1 << 17]byte +var z11516 [1 << 17]byte +var z11517 [1 << 17]byte +var z11518 [1 << 17]byte +var z11519 [1 << 17]byte +var z11520 [1 << 17]byte +var z11521 [1 << 17]byte +var z11522 [1 << 17]byte +var z11523 [1 << 17]byte +var z11524 [1 << 17]byte +var z11525 [1 << 17]byte +var z11526 [1 << 17]byte +var z11527 [1 << 17]byte +var z11528 [1 << 17]byte +var z11529 [1 << 17]byte +var z11530 [1 << 17]byte +var z11531 [1 << 17]byte +var z11532 [1 << 17]byte +var z11533 [1 << 17]byte +var z11534 [1 << 17]byte +var z11535 [1 << 17]byte +var z11536 [1 << 17]byte +var z11537 [1 << 17]byte +var z11538 [1 << 17]byte +var z11539 [1 << 17]byte +var z11540 [1 << 17]byte +var z11541 [1 << 17]byte +var z11542 [1 << 17]byte +var z11543 [1 << 17]byte +var z11544 [1 << 17]byte +var z11545 [1 << 17]byte +var z11546 [1 << 17]byte +var z11547 [1 << 17]byte +var z11548 [1 << 17]byte +var z11549 [1 << 17]byte +var z11550 [1 << 17]byte +var z11551 [1 << 17]byte +var z11552 [1 << 17]byte +var z11553 [1 << 17]byte +var z11554 [1 << 17]byte +var z11555 [1 << 17]byte +var z11556 [1 << 17]byte +var z11557 [1 << 17]byte +var z11558 [1 << 17]byte +var z11559 [1 << 17]byte +var z11560 [1 << 17]byte +var z11561 [1 << 17]byte +var z11562 [1 << 17]byte +var z11563 [1 << 17]byte +var z11564 [1 << 17]byte +var z11565 [1 << 17]byte +var z11566 [1 << 17]byte +var z11567 [1 << 17]byte +var z11568 [1 << 17]byte +var z11569 [1 << 17]byte +var z11570 [1 << 17]byte +var z11571 [1 << 17]byte +var z11572 [1 << 17]byte +var z11573 [1 << 17]byte +var z11574 [1 << 17]byte +var z11575 [1 << 17]byte +var z11576 [1 << 17]byte +var z11577 [1 << 17]byte +var z11578 [1 << 17]byte +var z11579 [1 << 17]byte +var z11580 [1 << 17]byte +var z11581 [1 << 17]byte +var z11582 [1 << 17]byte +var z11583 [1 << 17]byte +var z11584 [1 << 17]byte +var z11585 [1 << 17]byte +var z11586 [1 << 17]byte +var z11587 [1 << 17]byte +var z11588 [1 << 17]byte +var z11589 [1 << 17]byte +var z11590 [1 << 17]byte +var z11591 [1 << 17]byte +var z11592 [1 << 17]byte +var z11593 [1 << 17]byte +var z11594 [1 << 17]byte +var z11595 [1 << 17]byte +var z11596 [1 << 17]byte +var z11597 [1 << 17]byte +var z11598 [1 << 17]byte +var z11599 [1 << 17]byte +var z11600 [1 << 17]byte +var z11601 [1 << 17]byte +var z11602 [1 << 17]byte +var z11603 [1 << 17]byte +var z11604 [1 << 17]byte +var z11605 [1 << 17]byte +var z11606 [1 << 17]byte +var z11607 [1 << 17]byte +var z11608 [1 << 17]byte +var z11609 [1 << 17]byte +var z11610 [1 << 17]byte +var z11611 [1 << 17]byte +var z11612 [1 << 17]byte +var z11613 [1 << 17]byte +var z11614 [1 << 17]byte +var z11615 [1 << 17]byte +var z11616 [1 << 17]byte +var z11617 [1 << 17]byte +var z11618 [1 << 17]byte +var z11619 [1 << 17]byte +var z11620 [1 << 17]byte +var z11621 [1 << 17]byte +var z11622 [1 << 17]byte +var z11623 [1 << 17]byte +var z11624 [1 << 17]byte +var z11625 [1 << 17]byte +var z11626 [1 << 17]byte +var z11627 [1 << 17]byte +var z11628 [1 << 17]byte +var z11629 [1 << 17]byte +var z11630 [1 << 17]byte +var z11631 [1 << 17]byte +var z11632 [1 << 17]byte +var z11633 [1 << 17]byte +var z11634 [1 << 17]byte +var z11635 [1 << 17]byte +var z11636 [1 << 17]byte +var z11637 [1 << 17]byte +var z11638 [1 << 17]byte +var z11639 [1 << 17]byte +var z11640 [1 << 17]byte +var z11641 [1 << 17]byte +var z11642 [1 << 17]byte +var z11643 [1 << 17]byte +var z11644 [1 << 17]byte +var z11645 [1 << 17]byte +var z11646 [1 << 17]byte +var z11647 [1 << 17]byte +var z11648 [1 << 17]byte +var z11649 [1 << 17]byte +var z11650 [1 << 17]byte +var z11651 [1 << 17]byte +var z11652 [1 << 17]byte +var z11653 [1 << 17]byte +var z11654 [1 << 17]byte +var z11655 [1 << 17]byte +var z11656 [1 << 17]byte +var z11657 [1 << 17]byte +var z11658 [1 << 17]byte +var z11659 [1 << 17]byte +var z11660 [1 << 17]byte +var z11661 [1 << 17]byte +var z11662 [1 << 17]byte +var z11663 [1 << 17]byte +var z11664 [1 << 17]byte +var z11665 [1 << 17]byte +var z11666 [1 << 17]byte +var z11667 [1 << 17]byte +var z11668 [1 << 17]byte +var z11669 [1 << 17]byte +var z11670 [1 << 17]byte +var z11671 [1 << 17]byte +var z11672 [1 << 17]byte +var z11673 [1 << 17]byte +var z11674 [1 << 17]byte +var z11675 [1 << 17]byte +var z11676 [1 << 17]byte +var z11677 [1 << 17]byte +var z11678 [1 << 17]byte +var z11679 [1 << 17]byte +var z11680 [1 << 17]byte +var z11681 [1 << 17]byte +var z11682 [1 << 17]byte +var z11683 [1 << 17]byte +var z11684 [1 << 17]byte +var z11685 [1 << 17]byte +var z11686 [1 << 17]byte +var z11687 [1 << 17]byte +var z11688 [1 << 17]byte +var z11689 [1 << 17]byte +var z11690 [1 << 17]byte +var z11691 [1 << 17]byte +var z11692 [1 << 17]byte +var z11693 [1 << 17]byte +var z11694 [1 << 17]byte +var z11695 [1 << 17]byte +var z11696 [1 << 17]byte +var z11697 [1 << 17]byte +var z11698 [1 << 17]byte +var z11699 [1 << 17]byte +var z11700 [1 << 17]byte +var z11701 [1 << 17]byte +var z11702 [1 << 17]byte +var z11703 [1 << 17]byte +var z11704 [1 << 17]byte +var z11705 [1 << 17]byte +var z11706 [1 << 17]byte +var z11707 [1 << 17]byte +var z11708 [1 << 17]byte +var z11709 [1 << 17]byte +var z11710 [1 << 17]byte +var z11711 [1 << 17]byte +var z11712 [1 << 17]byte +var z11713 [1 << 17]byte +var z11714 [1 << 17]byte +var z11715 [1 << 17]byte +var z11716 [1 << 17]byte +var z11717 [1 << 17]byte +var z11718 [1 << 17]byte +var z11719 [1 << 17]byte +var z11720 [1 << 17]byte +var z11721 [1 << 17]byte +var z11722 [1 << 17]byte +var z11723 [1 << 17]byte +var z11724 [1 << 17]byte +var z11725 [1 << 17]byte +var z11726 [1 << 17]byte +var z11727 [1 << 17]byte +var z11728 [1 << 17]byte +var z11729 [1 << 17]byte +var z11730 [1 << 17]byte +var z11731 [1 << 17]byte +var z11732 [1 << 17]byte +var z11733 [1 << 17]byte +var z11734 [1 << 17]byte +var z11735 [1 << 17]byte +var z11736 [1 << 17]byte +var z11737 [1 << 17]byte +var z11738 [1 << 17]byte +var z11739 [1 << 17]byte +var z11740 [1 << 17]byte +var z11741 [1 << 17]byte +var z11742 [1 << 17]byte +var z11743 [1 << 17]byte +var z11744 [1 << 17]byte +var z11745 [1 << 17]byte +var z11746 [1 << 17]byte +var z11747 [1 << 17]byte +var z11748 [1 << 17]byte +var z11749 [1 << 17]byte +var z11750 [1 << 17]byte +var z11751 [1 << 17]byte +var z11752 [1 << 17]byte +var z11753 [1 << 17]byte +var z11754 [1 << 17]byte +var z11755 [1 << 17]byte +var z11756 [1 << 17]byte +var z11757 [1 << 17]byte +var z11758 [1 << 17]byte +var z11759 [1 << 17]byte +var z11760 [1 << 17]byte +var z11761 [1 << 17]byte +var z11762 [1 << 17]byte +var z11763 [1 << 17]byte +var z11764 [1 << 17]byte +var z11765 [1 << 17]byte +var z11766 [1 << 17]byte +var z11767 [1 << 17]byte +var z11768 [1 << 17]byte +var z11769 [1 << 17]byte +var z11770 [1 << 17]byte +var z11771 [1 << 17]byte +var z11772 [1 << 17]byte +var z11773 [1 << 17]byte +var z11774 [1 << 17]byte +var z11775 [1 << 17]byte +var z11776 [1 << 17]byte +var z11777 [1 << 17]byte +var z11778 [1 << 17]byte +var z11779 [1 << 17]byte +var z11780 [1 << 17]byte +var z11781 [1 << 17]byte +var z11782 [1 << 17]byte +var z11783 [1 << 17]byte +var z11784 [1 << 17]byte +var z11785 [1 << 17]byte +var z11786 [1 << 17]byte +var z11787 [1 << 17]byte +var z11788 [1 << 17]byte +var z11789 [1 << 17]byte +var z11790 [1 << 17]byte +var z11791 [1 << 17]byte +var z11792 [1 << 17]byte +var z11793 [1 << 17]byte +var z11794 [1 << 17]byte +var z11795 [1 << 17]byte +var z11796 [1 << 17]byte +var z11797 [1 << 17]byte +var z11798 [1 << 17]byte +var z11799 [1 << 17]byte +var z11800 [1 << 17]byte +var z11801 [1 << 17]byte +var z11802 [1 << 17]byte +var z11803 [1 << 17]byte +var z11804 [1 << 17]byte +var z11805 [1 << 17]byte +var z11806 [1 << 17]byte +var z11807 [1 << 17]byte +var z11808 [1 << 17]byte +var z11809 [1 << 17]byte +var z11810 [1 << 17]byte +var z11811 [1 << 17]byte +var z11812 [1 << 17]byte +var z11813 [1 << 17]byte +var z11814 [1 << 17]byte +var z11815 [1 << 17]byte +var z11816 [1 << 17]byte +var z11817 [1 << 17]byte +var z11818 [1 << 17]byte +var z11819 [1 << 17]byte +var z11820 [1 << 17]byte +var z11821 [1 << 17]byte +var z11822 [1 << 17]byte +var z11823 [1 << 17]byte +var z11824 [1 << 17]byte +var z11825 [1 << 17]byte +var z11826 [1 << 17]byte +var z11827 [1 << 17]byte +var z11828 [1 << 17]byte +var z11829 [1 << 17]byte +var z11830 [1 << 17]byte +var z11831 [1 << 17]byte +var z11832 [1 << 17]byte +var z11833 [1 << 17]byte +var z11834 [1 << 17]byte +var z11835 [1 << 17]byte +var z11836 [1 << 17]byte +var z11837 [1 << 17]byte +var z11838 [1 << 17]byte +var z11839 [1 << 17]byte +var z11840 [1 << 17]byte +var z11841 [1 << 17]byte +var z11842 [1 << 17]byte +var z11843 [1 << 17]byte +var z11844 [1 << 17]byte +var z11845 [1 << 17]byte +var z11846 [1 << 17]byte +var z11847 [1 << 17]byte +var z11848 [1 << 17]byte +var z11849 [1 << 17]byte +var z11850 [1 << 17]byte +var z11851 [1 << 17]byte +var z11852 [1 << 17]byte +var z11853 [1 << 17]byte +var z11854 [1 << 17]byte +var z11855 [1 << 17]byte +var z11856 [1 << 17]byte +var z11857 [1 << 17]byte +var z11858 [1 << 17]byte +var z11859 [1 << 17]byte +var z11860 [1 << 17]byte +var z11861 [1 << 17]byte +var z11862 [1 << 17]byte +var z11863 [1 << 17]byte +var z11864 [1 << 17]byte +var z11865 [1 << 17]byte +var z11866 [1 << 17]byte +var z11867 [1 << 17]byte +var z11868 [1 << 17]byte +var z11869 [1 << 17]byte +var z11870 [1 << 17]byte +var z11871 [1 << 17]byte +var z11872 [1 << 17]byte +var z11873 [1 << 17]byte +var z11874 [1 << 17]byte +var z11875 [1 << 17]byte +var z11876 [1 << 17]byte +var z11877 [1 << 17]byte +var z11878 [1 << 17]byte +var z11879 [1 << 17]byte +var z11880 [1 << 17]byte +var z11881 [1 << 17]byte +var z11882 [1 << 17]byte +var z11883 [1 << 17]byte +var z11884 [1 << 17]byte +var z11885 [1 << 17]byte +var z11886 [1 << 17]byte +var z11887 [1 << 17]byte +var z11888 [1 << 17]byte +var z11889 [1 << 17]byte +var z11890 [1 << 17]byte +var z11891 [1 << 17]byte +var z11892 [1 << 17]byte +var z11893 [1 << 17]byte +var z11894 [1 << 17]byte +var z11895 [1 << 17]byte +var z11896 [1 << 17]byte +var z11897 [1 << 17]byte +var z11898 [1 << 17]byte +var z11899 [1 << 17]byte +var z11900 [1 << 17]byte +var z11901 [1 << 17]byte +var z11902 [1 << 17]byte +var z11903 [1 << 17]byte +var z11904 [1 << 17]byte +var z11905 [1 << 17]byte +var z11906 [1 << 17]byte +var z11907 [1 << 17]byte +var z11908 [1 << 17]byte +var z11909 [1 << 17]byte +var z11910 [1 << 17]byte +var z11911 [1 << 17]byte +var z11912 [1 << 17]byte +var z11913 [1 << 17]byte +var z11914 [1 << 17]byte +var z11915 [1 << 17]byte +var z11916 [1 << 17]byte +var z11917 [1 << 17]byte +var z11918 [1 << 17]byte +var z11919 [1 << 17]byte +var z11920 [1 << 17]byte +var z11921 [1 << 17]byte +var z11922 [1 << 17]byte +var z11923 [1 << 17]byte +var z11924 [1 << 17]byte +var z11925 [1 << 17]byte +var z11926 [1 << 17]byte +var z11927 [1 << 17]byte +var z11928 [1 << 17]byte +var z11929 [1 << 17]byte +var z11930 [1 << 17]byte +var z11931 [1 << 17]byte +var z11932 [1 << 17]byte +var z11933 [1 << 17]byte +var z11934 [1 << 17]byte +var z11935 [1 << 17]byte +var z11936 [1 << 17]byte +var z11937 [1 << 17]byte +var z11938 [1 << 17]byte +var z11939 [1 << 17]byte +var z11940 [1 << 17]byte +var z11941 [1 << 17]byte +var z11942 [1 << 17]byte +var z11943 [1 << 17]byte +var z11944 [1 << 17]byte +var z11945 [1 << 17]byte +var z11946 [1 << 17]byte +var z11947 [1 << 17]byte +var z11948 [1 << 17]byte +var z11949 [1 << 17]byte +var z11950 [1 << 17]byte +var z11951 [1 << 17]byte +var z11952 [1 << 17]byte +var z11953 [1 << 17]byte +var z11954 [1 << 17]byte +var z11955 [1 << 17]byte +var z11956 [1 << 17]byte +var z11957 [1 << 17]byte +var z11958 [1 << 17]byte +var z11959 [1 << 17]byte +var z11960 [1 << 17]byte +var z11961 [1 << 17]byte +var z11962 [1 << 17]byte +var z11963 [1 << 17]byte +var z11964 [1 << 17]byte +var z11965 [1 << 17]byte +var z11966 [1 << 17]byte +var z11967 [1 << 17]byte +var z11968 [1 << 17]byte +var z11969 [1 << 17]byte +var z11970 [1 << 17]byte +var z11971 [1 << 17]byte +var z11972 [1 << 17]byte +var z11973 [1 << 17]byte +var z11974 [1 << 17]byte +var z11975 [1 << 17]byte +var z11976 [1 << 17]byte +var z11977 [1 << 17]byte +var z11978 [1 << 17]byte +var z11979 [1 << 17]byte +var z11980 [1 << 17]byte +var z11981 [1 << 17]byte +var z11982 [1 << 17]byte +var z11983 [1 << 17]byte +var z11984 [1 << 17]byte +var z11985 [1 << 17]byte +var z11986 [1 << 17]byte +var z11987 [1 << 17]byte +var z11988 [1 << 17]byte +var z11989 [1 << 17]byte +var z11990 [1 << 17]byte +var z11991 [1 << 17]byte +var z11992 [1 << 17]byte +var z11993 [1 << 17]byte +var z11994 [1 << 17]byte +var z11995 [1 << 17]byte +var z11996 [1 << 17]byte +var z11997 [1 << 17]byte +var z11998 [1 << 17]byte +var z11999 [1 << 17]byte +var z12000 [1 << 17]byte +var z12001 [1 << 17]byte +var z12002 [1 << 17]byte +var z12003 [1 << 17]byte +var z12004 [1 << 17]byte +var z12005 [1 << 17]byte +var z12006 [1 << 17]byte +var z12007 [1 << 17]byte +var z12008 [1 << 17]byte +var z12009 [1 << 17]byte +var z12010 [1 << 17]byte +var z12011 [1 << 17]byte +var z12012 [1 << 17]byte +var z12013 [1 << 17]byte +var z12014 [1 << 17]byte +var z12015 [1 << 17]byte +var z12016 [1 << 17]byte +var z12017 [1 << 17]byte +var z12018 [1 << 17]byte +var z12019 [1 << 17]byte +var z12020 [1 << 17]byte +var z12021 [1 << 17]byte +var z12022 [1 << 17]byte +var z12023 [1 << 17]byte +var z12024 [1 << 17]byte +var z12025 [1 << 17]byte +var z12026 [1 << 17]byte +var z12027 [1 << 17]byte +var z12028 [1 << 17]byte +var z12029 [1 << 17]byte +var z12030 [1 << 17]byte +var z12031 [1 << 17]byte +var z12032 [1 << 17]byte +var z12033 [1 << 17]byte +var z12034 [1 << 17]byte +var z12035 [1 << 17]byte +var z12036 [1 << 17]byte +var z12037 [1 << 17]byte +var z12038 [1 << 17]byte +var z12039 [1 << 17]byte +var z12040 [1 << 17]byte +var z12041 [1 << 17]byte +var z12042 [1 << 17]byte +var z12043 [1 << 17]byte +var z12044 [1 << 17]byte +var z12045 [1 << 17]byte +var z12046 [1 << 17]byte +var z12047 [1 << 17]byte +var z12048 [1 << 17]byte +var z12049 [1 << 17]byte +var z12050 [1 << 17]byte +var z12051 [1 << 17]byte +var z12052 [1 << 17]byte +var z12053 [1 << 17]byte +var z12054 [1 << 17]byte +var z12055 [1 << 17]byte +var z12056 [1 << 17]byte +var z12057 [1 << 17]byte +var z12058 [1 << 17]byte +var z12059 [1 << 17]byte +var z12060 [1 << 17]byte +var z12061 [1 << 17]byte +var z12062 [1 << 17]byte +var z12063 [1 << 17]byte +var z12064 [1 << 17]byte +var z12065 [1 << 17]byte +var z12066 [1 << 17]byte +var z12067 [1 << 17]byte +var z12068 [1 << 17]byte +var z12069 [1 << 17]byte +var z12070 [1 << 17]byte +var z12071 [1 << 17]byte +var z12072 [1 << 17]byte +var z12073 [1 << 17]byte +var z12074 [1 << 17]byte +var z12075 [1 << 17]byte +var z12076 [1 << 17]byte +var z12077 [1 << 17]byte +var z12078 [1 << 17]byte +var z12079 [1 << 17]byte +var z12080 [1 << 17]byte +var z12081 [1 << 17]byte +var z12082 [1 << 17]byte +var z12083 [1 << 17]byte +var z12084 [1 << 17]byte +var z12085 [1 << 17]byte +var z12086 [1 << 17]byte +var z12087 [1 << 17]byte +var z12088 [1 << 17]byte +var z12089 [1 << 17]byte +var z12090 [1 << 17]byte +var z12091 [1 << 17]byte +var z12092 [1 << 17]byte +var z12093 [1 << 17]byte +var z12094 [1 << 17]byte +var z12095 [1 << 17]byte +var z12096 [1 << 17]byte +var z12097 [1 << 17]byte +var z12098 [1 << 17]byte +var z12099 [1 << 17]byte +var z12100 [1 << 17]byte +var z12101 [1 << 17]byte +var z12102 [1 << 17]byte +var z12103 [1 << 17]byte +var z12104 [1 << 17]byte +var z12105 [1 << 17]byte +var z12106 [1 << 17]byte +var z12107 [1 << 17]byte +var z12108 [1 << 17]byte +var z12109 [1 << 17]byte +var z12110 [1 << 17]byte +var z12111 [1 << 17]byte +var z12112 [1 << 17]byte +var z12113 [1 << 17]byte +var z12114 [1 << 17]byte +var z12115 [1 << 17]byte +var z12116 [1 << 17]byte +var z12117 [1 << 17]byte +var z12118 [1 << 17]byte +var z12119 [1 << 17]byte +var z12120 [1 << 17]byte +var z12121 [1 << 17]byte +var z12122 [1 << 17]byte +var z12123 [1 << 17]byte +var z12124 [1 << 17]byte +var z12125 [1 << 17]byte +var z12126 [1 << 17]byte +var z12127 [1 << 17]byte +var z12128 [1 << 17]byte +var z12129 [1 << 17]byte +var z12130 [1 << 17]byte +var z12131 [1 << 17]byte +var z12132 [1 << 17]byte +var z12133 [1 << 17]byte +var z12134 [1 << 17]byte +var z12135 [1 << 17]byte +var z12136 [1 << 17]byte +var z12137 [1 << 17]byte +var z12138 [1 << 17]byte +var z12139 [1 << 17]byte +var z12140 [1 << 17]byte +var z12141 [1 << 17]byte +var z12142 [1 << 17]byte +var z12143 [1 << 17]byte +var z12144 [1 << 17]byte +var z12145 [1 << 17]byte +var z12146 [1 << 17]byte +var z12147 [1 << 17]byte +var z12148 [1 << 17]byte +var z12149 [1 << 17]byte +var z12150 [1 << 17]byte +var z12151 [1 << 17]byte +var z12152 [1 << 17]byte +var z12153 [1 << 17]byte +var z12154 [1 << 17]byte +var z12155 [1 << 17]byte +var z12156 [1 << 17]byte +var z12157 [1 << 17]byte +var z12158 [1 << 17]byte +var z12159 [1 << 17]byte +var z12160 [1 << 17]byte +var z12161 [1 << 17]byte +var z12162 [1 << 17]byte +var z12163 [1 << 17]byte +var z12164 [1 << 17]byte +var z12165 [1 << 17]byte +var z12166 [1 << 17]byte +var z12167 [1 << 17]byte +var z12168 [1 << 17]byte +var z12169 [1 << 17]byte +var z12170 [1 << 17]byte +var z12171 [1 << 17]byte +var z12172 [1 << 17]byte +var z12173 [1 << 17]byte +var z12174 [1 << 17]byte +var z12175 [1 << 17]byte +var z12176 [1 << 17]byte +var z12177 [1 << 17]byte +var z12178 [1 << 17]byte +var z12179 [1 << 17]byte +var z12180 [1 << 17]byte +var z12181 [1 << 17]byte +var z12182 [1 << 17]byte +var z12183 [1 << 17]byte +var z12184 [1 << 17]byte +var z12185 [1 << 17]byte +var z12186 [1 << 17]byte +var z12187 [1 << 17]byte +var z12188 [1 << 17]byte +var z12189 [1 << 17]byte +var z12190 [1 << 17]byte +var z12191 [1 << 17]byte +var z12192 [1 << 17]byte +var z12193 [1 << 17]byte +var z12194 [1 << 17]byte +var z12195 [1 << 17]byte +var z12196 [1 << 17]byte +var z12197 [1 << 17]byte +var z12198 [1 << 17]byte +var z12199 [1 << 17]byte +var z12200 [1 << 17]byte +var z12201 [1 << 17]byte +var z12202 [1 << 17]byte +var z12203 [1 << 17]byte +var z12204 [1 << 17]byte +var z12205 [1 << 17]byte +var z12206 [1 << 17]byte +var z12207 [1 << 17]byte +var z12208 [1 << 17]byte +var z12209 [1 << 17]byte +var z12210 [1 << 17]byte +var z12211 [1 << 17]byte +var z12212 [1 << 17]byte +var z12213 [1 << 17]byte +var z12214 [1 << 17]byte +var z12215 [1 << 17]byte +var z12216 [1 << 17]byte +var z12217 [1 << 17]byte +var z12218 [1 << 17]byte +var z12219 [1 << 17]byte +var z12220 [1 << 17]byte +var z12221 [1 << 17]byte +var z12222 [1 << 17]byte +var z12223 [1 << 17]byte +var z12224 [1 << 17]byte +var z12225 [1 << 17]byte +var z12226 [1 << 17]byte +var z12227 [1 << 17]byte +var z12228 [1 << 17]byte +var z12229 [1 << 17]byte +var z12230 [1 << 17]byte +var z12231 [1 << 17]byte +var z12232 [1 << 17]byte +var z12233 [1 << 17]byte +var z12234 [1 << 17]byte +var z12235 [1 << 17]byte +var z12236 [1 << 17]byte +var z12237 [1 << 17]byte +var z12238 [1 << 17]byte +var z12239 [1 << 17]byte +var z12240 [1 << 17]byte +var z12241 [1 << 17]byte +var z12242 [1 << 17]byte +var z12243 [1 << 17]byte +var z12244 [1 << 17]byte +var z12245 [1 << 17]byte +var z12246 [1 << 17]byte +var z12247 [1 << 17]byte +var z12248 [1 << 17]byte +var z12249 [1 << 17]byte +var z12250 [1 << 17]byte +var z12251 [1 << 17]byte +var z12252 [1 << 17]byte +var z12253 [1 << 17]byte +var z12254 [1 << 17]byte +var z12255 [1 << 17]byte +var z12256 [1 << 17]byte +var z12257 [1 << 17]byte +var z12258 [1 << 17]byte +var z12259 [1 << 17]byte +var z12260 [1 << 17]byte +var z12261 [1 << 17]byte +var z12262 [1 << 17]byte +var z12263 [1 << 17]byte +var z12264 [1 << 17]byte +var z12265 [1 << 17]byte +var z12266 [1 << 17]byte +var z12267 [1 << 17]byte +var z12268 [1 << 17]byte +var z12269 [1 << 17]byte +var z12270 [1 << 17]byte +var z12271 [1 << 17]byte +var z12272 [1 << 17]byte +var z12273 [1 << 17]byte +var z12274 [1 << 17]byte +var z12275 [1 << 17]byte +var z12276 [1 << 17]byte +var z12277 [1 << 17]byte +var z12278 [1 << 17]byte +var z12279 [1 << 17]byte +var z12280 [1 << 17]byte +var z12281 [1 << 17]byte +var z12282 [1 << 17]byte +var z12283 [1 << 17]byte +var z12284 [1 << 17]byte +var z12285 [1 << 17]byte +var z12286 [1 << 17]byte +var z12287 [1 << 17]byte +var z12288 [1 << 17]byte +var z12289 [1 << 17]byte +var z12290 [1 << 17]byte +var z12291 [1 << 17]byte +var z12292 [1 << 17]byte +var z12293 [1 << 17]byte +var z12294 [1 << 17]byte +var z12295 [1 << 17]byte +var z12296 [1 << 17]byte +var z12297 [1 << 17]byte +var z12298 [1 << 17]byte +var z12299 [1 << 17]byte +var z12300 [1 << 17]byte +var z12301 [1 << 17]byte +var z12302 [1 << 17]byte +var z12303 [1 << 17]byte +var z12304 [1 << 17]byte +var z12305 [1 << 17]byte +var z12306 [1 << 17]byte +var z12307 [1 << 17]byte +var z12308 [1 << 17]byte +var z12309 [1 << 17]byte +var z12310 [1 << 17]byte +var z12311 [1 << 17]byte +var z12312 [1 << 17]byte +var z12313 [1 << 17]byte +var z12314 [1 << 17]byte +var z12315 [1 << 17]byte +var z12316 [1 << 17]byte +var z12317 [1 << 17]byte +var z12318 [1 << 17]byte +var z12319 [1 << 17]byte +var z12320 [1 << 17]byte +var z12321 [1 << 17]byte +var z12322 [1 << 17]byte +var z12323 [1 << 17]byte +var z12324 [1 << 17]byte +var z12325 [1 << 17]byte +var z12326 [1 << 17]byte +var z12327 [1 << 17]byte +var z12328 [1 << 17]byte +var z12329 [1 << 17]byte +var z12330 [1 << 17]byte +var z12331 [1 << 17]byte +var z12332 [1 << 17]byte +var z12333 [1 << 17]byte +var z12334 [1 << 17]byte +var z12335 [1 << 17]byte +var z12336 [1 << 17]byte +var z12337 [1 << 17]byte +var z12338 [1 << 17]byte +var z12339 [1 << 17]byte +var z12340 [1 << 17]byte +var z12341 [1 << 17]byte +var z12342 [1 << 17]byte +var z12343 [1 << 17]byte +var z12344 [1 << 17]byte +var z12345 [1 << 17]byte +var z12346 [1 << 17]byte +var z12347 [1 << 17]byte +var z12348 [1 << 17]byte +var z12349 [1 << 17]byte +var z12350 [1 << 17]byte +var z12351 [1 << 17]byte +var z12352 [1 << 17]byte +var z12353 [1 << 17]byte +var z12354 [1 << 17]byte +var z12355 [1 << 17]byte +var z12356 [1 << 17]byte +var z12357 [1 << 17]byte +var z12358 [1 << 17]byte +var z12359 [1 << 17]byte +var z12360 [1 << 17]byte +var z12361 [1 << 17]byte +var z12362 [1 << 17]byte +var z12363 [1 << 17]byte +var z12364 [1 << 17]byte +var z12365 [1 << 17]byte +var z12366 [1 << 17]byte +var z12367 [1 << 17]byte +var z12368 [1 << 17]byte +var z12369 [1 << 17]byte +var z12370 [1 << 17]byte +var z12371 [1 << 17]byte +var z12372 [1 << 17]byte +var z12373 [1 << 17]byte +var z12374 [1 << 17]byte +var z12375 [1 << 17]byte +var z12376 [1 << 17]byte +var z12377 [1 << 17]byte +var z12378 [1 << 17]byte +var z12379 [1 << 17]byte +var z12380 [1 << 17]byte +var z12381 [1 << 17]byte +var z12382 [1 << 17]byte +var z12383 [1 << 17]byte +var z12384 [1 << 17]byte +var z12385 [1 << 17]byte +var z12386 [1 << 17]byte +var z12387 [1 << 17]byte +var z12388 [1 << 17]byte +var z12389 [1 << 17]byte +var z12390 [1 << 17]byte +var z12391 [1 << 17]byte +var z12392 [1 << 17]byte +var z12393 [1 << 17]byte +var z12394 [1 << 17]byte +var z12395 [1 << 17]byte +var z12396 [1 << 17]byte +var z12397 [1 << 17]byte +var z12398 [1 << 17]byte +var z12399 [1 << 17]byte +var z12400 [1 << 17]byte +var z12401 [1 << 17]byte +var z12402 [1 << 17]byte +var z12403 [1 << 17]byte +var z12404 [1 << 17]byte +var z12405 [1 << 17]byte +var z12406 [1 << 17]byte +var z12407 [1 << 17]byte +var z12408 [1 << 17]byte +var z12409 [1 << 17]byte +var z12410 [1 << 17]byte +var z12411 [1 << 17]byte +var z12412 [1 << 17]byte +var z12413 [1 << 17]byte +var z12414 [1 << 17]byte +var z12415 [1 << 17]byte +var z12416 [1 << 17]byte +var z12417 [1 << 17]byte +var z12418 [1 << 17]byte +var z12419 [1 << 17]byte +var z12420 [1 << 17]byte +var z12421 [1 << 17]byte +var z12422 [1 << 17]byte +var z12423 [1 << 17]byte +var z12424 [1 << 17]byte +var z12425 [1 << 17]byte +var z12426 [1 << 17]byte +var z12427 [1 << 17]byte +var z12428 [1 << 17]byte +var z12429 [1 << 17]byte +var z12430 [1 << 17]byte +var z12431 [1 << 17]byte +var z12432 [1 << 17]byte +var z12433 [1 << 17]byte +var z12434 [1 << 17]byte +var z12435 [1 << 17]byte +var z12436 [1 << 17]byte +var z12437 [1 << 17]byte +var z12438 [1 << 17]byte +var z12439 [1 << 17]byte +var z12440 [1 << 17]byte +var z12441 [1 << 17]byte +var z12442 [1 << 17]byte +var z12443 [1 << 17]byte +var z12444 [1 << 17]byte +var z12445 [1 << 17]byte +var z12446 [1 << 17]byte +var z12447 [1 << 17]byte +var z12448 [1 << 17]byte +var z12449 [1 << 17]byte +var z12450 [1 << 17]byte +var z12451 [1 << 17]byte +var z12452 [1 << 17]byte +var z12453 [1 << 17]byte +var z12454 [1 << 17]byte +var z12455 [1 << 17]byte +var z12456 [1 << 17]byte +var z12457 [1 << 17]byte +var z12458 [1 << 17]byte +var z12459 [1 << 17]byte +var z12460 [1 << 17]byte +var z12461 [1 << 17]byte +var z12462 [1 << 17]byte +var z12463 [1 << 17]byte +var z12464 [1 << 17]byte +var z12465 [1 << 17]byte +var z12466 [1 << 17]byte +var z12467 [1 << 17]byte +var z12468 [1 << 17]byte +var z12469 [1 << 17]byte +var z12470 [1 << 17]byte +var z12471 [1 << 17]byte +var z12472 [1 << 17]byte +var z12473 [1 << 17]byte +var z12474 [1 << 17]byte +var z12475 [1 << 17]byte +var z12476 [1 << 17]byte +var z12477 [1 << 17]byte +var z12478 [1 << 17]byte +var z12479 [1 << 17]byte +var z12480 [1 << 17]byte +var z12481 [1 << 17]byte +var z12482 [1 << 17]byte +var z12483 [1 << 17]byte +var z12484 [1 << 17]byte +var z12485 [1 << 17]byte +var z12486 [1 << 17]byte +var z12487 [1 << 17]byte +var z12488 [1 << 17]byte +var z12489 [1 << 17]byte +var z12490 [1 << 17]byte +var z12491 [1 << 17]byte +var z12492 [1 << 17]byte +var z12493 [1 << 17]byte +var z12494 [1 << 17]byte +var z12495 [1 << 17]byte +var z12496 [1 << 17]byte +var z12497 [1 << 17]byte +var z12498 [1 << 17]byte +var z12499 [1 << 17]byte +var z12500 [1 << 17]byte +var z12501 [1 << 17]byte +var z12502 [1 << 17]byte +var z12503 [1 << 17]byte +var z12504 [1 << 17]byte +var z12505 [1 << 17]byte +var z12506 [1 << 17]byte +var z12507 [1 << 17]byte +var z12508 [1 << 17]byte +var z12509 [1 << 17]byte +var z12510 [1 << 17]byte +var z12511 [1 << 17]byte +var z12512 [1 << 17]byte +var z12513 [1 << 17]byte +var z12514 [1 << 17]byte +var z12515 [1 << 17]byte +var z12516 [1 << 17]byte +var z12517 [1 << 17]byte +var z12518 [1 << 17]byte +var z12519 [1 << 17]byte +var z12520 [1 << 17]byte +var z12521 [1 << 17]byte +var z12522 [1 << 17]byte +var z12523 [1 << 17]byte +var z12524 [1 << 17]byte +var z12525 [1 << 17]byte +var z12526 [1 << 17]byte +var z12527 [1 << 17]byte +var z12528 [1 << 17]byte +var z12529 [1 << 17]byte +var z12530 [1 << 17]byte +var z12531 [1 << 17]byte +var z12532 [1 << 17]byte +var z12533 [1 << 17]byte +var z12534 [1 << 17]byte +var z12535 [1 << 17]byte +var z12536 [1 << 17]byte +var z12537 [1 << 17]byte +var z12538 [1 << 17]byte +var z12539 [1 << 17]byte +var z12540 [1 << 17]byte +var z12541 [1 << 17]byte +var z12542 [1 << 17]byte +var z12543 [1 << 17]byte +var z12544 [1 << 17]byte +var z12545 [1 << 17]byte +var z12546 [1 << 17]byte +var z12547 [1 << 17]byte +var z12548 [1 << 17]byte +var z12549 [1 << 17]byte +var z12550 [1 << 17]byte +var z12551 [1 << 17]byte +var z12552 [1 << 17]byte +var z12553 [1 << 17]byte +var z12554 [1 << 17]byte +var z12555 [1 << 17]byte +var z12556 [1 << 17]byte +var z12557 [1 << 17]byte +var z12558 [1 << 17]byte +var z12559 [1 << 17]byte +var z12560 [1 << 17]byte +var z12561 [1 << 17]byte +var z12562 [1 << 17]byte +var z12563 [1 << 17]byte +var z12564 [1 << 17]byte +var z12565 [1 << 17]byte +var z12566 [1 << 17]byte +var z12567 [1 << 17]byte +var z12568 [1 << 17]byte +var z12569 [1 << 17]byte +var z12570 [1 << 17]byte +var z12571 [1 << 17]byte +var z12572 [1 << 17]byte +var z12573 [1 << 17]byte +var z12574 [1 << 17]byte +var z12575 [1 << 17]byte +var z12576 [1 << 17]byte +var z12577 [1 << 17]byte +var z12578 [1 << 17]byte +var z12579 [1 << 17]byte +var z12580 [1 << 17]byte +var z12581 [1 << 17]byte +var z12582 [1 << 17]byte +var z12583 [1 << 17]byte +var z12584 [1 << 17]byte +var z12585 [1 << 17]byte +var z12586 [1 << 17]byte +var z12587 [1 << 17]byte +var z12588 [1 << 17]byte +var z12589 [1 << 17]byte +var z12590 [1 << 17]byte +var z12591 [1 << 17]byte +var z12592 [1 << 17]byte +var z12593 [1 << 17]byte +var z12594 [1 << 17]byte +var z12595 [1 << 17]byte +var z12596 [1 << 17]byte +var z12597 [1 << 17]byte +var z12598 [1 << 17]byte +var z12599 [1 << 17]byte +var z12600 [1 << 17]byte +var z12601 [1 << 17]byte +var z12602 [1 << 17]byte +var z12603 [1 << 17]byte +var z12604 [1 << 17]byte +var z12605 [1 << 17]byte +var z12606 [1 << 17]byte +var z12607 [1 << 17]byte +var z12608 [1 << 17]byte +var z12609 [1 << 17]byte +var z12610 [1 << 17]byte +var z12611 [1 << 17]byte +var z12612 [1 << 17]byte +var z12613 [1 << 17]byte +var z12614 [1 << 17]byte +var z12615 [1 << 17]byte +var z12616 [1 << 17]byte +var z12617 [1 << 17]byte +var z12618 [1 << 17]byte +var z12619 [1 << 17]byte +var z12620 [1 << 17]byte +var z12621 [1 << 17]byte +var z12622 [1 << 17]byte +var z12623 [1 << 17]byte +var z12624 [1 << 17]byte +var z12625 [1 << 17]byte +var z12626 [1 << 17]byte +var z12627 [1 << 17]byte +var z12628 [1 << 17]byte +var z12629 [1 << 17]byte +var z12630 [1 << 17]byte +var z12631 [1 << 17]byte +var z12632 [1 << 17]byte +var z12633 [1 << 17]byte +var z12634 [1 << 17]byte +var z12635 [1 << 17]byte +var z12636 [1 << 17]byte +var z12637 [1 << 17]byte +var z12638 [1 << 17]byte +var z12639 [1 << 17]byte +var z12640 [1 << 17]byte +var z12641 [1 << 17]byte +var z12642 [1 << 17]byte +var z12643 [1 << 17]byte +var z12644 [1 << 17]byte +var z12645 [1 << 17]byte +var z12646 [1 << 17]byte +var z12647 [1 << 17]byte +var z12648 [1 << 17]byte +var z12649 [1 << 17]byte +var z12650 [1 << 17]byte +var z12651 [1 << 17]byte +var z12652 [1 << 17]byte +var z12653 [1 << 17]byte +var z12654 [1 << 17]byte +var z12655 [1 << 17]byte +var z12656 [1 << 17]byte +var z12657 [1 << 17]byte +var z12658 [1 << 17]byte +var z12659 [1 << 17]byte +var z12660 [1 << 17]byte +var z12661 [1 << 17]byte +var z12662 [1 << 17]byte +var z12663 [1 << 17]byte +var z12664 [1 << 17]byte +var z12665 [1 << 17]byte +var z12666 [1 << 17]byte +var z12667 [1 << 17]byte +var z12668 [1 << 17]byte +var z12669 [1 << 17]byte +var z12670 [1 << 17]byte +var z12671 [1 << 17]byte +var z12672 [1 << 17]byte +var z12673 [1 << 17]byte +var z12674 [1 << 17]byte +var z12675 [1 << 17]byte +var z12676 [1 << 17]byte +var z12677 [1 << 17]byte +var z12678 [1 << 17]byte +var z12679 [1 << 17]byte +var z12680 [1 << 17]byte +var z12681 [1 << 17]byte +var z12682 [1 << 17]byte +var z12683 [1 << 17]byte +var z12684 [1 << 17]byte +var z12685 [1 << 17]byte +var z12686 [1 << 17]byte +var z12687 [1 << 17]byte +var z12688 [1 << 17]byte +var z12689 [1 << 17]byte +var z12690 [1 << 17]byte +var z12691 [1 << 17]byte +var z12692 [1 << 17]byte +var z12693 [1 << 17]byte +var z12694 [1 << 17]byte +var z12695 [1 << 17]byte +var z12696 [1 << 17]byte +var z12697 [1 << 17]byte +var z12698 [1 << 17]byte +var z12699 [1 << 17]byte +var z12700 [1 << 17]byte +var z12701 [1 << 17]byte +var z12702 [1 << 17]byte +var z12703 [1 << 17]byte +var z12704 [1 << 17]byte +var z12705 [1 << 17]byte +var z12706 [1 << 17]byte +var z12707 [1 << 17]byte +var z12708 [1 << 17]byte +var z12709 [1 << 17]byte +var z12710 [1 << 17]byte +var z12711 [1 << 17]byte +var z12712 [1 << 17]byte +var z12713 [1 << 17]byte +var z12714 [1 << 17]byte +var z12715 [1 << 17]byte +var z12716 [1 << 17]byte +var z12717 [1 << 17]byte +var z12718 [1 << 17]byte +var z12719 [1 << 17]byte +var z12720 [1 << 17]byte +var z12721 [1 << 17]byte +var z12722 [1 << 17]byte +var z12723 [1 << 17]byte +var z12724 [1 << 17]byte +var z12725 [1 << 17]byte +var z12726 [1 << 17]byte +var z12727 [1 << 17]byte +var z12728 [1 << 17]byte +var z12729 [1 << 17]byte +var z12730 [1 << 17]byte +var z12731 [1 << 17]byte +var z12732 [1 << 17]byte +var z12733 [1 << 17]byte +var z12734 [1 << 17]byte +var z12735 [1 << 17]byte +var z12736 [1 << 17]byte +var z12737 [1 << 17]byte +var z12738 [1 << 17]byte +var z12739 [1 << 17]byte +var z12740 [1 << 17]byte +var z12741 [1 << 17]byte +var z12742 [1 << 17]byte +var z12743 [1 << 17]byte +var z12744 [1 << 17]byte +var z12745 [1 << 17]byte +var z12746 [1 << 17]byte +var z12747 [1 << 17]byte +var z12748 [1 << 17]byte +var z12749 [1 << 17]byte +var z12750 [1 << 17]byte +var z12751 [1 << 17]byte +var z12752 [1 << 17]byte +var z12753 [1 << 17]byte +var z12754 [1 << 17]byte +var z12755 [1 << 17]byte +var z12756 [1 << 17]byte +var z12757 [1 << 17]byte +var z12758 [1 << 17]byte +var z12759 [1 << 17]byte +var z12760 [1 << 17]byte +var z12761 [1 << 17]byte +var z12762 [1 << 17]byte +var z12763 [1 << 17]byte +var z12764 [1 << 17]byte +var z12765 [1 << 17]byte +var z12766 [1 << 17]byte +var z12767 [1 << 17]byte +var z12768 [1 << 17]byte +var z12769 [1 << 17]byte +var z12770 [1 << 17]byte +var z12771 [1 << 17]byte +var z12772 [1 << 17]byte +var z12773 [1 << 17]byte +var z12774 [1 << 17]byte +var z12775 [1 << 17]byte +var z12776 [1 << 17]byte +var z12777 [1 << 17]byte +var z12778 [1 << 17]byte +var z12779 [1 << 17]byte +var z12780 [1 << 17]byte +var z12781 [1 << 17]byte +var z12782 [1 << 17]byte +var z12783 [1 << 17]byte +var z12784 [1 << 17]byte +var z12785 [1 << 17]byte +var z12786 [1 << 17]byte +var z12787 [1 << 17]byte +var z12788 [1 << 17]byte +var z12789 [1 << 17]byte +var z12790 [1 << 17]byte +var z12791 [1 << 17]byte +var z12792 [1 << 17]byte +var z12793 [1 << 17]byte +var z12794 [1 << 17]byte +var z12795 [1 << 17]byte +var z12796 [1 << 17]byte +var z12797 [1 << 17]byte +var z12798 [1 << 17]byte +var z12799 [1 << 17]byte +var z12800 [1 << 17]byte +var z12801 [1 << 17]byte +var z12802 [1 << 17]byte +var z12803 [1 << 17]byte +var z12804 [1 << 17]byte +var z12805 [1 << 17]byte +var z12806 [1 << 17]byte +var z12807 [1 << 17]byte +var z12808 [1 << 17]byte +var z12809 [1 << 17]byte +var z12810 [1 << 17]byte +var z12811 [1 << 17]byte +var z12812 [1 << 17]byte +var z12813 [1 << 17]byte +var z12814 [1 << 17]byte +var z12815 [1 << 17]byte +var z12816 [1 << 17]byte +var z12817 [1 << 17]byte +var z12818 [1 << 17]byte +var z12819 [1 << 17]byte +var z12820 [1 << 17]byte +var z12821 [1 << 17]byte +var z12822 [1 << 17]byte +var z12823 [1 << 17]byte +var z12824 [1 << 17]byte +var z12825 [1 << 17]byte +var z12826 [1 << 17]byte +var z12827 [1 << 17]byte +var z12828 [1 << 17]byte +var z12829 [1 << 17]byte +var z12830 [1 << 17]byte +var z12831 [1 << 17]byte +var z12832 [1 << 17]byte +var z12833 [1 << 17]byte +var z12834 [1 << 17]byte +var z12835 [1 << 17]byte +var z12836 [1 << 17]byte +var z12837 [1 << 17]byte +var z12838 [1 << 17]byte +var z12839 [1 << 17]byte +var z12840 [1 << 17]byte +var z12841 [1 << 17]byte +var z12842 [1 << 17]byte +var z12843 [1 << 17]byte +var z12844 [1 << 17]byte +var z12845 [1 << 17]byte +var z12846 [1 << 17]byte +var z12847 [1 << 17]byte +var z12848 [1 << 17]byte +var z12849 [1 << 17]byte +var z12850 [1 << 17]byte +var z12851 [1 << 17]byte +var z12852 [1 << 17]byte +var z12853 [1 << 17]byte +var z12854 [1 << 17]byte +var z12855 [1 << 17]byte +var z12856 [1 << 17]byte +var z12857 [1 << 17]byte +var z12858 [1 << 17]byte +var z12859 [1 << 17]byte +var z12860 [1 << 17]byte +var z12861 [1 << 17]byte +var z12862 [1 << 17]byte +var z12863 [1 << 17]byte +var z12864 [1 << 17]byte +var z12865 [1 << 17]byte +var z12866 [1 << 17]byte +var z12867 [1 << 17]byte +var z12868 [1 << 17]byte +var z12869 [1 << 17]byte +var z12870 [1 << 17]byte +var z12871 [1 << 17]byte +var z12872 [1 << 17]byte +var z12873 [1 << 17]byte +var z12874 [1 << 17]byte +var z12875 [1 << 17]byte +var z12876 [1 << 17]byte +var z12877 [1 << 17]byte +var z12878 [1 << 17]byte +var z12879 [1 << 17]byte +var z12880 [1 << 17]byte +var z12881 [1 << 17]byte +var z12882 [1 << 17]byte +var z12883 [1 << 17]byte +var z12884 [1 << 17]byte +var z12885 [1 << 17]byte +var z12886 [1 << 17]byte +var z12887 [1 << 17]byte +var z12888 [1 << 17]byte +var z12889 [1 << 17]byte +var z12890 [1 << 17]byte +var z12891 [1 << 17]byte +var z12892 [1 << 17]byte +var z12893 [1 << 17]byte +var z12894 [1 << 17]byte +var z12895 [1 << 17]byte +var z12896 [1 << 17]byte +var z12897 [1 << 17]byte +var z12898 [1 << 17]byte +var z12899 [1 << 17]byte +var z12900 [1 << 17]byte +var z12901 [1 << 17]byte +var z12902 [1 << 17]byte +var z12903 [1 << 17]byte +var z12904 [1 << 17]byte +var z12905 [1 << 17]byte +var z12906 [1 << 17]byte +var z12907 [1 << 17]byte +var z12908 [1 << 17]byte +var z12909 [1 << 17]byte +var z12910 [1 << 17]byte +var z12911 [1 << 17]byte +var z12912 [1 << 17]byte +var z12913 [1 << 17]byte +var z12914 [1 << 17]byte +var z12915 [1 << 17]byte +var z12916 [1 << 17]byte +var z12917 [1 << 17]byte +var z12918 [1 << 17]byte +var z12919 [1 << 17]byte +var z12920 [1 << 17]byte +var z12921 [1 << 17]byte +var z12922 [1 << 17]byte +var z12923 [1 << 17]byte +var z12924 [1 << 17]byte +var z12925 [1 << 17]byte +var z12926 [1 << 17]byte +var z12927 [1 << 17]byte +var z12928 [1 << 17]byte +var z12929 [1 << 17]byte +var z12930 [1 << 17]byte +var z12931 [1 << 17]byte +var z12932 [1 << 17]byte +var z12933 [1 << 17]byte +var z12934 [1 << 17]byte +var z12935 [1 << 17]byte +var z12936 [1 << 17]byte +var z12937 [1 << 17]byte +var z12938 [1 << 17]byte +var z12939 [1 << 17]byte +var z12940 [1 << 17]byte +var z12941 [1 << 17]byte +var z12942 [1 << 17]byte +var z12943 [1 << 17]byte +var z12944 [1 << 17]byte +var z12945 [1 << 17]byte +var z12946 [1 << 17]byte +var z12947 [1 << 17]byte +var z12948 [1 << 17]byte +var z12949 [1 << 17]byte +var z12950 [1 << 17]byte +var z12951 [1 << 17]byte +var z12952 [1 << 17]byte +var z12953 [1 << 17]byte +var z12954 [1 << 17]byte +var z12955 [1 << 17]byte +var z12956 [1 << 17]byte +var z12957 [1 << 17]byte +var z12958 [1 << 17]byte +var z12959 [1 << 17]byte +var z12960 [1 << 17]byte +var z12961 [1 << 17]byte +var z12962 [1 << 17]byte +var z12963 [1 << 17]byte +var z12964 [1 << 17]byte +var z12965 [1 << 17]byte +var z12966 [1 << 17]byte +var z12967 [1 << 17]byte +var z12968 [1 << 17]byte +var z12969 [1 << 17]byte +var z12970 [1 << 17]byte +var z12971 [1 << 17]byte +var z12972 [1 << 17]byte +var z12973 [1 << 17]byte +var z12974 [1 << 17]byte +var z12975 [1 << 17]byte +var z12976 [1 << 17]byte +var z12977 [1 << 17]byte +var z12978 [1 << 17]byte +var z12979 [1 << 17]byte +var z12980 [1 << 17]byte +var z12981 [1 << 17]byte +var z12982 [1 << 17]byte +var z12983 [1 << 17]byte +var z12984 [1 << 17]byte +var z12985 [1 << 17]byte +var z12986 [1 << 17]byte +var z12987 [1 << 17]byte +var z12988 [1 << 17]byte +var z12989 [1 << 17]byte +var z12990 [1 << 17]byte +var z12991 [1 << 17]byte +var z12992 [1 << 17]byte +var z12993 [1 << 17]byte +var z12994 [1 << 17]byte +var z12995 [1 << 17]byte +var z12996 [1 << 17]byte +var z12997 [1 << 17]byte +var z12998 [1 << 17]byte +var z12999 [1 << 17]byte +var z13000 [1 << 17]byte +var z13001 [1 << 17]byte +var z13002 [1 << 17]byte +var z13003 [1 << 17]byte +var z13004 [1 << 17]byte +var z13005 [1 << 17]byte +var z13006 [1 << 17]byte +var z13007 [1 << 17]byte +var z13008 [1 << 17]byte +var z13009 [1 << 17]byte +var z13010 [1 << 17]byte +var z13011 [1 << 17]byte +var z13012 [1 << 17]byte +var z13013 [1 << 17]byte +var z13014 [1 << 17]byte +var z13015 [1 << 17]byte +var z13016 [1 << 17]byte +var z13017 [1 << 17]byte +var z13018 [1 << 17]byte +var z13019 [1 << 17]byte +var z13020 [1 << 17]byte +var z13021 [1 << 17]byte +var z13022 [1 << 17]byte +var z13023 [1 << 17]byte +var z13024 [1 << 17]byte +var z13025 [1 << 17]byte +var z13026 [1 << 17]byte +var z13027 [1 << 17]byte +var z13028 [1 << 17]byte +var z13029 [1 << 17]byte +var z13030 [1 << 17]byte +var z13031 [1 << 17]byte +var z13032 [1 << 17]byte +var z13033 [1 << 17]byte +var z13034 [1 << 17]byte +var z13035 [1 << 17]byte +var z13036 [1 << 17]byte +var z13037 [1 << 17]byte +var z13038 [1 << 17]byte +var z13039 [1 << 17]byte +var z13040 [1 << 17]byte +var z13041 [1 << 17]byte +var z13042 [1 << 17]byte +var z13043 [1 << 17]byte +var z13044 [1 << 17]byte +var z13045 [1 << 17]byte +var z13046 [1 << 17]byte +var z13047 [1 << 17]byte +var z13048 [1 << 17]byte +var z13049 [1 << 17]byte +var z13050 [1 << 17]byte +var z13051 [1 << 17]byte +var z13052 [1 << 17]byte +var z13053 [1 << 17]byte +var z13054 [1 << 17]byte +var z13055 [1 << 17]byte +var z13056 [1 << 17]byte +var z13057 [1 << 17]byte +var z13058 [1 << 17]byte +var z13059 [1 << 17]byte +var z13060 [1 << 17]byte +var z13061 [1 << 17]byte +var z13062 [1 << 17]byte +var z13063 [1 << 17]byte +var z13064 [1 << 17]byte +var z13065 [1 << 17]byte +var z13066 [1 << 17]byte +var z13067 [1 << 17]byte +var z13068 [1 << 17]byte +var z13069 [1 << 17]byte +var z13070 [1 << 17]byte +var z13071 [1 << 17]byte +var z13072 [1 << 17]byte +var z13073 [1 << 17]byte +var z13074 [1 << 17]byte +var z13075 [1 << 17]byte +var z13076 [1 << 17]byte +var z13077 [1 << 17]byte +var z13078 [1 << 17]byte +var z13079 [1 << 17]byte +var z13080 [1 << 17]byte +var z13081 [1 << 17]byte +var z13082 [1 << 17]byte +var z13083 [1 << 17]byte +var z13084 [1 << 17]byte +var z13085 [1 << 17]byte +var z13086 [1 << 17]byte +var z13087 [1 << 17]byte +var z13088 [1 << 17]byte +var z13089 [1 << 17]byte +var z13090 [1 << 17]byte +var z13091 [1 << 17]byte +var z13092 [1 << 17]byte +var z13093 [1 << 17]byte +var z13094 [1 << 17]byte +var z13095 [1 << 17]byte +var z13096 [1 << 17]byte +var z13097 [1 << 17]byte +var z13098 [1 << 17]byte +var z13099 [1 << 17]byte +var z13100 [1 << 17]byte +var z13101 [1 << 17]byte +var z13102 [1 << 17]byte +var z13103 [1 << 17]byte +var z13104 [1 << 17]byte +var z13105 [1 << 17]byte +var z13106 [1 << 17]byte +var z13107 [1 << 17]byte +var z13108 [1 << 17]byte +var z13109 [1 << 17]byte +var z13110 [1 << 17]byte +var z13111 [1 << 17]byte +var z13112 [1 << 17]byte +var z13113 [1 << 17]byte +var z13114 [1 << 17]byte +var z13115 [1 << 17]byte +var z13116 [1 << 17]byte +var z13117 [1 << 17]byte +var z13118 [1 << 17]byte +var z13119 [1 << 17]byte +var z13120 [1 << 17]byte +var z13121 [1 << 17]byte +var z13122 [1 << 17]byte +var z13123 [1 << 17]byte +var z13124 [1 << 17]byte +var z13125 [1 << 17]byte +var z13126 [1 << 17]byte +var z13127 [1 << 17]byte +var z13128 [1 << 17]byte +var z13129 [1 << 17]byte +var z13130 [1 << 17]byte +var z13131 [1 << 17]byte +var z13132 [1 << 17]byte +var z13133 [1 << 17]byte +var z13134 [1 << 17]byte +var z13135 [1 << 17]byte +var z13136 [1 << 17]byte +var z13137 [1 << 17]byte +var z13138 [1 << 17]byte +var z13139 [1 << 17]byte +var z13140 [1 << 17]byte +var z13141 [1 << 17]byte +var z13142 [1 << 17]byte +var z13143 [1 << 17]byte +var z13144 [1 << 17]byte +var z13145 [1 << 17]byte +var z13146 [1 << 17]byte +var z13147 [1 << 17]byte +var z13148 [1 << 17]byte +var z13149 [1 << 17]byte +var z13150 [1 << 17]byte +var z13151 [1 << 17]byte +var z13152 [1 << 17]byte +var z13153 [1 << 17]byte +var z13154 [1 << 17]byte +var z13155 [1 << 17]byte +var z13156 [1 << 17]byte +var z13157 [1 << 17]byte +var z13158 [1 << 17]byte +var z13159 [1 << 17]byte +var z13160 [1 << 17]byte +var z13161 [1 << 17]byte +var z13162 [1 << 17]byte +var z13163 [1 << 17]byte +var z13164 [1 << 17]byte +var z13165 [1 << 17]byte +var z13166 [1 << 17]byte +var z13167 [1 << 17]byte +var z13168 [1 << 17]byte +var z13169 [1 << 17]byte +var z13170 [1 << 17]byte +var z13171 [1 << 17]byte +var z13172 [1 << 17]byte +var z13173 [1 << 17]byte +var z13174 [1 << 17]byte +var z13175 [1 << 17]byte +var z13176 [1 << 17]byte +var z13177 [1 << 17]byte +var z13178 [1 << 17]byte +var z13179 [1 << 17]byte +var z13180 [1 << 17]byte +var z13181 [1 << 17]byte +var z13182 [1 << 17]byte +var z13183 [1 << 17]byte +var z13184 [1 << 17]byte +var z13185 [1 << 17]byte +var z13186 [1 << 17]byte +var z13187 [1 << 17]byte +var z13188 [1 << 17]byte +var z13189 [1 << 17]byte +var z13190 [1 << 17]byte +var z13191 [1 << 17]byte +var z13192 [1 << 17]byte +var z13193 [1 << 17]byte +var z13194 [1 << 17]byte +var z13195 [1 << 17]byte +var z13196 [1 << 17]byte +var z13197 [1 << 17]byte +var z13198 [1 << 17]byte +var z13199 [1 << 17]byte +var z13200 [1 << 17]byte +var z13201 [1 << 17]byte +var z13202 [1 << 17]byte +var z13203 [1 << 17]byte +var z13204 [1 << 17]byte +var z13205 [1 << 17]byte +var z13206 [1 << 17]byte +var z13207 [1 << 17]byte +var z13208 [1 << 17]byte +var z13209 [1 << 17]byte +var z13210 [1 << 17]byte +var z13211 [1 << 17]byte +var z13212 [1 << 17]byte +var z13213 [1 << 17]byte +var z13214 [1 << 17]byte +var z13215 [1 << 17]byte +var z13216 [1 << 17]byte +var z13217 [1 << 17]byte +var z13218 [1 << 17]byte +var z13219 [1 << 17]byte +var z13220 [1 << 17]byte +var z13221 [1 << 17]byte +var z13222 [1 << 17]byte +var z13223 [1 << 17]byte +var z13224 [1 << 17]byte +var z13225 [1 << 17]byte +var z13226 [1 << 17]byte +var z13227 [1 << 17]byte +var z13228 [1 << 17]byte +var z13229 [1 << 17]byte +var z13230 [1 << 17]byte +var z13231 [1 << 17]byte +var z13232 [1 << 17]byte +var z13233 [1 << 17]byte +var z13234 [1 << 17]byte +var z13235 [1 << 17]byte +var z13236 [1 << 17]byte +var z13237 [1 << 17]byte +var z13238 [1 << 17]byte +var z13239 [1 << 17]byte +var z13240 [1 << 17]byte +var z13241 [1 << 17]byte +var z13242 [1 << 17]byte +var z13243 [1 << 17]byte +var z13244 [1 << 17]byte +var z13245 [1 << 17]byte +var z13246 [1 << 17]byte +var z13247 [1 << 17]byte +var z13248 [1 << 17]byte +var z13249 [1 << 17]byte +var z13250 [1 << 17]byte +var z13251 [1 << 17]byte +var z13252 [1 << 17]byte +var z13253 [1 << 17]byte +var z13254 [1 << 17]byte +var z13255 [1 << 17]byte +var z13256 [1 << 17]byte +var z13257 [1 << 17]byte +var z13258 [1 << 17]byte +var z13259 [1 << 17]byte +var z13260 [1 << 17]byte +var z13261 [1 << 17]byte +var z13262 [1 << 17]byte +var z13263 [1 << 17]byte +var z13264 [1 << 17]byte +var z13265 [1 << 17]byte +var z13266 [1 << 17]byte +var z13267 [1 << 17]byte +var z13268 [1 << 17]byte +var z13269 [1 << 17]byte +var z13270 [1 << 17]byte +var z13271 [1 << 17]byte +var z13272 [1 << 17]byte +var z13273 [1 << 17]byte +var z13274 [1 << 17]byte +var z13275 [1 << 17]byte +var z13276 [1 << 17]byte +var z13277 [1 << 17]byte +var z13278 [1 << 17]byte +var z13279 [1 << 17]byte +var z13280 [1 << 17]byte +var z13281 [1 << 17]byte +var z13282 [1 << 17]byte +var z13283 [1 << 17]byte +var z13284 [1 << 17]byte +var z13285 [1 << 17]byte +var z13286 [1 << 17]byte +var z13287 [1 << 17]byte +var z13288 [1 << 17]byte +var z13289 [1 << 17]byte +var z13290 [1 << 17]byte +var z13291 [1 << 17]byte +var z13292 [1 << 17]byte +var z13293 [1 << 17]byte +var z13294 [1 << 17]byte +var z13295 [1 << 17]byte +var z13296 [1 << 17]byte +var z13297 [1 << 17]byte +var z13298 [1 << 17]byte +var z13299 [1 << 17]byte +var z13300 [1 << 17]byte +var z13301 [1 << 17]byte +var z13302 [1 << 17]byte +var z13303 [1 << 17]byte +var z13304 [1 << 17]byte +var z13305 [1 << 17]byte +var z13306 [1 << 17]byte +var z13307 [1 << 17]byte +var z13308 [1 << 17]byte +var z13309 [1 << 17]byte +var z13310 [1 << 17]byte +var z13311 [1 << 17]byte +var z13312 [1 << 17]byte +var z13313 [1 << 17]byte +var z13314 [1 << 17]byte +var z13315 [1 << 17]byte +var z13316 [1 << 17]byte +var z13317 [1 << 17]byte +var z13318 [1 << 17]byte +var z13319 [1 << 17]byte +var z13320 [1 << 17]byte +var z13321 [1 << 17]byte +var z13322 [1 << 17]byte +var z13323 [1 << 17]byte +var z13324 [1 << 17]byte +var z13325 [1 << 17]byte +var z13326 [1 << 17]byte +var z13327 [1 << 17]byte +var z13328 [1 << 17]byte +var z13329 [1 << 17]byte +var z13330 [1 << 17]byte +var z13331 [1 << 17]byte +var z13332 [1 << 17]byte +var z13333 [1 << 17]byte +var z13334 [1 << 17]byte +var z13335 [1 << 17]byte +var z13336 [1 << 17]byte +var z13337 [1 << 17]byte +var z13338 [1 << 17]byte +var z13339 [1 << 17]byte +var z13340 [1 << 17]byte +var z13341 [1 << 17]byte +var z13342 [1 << 17]byte +var z13343 [1 << 17]byte +var z13344 [1 << 17]byte +var z13345 [1 << 17]byte +var z13346 [1 << 17]byte +var z13347 [1 << 17]byte +var z13348 [1 << 17]byte +var z13349 [1 << 17]byte +var z13350 [1 << 17]byte +var z13351 [1 << 17]byte +var z13352 [1 << 17]byte +var z13353 [1 << 17]byte +var z13354 [1 << 17]byte +var z13355 [1 << 17]byte +var z13356 [1 << 17]byte +var z13357 [1 << 17]byte +var z13358 [1 << 17]byte +var z13359 [1 << 17]byte +var z13360 [1 << 17]byte +var z13361 [1 << 17]byte +var z13362 [1 << 17]byte +var z13363 [1 << 17]byte +var z13364 [1 << 17]byte +var z13365 [1 << 17]byte +var z13366 [1 << 17]byte +var z13367 [1 << 17]byte +var z13368 [1 << 17]byte +var z13369 [1 << 17]byte +var z13370 [1 << 17]byte +var z13371 [1 << 17]byte +var z13372 [1 << 17]byte +var z13373 [1 << 17]byte +var z13374 [1 << 17]byte +var z13375 [1 << 17]byte +var z13376 [1 << 17]byte +var z13377 [1 << 17]byte +var z13378 [1 << 17]byte +var z13379 [1 << 17]byte +var z13380 [1 << 17]byte +var z13381 [1 << 17]byte +var z13382 [1 << 17]byte +var z13383 [1 << 17]byte +var z13384 [1 << 17]byte +var z13385 [1 << 17]byte +var z13386 [1 << 17]byte +var z13387 [1 << 17]byte +var z13388 [1 << 17]byte +var z13389 [1 << 17]byte +var z13390 [1 << 17]byte +var z13391 [1 << 17]byte +var z13392 [1 << 17]byte +var z13393 [1 << 17]byte +var z13394 [1 << 17]byte +var z13395 [1 << 17]byte +var z13396 [1 << 17]byte +var z13397 [1 << 17]byte +var z13398 [1 << 17]byte +var z13399 [1 << 17]byte +var z13400 [1 << 17]byte +var z13401 [1 << 17]byte +var z13402 [1 << 17]byte +var z13403 [1 << 17]byte +var z13404 [1 << 17]byte +var z13405 [1 << 17]byte +var z13406 [1 << 17]byte +var z13407 [1 << 17]byte +var z13408 [1 << 17]byte +var z13409 [1 << 17]byte +var z13410 [1 << 17]byte +var z13411 [1 << 17]byte +var z13412 [1 << 17]byte +var z13413 [1 << 17]byte +var z13414 [1 << 17]byte +var z13415 [1 << 17]byte +var z13416 [1 << 17]byte +var z13417 [1 << 17]byte +var z13418 [1 << 17]byte +var z13419 [1 << 17]byte +var z13420 [1 << 17]byte +var z13421 [1 << 17]byte +var z13422 [1 << 17]byte +var z13423 [1 << 17]byte +var z13424 [1 << 17]byte +var z13425 [1 << 17]byte +var z13426 [1 << 17]byte +var z13427 [1 << 17]byte +var z13428 [1 << 17]byte +var z13429 [1 << 17]byte +var z13430 [1 << 17]byte +var z13431 [1 << 17]byte +var z13432 [1 << 17]byte +var z13433 [1 << 17]byte +var z13434 [1 << 17]byte +var z13435 [1 << 17]byte +var z13436 [1 << 17]byte +var z13437 [1 << 17]byte +var z13438 [1 << 17]byte +var z13439 [1 << 17]byte +var z13440 [1 << 17]byte +var z13441 [1 << 17]byte +var z13442 [1 << 17]byte +var z13443 [1 << 17]byte +var z13444 [1 << 17]byte +var z13445 [1 << 17]byte +var z13446 [1 << 17]byte +var z13447 [1 << 17]byte +var z13448 [1 << 17]byte +var z13449 [1 << 17]byte +var z13450 [1 << 17]byte +var z13451 [1 << 17]byte +var z13452 [1 << 17]byte +var z13453 [1 << 17]byte +var z13454 [1 << 17]byte +var z13455 [1 << 17]byte +var z13456 [1 << 17]byte +var z13457 [1 << 17]byte +var z13458 [1 << 17]byte +var z13459 [1 << 17]byte +var z13460 [1 << 17]byte +var z13461 [1 << 17]byte +var z13462 [1 << 17]byte +var z13463 [1 << 17]byte +var z13464 [1 << 17]byte +var z13465 [1 << 17]byte +var z13466 [1 << 17]byte +var z13467 [1 << 17]byte +var z13468 [1 << 17]byte +var z13469 [1 << 17]byte +var z13470 [1 << 17]byte +var z13471 [1 << 17]byte +var z13472 [1 << 17]byte +var z13473 [1 << 17]byte +var z13474 [1 << 17]byte +var z13475 [1 << 17]byte +var z13476 [1 << 17]byte +var z13477 [1 << 17]byte +var z13478 [1 << 17]byte +var z13479 [1 << 17]byte +var z13480 [1 << 17]byte +var z13481 [1 << 17]byte +var z13482 [1 << 17]byte +var z13483 [1 << 17]byte +var z13484 [1 << 17]byte +var z13485 [1 << 17]byte +var z13486 [1 << 17]byte +var z13487 [1 << 17]byte +var z13488 [1 << 17]byte +var z13489 [1 << 17]byte +var z13490 [1 << 17]byte +var z13491 [1 << 17]byte +var z13492 [1 << 17]byte +var z13493 [1 << 17]byte +var z13494 [1 << 17]byte +var z13495 [1 << 17]byte +var z13496 [1 << 17]byte +var z13497 [1 << 17]byte +var z13498 [1 << 17]byte +var z13499 [1 << 17]byte +var z13500 [1 << 17]byte +var z13501 [1 << 17]byte +var z13502 [1 << 17]byte +var z13503 [1 << 17]byte +var z13504 [1 << 17]byte +var z13505 [1 << 17]byte +var z13506 [1 << 17]byte +var z13507 [1 << 17]byte +var z13508 [1 << 17]byte +var z13509 [1 << 17]byte +var z13510 [1 << 17]byte +var z13511 [1 << 17]byte +var z13512 [1 << 17]byte +var z13513 [1 << 17]byte +var z13514 [1 << 17]byte +var z13515 [1 << 17]byte +var z13516 [1 << 17]byte +var z13517 [1 << 17]byte +var z13518 [1 << 17]byte +var z13519 [1 << 17]byte +var z13520 [1 << 17]byte +var z13521 [1 << 17]byte +var z13522 [1 << 17]byte +var z13523 [1 << 17]byte +var z13524 [1 << 17]byte +var z13525 [1 << 17]byte +var z13526 [1 << 17]byte +var z13527 [1 << 17]byte +var z13528 [1 << 17]byte +var z13529 [1 << 17]byte +var z13530 [1 << 17]byte +var z13531 [1 << 17]byte +var z13532 [1 << 17]byte +var z13533 [1 << 17]byte +var z13534 [1 << 17]byte +var z13535 [1 << 17]byte +var z13536 [1 << 17]byte +var z13537 [1 << 17]byte +var z13538 [1 << 17]byte +var z13539 [1 << 17]byte +var z13540 [1 << 17]byte +var z13541 [1 << 17]byte +var z13542 [1 << 17]byte +var z13543 [1 << 17]byte +var z13544 [1 << 17]byte +var z13545 [1 << 17]byte +var z13546 [1 << 17]byte +var z13547 [1 << 17]byte +var z13548 [1 << 17]byte +var z13549 [1 << 17]byte +var z13550 [1 << 17]byte +var z13551 [1 << 17]byte +var z13552 [1 << 17]byte +var z13553 [1 << 17]byte +var z13554 [1 << 17]byte +var z13555 [1 << 17]byte +var z13556 [1 << 17]byte +var z13557 [1 << 17]byte +var z13558 [1 << 17]byte +var z13559 [1 << 17]byte +var z13560 [1 << 17]byte +var z13561 [1 << 17]byte +var z13562 [1 << 17]byte +var z13563 [1 << 17]byte +var z13564 [1 << 17]byte +var z13565 [1 << 17]byte +var z13566 [1 << 17]byte +var z13567 [1 << 17]byte +var z13568 [1 << 17]byte +var z13569 [1 << 17]byte +var z13570 [1 << 17]byte +var z13571 [1 << 17]byte +var z13572 [1 << 17]byte +var z13573 [1 << 17]byte +var z13574 [1 << 17]byte +var z13575 [1 << 17]byte +var z13576 [1 << 17]byte +var z13577 [1 << 17]byte +var z13578 [1 << 17]byte +var z13579 [1 << 17]byte +var z13580 [1 << 17]byte +var z13581 [1 << 17]byte +var z13582 [1 << 17]byte +var z13583 [1 << 17]byte +var z13584 [1 << 17]byte +var z13585 [1 << 17]byte +var z13586 [1 << 17]byte +var z13587 [1 << 17]byte +var z13588 [1 << 17]byte +var z13589 [1 << 17]byte +var z13590 [1 << 17]byte +var z13591 [1 << 17]byte +var z13592 [1 << 17]byte +var z13593 [1 << 17]byte +var z13594 [1 << 17]byte +var z13595 [1 << 17]byte +var z13596 [1 << 17]byte +var z13597 [1 << 17]byte +var z13598 [1 << 17]byte +var z13599 [1 << 17]byte +var z13600 [1 << 17]byte +var z13601 [1 << 17]byte +var z13602 [1 << 17]byte +var z13603 [1 << 17]byte +var z13604 [1 << 17]byte +var z13605 [1 << 17]byte +var z13606 [1 << 17]byte +var z13607 [1 << 17]byte +var z13608 [1 << 17]byte +var z13609 [1 << 17]byte +var z13610 [1 << 17]byte +var z13611 [1 << 17]byte +var z13612 [1 << 17]byte +var z13613 [1 << 17]byte +var z13614 [1 << 17]byte +var z13615 [1 << 17]byte +var z13616 [1 << 17]byte +var z13617 [1 << 17]byte +var z13618 [1 << 17]byte +var z13619 [1 << 17]byte +var z13620 [1 << 17]byte +var z13621 [1 << 17]byte +var z13622 [1 << 17]byte +var z13623 [1 << 17]byte +var z13624 [1 << 17]byte +var z13625 [1 << 17]byte +var z13626 [1 << 17]byte +var z13627 [1 << 17]byte +var z13628 [1 << 17]byte +var z13629 [1 << 17]byte +var z13630 [1 << 17]byte +var z13631 [1 << 17]byte +var z13632 [1 << 17]byte +var z13633 [1 << 17]byte +var z13634 [1 << 17]byte +var z13635 [1 << 17]byte +var z13636 [1 << 17]byte +var z13637 [1 << 17]byte +var z13638 [1 << 17]byte +var z13639 [1 << 17]byte +var z13640 [1 << 17]byte +var z13641 [1 << 17]byte +var z13642 [1 << 17]byte +var z13643 [1 << 17]byte +var z13644 [1 << 17]byte +var z13645 [1 << 17]byte +var z13646 [1 << 17]byte +var z13647 [1 << 17]byte +var z13648 [1 << 17]byte +var z13649 [1 << 17]byte +var z13650 [1 << 17]byte +var z13651 [1 << 17]byte +var z13652 [1 << 17]byte +var z13653 [1 << 17]byte +var z13654 [1 << 17]byte +var z13655 [1 << 17]byte +var z13656 [1 << 17]byte +var z13657 [1 << 17]byte +var z13658 [1 << 17]byte +var z13659 [1 << 17]byte +var z13660 [1 << 17]byte +var z13661 [1 << 17]byte +var z13662 [1 << 17]byte +var z13663 [1 << 17]byte +var z13664 [1 << 17]byte +var z13665 [1 << 17]byte +var z13666 [1 << 17]byte +var z13667 [1 << 17]byte +var z13668 [1 << 17]byte +var z13669 [1 << 17]byte +var z13670 [1 << 17]byte +var z13671 [1 << 17]byte +var z13672 [1 << 17]byte +var z13673 [1 << 17]byte +var z13674 [1 << 17]byte +var z13675 [1 << 17]byte +var z13676 [1 << 17]byte +var z13677 [1 << 17]byte +var z13678 [1 << 17]byte +var z13679 [1 << 17]byte +var z13680 [1 << 17]byte +var z13681 [1 << 17]byte +var z13682 [1 << 17]byte +var z13683 [1 << 17]byte +var z13684 [1 << 17]byte +var z13685 [1 << 17]byte +var z13686 [1 << 17]byte +var z13687 [1 << 17]byte +var z13688 [1 << 17]byte +var z13689 [1 << 17]byte +var z13690 [1 << 17]byte +var z13691 [1 << 17]byte +var z13692 [1 << 17]byte +var z13693 [1 << 17]byte +var z13694 [1 << 17]byte +var z13695 [1 << 17]byte +var z13696 [1 << 17]byte +var z13697 [1 << 17]byte +var z13698 [1 << 17]byte +var z13699 [1 << 17]byte +var z13700 [1 << 17]byte +var z13701 [1 << 17]byte +var z13702 [1 << 17]byte +var z13703 [1 << 17]byte +var z13704 [1 << 17]byte +var z13705 [1 << 17]byte +var z13706 [1 << 17]byte +var z13707 [1 << 17]byte +var z13708 [1 << 17]byte +var z13709 [1 << 17]byte +var z13710 [1 << 17]byte +var z13711 [1 << 17]byte +var z13712 [1 << 17]byte +var z13713 [1 << 17]byte +var z13714 [1 << 17]byte +var z13715 [1 << 17]byte +var z13716 [1 << 17]byte +var z13717 [1 << 17]byte +var z13718 [1 << 17]byte +var z13719 [1 << 17]byte +var z13720 [1 << 17]byte +var z13721 [1 << 17]byte +var z13722 [1 << 17]byte +var z13723 [1 << 17]byte +var z13724 [1 << 17]byte +var z13725 [1 << 17]byte +var z13726 [1 << 17]byte +var z13727 [1 << 17]byte +var z13728 [1 << 17]byte +var z13729 [1 << 17]byte +var z13730 [1 << 17]byte +var z13731 [1 << 17]byte +var z13732 [1 << 17]byte +var z13733 [1 << 17]byte +var z13734 [1 << 17]byte +var z13735 [1 << 17]byte +var z13736 [1 << 17]byte +var z13737 [1 << 17]byte +var z13738 [1 << 17]byte +var z13739 [1 << 17]byte +var z13740 [1 << 17]byte +var z13741 [1 << 17]byte +var z13742 [1 << 17]byte +var z13743 [1 << 17]byte +var z13744 [1 << 17]byte +var z13745 [1 << 17]byte +var z13746 [1 << 17]byte +var z13747 [1 << 17]byte +var z13748 [1 << 17]byte +var z13749 [1 << 17]byte +var z13750 [1 << 17]byte +var z13751 [1 << 17]byte +var z13752 [1 << 17]byte +var z13753 [1 << 17]byte +var z13754 [1 << 17]byte +var z13755 [1 << 17]byte +var z13756 [1 << 17]byte +var z13757 [1 << 17]byte +var z13758 [1 << 17]byte +var z13759 [1 << 17]byte +var z13760 [1 << 17]byte +var z13761 [1 << 17]byte +var z13762 [1 << 17]byte +var z13763 [1 << 17]byte +var z13764 [1 << 17]byte +var z13765 [1 << 17]byte +var z13766 [1 << 17]byte +var z13767 [1 << 17]byte +var z13768 [1 << 17]byte +var z13769 [1 << 17]byte +var z13770 [1 << 17]byte +var z13771 [1 << 17]byte +var z13772 [1 << 17]byte +var z13773 [1 << 17]byte +var z13774 [1 << 17]byte +var z13775 [1 << 17]byte +var z13776 [1 << 17]byte +var z13777 [1 << 17]byte +var z13778 [1 << 17]byte +var z13779 [1 << 17]byte +var z13780 [1 << 17]byte +var z13781 [1 << 17]byte +var z13782 [1 << 17]byte +var z13783 [1 << 17]byte +var z13784 [1 << 17]byte +var z13785 [1 << 17]byte +var z13786 [1 << 17]byte +var z13787 [1 << 17]byte +var z13788 [1 << 17]byte +var z13789 [1 << 17]byte +var z13790 [1 << 17]byte +var z13791 [1 << 17]byte +var z13792 [1 << 17]byte +var z13793 [1 << 17]byte +var z13794 [1 << 17]byte +var z13795 [1 << 17]byte +var z13796 [1 << 17]byte +var z13797 [1 << 17]byte +var z13798 [1 << 17]byte +var z13799 [1 << 17]byte +var z13800 [1 << 17]byte +var z13801 [1 << 17]byte +var z13802 [1 << 17]byte +var z13803 [1 << 17]byte +var z13804 [1 << 17]byte +var z13805 [1 << 17]byte +var z13806 [1 << 17]byte +var z13807 [1 << 17]byte +var z13808 [1 << 17]byte +var z13809 [1 << 17]byte +var z13810 [1 << 17]byte +var z13811 [1 << 17]byte +var z13812 [1 << 17]byte +var z13813 [1 << 17]byte +var z13814 [1 << 17]byte +var z13815 [1 << 17]byte +var z13816 [1 << 17]byte +var z13817 [1 << 17]byte +var z13818 [1 << 17]byte +var z13819 [1 << 17]byte +var z13820 [1 << 17]byte +var z13821 [1 << 17]byte +var z13822 [1 << 17]byte +var z13823 [1 << 17]byte +var z13824 [1 << 17]byte +var z13825 [1 << 17]byte +var z13826 [1 << 17]byte +var z13827 [1 << 17]byte +var z13828 [1 << 17]byte +var z13829 [1 << 17]byte +var z13830 [1 << 17]byte +var z13831 [1 << 17]byte +var z13832 [1 << 17]byte +var z13833 [1 << 17]byte +var z13834 [1 << 17]byte +var z13835 [1 << 17]byte +var z13836 [1 << 17]byte +var z13837 [1 << 17]byte +var z13838 [1 << 17]byte +var z13839 [1 << 17]byte +var z13840 [1 << 17]byte +var z13841 [1 << 17]byte +var z13842 [1 << 17]byte +var z13843 [1 << 17]byte +var z13844 [1 << 17]byte +var z13845 [1 << 17]byte +var z13846 [1 << 17]byte +var z13847 [1 << 17]byte +var z13848 [1 << 17]byte +var z13849 [1 << 17]byte +var z13850 [1 << 17]byte +var z13851 [1 << 17]byte +var z13852 [1 << 17]byte +var z13853 [1 << 17]byte +var z13854 [1 << 17]byte +var z13855 [1 << 17]byte +var z13856 [1 << 17]byte +var z13857 [1 << 17]byte +var z13858 [1 << 17]byte +var z13859 [1 << 17]byte +var z13860 [1 << 17]byte +var z13861 [1 << 17]byte +var z13862 [1 << 17]byte +var z13863 [1 << 17]byte +var z13864 [1 << 17]byte +var z13865 [1 << 17]byte +var z13866 [1 << 17]byte +var z13867 [1 << 17]byte +var z13868 [1 << 17]byte +var z13869 [1 << 17]byte +var z13870 [1 << 17]byte +var z13871 [1 << 17]byte +var z13872 [1 << 17]byte +var z13873 [1 << 17]byte +var z13874 [1 << 17]byte +var z13875 [1 << 17]byte +var z13876 [1 << 17]byte +var z13877 [1 << 17]byte +var z13878 [1 << 17]byte +var z13879 [1 << 17]byte +var z13880 [1 << 17]byte +var z13881 [1 << 17]byte +var z13882 [1 << 17]byte +var z13883 [1 << 17]byte +var z13884 [1 << 17]byte +var z13885 [1 << 17]byte +var z13886 [1 << 17]byte +var z13887 [1 << 17]byte +var z13888 [1 << 17]byte +var z13889 [1 << 17]byte +var z13890 [1 << 17]byte +var z13891 [1 << 17]byte +var z13892 [1 << 17]byte +var z13893 [1 << 17]byte +var z13894 [1 << 17]byte +var z13895 [1 << 17]byte +var z13896 [1 << 17]byte +var z13897 [1 << 17]byte +var z13898 [1 << 17]byte +var z13899 [1 << 17]byte +var z13900 [1 << 17]byte +var z13901 [1 << 17]byte +var z13902 [1 << 17]byte +var z13903 [1 << 17]byte +var z13904 [1 << 17]byte +var z13905 [1 << 17]byte +var z13906 [1 << 17]byte +var z13907 [1 << 17]byte +var z13908 [1 << 17]byte +var z13909 [1 << 17]byte +var z13910 [1 << 17]byte +var z13911 [1 << 17]byte +var z13912 [1 << 17]byte +var z13913 [1 << 17]byte +var z13914 [1 << 17]byte +var z13915 [1 << 17]byte +var z13916 [1 << 17]byte +var z13917 [1 << 17]byte +var z13918 [1 << 17]byte +var z13919 [1 << 17]byte +var z13920 [1 << 17]byte +var z13921 [1 << 17]byte +var z13922 [1 << 17]byte +var z13923 [1 << 17]byte +var z13924 [1 << 17]byte +var z13925 [1 << 17]byte +var z13926 [1 << 17]byte +var z13927 [1 << 17]byte +var z13928 [1 << 17]byte +var z13929 [1 << 17]byte +var z13930 [1 << 17]byte +var z13931 [1 << 17]byte +var z13932 [1 << 17]byte +var z13933 [1 << 17]byte +var z13934 [1 << 17]byte +var z13935 [1 << 17]byte +var z13936 [1 << 17]byte +var z13937 [1 << 17]byte +var z13938 [1 << 17]byte +var z13939 [1 << 17]byte +var z13940 [1 << 17]byte +var z13941 [1 << 17]byte +var z13942 [1 << 17]byte +var z13943 [1 << 17]byte +var z13944 [1 << 17]byte +var z13945 [1 << 17]byte +var z13946 [1 << 17]byte +var z13947 [1 << 17]byte +var z13948 [1 << 17]byte +var z13949 [1 << 17]byte +var z13950 [1 << 17]byte +var z13951 [1 << 17]byte +var z13952 [1 << 17]byte +var z13953 [1 << 17]byte +var z13954 [1 << 17]byte +var z13955 [1 << 17]byte +var z13956 [1 << 17]byte +var z13957 [1 << 17]byte +var z13958 [1 << 17]byte +var z13959 [1 << 17]byte +var z13960 [1 << 17]byte +var z13961 [1 << 17]byte +var z13962 [1 << 17]byte +var z13963 [1 << 17]byte +var z13964 [1 << 17]byte +var z13965 [1 << 17]byte +var z13966 [1 << 17]byte +var z13967 [1 << 17]byte +var z13968 [1 << 17]byte +var z13969 [1 << 17]byte +var z13970 [1 << 17]byte +var z13971 [1 << 17]byte +var z13972 [1 << 17]byte +var z13973 [1 << 17]byte +var z13974 [1 << 17]byte +var z13975 [1 << 17]byte +var z13976 [1 << 17]byte +var z13977 [1 << 17]byte +var z13978 [1 << 17]byte +var z13979 [1 << 17]byte +var z13980 [1 << 17]byte +var z13981 [1 << 17]byte +var z13982 [1 << 17]byte +var z13983 [1 << 17]byte +var z13984 [1 << 17]byte +var z13985 [1 << 17]byte +var z13986 [1 << 17]byte +var z13987 [1 << 17]byte +var z13988 [1 << 17]byte +var z13989 [1 << 17]byte +var z13990 [1 << 17]byte +var z13991 [1 << 17]byte +var z13992 [1 << 17]byte +var z13993 [1 << 17]byte +var z13994 [1 << 17]byte +var z13995 [1 << 17]byte +var z13996 [1 << 17]byte +var z13997 [1 << 17]byte +var z13998 [1 << 17]byte +var z13999 [1 << 17]byte +var z14000 [1 << 17]byte +var z14001 [1 << 17]byte +var z14002 [1 << 17]byte +var z14003 [1 << 17]byte +var z14004 [1 << 17]byte +var z14005 [1 << 17]byte +var z14006 [1 << 17]byte +var z14007 [1 << 17]byte +var z14008 [1 << 17]byte +var z14009 [1 << 17]byte +var z14010 [1 << 17]byte +var z14011 [1 << 17]byte +var z14012 [1 << 17]byte +var z14013 [1 << 17]byte +var z14014 [1 << 17]byte +var z14015 [1 << 17]byte +var z14016 [1 << 17]byte +var z14017 [1 << 17]byte +var z14018 [1 << 17]byte +var z14019 [1 << 17]byte +var z14020 [1 << 17]byte +var z14021 [1 << 17]byte +var z14022 [1 << 17]byte +var z14023 [1 << 17]byte +var z14024 [1 << 17]byte +var z14025 [1 << 17]byte +var z14026 [1 << 17]byte +var z14027 [1 << 17]byte +var z14028 [1 << 17]byte +var z14029 [1 << 17]byte +var z14030 [1 << 17]byte +var z14031 [1 << 17]byte +var z14032 [1 << 17]byte +var z14033 [1 << 17]byte +var z14034 [1 << 17]byte +var z14035 [1 << 17]byte +var z14036 [1 << 17]byte +var z14037 [1 << 17]byte +var z14038 [1 << 17]byte +var z14039 [1 << 17]byte +var z14040 [1 << 17]byte +var z14041 [1 << 17]byte +var z14042 [1 << 17]byte +var z14043 [1 << 17]byte +var z14044 [1 << 17]byte +var z14045 [1 << 17]byte +var z14046 [1 << 17]byte +var z14047 [1 << 17]byte +var z14048 [1 << 17]byte +var z14049 [1 << 17]byte +var z14050 [1 << 17]byte +var z14051 [1 << 17]byte +var z14052 [1 << 17]byte +var z14053 [1 << 17]byte +var z14054 [1 << 17]byte +var z14055 [1 << 17]byte +var z14056 [1 << 17]byte +var z14057 [1 << 17]byte +var z14058 [1 << 17]byte +var z14059 [1 << 17]byte +var z14060 [1 << 17]byte +var z14061 [1 << 17]byte +var z14062 [1 << 17]byte +var z14063 [1 << 17]byte +var z14064 [1 << 17]byte +var z14065 [1 << 17]byte +var z14066 [1 << 17]byte +var z14067 [1 << 17]byte +var z14068 [1 << 17]byte +var z14069 [1 << 17]byte +var z14070 [1 << 17]byte +var z14071 [1 << 17]byte +var z14072 [1 << 17]byte +var z14073 [1 << 17]byte +var z14074 [1 << 17]byte +var z14075 [1 << 17]byte +var z14076 [1 << 17]byte +var z14077 [1 << 17]byte +var z14078 [1 << 17]byte +var z14079 [1 << 17]byte +var z14080 [1 << 17]byte +var z14081 [1 << 17]byte +var z14082 [1 << 17]byte +var z14083 [1 << 17]byte +var z14084 [1 << 17]byte +var z14085 [1 << 17]byte +var z14086 [1 << 17]byte +var z14087 [1 << 17]byte +var z14088 [1 << 17]byte +var z14089 [1 << 17]byte +var z14090 [1 << 17]byte +var z14091 [1 << 17]byte +var z14092 [1 << 17]byte +var z14093 [1 << 17]byte +var z14094 [1 << 17]byte +var z14095 [1 << 17]byte +var z14096 [1 << 17]byte +var z14097 [1 << 17]byte +var z14098 [1 << 17]byte +var z14099 [1 << 17]byte +var z14100 [1 << 17]byte +var z14101 [1 << 17]byte +var z14102 [1 << 17]byte +var z14103 [1 << 17]byte +var z14104 [1 << 17]byte +var z14105 [1 << 17]byte +var z14106 [1 << 17]byte +var z14107 [1 << 17]byte +var z14108 [1 << 17]byte +var z14109 [1 << 17]byte +var z14110 [1 << 17]byte +var z14111 [1 << 17]byte +var z14112 [1 << 17]byte +var z14113 [1 << 17]byte +var z14114 [1 << 17]byte +var z14115 [1 << 17]byte +var z14116 [1 << 17]byte +var z14117 [1 << 17]byte +var z14118 [1 << 17]byte +var z14119 [1 << 17]byte +var z14120 [1 << 17]byte +var z14121 [1 << 17]byte +var z14122 [1 << 17]byte +var z14123 [1 << 17]byte +var z14124 [1 << 17]byte +var z14125 [1 << 17]byte +var z14126 [1 << 17]byte +var z14127 [1 << 17]byte +var z14128 [1 << 17]byte +var z14129 [1 << 17]byte +var z14130 [1 << 17]byte +var z14131 [1 << 17]byte +var z14132 [1 << 17]byte +var z14133 [1 << 17]byte +var z14134 [1 << 17]byte +var z14135 [1 << 17]byte +var z14136 [1 << 17]byte +var z14137 [1 << 17]byte +var z14138 [1 << 17]byte +var z14139 [1 << 17]byte +var z14140 [1 << 17]byte +var z14141 [1 << 17]byte +var z14142 [1 << 17]byte +var z14143 [1 << 17]byte +var z14144 [1 << 17]byte +var z14145 [1 << 17]byte +var z14146 [1 << 17]byte +var z14147 [1 << 17]byte +var z14148 [1 << 17]byte +var z14149 [1 << 17]byte +var z14150 [1 << 17]byte +var z14151 [1 << 17]byte +var z14152 [1 << 17]byte +var z14153 [1 << 17]byte +var z14154 [1 << 17]byte +var z14155 [1 << 17]byte +var z14156 [1 << 17]byte +var z14157 [1 << 17]byte +var z14158 [1 << 17]byte +var z14159 [1 << 17]byte +var z14160 [1 << 17]byte +var z14161 [1 << 17]byte +var z14162 [1 << 17]byte +var z14163 [1 << 17]byte +var z14164 [1 << 17]byte +var z14165 [1 << 17]byte +var z14166 [1 << 17]byte +var z14167 [1 << 17]byte +var z14168 [1 << 17]byte +var z14169 [1 << 17]byte +var z14170 [1 << 17]byte +var z14171 [1 << 17]byte +var z14172 [1 << 17]byte +var z14173 [1 << 17]byte +var z14174 [1 << 17]byte +var z14175 [1 << 17]byte +var z14176 [1 << 17]byte +var z14177 [1 << 17]byte +var z14178 [1 << 17]byte +var z14179 [1 << 17]byte +var z14180 [1 << 17]byte +var z14181 [1 << 17]byte +var z14182 [1 << 17]byte +var z14183 [1 << 17]byte +var z14184 [1 << 17]byte +var z14185 [1 << 17]byte +var z14186 [1 << 17]byte +var z14187 [1 << 17]byte +var z14188 [1 << 17]byte +var z14189 [1 << 17]byte +var z14190 [1 << 17]byte +var z14191 [1 << 17]byte +var z14192 [1 << 17]byte +var z14193 [1 << 17]byte +var z14194 [1 << 17]byte +var z14195 [1 << 17]byte +var z14196 [1 << 17]byte +var z14197 [1 << 17]byte +var z14198 [1 << 17]byte +var z14199 [1 << 17]byte +var z14200 [1 << 17]byte +var z14201 [1 << 17]byte +var z14202 [1 << 17]byte +var z14203 [1 << 17]byte +var z14204 [1 << 17]byte +var z14205 [1 << 17]byte +var z14206 [1 << 17]byte +var z14207 [1 << 17]byte +var z14208 [1 << 17]byte +var z14209 [1 << 17]byte +var z14210 [1 << 17]byte +var z14211 [1 << 17]byte +var z14212 [1 << 17]byte +var z14213 [1 << 17]byte +var z14214 [1 << 17]byte +var z14215 [1 << 17]byte +var z14216 [1 << 17]byte +var z14217 [1 << 17]byte +var z14218 [1 << 17]byte +var z14219 [1 << 17]byte +var z14220 [1 << 17]byte +var z14221 [1 << 17]byte +var z14222 [1 << 17]byte +var z14223 [1 << 17]byte +var z14224 [1 << 17]byte +var z14225 [1 << 17]byte +var z14226 [1 << 17]byte +var z14227 [1 << 17]byte +var z14228 [1 << 17]byte +var z14229 [1 << 17]byte +var z14230 [1 << 17]byte +var z14231 [1 << 17]byte +var z14232 [1 << 17]byte +var z14233 [1 << 17]byte +var z14234 [1 << 17]byte +var z14235 [1 << 17]byte +var z14236 [1 << 17]byte +var z14237 [1 << 17]byte +var z14238 [1 << 17]byte +var z14239 [1 << 17]byte +var z14240 [1 << 17]byte +var z14241 [1 << 17]byte +var z14242 [1 << 17]byte +var z14243 [1 << 17]byte +var z14244 [1 << 17]byte +var z14245 [1 << 17]byte +var z14246 [1 << 17]byte +var z14247 [1 << 17]byte +var z14248 [1 << 17]byte +var z14249 [1 << 17]byte +var z14250 [1 << 17]byte +var z14251 [1 << 17]byte +var z14252 [1 << 17]byte +var z14253 [1 << 17]byte +var z14254 [1 << 17]byte +var z14255 [1 << 17]byte +var z14256 [1 << 17]byte +var z14257 [1 << 17]byte +var z14258 [1 << 17]byte +var z14259 [1 << 17]byte +var z14260 [1 << 17]byte +var z14261 [1 << 17]byte +var z14262 [1 << 17]byte +var z14263 [1 << 17]byte +var z14264 [1 << 17]byte +var z14265 [1 << 17]byte +var z14266 [1 << 17]byte +var z14267 [1 << 17]byte +var z14268 [1 << 17]byte +var z14269 [1 << 17]byte +var z14270 [1 << 17]byte +var z14271 [1 << 17]byte +var z14272 [1 << 17]byte +var z14273 [1 << 17]byte +var z14274 [1 << 17]byte +var z14275 [1 << 17]byte +var z14276 [1 << 17]byte +var z14277 [1 << 17]byte +var z14278 [1 << 17]byte +var z14279 [1 << 17]byte +var z14280 [1 << 17]byte +var z14281 [1 << 17]byte +var z14282 [1 << 17]byte +var z14283 [1 << 17]byte +var z14284 [1 << 17]byte +var z14285 [1 << 17]byte +var z14286 [1 << 17]byte +var z14287 [1 << 17]byte +var z14288 [1 << 17]byte +var z14289 [1 << 17]byte +var z14290 [1 << 17]byte +var z14291 [1 << 17]byte +var z14292 [1 << 17]byte +var z14293 [1 << 17]byte +var z14294 [1 << 17]byte +var z14295 [1 << 17]byte +var z14296 [1 << 17]byte +var z14297 [1 << 17]byte +var z14298 [1 << 17]byte +var z14299 [1 << 17]byte +var z14300 [1 << 17]byte +var z14301 [1 << 17]byte +var z14302 [1 << 17]byte +var z14303 [1 << 17]byte +var z14304 [1 << 17]byte +var z14305 [1 << 17]byte +var z14306 [1 << 17]byte +var z14307 [1 << 17]byte +var z14308 [1 << 17]byte +var z14309 [1 << 17]byte +var z14310 [1 << 17]byte +var z14311 [1 << 17]byte +var z14312 [1 << 17]byte +var z14313 [1 << 17]byte +var z14314 [1 << 17]byte +var z14315 [1 << 17]byte +var z14316 [1 << 17]byte +var z14317 [1 << 17]byte +var z14318 [1 << 17]byte +var z14319 [1 << 17]byte +var z14320 [1 << 17]byte +var z14321 [1 << 17]byte +var z14322 [1 << 17]byte +var z14323 [1 << 17]byte +var z14324 [1 << 17]byte +var z14325 [1 << 17]byte +var z14326 [1 << 17]byte +var z14327 [1 << 17]byte +var z14328 [1 << 17]byte +var z14329 [1 << 17]byte +var z14330 [1 << 17]byte +var z14331 [1 << 17]byte +var z14332 [1 << 17]byte +var z14333 [1 << 17]byte +var z14334 [1 << 17]byte +var z14335 [1 << 17]byte +var z14336 [1 << 17]byte +var z14337 [1 << 17]byte +var z14338 [1 << 17]byte +var z14339 [1 << 17]byte +var z14340 [1 << 17]byte +var z14341 [1 << 17]byte +var z14342 [1 << 17]byte +var z14343 [1 << 17]byte +var z14344 [1 << 17]byte +var z14345 [1 << 17]byte +var z14346 [1 << 17]byte +var z14347 [1 << 17]byte +var z14348 [1 << 17]byte +var z14349 [1 << 17]byte +var z14350 [1 << 17]byte +var z14351 [1 << 17]byte +var z14352 [1 << 17]byte +var z14353 [1 << 17]byte +var z14354 [1 << 17]byte +var z14355 [1 << 17]byte +var z14356 [1 << 17]byte +var z14357 [1 << 17]byte +var z14358 [1 << 17]byte +var z14359 [1 << 17]byte +var z14360 [1 << 17]byte +var z14361 [1 << 17]byte +var z14362 [1 << 17]byte +var z14363 [1 << 17]byte +var z14364 [1 << 17]byte +var z14365 [1 << 17]byte +var z14366 [1 << 17]byte +var z14367 [1 << 17]byte +var z14368 [1 << 17]byte +var z14369 [1 << 17]byte +var z14370 [1 << 17]byte +var z14371 [1 << 17]byte +var z14372 [1 << 17]byte +var z14373 [1 << 17]byte +var z14374 [1 << 17]byte +var z14375 [1 << 17]byte +var z14376 [1 << 17]byte +var z14377 [1 << 17]byte +var z14378 [1 << 17]byte +var z14379 [1 << 17]byte +var z14380 [1 << 17]byte +var z14381 [1 << 17]byte +var z14382 [1 << 17]byte +var z14383 [1 << 17]byte +var z14384 [1 << 17]byte +var z14385 [1 << 17]byte +var z14386 [1 << 17]byte +var z14387 [1 << 17]byte +var z14388 [1 << 17]byte +var z14389 [1 << 17]byte +var z14390 [1 << 17]byte +var z14391 [1 << 17]byte +var z14392 [1 << 17]byte +var z14393 [1 << 17]byte +var z14394 [1 << 17]byte +var z14395 [1 << 17]byte +var z14396 [1 << 17]byte +var z14397 [1 << 17]byte +var z14398 [1 << 17]byte +var z14399 [1 << 17]byte +var z14400 [1 << 17]byte +var z14401 [1 << 17]byte +var z14402 [1 << 17]byte +var z14403 [1 << 17]byte +var z14404 [1 << 17]byte +var z14405 [1 << 17]byte +var z14406 [1 << 17]byte +var z14407 [1 << 17]byte +var z14408 [1 << 17]byte +var z14409 [1 << 17]byte +var z14410 [1 << 17]byte +var z14411 [1 << 17]byte +var z14412 [1 << 17]byte +var z14413 [1 << 17]byte +var z14414 [1 << 17]byte +var z14415 [1 << 17]byte +var z14416 [1 << 17]byte +var z14417 [1 << 17]byte +var z14418 [1 << 17]byte +var z14419 [1 << 17]byte +var z14420 [1 << 17]byte +var z14421 [1 << 17]byte +var z14422 [1 << 17]byte +var z14423 [1 << 17]byte +var z14424 [1 << 17]byte +var z14425 [1 << 17]byte +var z14426 [1 << 17]byte +var z14427 [1 << 17]byte +var z14428 [1 << 17]byte +var z14429 [1 << 17]byte +var z14430 [1 << 17]byte +var z14431 [1 << 17]byte +var z14432 [1 << 17]byte +var z14433 [1 << 17]byte +var z14434 [1 << 17]byte +var z14435 [1 << 17]byte +var z14436 [1 << 17]byte +var z14437 [1 << 17]byte +var z14438 [1 << 17]byte +var z14439 [1 << 17]byte +var z14440 [1 << 17]byte +var z14441 [1 << 17]byte +var z14442 [1 << 17]byte +var z14443 [1 << 17]byte +var z14444 [1 << 17]byte +var z14445 [1 << 17]byte +var z14446 [1 << 17]byte +var z14447 [1 << 17]byte +var z14448 [1 << 17]byte +var z14449 [1 << 17]byte +var z14450 [1 << 17]byte +var z14451 [1 << 17]byte +var z14452 [1 << 17]byte +var z14453 [1 << 17]byte +var z14454 [1 << 17]byte +var z14455 [1 << 17]byte +var z14456 [1 << 17]byte +var z14457 [1 << 17]byte +var z14458 [1 << 17]byte +var z14459 [1 << 17]byte +var z14460 [1 << 17]byte +var z14461 [1 << 17]byte +var z14462 [1 << 17]byte +var z14463 [1 << 17]byte +var z14464 [1 << 17]byte +var z14465 [1 << 17]byte +var z14466 [1 << 17]byte +var z14467 [1 << 17]byte +var z14468 [1 << 17]byte +var z14469 [1 << 17]byte +var z14470 [1 << 17]byte +var z14471 [1 << 17]byte +var z14472 [1 << 17]byte +var z14473 [1 << 17]byte +var z14474 [1 << 17]byte +var z14475 [1 << 17]byte +var z14476 [1 << 17]byte +var z14477 [1 << 17]byte +var z14478 [1 << 17]byte +var z14479 [1 << 17]byte +var z14480 [1 << 17]byte +var z14481 [1 << 17]byte +var z14482 [1 << 17]byte +var z14483 [1 << 17]byte +var z14484 [1 << 17]byte +var z14485 [1 << 17]byte +var z14486 [1 << 17]byte +var z14487 [1 << 17]byte +var z14488 [1 << 17]byte +var z14489 [1 << 17]byte +var z14490 [1 << 17]byte +var z14491 [1 << 17]byte +var z14492 [1 << 17]byte +var z14493 [1 << 17]byte +var z14494 [1 << 17]byte +var z14495 [1 << 17]byte +var z14496 [1 << 17]byte +var z14497 [1 << 17]byte +var z14498 [1 << 17]byte +var z14499 [1 << 17]byte +var z14500 [1 << 17]byte +var z14501 [1 << 17]byte +var z14502 [1 << 17]byte +var z14503 [1 << 17]byte +var z14504 [1 << 17]byte +var z14505 [1 << 17]byte +var z14506 [1 << 17]byte +var z14507 [1 << 17]byte +var z14508 [1 << 17]byte +var z14509 [1 << 17]byte +var z14510 [1 << 17]byte +var z14511 [1 << 17]byte +var z14512 [1 << 17]byte +var z14513 [1 << 17]byte +var z14514 [1 << 17]byte +var z14515 [1 << 17]byte +var z14516 [1 << 17]byte +var z14517 [1 << 17]byte +var z14518 [1 << 17]byte +var z14519 [1 << 17]byte +var z14520 [1 << 17]byte +var z14521 [1 << 17]byte +var z14522 [1 << 17]byte +var z14523 [1 << 17]byte +var z14524 [1 << 17]byte +var z14525 [1 << 17]byte +var z14526 [1 << 17]byte +var z14527 [1 << 17]byte +var z14528 [1 << 17]byte +var z14529 [1 << 17]byte +var z14530 [1 << 17]byte +var z14531 [1 << 17]byte +var z14532 [1 << 17]byte +var z14533 [1 << 17]byte +var z14534 [1 << 17]byte +var z14535 [1 << 17]byte +var z14536 [1 << 17]byte +var z14537 [1 << 17]byte +var z14538 [1 << 17]byte +var z14539 [1 << 17]byte +var z14540 [1 << 17]byte +var z14541 [1 << 17]byte +var z14542 [1 << 17]byte +var z14543 [1 << 17]byte +var z14544 [1 << 17]byte +var z14545 [1 << 17]byte +var z14546 [1 << 17]byte +var z14547 [1 << 17]byte +var z14548 [1 << 17]byte +var z14549 [1 << 17]byte +var z14550 [1 << 17]byte +var z14551 [1 << 17]byte +var z14552 [1 << 17]byte +var z14553 [1 << 17]byte +var z14554 [1 << 17]byte +var z14555 [1 << 17]byte +var z14556 [1 << 17]byte +var z14557 [1 << 17]byte +var z14558 [1 << 17]byte +var z14559 [1 << 17]byte +var z14560 [1 << 17]byte +var z14561 [1 << 17]byte +var z14562 [1 << 17]byte +var z14563 [1 << 17]byte +var z14564 [1 << 17]byte +var z14565 [1 << 17]byte +var z14566 [1 << 17]byte +var z14567 [1 << 17]byte +var z14568 [1 << 17]byte +var z14569 [1 << 17]byte +var z14570 [1 << 17]byte +var z14571 [1 << 17]byte +var z14572 [1 << 17]byte +var z14573 [1 << 17]byte +var z14574 [1 << 17]byte +var z14575 [1 << 17]byte +var z14576 [1 << 17]byte +var z14577 [1 << 17]byte +var z14578 [1 << 17]byte +var z14579 [1 << 17]byte +var z14580 [1 << 17]byte +var z14581 [1 << 17]byte +var z14582 [1 << 17]byte +var z14583 [1 << 17]byte +var z14584 [1 << 17]byte +var z14585 [1 << 17]byte +var z14586 [1 << 17]byte +var z14587 [1 << 17]byte +var z14588 [1 << 17]byte +var z14589 [1 << 17]byte +var z14590 [1 << 17]byte +var z14591 [1 << 17]byte +var z14592 [1 << 17]byte +var z14593 [1 << 17]byte +var z14594 [1 << 17]byte +var z14595 [1 << 17]byte +var z14596 [1 << 17]byte +var z14597 [1 << 17]byte +var z14598 [1 << 17]byte +var z14599 [1 << 17]byte +var z14600 [1 << 17]byte +var z14601 [1 << 17]byte +var z14602 [1 << 17]byte +var z14603 [1 << 17]byte +var z14604 [1 << 17]byte +var z14605 [1 << 17]byte +var z14606 [1 << 17]byte +var z14607 [1 << 17]byte +var z14608 [1 << 17]byte +var z14609 [1 << 17]byte +var z14610 [1 << 17]byte +var z14611 [1 << 17]byte +var z14612 [1 << 17]byte +var z14613 [1 << 17]byte +var z14614 [1 << 17]byte +var z14615 [1 << 17]byte +var z14616 [1 << 17]byte +var z14617 [1 << 17]byte +var z14618 [1 << 17]byte +var z14619 [1 << 17]byte +var z14620 [1 << 17]byte +var z14621 [1 << 17]byte +var z14622 [1 << 17]byte +var z14623 [1 << 17]byte +var z14624 [1 << 17]byte +var z14625 [1 << 17]byte +var z14626 [1 << 17]byte +var z14627 [1 << 17]byte +var z14628 [1 << 17]byte +var z14629 [1 << 17]byte +var z14630 [1 << 17]byte +var z14631 [1 << 17]byte +var z14632 [1 << 17]byte +var z14633 [1 << 17]byte +var z14634 [1 << 17]byte +var z14635 [1 << 17]byte +var z14636 [1 << 17]byte +var z14637 [1 << 17]byte +var z14638 [1 << 17]byte +var z14639 [1 << 17]byte +var z14640 [1 << 17]byte +var z14641 [1 << 17]byte +var z14642 [1 << 17]byte +var z14643 [1 << 17]byte +var z14644 [1 << 17]byte +var z14645 [1 << 17]byte +var z14646 [1 << 17]byte +var z14647 [1 << 17]byte +var z14648 [1 << 17]byte +var z14649 [1 << 17]byte +var z14650 [1 << 17]byte +var z14651 [1 << 17]byte +var z14652 [1 << 17]byte +var z14653 [1 << 17]byte +var z14654 [1 << 17]byte +var z14655 [1 << 17]byte +var z14656 [1 << 17]byte +var z14657 [1 << 17]byte +var z14658 [1 << 17]byte +var z14659 [1 << 17]byte +var z14660 [1 << 17]byte +var z14661 [1 << 17]byte +var z14662 [1 << 17]byte +var z14663 [1 << 17]byte +var z14664 [1 << 17]byte +var z14665 [1 << 17]byte +var z14666 [1 << 17]byte +var z14667 [1 << 17]byte +var z14668 [1 << 17]byte +var z14669 [1 << 17]byte +var z14670 [1 << 17]byte +var z14671 [1 << 17]byte +var z14672 [1 << 17]byte +var z14673 [1 << 17]byte +var z14674 [1 << 17]byte +var z14675 [1 << 17]byte +var z14676 [1 << 17]byte +var z14677 [1 << 17]byte +var z14678 [1 << 17]byte +var z14679 [1 << 17]byte +var z14680 [1 << 17]byte +var z14681 [1 << 17]byte +var z14682 [1 << 17]byte +var z14683 [1 << 17]byte +var z14684 [1 << 17]byte +var z14685 [1 << 17]byte +var z14686 [1 << 17]byte +var z14687 [1 << 17]byte +var z14688 [1 << 17]byte +var z14689 [1 << 17]byte +var z14690 [1 << 17]byte +var z14691 [1 << 17]byte +var z14692 [1 << 17]byte +var z14693 [1 << 17]byte +var z14694 [1 << 17]byte +var z14695 [1 << 17]byte +var z14696 [1 << 17]byte +var z14697 [1 << 17]byte +var z14698 [1 << 17]byte +var z14699 [1 << 17]byte +var z14700 [1 << 17]byte +var z14701 [1 << 17]byte +var z14702 [1 << 17]byte +var z14703 [1 << 17]byte +var z14704 [1 << 17]byte +var z14705 [1 << 17]byte +var z14706 [1 << 17]byte +var z14707 [1 << 17]byte +var z14708 [1 << 17]byte +var z14709 [1 << 17]byte +var z14710 [1 << 17]byte +var z14711 [1 << 17]byte +var z14712 [1 << 17]byte +var z14713 [1 << 17]byte +var z14714 [1 << 17]byte +var z14715 [1 << 17]byte +var z14716 [1 << 17]byte +var z14717 [1 << 17]byte +var z14718 [1 << 17]byte +var z14719 [1 << 17]byte +var z14720 [1 << 17]byte +var z14721 [1 << 17]byte +var z14722 [1 << 17]byte +var z14723 [1 << 17]byte +var z14724 [1 << 17]byte +var z14725 [1 << 17]byte +var z14726 [1 << 17]byte +var z14727 [1 << 17]byte +var z14728 [1 << 17]byte +var z14729 [1 << 17]byte +var z14730 [1 << 17]byte +var z14731 [1 << 17]byte +var z14732 [1 << 17]byte +var z14733 [1 << 17]byte +var z14734 [1 << 17]byte +var z14735 [1 << 17]byte +var z14736 [1 << 17]byte +var z14737 [1 << 17]byte +var z14738 [1 << 17]byte +var z14739 [1 << 17]byte +var z14740 [1 << 17]byte +var z14741 [1 << 17]byte +var z14742 [1 << 17]byte +var z14743 [1 << 17]byte +var z14744 [1 << 17]byte +var z14745 [1 << 17]byte +var z14746 [1 << 17]byte +var z14747 [1 << 17]byte +var z14748 [1 << 17]byte +var z14749 [1 << 17]byte +var z14750 [1 << 17]byte +var z14751 [1 << 17]byte +var z14752 [1 << 17]byte +var z14753 [1 << 17]byte +var z14754 [1 << 17]byte +var z14755 [1 << 17]byte +var z14756 [1 << 17]byte +var z14757 [1 << 17]byte +var z14758 [1 << 17]byte +var z14759 [1 << 17]byte +var z14760 [1 << 17]byte +var z14761 [1 << 17]byte +var z14762 [1 << 17]byte +var z14763 [1 << 17]byte +var z14764 [1 << 17]byte +var z14765 [1 << 17]byte +var z14766 [1 << 17]byte +var z14767 [1 << 17]byte +var z14768 [1 << 17]byte +var z14769 [1 << 17]byte +var z14770 [1 << 17]byte +var z14771 [1 << 17]byte +var z14772 [1 << 17]byte +var z14773 [1 << 17]byte +var z14774 [1 << 17]byte +var z14775 [1 << 17]byte +var z14776 [1 << 17]byte +var z14777 [1 << 17]byte +var z14778 [1 << 17]byte +var z14779 [1 << 17]byte +var z14780 [1 << 17]byte +var z14781 [1 << 17]byte +var z14782 [1 << 17]byte +var z14783 [1 << 17]byte +var z14784 [1 << 17]byte +var z14785 [1 << 17]byte +var z14786 [1 << 17]byte +var z14787 [1 << 17]byte +var z14788 [1 << 17]byte +var z14789 [1 << 17]byte +var z14790 [1 << 17]byte +var z14791 [1 << 17]byte +var z14792 [1 << 17]byte +var z14793 [1 << 17]byte +var z14794 [1 << 17]byte +var z14795 [1 << 17]byte +var z14796 [1 << 17]byte +var z14797 [1 << 17]byte +var z14798 [1 << 17]byte +var z14799 [1 << 17]byte +var z14800 [1 << 17]byte +var z14801 [1 << 17]byte +var z14802 [1 << 17]byte +var z14803 [1 << 17]byte +var z14804 [1 << 17]byte +var z14805 [1 << 17]byte +var z14806 [1 << 17]byte +var z14807 [1 << 17]byte +var z14808 [1 << 17]byte +var z14809 [1 << 17]byte +var z14810 [1 << 17]byte +var z14811 [1 << 17]byte +var z14812 [1 << 17]byte +var z14813 [1 << 17]byte +var z14814 [1 << 17]byte +var z14815 [1 << 17]byte +var z14816 [1 << 17]byte +var z14817 [1 << 17]byte +var z14818 [1 << 17]byte +var z14819 [1 << 17]byte +var z14820 [1 << 17]byte +var z14821 [1 << 17]byte +var z14822 [1 << 17]byte +var z14823 [1 << 17]byte +var z14824 [1 << 17]byte +var z14825 [1 << 17]byte +var z14826 [1 << 17]byte +var z14827 [1 << 17]byte +var z14828 [1 << 17]byte +var z14829 [1 << 17]byte +var z14830 [1 << 17]byte +var z14831 [1 << 17]byte +var z14832 [1 << 17]byte +var z14833 [1 << 17]byte +var z14834 [1 << 17]byte +var z14835 [1 << 17]byte +var z14836 [1 << 17]byte +var z14837 [1 << 17]byte +var z14838 [1 << 17]byte +var z14839 [1 << 17]byte +var z14840 [1 << 17]byte +var z14841 [1 << 17]byte +var z14842 [1 << 17]byte +var z14843 [1 << 17]byte +var z14844 [1 << 17]byte +var z14845 [1 << 17]byte +var z14846 [1 << 17]byte +var z14847 [1 << 17]byte +var z14848 [1 << 17]byte +var z14849 [1 << 17]byte +var z14850 [1 << 17]byte +var z14851 [1 << 17]byte +var z14852 [1 << 17]byte +var z14853 [1 << 17]byte +var z14854 [1 << 17]byte +var z14855 [1 << 17]byte +var z14856 [1 << 17]byte +var z14857 [1 << 17]byte +var z14858 [1 << 17]byte +var z14859 [1 << 17]byte +var z14860 [1 << 17]byte +var z14861 [1 << 17]byte +var z14862 [1 << 17]byte +var z14863 [1 << 17]byte +var z14864 [1 << 17]byte +var z14865 [1 << 17]byte +var z14866 [1 << 17]byte +var z14867 [1 << 17]byte +var z14868 [1 << 17]byte +var z14869 [1 << 17]byte +var z14870 [1 << 17]byte +var z14871 [1 << 17]byte +var z14872 [1 << 17]byte +var z14873 [1 << 17]byte +var z14874 [1 << 17]byte +var z14875 [1 << 17]byte +var z14876 [1 << 17]byte +var z14877 [1 << 17]byte +var z14878 [1 << 17]byte +var z14879 [1 << 17]byte +var z14880 [1 << 17]byte +var z14881 [1 << 17]byte +var z14882 [1 << 17]byte +var z14883 [1 << 17]byte +var z14884 [1 << 17]byte +var z14885 [1 << 17]byte +var z14886 [1 << 17]byte +var z14887 [1 << 17]byte +var z14888 [1 << 17]byte +var z14889 [1 << 17]byte +var z14890 [1 << 17]byte +var z14891 [1 << 17]byte +var z14892 [1 << 17]byte +var z14893 [1 << 17]byte +var z14894 [1 << 17]byte +var z14895 [1 << 17]byte +var z14896 [1 << 17]byte +var z14897 [1 << 17]byte +var z14898 [1 << 17]byte +var z14899 [1 << 17]byte +var z14900 [1 << 17]byte +var z14901 [1 << 17]byte +var z14902 [1 << 17]byte +var z14903 [1 << 17]byte +var z14904 [1 << 17]byte +var z14905 [1 << 17]byte +var z14906 [1 << 17]byte +var z14907 [1 << 17]byte +var z14908 [1 << 17]byte +var z14909 [1 << 17]byte +var z14910 [1 << 17]byte +var z14911 [1 << 17]byte +var z14912 [1 << 17]byte +var z14913 [1 << 17]byte +var z14914 [1 << 17]byte +var z14915 [1 << 17]byte +var z14916 [1 << 17]byte +var z14917 [1 << 17]byte +var z14918 [1 << 17]byte +var z14919 [1 << 17]byte +var z14920 [1 << 17]byte +var z14921 [1 << 17]byte +var z14922 [1 << 17]byte +var z14923 [1 << 17]byte +var z14924 [1 << 17]byte +var z14925 [1 << 17]byte +var z14926 [1 << 17]byte +var z14927 [1 << 17]byte +var z14928 [1 << 17]byte +var z14929 [1 << 17]byte +var z14930 [1 << 17]byte +var z14931 [1 << 17]byte +var z14932 [1 << 17]byte +var z14933 [1 << 17]byte +var z14934 [1 << 17]byte +var z14935 [1 << 17]byte +var z14936 [1 << 17]byte +var z14937 [1 << 17]byte +var z14938 [1 << 17]byte +var z14939 [1 << 17]byte +var z14940 [1 << 17]byte +var z14941 [1 << 17]byte +var z14942 [1 << 17]byte +var z14943 [1 << 17]byte +var z14944 [1 << 17]byte +var z14945 [1 << 17]byte +var z14946 [1 << 17]byte +var z14947 [1 << 17]byte +var z14948 [1 << 17]byte +var z14949 [1 << 17]byte +var z14950 [1 << 17]byte +var z14951 [1 << 17]byte +var z14952 [1 << 17]byte +var z14953 [1 << 17]byte +var z14954 [1 << 17]byte +var z14955 [1 << 17]byte +var z14956 [1 << 17]byte +var z14957 [1 << 17]byte +var z14958 [1 << 17]byte +var z14959 [1 << 17]byte +var z14960 [1 << 17]byte +var z14961 [1 << 17]byte +var z14962 [1 << 17]byte +var z14963 [1 << 17]byte +var z14964 [1 << 17]byte +var z14965 [1 << 17]byte +var z14966 [1 << 17]byte +var z14967 [1 << 17]byte +var z14968 [1 << 17]byte +var z14969 [1 << 17]byte +var z14970 [1 << 17]byte +var z14971 [1 << 17]byte +var z14972 [1 << 17]byte +var z14973 [1 << 17]byte +var z14974 [1 << 17]byte +var z14975 [1 << 17]byte +var z14976 [1 << 17]byte +var z14977 [1 << 17]byte +var z14978 [1 << 17]byte +var z14979 [1 << 17]byte +var z14980 [1 << 17]byte +var z14981 [1 << 17]byte +var z14982 [1 << 17]byte +var z14983 [1 << 17]byte +var z14984 [1 << 17]byte +var z14985 [1 << 17]byte +var z14986 [1 << 17]byte +var z14987 [1 << 17]byte +var z14988 [1 << 17]byte +var z14989 [1 << 17]byte +var z14990 [1 << 17]byte +var z14991 [1 << 17]byte +var z14992 [1 << 17]byte +var z14993 [1 << 17]byte +var z14994 [1 << 17]byte +var z14995 [1 << 17]byte +var z14996 [1 << 17]byte +var z14997 [1 << 17]byte +var z14998 [1 << 17]byte +var z14999 [1 << 17]byte +var z15000 [1 << 17]byte +var z15001 [1 << 17]byte +var z15002 [1 << 17]byte +var z15003 [1 << 17]byte +var z15004 [1 << 17]byte +var z15005 [1 << 17]byte +var z15006 [1 << 17]byte +var z15007 [1 << 17]byte +var z15008 [1 << 17]byte +var z15009 [1 << 17]byte +var z15010 [1 << 17]byte +var z15011 [1 << 17]byte +var z15012 [1 << 17]byte +var z15013 [1 << 17]byte +var z15014 [1 << 17]byte +var z15015 [1 << 17]byte +var z15016 [1 << 17]byte +var z15017 [1 << 17]byte +var z15018 [1 << 17]byte +var z15019 [1 << 17]byte +var z15020 [1 << 17]byte +var z15021 [1 << 17]byte +var z15022 [1 << 17]byte +var z15023 [1 << 17]byte +var z15024 [1 << 17]byte +var z15025 [1 << 17]byte +var z15026 [1 << 17]byte +var z15027 [1 << 17]byte +var z15028 [1 << 17]byte +var z15029 [1 << 17]byte +var z15030 [1 << 17]byte +var z15031 [1 << 17]byte +var z15032 [1 << 17]byte +var z15033 [1 << 17]byte +var z15034 [1 << 17]byte +var z15035 [1 << 17]byte +var z15036 [1 << 17]byte +var z15037 [1 << 17]byte +var z15038 [1 << 17]byte +var z15039 [1 << 17]byte +var z15040 [1 << 17]byte +var z15041 [1 << 17]byte +var z15042 [1 << 17]byte +var z15043 [1 << 17]byte +var z15044 [1 << 17]byte +var z15045 [1 << 17]byte +var z15046 [1 << 17]byte +var z15047 [1 << 17]byte +var z15048 [1 << 17]byte +var z15049 [1 << 17]byte +var z15050 [1 << 17]byte +var z15051 [1 << 17]byte +var z15052 [1 << 17]byte +var z15053 [1 << 17]byte +var z15054 [1 << 17]byte +var z15055 [1 << 17]byte +var z15056 [1 << 17]byte +var z15057 [1 << 17]byte +var z15058 [1 << 17]byte +var z15059 [1 << 17]byte +var z15060 [1 << 17]byte +var z15061 [1 << 17]byte +var z15062 [1 << 17]byte +var z15063 [1 << 17]byte +var z15064 [1 << 17]byte +var z15065 [1 << 17]byte +var z15066 [1 << 17]byte +var z15067 [1 << 17]byte +var z15068 [1 << 17]byte +var z15069 [1 << 17]byte +var z15070 [1 << 17]byte +var z15071 [1 << 17]byte +var z15072 [1 << 17]byte +var z15073 [1 << 17]byte +var z15074 [1 << 17]byte +var z15075 [1 << 17]byte +var z15076 [1 << 17]byte +var z15077 [1 << 17]byte +var z15078 [1 << 17]byte +var z15079 [1 << 17]byte +var z15080 [1 << 17]byte +var z15081 [1 << 17]byte +var z15082 [1 << 17]byte +var z15083 [1 << 17]byte +var z15084 [1 << 17]byte +var z15085 [1 << 17]byte +var z15086 [1 << 17]byte +var z15087 [1 << 17]byte +var z15088 [1 << 17]byte +var z15089 [1 << 17]byte +var z15090 [1 << 17]byte +var z15091 [1 << 17]byte +var z15092 [1 << 17]byte +var z15093 [1 << 17]byte +var z15094 [1 << 17]byte +var z15095 [1 << 17]byte +var z15096 [1 << 17]byte +var z15097 [1 << 17]byte +var z15098 [1 << 17]byte +var z15099 [1 << 17]byte +var z15100 [1 << 17]byte +var z15101 [1 << 17]byte +var z15102 [1 << 17]byte +var z15103 [1 << 17]byte +var z15104 [1 << 17]byte +var z15105 [1 << 17]byte +var z15106 [1 << 17]byte +var z15107 [1 << 17]byte +var z15108 [1 << 17]byte +var z15109 [1 << 17]byte +var z15110 [1 << 17]byte +var z15111 [1 << 17]byte +var z15112 [1 << 17]byte +var z15113 [1 << 17]byte +var z15114 [1 << 17]byte +var z15115 [1 << 17]byte +var z15116 [1 << 17]byte +var z15117 [1 << 17]byte +var z15118 [1 << 17]byte +var z15119 [1 << 17]byte +var z15120 [1 << 17]byte +var z15121 [1 << 17]byte +var z15122 [1 << 17]byte +var z15123 [1 << 17]byte +var z15124 [1 << 17]byte +var z15125 [1 << 17]byte +var z15126 [1 << 17]byte +var z15127 [1 << 17]byte +var z15128 [1 << 17]byte +var z15129 [1 << 17]byte +var z15130 [1 << 17]byte +var z15131 [1 << 17]byte +var z15132 [1 << 17]byte +var z15133 [1 << 17]byte +var z15134 [1 << 17]byte +var z15135 [1 << 17]byte +var z15136 [1 << 17]byte +var z15137 [1 << 17]byte +var z15138 [1 << 17]byte +var z15139 [1 << 17]byte +var z15140 [1 << 17]byte +var z15141 [1 << 17]byte +var z15142 [1 << 17]byte +var z15143 [1 << 17]byte +var z15144 [1 << 17]byte +var z15145 [1 << 17]byte +var z15146 [1 << 17]byte +var z15147 [1 << 17]byte +var z15148 [1 << 17]byte +var z15149 [1 << 17]byte +var z15150 [1 << 17]byte +var z15151 [1 << 17]byte +var z15152 [1 << 17]byte +var z15153 [1 << 17]byte +var z15154 [1 << 17]byte +var z15155 [1 << 17]byte +var z15156 [1 << 17]byte +var z15157 [1 << 17]byte +var z15158 [1 << 17]byte +var z15159 [1 << 17]byte +var z15160 [1 << 17]byte +var z15161 [1 << 17]byte +var z15162 [1 << 17]byte +var z15163 [1 << 17]byte +var z15164 [1 << 17]byte +var z15165 [1 << 17]byte +var z15166 [1 << 17]byte +var z15167 [1 << 17]byte +var z15168 [1 << 17]byte +var z15169 [1 << 17]byte +var z15170 [1 << 17]byte +var z15171 [1 << 17]byte +var z15172 [1 << 17]byte +var z15173 [1 << 17]byte +var z15174 [1 << 17]byte +var z15175 [1 << 17]byte +var z15176 [1 << 17]byte +var z15177 [1 << 17]byte +var z15178 [1 << 17]byte +var z15179 [1 << 17]byte +var z15180 [1 << 17]byte +var z15181 [1 << 17]byte +var z15182 [1 << 17]byte +var z15183 [1 << 17]byte +var z15184 [1 << 17]byte +var z15185 [1 << 17]byte +var z15186 [1 << 17]byte +var z15187 [1 << 17]byte +var z15188 [1 << 17]byte +var z15189 [1 << 17]byte +var z15190 [1 << 17]byte +var z15191 [1 << 17]byte +var z15192 [1 << 17]byte +var z15193 [1 << 17]byte +var z15194 [1 << 17]byte +var z15195 [1 << 17]byte +var z15196 [1 << 17]byte +var z15197 [1 << 17]byte +var z15198 [1 << 17]byte +var z15199 [1 << 17]byte +var z15200 [1 << 17]byte +var z15201 [1 << 17]byte +var z15202 [1 << 17]byte +var z15203 [1 << 17]byte +var z15204 [1 << 17]byte +var z15205 [1 << 17]byte +var z15206 [1 << 17]byte +var z15207 [1 << 17]byte +var z15208 [1 << 17]byte +var z15209 [1 << 17]byte +var z15210 [1 << 17]byte +var z15211 [1 << 17]byte +var z15212 [1 << 17]byte +var z15213 [1 << 17]byte +var z15214 [1 << 17]byte +var z15215 [1 << 17]byte +var z15216 [1 << 17]byte +var z15217 [1 << 17]byte +var z15218 [1 << 17]byte +var z15219 [1 << 17]byte +var z15220 [1 << 17]byte +var z15221 [1 << 17]byte +var z15222 [1 << 17]byte +var z15223 [1 << 17]byte +var z15224 [1 << 17]byte +var z15225 [1 << 17]byte +var z15226 [1 << 17]byte +var z15227 [1 << 17]byte +var z15228 [1 << 17]byte +var z15229 [1 << 17]byte +var z15230 [1 << 17]byte +var z15231 [1 << 17]byte +var z15232 [1 << 17]byte +var z15233 [1 << 17]byte +var z15234 [1 << 17]byte +var z15235 [1 << 17]byte +var z15236 [1 << 17]byte +var z15237 [1 << 17]byte +var z15238 [1 << 17]byte +var z15239 [1 << 17]byte +var z15240 [1 << 17]byte +var z15241 [1 << 17]byte +var z15242 [1 << 17]byte +var z15243 [1 << 17]byte +var z15244 [1 << 17]byte +var z15245 [1 << 17]byte +var z15246 [1 << 17]byte +var z15247 [1 << 17]byte +var z15248 [1 << 17]byte +var z15249 [1 << 17]byte +var z15250 [1 << 17]byte +var z15251 [1 << 17]byte +var z15252 [1 << 17]byte +var z15253 [1 << 17]byte +var z15254 [1 << 17]byte +var z15255 [1 << 17]byte +var z15256 [1 << 17]byte +var z15257 [1 << 17]byte +var z15258 [1 << 17]byte +var z15259 [1 << 17]byte +var z15260 [1 << 17]byte +var z15261 [1 << 17]byte +var z15262 [1 << 17]byte +var z15263 [1 << 17]byte +var z15264 [1 << 17]byte +var z15265 [1 << 17]byte +var z15266 [1 << 17]byte +var z15267 [1 << 17]byte +var z15268 [1 << 17]byte +var z15269 [1 << 17]byte +var z15270 [1 << 17]byte +var z15271 [1 << 17]byte +var z15272 [1 << 17]byte +var z15273 [1 << 17]byte +var z15274 [1 << 17]byte +var z15275 [1 << 17]byte +var z15276 [1 << 17]byte +var z15277 [1 << 17]byte +var z15278 [1 << 17]byte +var z15279 [1 << 17]byte +var z15280 [1 << 17]byte +var z15281 [1 << 17]byte +var z15282 [1 << 17]byte +var z15283 [1 << 17]byte +var z15284 [1 << 17]byte +var z15285 [1 << 17]byte +var z15286 [1 << 17]byte +var z15287 [1 << 17]byte +var z15288 [1 << 17]byte +var z15289 [1 << 17]byte +var z15290 [1 << 17]byte +var z15291 [1 << 17]byte +var z15292 [1 << 17]byte +var z15293 [1 << 17]byte +var z15294 [1 << 17]byte +var z15295 [1 << 17]byte +var z15296 [1 << 17]byte +var z15297 [1 << 17]byte +var z15298 [1 << 17]byte +var z15299 [1 << 17]byte +var z15300 [1 << 17]byte +var z15301 [1 << 17]byte +var z15302 [1 << 17]byte +var z15303 [1 << 17]byte +var z15304 [1 << 17]byte +var z15305 [1 << 17]byte +var z15306 [1 << 17]byte +var z15307 [1 << 17]byte +var z15308 [1 << 17]byte +var z15309 [1 << 17]byte +var z15310 [1 << 17]byte +var z15311 [1 << 17]byte +var z15312 [1 << 17]byte +var z15313 [1 << 17]byte +var z15314 [1 << 17]byte +var z15315 [1 << 17]byte +var z15316 [1 << 17]byte +var z15317 [1 << 17]byte +var z15318 [1 << 17]byte +var z15319 [1 << 17]byte +var z15320 [1 << 17]byte +var z15321 [1 << 17]byte +var z15322 [1 << 17]byte +var z15323 [1 << 17]byte +var z15324 [1 << 17]byte +var z15325 [1 << 17]byte +var z15326 [1 << 17]byte +var z15327 [1 << 17]byte +var z15328 [1 << 17]byte +var z15329 [1 << 17]byte +var z15330 [1 << 17]byte +var z15331 [1 << 17]byte +var z15332 [1 << 17]byte +var z15333 [1 << 17]byte +var z15334 [1 << 17]byte +var z15335 [1 << 17]byte +var z15336 [1 << 17]byte +var z15337 [1 << 17]byte +var z15338 [1 << 17]byte +var z15339 [1 << 17]byte +var z15340 [1 << 17]byte +var z15341 [1 << 17]byte +var z15342 [1 << 17]byte +var z15343 [1 << 17]byte +var z15344 [1 << 17]byte +var z15345 [1 << 17]byte +var z15346 [1 << 17]byte +var z15347 [1 << 17]byte +var z15348 [1 << 17]byte +var z15349 [1 << 17]byte +var z15350 [1 << 17]byte +var z15351 [1 << 17]byte +var z15352 [1 << 17]byte +var z15353 [1 << 17]byte +var z15354 [1 << 17]byte +var z15355 [1 << 17]byte +var z15356 [1 << 17]byte +var z15357 [1 << 17]byte +var z15358 [1 << 17]byte +var z15359 [1 << 17]byte +var z15360 [1 << 17]byte +var z15361 [1 << 17]byte +var z15362 [1 << 17]byte +var z15363 [1 << 17]byte +var z15364 [1 << 17]byte +var z15365 [1 << 17]byte +var z15366 [1 << 17]byte +var z15367 [1 << 17]byte +var z15368 [1 << 17]byte +var z15369 [1 << 17]byte +var z15370 [1 << 17]byte +var z15371 [1 << 17]byte +var z15372 [1 << 17]byte +var z15373 [1 << 17]byte +var z15374 [1 << 17]byte +var z15375 [1 << 17]byte +var z15376 [1 << 17]byte +var z15377 [1 << 17]byte +var z15378 [1 << 17]byte +var z15379 [1 << 17]byte +var z15380 [1 << 17]byte +var z15381 [1 << 17]byte +var z15382 [1 << 17]byte +var z15383 [1 << 17]byte +var z15384 [1 << 17]byte +var z15385 [1 << 17]byte +var z15386 [1 << 17]byte +var z15387 [1 << 17]byte +var z15388 [1 << 17]byte +var z15389 [1 << 17]byte +var z15390 [1 << 17]byte +var z15391 [1 << 17]byte +var z15392 [1 << 17]byte +var z15393 [1 << 17]byte +var z15394 [1 << 17]byte +var z15395 [1 << 17]byte +var z15396 [1 << 17]byte +var z15397 [1 << 17]byte +var z15398 [1 << 17]byte +var z15399 [1 << 17]byte +var z15400 [1 << 17]byte +var z15401 [1 << 17]byte +var z15402 [1 << 17]byte +var z15403 [1 << 17]byte +var z15404 [1 << 17]byte +var z15405 [1 << 17]byte +var z15406 [1 << 17]byte +var z15407 [1 << 17]byte +var z15408 [1 << 17]byte +var z15409 [1 << 17]byte +var z15410 [1 << 17]byte +var z15411 [1 << 17]byte +var z15412 [1 << 17]byte +var z15413 [1 << 17]byte +var z15414 [1 << 17]byte +var z15415 [1 << 17]byte +var z15416 [1 << 17]byte +var z15417 [1 << 17]byte +var z15418 [1 << 17]byte +var z15419 [1 << 17]byte +var z15420 [1 << 17]byte +var z15421 [1 << 17]byte +var z15422 [1 << 17]byte +var z15423 [1 << 17]byte +var z15424 [1 << 17]byte +var z15425 [1 << 17]byte +var z15426 [1 << 17]byte +var z15427 [1 << 17]byte +var z15428 [1 << 17]byte +var z15429 [1 << 17]byte +var z15430 [1 << 17]byte +var z15431 [1 << 17]byte +var z15432 [1 << 17]byte +var z15433 [1 << 17]byte +var z15434 [1 << 17]byte +var z15435 [1 << 17]byte +var z15436 [1 << 17]byte +var z15437 [1 << 17]byte +var z15438 [1 << 17]byte +var z15439 [1 << 17]byte +var z15440 [1 << 17]byte +var z15441 [1 << 17]byte +var z15442 [1 << 17]byte +var z15443 [1 << 17]byte +var z15444 [1 << 17]byte +var z15445 [1 << 17]byte +var z15446 [1 << 17]byte +var z15447 [1 << 17]byte +var z15448 [1 << 17]byte +var z15449 [1 << 17]byte +var z15450 [1 << 17]byte +var z15451 [1 << 17]byte +var z15452 [1 << 17]byte +var z15453 [1 << 17]byte +var z15454 [1 << 17]byte +var z15455 [1 << 17]byte +var z15456 [1 << 17]byte +var z15457 [1 << 17]byte +var z15458 [1 << 17]byte +var z15459 [1 << 17]byte +var z15460 [1 << 17]byte +var z15461 [1 << 17]byte +var z15462 [1 << 17]byte +var z15463 [1 << 17]byte +var z15464 [1 << 17]byte +var z15465 [1 << 17]byte +var z15466 [1 << 17]byte +var z15467 [1 << 17]byte +var z15468 [1 << 17]byte +var z15469 [1 << 17]byte +var z15470 [1 << 17]byte +var z15471 [1 << 17]byte +var z15472 [1 << 17]byte +var z15473 [1 << 17]byte +var z15474 [1 << 17]byte +var z15475 [1 << 17]byte +var z15476 [1 << 17]byte +var z15477 [1 << 17]byte +var z15478 [1 << 17]byte +var z15479 [1 << 17]byte +var z15480 [1 << 17]byte +var z15481 [1 << 17]byte +var z15482 [1 << 17]byte +var z15483 [1 << 17]byte +var z15484 [1 << 17]byte +var z15485 [1 << 17]byte +var z15486 [1 << 17]byte +var z15487 [1 << 17]byte +var z15488 [1 << 17]byte +var z15489 [1 << 17]byte +var z15490 [1 << 17]byte +var z15491 [1 << 17]byte +var z15492 [1 << 17]byte +var z15493 [1 << 17]byte +var z15494 [1 << 17]byte +var z15495 [1 << 17]byte +var z15496 [1 << 17]byte +var z15497 [1 << 17]byte +var z15498 [1 << 17]byte +var z15499 [1 << 17]byte +var z15500 [1 << 17]byte +var z15501 [1 << 17]byte +var z15502 [1 << 17]byte +var z15503 [1 << 17]byte +var z15504 [1 << 17]byte +var z15505 [1 << 17]byte +var z15506 [1 << 17]byte +var z15507 [1 << 17]byte +var z15508 [1 << 17]byte +var z15509 [1 << 17]byte +var z15510 [1 << 17]byte +var z15511 [1 << 17]byte +var z15512 [1 << 17]byte +var z15513 [1 << 17]byte +var z15514 [1 << 17]byte +var z15515 [1 << 17]byte +var z15516 [1 << 17]byte +var z15517 [1 << 17]byte +var z15518 [1 << 17]byte +var z15519 [1 << 17]byte +var z15520 [1 << 17]byte +var z15521 [1 << 17]byte +var z15522 [1 << 17]byte +var z15523 [1 << 17]byte +var z15524 [1 << 17]byte +var z15525 [1 << 17]byte +var z15526 [1 << 17]byte +var z15527 [1 << 17]byte +var z15528 [1 << 17]byte +var z15529 [1 << 17]byte +var z15530 [1 << 17]byte +var z15531 [1 << 17]byte +var z15532 [1 << 17]byte +var z15533 [1 << 17]byte +var z15534 [1 << 17]byte +var z15535 [1 << 17]byte +var z15536 [1 << 17]byte +var z15537 [1 << 17]byte +var z15538 [1 << 17]byte +var z15539 [1 << 17]byte +var z15540 [1 << 17]byte +var z15541 [1 << 17]byte +var z15542 [1 << 17]byte +var z15543 [1 << 17]byte +var z15544 [1 << 17]byte +var z15545 [1 << 17]byte +var z15546 [1 << 17]byte +var z15547 [1 << 17]byte +var z15548 [1 << 17]byte +var z15549 [1 << 17]byte +var z15550 [1 << 17]byte +var z15551 [1 << 17]byte +var z15552 [1 << 17]byte +var z15553 [1 << 17]byte +var z15554 [1 << 17]byte +var z15555 [1 << 17]byte +var z15556 [1 << 17]byte +var z15557 [1 << 17]byte +var z15558 [1 << 17]byte +var z15559 [1 << 17]byte +var z15560 [1 << 17]byte +var z15561 [1 << 17]byte +var z15562 [1 << 17]byte +var z15563 [1 << 17]byte +var z15564 [1 << 17]byte +var z15565 [1 << 17]byte +var z15566 [1 << 17]byte +var z15567 [1 << 17]byte +var z15568 [1 << 17]byte +var z15569 [1 << 17]byte +var z15570 [1 << 17]byte +var z15571 [1 << 17]byte +var z15572 [1 << 17]byte +var z15573 [1 << 17]byte +var z15574 [1 << 17]byte +var z15575 [1 << 17]byte +var z15576 [1 << 17]byte +var z15577 [1 << 17]byte +var z15578 [1 << 17]byte +var z15579 [1 << 17]byte +var z15580 [1 << 17]byte +var z15581 [1 << 17]byte +var z15582 [1 << 17]byte +var z15583 [1 << 17]byte +var z15584 [1 << 17]byte +var z15585 [1 << 17]byte +var z15586 [1 << 17]byte +var z15587 [1 << 17]byte +var z15588 [1 << 17]byte +var z15589 [1 << 17]byte +var z15590 [1 << 17]byte +var z15591 [1 << 17]byte +var z15592 [1 << 17]byte +var z15593 [1 << 17]byte +var z15594 [1 << 17]byte +var z15595 [1 << 17]byte +var z15596 [1 << 17]byte +var z15597 [1 << 17]byte +var z15598 [1 << 17]byte +var z15599 [1 << 17]byte +var z15600 [1 << 17]byte +var z15601 [1 << 17]byte +var z15602 [1 << 17]byte +var z15603 [1 << 17]byte +var z15604 [1 << 17]byte +var z15605 [1 << 17]byte +var z15606 [1 << 17]byte +var z15607 [1 << 17]byte +var z15608 [1 << 17]byte +var z15609 [1 << 17]byte +var z15610 [1 << 17]byte +var z15611 [1 << 17]byte +var z15612 [1 << 17]byte +var z15613 [1 << 17]byte +var z15614 [1 << 17]byte +var z15615 [1 << 17]byte +var z15616 [1 << 17]byte +var z15617 [1 << 17]byte +var z15618 [1 << 17]byte +var z15619 [1 << 17]byte +var z15620 [1 << 17]byte +var z15621 [1 << 17]byte +var z15622 [1 << 17]byte +var z15623 [1 << 17]byte +var z15624 [1 << 17]byte +var z15625 [1 << 17]byte +var z15626 [1 << 17]byte +var z15627 [1 << 17]byte +var z15628 [1 << 17]byte +var z15629 [1 << 17]byte +var z15630 [1 << 17]byte +var z15631 [1 << 17]byte +var z15632 [1 << 17]byte +var z15633 [1 << 17]byte +var z15634 [1 << 17]byte +var z15635 [1 << 17]byte +var z15636 [1 << 17]byte +var z15637 [1 << 17]byte +var z15638 [1 << 17]byte +var z15639 [1 << 17]byte +var z15640 [1 << 17]byte +var z15641 [1 << 17]byte +var z15642 [1 << 17]byte +var z15643 [1 << 17]byte +var z15644 [1 << 17]byte +var z15645 [1 << 17]byte +var z15646 [1 << 17]byte +var z15647 [1 << 17]byte +var z15648 [1 << 17]byte +var z15649 [1 << 17]byte +var z15650 [1 << 17]byte +var z15651 [1 << 17]byte +var z15652 [1 << 17]byte +var z15653 [1 << 17]byte +var z15654 [1 << 17]byte +var z15655 [1 << 17]byte +var z15656 [1 << 17]byte +var z15657 [1 << 17]byte +var z15658 [1 << 17]byte +var z15659 [1 << 17]byte +var z15660 [1 << 17]byte +var z15661 [1 << 17]byte +var z15662 [1 << 17]byte +var z15663 [1 << 17]byte +var z15664 [1 << 17]byte +var z15665 [1 << 17]byte +var z15666 [1 << 17]byte +var z15667 [1 << 17]byte +var z15668 [1 << 17]byte +var z15669 [1 << 17]byte +var z15670 [1 << 17]byte +var z15671 [1 << 17]byte +var z15672 [1 << 17]byte +var z15673 [1 << 17]byte +var z15674 [1 << 17]byte +var z15675 [1 << 17]byte +var z15676 [1 << 17]byte +var z15677 [1 << 17]byte +var z15678 [1 << 17]byte +var z15679 [1 << 17]byte +var z15680 [1 << 17]byte +var z15681 [1 << 17]byte +var z15682 [1 << 17]byte +var z15683 [1 << 17]byte +var z15684 [1 << 17]byte +var z15685 [1 << 17]byte +var z15686 [1 << 17]byte +var z15687 [1 << 17]byte +var z15688 [1 << 17]byte +var z15689 [1 << 17]byte +var z15690 [1 << 17]byte +var z15691 [1 << 17]byte +var z15692 [1 << 17]byte +var z15693 [1 << 17]byte +var z15694 [1 << 17]byte +var z15695 [1 << 17]byte +var z15696 [1 << 17]byte +var z15697 [1 << 17]byte +var z15698 [1 << 17]byte +var z15699 [1 << 17]byte +var z15700 [1 << 17]byte +var z15701 [1 << 17]byte +var z15702 [1 << 17]byte +var z15703 [1 << 17]byte +var z15704 [1 << 17]byte +var z15705 [1 << 17]byte +var z15706 [1 << 17]byte +var z15707 [1 << 17]byte +var z15708 [1 << 17]byte +var z15709 [1 << 17]byte +var z15710 [1 << 17]byte +var z15711 [1 << 17]byte +var z15712 [1 << 17]byte +var z15713 [1 << 17]byte +var z15714 [1 << 17]byte +var z15715 [1 << 17]byte +var z15716 [1 << 17]byte +var z15717 [1 << 17]byte +var z15718 [1 << 17]byte +var z15719 [1 << 17]byte +var z15720 [1 << 17]byte +var z15721 [1 << 17]byte +var z15722 [1 << 17]byte +var z15723 [1 << 17]byte +var z15724 [1 << 17]byte +var z15725 [1 << 17]byte +var z15726 [1 << 17]byte +var z15727 [1 << 17]byte +var z15728 [1 << 17]byte +var z15729 [1 << 17]byte +var z15730 [1 << 17]byte +var z15731 [1 << 17]byte +var z15732 [1 << 17]byte +var z15733 [1 << 17]byte +var z15734 [1 << 17]byte +var z15735 [1 << 17]byte +var z15736 [1 << 17]byte +var z15737 [1 << 17]byte +var z15738 [1 << 17]byte +var z15739 [1 << 17]byte +var z15740 [1 << 17]byte +var z15741 [1 << 17]byte +var z15742 [1 << 17]byte +var z15743 [1 << 17]byte +var z15744 [1 << 17]byte +var z15745 [1 << 17]byte +var z15746 [1 << 17]byte +var z15747 [1 << 17]byte +var z15748 [1 << 17]byte +var z15749 [1 << 17]byte +var z15750 [1 << 17]byte +var z15751 [1 << 17]byte +var z15752 [1 << 17]byte +var z15753 [1 << 17]byte +var z15754 [1 << 17]byte +var z15755 [1 << 17]byte +var z15756 [1 << 17]byte +var z15757 [1 << 17]byte +var z15758 [1 << 17]byte +var z15759 [1 << 17]byte +var z15760 [1 << 17]byte +var z15761 [1 << 17]byte +var z15762 [1 << 17]byte +var z15763 [1 << 17]byte +var z15764 [1 << 17]byte +var z15765 [1 << 17]byte +var z15766 [1 << 17]byte +var z15767 [1 << 17]byte +var z15768 [1 << 17]byte +var z15769 [1 << 17]byte +var z15770 [1 << 17]byte +var z15771 [1 << 17]byte +var z15772 [1 << 17]byte +var z15773 [1 << 17]byte +var z15774 [1 << 17]byte +var z15775 [1 << 17]byte +var z15776 [1 << 17]byte +var z15777 [1 << 17]byte +var z15778 [1 << 17]byte +var z15779 [1 << 17]byte +var z15780 [1 << 17]byte +var z15781 [1 << 17]byte +var z15782 [1 << 17]byte +var z15783 [1 << 17]byte +var z15784 [1 << 17]byte +var z15785 [1 << 17]byte +var z15786 [1 << 17]byte +var z15787 [1 << 17]byte +var z15788 [1 << 17]byte +var z15789 [1 << 17]byte +var z15790 [1 << 17]byte +var z15791 [1 << 17]byte +var z15792 [1 << 17]byte +var z15793 [1 << 17]byte +var z15794 [1 << 17]byte +var z15795 [1 << 17]byte +var z15796 [1 << 17]byte +var z15797 [1 << 17]byte +var z15798 [1 << 17]byte +var z15799 [1 << 17]byte +var z15800 [1 << 17]byte +var z15801 [1 << 17]byte +var z15802 [1 << 17]byte +var z15803 [1 << 17]byte +var z15804 [1 << 17]byte +var z15805 [1 << 17]byte +var z15806 [1 << 17]byte +var z15807 [1 << 17]byte +var z15808 [1 << 17]byte +var z15809 [1 << 17]byte +var z15810 [1 << 17]byte +var z15811 [1 << 17]byte +var z15812 [1 << 17]byte +var z15813 [1 << 17]byte +var z15814 [1 << 17]byte +var z15815 [1 << 17]byte +var z15816 [1 << 17]byte +var z15817 [1 << 17]byte +var z15818 [1 << 17]byte +var z15819 [1 << 17]byte +var z15820 [1 << 17]byte +var z15821 [1 << 17]byte +var z15822 [1 << 17]byte +var z15823 [1 << 17]byte +var z15824 [1 << 17]byte +var z15825 [1 << 17]byte +var z15826 [1 << 17]byte +var z15827 [1 << 17]byte +var z15828 [1 << 17]byte +var z15829 [1 << 17]byte +var z15830 [1 << 17]byte +var z15831 [1 << 17]byte +var z15832 [1 << 17]byte +var z15833 [1 << 17]byte +var z15834 [1 << 17]byte +var z15835 [1 << 17]byte +var z15836 [1 << 17]byte +var z15837 [1 << 17]byte +var z15838 [1 << 17]byte +var z15839 [1 << 17]byte +var z15840 [1 << 17]byte +var z15841 [1 << 17]byte +var z15842 [1 << 17]byte +var z15843 [1 << 17]byte +var z15844 [1 << 17]byte +var z15845 [1 << 17]byte +var z15846 [1 << 17]byte +var z15847 [1 << 17]byte +var z15848 [1 << 17]byte +var z15849 [1 << 17]byte +var z15850 [1 << 17]byte +var z15851 [1 << 17]byte +var z15852 [1 << 17]byte +var z15853 [1 << 17]byte +var z15854 [1 << 17]byte +var z15855 [1 << 17]byte +var z15856 [1 << 17]byte +var z15857 [1 << 17]byte +var z15858 [1 << 17]byte +var z15859 [1 << 17]byte +var z15860 [1 << 17]byte +var z15861 [1 << 17]byte +var z15862 [1 << 17]byte +var z15863 [1 << 17]byte +var z15864 [1 << 17]byte +var z15865 [1 << 17]byte +var z15866 [1 << 17]byte +var z15867 [1 << 17]byte +var z15868 [1 << 17]byte +var z15869 [1 << 17]byte +var z15870 [1 << 17]byte +var z15871 [1 << 17]byte +var z15872 [1 << 17]byte +var z15873 [1 << 17]byte +var z15874 [1 << 17]byte +var z15875 [1 << 17]byte +var z15876 [1 << 17]byte +var z15877 [1 << 17]byte +var z15878 [1 << 17]byte +var z15879 [1 << 17]byte +var z15880 [1 << 17]byte +var z15881 [1 << 17]byte +var z15882 [1 << 17]byte +var z15883 [1 << 17]byte +var z15884 [1 << 17]byte +var z15885 [1 << 17]byte +var z15886 [1 << 17]byte +var z15887 [1 << 17]byte +var z15888 [1 << 17]byte +var z15889 [1 << 17]byte +var z15890 [1 << 17]byte +var z15891 [1 << 17]byte +var z15892 [1 << 17]byte +var z15893 [1 << 17]byte +var z15894 [1 << 17]byte +var z15895 [1 << 17]byte +var z15896 [1 << 17]byte +var z15897 [1 << 17]byte +var z15898 [1 << 17]byte +var z15899 [1 << 17]byte +var z15900 [1 << 17]byte +var z15901 [1 << 17]byte +var z15902 [1 << 17]byte +var z15903 [1 << 17]byte +var z15904 [1 << 17]byte +var z15905 [1 << 17]byte +var z15906 [1 << 17]byte +var z15907 [1 << 17]byte +var z15908 [1 << 17]byte +var z15909 [1 << 17]byte +var z15910 [1 << 17]byte +var z15911 [1 << 17]byte +var z15912 [1 << 17]byte +var z15913 [1 << 17]byte +var z15914 [1 << 17]byte +var z15915 [1 << 17]byte +var z15916 [1 << 17]byte +var z15917 [1 << 17]byte +var z15918 [1 << 17]byte +var z15919 [1 << 17]byte +var z15920 [1 << 17]byte +var z15921 [1 << 17]byte +var z15922 [1 << 17]byte +var z15923 [1 << 17]byte +var z15924 [1 << 17]byte +var z15925 [1 << 17]byte +var z15926 [1 << 17]byte +var z15927 [1 << 17]byte +var z15928 [1 << 17]byte +var z15929 [1 << 17]byte +var z15930 [1 << 17]byte +var z15931 [1 << 17]byte +var z15932 [1 << 17]byte +var z15933 [1 << 17]byte +var z15934 [1 << 17]byte +var z15935 [1 << 17]byte +var z15936 [1 << 17]byte +var z15937 [1 << 17]byte +var z15938 [1 << 17]byte +var z15939 [1 << 17]byte +var z15940 [1 << 17]byte +var z15941 [1 << 17]byte +var z15942 [1 << 17]byte +var z15943 [1 << 17]byte +var z15944 [1 << 17]byte +var z15945 [1 << 17]byte +var z15946 [1 << 17]byte +var z15947 [1 << 17]byte +var z15948 [1 << 17]byte +var z15949 [1 << 17]byte +var z15950 [1 << 17]byte +var z15951 [1 << 17]byte +var z15952 [1 << 17]byte +var z15953 [1 << 17]byte +var z15954 [1 << 17]byte +var z15955 [1 << 17]byte +var z15956 [1 << 17]byte +var z15957 [1 << 17]byte +var z15958 [1 << 17]byte +var z15959 [1 << 17]byte +var z15960 [1 << 17]byte +var z15961 [1 << 17]byte +var z15962 [1 << 17]byte +var z15963 [1 << 17]byte +var z15964 [1 << 17]byte +var z15965 [1 << 17]byte +var z15966 [1 << 17]byte +var z15967 [1 << 17]byte +var z15968 [1 << 17]byte +var z15969 [1 << 17]byte +var z15970 [1 << 17]byte +var z15971 [1 << 17]byte +var z15972 [1 << 17]byte +var z15973 [1 << 17]byte +var z15974 [1 << 17]byte +var z15975 [1 << 17]byte +var z15976 [1 << 17]byte +var z15977 [1 << 17]byte +var z15978 [1 << 17]byte +var z15979 [1 << 17]byte +var z15980 [1 << 17]byte +var z15981 [1 << 17]byte +var z15982 [1 << 17]byte +var z15983 [1 << 17]byte +var z15984 [1 << 17]byte +var z15985 [1 << 17]byte +var z15986 [1 << 17]byte +var z15987 [1 << 17]byte +var z15988 [1 << 17]byte +var z15989 [1 << 17]byte +var z15990 [1 << 17]byte +var z15991 [1 << 17]byte +var z15992 [1 << 17]byte +var z15993 [1 << 17]byte +var z15994 [1 << 17]byte +var z15995 [1 << 17]byte +var z15996 [1 << 17]byte +var z15997 [1 << 17]byte +var z15998 [1 << 17]byte +var z15999 [1 << 17]byte +var z16000 [1 << 17]byte +var z16001 [1 << 17]byte +var z16002 [1 << 17]byte +var z16003 [1 << 17]byte +var z16004 [1 << 17]byte +var z16005 [1 << 17]byte +var z16006 [1 << 17]byte +var z16007 [1 << 17]byte +var z16008 [1 << 17]byte +var z16009 [1 << 17]byte +var z16010 [1 << 17]byte +var z16011 [1 << 17]byte +var z16012 [1 << 17]byte +var z16013 [1 << 17]byte +var z16014 [1 << 17]byte +var z16015 [1 << 17]byte +var z16016 [1 << 17]byte +var z16017 [1 << 17]byte +var z16018 [1 << 17]byte +var z16019 [1 << 17]byte +var z16020 [1 << 17]byte +var z16021 [1 << 17]byte +var z16022 [1 << 17]byte +var z16023 [1 << 17]byte +var z16024 [1 << 17]byte +var z16025 [1 << 17]byte +var z16026 [1 << 17]byte +var z16027 [1 << 17]byte +var z16028 [1 << 17]byte +var z16029 [1 << 17]byte +var z16030 [1 << 17]byte +var z16031 [1 << 17]byte +var z16032 [1 << 17]byte +var z16033 [1 << 17]byte +var z16034 [1 << 17]byte +var z16035 [1 << 17]byte +var z16036 [1 << 17]byte +var z16037 [1 << 17]byte +var z16038 [1 << 17]byte +var z16039 [1 << 17]byte +var z16040 [1 << 17]byte +var z16041 [1 << 17]byte +var z16042 [1 << 17]byte +var z16043 [1 << 17]byte +var z16044 [1 << 17]byte +var z16045 [1 << 17]byte +var z16046 [1 << 17]byte +var z16047 [1 << 17]byte +var z16048 [1 << 17]byte +var z16049 [1 << 17]byte +var z16050 [1 << 17]byte +var z16051 [1 << 17]byte +var z16052 [1 << 17]byte +var z16053 [1 << 17]byte +var z16054 [1 << 17]byte +var z16055 [1 << 17]byte +var z16056 [1 << 17]byte +var z16057 [1 << 17]byte +var z16058 [1 << 17]byte +var z16059 [1 << 17]byte +var z16060 [1 << 17]byte +var z16061 [1 << 17]byte +var z16062 [1 << 17]byte +var z16063 [1 << 17]byte +var z16064 [1 << 17]byte +var z16065 [1 << 17]byte +var z16066 [1 << 17]byte +var z16067 [1 << 17]byte +var z16068 [1 << 17]byte +var z16069 [1 << 17]byte +var z16070 [1 << 17]byte +var z16071 [1 << 17]byte +var z16072 [1 << 17]byte +var z16073 [1 << 17]byte +var z16074 [1 << 17]byte +var z16075 [1 << 17]byte +var z16076 [1 << 17]byte +var z16077 [1 << 17]byte +var z16078 [1 << 17]byte +var z16079 [1 << 17]byte +var z16080 [1 << 17]byte +var z16081 [1 << 17]byte +var z16082 [1 << 17]byte +var z16083 [1 << 17]byte +var z16084 [1 << 17]byte +var z16085 [1 << 17]byte +var z16086 [1 << 17]byte +var z16087 [1 << 17]byte +var z16088 [1 << 17]byte +var z16089 [1 << 17]byte +var z16090 [1 << 17]byte +var z16091 [1 << 17]byte +var z16092 [1 << 17]byte +var z16093 [1 << 17]byte +var z16094 [1 << 17]byte +var z16095 [1 << 17]byte +var z16096 [1 << 17]byte +var z16097 [1 << 17]byte +var z16098 [1 << 17]byte +var z16099 [1 << 17]byte +var z16100 [1 << 17]byte +var z16101 [1 << 17]byte +var z16102 [1 << 17]byte +var z16103 [1 << 17]byte +var z16104 [1 << 17]byte +var z16105 [1 << 17]byte +var z16106 [1 << 17]byte +var z16107 [1 << 17]byte +var z16108 [1 << 17]byte +var z16109 [1 << 17]byte +var z16110 [1 << 17]byte +var z16111 [1 << 17]byte +var z16112 [1 << 17]byte +var z16113 [1 << 17]byte +var z16114 [1 << 17]byte +var z16115 [1 << 17]byte +var z16116 [1 << 17]byte +var z16117 [1 << 17]byte +var z16118 [1 << 17]byte +var z16119 [1 << 17]byte +var z16120 [1 << 17]byte +var z16121 [1 << 17]byte +var z16122 [1 << 17]byte +var z16123 [1 << 17]byte +var z16124 [1 << 17]byte +var z16125 [1 << 17]byte +var z16126 [1 << 17]byte +var z16127 [1 << 17]byte +var z16128 [1 << 17]byte +var z16129 [1 << 17]byte +var z16130 [1 << 17]byte +var z16131 [1 << 17]byte +var z16132 [1 << 17]byte +var z16133 [1 << 17]byte +var z16134 [1 << 17]byte +var z16135 [1 << 17]byte +var z16136 [1 << 17]byte +var z16137 [1 << 17]byte +var z16138 [1 << 17]byte +var z16139 [1 << 17]byte +var z16140 [1 << 17]byte +var z16141 [1 << 17]byte +var z16142 [1 << 17]byte +var z16143 [1 << 17]byte +var z16144 [1 << 17]byte +var z16145 [1 << 17]byte +var z16146 [1 << 17]byte +var z16147 [1 << 17]byte +var z16148 [1 << 17]byte +var z16149 [1 << 17]byte +var z16150 [1 << 17]byte +var z16151 [1 << 17]byte +var z16152 [1 << 17]byte +var z16153 [1 << 17]byte +var z16154 [1 << 17]byte +var z16155 [1 << 17]byte +var z16156 [1 << 17]byte +var z16157 [1 << 17]byte +var z16158 [1 << 17]byte +var z16159 [1 << 17]byte +var z16160 [1 << 17]byte +var z16161 [1 << 17]byte +var z16162 [1 << 17]byte +var z16163 [1 << 17]byte +var z16164 [1 << 17]byte +var z16165 [1 << 17]byte +var z16166 [1 << 17]byte +var z16167 [1 << 17]byte +var z16168 [1 << 17]byte +var z16169 [1 << 17]byte +var z16170 [1 << 17]byte +var z16171 [1 << 17]byte +var z16172 [1 << 17]byte +var z16173 [1 << 17]byte +var z16174 [1 << 17]byte +var z16175 [1 << 17]byte +var z16176 [1 << 17]byte +var z16177 [1 << 17]byte +var z16178 [1 << 17]byte +var z16179 [1 << 17]byte +var z16180 [1 << 17]byte +var z16181 [1 << 17]byte +var z16182 [1 << 17]byte +var z16183 [1 << 17]byte +var z16184 [1 << 17]byte +var z16185 [1 << 17]byte +var z16186 [1 << 17]byte +var z16187 [1 << 17]byte +var z16188 [1 << 17]byte +var z16189 [1 << 17]byte +var z16190 [1 << 17]byte +var z16191 [1 << 17]byte +var z16192 [1 << 17]byte +var z16193 [1 << 17]byte +var z16194 [1 << 17]byte +var z16195 [1 << 17]byte +var z16196 [1 << 17]byte +var z16197 [1 << 17]byte +var z16198 [1 << 17]byte +var z16199 [1 << 17]byte +var z16200 [1 << 17]byte +var z16201 [1 << 17]byte +var z16202 [1 << 17]byte +var z16203 [1 << 17]byte +var z16204 [1 << 17]byte +var z16205 [1 << 17]byte +var z16206 [1 << 17]byte +var z16207 [1 << 17]byte +var z16208 [1 << 17]byte +var z16209 [1 << 17]byte +var z16210 [1 << 17]byte +var z16211 [1 << 17]byte +var z16212 [1 << 17]byte +var z16213 [1 << 17]byte +var z16214 [1 << 17]byte +var z16215 [1 << 17]byte +var z16216 [1 << 17]byte +var z16217 [1 << 17]byte +var z16218 [1 << 17]byte +var z16219 [1 << 17]byte +var z16220 [1 << 17]byte +var z16221 [1 << 17]byte +var z16222 [1 << 17]byte +var z16223 [1 << 17]byte +var z16224 [1 << 17]byte +var z16225 [1 << 17]byte +var z16226 [1 << 17]byte +var z16227 [1 << 17]byte +var z16228 [1 << 17]byte +var z16229 [1 << 17]byte +var z16230 [1 << 17]byte +var z16231 [1 << 17]byte +var z16232 [1 << 17]byte +var z16233 [1 << 17]byte +var z16234 [1 << 17]byte +var z16235 [1 << 17]byte +var z16236 [1 << 17]byte +var z16237 [1 << 17]byte +var z16238 [1 << 17]byte +var z16239 [1 << 17]byte +var z16240 [1 << 17]byte +var z16241 [1 << 17]byte +var z16242 [1 << 17]byte +var z16243 [1 << 17]byte +var z16244 [1 << 17]byte +var z16245 [1 << 17]byte +var z16246 [1 << 17]byte +var z16247 [1 << 17]byte +var z16248 [1 << 17]byte +var z16249 [1 << 17]byte +var z16250 [1 << 17]byte +var z16251 [1 << 17]byte +var z16252 [1 << 17]byte +var z16253 [1 << 17]byte +var z16254 [1 << 17]byte +var z16255 [1 << 17]byte +var z16256 [1 << 17]byte +var z16257 [1 << 17]byte +var z16258 [1 << 17]byte +var z16259 [1 << 17]byte +var z16260 [1 << 17]byte +var z16261 [1 << 17]byte +var z16262 [1 << 17]byte +var z16263 [1 << 17]byte +var z16264 [1 << 17]byte +var z16265 [1 << 17]byte +var z16266 [1 << 17]byte +var z16267 [1 << 17]byte +var z16268 [1 << 17]byte +var z16269 [1 << 17]byte +var z16270 [1 << 17]byte +var z16271 [1 << 17]byte +var z16272 [1 << 17]byte +var z16273 [1 << 17]byte +var z16274 [1 << 17]byte +var z16275 [1 << 17]byte +var z16276 [1 << 17]byte +var z16277 [1 << 17]byte +var z16278 [1 << 17]byte +var z16279 [1 << 17]byte +var z16280 [1 << 17]byte +var z16281 [1 << 17]byte +var z16282 [1 << 17]byte +var z16283 [1 << 17]byte +var z16284 [1 << 17]byte +var z16285 [1 << 17]byte +var z16286 [1 << 17]byte +var z16287 [1 << 17]byte +var z16288 [1 << 17]byte +var z16289 [1 << 17]byte +var z16290 [1 << 17]byte +var z16291 [1 << 17]byte +var z16292 [1 << 17]byte +var z16293 [1 << 17]byte +var z16294 [1 << 17]byte +var z16295 [1 << 17]byte +var z16296 [1 << 17]byte +var z16297 [1 << 17]byte +var z16298 [1 << 17]byte +var z16299 [1 << 17]byte +var z16300 [1 << 17]byte +var z16301 [1 << 17]byte +var z16302 [1 << 17]byte +var z16303 [1 << 17]byte +var z16304 [1 << 17]byte +var z16305 [1 << 17]byte +var z16306 [1 << 17]byte +var z16307 [1 << 17]byte +var z16308 [1 << 17]byte +var z16309 [1 << 17]byte +var z16310 [1 << 17]byte +var z16311 [1 << 17]byte +var z16312 [1 << 17]byte +var z16313 [1 << 17]byte +var z16314 [1 << 17]byte +var z16315 [1 << 17]byte +var z16316 [1 << 17]byte +var z16317 [1 << 17]byte +var z16318 [1 << 17]byte +var z16319 [1 << 17]byte +var z16320 [1 << 17]byte +var z16321 [1 << 17]byte +var z16322 [1 << 17]byte +var z16323 [1 << 17]byte +var z16324 [1 << 17]byte +var z16325 [1 << 17]byte +var z16326 [1 << 17]byte +var z16327 [1 << 17]byte +var z16328 [1 << 17]byte +var z16329 [1 << 17]byte +var z16330 [1 << 17]byte +var z16331 [1 << 17]byte +var z16332 [1 << 17]byte +var z16333 [1 << 17]byte +var z16334 [1 << 17]byte +var z16335 [1 << 17]byte +var z16336 [1 << 17]byte +var z16337 [1 << 17]byte +var z16338 [1 << 17]byte +var z16339 [1 << 17]byte +var z16340 [1 << 17]byte +var z16341 [1 << 17]byte +var z16342 [1 << 17]byte +var z16343 [1 << 17]byte +var z16344 [1 << 17]byte +var z16345 [1 << 17]byte +var z16346 [1 << 17]byte +var z16347 [1 << 17]byte +var z16348 [1 << 17]byte +var z16349 [1 << 17]byte +var z16350 [1 << 17]byte +var z16351 [1 << 17]byte +var z16352 [1 << 17]byte +var z16353 [1 << 17]byte +var z16354 [1 << 17]byte +var z16355 [1 << 17]byte +var z16356 [1 << 17]byte +var z16357 [1 << 17]byte +var z16358 [1 << 17]byte +var z16359 [1 << 17]byte +var z16360 [1 << 17]byte +var z16361 [1 << 17]byte +var z16362 [1 << 17]byte +var z16363 [1 << 17]byte +var z16364 [1 << 17]byte +var z16365 [1 << 17]byte +var z16366 [1 << 17]byte +var z16367 [1 << 17]byte +var z16368 [1 << 17]byte +var z16369 [1 << 17]byte +var z16370 [1 << 17]byte +var z16371 [1 << 17]byte +var z16372 [1 << 17]byte +var z16373 [1 << 17]byte +var z16374 [1 << 17]byte +var z16375 [1 << 17]byte +var z16376 [1 << 17]byte +var z16377 [1 << 17]byte +var z16378 [1 << 17]byte +var z16379 [1 << 17]byte +var z16380 [1 << 17]byte +var z16381 [1 << 17]byte +var z16382 [1 << 17]byte +var z16383 [1 << 17]byte +var z16384 [1 << 17]byte +var z16385 [1 << 17]byte +var z16386 [1 << 17]byte +var z16387 [1 << 17]byte +var z16388 [1 << 17]byte +var z16389 [1 << 17]byte +var z16390 [1 << 17]byte +var z16391 [1 << 17]byte +var z16392 [1 << 17]byte +var z16393 [1 << 17]byte +var z16394 [1 << 17]byte +var z16395 [1 << 17]byte +var z16396 [1 << 17]byte +var z16397 [1 << 17]byte +var z16398 [1 << 17]byte +var z16399 [1 << 17]byte +var z16400 [1 << 17]byte +var z16401 [1 << 17]byte +var z16402 [1 << 17]byte +var z16403 [1 << 17]byte +var z16404 [1 << 17]byte +var z16405 [1 << 17]byte +var z16406 [1 << 17]byte +var z16407 [1 << 17]byte +var z16408 [1 << 17]byte +var z16409 [1 << 17]byte +var z16410 [1 << 17]byte +var z16411 [1 << 17]byte +var z16412 [1 << 17]byte +var z16413 [1 << 17]byte +var z16414 [1 << 17]byte +var z16415 [1 << 17]byte +var z16416 [1 << 17]byte +var z16417 [1 << 17]byte +var z16418 [1 << 17]byte +var z16419 [1 << 17]byte +var z16420 [1 << 17]byte +var z16421 [1 << 17]byte +var z16422 [1 << 17]byte +var z16423 [1 << 17]byte +var z16424 [1 << 17]byte +var z16425 [1 << 17]byte +var z16426 [1 << 17]byte +var z16427 [1 << 17]byte +var z16428 [1 << 17]byte +var z16429 [1 << 17]byte +var z16430 [1 << 17]byte +var z16431 [1 << 17]byte +var z16432 [1 << 17]byte +var z16433 [1 << 17]byte +var z16434 [1 << 17]byte +var z16435 [1 << 17]byte +var z16436 [1 << 17]byte +var z16437 [1 << 17]byte +var z16438 [1 << 17]byte +var z16439 [1 << 17]byte +var z16440 [1 << 17]byte +var z16441 [1 << 17]byte +var z16442 [1 << 17]byte +var z16443 [1 << 17]byte +var z16444 [1 << 17]byte +var z16445 [1 << 17]byte +var z16446 [1 << 17]byte +var z16447 [1 << 17]byte +var z16448 [1 << 17]byte +var z16449 [1 << 17]byte +var z16450 [1 << 17]byte +var z16451 [1 << 17]byte +var z16452 [1 << 17]byte +var z16453 [1 << 17]byte +var z16454 [1 << 17]byte +var z16455 [1 << 17]byte +var z16456 [1 << 17]byte +var z16457 [1 << 17]byte +var z16458 [1 << 17]byte +var z16459 [1 << 17]byte +var z16460 [1 << 17]byte +var z16461 [1 << 17]byte +var z16462 [1 << 17]byte +var z16463 [1 << 17]byte +var z16464 [1 << 17]byte +var z16465 [1 << 17]byte +var z16466 [1 << 17]byte +var z16467 [1 << 17]byte +var z16468 [1 << 17]byte +var z16469 [1 << 17]byte +var z16470 [1 << 17]byte +var z16471 [1 << 17]byte +var z16472 [1 << 17]byte +var z16473 [1 << 17]byte +var z16474 [1 << 17]byte +var z16475 [1 << 17]byte +var z16476 [1 << 17]byte +var z16477 [1 << 17]byte +var z16478 [1 << 17]byte +var z16479 [1 << 17]byte +var z16480 [1 << 17]byte func main() { // GC_ERROR "stack frame too large" - // seq 1 16480 | sed 's/.*/ var x& [1<<17]byte/' - // seq 1 16480 | sed 's/.*/ z = x&/' + // seq 1 16480 | sed 's/.*/ var x& [1 << 17]byte/' + // seq 1 16480 | sed 's/.*/ z& = x&/' var x1 [1 << 17]byte var x2 [1 << 17]byte var x3 [1 << 17]byte @@ -16496,16484 +32976,16484 @@ var x16478 [1 << 17]byte var x16479 [1 << 17]byte var x16480 [1 << 17]byte - z = x1 - z = x2 - z = x3 - z = x4 - z = x5 - z = x6 - z = x7 - z = x8 - z = x9 - z = x10 - z = x11 - z = x12 - z = x13 - z = x14 - z = x15 - z = x16 - z = x17 - z = x18 - z = x19 - z = x20 - z = x21 - z = x22 - z = x23 - z = x24 - z = x25 - z = x26 - z = x27 - z = x28 - z = x29 - z = x30 - z = x31 - z = x32 - z = x33 - z = x34 - z = x35 - z = x36 - z = x37 - z = x38 - z = x39 - z = x40 - z = x41 - z = x42 - z = x43 - z = x44 - z = x45 - z = x46 - z = x47 - z = x48 - z = x49 - z = x50 - z = x51 - z = x52 - z = x53 - z = x54 - z = x55 - z = x56 - z = x57 - z = x58 - z = x59 - z = x60 - z = x61 - z = x62 - z = x63 - z = x64 - z = x65 - z = x66 - z = x67 - z = x68 - z = x69 - z = x70 - z = x71 - z = x72 - z = x73 - z = x74 - z = x75 - z = x76 - z = x77 - z = x78 - z = x79 - z = x80 - z = x81 - z = x82 - z = x83 - z = x84 - z = x85 - z = x86 - z = x87 - z = x88 - z = x89 - z = x90 - z = x91 - z = x92 - z = x93 - z = x94 - z = x95 - z = x96 - z = x97 - z = x98 - z = x99 - z = x100 - z = x101 - z = x102 - z = x103 - z = x104 - z = x105 - z = x106 - z = x107 - z = x108 - z = x109 - z = x110 - z = x111 - z = x112 - z = x113 - z = x114 - z = x115 - z = x116 - z = x117 - z = x118 - z = x119 - z = x120 - z = x121 - z = x122 - z = x123 - z = x124 - z = x125 - z = x126 - z = x127 - z = x128 - z = x129 - z = x130 - z = x131 - z = x132 - z = x133 - z = x134 - z = x135 - z = x136 - z = x137 - z = x138 - z = x139 - z = x140 - z = x141 - z = x142 - z = x143 - z = x144 - z = x145 - z = x146 - z = x147 - z = x148 - z = x149 - z = x150 - z = x151 - z = x152 - z = x153 - z = x154 - z = x155 - z = x156 - z = x157 - z = x158 - z = x159 - z = x160 - z = x161 - z = x162 - z = x163 - z = x164 - z = x165 - z = x166 - z = x167 - z = x168 - z = x169 - z = x170 - z = x171 - z = x172 - z = x173 - z = x174 - z = x175 - z = x176 - z = x177 - z = x178 - z = x179 - z = x180 - z = x181 - z = x182 - z = x183 - z = x184 - z = x185 - z = x186 - z = x187 - z = x188 - z = x189 - z = x190 - z = x191 - z = x192 - z = x193 - z = x194 - z = x195 - z = x196 - z = x197 - z = x198 - z = x199 - z = x200 - z = x201 - z = x202 - z = x203 - z = x204 - z = x205 - z = x206 - z = x207 - z = x208 - z = x209 - z = x210 - z = x211 - z = x212 - z = x213 - z = x214 - z = x215 - z = x216 - z = x217 - z = x218 - z = x219 - z = x220 - z = x221 - z = x222 - z = x223 - z = x224 - z = x225 - z = x226 - z = x227 - z = x228 - z = x229 - z = x230 - z = x231 - z = x232 - z = x233 - z = x234 - z = x235 - z = x236 - z = x237 - z = x238 - z = x239 - z = x240 - z = x241 - z = x242 - z = x243 - z = x244 - z = x245 - z = x246 - z = x247 - z = x248 - z = x249 - z = x250 - z = x251 - z = x252 - z = x253 - z = x254 - z = x255 - z = x256 - z = x257 - z = x258 - z = x259 - z = x260 - z = x261 - z = x262 - z = x263 - z = x264 - z = x265 - z = x266 - z = x267 - z = x268 - z = x269 - z = x270 - z = x271 - z = x272 - z = x273 - z = x274 - z = x275 - z = x276 - z = x277 - z = x278 - z = x279 - z = x280 - z = x281 - z = x282 - z = x283 - z = x284 - z = x285 - z = x286 - z = x287 - z = x288 - z = x289 - z = x290 - z = x291 - z = x292 - z = x293 - z = x294 - z = x295 - z = x296 - z = x297 - z = x298 - z = x299 - z = x300 - z = x301 - z = x302 - z = x303 - z = x304 - z = x305 - z = x306 - z = x307 - z = x308 - z = x309 - z = x310 - z = x311 - z = x312 - z = x313 - z = x314 - z = x315 - z = x316 - z = x317 - z = x318 - z = x319 - z = x320 - z = x321 - z = x322 - z = x323 - z = x324 - z = x325 - z = x326 - z = x327 - z = x328 - z = x329 - z = x330 - z = x331 - z = x332 - z = x333 - z = x334 - z = x335 - z = x336 - z = x337 - z = x338 - z = x339 - z = x340 - z = x341 - z = x342 - z = x343 - z = x344 - z = x345 - z = x346 - z = x347 - z = x348 - z = x349 - z = x350 - z = x351 - z = x352 - z = x353 - z = x354 - z = x355 - z = x356 - z = x357 - z = x358 - z = x359 - z = x360 - z = x361 - z = x362 - z = x363 - z = x364 - z = x365 - z = x366 - z = x367 - z = x368 - z = x369 - z = x370 - z = x371 - z = x372 - z = x373 - z = x374 - z = x375 - z = x376 - z = x377 - z = x378 - z = x379 - z = x380 - z = x381 - z = x382 - z = x383 - z = x384 - z = x385 - z = x386 - z = x387 - z = x388 - z = x389 - z = x390 - z = x391 - z = x392 - z = x393 - z = x394 - z = x395 - z = x396 - z = x397 - z = x398 - z = x399 - z = x400 - z = x401 - z = x402 - z = x403 - z = x404 - z = x405 - z = x406 - z = x407 - z = x408 - z = x409 - z = x410 - z = x411 - z = x412 - z = x413 - z = x414 - z = x415 - z = x416 - z = x417 - z = x418 - z = x419 - z = x420 - z = x421 - z = x422 - z = x423 - z = x424 - z = x425 - z = x426 - z = x427 - z = x428 - z = x429 - z = x430 - z = x431 - z = x432 - z = x433 - z = x434 - z = x435 - z = x436 - z = x437 - z = x438 - z = x439 - z = x440 - z = x441 - z = x442 - z = x443 - z = x444 - z = x445 - z = x446 - z = x447 - z = x448 - z = x449 - z = x450 - z = x451 - z = x452 - z = x453 - z = x454 - z = x455 - z = x456 - z = x457 - z = x458 - z = x459 - z = x460 - z = x461 - z = x462 - z = x463 - z = x464 - z = x465 - z = x466 - z = x467 - z = x468 - z = x469 - z = x470 - z = x471 - z = x472 - z = x473 - z = x474 - z = x475 - z = x476 - z = x477 - z = x478 - z = x479 - z = x480 - z = x481 - z = x482 - z = x483 - z = x484 - z = x485 - z = x486 - z = x487 - z = x488 - z = x489 - z = x490 - z = x491 - z = x492 - z = x493 - z = x494 - z = x495 - z = x496 - z = x497 - z = x498 - z = x499 - z = x500 - z = x501 - z = x502 - z = x503 - z = x504 - z = x505 - z = x506 - z = x507 - z = x508 - z = x509 - z = x510 - z = x511 - z = x512 - z = x513 - z = x514 - z = x515 - z = x516 - z = x517 - z = x518 - z = x519 - z = x520 - z = x521 - z = x522 - z = x523 - z = x524 - z = x525 - z = x526 - z = x527 - z = x528 - z = x529 - z = x530 - z = x531 - z = x532 - z = x533 - z = x534 - z = x535 - z = x536 - z = x537 - z = x538 - z = x539 - z = x540 - z = x541 - z = x542 - z = x543 - z = x544 - z = x545 - z = x546 - z = x547 - z = x548 - z = x549 - z = x550 - z = x551 - z = x552 - z = x553 - z = x554 - z = x555 - z = x556 - z = x557 - z = x558 - z = x559 - z = x560 - z = x561 - z = x562 - z = x563 - z = x564 - z = x565 - z = x566 - z = x567 - z = x568 - z = x569 - z = x570 - z = x571 - z = x572 - z = x573 - z = x574 - z = x575 - z = x576 - z = x577 - z = x578 - z = x579 - z = x580 - z = x581 - z = x582 - z = x583 - z = x584 - z = x585 - z = x586 - z = x587 - z = x588 - z = x589 - z = x590 - z = x591 - z = x592 - z = x593 - z = x594 - z = x595 - z = x596 - z = x597 - z = x598 - z = x599 - z = x600 - z = x601 - z = x602 - z = x603 - z = x604 - z = x605 - z = x606 - z = x607 - z = x608 - z = x609 - z = x610 - z = x611 - z = x612 - z = x613 - z = x614 - z = x615 - z = x616 - z = x617 - z = x618 - z = x619 - z = x620 - z = x621 - z = x622 - z = x623 - z = x624 - z = x625 - z = x626 - z = x627 - z = x628 - z = x629 - z = x630 - z = x631 - z = x632 - z = x633 - z = x634 - z = x635 - z = x636 - z = x637 - z = x638 - z = x639 - z = x640 - z = x641 - z = x642 - z = x643 - z = x644 - z = x645 - z = x646 - z = x647 - z = x648 - z = x649 - z = x650 - z = x651 - z = x652 - z = x653 - z = x654 - z = x655 - z = x656 - z = x657 - z = x658 - z = x659 - z = x660 - z = x661 - z = x662 - z = x663 - z = x664 - z = x665 - z = x666 - z = x667 - z = x668 - z = x669 - z = x670 - z = x671 - z = x672 - z = x673 - z = x674 - z = x675 - z = x676 - z = x677 - z = x678 - z = x679 - z = x680 - z = x681 - z = x682 - z = x683 - z = x684 - z = x685 - z = x686 - z = x687 - z = x688 - z = x689 - z = x690 - z = x691 - z = x692 - z = x693 - z = x694 - z = x695 - z = x696 - z = x697 - z = x698 - z = x699 - z = x700 - z = x701 - z = x702 - z = x703 - z = x704 - z = x705 - z = x706 - z = x707 - z = x708 - z = x709 - z = x710 - z = x711 - z = x712 - z = x713 - z = x714 - z = x715 - z = x716 - z = x717 - z = x718 - z = x719 - z = x720 - z = x721 - z = x722 - z = x723 - z = x724 - z = x725 - z = x726 - z = x727 - z = x728 - z = x729 - z = x730 - z = x731 - z = x732 - z = x733 - z = x734 - z = x735 - z = x736 - z = x737 - z = x738 - z = x739 - z = x740 - z = x741 - z = x742 - z = x743 - z = x744 - z = x745 - z = x746 - z = x747 - z = x748 - z = x749 - z = x750 - z = x751 - z = x752 - z = x753 - z = x754 - z = x755 - z = x756 - z = x757 - z = x758 - z = x759 - z = x760 - z = x761 - z = x762 - z = x763 - z = x764 - z = x765 - z = x766 - z = x767 - z = x768 - z = x769 - z = x770 - z = x771 - z = x772 - z = x773 - z = x774 - z = x775 - z = x776 - z = x777 - z = x778 - z = x779 - z = x780 - z = x781 - z = x782 - z = x783 - z = x784 - z = x785 - z = x786 - z = x787 - z = x788 - z = x789 - z = x790 - z = x791 - z = x792 - z = x793 - z = x794 - z = x795 - z = x796 - z = x797 - z = x798 - z = x799 - z = x800 - z = x801 - z = x802 - z = x803 - z = x804 - z = x805 - z = x806 - z = x807 - z = x808 - z = x809 - z = x810 - z = x811 - z = x812 - z = x813 - z = x814 - z = x815 - z = x816 - z = x817 - z = x818 - z = x819 - z = x820 - z = x821 - z = x822 - z = x823 - z = x824 - z = x825 - z = x826 - z = x827 - z = x828 - z = x829 - z = x830 - z = x831 - z = x832 - z = x833 - z = x834 - z = x835 - z = x836 - z = x837 - z = x838 - z = x839 - z = x840 - z = x841 - z = x842 - z = x843 - z = x844 - z = x845 - z = x846 - z = x847 - z = x848 - z = x849 - z = x850 - z = x851 - z = x852 - z = x853 - z = x854 - z = x855 - z = x856 - z = x857 - z = x858 - z = x859 - z = x860 - z = x861 - z = x862 - z = x863 - z = x864 - z = x865 - z = x866 - z = x867 - z = x868 - z = x869 - z = x870 - z = x871 - z = x872 - z = x873 - z = x874 - z = x875 - z = x876 - z = x877 - z = x878 - z = x879 - z = x880 - z = x881 - z = x882 - z = x883 - z = x884 - z = x885 - z = x886 - z = x887 - z = x888 - z = x889 - z = x890 - z = x891 - z = x892 - z = x893 - z = x894 - z = x895 - z = x896 - z = x897 - z = x898 - z = x899 - z = x900 - z = x901 - z = x902 - z = x903 - z = x904 - z = x905 - z = x906 - z = x907 - z = x908 - z = x909 - z = x910 - z = x911 - z = x912 - z = x913 - z = x914 - z = x915 - z = x916 - z = x917 - z = x918 - z = x919 - z = x920 - z = x921 - z = x922 - z = x923 - z = x924 - z = x925 - z = x926 - z = x927 - z = x928 - z = x929 - z = x930 - z = x931 - z = x932 - z = x933 - z = x934 - z = x935 - z = x936 - z = x937 - z = x938 - z = x939 - z = x940 - z = x941 - z = x942 - z = x943 - z = x944 - z = x945 - z = x946 - z = x947 - z = x948 - z = x949 - z = x950 - z = x951 - z = x952 - z = x953 - z = x954 - z = x955 - z = x956 - z = x957 - z = x958 - z = x959 - z = x960 - z = x961 - z = x962 - z = x963 - z = x964 - z = x965 - z = x966 - z = x967 - z = x968 - z = x969 - z = x970 - z = x971 - z = x972 - z = x973 - z = x974 - z = x975 - z = x976 - z = x977 - z = x978 - z = x979 - z = x980 - z = x981 - z = x982 - z = x983 - z = x984 - z = x985 - z = x986 - z = x987 - z = x988 - z = x989 - z = x990 - z = x991 - z = x992 - z = x993 - z = x994 - z = x995 - z = x996 - z = x997 - z = x998 - z = x999 - z = x1000 - z = x1001 - z = x1002 - z = x1003 - z = x1004 - z = x1005 - z = x1006 - z = x1007 - z = x1008 - z = x1009 - z = x1010 - z = x1011 - z = x1012 - z = x1013 - z = x1014 - z = x1015 - z = x1016 - z = x1017 - z = x1018 - z = x1019 - z = x1020 - z = x1021 - z = x1022 - z = x1023 - z = x1024 - z = x1025 - z = x1026 - z = x1027 - z = x1028 - z = x1029 - z = x1030 - z = x1031 - z = x1032 - z = x1033 - z = x1034 - z = x1035 - z = x1036 - z = x1037 - z = x1038 - z = x1039 - z = x1040 - z = x1041 - z = x1042 - z = x1043 - z = x1044 - z = x1045 - z = x1046 - z = x1047 - z = x1048 - z = x1049 - z = x1050 - z = x1051 - z = x1052 - z = x1053 - z = x1054 - z = x1055 - z = x1056 - z = x1057 - z = x1058 - z = x1059 - z = x1060 - z = x1061 - z = x1062 - z = x1063 - z = x1064 - z = x1065 - z = x1066 - z = x1067 - z = x1068 - z = x1069 - z = x1070 - z = x1071 - z = x1072 - z = x1073 - z = x1074 - z = x1075 - z = x1076 - z = x1077 - z = x1078 - z = x1079 - z = x1080 - z = x1081 - z = x1082 - z = x1083 - z = x1084 - z = x1085 - z = x1086 - z = x1087 - z = x1088 - z = x1089 - z = x1090 - z = x1091 - z = x1092 - z = x1093 - z = x1094 - z = x1095 - z = x1096 - z = x1097 - z = x1098 - z = x1099 - z = x1100 - z = x1101 - z = x1102 - z = x1103 - z = x1104 - z = x1105 - z = x1106 - z = x1107 - z = x1108 - z = x1109 - z = x1110 - z = x1111 - z = x1112 - z = x1113 - z = x1114 - z = x1115 - z = x1116 - z = x1117 - z = x1118 - z = x1119 - z = x1120 - z = x1121 - z = x1122 - z = x1123 - z = x1124 - z = x1125 - z = x1126 - z = x1127 - z = x1128 - z = x1129 - z = x1130 - z = x1131 - z = x1132 - z = x1133 - z = x1134 - z = x1135 - z = x1136 - z = x1137 - z = x1138 - z = x1139 - z = x1140 - z = x1141 - z = x1142 - z = x1143 - z = x1144 - z = x1145 - z = x1146 - z = x1147 - z = x1148 - z = x1149 - z = x1150 - z = x1151 - z = x1152 - z = x1153 - z = x1154 - z = x1155 - z = x1156 - z = x1157 - z = x1158 - z = x1159 - z = x1160 - z = x1161 - z = x1162 - z = x1163 - z = x1164 - z = x1165 - z = x1166 - z = x1167 - z = x1168 - z = x1169 - z = x1170 - z = x1171 - z = x1172 - z = x1173 - z = x1174 - z = x1175 - z = x1176 - z = x1177 - z = x1178 - z = x1179 - z = x1180 - z = x1181 - z = x1182 - z = x1183 - z = x1184 - z = x1185 - z = x1186 - z = x1187 - z = x1188 - z = x1189 - z = x1190 - z = x1191 - z = x1192 - z = x1193 - z = x1194 - z = x1195 - z = x1196 - z = x1197 - z = x1198 - z = x1199 - z = x1200 - z = x1201 - z = x1202 - z = x1203 - z = x1204 - z = x1205 - z = x1206 - z = x1207 - z = x1208 - z = x1209 - z = x1210 - z = x1211 - z = x1212 - z = x1213 - z = x1214 - z = x1215 - z = x1216 - z = x1217 - z = x1218 - z = x1219 - z = x1220 - z = x1221 - z = x1222 - z = x1223 - z = x1224 - z = x1225 - z = x1226 - z = x1227 - z = x1228 - z = x1229 - z = x1230 - z = x1231 - z = x1232 - z = x1233 - z = x1234 - z = x1235 - z = x1236 - z = x1237 - z = x1238 - z = x1239 - z = x1240 - z = x1241 - z = x1242 - z = x1243 - z = x1244 - z = x1245 - z = x1246 - z = x1247 - z = x1248 - z = x1249 - z = x1250 - z = x1251 - z = x1252 - z = x1253 - z = x1254 - z = x1255 - z = x1256 - z = x1257 - z = x1258 - z = x1259 - z = x1260 - z = x1261 - z = x1262 - z = x1263 - z = x1264 - z = x1265 - z = x1266 - z = x1267 - z = x1268 - z = x1269 - z = x1270 - z = x1271 - z = x1272 - z = x1273 - z = x1274 - z = x1275 - z = x1276 - z = x1277 - z = x1278 - z = x1279 - z = x1280 - z = x1281 - z = x1282 - z = x1283 - z = x1284 - z = x1285 - z = x1286 - z = x1287 - z = x1288 - z = x1289 - z = x1290 - z = x1291 - z = x1292 - z = x1293 - z = x1294 - z = x1295 - z = x1296 - z = x1297 - z = x1298 - z = x1299 - z = x1300 - z = x1301 - z = x1302 - z = x1303 - z = x1304 - z = x1305 - z = x1306 - z = x1307 - z = x1308 - z = x1309 - z = x1310 - z = x1311 - z = x1312 - z = x1313 - z = x1314 - z = x1315 - z = x1316 - z = x1317 - z = x1318 - z = x1319 - z = x1320 - z = x1321 - z = x1322 - z = x1323 - z = x1324 - z = x1325 - z = x1326 - z = x1327 - z = x1328 - z = x1329 - z = x1330 - z = x1331 - z = x1332 - z = x1333 - z = x1334 - z = x1335 - z = x1336 - z = x1337 - z = x1338 - z = x1339 - z = x1340 - z = x1341 - z = x1342 - z = x1343 - z = x1344 - z = x1345 - z = x1346 - z = x1347 - z = x1348 - z = x1349 - z = x1350 - z = x1351 - z = x1352 - z = x1353 - z = x1354 - z = x1355 - z = x1356 - z = x1357 - z = x1358 - z = x1359 - z = x1360 - z = x1361 - z = x1362 - z = x1363 - z = x1364 - z = x1365 - z = x1366 - z = x1367 - z = x1368 - z = x1369 - z = x1370 - z = x1371 - z = x1372 - z = x1373 - z = x1374 - z = x1375 - z = x1376 - z = x1377 - z = x1378 - z = x1379 - z = x1380 - z = x1381 - z = x1382 - z = x1383 - z = x1384 - z = x1385 - z = x1386 - z = x1387 - z = x1388 - z = x1389 - z = x1390 - z = x1391 - z = x1392 - z = x1393 - z = x1394 - z = x1395 - z = x1396 - z = x1397 - z = x1398 - z = x1399 - z = x1400 - z = x1401 - z = x1402 - z = x1403 - z = x1404 - z = x1405 - z = x1406 - z = x1407 - z = x1408 - z = x1409 - z = x1410 - z = x1411 - z = x1412 - z = x1413 - z = x1414 - z = x1415 - z = x1416 - z = x1417 - z = x1418 - z = x1419 - z = x1420 - z = x1421 - z = x1422 - z = x1423 - z = x1424 - z = x1425 - z = x1426 - z = x1427 - z = x1428 - z = x1429 - z = x1430 - z = x1431 - z = x1432 - z = x1433 - z = x1434 - z = x1435 - z = x1436 - z = x1437 - z = x1438 - z = x1439 - z = x1440 - z = x1441 - z = x1442 - z = x1443 - z = x1444 - z = x1445 - z = x1446 - z = x1447 - z = x1448 - z = x1449 - z = x1450 - z = x1451 - z = x1452 - z = x1453 - z = x1454 - z = x1455 - z = x1456 - z = x1457 - z = x1458 - z = x1459 - z = x1460 - z = x1461 - z = x1462 - z = x1463 - z = x1464 - z = x1465 - z = x1466 - z = x1467 - z = x1468 - z = x1469 - z = x1470 - z = x1471 - z = x1472 - z = x1473 - z = x1474 - z = x1475 - z = x1476 - z = x1477 - z = x1478 - z = x1479 - z = x1480 - z = x1481 - z = x1482 - z = x1483 - z = x1484 - z = x1485 - z = x1486 - z = x1487 - z = x1488 - z = x1489 - z = x1490 - z = x1491 - z = x1492 - z = x1493 - z = x1494 - z = x1495 - z = x1496 - z = x1497 - z = x1498 - z = x1499 - z = x1500 - z = x1501 - z = x1502 - z = x1503 - z = x1504 - z = x1505 - z = x1506 - z = x1507 - z = x1508 - z = x1509 - z = x1510 - z = x1511 - z = x1512 - z = x1513 - z = x1514 - z = x1515 - z = x1516 - z = x1517 - z = x1518 - z = x1519 - z = x1520 - z = x1521 - z = x1522 - z = x1523 - z = x1524 - z = x1525 - z = x1526 - z = x1527 - z = x1528 - z = x1529 - z = x1530 - z = x1531 - z = x1532 - z = x1533 - z = x1534 - z = x1535 - z = x1536 - z = x1537 - z = x1538 - z = x1539 - z = x1540 - z = x1541 - z = x1542 - z = x1543 - z = x1544 - z = x1545 - z = x1546 - z = x1547 - z = x1548 - z = x1549 - z = x1550 - z = x1551 - z = x1552 - z = x1553 - z = x1554 - z = x1555 - z = x1556 - z = x1557 - z = x1558 - z = x1559 - z = x1560 - z = x1561 - z = x1562 - z = x1563 - z = x1564 - z = x1565 - z = x1566 - z = x1567 - z = x1568 - z = x1569 - z = x1570 - z = x1571 - z = x1572 - z = x1573 - z = x1574 - z = x1575 - z = x1576 - z = x1577 - z = x1578 - z = x1579 - z = x1580 - z = x1581 - z = x1582 - z = x1583 - z = x1584 - z = x1585 - z = x1586 - z = x1587 - z = x1588 - z = x1589 - z = x1590 - z = x1591 - z = x1592 - z = x1593 - z = x1594 - z = x1595 - z = x1596 - z = x1597 - z = x1598 - z = x1599 - z = x1600 - z = x1601 - z = x1602 - z = x1603 - z = x1604 - z = x1605 - z = x1606 - z = x1607 - z = x1608 - z = x1609 - z = x1610 - z = x1611 - z = x1612 - z = x1613 - z = x1614 - z = x1615 - z = x1616 - z = x1617 - z = x1618 - z = x1619 - z = x1620 - z = x1621 - z = x1622 - z = x1623 - z = x1624 - z = x1625 - z = x1626 - z = x1627 - z = x1628 - z = x1629 - z = x1630 - z = x1631 - z = x1632 - z = x1633 - z = x1634 - z = x1635 - z = x1636 - z = x1637 - z = x1638 - z = x1639 - z = x1640 - z = x1641 - z = x1642 - z = x1643 - z = x1644 - z = x1645 - z = x1646 - z = x1647 - z = x1648 - z = x1649 - z = x1650 - z = x1651 - z = x1652 - z = x1653 - z = x1654 - z = x1655 - z = x1656 - z = x1657 - z = x1658 - z = x1659 - z = x1660 - z = x1661 - z = x1662 - z = x1663 - z = x1664 - z = x1665 - z = x1666 - z = x1667 - z = x1668 - z = x1669 - z = x1670 - z = x1671 - z = x1672 - z = x1673 - z = x1674 - z = x1675 - z = x1676 - z = x1677 - z = x1678 - z = x1679 - z = x1680 - z = x1681 - z = x1682 - z = x1683 - z = x1684 - z = x1685 - z = x1686 - z = x1687 - z = x1688 - z = x1689 - z = x1690 - z = x1691 - z = x1692 - z = x1693 - z = x1694 - z = x1695 - z = x1696 - z = x1697 - z = x1698 - z = x1699 - z = x1700 - z = x1701 - z = x1702 - z = x1703 - z = x1704 - z = x1705 - z = x1706 - z = x1707 - z = x1708 - z = x1709 - z = x1710 - z = x1711 - z = x1712 - z = x1713 - z = x1714 - z = x1715 - z = x1716 - z = x1717 - z = x1718 - z = x1719 - z = x1720 - z = x1721 - z = x1722 - z = x1723 - z = x1724 - z = x1725 - z = x1726 - z = x1727 - z = x1728 - z = x1729 - z = x1730 - z = x1731 - z = x1732 - z = x1733 - z = x1734 - z = x1735 - z = x1736 - z = x1737 - z = x1738 - z = x1739 - z = x1740 - z = x1741 - z = x1742 - z = x1743 - z = x1744 - z = x1745 - z = x1746 - z = x1747 - z = x1748 - z = x1749 - z = x1750 - z = x1751 - z = x1752 - z = x1753 - z = x1754 - z = x1755 - z = x1756 - z = x1757 - z = x1758 - z = x1759 - z = x1760 - z = x1761 - z = x1762 - z = x1763 - z = x1764 - z = x1765 - z = x1766 - z = x1767 - z = x1768 - z = x1769 - z = x1770 - z = x1771 - z = x1772 - z = x1773 - z = x1774 - z = x1775 - z = x1776 - z = x1777 - z = x1778 - z = x1779 - z = x1780 - z = x1781 - z = x1782 - z = x1783 - z = x1784 - z = x1785 - z = x1786 - z = x1787 - z = x1788 - z = x1789 - z = x1790 - z = x1791 - z = x1792 - z = x1793 - z = x1794 - z = x1795 - z = x1796 - z = x1797 - z = x1798 - z = x1799 - z = x1800 - z = x1801 - z = x1802 - z = x1803 - z = x1804 - z = x1805 - z = x1806 - z = x1807 - z = x1808 - z = x1809 - z = x1810 - z = x1811 - z = x1812 - z = x1813 - z = x1814 - z = x1815 - z = x1816 - z = x1817 - z = x1818 - z = x1819 - z = x1820 - z = x1821 - z = x1822 - z = x1823 - z = x1824 - z = x1825 - z = x1826 - z = x1827 - z = x1828 - z = x1829 - z = x1830 - z = x1831 - z = x1832 - z = x1833 - z = x1834 - z = x1835 - z = x1836 - z = x1837 - z = x1838 - z = x1839 - z = x1840 - z = x1841 - z = x1842 - z = x1843 - z = x1844 - z = x1845 - z = x1846 - z = x1847 - z = x1848 - z = x1849 - z = x1850 - z = x1851 - z = x1852 - z = x1853 - z = x1854 - z = x1855 - z = x1856 - z = x1857 - z = x1858 - z = x1859 - z = x1860 - z = x1861 - z = x1862 - z = x1863 - z = x1864 - z = x1865 - z = x1866 - z = x1867 - z = x1868 - z = x1869 - z = x1870 - z = x1871 - z = x1872 - z = x1873 - z = x1874 - z = x1875 - z = x1876 - z = x1877 - z = x1878 - z = x1879 - z = x1880 - z = x1881 - z = x1882 - z = x1883 - z = x1884 - z = x1885 - z = x1886 - z = x1887 - z = x1888 - z = x1889 - z = x1890 - z = x1891 - z = x1892 - z = x1893 - z = x1894 - z = x1895 - z = x1896 - z = x1897 - z = x1898 - z = x1899 - z = x1900 - z = x1901 - z = x1902 - z = x1903 - z = x1904 - z = x1905 - z = x1906 - z = x1907 - z = x1908 - z = x1909 - z = x1910 - z = x1911 - z = x1912 - z = x1913 - z = x1914 - z = x1915 - z = x1916 - z = x1917 - z = x1918 - z = x1919 - z = x1920 - z = x1921 - z = x1922 - z = x1923 - z = x1924 - z = x1925 - z = x1926 - z = x1927 - z = x1928 - z = x1929 - z = x1930 - z = x1931 - z = x1932 - z = x1933 - z = x1934 - z = x1935 - z = x1936 - z = x1937 - z = x1938 - z = x1939 - z = x1940 - z = x1941 - z = x1942 - z = x1943 - z = x1944 - z = x1945 - z = x1946 - z = x1947 - z = x1948 - z = x1949 - z = x1950 - z = x1951 - z = x1952 - z = x1953 - z = x1954 - z = x1955 - z = x1956 - z = x1957 - z = x1958 - z = x1959 - z = x1960 - z = x1961 - z = x1962 - z = x1963 - z = x1964 - z = x1965 - z = x1966 - z = x1967 - z = x1968 - z = x1969 - z = x1970 - z = x1971 - z = x1972 - z = x1973 - z = x1974 - z = x1975 - z = x1976 - z = x1977 - z = x1978 - z = x1979 - z = x1980 - z = x1981 - z = x1982 - z = x1983 - z = x1984 - z = x1985 - z = x1986 - z = x1987 - z = x1988 - z = x1989 - z = x1990 - z = x1991 - z = x1992 - z = x1993 - z = x1994 - z = x1995 - z = x1996 - z = x1997 - z = x1998 - z = x1999 - z = x2000 - z = x2001 - z = x2002 - z = x2003 - z = x2004 - z = x2005 - z = x2006 - z = x2007 - z = x2008 - z = x2009 - z = x2010 - z = x2011 - z = x2012 - z = x2013 - z = x2014 - z = x2015 - z = x2016 - z = x2017 - z = x2018 - z = x2019 - z = x2020 - z = x2021 - z = x2022 - z = x2023 - z = x2024 - z = x2025 - z = x2026 - z = x2027 - z = x2028 - z = x2029 - z = x2030 - z = x2031 - z = x2032 - z = x2033 - z = x2034 - z = x2035 - z = x2036 - z = x2037 - z = x2038 - z = x2039 - z = x2040 - z = x2041 - z = x2042 - z = x2043 - z = x2044 - z = x2045 - z = x2046 - z = x2047 - z = x2048 - z = x2049 - z = x2050 - z = x2051 - z = x2052 - z = x2053 - z = x2054 - z = x2055 - z = x2056 - z = x2057 - z = x2058 - z = x2059 - z = x2060 - z = x2061 - z = x2062 - z = x2063 - z = x2064 - z = x2065 - z = x2066 - z = x2067 - z = x2068 - z = x2069 - z = x2070 - z = x2071 - z = x2072 - z = x2073 - z = x2074 - z = x2075 - z = x2076 - z = x2077 - z = x2078 - z = x2079 - z = x2080 - z = x2081 - z = x2082 - z = x2083 - z = x2084 - z = x2085 - z = x2086 - z = x2087 - z = x2088 - z = x2089 - z = x2090 - z = x2091 - z = x2092 - z = x2093 - z = x2094 - z = x2095 - z = x2096 - z = x2097 - z = x2098 - z = x2099 - z = x2100 - z = x2101 - z = x2102 - z = x2103 - z = x2104 - z = x2105 - z = x2106 - z = x2107 - z = x2108 - z = x2109 - z = x2110 - z = x2111 - z = x2112 - z = x2113 - z = x2114 - z = x2115 - z = x2116 - z = x2117 - z = x2118 - z = x2119 - z = x2120 - z = x2121 - z = x2122 - z = x2123 - z = x2124 - z = x2125 - z = x2126 - z = x2127 - z = x2128 - z = x2129 - z = x2130 - z = x2131 - z = x2132 - z = x2133 - z = x2134 - z = x2135 - z = x2136 - z = x2137 - z = x2138 - z = x2139 - z = x2140 - z = x2141 - z = x2142 - z = x2143 - z = x2144 - z = x2145 - z = x2146 - z = x2147 - z = x2148 - z = x2149 - z = x2150 - z = x2151 - z = x2152 - z = x2153 - z = x2154 - z = x2155 - z = x2156 - z = x2157 - z = x2158 - z = x2159 - z = x2160 - z = x2161 - z = x2162 - z = x2163 - z = x2164 - z = x2165 - z = x2166 - z = x2167 - z = x2168 - z = x2169 - z = x2170 - z = x2171 - z = x2172 - z = x2173 - z = x2174 - z = x2175 - z = x2176 - z = x2177 - z = x2178 - z = x2179 - z = x2180 - z = x2181 - z = x2182 - z = x2183 - z = x2184 - z = x2185 - z = x2186 - z = x2187 - z = x2188 - z = x2189 - z = x2190 - z = x2191 - z = x2192 - z = x2193 - z = x2194 - z = x2195 - z = x2196 - z = x2197 - z = x2198 - z = x2199 - z = x2200 - z = x2201 - z = x2202 - z = x2203 - z = x2204 - z = x2205 - z = x2206 - z = x2207 - z = x2208 - z = x2209 - z = x2210 - z = x2211 - z = x2212 - z = x2213 - z = x2214 - z = x2215 - z = x2216 - z = x2217 - z = x2218 - z = x2219 - z = x2220 - z = x2221 - z = x2222 - z = x2223 - z = x2224 - z = x2225 - z = x2226 - z = x2227 - z = x2228 - z = x2229 - z = x2230 - z = x2231 - z = x2232 - z = x2233 - z = x2234 - z = x2235 - z = x2236 - z = x2237 - z = x2238 - z = x2239 - z = x2240 - z = x2241 - z = x2242 - z = x2243 - z = x2244 - z = x2245 - z = x2246 - z = x2247 - z = x2248 - z = x2249 - z = x2250 - z = x2251 - z = x2252 - z = x2253 - z = x2254 - z = x2255 - z = x2256 - z = x2257 - z = x2258 - z = x2259 - z = x2260 - z = x2261 - z = x2262 - z = x2263 - z = x2264 - z = x2265 - z = x2266 - z = x2267 - z = x2268 - z = x2269 - z = x2270 - z = x2271 - z = x2272 - z = x2273 - z = x2274 - z = x2275 - z = x2276 - z = x2277 - z = x2278 - z = x2279 - z = x2280 - z = x2281 - z = x2282 - z = x2283 - z = x2284 - z = x2285 - z = x2286 - z = x2287 - z = x2288 - z = x2289 - z = x2290 - z = x2291 - z = x2292 - z = x2293 - z = x2294 - z = x2295 - z = x2296 - z = x2297 - z = x2298 - z = x2299 - z = x2300 - z = x2301 - z = x2302 - z = x2303 - z = x2304 - z = x2305 - z = x2306 - z = x2307 - z = x2308 - z = x2309 - z = x2310 - z = x2311 - z = x2312 - z = x2313 - z = x2314 - z = x2315 - z = x2316 - z = x2317 - z = x2318 - z = x2319 - z = x2320 - z = x2321 - z = x2322 - z = x2323 - z = x2324 - z = x2325 - z = x2326 - z = x2327 - z = x2328 - z = x2329 - z = x2330 - z = x2331 - z = x2332 - z = x2333 - z = x2334 - z = x2335 - z = x2336 - z = x2337 - z = x2338 - z = x2339 - z = x2340 - z = x2341 - z = x2342 - z = x2343 - z = x2344 - z = x2345 - z = x2346 - z = x2347 - z = x2348 - z = x2349 - z = x2350 - z = x2351 - z = x2352 - z = x2353 - z = x2354 - z = x2355 - z = x2356 - z = x2357 - z = x2358 - z = x2359 - z = x2360 - z = x2361 - z = x2362 - z = x2363 - z = x2364 - z = x2365 - z = x2366 - z = x2367 - z = x2368 - z = x2369 - z = x2370 - z = x2371 - z = x2372 - z = x2373 - z = x2374 - z = x2375 - z = x2376 - z = x2377 - z = x2378 - z = x2379 - z = x2380 - z = x2381 - z = x2382 - z = x2383 - z = x2384 - z = x2385 - z = x2386 - z = x2387 - z = x2388 - z = x2389 - z = x2390 - z = x2391 - z = x2392 - z = x2393 - z = x2394 - z = x2395 - z = x2396 - z = x2397 - z = x2398 - z = x2399 - z = x2400 - z = x2401 - z = x2402 - z = x2403 - z = x2404 - z = x2405 - z = x2406 - z = x2407 - z = x2408 - z = x2409 - z = x2410 - z = x2411 - z = x2412 - z = x2413 - z = x2414 - z = x2415 - z = x2416 - z = x2417 - z = x2418 - z = x2419 - z = x2420 - z = x2421 - z = x2422 - z = x2423 - z = x2424 - z = x2425 - z = x2426 - z = x2427 - z = x2428 - z = x2429 - z = x2430 - z = x2431 - z = x2432 - z = x2433 - z = x2434 - z = x2435 - z = x2436 - z = x2437 - z = x2438 - z = x2439 - z = x2440 - z = x2441 - z = x2442 - z = x2443 - z = x2444 - z = x2445 - z = x2446 - z = x2447 - z = x2448 - z = x2449 - z = x2450 - z = x2451 - z = x2452 - z = x2453 - z = x2454 - z = x2455 - z = x2456 - z = x2457 - z = x2458 - z = x2459 - z = x2460 - z = x2461 - z = x2462 - z = x2463 - z = x2464 - z = x2465 - z = x2466 - z = x2467 - z = x2468 - z = x2469 - z = x2470 - z = x2471 - z = x2472 - z = x2473 - z = x2474 - z = x2475 - z = x2476 - z = x2477 - z = x2478 - z = x2479 - z = x2480 - z = x2481 - z = x2482 - z = x2483 - z = x2484 - z = x2485 - z = x2486 - z = x2487 - z = x2488 - z = x2489 - z = x2490 - z = x2491 - z = x2492 - z = x2493 - z = x2494 - z = x2495 - z = x2496 - z = x2497 - z = x2498 - z = x2499 - z = x2500 - z = x2501 - z = x2502 - z = x2503 - z = x2504 - z = x2505 - z = x2506 - z = x2507 - z = x2508 - z = x2509 - z = x2510 - z = x2511 - z = x2512 - z = x2513 - z = x2514 - z = x2515 - z = x2516 - z = x2517 - z = x2518 - z = x2519 - z = x2520 - z = x2521 - z = x2522 - z = x2523 - z = x2524 - z = x2525 - z = x2526 - z = x2527 - z = x2528 - z = x2529 - z = x2530 - z = x2531 - z = x2532 - z = x2533 - z = x2534 - z = x2535 - z = x2536 - z = x2537 - z = x2538 - z = x2539 - z = x2540 - z = x2541 - z = x2542 - z = x2543 - z = x2544 - z = x2545 - z = x2546 - z = x2547 - z = x2548 - z = x2549 - z = x2550 - z = x2551 - z = x2552 - z = x2553 - z = x2554 - z = x2555 - z = x2556 - z = x2557 - z = x2558 - z = x2559 - z = x2560 - z = x2561 - z = x2562 - z = x2563 - z = x2564 - z = x2565 - z = x2566 - z = x2567 - z = x2568 - z = x2569 - z = x2570 - z = x2571 - z = x2572 - z = x2573 - z = x2574 - z = x2575 - z = x2576 - z = x2577 - z = x2578 - z = x2579 - z = x2580 - z = x2581 - z = x2582 - z = x2583 - z = x2584 - z = x2585 - z = x2586 - z = x2587 - z = x2588 - z = x2589 - z = x2590 - z = x2591 - z = x2592 - z = x2593 - z = x2594 - z = x2595 - z = x2596 - z = x2597 - z = x2598 - z = x2599 - z = x2600 - z = x2601 - z = x2602 - z = x2603 - z = x2604 - z = x2605 - z = x2606 - z = x2607 - z = x2608 - z = x2609 - z = x2610 - z = x2611 - z = x2612 - z = x2613 - z = x2614 - z = x2615 - z = x2616 - z = x2617 - z = x2618 - z = x2619 - z = x2620 - z = x2621 - z = x2622 - z = x2623 - z = x2624 - z = x2625 - z = x2626 - z = x2627 - z = x2628 - z = x2629 - z = x2630 - z = x2631 - z = x2632 - z = x2633 - z = x2634 - z = x2635 - z = x2636 - z = x2637 - z = x2638 - z = x2639 - z = x2640 - z = x2641 - z = x2642 - z = x2643 - z = x2644 - z = x2645 - z = x2646 - z = x2647 - z = x2648 - z = x2649 - z = x2650 - z = x2651 - z = x2652 - z = x2653 - z = x2654 - z = x2655 - z = x2656 - z = x2657 - z = x2658 - z = x2659 - z = x2660 - z = x2661 - z = x2662 - z = x2663 - z = x2664 - z = x2665 - z = x2666 - z = x2667 - z = x2668 - z = x2669 - z = x2670 - z = x2671 - z = x2672 - z = x2673 - z = x2674 - z = x2675 - z = x2676 - z = x2677 - z = x2678 - z = x2679 - z = x2680 - z = x2681 - z = x2682 - z = x2683 - z = x2684 - z = x2685 - z = x2686 - z = x2687 - z = x2688 - z = x2689 - z = x2690 - z = x2691 - z = x2692 - z = x2693 - z = x2694 - z = x2695 - z = x2696 - z = x2697 - z = x2698 - z = x2699 - z = x2700 - z = x2701 - z = x2702 - z = x2703 - z = x2704 - z = x2705 - z = x2706 - z = x2707 - z = x2708 - z = x2709 - z = x2710 - z = x2711 - z = x2712 - z = x2713 - z = x2714 - z = x2715 - z = x2716 - z = x2717 - z = x2718 - z = x2719 - z = x2720 - z = x2721 - z = x2722 - z = x2723 - z = x2724 - z = x2725 - z = x2726 - z = x2727 - z = x2728 - z = x2729 - z = x2730 - z = x2731 - z = x2732 - z = x2733 - z = x2734 - z = x2735 - z = x2736 - z = x2737 - z = x2738 - z = x2739 - z = x2740 - z = x2741 - z = x2742 - z = x2743 - z = x2744 - z = x2745 - z = x2746 - z = x2747 - z = x2748 - z = x2749 - z = x2750 - z = x2751 - z = x2752 - z = x2753 - z = x2754 - z = x2755 - z = x2756 - z = x2757 - z = x2758 - z = x2759 - z = x2760 - z = x2761 - z = x2762 - z = x2763 - z = x2764 - z = x2765 - z = x2766 - z = x2767 - z = x2768 - z = x2769 - z = x2770 - z = x2771 - z = x2772 - z = x2773 - z = x2774 - z = x2775 - z = x2776 - z = x2777 - z = x2778 - z = x2779 - z = x2780 - z = x2781 - z = x2782 - z = x2783 - z = x2784 - z = x2785 - z = x2786 - z = x2787 - z = x2788 - z = x2789 - z = x2790 - z = x2791 - z = x2792 - z = x2793 - z = x2794 - z = x2795 - z = x2796 - z = x2797 - z = x2798 - z = x2799 - z = x2800 - z = x2801 - z = x2802 - z = x2803 - z = x2804 - z = x2805 - z = x2806 - z = x2807 - z = x2808 - z = x2809 - z = x2810 - z = x2811 - z = x2812 - z = x2813 - z = x2814 - z = x2815 - z = x2816 - z = x2817 - z = x2818 - z = x2819 - z = x2820 - z = x2821 - z = x2822 - z = x2823 - z = x2824 - z = x2825 - z = x2826 - z = x2827 - z = x2828 - z = x2829 - z = x2830 - z = x2831 - z = x2832 - z = x2833 - z = x2834 - z = x2835 - z = x2836 - z = x2837 - z = x2838 - z = x2839 - z = x2840 - z = x2841 - z = x2842 - z = x2843 - z = x2844 - z = x2845 - z = x2846 - z = x2847 - z = x2848 - z = x2849 - z = x2850 - z = x2851 - z = x2852 - z = x2853 - z = x2854 - z = x2855 - z = x2856 - z = x2857 - z = x2858 - z = x2859 - z = x2860 - z = x2861 - z = x2862 - z = x2863 - z = x2864 - z = x2865 - z = x2866 - z = x2867 - z = x2868 - z = x2869 - z = x2870 - z = x2871 - z = x2872 - z = x2873 - z = x2874 - z = x2875 - z = x2876 - z = x2877 - z = x2878 - z = x2879 - z = x2880 - z = x2881 - z = x2882 - z = x2883 - z = x2884 - z = x2885 - z = x2886 - z = x2887 - z = x2888 - z = x2889 - z = x2890 - z = x2891 - z = x2892 - z = x2893 - z = x2894 - z = x2895 - z = x2896 - z = x2897 - z = x2898 - z = x2899 - z = x2900 - z = x2901 - z = x2902 - z = x2903 - z = x2904 - z = x2905 - z = x2906 - z = x2907 - z = x2908 - z = x2909 - z = x2910 - z = x2911 - z = x2912 - z = x2913 - z = x2914 - z = x2915 - z = x2916 - z = x2917 - z = x2918 - z = x2919 - z = x2920 - z = x2921 - z = x2922 - z = x2923 - z = x2924 - z = x2925 - z = x2926 - z = x2927 - z = x2928 - z = x2929 - z = x2930 - z = x2931 - z = x2932 - z = x2933 - z = x2934 - z = x2935 - z = x2936 - z = x2937 - z = x2938 - z = x2939 - z = x2940 - z = x2941 - z = x2942 - z = x2943 - z = x2944 - z = x2945 - z = x2946 - z = x2947 - z = x2948 - z = x2949 - z = x2950 - z = x2951 - z = x2952 - z = x2953 - z = x2954 - z = x2955 - z = x2956 - z = x2957 - z = x2958 - z = x2959 - z = x2960 - z = x2961 - z = x2962 - z = x2963 - z = x2964 - z = x2965 - z = x2966 - z = x2967 - z = x2968 - z = x2969 - z = x2970 - z = x2971 - z = x2972 - z = x2973 - z = x2974 - z = x2975 - z = x2976 - z = x2977 - z = x2978 - z = x2979 - z = x2980 - z = x2981 - z = x2982 - z = x2983 - z = x2984 - z = x2985 - z = x2986 - z = x2987 - z = x2988 - z = x2989 - z = x2990 - z = x2991 - z = x2992 - z = x2993 - z = x2994 - z = x2995 - z = x2996 - z = x2997 - z = x2998 - z = x2999 - z = x3000 - z = x3001 - z = x3002 - z = x3003 - z = x3004 - z = x3005 - z = x3006 - z = x3007 - z = x3008 - z = x3009 - z = x3010 - z = x3011 - z = x3012 - z = x3013 - z = x3014 - z = x3015 - z = x3016 - z = x3017 - z = x3018 - z = x3019 - z = x3020 - z = x3021 - z = x3022 - z = x3023 - z = x3024 - z = x3025 - z = x3026 - z = x3027 - z = x3028 - z = x3029 - z = x3030 - z = x3031 - z = x3032 - z = x3033 - z = x3034 - z = x3035 - z = x3036 - z = x3037 - z = x3038 - z = x3039 - z = x3040 - z = x3041 - z = x3042 - z = x3043 - z = x3044 - z = x3045 - z = x3046 - z = x3047 - z = x3048 - z = x3049 - z = x3050 - z = x3051 - z = x3052 - z = x3053 - z = x3054 - z = x3055 - z = x3056 - z = x3057 - z = x3058 - z = x3059 - z = x3060 - z = x3061 - z = x3062 - z = x3063 - z = x3064 - z = x3065 - z = x3066 - z = x3067 - z = x3068 - z = x3069 - z = x3070 - z = x3071 - z = x3072 - z = x3073 - z = x3074 - z = x3075 - z = x3076 - z = x3077 - z = x3078 - z = x3079 - z = x3080 - z = x3081 - z = x3082 - z = x3083 - z = x3084 - z = x3085 - z = x3086 - z = x3087 - z = x3088 - z = x3089 - z = x3090 - z = x3091 - z = x3092 - z = x3093 - z = x3094 - z = x3095 - z = x3096 - z = x3097 - z = x3098 - z = x3099 - z = x3100 - z = x3101 - z = x3102 - z = x3103 - z = x3104 - z = x3105 - z = x3106 - z = x3107 - z = x3108 - z = x3109 - z = x3110 - z = x3111 - z = x3112 - z = x3113 - z = x3114 - z = x3115 - z = x3116 - z = x3117 - z = x3118 - z = x3119 - z = x3120 - z = x3121 - z = x3122 - z = x3123 - z = x3124 - z = x3125 - z = x3126 - z = x3127 - z = x3128 - z = x3129 - z = x3130 - z = x3131 - z = x3132 - z = x3133 - z = x3134 - z = x3135 - z = x3136 - z = x3137 - z = x3138 - z = x3139 - z = x3140 - z = x3141 - z = x3142 - z = x3143 - z = x3144 - z = x3145 - z = x3146 - z = x3147 - z = x3148 - z = x3149 - z = x3150 - z = x3151 - z = x3152 - z = x3153 - z = x3154 - z = x3155 - z = x3156 - z = x3157 - z = x3158 - z = x3159 - z = x3160 - z = x3161 - z = x3162 - z = x3163 - z = x3164 - z = x3165 - z = x3166 - z = x3167 - z = x3168 - z = x3169 - z = x3170 - z = x3171 - z = x3172 - z = x3173 - z = x3174 - z = x3175 - z = x3176 - z = x3177 - z = x3178 - z = x3179 - z = x3180 - z = x3181 - z = x3182 - z = x3183 - z = x3184 - z = x3185 - z = x3186 - z = x3187 - z = x3188 - z = x3189 - z = x3190 - z = x3191 - z = x3192 - z = x3193 - z = x3194 - z = x3195 - z = x3196 - z = x3197 - z = x3198 - z = x3199 - z = x3200 - z = x3201 - z = x3202 - z = x3203 - z = x3204 - z = x3205 - z = x3206 - z = x3207 - z = x3208 - z = x3209 - z = x3210 - z = x3211 - z = x3212 - z = x3213 - z = x3214 - z = x3215 - z = x3216 - z = x3217 - z = x3218 - z = x3219 - z = x3220 - z = x3221 - z = x3222 - z = x3223 - z = x3224 - z = x3225 - z = x3226 - z = x3227 - z = x3228 - z = x3229 - z = x3230 - z = x3231 - z = x3232 - z = x3233 - z = x3234 - z = x3235 - z = x3236 - z = x3237 - z = x3238 - z = x3239 - z = x3240 - z = x3241 - z = x3242 - z = x3243 - z = x3244 - z = x3245 - z = x3246 - z = x3247 - z = x3248 - z = x3249 - z = x3250 - z = x3251 - z = x3252 - z = x3253 - z = x3254 - z = x3255 - z = x3256 - z = x3257 - z = x3258 - z = x3259 - z = x3260 - z = x3261 - z = x3262 - z = x3263 - z = x3264 - z = x3265 - z = x3266 - z = x3267 - z = x3268 - z = x3269 - z = x3270 - z = x3271 - z = x3272 - z = x3273 - z = x3274 - z = x3275 - z = x3276 - z = x3277 - z = x3278 - z = x3279 - z = x3280 - z = x3281 - z = x3282 - z = x3283 - z = x3284 - z = x3285 - z = x3286 - z = x3287 - z = x3288 - z = x3289 - z = x3290 - z = x3291 - z = x3292 - z = x3293 - z = x3294 - z = x3295 - z = x3296 - z = x3297 - z = x3298 - z = x3299 - z = x3300 - z = x3301 - z = x3302 - z = x3303 - z = x3304 - z = x3305 - z = x3306 - z = x3307 - z = x3308 - z = x3309 - z = x3310 - z = x3311 - z = x3312 - z = x3313 - z = x3314 - z = x3315 - z = x3316 - z = x3317 - z = x3318 - z = x3319 - z = x3320 - z = x3321 - z = x3322 - z = x3323 - z = x3324 - z = x3325 - z = x3326 - z = x3327 - z = x3328 - z = x3329 - z = x3330 - z = x3331 - z = x3332 - z = x3333 - z = x3334 - z = x3335 - z = x3336 - z = x3337 - z = x3338 - z = x3339 - z = x3340 - z = x3341 - z = x3342 - z = x3343 - z = x3344 - z = x3345 - z = x3346 - z = x3347 - z = x3348 - z = x3349 - z = x3350 - z = x3351 - z = x3352 - z = x3353 - z = x3354 - z = x3355 - z = x3356 - z = x3357 - z = x3358 - z = x3359 - z = x3360 - z = x3361 - z = x3362 - z = x3363 - z = x3364 - z = x3365 - z = x3366 - z = x3367 - z = x3368 - z = x3369 - z = x3370 - z = x3371 - z = x3372 - z = x3373 - z = x3374 - z = x3375 - z = x3376 - z = x3377 - z = x3378 - z = x3379 - z = x3380 - z = x3381 - z = x3382 - z = x3383 - z = x3384 - z = x3385 - z = x3386 - z = x3387 - z = x3388 - z = x3389 - z = x3390 - z = x3391 - z = x3392 - z = x3393 - z = x3394 - z = x3395 - z = x3396 - z = x3397 - z = x3398 - z = x3399 - z = x3400 - z = x3401 - z = x3402 - z = x3403 - z = x3404 - z = x3405 - z = x3406 - z = x3407 - z = x3408 - z = x3409 - z = x3410 - z = x3411 - z = x3412 - z = x3413 - z = x3414 - z = x3415 - z = x3416 - z = x3417 - z = x3418 - z = x3419 - z = x3420 - z = x3421 - z = x3422 - z = x3423 - z = x3424 - z = x3425 - z = x3426 - z = x3427 - z = x3428 - z = x3429 - z = x3430 - z = x3431 - z = x3432 - z = x3433 - z = x3434 - z = x3435 - z = x3436 - z = x3437 - z = x3438 - z = x3439 - z = x3440 - z = x3441 - z = x3442 - z = x3443 - z = x3444 - z = x3445 - z = x3446 - z = x3447 - z = x3448 - z = x3449 - z = x3450 - z = x3451 - z = x3452 - z = x3453 - z = x3454 - z = x3455 - z = x3456 - z = x3457 - z = x3458 - z = x3459 - z = x3460 - z = x3461 - z = x3462 - z = x3463 - z = x3464 - z = x3465 - z = x3466 - z = x3467 - z = x3468 - z = x3469 - z = x3470 - z = x3471 - z = x3472 - z = x3473 - z = x3474 - z = x3475 - z = x3476 - z = x3477 - z = x3478 - z = x3479 - z = x3480 - z = x3481 - z = x3482 - z = x3483 - z = x3484 - z = x3485 - z = x3486 - z = x3487 - z = x3488 - z = x3489 - z = x3490 - z = x3491 - z = x3492 - z = x3493 - z = x3494 - z = x3495 - z = x3496 - z = x3497 - z = x3498 - z = x3499 - z = x3500 - z = x3501 - z = x3502 - z = x3503 - z = x3504 - z = x3505 - z = x3506 - z = x3507 - z = x3508 - z = x3509 - z = x3510 - z = x3511 - z = x3512 - z = x3513 - z = x3514 - z = x3515 - z = x3516 - z = x3517 - z = x3518 - z = x3519 - z = x3520 - z = x3521 - z = x3522 - z = x3523 - z = x3524 - z = x3525 - z = x3526 - z = x3527 - z = x3528 - z = x3529 - z = x3530 - z = x3531 - z = x3532 - z = x3533 - z = x3534 - z = x3535 - z = x3536 - z = x3537 - z = x3538 - z = x3539 - z = x3540 - z = x3541 - z = x3542 - z = x3543 - z = x3544 - z = x3545 - z = x3546 - z = x3547 - z = x3548 - z = x3549 - z = x3550 - z = x3551 - z = x3552 - z = x3553 - z = x3554 - z = x3555 - z = x3556 - z = x3557 - z = x3558 - z = x3559 - z = x3560 - z = x3561 - z = x3562 - z = x3563 - z = x3564 - z = x3565 - z = x3566 - z = x3567 - z = x3568 - z = x3569 - z = x3570 - z = x3571 - z = x3572 - z = x3573 - z = x3574 - z = x3575 - z = x3576 - z = x3577 - z = x3578 - z = x3579 - z = x3580 - z = x3581 - z = x3582 - z = x3583 - z = x3584 - z = x3585 - z = x3586 - z = x3587 - z = x3588 - z = x3589 - z = x3590 - z = x3591 - z = x3592 - z = x3593 - z = x3594 - z = x3595 - z = x3596 - z = x3597 - z = x3598 - z = x3599 - z = x3600 - z = x3601 - z = x3602 - z = x3603 - z = x3604 - z = x3605 - z = x3606 - z = x3607 - z = x3608 - z = x3609 - z = x3610 - z = x3611 - z = x3612 - z = x3613 - z = x3614 - z = x3615 - z = x3616 - z = x3617 - z = x3618 - z = x3619 - z = x3620 - z = x3621 - z = x3622 - z = x3623 - z = x3624 - z = x3625 - z = x3626 - z = x3627 - z = x3628 - z = x3629 - z = x3630 - z = x3631 - z = x3632 - z = x3633 - z = x3634 - z = x3635 - z = x3636 - z = x3637 - z = x3638 - z = x3639 - z = x3640 - z = x3641 - z = x3642 - z = x3643 - z = x3644 - z = x3645 - z = x3646 - z = x3647 - z = x3648 - z = x3649 - z = x3650 - z = x3651 - z = x3652 - z = x3653 - z = x3654 - z = x3655 - z = x3656 - z = x3657 - z = x3658 - z = x3659 - z = x3660 - z = x3661 - z = x3662 - z = x3663 - z = x3664 - z = x3665 - z = x3666 - z = x3667 - z = x3668 - z = x3669 - z = x3670 - z = x3671 - z = x3672 - z = x3673 - z = x3674 - z = x3675 - z = x3676 - z = x3677 - z = x3678 - z = x3679 - z = x3680 - z = x3681 - z = x3682 - z = x3683 - z = x3684 - z = x3685 - z = x3686 - z = x3687 - z = x3688 - z = x3689 - z = x3690 - z = x3691 - z = x3692 - z = x3693 - z = x3694 - z = x3695 - z = x3696 - z = x3697 - z = x3698 - z = x3699 - z = x3700 - z = x3701 - z = x3702 - z = x3703 - z = x3704 - z = x3705 - z = x3706 - z = x3707 - z = x3708 - z = x3709 - z = x3710 - z = x3711 - z = x3712 - z = x3713 - z = x3714 - z = x3715 - z = x3716 - z = x3717 - z = x3718 - z = x3719 - z = x3720 - z = x3721 - z = x3722 - z = x3723 - z = x3724 - z = x3725 - z = x3726 - z = x3727 - z = x3728 - z = x3729 - z = x3730 - z = x3731 - z = x3732 - z = x3733 - z = x3734 - z = x3735 - z = x3736 - z = x3737 - z = x3738 - z = x3739 - z = x3740 - z = x3741 - z = x3742 - z = x3743 - z = x3744 - z = x3745 - z = x3746 - z = x3747 - z = x3748 - z = x3749 - z = x3750 - z = x3751 - z = x3752 - z = x3753 - z = x3754 - z = x3755 - z = x3756 - z = x3757 - z = x3758 - z = x3759 - z = x3760 - z = x3761 - z = x3762 - z = x3763 - z = x3764 - z = x3765 - z = x3766 - z = x3767 - z = x3768 - z = x3769 - z = x3770 - z = x3771 - z = x3772 - z = x3773 - z = x3774 - z = x3775 - z = x3776 - z = x3777 - z = x3778 - z = x3779 - z = x3780 - z = x3781 - z = x3782 - z = x3783 - z = x3784 - z = x3785 - z = x3786 - z = x3787 - z = x3788 - z = x3789 - z = x3790 - z = x3791 - z = x3792 - z = x3793 - z = x3794 - z = x3795 - z = x3796 - z = x3797 - z = x3798 - z = x3799 - z = x3800 - z = x3801 - z = x3802 - z = x3803 - z = x3804 - z = x3805 - z = x3806 - z = x3807 - z = x3808 - z = x3809 - z = x3810 - z = x3811 - z = x3812 - z = x3813 - z = x3814 - z = x3815 - z = x3816 - z = x3817 - z = x3818 - z = x3819 - z = x3820 - z = x3821 - z = x3822 - z = x3823 - z = x3824 - z = x3825 - z = x3826 - z = x3827 - z = x3828 - z = x3829 - z = x3830 - z = x3831 - z = x3832 - z = x3833 - z = x3834 - z = x3835 - z = x3836 - z = x3837 - z = x3838 - z = x3839 - z = x3840 - z = x3841 - z = x3842 - z = x3843 - z = x3844 - z = x3845 - z = x3846 - z = x3847 - z = x3848 - z = x3849 - z = x3850 - z = x3851 - z = x3852 - z = x3853 - z = x3854 - z = x3855 - z = x3856 - z = x3857 - z = x3858 - z = x3859 - z = x3860 - z = x3861 - z = x3862 - z = x3863 - z = x3864 - z = x3865 - z = x3866 - z = x3867 - z = x3868 - z = x3869 - z = x3870 - z = x3871 - z = x3872 - z = x3873 - z = x3874 - z = x3875 - z = x3876 - z = x3877 - z = x3878 - z = x3879 - z = x3880 - z = x3881 - z = x3882 - z = x3883 - z = x3884 - z = x3885 - z = x3886 - z = x3887 - z = x3888 - z = x3889 - z = x3890 - z = x3891 - z = x3892 - z = x3893 - z = x3894 - z = x3895 - z = x3896 - z = x3897 - z = x3898 - z = x3899 - z = x3900 - z = x3901 - z = x3902 - z = x3903 - z = x3904 - z = x3905 - z = x3906 - z = x3907 - z = x3908 - z = x3909 - z = x3910 - z = x3911 - z = x3912 - z = x3913 - z = x3914 - z = x3915 - z = x3916 - z = x3917 - z = x3918 - z = x3919 - z = x3920 - z = x3921 - z = x3922 - z = x3923 - z = x3924 - z = x3925 - z = x3926 - z = x3927 - z = x3928 - z = x3929 - z = x3930 - z = x3931 - z = x3932 - z = x3933 - z = x3934 - z = x3935 - z = x3936 - z = x3937 - z = x3938 - z = x3939 - z = x3940 - z = x3941 - z = x3942 - z = x3943 - z = x3944 - z = x3945 - z = x3946 - z = x3947 - z = x3948 - z = x3949 - z = x3950 - z = x3951 - z = x3952 - z = x3953 - z = x3954 - z = x3955 - z = x3956 - z = x3957 - z = x3958 - z = x3959 - z = x3960 - z = x3961 - z = x3962 - z = x3963 - z = x3964 - z = x3965 - z = x3966 - z = x3967 - z = x3968 - z = x3969 - z = x3970 - z = x3971 - z = x3972 - z = x3973 - z = x3974 - z = x3975 - z = x3976 - z = x3977 - z = x3978 - z = x3979 - z = x3980 - z = x3981 - z = x3982 - z = x3983 - z = x3984 - z = x3985 - z = x3986 - z = x3987 - z = x3988 - z = x3989 - z = x3990 - z = x3991 - z = x3992 - z = x3993 - z = x3994 - z = x3995 - z = x3996 - z = x3997 - z = x3998 - z = x3999 - z = x4000 - z = x4001 - z = x4002 - z = x4003 - z = x4004 - z = x4005 - z = x4006 - z = x4007 - z = x4008 - z = x4009 - z = x4010 - z = x4011 - z = x4012 - z = x4013 - z = x4014 - z = x4015 - z = x4016 - z = x4017 - z = x4018 - z = x4019 - z = x4020 - z = x4021 - z = x4022 - z = x4023 - z = x4024 - z = x4025 - z = x4026 - z = x4027 - z = x4028 - z = x4029 - z = x4030 - z = x4031 - z = x4032 - z = x4033 - z = x4034 - z = x4035 - z = x4036 - z = x4037 - z = x4038 - z = x4039 - z = x4040 - z = x4041 - z = x4042 - z = x4043 - z = x4044 - z = x4045 - z = x4046 - z = x4047 - z = x4048 - z = x4049 - z = x4050 - z = x4051 - z = x4052 - z = x4053 - z = x4054 - z = x4055 - z = x4056 - z = x4057 - z = x4058 - z = x4059 - z = x4060 - z = x4061 - z = x4062 - z = x4063 - z = x4064 - z = x4065 - z = x4066 - z = x4067 - z = x4068 - z = x4069 - z = x4070 - z = x4071 - z = x4072 - z = x4073 - z = x4074 - z = x4075 - z = x4076 - z = x4077 - z = x4078 - z = x4079 - z = x4080 - z = x4081 - z = x4082 - z = x4083 - z = x4084 - z = x4085 - z = x4086 - z = x4087 - z = x4088 - z = x4089 - z = x4090 - z = x4091 - z = x4092 - z = x4093 - z = x4094 - z = x4095 - z = x4096 - z = x4097 - z = x4098 - z = x4099 - z = x4100 - z = x4101 - z = x4102 - z = x4103 - z = x4104 - z = x4105 - z = x4106 - z = x4107 - z = x4108 - z = x4109 - z = x4110 - z = x4111 - z = x4112 - z = x4113 - z = x4114 - z = x4115 - z = x4116 - z = x4117 - z = x4118 - z = x4119 - z = x4120 - z = x4121 - z = x4122 - z = x4123 - z = x4124 - z = x4125 - z = x4126 - z = x4127 - z = x4128 - z = x4129 - z = x4130 - z = x4131 - z = x4132 - z = x4133 - z = x4134 - z = x4135 - z = x4136 - z = x4137 - z = x4138 - z = x4139 - z = x4140 - z = x4141 - z = x4142 - z = x4143 - z = x4144 - z = x4145 - z = x4146 - z = x4147 - z = x4148 - z = x4149 - z = x4150 - z = x4151 - z = x4152 - z = x4153 - z = x4154 - z = x4155 - z = x4156 - z = x4157 - z = x4158 - z = x4159 - z = x4160 - z = x4161 - z = x4162 - z = x4163 - z = x4164 - z = x4165 - z = x4166 - z = x4167 - z = x4168 - z = x4169 - z = x4170 - z = x4171 - z = x4172 - z = x4173 - z = x4174 - z = x4175 - z = x4176 - z = x4177 - z = x4178 - z = x4179 - z = x4180 - z = x4181 - z = x4182 - z = x4183 - z = x4184 - z = x4185 - z = x4186 - z = x4187 - z = x4188 - z = x4189 - z = x4190 - z = x4191 - z = x4192 - z = x4193 - z = x4194 - z = x4195 - z = x4196 - z = x4197 - z = x4198 - z = x4199 - z = x4200 - z = x4201 - z = x4202 - z = x4203 - z = x4204 - z = x4205 - z = x4206 - z = x4207 - z = x4208 - z = x4209 - z = x4210 - z = x4211 - z = x4212 - z = x4213 - z = x4214 - z = x4215 - z = x4216 - z = x4217 - z = x4218 - z = x4219 - z = x4220 - z = x4221 - z = x4222 - z = x4223 - z = x4224 - z = x4225 - z = x4226 - z = x4227 - z = x4228 - z = x4229 - z = x4230 - z = x4231 - z = x4232 - z = x4233 - z = x4234 - z = x4235 - z = x4236 - z = x4237 - z = x4238 - z = x4239 - z = x4240 - z = x4241 - z = x4242 - z = x4243 - z = x4244 - z = x4245 - z = x4246 - z = x4247 - z = x4248 - z = x4249 - z = x4250 - z = x4251 - z = x4252 - z = x4253 - z = x4254 - z = x4255 - z = x4256 - z = x4257 - z = x4258 - z = x4259 - z = x4260 - z = x4261 - z = x4262 - z = x4263 - z = x4264 - z = x4265 - z = x4266 - z = x4267 - z = x4268 - z = x4269 - z = x4270 - z = x4271 - z = x4272 - z = x4273 - z = x4274 - z = x4275 - z = x4276 - z = x4277 - z = x4278 - z = x4279 - z = x4280 - z = x4281 - z = x4282 - z = x4283 - z = x4284 - z = x4285 - z = x4286 - z = x4287 - z = x4288 - z = x4289 - z = x4290 - z = x4291 - z = x4292 - z = x4293 - z = x4294 - z = x4295 - z = x4296 - z = x4297 - z = x4298 - z = x4299 - z = x4300 - z = x4301 - z = x4302 - z = x4303 - z = x4304 - z = x4305 - z = x4306 - z = x4307 - z = x4308 - z = x4309 - z = x4310 - z = x4311 - z = x4312 - z = x4313 - z = x4314 - z = x4315 - z = x4316 - z = x4317 - z = x4318 - z = x4319 - z = x4320 - z = x4321 - z = x4322 - z = x4323 - z = x4324 - z = x4325 - z = x4326 - z = x4327 - z = x4328 - z = x4329 - z = x4330 - z = x4331 - z = x4332 - z = x4333 - z = x4334 - z = x4335 - z = x4336 - z = x4337 - z = x4338 - z = x4339 - z = x4340 - z = x4341 - z = x4342 - z = x4343 - z = x4344 - z = x4345 - z = x4346 - z = x4347 - z = x4348 - z = x4349 - z = x4350 - z = x4351 - z = x4352 - z = x4353 - z = x4354 - z = x4355 - z = x4356 - z = x4357 - z = x4358 - z = x4359 - z = x4360 - z = x4361 - z = x4362 - z = x4363 - z = x4364 - z = x4365 - z = x4366 - z = x4367 - z = x4368 - z = x4369 - z = x4370 - z = x4371 - z = x4372 - z = x4373 - z = x4374 - z = x4375 - z = x4376 - z = x4377 - z = x4378 - z = x4379 - z = x4380 - z = x4381 - z = x4382 - z = x4383 - z = x4384 - z = x4385 - z = x4386 - z = x4387 - z = x4388 - z = x4389 - z = x4390 - z = x4391 - z = x4392 - z = x4393 - z = x4394 - z = x4395 - z = x4396 - z = x4397 - z = x4398 - z = x4399 - z = x4400 - z = x4401 - z = x4402 - z = x4403 - z = x4404 - z = x4405 - z = x4406 - z = x4407 - z = x4408 - z = x4409 - z = x4410 - z = x4411 - z = x4412 - z = x4413 - z = x4414 - z = x4415 - z = x4416 - z = x4417 - z = x4418 - z = x4419 - z = x4420 - z = x4421 - z = x4422 - z = x4423 - z = x4424 - z = x4425 - z = x4426 - z = x4427 - z = x4428 - z = x4429 - z = x4430 - z = x4431 - z = x4432 - z = x4433 - z = x4434 - z = x4435 - z = x4436 - z = x4437 - z = x4438 - z = x4439 - z = x4440 - z = x4441 - z = x4442 - z = x4443 - z = x4444 - z = x4445 - z = x4446 - z = x4447 - z = x4448 - z = x4449 - z = x4450 - z = x4451 - z = x4452 - z = x4453 - z = x4454 - z = x4455 - z = x4456 - z = x4457 - z = x4458 - z = x4459 - z = x4460 - z = x4461 - z = x4462 - z = x4463 - z = x4464 - z = x4465 - z = x4466 - z = x4467 - z = x4468 - z = x4469 - z = x4470 - z = x4471 - z = x4472 - z = x4473 - z = x4474 - z = x4475 - z = x4476 - z = x4477 - z = x4478 - z = x4479 - z = x4480 - z = x4481 - z = x4482 - z = x4483 - z = x4484 - z = x4485 - z = x4486 - z = x4487 - z = x4488 - z = x4489 - z = x4490 - z = x4491 - z = x4492 - z = x4493 - z = x4494 - z = x4495 - z = x4496 - z = x4497 - z = x4498 - z = x4499 - z = x4500 - z = x4501 - z = x4502 - z = x4503 - z = x4504 - z = x4505 - z = x4506 - z = x4507 - z = x4508 - z = x4509 - z = x4510 - z = x4511 - z = x4512 - z = x4513 - z = x4514 - z = x4515 - z = x4516 - z = x4517 - z = x4518 - z = x4519 - z = x4520 - z = x4521 - z = x4522 - z = x4523 - z = x4524 - z = x4525 - z = x4526 - z = x4527 - z = x4528 - z = x4529 - z = x4530 - z = x4531 - z = x4532 - z = x4533 - z = x4534 - z = x4535 - z = x4536 - z = x4537 - z = x4538 - z = x4539 - z = x4540 - z = x4541 - z = x4542 - z = x4543 - z = x4544 - z = x4545 - z = x4546 - z = x4547 - z = x4548 - z = x4549 - z = x4550 - z = x4551 - z = x4552 - z = x4553 - z = x4554 - z = x4555 - z = x4556 - z = x4557 - z = x4558 - z = x4559 - z = x4560 - z = x4561 - z = x4562 - z = x4563 - z = x4564 - z = x4565 - z = x4566 - z = x4567 - z = x4568 - z = x4569 - z = x4570 - z = x4571 - z = x4572 - z = x4573 - z = x4574 - z = x4575 - z = x4576 - z = x4577 - z = x4578 - z = x4579 - z = x4580 - z = x4581 - z = x4582 - z = x4583 - z = x4584 - z = x4585 - z = x4586 - z = x4587 - z = x4588 - z = x4589 - z = x4590 - z = x4591 - z = x4592 - z = x4593 - z = x4594 - z = x4595 - z = x4596 - z = x4597 - z = x4598 - z = x4599 - z = x4600 - z = x4601 - z = x4602 - z = x4603 - z = x4604 - z = x4605 - z = x4606 - z = x4607 - z = x4608 - z = x4609 - z = x4610 - z = x4611 - z = x4612 - z = x4613 - z = x4614 - z = x4615 - z = x4616 - z = x4617 - z = x4618 - z = x4619 - z = x4620 - z = x4621 - z = x4622 - z = x4623 - z = x4624 - z = x4625 - z = x4626 - z = x4627 - z = x4628 - z = x4629 - z = x4630 - z = x4631 - z = x4632 - z = x4633 - z = x4634 - z = x4635 - z = x4636 - z = x4637 - z = x4638 - z = x4639 - z = x4640 - z = x4641 - z = x4642 - z = x4643 - z = x4644 - z = x4645 - z = x4646 - z = x4647 - z = x4648 - z = x4649 - z = x4650 - z = x4651 - z = x4652 - z = x4653 - z = x4654 - z = x4655 - z = x4656 - z = x4657 - z = x4658 - z = x4659 - z = x4660 - z = x4661 - z = x4662 - z = x4663 - z = x4664 - z = x4665 - z = x4666 - z = x4667 - z = x4668 - z = x4669 - z = x4670 - z = x4671 - z = x4672 - z = x4673 - z = x4674 - z = x4675 - z = x4676 - z = x4677 - z = x4678 - z = x4679 - z = x4680 - z = x4681 - z = x4682 - z = x4683 - z = x4684 - z = x4685 - z = x4686 - z = x4687 - z = x4688 - z = x4689 - z = x4690 - z = x4691 - z = x4692 - z = x4693 - z = x4694 - z = x4695 - z = x4696 - z = x4697 - z = x4698 - z = x4699 - z = x4700 - z = x4701 - z = x4702 - z = x4703 - z = x4704 - z = x4705 - z = x4706 - z = x4707 - z = x4708 - z = x4709 - z = x4710 - z = x4711 - z = x4712 - z = x4713 - z = x4714 - z = x4715 - z = x4716 - z = x4717 - z = x4718 - z = x4719 - z = x4720 - z = x4721 - z = x4722 - z = x4723 - z = x4724 - z = x4725 - z = x4726 - z = x4727 - z = x4728 - z = x4729 - z = x4730 - z = x4731 - z = x4732 - z = x4733 - z = x4734 - z = x4735 - z = x4736 - z = x4737 - z = x4738 - z = x4739 - z = x4740 - z = x4741 - z = x4742 - z = x4743 - z = x4744 - z = x4745 - z = x4746 - z = x4747 - z = x4748 - z = x4749 - z = x4750 - z = x4751 - z = x4752 - z = x4753 - z = x4754 - z = x4755 - z = x4756 - z = x4757 - z = x4758 - z = x4759 - z = x4760 - z = x4761 - z = x4762 - z = x4763 - z = x4764 - z = x4765 - z = x4766 - z = x4767 - z = x4768 - z = x4769 - z = x4770 - z = x4771 - z = x4772 - z = x4773 - z = x4774 - z = x4775 - z = x4776 - z = x4777 - z = x4778 - z = x4779 - z = x4780 - z = x4781 - z = x4782 - z = x4783 - z = x4784 - z = x4785 - z = x4786 - z = x4787 - z = x4788 - z = x4789 - z = x4790 - z = x4791 - z = x4792 - z = x4793 - z = x4794 - z = x4795 - z = x4796 - z = x4797 - z = x4798 - z = x4799 - z = x4800 - z = x4801 - z = x4802 - z = x4803 - z = x4804 - z = x4805 - z = x4806 - z = x4807 - z = x4808 - z = x4809 - z = x4810 - z = x4811 - z = x4812 - z = x4813 - z = x4814 - z = x4815 - z = x4816 - z = x4817 - z = x4818 - z = x4819 - z = x4820 - z = x4821 - z = x4822 - z = x4823 - z = x4824 - z = x4825 - z = x4826 - z = x4827 - z = x4828 - z = x4829 - z = x4830 - z = x4831 - z = x4832 - z = x4833 - z = x4834 - z = x4835 - z = x4836 - z = x4837 - z = x4838 - z = x4839 - z = x4840 - z = x4841 - z = x4842 - z = x4843 - z = x4844 - z = x4845 - z = x4846 - z = x4847 - z = x4848 - z = x4849 - z = x4850 - z = x4851 - z = x4852 - z = x4853 - z = x4854 - z = x4855 - z = x4856 - z = x4857 - z = x4858 - z = x4859 - z = x4860 - z = x4861 - z = x4862 - z = x4863 - z = x4864 - z = x4865 - z = x4866 - z = x4867 - z = x4868 - z = x4869 - z = x4870 - z = x4871 - z = x4872 - z = x4873 - z = x4874 - z = x4875 - z = x4876 - z = x4877 - z = x4878 - z = x4879 - z = x4880 - z = x4881 - z = x4882 - z = x4883 - z = x4884 - z = x4885 - z = x4886 - z = x4887 - z = x4888 - z = x4889 - z = x4890 - z = x4891 - z = x4892 - z = x4893 - z = x4894 - z = x4895 - z = x4896 - z = x4897 - z = x4898 - z = x4899 - z = x4900 - z = x4901 - z = x4902 - z = x4903 - z = x4904 - z = x4905 - z = x4906 - z = x4907 - z = x4908 - z = x4909 - z = x4910 - z = x4911 - z = x4912 - z = x4913 - z = x4914 - z = x4915 - z = x4916 - z = x4917 - z = x4918 - z = x4919 - z = x4920 - z = x4921 - z = x4922 - z = x4923 - z = x4924 - z = x4925 - z = x4926 - z = x4927 - z = x4928 - z = x4929 - z = x4930 - z = x4931 - z = x4932 - z = x4933 - z = x4934 - z = x4935 - z = x4936 - z = x4937 - z = x4938 - z = x4939 - z = x4940 - z = x4941 - z = x4942 - z = x4943 - z = x4944 - z = x4945 - z = x4946 - z = x4947 - z = x4948 - z = x4949 - z = x4950 - z = x4951 - z = x4952 - z = x4953 - z = x4954 - z = x4955 - z = x4956 - z = x4957 - z = x4958 - z = x4959 - z = x4960 - z = x4961 - z = x4962 - z = x4963 - z = x4964 - z = x4965 - z = x4966 - z = x4967 - z = x4968 - z = x4969 - z = x4970 - z = x4971 - z = x4972 - z = x4973 - z = x4974 - z = x4975 - z = x4976 - z = x4977 - z = x4978 - z = x4979 - z = x4980 - z = x4981 - z = x4982 - z = x4983 - z = x4984 - z = x4985 - z = x4986 - z = x4987 - z = x4988 - z = x4989 - z = x4990 - z = x4991 - z = x4992 - z = x4993 - z = x4994 - z = x4995 - z = x4996 - z = x4997 - z = x4998 - z = x4999 - z = x5000 - z = x5001 - z = x5002 - z = x5003 - z = x5004 - z = x5005 - z = x5006 - z = x5007 - z = x5008 - z = x5009 - z = x5010 - z = x5011 - z = x5012 - z = x5013 - z = x5014 - z = x5015 - z = x5016 - z = x5017 - z = x5018 - z = x5019 - z = x5020 - z = x5021 - z = x5022 - z = x5023 - z = x5024 - z = x5025 - z = x5026 - z = x5027 - z = x5028 - z = x5029 - z = x5030 - z = x5031 - z = x5032 - z = x5033 - z = x5034 - z = x5035 - z = x5036 - z = x5037 - z = x5038 - z = x5039 - z = x5040 - z = x5041 - z = x5042 - z = x5043 - z = x5044 - z = x5045 - z = x5046 - z = x5047 - z = x5048 - z = x5049 - z = x5050 - z = x5051 - z = x5052 - z = x5053 - z = x5054 - z = x5055 - z = x5056 - z = x5057 - z = x5058 - z = x5059 - z = x5060 - z = x5061 - z = x5062 - z = x5063 - z = x5064 - z = x5065 - z = x5066 - z = x5067 - z = x5068 - z = x5069 - z = x5070 - z = x5071 - z = x5072 - z = x5073 - z = x5074 - z = x5075 - z = x5076 - z = x5077 - z = x5078 - z = x5079 - z = x5080 - z = x5081 - z = x5082 - z = x5083 - z = x5084 - z = x5085 - z = x5086 - z = x5087 - z = x5088 - z = x5089 - z = x5090 - z = x5091 - z = x5092 - z = x5093 - z = x5094 - z = x5095 - z = x5096 - z = x5097 - z = x5098 - z = x5099 - z = x5100 - z = x5101 - z = x5102 - z = x5103 - z = x5104 - z = x5105 - z = x5106 - z = x5107 - z = x5108 - z = x5109 - z = x5110 - z = x5111 - z = x5112 - z = x5113 - z = x5114 - z = x5115 - z = x5116 - z = x5117 - z = x5118 - z = x5119 - z = x5120 - z = x5121 - z = x5122 - z = x5123 - z = x5124 - z = x5125 - z = x5126 - z = x5127 - z = x5128 - z = x5129 - z = x5130 - z = x5131 - z = x5132 - z = x5133 - z = x5134 - z = x5135 - z = x5136 - z = x5137 - z = x5138 - z = x5139 - z = x5140 - z = x5141 - z = x5142 - z = x5143 - z = x5144 - z = x5145 - z = x5146 - z = x5147 - z = x5148 - z = x5149 - z = x5150 - z = x5151 - z = x5152 - z = x5153 - z = x5154 - z = x5155 - z = x5156 - z = x5157 - z = x5158 - z = x5159 - z = x5160 - z = x5161 - z = x5162 - z = x5163 - z = x5164 - z = x5165 - z = x5166 - z = x5167 - z = x5168 - z = x5169 - z = x5170 - z = x5171 - z = x5172 - z = x5173 - z = x5174 - z = x5175 - z = x5176 - z = x5177 - z = x5178 - z = x5179 - z = x5180 - z = x5181 - z = x5182 - z = x5183 - z = x5184 - z = x5185 - z = x5186 - z = x5187 - z = x5188 - z = x5189 - z = x5190 - z = x5191 - z = x5192 - z = x5193 - z = x5194 - z = x5195 - z = x5196 - z = x5197 - z = x5198 - z = x5199 - z = x5200 - z = x5201 - z = x5202 - z = x5203 - z = x5204 - z = x5205 - z = x5206 - z = x5207 - z = x5208 - z = x5209 - z = x5210 - z = x5211 - z = x5212 - z = x5213 - z = x5214 - z = x5215 - z = x5216 - z = x5217 - z = x5218 - z = x5219 - z = x5220 - z = x5221 - z = x5222 - z = x5223 - z = x5224 - z = x5225 - z = x5226 - z = x5227 - z = x5228 - z = x5229 - z = x5230 - z = x5231 - z = x5232 - z = x5233 - z = x5234 - z = x5235 - z = x5236 - z = x5237 - z = x5238 - z = x5239 - z = x5240 - z = x5241 - z = x5242 - z = x5243 - z = x5244 - z = x5245 - z = x5246 - z = x5247 - z = x5248 - z = x5249 - z = x5250 - z = x5251 - z = x5252 - z = x5253 - z = x5254 - z = x5255 - z = x5256 - z = x5257 - z = x5258 - z = x5259 - z = x5260 - z = x5261 - z = x5262 - z = x5263 - z = x5264 - z = x5265 - z = x5266 - z = x5267 - z = x5268 - z = x5269 - z = x5270 - z = x5271 - z = x5272 - z = x5273 - z = x5274 - z = x5275 - z = x5276 - z = x5277 - z = x5278 - z = x5279 - z = x5280 - z = x5281 - z = x5282 - z = x5283 - z = x5284 - z = x5285 - z = x5286 - z = x5287 - z = x5288 - z = x5289 - z = x5290 - z = x5291 - z = x5292 - z = x5293 - z = x5294 - z = x5295 - z = x5296 - z = x5297 - z = x5298 - z = x5299 - z = x5300 - z = x5301 - z = x5302 - z = x5303 - z = x5304 - z = x5305 - z = x5306 - z = x5307 - z = x5308 - z = x5309 - z = x5310 - z = x5311 - z = x5312 - z = x5313 - z = x5314 - z = x5315 - z = x5316 - z = x5317 - z = x5318 - z = x5319 - z = x5320 - z = x5321 - z = x5322 - z = x5323 - z = x5324 - z = x5325 - z = x5326 - z = x5327 - z = x5328 - z = x5329 - z = x5330 - z = x5331 - z = x5332 - z = x5333 - z = x5334 - z = x5335 - z = x5336 - z = x5337 - z = x5338 - z = x5339 - z = x5340 - z = x5341 - z = x5342 - z = x5343 - z = x5344 - z = x5345 - z = x5346 - z = x5347 - z = x5348 - z = x5349 - z = x5350 - z = x5351 - z = x5352 - z = x5353 - z = x5354 - z = x5355 - z = x5356 - z = x5357 - z = x5358 - z = x5359 - z = x5360 - z = x5361 - z = x5362 - z = x5363 - z = x5364 - z = x5365 - z = x5366 - z = x5367 - z = x5368 - z = x5369 - z = x5370 - z = x5371 - z = x5372 - z = x5373 - z = x5374 - z = x5375 - z = x5376 - z = x5377 - z = x5378 - z = x5379 - z = x5380 - z = x5381 - z = x5382 - z = x5383 - z = x5384 - z = x5385 - z = x5386 - z = x5387 - z = x5388 - z = x5389 - z = x5390 - z = x5391 - z = x5392 - z = x5393 - z = x5394 - z = x5395 - z = x5396 - z = x5397 - z = x5398 - z = x5399 - z = x5400 - z = x5401 - z = x5402 - z = x5403 - z = x5404 - z = x5405 - z = x5406 - z = x5407 - z = x5408 - z = x5409 - z = x5410 - z = x5411 - z = x5412 - z = x5413 - z = x5414 - z = x5415 - z = x5416 - z = x5417 - z = x5418 - z = x5419 - z = x5420 - z = x5421 - z = x5422 - z = x5423 - z = x5424 - z = x5425 - z = x5426 - z = x5427 - z = x5428 - z = x5429 - z = x5430 - z = x5431 - z = x5432 - z = x5433 - z = x5434 - z = x5435 - z = x5436 - z = x5437 - z = x5438 - z = x5439 - z = x5440 - z = x5441 - z = x5442 - z = x5443 - z = x5444 - z = x5445 - z = x5446 - z = x5447 - z = x5448 - z = x5449 - z = x5450 - z = x5451 - z = x5452 - z = x5453 - z = x5454 - z = x5455 - z = x5456 - z = x5457 - z = x5458 - z = x5459 - z = x5460 - z = x5461 - z = x5462 - z = x5463 - z = x5464 - z = x5465 - z = x5466 - z = x5467 - z = x5468 - z = x5469 - z = x5470 - z = x5471 - z = x5472 - z = x5473 - z = x5474 - z = x5475 - z = x5476 - z = x5477 - z = x5478 - z = x5479 - z = x5480 - z = x5481 - z = x5482 - z = x5483 - z = x5484 - z = x5485 - z = x5486 - z = x5487 - z = x5488 - z = x5489 - z = x5490 - z = x5491 - z = x5492 - z = x5493 - z = x5494 - z = x5495 - z = x5496 - z = x5497 - z = x5498 - z = x5499 - z = x5500 - z = x5501 - z = x5502 - z = x5503 - z = x5504 - z = x5505 - z = x5506 - z = x5507 - z = x5508 - z = x5509 - z = x5510 - z = x5511 - z = x5512 - z = x5513 - z = x5514 - z = x5515 - z = x5516 - z = x5517 - z = x5518 - z = x5519 - z = x5520 - z = x5521 - z = x5522 - z = x5523 - z = x5524 - z = x5525 - z = x5526 - z = x5527 - z = x5528 - z = x5529 - z = x5530 - z = x5531 - z = x5532 - z = x5533 - z = x5534 - z = x5535 - z = x5536 - z = x5537 - z = x5538 - z = x5539 - z = x5540 - z = x5541 - z = x5542 - z = x5543 - z = x5544 - z = x5545 - z = x5546 - z = x5547 - z = x5548 - z = x5549 - z = x5550 - z = x5551 - z = x5552 - z = x5553 - z = x5554 - z = x5555 - z = x5556 - z = x5557 - z = x5558 - z = x5559 - z = x5560 - z = x5561 - z = x5562 - z = x5563 - z = x5564 - z = x5565 - z = x5566 - z = x5567 - z = x5568 - z = x5569 - z = x5570 - z = x5571 - z = x5572 - z = x5573 - z = x5574 - z = x5575 - z = x5576 - z = x5577 - z = x5578 - z = x5579 - z = x5580 - z = x5581 - z = x5582 - z = x5583 - z = x5584 - z = x5585 - z = x5586 - z = x5587 - z = x5588 - z = x5589 - z = x5590 - z = x5591 - z = x5592 - z = x5593 - z = x5594 - z = x5595 - z = x5596 - z = x5597 - z = x5598 - z = x5599 - z = x5600 - z = x5601 - z = x5602 - z = x5603 - z = x5604 - z = x5605 - z = x5606 - z = x5607 - z = x5608 - z = x5609 - z = x5610 - z = x5611 - z = x5612 - z = x5613 - z = x5614 - z = x5615 - z = x5616 - z = x5617 - z = x5618 - z = x5619 - z = x5620 - z = x5621 - z = x5622 - z = x5623 - z = x5624 - z = x5625 - z = x5626 - z = x5627 - z = x5628 - z = x5629 - z = x5630 - z = x5631 - z = x5632 - z = x5633 - z = x5634 - z = x5635 - z = x5636 - z = x5637 - z = x5638 - z = x5639 - z = x5640 - z = x5641 - z = x5642 - z = x5643 - z = x5644 - z = x5645 - z = x5646 - z = x5647 - z = x5648 - z = x5649 - z = x5650 - z = x5651 - z = x5652 - z = x5653 - z = x5654 - z = x5655 - z = x5656 - z = x5657 - z = x5658 - z = x5659 - z = x5660 - z = x5661 - z = x5662 - z = x5663 - z = x5664 - z = x5665 - z = x5666 - z = x5667 - z = x5668 - z = x5669 - z = x5670 - z = x5671 - z = x5672 - z = x5673 - z = x5674 - z = x5675 - z = x5676 - z = x5677 - z = x5678 - z = x5679 - z = x5680 - z = x5681 - z = x5682 - z = x5683 - z = x5684 - z = x5685 - z = x5686 - z = x5687 - z = x5688 - z = x5689 - z = x5690 - z = x5691 - z = x5692 - z = x5693 - z = x5694 - z = x5695 - z = x5696 - z = x5697 - z = x5698 - z = x5699 - z = x5700 - z = x5701 - z = x5702 - z = x5703 - z = x5704 - z = x5705 - z = x5706 - z = x5707 - z = x5708 - z = x5709 - z = x5710 - z = x5711 - z = x5712 - z = x5713 - z = x5714 - z = x5715 - z = x5716 - z = x5717 - z = x5718 - z = x5719 - z = x5720 - z = x5721 - z = x5722 - z = x5723 - z = x5724 - z = x5725 - z = x5726 - z = x5727 - z = x5728 - z = x5729 - z = x5730 - z = x5731 - z = x5732 - z = x5733 - z = x5734 - z = x5735 - z = x5736 - z = x5737 - z = x5738 - z = x5739 - z = x5740 - z = x5741 - z = x5742 - z = x5743 - z = x5744 - z = x5745 - z = x5746 - z = x5747 - z = x5748 - z = x5749 - z = x5750 - z = x5751 - z = x5752 - z = x5753 - z = x5754 - z = x5755 - z = x5756 - z = x5757 - z = x5758 - z = x5759 - z = x5760 - z = x5761 - z = x5762 - z = x5763 - z = x5764 - z = x5765 - z = x5766 - z = x5767 - z = x5768 - z = x5769 - z = x5770 - z = x5771 - z = x5772 - z = x5773 - z = x5774 - z = x5775 - z = x5776 - z = x5777 - z = x5778 - z = x5779 - z = x5780 - z = x5781 - z = x5782 - z = x5783 - z = x5784 - z = x5785 - z = x5786 - z = x5787 - z = x5788 - z = x5789 - z = x5790 - z = x5791 - z = x5792 - z = x5793 - z = x5794 - z = x5795 - z = x5796 - z = x5797 - z = x5798 - z = x5799 - z = x5800 - z = x5801 - z = x5802 - z = x5803 - z = x5804 - z = x5805 - z = x5806 - z = x5807 - z = x5808 - z = x5809 - z = x5810 - z = x5811 - z = x5812 - z = x5813 - z = x5814 - z = x5815 - z = x5816 - z = x5817 - z = x5818 - z = x5819 - z = x5820 - z = x5821 - z = x5822 - z = x5823 - z = x5824 - z = x5825 - z = x5826 - z = x5827 - z = x5828 - z = x5829 - z = x5830 - z = x5831 - z = x5832 - z = x5833 - z = x5834 - z = x5835 - z = x5836 - z = x5837 - z = x5838 - z = x5839 - z = x5840 - z = x5841 - z = x5842 - z = x5843 - z = x5844 - z = x5845 - z = x5846 - z = x5847 - z = x5848 - z = x5849 - z = x5850 - z = x5851 - z = x5852 - z = x5853 - z = x5854 - z = x5855 - z = x5856 - z = x5857 - z = x5858 - z = x5859 - z = x5860 - z = x5861 - z = x5862 - z = x5863 - z = x5864 - z = x5865 - z = x5866 - z = x5867 - z = x5868 - z = x5869 - z = x5870 - z = x5871 - z = x5872 - z = x5873 - z = x5874 - z = x5875 - z = x5876 - z = x5877 - z = x5878 - z = x5879 - z = x5880 - z = x5881 - z = x5882 - z = x5883 - z = x5884 - z = x5885 - z = x5886 - z = x5887 - z = x5888 - z = x5889 - z = x5890 - z = x5891 - z = x5892 - z = x5893 - z = x5894 - z = x5895 - z = x5896 - z = x5897 - z = x5898 - z = x5899 - z = x5900 - z = x5901 - z = x5902 - z = x5903 - z = x5904 - z = x5905 - z = x5906 - z = x5907 - z = x5908 - z = x5909 - z = x5910 - z = x5911 - z = x5912 - z = x5913 - z = x5914 - z = x5915 - z = x5916 - z = x5917 - z = x5918 - z = x5919 - z = x5920 - z = x5921 - z = x5922 - z = x5923 - z = x5924 - z = x5925 - z = x5926 - z = x5927 - z = x5928 - z = x5929 - z = x5930 - z = x5931 - z = x5932 - z = x5933 - z = x5934 - z = x5935 - z = x5936 - z = x5937 - z = x5938 - z = x5939 - z = x5940 - z = x5941 - z = x5942 - z = x5943 - z = x5944 - z = x5945 - z = x5946 - z = x5947 - z = x5948 - z = x5949 - z = x5950 - z = x5951 - z = x5952 - z = x5953 - z = x5954 - z = x5955 - z = x5956 - z = x5957 - z = x5958 - z = x5959 - z = x5960 - z = x5961 - z = x5962 - z = x5963 - z = x5964 - z = x5965 - z = x5966 - z = x5967 - z = x5968 - z = x5969 - z = x5970 - z = x5971 - z = x5972 - z = x5973 - z = x5974 - z = x5975 - z = x5976 - z = x5977 - z = x5978 - z = x5979 - z = x5980 - z = x5981 - z = x5982 - z = x5983 - z = x5984 - z = x5985 - z = x5986 - z = x5987 - z = x5988 - z = x5989 - z = x5990 - z = x5991 - z = x5992 - z = x5993 - z = x5994 - z = x5995 - z = x5996 - z = x5997 - z = x5998 - z = x5999 - z = x6000 - z = x6001 - z = x6002 - z = x6003 - z = x6004 - z = x6005 - z = x6006 - z = x6007 - z = x6008 - z = x6009 - z = x6010 - z = x6011 - z = x6012 - z = x6013 - z = x6014 - z = x6015 - z = x6016 - z = x6017 - z = x6018 - z = x6019 - z = x6020 - z = x6021 - z = x6022 - z = x6023 - z = x6024 - z = x6025 - z = x6026 - z = x6027 - z = x6028 - z = x6029 - z = x6030 - z = x6031 - z = x6032 - z = x6033 - z = x6034 - z = x6035 - z = x6036 - z = x6037 - z = x6038 - z = x6039 - z = x6040 - z = x6041 - z = x6042 - z = x6043 - z = x6044 - z = x6045 - z = x6046 - z = x6047 - z = x6048 - z = x6049 - z = x6050 - z = x6051 - z = x6052 - z = x6053 - z = x6054 - z = x6055 - z = x6056 - z = x6057 - z = x6058 - z = x6059 - z = x6060 - z = x6061 - z = x6062 - z = x6063 - z = x6064 - z = x6065 - z = x6066 - z = x6067 - z = x6068 - z = x6069 - z = x6070 - z = x6071 - z = x6072 - z = x6073 - z = x6074 - z = x6075 - z = x6076 - z = x6077 - z = x6078 - z = x6079 - z = x6080 - z = x6081 - z = x6082 - z = x6083 - z = x6084 - z = x6085 - z = x6086 - z = x6087 - z = x6088 - z = x6089 - z = x6090 - z = x6091 - z = x6092 - z = x6093 - z = x6094 - z = x6095 - z = x6096 - z = x6097 - z = x6098 - z = x6099 - z = x6100 - z = x6101 - z = x6102 - z = x6103 - z = x6104 - z = x6105 - z = x6106 - z = x6107 - z = x6108 - z = x6109 - z = x6110 - z = x6111 - z = x6112 - z = x6113 - z = x6114 - z = x6115 - z = x6116 - z = x6117 - z = x6118 - z = x6119 - z = x6120 - z = x6121 - z = x6122 - z = x6123 - z = x6124 - z = x6125 - z = x6126 - z = x6127 - z = x6128 - z = x6129 - z = x6130 - z = x6131 - z = x6132 - z = x6133 - z = x6134 - z = x6135 - z = x6136 - z = x6137 - z = x6138 - z = x6139 - z = x6140 - z = x6141 - z = x6142 - z = x6143 - z = x6144 - z = x6145 - z = x6146 - z = x6147 - z = x6148 - z = x6149 - z = x6150 - z = x6151 - z = x6152 - z = x6153 - z = x6154 - z = x6155 - z = x6156 - z = x6157 - z = x6158 - z = x6159 - z = x6160 - z = x6161 - z = x6162 - z = x6163 - z = x6164 - z = x6165 - z = x6166 - z = x6167 - z = x6168 - z = x6169 - z = x6170 - z = x6171 - z = x6172 - z = x6173 - z = x6174 - z = x6175 - z = x6176 - z = x6177 - z = x6178 - z = x6179 - z = x6180 - z = x6181 - z = x6182 - z = x6183 - z = x6184 - z = x6185 - z = x6186 - z = x6187 - z = x6188 - z = x6189 - z = x6190 - z = x6191 - z = x6192 - z = x6193 - z = x6194 - z = x6195 - z = x6196 - z = x6197 - z = x6198 - z = x6199 - z = x6200 - z = x6201 - z = x6202 - z = x6203 - z = x6204 - z = x6205 - z = x6206 - z = x6207 - z = x6208 - z = x6209 - z = x6210 - z = x6211 - z = x6212 - z = x6213 - z = x6214 - z = x6215 - z = x6216 - z = x6217 - z = x6218 - z = x6219 - z = x6220 - z = x6221 - z = x6222 - z = x6223 - z = x6224 - z = x6225 - z = x6226 - z = x6227 - z = x6228 - z = x6229 - z = x6230 - z = x6231 - z = x6232 - z = x6233 - z = x6234 - z = x6235 - z = x6236 - z = x6237 - z = x6238 - z = x6239 - z = x6240 - z = x6241 - z = x6242 - z = x6243 - z = x6244 - z = x6245 - z = x6246 - z = x6247 - z = x6248 - z = x6249 - z = x6250 - z = x6251 - z = x6252 - z = x6253 - z = x6254 - z = x6255 - z = x6256 - z = x6257 - z = x6258 - z = x6259 - z = x6260 - z = x6261 - z = x6262 - z = x6263 - z = x6264 - z = x6265 - z = x6266 - z = x6267 - z = x6268 - z = x6269 - z = x6270 - z = x6271 - z = x6272 - z = x6273 - z = x6274 - z = x6275 - z = x6276 - z = x6277 - z = x6278 - z = x6279 - z = x6280 - z = x6281 - z = x6282 - z = x6283 - z = x6284 - z = x6285 - z = x6286 - z = x6287 - z = x6288 - z = x6289 - z = x6290 - z = x6291 - z = x6292 - z = x6293 - z = x6294 - z = x6295 - z = x6296 - z = x6297 - z = x6298 - z = x6299 - z = x6300 - z = x6301 - z = x6302 - z = x6303 - z = x6304 - z = x6305 - z = x6306 - z = x6307 - z = x6308 - z = x6309 - z = x6310 - z = x6311 - z = x6312 - z = x6313 - z = x6314 - z = x6315 - z = x6316 - z = x6317 - z = x6318 - z = x6319 - z = x6320 - z = x6321 - z = x6322 - z = x6323 - z = x6324 - z = x6325 - z = x6326 - z = x6327 - z = x6328 - z = x6329 - z = x6330 - z = x6331 - z = x6332 - z = x6333 - z = x6334 - z = x6335 - z = x6336 - z = x6337 - z = x6338 - z = x6339 - z = x6340 - z = x6341 - z = x6342 - z = x6343 - z = x6344 - z = x6345 - z = x6346 - z = x6347 - z = x6348 - z = x6349 - z = x6350 - z = x6351 - z = x6352 - z = x6353 - z = x6354 - z = x6355 - z = x6356 - z = x6357 - z = x6358 - z = x6359 - z = x6360 - z = x6361 - z = x6362 - z = x6363 - z = x6364 - z = x6365 - z = x6366 - z = x6367 - z = x6368 - z = x6369 - z = x6370 - z = x6371 - z = x6372 - z = x6373 - z = x6374 - z = x6375 - z = x6376 - z = x6377 - z = x6378 - z = x6379 - z = x6380 - z = x6381 - z = x6382 - z = x6383 - z = x6384 - z = x6385 - z = x6386 - z = x6387 - z = x6388 - z = x6389 - z = x6390 - z = x6391 - z = x6392 - z = x6393 - z = x6394 - z = x6395 - z = x6396 - z = x6397 - z = x6398 - z = x6399 - z = x6400 - z = x6401 - z = x6402 - z = x6403 - z = x6404 - z = x6405 - z = x6406 - z = x6407 - z = x6408 - z = x6409 - z = x6410 - z = x6411 - z = x6412 - z = x6413 - z = x6414 - z = x6415 - z = x6416 - z = x6417 - z = x6418 - z = x6419 - z = x6420 - z = x6421 - z = x6422 - z = x6423 - z = x6424 - z = x6425 - z = x6426 - z = x6427 - z = x6428 - z = x6429 - z = x6430 - z = x6431 - z = x6432 - z = x6433 - z = x6434 - z = x6435 - z = x6436 - z = x6437 - z = x6438 - z = x6439 - z = x6440 - z = x6441 - z = x6442 - z = x6443 - z = x6444 - z = x6445 - z = x6446 - z = x6447 - z = x6448 - z = x6449 - z = x6450 - z = x6451 - z = x6452 - z = x6453 - z = x6454 - z = x6455 - z = x6456 - z = x6457 - z = x6458 - z = x6459 - z = x6460 - z = x6461 - z = x6462 - z = x6463 - z = x6464 - z = x6465 - z = x6466 - z = x6467 - z = x6468 - z = x6469 - z = x6470 - z = x6471 - z = x6472 - z = x6473 - z = x6474 - z = x6475 - z = x6476 - z = x6477 - z = x6478 - z = x6479 - z = x6480 - z = x6481 - z = x6482 - z = x6483 - z = x6484 - z = x6485 - z = x6486 - z = x6487 - z = x6488 - z = x6489 - z = x6490 - z = x6491 - z = x6492 - z = x6493 - z = x6494 - z = x6495 - z = x6496 - z = x6497 - z = x6498 - z = x6499 - z = x6500 - z = x6501 - z = x6502 - z = x6503 - z = x6504 - z = x6505 - z = x6506 - z = x6507 - z = x6508 - z = x6509 - z = x6510 - z = x6511 - z = x6512 - z = x6513 - z = x6514 - z = x6515 - z = x6516 - z = x6517 - z = x6518 - z = x6519 - z = x6520 - z = x6521 - z = x6522 - z = x6523 - z = x6524 - z = x6525 - z = x6526 - z = x6527 - z = x6528 - z = x6529 - z = x6530 - z = x6531 - z = x6532 - z = x6533 - z = x6534 - z = x6535 - z = x6536 - z = x6537 - z = x6538 - z = x6539 - z = x6540 - z = x6541 - z = x6542 - z = x6543 - z = x6544 - z = x6545 - z = x6546 - z = x6547 - z = x6548 - z = x6549 - z = x6550 - z = x6551 - z = x6552 - z = x6553 - z = x6554 - z = x6555 - z = x6556 - z = x6557 - z = x6558 - z = x6559 - z = x6560 - z = x6561 - z = x6562 - z = x6563 - z = x6564 - z = x6565 - z = x6566 - z = x6567 - z = x6568 - z = x6569 - z = x6570 - z = x6571 - z = x6572 - z = x6573 - z = x6574 - z = x6575 - z = x6576 - z = x6577 - z = x6578 - z = x6579 - z = x6580 - z = x6581 - z = x6582 - z = x6583 - z = x6584 - z = x6585 - z = x6586 - z = x6587 - z = x6588 - z = x6589 - z = x6590 - z = x6591 - z = x6592 - z = x6593 - z = x6594 - z = x6595 - z = x6596 - z = x6597 - z = x6598 - z = x6599 - z = x6600 - z = x6601 - z = x6602 - z = x6603 - z = x6604 - z = x6605 - z = x6606 - z = x6607 - z = x6608 - z = x6609 - z = x6610 - z = x6611 - z = x6612 - z = x6613 - z = x6614 - z = x6615 - z = x6616 - z = x6617 - z = x6618 - z = x6619 - z = x6620 - z = x6621 - z = x6622 - z = x6623 - z = x6624 - z = x6625 - z = x6626 - z = x6627 - z = x6628 - z = x6629 - z = x6630 - z = x6631 - z = x6632 - z = x6633 - z = x6634 - z = x6635 - z = x6636 - z = x6637 - z = x6638 - z = x6639 - z = x6640 - z = x6641 - z = x6642 - z = x6643 - z = x6644 - z = x6645 - z = x6646 - z = x6647 - z = x6648 - z = x6649 - z = x6650 - z = x6651 - z = x6652 - z = x6653 - z = x6654 - z = x6655 - z = x6656 - z = x6657 - z = x6658 - z = x6659 - z = x6660 - z = x6661 - z = x6662 - z = x6663 - z = x6664 - z = x6665 - z = x6666 - z = x6667 - z = x6668 - z = x6669 - z = x6670 - z = x6671 - z = x6672 - z = x6673 - z = x6674 - z = x6675 - z = x6676 - z = x6677 - z = x6678 - z = x6679 - z = x6680 - z = x6681 - z = x6682 - z = x6683 - z = x6684 - z = x6685 - z = x6686 - z = x6687 - z = x6688 - z = x6689 - z = x6690 - z = x6691 - z = x6692 - z = x6693 - z = x6694 - z = x6695 - z = x6696 - z = x6697 - z = x6698 - z = x6699 - z = x6700 - z = x6701 - z = x6702 - z = x6703 - z = x6704 - z = x6705 - z = x6706 - z = x6707 - z = x6708 - z = x6709 - z = x6710 - z = x6711 - z = x6712 - z = x6713 - z = x6714 - z = x6715 - z = x6716 - z = x6717 - z = x6718 - z = x6719 - z = x6720 - z = x6721 - z = x6722 - z = x6723 - z = x6724 - z = x6725 - z = x6726 - z = x6727 - z = x6728 - z = x6729 - z = x6730 - z = x6731 - z = x6732 - z = x6733 - z = x6734 - z = x6735 - z = x6736 - z = x6737 - z = x6738 - z = x6739 - z = x6740 - z = x6741 - z = x6742 - z = x6743 - z = x6744 - z = x6745 - z = x6746 - z = x6747 - z = x6748 - z = x6749 - z = x6750 - z = x6751 - z = x6752 - z = x6753 - z = x6754 - z = x6755 - z = x6756 - z = x6757 - z = x6758 - z = x6759 - z = x6760 - z = x6761 - z = x6762 - z = x6763 - z = x6764 - z = x6765 - z = x6766 - z = x6767 - z = x6768 - z = x6769 - z = x6770 - z = x6771 - z = x6772 - z = x6773 - z = x6774 - z = x6775 - z = x6776 - z = x6777 - z = x6778 - z = x6779 - z = x6780 - z = x6781 - z = x6782 - z = x6783 - z = x6784 - z = x6785 - z = x6786 - z = x6787 - z = x6788 - z = x6789 - z = x6790 - z = x6791 - z = x6792 - z = x6793 - z = x6794 - z = x6795 - z = x6796 - z = x6797 - z = x6798 - z = x6799 - z = x6800 - z = x6801 - z = x6802 - z = x6803 - z = x6804 - z = x6805 - z = x6806 - z = x6807 - z = x6808 - z = x6809 - z = x6810 - z = x6811 - z = x6812 - z = x6813 - z = x6814 - z = x6815 - z = x6816 - z = x6817 - z = x6818 - z = x6819 - z = x6820 - z = x6821 - z = x6822 - z = x6823 - z = x6824 - z = x6825 - z = x6826 - z = x6827 - z = x6828 - z = x6829 - z = x6830 - z = x6831 - z = x6832 - z = x6833 - z = x6834 - z = x6835 - z = x6836 - z = x6837 - z = x6838 - z = x6839 - z = x6840 - z = x6841 - z = x6842 - z = x6843 - z = x6844 - z = x6845 - z = x6846 - z = x6847 - z = x6848 - z = x6849 - z = x6850 - z = x6851 - z = x6852 - z = x6853 - z = x6854 - z = x6855 - z = x6856 - z = x6857 - z = x6858 - z = x6859 - z = x6860 - z = x6861 - z = x6862 - z = x6863 - z = x6864 - z = x6865 - z = x6866 - z = x6867 - z = x6868 - z = x6869 - z = x6870 - z = x6871 - z = x6872 - z = x6873 - z = x6874 - z = x6875 - z = x6876 - z = x6877 - z = x6878 - z = x6879 - z = x6880 - z = x6881 - z = x6882 - z = x6883 - z = x6884 - z = x6885 - z = x6886 - z = x6887 - z = x6888 - z = x6889 - z = x6890 - z = x6891 - z = x6892 - z = x6893 - z = x6894 - z = x6895 - z = x6896 - z = x6897 - z = x6898 - z = x6899 - z = x6900 - z = x6901 - z = x6902 - z = x6903 - z = x6904 - z = x6905 - z = x6906 - z = x6907 - z = x6908 - z = x6909 - z = x6910 - z = x6911 - z = x6912 - z = x6913 - z = x6914 - z = x6915 - z = x6916 - z = x6917 - z = x6918 - z = x6919 - z = x6920 - z = x6921 - z = x6922 - z = x6923 - z = x6924 - z = x6925 - z = x6926 - z = x6927 - z = x6928 - z = x6929 - z = x6930 - z = x6931 - z = x6932 - z = x6933 - z = x6934 - z = x6935 - z = x6936 - z = x6937 - z = x6938 - z = x6939 - z = x6940 - z = x6941 - z = x6942 - z = x6943 - z = x6944 - z = x6945 - z = x6946 - z = x6947 - z = x6948 - z = x6949 - z = x6950 - z = x6951 - z = x6952 - z = x6953 - z = x6954 - z = x6955 - z = x6956 - z = x6957 - z = x6958 - z = x6959 - z = x6960 - z = x6961 - z = x6962 - z = x6963 - z = x6964 - z = x6965 - z = x6966 - z = x6967 - z = x6968 - z = x6969 - z = x6970 - z = x6971 - z = x6972 - z = x6973 - z = x6974 - z = x6975 - z = x6976 - z = x6977 - z = x6978 - z = x6979 - z = x6980 - z = x6981 - z = x6982 - z = x6983 - z = x6984 - z = x6985 - z = x6986 - z = x6987 - z = x6988 - z = x6989 - z = x6990 - z = x6991 - z = x6992 - z = x6993 - z = x6994 - z = x6995 - z = x6996 - z = x6997 - z = x6998 - z = x6999 - z = x7000 - z = x7001 - z = x7002 - z = x7003 - z = x7004 - z = x7005 - z = x7006 - z = x7007 - z = x7008 - z = x7009 - z = x7010 - z = x7011 - z = x7012 - z = x7013 - z = x7014 - z = x7015 - z = x7016 - z = x7017 - z = x7018 - z = x7019 - z = x7020 - z = x7021 - z = x7022 - z = x7023 - z = x7024 - z = x7025 - z = x7026 - z = x7027 - z = x7028 - z = x7029 - z = x7030 - z = x7031 - z = x7032 - z = x7033 - z = x7034 - z = x7035 - z = x7036 - z = x7037 - z = x7038 - z = x7039 - z = x7040 - z = x7041 - z = x7042 - z = x7043 - z = x7044 - z = x7045 - z = x7046 - z = x7047 - z = x7048 - z = x7049 - z = x7050 - z = x7051 - z = x7052 - z = x7053 - z = x7054 - z = x7055 - z = x7056 - z = x7057 - z = x7058 - z = x7059 - z = x7060 - z = x7061 - z = x7062 - z = x7063 - z = x7064 - z = x7065 - z = x7066 - z = x7067 - z = x7068 - z = x7069 - z = x7070 - z = x7071 - z = x7072 - z = x7073 - z = x7074 - z = x7075 - z = x7076 - z = x7077 - z = x7078 - z = x7079 - z = x7080 - z = x7081 - z = x7082 - z = x7083 - z = x7084 - z = x7085 - z = x7086 - z = x7087 - z = x7088 - z = x7089 - z = x7090 - z = x7091 - z = x7092 - z = x7093 - z = x7094 - z = x7095 - z = x7096 - z = x7097 - z = x7098 - z = x7099 - z = x7100 - z = x7101 - z = x7102 - z = x7103 - z = x7104 - z = x7105 - z = x7106 - z = x7107 - z = x7108 - z = x7109 - z = x7110 - z = x7111 - z = x7112 - z = x7113 - z = x7114 - z = x7115 - z = x7116 - z = x7117 - z = x7118 - z = x7119 - z = x7120 - z = x7121 - z = x7122 - z = x7123 - z = x7124 - z = x7125 - z = x7126 - z = x7127 - z = x7128 - z = x7129 - z = x7130 - z = x7131 - z = x7132 - z = x7133 - z = x7134 - z = x7135 - z = x7136 - z = x7137 - z = x7138 - z = x7139 - z = x7140 - z = x7141 - z = x7142 - z = x7143 - z = x7144 - z = x7145 - z = x7146 - z = x7147 - z = x7148 - z = x7149 - z = x7150 - z = x7151 - z = x7152 - z = x7153 - z = x7154 - z = x7155 - z = x7156 - z = x7157 - z = x7158 - z = x7159 - z = x7160 - z = x7161 - z = x7162 - z = x7163 - z = x7164 - z = x7165 - z = x7166 - z = x7167 - z = x7168 - z = x7169 - z = x7170 - z = x7171 - z = x7172 - z = x7173 - z = x7174 - z = x7175 - z = x7176 - z = x7177 - z = x7178 - z = x7179 - z = x7180 - z = x7181 - z = x7182 - z = x7183 - z = x7184 - z = x7185 - z = x7186 - z = x7187 - z = x7188 - z = x7189 - z = x7190 - z = x7191 - z = x7192 - z = x7193 - z = x7194 - z = x7195 - z = x7196 - z = x7197 - z = x7198 - z = x7199 - z = x7200 - z = x7201 - z = x7202 - z = x7203 - z = x7204 - z = x7205 - z = x7206 - z = x7207 - z = x7208 - z = x7209 - z = x7210 - z = x7211 - z = x7212 - z = x7213 - z = x7214 - z = x7215 - z = x7216 - z = x7217 - z = x7218 - z = x7219 - z = x7220 - z = x7221 - z = x7222 - z = x7223 - z = x7224 - z = x7225 - z = x7226 - z = x7227 - z = x7228 - z = x7229 - z = x7230 - z = x7231 - z = x7232 - z = x7233 - z = x7234 - z = x7235 - z = x7236 - z = x7237 - z = x7238 - z = x7239 - z = x7240 - z = x7241 - z = x7242 - z = x7243 - z = x7244 - z = x7245 - z = x7246 - z = x7247 - z = x7248 - z = x7249 - z = x7250 - z = x7251 - z = x7252 - z = x7253 - z = x7254 - z = x7255 - z = x7256 - z = x7257 - z = x7258 - z = x7259 - z = x7260 - z = x7261 - z = x7262 - z = x7263 - z = x7264 - z = x7265 - z = x7266 - z = x7267 - z = x7268 - z = x7269 - z = x7270 - z = x7271 - z = x7272 - z = x7273 - z = x7274 - z = x7275 - z = x7276 - z = x7277 - z = x7278 - z = x7279 - z = x7280 - z = x7281 - z = x7282 - z = x7283 - z = x7284 - z = x7285 - z = x7286 - z = x7287 - z = x7288 - z = x7289 - z = x7290 - z = x7291 - z = x7292 - z = x7293 - z = x7294 - z = x7295 - z = x7296 - z = x7297 - z = x7298 - z = x7299 - z = x7300 - z = x7301 - z = x7302 - z = x7303 - z = x7304 - z = x7305 - z = x7306 - z = x7307 - z = x7308 - z = x7309 - z = x7310 - z = x7311 - z = x7312 - z = x7313 - z = x7314 - z = x7315 - z = x7316 - z = x7317 - z = x7318 - z = x7319 - z = x7320 - z = x7321 - z = x7322 - z = x7323 - z = x7324 - z = x7325 - z = x7326 - z = x7327 - z = x7328 - z = x7329 - z = x7330 - z = x7331 - z = x7332 - z = x7333 - z = x7334 - z = x7335 - z = x7336 - z = x7337 - z = x7338 - z = x7339 - z = x7340 - z = x7341 - z = x7342 - z = x7343 - z = x7344 - z = x7345 - z = x7346 - z = x7347 - z = x7348 - z = x7349 - z = x7350 - z = x7351 - z = x7352 - z = x7353 - z = x7354 - z = x7355 - z = x7356 - z = x7357 - z = x7358 - z = x7359 - z = x7360 - z = x7361 - z = x7362 - z = x7363 - z = x7364 - z = x7365 - z = x7366 - z = x7367 - z = x7368 - z = x7369 - z = x7370 - z = x7371 - z = x7372 - z = x7373 - z = x7374 - z = x7375 - z = x7376 - z = x7377 - z = x7378 - z = x7379 - z = x7380 - z = x7381 - z = x7382 - z = x7383 - z = x7384 - z = x7385 - z = x7386 - z = x7387 - z = x7388 - z = x7389 - z = x7390 - z = x7391 - z = x7392 - z = x7393 - z = x7394 - z = x7395 - z = x7396 - z = x7397 - z = x7398 - z = x7399 - z = x7400 - z = x7401 - z = x7402 - z = x7403 - z = x7404 - z = x7405 - z = x7406 - z = x7407 - z = x7408 - z = x7409 - z = x7410 - z = x7411 - z = x7412 - z = x7413 - z = x7414 - z = x7415 - z = x7416 - z = x7417 - z = x7418 - z = x7419 - z = x7420 - z = x7421 - z = x7422 - z = x7423 - z = x7424 - z = x7425 - z = x7426 - z = x7427 - z = x7428 - z = x7429 - z = x7430 - z = x7431 - z = x7432 - z = x7433 - z = x7434 - z = x7435 - z = x7436 - z = x7437 - z = x7438 - z = x7439 - z = x7440 - z = x7441 - z = x7442 - z = x7443 - z = x7444 - z = x7445 - z = x7446 - z = x7447 - z = x7448 - z = x7449 - z = x7450 - z = x7451 - z = x7452 - z = x7453 - z = x7454 - z = x7455 - z = x7456 - z = x7457 - z = x7458 - z = x7459 - z = x7460 - z = x7461 - z = x7462 - z = x7463 - z = x7464 - z = x7465 - z = x7466 - z = x7467 - z = x7468 - z = x7469 - z = x7470 - z = x7471 - z = x7472 - z = x7473 - z = x7474 - z = x7475 - z = x7476 - z = x7477 - z = x7478 - z = x7479 - z = x7480 - z = x7481 - z = x7482 - z = x7483 - z = x7484 - z = x7485 - z = x7486 - z = x7487 - z = x7488 - z = x7489 - z = x7490 - z = x7491 - z = x7492 - z = x7493 - z = x7494 - z = x7495 - z = x7496 - z = x7497 - z = x7498 - z = x7499 - z = x7500 - z = x7501 - z = x7502 - z = x7503 - z = x7504 - z = x7505 - z = x7506 - z = x7507 - z = x7508 - z = x7509 - z = x7510 - z = x7511 - z = x7512 - z = x7513 - z = x7514 - z = x7515 - z = x7516 - z = x7517 - z = x7518 - z = x7519 - z = x7520 - z = x7521 - z = x7522 - z = x7523 - z = x7524 - z = x7525 - z = x7526 - z = x7527 - z = x7528 - z = x7529 - z = x7530 - z = x7531 - z = x7532 - z = x7533 - z = x7534 - z = x7535 - z = x7536 - z = x7537 - z = x7538 - z = x7539 - z = x7540 - z = x7541 - z = x7542 - z = x7543 - z = x7544 - z = x7545 - z = x7546 - z = x7547 - z = x7548 - z = x7549 - z = x7550 - z = x7551 - z = x7552 - z = x7553 - z = x7554 - z = x7555 - z = x7556 - z = x7557 - z = x7558 - z = x7559 - z = x7560 - z = x7561 - z = x7562 - z = x7563 - z = x7564 - z = x7565 - z = x7566 - z = x7567 - z = x7568 - z = x7569 - z = x7570 - z = x7571 - z = x7572 - z = x7573 - z = x7574 - z = x7575 - z = x7576 - z = x7577 - z = x7578 - z = x7579 - z = x7580 - z = x7581 - z = x7582 - z = x7583 - z = x7584 - z = x7585 - z = x7586 - z = x7587 - z = x7588 - z = x7589 - z = x7590 - z = x7591 - z = x7592 - z = x7593 - z = x7594 - z = x7595 - z = x7596 - z = x7597 - z = x7598 - z = x7599 - z = x7600 - z = x7601 - z = x7602 - z = x7603 - z = x7604 - z = x7605 - z = x7606 - z = x7607 - z = x7608 - z = x7609 - z = x7610 - z = x7611 - z = x7612 - z = x7613 - z = x7614 - z = x7615 - z = x7616 - z = x7617 - z = x7618 - z = x7619 - z = x7620 - z = x7621 - z = x7622 - z = x7623 - z = x7624 - z = x7625 - z = x7626 - z = x7627 - z = x7628 - z = x7629 - z = x7630 - z = x7631 - z = x7632 - z = x7633 - z = x7634 - z = x7635 - z = x7636 - z = x7637 - z = x7638 - z = x7639 - z = x7640 - z = x7641 - z = x7642 - z = x7643 - z = x7644 - z = x7645 - z = x7646 - z = x7647 - z = x7648 - z = x7649 - z = x7650 - z = x7651 - z = x7652 - z = x7653 - z = x7654 - z = x7655 - z = x7656 - z = x7657 - z = x7658 - z = x7659 - z = x7660 - z = x7661 - z = x7662 - z = x7663 - z = x7664 - z = x7665 - z = x7666 - z = x7667 - z = x7668 - z = x7669 - z = x7670 - z = x7671 - z = x7672 - z = x7673 - z = x7674 - z = x7675 - z = x7676 - z = x7677 - z = x7678 - z = x7679 - z = x7680 - z = x7681 - z = x7682 - z = x7683 - z = x7684 - z = x7685 - z = x7686 - z = x7687 - z = x7688 - z = x7689 - z = x7690 - z = x7691 - z = x7692 - z = x7693 - z = x7694 - z = x7695 - z = x7696 - z = x7697 - z = x7698 - z = x7699 - z = x7700 - z = x7701 - z = x7702 - z = x7703 - z = x7704 - z = x7705 - z = x7706 - z = x7707 - z = x7708 - z = x7709 - z = x7710 - z = x7711 - z = x7712 - z = x7713 - z = x7714 - z = x7715 - z = x7716 - z = x7717 - z = x7718 - z = x7719 - z = x7720 - z = x7721 - z = x7722 - z = x7723 - z = x7724 - z = x7725 - z = x7726 - z = x7727 - z = x7728 - z = x7729 - z = x7730 - z = x7731 - z = x7732 - z = x7733 - z = x7734 - z = x7735 - z = x7736 - z = x7737 - z = x7738 - z = x7739 - z = x7740 - z = x7741 - z = x7742 - z = x7743 - z = x7744 - z = x7745 - z = x7746 - z = x7747 - z = x7748 - z = x7749 - z = x7750 - z = x7751 - z = x7752 - z = x7753 - z = x7754 - z = x7755 - z = x7756 - z = x7757 - z = x7758 - z = x7759 - z = x7760 - z = x7761 - z = x7762 - z = x7763 - z = x7764 - z = x7765 - z = x7766 - z = x7767 - z = x7768 - z = x7769 - z = x7770 - z = x7771 - z = x7772 - z = x7773 - z = x7774 - z = x7775 - z = x7776 - z = x7777 - z = x7778 - z = x7779 - z = x7780 - z = x7781 - z = x7782 - z = x7783 - z = x7784 - z = x7785 - z = x7786 - z = x7787 - z = x7788 - z = x7789 - z = x7790 - z = x7791 - z = x7792 - z = x7793 - z = x7794 - z = x7795 - z = x7796 - z = x7797 - z = x7798 - z = x7799 - z = x7800 - z = x7801 - z = x7802 - z = x7803 - z = x7804 - z = x7805 - z = x7806 - z = x7807 - z = x7808 - z = x7809 - z = x7810 - z = x7811 - z = x7812 - z = x7813 - z = x7814 - z = x7815 - z = x7816 - z = x7817 - z = x7818 - z = x7819 - z = x7820 - z = x7821 - z = x7822 - z = x7823 - z = x7824 - z = x7825 - z = x7826 - z = x7827 - z = x7828 - z = x7829 - z = x7830 - z = x7831 - z = x7832 - z = x7833 - z = x7834 - z = x7835 - z = x7836 - z = x7837 - z = x7838 - z = x7839 - z = x7840 - z = x7841 - z = x7842 - z = x7843 - z = x7844 - z = x7845 - z = x7846 - z = x7847 - z = x7848 - z = x7849 - z = x7850 - z = x7851 - z = x7852 - z = x7853 - z = x7854 - z = x7855 - z = x7856 - z = x7857 - z = x7858 - z = x7859 - z = x7860 - z = x7861 - z = x7862 - z = x7863 - z = x7864 - z = x7865 - z = x7866 - z = x7867 - z = x7868 - z = x7869 - z = x7870 - z = x7871 - z = x7872 - z = x7873 - z = x7874 - z = x7875 - z = x7876 - z = x7877 - z = x7878 - z = x7879 - z = x7880 - z = x7881 - z = x7882 - z = x7883 - z = x7884 - z = x7885 - z = x7886 - z = x7887 - z = x7888 - z = x7889 - z = x7890 - z = x7891 - z = x7892 - z = x7893 - z = x7894 - z = x7895 - z = x7896 - z = x7897 - z = x7898 - z = x7899 - z = x7900 - z = x7901 - z = x7902 - z = x7903 - z = x7904 - z = x7905 - z = x7906 - z = x7907 - z = x7908 - z = x7909 - z = x7910 - z = x7911 - z = x7912 - z = x7913 - z = x7914 - z = x7915 - z = x7916 - z = x7917 - z = x7918 - z = x7919 - z = x7920 - z = x7921 - z = x7922 - z = x7923 - z = x7924 - z = x7925 - z = x7926 - z = x7927 - z = x7928 - z = x7929 - z = x7930 - z = x7931 - z = x7932 - z = x7933 - z = x7934 - z = x7935 - z = x7936 - z = x7937 - z = x7938 - z = x7939 - z = x7940 - z = x7941 - z = x7942 - z = x7943 - z = x7944 - z = x7945 - z = x7946 - z = x7947 - z = x7948 - z = x7949 - z = x7950 - z = x7951 - z = x7952 - z = x7953 - z = x7954 - z = x7955 - z = x7956 - z = x7957 - z = x7958 - z = x7959 - z = x7960 - z = x7961 - z = x7962 - z = x7963 - z = x7964 - z = x7965 - z = x7966 - z = x7967 - z = x7968 - z = x7969 - z = x7970 - z = x7971 - z = x7972 - z = x7973 - z = x7974 - z = x7975 - z = x7976 - z = x7977 - z = x7978 - z = x7979 - z = x7980 - z = x7981 - z = x7982 - z = x7983 - z = x7984 - z = x7985 - z = x7986 - z = x7987 - z = x7988 - z = x7989 - z = x7990 - z = x7991 - z = x7992 - z = x7993 - z = x7994 - z = x7995 - z = x7996 - z = x7997 - z = x7998 - z = x7999 - z = x8000 - z = x8001 - z = x8002 - z = x8003 - z = x8004 - z = x8005 - z = x8006 - z = x8007 - z = x8008 - z = x8009 - z = x8010 - z = x8011 - z = x8012 - z = x8013 - z = x8014 - z = x8015 - z = x8016 - z = x8017 - z = x8018 - z = x8019 - z = x8020 - z = x8021 - z = x8022 - z = x8023 - z = x8024 - z = x8025 - z = x8026 - z = x8027 - z = x8028 - z = x8029 - z = x8030 - z = x8031 - z = x8032 - z = x8033 - z = x8034 - z = x8035 - z = x8036 - z = x8037 - z = x8038 - z = x8039 - z = x8040 - z = x8041 - z = x8042 - z = x8043 - z = x8044 - z = x8045 - z = x8046 - z = x8047 - z = x8048 - z = x8049 - z = x8050 - z = x8051 - z = x8052 - z = x8053 - z = x8054 - z = x8055 - z = x8056 - z = x8057 - z = x8058 - z = x8059 - z = x8060 - z = x8061 - z = x8062 - z = x8063 - z = x8064 - z = x8065 - z = x8066 - z = x8067 - z = x8068 - z = x8069 - z = x8070 - z = x8071 - z = x8072 - z = x8073 - z = x8074 - z = x8075 - z = x8076 - z = x8077 - z = x8078 - z = x8079 - z = x8080 - z = x8081 - z = x8082 - z = x8083 - z = x8084 - z = x8085 - z = x8086 - z = x8087 - z = x8088 - z = x8089 - z = x8090 - z = x8091 - z = x8092 - z = x8093 - z = x8094 - z = x8095 - z = x8096 - z = x8097 - z = x8098 - z = x8099 - z = x8100 - z = x8101 - z = x8102 - z = x8103 - z = x8104 - z = x8105 - z = x8106 - z = x8107 - z = x8108 - z = x8109 - z = x8110 - z = x8111 - z = x8112 - z = x8113 - z = x8114 - z = x8115 - z = x8116 - z = x8117 - z = x8118 - z = x8119 - z = x8120 - z = x8121 - z = x8122 - z = x8123 - z = x8124 - z = x8125 - z = x8126 - z = x8127 - z = x8128 - z = x8129 - z = x8130 - z = x8131 - z = x8132 - z = x8133 - z = x8134 - z = x8135 - z = x8136 - z = x8137 - z = x8138 - z = x8139 - z = x8140 - z = x8141 - z = x8142 - z = x8143 - z = x8144 - z = x8145 - z = x8146 - z = x8147 - z = x8148 - z = x8149 - z = x8150 - z = x8151 - z = x8152 - z = x8153 - z = x8154 - z = x8155 - z = x8156 - z = x8157 - z = x8158 - z = x8159 - z = x8160 - z = x8161 - z = x8162 - z = x8163 - z = x8164 - z = x8165 - z = x8166 - z = x8167 - z = x8168 - z = x8169 - z = x8170 - z = x8171 - z = x8172 - z = x8173 - z = x8174 - z = x8175 - z = x8176 - z = x8177 - z = x8178 - z = x8179 - z = x8180 - z = x8181 - z = x8182 - z = x8183 - z = x8184 - z = x8185 - z = x8186 - z = x8187 - z = x8188 - z = x8189 - z = x8190 - z = x8191 - z = x8192 - z = x8193 - z = x8194 - z = x8195 - z = x8196 - z = x8197 - z = x8198 - z = x8199 - z = x8200 - z = x8201 - z = x8202 - z = x8203 - z = x8204 - z = x8205 - z = x8206 - z = x8207 - z = x8208 - z = x8209 - z = x8210 - z = x8211 - z = x8212 - z = x8213 - z = x8214 - z = x8215 - z = x8216 - z = x8217 - z = x8218 - z = x8219 - z = x8220 - z = x8221 - z = x8222 - z = x8223 - z = x8224 - z = x8225 - z = x8226 - z = x8227 - z = x8228 - z = x8229 - z = x8230 - z = x8231 - z = x8232 - z = x8233 - z = x8234 - z = x8235 - z = x8236 - z = x8237 - z = x8238 - z = x8239 - z = x8240 - z = x8241 - z = x8242 - z = x8243 - z = x8244 - z = x8245 - z = x8246 - z = x8247 - z = x8248 - z = x8249 - z = x8250 - z = x8251 - z = x8252 - z = x8253 - z = x8254 - z = x8255 - z = x8256 - z = x8257 - z = x8258 - z = x8259 - z = x8260 - z = x8261 - z = x8262 - z = x8263 - z = x8264 - z = x8265 - z = x8266 - z = x8267 - z = x8268 - z = x8269 - z = x8270 - z = x8271 - z = x8272 - z = x8273 - z = x8274 - z = x8275 - z = x8276 - z = x8277 - z = x8278 - z = x8279 - z = x8280 - z = x8281 - z = x8282 - z = x8283 - z = x8284 - z = x8285 - z = x8286 - z = x8287 - z = x8288 - z = x8289 - z = x8290 - z = x8291 - z = x8292 - z = x8293 - z = x8294 - z = x8295 - z = x8296 - z = x8297 - z = x8298 - z = x8299 - z = x8300 - z = x8301 - z = x8302 - z = x8303 - z = x8304 - z = x8305 - z = x8306 - z = x8307 - z = x8308 - z = x8309 - z = x8310 - z = x8311 - z = x8312 - z = x8313 - z = x8314 - z = x8315 - z = x8316 - z = x8317 - z = x8318 - z = x8319 - z = x8320 - z = x8321 - z = x8322 - z = x8323 - z = x8324 - z = x8325 - z = x8326 - z = x8327 - z = x8328 - z = x8329 - z = x8330 - z = x8331 - z = x8332 - z = x8333 - z = x8334 - z = x8335 - z = x8336 - z = x8337 - z = x8338 - z = x8339 - z = x8340 - z = x8341 - z = x8342 - z = x8343 - z = x8344 - z = x8345 - z = x8346 - z = x8347 - z = x8348 - z = x8349 - z = x8350 - z = x8351 - z = x8352 - z = x8353 - z = x8354 - z = x8355 - z = x8356 - z = x8357 - z = x8358 - z = x8359 - z = x8360 - z = x8361 - z = x8362 - z = x8363 - z = x8364 - z = x8365 - z = x8366 - z = x8367 - z = x8368 - z = x8369 - z = x8370 - z = x8371 - z = x8372 - z = x8373 - z = x8374 - z = x8375 - z = x8376 - z = x8377 - z = x8378 - z = x8379 - z = x8380 - z = x8381 - z = x8382 - z = x8383 - z = x8384 - z = x8385 - z = x8386 - z = x8387 - z = x8388 - z = x8389 - z = x8390 - z = x8391 - z = x8392 - z = x8393 - z = x8394 - z = x8395 - z = x8396 - z = x8397 - z = x8398 - z = x8399 - z = x8400 - z = x8401 - z = x8402 - z = x8403 - z = x8404 - z = x8405 - z = x8406 - z = x8407 - z = x8408 - z = x8409 - z = x8410 - z = x8411 - z = x8412 - z = x8413 - z = x8414 - z = x8415 - z = x8416 - z = x8417 - z = x8418 - z = x8419 - z = x8420 - z = x8421 - z = x8422 - z = x8423 - z = x8424 - z = x8425 - z = x8426 - z = x8427 - z = x8428 - z = x8429 - z = x8430 - z = x8431 - z = x8432 - z = x8433 - z = x8434 - z = x8435 - z = x8436 - z = x8437 - z = x8438 - z = x8439 - z = x8440 - z = x8441 - z = x8442 - z = x8443 - z = x8444 - z = x8445 - z = x8446 - z = x8447 - z = x8448 - z = x8449 - z = x8450 - z = x8451 - z = x8452 - z = x8453 - z = x8454 - z = x8455 - z = x8456 - z = x8457 - z = x8458 - z = x8459 - z = x8460 - z = x8461 - z = x8462 - z = x8463 - z = x8464 - z = x8465 - z = x8466 - z = x8467 - z = x8468 - z = x8469 - z = x8470 - z = x8471 - z = x8472 - z = x8473 - z = x8474 - z = x8475 - z = x8476 - z = x8477 - z = x8478 - z = x8479 - z = x8480 - z = x8481 - z = x8482 - z = x8483 - z = x8484 - z = x8485 - z = x8486 - z = x8487 - z = x8488 - z = x8489 - z = x8490 - z = x8491 - z = x8492 - z = x8493 - z = x8494 - z = x8495 - z = x8496 - z = x8497 - z = x8498 - z = x8499 - z = x8500 - z = x8501 - z = x8502 - z = x8503 - z = x8504 - z = x8505 - z = x8506 - z = x8507 - z = x8508 - z = x8509 - z = x8510 - z = x8511 - z = x8512 - z = x8513 - z = x8514 - z = x8515 - z = x8516 - z = x8517 - z = x8518 - z = x8519 - z = x8520 - z = x8521 - z = x8522 - z = x8523 - z = x8524 - z = x8525 - z = x8526 - z = x8527 - z = x8528 - z = x8529 - z = x8530 - z = x8531 - z = x8532 - z = x8533 - z = x8534 - z = x8535 - z = x8536 - z = x8537 - z = x8538 - z = x8539 - z = x8540 - z = x8541 - z = x8542 - z = x8543 - z = x8544 - z = x8545 - z = x8546 - z = x8547 - z = x8548 - z = x8549 - z = x8550 - z = x8551 - z = x8552 - z = x8553 - z = x8554 - z = x8555 - z = x8556 - z = x8557 - z = x8558 - z = x8559 - z = x8560 - z = x8561 - z = x8562 - z = x8563 - z = x8564 - z = x8565 - z = x8566 - z = x8567 - z = x8568 - z = x8569 - z = x8570 - z = x8571 - z = x8572 - z = x8573 - z = x8574 - z = x8575 - z = x8576 - z = x8577 - z = x8578 - z = x8579 - z = x8580 - z = x8581 - z = x8582 - z = x8583 - z = x8584 - z = x8585 - z = x8586 - z = x8587 - z = x8588 - z = x8589 - z = x8590 - z = x8591 - z = x8592 - z = x8593 - z = x8594 - z = x8595 - z = x8596 - z = x8597 - z = x8598 - z = x8599 - z = x8600 - z = x8601 - z = x8602 - z = x8603 - z = x8604 - z = x8605 - z = x8606 - z = x8607 - z = x8608 - z = x8609 - z = x8610 - z = x8611 - z = x8612 - z = x8613 - z = x8614 - z = x8615 - z = x8616 - z = x8617 - z = x8618 - z = x8619 - z = x8620 - z = x8621 - z = x8622 - z = x8623 - z = x8624 - z = x8625 - z = x8626 - z = x8627 - z = x8628 - z = x8629 - z = x8630 - z = x8631 - z = x8632 - z = x8633 - z = x8634 - z = x8635 - z = x8636 - z = x8637 - z = x8638 - z = x8639 - z = x8640 - z = x8641 - z = x8642 - z = x8643 - z = x8644 - z = x8645 - z = x8646 - z = x8647 - z = x8648 - z = x8649 - z = x8650 - z = x8651 - z = x8652 - z = x8653 - z = x8654 - z = x8655 - z = x8656 - z = x8657 - z = x8658 - z = x8659 - z = x8660 - z = x8661 - z = x8662 - z = x8663 - z = x8664 - z = x8665 - z = x8666 - z = x8667 - z = x8668 - z = x8669 - z = x8670 - z = x8671 - z = x8672 - z = x8673 - z = x8674 - z = x8675 - z = x8676 - z = x8677 - z = x8678 - z = x8679 - z = x8680 - z = x8681 - z = x8682 - z = x8683 - z = x8684 - z = x8685 - z = x8686 - z = x8687 - z = x8688 - z = x8689 - z = x8690 - z = x8691 - z = x8692 - z = x8693 - z = x8694 - z = x8695 - z = x8696 - z = x8697 - z = x8698 - z = x8699 - z = x8700 - z = x8701 - z = x8702 - z = x8703 - z = x8704 - z = x8705 - z = x8706 - z = x8707 - z = x8708 - z = x8709 - z = x8710 - z = x8711 - z = x8712 - z = x8713 - z = x8714 - z = x8715 - z = x8716 - z = x8717 - z = x8718 - z = x8719 - z = x8720 - z = x8721 - z = x8722 - z = x8723 - z = x8724 - z = x8725 - z = x8726 - z = x8727 - z = x8728 - z = x8729 - z = x8730 - z = x8731 - z = x8732 - z = x8733 - z = x8734 - z = x8735 - z = x8736 - z = x8737 - z = x8738 - z = x8739 - z = x8740 - z = x8741 - z = x8742 - z = x8743 - z = x8744 - z = x8745 - z = x8746 - z = x8747 - z = x8748 - z = x8749 - z = x8750 - z = x8751 - z = x8752 - z = x8753 - z = x8754 - z = x8755 - z = x8756 - z = x8757 - z = x8758 - z = x8759 - z = x8760 - z = x8761 - z = x8762 - z = x8763 - z = x8764 - z = x8765 - z = x8766 - z = x8767 - z = x8768 - z = x8769 - z = x8770 - z = x8771 - z = x8772 - z = x8773 - z = x8774 - z = x8775 - z = x8776 - z = x8777 - z = x8778 - z = x8779 - z = x8780 - z = x8781 - z = x8782 - z = x8783 - z = x8784 - z = x8785 - z = x8786 - z = x8787 - z = x8788 - z = x8789 - z = x8790 - z = x8791 - z = x8792 - z = x8793 - z = x8794 - z = x8795 - z = x8796 - z = x8797 - z = x8798 - z = x8799 - z = x8800 - z = x8801 - z = x8802 - z = x8803 - z = x8804 - z = x8805 - z = x8806 - z = x8807 - z = x8808 - z = x8809 - z = x8810 - z = x8811 - z = x8812 - z = x8813 - z = x8814 - z = x8815 - z = x8816 - z = x8817 - z = x8818 - z = x8819 - z = x8820 - z = x8821 - z = x8822 - z = x8823 - z = x8824 - z = x8825 - z = x8826 - z = x8827 - z = x8828 - z = x8829 - z = x8830 - z = x8831 - z = x8832 - z = x8833 - z = x8834 - z = x8835 - z = x8836 - z = x8837 - z = x8838 - z = x8839 - z = x8840 - z = x8841 - z = x8842 - z = x8843 - z = x8844 - z = x8845 - z = x8846 - z = x8847 - z = x8848 - z = x8849 - z = x8850 - z = x8851 - z = x8852 - z = x8853 - z = x8854 - z = x8855 - z = x8856 - z = x8857 - z = x8858 - z = x8859 - z = x8860 - z = x8861 - z = x8862 - z = x8863 - z = x8864 - z = x8865 - z = x8866 - z = x8867 - z = x8868 - z = x8869 - z = x8870 - z = x8871 - z = x8872 - z = x8873 - z = x8874 - z = x8875 - z = x8876 - z = x8877 - z = x8878 - z = x8879 - z = x8880 - z = x8881 - z = x8882 - z = x8883 - z = x8884 - z = x8885 - z = x8886 - z = x8887 - z = x8888 - z = x8889 - z = x8890 - z = x8891 - z = x8892 - z = x8893 - z = x8894 - z = x8895 - z = x8896 - z = x8897 - z = x8898 - z = x8899 - z = x8900 - z = x8901 - z = x8902 - z = x8903 - z = x8904 - z = x8905 - z = x8906 - z = x8907 - z = x8908 - z = x8909 - z = x8910 - z = x8911 - z = x8912 - z = x8913 - z = x8914 - z = x8915 - z = x8916 - z = x8917 - z = x8918 - z = x8919 - z = x8920 - z = x8921 - z = x8922 - z = x8923 - z = x8924 - z = x8925 - z = x8926 - z = x8927 - z = x8928 - z = x8929 - z = x8930 - z = x8931 - z = x8932 - z = x8933 - z = x8934 - z = x8935 - z = x8936 - z = x8937 - z = x8938 - z = x8939 - z = x8940 - z = x8941 - z = x8942 - z = x8943 - z = x8944 - z = x8945 - z = x8946 - z = x8947 - z = x8948 - z = x8949 - z = x8950 - z = x8951 - z = x8952 - z = x8953 - z = x8954 - z = x8955 - z = x8956 - z = x8957 - z = x8958 - z = x8959 - z = x8960 - z = x8961 - z = x8962 - z = x8963 - z = x8964 - z = x8965 - z = x8966 - z = x8967 - z = x8968 - z = x8969 - z = x8970 - z = x8971 - z = x8972 - z = x8973 - z = x8974 - z = x8975 - z = x8976 - z = x8977 - z = x8978 - z = x8979 - z = x8980 - z = x8981 - z = x8982 - z = x8983 - z = x8984 - z = x8985 - z = x8986 - z = x8987 - z = x8988 - z = x8989 - z = x8990 - z = x8991 - z = x8992 - z = x8993 - z = x8994 - z = x8995 - z = x8996 - z = x8997 - z = x8998 - z = x8999 - z = x9000 - z = x9001 - z = x9002 - z = x9003 - z = x9004 - z = x9005 - z = x9006 - z = x9007 - z = x9008 - z = x9009 - z = x9010 - z = x9011 - z = x9012 - z = x9013 - z = x9014 - z = x9015 - z = x9016 - z = x9017 - z = x9018 - z = x9019 - z = x9020 - z = x9021 - z = x9022 - z = x9023 - z = x9024 - z = x9025 - z = x9026 - z = x9027 - z = x9028 - z = x9029 - z = x9030 - z = x9031 - z = x9032 - z = x9033 - z = x9034 - z = x9035 - z = x9036 - z = x9037 - z = x9038 - z = x9039 - z = x9040 - z = x9041 - z = x9042 - z = x9043 - z = x9044 - z = x9045 - z = x9046 - z = x9047 - z = x9048 - z = x9049 - z = x9050 - z = x9051 - z = x9052 - z = x9053 - z = x9054 - z = x9055 - z = x9056 - z = x9057 - z = x9058 - z = x9059 - z = x9060 - z = x9061 - z = x9062 - z = x9063 - z = x9064 - z = x9065 - z = x9066 - z = x9067 - z = x9068 - z = x9069 - z = x9070 - z = x9071 - z = x9072 - z = x9073 - z = x9074 - z = x9075 - z = x9076 - z = x9077 - z = x9078 - z = x9079 - z = x9080 - z = x9081 - z = x9082 - z = x9083 - z = x9084 - z = x9085 - z = x9086 - z = x9087 - z = x9088 - z = x9089 - z = x9090 - z = x9091 - z = x9092 - z = x9093 - z = x9094 - z = x9095 - z = x9096 - z = x9097 - z = x9098 - z = x9099 - z = x9100 - z = x9101 - z = x9102 - z = x9103 - z = x9104 - z = x9105 - z = x9106 - z = x9107 - z = x9108 - z = x9109 - z = x9110 - z = x9111 - z = x9112 - z = x9113 - z = x9114 - z = x9115 - z = x9116 - z = x9117 - z = x9118 - z = x9119 - z = x9120 - z = x9121 - z = x9122 - z = x9123 - z = x9124 - z = x9125 - z = x9126 - z = x9127 - z = x9128 - z = x9129 - z = x9130 - z = x9131 - z = x9132 - z = x9133 - z = x9134 - z = x9135 - z = x9136 - z = x9137 - z = x9138 - z = x9139 - z = x9140 - z = x9141 - z = x9142 - z = x9143 - z = x9144 - z = x9145 - z = x9146 - z = x9147 - z = x9148 - z = x9149 - z = x9150 - z = x9151 - z = x9152 - z = x9153 - z = x9154 - z = x9155 - z = x9156 - z = x9157 - z = x9158 - z = x9159 - z = x9160 - z = x9161 - z = x9162 - z = x9163 - z = x9164 - z = x9165 - z = x9166 - z = x9167 - z = x9168 - z = x9169 - z = x9170 - z = x9171 - z = x9172 - z = x9173 - z = x9174 - z = x9175 - z = x9176 - z = x9177 - z = x9178 - z = x9179 - z = x9180 - z = x9181 - z = x9182 - z = x9183 - z = x9184 - z = x9185 - z = x9186 - z = x9187 - z = x9188 - z = x9189 - z = x9190 - z = x9191 - z = x9192 - z = x9193 - z = x9194 - z = x9195 - z = x9196 - z = x9197 - z = x9198 - z = x9199 - z = x9200 - z = x9201 - z = x9202 - z = x9203 - z = x9204 - z = x9205 - z = x9206 - z = x9207 - z = x9208 - z = x9209 - z = x9210 - z = x9211 - z = x9212 - z = x9213 - z = x9214 - z = x9215 - z = x9216 - z = x9217 - z = x9218 - z = x9219 - z = x9220 - z = x9221 - z = x9222 - z = x9223 - z = x9224 - z = x9225 - z = x9226 - z = x9227 - z = x9228 - z = x9229 - z = x9230 - z = x9231 - z = x9232 - z = x9233 - z = x9234 - z = x9235 - z = x9236 - z = x9237 - z = x9238 - z = x9239 - z = x9240 - z = x9241 - z = x9242 - z = x9243 - z = x9244 - z = x9245 - z = x9246 - z = x9247 - z = x9248 - z = x9249 - z = x9250 - z = x9251 - z = x9252 - z = x9253 - z = x9254 - z = x9255 - z = x9256 - z = x9257 - z = x9258 - z = x9259 - z = x9260 - z = x9261 - z = x9262 - z = x9263 - z = x9264 - z = x9265 - z = x9266 - z = x9267 - z = x9268 - z = x9269 - z = x9270 - z = x9271 - z = x9272 - z = x9273 - z = x9274 - z = x9275 - z = x9276 - z = x9277 - z = x9278 - z = x9279 - z = x9280 - z = x9281 - z = x9282 - z = x9283 - z = x9284 - z = x9285 - z = x9286 - z = x9287 - z = x9288 - z = x9289 - z = x9290 - z = x9291 - z = x9292 - z = x9293 - z = x9294 - z = x9295 - z = x9296 - z = x9297 - z = x9298 - z = x9299 - z = x9300 - z = x9301 - z = x9302 - z = x9303 - z = x9304 - z = x9305 - z = x9306 - z = x9307 - z = x9308 - z = x9309 - z = x9310 - z = x9311 - z = x9312 - z = x9313 - z = x9314 - z = x9315 - z = x9316 - z = x9317 - z = x9318 - z = x9319 - z = x9320 - z = x9321 - z = x9322 - z = x9323 - z = x9324 - z = x9325 - z = x9326 - z = x9327 - z = x9328 - z = x9329 - z = x9330 - z = x9331 - z = x9332 - z = x9333 - z = x9334 - z = x9335 - z = x9336 - z = x9337 - z = x9338 - z = x9339 - z = x9340 - z = x9341 - z = x9342 - z = x9343 - z = x9344 - z = x9345 - z = x9346 - z = x9347 - z = x9348 - z = x9349 - z = x9350 - z = x9351 - z = x9352 - z = x9353 - z = x9354 - z = x9355 - z = x9356 - z = x9357 - z = x9358 - z = x9359 - z = x9360 - z = x9361 - z = x9362 - z = x9363 - z = x9364 - z = x9365 - z = x9366 - z = x9367 - z = x9368 - z = x9369 - z = x9370 - z = x9371 - z = x9372 - z = x9373 - z = x9374 - z = x9375 - z = x9376 - z = x9377 - z = x9378 - z = x9379 - z = x9380 - z = x9381 - z = x9382 - z = x9383 - z = x9384 - z = x9385 - z = x9386 - z = x9387 - z = x9388 - z = x9389 - z = x9390 - z = x9391 - z = x9392 - z = x9393 - z = x9394 - z = x9395 - z = x9396 - z = x9397 - z = x9398 - z = x9399 - z = x9400 - z = x9401 - z = x9402 - z = x9403 - z = x9404 - z = x9405 - z = x9406 - z = x9407 - z = x9408 - z = x9409 - z = x9410 - z = x9411 - z = x9412 - z = x9413 - z = x9414 - z = x9415 - z = x9416 - z = x9417 - z = x9418 - z = x9419 - z = x9420 - z = x9421 - z = x9422 - z = x9423 - z = x9424 - z = x9425 - z = x9426 - z = x9427 - z = x9428 - z = x9429 - z = x9430 - z = x9431 - z = x9432 - z = x9433 - z = x9434 - z = x9435 - z = x9436 - z = x9437 - z = x9438 - z = x9439 - z = x9440 - z = x9441 - z = x9442 - z = x9443 - z = x9444 - z = x9445 - z = x9446 - z = x9447 - z = x9448 - z = x9449 - z = x9450 - z = x9451 - z = x9452 - z = x9453 - z = x9454 - z = x9455 - z = x9456 - z = x9457 - z = x9458 - z = x9459 - z = x9460 - z = x9461 - z = x9462 - z = x9463 - z = x9464 - z = x9465 - z = x9466 - z = x9467 - z = x9468 - z = x9469 - z = x9470 - z = x9471 - z = x9472 - z = x9473 - z = x9474 - z = x9475 - z = x9476 - z = x9477 - z = x9478 - z = x9479 - z = x9480 - z = x9481 - z = x9482 - z = x9483 - z = x9484 - z = x9485 - z = x9486 - z = x9487 - z = x9488 - z = x9489 - z = x9490 - z = x9491 - z = x9492 - z = x9493 - z = x9494 - z = x9495 - z = x9496 - z = x9497 - z = x9498 - z = x9499 - z = x9500 - z = x9501 - z = x9502 - z = x9503 - z = x9504 - z = x9505 - z = x9506 - z = x9507 - z = x9508 - z = x9509 - z = x9510 - z = x9511 - z = x9512 - z = x9513 - z = x9514 - z = x9515 - z = x9516 - z = x9517 - z = x9518 - z = x9519 - z = x9520 - z = x9521 - z = x9522 - z = x9523 - z = x9524 - z = x9525 - z = x9526 - z = x9527 - z = x9528 - z = x9529 - z = x9530 - z = x9531 - z = x9532 - z = x9533 - z = x9534 - z = x9535 - z = x9536 - z = x9537 - z = x9538 - z = x9539 - z = x9540 - z = x9541 - z = x9542 - z = x9543 - z = x9544 - z = x9545 - z = x9546 - z = x9547 - z = x9548 - z = x9549 - z = x9550 - z = x9551 - z = x9552 - z = x9553 - z = x9554 - z = x9555 - z = x9556 - z = x9557 - z = x9558 - z = x9559 - z = x9560 - z = x9561 - z = x9562 - z = x9563 - z = x9564 - z = x9565 - z = x9566 - z = x9567 - z = x9568 - z = x9569 - z = x9570 - z = x9571 - z = x9572 - z = x9573 - z = x9574 - z = x9575 - z = x9576 - z = x9577 - z = x9578 - z = x9579 - z = x9580 - z = x9581 - z = x9582 - z = x9583 - z = x9584 - z = x9585 - z = x9586 - z = x9587 - z = x9588 - z = x9589 - z = x9590 - z = x9591 - z = x9592 - z = x9593 - z = x9594 - z = x9595 - z = x9596 - z = x9597 - z = x9598 - z = x9599 - z = x9600 - z = x9601 - z = x9602 - z = x9603 - z = x9604 - z = x9605 - z = x9606 - z = x9607 - z = x9608 - z = x9609 - z = x9610 - z = x9611 - z = x9612 - z = x9613 - z = x9614 - z = x9615 - z = x9616 - z = x9617 - z = x9618 - z = x9619 - z = x9620 - z = x9621 - z = x9622 - z = x9623 - z = x9624 - z = x9625 - z = x9626 - z = x9627 - z = x9628 - z = x9629 - z = x9630 - z = x9631 - z = x9632 - z = x9633 - z = x9634 - z = x9635 - z = x9636 - z = x9637 - z = x9638 - z = x9639 - z = x9640 - z = x9641 - z = x9642 - z = x9643 - z = x9644 - z = x9645 - z = x9646 - z = x9647 - z = x9648 - z = x9649 - z = x9650 - z = x9651 - z = x9652 - z = x9653 - z = x9654 - z = x9655 - z = x9656 - z = x9657 - z = x9658 - z = x9659 - z = x9660 - z = x9661 - z = x9662 - z = x9663 - z = x9664 - z = x9665 - z = x9666 - z = x9667 - z = x9668 - z = x9669 - z = x9670 - z = x9671 - z = x9672 - z = x9673 - z = x9674 - z = x9675 - z = x9676 - z = x9677 - z = x9678 - z = x9679 - z = x9680 - z = x9681 - z = x9682 - z = x9683 - z = x9684 - z = x9685 - z = x9686 - z = x9687 - z = x9688 - z = x9689 - z = x9690 - z = x9691 - z = x9692 - z = x9693 - z = x9694 - z = x9695 - z = x9696 - z = x9697 - z = x9698 - z = x9699 - z = x9700 - z = x9701 - z = x9702 - z = x9703 - z = x9704 - z = x9705 - z = x9706 - z = x9707 - z = x9708 - z = x9709 - z = x9710 - z = x9711 - z = x9712 - z = x9713 - z = x9714 - z = x9715 - z = x9716 - z = x9717 - z = x9718 - z = x9719 - z = x9720 - z = x9721 - z = x9722 - z = x9723 - z = x9724 - z = x9725 - z = x9726 - z = x9727 - z = x9728 - z = x9729 - z = x9730 - z = x9731 - z = x9732 - z = x9733 - z = x9734 - z = x9735 - z = x9736 - z = x9737 - z = x9738 - z = x9739 - z = x9740 - z = x9741 - z = x9742 - z = x9743 - z = x9744 - z = x9745 - z = x9746 - z = x9747 - z = x9748 - z = x9749 - z = x9750 - z = x9751 - z = x9752 - z = x9753 - z = x9754 - z = x9755 - z = x9756 - z = x9757 - z = x9758 - z = x9759 - z = x9760 - z = x9761 - z = x9762 - z = x9763 - z = x9764 - z = x9765 - z = x9766 - z = x9767 - z = x9768 - z = x9769 - z = x9770 - z = x9771 - z = x9772 - z = x9773 - z = x9774 - z = x9775 - z = x9776 - z = x9777 - z = x9778 - z = x9779 - z = x9780 - z = x9781 - z = x9782 - z = x9783 - z = x9784 - z = x9785 - z = x9786 - z = x9787 - z = x9788 - z = x9789 - z = x9790 - z = x9791 - z = x9792 - z = x9793 - z = x9794 - z = x9795 - z = x9796 - z = x9797 - z = x9798 - z = x9799 - z = x9800 - z = x9801 - z = x9802 - z = x9803 - z = x9804 - z = x9805 - z = x9806 - z = x9807 - z = x9808 - z = x9809 - z = x9810 - z = x9811 - z = x9812 - z = x9813 - z = x9814 - z = x9815 - z = x9816 - z = x9817 - z = x9818 - z = x9819 - z = x9820 - z = x9821 - z = x9822 - z = x9823 - z = x9824 - z = x9825 - z = x9826 - z = x9827 - z = x9828 - z = x9829 - z = x9830 - z = x9831 - z = x9832 - z = x9833 - z = x9834 - z = x9835 - z = x9836 - z = x9837 - z = x9838 - z = x9839 - z = x9840 - z = x9841 - z = x9842 - z = x9843 - z = x9844 - z = x9845 - z = x9846 - z = x9847 - z = x9848 - z = x9849 - z = x9850 - z = x9851 - z = x9852 - z = x9853 - z = x9854 - z = x9855 - z = x9856 - z = x9857 - z = x9858 - z = x9859 - z = x9860 - z = x9861 - z = x9862 - z = x9863 - z = x9864 - z = x9865 - z = x9866 - z = x9867 - z = x9868 - z = x9869 - z = x9870 - z = x9871 - z = x9872 - z = x9873 - z = x9874 - z = x9875 - z = x9876 - z = x9877 - z = x9878 - z = x9879 - z = x9880 - z = x9881 - z = x9882 - z = x9883 - z = x9884 - z = x9885 - z = x9886 - z = x9887 - z = x9888 - z = x9889 - z = x9890 - z = x9891 - z = x9892 - z = x9893 - z = x9894 - z = x9895 - z = x9896 - z = x9897 - z = x9898 - z = x9899 - z = x9900 - z = x9901 - z = x9902 - z = x9903 - z = x9904 - z = x9905 - z = x9906 - z = x9907 - z = x9908 - z = x9909 - z = x9910 - z = x9911 - z = x9912 - z = x9913 - z = x9914 - z = x9915 - z = x9916 - z = x9917 - z = x9918 - z = x9919 - z = x9920 - z = x9921 - z = x9922 - z = x9923 - z = x9924 - z = x9925 - z = x9926 - z = x9927 - z = x9928 - z = x9929 - z = x9930 - z = x9931 - z = x9932 - z = x9933 - z = x9934 - z = x9935 - z = x9936 - z = x9937 - z = x9938 - z = x9939 - z = x9940 - z = x9941 - z = x9942 - z = x9943 - z = x9944 - z = x9945 - z = x9946 - z = x9947 - z = x9948 - z = x9949 - z = x9950 - z = x9951 - z = x9952 - z = x9953 - z = x9954 - z = x9955 - z = x9956 - z = x9957 - z = x9958 - z = x9959 - z = x9960 - z = x9961 - z = x9962 - z = x9963 - z = x9964 - z = x9965 - z = x9966 - z = x9967 - z = x9968 - z = x9969 - z = x9970 - z = x9971 - z = x9972 - z = x9973 - z = x9974 - z = x9975 - z = x9976 - z = x9977 - z = x9978 - z = x9979 - z = x9980 - z = x9981 - z = x9982 - z = x9983 - z = x9984 - z = x9985 - z = x9986 - z = x9987 - z = x9988 - z = x9989 - z = x9990 - z = x9991 - z = x9992 - z = x9993 - z = x9994 - z = x9995 - z = x9996 - z = x9997 - z = x9998 - z = x9999 - z = x10000 - z = x10001 - z = x10002 - z = x10003 - z = x10004 - z = x10005 - z = x10006 - z = x10007 - z = x10008 - z = x10009 - z = x10010 - z = x10011 - z = x10012 - z = x10013 - z = x10014 - z = x10015 - z = x10016 - z = x10017 - z = x10018 - z = x10019 - z = x10020 - z = x10021 - z = x10022 - z = x10023 - z = x10024 - z = x10025 - z = x10026 - z = x10027 - z = x10028 - z = x10029 - z = x10030 - z = x10031 - z = x10032 - z = x10033 - z = x10034 - z = x10035 - z = x10036 - z = x10037 - z = x10038 - z = x10039 - z = x10040 - z = x10041 - z = x10042 - z = x10043 - z = x10044 - z = x10045 - z = x10046 - z = x10047 - z = x10048 - z = x10049 - z = x10050 - z = x10051 - z = x10052 - z = x10053 - z = x10054 - z = x10055 - z = x10056 - z = x10057 - z = x10058 - z = x10059 - z = x10060 - z = x10061 - z = x10062 - z = x10063 - z = x10064 - z = x10065 - z = x10066 - z = x10067 - z = x10068 - z = x10069 - z = x10070 - z = x10071 - z = x10072 - z = x10073 - z = x10074 - z = x10075 - z = x10076 - z = x10077 - z = x10078 - z = x10079 - z = x10080 - z = x10081 - z = x10082 - z = x10083 - z = x10084 - z = x10085 - z = x10086 - z = x10087 - z = x10088 - z = x10089 - z = x10090 - z = x10091 - z = x10092 - z = x10093 - z = x10094 - z = x10095 - z = x10096 - z = x10097 - z = x10098 - z = x10099 - z = x10100 - z = x10101 - z = x10102 - z = x10103 - z = x10104 - z = x10105 - z = x10106 - z = x10107 - z = x10108 - z = x10109 - z = x10110 - z = x10111 - z = x10112 - z = x10113 - z = x10114 - z = x10115 - z = x10116 - z = x10117 - z = x10118 - z = x10119 - z = x10120 - z = x10121 - z = x10122 - z = x10123 - z = x10124 - z = x10125 - z = x10126 - z = x10127 - z = x10128 - z = x10129 - z = x10130 - z = x10131 - z = x10132 - z = x10133 - z = x10134 - z = x10135 - z = x10136 - z = x10137 - z = x10138 - z = x10139 - z = x10140 - z = x10141 - z = x10142 - z = x10143 - z = x10144 - z = x10145 - z = x10146 - z = x10147 - z = x10148 - z = x10149 - z = x10150 - z = x10151 - z = x10152 - z = x10153 - z = x10154 - z = x10155 - z = x10156 - z = x10157 - z = x10158 - z = x10159 - z = x10160 - z = x10161 - z = x10162 - z = x10163 - z = x10164 - z = x10165 - z = x10166 - z = x10167 - z = x10168 - z = x10169 - z = x10170 - z = x10171 - z = x10172 - z = x10173 - z = x10174 - z = x10175 - z = x10176 - z = x10177 - z = x10178 - z = x10179 - z = x10180 - z = x10181 - z = x10182 - z = x10183 - z = x10184 - z = x10185 - z = x10186 - z = x10187 - z = x10188 - z = x10189 - z = x10190 - z = x10191 - z = x10192 - z = x10193 - z = x10194 - z = x10195 - z = x10196 - z = x10197 - z = x10198 - z = x10199 - z = x10200 - z = x10201 - z = x10202 - z = x10203 - z = x10204 - z = x10205 - z = x10206 - z = x10207 - z = x10208 - z = x10209 - z = x10210 - z = x10211 - z = x10212 - z = x10213 - z = x10214 - z = x10215 - z = x10216 - z = x10217 - z = x10218 - z = x10219 - z = x10220 - z = x10221 - z = x10222 - z = x10223 - z = x10224 - z = x10225 - z = x10226 - z = x10227 - z = x10228 - z = x10229 - z = x10230 - z = x10231 - z = x10232 - z = x10233 - z = x10234 - z = x10235 - z = x10236 - z = x10237 - z = x10238 - z = x10239 - z = x10240 - z = x10241 - z = x10242 - z = x10243 - z = x10244 - z = x10245 - z = x10246 - z = x10247 - z = x10248 - z = x10249 - z = x10250 - z = x10251 - z = x10252 - z = x10253 - z = x10254 - z = x10255 - z = x10256 - z = x10257 - z = x10258 - z = x10259 - z = x10260 - z = x10261 - z = x10262 - z = x10263 - z = x10264 - z = x10265 - z = x10266 - z = x10267 - z = x10268 - z = x10269 - z = x10270 - z = x10271 - z = x10272 - z = x10273 - z = x10274 - z = x10275 - z = x10276 - z = x10277 - z = x10278 - z = x10279 - z = x10280 - z = x10281 - z = x10282 - z = x10283 - z = x10284 - z = x10285 - z = x10286 - z = x10287 - z = x10288 - z = x10289 - z = x10290 - z = x10291 - z = x10292 - z = x10293 - z = x10294 - z = x10295 - z = x10296 - z = x10297 - z = x10298 - z = x10299 - z = x10300 - z = x10301 - z = x10302 - z = x10303 - z = x10304 - z = x10305 - z = x10306 - z = x10307 - z = x10308 - z = x10309 - z = x10310 - z = x10311 - z = x10312 - z = x10313 - z = x10314 - z = x10315 - z = x10316 - z = x10317 - z = x10318 - z = x10319 - z = x10320 - z = x10321 - z = x10322 - z = x10323 - z = x10324 - z = x10325 - z = x10326 - z = x10327 - z = x10328 - z = x10329 - z = x10330 - z = x10331 - z = x10332 - z = x10333 - z = x10334 - z = x10335 - z = x10336 - z = x10337 - z = x10338 - z = x10339 - z = x10340 - z = x10341 - z = x10342 - z = x10343 - z = x10344 - z = x10345 - z = x10346 - z = x10347 - z = x10348 - z = x10349 - z = x10350 - z = x10351 - z = x10352 - z = x10353 - z = x10354 - z = x10355 - z = x10356 - z = x10357 - z = x10358 - z = x10359 - z = x10360 - z = x10361 - z = x10362 - z = x10363 - z = x10364 - z = x10365 - z = x10366 - z = x10367 - z = x10368 - z = x10369 - z = x10370 - z = x10371 - z = x10372 - z = x10373 - z = x10374 - z = x10375 - z = x10376 - z = x10377 - z = x10378 - z = x10379 - z = x10380 - z = x10381 - z = x10382 - z = x10383 - z = x10384 - z = x10385 - z = x10386 - z = x10387 - z = x10388 - z = x10389 - z = x10390 - z = x10391 - z = x10392 - z = x10393 - z = x10394 - z = x10395 - z = x10396 - z = x10397 - z = x10398 - z = x10399 - z = x10400 - z = x10401 - z = x10402 - z = x10403 - z = x10404 - z = x10405 - z = x10406 - z = x10407 - z = x10408 - z = x10409 - z = x10410 - z = x10411 - z = x10412 - z = x10413 - z = x10414 - z = x10415 - z = x10416 - z = x10417 - z = x10418 - z = x10419 - z = x10420 - z = x10421 - z = x10422 - z = x10423 - z = x10424 - z = x10425 - z = x10426 - z = x10427 - z = x10428 - z = x10429 - z = x10430 - z = x10431 - z = x10432 - z = x10433 - z = x10434 - z = x10435 - z = x10436 - z = x10437 - z = x10438 - z = x10439 - z = x10440 - z = x10441 - z = x10442 - z = x10443 - z = x10444 - z = x10445 - z = x10446 - z = x10447 - z = x10448 - z = x10449 - z = x10450 - z = x10451 - z = x10452 - z = x10453 - z = x10454 - z = x10455 - z = x10456 - z = x10457 - z = x10458 - z = x10459 - z = x10460 - z = x10461 - z = x10462 - z = x10463 - z = x10464 - z = x10465 - z = x10466 - z = x10467 - z = x10468 - z = x10469 - z = x10470 - z = x10471 - z = x10472 - z = x10473 - z = x10474 - z = x10475 - z = x10476 - z = x10477 - z = x10478 - z = x10479 - z = x10480 - z = x10481 - z = x10482 - z = x10483 - z = x10484 - z = x10485 - z = x10486 - z = x10487 - z = x10488 - z = x10489 - z = x10490 - z = x10491 - z = x10492 - z = x10493 - z = x10494 - z = x10495 - z = x10496 - z = x10497 - z = x10498 - z = x10499 - z = x10500 - z = x10501 - z = x10502 - z = x10503 - z = x10504 - z = x10505 - z = x10506 - z = x10507 - z = x10508 - z = x10509 - z = x10510 - z = x10511 - z = x10512 - z = x10513 - z = x10514 - z = x10515 - z = x10516 - z = x10517 - z = x10518 - z = x10519 - z = x10520 - z = x10521 - z = x10522 - z = x10523 - z = x10524 - z = x10525 - z = x10526 - z = x10527 - z = x10528 - z = x10529 - z = x10530 - z = x10531 - z = x10532 - z = x10533 - z = x10534 - z = x10535 - z = x10536 - z = x10537 - z = x10538 - z = x10539 - z = x10540 - z = x10541 - z = x10542 - z = x10543 - z = x10544 - z = x10545 - z = x10546 - z = x10547 - z = x10548 - z = x10549 - z = x10550 - z = x10551 - z = x10552 - z = x10553 - z = x10554 - z = x10555 - z = x10556 - z = x10557 - z = x10558 - z = x10559 - z = x10560 - z = x10561 - z = x10562 - z = x10563 - z = x10564 - z = x10565 - z = x10566 - z = x10567 - z = x10568 - z = x10569 - z = x10570 - z = x10571 - z = x10572 - z = x10573 - z = x10574 - z = x10575 - z = x10576 - z = x10577 - z = x10578 - z = x10579 - z = x10580 - z = x10581 - z = x10582 - z = x10583 - z = x10584 - z = x10585 - z = x10586 - z = x10587 - z = x10588 - z = x10589 - z = x10590 - z = x10591 - z = x10592 - z = x10593 - z = x10594 - z = x10595 - z = x10596 - z = x10597 - z = x10598 - z = x10599 - z = x10600 - z = x10601 - z = x10602 - z = x10603 - z = x10604 - z = x10605 - z = x10606 - z = x10607 - z = x10608 - z = x10609 - z = x10610 - z = x10611 - z = x10612 - z = x10613 - z = x10614 - z = x10615 - z = x10616 - z = x10617 - z = x10618 - z = x10619 - z = x10620 - z = x10621 - z = x10622 - z = x10623 - z = x10624 - z = x10625 - z = x10626 - z = x10627 - z = x10628 - z = x10629 - z = x10630 - z = x10631 - z = x10632 - z = x10633 - z = x10634 - z = x10635 - z = x10636 - z = x10637 - z = x10638 - z = x10639 - z = x10640 - z = x10641 - z = x10642 - z = x10643 - z = x10644 - z = x10645 - z = x10646 - z = x10647 - z = x10648 - z = x10649 - z = x10650 - z = x10651 - z = x10652 - z = x10653 - z = x10654 - z = x10655 - z = x10656 - z = x10657 - z = x10658 - z = x10659 - z = x10660 - z = x10661 - z = x10662 - z = x10663 - z = x10664 - z = x10665 - z = x10666 - z = x10667 - z = x10668 - z = x10669 - z = x10670 - z = x10671 - z = x10672 - z = x10673 - z = x10674 - z = x10675 - z = x10676 - z = x10677 - z = x10678 - z = x10679 - z = x10680 - z = x10681 - z = x10682 - z = x10683 - z = x10684 - z = x10685 - z = x10686 - z = x10687 - z = x10688 - z = x10689 - z = x10690 - z = x10691 - z = x10692 - z = x10693 - z = x10694 - z = x10695 - z = x10696 - z = x10697 - z = x10698 - z = x10699 - z = x10700 - z = x10701 - z = x10702 - z = x10703 - z = x10704 - z = x10705 - z = x10706 - z = x10707 - z = x10708 - z = x10709 - z = x10710 - z = x10711 - z = x10712 - z = x10713 - z = x10714 - z = x10715 - z = x10716 - z = x10717 - z = x10718 - z = x10719 - z = x10720 - z = x10721 - z = x10722 - z = x10723 - z = x10724 - z = x10725 - z = x10726 - z = x10727 - z = x10728 - z = x10729 - z = x10730 - z = x10731 - z = x10732 - z = x10733 - z = x10734 - z = x10735 - z = x10736 - z = x10737 - z = x10738 - z = x10739 - z = x10740 - z = x10741 - z = x10742 - z = x10743 - z = x10744 - z = x10745 - z = x10746 - z = x10747 - z = x10748 - z = x10749 - z = x10750 - z = x10751 - z = x10752 - z = x10753 - z = x10754 - z = x10755 - z = x10756 - z = x10757 - z = x10758 - z = x10759 - z = x10760 - z = x10761 - z = x10762 - z = x10763 - z = x10764 - z = x10765 - z = x10766 - z = x10767 - z = x10768 - z = x10769 - z = x10770 - z = x10771 - z = x10772 - z = x10773 - z = x10774 - z = x10775 - z = x10776 - z = x10777 - z = x10778 - z = x10779 - z = x10780 - z = x10781 - z = x10782 - z = x10783 - z = x10784 - z = x10785 - z = x10786 - z = x10787 - z = x10788 - z = x10789 - z = x10790 - z = x10791 - z = x10792 - z = x10793 - z = x10794 - z = x10795 - z = x10796 - z = x10797 - z = x10798 - z = x10799 - z = x10800 - z = x10801 - z = x10802 - z = x10803 - z = x10804 - z = x10805 - z = x10806 - z = x10807 - z = x10808 - z = x10809 - z = x10810 - z = x10811 - z = x10812 - z = x10813 - z = x10814 - z = x10815 - z = x10816 - z = x10817 - z = x10818 - z = x10819 - z = x10820 - z = x10821 - z = x10822 - z = x10823 - z = x10824 - z = x10825 - z = x10826 - z = x10827 - z = x10828 - z = x10829 - z = x10830 - z = x10831 - z = x10832 - z = x10833 - z = x10834 - z = x10835 - z = x10836 - z = x10837 - z = x10838 - z = x10839 - z = x10840 - z = x10841 - z = x10842 - z = x10843 - z = x10844 - z = x10845 - z = x10846 - z = x10847 - z = x10848 - z = x10849 - z = x10850 - z = x10851 - z = x10852 - z = x10853 - z = x10854 - z = x10855 - z = x10856 - z = x10857 - z = x10858 - z = x10859 - z = x10860 - z = x10861 - z = x10862 - z = x10863 - z = x10864 - z = x10865 - z = x10866 - z = x10867 - z = x10868 - z = x10869 - z = x10870 - z = x10871 - z = x10872 - z = x10873 - z = x10874 - z = x10875 - z = x10876 - z = x10877 - z = x10878 - z = x10879 - z = x10880 - z = x10881 - z = x10882 - z = x10883 - z = x10884 - z = x10885 - z = x10886 - z = x10887 - z = x10888 - z = x10889 - z = x10890 - z = x10891 - z = x10892 - z = x10893 - z = x10894 - z = x10895 - z = x10896 - z = x10897 - z = x10898 - z = x10899 - z = x10900 - z = x10901 - z = x10902 - z = x10903 - z = x10904 - z = x10905 - z = x10906 - z = x10907 - z = x10908 - z = x10909 - z = x10910 - z = x10911 - z = x10912 - z = x10913 - z = x10914 - z = x10915 - z = x10916 - z = x10917 - z = x10918 - z = x10919 - z = x10920 - z = x10921 - z = x10922 - z = x10923 - z = x10924 - z = x10925 - z = x10926 - z = x10927 - z = x10928 - z = x10929 - z = x10930 - z = x10931 - z = x10932 - z = x10933 - z = x10934 - z = x10935 - z = x10936 - z = x10937 - z = x10938 - z = x10939 - z = x10940 - z = x10941 - z = x10942 - z = x10943 - z = x10944 - z = x10945 - z = x10946 - z = x10947 - z = x10948 - z = x10949 - z = x10950 - z = x10951 - z = x10952 - z = x10953 - z = x10954 - z = x10955 - z = x10956 - z = x10957 - z = x10958 - z = x10959 - z = x10960 - z = x10961 - z = x10962 - z = x10963 - z = x10964 - z = x10965 - z = x10966 - z = x10967 - z = x10968 - z = x10969 - z = x10970 - z = x10971 - z = x10972 - z = x10973 - z = x10974 - z = x10975 - z = x10976 - z = x10977 - z = x10978 - z = x10979 - z = x10980 - z = x10981 - z = x10982 - z = x10983 - z = x10984 - z = x10985 - z = x10986 - z = x10987 - z = x10988 - z = x10989 - z = x10990 - z = x10991 - z = x10992 - z = x10993 - z = x10994 - z = x10995 - z = x10996 - z = x10997 - z = x10998 - z = x10999 - z = x11000 - z = x11001 - z = x11002 - z = x11003 - z = x11004 - z = x11005 - z = x11006 - z = x11007 - z = x11008 - z = x11009 - z = x11010 - z = x11011 - z = x11012 - z = x11013 - z = x11014 - z = x11015 - z = x11016 - z = x11017 - z = x11018 - z = x11019 - z = x11020 - z = x11021 - z = x11022 - z = x11023 - z = x11024 - z = x11025 - z = x11026 - z = x11027 - z = x11028 - z = x11029 - z = x11030 - z = x11031 - z = x11032 - z = x11033 - z = x11034 - z = x11035 - z = x11036 - z = x11037 - z = x11038 - z = x11039 - z = x11040 - z = x11041 - z = x11042 - z = x11043 - z = x11044 - z = x11045 - z = x11046 - z = x11047 - z = x11048 - z = x11049 - z = x11050 - z = x11051 - z = x11052 - z = x11053 - z = x11054 - z = x11055 - z = x11056 - z = x11057 - z = x11058 - z = x11059 - z = x11060 - z = x11061 - z = x11062 - z = x11063 - z = x11064 - z = x11065 - z = x11066 - z = x11067 - z = x11068 - z = x11069 - z = x11070 - z = x11071 - z = x11072 - z = x11073 - z = x11074 - z = x11075 - z = x11076 - z = x11077 - z = x11078 - z = x11079 - z = x11080 - z = x11081 - z = x11082 - z = x11083 - z = x11084 - z = x11085 - z = x11086 - z = x11087 - z = x11088 - z = x11089 - z = x11090 - z = x11091 - z = x11092 - z = x11093 - z = x11094 - z = x11095 - z = x11096 - z = x11097 - z = x11098 - z = x11099 - z = x11100 - z = x11101 - z = x11102 - z = x11103 - z = x11104 - z = x11105 - z = x11106 - z = x11107 - z = x11108 - z = x11109 - z = x11110 - z = x11111 - z = x11112 - z = x11113 - z = x11114 - z = x11115 - z = x11116 - z = x11117 - z = x11118 - z = x11119 - z = x11120 - z = x11121 - z = x11122 - z = x11123 - z = x11124 - z = x11125 - z = x11126 - z = x11127 - z = x11128 - z = x11129 - z = x11130 - z = x11131 - z = x11132 - z = x11133 - z = x11134 - z = x11135 - z = x11136 - z = x11137 - z = x11138 - z = x11139 - z = x11140 - z = x11141 - z = x11142 - z = x11143 - z = x11144 - z = x11145 - z = x11146 - z = x11147 - z = x11148 - z = x11149 - z = x11150 - z = x11151 - z = x11152 - z = x11153 - z = x11154 - z = x11155 - z = x11156 - z = x11157 - z = x11158 - z = x11159 - z = x11160 - z = x11161 - z = x11162 - z = x11163 - z = x11164 - z = x11165 - z = x11166 - z = x11167 - z = x11168 - z = x11169 - z = x11170 - z = x11171 - z = x11172 - z = x11173 - z = x11174 - z = x11175 - z = x11176 - z = x11177 - z = x11178 - z = x11179 - z = x11180 - z = x11181 - z = x11182 - z = x11183 - z = x11184 - z = x11185 - z = x11186 - z = x11187 - z = x11188 - z = x11189 - z = x11190 - z = x11191 - z = x11192 - z = x11193 - z = x11194 - z = x11195 - z = x11196 - z = x11197 - z = x11198 - z = x11199 - z = x11200 - z = x11201 - z = x11202 - z = x11203 - z = x11204 - z = x11205 - z = x11206 - z = x11207 - z = x11208 - z = x11209 - z = x11210 - z = x11211 - z = x11212 - z = x11213 - z = x11214 - z = x11215 - z = x11216 - z = x11217 - z = x11218 - z = x11219 - z = x11220 - z = x11221 - z = x11222 - z = x11223 - z = x11224 - z = x11225 - z = x11226 - z = x11227 - z = x11228 - z = x11229 - z = x11230 - z = x11231 - z = x11232 - z = x11233 - z = x11234 - z = x11235 - z = x11236 - z = x11237 - z = x11238 - z = x11239 - z = x11240 - z = x11241 - z = x11242 - z = x11243 - z = x11244 - z = x11245 - z = x11246 - z = x11247 - z = x11248 - z = x11249 - z = x11250 - z = x11251 - z = x11252 - z = x11253 - z = x11254 - z = x11255 - z = x11256 - z = x11257 - z = x11258 - z = x11259 - z = x11260 - z = x11261 - z = x11262 - z = x11263 - z = x11264 - z = x11265 - z = x11266 - z = x11267 - z = x11268 - z = x11269 - z = x11270 - z = x11271 - z = x11272 - z = x11273 - z = x11274 - z = x11275 - z = x11276 - z = x11277 - z = x11278 - z = x11279 - z = x11280 - z = x11281 - z = x11282 - z = x11283 - z = x11284 - z = x11285 - z = x11286 - z = x11287 - z = x11288 - z = x11289 - z = x11290 - z = x11291 - z = x11292 - z = x11293 - z = x11294 - z = x11295 - z = x11296 - z = x11297 - z = x11298 - z = x11299 - z = x11300 - z = x11301 - z = x11302 - z = x11303 - z = x11304 - z = x11305 - z = x11306 - z = x11307 - z = x11308 - z = x11309 - z = x11310 - z = x11311 - z = x11312 - z = x11313 - z = x11314 - z = x11315 - z = x11316 - z = x11317 - z = x11318 - z = x11319 - z = x11320 - z = x11321 - z = x11322 - z = x11323 - z = x11324 - z = x11325 - z = x11326 - z = x11327 - z = x11328 - z = x11329 - z = x11330 - z = x11331 - z = x11332 - z = x11333 - z = x11334 - z = x11335 - z = x11336 - z = x11337 - z = x11338 - z = x11339 - z = x11340 - z = x11341 - z = x11342 - z = x11343 - z = x11344 - z = x11345 - z = x11346 - z = x11347 - z = x11348 - z = x11349 - z = x11350 - z = x11351 - z = x11352 - z = x11353 - z = x11354 - z = x11355 - z = x11356 - z = x11357 - z = x11358 - z = x11359 - z = x11360 - z = x11361 - z = x11362 - z = x11363 - z = x11364 - z = x11365 - z = x11366 - z = x11367 - z = x11368 - z = x11369 - z = x11370 - z = x11371 - z = x11372 - z = x11373 - z = x11374 - z = x11375 - z = x11376 - z = x11377 - z = x11378 - z = x11379 - z = x11380 - z = x11381 - z = x11382 - z = x11383 - z = x11384 - z = x11385 - z = x11386 - z = x11387 - z = x11388 - z = x11389 - z = x11390 - z = x11391 - z = x11392 - z = x11393 - z = x11394 - z = x11395 - z = x11396 - z = x11397 - z = x11398 - z = x11399 - z = x11400 - z = x11401 - z = x11402 - z = x11403 - z = x11404 - z = x11405 - z = x11406 - z = x11407 - z = x11408 - z = x11409 - z = x11410 - z = x11411 - z = x11412 - z = x11413 - z = x11414 - z = x11415 - z = x11416 - z = x11417 - z = x11418 - z = x11419 - z = x11420 - z = x11421 - z = x11422 - z = x11423 - z = x11424 - z = x11425 - z = x11426 - z = x11427 - z = x11428 - z = x11429 - z = x11430 - z = x11431 - z = x11432 - z = x11433 - z = x11434 - z = x11435 - z = x11436 - z = x11437 - z = x11438 - z = x11439 - z = x11440 - z = x11441 - z = x11442 - z = x11443 - z = x11444 - z = x11445 - z = x11446 - z = x11447 - z = x11448 - z = x11449 - z = x11450 - z = x11451 - z = x11452 - z = x11453 - z = x11454 - z = x11455 - z = x11456 - z = x11457 - z = x11458 - z = x11459 - z = x11460 - z = x11461 - z = x11462 - z = x11463 - z = x11464 - z = x11465 - z = x11466 - z = x11467 - z = x11468 - z = x11469 - z = x11470 - z = x11471 - z = x11472 - z = x11473 - z = x11474 - z = x11475 - z = x11476 - z = x11477 - z = x11478 - z = x11479 - z = x11480 - z = x11481 - z = x11482 - z = x11483 - z = x11484 - z = x11485 - z = x11486 - z = x11487 - z = x11488 - z = x11489 - z = x11490 - z = x11491 - z = x11492 - z = x11493 - z = x11494 - z = x11495 - z = x11496 - z = x11497 - z = x11498 - z = x11499 - z = x11500 - z = x11501 - z = x11502 - z = x11503 - z = x11504 - z = x11505 - z = x11506 - z = x11507 - z = x11508 - z = x11509 - z = x11510 - z = x11511 - z = x11512 - z = x11513 - z = x11514 - z = x11515 - z = x11516 - z = x11517 - z = x11518 - z = x11519 - z = x11520 - z = x11521 - z = x11522 - z = x11523 - z = x11524 - z = x11525 - z = x11526 - z = x11527 - z = x11528 - z = x11529 - z = x11530 - z = x11531 - z = x11532 - z = x11533 - z = x11534 - z = x11535 - z = x11536 - z = x11537 - z = x11538 - z = x11539 - z = x11540 - z = x11541 - z = x11542 - z = x11543 - z = x11544 - z = x11545 - z = x11546 - z = x11547 - z = x11548 - z = x11549 - z = x11550 - z = x11551 - z = x11552 - z = x11553 - z = x11554 - z = x11555 - z = x11556 - z = x11557 - z = x11558 - z = x11559 - z = x11560 - z = x11561 - z = x11562 - z = x11563 - z = x11564 - z = x11565 - z = x11566 - z = x11567 - z = x11568 - z = x11569 - z = x11570 - z = x11571 - z = x11572 - z = x11573 - z = x11574 - z = x11575 - z = x11576 - z = x11577 - z = x11578 - z = x11579 - z = x11580 - z = x11581 - z = x11582 - z = x11583 - z = x11584 - z = x11585 - z = x11586 - z = x11587 - z = x11588 - z = x11589 - z = x11590 - z = x11591 - z = x11592 - z = x11593 - z = x11594 - z = x11595 - z = x11596 - z = x11597 - z = x11598 - z = x11599 - z = x11600 - z = x11601 - z = x11602 - z = x11603 - z = x11604 - z = x11605 - z = x11606 - z = x11607 - z = x11608 - z = x11609 - z = x11610 - z = x11611 - z = x11612 - z = x11613 - z = x11614 - z = x11615 - z = x11616 - z = x11617 - z = x11618 - z = x11619 - z = x11620 - z = x11621 - z = x11622 - z = x11623 - z = x11624 - z = x11625 - z = x11626 - z = x11627 - z = x11628 - z = x11629 - z = x11630 - z = x11631 - z = x11632 - z = x11633 - z = x11634 - z = x11635 - z = x11636 - z = x11637 - z = x11638 - z = x11639 - z = x11640 - z = x11641 - z = x11642 - z = x11643 - z = x11644 - z = x11645 - z = x11646 - z = x11647 - z = x11648 - z = x11649 - z = x11650 - z = x11651 - z = x11652 - z = x11653 - z = x11654 - z = x11655 - z = x11656 - z = x11657 - z = x11658 - z = x11659 - z = x11660 - z = x11661 - z = x11662 - z = x11663 - z = x11664 - z = x11665 - z = x11666 - z = x11667 - z = x11668 - z = x11669 - z = x11670 - z = x11671 - z = x11672 - z = x11673 - z = x11674 - z = x11675 - z = x11676 - z = x11677 - z = x11678 - z = x11679 - z = x11680 - z = x11681 - z = x11682 - z = x11683 - z = x11684 - z = x11685 - z = x11686 - z = x11687 - z = x11688 - z = x11689 - z = x11690 - z = x11691 - z = x11692 - z = x11693 - z = x11694 - z = x11695 - z = x11696 - z = x11697 - z = x11698 - z = x11699 - z = x11700 - z = x11701 - z = x11702 - z = x11703 - z = x11704 - z = x11705 - z = x11706 - z = x11707 - z = x11708 - z = x11709 - z = x11710 - z = x11711 - z = x11712 - z = x11713 - z = x11714 - z = x11715 - z = x11716 - z = x11717 - z = x11718 - z = x11719 - z = x11720 - z = x11721 - z = x11722 - z = x11723 - z = x11724 - z = x11725 - z = x11726 - z = x11727 - z = x11728 - z = x11729 - z = x11730 - z = x11731 - z = x11732 - z = x11733 - z = x11734 - z = x11735 - z = x11736 - z = x11737 - z = x11738 - z = x11739 - z = x11740 - z = x11741 - z = x11742 - z = x11743 - z = x11744 - z = x11745 - z = x11746 - z = x11747 - z = x11748 - z = x11749 - z = x11750 - z = x11751 - z = x11752 - z = x11753 - z = x11754 - z = x11755 - z = x11756 - z = x11757 - z = x11758 - z = x11759 - z = x11760 - z = x11761 - z = x11762 - z = x11763 - z = x11764 - z = x11765 - z = x11766 - z = x11767 - z = x11768 - z = x11769 - z = x11770 - z = x11771 - z = x11772 - z = x11773 - z = x11774 - z = x11775 - z = x11776 - z = x11777 - z = x11778 - z = x11779 - z = x11780 - z = x11781 - z = x11782 - z = x11783 - z = x11784 - z = x11785 - z = x11786 - z = x11787 - z = x11788 - z = x11789 - z = x11790 - z = x11791 - z = x11792 - z = x11793 - z = x11794 - z = x11795 - z = x11796 - z = x11797 - z = x11798 - z = x11799 - z = x11800 - z = x11801 - z = x11802 - z = x11803 - z = x11804 - z = x11805 - z = x11806 - z = x11807 - z = x11808 - z = x11809 - z = x11810 - z = x11811 - z = x11812 - z = x11813 - z = x11814 - z = x11815 - z = x11816 - z = x11817 - z = x11818 - z = x11819 - z = x11820 - z = x11821 - z = x11822 - z = x11823 - z = x11824 - z = x11825 - z = x11826 - z = x11827 - z = x11828 - z = x11829 - z = x11830 - z = x11831 - z = x11832 - z = x11833 - z = x11834 - z = x11835 - z = x11836 - z = x11837 - z = x11838 - z = x11839 - z = x11840 - z = x11841 - z = x11842 - z = x11843 - z = x11844 - z = x11845 - z = x11846 - z = x11847 - z = x11848 - z = x11849 - z = x11850 - z = x11851 - z = x11852 - z = x11853 - z = x11854 - z = x11855 - z = x11856 - z = x11857 - z = x11858 - z = x11859 - z = x11860 - z = x11861 - z = x11862 - z = x11863 - z = x11864 - z = x11865 - z = x11866 - z = x11867 - z = x11868 - z = x11869 - z = x11870 - z = x11871 - z = x11872 - z = x11873 - z = x11874 - z = x11875 - z = x11876 - z = x11877 - z = x11878 - z = x11879 - z = x11880 - z = x11881 - z = x11882 - z = x11883 - z = x11884 - z = x11885 - z = x11886 - z = x11887 - z = x11888 - z = x11889 - z = x11890 - z = x11891 - z = x11892 - z = x11893 - z = x11894 - z = x11895 - z = x11896 - z = x11897 - z = x11898 - z = x11899 - z = x11900 - z = x11901 - z = x11902 - z = x11903 - z = x11904 - z = x11905 - z = x11906 - z = x11907 - z = x11908 - z = x11909 - z = x11910 - z = x11911 - z = x11912 - z = x11913 - z = x11914 - z = x11915 - z = x11916 - z = x11917 - z = x11918 - z = x11919 - z = x11920 - z = x11921 - z = x11922 - z = x11923 - z = x11924 - z = x11925 - z = x11926 - z = x11927 - z = x11928 - z = x11929 - z = x11930 - z = x11931 - z = x11932 - z = x11933 - z = x11934 - z = x11935 - z = x11936 - z = x11937 - z = x11938 - z = x11939 - z = x11940 - z = x11941 - z = x11942 - z = x11943 - z = x11944 - z = x11945 - z = x11946 - z = x11947 - z = x11948 - z = x11949 - z = x11950 - z = x11951 - z = x11952 - z = x11953 - z = x11954 - z = x11955 - z = x11956 - z = x11957 - z = x11958 - z = x11959 - z = x11960 - z = x11961 - z = x11962 - z = x11963 - z = x11964 - z = x11965 - z = x11966 - z = x11967 - z = x11968 - z = x11969 - z = x11970 - z = x11971 - z = x11972 - z = x11973 - z = x11974 - z = x11975 - z = x11976 - z = x11977 - z = x11978 - z = x11979 - z = x11980 - z = x11981 - z = x11982 - z = x11983 - z = x11984 - z = x11985 - z = x11986 - z = x11987 - z = x11988 - z = x11989 - z = x11990 - z = x11991 - z = x11992 - z = x11993 - z = x11994 - z = x11995 - z = x11996 - z = x11997 - z = x11998 - z = x11999 - z = x12000 - z = x12001 - z = x12002 - z = x12003 - z = x12004 - z = x12005 - z = x12006 - z = x12007 - z = x12008 - z = x12009 - z = x12010 - z = x12011 - z = x12012 - z = x12013 - z = x12014 - z = x12015 - z = x12016 - z = x12017 - z = x12018 - z = x12019 - z = x12020 - z = x12021 - z = x12022 - z = x12023 - z = x12024 - z = x12025 - z = x12026 - z = x12027 - z = x12028 - z = x12029 - z = x12030 - z = x12031 - z = x12032 - z = x12033 - z = x12034 - z = x12035 - z = x12036 - z = x12037 - z = x12038 - z = x12039 - z = x12040 - z = x12041 - z = x12042 - z = x12043 - z = x12044 - z = x12045 - z = x12046 - z = x12047 - z = x12048 - z = x12049 - z = x12050 - z = x12051 - z = x12052 - z = x12053 - z = x12054 - z = x12055 - z = x12056 - z = x12057 - z = x12058 - z = x12059 - z = x12060 - z = x12061 - z = x12062 - z = x12063 - z = x12064 - z = x12065 - z = x12066 - z = x12067 - z = x12068 - z = x12069 - z = x12070 - z = x12071 - z = x12072 - z = x12073 - z = x12074 - z = x12075 - z = x12076 - z = x12077 - z = x12078 - z = x12079 - z = x12080 - z = x12081 - z = x12082 - z = x12083 - z = x12084 - z = x12085 - z = x12086 - z = x12087 - z = x12088 - z = x12089 - z = x12090 - z = x12091 - z = x12092 - z = x12093 - z = x12094 - z = x12095 - z = x12096 - z = x12097 - z = x12098 - z = x12099 - z = x12100 - z = x12101 - z = x12102 - z = x12103 - z = x12104 - z = x12105 - z = x12106 - z = x12107 - z = x12108 - z = x12109 - z = x12110 - z = x12111 - z = x12112 - z = x12113 - z = x12114 - z = x12115 - z = x12116 - z = x12117 - z = x12118 - z = x12119 - z = x12120 - z = x12121 - z = x12122 - z = x12123 - z = x12124 - z = x12125 - z = x12126 - z = x12127 - z = x12128 - z = x12129 - z = x12130 - z = x12131 - z = x12132 - z = x12133 - z = x12134 - z = x12135 - z = x12136 - z = x12137 - z = x12138 - z = x12139 - z = x12140 - z = x12141 - z = x12142 - z = x12143 - z = x12144 - z = x12145 - z = x12146 - z = x12147 - z = x12148 - z = x12149 - z = x12150 - z = x12151 - z = x12152 - z = x12153 - z = x12154 - z = x12155 - z = x12156 - z = x12157 - z = x12158 - z = x12159 - z = x12160 - z = x12161 - z = x12162 - z = x12163 - z = x12164 - z = x12165 - z = x12166 - z = x12167 - z = x12168 - z = x12169 - z = x12170 - z = x12171 - z = x12172 - z = x12173 - z = x12174 - z = x12175 - z = x12176 - z = x12177 - z = x12178 - z = x12179 - z = x12180 - z = x12181 - z = x12182 - z = x12183 - z = x12184 - z = x12185 - z = x12186 - z = x12187 - z = x12188 - z = x12189 - z = x12190 - z = x12191 - z = x12192 - z = x12193 - z = x12194 - z = x12195 - z = x12196 - z = x12197 - z = x12198 - z = x12199 - z = x12200 - z = x12201 - z = x12202 - z = x12203 - z = x12204 - z = x12205 - z = x12206 - z = x12207 - z = x12208 - z = x12209 - z = x12210 - z = x12211 - z = x12212 - z = x12213 - z = x12214 - z = x12215 - z = x12216 - z = x12217 - z = x12218 - z = x12219 - z = x12220 - z = x12221 - z = x12222 - z = x12223 - z = x12224 - z = x12225 - z = x12226 - z = x12227 - z = x12228 - z = x12229 - z = x12230 - z = x12231 - z = x12232 - z = x12233 - z = x12234 - z = x12235 - z = x12236 - z = x12237 - z = x12238 - z = x12239 - z = x12240 - z = x12241 - z = x12242 - z = x12243 - z = x12244 - z = x12245 - z = x12246 - z = x12247 - z = x12248 - z = x12249 - z = x12250 - z = x12251 - z = x12252 - z = x12253 - z = x12254 - z = x12255 - z = x12256 - z = x12257 - z = x12258 - z = x12259 - z = x12260 - z = x12261 - z = x12262 - z = x12263 - z = x12264 - z = x12265 - z = x12266 - z = x12267 - z = x12268 - z = x12269 - z = x12270 - z = x12271 - z = x12272 - z = x12273 - z = x12274 - z = x12275 - z = x12276 - z = x12277 - z = x12278 - z = x12279 - z = x12280 - z = x12281 - z = x12282 - z = x12283 - z = x12284 - z = x12285 - z = x12286 - z = x12287 - z = x12288 - z = x12289 - z = x12290 - z = x12291 - z = x12292 - z = x12293 - z = x12294 - z = x12295 - z = x12296 - z = x12297 - z = x12298 - z = x12299 - z = x12300 - z = x12301 - z = x12302 - z = x12303 - z = x12304 - z = x12305 - z = x12306 - z = x12307 - z = x12308 - z = x12309 - z = x12310 - z = x12311 - z = x12312 - z = x12313 - z = x12314 - z = x12315 - z = x12316 - z = x12317 - z = x12318 - z = x12319 - z = x12320 - z = x12321 - z = x12322 - z = x12323 - z = x12324 - z = x12325 - z = x12326 - z = x12327 - z = x12328 - z = x12329 - z = x12330 - z = x12331 - z = x12332 - z = x12333 - z = x12334 - z = x12335 - z = x12336 - z = x12337 - z = x12338 - z = x12339 - z = x12340 - z = x12341 - z = x12342 - z = x12343 - z = x12344 - z = x12345 - z = x12346 - z = x12347 - z = x12348 - z = x12349 - z = x12350 - z = x12351 - z = x12352 - z = x12353 - z = x12354 - z = x12355 - z = x12356 - z = x12357 - z = x12358 - z = x12359 - z = x12360 - z = x12361 - z = x12362 - z = x12363 - z = x12364 - z = x12365 - z = x12366 - z = x12367 - z = x12368 - z = x12369 - z = x12370 - z = x12371 - z = x12372 - z = x12373 - z = x12374 - z = x12375 - z = x12376 - z = x12377 - z = x12378 - z = x12379 - z = x12380 - z = x12381 - z = x12382 - z = x12383 - z = x12384 - z = x12385 - z = x12386 - z = x12387 - z = x12388 - z = x12389 - z = x12390 - z = x12391 - z = x12392 - z = x12393 - z = x12394 - z = x12395 - z = x12396 - z = x12397 - z = x12398 - z = x12399 - z = x12400 - z = x12401 - z = x12402 - z = x12403 - z = x12404 - z = x12405 - z = x12406 - z = x12407 - z = x12408 - z = x12409 - z = x12410 - z = x12411 - z = x12412 - z = x12413 - z = x12414 - z = x12415 - z = x12416 - z = x12417 - z = x12418 - z = x12419 - z = x12420 - z = x12421 - z = x12422 - z = x12423 - z = x12424 - z = x12425 - z = x12426 - z = x12427 - z = x12428 - z = x12429 - z = x12430 - z = x12431 - z = x12432 - z = x12433 - z = x12434 - z = x12435 - z = x12436 - z = x12437 - z = x12438 - z = x12439 - z = x12440 - z = x12441 - z = x12442 - z = x12443 - z = x12444 - z = x12445 - z = x12446 - z = x12447 - z = x12448 - z = x12449 - z = x12450 - z = x12451 - z = x12452 - z = x12453 - z = x12454 - z = x12455 - z = x12456 - z = x12457 - z = x12458 - z = x12459 - z = x12460 - z = x12461 - z = x12462 - z = x12463 - z = x12464 - z = x12465 - z = x12466 - z = x12467 - z = x12468 - z = x12469 - z = x12470 - z = x12471 - z = x12472 - z = x12473 - z = x12474 - z = x12475 - z = x12476 - z = x12477 - z = x12478 - z = x12479 - z = x12480 - z = x12481 - z = x12482 - z = x12483 - z = x12484 - z = x12485 - z = x12486 - z = x12487 - z = x12488 - z = x12489 - z = x12490 - z = x12491 - z = x12492 - z = x12493 - z = x12494 - z = x12495 - z = x12496 - z = x12497 - z = x12498 - z = x12499 - z = x12500 - z = x12501 - z = x12502 - z = x12503 - z = x12504 - z = x12505 - z = x12506 - z = x12507 - z = x12508 - z = x12509 - z = x12510 - z = x12511 - z = x12512 - z = x12513 - z = x12514 - z = x12515 - z = x12516 - z = x12517 - z = x12518 - z = x12519 - z = x12520 - z = x12521 - z = x12522 - z = x12523 - z = x12524 - z = x12525 - z = x12526 - z = x12527 - z = x12528 - z = x12529 - z = x12530 - z = x12531 - z = x12532 - z = x12533 - z = x12534 - z = x12535 - z = x12536 - z = x12537 - z = x12538 - z = x12539 - z = x12540 - z = x12541 - z = x12542 - z = x12543 - z = x12544 - z = x12545 - z = x12546 - z = x12547 - z = x12548 - z = x12549 - z = x12550 - z = x12551 - z = x12552 - z = x12553 - z = x12554 - z = x12555 - z = x12556 - z = x12557 - z = x12558 - z = x12559 - z = x12560 - z = x12561 - z = x12562 - z = x12563 - z = x12564 - z = x12565 - z = x12566 - z = x12567 - z = x12568 - z = x12569 - z = x12570 - z = x12571 - z = x12572 - z = x12573 - z = x12574 - z = x12575 - z = x12576 - z = x12577 - z = x12578 - z = x12579 - z = x12580 - z = x12581 - z = x12582 - z = x12583 - z = x12584 - z = x12585 - z = x12586 - z = x12587 - z = x12588 - z = x12589 - z = x12590 - z = x12591 - z = x12592 - z = x12593 - z = x12594 - z = x12595 - z = x12596 - z = x12597 - z = x12598 - z = x12599 - z = x12600 - z = x12601 - z = x12602 - z = x12603 - z = x12604 - z = x12605 - z = x12606 - z = x12607 - z = x12608 - z = x12609 - z = x12610 - z = x12611 - z = x12612 - z = x12613 - z = x12614 - z = x12615 - z = x12616 - z = x12617 - z = x12618 - z = x12619 - z = x12620 - z = x12621 - z = x12622 - z = x12623 - z = x12624 - z = x12625 - z = x12626 - z = x12627 - z = x12628 - z = x12629 - z = x12630 - z = x12631 - z = x12632 - z = x12633 - z = x12634 - z = x12635 - z = x12636 - z = x12637 - z = x12638 - z = x12639 - z = x12640 - z = x12641 - z = x12642 - z = x12643 - z = x12644 - z = x12645 - z = x12646 - z = x12647 - z = x12648 - z = x12649 - z = x12650 - z = x12651 - z = x12652 - z = x12653 - z = x12654 - z = x12655 - z = x12656 - z = x12657 - z = x12658 - z = x12659 - z = x12660 - z = x12661 - z = x12662 - z = x12663 - z = x12664 - z = x12665 - z = x12666 - z = x12667 - z = x12668 - z = x12669 - z = x12670 - z = x12671 - z = x12672 - z = x12673 - z = x12674 - z = x12675 - z = x12676 - z = x12677 - z = x12678 - z = x12679 - z = x12680 - z = x12681 - z = x12682 - z = x12683 - z = x12684 - z = x12685 - z = x12686 - z = x12687 - z = x12688 - z = x12689 - z = x12690 - z = x12691 - z = x12692 - z = x12693 - z = x12694 - z = x12695 - z = x12696 - z = x12697 - z = x12698 - z = x12699 - z = x12700 - z = x12701 - z = x12702 - z = x12703 - z = x12704 - z = x12705 - z = x12706 - z = x12707 - z = x12708 - z = x12709 - z = x12710 - z = x12711 - z = x12712 - z = x12713 - z = x12714 - z = x12715 - z = x12716 - z = x12717 - z = x12718 - z = x12719 - z = x12720 - z = x12721 - z = x12722 - z = x12723 - z = x12724 - z = x12725 - z = x12726 - z = x12727 - z = x12728 - z = x12729 - z = x12730 - z = x12731 - z = x12732 - z = x12733 - z = x12734 - z = x12735 - z = x12736 - z = x12737 - z = x12738 - z = x12739 - z = x12740 - z = x12741 - z = x12742 - z = x12743 - z = x12744 - z = x12745 - z = x12746 - z = x12747 - z = x12748 - z = x12749 - z = x12750 - z = x12751 - z = x12752 - z = x12753 - z = x12754 - z = x12755 - z = x12756 - z = x12757 - z = x12758 - z = x12759 - z = x12760 - z = x12761 - z = x12762 - z = x12763 - z = x12764 - z = x12765 - z = x12766 - z = x12767 - z = x12768 - z = x12769 - z = x12770 - z = x12771 - z = x12772 - z = x12773 - z = x12774 - z = x12775 - z = x12776 - z = x12777 - z = x12778 - z = x12779 - z = x12780 - z = x12781 - z = x12782 - z = x12783 - z = x12784 - z = x12785 - z = x12786 - z = x12787 - z = x12788 - z = x12789 - z = x12790 - z = x12791 - z = x12792 - z = x12793 - z = x12794 - z = x12795 - z = x12796 - z = x12797 - z = x12798 - z = x12799 - z = x12800 - z = x12801 - z = x12802 - z = x12803 - z = x12804 - z = x12805 - z = x12806 - z = x12807 - z = x12808 - z = x12809 - z = x12810 - z = x12811 - z = x12812 - z = x12813 - z = x12814 - z = x12815 - z = x12816 - z = x12817 - z = x12818 - z = x12819 - z = x12820 - z = x12821 - z = x12822 - z = x12823 - z = x12824 - z = x12825 - z = x12826 - z = x12827 - z = x12828 - z = x12829 - z = x12830 - z = x12831 - z = x12832 - z = x12833 - z = x12834 - z = x12835 - z = x12836 - z = x12837 - z = x12838 - z = x12839 - z = x12840 - z = x12841 - z = x12842 - z = x12843 - z = x12844 - z = x12845 - z = x12846 - z = x12847 - z = x12848 - z = x12849 - z = x12850 - z = x12851 - z = x12852 - z = x12853 - z = x12854 - z = x12855 - z = x12856 - z = x12857 - z = x12858 - z = x12859 - z = x12860 - z = x12861 - z = x12862 - z = x12863 - z = x12864 - z = x12865 - z = x12866 - z = x12867 - z = x12868 - z = x12869 - z = x12870 - z = x12871 - z = x12872 - z = x12873 - z = x12874 - z = x12875 - z = x12876 - z = x12877 - z = x12878 - z = x12879 - z = x12880 - z = x12881 - z = x12882 - z = x12883 - z = x12884 - z = x12885 - z = x12886 - z = x12887 - z = x12888 - z = x12889 - z = x12890 - z = x12891 - z = x12892 - z = x12893 - z = x12894 - z = x12895 - z = x12896 - z = x12897 - z = x12898 - z = x12899 - z = x12900 - z = x12901 - z = x12902 - z = x12903 - z = x12904 - z = x12905 - z = x12906 - z = x12907 - z = x12908 - z = x12909 - z = x12910 - z = x12911 - z = x12912 - z = x12913 - z = x12914 - z = x12915 - z = x12916 - z = x12917 - z = x12918 - z = x12919 - z = x12920 - z = x12921 - z = x12922 - z = x12923 - z = x12924 - z = x12925 - z = x12926 - z = x12927 - z = x12928 - z = x12929 - z = x12930 - z = x12931 - z = x12932 - z = x12933 - z = x12934 - z = x12935 - z = x12936 - z = x12937 - z = x12938 - z = x12939 - z = x12940 - z = x12941 - z = x12942 - z = x12943 - z = x12944 - z = x12945 - z = x12946 - z = x12947 - z = x12948 - z = x12949 - z = x12950 - z = x12951 - z = x12952 - z = x12953 - z = x12954 - z = x12955 - z = x12956 - z = x12957 - z = x12958 - z = x12959 - z = x12960 - z = x12961 - z = x12962 - z = x12963 - z = x12964 - z = x12965 - z = x12966 - z = x12967 - z = x12968 - z = x12969 - z = x12970 - z = x12971 - z = x12972 - z = x12973 - z = x12974 - z = x12975 - z = x12976 - z = x12977 - z = x12978 - z = x12979 - z = x12980 - z = x12981 - z = x12982 - z = x12983 - z = x12984 - z = x12985 - z = x12986 - z = x12987 - z = x12988 - z = x12989 - z = x12990 - z = x12991 - z = x12992 - z = x12993 - z = x12994 - z = x12995 - z = x12996 - z = x12997 - z = x12998 - z = x12999 - z = x13000 - z = x13001 - z = x13002 - z = x13003 - z = x13004 - z = x13005 - z = x13006 - z = x13007 - z = x13008 - z = x13009 - z = x13010 - z = x13011 - z = x13012 - z = x13013 - z = x13014 - z = x13015 - z = x13016 - z = x13017 - z = x13018 - z = x13019 - z = x13020 - z = x13021 - z = x13022 - z = x13023 - z = x13024 - z = x13025 - z = x13026 - z = x13027 - z = x13028 - z = x13029 - z = x13030 - z = x13031 - z = x13032 - z = x13033 - z = x13034 - z = x13035 - z = x13036 - z = x13037 - z = x13038 - z = x13039 - z = x13040 - z = x13041 - z = x13042 - z = x13043 - z = x13044 - z = x13045 - z = x13046 - z = x13047 - z = x13048 - z = x13049 - z = x13050 - z = x13051 - z = x13052 - z = x13053 - z = x13054 - z = x13055 - z = x13056 - z = x13057 - z = x13058 - z = x13059 - z = x13060 - z = x13061 - z = x13062 - z = x13063 - z = x13064 - z = x13065 - z = x13066 - z = x13067 - z = x13068 - z = x13069 - z = x13070 - z = x13071 - z = x13072 - z = x13073 - z = x13074 - z = x13075 - z = x13076 - z = x13077 - z = x13078 - z = x13079 - z = x13080 - z = x13081 - z = x13082 - z = x13083 - z = x13084 - z = x13085 - z = x13086 - z = x13087 - z = x13088 - z = x13089 - z = x13090 - z = x13091 - z = x13092 - z = x13093 - z = x13094 - z = x13095 - z = x13096 - z = x13097 - z = x13098 - z = x13099 - z = x13100 - z = x13101 - z = x13102 - z = x13103 - z = x13104 - z = x13105 - z = x13106 - z = x13107 - z = x13108 - z = x13109 - z = x13110 - z = x13111 - z = x13112 - z = x13113 - z = x13114 - z = x13115 - z = x13116 - z = x13117 - z = x13118 - z = x13119 - z = x13120 - z = x13121 - z = x13122 - z = x13123 - z = x13124 - z = x13125 - z = x13126 - z = x13127 - z = x13128 - z = x13129 - z = x13130 - z = x13131 - z = x13132 - z = x13133 - z = x13134 - z = x13135 - z = x13136 - z = x13137 - z = x13138 - z = x13139 - z = x13140 - z = x13141 - z = x13142 - z = x13143 - z = x13144 - z = x13145 - z = x13146 - z = x13147 - z = x13148 - z = x13149 - z = x13150 - z = x13151 - z = x13152 - z = x13153 - z = x13154 - z = x13155 - z = x13156 - z = x13157 - z = x13158 - z = x13159 - z = x13160 - z = x13161 - z = x13162 - z = x13163 - z = x13164 - z = x13165 - z = x13166 - z = x13167 - z = x13168 - z = x13169 - z = x13170 - z = x13171 - z = x13172 - z = x13173 - z = x13174 - z = x13175 - z = x13176 - z = x13177 - z = x13178 - z = x13179 - z = x13180 - z = x13181 - z = x13182 - z = x13183 - z = x13184 - z = x13185 - z = x13186 - z = x13187 - z = x13188 - z = x13189 - z = x13190 - z = x13191 - z = x13192 - z = x13193 - z = x13194 - z = x13195 - z = x13196 - z = x13197 - z = x13198 - z = x13199 - z = x13200 - z = x13201 - z = x13202 - z = x13203 - z = x13204 - z = x13205 - z = x13206 - z = x13207 - z = x13208 - z = x13209 - z = x13210 - z = x13211 - z = x13212 - z = x13213 - z = x13214 - z = x13215 - z = x13216 - z = x13217 - z = x13218 - z = x13219 - z = x13220 - z = x13221 - z = x13222 - z = x13223 - z = x13224 - z = x13225 - z = x13226 - z = x13227 - z = x13228 - z = x13229 - z = x13230 - z = x13231 - z = x13232 - z = x13233 - z = x13234 - z = x13235 - z = x13236 - z = x13237 - z = x13238 - z = x13239 - z = x13240 - z = x13241 - z = x13242 - z = x13243 - z = x13244 - z = x13245 - z = x13246 - z = x13247 - z = x13248 - z = x13249 - z = x13250 - z = x13251 - z = x13252 - z = x13253 - z = x13254 - z = x13255 - z = x13256 - z = x13257 - z = x13258 - z = x13259 - z = x13260 - z = x13261 - z = x13262 - z = x13263 - z = x13264 - z = x13265 - z = x13266 - z = x13267 - z = x13268 - z = x13269 - z = x13270 - z = x13271 - z = x13272 - z = x13273 - z = x13274 - z = x13275 - z = x13276 - z = x13277 - z = x13278 - z = x13279 - z = x13280 - z = x13281 - z = x13282 - z = x13283 - z = x13284 - z = x13285 - z = x13286 - z = x13287 - z = x13288 - z = x13289 - z = x13290 - z = x13291 - z = x13292 - z = x13293 - z = x13294 - z = x13295 - z = x13296 - z = x13297 - z = x13298 - z = x13299 - z = x13300 - z = x13301 - z = x13302 - z = x13303 - z = x13304 - z = x13305 - z = x13306 - z = x13307 - z = x13308 - z = x13309 - z = x13310 - z = x13311 - z = x13312 - z = x13313 - z = x13314 - z = x13315 - z = x13316 - z = x13317 - z = x13318 - z = x13319 - z = x13320 - z = x13321 - z = x13322 - z = x13323 - z = x13324 - z = x13325 - z = x13326 - z = x13327 - z = x13328 - z = x13329 - z = x13330 - z = x13331 - z = x13332 - z = x13333 - z = x13334 - z = x13335 - z = x13336 - z = x13337 - z = x13338 - z = x13339 - z = x13340 - z = x13341 - z = x13342 - z = x13343 - z = x13344 - z = x13345 - z = x13346 - z = x13347 - z = x13348 - z = x13349 - z = x13350 - z = x13351 - z = x13352 - z = x13353 - z = x13354 - z = x13355 - z = x13356 - z = x13357 - z = x13358 - z = x13359 - z = x13360 - z = x13361 - z = x13362 - z = x13363 - z = x13364 - z = x13365 - z = x13366 - z = x13367 - z = x13368 - z = x13369 - z = x13370 - z = x13371 - z = x13372 - z = x13373 - z = x13374 - z = x13375 - z = x13376 - z = x13377 - z = x13378 - z = x13379 - z = x13380 - z = x13381 - z = x13382 - z = x13383 - z = x13384 - z = x13385 - z = x13386 - z = x13387 - z = x13388 - z = x13389 - z = x13390 - z = x13391 - z = x13392 - z = x13393 - z = x13394 - z = x13395 - z = x13396 - z = x13397 - z = x13398 - z = x13399 - z = x13400 - z = x13401 - z = x13402 - z = x13403 - z = x13404 - z = x13405 - z = x13406 - z = x13407 - z = x13408 - z = x13409 - z = x13410 - z = x13411 - z = x13412 - z = x13413 - z = x13414 - z = x13415 - z = x13416 - z = x13417 - z = x13418 - z = x13419 - z = x13420 - z = x13421 - z = x13422 - z = x13423 - z = x13424 - z = x13425 - z = x13426 - z = x13427 - z = x13428 - z = x13429 - z = x13430 - z = x13431 - z = x13432 - z = x13433 - z = x13434 - z = x13435 - z = x13436 - z = x13437 - z = x13438 - z = x13439 - z = x13440 - z = x13441 - z = x13442 - z = x13443 - z = x13444 - z = x13445 - z = x13446 - z = x13447 - z = x13448 - z = x13449 - z = x13450 - z = x13451 - z = x13452 - z = x13453 - z = x13454 - z = x13455 - z = x13456 - z = x13457 - z = x13458 - z = x13459 - z = x13460 - z = x13461 - z = x13462 - z = x13463 - z = x13464 - z = x13465 - z = x13466 - z = x13467 - z = x13468 - z = x13469 - z = x13470 - z = x13471 - z = x13472 - z = x13473 - z = x13474 - z = x13475 - z = x13476 - z = x13477 - z = x13478 - z = x13479 - z = x13480 - z = x13481 - z = x13482 - z = x13483 - z = x13484 - z = x13485 - z = x13486 - z = x13487 - z = x13488 - z = x13489 - z = x13490 - z = x13491 - z = x13492 - z = x13493 - z = x13494 - z = x13495 - z = x13496 - z = x13497 - z = x13498 - z = x13499 - z = x13500 - z = x13501 - z = x13502 - z = x13503 - z = x13504 - z = x13505 - z = x13506 - z = x13507 - z = x13508 - z = x13509 - z = x13510 - z = x13511 - z = x13512 - z = x13513 - z = x13514 - z = x13515 - z = x13516 - z = x13517 - z = x13518 - z = x13519 - z = x13520 - z = x13521 - z = x13522 - z = x13523 - z = x13524 - z = x13525 - z = x13526 - z = x13527 - z = x13528 - z = x13529 - z = x13530 - z = x13531 - z = x13532 - z = x13533 - z = x13534 - z = x13535 - z = x13536 - z = x13537 - z = x13538 - z = x13539 - z = x13540 - z = x13541 - z = x13542 - z = x13543 - z = x13544 - z = x13545 - z = x13546 - z = x13547 - z = x13548 - z = x13549 - z = x13550 - z = x13551 - z = x13552 - z = x13553 - z = x13554 - z = x13555 - z = x13556 - z = x13557 - z = x13558 - z = x13559 - z = x13560 - z = x13561 - z = x13562 - z = x13563 - z = x13564 - z = x13565 - z = x13566 - z = x13567 - z = x13568 - z = x13569 - z = x13570 - z = x13571 - z = x13572 - z = x13573 - z = x13574 - z = x13575 - z = x13576 - z = x13577 - z = x13578 - z = x13579 - z = x13580 - z = x13581 - z = x13582 - z = x13583 - z = x13584 - z = x13585 - z = x13586 - z = x13587 - z = x13588 - z = x13589 - z = x13590 - z = x13591 - z = x13592 - z = x13593 - z = x13594 - z = x13595 - z = x13596 - z = x13597 - z = x13598 - z = x13599 - z = x13600 - z = x13601 - z = x13602 - z = x13603 - z = x13604 - z = x13605 - z = x13606 - z = x13607 - z = x13608 - z = x13609 - z = x13610 - z = x13611 - z = x13612 - z = x13613 - z = x13614 - z = x13615 - z = x13616 - z = x13617 - z = x13618 - z = x13619 - z = x13620 - z = x13621 - z = x13622 - z = x13623 - z = x13624 - z = x13625 - z = x13626 - z = x13627 - z = x13628 - z = x13629 - z = x13630 - z = x13631 - z = x13632 - z = x13633 - z = x13634 - z = x13635 - z = x13636 - z = x13637 - z = x13638 - z = x13639 - z = x13640 - z = x13641 - z = x13642 - z = x13643 - z = x13644 - z = x13645 - z = x13646 - z = x13647 - z = x13648 - z = x13649 - z = x13650 - z = x13651 - z = x13652 - z = x13653 - z = x13654 - z = x13655 - z = x13656 - z = x13657 - z = x13658 - z = x13659 - z = x13660 - z = x13661 - z = x13662 - z = x13663 - z = x13664 - z = x13665 - z = x13666 - z = x13667 - z = x13668 - z = x13669 - z = x13670 - z = x13671 - z = x13672 - z = x13673 - z = x13674 - z = x13675 - z = x13676 - z = x13677 - z = x13678 - z = x13679 - z = x13680 - z = x13681 - z = x13682 - z = x13683 - z = x13684 - z = x13685 - z = x13686 - z = x13687 - z = x13688 - z = x13689 - z = x13690 - z = x13691 - z = x13692 - z = x13693 - z = x13694 - z = x13695 - z = x13696 - z = x13697 - z = x13698 - z = x13699 - z = x13700 - z = x13701 - z = x13702 - z = x13703 - z = x13704 - z = x13705 - z = x13706 - z = x13707 - z = x13708 - z = x13709 - z = x13710 - z = x13711 - z = x13712 - z = x13713 - z = x13714 - z = x13715 - z = x13716 - z = x13717 - z = x13718 - z = x13719 - z = x13720 - z = x13721 - z = x13722 - z = x13723 - z = x13724 - z = x13725 - z = x13726 - z = x13727 - z = x13728 - z = x13729 - z = x13730 - z = x13731 - z = x13732 - z = x13733 - z = x13734 - z = x13735 - z = x13736 - z = x13737 - z = x13738 - z = x13739 - z = x13740 - z = x13741 - z = x13742 - z = x13743 - z = x13744 - z = x13745 - z = x13746 - z = x13747 - z = x13748 - z = x13749 - z = x13750 - z = x13751 - z = x13752 - z = x13753 - z = x13754 - z = x13755 - z = x13756 - z = x13757 - z = x13758 - z = x13759 - z = x13760 - z = x13761 - z = x13762 - z = x13763 - z = x13764 - z = x13765 - z = x13766 - z = x13767 - z = x13768 - z = x13769 - z = x13770 - z = x13771 - z = x13772 - z = x13773 - z = x13774 - z = x13775 - z = x13776 - z = x13777 - z = x13778 - z = x13779 - z = x13780 - z = x13781 - z = x13782 - z = x13783 - z = x13784 - z = x13785 - z = x13786 - z = x13787 - z = x13788 - z = x13789 - z = x13790 - z = x13791 - z = x13792 - z = x13793 - z = x13794 - z = x13795 - z = x13796 - z = x13797 - z = x13798 - z = x13799 - z = x13800 - z = x13801 - z = x13802 - z = x13803 - z = x13804 - z = x13805 - z = x13806 - z = x13807 - z = x13808 - z = x13809 - z = x13810 - z = x13811 - z = x13812 - z = x13813 - z = x13814 - z = x13815 - z = x13816 - z = x13817 - z = x13818 - z = x13819 - z = x13820 - z = x13821 - z = x13822 - z = x13823 - z = x13824 - z = x13825 - z = x13826 - z = x13827 - z = x13828 - z = x13829 - z = x13830 - z = x13831 - z = x13832 - z = x13833 - z = x13834 - z = x13835 - z = x13836 - z = x13837 - z = x13838 - z = x13839 - z = x13840 - z = x13841 - z = x13842 - z = x13843 - z = x13844 - z = x13845 - z = x13846 - z = x13847 - z = x13848 - z = x13849 - z = x13850 - z = x13851 - z = x13852 - z = x13853 - z = x13854 - z = x13855 - z = x13856 - z = x13857 - z = x13858 - z = x13859 - z = x13860 - z = x13861 - z = x13862 - z = x13863 - z = x13864 - z = x13865 - z = x13866 - z = x13867 - z = x13868 - z = x13869 - z = x13870 - z = x13871 - z = x13872 - z = x13873 - z = x13874 - z = x13875 - z = x13876 - z = x13877 - z = x13878 - z = x13879 - z = x13880 - z = x13881 - z = x13882 - z = x13883 - z = x13884 - z = x13885 - z = x13886 - z = x13887 - z = x13888 - z = x13889 - z = x13890 - z = x13891 - z = x13892 - z = x13893 - z = x13894 - z = x13895 - z = x13896 - z = x13897 - z = x13898 - z = x13899 - z = x13900 - z = x13901 - z = x13902 - z = x13903 - z = x13904 - z = x13905 - z = x13906 - z = x13907 - z = x13908 - z = x13909 - z = x13910 - z = x13911 - z = x13912 - z = x13913 - z = x13914 - z = x13915 - z = x13916 - z = x13917 - z = x13918 - z = x13919 - z = x13920 - z = x13921 - z = x13922 - z = x13923 - z = x13924 - z = x13925 - z = x13926 - z = x13927 - z = x13928 - z = x13929 - z = x13930 - z = x13931 - z = x13932 - z = x13933 - z = x13934 - z = x13935 - z = x13936 - z = x13937 - z = x13938 - z = x13939 - z = x13940 - z = x13941 - z = x13942 - z = x13943 - z = x13944 - z = x13945 - z = x13946 - z = x13947 - z = x13948 - z = x13949 - z = x13950 - z = x13951 - z = x13952 - z = x13953 - z = x13954 - z = x13955 - z = x13956 - z = x13957 - z = x13958 - z = x13959 - z = x13960 - z = x13961 - z = x13962 - z = x13963 - z = x13964 - z = x13965 - z = x13966 - z = x13967 - z = x13968 - z = x13969 - z = x13970 - z = x13971 - z = x13972 - z = x13973 - z = x13974 - z = x13975 - z = x13976 - z = x13977 - z = x13978 - z = x13979 - z = x13980 - z = x13981 - z = x13982 - z = x13983 - z = x13984 - z = x13985 - z = x13986 - z = x13987 - z = x13988 - z = x13989 - z = x13990 - z = x13991 - z = x13992 - z = x13993 - z = x13994 - z = x13995 - z = x13996 - z = x13997 - z = x13998 - z = x13999 - z = x14000 - z = x14001 - z = x14002 - z = x14003 - z = x14004 - z = x14005 - z = x14006 - z = x14007 - z = x14008 - z = x14009 - z = x14010 - z = x14011 - z = x14012 - z = x14013 - z = x14014 - z = x14015 - z = x14016 - z = x14017 - z = x14018 - z = x14019 - z = x14020 - z = x14021 - z = x14022 - z = x14023 - z = x14024 - z = x14025 - z = x14026 - z = x14027 - z = x14028 - z = x14029 - z = x14030 - z = x14031 - z = x14032 - z = x14033 - z = x14034 - z = x14035 - z = x14036 - z = x14037 - z = x14038 - z = x14039 - z = x14040 - z = x14041 - z = x14042 - z = x14043 - z = x14044 - z = x14045 - z = x14046 - z = x14047 - z = x14048 - z = x14049 - z = x14050 - z = x14051 - z = x14052 - z = x14053 - z = x14054 - z = x14055 - z = x14056 - z = x14057 - z = x14058 - z = x14059 - z = x14060 - z = x14061 - z = x14062 - z = x14063 - z = x14064 - z = x14065 - z = x14066 - z = x14067 - z = x14068 - z = x14069 - z = x14070 - z = x14071 - z = x14072 - z = x14073 - z = x14074 - z = x14075 - z = x14076 - z = x14077 - z = x14078 - z = x14079 - z = x14080 - z = x14081 - z = x14082 - z = x14083 - z = x14084 - z = x14085 - z = x14086 - z = x14087 - z = x14088 - z = x14089 - z = x14090 - z = x14091 - z = x14092 - z = x14093 - z = x14094 - z = x14095 - z = x14096 - z = x14097 - z = x14098 - z = x14099 - z = x14100 - z = x14101 - z = x14102 - z = x14103 - z = x14104 - z = x14105 - z = x14106 - z = x14107 - z = x14108 - z = x14109 - z = x14110 - z = x14111 - z = x14112 - z = x14113 - z = x14114 - z = x14115 - z = x14116 - z = x14117 - z = x14118 - z = x14119 - z = x14120 - z = x14121 - z = x14122 - z = x14123 - z = x14124 - z = x14125 - z = x14126 - z = x14127 - z = x14128 - z = x14129 - z = x14130 - z = x14131 - z = x14132 - z = x14133 - z = x14134 - z = x14135 - z = x14136 - z = x14137 - z = x14138 - z = x14139 - z = x14140 - z = x14141 - z = x14142 - z = x14143 - z = x14144 - z = x14145 - z = x14146 - z = x14147 - z = x14148 - z = x14149 - z = x14150 - z = x14151 - z = x14152 - z = x14153 - z = x14154 - z = x14155 - z = x14156 - z = x14157 - z = x14158 - z = x14159 - z = x14160 - z = x14161 - z = x14162 - z = x14163 - z = x14164 - z = x14165 - z = x14166 - z = x14167 - z = x14168 - z = x14169 - z = x14170 - z = x14171 - z = x14172 - z = x14173 - z = x14174 - z = x14175 - z = x14176 - z = x14177 - z = x14178 - z = x14179 - z = x14180 - z = x14181 - z = x14182 - z = x14183 - z = x14184 - z = x14185 - z = x14186 - z = x14187 - z = x14188 - z = x14189 - z = x14190 - z = x14191 - z = x14192 - z = x14193 - z = x14194 - z = x14195 - z = x14196 - z = x14197 - z = x14198 - z = x14199 - z = x14200 - z = x14201 - z = x14202 - z = x14203 - z = x14204 - z = x14205 - z = x14206 - z = x14207 - z = x14208 - z = x14209 - z = x14210 - z = x14211 - z = x14212 - z = x14213 - z = x14214 - z = x14215 - z = x14216 - z = x14217 - z = x14218 - z = x14219 - z = x14220 - z = x14221 - z = x14222 - z = x14223 - z = x14224 - z = x14225 - z = x14226 - z = x14227 - z = x14228 - z = x14229 - z = x14230 - z = x14231 - z = x14232 - z = x14233 - z = x14234 - z = x14235 - z = x14236 - z = x14237 - z = x14238 - z = x14239 - z = x14240 - z = x14241 - z = x14242 - z = x14243 - z = x14244 - z = x14245 - z = x14246 - z = x14247 - z = x14248 - z = x14249 - z = x14250 - z = x14251 - z = x14252 - z = x14253 - z = x14254 - z = x14255 - z = x14256 - z = x14257 - z = x14258 - z = x14259 - z = x14260 - z = x14261 - z = x14262 - z = x14263 - z = x14264 - z = x14265 - z = x14266 - z = x14267 - z = x14268 - z = x14269 - z = x14270 - z = x14271 - z = x14272 - z = x14273 - z = x14274 - z = x14275 - z = x14276 - z = x14277 - z = x14278 - z = x14279 - z = x14280 - z = x14281 - z = x14282 - z = x14283 - z = x14284 - z = x14285 - z = x14286 - z = x14287 - z = x14288 - z = x14289 - z = x14290 - z = x14291 - z = x14292 - z = x14293 - z = x14294 - z = x14295 - z = x14296 - z = x14297 - z = x14298 - z = x14299 - z = x14300 - z = x14301 - z = x14302 - z = x14303 - z = x14304 - z = x14305 - z = x14306 - z = x14307 - z = x14308 - z = x14309 - z = x14310 - z = x14311 - z = x14312 - z = x14313 - z = x14314 - z = x14315 - z = x14316 - z = x14317 - z = x14318 - z = x14319 - z = x14320 - z = x14321 - z = x14322 - z = x14323 - z = x14324 - z = x14325 - z = x14326 - z = x14327 - z = x14328 - z = x14329 - z = x14330 - z = x14331 - z = x14332 - z = x14333 - z = x14334 - z = x14335 - z = x14336 - z = x14337 - z = x14338 - z = x14339 - z = x14340 - z = x14341 - z = x14342 - z = x14343 - z = x14344 - z = x14345 - z = x14346 - z = x14347 - z = x14348 - z = x14349 - z = x14350 - z = x14351 - z = x14352 - z = x14353 - z = x14354 - z = x14355 - z = x14356 - z = x14357 - z = x14358 - z = x14359 - z = x14360 - z = x14361 - z = x14362 - z = x14363 - z = x14364 - z = x14365 - z = x14366 - z = x14367 - z = x14368 - z = x14369 - z = x14370 - z = x14371 - z = x14372 - z = x14373 - z = x14374 - z = x14375 - z = x14376 - z = x14377 - z = x14378 - z = x14379 - z = x14380 - z = x14381 - z = x14382 - z = x14383 - z = x14384 - z = x14385 - z = x14386 - z = x14387 - z = x14388 - z = x14389 - z = x14390 - z = x14391 - z = x14392 - z = x14393 - z = x14394 - z = x14395 - z = x14396 - z = x14397 - z = x14398 - z = x14399 - z = x14400 - z = x14401 - z = x14402 - z = x14403 - z = x14404 - z = x14405 - z = x14406 - z = x14407 - z = x14408 - z = x14409 - z = x14410 - z = x14411 - z = x14412 - z = x14413 - z = x14414 - z = x14415 - z = x14416 - z = x14417 - z = x14418 - z = x14419 - z = x14420 - z = x14421 - z = x14422 - z = x14423 - z = x14424 - z = x14425 - z = x14426 - z = x14427 - z = x14428 - z = x14429 - z = x14430 - z = x14431 - z = x14432 - z = x14433 - z = x14434 - z = x14435 - z = x14436 - z = x14437 - z = x14438 - z = x14439 - z = x14440 - z = x14441 - z = x14442 - z = x14443 - z = x14444 - z = x14445 - z = x14446 - z = x14447 - z = x14448 - z = x14449 - z = x14450 - z = x14451 - z = x14452 - z = x14453 - z = x14454 - z = x14455 - z = x14456 - z = x14457 - z = x14458 - z = x14459 - z = x14460 - z = x14461 - z = x14462 - z = x14463 - z = x14464 - z = x14465 - z = x14466 - z = x14467 - z = x14468 - z = x14469 - z = x14470 - z = x14471 - z = x14472 - z = x14473 - z = x14474 - z = x14475 - z = x14476 - z = x14477 - z = x14478 - z = x14479 - z = x14480 - z = x14481 - z = x14482 - z = x14483 - z = x14484 - z = x14485 - z = x14486 - z = x14487 - z = x14488 - z = x14489 - z = x14490 - z = x14491 - z = x14492 - z = x14493 - z = x14494 - z = x14495 - z = x14496 - z = x14497 - z = x14498 - z = x14499 - z = x14500 - z = x14501 - z = x14502 - z = x14503 - z = x14504 - z = x14505 - z = x14506 - z = x14507 - z = x14508 - z = x14509 - z = x14510 - z = x14511 - z = x14512 - z = x14513 - z = x14514 - z = x14515 - z = x14516 - z = x14517 - z = x14518 - z = x14519 - z = x14520 - z = x14521 - z = x14522 - z = x14523 - z = x14524 - z = x14525 - z = x14526 - z = x14527 - z = x14528 - z = x14529 - z = x14530 - z = x14531 - z = x14532 - z = x14533 - z = x14534 - z = x14535 - z = x14536 - z = x14537 - z = x14538 - z = x14539 - z = x14540 - z = x14541 - z = x14542 - z = x14543 - z = x14544 - z = x14545 - z = x14546 - z = x14547 - z = x14548 - z = x14549 - z = x14550 - z = x14551 - z = x14552 - z = x14553 - z = x14554 - z = x14555 - z = x14556 - z = x14557 - z = x14558 - z = x14559 - z = x14560 - z = x14561 - z = x14562 - z = x14563 - z = x14564 - z = x14565 - z = x14566 - z = x14567 - z = x14568 - z = x14569 - z = x14570 - z = x14571 - z = x14572 - z = x14573 - z = x14574 - z = x14575 - z = x14576 - z = x14577 - z = x14578 - z = x14579 - z = x14580 - z = x14581 - z = x14582 - z = x14583 - z = x14584 - z = x14585 - z = x14586 - z = x14587 - z = x14588 - z = x14589 - z = x14590 - z = x14591 - z = x14592 - z = x14593 - z = x14594 - z = x14595 - z = x14596 - z = x14597 - z = x14598 - z = x14599 - z = x14600 - z = x14601 - z = x14602 - z = x14603 - z = x14604 - z = x14605 - z = x14606 - z = x14607 - z = x14608 - z = x14609 - z = x14610 - z = x14611 - z = x14612 - z = x14613 - z = x14614 - z = x14615 - z = x14616 - z = x14617 - z = x14618 - z = x14619 - z = x14620 - z = x14621 - z = x14622 - z = x14623 - z = x14624 - z = x14625 - z = x14626 - z = x14627 - z = x14628 - z = x14629 - z = x14630 - z = x14631 - z = x14632 - z = x14633 - z = x14634 - z = x14635 - z = x14636 - z = x14637 - z = x14638 - z = x14639 - z = x14640 - z = x14641 - z = x14642 - z = x14643 - z = x14644 - z = x14645 - z = x14646 - z = x14647 - z = x14648 - z = x14649 - z = x14650 - z = x14651 - z = x14652 - z = x14653 - z = x14654 - z = x14655 - z = x14656 - z = x14657 - z = x14658 - z = x14659 - z = x14660 - z = x14661 - z = x14662 - z = x14663 - z = x14664 - z = x14665 - z = x14666 - z = x14667 - z = x14668 - z = x14669 - z = x14670 - z = x14671 - z = x14672 - z = x14673 - z = x14674 - z = x14675 - z = x14676 - z = x14677 - z = x14678 - z = x14679 - z = x14680 - z = x14681 - z = x14682 - z = x14683 - z = x14684 - z = x14685 - z = x14686 - z = x14687 - z = x14688 - z = x14689 - z = x14690 - z = x14691 - z = x14692 - z = x14693 - z = x14694 - z = x14695 - z = x14696 - z = x14697 - z = x14698 - z = x14699 - z = x14700 - z = x14701 - z = x14702 - z = x14703 - z = x14704 - z = x14705 - z = x14706 - z = x14707 - z = x14708 - z = x14709 - z = x14710 - z = x14711 - z = x14712 - z = x14713 - z = x14714 - z = x14715 - z = x14716 - z = x14717 - z = x14718 - z = x14719 - z = x14720 - z = x14721 - z = x14722 - z = x14723 - z = x14724 - z = x14725 - z = x14726 - z = x14727 - z = x14728 - z = x14729 - z = x14730 - z = x14731 - z = x14732 - z = x14733 - z = x14734 - z = x14735 - z = x14736 - z = x14737 - z = x14738 - z = x14739 - z = x14740 - z = x14741 - z = x14742 - z = x14743 - z = x14744 - z = x14745 - z = x14746 - z = x14747 - z = x14748 - z = x14749 - z = x14750 - z = x14751 - z = x14752 - z = x14753 - z = x14754 - z = x14755 - z = x14756 - z = x14757 - z = x14758 - z = x14759 - z = x14760 - z = x14761 - z = x14762 - z = x14763 - z = x14764 - z = x14765 - z = x14766 - z = x14767 - z = x14768 - z = x14769 - z = x14770 - z = x14771 - z = x14772 - z = x14773 - z = x14774 - z = x14775 - z = x14776 - z = x14777 - z = x14778 - z = x14779 - z = x14780 - z = x14781 - z = x14782 - z = x14783 - z = x14784 - z = x14785 - z = x14786 - z = x14787 - z = x14788 - z = x14789 - z = x14790 - z = x14791 - z = x14792 - z = x14793 - z = x14794 - z = x14795 - z = x14796 - z = x14797 - z = x14798 - z = x14799 - z = x14800 - z = x14801 - z = x14802 - z = x14803 - z = x14804 - z = x14805 - z = x14806 - z = x14807 - z = x14808 - z = x14809 - z = x14810 - z = x14811 - z = x14812 - z = x14813 - z = x14814 - z = x14815 - z = x14816 - z = x14817 - z = x14818 - z = x14819 - z = x14820 - z = x14821 - z = x14822 - z = x14823 - z = x14824 - z = x14825 - z = x14826 - z = x14827 - z = x14828 - z = x14829 - z = x14830 - z = x14831 - z = x14832 - z = x14833 - z = x14834 - z = x14835 - z = x14836 - z = x14837 - z = x14838 - z = x14839 - z = x14840 - z = x14841 - z = x14842 - z = x14843 - z = x14844 - z = x14845 - z = x14846 - z = x14847 - z = x14848 - z = x14849 - z = x14850 - z = x14851 - z = x14852 - z = x14853 - z = x14854 - z = x14855 - z = x14856 - z = x14857 - z = x14858 - z = x14859 - z = x14860 - z = x14861 - z = x14862 - z = x14863 - z = x14864 - z = x14865 - z = x14866 - z = x14867 - z = x14868 - z = x14869 - z = x14870 - z = x14871 - z = x14872 - z = x14873 - z = x14874 - z = x14875 - z = x14876 - z = x14877 - z = x14878 - z = x14879 - z = x14880 - z = x14881 - z = x14882 - z = x14883 - z = x14884 - z = x14885 - z = x14886 - z = x14887 - z = x14888 - z = x14889 - z = x14890 - z = x14891 - z = x14892 - z = x14893 - z = x14894 - z = x14895 - z = x14896 - z = x14897 - z = x14898 - z = x14899 - z = x14900 - z = x14901 - z = x14902 - z = x14903 - z = x14904 - z = x14905 - z = x14906 - z = x14907 - z = x14908 - z = x14909 - z = x14910 - z = x14911 - z = x14912 - z = x14913 - z = x14914 - z = x14915 - z = x14916 - z = x14917 - z = x14918 - z = x14919 - z = x14920 - z = x14921 - z = x14922 - z = x14923 - z = x14924 - z = x14925 - z = x14926 - z = x14927 - z = x14928 - z = x14929 - z = x14930 - z = x14931 - z = x14932 - z = x14933 - z = x14934 - z = x14935 - z = x14936 - z = x14937 - z = x14938 - z = x14939 - z = x14940 - z = x14941 - z = x14942 - z = x14943 - z = x14944 - z = x14945 - z = x14946 - z = x14947 - z = x14948 - z = x14949 - z = x14950 - z = x14951 - z = x14952 - z = x14953 - z = x14954 - z = x14955 - z = x14956 - z = x14957 - z = x14958 - z = x14959 - z = x14960 - z = x14961 - z = x14962 - z = x14963 - z = x14964 - z = x14965 - z = x14966 - z = x14967 - z = x14968 - z = x14969 - z = x14970 - z = x14971 - z = x14972 - z = x14973 - z = x14974 - z = x14975 - z = x14976 - z = x14977 - z = x14978 - z = x14979 - z = x14980 - z = x14981 - z = x14982 - z = x14983 - z = x14984 - z = x14985 - z = x14986 - z = x14987 - z = x14988 - z = x14989 - z = x14990 - z = x14991 - z = x14992 - z = x14993 - z = x14994 - z = x14995 - z = x14996 - z = x14997 - z = x14998 - z = x14999 - z = x15000 - z = x15001 - z = x15002 - z = x15003 - z = x15004 - z = x15005 - z = x15006 - z = x15007 - z = x15008 - z = x15009 - z = x15010 - z = x15011 - z = x15012 - z = x15013 - z = x15014 - z = x15015 - z = x15016 - z = x15017 - z = x15018 - z = x15019 - z = x15020 - z = x15021 - z = x15022 - z = x15023 - z = x15024 - z = x15025 - z = x15026 - z = x15027 - z = x15028 - z = x15029 - z = x15030 - z = x15031 - z = x15032 - z = x15033 - z = x15034 - z = x15035 - z = x15036 - z = x15037 - z = x15038 - z = x15039 - z = x15040 - z = x15041 - z = x15042 - z = x15043 - z = x15044 - z = x15045 - z = x15046 - z = x15047 - z = x15048 - z = x15049 - z = x15050 - z = x15051 - z = x15052 - z = x15053 - z = x15054 - z = x15055 - z = x15056 - z = x15057 - z = x15058 - z = x15059 - z = x15060 - z = x15061 - z = x15062 - z = x15063 - z = x15064 - z = x15065 - z = x15066 - z = x15067 - z = x15068 - z = x15069 - z = x15070 - z = x15071 - z = x15072 - z = x15073 - z = x15074 - z = x15075 - z = x15076 - z = x15077 - z = x15078 - z = x15079 - z = x15080 - z = x15081 - z = x15082 - z = x15083 - z = x15084 - z = x15085 - z = x15086 - z = x15087 - z = x15088 - z = x15089 - z = x15090 - z = x15091 - z = x15092 - z = x15093 - z = x15094 - z = x15095 - z = x15096 - z = x15097 - z = x15098 - z = x15099 - z = x15100 - z = x15101 - z = x15102 - z = x15103 - z = x15104 - z = x15105 - z = x15106 - z = x15107 - z = x15108 - z = x15109 - z = x15110 - z = x15111 - z = x15112 - z = x15113 - z = x15114 - z = x15115 - z = x15116 - z = x15117 - z = x15118 - z = x15119 - z = x15120 - z = x15121 - z = x15122 - z = x15123 - z = x15124 - z = x15125 - z = x15126 - z = x15127 - z = x15128 - z = x15129 - z = x15130 - z = x15131 - z = x15132 - z = x15133 - z = x15134 - z = x15135 - z = x15136 - z = x15137 - z = x15138 - z = x15139 - z = x15140 - z = x15141 - z = x15142 - z = x15143 - z = x15144 - z = x15145 - z = x15146 - z = x15147 - z = x15148 - z = x15149 - z = x15150 - z = x15151 - z = x15152 - z = x15153 - z = x15154 - z = x15155 - z = x15156 - z = x15157 - z = x15158 - z = x15159 - z = x15160 - z = x15161 - z = x15162 - z = x15163 - z = x15164 - z = x15165 - z = x15166 - z = x15167 - z = x15168 - z = x15169 - z = x15170 - z = x15171 - z = x15172 - z = x15173 - z = x15174 - z = x15175 - z = x15176 - z = x15177 - z = x15178 - z = x15179 - z = x15180 - z = x15181 - z = x15182 - z = x15183 - z = x15184 - z = x15185 - z = x15186 - z = x15187 - z = x15188 - z = x15189 - z = x15190 - z = x15191 - z = x15192 - z = x15193 - z = x15194 - z = x15195 - z = x15196 - z = x15197 - z = x15198 - z = x15199 - z = x15200 - z = x15201 - z = x15202 - z = x15203 - z = x15204 - z = x15205 - z = x15206 - z = x15207 - z = x15208 - z = x15209 - z = x15210 - z = x15211 - z = x15212 - z = x15213 - z = x15214 - z = x15215 - z = x15216 - z = x15217 - z = x15218 - z = x15219 - z = x15220 - z = x15221 - z = x15222 - z = x15223 - z = x15224 - z = x15225 - z = x15226 - z = x15227 - z = x15228 - z = x15229 - z = x15230 - z = x15231 - z = x15232 - z = x15233 - z = x15234 - z = x15235 - z = x15236 - z = x15237 - z = x15238 - z = x15239 - z = x15240 - z = x15241 - z = x15242 - z = x15243 - z = x15244 - z = x15245 - z = x15246 - z = x15247 - z = x15248 - z = x15249 - z = x15250 - z = x15251 - z = x15252 - z = x15253 - z = x15254 - z = x15255 - z = x15256 - z = x15257 - z = x15258 - z = x15259 - z = x15260 - z = x15261 - z = x15262 - z = x15263 - z = x15264 - z = x15265 - z = x15266 - z = x15267 - z = x15268 - z = x15269 - z = x15270 - z = x15271 - z = x15272 - z = x15273 - z = x15274 - z = x15275 - z = x15276 - z = x15277 - z = x15278 - z = x15279 - z = x15280 - z = x15281 - z = x15282 - z = x15283 - z = x15284 - z = x15285 - z = x15286 - z = x15287 - z = x15288 - z = x15289 - z = x15290 - z = x15291 - z = x15292 - z = x15293 - z = x15294 - z = x15295 - z = x15296 - z = x15297 - z = x15298 - z = x15299 - z = x15300 - z = x15301 - z = x15302 - z = x15303 - z = x15304 - z = x15305 - z = x15306 - z = x15307 - z = x15308 - z = x15309 - z = x15310 - z = x15311 - z = x15312 - z = x15313 - z = x15314 - z = x15315 - z = x15316 - z = x15317 - z = x15318 - z = x15319 - z = x15320 - z = x15321 - z = x15322 - z = x15323 - z = x15324 - z = x15325 - z = x15326 - z = x15327 - z = x15328 - z = x15329 - z = x15330 - z = x15331 - z = x15332 - z = x15333 - z = x15334 - z = x15335 - z = x15336 - z = x15337 - z = x15338 - z = x15339 - z = x15340 - z = x15341 - z = x15342 - z = x15343 - z = x15344 - z = x15345 - z = x15346 - z = x15347 - z = x15348 - z = x15349 - z = x15350 - z = x15351 - z = x15352 - z = x15353 - z = x15354 - z = x15355 - z = x15356 - z = x15357 - z = x15358 - z = x15359 - z = x15360 - z = x15361 - z = x15362 - z = x15363 - z = x15364 - z = x15365 - z = x15366 - z = x15367 - z = x15368 - z = x15369 - z = x15370 - z = x15371 - z = x15372 - z = x15373 - z = x15374 - z = x15375 - z = x15376 - z = x15377 - z = x15378 - z = x15379 - z = x15380 - z = x15381 - z = x15382 - z = x15383 - z = x15384 - z = x15385 - z = x15386 - z = x15387 - z = x15388 - z = x15389 - z = x15390 - z = x15391 - z = x15392 - z = x15393 - z = x15394 - z = x15395 - z = x15396 - z = x15397 - z = x15398 - z = x15399 - z = x15400 - z = x15401 - z = x15402 - z = x15403 - z = x15404 - z = x15405 - z = x15406 - z = x15407 - z = x15408 - z = x15409 - z = x15410 - z = x15411 - z = x15412 - z = x15413 - z = x15414 - z = x15415 - z = x15416 - z = x15417 - z = x15418 - z = x15419 - z = x15420 - z = x15421 - z = x15422 - z = x15423 - z = x15424 - z = x15425 - z = x15426 - z = x15427 - z = x15428 - z = x15429 - z = x15430 - z = x15431 - z = x15432 - z = x15433 - z = x15434 - z = x15435 - z = x15436 - z = x15437 - z = x15438 - z = x15439 - z = x15440 - z = x15441 - z = x15442 - z = x15443 - z = x15444 - z = x15445 - z = x15446 - z = x15447 - z = x15448 - z = x15449 - z = x15450 - z = x15451 - z = x15452 - z = x15453 - z = x15454 - z = x15455 - z = x15456 - z = x15457 - z = x15458 - z = x15459 - z = x15460 - z = x15461 - z = x15462 - z = x15463 - z = x15464 - z = x15465 - z = x15466 - z = x15467 - z = x15468 - z = x15469 - z = x15470 - z = x15471 - z = x15472 - z = x15473 - z = x15474 - z = x15475 - z = x15476 - z = x15477 - z = x15478 - z = x15479 - z = x15480 - z = x15481 - z = x15482 - z = x15483 - z = x15484 - z = x15485 - z = x15486 - z = x15487 - z = x15488 - z = x15489 - z = x15490 - z = x15491 - z = x15492 - z = x15493 - z = x15494 - z = x15495 - z = x15496 - z = x15497 - z = x15498 - z = x15499 - z = x15500 - z = x15501 - z = x15502 - z = x15503 - z = x15504 - z = x15505 - z = x15506 - z = x15507 - z = x15508 - z = x15509 - z = x15510 - z = x15511 - z = x15512 - z = x15513 - z = x15514 - z = x15515 - z = x15516 - z = x15517 - z = x15518 - z = x15519 - z = x15520 - z = x15521 - z = x15522 - z = x15523 - z = x15524 - z = x15525 - z = x15526 - z = x15527 - z = x15528 - z = x15529 - z = x15530 - z = x15531 - z = x15532 - z = x15533 - z = x15534 - z = x15535 - z = x15536 - z = x15537 - z = x15538 - z = x15539 - z = x15540 - z = x15541 - z = x15542 - z = x15543 - z = x15544 - z = x15545 - z = x15546 - z = x15547 - z = x15548 - z = x15549 - z = x15550 - z = x15551 - z = x15552 - z = x15553 - z = x15554 - z = x15555 - z = x15556 - z = x15557 - z = x15558 - z = x15559 - z = x15560 - z = x15561 - z = x15562 - z = x15563 - z = x15564 - z = x15565 - z = x15566 - z = x15567 - z = x15568 - z = x15569 - z = x15570 - z = x15571 - z = x15572 - z = x15573 - z = x15574 - z = x15575 - z = x15576 - z = x15577 - z = x15578 - z = x15579 - z = x15580 - z = x15581 - z = x15582 - z = x15583 - z = x15584 - z = x15585 - z = x15586 - z = x15587 - z = x15588 - z = x15589 - z = x15590 - z = x15591 - z = x15592 - z = x15593 - z = x15594 - z = x15595 - z = x15596 - z = x15597 - z = x15598 - z = x15599 - z = x15600 - z = x15601 - z = x15602 - z = x15603 - z = x15604 - z = x15605 - z = x15606 - z = x15607 - z = x15608 - z = x15609 - z = x15610 - z = x15611 - z = x15612 - z = x15613 - z = x15614 - z = x15615 - z = x15616 - z = x15617 - z = x15618 - z = x15619 - z = x15620 - z = x15621 - z = x15622 - z = x15623 - z = x15624 - z = x15625 - z = x15626 - z = x15627 - z = x15628 - z = x15629 - z = x15630 - z = x15631 - z = x15632 - z = x15633 - z = x15634 - z = x15635 - z = x15636 - z = x15637 - z = x15638 - z = x15639 - z = x15640 - z = x15641 - z = x15642 - z = x15643 - z = x15644 - z = x15645 - z = x15646 - z = x15647 - z = x15648 - z = x15649 - z = x15650 - z = x15651 - z = x15652 - z = x15653 - z = x15654 - z = x15655 - z = x15656 - z = x15657 - z = x15658 - z = x15659 - z = x15660 - z = x15661 - z = x15662 - z = x15663 - z = x15664 - z = x15665 - z = x15666 - z = x15667 - z = x15668 - z = x15669 - z = x15670 - z = x15671 - z = x15672 - z = x15673 - z = x15674 - z = x15675 - z = x15676 - z = x15677 - z = x15678 - z = x15679 - z = x15680 - z = x15681 - z = x15682 - z = x15683 - z = x15684 - z = x15685 - z = x15686 - z = x15687 - z = x15688 - z = x15689 - z = x15690 - z = x15691 - z = x15692 - z = x15693 - z = x15694 - z = x15695 - z = x15696 - z = x15697 - z = x15698 - z = x15699 - z = x15700 - z = x15701 - z = x15702 - z = x15703 - z = x15704 - z = x15705 - z = x15706 - z = x15707 - z = x15708 - z = x15709 - z = x15710 - z = x15711 - z = x15712 - z = x15713 - z = x15714 - z = x15715 - z = x15716 - z = x15717 - z = x15718 - z = x15719 - z = x15720 - z = x15721 - z = x15722 - z = x15723 - z = x15724 - z = x15725 - z = x15726 - z = x15727 - z = x15728 - z = x15729 - z = x15730 - z = x15731 - z = x15732 - z = x15733 - z = x15734 - z = x15735 - z = x15736 - z = x15737 - z = x15738 - z = x15739 - z = x15740 - z = x15741 - z = x15742 - z = x15743 - z = x15744 - z = x15745 - z = x15746 - z = x15747 - z = x15748 - z = x15749 - z = x15750 - z = x15751 - z = x15752 - z = x15753 - z = x15754 - z = x15755 - z = x15756 - z = x15757 - z = x15758 - z = x15759 - z = x15760 - z = x15761 - z = x15762 - z = x15763 - z = x15764 - z = x15765 - z = x15766 - z = x15767 - z = x15768 - z = x15769 - z = x15770 - z = x15771 - z = x15772 - z = x15773 - z = x15774 - z = x15775 - z = x15776 - z = x15777 - z = x15778 - z = x15779 - z = x15780 - z = x15781 - z = x15782 - z = x15783 - z = x15784 - z = x15785 - z = x15786 - z = x15787 - z = x15788 - z = x15789 - z = x15790 - z = x15791 - z = x15792 - z = x15793 - z = x15794 - z = x15795 - z = x15796 - z = x15797 - z = x15798 - z = x15799 - z = x15800 - z = x15801 - z = x15802 - z = x15803 - z = x15804 - z = x15805 - z = x15806 - z = x15807 - z = x15808 - z = x15809 - z = x15810 - z = x15811 - z = x15812 - z = x15813 - z = x15814 - z = x15815 - z = x15816 - z = x15817 - z = x15818 - z = x15819 - z = x15820 - z = x15821 - z = x15822 - z = x15823 - z = x15824 - z = x15825 - z = x15826 - z = x15827 - z = x15828 - z = x15829 - z = x15830 - z = x15831 - z = x15832 - z = x15833 - z = x15834 - z = x15835 - z = x15836 - z = x15837 - z = x15838 - z = x15839 - z = x15840 - z = x15841 - z = x15842 - z = x15843 - z = x15844 - z = x15845 - z = x15846 - z = x15847 - z = x15848 - z = x15849 - z = x15850 - z = x15851 - z = x15852 - z = x15853 - z = x15854 - z = x15855 - z = x15856 - z = x15857 - z = x15858 - z = x15859 - z = x15860 - z = x15861 - z = x15862 - z = x15863 - z = x15864 - z = x15865 - z = x15866 - z = x15867 - z = x15868 - z = x15869 - z = x15870 - z = x15871 - z = x15872 - z = x15873 - z = x15874 - z = x15875 - z = x15876 - z = x15877 - z = x15878 - z = x15879 - z = x15880 - z = x15881 - z = x15882 - z = x15883 - z = x15884 - z = x15885 - z = x15886 - z = x15887 - z = x15888 - z = x15889 - z = x15890 - z = x15891 - z = x15892 - z = x15893 - z = x15894 - z = x15895 - z = x15896 - z = x15897 - z = x15898 - z = x15899 - z = x15900 - z = x15901 - z = x15902 - z = x15903 - z = x15904 - z = x15905 - z = x15906 - z = x15907 - z = x15908 - z = x15909 - z = x15910 - z = x15911 - z = x15912 - z = x15913 - z = x15914 - z = x15915 - z = x15916 - z = x15917 - z = x15918 - z = x15919 - z = x15920 - z = x15921 - z = x15922 - z = x15923 - z = x15924 - z = x15925 - z = x15926 - z = x15927 - z = x15928 - z = x15929 - z = x15930 - z = x15931 - z = x15932 - z = x15933 - z = x15934 - z = x15935 - z = x15936 - z = x15937 - z = x15938 - z = x15939 - z = x15940 - z = x15941 - z = x15942 - z = x15943 - z = x15944 - z = x15945 - z = x15946 - z = x15947 - z = x15948 - z = x15949 - z = x15950 - z = x15951 - z = x15952 - z = x15953 - z = x15954 - z = x15955 - z = x15956 - z = x15957 - z = x15958 - z = x15959 - z = x15960 - z = x15961 - z = x15962 - z = x15963 - z = x15964 - z = x15965 - z = x15966 - z = x15967 - z = x15968 - z = x15969 - z = x15970 - z = x15971 - z = x15972 - z = x15973 - z = x15974 - z = x15975 - z = x15976 - z = x15977 - z = x15978 - z = x15979 - z = x15980 - z = x15981 - z = x15982 - z = x15983 - z = x15984 - z = x15985 - z = x15986 - z = x15987 - z = x15988 - z = x15989 - z = x15990 - z = x15991 - z = x15992 - z = x15993 - z = x15994 - z = x15995 - z = x15996 - z = x15997 - z = x15998 - z = x15999 - z = x16000 - z = x16001 - z = x16002 - z = x16003 - z = x16004 - z = x16005 - z = x16006 - z = x16007 - z = x16008 - z = x16009 - z = x16010 - z = x16011 - z = x16012 - z = x16013 - z = x16014 - z = x16015 - z = x16016 - z = x16017 - z = x16018 - z = x16019 - z = x16020 - z = x16021 - z = x16022 - z = x16023 - z = x16024 - z = x16025 - z = x16026 - z = x16027 - z = x16028 - z = x16029 - z = x16030 - z = x16031 - z = x16032 - z = x16033 - z = x16034 - z = x16035 - z = x16036 - z = x16037 - z = x16038 - z = x16039 - z = x16040 - z = x16041 - z = x16042 - z = x16043 - z = x16044 - z = x16045 - z = x16046 - z = x16047 - z = x16048 - z = x16049 - z = x16050 - z = x16051 - z = x16052 - z = x16053 - z = x16054 - z = x16055 - z = x16056 - z = x16057 - z = x16058 - z = x16059 - z = x16060 - z = x16061 - z = x16062 - z = x16063 - z = x16064 - z = x16065 - z = x16066 - z = x16067 - z = x16068 - z = x16069 - z = x16070 - z = x16071 - z = x16072 - z = x16073 - z = x16074 - z = x16075 - z = x16076 - z = x16077 - z = x16078 - z = x16079 - z = x16080 - z = x16081 - z = x16082 - z = x16083 - z = x16084 - z = x16085 - z = x16086 - z = x16087 - z = x16088 - z = x16089 - z = x16090 - z = x16091 - z = x16092 - z = x16093 - z = x16094 - z = x16095 - z = x16096 - z = x16097 - z = x16098 - z = x16099 - z = x16100 - z = x16101 - z = x16102 - z = x16103 - z = x16104 - z = x16105 - z = x16106 - z = x16107 - z = x16108 - z = x16109 - z = x16110 - z = x16111 - z = x16112 - z = x16113 - z = x16114 - z = x16115 - z = x16116 - z = x16117 - z = x16118 - z = x16119 - z = x16120 - z = x16121 - z = x16122 - z = x16123 - z = x16124 - z = x16125 - z = x16126 - z = x16127 - z = x16128 - z = x16129 - z = x16130 - z = x16131 - z = x16132 - z = x16133 - z = x16134 - z = x16135 - z = x16136 - z = x16137 - z = x16138 - z = x16139 - z = x16140 - z = x16141 - z = x16142 - z = x16143 - z = x16144 - z = x16145 - z = x16146 - z = x16147 - z = x16148 - z = x16149 - z = x16150 - z = x16151 - z = x16152 - z = x16153 - z = x16154 - z = x16155 - z = x16156 - z = x16157 - z = x16158 - z = x16159 - z = x16160 - z = x16161 - z = x16162 - z = x16163 - z = x16164 - z = x16165 - z = x16166 - z = x16167 - z = x16168 - z = x16169 - z = x16170 - z = x16171 - z = x16172 - z = x16173 - z = x16174 - z = x16175 - z = x16176 - z = x16177 - z = x16178 - z = x16179 - z = x16180 - z = x16181 - z = x16182 - z = x16183 - z = x16184 - z = x16185 - z = x16186 - z = x16187 - z = x16188 - z = x16189 - z = x16190 - z = x16191 - z = x16192 - z = x16193 - z = x16194 - z = x16195 - z = x16196 - z = x16197 - z = x16198 - z = x16199 - z = x16200 - z = x16201 - z = x16202 - z = x16203 - z = x16204 - z = x16205 - z = x16206 - z = x16207 - z = x16208 - z = x16209 - z = x16210 - z = x16211 - z = x16212 - z = x16213 - z = x16214 - z = x16215 - z = x16216 - z = x16217 - z = x16218 - z = x16219 - z = x16220 - z = x16221 - z = x16222 - z = x16223 - z = x16224 - z = x16225 - z = x16226 - z = x16227 - z = x16228 - z = x16229 - z = x16230 - z = x16231 - z = x16232 - z = x16233 - z = x16234 - z = x16235 - z = x16236 - z = x16237 - z = x16238 - z = x16239 - z = x16240 - z = x16241 - z = x16242 - z = x16243 - z = x16244 - z = x16245 - z = x16246 - z = x16247 - z = x16248 - z = x16249 - z = x16250 - z = x16251 - z = x16252 - z = x16253 - z = x16254 - z = x16255 - z = x16256 - z = x16257 - z = x16258 - z = x16259 - z = x16260 - z = x16261 - z = x16262 - z = x16263 - z = x16264 - z = x16265 - z = x16266 - z = x16267 - z = x16268 - z = x16269 - z = x16270 - z = x16271 - z = x16272 - z = x16273 - z = x16274 - z = x16275 - z = x16276 - z = x16277 - z = x16278 - z = x16279 - z = x16280 - z = x16281 - z = x16282 - z = x16283 - z = x16284 - z = x16285 - z = x16286 - z = x16287 - z = x16288 - z = x16289 - z = x16290 - z = x16291 - z = x16292 - z = x16293 - z = x16294 - z = x16295 - z = x16296 - z = x16297 - z = x16298 - z = x16299 - z = x16300 - z = x16301 - z = x16302 - z = x16303 - z = x16304 - z = x16305 - z = x16306 - z = x16307 - z = x16308 - z = x16309 - z = x16310 - z = x16311 - z = x16312 - z = x16313 - z = x16314 - z = x16315 - z = x16316 - z = x16317 - z = x16318 - z = x16319 - z = x16320 - z = x16321 - z = x16322 - z = x16323 - z = x16324 - z = x16325 - z = x16326 - z = x16327 - z = x16328 - z = x16329 - z = x16330 - z = x16331 - z = x16332 - z = x16333 - z = x16334 - z = x16335 - z = x16336 - z = x16337 - z = x16338 - z = x16339 - z = x16340 - z = x16341 - z = x16342 - z = x16343 - z = x16344 - z = x16345 - z = x16346 - z = x16347 - z = x16348 - z = x16349 - z = x16350 - z = x16351 - z = x16352 - z = x16353 - z = x16354 - z = x16355 - z = x16356 - z = x16357 - z = x16358 - z = x16359 - z = x16360 - z = x16361 - z = x16362 - z = x16363 - z = x16364 - z = x16365 - z = x16366 - z = x16367 - z = x16368 - z = x16369 - z = x16370 - z = x16371 - z = x16372 - z = x16373 - z = x16374 - z = x16375 - z = x16376 - z = x16377 - z = x16378 - z = x16379 - z = x16380 - z = x16381 - z = x16382 - z = x16383 - z = x16384 - z = x16385 - z = x16386 - z = x16387 - z = x16388 - z = x16389 - z = x16390 - z = x16391 - z = x16392 - z = x16393 - z = x16394 - z = x16395 - z = x16396 - z = x16397 - z = x16398 - z = x16399 - z = x16400 - z = x16401 - z = x16402 - z = x16403 - z = x16404 - z = x16405 - z = x16406 - z = x16407 - z = x16408 - z = x16409 - z = x16410 - z = x16411 - z = x16412 - z = x16413 - z = x16414 - z = x16415 - z = x16416 - z = x16417 - z = x16418 - z = x16419 - z = x16420 - z = x16421 - z = x16422 - z = x16423 - z = x16424 - z = x16425 - z = x16426 - z = x16427 - z = x16428 - z = x16429 - z = x16430 - z = x16431 - z = x16432 - z = x16433 - z = x16434 - z = x16435 - z = x16436 - z = x16437 - z = x16438 - z = x16439 - z = x16440 - z = x16441 - z = x16442 - z = x16443 - z = x16444 - z = x16445 - z = x16446 - z = x16447 - z = x16448 - z = x16449 - z = x16450 - z = x16451 - z = x16452 - z = x16453 - z = x16454 - z = x16455 - z = x16456 - z = x16457 - z = x16458 - z = x16459 - z = x16460 - z = x16461 - z = x16462 - z = x16463 - z = x16464 - z = x16465 - z = x16466 - z = x16467 - z = x16468 - z = x16469 - z = x16470 - z = x16471 - z = x16472 - z = x16473 - z = x16474 - z = x16475 - z = x16476 - z = x16477 - z = x16478 - z = x16479 - z = x16480 + z1 = x1 + z2 = x2 + z3 = x3 + z4 = x4 + z5 = x5 + z6 = x6 + z7 = x7 + z8 = x8 + z9 = x9 + z10 = x10 + z11 = x11 + z12 = x12 + z13 = x13 + z14 = x14 + z15 = x15 + z16 = x16 + z17 = x17 + z18 = x18 + z19 = x19 + z20 = x20 + z21 = x21 + z22 = x22 + z23 = x23 + z24 = x24 + z25 = x25 + z26 = x26 + z27 = x27 + z28 = x28 + z29 = x29 + z30 = x30 + z31 = x31 + z32 = x32 + z33 = x33 + z34 = x34 + z35 = x35 + z36 = x36 + z37 = x37 + z38 = x38 + z39 = x39 + z40 = x40 + z41 = x41 + z42 = x42 + z43 = x43 + z44 = x44 + z45 = x45 + z46 = x46 + z47 = x47 + z48 = x48 + z49 = x49 + z50 = x50 + z51 = x51 + z52 = x52 + z53 = x53 + z54 = x54 + z55 = x55 + z56 = x56 + z57 = x57 + z58 = x58 + z59 = x59 + z60 = x60 + z61 = x61 + z62 = x62 + z63 = x63 + z64 = x64 + z65 = x65 + z66 = x66 + z67 = x67 + z68 = x68 + z69 = x69 + z70 = x70 + z71 = x71 + z72 = x72 + z73 = x73 + z74 = x74 + z75 = x75 + z76 = x76 + z77 = x77 + z78 = x78 + z79 = x79 + z80 = x80 + z81 = x81 + z82 = x82 + z83 = x83 + z84 = x84 + z85 = x85 + z86 = x86 + z87 = x87 + z88 = x88 + z89 = x89 + z90 = x90 + z91 = x91 + z92 = x92 + z93 = x93 + z94 = x94 + z95 = x95 + z96 = x96 + z97 = x97 + z98 = x98 + z99 = x99 + z100 = x100 + z101 = x101 + z102 = x102 + z103 = x103 + z104 = x104 + z105 = x105 + z106 = x106 + z107 = x107 + z108 = x108 + z109 = x109 + z110 = x110 + z111 = x111 + z112 = x112 + z113 = x113 + z114 = x114 + z115 = x115 + z116 = x116 + z117 = x117 + z118 = x118 + z119 = x119 + z120 = x120 + z121 = x121 + z122 = x122 + z123 = x123 + z124 = x124 + z125 = x125 + z126 = x126 + z127 = x127 + z128 = x128 + z129 = x129 + z130 = x130 + z131 = x131 + z132 = x132 + z133 = x133 + z134 = x134 + z135 = x135 + z136 = x136 + z137 = x137 + z138 = x138 + z139 = x139 + z140 = x140 + z141 = x141 + z142 = x142 + z143 = x143 + z144 = x144 + z145 = x145 + z146 = x146 + z147 = x147 + z148 = x148 + z149 = x149 + z150 = x150 + z151 = x151 + z152 = x152 + z153 = x153 + z154 = x154 + z155 = x155 + z156 = x156 + z157 = x157 + z158 = x158 + z159 = x159 + z160 = x160 + z161 = x161 + z162 = x162 + z163 = x163 + z164 = x164 + z165 = x165 + z166 = x166 + z167 = x167 + z168 = x168 + z169 = x169 + z170 = x170 + z171 = x171 + z172 = x172 + z173 = x173 + z174 = x174 + z175 = x175 + z176 = x176 + z177 = x177 + z178 = x178 + z179 = x179 + z180 = x180 + z181 = x181 + z182 = x182 + z183 = x183 + z184 = x184 + z185 = x185 + z186 = x186 + z187 = x187 + z188 = x188 + z189 = x189 + z190 = x190 + z191 = x191 + z192 = x192 + z193 = x193 + z194 = x194 + z195 = x195 + z196 = x196 + z197 = x197 + z198 = x198 + z199 = x199 + z200 = x200 + z201 = x201 + z202 = x202 + z203 = x203 + z204 = x204 + z205 = x205 + z206 = x206 + z207 = x207 + z208 = x208 + z209 = x209 + z210 = x210 + z211 = x211 + z212 = x212 + z213 = x213 + z214 = x214 + z215 = x215 + z216 = x216 + z217 = x217 + z218 = x218 + z219 = x219 + z220 = x220 + z221 = x221 + z222 = x222 + z223 = x223 + z224 = x224 + z225 = x225 + z226 = x226 + z227 = x227 + z228 = x228 + z229 = x229 + z230 = x230 + z231 = x231 + z232 = x232 + z233 = x233 + z234 = x234 + z235 = x235 + z236 = x236 + z237 = x237 + z238 = x238 + z239 = x239 + z240 = x240 + z241 = x241 + z242 = x242 + z243 = x243 + z244 = x244 + z245 = x245 + z246 = x246 + z247 = x247 + z248 = x248 + z249 = x249 + z250 = x250 + z251 = x251 + z252 = x252 + z253 = x253 + z254 = x254 + z255 = x255 + z256 = x256 + z257 = x257 + z258 = x258 + z259 = x259 + z260 = x260 + z261 = x261 + z262 = x262 + z263 = x263 + z264 = x264 + z265 = x265 + z266 = x266 + z267 = x267 + z268 = x268 + z269 = x269 + z270 = x270 + z271 = x271 + z272 = x272 + z273 = x273 + z274 = x274 + z275 = x275 + z276 = x276 + z277 = x277 + z278 = x278 + z279 = x279 + z280 = x280 + z281 = x281 + z282 = x282 + z283 = x283 + z284 = x284 + z285 = x285 + z286 = x286 + z287 = x287 + z288 = x288 + z289 = x289 + z290 = x290 + z291 = x291 + z292 = x292 + z293 = x293 + z294 = x294 + z295 = x295 + z296 = x296 + z297 = x297 + z298 = x298 + z299 = x299 + z300 = x300 + z301 = x301 + z302 = x302 + z303 = x303 + z304 = x304 + z305 = x305 + z306 = x306 + z307 = x307 + z308 = x308 + z309 = x309 + z310 = x310 + z311 = x311 + z312 = x312 + z313 = x313 + z314 = x314 + z315 = x315 + z316 = x316 + z317 = x317 + z318 = x318 + z319 = x319 + z320 = x320 + z321 = x321 + z322 = x322 + z323 = x323 + z324 = x324 + z325 = x325 + z326 = x326 + z327 = x327 + z328 = x328 + z329 = x329 + z330 = x330 + z331 = x331 + z332 = x332 + z333 = x333 + z334 = x334 + z335 = x335 + z336 = x336 + z337 = x337 + z338 = x338 + z339 = x339 + z340 = x340 + z341 = x341 + z342 = x342 + z343 = x343 + z344 = x344 + z345 = x345 + z346 = x346 + z347 = x347 + z348 = x348 + z349 = x349 + z350 = x350 + z351 = x351 + z352 = x352 + z353 = x353 + z354 = x354 + z355 = x355 + z356 = x356 + z357 = x357 + z358 = x358 + z359 = x359 + z360 = x360 + z361 = x361 + z362 = x362 + z363 = x363 + z364 = x364 + z365 = x365 + z366 = x366 + z367 = x367 + z368 = x368 + z369 = x369 + z370 = x370 + z371 = x371 + z372 = x372 + z373 = x373 + z374 = x374 + z375 = x375 + z376 = x376 + z377 = x377 + z378 = x378 + z379 = x379 + z380 = x380 + z381 = x381 + z382 = x382 + z383 = x383 + z384 = x384 + z385 = x385 + z386 = x386 + z387 = x387 + z388 = x388 + z389 = x389 + z390 = x390 + z391 = x391 + z392 = x392 + z393 = x393 + z394 = x394 + z395 = x395 + z396 = x396 + z397 = x397 + z398 = x398 + z399 = x399 + z400 = x400 + z401 = x401 + z402 = x402 + z403 = x403 + z404 = x404 + z405 = x405 + z406 = x406 + z407 = x407 + z408 = x408 + z409 = x409 + z410 = x410 + z411 = x411 + z412 = x412 + z413 = x413 + z414 = x414 + z415 = x415 + z416 = x416 + z417 = x417 + z418 = x418 + z419 = x419 + z420 = x420 + z421 = x421 + z422 = x422 + z423 = x423 + z424 = x424 + z425 = x425 + z426 = x426 + z427 = x427 + z428 = x428 + z429 = x429 + z430 = x430 + z431 = x431 + z432 = x432 + z433 = x433 + z434 = x434 + z435 = x435 + z436 = x436 + z437 = x437 + z438 = x438 + z439 = x439 + z440 = x440 + z441 = x441 + z442 = x442 + z443 = x443 + z444 = x444 + z445 = x445 + z446 = x446 + z447 = x447 + z448 = x448 + z449 = x449 + z450 = x450 + z451 = x451 + z452 = x452 + z453 = x453 + z454 = x454 + z455 = x455 + z456 = x456 + z457 = x457 + z458 = x458 + z459 = x459 + z460 = x460 + z461 = x461 + z462 = x462 + z463 = x463 + z464 = x464 + z465 = x465 + z466 = x466 + z467 = x467 + z468 = x468 + z469 = x469 + z470 = x470 + z471 = x471 + z472 = x472 + z473 = x473 + z474 = x474 + z475 = x475 + z476 = x476 + z477 = x477 + z478 = x478 + z479 = x479 + z480 = x480 + z481 = x481 + z482 = x482 + z483 = x483 + z484 = x484 + z485 = x485 + z486 = x486 + z487 = x487 + z488 = x488 + z489 = x489 + z490 = x490 + z491 = x491 + z492 = x492 + z493 = x493 + z494 = x494 + z495 = x495 + z496 = x496 + z497 = x497 + z498 = x498 + z499 = x499 + z500 = x500 + z501 = x501 + z502 = x502 + z503 = x503 + z504 = x504 + z505 = x505 + z506 = x506 + z507 = x507 + z508 = x508 + z509 = x509 + z510 = x510 + z511 = x511 + z512 = x512 + z513 = x513 + z514 = x514 + z515 = x515 + z516 = x516 + z517 = x517 + z518 = x518 + z519 = x519 + z520 = x520 + z521 = x521 + z522 = x522 + z523 = x523 + z524 = x524 + z525 = x525 + z526 = x526 + z527 = x527 + z528 = x528 + z529 = x529 + z530 = x530 + z531 = x531 + z532 = x532 + z533 = x533 + z534 = x534 + z535 = x535 + z536 = x536 + z537 = x537 + z538 = x538 + z539 = x539 + z540 = x540 + z541 = x541 + z542 = x542 + z543 = x543 + z544 = x544 + z545 = x545 + z546 = x546 + z547 = x547 + z548 = x548 + z549 = x549 + z550 = x550 + z551 = x551 + z552 = x552 + z553 = x553 + z554 = x554 + z555 = x555 + z556 = x556 + z557 = x557 + z558 = x558 + z559 = x559 + z560 = x560 + z561 = x561 + z562 = x562 + z563 = x563 + z564 = x564 + z565 = x565 + z566 = x566 + z567 = x567 + z568 = x568 + z569 = x569 + z570 = x570 + z571 = x571 + z572 = x572 + z573 = x573 + z574 = x574 + z575 = x575 + z576 = x576 + z577 = x577 + z578 = x578 + z579 = x579 + z580 = x580 + z581 = x581 + z582 = x582 + z583 = x583 + z584 = x584 + z585 = x585 + z586 = x586 + z587 = x587 + z588 = x588 + z589 = x589 + z590 = x590 + z591 = x591 + z592 = x592 + z593 = x593 + z594 = x594 + z595 = x595 + z596 = x596 + z597 = x597 + z598 = x598 + z599 = x599 + z600 = x600 + z601 = x601 + z602 = x602 + z603 = x603 + z604 = x604 + z605 = x605 + z606 = x606 + z607 = x607 + z608 = x608 + z609 = x609 + z610 = x610 + z611 = x611 + z612 = x612 + z613 = x613 + z614 = x614 + z615 = x615 + z616 = x616 + z617 = x617 + z618 = x618 + z619 = x619 + z620 = x620 + z621 = x621 + z622 = x622 + z623 = x623 + z624 = x624 + z625 = x625 + z626 = x626 + z627 = x627 + z628 = x628 + z629 = x629 + z630 = x630 + z631 = x631 + z632 = x632 + z633 = x633 + z634 = x634 + z635 = x635 + z636 = x636 + z637 = x637 + z638 = x638 + z639 = x639 + z640 = x640 + z641 = x641 + z642 = x642 + z643 = x643 + z644 = x644 + z645 = x645 + z646 = x646 + z647 = x647 + z648 = x648 + z649 = x649 + z650 = x650 + z651 = x651 + z652 = x652 + z653 = x653 + z654 = x654 + z655 = x655 + z656 = x656 + z657 = x657 + z658 = x658 + z659 = x659 + z660 = x660 + z661 = x661 + z662 = x662 + z663 = x663 + z664 = x664 + z665 = x665 + z666 = x666 + z667 = x667 + z668 = x668 + z669 = x669 + z670 = x670 + z671 = x671 + z672 = x672 + z673 = x673 + z674 = x674 + z675 = x675 + z676 = x676 + z677 = x677 + z678 = x678 + z679 = x679 + z680 = x680 + z681 = x681 + z682 = x682 + z683 = x683 + z684 = x684 + z685 = x685 + z686 = x686 + z687 = x687 + z688 = x688 + z689 = x689 + z690 = x690 + z691 = x691 + z692 = x692 + z693 = x693 + z694 = x694 + z695 = x695 + z696 = x696 + z697 = x697 + z698 = x698 + z699 = x699 + z700 = x700 + z701 = x701 + z702 = x702 + z703 = x703 + z704 = x704 + z705 = x705 + z706 = x706 + z707 = x707 + z708 = x708 + z709 = x709 + z710 = x710 + z711 = x711 + z712 = x712 + z713 = x713 + z714 = x714 + z715 = x715 + z716 = x716 + z717 = x717 + z718 = x718 + z719 = x719 + z720 = x720 + z721 = x721 + z722 = x722 + z723 = x723 + z724 = x724 + z725 = x725 + z726 = x726 + z727 = x727 + z728 = x728 + z729 = x729 + z730 = x730 + z731 = x731 + z732 = x732 + z733 = x733 + z734 = x734 + z735 = x735 + z736 = x736 + z737 = x737 + z738 = x738 + z739 = x739 + z740 = x740 + z741 = x741 + z742 = x742 + z743 = x743 + z744 = x744 + z745 = x745 + z746 = x746 + z747 = x747 + z748 = x748 + z749 = x749 + z750 = x750 + z751 = x751 + z752 = x752 + z753 = x753 + z754 = x754 + z755 = x755 + z756 = x756 + z757 = x757 + z758 = x758 + z759 = x759 + z760 = x760 + z761 = x761 + z762 = x762 + z763 = x763 + z764 = x764 + z765 = x765 + z766 = x766 + z767 = x767 + z768 = x768 + z769 = x769 + z770 = x770 + z771 = x771 + z772 = x772 + z773 = x773 + z774 = x774 + z775 = x775 + z776 = x776 + z777 = x777 + z778 = x778 + z779 = x779 + z780 = x780 + z781 = x781 + z782 = x782 + z783 = x783 + z784 = x784 + z785 = x785 + z786 = x786 + z787 = x787 + z788 = x788 + z789 = x789 + z790 = x790 + z791 = x791 + z792 = x792 + z793 = x793 + z794 = x794 + z795 = x795 + z796 = x796 + z797 = x797 + z798 = x798 + z799 = x799 + z800 = x800 + z801 = x801 + z802 = x802 + z803 = x803 + z804 = x804 + z805 = x805 + z806 = x806 + z807 = x807 + z808 = x808 + z809 = x809 + z810 = x810 + z811 = x811 + z812 = x812 + z813 = x813 + z814 = x814 + z815 = x815 + z816 = x816 + z817 = x817 + z818 = x818 + z819 = x819 + z820 = x820 + z821 = x821 + z822 = x822 + z823 = x823 + z824 = x824 + z825 = x825 + z826 = x826 + z827 = x827 + z828 = x828 + z829 = x829 + z830 = x830 + z831 = x831 + z832 = x832 + z833 = x833 + z834 = x834 + z835 = x835 + z836 = x836 + z837 = x837 + z838 = x838 + z839 = x839 + z840 = x840 + z841 = x841 + z842 = x842 + z843 = x843 + z844 = x844 + z845 = x845 + z846 = x846 + z847 = x847 + z848 = x848 + z849 = x849 + z850 = x850 + z851 = x851 + z852 = x852 + z853 = x853 + z854 = x854 + z855 = x855 + z856 = x856 + z857 = x857 + z858 = x858 + z859 = x859 + z860 = x860 + z861 = x861 + z862 = x862 + z863 = x863 + z864 = x864 + z865 = x865 + z866 = x866 + z867 = x867 + z868 = x868 + z869 = x869 + z870 = x870 + z871 = x871 + z872 = x872 + z873 = x873 + z874 = x874 + z875 = x875 + z876 = x876 + z877 = x877 + z878 = x878 + z879 = x879 + z880 = x880 + z881 = x881 + z882 = x882 + z883 = x883 + z884 = x884 + z885 = x885 + z886 = x886 + z887 = x887 + z888 = x888 + z889 = x889 + z890 = x890 + z891 = x891 + z892 = x892 + z893 = x893 + z894 = x894 + z895 = x895 + z896 = x896 + z897 = x897 + z898 = x898 + z899 = x899 + z900 = x900 + z901 = x901 + z902 = x902 + z903 = x903 + z904 = x904 + z905 = x905 + z906 = x906 + z907 = x907 + z908 = x908 + z909 = x909 + z910 = x910 + z911 = x911 + z912 = x912 + z913 = x913 + z914 = x914 + z915 = x915 + z916 = x916 + z917 = x917 + z918 = x918 + z919 = x919 + z920 = x920 + z921 = x921 + z922 = x922 + z923 = x923 + z924 = x924 + z925 = x925 + z926 = x926 + z927 = x927 + z928 = x928 + z929 = x929 + z930 = x930 + z931 = x931 + z932 = x932 + z933 = x933 + z934 = x934 + z935 = x935 + z936 = x936 + z937 = x937 + z938 = x938 + z939 = x939 + z940 = x940 + z941 = x941 + z942 = x942 + z943 = x943 + z944 = x944 + z945 = x945 + z946 = x946 + z947 = x947 + z948 = x948 + z949 = x949 + z950 = x950 + z951 = x951 + z952 = x952 + z953 = x953 + z954 = x954 + z955 = x955 + z956 = x956 + z957 = x957 + z958 = x958 + z959 = x959 + z960 = x960 + z961 = x961 + z962 = x962 + z963 = x963 + z964 = x964 + z965 = x965 + z966 = x966 + z967 = x967 + z968 = x968 + z969 = x969 + z970 = x970 + z971 = x971 + z972 = x972 + z973 = x973 + z974 = x974 + z975 = x975 + z976 = x976 + z977 = x977 + z978 = x978 + z979 = x979 + z980 = x980 + z981 = x981 + z982 = x982 + z983 = x983 + z984 = x984 + z985 = x985 + z986 = x986 + z987 = x987 + z988 = x988 + z989 = x989 + z990 = x990 + z991 = x991 + z992 = x992 + z993 = x993 + z994 = x994 + z995 = x995 + z996 = x996 + z997 = x997 + z998 = x998 + z999 = x999 + z1000 = x1000 + z1001 = x1001 + z1002 = x1002 + z1003 = x1003 + z1004 = x1004 + z1005 = x1005 + z1006 = x1006 + z1007 = x1007 + z1008 = x1008 + z1009 = x1009 + z1010 = x1010 + z1011 = x1011 + z1012 = x1012 + z1013 = x1013 + z1014 = x1014 + z1015 = x1015 + z1016 = x1016 + z1017 = x1017 + z1018 = x1018 + z1019 = x1019 + z1020 = x1020 + z1021 = x1021 + z1022 = x1022 + z1023 = x1023 + z1024 = x1024 + z1025 = x1025 + z1026 = x1026 + z1027 = x1027 + z1028 = x1028 + z1029 = x1029 + z1030 = x1030 + z1031 = x1031 + z1032 = x1032 + z1033 = x1033 + z1034 = x1034 + z1035 = x1035 + z1036 = x1036 + z1037 = x1037 + z1038 = x1038 + z1039 = x1039 + z1040 = x1040 + z1041 = x1041 + z1042 = x1042 + z1043 = x1043 + z1044 = x1044 + z1045 = x1045 + z1046 = x1046 + z1047 = x1047 + z1048 = x1048 + z1049 = x1049 + z1050 = x1050 + z1051 = x1051 + z1052 = x1052 + z1053 = x1053 + z1054 = x1054 + z1055 = x1055 + z1056 = x1056 + z1057 = x1057 + z1058 = x1058 + z1059 = x1059 + z1060 = x1060 + z1061 = x1061 + z1062 = x1062 + z1063 = x1063 + z1064 = x1064 + z1065 = x1065 + z1066 = x1066 + z1067 = x1067 + z1068 = x1068 + z1069 = x1069 + z1070 = x1070 + z1071 = x1071 + z1072 = x1072 + z1073 = x1073 + z1074 = x1074 + z1075 = x1075 + z1076 = x1076 + z1077 = x1077 + z1078 = x1078 + z1079 = x1079 + z1080 = x1080 + z1081 = x1081 + z1082 = x1082 + z1083 = x1083 + z1084 = x1084 + z1085 = x1085 + z1086 = x1086 + z1087 = x1087 + z1088 = x1088 + z1089 = x1089 + z1090 = x1090 + z1091 = x1091 + z1092 = x1092 + z1093 = x1093 + z1094 = x1094 + z1095 = x1095 + z1096 = x1096 + z1097 = x1097 + z1098 = x1098 + z1099 = x1099 + z1100 = x1100 + z1101 = x1101 + z1102 = x1102 + z1103 = x1103 + z1104 = x1104 + z1105 = x1105 + z1106 = x1106 + z1107 = x1107 + z1108 = x1108 + z1109 = x1109 + z1110 = x1110 + z1111 = x1111 + z1112 = x1112 + z1113 = x1113 + z1114 = x1114 + z1115 = x1115 + z1116 = x1116 + z1117 = x1117 + z1118 = x1118 + z1119 = x1119 + z1120 = x1120 + z1121 = x1121 + z1122 = x1122 + z1123 = x1123 + z1124 = x1124 + z1125 = x1125 + z1126 = x1126 + z1127 = x1127 + z1128 = x1128 + z1129 = x1129 + z1130 = x1130 + z1131 = x1131 + z1132 = x1132 + z1133 = x1133 + z1134 = x1134 + z1135 = x1135 + z1136 = x1136 + z1137 = x1137 + z1138 = x1138 + z1139 = x1139 + z1140 = x1140 + z1141 = x1141 + z1142 = x1142 + z1143 = x1143 + z1144 = x1144 + z1145 = x1145 + z1146 = x1146 + z1147 = x1147 + z1148 = x1148 + z1149 = x1149 + z1150 = x1150 + z1151 = x1151 + z1152 = x1152 + z1153 = x1153 + z1154 = x1154 + z1155 = x1155 + z1156 = x1156 + z1157 = x1157 + z1158 = x1158 + z1159 = x1159 + z1160 = x1160 + z1161 = x1161 + z1162 = x1162 + z1163 = x1163 + z1164 = x1164 + z1165 = x1165 + z1166 = x1166 + z1167 = x1167 + z1168 = x1168 + z1169 = x1169 + z1170 = x1170 + z1171 = x1171 + z1172 = x1172 + z1173 = x1173 + z1174 = x1174 + z1175 = x1175 + z1176 = x1176 + z1177 = x1177 + z1178 = x1178 + z1179 = x1179 + z1180 = x1180 + z1181 = x1181 + z1182 = x1182 + z1183 = x1183 + z1184 = x1184 + z1185 = x1185 + z1186 = x1186 + z1187 = x1187 + z1188 = x1188 + z1189 = x1189 + z1190 = x1190 + z1191 = x1191 + z1192 = x1192 + z1193 = x1193 + z1194 = x1194 + z1195 = x1195 + z1196 = x1196 + z1197 = x1197 + z1198 = x1198 + z1199 = x1199 + z1200 = x1200 + z1201 = x1201 + z1202 = x1202 + z1203 = x1203 + z1204 = x1204 + z1205 = x1205 + z1206 = x1206 + z1207 = x1207 + z1208 = x1208 + z1209 = x1209 + z1210 = x1210 + z1211 = x1211 + z1212 = x1212 + z1213 = x1213 + z1214 = x1214 + z1215 = x1215 + z1216 = x1216 + z1217 = x1217 + z1218 = x1218 + z1219 = x1219 + z1220 = x1220 + z1221 = x1221 + z1222 = x1222 + z1223 = x1223 + z1224 = x1224 + z1225 = x1225 + z1226 = x1226 + z1227 = x1227 + z1228 = x1228 + z1229 = x1229 + z1230 = x1230 + z1231 = x1231 + z1232 = x1232 + z1233 = x1233 + z1234 = x1234 + z1235 = x1235 + z1236 = x1236 + z1237 = x1237 + z1238 = x1238 + z1239 = x1239 + z1240 = x1240 + z1241 = x1241 + z1242 = x1242 + z1243 = x1243 + z1244 = x1244 + z1245 = x1245 + z1246 = x1246 + z1247 = x1247 + z1248 = x1248 + z1249 = x1249 + z1250 = x1250 + z1251 = x1251 + z1252 = x1252 + z1253 = x1253 + z1254 = x1254 + z1255 = x1255 + z1256 = x1256 + z1257 = x1257 + z1258 = x1258 + z1259 = x1259 + z1260 = x1260 + z1261 = x1261 + z1262 = x1262 + z1263 = x1263 + z1264 = x1264 + z1265 = x1265 + z1266 = x1266 + z1267 = x1267 + z1268 = x1268 + z1269 = x1269 + z1270 = x1270 + z1271 = x1271 + z1272 = x1272 + z1273 = x1273 + z1274 = x1274 + z1275 = x1275 + z1276 = x1276 + z1277 = x1277 + z1278 = x1278 + z1279 = x1279 + z1280 = x1280 + z1281 = x1281 + z1282 = x1282 + z1283 = x1283 + z1284 = x1284 + z1285 = x1285 + z1286 = x1286 + z1287 = x1287 + z1288 = x1288 + z1289 = x1289 + z1290 = x1290 + z1291 = x1291 + z1292 = x1292 + z1293 = x1293 + z1294 = x1294 + z1295 = x1295 + z1296 = x1296 + z1297 = x1297 + z1298 = x1298 + z1299 = x1299 + z1300 = x1300 + z1301 = x1301 + z1302 = x1302 + z1303 = x1303 + z1304 = x1304 + z1305 = x1305 + z1306 = x1306 + z1307 = x1307 + z1308 = x1308 + z1309 = x1309 + z1310 = x1310 + z1311 = x1311 + z1312 = x1312 + z1313 = x1313 + z1314 = x1314 + z1315 = x1315 + z1316 = x1316 + z1317 = x1317 + z1318 = x1318 + z1319 = x1319 + z1320 = x1320 + z1321 = x1321 + z1322 = x1322 + z1323 = x1323 + z1324 = x1324 + z1325 = x1325 + z1326 = x1326 + z1327 = x1327 + z1328 = x1328 + z1329 = x1329 + z1330 = x1330 + z1331 = x1331 + z1332 = x1332 + z1333 = x1333 + z1334 = x1334 + z1335 = x1335 + z1336 = x1336 + z1337 = x1337 + z1338 = x1338 + z1339 = x1339 + z1340 = x1340 + z1341 = x1341 + z1342 = x1342 + z1343 = x1343 + z1344 = x1344 + z1345 = x1345 + z1346 = x1346 + z1347 = x1347 + z1348 = x1348 + z1349 = x1349 + z1350 = x1350 + z1351 = x1351 + z1352 = x1352 + z1353 = x1353 + z1354 = x1354 + z1355 = x1355 + z1356 = x1356 + z1357 = x1357 + z1358 = x1358 + z1359 = x1359 + z1360 = x1360 + z1361 = x1361 + z1362 = x1362 + z1363 = x1363 + z1364 = x1364 + z1365 = x1365 + z1366 = x1366 + z1367 = x1367 + z1368 = x1368 + z1369 = x1369 + z1370 = x1370 + z1371 = x1371 + z1372 = x1372 + z1373 = x1373 + z1374 = x1374 + z1375 = x1375 + z1376 = x1376 + z1377 = x1377 + z1378 = x1378 + z1379 = x1379 + z1380 = x1380 + z1381 = x1381 + z1382 = x1382 + z1383 = x1383 + z1384 = x1384 + z1385 = x1385 + z1386 = x1386 + z1387 = x1387 + z1388 = x1388 + z1389 = x1389 + z1390 = x1390 + z1391 = x1391 + z1392 = x1392 + z1393 = x1393 + z1394 = x1394 + z1395 = x1395 + z1396 = x1396 + z1397 = x1397 + z1398 = x1398 + z1399 = x1399 + z1400 = x1400 + z1401 = x1401 + z1402 = x1402 + z1403 = x1403 + z1404 = x1404 + z1405 = x1405 + z1406 = x1406 + z1407 = x1407 + z1408 = x1408 + z1409 = x1409 + z1410 = x1410 + z1411 = x1411 + z1412 = x1412 + z1413 = x1413 + z1414 = x1414 + z1415 = x1415 + z1416 = x1416 + z1417 = x1417 + z1418 = x1418 + z1419 = x1419 + z1420 = x1420 + z1421 = x1421 + z1422 = x1422 + z1423 = x1423 + z1424 = x1424 + z1425 = x1425 + z1426 = x1426 + z1427 = x1427 + z1428 = x1428 + z1429 = x1429 + z1430 = x1430 + z1431 = x1431 + z1432 = x1432 + z1433 = x1433 + z1434 = x1434 + z1435 = x1435 + z1436 = x1436 + z1437 = x1437 + z1438 = x1438 + z1439 = x1439 + z1440 = x1440 + z1441 = x1441 + z1442 = x1442 + z1443 = x1443 + z1444 = x1444 + z1445 = x1445 + z1446 = x1446 + z1447 = x1447 + z1448 = x1448 + z1449 = x1449 + z1450 = x1450 + z1451 = x1451 + z1452 = x1452 + z1453 = x1453 + z1454 = x1454 + z1455 = x1455 + z1456 = x1456 + z1457 = x1457 + z1458 = x1458 + z1459 = x1459 + z1460 = x1460 + z1461 = x1461 + z1462 = x1462 + z1463 = x1463 + z1464 = x1464 + z1465 = x1465 + z1466 = x1466 + z1467 = x1467 + z1468 = x1468 + z1469 = x1469 + z1470 = x1470 + z1471 = x1471 + z1472 = x1472 + z1473 = x1473 + z1474 = x1474 + z1475 = x1475 + z1476 = x1476 + z1477 = x1477 + z1478 = x1478 + z1479 = x1479 + z1480 = x1480 + z1481 = x1481 + z1482 = x1482 + z1483 = x1483 + z1484 = x1484 + z1485 = x1485 + z1486 = x1486 + z1487 = x1487 + z1488 = x1488 + z1489 = x1489 + z1490 = x1490 + z1491 = x1491 + z1492 = x1492 + z1493 = x1493 + z1494 = x1494 + z1495 = x1495 + z1496 = x1496 + z1497 = x1497 + z1498 = x1498 + z1499 = x1499 + z1500 = x1500 + z1501 = x1501 + z1502 = x1502 + z1503 = x1503 + z1504 = x1504 + z1505 = x1505 + z1506 = x1506 + z1507 = x1507 + z1508 = x1508 + z1509 = x1509 + z1510 = x1510 + z1511 = x1511 + z1512 = x1512 + z1513 = x1513 + z1514 = x1514 + z1515 = x1515 + z1516 = x1516 + z1517 = x1517 + z1518 = x1518 + z1519 = x1519 + z1520 = x1520 + z1521 = x1521 + z1522 = x1522 + z1523 = x1523 + z1524 = x1524 + z1525 = x1525 + z1526 = x1526 + z1527 = x1527 + z1528 = x1528 + z1529 = x1529 + z1530 = x1530 + z1531 = x1531 + z1532 = x1532 + z1533 = x1533 + z1534 = x1534 + z1535 = x1535 + z1536 = x1536 + z1537 = x1537 + z1538 = x1538 + z1539 = x1539 + z1540 = x1540 + z1541 = x1541 + z1542 = x1542 + z1543 = x1543 + z1544 = x1544 + z1545 = x1545 + z1546 = x1546 + z1547 = x1547 + z1548 = x1548 + z1549 = x1549 + z1550 = x1550 + z1551 = x1551 + z1552 = x1552 + z1553 = x1553 + z1554 = x1554 + z1555 = x1555 + z1556 = x1556 + z1557 = x1557 + z1558 = x1558 + z1559 = x1559 + z1560 = x1560 + z1561 = x1561 + z1562 = x1562 + z1563 = x1563 + z1564 = x1564 + z1565 = x1565 + z1566 = x1566 + z1567 = x1567 + z1568 = x1568 + z1569 = x1569 + z1570 = x1570 + z1571 = x1571 + z1572 = x1572 + z1573 = x1573 + z1574 = x1574 + z1575 = x1575 + z1576 = x1576 + z1577 = x1577 + z1578 = x1578 + z1579 = x1579 + z1580 = x1580 + z1581 = x1581 + z1582 = x1582 + z1583 = x1583 + z1584 = x1584 + z1585 = x1585 + z1586 = x1586 + z1587 = x1587 + z1588 = x1588 + z1589 = x1589 + z1590 = x1590 + z1591 = x1591 + z1592 = x1592 + z1593 = x1593 + z1594 = x1594 + z1595 = x1595 + z1596 = x1596 + z1597 = x1597 + z1598 = x1598 + z1599 = x1599 + z1600 = x1600 + z1601 = x1601 + z1602 = x1602 + z1603 = x1603 + z1604 = x1604 + z1605 = x1605 + z1606 = x1606 + z1607 = x1607 + z1608 = x1608 + z1609 = x1609 + z1610 = x1610 + z1611 = x1611 + z1612 = x1612 + z1613 = x1613 + z1614 = x1614 + z1615 = x1615 + z1616 = x1616 + z1617 = x1617 + z1618 = x1618 + z1619 = x1619 + z1620 = x1620 + z1621 = x1621 + z1622 = x1622 + z1623 = x1623 + z1624 = x1624 + z1625 = x1625 + z1626 = x1626 + z1627 = x1627 + z1628 = x1628 + z1629 = x1629 + z1630 = x1630 + z1631 = x1631 + z1632 = x1632 + z1633 = x1633 + z1634 = x1634 + z1635 = x1635 + z1636 = x1636 + z1637 = x1637 + z1638 = x1638 + z1639 = x1639 + z1640 = x1640 + z1641 = x1641 + z1642 = x1642 + z1643 = x1643 + z1644 = x1644 + z1645 = x1645 + z1646 = x1646 + z1647 = x1647 + z1648 = x1648 + z1649 = x1649 + z1650 = x1650 + z1651 = x1651 + z1652 = x1652 + z1653 = x1653 + z1654 = x1654 + z1655 = x1655 + z1656 = x1656 + z1657 = x1657 + z1658 = x1658 + z1659 = x1659 + z1660 = x1660 + z1661 = x1661 + z1662 = x1662 + z1663 = x1663 + z1664 = x1664 + z1665 = x1665 + z1666 = x1666 + z1667 = x1667 + z1668 = x1668 + z1669 = x1669 + z1670 = x1670 + z1671 = x1671 + z1672 = x1672 + z1673 = x1673 + z1674 = x1674 + z1675 = x1675 + z1676 = x1676 + z1677 = x1677 + z1678 = x1678 + z1679 = x1679 + z1680 = x1680 + z1681 = x1681 + z1682 = x1682 + z1683 = x1683 + z1684 = x1684 + z1685 = x1685 + z1686 = x1686 + z1687 = x1687 + z1688 = x1688 + z1689 = x1689 + z1690 = x1690 + z1691 = x1691 + z1692 = x1692 + z1693 = x1693 + z1694 = x1694 + z1695 = x1695 + z1696 = x1696 + z1697 = x1697 + z1698 = x1698 + z1699 = x1699 + z1700 = x1700 + z1701 = x1701 + z1702 = x1702 + z1703 = x1703 + z1704 = x1704 + z1705 = x1705 + z1706 = x1706 + z1707 = x1707 + z1708 = x1708 + z1709 = x1709 + z1710 = x1710 + z1711 = x1711 + z1712 = x1712 + z1713 = x1713 + z1714 = x1714 + z1715 = x1715 + z1716 = x1716 + z1717 = x1717 + z1718 = x1718 + z1719 = x1719 + z1720 = x1720 + z1721 = x1721 + z1722 = x1722 + z1723 = x1723 + z1724 = x1724 + z1725 = x1725 + z1726 = x1726 + z1727 = x1727 + z1728 = x1728 + z1729 = x1729 + z1730 = x1730 + z1731 = x1731 + z1732 = x1732 + z1733 = x1733 + z1734 = x1734 + z1735 = x1735 + z1736 = x1736 + z1737 = x1737 + z1738 = x1738 + z1739 = x1739 + z1740 = x1740 + z1741 = x1741 + z1742 = x1742 + z1743 = x1743 + z1744 = x1744 + z1745 = x1745 + z1746 = x1746 + z1747 = x1747 + z1748 = x1748 + z1749 = x1749 + z1750 = x1750 + z1751 = x1751 + z1752 = x1752 + z1753 = x1753 + z1754 = x1754 + z1755 = x1755 + z1756 = x1756 + z1757 = x1757 + z1758 = x1758 + z1759 = x1759 + z1760 = x1760 + z1761 = x1761 + z1762 = x1762 + z1763 = x1763 + z1764 = x1764 + z1765 = x1765 + z1766 = x1766 + z1767 = x1767 + z1768 = x1768 + z1769 = x1769 + z1770 = x1770 + z1771 = x1771 + z1772 = x1772 + z1773 = x1773 + z1774 = x1774 + z1775 = x1775 + z1776 = x1776 + z1777 = x1777 + z1778 = x1778 + z1779 = x1779 + z1780 = x1780 + z1781 = x1781 + z1782 = x1782 + z1783 = x1783 + z1784 = x1784 + z1785 = x1785 + z1786 = x1786 + z1787 = x1787 + z1788 = x1788 + z1789 = x1789 + z1790 = x1790 + z1791 = x1791 + z1792 = x1792 + z1793 = x1793 + z1794 = x1794 + z1795 = x1795 + z1796 = x1796 + z1797 = x1797 + z1798 = x1798 + z1799 = x1799 + z1800 = x1800 + z1801 = x1801 + z1802 = x1802 + z1803 = x1803 + z1804 = x1804 + z1805 = x1805 + z1806 = x1806 + z1807 = x1807 + z1808 = x1808 + z1809 = x1809 + z1810 = x1810 + z1811 = x1811 + z1812 = x1812 + z1813 = x1813 + z1814 = x1814 + z1815 = x1815 + z1816 = x1816 + z1817 = x1817 + z1818 = x1818 + z1819 = x1819 + z1820 = x1820 + z1821 = x1821 + z1822 = x1822 + z1823 = x1823 + z1824 = x1824 + z1825 = x1825 + z1826 = x1826 + z1827 = x1827 + z1828 = x1828 + z1829 = x1829 + z1830 = x1830 + z1831 = x1831 + z1832 = x1832 + z1833 = x1833 + z1834 = x1834 + z1835 = x1835 + z1836 = x1836 + z1837 = x1837 + z1838 = x1838 + z1839 = x1839 + z1840 = x1840 + z1841 = x1841 + z1842 = x1842 + z1843 = x1843 + z1844 = x1844 + z1845 = x1845 + z1846 = x1846 + z1847 = x1847 + z1848 = x1848 + z1849 = x1849 + z1850 = x1850 + z1851 = x1851 + z1852 = x1852 + z1853 = x1853 + z1854 = x1854 + z1855 = x1855 + z1856 = x1856 + z1857 = x1857 + z1858 = x1858 + z1859 = x1859 + z1860 = x1860 + z1861 = x1861 + z1862 = x1862 + z1863 = x1863 + z1864 = x1864 + z1865 = x1865 + z1866 = x1866 + z1867 = x1867 + z1868 = x1868 + z1869 = x1869 + z1870 = x1870 + z1871 = x1871 + z1872 = x1872 + z1873 = x1873 + z1874 = x1874 + z1875 = x1875 + z1876 = x1876 + z1877 = x1877 + z1878 = x1878 + z1879 = x1879 + z1880 = x1880 + z1881 = x1881 + z1882 = x1882 + z1883 = x1883 + z1884 = x1884 + z1885 = x1885 + z1886 = x1886 + z1887 = x1887 + z1888 = x1888 + z1889 = x1889 + z1890 = x1890 + z1891 = x1891 + z1892 = x1892 + z1893 = x1893 + z1894 = x1894 + z1895 = x1895 + z1896 = x1896 + z1897 = x1897 + z1898 = x1898 + z1899 = x1899 + z1900 = x1900 + z1901 = x1901 + z1902 = x1902 + z1903 = x1903 + z1904 = x1904 + z1905 = x1905 + z1906 = x1906 + z1907 = x1907 + z1908 = x1908 + z1909 = x1909 + z1910 = x1910 + z1911 = x1911 + z1912 = x1912 + z1913 = x1913 + z1914 = x1914 + z1915 = x1915 + z1916 = x1916 + z1917 = x1917 + z1918 = x1918 + z1919 = x1919 + z1920 = x1920 + z1921 = x1921 + z1922 = x1922 + z1923 = x1923 + z1924 = x1924 + z1925 = x1925 + z1926 = x1926 + z1927 = x1927 + z1928 = x1928 + z1929 = x1929 + z1930 = x1930 + z1931 = x1931 + z1932 = x1932 + z1933 = x1933 + z1934 = x1934 + z1935 = x1935 + z1936 = x1936 + z1937 = x1937 + z1938 = x1938 + z1939 = x1939 + z1940 = x1940 + z1941 = x1941 + z1942 = x1942 + z1943 = x1943 + z1944 = x1944 + z1945 = x1945 + z1946 = x1946 + z1947 = x1947 + z1948 = x1948 + z1949 = x1949 + z1950 = x1950 + z1951 = x1951 + z1952 = x1952 + z1953 = x1953 + z1954 = x1954 + z1955 = x1955 + z1956 = x1956 + z1957 = x1957 + z1958 = x1958 + z1959 = x1959 + z1960 = x1960 + z1961 = x1961 + z1962 = x1962 + z1963 = x1963 + z1964 = x1964 + z1965 = x1965 + z1966 = x1966 + z1967 = x1967 + z1968 = x1968 + z1969 = x1969 + z1970 = x1970 + z1971 = x1971 + z1972 = x1972 + z1973 = x1973 + z1974 = x1974 + z1975 = x1975 + z1976 = x1976 + z1977 = x1977 + z1978 = x1978 + z1979 = x1979 + z1980 = x1980 + z1981 = x1981 + z1982 = x1982 + z1983 = x1983 + z1984 = x1984 + z1985 = x1985 + z1986 = x1986 + z1987 = x1987 + z1988 = x1988 + z1989 = x1989 + z1990 = x1990 + z1991 = x1991 + z1992 = x1992 + z1993 = x1993 + z1994 = x1994 + z1995 = x1995 + z1996 = x1996 + z1997 = x1997 + z1998 = x1998 + z1999 = x1999 + z2000 = x2000 + z2001 = x2001 + z2002 = x2002 + z2003 = x2003 + z2004 = x2004 + z2005 = x2005 + z2006 = x2006 + z2007 = x2007 + z2008 = x2008 + z2009 = x2009 + z2010 = x2010 + z2011 = x2011 + z2012 = x2012 + z2013 = x2013 + z2014 = x2014 + z2015 = x2015 + z2016 = x2016 + z2017 = x2017 + z2018 = x2018 + z2019 = x2019 + z2020 = x2020 + z2021 = x2021 + z2022 = x2022 + z2023 = x2023 + z2024 = x2024 + z2025 = x2025 + z2026 = x2026 + z2027 = x2027 + z2028 = x2028 + z2029 = x2029 + z2030 = x2030 + z2031 = x2031 + z2032 = x2032 + z2033 = x2033 + z2034 = x2034 + z2035 = x2035 + z2036 = x2036 + z2037 = x2037 + z2038 = x2038 + z2039 = x2039 + z2040 = x2040 + z2041 = x2041 + z2042 = x2042 + z2043 = x2043 + z2044 = x2044 + z2045 = x2045 + z2046 = x2046 + z2047 = x2047 + z2048 = x2048 + z2049 = x2049 + z2050 = x2050 + z2051 = x2051 + z2052 = x2052 + z2053 = x2053 + z2054 = x2054 + z2055 = x2055 + z2056 = x2056 + z2057 = x2057 + z2058 = x2058 + z2059 = x2059 + z2060 = x2060 + z2061 = x2061 + z2062 = x2062 + z2063 = x2063 + z2064 = x2064 + z2065 = x2065 + z2066 = x2066 + z2067 = x2067 + z2068 = x2068 + z2069 = x2069 + z2070 = x2070 + z2071 = x2071 + z2072 = x2072 + z2073 = x2073 + z2074 = x2074 + z2075 = x2075 + z2076 = x2076 + z2077 = x2077 + z2078 = x2078 + z2079 = x2079 + z2080 = x2080 + z2081 = x2081 + z2082 = x2082 + z2083 = x2083 + z2084 = x2084 + z2085 = x2085 + z2086 = x2086 + z2087 = x2087 + z2088 = x2088 + z2089 = x2089 + z2090 = x2090 + z2091 = x2091 + z2092 = x2092 + z2093 = x2093 + z2094 = x2094 + z2095 = x2095 + z2096 = x2096 + z2097 = x2097 + z2098 = x2098 + z2099 = x2099 + z2100 = x2100 + z2101 = x2101 + z2102 = x2102 + z2103 = x2103 + z2104 = x2104 + z2105 = x2105 + z2106 = x2106 + z2107 = x2107 + z2108 = x2108 + z2109 = x2109 + z2110 = x2110 + z2111 = x2111 + z2112 = x2112 + z2113 = x2113 + z2114 = x2114 + z2115 = x2115 + z2116 = x2116 + z2117 = x2117 + z2118 = x2118 + z2119 = x2119 + z2120 = x2120 + z2121 = x2121 + z2122 = x2122 + z2123 = x2123 + z2124 = x2124 + z2125 = x2125 + z2126 = x2126 + z2127 = x2127 + z2128 = x2128 + z2129 = x2129 + z2130 = x2130 + z2131 = x2131 + z2132 = x2132 + z2133 = x2133 + z2134 = x2134 + z2135 = x2135 + z2136 = x2136 + z2137 = x2137 + z2138 = x2138 + z2139 = x2139 + z2140 = x2140 + z2141 = x2141 + z2142 = x2142 + z2143 = x2143 + z2144 = x2144 + z2145 = x2145 + z2146 = x2146 + z2147 = x2147 + z2148 = x2148 + z2149 = x2149 + z2150 = x2150 + z2151 = x2151 + z2152 = x2152 + z2153 = x2153 + z2154 = x2154 + z2155 = x2155 + z2156 = x2156 + z2157 = x2157 + z2158 = x2158 + z2159 = x2159 + z2160 = x2160 + z2161 = x2161 + z2162 = x2162 + z2163 = x2163 + z2164 = x2164 + z2165 = x2165 + z2166 = x2166 + z2167 = x2167 + z2168 = x2168 + z2169 = x2169 + z2170 = x2170 + z2171 = x2171 + z2172 = x2172 + z2173 = x2173 + z2174 = x2174 + z2175 = x2175 + z2176 = x2176 + z2177 = x2177 + z2178 = x2178 + z2179 = x2179 + z2180 = x2180 + z2181 = x2181 + z2182 = x2182 + z2183 = x2183 + z2184 = x2184 + z2185 = x2185 + z2186 = x2186 + z2187 = x2187 + z2188 = x2188 + z2189 = x2189 + z2190 = x2190 + z2191 = x2191 + z2192 = x2192 + z2193 = x2193 + z2194 = x2194 + z2195 = x2195 + z2196 = x2196 + z2197 = x2197 + z2198 = x2198 + z2199 = x2199 + z2200 = x2200 + z2201 = x2201 + z2202 = x2202 + z2203 = x2203 + z2204 = x2204 + z2205 = x2205 + z2206 = x2206 + z2207 = x2207 + z2208 = x2208 + z2209 = x2209 + z2210 = x2210 + z2211 = x2211 + z2212 = x2212 + z2213 = x2213 + z2214 = x2214 + z2215 = x2215 + z2216 = x2216 + z2217 = x2217 + z2218 = x2218 + z2219 = x2219 + z2220 = x2220 + z2221 = x2221 + z2222 = x2222 + z2223 = x2223 + z2224 = x2224 + z2225 = x2225 + z2226 = x2226 + z2227 = x2227 + z2228 = x2228 + z2229 = x2229 + z2230 = x2230 + z2231 = x2231 + z2232 = x2232 + z2233 = x2233 + z2234 = x2234 + z2235 = x2235 + z2236 = x2236 + z2237 = x2237 + z2238 = x2238 + z2239 = x2239 + z2240 = x2240 + z2241 = x2241 + z2242 = x2242 + z2243 = x2243 + z2244 = x2244 + z2245 = x2245 + z2246 = x2246 + z2247 = x2247 + z2248 = x2248 + z2249 = x2249 + z2250 = x2250 + z2251 = x2251 + z2252 = x2252 + z2253 = x2253 + z2254 = x2254 + z2255 = x2255 + z2256 = x2256 + z2257 = x2257 + z2258 = x2258 + z2259 = x2259 + z2260 = x2260 + z2261 = x2261 + z2262 = x2262 + z2263 = x2263 + z2264 = x2264 + z2265 = x2265 + z2266 = x2266 + z2267 = x2267 + z2268 = x2268 + z2269 = x2269 + z2270 = x2270 + z2271 = x2271 + z2272 = x2272 + z2273 = x2273 + z2274 = x2274 + z2275 = x2275 + z2276 = x2276 + z2277 = x2277 + z2278 = x2278 + z2279 = x2279 + z2280 = x2280 + z2281 = x2281 + z2282 = x2282 + z2283 = x2283 + z2284 = x2284 + z2285 = x2285 + z2286 = x2286 + z2287 = x2287 + z2288 = x2288 + z2289 = x2289 + z2290 = x2290 + z2291 = x2291 + z2292 = x2292 + z2293 = x2293 + z2294 = x2294 + z2295 = x2295 + z2296 = x2296 + z2297 = x2297 + z2298 = x2298 + z2299 = x2299 + z2300 = x2300 + z2301 = x2301 + z2302 = x2302 + z2303 = x2303 + z2304 = x2304 + z2305 = x2305 + z2306 = x2306 + z2307 = x2307 + z2308 = x2308 + z2309 = x2309 + z2310 = x2310 + z2311 = x2311 + z2312 = x2312 + z2313 = x2313 + z2314 = x2314 + z2315 = x2315 + z2316 = x2316 + z2317 = x2317 + z2318 = x2318 + z2319 = x2319 + z2320 = x2320 + z2321 = x2321 + z2322 = x2322 + z2323 = x2323 + z2324 = x2324 + z2325 = x2325 + z2326 = x2326 + z2327 = x2327 + z2328 = x2328 + z2329 = x2329 + z2330 = x2330 + z2331 = x2331 + z2332 = x2332 + z2333 = x2333 + z2334 = x2334 + z2335 = x2335 + z2336 = x2336 + z2337 = x2337 + z2338 = x2338 + z2339 = x2339 + z2340 = x2340 + z2341 = x2341 + z2342 = x2342 + z2343 = x2343 + z2344 = x2344 + z2345 = x2345 + z2346 = x2346 + z2347 = x2347 + z2348 = x2348 + z2349 = x2349 + z2350 = x2350 + z2351 = x2351 + z2352 = x2352 + z2353 = x2353 + z2354 = x2354 + z2355 = x2355 + z2356 = x2356 + z2357 = x2357 + z2358 = x2358 + z2359 = x2359 + z2360 = x2360 + z2361 = x2361 + z2362 = x2362 + z2363 = x2363 + z2364 = x2364 + z2365 = x2365 + z2366 = x2366 + z2367 = x2367 + z2368 = x2368 + z2369 = x2369 + z2370 = x2370 + z2371 = x2371 + z2372 = x2372 + z2373 = x2373 + z2374 = x2374 + z2375 = x2375 + z2376 = x2376 + z2377 = x2377 + z2378 = x2378 + z2379 = x2379 + z2380 = x2380 + z2381 = x2381 + z2382 = x2382 + z2383 = x2383 + z2384 = x2384 + z2385 = x2385 + z2386 = x2386 + z2387 = x2387 + z2388 = x2388 + z2389 = x2389 + z2390 = x2390 + z2391 = x2391 + z2392 = x2392 + z2393 = x2393 + z2394 = x2394 + z2395 = x2395 + z2396 = x2396 + z2397 = x2397 + z2398 = x2398 + z2399 = x2399 + z2400 = x2400 + z2401 = x2401 + z2402 = x2402 + z2403 = x2403 + z2404 = x2404 + z2405 = x2405 + z2406 = x2406 + z2407 = x2407 + z2408 = x2408 + z2409 = x2409 + z2410 = x2410 + z2411 = x2411 + z2412 = x2412 + z2413 = x2413 + z2414 = x2414 + z2415 = x2415 + z2416 = x2416 + z2417 = x2417 + z2418 = x2418 + z2419 = x2419 + z2420 = x2420 + z2421 = x2421 + z2422 = x2422 + z2423 = x2423 + z2424 = x2424 + z2425 = x2425 + z2426 = x2426 + z2427 = x2427 + z2428 = x2428 + z2429 = x2429 + z2430 = x2430 + z2431 = x2431 + z2432 = x2432 + z2433 = x2433 + z2434 = x2434 + z2435 = x2435 + z2436 = x2436 + z2437 = x2437 + z2438 = x2438 + z2439 = x2439 + z2440 = x2440 + z2441 = x2441 + z2442 = x2442 + z2443 = x2443 + z2444 = x2444 + z2445 = x2445 + z2446 = x2446 + z2447 = x2447 + z2448 = x2448 + z2449 = x2449 + z2450 = x2450 + z2451 = x2451 + z2452 = x2452 + z2453 = x2453 + z2454 = x2454 + z2455 = x2455 + z2456 = x2456 + z2457 = x2457 + z2458 = x2458 + z2459 = x2459 + z2460 = x2460 + z2461 = x2461 + z2462 = x2462 + z2463 = x2463 + z2464 = x2464 + z2465 = x2465 + z2466 = x2466 + z2467 = x2467 + z2468 = x2468 + z2469 = x2469 + z2470 = x2470 + z2471 = x2471 + z2472 = x2472 + z2473 = x2473 + z2474 = x2474 + z2475 = x2475 + z2476 = x2476 + z2477 = x2477 + z2478 = x2478 + z2479 = x2479 + z2480 = x2480 + z2481 = x2481 + z2482 = x2482 + z2483 = x2483 + z2484 = x2484 + z2485 = x2485 + z2486 = x2486 + z2487 = x2487 + z2488 = x2488 + z2489 = x2489 + z2490 = x2490 + z2491 = x2491 + z2492 = x2492 + z2493 = x2493 + z2494 = x2494 + z2495 = x2495 + z2496 = x2496 + z2497 = x2497 + z2498 = x2498 + z2499 = x2499 + z2500 = x2500 + z2501 = x2501 + z2502 = x2502 + z2503 = x2503 + z2504 = x2504 + z2505 = x2505 + z2506 = x2506 + z2507 = x2507 + z2508 = x2508 + z2509 = x2509 + z2510 = x2510 + z2511 = x2511 + z2512 = x2512 + z2513 = x2513 + z2514 = x2514 + z2515 = x2515 + z2516 = x2516 + z2517 = x2517 + z2518 = x2518 + z2519 = x2519 + z2520 = x2520 + z2521 = x2521 + z2522 = x2522 + z2523 = x2523 + z2524 = x2524 + z2525 = x2525 + z2526 = x2526 + z2527 = x2527 + z2528 = x2528 + z2529 = x2529 + z2530 = x2530 + z2531 = x2531 + z2532 = x2532 + z2533 = x2533 + z2534 = x2534 + z2535 = x2535 + z2536 = x2536 + z2537 = x2537 + z2538 = x2538 + z2539 = x2539 + z2540 = x2540 + z2541 = x2541 + z2542 = x2542 + z2543 = x2543 + z2544 = x2544 + z2545 = x2545 + z2546 = x2546 + z2547 = x2547 + z2548 = x2548 + z2549 = x2549 + z2550 = x2550 + z2551 = x2551 + z2552 = x2552 + z2553 = x2553 + z2554 = x2554 + z2555 = x2555 + z2556 = x2556 + z2557 = x2557 + z2558 = x2558 + z2559 = x2559 + z2560 = x2560 + z2561 = x2561 + z2562 = x2562 + z2563 = x2563 + z2564 = x2564 + z2565 = x2565 + z2566 = x2566 + z2567 = x2567 + z2568 = x2568 + z2569 = x2569 + z2570 = x2570 + z2571 = x2571 + z2572 = x2572 + z2573 = x2573 + z2574 = x2574 + z2575 = x2575 + z2576 = x2576 + z2577 = x2577 + z2578 = x2578 + z2579 = x2579 + z2580 = x2580 + z2581 = x2581 + z2582 = x2582 + z2583 = x2583 + z2584 = x2584 + z2585 = x2585 + z2586 = x2586 + z2587 = x2587 + z2588 = x2588 + z2589 = x2589 + z2590 = x2590 + z2591 = x2591 + z2592 = x2592 + z2593 = x2593 + z2594 = x2594 + z2595 = x2595 + z2596 = x2596 + z2597 = x2597 + z2598 = x2598 + z2599 = x2599 + z2600 = x2600 + z2601 = x2601 + z2602 = x2602 + z2603 = x2603 + z2604 = x2604 + z2605 = x2605 + z2606 = x2606 + z2607 = x2607 + z2608 = x2608 + z2609 = x2609 + z2610 = x2610 + z2611 = x2611 + z2612 = x2612 + z2613 = x2613 + z2614 = x2614 + z2615 = x2615 + z2616 = x2616 + z2617 = x2617 + z2618 = x2618 + z2619 = x2619 + z2620 = x2620 + z2621 = x2621 + z2622 = x2622 + z2623 = x2623 + z2624 = x2624 + z2625 = x2625 + z2626 = x2626 + z2627 = x2627 + z2628 = x2628 + z2629 = x2629 + z2630 = x2630 + z2631 = x2631 + z2632 = x2632 + z2633 = x2633 + z2634 = x2634 + z2635 = x2635 + z2636 = x2636 + z2637 = x2637 + z2638 = x2638 + z2639 = x2639 + z2640 = x2640 + z2641 = x2641 + z2642 = x2642 + z2643 = x2643 + z2644 = x2644 + z2645 = x2645 + z2646 = x2646 + z2647 = x2647 + z2648 = x2648 + z2649 = x2649 + z2650 = x2650 + z2651 = x2651 + z2652 = x2652 + z2653 = x2653 + z2654 = x2654 + z2655 = x2655 + z2656 = x2656 + z2657 = x2657 + z2658 = x2658 + z2659 = x2659 + z2660 = x2660 + z2661 = x2661 + z2662 = x2662 + z2663 = x2663 + z2664 = x2664 + z2665 = x2665 + z2666 = x2666 + z2667 = x2667 + z2668 = x2668 + z2669 = x2669 + z2670 = x2670 + z2671 = x2671 + z2672 = x2672 + z2673 = x2673 + z2674 = x2674 + z2675 = x2675 + z2676 = x2676 + z2677 = x2677 + z2678 = x2678 + z2679 = x2679 + z2680 = x2680 + z2681 = x2681 + z2682 = x2682 + z2683 = x2683 + z2684 = x2684 + z2685 = x2685 + z2686 = x2686 + z2687 = x2687 + z2688 = x2688 + z2689 = x2689 + z2690 = x2690 + z2691 = x2691 + z2692 = x2692 + z2693 = x2693 + z2694 = x2694 + z2695 = x2695 + z2696 = x2696 + z2697 = x2697 + z2698 = x2698 + z2699 = x2699 + z2700 = x2700 + z2701 = x2701 + z2702 = x2702 + z2703 = x2703 + z2704 = x2704 + z2705 = x2705 + z2706 = x2706 + z2707 = x2707 + z2708 = x2708 + z2709 = x2709 + z2710 = x2710 + z2711 = x2711 + z2712 = x2712 + z2713 = x2713 + z2714 = x2714 + z2715 = x2715 + z2716 = x2716 + z2717 = x2717 + z2718 = x2718 + z2719 = x2719 + z2720 = x2720 + z2721 = x2721 + z2722 = x2722 + z2723 = x2723 + z2724 = x2724 + z2725 = x2725 + z2726 = x2726 + z2727 = x2727 + z2728 = x2728 + z2729 = x2729 + z2730 = x2730 + z2731 = x2731 + z2732 = x2732 + z2733 = x2733 + z2734 = x2734 + z2735 = x2735 + z2736 = x2736 + z2737 = x2737 + z2738 = x2738 + z2739 = x2739 + z2740 = x2740 + z2741 = x2741 + z2742 = x2742 + z2743 = x2743 + z2744 = x2744 + z2745 = x2745 + z2746 = x2746 + z2747 = x2747 + z2748 = x2748 + z2749 = x2749 + z2750 = x2750 + z2751 = x2751 + z2752 = x2752 + z2753 = x2753 + z2754 = x2754 + z2755 = x2755 + z2756 = x2756 + z2757 = x2757 + z2758 = x2758 + z2759 = x2759 + z2760 = x2760 + z2761 = x2761 + z2762 = x2762 + z2763 = x2763 + z2764 = x2764 + z2765 = x2765 + z2766 = x2766 + z2767 = x2767 + z2768 = x2768 + z2769 = x2769 + z2770 = x2770 + z2771 = x2771 + z2772 = x2772 + z2773 = x2773 + z2774 = x2774 + z2775 = x2775 + z2776 = x2776 + z2777 = x2777 + z2778 = x2778 + z2779 = x2779 + z2780 = x2780 + z2781 = x2781 + z2782 = x2782 + z2783 = x2783 + z2784 = x2784 + z2785 = x2785 + z2786 = x2786 + z2787 = x2787 + z2788 = x2788 + z2789 = x2789 + z2790 = x2790 + z2791 = x2791 + z2792 = x2792 + z2793 = x2793 + z2794 = x2794 + z2795 = x2795 + z2796 = x2796 + z2797 = x2797 + z2798 = x2798 + z2799 = x2799 + z2800 = x2800 + z2801 = x2801 + z2802 = x2802 + z2803 = x2803 + z2804 = x2804 + z2805 = x2805 + z2806 = x2806 + z2807 = x2807 + z2808 = x2808 + z2809 = x2809 + z2810 = x2810 + z2811 = x2811 + z2812 = x2812 + z2813 = x2813 + z2814 = x2814 + z2815 = x2815 + z2816 = x2816 + z2817 = x2817 + z2818 = x2818 + z2819 = x2819 + z2820 = x2820 + z2821 = x2821 + z2822 = x2822 + z2823 = x2823 + z2824 = x2824 + z2825 = x2825 + z2826 = x2826 + z2827 = x2827 + z2828 = x2828 + z2829 = x2829 + z2830 = x2830 + z2831 = x2831 + z2832 = x2832 + z2833 = x2833 + z2834 = x2834 + z2835 = x2835 + z2836 = x2836 + z2837 = x2837 + z2838 = x2838 + z2839 = x2839 + z2840 = x2840 + z2841 = x2841 + z2842 = x2842 + z2843 = x2843 + z2844 = x2844 + z2845 = x2845 + z2846 = x2846 + z2847 = x2847 + z2848 = x2848 + z2849 = x2849 + z2850 = x2850 + z2851 = x2851 + z2852 = x2852 + z2853 = x2853 + z2854 = x2854 + z2855 = x2855 + z2856 = x2856 + z2857 = x2857 + z2858 = x2858 + z2859 = x2859 + z2860 = x2860 + z2861 = x2861 + z2862 = x2862 + z2863 = x2863 + z2864 = x2864 + z2865 = x2865 + z2866 = x2866 + z2867 = x2867 + z2868 = x2868 + z2869 = x2869 + z2870 = x2870 + z2871 = x2871 + z2872 = x2872 + z2873 = x2873 + z2874 = x2874 + z2875 = x2875 + z2876 = x2876 + z2877 = x2877 + z2878 = x2878 + z2879 = x2879 + z2880 = x2880 + z2881 = x2881 + z2882 = x2882 + z2883 = x2883 + z2884 = x2884 + z2885 = x2885 + z2886 = x2886 + z2887 = x2887 + z2888 = x2888 + z2889 = x2889 + z2890 = x2890 + z2891 = x2891 + z2892 = x2892 + z2893 = x2893 + z2894 = x2894 + z2895 = x2895 + z2896 = x2896 + z2897 = x2897 + z2898 = x2898 + z2899 = x2899 + z2900 = x2900 + z2901 = x2901 + z2902 = x2902 + z2903 = x2903 + z2904 = x2904 + z2905 = x2905 + z2906 = x2906 + z2907 = x2907 + z2908 = x2908 + z2909 = x2909 + z2910 = x2910 + z2911 = x2911 + z2912 = x2912 + z2913 = x2913 + z2914 = x2914 + z2915 = x2915 + z2916 = x2916 + z2917 = x2917 + z2918 = x2918 + z2919 = x2919 + z2920 = x2920 + z2921 = x2921 + z2922 = x2922 + z2923 = x2923 + z2924 = x2924 + z2925 = x2925 + z2926 = x2926 + z2927 = x2927 + z2928 = x2928 + z2929 = x2929 + z2930 = x2930 + z2931 = x2931 + z2932 = x2932 + z2933 = x2933 + z2934 = x2934 + z2935 = x2935 + z2936 = x2936 + z2937 = x2937 + z2938 = x2938 + z2939 = x2939 + z2940 = x2940 + z2941 = x2941 + z2942 = x2942 + z2943 = x2943 + z2944 = x2944 + z2945 = x2945 + z2946 = x2946 + z2947 = x2947 + z2948 = x2948 + z2949 = x2949 + z2950 = x2950 + z2951 = x2951 + z2952 = x2952 + z2953 = x2953 + z2954 = x2954 + z2955 = x2955 + z2956 = x2956 + z2957 = x2957 + z2958 = x2958 + z2959 = x2959 + z2960 = x2960 + z2961 = x2961 + z2962 = x2962 + z2963 = x2963 + z2964 = x2964 + z2965 = x2965 + z2966 = x2966 + z2967 = x2967 + z2968 = x2968 + z2969 = x2969 + z2970 = x2970 + z2971 = x2971 + z2972 = x2972 + z2973 = x2973 + z2974 = x2974 + z2975 = x2975 + z2976 = x2976 + z2977 = x2977 + z2978 = x2978 + z2979 = x2979 + z2980 = x2980 + z2981 = x2981 + z2982 = x2982 + z2983 = x2983 + z2984 = x2984 + z2985 = x2985 + z2986 = x2986 + z2987 = x2987 + z2988 = x2988 + z2989 = x2989 + z2990 = x2990 + z2991 = x2991 + z2992 = x2992 + z2993 = x2993 + z2994 = x2994 + z2995 = x2995 + z2996 = x2996 + z2997 = x2997 + z2998 = x2998 + z2999 = x2999 + z3000 = x3000 + z3001 = x3001 + z3002 = x3002 + z3003 = x3003 + z3004 = x3004 + z3005 = x3005 + z3006 = x3006 + z3007 = x3007 + z3008 = x3008 + z3009 = x3009 + z3010 = x3010 + z3011 = x3011 + z3012 = x3012 + z3013 = x3013 + z3014 = x3014 + z3015 = x3015 + z3016 = x3016 + z3017 = x3017 + z3018 = x3018 + z3019 = x3019 + z3020 = x3020 + z3021 = x3021 + z3022 = x3022 + z3023 = x3023 + z3024 = x3024 + z3025 = x3025 + z3026 = x3026 + z3027 = x3027 + z3028 = x3028 + z3029 = x3029 + z3030 = x3030 + z3031 = x3031 + z3032 = x3032 + z3033 = x3033 + z3034 = x3034 + z3035 = x3035 + z3036 = x3036 + z3037 = x3037 + z3038 = x3038 + z3039 = x3039 + z3040 = x3040 + z3041 = x3041 + z3042 = x3042 + z3043 = x3043 + z3044 = x3044 + z3045 = x3045 + z3046 = x3046 + z3047 = x3047 + z3048 = x3048 + z3049 = x3049 + z3050 = x3050 + z3051 = x3051 + z3052 = x3052 + z3053 = x3053 + z3054 = x3054 + z3055 = x3055 + z3056 = x3056 + z3057 = x3057 + z3058 = x3058 + z3059 = x3059 + z3060 = x3060 + z3061 = x3061 + z3062 = x3062 + z3063 = x3063 + z3064 = x3064 + z3065 = x3065 + z3066 = x3066 + z3067 = x3067 + z3068 = x3068 + z3069 = x3069 + z3070 = x3070 + z3071 = x3071 + z3072 = x3072 + z3073 = x3073 + z3074 = x3074 + z3075 = x3075 + z3076 = x3076 + z3077 = x3077 + z3078 = x3078 + z3079 = x3079 + z3080 = x3080 + z3081 = x3081 + z3082 = x3082 + z3083 = x3083 + z3084 = x3084 + z3085 = x3085 + z3086 = x3086 + z3087 = x3087 + z3088 = x3088 + z3089 = x3089 + z3090 = x3090 + z3091 = x3091 + z3092 = x3092 + z3093 = x3093 + z3094 = x3094 + z3095 = x3095 + z3096 = x3096 + z3097 = x3097 + z3098 = x3098 + z3099 = x3099 + z3100 = x3100 + z3101 = x3101 + z3102 = x3102 + z3103 = x3103 + z3104 = x3104 + z3105 = x3105 + z3106 = x3106 + z3107 = x3107 + z3108 = x3108 + z3109 = x3109 + z3110 = x3110 + z3111 = x3111 + z3112 = x3112 + z3113 = x3113 + z3114 = x3114 + z3115 = x3115 + z3116 = x3116 + z3117 = x3117 + z3118 = x3118 + z3119 = x3119 + z3120 = x3120 + z3121 = x3121 + z3122 = x3122 + z3123 = x3123 + z3124 = x3124 + z3125 = x3125 + z3126 = x3126 + z3127 = x3127 + z3128 = x3128 + z3129 = x3129 + z3130 = x3130 + z3131 = x3131 + z3132 = x3132 + z3133 = x3133 + z3134 = x3134 + z3135 = x3135 + z3136 = x3136 + z3137 = x3137 + z3138 = x3138 + z3139 = x3139 + z3140 = x3140 + z3141 = x3141 + z3142 = x3142 + z3143 = x3143 + z3144 = x3144 + z3145 = x3145 + z3146 = x3146 + z3147 = x3147 + z3148 = x3148 + z3149 = x3149 + z3150 = x3150 + z3151 = x3151 + z3152 = x3152 + z3153 = x3153 + z3154 = x3154 + z3155 = x3155 + z3156 = x3156 + z3157 = x3157 + z3158 = x3158 + z3159 = x3159 + z3160 = x3160 + z3161 = x3161 + z3162 = x3162 + z3163 = x3163 + z3164 = x3164 + z3165 = x3165 + z3166 = x3166 + z3167 = x3167 + z3168 = x3168 + z3169 = x3169 + z3170 = x3170 + z3171 = x3171 + z3172 = x3172 + z3173 = x3173 + z3174 = x3174 + z3175 = x3175 + z3176 = x3176 + z3177 = x3177 + z3178 = x3178 + z3179 = x3179 + z3180 = x3180 + z3181 = x3181 + z3182 = x3182 + z3183 = x3183 + z3184 = x3184 + z3185 = x3185 + z3186 = x3186 + z3187 = x3187 + z3188 = x3188 + z3189 = x3189 + z3190 = x3190 + z3191 = x3191 + z3192 = x3192 + z3193 = x3193 + z3194 = x3194 + z3195 = x3195 + z3196 = x3196 + z3197 = x3197 + z3198 = x3198 + z3199 = x3199 + z3200 = x3200 + z3201 = x3201 + z3202 = x3202 + z3203 = x3203 + z3204 = x3204 + z3205 = x3205 + z3206 = x3206 + z3207 = x3207 + z3208 = x3208 + z3209 = x3209 + z3210 = x3210 + z3211 = x3211 + z3212 = x3212 + z3213 = x3213 + z3214 = x3214 + z3215 = x3215 + z3216 = x3216 + z3217 = x3217 + z3218 = x3218 + z3219 = x3219 + z3220 = x3220 + z3221 = x3221 + z3222 = x3222 + z3223 = x3223 + z3224 = x3224 + z3225 = x3225 + z3226 = x3226 + z3227 = x3227 + z3228 = x3228 + z3229 = x3229 + z3230 = x3230 + z3231 = x3231 + z3232 = x3232 + z3233 = x3233 + z3234 = x3234 + z3235 = x3235 + z3236 = x3236 + z3237 = x3237 + z3238 = x3238 + z3239 = x3239 + z3240 = x3240 + z3241 = x3241 + z3242 = x3242 + z3243 = x3243 + z3244 = x3244 + z3245 = x3245 + z3246 = x3246 + z3247 = x3247 + z3248 = x3248 + z3249 = x3249 + z3250 = x3250 + z3251 = x3251 + z3252 = x3252 + z3253 = x3253 + z3254 = x3254 + z3255 = x3255 + z3256 = x3256 + z3257 = x3257 + z3258 = x3258 + z3259 = x3259 + z3260 = x3260 + z3261 = x3261 + z3262 = x3262 + z3263 = x3263 + z3264 = x3264 + z3265 = x3265 + z3266 = x3266 + z3267 = x3267 + z3268 = x3268 + z3269 = x3269 + z3270 = x3270 + z3271 = x3271 + z3272 = x3272 + z3273 = x3273 + z3274 = x3274 + z3275 = x3275 + z3276 = x3276 + z3277 = x3277 + z3278 = x3278 + z3279 = x3279 + z3280 = x3280 + z3281 = x3281 + z3282 = x3282 + z3283 = x3283 + z3284 = x3284 + z3285 = x3285 + z3286 = x3286 + z3287 = x3287 + z3288 = x3288 + z3289 = x3289 + z3290 = x3290 + z3291 = x3291 + z3292 = x3292 + z3293 = x3293 + z3294 = x3294 + z3295 = x3295 + z3296 = x3296 + z3297 = x3297 + z3298 = x3298 + z3299 = x3299 + z3300 = x3300 + z3301 = x3301 + z3302 = x3302 + z3303 = x3303 + z3304 = x3304 + z3305 = x3305 + z3306 = x3306 + z3307 = x3307 + z3308 = x3308 + z3309 = x3309 + z3310 = x3310 + z3311 = x3311 + z3312 = x3312 + z3313 = x3313 + z3314 = x3314 + z3315 = x3315 + z3316 = x3316 + z3317 = x3317 + z3318 = x3318 + z3319 = x3319 + z3320 = x3320 + z3321 = x3321 + z3322 = x3322 + z3323 = x3323 + z3324 = x3324 + z3325 = x3325 + z3326 = x3326 + z3327 = x3327 + z3328 = x3328 + z3329 = x3329 + z3330 = x3330 + z3331 = x3331 + z3332 = x3332 + z3333 = x3333 + z3334 = x3334 + z3335 = x3335 + z3336 = x3336 + z3337 = x3337 + z3338 = x3338 + z3339 = x3339 + z3340 = x3340 + z3341 = x3341 + z3342 = x3342 + z3343 = x3343 + z3344 = x3344 + z3345 = x3345 + z3346 = x3346 + z3347 = x3347 + z3348 = x3348 + z3349 = x3349 + z3350 = x3350 + z3351 = x3351 + z3352 = x3352 + z3353 = x3353 + z3354 = x3354 + z3355 = x3355 + z3356 = x3356 + z3357 = x3357 + z3358 = x3358 + z3359 = x3359 + z3360 = x3360 + z3361 = x3361 + z3362 = x3362 + z3363 = x3363 + z3364 = x3364 + z3365 = x3365 + z3366 = x3366 + z3367 = x3367 + z3368 = x3368 + z3369 = x3369 + z3370 = x3370 + z3371 = x3371 + z3372 = x3372 + z3373 = x3373 + z3374 = x3374 + z3375 = x3375 + z3376 = x3376 + z3377 = x3377 + z3378 = x3378 + z3379 = x3379 + z3380 = x3380 + z3381 = x3381 + z3382 = x3382 + z3383 = x3383 + z3384 = x3384 + z3385 = x3385 + z3386 = x3386 + z3387 = x3387 + z3388 = x3388 + z3389 = x3389 + z3390 = x3390 + z3391 = x3391 + z3392 = x3392 + z3393 = x3393 + z3394 = x3394 + z3395 = x3395 + z3396 = x3396 + z3397 = x3397 + z3398 = x3398 + z3399 = x3399 + z3400 = x3400 + z3401 = x3401 + z3402 = x3402 + z3403 = x3403 + z3404 = x3404 + z3405 = x3405 + z3406 = x3406 + z3407 = x3407 + z3408 = x3408 + z3409 = x3409 + z3410 = x3410 + z3411 = x3411 + z3412 = x3412 + z3413 = x3413 + z3414 = x3414 + z3415 = x3415 + z3416 = x3416 + z3417 = x3417 + z3418 = x3418 + z3419 = x3419 + z3420 = x3420 + z3421 = x3421 + z3422 = x3422 + z3423 = x3423 + z3424 = x3424 + z3425 = x3425 + z3426 = x3426 + z3427 = x3427 + z3428 = x3428 + z3429 = x3429 + z3430 = x3430 + z3431 = x3431 + z3432 = x3432 + z3433 = x3433 + z3434 = x3434 + z3435 = x3435 + z3436 = x3436 + z3437 = x3437 + z3438 = x3438 + z3439 = x3439 + z3440 = x3440 + z3441 = x3441 + z3442 = x3442 + z3443 = x3443 + z3444 = x3444 + z3445 = x3445 + z3446 = x3446 + z3447 = x3447 + z3448 = x3448 + z3449 = x3449 + z3450 = x3450 + z3451 = x3451 + z3452 = x3452 + z3453 = x3453 + z3454 = x3454 + z3455 = x3455 + z3456 = x3456 + z3457 = x3457 + z3458 = x3458 + z3459 = x3459 + z3460 = x3460 + z3461 = x3461 + z3462 = x3462 + z3463 = x3463 + z3464 = x3464 + z3465 = x3465 + z3466 = x3466 + z3467 = x3467 + z3468 = x3468 + z3469 = x3469 + z3470 = x3470 + z3471 = x3471 + z3472 = x3472 + z3473 = x3473 + z3474 = x3474 + z3475 = x3475 + z3476 = x3476 + z3477 = x3477 + z3478 = x3478 + z3479 = x3479 + z3480 = x3480 + z3481 = x3481 + z3482 = x3482 + z3483 = x3483 + z3484 = x3484 + z3485 = x3485 + z3486 = x3486 + z3487 = x3487 + z3488 = x3488 + z3489 = x3489 + z3490 = x3490 + z3491 = x3491 + z3492 = x3492 + z3493 = x3493 + z3494 = x3494 + z3495 = x3495 + z3496 = x3496 + z3497 = x3497 + z3498 = x3498 + z3499 = x3499 + z3500 = x3500 + z3501 = x3501 + z3502 = x3502 + z3503 = x3503 + z3504 = x3504 + z3505 = x3505 + z3506 = x3506 + z3507 = x3507 + z3508 = x3508 + z3509 = x3509 + z3510 = x3510 + z3511 = x3511 + z3512 = x3512 + z3513 = x3513 + z3514 = x3514 + z3515 = x3515 + z3516 = x3516 + z3517 = x3517 + z3518 = x3518 + z3519 = x3519 + z3520 = x3520 + z3521 = x3521 + z3522 = x3522 + z3523 = x3523 + z3524 = x3524 + z3525 = x3525 + z3526 = x3526 + z3527 = x3527 + z3528 = x3528 + z3529 = x3529 + z3530 = x3530 + z3531 = x3531 + z3532 = x3532 + z3533 = x3533 + z3534 = x3534 + z3535 = x3535 + z3536 = x3536 + z3537 = x3537 + z3538 = x3538 + z3539 = x3539 + z3540 = x3540 + z3541 = x3541 + z3542 = x3542 + z3543 = x3543 + z3544 = x3544 + z3545 = x3545 + z3546 = x3546 + z3547 = x3547 + z3548 = x3548 + z3549 = x3549 + z3550 = x3550 + z3551 = x3551 + z3552 = x3552 + z3553 = x3553 + z3554 = x3554 + z3555 = x3555 + z3556 = x3556 + z3557 = x3557 + z3558 = x3558 + z3559 = x3559 + z3560 = x3560 + z3561 = x3561 + z3562 = x3562 + z3563 = x3563 + z3564 = x3564 + z3565 = x3565 + z3566 = x3566 + z3567 = x3567 + z3568 = x3568 + z3569 = x3569 + z3570 = x3570 + z3571 = x3571 + z3572 = x3572 + z3573 = x3573 + z3574 = x3574 + z3575 = x3575 + z3576 = x3576 + z3577 = x3577 + z3578 = x3578 + z3579 = x3579 + z3580 = x3580 + z3581 = x3581 + z3582 = x3582 + z3583 = x3583 + z3584 = x3584 + z3585 = x3585 + z3586 = x3586 + z3587 = x3587 + z3588 = x3588 + z3589 = x3589 + z3590 = x3590 + z3591 = x3591 + z3592 = x3592 + z3593 = x3593 + z3594 = x3594 + z3595 = x3595 + z3596 = x3596 + z3597 = x3597 + z3598 = x3598 + z3599 = x3599 + z3600 = x3600 + z3601 = x3601 + z3602 = x3602 + z3603 = x3603 + z3604 = x3604 + z3605 = x3605 + z3606 = x3606 + z3607 = x3607 + z3608 = x3608 + z3609 = x3609 + z3610 = x3610 + z3611 = x3611 + z3612 = x3612 + z3613 = x3613 + z3614 = x3614 + z3615 = x3615 + z3616 = x3616 + z3617 = x3617 + z3618 = x3618 + z3619 = x3619 + z3620 = x3620 + z3621 = x3621 + z3622 = x3622 + z3623 = x3623 + z3624 = x3624 + z3625 = x3625 + z3626 = x3626 + z3627 = x3627 + z3628 = x3628 + z3629 = x3629 + z3630 = x3630 + z3631 = x3631 + z3632 = x3632 + z3633 = x3633 + z3634 = x3634 + z3635 = x3635 + z3636 = x3636 + z3637 = x3637 + z3638 = x3638 + z3639 = x3639 + z3640 = x3640 + z3641 = x3641 + z3642 = x3642 + z3643 = x3643 + z3644 = x3644 + z3645 = x3645 + z3646 = x3646 + z3647 = x3647 + z3648 = x3648 + z3649 = x3649 + z3650 = x3650 + z3651 = x3651 + z3652 = x3652 + z3653 = x3653 + z3654 = x3654 + z3655 = x3655 + z3656 = x3656 + z3657 = x3657 + z3658 = x3658 + z3659 = x3659 + z3660 = x3660 + z3661 = x3661 + z3662 = x3662 + z3663 = x3663 + z3664 = x3664 + z3665 = x3665 + z3666 = x3666 + z3667 = x3667 + z3668 = x3668 + z3669 = x3669 + z3670 = x3670 + z3671 = x3671 + z3672 = x3672 + z3673 = x3673 + z3674 = x3674 + z3675 = x3675 + z3676 = x3676 + z3677 = x3677 + z3678 = x3678 + z3679 = x3679 + z3680 = x3680 + z3681 = x3681 + z3682 = x3682 + z3683 = x3683 + z3684 = x3684 + z3685 = x3685 + z3686 = x3686 + z3687 = x3687 + z3688 = x3688 + z3689 = x3689 + z3690 = x3690 + z3691 = x3691 + z3692 = x3692 + z3693 = x3693 + z3694 = x3694 + z3695 = x3695 + z3696 = x3696 + z3697 = x3697 + z3698 = x3698 + z3699 = x3699 + z3700 = x3700 + z3701 = x3701 + z3702 = x3702 + z3703 = x3703 + z3704 = x3704 + z3705 = x3705 + z3706 = x3706 + z3707 = x3707 + z3708 = x3708 + z3709 = x3709 + z3710 = x3710 + z3711 = x3711 + z3712 = x3712 + z3713 = x3713 + z3714 = x3714 + z3715 = x3715 + z3716 = x3716 + z3717 = x3717 + z3718 = x3718 + z3719 = x3719 + z3720 = x3720 + z3721 = x3721 + z3722 = x3722 + z3723 = x3723 + z3724 = x3724 + z3725 = x3725 + z3726 = x3726 + z3727 = x3727 + z3728 = x3728 + z3729 = x3729 + z3730 = x3730 + z3731 = x3731 + z3732 = x3732 + z3733 = x3733 + z3734 = x3734 + z3735 = x3735 + z3736 = x3736 + z3737 = x3737 + z3738 = x3738 + z3739 = x3739 + z3740 = x3740 + z3741 = x3741 + z3742 = x3742 + z3743 = x3743 + z3744 = x3744 + z3745 = x3745 + z3746 = x3746 + z3747 = x3747 + z3748 = x3748 + z3749 = x3749 + z3750 = x3750 + z3751 = x3751 + z3752 = x3752 + z3753 = x3753 + z3754 = x3754 + z3755 = x3755 + z3756 = x3756 + z3757 = x3757 + z3758 = x3758 + z3759 = x3759 + z3760 = x3760 + z3761 = x3761 + z3762 = x3762 + z3763 = x3763 + z3764 = x3764 + z3765 = x3765 + z3766 = x3766 + z3767 = x3767 + z3768 = x3768 + z3769 = x3769 + z3770 = x3770 + z3771 = x3771 + z3772 = x3772 + z3773 = x3773 + z3774 = x3774 + z3775 = x3775 + z3776 = x3776 + z3777 = x3777 + z3778 = x3778 + z3779 = x3779 + z3780 = x3780 + z3781 = x3781 + z3782 = x3782 + z3783 = x3783 + z3784 = x3784 + z3785 = x3785 + z3786 = x3786 + z3787 = x3787 + z3788 = x3788 + z3789 = x3789 + z3790 = x3790 + z3791 = x3791 + z3792 = x3792 + z3793 = x3793 + z3794 = x3794 + z3795 = x3795 + z3796 = x3796 + z3797 = x3797 + z3798 = x3798 + z3799 = x3799 + z3800 = x3800 + z3801 = x3801 + z3802 = x3802 + z3803 = x3803 + z3804 = x3804 + z3805 = x3805 + z3806 = x3806 + z3807 = x3807 + z3808 = x3808 + z3809 = x3809 + z3810 = x3810 + z3811 = x3811 + z3812 = x3812 + z3813 = x3813 + z3814 = x3814 + z3815 = x3815 + z3816 = x3816 + z3817 = x3817 + z3818 = x3818 + z3819 = x3819 + z3820 = x3820 + z3821 = x3821 + z3822 = x3822 + z3823 = x3823 + z3824 = x3824 + z3825 = x3825 + z3826 = x3826 + z3827 = x3827 + z3828 = x3828 + z3829 = x3829 + z3830 = x3830 + z3831 = x3831 + z3832 = x3832 + z3833 = x3833 + z3834 = x3834 + z3835 = x3835 + z3836 = x3836 + z3837 = x3837 + z3838 = x3838 + z3839 = x3839 + z3840 = x3840 + z3841 = x3841 + z3842 = x3842 + z3843 = x3843 + z3844 = x3844 + z3845 = x3845 + z3846 = x3846 + z3847 = x3847 + z3848 = x3848 + z3849 = x3849 + z3850 = x3850 + z3851 = x3851 + z3852 = x3852 + z3853 = x3853 + z3854 = x3854 + z3855 = x3855 + z3856 = x3856 + z3857 = x3857 + z3858 = x3858 + z3859 = x3859 + z3860 = x3860 + z3861 = x3861 + z3862 = x3862 + z3863 = x3863 + z3864 = x3864 + z3865 = x3865 + z3866 = x3866 + z3867 = x3867 + z3868 = x3868 + z3869 = x3869 + z3870 = x3870 + z3871 = x3871 + z3872 = x3872 + z3873 = x3873 + z3874 = x3874 + z3875 = x3875 + z3876 = x3876 + z3877 = x3877 + z3878 = x3878 + z3879 = x3879 + z3880 = x3880 + z3881 = x3881 + z3882 = x3882 + z3883 = x3883 + z3884 = x3884 + z3885 = x3885 + z3886 = x3886 + z3887 = x3887 + z3888 = x3888 + z3889 = x3889 + z3890 = x3890 + z3891 = x3891 + z3892 = x3892 + z3893 = x3893 + z3894 = x3894 + z3895 = x3895 + z3896 = x3896 + z3897 = x3897 + z3898 = x3898 + z3899 = x3899 + z3900 = x3900 + z3901 = x3901 + z3902 = x3902 + z3903 = x3903 + z3904 = x3904 + z3905 = x3905 + z3906 = x3906 + z3907 = x3907 + z3908 = x3908 + z3909 = x3909 + z3910 = x3910 + z3911 = x3911 + z3912 = x3912 + z3913 = x3913 + z3914 = x3914 + z3915 = x3915 + z3916 = x3916 + z3917 = x3917 + z3918 = x3918 + z3919 = x3919 + z3920 = x3920 + z3921 = x3921 + z3922 = x3922 + z3923 = x3923 + z3924 = x3924 + z3925 = x3925 + z3926 = x3926 + z3927 = x3927 + z3928 = x3928 + z3929 = x3929 + z3930 = x3930 + z3931 = x3931 + z3932 = x3932 + z3933 = x3933 + z3934 = x3934 + z3935 = x3935 + z3936 = x3936 + z3937 = x3937 + z3938 = x3938 + z3939 = x3939 + z3940 = x3940 + z3941 = x3941 + z3942 = x3942 + z3943 = x3943 + z3944 = x3944 + z3945 = x3945 + z3946 = x3946 + z3947 = x3947 + z3948 = x3948 + z3949 = x3949 + z3950 = x3950 + z3951 = x3951 + z3952 = x3952 + z3953 = x3953 + z3954 = x3954 + z3955 = x3955 + z3956 = x3956 + z3957 = x3957 + z3958 = x3958 + z3959 = x3959 + z3960 = x3960 + z3961 = x3961 + z3962 = x3962 + z3963 = x3963 + z3964 = x3964 + z3965 = x3965 + z3966 = x3966 + z3967 = x3967 + z3968 = x3968 + z3969 = x3969 + z3970 = x3970 + z3971 = x3971 + z3972 = x3972 + z3973 = x3973 + z3974 = x3974 + z3975 = x3975 + z3976 = x3976 + z3977 = x3977 + z3978 = x3978 + z3979 = x3979 + z3980 = x3980 + z3981 = x3981 + z3982 = x3982 + z3983 = x3983 + z3984 = x3984 + z3985 = x3985 + z3986 = x3986 + z3987 = x3987 + z3988 = x3988 + z3989 = x3989 + z3990 = x3990 + z3991 = x3991 + z3992 = x3992 + z3993 = x3993 + z3994 = x3994 + z3995 = x3995 + z3996 = x3996 + z3997 = x3997 + z3998 = x3998 + z3999 = x3999 + z4000 = x4000 + z4001 = x4001 + z4002 = x4002 + z4003 = x4003 + z4004 = x4004 + z4005 = x4005 + z4006 = x4006 + z4007 = x4007 + z4008 = x4008 + z4009 = x4009 + z4010 = x4010 + z4011 = x4011 + z4012 = x4012 + z4013 = x4013 + z4014 = x4014 + z4015 = x4015 + z4016 = x4016 + z4017 = x4017 + z4018 = x4018 + z4019 = x4019 + z4020 = x4020 + z4021 = x4021 + z4022 = x4022 + z4023 = x4023 + z4024 = x4024 + z4025 = x4025 + z4026 = x4026 + z4027 = x4027 + z4028 = x4028 + z4029 = x4029 + z4030 = x4030 + z4031 = x4031 + z4032 = x4032 + z4033 = x4033 + z4034 = x4034 + z4035 = x4035 + z4036 = x4036 + z4037 = x4037 + z4038 = x4038 + z4039 = x4039 + z4040 = x4040 + z4041 = x4041 + z4042 = x4042 + z4043 = x4043 + z4044 = x4044 + z4045 = x4045 + z4046 = x4046 + z4047 = x4047 + z4048 = x4048 + z4049 = x4049 + z4050 = x4050 + z4051 = x4051 + z4052 = x4052 + z4053 = x4053 + z4054 = x4054 + z4055 = x4055 + z4056 = x4056 + z4057 = x4057 + z4058 = x4058 + z4059 = x4059 + z4060 = x4060 + z4061 = x4061 + z4062 = x4062 + z4063 = x4063 + z4064 = x4064 + z4065 = x4065 + z4066 = x4066 + z4067 = x4067 + z4068 = x4068 + z4069 = x4069 + z4070 = x4070 + z4071 = x4071 + z4072 = x4072 + z4073 = x4073 + z4074 = x4074 + z4075 = x4075 + z4076 = x4076 + z4077 = x4077 + z4078 = x4078 + z4079 = x4079 + z4080 = x4080 + z4081 = x4081 + z4082 = x4082 + z4083 = x4083 + z4084 = x4084 + z4085 = x4085 + z4086 = x4086 + z4087 = x4087 + z4088 = x4088 + z4089 = x4089 + z4090 = x4090 + z4091 = x4091 + z4092 = x4092 + z4093 = x4093 + z4094 = x4094 + z4095 = x4095 + z4096 = x4096 + z4097 = x4097 + z4098 = x4098 + z4099 = x4099 + z4100 = x4100 + z4101 = x4101 + z4102 = x4102 + z4103 = x4103 + z4104 = x4104 + z4105 = x4105 + z4106 = x4106 + z4107 = x4107 + z4108 = x4108 + z4109 = x4109 + z4110 = x4110 + z4111 = x4111 + z4112 = x4112 + z4113 = x4113 + z4114 = x4114 + z4115 = x4115 + z4116 = x4116 + z4117 = x4117 + z4118 = x4118 + z4119 = x4119 + z4120 = x4120 + z4121 = x4121 + z4122 = x4122 + z4123 = x4123 + z4124 = x4124 + z4125 = x4125 + z4126 = x4126 + z4127 = x4127 + z4128 = x4128 + z4129 = x4129 + z4130 = x4130 + z4131 = x4131 + z4132 = x4132 + z4133 = x4133 + z4134 = x4134 + z4135 = x4135 + z4136 = x4136 + z4137 = x4137 + z4138 = x4138 + z4139 = x4139 + z4140 = x4140 + z4141 = x4141 + z4142 = x4142 + z4143 = x4143 + z4144 = x4144 + z4145 = x4145 + z4146 = x4146 + z4147 = x4147 + z4148 = x4148 + z4149 = x4149 + z4150 = x4150 + z4151 = x4151 + z4152 = x4152 + z4153 = x4153 + z4154 = x4154 + z4155 = x4155 + z4156 = x4156 + z4157 = x4157 + z4158 = x4158 + z4159 = x4159 + z4160 = x4160 + z4161 = x4161 + z4162 = x4162 + z4163 = x4163 + z4164 = x4164 + z4165 = x4165 + z4166 = x4166 + z4167 = x4167 + z4168 = x4168 + z4169 = x4169 + z4170 = x4170 + z4171 = x4171 + z4172 = x4172 + z4173 = x4173 + z4174 = x4174 + z4175 = x4175 + z4176 = x4176 + z4177 = x4177 + z4178 = x4178 + z4179 = x4179 + z4180 = x4180 + z4181 = x4181 + z4182 = x4182 + z4183 = x4183 + z4184 = x4184 + z4185 = x4185 + z4186 = x4186 + z4187 = x4187 + z4188 = x4188 + z4189 = x4189 + z4190 = x4190 + z4191 = x4191 + z4192 = x4192 + z4193 = x4193 + z4194 = x4194 + z4195 = x4195 + z4196 = x4196 + z4197 = x4197 + z4198 = x4198 + z4199 = x4199 + z4200 = x4200 + z4201 = x4201 + z4202 = x4202 + z4203 = x4203 + z4204 = x4204 + z4205 = x4205 + z4206 = x4206 + z4207 = x4207 + z4208 = x4208 + z4209 = x4209 + z4210 = x4210 + z4211 = x4211 + z4212 = x4212 + z4213 = x4213 + z4214 = x4214 + z4215 = x4215 + z4216 = x4216 + z4217 = x4217 + z4218 = x4218 + z4219 = x4219 + z4220 = x4220 + z4221 = x4221 + z4222 = x4222 + z4223 = x4223 + z4224 = x4224 + z4225 = x4225 + z4226 = x4226 + z4227 = x4227 + z4228 = x4228 + z4229 = x4229 + z4230 = x4230 + z4231 = x4231 + z4232 = x4232 + z4233 = x4233 + z4234 = x4234 + z4235 = x4235 + z4236 = x4236 + z4237 = x4237 + z4238 = x4238 + z4239 = x4239 + z4240 = x4240 + z4241 = x4241 + z4242 = x4242 + z4243 = x4243 + z4244 = x4244 + z4245 = x4245 + z4246 = x4246 + z4247 = x4247 + z4248 = x4248 + z4249 = x4249 + z4250 = x4250 + z4251 = x4251 + z4252 = x4252 + z4253 = x4253 + z4254 = x4254 + z4255 = x4255 + z4256 = x4256 + z4257 = x4257 + z4258 = x4258 + z4259 = x4259 + z4260 = x4260 + z4261 = x4261 + z4262 = x4262 + z4263 = x4263 + z4264 = x4264 + z4265 = x4265 + z4266 = x4266 + z4267 = x4267 + z4268 = x4268 + z4269 = x4269 + z4270 = x4270 + z4271 = x4271 + z4272 = x4272 + z4273 = x4273 + z4274 = x4274 + z4275 = x4275 + z4276 = x4276 + z4277 = x4277 + z4278 = x4278 + z4279 = x4279 + z4280 = x4280 + z4281 = x4281 + z4282 = x4282 + z4283 = x4283 + z4284 = x4284 + z4285 = x4285 + z4286 = x4286 + z4287 = x4287 + z4288 = x4288 + z4289 = x4289 + z4290 = x4290 + z4291 = x4291 + z4292 = x4292 + z4293 = x4293 + z4294 = x4294 + z4295 = x4295 + z4296 = x4296 + z4297 = x4297 + z4298 = x4298 + z4299 = x4299 + z4300 = x4300 + z4301 = x4301 + z4302 = x4302 + z4303 = x4303 + z4304 = x4304 + z4305 = x4305 + z4306 = x4306 + z4307 = x4307 + z4308 = x4308 + z4309 = x4309 + z4310 = x4310 + z4311 = x4311 + z4312 = x4312 + z4313 = x4313 + z4314 = x4314 + z4315 = x4315 + z4316 = x4316 + z4317 = x4317 + z4318 = x4318 + z4319 = x4319 + z4320 = x4320 + z4321 = x4321 + z4322 = x4322 + z4323 = x4323 + z4324 = x4324 + z4325 = x4325 + z4326 = x4326 + z4327 = x4327 + z4328 = x4328 + z4329 = x4329 + z4330 = x4330 + z4331 = x4331 + z4332 = x4332 + z4333 = x4333 + z4334 = x4334 + z4335 = x4335 + z4336 = x4336 + z4337 = x4337 + z4338 = x4338 + z4339 = x4339 + z4340 = x4340 + z4341 = x4341 + z4342 = x4342 + z4343 = x4343 + z4344 = x4344 + z4345 = x4345 + z4346 = x4346 + z4347 = x4347 + z4348 = x4348 + z4349 = x4349 + z4350 = x4350 + z4351 = x4351 + z4352 = x4352 + z4353 = x4353 + z4354 = x4354 + z4355 = x4355 + z4356 = x4356 + z4357 = x4357 + z4358 = x4358 + z4359 = x4359 + z4360 = x4360 + z4361 = x4361 + z4362 = x4362 + z4363 = x4363 + z4364 = x4364 + z4365 = x4365 + z4366 = x4366 + z4367 = x4367 + z4368 = x4368 + z4369 = x4369 + z4370 = x4370 + z4371 = x4371 + z4372 = x4372 + z4373 = x4373 + z4374 = x4374 + z4375 = x4375 + z4376 = x4376 + z4377 = x4377 + z4378 = x4378 + z4379 = x4379 + z4380 = x4380 + z4381 = x4381 + z4382 = x4382 + z4383 = x4383 + z4384 = x4384 + z4385 = x4385 + z4386 = x4386 + z4387 = x4387 + z4388 = x4388 + z4389 = x4389 + z4390 = x4390 + z4391 = x4391 + z4392 = x4392 + z4393 = x4393 + z4394 = x4394 + z4395 = x4395 + z4396 = x4396 + z4397 = x4397 + z4398 = x4398 + z4399 = x4399 + z4400 = x4400 + z4401 = x4401 + z4402 = x4402 + z4403 = x4403 + z4404 = x4404 + z4405 = x4405 + z4406 = x4406 + z4407 = x4407 + z4408 = x4408 + z4409 = x4409 + z4410 = x4410 + z4411 = x4411 + z4412 = x4412 + z4413 = x4413 + z4414 = x4414 + z4415 = x4415 + z4416 = x4416 + z4417 = x4417 + z4418 = x4418 + z4419 = x4419 + z4420 = x4420 + z4421 = x4421 + z4422 = x4422 + z4423 = x4423 + z4424 = x4424 + z4425 = x4425 + z4426 = x4426 + z4427 = x4427 + z4428 = x4428 + z4429 = x4429 + z4430 = x4430 + z4431 = x4431 + z4432 = x4432 + z4433 = x4433 + z4434 = x4434 + z4435 = x4435 + z4436 = x4436 + z4437 = x4437 + z4438 = x4438 + z4439 = x4439 + z4440 = x4440 + z4441 = x4441 + z4442 = x4442 + z4443 = x4443 + z4444 = x4444 + z4445 = x4445 + z4446 = x4446 + z4447 = x4447 + z4448 = x4448 + z4449 = x4449 + z4450 = x4450 + z4451 = x4451 + z4452 = x4452 + z4453 = x4453 + z4454 = x4454 + z4455 = x4455 + z4456 = x4456 + z4457 = x4457 + z4458 = x4458 + z4459 = x4459 + z4460 = x4460 + z4461 = x4461 + z4462 = x4462 + z4463 = x4463 + z4464 = x4464 + z4465 = x4465 + z4466 = x4466 + z4467 = x4467 + z4468 = x4468 + z4469 = x4469 + z4470 = x4470 + z4471 = x4471 + z4472 = x4472 + z4473 = x4473 + z4474 = x4474 + z4475 = x4475 + z4476 = x4476 + z4477 = x4477 + z4478 = x4478 + z4479 = x4479 + z4480 = x4480 + z4481 = x4481 + z4482 = x4482 + z4483 = x4483 + z4484 = x4484 + z4485 = x4485 + z4486 = x4486 + z4487 = x4487 + z4488 = x4488 + z4489 = x4489 + z4490 = x4490 + z4491 = x4491 + z4492 = x4492 + z4493 = x4493 + z4494 = x4494 + z4495 = x4495 + z4496 = x4496 + z4497 = x4497 + z4498 = x4498 + z4499 = x4499 + z4500 = x4500 + z4501 = x4501 + z4502 = x4502 + z4503 = x4503 + z4504 = x4504 + z4505 = x4505 + z4506 = x4506 + z4507 = x4507 + z4508 = x4508 + z4509 = x4509 + z4510 = x4510 + z4511 = x4511 + z4512 = x4512 + z4513 = x4513 + z4514 = x4514 + z4515 = x4515 + z4516 = x4516 + z4517 = x4517 + z4518 = x4518 + z4519 = x4519 + z4520 = x4520 + z4521 = x4521 + z4522 = x4522 + z4523 = x4523 + z4524 = x4524 + z4525 = x4525 + z4526 = x4526 + z4527 = x4527 + z4528 = x4528 + z4529 = x4529 + z4530 = x4530 + z4531 = x4531 + z4532 = x4532 + z4533 = x4533 + z4534 = x4534 + z4535 = x4535 + z4536 = x4536 + z4537 = x4537 + z4538 = x4538 + z4539 = x4539 + z4540 = x4540 + z4541 = x4541 + z4542 = x4542 + z4543 = x4543 + z4544 = x4544 + z4545 = x4545 + z4546 = x4546 + z4547 = x4547 + z4548 = x4548 + z4549 = x4549 + z4550 = x4550 + z4551 = x4551 + z4552 = x4552 + z4553 = x4553 + z4554 = x4554 + z4555 = x4555 + z4556 = x4556 + z4557 = x4557 + z4558 = x4558 + z4559 = x4559 + z4560 = x4560 + z4561 = x4561 + z4562 = x4562 + z4563 = x4563 + z4564 = x4564 + z4565 = x4565 + z4566 = x4566 + z4567 = x4567 + z4568 = x4568 + z4569 = x4569 + z4570 = x4570 + z4571 = x4571 + z4572 = x4572 + z4573 = x4573 + z4574 = x4574 + z4575 = x4575 + z4576 = x4576 + z4577 = x4577 + z4578 = x4578 + z4579 = x4579 + z4580 = x4580 + z4581 = x4581 + z4582 = x4582 + z4583 = x4583 + z4584 = x4584 + z4585 = x4585 + z4586 = x4586 + z4587 = x4587 + z4588 = x4588 + z4589 = x4589 + z4590 = x4590 + z4591 = x4591 + z4592 = x4592 + z4593 = x4593 + z4594 = x4594 + z4595 = x4595 + z4596 = x4596 + z4597 = x4597 + z4598 = x4598 + z4599 = x4599 + z4600 = x4600 + z4601 = x4601 + z4602 = x4602 + z4603 = x4603 + z4604 = x4604 + z4605 = x4605 + z4606 = x4606 + z4607 = x4607 + z4608 = x4608 + z4609 = x4609 + z4610 = x4610 + z4611 = x4611 + z4612 = x4612 + z4613 = x4613 + z4614 = x4614 + z4615 = x4615 + z4616 = x4616 + z4617 = x4617 + z4618 = x4618 + z4619 = x4619 + z4620 = x4620 + z4621 = x4621 + z4622 = x4622 + z4623 = x4623 + z4624 = x4624 + z4625 = x4625 + z4626 = x4626 + z4627 = x4627 + z4628 = x4628 + z4629 = x4629 + z4630 = x4630 + z4631 = x4631 + z4632 = x4632 + z4633 = x4633 + z4634 = x4634 + z4635 = x4635 + z4636 = x4636 + z4637 = x4637 + z4638 = x4638 + z4639 = x4639 + z4640 = x4640 + z4641 = x4641 + z4642 = x4642 + z4643 = x4643 + z4644 = x4644 + z4645 = x4645 + z4646 = x4646 + z4647 = x4647 + z4648 = x4648 + z4649 = x4649 + z4650 = x4650 + z4651 = x4651 + z4652 = x4652 + z4653 = x4653 + z4654 = x4654 + z4655 = x4655 + z4656 = x4656 + z4657 = x4657 + z4658 = x4658 + z4659 = x4659 + z4660 = x4660 + z4661 = x4661 + z4662 = x4662 + z4663 = x4663 + z4664 = x4664 + z4665 = x4665 + z4666 = x4666 + z4667 = x4667 + z4668 = x4668 + z4669 = x4669 + z4670 = x4670 + z4671 = x4671 + z4672 = x4672 + z4673 = x4673 + z4674 = x4674 + z4675 = x4675 + z4676 = x4676 + z4677 = x4677 + z4678 = x4678 + z4679 = x4679 + z4680 = x4680 + z4681 = x4681 + z4682 = x4682 + z4683 = x4683 + z4684 = x4684 + z4685 = x4685 + z4686 = x4686 + z4687 = x4687 + z4688 = x4688 + z4689 = x4689 + z4690 = x4690 + z4691 = x4691 + z4692 = x4692 + z4693 = x4693 + z4694 = x4694 + z4695 = x4695 + z4696 = x4696 + z4697 = x4697 + z4698 = x4698 + z4699 = x4699 + z4700 = x4700 + z4701 = x4701 + z4702 = x4702 + z4703 = x4703 + z4704 = x4704 + z4705 = x4705 + z4706 = x4706 + z4707 = x4707 + z4708 = x4708 + z4709 = x4709 + z4710 = x4710 + z4711 = x4711 + z4712 = x4712 + z4713 = x4713 + z4714 = x4714 + z4715 = x4715 + z4716 = x4716 + z4717 = x4717 + z4718 = x4718 + z4719 = x4719 + z4720 = x4720 + z4721 = x4721 + z4722 = x4722 + z4723 = x4723 + z4724 = x4724 + z4725 = x4725 + z4726 = x4726 + z4727 = x4727 + z4728 = x4728 + z4729 = x4729 + z4730 = x4730 + z4731 = x4731 + z4732 = x4732 + z4733 = x4733 + z4734 = x4734 + z4735 = x4735 + z4736 = x4736 + z4737 = x4737 + z4738 = x4738 + z4739 = x4739 + z4740 = x4740 + z4741 = x4741 + z4742 = x4742 + z4743 = x4743 + z4744 = x4744 + z4745 = x4745 + z4746 = x4746 + z4747 = x4747 + z4748 = x4748 + z4749 = x4749 + z4750 = x4750 + z4751 = x4751 + z4752 = x4752 + z4753 = x4753 + z4754 = x4754 + z4755 = x4755 + z4756 = x4756 + z4757 = x4757 + z4758 = x4758 + z4759 = x4759 + z4760 = x4760 + z4761 = x4761 + z4762 = x4762 + z4763 = x4763 + z4764 = x4764 + z4765 = x4765 + z4766 = x4766 + z4767 = x4767 + z4768 = x4768 + z4769 = x4769 + z4770 = x4770 + z4771 = x4771 + z4772 = x4772 + z4773 = x4773 + z4774 = x4774 + z4775 = x4775 + z4776 = x4776 + z4777 = x4777 + z4778 = x4778 + z4779 = x4779 + z4780 = x4780 + z4781 = x4781 + z4782 = x4782 + z4783 = x4783 + z4784 = x4784 + z4785 = x4785 + z4786 = x4786 + z4787 = x4787 + z4788 = x4788 + z4789 = x4789 + z4790 = x4790 + z4791 = x4791 + z4792 = x4792 + z4793 = x4793 + z4794 = x4794 + z4795 = x4795 + z4796 = x4796 + z4797 = x4797 + z4798 = x4798 + z4799 = x4799 + z4800 = x4800 + z4801 = x4801 + z4802 = x4802 + z4803 = x4803 + z4804 = x4804 + z4805 = x4805 + z4806 = x4806 + z4807 = x4807 + z4808 = x4808 + z4809 = x4809 + z4810 = x4810 + z4811 = x4811 + z4812 = x4812 + z4813 = x4813 + z4814 = x4814 + z4815 = x4815 + z4816 = x4816 + z4817 = x4817 + z4818 = x4818 + z4819 = x4819 + z4820 = x4820 + z4821 = x4821 + z4822 = x4822 + z4823 = x4823 + z4824 = x4824 + z4825 = x4825 + z4826 = x4826 + z4827 = x4827 + z4828 = x4828 + z4829 = x4829 + z4830 = x4830 + z4831 = x4831 + z4832 = x4832 + z4833 = x4833 + z4834 = x4834 + z4835 = x4835 + z4836 = x4836 + z4837 = x4837 + z4838 = x4838 + z4839 = x4839 + z4840 = x4840 + z4841 = x4841 + z4842 = x4842 + z4843 = x4843 + z4844 = x4844 + z4845 = x4845 + z4846 = x4846 + z4847 = x4847 + z4848 = x4848 + z4849 = x4849 + z4850 = x4850 + z4851 = x4851 + z4852 = x4852 + z4853 = x4853 + z4854 = x4854 + z4855 = x4855 + z4856 = x4856 + z4857 = x4857 + z4858 = x4858 + z4859 = x4859 + z4860 = x4860 + z4861 = x4861 + z4862 = x4862 + z4863 = x4863 + z4864 = x4864 + z4865 = x4865 + z4866 = x4866 + z4867 = x4867 + z4868 = x4868 + z4869 = x4869 + z4870 = x4870 + z4871 = x4871 + z4872 = x4872 + z4873 = x4873 + z4874 = x4874 + z4875 = x4875 + z4876 = x4876 + z4877 = x4877 + z4878 = x4878 + z4879 = x4879 + z4880 = x4880 + z4881 = x4881 + z4882 = x4882 + z4883 = x4883 + z4884 = x4884 + z4885 = x4885 + z4886 = x4886 + z4887 = x4887 + z4888 = x4888 + z4889 = x4889 + z4890 = x4890 + z4891 = x4891 + z4892 = x4892 + z4893 = x4893 + z4894 = x4894 + z4895 = x4895 + z4896 = x4896 + z4897 = x4897 + z4898 = x4898 + z4899 = x4899 + z4900 = x4900 + z4901 = x4901 + z4902 = x4902 + z4903 = x4903 + z4904 = x4904 + z4905 = x4905 + z4906 = x4906 + z4907 = x4907 + z4908 = x4908 + z4909 = x4909 + z4910 = x4910 + z4911 = x4911 + z4912 = x4912 + z4913 = x4913 + z4914 = x4914 + z4915 = x4915 + z4916 = x4916 + z4917 = x4917 + z4918 = x4918 + z4919 = x4919 + z4920 = x4920 + z4921 = x4921 + z4922 = x4922 + z4923 = x4923 + z4924 = x4924 + z4925 = x4925 + z4926 = x4926 + z4927 = x4927 + z4928 = x4928 + z4929 = x4929 + z4930 = x4930 + z4931 = x4931 + z4932 = x4932 + z4933 = x4933 + z4934 = x4934 + z4935 = x4935 + z4936 = x4936 + z4937 = x4937 + z4938 = x4938 + z4939 = x4939 + z4940 = x4940 + z4941 = x4941 + z4942 = x4942 + z4943 = x4943 + z4944 = x4944 + z4945 = x4945 + z4946 = x4946 + z4947 = x4947 + z4948 = x4948 + z4949 = x4949 + z4950 = x4950 + z4951 = x4951 + z4952 = x4952 + z4953 = x4953 + z4954 = x4954 + z4955 = x4955 + z4956 = x4956 + z4957 = x4957 + z4958 = x4958 + z4959 = x4959 + z4960 = x4960 + z4961 = x4961 + z4962 = x4962 + z4963 = x4963 + z4964 = x4964 + z4965 = x4965 + z4966 = x4966 + z4967 = x4967 + z4968 = x4968 + z4969 = x4969 + z4970 = x4970 + z4971 = x4971 + z4972 = x4972 + z4973 = x4973 + z4974 = x4974 + z4975 = x4975 + z4976 = x4976 + z4977 = x4977 + z4978 = x4978 + z4979 = x4979 + z4980 = x4980 + z4981 = x4981 + z4982 = x4982 + z4983 = x4983 + z4984 = x4984 + z4985 = x4985 + z4986 = x4986 + z4987 = x4987 + z4988 = x4988 + z4989 = x4989 + z4990 = x4990 + z4991 = x4991 + z4992 = x4992 + z4993 = x4993 + z4994 = x4994 + z4995 = x4995 + z4996 = x4996 + z4997 = x4997 + z4998 = x4998 + z4999 = x4999 + z5000 = x5000 + z5001 = x5001 + z5002 = x5002 + z5003 = x5003 + z5004 = x5004 + z5005 = x5005 + z5006 = x5006 + z5007 = x5007 + z5008 = x5008 + z5009 = x5009 + z5010 = x5010 + z5011 = x5011 + z5012 = x5012 + z5013 = x5013 + z5014 = x5014 + z5015 = x5015 + z5016 = x5016 + z5017 = x5017 + z5018 = x5018 + z5019 = x5019 + z5020 = x5020 + z5021 = x5021 + z5022 = x5022 + z5023 = x5023 + z5024 = x5024 + z5025 = x5025 + z5026 = x5026 + z5027 = x5027 + z5028 = x5028 + z5029 = x5029 + z5030 = x5030 + z5031 = x5031 + z5032 = x5032 + z5033 = x5033 + z5034 = x5034 + z5035 = x5035 + z5036 = x5036 + z5037 = x5037 + z5038 = x5038 + z5039 = x5039 + z5040 = x5040 + z5041 = x5041 + z5042 = x5042 + z5043 = x5043 + z5044 = x5044 + z5045 = x5045 + z5046 = x5046 + z5047 = x5047 + z5048 = x5048 + z5049 = x5049 + z5050 = x5050 + z5051 = x5051 + z5052 = x5052 + z5053 = x5053 + z5054 = x5054 + z5055 = x5055 + z5056 = x5056 + z5057 = x5057 + z5058 = x5058 + z5059 = x5059 + z5060 = x5060 + z5061 = x5061 + z5062 = x5062 + z5063 = x5063 + z5064 = x5064 + z5065 = x5065 + z5066 = x5066 + z5067 = x5067 + z5068 = x5068 + z5069 = x5069 + z5070 = x5070 + z5071 = x5071 + z5072 = x5072 + z5073 = x5073 + z5074 = x5074 + z5075 = x5075 + z5076 = x5076 + z5077 = x5077 + z5078 = x5078 + z5079 = x5079 + z5080 = x5080 + z5081 = x5081 + z5082 = x5082 + z5083 = x5083 + z5084 = x5084 + z5085 = x5085 + z5086 = x5086 + z5087 = x5087 + z5088 = x5088 + z5089 = x5089 + z5090 = x5090 + z5091 = x5091 + z5092 = x5092 + z5093 = x5093 + z5094 = x5094 + z5095 = x5095 + z5096 = x5096 + z5097 = x5097 + z5098 = x5098 + z5099 = x5099 + z5100 = x5100 + z5101 = x5101 + z5102 = x5102 + z5103 = x5103 + z5104 = x5104 + z5105 = x5105 + z5106 = x5106 + z5107 = x5107 + z5108 = x5108 + z5109 = x5109 + z5110 = x5110 + z5111 = x5111 + z5112 = x5112 + z5113 = x5113 + z5114 = x5114 + z5115 = x5115 + z5116 = x5116 + z5117 = x5117 + z5118 = x5118 + z5119 = x5119 + z5120 = x5120 + z5121 = x5121 + z5122 = x5122 + z5123 = x5123 + z5124 = x5124 + z5125 = x5125 + z5126 = x5126 + z5127 = x5127 + z5128 = x5128 + z5129 = x5129 + z5130 = x5130 + z5131 = x5131 + z5132 = x5132 + z5133 = x5133 + z5134 = x5134 + z5135 = x5135 + z5136 = x5136 + z5137 = x5137 + z5138 = x5138 + z5139 = x5139 + z5140 = x5140 + z5141 = x5141 + z5142 = x5142 + z5143 = x5143 + z5144 = x5144 + z5145 = x5145 + z5146 = x5146 + z5147 = x5147 + z5148 = x5148 + z5149 = x5149 + z5150 = x5150 + z5151 = x5151 + z5152 = x5152 + z5153 = x5153 + z5154 = x5154 + z5155 = x5155 + z5156 = x5156 + z5157 = x5157 + z5158 = x5158 + z5159 = x5159 + z5160 = x5160 + z5161 = x5161 + z5162 = x5162 + z5163 = x5163 + z5164 = x5164 + z5165 = x5165 + z5166 = x5166 + z5167 = x5167 + z5168 = x5168 + z5169 = x5169 + z5170 = x5170 + z5171 = x5171 + z5172 = x5172 + z5173 = x5173 + z5174 = x5174 + z5175 = x5175 + z5176 = x5176 + z5177 = x5177 + z5178 = x5178 + z5179 = x5179 + z5180 = x5180 + z5181 = x5181 + z5182 = x5182 + z5183 = x5183 + z5184 = x5184 + z5185 = x5185 + z5186 = x5186 + z5187 = x5187 + z5188 = x5188 + z5189 = x5189 + z5190 = x5190 + z5191 = x5191 + z5192 = x5192 + z5193 = x5193 + z5194 = x5194 + z5195 = x5195 + z5196 = x5196 + z5197 = x5197 + z5198 = x5198 + z5199 = x5199 + z5200 = x5200 + z5201 = x5201 + z5202 = x5202 + z5203 = x5203 + z5204 = x5204 + z5205 = x5205 + z5206 = x5206 + z5207 = x5207 + z5208 = x5208 + z5209 = x5209 + z5210 = x5210 + z5211 = x5211 + z5212 = x5212 + z5213 = x5213 + z5214 = x5214 + z5215 = x5215 + z5216 = x5216 + z5217 = x5217 + z5218 = x5218 + z5219 = x5219 + z5220 = x5220 + z5221 = x5221 + z5222 = x5222 + z5223 = x5223 + z5224 = x5224 + z5225 = x5225 + z5226 = x5226 + z5227 = x5227 + z5228 = x5228 + z5229 = x5229 + z5230 = x5230 + z5231 = x5231 + z5232 = x5232 + z5233 = x5233 + z5234 = x5234 + z5235 = x5235 + z5236 = x5236 + z5237 = x5237 + z5238 = x5238 + z5239 = x5239 + z5240 = x5240 + z5241 = x5241 + z5242 = x5242 + z5243 = x5243 + z5244 = x5244 + z5245 = x5245 + z5246 = x5246 + z5247 = x5247 + z5248 = x5248 + z5249 = x5249 + z5250 = x5250 + z5251 = x5251 + z5252 = x5252 + z5253 = x5253 + z5254 = x5254 + z5255 = x5255 + z5256 = x5256 + z5257 = x5257 + z5258 = x5258 + z5259 = x5259 + z5260 = x5260 + z5261 = x5261 + z5262 = x5262 + z5263 = x5263 + z5264 = x5264 + z5265 = x5265 + z5266 = x5266 + z5267 = x5267 + z5268 = x5268 + z5269 = x5269 + z5270 = x5270 + z5271 = x5271 + z5272 = x5272 + z5273 = x5273 + z5274 = x5274 + z5275 = x5275 + z5276 = x5276 + z5277 = x5277 + z5278 = x5278 + z5279 = x5279 + z5280 = x5280 + z5281 = x5281 + z5282 = x5282 + z5283 = x5283 + z5284 = x5284 + z5285 = x5285 + z5286 = x5286 + z5287 = x5287 + z5288 = x5288 + z5289 = x5289 + z5290 = x5290 + z5291 = x5291 + z5292 = x5292 + z5293 = x5293 + z5294 = x5294 + z5295 = x5295 + z5296 = x5296 + z5297 = x5297 + z5298 = x5298 + z5299 = x5299 + z5300 = x5300 + z5301 = x5301 + z5302 = x5302 + z5303 = x5303 + z5304 = x5304 + z5305 = x5305 + z5306 = x5306 + z5307 = x5307 + z5308 = x5308 + z5309 = x5309 + z5310 = x5310 + z5311 = x5311 + z5312 = x5312 + z5313 = x5313 + z5314 = x5314 + z5315 = x5315 + z5316 = x5316 + z5317 = x5317 + z5318 = x5318 + z5319 = x5319 + z5320 = x5320 + z5321 = x5321 + z5322 = x5322 + z5323 = x5323 + z5324 = x5324 + z5325 = x5325 + z5326 = x5326 + z5327 = x5327 + z5328 = x5328 + z5329 = x5329 + z5330 = x5330 + z5331 = x5331 + z5332 = x5332 + z5333 = x5333 + z5334 = x5334 + z5335 = x5335 + z5336 = x5336 + z5337 = x5337 + z5338 = x5338 + z5339 = x5339 + z5340 = x5340 + z5341 = x5341 + z5342 = x5342 + z5343 = x5343 + z5344 = x5344 + z5345 = x5345 + z5346 = x5346 + z5347 = x5347 + z5348 = x5348 + z5349 = x5349 + z5350 = x5350 + z5351 = x5351 + z5352 = x5352 + z5353 = x5353 + z5354 = x5354 + z5355 = x5355 + z5356 = x5356 + z5357 = x5357 + z5358 = x5358 + z5359 = x5359 + z5360 = x5360 + z5361 = x5361 + z5362 = x5362 + z5363 = x5363 + z5364 = x5364 + z5365 = x5365 + z5366 = x5366 + z5367 = x5367 + z5368 = x5368 + z5369 = x5369 + z5370 = x5370 + z5371 = x5371 + z5372 = x5372 + z5373 = x5373 + z5374 = x5374 + z5375 = x5375 + z5376 = x5376 + z5377 = x5377 + z5378 = x5378 + z5379 = x5379 + z5380 = x5380 + z5381 = x5381 + z5382 = x5382 + z5383 = x5383 + z5384 = x5384 + z5385 = x5385 + z5386 = x5386 + z5387 = x5387 + z5388 = x5388 + z5389 = x5389 + z5390 = x5390 + z5391 = x5391 + z5392 = x5392 + z5393 = x5393 + z5394 = x5394 + z5395 = x5395 + z5396 = x5396 + z5397 = x5397 + z5398 = x5398 + z5399 = x5399 + z5400 = x5400 + z5401 = x5401 + z5402 = x5402 + z5403 = x5403 + z5404 = x5404 + z5405 = x5405 + z5406 = x5406 + z5407 = x5407 + z5408 = x5408 + z5409 = x5409 + z5410 = x5410 + z5411 = x5411 + z5412 = x5412 + z5413 = x5413 + z5414 = x5414 + z5415 = x5415 + z5416 = x5416 + z5417 = x5417 + z5418 = x5418 + z5419 = x5419 + z5420 = x5420 + z5421 = x5421 + z5422 = x5422 + z5423 = x5423 + z5424 = x5424 + z5425 = x5425 + z5426 = x5426 + z5427 = x5427 + z5428 = x5428 + z5429 = x5429 + z5430 = x5430 + z5431 = x5431 + z5432 = x5432 + z5433 = x5433 + z5434 = x5434 + z5435 = x5435 + z5436 = x5436 + z5437 = x5437 + z5438 = x5438 + z5439 = x5439 + z5440 = x5440 + z5441 = x5441 + z5442 = x5442 + z5443 = x5443 + z5444 = x5444 + z5445 = x5445 + z5446 = x5446 + z5447 = x5447 + z5448 = x5448 + z5449 = x5449 + z5450 = x5450 + z5451 = x5451 + z5452 = x5452 + z5453 = x5453 + z5454 = x5454 + z5455 = x5455 + z5456 = x5456 + z5457 = x5457 + z5458 = x5458 + z5459 = x5459 + z5460 = x5460 + z5461 = x5461 + z5462 = x5462 + z5463 = x5463 + z5464 = x5464 + z5465 = x5465 + z5466 = x5466 + z5467 = x5467 + z5468 = x5468 + z5469 = x5469 + z5470 = x5470 + z5471 = x5471 + z5472 = x5472 + z5473 = x5473 + z5474 = x5474 + z5475 = x5475 + z5476 = x5476 + z5477 = x5477 + z5478 = x5478 + z5479 = x5479 + z5480 = x5480 + z5481 = x5481 + z5482 = x5482 + z5483 = x5483 + z5484 = x5484 + z5485 = x5485 + z5486 = x5486 + z5487 = x5487 + z5488 = x5488 + z5489 = x5489 + z5490 = x5490 + z5491 = x5491 + z5492 = x5492 + z5493 = x5493 + z5494 = x5494 + z5495 = x5495 + z5496 = x5496 + z5497 = x5497 + z5498 = x5498 + z5499 = x5499 + z5500 = x5500 + z5501 = x5501 + z5502 = x5502 + z5503 = x5503 + z5504 = x5504 + z5505 = x5505 + z5506 = x5506 + z5507 = x5507 + z5508 = x5508 + z5509 = x5509 + z5510 = x5510 + z5511 = x5511 + z5512 = x5512 + z5513 = x5513 + z5514 = x5514 + z5515 = x5515 + z5516 = x5516 + z5517 = x5517 + z5518 = x5518 + z5519 = x5519 + z5520 = x5520 + z5521 = x5521 + z5522 = x5522 + z5523 = x5523 + z5524 = x5524 + z5525 = x5525 + z5526 = x5526 + z5527 = x5527 + z5528 = x5528 + z5529 = x5529 + z5530 = x5530 + z5531 = x5531 + z5532 = x5532 + z5533 = x5533 + z5534 = x5534 + z5535 = x5535 + z5536 = x5536 + z5537 = x5537 + z5538 = x5538 + z5539 = x5539 + z5540 = x5540 + z5541 = x5541 + z5542 = x5542 + z5543 = x5543 + z5544 = x5544 + z5545 = x5545 + z5546 = x5546 + z5547 = x5547 + z5548 = x5548 + z5549 = x5549 + z5550 = x5550 + z5551 = x5551 + z5552 = x5552 + z5553 = x5553 + z5554 = x5554 + z5555 = x5555 + z5556 = x5556 + z5557 = x5557 + z5558 = x5558 + z5559 = x5559 + z5560 = x5560 + z5561 = x5561 + z5562 = x5562 + z5563 = x5563 + z5564 = x5564 + z5565 = x5565 + z5566 = x5566 + z5567 = x5567 + z5568 = x5568 + z5569 = x5569 + z5570 = x5570 + z5571 = x5571 + z5572 = x5572 + z5573 = x5573 + z5574 = x5574 + z5575 = x5575 + z5576 = x5576 + z5577 = x5577 + z5578 = x5578 + z5579 = x5579 + z5580 = x5580 + z5581 = x5581 + z5582 = x5582 + z5583 = x5583 + z5584 = x5584 + z5585 = x5585 + z5586 = x5586 + z5587 = x5587 + z5588 = x5588 + z5589 = x5589 + z5590 = x5590 + z5591 = x5591 + z5592 = x5592 + z5593 = x5593 + z5594 = x5594 + z5595 = x5595 + z5596 = x5596 + z5597 = x5597 + z5598 = x5598 + z5599 = x5599 + z5600 = x5600 + z5601 = x5601 + z5602 = x5602 + z5603 = x5603 + z5604 = x5604 + z5605 = x5605 + z5606 = x5606 + z5607 = x5607 + z5608 = x5608 + z5609 = x5609 + z5610 = x5610 + z5611 = x5611 + z5612 = x5612 + z5613 = x5613 + z5614 = x5614 + z5615 = x5615 + z5616 = x5616 + z5617 = x5617 + z5618 = x5618 + z5619 = x5619 + z5620 = x5620 + z5621 = x5621 + z5622 = x5622 + z5623 = x5623 + z5624 = x5624 + z5625 = x5625 + z5626 = x5626 + z5627 = x5627 + z5628 = x5628 + z5629 = x5629 + z5630 = x5630 + z5631 = x5631 + z5632 = x5632 + z5633 = x5633 + z5634 = x5634 + z5635 = x5635 + z5636 = x5636 + z5637 = x5637 + z5638 = x5638 + z5639 = x5639 + z5640 = x5640 + z5641 = x5641 + z5642 = x5642 + z5643 = x5643 + z5644 = x5644 + z5645 = x5645 + z5646 = x5646 + z5647 = x5647 + z5648 = x5648 + z5649 = x5649 + z5650 = x5650 + z5651 = x5651 + z5652 = x5652 + z5653 = x5653 + z5654 = x5654 + z5655 = x5655 + z5656 = x5656 + z5657 = x5657 + z5658 = x5658 + z5659 = x5659 + z5660 = x5660 + z5661 = x5661 + z5662 = x5662 + z5663 = x5663 + z5664 = x5664 + z5665 = x5665 + z5666 = x5666 + z5667 = x5667 + z5668 = x5668 + z5669 = x5669 + z5670 = x5670 + z5671 = x5671 + z5672 = x5672 + z5673 = x5673 + z5674 = x5674 + z5675 = x5675 + z5676 = x5676 + z5677 = x5677 + z5678 = x5678 + z5679 = x5679 + z5680 = x5680 + z5681 = x5681 + z5682 = x5682 + z5683 = x5683 + z5684 = x5684 + z5685 = x5685 + z5686 = x5686 + z5687 = x5687 + z5688 = x5688 + z5689 = x5689 + z5690 = x5690 + z5691 = x5691 + z5692 = x5692 + z5693 = x5693 + z5694 = x5694 + z5695 = x5695 + z5696 = x5696 + z5697 = x5697 + z5698 = x5698 + z5699 = x5699 + z5700 = x5700 + z5701 = x5701 + z5702 = x5702 + z5703 = x5703 + z5704 = x5704 + z5705 = x5705 + z5706 = x5706 + z5707 = x5707 + z5708 = x5708 + z5709 = x5709 + z5710 = x5710 + z5711 = x5711 + z5712 = x5712 + z5713 = x5713 + z5714 = x5714 + z5715 = x5715 + z5716 = x5716 + z5717 = x5717 + z5718 = x5718 + z5719 = x5719 + z5720 = x5720 + z5721 = x5721 + z5722 = x5722 + z5723 = x5723 + z5724 = x5724 + z5725 = x5725 + z5726 = x5726 + z5727 = x5727 + z5728 = x5728 + z5729 = x5729 + z5730 = x5730 + z5731 = x5731 + z5732 = x5732 + z5733 = x5733 + z5734 = x5734 + z5735 = x5735 + z5736 = x5736 + z5737 = x5737 + z5738 = x5738 + z5739 = x5739 + z5740 = x5740 + z5741 = x5741 + z5742 = x5742 + z5743 = x5743 + z5744 = x5744 + z5745 = x5745 + z5746 = x5746 + z5747 = x5747 + z5748 = x5748 + z5749 = x5749 + z5750 = x5750 + z5751 = x5751 + z5752 = x5752 + z5753 = x5753 + z5754 = x5754 + z5755 = x5755 + z5756 = x5756 + z5757 = x5757 + z5758 = x5758 + z5759 = x5759 + z5760 = x5760 + z5761 = x5761 + z5762 = x5762 + z5763 = x5763 + z5764 = x5764 + z5765 = x5765 + z5766 = x5766 + z5767 = x5767 + z5768 = x5768 + z5769 = x5769 + z5770 = x5770 + z5771 = x5771 + z5772 = x5772 + z5773 = x5773 + z5774 = x5774 + z5775 = x5775 + z5776 = x5776 + z5777 = x5777 + z5778 = x5778 + z5779 = x5779 + z5780 = x5780 + z5781 = x5781 + z5782 = x5782 + z5783 = x5783 + z5784 = x5784 + z5785 = x5785 + z5786 = x5786 + z5787 = x5787 + z5788 = x5788 + z5789 = x5789 + z5790 = x5790 + z5791 = x5791 + z5792 = x5792 + z5793 = x5793 + z5794 = x5794 + z5795 = x5795 + z5796 = x5796 + z5797 = x5797 + z5798 = x5798 + z5799 = x5799 + z5800 = x5800 + z5801 = x5801 + z5802 = x5802 + z5803 = x5803 + z5804 = x5804 + z5805 = x5805 + z5806 = x5806 + z5807 = x5807 + z5808 = x5808 + z5809 = x5809 + z5810 = x5810 + z5811 = x5811 + z5812 = x5812 + z5813 = x5813 + z5814 = x5814 + z5815 = x5815 + z5816 = x5816 + z5817 = x5817 + z5818 = x5818 + z5819 = x5819 + z5820 = x5820 + z5821 = x5821 + z5822 = x5822 + z5823 = x5823 + z5824 = x5824 + z5825 = x5825 + z5826 = x5826 + z5827 = x5827 + z5828 = x5828 + z5829 = x5829 + z5830 = x5830 + z5831 = x5831 + z5832 = x5832 + z5833 = x5833 + z5834 = x5834 + z5835 = x5835 + z5836 = x5836 + z5837 = x5837 + z5838 = x5838 + z5839 = x5839 + z5840 = x5840 + z5841 = x5841 + z5842 = x5842 + z5843 = x5843 + z5844 = x5844 + z5845 = x5845 + z5846 = x5846 + z5847 = x5847 + z5848 = x5848 + z5849 = x5849 + z5850 = x5850 + z5851 = x5851 + z5852 = x5852 + z5853 = x5853 + z5854 = x5854 + z5855 = x5855 + z5856 = x5856 + z5857 = x5857 + z5858 = x5858 + z5859 = x5859 + z5860 = x5860 + z5861 = x5861 + z5862 = x5862 + z5863 = x5863 + z5864 = x5864 + z5865 = x5865 + z5866 = x5866 + z5867 = x5867 + z5868 = x5868 + z5869 = x5869 + z5870 = x5870 + z5871 = x5871 + z5872 = x5872 + z5873 = x5873 + z5874 = x5874 + z5875 = x5875 + z5876 = x5876 + z5877 = x5877 + z5878 = x5878 + z5879 = x5879 + z5880 = x5880 + z5881 = x5881 + z5882 = x5882 + z5883 = x5883 + z5884 = x5884 + z5885 = x5885 + z5886 = x5886 + z5887 = x5887 + z5888 = x5888 + z5889 = x5889 + z5890 = x5890 + z5891 = x5891 + z5892 = x5892 + z5893 = x5893 + z5894 = x5894 + z5895 = x5895 + z5896 = x5896 + z5897 = x5897 + z5898 = x5898 + z5899 = x5899 + z5900 = x5900 + z5901 = x5901 + z5902 = x5902 + z5903 = x5903 + z5904 = x5904 + z5905 = x5905 + z5906 = x5906 + z5907 = x5907 + z5908 = x5908 + z5909 = x5909 + z5910 = x5910 + z5911 = x5911 + z5912 = x5912 + z5913 = x5913 + z5914 = x5914 + z5915 = x5915 + z5916 = x5916 + z5917 = x5917 + z5918 = x5918 + z5919 = x5919 + z5920 = x5920 + z5921 = x5921 + z5922 = x5922 + z5923 = x5923 + z5924 = x5924 + z5925 = x5925 + z5926 = x5926 + z5927 = x5927 + z5928 = x5928 + z5929 = x5929 + z5930 = x5930 + z5931 = x5931 + z5932 = x5932 + z5933 = x5933 + z5934 = x5934 + z5935 = x5935 + z5936 = x5936 + z5937 = x5937 + z5938 = x5938 + z5939 = x5939 + z5940 = x5940 + z5941 = x5941 + z5942 = x5942 + z5943 = x5943 + z5944 = x5944 + z5945 = x5945 + z5946 = x5946 + z5947 = x5947 + z5948 = x5948 + z5949 = x5949 + z5950 = x5950 + z5951 = x5951 + z5952 = x5952 + z5953 = x5953 + z5954 = x5954 + z5955 = x5955 + z5956 = x5956 + z5957 = x5957 + z5958 = x5958 + z5959 = x5959 + z5960 = x5960 + z5961 = x5961 + z5962 = x5962 + z5963 = x5963 + z5964 = x5964 + z5965 = x5965 + z5966 = x5966 + z5967 = x5967 + z5968 = x5968 + z5969 = x5969 + z5970 = x5970 + z5971 = x5971 + z5972 = x5972 + z5973 = x5973 + z5974 = x5974 + z5975 = x5975 + z5976 = x5976 + z5977 = x5977 + z5978 = x5978 + z5979 = x5979 + z5980 = x5980 + z5981 = x5981 + z5982 = x5982 + z5983 = x5983 + z5984 = x5984 + z5985 = x5985 + z5986 = x5986 + z5987 = x5987 + z5988 = x5988 + z5989 = x5989 + z5990 = x5990 + z5991 = x5991 + z5992 = x5992 + z5993 = x5993 + z5994 = x5994 + z5995 = x5995 + z5996 = x5996 + z5997 = x5997 + z5998 = x5998 + z5999 = x5999 + z6000 = x6000 + z6001 = x6001 + z6002 = x6002 + z6003 = x6003 + z6004 = x6004 + z6005 = x6005 + z6006 = x6006 + z6007 = x6007 + z6008 = x6008 + z6009 = x6009 + z6010 = x6010 + z6011 = x6011 + z6012 = x6012 + z6013 = x6013 + z6014 = x6014 + z6015 = x6015 + z6016 = x6016 + z6017 = x6017 + z6018 = x6018 + z6019 = x6019 + z6020 = x6020 + z6021 = x6021 + z6022 = x6022 + z6023 = x6023 + z6024 = x6024 + z6025 = x6025 + z6026 = x6026 + z6027 = x6027 + z6028 = x6028 + z6029 = x6029 + z6030 = x6030 + z6031 = x6031 + z6032 = x6032 + z6033 = x6033 + z6034 = x6034 + z6035 = x6035 + z6036 = x6036 + z6037 = x6037 + z6038 = x6038 + z6039 = x6039 + z6040 = x6040 + z6041 = x6041 + z6042 = x6042 + z6043 = x6043 + z6044 = x6044 + z6045 = x6045 + z6046 = x6046 + z6047 = x6047 + z6048 = x6048 + z6049 = x6049 + z6050 = x6050 + z6051 = x6051 + z6052 = x6052 + z6053 = x6053 + z6054 = x6054 + z6055 = x6055 + z6056 = x6056 + z6057 = x6057 + z6058 = x6058 + z6059 = x6059 + z6060 = x6060 + z6061 = x6061 + z6062 = x6062 + z6063 = x6063 + z6064 = x6064 + z6065 = x6065 + z6066 = x6066 + z6067 = x6067 + z6068 = x6068 + z6069 = x6069 + z6070 = x6070 + z6071 = x6071 + z6072 = x6072 + z6073 = x6073 + z6074 = x6074 + z6075 = x6075 + z6076 = x6076 + z6077 = x6077 + z6078 = x6078 + z6079 = x6079 + z6080 = x6080 + z6081 = x6081 + z6082 = x6082 + z6083 = x6083 + z6084 = x6084 + z6085 = x6085 + z6086 = x6086 + z6087 = x6087 + z6088 = x6088 + z6089 = x6089 + z6090 = x6090 + z6091 = x6091 + z6092 = x6092 + z6093 = x6093 + z6094 = x6094 + z6095 = x6095 + z6096 = x6096 + z6097 = x6097 + z6098 = x6098 + z6099 = x6099 + z6100 = x6100 + z6101 = x6101 + z6102 = x6102 + z6103 = x6103 + z6104 = x6104 + z6105 = x6105 + z6106 = x6106 + z6107 = x6107 + z6108 = x6108 + z6109 = x6109 + z6110 = x6110 + z6111 = x6111 + z6112 = x6112 + z6113 = x6113 + z6114 = x6114 + z6115 = x6115 + z6116 = x6116 + z6117 = x6117 + z6118 = x6118 + z6119 = x6119 + z6120 = x6120 + z6121 = x6121 + z6122 = x6122 + z6123 = x6123 + z6124 = x6124 + z6125 = x6125 + z6126 = x6126 + z6127 = x6127 + z6128 = x6128 + z6129 = x6129 + z6130 = x6130 + z6131 = x6131 + z6132 = x6132 + z6133 = x6133 + z6134 = x6134 + z6135 = x6135 + z6136 = x6136 + z6137 = x6137 + z6138 = x6138 + z6139 = x6139 + z6140 = x6140 + z6141 = x6141 + z6142 = x6142 + z6143 = x6143 + z6144 = x6144 + z6145 = x6145 + z6146 = x6146 + z6147 = x6147 + z6148 = x6148 + z6149 = x6149 + z6150 = x6150 + z6151 = x6151 + z6152 = x6152 + z6153 = x6153 + z6154 = x6154 + z6155 = x6155 + z6156 = x6156 + z6157 = x6157 + z6158 = x6158 + z6159 = x6159 + z6160 = x6160 + z6161 = x6161 + z6162 = x6162 + z6163 = x6163 + z6164 = x6164 + z6165 = x6165 + z6166 = x6166 + z6167 = x6167 + z6168 = x6168 + z6169 = x6169 + z6170 = x6170 + z6171 = x6171 + z6172 = x6172 + z6173 = x6173 + z6174 = x6174 + z6175 = x6175 + z6176 = x6176 + z6177 = x6177 + z6178 = x6178 + z6179 = x6179 + z6180 = x6180 + z6181 = x6181 + z6182 = x6182 + z6183 = x6183 + z6184 = x6184 + z6185 = x6185 + z6186 = x6186 + z6187 = x6187 + z6188 = x6188 + z6189 = x6189 + z6190 = x6190 + z6191 = x6191 + z6192 = x6192 + z6193 = x6193 + z6194 = x6194 + z6195 = x6195 + z6196 = x6196 + z6197 = x6197 + z6198 = x6198 + z6199 = x6199 + z6200 = x6200 + z6201 = x6201 + z6202 = x6202 + z6203 = x6203 + z6204 = x6204 + z6205 = x6205 + z6206 = x6206 + z6207 = x6207 + z6208 = x6208 + z6209 = x6209 + z6210 = x6210 + z6211 = x6211 + z6212 = x6212 + z6213 = x6213 + z6214 = x6214 + z6215 = x6215 + z6216 = x6216 + z6217 = x6217 + z6218 = x6218 + z6219 = x6219 + z6220 = x6220 + z6221 = x6221 + z6222 = x6222 + z6223 = x6223 + z6224 = x6224 + z6225 = x6225 + z6226 = x6226 + z6227 = x6227 + z6228 = x6228 + z6229 = x6229 + z6230 = x6230 + z6231 = x6231 + z6232 = x6232 + z6233 = x6233 + z6234 = x6234 + z6235 = x6235 + z6236 = x6236 + z6237 = x6237 + z6238 = x6238 + z6239 = x6239 + z6240 = x6240 + z6241 = x6241 + z6242 = x6242 + z6243 = x6243 + z6244 = x6244 + z6245 = x6245 + z6246 = x6246 + z6247 = x6247 + z6248 = x6248 + z6249 = x6249 + z6250 = x6250 + z6251 = x6251 + z6252 = x6252 + z6253 = x6253 + z6254 = x6254 + z6255 = x6255 + z6256 = x6256 + z6257 = x6257 + z6258 = x6258 + z6259 = x6259 + z6260 = x6260 + z6261 = x6261 + z6262 = x6262 + z6263 = x6263 + z6264 = x6264 + z6265 = x6265 + z6266 = x6266 + z6267 = x6267 + z6268 = x6268 + z6269 = x6269 + z6270 = x6270 + z6271 = x6271 + z6272 = x6272 + z6273 = x6273 + z6274 = x6274 + z6275 = x6275 + z6276 = x6276 + z6277 = x6277 + z6278 = x6278 + z6279 = x6279 + z6280 = x6280 + z6281 = x6281 + z6282 = x6282 + z6283 = x6283 + z6284 = x6284 + z6285 = x6285 + z6286 = x6286 + z6287 = x6287 + z6288 = x6288 + z6289 = x6289 + z6290 = x6290 + z6291 = x6291 + z6292 = x6292 + z6293 = x6293 + z6294 = x6294 + z6295 = x6295 + z6296 = x6296 + z6297 = x6297 + z6298 = x6298 + z6299 = x6299 + z6300 = x6300 + z6301 = x6301 + z6302 = x6302 + z6303 = x6303 + z6304 = x6304 + z6305 = x6305 + z6306 = x6306 + z6307 = x6307 + z6308 = x6308 + z6309 = x6309 + z6310 = x6310 + z6311 = x6311 + z6312 = x6312 + z6313 = x6313 + z6314 = x6314 + z6315 = x6315 + z6316 = x6316 + z6317 = x6317 + z6318 = x6318 + z6319 = x6319 + z6320 = x6320 + z6321 = x6321 + z6322 = x6322 + z6323 = x6323 + z6324 = x6324 + z6325 = x6325 + z6326 = x6326 + z6327 = x6327 + z6328 = x6328 + z6329 = x6329 + z6330 = x6330 + z6331 = x6331 + z6332 = x6332 + z6333 = x6333 + z6334 = x6334 + z6335 = x6335 + z6336 = x6336 + z6337 = x6337 + z6338 = x6338 + z6339 = x6339 + z6340 = x6340 + z6341 = x6341 + z6342 = x6342 + z6343 = x6343 + z6344 = x6344 + z6345 = x6345 + z6346 = x6346 + z6347 = x6347 + z6348 = x6348 + z6349 = x6349 + z6350 = x6350 + z6351 = x6351 + z6352 = x6352 + z6353 = x6353 + z6354 = x6354 + z6355 = x6355 + z6356 = x6356 + z6357 = x6357 + z6358 = x6358 + z6359 = x6359 + z6360 = x6360 + z6361 = x6361 + z6362 = x6362 + z6363 = x6363 + z6364 = x6364 + z6365 = x6365 + z6366 = x6366 + z6367 = x6367 + z6368 = x6368 + z6369 = x6369 + z6370 = x6370 + z6371 = x6371 + z6372 = x6372 + z6373 = x6373 + z6374 = x6374 + z6375 = x6375 + z6376 = x6376 + z6377 = x6377 + z6378 = x6378 + z6379 = x6379 + z6380 = x6380 + z6381 = x6381 + z6382 = x6382 + z6383 = x6383 + z6384 = x6384 + z6385 = x6385 + z6386 = x6386 + z6387 = x6387 + z6388 = x6388 + z6389 = x6389 + z6390 = x6390 + z6391 = x6391 + z6392 = x6392 + z6393 = x6393 + z6394 = x6394 + z6395 = x6395 + z6396 = x6396 + z6397 = x6397 + z6398 = x6398 + z6399 = x6399 + z6400 = x6400 + z6401 = x6401 + z6402 = x6402 + z6403 = x6403 + z6404 = x6404 + z6405 = x6405 + z6406 = x6406 + z6407 = x6407 + z6408 = x6408 + z6409 = x6409 + z6410 = x6410 + z6411 = x6411 + z6412 = x6412 + z6413 = x6413 + z6414 = x6414 + z6415 = x6415 + z6416 = x6416 + z6417 = x6417 + z6418 = x6418 + z6419 = x6419 + z6420 = x6420 + z6421 = x6421 + z6422 = x6422 + z6423 = x6423 + z6424 = x6424 + z6425 = x6425 + z6426 = x6426 + z6427 = x6427 + z6428 = x6428 + z6429 = x6429 + z6430 = x6430 + z6431 = x6431 + z6432 = x6432 + z6433 = x6433 + z6434 = x6434 + z6435 = x6435 + z6436 = x6436 + z6437 = x6437 + z6438 = x6438 + z6439 = x6439 + z6440 = x6440 + z6441 = x6441 + z6442 = x6442 + z6443 = x6443 + z6444 = x6444 + z6445 = x6445 + z6446 = x6446 + z6447 = x6447 + z6448 = x6448 + z6449 = x6449 + z6450 = x6450 + z6451 = x6451 + z6452 = x6452 + z6453 = x6453 + z6454 = x6454 + z6455 = x6455 + z6456 = x6456 + z6457 = x6457 + z6458 = x6458 + z6459 = x6459 + z6460 = x6460 + z6461 = x6461 + z6462 = x6462 + z6463 = x6463 + z6464 = x6464 + z6465 = x6465 + z6466 = x6466 + z6467 = x6467 + z6468 = x6468 + z6469 = x6469 + z6470 = x6470 + z6471 = x6471 + z6472 = x6472 + z6473 = x6473 + z6474 = x6474 + z6475 = x6475 + z6476 = x6476 + z6477 = x6477 + z6478 = x6478 + z6479 = x6479 + z6480 = x6480 + z6481 = x6481 + z6482 = x6482 + z6483 = x6483 + z6484 = x6484 + z6485 = x6485 + z6486 = x6486 + z6487 = x6487 + z6488 = x6488 + z6489 = x6489 + z6490 = x6490 + z6491 = x6491 + z6492 = x6492 + z6493 = x6493 + z6494 = x6494 + z6495 = x6495 + z6496 = x6496 + z6497 = x6497 + z6498 = x6498 + z6499 = x6499 + z6500 = x6500 + z6501 = x6501 + z6502 = x6502 + z6503 = x6503 + z6504 = x6504 + z6505 = x6505 + z6506 = x6506 + z6507 = x6507 + z6508 = x6508 + z6509 = x6509 + z6510 = x6510 + z6511 = x6511 + z6512 = x6512 + z6513 = x6513 + z6514 = x6514 + z6515 = x6515 + z6516 = x6516 + z6517 = x6517 + z6518 = x6518 + z6519 = x6519 + z6520 = x6520 + z6521 = x6521 + z6522 = x6522 + z6523 = x6523 + z6524 = x6524 + z6525 = x6525 + z6526 = x6526 + z6527 = x6527 + z6528 = x6528 + z6529 = x6529 + z6530 = x6530 + z6531 = x6531 + z6532 = x6532 + z6533 = x6533 + z6534 = x6534 + z6535 = x6535 + z6536 = x6536 + z6537 = x6537 + z6538 = x6538 + z6539 = x6539 + z6540 = x6540 + z6541 = x6541 + z6542 = x6542 + z6543 = x6543 + z6544 = x6544 + z6545 = x6545 + z6546 = x6546 + z6547 = x6547 + z6548 = x6548 + z6549 = x6549 + z6550 = x6550 + z6551 = x6551 + z6552 = x6552 + z6553 = x6553 + z6554 = x6554 + z6555 = x6555 + z6556 = x6556 + z6557 = x6557 + z6558 = x6558 + z6559 = x6559 + z6560 = x6560 + z6561 = x6561 + z6562 = x6562 + z6563 = x6563 + z6564 = x6564 + z6565 = x6565 + z6566 = x6566 + z6567 = x6567 + z6568 = x6568 + z6569 = x6569 + z6570 = x6570 + z6571 = x6571 + z6572 = x6572 + z6573 = x6573 + z6574 = x6574 + z6575 = x6575 + z6576 = x6576 + z6577 = x6577 + z6578 = x6578 + z6579 = x6579 + z6580 = x6580 + z6581 = x6581 + z6582 = x6582 + z6583 = x6583 + z6584 = x6584 + z6585 = x6585 + z6586 = x6586 + z6587 = x6587 + z6588 = x6588 + z6589 = x6589 + z6590 = x6590 + z6591 = x6591 + z6592 = x6592 + z6593 = x6593 + z6594 = x6594 + z6595 = x6595 + z6596 = x6596 + z6597 = x6597 + z6598 = x6598 + z6599 = x6599 + z6600 = x6600 + z6601 = x6601 + z6602 = x6602 + z6603 = x6603 + z6604 = x6604 + z6605 = x6605 + z6606 = x6606 + z6607 = x6607 + z6608 = x6608 + z6609 = x6609 + z6610 = x6610 + z6611 = x6611 + z6612 = x6612 + z6613 = x6613 + z6614 = x6614 + z6615 = x6615 + z6616 = x6616 + z6617 = x6617 + z6618 = x6618 + z6619 = x6619 + z6620 = x6620 + z6621 = x6621 + z6622 = x6622 + z6623 = x6623 + z6624 = x6624 + z6625 = x6625 + z6626 = x6626 + z6627 = x6627 + z6628 = x6628 + z6629 = x6629 + z6630 = x6630 + z6631 = x6631 + z6632 = x6632 + z6633 = x6633 + z6634 = x6634 + z6635 = x6635 + z6636 = x6636 + z6637 = x6637 + z6638 = x6638 + z6639 = x6639 + z6640 = x6640 + z6641 = x6641 + z6642 = x6642 + z6643 = x6643 + z6644 = x6644 + z6645 = x6645 + z6646 = x6646 + z6647 = x6647 + z6648 = x6648 + z6649 = x6649 + z6650 = x6650 + z6651 = x6651 + z6652 = x6652 + z6653 = x6653 + z6654 = x6654 + z6655 = x6655 + z6656 = x6656 + z6657 = x6657 + z6658 = x6658 + z6659 = x6659 + z6660 = x6660 + z6661 = x6661 + z6662 = x6662 + z6663 = x6663 + z6664 = x6664 + z6665 = x6665 + z6666 = x6666 + z6667 = x6667 + z6668 = x6668 + z6669 = x6669 + z6670 = x6670 + z6671 = x6671 + z6672 = x6672 + z6673 = x6673 + z6674 = x6674 + z6675 = x6675 + z6676 = x6676 + z6677 = x6677 + z6678 = x6678 + z6679 = x6679 + z6680 = x6680 + z6681 = x6681 + z6682 = x6682 + z6683 = x6683 + z6684 = x6684 + z6685 = x6685 + z6686 = x6686 + z6687 = x6687 + z6688 = x6688 + z6689 = x6689 + z6690 = x6690 + z6691 = x6691 + z6692 = x6692 + z6693 = x6693 + z6694 = x6694 + z6695 = x6695 + z6696 = x6696 + z6697 = x6697 + z6698 = x6698 + z6699 = x6699 + z6700 = x6700 + z6701 = x6701 + z6702 = x6702 + z6703 = x6703 + z6704 = x6704 + z6705 = x6705 + z6706 = x6706 + z6707 = x6707 + z6708 = x6708 + z6709 = x6709 + z6710 = x6710 + z6711 = x6711 + z6712 = x6712 + z6713 = x6713 + z6714 = x6714 + z6715 = x6715 + z6716 = x6716 + z6717 = x6717 + z6718 = x6718 + z6719 = x6719 + z6720 = x6720 + z6721 = x6721 + z6722 = x6722 + z6723 = x6723 + z6724 = x6724 + z6725 = x6725 + z6726 = x6726 + z6727 = x6727 + z6728 = x6728 + z6729 = x6729 + z6730 = x6730 + z6731 = x6731 + z6732 = x6732 + z6733 = x6733 + z6734 = x6734 + z6735 = x6735 + z6736 = x6736 + z6737 = x6737 + z6738 = x6738 + z6739 = x6739 + z6740 = x6740 + z6741 = x6741 + z6742 = x6742 + z6743 = x6743 + z6744 = x6744 + z6745 = x6745 + z6746 = x6746 + z6747 = x6747 + z6748 = x6748 + z6749 = x6749 + z6750 = x6750 + z6751 = x6751 + z6752 = x6752 + z6753 = x6753 + z6754 = x6754 + z6755 = x6755 + z6756 = x6756 + z6757 = x6757 + z6758 = x6758 + z6759 = x6759 + z6760 = x6760 + z6761 = x6761 + z6762 = x6762 + z6763 = x6763 + z6764 = x6764 + z6765 = x6765 + z6766 = x6766 + z6767 = x6767 + z6768 = x6768 + z6769 = x6769 + z6770 = x6770 + z6771 = x6771 + z6772 = x6772 + z6773 = x6773 + z6774 = x6774 + z6775 = x6775 + z6776 = x6776 + z6777 = x6777 + z6778 = x6778 + z6779 = x6779 + z6780 = x6780 + z6781 = x6781 + z6782 = x6782 + z6783 = x6783 + z6784 = x6784 + z6785 = x6785 + z6786 = x6786 + z6787 = x6787 + z6788 = x6788 + z6789 = x6789 + z6790 = x6790 + z6791 = x6791 + z6792 = x6792 + z6793 = x6793 + z6794 = x6794 + z6795 = x6795 + z6796 = x6796 + z6797 = x6797 + z6798 = x6798 + z6799 = x6799 + z6800 = x6800 + z6801 = x6801 + z6802 = x6802 + z6803 = x6803 + z6804 = x6804 + z6805 = x6805 + z6806 = x6806 + z6807 = x6807 + z6808 = x6808 + z6809 = x6809 + z6810 = x6810 + z6811 = x6811 + z6812 = x6812 + z6813 = x6813 + z6814 = x6814 + z6815 = x6815 + z6816 = x6816 + z6817 = x6817 + z6818 = x6818 + z6819 = x6819 + z6820 = x6820 + z6821 = x6821 + z6822 = x6822 + z6823 = x6823 + z6824 = x6824 + z6825 = x6825 + z6826 = x6826 + z6827 = x6827 + z6828 = x6828 + z6829 = x6829 + z6830 = x6830 + z6831 = x6831 + z6832 = x6832 + z6833 = x6833 + z6834 = x6834 + z6835 = x6835 + z6836 = x6836 + z6837 = x6837 + z6838 = x6838 + z6839 = x6839 + z6840 = x6840 + z6841 = x6841 + z6842 = x6842 + z6843 = x6843 + z6844 = x6844 + z6845 = x6845 + z6846 = x6846 + z6847 = x6847 + z6848 = x6848 + z6849 = x6849 + z6850 = x6850 + z6851 = x6851 + z6852 = x6852 + z6853 = x6853 + z6854 = x6854 + z6855 = x6855 + z6856 = x6856 + z6857 = x6857 + z6858 = x6858 + z6859 = x6859 + z6860 = x6860 + z6861 = x6861 + z6862 = x6862 + z6863 = x6863 + z6864 = x6864 + z6865 = x6865 + z6866 = x6866 + z6867 = x6867 + z6868 = x6868 + z6869 = x6869 + z6870 = x6870 + z6871 = x6871 + z6872 = x6872 + z6873 = x6873 + z6874 = x6874 + z6875 = x6875 + z6876 = x6876 + z6877 = x6877 + z6878 = x6878 + z6879 = x6879 + z6880 = x6880 + z6881 = x6881 + z6882 = x6882 + z6883 = x6883 + z6884 = x6884 + z6885 = x6885 + z6886 = x6886 + z6887 = x6887 + z6888 = x6888 + z6889 = x6889 + z6890 = x6890 + z6891 = x6891 + z6892 = x6892 + z6893 = x6893 + z6894 = x6894 + z6895 = x6895 + z6896 = x6896 + z6897 = x6897 + z6898 = x6898 + z6899 = x6899 + z6900 = x6900 + z6901 = x6901 + z6902 = x6902 + z6903 = x6903 + z6904 = x6904 + z6905 = x6905 + z6906 = x6906 + z6907 = x6907 + z6908 = x6908 + z6909 = x6909 + z6910 = x6910 + z6911 = x6911 + z6912 = x6912 + z6913 = x6913 + z6914 = x6914 + z6915 = x6915 + z6916 = x6916 + z6917 = x6917 + z6918 = x6918 + z6919 = x6919 + z6920 = x6920 + z6921 = x6921 + z6922 = x6922 + z6923 = x6923 + z6924 = x6924 + z6925 = x6925 + z6926 = x6926 + z6927 = x6927 + z6928 = x6928 + z6929 = x6929 + z6930 = x6930 + z6931 = x6931 + z6932 = x6932 + z6933 = x6933 + z6934 = x6934 + z6935 = x6935 + z6936 = x6936 + z6937 = x6937 + z6938 = x6938 + z6939 = x6939 + z6940 = x6940 + z6941 = x6941 + z6942 = x6942 + z6943 = x6943 + z6944 = x6944 + z6945 = x6945 + z6946 = x6946 + z6947 = x6947 + z6948 = x6948 + z6949 = x6949 + z6950 = x6950 + z6951 = x6951 + z6952 = x6952 + z6953 = x6953 + z6954 = x6954 + z6955 = x6955 + z6956 = x6956 + z6957 = x6957 + z6958 = x6958 + z6959 = x6959 + z6960 = x6960 + z6961 = x6961 + z6962 = x6962 + z6963 = x6963 + z6964 = x6964 + z6965 = x6965 + z6966 = x6966 + z6967 = x6967 + z6968 = x6968 + z6969 = x6969 + z6970 = x6970 + z6971 = x6971 + z6972 = x6972 + z6973 = x6973 + z6974 = x6974 + z6975 = x6975 + z6976 = x6976 + z6977 = x6977 + z6978 = x6978 + z6979 = x6979 + z6980 = x6980 + z6981 = x6981 + z6982 = x6982 + z6983 = x6983 + z6984 = x6984 + z6985 = x6985 + z6986 = x6986 + z6987 = x6987 + z6988 = x6988 + z6989 = x6989 + z6990 = x6990 + z6991 = x6991 + z6992 = x6992 + z6993 = x6993 + z6994 = x6994 + z6995 = x6995 + z6996 = x6996 + z6997 = x6997 + z6998 = x6998 + z6999 = x6999 + z7000 = x7000 + z7001 = x7001 + z7002 = x7002 + z7003 = x7003 + z7004 = x7004 + z7005 = x7005 + z7006 = x7006 + z7007 = x7007 + z7008 = x7008 + z7009 = x7009 + z7010 = x7010 + z7011 = x7011 + z7012 = x7012 + z7013 = x7013 + z7014 = x7014 + z7015 = x7015 + z7016 = x7016 + z7017 = x7017 + z7018 = x7018 + z7019 = x7019 + z7020 = x7020 + z7021 = x7021 + z7022 = x7022 + z7023 = x7023 + z7024 = x7024 + z7025 = x7025 + z7026 = x7026 + z7027 = x7027 + z7028 = x7028 + z7029 = x7029 + z7030 = x7030 + z7031 = x7031 + z7032 = x7032 + z7033 = x7033 + z7034 = x7034 + z7035 = x7035 + z7036 = x7036 + z7037 = x7037 + z7038 = x7038 + z7039 = x7039 + z7040 = x7040 + z7041 = x7041 + z7042 = x7042 + z7043 = x7043 + z7044 = x7044 + z7045 = x7045 + z7046 = x7046 + z7047 = x7047 + z7048 = x7048 + z7049 = x7049 + z7050 = x7050 + z7051 = x7051 + z7052 = x7052 + z7053 = x7053 + z7054 = x7054 + z7055 = x7055 + z7056 = x7056 + z7057 = x7057 + z7058 = x7058 + z7059 = x7059 + z7060 = x7060 + z7061 = x7061 + z7062 = x7062 + z7063 = x7063 + z7064 = x7064 + z7065 = x7065 + z7066 = x7066 + z7067 = x7067 + z7068 = x7068 + z7069 = x7069 + z7070 = x7070 + z7071 = x7071 + z7072 = x7072 + z7073 = x7073 + z7074 = x7074 + z7075 = x7075 + z7076 = x7076 + z7077 = x7077 + z7078 = x7078 + z7079 = x7079 + z7080 = x7080 + z7081 = x7081 + z7082 = x7082 + z7083 = x7083 + z7084 = x7084 + z7085 = x7085 + z7086 = x7086 + z7087 = x7087 + z7088 = x7088 + z7089 = x7089 + z7090 = x7090 + z7091 = x7091 + z7092 = x7092 + z7093 = x7093 + z7094 = x7094 + z7095 = x7095 + z7096 = x7096 + z7097 = x7097 + z7098 = x7098 + z7099 = x7099 + z7100 = x7100 + z7101 = x7101 + z7102 = x7102 + z7103 = x7103 + z7104 = x7104 + z7105 = x7105 + z7106 = x7106 + z7107 = x7107 + z7108 = x7108 + z7109 = x7109 + z7110 = x7110 + z7111 = x7111 + z7112 = x7112 + z7113 = x7113 + z7114 = x7114 + z7115 = x7115 + z7116 = x7116 + z7117 = x7117 + z7118 = x7118 + z7119 = x7119 + z7120 = x7120 + z7121 = x7121 + z7122 = x7122 + z7123 = x7123 + z7124 = x7124 + z7125 = x7125 + z7126 = x7126 + z7127 = x7127 + z7128 = x7128 + z7129 = x7129 + z7130 = x7130 + z7131 = x7131 + z7132 = x7132 + z7133 = x7133 + z7134 = x7134 + z7135 = x7135 + z7136 = x7136 + z7137 = x7137 + z7138 = x7138 + z7139 = x7139 + z7140 = x7140 + z7141 = x7141 + z7142 = x7142 + z7143 = x7143 + z7144 = x7144 + z7145 = x7145 + z7146 = x7146 + z7147 = x7147 + z7148 = x7148 + z7149 = x7149 + z7150 = x7150 + z7151 = x7151 + z7152 = x7152 + z7153 = x7153 + z7154 = x7154 + z7155 = x7155 + z7156 = x7156 + z7157 = x7157 + z7158 = x7158 + z7159 = x7159 + z7160 = x7160 + z7161 = x7161 + z7162 = x7162 + z7163 = x7163 + z7164 = x7164 + z7165 = x7165 + z7166 = x7166 + z7167 = x7167 + z7168 = x7168 + z7169 = x7169 + z7170 = x7170 + z7171 = x7171 + z7172 = x7172 + z7173 = x7173 + z7174 = x7174 + z7175 = x7175 + z7176 = x7176 + z7177 = x7177 + z7178 = x7178 + z7179 = x7179 + z7180 = x7180 + z7181 = x7181 + z7182 = x7182 + z7183 = x7183 + z7184 = x7184 + z7185 = x7185 + z7186 = x7186 + z7187 = x7187 + z7188 = x7188 + z7189 = x7189 + z7190 = x7190 + z7191 = x7191 + z7192 = x7192 + z7193 = x7193 + z7194 = x7194 + z7195 = x7195 + z7196 = x7196 + z7197 = x7197 + z7198 = x7198 + z7199 = x7199 + z7200 = x7200 + z7201 = x7201 + z7202 = x7202 + z7203 = x7203 + z7204 = x7204 + z7205 = x7205 + z7206 = x7206 + z7207 = x7207 + z7208 = x7208 + z7209 = x7209 + z7210 = x7210 + z7211 = x7211 + z7212 = x7212 + z7213 = x7213 + z7214 = x7214 + z7215 = x7215 + z7216 = x7216 + z7217 = x7217 + z7218 = x7218 + z7219 = x7219 + z7220 = x7220 + z7221 = x7221 + z7222 = x7222 + z7223 = x7223 + z7224 = x7224 + z7225 = x7225 + z7226 = x7226 + z7227 = x7227 + z7228 = x7228 + z7229 = x7229 + z7230 = x7230 + z7231 = x7231 + z7232 = x7232 + z7233 = x7233 + z7234 = x7234 + z7235 = x7235 + z7236 = x7236 + z7237 = x7237 + z7238 = x7238 + z7239 = x7239 + z7240 = x7240 + z7241 = x7241 + z7242 = x7242 + z7243 = x7243 + z7244 = x7244 + z7245 = x7245 + z7246 = x7246 + z7247 = x7247 + z7248 = x7248 + z7249 = x7249 + z7250 = x7250 + z7251 = x7251 + z7252 = x7252 + z7253 = x7253 + z7254 = x7254 + z7255 = x7255 + z7256 = x7256 + z7257 = x7257 + z7258 = x7258 + z7259 = x7259 + z7260 = x7260 + z7261 = x7261 + z7262 = x7262 + z7263 = x7263 + z7264 = x7264 + z7265 = x7265 + z7266 = x7266 + z7267 = x7267 + z7268 = x7268 + z7269 = x7269 + z7270 = x7270 + z7271 = x7271 + z7272 = x7272 + z7273 = x7273 + z7274 = x7274 + z7275 = x7275 + z7276 = x7276 + z7277 = x7277 + z7278 = x7278 + z7279 = x7279 + z7280 = x7280 + z7281 = x7281 + z7282 = x7282 + z7283 = x7283 + z7284 = x7284 + z7285 = x7285 + z7286 = x7286 + z7287 = x7287 + z7288 = x7288 + z7289 = x7289 + z7290 = x7290 + z7291 = x7291 + z7292 = x7292 + z7293 = x7293 + z7294 = x7294 + z7295 = x7295 + z7296 = x7296 + z7297 = x7297 + z7298 = x7298 + z7299 = x7299 + z7300 = x7300 + z7301 = x7301 + z7302 = x7302 + z7303 = x7303 + z7304 = x7304 + z7305 = x7305 + z7306 = x7306 + z7307 = x7307 + z7308 = x7308 + z7309 = x7309 + z7310 = x7310 + z7311 = x7311 + z7312 = x7312 + z7313 = x7313 + z7314 = x7314 + z7315 = x7315 + z7316 = x7316 + z7317 = x7317 + z7318 = x7318 + z7319 = x7319 + z7320 = x7320 + z7321 = x7321 + z7322 = x7322 + z7323 = x7323 + z7324 = x7324 + z7325 = x7325 + z7326 = x7326 + z7327 = x7327 + z7328 = x7328 + z7329 = x7329 + z7330 = x7330 + z7331 = x7331 + z7332 = x7332 + z7333 = x7333 + z7334 = x7334 + z7335 = x7335 + z7336 = x7336 + z7337 = x7337 + z7338 = x7338 + z7339 = x7339 + z7340 = x7340 + z7341 = x7341 + z7342 = x7342 + z7343 = x7343 + z7344 = x7344 + z7345 = x7345 + z7346 = x7346 + z7347 = x7347 + z7348 = x7348 + z7349 = x7349 + z7350 = x7350 + z7351 = x7351 + z7352 = x7352 + z7353 = x7353 + z7354 = x7354 + z7355 = x7355 + z7356 = x7356 + z7357 = x7357 + z7358 = x7358 + z7359 = x7359 + z7360 = x7360 + z7361 = x7361 + z7362 = x7362 + z7363 = x7363 + z7364 = x7364 + z7365 = x7365 + z7366 = x7366 + z7367 = x7367 + z7368 = x7368 + z7369 = x7369 + z7370 = x7370 + z7371 = x7371 + z7372 = x7372 + z7373 = x7373 + z7374 = x7374 + z7375 = x7375 + z7376 = x7376 + z7377 = x7377 + z7378 = x7378 + z7379 = x7379 + z7380 = x7380 + z7381 = x7381 + z7382 = x7382 + z7383 = x7383 + z7384 = x7384 + z7385 = x7385 + z7386 = x7386 + z7387 = x7387 + z7388 = x7388 + z7389 = x7389 + z7390 = x7390 + z7391 = x7391 + z7392 = x7392 + z7393 = x7393 + z7394 = x7394 + z7395 = x7395 + z7396 = x7396 + z7397 = x7397 + z7398 = x7398 + z7399 = x7399 + z7400 = x7400 + z7401 = x7401 + z7402 = x7402 + z7403 = x7403 + z7404 = x7404 + z7405 = x7405 + z7406 = x7406 + z7407 = x7407 + z7408 = x7408 + z7409 = x7409 + z7410 = x7410 + z7411 = x7411 + z7412 = x7412 + z7413 = x7413 + z7414 = x7414 + z7415 = x7415 + z7416 = x7416 + z7417 = x7417 + z7418 = x7418 + z7419 = x7419 + z7420 = x7420 + z7421 = x7421 + z7422 = x7422 + z7423 = x7423 + z7424 = x7424 + z7425 = x7425 + z7426 = x7426 + z7427 = x7427 + z7428 = x7428 + z7429 = x7429 + z7430 = x7430 + z7431 = x7431 + z7432 = x7432 + z7433 = x7433 + z7434 = x7434 + z7435 = x7435 + z7436 = x7436 + z7437 = x7437 + z7438 = x7438 + z7439 = x7439 + z7440 = x7440 + z7441 = x7441 + z7442 = x7442 + z7443 = x7443 + z7444 = x7444 + z7445 = x7445 + z7446 = x7446 + z7447 = x7447 + z7448 = x7448 + z7449 = x7449 + z7450 = x7450 + z7451 = x7451 + z7452 = x7452 + z7453 = x7453 + z7454 = x7454 + z7455 = x7455 + z7456 = x7456 + z7457 = x7457 + z7458 = x7458 + z7459 = x7459 + z7460 = x7460 + z7461 = x7461 + z7462 = x7462 + z7463 = x7463 + z7464 = x7464 + z7465 = x7465 + z7466 = x7466 + z7467 = x7467 + z7468 = x7468 + z7469 = x7469 + z7470 = x7470 + z7471 = x7471 + z7472 = x7472 + z7473 = x7473 + z7474 = x7474 + z7475 = x7475 + z7476 = x7476 + z7477 = x7477 + z7478 = x7478 + z7479 = x7479 + z7480 = x7480 + z7481 = x7481 + z7482 = x7482 + z7483 = x7483 + z7484 = x7484 + z7485 = x7485 + z7486 = x7486 + z7487 = x7487 + z7488 = x7488 + z7489 = x7489 + z7490 = x7490 + z7491 = x7491 + z7492 = x7492 + z7493 = x7493 + z7494 = x7494 + z7495 = x7495 + z7496 = x7496 + z7497 = x7497 + z7498 = x7498 + z7499 = x7499 + z7500 = x7500 + z7501 = x7501 + z7502 = x7502 + z7503 = x7503 + z7504 = x7504 + z7505 = x7505 + z7506 = x7506 + z7507 = x7507 + z7508 = x7508 + z7509 = x7509 + z7510 = x7510 + z7511 = x7511 + z7512 = x7512 + z7513 = x7513 + z7514 = x7514 + z7515 = x7515 + z7516 = x7516 + z7517 = x7517 + z7518 = x7518 + z7519 = x7519 + z7520 = x7520 + z7521 = x7521 + z7522 = x7522 + z7523 = x7523 + z7524 = x7524 + z7525 = x7525 + z7526 = x7526 + z7527 = x7527 + z7528 = x7528 + z7529 = x7529 + z7530 = x7530 + z7531 = x7531 + z7532 = x7532 + z7533 = x7533 + z7534 = x7534 + z7535 = x7535 + z7536 = x7536 + z7537 = x7537 + z7538 = x7538 + z7539 = x7539 + z7540 = x7540 + z7541 = x7541 + z7542 = x7542 + z7543 = x7543 + z7544 = x7544 + z7545 = x7545 + z7546 = x7546 + z7547 = x7547 + z7548 = x7548 + z7549 = x7549 + z7550 = x7550 + z7551 = x7551 + z7552 = x7552 + z7553 = x7553 + z7554 = x7554 + z7555 = x7555 + z7556 = x7556 + z7557 = x7557 + z7558 = x7558 + z7559 = x7559 + z7560 = x7560 + z7561 = x7561 + z7562 = x7562 + z7563 = x7563 + z7564 = x7564 + z7565 = x7565 + z7566 = x7566 + z7567 = x7567 + z7568 = x7568 + z7569 = x7569 + z7570 = x7570 + z7571 = x7571 + z7572 = x7572 + z7573 = x7573 + z7574 = x7574 + z7575 = x7575 + z7576 = x7576 + z7577 = x7577 + z7578 = x7578 + z7579 = x7579 + z7580 = x7580 + z7581 = x7581 + z7582 = x7582 + z7583 = x7583 + z7584 = x7584 + z7585 = x7585 + z7586 = x7586 + z7587 = x7587 + z7588 = x7588 + z7589 = x7589 + z7590 = x7590 + z7591 = x7591 + z7592 = x7592 + z7593 = x7593 + z7594 = x7594 + z7595 = x7595 + z7596 = x7596 + z7597 = x7597 + z7598 = x7598 + z7599 = x7599 + z7600 = x7600 + z7601 = x7601 + z7602 = x7602 + z7603 = x7603 + z7604 = x7604 + z7605 = x7605 + z7606 = x7606 + z7607 = x7607 + z7608 = x7608 + z7609 = x7609 + z7610 = x7610 + z7611 = x7611 + z7612 = x7612 + z7613 = x7613 + z7614 = x7614 + z7615 = x7615 + z7616 = x7616 + z7617 = x7617 + z7618 = x7618 + z7619 = x7619 + z7620 = x7620 + z7621 = x7621 + z7622 = x7622 + z7623 = x7623 + z7624 = x7624 + z7625 = x7625 + z7626 = x7626 + z7627 = x7627 + z7628 = x7628 + z7629 = x7629 + z7630 = x7630 + z7631 = x7631 + z7632 = x7632 + z7633 = x7633 + z7634 = x7634 + z7635 = x7635 + z7636 = x7636 + z7637 = x7637 + z7638 = x7638 + z7639 = x7639 + z7640 = x7640 + z7641 = x7641 + z7642 = x7642 + z7643 = x7643 + z7644 = x7644 + z7645 = x7645 + z7646 = x7646 + z7647 = x7647 + z7648 = x7648 + z7649 = x7649 + z7650 = x7650 + z7651 = x7651 + z7652 = x7652 + z7653 = x7653 + z7654 = x7654 + z7655 = x7655 + z7656 = x7656 + z7657 = x7657 + z7658 = x7658 + z7659 = x7659 + z7660 = x7660 + z7661 = x7661 + z7662 = x7662 + z7663 = x7663 + z7664 = x7664 + z7665 = x7665 + z7666 = x7666 + z7667 = x7667 + z7668 = x7668 + z7669 = x7669 + z7670 = x7670 + z7671 = x7671 + z7672 = x7672 + z7673 = x7673 + z7674 = x7674 + z7675 = x7675 + z7676 = x7676 + z7677 = x7677 + z7678 = x7678 + z7679 = x7679 + z7680 = x7680 + z7681 = x7681 + z7682 = x7682 + z7683 = x7683 + z7684 = x7684 + z7685 = x7685 + z7686 = x7686 + z7687 = x7687 + z7688 = x7688 + z7689 = x7689 + z7690 = x7690 + z7691 = x7691 + z7692 = x7692 + z7693 = x7693 + z7694 = x7694 + z7695 = x7695 + z7696 = x7696 + z7697 = x7697 + z7698 = x7698 + z7699 = x7699 + z7700 = x7700 + z7701 = x7701 + z7702 = x7702 + z7703 = x7703 + z7704 = x7704 + z7705 = x7705 + z7706 = x7706 + z7707 = x7707 + z7708 = x7708 + z7709 = x7709 + z7710 = x7710 + z7711 = x7711 + z7712 = x7712 + z7713 = x7713 + z7714 = x7714 + z7715 = x7715 + z7716 = x7716 + z7717 = x7717 + z7718 = x7718 + z7719 = x7719 + z7720 = x7720 + z7721 = x7721 + z7722 = x7722 + z7723 = x7723 + z7724 = x7724 + z7725 = x7725 + z7726 = x7726 + z7727 = x7727 + z7728 = x7728 + z7729 = x7729 + z7730 = x7730 + z7731 = x7731 + z7732 = x7732 + z7733 = x7733 + z7734 = x7734 + z7735 = x7735 + z7736 = x7736 + z7737 = x7737 + z7738 = x7738 + z7739 = x7739 + z7740 = x7740 + z7741 = x7741 + z7742 = x7742 + z7743 = x7743 + z7744 = x7744 + z7745 = x7745 + z7746 = x7746 + z7747 = x7747 + z7748 = x7748 + z7749 = x7749 + z7750 = x7750 + z7751 = x7751 + z7752 = x7752 + z7753 = x7753 + z7754 = x7754 + z7755 = x7755 + z7756 = x7756 + z7757 = x7757 + z7758 = x7758 + z7759 = x7759 + z7760 = x7760 + z7761 = x7761 + z7762 = x7762 + z7763 = x7763 + z7764 = x7764 + z7765 = x7765 + z7766 = x7766 + z7767 = x7767 + z7768 = x7768 + z7769 = x7769 + z7770 = x7770 + z7771 = x7771 + z7772 = x7772 + z7773 = x7773 + z7774 = x7774 + z7775 = x7775 + z7776 = x7776 + z7777 = x7777 + z7778 = x7778 + z7779 = x7779 + z7780 = x7780 + z7781 = x7781 + z7782 = x7782 + z7783 = x7783 + z7784 = x7784 + z7785 = x7785 + z7786 = x7786 + z7787 = x7787 + z7788 = x7788 + z7789 = x7789 + z7790 = x7790 + z7791 = x7791 + z7792 = x7792 + z7793 = x7793 + z7794 = x7794 + z7795 = x7795 + z7796 = x7796 + z7797 = x7797 + z7798 = x7798 + z7799 = x7799 + z7800 = x7800 + z7801 = x7801 + z7802 = x7802 + z7803 = x7803 + z7804 = x7804 + z7805 = x7805 + z7806 = x7806 + z7807 = x7807 + z7808 = x7808 + z7809 = x7809 + z7810 = x7810 + z7811 = x7811 + z7812 = x7812 + z7813 = x7813 + z7814 = x7814 + z7815 = x7815 + z7816 = x7816 + z7817 = x7817 + z7818 = x7818 + z7819 = x7819 + z7820 = x7820 + z7821 = x7821 + z7822 = x7822 + z7823 = x7823 + z7824 = x7824 + z7825 = x7825 + z7826 = x7826 + z7827 = x7827 + z7828 = x7828 + z7829 = x7829 + z7830 = x7830 + z7831 = x7831 + z7832 = x7832 + z7833 = x7833 + z7834 = x7834 + z7835 = x7835 + z7836 = x7836 + z7837 = x7837 + z7838 = x7838 + z7839 = x7839 + z7840 = x7840 + z7841 = x7841 + z7842 = x7842 + z7843 = x7843 + z7844 = x7844 + z7845 = x7845 + z7846 = x7846 + z7847 = x7847 + z7848 = x7848 + z7849 = x7849 + z7850 = x7850 + z7851 = x7851 + z7852 = x7852 + z7853 = x7853 + z7854 = x7854 + z7855 = x7855 + z7856 = x7856 + z7857 = x7857 + z7858 = x7858 + z7859 = x7859 + z7860 = x7860 + z7861 = x7861 + z7862 = x7862 + z7863 = x7863 + z7864 = x7864 + z7865 = x7865 + z7866 = x7866 + z7867 = x7867 + z7868 = x7868 + z7869 = x7869 + z7870 = x7870 + z7871 = x7871 + z7872 = x7872 + z7873 = x7873 + z7874 = x7874 + z7875 = x7875 + z7876 = x7876 + z7877 = x7877 + z7878 = x7878 + z7879 = x7879 + z7880 = x7880 + z7881 = x7881 + z7882 = x7882 + z7883 = x7883 + z7884 = x7884 + z7885 = x7885 + z7886 = x7886 + z7887 = x7887 + z7888 = x7888 + z7889 = x7889 + z7890 = x7890 + z7891 = x7891 + z7892 = x7892 + z7893 = x7893 + z7894 = x7894 + z7895 = x7895 + z7896 = x7896 + z7897 = x7897 + z7898 = x7898 + z7899 = x7899 + z7900 = x7900 + z7901 = x7901 + z7902 = x7902 + z7903 = x7903 + z7904 = x7904 + z7905 = x7905 + z7906 = x7906 + z7907 = x7907 + z7908 = x7908 + z7909 = x7909 + z7910 = x7910 + z7911 = x7911 + z7912 = x7912 + z7913 = x7913 + z7914 = x7914 + z7915 = x7915 + z7916 = x7916 + z7917 = x7917 + z7918 = x7918 + z7919 = x7919 + z7920 = x7920 + z7921 = x7921 + z7922 = x7922 + z7923 = x7923 + z7924 = x7924 + z7925 = x7925 + z7926 = x7926 + z7927 = x7927 + z7928 = x7928 + z7929 = x7929 + z7930 = x7930 + z7931 = x7931 + z7932 = x7932 + z7933 = x7933 + z7934 = x7934 + z7935 = x7935 + z7936 = x7936 + z7937 = x7937 + z7938 = x7938 + z7939 = x7939 + z7940 = x7940 + z7941 = x7941 + z7942 = x7942 + z7943 = x7943 + z7944 = x7944 + z7945 = x7945 + z7946 = x7946 + z7947 = x7947 + z7948 = x7948 + z7949 = x7949 + z7950 = x7950 + z7951 = x7951 + z7952 = x7952 + z7953 = x7953 + z7954 = x7954 + z7955 = x7955 + z7956 = x7956 + z7957 = x7957 + z7958 = x7958 + z7959 = x7959 + z7960 = x7960 + z7961 = x7961 + z7962 = x7962 + z7963 = x7963 + z7964 = x7964 + z7965 = x7965 + z7966 = x7966 + z7967 = x7967 + z7968 = x7968 + z7969 = x7969 + z7970 = x7970 + z7971 = x7971 + z7972 = x7972 + z7973 = x7973 + z7974 = x7974 + z7975 = x7975 + z7976 = x7976 + z7977 = x7977 + z7978 = x7978 + z7979 = x7979 + z7980 = x7980 + z7981 = x7981 + z7982 = x7982 + z7983 = x7983 + z7984 = x7984 + z7985 = x7985 + z7986 = x7986 + z7987 = x7987 + z7988 = x7988 + z7989 = x7989 + z7990 = x7990 + z7991 = x7991 + z7992 = x7992 + z7993 = x7993 + z7994 = x7994 + z7995 = x7995 + z7996 = x7996 + z7997 = x7997 + z7998 = x7998 + z7999 = x7999 + z8000 = x8000 + z8001 = x8001 + z8002 = x8002 + z8003 = x8003 + z8004 = x8004 + z8005 = x8005 + z8006 = x8006 + z8007 = x8007 + z8008 = x8008 + z8009 = x8009 + z8010 = x8010 + z8011 = x8011 + z8012 = x8012 + z8013 = x8013 + z8014 = x8014 + z8015 = x8015 + z8016 = x8016 + z8017 = x8017 + z8018 = x8018 + z8019 = x8019 + z8020 = x8020 + z8021 = x8021 + z8022 = x8022 + z8023 = x8023 + z8024 = x8024 + z8025 = x8025 + z8026 = x8026 + z8027 = x8027 + z8028 = x8028 + z8029 = x8029 + z8030 = x8030 + z8031 = x8031 + z8032 = x8032 + z8033 = x8033 + z8034 = x8034 + z8035 = x8035 + z8036 = x8036 + z8037 = x8037 + z8038 = x8038 + z8039 = x8039 + z8040 = x8040 + z8041 = x8041 + z8042 = x8042 + z8043 = x8043 + z8044 = x8044 + z8045 = x8045 + z8046 = x8046 + z8047 = x8047 + z8048 = x8048 + z8049 = x8049 + z8050 = x8050 + z8051 = x8051 + z8052 = x8052 + z8053 = x8053 + z8054 = x8054 + z8055 = x8055 + z8056 = x8056 + z8057 = x8057 + z8058 = x8058 + z8059 = x8059 + z8060 = x8060 + z8061 = x8061 + z8062 = x8062 + z8063 = x8063 + z8064 = x8064 + z8065 = x8065 + z8066 = x8066 + z8067 = x8067 + z8068 = x8068 + z8069 = x8069 + z8070 = x8070 + z8071 = x8071 + z8072 = x8072 + z8073 = x8073 + z8074 = x8074 + z8075 = x8075 + z8076 = x8076 + z8077 = x8077 + z8078 = x8078 + z8079 = x8079 + z8080 = x8080 + z8081 = x8081 + z8082 = x8082 + z8083 = x8083 + z8084 = x8084 + z8085 = x8085 + z8086 = x8086 + z8087 = x8087 + z8088 = x8088 + z8089 = x8089 + z8090 = x8090 + z8091 = x8091 + z8092 = x8092 + z8093 = x8093 + z8094 = x8094 + z8095 = x8095 + z8096 = x8096 + z8097 = x8097 + z8098 = x8098 + z8099 = x8099 + z8100 = x8100 + z8101 = x8101 + z8102 = x8102 + z8103 = x8103 + z8104 = x8104 + z8105 = x8105 + z8106 = x8106 + z8107 = x8107 + z8108 = x8108 + z8109 = x8109 + z8110 = x8110 + z8111 = x8111 + z8112 = x8112 + z8113 = x8113 + z8114 = x8114 + z8115 = x8115 + z8116 = x8116 + z8117 = x8117 + z8118 = x8118 + z8119 = x8119 + z8120 = x8120 + z8121 = x8121 + z8122 = x8122 + z8123 = x8123 + z8124 = x8124 + z8125 = x8125 + z8126 = x8126 + z8127 = x8127 + z8128 = x8128 + z8129 = x8129 + z8130 = x8130 + z8131 = x8131 + z8132 = x8132 + z8133 = x8133 + z8134 = x8134 + z8135 = x8135 + z8136 = x8136 + z8137 = x8137 + z8138 = x8138 + z8139 = x8139 + z8140 = x8140 + z8141 = x8141 + z8142 = x8142 + z8143 = x8143 + z8144 = x8144 + z8145 = x8145 + z8146 = x8146 + z8147 = x8147 + z8148 = x8148 + z8149 = x8149 + z8150 = x8150 + z8151 = x8151 + z8152 = x8152 + z8153 = x8153 + z8154 = x8154 + z8155 = x8155 + z8156 = x8156 + z8157 = x8157 + z8158 = x8158 + z8159 = x8159 + z8160 = x8160 + z8161 = x8161 + z8162 = x8162 + z8163 = x8163 + z8164 = x8164 + z8165 = x8165 + z8166 = x8166 + z8167 = x8167 + z8168 = x8168 + z8169 = x8169 + z8170 = x8170 + z8171 = x8171 + z8172 = x8172 + z8173 = x8173 + z8174 = x8174 + z8175 = x8175 + z8176 = x8176 + z8177 = x8177 + z8178 = x8178 + z8179 = x8179 + z8180 = x8180 + z8181 = x8181 + z8182 = x8182 + z8183 = x8183 + z8184 = x8184 + z8185 = x8185 + z8186 = x8186 + z8187 = x8187 + z8188 = x8188 + z8189 = x8189 + z8190 = x8190 + z8191 = x8191 + z8192 = x8192 + z8193 = x8193 + z8194 = x8194 + z8195 = x8195 + z8196 = x8196 + z8197 = x8197 + z8198 = x8198 + z8199 = x8199 + z8200 = x8200 + z8201 = x8201 + z8202 = x8202 + z8203 = x8203 + z8204 = x8204 + z8205 = x8205 + z8206 = x8206 + z8207 = x8207 + z8208 = x8208 + z8209 = x8209 + z8210 = x8210 + z8211 = x8211 + z8212 = x8212 + z8213 = x8213 + z8214 = x8214 + z8215 = x8215 + z8216 = x8216 + z8217 = x8217 + z8218 = x8218 + z8219 = x8219 + z8220 = x8220 + z8221 = x8221 + z8222 = x8222 + z8223 = x8223 + z8224 = x8224 + z8225 = x8225 + z8226 = x8226 + z8227 = x8227 + z8228 = x8228 + z8229 = x8229 + z8230 = x8230 + z8231 = x8231 + z8232 = x8232 + z8233 = x8233 + z8234 = x8234 + z8235 = x8235 + z8236 = x8236 + z8237 = x8237 + z8238 = x8238 + z8239 = x8239 + z8240 = x8240 + z8241 = x8241 + z8242 = x8242 + z8243 = x8243 + z8244 = x8244 + z8245 = x8245 + z8246 = x8246 + z8247 = x8247 + z8248 = x8248 + z8249 = x8249 + z8250 = x8250 + z8251 = x8251 + z8252 = x8252 + z8253 = x8253 + z8254 = x8254 + z8255 = x8255 + z8256 = x8256 + z8257 = x8257 + z8258 = x8258 + z8259 = x8259 + z8260 = x8260 + z8261 = x8261 + z8262 = x8262 + z8263 = x8263 + z8264 = x8264 + z8265 = x8265 + z8266 = x8266 + z8267 = x8267 + z8268 = x8268 + z8269 = x8269 + z8270 = x8270 + z8271 = x8271 + z8272 = x8272 + z8273 = x8273 + z8274 = x8274 + z8275 = x8275 + z8276 = x8276 + z8277 = x8277 + z8278 = x8278 + z8279 = x8279 + z8280 = x8280 + z8281 = x8281 + z8282 = x8282 + z8283 = x8283 + z8284 = x8284 + z8285 = x8285 + z8286 = x8286 + z8287 = x8287 + z8288 = x8288 + z8289 = x8289 + z8290 = x8290 + z8291 = x8291 + z8292 = x8292 + z8293 = x8293 + z8294 = x8294 + z8295 = x8295 + z8296 = x8296 + z8297 = x8297 + z8298 = x8298 + z8299 = x8299 + z8300 = x8300 + z8301 = x8301 + z8302 = x8302 + z8303 = x8303 + z8304 = x8304 + z8305 = x8305 + z8306 = x8306 + z8307 = x8307 + z8308 = x8308 + z8309 = x8309 + z8310 = x8310 + z8311 = x8311 + z8312 = x8312 + z8313 = x8313 + z8314 = x8314 + z8315 = x8315 + z8316 = x8316 + z8317 = x8317 + z8318 = x8318 + z8319 = x8319 + z8320 = x8320 + z8321 = x8321 + z8322 = x8322 + z8323 = x8323 + z8324 = x8324 + z8325 = x8325 + z8326 = x8326 + z8327 = x8327 + z8328 = x8328 + z8329 = x8329 + z8330 = x8330 + z8331 = x8331 + z8332 = x8332 + z8333 = x8333 + z8334 = x8334 + z8335 = x8335 + z8336 = x8336 + z8337 = x8337 + z8338 = x8338 + z8339 = x8339 + z8340 = x8340 + z8341 = x8341 + z8342 = x8342 + z8343 = x8343 + z8344 = x8344 + z8345 = x8345 + z8346 = x8346 + z8347 = x8347 + z8348 = x8348 + z8349 = x8349 + z8350 = x8350 + z8351 = x8351 + z8352 = x8352 + z8353 = x8353 + z8354 = x8354 + z8355 = x8355 + z8356 = x8356 + z8357 = x8357 + z8358 = x8358 + z8359 = x8359 + z8360 = x8360 + z8361 = x8361 + z8362 = x8362 + z8363 = x8363 + z8364 = x8364 + z8365 = x8365 + z8366 = x8366 + z8367 = x8367 + z8368 = x8368 + z8369 = x8369 + z8370 = x8370 + z8371 = x8371 + z8372 = x8372 + z8373 = x8373 + z8374 = x8374 + z8375 = x8375 + z8376 = x8376 + z8377 = x8377 + z8378 = x8378 + z8379 = x8379 + z8380 = x8380 + z8381 = x8381 + z8382 = x8382 + z8383 = x8383 + z8384 = x8384 + z8385 = x8385 + z8386 = x8386 + z8387 = x8387 + z8388 = x8388 + z8389 = x8389 + z8390 = x8390 + z8391 = x8391 + z8392 = x8392 + z8393 = x8393 + z8394 = x8394 + z8395 = x8395 + z8396 = x8396 + z8397 = x8397 + z8398 = x8398 + z8399 = x8399 + z8400 = x8400 + z8401 = x8401 + z8402 = x8402 + z8403 = x8403 + z8404 = x8404 + z8405 = x8405 + z8406 = x8406 + z8407 = x8407 + z8408 = x8408 + z8409 = x8409 + z8410 = x8410 + z8411 = x8411 + z8412 = x8412 + z8413 = x8413 + z8414 = x8414 + z8415 = x8415 + z8416 = x8416 + z8417 = x8417 + z8418 = x8418 + z8419 = x8419 + z8420 = x8420 + z8421 = x8421 + z8422 = x8422 + z8423 = x8423 + z8424 = x8424 + z8425 = x8425 + z8426 = x8426 + z8427 = x8427 + z8428 = x8428 + z8429 = x8429 + z8430 = x8430 + z8431 = x8431 + z8432 = x8432 + z8433 = x8433 + z8434 = x8434 + z8435 = x8435 + z8436 = x8436 + z8437 = x8437 + z8438 = x8438 + z8439 = x8439 + z8440 = x8440 + z8441 = x8441 + z8442 = x8442 + z8443 = x8443 + z8444 = x8444 + z8445 = x8445 + z8446 = x8446 + z8447 = x8447 + z8448 = x8448 + z8449 = x8449 + z8450 = x8450 + z8451 = x8451 + z8452 = x8452 + z8453 = x8453 + z8454 = x8454 + z8455 = x8455 + z8456 = x8456 + z8457 = x8457 + z8458 = x8458 + z8459 = x8459 + z8460 = x8460 + z8461 = x8461 + z8462 = x8462 + z8463 = x8463 + z8464 = x8464 + z8465 = x8465 + z8466 = x8466 + z8467 = x8467 + z8468 = x8468 + z8469 = x8469 + z8470 = x8470 + z8471 = x8471 + z8472 = x8472 + z8473 = x8473 + z8474 = x8474 + z8475 = x8475 + z8476 = x8476 + z8477 = x8477 + z8478 = x8478 + z8479 = x8479 + z8480 = x8480 + z8481 = x8481 + z8482 = x8482 + z8483 = x8483 + z8484 = x8484 + z8485 = x8485 + z8486 = x8486 + z8487 = x8487 + z8488 = x8488 + z8489 = x8489 + z8490 = x8490 + z8491 = x8491 + z8492 = x8492 + z8493 = x8493 + z8494 = x8494 + z8495 = x8495 + z8496 = x8496 + z8497 = x8497 + z8498 = x8498 + z8499 = x8499 + z8500 = x8500 + z8501 = x8501 + z8502 = x8502 + z8503 = x8503 + z8504 = x8504 + z8505 = x8505 + z8506 = x8506 + z8507 = x8507 + z8508 = x8508 + z8509 = x8509 + z8510 = x8510 + z8511 = x8511 + z8512 = x8512 + z8513 = x8513 + z8514 = x8514 + z8515 = x8515 + z8516 = x8516 + z8517 = x8517 + z8518 = x8518 + z8519 = x8519 + z8520 = x8520 + z8521 = x8521 + z8522 = x8522 + z8523 = x8523 + z8524 = x8524 + z8525 = x8525 + z8526 = x8526 + z8527 = x8527 + z8528 = x8528 + z8529 = x8529 + z8530 = x8530 + z8531 = x8531 + z8532 = x8532 + z8533 = x8533 + z8534 = x8534 + z8535 = x8535 + z8536 = x8536 + z8537 = x8537 + z8538 = x8538 + z8539 = x8539 + z8540 = x8540 + z8541 = x8541 + z8542 = x8542 + z8543 = x8543 + z8544 = x8544 + z8545 = x8545 + z8546 = x8546 + z8547 = x8547 + z8548 = x8548 + z8549 = x8549 + z8550 = x8550 + z8551 = x8551 + z8552 = x8552 + z8553 = x8553 + z8554 = x8554 + z8555 = x8555 + z8556 = x8556 + z8557 = x8557 + z8558 = x8558 + z8559 = x8559 + z8560 = x8560 + z8561 = x8561 + z8562 = x8562 + z8563 = x8563 + z8564 = x8564 + z8565 = x8565 + z8566 = x8566 + z8567 = x8567 + z8568 = x8568 + z8569 = x8569 + z8570 = x8570 + z8571 = x8571 + z8572 = x8572 + z8573 = x8573 + z8574 = x8574 + z8575 = x8575 + z8576 = x8576 + z8577 = x8577 + z8578 = x8578 + z8579 = x8579 + z8580 = x8580 + z8581 = x8581 + z8582 = x8582 + z8583 = x8583 + z8584 = x8584 + z8585 = x8585 + z8586 = x8586 + z8587 = x8587 + z8588 = x8588 + z8589 = x8589 + z8590 = x8590 + z8591 = x8591 + z8592 = x8592 + z8593 = x8593 + z8594 = x8594 + z8595 = x8595 + z8596 = x8596 + z8597 = x8597 + z8598 = x8598 + z8599 = x8599 + z8600 = x8600 + z8601 = x8601 + z8602 = x8602 + z8603 = x8603 + z8604 = x8604 + z8605 = x8605 + z8606 = x8606 + z8607 = x8607 + z8608 = x8608 + z8609 = x8609 + z8610 = x8610 + z8611 = x8611 + z8612 = x8612 + z8613 = x8613 + z8614 = x8614 + z8615 = x8615 + z8616 = x8616 + z8617 = x8617 + z8618 = x8618 + z8619 = x8619 + z8620 = x8620 + z8621 = x8621 + z8622 = x8622 + z8623 = x8623 + z8624 = x8624 + z8625 = x8625 + z8626 = x8626 + z8627 = x8627 + z8628 = x8628 + z8629 = x8629 + z8630 = x8630 + z8631 = x8631 + z8632 = x8632 + z8633 = x8633 + z8634 = x8634 + z8635 = x8635 + z8636 = x8636 + z8637 = x8637 + z8638 = x8638 + z8639 = x8639 + z8640 = x8640 + z8641 = x8641 + z8642 = x8642 + z8643 = x8643 + z8644 = x8644 + z8645 = x8645 + z8646 = x8646 + z8647 = x8647 + z8648 = x8648 + z8649 = x8649 + z8650 = x8650 + z8651 = x8651 + z8652 = x8652 + z8653 = x8653 + z8654 = x8654 + z8655 = x8655 + z8656 = x8656 + z8657 = x8657 + z8658 = x8658 + z8659 = x8659 + z8660 = x8660 + z8661 = x8661 + z8662 = x8662 + z8663 = x8663 + z8664 = x8664 + z8665 = x8665 + z8666 = x8666 + z8667 = x8667 + z8668 = x8668 + z8669 = x8669 + z8670 = x8670 + z8671 = x8671 + z8672 = x8672 + z8673 = x8673 + z8674 = x8674 + z8675 = x8675 + z8676 = x8676 + z8677 = x8677 + z8678 = x8678 + z8679 = x8679 + z8680 = x8680 + z8681 = x8681 + z8682 = x8682 + z8683 = x8683 + z8684 = x8684 + z8685 = x8685 + z8686 = x8686 + z8687 = x8687 + z8688 = x8688 + z8689 = x8689 + z8690 = x8690 + z8691 = x8691 + z8692 = x8692 + z8693 = x8693 + z8694 = x8694 + z8695 = x8695 + z8696 = x8696 + z8697 = x8697 + z8698 = x8698 + z8699 = x8699 + z8700 = x8700 + z8701 = x8701 + z8702 = x8702 + z8703 = x8703 + z8704 = x8704 + z8705 = x8705 + z8706 = x8706 + z8707 = x8707 + z8708 = x8708 + z8709 = x8709 + z8710 = x8710 + z8711 = x8711 + z8712 = x8712 + z8713 = x8713 + z8714 = x8714 + z8715 = x8715 + z8716 = x8716 + z8717 = x8717 + z8718 = x8718 + z8719 = x8719 + z8720 = x8720 + z8721 = x8721 + z8722 = x8722 + z8723 = x8723 + z8724 = x8724 + z8725 = x8725 + z8726 = x8726 + z8727 = x8727 + z8728 = x8728 + z8729 = x8729 + z8730 = x8730 + z8731 = x8731 + z8732 = x8732 + z8733 = x8733 + z8734 = x8734 + z8735 = x8735 + z8736 = x8736 + z8737 = x8737 + z8738 = x8738 + z8739 = x8739 + z8740 = x8740 + z8741 = x8741 + z8742 = x8742 + z8743 = x8743 + z8744 = x8744 + z8745 = x8745 + z8746 = x8746 + z8747 = x8747 + z8748 = x8748 + z8749 = x8749 + z8750 = x8750 + z8751 = x8751 + z8752 = x8752 + z8753 = x8753 + z8754 = x8754 + z8755 = x8755 + z8756 = x8756 + z8757 = x8757 + z8758 = x8758 + z8759 = x8759 + z8760 = x8760 + z8761 = x8761 + z8762 = x8762 + z8763 = x8763 + z8764 = x8764 + z8765 = x8765 + z8766 = x8766 + z8767 = x8767 + z8768 = x8768 + z8769 = x8769 + z8770 = x8770 + z8771 = x8771 + z8772 = x8772 + z8773 = x8773 + z8774 = x8774 + z8775 = x8775 + z8776 = x8776 + z8777 = x8777 + z8778 = x8778 + z8779 = x8779 + z8780 = x8780 + z8781 = x8781 + z8782 = x8782 + z8783 = x8783 + z8784 = x8784 + z8785 = x8785 + z8786 = x8786 + z8787 = x8787 + z8788 = x8788 + z8789 = x8789 + z8790 = x8790 + z8791 = x8791 + z8792 = x8792 + z8793 = x8793 + z8794 = x8794 + z8795 = x8795 + z8796 = x8796 + z8797 = x8797 + z8798 = x8798 + z8799 = x8799 + z8800 = x8800 + z8801 = x8801 + z8802 = x8802 + z8803 = x8803 + z8804 = x8804 + z8805 = x8805 + z8806 = x8806 + z8807 = x8807 + z8808 = x8808 + z8809 = x8809 + z8810 = x8810 + z8811 = x8811 + z8812 = x8812 + z8813 = x8813 + z8814 = x8814 + z8815 = x8815 + z8816 = x8816 + z8817 = x8817 + z8818 = x8818 + z8819 = x8819 + z8820 = x8820 + z8821 = x8821 + z8822 = x8822 + z8823 = x8823 + z8824 = x8824 + z8825 = x8825 + z8826 = x8826 + z8827 = x8827 + z8828 = x8828 + z8829 = x8829 + z8830 = x8830 + z8831 = x8831 + z8832 = x8832 + z8833 = x8833 + z8834 = x8834 + z8835 = x8835 + z8836 = x8836 + z8837 = x8837 + z8838 = x8838 + z8839 = x8839 + z8840 = x8840 + z8841 = x8841 + z8842 = x8842 + z8843 = x8843 + z8844 = x8844 + z8845 = x8845 + z8846 = x8846 + z8847 = x8847 + z8848 = x8848 + z8849 = x8849 + z8850 = x8850 + z8851 = x8851 + z8852 = x8852 + z8853 = x8853 + z8854 = x8854 + z8855 = x8855 + z8856 = x8856 + z8857 = x8857 + z8858 = x8858 + z8859 = x8859 + z8860 = x8860 + z8861 = x8861 + z8862 = x8862 + z8863 = x8863 + z8864 = x8864 + z8865 = x8865 + z8866 = x8866 + z8867 = x8867 + z8868 = x8868 + z8869 = x8869 + z8870 = x8870 + z8871 = x8871 + z8872 = x8872 + z8873 = x8873 + z8874 = x8874 + z8875 = x8875 + z8876 = x8876 + z8877 = x8877 + z8878 = x8878 + z8879 = x8879 + z8880 = x8880 + z8881 = x8881 + z8882 = x8882 + z8883 = x8883 + z8884 = x8884 + z8885 = x8885 + z8886 = x8886 + z8887 = x8887 + z8888 = x8888 + z8889 = x8889 + z8890 = x8890 + z8891 = x8891 + z8892 = x8892 + z8893 = x8893 + z8894 = x8894 + z8895 = x8895 + z8896 = x8896 + z8897 = x8897 + z8898 = x8898 + z8899 = x8899 + z8900 = x8900 + z8901 = x8901 + z8902 = x8902 + z8903 = x8903 + z8904 = x8904 + z8905 = x8905 + z8906 = x8906 + z8907 = x8907 + z8908 = x8908 + z8909 = x8909 + z8910 = x8910 + z8911 = x8911 + z8912 = x8912 + z8913 = x8913 + z8914 = x8914 + z8915 = x8915 + z8916 = x8916 + z8917 = x8917 + z8918 = x8918 + z8919 = x8919 + z8920 = x8920 + z8921 = x8921 + z8922 = x8922 + z8923 = x8923 + z8924 = x8924 + z8925 = x8925 + z8926 = x8926 + z8927 = x8927 + z8928 = x8928 + z8929 = x8929 + z8930 = x8930 + z8931 = x8931 + z8932 = x8932 + z8933 = x8933 + z8934 = x8934 + z8935 = x8935 + z8936 = x8936 + z8937 = x8937 + z8938 = x8938 + z8939 = x8939 + z8940 = x8940 + z8941 = x8941 + z8942 = x8942 + z8943 = x8943 + z8944 = x8944 + z8945 = x8945 + z8946 = x8946 + z8947 = x8947 + z8948 = x8948 + z8949 = x8949 + z8950 = x8950 + z8951 = x8951 + z8952 = x8952 + z8953 = x8953 + z8954 = x8954 + z8955 = x8955 + z8956 = x8956 + z8957 = x8957 + z8958 = x8958 + z8959 = x8959 + z8960 = x8960 + z8961 = x8961 + z8962 = x8962 + z8963 = x8963 + z8964 = x8964 + z8965 = x8965 + z8966 = x8966 + z8967 = x8967 + z8968 = x8968 + z8969 = x8969 + z8970 = x8970 + z8971 = x8971 + z8972 = x8972 + z8973 = x8973 + z8974 = x8974 + z8975 = x8975 + z8976 = x8976 + z8977 = x8977 + z8978 = x8978 + z8979 = x8979 + z8980 = x8980 + z8981 = x8981 + z8982 = x8982 + z8983 = x8983 + z8984 = x8984 + z8985 = x8985 + z8986 = x8986 + z8987 = x8987 + z8988 = x8988 + z8989 = x8989 + z8990 = x8990 + z8991 = x8991 + z8992 = x8992 + z8993 = x8993 + z8994 = x8994 + z8995 = x8995 + z8996 = x8996 + z8997 = x8997 + z8998 = x8998 + z8999 = x8999 + z9000 = x9000 + z9001 = x9001 + z9002 = x9002 + z9003 = x9003 + z9004 = x9004 + z9005 = x9005 + z9006 = x9006 + z9007 = x9007 + z9008 = x9008 + z9009 = x9009 + z9010 = x9010 + z9011 = x9011 + z9012 = x9012 + z9013 = x9013 + z9014 = x9014 + z9015 = x9015 + z9016 = x9016 + z9017 = x9017 + z9018 = x9018 + z9019 = x9019 + z9020 = x9020 + z9021 = x9021 + z9022 = x9022 + z9023 = x9023 + z9024 = x9024 + z9025 = x9025 + z9026 = x9026 + z9027 = x9027 + z9028 = x9028 + z9029 = x9029 + z9030 = x9030 + z9031 = x9031 + z9032 = x9032 + z9033 = x9033 + z9034 = x9034 + z9035 = x9035 + z9036 = x9036 + z9037 = x9037 + z9038 = x9038 + z9039 = x9039 + z9040 = x9040 + z9041 = x9041 + z9042 = x9042 + z9043 = x9043 + z9044 = x9044 + z9045 = x9045 + z9046 = x9046 + z9047 = x9047 + z9048 = x9048 + z9049 = x9049 + z9050 = x9050 + z9051 = x9051 + z9052 = x9052 + z9053 = x9053 + z9054 = x9054 + z9055 = x9055 + z9056 = x9056 + z9057 = x9057 + z9058 = x9058 + z9059 = x9059 + z9060 = x9060 + z9061 = x9061 + z9062 = x9062 + z9063 = x9063 + z9064 = x9064 + z9065 = x9065 + z9066 = x9066 + z9067 = x9067 + z9068 = x9068 + z9069 = x9069 + z9070 = x9070 + z9071 = x9071 + z9072 = x9072 + z9073 = x9073 + z9074 = x9074 + z9075 = x9075 + z9076 = x9076 + z9077 = x9077 + z9078 = x9078 + z9079 = x9079 + z9080 = x9080 + z9081 = x9081 + z9082 = x9082 + z9083 = x9083 + z9084 = x9084 + z9085 = x9085 + z9086 = x9086 + z9087 = x9087 + z9088 = x9088 + z9089 = x9089 + z9090 = x9090 + z9091 = x9091 + z9092 = x9092 + z9093 = x9093 + z9094 = x9094 + z9095 = x9095 + z9096 = x9096 + z9097 = x9097 + z9098 = x9098 + z9099 = x9099 + z9100 = x9100 + z9101 = x9101 + z9102 = x9102 + z9103 = x9103 + z9104 = x9104 + z9105 = x9105 + z9106 = x9106 + z9107 = x9107 + z9108 = x9108 + z9109 = x9109 + z9110 = x9110 + z9111 = x9111 + z9112 = x9112 + z9113 = x9113 + z9114 = x9114 + z9115 = x9115 + z9116 = x9116 + z9117 = x9117 + z9118 = x9118 + z9119 = x9119 + z9120 = x9120 + z9121 = x9121 + z9122 = x9122 + z9123 = x9123 + z9124 = x9124 + z9125 = x9125 + z9126 = x9126 + z9127 = x9127 + z9128 = x9128 + z9129 = x9129 + z9130 = x9130 + z9131 = x9131 + z9132 = x9132 + z9133 = x9133 + z9134 = x9134 + z9135 = x9135 + z9136 = x9136 + z9137 = x9137 + z9138 = x9138 + z9139 = x9139 + z9140 = x9140 + z9141 = x9141 + z9142 = x9142 + z9143 = x9143 + z9144 = x9144 + z9145 = x9145 + z9146 = x9146 + z9147 = x9147 + z9148 = x9148 + z9149 = x9149 + z9150 = x9150 + z9151 = x9151 + z9152 = x9152 + z9153 = x9153 + z9154 = x9154 + z9155 = x9155 + z9156 = x9156 + z9157 = x9157 + z9158 = x9158 + z9159 = x9159 + z9160 = x9160 + z9161 = x9161 + z9162 = x9162 + z9163 = x9163 + z9164 = x9164 + z9165 = x9165 + z9166 = x9166 + z9167 = x9167 + z9168 = x9168 + z9169 = x9169 + z9170 = x9170 + z9171 = x9171 + z9172 = x9172 + z9173 = x9173 + z9174 = x9174 + z9175 = x9175 + z9176 = x9176 + z9177 = x9177 + z9178 = x9178 + z9179 = x9179 + z9180 = x9180 + z9181 = x9181 + z9182 = x9182 + z9183 = x9183 + z9184 = x9184 + z9185 = x9185 + z9186 = x9186 + z9187 = x9187 + z9188 = x9188 + z9189 = x9189 + z9190 = x9190 + z9191 = x9191 + z9192 = x9192 + z9193 = x9193 + z9194 = x9194 + z9195 = x9195 + z9196 = x9196 + z9197 = x9197 + z9198 = x9198 + z9199 = x9199 + z9200 = x9200 + z9201 = x9201 + z9202 = x9202 + z9203 = x9203 + z9204 = x9204 + z9205 = x9205 + z9206 = x9206 + z9207 = x9207 + z9208 = x9208 + z9209 = x9209 + z9210 = x9210 + z9211 = x9211 + z9212 = x9212 + z9213 = x9213 + z9214 = x9214 + z9215 = x9215 + z9216 = x9216 + z9217 = x9217 + z9218 = x9218 + z9219 = x9219 + z9220 = x9220 + z9221 = x9221 + z9222 = x9222 + z9223 = x9223 + z9224 = x9224 + z9225 = x9225 + z9226 = x9226 + z9227 = x9227 + z9228 = x9228 + z9229 = x9229 + z9230 = x9230 + z9231 = x9231 + z9232 = x9232 + z9233 = x9233 + z9234 = x9234 + z9235 = x9235 + z9236 = x9236 + z9237 = x9237 + z9238 = x9238 + z9239 = x9239 + z9240 = x9240 + z9241 = x9241 + z9242 = x9242 + z9243 = x9243 + z9244 = x9244 + z9245 = x9245 + z9246 = x9246 + z9247 = x9247 + z9248 = x9248 + z9249 = x9249 + z9250 = x9250 + z9251 = x9251 + z9252 = x9252 + z9253 = x9253 + z9254 = x9254 + z9255 = x9255 + z9256 = x9256 + z9257 = x9257 + z9258 = x9258 + z9259 = x9259 + z9260 = x9260 + z9261 = x9261 + z9262 = x9262 + z9263 = x9263 + z9264 = x9264 + z9265 = x9265 + z9266 = x9266 + z9267 = x9267 + z9268 = x9268 + z9269 = x9269 + z9270 = x9270 + z9271 = x9271 + z9272 = x9272 + z9273 = x9273 + z9274 = x9274 + z9275 = x9275 + z9276 = x9276 + z9277 = x9277 + z9278 = x9278 + z9279 = x9279 + z9280 = x9280 + z9281 = x9281 + z9282 = x9282 + z9283 = x9283 + z9284 = x9284 + z9285 = x9285 + z9286 = x9286 + z9287 = x9287 + z9288 = x9288 + z9289 = x9289 + z9290 = x9290 + z9291 = x9291 + z9292 = x9292 + z9293 = x9293 + z9294 = x9294 + z9295 = x9295 + z9296 = x9296 + z9297 = x9297 + z9298 = x9298 + z9299 = x9299 + z9300 = x9300 + z9301 = x9301 + z9302 = x9302 + z9303 = x9303 + z9304 = x9304 + z9305 = x9305 + z9306 = x9306 + z9307 = x9307 + z9308 = x9308 + z9309 = x9309 + z9310 = x9310 + z9311 = x9311 + z9312 = x9312 + z9313 = x9313 + z9314 = x9314 + z9315 = x9315 + z9316 = x9316 + z9317 = x9317 + z9318 = x9318 + z9319 = x9319 + z9320 = x9320 + z9321 = x9321 + z9322 = x9322 + z9323 = x9323 + z9324 = x9324 + z9325 = x9325 + z9326 = x9326 + z9327 = x9327 + z9328 = x9328 + z9329 = x9329 + z9330 = x9330 + z9331 = x9331 + z9332 = x9332 + z9333 = x9333 + z9334 = x9334 + z9335 = x9335 + z9336 = x9336 + z9337 = x9337 + z9338 = x9338 + z9339 = x9339 + z9340 = x9340 + z9341 = x9341 + z9342 = x9342 + z9343 = x9343 + z9344 = x9344 + z9345 = x9345 + z9346 = x9346 + z9347 = x9347 + z9348 = x9348 + z9349 = x9349 + z9350 = x9350 + z9351 = x9351 + z9352 = x9352 + z9353 = x9353 + z9354 = x9354 + z9355 = x9355 + z9356 = x9356 + z9357 = x9357 + z9358 = x9358 + z9359 = x9359 + z9360 = x9360 + z9361 = x9361 + z9362 = x9362 + z9363 = x9363 + z9364 = x9364 + z9365 = x9365 + z9366 = x9366 + z9367 = x9367 + z9368 = x9368 + z9369 = x9369 + z9370 = x9370 + z9371 = x9371 + z9372 = x9372 + z9373 = x9373 + z9374 = x9374 + z9375 = x9375 + z9376 = x9376 + z9377 = x9377 + z9378 = x9378 + z9379 = x9379 + z9380 = x9380 + z9381 = x9381 + z9382 = x9382 + z9383 = x9383 + z9384 = x9384 + z9385 = x9385 + z9386 = x9386 + z9387 = x9387 + z9388 = x9388 + z9389 = x9389 + z9390 = x9390 + z9391 = x9391 + z9392 = x9392 + z9393 = x9393 + z9394 = x9394 + z9395 = x9395 + z9396 = x9396 + z9397 = x9397 + z9398 = x9398 + z9399 = x9399 + z9400 = x9400 + z9401 = x9401 + z9402 = x9402 + z9403 = x9403 + z9404 = x9404 + z9405 = x9405 + z9406 = x9406 + z9407 = x9407 + z9408 = x9408 + z9409 = x9409 + z9410 = x9410 + z9411 = x9411 + z9412 = x9412 + z9413 = x9413 + z9414 = x9414 + z9415 = x9415 + z9416 = x9416 + z9417 = x9417 + z9418 = x9418 + z9419 = x9419 + z9420 = x9420 + z9421 = x9421 + z9422 = x9422 + z9423 = x9423 + z9424 = x9424 + z9425 = x9425 + z9426 = x9426 + z9427 = x9427 + z9428 = x9428 + z9429 = x9429 + z9430 = x9430 + z9431 = x9431 + z9432 = x9432 + z9433 = x9433 + z9434 = x9434 + z9435 = x9435 + z9436 = x9436 + z9437 = x9437 + z9438 = x9438 + z9439 = x9439 + z9440 = x9440 + z9441 = x9441 + z9442 = x9442 + z9443 = x9443 + z9444 = x9444 + z9445 = x9445 + z9446 = x9446 + z9447 = x9447 + z9448 = x9448 + z9449 = x9449 + z9450 = x9450 + z9451 = x9451 + z9452 = x9452 + z9453 = x9453 + z9454 = x9454 + z9455 = x9455 + z9456 = x9456 + z9457 = x9457 + z9458 = x9458 + z9459 = x9459 + z9460 = x9460 + z9461 = x9461 + z9462 = x9462 + z9463 = x9463 + z9464 = x9464 + z9465 = x9465 + z9466 = x9466 + z9467 = x9467 + z9468 = x9468 + z9469 = x9469 + z9470 = x9470 + z9471 = x9471 + z9472 = x9472 + z9473 = x9473 + z9474 = x9474 + z9475 = x9475 + z9476 = x9476 + z9477 = x9477 + z9478 = x9478 + z9479 = x9479 + z9480 = x9480 + z9481 = x9481 + z9482 = x9482 + z9483 = x9483 + z9484 = x9484 + z9485 = x9485 + z9486 = x9486 + z9487 = x9487 + z9488 = x9488 + z9489 = x9489 + z9490 = x9490 + z9491 = x9491 + z9492 = x9492 + z9493 = x9493 + z9494 = x9494 + z9495 = x9495 + z9496 = x9496 + z9497 = x9497 + z9498 = x9498 + z9499 = x9499 + z9500 = x9500 + z9501 = x9501 + z9502 = x9502 + z9503 = x9503 + z9504 = x9504 + z9505 = x9505 + z9506 = x9506 + z9507 = x9507 + z9508 = x9508 + z9509 = x9509 + z9510 = x9510 + z9511 = x9511 + z9512 = x9512 + z9513 = x9513 + z9514 = x9514 + z9515 = x9515 + z9516 = x9516 + z9517 = x9517 + z9518 = x9518 + z9519 = x9519 + z9520 = x9520 + z9521 = x9521 + z9522 = x9522 + z9523 = x9523 + z9524 = x9524 + z9525 = x9525 + z9526 = x9526 + z9527 = x9527 + z9528 = x9528 + z9529 = x9529 + z9530 = x9530 + z9531 = x9531 + z9532 = x9532 + z9533 = x9533 + z9534 = x9534 + z9535 = x9535 + z9536 = x9536 + z9537 = x9537 + z9538 = x9538 + z9539 = x9539 + z9540 = x9540 + z9541 = x9541 + z9542 = x9542 + z9543 = x9543 + z9544 = x9544 + z9545 = x9545 + z9546 = x9546 + z9547 = x9547 + z9548 = x9548 + z9549 = x9549 + z9550 = x9550 + z9551 = x9551 + z9552 = x9552 + z9553 = x9553 + z9554 = x9554 + z9555 = x9555 + z9556 = x9556 + z9557 = x9557 + z9558 = x9558 + z9559 = x9559 + z9560 = x9560 + z9561 = x9561 + z9562 = x9562 + z9563 = x9563 + z9564 = x9564 + z9565 = x9565 + z9566 = x9566 + z9567 = x9567 + z9568 = x9568 + z9569 = x9569 + z9570 = x9570 + z9571 = x9571 + z9572 = x9572 + z9573 = x9573 + z9574 = x9574 + z9575 = x9575 + z9576 = x9576 + z9577 = x9577 + z9578 = x9578 + z9579 = x9579 + z9580 = x9580 + z9581 = x9581 + z9582 = x9582 + z9583 = x9583 + z9584 = x9584 + z9585 = x9585 + z9586 = x9586 + z9587 = x9587 + z9588 = x9588 + z9589 = x9589 + z9590 = x9590 + z9591 = x9591 + z9592 = x9592 + z9593 = x9593 + z9594 = x9594 + z9595 = x9595 + z9596 = x9596 + z9597 = x9597 + z9598 = x9598 + z9599 = x9599 + z9600 = x9600 + z9601 = x9601 + z9602 = x9602 + z9603 = x9603 + z9604 = x9604 + z9605 = x9605 + z9606 = x9606 + z9607 = x9607 + z9608 = x9608 + z9609 = x9609 + z9610 = x9610 + z9611 = x9611 + z9612 = x9612 + z9613 = x9613 + z9614 = x9614 + z9615 = x9615 + z9616 = x9616 + z9617 = x9617 + z9618 = x9618 + z9619 = x9619 + z9620 = x9620 + z9621 = x9621 + z9622 = x9622 + z9623 = x9623 + z9624 = x9624 + z9625 = x9625 + z9626 = x9626 + z9627 = x9627 + z9628 = x9628 + z9629 = x9629 + z9630 = x9630 + z9631 = x9631 + z9632 = x9632 + z9633 = x9633 + z9634 = x9634 + z9635 = x9635 + z9636 = x9636 + z9637 = x9637 + z9638 = x9638 + z9639 = x9639 + z9640 = x9640 + z9641 = x9641 + z9642 = x9642 + z9643 = x9643 + z9644 = x9644 + z9645 = x9645 + z9646 = x9646 + z9647 = x9647 + z9648 = x9648 + z9649 = x9649 + z9650 = x9650 + z9651 = x9651 + z9652 = x9652 + z9653 = x9653 + z9654 = x9654 + z9655 = x9655 + z9656 = x9656 + z9657 = x9657 + z9658 = x9658 + z9659 = x9659 + z9660 = x9660 + z9661 = x9661 + z9662 = x9662 + z9663 = x9663 + z9664 = x9664 + z9665 = x9665 + z9666 = x9666 + z9667 = x9667 + z9668 = x9668 + z9669 = x9669 + z9670 = x9670 + z9671 = x9671 + z9672 = x9672 + z9673 = x9673 + z9674 = x9674 + z9675 = x9675 + z9676 = x9676 + z9677 = x9677 + z9678 = x9678 + z9679 = x9679 + z9680 = x9680 + z9681 = x9681 + z9682 = x9682 + z9683 = x9683 + z9684 = x9684 + z9685 = x9685 + z9686 = x9686 + z9687 = x9687 + z9688 = x9688 + z9689 = x9689 + z9690 = x9690 + z9691 = x9691 + z9692 = x9692 + z9693 = x9693 + z9694 = x9694 + z9695 = x9695 + z9696 = x9696 + z9697 = x9697 + z9698 = x9698 + z9699 = x9699 + z9700 = x9700 + z9701 = x9701 + z9702 = x9702 + z9703 = x9703 + z9704 = x9704 + z9705 = x9705 + z9706 = x9706 + z9707 = x9707 + z9708 = x9708 + z9709 = x9709 + z9710 = x9710 + z9711 = x9711 + z9712 = x9712 + z9713 = x9713 + z9714 = x9714 + z9715 = x9715 + z9716 = x9716 + z9717 = x9717 + z9718 = x9718 + z9719 = x9719 + z9720 = x9720 + z9721 = x9721 + z9722 = x9722 + z9723 = x9723 + z9724 = x9724 + z9725 = x9725 + z9726 = x9726 + z9727 = x9727 + z9728 = x9728 + z9729 = x9729 + z9730 = x9730 + z9731 = x9731 + z9732 = x9732 + z9733 = x9733 + z9734 = x9734 + z9735 = x9735 + z9736 = x9736 + z9737 = x9737 + z9738 = x9738 + z9739 = x9739 + z9740 = x9740 + z9741 = x9741 + z9742 = x9742 + z9743 = x9743 + z9744 = x9744 + z9745 = x9745 + z9746 = x9746 + z9747 = x9747 + z9748 = x9748 + z9749 = x9749 + z9750 = x9750 + z9751 = x9751 + z9752 = x9752 + z9753 = x9753 + z9754 = x9754 + z9755 = x9755 + z9756 = x9756 + z9757 = x9757 + z9758 = x9758 + z9759 = x9759 + z9760 = x9760 + z9761 = x9761 + z9762 = x9762 + z9763 = x9763 + z9764 = x9764 + z9765 = x9765 + z9766 = x9766 + z9767 = x9767 + z9768 = x9768 + z9769 = x9769 + z9770 = x9770 + z9771 = x9771 + z9772 = x9772 + z9773 = x9773 + z9774 = x9774 + z9775 = x9775 + z9776 = x9776 + z9777 = x9777 + z9778 = x9778 + z9779 = x9779 + z9780 = x9780 + z9781 = x9781 + z9782 = x9782 + z9783 = x9783 + z9784 = x9784 + z9785 = x9785 + z9786 = x9786 + z9787 = x9787 + z9788 = x9788 + z9789 = x9789 + z9790 = x9790 + z9791 = x9791 + z9792 = x9792 + z9793 = x9793 + z9794 = x9794 + z9795 = x9795 + z9796 = x9796 + z9797 = x9797 + z9798 = x9798 + z9799 = x9799 + z9800 = x9800 + z9801 = x9801 + z9802 = x9802 + z9803 = x9803 + z9804 = x9804 + z9805 = x9805 + z9806 = x9806 + z9807 = x9807 + z9808 = x9808 + z9809 = x9809 + z9810 = x9810 + z9811 = x9811 + z9812 = x9812 + z9813 = x9813 + z9814 = x9814 + z9815 = x9815 + z9816 = x9816 + z9817 = x9817 + z9818 = x9818 + z9819 = x9819 + z9820 = x9820 + z9821 = x9821 + z9822 = x9822 + z9823 = x9823 + z9824 = x9824 + z9825 = x9825 + z9826 = x9826 + z9827 = x9827 + z9828 = x9828 + z9829 = x9829 + z9830 = x9830 + z9831 = x9831 + z9832 = x9832 + z9833 = x9833 + z9834 = x9834 + z9835 = x9835 + z9836 = x9836 + z9837 = x9837 + z9838 = x9838 + z9839 = x9839 + z9840 = x9840 + z9841 = x9841 + z9842 = x9842 + z9843 = x9843 + z9844 = x9844 + z9845 = x9845 + z9846 = x9846 + z9847 = x9847 + z9848 = x9848 + z9849 = x9849 + z9850 = x9850 + z9851 = x9851 + z9852 = x9852 + z9853 = x9853 + z9854 = x9854 + z9855 = x9855 + z9856 = x9856 + z9857 = x9857 + z9858 = x9858 + z9859 = x9859 + z9860 = x9860 + z9861 = x9861 + z9862 = x9862 + z9863 = x9863 + z9864 = x9864 + z9865 = x9865 + z9866 = x9866 + z9867 = x9867 + z9868 = x9868 + z9869 = x9869 + z9870 = x9870 + z9871 = x9871 + z9872 = x9872 + z9873 = x9873 + z9874 = x9874 + z9875 = x9875 + z9876 = x9876 + z9877 = x9877 + z9878 = x9878 + z9879 = x9879 + z9880 = x9880 + z9881 = x9881 + z9882 = x9882 + z9883 = x9883 + z9884 = x9884 + z9885 = x9885 + z9886 = x9886 + z9887 = x9887 + z9888 = x9888 + z9889 = x9889 + z9890 = x9890 + z9891 = x9891 + z9892 = x9892 + z9893 = x9893 + z9894 = x9894 + z9895 = x9895 + z9896 = x9896 + z9897 = x9897 + z9898 = x9898 + z9899 = x9899 + z9900 = x9900 + z9901 = x9901 + z9902 = x9902 + z9903 = x9903 + z9904 = x9904 + z9905 = x9905 + z9906 = x9906 + z9907 = x9907 + z9908 = x9908 + z9909 = x9909 + z9910 = x9910 + z9911 = x9911 + z9912 = x9912 + z9913 = x9913 + z9914 = x9914 + z9915 = x9915 + z9916 = x9916 + z9917 = x9917 + z9918 = x9918 + z9919 = x9919 + z9920 = x9920 + z9921 = x9921 + z9922 = x9922 + z9923 = x9923 + z9924 = x9924 + z9925 = x9925 + z9926 = x9926 + z9927 = x9927 + z9928 = x9928 + z9929 = x9929 + z9930 = x9930 + z9931 = x9931 + z9932 = x9932 + z9933 = x9933 + z9934 = x9934 + z9935 = x9935 + z9936 = x9936 + z9937 = x9937 + z9938 = x9938 + z9939 = x9939 + z9940 = x9940 + z9941 = x9941 + z9942 = x9942 + z9943 = x9943 + z9944 = x9944 + z9945 = x9945 + z9946 = x9946 + z9947 = x9947 + z9948 = x9948 + z9949 = x9949 + z9950 = x9950 + z9951 = x9951 + z9952 = x9952 + z9953 = x9953 + z9954 = x9954 + z9955 = x9955 + z9956 = x9956 + z9957 = x9957 + z9958 = x9958 + z9959 = x9959 + z9960 = x9960 + z9961 = x9961 + z9962 = x9962 + z9963 = x9963 + z9964 = x9964 + z9965 = x9965 + z9966 = x9966 + z9967 = x9967 + z9968 = x9968 + z9969 = x9969 + z9970 = x9970 + z9971 = x9971 + z9972 = x9972 + z9973 = x9973 + z9974 = x9974 + z9975 = x9975 + z9976 = x9976 + z9977 = x9977 + z9978 = x9978 + z9979 = x9979 + z9980 = x9980 + z9981 = x9981 + z9982 = x9982 + z9983 = x9983 + z9984 = x9984 + z9985 = x9985 + z9986 = x9986 + z9987 = x9987 + z9988 = x9988 + z9989 = x9989 + z9990 = x9990 + z9991 = x9991 + z9992 = x9992 + z9993 = x9993 + z9994 = x9994 + z9995 = x9995 + z9996 = x9996 + z9997 = x9997 + z9998 = x9998 + z9999 = x9999 + z10000 = x10000 + z10001 = x10001 + z10002 = x10002 + z10003 = x10003 + z10004 = x10004 + z10005 = x10005 + z10006 = x10006 + z10007 = x10007 + z10008 = x10008 + z10009 = x10009 + z10010 = x10010 + z10011 = x10011 + z10012 = x10012 + z10013 = x10013 + z10014 = x10014 + z10015 = x10015 + z10016 = x10016 + z10017 = x10017 + z10018 = x10018 + z10019 = x10019 + z10020 = x10020 + z10021 = x10021 + z10022 = x10022 + z10023 = x10023 + z10024 = x10024 + z10025 = x10025 + z10026 = x10026 + z10027 = x10027 + z10028 = x10028 + z10029 = x10029 + z10030 = x10030 + z10031 = x10031 + z10032 = x10032 + z10033 = x10033 + z10034 = x10034 + z10035 = x10035 + z10036 = x10036 + z10037 = x10037 + z10038 = x10038 + z10039 = x10039 + z10040 = x10040 + z10041 = x10041 + z10042 = x10042 + z10043 = x10043 + z10044 = x10044 + z10045 = x10045 + z10046 = x10046 + z10047 = x10047 + z10048 = x10048 + z10049 = x10049 + z10050 = x10050 + z10051 = x10051 + z10052 = x10052 + z10053 = x10053 + z10054 = x10054 + z10055 = x10055 + z10056 = x10056 + z10057 = x10057 + z10058 = x10058 + z10059 = x10059 + z10060 = x10060 + z10061 = x10061 + z10062 = x10062 + z10063 = x10063 + z10064 = x10064 + z10065 = x10065 + z10066 = x10066 + z10067 = x10067 + z10068 = x10068 + z10069 = x10069 + z10070 = x10070 + z10071 = x10071 + z10072 = x10072 + z10073 = x10073 + z10074 = x10074 + z10075 = x10075 + z10076 = x10076 + z10077 = x10077 + z10078 = x10078 + z10079 = x10079 + z10080 = x10080 + z10081 = x10081 + z10082 = x10082 + z10083 = x10083 + z10084 = x10084 + z10085 = x10085 + z10086 = x10086 + z10087 = x10087 + z10088 = x10088 + z10089 = x10089 + z10090 = x10090 + z10091 = x10091 + z10092 = x10092 + z10093 = x10093 + z10094 = x10094 + z10095 = x10095 + z10096 = x10096 + z10097 = x10097 + z10098 = x10098 + z10099 = x10099 + z10100 = x10100 + z10101 = x10101 + z10102 = x10102 + z10103 = x10103 + z10104 = x10104 + z10105 = x10105 + z10106 = x10106 + z10107 = x10107 + z10108 = x10108 + z10109 = x10109 + z10110 = x10110 + z10111 = x10111 + z10112 = x10112 + z10113 = x10113 + z10114 = x10114 + z10115 = x10115 + z10116 = x10116 + z10117 = x10117 + z10118 = x10118 + z10119 = x10119 + z10120 = x10120 + z10121 = x10121 + z10122 = x10122 + z10123 = x10123 + z10124 = x10124 + z10125 = x10125 + z10126 = x10126 + z10127 = x10127 + z10128 = x10128 + z10129 = x10129 + z10130 = x10130 + z10131 = x10131 + z10132 = x10132 + z10133 = x10133 + z10134 = x10134 + z10135 = x10135 + z10136 = x10136 + z10137 = x10137 + z10138 = x10138 + z10139 = x10139 + z10140 = x10140 + z10141 = x10141 + z10142 = x10142 + z10143 = x10143 + z10144 = x10144 + z10145 = x10145 + z10146 = x10146 + z10147 = x10147 + z10148 = x10148 + z10149 = x10149 + z10150 = x10150 + z10151 = x10151 + z10152 = x10152 + z10153 = x10153 + z10154 = x10154 + z10155 = x10155 + z10156 = x10156 + z10157 = x10157 + z10158 = x10158 + z10159 = x10159 + z10160 = x10160 + z10161 = x10161 + z10162 = x10162 + z10163 = x10163 + z10164 = x10164 + z10165 = x10165 + z10166 = x10166 + z10167 = x10167 + z10168 = x10168 + z10169 = x10169 + z10170 = x10170 + z10171 = x10171 + z10172 = x10172 + z10173 = x10173 + z10174 = x10174 + z10175 = x10175 + z10176 = x10176 + z10177 = x10177 + z10178 = x10178 + z10179 = x10179 + z10180 = x10180 + z10181 = x10181 + z10182 = x10182 + z10183 = x10183 + z10184 = x10184 + z10185 = x10185 + z10186 = x10186 + z10187 = x10187 + z10188 = x10188 + z10189 = x10189 + z10190 = x10190 + z10191 = x10191 + z10192 = x10192 + z10193 = x10193 + z10194 = x10194 + z10195 = x10195 + z10196 = x10196 + z10197 = x10197 + z10198 = x10198 + z10199 = x10199 + z10200 = x10200 + z10201 = x10201 + z10202 = x10202 + z10203 = x10203 + z10204 = x10204 + z10205 = x10205 + z10206 = x10206 + z10207 = x10207 + z10208 = x10208 + z10209 = x10209 + z10210 = x10210 + z10211 = x10211 + z10212 = x10212 + z10213 = x10213 + z10214 = x10214 + z10215 = x10215 + z10216 = x10216 + z10217 = x10217 + z10218 = x10218 + z10219 = x10219 + z10220 = x10220 + z10221 = x10221 + z10222 = x10222 + z10223 = x10223 + z10224 = x10224 + z10225 = x10225 + z10226 = x10226 + z10227 = x10227 + z10228 = x10228 + z10229 = x10229 + z10230 = x10230 + z10231 = x10231 + z10232 = x10232 + z10233 = x10233 + z10234 = x10234 + z10235 = x10235 + z10236 = x10236 + z10237 = x10237 + z10238 = x10238 + z10239 = x10239 + z10240 = x10240 + z10241 = x10241 + z10242 = x10242 + z10243 = x10243 + z10244 = x10244 + z10245 = x10245 + z10246 = x10246 + z10247 = x10247 + z10248 = x10248 + z10249 = x10249 + z10250 = x10250 + z10251 = x10251 + z10252 = x10252 + z10253 = x10253 + z10254 = x10254 + z10255 = x10255 + z10256 = x10256 + z10257 = x10257 + z10258 = x10258 + z10259 = x10259 + z10260 = x10260 + z10261 = x10261 + z10262 = x10262 + z10263 = x10263 + z10264 = x10264 + z10265 = x10265 + z10266 = x10266 + z10267 = x10267 + z10268 = x10268 + z10269 = x10269 + z10270 = x10270 + z10271 = x10271 + z10272 = x10272 + z10273 = x10273 + z10274 = x10274 + z10275 = x10275 + z10276 = x10276 + z10277 = x10277 + z10278 = x10278 + z10279 = x10279 + z10280 = x10280 + z10281 = x10281 + z10282 = x10282 + z10283 = x10283 + z10284 = x10284 + z10285 = x10285 + z10286 = x10286 + z10287 = x10287 + z10288 = x10288 + z10289 = x10289 + z10290 = x10290 + z10291 = x10291 + z10292 = x10292 + z10293 = x10293 + z10294 = x10294 + z10295 = x10295 + z10296 = x10296 + z10297 = x10297 + z10298 = x10298 + z10299 = x10299 + z10300 = x10300 + z10301 = x10301 + z10302 = x10302 + z10303 = x10303 + z10304 = x10304 + z10305 = x10305 + z10306 = x10306 + z10307 = x10307 + z10308 = x10308 + z10309 = x10309 + z10310 = x10310 + z10311 = x10311 + z10312 = x10312 + z10313 = x10313 + z10314 = x10314 + z10315 = x10315 + z10316 = x10316 + z10317 = x10317 + z10318 = x10318 + z10319 = x10319 + z10320 = x10320 + z10321 = x10321 + z10322 = x10322 + z10323 = x10323 + z10324 = x10324 + z10325 = x10325 + z10326 = x10326 + z10327 = x10327 + z10328 = x10328 + z10329 = x10329 + z10330 = x10330 + z10331 = x10331 + z10332 = x10332 + z10333 = x10333 + z10334 = x10334 + z10335 = x10335 + z10336 = x10336 + z10337 = x10337 + z10338 = x10338 + z10339 = x10339 + z10340 = x10340 + z10341 = x10341 + z10342 = x10342 + z10343 = x10343 + z10344 = x10344 + z10345 = x10345 + z10346 = x10346 + z10347 = x10347 + z10348 = x10348 + z10349 = x10349 + z10350 = x10350 + z10351 = x10351 + z10352 = x10352 + z10353 = x10353 + z10354 = x10354 + z10355 = x10355 + z10356 = x10356 + z10357 = x10357 + z10358 = x10358 + z10359 = x10359 + z10360 = x10360 + z10361 = x10361 + z10362 = x10362 + z10363 = x10363 + z10364 = x10364 + z10365 = x10365 + z10366 = x10366 + z10367 = x10367 + z10368 = x10368 + z10369 = x10369 + z10370 = x10370 + z10371 = x10371 + z10372 = x10372 + z10373 = x10373 + z10374 = x10374 + z10375 = x10375 + z10376 = x10376 + z10377 = x10377 + z10378 = x10378 + z10379 = x10379 + z10380 = x10380 + z10381 = x10381 + z10382 = x10382 + z10383 = x10383 + z10384 = x10384 + z10385 = x10385 + z10386 = x10386 + z10387 = x10387 + z10388 = x10388 + z10389 = x10389 + z10390 = x10390 + z10391 = x10391 + z10392 = x10392 + z10393 = x10393 + z10394 = x10394 + z10395 = x10395 + z10396 = x10396 + z10397 = x10397 + z10398 = x10398 + z10399 = x10399 + z10400 = x10400 + z10401 = x10401 + z10402 = x10402 + z10403 = x10403 + z10404 = x10404 + z10405 = x10405 + z10406 = x10406 + z10407 = x10407 + z10408 = x10408 + z10409 = x10409 + z10410 = x10410 + z10411 = x10411 + z10412 = x10412 + z10413 = x10413 + z10414 = x10414 + z10415 = x10415 + z10416 = x10416 + z10417 = x10417 + z10418 = x10418 + z10419 = x10419 + z10420 = x10420 + z10421 = x10421 + z10422 = x10422 + z10423 = x10423 + z10424 = x10424 + z10425 = x10425 + z10426 = x10426 + z10427 = x10427 + z10428 = x10428 + z10429 = x10429 + z10430 = x10430 + z10431 = x10431 + z10432 = x10432 + z10433 = x10433 + z10434 = x10434 + z10435 = x10435 + z10436 = x10436 + z10437 = x10437 + z10438 = x10438 + z10439 = x10439 + z10440 = x10440 + z10441 = x10441 + z10442 = x10442 + z10443 = x10443 + z10444 = x10444 + z10445 = x10445 + z10446 = x10446 + z10447 = x10447 + z10448 = x10448 + z10449 = x10449 + z10450 = x10450 + z10451 = x10451 + z10452 = x10452 + z10453 = x10453 + z10454 = x10454 + z10455 = x10455 + z10456 = x10456 + z10457 = x10457 + z10458 = x10458 + z10459 = x10459 + z10460 = x10460 + z10461 = x10461 + z10462 = x10462 + z10463 = x10463 + z10464 = x10464 + z10465 = x10465 + z10466 = x10466 + z10467 = x10467 + z10468 = x10468 + z10469 = x10469 + z10470 = x10470 + z10471 = x10471 + z10472 = x10472 + z10473 = x10473 + z10474 = x10474 + z10475 = x10475 + z10476 = x10476 + z10477 = x10477 + z10478 = x10478 + z10479 = x10479 + z10480 = x10480 + z10481 = x10481 + z10482 = x10482 + z10483 = x10483 + z10484 = x10484 + z10485 = x10485 + z10486 = x10486 + z10487 = x10487 + z10488 = x10488 + z10489 = x10489 + z10490 = x10490 + z10491 = x10491 + z10492 = x10492 + z10493 = x10493 + z10494 = x10494 + z10495 = x10495 + z10496 = x10496 + z10497 = x10497 + z10498 = x10498 + z10499 = x10499 + z10500 = x10500 + z10501 = x10501 + z10502 = x10502 + z10503 = x10503 + z10504 = x10504 + z10505 = x10505 + z10506 = x10506 + z10507 = x10507 + z10508 = x10508 + z10509 = x10509 + z10510 = x10510 + z10511 = x10511 + z10512 = x10512 + z10513 = x10513 + z10514 = x10514 + z10515 = x10515 + z10516 = x10516 + z10517 = x10517 + z10518 = x10518 + z10519 = x10519 + z10520 = x10520 + z10521 = x10521 + z10522 = x10522 + z10523 = x10523 + z10524 = x10524 + z10525 = x10525 + z10526 = x10526 + z10527 = x10527 + z10528 = x10528 + z10529 = x10529 + z10530 = x10530 + z10531 = x10531 + z10532 = x10532 + z10533 = x10533 + z10534 = x10534 + z10535 = x10535 + z10536 = x10536 + z10537 = x10537 + z10538 = x10538 + z10539 = x10539 + z10540 = x10540 + z10541 = x10541 + z10542 = x10542 + z10543 = x10543 + z10544 = x10544 + z10545 = x10545 + z10546 = x10546 + z10547 = x10547 + z10548 = x10548 + z10549 = x10549 + z10550 = x10550 + z10551 = x10551 + z10552 = x10552 + z10553 = x10553 + z10554 = x10554 + z10555 = x10555 + z10556 = x10556 + z10557 = x10557 + z10558 = x10558 + z10559 = x10559 + z10560 = x10560 + z10561 = x10561 + z10562 = x10562 + z10563 = x10563 + z10564 = x10564 + z10565 = x10565 + z10566 = x10566 + z10567 = x10567 + z10568 = x10568 + z10569 = x10569 + z10570 = x10570 + z10571 = x10571 + z10572 = x10572 + z10573 = x10573 + z10574 = x10574 + z10575 = x10575 + z10576 = x10576 + z10577 = x10577 + z10578 = x10578 + z10579 = x10579 + z10580 = x10580 + z10581 = x10581 + z10582 = x10582 + z10583 = x10583 + z10584 = x10584 + z10585 = x10585 + z10586 = x10586 + z10587 = x10587 + z10588 = x10588 + z10589 = x10589 + z10590 = x10590 + z10591 = x10591 + z10592 = x10592 + z10593 = x10593 + z10594 = x10594 + z10595 = x10595 + z10596 = x10596 + z10597 = x10597 + z10598 = x10598 + z10599 = x10599 + z10600 = x10600 + z10601 = x10601 + z10602 = x10602 + z10603 = x10603 + z10604 = x10604 + z10605 = x10605 + z10606 = x10606 + z10607 = x10607 + z10608 = x10608 + z10609 = x10609 + z10610 = x10610 + z10611 = x10611 + z10612 = x10612 + z10613 = x10613 + z10614 = x10614 + z10615 = x10615 + z10616 = x10616 + z10617 = x10617 + z10618 = x10618 + z10619 = x10619 + z10620 = x10620 + z10621 = x10621 + z10622 = x10622 + z10623 = x10623 + z10624 = x10624 + z10625 = x10625 + z10626 = x10626 + z10627 = x10627 + z10628 = x10628 + z10629 = x10629 + z10630 = x10630 + z10631 = x10631 + z10632 = x10632 + z10633 = x10633 + z10634 = x10634 + z10635 = x10635 + z10636 = x10636 + z10637 = x10637 + z10638 = x10638 + z10639 = x10639 + z10640 = x10640 + z10641 = x10641 + z10642 = x10642 + z10643 = x10643 + z10644 = x10644 + z10645 = x10645 + z10646 = x10646 + z10647 = x10647 + z10648 = x10648 + z10649 = x10649 + z10650 = x10650 + z10651 = x10651 + z10652 = x10652 + z10653 = x10653 + z10654 = x10654 + z10655 = x10655 + z10656 = x10656 + z10657 = x10657 + z10658 = x10658 + z10659 = x10659 + z10660 = x10660 + z10661 = x10661 + z10662 = x10662 + z10663 = x10663 + z10664 = x10664 + z10665 = x10665 + z10666 = x10666 + z10667 = x10667 + z10668 = x10668 + z10669 = x10669 + z10670 = x10670 + z10671 = x10671 + z10672 = x10672 + z10673 = x10673 + z10674 = x10674 + z10675 = x10675 + z10676 = x10676 + z10677 = x10677 + z10678 = x10678 + z10679 = x10679 + z10680 = x10680 + z10681 = x10681 + z10682 = x10682 + z10683 = x10683 + z10684 = x10684 + z10685 = x10685 + z10686 = x10686 + z10687 = x10687 + z10688 = x10688 + z10689 = x10689 + z10690 = x10690 + z10691 = x10691 + z10692 = x10692 + z10693 = x10693 + z10694 = x10694 + z10695 = x10695 + z10696 = x10696 + z10697 = x10697 + z10698 = x10698 + z10699 = x10699 + z10700 = x10700 + z10701 = x10701 + z10702 = x10702 + z10703 = x10703 + z10704 = x10704 + z10705 = x10705 + z10706 = x10706 + z10707 = x10707 + z10708 = x10708 + z10709 = x10709 + z10710 = x10710 + z10711 = x10711 + z10712 = x10712 + z10713 = x10713 + z10714 = x10714 + z10715 = x10715 + z10716 = x10716 + z10717 = x10717 + z10718 = x10718 + z10719 = x10719 + z10720 = x10720 + z10721 = x10721 + z10722 = x10722 + z10723 = x10723 + z10724 = x10724 + z10725 = x10725 + z10726 = x10726 + z10727 = x10727 + z10728 = x10728 + z10729 = x10729 + z10730 = x10730 + z10731 = x10731 + z10732 = x10732 + z10733 = x10733 + z10734 = x10734 + z10735 = x10735 + z10736 = x10736 + z10737 = x10737 + z10738 = x10738 + z10739 = x10739 + z10740 = x10740 + z10741 = x10741 + z10742 = x10742 + z10743 = x10743 + z10744 = x10744 + z10745 = x10745 + z10746 = x10746 + z10747 = x10747 + z10748 = x10748 + z10749 = x10749 + z10750 = x10750 + z10751 = x10751 + z10752 = x10752 + z10753 = x10753 + z10754 = x10754 + z10755 = x10755 + z10756 = x10756 + z10757 = x10757 + z10758 = x10758 + z10759 = x10759 + z10760 = x10760 + z10761 = x10761 + z10762 = x10762 + z10763 = x10763 + z10764 = x10764 + z10765 = x10765 + z10766 = x10766 + z10767 = x10767 + z10768 = x10768 + z10769 = x10769 + z10770 = x10770 + z10771 = x10771 + z10772 = x10772 + z10773 = x10773 + z10774 = x10774 + z10775 = x10775 + z10776 = x10776 + z10777 = x10777 + z10778 = x10778 + z10779 = x10779 + z10780 = x10780 + z10781 = x10781 + z10782 = x10782 + z10783 = x10783 + z10784 = x10784 + z10785 = x10785 + z10786 = x10786 + z10787 = x10787 + z10788 = x10788 + z10789 = x10789 + z10790 = x10790 + z10791 = x10791 + z10792 = x10792 + z10793 = x10793 + z10794 = x10794 + z10795 = x10795 + z10796 = x10796 + z10797 = x10797 + z10798 = x10798 + z10799 = x10799 + z10800 = x10800 + z10801 = x10801 + z10802 = x10802 + z10803 = x10803 + z10804 = x10804 + z10805 = x10805 + z10806 = x10806 + z10807 = x10807 + z10808 = x10808 + z10809 = x10809 + z10810 = x10810 + z10811 = x10811 + z10812 = x10812 + z10813 = x10813 + z10814 = x10814 + z10815 = x10815 + z10816 = x10816 + z10817 = x10817 + z10818 = x10818 + z10819 = x10819 + z10820 = x10820 + z10821 = x10821 + z10822 = x10822 + z10823 = x10823 + z10824 = x10824 + z10825 = x10825 + z10826 = x10826 + z10827 = x10827 + z10828 = x10828 + z10829 = x10829 + z10830 = x10830 + z10831 = x10831 + z10832 = x10832 + z10833 = x10833 + z10834 = x10834 + z10835 = x10835 + z10836 = x10836 + z10837 = x10837 + z10838 = x10838 + z10839 = x10839 + z10840 = x10840 + z10841 = x10841 + z10842 = x10842 + z10843 = x10843 + z10844 = x10844 + z10845 = x10845 + z10846 = x10846 + z10847 = x10847 + z10848 = x10848 + z10849 = x10849 + z10850 = x10850 + z10851 = x10851 + z10852 = x10852 + z10853 = x10853 + z10854 = x10854 + z10855 = x10855 + z10856 = x10856 + z10857 = x10857 + z10858 = x10858 + z10859 = x10859 + z10860 = x10860 + z10861 = x10861 + z10862 = x10862 + z10863 = x10863 + z10864 = x10864 + z10865 = x10865 + z10866 = x10866 + z10867 = x10867 + z10868 = x10868 + z10869 = x10869 + z10870 = x10870 + z10871 = x10871 + z10872 = x10872 + z10873 = x10873 + z10874 = x10874 + z10875 = x10875 + z10876 = x10876 + z10877 = x10877 + z10878 = x10878 + z10879 = x10879 + z10880 = x10880 + z10881 = x10881 + z10882 = x10882 + z10883 = x10883 + z10884 = x10884 + z10885 = x10885 + z10886 = x10886 + z10887 = x10887 + z10888 = x10888 + z10889 = x10889 + z10890 = x10890 + z10891 = x10891 + z10892 = x10892 + z10893 = x10893 + z10894 = x10894 + z10895 = x10895 + z10896 = x10896 + z10897 = x10897 + z10898 = x10898 + z10899 = x10899 + z10900 = x10900 + z10901 = x10901 + z10902 = x10902 + z10903 = x10903 + z10904 = x10904 + z10905 = x10905 + z10906 = x10906 + z10907 = x10907 + z10908 = x10908 + z10909 = x10909 + z10910 = x10910 + z10911 = x10911 + z10912 = x10912 + z10913 = x10913 + z10914 = x10914 + z10915 = x10915 + z10916 = x10916 + z10917 = x10917 + z10918 = x10918 + z10919 = x10919 + z10920 = x10920 + z10921 = x10921 + z10922 = x10922 + z10923 = x10923 + z10924 = x10924 + z10925 = x10925 + z10926 = x10926 + z10927 = x10927 + z10928 = x10928 + z10929 = x10929 + z10930 = x10930 + z10931 = x10931 + z10932 = x10932 + z10933 = x10933 + z10934 = x10934 + z10935 = x10935 + z10936 = x10936 + z10937 = x10937 + z10938 = x10938 + z10939 = x10939 + z10940 = x10940 + z10941 = x10941 + z10942 = x10942 + z10943 = x10943 + z10944 = x10944 + z10945 = x10945 + z10946 = x10946 + z10947 = x10947 + z10948 = x10948 + z10949 = x10949 + z10950 = x10950 + z10951 = x10951 + z10952 = x10952 + z10953 = x10953 + z10954 = x10954 + z10955 = x10955 + z10956 = x10956 + z10957 = x10957 + z10958 = x10958 + z10959 = x10959 + z10960 = x10960 + z10961 = x10961 + z10962 = x10962 + z10963 = x10963 + z10964 = x10964 + z10965 = x10965 + z10966 = x10966 + z10967 = x10967 + z10968 = x10968 + z10969 = x10969 + z10970 = x10970 + z10971 = x10971 + z10972 = x10972 + z10973 = x10973 + z10974 = x10974 + z10975 = x10975 + z10976 = x10976 + z10977 = x10977 + z10978 = x10978 + z10979 = x10979 + z10980 = x10980 + z10981 = x10981 + z10982 = x10982 + z10983 = x10983 + z10984 = x10984 + z10985 = x10985 + z10986 = x10986 + z10987 = x10987 + z10988 = x10988 + z10989 = x10989 + z10990 = x10990 + z10991 = x10991 + z10992 = x10992 + z10993 = x10993 + z10994 = x10994 + z10995 = x10995 + z10996 = x10996 + z10997 = x10997 + z10998 = x10998 + z10999 = x10999 + z11000 = x11000 + z11001 = x11001 + z11002 = x11002 + z11003 = x11003 + z11004 = x11004 + z11005 = x11005 + z11006 = x11006 + z11007 = x11007 + z11008 = x11008 + z11009 = x11009 + z11010 = x11010 + z11011 = x11011 + z11012 = x11012 + z11013 = x11013 + z11014 = x11014 + z11015 = x11015 + z11016 = x11016 + z11017 = x11017 + z11018 = x11018 + z11019 = x11019 + z11020 = x11020 + z11021 = x11021 + z11022 = x11022 + z11023 = x11023 + z11024 = x11024 + z11025 = x11025 + z11026 = x11026 + z11027 = x11027 + z11028 = x11028 + z11029 = x11029 + z11030 = x11030 + z11031 = x11031 + z11032 = x11032 + z11033 = x11033 + z11034 = x11034 + z11035 = x11035 + z11036 = x11036 + z11037 = x11037 + z11038 = x11038 + z11039 = x11039 + z11040 = x11040 + z11041 = x11041 + z11042 = x11042 + z11043 = x11043 + z11044 = x11044 + z11045 = x11045 + z11046 = x11046 + z11047 = x11047 + z11048 = x11048 + z11049 = x11049 + z11050 = x11050 + z11051 = x11051 + z11052 = x11052 + z11053 = x11053 + z11054 = x11054 + z11055 = x11055 + z11056 = x11056 + z11057 = x11057 + z11058 = x11058 + z11059 = x11059 + z11060 = x11060 + z11061 = x11061 + z11062 = x11062 + z11063 = x11063 + z11064 = x11064 + z11065 = x11065 + z11066 = x11066 + z11067 = x11067 + z11068 = x11068 + z11069 = x11069 + z11070 = x11070 + z11071 = x11071 + z11072 = x11072 + z11073 = x11073 + z11074 = x11074 + z11075 = x11075 + z11076 = x11076 + z11077 = x11077 + z11078 = x11078 + z11079 = x11079 + z11080 = x11080 + z11081 = x11081 + z11082 = x11082 + z11083 = x11083 + z11084 = x11084 + z11085 = x11085 + z11086 = x11086 + z11087 = x11087 + z11088 = x11088 + z11089 = x11089 + z11090 = x11090 + z11091 = x11091 + z11092 = x11092 + z11093 = x11093 + z11094 = x11094 + z11095 = x11095 + z11096 = x11096 + z11097 = x11097 + z11098 = x11098 + z11099 = x11099 + z11100 = x11100 + z11101 = x11101 + z11102 = x11102 + z11103 = x11103 + z11104 = x11104 + z11105 = x11105 + z11106 = x11106 + z11107 = x11107 + z11108 = x11108 + z11109 = x11109 + z11110 = x11110 + z11111 = x11111 + z11112 = x11112 + z11113 = x11113 + z11114 = x11114 + z11115 = x11115 + z11116 = x11116 + z11117 = x11117 + z11118 = x11118 + z11119 = x11119 + z11120 = x11120 + z11121 = x11121 + z11122 = x11122 + z11123 = x11123 + z11124 = x11124 + z11125 = x11125 + z11126 = x11126 + z11127 = x11127 + z11128 = x11128 + z11129 = x11129 + z11130 = x11130 + z11131 = x11131 + z11132 = x11132 + z11133 = x11133 + z11134 = x11134 + z11135 = x11135 + z11136 = x11136 + z11137 = x11137 + z11138 = x11138 + z11139 = x11139 + z11140 = x11140 + z11141 = x11141 + z11142 = x11142 + z11143 = x11143 + z11144 = x11144 + z11145 = x11145 + z11146 = x11146 + z11147 = x11147 + z11148 = x11148 + z11149 = x11149 + z11150 = x11150 + z11151 = x11151 + z11152 = x11152 + z11153 = x11153 + z11154 = x11154 + z11155 = x11155 + z11156 = x11156 + z11157 = x11157 + z11158 = x11158 + z11159 = x11159 + z11160 = x11160 + z11161 = x11161 + z11162 = x11162 + z11163 = x11163 + z11164 = x11164 + z11165 = x11165 + z11166 = x11166 + z11167 = x11167 + z11168 = x11168 + z11169 = x11169 + z11170 = x11170 + z11171 = x11171 + z11172 = x11172 + z11173 = x11173 + z11174 = x11174 + z11175 = x11175 + z11176 = x11176 + z11177 = x11177 + z11178 = x11178 + z11179 = x11179 + z11180 = x11180 + z11181 = x11181 + z11182 = x11182 + z11183 = x11183 + z11184 = x11184 + z11185 = x11185 + z11186 = x11186 + z11187 = x11187 + z11188 = x11188 + z11189 = x11189 + z11190 = x11190 + z11191 = x11191 + z11192 = x11192 + z11193 = x11193 + z11194 = x11194 + z11195 = x11195 + z11196 = x11196 + z11197 = x11197 + z11198 = x11198 + z11199 = x11199 + z11200 = x11200 + z11201 = x11201 + z11202 = x11202 + z11203 = x11203 + z11204 = x11204 + z11205 = x11205 + z11206 = x11206 + z11207 = x11207 + z11208 = x11208 + z11209 = x11209 + z11210 = x11210 + z11211 = x11211 + z11212 = x11212 + z11213 = x11213 + z11214 = x11214 + z11215 = x11215 + z11216 = x11216 + z11217 = x11217 + z11218 = x11218 + z11219 = x11219 + z11220 = x11220 + z11221 = x11221 + z11222 = x11222 + z11223 = x11223 + z11224 = x11224 + z11225 = x11225 + z11226 = x11226 + z11227 = x11227 + z11228 = x11228 + z11229 = x11229 + z11230 = x11230 + z11231 = x11231 + z11232 = x11232 + z11233 = x11233 + z11234 = x11234 + z11235 = x11235 + z11236 = x11236 + z11237 = x11237 + z11238 = x11238 + z11239 = x11239 + z11240 = x11240 + z11241 = x11241 + z11242 = x11242 + z11243 = x11243 + z11244 = x11244 + z11245 = x11245 + z11246 = x11246 + z11247 = x11247 + z11248 = x11248 + z11249 = x11249 + z11250 = x11250 + z11251 = x11251 + z11252 = x11252 + z11253 = x11253 + z11254 = x11254 + z11255 = x11255 + z11256 = x11256 + z11257 = x11257 + z11258 = x11258 + z11259 = x11259 + z11260 = x11260 + z11261 = x11261 + z11262 = x11262 + z11263 = x11263 + z11264 = x11264 + z11265 = x11265 + z11266 = x11266 + z11267 = x11267 + z11268 = x11268 + z11269 = x11269 + z11270 = x11270 + z11271 = x11271 + z11272 = x11272 + z11273 = x11273 + z11274 = x11274 + z11275 = x11275 + z11276 = x11276 + z11277 = x11277 + z11278 = x11278 + z11279 = x11279 + z11280 = x11280 + z11281 = x11281 + z11282 = x11282 + z11283 = x11283 + z11284 = x11284 + z11285 = x11285 + z11286 = x11286 + z11287 = x11287 + z11288 = x11288 + z11289 = x11289 + z11290 = x11290 + z11291 = x11291 + z11292 = x11292 + z11293 = x11293 + z11294 = x11294 + z11295 = x11295 + z11296 = x11296 + z11297 = x11297 + z11298 = x11298 + z11299 = x11299 + z11300 = x11300 + z11301 = x11301 + z11302 = x11302 + z11303 = x11303 + z11304 = x11304 + z11305 = x11305 + z11306 = x11306 + z11307 = x11307 + z11308 = x11308 + z11309 = x11309 + z11310 = x11310 + z11311 = x11311 + z11312 = x11312 + z11313 = x11313 + z11314 = x11314 + z11315 = x11315 + z11316 = x11316 + z11317 = x11317 + z11318 = x11318 + z11319 = x11319 + z11320 = x11320 + z11321 = x11321 + z11322 = x11322 + z11323 = x11323 + z11324 = x11324 + z11325 = x11325 + z11326 = x11326 + z11327 = x11327 + z11328 = x11328 + z11329 = x11329 + z11330 = x11330 + z11331 = x11331 + z11332 = x11332 + z11333 = x11333 + z11334 = x11334 + z11335 = x11335 + z11336 = x11336 + z11337 = x11337 + z11338 = x11338 + z11339 = x11339 + z11340 = x11340 + z11341 = x11341 + z11342 = x11342 + z11343 = x11343 + z11344 = x11344 + z11345 = x11345 + z11346 = x11346 + z11347 = x11347 + z11348 = x11348 + z11349 = x11349 + z11350 = x11350 + z11351 = x11351 + z11352 = x11352 + z11353 = x11353 + z11354 = x11354 + z11355 = x11355 + z11356 = x11356 + z11357 = x11357 + z11358 = x11358 + z11359 = x11359 + z11360 = x11360 + z11361 = x11361 + z11362 = x11362 + z11363 = x11363 + z11364 = x11364 + z11365 = x11365 + z11366 = x11366 + z11367 = x11367 + z11368 = x11368 + z11369 = x11369 + z11370 = x11370 + z11371 = x11371 + z11372 = x11372 + z11373 = x11373 + z11374 = x11374 + z11375 = x11375 + z11376 = x11376 + z11377 = x11377 + z11378 = x11378 + z11379 = x11379 + z11380 = x11380 + z11381 = x11381 + z11382 = x11382 + z11383 = x11383 + z11384 = x11384 + z11385 = x11385 + z11386 = x11386 + z11387 = x11387 + z11388 = x11388 + z11389 = x11389 + z11390 = x11390 + z11391 = x11391 + z11392 = x11392 + z11393 = x11393 + z11394 = x11394 + z11395 = x11395 + z11396 = x11396 + z11397 = x11397 + z11398 = x11398 + z11399 = x11399 + z11400 = x11400 + z11401 = x11401 + z11402 = x11402 + z11403 = x11403 + z11404 = x11404 + z11405 = x11405 + z11406 = x11406 + z11407 = x11407 + z11408 = x11408 + z11409 = x11409 + z11410 = x11410 + z11411 = x11411 + z11412 = x11412 + z11413 = x11413 + z11414 = x11414 + z11415 = x11415 + z11416 = x11416 + z11417 = x11417 + z11418 = x11418 + z11419 = x11419 + z11420 = x11420 + z11421 = x11421 + z11422 = x11422 + z11423 = x11423 + z11424 = x11424 + z11425 = x11425 + z11426 = x11426 + z11427 = x11427 + z11428 = x11428 + z11429 = x11429 + z11430 = x11430 + z11431 = x11431 + z11432 = x11432 + z11433 = x11433 + z11434 = x11434 + z11435 = x11435 + z11436 = x11436 + z11437 = x11437 + z11438 = x11438 + z11439 = x11439 + z11440 = x11440 + z11441 = x11441 + z11442 = x11442 + z11443 = x11443 + z11444 = x11444 + z11445 = x11445 + z11446 = x11446 + z11447 = x11447 + z11448 = x11448 + z11449 = x11449 + z11450 = x11450 + z11451 = x11451 + z11452 = x11452 + z11453 = x11453 + z11454 = x11454 + z11455 = x11455 + z11456 = x11456 + z11457 = x11457 + z11458 = x11458 + z11459 = x11459 + z11460 = x11460 + z11461 = x11461 + z11462 = x11462 + z11463 = x11463 + z11464 = x11464 + z11465 = x11465 + z11466 = x11466 + z11467 = x11467 + z11468 = x11468 + z11469 = x11469 + z11470 = x11470 + z11471 = x11471 + z11472 = x11472 + z11473 = x11473 + z11474 = x11474 + z11475 = x11475 + z11476 = x11476 + z11477 = x11477 + z11478 = x11478 + z11479 = x11479 + z11480 = x11480 + z11481 = x11481 + z11482 = x11482 + z11483 = x11483 + z11484 = x11484 + z11485 = x11485 + z11486 = x11486 + z11487 = x11487 + z11488 = x11488 + z11489 = x11489 + z11490 = x11490 + z11491 = x11491 + z11492 = x11492 + z11493 = x11493 + z11494 = x11494 + z11495 = x11495 + z11496 = x11496 + z11497 = x11497 + z11498 = x11498 + z11499 = x11499 + z11500 = x11500 + z11501 = x11501 + z11502 = x11502 + z11503 = x11503 + z11504 = x11504 + z11505 = x11505 + z11506 = x11506 + z11507 = x11507 + z11508 = x11508 + z11509 = x11509 + z11510 = x11510 + z11511 = x11511 + z11512 = x11512 + z11513 = x11513 + z11514 = x11514 + z11515 = x11515 + z11516 = x11516 + z11517 = x11517 + z11518 = x11518 + z11519 = x11519 + z11520 = x11520 + z11521 = x11521 + z11522 = x11522 + z11523 = x11523 + z11524 = x11524 + z11525 = x11525 + z11526 = x11526 + z11527 = x11527 + z11528 = x11528 + z11529 = x11529 + z11530 = x11530 + z11531 = x11531 + z11532 = x11532 + z11533 = x11533 + z11534 = x11534 + z11535 = x11535 + z11536 = x11536 + z11537 = x11537 + z11538 = x11538 + z11539 = x11539 + z11540 = x11540 + z11541 = x11541 + z11542 = x11542 + z11543 = x11543 + z11544 = x11544 + z11545 = x11545 + z11546 = x11546 + z11547 = x11547 + z11548 = x11548 + z11549 = x11549 + z11550 = x11550 + z11551 = x11551 + z11552 = x11552 + z11553 = x11553 + z11554 = x11554 + z11555 = x11555 + z11556 = x11556 + z11557 = x11557 + z11558 = x11558 + z11559 = x11559 + z11560 = x11560 + z11561 = x11561 + z11562 = x11562 + z11563 = x11563 + z11564 = x11564 + z11565 = x11565 + z11566 = x11566 + z11567 = x11567 + z11568 = x11568 + z11569 = x11569 + z11570 = x11570 + z11571 = x11571 + z11572 = x11572 + z11573 = x11573 + z11574 = x11574 + z11575 = x11575 + z11576 = x11576 + z11577 = x11577 + z11578 = x11578 + z11579 = x11579 + z11580 = x11580 + z11581 = x11581 + z11582 = x11582 + z11583 = x11583 + z11584 = x11584 + z11585 = x11585 + z11586 = x11586 + z11587 = x11587 + z11588 = x11588 + z11589 = x11589 + z11590 = x11590 + z11591 = x11591 + z11592 = x11592 + z11593 = x11593 + z11594 = x11594 + z11595 = x11595 + z11596 = x11596 + z11597 = x11597 + z11598 = x11598 + z11599 = x11599 + z11600 = x11600 + z11601 = x11601 + z11602 = x11602 + z11603 = x11603 + z11604 = x11604 + z11605 = x11605 + z11606 = x11606 + z11607 = x11607 + z11608 = x11608 + z11609 = x11609 + z11610 = x11610 + z11611 = x11611 + z11612 = x11612 + z11613 = x11613 + z11614 = x11614 + z11615 = x11615 + z11616 = x11616 + z11617 = x11617 + z11618 = x11618 + z11619 = x11619 + z11620 = x11620 + z11621 = x11621 + z11622 = x11622 + z11623 = x11623 + z11624 = x11624 + z11625 = x11625 + z11626 = x11626 + z11627 = x11627 + z11628 = x11628 + z11629 = x11629 + z11630 = x11630 + z11631 = x11631 + z11632 = x11632 + z11633 = x11633 + z11634 = x11634 + z11635 = x11635 + z11636 = x11636 + z11637 = x11637 + z11638 = x11638 + z11639 = x11639 + z11640 = x11640 + z11641 = x11641 + z11642 = x11642 + z11643 = x11643 + z11644 = x11644 + z11645 = x11645 + z11646 = x11646 + z11647 = x11647 + z11648 = x11648 + z11649 = x11649 + z11650 = x11650 + z11651 = x11651 + z11652 = x11652 + z11653 = x11653 + z11654 = x11654 + z11655 = x11655 + z11656 = x11656 + z11657 = x11657 + z11658 = x11658 + z11659 = x11659 + z11660 = x11660 + z11661 = x11661 + z11662 = x11662 + z11663 = x11663 + z11664 = x11664 + z11665 = x11665 + z11666 = x11666 + z11667 = x11667 + z11668 = x11668 + z11669 = x11669 + z11670 = x11670 + z11671 = x11671 + z11672 = x11672 + z11673 = x11673 + z11674 = x11674 + z11675 = x11675 + z11676 = x11676 + z11677 = x11677 + z11678 = x11678 + z11679 = x11679 + z11680 = x11680 + z11681 = x11681 + z11682 = x11682 + z11683 = x11683 + z11684 = x11684 + z11685 = x11685 + z11686 = x11686 + z11687 = x11687 + z11688 = x11688 + z11689 = x11689 + z11690 = x11690 + z11691 = x11691 + z11692 = x11692 + z11693 = x11693 + z11694 = x11694 + z11695 = x11695 + z11696 = x11696 + z11697 = x11697 + z11698 = x11698 + z11699 = x11699 + z11700 = x11700 + z11701 = x11701 + z11702 = x11702 + z11703 = x11703 + z11704 = x11704 + z11705 = x11705 + z11706 = x11706 + z11707 = x11707 + z11708 = x11708 + z11709 = x11709 + z11710 = x11710 + z11711 = x11711 + z11712 = x11712 + z11713 = x11713 + z11714 = x11714 + z11715 = x11715 + z11716 = x11716 + z11717 = x11717 + z11718 = x11718 + z11719 = x11719 + z11720 = x11720 + z11721 = x11721 + z11722 = x11722 + z11723 = x11723 + z11724 = x11724 + z11725 = x11725 + z11726 = x11726 + z11727 = x11727 + z11728 = x11728 + z11729 = x11729 + z11730 = x11730 + z11731 = x11731 + z11732 = x11732 + z11733 = x11733 + z11734 = x11734 + z11735 = x11735 + z11736 = x11736 + z11737 = x11737 + z11738 = x11738 + z11739 = x11739 + z11740 = x11740 + z11741 = x11741 + z11742 = x11742 + z11743 = x11743 + z11744 = x11744 + z11745 = x11745 + z11746 = x11746 + z11747 = x11747 + z11748 = x11748 + z11749 = x11749 + z11750 = x11750 + z11751 = x11751 + z11752 = x11752 + z11753 = x11753 + z11754 = x11754 + z11755 = x11755 + z11756 = x11756 + z11757 = x11757 + z11758 = x11758 + z11759 = x11759 + z11760 = x11760 + z11761 = x11761 + z11762 = x11762 + z11763 = x11763 + z11764 = x11764 + z11765 = x11765 + z11766 = x11766 + z11767 = x11767 + z11768 = x11768 + z11769 = x11769 + z11770 = x11770 + z11771 = x11771 + z11772 = x11772 + z11773 = x11773 + z11774 = x11774 + z11775 = x11775 + z11776 = x11776 + z11777 = x11777 + z11778 = x11778 + z11779 = x11779 + z11780 = x11780 + z11781 = x11781 + z11782 = x11782 + z11783 = x11783 + z11784 = x11784 + z11785 = x11785 + z11786 = x11786 + z11787 = x11787 + z11788 = x11788 + z11789 = x11789 + z11790 = x11790 + z11791 = x11791 + z11792 = x11792 + z11793 = x11793 + z11794 = x11794 + z11795 = x11795 + z11796 = x11796 + z11797 = x11797 + z11798 = x11798 + z11799 = x11799 + z11800 = x11800 + z11801 = x11801 + z11802 = x11802 + z11803 = x11803 + z11804 = x11804 + z11805 = x11805 + z11806 = x11806 + z11807 = x11807 + z11808 = x11808 + z11809 = x11809 + z11810 = x11810 + z11811 = x11811 + z11812 = x11812 + z11813 = x11813 + z11814 = x11814 + z11815 = x11815 + z11816 = x11816 + z11817 = x11817 + z11818 = x11818 + z11819 = x11819 + z11820 = x11820 + z11821 = x11821 + z11822 = x11822 + z11823 = x11823 + z11824 = x11824 + z11825 = x11825 + z11826 = x11826 + z11827 = x11827 + z11828 = x11828 + z11829 = x11829 + z11830 = x11830 + z11831 = x11831 + z11832 = x11832 + z11833 = x11833 + z11834 = x11834 + z11835 = x11835 + z11836 = x11836 + z11837 = x11837 + z11838 = x11838 + z11839 = x11839 + z11840 = x11840 + z11841 = x11841 + z11842 = x11842 + z11843 = x11843 + z11844 = x11844 + z11845 = x11845 + z11846 = x11846 + z11847 = x11847 + z11848 = x11848 + z11849 = x11849 + z11850 = x11850 + z11851 = x11851 + z11852 = x11852 + z11853 = x11853 + z11854 = x11854 + z11855 = x11855 + z11856 = x11856 + z11857 = x11857 + z11858 = x11858 + z11859 = x11859 + z11860 = x11860 + z11861 = x11861 + z11862 = x11862 + z11863 = x11863 + z11864 = x11864 + z11865 = x11865 + z11866 = x11866 + z11867 = x11867 + z11868 = x11868 + z11869 = x11869 + z11870 = x11870 + z11871 = x11871 + z11872 = x11872 + z11873 = x11873 + z11874 = x11874 + z11875 = x11875 + z11876 = x11876 + z11877 = x11877 + z11878 = x11878 + z11879 = x11879 + z11880 = x11880 + z11881 = x11881 + z11882 = x11882 + z11883 = x11883 + z11884 = x11884 + z11885 = x11885 + z11886 = x11886 + z11887 = x11887 + z11888 = x11888 + z11889 = x11889 + z11890 = x11890 + z11891 = x11891 + z11892 = x11892 + z11893 = x11893 + z11894 = x11894 + z11895 = x11895 + z11896 = x11896 + z11897 = x11897 + z11898 = x11898 + z11899 = x11899 + z11900 = x11900 + z11901 = x11901 + z11902 = x11902 + z11903 = x11903 + z11904 = x11904 + z11905 = x11905 + z11906 = x11906 + z11907 = x11907 + z11908 = x11908 + z11909 = x11909 + z11910 = x11910 + z11911 = x11911 + z11912 = x11912 + z11913 = x11913 + z11914 = x11914 + z11915 = x11915 + z11916 = x11916 + z11917 = x11917 + z11918 = x11918 + z11919 = x11919 + z11920 = x11920 + z11921 = x11921 + z11922 = x11922 + z11923 = x11923 + z11924 = x11924 + z11925 = x11925 + z11926 = x11926 + z11927 = x11927 + z11928 = x11928 + z11929 = x11929 + z11930 = x11930 + z11931 = x11931 + z11932 = x11932 + z11933 = x11933 + z11934 = x11934 + z11935 = x11935 + z11936 = x11936 + z11937 = x11937 + z11938 = x11938 + z11939 = x11939 + z11940 = x11940 + z11941 = x11941 + z11942 = x11942 + z11943 = x11943 + z11944 = x11944 + z11945 = x11945 + z11946 = x11946 + z11947 = x11947 + z11948 = x11948 + z11949 = x11949 + z11950 = x11950 + z11951 = x11951 + z11952 = x11952 + z11953 = x11953 + z11954 = x11954 + z11955 = x11955 + z11956 = x11956 + z11957 = x11957 + z11958 = x11958 + z11959 = x11959 + z11960 = x11960 + z11961 = x11961 + z11962 = x11962 + z11963 = x11963 + z11964 = x11964 + z11965 = x11965 + z11966 = x11966 + z11967 = x11967 + z11968 = x11968 + z11969 = x11969 + z11970 = x11970 + z11971 = x11971 + z11972 = x11972 + z11973 = x11973 + z11974 = x11974 + z11975 = x11975 + z11976 = x11976 + z11977 = x11977 + z11978 = x11978 + z11979 = x11979 + z11980 = x11980 + z11981 = x11981 + z11982 = x11982 + z11983 = x11983 + z11984 = x11984 + z11985 = x11985 + z11986 = x11986 + z11987 = x11987 + z11988 = x11988 + z11989 = x11989 + z11990 = x11990 + z11991 = x11991 + z11992 = x11992 + z11993 = x11993 + z11994 = x11994 + z11995 = x11995 + z11996 = x11996 + z11997 = x11997 + z11998 = x11998 + z11999 = x11999 + z12000 = x12000 + z12001 = x12001 + z12002 = x12002 + z12003 = x12003 + z12004 = x12004 + z12005 = x12005 + z12006 = x12006 + z12007 = x12007 + z12008 = x12008 + z12009 = x12009 + z12010 = x12010 + z12011 = x12011 + z12012 = x12012 + z12013 = x12013 + z12014 = x12014 + z12015 = x12015 + z12016 = x12016 + z12017 = x12017 + z12018 = x12018 + z12019 = x12019 + z12020 = x12020 + z12021 = x12021 + z12022 = x12022 + z12023 = x12023 + z12024 = x12024 + z12025 = x12025 + z12026 = x12026 + z12027 = x12027 + z12028 = x12028 + z12029 = x12029 + z12030 = x12030 + z12031 = x12031 + z12032 = x12032 + z12033 = x12033 + z12034 = x12034 + z12035 = x12035 + z12036 = x12036 + z12037 = x12037 + z12038 = x12038 + z12039 = x12039 + z12040 = x12040 + z12041 = x12041 + z12042 = x12042 + z12043 = x12043 + z12044 = x12044 + z12045 = x12045 + z12046 = x12046 + z12047 = x12047 + z12048 = x12048 + z12049 = x12049 + z12050 = x12050 + z12051 = x12051 + z12052 = x12052 + z12053 = x12053 + z12054 = x12054 + z12055 = x12055 + z12056 = x12056 + z12057 = x12057 + z12058 = x12058 + z12059 = x12059 + z12060 = x12060 + z12061 = x12061 + z12062 = x12062 + z12063 = x12063 + z12064 = x12064 + z12065 = x12065 + z12066 = x12066 + z12067 = x12067 + z12068 = x12068 + z12069 = x12069 + z12070 = x12070 + z12071 = x12071 + z12072 = x12072 + z12073 = x12073 + z12074 = x12074 + z12075 = x12075 + z12076 = x12076 + z12077 = x12077 + z12078 = x12078 + z12079 = x12079 + z12080 = x12080 + z12081 = x12081 + z12082 = x12082 + z12083 = x12083 + z12084 = x12084 + z12085 = x12085 + z12086 = x12086 + z12087 = x12087 + z12088 = x12088 + z12089 = x12089 + z12090 = x12090 + z12091 = x12091 + z12092 = x12092 + z12093 = x12093 + z12094 = x12094 + z12095 = x12095 + z12096 = x12096 + z12097 = x12097 + z12098 = x12098 + z12099 = x12099 + z12100 = x12100 + z12101 = x12101 + z12102 = x12102 + z12103 = x12103 + z12104 = x12104 + z12105 = x12105 + z12106 = x12106 + z12107 = x12107 + z12108 = x12108 + z12109 = x12109 + z12110 = x12110 + z12111 = x12111 + z12112 = x12112 + z12113 = x12113 + z12114 = x12114 + z12115 = x12115 + z12116 = x12116 + z12117 = x12117 + z12118 = x12118 + z12119 = x12119 + z12120 = x12120 + z12121 = x12121 + z12122 = x12122 + z12123 = x12123 + z12124 = x12124 + z12125 = x12125 + z12126 = x12126 + z12127 = x12127 + z12128 = x12128 + z12129 = x12129 + z12130 = x12130 + z12131 = x12131 + z12132 = x12132 + z12133 = x12133 + z12134 = x12134 + z12135 = x12135 + z12136 = x12136 + z12137 = x12137 + z12138 = x12138 + z12139 = x12139 + z12140 = x12140 + z12141 = x12141 + z12142 = x12142 + z12143 = x12143 + z12144 = x12144 + z12145 = x12145 + z12146 = x12146 + z12147 = x12147 + z12148 = x12148 + z12149 = x12149 + z12150 = x12150 + z12151 = x12151 + z12152 = x12152 + z12153 = x12153 + z12154 = x12154 + z12155 = x12155 + z12156 = x12156 + z12157 = x12157 + z12158 = x12158 + z12159 = x12159 + z12160 = x12160 + z12161 = x12161 + z12162 = x12162 + z12163 = x12163 + z12164 = x12164 + z12165 = x12165 + z12166 = x12166 + z12167 = x12167 + z12168 = x12168 + z12169 = x12169 + z12170 = x12170 + z12171 = x12171 + z12172 = x12172 + z12173 = x12173 + z12174 = x12174 + z12175 = x12175 + z12176 = x12176 + z12177 = x12177 + z12178 = x12178 + z12179 = x12179 + z12180 = x12180 + z12181 = x12181 + z12182 = x12182 + z12183 = x12183 + z12184 = x12184 + z12185 = x12185 + z12186 = x12186 + z12187 = x12187 + z12188 = x12188 + z12189 = x12189 + z12190 = x12190 + z12191 = x12191 + z12192 = x12192 + z12193 = x12193 + z12194 = x12194 + z12195 = x12195 + z12196 = x12196 + z12197 = x12197 + z12198 = x12198 + z12199 = x12199 + z12200 = x12200 + z12201 = x12201 + z12202 = x12202 + z12203 = x12203 + z12204 = x12204 + z12205 = x12205 + z12206 = x12206 + z12207 = x12207 + z12208 = x12208 + z12209 = x12209 + z12210 = x12210 + z12211 = x12211 + z12212 = x12212 + z12213 = x12213 + z12214 = x12214 + z12215 = x12215 + z12216 = x12216 + z12217 = x12217 + z12218 = x12218 + z12219 = x12219 + z12220 = x12220 + z12221 = x12221 + z12222 = x12222 + z12223 = x12223 + z12224 = x12224 + z12225 = x12225 + z12226 = x12226 + z12227 = x12227 + z12228 = x12228 + z12229 = x12229 + z12230 = x12230 + z12231 = x12231 + z12232 = x12232 + z12233 = x12233 + z12234 = x12234 + z12235 = x12235 + z12236 = x12236 + z12237 = x12237 + z12238 = x12238 + z12239 = x12239 + z12240 = x12240 + z12241 = x12241 + z12242 = x12242 + z12243 = x12243 + z12244 = x12244 + z12245 = x12245 + z12246 = x12246 + z12247 = x12247 + z12248 = x12248 + z12249 = x12249 + z12250 = x12250 + z12251 = x12251 + z12252 = x12252 + z12253 = x12253 + z12254 = x12254 + z12255 = x12255 + z12256 = x12256 + z12257 = x12257 + z12258 = x12258 + z12259 = x12259 + z12260 = x12260 + z12261 = x12261 + z12262 = x12262 + z12263 = x12263 + z12264 = x12264 + z12265 = x12265 + z12266 = x12266 + z12267 = x12267 + z12268 = x12268 + z12269 = x12269 + z12270 = x12270 + z12271 = x12271 + z12272 = x12272 + z12273 = x12273 + z12274 = x12274 + z12275 = x12275 + z12276 = x12276 + z12277 = x12277 + z12278 = x12278 + z12279 = x12279 + z12280 = x12280 + z12281 = x12281 + z12282 = x12282 + z12283 = x12283 + z12284 = x12284 + z12285 = x12285 + z12286 = x12286 + z12287 = x12287 + z12288 = x12288 + z12289 = x12289 + z12290 = x12290 + z12291 = x12291 + z12292 = x12292 + z12293 = x12293 + z12294 = x12294 + z12295 = x12295 + z12296 = x12296 + z12297 = x12297 + z12298 = x12298 + z12299 = x12299 + z12300 = x12300 + z12301 = x12301 + z12302 = x12302 + z12303 = x12303 + z12304 = x12304 + z12305 = x12305 + z12306 = x12306 + z12307 = x12307 + z12308 = x12308 + z12309 = x12309 + z12310 = x12310 + z12311 = x12311 + z12312 = x12312 + z12313 = x12313 + z12314 = x12314 + z12315 = x12315 + z12316 = x12316 + z12317 = x12317 + z12318 = x12318 + z12319 = x12319 + z12320 = x12320 + z12321 = x12321 + z12322 = x12322 + z12323 = x12323 + z12324 = x12324 + z12325 = x12325 + z12326 = x12326 + z12327 = x12327 + z12328 = x12328 + z12329 = x12329 + z12330 = x12330 + z12331 = x12331 + z12332 = x12332 + z12333 = x12333 + z12334 = x12334 + z12335 = x12335 + z12336 = x12336 + z12337 = x12337 + z12338 = x12338 + z12339 = x12339 + z12340 = x12340 + z12341 = x12341 + z12342 = x12342 + z12343 = x12343 + z12344 = x12344 + z12345 = x12345 + z12346 = x12346 + z12347 = x12347 + z12348 = x12348 + z12349 = x12349 + z12350 = x12350 + z12351 = x12351 + z12352 = x12352 + z12353 = x12353 + z12354 = x12354 + z12355 = x12355 + z12356 = x12356 + z12357 = x12357 + z12358 = x12358 + z12359 = x12359 + z12360 = x12360 + z12361 = x12361 + z12362 = x12362 + z12363 = x12363 + z12364 = x12364 + z12365 = x12365 + z12366 = x12366 + z12367 = x12367 + z12368 = x12368 + z12369 = x12369 + z12370 = x12370 + z12371 = x12371 + z12372 = x12372 + z12373 = x12373 + z12374 = x12374 + z12375 = x12375 + z12376 = x12376 + z12377 = x12377 + z12378 = x12378 + z12379 = x12379 + z12380 = x12380 + z12381 = x12381 + z12382 = x12382 + z12383 = x12383 + z12384 = x12384 + z12385 = x12385 + z12386 = x12386 + z12387 = x12387 + z12388 = x12388 + z12389 = x12389 + z12390 = x12390 + z12391 = x12391 + z12392 = x12392 + z12393 = x12393 + z12394 = x12394 + z12395 = x12395 + z12396 = x12396 + z12397 = x12397 + z12398 = x12398 + z12399 = x12399 + z12400 = x12400 + z12401 = x12401 + z12402 = x12402 + z12403 = x12403 + z12404 = x12404 + z12405 = x12405 + z12406 = x12406 + z12407 = x12407 + z12408 = x12408 + z12409 = x12409 + z12410 = x12410 + z12411 = x12411 + z12412 = x12412 + z12413 = x12413 + z12414 = x12414 + z12415 = x12415 + z12416 = x12416 + z12417 = x12417 + z12418 = x12418 + z12419 = x12419 + z12420 = x12420 + z12421 = x12421 + z12422 = x12422 + z12423 = x12423 + z12424 = x12424 + z12425 = x12425 + z12426 = x12426 + z12427 = x12427 + z12428 = x12428 + z12429 = x12429 + z12430 = x12430 + z12431 = x12431 + z12432 = x12432 + z12433 = x12433 + z12434 = x12434 + z12435 = x12435 + z12436 = x12436 + z12437 = x12437 + z12438 = x12438 + z12439 = x12439 + z12440 = x12440 + z12441 = x12441 + z12442 = x12442 + z12443 = x12443 + z12444 = x12444 + z12445 = x12445 + z12446 = x12446 + z12447 = x12447 + z12448 = x12448 + z12449 = x12449 + z12450 = x12450 + z12451 = x12451 + z12452 = x12452 + z12453 = x12453 + z12454 = x12454 + z12455 = x12455 + z12456 = x12456 + z12457 = x12457 + z12458 = x12458 + z12459 = x12459 + z12460 = x12460 + z12461 = x12461 + z12462 = x12462 + z12463 = x12463 + z12464 = x12464 + z12465 = x12465 + z12466 = x12466 + z12467 = x12467 + z12468 = x12468 + z12469 = x12469 + z12470 = x12470 + z12471 = x12471 + z12472 = x12472 + z12473 = x12473 + z12474 = x12474 + z12475 = x12475 + z12476 = x12476 + z12477 = x12477 + z12478 = x12478 + z12479 = x12479 + z12480 = x12480 + z12481 = x12481 + z12482 = x12482 + z12483 = x12483 + z12484 = x12484 + z12485 = x12485 + z12486 = x12486 + z12487 = x12487 + z12488 = x12488 + z12489 = x12489 + z12490 = x12490 + z12491 = x12491 + z12492 = x12492 + z12493 = x12493 + z12494 = x12494 + z12495 = x12495 + z12496 = x12496 + z12497 = x12497 + z12498 = x12498 + z12499 = x12499 + z12500 = x12500 + z12501 = x12501 + z12502 = x12502 + z12503 = x12503 + z12504 = x12504 + z12505 = x12505 + z12506 = x12506 + z12507 = x12507 + z12508 = x12508 + z12509 = x12509 + z12510 = x12510 + z12511 = x12511 + z12512 = x12512 + z12513 = x12513 + z12514 = x12514 + z12515 = x12515 + z12516 = x12516 + z12517 = x12517 + z12518 = x12518 + z12519 = x12519 + z12520 = x12520 + z12521 = x12521 + z12522 = x12522 + z12523 = x12523 + z12524 = x12524 + z12525 = x12525 + z12526 = x12526 + z12527 = x12527 + z12528 = x12528 + z12529 = x12529 + z12530 = x12530 + z12531 = x12531 + z12532 = x12532 + z12533 = x12533 + z12534 = x12534 + z12535 = x12535 + z12536 = x12536 + z12537 = x12537 + z12538 = x12538 + z12539 = x12539 + z12540 = x12540 + z12541 = x12541 + z12542 = x12542 + z12543 = x12543 + z12544 = x12544 + z12545 = x12545 + z12546 = x12546 + z12547 = x12547 + z12548 = x12548 + z12549 = x12549 + z12550 = x12550 + z12551 = x12551 + z12552 = x12552 + z12553 = x12553 + z12554 = x12554 + z12555 = x12555 + z12556 = x12556 + z12557 = x12557 + z12558 = x12558 + z12559 = x12559 + z12560 = x12560 + z12561 = x12561 + z12562 = x12562 + z12563 = x12563 + z12564 = x12564 + z12565 = x12565 + z12566 = x12566 + z12567 = x12567 + z12568 = x12568 + z12569 = x12569 + z12570 = x12570 + z12571 = x12571 + z12572 = x12572 + z12573 = x12573 + z12574 = x12574 + z12575 = x12575 + z12576 = x12576 + z12577 = x12577 + z12578 = x12578 + z12579 = x12579 + z12580 = x12580 + z12581 = x12581 + z12582 = x12582 + z12583 = x12583 + z12584 = x12584 + z12585 = x12585 + z12586 = x12586 + z12587 = x12587 + z12588 = x12588 + z12589 = x12589 + z12590 = x12590 + z12591 = x12591 + z12592 = x12592 + z12593 = x12593 + z12594 = x12594 + z12595 = x12595 + z12596 = x12596 + z12597 = x12597 + z12598 = x12598 + z12599 = x12599 + z12600 = x12600 + z12601 = x12601 + z12602 = x12602 + z12603 = x12603 + z12604 = x12604 + z12605 = x12605 + z12606 = x12606 + z12607 = x12607 + z12608 = x12608 + z12609 = x12609 + z12610 = x12610 + z12611 = x12611 + z12612 = x12612 + z12613 = x12613 + z12614 = x12614 + z12615 = x12615 + z12616 = x12616 + z12617 = x12617 + z12618 = x12618 + z12619 = x12619 + z12620 = x12620 + z12621 = x12621 + z12622 = x12622 + z12623 = x12623 + z12624 = x12624 + z12625 = x12625 + z12626 = x12626 + z12627 = x12627 + z12628 = x12628 + z12629 = x12629 + z12630 = x12630 + z12631 = x12631 + z12632 = x12632 + z12633 = x12633 + z12634 = x12634 + z12635 = x12635 + z12636 = x12636 + z12637 = x12637 + z12638 = x12638 + z12639 = x12639 + z12640 = x12640 + z12641 = x12641 + z12642 = x12642 + z12643 = x12643 + z12644 = x12644 + z12645 = x12645 + z12646 = x12646 + z12647 = x12647 + z12648 = x12648 + z12649 = x12649 + z12650 = x12650 + z12651 = x12651 + z12652 = x12652 + z12653 = x12653 + z12654 = x12654 + z12655 = x12655 + z12656 = x12656 + z12657 = x12657 + z12658 = x12658 + z12659 = x12659 + z12660 = x12660 + z12661 = x12661 + z12662 = x12662 + z12663 = x12663 + z12664 = x12664 + z12665 = x12665 + z12666 = x12666 + z12667 = x12667 + z12668 = x12668 + z12669 = x12669 + z12670 = x12670 + z12671 = x12671 + z12672 = x12672 + z12673 = x12673 + z12674 = x12674 + z12675 = x12675 + z12676 = x12676 + z12677 = x12677 + z12678 = x12678 + z12679 = x12679 + z12680 = x12680 + z12681 = x12681 + z12682 = x12682 + z12683 = x12683 + z12684 = x12684 + z12685 = x12685 + z12686 = x12686 + z12687 = x12687 + z12688 = x12688 + z12689 = x12689 + z12690 = x12690 + z12691 = x12691 + z12692 = x12692 + z12693 = x12693 + z12694 = x12694 + z12695 = x12695 + z12696 = x12696 + z12697 = x12697 + z12698 = x12698 + z12699 = x12699 + z12700 = x12700 + z12701 = x12701 + z12702 = x12702 + z12703 = x12703 + z12704 = x12704 + z12705 = x12705 + z12706 = x12706 + z12707 = x12707 + z12708 = x12708 + z12709 = x12709 + z12710 = x12710 + z12711 = x12711 + z12712 = x12712 + z12713 = x12713 + z12714 = x12714 + z12715 = x12715 + z12716 = x12716 + z12717 = x12717 + z12718 = x12718 + z12719 = x12719 + z12720 = x12720 + z12721 = x12721 + z12722 = x12722 + z12723 = x12723 + z12724 = x12724 + z12725 = x12725 + z12726 = x12726 + z12727 = x12727 + z12728 = x12728 + z12729 = x12729 + z12730 = x12730 + z12731 = x12731 + z12732 = x12732 + z12733 = x12733 + z12734 = x12734 + z12735 = x12735 + z12736 = x12736 + z12737 = x12737 + z12738 = x12738 + z12739 = x12739 + z12740 = x12740 + z12741 = x12741 + z12742 = x12742 + z12743 = x12743 + z12744 = x12744 + z12745 = x12745 + z12746 = x12746 + z12747 = x12747 + z12748 = x12748 + z12749 = x12749 + z12750 = x12750 + z12751 = x12751 + z12752 = x12752 + z12753 = x12753 + z12754 = x12754 + z12755 = x12755 + z12756 = x12756 + z12757 = x12757 + z12758 = x12758 + z12759 = x12759 + z12760 = x12760 + z12761 = x12761 + z12762 = x12762 + z12763 = x12763 + z12764 = x12764 + z12765 = x12765 + z12766 = x12766 + z12767 = x12767 + z12768 = x12768 + z12769 = x12769 + z12770 = x12770 + z12771 = x12771 + z12772 = x12772 + z12773 = x12773 + z12774 = x12774 + z12775 = x12775 + z12776 = x12776 + z12777 = x12777 + z12778 = x12778 + z12779 = x12779 + z12780 = x12780 + z12781 = x12781 + z12782 = x12782 + z12783 = x12783 + z12784 = x12784 + z12785 = x12785 + z12786 = x12786 + z12787 = x12787 + z12788 = x12788 + z12789 = x12789 + z12790 = x12790 + z12791 = x12791 + z12792 = x12792 + z12793 = x12793 + z12794 = x12794 + z12795 = x12795 + z12796 = x12796 + z12797 = x12797 + z12798 = x12798 + z12799 = x12799 + z12800 = x12800 + z12801 = x12801 + z12802 = x12802 + z12803 = x12803 + z12804 = x12804 + z12805 = x12805 + z12806 = x12806 + z12807 = x12807 + z12808 = x12808 + z12809 = x12809 + z12810 = x12810 + z12811 = x12811 + z12812 = x12812 + z12813 = x12813 + z12814 = x12814 + z12815 = x12815 + z12816 = x12816 + z12817 = x12817 + z12818 = x12818 + z12819 = x12819 + z12820 = x12820 + z12821 = x12821 + z12822 = x12822 + z12823 = x12823 + z12824 = x12824 + z12825 = x12825 + z12826 = x12826 + z12827 = x12827 + z12828 = x12828 + z12829 = x12829 + z12830 = x12830 + z12831 = x12831 + z12832 = x12832 + z12833 = x12833 + z12834 = x12834 + z12835 = x12835 + z12836 = x12836 + z12837 = x12837 + z12838 = x12838 + z12839 = x12839 + z12840 = x12840 + z12841 = x12841 + z12842 = x12842 + z12843 = x12843 + z12844 = x12844 + z12845 = x12845 + z12846 = x12846 + z12847 = x12847 + z12848 = x12848 + z12849 = x12849 + z12850 = x12850 + z12851 = x12851 + z12852 = x12852 + z12853 = x12853 + z12854 = x12854 + z12855 = x12855 + z12856 = x12856 + z12857 = x12857 + z12858 = x12858 + z12859 = x12859 + z12860 = x12860 + z12861 = x12861 + z12862 = x12862 + z12863 = x12863 + z12864 = x12864 + z12865 = x12865 + z12866 = x12866 + z12867 = x12867 + z12868 = x12868 + z12869 = x12869 + z12870 = x12870 + z12871 = x12871 + z12872 = x12872 + z12873 = x12873 + z12874 = x12874 + z12875 = x12875 + z12876 = x12876 + z12877 = x12877 + z12878 = x12878 + z12879 = x12879 + z12880 = x12880 + z12881 = x12881 + z12882 = x12882 + z12883 = x12883 + z12884 = x12884 + z12885 = x12885 + z12886 = x12886 + z12887 = x12887 + z12888 = x12888 + z12889 = x12889 + z12890 = x12890 + z12891 = x12891 + z12892 = x12892 + z12893 = x12893 + z12894 = x12894 + z12895 = x12895 + z12896 = x12896 + z12897 = x12897 + z12898 = x12898 + z12899 = x12899 + z12900 = x12900 + z12901 = x12901 + z12902 = x12902 + z12903 = x12903 + z12904 = x12904 + z12905 = x12905 + z12906 = x12906 + z12907 = x12907 + z12908 = x12908 + z12909 = x12909 + z12910 = x12910 + z12911 = x12911 + z12912 = x12912 + z12913 = x12913 + z12914 = x12914 + z12915 = x12915 + z12916 = x12916 + z12917 = x12917 + z12918 = x12918 + z12919 = x12919 + z12920 = x12920 + z12921 = x12921 + z12922 = x12922 + z12923 = x12923 + z12924 = x12924 + z12925 = x12925 + z12926 = x12926 + z12927 = x12927 + z12928 = x12928 + z12929 = x12929 + z12930 = x12930 + z12931 = x12931 + z12932 = x12932 + z12933 = x12933 + z12934 = x12934 + z12935 = x12935 + z12936 = x12936 + z12937 = x12937 + z12938 = x12938 + z12939 = x12939 + z12940 = x12940 + z12941 = x12941 + z12942 = x12942 + z12943 = x12943 + z12944 = x12944 + z12945 = x12945 + z12946 = x12946 + z12947 = x12947 + z12948 = x12948 + z12949 = x12949 + z12950 = x12950 + z12951 = x12951 + z12952 = x12952 + z12953 = x12953 + z12954 = x12954 + z12955 = x12955 + z12956 = x12956 + z12957 = x12957 + z12958 = x12958 + z12959 = x12959 + z12960 = x12960 + z12961 = x12961 + z12962 = x12962 + z12963 = x12963 + z12964 = x12964 + z12965 = x12965 + z12966 = x12966 + z12967 = x12967 + z12968 = x12968 + z12969 = x12969 + z12970 = x12970 + z12971 = x12971 + z12972 = x12972 + z12973 = x12973 + z12974 = x12974 + z12975 = x12975 + z12976 = x12976 + z12977 = x12977 + z12978 = x12978 + z12979 = x12979 + z12980 = x12980 + z12981 = x12981 + z12982 = x12982 + z12983 = x12983 + z12984 = x12984 + z12985 = x12985 + z12986 = x12986 + z12987 = x12987 + z12988 = x12988 + z12989 = x12989 + z12990 = x12990 + z12991 = x12991 + z12992 = x12992 + z12993 = x12993 + z12994 = x12994 + z12995 = x12995 + z12996 = x12996 + z12997 = x12997 + z12998 = x12998 + z12999 = x12999 + z13000 = x13000 + z13001 = x13001 + z13002 = x13002 + z13003 = x13003 + z13004 = x13004 + z13005 = x13005 + z13006 = x13006 + z13007 = x13007 + z13008 = x13008 + z13009 = x13009 + z13010 = x13010 + z13011 = x13011 + z13012 = x13012 + z13013 = x13013 + z13014 = x13014 + z13015 = x13015 + z13016 = x13016 + z13017 = x13017 + z13018 = x13018 + z13019 = x13019 + z13020 = x13020 + z13021 = x13021 + z13022 = x13022 + z13023 = x13023 + z13024 = x13024 + z13025 = x13025 + z13026 = x13026 + z13027 = x13027 + z13028 = x13028 + z13029 = x13029 + z13030 = x13030 + z13031 = x13031 + z13032 = x13032 + z13033 = x13033 + z13034 = x13034 + z13035 = x13035 + z13036 = x13036 + z13037 = x13037 + z13038 = x13038 + z13039 = x13039 + z13040 = x13040 + z13041 = x13041 + z13042 = x13042 + z13043 = x13043 + z13044 = x13044 + z13045 = x13045 + z13046 = x13046 + z13047 = x13047 + z13048 = x13048 + z13049 = x13049 + z13050 = x13050 + z13051 = x13051 + z13052 = x13052 + z13053 = x13053 + z13054 = x13054 + z13055 = x13055 + z13056 = x13056 + z13057 = x13057 + z13058 = x13058 + z13059 = x13059 + z13060 = x13060 + z13061 = x13061 + z13062 = x13062 + z13063 = x13063 + z13064 = x13064 + z13065 = x13065 + z13066 = x13066 + z13067 = x13067 + z13068 = x13068 + z13069 = x13069 + z13070 = x13070 + z13071 = x13071 + z13072 = x13072 + z13073 = x13073 + z13074 = x13074 + z13075 = x13075 + z13076 = x13076 + z13077 = x13077 + z13078 = x13078 + z13079 = x13079 + z13080 = x13080 + z13081 = x13081 + z13082 = x13082 + z13083 = x13083 + z13084 = x13084 + z13085 = x13085 + z13086 = x13086 + z13087 = x13087 + z13088 = x13088 + z13089 = x13089 + z13090 = x13090 + z13091 = x13091 + z13092 = x13092 + z13093 = x13093 + z13094 = x13094 + z13095 = x13095 + z13096 = x13096 + z13097 = x13097 + z13098 = x13098 + z13099 = x13099 + z13100 = x13100 + z13101 = x13101 + z13102 = x13102 + z13103 = x13103 + z13104 = x13104 + z13105 = x13105 + z13106 = x13106 + z13107 = x13107 + z13108 = x13108 + z13109 = x13109 + z13110 = x13110 + z13111 = x13111 + z13112 = x13112 + z13113 = x13113 + z13114 = x13114 + z13115 = x13115 + z13116 = x13116 + z13117 = x13117 + z13118 = x13118 + z13119 = x13119 + z13120 = x13120 + z13121 = x13121 + z13122 = x13122 + z13123 = x13123 + z13124 = x13124 + z13125 = x13125 + z13126 = x13126 + z13127 = x13127 + z13128 = x13128 + z13129 = x13129 + z13130 = x13130 + z13131 = x13131 + z13132 = x13132 + z13133 = x13133 + z13134 = x13134 + z13135 = x13135 + z13136 = x13136 + z13137 = x13137 + z13138 = x13138 + z13139 = x13139 + z13140 = x13140 + z13141 = x13141 + z13142 = x13142 + z13143 = x13143 + z13144 = x13144 + z13145 = x13145 + z13146 = x13146 + z13147 = x13147 + z13148 = x13148 + z13149 = x13149 + z13150 = x13150 + z13151 = x13151 + z13152 = x13152 + z13153 = x13153 + z13154 = x13154 + z13155 = x13155 + z13156 = x13156 + z13157 = x13157 + z13158 = x13158 + z13159 = x13159 + z13160 = x13160 + z13161 = x13161 + z13162 = x13162 + z13163 = x13163 + z13164 = x13164 + z13165 = x13165 + z13166 = x13166 + z13167 = x13167 + z13168 = x13168 + z13169 = x13169 + z13170 = x13170 + z13171 = x13171 + z13172 = x13172 + z13173 = x13173 + z13174 = x13174 + z13175 = x13175 + z13176 = x13176 + z13177 = x13177 + z13178 = x13178 + z13179 = x13179 + z13180 = x13180 + z13181 = x13181 + z13182 = x13182 + z13183 = x13183 + z13184 = x13184 + z13185 = x13185 + z13186 = x13186 + z13187 = x13187 + z13188 = x13188 + z13189 = x13189 + z13190 = x13190 + z13191 = x13191 + z13192 = x13192 + z13193 = x13193 + z13194 = x13194 + z13195 = x13195 + z13196 = x13196 + z13197 = x13197 + z13198 = x13198 + z13199 = x13199 + z13200 = x13200 + z13201 = x13201 + z13202 = x13202 + z13203 = x13203 + z13204 = x13204 + z13205 = x13205 + z13206 = x13206 + z13207 = x13207 + z13208 = x13208 + z13209 = x13209 + z13210 = x13210 + z13211 = x13211 + z13212 = x13212 + z13213 = x13213 + z13214 = x13214 + z13215 = x13215 + z13216 = x13216 + z13217 = x13217 + z13218 = x13218 + z13219 = x13219 + z13220 = x13220 + z13221 = x13221 + z13222 = x13222 + z13223 = x13223 + z13224 = x13224 + z13225 = x13225 + z13226 = x13226 + z13227 = x13227 + z13228 = x13228 + z13229 = x13229 + z13230 = x13230 + z13231 = x13231 + z13232 = x13232 + z13233 = x13233 + z13234 = x13234 + z13235 = x13235 + z13236 = x13236 + z13237 = x13237 + z13238 = x13238 + z13239 = x13239 + z13240 = x13240 + z13241 = x13241 + z13242 = x13242 + z13243 = x13243 + z13244 = x13244 + z13245 = x13245 + z13246 = x13246 + z13247 = x13247 + z13248 = x13248 + z13249 = x13249 + z13250 = x13250 + z13251 = x13251 + z13252 = x13252 + z13253 = x13253 + z13254 = x13254 + z13255 = x13255 + z13256 = x13256 + z13257 = x13257 + z13258 = x13258 + z13259 = x13259 + z13260 = x13260 + z13261 = x13261 + z13262 = x13262 + z13263 = x13263 + z13264 = x13264 + z13265 = x13265 + z13266 = x13266 + z13267 = x13267 + z13268 = x13268 + z13269 = x13269 + z13270 = x13270 + z13271 = x13271 + z13272 = x13272 + z13273 = x13273 + z13274 = x13274 + z13275 = x13275 + z13276 = x13276 + z13277 = x13277 + z13278 = x13278 + z13279 = x13279 + z13280 = x13280 + z13281 = x13281 + z13282 = x13282 + z13283 = x13283 + z13284 = x13284 + z13285 = x13285 + z13286 = x13286 + z13287 = x13287 + z13288 = x13288 + z13289 = x13289 + z13290 = x13290 + z13291 = x13291 + z13292 = x13292 + z13293 = x13293 + z13294 = x13294 + z13295 = x13295 + z13296 = x13296 + z13297 = x13297 + z13298 = x13298 + z13299 = x13299 + z13300 = x13300 + z13301 = x13301 + z13302 = x13302 + z13303 = x13303 + z13304 = x13304 + z13305 = x13305 + z13306 = x13306 + z13307 = x13307 + z13308 = x13308 + z13309 = x13309 + z13310 = x13310 + z13311 = x13311 + z13312 = x13312 + z13313 = x13313 + z13314 = x13314 + z13315 = x13315 + z13316 = x13316 + z13317 = x13317 + z13318 = x13318 + z13319 = x13319 + z13320 = x13320 + z13321 = x13321 + z13322 = x13322 + z13323 = x13323 + z13324 = x13324 + z13325 = x13325 + z13326 = x13326 + z13327 = x13327 + z13328 = x13328 + z13329 = x13329 + z13330 = x13330 + z13331 = x13331 + z13332 = x13332 + z13333 = x13333 + z13334 = x13334 + z13335 = x13335 + z13336 = x13336 + z13337 = x13337 + z13338 = x13338 + z13339 = x13339 + z13340 = x13340 + z13341 = x13341 + z13342 = x13342 + z13343 = x13343 + z13344 = x13344 + z13345 = x13345 + z13346 = x13346 + z13347 = x13347 + z13348 = x13348 + z13349 = x13349 + z13350 = x13350 + z13351 = x13351 + z13352 = x13352 + z13353 = x13353 + z13354 = x13354 + z13355 = x13355 + z13356 = x13356 + z13357 = x13357 + z13358 = x13358 + z13359 = x13359 + z13360 = x13360 + z13361 = x13361 + z13362 = x13362 + z13363 = x13363 + z13364 = x13364 + z13365 = x13365 + z13366 = x13366 + z13367 = x13367 + z13368 = x13368 + z13369 = x13369 + z13370 = x13370 + z13371 = x13371 + z13372 = x13372 + z13373 = x13373 + z13374 = x13374 + z13375 = x13375 + z13376 = x13376 + z13377 = x13377 + z13378 = x13378 + z13379 = x13379 + z13380 = x13380 + z13381 = x13381 + z13382 = x13382 + z13383 = x13383 + z13384 = x13384 + z13385 = x13385 + z13386 = x13386 + z13387 = x13387 + z13388 = x13388 + z13389 = x13389 + z13390 = x13390 + z13391 = x13391 + z13392 = x13392 + z13393 = x13393 + z13394 = x13394 + z13395 = x13395 + z13396 = x13396 + z13397 = x13397 + z13398 = x13398 + z13399 = x13399 + z13400 = x13400 + z13401 = x13401 + z13402 = x13402 + z13403 = x13403 + z13404 = x13404 + z13405 = x13405 + z13406 = x13406 + z13407 = x13407 + z13408 = x13408 + z13409 = x13409 + z13410 = x13410 + z13411 = x13411 + z13412 = x13412 + z13413 = x13413 + z13414 = x13414 + z13415 = x13415 + z13416 = x13416 + z13417 = x13417 + z13418 = x13418 + z13419 = x13419 + z13420 = x13420 + z13421 = x13421 + z13422 = x13422 + z13423 = x13423 + z13424 = x13424 + z13425 = x13425 + z13426 = x13426 + z13427 = x13427 + z13428 = x13428 + z13429 = x13429 + z13430 = x13430 + z13431 = x13431 + z13432 = x13432 + z13433 = x13433 + z13434 = x13434 + z13435 = x13435 + z13436 = x13436 + z13437 = x13437 + z13438 = x13438 + z13439 = x13439 + z13440 = x13440 + z13441 = x13441 + z13442 = x13442 + z13443 = x13443 + z13444 = x13444 + z13445 = x13445 + z13446 = x13446 + z13447 = x13447 + z13448 = x13448 + z13449 = x13449 + z13450 = x13450 + z13451 = x13451 + z13452 = x13452 + z13453 = x13453 + z13454 = x13454 + z13455 = x13455 + z13456 = x13456 + z13457 = x13457 + z13458 = x13458 + z13459 = x13459 + z13460 = x13460 + z13461 = x13461 + z13462 = x13462 + z13463 = x13463 + z13464 = x13464 + z13465 = x13465 + z13466 = x13466 + z13467 = x13467 + z13468 = x13468 + z13469 = x13469 + z13470 = x13470 + z13471 = x13471 + z13472 = x13472 + z13473 = x13473 + z13474 = x13474 + z13475 = x13475 + z13476 = x13476 + z13477 = x13477 + z13478 = x13478 + z13479 = x13479 + z13480 = x13480 + z13481 = x13481 + z13482 = x13482 + z13483 = x13483 + z13484 = x13484 + z13485 = x13485 + z13486 = x13486 + z13487 = x13487 + z13488 = x13488 + z13489 = x13489 + z13490 = x13490 + z13491 = x13491 + z13492 = x13492 + z13493 = x13493 + z13494 = x13494 + z13495 = x13495 + z13496 = x13496 + z13497 = x13497 + z13498 = x13498 + z13499 = x13499 + z13500 = x13500 + z13501 = x13501 + z13502 = x13502 + z13503 = x13503 + z13504 = x13504 + z13505 = x13505 + z13506 = x13506 + z13507 = x13507 + z13508 = x13508 + z13509 = x13509 + z13510 = x13510 + z13511 = x13511 + z13512 = x13512 + z13513 = x13513 + z13514 = x13514 + z13515 = x13515 + z13516 = x13516 + z13517 = x13517 + z13518 = x13518 + z13519 = x13519 + z13520 = x13520 + z13521 = x13521 + z13522 = x13522 + z13523 = x13523 + z13524 = x13524 + z13525 = x13525 + z13526 = x13526 + z13527 = x13527 + z13528 = x13528 + z13529 = x13529 + z13530 = x13530 + z13531 = x13531 + z13532 = x13532 + z13533 = x13533 + z13534 = x13534 + z13535 = x13535 + z13536 = x13536 + z13537 = x13537 + z13538 = x13538 + z13539 = x13539 + z13540 = x13540 + z13541 = x13541 + z13542 = x13542 + z13543 = x13543 + z13544 = x13544 + z13545 = x13545 + z13546 = x13546 + z13547 = x13547 + z13548 = x13548 + z13549 = x13549 + z13550 = x13550 + z13551 = x13551 + z13552 = x13552 + z13553 = x13553 + z13554 = x13554 + z13555 = x13555 + z13556 = x13556 + z13557 = x13557 + z13558 = x13558 + z13559 = x13559 + z13560 = x13560 + z13561 = x13561 + z13562 = x13562 + z13563 = x13563 + z13564 = x13564 + z13565 = x13565 + z13566 = x13566 + z13567 = x13567 + z13568 = x13568 + z13569 = x13569 + z13570 = x13570 + z13571 = x13571 + z13572 = x13572 + z13573 = x13573 + z13574 = x13574 + z13575 = x13575 + z13576 = x13576 + z13577 = x13577 + z13578 = x13578 + z13579 = x13579 + z13580 = x13580 + z13581 = x13581 + z13582 = x13582 + z13583 = x13583 + z13584 = x13584 + z13585 = x13585 + z13586 = x13586 + z13587 = x13587 + z13588 = x13588 + z13589 = x13589 + z13590 = x13590 + z13591 = x13591 + z13592 = x13592 + z13593 = x13593 + z13594 = x13594 + z13595 = x13595 + z13596 = x13596 + z13597 = x13597 + z13598 = x13598 + z13599 = x13599 + z13600 = x13600 + z13601 = x13601 + z13602 = x13602 + z13603 = x13603 + z13604 = x13604 + z13605 = x13605 + z13606 = x13606 + z13607 = x13607 + z13608 = x13608 + z13609 = x13609 + z13610 = x13610 + z13611 = x13611 + z13612 = x13612 + z13613 = x13613 + z13614 = x13614 + z13615 = x13615 + z13616 = x13616 + z13617 = x13617 + z13618 = x13618 + z13619 = x13619 + z13620 = x13620 + z13621 = x13621 + z13622 = x13622 + z13623 = x13623 + z13624 = x13624 + z13625 = x13625 + z13626 = x13626 + z13627 = x13627 + z13628 = x13628 + z13629 = x13629 + z13630 = x13630 + z13631 = x13631 + z13632 = x13632 + z13633 = x13633 + z13634 = x13634 + z13635 = x13635 + z13636 = x13636 + z13637 = x13637 + z13638 = x13638 + z13639 = x13639 + z13640 = x13640 + z13641 = x13641 + z13642 = x13642 + z13643 = x13643 + z13644 = x13644 + z13645 = x13645 + z13646 = x13646 + z13647 = x13647 + z13648 = x13648 + z13649 = x13649 + z13650 = x13650 + z13651 = x13651 + z13652 = x13652 + z13653 = x13653 + z13654 = x13654 + z13655 = x13655 + z13656 = x13656 + z13657 = x13657 + z13658 = x13658 + z13659 = x13659 + z13660 = x13660 + z13661 = x13661 + z13662 = x13662 + z13663 = x13663 + z13664 = x13664 + z13665 = x13665 + z13666 = x13666 + z13667 = x13667 + z13668 = x13668 + z13669 = x13669 + z13670 = x13670 + z13671 = x13671 + z13672 = x13672 + z13673 = x13673 + z13674 = x13674 + z13675 = x13675 + z13676 = x13676 + z13677 = x13677 + z13678 = x13678 + z13679 = x13679 + z13680 = x13680 + z13681 = x13681 + z13682 = x13682 + z13683 = x13683 + z13684 = x13684 + z13685 = x13685 + z13686 = x13686 + z13687 = x13687 + z13688 = x13688 + z13689 = x13689 + z13690 = x13690 + z13691 = x13691 + z13692 = x13692 + z13693 = x13693 + z13694 = x13694 + z13695 = x13695 + z13696 = x13696 + z13697 = x13697 + z13698 = x13698 + z13699 = x13699 + z13700 = x13700 + z13701 = x13701 + z13702 = x13702 + z13703 = x13703 + z13704 = x13704 + z13705 = x13705 + z13706 = x13706 + z13707 = x13707 + z13708 = x13708 + z13709 = x13709 + z13710 = x13710 + z13711 = x13711 + z13712 = x13712 + z13713 = x13713 + z13714 = x13714 + z13715 = x13715 + z13716 = x13716 + z13717 = x13717 + z13718 = x13718 + z13719 = x13719 + z13720 = x13720 + z13721 = x13721 + z13722 = x13722 + z13723 = x13723 + z13724 = x13724 + z13725 = x13725 + z13726 = x13726 + z13727 = x13727 + z13728 = x13728 + z13729 = x13729 + z13730 = x13730 + z13731 = x13731 + z13732 = x13732 + z13733 = x13733 + z13734 = x13734 + z13735 = x13735 + z13736 = x13736 + z13737 = x13737 + z13738 = x13738 + z13739 = x13739 + z13740 = x13740 + z13741 = x13741 + z13742 = x13742 + z13743 = x13743 + z13744 = x13744 + z13745 = x13745 + z13746 = x13746 + z13747 = x13747 + z13748 = x13748 + z13749 = x13749 + z13750 = x13750 + z13751 = x13751 + z13752 = x13752 + z13753 = x13753 + z13754 = x13754 + z13755 = x13755 + z13756 = x13756 + z13757 = x13757 + z13758 = x13758 + z13759 = x13759 + z13760 = x13760 + z13761 = x13761 + z13762 = x13762 + z13763 = x13763 + z13764 = x13764 + z13765 = x13765 + z13766 = x13766 + z13767 = x13767 + z13768 = x13768 + z13769 = x13769 + z13770 = x13770 + z13771 = x13771 + z13772 = x13772 + z13773 = x13773 + z13774 = x13774 + z13775 = x13775 + z13776 = x13776 + z13777 = x13777 + z13778 = x13778 + z13779 = x13779 + z13780 = x13780 + z13781 = x13781 + z13782 = x13782 + z13783 = x13783 + z13784 = x13784 + z13785 = x13785 + z13786 = x13786 + z13787 = x13787 + z13788 = x13788 + z13789 = x13789 + z13790 = x13790 + z13791 = x13791 + z13792 = x13792 + z13793 = x13793 + z13794 = x13794 + z13795 = x13795 + z13796 = x13796 + z13797 = x13797 + z13798 = x13798 + z13799 = x13799 + z13800 = x13800 + z13801 = x13801 + z13802 = x13802 + z13803 = x13803 + z13804 = x13804 + z13805 = x13805 + z13806 = x13806 + z13807 = x13807 + z13808 = x13808 + z13809 = x13809 + z13810 = x13810 + z13811 = x13811 + z13812 = x13812 + z13813 = x13813 + z13814 = x13814 + z13815 = x13815 + z13816 = x13816 + z13817 = x13817 + z13818 = x13818 + z13819 = x13819 + z13820 = x13820 + z13821 = x13821 + z13822 = x13822 + z13823 = x13823 + z13824 = x13824 + z13825 = x13825 + z13826 = x13826 + z13827 = x13827 + z13828 = x13828 + z13829 = x13829 + z13830 = x13830 + z13831 = x13831 + z13832 = x13832 + z13833 = x13833 + z13834 = x13834 + z13835 = x13835 + z13836 = x13836 + z13837 = x13837 + z13838 = x13838 + z13839 = x13839 + z13840 = x13840 + z13841 = x13841 + z13842 = x13842 + z13843 = x13843 + z13844 = x13844 + z13845 = x13845 + z13846 = x13846 + z13847 = x13847 + z13848 = x13848 + z13849 = x13849 + z13850 = x13850 + z13851 = x13851 + z13852 = x13852 + z13853 = x13853 + z13854 = x13854 + z13855 = x13855 + z13856 = x13856 + z13857 = x13857 + z13858 = x13858 + z13859 = x13859 + z13860 = x13860 + z13861 = x13861 + z13862 = x13862 + z13863 = x13863 + z13864 = x13864 + z13865 = x13865 + z13866 = x13866 + z13867 = x13867 + z13868 = x13868 + z13869 = x13869 + z13870 = x13870 + z13871 = x13871 + z13872 = x13872 + z13873 = x13873 + z13874 = x13874 + z13875 = x13875 + z13876 = x13876 + z13877 = x13877 + z13878 = x13878 + z13879 = x13879 + z13880 = x13880 + z13881 = x13881 + z13882 = x13882 + z13883 = x13883 + z13884 = x13884 + z13885 = x13885 + z13886 = x13886 + z13887 = x13887 + z13888 = x13888 + z13889 = x13889 + z13890 = x13890 + z13891 = x13891 + z13892 = x13892 + z13893 = x13893 + z13894 = x13894 + z13895 = x13895 + z13896 = x13896 + z13897 = x13897 + z13898 = x13898 + z13899 = x13899 + z13900 = x13900 + z13901 = x13901 + z13902 = x13902 + z13903 = x13903 + z13904 = x13904 + z13905 = x13905 + z13906 = x13906 + z13907 = x13907 + z13908 = x13908 + z13909 = x13909 + z13910 = x13910 + z13911 = x13911 + z13912 = x13912 + z13913 = x13913 + z13914 = x13914 + z13915 = x13915 + z13916 = x13916 + z13917 = x13917 + z13918 = x13918 + z13919 = x13919 + z13920 = x13920 + z13921 = x13921 + z13922 = x13922 + z13923 = x13923 + z13924 = x13924 + z13925 = x13925 + z13926 = x13926 + z13927 = x13927 + z13928 = x13928 + z13929 = x13929 + z13930 = x13930 + z13931 = x13931 + z13932 = x13932 + z13933 = x13933 + z13934 = x13934 + z13935 = x13935 + z13936 = x13936 + z13937 = x13937 + z13938 = x13938 + z13939 = x13939 + z13940 = x13940 + z13941 = x13941 + z13942 = x13942 + z13943 = x13943 + z13944 = x13944 + z13945 = x13945 + z13946 = x13946 + z13947 = x13947 + z13948 = x13948 + z13949 = x13949 + z13950 = x13950 + z13951 = x13951 + z13952 = x13952 + z13953 = x13953 + z13954 = x13954 + z13955 = x13955 + z13956 = x13956 + z13957 = x13957 + z13958 = x13958 + z13959 = x13959 + z13960 = x13960 + z13961 = x13961 + z13962 = x13962 + z13963 = x13963 + z13964 = x13964 + z13965 = x13965 + z13966 = x13966 + z13967 = x13967 + z13968 = x13968 + z13969 = x13969 + z13970 = x13970 + z13971 = x13971 + z13972 = x13972 + z13973 = x13973 + z13974 = x13974 + z13975 = x13975 + z13976 = x13976 + z13977 = x13977 + z13978 = x13978 + z13979 = x13979 + z13980 = x13980 + z13981 = x13981 + z13982 = x13982 + z13983 = x13983 + z13984 = x13984 + z13985 = x13985 + z13986 = x13986 + z13987 = x13987 + z13988 = x13988 + z13989 = x13989 + z13990 = x13990 + z13991 = x13991 + z13992 = x13992 + z13993 = x13993 + z13994 = x13994 + z13995 = x13995 + z13996 = x13996 + z13997 = x13997 + z13998 = x13998 + z13999 = x13999 + z14000 = x14000 + z14001 = x14001 + z14002 = x14002 + z14003 = x14003 + z14004 = x14004 + z14005 = x14005 + z14006 = x14006 + z14007 = x14007 + z14008 = x14008 + z14009 = x14009 + z14010 = x14010 + z14011 = x14011 + z14012 = x14012 + z14013 = x14013 + z14014 = x14014 + z14015 = x14015 + z14016 = x14016 + z14017 = x14017 + z14018 = x14018 + z14019 = x14019 + z14020 = x14020 + z14021 = x14021 + z14022 = x14022 + z14023 = x14023 + z14024 = x14024 + z14025 = x14025 + z14026 = x14026 + z14027 = x14027 + z14028 = x14028 + z14029 = x14029 + z14030 = x14030 + z14031 = x14031 + z14032 = x14032 + z14033 = x14033 + z14034 = x14034 + z14035 = x14035 + z14036 = x14036 + z14037 = x14037 + z14038 = x14038 + z14039 = x14039 + z14040 = x14040 + z14041 = x14041 + z14042 = x14042 + z14043 = x14043 + z14044 = x14044 + z14045 = x14045 + z14046 = x14046 + z14047 = x14047 + z14048 = x14048 + z14049 = x14049 + z14050 = x14050 + z14051 = x14051 + z14052 = x14052 + z14053 = x14053 + z14054 = x14054 + z14055 = x14055 + z14056 = x14056 + z14057 = x14057 + z14058 = x14058 + z14059 = x14059 + z14060 = x14060 + z14061 = x14061 + z14062 = x14062 + z14063 = x14063 + z14064 = x14064 + z14065 = x14065 + z14066 = x14066 + z14067 = x14067 + z14068 = x14068 + z14069 = x14069 + z14070 = x14070 + z14071 = x14071 + z14072 = x14072 + z14073 = x14073 + z14074 = x14074 + z14075 = x14075 + z14076 = x14076 + z14077 = x14077 + z14078 = x14078 + z14079 = x14079 + z14080 = x14080 + z14081 = x14081 + z14082 = x14082 + z14083 = x14083 + z14084 = x14084 + z14085 = x14085 + z14086 = x14086 + z14087 = x14087 + z14088 = x14088 + z14089 = x14089 + z14090 = x14090 + z14091 = x14091 + z14092 = x14092 + z14093 = x14093 + z14094 = x14094 + z14095 = x14095 + z14096 = x14096 + z14097 = x14097 + z14098 = x14098 + z14099 = x14099 + z14100 = x14100 + z14101 = x14101 + z14102 = x14102 + z14103 = x14103 + z14104 = x14104 + z14105 = x14105 + z14106 = x14106 + z14107 = x14107 + z14108 = x14108 + z14109 = x14109 + z14110 = x14110 + z14111 = x14111 + z14112 = x14112 + z14113 = x14113 + z14114 = x14114 + z14115 = x14115 + z14116 = x14116 + z14117 = x14117 + z14118 = x14118 + z14119 = x14119 + z14120 = x14120 + z14121 = x14121 + z14122 = x14122 + z14123 = x14123 + z14124 = x14124 + z14125 = x14125 + z14126 = x14126 + z14127 = x14127 + z14128 = x14128 + z14129 = x14129 + z14130 = x14130 + z14131 = x14131 + z14132 = x14132 + z14133 = x14133 + z14134 = x14134 + z14135 = x14135 + z14136 = x14136 + z14137 = x14137 + z14138 = x14138 + z14139 = x14139 + z14140 = x14140 + z14141 = x14141 + z14142 = x14142 + z14143 = x14143 + z14144 = x14144 + z14145 = x14145 + z14146 = x14146 + z14147 = x14147 + z14148 = x14148 + z14149 = x14149 + z14150 = x14150 + z14151 = x14151 + z14152 = x14152 + z14153 = x14153 + z14154 = x14154 + z14155 = x14155 + z14156 = x14156 + z14157 = x14157 + z14158 = x14158 + z14159 = x14159 + z14160 = x14160 + z14161 = x14161 + z14162 = x14162 + z14163 = x14163 + z14164 = x14164 + z14165 = x14165 + z14166 = x14166 + z14167 = x14167 + z14168 = x14168 + z14169 = x14169 + z14170 = x14170 + z14171 = x14171 + z14172 = x14172 + z14173 = x14173 + z14174 = x14174 + z14175 = x14175 + z14176 = x14176 + z14177 = x14177 + z14178 = x14178 + z14179 = x14179 + z14180 = x14180 + z14181 = x14181 + z14182 = x14182 + z14183 = x14183 + z14184 = x14184 + z14185 = x14185 + z14186 = x14186 + z14187 = x14187 + z14188 = x14188 + z14189 = x14189 + z14190 = x14190 + z14191 = x14191 + z14192 = x14192 + z14193 = x14193 + z14194 = x14194 + z14195 = x14195 + z14196 = x14196 + z14197 = x14197 + z14198 = x14198 + z14199 = x14199 + z14200 = x14200 + z14201 = x14201 + z14202 = x14202 + z14203 = x14203 + z14204 = x14204 + z14205 = x14205 + z14206 = x14206 + z14207 = x14207 + z14208 = x14208 + z14209 = x14209 + z14210 = x14210 + z14211 = x14211 + z14212 = x14212 + z14213 = x14213 + z14214 = x14214 + z14215 = x14215 + z14216 = x14216 + z14217 = x14217 + z14218 = x14218 + z14219 = x14219 + z14220 = x14220 + z14221 = x14221 + z14222 = x14222 + z14223 = x14223 + z14224 = x14224 + z14225 = x14225 + z14226 = x14226 + z14227 = x14227 + z14228 = x14228 + z14229 = x14229 + z14230 = x14230 + z14231 = x14231 + z14232 = x14232 + z14233 = x14233 + z14234 = x14234 + z14235 = x14235 + z14236 = x14236 + z14237 = x14237 + z14238 = x14238 + z14239 = x14239 + z14240 = x14240 + z14241 = x14241 + z14242 = x14242 + z14243 = x14243 + z14244 = x14244 + z14245 = x14245 + z14246 = x14246 + z14247 = x14247 + z14248 = x14248 + z14249 = x14249 + z14250 = x14250 + z14251 = x14251 + z14252 = x14252 + z14253 = x14253 + z14254 = x14254 + z14255 = x14255 + z14256 = x14256 + z14257 = x14257 + z14258 = x14258 + z14259 = x14259 + z14260 = x14260 + z14261 = x14261 + z14262 = x14262 + z14263 = x14263 + z14264 = x14264 + z14265 = x14265 + z14266 = x14266 + z14267 = x14267 + z14268 = x14268 + z14269 = x14269 + z14270 = x14270 + z14271 = x14271 + z14272 = x14272 + z14273 = x14273 + z14274 = x14274 + z14275 = x14275 + z14276 = x14276 + z14277 = x14277 + z14278 = x14278 + z14279 = x14279 + z14280 = x14280 + z14281 = x14281 + z14282 = x14282 + z14283 = x14283 + z14284 = x14284 + z14285 = x14285 + z14286 = x14286 + z14287 = x14287 + z14288 = x14288 + z14289 = x14289 + z14290 = x14290 + z14291 = x14291 + z14292 = x14292 + z14293 = x14293 + z14294 = x14294 + z14295 = x14295 + z14296 = x14296 + z14297 = x14297 + z14298 = x14298 + z14299 = x14299 + z14300 = x14300 + z14301 = x14301 + z14302 = x14302 + z14303 = x14303 + z14304 = x14304 + z14305 = x14305 + z14306 = x14306 + z14307 = x14307 + z14308 = x14308 + z14309 = x14309 + z14310 = x14310 + z14311 = x14311 + z14312 = x14312 + z14313 = x14313 + z14314 = x14314 + z14315 = x14315 + z14316 = x14316 + z14317 = x14317 + z14318 = x14318 + z14319 = x14319 + z14320 = x14320 + z14321 = x14321 + z14322 = x14322 + z14323 = x14323 + z14324 = x14324 + z14325 = x14325 + z14326 = x14326 + z14327 = x14327 + z14328 = x14328 + z14329 = x14329 + z14330 = x14330 + z14331 = x14331 + z14332 = x14332 + z14333 = x14333 + z14334 = x14334 + z14335 = x14335 + z14336 = x14336 + z14337 = x14337 + z14338 = x14338 + z14339 = x14339 + z14340 = x14340 + z14341 = x14341 + z14342 = x14342 + z14343 = x14343 + z14344 = x14344 + z14345 = x14345 + z14346 = x14346 + z14347 = x14347 + z14348 = x14348 + z14349 = x14349 + z14350 = x14350 + z14351 = x14351 + z14352 = x14352 + z14353 = x14353 + z14354 = x14354 + z14355 = x14355 + z14356 = x14356 + z14357 = x14357 + z14358 = x14358 + z14359 = x14359 + z14360 = x14360 + z14361 = x14361 + z14362 = x14362 + z14363 = x14363 + z14364 = x14364 + z14365 = x14365 + z14366 = x14366 + z14367 = x14367 + z14368 = x14368 + z14369 = x14369 + z14370 = x14370 + z14371 = x14371 + z14372 = x14372 + z14373 = x14373 + z14374 = x14374 + z14375 = x14375 + z14376 = x14376 + z14377 = x14377 + z14378 = x14378 + z14379 = x14379 + z14380 = x14380 + z14381 = x14381 + z14382 = x14382 + z14383 = x14383 + z14384 = x14384 + z14385 = x14385 + z14386 = x14386 + z14387 = x14387 + z14388 = x14388 + z14389 = x14389 + z14390 = x14390 + z14391 = x14391 + z14392 = x14392 + z14393 = x14393 + z14394 = x14394 + z14395 = x14395 + z14396 = x14396 + z14397 = x14397 + z14398 = x14398 + z14399 = x14399 + z14400 = x14400 + z14401 = x14401 + z14402 = x14402 + z14403 = x14403 + z14404 = x14404 + z14405 = x14405 + z14406 = x14406 + z14407 = x14407 + z14408 = x14408 + z14409 = x14409 + z14410 = x14410 + z14411 = x14411 + z14412 = x14412 + z14413 = x14413 + z14414 = x14414 + z14415 = x14415 + z14416 = x14416 + z14417 = x14417 + z14418 = x14418 + z14419 = x14419 + z14420 = x14420 + z14421 = x14421 + z14422 = x14422 + z14423 = x14423 + z14424 = x14424 + z14425 = x14425 + z14426 = x14426 + z14427 = x14427 + z14428 = x14428 + z14429 = x14429 + z14430 = x14430 + z14431 = x14431 + z14432 = x14432 + z14433 = x14433 + z14434 = x14434 + z14435 = x14435 + z14436 = x14436 + z14437 = x14437 + z14438 = x14438 + z14439 = x14439 + z14440 = x14440 + z14441 = x14441 + z14442 = x14442 + z14443 = x14443 + z14444 = x14444 + z14445 = x14445 + z14446 = x14446 + z14447 = x14447 + z14448 = x14448 + z14449 = x14449 + z14450 = x14450 + z14451 = x14451 + z14452 = x14452 + z14453 = x14453 + z14454 = x14454 + z14455 = x14455 + z14456 = x14456 + z14457 = x14457 + z14458 = x14458 + z14459 = x14459 + z14460 = x14460 + z14461 = x14461 + z14462 = x14462 + z14463 = x14463 + z14464 = x14464 + z14465 = x14465 + z14466 = x14466 + z14467 = x14467 + z14468 = x14468 + z14469 = x14469 + z14470 = x14470 + z14471 = x14471 + z14472 = x14472 + z14473 = x14473 + z14474 = x14474 + z14475 = x14475 + z14476 = x14476 + z14477 = x14477 + z14478 = x14478 + z14479 = x14479 + z14480 = x14480 + z14481 = x14481 + z14482 = x14482 + z14483 = x14483 + z14484 = x14484 + z14485 = x14485 + z14486 = x14486 + z14487 = x14487 + z14488 = x14488 + z14489 = x14489 + z14490 = x14490 + z14491 = x14491 + z14492 = x14492 + z14493 = x14493 + z14494 = x14494 + z14495 = x14495 + z14496 = x14496 + z14497 = x14497 + z14498 = x14498 + z14499 = x14499 + z14500 = x14500 + z14501 = x14501 + z14502 = x14502 + z14503 = x14503 + z14504 = x14504 + z14505 = x14505 + z14506 = x14506 + z14507 = x14507 + z14508 = x14508 + z14509 = x14509 + z14510 = x14510 + z14511 = x14511 + z14512 = x14512 + z14513 = x14513 + z14514 = x14514 + z14515 = x14515 + z14516 = x14516 + z14517 = x14517 + z14518 = x14518 + z14519 = x14519 + z14520 = x14520 + z14521 = x14521 + z14522 = x14522 + z14523 = x14523 + z14524 = x14524 + z14525 = x14525 + z14526 = x14526 + z14527 = x14527 + z14528 = x14528 + z14529 = x14529 + z14530 = x14530 + z14531 = x14531 + z14532 = x14532 + z14533 = x14533 + z14534 = x14534 + z14535 = x14535 + z14536 = x14536 + z14537 = x14537 + z14538 = x14538 + z14539 = x14539 + z14540 = x14540 + z14541 = x14541 + z14542 = x14542 + z14543 = x14543 + z14544 = x14544 + z14545 = x14545 + z14546 = x14546 + z14547 = x14547 + z14548 = x14548 + z14549 = x14549 + z14550 = x14550 + z14551 = x14551 + z14552 = x14552 + z14553 = x14553 + z14554 = x14554 + z14555 = x14555 + z14556 = x14556 + z14557 = x14557 + z14558 = x14558 + z14559 = x14559 + z14560 = x14560 + z14561 = x14561 + z14562 = x14562 + z14563 = x14563 + z14564 = x14564 + z14565 = x14565 + z14566 = x14566 + z14567 = x14567 + z14568 = x14568 + z14569 = x14569 + z14570 = x14570 + z14571 = x14571 + z14572 = x14572 + z14573 = x14573 + z14574 = x14574 + z14575 = x14575 + z14576 = x14576 + z14577 = x14577 + z14578 = x14578 + z14579 = x14579 + z14580 = x14580 + z14581 = x14581 + z14582 = x14582 + z14583 = x14583 + z14584 = x14584 + z14585 = x14585 + z14586 = x14586 + z14587 = x14587 + z14588 = x14588 + z14589 = x14589 + z14590 = x14590 + z14591 = x14591 + z14592 = x14592 + z14593 = x14593 + z14594 = x14594 + z14595 = x14595 + z14596 = x14596 + z14597 = x14597 + z14598 = x14598 + z14599 = x14599 + z14600 = x14600 + z14601 = x14601 + z14602 = x14602 + z14603 = x14603 + z14604 = x14604 + z14605 = x14605 + z14606 = x14606 + z14607 = x14607 + z14608 = x14608 + z14609 = x14609 + z14610 = x14610 + z14611 = x14611 + z14612 = x14612 + z14613 = x14613 + z14614 = x14614 + z14615 = x14615 + z14616 = x14616 + z14617 = x14617 + z14618 = x14618 + z14619 = x14619 + z14620 = x14620 + z14621 = x14621 + z14622 = x14622 + z14623 = x14623 + z14624 = x14624 + z14625 = x14625 + z14626 = x14626 + z14627 = x14627 + z14628 = x14628 + z14629 = x14629 + z14630 = x14630 + z14631 = x14631 + z14632 = x14632 + z14633 = x14633 + z14634 = x14634 + z14635 = x14635 + z14636 = x14636 + z14637 = x14637 + z14638 = x14638 + z14639 = x14639 + z14640 = x14640 + z14641 = x14641 + z14642 = x14642 + z14643 = x14643 + z14644 = x14644 + z14645 = x14645 + z14646 = x14646 + z14647 = x14647 + z14648 = x14648 + z14649 = x14649 + z14650 = x14650 + z14651 = x14651 + z14652 = x14652 + z14653 = x14653 + z14654 = x14654 + z14655 = x14655 + z14656 = x14656 + z14657 = x14657 + z14658 = x14658 + z14659 = x14659 + z14660 = x14660 + z14661 = x14661 + z14662 = x14662 + z14663 = x14663 + z14664 = x14664 + z14665 = x14665 + z14666 = x14666 + z14667 = x14667 + z14668 = x14668 + z14669 = x14669 + z14670 = x14670 + z14671 = x14671 + z14672 = x14672 + z14673 = x14673 + z14674 = x14674 + z14675 = x14675 + z14676 = x14676 + z14677 = x14677 + z14678 = x14678 + z14679 = x14679 + z14680 = x14680 + z14681 = x14681 + z14682 = x14682 + z14683 = x14683 + z14684 = x14684 + z14685 = x14685 + z14686 = x14686 + z14687 = x14687 + z14688 = x14688 + z14689 = x14689 + z14690 = x14690 + z14691 = x14691 + z14692 = x14692 + z14693 = x14693 + z14694 = x14694 + z14695 = x14695 + z14696 = x14696 + z14697 = x14697 + z14698 = x14698 + z14699 = x14699 + z14700 = x14700 + z14701 = x14701 + z14702 = x14702 + z14703 = x14703 + z14704 = x14704 + z14705 = x14705 + z14706 = x14706 + z14707 = x14707 + z14708 = x14708 + z14709 = x14709 + z14710 = x14710 + z14711 = x14711 + z14712 = x14712 + z14713 = x14713 + z14714 = x14714 + z14715 = x14715 + z14716 = x14716 + z14717 = x14717 + z14718 = x14718 + z14719 = x14719 + z14720 = x14720 + z14721 = x14721 + z14722 = x14722 + z14723 = x14723 + z14724 = x14724 + z14725 = x14725 + z14726 = x14726 + z14727 = x14727 + z14728 = x14728 + z14729 = x14729 + z14730 = x14730 + z14731 = x14731 + z14732 = x14732 + z14733 = x14733 + z14734 = x14734 + z14735 = x14735 + z14736 = x14736 + z14737 = x14737 + z14738 = x14738 + z14739 = x14739 + z14740 = x14740 + z14741 = x14741 + z14742 = x14742 + z14743 = x14743 + z14744 = x14744 + z14745 = x14745 + z14746 = x14746 + z14747 = x14747 + z14748 = x14748 + z14749 = x14749 + z14750 = x14750 + z14751 = x14751 + z14752 = x14752 + z14753 = x14753 + z14754 = x14754 + z14755 = x14755 + z14756 = x14756 + z14757 = x14757 + z14758 = x14758 + z14759 = x14759 + z14760 = x14760 + z14761 = x14761 + z14762 = x14762 + z14763 = x14763 + z14764 = x14764 + z14765 = x14765 + z14766 = x14766 + z14767 = x14767 + z14768 = x14768 + z14769 = x14769 + z14770 = x14770 + z14771 = x14771 + z14772 = x14772 + z14773 = x14773 + z14774 = x14774 + z14775 = x14775 + z14776 = x14776 + z14777 = x14777 + z14778 = x14778 + z14779 = x14779 + z14780 = x14780 + z14781 = x14781 + z14782 = x14782 + z14783 = x14783 + z14784 = x14784 + z14785 = x14785 + z14786 = x14786 + z14787 = x14787 + z14788 = x14788 + z14789 = x14789 + z14790 = x14790 + z14791 = x14791 + z14792 = x14792 + z14793 = x14793 + z14794 = x14794 + z14795 = x14795 + z14796 = x14796 + z14797 = x14797 + z14798 = x14798 + z14799 = x14799 + z14800 = x14800 + z14801 = x14801 + z14802 = x14802 + z14803 = x14803 + z14804 = x14804 + z14805 = x14805 + z14806 = x14806 + z14807 = x14807 + z14808 = x14808 + z14809 = x14809 + z14810 = x14810 + z14811 = x14811 + z14812 = x14812 + z14813 = x14813 + z14814 = x14814 + z14815 = x14815 + z14816 = x14816 + z14817 = x14817 + z14818 = x14818 + z14819 = x14819 + z14820 = x14820 + z14821 = x14821 + z14822 = x14822 + z14823 = x14823 + z14824 = x14824 + z14825 = x14825 + z14826 = x14826 + z14827 = x14827 + z14828 = x14828 + z14829 = x14829 + z14830 = x14830 + z14831 = x14831 + z14832 = x14832 + z14833 = x14833 + z14834 = x14834 + z14835 = x14835 + z14836 = x14836 + z14837 = x14837 + z14838 = x14838 + z14839 = x14839 + z14840 = x14840 + z14841 = x14841 + z14842 = x14842 + z14843 = x14843 + z14844 = x14844 + z14845 = x14845 + z14846 = x14846 + z14847 = x14847 + z14848 = x14848 + z14849 = x14849 + z14850 = x14850 + z14851 = x14851 + z14852 = x14852 + z14853 = x14853 + z14854 = x14854 + z14855 = x14855 + z14856 = x14856 + z14857 = x14857 + z14858 = x14858 + z14859 = x14859 + z14860 = x14860 + z14861 = x14861 + z14862 = x14862 + z14863 = x14863 + z14864 = x14864 + z14865 = x14865 + z14866 = x14866 + z14867 = x14867 + z14868 = x14868 + z14869 = x14869 + z14870 = x14870 + z14871 = x14871 + z14872 = x14872 + z14873 = x14873 + z14874 = x14874 + z14875 = x14875 + z14876 = x14876 + z14877 = x14877 + z14878 = x14878 + z14879 = x14879 + z14880 = x14880 + z14881 = x14881 + z14882 = x14882 + z14883 = x14883 + z14884 = x14884 + z14885 = x14885 + z14886 = x14886 + z14887 = x14887 + z14888 = x14888 + z14889 = x14889 + z14890 = x14890 + z14891 = x14891 + z14892 = x14892 + z14893 = x14893 + z14894 = x14894 + z14895 = x14895 + z14896 = x14896 + z14897 = x14897 + z14898 = x14898 + z14899 = x14899 + z14900 = x14900 + z14901 = x14901 + z14902 = x14902 + z14903 = x14903 + z14904 = x14904 + z14905 = x14905 + z14906 = x14906 + z14907 = x14907 + z14908 = x14908 + z14909 = x14909 + z14910 = x14910 + z14911 = x14911 + z14912 = x14912 + z14913 = x14913 + z14914 = x14914 + z14915 = x14915 + z14916 = x14916 + z14917 = x14917 + z14918 = x14918 + z14919 = x14919 + z14920 = x14920 + z14921 = x14921 + z14922 = x14922 + z14923 = x14923 + z14924 = x14924 + z14925 = x14925 + z14926 = x14926 + z14927 = x14927 + z14928 = x14928 + z14929 = x14929 + z14930 = x14930 + z14931 = x14931 + z14932 = x14932 + z14933 = x14933 + z14934 = x14934 + z14935 = x14935 + z14936 = x14936 + z14937 = x14937 + z14938 = x14938 + z14939 = x14939 + z14940 = x14940 + z14941 = x14941 + z14942 = x14942 + z14943 = x14943 + z14944 = x14944 + z14945 = x14945 + z14946 = x14946 + z14947 = x14947 + z14948 = x14948 + z14949 = x14949 + z14950 = x14950 + z14951 = x14951 + z14952 = x14952 + z14953 = x14953 + z14954 = x14954 + z14955 = x14955 + z14956 = x14956 + z14957 = x14957 + z14958 = x14958 + z14959 = x14959 + z14960 = x14960 + z14961 = x14961 + z14962 = x14962 + z14963 = x14963 + z14964 = x14964 + z14965 = x14965 + z14966 = x14966 + z14967 = x14967 + z14968 = x14968 + z14969 = x14969 + z14970 = x14970 + z14971 = x14971 + z14972 = x14972 + z14973 = x14973 + z14974 = x14974 + z14975 = x14975 + z14976 = x14976 + z14977 = x14977 + z14978 = x14978 + z14979 = x14979 + z14980 = x14980 + z14981 = x14981 + z14982 = x14982 + z14983 = x14983 + z14984 = x14984 + z14985 = x14985 + z14986 = x14986 + z14987 = x14987 + z14988 = x14988 + z14989 = x14989 + z14990 = x14990 + z14991 = x14991 + z14992 = x14992 + z14993 = x14993 + z14994 = x14994 + z14995 = x14995 + z14996 = x14996 + z14997 = x14997 + z14998 = x14998 + z14999 = x14999 + z15000 = x15000 + z15001 = x15001 + z15002 = x15002 + z15003 = x15003 + z15004 = x15004 + z15005 = x15005 + z15006 = x15006 + z15007 = x15007 + z15008 = x15008 + z15009 = x15009 + z15010 = x15010 + z15011 = x15011 + z15012 = x15012 + z15013 = x15013 + z15014 = x15014 + z15015 = x15015 + z15016 = x15016 + z15017 = x15017 + z15018 = x15018 + z15019 = x15019 + z15020 = x15020 + z15021 = x15021 + z15022 = x15022 + z15023 = x15023 + z15024 = x15024 + z15025 = x15025 + z15026 = x15026 + z15027 = x15027 + z15028 = x15028 + z15029 = x15029 + z15030 = x15030 + z15031 = x15031 + z15032 = x15032 + z15033 = x15033 + z15034 = x15034 + z15035 = x15035 + z15036 = x15036 + z15037 = x15037 + z15038 = x15038 + z15039 = x15039 + z15040 = x15040 + z15041 = x15041 + z15042 = x15042 + z15043 = x15043 + z15044 = x15044 + z15045 = x15045 + z15046 = x15046 + z15047 = x15047 + z15048 = x15048 + z15049 = x15049 + z15050 = x15050 + z15051 = x15051 + z15052 = x15052 + z15053 = x15053 + z15054 = x15054 + z15055 = x15055 + z15056 = x15056 + z15057 = x15057 + z15058 = x15058 + z15059 = x15059 + z15060 = x15060 + z15061 = x15061 + z15062 = x15062 + z15063 = x15063 + z15064 = x15064 + z15065 = x15065 + z15066 = x15066 + z15067 = x15067 + z15068 = x15068 + z15069 = x15069 + z15070 = x15070 + z15071 = x15071 + z15072 = x15072 + z15073 = x15073 + z15074 = x15074 + z15075 = x15075 + z15076 = x15076 + z15077 = x15077 + z15078 = x15078 + z15079 = x15079 + z15080 = x15080 + z15081 = x15081 + z15082 = x15082 + z15083 = x15083 + z15084 = x15084 + z15085 = x15085 + z15086 = x15086 + z15087 = x15087 + z15088 = x15088 + z15089 = x15089 + z15090 = x15090 + z15091 = x15091 + z15092 = x15092 + z15093 = x15093 + z15094 = x15094 + z15095 = x15095 + z15096 = x15096 + z15097 = x15097 + z15098 = x15098 + z15099 = x15099 + z15100 = x15100 + z15101 = x15101 + z15102 = x15102 + z15103 = x15103 + z15104 = x15104 + z15105 = x15105 + z15106 = x15106 + z15107 = x15107 + z15108 = x15108 + z15109 = x15109 + z15110 = x15110 + z15111 = x15111 + z15112 = x15112 + z15113 = x15113 + z15114 = x15114 + z15115 = x15115 + z15116 = x15116 + z15117 = x15117 + z15118 = x15118 + z15119 = x15119 + z15120 = x15120 + z15121 = x15121 + z15122 = x15122 + z15123 = x15123 + z15124 = x15124 + z15125 = x15125 + z15126 = x15126 + z15127 = x15127 + z15128 = x15128 + z15129 = x15129 + z15130 = x15130 + z15131 = x15131 + z15132 = x15132 + z15133 = x15133 + z15134 = x15134 + z15135 = x15135 + z15136 = x15136 + z15137 = x15137 + z15138 = x15138 + z15139 = x15139 + z15140 = x15140 + z15141 = x15141 + z15142 = x15142 + z15143 = x15143 + z15144 = x15144 + z15145 = x15145 + z15146 = x15146 + z15147 = x15147 + z15148 = x15148 + z15149 = x15149 + z15150 = x15150 + z15151 = x15151 + z15152 = x15152 + z15153 = x15153 + z15154 = x15154 + z15155 = x15155 + z15156 = x15156 + z15157 = x15157 + z15158 = x15158 + z15159 = x15159 + z15160 = x15160 + z15161 = x15161 + z15162 = x15162 + z15163 = x15163 + z15164 = x15164 + z15165 = x15165 + z15166 = x15166 + z15167 = x15167 + z15168 = x15168 + z15169 = x15169 + z15170 = x15170 + z15171 = x15171 + z15172 = x15172 + z15173 = x15173 + z15174 = x15174 + z15175 = x15175 + z15176 = x15176 + z15177 = x15177 + z15178 = x15178 + z15179 = x15179 + z15180 = x15180 + z15181 = x15181 + z15182 = x15182 + z15183 = x15183 + z15184 = x15184 + z15185 = x15185 + z15186 = x15186 + z15187 = x15187 + z15188 = x15188 + z15189 = x15189 + z15190 = x15190 + z15191 = x15191 + z15192 = x15192 + z15193 = x15193 + z15194 = x15194 + z15195 = x15195 + z15196 = x15196 + z15197 = x15197 + z15198 = x15198 + z15199 = x15199 + z15200 = x15200 + z15201 = x15201 + z15202 = x15202 + z15203 = x15203 + z15204 = x15204 + z15205 = x15205 + z15206 = x15206 + z15207 = x15207 + z15208 = x15208 + z15209 = x15209 + z15210 = x15210 + z15211 = x15211 + z15212 = x15212 + z15213 = x15213 + z15214 = x15214 + z15215 = x15215 + z15216 = x15216 + z15217 = x15217 + z15218 = x15218 + z15219 = x15219 + z15220 = x15220 + z15221 = x15221 + z15222 = x15222 + z15223 = x15223 + z15224 = x15224 + z15225 = x15225 + z15226 = x15226 + z15227 = x15227 + z15228 = x15228 + z15229 = x15229 + z15230 = x15230 + z15231 = x15231 + z15232 = x15232 + z15233 = x15233 + z15234 = x15234 + z15235 = x15235 + z15236 = x15236 + z15237 = x15237 + z15238 = x15238 + z15239 = x15239 + z15240 = x15240 + z15241 = x15241 + z15242 = x15242 + z15243 = x15243 + z15244 = x15244 + z15245 = x15245 + z15246 = x15246 + z15247 = x15247 + z15248 = x15248 + z15249 = x15249 + z15250 = x15250 + z15251 = x15251 + z15252 = x15252 + z15253 = x15253 + z15254 = x15254 + z15255 = x15255 + z15256 = x15256 + z15257 = x15257 + z15258 = x15258 + z15259 = x15259 + z15260 = x15260 + z15261 = x15261 + z15262 = x15262 + z15263 = x15263 + z15264 = x15264 + z15265 = x15265 + z15266 = x15266 + z15267 = x15267 + z15268 = x15268 + z15269 = x15269 + z15270 = x15270 + z15271 = x15271 + z15272 = x15272 + z15273 = x15273 + z15274 = x15274 + z15275 = x15275 + z15276 = x15276 + z15277 = x15277 + z15278 = x15278 + z15279 = x15279 + z15280 = x15280 + z15281 = x15281 + z15282 = x15282 + z15283 = x15283 + z15284 = x15284 + z15285 = x15285 + z15286 = x15286 + z15287 = x15287 + z15288 = x15288 + z15289 = x15289 + z15290 = x15290 + z15291 = x15291 + z15292 = x15292 + z15293 = x15293 + z15294 = x15294 + z15295 = x15295 + z15296 = x15296 + z15297 = x15297 + z15298 = x15298 + z15299 = x15299 + z15300 = x15300 + z15301 = x15301 + z15302 = x15302 + z15303 = x15303 + z15304 = x15304 + z15305 = x15305 + z15306 = x15306 + z15307 = x15307 + z15308 = x15308 + z15309 = x15309 + z15310 = x15310 + z15311 = x15311 + z15312 = x15312 + z15313 = x15313 + z15314 = x15314 + z15315 = x15315 + z15316 = x15316 + z15317 = x15317 + z15318 = x15318 + z15319 = x15319 + z15320 = x15320 + z15321 = x15321 + z15322 = x15322 + z15323 = x15323 + z15324 = x15324 + z15325 = x15325 + z15326 = x15326 + z15327 = x15327 + z15328 = x15328 + z15329 = x15329 + z15330 = x15330 + z15331 = x15331 + z15332 = x15332 + z15333 = x15333 + z15334 = x15334 + z15335 = x15335 + z15336 = x15336 + z15337 = x15337 + z15338 = x15338 + z15339 = x15339 + z15340 = x15340 + z15341 = x15341 + z15342 = x15342 + z15343 = x15343 + z15344 = x15344 + z15345 = x15345 + z15346 = x15346 + z15347 = x15347 + z15348 = x15348 + z15349 = x15349 + z15350 = x15350 + z15351 = x15351 + z15352 = x15352 + z15353 = x15353 + z15354 = x15354 + z15355 = x15355 + z15356 = x15356 + z15357 = x15357 + z15358 = x15358 + z15359 = x15359 + z15360 = x15360 + z15361 = x15361 + z15362 = x15362 + z15363 = x15363 + z15364 = x15364 + z15365 = x15365 + z15366 = x15366 + z15367 = x15367 + z15368 = x15368 + z15369 = x15369 + z15370 = x15370 + z15371 = x15371 + z15372 = x15372 + z15373 = x15373 + z15374 = x15374 + z15375 = x15375 + z15376 = x15376 + z15377 = x15377 + z15378 = x15378 + z15379 = x15379 + z15380 = x15380 + z15381 = x15381 + z15382 = x15382 + z15383 = x15383 + z15384 = x15384 + z15385 = x15385 + z15386 = x15386 + z15387 = x15387 + z15388 = x15388 + z15389 = x15389 + z15390 = x15390 + z15391 = x15391 + z15392 = x15392 + z15393 = x15393 + z15394 = x15394 + z15395 = x15395 + z15396 = x15396 + z15397 = x15397 + z15398 = x15398 + z15399 = x15399 + z15400 = x15400 + z15401 = x15401 + z15402 = x15402 + z15403 = x15403 + z15404 = x15404 + z15405 = x15405 + z15406 = x15406 + z15407 = x15407 + z15408 = x15408 + z15409 = x15409 + z15410 = x15410 + z15411 = x15411 + z15412 = x15412 + z15413 = x15413 + z15414 = x15414 + z15415 = x15415 + z15416 = x15416 + z15417 = x15417 + z15418 = x15418 + z15419 = x15419 + z15420 = x15420 + z15421 = x15421 + z15422 = x15422 + z15423 = x15423 + z15424 = x15424 + z15425 = x15425 + z15426 = x15426 + z15427 = x15427 + z15428 = x15428 + z15429 = x15429 + z15430 = x15430 + z15431 = x15431 + z15432 = x15432 + z15433 = x15433 + z15434 = x15434 + z15435 = x15435 + z15436 = x15436 + z15437 = x15437 + z15438 = x15438 + z15439 = x15439 + z15440 = x15440 + z15441 = x15441 + z15442 = x15442 + z15443 = x15443 + z15444 = x15444 + z15445 = x15445 + z15446 = x15446 + z15447 = x15447 + z15448 = x15448 + z15449 = x15449 + z15450 = x15450 + z15451 = x15451 + z15452 = x15452 + z15453 = x15453 + z15454 = x15454 + z15455 = x15455 + z15456 = x15456 + z15457 = x15457 + z15458 = x15458 + z15459 = x15459 + z15460 = x15460 + z15461 = x15461 + z15462 = x15462 + z15463 = x15463 + z15464 = x15464 + z15465 = x15465 + z15466 = x15466 + z15467 = x15467 + z15468 = x15468 + z15469 = x15469 + z15470 = x15470 + z15471 = x15471 + z15472 = x15472 + z15473 = x15473 + z15474 = x15474 + z15475 = x15475 + z15476 = x15476 + z15477 = x15477 + z15478 = x15478 + z15479 = x15479 + z15480 = x15480 + z15481 = x15481 + z15482 = x15482 + z15483 = x15483 + z15484 = x15484 + z15485 = x15485 + z15486 = x15486 + z15487 = x15487 + z15488 = x15488 + z15489 = x15489 + z15490 = x15490 + z15491 = x15491 + z15492 = x15492 + z15493 = x15493 + z15494 = x15494 + z15495 = x15495 + z15496 = x15496 + z15497 = x15497 + z15498 = x15498 + z15499 = x15499 + z15500 = x15500 + z15501 = x15501 + z15502 = x15502 + z15503 = x15503 + z15504 = x15504 + z15505 = x15505 + z15506 = x15506 + z15507 = x15507 + z15508 = x15508 + z15509 = x15509 + z15510 = x15510 + z15511 = x15511 + z15512 = x15512 + z15513 = x15513 + z15514 = x15514 + z15515 = x15515 + z15516 = x15516 + z15517 = x15517 + z15518 = x15518 + z15519 = x15519 + z15520 = x15520 + z15521 = x15521 + z15522 = x15522 + z15523 = x15523 + z15524 = x15524 + z15525 = x15525 + z15526 = x15526 + z15527 = x15527 + z15528 = x15528 + z15529 = x15529 + z15530 = x15530 + z15531 = x15531 + z15532 = x15532 + z15533 = x15533 + z15534 = x15534 + z15535 = x15535 + z15536 = x15536 + z15537 = x15537 + z15538 = x15538 + z15539 = x15539 + z15540 = x15540 + z15541 = x15541 + z15542 = x15542 + z15543 = x15543 + z15544 = x15544 + z15545 = x15545 + z15546 = x15546 + z15547 = x15547 + z15548 = x15548 + z15549 = x15549 + z15550 = x15550 + z15551 = x15551 + z15552 = x15552 + z15553 = x15553 + z15554 = x15554 + z15555 = x15555 + z15556 = x15556 + z15557 = x15557 + z15558 = x15558 + z15559 = x15559 + z15560 = x15560 + z15561 = x15561 + z15562 = x15562 + z15563 = x15563 + z15564 = x15564 + z15565 = x15565 + z15566 = x15566 + z15567 = x15567 + z15568 = x15568 + z15569 = x15569 + z15570 = x15570 + z15571 = x15571 + z15572 = x15572 + z15573 = x15573 + z15574 = x15574 + z15575 = x15575 + z15576 = x15576 + z15577 = x15577 + z15578 = x15578 + z15579 = x15579 + z15580 = x15580 + z15581 = x15581 + z15582 = x15582 + z15583 = x15583 + z15584 = x15584 + z15585 = x15585 + z15586 = x15586 + z15587 = x15587 + z15588 = x15588 + z15589 = x15589 + z15590 = x15590 + z15591 = x15591 + z15592 = x15592 + z15593 = x15593 + z15594 = x15594 + z15595 = x15595 + z15596 = x15596 + z15597 = x15597 + z15598 = x15598 + z15599 = x15599 + z15600 = x15600 + z15601 = x15601 + z15602 = x15602 + z15603 = x15603 + z15604 = x15604 + z15605 = x15605 + z15606 = x15606 + z15607 = x15607 + z15608 = x15608 + z15609 = x15609 + z15610 = x15610 + z15611 = x15611 + z15612 = x15612 + z15613 = x15613 + z15614 = x15614 + z15615 = x15615 + z15616 = x15616 + z15617 = x15617 + z15618 = x15618 + z15619 = x15619 + z15620 = x15620 + z15621 = x15621 + z15622 = x15622 + z15623 = x15623 + z15624 = x15624 + z15625 = x15625 + z15626 = x15626 + z15627 = x15627 + z15628 = x15628 + z15629 = x15629 + z15630 = x15630 + z15631 = x15631 + z15632 = x15632 + z15633 = x15633 + z15634 = x15634 + z15635 = x15635 + z15636 = x15636 + z15637 = x15637 + z15638 = x15638 + z15639 = x15639 + z15640 = x15640 + z15641 = x15641 + z15642 = x15642 + z15643 = x15643 + z15644 = x15644 + z15645 = x15645 + z15646 = x15646 + z15647 = x15647 + z15648 = x15648 + z15649 = x15649 + z15650 = x15650 + z15651 = x15651 + z15652 = x15652 + z15653 = x15653 + z15654 = x15654 + z15655 = x15655 + z15656 = x15656 + z15657 = x15657 + z15658 = x15658 + z15659 = x15659 + z15660 = x15660 + z15661 = x15661 + z15662 = x15662 + z15663 = x15663 + z15664 = x15664 + z15665 = x15665 + z15666 = x15666 + z15667 = x15667 + z15668 = x15668 + z15669 = x15669 + z15670 = x15670 + z15671 = x15671 + z15672 = x15672 + z15673 = x15673 + z15674 = x15674 + z15675 = x15675 + z15676 = x15676 + z15677 = x15677 + z15678 = x15678 + z15679 = x15679 + z15680 = x15680 + z15681 = x15681 + z15682 = x15682 + z15683 = x15683 + z15684 = x15684 + z15685 = x15685 + z15686 = x15686 + z15687 = x15687 + z15688 = x15688 + z15689 = x15689 + z15690 = x15690 + z15691 = x15691 + z15692 = x15692 + z15693 = x15693 + z15694 = x15694 + z15695 = x15695 + z15696 = x15696 + z15697 = x15697 + z15698 = x15698 + z15699 = x15699 + z15700 = x15700 + z15701 = x15701 + z15702 = x15702 + z15703 = x15703 + z15704 = x15704 + z15705 = x15705 + z15706 = x15706 + z15707 = x15707 + z15708 = x15708 + z15709 = x15709 + z15710 = x15710 + z15711 = x15711 + z15712 = x15712 + z15713 = x15713 + z15714 = x15714 + z15715 = x15715 + z15716 = x15716 + z15717 = x15717 + z15718 = x15718 + z15719 = x15719 + z15720 = x15720 + z15721 = x15721 + z15722 = x15722 + z15723 = x15723 + z15724 = x15724 + z15725 = x15725 + z15726 = x15726 + z15727 = x15727 + z15728 = x15728 + z15729 = x15729 + z15730 = x15730 + z15731 = x15731 + z15732 = x15732 + z15733 = x15733 + z15734 = x15734 + z15735 = x15735 + z15736 = x15736 + z15737 = x15737 + z15738 = x15738 + z15739 = x15739 + z15740 = x15740 + z15741 = x15741 + z15742 = x15742 + z15743 = x15743 + z15744 = x15744 + z15745 = x15745 + z15746 = x15746 + z15747 = x15747 + z15748 = x15748 + z15749 = x15749 + z15750 = x15750 + z15751 = x15751 + z15752 = x15752 + z15753 = x15753 + z15754 = x15754 + z15755 = x15755 + z15756 = x15756 + z15757 = x15757 + z15758 = x15758 + z15759 = x15759 + z15760 = x15760 + z15761 = x15761 + z15762 = x15762 + z15763 = x15763 + z15764 = x15764 + z15765 = x15765 + z15766 = x15766 + z15767 = x15767 + z15768 = x15768 + z15769 = x15769 + z15770 = x15770 + z15771 = x15771 + z15772 = x15772 + z15773 = x15773 + z15774 = x15774 + z15775 = x15775 + z15776 = x15776 + z15777 = x15777 + z15778 = x15778 + z15779 = x15779 + z15780 = x15780 + z15781 = x15781 + z15782 = x15782 + z15783 = x15783 + z15784 = x15784 + z15785 = x15785 + z15786 = x15786 + z15787 = x15787 + z15788 = x15788 + z15789 = x15789 + z15790 = x15790 + z15791 = x15791 + z15792 = x15792 + z15793 = x15793 + z15794 = x15794 + z15795 = x15795 + z15796 = x15796 + z15797 = x15797 + z15798 = x15798 + z15799 = x15799 + z15800 = x15800 + z15801 = x15801 + z15802 = x15802 + z15803 = x15803 + z15804 = x15804 + z15805 = x15805 + z15806 = x15806 + z15807 = x15807 + z15808 = x15808 + z15809 = x15809 + z15810 = x15810 + z15811 = x15811 + z15812 = x15812 + z15813 = x15813 + z15814 = x15814 + z15815 = x15815 + z15816 = x15816 + z15817 = x15817 + z15818 = x15818 + z15819 = x15819 + z15820 = x15820 + z15821 = x15821 + z15822 = x15822 + z15823 = x15823 + z15824 = x15824 + z15825 = x15825 + z15826 = x15826 + z15827 = x15827 + z15828 = x15828 + z15829 = x15829 + z15830 = x15830 + z15831 = x15831 + z15832 = x15832 + z15833 = x15833 + z15834 = x15834 + z15835 = x15835 + z15836 = x15836 + z15837 = x15837 + z15838 = x15838 + z15839 = x15839 + z15840 = x15840 + z15841 = x15841 + z15842 = x15842 + z15843 = x15843 + z15844 = x15844 + z15845 = x15845 + z15846 = x15846 + z15847 = x15847 + z15848 = x15848 + z15849 = x15849 + z15850 = x15850 + z15851 = x15851 + z15852 = x15852 + z15853 = x15853 + z15854 = x15854 + z15855 = x15855 + z15856 = x15856 + z15857 = x15857 + z15858 = x15858 + z15859 = x15859 + z15860 = x15860 + z15861 = x15861 + z15862 = x15862 + z15863 = x15863 + z15864 = x15864 + z15865 = x15865 + z15866 = x15866 + z15867 = x15867 + z15868 = x15868 + z15869 = x15869 + z15870 = x15870 + z15871 = x15871 + z15872 = x15872 + z15873 = x15873 + z15874 = x15874 + z15875 = x15875 + z15876 = x15876 + z15877 = x15877 + z15878 = x15878 + z15879 = x15879 + z15880 = x15880 + z15881 = x15881 + z15882 = x15882 + z15883 = x15883 + z15884 = x15884 + z15885 = x15885 + z15886 = x15886 + z15887 = x15887 + z15888 = x15888 + z15889 = x15889 + z15890 = x15890 + z15891 = x15891 + z15892 = x15892 + z15893 = x15893 + z15894 = x15894 + z15895 = x15895 + z15896 = x15896 + z15897 = x15897 + z15898 = x15898 + z15899 = x15899 + z15900 = x15900 + z15901 = x15901 + z15902 = x15902 + z15903 = x15903 + z15904 = x15904 + z15905 = x15905 + z15906 = x15906 + z15907 = x15907 + z15908 = x15908 + z15909 = x15909 + z15910 = x15910 + z15911 = x15911 + z15912 = x15912 + z15913 = x15913 + z15914 = x15914 + z15915 = x15915 + z15916 = x15916 + z15917 = x15917 + z15918 = x15918 + z15919 = x15919 + z15920 = x15920 + z15921 = x15921 + z15922 = x15922 + z15923 = x15923 + z15924 = x15924 + z15925 = x15925 + z15926 = x15926 + z15927 = x15927 + z15928 = x15928 + z15929 = x15929 + z15930 = x15930 + z15931 = x15931 + z15932 = x15932 + z15933 = x15933 + z15934 = x15934 + z15935 = x15935 + z15936 = x15936 + z15937 = x15937 + z15938 = x15938 + z15939 = x15939 + z15940 = x15940 + z15941 = x15941 + z15942 = x15942 + z15943 = x15943 + z15944 = x15944 + z15945 = x15945 + z15946 = x15946 + z15947 = x15947 + z15948 = x15948 + z15949 = x15949 + z15950 = x15950 + z15951 = x15951 + z15952 = x15952 + z15953 = x15953 + z15954 = x15954 + z15955 = x15955 + z15956 = x15956 + z15957 = x15957 + z15958 = x15958 + z15959 = x15959 + z15960 = x15960 + z15961 = x15961 + z15962 = x15962 + z15963 = x15963 + z15964 = x15964 + z15965 = x15965 + z15966 = x15966 + z15967 = x15967 + z15968 = x15968 + z15969 = x15969 + z15970 = x15970 + z15971 = x15971 + z15972 = x15972 + z15973 = x15973 + z15974 = x15974 + z15975 = x15975 + z15976 = x15976 + z15977 = x15977 + z15978 = x15978 + z15979 = x15979 + z15980 = x15980 + z15981 = x15981 + z15982 = x15982 + z15983 = x15983 + z15984 = x15984 + z15985 = x15985 + z15986 = x15986 + z15987 = x15987 + z15988 = x15988 + z15989 = x15989 + z15990 = x15990 + z15991 = x15991 + z15992 = x15992 + z15993 = x15993 + z15994 = x15994 + z15995 = x15995 + z15996 = x15996 + z15997 = x15997 + z15998 = x15998 + z15999 = x15999 + z16000 = x16000 + z16001 = x16001 + z16002 = x16002 + z16003 = x16003 + z16004 = x16004 + z16005 = x16005 + z16006 = x16006 + z16007 = x16007 + z16008 = x16008 + z16009 = x16009 + z16010 = x16010 + z16011 = x16011 + z16012 = x16012 + z16013 = x16013 + z16014 = x16014 + z16015 = x16015 + z16016 = x16016 + z16017 = x16017 + z16018 = x16018 + z16019 = x16019 + z16020 = x16020 + z16021 = x16021 + z16022 = x16022 + z16023 = x16023 + z16024 = x16024 + z16025 = x16025 + z16026 = x16026 + z16027 = x16027 + z16028 = x16028 + z16029 = x16029 + z16030 = x16030 + z16031 = x16031 + z16032 = x16032 + z16033 = x16033 + z16034 = x16034 + z16035 = x16035 + z16036 = x16036 + z16037 = x16037 + z16038 = x16038 + z16039 = x16039 + z16040 = x16040 + z16041 = x16041 + z16042 = x16042 + z16043 = x16043 + z16044 = x16044 + z16045 = x16045 + z16046 = x16046 + z16047 = x16047 + z16048 = x16048 + z16049 = x16049 + z16050 = x16050 + z16051 = x16051 + z16052 = x16052 + z16053 = x16053 + z16054 = x16054 + z16055 = x16055 + z16056 = x16056 + z16057 = x16057 + z16058 = x16058 + z16059 = x16059 + z16060 = x16060 + z16061 = x16061 + z16062 = x16062 + z16063 = x16063 + z16064 = x16064 + z16065 = x16065 + z16066 = x16066 + z16067 = x16067 + z16068 = x16068 + z16069 = x16069 + z16070 = x16070 + z16071 = x16071 + z16072 = x16072 + z16073 = x16073 + z16074 = x16074 + z16075 = x16075 + z16076 = x16076 + z16077 = x16077 + z16078 = x16078 + z16079 = x16079 + z16080 = x16080 + z16081 = x16081 + z16082 = x16082 + z16083 = x16083 + z16084 = x16084 + z16085 = x16085 + z16086 = x16086 + z16087 = x16087 + z16088 = x16088 + z16089 = x16089 + z16090 = x16090 + z16091 = x16091 + z16092 = x16092 + z16093 = x16093 + z16094 = x16094 + z16095 = x16095 + z16096 = x16096 + z16097 = x16097 + z16098 = x16098 + z16099 = x16099 + z16100 = x16100 + z16101 = x16101 + z16102 = x16102 + z16103 = x16103 + z16104 = x16104 + z16105 = x16105 + z16106 = x16106 + z16107 = x16107 + z16108 = x16108 + z16109 = x16109 + z16110 = x16110 + z16111 = x16111 + z16112 = x16112 + z16113 = x16113 + z16114 = x16114 + z16115 = x16115 + z16116 = x16116 + z16117 = x16117 + z16118 = x16118 + z16119 = x16119 + z16120 = x16120 + z16121 = x16121 + z16122 = x16122 + z16123 = x16123 + z16124 = x16124 + z16125 = x16125 + z16126 = x16126 + z16127 = x16127 + z16128 = x16128 + z16129 = x16129 + z16130 = x16130 + z16131 = x16131 + z16132 = x16132 + z16133 = x16133 + z16134 = x16134 + z16135 = x16135 + z16136 = x16136 + z16137 = x16137 + z16138 = x16138 + z16139 = x16139 + z16140 = x16140 + z16141 = x16141 + z16142 = x16142 + z16143 = x16143 + z16144 = x16144 + z16145 = x16145 + z16146 = x16146 + z16147 = x16147 + z16148 = x16148 + z16149 = x16149 + z16150 = x16150 + z16151 = x16151 + z16152 = x16152 + z16153 = x16153 + z16154 = x16154 + z16155 = x16155 + z16156 = x16156 + z16157 = x16157 + z16158 = x16158 + z16159 = x16159 + z16160 = x16160 + z16161 = x16161 + z16162 = x16162 + z16163 = x16163 + z16164 = x16164 + z16165 = x16165 + z16166 = x16166 + z16167 = x16167 + z16168 = x16168 + z16169 = x16169 + z16170 = x16170 + z16171 = x16171 + z16172 = x16172 + z16173 = x16173 + z16174 = x16174 + z16175 = x16175 + z16176 = x16176 + z16177 = x16177 + z16178 = x16178 + z16179 = x16179 + z16180 = x16180 + z16181 = x16181 + z16182 = x16182 + z16183 = x16183 + z16184 = x16184 + z16185 = x16185 + z16186 = x16186 + z16187 = x16187 + z16188 = x16188 + z16189 = x16189 + z16190 = x16190 + z16191 = x16191 + z16192 = x16192 + z16193 = x16193 + z16194 = x16194 + z16195 = x16195 + z16196 = x16196 + z16197 = x16197 + z16198 = x16198 + z16199 = x16199 + z16200 = x16200 + z16201 = x16201 + z16202 = x16202 + z16203 = x16203 + z16204 = x16204 + z16205 = x16205 + z16206 = x16206 + z16207 = x16207 + z16208 = x16208 + z16209 = x16209 + z16210 = x16210 + z16211 = x16211 + z16212 = x16212 + z16213 = x16213 + z16214 = x16214 + z16215 = x16215 + z16216 = x16216 + z16217 = x16217 + z16218 = x16218 + z16219 = x16219 + z16220 = x16220 + z16221 = x16221 + z16222 = x16222 + z16223 = x16223 + z16224 = x16224 + z16225 = x16225 + z16226 = x16226 + z16227 = x16227 + z16228 = x16228 + z16229 = x16229 + z16230 = x16230 + z16231 = x16231 + z16232 = x16232 + z16233 = x16233 + z16234 = x16234 + z16235 = x16235 + z16236 = x16236 + z16237 = x16237 + z16238 = x16238 + z16239 = x16239 + z16240 = x16240 + z16241 = x16241 + z16242 = x16242 + z16243 = x16243 + z16244 = x16244 + z16245 = x16245 + z16246 = x16246 + z16247 = x16247 + z16248 = x16248 + z16249 = x16249 + z16250 = x16250 + z16251 = x16251 + z16252 = x16252 + z16253 = x16253 + z16254 = x16254 + z16255 = x16255 + z16256 = x16256 + z16257 = x16257 + z16258 = x16258 + z16259 = x16259 + z16260 = x16260 + z16261 = x16261 + z16262 = x16262 + z16263 = x16263 + z16264 = x16264 + z16265 = x16265 + z16266 = x16266 + z16267 = x16267 + z16268 = x16268 + z16269 = x16269 + z16270 = x16270 + z16271 = x16271 + z16272 = x16272 + z16273 = x16273 + z16274 = x16274 + z16275 = x16275 + z16276 = x16276 + z16277 = x16277 + z16278 = x16278 + z16279 = x16279 + z16280 = x16280 + z16281 = x16281 + z16282 = x16282 + z16283 = x16283 + z16284 = x16284 + z16285 = x16285 + z16286 = x16286 + z16287 = x16287 + z16288 = x16288 + z16289 = x16289 + z16290 = x16290 + z16291 = x16291 + z16292 = x16292 + z16293 = x16293 + z16294 = x16294 + z16295 = x16295 + z16296 = x16296 + z16297 = x16297 + z16298 = x16298 + z16299 = x16299 + z16300 = x16300 + z16301 = x16301 + z16302 = x16302 + z16303 = x16303 + z16304 = x16304 + z16305 = x16305 + z16306 = x16306 + z16307 = x16307 + z16308 = x16308 + z16309 = x16309 + z16310 = x16310 + z16311 = x16311 + z16312 = x16312 + z16313 = x16313 + z16314 = x16314 + z16315 = x16315 + z16316 = x16316 + z16317 = x16317 + z16318 = x16318 + z16319 = x16319 + z16320 = x16320 + z16321 = x16321 + z16322 = x16322 + z16323 = x16323 + z16324 = x16324 + z16325 = x16325 + z16326 = x16326 + z16327 = x16327 + z16328 = x16328 + z16329 = x16329 + z16330 = x16330 + z16331 = x16331 + z16332 = x16332 + z16333 = x16333 + z16334 = x16334 + z16335 = x16335 + z16336 = x16336 + z16337 = x16337 + z16338 = x16338 + z16339 = x16339 + z16340 = x16340 + z16341 = x16341 + z16342 = x16342 + z16343 = x16343 + z16344 = x16344 + z16345 = x16345 + z16346 = x16346 + z16347 = x16347 + z16348 = x16348 + z16349 = x16349 + z16350 = x16350 + z16351 = x16351 + z16352 = x16352 + z16353 = x16353 + z16354 = x16354 + z16355 = x16355 + z16356 = x16356 + z16357 = x16357 + z16358 = x16358 + z16359 = x16359 + z16360 = x16360 + z16361 = x16361 + z16362 = x16362 + z16363 = x16363 + z16364 = x16364 + z16365 = x16365 + z16366 = x16366 + z16367 = x16367 + z16368 = x16368 + z16369 = x16369 + z16370 = x16370 + z16371 = x16371 + z16372 = x16372 + z16373 = x16373 + z16374 = x16374 + z16375 = x16375 + z16376 = x16376 + z16377 = x16377 + z16378 = x16378 + z16379 = x16379 + z16380 = x16380 + z16381 = x16381 + z16382 = x16382 + z16383 = x16383 + z16384 = x16384 + z16385 = x16385 + z16386 = x16386 + z16387 = x16387 + z16388 = x16388 + z16389 = x16389 + z16390 = x16390 + z16391 = x16391 + z16392 = x16392 + z16393 = x16393 + z16394 = x16394 + z16395 = x16395 + z16396 = x16396 + z16397 = x16397 + z16398 = x16398 + z16399 = x16399 + z16400 = x16400 + z16401 = x16401 + z16402 = x16402 + z16403 = x16403 + z16404 = x16404 + z16405 = x16405 + z16406 = x16406 + z16407 = x16407 + z16408 = x16408 + z16409 = x16409 + z16410 = x16410 + z16411 = x16411 + z16412 = x16412 + z16413 = x16413 + z16414 = x16414 + z16415 = x16415 + z16416 = x16416 + z16417 = x16417 + z16418 = x16418 + z16419 = x16419 + z16420 = x16420 + z16421 = x16421 + z16422 = x16422 + z16423 = x16423 + z16424 = x16424 + z16425 = x16425 + z16426 = x16426 + z16427 = x16427 + z16428 = x16428 + z16429 = x16429 + z16430 = x16430 + z16431 = x16431 + z16432 = x16432 + z16433 = x16433 + z16434 = x16434 + z16435 = x16435 + z16436 = x16436 + z16437 = x16437 + z16438 = x16438 + z16439 = x16439 + z16440 = x16440 + z16441 = x16441 + z16442 = x16442 + z16443 = x16443 + z16444 = x16444 + z16445 = x16445 + z16446 = x16446 + z16447 = x16447 + z16448 = x16448 + z16449 = x16449 + z16450 = x16450 + z16451 = x16451 + z16452 = x16452 + z16453 = x16453 + z16454 = x16454 + z16455 = x16455 + z16456 = x16456 + z16457 = x16457 + z16458 = x16458 + z16459 = x16459 + z16460 = x16460 + z16461 = x16461 + z16462 = x16462 + z16463 = x16463 + z16464 = x16464 + z16465 = x16465 + z16466 = x16466 + z16467 = x16467 + z16468 = x16468 + z16469 = x16469 + z16470 = x16470 + z16471 = x16471 + z16472 = x16472 + z16473 = x16473 + z16474 = x16474 + z16475 = x16475 + z16476 = x16476 + z16477 = x16477 + z16478 = x16478 + z16479 = x16479 + z16480 = x16480 } -- diff -- # indent-heuristic: true @@ -11,11 +11,16491 @@ package main -var z [1 << 17]byte +// seq 1 16480 | sed 's/.*/var z& [1 << 17]byte/' +var z1 [1 << 17]byte +var z2 [1 << 17]byte +var z3 [1 << 17]byte +var z4 [1 << 17]byte +var z5 [1 << 17]byte +var z6 [1 << 17]byte +var z7 [1 << 17]byte +var z8 [1 << 17]byte +var z9 [1 << 17]byte +var z10 [1 << 17]byte +var z11 [1 << 17]byte +var z12 [1 << 17]byte +var z13 [1 << 17]byte +var z14 [1 << 17]byte +var z15 [1 << 17]byte +var z16 [1 << 17]byte +var z17 [1 << 17]byte +var z18 [1 << 17]byte +var z19 [1 << 17]byte +var z20 [1 << 17]byte +var z21 [1 << 17]byte +var z22 [1 << 17]byte +var z23 [1 << 17]byte +var z24 [1 << 17]byte +var z25 [1 << 17]byte +var z26 [1 << 17]byte +var z27 [1 << 17]byte +var z28 [1 << 17]byte +var z29 [1 << 17]byte +var z30 [1 << 17]byte +var z31 [1 << 17]byte +var z32 [1 << 17]byte +var z33 [1 << 17]byte +var z34 [1 << 17]byte +var z35 [1 << 17]byte +var z36 [1 << 17]byte +var z37 [1 << 17]byte +var z38 [1 << 17]byte +var z39 [1 << 17]byte +var z40 [1 << 17]byte +var z41 [1 << 17]byte +var z42 [1 << 17]byte +var z43 [1 << 17]byte +var z44 [1 << 17]byte +var z45 [1 << 17]byte +var z46 [1 << 17]byte +var z47 [1 << 17]byte +var z48 [1 << 17]byte +var z49 [1 << 17]byte +var z50 [1 << 17]byte +var z51 [1 << 17]byte +var z52 [1 << 17]byte +var z53 [1 << 17]byte +var z54 [1 << 17]byte +var z55 [1 << 17]byte +var z56 [1 << 17]byte +var z57 [1 << 17]byte +var z58 [1 << 17]byte +var z59 [1 << 17]byte +var z60 [1 << 17]byte +var z61 [1 << 17]byte +var z62 [1 << 17]byte +var z63 [1 << 17]byte +var z64 [1 << 17]byte +var z65 [1 << 17]byte +var z66 [1 << 17]byte +var z67 [1 << 17]byte +var z68 [1 << 17]byte +var z69 [1 << 17]byte +var z70 [1 << 17]byte +var z71 [1 << 17]byte +var z72 [1 << 17]byte +var z73 [1 << 17]byte +var z74 [1 << 17]byte +var z75 [1 << 17]byte +var z76 [1 << 17]byte +var z77 [1 << 17]byte +var z78 [1 << 17]byte +var z79 [1 << 17]byte +var z80 [1 << 17]byte +var z81 [1 << 17]byte +var z82 [1 << 17]byte +var z83 [1 << 17]byte +var z84 [1 << 17]byte +var z85 [1 << 17]byte +var z86 [1 << 17]byte +var z87 [1 << 17]byte +var z88 [1 << 17]byte +var z89 [1 << 17]byte +var z90 [1 << 17]byte +var z91 [1 << 17]byte +var z92 [1 << 17]byte +var z93 [1 << 17]byte +var z94 [1 << 17]byte +var z95 [1 << 17]byte +var z96 [1 << 17]byte +var z97 [1 << 17]byte +var z98 [1 << 17]byte +var z99 [1 << 17]byte +var z100 [1 << 17]byte +var z101 [1 << 17]byte +var z102 [1 << 17]byte +var z103 [1 << 17]byte +var z104 [1 << 17]byte +var z105 [1 << 17]byte +var z106 [1 << 17]byte +var z107 [1 << 17]byte +var z108 [1 << 17]byte +var z109 [1 << 17]byte +var z110 [1 << 17]byte +var z111 [1 << 17]byte +var z112 [1 << 17]byte +var z113 [1 << 17]byte +var z114 [1 << 17]byte +var z115 [1 << 17]byte +var z116 [1 << 17]byte +var z117 [1 << 17]byte +var z118 [1 << 17]byte +var z119 [1 << 17]byte +var z120 [1 << 17]byte +var z121 [1 << 17]byte +var z122 [1 << 17]byte +var z123 [1 << 17]byte +var z124 [1 << 17]byte +var z125 [1 << 17]byte +var z126 [1 << 17]byte +var z127 [1 << 17]byte +var z128 [1 << 17]byte +var z129 [1 << 17]byte +var z130 [1 << 17]byte +var z131 [1 << 17]byte +var z132 [1 << 17]byte +var z133 [1 << 17]byte +var z134 [1 << 17]byte +var z135 [1 << 17]byte +var z136 [1 << 17]byte +var z137 [1 << 17]byte +var z138 [1 << 17]byte +var z139 [1 << 17]byte +var z140 [1 << 17]byte +var z141 [1 << 17]byte +var z142 [1 << 17]byte +var z143 [1 << 17]byte +var z144 [1 << 17]byte +var z145 [1 << 17]byte +var z146 [1 << 17]byte +var z147 [1 << 17]byte +var z148 [1 << 17]byte +var z149 [1 << 17]byte +var z150 [1 << 17]byte +var z151 [1 << 17]byte +var z152 [1 << 17]byte +var z153 [1 << 17]byte +var z154 [1 << 17]byte +var z155 [1 << 17]byte +var z156 [1 << 17]byte +var z157 [1 << 17]byte +var z158 [1 << 17]byte +var z159 [1 << 17]byte +var z160 [1 << 17]byte +var z161 [1 << 17]byte +var z162 [1 << 17]byte +var z163 [1 << 17]byte +var z164 [1 << 17]byte +var z165 [1 << 17]byte +var z166 [1 << 17]byte +var z167 [1 << 17]byte +var z168 [1 << 17]byte +var z169 [1 << 17]byte +var z170 [1 << 17]byte +var z171 [1 << 17]byte +var z172 [1 << 17]byte +var z173 [1 << 17]byte +var z174 [1 << 17]byte +var z175 [1 << 17]byte +var z176 [1 << 17]byte +var z177 [1 << 17]byte +var z178 [1 << 17]byte +var z179 [1 << 17]byte +var z180 [1 << 17]byte +var z181 [1 << 17]byte +var z182 [1 << 17]byte +var z183 [1 << 17]byte +var z184 [1 << 17]byte +var z185 [1 << 17]byte +var z186 [1 << 17]byte +var z187 [1 << 17]byte +var z188 [1 << 17]byte +var z189 [1 << 17]byte +var z190 [1 << 17]byte +var z191 [1 << 17]byte +var z192 [1 << 17]byte +var z193 [1 << 17]byte +var z194 [1 << 17]byte +var z195 [1 << 17]byte +var z196 [1 << 17]byte +var z197 [1 << 17]byte +var z198 [1 << 17]byte +var z199 [1 << 17]byte +var z200 [1 << 17]byte +var z201 [1 << 17]byte +var z202 [1 << 17]byte +var z203 [1 << 17]byte +var z204 [1 << 17]byte +var z205 [1 << 17]byte +var z206 [1 << 17]byte +var z207 [1 << 17]byte +var z208 [1 << 17]byte +var z209 [1 << 17]byte +var z210 [1 << 17]byte +var z211 [1 << 17]byte +var z212 [1 << 17]byte +var z213 [1 << 17]byte +var z214 [1 << 17]byte +var z215 [1 << 17]byte +var z216 [1 << 17]byte +var z217 [1 << 17]byte +var z218 [1 << 17]byte +var z219 [1 << 17]byte +var z220 [1 << 17]byte +var z221 [1 << 17]byte +var z222 [1 << 17]byte +var z223 [1 << 17]byte +var z224 [1 << 17]byte +var z225 [1 << 17]byte +var z226 [1 << 17]byte +var z227 [1 << 17]byte +var z228 [1 << 17]byte +var z229 [1 << 17]byte +var z230 [1 << 17]byte +var z231 [1 << 17]byte +var z232 [1 << 17]byte +var z233 [1 << 17]byte +var z234 [1 << 17]byte +var z235 [1 << 17]byte +var z236 [1 << 17]byte +var z237 [1 << 17]byte +var z238 [1 << 17]byte +var z239 [1 << 17]byte +var z240 [1 << 17]byte +var z241 [1 << 17]byte +var z242 [1 << 17]byte +var z243 [1 << 17]byte +var z244 [1 << 17]byte +var z245 [1 << 17]byte +var z246 [1 << 17]byte +var z247 [1 << 17]byte +var z248 [1 << 17]byte +var z249 [1 << 17]byte +var z250 [1 << 17]byte +var z251 [1 << 17]byte +var z252 [1 << 17]byte +var z253 [1 << 17]byte +var z254 [1 << 17]byte +var z255 [1 << 17]byte +var z256 [1 << 17]byte +var z257 [1 << 17]byte +var z258 [1 << 17]byte +var z259 [1 << 17]byte +var z260 [1 << 17]byte +var z261 [1 << 17]byte +var z262 [1 << 17]byte +var z263 [1 << 17]byte +var z264 [1 << 17]byte +var z265 [1 << 17]byte +var z266 [1 << 17]byte +var z267 [1 << 17]byte +var z268 [1 << 17]byte +var z269 [1 << 17]byte +var z270 [1 << 17]byte +var z271 [1 << 17]byte +var z272 [1 << 17]byte +var z273 [1 << 17]byte +var z274 [1 << 17]byte +var z275 [1 << 17]byte +var z276 [1 << 17]byte +var z277 [1 << 17]byte +var z278 [1 << 17]byte +var z279 [1 << 17]byte +var z280 [1 << 17]byte +var z281 [1 << 17]byte +var z282 [1 << 17]byte +var z283 [1 << 17]byte +var z284 [1 << 17]byte +var z285 [1 << 17]byte +var z286 [1 << 17]byte +var z287 [1 << 17]byte +var z288 [1 << 17]byte +var z289 [1 << 17]byte +var z290 [1 << 17]byte +var z291 [1 << 17]byte +var z292 [1 << 17]byte +var z293 [1 << 17]byte +var z294 [1 << 17]byte +var z295 [1 << 17]byte +var z296 [1 << 17]byte +var z297 [1 << 17]byte +var z298 [1 << 17]byte +var z299 [1 << 17]byte +var z300 [1 << 17]byte +var z301 [1 << 17]byte +var z302 [1 << 17]byte +var z303 [1 << 17]byte +var z304 [1 << 17]byte +var z305 [1 << 17]byte +var z306 [1 << 17]byte +var z307 [1 << 17]byte +var z308 [1 << 17]byte +var z309 [1 << 17]byte +var z310 [1 << 17]byte +var z311 [1 << 17]byte +var z312 [1 << 17]byte +var z313 [1 << 17]byte +var z314 [1 << 17]byte +var z315 [1 << 17]byte +var z316 [1 << 17]byte +var z317 [1 << 17]byte +var z318 [1 << 17]byte +var z319 [1 << 17]byte +var z320 [1 << 17]byte +var z321 [1 << 17]byte +var z322 [1 << 17]byte +var z323 [1 << 17]byte +var z324 [1 << 17]byte +var z325 [1 << 17]byte +var z326 [1 << 17]byte +var z327 [1 << 17]byte +var z328 [1 << 17]byte +var z329 [1 << 17]byte +var z330 [1 << 17]byte +var z331 [1 << 17]byte +var z332 [1 << 17]byte +var z333 [1 << 17]byte +var z334 [1 << 17]byte +var z335 [1 << 17]byte +var z336 [1 << 17]byte +var z337 [1 << 17]byte +var z338 [1 << 17]byte +var z339 [1 << 17]byte +var z340 [1 << 17]byte +var z341 [1 << 17]byte +var z342 [1 << 17]byte +var z343 [1 << 17]byte +var z344 [1 << 17]byte +var z345 [1 << 17]byte +var z346 [1 << 17]byte +var z347 [1 << 17]byte +var z348 [1 << 17]byte +var z349 [1 << 17]byte +var z350 [1 << 17]byte +var z351 [1 << 17]byte +var z352 [1 << 17]byte +var z353 [1 << 17]byte +var z354 [1 << 17]byte +var z355 [1 << 17]byte +var z356 [1 << 17]byte +var z357 [1 << 17]byte +var z358 [1 << 17]byte +var z359 [1 << 17]byte +var z360 [1 << 17]byte +var z361 [1 << 17]byte +var z362 [1 << 17]byte +var z363 [1 << 17]byte +var z364 [1 << 17]byte +var z365 [1 << 17]byte +var z366 [1 << 17]byte +var z367 [1 << 17]byte +var z368 [1 << 17]byte +var z369 [1 << 17]byte +var z370 [1 << 17]byte +var z371 [1 << 17]byte +var z372 [1 << 17]byte +var z373 [1 << 17]byte +var z374 [1 << 17]byte +var z375 [1 << 17]byte +var z376 [1 << 17]byte +var z377 [1 << 17]byte +var z378 [1 << 17]byte +var z379 [1 << 17]byte +var z380 [1 << 17]byte +var z381 [1 << 17]byte +var z382 [1 << 17]byte +var z383 [1 << 17]byte +var z384 [1 << 17]byte +var z385 [1 << 17]byte +var z386 [1 << 17]byte +var z387 [1 << 17]byte +var z388 [1 << 17]byte +var z389 [1 << 17]byte +var z390 [1 << 17]byte +var z391 [1 << 17]byte +var z392 [1 << 17]byte +var z393 [1 << 17]byte +var z394 [1 << 17]byte +var z395 [1 << 17]byte +var z396 [1 << 17]byte +var z397 [1 << 17]byte +var z398 [1 << 17]byte +var z399 [1 << 17]byte +var z400 [1 << 17]byte +var z401 [1 << 17]byte +var z402 [1 << 17]byte +var z403 [1 << 17]byte +var z404 [1 << 17]byte +var z405 [1 << 17]byte +var z406 [1 << 17]byte +var z407 [1 << 17]byte +var z408 [1 << 17]byte +var z409 [1 << 17]byte +var z410 [1 << 17]byte +var z411 [1 << 17]byte +var z412 [1 << 17]byte +var z413 [1 << 17]byte +var z414 [1 << 17]byte +var z415 [1 << 17]byte +var z416 [1 << 17]byte +var z417 [1 << 17]byte +var z418 [1 << 17]byte +var z419 [1 << 17]byte +var z420 [1 << 17]byte +var z421 [1 << 17]byte +var z422 [1 << 17]byte +var z423 [1 << 17]byte +var z424 [1 << 17]byte +var z425 [1 << 17]byte +var z426 [1 << 17]byte +var z427 [1 << 17]byte +var z428 [1 << 17]byte +var z429 [1 << 17]byte +var z430 [1 << 17]byte +var z431 [1 << 17]byte +var z432 [1 << 17]byte +var z433 [1 << 17]byte +var z434 [1 << 17]byte +var z435 [1 << 17]byte +var z436 [1 << 17]byte +var z437 [1 << 17]byte +var z438 [1 << 17]byte +var z439 [1 << 17]byte +var z440 [1 << 17]byte +var z441 [1 << 17]byte +var z442 [1 << 17]byte +var z443 [1 << 17]byte +var z444 [1 << 17]byte +var z445 [1 << 17]byte +var z446 [1 << 17]byte +var z447 [1 << 17]byte +var z448 [1 << 17]byte +var z449 [1 << 17]byte +var z450 [1 << 17]byte +var z451 [1 << 17]byte +var z452 [1 << 17]byte +var z453 [1 << 17]byte +var z454 [1 << 17]byte +var z455 [1 << 17]byte +var z456 [1 << 17]byte +var z457 [1 << 17]byte +var z458 [1 << 17]byte +var z459 [1 << 17]byte +var z460 [1 << 17]byte +var z461 [1 << 17]byte +var z462 [1 << 17]byte +var z463 [1 << 17]byte +var z464 [1 << 17]byte +var z465 [1 << 17]byte +var z466 [1 << 17]byte +var z467 [1 << 17]byte +var z468 [1 << 17]byte +var z469 [1 << 17]byte +var z470 [1 << 17]byte +var z471 [1 << 17]byte +var z472 [1 << 17]byte +var z473 [1 << 17]byte +var z474 [1 << 17]byte +var z475 [1 << 17]byte +var z476 [1 << 17]byte +var z477 [1 << 17]byte +var z478 [1 << 17]byte +var z479 [1 << 17]byte +var z480 [1 << 17]byte +var z481 [1 << 17]byte +var z482 [1 << 17]byte +var z483 [1 << 17]byte +var z484 [1 << 17]byte +var z485 [1 << 17]byte +var z486 [1 << 17]byte +var z487 [1 << 17]byte +var z488 [1 << 17]byte +var z489 [1 << 17]byte +var z490 [1 << 17]byte +var z491 [1 << 17]byte +var z492 [1 << 17]byte +var z493 [1 << 17]byte +var z494 [1 << 17]byte +var z495 [1 << 17]byte +var z496 [1 << 17]byte +var z497 [1 << 17]byte +var z498 [1 << 17]byte +var z499 [1 << 17]byte +var z500 [1 << 17]byte +var z501 [1 << 17]byte +var z502 [1 << 17]byte +var z503 [1 << 17]byte +var z504 [1 << 17]byte +var z505 [1 << 17]byte +var z506 [1 << 17]byte +var z507 [1 << 17]byte +var z508 [1 << 17]byte +var z509 [1 << 17]byte +var z510 [1 << 17]byte +var z511 [1 << 17]byte +var z512 [1 << 17]byte +var z513 [1 << 17]byte +var z514 [1 << 17]byte +var z515 [1 << 17]byte +var z516 [1 << 17]byte +var z517 [1 << 17]byte +var z518 [1 << 17]byte +var z519 [1 << 17]byte +var z520 [1 << 17]byte +var z521 [1 << 17]byte +var z522 [1 << 17]byte +var z523 [1 << 17]byte +var z524 [1 << 17]byte +var z525 [1 << 17]byte +var z526 [1 << 17]byte +var z527 [1 << 17]byte +var z528 [1 << 17]byte +var z529 [1 << 17]byte +var z530 [1 << 17]byte +var z531 [1 << 17]byte +var z532 [1 << 17]byte +var z533 [1 << 17]byte +var z534 [1 << 17]byte +var z535 [1 << 17]byte +var z536 [1 << 17]byte +var z537 [1 << 17]byte +var z538 [1 << 17]byte +var z539 [1 << 17]byte +var z540 [1 << 17]byte +var z541 [1 << 17]byte +var z542 [1 << 17]byte +var z543 [1 << 17]byte +var z544 [1 << 17]byte +var z545 [1 << 17]byte +var z546 [1 << 17]byte +var z547 [1 << 17]byte +var z548 [1 << 17]byte +var z549 [1 << 17]byte +var z550 [1 << 17]byte +var z551 [1 << 17]byte +var z552 [1 << 17]byte +var z553 [1 << 17]byte +var z554 [1 << 17]byte +var z555 [1 << 17]byte +var z556 [1 << 17]byte +var z557 [1 << 17]byte +var z558 [1 << 17]byte +var z559 [1 << 17]byte +var z560 [1 << 17]byte +var z561 [1 << 17]byte +var z562 [1 << 17]byte +var z563 [1 << 17]byte +var z564 [1 << 17]byte +var z565 [1 << 17]byte +var z566 [1 << 17]byte +var z567 [1 << 17]byte +var z568 [1 << 17]byte +var z569 [1 << 17]byte +var z570 [1 << 17]byte +var z571 [1 << 17]byte +var z572 [1 << 17]byte +var z573 [1 << 17]byte +var z574 [1 << 17]byte +var z575 [1 << 17]byte +var z576 [1 << 17]byte +var z577 [1 << 17]byte +var z578 [1 << 17]byte +var z579 [1 << 17]byte +var z580 [1 << 17]byte +var z581 [1 << 17]byte +var z582 [1 << 17]byte +var z583 [1 << 17]byte +var z584 [1 << 17]byte +var z585 [1 << 17]byte +var z586 [1 << 17]byte +var z587 [1 << 17]byte +var z588 [1 << 17]byte +var z589 [1 << 17]byte +var z590 [1 << 17]byte +var z591 [1 << 17]byte +var z592 [1 << 17]byte +var z593 [1 << 17]byte +var z594 [1 << 17]byte +var z595 [1 << 17]byte +var z596 [1 << 17]byte +var z597 [1 << 17]byte +var z598 [1 << 17]byte +var z599 [1 << 17]byte +var z600 [1 << 17]byte +var z601 [1 << 17]byte +var z602 [1 << 17]byte +var z603 [1 << 17]byte +var z604 [1 << 17]byte +var z605 [1 << 17]byte +var z606 [1 << 17]byte +var z607 [1 << 17]byte +var z608 [1 << 17]byte +var z609 [1 << 17]byte +var z610 [1 << 17]byte +var z611 [1 << 17]byte +var z612 [1 << 17]byte +var z613 [1 << 17]byte +var z614 [1 << 17]byte +var z615 [1 << 17]byte +var z616 [1 << 17]byte +var z617 [1 << 17]byte +var z618 [1 << 17]byte +var z619 [1 << 17]byte +var z620 [1 << 17]byte +var z621 [1 << 17]byte +var z622 [1 << 17]byte +var z623 [1 << 17]byte +var z624 [1 << 17]byte +var z625 [1 << 17]byte +var z626 [1 << 17]byte +var z627 [1 << 17]byte +var z628 [1 << 17]byte +var z629 [1 << 17]byte +var z630 [1 << 17]byte +var z631 [1 << 17]byte +var z632 [1 << 17]byte +var z633 [1 << 17]byte +var z634 [1 << 17]byte +var z635 [1 << 17]byte +var z636 [1 << 17]byte +var z637 [1 << 17]byte +var z638 [1 << 17]byte +var z639 [1 << 17]byte +var z640 [1 << 17]byte +var z641 [1 << 17]byte +var z642 [1 << 17]byte +var z643 [1 << 17]byte +var z644 [1 << 17]byte +var z645 [1 << 17]byte +var z646 [1 << 17]byte +var z647 [1 << 17]byte +var z648 [1 << 17]byte +var z649 [1 << 17]byte +var z650 [1 << 17]byte +var z651 [1 << 17]byte +var z652 [1 << 17]byte +var z653 [1 << 17]byte +var z654 [1 << 17]byte +var z655 [1 << 17]byte +var z656 [1 << 17]byte +var z657 [1 << 17]byte +var z658 [1 << 17]byte +var z659 [1 << 17]byte +var z660 [1 << 17]byte +var z661 [1 << 17]byte +var z662 [1 << 17]byte +var z663 [1 << 17]byte +var z664 [1 << 17]byte +var z665 [1 << 17]byte +var z666 [1 << 17]byte +var z667 [1 << 17]byte +var z668 [1 << 17]byte +var z669 [1 << 17]byte +var z670 [1 << 17]byte +var z671 [1 << 17]byte +var z672 [1 << 17]byte +var z673 [1 << 17]byte +var z674 [1 << 17]byte +var z675 [1 << 17]byte +var z676 [1 << 17]byte +var z677 [1 << 17]byte +var z678 [1 << 17]byte +var z679 [1 << 17]byte +var z680 [1 << 17]byte +var z681 [1 << 17]byte +var z682 [1 << 17]byte +var z683 [1 << 17]byte +var z684 [1 << 17]byte +var z685 [1 << 17]byte +var z686 [1 << 17]byte +var z687 [1 << 17]byte +var z688 [1 << 17]byte +var z689 [1 << 17]byte +var z690 [1 << 17]byte +var z691 [1 << 17]byte +var z692 [1 << 17]byte +var z693 [1 << 17]byte +var z694 [1 << 17]byte +var z695 [1 << 17]byte +var z696 [1 << 17]byte +var z697 [1 << 17]byte +var z698 [1 << 17]byte +var z699 [1 << 17]byte +var z700 [1 << 17]byte +var z701 [1 << 17]byte +var z702 [1 << 17]byte +var z703 [1 << 17]byte +var z704 [1 << 17]byte +var z705 [1 << 17]byte +var z706 [1 << 17]byte +var z707 [1 << 17]byte +var z708 [1 << 17]byte +var z709 [1 << 17]byte +var z710 [1 << 17]byte +var z711 [1 << 17]byte +var z712 [1 << 17]byte +var z713 [1 << 17]byte +var z714 [1 << 17]byte +var z715 [1 << 17]byte +var z716 [1 << 17]byte +var z717 [1 << 17]byte +var z718 [1 << 17]byte +var z719 [1 << 17]byte +var z720 [1 << 17]byte +var z721 [1 << 17]byte +var z722 [1 << 17]byte +var z723 [1 << 17]byte +var z724 [1 << 17]byte +var z725 [1 << 17]byte +var z726 [1 << 17]byte +var z727 [1 << 17]byte +var z728 [1 << 17]byte +var z729 [1 << 17]byte +var z730 [1 << 17]byte +var z731 [1 << 17]byte +var z732 [1 << 17]byte +var z733 [1 << 17]byte +var z734 [1 << 17]byte +var z735 [1 << 17]byte +var z736 [1 << 17]byte +var z737 [1 << 17]byte +var z738 [1 << 17]byte +var z739 [1 << 17]byte +var z740 [1 << 17]byte +var z741 [1 << 17]byte +var z742 [1 << 17]byte +var z743 [1 << 17]byte +var z744 [1 << 17]byte +var z745 [1 << 17]byte +var z746 [1 << 17]byte +var z747 [1 << 17]byte +var z748 [1 << 17]byte +var z749 [1 << 17]byte +var z750 [1 << 17]byte +var z751 [1 << 17]byte +var z752 [1 << 17]byte +var z753 [1 << 17]byte +var z754 [1 << 17]byte +var z755 [1 << 17]byte +var z756 [1 << 17]byte +var z757 [1 << 17]byte +var z758 [1 << 17]byte +var z759 [1 << 17]byte +var z760 [1 << 17]byte +var z761 [1 << 17]byte +var z762 [1 << 17]byte +var z763 [1 << 17]byte +var z764 [1 << 17]byte +var z765 [1 << 17]byte +var z766 [1 << 17]byte +var z767 [1 << 17]byte +var z768 [1 << 17]byte +var z769 [1 << 17]byte +var z770 [1 << 17]byte +var z771 [1 << 17]byte +var z772 [1 << 17]byte +var z773 [1 << 17]byte +var z774 [1 << 17]byte +var z775 [1 << 17]byte +var z776 [1 << 17]byte +var z777 [1 << 17]byte +var z778 [1 << 17]byte +var z779 [1 << 17]byte +var z780 [1 << 17]byte +var z781 [1 << 17]byte +var z782 [1 << 17]byte +var z783 [1 << 17]byte +var z784 [1 << 17]byte +var z785 [1 << 17]byte +var z786 [1 << 17]byte +var z787 [1 << 17]byte +var z788 [1 << 17]byte +var z789 [1 << 17]byte +var z790 [1 << 17]byte +var z791 [1 << 17]byte +var z792 [1 << 17]byte +var z793 [1 << 17]byte +var z794 [1 << 17]byte +var z795 [1 << 17]byte +var z796 [1 << 17]byte +var z797 [1 << 17]byte +var z798 [1 << 17]byte +var z799 [1 << 17]byte +var z800 [1 << 17]byte +var z801 [1 << 17]byte +var z802 [1 << 17]byte +var z803 [1 << 17]byte +var z804 [1 << 17]byte +var z805 [1 << 17]byte +var z806 [1 << 17]byte +var z807 [1 << 17]byte +var z808 [1 << 17]byte +var z809 [1 << 17]byte +var z810 [1 << 17]byte +var z811 [1 << 17]byte +var z812 [1 << 17]byte +var z813 [1 << 17]byte +var z814 [1 << 17]byte +var z815 [1 << 17]byte +var z816 [1 << 17]byte +var z817 [1 << 17]byte +var z818 [1 << 17]byte +var z819 [1 << 17]byte +var z820 [1 << 17]byte +var z821 [1 << 17]byte +var z822 [1 << 17]byte +var z823 [1 << 17]byte +var z824 [1 << 17]byte +var z825 [1 << 17]byte +var z826 [1 << 17]byte +var z827 [1 << 17]byte +var z828 [1 << 17]byte +var z829 [1 << 17]byte +var z830 [1 << 17]byte +var z831 [1 << 17]byte +var z832 [1 << 17]byte +var z833 [1 << 17]byte +var z834 [1 << 17]byte +var z835 [1 << 17]byte +var z836 [1 << 17]byte +var z837 [1 << 17]byte +var z838 [1 << 17]byte +var z839 [1 << 17]byte +var z840 [1 << 17]byte +var z841 [1 << 17]byte +var z842 [1 << 17]byte +var z843 [1 << 17]byte +var z844 [1 << 17]byte +var z845 [1 << 17]byte +var z846 [1 << 17]byte +var z847 [1 << 17]byte +var z848 [1 << 17]byte +var z849 [1 << 17]byte +var z850 [1 << 17]byte +var z851 [1 << 17]byte +var z852 [1 << 17]byte +var z853 [1 << 17]byte +var z854 [1 << 17]byte +var z855 [1 << 17]byte +var z856 [1 << 17]byte +var z857 [1 << 17]byte +var z858 [1 << 17]byte +var z859 [1 << 17]byte +var z860 [1 << 17]byte +var z861 [1 << 17]byte +var z862 [1 << 17]byte +var z863 [1 << 17]byte +var z864 [1 << 17]byte +var z865 [1 << 17]byte +var z866 [1 << 17]byte +var z867 [1 << 17]byte +var z868 [1 << 17]byte +var z869 [1 << 17]byte +var z870 [1 << 17]byte +var z871 [1 << 17]byte +var z872 [1 << 17]byte +var z873 [1 << 17]byte +var z874 [1 << 17]byte +var z875 [1 << 17]byte +var z876 [1 << 17]byte +var z877 [1 << 17]byte +var z878 [1 << 17]byte +var z879 [1 << 17]byte +var z880 [1 << 17]byte +var z881 [1 << 17]byte +var z882 [1 << 17]byte +var z883 [1 << 17]byte +var z884 [1 << 17]byte +var z885 [1 << 17]byte +var z886 [1 << 17]byte +var z887 [1 << 17]byte +var z888 [1 << 17]byte +var z889 [1 << 17]byte +var z890 [1 << 17]byte +var z891 [1 << 17]byte +var z892 [1 << 17]byte +var z893 [1 << 17]byte +var z894 [1 << 17]byte +var z895 [1 << 17]byte +var z896 [1 << 17]byte +var z897 [1 << 17]byte +var z898 [1 << 17]byte +var z899 [1 << 17]byte +var z900 [1 << 17]byte +var z901 [1 << 17]byte +var z902 [1 << 17]byte +var z903 [1 << 17]byte +var z904 [1 << 17]byte +var z905 [1 << 17]byte +var z906 [1 << 17]byte +var z907 [1 << 17]byte +var z908 [1 << 17]byte +var z909 [1 << 17]byte +var z910 [1 << 17]byte +var z911 [1 << 17]byte +var z912 [1 << 17]byte +var z913 [1 << 17]byte +var z914 [1 << 17]byte +var z915 [1 << 17]byte +var z916 [1 << 17]byte +var z917 [1 << 17]byte +var z918 [1 << 17]byte +var z919 [1 << 17]byte +var z920 [1 << 17]byte +var z921 [1 << 17]byte +var z922 [1 << 17]byte +var z923 [1 << 17]byte +var z924 [1 << 17]byte +var z925 [1 << 17]byte +var z926 [1 << 17]byte +var z927 [1 << 17]byte +var z928 [1 << 17]byte +var z929 [1 << 17]byte +var z930 [1 << 17]byte +var z931 [1 << 17]byte +var z932 [1 << 17]byte +var z933 [1 << 17]byte +var z934 [1 << 17]byte +var z935 [1 << 17]byte +var z936 [1 << 17]byte +var z937 [1 << 17]byte +var z938 [1 << 17]byte +var z939 [1 << 17]byte +var z940 [1 << 17]byte +var z941 [1 << 17]byte +var z942 [1 << 17]byte +var z943 [1 << 17]byte +var z944 [1 << 17]byte +var z945 [1 << 17]byte +var z946 [1 << 17]byte +var z947 [1 << 17]byte +var z948 [1 << 17]byte +var z949 [1 << 17]byte +var z950 [1 << 17]byte +var z951 [1 << 17]byte +var z952 [1 << 17]byte +var z953 [1 << 17]byte +var z954 [1 << 17]byte +var z955 [1 << 17]byte +var z956 [1 << 17]byte +var z957 [1 << 17]byte +var z958 [1 << 17]byte +var z959 [1 << 17]byte +var z960 [1 << 17]byte +var z961 [1 << 17]byte +var z962 [1 << 17]byte +var z963 [1 << 17]byte +var z964 [1 << 17]byte +var z965 [1 << 17]byte +var z966 [1 << 17]byte +var z967 [1 << 17]byte +var z968 [1 << 17]byte +var z969 [1 << 17]byte +var z970 [1 << 17]byte +var z971 [1 << 17]byte +var z972 [1 << 17]byte +var z973 [1 << 17]byte +var z974 [1 << 17]byte +var z975 [1 << 17]byte +var z976 [1 << 17]byte +var z977 [1 << 17]byte +var z978 [1 << 17]byte +var z979 [1 << 17]byte +var z980 [1 << 17]byte +var z981 [1 << 17]byte +var z982 [1 << 17]byte +var z983 [1 << 17]byte +var z984 [1 << 17]byte +var z985 [1 << 17]byte +var z986 [1 << 17]byte +var z987 [1 << 17]byte +var z988 [1 << 17]byte +var z989 [1 << 17]byte +var z990 [1 << 17]byte +var z991 [1 << 17]byte +var z992 [1 << 17]byte +var z993 [1 << 17]byte +var z994 [1 << 17]byte +var z995 [1 << 17]byte +var z996 [1 << 17]byte +var z997 [1 << 17]byte +var z998 [1 << 17]byte +var z999 [1 << 17]byte +var z1000 [1 << 17]byte +var z1001 [1 << 17]byte +var z1002 [1 << 17]byte +var z1003 [1 << 17]byte +var z1004 [1 << 17]byte +var z1005 [1 << 17]byte +var z1006 [1 << 17]byte +var z1007 [1 << 17]byte +var z1008 [1 << 17]byte +var z1009 [1 << 17]byte +var z1010 [1 << 17]byte +var z1011 [1 << 17]byte +var z1012 [1 << 17]byte +var z1013 [1 << 17]byte +var z1014 [1 << 17]byte +var z1015 [1 << 17]byte +var z1016 [1 << 17]byte +var z1017 [1 << 17]byte +var z1018 [1 << 17]byte +var z1019 [1 << 17]byte +var z1020 [1 << 17]byte +var z1021 [1 << 17]byte +var z1022 [1 << 17]byte +var z1023 [1 << 17]byte +var z1024 [1 << 17]byte +var z1025 [1 << 17]byte +var z1026 [1 << 17]byte +var z1027 [1 << 17]byte +var z1028 [1 << 17]byte +var z1029 [1 << 17]byte +var z1030 [1 << 17]byte +var z1031 [1 << 17]byte +var z1032 [1 << 17]byte +var z1033 [1 << 17]byte +var z1034 [1 << 17]byte +var z1035 [1 << 17]byte +var z1036 [1 << 17]byte +var z1037 [1 << 17]byte +var z1038 [1 << 17]byte +var z1039 [1 << 17]byte +var z1040 [1 << 17]byte +var z1041 [1 << 17]byte +var z1042 [1 << 17]byte +var z1043 [1 << 17]byte +var z1044 [1 << 17]byte +var z1045 [1 << 17]byte +var z1046 [1 << 17]byte +var z1047 [1 << 17]byte +var z1048 [1 << 17]byte +var z1049 [1 << 17]byte +var z1050 [1 << 17]byte +var z1051 [1 << 17]byte +var z1052 [1 << 17]byte +var z1053 [1 << 17]byte +var z1054 [1 << 17]byte +var z1055 [1 << 17]byte +var z1056 [1 << 17]byte +var z1057 [1 << 17]byte +var z1058 [1 << 17]byte +var z1059 [1 << 17]byte +var z1060 [1 << 17]byte +var z1061 [1 << 17]byte +var z1062 [1 << 17]byte +var z1063 [1 << 17]byte +var z1064 [1 << 17]byte +var z1065 [1 << 17]byte +var z1066 [1 << 17]byte +var z1067 [1 << 17]byte +var z1068 [1 << 17]byte +var z1069 [1 << 17]byte +var z1070 [1 << 17]byte +var z1071 [1 << 17]byte +var z1072 [1 << 17]byte +var z1073 [1 << 17]byte +var z1074 [1 << 17]byte +var z1075 [1 << 17]byte +var z1076 [1 << 17]byte +var z1077 [1 << 17]byte +var z1078 [1 << 17]byte +var z1079 [1 << 17]byte +var z1080 [1 << 17]byte +var z1081 [1 << 17]byte +var z1082 [1 << 17]byte +var z1083 [1 << 17]byte +var z1084 [1 << 17]byte +var z1085 [1 << 17]byte +var z1086 [1 << 17]byte +var z1087 [1 << 17]byte +var z1088 [1 << 17]byte +var z1089 [1 << 17]byte +var z1090 [1 << 17]byte +var z1091 [1 << 17]byte +var z1092 [1 << 17]byte +var z1093 [1 << 17]byte +var z1094 [1 << 17]byte +var z1095 [1 << 17]byte +var z1096 [1 << 17]byte +var z1097 [1 << 17]byte +var z1098 [1 << 17]byte +var z1099 [1 << 17]byte +var z1100 [1 << 17]byte +var z1101 [1 << 17]byte +var z1102 [1 << 17]byte +var z1103 [1 << 17]byte +var z1104 [1 << 17]byte +var z1105 [1 << 17]byte +var z1106 [1 << 17]byte +var z1107 [1 << 17]byte +var z1108 [1 << 17]byte +var z1109 [1 << 17]byte +var z1110 [1 << 17]byte +var z1111 [1 << 17]byte +var z1112 [1 << 17]byte +var z1113 [1 << 17]byte +var z1114 [1 << 17]byte +var z1115 [1 << 17]byte +var z1116 [1 << 17]byte +var z1117 [1 << 17]byte +var z1118 [1 << 17]byte +var z1119 [1 << 17]byte +var z1120 [1 << 17]byte +var z1121 [1 << 17]byte +var z1122 [1 << 17]byte +var z1123 [1 << 17]byte +var z1124 [1 << 17]byte +var z1125 [1 << 17]byte +var z1126 [1 << 17]byte +var z1127 [1 << 17]byte +var z1128 [1 << 17]byte +var z1129 [1 << 17]byte +var z1130 [1 << 17]byte +var z1131 [1 << 17]byte +var z1132 [1 << 17]byte +var z1133 [1 << 17]byte +var z1134 [1 << 17]byte +var z1135 [1 << 17]byte +var z1136 [1 << 17]byte +var z1137 [1 << 17]byte +var z1138 [1 << 17]byte +var z1139 [1 << 17]byte +var z1140 [1 << 17]byte +var z1141 [1 << 17]byte +var z1142 [1 << 17]byte +var z1143 [1 << 17]byte +var z1144 [1 << 17]byte +var z1145 [1 << 17]byte +var z1146 [1 << 17]byte +var z1147 [1 << 17]byte +var z1148 [1 << 17]byte +var z1149 [1 << 17]byte +var z1150 [1 << 17]byte +var z1151 [1 << 17]byte +var z1152 [1 << 17]byte +var z1153 [1 << 17]byte +var z1154 [1 << 17]byte +var z1155 [1 << 17]byte +var z1156 [1 << 17]byte +var z1157 [1 << 17]byte +var z1158 [1 << 17]byte +var z1159 [1 << 17]byte +var z1160 [1 << 17]byte +var z1161 [1 << 17]byte +var z1162 [1 << 17]byte +var z1163 [1 << 17]byte +var z1164 [1 << 17]byte +var z1165 [1 << 17]byte +var z1166 [1 << 17]byte +var z1167 [1 << 17]byte +var z1168 [1 << 17]byte +var z1169 [1 << 17]byte +var z1170 [1 << 17]byte +var z1171 [1 << 17]byte +var z1172 [1 << 17]byte +var z1173 [1 << 17]byte +var z1174 [1 << 17]byte +var z1175 [1 << 17]byte +var z1176 [1 << 17]byte +var z1177 [1 << 17]byte +var z1178 [1 << 17]byte +var z1179 [1 << 17]byte +var z1180 [1 << 17]byte +var z1181 [1 << 17]byte +var z1182 [1 << 17]byte +var z1183 [1 << 17]byte +var z1184 [1 << 17]byte +var z1185 [1 << 17]byte +var z1186 [1 << 17]byte +var z1187 [1 << 17]byte +var z1188 [1 << 17]byte +var z1189 [1 << 17]byte +var z1190 [1 << 17]byte +var z1191 [1 << 17]byte +var z1192 [1 << 17]byte +var z1193 [1 << 17]byte +var z1194 [1 << 17]byte +var z1195 [1 << 17]byte +var z1196 [1 << 17]byte +var z1197 [1 << 17]byte +var z1198 [1 << 17]byte +var z1199 [1 << 17]byte +var z1200 [1 << 17]byte +var z1201 [1 << 17]byte +var z1202 [1 << 17]byte +var z1203 [1 << 17]byte +var z1204 [1 << 17]byte +var z1205 [1 << 17]byte +var z1206 [1 << 17]byte +var z1207 [1 << 17]byte +var z1208 [1 << 17]byte +var z1209 [1 << 17]byte +var z1210 [1 << 17]byte +var z1211 [1 << 17]byte +var z1212 [1 << 17]byte +var z1213 [1 << 17]byte +var z1214 [1 << 17]byte +var z1215 [1 << 17]byte +var z1216 [1 << 17]byte +var z1217 [1 << 17]byte +var z1218 [1 << 17]byte +var z1219 [1 << 17]byte +var z1220 [1 << 17]byte +var z1221 [1 << 17]byte +var z1222 [1 << 17]byte +var z1223 [1 << 17]byte +var z1224 [1 << 17]byte +var z1225 [1 << 17]byte +var z1226 [1 << 17]byte +var z1227 [1 << 17]byte +var z1228 [1 << 17]byte +var z1229 [1 << 17]byte +var z1230 [1 << 17]byte +var z1231 [1 << 17]byte +var z1232 [1 << 17]byte +var z1233 [1 << 17]byte +var z1234 [1 << 17]byte +var z1235 [1 << 17]byte +var z1236 [1 << 17]byte +var z1237 [1 << 17]byte +var z1238 [1 << 17]byte +var z1239 [1 << 17]byte +var z1240 [1 << 17]byte +var z1241 [1 << 17]byte +var z1242 [1 << 17]byte +var z1243 [1 << 17]byte +var z1244 [1 << 17]byte +var z1245 [1 << 17]byte +var z1246 [1 << 17]byte +var z1247 [1 << 17]byte +var z1248 [1 << 17]byte +var z1249 [1 << 17]byte +var z1250 [1 << 17]byte +var z1251 [1 << 17]byte +var z1252 [1 << 17]byte +var z1253 [1 << 17]byte +var z1254 [1 << 17]byte +var z1255 [1 << 17]byte +var z1256 [1 << 17]byte +var z1257 [1 << 17]byte +var z1258 [1 << 17]byte +var z1259 [1 << 17]byte +var z1260 [1 << 17]byte +var z1261 [1 << 17]byte +var z1262 [1 << 17]byte +var z1263 [1 << 17]byte +var z1264 [1 << 17]byte +var z1265 [1 << 17]byte +var z1266 [1 << 17]byte +var z1267 [1 << 17]byte +var z1268 [1 << 17]byte +var z1269 [1 << 17]byte +var z1270 [1 << 17]byte +var z1271 [1 << 17]byte +var z1272 [1 << 17]byte +var z1273 [1 << 17]byte +var z1274 [1 << 17]byte +var z1275 [1 << 17]byte +var z1276 [1 << 17]byte +var z1277 [1 << 17]byte +var z1278 [1 << 17]byte +var z1279 [1 << 17]byte +var z1280 [1 << 17]byte +var z1281 [1 << 17]byte +var z1282 [1 << 17]byte +var z1283 [1 << 17]byte +var z1284 [1 << 17]byte +var z1285 [1 << 17]byte +var z1286 [1 << 17]byte +var z1287 [1 << 17]byte +var z1288 [1 << 17]byte +var z1289 [1 << 17]byte +var z1290 [1 << 17]byte +var z1291 [1 << 17]byte +var z1292 [1 << 17]byte +var z1293 [1 << 17]byte +var z1294 [1 << 17]byte +var z1295 [1 << 17]byte +var z1296 [1 << 17]byte +var z1297 [1 << 17]byte +var z1298 [1 << 17]byte +var z1299 [1 << 17]byte +var z1300 [1 << 17]byte +var z1301 [1 << 17]byte +var z1302 [1 << 17]byte +var z1303 [1 << 17]byte +var z1304 [1 << 17]byte +var z1305 [1 << 17]byte +var z1306 [1 << 17]byte +var z1307 [1 << 17]byte +var z1308 [1 << 17]byte +var z1309 [1 << 17]byte +var z1310 [1 << 17]byte +var z1311 [1 << 17]byte +var z1312 [1 << 17]byte +var z1313 [1 << 17]byte +var z1314 [1 << 17]byte +var z1315 [1 << 17]byte +var z1316 [1 << 17]byte +var z1317 [1 << 17]byte +var z1318 [1 << 17]byte +var z1319 [1 << 17]byte +var z1320 [1 << 17]byte +var z1321 [1 << 17]byte +var z1322 [1 << 17]byte +var z1323 [1 << 17]byte +var z1324 [1 << 17]byte +var z1325 [1 << 17]byte +var z1326 [1 << 17]byte +var z1327 [1 << 17]byte +var z1328 [1 << 17]byte +var z1329 [1 << 17]byte +var z1330 [1 << 17]byte +var z1331 [1 << 17]byte +var z1332 [1 << 17]byte +var z1333 [1 << 17]byte +var z1334 [1 << 17]byte +var z1335 [1 << 17]byte +var z1336 [1 << 17]byte +var z1337 [1 << 17]byte +var z1338 [1 << 17]byte +var z1339 [1 << 17]byte +var z1340 [1 << 17]byte +var z1341 [1 << 17]byte +var z1342 [1 << 17]byte +var z1343 [1 << 17]byte +var z1344 [1 << 17]byte +var z1345 [1 << 17]byte +var z1346 [1 << 17]byte +var z1347 [1 << 17]byte +var z1348 [1 << 17]byte +var z1349 [1 << 17]byte +var z1350 [1 << 17]byte +var z1351 [1 << 17]byte +var z1352 [1 << 17]byte +var z1353 [1 << 17]byte +var z1354 [1 << 17]byte +var z1355 [1 << 17]byte +var z1356 [1 << 17]byte +var z1357 [1 << 17]byte +var z1358 [1 << 17]byte +var z1359 [1 << 17]byte +var z1360 [1 << 17]byte +var z1361 [1 << 17]byte +var z1362 [1 << 17]byte +var z1363 [1 << 17]byte +var z1364 [1 << 17]byte +var z1365 [1 << 17]byte +var z1366 [1 << 17]byte +var z1367 [1 << 17]byte +var z1368 [1 << 17]byte +var z1369 [1 << 17]byte +var z1370 [1 << 17]byte +var z1371 [1 << 17]byte +var z1372 [1 << 17]byte +var z1373 [1 << 17]byte +var z1374 [1 << 17]byte +var z1375 [1 << 17]byte +var z1376 [1 << 17]byte +var z1377 [1 << 17]byte +var z1378 [1 << 17]byte +var z1379 [1 << 17]byte +var z1380 [1 << 17]byte +var z1381 [1 << 17]byte +var z1382 [1 << 17]byte +var z1383 [1 << 17]byte +var z1384 [1 << 17]byte +var z1385 [1 << 17]byte +var z1386 [1 << 17]byte +var z1387 [1 << 17]byte +var z1388 [1 << 17]byte +var z1389 [1 << 17]byte +var z1390 [1 << 17]byte +var z1391 [1 << 17]byte +var z1392 [1 << 17]byte +var z1393 [1 << 17]byte +var z1394 [1 << 17]byte +var z1395 [1 << 17]byte +var z1396 [1 << 17]byte +var z1397 [1 << 17]byte +var z1398 [1 << 17]byte +var z1399 [1 << 17]byte +var z1400 [1 << 17]byte +var z1401 [1 << 17]byte +var z1402 [1 << 17]byte +var z1403 [1 << 17]byte +var z1404 [1 << 17]byte +var z1405 [1 << 17]byte +var z1406 [1 << 17]byte +var z1407 [1 << 17]byte +var z1408 [1 << 17]byte +var z1409 [1 << 17]byte +var z1410 [1 << 17]byte +var z1411 [1 << 17]byte +var z1412 [1 << 17]byte +var z1413 [1 << 17]byte +var z1414 [1 << 17]byte +var z1415 [1 << 17]byte +var z1416 [1 << 17]byte +var z1417 [1 << 17]byte +var z1418 [1 << 17]byte +var z1419 [1 << 17]byte +var z1420 [1 << 17]byte +var z1421 [1 << 17]byte +var z1422 [1 << 17]byte +var z1423 [1 << 17]byte +var z1424 [1 << 17]byte +var z1425 [1 << 17]byte +var z1426 [1 << 17]byte +var z1427 [1 << 17]byte +var z1428 [1 << 17]byte +var z1429 [1 << 17]byte +var z1430 [1 << 17]byte +var z1431 [1 << 17]byte +var z1432 [1 << 17]byte +var z1433 [1 << 17]byte +var z1434 [1 << 17]byte +var z1435 [1 << 17]byte +var z1436 [1 << 17]byte +var z1437 [1 << 17]byte +var z1438 [1 << 17]byte +var z1439 [1 << 17]byte +var z1440 [1 << 17]byte +var z1441 [1 << 17]byte +var z1442 [1 << 17]byte +var z1443 [1 << 17]byte +var z1444 [1 << 17]byte +var z1445 [1 << 17]byte +var z1446 [1 << 17]byte +var z1447 [1 << 17]byte +var z1448 [1 << 17]byte +var z1449 [1 << 17]byte +var z1450 [1 << 17]byte +var z1451 [1 << 17]byte +var z1452 [1 << 17]byte +var z1453 [1 << 17]byte +var z1454 [1 << 17]byte +var z1455 [1 << 17]byte +var z1456 [1 << 17]byte +var z1457 [1 << 17]byte +var z1458 [1 << 17]byte +var z1459 [1 << 17]byte +var z1460 [1 << 17]byte +var z1461 [1 << 17]byte +var z1462 [1 << 17]byte +var z1463 [1 << 17]byte +var z1464 [1 << 17]byte +var z1465 [1 << 17]byte +var z1466 [1 << 17]byte +var z1467 [1 << 17]byte +var z1468 [1 << 17]byte +var z1469 [1 << 17]byte +var z1470 [1 << 17]byte +var z1471 [1 << 17]byte +var z1472 [1 << 17]byte +var z1473 [1 << 17]byte +var z1474 [1 << 17]byte +var z1475 [1 << 17]byte +var z1476 [1 << 17]byte +var z1477 [1 << 17]byte +var z1478 [1 << 17]byte +var z1479 [1 << 17]byte +var z1480 [1 << 17]byte +var z1481 [1 << 17]byte +var z1482 [1 << 17]byte +var z1483 [1 << 17]byte +var z1484 [1 << 17]byte +var z1485 [1 << 17]byte +var z1486 [1 << 17]byte +var z1487 [1 << 17]byte +var z1488 [1 << 17]byte +var z1489 [1 << 17]byte +var z1490 [1 << 17]byte +var z1491 [1 << 17]byte +var z1492 [1 << 17]byte +var z1493 [1 << 17]byte +var z1494 [1 << 17]byte +var z1495 [1 << 17]byte +var z1496 [1 << 17]byte +var z1497 [1 << 17]byte +var z1498 [1 << 17]byte +var z1499 [1 << 17]byte +var z1500 [1 << 17]byte +var z1501 [1 << 17]byte +var z1502 [1 << 17]byte +var z1503 [1 << 17]byte +var z1504 [1 << 17]byte +var z1505 [1 << 17]byte +var z1506 [1 << 17]byte +var z1507 [1 << 17]byte +var z1508 [1 << 17]byte +var z1509 [1 << 17]byte +var z1510 [1 << 17]byte +var z1511 [1 << 17]byte +var z1512 [1 << 17]byte +var z1513 [1 << 17]byte +var z1514 [1 << 17]byte +var z1515 [1 << 17]byte +var z1516 [1 << 17]byte +var z1517 [1 << 17]byte +var z1518 [1 << 17]byte +var z1519 [1 << 17]byte +var z1520 [1 << 17]byte +var z1521 [1 << 17]byte +var z1522 [1 << 17]byte +var z1523 [1 << 17]byte +var z1524 [1 << 17]byte +var z1525 [1 << 17]byte +var z1526 [1 << 17]byte +var z1527 [1 << 17]byte +var z1528 [1 << 17]byte +var z1529 [1 << 17]byte +var z1530 [1 << 17]byte +var z1531 [1 << 17]byte +var z1532 [1 << 17]byte +var z1533 [1 << 17]byte +var z1534 [1 << 17]byte +var z1535 [1 << 17]byte +var z1536 [1 << 17]byte +var z1537 [1 << 17]byte +var z1538 [1 << 17]byte +var z1539 [1 << 17]byte +var z1540 [1 << 17]byte +var z1541 [1 << 17]byte +var z1542 [1 << 17]byte +var z1543 [1 << 17]byte +var z1544 [1 << 17]byte +var z1545 [1 << 17]byte +var z1546 [1 << 17]byte +var z1547 [1 << 17]byte +var z1548 [1 << 17]byte +var z1549 [1 << 17]byte +var z1550 [1 << 17]byte +var z1551 [1 << 17]byte +var z1552 [1 << 17]byte +var z1553 [1 << 17]byte +var z1554 [1 << 17]byte +var z1555 [1 << 17]byte +var z1556 [1 << 17]byte +var z1557 [1 << 17]byte +var z1558 [1 << 17]byte +var z1559 [1 << 17]byte +var z1560 [1 << 17]byte +var z1561 [1 << 17]byte +var z1562 [1 << 17]byte +var z1563 [1 << 17]byte +var z1564 [1 << 17]byte +var z1565 [1 << 17]byte +var z1566 [1 << 17]byte +var z1567 [1 << 17]byte +var z1568 [1 << 17]byte +var z1569 [1 << 17]byte +var z1570 [1 << 17]byte +var z1571 [1 << 17]byte +var z1572 [1 << 17]byte +var z1573 [1 << 17]byte +var z1574 [1 << 17]byte +var z1575 [1 << 17]byte +var z1576 [1 << 17]byte +var z1577 [1 << 17]byte +var z1578 [1 << 17]byte +var z1579 [1 << 17]byte +var z1580 [1 << 17]byte +var z1581 [1 << 17]byte +var z1582 [1 << 17]byte +var z1583 [1 << 17]byte +var z1584 [1 << 17]byte +var z1585 [1 << 17]byte +var z1586 [1 << 17]byte +var z1587 [1 << 17]byte +var z1588 [1 << 17]byte +var z1589 [1 << 17]byte +var z1590 [1 << 17]byte +var z1591 [1 << 17]byte +var z1592 [1 << 17]byte +var z1593 [1 << 17]byte +var z1594 [1 << 17]byte +var z1595 [1 << 17]byte +var z1596 [1 << 17]byte +var z1597 [1 << 17]byte +var z1598 [1 << 17]byte +var z1599 [1 << 17]byte +var z1600 [1 << 17]byte +var z1601 [1 << 17]byte +var z1602 [1 << 17]byte +var z1603 [1 << 17]byte +var z1604 [1 << 17]byte +var z1605 [1 << 17]byte +var z1606 [1 << 17]byte +var z1607 [1 << 17]byte +var z1608 [1 << 17]byte +var z1609 [1 << 17]byte +var z1610 [1 << 17]byte +var z1611 [1 << 17]byte +var z1612 [1 << 17]byte +var z1613 [1 << 17]byte +var z1614 [1 << 17]byte +var z1615 [1 << 17]byte +var z1616 [1 << 17]byte +var z1617 [1 << 17]byte +var z1618 [1 << 17]byte +var z1619 [1 << 17]byte +var z1620 [1 << 17]byte +var z1621 [1 << 17]byte +var z1622 [1 << 17]byte +var z1623 [1 << 17]byte +var z1624 [1 << 17]byte +var z1625 [1 << 17]byte +var z1626 [1 << 17]byte +var z1627 [1 << 17]byte +var z1628 [1 << 17]byte +var z1629 [1 << 17]byte +var z1630 [1 << 17]byte +var z1631 [1 << 17]byte +var z1632 [1 << 17]byte +var z1633 [1 << 17]byte +var z1634 [1 << 17]byte +var z1635 [1 << 17]byte +var z1636 [1 << 17]byte +var z1637 [1 << 17]byte +var z1638 [1 << 17]byte +var z1639 [1 << 17]byte +var z1640 [1 << 17]byte +var z1641 [1 << 17]byte +var z1642 [1 << 17]byte +var z1643 [1 << 17]byte +var z1644 [1 << 17]byte +var z1645 [1 << 17]byte +var z1646 [1 << 17]byte +var z1647 [1 << 17]byte +var z1648 [1 << 17]byte +var z1649 [1 << 17]byte +var z1650 [1 << 17]byte +var z1651 [1 << 17]byte +var z1652 [1 << 17]byte +var z1653 [1 << 17]byte +var z1654 [1 << 17]byte +var z1655 [1 << 17]byte +var z1656 [1 << 17]byte +var z1657 [1 << 17]byte +var z1658 [1 << 17]byte +var z1659 [1 << 17]byte +var z1660 [1 << 17]byte +var z1661 [1 << 17]byte +var z1662 [1 << 17]byte +var z1663 [1 << 17]byte +var z1664 [1 << 17]byte +var z1665 [1 << 17]byte +var z1666 [1 << 17]byte +var z1667 [1 << 17]byte +var z1668 [1 << 17]byte +var z1669 [1 << 17]byte +var z1670 [1 << 17]byte +var z1671 [1 << 17]byte +var z1672 [1 << 17]byte +var z1673 [1 << 17]byte +var z1674 [1 << 17]byte +var z1675 [1 << 17]byte +var z1676 [1 << 17]byte +var z1677 [1 << 17]byte +var z1678 [1 << 17]byte +var z1679 [1 << 17]byte +var z1680 [1 << 17]byte +var z1681 [1 << 17]byte +var z1682 [1 << 17]byte +var z1683 [1 << 17]byte +var z1684 [1 << 17]byte +var z1685 [1 << 17]byte +var z1686 [1 << 17]byte +var z1687 [1 << 17]byte +var z1688 [1 << 17]byte +var z1689 [1 << 17]byte +var z1690 [1 << 17]byte +var z1691 [1 << 17]byte +var z1692 [1 << 17]byte +var z1693 [1 << 17]byte +var z1694 [1 << 17]byte +var z1695 [1 << 17]byte +var z1696 [1 << 17]byte +var z1697 [1 << 17]byte +var z1698 [1 << 17]byte +var z1699 [1 << 17]byte +var z1700 [1 << 17]byte +var z1701 [1 << 17]byte +var z1702 [1 << 17]byte +var z1703 [1 << 17]byte +var z1704 [1 << 17]byte +var z1705 [1 << 17]byte +var z1706 [1 << 17]byte +var z1707 [1 << 17]byte +var z1708 [1 << 17]byte +var z1709 [1 << 17]byte +var z1710 [1 << 17]byte +var z1711 [1 << 17]byte +var z1712 [1 << 17]byte +var z1713 [1 << 17]byte +var z1714 [1 << 17]byte +var z1715 [1 << 17]byte +var z1716 [1 << 17]byte +var z1717 [1 << 17]byte +var z1718 [1 << 17]byte +var z1719 [1 << 17]byte +var z1720 [1 << 17]byte +var z1721 [1 << 17]byte +var z1722 [1 << 17]byte +var z1723 [1 << 17]byte +var z1724 [1 << 17]byte +var z1725 [1 << 17]byte +var z1726 [1 << 17]byte +var z1727 [1 << 17]byte +var z1728 [1 << 17]byte +var z1729 [1 << 17]byte +var z1730 [1 << 17]byte +var z1731 [1 << 17]byte +var z1732 [1 << 17]byte +var z1733 [1 << 17]byte +var z1734 [1 << 17]byte +var z1735 [1 << 17]byte +var z1736 [1 << 17]byte +var z1737 [1 << 17]byte +var z1738 [1 << 17]byte +var z1739 [1 << 17]byte +var z1740 [1 << 17]byte +var z1741 [1 << 17]byte +var z1742 [1 << 17]byte +var z1743 [1 << 17]byte +var z1744 [1 << 17]byte +var z1745 [1 << 17]byte +var z1746 [1 << 17]byte +var z1747 [1 << 17]byte +var z1748 [1 << 17]byte +var z1749 [1 << 17]byte +var z1750 [1 << 17]byte +var z1751 [1 << 17]byte +var z1752 [1 << 17]byte +var z1753 [1 << 17]byte +var z1754 [1 << 17]byte +var z1755 [1 << 17]byte +var z1756 [1 << 17]byte +var z1757 [1 << 17]byte +var z1758 [1 << 17]byte +var z1759 [1 << 17]byte +var z1760 [1 << 17]byte +var z1761 [1 << 17]byte +var z1762 [1 << 17]byte +var z1763 [1 << 17]byte +var z1764 [1 << 17]byte +var z1765 [1 << 17]byte +var z1766 [1 << 17]byte +var z1767 [1 << 17]byte +var z1768 [1 << 17]byte +var z1769 [1 << 17]byte +var z1770 [1 << 17]byte +var z1771 [1 << 17]byte +var z1772 [1 << 17]byte +var z1773 [1 << 17]byte +var z1774 [1 << 17]byte +var z1775 [1 << 17]byte +var z1776 [1 << 17]byte +var z1777 [1 << 17]byte +var z1778 [1 << 17]byte +var z1779 [1 << 17]byte +var z1780 [1 << 17]byte +var z1781 [1 << 17]byte +var z1782 [1 << 17]byte +var z1783 [1 << 17]byte +var z1784 [1 << 17]byte +var z1785 [1 << 17]byte +var z1786 [1 << 17]byte +var z1787 [1 << 17]byte +var z1788 [1 << 17]byte +var z1789 [1 << 17]byte +var z1790 [1 << 17]byte +var z1791 [1 << 17]byte +var z1792 [1 << 17]byte +var z1793 [1 << 17]byte +var z1794 [1 << 17]byte +var z1795 [1 << 17]byte +var z1796 [1 << 17]byte +var z1797 [1 << 17]byte +var z1798 [1 << 17]byte +var z1799 [1 << 17]byte +var z1800 [1 << 17]byte +var z1801 [1 << 17]byte +var z1802 [1 << 17]byte +var z1803 [1 << 17]byte +var z1804 [1 << 17]byte +var z1805 [1 << 17]byte +var z1806 [1 << 17]byte +var z1807 [1 << 17]byte +var z1808 [1 << 17]byte +var z1809 [1 << 17]byte +var z1810 [1 << 17]byte +var z1811 [1 << 17]byte +var z1812 [1 << 17]byte +var z1813 [1 << 17]byte +var z1814 [1 << 17]byte +var z1815 [1 << 17]byte +var z1816 [1 << 17]byte +var z1817 [1 << 17]byte +var z1818 [1 << 17]byte +var z1819 [1 << 17]byte +var z1820 [1 << 17]byte +var z1821 [1 << 17]byte +var z1822 [1 << 17]byte +var z1823 [1 << 17]byte +var z1824 [1 << 17]byte +var z1825 [1 << 17]byte +var z1826 [1 << 17]byte +var z1827 [1 << 17]byte +var z1828 [1 << 17]byte +var z1829 [1 << 17]byte +var z1830 [1 << 17]byte +var z1831 [1 << 17]byte +var z1832 [1 << 17]byte +var z1833 [1 << 17]byte +var z1834 [1 << 17]byte +var z1835 [1 << 17]byte +var z1836 [1 << 17]byte +var z1837 [1 << 17]byte +var z1838 [1 << 17]byte +var z1839 [1 << 17]byte +var z1840 [1 << 17]byte +var z1841 [1 << 17]byte +var z1842 [1 << 17]byte +var z1843 [1 << 17]byte +var z1844 [1 << 17]byte +var z1845 [1 << 17]byte +var z1846 [1 << 17]byte +var z1847 [1 << 17]byte +var z1848 [1 << 17]byte +var z1849 [1 << 17]byte +var z1850 [1 << 17]byte +var z1851 [1 << 17]byte +var z1852 [1 << 17]byte +var z1853 [1 << 17]byte +var z1854 [1 << 17]byte +var z1855 [1 << 17]byte +var z1856 [1 << 17]byte +var z1857 [1 << 17]byte +var z1858 [1 << 17]byte +var z1859 [1 << 17]byte +var z1860 [1 << 17]byte +var z1861 [1 << 17]byte +var z1862 [1 << 17]byte +var z1863 [1 << 17]byte +var z1864 [1 << 17]byte +var z1865 [1 << 17]byte +var z1866 [1 << 17]byte +var z1867 [1 << 17]byte +var z1868 [1 << 17]byte +var z1869 [1 << 17]byte +var z1870 [1 << 17]byte +var z1871 [1 << 17]byte +var z1872 [1 << 17]byte +var z1873 [1 << 17]byte +var z1874 [1 << 17]byte +var z1875 [1 << 17]byte +var z1876 [1 << 17]byte +var z1877 [1 << 17]byte +var z1878 [1 << 17]byte +var z1879 [1 << 17]byte +var z1880 [1 << 17]byte +var z1881 [1 << 17]byte +var z1882 [1 << 17]byte +var z1883 [1 << 17]byte +var z1884 [1 << 17]byte +var z1885 [1 << 17]byte +var z1886 [1 << 17]byte +var z1887 [1 << 17]byte +var z1888 [1 << 17]byte +var z1889 [1 << 17]byte +var z1890 [1 << 17]byte +var z1891 [1 << 17]byte +var z1892 [1 << 17]byte +var z1893 [1 << 17]byte +var z1894 [1 << 17]byte +var z1895 [1 << 17]byte +var z1896 [1 << 17]byte +var z1897 [1 << 17]byte +var z1898 [1 << 17]byte +var z1899 [1 << 17]byte +var z1900 [1 << 17]byte +var z1901 [1 << 17]byte +var z1902 [1 << 17]byte +var z1903 [1 << 17]byte +var z1904 [1 << 17]byte +var z1905 [1 << 17]byte +var z1906 [1 << 17]byte +var z1907 [1 << 17]byte +var z1908 [1 << 17]byte +var z1909 [1 << 17]byte +var z1910 [1 << 17]byte +var z1911 [1 << 17]byte +var z1912 [1 << 17]byte +var z1913 [1 << 17]byte +var z1914 [1 << 17]byte +var z1915 [1 << 17]byte +var z1916 [1 << 17]byte +var z1917 [1 << 17]byte +var z1918 [1 << 17]byte +var z1919 [1 << 17]byte +var z1920 [1 << 17]byte +var z1921 [1 << 17]byte +var z1922 [1 << 17]byte +var z1923 [1 << 17]byte +var z1924 [1 << 17]byte +var z1925 [1 << 17]byte +var z1926 [1 << 17]byte +var z1927 [1 << 17]byte +var z1928 [1 << 17]byte +var z1929 [1 << 17]byte +var z1930 [1 << 17]byte +var z1931 [1 << 17]byte +var z1932 [1 << 17]byte +var z1933 [1 << 17]byte +var z1934 [1 << 17]byte +var z1935 [1 << 17]byte +var z1936 [1 << 17]byte +var z1937 [1 << 17]byte +var z1938 [1 << 17]byte +var z1939 [1 << 17]byte +var z1940 [1 << 17]byte +var z1941 [1 << 17]byte +var z1942 [1 << 17]byte +var z1943 [1 << 17]byte +var z1944 [1 << 17]byte +var z1945 [1 << 17]byte +var z1946 [1 << 17]byte +var z1947 [1 << 17]byte +var z1948 [1 << 17]byte +var z1949 [1 << 17]byte +var z1950 [1 << 17]byte +var z1951 [1 << 17]byte +var z1952 [1 << 17]byte +var z1953 [1 << 17]byte +var z1954 [1 << 17]byte +var z1955 [1 << 17]byte +var z1956 [1 << 17]byte +var z1957 [1 << 17]byte +var z1958 [1 << 17]byte +var z1959 [1 << 17]byte +var z1960 [1 << 17]byte +var z1961 [1 << 17]byte +var z1962 [1 << 17]byte +var z1963 [1 << 17]byte +var z1964 [1 << 17]byte +var z1965 [1 << 17]byte +var z1966 [1 << 17]byte +var z1967 [1 << 17]byte +var z1968 [1 << 17]byte +var z1969 [1 << 17]byte +var z1970 [1 << 17]byte +var z1971 [1 << 17]byte +var z1972 [1 << 17]byte +var z1973 [1 << 17]byte +var z1974 [1 << 17]byte +var z1975 [1 << 17]byte +var z1976 [1 << 17]byte +var z1977 [1 << 17]byte +var z1978 [1 << 17]byte +var z1979 [1 << 17]byte +var z1980 [1 << 17]byte +var z1981 [1 << 17]byte +var z1982 [1 << 17]byte +var z1983 [1 << 17]byte +var z1984 [1 << 17]byte +var z1985 [1 << 17]byte +var z1986 [1 << 17]byte +var z1987 [1 << 17]byte +var z1988 [1 << 17]byte +var z1989 [1 << 17]byte +var z1990 [1 << 17]byte +var z1991 [1 << 17]byte +var z1992 [1 << 17]byte +var z1993 [1 << 17]byte +var z1994 [1 << 17]byte +var z1995 [1 << 17]byte +var z1996 [1 << 17]byte +var z1997 [1 << 17]byte +var z1998 [1 << 17]byte +var z1999 [1 << 17]byte +var z2000 [1 << 17]byte +var z2001 [1 << 17]byte +var z2002 [1 << 17]byte +var z2003 [1 << 17]byte +var z2004 [1 << 17]byte +var z2005 [1 << 17]byte +var z2006 [1 << 17]byte +var z2007 [1 << 17]byte +var z2008 [1 << 17]byte +var z2009 [1 << 17]byte +var z2010 [1 << 17]byte +var z2011 [1 << 17]byte +var z2012 [1 << 17]byte +var z2013 [1 << 17]byte +var z2014 [1 << 17]byte +var z2015 [1 << 17]byte +var z2016 [1 << 17]byte +var z2017 [1 << 17]byte +var z2018 [1 << 17]byte +var z2019 [1 << 17]byte +var z2020 [1 << 17]byte +var z2021 [1 << 17]byte +var z2022 [1 << 17]byte +var z2023 [1 << 17]byte +var z2024 [1 << 17]byte +var z2025 [1 << 17]byte +var z2026 [1 << 17]byte +var z2027 [1 << 17]byte +var z2028 [1 << 17]byte +var z2029 [1 << 17]byte +var z2030 [1 << 17]byte +var z2031 [1 << 17]byte +var z2032 [1 << 17]byte +var z2033 [1 << 17]byte +var z2034 [1 << 17]byte +var z2035 [1 << 17]byte +var z2036 [1 << 17]byte +var z2037 [1 << 17]byte +var z2038 [1 << 17]byte +var z2039 [1 << 17]byte +var z2040 [1 << 17]byte +var z2041 [1 << 17]byte +var z2042 [1 << 17]byte +var z2043 [1 << 17]byte +var z2044 [1 << 17]byte +var z2045 [1 << 17]byte +var z2046 [1 << 17]byte +var z2047 [1 << 17]byte +var z2048 [1 << 17]byte +var z2049 [1 << 17]byte +var z2050 [1 << 17]byte +var z2051 [1 << 17]byte +var z2052 [1 << 17]byte +var z2053 [1 << 17]byte +var z2054 [1 << 17]byte +var z2055 [1 << 17]byte +var z2056 [1 << 17]byte +var z2057 [1 << 17]byte +var z2058 [1 << 17]byte +var z2059 [1 << 17]byte +var z2060 [1 << 17]byte +var z2061 [1 << 17]byte +var z2062 [1 << 17]byte +var z2063 [1 << 17]byte +var z2064 [1 << 17]byte +var z2065 [1 << 17]byte +var z2066 [1 << 17]byte +var z2067 [1 << 17]byte +var z2068 [1 << 17]byte +var z2069 [1 << 17]byte +var z2070 [1 << 17]byte +var z2071 [1 << 17]byte +var z2072 [1 << 17]byte +var z2073 [1 << 17]byte +var z2074 [1 << 17]byte +var z2075 [1 << 17]byte +var z2076 [1 << 17]byte +var z2077 [1 << 17]byte +var z2078 [1 << 17]byte +var z2079 [1 << 17]byte +var z2080 [1 << 17]byte +var z2081 [1 << 17]byte +var z2082 [1 << 17]byte +var z2083 [1 << 17]byte +var z2084 [1 << 17]byte +var z2085 [1 << 17]byte +var z2086 [1 << 17]byte +var z2087 [1 << 17]byte +var z2088 [1 << 17]byte +var z2089 [1 << 17]byte +var z2090 [1 << 17]byte +var z2091 [1 << 17]byte +var z2092 [1 << 17]byte +var z2093 [1 << 17]byte +var z2094 [1 << 17]byte +var z2095 [1 << 17]byte +var z2096 [1 << 17]byte +var z2097 [1 << 17]byte +var z2098 [1 << 17]byte +var z2099 [1 << 17]byte +var z2100 [1 << 17]byte +var z2101 [1 << 17]byte +var z2102 [1 << 17]byte +var z2103 [1 << 17]byte +var z2104 [1 << 17]byte +var z2105 [1 << 17]byte +var z2106 [1 << 17]byte +var z2107 [1 << 17]byte +var z2108 [1 << 17]byte +var z2109 [1 << 17]byte +var z2110 [1 << 17]byte +var z2111 [1 << 17]byte +var z2112 [1 << 17]byte +var z2113 [1 << 17]byte +var z2114 [1 << 17]byte +var z2115 [1 << 17]byte +var z2116 [1 << 17]byte +var z2117 [1 << 17]byte +var z2118 [1 << 17]byte +var z2119 [1 << 17]byte +var z2120 [1 << 17]byte +var z2121 [1 << 17]byte +var z2122 [1 << 17]byte +var z2123 [1 << 17]byte +var z2124 [1 << 17]byte +var z2125 [1 << 17]byte +var z2126 [1 << 17]byte +var z2127 [1 << 17]byte +var z2128 [1 << 17]byte +var z2129 [1 << 17]byte +var z2130 [1 << 17]byte +var z2131 [1 << 17]byte +var z2132 [1 << 17]byte +var z2133 [1 << 17]byte +var z2134 [1 << 17]byte +var z2135 [1 << 17]byte +var z2136 [1 << 17]byte +var z2137 [1 << 17]byte +var z2138 [1 << 17]byte +var z2139 [1 << 17]byte +var z2140 [1 << 17]byte +var z2141 [1 << 17]byte +var z2142 [1 << 17]byte +var z2143 [1 << 17]byte +var z2144 [1 << 17]byte +var z2145 [1 << 17]byte +var z2146 [1 << 17]byte +var z2147 [1 << 17]byte +var z2148 [1 << 17]byte +var z2149 [1 << 17]byte +var z2150 [1 << 17]byte +var z2151 [1 << 17]byte +var z2152 [1 << 17]byte +var z2153 [1 << 17]byte +var z2154 [1 << 17]byte +var z2155 [1 << 17]byte +var z2156 [1 << 17]byte +var z2157 [1 << 17]byte +var z2158 [1 << 17]byte +var z2159 [1 << 17]byte +var z2160 [1 << 17]byte +var z2161 [1 << 17]byte +var z2162 [1 << 17]byte +var z2163 [1 << 17]byte +var z2164 [1 << 17]byte +var z2165 [1 << 17]byte +var z2166 [1 << 17]byte +var z2167 [1 << 17]byte +var z2168 [1 << 17]byte +var z2169 [1 << 17]byte +var z2170 [1 << 17]byte +var z2171 [1 << 17]byte +var z2172 [1 << 17]byte +var z2173 [1 << 17]byte +var z2174 [1 << 17]byte +var z2175 [1 << 17]byte +var z2176 [1 << 17]byte +var z2177 [1 << 17]byte +var z2178 [1 << 17]byte +var z2179 [1 << 17]byte +var z2180 [1 << 17]byte +var z2181 [1 << 17]byte +var z2182 [1 << 17]byte +var z2183 [1 << 17]byte +var z2184 [1 << 17]byte +var z2185 [1 << 17]byte +var z2186 [1 << 17]byte +var z2187 [1 << 17]byte +var z2188 [1 << 17]byte +var z2189 [1 << 17]byte +var z2190 [1 << 17]byte +var z2191 [1 << 17]byte +var z2192 [1 << 17]byte +var z2193 [1 << 17]byte +var z2194 [1 << 17]byte +var z2195 [1 << 17]byte +var z2196 [1 << 17]byte +var z2197 [1 << 17]byte +var z2198 [1 << 17]byte +var z2199 [1 << 17]byte +var z2200 [1 << 17]byte +var z2201 [1 << 17]byte +var z2202 [1 << 17]byte +var z2203 [1 << 17]byte +var z2204 [1 << 17]byte +var z2205 [1 << 17]byte +var z2206 [1 << 17]byte +var z2207 [1 << 17]byte +var z2208 [1 << 17]byte +var z2209 [1 << 17]byte +var z2210 [1 << 17]byte +var z2211 [1 << 17]byte +var z2212 [1 << 17]byte +var z2213 [1 << 17]byte +var z2214 [1 << 17]byte +var z2215 [1 << 17]byte +var z2216 [1 << 17]byte +var z2217 [1 << 17]byte +var z2218 [1 << 17]byte +var z2219 [1 << 17]byte +var z2220 [1 << 17]byte +var z2221 [1 << 17]byte +var z2222 [1 << 17]byte +var z2223 [1 << 17]byte +var z2224 [1 << 17]byte +var z2225 [1 << 17]byte +var z2226 [1 << 17]byte +var z2227 [1 << 17]byte +var z2228 [1 << 17]byte +var z2229 [1 << 17]byte +var z2230 [1 << 17]byte +var z2231 [1 << 17]byte +var z2232 [1 << 17]byte +var z2233 [1 << 17]byte +var z2234 [1 << 17]byte +var z2235 [1 << 17]byte +var z2236 [1 << 17]byte +var z2237 [1 << 17]byte +var z2238 [1 << 17]byte +var z2239 [1 << 17]byte +var z2240 [1 << 17]byte +var z2241 [1 << 17]byte +var z2242 [1 << 17]byte +var z2243 [1 << 17]byte +var z2244 [1 << 17]byte +var z2245 [1 << 17]byte +var z2246 [1 << 17]byte +var z2247 [1 << 17]byte +var z2248 [1 << 17]byte +var z2249 [1 << 17]byte +var z2250 [1 << 17]byte +var z2251 [1 << 17]byte +var z2252 [1 << 17]byte +var z2253 [1 << 17]byte +var z2254 [1 << 17]byte +var z2255 [1 << 17]byte +var z2256 [1 << 17]byte +var z2257 [1 << 17]byte +var z2258 [1 << 17]byte +var z2259 [1 << 17]byte +var z2260 [1 << 17]byte +var z2261 [1 << 17]byte +var z2262 [1 << 17]byte +var z2263 [1 << 17]byte +var z2264 [1 << 17]byte +var z2265 [1 << 17]byte +var z2266 [1 << 17]byte +var z2267 [1 << 17]byte +var z2268 [1 << 17]byte +var z2269 [1 << 17]byte +var z2270 [1 << 17]byte +var z2271 [1 << 17]byte +var z2272 [1 << 17]byte +var z2273 [1 << 17]byte +var z2274 [1 << 17]byte +var z2275 [1 << 17]byte +var z2276 [1 << 17]byte +var z2277 [1 << 17]byte +var z2278 [1 << 17]byte +var z2279 [1 << 17]byte +var z2280 [1 << 17]byte +var z2281 [1 << 17]byte +var z2282 [1 << 17]byte +var z2283 [1 << 17]byte +var z2284 [1 << 17]byte +var z2285 [1 << 17]byte +var z2286 [1 << 17]byte +var z2287 [1 << 17]byte +var z2288 [1 << 17]byte +var z2289 [1 << 17]byte +var z2290 [1 << 17]byte +var z2291 [1 << 17]byte +var z2292 [1 << 17]byte +var z2293 [1 << 17]byte +var z2294 [1 << 17]byte +var z2295 [1 << 17]byte +var z2296 [1 << 17]byte +var z2297 [1 << 17]byte +var z2298 [1 << 17]byte +var z2299 [1 << 17]byte +var z2300 [1 << 17]byte +var z2301 [1 << 17]byte +var z2302 [1 << 17]byte +var z2303 [1 << 17]byte +var z2304 [1 << 17]byte +var z2305 [1 << 17]byte +var z2306 [1 << 17]byte +var z2307 [1 << 17]byte +var z2308 [1 << 17]byte +var z2309 [1 << 17]byte +var z2310 [1 << 17]byte +var z2311 [1 << 17]byte +var z2312 [1 << 17]byte +var z2313 [1 << 17]byte +var z2314 [1 << 17]byte +var z2315 [1 << 17]byte +var z2316 [1 << 17]byte +var z2317 [1 << 17]byte +var z2318 [1 << 17]byte +var z2319 [1 << 17]byte +var z2320 [1 << 17]byte +var z2321 [1 << 17]byte +var z2322 [1 << 17]byte +var z2323 [1 << 17]byte +var z2324 [1 << 17]byte +var z2325 [1 << 17]byte +var z2326 [1 << 17]byte +var z2327 [1 << 17]byte +var z2328 [1 << 17]byte +var z2329 [1 << 17]byte +var z2330 [1 << 17]byte +var z2331 [1 << 17]byte +var z2332 [1 << 17]byte +var z2333 [1 << 17]byte +var z2334 [1 << 17]byte +var z2335 [1 << 17]byte +var z2336 [1 << 17]byte +var z2337 [1 << 17]byte +var z2338 [1 << 17]byte +var z2339 [1 << 17]byte +var z2340 [1 << 17]byte +var z2341 [1 << 17]byte +var z2342 [1 << 17]byte +var z2343 [1 << 17]byte +var z2344 [1 << 17]byte +var z2345 [1 << 17]byte +var z2346 [1 << 17]byte +var z2347 [1 << 17]byte +var z2348 [1 << 17]byte +var z2349 [1 << 17]byte +var z2350 [1 << 17]byte +var z2351 [1 << 17]byte +var z2352 [1 << 17]byte +var z2353 [1 << 17]byte +var z2354 [1 << 17]byte +var z2355 [1 << 17]byte +var z2356 [1 << 17]byte +var z2357 [1 << 17]byte +var z2358 [1 << 17]byte +var z2359 [1 << 17]byte +var z2360 [1 << 17]byte +var z2361 [1 << 17]byte +var z2362 [1 << 17]byte +var z2363 [1 << 17]byte +var z2364 [1 << 17]byte +var z2365 [1 << 17]byte +var z2366 [1 << 17]byte +var z2367 [1 << 17]byte +var z2368 [1 << 17]byte +var z2369 [1 << 17]byte +var z2370 [1 << 17]byte +var z2371 [1 << 17]byte +var z2372 [1 << 17]byte +var z2373 [1 << 17]byte +var z2374 [1 << 17]byte +var z2375 [1 << 17]byte +var z2376 [1 << 17]byte +var z2377 [1 << 17]byte +var z2378 [1 << 17]byte +var z2379 [1 << 17]byte +var z2380 [1 << 17]byte +var z2381 [1 << 17]byte +var z2382 [1 << 17]byte +var z2383 [1 << 17]byte +var z2384 [1 << 17]byte +var z2385 [1 << 17]byte +var z2386 [1 << 17]byte +var z2387 [1 << 17]byte +var z2388 [1 << 17]byte +var z2389 [1 << 17]byte +var z2390 [1 << 17]byte +var z2391 [1 << 17]byte +var z2392 [1 << 17]byte +var z2393 [1 << 17]byte +var z2394 [1 << 17]byte +var z2395 [1 << 17]byte +var z2396 [1 << 17]byte +var z2397 [1 << 17]byte +var z2398 [1 << 17]byte +var z2399 [1 << 17]byte +var z2400 [1 << 17]byte +var z2401 [1 << 17]byte +var z2402 [1 << 17]byte +var z2403 [1 << 17]byte +var z2404 [1 << 17]byte +var z2405 [1 << 17]byte +var z2406 [1 << 17]byte +var z2407 [1 << 17]byte +var z2408 [1 << 17]byte +var z2409 [1 << 17]byte +var z2410 [1 << 17]byte +var z2411 [1 << 17]byte +var z2412 [1 << 17]byte +var z2413 [1 << 17]byte +var z2414 [1 << 17]byte +var z2415 [1 << 17]byte +var z2416 [1 << 17]byte +var z2417 [1 << 17]byte +var z2418 [1 << 17]byte +var z2419 [1 << 17]byte +var z2420 [1 << 17]byte +var z2421 [1 << 17]byte +var z2422 [1 << 17]byte +var z2423 [1 << 17]byte +var z2424 [1 << 17]byte +var z2425 [1 << 17]byte +var z2426 [1 << 17]byte +var z2427 [1 << 17]byte +var z2428 [1 << 17]byte +var z2429 [1 << 17]byte +var z2430 [1 << 17]byte +var z2431 [1 << 17]byte +var z2432 [1 << 17]byte +var z2433 [1 << 17]byte +var z2434 [1 << 17]byte +var z2435 [1 << 17]byte +var z2436 [1 << 17]byte +var z2437 [1 << 17]byte +var z2438 [1 << 17]byte +var z2439 [1 << 17]byte +var z2440 [1 << 17]byte +var z2441 [1 << 17]byte +var z2442 [1 << 17]byte +var z2443 [1 << 17]byte +var z2444 [1 << 17]byte +var z2445 [1 << 17]byte +var z2446 [1 << 17]byte +var z2447 [1 << 17]byte +var z2448 [1 << 17]byte +var z2449 [1 << 17]byte +var z2450 [1 << 17]byte +var z2451 [1 << 17]byte +var z2452 [1 << 17]byte +var z2453 [1 << 17]byte +var z2454 [1 << 17]byte +var z2455 [1 << 17]byte +var z2456 [1 << 17]byte +var z2457 [1 << 17]byte +var z2458 [1 << 17]byte +var z2459 [1 << 17]byte +var z2460 [1 << 17]byte +var z2461 [1 << 17]byte +var z2462 [1 << 17]byte +var z2463 [1 << 17]byte +var z2464 [1 << 17]byte +var z2465 [1 << 17]byte +var z2466 [1 << 17]byte +var z2467 [1 << 17]byte +var z2468 [1 << 17]byte +var z2469 [1 << 17]byte +var z2470 [1 << 17]byte +var z2471 [1 << 17]byte +var z2472 [1 << 17]byte +var z2473 [1 << 17]byte +var z2474 [1 << 17]byte +var z2475 [1 << 17]byte +var z2476 [1 << 17]byte +var z2477 [1 << 17]byte +var z2478 [1 << 17]byte +var z2479 [1 << 17]byte +var z2480 [1 << 17]byte +var z2481 [1 << 17]byte +var z2482 [1 << 17]byte +var z2483 [1 << 17]byte +var z2484 [1 << 17]byte +var z2485 [1 << 17]byte +var z2486 [1 << 17]byte +var z2487 [1 << 17]byte +var z2488 [1 << 17]byte +var z2489 [1 << 17]byte +var z2490 [1 << 17]byte +var z2491 [1 << 17]byte +var z2492 [1 << 17]byte +var z2493 [1 << 17]byte +var z2494 [1 << 17]byte +var z2495 [1 << 17]byte +var z2496 [1 << 17]byte +var z2497 [1 << 17]byte +var z2498 [1 << 17]byte +var z2499 [1 << 17]byte +var z2500 [1 << 17]byte +var z2501 [1 << 17]byte +var z2502 [1 << 17]byte +var z2503 [1 << 17]byte +var z2504 [1 << 17]byte +var z2505 [1 << 17]byte +var z2506 [1 << 17]byte +var z2507 [1 << 17]byte +var z2508 [1 << 17]byte +var z2509 [1 << 17]byte +var z2510 [1 << 17]byte +var z2511 [1 << 17]byte +var z2512 [1 << 17]byte +var z2513 [1 << 17]byte +var z2514 [1 << 17]byte +var z2515 [1 << 17]byte +var z2516 [1 << 17]byte +var z2517 [1 << 17]byte +var z2518 [1 << 17]byte +var z2519 [1 << 17]byte +var z2520 [1 << 17]byte +var z2521 [1 << 17]byte +var z2522 [1 << 17]byte +var z2523 [1 << 17]byte +var z2524 [1 << 17]byte +var z2525 [1 << 17]byte +var z2526 [1 << 17]byte +var z2527 [1 << 17]byte +var z2528 [1 << 17]byte +var z2529 [1 << 17]byte +var z2530 [1 << 17]byte +var z2531 [1 << 17]byte +var z2532 [1 << 17]byte +var z2533 [1 << 17]byte +var z2534 [1 << 17]byte +var z2535 [1 << 17]byte +var z2536 [1 << 17]byte +var z2537 [1 << 17]byte +var z2538 [1 << 17]byte +var z2539 [1 << 17]byte +var z2540 [1 << 17]byte +var z2541 [1 << 17]byte +var z2542 [1 << 17]byte +var z2543 [1 << 17]byte +var z2544 [1 << 17]byte +var z2545 [1 << 17]byte +var z2546 [1 << 17]byte +var z2547 [1 << 17]byte +var z2548 [1 << 17]byte +var z2549 [1 << 17]byte +var z2550 [1 << 17]byte +var z2551 [1 << 17]byte +var z2552 [1 << 17]byte +var z2553 [1 << 17]byte +var z2554 [1 << 17]byte +var z2555 [1 << 17]byte +var z2556 [1 << 17]byte +var z2557 [1 << 17]byte +var z2558 [1 << 17]byte +var z2559 [1 << 17]byte +var z2560 [1 << 17]byte +var z2561 [1 << 17]byte +var z2562 [1 << 17]byte +var z2563 [1 << 17]byte +var z2564 [1 << 17]byte +var z2565 [1 << 17]byte +var z2566 [1 << 17]byte +var z2567 [1 << 17]byte +var z2568 [1 << 17]byte +var z2569 [1 << 17]byte +var z2570 [1 << 17]byte +var z2571 [1 << 17]byte +var z2572 [1 << 17]byte +var z2573 [1 << 17]byte +var z2574 [1 << 17]byte +var z2575 [1 << 17]byte +var z2576 [1 << 17]byte +var z2577 [1 << 17]byte +var z2578 [1 << 17]byte +var z2579 [1 << 17]byte +var z2580 [1 << 17]byte +var z2581 [1 << 17]byte +var z2582 [1 << 17]byte +var z2583 [1 << 17]byte +var z2584 [1 << 17]byte +var z2585 [1 << 17]byte +var z2586 [1 << 17]byte +var z2587 [1 << 17]byte +var z2588 [1 << 17]byte +var z2589 [1 << 17]byte +var z2590 [1 << 17]byte +var z2591 [1 << 17]byte +var z2592 [1 << 17]byte +var z2593 [1 << 17]byte +var z2594 [1 << 17]byte +var z2595 [1 << 17]byte +var z2596 [1 << 17]byte +var z2597 [1 << 17]byte +var z2598 [1 << 17]byte +var z2599 [1 << 17]byte +var z2600 [1 << 17]byte +var z2601 [1 << 17]byte +var z2602 [1 << 17]byte +var z2603 [1 << 17]byte +var z2604 [1 << 17]byte +var z2605 [1 << 17]byte +var z2606 [1 << 17]byte +var z2607 [1 << 17]byte +var z2608 [1 << 17]byte +var z2609 [1 << 17]byte +var z2610 [1 << 17]byte +var z2611 [1 << 17]byte +var z2612 [1 << 17]byte +var z2613 [1 << 17]byte +var z2614 [1 << 17]byte +var z2615 [1 << 17]byte +var z2616 [1 << 17]byte +var z2617 [1 << 17]byte +var z2618 [1 << 17]byte +var z2619 [1 << 17]byte +var z2620 [1 << 17]byte +var z2621 [1 << 17]byte +var z2622 [1 << 17]byte +var z2623 [1 << 17]byte +var z2624 [1 << 17]byte +var z2625 [1 << 17]byte +var z2626 [1 << 17]byte +var z2627 [1 << 17]byte +var z2628 [1 << 17]byte +var z2629 [1 << 17]byte +var z2630 [1 << 17]byte +var z2631 [1 << 17]byte +var z2632 [1 << 17]byte +var z2633 [1 << 17]byte +var z2634 [1 << 17]byte +var z2635 [1 << 17]byte +var z2636 [1 << 17]byte +var z2637 [1 << 17]byte +var z2638 [1 << 17]byte +var z2639 [1 << 17]byte +var z2640 [1 << 17]byte +var z2641 [1 << 17]byte +var z2642 [1 << 17]byte +var z2643 [1 << 17]byte +var z2644 [1 << 17]byte +var z2645 [1 << 17]byte +var z2646 [1 << 17]byte +var z2647 [1 << 17]byte +var z2648 [1 << 17]byte +var z2649 [1 << 17]byte +var z2650 [1 << 17]byte +var z2651 [1 << 17]byte +var z2652 [1 << 17]byte +var z2653 [1 << 17]byte +var z2654 [1 << 17]byte +var z2655 [1 << 17]byte +var z2656 [1 << 17]byte +var z2657 [1 << 17]byte +var z2658 [1 << 17]byte +var z2659 [1 << 17]byte +var z2660 [1 << 17]byte +var z2661 [1 << 17]byte +var z2662 [1 << 17]byte +var z2663 [1 << 17]byte +var z2664 [1 << 17]byte +var z2665 [1 << 17]byte +var z2666 [1 << 17]byte +var z2667 [1 << 17]byte +var z2668 [1 << 17]byte +var z2669 [1 << 17]byte +var z2670 [1 << 17]byte +var z2671 [1 << 17]byte +var z2672 [1 << 17]byte +var z2673 [1 << 17]byte +var z2674 [1 << 17]byte +var z2675 [1 << 17]byte +var z2676 [1 << 17]byte +var z2677 [1 << 17]byte +var z2678 [1 << 17]byte +var z2679 [1 << 17]byte +var z2680 [1 << 17]byte +var z2681 [1 << 17]byte +var z2682 [1 << 17]byte +var z2683 [1 << 17]byte +var z2684 [1 << 17]byte +var z2685 [1 << 17]byte +var z2686 [1 << 17]byte +var z2687 [1 << 17]byte +var z2688 [1 << 17]byte +var z2689 [1 << 17]byte +var z2690 [1 << 17]byte +var z2691 [1 << 17]byte +var z2692 [1 << 17]byte +var z2693 [1 << 17]byte +var z2694 [1 << 17]byte +var z2695 [1 << 17]byte +var z2696 [1 << 17]byte +var z2697 [1 << 17]byte +var z2698 [1 << 17]byte +var z2699 [1 << 17]byte +var z2700 [1 << 17]byte +var z2701 [1 << 17]byte +var z2702 [1 << 17]byte +var z2703 [1 << 17]byte +var z2704 [1 << 17]byte +var z2705 [1 << 17]byte +var z2706 [1 << 17]byte +var z2707 [1 << 17]byte +var z2708 [1 << 17]byte +var z2709 [1 << 17]byte +var z2710 [1 << 17]byte +var z2711 [1 << 17]byte +var z2712 [1 << 17]byte +var z2713 [1 << 17]byte +var z2714 [1 << 17]byte +var z2715 [1 << 17]byte +var z2716 [1 << 17]byte +var z2717 [1 << 17]byte +var z2718 [1 << 17]byte +var z2719 [1 << 17]byte +var z2720 [1 << 17]byte +var z2721 [1 << 17]byte +var z2722 [1 << 17]byte +var z2723 [1 << 17]byte +var z2724 [1 << 17]byte +var z2725 [1 << 17]byte +var z2726 [1 << 17]byte +var z2727 [1 << 17]byte +var z2728 [1 << 17]byte +var z2729 [1 << 17]byte +var z2730 [1 << 17]byte +var z2731 [1 << 17]byte +var z2732 [1 << 17]byte +var z2733 [1 << 17]byte +var z2734 [1 << 17]byte +var z2735 [1 << 17]byte +var z2736 [1 << 17]byte +var z2737 [1 << 17]byte +var z2738 [1 << 17]byte +var z2739 [1 << 17]byte +var z2740 [1 << 17]byte +var z2741 [1 << 17]byte +var z2742 [1 << 17]byte +var z2743 [1 << 17]byte +var z2744 [1 << 17]byte +var z2745 [1 << 17]byte +var z2746 [1 << 17]byte +var z2747 [1 << 17]byte +var z2748 [1 << 17]byte +var z2749 [1 << 17]byte +var z2750 [1 << 17]byte +var z2751 [1 << 17]byte +var z2752 [1 << 17]byte +var z2753 [1 << 17]byte +var z2754 [1 << 17]byte +var z2755 [1 << 17]byte +var z2756 [1 << 17]byte +var z2757 [1 << 17]byte +var z2758 [1 << 17]byte +var z2759 [1 << 17]byte +var z2760 [1 << 17]byte +var z2761 [1 << 17]byte +var z2762 [1 << 17]byte +var z2763 [1 << 17]byte +var z2764 [1 << 17]byte +var z2765 [1 << 17]byte +var z2766 [1 << 17]byte +var z2767 [1 << 17]byte +var z2768 [1 << 17]byte +var z2769 [1 << 17]byte +var z2770 [1 << 17]byte +var z2771 [1 << 17]byte +var z2772 [1 << 17]byte +var z2773 [1 << 17]byte +var z2774 [1 << 17]byte +var z2775 [1 << 17]byte +var z2776 [1 << 17]byte +var z2777 [1 << 17]byte +var z2778 [1 << 17]byte +var z2779 [1 << 17]byte +var z2780 [1 << 17]byte +var z2781 [1 << 17]byte +var z2782 [1 << 17]byte +var z2783 [1 << 17]byte +var z2784 [1 << 17]byte +var z2785 [1 << 17]byte +var z2786 [1 << 17]byte +var z2787 [1 << 17]byte +var z2788 [1 << 17]byte +var z2789 [1 << 17]byte +var z2790 [1 << 17]byte +var z2791 [1 << 17]byte +var z2792 [1 << 17]byte +var z2793 [1 << 17]byte +var z2794 [1 << 17]byte +var z2795 [1 << 17]byte +var z2796 [1 << 17]byte +var z2797 [1 << 17]byte +var z2798 [1 << 17]byte +var z2799 [1 << 17]byte +var z2800 [1 << 17]byte +var z2801 [1 << 17]byte +var z2802 [1 << 17]byte +var z2803 [1 << 17]byte +var z2804 [1 << 17]byte +var z2805 [1 << 17]byte +var z2806 [1 << 17]byte +var z2807 [1 << 17]byte +var z2808 [1 << 17]byte +var z2809 [1 << 17]byte +var z2810 [1 << 17]byte +var z2811 [1 << 17]byte +var z2812 [1 << 17]byte +var z2813 [1 << 17]byte +var z2814 [1 << 17]byte +var z2815 [1 << 17]byte +var z2816 [1 << 17]byte +var z2817 [1 << 17]byte +var z2818 [1 << 17]byte +var z2819 [1 << 17]byte +var z2820 [1 << 17]byte +var z2821 [1 << 17]byte +var z2822 [1 << 17]byte +var z2823 [1 << 17]byte +var z2824 [1 << 17]byte +var z2825 [1 << 17]byte +var z2826 [1 << 17]byte +var z2827 [1 << 17]byte +var z2828 [1 << 17]byte +var z2829 [1 << 17]byte +var z2830 [1 << 17]byte +var z2831 [1 << 17]byte +var z2832 [1 << 17]byte +var z2833 [1 << 17]byte +var z2834 [1 << 17]byte +var z2835 [1 << 17]byte +var z2836 [1 << 17]byte +var z2837 [1 << 17]byte +var z2838 [1 << 17]byte +var z2839 [1 << 17]byte +var z2840 [1 << 17]byte +var z2841 [1 << 17]byte +var z2842 [1 << 17]byte +var z2843 [1 << 17]byte +var z2844 [1 << 17]byte +var z2845 [1 << 17]byte +var z2846 [1 << 17]byte +var z2847 [1 << 17]byte +var z2848 [1 << 17]byte +var z2849 [1 << 17]byte +var z2850 [1 << 17]byte +var z2851 [1 << 17]byte +var z2852 [1 << 17]byte +var z2853 [1 << 17]byte +var z2854 [1 << 17]byte +var z2855 [1 << 17]byte +var z2856 [1 << 17]byte +var z2857 [1 << 17]byte +var z2858 [1 << 17]byte +var z2859 [1 << 17]byte +var z2860 [1 << 17]byte +var z2861 [1 << 17]byte +var z2862 [1 << 17]byte +var z2863 [1 << 17]byte +var z2864 [1 << 17]byte +var z2865 [1 << 17]byte +var z2866 [1 << 17]byte +var z2867 [1 << 17]byte +var z2868 [1 << 17]byte +var z2869 [1 << 17]byte +var z2870 [1 << 17]byte +var z2871 [1 << 17]byte +var z2872 [1 << 17]byte +var z2873 [1 << 17]byte +var z2874 [1 << 17]byte +var z2875 [1 << 17]byte +var z2876 [1 << 17]byte +var z2877 [1 << 17]byte +var z2878 [1 << 17]byte +var z2879 [1 << 17]byte +var z2880 [1 << 17]byte +var z2881 [1 << 17]byte +var z2882 [1 << 17]byte +var z2883 [1 << 17]byte +var z2884 [1 << 17]byte +var z2885 [1 << 17]byte +var z2886 [1 << 17]byte +var z2887 [1 << 17]byte +var z2888 [1 << 17]byte +var z2889 [1 << 17]byte +var z2890 [1 << 17]byte +var z2891 [1 << 17]byte +var z2892 [1 << 17]byte +var z2893 [1 << 17]byte +var z2894 [1 << 17]byte +var z2895 [1 << 17]byte +var z2896 [1 << 17]byte +var z2897 [1 << 17]byte +var z2898 [1 << 17]byte +var z2899 [1 << 17]byte +var z2900 [1 << 17]byte +var z2901 [1 << 17]byte +var z2902 [1 << 17]byte +var z2903 [1 << 17]byte +var z2904 [1 << 17]byte +var z2905 [1 << 17]byte +var z2906 [1 << 17]byte +var z2907 [1 << 17]byte +var z2908 [1 << 17]byte +var z2909 [1 << 17]byte +var z2910 [1 << 17]byte +var z2911 [1 << 17]byte +var z2912 [1 << 17]byte +var z2913 [1 << 17]byte +var z2914 [1 << 17]byte +var z2915 [1 << 17]byte +var z2916 [1 << 17]byte +var z2917 [1 << 17]byte +var z2918 [1 << 17]byte +var z2919 [1 << 17]byte +var z2920 [1 << 17]byte +var z2921 [1 << 17]byte +var z2922 [1 << 17]byte +var z2923 [1 << 17]byte +var z2924 [1 << 17]byte +var z2925 [1 << 17]byte +var z2926 [1 << 17]byte +var z2927 [1 << 17]byte +var z2928 [1 << 17]byte +var z2929 [1 << 17]byte +var z2930 [1 << 17]byte +var z2931 [1 << 17]byte +var z2932 [1 << 17]byte +var z2933 [1 << 17]byte +var z2934 [1 << 17]byte +var z2935 [1 << 17]byte +var z2936 [1 << 17]byte +var z2937 [1 << 17]byte +var z2938 [1 << 17]byte +var z2939 [1 << 17]byte +var z2940 [1 << 17]byte +var z2941 [1 << 17]byte +var z2942 [1 << 17]byte +var z2943 [1 << 17]byte +var z2944 [1 << 17]byte +var z2945 [1 << 17]byte +var z2946 [1 << 17]byte +var z2947 [1 << 17]byte +var z2948 [1 << 17]byte +var z2949 [1 << 17]byte +var z2950 [1 << 17]byte +var z2951 [1 << 17]byte +var z2952 [1 << 17]byte +var z2953 [1 << 17]byte +var z2954 [1 << 17]byte +var z2955 [1 << 17]byte +var z2956 [1 << 17]byte +var z2957 [1 << 17]byte +var z2958 [1 << 17]byte +var z2959 [1 << 17]byte +var z2960 [1 << 17]byte +var z2961 [1 << 17]byte +var z2962 [1 << 17]byte +var z2963 [1 << 17]byte +var z2964 [1 << 17]byte +var z2965 [1 << 17]byte +var z2966 [1 << 17]byte +var z2967 [1 << 17]byte +var z2968 [1 << 17]byte +var z2969 [1 << 17]byte +var z2970 [1 << 17]byte +var z2971 [1 << 17]byte +var z2972 [1 << 17]byte +var z2973 [1 << 17]byte +var z2974 [1 << 17]byte +var z2975 [1 << 17]byte +var z2976 [1 << 17]byte +var z2977 [1 << 17]byte +var z2978 [1 << 17]byte +var z2979 [1 << 17]byte +var z2980 [1 << 17]byte +var z2981 [1 << 17]byte +var z2982 [1 << 17]byte +var z2983 [1 << 17]byte +var z2984 [1 << 17]byte +var z2985 [1 << 17]byte +var z2986 [1 << 17]byte +var z2987 [1 << 17]byte +var z2988 [1 << 17]byte +var z2989 [1 << 17]byte +var z2990 [1 << 17]byte +var z2991 [1 << 17]byte +var z2992 [1 << 17]byte +var z2993 [1 << 17]byte +var z2994 [1 << 17]byte +var z2995 [1 << 17]byte +var z2996 [1 << 17]byte +var z2997 [1 << 17]byte +var z2998 [1 << 17]byte +var z2999 [1 << 17]byte +var z3000 [1 << 17]byte +var z3001 [1 << 17]byte +var z3002 [1 << 17]byte +var z3003 [1 << 17]byte +var z3004 [1 << 17]byte +var z3005 [1 << 17]byte +var z3006 [1 << 17]byte +var z3007 [1 << 17]byte +var z3008 [1 << 17]byte +var z3009 [1 << 17]byte +var z3010 [1 << 17]byte +var z3011 [1 << 17]byte +var z3012 [1 << 17]byte +var z3013 [1 << 17]byte +var z3014 [1 << 17]byte +var z3015 [1 << 17]byte +var z3016 [1 << 17]byte +var z3017 [1 << 17]byte +var z3018 [1 << 17]byte +var z3019 [1 << 17]byte +var z3020 [1 << 17]byte +var z3021 [1 << 17]byte +var z3022 [1 << 17]byte +var z3023 [1 << 17]byte +var z3024 [1 << 17]byte +var z3025 [1 << 17]byte +var z3026 [1 << 17]byte +var z3027 [1 << 17]byte +var z3028 [1 << 17]byte +var z3029 [1 << 17]byte +var z3030 [1 << 17]byte +var z3031 [1 << 17]byte +var z3032 [1 << 17]byte +var z3033 [1 << 17]byte +var z3034 [1 << 17]byte +var z3035 [1 << 17]byte +var z3036 [1 << 17]byte +var z3037 [1 << 17]byte +var z3038 [1 << 17]byte +var z3039 [1 << 17]byte +var z3040 [1 << 17]byte +var z3041 [1 << 17]byte +var z3042 [1 << 17]byte +var z3043 [1 << 17]byte +var z3044 [1 << 17]byte +var z3045 [1 << 17]byte +var z3046 [1 << 17]byte +var z3047 [1 << 17]byte +var z3048 [1 << 17]byte +var z3049 [1 << 17]byte +var z3050 [1 << 17]byte +var z3051 [1 << 17]byte +var z3052 [1 << 17]byte +var z3053 [1 << 17]byte +var z3054 [1 << 17]byte +var z3055 [1 << 17]byte +var z3056 [1 << 17]byte +var z3057 [1 << 17]byte +var z3058 [1 << 17]byte +var z3059 [1 << 17]byte +var z3060 [1 << 17]byte +var z3061 [1 << 17]byte +var z3062 [1 << 17]byte +var z3063 [1 << 17]byte +var z3064 [1 << 17]byte +var z3065 [1 << 17]byte +var z3066 [1 << 17]byte +var z3067 [1 << 17]byte +var z3068 [1 << 17]byte +var z3069 [1 << 17]byte +var z3070 [1 << 17]byte +var z3071 [1 << 17]byte +var z3072 [1 << 17]byte +var z3073 [1 << 17]byte +var z3074 [1 << 17]byte +var z3075 [1 << 17]byte +var z3076 [1 << 17]byte +var z3077 [1 << 17]byte +var z3078 [1 << 17]byte +var z3079 [1 << 17]byte +var z3080 [1 << 17]byte +var z3081 [1 << 17]byte +var z3082 [1 << 17]byte +var z3083 [1 << 17]byte +var z3084 [1 << 17]byte +var z3085 [1 << 17]byte +var z3086 [1 << 17]byte +var z3087 [1 << 17]byte +var z3088 [1 << 17]byte +var z3089 [1 << 17]byte +var z3090 [1 << 17]byte +var z3091 [1 << 17]byte +var z3092 [1 << 17]byte +var z3093 [1 << 17]byte +var z3094 [1 << 17]byte +var z3095 [1 << 17]byte +var z3096 [1 << 17]byte +var z3097 [1 << 17]byte +var z3098 [1 << 17]byte +var z3099 [1 << 17]byte +var z3100 [1 << 17]byte +var z3101 [1 << 17]byte +var z3102 [1 << 17]byte +var z3103 [1 << 17]byte +var z3104 [1 << 17]byte +var z3105 [1 << 17]byte +var z3106 [1 << 17]byte +var z3107 [1 << 17]byte +var z3108 [1 << 17]byte +var z3109 [1 << 17]byte +var z3110 [1 << 17]byte +var z3111 [1 << 17]byte +var z3112 [1 << 17]byte +var z3113 [1 << 17]byte +var z3114 [1 << 17]byte +var z3115 [1 << 17]byte +var z3116 [1 << 17]byte +var z3117 [1 << 17]byte +var z3118 [1 << 17]byte +var z3119 [1 << 17]byte +var z3120 [1 << 17]byte +var z3121 [1 << 17]byte +var z3122 [1 << 17]byte +var z3123 [1 << 17]byte +var z3124 [1 << 17]byte +var z3125 [1 << 17]byte +var z3126 [1 << 17]byte +var z3127 [1 << 17]byte +var z3128 [1 << 17]byte +var z3129 [1 << 17]byte +var z3130 [1 << 17]byte +var z3131 [1 << 17]byte +var z3132 [1 << 17]byte +var z3133 [1 << 17]byte +var z3134 [1 << 17]byte +var z3135 [1 << 17]byte +var z3136 [1 << 17]byte +var z3137 [1 << 17]byte +var z3138 [1 << 17]byte +var z3139 [1 << 17]byte +var z3140 [1 << 17]byte +var z3141 [1 << 17]byte +var z3142 [1 << 17]byte +var z3143 [1 << 17]byte +var z3144 [1 << 17]byte +var z3145 [1 << 17]byte +var z3146 [1 << 17]byte +var z3147 [1 << 17]byte +var z3148 [1 << 17]byte +var z3149 [1 << 17]byte +var z3150 [1 << 17]byte +var z3151 [1 << 17]byte +var z3152 [1 << 17]byte +var z3153 [1 << 17]byte +var z3154 [1 << 17]byte +var z3155 [1 << 17]byte +var z3156 [1 << 17]byte +var z3157 [1 << 17]byte +var z3158 [1 << 17]byte +var z3159 [1 << 17]byte +var z3160 [1 << 17]byte +var z3161 [1 << 17]byte +var z3162 [1 << 17]byte +var z3163 [1 << 17]byte +var z3164 [1 << 17]byte +var z3165 [1 << 17]byte +var z3166 [1 << 17]byte +var z3167 [1 << 17]byte +var z3168 [1 << 17]byte +var z3169 [1 << 17]byte +var z3170 [1 << 17]byte +var z3171 [1 << 17]byte +var z3172 [1 << 17]byte +var z3173 [1 << 17]byte +var z3174 [1 << 17]byte +var z3175 [1 << 17]byte +var z3176 [1 << 17]byte +var z3177 [1 << 17]byte +var z3178 [1 << 17]byte +var z3179 [1 << 17]byte +var z3180 [1 << 17]byte +var z3181 [1 << 17]byte +var z3182 [1 << 17]byte +var z3183 [1 << 17]byte +var z3184 [1 << 17]byte +var z3185 [1 << 17]byte +var z3186 [1 << 17]byte +var z3187 [1 << 17]byte +var z3188 [1 << 17]byte +var z3189 [1 << 17]byte +var z3190 [1 << 17]byte +var z3191 [1 << 17]byte +var z3192 [1 << 17]byte +var z3193 [1 << 17]byte +var z3194 [1 << 17]byte +var z3195 [1 << 17]byte +var z3196 [1 << 17]byte +var z3197 [1 << 17]byte +var z3198 [1 << 17]byte +var z3199 [1 << 17]byte +var z3200 [1 << 17]byte +var z3201 [1 << 17]byte +var z3202 [1 << 17]byte +var z3203 [1 << 17]byte +var z3204 [1 << 17]byte +var z3205 [1 << 17]byte +var z3206 [1 << 17]byte +var z3207 [1 << 17]byte +var z3208 [1 << 17]byte +var z3209 [1 << 17]byte +var z3210 [1 << 17]byte +var z3211 [1 << 17]byte +var z3212 [1 << 17]byte +var z3213 [1 << 17]byte +var z3214 [1 << 17]byte +var z3215 [1 << 17]byte +var z3216 [1 << 17]byte +var z3217 [1 << 17]byte +var z3218 [1 << 17]byte +var z3219 [1 << 17]byte +var z3220 [1 << 17]byte +var z3221 [1 << 17]byte +var z3222 [1 << 17]byte +var z3223 [1 << 17]byte +var z3224 [1 << 17]byte +var z3225 [1 << 17]byte +var z3226 [1 << 17]byte +var z3227 [1 << 17]byte +var z3228 [1 << 17]byte +var z3229 [1 << 17]byte +var z3230 [1 << 17]byte +var z3231 [1 << 17]byte +var z3232 [1 << 17]byte +var z3233 [1 << 17]byte +var z3234 [1 << 17]byte +var z3235 [1 << 17]byte +var z3236 [1 << 17]byte +var z3237 [1 << 17]byte +var z3238 [1 << 17]byte +var z3239 [1 << 17]byte +var z3240 [1 << 17]byte +var z3241 [1 << 17]byte +var z3242 [1 << 17]byte +var z3243 [1 << 17]byte +var z3244 [1 << 17]byte +var z3245 [1 << 17]byte +var z3246 [1 << 17]byte +var z3247 [1 << 17]byte +var z3248 [1 << 17]byte +var z3249 [1 << 17]byte +var z3250 [1 << 17]byte +var z3251 [1 << 17]byte +var z3252 [1 << 17]byte +var z3253 [1 << 17]byte +var z3254 [1 << 17]byte +var z3255 [1 << 17]byte +var z3256 [1 << 17]byte +var z3257 [1 << 17]byte +var z3258 [1 << 17]byte +var z3259 [1 << 17]byte +var z3260 [1 << 17]byte +var z3261 [1 << 17]byte +var z3262 [1 << 17]byte +var z3263 [1 << 17]byte +var z3264 [1 << 17]byte +var z3265 [1 << 17]byte +var z3266 [1 << 17]byte +var z3267 [1 << 17]byte +var z3268 [1 << 17]byte +var z3269 [1 << 17]byte +var z3270 [1 << 17]byte +var z3271 [1 << 17]byte +var z3272 [1 << 17]byte +var z3273 [1 << 17]byte +var z3274 [1 << 17]byte +var z3275 [1 << 17]byte +var z3276 [1 << 17]byte +var z3277 [1 << 17]byte +var z3278 [1 << 17]byte +var z3279 [1 << 17]byte +var z3280 [1 << 17]byte +var z3281 [1 << 17]byte +var z3282 [1 << 17]byte +var z3283 [1 << 17]byte +var z3284 [1 << 17]byte +var z3285 [1 << 17]byte +var z3286 [1 << 17]byte +var z3287 [1 << 17]byte +var z3288 [1 << 17]byte +var z3289 [1 << 17]byte +var z3290 [1 << 17]byte +var z3291 [1 << 17]byte +var z3292 [1 << 17]byte +var z3293 [1 << 17]byte +var z3294 [1 << 17]byte +var z3295 [1 << 17]byte +var z3296 [1 << 17]byte +var z3297 [1 << 17]byte +var z3298 [1 << 17]byte +var z3299 [1 << 17]byte +var z3300 [1 << 17]byte +var z3301 [1 << 17]byte +var z3302 [1 << 17]byte +var z3303 [1 << 17]byte +var z3304 [1 << 17]byte +var z3305 [1 << 17]byte +var z3306 [1 << 17]byte +var z3307 [1 << 17]byte +var z3308 [1 << 17]byte +var z3309 [1 << 17]byte +var z3310 [1 << 17]byte +var z3311 [1 << 17]byte +var z3312 [1 << 17]byte +var z3313 [1 << 17]byte +var z3314 [1 << 17]byte +var z3315 [1 << 17]byte +var z3316 [1 << 17]byte +var z3317 [1 << 17]byte +var z3318 [1 << 17]byte +var z3319 [1 << 17]byte +var z3320 [1 << 17]byte +var z3321 [1 << 17]byte +var z3322 [1 << 17]byte +var z3323 [1 << 17]byte +var z3324 [1 << 17]byte +var z3325 [1 << 17]byte +var z3326 [1 << 17]byte +var z3327 [1 << 17]byte +var z3328 [1 << 17]byte +var z3329 [1 << 17]byte +var z3330 [1 << 17]byte +var z3331 [1 << 17]byte +var z3332 [1 << 17]byte +var z3333 [1 << 17]byte +var z3334 [1 << 17]byte +var z3335 [1 << 17]byte +var z3336 [1 << 17]byte +var z3337 [1 << 17]byte +var z3338 [1 << 17]byte +var z3339 [1 << 17]byte +var z3340 [1 << 17]byte +var z3341 [1 << 17]byte +var z3342 [1 << 17]byte +var z3343 [1 << 17]byte +var z3344 [1 << 17]byte +var z3345 [1 << 17]byte +var z3346 [1 << 17]byte +var z3347 [1 << 17]byte +var z3348 [1 << 17]byte +var z3349 [1 << 17]byte +var z3350 [1 << 17]byte +var z3351 [1 << 17]byte +var z3352 [1 << 17]byte +var z3353 [1 << 17]byte +var z3354 [1 << 17]byte +var z3355 [1 << 17]byte +var z3356 [1 << 17]byte +var z3357 [1 << 17]byte +var z3358 [1 << 17]byte +var z3359 [1 << 17]byte +var z3360 [1 << 17]byte +var z3361 [1 << 17]byte +var z3362 [1 << 17]byte +var z3363 [1 << 17]byte +var z3364 [1 << 17]byte +var z3365 [1 << 17]byte +var z3366 [1 << 17]byte +var z3367 [1 << 17]byte +var z3368 [1 << 17]byte +var z3369 [1 << 17]byte +var z3370 [1 << 17]byte +var z3371 [1 << 17]byte +var z3372 [1 << 17]byte +var z3373 [1 << 17]byte +var z3374 [1 << 17]byte +var z3375 [1 << 17]byte +var z3376 [1 << 17]byte +var z3377 [1 << 17]byte +var z3378 [1 << 17]byte +var z3379 [1 << 17]byte +var z3380 [1 << 17]byte +var z3381 [1 << 17]byte +var z3382 [1 << 17]byte +var z3383 [1 << 17]byte +var z3384 [1 << 17]byte +var z3385 [1 << 17]byte +var z3386 [1 << 17]byte +var z3387 [1 << 17]byte +var z3388 [1 << 17]byte +var z3389 [1 << 17]byte +var z3390 [1 << 17]byte +var z3391 [1 << 17]byte +var z3392 [1 << 17]byte +var z3393 [1 << 17]byte +var z3394 [1 << 17]byte +var z3395 [1 << 17]byte +var z3396 [1 << 17]byte +var z3397 [1 << 17]byte +var z3398 [1 << 17]byte +var z3399 [1 << 17]byte +var z3400 [1 << 17]byte +var z3401 [1 << 17]byte +var z3402 [1 << 17]byte +var z3403 [1 << 17]byte +var z3404 [1 << 17]byte +var z3405 [1 << 17]byte +var z3406 [1 << 17]byte +var z3407 [1 << 17]byte +var z3408 [1 << 17]byte +var z3409 [1 << 17]byte +var z3410 [1 << 17]byte +var z3411 [1 << 17]byte +var z3412 [1 << 17]byte +var z3413 [1 << 17]byte +var z3414 [1 << 17]byte +var z3415 [1 << 17]byte +var z3416 [1 << 17]byte +var z3417 [1 << 17]byte +var z3418 [1 << 17]byte +var z3419 [1 << 17]byte +var z3420 [1 << 17]byte +var z3421 [1 << 17]byte +var z3422 [1 << 17]byte +var z3423 [1 << 17]byte +var z3424 [1 << 17]byte +var z3425 [1 << 17]byte +var z3426 [1 << 17]byte +var z3427 [1 << 17]byte +var z3428 [1 << 17]byte +var z3429 [1 << 17]byte +var z3430 [1 << 17]byte +var z3431 [1 << 17]byte +var z3432 [1 << 17]byte +var z3433 [1 << 17]byte +var z3434 [1 << 17]byte +var z3435 [1 << 17]byte +var z3436 [1 << 17]byte +var z3437 [1 << 17]byte +var z3438 [1 << 17]byte +var z3439 [1 << 17]byte +var z3440 [1 << 17]byte +var z3441 [1 << 17]byte +var z3442 [1 << 17]byte +var z3443 [1 << 17]byte +var z3444 [1 << 17]byte +var z3445 [1 << 17]byte +var z3446 [1 << 17]byte +var z3447 [1 << 17]byte +var z3448 [1 << 17]byte +var z3449 [1 << 17]byte +var z3450 [1 << 17]byte +var z3451 [1 << 17]byte +var z3452 [1 << 17]byte +var z3453 [1 << 17]byte +var z3454 [1 << 17]byte +var z3455 [1 << 17]byte +var z3456 [1 << 17]byte +var z3457 [1 << 17]byte +var z3458 [1 << 17]byte +var z3459 [1 << 17]byte +var z3460 [1 << 17]byte +var z3461 [1 << 17]byte +var z3462 [1 << 17]byte +var z3463 [1 << 17]byte +var z3464 [1 << 17]byte +var z3465 [1 << 17]byte +var z3466 [1 << 17]byte +var z3467 [1 << 17]byte +var z3468 [1 << 17]byte +var z3469 [1 << 17]byte +var z3470 [1 << 17]byte +var z3471 [1 << 17]byte +var z3472 [1 << 17]byte +var z3473 [1 << 17]byte +var z3474 [1 << 17]byte +var z3475 [1 << 17]byte +var z3476 [1 << 17]byte +var z3477 [1 << 17]byte +var z3478 [1 << 17]byte +var z3479 [1 << 17]byte +var z3480 [1 << 17]byte +var z3481 [1 << 17]byte +var z3482 [1 << 17]byte +var z3483 [1 << 17]byte +var z3484 [1 << 17]byte +var z3485 [1 << 17]byte +var z3486 [1 << 17]byte +var z3487 [1 << 17]byte +var z3488 [1 << 17]byte +var z3489 [1 << 17]byte +var z3490 [1 << 17]byte +var z3491 [1 << 17]byte +var z3492 [1 << 17]byte +var z3493 [1 << 17]byte +var z3494 [1 << 17]byte +var z3495 [1 << 17]byte +var z3496 [1 << 17]byte +var z3497 [1 << 17]byte +var z3498 [1 << 17]byte +var z3499 [1 << 17]byte +var z3500 [1 << 17]byte +var z3501 [1 << 17]byte +var z3502 [1 << 17]byte +var z3503 [1 << 17]byte +var z3504 [1 << 17]byte +var z3505 [1 << 17]byte +var z3506 [1 << 17]byte +var z3507 [1 << 17]byte +var z3508 [1 << 17]byte +var z3509 [1 << 17]byte +var z3510 [1 << 17]byte +var z3511 [1 << 17]byte +var z3512 [1 << 17]byte +var z3513 [1 << 17]byte +var z3514 [1 << 17]byte +var z3515 [1 << 17]byte +var z3516 [1 << 17]byte +var z3517 [1 << 17]byte +var z3518 [1 << 17]byte +var z3519 [1 << 17]byte +var z3520 [1 << 17]byte +var z3521 [1 << 17]byte +var z3522 [1 << 17]byte +var z3523 [1 << 17]byte +var z3524 [1 << 17]byte +var z3525 [1 << 17]byte +var z3526 [1 << 17]byte +var z3527 [1 << 17]byte +var z3528 [1 << 17]byte +var z3529 [1 << 17]byte +var z3530 [1 << 17]byte +var z3531 [1 << 17]byte +var z3532 [1 << 17]byte +var z3533 [1 << 17]byte +var z3534 [1 << 17]byte +var z3535 [1 << 17]byte +var z3536 [1 << 17]byte +var z3537 [1 << 17]byte +var z3538 [1 << 17]byte +var z3539 [1 << 17]byte +var z3540 [1 << 17]byte +var z3541 [1 << 17]byte +var z3542 [1 << 17]byte +var z3543 [1 << 17]byte +var z3544 [1 << 17]byte +var z3545 [1 << 17]byte +var z3546 [1 << 17]byte +var z3547 [1 << 17]byte +var z3548 [1 << 17]byte +var z3549 [1 << 17]byte +var z3550 [1 << 17]byte +var z3551 [1 << 17]byte +var z3552 [1 << 17]byte +var z3553 [1 << 17]byte +var z3554 [1 << 17]byte +var z3555 [1 << 17]byte +var z3556 [1 << 17]byte +var z3557 [1 << 17]byte +var z3558 [1 << 17]byte +var z3559 [1 << 17]byte +var z3560 [1 << 17]byte +var z3561 [1 << 17]byte +var z3562 [1 << 17]byte +var z3563 [1 << 17]byte +var z3564 [1 << 17]byte +var z3565 [1 << 17]byte +var z3566 [1 << 17]byte +var z3567 [1 << 17]byte +var z3568 [1 << 17]byte +var z3569 [1 << 17]byte +var z3570 [1 << 17]byte +var z3571 [1 << 17]byte +var z3572 [1 << 17]byte +var z3573 [1 << 17]byte +var z3574 [1 << 17]byte +var z3575 [1 << 17]byte +var z3576 [1 << 17]byte +var z3577 [1 << 17]byte +var z3578 [1 << 17]byte +var z3579 [1 << 17]byte +var z3580 [1 << 17]byte +var z3581 [1 << 17]byte +var z3582 [1 << 17]byte +var z3583 [1 << 17]byte +var z3584 [1 << 17]byte +var z3585 [1 << 17]byte +var z3586 [1 << 17]byte +var z3587 [1 << 17]byte +var z3588 [1 << 17]byte +var z3589 [1 << 17]byte +var z3590 [1 << 17]byte +var z3591 [1 << 17]byte +var z3592 [1 << 17]byte +var z3593 [1 << 17]byte +var z3594 [1 << 17]byte +var z3595 [1 << 17]byte +var z3596 [1 << 17]byte +var z3597 [1 << 17]byte +var z3598 [1 << 17]byte +var z3599 [1 << 17]byte +var z3600 [1 << 17]byte +var z3601 [1 << 17]byte +var z3602 [1 << 17]byte +var z3603 [1 << 17]byte +var z3604 [1 << 17]byte +var z3605 [1 << 17]byte +var z3606 [1 << 17]byte +var z3607 [1 << 17]byte +var z3608 [1 << 17]byte +var z3609 [1 << 17]byte +var z3610 [1 << 17]byte +var z3611 [1 << 17]byte +var z3612 [1 << 17]byte +var z3613 [1 << 17]byte +var z3614 [1 << 17]byte +var z3615 [1 << 17]byte +var z3616 [1 << 17]byte +var z3617 [1 << 17]byte +var z3618 [1 << 17]byte +var z3619 [1 << 17]byte +var z3620 [1 << 17]byte +var z3621 [1 << 17]byte +var z3622 [1 << 17]byte +var z3623 [1 << 17]byte +var z3624 [1 << 17]byte +var z3625 [1 << 17]byte +var z3626 [1 << 17]byte +var z3627 [1 << 17]byte +var z3628 [1 << 17]byte +var z3629 [1 << 17]byte +var z3630 [1 << 17]byte +var z3631 [1 << 17]byte +var z3632 [1 << 17]byte +var z3633 [1 << 17]byte +var z3634 [1 << 17]byte +var z3635 [1 << 17]byte +var z3636 [1 << 17]byte +var z3637 [1 << 17]byte +var z3638 [1 << 17]byte +var z3639 [1 << 17]byte +var z3640 [1 << 17]byte +var z3641 [1 << 17]byte +var z3642 [1 << 17]byte +var z3643 [1 << 17]byte +var z3644 [1 << 17]byte +var z3645 [1 << 17]byte +var z3646 [1 << 17]byte +var z3647 [1 << 17]byte +var z3648 [1 << 17]byte +var z3649 [1 << 17]byte +var z3650 [1 << 17]byte +var z3651 [1 << 17]byte +var z3652 [1 << 17]byte +var z3653 [1 << 17]byte +var z3654 [1 << 17]byte +var z3655 [1 << 17]byte +var z3656 [1 << 17]byte +var z3657 [1 << 17]byte +var z3658 [1 << 17]byte +var z3659 [1 << 17]byte +var z3660 [1 << 17]byte +var z3661 [1 << 17]byte +var z3662 [1 << 17]byte +var z3663 [1 << 17]byte +var z3664 [1 << 17]byte +var z3665 [1 << 17]byte +var z3666 [1 << 17]byte +var z3667 [1 << 17]byte +var z3668 [1 << 17]byte +var z3669 [1 << 17]byte +var z3670 [1 << 17]byte +var z3671 [1 << 17]byte +var z3672 [1 << 17]byte +var z3673 [1 << 17]byte +var z3674 [1 << 17]byte +var z3675 [1 << 17]byte +var z3676 [1 << 17]byte +var z3677 [1 << 17]byte +var z3678 [1 << 17]byte +var z3679 [1 << 17]byte +var z3680 [1 << 17]byte +var z3681 [1 << 17]byte +var z3682 [1 << 17]byte +var z3683 [1 << 17]byte +var z3684 [1 << 17]byte +var z3685 [1 << 17]byte +var z3686 [1 << 17]byte +var z3687 [1 << 17]byte +var z3688 [1 << 17]byte +var z3689 [1 << 17]byte +var z3690 [1 << 17]byte +var z3691 [1 << 17]byte +var z3692 [1 << 17]byte +var z3693 [1 << 17]byte +var z3694 [1 << 17]byte +var z3695 [1 << 17]byte +var z3696 [1 << 17]byte +var z3697 [1 << 17]byte +var z3698 [1 << 17]byte +var z3699 [1 << 17]byte +var z3700 [1 << 17]byte +var z3701 [1 << 17]byte +var z3702 [1 << 17]byte +var z3703 [1 << 17]byte +var z3704 [1 << 17]byte +var z3705 [1 << 17]byte +var z3706 [1 << 17]byte +var z3707 [1 << 17]byte +var z3708 [1 << 17]byte +var z3709 [1 << 17]byte +var z3710 [1 << 17]byte +var z3711 [1 << 17]byte +var z3712 [1 << 17]byte +var z3713 [1 << 17]byte +var z3714 [1 << 17]byte +var z3715 [1 << 17]byte +var z3716 [1 << 17]byte +var z3717 [1 << 17]byte +var z3718 [1 << 17]byte +var z3719 [1 << 17]byte +var z3720 [1 << 17]byte +var z3721 [1 << 17]byte +var z3722 [1 << 17]byte +var z3723 [1 << 17]byte +var z3724 [1 << 17]byte +var z3725 [1 << 17]byte +var z3726 [1 << 17]byte +var z3727 [1 << 17]byte +var z3728 [1 << 17]byte +var z3729 [1 << 17]byte +var z3730 [1 << 17]byte +var z3731 [1 << 17]byte +var z3732 [1 << 17]byte +var z3733 [1 << 17]byte +var z3734 [1 << 17]byte +var z3735 [1 << 17]byte +var z3736 [1 << 17]byte +var z3737 [1 << 17]byte +var z3738 [1 << 17]byte +var z3739 [1 << 17]byte +var z3740 [1 << 17]byte +var z3741 [1 << 17]byte +var z3742 [1 << 17]byte +var z3743 [1 << 17]byte +var z3744 [1 << 17]byte +var z3745 [1 << 17]byte +var z3746 [1 << 17]byte +var z3747 [1 << 17]byte +var z3748 [1 << 17]byte +var z3749 [1 << 17]byte +var z3750 [1 << 17]byte +var z3751 [1 << 17]byte +var z3752 [1 << 17]byte +var z3753 [1 << 17]byte +var z3754 [1 << 17]byte +var z3755 [1 << 17]byte +var z3756 [1 << 17]byte +var z3757 [1 << 17]byte +var z3758 [1 << 17]byte +var z3759 [1 << 17]byte +var z3760 [1 << 17]byte +var z3761 [1 << 17]byte +var z3762 [1 << 17]byte +var z3763 [1 << 17]byte +var z3764 [1 << 17]byte +var z3765 [1 << 17]byte +var z3766 [1 << 17]byte +var z3767 [1 << 17]byte +var z3768 [1 << 17]byte +var z3769 [1 << 17]byte +var z3770 [1 << 17]byte +var z3771 [1 << 17]byte +var z3772 [1 << 17]byte +var z3773 [1 << 17]byte +var z3774 [1 << 17]byte +var z3775 [1 << 17]byte +var z3776 [1 << 17]byte +var z3777 [1 << 17]byte +var z3778 [1 << 17]byte +var z3779 [1 << 17]byte +var z3780 [1 << 17]byte +var z3781 [1 << 17]byte +var z3782 [1 << 17]byte +var z3783 [1 << 17]byte +var z3784 [1 << 17]byte +var z3785 [1 << 17]byte +var z3786 [1 << 17]byte +var z3787 [1 << 17]byte +var z3788 [1 << 17]byte +var z3789 [1 << 17]byte +var z3790 [1 << 17]byte +var z3791 [1 << 17]byte +var z3792 [1 << 17]byte +var z3793 [1 << 17]byte +var z3794 [1 << 17]byte +var z3795 [1 << 17]byte +var z3796 [1 << 17]byte +var z3797 [1 << 17]byte +var z3798 [1 << 17]byte +var z3799 [1 << 17]byte +var z3800 [1 << 17]byte +var z3801 [1 << 17]byte +var z3802 [1 << 17]byte +var z3803 [1 << 17]byte +var z3804 [1 << 17]byte +var z3805 [1 << 17]byte +var z3806 [1 << 17]byte +var z3807 [1 << 17]byte +var z3808 [1 << 17]byte +var z3809 [1 << 17]byte +var z3810 [1 << 17]byte +var z3811 [1 << 17]byte +var z3812 [1 << 17]byte +var z3813 [1 << 17]byte +var z3814 [1 << 17]byte +var z3815 [1 << 17]byte +var z3816 [1 << 17]byte +var z3817 [1 << 17]byte +var z3818 [1 << 17]byte +var z3819 [1 << 17]byte +var z3820 [1 << 17]byte +var z3821 [1 << 17]byte +var z3822 [1 << 17]byte +var z3823 [1 << 17]byte +var z3824 [1 << 17]byte +var z3825 [1 << 17]byte +var z3826 [1 << 17]byte +var z3827 [1 << 17]byte +var z3828 [1 << 17]byte +var z3829 [1 << 17]byte +var z3830 [1 << 17]byte +var z3831 [1 << 17]byte +var z3832 [1 << 17]byte +var z3833 [1 << 17]byte +var z3834 [1 << 17]byte +var z3835 [1 << 17]byte +var z3836 [1 << 17]byte +var z3837 [1 << 17]byte +var z3838 [1 << 17]byte +var z3839 [1 << 17]byte +var z3840 [1 << 17]byte +var z3841 [1 << 17]byte +var z3842 [1 << 17]byte +var z3843 [1 << 17]byte +var z3844 [1 << 17]byte +var z3845 [1 << 17]byte +var z3846 [1 << 17]byte +var z3847 [1 << 17]byte +var z3848 [1 << 17]byte +var z3849 [1 << 17]byte +var z3850 [1 << 17]byte +var z3851 [1 << 17]byte +var z3852 [1 << 17]byte +var z3853 [1 << 17]byte +var z3854 [1 << 17]byte +var z3855 [1 << 17]byte +var z3856 [1 << 17]byte +var z3857 [1 << 17]byte +var z3858 [1 << 17]byte +var z3859 [1 << 17]byte +var z3860 [1 << 17]byte +var z3861 [1 << 17]byte +var z3862 [1 << 17]byte +var z3863 [1 << 17]byte +var z3864 [1 << 17]byte +var z3865 [1 << 17]byte +var z3866 [1 << 17]byte +var z3867 [1 << 17]byte +var z3868 [1 << 17]byte +var z3869 [1 << 17]byte +var z3870 [1 << 17]byte +var z3871 [1 << 17]byte +var z3872 [1 << 17]byte +var z3873 [1 << 17]byte +var z3874 [1 << 17]byte +var z3875 [1 << 17]byte +var z3876 [1 << 17]byte +var z3877 [1 << 17]byte +var z3878 [1 << 17]byte +var z3879 [1 << 17]byte +var z3880 [1 << 17]byte +var z3881 [1 << 17]byte +var z3882 [1 << 17]byte +var z3883 [1 << 17]byte +var z3884 [1 << 17]byte +var z3885 [1 << 17]byte +var z3886 [1 << 17]byte +var z3887 [1 << 17]byte +var z3888 [1 << 17]byte +var z3889 [1 << 17]byte +var z3890 [1 << 17]byte +var z3891 [1 << 17]byte +var z3892 [1 << 17]byte +var z3893 [1 << 17]byte +var z3894 [1 << 17]byte +var z3895 [1 << 17]byte +var z3896 [1 << 17]byte +var z3897 [1 << 17]byte +var z3898 [1 << 17]byte +var z3899 [1 << 17]byte +var z3900 [1 << 17]byte +var z3901 [1 << 17]byte +var z3902 [1 << 17]byte +var z3903 [1 << 17]byte +var z3904 [1 << 17]byte +var z3905 [1 << 17]byte +var z3906 [1 << 17]byte +var z3907 [1 << 17]byte +var z3908 [1 << 17]byte +var z3909 [1 << 17]byte +var z3910 [1 << 17]byte +var z3911 [1 << 17]byte +var z3912 [1 << 17]byte +var z3913 [1 << 17]byte +var z3914 [1 << 17]byte +var z3915 [1 << 17]byte +var z3916 [1 << 17]byte +var z3917 [1 << 17]byte +var z3918 [1 << 17]byte +var z3919 [1 << 17]byte +var z3920 [1 << 17]byte +var z3921 [1 << 17]byte +var z3922 [1 << 17]byte +var z3923 [1 << 17]byte +var z3924 [1 << 17]byte +var z3925 [1 << 17]byte +var z3926 [1 << 17]byte +var z3927 [1 << 17]byte +var z3928 [1 << 17]byte +var z3929 [1 << 17]byte +var z3930 [1 << 17]byte +var z3931 [1 << 17]byte +var z3932 [1 << 17]byte +var z3933 [1 << 17]byte +var z3934 [1 << 17]byte +var z3935 [1 << 17]byte +var z3936 [1 << 17]byte +var z3937 [1 << 17]byte +var z3938 [1 << 17]byte +var z3939 [1 << 17]byte +var z3940 [1 << 17]byte +var z3941 [1 << 17]byte +var z3942 [1 << 17]byte +var z3943 [1 << 17]byte +var z3944 [1 << 17]byte +var z3945 [1 << 17]byte +var z3946 [1 << 17]byte +var z3947 [1 << 17]byte +var z3948 [1 << 17]byte +var z3949 [1 << 17]byte +var z3950 [1 << 17]byte +var z3951 [1 << 17]byte +var z3952 [1 << 17]byte +var z3953 [1 << 17]byte +var z3954 [1 << 17]byte +var z3955 [1 << 17]byte +var z3956 [1 << 17]byte +var z3957 [1 << 17]byte +var z3958 [1 << 17]byte +var z3959 [1 << 17]byte +var z3960 [1 << 17]byte +var z3961 [1 << 17]byte +var z3962 [1 << 17]byte +var z3963 [1 << 17]byte +var z3964 [1 << 17]byte +var z3965 [1 << 17]byte +var z3966 [1 << 17]byte +var z3967 [1 << 17]byte +var z3968 [1 << 17]byte +var z3969 [1 << 17]byte +var z3970 [1 << 17]byte +var z3971 [1 << 17]byte +var z3972 [1 << 17]byte +var z3973 [1 << 17]byte +var z3974 [1 << 17]byte +var z3975 [1 << 17]byte +var z3976 [1 << 17]byte +var z3977 [1 << 17]byte +var z3978 [1 << 17]byte +var z3979 [1 << 17]byte +var z3980 [1 << 17]byte +var z3981 [1 << 17]byte +var z3982 [1 << 17]byte +var z3983 [1 << 17]byte +var z3984 [1 << 17]byte +var z3985 [1 << 17]byte +var z3986 [1 << 17]byte +var z3987 [1 << 17]byte +var z3988 [1 << 17]byte +var z3989 [1 << 17]byte +var z3990 [1 << 17]byte +var z3991 [1 << 17]byte +var z3992 [1 << 17]byte +var z3993 [1 << 17]byte +var z3994 [1 << 17]byte +var z3995 [1 << 17]byte +var z3996 [1 << 17]byte +var z3997 [1 << 17]byte +var z3998 [1 << 17]byte +var z3999 [1 << 17]byte +var z4000 [1 << 17]byte +var z4001 [1 << 17]byte +var z4002 [1 << 17]byte +var z4003 [1 << 17]byte +var z4004 [1 << 17]byte +var z4005 [1 << 17]byte +var z4006 [1 << 17]byte +var z4007 [1 << 17]byte +var z4008 [1 << 17]byte +var z4009 [1 << 17]byte +var z4010 [1 << 17]byte +var z4011 [1 << 17]byte +var z4012 [1 << 17]byte +var z4013 [1 << 17]byte +var z4014 [1 << 17]byte +var z4015 [1 << 17]byte +var z4016 [1 << 17]byte +var z4017 [1 << 17]byte +var z4018 [1 << 17]byte +var z4019 [1 << 17]byte +var z4020 [1 << 17]byte +var z4021 [1 << 17]byte +var z4022 [1 << 17]byte +var z4023 [1 << 17]byte +var z4024 [1 << 17]byte +var z4025 [1 << 17]byte +var z4026 [1 << 17]byte +var z4027 [1 << 17]byte +var z4028 [1 << 17]byte +var z4029 [1 << 17]byte +var z4030 [1 << 17]byte +var z4031 [1 << 17]byte +var z4032 [1 << 17]byte +var z4033 [1 << 17]byte +var z4034 [1 << 17]byte +var z4035 [1 << 17]byte +var z4036 [1 << 17]byte +var z4037 [1 << 17]byte +var z4038 [1 << 17]byte +var z4039 [1 << 17]byte +var z4040 [1 << 17]byte +var z4041 [1 << 17]byte +var z4042 [1 << 17]byte +var z4043 [1 << 17]byte +var z4044 [1 << 17]byte +var z4045 [1 << 17]byte +var z4046 [1 << 17]byte +var z4047 [1 << 17]byte +var z4048 [1 << 17]byte +var z4049 [1 << 17]byte +var z4050 [1 << 17]byte +var z4051 [1 << 17]byte +var z4052 [1 << 17]byte +var z4053 [1 << 17]byte +var z4054 [1 << 17]byte +var z4055 [1 << 17]byte +var z4056 [1 << 17]byte +var z4057 [1 << 17]byte +var z4058 [1 << 17]byte +var z4059 [1 << 17]byte +var z4060 [1 << 17]byte +var z4061 [1 << 17]byte +var z4062 [1 << 17]byte +var z4063 [1 << 17]byte +var z4064 [1 << 17]byte +var z4065 [1 << 17]byte +var z4066 [1 << 17]byte +var z4067 [1 << 17]byte +var z4068 [1 << 17]byte +var z4069 [1 << 17]byte +var z4070 [1 << 17]byte +var z4071 [1 << 17]byte +var z4072 [1 << 17]byte +var z4073 [1 << 17]byte +var z4074 [1 << 17]byte +var z4075 [1 << 17]byte +var z4076 [1 << 17]byte +var z4077 [1 << 17]byte +var z4078 [1 << 17]byte +var z4079 [1 << 17]byte +var z4080 [1 << 17]byte +var z4081 [1 << 17]byte +var z4082 [1 << 17]byte +var z4083 [1 << 17]byte +var z4084 [1 << 17]byte +var z4085 [1 << 17]byte +var z4086 [1 << 17]byte +var z4087 [1 << 17]byte +var z4088 [1 << 17]byte +var z4089 [1 << 17]byte +var z4090 [1 << 17]byte +var z4091 [1 << 17]byte +var z4092 [1 << 17]byte +var z4093 [1 << 17]byte +var z4094 [1 << 17]byte +var z4095 [1 << 17]byte +var z4096 [1 << 17]byte +var z4097 [1 << 17]byte +var z4098 [1 << 17]byte +var z4099 [1 << 17]byte +var z4100 [1 << 17]byte +var z4101 [1 << 17]byte +var z4102 [1 << 17]byte +var z4103 [1 << 17]byte +var z4104 [1 << 17]byte +var z4105 [1 << 17]byte +var z4106 [1 << 17]byte +var z4107 [1 << 17]byte +var z4108 [1 << 17]byte +var z4109 [1 << 17]byte +var z4110 [1 << 17]byte +var z4111 [1 << 17]byte +var z4112 [1 << 17]byte +var z4113 [1 << 17]byte +var z4114 [1 << 17]byte +var z4115 [1 << 17]byte +var z4116 [1 << 17]byte +var z4117 [1 << 17]byte +var z4118 [1 << 17]byte +var z4119 [1 << 17]byte +var z4120 [1 << 17]byte +var z4121 [1 << 17]byte +var z4122 [1 << 17]byte +var z4123 [1 << 17]byte +var z4124 [1 << 17]byte +var z4125 [1 << 17]byte +var z4126 [1 << 17]byte +var z4127 [1 << 17]byte +var z4128 [1 << 17]byte +var z4129 [1 << 17]byte +var z4130 [1 << 17]byte +var z4131 [1 << 17]byte +var z4132 [1 << 17]byte +var z4133 [1 << 17]byte +var z4134 [1 << 17]byte +var z4135 [1 << 17]byte +var z4136 [1 << 17]byte +var z4137 [1 << 17]byte +var z4138 [1 << 17]byte +var z4139 [1 << 17]byte +var z4140 [1 << 17]byte +var z4141 [1 << 17]byte +var z4142 [1 << 17]byte +var z4143 [1 << 17]byte +var z4144 [1 << 17]byte +var z4145 [1 << 17]byte +var z4146 [1 << 17]byte +var z4147 [1 << 17]byte +var z4148 [1 << 17]byte +var z4149 [1 << 17]byte +var z4150 [1 << 17]byte +var z4151 [1 << 17]byte +var z4152 [1 << 17]byte +var z4153 [1 << 17]byte +var z4154 [1 << 17]byte +var z4155 [1 << 17]byte +var z4156 [1 << 17]byte +var z4157 [1 << 17]byte +var z4158 [1 << 17]byte +var z4159 [1 << 17]byte +var z4160 [1 << 17]byte +var z4161 [1 << 17]byte +var z4162 [1 << 17]byte +var z4163 [1 << 17]byte +var z4164 [1 << 17]byte +var z4165 [1 << 17]byte +var z4166 [1 << 17]byte +var z4167 [1 << 17]byte +var z4168 [1 << 17]byte +var z4169 [1 << 17]byte +var z4170 [1 << 17]byte +var z4171 [1 << 17]byte +var z4172 [1 << 17]byte +var z4173 [1 << 17]byte +var z4174 [1 << 17]byte +var z4175 [1 << 17]byte +var z4176 [1 << 17]byte +var z4177 [1 << 17]byte +var z4178 [1 << 17]byte +var z4179 [1 << 17]byte +var z4180 [1 << 17]byte +var z4181 [1 << 17]byte +var z4182 [1 << 17]byte +var z4183 [1 << 17]byte +var z4184 [1 << 17]byte +var z4185 [1 << 17]byte +var z4186 [1 << 17]byte +var z4187 [1 << 17]byte +var z4188 [1 << 17]byte +var z4189 [1 << 17]byte +var z4190 [1 << 17]byte +var z4191 [1 << 17]byte +var z4192 [1 << 17]byte +var z4193 [1 << 17]byte +var z4194 [1 << 17]byte +var z4195 [1 << 17]byte +var z4196 [1 << 17]byte +var z4197 [1 << 17]byte +var z4198 [1 << 17]byte +var z4199 [1 << 17]byte +var z4200 [1 << 17]byte +var z4201 [1 << 17]byte +var z4202 [1 << 17]byte +var z4203 [1 << 17]byte +var z4204 [1 << 17]byte +var z4205 [1 << 17]byte +var z4206 [1 << 17]byte +var z4207 [1 << 17]byte +var z4208 [1 << 17]byte +var z4209 [1 << 17]byte +var z4210 [1 << 17]byte +var z4211 [1 << 17]byte +var z4212 [1 << 17]byte +var z4213 [1 << 17]byte +var z4214 [1 << 17]byte +var z4215 [1 << 17]byte +var z4216 [1 << 17]byte +var z4217 [1 << 17]byte +var z4218 [1 << 17]byte +var z4219 [1 << 17]byte +var z4220 [1 << 17]byte +var z4221 [1 << 17]byte +var z4222 [1 << 17]byte +var z4223 [1 << 17]byte +var z4224 [1 << 17]byte +var z4225 [1 << 17]byte +var z4226 [1 << 17]byte +var z4227 [1 << 17]byte +var z4228 [1 << 17]byte +var z4229 [1 << 17]byte +var z4230 [1 << 17]byte +var z4231 [1 << 17]byte +var z4232 [1 << 17]byte +var z4233 [1 << 17]byte +var z4234 [1 << 17]byte +var z4235 [1 << 17]byte +var z4236 [1 << 17]byte +var z4237 [1 << 17]byte +var z4238 [1 << 17]byte +var z4239 [1 << 17]byte +var z4240 [1 << 17]byte +var z4241 [1 << 17]byte +var z4242 [1 << 17]byte +var z4243 [1 << 17]byte +var z4244 [1 << 17]byte +var z4245 [1 << 17]byte +var z4246 [1 << 17]byte +var z4247 [1 << 17]byte +var z4248 [1 << 17]byte +var z4249 [1 << 17]byte +var z4250 [1 << 17]byte +var z4251 [1 << 17]byte +var z4252 [1 << 17]byte +var z4253 [1 << 17]byte +var z4254 [1 << 17]byte +var z4255 [1 << 17]byte +var z4256 [1 << 17]byte +var z4257 [1 << 17]byte +var z4258 [1 << 17]byte +var z4259 [1 << 17]byte +var z4260 [1 << 17]byte +var z4261 [1 << 17]byte +var z4262 [1 << 17]byte +var z4263 [1 << 17]byte +var z4264 [1 << 17]byte +var z4265 [1 << 17]byte +var z4266 [1 << 17]byte +var z4267 [1 << 17]byte +var z4268 [1 << 17]byte +var z4269 [1 << 17]byte +var z4270 [1 << 17]byte +var z4271 [1 << 17]byte +var z4272 [1 << 17]byte +var z4273 [1 << 17]byte +var z4274 [1 << 17]byte +var z4275 [1 << 17]byte +var z4276 [1 << 17]byte +var z4277 [1 << 17]byte +var z4278 [1 << 17]byte +var z4279 [1 << 17]byte +var z4280 [1 << 17]byte +var z4281 [1 << 17]byte +var z4282 [1 << 17]byte +var z4283 [1 << 17]byte +var z4284 [1 << 17]byte +var z4285 [1 << 17]byte +var z4286 [1 << 17]byte +var z4287 [1 << 17]byte +var z4288 [1 << 17]byte +var z4289 [1 << 17]byte +var z4290 [1 << 17]byte +var z4291 [1 << 17]byte +var z4292 [1 << 17]byte +var z4293 [1 << 17]byte +var z4294 [1 << 17]byte +var z4295 [1 << 17]byte +var z4296 [1 << 17]byte +var z4297 [1 << 17]byte +var z4298 [1 << 17]byte +var z4299 [1 << 17]byte +var z4300 [1 << 17]byte +var z4301 [1 << 17]byte +var z4302 [1 << 17]byte +var z4303 [1 << 17]byte +var z4304 [1 << 17]byte +var z4305 [1 << 17]byte +var z4306 [1 << 17]byte +var z4307 [1 << 17]byte +var z4308 [1 << 17]byte +var z4309 [1 << 17]byte +var z4310 [1 << 17]byte +var z4311 [1 << 17]byte +var z4312 [1 << 17]byte +var z4313 [1 << 17]byte +var z4314 [1 << 17]byte +var z4315 [1 << 17]byte +var z4316 [1 << 17]byte +var z4317 [1 << 17]byte +var z4318 [1 << 17]byte +var z4319 [1 << 17]byte +var z4320 [1 << 17]byte +var z4321 [1 << 17]byte +var z4322 [1 << 17]byte +var z4323 [1 << 17]byte +var z4324 [1 << 17]byte +var z4325 [1 << 17]byte +var z4326 [1 << 17]byte +var z4327 [1 << 17]byte +var z4328 [1 << 17]byte +var z4329 [1 << 17]byte +var z4330 [1 << 17]byte +var z4331 [1 << 17]byte +var z4332 [1 << 17]byte +var z4333 [1 << 17]byte +var z4334 [1 << 17]byte +var z4335 [1 << 17]byte +var z4336 [1 << 17]byte +var z4337 [1 << 17]byte +var z4338 [1 << 17]byte +var z4339 [1 << 17]byte +var z4340 [1 << 17]byte +var z4341 [1 << 17]byte +var z4342 [1 << 17]byte +var z4343 [1 << 17]byte +var z4344 [1 << 17]byte +var z4345 [1 << 17]byte +var z4346 [1 << 17]byte +var z4347 [1 << 17]byte +var z4348 [1 << 17]byte +var z4349 [1 << 17]byte +var z4350 [1 << 17]byte +var z4351 [1 << 17]byte +var z4352 [1 << 17]byte +var z4353 [1 << 17]byte +var z4354 [1 << 17]byte +var z4355 [1 << 17]byte +var z4356 [1 << 17]byte +var z4357 [1 << 17]byte +var z4358 [1 << 17]byte +var z4359 [1 << 17]byte +var z4360 [1 << 17]byte +var z4361 [1 << 17]byte +var z4362 [1 << 17]byte +var z4363 [1 << 17]byte +var z4364 [1 << 17]byte +var z4365 [1 << 17]byte +var z4366 [1 << 17]byte +var z4367 [1 << 17]byte +var z4368 [1 << 17]byte +var z4369 [1 << 17]byte +var z4370 [1 << 17]byte +var z4371 [1 << 17]byte +var z4372 [1 << 17]byte +var z4373 [1 << 17]byte +var z4374 [1 << 17]byte +var z4375 [1 << 17]byte +var z4376 [1 << 17]byte +var z4377 [1 << 17]byte +var z4378 [1 << 17]byte +var z4379 [1 << 17]byte +var z4380 [1 << 17]byte +var z4381 [1 << 17]byte +var z4382 [1 << 17]byte +var z4383 [1 << 17]byte +var z4384 [1 << 17]byte +var z4385 [1 << 17]byte +var z4386 [1 << 17]byte +var z4387 [1 << 17]byte +var z4388 [1 << 17]byte +var z4389 [1 << 17]byte +var z4390 [1 << 17]byte +var z4391 [1 << 17]byte +var z4392 [1 << 17]byte +var z4393 [1 << 17]byte +var z4394 [1 << 17]byte +var z4395 [1 << 17]byte +var z4396 [1 << 17]byte +var z4397 [1 << 17]byte +var z4398 [1 << 17]byte +var z4399 [1 << 17]byte +var z4400 [1 << 17]byte +var z4401 [1 << 17]byte +var z4402 [1 << 17]byte +var z4403 [1 << 17]byte +var z4404 [1 << 17]byte +var z4405 [1 << 17]byte +var z4406 [1 << 17]byte +var z4407 [1 << 17]byte +var z4408 [1 << 17]byte +var z4409 [1 << 17]byte +var z4410 [1 << 17]byte +var z4411 [1 << 17]byte +var z4412 [1 << 17]byte +var z4413 [1 << 17]byte +var z4414 [1 << 17]byte +var z4415 [1 << 17]byte +var z4416 [1 << 17]byte +var z4417 [1 << 17]byte +var z4418 [1 << 17]byte +var z4419 [1 << 17]byte +var z4420 [1 << 17]byte +var z4421 [1 << 17]byte +var z4422 [1 << 17]byte +var z4423 [1 << 17]byte +var z4424 [1 << 17]byte +var z4425 [1 << 17]byte +var z4426 [1 << 17]byte +var z4427 [1 << 17]byte +var z4428 [1 << 17]byte +var z4429 [1 << 17]byte +var z4430 [1 << 17]byte +var z4431 [1 << 17]byte +var z4432 [1 << 17]byte +var z4433 [1 << 17]byte +var z4434 [1 << 17]byte +var z4435 [1 << 17]byte +var z4436 [1 << 17]byte +var z4437 [1 << 17]byte +var z4438 [1 << 17]byte +var z4439 [1 << 17]byte +var z4440 [1 << 17]byte +var z4441 [1 << 17]byte +var z4442 [1 << 17]byte +var z4443 [1 << 17]byte +var z4444 [1 << 17]byte +var z4445 [1 << 17]byte +var z4446 [1 << 17]byte +var z4447 [1 << 17]byte +var z4448 [1 << 17]byte +var z4449 [1 << 17]byte +var z4450 [1 << 17]byte +var z4451 [1 << 17]byte +var z4452 [1 << 17]byte +var z4453 [1 << 17]byte +var z4454 [1 << 17]byte +var z4455 [1 << 17]byte +var z4456 [1 << 17]byte +var z4457 [1 << 17]byte +var z4458 [1 << 17]byte +var z4459 [1 << 17]byte +var z4460 [1 << 17]byte +var z4461 [1 << 17]byte +var z4462 [1 << 17]byte +var z4463 [1 << 17]byte +var z4464 [1 << 17]byte +var z4465 [1 << 17]byte +var z4466 [1 << 17]byte +var z4467 [1 << 17]byte +var z4468 [1 << 17]byte +var z4469 [1 << 17]byte +var z4470 [1 << 17]byte +var z4471 [1 << 17]byte +var z4472 [1 << 17]byte +var z4473 [1 << 17]byte +var z4474 [1 << 17]byte +var z4475 [1 << 17]byte +var z4476 [1 << 17]byte +var z4477 [1 << 17]byte +var z4478 [1 << 17]byte +var z4479 [1 << 17]byte +var z4480 [1 << 17]byte +var z4481 [1 << 17]byte +var z4482 [1 << 17]byte +var z4483 [1 << 17]byte +var z4484 [1 << 17]byte +var z4485 [1 << 17]byte +var z4486 [1 << 17]byte +var z4487 [1 << 17]byte +var z4488 [1 << 17]byte +var z4489 [1 << 17]byte +var z4490 [1 << 17]byte +var z4491 [1 << 17]byte +var z4492 [1 << 17]byte +var z4493 [1 << 17]byte +var z4494 [1 << 17]byte +var z4495 [1 << 17]byte +var z4496 [1 << 17]byte +var z4497 [1 << 17]byte +var z4498 [1 << 17]byte +var z4499 [1 << 17]byte +var z4500 [1 << 17]byte +var z4501 [1 << 17]byte +var z4502 [1 << 17]byte +var z4503 [1 << 17]byte +var z4504 [1 << 17]byte +var z4505 [1 << 17]byte +var z4506 [1 << 17]byte +var z4507 [1 << 17]byte +var z4508 [1 << 17]byte +var z4509 [1 << 17]byte +var z4510 [1 << 17]byte +var z4511 [1 << 17]byte +var z4512 [1 << 17]byte +var z4513 [1 << 17]byte +var z4514 [1 << 17]byte +var z4515 [1 << 17]byte +var z4516 [1 << 17]byte +var z4517 [1 << 17]byte +var z4518 [1 << 17]byte +var z4519 [1 << 17]byte +var z4520 [1 << 17]byte +var z4521 [1 << 17]byte +var z4522 [1 << 17]byte +var z4523 [1 << 17]byte +var z4524 [1 << 17]byte +var z4525 [1 << 17]byte +var z4526 [1 << 17]byte +var z4527 [1 << 17]byte +var z4528 [1 << 17]byte +var z4529 [1 << 17]byte +var z4530 [1 << 17]byte +var z4531 [1 << 17]byte +var z4532 [1 << 17]byte +var z4533 [1 << 17]byte +var z4534 [1 << 17]byte +var z4535 [1 << 17]byte +var z4536 [1 << 17]byte +var z4537 [1 << 17]byte +var z4538 [1 << 17]byte +var z4539 [1 << 17]byte +var z4540 [1 << 17]byte +var z4541 [1 << 17]byte +var z4542 [1 << 17]byte +var z4543 [1 << 17]byte +var z4544 [1 << 17]byte +var z4545 [1 << 17]byte +var z4546 [1 << 17]byte +var z4547 [1 << 17]byte +var z4548 [1 << 17]byte +var z4549 [1 << 17]byte +var z4550 [1 << 17]byte +var z4551 [1 << 17]byte +var z4552 [1 << 17]byte +var z4553 [1 << 17]byte +var z4554 [1 << 17]byte +var z4555 [1 << 17]byte +var z4556 [1 << 17]byte +var z4557 [1 << 17]byte +var z4558 [1 << 17]byte +var z4559 [1 << 17]byte +var z4560 [1 << 17]byte +var z4561 [1 << 17]byte +var z4562 [1 << 17]byte +var z4563 [1 << 17]byte +var z4564 [1 << 17]byte +var z4565 [1 << 17]byte +var z4566 [1 << 17]byte +var z4567 [1 << 17]byte +var z4568 [1 << 17]byte +var z4569 [1 << 17]byte +var z4570 [1 << 17]byte +var z4571 [1 << 17]byte +var z4572 [1 << 17]byte +var z4573 [1 << 17]byte +var z4574 [1 << 17]byte +var z4575 [1 << 17]byte +var z4576 [1 << 17]byte +var z4577 [1 << 17]byte +var z4578 [1 << 17]byte +var z4579 [1 << 17]byte +var z4580 [1 << 17]byte +var z4581 [1 << 17]byte +var z4582 [1 << 17]byte +var z4583 [1 << 17]byte +var z4584 [1 << 17]byte +var z4585 [1 << 17]byte +var z4586 [1 << 17]byte +var z4587 [1 << 17]byte +var z4588 [1 << 17]byte +var z4589 [1 << 17]byte +var z4590 [1 << 17]byte +var z4591 [1 << 17]byte +var z4592 [1 << 17]byte +var z4593 [1 << 17]byte +var z4594 [1 << 17]byte +var z4595 [1 << 17]byte +var z4596 [1 << 17]byte +var z4597 [1 << 17]byte +var z4598 [1 << 17]byte +var z4599 [1 << 17]byte +var z4600 [1 << 17]byte +var z4601 [1 << 17]byte +var z4602 [1 << 17]byte +var z4603 [1 << 17]byte +var z4604 [1 << 17]byte +var z4605 [1 << 17]byte +var z4606 [1 << 17]byte +var z4607 [1 << 17]byte +var z4608 [1 << 17]byte +var z4609 [1 << 17]byte +var z4610 [1 << 17]byte +var z4611 [1 << 17]byte +var z4612 [1 << 17]byte +var z4613 [1 << 17]byte +var z4614 [1 << 17]byte +var z4615 [1 << 17]byte +var z4616 [1 << 17]byte +var z4617 [1 << 17]byte +var z4618 [1 << 17]byte +var z4619 [1 << 17]byte +var z4620 [1 << 17]byte +var z4621 [1 << 17]byte +var z4622 [1 << 17]byte +var z4623 [1 << 17]byte +var z4624 [1 << 17]byte +var z4625 [1 << 17]byte +var z4626 [1 << 17]byte +var z4627 [1 << 17]byte +var z4628 [1 << 17]byte +var z4629 [1 << 17]byte +var z4630 [1 << 17]byte +var z4631 [1 << 17]byte +var z4632 [1 << 17]byte +var z4633 [1 << 17]byte +var z4634 [1 << 17]byte +var z4635 [1 << 17]byte +var z4636 [1 << 17]byte +var z4637 [1 << 17]byte +var z4638 [1 << 17]byte +var z4639 [1 << 17]byte +var z4640 [1 << 17]byte +var z4641 [1 << 17]byte +var z4642 [1 << 17]byte +var z4643 [1 << 17]byte +var z4644 [1 << 17]byte +var z4645 [1 << 17]byte +var z4646 [1 << 17]byte +var z4647 [1 << 17]byte +var z4648 [1 << 17]byte +var z4649 [1 << 17]byte +var z4650 [1 << 17]byte +var z4651 [1 << 17]byte +var z4652 [1 << 17]byte +var z4653 [1 << 17]byte +var z4654 [1 << 17]byte +var z4655 [1 << 17]byte +var z4656 [1 << 17]byte +var z4657 [1 << 17]byte +var z4658 [1 << 17]byte +var z4659 [1 << 17]byte +var z4660 [1 << 17]byte +var z4661 [1 << 17]byte +var z4662 [1 << 17]byte +var z4663 [1 << 17]byte +var z4664 [1 << 17]byte +var z4665 [1 << 17]byte +var z4666 [1 << 17]byte +var z4667 [1 << 17]byte +var z4668 [1 << 17]byte +var z4669 [1 << 17]byte +var z4670 [1 << 17]byte +var z4671 [1 << 17]byte +var z4672 [1 << 17]byte +var z4673 [1 << 17]byte +var z4674 [1 << 17]byte +var z4675 [1 << 17]byte +var z4676 [1 << 17]byte +var z4677 [1 << 17]byte +var z4678 [1 << 17]byte +var z4679 [1 << 17]byte +var z4680 [1 << 17]byte +var z4681 [1 << 17]byte +var z4682 [1 << 17]byte +var z4683 [1 << 17]byte +var z4684 [1 << 17]byte +var z4685 [1 << 17]byte +var z4686 [1 << 17]byte +var z4687 [1 << 17]byte +var z4688 [1 << 17]byte +var z4689 [1 << 17]byte +var z4690 [1 << 17]byte +var z4691 [1 << 17]byte +var z4692 [1 << 17]byte +var z4693 [1 << 17]byte +var z4694 [1 << 17]byte +var z4695 [1 << 17]byte +var z4696 [1 << 17]byte +var z4697 [1 << 17]byte +var z4698 [1 << 17]byte +var z4699 [1 << 17]byte +var z4700 [1 << 17]byte +var z4701 [1 << 17]byte +var z4702 [1 << 17]byte +var z4703 [1 << 17]byte +var z4704 [1 << 17]byte +var z4705 [1 << 17]byte +var z4706 [1 << 17]byte +var z4707 [1 << 17]byte +var z4708 [1 << 17]byte +var z4709 [1 << 17]byte +var z4710 [1 << 17]byte +var z4711 [1 << 17]byte +var z4712 [1 << 17]byte +var z4713 [1 << 17]byte +var z4714 [1 << 17]byte +var z4715 [1 << 17]byte +var z4716 [1 << 17]byte +var z4717 [1 << 17]byte +var z4718 [1 << 17]byte +var z4719 [1 << 17]byte +var z4720 [1 << 17]byte +var z4721 [1 << 17]byte +var z4722 [1 << 17]byte +var z4723 [1 << 17]byte +var z4724 [1 << 17]byte +var z4725 [1 << 17]byte +var z4726 [1 << 17]byte +var z4727 [1 << 17]byte +var z4728 [1 << 17]byte +var z4729 [1 << 17]byte +var z4730 [1 << 17]byte +var z4731 [1 << 17]byte +var z4732 [1 << 17]byte +var z4733 [1 << 17]byte +var z4734 [1 << 17]byte +var z4735 [1 << 17]byte +var z4736 [1 << 17]byte +var z4737 [1 << 17]byte +var z4738 [1 << 17]byte +var z4739 [1 << 17]byte +var z4740 [1 << 17]byte +var z4741 [1 << 17]byte +var z4742 [1 << 17]byte +var z4743 [1 << 17]byte +var z4744 [1 << 17]byte +var z4745 [1 << 17]byte +var z4746 [1 << 17]byte +var z4747 [1 << 17]byte +var z4748 [1 << 17]byte +var z4749 [1 << 17]byte +var z4750 [1 << 17]byte +var z4751 [1 << 17]byte +var z4752 [1 << 17]byte +var z4753 [1 << 17]byte +var z4754 [1 << 17]byte +var z4755 [1 << 17]byte +var z4756 [1 << 17]byte +var z4757 [1 << 17]byte +var z4758 [1 << 17]byte +var z4759 [1 << 17]byte +var z4760 [1 << 17]byte +var z4761 [1 << 17]byte +var z4762 [1 << 17]byte +var z4763 [1 << 17]byte +var z4764 [1 << 17]byte +var z4765 [1 << 17]byte +var z4766 [1 << 17]byte +var z4767 [1 << 17]byte +var z4768 [1 << 17]byte +var z4769 [1 << 17]byte +var z4770 [1 << 17]byte +var z4771 [1 << 17]byte +var z4772 [1 << 17]byte +var z4773 [1 << 17]byte +var z4774 [1 << 17]byte +var z4775 [1 << 17]byte +var z4776 [1 << 17]byte +var z4777 [1 << 17]byte +var z4778 [1 << 17]byte +var z4779 [1 << 17]byte +var z4780 [1 << 17]byte +var z4781 [1 << 17]byte +var z4782 [1 << 17]byte +var z4783 [1 << 17]byte +var z4784 [1 << 17]byte +var z4785 [1 << 17]byte +var z4786 [1 << 17]byte +var z4787 [1 << 17]byte +var z4788 [1 << 17]byte +var z4789 [1 << 17]byte +var z4790 [1 << 17]byte +var z4791 [1 << 17]byte +var z4792 [1 << 17]byte +var z4793 [1 << 17]byte +var z4794 [1 << 17]byte +var z4795 [1 << 17]byte +var z4796 [1 << 17]byte +var z4797 [1 << 17]byte +var z4798 [1 << 17]byte +var z4799 [1 << 17]byte +var z4800 [1 << 17]byte +var z4801 [1 << 17]byte +var z4802 [1 << 17]byte +var z4803 [1 << 17]byte +var z4804 [1 << 17]byte +var z4805 [1 << 17]byte +var z4806 [1 << 17]byte +var z4807 [1 << 17]byte +var z4808 [1 << 17]byte +var z4809 [1 << 17]byte +var z4810 [1 << 17]byte +var z4811 [1 << 17]byte +var z4812 [1 << 17]byte +var z4813 [1 << 17]byte +var z4814 [1 << 17]byte +var z4815 [1 << 17]byte +var z4816 [1 << 17]byte +var z4817 [1 << 17]byte +var z4818 [1 << 17]byte +var z4819 [1 << 17]byte +var z4820 [1 << 17]byte +var z4821 [1 << 17]byte +var z4822 [1 << 17]byte +var z4823 [1 << 17]byte +var z4824 [1 << 17]byte +var z4825 [1 << 17]byte +var z4826 [1 << 17]byte +var z4827 [1 << 17]byte +var z4828 [1 << 17]byte +var z4829 [1 << 17]byte +var z4830 [1 << 17]byte +var z4831 [1 << 17]byte +var z4832 [1 << 17]byte +var z4833 [1 << 17]byte +var z4834 [1 << 17]byte +var z4835 [1 << 17]byte +var z4836 [1 << 17]byte +var z4837 [1 << 17]byte +var z4838 [1 << 17]byte +var z4839 [1 << 17]byte +var z4840 [1 << 17]byte +var z4841 [1 << 17]byte +var z4842 [1 << 17]byte +var z4843 [1 << 17]byte +var z4844 [1 << 17]byte +var z4845 [1 << 17]byte +var z4846 [1 << 17]byte +var z4847 [1 << 17]byte +var z4848 [1 << 17]byte +var z4849 [1 << 17]byte +var z4850 [1 << 17]byte +var z4851 [1 << 17]byte +var z4852 [1 << 17]byte +var z4853 [1 << 17]byte +var z4854 [1 << 17]byte +var z4855 [1 << 17]byte +var z4856 [1 << 17]byte +var z4857 [1 << 17]byte +var z4858 [1 << 17]byte +var z4859 [1 << 17]byte +var z4860 [1 << 17]byte +var z4861 [1 << 17]byte +var z4862 [1 << 17]byte +var z4863 [1 << 17]byte +var z4864 [1 << 17]byte +var z4865 [1 << 17]byte +var z4866 [1 << 17]byte +var z4867 [1 << 17]byte +var z4868 [1 << 17]byte +var z4869 [1 << 17]byte +var z4870 [1 << 17]byte +var z4871 [1 << 17]byte +var z4872 [1 << 17]byte +var z4873 [1 << 17]byte +var z4874 [1 << 17]byte +var z4875 [1 << 17]byte +var z4876 [1 << 17]byte +var z4877 [1 << 17]byte +var z4878 [1 << 17]byte +var z4879 [1 << 17]byte +var z4880 [1 << 17]byte +var z4881 [1 << 17]byte +var z4882 [1 << 17]byte +var z4883 [1 << 17]byte +var z4884 [1 << 17]byte +var z4885 [1 << 17]byte +var z4886 [1 << 17]byte +var z4887 [1 << 17]byte +var z4888 [1 << 17]byte +var z4889 [1 << 17]byte +var z4890 [1 << 17]byte +var z4891 [1 << 17]byte +var z4892 [1 << 17]byte +var z4893 [1 << 17]byte +var z4894 [1 << 17]byte +var z4895 [1 << 17]byte +var z4896 [1 << 17]byte +var z4897 [1 << 17]byte +var z4898 [1 << 17]byte +var z4899 [1 << 17]byte +var z4900 [1 << 17]byte +var z4901 [1 << 17]byte +var z4902 [1 << 17]byte +var z4903 [1 << 17]byte +var z4904 [1 << 17]byte +var z4905 [1 << 17]byte +var z4906 [1 << 17]byte +var z4907 [1 << 17]byte +var z4908 [1 << 17]byte +var z4909 [1 << 17]byte +var z4910 [1 << 17]byte +var z4911 [1 << 17]byte +var z4912 [1 << 17]byte +var z4913 [1 << 17]byte +var z4914 [1 << 17]byte +var z4915 [1 << 17]byte +var z4916 [1 << 17]byte +var z4917 [1 << 17]byte +var z4918 [1 << 17]byte +var z4919 [1 << 17]byte +var z4920 [1 << 17]byte +var z4921 [1 << 17]byte +var z4922 [1 << 17]byte +var z4923 [1 << 17]byte +var z4924 [1 << 17]byte +var z4925 [1 << 17]byte +var z4926 [1 << 17]byte +var z4927 [1 << 17]byte +var z4928 [1 << 17]byte +var z4929 [1 << 17]byte +var z4930 [1 << 17]byte +var z4931 [1 << 17]byte +var z4932 [1 << 17]byte +var z4933 [1 << 17]byte +var z4934 [1 << 17]byte +var z4935 [1 << 17]byte +var z4936 [1 << 17]byte +var z4937 [1 << 17]byte +var z4938 [1 << 17]byte +var z4939 [1 << 17]byte +var z4940 [1 << 17]byte +var z4941 [1 << 17]byte +var z4942 [1 << 17]byte +var z4943 [1 << 17]byte +var z4944 [1 << 17]byte +var z4945 [1 << 17]byte +var z4946 [1 << 17]byte +var z4947 [1 << 17]byte +var z4948 [1 << 17]byte +var z4949 [1 << 17]byte +var z4950 [1 << 17]byte +var z4951 [1 << 17]byte +var z4952 [1 << 17]byte +var z4953 [1 << 17]byte +var z4954 [1 << 17]byte +var z4955 [1 << 17]byte +var z4956 [1 << 17]byte +var z4957 [1 << 17]byte +var z4958 [1 << 17]byte +var z4959 [1 << 17]byte +var z4960 [1 << 17]byte +var z4961 [1 << 17]byte +var z4962 [1 << 17]byte +var z4963 [1 << 17]byte +var z4964 [1 << 17]byte +var z4965 [1 << 17]byte +var z4966 [1 << 17]byte +var z4967 [1 << 17]byte +var z4968 [1 << 17]byte +var z4969 [1 << 17]byte +var z4970 [1 << 17]byte +var z4971 [1 << 17]byte +var z4972 [1 << 17]byte +var z4973 [1 << 17]byte +var z4974 [1 << 17]byte +var z4975 [1 << 17]byte +var z4976 [1 << 17]byte +var z4977 [1 << 17]byte +var z4978 [1 << 17]byte +var z4979 [1 << 17]byte +var z4980 [1 << 17]byte +var z4981 [1 << 17]byte +var z4982 [1 << 17]byte +var z4983 [1 << 17]byte +var z4984 [1 << 17]byte +var z4985 [1 << 17]byte +var z4986 [1 << 17]byte +var z4987 [1 << 17]byte +var z4988 [1 << 17]byte +var z4989 [1 << 17]byte +var z4990 [1 << 17]byte +var z4991 [1 << 17]byte +var z4992 [1 << 17]byte +var z4993 [1 << 17]byte +var z4994 [1 << 17]byte +var z4995 [1 << 17]byte +var z4996 [1 << 17]byte +var z4997 [1 << 17]byte +var z4998 [1 << 17]byte +var z4999 [1 << 17]byte +var z5000 [1 << 17]byte +var z5001 [1 << 17]byte +var z5002 [1 << 17]byte +var z5003 [1 << 17]byte +var z5004 [1 << 17]byte +var z5005 [1 << 17]byte +var z5006 [1 << 17]byte +var z5007 [1 << 17]byte +var z5008 [1 << 17]byte +var z5009 [1 << 17]byte +var z5010 [1 << 17]byte +var z5011 [1 << 17]byte +var z5012 [1 << 17]byte +var z5013 [1 << 17]byte +var z5014 [1 << 17]byte +var z5015 [1 << 17]byte +var z5016 [1 << 17]byte +var z5017 [1 << 17]byte +var z5018 [1 << 17]byte +var z5019 [1 << 17]byte +var z5020 [1 << 17]byte +var z5021 [1 << 17]byte +var z5022 [1 << 17]byte +var z5023 [1 << 17]byte +var z5024 [1 << 17]byte +var z5025 [1 << 17]byte +var z5026 [1 << 17]byte +var z5027 [1 << 17]byte +var z5028 [1 << 17]byte +var z5029 [1 << 17]byte +var z5030 [1 << 17]byte +var z5031 [1 << 17]byte +var z5032 [1 << 17]byte +var z5033 [1 << 17]byte +var z5034 [1 << 17]byte +var z5035 [1 << 17]byte +var z5036 [1 << 17]byte +var z5037 [1 << 17]byte +var z5038 [1 << 17]byte +var z5039 [1 << 17]byte +var z5040 [1 << 17]byte +var z5041 [1 << 17]byte +var z5042 [1 << 17]byte +var z5043 [1 << 17]byte +var z5044 [1 << 17]byte +var z5045 [1 << 17]byte +var z5046 [1 << 17]byte +var z5047 [1 << 17]byte +var z5048 [1 << 17]byte +var z5049 [1 << 17]byte +var z5050 [1 << 17]byte +var z5051 [1 << 17]byte +var z5052 [1 << 17]byte +var z5053 [1 << 17]byte +var z5054 [1 << 17]byte +var z5055 [1 << 17]byte +var z5056 [1 << 17]byte +var z5057 [1 << 17]byte +var z5058 [1 << 17]byte +var z5059 [1 << 17]byte +var z5060 [1 << 17]byte +var z5061 [1 << 17]byte +var z5062 [1 << 17]byte +var z5063 [1 << 17]byte +var z5064 [1 << 17]byte +var z5065 [1 << 17]byte +var z5066 [1 << 17]byte +var z5067 [1 << 17]byte +var z5068 [1 << 17]byte +var z5069 [1 << 17]byte +var z5070 [1 << 17]byte +var z5071 [1 << 17]byte +var z5072 [1 << 17]byte +var z5073 [1 << 17]byte +var z5074 [1 << 17]byte +var z5075 [1 << 17]byte +var z5076 [1 << 17]byte +var z5077 [1 << 17]byte +var z5078 [1 << 17]byte +var z5079 [1 << 17]byte +var z5080 [1 << 17]byte +var z5081 [1 << 17]byte +var z5082 [1 << 17]byte +var z5083 [1 << 17]byte +var z5084 [1 << 17]byte +var z5085 [1 << 17]byte +var z5086 [1 << 17]byte +var z5087 [1 << 17]byte +var z5088 [1 << 17]byte +var z5089 [1 << 17]byte +var z5090 [1 << 17]byte +var z5091 [1 << 17]byte +var z5092 [1 << 17]byte +var z5093 [1 << 17]byte +var z5094 [1 << 17]byte +var z5095 [1 << 17]byte +var z5096 [1 << 17]byte +var z5097 [1 << 17]byte +var z5098 [1 << 17]byte +var z5099 [1 << 17]byte +var z5100 [1 << 17]byte +var z5101 [1 << 17]byte +var z5102 [1 << 17]byte +var z5103 [1 << 17]byte +var z5104 [1 << 17]byte +var z5105 [1 << 17]byte +var z5106 [1 << 17]byte +var z5107 [1 << 17]byte +var z5108 [1 << 17]byte +var z5109 [1 << 17]byte +var z5110 [1 << 17]byte +var z5111 [1 << 17]byte +var z5112 [1 << 17]byte +var z5113 [1 << 17]byte +var z5114 [1 << 17]byte +var z5115 [1 << 17]byte +var z5116 [1 << 17]byte +var z5117 [1 << 17]byte +var z5118 [1 << 17]byte +var z5119 [1 << 17]byte +var z5120 [1 << 17]byte +var z5121 [1 << 17]byte +var z5122 [1 << 17]byte +var z5123 [1 << 17]byte +var z5124 [1 << 17]byte +var z5125 [1 << 17]byte +var z5126 [1 << 17]byte +var z5127 [1 << 17]byte +var z5128 [1 << 17]byte +var z5129 [1 << 17]byte +var z5130 [1 << 17]byte +var z5131 [1 << 17]byte +var z5132 [1 << 17]byte +var z5133 [1 << 17]byte +var z5134 [1 << 17]byte +var z5135 [1 << 17]byte +var z5136 [1 << 17]byte +var z5137 [1 << 17]byte +var z5138 [1 << 17]byte +var z5139 [1 << 17]byte +var z5140 [1 << 17]byte +var z5141 [1 << 17]byte +var z5142 [1 << 17]byte +var z5143 [1 << 17]byte +var z5144 [1 << 17]byte +var z5145 [1 << 17]byte +var z5146 [1 << 17]byte +var z5147 [1 << 17]byte +var z5148 [1 << 17]byte +var z5149 [1 << 17]byte +var z5150 [1 << 17]byte +var z5151 [1 << 17]byte +var z5152 [1 << 17]byte +var z5153 [1 << 17]byte +var z5154 [1 << 17]byte +var z5155 [1 << 17]byte +var z5156 [1 << 17]byte +var z5157 [1 << 17]byte +var z5158 [1 << 17]byte +var z5159 [1 << 17]byte +var z5160 [1 << 17]byte +var z5161 [1 << 17]byte +var z5162 [1 << 17]byte +var z5163 [1 << 17]byte +var z5164 [1 << 17]byte +var z5165 [1 << 17]byte +var z5166 [1 << 17]byte +var z5167 [1 << 17]byte +var z5168 [1 << 17]byte +var z5169 [1 << 17]byte +var z5170 [1 << 17]byte +var z5171 [1 << 17]byte +var z5172 [1 << 17]byte +var z5173 [1 << 17]byte +var z5174 [1 << 17]byte +var z5175 [1 << 17]byte +var z5176 [1 << 17]byte +var z5177 [1 << 17]byte +var z5178 [1 << 17]byte +var z5179 [1 << 17]byte +var z5180 [1 << 17]byte +var z5181 [1 << 17]byte +var z5182 [1 << 17]byte +var z5183 [1 << 17]byte +var z5184 [1 << 17]byte +var z5185 [1 << 17]byte +var z5186 [1 << 17]byte +var z5187 [1 << 17]byte +var z5188 [1 << 17]byte +var z5189 [1 << 17]byte +var z5190 [1 << 17]byte +var z5191 [1 << 17]byte +var z5192 [1 << 17]byte +var z5193 [1 << 17]byte +var z5194 [1 << 17]byte +var z5195 [1 << 17]byte +var z5196 [1 << 17]byte +var z5197 [1 << 17]byte +var z5198 [1 << 17]byte +var z5199 [1 << 17]byte +var z5200 [1 << 17]byte +var z5201 [1 << 17]byte +var z5202 [1 << 17]byte +var z5203 [1 << 17]byte +var z5204 [1 << 17]byte +var z5205 [1 << 17]byte +var z5206 [1 << 17]byte +var z5207 [1 << 17]byte +var z5208 [1 << 17]byte +var z5209 [1 << 17]byte +var z5210 [1 << 17]byte +var z5211 [1 << 17]byte +var z5212 [1 << 17]byte +var z5213 [1 << 17]byte +var z5214 [1 << 17]byte +var z5215 [1 << 17]byte +var z5216 [1 << 17]byte +var z5217 [1 << 17]byte +var z5218 [1 << 17]byte +var z5219 [1 << 17]byte +var z5220 [1 << 17]byte +var z5221 [1 << 17]byte +var z5222 [1 << 17]byte +var z5223 [1 << 17]byte +var z5224 [1 << 17]byte +var z5225 [1 << 17]byte +var z5226 [1 << 17]byte +var z5227 [1 << 17]byte +var z5228 [1 << 17]byte +var z5229 [1 << 17]byte +var z5230 [1 << 17]byte +var z5231 [1 << 17]byte +var z5232 [1 << 17]byte +var z5233 [1 << 17]byte +var z5234 [1 << 17]byte +var z5235 [1 << 17]byte +var z5236 [1 << 17]byte +var z5237 [1 << 17]byte +var z5238 [1 << 17]byte +var z5239 [1 << 17]byte +var z5240 [1 << 17]byte +var z5241 [1 << 17]byte +var z5242 [1 << 17]byte +var z5243 [1 << 17]byte +var z5244 [1 << 17]byte +var z5245 [1 << 17]byte +var z5246 [1 << 17]byte +var z5247 [1 << 17]byte +var z5248 [1 << 17]byte +var z5249 [1 << 17]byte +var z5250 [1 << 17]byte +var z5251 [1 << 17]byte +var z5252 [1 << 17]byte +var z5253 [1 << 17]byte +var z5254 [1 << 17]byte +var z5255 [1 << 17]byte +var z5256 [1 << 17]byte +var z5257 [1 << 17]byte +var z5258 [1 << 17]byte +var z5259 [1 << 17]byte +var z5260 [1 << 17]byte +var z5261 [1 << 17]byte +var z5262 [1 << 17]byte +var z5263 [1 << 17]byte +var z5264 [1 << 17]byte +var z5265 [1 << 17]byte +var z5266 [1 << 17]byte +var z5267 [1 << 17]byte +var z5268 [1 << 17]byte +var z5269 [1 << 17]byte +var z5270 [1 << 17]byte +var z5271 [1 << 17]byte +var z5272 [1 << 17]byte +var z5273 [1 << 17]byte +var z5274 [1 << 17]byte +var z5275 [1 << 17]byte +var z5276 [1 << 17]byte +var z5277 [1 << 17]byte +var z5278 [1 << 17]byte +var z5279 [1 << 17]byte +var z5280 [1 << 17]byte +var z5281 [1 << 17]byte +var z5282 [1 << 17]byte +var z5283 [1 << 17]byte +var z5284 [1 << 17]byte +var z5285 [1 << 17]byte +var z5286 [1 << 17]byte +var z5287 [1 << 17]byte +var z5288 [1 << 17]byte +var z5289 [1 << 17]byte +var z5290 [1 << 17]byte +var z5291 [1 << 17]byte +var z5292 [1 << 17]byte +var z5293 [1 << 17]byte +var z5294 [1 << 17]byte +var z5295 [1 << 17]byte +var z5296 [1 << 17]byte +var z5297 [1 << 17]byte +var z5298 [1 << 17]byte +var z5299 [1 << 17]byte +var z5300 [1 << 17]byte +var z5301 [1 << 17]byte +var z5302 [1 << 17]byte +var z5303 [1 << 17]byte +var z5304 [1 << 17]byte +var z5305 [1 << 17]byte +var z5306 [1 << 17]byte +var z5307 [1 << 17]byte +var z5308 [1 << 17]byte +var z5309 [1 << 17]byte +var z5310 [1 << 17]byte +var z5311 [1 << 17]byte +var z5312 [1 << 17]byte +var z5313 [1 << 17]byte +var z5314 [1 << 17]byte +var z5315 [1 << 17]byte +var z5316 [1 << 17]byte +var z5317 [1 << 17]byte +var z5318 [1 << 17]byte +var z5319 [1 << 17]byte +var z5320 [1 << 17]byte +var z5321 [1 << 17]byte +var z5322 [1 << 17]byte +var z5323 [1 << 17]byte +var z5324 [1 << 17]byte +var z5325 [1 << 17]byte +var z5326 [1 << 17]byte +var z5327 [1 << 17]byte +var z5328 [1 << 17]byte +var z5329 [1 << 17]byte +var z5330 [1 << 17]byte +var z5331 [1 << 17]byte +var z5332 [1 << 17]byte +var z5333 [1 << 17]byte +var z5334 [1 << 17]byte +var z5335 [1 << 17]byte +var z5336 [1 << 17]byte +var z5337 [1 << 17]byte +var z5338 [1 << 17]byte +var z5339 [1 << 17]byte +var z5340 [1 << 17]byte +var z5341 [1 << 17]byte +var z5342 [1 << 17]byte +var z5343 [1 << 17]byte +var z5344 [1 << 17]byte +var z5345 [1 << 17]byte +var z5346 [1 << 17]byte +var z5347 [1 << 17]byte +var z5348 [1 << 17]byte +var z5349 [1 << 17]byte +var z5350 [1 << 17]byte +var z5351 [1 << 17]byte +var z5352 [1 << 17]byte +var z5353 [1 << 17]byte +var z5354 [1 << 17]byte +var z5355 [1 << 17]byte +var z5356 [1 << 17]byte +var z5357 [1 << 17]byte +var z5358 [1 << 17]byte +var z5359 [1 << 17]byte +var z5360 [1 << 17]byte +var z5361 [1 << 17]byte +var z5362 [1 << 17]byte +var z5363 [1 << 17]byte +var z5364 [1 << 17]byte +var z5365 [1 << 17]byte +var z5366 [1 << 17]byte +var z5367 [1 << 17]byte +var z5368 [1 << 17]byte +var z5369 [1 << 17]byte +var z5370 [1 << 17]byte +var z5371 [1 << 17]byte +var z5372 [1 << 17]byte +var z5373 [1 << 17]byte +var z5374 [1 << 17]byte +var z5375 [1 << 17]byte +var z5376 [1 << 17]byte +var z5377 [1 << 17]byte +var z5378 [1 << 17]byte +var z5379 [1 << 17]byte +var z5380 [1 << 17]byte +var z5381 [1 << 17]byte +var z5382 [1 << 17]byte +var z5383 [1 << 17]byte +var z5384 [1 << 17]byte +var z5385 [1 << 17]byte +var z5386 [1 << 17]byte +var z5387 [1 << 17]byte +var z5388 [1 << 17]byte +var z5389 [1 << 17]byte +var z5390 [1 << 17]byte +var z5391 [1 << 17]byte +var z5392 [1 << 17]byte +var z5393 [1 << 17]byte +var z5394 [1 << 17]byte +var z5395 [1 << 17]byte +var z5396 [1 << 17]byte +var z5397 [1 << 17]byte +var z5398 [1 << 17]byte +var z5399 [1 << 17]byte +var z5400 [1 << 17]byte +var z5401 [1 << 17]byte +var z5402 [1 << 17]byte +var z5403 [1 << 17]byte +var z5404 [1 << 17]byte +var z5405 [1 << 17]byte +var z5406 [1 << 17]byte +var z5407 [1 << 17]byte +var z5408 [1 << 17]byte +var z5409 [1 << 17]byte +var z5410 [1 << 17]byte +var z5411 [1 << 17]byte +var z5412 [1 << 17]byte +var z5413 [1 << 17]byte +var z5414 [1 << 17]byte +var z5415 [1 << 17]byte +var z5416 [1 << 17]byte +var z5417 [1 << 17]byte +var z5418 [1 << 17]byte +var z5419 [1 << 17]byte +var z5420 [1 << 17]byte +var z5421 [1 << 17]byte +var z5422 [1 << 17]byte +var z5423 [1 << 17]byte +var z5424 [1 << 17]byte +var z5425 [1 << 17]byte +var z5426 [1 << 17]byte +var z5427 [1 << 17]byte +var z5428 [1 << 17]byte +var z5429 [1 << 17]byte +var z5430 [1 << 17]byte +var z5431 [1 << 17]byte +var z5432 [1 << 17]byte +var z5433 [1 << 17]byte +var z5434 [1 << 17]byte +var z5435 [1 << 17]byte +var z5436 [1 << 17]byte +var z5437 [1 << 17]byte +var z5438 [1 << 17]byte +var z5439 [1 << 17]byte +var z5440 [1 << 17]byte +var z5441 [1 << 17]byte +var z5442 [1 << 17]byte +var z5443 [1 << 17]byte +var z5444 [1 << 17]byte +var z5445 [1 << 17]byte +var z5446 [1 << 17]byte +var z5447 [1 << 17]byte +var z5448 [1 << 17]byte +var z5449 [1 << 17]byte +var z5450 [1 << 17]byte +var z5451 [1 << 17]byte +var z5452 [1 << 17]byte +var z5453 [1 << 17]byte +var z5454 [1 << 17]byte +var z5455 [1 << 17]byte +var z5456 [1 << 17]byte +var z5457 [1 << 17]byte +var z5458 [1 << 17]byte +var z5459 [1 << 17]byte +var z5460 [1 << 17]byte +var z5461 [1 << 17]byte +var z5462 [1 << 17]byte +var z5463 [1 << 17]byte +var z5464 [1 << 17]byte +var z5465 [1 << 17]byte +var z5466 [1 << 17]byte +var z5467 [1 << 17]byte +var z5468 [1 << 17]byte +var z5469 [1 << 17]byte +var z5470 [1 << 17]byte +var z5471 [1 << 17]byte +var z5472 [1 << 17]byte +var z5473 [1 << 17]byte +var z5474 [1 << 17]byte +var z5475 [1 << 17]byte +var z5476 [1 << 17]byte +var z5477 [1 << 17]byte +var z5478 [1 << 17]byte +var z5479 [1 << 17]byte +var z5480 [1 << 17]byte +var z5481 [1 << 17]byte +var z5482 [1 << 17]byte +var z5483 [1 << 17]byte +var z5484 [1 << 17]byte +var z5485 [1 << 17]byte +var z5486 [1 << 17]byte +var z5487 [1 << 17]byte +var z5488 [1 << 17]byte +var z5489 [1 << 17]byte +var z5490 [1 << 17]byte +var z5491 [1 << 17]byte +var z5492 [1 << 17]byte +var z5493 [1 << 17]byte +var z5494 [1 << 17]byte +var z5495 [1 << 17]byte +var z5496 [1 << 17]byte +var z5497 [1 << 17]byte +var z5498 [1 << 17]byte +var z5499 [1 << 17]byte +var z5500 [1 << 17]byte +var z5501 [1 << 17]byte +var z5502 [1 << 17]byte +var z5503 [1 << 17]byte +var z5504 [1 << 17]byte +var z5505 [1 << 17]byte +var z5506 [1 << 17]byte +var z5507 [1 << 17]byte +var z5508 [1 << 17]byte +var z5509 [1 << 17]byte +var z5510 [1 << 17]byte +var z5511 [1 << 17]byte +var z5512 [1 << 17]byte +var z5513 [1 << 17]byte +var z5514 [1 << 17]byte +var z5515 [1 << 17]byte +var z5516 [1 << 17]byte +var z5517 [1 << 17]byte +var z5518 [1 << 17]byte +var z5519 [1 << 17]byte +var z5520 [1 << 17]byte +var z5521 [1 << 17]byte +var z5522 [1 << 17]byte +var z5523 [1 << 17]byte +var z5524 [1 << 17]byte +var z5525 [1 << 17]byte +var z5526 [1 << 17]byte +var z5527 [1 << 17]byte +var z5528 [1 << 17]byte +var z5529 [1 << 17]byte +var z5530 [1 << 17]byte +var z5531 [1 << 17]byte +var z5532 [1 << 17]byte +var z5533 [1 << 17]byte +var z5534 [1 << 17]byte +var z5535 [1 << 17]byte +var z5536 [1 << 17]byte +var z5537 [1 << 17]byte +var z5538 [1 << 17]byte +var z5539 [1 << 17]byte +var z5540 [1 << 17]byte +var z5541 [1 << 17]byte +var z5542 [1 << 17]byte +var z5543 [1 << 17]byte +var z5544 [1 << 17]byte +var z5545 [1 << 17]byte +var z5546 [1 << 17]byte +var z5547 [1 << 17]byte +var z5548 [1 << 17]byte +var z5549 [1 << 17]byte +var z5550 [1 << 17]byte +var z5551 [1 << 17]byte +var z5552 [1 << 17]byte +var z5553 [1 << 17]byte +var z5554 [1 << 17]byte +var z5555 [1 << 17]byte +var z5556 [1 << 17]byte +var z5557 [1 << 17]byte +var z5558 [1 << 17]byte +var z5559 [1 << 17]byte +var z5560 [1 << 17]byte +var z5561 [1 << 17]byte +var z5562 [1 << 17]byte +var z5563 [1 << 17]byte +var z5564 [1 << 17]byte +var z5565 [1 << 17]byte +var z5566 [1 << 17]byte +var z5567 [1 << 17]byte +var z5568 [1 << 17]byte +var z5569 [1 << 17]byte +var z5570 [1 << 17]byte +var z5571 [1 << 17]byte +var z5572 [1 << 17]byte +var z5573 [1 << 17]byte +var z5574 [1 << 17]byte +var z5575 [1 << 17]byte +var z5576 [1 << 17]byte +var z5577 [1 << 17]byte +var z5578 [1 << 17]byte +var z5579 [1 << 17]byte +var z5580 [1 << 17]byte +var z5581 [1 << 17]byte +var z5582 [1 << 17]byte +var z5583 [1 << 17]byte +var z5584 [1 << 17]byte +var z5585 [1 << 17]byte +var z5586 [1 << 17]byte +var z5587 [1 << 17]byte +var z5588 [1 << 17]byte +var z5589 [1 << 17]byte +var z5590 [1 << 17]byte +var z5591 [1 << 17]byte +var z5592 [1 << 17]byte +var z5593 [1 << 17]byte +var z5594 [1 << 17]byte +var z5595 [1 << 17]byte +var z5596 [1 << 17]byte +var z5597 [1 << 17]byte +var z5598 [1 << 17]byte +var z5599 [1 << 17]byte +var z5600 [1 << 17]byte +var z5601 [1 << 17]byte +var z5602 [1 << 17]byte +var z5603 [1 << 17]byte +var z5604 [1 << 17]byte +var z5605 [1 << 17]byte +var z5606 [1 << 17]byte +var z5607 [1 << 17]byte +var z5608 [1 << 17]byte +var z5609 [1 << 17]byte +var z5610 [1 << 17]byte +var z5611 [1 << 17]byte +var z5612 [1 << 17]byte +var z5613 [1 << 17]byte +var z5614 [1 << 17]byte +var z5615 [1 << 17]byte +var z5616 [1 << 17]byte +var z5617 [1 << 17]byte +var z5618 [1 << 17]byte +var z5619 [1 << 17]byte +var z5620 [1 << 17]byte +var z5621 [1 << 17]byte +var z5622 [1 << 17]byte +var z5623 [1 << 17]byte +var z5624 [1 << 17]byte +var z5625 [1 << 17]byte +var z5626 [1 << 17]byte +var z5627 [1 << 17]byte +var z5628 [1 << 17]byte +var z5629 [1 << 17]byte +var z5630 [1 << 17]byte +var z5631 [1 << 17]byte +var z5632 [1 << 17]byte +var z5633 [1 << 17]byte +var z5634 [1 << 17]byte +var z5635 [1 << 17]byte +var z5636 [1 << 17]byte +var z5637 [1 << 17]byte +var z5638 [1 << 17]byte +var z5639 [1 << 17]byte +var z5640 [1 << 17]byte +var z5641 [1 << 17]byte +var z5642 [1 << 17]byte +var z5643 [1 << 17]byte +var z5644 [1 << 17]byte +var z5645 [1 << 17]byte +var z5646 [1 << 17]byte +var z5647 [1 << 17]byte +var z5648 [1 << 17]byte +var z5649 [1 << 17]byte +var z5650 [1 << 17]byte +var z5651 [1 << 17]byte +var z5652 [1 << 17]byte +var z5653 [1 << 17]byte +var z5654 [1 << 17]byte +var z5655 [1 << 17]byte +var z5656 [1 << 17]byte +var z5657 [1 << 17]byte +var z5658 [1 << 17]byte +var z5659 [1 << 17]byte +var z5660 [1 << 17]byte +var z5661 [1 << 17]byte +var z5662 [1 << 17]byte +var z5663 [1 << 17]byte +var z5664 [1 << 17]byte +var z5665 [1 << 17]byte +var z5666 [1 << 17]byte +var z5667 [1 << 17]byte +var z5668 [1 << 17]byte +var z5669 [1 << 17]byte +var z5670 [1 << 17]byte +var z5671 [1 << 17]byte +var z5672 [1 << 17]byte +var z5673 [1 << 17]byte +var z5674 [1 << 17]byte +var z5675 [1 << 17]byte +var z5676 [1 << 17]byte +var z5677 [1 << 17]byte +var z5678 [1 << 17]byte +var z5679 [1 << 17]byte +var z5680 [1 << 17]byte +var z5681 [1 << 17]byte +var z5682 [1 << 17]byte +var z5683 [1 << 17]byte +var z5684 [1 << 17]byte +var z5685 [1 << 17]byte +var z5686 [1 << 17]byte +var z5687 [1 << 17]byte +var z5688 [1 << 17]byte +var z5689 [1 << 17]byte +var z5690 [1 << 17]byte +var z5691 [1 << 17]byte +var z5692 [1 << 17]byte +var z5693 [1 << 17]byte +var z5694 [1 << 17]byte +var z5695 [1 << 17]byte +var z5696 [1 << 17]byte +var z5697 [1 << 17]byte +var z5698 [1 << 17]byte +var z5699 [1 << 17]byte +var z5700 [1 << 17]byte +var z5701 [1 << 17]byte +var z5702 [1 << 17]byte +var z5703 [1 << 17]byte +var z5704 [1 << 17]byte +var z5705 [1 << 17]byte +var z5706 [1 << 17]byte +var z5707 [1 << 17]byte +var z5708 [1 << 17]byte +var z5709 [1 << 17]byte +var z5710 [1 << 17]byte +var z5711 [1 << 17]byte +var z5712 [1 << 17]byte +var z5713 [1 << 17]byte +var z5714 [1 << 17]byte +var z5715 [1 << 17]byte +var z5716 [1 << 17]byte +var z5717 [1 << 17]byte +var z5718 [1 << 17]byte +var z5719 [1 << 17]byte +var z5720 [1 << 17]byte +var z5721 [1 << 17]byte +var z5722 [1 << 17]byte +var z5723 [1 << 17]byte +var z5724 [1 << 17]byte +var z5725 [1 << 17]byte +var z5726 [1 << 17]byte +var z5727 [1 << 17]byte +var z5728 [1 << 17]byte +var z5729 [1 << 17]byte +var z5730 [1 << 17]byte +var z5731 [1 << 17]byte +var z5732 [1 << 17]byte +var z5733 [1 << 17]byte +var z5734 [1 << 17]byte +var z5735 [1 << 17]byte +var z5736 [1 << 17]byte +var z5737 [1 << 17]byte +var z5738 [1 << 17]byte +var z5739 [1 << 17]byte +var z5740 [1 << 17]byte +var z5741 [1 << 17]byte +var z5742 [1 << 17]byte +var z5743 [1 << 17]byte +var z5744 [1 << 17]byte +var z5745 [1 << 17]byte +var z5746 [1 << 17]byte +var z5747 [1 << 17]byte +var z5748 [1 << 17]byte +var z5749 [1 << 17]byte +var z5750 [1 << 17]byte +var z5751 [1 << 17]byte +var z5752 [1 << 17]byte +var z5753 [1 << 17]byte +var z5754 [1 << 17]byte +var z5755 [1 << 17]byte +var z5756 [1 << 17]byte +var z5757 [1 << 17]byte +var z5758 [1 << 17]byte +var z5759 [1 << 17]byte +var z5760 [1 << 17]byte +var z5761 [1 << 17]byte +var z5762 [1 << 17]byte +var z5763 [1 << 17]byte +var z5764 [1 << 17]byte +var z5765 [1 << 17]byte +var z5766 [1 << 17]byte +var z5767 [1 << 17]byte +var z5768 [1 << 17]byte +var z5769 [1 << 17]byte +var z5770 [1 << 17]byte +var z5771 [1 << 17]byte +var z5772 [1 << 17]byte +var z5773 [1 << 17]byte +var z5774 [1 << 17]byte +var z5775 [1 << 17]byte +var z5776 [1 << 17]byte +var z5777 [1 << 17]byte +var z5778 [1 << 17]byte +var z5779 [1 << 17]byte +var z5780 [1 << 17]byte +var z5781 [1 << 17]byte +var z5782 [1 << 17]byte +var z5783 [1 << 17]byte +var z5784 [1 << 17]byte +var z5785 [1 << 17]byte +var z5786 [1 << 17]byte +var z5787 [1 << 17]byte +var z5788 [1 << 17]byte +var z5789 [1 << 17]byte +var z5790 [1 << 17]byte +var z5791 [1 << 17]byte +var z5792 [1 << 17]byte +var z5793 [1 << 17]byte +var z5794 [1 << 17]byte +var z5795 [1 << 17]byte +var z5796 [1 << 17]byte +var z5797 [1 << 17]byte +var z5798 [1 << 17]byte +var z5799 [1 << 17]byte +var z5800 [1 << 17]byte +var z5801 [1 << 17]byte +var z5802 [1 << 17]byte +var z5803 [1 << 17]byte +var z5804 [1 << 17]byte +var z5805 [1 << 17]byte +var z5806 [1 << 17]byte +var z5807 [1 << 17]byte +var z5808 [1 << 17]byte +var z5809 [1 << 17]byte +var z5810 [1 << 17]byte +var z5811 [1 << 17]byte +var z5812 [1 << 17]byte +var z5813 [1 << 17]byte +var z5814 [1 << 17]byte +var z5815 [1 << 17]byte +var z5816 [1 << 17]byte +var z5817 [1 << 17]byte +var z5818 [1 << 17]byte +var z5819 [1 << 17]byte +var z5820 [1 << 17]byte +var z5821 [1 << 17]byte +var z5822 [1 << 17]byte +var z5823 [1 << 17]byte +var z5824 [1 << 17]byte +var z5825 [1 << 17]byte +var z5826 [1 << 17]byte +var z5827 [1 << 17]byte +var z5828 [1 << 17]byte +var z5829 [1 << 17]byte +var z5830 [1 << 17]byte +var z5831 [1 << 17]byte +var z5832 [1 << 17]byte +var z5833 [1 << 17]byte +var z5834 [1 << 17]byte +var z5835 [1 << 17]byte +var z5836 [1 << 17]byte +var z5837 [1 << 17]byte +var z5838 [1 << 17]byte +var z5839 [1 << 17]byte +var z5840 [1 << 17]byte +var z5841 [1 << 17]byte +var z5842 [1 << 17]byte +var z5843 [1 << 17]byte +var z5844 [1 << 17]byte +var z5845 [1 << 17]byte +var z5846 [1 << 17]byte +var z5847 [1 << 17]byte +var z5848 [1 << 17]byte +var z5849 [1 << 17]byte +var z5850 [1 << 17]byte +var z5851 [1 << 17]byte +var z5852 [1 << 17]byte +var z5853 [1 << 17]byte +var z5854 [1 << 17]byte +var z5855 [1 << 17]byte +var z5856 [1 << 17]byte +var z5857 [1 << 17]byte +var z5858 [1 << 17]byte +var z5859 [1 << 17]byte +var z5860 [1 << 17]byte +var z5861 [1 << 17]byte +var z5862 [1 << 17]byte +var z5863 [1 << 17]byte +var z5864 [1 << 17]byte +var z5865 [1 << 17]byte +var z5866 [1 << 17]byte +var z5867 [1 << 17]byte +var z5868 [1 << 17]byte +var z5869 [1 << 17]byte +var z5870 [1 << 17]byte +var z5871 [1 << 17]byte +var z5872 [1 << 17]byte +var z5873 [1 << 17]byte +var z5874 [1 << 17]byte +var z5875 [1 << 17]byte +var z5876 [1 << 17]byte +var z5877 [1 << 17]byte +var z5878 [1 << 17]byte +var z5879 [1 << 17]byte +var z5880 [1 << 17]byte +var z5881 [1 << 17]byte +var z5882 [1 << 17]byte +var z5883 [1 << 17]byte +var z5884 [1 << 17]byte +var z5885 [1 << 17]byte +var z5886 [1 << 17]byte +var z5887 [1 << 17]byte +var z5888 [1 << 17]byte +var z5889 [1 << 17]byte +var z5890 [1 << 17]byte +var z5891 [1 << 17]byte +var z5892 [1 << 17]byte +var z5893 [1 << 17]byte +var z5894 [1 << 17]byte +var z5895 [1 << 17]byte +var z5896 [1 << 17]byte +var z5897 [1 << 17]byte +var z5898 [1 << 17]byte +var z5899 [1 << 17]byte +var z5900 [1 << 17]byte +var z5901 [1 << 17]byte +var z5902 [1 << 17]byte +var z5903 [1 << 17]byte +var z5904 [1 << 17]byte +var z5905 [1 << 17]byte +var z5906 [1 << 17]byte +var z5907 [1 << 17]byte +var z5908 [1 << 17]byte +var z5909 [1 << 17]byte +var z5910 [1 << 17]byte +var z5911 [1 << 17]byte +var z5912 [1 << 17]byte +var z5913 [1 << 17]byte +var z5914 [1 << 17]byte +var z5915 [1 << 17]byte +var z5916 [1 << 17]byte +var z5917 [1 << 17]byte +var z5918 [1 << 17]byte +var z5919 [1 << 17]byte +var z5920 [1 << 17]byte +var z5921 [1 << 17]byte +var z5922 [1 << 17]byte +var z5923 [1 << 17]byte +var z5924 [1 << 17]byte +var z5925 [1 << 17]byte +var z5926 [1 << 17]byte +var z5927 [1 << 17]byte +var z5928 [1 << 17]byte +var z5929 [1 << 17]byte +var z5930 [1 << 17]byte +var z5931 [1 << 17]byte +var z5932 [1 << 17]byte +var z5933 [1 << 17]byte +var z5934 [1 << 17]byte +var z5935 [1 << 17]byte +var z5936 [1 << 17]byte +var z5937 [1 << 17]byte +var z5938 [1 << 17]byte +var z5939 [1 << 17]byte +var z5940 [1 << 17]byte +var z5941 [1 << 17]byte +var z5942 [1 << 17]byte +var z5943 [1 << 17]byte +var z5944 [1 << 17]byte +var z5945 [1 << 17]byte +var z5946 [1 << 17]byte +var z5947 [1 << 17]byte +var z5948 [1 << 17]byte +var z5949 [1 << 17]byte +var z5950 [1 << 17]byte +var z5951 [1 << 17]byte +var z5952 [1 << 17]byte +var z5953 [1 << 17]byte +var z5954 [1 << 17]byte +var z5955 [1 << 17]byte +var z5956 [1 << 17]byte +var z5957 [1 << 17]byte +var z5958 [1 << 17]byte +var z5959 [1 << 17]byte +var z5960 [1 << 17]byte +var z5961 [1 << 17]byte +var z5962 [1 << 17]byte +var z5963 [1 << 17]byte +var z5964 [1 << 17]byte +var z5965 [1 << 17]byte +var z5966 [1 << 17]byte +var z5967 [1 << 17]byte +var z5968 [1 << 17]byte +var z5969 [1 << 17]byte +var z5970 [1 << 17]byte +var z5971 [1 << 17]byte +var z5972 [1 << 17]byte +var z5973 [1 << 17]byte +var z5974 [1 << 17]byte +var z5975 [1 << 17]byte +var z5976 [1 << 17]byte +var z5977 [1 << 17]byte +var z5978 [1 << 17]byte +var z5979 [1 << 17]byte +var z5980 [1 << 17]byte +var z5981 [1 << 17]byte +var z5982 [1 << 17]byte +var z5983 [1 << 17]byte +var z5984 [1 << 17]byte +var z5985 [1 << 17]byte +var z5986 [1 << 17]byte +var z5987 [1 << 17]byte +var z5988 [1 << 17]byte +var z5989 [1 << 17]byte +var z5990 [1 << 17]byte +var z5991 [1 << 17]byte +var z5992 [1 << 17]byte +var z5993 [1 << 17]byte +var z5994 [1 << 17]byte +var z5995 [1 << 17]byte +var z5996 [1 << 17]byte +var z5997 [1 << 17]byte +var z5998 [1 << 17]byte +var z5999 [1 << 17]byte +var z6000 [1 << 17]byte +var z6001 [1 << 17]byte +var z6002 [1 << 17]byte +var z6003 [1 << 17]byte +var z6004 [1 << 17]byte +var z6005 [1 << 17]byte +var z6006 [1 << 17]byte +var z6007 [1 << 17]byte +var z6008 [1 << 17]byte +var z6009 [1 << 17]byte +var z6010 [1 << 17]byte +var z6011 [1 << 17]byte +var z6012 [1 << 17]byte +var z6013 [1 << 17]byte +var z6014 [1 << 17]byte +var z6015 [1 << 17]byte +var z6016 [1 << 17]byte +var z6017 [1 << 17]byte +var z6018 [1 << 17]byte +var z6019 [1 << 17]byte +var z6020 [1 << 17]byte +var z6021 [1 << 17]byte +var z6022 [1 << 17]byte +var z6023 [1 << 17]byte +var z6024 [1 << 17]byte +var z6025 [1 << 17]byte +var z6026 [1 << 17]byte +var z6027 [1 << 17]byte +var z6028 [1 << 17]byte +var z6029 [1 << 17]byte +var z6030 [1 << 17]byte +var z6031 [1 << 17]byte +var z6032 [1 << 17]byte +var z6033 [1 << 17]byte +var z6034 [1 << 17]byte +var z6035 [1 << 17]byte +var z6036 [1 << 17]byte +var z6037 [1 << 17]byte +var z6038 [1 << 17]byte +var z6039 [1 << 17]byte +var z6040 [1 << 17]byte +var z6041 [1 << 17]byte +var z6042 [1 << 17]byte +var z6043 [1 << 17]byte +var z6044 [1 << 17]byte +var z6045 [1 << 17]byte +var z6046 [1 << 17]byte +var z6047 [1 << 17]byte +var z6048 [1 << 17]byte +var z6049 [1 << 17]byte +var z6050 [1 << 17]byte +var z6051 [1 << 17]byte +var z6052 [1 << 17]byte +var z6053 [1 << 17]byte +var z6054 [1 << 17]byte +var z6055 [1 << 17]byte +var z6056 [1 << 17]byte +var z6057 [1 << 17]byte +var z6058 [1 << 17]byte +var z6059 [1 << 17]byte +var z6060 [1 << 17]byte +var z6061 [1 << 17]byte +var z6062 [1 << 17]byte +var z6063 [1 << 17]byte +var z6064 [1 << 17]byte +var z6065 [1 << 17]byte +var z6066 [1 << 17]byte +var z6067 [1 << 17]byte +var z6068 [1 << 17]byte +var z6069 [1 << 17]byte +var z6070 [1 << 17]byte +var z6071 [1 << 17]byte +var z6072 [1 << 17]byte +var z6073 [1 << 17]byte +var z6074 [1 << 17]byte +var z6075 [1 << 17]byte +var z6076 [1 << 17]byte +var z6077 [1 << 17]byte +var z6078 [1 << 17]byte +var z6079 [1 << 17]byte +var z6080 [1 << 17]byte +var z6081 [1 << 17]byte +var z6082 [1 << 17]byte +var z6083 [1 << 17]byte +var z6084 [1 << 17]byte +var z6085 [1 << 17]byte +var z6086 [1 << 17]byte +var z6087 [1 << 17]byte +var z6088 [1 << 17]byte +var z6089 [1 << 17]byte +var z6090 [1 << 17]byte +var z6091 [1 << 17]byte +var z6092 [1 << 17]byte +var z6093 [1 << 17]byte +var z6094 [1 << 17]byte +var z6095 [1 << 17]byte +var z6096 [1 << 17]byte +var z6097 [1 << 17]byte +var z6098 [1 << 17]byte +var z6099 [1 << 17]byte +var z6100 [1 << 17]byte +var z6101 [1 << 17]byte +var z6102 [1 << 17]byte +var z6103 [1 << 17]byte +var z6104 [1 << 17]byte +var z6105 [1 << 17]byte +var z6106 [1 << 17]byte +var z6107 [1 << 17]byte +var z6108 [1 << 17]byte +var z6109 [1 << 17]byte +var z6110 [1 << 17]byte +var z6111 [1 << 17]byte +var z6112 [1 << 17]byte +var z6113 [1 << 17]byte +var z6114 [1 << 17]byte +var z6115 [1 << 17]byte +var z6116 [1 << 17]byte +var z6117 [1 << 17]byte +var z6118 [1 << 17]byte +var z6119 [1 << 17]byte +var z6120 [1 << 17]byte +var z6121 [1 << 17]byte +var z6122 [1 << 17]byte +var z6123 [1 << 17]byte +var z6124 [1 << 17]byte +var z6125 [1 << 17]byte +var z6126 [1 << 17]byte +var z6127 [1 << 17]byte +var z6128 [1 << 17]byte +var z6129 [1 << 17]byte +var z6130 [1 << 17]byte +var z6131 [1 << 17]byte +var z6132 [1 << 17]byte +var z6133 [1 << 17]byte +var z6134 [1 << 17]byte +var z6135 [1 << 17]byte +var z6136 [1 << 17]byte +var z6137 [1 << 17]byte +var z6138 [1 << 17]byte +var z6139 [1 << 17]byte +var z6140 [1 << 17]byte +var z6141 [1 << 17]byte +var z6142 [1 << 17]byte +var z6143 [1 << 17]byte +var z6144 [1 << 17]byte +var z6145 [1 << 17]byte +var z6146 [1 << 17]byte +var z6147 [1 << 17]byte +var z6148 [1 << 17]byte +var z6149 [1 << 17]byte +var z6150 [1 << 17]byte +var z6151 [1 << 17]byte +var z6152 [1 << 17]byte +var z6153 [1 << 17]byte +var z6154 [1 << 17]byte +var z6155 [1 << 17]byte +var z6156 [1 << 17]byte +var z6157 [1 << 17]byte +var z6158 [1 << 17]byte +var z6159 [1 << 17]byte +var z6160 [1 << 17]byte +var z6161 [1 << 17]byte +var z6162 [1 << 17]byte +var z6163 [1 << 17]byte +var z6164 [1 << 17]byte +var z6165 [1 << 17]byte +var z6166 [1 << 17]byte +var z6167 [1 << 17]byte +var z6168 [1 << 17]byte +var z6169 [1 << 17]byte +var z6170 [1 << 17]byte +var z6171 [1 << 17]byte +var z6172 [1 << 17]byte +var z6173 [1 << 17]byte +var z6174 [1 << 17]byte +var z6175 [1 << 17]byte +var z6176 [1 << 17]byte +var z6177 [1 << 17]byte +var z6178 [1 << 17]byte +var z6179 [1 << 17]byte +var z6180 [1 << 17]byte +var z6181 [1 << 17]byte +var z6182 [1 << 17]byte +var z6183 [1 << 17]byte +var z6184 [1 << 17]byte +var z6185 [1 << 17]byte +var z6186 [1 << 17]byte +var z6187 [1 << 17]byte +var z6188 [1 << 17]byte +var z6189 [1 << 17]byte +var z6190 [1 << 17]byte +var z6191 [1 << 17]byte +var z6192 [1 << 17]byte +var z6193 [1 << 17]byte +var z6194 [1 << 17]byte +var z6195 [1 << 17]byte +var z6196 [1 << 17]byte +var z6197 [1 << 17]byte +var z6198 [1 << 17]byte +var z6199 [1 << 17]byte +var z6200 [1 << 17]byte +var z6201 [1 << 17]byte +var z6202 [1 << 17]byte +var z6203 [1 << 17]byte +var z6204 [1 << 17]byte +var z6205 [1 << 17]byte +var z6206 [1 << 17]byte +var z6207 [1 << 17]byte +var z6208 [1 << 17]byte +var z6209 [1 << 17]byte +var z6210 [1 << 17]byte +var z6211 [1 << 17]byte +var z6212 [1 << 17]byte +var z6213 [1 << 17]byte +var z6214 [1 << 17]byte +var z6215 [1 << 17]byte +var z6216 [1 << 17]byte +var z6217 [1 << 17]byte +var z6218 [1 << 17]byte +var z6219 [1 << 17]byte +var z6220 [1 << 17]byte +var z6221 [1 << 17]byte +var z6222 [1 << 17]byte +var z6223 [1 << 17]byte +var z6224 [1 << 17]byte +var z6225 [1 << 17]byte +var z6226 [1 << 17]byte +var z6227 [1 << 17]byte +var z6228 [1 << 17]byte +var z6229 [1 << 17]byte +var z6230 [1 << 17]byte +var z6231 [1 << 17]byte +var z6232 [1 << 17]byte +var z6233 [1 << 17]byte +var z6234 [1 << 17]byte +var z6235 [1 << 17]byte +var z6236 [1 << 17]byte +var z6237 [1 << 17]byte +var z6238 [1 << 17]byte +var z6239 [1 << 17]byte +var z6240 [1 << 17]byte +var z6241 [1 << 17]byte +var z6242 [1 << 17]byte +var z6243 [1 << 17]byte +var z6244 [1 << 17]byte +var z6245 [1 << 17]byte +var z6246 [1 << 17]byte +var z6247 [1 << 17]byte +var z6248 [1 << 17]byte +var z6249 [1 << 17]byte +var z6250 [1 << 17]byte +var z6251 [1 << 17]byte +var z6252 [1 << 17]byte +var z6253 [1 << 17]byte +var z6254 [1 << 17]byte +var z6255 [1 << 17]byte +var z6256 [1 << 17]byte +var z6257 [1 << 17]byte +var z6258 [1 << 17]byte +var z6259 [1 << 17]byte +var z6260 [1 << 17]byte +var z6261 [1 << 17]byte +var z6262 [1 << 17]byte +var z6263 [1 << 17]byte +var z6264 [1 << 17]byte +var z6265 [1 << 17]byte +var z6266 [1 << 17]byte +var z6267 [1 << 17]byte +var z6268 [1 << 17]byte +var z6269 [1 << 17]byte +var z6270 [1 << 17]byte +var z6271 [1 << 17]byte +var z6272 [1 << 17]byte +var z6273 [1 << 17]byte +var z6274 [1 << 17]byte +var z6275 [1 << 17]byte +var z6276 [1 << 17]byte +var z6277 [1 << 17]byte +var z6278 [1 << 17]byte +var z6279 [1 << 17]byte +var z6280 [1 << 17]byte +var z6281 [1 << 17]byte +var z6282 [1 << 17]byte +var z6283 [1 << 17]byte +var z6284 [1 << 17]byte +var z6285 [1 << 17]byte +var z6286 [1 << 17]byte +var z6287 [1 << 17]byte +var z6288 [1 << 17]byte +var z6289 [1 << 17]byte +var z6290 [1 << 17]byte +var z6291 [1 << 17]byte +var z6292 [1 << 17]byte +var z6293 [1 << 17]byte +var z6294 [1 << 17]byte +var z6295 [1 << 17]byte +var z6296 [1 << 17]byte +var z6297 [1 << 17]byte +var z6298 [1 << 17]byte +var z6299 [1 << 17]byte +var z6300 [1 << 17]byte +var z6301 [1 << 17]byte +var z6302 [1 << 17]byte +var z6303 [1 << 17]byte +var z6304 [1 << 17]byte +var z6305 [1 << 17]byte +var z6306 [1 << 17]byte +var z6307 [1 << 17]byte +var z6308 [1 << 17]byte +var z6309 [1 << 17]byte +var z6310 [1 << 17]byte +var z6311 [1 << 17]byte +var z6312 [1 << 17]byte +var z6313 [1 << 17]byte +var z6314 [1 << 17]byte +var z6315 [1 << 17]byte +var z6316 [1 << 17]byte +var z6317 [1 << 17]byte +var z6318 [1 << 17]byte +var z6319 [1 << 17]byte +var z6320 [1 << 17]byte +var z6321 [1 << 17]byte +var z6322 [1 << 17]byte +var z6323 [1 << 17]byte +var z6324 [1 << 17]byte +var z6325 [1 << 17]byte +var z6326 [1 << 17]byte +var z6327 [1 << 17]byte +var z6328 [1 << 17]byte +var z6329 [1 << 17]byte +var z6330 [1 << 17]byte +var z6331 [1 << 17]byte +var z6332 [1 << 17]byte +var z6333 [1 << 17]byte +var z6334 [1 << 17]byte +var z6335 [1 << 17]byte +var z6336 [1 << 17]byte +var z6337 [1 << 17]byte +var z6338 [1 << 17]byte +var z6339 [1 << 17]byte +var z6340 [1 << 17]byte +var z6341 [1 << 17]byte +var z6342 [1 << 17]byte +var z6343 [1 << 17]byte +var z6344 [1 << 17]byte +var z6345 [1 << 17]byte +var z6346 [1 << 17]byte +var z6347 [1 << 17]byte +var z6348 [1 << 17]byte +var z6349 [1 << 17]byte +var z6350 [1 << 17]byte +var z6351 [1 << 17]byte +var z6352 [1 << 17]byte +var z6353 [1 << 17]byte +var z6354 [1 << 17]byte +var z6355 [1 << 17]byte +var z6356 [1 << 17]byte +var z6357 [1 << 17]byte +var z6358 [1 << 17]byte +var z6359 [1 << 17]byte +var z6360 [1 << 17]byte +var z6361 [1 << 17]byte +var z6362 [1 << 17]byte +var z6363 [1 << 17]byte +var z6364 [1 << 17]byte +var z6365 [1 << 17]byte +var z6366 [1 << 17]byte +var z6367 [1 << 17]byte +var z6368 [1 << 17]byte +var z6369 [1 << 17]byte +var z6370 [1 << 17]byte +var z6371 [1 << 17]byte +var z6372 [1 << 17]byte +var z6373 [1 << 17]byte +var z6374 [1 << 17]byte +var z6375 [1 << 17]byte +var z6376 [1 << 17]byte +var z6377 [1 << 17]byte +var z6378 [1 << 17]byte +var z6379 [1 << 17]byte +var z6380 [1 << 17]byte +var z6381 [1 << 17]byte +var z6382 [1 << 17]byte +var z6383 [1 << 17]byte +var z6384 [1 << 17]byte +var z6385 [1 << 17]byte +var z6386 [1 << 17]byte +var z6387 [1 << 17]byte +var z6388 [1 << 17]byte +var z6389 [1 << 17]byte +var z6390 [1 << 17]byte +var z6391 [1 << 17]byte +var z6392 [1 << 17]byte +var z6393 [1 << 17]byte +var z6394 [1 << 17]byte +var z6395 [1 << 17]byte +var z6396 [1 << 17]byte +var z6397 [1 << 17]byte +var z6398 [1 << 17]byte +var z6399 [1 << 17]byte +var z6400 [1 << 17]byte +var z6401 [1 << 17]byte +var z6402 [1 << 17]byte +var z6403 [1 << 17]byte +var z6404 [1 << 17]byte +var z6405 [1 << 17]byte +var z6406 [1 << 17]byte +var z6407 [1 << 17]byte +var z6408 [1 << 17]byte +var z6409 [1 << 17]byte +var z6410 [1 << 17]byte +var z6411 [1 << 17]byte +var z6412 [1 << 17]byte +var z6413 [1 << 17]byte +var z6414 [1 << 17]byte +var z6415 [1 << 17]byte +var z6416 [1 << 17]byte +var z6417 [1 << 17]byte +var z6418 [1 << 17]byte +var z6419 [1 << 17]byte +var z6420 [1 << 17]byte +var z6421 [1 << 17]byte +var z6422 [1 << 17]byte +var z6423 [1 << 17]byte +var z6424 [1 << 17]byte +var z6425 [1 << 17]byte +var z6426 [1 << 17]byte +var z6427 [1 << 17]byte +var z6428 [1 << 17]byte +var z6429 [1 << 17]byte +var z6430 [1 << 17]byte +var z6431 [1 << 17]byte +var z6432 [1 << 17]byte +var z6433 [1 << 17]byte +var z6434 [1 << 17]byte +var z6435 [1 << 17]byte +var z6436 [1 << 17]byte +var z6437 [1 << 17]byte +var z6438 [1 << 17]byte +var z6439 [1 << 17]byte +var z6440 [1 << 17]byte +var z6441 [1 << 17]byte +var z6442 [1 << 17]byte +var z6443 [1 << 17]byte +var z6444 [1 << 17]byte +var z6445 [1 << 17]byte +var z6446 [1 << 17]byte +var z6447 [1 << 17]byte +var z6448 [1 << 17]byte +var z6449 [1 << 17]byte +var z6450 [1 << 17]byte +var z6451 [1 << 17]byte +var z6452 [1 << 17]byte +var z6453 [1 << 17]byte +var z6454 [1 << 17]byte +var z6455 [1 << 17]byte +var z6456 [1 << 17]byte +var z6457 [1 << 17]byte +var z6458 [1 << 17]byte +var z6459 [1 << 17]byte +var z6460 [1 << 17]byte +var z6461 [1 << 17]byte +var z6462 [1 << 17]byte +var z6463 [1 << 17]byte +var z6464 [1 << 17]byte +var z6465 [1 << 17]byte +var z6466 [1 << 17]byte +var z6467 [1 << 17]byte +var z6468 [1 << 17]byte +var z6469 [1 << 17]byte +var z6470 [1 << 17]byte +var z6471 [1 << 17]byte +var z6472 [1 << 17]byte +var z6473 [1 << 17]byte +var z6474 [1 << 17]byte +var z6475 [1 << 17]byte +var z6476 [1 << 17]byte +var z6477 [1 << 17]byte +var z6478 [1 << 17]byte +var z6479 [1 << 17]byte +var z6480 [1 << 17]byte +var z6481 [1 << 17]byte +var z6482 [1 << 17]byte +var z6483 [1 << 17]byte +var z6484 [1 << 17]byte +var z6485 [1 << 17]byte +var z6486 [1 << 17]byte +var z6487 [1 << 17]byte +var z6488 [1 << 17]byte +var z6489 [1 << 17]byte +var z6490 [1 << 17]byte +var z6491 [1 << 17]byte +var z6492 [1 << 17]byte +var z6493 [1 << 17]byte +var z6494 [1 << 17]byte +var z6495 [1 << 17]byte +var z6496 [1 << 17]byte +var z6497 [1 << 17]byte +var z6498 [1 << 17]byte +var z6499 [1 << 17]byte +var z6500 [1 << 17]byte +var z6501 [1 << 17]byte +var z6502 [1 << 17]byte +var z6503 [1 << 17]byte +var z6504 [1 << 17]byte +var z6505 [1 << 17]byte +var z6506 [1 << 17]byte +var z6507 [1 << 17]byte +var z6508 [1 << 17]byte +var z6509 [1 << 17]byte +var z6510 [1 << 17]byte +var z6511 [1 << 17]byte +var z6512 [1 << 17]byte +var z6513 [1 << 17]byte +var z6514 [1 << 17]byte +var z6515 [1 << 17]byte +var z6516 [1 << 17]byte +var z6517 [1 << 17]byte +var z6518 [1 << 17]byte +var z6519 [1 << 17]byte +var z6520 [1 << 17]byte +var z6521 [1 << 17]byte +var z6522 [1 << 17]byte +var z6523 [1 << 17]byte +var z6524 [1 << 17]byte +var z6525 [1 << 17]byte +var z6526 [1 << 17]byte +var z6527 [1 << 17]byte +var z6528 [1 << 17]byte +var z6529 [1 << 17]byte +var z6530 [1 << 17]byte +var z6531 [1 << 17]byte +var z6532 [1 << 17]byte +var z6533 [1 << 17]byte +var z6534 [1 << 17]byte +var z6535 [1 << 17]byte +var z6536 [1 << 17]byte +var z6537 [1 << 17]byte +var z6538 [1 << 17]byte +var z6539 [1 << 17]byte +var z6540 [1 << 17]byte +var z6541 [1 << 17]byte +var z6542 [1 << 17]byte +var z6543 [1 << 17]byte +var z6544 [1 << 17]byte +var z6545 [1 << 17]byte +var z6546 [1 << 17]byte +var z6547 [1 << 17]byte +var z6548 [1 << 17]byte +var z6549 [1 << 17]byte +var z6550 [1 << 17]byte +var z6551 [1 << 17]byte +var z6552 [1 << 17]byte +var z6553 [1 << 17]byte +var z6554 [1 << 17]byte +var z6555 [1 << 17]byte +var z6556 [1 << 17]byte +var z6557 [1 << 17]byte +var z6558 [1 << 17]byte +var z6559 [1 << 17]byte +var z6560 [1 << 17]byte +var z6561 [1 << 17]byte +var z6562 [1 << 17]byte +var z6563 [1 << 17]byte +var z6564 [1 << 17]byte +var z6565 [1 << 17]byte +var z6566 [1 << 17]byte +var z6567 [1 << 17]byte +var z6568 [1 << 17]byte +var z6569 [1 << 17]byte +var z6570 [1 << 17]byte +var z6571 [1 << 17]byte +var z6572 [1 << 17]byte +var z6573 [1 << 17]byte +var z6574 [1 << 17]byte +var z6575 [1 << 17]byte +var z6576 [1 << 17]byte +var z6577 [1 << 17]byte +var z6578 [1 << 17]byte +var z6579 [1 << 17]byte +var z6580 [1 << 17]byte +var z6581 [1 << 17]byte +var z6582 [1 << 17]byte +var z6583 [1 << 17]byte +var z6584 [1 << 17]byte +var z6585 [1 << 17]byte +var z6586 [1 << 17]byte +var z6587 [1 << 17]byte +var z6588 [1 << 17]byte +var z6589 [1 << 17]byte +var z6590 [1 << 17]byte +var z6591 [1 << 17]byte +var z6592 [1 << 17]byte +var z6593 [1 << 17]byte +var z6594 [1 << 17]byte +var z6595 [1 << 17]byte +var z6596 [1 << 17]byte +var z6597 [1 << 17]byte +var z6598 [1 << 17]byte +var z6599 [1 << 17]byte +var z6600 [1 << 17]byte +var z6601 [1 << 17]byte +var z6602 [1 << 17]byte +var z6603 [1 << 17]byte +var z6604 [1 << 17]byte +var z6605 [1 << 17]byte +var z6606 [1 << 17]byte +var z6607 [1 << 17]byte +var z6608 [1 << 17]byte +var z6609 [1 << 17]byte +var z6610 [1 << 17]byte +var z6611 [1 << 17]byte +var z6612 [1 << 17]byte +var z6613 [1 << 17]byte +var z6614 [1 << 17]byte +var z6615 [1 << 17]byte +var z6616 [1 << 17]byte +var z6617 [1 << 17]byte +var z6618 [1 << 17]byte +var z6619 [1 << 17]byte +var z6620 [1 << 17]byte +var z6621 [1 << 17]byte +var z6622 [1 << 17]byte +var z6623 [1 << 17]byte +var z6624 [1 << 17]byte +var z6625 [1 << 17]byte +var z6626 [1 << 17]byte +var z6627 [1 << 17]byte +var z6628 [1 << 17]byte +var z6629 [1 << 17]byte +var z6630 [1 << 17]byte +var z6631 [1 << 17]byte +var z6632 [1 << 17]byte +var z6633 [1 << 17]byte +var z6634 [1 << 17]byte +var z6635 [1 << 17]byte +var z6636 [1 << 17]byte +var z6637 [1 << 17]byte +var z6638 [1 << 17]byte +var z6639 [1 << 17]byte +var z6640 [1 << 17]byte +var z6641 [1 << 17]byte +var z6642 [1 << 17]byte +var z6643 [1 << 17]byte +var z6644 [1 << 17]byte +var z6645 [1 << 17]byte +var z6646 [1 << 17]byte +var z6647 [1 << 17]byte +var z6648 [1 << 17]byte +var z6649 [1 << 17]byte +var z6650 [1 << 17]byte +var z6651 [1 << 17]byte +var z6652 [1 << 17]byte +var z6653 [1 << 17]byte +var z6654 [1 << 17]byte +var z6655 [1 << 17]byte +var z6656 [1 << 17]byte +var z6657 [1 << 17]byte +var z6658 [1 << 17]byte +var z6659 [1 << 17]byte +var z6660 [1 << 17]byte +var z6661 [1 << 17]byte +var z6662 [1 << 17]byte +var z6663 [1 << 17]byte +var z6664 [1 << 17]byte +var z6665 [1 << 17]byte +var z6666 [1 << 17]byte +var z6667 [1 << 17]byte +var z6668 [1 << 17]byte +var z6669 [1 << 17]byte +var z6670 [1 << 17]byte +var z6671 [1 << 17]byte +var z6672 [1 << 17]byte +var z6673 [1 << 17]byte +var z6674 [1 << 17]byte +var z6675 [1 << 17]byte +var z6676 [1 << 17]byte +var z6677 [1 << 17]byte +var z6678 [1 << 17]byte +var z6679 [1 << 17]byte +var z6680 [1 << 17]byte +var z6681 [1 << 17]byte +var z6682 [1 << 17]byte +var z6683 [1 << 17]byte +var z6684 [1 << 17]byte +var z6685 [1 << 17]byte +var z6686 [1 << 17]byte +var z6687 [1 << 17]byte +var z6688 [1 << 17]byte +var z6689 [1 << 17]byte +var z6690 [1 << 17]byte +var z6691 [1 << 17]byte +var z6692 [1 << 17]byte +var z6693 [1 << 17]byte +var z6694 [1 << 17]byte +var z6695 [1 << 17]byte +var z6696 [1 << 17]byte +var z6697 [1 << 17]byte +var z6698 [1 << 17]byte +var z6699 [1 << 17]byte +var z6700 [1 << 17]byte +var z6701 [1 << 17]byte +var z6702 [1 << 17]byte +var z6703 [1 << 17]byte +var z6704 [1 << 17]byte +var z6705 [1 << 17]byte +var z6706 [1 << 17]byte +var z6707 [1 << 17]byte +var z6708 [1 << 17]byte +var z6709 [1 << 17]byte +var z6710 [1 << 17]byte +var z6711 [1 << 17]byte +var z6712 [1 << 17]byte +var z6713 [1 << 17]byte +var z6714 [1 << 17]byte +var z6715 [1 << 17]byte +var z6716 [1 << 17]byte +var z6717 [1 << 17]byte +var z6718 [1 << 17]byte +var z6719 [1 << 17]byte +var z6720 [1 << 17]byte +var z6721 [1 << 17]byte +var z6722 [1 << 17]byte +var z6723 [1 << 17]byte +var z6724 [1 << 17]byte +var z6725 [1 << 17]byte +var z6726 [1 << 17]byte +var z6727 [1 << 17]byte +var z6728 [1 << 17]byte +var z6729 [1 << 17]byte +var z6730 [1 << 17]byte +var z6731 [1 << 17]byte +var z6732 [1 << 17]byte +var z6733 [1 << 17]byte +var z6734 [1 << 17]byte +var z6735 [1 << 17]byte +var z6736 [1 << 17]byte +var z6737 [1 << 17]byte +var z6738 [1 << 17]byte +var z6739 [1 << 17]byte +var z6740 [1 << 17]byte +var z6741 [1 << 17]byte +var z6742 [1 << 17]byte +var z6743 [1 << 17]byte +var z6744 [1 << 17]byte +var z6745 [1 << 17]byte +var z6746 [1 << 17]byte +var z6747 [1 << 17]byte +var z6748 [1 << 17]byte +var z6749 [1 << 17]byte +var z6750 [1 << 17]byte +var z6751 [1 << 17]byte +var z6752 [1 << 17]byte +var z6753 [1 << 17]byte +var z6754 [1 << 17]byte +var z6755 [1 << 17]byte +var z6756 [1 << 17]byte +var z6757 [1 << 17]byte +var z6758 [1 << 17]byte +var z6759 [1 << 17]byte +var z6760 [1 << 17]byte +var z6761 [1 << 17]byte +var z6762 [1 << 17]byte +var z6763 [1 << 17]byte +var z6764 [1 << 17]byte +var z6765 [1 << 17]byte +var z6766 [1 << 17]byte +var z6767 [1 << 17]byte +var z6768 [1 << 17]byte +var z6769 [1 << 17]byte +var z6770 [1 << 17]byte +var z6771 [1 << 17]byte +var z6772 [1 << 17]byte +var z6773 [1 << 17]byte +var z6774 [1 << 17]byte +var z6775 [1 << 17]byte +var z6776 [1 << 17]byte +var z6777 [1 << 17]byte +var z6778 [1 << 17]byte +var z6779 [1 << 17]byte +var z6780 [1 << 17]byte +var z6781 [1 << 17]byte +var z6782 [1 << 17]byte +var z6783 [1 << 17]byte +var z6784 [1 << 17]byte +var z6785 [1 << 17]byte +var z6786 [1 << 17]byte +var z6787 [1 << 17]byte +var z6788 [1 << 17]byte +var z6789 [1 << 17]byte +var z6790 [1 << 17]byte +var z6791 [1 << 17]byte +var z6792 [1 << 17]byte +var z6793 [1 << 17]byte +var z6794 [1 << 17]byte +var z6795 [1 << 17]byte +var z6796 [1 << 17]byte +var z6797 [1 << 17]byte +var z6798 [1 << 17]byte +var z6799 [1 << 17]byte +var z6800 [1 << 17]byte +var z6801 [1 << 17]byte +var z6802 [1 << 17]byte +var z6803 [1 << 17]byte +var z6804 [1 << 17]byte +var z6805 [1 << 17]byte +var z6806 [1 << 17]byte +var z6807 [1 << 17]byte +var z6808 [1 << 17]byte +var z6809 [1 << 17]byte +var z6810 [1 << 17]byte +var z6811 [1 << 17]byte +var z6812 [1 << 17]byte +var z6813 [1 << 17]byte +var z6814 [1 << 17]byte +var z6815 [1 << 17]byte +var z6816 [1 << 17]byte +var z6817 [1 << 17]byte +var z6818 [1 << 17]byte +var z6819 [1 << 17]byte +var z6820 [1 << 17]byte +var z6821 [1 << 17]byte +var z6822 [1 << 17]byte +var z6823 [1 << 17]byte +var z6824 [1 << 17]byte +var z6825 [1 << 17]byte +var z6826 [1 << 17]byte +var z6827 [1 << 17]byte +var z6828 [1 << 17]byte +var z6829 [1 << 17]byte +var z6830 [1 << 17]byte +var z6831 [1 << 17]byte +var z6832 [1 << 17]byte +var z6833 [1 << 17]byte +var z6834 [1 << 17]byte +var z6835 [1 << 17]byte +var z6836 [1 << 17]byte +var z6837 [1 << 17]byte +var z6838 [1 << 17]byte +var z6839 [1 << 17]byte +var z6840 [1 << 17]byte +var z6841 [1 << 17]byte +var z6842 [1 << 17]byte +var z6843 [1 << 17]byte +var z6844 [1 << 17]byte +var z6845 [1 << 17]byte +var z6846 [1 << 17]byte +var z6847 [1 << 17]byte +var z6848 [1 << 17]byte +var z6849 [1 << 17]byte +var z6850 [1 << 17]byte +var z6851 [1 << 17]byte +var z6852 [1 << 17]byte +var z6853 [1 << 17]byte +var z6854 [1 << 17]byte +var z6855 [1 << 17]byte +var z6856 [1 << 17]byte +var z6857 [1 << 17]byte +var z6858 [1 << 17]byte +var z6859 [1 << 17]byte +var z6860 [1 << 17]byte +var z6861 [1 << 17]byte +var z6862 [1 << 17]byte +var z6863 [1 << 17]byte +var z6864 [1 << 17]byte +var z6865 [1 << 17]byte +var z6866 [1 << 17]byte +var z6867 [1 << 17]byte +var z6868 [1 << 17]byte +var z6869 [1 << 17]byte +var z6870 [1 << 17]byte +var z6871 [1 << 17]byte +var z6872 [1 << 17]byte +var z6873 [1 << 17]byte +var z6874 [1 << 17]byte +var z6875 [1 << 17]byte +var z6876 [1 << 17]byte +var z6877 [1 << 17]byte +var z6878 [1 << 17]byte +var z6879 [1 << 17]byte +var z6880 [1 << 17]byte +var z6881 [1 << 17]byte +var z6882 [1 << 17]byte +var z6883 [1 << 17]byte +var z6884 [1 << 17]byte +var z6885 [1 << 17]byte +var z6886 [1 << 17]byte +var z6887 [1 << 17]byte +var z6888 [1 << 17]byte +var z6889 [1 << 17]byte +var z6890 [1 << 17]byte +var z6891 [1 << 17]byte +var z6892 [1 << 17]byte +var z6893 [1 << 17]byte +var z6894 [1 << 17]byte +var z6895 [1 << 17]byte +var z6896 [1 << 17]byte +var z6897 [1 << 17]byte +var z6898 [1 << 17]byte +var z6899 [1 << 17]byte +var z6900 [1 << 17]byte +var z6901 [1 << 17]byte +var z6902 [1 << 17]byte +var z6903 [1 << 17]byte +var z6904 [1 << 17]byte +var z6905 [1 << 17]byte +var z6906 [1 << 17]byte +var z6907 [1 << 17]byte +var z6908 [1 << 17]byte +var z6909 [1 << 17]byte +var z6910 [1 << 17]byte +var z6911 [1 << 17]byte +var z6912 [1 << 17]byte +var z6913 [1 << 17]byte +var z6914 [1 << 17]byte +var z6915 [1 << 17]byte +var z6916 [1 << 17]byte +var z6917 [1 << 17]byte +var z6918 [1 << 17]byte +var z6919 [1 << 17]byte +var z6920 [1 << 17]byte +var z6921 [1 << 17]byte +var z6922 [1 << 17]byte +var z6923 [1 << 17]byte +var z6924 [1 << 17]byte +var z6925 [1 << 17]byte +var z6926 [1 << 17]byte +var z6927 [1 << 17]byte +var z6928 [1 << 17]byte +var z6929 [1 << 17]byte +var z6930 [1 << 17]byte +var z6931 [1 << 17]byte +var z6932 [1 << 17]byte +var z6933 [1 << 17]byte +var z6934 [1 << 17]byte +var z6935 [1 << 17]byte +var z6936 [1 << 17]byte +var z6937 [1 << 17]byte +var z6938 [1 << 17]byte +var z6939 [1 << 17]byte +var z6940 [1 << 17]byte +var z6941 [1 << 17]byte +var z6942 [1 << 17]byte +var z6943 [1 << 17]byte +var z6944 [1 << 17]byte +var z6945 [1 << 17]byte +var z6946 [1 << 17]byte +var z6947 [1 << 17]byte +var z6948 [1 << 17]byte +var z6949 [1 << 17]byte +var z6950 [1 << 17]byte +var z6951 [1 << 17]byte +var z6952 [1 << 17]byte +var z6953 [1 << 17]byte +var z6954 [1 << 17]byte +var z6955 [1 << 17]byte +var z6956 [1 << 17]byte +var z6957 [1 << 17]byte +var z6958 [1 << 17]byte +var z6959 [1 << 17]byte +var z6960 [1 << 17]byte +var z6961 [1 << 17]byte +var z6962 [1 << 17]byte +var z6963 [1 << 17]byte +var z6964 [1 << 17]byte +var z6965 [1 << 17]byte +var z6966 [1 << 17]byte +var z6967 [1 << 17]byte +var z6968 [1 << 17]byte +var z6969 [1 << 17]byte +var z6970 [1 << 17]byte +var z6971 [1 << 17]byte +var z6972 [1 << 17]byte +var z6973 [1 << 17]byte +var z6974 [1 << 17]byte +var z6975 [1 << 17]byte +var z6976 [1 << 17]byte +var z6977 [1 << 17]byte +var z6978 [1 << 17]byte +var z6979 [1 << 17]byte +var z6980 [1 << 17]byte +var z6981 [1 << 17]byte +var z6982 [1 << 17]byte +var z6983 [1 << 17]byte +var z6984 [1 << 17]byte +var z6985 [1 << 17]byte +var z6986 [1 << 17]byte +var z6987 [1 << 17]byte +var z6988 [1 << 17]byte +var z6989 [1 << 17]byte +var z6990 [1 << 17]byte +var z6991 [1 << 17]byte +var z6992 [1 << 17]byte +var z6993 [1 << 17]byte +var z6994 [1 << 17]byte +var z6995 [1 << 17]byte +var z6996 [1 << 17]byte +var z6997 [1 << 17]byte +var z6998 [1 << 17]byte +var z6999 [1 << 17]byte +var z7000 [1 << 17]byte +var z7001 [1 << 17]byte +var z7002 [1 << 17]byte +var z7003 [1 << 17]byte +var z7004 [1 << 17]byte +var z7005 [1 << 17]byte +var z7006 [1 << 17]byte +var z7007 [1 << 17]byte +var z7008 [1 << 17]byte +var z7009 [1 << 17]byte +var z7010 [1 << 17]byte +var z7011 [1 << 17]byte +var z7012 [1 << 17]byte +var z7013 [1 << 17]byte +var z7014 [1 << 17]byte +var z7015 [1 << 17]byte +var z7016 [1 << 17]byte +var z7017 [1 << 17]byte +var z7018 [1 << 17]byte +var z7019 [1 << 17]byte +var z7020 [1 << 17]byte +var z7021 [1 << 17]byte +var z7022 [1 << 17]byte +var z7023 [1 << 17]byte +var z7024 [1 << 17]byte +var z7025 [1 << 17]byte +var z7026 [1 << 17]byte +var z7027 [1 << 17]byte +var z7028 [1 << 17]byte +var z7029 [1 << 17]byte +var z7030 [1 << 17]byte +var z7031 [1 << 17]byte +var z7032 [1 << 17]byte +var z7033 [1 << 17]byte +var z7034 [1 << 17]byte +var z7035 [1 << 17]byte +var z7036 [1 << 17]byte +var z7037 [1 << 17]byte +var z7038 [1 << 17]byte +var z7039 [1 << 17]byte +var z7040 [1 << 17]byte +var z7041 [1 << 17]byte +var z7042 [1 << 17]byte +var z7043 [1 << 17]byte +var z7044 [1 << 17]byte +var z7045 [1 << 17]byte +var z7046 [1 << 17]byte +var z7047 [1 << 17]byte +var z7048 [1 << 17]byte +var z7049 [1 << 17]byte +var z7050 [1 << 17]byte +var z7051 [1 << 17]byte +var z7052 [1 << 17]byte +var z7053 [1 << 17]byte +var z7054 [1 << 17]byte +var z7055 [1 << 17]byte +var z7056 [1 << 17]byte +var z7057 [1 << 17]byte +var z7058 [1 << 17]byte +var z7059 [1 << 17]byte +var z7060 [1 << 17]byte +var z7061 [1 << 17]byte +var z7062 [1 << 17]byte +var z7063 [1 << 17]byte +var z7064 [1 << 17]byte +var z7065 [1 << 17]byte +var z7066 [1 << 17]byte +var z7067 [1 << 17]byte +var z7068 [1 << 17]byte +var z7069 [1 << 17]byte +var z7070 [1 << 17]byte +var z7071 [1 << 17]byte +var z7072 [1 << 17]byte +var z7073 [1 << 17]byte +var z7074 [1 << 17]byte +var z7075 [1 << 17]byte +var z7076 [1 << 17]byte +var z7077 [1 << 17]byte +var z7078 [1 << 17]byte +var z7079 [1 << 17]byte +var z7080 [1 << 17]byte +var z7081 [1 << 17]byte +var z7082 [1 << 17]byte +var z7083 [1 << 17]byte +var z7084 [1 << 17]byte +var z7085 [1 << 17]byte +var z7086 [1 << 17]byte +var z7087 [1 << 17]byte +var z7088 [1 << 17]byte +var z7089 [1 << 17]byte +var z7090 [1 << 17]byte +var z7091 [1 << 17]byte +var z7092 [1 << 17]byte +var z7093 [1 << 17]byte +var z7094 [1 << 17]byte +var z7095 [1 << 17]byte +var z7096 [1 << 17]byte +var z7097 [1 << 17]byte +var z7098 [1 << 17]byte +var z7099 [1 << 17]byte +var z7100 [1 << 17]byte +var z7101 [1 << 17]byte +var z7102 [1 << 17]byte +var z7103 [1 << 17]byte +var z7104 [1 << 17]byte +var z7105 [1 << 17]byte +var z7106 [1 << 17]byte +var z7107 [1 << 17]byte +var z7108 [1 << 17]byte +var z7109 [1 << 17]byte +var z7110 [1 << 17]byte +var z7111 [1 << 17]byte +var z7112 [1 << 17]byte +var z7113 [1 << 17]byte +var z7114 [1 << 17]byte +var z7115 [1 << 17]byte +var z7116 [1 << 17]byte +var z7117 [1 << 17]byte +var z7118 [1 << 17]byte +var z7119 [1 << 17]byte +var z7120 [1 << 17]byte +var z7121 [1 << 17]byte +var z7122 [1 << 17]byte +var z7123 [1 << 17]byte +var z7124 [1 << 17]byte +var z7125 [1 << 17]byte +var z7126 [1 << 17]byte +var z7127 [1 << 17]byte +var z7128 [1 << 17]byte +var z7129 [1 << 17]byte +var z7130 [1 << 17]byte +var z7131 [1 << 17]byte +var z7132 [1 << 17]byte +var z7133 [1 << 17]byte +var z7134 [1 << 17]byte +var z7135 [1 << 17]byte +var z7136 [1 << 17]byte +var z7137 [1 << 17]byte +var z7138 [1 << 17]byte +var z7139 [1 << 17]byte +var z7140 [1 << 17]byte +var z7141 [1 << 17]byte +var z7142 [1 << 17]byte +var z7143 [1 << 17]byte +var z7144 [1 << 17]byte +var z7145 [1 << 17]byte +var z7146 [1 << 17]byte +var z7147 [1 << 17]byte +var z7148 [1 << 17]byte +var z7149 [1 << 17]byte +var z7150 [1 << 17]byte +var z7151 [1 << 17]byte +var z7152 [1 << 17]byte +var z7153 [1 << 17]byte +var z7154 [1 << 17]byte +var z7155 [1 << 17]byte +var z7156 [1 << 17]byte +var z7157 [1 << 17]byte +var z7158 [1 << 17]byte +var z7159 [1 << 17]byte +var z7160 [1 << 17]byte +var z7161 [1 << 17]byte +var z7162 [1 << 17]byte +var z7163 [1 << 17]byte +var z7164 [1 << 17]byte +var z7165 [1 << 17]byte +var z7166 [1 << 17]byte +var z7167 [1 << 17]byte +var z7168 [1 << 17]byte +var z7169 [1 << 17]byte +var z7170 [1 << 17]byte +var z7171 [1 << 17]byte +var z7172 [1 << 17]byte +var z7173 [1 << 17]byte +var z7174 [1 << 17]byte +var z7175 [1 << 17]byte +var z7176 [1 << 17]byte +var z7177 [1 << 17]byte +var z7178 [1 << 17]byte +var z7179 [1 << 17]byte +var z7180 [1 << 17]byte +var z7181 [1 << 17]byte +var z7182 [1 << 17]byte +var z7183 [1 << 17]byte +var z7184 [1 << 17]byte +var z7185 [1 << 17]byte +var z7186 [1 << 17]byte +var z7187 [1 << 17]byte +var z7188 [1 << 17]byte +var z7189 [1 << 17]byte +var z7190 [1 << 17]byte +var z7191 [1 << 17]byte +var z7192 [1 << 17]byte +var z7193 [1 << 17]byte +var z7194 [1 << 17]byte +var z7195 [1 << 17]byte +var z7196 [1 << 17]byte +var z7197 [1 << 17]byte +var z7198 [1 << 17]byte +var z7199 [1 << 17]byte +var z7200 [1 << 17]byte +var z7201 [1 << 17]byte +var z7202 [1 << 17]byte +var z7203 [1 << 17]byte +var z7204 [1 << 17]byte +var z7205 [1 << 17]byte +var z7206 [1 << 17]byte +var z7207 [1 << 17]byte +var z7208 [1 << 17]byte +var z7209 [1 << 17]byte +var z7210 [1 << 17]byte +var z7211 [1 << 17]byte +var z7212 [1 << 17]byte +var z7213 [1 << 17]byte +var z7214 [1 << 17]byte +var z7215 [1 << 17]byte +var z7216 [1 << 17]byte +var z7217 [1 << 17]byte +var z7218 [1 << 17]byte +var z7219 [1 << 17]byte +var z7220 [1 << 17]byte +var z7221 [1 << 17]byte +var z7222 [1 << 17]byte +var z7223 [1 << 17]byte +var z7224 [1 << 17]byte +var z7225 [1 << 17]byte +var z7226 [1 << 17]byte +var z7227 [1 << 17]byte +var z7228 [1 << 17]byte +var z7229 [1 << 17]byte +var z7230 [1 << 17]byte +var z7231 [1 << 17]byte +var z7232 [1 << 17]byte +var z7233 [1 << 17]byte +var z7234 [1 << 17]byte +var z7235 [1 << 17]byte +var z7236 [1 << 17]byte +var z7237 [1 << 17]byte +var z7238 [1 << 17]byte +var z7239 [1 << 17]byte +var z7240 [1 << 17]byte +var z7241 [1 << 17]byte +var z7242 [1 << 17]byte +var z7243 [1 << 17]byte +var z7244 [1 << 17]byte +var z7245 [1 << 17]byte +var z7246 [1 << 17]byte +var z7247 [1 << 17]byte +var z7248 [1 << 17]byte +var z7249 [1 << 17]byte +var z7250 [1 << 17]byte +var z7251 [1 << 17]byte +var z7252 [1 << 17]byte +var z7253 [1 << 17]byte +var z7254 [1 << 17]byte +var z7255 [1 << 17]byte +var z7256 [1 << 17]byte +var z7257 [1 << 17]byte +var z7258 [1 << 17]byte +var z7259 [1 << 17]byte +var z7260 [1 << 17]byte +var z7261 [1 << 17]byte +var z7262 [1 << 17]byte +var z7263 [1 << 17]byte +var z7264 [1 << 17]byte +var z7265 [1 << 17]byte +var z7266 [1 << 17]byte +var z7267 [1 << 17]byte +var z7268 [1 << 17]byte +var z7269 [1 << 17]byte +var z7270 [1 << 17]byte +var z7271 [1 << 17]byte +var z7272 [1 << 17]byte +var z7273 [1 << 17]byte +var z7274 [1 << 17]byte +var z7275 [1 << 17]byte +var z7276 [1 << 17]byte +var z7277 [1 << 17]byte +var z7278 [1 << 17]byte +var z7279 [1 << 17]byte +var z7280 [1 << 17]byte +var z7281 [1 << 17]byte +var z7282 [1 << 17]byte +var z7283 [1 << 17]byte +var z7284 [1 << 17]byte +var z7285 [1 << 17]byte +var z7286 [1 << 17]byte +var z7287 [1 << 17]byte +var z7288 [1 << 17]byte +var z7289 [1 << 17]byte +var z7290 [1 << 17]byte +var z7291 [1 << 17]byte +var z7292 [1 << 17]byte +var z7293 [1 << 17]byte +var z7294 [1 << 17]byte +var z7295 [1 << 17]byte +var z7296 [1 << 17]byte +var z7297 [1 << 17]byte +var z7298 [1 << 17]byte +var z7299 [1 << 17]byte +var z7300 [1 << 17]byte +var z7301 [1 << 17]byte +var z7302 [1 << 17]byte +var z7303 [1 << 17]byte +var z7304 [1 << 17]byte +var z7305 [1 << 17]byte +var z7306 [1 << 17]byte +var z7307 [1 << 17]byte +var z7308 [1 << 17]byte +var z7309 [1 << 17]byte +var z7310 [1 << 17]byte +var z7311 [1 << 17]byte +var z7312 [1 << 17]byte +var z7313 [1 << 17]byte +var z7314 [1 << 17]byte +var z7315 [1 << 17]byte +var z7316 [1 << 17]byte +var z7317 [1 << 17]byte +var z7318 [1 << 17]byte +var z7319 [1 << 17]byte +var z7320 [1 << 17]byte +var z7321 [1 << 17]byte +var z7322 [1 << 17]byte +var z7323 [1 << 17]byte +var z7324 [1 << 17]byte +var z7325 [1 << 17]byte +var z7326 [1 << 17]byte +var z7327 [1 << 17]byte +var z7328 [1 << 17]byte +var z7329 [1 << 17]byte +var z7330 [1 << 17]byte +var z7331 [1 << 17]byte +var z7332 [1 << 17]byte +var z7333 [1 << 17]byte +var z7334 [1 << 17]byte +var z7335 [1 << 17]byte +var z7336 [1 << 17]byte +var z7337 [1 << 17]byte +var z7338 [1 << 17]byte +var z7339 [1 << 17]byte +var z7340 [1 << 17]byte +var z7341 [1 << 17]byte +var z7342 [1 << 17]byte +var z7343 [1 << 17]byte +var z7344 [1 << 17]byte +var z7345 [1 << 17]byte +var z7346 [1 << 17]byte +var z7347 [1 << 17]byte +var z7348 [1 << 17]byte +var z7349 [1 << 17]byte +var z7350 [1 << 17]byte +var z7351 [1 << 17]byte +var z7352 [1 << 17]byte +var z7353 [1 << 17]byte +var z7354 [1 << 17]byte +var z7355 [1 << 17]byte +var z7356 [1 << 17]byte +var z7357 [1 << 17]byte +var z7358 [1 << 17]byte +var z7359 [1 << 17]byte +var z7360 [1 << 17]byte +var z7361 [1 << 17]byte +var z7362 [1 << 17]byte +var z7363 [1 << 17]byte +var z7364 [1 << 17]byte +var z7365 [1 << 17]byte +var z7366 [1 << 17]byte +var z7367 [1 << 17]byte +var z7368 [1 << 17]byte +var z7369 [1 << 17]byte +var z7370 [1 << 17]byte +var z7371 [1 << 17]byte +var z7372 [1 << 17]byte +var z7373 [1 << 17]byte +var z7374 [1 << 17]byte +var z7375 [1 << 17]byte +var z7376 [1 << 17]byte +var z7377 [1 << 17]byte +var z7378 [1 << 17]byte +var z7379 [1 << 17]byte +var z7380 [1 << 17]byte +var z7381 [1 << 17]byte +var z7382 [1 << 17]byte +var z7383 [1 << 17]byte +var z7384 [1 << 17]byte +var z7385 [1 << 17]byte +var z7386 [1 << 17]byte +var z7387 [1 << 17]byte +var z7388 [1 << 17]byte +var z7389 [1 << 17]byte +var z7390 [1 << 17]byte +var z7391 [1 << 17]byte +var z7392 [1 << 17]byte +var z7393 [1 << 17]byte +var z7394 [1 << 17]byte +var z7395 [1 << 17]byte +var z7396 [1 << 17]byte +var z7397 [1 << 17]byte +var z7398 [1 << 17]byte +var z7399 [1 << 17]byte +var z7400 [1 << 17]byte +var z7401 [1 << 17]byte +var z7402 [1 << 17]byte +var z7403 [1 << 17]byte +var z7404 [1 << 17]byte +var z7405 [1 << 17]byte +var z7406 [1 << 17]byte +var z7407 [1 << 17]byte +var z7408 [1 << 17]byte +var z7409 [1 << 17]byte +var z7410 [1 << 17]byte +var z7411 [1 << 17]byte +var z7412 [1 << 17]byte +var z7413 [1 << 17]byte +var z7414 [1 << 17]byte +var z7415 [1 << 17]byte +var z7416 [1 << 17]byte +var z7417 [1 << 17]byte +var z7418 [1 << 17]byte +var z7419 [1 << 17]byte +var z7420 [1 << 17]byte +var z7421 [1 << 17]byte +var z7422 [1 << 17]byte +var z7423 [1 << 17]byte +var z7424 [1 << 17]byte +var z7425 [1 << 17]byte +var z7426 [1 << 17]byte +var z7427 [1 << 17]byte +var z7428 [1 << 17]byte +var z7429 [1 << 17]byte +var z7430 [1 << 17]byte +var z7431 [1 << 17]byte +var z7432 [1 << 17]byte +var z7433 [1 << 17]byte +var z7434 [1 << 17]byte +var z7435 [1 << 17]byte +var z7436 [1 << 17]byte +var z7437 [1 << 17]byte +var z7438 [1 << 17]byte +var z7439 [1 << 17]byte +var z7440 [1 << 17]byte +var z7441 [1 << 17]byte +var z7442 [1 << 17]byte +var z7443 [1 << 17]byte +var z7444 [1 << 17]byte +var z7445 [1 << 17]byte +var z7446 [1 << 17]byte +var z7447 [1 << 17]byte +var z7448 [1 << 17]byte +var z7449 [1 << 17]byte +var z7450 [1 << 17]byte +var z7451 [1 << 17]byte +var z7452 [1 << 17]byte +var z7453 [1 << 17]byte +var z7454 [1 << 17]byte +var z7455 [1 << 17]byte +var z7456 [1 << 17]byte +var z7457 [1 << 17]byte +var z7458 [1 << 17]byte +var z7459 [1 << 17]byte +var z7460 [1 << 17]byte +var z7461 [1 << 17]byte +var z7462 [1 << 17]byte +var z7463 [1 << 17]byte +var z7464 [1 << 17]byte +var z7465 [1 << 17]byte +var z7466 [1 << 17]byte +var z7467 [1 << 17]byte +var z7468 [1 << 17]byte +var z7469 [1 << 17]byte +var z7470 [1 << 17]byte +var z7471 [1 << 17]byte +var z7472 [1 << 17]byte +var z7473 [1 << 17]byte +var z7474 [1 << 17]byte +var z7475 [1 << 17]byte +var z7476 [1 << 17]byte +var z7477 [1 << 17]byte +var z7478 [1 << 17]byte +var z7479 [1 << 17]byte +var z7480 [1 << 17]byte +var z7481 [1 << 17]byte +var z7482 [1 << 17]byte +var z7483 [1 << 17]byte +var z7484 [1 << 17]byte +var z7485 [1 << 17]byte +var z7486 [1 << 17]byte +var z7487 [1 << 17]byte +var z7488 [1 << 17]byte +var z7489 [1 << 17]byte +var z7490 [1 << 17]byte +var z7491 [1 << 17]byte +var z7492 [1 << 17]byte +var z7493 [1 << 17]byte +var z7494 [1 << 17]byte +var z7495 [1 << 17]byte +var z7496 [1 << 17]byte +var z7497 [1 << 17]byte +var z7498 [1 << 17]byte +var z7499 [1 << 17]byte +var z7500 [1 << 17]byte +var z7501 [1 << 17]byte +var z7502 [1 << 17]byte +var z7503 [1 << 17]byte +var z7504 [1 << 17]byte +var z7505 [1 << 17]byte +var z7506 [1 << 17]byte +var z7507 [1 << 17]byte +var z7508 [1 << 17]byte +var z7509 [1 << 17]byte +var z7510 [1 << 17]byte +var z7511 [1 << 17]byte +var z7512 [1 << 17]byte +var z7513 [1 << 17]byte +var z7514 [1 << 17]byte +var z7515 [1 << 17]byte +var z7516 [1 << 17]byte +var z7517 [1 << 17]byte +var z7518 [1 << 17]byte +var z7519 [1 << 17]byte +var z7520 [1 << 17]byte +var z7521 [1 << 17]byte +var z7522 [1 << 17]byte +var z7523 [1 << 17]byte +var z7524 [1 << 17]byte +var z7525 [1 << 17]byte +var z7526 [1 << 17]byte +var z7527 [1 << 17]byte +var z7528 [1 << 17]byte +var z7529 [1 << 17]byte +var z7530 [1 << 17]byte +var z7531 [1 << 17]byte +var z7532 [1 << 17]byte +var z7533 [1 << 17]byte +var z7534 [1 << 17]byte +var z7535 [1 << 17]byte +var z7536 [1 << 17]byte +var z7537 [1 << 17]byte +var z7538 [1 << 17]byte +var z7539 [1 << 17]byte +var z7540 [1 << 17]byte +var z7541 [1 << 17]byte +var z7542 [1 << 17]byte +var z7543 [1 << 17]byte +var z7544 [1 << 17]byte +var z7545 [1 << 17]byte +var z7546 [1 << 17]byte +var z7547 [1 << 17]byte +var z7548 [1 << 17]byte +var z7549 [1 << 17]byte +var z7550 [1 << 17]byte +var z7551 [1 << 17]byte +var z7552 [1 << 17]byte +var z7553 [1 << 17]byte +var z7554 [1 << 17]byte +var z7555 [1 << 17]byte +var z7556 [1 << 17]byte +var z7557 [1 << 17]byte +var z7558 [1 << 17]byte +var z7559 [1 << 17]byte +var z7560 [1 << 17]byte +var z7561 [1 << 17]byte +var z7562 [1 << 17]byte +var z7563 [1 << 17]byte +var z7564 [1 << 17]byte +var z7565 [1 << 17]byte +var z7566 [1 << 17]byte +var z7567 [1 << 17]byte +var z7568 [1 << 17]byte +var z7569 [1 << 17]byte +var z7570 [1 << 17]byte +var z7571 [1 << 17]byte +var z7572 [1 << 17]byte +var z7573 [1 << 17]byte +var z7574 [1 << 17]byte +var z7575 [1 << 17]byte +var z7576 [1 << 17]byte +var z7577 [1 << 17]byte +var z7578 [1 << 17]byte +var z7579 [1 << 17]byte +var z7580 [1 << 17]byte +var z7581 [1 << 17]byte +var z7582 [1 << 17]byte +var z7583 [1 << 17]byte +var z7584 [1 << 17]byte +var z7585 [1 << 17]byte +var z7586 [1 << 17]byte +var z7587 [1 << 17]byte +var z7588 [1 << 17]byte +var z7589 [1 << 17]byte +var z7590 [1 << 17]byte +var z7591 [1 << 17]byte +var z7592 [1 << 17]byte +var z7593 [1 << 17]byte +var z7594 [1 << 17]byte +var z7595 [1 << 17]byte +var z7596 [1 << 17]byte +var z7597 [1 << 17]byte +var z7598 [1 << 17]byte +var z7599 [1 << 17]byte +var z7600 [1 << 17]byte +var z7601 [1 << 17]byte +var z7602 [1 << 17]byte +var z7603 [1 << 17]byte +var z7604 [1 << 17]byte +var z7605 [1 << 17]byte +var z7606 [1 << 17]byte +var z7607 [1 << 17]byte +var z7608 [1 << 17]byte +var z7609 [1 << 17]byte +var z7610 [1 << 17]byte +var z7611 [1 << 17]byte +var z7612 [1 << 17]byte +var z7613 [1 << 17]byte +var z7614 [1 << 17]byte +var z7615 [1 << 17]byte +var z7616 [1 << 17]byte +var z7617 [1 << 17]byte +var z7618 [1 << 17]byte +var z7619 [1 << 17]byte +var z7620 [1 << 17]byte +var z7621 [1 << 17]byte +var z7622 [1 << 17]byte +var z7623 [1 << 17]byte +var z7624 [1 << 17]byte +var z7625 [1 << 17]byte +var z7626 [1 << 17]byte +var z7627 [1 << 17]byte +var z7628 [1 << 17]byte +var z7629 [1 << 17]byte +var z7630 [1 << 17]byte +var z7631 [1 << 17]byte +var z7632 [1 << 17]byte +var z7633 [1 << 17]byte +var z7634 [1 << 17]byte +var z7635 [1 << 17]byte +var z7636 [1 << 17]byte +var z7637 [1 << 17]byte +var z7638 [1 << 17]byte +var z7639 [1 << 17]byte +var z7640 [1 << 17]byte +var z7641 [1 << 17]byte +var z7642 [1 << 17]byte +var z7643 [1 << 17]byte +var z7644 [1 << 17]byte +var z7645 [1 << 17]byte +var z7646 [1 << 17]byte +var z7647 [1 << 17]byte +var z7648 [1 << 17]byte +var z7649 [1 << 17]byte +var z7650 [1 << 17]byte +var z7651 [1 << 17]byte +var z7652 [1 << 17]byte +var z7653 [1 << 17]byte +var z7654 [1 << 17]byte +var z7655 [1 << 17]byte +var z7656 [1 << 17]byte +var z7657 [1 << 17]byte +var z7658 [1 << 17]byte +var z7659 [1 << 17]byte +var z7660 [1 << 17]byte +var z7661 [1 << 17]byte +var z7662 [1 << 17]byte +var z7663 [1 << 17]byte +var z7664 [1 << 17]byte +var z7665 [1 << 17]byte +var z7666 [1 << 17]byte +var z7667 [1 << 17]byte +var z7668 [1 << 17]byte +var z7669 [1 << 17]byte +var z7670 [1 << 17]byte +var z7671 [1 << 17]byte +var z7672 [1 << 17]byte +var z7673 [1 << 17]byte +var z7674 [1 << 17]byte +var z7675 [1 << 17]byte +var z7676 [1 << 17]byte +var z7677 [1 << 17]byte +var z7678 [1 << 17]byte +var z7679 [1 << 17]byte +var z7680 [1 << 17]byte +var z7681 [1 << 17]byte +var z7682 [1 << 17]byte +var z7683 [1 << 17]byte +var z7684 [1 << 17]byte +var z7685 [1 << 17]byte +var z7686 [1 << 17]byte +var z7687 [1 << 17]byte +var z7688 [1 << 17]byte +var z7689 [1 << 17]byte +var z7690 [1 << 17]byte +var z7691 [1 << 17]byte +var z7692 [1 << 17]byte +var z7693 [1 << 17]byte +var z7694 [1 << 17]byte +var z7695 [1 << 17]byte +var z7696 [1 << 17]byte +var z7697 [1 << 17]byte +var z7698 [1 << 17]byte +var z7699 [1 << 17]byte +var z7700 [1 << 17]byte +var z7701 [1 << 17]byte +var z7702 [1 << 17]byte +var z7703 [1 << 17]byte +var z7704 [1 << 17]byte +var z7705 [1 << 17]byte +var z7706 [1 << 17]byte +var z7707 [1 << 17]byte +var z7708 [1 << 17]byte +var z7709 [1 << 17]byte +var z7710 [1 << 17]byte +var z7711 [1 << 17]byte +var z7712 [1 << 17]byte +var z7713 [1 << 17]byte +var z7714 [1 << 17]byte +var z7715 [1 << 17]byte +var z7716 [1 << 17]byte +var z7717 [1 << 17]byte +var z7718 [1 << 17]byte +var z7719 [1 << 17]byte +var z7720 [1 << 17]byte +var z7721 [1 << 17]byte +var z7722 [1 << 17]byte +var z7723 [1 << 17]byte +var z7724 [1 << 17]byte +var z7725 [1 << 17]byte +var z7726 [1 << 17]byte +var z7727 [1 << 17]byte +var z7728 [1 << 17]byte +var z7729 [1 << 17]byte +var z7730 [1 << 17]byte +var z7731 [1 << 17]byte +var z7732 [1 << 17]byte +var z7733 [1 << 17]byte +var z7734 [1 << 17]byte +var z7735 [1 << 17]byte +var z7736 [1 << 17]byte +var z7737 [1 << 17]byte +var z7738 [1 << 17]byte +var z7739 [1 << 17]byte +var z7740 [1 << 17]byte +var z7741 [1 << 17]byte +var z7742 [1 << 17]byte +var z7743 [1 << 17]byte +var z7744 [1 << 17]byte +var z7745 [1 << 17]byte +var z7746 [1 << 17]byte +var z7747 [1 << 17]byte +var z7748 [1 << 17]byte +var z7749 [1 << 17]byte +var z7750 [1 << 17]byte +var z7751 [1 << 17]byte +var z7752 [1 << 17]byte +var z7753 [1 << 17]byte +var z7754 [1 << 17]byte +var z7755 [1 << 17]byte +var z7756 [1 << 17]byte +var z7757 [1 << 17]byte +var z7758 [1 << 17]byte +var z7759 [1 << 17]byte +var z7760 [1 << 17]byte +var z7761 [1 << 17]byte +var z7762 [1 << 17]byte +var z7763 [1 << 17]byte +var z7764 [1 << 17]byte +var z7765 [1 << 17]byte +var z7766 [1 << 17]byte +var z7767 [1 << 17]byte +var z7768 [1 << 17]byte +var z7769 [1 << 17]byte +var z7770 [1 << 17]byte +var z7771 [1 << 17]byte +var z7772 [1 << 17]byte +var z7773 [1 << 17]byte +var z7774 [1 << 17]byte +var z7775 [1 << 17]byte +var z7776 [1 << 17]byte +var z7777 [1 << 17]byte +var z7778 [1 << 17]byte +var z7779 [1 << 17]byte +var z7780 [1 << 17]byte +var z7781 [1 << 17]byte +var z7782 [1 << 17]byte +var z7783 [1 << 17]byte +var z7784 [1 << 17]byte +var z7785 [1 << 17]byte +var z7786 [1 << 17]byte +var z7787 [1 << 17]byte +var z7788 [1 << 17]byte +var z7789 [1 << 17]byte +var z7790 [1 << 17]byte +var z7791 [1 << 17]byte +var z7792 [1 << 17]byte +var z7793 [1 << 17]byte +var z7794 [1 << 17]byte +var z7795 [1 << 17]byte +var z7796 [1 << 17]byte +var z7797 [1 << 17]byte +var z7798 [1 << 17]byte +var z7799 [1 << 17]byte +var z7800 [1 << 17]byte +var z7801 [1 << 17]byte +var z7802 [1 << 17]byte +var z7803 [1 << 17]byte +var z7804 [1 << 17]byte +var z7805 [1 << 17]byte +var z7806 [1 << 17]byte +var z7807 [1 << 17]byte +var z7808 [1 << 17]byte +var z7809 [1 << 17]byte +var z7810 [1 << 17]byte +var z7811 [1 << 17]byte +var z7812 [1 << 17]byte +var z7813 [1 << 17]byte +var z7814 [1 << 17]byte +var z7815 [1 << 17]byte +var z7816 [1 << 17]byte +var z7817 [1 << 17]byte +var z7818 [1 << 17]byte +var z7819 [1 << 17]byte +var z7820 [1 << 17]byte +var z7821 [1 << 17]byte +var z7822 [1 << 17]byte +var z7823 [1 << 17]byte +var z7824 [1 << 17]byte +var z7825 [1 << 17]byte +var z7826 [1 << 17]byte +var z7827 [1 << 17]byte +var z7828 [1 << 17]byte +var z7829 [1 << 17]byte +var z7830 [1 << 17]byte +var z7831 [1 << 17]byte +var z7832 [1 << 17]byte +var z7833 [1 << 17]byte +var z7834 [1 << 17]byte +var z7835 [1 << 17]byte +var z7836 [1 << 17]byte +var z7837 [1 << 17]byte +var z7838 [1 << 17]byte +var z7839 [1 << 17]byte +var z7840 [1 << 17]byte +var z7841 [1 << 17]byte +var z7842 [1 << 17]byte +var z7843 [1 << 17]byte +var z7844 [1 << 17]byte +var z7845 [1 << 17]byte +var z7846 [1 << 17]byte +var z7847 [1 << 17]byte +var z7848 [1 << 17]byte +var z7849 [1 << 17]byte +var z7850 [1 << 17]byte +var z7851 [1 << 17]byte +var z7852 [1 << 17]byte +var z7853 [1 << 17]byte +var z7854 [1 << 17]byte +var z7855 [1 << 17]byte +var z7856 [1 << 17]byte +var z7857 [1 << 17]byte +var z7858 [1 << 17]byte +var z7859 [1 << 17]byte +var z7860 [1 << 17]byte +var z7861 [1 << 17]byte +var z7862 [1 << 17]byte +var z7863 [1 << 17]byte +var z7864 [1 << 17]byte +var z7865 [1 << 17]byte +var z7866 [1 << 17]byte +var z7867 [1 << 17]byte +var z7868 [1 << 17]byte +var z7869 [1 << 17]byte +var z7870 [1 << 17]byte +var z7871 [1 << 17]byte +var z7872 [1 << 17]byte +var z7873 [1 << 17]byte +var z7874 [1 << 17]byte +var z7875 [1 << 17]byte +var z7876 [1 << 17]byte +var z7877 [1 << 17]byte +var z7878 [1 << 17]byte +var z7879 [1 << 17]byte +var z7880 [1 << 17]byte +var z7881 [1 << 17]byte +var z7882 [1 << 17]byte +var z7883 [1 << 17]byte +var z7884 [1 << 17]byte +var z7885 [1 << 17]byte +var z7886 [1 << 17]byte +var z7887 [1 << 17]byte +var z7888 [1 << 17]byte +var z7889 [1 << 17]byte +var z7890 [1 << 17]byte +var z7891 [1 << 17]byte +var z7892 [1 << 17]byte +var z7893 [1 << 17]byte +var z7894 [1 << 17]byte +var z7895 [1 << 17]byte +var z7896 [1 << 17]byte +var z7897 [1 << 17]byte +var z7898 [1 << 17]byte +var z7899 [1 << 17]byte +var z7900 [1 << 17]byte +var z7901 [1 << 17]byte +var z7902 [1 << 17]byte +var z7903 [1 << 17]byte +var z7904 [1 << 17]byte +var z7905 [1 << 17]byte +var z7906 [1 << 17]byte +var z7907 [1 << 17]byte +var z7908 [1 << 17]byte +var z7909 [1 << 17]byte +var z7910 [1 << 17]byte +var z7911 [1 << 17]byte +var z7912 [1 << 17]byte +var z7913 [1 << 17]byte +var z7914 [1 << 17]byte +var z7915 [1 << 17]byte +var z7916 [1 << 17]byte +var z7917 [1 << 17]byte +var z7918 [1 << 17]byte +var z7919 [1 << 17]byte +var z7920 [1 << 17]byte +var z7921 [1 << 17]byte +var z7922 [1 << 17]byte +var z7923 [1 << 17]byte +var z7924 [1 << 17]byte +var z7925 [1 << 17]byte +var z7926 [1 << 17]byte +var z7927 [1 << 17]byte +var z7928 [1 << 17]byte +var z7929 [1 << 17]byte +var z7930 [1 << 17]byte +var z7931 [1 << 17]byte +var z7932 [1 << 17]byte +var z7933 [1 << 17]byte +var z7934 [1 << 17]byte +var z7935 [1 << 17]byte +var z7936 [1 << 17]byte +var z7937 [1 << 17]byte +var z7938 [1 << 17]byte +var z7939 [1 << 17]byte +var z7940 [1 << 17]byte +var z7941 [1 << 17]byte +var z7942 [1 << 17]byte +var z7943 [1 << 17]byte +var z7944 [1 << 17]byte +var z7945 [1 << 17]byte +var z7946 [1 << 17]byte +var z7947 [1 << 17]byte +var z7948 [1 << 17]byte +var z7949 [1 << 17]byte +var z7950 [1 << 17]byte +var z7951 [1 << 17]byte +var z7952 [1 << 17]byte +var z7953 [1 << 17]byte +var z7954 [1 << 17]byte +var z7955 [1 << 17]byte +var z7956 [1 << 17]byte +var z7957 [1 << 17]byte +var z7958 [1 << 17]byte +var z7959 [1 << 17]byte +var z7960 [1 << 17]byte +var z7961 [1 << 17]byte +var z7962 [1 << 17]byte +var z7963 [1 << 17]byte +var z7964 [1 << 17]byte +var z7965 [1 << 17]byte +var z7966 [1 << 17]byte +var z7967 [1 << 17]byte +var z7968 [1 << 17]byte +var z7969 [1 << 17]byte +var z7970 [1 << 17]byte +var z7971 [1 << 17]byte +var z7972 [1 << 17]byte +var z7973 [1 << 17]byte +var z7974 [1 << 17]byte +var z7975 [1 << 17]byte +var z7976 [1 << 17]byte +var z7977 [1 << 17]byte +var z7978 [1 << 17]byte +var z7979 [1 << 17]byte +var z7980 [1 << 17]byte +var z7981 [1 << 17]byte +var z7982 [1 << 17]byte +var z7983 [1 << 17]byte +var z7984 [1 << 17]byte +var z7985 [1 << 17]byte +var z7986 [1 << 17]byte +var z7987 [1 << 17]byte +var z7988 [1 << 17]byte +var z7989 [1 << 17]byte +var z7990 [1 << 17]byte +var z7991 [1 << 17]byte +var z7992 [1 << 17]byte +var z7993 [1 << 17]byte +var z7994 [1 << 17]byte +var z7995 [1 << 17]byte +var z7996 [1 << 17]byte +var z7997 [1 << 17]byte +var z7998 [1 << 17]byte +var z7999 [1 << 17]byte +var z8000 [1 << 17]byte +var z8001 [1 << 17]byte +var z8002 [1 << 17]byte +var z8003 [1 << 17]byte +var z8004 [1 << 17]byte +var z8005 [1 << 17]byte +var z8006 [1 << 17]byte +var z8007 [1 << 17]byte +var z8008 [1 << 17]byte +var z8009 [1 << 17]byte +var z8010 [1 << 17]byte +var z8011 [1 << 17]byte +var z8012 [1 << 17]byte +var z8013 [1 << 17]byte +var z8014 [1 << 17]byte +var z8015 [1 << 17]byte +var z8016 [1 << 17]byte +var z8017 [1 << 17]byte +var z8018 [1 << 17]byte +var z8019 [1 << 17]byte +var z8020 [1 << 17]byte +var z8021 [1 << 17]byte +var z8022 [1 << 17]byte +var z8023 [1 << 17]byte +var z8024 [1 << 17]byte +var z8025 [1 << 17]byte +var z8026 [1 << 17]byte +var z8027 [1 << 17]byte +var z8028 [1 << 17]byte +var z8029 [1 << 17]byte +var z8030 [1 << 17]byte +var z8031 [1 << 17]byte +var z8032 [1 << 17]byte +var z8033 [1 << 17]byte +var z8034 [1 << 17]byte +var z8035 [1 << 17]byte +var z8036 [1 << 17]byte +var z8037 [1 << 17]byte +var z8038 [1 << 17]byte +var z8039 [1 << 17]byte +var z8040 [1 << 17]byte +var z8041 [1 << 17]byte +var z8042 [1 << 17]byte +var z8043 [1 << 17]byte +var z8044 [1 << 17]byte +var z8045 [1 << 17]byte +var z8046 [1 << 17]byte +var z8047 [1 << 17]byte +var z8048 [1 << 17]byte +var z8049 [1 << 17]byte +var z8050 [1 << 17]byte +var z8051 [1 << 17]byte +var z8052 [1 << 17]byte +var z8053 [1 << 17]byte +var z8054 [1 << 17]byte +var z8055 [1 << 17]byte +var z8056 [1 << 17]byte +var z8057 [1 << 17]byte +var z8058 [1 << 17]byte +var z8059 [1 << 17]byte +var z8060 [1 << 17]byte +var z8061 [1 << 17]byte +var z8062 [1 << 17]byte +var z8063 [1 << 17]byte +var z8064 [1 << 17]byte +var z8065 [1 << 17]byte +var z8066 [1 << 17]byte +var z8067 [1 << 17]byte +var z8068 [1 << 17]byte +var z8069 [1 << 17]byte +var z8070 [1 << 17]byte +var z8071 [1 << 17]byte +var z8072 [1 << 17]byte +var z8073 [1 << 17]byte +var z8074 [1 << 17]byte +var z8075 [1 << 17]byte +var z8076 [1 << 17]byte +var z8077 [1 << 17]byte +var z8078 [1 << 17]byte +var z8079 [1 << 17]byte +var z8080 [1 << 17]byte +var z8081 [1 << 17]byte +var z8082 [1 << 17]byte +var z8083 [1 << 17]byte +var z8084 [1 << 17]byte +var z8085 [1 << 17]byte +var z8086 [1 << 17]byte +var z8087 [1 << 17]byte +var z8088 [1 << 17]byte +var z8089 [1 << 17]byte +var z8090 [1 << 17]byte +var z8091 [1 << 17]byte +var z8092 [1 << 17]byte +var z8093 [1 << 17]byte +var z8094 [1 << 17]byte +var z8095 [1 << 17]byte +var z8096 [1 << 17]byte +var z8097 [1 << 17]byte +var z8098 [1 << 17]byte +var z8099 [1 << 17]byte +var z8100 [1 << 17]byte +var z8101 [1 << 17]byte +var z8102 [1 << 17]byte +var z8103 [1 << 17]byte +var z8104 [1 << 17]byte +var z8105 [1 << 17]byte +var z8106 [1 << 17]byte +var z8107 [1 << 17]byte +var z8108 [1 << 17]byte +var z8109 [1 << 17]byte +var z8110 [1 << 17]byte +var z8111 [1 << 17]byte +var z8112 [1 << 17]byte +var z8113 [1 << 17]byte +var z8114 [1 << 17]byte +var z8115 [1 << 17]byte +var z8116 [1 << 17]byte +var z8117 [1 << 17]byte +var z8118 [1 << 17]byte +var z8119 [1 << 17]byte +var z8120 [1 << 17]byte +var z8121 [1 << 17]byte +var z8122 [1 << 17]byte +var z8123 [1 << 17]byte +var z8124 [1 << 17]byte +var z8125 [1 << 17]byte +var z8126 [1 << 17]byte +var z8127 [1 << 17]byte +var z8128 [1 << 17]byte +var z8129 [1 << 17]byte +var z8130 [1 << 17]byte +var z8131 [1 << 17]byte +var z8132 [1 << 17]byte +var z8133 [1 << 17]byte +var z8134 [1 << 17]byte +var z8135 [1 << 17]byte +var z8136 [1 << 17]byte +var z8137 [1 << 17]byte +var z8138 [1 << 17]byte +var z8139 [1 << 17]byte +var z8140 [1 << 17]byte +var z8141 [1 << 17]byte +var z8142 [1 << 17]byte +var z8143 [1 << 17]byte +var z8144 [1 << 17]byte +var z8145 [1 << 17]byte +var z8146 [1 << 17]byte +var z8147 [1 << 17]byte +var z8148 [1 << 17]byte +var z8149 [1 << 17]byte +var z8150 [1 << 17]byte +var z8151 [1 << 17]byte +var z8152 [1 << 17]byte +var z8153 [1 << 17]byte +var z8154 [1 << 17]byte +var z8155 [1 << 17]byte +var z8156 [1 << 17]byte +var z8157 [1 << 17]byte +var z8158 [1 << 17]byte +var z8159 [1 << 17]byte +var z8160 [1 << 17]byte +var z8161 [1 << 17]byte +var z8162 [1 << 17]byte +var z8163 [1 << 17]byte +var z8164 [1 << 17]byte +var z8165 [1 << 17]byte +var z8166 [1 << 17]byte +var z8167 [1 << 17]byte +var z8168 [1 << 17]byte +var z8169 [1 << 17]byte +var z8170 [1 << 17]byte +var z8171 [1 << 17]byte +var z8172 [1 << 17]byte +var z8173 [1 << 17]byte +var z8174 [1 << 17]byte +var z8175 [1 << 17]byte +var z8176 [1 << 17]byte +var z8177 [1 << 17]byte +var z8178 [1 << 17]byte +var z8179 [1 << 17]byte +var z8180 [1 << 17]byte +var z8181 [1 << 17]byte +var z8182 [1 << 17]byte +var z8183 [1 << 17]byte +var z8184 [1 << 17]byte +var z8185 [1 << 17]byte +var z8186 [1 << 17]byte +var z8187 [1 << 17]byte +var z8188 [1 << 17]byte +var z8189 [1 << 17]byte +var z8190 [1 << 17]byte +var z8191 [1 << 17]byte +var z8192 [1 << 17]byte +var z8193 [1 << 17]byte +var z8194 [1 << 17]byte +var z8195 [1 << 17]byte +var z8196 [1 << 17]byte +var z8197 [1 << 17]byte +var z8198 [1 << 17]byte +var z8199 [1 << 17]byte +var z8200 [1 << 17]byte +var z8201 [1 << 17]byte +var z8202 [1 << 17]byte +var z8203 [1 << 17]byte +var z8204 [1 << 17]byte +var z8205 [1 << 17]byte +var z8206 [1 << 17]byte +var z8207 [1 << 17]byte +var z8208 [1 << 17]byte +var z8209 [1 << 17]byte +var z8210 [1 << 17]byte +var z8211 [1 << 17]byte +var z8212 [1 << 17]byte +var z8213 [1 << 17]byte +var z8214 [1 << 17]byte +var z8215 [1 << 17]byte +var z8216 [1 << 17]byte +var z8217 [1 << 17]byte +var z8218 [1 << 17]byte +var z8219 [1 << 17]byte +var z8220 [1 << 17]byte +var z8221 [1 << 17]byte +var z8222 [1 << 17]byte +var z8223 [1 << 17]byte +var z8224 [1 << 17]byte +var z8225 [1 << 17]byte +var z8226 [1 << 17]byte +var z8227 [1 << 17]byte +var z8228 [1 << 17]byte +var z8229 [1 << 17]byte +var z8230 [1 << 17]byte +var z8231 [1 << 17]byte +var z8232 [1 << 17]byte +var z8233 [1 << 17]byte +var z8234 [1 << 17]byte +var z8235 [1 << 17]byte +var z8236 [1 << 17]byte +var z8237 [1 << 17]byte +var z8238 [1 << 17]byte +var z8239 [1 << 17]byte +var z8240 [1 << 17]byte +var z8241 [1 << 17]byte +var z8242 [1 << 17]byte +var z8243 [1 << 17]byte +var z8244 [1 << 17]byte +var z8245 [1 << 17]byte +var z8246 [1 << 17]byte +var z8247 [1 << 17]byte +var z8248 [1 << 17]byte +var z8249 [1 << 17]byte +var z8250 [1 << 17]byte +var z8251 [1 << 17]byte +var z8252 [1 << 17]byte +var z8253 [1 << 17]byte +var z8254 [1 << 17]byte +var z8255 [1 << 17]byte +var z8256 [1 << 17]byte +var z8257 [1 << 17]byte +var z8258 [1 << 17]byte +var z8259 [1 << 17]byte +var z8260 [1 << 17]byte +var z8261 [1 << 17]byte +var z8262 [1 << 17]byte +var z8263 [1 << 17]byte +var z8264 [1 << 17]byte +var z8265 [1 << 17]byte +var z8266 [1 << 17]byte +var z8267 [1 << 17]byte +var z8268 [1 << 17]byte +var z8269 [1 << 17]byte +var z8270 [1 << 17]byte +var z8271 [1 << 17]byte +var z8272 [1 << 17]byte +var z8273 [1 << 17]byte +var z8274 [1 << 17]byte +var z8275 [1 << 17]byte +var z8276 [1 << 17]byte +var z8277 [1 << 17]byte +var z8278 [1 << 17]byte +var z8279 [1 << 17]byte +var z8280 [1 << 17]byte +var z8281 [1 << 17]byte +var z8282 [1 << 17]byte +var z8283 [1 << 17]byte +var z8284 [1 << 17]byte +var z8285 [1 << 17]byte +var z8286 [1 << 17]byte +var z8287 [1 << 17]byte +var z8288 [1 << 17]byte +var z8289 [1 << 17]byte +var z8290 [1 << 17]byte +var z8291 [1 << 17]byte +var z8292 [1 << 17]byte +var z8293 [1 << 17]byte +var z8294 [1 << 17]byte +var z8295 [1 << 17]byte +var z8296 [1 << 17]byte +var z8297 [1 << 17]byte +var z8298 [1 << 17]byte +var z8299 [1 << 17]byte +var z8300 [1 << 17]byte +var z8301 [1 << 17]byte +var z8302 [1 << 17]byte +var z8303 [1 << 17]byte +var z8304 [1 << 17]byte +var z8305 [1 << 17]byte +var z8306 [1 << 17]byte +var z8307 [1 << 17]byte +var z8308 [1 << 17]byte +var z8309 [1 << 17]byte +var z8310 [1 << 17]byte +var z8311 [1 << 17]byte +var z8312 [1 << 17]byte +var z8313 [1 << 17]byte +var z8314 [1 << 17]byte +var z8315 [1 << 17]byte +var z8316 [1 << 17]byte +var z8317 [1 << 17]byte +var z8318 [1 << 17]byte +var z8319 [1 << 17]byte +var z8320 [1 << 17]byte +var z8321 [1 << 17]byte +var z8322 [1 << 17]byte +var z8323 [1 << 17]byte +var z8324 [1 << 17]byte +var z8325 [1 << 17]byte +var z8326 [1 << 17]byte +var z8327 [1 << 17]byte +var z8328 [1 << 17]byte +var z8329 [1 << 17]byte +var z8330 [1 << 17]byte +var z8331 [1 << 17]byte +var z8332 [1 << 17]byte +var z8333 [1 << 17]byte +var z8334 [1 << 17]byte +var z8335 [1 << 17]byte +var z8336 [1 << 17]byte +var z8337 [1 << 17]byte +var z8338 [1 << 17]byte +var z8339 [1 << 17]byte +var z8340 [1 << 17]byte +var z8341 [1 << 17]byte +var z8342 [1 << 17]byte +var z8343 [1 << 17]byte +var z8344 [1 << 17]byte +var z8345 [1 << 17]byte +var z8346 [1 << 17]byte +var z8347 [1 << 17]byte +var z8348 [1 << 17]byte +var z8349 [1 << 17]byte +var z8350 [1 << 17]byte +var z8351 [1 << 17]byte +var z8352 [1 << 17]byte +var z8353 [1 << 17]byte +var z8354 [1 << 17]byte +var z8355 [1 << 17]byte +var z8356 [1 << 17]byte +var z8357 [1 << 17]byte +var z8358 [1 << 17]byte +var z8359 [1 << 17]byte +var z8360 [1 << 17]byte +var z8361 [1 << 17]byte +var z8362 [1 << 17]byte +var z8363 [1 << 17]byte +var z8364 [1 << 17]byte +var z8365 [1 << 17]byte +var z8366 [1 << 17]byte +var z8367 [1 << 17]byte +var z8368 [1 << 17]byte +var z8369 [1 << 17]byte +var z8370 [1 << 17]byte +var z8371 [1 << 17]byte +var z8372 [1 << 17]byte +var z8373 [1 << 17]byte +var z8374 [1 << 17]byte +var z8375 [1 << 17]byte +var z8376 [1 << 17]byte +var z8377 [1 << 17]byte +var z8378 [1 << 17]byte +var z8379 [1 << 17]byte +var z8380 [1 << 17]byte +var z8381 [1 << 17]byte +var z8382 [1 << 17]byte +var z8383 [1 << 17]byte +var z8384 [1 << 17]byte +var z8385 [1 << 17]byte +var z8386 [1 << 17]byte +var z8387 [1 << 17]byte +var z8388 [1 << 17]byte +var z8389 [1 << 17]byte +var z8390 [1 << 17]byte +var z8391 [1 << 17]byte +var z8392 [1 << 17]byte +var z8393 [1 << 17]byte +var z8394 [1 << 17]byte +var z8395 [1 << 17]byte +var z8396 [1 << 17]byte +var z8397 [1 << 17]byte +var z8398 [1 << 17]byte +var z8399 [1 << 17]byte +var z8400 [1 << 17]byte +var z8401 [1 << 17]byte +var z8402 [1 << 17]byte +var z8403 [1 << 17]byte +var z8404 [1 << 17]byte +var z8405 [1 << 17]byte +var z8406 [1 << 17]byte +var z8407 [1 << 17]byte +var z8408 [1 << 17]byte +var z8409 [1 << 17]byte +var z8410 [1 << 17]byte +var z8411 [1 << 17]byte +var z8412 [1 << 17]byte +var z8413 [1 << 17]byte +var z8414 [1 << 17]byte +var z8415 [1 << 17]byte +var z8416 [1 << 17]byte +var z8417 [1 << 17]byte +var z8418 [1 << 17]byte +var z8419 [1 << 17]byte +var z8420 [1 << 17]byte +var z8421 [1 << 17]byte +var z8422 [1 << 17]byte +var z8423 [1 << 17]byte +var z8424 [1 << 17]byte +var z8425 [1 << 17]byte +var z8426 [1 << 17]byte +var z8427 [1 << 17]byte +var z8428 [1 << 17]byte +var z8429 [1 << 17]byte +var z8430 [1 << 17]byte +var z8431 [1 << 17]byte +var z8432 [1 << 17]byte +var z8433 [1 << 17]byte +var z8434 [1 << 17]byte +var z8435 [1 << 17]byte +var z8436 [1 << 17]byte +var z8437 [1 << 17]byte +var z8438 [1 << 17]byte +var z8439 [1 << 17]byte +var z8440 [1 << 17]byte +var z8441 [1 << 17]byte +var z8442 [1 << 17]byte +var z8443 [1 << 17]byte +var z8444 [1 << 17]byte +var z8445 [1 << 17]byte +var z8446 [1 << 17]byte +var z8447 [1 << 17]byte +var z8448 [1 << 17]byte +var z8449 [1 << 17]byte +var z8450 [1 << 17]byte +var z8451 [1 << 17]byte +var z8452 [1 << 17]byte +var z8453 [1 << 17]byte +var z8454 [1 << 17]byte +var z8455 [1 << 17]byte +var z8456 [1 << 17]byte +var z8457 [1 << 17]byte +var z8458 [1 << 17]byte +var z8459 [1 << 17]byte +var z8460 [1 << 17]byte +var z8461 [1 << 17]byte +var z8462 [1 << 17]byte +var z8463 [1 << 17]byte +var z8464 [1 << 17]byte +var z8465 [1 << 17]byte +var z8466 [1 << 17]byte +var z8467 [1 << 17]byte +var z8468 [1 << 17]byte +var z8469 [1 << 17]byte +var z8470 [1 << 17]byte +var z8471 [1 << 17]byte +var z8472 [1 << 17]byte +var z8473 [1 << 17]byte +var z8474 [1 << 17]byte +var z8475 [1 << 17]byte +var z8476 [1 << 17]byte +var z8477 [1 << 17]byte +var z8478 [1 << 17]byte +var z8479 [1 << 17]byte +var z8480 [1 << 17]byte +var z8481 [1 << 17]byte +var z8482 [1 << 17]byte +var z8483 [1 << 17]byte +var z8484 [1 << 17]byte +var z8485 [1 << 17]byte +var z8486 [1 << 17]byte +var z8487 [1 << 17]byte +var z8488 [1 << 17]byte +var z8489 [1 << 17]byte +var z8490 [1 << 17]byte +var z8491 [1 << 17]byte +var z8492 [1 << 17]byte +var z8493 [1 << 17]byte +var z8494 [1 << 17]byte +var z8495 [1 << 17]byte +var z8496 [1 << 17]byte +var z8497 [1 << 17]byte +var z8498 [1 << 17]byte +var z8499 [1 << 17]byte +var z8500 [1 << 17]byte +var z8501 [1 << 17]byte +var z8502 [1 << 17]byte +var z8503 [1 << 17]byte +var z8504 [1 << 17]byte +var z8505 [1 << 17]byte +var z8506 [1 << 17]byte +var z8507 [1 << 17]byte +var z8508 [1 << 17]byte +var z8509 [1 << 17]byte +var z8510 [1 << 17]byte +var z8511 [1 << 17]byte +var z8512 [1 << 17]byte +var z8513 [1 << 17]byte +var z8514 [1 << 17]byte +var z8515 [1 << 17]byte +var z8516 [1 << 17]byte +var z8517 [1 << 17]byte +var z8518 [1 << 17]byte +var z8519 [1 << 17]byte +var z8520 [1 << 17]byte +var z8521 [1 << 17]byte +var z8522 [1 << 17]byte +var z8523 [1 << 17]byte +var z8524 [1 << 17]byte +var z8525 [1 << 17]byte +var z8526 [1 << 17]byte +var z8527 [1 << 17]byte +var z8528 [1 << 17]byte +var z8529 [1 << 17]byte +var z8530 [1 << 17]byte +var z8531 [1 << 17]byte +var z8532 [1 << 17]byte +var z8533 [1 << 17]byte +var z8534 [1 << 17]byte +var z8535 [1 << 17]byte +var z8536 [1 << 17]byte +var z8537 [1 << 17]byte +var z8538 [1 << 17]byte +var z8539 [1 << 17]byte +var z8540 [1 << 17]byte +var z8541 [1 << 17]byte +var z8542 [1 << 17]byte +var z8543 [1 << 17]byte +var z8544 [1 << 17]byte +var z8545 [1 << 17]byte +var z8546 [1 << 17]byte +var z8547 [1 << 17]byte +var z8548 [1 << 17]byte +var z8549 [1 << 17]byte +var z8550 [1 << 17]byte +var z8551 [1 << 17]byte +var z8552 [1 << 17]byte +var z8553 [1 << 17]byte +var z8554 [1 << 17]byte +var z8555 [1 << 17]byte +var z8556 [1 << 17]byte +var z8557 [1 << 17]byte +var z8558 [1 << 17]byte +var z8559 [1 << 17]byte +var z8560 [1 << 17]byte +var z8561 [1 << 17]byte +var z8562 [1 << 17]byte +var z8563 [1 << 17]byte +var z8564 [1 << 17]byte +var z8565 [1 << 17]byte +var z8566 [1 << 17]byte +var z8567 [1 << 17]byte +var z8568 [1 << 17]byte +var z8569 [1 << 17]byte +var z8570 [1 << 17]byte +var z8571 [1 << 17]byte +var z8572 [1 << 17]byte +var z8573 [1 << 17]byte +var z8574 [1 << 17]byte +var z8575 [1 << 17]byte +var z8576 [1 << 17]byte +var z8577 [1 << 17]byte +var z8578 [1 << 17]byte +var z8579 [1 << 17]byte +var z8580 [1 << 17]byte +var z8581 [1 << 17]byte +var z8582 [1 << 17]byte +var z8583 [1 << 17]byte +var z8584 [1 << 17]byte +var z8585 [1 << 17]byte +var z8586 [1 << 17]byte +var z8587 [1 << 17]byte +var z8588 [1 << 17]byte +var z8589 [1 << 17]byte +var z8590 [1 << 17]byte +var z8591 [1 << 17]byte +var z8592 [1 << 17]byte +var z8593 [1 << 17]byte +var z8594 [1 << 17]byte +var z8595 [1 << 17]byte +var z8596 [1 << 17]byte +var z8597 [1 << 17]byte +var z8598 [1 << 17]byte +var z8599 [1 << 17]byte +var z8600 [1 << 17]byte +var z8601 [1 << 17]byte +var z8602 [1 << 17]byte +var z8603 [1 << 17]byte +var z8604 [1 << 17]byte +var z8605 [1 << 17]byte +var z8606 [1 << 17]byte +var z8607 [1 << 17]byte +var z8608 [1 << 17]byte +var z8609 [1 << 17]byte +var z8610 [1 << 17]byte +var z8611 [1 << 17]byte +var z8612 [1 << 17]byte +var z8613 [1 << 17]byte +var z8614 [1 << 17]byte +var z8615 [1 << 17]byte +var z8616 [1 << 17]byte +var z8617 [1 << 17]byte +var z8618 [1 << 17]byte +var z8619 [1 << 17]byte +var z8620 [1 << 17]byte +var z8621 [1 << 17]byte +var z8622 [1 << 17]byte +var z8623 [1 << 17]byte +var z8624 [1 << 17]byte +var z8625 [1 << 17]byte +var z8626 [1 << 17]byte +var z8627 [1 << 17]byte +var z8628 [1 << 17]byte +var z8629 [1 << 17]byte +var z8630 [1 << 17]byte +var z8631 [1 << 17]byte +var z8632 [1 << 17]byte +var z8633 [1 << 17]byte +var z8634 [1 << 17]byte +var z8635 [1 << 17]byte +var z8636 [1 << 17]byte +var z8637 [1 << 17]byte +var z8638 [1 << 17]byte +var z8639 [1 << 17]byte +var z8640 [1 << 17]byte +var z8641 [1 << 17]byte +var z8642 [1 << 17]byte +var z8643 [1 << 17]byte +var z8644 [1 << 17]byte +var z8645 [1 << 17]byte +var z8646 [1 << 17]byte +var z8647 [1 << 17]byte +var z8648 [1 << 17]byte +var z8649 [1 << 17]byte +var z8650 [1 << 17]byte +var z8651 [1 << 17]byte +var z8652 [1 << 17]byte +var z8653 [1 << 17]byte +var z8654 [1 << 17]byte +var z8655 [1 << 17]byte +var z8656 [1 << 17]byte +var z8657 [1 << 17]byte +var z8658 [1 << 17]byte +var z8659 [1 << 17]byte +var z8660 [1 << 17]byte +var z8661 [1 << 17]byte +var z8662 [1 << 17]byte +var z8663 [1 << 17]byte +var z8664 [1 << 17]byte +var z8665 [1 << 17]byte +var z8666 [1 << 17]byte +var z8667 [1 << 17]byte +var z8668 [1 << 17]byte +var z8669 [1 << 17]byte +var z8670 [1 << 17]byte +var z8671 [1 << 17]byte +var z8672 [1 << 17]byte +var z8673 [1 << 17]byte +var z8674 [1 << 17]byte +var z8675 [1 << 17]byte +var z8676 [1 << 17]byte +var z8677 [1 << 17]byte +var z8678 [1 << 17]byte +var z8679 [1 << 17]byte +var z8680 [1 << 17]byte +var z8681 [1 << 17]byte +var z8682 [1 << 17]byte +var z8683 [1 << 17]byte +var z8684 [1 << 17]byte +var z8685 [1 << 17]byte +var z8686 [1 << 17]byte +var z8687 [1 << 17]byte +var z8688 [1 << 17]byte +var z8689 [1 << 17]byte +var z8690 [1 << 17]byte +var z8691 [1 << 17]byte +var z8692 [1 << 17]byte +var z8693 [1 << 17]byte +var z8694 [1 << 17]byte +var z8695 [1 << 17]byte +var z8696 [1 << 17]byte +var z8697 [1 << 17]byte +var z8698 [1 << 17]byte +var z8699 [1 << 17]byte +var z8700 [1 << 17]byte +var z8701 [1 << 17]byte +var z8702 [1 << 17]byte +var z8703 [1 << 17]byte +var z8704 [1 << 17]byte +var z8705 [1 << 17]byte +var z8706 [1 << 17]byte +var z8707 [1 << 17]byte +var z8708 [1 << 17]byte +var z8709 [1 << 17]byte +var z8710 [1 << 17]byte +var z8711 [1 << 17]byte +var z8712 [1 << 17]byte +var z8713 [1 << 17]byte +var z8714 [1 << 17]byte +var z8715 [1 << 17]byte +var z8716 [1 << 17]byte +var z8717 [1 << 17]byte +var z8718 [1 << 17]byte +var z8719 [1 << 17]byte +var z8720 [1 << 17]byte +var z8721 [1 << 17]byte +var z8722 [1 << 17]byte +var z8723 [1 << 17]byte +var z8724 [1 << 17]byte +var z8725 [1 << 17]byte +var z8726 [1 << 17]byte +var z8727 [1 << 17]byte +var z8728 [1 << 17]byte +var z8729 [1 << 17]byte +var z8730 [1 << 17]byte +var z8731 [1 << 17]byte +var z8732 [1 << 17]byte +var z8733 [1 << 17]byte +var z8734 [1 << 17]byte +var z8735 [1 << 17]byte +var z8736 [1 << 17]byte +var z8737 [1 << 17]byte +var z8738 [1 << 17]byte +var z8739 [1 << 17]byte +var z8740 [1 << 17]byte +var z8741 [1 << 17]byte +var z8742 [1 << 17]byte +var z8743 [1 << 17]byte +var z8744 [1 << 17]byte +var z8745 [1 << 17]byte +var z8746 [1 << 17]byte +var z8747 [1 << 17]byte +var z8748 [1 << 17]byte +var z8749 [1 << 17]byte +var z8750 [1 << 17]byte +var z8751 [1 << 17]byte +var z8752 [1 << 17]byte +var z8753 [1 << 17]byte +var z8754 [1 << 17]byte +var z8755 [1 << 17]byte +var z8756 [1 << 17]byte +var z8757 [1 << 17]byte +var z8758 [1 << 17]byte +var z8759 [1 << 17]byte +var z8760 [1 << 17]byte +var z8761 [1 << 17]byte +var z8762 [1 << 17]byte +var z8763 [1 << 17]byte +var z8764 [1 << 17]byte +var z8765 [1 << 17]byte +var z8766 [1 << 17]byte +var z8767 [1 << 17]byte +var z8768 [1 << 17]byte +var z8769 [1 << 17]byte +var z8770 [1 << 17]byte +var z8771 [1 << 17]byte +var z8772 [1 << 17]byte +var z8773 [1 << 17]byte +var z8774 [1 << 17]byte +var z8775 [1 << 17]byte +var z8776 [1 << 17]byte +var z8777 [1 << 17]byte +var z8778 [1 << 17]byte +var z8779 [1 << 17]byte +var z8780 [1 << 17]byte +var z8781 [1 << 17]byte +var z8782 [1 << 17]byte +var z8783 [1 << 17]byte +var z8784 [1 << 17]byte +var z8785 [1 << 17]byte +var z8786 [1 << 17]byte +var z8787 [1 << 17]byte +var z8788 [1 << 17]byte +var z8789 [1 << 17]byte +var z8790 [1 << 17]byte +var z8791 [1 << 17]byte +var z8792 [1 << 17]byte +var z8793 [1 << 17]byte +var z8794 [1 << 17]byte +var z8795 [1 << 17]byte +var z8796 [1 << 17]byte +var z8797 [1 << 17]byte +var z8798 [1 << 17]byte +var z8799 [1 << 17]byte +var z8800 [1 << 17]byte +var z8801 [1 << 17]byte +var z8802 [1 << 17]byte +var z8803 [1 << 17]byte +var z8804 [1 << 17]byte +var z8805 [1 << 17]byte +var z8806 [1 << 17]byte +var z8807 [1 << 17]byte +var z8808 [1 << 17]byte +var z8809 [1 << 17]byte +var z8810 [1 << 17]byte +var z8811 [1 << 17]byte +var z8812 [1 << 17]byte +var z8813 [1 << 17]byte +var z8814 [1 << 17]byte +var z8815 [1 << 17]byte +var z8816 [1 << 17]byte +var z8817 [1 << 17]byte +var z8818 [1 << 17]byte +var z8819 [1 << 17]byte +var z8820 [1 << 17]byte +var z8821 [1 << 17]byte +var z8822 [1 << 17]byte +var z8823 [1 << 17]byte +var z8824 [1 << 17]byte +var z8825 [1 << 17]byte +var z8826 [1 << 17]byte +var z8827 [1 << 17]byte +var z8828 [1 << 17]byte +var z8829 [1 << 17]byte +var z8830 [1 << 17]byte +var z8831 [1 << 17]byte +var z8832 [1 << 17]byte +var z8833 [1 << 17]byte +var z8834 [1 << 17]byte +var z8835 [1 << 17]byte +var z8836 [1 << 17]byte +var z8837 [1 << 17]byte +var z8838 [1 << 17]byte +var z8839 [1 << 17]byte +var z8840 [1 << 17]byte +var z8841 [1 << 17]byte +var z8842 [1 << 17]byte +var z8843 [1 << 17]byte +var z8844 [1 << 17]byte +var z8845 [1 << 17]byte +var z8846 [1 << 17]byte +var z8847 [1 << 17]byte +var z8848 [1 << 17]byte +var z8849 [1 << 17]byte +var z8850 [1 << 17]byte +var z8851 [1 << 17]byte +var z8852 [1 << 17]byte +var z8853 [1 << 17]byte +var z8854 [1 << 17]byte +var z8855 [1 << 17]byte +var z8856 [1 << 17]byte +var z8857 [1 << 17]byte +var z8858 [1 << 17]byte +var z8859 [1 << 17]byte +var z8860 [1 << 17]byte +var z8861 [1 << 17]byte +var z8862 [1 << 17]byte +var z8863 [1 << 17]byte +var z8864 [1 << 17]byte +var z8865 [1 << 17]byte +var z8866 [1 << 17]byte +var z8867 [1 << 17]byte +var z8868 [1 << 17]byte +var z8869 [1 << 17]byte +var z8870 [1 << 17]byte +var z8871 [1 << 17]byte +var z8872 [1 << 17]byte +var z8873 [1 << 17]byte +var z8874 [1 << 17]byte +var z8875 [1 << 17]byte +var z8876 [1 << 17]byte +var z8877 [1 << 17]byte +var z8878 [1 << 17]byte +var z8879 [1 << 17]byte +var z8880 [1 << 17]byte +var z8881 [1 << 17]byte +var z8882 [1 << 17]byte +var z8883 [1 << 17]byte +var z8884 [1 << 17]byte +var z8885 [1 << 17]byte +var z8886 [1 << 17]byte +var z8887 [1 << 17]byte +var z8888 [1 << 17]byte +var z8889 [1 << 17]byte +var z8890 [1 << 17]byte +var z8891 [1 << 17]byte +var z8892 [1 << 17]byte +var z8893 [1 << 17]byte +var z8894 [1 << 17]byte +var z8895 [1 << 17]byte +var z8896 [1 << 17]byte +var z8897 [1 << 17]byte +var z8898 [1 << 17]byte +var z8899 [1 << 17]byte +var z8900 [1 << 17]byte +var z8901 [1 << 17]byte +var z8902 [1 << 17]byte +var z8903 [1 << 17]byte +var z8904 [1 << 17]byte +var z8905 [1 << 17]byte +var z8906 [1 << 17]byte +var z8907 [1 << 17]byte +var z8908 [1 << 17]byte +var z8909 [1 << 17]byte +var z8910 [1 << 17]byte +var z8911 [1 << 17]byte +var z8912 [1 << 17]byte +var z8913 [1 << 17]byte +var z8914 [1 << 17]byte +var z8915 [1 << 17]byte +var z8916 [1 << 17]byte +var z8917 [1 << 17]byte +var z8918 [1 << 17]byte +var z8919 [1 << 17]byte +var z8920 [1 << 17]byte +var z8921 [1 << 17]byte +var z8922 [1 << 17]byte +var z8923 [1 << 17]byte +var z8924 [1 << 17]byte +var z8925 [1 << 17]byte +var z8926 [1 << 17]byte +var z8927 [1 << 17]byte +var z8928 [1 << 17]byte +var z8929 [1 << 17]byte +var z8930 [1 << 17]byte +var z8931 [1 << 17]byte +var z8932 [1 << 17]byte +var z8933 [1 << 17]byte +var z8934 [1 << 17]byte +var z8935 [1 << 17]byte +var z8936 [1 << 17]byte +var z8937 [1 << 17]byte +var z8938 [1 << 17]byte +var z8939 [1 << 17]byte +var z8940 [1 << 17]byte +var z8941 [1 << 17]byte +var z8942 [1 << 17]byte +var z8943 [1 << 17]byte +var z8944 [1 << 17]byte +var z8945 [1 << 17]byte +var z8946 [1 << 17]byte +var z8947 [1 << 17]byte +var z8948 [1 << 17]byte +var z8949 [1 << 17]byte +var z8950 [1 << 17]byte +var z8951 [1 << 17]byte +var z8952 [1 << 17]byte +var z8953 [1 << 17]byte +var z8954 [1 << 17]byte +var z8955 [1 << 17]byte +var z8956 [1 << 17]byte +var z8957 [1 << 17]byte +var z8958 [1 << 17]byte +var z8959 [1 << 17]byte +var z8960 [1 << 17]byte +var z8961 [1 << 17]byte +var z8962 [1 << 17]byte +var z8963 [1 << 17]byte +var z8964 [1 << 17]byte +var z8965 [1 << 17]byte +var z8966 [1 << 17]byte +var z8967 [1 << 17]byte +var z8968 [1 << 17]byte +var z8969 [1 << 17]byte +var z8970 [1 << 17]byte +var z8971 [1 << 17]byte +var z8972 [1 << 17]byte +var z8973 [1 << 17]byte +var z8974 [1 << 17]byte +var z8975 [1 << 17]byte +var z8976 [1 << 17]byte +var z8977 [1 << 17]byte +var z8978 [1 << 17]byte +var z8979 [1 << 17]byte +var z8980 [1 << 17]byte +var z8981 [1 << 17]byte +var z8982 [1 << 17]byte +var z8983 [1 << 17]byte +var z8984 [1 << 17]byte +var z8985 [1 << 17]byte +var z8986 [1 << 17]byte +var z8987 [1 << 17]byte +var z8988 [1 << 17]byte +var z8989 [1 << 17]byte +var z8990 [1 << 17]byte +var z8991 [1 << 17]byte +var z8992 [1 << 17]byte +var z8993 [1 << 17]byte +var z8994 [1 << 17]byte +var z8995 [1 << 17]byte +var z8996 [1 << 17]byte +var z8997 [1 << 17]byte +var z8998 [1 << 17]byte +var z8999 [1 << 17]byte +var z9000 [1 << 17]byte +var z9001 [1 << 17]byte +var z9002 [1 << 17]byte +var z9003 [1 << 17]byte +var z9004 [1 << 17]byte +var z9005 [1 << 17]byte +var z9006 [1 << 17]byte +var z9007 [1 << 17]byte +var z9008 [1 << 17]byte +var z9009 [1 << 17]byte +var z9010 [1 << 17]byte +var z9011 [1 << 17]byte +var z9012 [1 << 17]byte +var z9013 [1 << 17]byte +var z9014 [1 << 17]byte +var z9015 [1 << 17]byte +var z9016 [1 << 17]byte +var z9017 [1 << 17]byte +var z9018 [1 << 17]byte +var z9019 [1 << 17]byte +var z9020 [1 << 17]byte +var z9021 [1 << 17]byte +var z9022 [1 << 17]byte +var z9023 [1 << 17]byte +var z9024 [1 << 17]byte +var z9025 [1 << 17]byte +var z9026 [1 << 17]byte +var z9027 [1 << 17]byte +var z9028 [1 << 17]byte +var z9029 [1 << 17]byte +var z9030 [1 << 17]byte +var z9031 [1 << 17]byte +var z9032 [1 << 17]byte +var z9033 [1 << 17]byte +var z9034 [1 << 17]byte +var z9035 [1 << 17]byte +var z9036 [1 << 17]byte +var z9037 [1 << 17]byte +var z9038 [1 << 17]byte +var z9039 [1 << 17]byte +var z9040 [1 << 17]byte +var z9041 [1 << 17]byte +var z9042 [1 << 17]byte +var z9043 [1 << 17]byte +var z9044 [1 << 17]byte +var z9045 [1 << 17]byte +var z9046 [1 << 17]byte +var z9047 [1 << 17]byte +var z9048 [1 << 17]byte +var z9049 [1 << 17]byte +var z9050 [1 << 17]byte +var z9051 [1 << 17]byte +var z9052 [1 << 17]byte +var z9053 [1 << 17]byte +var z9054 [1 << 17]byte +var z9055 [1 << 17]byte +var z9056 [1 << 17]byte +var z9057 [1 << 17]byte +var z9058 [1 << 17]byte +var z9059 [1 << 17]byte +var z9060 [1 << 17]byte +var z9061 [1 << 17]byte +var z9062 [1 << 17]byte +var z9063 [1 << 17]byte +var z9064 [1 << 17]byte +var z9065 [1 << 17]byte +var z9066 [1 << 17]byte +var z9067 [1 << 17]byte +var z9068 [1 << 17]byte +var z9069 [1 << 17]byte +var z9070 [1 << 17]byte +var z9071 [1 << 17]byte +var z9072 [1 << 17]byte +var z9073 [1 << 17]byte +var z9074 [1 << 17]byte +var z9075 [1 << 17]byte +var z9076 [1 << 17]byte +var z9077 [1 << 17]byte +var z9078 [1 << 17]byte +var z9079 [1 << 17]byte +var z9080 [1 << 17]byte +var z9081 [1 << 17]byte +var z9082 [1 << 17]byte +var z9083 [1 << 17]byte +var z9084 [1 << 17]byte +var z9085 [1 << 17]byte +var z9086 [1 << 17]byte +var z9087 [1 << 17]byte +var z9088 [1 << 17]byte +var z9089 [1 << 17]byte +var z9090 [1 << 17]byte +var z9091 [1 << 17]byte +var z9092 [1 << 17]byte +var z9093 [1 << 17]byte +var z9094 [1 << 17]byte +var z9095 [1 << 17]byte +var z9096 [1 << 17]byte +var z9097 [1 << 17]byte +var z9098 [1 << 17]byte +var z9099 [1 << 17]byte +var z9100 [1 << 17]byte +var z9101 [1 << 17]byte +var z9102 [1 << 17]byte +var z9103 [1 << 17]byte +var z9104 [1 << 17]byte +var z9105 [1 << 17]byte +var z9106 [1 << 17]byte +var z9107 [1 << 17]byte +var z9108 [1 << 17]byte +var z9109 [1 << 17]byte +var z9110 [1 << 17]byte +var z9111 [1 << 17]byte +var z9112 [1 << 17]byte +var z9113 [1 << 17]byte +var z9114 [1 << 17]byte +var z9115 [1 << 17]byte +var z9116 [1 << 17]byte +var z9117 [1 << 17]byte +var z9118 [1 << 17]byte +var z9119 [1 << 17]byte +var z9120 [1 << 17]byte +var z9121 [1 << 17]byte +var z9122 [1 << 17]byte +var z9123 [1 << 17]byte +var z9124 [1 << 17]byte +var z9125 [1 << 17]byte +var z9126 [1 << 17]byte +var z9127 [1 << 17]byte +var z9128 [1 << 17]byte +var z9129 [1 << 17]byte +var z9130 [1 << 17]byte +var z9131 [1 << 17]byte +var z9132 [1 << 17]byte +var z9133 [1 << 17]byte +var z9134 [1 << 17]byte +var z9135 [1 << 17]byte +var z9136 [1 << 17]byte +var z9137 [1 << 17]byte +var z9138 [1 << 17]byte +var z9139 [1 << 17]byte +var z9140 [1 << 17]byte +var z9141 [1 << 17]byte +var z9142 [1 << 17]byte +var z9143 [1 << 17]byte +var z9144 [1 << 17]byte +var z9145 [1 << 17]byte +var z9146 [1 << 17]byte +var z9147 [1 << 17]byte +var z9148 [1 << 17]byte +var z9149 [1 << 17]byte +var z9150 [1 << 17]byte +var z9151 [1 << 17]byte +var z9152 [1 << 17]byte +var z9153 [1 << 17]byte +var z9154 [1 << 17]byte +var z9155 [1 << 17]byte +var z9156 [1 << 17]byte +var z9157 [1 << 17]byte +var z9158 [1 << 17]byte +var z9159 [1 << 17]byte +var z9160 [1 << 17]byte +var z9161 [1 << 17]byte +var z9162 [1 << 17]byte +var z9163 [1 << 17]byte +var z9164 [1 << 17]byte +var z9165 [1 << 17]byte +var z9166 [1 << 17]byte +var z9167 [1 << 17]byte +var z9168 [1 << 17]byte +var z9169 [1 << 17]byte +var z9170 [1 << 17]byte +var z9171 [1 << 17]byte +var z9172 [1 << 17]byte +var z9173 [1 << 17]byte +var z9174 [1 << 17]byte +var z9175 [1 << 17]byte +var z9176 [1 << 17]byte +var z9177 [1 << 17]byte +var z9178 [1 << 17]byte +var z9179 [1 << 17]byte +var z9180 [1 << 17]byte +var z9181 [1 << 17]byte +var z9182 [1 << 17]byte +var z9183 [1 << 17]byte +var z9184 [1 << 17]byte +var z9185 [1 << 17]byte +var z9186 [1 << 17]byte +var z9187 [1 << 17]byte +var z9188 [1 << 17]byte +var z9189 [1 << 17]byte +var z9190 [1 << 17]byte +var z9191 [1 << 17]byte +var z9192 [1 << 17]byte +var z9193 [1 << 17]byte +var z9194 [1 << 17]byte +var z9195 [1 << 17]byte +var z9196 [1 << 17]byte +var z9197 [1 << 17]byte +var z9198 [1 << 17]byte +var z9199 [1 << 17]byte +var z9200 [1 << 17]byte +var z9201 [1 << 17]byte +var z9202 [1 << 17]byte +var z9203 [1 << 17]byte +var z9204 [1 << 17]byte +var z9205 [1 << 17]byte +var z9206 [1 << 17]byte +var z9207 [1 << 17]byte +var z9208 [1 << 17]byte +var z9209 [1 << 17]byte +var z9210 [1 << 17]byte +var z9211 [1 << 17]byte +var z9212 [1 << 17]byte +var z9213 [1 << 17]byte +var z9214 [1 << 17]byte +var z9215 [1 << 17]byte +var z9216 [1 << 17]byte +var z9217 [1 << 17]byte +var z9218 [1 << 17]byte +var z9219 [1 << 17]byte +var z9220 [1 << 17]byte +var z9221 [1 << 17]byte +var z9222 [1 << 17]byte +var z9223 [1 << 17]byte +var z9224 [1 << 17]byte +var z9225 [1 << 17]byte +var z9226 [1 << 17]byte +var z9227 [1 << 17]byte +var z9228 [1 << 17]byte +var z9229 [1 << 17]byte +var z9230 [1 << 17]byte +var z9231 [1 << 17]byte +var z9232 [1 << 17]byte +var z9233 [1 << 17]byte +var z9234 [1 << 17]byte +var z9235 [1 << 17]byte +var z9236 [1 << 17]byte +var z9237 [1 << 17]byte +var z9238 [1 << 17]byte +var z9239 [1 << 17]byte +var z9240 [1 << 17]byte +var z9241 [1 << 17]byte +var z9242 [1 << 17]byte +var z9243 [1 << 17]byte +var z9244 [1 << 17]byte +var z9245 [1 << 17]byte +var z9246 [1 << 17]byte +var z9247 [1 << 17]byte +var z9248 [1 << 17]byte +var z9249 [1 << 17]byte +var z9250 [1 << 17]byte +var z9251 [1 << 17]byte +var z9252 [1 << 17]byte +var z9253 [1 << 17]byte +var z9254 [1 << 17]byte +var z9255 [1 << 17]byte +var z9256 [1 << 17]byte +var z9257 [1 << 17]byte +var z9258 [1 << 17]byte +var z9259 [1 << 17]byte +var z9260 [1 << 17]byte +var z9261 [1 << 17]byte +var z9262 [1 << 17]byte +var z9263 [1 << 17]byte +var z9264 [1 << 17]byte +var z9265 [1 << 17]byte +var z9266 [1 << 17]byte +var z9267 [1 << 17]byte +var z9268 [1 << 17]byte +var z9269 [1 << 17]byte +var z9270 [1 << 17]byte +var z9271 [1 << 17]byte +var z9272 [1 << 17]byte +var z9273 [1 << 17]byte +var z9274 [1 << 17]byte +var z9275 [1 << 17]byte +var z9276 [1 << 17]byte +var z9277 [1 << 17]byte +var z9278 [1 << 17]byte +var z9279 [1 << 17]byte +var z9280 [1 << 17]byte +var z9281 [1 << 17]byte +var z9282 [1 << 17]byte +var z9283 [1 << 17]byte +var z9284 [1 << 17]byte +var z9285 [1 << 17]byte +var z9286 [1 << 17]byte +var z9287 [1 << 17]byte +var z9288 [1 << 17]byte +var z9289 [1 << 17]byte +var z9290 [1 << 17]byte +var z9291 [1 << 17]byte +var z9292 [1 << 17]byte +var z9293 [1 << 17]byte +var z9294 [1 << 17]byte +var z9295 [1 << 17]byte +var z9296 [1 << 17]byte +var z9297 [1 << 17]byte +var z9298 [1 << 17]byte +var z9299 [1 << 17]byte +var z9300 [1 << 17]byte +var z9301 [1 << 17]byte +var z9302 [1 << 17]byte +var z9303 [1 << 17]byte +var z9304 [1 << 17]byte +var z9305 [1 << 17]byte +var z9306 [1 << 17]byte +var z9307 [1 << 17]byte +var z9308 [1 << 17]byte +var z9309 [1 << 17]byte +var z9310 [1 << 17]byte +var z9311 [1 << 17]byte +var z9312 [1 << 17]byte +var z9313 [1 << 17]byte +var z9314 [1 << 17]byte +var z9315 [1 << 17]byte +var z9316 [1 << 17]byte +var z9317 [1 << 17]byte +var z9318 [1 << 17]byte +var z9319 [1 << 17]byte +var z9320 [1 << 17]byte +var z9321 [1 << 17]byte +var z9322 [1 << 17]byte +var z9323 [1 << 17]byte +var z9324 [1 << 17]byte +var z9325 [1 << 17]byte +var z9326 [1 << 17]byte +var z9327 [1 << 17]byte +var z9328 [1 << 17]byte +var z9329 [1 << 17]byte +var z9330 [1 << 17]byte +var z9331 [1 << 17]byte +var z9332 [1 << 17]byte +var z9333 [1 << 17]byte +var z9334 [1 << 17]byte +var z9335 [1 << 17]byte +var z9336 [1 << 17]byte +var z9337 [1 << 17]byte +var z9338 [1 << 17]byte +var z9339 [1 << 17]byte +var z9340 [1 << 17]byte +var z9341 [1 << 17]byte +var z9342 [1 << 17]byte +var z9343 [1 << 17]byte +var z9344 [1 << 17]byte +var z9345 [1 << 17]byte +var z9346 [1 << 17]byte +var z9347 [1 << 17]byte +var z9348 [1 << 17]byte +var z9349 [1 << 17]byte +var z9350 [1 << 17]byte +var z9351 [1 << 17]byte +var z9352 [1 << 17]byte +var z9353 [1 << 17]byte +var z9354 [1 << 17]byte +var z9355 [1 << 17]byte +var z9356 [1 << 17]byte +var z9357 [1 << 17]byte +var z9358 [1 << 17]byte +var z9359 [1 << 17]byte +var z9360 [1 << 17]byte +var z9361 [1 << 17]byte +var z9362 [1 << 17]byte +var z9363 [1 << 17]byte +var z9364 [1 << 17]byte +var z9365 [1 << 17]byte +var z9366 [1 << 17]byte +var z9367 [1 << 17]byte +var z9368 [1 << 17]byte +var z9369 [1 << 17]byte +var z9370 [1 << 17]byte +var z9371 [1 << 17]byte +var z9372 [1 << 17]byte +var z9373 [1 << 17]byte +var z9374 [1 << 17]byte +var z9375 [1 << 17]byte +var z9376 [1 << 17]byte +var z9377 [1 << 17]byte +var z9378 [1 << 17]byte +var z9379 [1 << 17]byte +var z9380 [1 << 17]byte +var z9381 [1 << 17]byte +var z9382 [1 << 17]byte +var z9383 [1 << 17]byte +var z9384 [1 << 17]byte +var z9385 [1 << 17]byte +var z9386 [1 << 17]byte +var z9387 [1 << 17]byte +var z9388 [1 << 17]byte +var z9389 [1 << 17]byte +var z9390 [1 << 17]byte +var z9391 [1 << 17]byte +var z9392 [1 << 17]byte +var z9393 [1 << 17]byte +var z9394 [1 << 17]byte +var z9395 [1 << 17]byte +var z9396 [1 << 17]byte +var z9397 [1 << 17]byte +var z9398 [1 << 17]byte +var z9399 [1 << 17]byte +var z9400 [1 << 17]byte +var z9401 [1 << 17]byte +var z9402 [1 << 17]byte +var z9403 [1 << 17]byte +var z9404 [1 << 17]byte +var z9405 [1 << 17]byte +var z9406 [1 << 17]byte +var z9407 [1 << 17]byte +var z9408 [1 << 17]byte +var z9409 [1 << 17]byte +var z9410 [1 << 17]byte +var z9411 [1 << 17]byte +var z9412 [1 << 17]byte +var z9413 [1 << 17]byte +var z9414 [1 << 17]byte +var z9415 [1 << 17]byte +var z9416 [1 << 17]byte +var z9417 [1 << 17]byte +var z9418 [1 << 17]byte +var z9419 [1 << 17]byte +var z9420 [1 << 17]byte +var z9421 [1 << 17]byte +var z9422 [1 << 17]byte +var z9423 [1 << 17]byte +var z9424 [1 << 17]byte +var z9425 [1 << 17]byte +var z9426 [1 << 17]byte +var z9427 [1 << 17]byte +var z9428 [1 << 17]byte +var z9429 [1 << 17]byte +var z9430 [1 << 17]byte +var z9431 [1 << 17]byte +var z9432 [1 << 17]byte +var z9433 [1 << 17]byte +var z9434 [1 << 17]byte +var z9435 [1 << 17]byte +var z9436 [1 << 17]byte +var z9437 [1 << 17]byte +var z9438 [1 << 17]byte +var z9439 [1 << 17]byte +var z9440 [1 << 17]byte +var z9441 [1 << 17]byte +var z9442 [1 << 17]byte +var z9443 [1 << 17]byte +var z9444 [1 << 17]byte +var z9445 [1 << 17]byte +var z9446 [1 << 17]byte +var z9447 [1 << 17]byte +var z9448 [1 << 17]byte +var z9449 [1 << 17]byte +var z9450 [1 << 17]byte +var z9451 [1 << 17]byte +var z9452 [1 << 17]byte +var z9453 [1 << 17]byte +var z9454 [1 << 17]byte +var z9455 [1 << 17]byte +var z9456 [1 << 17]byte +var z9457 [1 << 17]byte +var z9458 [1 << 17]byte +var z9459 [1 << 17]byte +var z9460 [1 << 17]byte +var z9461 [1 << 17]byte +var z9462 [1 << 17]byte +var z9463 [1 << 17]byte +var z9464 [1 << 17]byte +var z9465 [1 << 17]byte +var z9466 [1 << 17]byte +var z9467 [1 << 17]byte +var z9468 [1 << 17]byte +var z9469 [1 << 17]byte +var z9470 [1 << 17]byte +var z9471 [1 << 17]byte +var z9472 [1 << 17]byte +var z9473 [1 << 17]byte +var z9474 [1 << 17]byte +var z9475 [1 << 17]byte +var z9476 [1 << 17]byte +var z9477 [1 << 17]byte +var z9478 [1 << 17]byte +var z9479 [1 << 17]byte +var z9480 [1 << 17]byte +var z9481 [1 << 17]byte +var z9482 [1 << 17]byte +var z9483 [1 << 17]byte +var z9484 [1 << 17]byte +var z9485 [1 << 17]byte +var z9486 [1 << 17]byte +var z9487 [1 << 17]byte +var z9488 [1 << 17]byte +var z9489 [1 << 17]byte +var z9490 [1 << 17]byte +var z9491 [1 << 17]byte +var z9492 [1 << 17]byte +var z9493 [1 << 17]byte +var z9494 [1 << 17]byte +var z9495 [1 << 17]byte +var z9496 [1 << 17]byte +var z9497 [1 << 17]byte +var z9498 [1 << 17]byte +var z9499 [1 << 17]byte +var z9500 [1 << 17]byte +var z9501 [1 << 17]byte +var z9502 [1 << 17]byte +var z9503 [1 << 17]byte +var z9504 [1 << 17]byte +var z9505 [1 << 17]byte +var z9506 [1 << 17]byte +var z9507 [1 << 17]byte +var z9508 [1 << 17]byte +var z9509 [1 << 17]byte +var z9510 [1 << 17]byte +var z9511 [1 << 17]byte +var z9512 [1 << 17]byte +var z9513 [1 << 17]byte +var z9514 [1 << 17]byte +var z9515 [1 << 17]byte +var z9516 [1 << 17]byte +var z9517 [1 << 17]byte +var z9518 [1 << 17]byte +var z9519 [1 << 17]byte +var z9520 [1 << 17]byte +var z9521 [1 << 17]byte +var z9522 [1 << 17]byte +var z9523 [1 << 17]byte +var z9524 [1 << 17]byte +var z9525 [1 << 17]byte +var z9526 [1 << 17]byte +var z9527 [1 << 17]byte +var z9528 [1 << 17]byte +var z9529 [1 << 17]byte +var z9530 [1 << 17]byte +var z9531 [1 << 17]byte +var z9532 [1 << 17]byte +var z9533 [1 << 17]byte +var z9534 [1 << 17]byte +var z9535 [1 << 17]byte +var z9536 [1 << 17]byte +var z9537 [1 << 17]byte +var z9538 [1 << 17]byte +var z9539 [1 << 17]byte +var z9540 [1 << 17]byte +var z9541 [1 << 17]byte +var z9542 [1 << 17]byte +var z9543 [1 << 17]byte +var z9544 [1 << 17]byte +var z9545 [1 << 17]byte +var z9546 [1 << 17]byte +var z9547 [1 << 17]byte +var z9548 [1 << 17]byte +var z9549 [1 << 17]byte +var z9550 [1 << 17]byte +var z9551 [1 << 17]byte +var z9552 [1 << 17]byte +var z9553 [1 << 17]byte +var z9554 [1 << 17]byte +var z9555 [1 << 17]byte +var z9556 [1 << 17]byte +var z9557 [1 << 17]byte +var z9558 [1 << 17]byte +var z9559 [1 << 17]byte +var z9560 [1 << 17]byte +var z9561 [1 << 17]byte +var z9562 [1 << 17]byte +var z9563 [1 << 17]byte +var z9564 [1 << 17]byte +var z9565 [1 << 17]byte +var z9566 [1 << 17]byte +var z9567 [1 << 17]byte +var z9568 [1 << 17]byte +var z9569 [1 << 17]byte +var z9570 [1 << 17]byte +var z9571 [1 << 17]byte +var z9572 [1 << 17]byte +var z9573 [1 << 17]byte +var z9574 [1 << 17]byte +var z9575 [1 << 17]byte +var z9576 [1 << 17]byte +var z9577 [1 << 17]byte +var z9578 [1 << 17]byte +var z9579 [1 << 17]byte +var z9580 [1 << 17]byte +var z9581 [1 << 17]byte +var z9582 [1 << 17]byte +var z9583 [1 << 17]byte +var z9584 [1 << 17]byte +var z9585 [1 << 17]byte +var z9586 [1 << 17]byte +var z9587 [1 << 17]byte +var z9588 [1 << 17]byte +var z9589 [1 << 17]byte +var z9590 [1 << 17]byte +var z9591 [1 << 17]byte +var z9592 [1 << 17]byte +var z9593 [1 << 17]byte +var z9594 [1 << 17]byte +var z9595 [1 << 17]byte +var z9596 [1 << 17]byte +var z9597 [1 << 17]byte +var z9598 [1 << 17]byte +var z9599 [1 << 17]byte +var z9600 [1 << 17]byte +var z9601 [1 << 17]byte +var z9602 [1 << 17]byte +var z9603 [1 << 17]byte +var z9604 [1 << 17]byte +var z9605 [1 << 17]byte +var z9606 [1 << 17]byte +var z9607 [1 << 17]byte +var z9608 [1 << 17]byte +var z9609 [1 << 17]byte +var z9610 [1 << 17]byte +var z9611 [1 << 17]byte +var z9612 [1 << 17]byte +var z9613 [1 << 17]byte +var z9614 [1 << 17]byte +var z9615 [1 << 17]byte +var z9616 [1 << 17]byte +var z9617 [1 << 17]byte +var z9618 [1 << 17]byte +var z9619 [1 << 17]byte +var z9620 [1 << 17]byte +var z9621 [1 << 17]byte +var z9622 [1 << 17]byte +var z9623 [1 << 17]byte +var z9624 [1 << 17]byte +var z9625 [1 << 17]byte +var z9626 [1 << 17]byte +var z9627 [1 << 17]byte +var z9628 [1 << 17]byte +var z9629 [1 << 17]byte +var z9630 [1 << 17]byte +var z9631 [1 << 17]byte +var z9632 [1 << 17]byte +var z9633 [1 << 17]byte +var z9634 [1 << 17]byte +var z9635 [1 << 17]byte +var z9636 [1 << 17]byte +var z9637 [1 << 17]byte +var z9638 [1 << 17]byte +var z9639 [1 << 17]byte +var z9640 [1 << 17]byte +var z9641 [1 << 17]byte +var z9642 [1 << 17]byte +var z9643 [1 << 17]byte +var z9644 [1 << 17]byte +var z9645 [1 << 17]byte +var z9646 [1 << 17]byte +var z9647 [1 << 17]byte +var z9648 [1 << 17]byte +var z9649 [1 << 17]byte +var z9650 [1 << 17]byte +var z9651 [1 << 17]byte +var z9652 [1 << 17]byte +var z9653 [1 << 17]byte +var z9654 [1 << 17]byte +var z9655 [1 << 17]byte +var z9656 [1 << 17]byte +var z9657 [1 << 17]byte +var z9658 [1 << 17]byte +var z9659 [1 << 17]byte +var z9660 [1 << 17]byte +var z9661 [1 << 17]byte +var z9662 [1 << 17]byte +var z9663 [1 << 17]byte +var z9664 [1 << 17]byte +var z9665 [1 << 17]byte +var z9666 [1 << 17]byte +var z9667 [1 << 17]byte +var z9668 [1 << 17]byte +var z9669 [1 << 17]byte +var z9670 [1 << 17]byte +var z9671 [1 << 17]byte +var z9672 [1 << 17]byte +var z9673 [1 << 17]byte +var z9674 [1 << 17]byte +var z9675 [1 << 17]byte +var z9676 [1 << 17]byte +var z9677 [1 << 17]byte +var z9678 [1 << 17]byte +var z9679 [1 << 17]byte +var z9680 [1 << 17]byte +var z9681 [1 << 17]byte +var z9682 [1 << 17]byte +var z9683 [1 << 17]byte +var z9684 [1 << 17]byte +var z9685 [1 << 17]byte +var z9686 [1 << 17]byte +var z9687 [1 << 17]byte +var z9688 [1 << 17]byte +var z9689 [1 << 17]byte +var z9690 [1 << 17]byte +var z9691 [1 << 17]byte +var z9692 [1 << 17]byte +var z9693 [1 << 17]byte +var z9694 [1 << 17]byte +var z9695 [1 << 17]byte +var z9696 [1 << 17]byte +var z9697 [1 << 17]byte +var z9698 [1 << 17]byte +var z9699 [1 << 17]byte +var z9700 [1 << 17]byte +var z9701 [1 << 17]byte +var z9702 [1 << 17]byte +var z9703 [1 << 17]byte +var z9704 [1 << 17]byte +var z9705 [1 << 17]byte +var z9706 [1 << 17]byte +var z9707 [1 << 17]byte +var z9708 [1 << 17]byte +var z9709 [1 << 17]byte +var z9710 [1 << 17]byte +var z9711 [1 << 17]byte +var z9712 [1 << 17]byte +var z9713 [1 << 17]byte +var z9714 [1 << 17]byte +var z9715 [1 << 17]byte +var z9716 [1 << 17]byte +var z9717 [1 << 17]byte +var z9718 [1 << 17]byte +var z9719 [1 << 17]byte +var z9720 [1 << 17]byte +var z9721 [1 << 17]byte +var z9722 [1 << 17]byte +var z9723 [1 << 17]byte +var z9724 [1 << 17]byte +var z9725 [1 << 17]byte +var z9726 [1 << 17]byte +var z9727 [1 << 17]byte +var z9728 [1 << 17]byte +var z9729 [1 << 17]byte +var z9730 [1 << 17]byte +var z9731 [1 << 17]byte +var z9732 [1 << 17]byte +var z9733 [1 << 17]byte +var z9734 [1 << 17]byte +var z9735 [1 << 17]byte +var z9736 [1 << 17]byte +var z9737 [1 << 17]byte +var z9738 [1 << 17]byte +var z9739 [1 << 17]byte +var z9740 [1 << 17]byte +var z9741 [1 << 17]byte +var z9742 [1 << 17]byte +var z9743 [1 << 17]byte +var z9744 [1 << 17]byte +var z9745 [1 << 17]byte +var z9746 [1 << 17]byte +var z9747 [1 << 17]byte +var z9748 [1 << 17]byte +var z9749 [1 << 17]byte +var z9750 [1 << 17]byte +var z9751 [1 << 17]byte +var z9752 [1 << 17]byte +var z9753 [1 << 17]byte +var z9754 [1 << 17]byte +var z9755 [1 << 17]byte +var z9756 [1 << 17]byte +var z9757 [1 << 17]byte +var z9758 [1 << 17]byte +var z9759 [1 << 17]byte +var z9760 [1 << 17]byte +var z9761 [1 << 17]byte +var z9762 [1 << 17]byte +var z9763 [1 << 17]byte +var z9764 [1 << 17]byte +var z9765 [1 << 17]byte +var z9766 [1 << 17]byte +var z9767 [1 << 17]byte +var z9768 [1 << 17]byte +var z9769 [1 << 17]byte +var z9770 [1 << 17]byte +var z9771 [1 << 17]byte +var z9772 [1 << 17]byte +var z9773 [1 << 17]byte +var z9774 [1 << 17]byte +var z9775 [1 << 17]byte +var z9776 [1 << 17]byte +var z9777 [1 << 17]byte +var z9778 [1 << 17]byte +var z9779 [1 << 17]byte +var z9780 [1 << 17]byte +var z9781 [1 << 17]byte +var z9782 [1 << 17]byte +var z9783 [1 << 17]byte +var z9784 [1 << 17]byte +var z9785 [1 << 17]byte +var z9786 [1 << 17]byte +var z9787 [1 << 17]byte +var z9788 [1 << 17]byte +var z9789 [1 << 17]byte +var z9790 [1 << 17]byte +var z9791 [1 << 17]byte +var z9792 [1 << 17]byte +var z9793 [1 << 17]byte +var z9794 [1 << 17]byte +var z9795 [1 << 17]byte +var z9796 [1 << 17]byte +var z9797 [1 << 17]byte +var z9798 [1 << 17]byte +var z9799 [1 << 17]byte +var z9800 [1 << 17]byte +var z9801 [1 << 17]byte +var z9802 [1 << 17]byte +var z9803 [1 << 17]byte +var z9804 [1 << 17]byte +var z9805 [1 << 17]byte +var z9806 [1 << 17]byte +var z9807 [1 << 17]byte +var z9808 [1 << 17]byte +var z9809 [1 << 17]byte +var z9810 [1 << 17]byte +var z9811 [1 << 17]byte +var z9812 [1 << 17]byte +var z9813 [1 << 17]byte +var z9814 [1 << 17]byte +var z9815 [1 << 17]byte +var z9816 [1 << 17]byte +var z9817 [1 << 17]byte +var z9818 [1 << 17]byte +var z9819 [1 << 17]byte +var z9820 [1 << 17]byte +var z9821 [1 << 17]byte +var z9822 [1 << 17]byte +var z9823 [1 << 17]byte +var z9824 [1 << 17]byte +var z9825 [1 << 17]byte +var z9826 [1 << 17]byte +var z9827 [1 << 17]byte +var z9828 [1 << 17]byte +var z9829 [1 << 17]byte +var z9830 [1 << 17]byte +var z9831 [1 << 17]byte +var z9832 [1 << 17]byte +var z9833 [1 << 17]byte +var z9834 [1 << 17]byte +var z9835 [1 << 17]byte +var z9836 [1 << 17]byte +var z9837 [1 << 17]byte +var z9838 [1 << 17]byte +var z9839 [1 << 17]byte +var z9840 [1 << 17]byte +var z9841 [1 << 17]byte +var z9842 [1 << 17]byte +var z9843 [1 << 17]byte +var z9844 [1 << 17]byte +var z9845 [1 << 17]byte +var z9846 [1 << 17]byte +var z9847 [1 << 17]byte +var z9848 [1 << 17]byte +var z9849 [1 << 17]byte +var z9850 [1 << 17]byte +var z9851 [1 << 17]byte +var z9852 [1 << 17]byte +var z9853 [1 << 17]byte +var z9854 [1 << 17]byte +var z9855 [1 << 17]byte +var z9856 [1 << 17]byte +var z9857 [1 << 17]byte +var z9858 [1 << 17]byte +var z9859 [1 << 17]byte +var z9860 [1 << 17]byte +var z9861 [1 << 17]byte +var z9862 [1 << 17]byte +var z9863 [1 << 17]byte +var z9864 [1 << 17]byte +var z9865 [1 << 17]byte +var z9866 [1 << 17]byte +var z9867 [1 << 17]byte +var z9868 [1 << 17]byte +var z9869 [1 << 17]byte +var z9870 [1 << 17]byte +var z9871 [1 << 17]byte +var z9872 [1 << 17]byte +var z9873 [1 << 17]byte +var z9874 [1 << 17]byte +var z9875 [1 << 17]byte +var z9876 [1 << 17]byte +var z9877 [1 << 17]byte +var z9878 [1 << 17]byte +var z9879 [1 << 17]byte +var z9880 [1 << 17]byte +var z9881 [1 << 17]byte +var z9882 [1 << 17]byte +var z9883 [1 << 17]byte +var z9884 [1 << 17]byte +var z9885 [1 << 17]byte +var z9886 [1 << 17]byte +var z9887 [1 << 17]byte +var z9888 [1 << 17]byte +var z9889 [1 << 17]byte +var z9890 [1 << 17]byte +var z9891 [1 << 17]byte +var z9892 [1 << 17]byte +var z9893 [1 << 17]byte +var z9894 [1 << 17]byte +var z9895 [1 << 17]byte +var z9896 [1 << 17]byte +var z9897 [1 << 17]byte +var z9898 [1 << 17]byte +var z9899 [1 << 17]byte +var z9900 [1 << 17]byte +var z9901 [1 << 17]byte +var z9902 [1 << 17]byte +var z9903 [1 << 17]byte +var z9904 [1 << 17]byte +var z9905 [1 << 17]byte +var z9906 [1 << 17]byte +var z9907 [1 << 17]byte +var z9908 [1 << 17]byte +var z9909 [1 << 17]byte +var z9910 [1 << 17]byte +var z9911 [1 << 17]byte +var z9912 [1 << 17]byte +var z9913 [1 << 17]byte +var z9914 [1 << 17]byte +var z9915 [1 << 17]byte +var z9916 [1 << 17]byte +var z9917 [1 << 17]byte +var z9918 [1 << 17]byte +var z9919 [1 << 17]byte +var z9920 [1 << 17]byte +var z9921 [1 << 17]byte +var z9922 [1 << 17]byte +var z9923 [1 << 17]byte +var z9924 [1 << 17]byte +var z9925 [1 << 17]byte +var z9926 [1 << 17]byte +var z9927 [1 << 17]byte +var z9928 [1 << 17]byte +var z9929 [1 << 17]byte +var z9930 [1 << 17]byte +var z9931 [1 << 17]byte +var z9932 [1 << 17]byte +var z9933 [1 << 17]byte +var z9934 [1 << 17]byte +var z9935 [1 << 17]byte +var z9936 [1 << 17]byte +var z9937 [1 << 17]byte +var z9938 [1 << 17]byte +var z9939 [1 << 17]byte +var z9940 [1 << 17]byte +var z9941 [1 << 17]byte +var z9942 [1 << 17]byte +var z9943 [1 << 17]byte +var z9944 [1 << 17]byte +var z9945 [1 << 17]byte +var z9946 [1 << 17]byte +var z9947 [1 << 17]byte +var z9948 [1 << 17]byte +var z9949 [1 << 17]byte +var z9950 [1 << 17]byte +var z9951 [1 << 17]byte +var z9952 [1 << 17]byte +var z9953 [1 << 17]byte +var z9954 [1 << 17]byte +var z9955 [1 << 17]byte +var z9956 [1 << 17]byte +var z9957 [1 << 17]byte +var z9958 [1 << 17]byte +var z9959 [1 << 17]byte +var z9960 [1 << 17]byte +var z9961 [1 << 17]byte +var z9962 [1 << 17]byte +var z9963 [1 << 17]byte +var z9964 [1 << 17]byte +var z9965 [1 << 17]byte +var z9966 [1 << 17]byte +var z9967 [1 << 17]byte +var z9968 [1 << 17]byte +var z9969 [1 << 17]byte +var z9970 [1 << 17]byte +var z9971 [1 << 17]byte +var z9972 [1 << 17]byte +var z9973 [1 << 17]byte +var z9974 [1 << 17]byte +var z9975 [1 << 17]byte +var z9976 [1 << 17]byte +var z9977 [1 << 17]byte +var z9978 [1 << 17]byte +var z9979 [1 << 17]byte +var z9980 [1 << 17]byte +var z9981 [1 << 17]byte +var z9982 [1 << 17]byte +var z9983 [1 << 17]byte +var z9984 [1 << 17]byte +var z9985 [1 << 17]byte +var z9986 [1 << 17]byte +var z9987 [1 << 17]byte +var z9988 [1 << 17]byte +var z9989 [1 << 17]byte +var z9990 [1 << 17]byte +var z9991 [1 << 17]byte +var z9992 [1 << 17]byte +var z9993 [1 << 17]byte +var z9994 [1 << 17]byte +var z9995 [1 << 17]byte +var z9996 [1 << 17]byte +var z9997 [1 << 17]byte +var z9998 [1 << 17]byte +var z9999 [1 << 17]byte +var z10000 [1 << 17]byte +var z10001 [1 << 17]byte +var z10002 [1 << 17]byte +var z10003 [1 << 17]byte +var z10004 [1 << 17]byte +var z10005 [1 << 17]byte +var z10006 [1 << 17]byte +var z10007 [1 << 17]byte +var z10008 [1 << 17]byte +var z10009 [1 << 17]byte +var z10010 [1 << 17]byte +var z10011 [1 << 17]byte +var z10012 [1 << 17]byte +var z10013 [1 << 17]byte +var z10014 [1 << 17]byte +var z10015 [1 << 17]byte +var z10016 [1 << 17]byte +var z10017 [1 << 17]byte +var z10018 [1 << 17]byte +var z10019 [1 << 17]byte +var z10020 [1 << 17]byte +var z10021 [1 << 17]byte +var z10022 [1 << 17]byte +var z10023 [1 << 17]byte +var z10024 [1 << 17]byte +var z10025 [1 << 17]byte +var z10026 [1 << 17]byte +var z10027 [1 << 17]byte +var z10028 [1 << 17]byte +var z10029 [1 << 17]byte +var z10030 [1 << 17]byte +var z10031 [1 << 17]byte +var z10032 [1 << 17]byte +var z10033 [1 << 17]byte +var z10034 [1 << 17]byte +var z10035 [1 << 17]byte +var z10036 [1 << 17]byte +var z10037 [1 << 17]byte +var z10038 [1 << 17]byte +var z10039 [1 << 17]byte +var z10040 [1 << 17]byte +var z10041 [1 << 17]byte +var z10042 [1 << 17]byte +var z10043 [1 << 17]byte +var z10044 [1 << 17]byte +var z10045 [1 << 17]byte +var z10046 [1 << 17]byte +var z10047 [1 << 17]byte +var z10048 [1 << 17]byte +var z10049 [1 << 17]byte +var z10050 [1 << 17]byte +var z10051 [1 << 17]byte +var z10052 [1 << 17]byte +var z10053 [1 << 17]byte +var z10054 [1 << 17]byte +var z10055 [1 << 17]byte +var z10056 [1 << 17]byte +var z10057 [1 << 17]byte +var z10058 [1 << 17]byte +var z10059 [1 << 17]byte +var z10060 [1 << 17]byte +var z10061 [1 << 17]byte +var z10062 [1 << 17]byte +var z10063 [1 << 17]byte +var z10064 [1 << 17]byte +var z10065 [1 << 17]byte +var z10066 [1 << 17]byte +var z10067 [1 << 17]byte +var z10068 [1 << 17]byte +var z10069 [1 << 17]byte +var z10070 [1 << 17]byte +var z10071 [1 << 17]byte +var z10072 [1 << 17]byte +var z10073 [1 << 17]byte +var z10074 [1 << 17]byte +var z10075 [1 << 17]byte +var z10076 [1 << 17]byte +var z10077 [1 << 17]byte +var z10078 [1 << 17]byte +var z10079 [1 << 17]byte +var z10080 [1 << 17]byte +var z10081 [1 << 17]byte +var z10082 [1 << 17]byte +var z10083 [1 << 17]byte +var z10084 [1 << 17]byte +var z10085 [1 << 17]byte +var z10086 [1 << 17]byte +var z10087 [1 << 17]byte +var z10088 [1 << 17]byte +var z10089 [1 << 17]byte +var z10090 [1 << 17]byte +var z10091 [1 << 17]byte +var z10092 [1 << 17]byte +var z10093 [1 << 17]byte +var z10094 [1 << 17]byte +var z10095 [1 << 17]byte +var z10096 [1 << 17]byte +var z10097 [1 << 17]byte +var z10098 [1 << 17]byte +var z10099 [1 << 17]byte +var z10100 [1 << 17]byte +var z10101 [1 << 17]byte +var z10102 [1 << 17]byte +var z10103 [1 << 17]byte +var z10104 [1 << 17]byte +var z10105 [1 << 17]byte +var z10106 [1 << 17]byte +var z10107 [1 << 17]byte +var z10108 [1 << 17]byte +var z10109 [1 << 17]byte +var z10110 [1 << 17]byte +var z10111 [1 << 17]byte +var z10112 [1 << 17]byte +var z10113 [1 << 17]byte +var z10114 [1 << 17]byte +var z10115 [1 << 17]byte +var z10116 [1 << 17]byte +var z10117 [1 << 17]byte +var z10118 [1 << 17]byte +var z10119 [1 << 17]byte +var z10120 [1 << 17]byte +var z10121 [1 << 17]byte +var z10122 [1 << 17]byte +var z10123 [1 << 17]byte +var z10124 [1 << 17]byte +var z10125 [1 << 17]byte +var z10126 [1 << 17]byte +var z10127 [1 << 17]byte +var z10128 [1 << 17]byte +var z10129 [1 << 17]byte +var z10130 [1 << 17]byte +var z10131 [1 << 17]byte +var z10132 [1 << 17]byte +var z10133 [1 << 17]byte +var z10134 [1 << 17]byte +var z10135 [1 << 17]byte +var z10136 [1 << 17]byte +var z10137 [1 << 17]byte +var z10138 [1 << 17]byte +var z10139 [1 << 17]byte +var z10140 [1 << 17]byte +var z10141 [1 << 17]byte +var z10142 [1 << 17]byte +var z10143 [1 << 17]byte +var z10144 [1 << 17]byte +var z10145 [1 << 17]byte +var z10146 [1 << 17]byte +var z10147 [1 << 17]byte +var z10148 [1 << 17]byte +var z10149 [1 << 17]byte +var z10150 [1 << 17]byte +var z10151 [1 << 17]byte +var z10152 [1 << 17]byte +var z10153 [1 << 17]byte +var z10154 [1 << 17]byte +var z10155 [1 << 17]byte +var z10156 [1 << 17]byte +var z10157 [1 << 17]byte +var z10158 [1 << 17]byte +var z10159 [1 << 17]byte +var z10160 [1 << 17]byte +var z10161 [1 << 17]byte +var z10162 [1 << 17]byte +var z10163 [1 << 17]byte +var z10164 [1 << 17]byte +var z10165 [1 << 17]byte +var z10166 [1 << 17]byte +var z10167 [1 << 17]byte +var z10168 [1 << 17]byte +var z10169 [1 << 17]byte +var z10170 [1 << 17]byte +var z10171 [1 << 17]byte +var z10172 [1 << 17]byte +var z10173 [1 << 17]byte +var z10174 [1 << 17]byte +var z10175 [1 << 17]byte +var z10176 [1 << 17]byte +var z10177 [1 << 17]byte +var z10178 [1 << 17]byte +var z10179 [1 << 17]byte +var z10180 [1 << 17]byte +var z10181 [1 << 17]byte +var z10182 [1 << 17]byte +var z10183 [1 << 17]byte +var z10184 [1 << 17]byte +var z10185 [1 << 17]byte +var z10186 [1 << 17]byte +var z10187 [1 << 17]byte +var z10188 [1 << 17]byte +var z10189 [1 << 17]byte +var z10190 [1 << 17]byte +var z10191 [1 << 17]byte +var z10192 [1 << 17]byte +var z10193 [1 << 17]byte +var z10194 [1 << 17]byte +var z10195 [1 << 17]byte +var z10196 [1 << 17]byte +var z10197 [1 << 17]byte +var z10198 [1 << 17]byte +var z10199 [1 << 17]byte +var z10200 [1 << 17]byte +var z10201 [1 << 17]byte +var z10202 [1 << 17]byte +var z10203 [1 << 17]byte +var z10204 [1 << 17]byte +var z10205 [1 << 17]byte +var z10206 [1 << 17]byte +var z10207 [1 << 17]byte +var z10208 [1 << 17]byte +var z10209 [1 << 17]byte +var z10210 [1 << 17]byte +var z10211 [1 << 17]byte +var z10212 [1 << 17]byte +var z10213 [1 << 17]byte +var z10214 [1 << 17]byte +var z10215 [1 << 17]byte +var z10216 [1 << 17]byte +var z10217 [1 << 17]byte +var z10218 [1 << 17]byte +var z10219 [1 << 17]byte +var z10220 [1 << 17]byte +var z10221 [1 << 17]byte +var z10222 [1 << 17]byte +var z10223 [1 << 17]byte +var z10224 [1 << 17]byte +var z10225 [1 << 17]byte +var z10226 [1 << 17]byte +var z10227 [1 << 17]byte +var z10228 [1 << 17]byte +var z10229 [1 << 17]byte +var z10230 [1 << 17]byte +var z10231 [1 << 17]byte +var z10232 [1 << 17]byte +var z10233 [1 << 17]byte +var z10234 [1 << 17]byte +var z10235 [1 << 17]byte +var z10236 [1 << 17]byte +var z10237 [1 << 17]byte +var z10238 [1 << 17]byte +var z10239 [1 << 17]byte +var z10240 [1 << 17]byte +var z10241 [1 << 17]byte +var z10242 [1 << 17]byte +var z10243 [1 << 17]byte +var z10244 [1 << 17]byte +var z10245 [1 << 17]byte +var z10246 [1 << 17]byte +var z10247 [1 << 17]byte +var z10248 [1 << 17]byte +var z10249 [1 << 17]byte +var z10250 [1 << 17]byte +var z10251 [1 << 17]byte +var z10252 [1 << 17]byte +var z10253 [1 << 17]byte +var z10254 [1 << 17]byte +var z10255 [1 << 17]byte +var z10256 [1 << 17]byte +var z10257 [1 << 17]byte +var z10258 [1 << 17]byte +var z10259 [1 << 17]byte +var z10260 [1 << 17]byte +var z10261 [1 << 17]byte +var z10262 [1 << 17]byte +var z10263 [1 << 17]byte +var z10264 [1 << 17]byte +var z10265 [1 << 17]byte +var z10266 [1 << 17]byte +var z10267 [1 << 17]byte +var z10268 [1 << 17]byte +var z10269 [1 << 17]byte +var z10270 [1 << 17]byte +var z10271 [1 << 17]byte +var z10272 [1 << 17]byte +var z10273 [1 << 17]byte +var z10274 [1 << 17]byte +var z10275 [1 << 17]byte +var z10276 [1 << 17]byte +var z10277 [1 << 17]byte +var z10278 [1 << 17]byte +var z10279 [1 << 17]byte +var z10280 [1 << 17]byte +var z10281 [1 << 17]byte +var z10282 [1 << 17]byte +var z10283 [1 << 17]byte +var z10284 [1 << 17]byte +var z10285 [1 << 17]byte +var z10286 [1 << 17]byte +var z10287 [1 << 17]byte +var z10288 [1 << 17]byte +var z10289 [1 << 17]byte +var z10290 [1 << 17]byte +var z10291 [1 << 17]byte +var z10292 [1 << 17]byte +var z10293 [1 << 17]byte +var z10294 [1 << 17]byte +var z10295 [1 << 17]byte +var z10296 [1 << 17]byte +var z10297 [1 << 17]byte +var z10298 [1 << 17]byte +var z10299 [1 << 17]byte +var z10300 [1 << 17]byte +var z10301 [1 << 17]byte +var z10302 [1 << 17]byte +var z10303 [1 << 17]byte +var z10304 [1 << 17]byte +var z10305 [1 << 17]byte +var z10306 [1 << 17]byte +var z10307 [1 << 17]byte +var z10308 [1 << 17]byte +var z10309 [1 << 17]byte +var z10310 [1 << 17]byte +var z10311 [1 << 17]byte +var z10312 [1 << 17]byte +var z10313 [1 << 17]byte +var z10314 [1 << 17]byte +var z10315 [1 << 17]byte +var z10316 [1 << 17]byte +var z10317 [1 << 17]byte +var z10318 [1 << 17]byte +var z10319 [1 << 17]byte +var z10320 [1 << 17]byte +var z10321 [1 << 17]byte +var z10322 [1 << 17]byte +var z10323 [1 << 17]byte +var z10324 [1 << 17]byte +var z10325 [1 << 17]byte +var z10326 [1 << 17]byte +var z10327 [1 << 17]byte +var z10328 [1 << 17]byte +var z10329 [1 << 17]byte +var z10330 [1 << 17]byte +var z10331 [1 << 17]byte +var z10332 [1 << 17]byte +var z10333 [1 << 17]byte +var z10334 [1 << 17]byte +var z10335 [1 << 17]byte +var z10336 [1 << 17]byte +var z10337 [1 << 17]byte +var z10338 [1 << 17]byte +var z10339 [1 << 17]byte +var z10340 [1 << 17]byte +var z10341 [1 << 17]byte +var z10342 [1 << 17]byte +var z10343 [1 << 17]byte +var z10344 [1 << 17]byte +var z10345 [1 << 17]byte +var z10346 [1 << 17]byte +var z10347 [1 << 17]byte +var z10348 [1 << 17]byte +var z10349 [1 << 17]byte +var z10350 [1 << 17]byte +var z10351 [1 << 17]byte +var z10352 [1 << 17]byte +var z10353 [1 << 17]byte +var z10354 [1 << 17]byte +var z10355 [1 << 17]byte +var z10356 [1 << 17]byte +var z10357 [1 << 17]byte +var z10358 [1 << 17]byte +var z10359 [1 << 17]byte +var z10360 [1 << 17]byte +var z10361 [1 << 17]byte +var z10362 [1 << 17]byte +var z10363 [1 << 17]byte +var z10364 [1 << 17]byte +var z10365 [1 << 17]byte +var z10366 [1 << 17]byte +var z10367 [1 << 17]byte +var z10368 [1 << 17]byte +var z10369 [1 << 17]byte +var z10370 [1 << 17]byte +var z10371 [1 << 17]byte +var z10372 [1 << 17]byte +var z10373 [1 << 17]byte +var z10374 [1 << 17]byte +var z10375 [1 << 17]byte +var z10376 [1 << 17]byte +var z10377 [1 << 17]byte +var z10378 [1 << 17]byte +var z10379 [1 << 17]byte +var z10380 [1 << 17]byte +var z10381 [1 << 17]byte +var z10382 [1 << 17]byte +var z10383 [1 << 17]byte +var z10384 [1 << 17]byte +var z10385 [1 << 17]byte +var z10386 [1 << 17]byte +var z10387 [1 << 17]byte +var z10388 [1 << 17]byte +var z10389 [1 << 17]byte +var z10390 [1 << 17]byte +var z10391 [1 << 17]byte +var z10392 [1 << 17]byte +var z10393 [1 << 17]byte +var z10394 [1 << 17]byte +var z10395 [1 << 17]byte +var z10396 [1 << 17]byte +var z10397 [1 << 17]byte +var z10398 [1 << 17]byte +var z10399 [1 << 17]byte +var z10400 [1 << 17]byte +var z10401 [1 << 17]byte +var z10402 [1 << 17]byte +var z10403 [1 << 17]byte +var z10404 [1 << 17]byte +var z10405 [1 << 17]byte +var z10406 [1 << 17]byte +var z10407 [1 << 17]byte +var z10408 [1 << 17]byte +var z10409 [1 << 17]byte +var z10410 [1 << 17]byte +var z10411 [1 << 17]byte +var z10412 [1 << 17]byte +var z10413 [1 << 17]byte +var z10414 [1 << 17]byte +var z10415 [1 << 17]byte +var z10416 [1 << 17]byte +var z10417 [1 << 17]byte +var z10418 [1 << 17]byte +var z10419 [1 << 17]byte +var z10420 [1 << 17]byte +var z10421 [1 << 17]byte +var z10422 [1 << 17]byte +var z10423 [1 << 17]byte +var z10424 [1 << 17]byte +var z10425 [1 << 17]byte +var z10426 [1 << 17]byte +var z10427 [1 << 17]byte +var z10428 [1 << 17]byte +var z10429 [1 << 17]byte +var z10430 [1 << 17]byte +var z10431 [1 << 17]byte +var z10432 [1 << 17]byte +var z10433 [1 << 17]byte +var z10434 [1 << 17]byte +var z10435 [1 << 17]byte +var z10436 [1 << 17]byte +var z10437 [1 << 17]byte +var z10438 [1 << 17]byte +var z10439 [1 << 17]byte +var z10440 [1 << 17]byte +var z10441 [1 << 17]byte +var z10442 [1 << 17]byte +var z10443 [1 << 17]byte +var z10444 [1 << 17]byte +var z10445 [1 << 17]byte +var z10446 [1 << 17]byte +var z10447 [1 << 17]byte +var z10448 [1 << 17]byte +var z10449 [1 << 17]byte +var z10450 [1 << 17]byte +var z10451 [1 << 17]byte +var z10452 [1 << 17]byte +var z10453 [1 << 17]byte +var z10454 [1 << 17]byte +var z10455 [1 << 17]byte +var z10456 [1 << 17]byte +var z10457 [1 << 17]byte +var z10458 [1 << 17]byte +var z10459 [1 << 17]byte +var z10460 [1 << 17]byte +var z10461 [1 << 17]byte +var z10462 [1 << 17]byte +var z10463 [1 << 17]byte +var z10464 [1 << 17]byte +var z10465 [1 << 17]byte +var z10466 [1 << 17]byte +var z10467 [1 << 17]byte +var z10468 [1 << 17]byte +var z10469 [1 << 17]byte +var z10470 [1 << 17]byte +var z10471 [1 << 17]byte +var z10472 [1 << 17]byte +var z10473 [1 << 17]byte +var z10474 [1 << 17]byte +var z10475 [1 << 17]byte +var z10476 [1 << 17]byte +var z10477 [1 << 17]byte +var z10478 [1 << 17]byte +var z10479 [1 << 17]byte +var z10480 [1 << 17]byte +var z10481 [1 << 17]byte +var z10482 [1 << 17]byte +var z10483 [1 << 17]byte +var z10484 [1 << 17]byte +var z10485 [1 << 17]byte +var z10486 [1 << 17]byte +var z10487 [1 << 17]byte +var z10488 [1 << 17]byte +var z10489 [1 << 17]byte +var z10490 [1 << 17]byte +var z10491 [1 << 17]byte +var z10492 [1 << 17]byte +var z10493 [1 << 17]byte +var z10494 [1 << 17]byte +var z10495 [1 << 17]byte +var z10496 [1 << 17]byte +var z10497 [1 << 17]byte +var z10498 [1 << 17]byte +var z10499 [1 << 17]byte +var z10500 [1 << 17]byte +var z10501 [1 << 17]byte +var z10502 [1 << 17]byte +var z10503 [1 << 17]byte +var z10504 [1 << 17]byte +var z10505 [1 << 17]byte +var z10506 [1 << 17]byte +var z10507 [1 << 17]byte +var z10508 [1 << 17]byte +var z10509 [1 << 17]byte +var z10510 [1 << 17]byte +var z10511 [1 << 17]byte +var z10512 [1 << 17]byte +var z10513 [1 << 17]byte +var z10514 [1 << 17]byte +var z10515 [1 << 17]byte +var z10516 [1 << 17]byte +var z10517 [1 << 17]byte +var z10518 [1 << 17]byte +var z10519 [1 << 17]byte +var z10520 [1 << 17]byte +var z10521 [1 << 17]byte +var z10522 [1 << 17]byte +var z10523 [1 << 17]byte +var z10524 [1 << 17]byte +var z10525 [1 << 17]byte +var z10526 [1 << 17]byte +var z10527 [1 << 17]byte +var z10528 [1 << 17]byte +var z10529 [1 << 17]byte +var z10530 [1 << 17]byte +var z10531 [1 << 17]byte +var z10532 [1 << 17]byte +var z10533 [1 << 17]byte +var z10534 [1 << 17]byte +var z10535 [1 << 17]byte +var z10536 [1 << 17]byte +var z10537 [1 << 17]byte +var z10538 [1 << 17]byte +var z10539 [1 << 17]byte +var z10540 [1 << 17]byte +var z10541 [1 << 17]byte +var z10542 [1 << 17]byte +var z10543 [1 << 17]byte +var z10544 [1 << 17]byte +var z10545 [1 << 17]byte +var z10546 [1 << 17]byte +var z10547 [1 << 17]byte +var z10548 [1 << 17]byte +var z10549 [1 << 17]byte +var z10550 [1 << 17]byte +var z10551 [1 << 17]byte +var z10552 [1 << 17]byte +var z10553 [1 << 17]byte +var z10554 [1 << 17]byte +var z10555 [1 << 17]byte +var z10556 [1 << 17]byte +var z10557 [1 << 17]byte +var z10558 [1 << 17]byte +var z10559 [1 << 17]byte +var z10560 [1 << 17]byte +var z10561 [1 << 17]byte +var z10562 [1 << 17]byte +var z10563 [1 << 17]byte +var z10564 [1 << 17]byte +var z10565 [1 << 17]byte +var z10566 [1 << 17]byte +var z10567 [1 << 17]byte +var z10568 [1 << 17]byte +var z10569 [1 << 17]byte +var z10570 [1 << 17]byte +var z10571 [1 << 17]byte +var z10572 [1 << 17]byte +var z10573 [1 << 17]byte +var z10574 [1 << 17]byte +var z10575 [1 << 17]byte +var z10576 [1 << 17]byte +var z10577 [1 << 17]byte +var z10578 [1 << 17]byte +var z10579 [1 << 17]byte +var z10580 [1 << 17]byte +var z10581 [1 << 17]byte +var z10582 [1 << 17]byte +var z10583 [1 << 17]byte +var z10584 [1 << 17]byte +var z10585 [1 << 17]byte +var z10586 [1 << 17]byte +var z10587 [1 << 17]byte +var z10588 [1 << 17]byte +var z10589 [1 << 17]byte +var z10590 [1 << 17]byte +var z10591 [1 << 17]byte +var z10592 [1 << 17]byte +var z10593 [1 << 17]byte +var z10594 [1 << 17]byte +var z10595 [1 << 17]byte +var z10596 [1 << 17]byte +var z10597 [1 << 17]byte +var z10598 [1 << 17]byte +var z10599 [1 << 17]byte +var z10600 [1 << 17]byte +var z10601 [1 << 17]byte +var z10602 [1 << 17]byte +var z10603 [1 << 17]byte +var z10604 [1 << 17]byte +var z10605 [1 << 17]byte +var z10606 [1 << 17]byte +var z10607 [1 << 17]byte +var z10608 [1 << 17]byte +var z10609 [1 << 17]byte +var z10610 [1 << 17]byte +var z10611 [1 << 17]byte +var z10612 [1 << 17]byte +var z10613 [1 << 17]byte +var z10614 [1 << 17]byte +var z10615 [1 << 17]byte +var z10616 [1 << 17]byte +var z10617 [1 << 17]byte +var z10618 [1 << 17]byte +var z10619 [1 << 17]byte +var z10620 [1 << 17]byte +var z10621 [1 << 17]byte +var z10622 [1 << 17]byte +var z10623 [1 << 17]byte +var z10624 [1 << 17]byte +var z10625 [1 << 17]byte +var z10626 [1 << 17]byte +var z10627 [1 << 17]byte +var z10628 [1 << 17]byte +var z10629 [1 << 17]byte +var z10630 [1 << 17]byte +var z10631 [1 << 17]byte +var z10632 [1 << 17]byte +var z10633 [1 << 17]byte +var z10634 [1 << 17]byte +var z10635 [1 << 17]byte +var z10636 [1 << 17]byte +var z10637 [1 << 17]byte +var z10638 [1 << 17]byte +var z10639 [1 << 17]byte +var z10640 [1 << 17]byte +var z10641 [1 << 17]byte +var z10642 [1 << 17]byte +var z10643 [1 << 17]byte +var z10644 [1 << 17]byte +var z10645 [1 << 17]byte +var z10646 [1 << 17]byte +var z10647 [1 << 17]byte +var z10648 [1 << 17]byte +var z10649 [1 << 17]byte +var z10650 [1 << 17]byte +var z10651 [1 << 17]byte +var z10652 [1 << 17]byte +var z10653 [1 << 17]byte +var z10654 [1 << 17]byte +var z10655 [1 << 17]byte +var z10656 [1 << 17]byte +var z10657 [1 << 17]byte +var z10658 [1 << 17]byte +var z10659 [1 << 17]byte +var z10660 [1 << 17]byte +var z10661 [1 << 17]byte +var z10662 [1 << 17]byte +var z10663 [1 << 17]byte +var z10664 [1 << 17]byte +var z10665 [1 << 17]byte +var z10666 [1 << 17]byte +var z10667 [1 << 17]byte +var z10668 [1 << 17]byte +var z10669 [1 << 17]byte +var z10670 [1 << 17]byte +var z10671 [1 << 17]byte +var z10672 [1 << 17]byte +var z10673 [1 << 17]byte +var z10674 [1 << 17]byte +var z10675 [1 << 17]byte +var z10676 [1 << 17]byte +var z10677 [1 << 17]byte +var z10678 [1 << 17]byte +var z10679 [1 << 17]byte +var z10680 [1 << 17]byte +var z10681 [1 << 17]byte +var z10682 [1 << 17]byte +var z10683 [1 << 17]byte +var z10684 [1 << 17]byte +var z10685 [1 << 17]byte +var z10686 [1 << 17]byte +var z10687 [1 << 17]byte +var z10688 [1 << 17]byte +var z10689 [1 << 17]byte +var z10690 [1 << 17]byte +var z10691 [1 << 17]byte +var z10692 [1 << 17]byte +var z10693 [1 << 17]byte +var z10694 [1 << 17]byte +var z10695 [1 << 17]byte +var z10696 [1 << 17]byte +var z10697 [1 << 17]byte +var z10698 [1 << 17]byte +var z10699 [1 << 17]byte +var z10700 [1 << 17]byte +var z10701 [1 << 17]byte +var z10702 [1 << 17]byte +var z10703 [1 << 17]byte +var z10704 [1 << 17]byte +var z10705 [1 << 17]byte +var z10706 [1 << 17]byte +var z10707 [1 << 17]byte +var z10708 [1 << 17]byte +var z10709 [1 << 17]byte +var z10710 [1 << 17]byte +var z10711 [1 << 17]byte +var z10712 [1 << 17]byte +var z10713 [1 << 17]byte +var z10714 [1 << 17]byte +var z10715 [1 << 17]byte +var z10716 [1 << 17]byte +var z10717 [1 << 17]byte +var z10718 [1 << 17]byte +var z10719 [1 << 17]byte +var z10720 [1 << 17]byte +var z10721 [1 << 17]byte +var z10722 [1 << 17]byte +var z10723 [1 << 17]byte +var z10724 [1 << 17]byte +var z10725 [1 << 17]byte +var z10726 [1 << 17]byte +var z10727 [1 << 17]byte +var z10728 [1 << 17]byte +var z10729 [1 << 17]byte +var z10730 [1 << 17]byte +var z10731 [1 << 17]byte +var z10732 [1 << 17]byte +var z10733 [1 << 17]byte +var z10734 [1 << 17]byte +var z10735 [1 << 17]byte +var z10736 [1 << 17]byte +var z10737 [1 << 17]byte +var z10738 [1 << 17]byte +var z10739 [1 << 17]byte +var z10740 [1 << 17]byte +var z10741 [1 << 17]byte +var z10742 [1 << 17]byte +var z10743 [1 << 17]byte +var z10744 [1 << 17]byte +var z10745 [1 << 17]byte +var z10746 [1 << 17]byte +var z10747 [1 << 17]byte +var z10748 [1 << 17]byte +var z10749 [1 << 17]byte +var z10750 [1 << 17]byte +var z10751 [1 << 17]byte +var z10752 [1 << 17]byte +var z10753 [1 << 17]byte +var z10754 [1 << 17]byte +var z10755 [1 << 17]byte +var z10756 [1 << 17]byte +var z10757 [1 << 17]byte +var z10758 [1 << 17]byte +var z10759 [1 << 17]byte +var z10760 [1 << 17]byte +var z10761 [1 << 17]byte +var z10762 [1 << 17]byte +var z10763 [1 << 17]byte +var z10764 [1 << 17]byte +var z10765 [1 << 17]byte +var z10766 [1 << 17]byte +var z10767 [1 << 17]byte +var z10768 [1 << 17]byte +var z10769 [1 << 17]byte +var z10770 [1 << 17]byte +var z10771 [1 << 17]byte +var z10772 [1 << 17]byte +var z10773 [1 << 17]byte +var z10774 [1 << 17]byte +var z10775 [1 << 17]byte +var z10776 [1 << 17]byte +var z10777 [1 << 17]byte +var z10778 [1 << 17]byte +var z10779 [1 << 17]byte +var z10780 [1 << 17]byte +var z10781 [1 << 17]byte +var z10782 [1 << 17]byte +var z10783 [1 << 17]byte +var z10784 [1 << 17]byte +var z10785 [1 << 17]byte +var z10786 [1 << 17]byte +var z10787 [1 << 17]byte +var z10788 [1 << 17]byte +var z10789 [1 << 17]byte +var z10790 [1 << 17]byte +var z10791 [1 << 17]byte +var z10792 [1 << 17]byte +var z10793 [1 << 17]byte +var z10794 [1 << 17]byte +var z10795 [1 << 17]byte +var z10796 [1 << 17]byte +var z10797 [1 << 17]byte +var z10798 [1 << 17]byte +var z10799 [1 << 17]byte +var z10800 [1 << 17]byte +var z10801 [1 << 17]byte +var z10802 [1 << 17]byte +var z10803 [1 << 17]byte +var z10804 [1 << 17]byte +var z10805 [1 << 17]byte +var z10806 [1 << 17]byte +var z10807 [1 << 17]byte +var z10808 [1 << 17]byte +var z10809 [1 << 17]byte +var z10810 [1 << 17]byte +var z10811 [1 << 17]byte +var z10812 [1 << 17]byte +var z10813 [1 << 17]byte +var z10814 [1 << 17]byte +var z10815 [1 << 17]byte +var z10816 [1 << 17]byte +var z10817 [1 << 17]byte +var z10818 [1 << 17]byte +var z10819 [1 << 17]byte +var z10820 [1 << 17]byte +var z10821 [1 << 17]byte +var z10822 [1 << 17]byte +var z10823 [1 << 17]byte +var z10824 [1 << 17]byte +var z10825 [1 << 17]byte +var z10826 [1 << 17]byte +var z10827 [1 << 17]byte +var z10828 [1 << 17]byte +var z10829 [1 << 17]byte +var z10830 [1 << 17]byte +var z10831 [1 << 17]byte +var z10832 [1 << 17]byte +var z10833 [1 << 17]byte +var z10834 [1 << 17]byte +var z10835 [1 << 17]byte +var z10836 [1 << 17]byte +var z10837 [1 << 17]byte +var z10838 [1 << 17]byte +var z10839 [1 << 17]byte +var z10840 [1 << 17]byte +var z10841 [1 << 17]byte +var z10842 [1 << 17]byte +var z10843 [1 << 17]byte +var z10844 [1 << 17]byte +var z10845 [1 << 17]byte +var z10846 [1 << 17]byte +var z10847 [1 << 17]byte +var z10848 [1 << 17]byte +var z10849 [1 << 17]byte +var z10850 [1 << 17]byte +var z10851 [1 << 17]byte +var z10852 [1 << 17]byte +var z10853 [1 << 17]byte +var z10854 [1 << 17]byte +var z10855 [1 << 17]byte +var z10856 [1 << 17]byte +var z10857 [1 << 17]byte +var z10858 [1 << 17]byte +var z10859 [1 << 17]byte +var z10860 [1 << 17]byte +var z10861 [1 << 17]byte +var z10862 [1 << 17]byte +var z10863 [1 << 17]byte +var z10864 [1 << 17]byte +var z10865 [1 << 17]byte +var z10866 [1 << 17]byte +var z10867 [1 << 17]byte +var z10868 [1 << 17]byte +var z10869 [1 << 17]byte +var z10870 [1 << 17]byte +var z10871 [1 << 17]byte +var z10872 [1 << 17]byte +var z10873 [1 << 17]byte +var z10874 [1 << 17]byte +var z10875 [1 << 17]byte +var z10876 [1 << 17]byte +var z10877 [1 << 17]byte +var z10878 [1 << 17]byte +var z10879 [1 << 17]byte +var z10880 [1 << 17]byte +var z10881 [1 << 17]byte +var z10882 [1 << 17]byte +var z10883 [1 << 17]byte +var z10884 [1 << 17]byte +var z10885 [1 << 17]byte +var z10886 [1 << 17]byte +var z10887 [1 << 17]byte +var z10888 [1 << 17]byte +var z10889 [1 << 17]byte +var z10890 [1 << 17]byte +var z10891 [1 << 17]byte +var z10892 [1 << 17]byte +var z10893 [1 << 17]byte +var z10894 [1 << 17]byte +var z10895 [1 << 17]byte +var z10896 [1 << 17]byte +var z10897 [1 << 17]byte +var z10898 [1 << 17]byte +var z10899 [1 << 17]byte +var z10900 [1 << 17]byte +var z10901 [1 << 17]byte +var z10902 [1 << 17]byte +var z10903 [1 << 17]byte +var z10904 [1 << 17]byte +var z10905 [1 << 17]byte +var z10906 [1 << 17]byte +var z10907 [1 << 17]byte +var z10908 [1 << 17]byte +var z10909 [1 << 17]byte +var z10910 [1 << 17]byte +var z10911 [1 << 17]byte +var z10912 [1 << 17]byte +var z10913 [1 << 17]byte +var z10914 [1 << 17]byte +var z10915 [1 << 17]byte +var z10916 [1 << 17]byte +var z10917 [1 << 17]byte +var z10918 [1 << 17]byte +var z10919 [1 << 17]byte +var z10920 [1 << 17]byte +var z10921 [1 << 17]byte +var z10922 [1 << 17]byte +var z10923 [1 << 17]byte +var z10924 [1 << 17]byte +var z10925 [1 << 17]byte +var z10926 [1 << 17]byte +var z10927 [1 << 17]byte +var z10928 [1 << 17]byte +var z10929 [1 << 17]byte +var z10930 [1 << 17]byte +var z10931 [1 << 17]byte +var z10932 [1 << 17]byte +var z10933 [1 << 17]byte +var z10934 [1 << 17]byte +var z10935 [1 << 17]byte +var z10936 [1 << 17]byte +var z10937 [1 << 17]byte +var z10938 [1 << 17]byte +var z10939 [1 << 17]byte +var z10940 [1 << 17]byte +var z10941 [1 << 17]byte +var z10942 [1 << 17]byte +var z10943 [1 << 17]byte +var z10944 [1 << 17]byte +var z10945 [1 << 17]byte +var z10946 [1 << 17]byte +var z10947 [1 << 17]byte +var z10948 [1 << 17]byte +var z10949 [1 << 17]byte +var z10950 [1 << 17]byte +var z10951 [1 << 17]byte +var z10952 [1 << 17]byte +var z10953 [1 << 17]byte +var z10954 [1 << 17]byte +var z10955 [1 << 17]byte +var z10956 [1 << 17]byte +var z10957 [1 << 17]byte +var z10958 [1 << 17]byte +var z10959 [1 << 17]byte +var z10960 [1 << 17]byte +var z10961 [1 << 17]byte +var z10962 [1 << 17]byte +var z10963 [1 << 17]byte +var z10964 [1 << 17]byte +var z10965 [1 << 17]byte +var z10966 [1 << 17]byte +var z10967 [1 << 17]byte +var z10968 [1 << 17]byte +var z10969 [1 << 17]byte +var z10970 [1 << 17]byte +var z10971 [1 << 17]byte +var z10972 [1 << 17]byte +var z10973 [1 << 17]byte +var z10974 [1 << 17]byte +var z10975 [1 << 17]byte +var z10976 [1 << 17]byte +var z10977 [1 << 17]byte +var z10978 [1 << 17]byte +var z10979 [1 << 17]byte +var z10980 [1 << 17]byte +var z10981 [1 << 17]byte +var z10982 [1 << 17]byte +var z10983 [1 << 17]byte +var z10984 [1 << 17]byte +var z10985 [1 << 17]byte +var z10986 [1 << 17]byte +var z10987 [1 << 17]byte +var z10988 [1 << 17]byte +var z10989 [1 << 17]byte +var z10990 [1 << 17]byte +var z10991 [1 << 17]byte +var z10992 [1 << 17]byte +var z10993 [1 << 17]byte +var z10994 [1 << 17]byte +var z10995 [1 << 17]byte +var z10996 [1 << 17]byte +var z10997 [1 << 17]byte +var z10998 [1 << 17]byte +var z10999 [1 << 17]byte +var z11000 [1 << 17]byte +var z11001 [1 << 17]byte +var z11002 [1 << 17]byte +var z11003 [1 << 17]byte +var z11004 [1 << 17]byte +var z11005 [1 << 17]byte +var z11006 [1 << 17]byte +var z11007 [1 << 17]byte +var z11008 [1 << 17]byte +var z11009 [1 << 17]byte +var z11010 [1 << 17]byte +var z11011 [1 << 17]byte +var z11012 [1 << 17]byte +var z11013 [1 << 17]byte +var z11014 [1 << 17]byte +var z11015 [1 << 17]byte +var z11016 [1 << 17]byte +var z11017 [1 << 17]byte +var z11018 [1 << 17]byte +var z11019 [1 << 17]byte +var z11020 [1 << 17]byte +var z11021 [1 << 17]byte +var z11022 [1 << 17]byte +var z11023 [1 << 17]byte +var z11024 [1 << 17]byte +var z11025 [1 << 17]byte +var z11026 [1 << 17]byte +var z11027 [1 << 17]byte +var z11028 [1 << 17]byte +var z11029 [1 << 17]byte +var z11030 [1 << 17]byte +var z11031 [1 << 17]byte +var z11032 [1 << 17]byte +var z11033 [1 << 17]byte +var z11034 [1 << 17]byte +var z11035 [1 << 17]byte +var z11036 [1 << 17]byte +var z11037 [1 << 17]byte +var z11038 [1 << 17]byte +var z11039 [1 << 17]byte +var z11040 [1 << 17]byte +var z11041 [1 << 17]byte +var z11042 [1 << 17]byte +var z11043 [1 << 17]byte +var z11044 [1 << 17]byte +var z11045 [1 << 17]byte +var z11046 [1 << 17]byte +var z11047 [1 << 17]byte +var z11048 [1 << 17]byte +var z11049 [1 << 17]byte +var z11050 [1 << 17]byte +var z11051 [1 << 17]byte +var z11052 [1 << 17]byte +var z11053 [1 << 17]byte +var z11054 [1 << 17]byte +var z11055 [1 << 17]byte +var z11056 [1 << 17]byte +var z11057 [1 << 17]byte +var z11058 [1 << 17]byte +var z11059 [1 << 17]byte +var z11060 [1 << 17]byte +var z11061 [1 << 17]byte +var z11062 [1 << 17]byte +var z11063 [1 << 17]byte +var z11064 [1 << 17]byte +var z11065 [1 << 17]byte +var z11066 [1 << 17]byte +var z11067 [1 << 17]byte +var z11068 [1 << 17]byte +var z11069 [1 << 17]byte +var z11070 [1 << 17]byte +var z11071 [1 << 17]byte +var z11072 [1 << 17]byte +var z11073 [1 << 17]byte +var z11074 [1 << 17]byte +var z11075 [1 << 17]byte +var z11076 [1 << 17]byte +var z11077 [1 << 17]byte +var z11078 [1 << 17]byte +var z11079 [1 << 17]byte +var z11080 [1 << 17]byte +var z11081 [1 << 17]byte +var z11082 [1 << 17]byte +var z11083 [1 << 17]byte +var z11084 [1 << 17]byte +var z11085 [1 << 17]byte +var z11086 [1 << 17]byte +var z11087 [1 << 17]byte +var z11088 [1 << 17]byte +var z11089 [1 << 17]byte +var z11090 [1 << 17]byte +var z11091 [1 << 17]byte +var z11092 [1 << 17]byte +var z11093 [1 << 17]byte +var z11094 [1 << 17]byte +var z11095 [1 << 17]byte +var z11096 [1 << 17]byte +var z11097 [1 << 17]byte +var z11098 [1 << 17]byte +var z11099 [1 << 17]byte +var z11100 [1 << 17]byte +var z11101 [1 << 17]byte +var z11102 [1 << 17]byte +var z11103 [1 << 17]byte +var z11104 [1 << 17]byte +var z11105 [1 << 17]byte +var z11106 [1 << 17]byte +var z11107 [1 << 17]byte +var z11108 [1 << 17]byte +var z11109 [1 << 17]byte +var z11110 [1 << 17]byte +var z11111 [1 << 17]byte +var z11112 [1 << 17]byte +var z11113 [1 << 17]byte +var z11114 [1 << 17]byte +var z11115 [1 << 17]byte +var z11116 [1 << 17]byte +var z11117 [1 << 17]byte +var z11118 [1 << 17]byte +var z11119 [1 << 17]byte +var z11120 [1 << 17]byte +var z11121 [1 << 17]byte +var z11122 [1 << 17]byte +var z11123 [1 << 17]byte +var z11124 [1 << 17]byte +var z11125 [1 << 17]byte +var z11126 [1 << 17]byte +var z11127 [1 << 17]byte +var z11128 [1 << 17]byte +var z11129 [1 << 17]byte +var z11130 [1 << 17]byte +var z11131 [1 << 17]byte +var z11132 [1 << 17]byte +var z11133 [1 << 17]byte +var z11134 [1 << 17]byte +var z11135 [1 << 17]byte +var z11136 [1 << 17]byte +var z11137 [1 << 17]byte +var z11138 [1 << 17]byte +var z11139 [1 << 17]byte +var z11140 [1 << 17]byte +var z11141 [1 << 17]byte +var z11142 [1 << 17]byte +var z11143 [1 << 17]byte +var z11144 [1 << 17]byte +var z11145 [1 << 17]byte +var z11146 [1 << 17]byte +var z11147 [1 << 17]byte +var z11148 [1 << 17]byte +var z11149 [1 << 17]byte +var z11150 [1 << 17]byte +var z11151 [1 << 17]byte +var z11152 [1 << 17]byte +var z11153 [1 << 17]byte +var z11154 [1 << 17]byte +var z11155 [1 << 17]byte +var z11156 [1 << 17]byte +var z11157 [1 << 17]byte +var z11158 [1 << 17]byte +var z11159 [1 << 17]byte +var z11160 [1 << 17]byte +var z11161 [1 << 17]byte +var z11162 [1 << 17]byte +var z11163 [1 << 17]byte +var z11164 [1 << 17]byte +var z11165 [1 << 17]byte +var z11166 [1 << 17]byte +var z11167 [1 << 17]byte +var z11168 [1 << 17]byte +var z11169 [1 << 17]byte +var z11170 [1 << 17]byte +var z11171 [1 << 17]byte +var z11172 [1 << 17]byte +var z11173 [1 << 17]byte +var z11174 [1 << 17]byte +var z11175 [1 << 17]byte +var z11176 [1 << 17]byte +var z11177 [1 << 17]byte +var z11178 [1 << 17]byte +var z11179 [1 << 17]byte +var z11180 [1 << 17]byte +var z11181 [1 << 17]byte +var z11182 [1 << 17]byte +var z11183 [1 << 17]byte +var z11184 [1 << 17]byte +var z11185 [1 << 17]byte +var z11186 [1 << 17]byte +var z11187 [1 << 17]byte +var z11188 [1 << 17]byte +var z11189 [1 << 17]byte +var z11190 [1 << 17]byte +var z11191 [1 << 17]byte +var z11192 [1 << 17]byte +var z11193 [1 << 17]byte +var z11194 [1 << 17]byte +var z11195 [1 << 17]byte +var z11196 [1 << 17]byte +var z11197 [1 << 17]byte +var z11198 [1 << 17]byte +var z11199 [1 << 17]byte +var z11200 [1 << 17]byte +var z11201 [1 << 17]byte +var z11202 [1 << 17]byte +var z11203 [1 << 17]byte +var z11204 [1 << 17]byte +var z11205 [1 << 17]byte +var z11206 [1 << 17]byte +var z11207 [1 << 17]byte +var z11208 [1 << 17]byte +var z11209 [1 << 17]byte +var z11210 [1 << 17]byte +var z11211 [1 << 17]byte +var z11212 [1 << 17]byte +var z11213 [1 << 17]byte +var z11214 [1 << 17]byte +var z11215 [1 << 17]byte +var z11216 [1 << 17]byte +var z11217 [1 << 17]byte +var z11218 [1 << 17]byte +var z11219 [1 << 17]byte +var z11220 [1 << 17]byte +var z11221 [1 << 17]byte +var z11222 [1 << 17]byte +var z11223 [1 << 17]byte +var z11224 [1 << 17]byte +var z11225 [1 << 17]byte +var z11226 [1 << 17]byte +var z11227 [1 << 17]byte +var z11228 [1 << 17]byte +var z11229 [1 << 17]byte +var z11230 [1 << 17]byte +var z11231 [1 << 17]byte +var z11232 [1 << 17]byte +var z11233 [1 << 17]byte +var z11234 [1 << 17]byte +var z11235 [1 << 17]byte +var z11236 [1 << 17]byte +var z11237 [1 << 17]byte +var z11238 [1 << 17]byte +var z11239 [1 << 17]byte +var z11240 [1 << 17]byte +var z11241 [1 << 17]byte +var z11242 [1 << 17]byte +var z11243 [1 << 17]byte +var z11244 [1 << 17]byte +var z11245 [1 << 17]byte +var z11246 [1 << 17]byte +var z11247 [1 << 17]byte +var z11248 [1 << 17]byte +var z11249 [1 << 17]byte +var z11250 [1 << 17]byte +var z11251 [1 << 17]byte +var z11252 [1 << 17]byte +var z11253 [1 << 17]byte +var z11254 [1 << 17]byte +var z11255 [1 << 17]byte +var z11256 [1 << 17]byte +var z11257 [1 << 17]byte +var z11258 [1 << 17]byte +var z11259 [1 << 17]byte +var z11260 [1 << 17]byte +var z11261 [1 << 17]byte +var z11262 [1 << 17]byte +var z11263 [1 << 17]byte +var z11264 [1 << 17]byte +var z11265 [1 << 17]byte +var z11266 [1 << 17]byte +var z11267 [1 << 17]byte +var z11268 [1 << 17]byte +var z11269 [1 << 17]byte +var z11270 [1 << 17]byte +var z11271 [1 << 17]byte +var z11272 [1 << 17]byte +var z11273 [1 << 17]byte +var z11274 [1 << 17]byte +var z11275 [1 << 17]byte +var z11276 [1 << 17]byte +var z11277 [1 << 17]byte +var z11278 [1 << 17]byte +var z11279 [1 << 17]byte +var z11280 [1 << 17]byte +var z11281 [1 << 17]byte +var z11282 [1 << 17]byte +var z11283 [1 << 17]byte +var z11284 [1 << 17]byte +var z11285 [1 << 17]byte +var z11286 [1 << 17]byte +var z11287 [1 << 17]byte +var z11288 [1 << 17]byte +var z11289 [1 << 17]byte +var z11290 [1 << 17]byte +var z11291 [1 << 17]byte +var z11292 [1 << 17]byte +var z11293 [1 << 17]byte +var z11294 [1 << 17]byte +var z11295 [1 << 17]byte +var z11296 [1 << 17]byte +var z11297 [1 << 17]byte +var z11298 [1 << 17]byte +var z11299 [1 << 17]byte +var z11300 [1 << 17]byte +var z11301 [1 << 17]byte +var z11302 [1 << 17]byte +var z11303 [1 << 17]byte +var z11304 [1 << 17]byte +var z11305 [1 << 17]byte +var z11306 [1 << 17]byte +var z11307 [1 << 17]byte +var z11308 [1 << 17]byte +var z11309 [1 << 17]byte +var z11310 [1 << 17]byte +var z11311 [1 << 17]byte +var z11312 [1 << 17]byte +var z11313 [1 << 17]byte +var z11314 [1 << 17]byte +var z11315 [1 << 17]byte +var z11316 [1 << 17]byte +var z11317 [1 << 17]byte +var z11318 [1 << 17]byte +var z11319 [1 << 17]byte +var z11320 [1 << 17]byte +var z11321 [1 << 17]byte +var z11322 [1 << 17]byte +var z11323 [1 << 17]byte +var z11324 [1 << 17]byte +var z11325 [1 << 17]byte +var z11326 [1 << 17]byte +var z11327 [1 << 17]byte +var z11328 [1 << 17]byte +var z11329 [1 << 17]byte +var z11330 [1 << 17]byte +var z11331 [1 << 17]byte +var z11332 [1 << 17]byte +var z11333 [1 << 17]byte +var z11334 [1 << 17]byte +var z11335 [1 << 17]byte +var z11336 [1 << 17]byte +var z11337 [1 << 17]byte +var z11338 [1 << 17]byte +var z11339 [1 << 17]byte +var z11340 [1 << 17]byte +var z11341 [1 << 17]byte +var z11342 [1 << 17]byte +var z11343 [1 << 17]byte +var z11344 [1 << 17]byte +var z11345 [1 << 17]byte +var z11346 [1 << 17]byte +var z11347 [1 << 17]byte +var z11348 [1 << 17]byte +var z11349 [1 << 17]byte +var z11350 [1 << 17]byte +var z11351 [1 << 17]byte +var z11352 [1 << 17]byte +var z11353 [1 << 17]byte +var z11354 [1 << 17]byte +var z11355 [1 << 17]byte +var z11356 [1 << 17]byte +var z11357 [1 << 17]byte +var z11358 [1 << 17]byte +var z11359 [1 << 17]byte +var z11360 [1 << 17]byte +var z11361 [1 << 17]byte +var z11362 [1 << 17]byte +var z11363 [1 << 17]byte +var z11364 [1 << 17]byte +var z11365 [1 << 17]byte +var z11366 [1 << 17]byte +var z11367 [1 << 17]byte +var z11368 [1 << 17]byte +var z11369 [1 << 17]byte +var z11370 [1 << 17]byte +var z11371 [1 << 17]byte +var z11372 [1 << 17]byte +var z11373 [1 << 17]byte +var z11374 [1 << 17]byte +var z11375 [1 << 17]byte +var z11376 [1 << 17]byte +var z11377 [1 << 17]byte +var z11378 [1 << 17]byte +var z11379 [1 << 17]byte +var z11380 [1 << 17]byte +var z11381 [1 << 17]byte +var z11382 [1 << 17]byte +var z11383 [1 << 17]byte +var z11384 [1 << 17]byte +var z11385 [1 << 17]byte +var z11386 [1 << 17]byte +var z11387 [1 << 17]byte +var z11388 [1 << 17]byte +var z11389 [1 << 17]byte +var z11390 [1 << 17]byte +var z11391 [1 << 17]byte +var z11392 [1 << 17]byte +var z11393 [1 << 17]byte +var z11394 [1 << 17]byte +var z11395 [1 << 17]byte +var z11396 [1 << 17]byte +var z11397 [1 << 17]byte +var z11398 [1 << 17]byte +var z11399 [1 << 17]byte +var z11400 [1 << 17]byte +var z11401 [1 << 17]byte +var z11402 [1 << 17]byte +var z11403 [1 << 17]byte +var z11404 [1 << 17]byte +var z11405 [1 << 17]byte +var z11406 [1 << 17]byte +var z11407 [1 << 17]byte +var z11408 [1 << 17]byte +var z11409 [1 << 17]byte +var z11410 [1 << 17]byte +var z11411 [1 << 17]byte +var z11412 [1 << 17]byte +var z11413 [1 << 17]byte +var z11414 [1 << 17]byte +var z11415 [1 << 17]byte +var z11416 [1 << 17]byte +var z11417 [1 << 17]byte +var z11418 [1 << 17]byte +var z11419 [1 << 17]byte +var z11420 [1 << 17]byte +var z11421 [1 << 17]byte +var z11422 [1 << 17]byte +var z11423 [1 << 17]byte +var z11424 [1 << 17]byte +var z11425 [1 << 17]byte +var z11426 [1 << 17]byte +var z11427 [1 << 17]byte +var z11428 [1 << 17]byte +var z11429 [1 << 17]byte +var z11430 [1 << 17]byte +var z11431 [1 << 17]byte +var z11432 [1 << 17]byte +var z11433 [1 << 17]byte +var z11434 [1 << 17]byte +var z11435 [1 << 17]byte +var z11436 [1 << 17]byte +var z11437 [1 << 17]byte +var z11438 [1 << 17]byte +var z11439 [1 << 17]byte +var z11440 [1 << 17]byte +var z11441 [1 << 17]byte +var z11442 [1 << 17]byte +var z11443 [1 << 17]byte +var z11444 [1 << 17]byte +var z11445 [1 << 17]byte +var z11446 [1 << 17]byte +var z11447 [1 << 17]byte +var z11448 [1 << 17]byte +var z11449 [1 << 17]byte +var z11450 [1 << 17]byte +var z11451 [1 << 17]byte +var z11452 [1 << 17]byte +var z11453 [1 << 17]byte +var z11454 [1 << 17]byte +var z11455 [1 << 17]byte +var z11456 [1 << 17]byte +var z11457 [1 << 17]byte +var z11458 [1 << 17]byte +var z11459 [1 << 17]byte +var z11460 [1 << 17]byte +var z11461 [1 << 17]byte +var z11462 [1 << 17]byte +var z11463 [1 << 17]byte +var z11464 [1 << 17]byte +var z11465 [1 << 17]byte +var z11466 [1 << 17]byte +var z11467 [1 << 17]byte +var z11468 [1 << 17]byte +var z11469 [1 << 17]byte +var z11470 [1 << 17]byte +var z11471 [1 << 17]byte +var z11472 [1 << 17]byte +var z11473 [1 << 17]byte +var z11474 [1 << 17]byte +var z11475 [1 << 17]byte +var z11476 [1 << 17]byte +var z11477 [1 << 17]byte +var z11478 [1 << 17]byte +var z11479 [1 << 17]byte +var z11480 [1 << 17]byte +var z11481 [1 << 17]byte +var z11482 [1 << 17]byte +var z11483 [1 << 17]byte +var z11484 [1 << 17]byte +var z11485 [1 << 17]byte +var z11486 [1 << 17]byte +var z11487 [1 << 17]byte +var z11488 [1 << 17]byte +var z11489 [1 << 17]byte +var z11490 [1 << 17]byte +var z11491 [1 << 17]byte +var z11492 [1 << 17]byte +var z11493 [1 << 17]byte +var z11494 [1 << 17]byte +var z11495 [1 << 17]byte +var z11496 [1 << 17]byte +var z11497 [1 << 17]byte +var z11498 [1 << 17]byte +var z11499 [1 << 17]byte +var z11500 [1 << 17]byte +var z11501 [1 << 17]byte +var z11502 [1 << 17]byte +var z11503 [1 << 17]byte +var z11504 [1 << 17]byte +var z11505 [1 << 17]byte +var z11506 [1 << 17]byte +var z11507 [1 << 17]byte +var z11508 [1 << 17]byte +var z11509 [1 << 17]byte +var z11510 [1 << 17]byte +var z11511 [1 << 17]byte +var z11512 [1 << 17]byte +var z11513 [1 << 17]byte +var z11514 [1 << 17]byte +var z11515 [1 << 17]byte +var z11516 [1 << 17]byte +var z11517 [1 << 17]byte +var z11518 [1 << 17]byte +var z11519 [1 << 17]byte +var z11520 [1 << 17]byte +var z11521 [1 << 17]byte +var z11522 [1 << 17]byte +var z11523 [1 << 17]byte +var z11524 [1 << 17]byte +var z11525 [1 << 17]byte +var z11526 [1 << 17]byte +var z11527 [1 << 17]byte +var z11528 [1 << 17]byte +var z11529 [1 << 17]byte +var z11530 [1 << 17]byte +var z11531 [1 << 17]byte +var z11532 [1 << 17]byte +var z11533 [1 << 17]byte +var z11534 [1 << 17]byte +var z11535 [1 << 17]byte +var z11536 [1 << 17]byte +var z11537 [1 << 17]byte +var z11538 [1 << 17]byte +var z11539 [1 << 17]byte +var z11540 [1 << 17]byte +var z11541 [1 << 17]byte +var z11542 [1 << 17]byte +var z11543 [1 << 17]byte +var z11544 [1 << 17]byte +var z11545 [1 << 17]byte +var z11546 [1 << 17]byte +var z11547 [1 << 17]byte +var z11548 [1 << 17]byte +var z11549 [1 << 17]byte +var z11550 [1 << 17]byte +var z11551 [1 << 17]byte +var z11552 [1 << 17]byte +var z11553 [1 << 17]byte +var z11554 [1 << 17]byte +var z11555 [1 << 17]byte +var z11556 [1 << 17]byte +var z11557 [1 << 17]byte +var z11558 [1 << 17]byte +var z11559 [1 << 17]byte +var z11560 [1 << 17]byte +var z11561 [1 << 17]byte +var z11562 [1 << 17]byte +var z11563 [1 << 17]byte +var z11564 [1 << 17]byte +var z11565 [1 << 17]byte +var z11566 [1 << 17]byte +var z11567 [1 << 17]byte +var z11568 [1 << 17]byte +var z11569 [1 << 17]byte +var z11570 [1 << 17]byte +var z11571 [1 << 17]byte +var z11572 [1 << 17]byte +var z11573 [1 << 17]byte +var z11574 [1 << 17]byte +var z11575 [1 << 17]byte +var z11576 [1 << 17]byte +var z11577 [1 << 17]byte +var z11578 [1 << 17]byte +var z11579 [1 << 17]byte +var z11580 [1 << 17]byte +var z11581 [1 << 17]byte +var z11582 [1 << 17]byte +var z11583 [1 << 17]byte +var z11584 [1 << 17]byte +var z11585 [1 << 17]byte +var z11586 [1 << 17]byte +var z11587 [1 << 17]byte +var z11588 [1 << 17]byte +var z11589 [1 << 17]byte +var z11590 [1 << 17]byte +var z11591 [1 << 17]byte +var z11592 [1 << 17]byte +var z11593 [1 << 17]byte +var z11594 [1 << 17]byte +var z11595 [1 << 17]byte +var z11596 [1 << 17]byte +var z11597 [1 << 17]byte +var z11598 [1 << 17]byte +var z11599 [1 << 17]byte +var z11600 [1 << 17]byte +var z11601 [1 << 17]byte +var z11602 [1 << 17]byte +var z11603 [1 << 17]byte +var z11604 [1 << 17]byte +var z11605 [1 << 17]byte +var z11606 [1 << 17]byte +var z11607 [1 << 17]byte +var z11608 [1 << 17]byte +var z11609 [1 << 17]byte +var z11610 [1 << 17]byte +var z11611 [1 << 17]byte +var z11612 [1 << 17]byte +var z11613 [1 << 17]byte +var z11614 [1 << 17]byte +var z11615 [1 << 17]byte +var z11616 [1 << 17]byte +var z11617 [1 << 17]byte +var z11618 [1 << 17]byte +var z11619 [1 << 17]byte +var z11620 [1 << 17]byte +var z11621 [1 << 17]byte +var z11622 [1 << 17]byte +var z11623 [1 << 17]byte +var z11624 [1 << 17]byte +var z11625 [1 << 17]byte +var z11626 [1 << 17]byte +var z11627 [1 << 17]byte +var z11628 [1 << 17]byte +var z11629 [1 << 17]byte +var z11630 [1 << 17]byte +var z11631 [1 << 17]byte +var z11632 [1 << 17]byte +var z11633 [1 << 17]byte +var z11634 [1 << 17]byte +var z11635 [1 << 17]byte +var z11636 [1 << 17]byte +var z11637 [1 << 17]byte +var z11638 [1 << 17]byte +var z11639 [1 << 17]byte +var z11640 [1 << 17]byte +var z11641 [1 << 17]byte +var z11642 [1 << 17]byte +var z11643 [1 << 17]byte +var z11644 [1 << 17]byte +var z11645 [1 << 17]byte +var z11646 [1 << 17]byte +var z11647 [1 << 17]byte +var z11648 [1 << 17]byte +var z11649 [1 << 17]byte +var z11650 [1 << 17]byte +var z11651 [1 << 17]byte +var z11652 [1 << 17]byte +var z11653 [1 << 17]byte +var z11654 [1 << 17]byte +var z11655 [1 << 17]byte +var z11656 [1 << 17]byte +var z11657 [1 << 17]byte +var z11658 [1 << 17]byte +var z11659 [1 << 17]byte +var z11660 [1 << 17]byte +var z11661 [1 << 17]byte +var z11662 [1 << 17]byte +var z11663 [1 << 17]byte +var z11664 [1 << 17]byte +var z11665 [1 << 17]byte +var z11666 [1 << 17]byte +var z11667 [1 << 17]byte +var z11668 [1 << 17]byte +var z11669 [1 << 17]byte +var z11670 [1 << 17]byte +var z11671 [1 << 17]byte +var z11672 [1 << 17]byte +var z11673 [1 << 17]byte +var z11674 [1 << 17]byte +var z11675 [1 << 17]byte +var z11676 [1 << 17]byte +var z11677 [1 << 17]byte +var z11678 [1 << 17]byte +var z11679 [1 << 17]byte +var z11680 [1 << 17]byte +var z11681 [1 << 17]byte +var z11682 [1 << 17]byte +var z11683 [1 << 17]byte +var z11684 [1 << 17]byte +var z11685 [1 << 17]byte +var z11686 [1 << 17]byte +var z11687 [1 << 17]byte +var z11688 [1 << 17]byte +var z11689 [1 << 17]byte +var z11690 [1 << 17]byte +var z11691 [1 << 17]byte +var z11692 [1 << 17]byte +var z11693 [1 << 17]byte +var z11694 [1 << 17]byte +var z11695 [1 << 17]byte +var z11696 [1 << 17]byte +var z11697 [1 << 17]byte +var z11698 [1 << 17]byte +var z11699 [1 << 17]byte +var z11700 [1 << 17]byte +var z11701 [1 << 17]byte +var z11702 [1 << 17]byte +var z11703 [1 << 17]byte +var z11704 [1 << 17]byte +var z11705 [1 << 17]byte +var z11706 [1 << 17]byte +var z11707 [1 << 17]byte +var z11708 [1 << 17]byte +var z11709 [1 << 17]byte +var z11710 [1 << 17]byte +var z11711 [1 << 17]byte +var z11712 [1 << 17]byte +var z11713 [1 << 17]byte +var z11714 [1 << 17]byte +var z11715 [1 << 17]byte +var z11716 [1 << 17]byte +var z11717 [1 << 17]byte +var z11718 [1 << 17]byte +var z11719 [1 << 17]byte +var z11720 [1 << 17]byte +var z11721 [1 << 17]byte +var z11722 [1 << 17]byte +var z11723 [1 << 17]byte +var z11724 [1 << 17]byte +var z11725 [1 << 17]byte +var z11726 [1 << 17]byte +var z11727 [1 << 17]byte +var z11728 [1 << 17]byte +var z11729 [1 << 17]byte +var z11730 [1 << 17]byte +var z11731 [1 << 17]byte +var z11732 [1 << 17]byte +var z11733 [1 << 17]byte +var z11734 [1 << 17]byte +var z11735 [1 << 17]byte +var z11736 [1 << 17]byte +var z11737 [1 << 17]byte +var z11738 [1 << 17]byte +var z11739 [1 << 17]byte +var z11740 [1 << 17]byte +var z11741 [1 << 17]byte +var z11742 [1 << 17]byte +var z11743 [1 << 17]byte +var z11744 [1 << 17]byte +var z11745 [1 << 17]byte +var z11746 [1 << 17]byte +var z11747 [1 << 17]byte +var z11748 [1 << 17]byte +var z11749 [1 << 17]byte +var z11750 [1 << 17]byte +var z11751 [1 << 17]byte +var z11752 [1 << 17]byte +var z11753 [1 << 17]byte +var z11754 [1 << 17]byte +var z11755 [1 << 17]byte +var z11756 [1 << 17]byte +var z11757 [1 << 17]byte +var z11758 [1 << 17]byte +var z11759 [1 << 17]byte +var z11760 [1 << 17]byte +var z11761 [1 << 17]byte +var z11762 [1 << 17]byte +var z11763 [1 << 17]byte +var z11764 [1 << 17]byte +var z11765 [1 << 17]byte +var z11766 [1 << 17]byte +var z11767 [1 << 17]byte +var z11768 [1 << 17]byte +var z11769 [1 << 17]byte +var z11770 [1 << 17]byte +var z11771 [1 << 17]byte +var z11772 [1 << 17]byte +var z11773 [1 << 17]byte +var z11774 [1 << 17]byte +var z11775 [1 << 17]byte +var z11776 [1 << 17]byte +var z11777 [1 << 17]byte +var z11778 [1 << 17]byte +var z11779 [1 << 17]byte +var z11780 [1 << 17]byte +var z11781 [1 << 17]byte +var z11782 [1 << 17]byte +var z11783 [1 << 17]byte +var z11784 [1 << 17]byte +var z11785 [1 << 17]byte +var z11786 [1 << 17]byte +var z11787 [1 << 17]byte +var z11788 [1 << 17]byte +var z11789 [1 << 17]byte +var z11790 [1 << 17]byte +var z11791 [1 << 17]byte +var z11792 [1 << 17]byte +var z11793 [1 << 17]byte +var z11794 [1 << 17]byte +var z11795 [1 << 17]byte +var z11796 [1 << 17]byte +var z11797 [1 << 17]byte +var z11798 [1 << 17]byte +var z11799 [1 << 17]byte +var z11800 [1 << 17]byte +var z11801 [1 << 17]byte +var z11802 [1 << 17]byte +var z11803 [1 << 17]byte +var z11804 [1 << 17]byte +var z11805 [1 << 17]byte +var z11806 [1 << 17]byte +var z11807 [1 << 17]byte +var z11808 [1 << 17]byte +var z11809 [1 << 17]byte +var z11810 [1 << 17]byte +var z11811 [1 << 17]byte +var z11812 [1 << 17]byte +var z11813 [1 << 17]byte +var z11814 [1 << 17]byte +var z11815 [1 << 17]byte +var z11816 [1 << 17]byte +var z11817 [1 << 17]byte +var z11818 [1 << 17]byte +var z11819 [1 << 17]byte +var z11820 [1 << 17]byte +var z11821 [1 << 17]byte +var z11822 [1 << 17]byte +var z11823 [1 << 17]byte +var z11824 [1 << 17]byte +var z11825 [1 << 17]byte +var z11826 [1 << 17]byte +var z11827 [1 << 17]byte +var z11828 [1 << 17]byte +var z11829 [1 << 17]byte +var z11830 [1 << 17]byte +var z11831 [1 << 17]byte +var z11832 [1 << 17]byte +var z11833 [1 << 17]byte +var z11834 [1 << 17]byte +var z11835 [1 << 17]byte +var z11836 [1 << 17]byte +var z11837 [1 << 17]byte +var z11838 [1 << 17]byte +var z11839 [1 << 17]byte +var z11840 [1 << 17]byte +var z11841 [1 << 17]byte +var z11842 [1 << 17]byte +var z11843 [1 << 17]byte +var z11844 [1 << 17]byte +var z11845 [1 << 17]byte +var z11846 [1 << 17]byte +var z11847 [1 << 17]byte +var z11848 [1 << 17]byte +var z11849 [1 << 17]byte +var z11850 [1 << 17]byte +var z11851 [1 << 17]byte +var z11852 [1 << 17]byte +var z11853 [1 << 17]byte +var z11854 [1 << 17]byte +var z11855 [1 << 17]byte +var z11856 [1 << 17]byte +var z11857 [1 << 17]byte +var z11858 [1 << 17]byte +var z11859 [1 << 17]byte +var z11860 [1 << 17]byte +var z11861 [1 << 17]byte +var z11862 [1 << 17]byte +var z11863 [1 << 17]byte +var z11864 [1 << 17]byte +var z11865 [1 << 17]byte +var z11866 [1 << 17]byte +var z11867 [1 << 17]byte +var z11868 [1 << 17]byte +var z11869 [1 << 17]byte +var z11870 [1 << 17]byte +var z11871 [1 << 17]byte +var z11872 [1 << 17]byte +var z11873 [1 << 17]byte +var z11874 [1 << 17]byte +var z11875 [1 << 17]byte +var z11876 [1 << 17]byte +var z11877 [1 << 17]byte +var z11878 [1 << 17]byte +var z11879 [1 << 17]byte +var z11880 [1 << 17]byte +var z11881 [1 << 17]byte +var z11882 [1 << 17]byte +var z11883 [1 << 17]byte +var z11884 [1 << 17]byte +var z11885 [1 << 17]byte +var z11886 [1 << 17]byte +var z11887 [1 << 17]byte +var z11888 [1 << 17]byte +var z11889 [1 << 17]byte +var z11890 [1 << 17]byte +var z11891 [1 << 17]byte +var z11892 [1 << 17]byte +var z11893 [1 << 17]byte +var z11894 [1 << 17]byte +var z11895 [1 << 17]byte +var z11896 [1 << 17]byte +var z11897 [1 << 17]byte +var z11898 [1 << 17]byte +var z11899 [1 << 17]byte +var z11900 [1 << 17]byte +var z11901 [1 << 17]byte +var z11902 [1 << 17]byte +var z11903 [1 << 17]byte +var z11904 [1 << 17]byte +var z11905 [1 << 17]byte +var z11906 [1 << 17]byte +var z11907 [1 << 17]byte +var z11908 [1 << 17]byte +var z11909 [1 << 17]byte +var z11910 [1 << 17]byte +var z11911 [1 << 17]byte +var z11912 [1 << 17]byte +var z11913 [1 << 17]byte +var z11914 [1 << 17]byte +var z11915 [1 << 17]byte +var z11916 [1 << 17]byte +var z11917 [1 << 17]byte +var z11918 [1 << 17]byte +var z11919 [1 << 17]byte +var z11920 [1 << 17]byte +var z11921 [1 << 17]byte +var z11922 [1 << 17]byte +var z11923 [1 << 17]byte +var z11924 [1 << 17]byte +var z11925 [1 << 17]byte +var z11926 [1 << 17]byte +var z11927 [1 << 17]byte +var z11928 [1 << 17]byte +var z11929 [1 << 17]byte +var z11930 [1 << 17]byte +var z11931 [1 << 17]byte +var z11932 [1 << 17]byte +var z11933 [1 << 17]byte +var z11934 [1 << 17]byte +var z11935 [1 << 17]byte +var z11936 [1 << 17]byte +var z11937 [1 << 17]byte +var z11938 [1 << 17]byte +var z11939 [1 << 17]byte +var z11940 [1 << 17]byte +var z11941 [1 << 17]byte +var z11942 [1 << 17]byte +var z11943 [1 << 17]byte +var z11944 [1 << 17]byte +var z11945 [1 << 17]byte +var z11946 [1 << 17]byte +var z11947 [1 << 17]byte +var z11948 [1 << 17]byte +var z11949 [1 << 17]byte +var z11950 [1 << 17]byte +var z11951 [1 << 17]byte +var z11952 [1 << 17]byte +var z11953 [1 << 17]byte +var z11954 [1 << 17]byte +var z11955 [1 << 17]byte +var z11956 [1 << 17]byte +var z11957 [1 << 17]byte +var z11958 [1 << 17]byte +var z11959 [1 << 17]byte +var z11960 [1 << 17]byte +var z11961 [1 << 17]byte +var z11962 [1 << 17]byte +var z11963 [1 << 17]byte +var z11964 [1 << 17]byte +var z11965 [1 << 17]byte +var z11966 [1 << 17]byte +var z11967 [1 << 17]byte +var z11968 [1 << 17]byte +var z11969 [1 << 17]byte +var z11970 [1 << 17]byte +var z11971 [1 << 17]byte +var z11972 [1 << 17]byte +var z11973 [1 << 17]byte +var z11974 [1 << 17]byte +var z11975 [1 << 17]byte +var z11976 [1 << 17]byte +var z11977 [1 << 17]byte +var z11978 [1 << 17]byte +var z11979 [1 << 17]byte +var z11980 [1 << 17]byte +var z11981 [1 << 17]byte +var z11982 [1 << 17]byte +var z11983 [1 << 17]byte +var z11984 [1 << 17]byte +var z11985 [1 << 17]byte +var z11986 [1 << 17]byte +var z11987 [1 << 17]byte +var z11988 [1 << 17]byte +var z11989 [1 << 17]byte +var z11990 [1 << 17]byte +var z11991 [1 << 17]byte +var z11992 [1 << 17]byte +var z11993 [1 << 17]byte +var z11994 [1 << 17]byte +var z11995 [1 << 17]byte +var z11996 [1 << 17]byte +var z11997 [1 << 17]byte +var z11998 [1 << 17]byte +var z11999 [1 << 17]byte +var z12000 [1 << 17]byte +var z12001 [1 << 17]byte +var z12002 [1 << 17]byte +var z12003 [1 << 17]byte +var z12004 [1 << 17]byte +var z12005 [1 << 17]byte +var z12006 [1 << 17]byte +var z12007 [1 << 17]byte +var z12008 [1 << 17]byte +var z12009 [1 << 17]byte +var z12010 [1 << 17]byte +var z12011 [1 << 17]byte +var z12012 [1 << 17]byte +var z12013 [1 << 17]byte +var z12014 [1 << 17]byte +var z12015 [1 << 17]byte +var z12016 [1 << 17]byte +var z12017 [1 << 17]byte +var z12018 [1 << 17]byte +var z12019 [1 << 17]byte +var z12020 [1 << 17]byte +var z12021 [1 << 17]byte +var z12022 [1 << 17]byte +var z12023 [1 << 17]byte +var z12024 [1 << 17]byte +var z12025 [1 << 17]byte +var z12026 [1 << 17]byte +var z12027 [1 << 17]byte +var z12028 [1 << 17]byte +var z12029 [1 << 17]byte +var z12030 [1 << 17]byte +var z12031 [1 << 17]byte +var z12032 [1 << 17]byte +var z12033 [1 << 17]byte +var z12034 [1 << 17]byte +var z12035 [1 << 17]byte +var z12036 [1 << 17]byte +var z12037 [1 << 17]byte +var z12038 [1 << 17]byte +var z12039 [1 << 17]byte +var z12040 [1 << 17]byte +var z12041 [1 << 17]byte +var z12042 [1 << 17]byte +var z12043 [1 << 17]byte +var z12044 [1 << 17]byte +var z12045 [1 << 17]byte +var z12046 [1 << 17]byte +var z12047 [1 << 17]byte +var z12048 [1 << 17]byte +var z12049 [1 << 17]byte +var z12050 [1 << 17]byte +var z12051 [1 << 17]byte +var z12052 [1 << 17]byte +var z12053 [1 << 17]byte +var z12054 [1 << 17]byte +var z12055 [1 << 17]byte +var z12056 [1 << 17]byte +var z12057 [1 << 17]byte +var z12058 [1 << 17]byte +var z12059 [1 << 17]byte +var z12060 [1 << 17]byte +var z12061 [1 << 17]byte +var z12062 [1 << 17]byte +var z12063 [1 << 17]byte +var z12064 [1 << 17]byte +var z12065 [1 << 17]byte +var z12066 [1 << 17]byte +var z12067 [1 << 17]byte +var z12068 [1 << 17]byte +var z12069 [1 << 17]byte +var z12070 [1 << 17]byte +var z12071 [1 << 17]byte +var z12072 [1 << 17]byte +var z12073 [1 << 17]byte +var z12074 [1 << 17]byte +var z12075 [1 << 17]byte +var z12076 [1 << 17]byte +var z12077 [1 << 17]byte +var z12078 [1 << 17]byte +var z12079 [1 << 17]byte +var z12080 [1 << 17]byte +var z12081 [1 << 17]byte +var z12082 [1 << 17]byte +var z12083 [1 << 17]byte +var z12084 [1 << 17]byte +var z12085 [1 << 17]byte +var z12086 [1 << 17]byte +var z12087 [1 << 17]byte +var z12088 [1 << 17]byte +var z12089 [1 << 17]byte +var z12090 [1 << 17]byte +var z12091 [1 << 17]byte +var z12092 [1 << 17]byte +var z12093 [1 << 17]byte +var z12094 [1 << 17]byte +var z12095 [1 << 17]byte +var z12096 [1 << 17]byte +var z12097 [1 << 17]byte +var z12098 [1 << 17]byte +var z12099 [1 << 17]byte +var z12100 [1 << 17]byte +var z12101 [1 << 17]byte +var z12102 [1 << 17]byte +var z12103 [1 << 17]byte +var z12104 [1 << 17]byte +var z12105 [1 << 17]byte +var z12106 [1 << 17]byte +var z12107 [1 << 17]byte +var z12108 [1 << 17]byte +var z12109 [1 << 17]byte +var z12110 [1 << 17]byte +var z12111 [1 << 17]byte +var z12112 [1 << 17]byte +var z12113 [1 << 17]byte +var z12114 [1 << 17]byte +var z12115 [1 << 17]byte +var z12116 [1 << 17]byte +var z12117 [1 << 17]byte +var z12118 [1 << 17]byte +var z12119 [1 << 17]byte +var z12120 [1 << 17]byte +var z12121 [1 << 17]byte +var z12122 [1 << 17]byte +var z12123 [1 << 17]byte +var z12124 [1 << 17]byte +var z12125 [1 << 17]byte +var z12126 [1 << 17]byte +var z12127 [1 << 17]byte +var z12128 [1 << 17]byte +var z12129 [1 << 17]byte +var z12130 [1 << 17]byte +var z12131 [1 << 17]byte +var z12132 [1 << 17]byte +var z12133 [1 << 17]byte +var z12134 [1 << 17]byte +var z12135 [1 << 17]byte +var z12136 [1 << 17]byte +var z12137 [1 << 17]byte +var z12138 [1 << 17]byte +var z12139 [1 << 17]byte +var z12140 [1 << 17]byte +var z12141 [1 << 17]byte +var z12142 [1 << 17]byte +var z12143 [1 << 17]byte +var z12144 [1 << 17]byte +var z12145 [1 << 17]byte +var z12146 [1 << 17]byte +var z12147 [1 << 17]byte +var z12148 [1 << 17]byte +var z12149 [1 << 17]byte +var z12150 [1 << 17]byte +var z12151 [1 << 17]byte +var z12152 [1 << 17]byte +var z12153 [1 << 17]byte +var z12154 [1 << 17]byte +var z12155 [1 << 17]byte +var z12156 [1 << 17]byte +var z12157 [1 << 17]byte +var z12158 [1 << 17]byte +var z12159 [1 << 17]byte +var z12160 [1 << 17]byte +var z12161 [1 << 17]byte +var z12162 [1 << 17]byte +var z12163 [1 << 17]byte +var z12164 [1 << 17]byte +var z12165 [1 << 17]byte +var z12166 [1 << 17]byte +var z12167 [1 << 17]byte +var z12168 [1 << 17]byte +var z12169 [1 << 17]byte +var z12170 [1 << 17]byte +var z12171 [1 << 17]byte +var z12172 [1 << 17]byte +var z12173 [1 << 17]byte +var z12174 [1 << 17]byte +var z12175 [1 << 17]byte +var z12176 [1 << 17]byte +var z12177 [1 << 17]byte +var z12178 [1 << 17]byte +var z12179 [1 << 17]byte +var z12180 [1 << 17]byte +var z12181 [1 << 17]byte +var z12182 [1 << 17]byte +var z12183 [1 << 17]byte +var z12184 [1 << 17]byte +var z12185 [1 << 17]byte +var z12186 [1 << 17]byte +var z12187 [1 << 17]byte +var z12188 [1 << 17]byte +var z12189 [1 << 17]byte +var z12190 [1 << 17]byte +var z12191 [1 << 17]byte +var z12192 [1 << 17]byte +var z12193 [1 << 17]byte +var z12194 [1 << 17]byte +var z12195 [1 << 17]byte +var z12196 [1 << 17]byte +var z12197 [1 << 17]byte +var z12198 [1 << 17]byte +var z12199 [1 << 17]byte +var z12200 [1 << 17]byte +var z12201 [1 << 17]byte +var z12202 [1 << 17]byte +var z12203 [1 << 17]byte +var z12204 [1 << 17]byte +var z12205 [1 << 17]byte +var z12206 [1 << 17]byte +var z12207 [1 << 17]byte +var z12208 [1 << 17]byte +var z12209 [1 << 17]byte +var z12210 [1 << 17]byte +var z12211 [1 << 17]byte +var z12212 [1 << 17]byte +var z12213 [1 << 17]byte +var z12214 [1 << 17]byte +var z12215 [1 << 17]byte +var z12216 [1 << 17]byte +var z12217 [1 << 17]byte +var z12218 [1 << 17]byte +var z12219 [1 << 17]byte +var z12220 [1 << 17]byte +var z12221 [1 << 17]byte +var z12222 [1 << 17]byte +var z12223 [1 << 17]byte +var z12224 [1 << 17]byte +var z12225 [1 << 17]byte +var z12226 [1 << 17]byte +var z12227 [1 << 17]byte +var z12228 [1 << 17]byte +var z12229 [1 << 17]byte +var z12230 [1 << 17]byte +var z12231 [1 << 17]byte +var z12232 [1 << 17]byte +var z12233 [1 << 17]byte +var z12234 [1 << 17]byte +var z12235 [1 << 17]byte +var z12236 [1 << 17]byte +var z12237 [1 << 17]byte +var z12238 [1 << 17]byte +var z12239 [1 << 17]byte +var z12240 [1 << 17]byte +var z12241 [1 << 17]byte +var z12242 [1 << 17]byte +var z12243 [1 << 17]byte +var z12244 [1 << 17]byte +var z12245 [1 << 17]byte +var z12246 [1 << 17]byte +var z12247 [1 << 17]byte +var z12248 [1 << 17]byte +var z12249 [1 << 17]byte +var z12250 [1 << 17]byte +var z12251 [1 << 17]byte +var z12252 [1 << 17]byte +var z12253 [1 << 17]byte +var z12254 [1 << 17]byte +var z12255 [1 << 17]byte +var z12256 [1 << 17]byte +var z12257 [1 << 17]byte +var z12258 [1 << 17]byte +var z12259 [1 << 17]byte +var z12260 [1 << 17]byte +var z12261 [1 << 17]byte +var z12262 [1 << 17]byte +var z12263 [1 << 17]byte +var z12264 [1 << 17]byte +var z12265 [1 << 17]byte +var z12266 [1 << 17]byte +var z12267 [1 << 17]byte +var z12268 [1 << 17]byte +var z12269 [1 << 17]byte +var z12270 [1 << 17]byte +var z12271 [1 << 17]byte +var z12272 [1 << 17]byte +var z12273 [1 << 17]byte +var z12274 [1 << 17]byte +var z12275 [1 << 17]byte +var z12276 [1 << 17]byte +var z12277 [1 << 17]byte +var z12278 [1 << 17]byte +var z12279 [1 << 17]byte +var z12280 [1 << 17]byte +var z12281 [1 << 17]byte +var z12282 [1 << 17]byte +var z12283 [1 << 17]byte +var z12284 [1 << 17]byte +var z12285 [1 << 17]byte +var z12286 [1 << 17]byte +var z12287 [1 << 17]byte +var z12288 [1 << 17]byte +var z12289 [1 << 17]byte +var z12290 [1 << 17]byte +var z12291 [1 << 17]byte +var z12292 [1 << 17]byte +var z12293 [1 << 17]byte +var z12294 [1 << 17]byte +var z12295 [1 << 17]byte +var z12296 [1 << 17]byte +var z12297 [1 << 17]byte +var z12298 [1 << 17]byte +var z12299 [1 << 17]byte +var z12300 [1 << 17]byte +var z12301 [1 << 17]byte +var z12302 [1 << 17]byte +var z12303 [1 << 17]byte +var z12304 [1 << 17]byte +var z12305 [1 << 17]byte +var z12306 [1 << 17]byte +var z12307 [1 << 17]byte +var z12308 [1 << 17]byte +var z12309 [1 << 17]byte +var z12310 [1 << 17]byte +var z12311 [1 << 17]byte +var z12312 [1 << 17]byte +var z12313 [1 << 17]byte +var z12314 [1 << 17]byte +var z12315 [1 << 17]byte +var z12316 [1 << 17]byte +var z12317 [1 << 17]byte +var z12318 [1 << 17]byte +var z12319 [1 << 17]byte +var z12320 [1 << 17]byte +var z12321 [1 << 17]byte +var z12322 [1 << 17]byte +var z12323 [1 << 17]byte +var z12324 [1 << 17]byte +var z12325 [1 << 17]byte +var z12326 [1 << 17]byte +var z12327 [1 << 17]byte +var z12328 [1 << 17]byte +var z12329 [1 << 17]byte +var z12330 [1 << 17]byte +var z12331 [1 << 17]byte +var z12332 [1 << 17]byte +var z12333 [1 << 17]byte +var z12334 [1 << 17]byte +var z12335 [1 << 17]byte +var z12336 [1 << 17]byte +var z12337 [1 << 17]byte +var z12338 [1 << 17]byte +var z12339 [1 << 17]byte +var z12340 [1 << 17]byte +var z12341 [1 << 17]byte +var z12342 [1 << 17]byte +var z12343 [1 << 17]byte +var z12344 [1 << 17]byte +var z12345 [1 << 17]byte +var z12346 [1 << 17]byte +var z12347 [1 << 17]byte +var z12348 [1 << 17]byte +var z12349 [1 << 17]byte +var z12350 [1 << 17]byte +var z12351 [1 << 17]byte +var z12352 [1 << 17]byte +var z12353 [1 << 17]byte +var z12354 [1 << 17]byte +var z12355 [1 << 17]byte +var z12356 [1 << 17]byte +var z12357 [1 << 17]byte +var z12358 [1 << 17]byte +var z12359 [1 << 17]byte +var z12360 [1 << 17]byte +var z12361 [1 << 17]byte +var z12362 [1 << 17]byte +var z12363 [1 << 17]byte +var z12364 [1 << 17]byte +var z12365 [1 << 17]byte +var z12366 [1 << 17]byte +var z12367 [1 << 17]byte +var z12368 [1 << 17]byte +var z12369 [1 << 17]byte +var z12370 [1 << 17]byte +var z12371 [1 << 17]byte +var z12372 [1 << 17]byte +var z12373 [1 << 17]byte +var z12374 [1 << 17]byte +var z12375 [1 << 17]byte +var z12376 [1 << 17]byte +var z12377 [1 << 17]byte +var z12378 [1 << 17]byte +var z12379 [1 << 17]byte +var z12380 [1 << 17]byte +var z12381 [1 << 17]byte +var z12382 [1 << 17]byte +var z12383 [1 << 17]byte +var z12384 [1 << 17]byte +var z12385 [1 << 17]byte +var z12386 [1 << 17]byte +var z12387 [1 << 17]byte +var z12388 [1 << 17]byte +var z12389 [1 << 17]byte +var z12390 [1 << 17]byte +var z12391 [1 << 17]byte +var z12392 [1 << 17]byte +var z12393 [1 << 17]byte +var z12394 [1 << 17]byte +var z12395 [1 << 17]byte +var z12396 [1 << 17]byte +var z12397 [1 << 17]byte +var z12398 [1 << 17]byte +var z12399 [1 << 17]byte +var z12400 [1 << 17]byte +var z12401 [1 << 17]byte +var z12402 [1 << 17]byte +var z12403 [1 << 17]byte +var z12404 [1 << 17]byte +var z12405 [1 << 17]byte +var z12406 [1 << 17]byte +var z12407 [1 << 17]byte +var z12408 [1 << 17]byte +var z12409 [1 << 17]byte +var z12410 [1 << 17]byte +var z12411 [1 << 17]byte +var z12412 [1 << 17]byte +var z12413 [1 << 17]byte +var z12414 [1 << 17]byte +var z12415 [1 << 17]byte +var z12416 [1 << 17]byte +var z12417 [1 << 17]byte +var z12418 [1 << 17]byte +var z12419 [1 << 17]byte +var z12420 [1 << 17]byte +var z12421 [1 << 17]byte +var z12422 [1 << 17]byte +var z12423 [1 << 17]byte +var z12424 [1 << 17]byte +var z12425 [1 << 17]byte +var z12426 [1 << 17]byte +var z12427 [1 << 17]byte +var z12428 [1 << 17]byte +var z12429 [1 << 17]byte +var z12430 [1 << 17]byte +var z12431 [1 << 17]byte +var z12432 [1 << 17]byte +var z12433 [1 << 17]byte +var z12434 [1 << 17]byte +var z12435 [1 << 17]byte +var z12436 [1 << 17]byte +var z12437 [1 << 17]byte +var z12438 [1 << 17]byte +var z12439 [1 << 17]byte +var z12440 [1 << 17]byte +var z12441 [1 << 17]byte +var z12442 [1 << 17]byte +var z12443 [1 << 17]byte +var z12444 [1 << 17]byte +var z12445 [1 << 17]byte +var z12446 [1 << 17]byte +var z12447 [1 << 17]byte +var z12448 [1 << 17]byte +var z12449 [1 << 17]byte +var z12450 [1 << 17]byte +var z12451 [1 << 17]byte +var z12452 [1 << 17]byte +var z12453 [1 << 17]byte +var z12454 [1 << 17]byte +var z12455 [1 << 17]byte +var z12456 [1 << 17]byte +var z12457 [1 << 17]byte +var z12458 [1 << 17]byte +var z12459 [1 << 17]byte +var z12460 [1 << 17]byte +var z12461 [1 << 17]byte +var z12462 [1 << 17]byte +var z12463 [1 << 17]byte +var z12464 [1 << 17]byte +var z12465 [1 << 17]byte +var z12466 [1 << 17]byte +var z12467 [1 << 17]byte +var z12468 [1 << 17]byte +var z12469 [1 << 17]byte +var z12470 [1 << 17]byte +var z12471 [1 << 17]byte +var z12472 [1 << 17]byte +var z12473 [1 << 17]byte +var z12474 [1 << 17]byte +var z12475 [1 << 17]byte +var z12476 [1 << 17]byte +var z12477 [1 << 17]byte +var z12478 [1 << 17]byte +var z12479 [1 << 17]byte +var z12480 [1 << 17]byte +var z12481 [1 << 17]byte +var z12482 [1 << 17]byte +var z12483 [1 << 17]byte +var z12484 [1 << 17]byte +var z12485 [1 << 17]byte +var z12486 [1 << 17]byte +var z12487 [1 << 17]byte +var z12488 [1 << 17]byte +var z12489 [1 << 17]byte +var z12490 [1 << 17]byte +var z12491 [1 << 17]byte +var z12492 [1 << 17]byte +var z12493 [1 << 17]byte +var z12494 [1 << 17]byte +var z12495 [1 << 17]byte +var z12496 [1 << 17]byte +var z12497 [1 << 17]byte +var z12498 [1 << 17]byte +var z12499 [1 << 17]byte +var z12500 [1 << 17]byte +var z12501 [1 << 17]byte +var z12502 [1 << 17]byte +var z12503 [1 << 17]byte +var z12504 [1 << 17]byte +var z12505 [1 << 17]byte +var z12506 [1 << 17]byte +var z12507 [1 << 17]byte +var z12508 [1 << 17]byte +var z12509 [1 << 17]byte +var z12510 [1 << 17]byte +var z12511 [1 << 17]byte +var z12512 [1 << 17]byte +var z12513 [1 << 17]byte +var z12514 [1 << 17]byte +var z12515 [1 << 17]byte +var z12516 [1 << 17]byte +var z12517 [1 << 17]byte +var z12518 [1 << 17]byte +var z12519 [1 << 17]byte +var z12520 [1 << 17]byte +var z12521 [1 << 17]byte +var z12522 [1 << 17]byte +var z12523 [1 << 17]byte +var z12524 [1 << 17]byte +var z12525 [1 << 17]byte +var z12526 [1 << 17]byte +var z12527 [1 << 17]byte +var z12528 [1 << 17]byte +var z12529 [1 << 17]byte +var z12530 [1 << 17]byte +var z12531 [1 << 17]byte +var z12532 [1 << 17]byte +var z12533 [1 << 17]byte +var z12534 [1 << 17]byte +var z12535 [1 << 17]byte +var z12536 [1 << 17]byte +var z12537 [1 << 17]byte +var z12538 [1 << 17]byte +var z12539 [1 << 17]byte +var z12540 [1 << 17]byte +var z12541 [1 << 17]byte +var z12542 [1 << 17]byte +var z12543 [1 << 17]byte +var z12544 [1 << 17]byte +var z12545 [1 << 17]byte +var z12546 [1 << 17]byte +var z12547 [1 << 17]byte +var z12548 [1 << 17]byte +var z12549 [1 << 17]byte +var z12550 [1 << 17]byte +var z12551 [1 << 17]byte +var z12552 [1 << 17]byte +var z12553 [1 << 17]byte +var z12554 [1 << 17]byte +var z12555 [1 << 17]byte +var z12556 [1 << 17]byte +var z12557 [1 << 17]byte +var z12558 [1 << 17]byte +var z12559 [1 << 17]byte +var z12560 [1 << 17]byte +var z12561 [1 << 17]byte +var z12562 [1 << 17]byte +var z12563 [1 << 17]byte +var z12564 [1 << 17]byte +var z12565 [1 << 17]byte +var z12566 [1 << 17]byte +var z12567 [1 << 17]byte +var z12568 [1 << 17]byte +var z12569 [1 << 17]byte +var z12570 [1 << 17]byte +var z12571 [1 << 17]byte +var z12572 [1 << 17]byte +var z12573 [1 << 17]byte +var z12574 [1 << 17]byte +var z12575 [1 << 17]byte +var z12576 [1 << 17]byte +var z12577 [1 << 17]byte +var z12578 [1 << 17]byte +var z12579 [1 << 17]byte +var z12580 [1 << 17]byte +var z12581 [1 << 17]byte +var z12582 [1 << 17]byte +var z12583 [1 << 17]byte +var z12584 [1 << 17]byte +var z12585 [1 << 17]byte +var z12586 [1 << 17]byte +var z12587 [1 << 17]byte +var z12588 [1 << 17]byte +var z12589 [1 << 17]byte +var z12590 [1 << 17]byte +var z12591 [1 << 17]byte +var z12592 [1 << 17]byte +var z12593 [1 << 17]byte +var z12594 [1 << 17]byte +var z12595 [1 << 17]byte +var z12596 [1 << 17]byte +var z12597 [1 << 17]byte +var z12598 [1 << 17]byte +var z12599 [1 << 17]byte +var z12600 [1 << 17]byte +var z12601 [1 << 17]byte +var z12602 [1 << 17]byte +var z12603 [1 << 17]byte +var z12604 [1 << 17]byte +var z12605 [1 << 17]byte +var z12606 [1 << 17]byte +var z12607 [1 << 17]byte +var z12608 [1 << 17]byte +var z12609 [1 << 17]byte +var z12610 [1 << 17]byte +var z12611 [1 << 17]byte +var z12612 [1 << 17]byte +var z12613 [1 << 17]byte +var z12614 [1 << 17]byte +var z12615 [1 << 17]byte +var z12616 [1 << 17]byte +var z12617 [1 << 17]byte +var z12618 [1 << 17]byte +var z12619 [1 << 17]byte +var z12620 [1 << 17]byte +var z12621 [1 << 17]byte +var z12622 [1 << 17]byte +var z12623 [1 << 17]byte +var z12624 [1 << 17]byte +var z12625 [1 << 17]byte +var z12626 [1 << 17]byte +var z12627 [1 << 17]byte +var z12628 [1 << 17]byte +var z12629 [1 << 17]byte +var z12630 [1 << 17]byte +var z12631 [1 << 17]byte +var z12632 [1 << 17]byte +var z12633 [1 << 17]byte +var z12634 [1 << 17]byte +var z12635 [1 << 17]byte +var z12636 [1 << 17]byte +var z12637 [1 << 17]byte +var z12638 [1 << 17]byte +var z12639 [1 << 17]byte +var z12640 [1 << 17]byte +var z12641 [1 << 17]byte +var z12642 [1 << 17]byte +var z12643 [1 << 17]byte +var z12644 [1 << 17]byte +var z12645 [1 << 17]byte +var z12646 [1 << 17]byte +var z12647 [1 << 17]byte +var z12648 [1 << 17]byte +var z12649 [1 << 17]byte +var z12650 [1 << 17]byte +var z12651 [1 << 17]byte +var z12652 [1 << 17]byte +var z12653 [1 << 17]byte +var z12654 [1 << 17]byte +var z12655 [1 << 17]byte +var z12656 [1 << 17]byte +var z12657 [1 << 17]byte +var z12658 [1 << 17]byte +var z12659 [1 << 17]byte +var z12660 [1 << 17]byte +var z12661 [1 << 17]byte +var z12662 [1 << 17]byte +var z12663 [1 << 17]byte +var z12664 [1 << 17]byte +var z12665 [1 << 17]byte +var z12666 [1 << 17]byte +var z12667 [1 << 17]byte +var z12668 [1 << 17]byte +var z12669 [1 << 17]byte +var z12670 [1 << 17]byte +var z12671 [1 << 17]byte +var z12672 [1 << 17]byte +var z12673 [1 << 17]byte +var z12674 [1 << 17]byte +var z12675 [1 << 17]byte +var z12676 [1 << 17]byte +var z12677 [1 << 17]byte +var z12678 [1 << 17]byte +var z12679 [1 << 17]byte +var z12680 [1 << 17]byte +var z12681 [1 << 17]byte +var z12682 [1 << 17]byte +var z12683 [1 << 17]byte +var z12684 [1 << 17]byte +var z12685 [1 << 17]byte +var z12686 [1 << 17]byte +var z12687 [1 << 17]byte +var z12688 [1 << 17]byte +var z12689 [1 << 17]byte +var z12690 [1 << 17]byte +var z12691 [1 << 17]byte +var z12692 [1 << 17]byte +var z12693 [1 << 17]byte +var z12694 [1 << 17]byte +var z12695 [1 << 17]byte +var z12696 [1 << 17]byte +var z12697 [1 << 17]byte +var z12698 [1 << 17]byte +var z12699 [1 << 17]byte +var z12700 [1 << 17]byte +var z12701 [1 << 17]byte +var z12702 [1 << 17]byte +var z12703 [1 << 17]byte +var z12704 [1 << 17]byte +var z12705 [1 << 17]byte +var z12706 [1 << 17]byte +var z12707 [1 << 17]byte +var z12708 [1 << 17]byte +var z12709 [1 << 17]byte +var z12710 [1 << 17]byte +var z12711 [1 << 17]byte +var z12712 [1 << 17]byte +var z12713 [1 << 17]byte +var z12714 [1 << 17]byte +var z12715 [1 << 17]byte +var z12716 [1 << 17]byte +var z12717 [1 << 17]byte +var z12718 [1 << 17]byte +var z12719 [1 << 17]byte +var z12720 [1 << 17]byte +var z12721 [1 << 17]byte +var z12722 [1 << 17]byte +var z12723 [1 << 17]byte +var z12724 [1 << 17]byte +var z12725 [1 << 17]byte +var z12726 [1 << 17]byte +var z12727 [1 << 17]byte +var z12728 [1 << 17]byte +var z12729 [1 << 17]byte +var z12730 [1 << 17]byte +var z12731 [1 << 17]byte +var z12732 [1 << 17]byte +var z12733 [1 << 17]byte +var z12734 [1 << 17]byte +var z12735 [1 << 17]byte +var z12736 [1 << 17]byte +var z12737 [1 << 17]byte +var z12738 [1 << 17]byte +var z12739 [1 << 17]byte +var z12740 [1 << 17]byte +var z12741 [1 << 17]byte +var z12742 [1 << 17]byte +var z12743 [1 << 17]byte +var z12744 [1 << 17]byte +var z12745 [1 << 17]byte +var z12746 [1 << 17]byte +var z12747 [1 << 17]byte +var z12748 [1 << 17]byte +var z12749 [1 << 17]byte +var z12750 [1 << 17]byte +var z12751 [1 << 17]byte +var z12752 [1 << 17]byte +var z12753 [1 << 17]byte +var z12754 [1 << 17]byte +var z12755 [1 << 17]byte +var z12756 [1 << 17]byte +var z12757 [1 << 17]byte +var z12758 [1 << 17]byte +var z12759 [1 << 17]byte +var z12760 [1 << 17]byte +var z12761 [1 << 17]byte +var z12762 [1 << 17]byte +var z12763 [1 << 17]byte +var z12764 [1 << 17]byte +var z12765 [1 << 17]byte +var z12766 [1 << 17]byte +var z12767 [1 << 17]byte +var z12768 [1 << 17]byte +var z12769 [1 << 17]byte +var z12770 [1 << 17]byte +var z12771 [1 << 17]byte +var z12772 [1 << 17]byte +var z12773 [1 << 17]byte +var z12774 [1 << 17]byte +var z12775 [1 << 17]byte +var z12776 [1 << 17]byte +var z12777 [1 << 17]byte +var z12778 [1 << 17]byte +var z12779 [1 << 17]byte +var z12780 [1 << 17]byte +var z12781 [1 << 17]byte +var z12782 [1 << 17]byte +var z12783 [1 << 17]byte +var z12784 [1 << 17]byte +var z12785 [1 << 17]byte +var z12786 [1 << 17]byte +var z12787 [1 << 17]byte +var z12788 [1 << 17]byte +var z12789 [1 << 17]byte +var z12790 [1 << 17]byte +var z12791 [1 << 17]byte +var z12792 [1 << 17]byte +var z12793 [1 << 17]byte +var z12794 [1 << 17]byte +var z12795 [1 << 17]byte +var z12796 [1 << 17]byte +var z12797 [1 << 17]byte +var z12798 [1 << 17]byte +var z12799 [1 << 17]byte +var z12800 [1 << 17]byte +var z12801 [1 << 17]byte +var z12802 [1 << 17]byte +var z12803 [1 << 17]byte +var z12804 [1 << 17]byte +var z12805 [1 << 17]byte +var z12806 [1 << 17]byte +var z12807 [1 << 17]byte +var z12808 [1 << 17]byte +var z12809 [1 << 17]byte +var z12810 [1 << 17]byte +var z12811 [1 << 17]byte +var z12812 [1 << 17]byte +var z12813 [1 << 17]byte +var z12814 [1 << 17]byte +var z12815 [1 << 17]byte +var z12816 [1 << 17]byte +var z12817 [1 << 17]byte +var z12818 [1 << 17]byte +var z12819 [1 << 17]byte +var z12820 [1 << 17]byte +var z12821 [1 << 17]byte +var z12822 [1 << 17]byte +var z12823 [1 << 17]byte +var z12824 [1 << 17]byte +var z12825 [1 << 17]byte +var z12826 [1 << 17]byte +var z12827 [1 << 17]byte +var z12828 [1 << 17]byte +var z12829 [1 << 17]byte +var z12830 [1 << 17]byte +var z12831 [1 << 17]byte +var z12832 [1 << 17]byte +var z12833 [1 << 17]byte +var z12834 [1 << 17]byte +var z12835 [1 << 17]byte +var z12836 [1 << 17]byte +var z12837 [1 << 17]byte +var z12838 [1 << 17]byte +var z12839 [1 << 17]byte +var z12840 [1 << 17]byte +var z12841 [1 << 17]byte +var z12842 [1 << 17]byte +var z12843 [1 << 17]byte +var z12844 [1 << 17]byte +var z12845 [1 << 17]byte +var z12846 [1 << 17]byte +var z12847 [1 << 17]byte +var z12848 [1 << 17]byte +var z12849 [1 << 17]byte +var z12850 [1 << 17]byte +var z12851 [1 << 17]byte +var z12852 [1 << 17]byte +var z12853 [1 << 17]byte +var z12854 [1 << 17]byte +var z12855 [1 << 17]byte +var z12856 [1 << 17]byte +var z12857 [1 << 17]byte +var z12858 [1 << 17]byte +var z12859 [1 << 17]byte +var z12860 [1 << 17]byte +var z12861 [1 << 17]byte +var z12862 [1 << 17]byte +var z12863 [1 << 17]byte +var z12864 [1 << 17]byte +var z12865 [1 << 17]byte +var z12866 [1 << 17]byte +var z12867 [1 << 17]byte +var z12868 [1 << 17]byte +var z12869 [1 << 17]byte +var z12870 [1 << 17]byte +var z12871 [1 << 17]byte +var z12872 [1 << 17]byte +var z12873 [1 << 17]byte +var z12874 [1 << 17]byte +var z12875 [1 << 17]byte +var z12876 [1 << 17]byte +var z12877 [1 << 17]byte +var z12878 [1 << 17]byte +var z12879 [1 << 17]byte +var z12880 [1 << 17]byte +var z12881 [1 << 17]byte +var z12882 [1 << 17]byte +var z12883 [1 << 17]byte +var z12884 [1 << 17]byte +var z12885 [1 << 17]byte +var z12886 [1 << 17]byte +var z12887 [1 << 17]byte +var z12888 [1 << 17]byte +var z12889 [1 << 17]byte +var z12890 [1 << 17]byte +var z12891 [1 << 17]byte +var z12892 [1 << 17]byte +var z12893 [1 << 17]byte +var z12894 [1 << 17]byte +var z12895 [1 << 17]byte +var z12896 [1 << 17]byte +var z12897 [1 << 17]byte +var z12898 [1 << 17]byte +var z12899 [1 << 17]byte +var z12900 [1 << 17]byte +var z12901 [1 << 17]byte +var z12902 [1 << 17]byte +var z12903 [1 << 17]byte +var z12904 [1 << 17]byte +var z12905 [1 << 17]byte +var z12906 [1 << 17]byte +var z12907 [1 << 17]byte +var z12908 [1 << 17]byte +var z12909 [1 << 17]byte +var z12910 [1 << 17]byte +var z12911 [1 << 17]byte +var z12912 [1 << 17]byte +var z12913 [1 << 17]byte +var z12914 [1 << 17]byte +var z12915 [1 << 17]byte +var z12916 [1 << 17]byte +var z12917 [1 << 17]byte +var z12918 [1 << 17]byte +var z12919 [1 << 17]byte +var z12920 [1 << 17]byte +var z12921 [1 << 17]byte +var z12922 [1 << 17]byte +var z12923 [1 << 17]byte +var z12924 [1 << 17]byte +var z12925 [1 << 17]byte +var z12926 [1 << 17]byte +var z12927 [1 << 17]byte +var z12928 [1 << 17]byte +var z12929 [1 << 17]byte +var z12930 [1 << 17]byte +var z12931 [1 << 17]byte +var z12932 [1 << 17]byte +var z12933 [1 << 17]byte +var z12934 [1 << 17]byte +var z12935 [1 << 17]byte +var z12936 [1 << 17]byte +var z12937 [1 << 17]byte +var z12938 [1 << 17]byte +var z12939 [1 << 17]byte +var z12940 [1 << 17]byte +var z12941 [1 << 17]byte +var z12942 [1 << 17]byte +var z12943 [1 << 17]byte +var z12944 [1 << 17]byte +var z12945 [1 << 17]byte +var z12946 [1 << 17]byte +var z12947 [1 << 17]byte +var z12948 [1 << 17]byte +var z12949 [1 << 17]byte +var z12950 [1 << 17]byte +var z12951 [1 << 17]byte +var z12952 [1 << 17]byte +var z12953 [1 << 17]byte +var z12954 [1 << 17]byte +var z12955 [1 << 17]byte +var z12956 [1 << 17]byte +var z12957 [1 << 17]byte +var z12958 [1 << 17]byte +var z12959 [1 << 17]byte +var z12960 [1 << 17]byte +var z12961 [1 << 17]byte +var z12962 [1 << 17]byte +var z12963 [1 << 17]byte +var z12964 [1 << 17]byte +var z12965 [1 << 17]byte +var z12966 [1 << 17]byte +var z12967 [1 << 17]byte +var z12968 [1 << 17]byte +var z12969 [1 << 17]byte +var z12970 [1 << 17]byte +var z12971 [1 << 17]byte +var z12972 [1 << 17]byte +var z12973 [1 << 17]byte +var z12974 [1 << 17]byte +var z12975 [1 << 17]byte +var z12976 [1 << 17]byte +var z12977 [1 << 17]byte +var z12978 [1 << 17]byte +var z12979 [1 << 17]byte +var z12980 [1 << 17]byte +var z12981 [1 << 17]byte +var z12982 [1 << 17]byte +var z12983 [1 << 17]byte +var z12984 [1 << 17]byte +var z12985 [1 << 17]byte +var z12986 [1 << 17]byte +var z12987 [1 << 17]byte +var z12988 [1 << 17]byte +var z12989 [1 << 17]byte +var z12990 [1 << 17]byte +var z12991 [1 << 17]byte +var z12992 [1 << 17]byte +var z12993 [1 << 17]byte +var z12994 [1 << 17]byte +var z12995 [1 << 17]byte +var z12996 [1 << 17]byte +var z12997 [1 << 17]byte +var z12998 [1 << 17]byte +var z12999 [1 << 17]byte +var z13000 [1 << 17]byte +var z13001 [1 << 17]byte +var z13002 [1 << 17]byte +var z13003 [1 << 17]byte +var z13004 [1 << 17]byte +var z13005 [1 << 17]byte +var z13006 [1 << 17]byte +var z13007 [1 << 17]byte +var z13008 [1 << 17]byte +var z13009 [1 << 17]byte +var z13010 [1 << 17]byte +var z13011 [1 << 17]byte +var z13012 [1 << 17]byte +var z13013 [1 << 17]byte +var z13014 [1 << 17]byte +var z13015 [1 << 17]byte +var z13016 [1 << 17]byte +var z13017 [1 << 17]byte +var z13018 [1 << 17]byte +var z13019 [1 << 17]byte +var z13020 [1 << 17]byte +var z13021 [1 << 17]byte +var z13022 [1 << 17]byte +var z13023 [1 << 17]byte +var z13024 [1 << 17]byte +var z13025 [1 << 17]byte +var z13026 [1 << 17]byte +var z13027 [1 << 17]byte +var z13028 [1 << 17]byte +var z13029 [1 << 17]byte +var z13030 [1 << 17]byte +var z13031 [1 << 17]byte +var z13032 [1 << 17]byte +var z13033 [1 << 17]byte +var z13034 [1 << 17]byte +var z13035 [1 << 17]byte +var z13036 [1 << 17]byte +var z13037 [1 << 17]byte +var z13038 [1 << 17]byte +var z13039 [1 << 17]byte +var z13040 [1 << 17]byte +var z13041 [1 << 17]byte +var z13042 [1 << 17]byte +var z13043 [1 << 17]byte +var z13044 [1 << 17]byte +var z13045 [1 << 17]byte +var z13046 [1 << 17]byte +var z13047 [1 << 17]byte +var z13048 [1 << 17]byte +var z13049 [1 << 17]byte +var z13050 [1 << 17]byte +var z13051 [1 << 17]byte +var z13052 [1 << 17]byte +var z13053 [1 << 17]byte +var z13054 [1 << 17]byte +var z13055 [1 << 17]byte +var z13056 [1 << 17]byte +var z13057 [1 << 17]byte +var z13058 [1 << 17]byte +var z13059 [1 << 17]byte +var z13060 [1 << 17]byte +var z13061 [1 << 17]byte +var z13062 [1 << 17]byte +var z13063 [1 << 17]byte +var z13064 [1 << 17]byte +var z13065 [1 << 17]byte +var z13066 [1 << 17]byte +var z13067 [1 << 17]byte +var z13068 [1 << 17]byte +var z13069 [1 << 17]byte +var z13070 [1 << 17]byte +var z13071 [1 << 17]byte +var z13072 [1 << 17]byte +var z13073 [1 << 17]byte +var z13074 [1 << 17]byte +var z13075 [1 << 17]byte +var z13076 [1 << 17]byte +var z13077 [1 << 17]byte +var z13078 [1 << 17]byte +var z13079 [1 << 17]byte +var z13080 [1 << 17]byte +var z13081 [1 << 17]byte +var z13082 [1 << 17]byte +var z13083 [1 << 17]byte +var z13084 [1 << 17]byte +var z13085 [1 << 17]byte +var z13086 [1 << 17]byte +var z13087 [1 << 17]byte +var z13088 [1 << 17]byte +var z13089 [1 << 17]byte +var z13090 [1 << 17]byte +var z13091 [1 << 17]byte +var z13092 [1 << 17]byte +var z13093 [1 << 17]byte +var z13094 [1 << 17]byte +var z13095 [1 << 17]byte +var z13096 [1 << 17]byte +var z13097 [1 << 17]byte +var z13098 [1 << 17]byte +var z13099 [1 << 17]byte +var z13100 [1 << 17]byte +var z13101 [1 << 17]byte +var z13102 [1 << 17]byte +var z13103 [1 << 17]byte +var z13104 [1 << 17]byte +var z13105 [1 << 17]byte +var z13106 [1 << 17]byte +var z13107 [1 << 17]byte +var z13108 [1 << 17]byte +var z13109 [1 << 17]byte +var z13110 [1 << 17]byte +var z13111 [1 << 17]byte +var z13112 [1 << 17]byte +var z13113 [1 << 17]byte +var z13114 [1 << 17]byte +var z13115 [1 << 17]byte +var z13116 [1 << 17]byte +var z13117 [1 << 17]byte +var z13118 [1 << 17]byte +var z13119 [1 << 17]byte +var z13120 [1 << 17]byte +var z13121 [1 << 17]byte +var z13122 [1 << 17]byte +var z13123 [1 << 17]byte +var z13124 [1 << 17]byte +var z13125 [1 << 17]byte +var z13126 [1 << 17]byte +var z13127 [1 << 17]byte +var z13128 [1 << 17]byte +var z13129 [1 << 17]byte +var z13130 [1 << 17]byte +var z13131 [1 << 17]byte +var z13132 [1 << 17]byte +var z13133 [1 << 17]byte +var z13134 [1 << 17]byte +var z13135 [1 << 17]byte +var z13136 [1 << 17]byte +var z13137 [1 << 17]byte +var z13138 [1 << 17]byte +var z13139 [1 << 17]byte +var z13140 [1 << 17]byte +var z13141 [1 << 17]byte +var z13142 [1 << 17]byte +var z13143 [1 << 17]byte +var z13144 [1 << 17]byte +var z13145 [1 << 17]byte +var z13146 [1 << 17]byte +var z13147 [1 << 17]byte +var z13148 [1 << 17]byte +var z13149 [1 << 17]byte +var z13150 [1 << 17]byte +var z13151 [1 << 17]byte +var z13152 [1 << 17]byte +var z13153 [1 << 17]byte +var z13154 [1 << 17]byte +var z13155 [1 << 17]byte +var z13156 [1 << 17]byte +var z13157 [1 << 17]byte +var z13158 [1 << 17]byte +var z13159 [1 << 17]byte +var z13160 [1 << 17]byte +var z13161 [1 << 17]byte +var z13162 [1 << 17]byte +var z13163 [1 << 17]byte +var z13164 [1 << 17]byte +var z13165 [1 << 17]byte +var z13166 [1 << 17]byte +var z13167 [1 << 17]byte +var z13168 [1 << 17]byte +var z13169 [1 << 17]byte +var z13170 [1 << 17]byte +var z13171 [1 << 17]byte +var z13172 [1 << 17]byte +var z13173 [1 << 17]byte +var z13174 [1 << 17]byte +var z13175 [1 << 17]byte +var z13176 [1 << 17]byte +var z13177 [1 << 17]byte +var z13178 [1 << 17]byte +var z13179 [1 << 17]byte +var z13180 [1 << 17]byte +var z13181 [1 << 17]byte +var z13182 [1 << 17]byte +var z13183 [1 << 17]byte +var z13184 [1 << 17]byte +var z13185 [1 << 17]byte +var z13186 [1 << 17]byte +var z13187 [1 << 17]byte +var z13188 [1 << 17]byte +var z13189 [1 << 17]byte +var z13190 [1 << 17]byte +var z13191 [1 << 17]byte +var z13192 [1 << 17]byte +var z13193 [1 << 17]byte +var z13194 [1 << 17]byte +var z13195 [1 << 17]byte +var z13196 [1 << 17]byte +var z13197 [1 << 17]byte +var z13198 [1 << 17]byte +var z13199 [1 << 17]byte +var z13200 [1 << 17]byte +var z13201 [1 << 17]byte +var z13202 [1 << 17]byte +var z13203 [1 << 17]byte +var z13204 [1 << 17]byte +var z13205 [1 << 17]byte +var z13206 [1 << 17]byte +var z13207 [1 << 17]byte +var z13208 [1 << 17]byte +var z13209 [1 << 17]byte +var z13210 [1 << 17]byte +var z13211 [1 << 17]byte +var z13212 [1 << 17]byte +var z13213 [1 << 17]byte +var z13214 [1 << 17]byte +var z13215 [1 << 17]byte +var z13216 [1 << 17]byte +var z13217 [1 << 17]byte +var z13218 [1 << 17]byte +var z13219 [1 << 17]byte +var z13220 [1 << 17]byte +var z13221 [1 << 17]byte +var z13222 [1 << 17]byte +var z13223 [1 << 17]byte +var z13224 [1 << 17]byte +var z13225 [1 << 17]byte +var z13226 [1 << 17]byte +var z13227 [1 << 17]byte +var z13228 [1 << 17]byte +var z13229 [1 << 17]byte +var z13230 [1 << 17]byte +var z13231 [1 << 17]byte +var z13232 [1 << 17]byte +var z13233 [1 << 17]byte +var z13234 [1 << 17]byte +var z13235 [1 << 17]byte +var z13236 [1 << 17]byte +var z13237 [1 << 17]byte +var z13238 [1 << 17]byte +var z13239 [1 << 17]byte +var z13240 [1 << 17]byte +var z13241 [1 << 17]byte +var z13242 [1 << 17]byte +var z13243 [1 << 17]byte +var z13244 [1 << 17]byte +var z13245 [1 << 17]byte +var z13246 [1 << 17]byte +var z13247 [1 << 17]byte +var z13248 [1 << 17]byte +var z13249 [1 << 17]byte +var z13250 [1 << 17]byte +var z13251 [1 << 17]byte +var z13252 [1 << 17]byte +var z13253 [1 << 17]byte +var z13254 [1 << 17]byte +var z13255 [1 << 17]byte +var z13256 [1 << 17]byte +var z13257 [1 << 17]byte +var z13258 [1 << 17]byte +var z13259 [1 << 17]byte +var z13260 [1 << 17]byte +var z13261 [1 << 17]byte +var z13262 [1 << 17]byte +var z13263 [1 << 17]byte +var z13264 [1 << 17]byte +var z13265 [1 << 17]byte +var z13266 [1 << 17]byte +var z13267 [1 << 17]byte +var z13268 [1 << 17]byte +var z13269 [1 << 17]byte +var z13270 [1 << 17]byte +var z13271 [1 << 17]byte +var z13272 [1 << 17]byte +var z13273 [1 << 17]byte +var z13274 [1 << 17]byte +var z13275 [1 << 17]byte +var z13276 [1 << 17]byte +var z13277 [1 << 17]byte +var z13278 [1 << 17]byte +var z13279 [1 << 17]byte +var z13280 [1 << 17]byte +var z13281 [1 << 17]byte +var z13282 [1 << 17]byte +var z13283 [1 << 17]byte +var z13284 [1 << 17]byte +var z13285 [1 << 17]byte +var z13286 [1 << 17]byte +var z13287 [1 << 17]byte +var z13288 [1 << 17]byte +var z13289 [1 << 17]byte +var z13290 [1 << 17]byte +var z13291 [1 << 17]byte +var z13292 [1 << 17]byte +var z13293 [1 << 17]byte +var z13294 [1 << 17]byte +var z13295 [1 << 17]byte +var z13296 [1 << 17]byte +var z13297 [1 << 17]byte +var z13298 [1 << 17]byte +var z13299 [1 << 17]byte +var z13300 [1 << 17]byte +var z13301 [1 << 17]byte +var z13302 [1 << 17]byte +var z13303 [1 << 17]byte +var z13304 [1 << 17]byte +var z13305 [1 << 17]byte +var z13306 [1 << 17]byte +var z13307 [1 << 17]byte +var z13308 [1 << 17]byte +var z13309 [1 << 17]byte +var z13310 [1 << 17]byte +var z13311 [1 << 17]byte +var z13312 [1 << 17]byte +var z13313 [1 << 17]byte +var z13314 [1 << 17]byte +var z13315 [1 << 17]byte +var z13316 [1 << 17]byte +var z13317 [1 << 17]byte +var z13318 [1 << 17]byte +var z13319 [1 << 17]byte +var z13320 [1 << 17]byte +var z13321 [1 << 17]byte +var z13322 [1 << 17]byte +var z13323 [1 << 17]byte +var z13324 [1 << 17]byte +var z13325 [1 << 17]byte +var z13326 [1 << 17]byte +var z13327 [1 << 17]byte +var z13328 [1 << 17]byte +var z13329 [1 << 17]byte +var z13330 [1 << 17]byte +var z13331 [1 << 17]byte +var z13332 [1 << 17]byte +var z13333 [1 << 17]byte +var z13334 [1 << 17]byte +var z13335 [1 << 17]byte +var z13336 [1 << 17]byte +var z13337 [1 << 17]byte +var z13338 [1 << 17]byte +var z13339 [1 << 17]byte +var z13340 [1 << 17]byte +var z13341 [1 << 17]byte +var z13342 [1 << 17]byte +var z13343 [1 << 17]byte +var z13344 [1 << 17]byte +var z13345 [1 << 17]byte +var z13346 [1 << 17]byte +var z13347 [1 << 17]byte +var z13348 [1 << 17]byte +var z13349 [1 << 17]byte +var z13350 [1 << 17]byte +var z13351 [1 << 17]byte +var z13352 [1 << 17]byte +var z13353 [1 << 17]byte +var z13354 [1 << 17]byte +var z13355 [1 << 17]byte +var z13356 [1 << 17]byte +var z13357 [1 << 17]byte +var z13358 [1 << 17]byte +var z13359 [1 << 17]byte +var z13360 [1 << 17]byte +var z13361 [1 << 17]byte +var z13362 [1 << 17]byte +var z13363 [1 << 17]byte +var z13364 [1 << 17]byte +var z13365 [1 << 17]byte +var z13366 [1 << 17]byte +var z13367 [1 << 17]byte +var z13368 [1 << 17]byte +var z13369 [1 << 17]byte +var z13370 [1 << 17]byte +var z13371 [1 << 17]byte +var z13372 [1 << 17]byte +var z13373 [1 << 17]byte +var z13374 [1 << 17]byte +var z13375 [1 << 17]byte +var z13376 [1 << 17]byte +var z13377 [1 << 17]byte +var z13378 [1 << 17]byte +var z13379 [1 << 17]byte +var z13380 [1 << 17]byte +var z13381 [1 << 17]byte +var z13382 [1 << 17]byte +var z13383 [1 << 17]byte +var z13384 [1 << 17]byte +var z13385 [1 << 17]byte +var z13386 [1 << 17]byte +var z13387 [1 << 17]byte +var z13388 [1 << 17]byte +var z13389 [1 << 17]byte +var z13390 [1 << 17]byte +var z13391 [1 << 17]byte +var z13392 [1 << 17]byte +var z13393 [1 << 17]byte +var z13394 [1 << 17]byte +var z13395 [1 << 17]byte +var z13396 [1 << 17]byte +var z13397 [1 << 17]byte +var z13398 [1 << 17]byte +var z13399 [1 << 17]byte +var z13400 [1 << 17]byte +var z13401 [1 << 17]byte +var z13402 [1 << 17]byte +var z13403 [1 << 17]byte +var z13404 [1 << 17]byte +var z13405 [1 << 17]byte +var z13406 [1 << 17]byte +var z13407 [1 << 17]byte +var z13408 [1 << 17]byte +var z13409 [1 << 17]byte +var z13410 [1 << 17]byte +var z13411 [1 << 17]byte +var z13412 [1 << 17]byte +var z13413 [1 << 17]byte +var z13414 [1 << 17]byte +var z13415 [1 << 17]byte +var z13416 [1 << 17]byte +var z13417 [1 << 17]byte +var z13418 [1 << 17]byte +var z13419 [1 << 17]byte +var z13420 [1 << 17]byte +var z13421 [1 << 17]byte +var z13422 [1 << 17]byte +var z13423 [1 << 17]byte +var z13424 [1 << 17]byte +var z13425 [1 << 17]byte +var z13426 [1 << 17]byte +var z13427 [1 << 17]byte +var z13428 [1 << 17]byte +var z13429 [1 << 17]byte +var z13430 [1 << 17]byte +var z13431 [1 << 17]byte +var z13432 [1 << 17]byte +var z13433 [1 << 17]byte +var z13434 [1 << 17]byte +var z13435 [1 << 17]byte +var z13436 [1 << 17]byte +var z13437 [1 << 17]byte +var z13438 [1 << 17]byte +var z13439 [1 << 17]byte +var z13440 [1 << 17]byte +var z13441 [1 << 17]byte +var z13442 [1 << 17]byte +var z13443 [1 << 17]byte +var z13444 [1 << 17]byte +var z13445 [1 << 17]byte +var z13446 [1 << 17]byte +var z13447 [1 << 17]byte +var z13448 [1 << 17]byte +var z13449 [1 << 17]byte +var z13450 [1 << 17]byte +var z13451 [1 << 17]byte +var z13452 [1 << 17]byte +var z13453 [1 << 17]byte +var z13454 [1 << 17]byte +var z13455 [1 << 17]byte +var z13456 [1 << 17]byte +var z13457 [1 << 17]byte +var z13458 [1 << 17]byte +var z13459 [1 << 17]byte +var z13460 [1 << 17]byte +var z13461 [1 << 17]byte +var z13462 [1 << 17]byte +var z13463 [1 << 17]byte +var z13464 [1 << 17]byte +var z13465 [1 << 17]byte +var z13466 [1 << 17]byte +var z13467 [1 << 17]byte +var z13468 [1 << 17]byte +var z13469 [1 << 17]byte +var z13470 [1 << 17]byte +var z13471 [1 << 17]byte +var z13472 [1 << 17]byte +var z13473 [1 << 17]byte +var z13474 [1 << 17]byte +var z13475 [1 << 17]byte +var z13476 [1 << 17]byte +var z13477 [1 << 17]byte +var z13478 [1 << 17]byte +var z13479 [1 << 17]byte +var z13480 [1 << 17]byte +var z13481 [1 << 17]byte +var z13482 [1 << 17]byte +var z13483 [1 << 17]byte +var z13484 [1 << 17]byte +var z13485 [1 << 17]byte +var z13486 [1 << 17]byte +var z13487 [1 << 17]byte +var z13488 [1 << 17]byte +var z13489 [1 << 17]byte +var z13490 [1 << 17]byte +var z13491 [1 << 17]byte +var z13492 [1 << 17]byte +var z13493 [1 << 17]byte +var z13494 [1 << 17]byte +var z13495 [1 << 17]byte +var z13496 [1 << 17]byte +var z13497 [1 << 17]byte +var z13498 [1 << 17]byte +var z13499 [1 << 17]byte +var z13500 [1 << 17]byte +var z13501 [1 << 17]byte +var z13502 [1 << 17]byte +var z13503 [1 << 17]byte +var z13504 [1 << 17]byte +var z13505 [1 << 17]byte +var z13506 [1 << 17]byte +var z13507 [1 << 17]byte +var z13508 [1 << 17]byte +var z13509 [1 << 17]byte +var z13510 [1 << 17]byte +var z13511 [1 << 17]byte +var z13512 [1 << 17]byte +var z13513 [1 << 17]byte +var z13514 [1 << 17]byte +var z13515 [1 << 17]byte +var z13516 [1 << 17]byte +var z13517 [1 << 17]byte +var z13518 [1 << 17]byte +var z13519 [1 << 17]byte +var z13520 [1 << 17]byte +var z13521 [1 << 17]byte +var z13522 [1 << 17]byte +var z13523 [1 << 17]byte +var z13524 [1 << 17]byte +var z13525 [1 << 17]byte +var z13526 [1 << 17]byte +var z13527 [1 << 17]byte +var z13528 [1 << 17]byte +var z13529 [1 << 17]byte +var z13530 [1 << 17]byte +var z13531 [1 << 17]byte +var z13532 [1 << 17]byte +var z13533 [1 << 17]byte +var z13534 [1 << 17]byte +var z13535 [1 << 17]byte +var z13536 [1 << 17]byte +var z13537 [1 << 17]byte +var z13538 [1 << 17]byte +var z13539 [1 << 17]byte +var z13540 [1 << 17]byte +var z13541 [1 << 17]byte +var z13542 [1 << 17]byte +var z13543 [1 << 17]byte +var z13544 [1 << 17]byte +var z13545 [1 << 17]byte +var z13546 [1 << 17]byte +var z13547 [1 << 17]byte +var z13548 [1 << 17]byte +var z13549 [1 << 17]byte +var z13550 [1 << 17]byte +var z13551 [1 << 17]byte +var z13552 [1 << 17]byte +var z13553 [1 << 17]byte +var z13554 [1 << 17]byte +var z13555 [1 << 17]byte +var z13556 [1 << 17]byte +var z13557 [1 << 17]byte +var z13558 [1 << 17]byte +var z13559 [1 << 17]byte +var z13560 [1 << 17]byte +var z13561 [1 << 17]byte +var z13562 [1 << 17]byte +var z13563 [1 << 17]byte +var z13564 [1 << 17]byte +var z13565 [1 << 17]byte +var z13566 [1 << 17]byte +var z13567 [1 << 17]byte +var z13568 [1 << 17]byte +var z13569 [1 << 17]byte +var z13570 [1 << 17]byte +var z13571 [1 << 17]byte +var z13572 [1 << 17]byte +var z13573 [1 << 17]byte +var z13574 [1 << 17]byte +var z13575 [1 << 17]byte +var z13576 [1 << 17]byte +var z13577 [1 << 17]byte +var z13578 [1 << 17]byte +var z13579 [1 << 17]byte +var z13580 [1 << 17]byte +var z13581 [1 << 17]byte +var z13582 [1 << 17]byte +var z13583 [1 << 17]byte +var z13584 [1 << 17]byte +var z13585 [1 << 17]byte +var z13586 [1 << 17]byte +var z13587 [1 << 17]byte +var z13588 [1 << 17]byte +var z13589 [1 << 17]byte +var z13590 [1 << 17]byte +var z13591 [1 << 17]byte +var z13592 [1 << 17]byte +var z13593 [1 << 17]byte +var z13594 [1 << 17]byte +var z13595 [1 << 17]byte +var z13596 [1 << 17]byte +var z13597 [1 << 17]byte +var z13598 [1 << 17]byte +var z13599 [1 << 17]byte +var z13600 [1 << 17]byte +var z13601 [1 << 17]byte +var z13602 [1 << 17]byte +var z13603 [1 << 17]byte +var z13604 [1 << 17]byte +var z13605 [1 << 17]byte +var z13606 [1 << 17]byte +var z13607 [1 << 17]byte +var z13608 [1 << 17]byte +var z13609 [1 << 17]byte +var z13610 [1 << 17]byte +var z13611 [1 << 17]byte +var z13612 [1 << 17]byte +var z13613 [1 << 17]byte +var z13614 [1 << 17]byte +var z13615 [1 << 17]byte +var z13616 [1 << 17]byte +var z13617 [1 << 17]byte +var z13618 [1 << 17]byte +var z13619 [1 << 17]byte +var z13620 [1 << 17]byte +var z13621 [1 << 17]byte +var z13622 [1 << 17]byte +var z13623 [1 << 17]byte +var z13624 [1 << 17]byte +var z13625 [1 << 17]byte +var z13626 [1 << 17]byte +var z13627 [1 << 17]byte +var z13628 [1 << 17]byte +var z13629 [1 << 17]byte +var z13630 [1 << 17]byte +var z13631 [1 << 17]byte +var z13632 [1 << 17]byte +var z13633 [1 << 17]byte +var z13634 [1 << 17]byte +var z13635 [1 << 17]byte +var z13636 [1 << 17]byte +var z13637 [1 << 17]byte +var z13638 [1 << 17]byte +var z13639 [1 << 17]byte +var z13640 [1 << 17]byte +var z13641 [1 << 17]byte +var z13642 [1 << 17]byte +var z13643 [1 << 17]byte +var z13644 [1 << 17]byte +var z13645 [1 << 17]byte +var z13646 [1 << 17]byte +var z13647 [1 << 17]byte +var z13648 [1 << 17]byte +var z13649 [1 << 17]byte +var z13650 [1 << 17]byte +var z13651 [1 << 17]byte +var z13652 [1 << 17]byte +var z13653 [1 << 17]byte +var z13654 [1 << 17]byte +var z13655 [1 << 17]byte +var z13656 [1 << 17]byte +var z13657 [1 << 17]byte +var z13658 [1 << 17]byte +var z13659 [1 << 17]byte +var z13660 [1 << 17]byte +var z13661 [1 << 17]byte +var z13662 [1 << 17]byte +var z13663 [1 << 17]byte +var z13664 [1 << 17]byte +var z13665 [1 << 17]byte +var z13666 [1 << 17]byte +var z13667 [1 << 17]byte +var z13668 [1 << 17]byte +var z13669 [1 << 17]byte +var z13670 [1 << 17]byte +var z13671 [1 << 17]byte +var z13672 [1 << 17]byte +var z13673 [1 << 17]byte +var z13674 [1 << 17]byte +var z13675 [1 << 17]byte +var z13676 [1 << 17]byte +var z13677 [1 << 17]byte +var z13678 [1 << 17]byte +var z13679 [1 << 17]byte +var z13680 [1 << 17]byte +var z13681 [1 << 17]byte +var z13682 [1 << 17]byte +var z13683 [1 << 17]byte +var z13684 [1 << 17]byte +var z13685 [1 << 17]byte +var z13686 [1 << 17]byte +var z13687 [1 << 17]byte +var z13688 [1 << 17]byte +var z13689 [1 << 17]byte +var z13690 [1 << 17]byte +var z13691 [1 << 17]byte +var z13692 [1 << 17]byte +var z13693 [1 << 17]byte +var z13694 [1 << 17]byte +var z13695 [1 << 17]byte +var z13696 [1 << 17]byte +var z13697 [1 << 17]byte +var z13698 [1 << 17]byte +var z13699 [1 << 17]byte +var z13700 [1 << 17]byte +var z13701 [1 << 17]byte +var z13702 [1 << 17]byte +var z13703 [1 << 17]byte +var z13704 [1 << 17]byte +var z13705 [1 << 17]byte +var z13706 [1 << 17]byte +var z13707 [1 << 17]byte +var z13708 [1 << 17]byte +var z13709 [1 << 17]byte +var z13710 [1 << 17]byte +var z13711 [1 << 17]byte +var z13712 [1 << 17]byte +var z13713 [1 << 17]byte +var z13714 [1 << 17]byte +var z13715 [1 << 17]byte +var z13716 [1 << 17]byte +var z13717 [1 << 17]byte +var z13718 [1 << 17]byte +var z13719 [1 << 17]byte +var z13720 [1 << 17]byte +var z13721 [1 << 17]byte +var z13722 [1 << 17]byte +var z13723 [1 << 17]byte +var z13724 [1 << 17]byte +var z13725 [1 << 17]byte +var z13726 [1 << 17]byte +var z13727 [1 << 17]byte +var z13728 [1 << 17]byte +var z13729 [1 << 17]byte +var z13730 [1 << 17]byte +var z13731 [1 << 17]byte +var z13732 [1 << 17]byte +var z13733 [1 << 17]byte +var z13734 [1 << 17]byte +var z13735 [1 << 17]byte +var z13736 [1 << 17]byte +var z13737 [1 << 17]byte +var z13738 [1 << 17]byte +var z13739 [1 << 17]byte +var z13740 [1 << 17]byte +var z13741 [1 << 17]byte +var z13742 [1 << 17]byte +var z13743 [1 << 17]byte +var z13744 [1 << 17]byte +var z13745 [1 << 17]byte +var z13746 [1 << 17]byte +var z13747 [1 << 17]byte +var z13748 [1 << 17]byte +var z13749 [1 << 17]byte +var z13750 [1 << 17]byte +var z13751 [1 << 17]byte +var z13752 [1 << 17]byte +var z13753 [1 << 17]byte +var z13754 [1 << 17]byte +var z13755 [1 << 17]byte +var z13756 [1 << 17]byte +var z13757 [1 << 17]byte +var z13758 [1 << 17]byte +var z13759 [1 << 17]byte +var z13760 [1 << 17]byte +var z13761 [1 << 17]byte +var z13762 [1 << 17]byte +var z13763 [1 << 17]byte +var z13764 [1 << 17]byte +var z13765 [1 << 17]byte +var z13766 [1 << 17]byte +var z13767 [1 << 17]byte +var z13768 [1 << 17]byte +var z13769 [1 << 17]byte +var z13770 [1 << 17]byte +var z13771 [1 << 17]byte +var z13772 [1 << 17]byte +var z13773 [1 << 17]byte +var z13774 [1 << 17]byte +var z13775 [1 << 17]byte +var z13776 [1 << 17]byte +var z13777 [1 << 17]byte +var z13778 [1 << 17]byte +var z13779 [1 << 17]byte +var z13780 [1 << 17]byte +var z13781 [1 << 17]byte +var z13782 [1 << 17]byte +var z13783 [1 << 17]byte +var z13784 [1 << 17]byte +var z13785 [1 << 17]byte +var z13786 [1 << 17]byte +var z13787 [1 << 17]byte +var z13788 [1 << 17]byte +var z13789 [1 << 17]byte +var z13790 [1 << 17]byte +var z13791 [1 << 17]byte +var z13792 [1 << 17]byte +var z13793 [1 << 17]byte +var z13794 [1 << 17]byte +var z13795 [1 << 17]byte +var z13796 [1 << 17]byte +var z13797 [1 << 17]byte +var z13798 [1 << 17]byte +var z13799 [1 << 17]byte +var z13800 [1 << 17]byte +var z13801 [1 << 17]byte +var z13802 [1 << 17]byte +var z13803 [1 << 17]byte +var z13804 [1 << 17]byte +var z13805 [1 << 17]byte +var z13806 [1 << 17]byte +var z13807 [1 << 17]byte +var z13808 [1 << 17]byte +var z13809 [1 << 17]byte +var z13810 [1 << 17]byte +var z13811 [1 << 17]byte +var z13812 [1 << 17]byte +var z13813 [1 << 17]byte +var z13814 [1 << 17]byte +var z13815 [1 << 17]byte +var z13816 [1 << 17]byte +var z13817 [1 << 17]byte +var z13818 [1 << 17]byte +var z13819 [1 << 17]byte +var z13820 [1 << 17]byte +var z13821 [1 << 17]byte +var z13822 [1 << 17]byte +var z13823 [1 << 17]byte +var z13824 [1 << 17]byte +var z13825 [1 << 17]byte +var z13826 [1 << 17]byte +var z13827 [1 << 17]byte +var z13828 [1 << 17]byte +var z13829 [1 << 17]byte +var z13830 [1 << 17]byte +var z13831 [1 << 17]byte +var z13832 [1 << 17]byte +var z13833 [1 << 17]byte +var z13834 [1 << 17]byte +var z13835 [1 << 17]byte +var z13836 [1 << 17]byte +var z13837 [1 << 17]byte +var z13838 [1 << 17]byte +var z13839 [1 << 17]byte +var z13840 [1 << 17]byte +var z13841 [1 << 17]byte +var z13842 [1 << 17]byte +var z13843 [1 << 17]byte +var z13844 [1 << 17]byte +var z13845 [1 << 17]byte +var z13846 [1 << 17]byte +var z13847 [1 << 17]byte +var z13848 [1 << 17]byte +var z13849 [1 << 17]byte +var z13850 [1 << 17]byte +var z13851 [1 << 17]byte +var z13852 [1 << 17]byte +var z13853 [1 << 17]byte +var z13854 [1 << 17]byte +var z13855 [1 << 17]byte +var z13856 [1 << 17]byte +var z13857 [1 << 17]byte +var z13858 [1 << 17]byte +var z13859 [1 << 17]byte +var z13860 [1 << 17]byte +var z13861 [1 << 17]byte +var z13862 [1 << 17]byte +var z13863 [1 << 17]byte +var z13864 [1 << 17]byte +var z13865 [1 << 17]byte +var z13866 [1 << 17]byte +var z13867 [1 << 17]byte +var z13868 [1 << 17]byte +var z13869 [1 << 17]byte +var z13870 [1 << 17]byte +var z13871 [1 << 17]byte +var z13872 [1 << 17]byte +var z13873 [1 << 17]byte +var z13874 [1 << 17]byte +var z13875 [1 << 17]byte +var z13876 [1 << 17]byte +var z13877 [1 << 17]byte +var z13878 [1 << 17]byte +var z13879 [1 << 17]byte +var z13880 [1 << 17]byte +var z13881 [1 << 17]byte +var z13882 [1 << 17]byte +var z13883 [1 << 17]byte +var z13884 [1 << 17]byte +var z13885 [1 << 17]byte +var z13886 [1 << 17]byte +var z13887 [1 << 17]byte +var z13888 [1 << 17]byte +var z13889 [1 << 17]byte +var z13890 [1 << 17]byte +var z13891 [1 << 17]byte +var z13892 [1 << 17]byte +var z13893 [1 << 17]byte +var z13894 [1 << 17]byte +var z13895 [1 << 17]byte +var z13896 [1 << 17]byte +var z13897 [1 << 17]byte +var z13898 [1 << 17]byte +var z13899 [1 << 17]byte +var z13900 [1 << 17]byte +var z13901 [1 << 17]byte +var z13902 [1 << 17]byte +var z13903 [1 << 17]byte +var z13904 [1 << 17]byte +var z13905 [1 << 17]byte +var z13906 [1 << 17]byte +var z13907 [1 << 17]byte +var z13908 [1 << 17]byte +var z13909 [1 << 17]byte +var z13910 [1 << 17]byte +var z13911 [1 << 17]byte +var z13912 [1 << 17]byte +var z13913 [1 << 17]byte +var z13914 [1 << 17]byte +var z13915 [1 << 17]byte +var z13916 [1 << 17]byte +var z13917 [1 << 17]byte +var z13918 [1 << 17]byte +var z13919 [1 << 17]byte +var z13920 [1 << 17]byte +var z13921 [1 << 17]byte +var z13922 [1 << 17]byte +var z13923 [1 << 17]byte +var z13924 [1 << 17]byte +var z13925 [1 << 17]byte +var z13926 [1 << 17]byte +var z13927 [1 << 17]byte +var z13928 [1 << 17]byte +var z13929 [1 << 17]byte +var z13930 [1 << 17]byte +var z13931 [1 << 17]byte +var z13932 [1 << 17]byte +var z13933 [1 << 17]byte +var z13934 [1 << 17]byte +var z13935 [1 << 17]byte +var z13936 [1 << 17]byte +var z13937 [1 << 17]byte +var z13938 [1 << 17]byte +var z13939 [1 << 17]byte +var z13940 [1 << 17]byte +var z13941 [1 << 17]byte +var z13942 [1 << 17]byte +var z13943 [1 << 17]byte +var z13944 [1 << 17]byte +var z13945 [1 << 17]byte +var z13946 [1 << 17]byte +var z13947 [1 << 17]byte +var z13948 [1 << 17]byte +var z13949 [1 << 17]byte +var z13950 [1 << 17]byte +var z13951 [1 << 17]byte +var z13952 [1 << 17]byte +var z13953 [1 << 17]byte +var z13954 [1 << 17]byte +var z13955 [1 << 17]byte +var z13956 [1 << 17]byte +var z13957 [1 << 17]byte +var z13958 [1 << 17]byte +var z13959 [1 << 17]byte +var z13960 [1 << 17]byte +var z13961 [1 << 17]byte +var z13962 [1 << 17]byte +var z13963 [1 << 17]byte +var z13964 [1 << 17]byte +var z13965 [1 << 17]byte +var z13966 [1 << 17]byte +var z13967 [1 << 17]byte +var z13968 [1 << 17]byte +var z13969 [1 << 17]byte +var z13970 [1 << 17]byte +var z13971 [1 << 17]byte +var z13972 [1 << 17]byte +var z13973 [1 << 17]byte +var z13974 [1 << 17]byte +var z13975 [1 << 17]byte +var z13976 [1 << 17]byte +var z13977 [1 << 17]byte +var z13978 [1 << 17]byte +var z13979 [1 << 17]byte +var z13980 [1 << 17]byte +var z13981 [1 << 17]byte +var z13982 [1 << 17]byte +var z13983 [1 << 17]byte +var z13984 [1 << 17]byte +var z13985 [1 << 17]byte +var z13986 [1 << 17]byte +var z13987 [1 << 17]byte +var z13988 [1 << 17]byte +var z13989 [1 << 17]byte +var z13990 [1 << 17]byte +var z13991 [1 << 17]byte +var z13992 [1 << 17]byte +var z13993 [1 << 17]byte +var z13994 [1 << 17]byte +var z13995 [1 << 17]byte +var z13996 [1 << 17]byte +var z13997 [1 << 17]byte +var z13998 [1 << 17]byte +var z13999 [1 << 17]byte +var z14000 [1 << 17]byte +var z14001 [1 << 17]byte +var z14002 [1 << 17]byte +var z14003 [1 << 17]byte +var z14004 [1 << 17]byte +var z14005 [1 << 17]byte +var z14006 [1 << 17]byte +var z14007 [1 << 17]byte +var z14008 [1 << 17]byte +var z14009 [1 << 17]byte +var z14010 [1 << 17]byte +var z14011 [1 << 17]byte +var z14012 [1 << 17]byte +var z14013 [1 << 17]byte +var z14014 [1 << 17]byte +var z14015 [1 << 17]byte +var z14016 [1 << 17]byte +var z14017 [1 << 17]byte +var z14018 [1 << 17]byte +var z14019 [1 << 17]byte +var z14020 [1 << 17]byte +var z14021 [1 << 17]byte +var z14022 [1 << 17]byte +var z14023 [1 << 17]byte +var z14024 [1 << 17]byte +var z14025 [1 << 17]byte +var z14026 [1 << 17]byte +var z14027 [1 << 17]byte +var z14028 [1 << 17]byte +var z14029 [1 << 17]byte +var z14030 [1 << 17]byte +var z14031 [1 << 17]byte +var z14032 [1 << 17]byte +var z14033 [1 << 17]byte +var z14034 [1 << 17]byte +var z14035 [1 << 17]byte +var z14036 [1 << 17]byte +var z14037 [1 << 17]byte +var z14038 [1 << 17]byte +var z14039 [1 << 17]byte +var z14040 [1 << 17]byte +var z14041 [1 << 17]byte +var z14042 [1 << 17]byte +var z14043 [1 << 17]byte +var z14044 [1 << 17]byte +var z14045 [1 << 17]byte +var z14046 [1 << 17]byte +var z14047 [1 << 17]byte +var z14048 [1 << 17]byte +var z14049 [1 << 17]byte +var z14050 [1 << 17]byte +var z14051 [1 << 17]byte +var z14052 [1 << 17]byte +var z14053 [1 << 17]byte +var z14054 [1 << 17]byte +var z14055 [1 << 17]byte +var z14056 [1 << 17]byte +var z14057 [1 << 17]byte +var z14058 [1 << 17]byte +var z14059 [1 << 17]byte +var z14060 [1 << 17]byte +var z14061 [1 << 17]byte +var z14062 [1 << 17]byte +var z14063 [1 << 17]byte +var z14064 [1 << 17]byte +var z14065 [1 << 17]byte +var z14066 [1 << 17]byte +var z14067 [1 << 17]byte +var z14068 [1 << 17]byte +var z14069 [1 << 17]byte +var z14070 [1 << 17]byte +var z14071 [1 << 17]byte +var z14072 [1 << 17]byte +var z14073 [1 << 17]byte +var z14074 [1 << 17]byte +var z14075 [1 << 17]byte +var z14076 [1 << 17]byte +var z14077 [1 << 17]byte +var z14078 [1 << 17]byte +var z14079 [1 << 17]byte +var z14080 [1 << 17]byte +var z14081 [1 << 17]byte +var z14082 [1 << 17]byte +var z14083 [1 << 17]byte +var z14084 [1 << 17]byte +var z14085 [1 << 17]byte +var z14086 [1 << 17]byte +var z14087 [1 << 17]byte +var z14088 [1 << 17]byte +var z14089 [1 << 17]byte +var z14090 [1 << 17]byte +var z14091 [1 << 17]byte +var z14092 [1 << 17]byte +var z14093 [1 << 17]byte +var z14094 [1 << 17]byte +var z14095 [1 << 17]byte +var z14096 [1 << 17]byte +var z14097 [1 << 17]byte +var z14098 [1 << 17]byte +var z14099 [1 << 17]byte +var z14100 [1 << 17]byte +var z14101 [1 << 17]byte +var z14102 [1 << 17]byte +var z14103 [1 << 17]byte +var z14104 [1 << 17]byte +var z14105 [1 << 17]byte +var z14106 [1 << 17]byte +var z14107 [1 << 17]byte +var z14108 [1 << 17]byte +var z14109 [1 << 17]byte +var z14110 [1 << 17]byte +var z14111 [1 << 17]byte +var z14112 [1 << 17]byte +var z14113 [1 << 17]byte +var z14114 [1 << 17]byte +var z14115 [1 << 17]byte +var z14116 [1 << 17]byte +var z14117 [1 << 17]byte +var z14118 [1 << 17]byte +var z14119 [1 << 17]byte +var z14120 [1 << 17]byte +var z14121 [1 << 17]byte +var z14122 [1 << 17]byte +var z14123 [1 << 17]byte +var z14124 [1 << 17]byte +var z14125 [1 << 17]byte +var z14126 [1 << 17]byte +var z14127 [1 << 17]byte +var z14128 [1 << 17]byte +var z14129 [1 << 17]byte +var z14130 [1 << 17]byte +var z14131 [1 << 17]byte +var z14132 [1 << 17]byte +var z14133 [1 << 17]byte +var z14134 [1 << 17]byte +var z14135 [1 << 17]byte +var z14136 [1 << 17]byte +var z14137 [1 << 17]byte +var z14138 [1 << 17]byte +var z14139 [1 << 17]byte +var z14140 [1 << 17]byte +var z14141 [1 << 17]byte +var z14142 [1 << 17]byte +var z14143 [1 << 17]byte +var z14144 [1 << 17]byte +var z14145 [1 << 17]byte +var z14146 [1 << 17]byte +var z14147 [1 << 17]byte +var z14148 [1 << 17]byte +var z14149 [1 << 17]byte +var z14150 [1 << 17]byte +var z14151 [1 << 17]byte +var z14152 [1 << 17]byte +var z14153 [1 << 17]byte +var z14154 [1 << 17]byte +var z14155 [1 << 17]byte +var z14156 [1 << 17]byte +var z14157 [1 << 17]byte +var z14158 [1 << 17]byte +var z14159 [1 << 17]byte +var z14160 [1 << 17]byte +var z14161 [1 << 17]byte +var z14162 [1 << 17]byte +var z14163 [1 << 17]byte +var z14164 [1 << 17]byte +var z14165 [1 << 17]byte +var z14166 [1 << 17]byte +var z14167 [1 << 17]byte +var z14168 [1 << 17]byte +var z14169 [1 << 17]byte +var z14170 [1 << 17]byte +var z14171 [1 << 17]byte +var z14172 [1 << 17]byte +var z14173 [1 << 17]byte +var z14174 [1 << 17]byte +var z14175 [1 << 17]byte +var z14176 [1 << 17]byte +var z14177 [1 << 17]byte +var z14178 [1 << 17]byte +var z14179 [1 << 17]byte +var z14180 [1 << 17]byte +var z14181 [1 << 17]byte +var z14182 [1 << 17]byte +var z14183 [1 << 17]byte +var z14184 [1 << 17]byte +var z14185 [1 << 17]byte +var z14186 [1 << 17]byte +var z14187 [1 << 17]byte +var z14188 [1 << 17]byte +var z14189 [1 << 17]byte +var z14190 [1 << 17]byte +var z14191 [1 << 17]byte +var z14192 [1 << 17]byte +var z14193 [1 << 17]byte +var z14194 [1 << 17]byte +var z14195 [1 << 17]byte +var z14196 [1 << 17]byte +var z14197 [1 << 17]byte +var z14198 [1 << 17]byte +var z14199 [1 << 17]byte +var z14200 [1 << 17]byte +var z14201 [1 << 17]byte +var z14202 [1 << 17]byte +var z14203 [1 << 17]byte +var z14204 [1 << 17]byte +var z14205 [1 << 17]byte +var z14206 [1 << 17]byte +var z14207 [1 << 17]byte +var z14208 [1 << 17]byte +var z14209 [1 << 17]byte +var z14210 [1 << 17]byte +var z14211 [1 << 17]byte +var z14212 [1 << 17]byte +var z14213 [1 << 17]byte +var z14214 [1 << 17]byte +var z14215 [1 << 17]byte +var z14216 [1 << 17]byte +var z14217 [1 << 17]byte +var z14218 [1 << 17]byte +var z14219 [1 << 17]byte +var z14220 [1 << 17]byte +var z14221 [1 << 17]byte +var z14222 [1 << 17]byte +var z14223 [1 << 17]byte +var z14224 [1 << 17]byte +var z14225 [1 << 17]byte +var z14226 [1 << 17]byte +var z14227 [1 << 17]byte +var z14228 [1 << 17]byte +var z14229 [1 << 17]byte +var z14230 [1 << 17]byte +var z14231 [1 << 17]byte +var z14232 [1 << 17]byte +var z14233 [1 << 17]byte +var z14234 [1 << 17]byte +var z14235 [1 << 17]byte +var z14236 [1 << 17]byte +var z14237 [1 << 17]byte +var z14238 [1 << 17]byte +var z14239 [1 << 17]byte +var z14240 [1 << 17]byte +var z14241 [1 << 17]byte +var z14242 [1 << 17]byte +var z14243 [1 << 17]byte +var z14244 [1 << 17]byte +var z14245 [1 << 17]byte +var z14246 [1 << 17]byte +var z14247 [1 << 17]byte +var z14248 [1 << 17]byte +var z14249 [1 << 17]byte +var z14250 [1 << 17]byte +var z14251 [1 << 17]byte +var z14252 [1 << 17]byte +var z14253 [1 << 17]byte +var z14254 [1 << 17]byte +var z14255 [1 << 17]byte +var z14256 [1 << 17]byte +var z14257 [1 << 17]byte +var z14258 [1 << 17]byte +var z14259 [1 << 17]byte +var z14260 [1 << 17]byte +var z14261 [1 << 17]byte +var z14262 [1 << 17]byte +var z14263 [1 << 17]byte +var z14264 [1 << 17]byte +var z14265 [1 << 17]byte +var z14266 [1 << 17]byte +var z14267 [1 << 17]byte +var z14268 [1 << 17]byte +var z14269 [1 << 17]byte +var z14270 [1 << 17]byte +var z14271 [1 << 17]byte +var z14272 [1 << 17]byte +var z14273 [1 << 17]byte +var z14274 [1 << 17]byte +var z14275 [1 << 17]byte +var z14276 [1 << 17]byte +var z14277 [1 << 17]byte +var z14278 [1 << 17]byte +var z14279 [1 << 17]byte +var z14280 [1 << 17]byte +var z14281 [1 << 17]byte +var z14282 [1 << 17]byte +var z14283 [1 << 17]byte +var z14284 [1 << 17]byte +var z14285 [1 << 17]byte +var z14286 [1 << 17]byte +var z14287 [1 << 17]byte +var z14288 [1 << 17]byte +var z14289 [1 << 17]byte +var z14290 [1 << 17]byte +var z14291 [1 << 17]byte +var z14292 [1 << 17]byte +var z14293 [1 << 17]byte +var z14294 [1 << 17]byte +var z14295 [1 << 17]byte +var z14296 [1 << 17]byte +var z14297 [1 << 17]byte +var z14298 [1 << 17]byte +var z14299 [1 << 17]byte +var z14300 [1 << 17]byte +var z14301 [1 << 17]byte +var z14302 [1 << 17]byte +var z14303 [1 << 17]byte +var z14304 [1 << 17]byte +var z14305 [1 << 17]byte +var z14306 [1 << 17]byte +var z14307 [1 << 17]byte +var z14308 [1 << 17]byte +var z14309 [1 << 17]byte +var z14310 [1 << 17]byte +var z14311 [1 << 17]byte +var z14312 [1 << 17]byte +var z14313 [1 << 17]byte +var z14314 [1 << 17]byte +var z14315 [1 << 17]byte +var z14316 [1 << 17]byte +var z14317 [1 << 17]byte +var z14318 [1 << 17]byte +var z14319 [1 << 17]byte +var z14320 [1 << 17]byte +var z14321 [1 << 17]byte +var z14322 [1 << 17]byte +var z14323 [1 << 17]byte +var z14324 [1 << 17]byte +var z14325 [1 << 17]byte +var z14326 [1 << 17]byte +var z14327 [1 << 17]byte +var z14328 [1 << 17]byte +var z14329 [1 << 17]byte +var z14330 [1 << 17]byte +var z14331 [1 << 17]byte +var z14332 [1 << 17]byte +var z14333 [1 << 17]byte +var z14334 [1 << 17]byte +var z14335 [1 << 17]byte +var z14336 [1 << 17]byte +var z14337 [1 << 17]byte +var z14338 [1 << 17]byte +var z14339 [1 << 17]byte +var z14340 [1 << 17]byte +var z14341 [1 << 17]byte +var z14342 [1 << 17]byte +var z14343 [1 << 17]byte +var z14344 [1 << 17]byte +var z14345 [1 << 17]byte +var z14346 [1 << 17]byte +var z14347 [1 << 17]byte +var z14348 [1 << 17]byte +var z14349 [1 << 17]byte +var z14350 [1 << 17]byte +var z14351 [1 << 17]byte +var z14352 [1 << 17]byte +var z14353 [1 << 17]byte +var z14354 [1 << 17]byte +var z14355 [1 << 17]byte +var z14356 [1 << 17]byte +var z14357 [1 << 17]byte +var z14358 [1 << 17]byte +var z14359 [1 << 17]byte +var z14360 [1 << 17]byte +var z14361 [1 << 17]byte +var z14362 [1 << 17]byte +var z14363 [1 << 17]byte +var z14364 [1 << 17]byte +var z14365 [1 << 17]byte +var z14366 [1 << 17]byte +var z14367 [1 << 17]byte +var z14368 [1 << 17]byte +var z14369 [1 << 17]byte +var z14370 [1 << 17]byte +var z14371 [1 << 17]byte +var z14372 [1 << 17]byte +var z14373 [1 << 17]byte +var z14374 [1 << 17]byte +var z14375 [1 << 17]byte +var z14376 [1 << 17]byte +var z14377 [1 << 17]byte +var z14378 [1 << 17]byte +var z14379 [1 << 17]byte +var z14380 [1 << 17]byte +var z14381 [1 << 17]byte +var z14382 [1 << 17]byte +var z14383 [1 << 17]byte +var z14384 [1 << 17]byte +var z14385 [1 << 17]byte +var z14386 [1 << 17]byte +var z14387 [1 << 17]byte +var z14388 [1 << 17]byte +var z14389 [1 << 17]byte +var z14390 [1 << 17]byte +var z14391 [1 << 17]byte +var z14392 [1 << 17]byte +var z14393 [1 << 17]byte +var z14394 [1 << 17]byte +var z14395 [1 << 17]byte +var z14396 [1 << 17]byte +var z14397 [1 << 17]byte +var z14398 [1 << 17]byte +var z14399 [1 << 17]byte +var z14400 [1 << 17]byte +var z14401 [1 << 17]byte +var z14402 [1 << 17]byte +var z14403 [1 << 17]byte +var z14404 [1 << 17]byte +var z14405 [1 << 17]byte +var z14406 [1 << 17]byte +var z14407 [1 << 17]byte +var z14408 [1 << 17]byte +var z14409 [1 << 17]byte +var z14410 [1 << 17]byte +var z14411 [1 << 17]byte +var z14412 [1 << 17]byte +var z14413 [1 << 17]byte +var z14414 [1 << 17]byte +var z14415 [1 << 17]byte +var z14416 [1 << 17]byte +var z14417 [1 << 17]byte +var z14418 [1 << 17]byte +var z14419 [1 << 17]byte +var z14420 [1 << 17]byte +var z14421 [1 << 17]byte +var z14422 [1 << 17]byte +var z14423 [1 << 17]byte +var z14424 [1 << 17]byte +var z14425 [1 << 17]byte +var z14426 [1 << 17]byte +var z14427 [1 << 17]byte +var z14428 [1 << 17]byte +var z14429 [1 << 17]byte +var z14430 [1 << 17]byte +var z14431 [1 << 17]byte +var z14432 [1 << 17]byte +var z14433 [1 << 17]byte +var z14434 [1 << 17]byte +var z14435 [1 << 17]byte +var z14436 [1 << 17]byte +var z14437 [1 << 17]byte +var z14438 [1 << 17]byte +var z14439 [1 << 17]byte +var z14440 [1 << 17]byte +var z14441 [1 << 17]byte +var z14442 [1 << 17]byte +var z14443 [1 << 17]byte +var z14444 [1 << 17]byte +var z14445 [1 << 17]byte +var z14446 [1 << 17]byte +var z14447 [1 << 17]byte +var z14448 [1 << 17]byte +var z14449 [1 << 17]byte +var z14450 [1 << 17]byte +var z14451 [1 << 17]byte +var z14452 [1 << 17]byte +var z14453 [1 << 17]byte +var z14454 [1 << 17]byte +var z14455 [1 << 17]byte +var z14456 [1 << 17]byte +var z14457 [1 << 17]byte +var z14458 [1 << 17]byte +var z14459 [1 << 17]byte +var z14460 [1 << 17]byte +var z14461 [1 << 17]byte +var z14462 [1 << 17]byte +var z14463 [1 << 17]byte +var z14464 [1 << 17]byte +var z14465 [1 << 17]byte +var z14466 [1 << 17]byte +var z14467 [1 << 17]byte +var z14468 [1 << 17]byte +var z14469 [1 << 17]byte +var z14470 [1 << 17]byte +var z14471 [1 << 17]byte +var z14472 [1 << 17]byte +var z14473 [1 << 17]byte +var z14474 [1 << 17]byte +var z14475 [1 << 17]byte +var z14476 [1 << 17]byte +var z14477 [1 << 17]byte +var z14478 [1 << 17]byte +var z14479 [1 << 17]byte +var z14480 [1 << 17]byte +var z14481 [1 << 17]byte +var z14482 [1 << 17]byte +var z14483 [1 << 17]byte +var z14484 [1 << 17]byte +var z14485 [1 << 17]byte +var z14486 [1 << 17]byte +var z14487 [1 << 17]byte +var z14488 [1 << 17]byte +var z14489 [1 << 17]byte +var z14490 [1 << 17]byte +var z14491 [1 << 17]byte +var z14492 [1 << 17]byte +var z14493 [1 << 17]byte +var z14494 [1 << 17]byte +var z14495 [1 << 17]byte +var z14496 [1 << 17]byte +var z14497 [1 << 17]byte +var z14498 [1 << 17]byte +var z14499 [1 << 17]byte +var z14500 [1 << 17]byte +var z14501 [1 << 17]byte +var z14502 [1 << 17]byte +var z14503 [1 << 17]byte +var z14504 [1 << 17]byte +var z14505 [1 << 17]byte +var z14506 [1 << 17]byte +var z14507 [1 << 17]byte +var z14508 [1 << 17]byte +var z14509 [1 << 17]byte +var z14510 [1 << 17]byte +var z14511 [1 << 17]byte +var z14512 [1 << 17]byte +var z14513 [1 << 17]byte +var z14514 [1 << 17]byte +var z14515 [1 << 17]byte +var z14516 [1 << 17]byte +var z14517 [1 << 17]byte +var z14518 [1 << 17]byte +var z14519 [1 << 17]byte +var z14520 [1 << 17]byte +var z14521 [1 << 17]byte +var z14522 [1 << 17]byte +var z14523 [1 << 17]byte +var z14524 [1 << 17]byte +var z14525 [1 << 17]byte +var z14526 [1 << 17]byte +var z14527 [1 << 17]byte +var z14528 [1 << 17]byte +var z14529 [1 << 17]byte +var z14530 [1 << 17]byte +var z14531 [1 << 17]byte +var z14532 [1 << 17]byte +var z14533 [1 << 17]byte +var z14534 [1 << 17]byte +var z14535 [1 << 17]byte +var z14536 [1 << 17]byte +var z14537 [1 << 17]byte +var z14538 [1 << 17]byte +var z14539 [1 << 17]byte +var z14540 [1 << 17]byte +var z14541 [1 << 17]byte +var z14542 [1 << 17]byte +var z14543 [1 << 17]byte +var z14544 [1 << 17]byte +var z14545 [1 << 17]byte +var z14546 [1 << 17]byte +var z14547 [1 << 17]byte +var z14548 [1 << 17]byte +var z14549 [1 << 17]byte +var z14550 [1 << 17]byte +var z14551 [1 << 17]byte +var z14552 [1 << 17]byte +var z14553 [1 << 17]byte +var z14554 [1 << 17]byte +var z14555 [1 << 17]byte +var z14556 [1 << 17]byte +var z14557 [1 << 17]byte +var z14558 [1 << 17]byte +var z14559 [1 << 17]byte +var z14560 [1 << 17]byte +var z14561 [1 << 17]byte +var z14562 [1 << 17]byte +var z14563 [1 << 17]byte +var z14564 [1 << 17]byte +var z14565 [1 << 17]byte +var z14566 [1 << 17]byte +var z14567 [1 << 17]byte +var z14568 [1 << 17]byte +var z14569 [1 << 17]byte +var z14570 [1 << 17]byte +var z14571 [1 << 17]byte +var z14572 [1 << 17]byte +var z14573 [1 << 17]byte +var z14574 [1 << 17]byte +var z14575 [1 << 17]byte +var z14576 [1 << 17]byte +var z14577 [1 << 17]byte +var z14578 [1 << 17]byte +var z14579 [1 << 17]byte +var z14580 [1 << 17]byte +var z14581 [1 << 17]byte +var z14582 [1 << 17]byte +var z14583 [1 << 17]byte +var z14584 [1 << 17]byte +var z14585 [1 << 17]byte +var z14586 [1 << 17]byte +var z14587 [1 << 17]byte +var z14588 [1 << 17]byte +var z14589 [1 << 17]byte +var z14590 [1 << 17]byte +var z14591 [1 << 17]byte +var z14592 [1 << 17]byte +var z14593 [1 << 17]byte +var z14594 [1 << 17]byte +var z14595 [1 << 17]byte +var z14596 [1 << 17]byte +var z14597 [1 << 17]byte +var z14598 [1 << 17]byte +var z14599 [1 << 17]byte +var z14600 [1 << 17]byte +var z14601 [1 << 17]byte +var z14602 [1 << 17]byte +var z14603 [1 << 17]byte +var z14604 [1 << 17]byte +var z14605 [1 << 17]byte +var z14606 [1 << 17]byte +var z14607 [1 << 17]byte +var z14608 [1 << 17]byte +var z14609 [1 << 17]byte +var z14610 [1 << 17]byte +var z14611 [1 << 17]byte +var z14612 [1 << 17]byte +var z14613 [1 << 17]byte +var z14614 [1 << 17]byte +var z14615 [1 << 17]byte +var z14616 [1 << 17]byte +var z14617 [1 << 17]byte +var z14618 [1 << 17]byte +var z14619 [1 << 17]byte +var z14620 [1 << 17]byte +var z14621 [1 << 17]byte +var z14622 [1 << 17]byte +var z14623 [1 << 17]byte +var z14624 [1 << 17]byte +var z14625 [1 << 17]byte +var z14626 [1 << 17]byte +var z14627 [1 << 17]byte +var z14628 [1 << 17]byte +var z14629 [1 << 17]byte +var z14630 [1 << 17]byte +var z14631 [1 << 17]byte +var z14632 [1 << 17]byte +var z14633 [1 << 17]byte +var z14634 [1 << 17]byte +var z14635 [1 << 17]byte +var z14636 [1 << 17]byte +var z14637 [1 << 17]byte +var z14638 [1 << 17]byte +var z14639 [1 << 17]byte +var z14640 [1 << 17]byte +var z14641 [1 << 17]byte +var z14642 [1 << 17]byte +var z14643 [1 << 17]byte +var z14644 [1 << 17]byte +var z14645 [1 << 17]byte +var z14646 [1 << 17]byte +var z14647 [1 << 17]byte +var z14648 [1 << 17]byte +var z14649 [1 << 17]byte +var z14650 [1 << 17]byte +var z14651 [1 << 17]byte +var z14652 [1 << 17]byte +var z14653 [1 << 17]byte +var z14654 [1 << 17]byte +var z14655 [1 << 17]byte +var z14656 [1 << 17]byte +var z14657 [1 << 17]byte +var z14658 [1 << 17]byte +var z14659 [1 << 17]byte +var z14660 [1 << 17]byte +var z14661 [1 << 17]byte +var z14662 [1 << 17]byte +var z14663 [1 << 17]byte +var z14664 [1 << 17]byte +var z14665 [1 << 17]byte +var z14666 [1 << 17]byte +var z14667 [1 << 17]byte +var z14668 [1 << 17]byte +var z14669 [1 << 17]byte +var z14670 [1 << 17]byte +var z14671 [1 << 17]byte +var z14672 [1 << 17]byte +var z14673 [1 << 17]byte +var z14674 [1 << 17]byte +var z14675 [1 << 17]byte +var z14676 [1 << 17]byte +var z14677 [1 << 17]byte +var z14678 [1 << 17]byte +var z14679 [1 << 17]byte +var z14680 [1 << 17]byte +var z14681 [1 << 17]byte +var z14682 [1 << 17]byte +var z14683 [1 << 17]byte +var z14684 [1 << 17]byte +var z14685 [1 << 17]byte +var z14686 [1 << 17]byte +var z14687 [1 << 17]byte +var z14688 [1 << 17]byte +var z14689 [1 << 17]byte +var z14690 [1 << 17]byte +var z14691 [1 << 17]byte +var z14692 [1 << 17]byte +var z14693 [1 << 17]byte +var z14694 [1 << 17]byte +var z14695 [1 << 17]byte +var z14696 [1 << 17]byte +var z14697 [1 << 17]byte +var z14698 [1 << 17]byte +var z14699 [1 << 17]byte +var z14700 [1 << 17]byte +var z14701 [1 << 17]byte +var z14702 [1 << 17]byte +var z14703 [1 << 17]byte +var z14704 [1 << 17]byte +var z14705 [1 << 17]byte +var z14706 [1 << 17]byte +var z14707 [1 << 17]byte +var z14708 [1 << 17]byte +var z14709 [1 << 17]byte +var z14710 [1 << 17]byte +var z14711 [1 << 17]byte +var z14712 [1 << 17]byte +var z14713 [1 << 17]byte +var z14714 [1 << 17]byte +var z14715 [1 << 17]byte +var z14716 [1 << 17]byte +var z14717 [1 << 17]byte +var z14718 [1 << 17]byte +var z14719 [1 << 17]byte +var z14720 [1 << 17]byte +var z14721 [1 << 17]byte +var z14722 [1 << 17]byte +var z14723 [1 << 17]byte +var z14724 [1 << 17]byte +var z14725 [1 << 17]byte +var z14726 [1 << 17]byte +var z14727 [1 << 17]byte +var z14728 [1 << 17]byte +var z14729 [1 << 17]byte +var z14730 [1 << 17]byte +var z14731 [1 << 17]byte +var z14732 [1 << 17]byte +var z14733 [1 << 17]byte +var z14734 [1 << 17]byte +var z14735 [1 << 17]byte +var z14736 [1 << 17]byte +var z14737 [1 << 17]byte +var z14738 [1 << 17]byte +var z14739 [1 << 17]byte +var z14740 [1 << 17]byte +var z14741 [1 << 17]byte +var z14742 [1 << 17]byte +var z14743 [1 << 17]byte +var z14744 [1 << 17]byte +var z14745 [1 << 17]byte +var z14746 [1 << 17]byte +var z14747 [1 << 17]byte +var z14748 [1 << 17]byte +var z14749 [1 << 17]byte +var z14750 [1 << 17]byte +var z14751 [1 << 17]byte +var z14752 [1 << 17]byte +var z14753 [1 << 17]byte +var z14754 [1 << 17]byte +var z14755 [1 << 17]byte +var z14756 [1 << 17]byte +var z14757 [1 << 17]byte +var z14758 [1 << 17]byte +var z14759 [1 << 17]byte +var z14760 [1 << 17]byte +var z14761 [1 << 17]byte +var z14762 [1 << 17]byte +var z14763 [1 << 17]byte +var z14764 [1 << 17]byte +var z14765 [1 << 17]byte +var z14766 [1 << 17]byte +var z14767 [1 << 17]byte +var z14768 [1 << 17]byte +var z14769 [1 << 17]byte +var z14770 [1 << 17]byte +var z14771 [1 << 17]byte +var z14772 [1 << 17]byte +var z14773 [1 << 17]byte +var z14774 [1 << 17]byte +var z14775 [1 << 17]byte +var z14776 [1 << 17]byte +var z14777 [1 << 17]byte +var z14778 [1 << 17]byte +var z14779 [1 << 17]byte +var z14780 [1 << 17]byte +var z14781 [1 << 17]byte +var z14782 [1 << 17]byte +var z14783 [1 << 17]byte +var z14784 [1 << 17]byte +var z14785 [1 << 17]byte +var z14786 [1 << 17]byte +var z14787 [1 << 17]byte +var z14788 [1 << 17]byte +var z14789 [1 << 17]byte +var z14790 [1 << 17]byte +var z14791 [1 << 17]byte +var z14792 [1 << 17]byte +var z14793 [1 << 17]byte +var z14794 [1 << 17]byte +var z14795 [1 << 17]byte +var z14796 [1 << 17]byte +var z14797 [1 << 17]byte +var z14798 [1 << 17]byte +var z14799 [1 << 17]byte +var z14800 [1 << 17]byte +var z14801 [1 << 17]byte +var z14802 [1 << 17]byte +var z14803 [1 << 17]byte +var z14804 [1 << 17]byte +var z14805 [1 << 17]byte +var z14806 [1 << 17]byte +var z14807 [1 << 17]byte +var z14808 [1 << 17]byte +var z14809 [1 << 17]byte +var z14810 [1 << 17]byte +var z14811 [1 << 17]byte +var z14812 [1 << 17]byte +var z14813 [1 << 17]byte +var z14814 [1 << 17]byte +var z14815 [1 << 17]byte +var z14816 [1 << 17]byte +var z14817 [1 << 17]byte +var z14818 [1 << 17]byte +var z14819 [1 << 17]byte +var z14820 [1 << 17]byte +var z14821 [1 << 17]byte +var z14822 [1 << 17]byte +var z14823 [1 << 17]byte +var z14824 [1 << 17]byte +var z14825 [1 << 17]byte +var z14826 [1 << 17]byte +var z14827 [1 << 17]byte +var z14828 [1 << 17]byte +var z14829 [1 << 17]byte +var z14830 [1 << 17]byte +var z14831 [1 << 17]byte +var z14832 [1 << 17]byte +var z14833 [1 << 17]byte +var z14834 [1 << 17]byte +var z14835 [1 << 17]byte +var z14836 [1 << 17]byte +var z14837 [1 << 17]byte +var z14838 [1 << 17]byte +var z14839 [1 << 17]byte +var z14840 [1 << 17]byte +var z14841 [1 << 17]byte +var z14842 [1 << 17]byte +var z14843 [1 << 17]byte +var z14844 [1 << 17]byte +var z14845 [1 << 17]byte +var z14846 [1 << 17]byte +var z14847 [1 << 17]byte +var z14848 [1 << 17]byte +var z14849 [1 << 17]byte +var z14850 [1 << 17]byte +var z14851 [1 << 17]byte +var z14852 [1 << 17]byte +var z14853 [1 << 17]byte +var z14854 [1 << 17]byte +var z14855 [1 << 17]byte +var z14856 [1 << 17]byte +var z14857 [1 << 17]byte +var z14858 [1 << 17]byte +var z14859 [1 << 17]byte +var z14860 [1 << 17]byte +var z14861 [1 << 17]byte +var z14862 [1 << 17]byte +var z14863 [1 << 17]byte +var z14864 [1 << 17]byte +var z14865 [1 << 17]byte +var z14866 [1 << 17]byte +var z14867 [1 << 17]byte +var z14868 [1 << 17]byte +var z14869 [1 << 17]byte +var z14870 [1 << 17]byte +var z14871 [1 << 17]byte +var z14872 [1 << 17]byte +var z14873 [1 << 17]byte +var z14874 [1 << 17]byte +var z14875 [1 << 17]byte +var z14876 [1 << 17]byte +var z14877 [1 << 17]byte +var z14878 [1 << 17]byte +var z14879 [1 << 17]byte +var z14880 [1 << 17]byte +var z14881 [1 << 17]byte +var z14882 [1 << 17]byte +var z14883 [1 << 17]byte +var z14884 [1 << 17]byte +var z14885 [1 << 17]byte +var z14886 [1 << 17]byte +var z14887 [1 << 17]byte +var z14888 [1 << 17]byte +var z14889 [1 << 17]byte +var z14890 [1 << 17]byte +var z14891 [1 << 17]byte +var z14892 [1 << 17]byte +var z14893 [1 << 17]byte +var z14894 [1 << 17]byte +var z14895 [1 << 17]byte +var z14896 [1 << 17]byte +var z14897 [1 << 17]byte +var z14898 [1 << 17]byte +var z14899 [1 << 17]byte +var z14900 [1 << 17]byte +var z14901 [1 << 17]byte +var z14902 [1 << 17]byte +var z14903 [1 << 17]byte +var z14904 [1 << 17]byte +var z14905 [1 << 17]byte +var z14906 [1 << 17]byte +var z14907 [1 << 17]byte +var z14908 [1 << 17]byte +var z14909 [1 << 17]byte +var z14910 [1 << 17]byte +var z14911 [1 << 17]byte +var z14912 [1 << 17]byte +var z14913 [1 << 17]byte +var z14914 [1 << 17]byte +var z14915 [1 << 17]byte +var z14916 [1 << 17]byte +var z14917 [1 << 17]byte +var z14918 [1 << 17]byte +var z14919 [1 << 17]byte +var z14920 [1 << 17]byte +var z14921 [1 << 17]byte +var z14922 [1 << 17]byte +var z14923 [1 << 17]byte +var z14924 [1 << 17]byte +var z14925 [1 << 17]byte +var z14926 [1 << 17]byte +var z14927 [1 << 17]byte +var z14928 [1 << 17]byte +var z14929 [1 << 17]byte +var z14930 [1 << 17]byte +var z14931 [1 << 17]byte +var z14932 [1 << 17]byte +var z14933 [1 << 17]byte +var z14934 [1 << 17]byte +var z14935 [1 << 17]byte +var z14936 [1 << 17]byte +var z14937 [1 << 17]byte +var z14938 [1 << 17]byte +var z14939 [1 << 17]byte +var z14940 [1 << 17]byte +var z14941 [1 << 17]byte +var z14942 [1 << 17]byte +var z14943 [1 << 17]byte +var z14944 [1 << 17]byte +var z14945 [1 << 17]byte +var z14946 [1 << 17]byte +var z14947 [1 << 17]byte +var z14948 [1 << 17]byte +var z14949 [1 << 17]byte +var z14950 [1 << 17]byte +var z14951 [1 << 17]byte +var z14952 [1 << 17]byte +var z14953 [1 << 17]byte +var z14954 [1 << 17]byte +var z14955 [1 << 17]byte +var z14956 [1 << 17]byte +var z14957 [1 << 17]byte +var z14958 [1 << 17]byte +var z14959 [1 << 17]byte +var z14960 [1 << 17]byte +var z14961 [1 << 17]byte +var z14962 [1 << 17]byte +var z14963 [1 << 17]byte +var z14964 [1 << 17]byte +var z14965 [1 << 17]byte +var z14966 [1 << 17]byte +var z14967 [1 << 17]byte +var z14968 [1 << 17]byte +var z14969 [1 << 17]byte +var z14970 [1 << 17]byte +var z14971 [1 << 17]byte +var z14972 [1 << 17]byte +var z14973 [1 << 17]byte +var z14974 [1 << 17]byte +var z14975 [1 << 17]byte +var z14976 [1 << 17]byte +var z14977 [1 << 17]byte +var z14978 [1 << 17]byte +var z14979 [1 << 17]byte +var z14980 [1 << 17]byte +var z14981 [1 << 17]byte +var z14982 [1 << 17]byte +var z14983 [1 << 17]byte +var z14984 [1 << 17]byte +var z14985 [1 << 17]byte +var z14986 [1 << 17]byte +var z14987 [1 << 17]byte +var z14988 [1 << 17]byte +var z14989 [1 << 17]byte +var z14990 [1 << 17]byte +var z14991 [1 << 17]byte +var z14992 [1 << 17]byte +var z14993 [1 << 17]byte +var z14994 [1 << 17]byte +var z14995 [1 << 17]byte +var z14996 [1 << 17]byte +var z14997 [1 << 17]byte +var z14998 [1 << 17]byte +var z14999 [1 << 17]byte +var z15000 [1 << 17]byte +var z15001 [1 << 17]byte +var z15002 [1 << 17]byte +var z15003 [1 << 17]byte +var z15004 [1 << 17]byte +var z15005 [1 << 17]byte +var z15006 [1 << 17]byte +var z15007 [1 << 17]byte +var z15008 [1 << 17]byte +var z15009 [1 << 17]byte +var z15010 [1 << 17]byte +var z15011 [1 << 17]byte +var z15012 [1 << 17]byte +var z15013 [1 << 17]byte +var z15014 [1 << 17]byte +var z15015 [1 << 17]byte +var z15016 [1 << 17]byte +var z15017 [1 << 17]byte +var z15018 [1 << 17]byte +var z15019 [1 << 17]byte +var z15020 [1 << 17]byte +var z15021 [1 << 17]byte +var z15022 [1 << 17]byte +var z15023 [1 << 17]byte +var z15024 [1 << 17]byte +var z15025 [1 << 17]byte +var z15026 [1 << 17]byte +var z15027 [1 << 17]byte +var z15028 [1 << 17]byte +var z15029 [1 << 17]byte +var z15030 [1 << 17]byte +var z15031 [1 << 17]byte +var z15032 [1 << 17]byte +var z15033 [1 << 17]byte +var z15034 [1 << 17]byte +var z15035 [1 << 17]byte +var z15036 [1 << 17]byte +var z15037 [1 << 17]byte +var z15038 [1 << 17]byte +var z15039 [1 << 17]byte +var z15040 [1 << 17]byte +var z15041 [1 << 17]byte +var z15042 [1 << 17]byte +var z15043 [1 << 17]byte +var z15044 [1 << 17]byte +var z15045 [1 << 17]byte +var z15046 [1 << 17]byte +var z15047 [1 << 17]byte +var z15048 [1 << 17]byte +var z15049 [1 << 17]byte +var z15050 [1 << 17]byte +var z15051 [1 << 17]byte +var z15052 [1 << 17]byte +var z15053 [1 << 17]byte +var z15054 [1 << 17]byte +var z15055 [1 << 17]byte +var z15056 [1 << 17]byte +var z15057 [1 << 17]byte +var z15058 [1 << 17]byte +var z15059 [1 << 17]byte +var z15060 [1 << 17]byte +var z15061 [1 << 17]byte +var z15062 [1 << 17]byte +var z15063 [1 << 17]byte +var z15064 [1 << 17]byte +var z15065 [1 << 17]byte +var z15066 [1 << 17]byte +var z15067 [1 << 17]byte +var z15068 [1 << 17]byte +var z15069 [1 << 17]byte +var z15070 [1 << 17]byte +var z15071 [1 << 17]byte +var z15072 [1 << 17]byte +var z15073 [1 << 17]byte +var z15074 [1 << 17]byte +var z15075 [1 << 17]byte +var z15076 [1 << 17]byte +var z15077 [1 << 17]byte +var z15078 [1 << 17]byte +var z15079 [1 << 17]byte +var z15080 [1 << 17]byte +var z15081 [1 << 17]byte +var z15082 [1 << 17]byte +var z15083 [1 << 17]byte +var z15084 [1 << 17]byte +var z15085 [1 << 17]byte +var z15086 [1 << 17]byte +var z15087 [1 << 17]byte +var z15088 [1 << 17]byte +var z15089 [1 << 17]byte +var z15090 [1 << 17]byte +var z15091 [1 << 17]byte +var z15092 [1 << 17]byte +var z15093 [1 << 17]byte +var z15094 [1 << 17]byte +var z15095 [1 << 17]byte +var z15096 [1 << 17]byte +var z15097 [1 << 17]byte +var z15098 [1 << 17]byte +var z15099 [1 << 17]byte +var z15100 [1 << 17]byte +var z15101 [1 << 17]byte +var z15102 [1 << 17]byte +var z15103 [1 << 17]byte +var z15104 [1 << 17]byte +var z15105 [1 << 17]byte +var z15106 [1 << 17]byte +var z15107 [1 << 17]byte +var z15108 [1 << 17]byte +var z15109 [1 << 17]byte +var z15110 [1 << 17]byte +var z15111 [1 << 17]byte +var z15112 [1 << 17]byte +var z15113 [1 << 17]byte +var z15114 [1 << 17]byte +var z15115 [1 << 17]byte +var z15116 [1 << 17]byte +var z15117 [1 << 17]byte +var z15118 [1 << 17]byte +var z15119 [1 << 17]byte +var z15120 [1 << 17]byte +var z15121 [1 << 17]byte +var z15122 [1 << 17]byte +var z15123 [1 << 17]byte +var z15124 [1 << 17]byte +var z15125 [1 << 17]byte +var z15126 [1 << 17]byte +var z15127 [1 << 17]byte +var z15128 [1 << 17]byte +var z15129 [1 << 17]byte +var z15130 [1 << 17]byte +var z15131 [1 << 17]byte +var z15132 [1 << 17]byte +var z15133 [1 << 17]byte +var z15134 [1 << 17]byte +var z15135 [1 << 17]byte +var z15136 [1 << 17]byte +var z15137 [1 << 17]byte +var z15138 [1 << 17]byte +var z15139 [1 << 17]byte +var z15140 [1 << 17]byte +var z15141 [1 << 17]byte +var z15142 [1 << 17]byte +var z15143 [1 << 17]byte +var z15144 [1 << 17]byte +var z15145 [1 << 17]byte +var z15146 [1 << 17]byte +var z15147 [1 << 17]byte +var z15148 [1 << 17]byte +var z15149 [1 << 17]byte +var z15150 [1 << 17]byte +var z15151 [1 << 17]byte +var z15152 [1 << 17]byte +var z15153 [1 << 17]byte +var z15154 [1 << 17]byte +var z15155 [1 << 17]byte +var z15156 [1 << 17]byte +var z15157 [1 << 17]byte +var z15158 [1 << 17]byte +var z15159 [1 << 17]byte +var z15160 [1 << 17]byte +var z15161 [1 << 17]byte +var z15162 [1 << 17]byte +var z15163 [1 << 17]byte +var z15164 [1 << 17]byte +var z15165 [1 << 17]byte +var z15166 [1 << 17]byte +var z15167 [1 << 17]byte +var z15168 [1 << 17]byte +var z15169 [1 << 17]byte +var z15170 [1 << 17]byte +var z15171 [1 << 17]byte +var z15172 [1 << 17]byte +var z15173 [1 << 17]byte +var z15174 [1 << 17]byte +var z15175 [1 << 17]byte +var z15176 [1 << 17]byte +var z15177 [1 << 17]byte +var z15178 [1 << 17]byte +var z15179 [1 << 17]byte +var z15180 [1 << 17]byte +var z15181 [1 << 17]byte +var z15182 [1 << 17]byte +var z15183 [1 << 17]byte +var z15184 [1 << 17]byte +var z15185 [1 << 17]byte +var z15186 [1 << 17]byte +var z15187 [1 << 17]byte +var z15188 [1 << 17]byte +var z15189 [1 << 17]byte +var z15190 [1 << 17]byte +var z15191 [1 << 17]byte +var z15192 [1 << 17]byte +var z15193 [1 << 17]byte +var z15194 [1 << 17]byte +var z15195 [1 << 17]byte +var z15196 [1 << 17]byte +var z15197 [1 << 17]byte +var z15198 [1 << 17]byte +var z15199 [1 << 17]byte +var z15200 [1 << 17]byte +var z15201 [1 << 17]byte +var z15202 [1 << 17]byte +var z15203 [1 << 17]byte +var z15204 [1 << 17]byte +var z15205 [1 << 17]byte +var z15206 [1 << 17]byte +var z15207 [1 << 17]byte +var z15208 [1 << 17]byte +var z15209 [1 << 17]byte +var z15210 [1 << 17]byte +var z15211 [1 << 17]byte +var z15212 [1 << 17]byte +var z15213 [1 << 17]byte +var z15214 [1 << 17]byte +var z15215 [1 << 17]byte +var z15216 [1 << 17]byte +var z15217 [1 << 17]byte +var z15218 [1 << 17]byte +var z15219 [1 << 17]byte +var z15220 [1 << 17]byte +var z15221 [1 << 17]byte +var z15222 [1 << 17]byte +var z15223 [1 << 17]byte +var z15224 [1 << 17]byte +var z15225 [1 << 17]byte +var z15226 [1 << 17]byte +var z15227 [1 << 17]byte +var z15228 [1 << 17]byte +var z15229 [1 << 17]byte +var z15230 [1 << 17]byte +var z15231 [1 << 17]byte +var z15232 [1 << 17]byte +var z15233 [1 << 17]byte +var z15234 [1 << 17]byte +var z15235 [1 << 17]byte +var z15236 [1 << 17]byte +var z15237 [1 << 17]byte +var z15238 [1 << 17]byte +var z15239 [1 << 17]byte +var z15240 [1 << 17]byte +var z15241 [1 << 17]byte +var z15242 [1 << 17]byte +var z15243 [1 << 17]byte +var z15244 [1 << 17]byte +var z15245 [1 << 17]byte +var z15246 [1 << 17]byte +var z15247 [1 << 17]byte +var z15248 [1 << 17]byte +var z15249 [1 << 17]byte +var z15250 [1 << 17]byte +var z15251 [1 << 17]byte +var z15252 [1 << 17]byte +var z15253 [1 << 17]byte +var z15254 [1 << 17]byte +var z15255 [1 << 17]byte +var z15256 [1 << 17]byte +var z15257 [1 << 17]byte +var z15258 [1 << 17]byte +var z15259 [1 << 17]byte +var z15260 [1 << 17]byte +var z15261 [1 << 17]byte +var z15262 [1 << 17]byte +var z15263 [1 << 17]byte +var z15264 [1 << 17]byte +var z15265 [1 << 17]byte +var z15266 [1 << 17]byte +var z15267 [1 << 17]byte +var z15268 [1 << 17]byte +var z15269 [1 << 17]byte +var z15270 [1 << 17]byte +var z15271 [1 << 17]byte +var z15272 [1 << 17]byte +var z15273 [1 << 17]byte +var z15274 [1 << 17]byte +var z15275 [1 << 17]byte +var z15276 [1 << 17]byte +var z15277 [1 << 17]byte +var z15278 [1 << 17]byte +var z15279 [1 << 17]byte +var z15280 [1 << 17]byte +var z15281 [1 << 17]byte +var z15282 [1 << 17]byte +var z15283 [1 << 17]byte +var z15284 [1 << 17]byte +var z15285 [1 << 17]byte +var z15286 [1 << 17]byte +var z15287 [1 << 17]byte +var z15288 [1 << 17]byte +var z15289 [1 << 17]byte +var z15290 [1 << 17]byte +var z15291 [1 << 17]byte +var z15292 [1 << 17]byte +var z15293 [1 << 17]byte +var z15294 [1 << 17]byte +var z15295 [1 << 17]byte +var z15296 [1 << 17]byte +var z15297 [1 << 17]byte +var z15298 [1 << 17]byte +var z15299 [1 << 17]byte +var z15300 [1 << 17]byte +var z15301 [1 << 17]byte +var z15302 [1 << 17]byte +var z15303 [1 << 17]byte +var z15304 [1 << 17]byte +var z15305 [1 << 17]byte +var z15306 [1 << 17]byte +var z15307 [1 << 17]byte +var z15308 [1 << 17]byte +var z15309 [1 << 17]byte +var z15310 [1 << 17]byte +var z15311 [1 << 17]byte +var z15312 [1 << 17]byte +var z15313 [1 << 17]byte +var z15314 [1 << 17]byte +var z15315 [1 << 17]byte +var z15316 [1 << 17]byte +var z15317 [1 << 17]byte +var z15318 [1 << 17]byte +var z15319 [1 << 17]byte +var z15320 [1 << 17]byte +var z15321 [1 << 17]byte +var z15322 [1 << 17]byte +var z15323 [1 << 17]byte +var z15324 [1 << 17]byte +var z15325 [1 << 17]byte +var z15326 [1 << 17]byte +var z15327 [1 << 17]byte +var z15328 [1 << 17]byte +var z15329 [1 << 17]byte +var z15330 [1 << 17]byte +var z15331 [1 << 17]byte +var z15332 [1 << 17]byte +var z15333 [1 << 17]byte +var z15334 [1 << 17]byte +var z15335 [1 << 17]byte +var z15336 [1 << 17]byte +var z15337 [1 << 17]byte +var z15338 [1 << 17]byte +var z15339 [1 << 17]byte +var z15340 [1 << 17]byte +var z15341 [1 << 17]byte +var z15342 [1 << 17]byte +var z15343 [1 << 17]byte +var z15344 [1 << 17]byte +var z15345 [1 << 17]byte +var z15346 [1 << 17]byte +var z15347 [1 << 17]byte +var z15348 [1 << 17]byte +var z15349 [1 << 17]byte +var z15350 [1 << 17]byte +var z15351 [1 << 17]byte +var z15352 [1 << 17]byte +var z15353 [1 << 17]byte +var z15354 [1 << 17]byte +var z15355 [1 << 17]byte +var z15356 [1 << 17]byte +var z15357 [1 << 17]byte +var z15358 [1 << 17]byte +var z15359 [1 << 17]byte +var z15360 [1 << 17]byte +var z15361 [1 << 17]byte +var z15362 [1 << 17]byte +var z15363 [1 << 17]byte +var z15364 [1 << 17]byte +var z15365 [1 << 17]byte +var z15366 [1 << 17]byte +var z15367 [1 << 17]byte +var z15368 [1 << 17]byte +var z15369 [1 << 17]byte +var z15370 [1 << 17]byte +var z15371 [1 << 17]byte +var z15372 [1 << 17]byte +var z15373 [1 << 17]byte +var z15374 [1 << 17]byte +var z15375 [1 << 17]byte +var z15376 [1 << 17]byte +var z15377 [1 << 17]byte +var z15378 [1 << 17]byte +var z15379 [1 << 17]byte +var z15380 [1 << 17]byte +var z15381 [1 << 17]byte +var z15382 [1 << 17]byte +var z15383 [1 << 17]byte +var z15384 [1 << 17]byte +var z15385 [1 << 17]byte +var z15386 [1 << 17]byte +var z15387 [1 << 17]byte +var z15388 [1 << 17]byte +var z15389 [1 << 17]byte +var z15390 [1 << 17]byte +var z15391 [1 << 17]byte +var z15392 [1 << 17]byte +var z15393 [1 << 17]byte +var z15394 [1 << 17]byte +var z15395 [1 << 17]byte +var z15396 [1 << 17]byte +var z15397 [1 << 17]byte +var z15398 [1 << 17]byte +var z15399 [1 << 17]byte +var z15400 [1 << 17]byte +var z15401 [1 << 17]byte +var z15402 [1 << 17]byte +var z15403 [1 << 17]byte +var z15404 [1 << 17]byte +var z15405 [1 << 17]byte +var z15406 [1 << 17]byte +var z15407 [1 << 17]byte +var z15408 [1 << 17]byte +var z15409 [1 << 17]byte +var z15410 [1 << 17]byte +var z15411 [1 << 17]byte +var z15412 [1 << 17]byte +var z15413 [1 << 17]byte +var z15414 [1 << 17]byte +var z15415 [1 << 17]byte +var z15416 [1 << 17]byte +var z15417 [1 << 17]byte +var z15418 [1 << 17]byte +var z15419 [1 << 17]byte +var z15420 [1 << 17]byte +var z15421 [1 << 17]byte +var z15422 [1 << 17]byte +var z15423 [1 << 17]byte +var z15424 [1 << 17]byte +var z15425 [1 << 17]byte +var z15426 [1 << 17]byte +var z15427 [1 << 17]byte +var z15428 [1 << 17]byte +var z15429 [1 << 17]byte +var z15430 [1 << 17]byte +var z15431 [1 << 17]byte +var z15432 [1 << 17]byte +var z15433 [1 << 17]byte +var z15434 [1 << 17]byte +var z15435 [1 << 17]byte +var z15436 [1 << 17]byte +var z15437 [1 << 17]byte +var z15438 [1 << 17]byte +var z15439 [1 << 17]byte +var z15440 [1 << 17]byte +var z15441 [1 << 17]byte +var z15442 [1 << 17]byte +var z15443 [1 << 17]byte +var z15444 [1 << 17]byte +var z15445 [1 << 17]byte +var z15446 [1 << 17]byte +var z15447 [1 << 17]byte +var z15448 [1 << 17]byte +var z15449 [1 << 17]byte +var z15450 [1 << 17]byte +var z15451 [1 << 17]byte +var z15452 [1 << 17]byte +var z15453 [1 << 17]byte +var z15454 [1 << 17]byte +var z15455 [1 << 17]byte +var z15456 [1 << 17]byte +var z15457 [1 << 17]byte +var z15458 [1 << 17]byte +var z15459 [1 << 17]byte +var z15460 [1 << 17]byte +var z15461 [1 << 17]byte +var z15462 [1 << 17]byte +var z15463 [1 << 17]byte +var z15464 [1 << 17]byte +var z15465 [1 << 17]byte +var z15466 [1 << 17]byte +var z15467 [1 << 17]byte +var z15468 [1 << 17]byte +var z15469 [1 << 17]byte +var z15470 [1 << 17]byte +var z15471 [1 << 17]byte +var z15472 [1 << 17]byte +var z15473 [1 << 17]byte +var z15474 [1 << 17]byte +var z15475 [1 << 17]byte +var z15476 [1 << 17]byte +var z15477 [1 << 17]byte +var z15478 [1 << 17]byte +var z15479 [1 << 17]byte +var z15480 [1 << 17]byte +var z15481 [1 << 17]byte +var z15482 [1 << 17]byte +var z15483 [1 << 17]byte +var z15484 [1 << 17]byte +var z15485 [1 << 17]byte +var z15486 [1 << 17]byte +var z15487 [1 << 17]byte +var z15488 [1 << 17]byte +var z15489 [1 << 17]byte +var z15490 [1 << 17]byte +var z15491 [1 << 17]byte +var z15492 [1 << 17]byte +var z15493 [1 << 17]byte +var z15494 [1 << 17]byte +var z15495 [1 << 17]byte +var z15496 [1 << 17]byte +var z15497 [1 << 17]byte +var z15498 [1 << 17]byte +var z15499 [1 << 17]byte +var z15500 [1 << 17]byte +var z15501 [1 << 17]byte +var z15502 [1 << 17]byte +var z15503 [1 << 17]byte +var z15504 [1 << 17]byte +var z15505 [1 << 17]byte +var z15506 [1 << 17]byte +var z15507 [1 << 17]byte +var z15508 [1 << 17]byte +var z15509 [1 << 17]byte +var z15510 [1 << 17]byte +var z15511 [1 << 17]byte +var z15512 [1 << 17]byte +var z15513 [1 << 17]byte +var z15514 [1 << 17]byte +var z15515 [1 << 17]byte +var z15516 [1 << 17]byte +var z15517 [1 << 17]byte +var z15518 [1 << 17]byte +var z15519 [1 << 17]byte +var z15520 [1 << 17]byte +var z15521 [1 << 17]byte +var z15522 [1 << 17]byte +var z15523 [1 << 17]byte +var z15524 [1 << 17]byte +var z15525 [1 << 17]byte +var z15526 [1 << 17]byte +var z15527 [1 << 17]byte +var z15528 [1 << 17]byte +var z15529 [1 << 17]byte +var z15530 [1 << 17]byte +var z15531 [1 << 17]byte +var z15532 [1 << 17]byte +var z15533 [1 << 17]byte +var z15534 [1 << 17]byte +var z15535 [1 << 17]byte +var z15536 [1 << 17]byte +var z15537 [1 << 17]byte +var z15538 [1 << 17]byte +var z15539 [1 << 17]byte +var z15540 [1 << 17]byte +var z15541 [1 << 17]byte +var z15542 [1 << 17]byte +var z15543 [1 << 17]byte +var z15544 [1 << 17]byte +var z15545 [1 << 17]byte +var z15546 [1 << 17]byte +var z15547 [1 << 17]byte +var z15548 [1 << 17]byte +var z15549 [1 << 17]byte +var z15550 [1 << 17]byte +var z15551 [1 << 17]byte +var z15552 [1 << 17]byte +var z15553 [1 << 17]byte +var z15554 [1 << 17]byte +var z15555 [1 << 17]byte +var z15556 [1 << 17]byte +var z15557 [1 << 17]byte +var z15558 [1 << 17]byte +var z15559 [1 << 17]byte +var z15560 [1 << 17]byte +var z15561 [1 << 17]byte +var z15562 [1 << 17]byte +var z15563 [1 << 17]byte +var z15564 [1 << 17]byte +var z15565 [1 << 17]byte +var z15566 [1 << 17]byte +var z15567 [1 << 17]byte +var z15568 [1 << 17]byte +var z15569 [1 << 17]byte +var z15570 [1 << 17]byte +var z15571 [1 << 17]byte +var z15572 [1 << 17]byte +var z15573 [1 << 17]byte +var z15574 [1 << 17]byte +var z15575 [1 << 17]byte +var z15576 [1 << 17]byte +var z15577 [1 << 17]byte +var z15578 [1 << 17]byte +var z15579 [1 << 17]byte +var z15580 [1 << 17]byte +var z15581 [1 << 17]byte +var z15582 [1 << 17]byte +var z15583 [1 << 17]byte +var z15584 [1 << 17]byte +var z15585 [1 << 17]byte +var z15586 [1 << 17]byte +var z15587 [1 << 17]byte +var z15588 [1 << 17]byte +var z15589 [1 << 17]byte +var z15590 [1 << 17]byte +var z15591 [1 << 17]byte +var z15592 [1 << 17]byte +var z15593 [1 << 17]byte +var z15594 [1 << 17]byte +var z15595 [1 << 17]byte +var z15596 [1 << 17]byte +var z15597 [1 << 17]byte +var z15598 [1 << 17]byte +var z15599 [1 << 17]byte +var z15600 [1 << 17]byte +var z15601 [1 << 17]byte +var z15602 [1 << 17]byte +var z15603 [1 << 17]byte +var z15604 [1 << 17]byte +var z15605 [1 << 17]byte +var z15606 [1 << 17]byte +var z15607 [1 << 17]byte +var z15608 [1 << 17]byte +var z15609 [1 << 17]byte +var z15610 [1 << 17]byte +var z15611 [1 << 17]byte +var z15612 [1 << 17]byte +var z15613 [1 << 17]byte +var z15614 [1 << 17]byte +var z15615 [1 << 17]byte +var z15616 [1 << 17]byte +var z15617 [1 << 17]byte +var z15618 [1 << 17]byte +var z15619 [1 << 17]byte +var z15620 [1 << 17]byte +var z15621 [1 << 17]byte +var z15622 [1 << 17]byte +var z15623 [1 << 17]byte +var z15624 [1 << 17]byte +var z15625 [1 << 17]byte +var z15626 [1 << 17]byte +var z15627 [1 << 17]byte +var z15628 [1 << 17]byte +var z15629 [1 << 17]byte +var z15630 [1 << 17]byte +var z15631 [1 << 17]byte +var z15632 [1 << 17]byte +var z15633 [1 << 17]byte +var z15634 [1 << 17]byte +var z15635 [1 << 17]byte +var z15636 [1 << 17]byte +var z15637 [1 << 17]byte +var z15638 [1 << 17]byte +var z15639 [1 << 17]byte +var z15640 [1 << 17]byte +var z15641 [1 << 17]byte +var z15642 [1 << 17]byte +var z15643 [1 << 17]byte +var z15644 [1 << 17]byte +var z15645 [1 << 17]byte +var z15646 [1 << 17]byte +var z15647 [1 << 17]byte +var z15648 [1 << 17]byte +var z15649 [1 << 17]byte +var z15650 [1 << 17]byte +var z15651 [1 << 17]byte +var z15652 [1 << 17]byte +var z15653 [1 << 17]byte +var z15654 [1 << 17]byte +var z15655 [1 << 17]byte +var z15656 [1 << 17]byte +var z15657 [1 << 17]byte +var z15658 [1 << 17]byte +var z15659 [1 << 17]byte +var z15660 [1 << 17]byte +var z15661 [1 << 17]byte +var z15662 [1 << 17]byte +var z15663 [1 << 17]byte +var z15664 [1 << 17]byte +var z15665 [1 << 17]byte +var z15666 [1 << 17]byte +var z15667 [1 << 17]byte +var z15668 [1 << 17]byte +var z15669 [1 << 17]byte +var z15670 [1 << 17]byte +var z15671 [1 << 17]byte +var z15672 [1 << 17]byte +var z15673 [1 << 17]byte +var z15674 [1 << 17]byte +var z15675 [1 << 17]byte +var z15676 [1 << 17]byte +var z15677 [1 << 17]byte +var z15678 [1 << 17]byte +var z15679 [1 << 17]byte +var z15680 [1 << 17]byte +var z15681 [1 << 17]byte +var z15682 [1 << 17]byte +var z15683 [1 << 17]byte +var z15684 [1 << 17]byte +var z15685 [1 << 17]byte +var z15686 [1 << 17]byte +var z15687 [1 << 17]byte +var z15688 [1 << 17]byte +var z15689 [1 << 17]byte +var z15690 [1 << 17]byte +var z15691 [1 << 17]byte +var z15692 [1 << 17]byte +var z15693 [1 << 17]byte +var z15694 [1 << 17]byte +var z15695 [1 << 17]byte +var z15696 [1 << 17]byte +var z15697 [1 << 17]byte +var z15698 [1 << 17]byte +var z15699 [1 << 17]byte +var z15700 [1 << 17]byte +var z15701 [1 << 17]byte +var z15702 [1 << 17]byte +var z15703 [1 << 17]byte +var z15704 [1 << 17]byte +var z15705 [1 << 17]byte +var z15706 [1 << 17]byte +var z15707 [1 << 17]byte +var z15708 [1 << 17]byte +var z15709 [1 << 17]byte +var z15710 [1 << 17]byte +var z15711 [1 << 17]byte +var z15712 [1 << 17]byte +var z15713 [1 << 17]byte +var z15714 [1 << 17]byte +var z15715 [1 << 17]byte +var z15716 [1 << 17]byte +var z15717 [1 << 17]byte +var z15718 [1 << 17]byte +var z15719 [1 << 17]byte +var z15720 [1 << 17]byte +var z15721 [1 << 17]byte +var z15722 [1 << 17]byte +var z15723 [1 << 17]byte +var z15724 [1 << 17]byte +var z15725 [1 << 17]byte +var z15726 [1 << 17]byte +var z15727 [1 << 17]byte +var z15728 [1 << 17]byte +var z15729 [1 << 17]byte +var z15730 [1 << 17]byte +var z15731 [1 << 17]byte +var z15732 [1 << 17]byte +var z15733 [1 << 17]byte +var z15734 [1 << 17]byte +var z15735 [1 << 17]byte +var z15736 [1 << 17]byte +var z15737 [1 << 17]byte +var z15738 [1 << 17]byte +var z15739 [1 << 17]byte +var z15740 [1 << 17]byte +var z15741 [1 << 17]byte +var z15742 [1 << 17]byte +var z15743 [1 << 17]byte +var z15744 [1 << 17]byte +var z15745 [1 << 17]byte +var z15746 [1 << 17]byte +var z15747 [1 << 17]byte +var z15748 [1 << 17]byte +var z15749 [1 << 17]byte +var z15750 [1 << 17]byte +var z15751 [1 << 17]byte +var z15752 [1 << 17]byte +var z15753 [1 << 17]byte +var z15754 [1 << 17]byte +var z15755 [1 << 17]byte +var z15756 [1 << 17]byte +var z15757 [1 << 17]byte +var z15758 [1 << 17]byte +var z15759 [1 << 17]byte +var z15760 [1 << 17]byte +var z15761 [1 << 17]byte +var z15762 [1 << 17]byte +var z15763 [1 << 17]byte +var z15764 [1 << 17]byte +var z15765 [1 << 17]byte +var z15766 [1 << 17]byte +var z15767 [1 << 17]byte +var z15768 [1 << 17]byte +var z15769 [1 << 17]byte +var z15770 [1 << 17]byte +var z15771 [1 << 17]byte +var z15772 [1 << 17]byte +var z15773 [1 << 17]byte +var z15774 [1 << 17]byte +var z15775 [1 << 17]byte +var z15776 [1 << 17]byte +var z15777 [1 << 17]byte +var z15778 [1 << 17]byte +var z15779 [1 << 17]byte +var z15780 [1 << 17]byte +var z15781 [1 << 17]byte +var z15782 [1 << 17]byte +var z15783 [1 << 17]byte +var z15784 [1 << 17]byte +var z15785 [1 << 17]byte +var z15786 [1 << 17]byte +var z15787 [1 << 17]byte +var z15788 [1 << 17]byte +var z15789 [1 << 17]byte +var z15790 [1 << 17]byte +var z15791 [1 << 17]byte +var z15792 [1 << 17]byte +var z15793 [1 << 17]byte +var z15794 [1 << 17]byte +var z15795 [1 << 17]byte +var z15796 [1 << 17]byte +var z15797 [1 << 17]byte +var z15798 [1 << 17]byte +var z15799 [1 << 17]byte +var z15800 [1 << 17]byte +var z15801 [1 << 17]byte +var z15802 [1 << 17]byte +var z15803 [1 << 17]byte +var z15804 [1 << 17]byte +var z15805 [1 << 17]byte +var z15806 [1 << 17]byte +var z15807 [1 << 17]byte +var z15808 [1 << 17]byte +var z15809 [1 << 17]byte +var z15810 [1 << 17]byte +var z15811 [1 << 17]byte +var z15812 [1 << 17]byte +var z15813 [1 << 17]byte +var z15814 [1 << 17]byte +var z15815 [1 << 17]byte +var z15816 [1 << 17]byte +var z15817 [1 << 17]byte +var z15818 [1 << 17]byte +var z15819 [1 << 17]byte +var z15820 [1 << 17]byte +var z15821 [1 << 17]byte +var z15822 [1 << 17]byte +var z15823 [1 << 17]byte +var z15824 [1 << 17]byte +var z15825 [1 << 17]byte +var z15826 [1 << 17]byte +var z15827 [1 << 17]byte +var z15828 [1 << 17]byte +var z15829 [1 << 17]byte +var z15830 [1 << 17]byte +var z15831 [1 << 17]byte +var z15832 [1 << 17]byte +var z15833 [1 << 17]byte +var z15834 [1 << 17]byte +var z15835 [1 << 17]byte +var z15836 [1 << 17]byte +var z15837 [1 << 17]byte +var z15838 [1 << 17]byte +var z15839 [1 << 17]byte +var z15840 [1 << 17]byte +var z15841 [1 << 17]byte +var z15842 [1 << 17]byte +var z15843 [1 << 17]byte +var z15844 [1 << 17]byte +var z15845 [1 << 17]byte +var z15846 [1 << 17]byte +var z15847 [1 << 17]byte +var z15848 [1 << 17]byte +var z15849 [1 << 17]byte +var z15850 [1 << 17]byte +var z15851 [1 << 17]byte +var z15852 [1 << 17]byte +var z15853 [1 << 17]byte +var z15854 [1 << 17]byte +var z15855 [1 << 17]byte +var z15856 [1 << 17]byte +var z15857 [1 << 17]byte +var z15858 [1 << 17]byte +var z15859 [1 << 17]byte +var z15860 [1 << 17]byte +var z15861 [1 << 17]byte +var z15862 [1 << 17]byte +var z15863 [1 << 17]byte +var z15864 [1 << 17]byte +var z15865 [1 << 17]byte +var z15866 [1 << 17]byte +var z15867 [1 << 17]byte +var z15868 [1 << 17]byte +var z15869 [1 << 17]byte +var z15870 [1 << 17]byte +var z15871 [1 << 17]byte +var z15872 [1 << 17]byte +var z15873 [1 << 17]byte +var z15874 [1 << 17]byte +var z15875 [1 << 17]byte +var z15876 [1 << 17]byte +var z15877 [1 << 17]byte +var z15878 [1 << 17]byte +var z15879 [1 << 17]byte +var z15880 [1 << 17]byte +var z15881 [1 << 17]byte +var z15882 [1 << 17]byte +var z15883 [1 << 17]byte +var z15884 [1 << 17]byte +var z15885 [1 << 17]byte +var z15886 [1 << 17]byte +var z15887 [1 << 17]byte +var z15888 [1 << 17]byte +var z15889 [1 << 17]byte +var z15890 [1 << 17]byte +var z15891 [1 << 17]byte +var z15892 [1 << 17]byte +var z15893 [1 << 17]byte +var z15894 [1 << 17]byte +var z15895 [1 << 17]byte +var z15896 [1 << 17]byte +var z15897 [1 << 17]byte +var z15898 [1 << 17]byte +var z15899 [1 << 17]byte +var z15900 [1 << 17]byte +var z15901 [1 << 17]byte +var z15902 [1 << 17]byte +var z15903 [1 << 17]byte +var z15904 [1 << 17]byte +var z15905 [1 << 17]byte +var z15906 [1 << 17]byte +var z15907 [1 << 17]byte +var z15908 [1 << 17]byte +var z15909 [1 << 17]byte +var z15910 [1 << 17]byte +var z15911 [1 << 17]byte +var z15912 [1 << 17]byte +var z15913 [1 << 17]byte +var z15914 [1 << 17]byte +var z15915 [1 << 17]byte +var z15916 [1 << 17]byte +var z15917 [1 << 17]byte +var z15918 [1 << 17]byte +var z15919 [1 << 17]byte +var z15920 [1 << 17]byte +var z15921 [1 << 17]byte +var z15922 [1 << 17]byte +var z15923 [1 << 17]byte +var z15924 [1 << 17]byte +var z15925 [1 << 17]byte +var z15926 [1 << 17]byte +var z15927 [1 << 17]byte +var z15928 [1 << 17]byte +var z15929 [1 << 17]byte +var z15930 [1 << 17]byte +var z15931 [1 << 17]byte +var z15932 [1 << 17]byte +var z15933 [1 << 17]byte +var z15934 [1 << 17]byte +var z15935 [1 << 17]byte +var z15936 [1 << 17]byte +var z15937 [1 << 17]byte +var z15938 [1 << 17]byte +var z15939 [1 << 17]byte +var z15940 [1 << 17]byte +var z15941 [1 << 17]byte +var z15942 [1 << 17]byte +var z15943 [1 << 17]byte +var z15944 [1 << 17]byte +var z15945 [1 << 17]byte +var z15946 [1 << 17]byte +var z15947 [1 << 17]byte +var z15948 [1 << 17]byte +var z15949 [1 << 17]byte +var z15950 [1 << 17]byte +var z15951 [1 << 17]byte +var z15952 [1 << 17]byte +var z15953 [1 << 17]byte +var z15954 [1 << 17]byte +var z15955 [1 << 17]byte +var z15956 [1 << 17]byte +var z15957 [1 << 17]byte +var z15958 [1 << 17]byte +var z15959 [1 << 17]byte +var z15960 [1 << 17]byte +var z15961 [1 << 17]byte +var z15962 [1 << 17]byte +var z15963 [1 << 17]byte +var z15964 [1 << 17]byte +var z15965 [1 << 17]byte +var z15966 [1 << 17]byte +var z15967 [1 << 17]byte +var z15968 [1 << 17]byte +var z15969 [1 << 17]byte +var z15970 [1 << 17]byte +var z15971 [1 << 17]byte +var z15972 [1 << 17]byte +var z15973 [1 << 17]byte +var z15974 [1 << 17]byte +var z15975 [1 << 17]byte +var z15976 [1 << 17]byte +var z15977 [1 << 17]byte +var z15978 [1 << 17]byte +var z15979 [1 << 17]byte +var z15980 [1 << 17]byte +var z15981 [1 << 17]byte +var z15982 [1 << 17]byte +var z15983 [1 << 17]byte +var z15984 [1 << 17]byte +var z15985 [1 << 17]byte +var z15986 [1 << 17]byte +var z15987 [1 << 17]byte +var z15988 [1 << 17]byte +var z15989 [1 << 17]byte +var z15990 [1 << 17]byte +var z15991 [1 << 17]byte +var z15992 [1 << 17]byte +var z15993 [1 << 17]byte +var z15994 [1 << 17]byte +var z15995 [1 << 17]byte +var z15996 [1 << 17]byte +var z15997 [1 << 17]byte +var z15998 [1 << 17]byte +var z15999 [1 << 17]byte +var z16000 [1 << 17]byte +var z16001 [1 << 17]byte +var z16002 [1 << 17]byte +var z16003 [1 << 17]byte +var z16004 [1 << 17]byte +var z16005 [1 << 17]byte +var z16006 [1 << 17]byte +var z16007 [1 << 17]byte +var z16008 [1 << 17]byte +var z16009 [1 << 17]byte +var z16010 [1 << 17]byte +var z16011 [1 << 17]byte +var z16012 [1 << 17]byte +var z16013 [1 << 17]byte +var z16014 [1 << 17]byte +var z16015 [1 << 17]byte +var z16016 [1 << 17]byte +var z16017 [1 << 17]byte +var z16018 [1 << 17]byte +var z16019 [1 << 17]byte +var z16020 [1 << 17]byte +var z16021 [1 << 17]byte +var z16022 [1 << 17]byte +var z16023 [1 << 17]byte +var z16024 [1 << 17]byte +var z16025 [1 << 17]byte +var z16026 [1 << 17]byte +var z16027 [1 << 17]byte +var z16028 [1 << 17]byte +var z16029 [1 << 17]byte +var z16030 [1 << 17]byte +var z16031 [1 << 17]byte +var z16032 [1 << 17]byte +var z16033 [1 << 17]byte +var z16034 [1 << 17]byte +var z16035 [1 << 17]byte +var z16036 [1 << 17]byte +var z16037 [1 << 17]byte +var z16038 [1 << 17]byte +var z16039 [1 << 17]byte +var z16040 [1 << 17]byte +var z16041 [1 << 17]byte +var z16042 [1 << 17]byte +var z16043 [1 << 17]byte +var z16044 [1 << 17]byte +var z16045 [1 << 17]byte +var z16046 [1 << 17]byte +var z16047 [1 << 17]byte +var z16048 [1 << 17]byte +var z16049 [1 << 17]byte +var z16050 [1 << 17]byte +var z16051 [1 << 17]byte +var z16052 [1 << 17]byte +var z16053 [1 << 17]byte +var z16054 [1 << 17]byte +var z16055 [1 << 17]byte +var z16056 [1 << 17]byte +var z16057 [1 << 17]byte +var z16058 [1 << 17]byte +var z16059 [1 << 17]byte +var z16060 [1 << 17]byte +var z16061 [1 << 17]byte +var z16062 [1 << 17]byte +var z16063 [1 << 17]byte +var z16064 [1 << 17]byte +var z16065 [1 << 17]byte +var z16066 [1 << 17]byte +var z16067 [1 << 17]byte +var z16068 [1 << 17]byte +var z16069 [1 << 17]byte +var z16070 [1 << 17]byte +var z16071 [1 << 17]byte +var z16072 [1 << 17]byte +var z16073 [1 << 17]byte +var z16074 [1 << 17]byte +var z16075 [1 << 17]byte +var z16076 [1 << 17]byte +var z16077 [1 << 17]byte +var z16078 [1 << 17]byte +var z16079 [1 << 17]byte +var z16080 [1 << 17]byte +var z16081 [1 << 17]byte +var z16082 [1 << 17]byte +var z16083 [1 << 17]byte +var z16084 [1 << 17]byte +var z16085 [1 << 17]byte +var z16086 [1 << 17]byte +var z16087 [1 << 17]byte +var z16088 [1 << 17]byte +var z16089 [1 << 17]byte +var z16090 [1 << 17]byte +var z16091 [1 << 17]byte +var z16092 [1 << 17]byte +var z16093 [1 << 17]byte +var z16094 [1 << 17]byte +var z16095 [1 << 17]byte +var z16096 [1 << 17]byte +var z16097 [1 << 17]byte +var z16098 [1 << 17]byte +var z16099 [1 << 17]byte +var z16100 [1 << 17]byte +var z16101 [1 << 17]byte +var z16102 [1 << 17]byte +var z16103 [1 << 17]byte +var z16104 [1 << 17]byte +var z16105 [1 << 17]byte +var z16106 [1 << 17]byte +var z16107 [1 << 17]byte +var z16108 [1 << 17]byte +var z16109 [1 << 17]byte +var z16110 [1 << 17]byte +var z16111 [1 << 17]byte +var z16112 [1 << 17]byte +var z16113 [1 << 17]byte +var z16114 [1 << 17]byte +var z16115 [1 << 17]byte +var z16116 [1 << 17]byte +var z16117 [1 << 17]byte +var z16118 [1 << 17]byte +var z16119 [1 << 17]byte +var z16120 [1 << 17]byte +var z16121 [1 << 17]byte +var z16122 [1 << 17]byte +var z16123 [1 << 17]byte +var z16124 [1 << 17]byte +var z16125 [1 << 17]byte +var z16126 [1 << 17]byte +var z16127 [1 << 17]byte +var z16128 [1 << 17]byte +var z16129 [1 << 17]byte +var z16130 [1 << 17]byte +var z16131 [1 << 17]byte +var z16132 [1 << 17]byte +var z16133 [1 << 17]byte +var z16134 [1 << 17]byte +var z16135 [1 << 17]byte +var z16136 [1 << 17]byte +var z16137 [1 << 17]byte +var z16138 [1 << 17]byte +var z16139 [1 << 17]byte +var z16140 [1 << 17]byte +var z16141 [1 << 17]byte +var z16142 [1 << 17]byte +var z16143 [1 << 17]byte +var z16144 [1 << 17]byte +var z16145 [1 << 17]byte +var z16146 [1 << 17]byte +var z16147 [1 << 17]byte +var z16148 [1 << 17]byte +var z16149 [1 << 17]byte +var z16150 [1 << 17]byte +var z16151 [1 << 17]byte +var z16152 [1 << 17]byte +var z16153 [1 << 17]byte +var z16154 [1 << 17]byte +var z16155 [1 << 17]byte +var z16156 [1 << 17]byte +var z16157 [1 << 17]byte +var z16158 [1 << 17]byte +var z16159 [1 << 17]byte +var z16160 [1 << 17]byte +var z16161 [1 << 17]byte +var z16162 [1 << 17]byte +var z16163 [1 << 17]byte +var z16164 [1 << 17]byte +var z16165 [1 << 17]byte +var z16166 [1 << 17]byte +var z16167 [1 << 17]byte +var z16168 [1 << 17]byte +var z16169 [1 << 17]byte +var z16170 [1 << 17]byte +var z16171 [1 << 17]byte +var z16172 [1 << 17]byte +var z16173 [1 << 17]byte +var z16174 [1 << 17]byte +var z16175 [1 << 17]byte +var z16176 [1 << 17]byte +var z16177 [1 << 17]byte +var z16178 [1 << 17]byte +var z16179 [1 << 17]byte +var z16180 [1 << 17]byte +var z16181 [1 << 17]byte +var z16182 [1 << 17]byte +var z16183 [1 << 17]byte +var z16184 [1 << 17]byte +var z16185 [1 << 17]byte +var z16186 [1 << 17]byte +var z16187 [1 << 17]byte +var z16188 [1 << 17]byte +var z16189 [1 << 17]byte +var z16190 [1 << 17]byte +var z16191 [1 << 17]byte +var z16192 [1 << 17]byte +var z16193 [1 << 17]byte +var z16194 [1 << 17]byte +var z16195 [1 << 17]byte +var z16196 [1 << 17]byte +var z16197 [1 << 17]byte +var z16198 [1 << 17]byte +var z16199 [1 << 17]byte +var z16200 [1 << 17]byte +var z16201 [1 << 17]byte +var z16202 [1 << 17]byte +var z16203 [1 << 17]byte +var z16204 [1 << 17]byte +var z16205 [1 << 17]byte +var z16206 [1 << 17]byte +var z16207 [1 << 17]byte +var z16208 [1 << 17]byte +var z16209 [1 << 17]byte +var z16210 [1 << 17]byte +var z16211 [1 << 17]byte +var z16212 [1 << 17]byte +var z16213 [1 << 17]byte +var z16214 [1 << 17]byte +var z16215 [1 << 17]byte +var z16216 [1 << 17]byte +var z16217 [1 << 17]byte +var z16218 [1 << 17]byte +var z16219 [1 << 17]byte +var z16220 [1 << 17]byte +var z16221 [1 << 17]byte +var z16222 [1 << 17]byte +var z16223 [1 << 17]byte +var z16224 [1 << 17]byte +var z16225 [1 << 17]byte +var z16226 [1 << 17]byte +var z16227 [1 << 17]byte +var z16228 [1 << 17]byte +var z16229 [1 << 17]byte +var z16230 [1 << 17]byte +var z16231 [1 << 17]byte +var z16232 [1 << 17]byte +var z16233 [1 << 17]byte +var z16234 [1 << 17]byte +var z16235 [1 << 17]byte +var z16236 [1 << 17]byte +var z16237 [1 << 17]byte +var z16238 [1 << 17]byte +var z16239 [1 << 17]byte +var z16240 [1 << 17]byte +var z16241 [1 << 17]byte +var z16242 [1 << 17]byte +var z16243 [1 << 17]byte +var z16244 [1 << 17]byte +var z16245 [1 << 17]byte +var z16246 [1 << 17]byte +var z16247 [1 << 17]byte +var z16248 [1 << 17]byte +var z16249 [1 << 17]byte +var z16250 [1 << 17]byte +var z16251 [1 << 17]byte +var z16252 [1 << 17]byte +var z16253 [1 << 17]byte +var z16254 [1 << 17]byte +var z16255 [1 << 17]byte +var z16256 [1 << 17]byte +var z16257 [1 << 17]byte +var z16258 [1 << 17]byte +var z16259 [1 << 17]byte +var z16260 [1 << 17]byte +var z16261 [1 << 17]byte +var z16262 [1 << 17]byte +var z16263 [1 << 17]byte +var z16264 [1 << 17]byte +var z16265 [1 << 17]byte +var z16266 [1 << 17]byte +var z16267 [1 << 17]byte +var z16268 [1 << 17]byte +var z16269 [1 << 17]byte +var z16270 [1 << 17]byte +var z16271 [1 << 17]byte +var z16272 [1 << 17]byte +var z16273 [1 << 17]byte +var z16274 [1 << 17]byte +var z16275 [1 << 17]byte +var z16276 [1 << 17]byte +var z16277 [1 << 17]byte +var z16278 [1 << 17]byte +var z16279 [1 << 17]byte +var z16280 [1 << 17]byte +var z16281 [1 << 17]byte +var z16282 [1 << 17]byte +var z16283 [1 << 17]byte +var z16284 [1 << 17]byte +var z16285 [1 << 17]byte +var z16286 [1 << 17]byte +var z16287 [1 << 17]byte +var z16288 [1 << 17]byte +var z16289 [1 << 17]byte +var z16290 [1 << 17]byte +var z16291 [1 << 17]byte +var z16292 [1 << 17]byte +var z16293 [1 << 17]byte +var z16294 [1 << 17]byte +var z16295 [1 << 17]byte +var z16296 [1 << 17]byte +var z16297 [1 << 17]byte +var z16298 [1 << 17]byte +var z16299 [1 << 17]byte +var z16300 [1 << 17]byte +var z16301 [1 << 17]byte +var z16302 [1 << 17]byte +var z16303 [1 << 17]byte +var z16304 [1 << 17]byte +var z16305 [1 << 17]byte +var z16306 [1 << 17]byte +var z16307 [1 << 17]byte +var z16308 [1 << 17]byte +var z16309 [1 << 17]byte +var z16310 [1 << 17]byte +var z16311 [1 << 17]byte +var z16312 [1 << 17]byte +var z16313 [1 << 17]byte +var z16314 [1 << 17]byte +var z16315 [1 << 17]byte +var z16316 [1 << 17]byte +var z16317 [1 << 17]byte +var z16318 [1 << 17]byte +var z16319 [1 << 17]byte +var z16320 [1 << 17]byte +var z16321 [1 << 17]byte +var z16322 [1 << 17]byte +var z16323 [1 << 17]byte +var z16324 [1 << 17]byte +var z16325 [1 << 17]byte +var z16326 [1 << 17]byte +var z16327 [1 << 17]byte +var z16328 [1 << 17]byte +var z16329 [1 << 17]byte +var z16330 [1 << 17]byte +var z16331 [1 << 17]byte +var z16332 [1 << 17]byte +var z16333 [1 << 17]byte +var z16334 [1 << 17]byte +var z16335 [1 << 17]byte +var z16336 [1 << 17]byte +var z16337 [1 << 17]byte +var z16338 [1 << 17]byte +var z16339 [1 << 17]byte +var z16340 [1 << 17]byte +var z16341 [1 << 17]byte +var z16342 [1 << 17]byte +var z16343 [1 << 17]byte +var z16344 [1 << 17]byte +var z16345 [1 << 17]byte +var z16346 [1 << 17]byte +var z16347 [1 << 17]byte +var z16348 [1 << 17]byte +var z16349 [1 << 17]byte +var z16350 [1 << 17]byte +var z16351 [1 << 17]byte +var z16352 [1 << 17]byte +var z16353 [1 << 17]byte +var z16354 [1 << 17]byte +var z16355 [1 << 17]byte +var z16356 [1 << 17]byte +var z16357 [1 << 17]byte +var z16358 [1 << 17]byte +var z16359 [1 << 17]byte +var z16360 [1 << 17]byte +var z16361 [1 << 17]byte +var z16362 [1 << 17]byte +var z16363 [1 << 17]byte +var z16364 [1 << 17]byte +var z16365 [1 << 17]byte +var z16366 [1 << 17]byte +var z16367 [1 << 17]byte +var z16368 [1 << 17]byte +var z16369 [1 << 17]byte +var z16370 [1 << 17]byte +var z16371 [1 << 17]byte +var z16372 [1 << 17]byte +var z16373 [1 << 17]byte +var z16374 [1 << 17]byte +var z16375 [1 << 17]byte +var z16376 [1 << 17]byte +var z16377 [1 << 17]byte +var z16378 [1 << 17]byte +var z16379 [1 << 17]byte +var z16380 [1 << 17]byte +var z16381 [1 << 17]byte +var z16382 [1 << 17]byte +var z16383 [1 << 17]byte +var z16384 [1 << 17]byte +var z16385 [1 << 17]byte +var z16386 [1 << 17]byte +var z16387 [1 << 17]byte +var z16388 [1 << 17]byte +var z16389 [1 << 17]byte +var z16390 [1 << 17]byte +var z16391 [1 << 17]byte +var z16392 [1 << 17]byte +var z16393 [1 << 17]byte +var z16394 [1 << 17]byte +var z16395 [1 << 17]byte +var z16396 [1 << 17]byte +var z16397 [1 << 17]byte +var z16398 [1 << 17]byte +var z16399 [1 << 17]byte +var z16400 [1 << 17]byte +var z16401 [1 << 17]byte +var z16402 [1 << 17]byte +var z16403 [1 << 17]byte +var z16404 [1 << 17]byte +var z16405 [1 << 17]byte +var z16406 [1 << 17]byte +var z16407 [1 << 17]byte +var z16408 [1 << 17]byte +var z16409 [1 << 17]byte +var z16410 [1 << 17]byte +var z16411 [1 << 17]byte +var z16412 [1 << 17]byte +var z16413 [1 << 17]byte +var z16414 [1 << 17]byte +var z16415 [1 << 17]byte +var z16416 [1 << 17]byte +var z16417 [1 << 17]byte +var z16418 [1 << 17]byte +var z16419 [1 << 17]byte +var z16420 [1 << 17]byte +var z16421 [1 << 17]byte +var z16422 [1 << 17]byte +var z16423 [1 << 17]byte +var z16424 [1 << 17]byte +var z16425 [1 << 17]byte +var z16426 [1 << 17]byte +var z16427 [1 << 17]byte +var z16428 [1 << 17]byte +var z16429 [1 << 17]byte +var z16430 [1 << 17]byte +var z16431 [1 << 17]byte +var z16432 [1 << 17]byte +var z16433 [1 << 17]byte +var z16434 [1 << 17]byte +var z16435 [1 << 17]byte +var z16436 [1 << 17]byte +var z16437 [1 << 17]byte +var z16438 [1 << 17]byte +var z16439 [1 << 17]byte +var z16440 [1 << 17]byte +var z16441 [1 << 17]byte +var z16442 [1 << 17]byte +var z16443 [1 << 17]byte +var z16444 [1 << 17]byte +var z16445 [1 << 17]byte +var z16446 [1 << 17]byte +var z16447 [1 << 17]byte +var z16448 [1 << 17]byte +var z16449 [1 << 17]byte +var z16450 [1 << 17]byte +var z16451 [1 << 17]byte +var z16452 [1 << 17]byte +var z16453 [1 << 17]byte +var z16454 [1 << 17]byte +var z16455 [1 << 17]byte +var z16456 [1 << 17]byte +var z16457 [1 << 17]byte +var z16458 [1 << 17]byte +var z16459 [1 << 17]byte +var z16460 [1 << 17]byte +var z16461 [1 << 17]byte +var z16462 [1 << 17]byte +var z16463 [1 << 17]byte +var z16464 [1 << 17]byte +var z16465 [1 << 17]byte +var z16466 [1 << 17]byte +var z16467 [1 << 17]byte +var z16468 [1 << 17]byte +var z16469 [1 << 17]byte +var z16470 [1 << 17]byte +var z16471 [1 << 17]byte +var z16472 [1 << 17]byte +var z16473 [1 << 17]byte +var z16474 [1 << 17]byte +var z16475 [1 << 17]byte +var z16476 [1 << 17]byte +var z16477 [1 << 17]byte +var z16478 [1 << 17]byte +var z16479 [1 << 17]byte +var z16480 [1 << 17]byte func main() { // GC_ERROR "stack frame too large" - // seq 1 16480 | sed 's/.*/ var x& [1<<17]byte/' - // seq 1 16480 | sed 's/.*/ z = x&/' + // seq 1 16480 | sed 's/.*/ var x& [1 << 17]byte/' + // seq 1 16480 | sed 's/.*/ z& = x&/' var x1 [1 << 17]byte var x2 [1 << 17]byte var x3 [1 << 17]byte @@ -16496,16484 +32976,16484 @@ var x16478 [1 << 17]byte var x16479 [1 << 17]byte var x16480 [1 << 17]byte - z = x1 - z = x2 - z = x3 - z = x4 - z = x5 - z = x6 - z = x7 - z = x8 - z = x9 - z = x10 - z = x11 - z = x12 - z = x13 - z = x14 - z = x15 - z = x16 - z = x17 - z = x18 - z = x19 - z = x20 - z = x21 - z = x22 - z = x23 - z = x24 - z = x25 - z = x26 - z = x27 - z = x28 - z = x29 - z = x30 - z = x31 - z = x32 - z = x33 - z = x34 - z = x35 - z = x36 - z = x37 - z = x38 - z = x39 - z = x40 - z = x41 - z = x42 - z = x43 - z = x44 - z = x45 - z = x46 - z = x47 - z = x48 - z = x49 - z = x50 - z = x51 - z = x52 - z = x53 - z = x54 - z = x55 - z = x56 - z = x57 - z = x58 - z = x59 - z = x60 - z = x61 - z = x62 - z = x63 - z = x64 - z = x65 - z = x66 - z = x67 - z = x68 - z = x69 - z = x70 - z = x71 - z = x72 - z = x73 - z = x74 - z = x75 - z = x76 - z = x77 - z = x78 - z = x79 - z = x80 - z = x81 - z = x82 - z = x83 - z = x84 - z = x85 - z = x86 - z = x87 - z = x88 - z = x89 - z = x90 - z = x91 - z = x92 - z = x93 - z = x94 - z = x95 - z = x96 - z = x97 - z = x98 - z = x99 - z = x100 - z = x101 - z = x102 - z = x103 - z = x104 - z = x105 - z = x106 - z = x107 - z = x108 - z = x109 - z = x110 - z = x111 - z = x112 - z = x113 - z = x114 - z = x115 - z = x116 - z = x117 - z = x118 - z = x119 - z = x120 - z = x121 - z = x122 - z = x123 - z = x124 - z = x125 - z = x126 - z = x127 - z = x128 - z = x129 - z = x130 - z = x131 - z = x132 - z = x133 - z = x134 - z = x135 - z = x136 - z = x137 - z = x138 - z = x139 - z = x140 - z = x141 - z = x142 - z = x143 - z = x144 - z = x145 - z = x146 - z = x147 - z = x148 - z = x149 - z = x150 - z = x151 - z = x152 - z = x153 - z = x154 - z = x155 - z = x156 - z = x157 - z = x158 - z = x159 - z = x160 - z = x161 - z = x162 - z = x163 - z = x164 - z = x165 - z = x166 - z = x167 - z = x168 - z = x169 - z = x170 - z = x171 - z = x172 - z = x173 - z = x174 - z = x175 - z = x176 - z = x177 - z = x178 - z = x179 - z = x180 - z = x181 - z = x182 - z = x183 - z = x184 - z = x185 - z = x186 - z = x187 - z = x188 - z = x189 - z = x190 - z = x191 - z = x192 - z = x193 - z = x194 - z = x195 - z = x196 - z = x197 - z = x198 - z = x199 - z = x200 - z = x201 - z = x202 - z = x203 - z = x204 - z = x205 - z = x206 - z = x207 - z = x208 - z = x209 - z = x210 - z = x211 - z = x212 - z = x213 - z = x214 - z = x215 - z = x216 - z = x217 - z = x218 - z = x219 - z = x220 - z = x221 - z = x222 - z = x223 - z = x224 - z = x225 - z = x226 - z = x227 - z = x228 - z = x229 - z = x230 - z = x231 - z = x232 - z = x233 - z = x234 - z = x235 - z = x236 - z = x237 - z = x238 - z = x239 - z = x240 - z = x241 - z = x242 - z = x243 - z = x244 - z = x245 - z = x246 - z = x247 - z = x248 - z = x249 - z = x250 - z = x251 - z = x252 - z = x253 - z = x254 - z = x255 - z = x256 - z = x257 - z = x258 - z = x259 - z = x260 - z = x261 - z = x262 - z = x263 - z = x264 - z = x265 - z = x266 - z = x267 - z = x268 - z = x269 - z = x270 - z = x271 - z = x272 - z = x273 - z = x274 - z = x275 - z = x276 - z = x277 - z = x278 - z = x279 - z = x280 - z = x281 - z = x282 - z = x283 - z = x284 - z = x285 - z = x286 - z = x287 - z = x288 - z = x289 - z = x290 - z = x291 - z = x292 - z = x293 - z = x294 - z = x295 - z = x296 - z = x297 - z = x298 - z = x299 - z = x300 - z = x301 - z = x302 - z = x303 - z = x304 - z = x305 - z = x306 - z = x307 - z = x308 - z = x309 - z = x310 - z = x311 - z = x312 - z = x313 - z = x314 - z = x315 - z = x316 - z = x317 - z = x318 - z = x319 - z = x320 - z = x321 - z = x322 - z = x323 - z = x324 - z = x325 - z = x326 - z = x327 - z = x328 - z = x329 - z = x330 - z = x331 - z = x332 - z = x333 - z = x334 - z = x335 - z = x336 - z = x337 - z = x338 - z = x339 - z = x340 - z = x341 - z = x342 - z = x343 - z = x344 - z = x345 - z = x346 - z = x347 - z = x348 - z = x349 - z = x350 - z = x351 - z = x352 - z = x353 - z = x354 - z = x355 - z = x356 - z = x357 - z = x358 - z = x359 - z = x360 - z = x361 - z = x362 - z = x363 - z = x364 - z = x365 - z = x366 - z = x367 - z = x368 - z = x369 - z = x370 - z = x371 - z = x372 - z = x373 - z = x374 - z = x375 - z = x376 - z = x377 - z = x378 - z = x379 - z = x380 - z = x381 - z = x382 - z = x383 - z = x384 - z = x385 - z = x386 - z = x387 - z = x388 - z = x389 - z = x390 - z = x391 - z = x392 - z = x393 - z = x394 - z = x395 - z = x396 - z = x397 - z = x398 - z = x399 - z = x400 - z = x401 - z = x402 - z = x403 - z = x404 - z = x405 - z = x406 - z = x407 - z = x408 - z = x409 - z = x410 - z = x411 - z = x412 - z = x413 - z = x414 - z = x415 - z = x416 - z = x417 - z = x418 - z = x419 - z = x420 - z = x421 - z = x422 - z = x423 - z = x424 - z = x425 - z = x426 - z = x427 - z = x428 - z = x429 - z = x430 - z = x431 - z = x432 - z = x433 - z = x434 - z = x435 - z = x436 - z = x437 - z = x438 - z = x439 - z = x440 - z = x441 - z = x442 - z = x443 - z = x444 - z = x445 - z = x446 - z = x447 - z = x448 - z = x449 - z = x450 - z = x451 - z = x452 - z = x453 - z = x454 - z = x455 - z = x456 - z = x457 - z = x458 - z = x459 - z = x460 - z = x461 - z = x462 - z = x463 - z = x464 - z = x465 - z = x466 - z = x467 - z = x468 - z = x469 - z = x470 - z = x471 - z = x472 - z = x473 - z = x474 - z = x475 - z = x476 - z = x477 - z = x478 - z = x479 - z = x480 - z = x481 - z = x482 - z = x483 - z = x484 - z = x485 - z = x486 - z = x487 - z = x488 - z = x489 - z = x490 - z = x491 - z = x492 - z = x493 - z = x494 - z = x495 - z = x496 - z = x497 - z = x498 - z = x499 - z = x500 - z = x501 - z = x502 - z = x503 - z = x504 - z = x505 - z = x506 - z = x507 - z = x508 - z = x509 - z = x510 - z = x511 - z = x512 - z = x513 - z = x514 - z = x515 - z = x516 - z = x517 - z = x518 - z = x519 - z = x520 - z = x521 - z = x522 - z = x523 - z = x524 - z = x525 - z = x526 - z = x527 - z = x528 - z = x529 - z = x530 - z = x531 - z = x532 - z = x533 - z = x534 - z = x535 - z = x536 - z = x537 - z = x538 - z = x539 - z = x540 - z = x541 - z = x542 - z = x543 - z = x544 - z = x545 - z = x546 - z = x547 - z = x548 - z = x549 - z = x550 - z = x551 - z = x552 - z = x553 - z = x554 - z = x555 - z = x556 - z = x557 - z = x558 - z = x559 - z = x560 - z = x561 - z = x562 - z = x563 - z = x564 - z = x565 - z = x566 - z = x567 - z = x568 - z = x569 - z = x570 - z = x571 - z = x572 - z = x573 - z = x574 - z = x575 - z = x576 - z = x577 - z = x578 - z = x579 - z = x580 - z = x581 - z = x582 - z = x583 - z = x584 - z = x585 - z = x586 - z = x587 - z = x588 - z = x589 - z = x590 - z = x591 - z = x592 - z = x593 - z = x594 - z = x595 - z = x596 - z = x597 - z = x598 - z = x599 - z = x600 - z = x601 - z = x602 - z = x603 - z = x604 - z = x605 - z = x606 - z = x607 - z = x608 - z = x609 - z = x610 - z = x611 - z = x612 - z = x613 - z = x614 - z = x615 - z = x616 - z = x617 - z = x618 - z = x619 - z = x620 - z = x621 - z = x622 - z = x623 - z = x624 - z = x625 - z = x626 - z = x627 - z = x628 - z = x629 - z = x630 - z = x631 - z = x632 - z = x633 - z = x634 - z = x635 - z = x636 - z = x637 - z = x638 - z = x639 - z = x640 - z = x641 - z = x642 - z = x643 - z = x644 - z = x645 - z = x646 - z = x647 - z = x648 - z = x649 - z = x650 - z = x651 - z = x652 - z = x653 - z = x654 - z = x655 - z = x656 - z = x657 - z = x658 - z = x659 - z = x660 - z = x661 - z = x662 - z = x663 - z = x664 - z = x665 - z = x666 - z = x667 - z = x668 - z = x669 - z = x670 - z = x671 - z = x672 - z = x673 - z = x674 - z = x675 - z = x676 - z = x677 - z = x678 - z = x679 - z = x680 - z = x681 - z = x682 - z = x683 - z = x684 - z = x685 - z = x686 - z = x687 - z = x688 - z = x689 - z = x690 - z = x691 - z = x692 - z = x693 - z = x694 - z = x695 - z = x696 - z = x697 - z = x698 - z = x699 - z = x700 - z = x701 - z = x702 - z = x703 - z = x704 - z = x705 - z = x706 - z = x707 - z = x708 - z = x709 - z = x710 - z = x711 - z = x712 - z = x713 - z = x714 - z = x715 - z = x716 - z = x717 - z = x718 - z = x719 - z = x720 - z = x721 - z = x722 - z = x723 - z = x724 - z = x725 - z = x726 - z = x727 - z = x728 - z = x729 - z = x730 - z = x731 - z = x732 - z = x733 - z = x734 - z = x735 - z = x736 - z = x737 - z = x738 - z = x739 - z = x740 - z = x741 - z = x742 - z = x743 - z = x744 - z = x745 - z = x746 - z = x747 - z = x748 - z = x749 - z = x750 - z = x751 - z = x752 - z = x753 - z = x754 - z = x755 - z = x756 - z = x757 - z = x758 - z = x759 - z = x760 - z = x761 - z = x762 - z = x763 - z = x764 - z = x765 - z = x766 - z = x767 - z = x768 - z = x769 - z = x770 - z = x771 - z = x772 - z = x773 - z = x774 - z = x775 - z = x776 - z = x777 - z = x778 - z = x779 - z = x780 - z = x781 - z = x782 - z = x783 - z = x784 - z = x785 - z = x786 - z = x787 - z = x788 - z = x789 - z = x790 - z = x791 - z = x792 - z = x793 - z = x794 - z = x795 - z = x796 - z = x797 - z = x798 - z = x799 - z = x800 - z = x801 - z = x802 - z = x803 - z = x804 - z = x805 - z = x806 - z = x807 - z = x808 - z = x809 - z = x810 - z = x811 - z = x812 - z = x813 - z = x814 - z = x815 - z = x816 - z = x817 - z = x818 - z = x819 - z = x820 - z = x821 - z = x822 - z = x823 - z = x824 - z = x825 - z = x826 - z = x827 - z = x828 - z = x829 - z = x830 - z = x831 - z = x832 - z = x833 - z = x834 - z = x835 - z = x836 - z = x837 - z = x838 - z = x839 - z = x840 - z = x841 - z = x842 - z = x843 - z = x844 - z = x845 - z = x846 - z = x847 - z = x848 - z = x849 - z = x850 - z = x851 - z = x852 - z = x853 - z = x854 - z = x855 - z = x856 - z = x857 - z = x858 - z = x859 - z = x860 - z = x861 - z = x862 - z = x863 - z = x864 - z = x865 - z = x866 - z = x867 - z = x868 - z = x869 - z = x870 - z = x871 - z = x872 - z = x873 - z = x874 - z = x875 - z = x876 - z = x877 - z = x878 - z = x879 - z = x880 - z = x881 - z = x882 - z = x883 - z = x884 - z = x885 - z = x886 - z = x887 - z = x888 - z = x889 - z = x890 - z = x891 - z = x892 - z = x893 - z = x894 - z = x895 - z = x896 - z = x897 - z = x898 - z = x899 - z = x900 - z = x901 - z = x902 - z = x903 - z = x904 - z = x905 - z = x906 - z = x907 - z = x908 - z = x909 - z = x910 - z = x911 - z = x912 - z = x913 - z = x914 - z = x915 - z = x916 - z = x917 - z = x918 - z = x919 - z = x920 - z = x921 - z = x922 - z = x923 - z = x924 - z = x925 - z = x926 - z = x927 - z = x928 - z = x929 - z = x930 - z = x931 - z = x932 - z = x933 - z = x934 - z = x935 - z = x936 - z = x937 - z = x938 - z = x939 - z = x940 - z = x941 - z = x942 - z = x943 - z = x944 - z = x945 - z = x946 - z = x947 - z = x948 - z = x949 - z = x950 - z = x951 - z = x952 - z = x953 - z = x954 - z = x955 - z = x956 - z = x957 - z = x958 - z = x959 - z = x960 - z = x961 - z = x962 - z = x963 - z = x964 - z = x965 - z = x966 - z = x967 - z = x968 - z = x969 - z = x970 - z = x971 - z = x972 - z = x973 - z = x974 - z = x975 - z = x976 - z = x977 - z = x978 - z = x979 - z = x980 - z = x981 - z = x982 - z = x983 - z = x984 - z = x985 - z = x986 - z = x987 - z = x988 - z = x989 - z = x990 - z = x991 - z = x992 - z = x993 - z = x994 - z = x995 - z = x996 - z = x997 - z = x998 - z = x999 - z = x1000 - z = x1001 - z = x1002 - z = x1003 - z = x1004 - z = x1005 - z = x1006 - z = x1007 - z = x1008 - z = x1009 - z = x1010 - z = x1011 - z = x1012 - z = x1013 - z = x1014 - z = x1015 - z = x1016 - z = x1017 - z = x1018 - z = x1019 - z = x1020 - z = x1021 - z = x1022 - z = x1023 - z = x1024 - z = x1025 - z = x1026 - z = x1027 - z = x1028 - z = x1029 - z = x1030 - z = x1031 - z = x1032 - z = x1033 - z = x1034 - z = x1035 - z = x1036 - z = x1037 - z = x1038 - z = x1039 - z = x1040 - z = x1041 - z = x1042 - z = x1043 - z = x1044 - z = x1045 - z = x1046 - z = x1047 - z = x1048 - z = x1049 - z = x1050 - z = x1051 - z = x1052 - z = x1053 - z = x1054 - z = x1055 - z = x1056 - z = x1057 - z = x1058 - z = x1059 - z = x1060 - z = x1061 - z = x1062 - z = x1063 - z = x1064 - z = x1065 - z = x1066 - z = x1067 - z = x1068 - z = x1069 - z = x1070 - z = x1071 - z = x1072 - z = x1073 - z = x1074 - z = x1075 - z = x1076 - z = x1077 - z = x1078 - z = x1079 - z = x1080 - z = x1081 - z = x1082 - z = x1083 - z = x1084 - z = x1085 - z = x1086 - z = x1087 - z = x1088 - z = x1089 - z = x1090 - z = x1091 - z = x1092 - z = x1093 - z = x1094 - z = x1095 - z = x1096 - z = x1097 - z = x1098 - z = x1099 - z = x1100 - z = x1101 - z = x1102 - z = x1103 - z = x1104 - z = x1105 - z = x1106 - z = x1107 - z = x1108 - z = x1109 - z = x1110 - z = x1111 - z = x1112 - z = x1113 - z = x1114 - z = x1115 - z = x1116 - z = x1117 - z = x1118 - z = x1119 - z = x1120 - z = x1121 - z = x1122 - z = x1123 - z = x1124 - z = x1125 - z = x1126 - z = x1127 - z = x1128 - z = x1129 - z = x1130 - z = x1131 - z = x1132 - z = x1133 - z = x1134 - z = x1135 - z = x1136 - z = x1137 - z = x1138 - z = x1139 - z = x1140 - z = x1141 - z = x1142 - z = x1143 - z = x1144 - z = x1145 - z = x1146 - z = x1147 - z = x1148 - z = x1149 - z = x1150 - z = x1151 - z = x1152 - z = x1153 - z = x1154 - z = x1155 - z = x1156 - z = x1157 - z = x1158 - z = x1159 - z = x1160 - z = x1161 - z = x1162 - z = x1163 - z = x1164 - z = x1165 - z = x1166 - z = x1167 - z = x1168 - z = x1169 - z = x1170 - z = x1171 - z = x1172 - z = x1173 - z = x1174 - z = x1175 - z = x1176 - z = x1177 - z = x1178 - z = x1179 - z = x1180 - z = x1181 - z = x1182 - z = x1183 - z = x1184 - z = x1185 - z = x1186 - z = x1187 - z = x1188 - z = x1189 - z = x1190 - z = x1191 - z = x1192 - z = x1193 - z = x1194 - z = x1195 - z = x1196 - z = x1197 - z = x1198 - z = x1199 - z = x1200 - z = x1201 - z = x1202 - z = x1203 - z = x1204 - z = x1205 - z = x1206 - z = x1207 - z = x1208 - z = x1209 - z = x1210 - z = x1211 - z = x1212 - z = x1213 - z = x1214 - z = x1215 - z = x1216 - z = x1217 - z = x1218 - z = x1219 - z = x1220 - z = x1221 - z = x1222 - z = x1223 - z = x1224 - z = x1225 - z = x1226 - z = x1227 - z = x1228 - z = x1229 - z = x1230 - z = x1231 - z = x1232 - z = x1233 - z = x1234 - z = x1235 - z = x1236 - z = x1237 - z = x1238 - z = x1239 - z = x1240 - z = x1241 - z = x1242 - z = x1243 - z = x1244 - z = x1245 - z = x1246 - z = x1247 - z = x1248 - z = x1249 - z = x1250 - z = x1251 - z = x1252 - z = x1253 - z = x1254 - z = x1255 - z = x1256 - z = x1257 - z = x1258 - z = x1259 - z = x1260 - z = x1261 - z = x1262 - z = x1263 - z = x1264 - z = x1265 - z = x1266 - z = x1267 - z = x1268 - z = x1269 - z = x1270 - z = x1271 - z = x1272 - z = x1273 - z = x1274 - z = x1275 - z = x1276 - z = x1277 - z = x1278 - z = x1279 - z = x1280 - z = x1281 - z = x1282 - z = x1283 - z = x1284 - z = x1285 - z = x1286 - z = x1287 - z = x1288 - z = x1289 - z = x1290 - z = x1291 - z = x1292 - z = x1293 - z = x1294 - z = x1295 - z = x1296 - z = x1297 - z = x1298 - z = x1299 - z = x1300 - z = x1301 - z = x1302 - z = x1303 - z = x1304 - z = x1305 - z = x1306 - z = x1307 - z = x1308 - z = x1309 - z = x1310 - z = x1311 - z = x1312 - z = x1313 - z = x1314 - z = x1315 - z = x1316 - z = x1317 - z = x1318 - z = x1319 - z = x1320 - z = x1321 - z = x1322 - z = x1323 - z = x1324 - z = x1325 - z = x1326 - z = x1327 - z = x1328 - z = x1329 - z = x1330 - z = x1331 - z = x1332 - z = x1333 - z = x1334 - z = x1335 - z = x1336 - z = x1337 - z = x1338 - z = x1339 - z = x1340 - z = x1341 - z = x1342 - z = x1343 - z = x1344 - z = x1345 - z = x1346 - z = x1347 - z = x1348 - z = x1349 - z = x1350 - z = x1351 - z = x1352 - z = x1353 - z = x1354 - z = x1355 - z = x1356 - z = x1357 - z = x1358 - z = x1359 - z = x1360 - z = x1361 - z = x1362 - z = x1363 - z = x1364 - z = x1365 - z = x1366 - z = x1367 - z = x1368 - z = x1369 - z = x1370 - z = x1371 - z = x1372 - z = x1373 - z = x1374 - z = x1375 - z = x1376 - z = x1377 - z = x1378 - z = x1379 - z = x1380 - z = x1381 - z = x1382 - z = x1383 - z = x1384 - z = x1385 - z = x1386 - z = x1387 - z = x1388 - z = x1389 - z = x1390 - z = x1391 - z = x1392 - z = x1393 - z = x1394 - z = x1395 - z = x1396 - z = x1397 - z = x1398 - z = x1399 - z = x1400 - z = x1401 - z = x1402 - z = x1403 - z = x1404 - z = x1405 - z = x1406 - z = x1407 - z = x1408 - z = x1409 - z = x1410 - z = x1411 - z = x1412 - z = x1413 - z = x1414 - z = x1415 - z = x1416 - z = x1417 - z = x1418 - z = x1419 - z = x1420 - z = x1421 - z = x1422 - z = x1423 - z = x1424 - z = x1425 - z = x1426 - z = x1427 - z = x1428 - z = x1429 - z = x1430 - z = x1431 - z = x1432 - z = x1433 - z = x1434 - z = x1435 - z = x1436 - z = x1437 - z = x1438 - z = x1439 - z = x1440 - z = x1441 - z = x1442 - z = x1443 - z = x1444 - z = x1445 - z = x1446 - z = x1447 - z = x1448 - z = x1449 - z = x1450 - z = x1451 - z = x1452 - z = x1453 - z = x1454 - z = x1455 - z = x1456 - z = x1457 - z = x1458 - z = x1459 - z = x1460 - z = x1461 - z = x1462 - z = x1463 - z = x1464 - z = x1465 - z = x1466 - z = x1467 - z = x1468 - z = x1469 - z = x1470 - z = x1471 - z = x1472 - z = x1473 - z = x1474 - z = x1475 - z = x1476 - z = x1477 - z = x1478 - z = x1479 - z = x1480 - z = x1481 - z = x1482 - z = x1483 - z = x1484 - z = x1485 - z = x1486 - z = x1487 - z = x1488 - z = x1489 - z = x1490 - z = x1491 - z = x1492 - z = x1493 - z = x1494 - z = x1495 - z = x1496 - z = x1497 - z = x1498 - z = x1499 - z = x1500 - z = x1501 - z = x1502 - z = x1503 - z = x1504 - z = x1505 - z = x1506 - z = x1507 - z = x1508 - z = x1509 - z = x1510 - z = x1511 - z = x1512 - z = x1513 - z = x1514 - z = x1515 - z = x1516 - z = x1517 - z = x1518 - z = x1519 - z = x1520 - z = x1521 - z = x1522 - z = x1523 - z = x1524 - z = x1525 - z = x1526 - z = x1527 - z = x1528 - z = x1529 - z = x1530 - z = x1531 - z = x1532 - z = x1533 - z = x1534 - z = x1535 - z = x1536 - z = x1537 - z = x1538 - z = x1539 - z = x1540 - z = x1541 - z = x1542 - z = x1543 - z = x1544 - z = x1545 - z = x1546 - z = x1547 - z = x1548 - z = x1549 - z = x1550 - z = x1551 - z = x1552 - z = x1553 - z = x1554 - z = x1555 - z = x1556 - z = x1557 - z = x1558 - z = x1559 - z = x1560 - z = x1561 - z = x1562 - z = x1563 - z = x1564 - z = x1565 - z = x1566 - z = x1567 - z = x1568 - z = x1569 - z = x1570 - z = x1571 - z = x1572 - z = x1573 - z = x1574 - z = x1575 - z = x1576 - z = x1577 - z = x1578 - z = x1579 - z = x1580 - z = x1581 - z = x1582 - z = x1583 - z = x1584 - z = x1585 - z = x1586 - z = x1587 - z = x1588 - z = x1589 - z = x1590 - z = x1591 - z = x1592 - z = x1593 - z = x1594 - z = x1595 - z = x1596 - z = x1597 - z = x1598 - z = x1599 - z = x1600 - z = x1601 - z = x1602 - z = x1603 - z = x1604 - z = x1605 - z = x1606 - z = x1607 - z = x1608 - z = x1609 - z = x1610 - z = x1611 - z = x1612 - z = x1613 - z = x1614 - z = x1615 - z = x1616 - z = x1617 - z = x1618 - z = x1619 - z = x1620 - z = x1621 - z = x1622 - z = x1623 - z = x1624 - z = x1625 - z = x1626 - z = x1627 - z = x1628 - z = x1629 - z = x1630 - z = x1631 - z = x1632 - z = x1633 - z = x1634 - z = x1635 - z = x1636 - z = x1637 - z = x1638 - z = x1639 - z = x1640 - z = x1641 - z = x1642 - z = x1643 - z = x1644 - z = x1645 - z = x1646 - z = x1647 - z = x1648 - z = x1649 - z = x1650 - z = x1651 - z = x1652 - z = x1653 - z = x1654 - z = x1655 - z = x1656 - z = x1657 - z = x1658 - z = x1659 - z = x1660 - z = x1661 - z = x1662 - z = x1663 - z = x1664 - z = x1665 - z = x1666 - z = x1667 - z = x1668 - z = x1669 - z = x1670 - z = x1671 - z = x1672 - z = x1673 - z = x1674 - z = x1675 - z = x1676 - z = x1677 - z = x1678 - z = x1679 - z = x1680 - z = x1681 - z = x1682 - z = x1683 - z = x1684 - z = x1685 - z = x1686 - z = x1687 - z = x1688 - z = x1689 - z = x1690 - z = x1691 - z = x1692 - z = x1693 - z = x1694 - z = x1695 - z = x1696 - z = x1697 - z = x1698 - z = x1699 - z = x1700 - z = x1701 - z = x1702 - z = x1703 - z = x1704 - z = x1705 - z = x1706 - z = x1707 - z = x1708 - z = x1709 - z = x1710 - z = x1711 - z = x1712 - z = x1713 - z = x1714 - z = x1715 - z = x1716 - z = x1717 - z = x1718 - z = x1719 - z = x1720 - z = x1721 - z = x1722 - z = x1723 - z = x1724 - z = x1725 - z = x1726 - z = x1727 - z = x1728 - z = x1729 - z = x1730 - z = x1731 - z = x1732 - z = x1733 - z = x1734 - z = x1735 - z = x1736 - z = x1737 - z = x1738 - z = x1739 - z = x1740 - z = x1741 - z = x1742 - z = x1743 - z = x1744 - z = x1745 - z = x1746 - z = x1747 - z = x1748 - z = x1749 - z = x1750 - z = x1751 - z = x1752 - z = x1753 - z = x1754 - z = x1755 - z = x1756 - z = x1757 - z = x1758 - z = x1759 - z = x1760 - z = x1761 - z = x1762 - z = x1763 - z = x1764 - z = x1765 - z = x1766 - z = x1767 - z = x1768 - z = x1769 - z = x1770 - z = x1771 - z = x1772 - z = x1773 - z = x1774 - z = x1775 - z = x1776 - z = x1777 - z = x1778 - z = x1779 - z = x1780 - z = x1781 - z = x1782 - z = x1783 - z = x1784 - z = x1785 - z = x1786 - z = x1787 - z = x1788 - z = x1789 - z = x1790 - z = x1791 - z = x1792 - z = x1793 - z = x1794 - z = x1795 - z = x1796 - z = x1797 - z = x1798 - z = x1799 - z = x1800 - z = x1801 - z = x1802 - z = x1803 - z = x1804 - z = x1805 - z = x1806 - z = x1807 - z = x1808 - z = x1809 - z = x1810 - z = x1811 - z = x1812 - z = x1813 - z = x1814 - z = x1815 - z = x1816 - z = x1817 - z = x1818 - z = x1819 - z = x1820 - z = x1821 - z = x1822 - z = x1823 - z = x1824 - z = x1825 - z = x1826 - z = x1827 - z = x1828 - z = x1829 - z = x1830 - z = x1831 - z = x1832 - z = x1833 - z = x1834 - z = x1835 - z = x1836 - z = x1837 - z = x1838 - z = x1839 - z = x1840 - z = x1841 - z = x1842 - z = x1843 - z = x1844 - z = x1845 - z = x1846 - z = x1847 - z = x1848 - z = x1849 - z = x1850 - z = x1851 - z = x1852 - z = x1853 - z = x1854 - z = x1855 - z = x1856 - z = x1857 - z = x1858 - z = x1859 - z = x1860 - z = x1861 - z = x1862 - z = x1863 - z = x1864 - z = x1865 - z = x1866 - z = x1867 - z = x1868 - z = x1869 - z = x1870 - z = x1871 - z = x1872 - z = x1873 - z = x1874 - z = x1875 - z = x1876 - z = x1877 - z = x1878 - z = x1879 - z = x1880 - z = x1881 - z = x1882 - z = x1883 - z = x1884 - z = x1885 - z = x1886 - z = x1887 - z = x1888 - z = x1889 - z = x1890 - z = x1891 - z = x1892 - z = x1893 - z = x1894 - z = x1895 - z = x1896 - z = x1897 - z = x1898 - z = x1899 - z = x1900 - z = x1901 - z = x1902 - z = x1903 - z = x1904 - z = x1905 - z = x1906 - z = x1907 - z = x1908 - z = x1909 - z = x1910 - z = x1911 - z = x1912 - z = x1913 - z = x1914 - z = x1915 - z = x1916 - z = x1917 - z = x1918 - z = x1919 - z = x1920 - z = x1921 - z = x1922 - z = x1923 - z = x1924 - z = x1925 - z = x1926 - z = x1927 - z = x1928 - z = x1929 - z = x1930 - z = x1931 - z = x1932 - z = x1933 - z = x1934 - z = x1935 - z = x1936 - z = x1937 - z = x1938 - z = x1939 - z = x1940 - z = x1941 - z = x1942 - z = x1943 - z = x1944 - z = x1945 - z = x1946 - z = x1947 - z = x1948 - z = x1949 - z = x1950 - z = x1951 - z = x1952 - z = x1953 - z = x1954 - z = x1955 - z = x1956 - z = x1957 - z = x1958 - z = x1959 - z = x1960 - z = x1961 - z = x1962 - z = x1963 - z = x1964 - z = x1965 - z = x1966 - z = x1967 - z = x1968 - z = x1969 - z = x1970 - z = x1971 - z = x1972 - z = x1973 - z = x1974 - z = x1975 - z = x1976 - z = x1977 - z = x1978 - z = x1979 - z = x1980 - z = x1981 - z = x1982 - z = x1983 - z = x1984 - z = x1985 - z = x1986 - z = x1987 - z = x1988 - z = x1989 - z = x1990 - z = x1991 - z = x1992 - z = x1993 - z = x1994 - z = x1995 - z = x1996 - z = x1997 - z = x1998 - z = x1999 - z = x2000 - z = x2001 - z = x2002 - z = x2003 - z = x2004 - z = x2005 - z = x2006 - z = x2007 - z = x2008 - z = x2009 - z = x2010 - z = x2011 - z = x2012 - z = x2013 - z = x2014 - z = x2015 - z = x2016 - z = x2017 - z = x2018 - z = x2019 - z = x2020 - z = x2021 - z = x2022 - z = x2023 - z = x2024 - z = x2025 - z = x2026 - z = x2027 - z = x2028 - z = x2029 - z = x2030 - z = x2031 - z = x2032 - z = x2033 - z = x2034 - z = x2035 - z = x2036 - z = x2037 - z = x2038 - z = x2039 - z = x2040 - z = x2041 - z = x2042 - z = x2043 - z = x2044 - z = x2045 - z = x2046 - z = x2047 - z = x2048 - z = x2049 - z = x2050 - z = x2051 - z = x2052 - z = x2053 - z = x2054 - z = x2055 - z = x2056 - z = x2057 - z = x2058 - z = x2059 - z = x2060 - z = x2061 - z = x2062 - z = x2063 - z = x2064 - z = x2065 - z = x2066 - z = x2067 - z = x2068 - z = x2069 - z = x2070 - z = x2071 - z = x2072 - z = x2073 - z = x2074 - z = x2075 - z = x2076 - z = x2077 - z = x2078 - z = x2079 - z = x2080 - z = x2081 - z = x2082 - z = x2083 - z = x2084 - z = x2085 - z = x2086 - z = x2087 - z = x2088 - z = x2089 - z = x2090 - z = x2091 - z = x2092 - z = x2093 - z = x2094 - z = x2095 - z = x2096 - z = x2097 - z = x2098 - z = x2099 - z = x2100 - z = x2101 - z = x2102 - z = x2103 - z = x2104 - z = x2105 - z = x2106 - z = x2107 - z = x2108 - z = x2109 - z = x2110 - z = x2111 - z = x2112 - z = x2113 - z = x2114 - z = x2115 - z = x2116 - z = x2117 - z = x2118 - z = x2119 - z = x2120 - z = x2121 - z = x2122 - z = x2123 - z = x2124 - z = x2125 - z = x2126 - z = x2127 - z = x2128 - z = x2129 - z = x2130 - z = x2131 - z = x2132 - z = x2133 - z = x2134 - z = x2135 - z = x2136 - z = x2137 - z = x2138 - z = x2139 - z = x2140 - z = x2141 - z = x2142 - z = x2143 - z = x2144 - z = x2145 - z = x2146 - z = x2147 - z = x2148 - z = x2149 - z = x2150 - z = x2151 - z = x2152 - z = x2153 - z = x2154 - z = x2155 - z = x2156 - z = x2157 - z = x2158 - z = x2159 - z = x2160 - z = x2161 - z = x2162 - z = x2163 - z = x2164 - z = x2165 - z = x2166 - z = x2167 - z = x2168 - z = x2169 - z = x2170 - z = x2171 - z = x2172 - z = x2173 - z = x2174 - z = x2175 - z = x2176 - z = x2177 - z = x2178 - z = x2179 - z = x2180 - z = x2181 - z = x2182 - z = x2183 - z = x2184 - z = x2185 - z = x2186 - z = x2187 - z = x2188 - z = x2189 - z = x2190 - z = x2191 - z = x2192 - z = x2193 - z = x2194 - z = x2195 - z = x2196 - z = x2197 - z = x2198 - z = x2199 - z = x2200 - z = x2201 - z = x2202 - z = x2203 - z = x2204 - z = x2205 - z = x2206 - z = x2207 - z = x2208 - z = x2209 - z = x2210 - z = x2211 - z = x2212 - z = x2213 - z = x2214 - z = x2215 - z = x2216 - z = x2217 - z = x2218 - z = x2219 - z = x2220 - z = x2221 - z = x2222 - z = x2223 - z = x2224 - z = x2225 - z = x2226 - z = x2227 - z = x2228 - z = x2229 - z = x2230 - z = x2231 - z = x2232 - z = x2233 - z = x2234 - z = x2235 - z = x2236 - z = x2237 - z = x2238 - z = x2239 - z = x2240 - z = x2241 - z = x2242 - z = x2243 - z = x2244 - z = x2245 - z = x2246 - z = x2247 - z = x2248 - z = x2249 - z = x2250 - z = x2251 - z = x2252 - z = x2253 - z = x2254 - z = x2255 - z = x2256 - z = x2257 - z = x2258 - z = x2259 - z = x2260 - z = x2261 - z = x2262 - z = x2263 - z = x2264 - z = x2265 - z = x2266 - z = x2267 - z = x2268 - z = x2269 - z = x2270 - z = x2271 - z = x2272 - z = x2273 - z = x2274 - z = x2275 - z = x2276 - z = x2277 - z = x2278 - z = x2279 - z = x2280 - z = x2281 - z = x2282 - z = x2283 - z = x2284 - z = x2285 - z = x2286 - z = x2287 - z = x2288 - z = x2289 - z = x2290 - z = x2291 - z = x2292 - z = x2293 - z = x2294 - z = x2295 - z = x2296 - z = x2297 - z = x2298 - z = x2299 - z = x2300 - z = x2301 - z = x2302 - z = x2303 - z = x2304 - z = x2305 - z = x2306 - z = x2307 - z = x2308 - z = x2309 - z = x2310 - z = x2311 - z = x2312 - z = x2313 - z = x2314 - z = x2315 - z = x2316 - z = x2317 - z = x2318 - z = x2319 - z = x2320 - z = x2321 - z = x2322 - z = x2323 - z = x2324 - z = x2325 - z = x2326 - z = x2327 - z = x2328 - z = x2329 - z = x2330 - z = x2331 - z = x2332 - z = x2333 - z = x2334 - z = x2335 - z = x2336 - z = x2337 - z = x2338 - z = x2339 - z = x2340 - z = x2341 - z = x2342 - z = x2343 - z = x2344 - z = x2345 - z = x2346 - z = x2347 - z = x2348 - z = x2349 - z = x2350 - z = x2351 - z = x2352 - z = x2353 - z = x2354 - z = x2355 - z = x2356 - z = x2357 - z = x2358 - z = x2359 - z = x2360 - z = x2361 - z = x2362 - z = x2363 - z = x2364 - z = x2365 - z = x2366 - z = x2367 - z = x2368 - z = x2369 - z = x2370 - z = x2371 - z = x2372 - z = x2373 - z = x2374 - z = x2375 - z = x2376 - z = x2377 - z = x2378 - z = x2379 - z = x2380 - z = x2381 - z = x2382 - z = x2383 - z = x2384 - z = x2385 - z = x2386 - z = x2387 - z = x2388 - z = x2389 - z = x2390 - z = x2391 - z = x2392 - z = x2393 - z = x2394 - z = x2395 - z = x2396 - z = x2397 - z = x2398 - z = x2399 - z = x2400 - z = x2401 - z = x2402 - z = x2403 - z = x2404 - z = x2405 - z = x2406 - z = x2407 - z = x2408 - z = x2409 - z = x2410 - z = x2411 - z = x2412 - z = x2413 - z = x2414 - z = x2415 - z = x2416 - z = x2417 - z = x2418 - z = x2419 - z = x2420 - z = x2421 - z = x2422 - z = x2423 - z = x2424 - z = x2425 - z = x2426 - z = x2427 - z = x2428 - z = x2429 - z = x2430 - z = x2431 - z = x2432 - z = x2433 - z = x2434 - z = x2435 - z = x2436 - z = x2437 - z = x2438 - z = x2439 - z = x2440 - z = x2441 - z = x2442 - z = x2443 - z = x2444 - z = x2445 - z = x2446 - z = x2447 - z = x2448 - z = x2449 - z = x2450 - z = x2451 - z = x2452 - z = x2453 - z = x2454 - z = x2455 - z = x2456 - z = x2457 - z = x2458 - z = x2459 - z = x2460 - z = x2461 - z = x2462 - z = x2463 - z = x2464 - z = x2465 - z = x2466 - z = x2467 - z = x2468 - z = x2469 - z = x2470 - z = x2471 - z = x2472 - z = x2473 - z = x2474 - z = x2475 - z = x2476 - z = x2477 - z = x2478 - z = x2479 - z = x2480 - z = x2481 - z = x2482 - z = x2483 - z = x2484 - z = x2485 - z = x2486 - z = x2487 - z = x2488 - z = x2489 - z = x2490 - z = x2491 - z = x2492 - z = x2493 - z = x2494 - z = x2495 - z = x2496 - z = x2497 - z = x2498 - z = x2499 - z = x2500 - z = x2501 - z = x2502 - z = x2503 - z = x2504 - z = x2505 - z = x2506 - z = x2507 - z = x2508 - z = x2509 - z = x2510 - z = x2511 - z = x2512 - z = x2513 - z = x2514 - z = x2515 - z = x2516 - z = x2517 - z = x2518 - z = x2519 - z = x2520 - z = x2521 - z = x2522 - z = x2523 - z = x2524 - z = x2525 - z = x2526 - z = x2527 - z = x2528 - z = x2529 - z = x2530 - z = x2531 - z = x2532 - z = x2533 - z = x2534 - z = x2535 - z = x2536 - z = x2537 - z = x2538 - z = x2539 - z = x2540 - z = x2541 - z = x2542 - z = x2543 - z = x2544 - z = x2545 - z = x2546 - z = x2547 - z = x2548 - z = x2549 - z = x2550 - z = x2551 - z = x2552 - z = x2553 - z = x2554 - z = x2555 - z = x2556 - z = x2557 - z = x2558 - z = x2559 - z = x2560 - z = x2561 - z = x2562 - z = x2563 - z = x2564 - z = x2565 - z = x2566 - z = x2567 - z = x2568 - z = x2569 - z = x2570 - z = x2571 - z = x2572 - z = x2573 - z = x2574 - z = x2575 - z = x2576 - z = x2577 - z = x2578 - z = x2579 - z = x2580 - z = x2581 - z = x2582 - z = x2583 - z = x2584 - z = x2585 - z = x2586 - z = x2587 - z = x2588 - z = x2589 - z = x2590 - z = x2591 - z = x2592 - z = x2593 - z = x2594 - z = x2595 - z = x2596 - z = x2597 - z = x2598 - z = x2599 - z = x2600 - z = x2601 - z = x2602 - z = x2603 - z = x2604 - z = x2605 - z = x2606 - z = x2607 - z = x2608 - z = x2609 - z = x2610 - z = x2611 - z = x2612 - z = x2613 - z = x2614 - z = x2615 - z = x2616 - z = x2617 - z = x2618 - z = x2619 - z = x2620 - z = x2621 - z = x2622 - z = x2623 - z = x2624 - z = x2625 - z = x2626 - z = x2627 - z = x2628 - z = x2629 - z = x2630 - z = x2631 - z = x2632 - z = x2633 - z = x2634 - z = x2635 - z = x2636 - z = x2637 - z = x2638 - z = x2639 - z = x2640 - z = x2641 - z = x2642 - z = x2643 - z = x2644 - z = x2645 - z = x2646 - z = x2647 - z = x2648 - z = x2649 - z = x2650 - z = x2651 - z = x2652 - z = x2653 - z = x2654 - z = x2655 - z = x2656 - z = x2657 - z = x2658 - z = x2659 - z = x2660 - z = x2661 - z = x2662 - z = x2663 - z = x2664 - z = x2665 - z = x2666 - z = x2667 - z = x2668 - z = x2669 - z = x2670 - z = x2671 - z = x2672 - z = x2673 - z = x2674 - z = x2675 - z = x2676 - z = x2677 - z = x2678 - z = x2679 - z = x2680 - z = x2681 - z = x2682 - z = x2683 - z = x2684 - z = x2685 - z = x2686 - z = x2687 - z = x2688 - z = x2689 - z = x2690 - z = x2691 - z = x2692 - z = x2693 - z = x2694 - z = x2695 - z = x2696 - z = x2697 - z = x2698 - z = x2699 - z = x2700 - z = x2701 - z = x2702 - z = x2703 - z = x2704 - z = x2705 - z = x2706 - z = x2707 - z = x2708 - z = x2709 - z = x2710 - z = x2711 - z = x2712 - z = x2713 - z = x2714 - z = x2715 - z = x2716 - z = x2717 - z = x2718 - z = x2719 - z = x2720 - z = x2721 - z = x2722 - z = x2723 - z = x2724 - z = x2725 - z = x2726 - z = x2727 - z = x2728 - z = x2729 - z = x2730 - z = x2731 - z = x2732 - z = x2733 - z = x2734 - z = x2735 - z = x2736 - z = x2737 - z = x2738 - z = x2739 - z = x2740 - z = x2741 - z = x2742 - z = x2743 - z = x2744 - z = x2745 - z = x2746 - z = x2747 - z = x2748 - z = x2749 - z = x2750 - z = x2751 - z = x2752 - z = x2753 - z = x2754 - z = x2755 - z = x2756 - z = x2757 - z = x2758 - z = x2759 - z = x2760 - z = x2761 - z = x2762 - z = x2763 - z = x2764 - z = x2765 - z = x2766 - z = x2767 - z = x2768 - z = x2769 - z = x2770 - z = x2771 - z = x2772 - z = x2773 - z = x2774 - z = x2775 - z = x2776 - z = x2777 - z = x2778 - z = x2779 - z = x2780 - z = x2781 - z = x2782 - z = x2783 - z = x2784 - z = x2785 - z = x2786 - z = x2787 - z = x2788 - z = x2789 - z = x2790 - z = x2791 - z = x2792 - z = x2793 - z = x2794 - z = x2795 - z = x2796 - z = x2797 - z = x2798 - z = x2799 - z = x2800 - z = x2801 - z = x2802 - z = x2803 - z = x2804 - z = x2805 - z = x2806 - z = x2807 - z = x2808 - z = x2809 - z = x2810 - z = x2811 - z = x2812 - z = x2813 - z = x2814 - z = x2815 - z = x2816 - z = x2817 - z = x2818 - z = x2819 - z = x2820 - z = x2821 - z = x2822 - z = x2823 - z = x2824 - z = x2825 - z = x2826 - z = x2827 - z = x2828 - z = x2829 - z = x2830 - z = x2831 - z = x2832 - z = x2833 - z = x2834 - z = x2835 - z = x2836 - z = x2837 - z = x2838 - z = x2839 - z = x2840 - z = x2841 - z = x2842 - z = x2843 - z = x2844 - z = x2845 - z = x2846 - z = x2847 - z = x2848 - z = x2849 - z = x2850 - z = x2851 - z = x2852 - z = x2853 - z = x2854 - z = x2855 - z = x2856 - z = x2857 - z = x2858 - z = x2859 - z = x2860 - z = x2861 - z = x2862 - z = x2863 - z = x2864 - z = x2865 - z = x2866 - z = x2867 - z = x2868 - z = x2869 - z = x2870 - z = x2871 - z = x2872 - z = x2873 - z = x2874 - z = x2875 - z = x2876 - z = x2877 - z = x2878 - z = x2879 - z = x2880 - z = x2881 - z = x2882 - z = x2883 - z = x2884 - z = x2885 - z = x2886 - z = x2887 - z = x2888 - z = x2889 - z = x2890 - z = x2891 - z = x2892 - z = x2893 - z = x2894 - z = x2895 - z = x2896 - z = x2897 - z = x2898 - z = x2899 - z = x2900 - z = x2901 - z = x2902 - z = x2903 - z = x2904 - z = x2905 - z = x2906 - z = x2907 - z = x2908 - z = x2909 - z = x2910 - z = x2911 - z = x2912 - z = x2913 - z = x2914 - z = x2915 - z = x2916 - z = x2917 - z = x2918 - z = x2919 - z = x2920 - z = x2921 - z = x2922 - z = x2923 - z = x2924 - z = x2925 - z = x2926 - z = x2927 - z = x2928 - z = x2929 - z = x2930 - z = x2931 - z = x2932 - z = x2933 - z = x2934 - z = x2935 - z = x2936 - z = x2937 - z = x2938 - z = x2939 - z = x2940 - z = x2941 - z = x2942 - z = x2943 - z = x2944 - z = x2945 - z = x2946 - z = x2947 - z = x2948 - z = x2949 - z = x2950 - z = x2951 - z = x2952 - z = x2953 - z = x2954 - z = x2955 - z = x2956 - z = x2957 - z = x2958 - z = x2959 - z = x2960 - z = x2961 - z = x2962 - z = x2963 - z = x2964 - z = x2965 - z = x2966 - z = x2967 - z = x2968 - z = x2969 - z = x2970 - z = x2971 - z = x2972 - z = x2973 - z = x2974 - z = x2975 - z = x2976 - z = x2977 - z = x2978 - z = x2979 - z = x2980 - z = x2981 - z = x2982 - z = x2983 - z = x2984 - z = x2985 - z = x2986 - z = x2987 - z = x2988 - z = x2989 - z = x2990 - z = x2991 - z = x2992 - z = x2993 - z = x2994 - z = x2995 - z = x2996 - z = x2997 - z = x2998 - z = x2999 - z = x3000 - z = x3001 - z = x3002 - z = x3003 - z = x3004 - z = x3005 - z = x3006 - z = x3007 - z = x3008 - z = x3009 - z = x3010 - z = x3011 - z = x3012 - z = x3013 - z = x3014 - z = x3015 - z = x3016 - z = x3017 - z = x3018 - z = x3019 - z = x3020 - z = x3021 - z = x3022 - z = x3023 - z = x3024 - z = x3025 - z = x3026 - z = x3027 - z = x3028 - z = x3029 - z = x3030 - z = x3031 - z = x3032 - z = x3033 - z = x3034 - z = x3035 - z = x3036 - z = x3037 - z = x3038 - z = x3039 - z = x3040 - z = x3041 - z = x3042 - z = x3043 - z = x3044 - z = x3045 - z = x3046 - z = x3047 - z = x3048 - z = x3049 - z = x3050 - z = x3051 - z = x3052 - z = x3053 - z = x3054 - z = x3055 - z = x3056 - z = x3057 - z = x3058 - z = x3059 - z = x3060 - z = x3061 - z = x3062 - z = x3063 - z = x3064 - z = x3065 - z = x3066 - z = x3067 - z = x3068 - z = x3069 - z = x3070 - z = x3071 - z = x3072 - z = x3073 - z = x3074 - z = x3075 - z = x3076 - z = x3077 - z = x3078 - z = x3079 - z = x3080 - z = x3081 - z = x3082 - z = x3083 - z = x3084 - z = x3085 - z = x3086 - z = x3087 - z = x3088 - z = x3089 - z = x3090 - z = x3091 - z = x3092 - z = x3093 - z = x3094 - z = x3095 - z = x3096 - z = x3097 - z = x3098 - z = x3099 - z = x3100 - z = x3101 - z = x3102 - z = x3103 - z = x3104 - z = x3105 - z = x3106 - z = x3107 - z = x3108 - z = x3109 - z = x3110 - z = x3111 - z = x3112 - z = x3113 - z = x3114 - z = x3115 - z = x3116 - z = x3117 - z = x3118 - z = x3119 - z = x3120 - z = x3121 - z = x3122 - z = x3123 - z = x3124 - z = x3125 - z = x3126 - z = x3127 - z = x3128 - z = x3129 - z = x3130 - z = x3131 - z = x3132 - z = x3133 - z = x3134 - z = x3135 - z = x3136 - z = x3137 - z = x3138 - z = x3139 - z = x3140 - z = x3141 - z = x3142 - z = x3143 - z = x3144 - z = x3145 - z = x3146 - z = x3147 - z = x3148 - z = x3149 - z = x3150 - z = x3151 - z = x3152 - z = x3153 - z = x3154 - z = x3155 - z = x3156 - z = x3157 - z = x3158 - z = x3159 - z = x3160 - z = x3161 - z = x3162 - z = x3163 - z = x3164 - z = x3165 - z = x3166 - z = x3167 - z = x3168 - z = x3169 - z = x3170 - z = x3171 - z = x3172 - z = x3173 - z = x3174 - z = x3175 - z = x3176 - z = x3177 - z = x3178 - z = x3179 - z = x3180 - z = x3181 - z = x3182 - z = x3183 - z = x3184 - z = x3185 - z = x3186 - z = x3187 - z = x3188 - z = x3189 - z = x3190 - z = x3191 - z = x3192 - z = x3193 - z = x3194 - z = x3195 - z = x3196 - z = x3197 - z = x3198 - z = x3199 - z = x3200 - z = x3201 - z = x3202 - z = x3203 - z = x3204 - z = x3205 - z = x3206 - z = x3207 - z = x3208 - z = x3209 - z = x3210 - z = x3211 - z = x3212 - z = x3213 - z = x3214 - z = x3215 - z = x3216 - z = x3217 - z = x3218 - z = x3219 - z = x3220 - z = x3221 - z = x3222 - z = x3223 - z = x3224 - z = x3225 - z = x3226 - z = x3227 - z = x3228 - z = x3229 - z = x3230 - z = x3231 - z = x3232 - z = x3233 - z = x3234 - z = x3235 - z = x3236 - z = x3237 - z = x3238 - z = x3239 - z = x3240 - z = x3241 - z = x3242 - z = x3243 - z = x3244 - z = x3245 - z = x3246 - z = x3247 - z = x3248 - z = x3249 - z = x3250 - z = x3251 - z = x3252 - z = x3253 - z = x3254 - z = x3255 - z = x3256 - z = x3257 - z = x3258 - z = x3259 - z = x3260 - z = x3261 - z = x3262 - z = x3263 - z = x3264 - z = x3265 - z = x3266 - z = x3267 - z = x3268 - z = x3269 - z = x3270 - z = x3271 - z = x3272 - z = x3273 - z = x3274 - z = x3275 - z = x3276 - z = x3277 - z = x3278 - z = x3279 - z = x3280 - z = x3281 - z = x3282 - z = x3283 - z = x3284 - z = x3285 - z = x3286 - z = x3287 - z = x3288 - z = x3289 - z = x3290 - z = x3291 - z = x3292 - z = x3293 - z = x3294 - z = x3295 - z = x3296 - z = x3297 - z = x3298 - z = x3299 - z = x3300 - z = x3301 - z = x3302 - z = x3303 - z = x3304 - z = x3305 - z = x3306 - z = x3307 - z = x3308 - z = x3309 - z = x3310 - z = x3311 - z = x3312 - z = x3313 - z = x3314 - z = x3315 - z = x3316 - z = x3317 - z = x3318 - z = x3319 - z = x3320 - z = x3321 - z = x3322 - z = x3323 - z = x3324 - z = x3325 - z = x3326 - z = x3327 - z = x3328 - z = x3329 - z = x3330 - z = x3331 - z = x3332 - z = x3333 - z = x3334 - z = x3335 - z = x3336 - z = x3337 - z = x3338 - z = x3339 - z = x3340 - z = x3341 - z = x3342 - z = x3343 - z = x3344 - z = x3345 - z = x3346 - z = x3347 - z = x3348 - z = x3349 - z = x3350 - z = x3351 - z = x3352 - z = x3353 - z = x3354 - z = x3355 - z = x3356 - z = x3357 - z = x3358 - z = x3359 - z = x3360 - z = x3361 - z = x3362 - z = x3363 - z = x3364 - z = x3365 - z = x3366 - z = x3367 - z = x3368 - z = x3369 - z = x3370 - z = x3371 - z = x3372 - z = x3373 - z = x3374 - z = x3375 - z = x3376 - z = x3377 - z = x3378 - z = x3379 - z = x3380 - z = x3381 - z = x3382 - z = x3383 - z = x3384 - z = x3385 - z = x3386 - z = x3387 - z = x3388 - z = x3389 - z = x3390 - z = x3391 - z = x3392 - z = x3393 - z = x3394 - z = x3395 - z = x3396 - z = x3397 - z = x3398 - z = x3399 - z = x3400 - z = x3401 - z = x3402 - z = x3403 - z = x3404 - z = x3405 - z = x3406 - z = x3407 - z = x3408 - z = x3409 - z = x3410 - z = x3411 - z = x3412 - z = x3413 - z = x3414 - z = x3415 - z = x3416 - z = x3417 - z = x3418 - z = x3419 - z = x3420 - z = x3421 - z = x3422 - z = x3423 - z = x3424 - z = x3425 - z = x3426 - z = x3427 - z = x3428 - z = x3429 - z = x3430 - z = x3431 - z = x3432 - z = x3433 - z = x3434 - z = x3435 - z = x3436 - z = x3437 - z = x3438 - z = x3439 - z = x3440 - z = x3441 - z = x3442 - z = x3443 - z = x3444 - z = x3445 - z = x3446 - z = x3447 - z = x3448 - z = x3449 - z = x3450 - z = x3451 - z = x3452 - z = x3453 - z = x3454 - z = x3455 - z = x3456 - z = x3457 - z = x3458 - z = x3459 - z = x3460 - z = x3461 - z = x3462 - z = x3463 - z = x3464 - z = x3465 - z = x3466 - z = x3467 - z = x3468 - z = x3469 - z = x3470 - z = x3471 - z = x3472 - z = x3473 - z = x3474 - z = x3475 - z = x3476 - z = x3477 - z = x3478 - z = x3479 - z = x3480 - z = x3481 - z = x3482 - z = x3483 - z = x3484 - z = x3485 - z = x3486 - z = x3487 - z = x3488 - z = x3489 - z = x3490 - z = x3491 - z = x3492 - z = x3493 - z = x3494 - z = x3495 - z = x3496 - z = x3497 - z = x3498 - z = x3499 - z = x3500 - z = x3501 - z = x3502 - z = x3503 - z = x3504 - z = x3505 - z = x3506 - z = x3507 - z = x3508 - z = x3509 - z = x3510 - z = x3511 - z = x3512 - z = x3513 - z = x3514 - z = x3515 - z = x3516 - z = x3517 - z = x3518 - z = x3519 - z = x3520 - z = x3521 - z = x3522 - z = x3523 - z = x3524 - z = x3525 - z = x3526 - z = x3527 - z = x3528 - z = x3529 - z = x3530 - z = x3531 - z = x3532 - z = x3533 - z = x3534 - z = x3535 - z = x3536 - z = x3537 - z = x3538 - z = x3539 - z = x3540 - z = x3541 - z = x3542 - z = x3543 - z = x3544 - z = x3545 - z = x3546 - z = x3547 - z = x3548 - z = x3549 - z = x3550 - z = x3551 - z = x3552 - z = x3553 - z = x3554 - z = x3555 - z = x3556 - z = x3557 - z = x3558 - z = x3559 - z = x3560 - z = x3561 - z = x3562 - z = x3563 - z = x3564 - z = x3565 - z = x3566 - z = x3567 - z = x3568 - z = x3569 - z = x3570 - z = x3571 - z = x3572 - z = x3573 - z = x3574 - z = x3575 - z = x3576 - z = x3577 - z = x3578 - z = x3579 - z = x3580 - z = x3581 - z = x3582 - z = x3583 - z = x3584 - z = x3585 - z = x3586 - z = x3587 - z = x3588 - z = x3589 - z = x3590 - z = x3591 - z = x3592 - z = x3593 - z = x3594 - z = x3595 - z = x3596 - z = x3597 - z = x3598 - z = x3599 - z = x3600 - z = x3601 - z = x3602 - z = x3603 - z = x3604 - z = x3605 - z = x3606 - z = x3607 - z = x3608 - z = x3609 - z = x3610 - z = x3611 - z = x3612 - z = x3613 - z = x3614 - z = x3615 - z = x3616 - z = x3617 - z = x3618 - z = x3619 - z = x3620 - z = x3621 - z = x3622 - z = x3623 - z = x3624 - z = x3625 - z = x3626 - z = x3627 - z = x3628 - z = x3629 - z = x3630 - z = x3631 - z = x3632 - z = x3633 - z = x3634 - z = x3635 - z = x3636 - z = x3637 - z = x3638 - z = x3639 - z = x3640 - z = x3641 - z = x3642 - z = x3643 - z = x3644 - z = x3645 - z = x3646 - z = x3647 - z = x3648 - z = x3649 - z = x3650 - z = x3651 - z = x3652 - z = x3653 - z = x3654 - z = x3655 - z = x3656 - z = x3657 - z = x3658 - z = x3659 - z = x3660 - z = x3661 - z = x3662 - z = x3663 - z = x3664 - z = x3665 - z = x3666 - z = x3667 - z = x3668 - z = x3669 - z = x3670 - z = x3671 - z = x3672 - z = x3673 - z = x3674 - z = x3675 - z = x3676 - z = x3677 - z = x3678 - z = x3679 - z = x3680 - z = x3681 - z = x3682 - z = x3683 - z = x3684 - z = x3685 - z = x3686 - z = x3687 - z = x3688 - z = x3689 - z = x3690 - z = x3691 - z = x3692 - z = x3693 - z = x3694 - z = x3695 - z = x3696 - z = x3697 - z = x3698 - z = x3699 - z = x3700 - z = x3701 - z = x3702 - z = x3703 - z = x3704 - z = x3705 - z = x3706 - z = x3707 - z = x3708 - z = x3709 - z = x3710 - z = x3711 - z = x3712 - z = x3713 - z = x3714 - z = x3715 - z = x3716 - z = x3717 - z = x3718 - z = x3719 - z = x3720 - z = x3721 - z = x3722 - z = x3723 - z = x3724 - z = x3725 - z = x3726 - z = x3727 - z = x3728 - z = x3729 - z = x3730 - z = x3731 - z = x3732 - z = x3733 - z = x3734 - z = x3735 - z = x3736 - z = x3737 - z = x3738 - z = x3739 - z = x3740 - z = x3741 - z = x3742 - z = x3743 - z = x3744 - z = x3745 - z = x3746 - z = x3747 - z = x3748 - z = x3749 - z = x3750 - z = x3751 - z = x3752 - z = x3753 - z = x3754 - z = x3755 - z = x3756 - z = x3757 - z = x3758 - z = x3759 - z = x3760 - z = x3761 - z = x3762 - z = x3763 - z = x3764 - z = x3765 - z = x3766 - z = x3767 - z = x3768 - z = x3769 - z = x3770 - z = x3771 - z = x3772 - z = x3773 - z = x3774 - z = x3775 - z = x3776 - z = x3777 - z = x3778 - z = x3779 - z = x3780 - z = x3781 - z = x3782 - z = x3783 - z = x3784 - z = x3785 - z = x3786 - z = x3787 - z = x3788 - z = x3789 - z = x3790 - z = x3791 - z = x3792 - z = x3793 - z = x3794 - z = x3795 - z = x3796 - z = x3797 - z = x3798 - z = x3799 - z = x3800 - z = x3801 - z = x3802 - z = x3803 - z = x3804 - z = x3805 - z = x3806 - z = x3807 - z = x3808 - z = x3809 - z = x3810 - z = x3811 - z = x3812 - z = x3813 - z = x3814 - z = x3815 - z = x3816 - z = x3817 - z = x3818 - z = x3819 - z = x3820 - z = x3821 - z = x3822 - z = x3823 - z = x3824 - z = x3825 - z = x3826 - z = x3827 - z = x3828 - z = x3829 - z = x3830 - z = x3831 - z = x3832 - z = x3833 - z = x3834 - z = x3835 - z = x3836 - z = x3837 - z = x3838 - z = x3839 - z = x3840 - z = x3841 - z = x3842 - z = x3843 - z = x3844 - z = x3845 - z = x3846 - z = x3847 - z = x3848 - z = x3849 - z = x3850 - z = x3851 - z = x3852 - z = x3853 - z = x3854 - z = x3855 - z = x3856 - z = x3857 - z = x3858 - z = x3859 - z = x3860 - z = x3861 - z = x3862 - z = x3863 - z = x3864 - z = x3865 - z = x3866 - z = x3867 - z = x3868 - z = x3869 - z = x3870 - z = x3871 - z = x3872 - z = x3873 - z = x3874 - z = x3875 - z = x3876 - z = x3877 - z = x3878 - z = x3879 - z = x3880 - z = x3881 - z = x3882 - z = x3883 - z = x3884 - z = x3885 - z = x3886 - z = x3887 - z = x3888 - z = x3889 - z = x3890 - z = x3891 - z = x3892 - z = x3893 - z = x3894 - z = x3895 - z = x3896 - z = x3897 - z = x3898 - z = x3899 - z = x3900 - z = x3901 - z = x3902 - z = x3903 - z = x3904 - z = x3905 - z = x3906 - z = x3907 - z = x3908 - z = x3909 - z = x3910 - z = x3911 - z = x3912 - z = x3913 - z = x3914 - z = x3915 - z = x3916 - z = x3917 - z = x3918 - z = x3919 - z = x3920 - z = x3921 - z = x3922 - z = x3923 - z = x3924 - z = x3925 - z = x3926 - z = x3927 - z = x3928 - z = x3929 - z = x3930 - z = x3931 - z = x3932 - z = x3933 - z = x3934 - z = x3935 - z = x3936 - z = x3937 - z = x3938 - z = x3939 - z = x3940 - z = x3941 - z = x3942 - z = x3943 - z = x3944 - z = x3945 - z = x3946 - z = x3947 - z = x3948 - z = x3949 - z = x3950 - z = x3951 - z = x3952 - z = x3953 - z = x3954 - z = x3955 - z = x3956 - z = x3957 - z = x3958 - z = x3959 - z = x3960 - z = x3961 - z = x3962 - z = x3963 - z = x3964 - z = x3965 - z = x3966 - z = x3967 - z = x3968 - z = x3969 - z = x3970 - z = x3971 - z = x3972 - z = x3973 - z = x3974 - z = x3975 - z = x3976 - z = x3977 - z = x3978 - z = x3979 - z = x3980 - z = x3981 - z = x3982 - z = x3983 - z = x3984 - z = x3985 - z = x3986 - z = x3987 - z = x3988 - z = x3989 - z = x3990 - z = x3991 - z = x3992 - z = x3993 - z = x3994 - z = x3995 - z = x3996 - z = x3997 - z = x3998 - z = x3999 - z = x4000 - z = x4001 - z = x4002 - z = x4003 - z = x4004 - z = x4005 - z = x4006 - z = x4007 - z = x4008 - z = x4009 - z = x4010 - z = x4011 - z = x4012 - z = x4013 - z = x4014 - z = x4015 - z = x4016 - z = x4017 - z = x4018 - z = x4019 - z = x4020 - z = x4021 - z = x4022 - z = x4023 - z = x4024 - z = x4025 - z = x4026 - z = x4027 - z = x4028 - z = x4029 - z = x4030 - z = x4031 - z = x4032 - z = x4033 - z = x4034 - z = x4035 - z = x4036 - z = x4037 - z = x4038 - z = x4039 - z = x4040 - z = x4041 - z = x4042 - z = x4043 - z = x4044 - z = x4045 - z = x4046 - z = x4047 - z = x4048 - z = x4049 - z = x4050 - z = x4051 - z = x4052 - z = x4053 - z = x4054 - z = x4055 - z = x4056 - z = x4057 - z = x4058 - z = x4059 - z = x4060 - z = x4061 - z = x4062 - z = x4063 - z = x4064 - z = x4065 - z = x4066 - z = x4067 - z = x4068 - z = x4069 - z = x4070 - z = x4071 - z = x4072 - z = x4073 - z = x4074 - z = x4075 - z = x4076 - z = x4077 - z = x4078 - z = x4079 - z = x4080 - z = x4081 - z = x4082 - z = x4083 - z = x4084 - z = x4085 - z = x4086 - z = x4087 - z = x4088 - z = x4089 - z = x4090 - z = x4091 - z = x4092 - z = x4093 - z = x4094 - z = x4095 - z = x4096 - z = x4097 - z = x4098 - z = x4099 - z = x4100 - z = x4101 - z = x4102 - z = x4103 - z = x4104 - z = x4105 - z = x4106 - z = x4107 - z = x4108 - z = x4109 - z = x4110 - z = x4111 - z = x4112 - z = x4113 - z = x4114 - z = x4115 - z = x4116 - z = x4117 - z = x4118 - z = x4119 - z = x4120 - z = x4121 - z = x4122 - z = x4123 - z = x4124 - z = x4125 - z = x4126 - z = x4127 - z = x4128 - z = x4129 - z = x4130 - z = x4131 - z = x4132 - z = x4133 - z = x4134 - z = x4135 - z = x4136 - z = x4137 - z = x4138 - z = x4139 - z = x4140 - z = x4141 - z = x4142 - z = x4143 - z = x4144 - z = x4145 - z = x4146 - z = x4147 - z = x4148 - z = x4149 - z = x4150 - z = x4151 - z = x4152 - z = x4153 - z = x4154 - z = x4155 - z = x4156 - z = x4157 - z = x4158 - z = x4159 - z = x4160 - z = x4161 - z = x4162 - z = x4163 - z = x4164 - z = x4165 - z = x4166 - z = x4167 - z = x4168 - z = x4169 - z = x4170 - z = x4171 - z = x4172 - z = x4173 - z = x4174 - z = x4175 - z = x4176 - z = x4177 - z = x4178 - z = x4179 - z = x4180 - z = x4181 - z = x4182 - z = x4183 - z = x4184 - z = x4185 - z = x4186 - z = x4187 - z = x4188 - z = x4189 - z = x4190 - z = x4191 - z = x4192 - z = x4193 - z = x4194 - z = x4195 - z = x4196 - z = x4197 - z = x4198 - z = x4199 - z = x4200 - z = x4201 - z = x4202 - z = x4203 - z = x4204 - z = x4205 - z = x4206 - z = x4207 - z = x4208 - z = x4209 - z = x4210 - z = x4211 - z = x4212 - z = x4213 - z = x4214 - z = x4215 - z = x4216 - z = x4217 - z = x4218 - z = x4219 - z = x4220 - z = x4221 - z = x4222 - z = x4223 - z = x4224 - z = x4225 - z = x4226 - z = x4227 - z = x4228 - z = x4229 - z = x4230 - z = x4231 - z = x4232 - z = x4233 - z = x4234 - z = x4235 - z = x4236 - z = x4237 - z = x4238 - z = x4239 - z = x4240 - z = x4241 - z = x4242 - z = x4243 - z = x4244 - z = x4245 - z = x4246 - z = x4247 - z = x4248 - z = x4249 - z = x4250 - z = x4251 - z = x4252 - z = x4253 - z = x4254 - z = x4255 - z = x4256 - z = x4257 - z = x4258 - z = x4259 - z = x4260 - z = x4261 - z = x4262 - z = x4263 - z = x4264 - z = x4265 - z = x4266 - z = x4267 - z = x4268 - z = x4269 - z = x4270 - z = x4271 - z = x4272 - z = x4273 - z = x4274 - z = x4275 - z = x4276 - z = x4277 - z = x4278 - z = x4279 - z = x4280 - z = x4281 - z = x4282 - z = x4283 - z = x4284 - z = x4285 - z = x4286 - z = x4287 - z = x4288 - z = x4289 - z = x4290 - z = x4291 - z = x4292 - z = x4293 - z = x4294 - z = x4295 - z = x4296 - z = x4297 - z = x4298 - z = x4299 - z = x4300 - z = x4301 - z = x4302 - z = x4303 - z = x4304 - z = x4305 - z = x4306 - z = x4307 - z = x4308 - z = x4309 - z = x4310 - z = x4311 - z = x4312 - z = x4313 - z = x4314 - z = x4315 - z = x4316 - z = x4317 - z = x4318 - z = x4319 - z = x4320 - z = x4321 - z = x4322 - z = x4323 - z = x4324 - z = x4325 - z = x4326 - z = x4327 - z = x4328 - z = x4329 - z = x4330 - z = x4331 - z = x4332 - z = x4333 - z = x4334 - z = x4335 - z = x4336 - z = x4337 - z = x4338 - z = x4339 - z = x4340 - z = x4341 - z = x4342 - z = x4343 - z = x4344 - z = x4345 - z = x4346 - z = x4347 - z = x4348 - z = x4349 - z = x4350 - z = x4351 - z = x4352 - z = x4353 - z = x4354 - z = x4355 - z = x4356 - z = x4357 - z = x4358 - z = x4359 - z = x4360 - z = x4361 - z = x4362 - z = x4363 - z = x4364 - z = x4365 - z = x4366 - z = x4367 - z = x4368 - z = x4369 - z = x4370 - z = x4371 - z = x4372 - z = x4373 - z = x4374 - z = x4375 - z = x4376 - z = x4377 - z = x4378 - z = x4379 - z = x4380 - z = x4381 - z = x4382 - z = x4383 - z = x4384 - z = x4385 - z = x4386 - z = x4387 - z = x4388 - z = x4389 - z = x4390 - z = x4391 - z = x4392 - z = x4393 - z = x4394 - z = x4395 - z = x4396 - z = x4397 - z = x4398 - z = x4399 - z = x4400 - z = x4401 - z = x4402 - z = x4403 - z = x4404 - z = x4405 - z = x4406 - z = x4407 - z = x4408 - z = x4409 - z = x4410 - z = x4411 - z = x4412 - z = x4413 - z = x4414 - z = x4415 - z = x4416 - z = x4417 - z = x4418 - z = x4419 - z = x4420 - z = x4421 - z = x4422 - z = x4423 - z = x4424 - z = x4425 - z = x4426 - z = x4427 - z = x4428 - z = x4429 - z = x4430 - z = x4431 - z = x4432 - z = x4433 - z = x4434 - z = x4435 - z = x4436 - z = x4437 - z = x4438 - z = x4439 - z = x4440 - z = x4441 - z = x4442 - z = x4443 - z = x4444 - z = x4445 - z = x4446 - z = x4447 - z = x4448 - z = x4449 - z = x4450 - z = x4451 - z = x4452 - z = x4453 - z = x4454 - z = x4455 - z = x4456 - z = x4457 - z = x4458 - z = x4459 - z = x4460 - z = x4461 - z = x4462 - z = x4463 - z = x4464 - z = x4465 - z = x4466 - z = x4467 - z = x4468 - z = x4469 - z = x4470 - z = x4471 - z = x4472 - z = x4473 - z = x4474 - z = x4475 - z = x4476 - z = x4477 - z = x4478 - z = x4479 - z = x4480 - z = x4481 - z = x4482 - z = x4483 - z = x4484 - z = x4485 - z = x4486 - z = x4487 - z = x4488 - z = x4489 - z = x4490 - z = x4491 - z = x4492 - z = x4493 - z = x4494 - z = x4495 - z = x4496 - z = x4497 - z = x4498 - z = x4499 - z = x4500 - z = x4501 - z = x4502 - z = x4503 - z = x4504 - z = x4505 - z = x4506 - z = x4507 - z = x4508 - z = x4509 - z = x4510 - z = x4511 - z = x4512 - z = x4513 - z = x4514 - z = x4515 - z = x4516 - z = x4517 - z = x4518 - z = x4519 - z = x4520 - z = x4521 - z = x4522 - z = x4523 - z = x4524 - z = x4525 - z = x4526 - z = x4527 - z = x4528 - z = x4529 - z = x4530 - z = x4531 - z = x4532 - z = x4533 - z = x4534 - z = x4535 - z = x4536 - z = x4537 - z = x4538 - z = x4539 - z = x4540 - z = x4541 - z = x4542 - z = x4543 - z = x4544 - z = x4545 - z = x4546 - z = x4547 - z = x4548 - z = x4549 - z = x4550 - z = x4551 - z = x4552 - z = x4553 - z = x4554 - z = x4555 - z = x4556 - z = x4557 - z = x4558 - z = x4559 - z = x4560 - z = x4561 - z = x4562 - z = x4563 - z = x4564 - z = x4565 - z = x4566 - z = x4567 - z = x4568 - z = x4569 - z = x4570 - z = x4571 - z = x4572 - z = x4573 - z = x4574 - z = x4575 - z = x4576 - z = x4577 - z = x4578 - z = x4579 - z = x4580 - z = x4581 - z = x4582 - z = x4583 - z = x4584 - z = x4585 - z = x4586 - z = x4587 - z = x4588 - z = x4589 - z = x4590 - z = x4591 - z = x4592 - z = x4593 - z = x4594 - z = x4595 - z = x4596 - z = x4597 - z = x4598 - z = x4599 - z = x4600 - z = x4601 - z = x4602 - z = x4603 - z = x4604 - z = x4605 - z = x4606 - z = x4607 - z = x4608 - z = x4609 - z = x4610 - z = x4611 - z = x4612 - z = x4613 - z = x4614 - z = x4615 - z = x4616 - z = x4617 - z = x4618 - z = x4619 - z = x4620 - z = x4621 - z = x4622 - z = x4623 - z = x4624 - z = x4625 - z = x4626 - z = x4627 - z = x4628 - z = x4629 - z = x4630 - z = x4631 - z = x4632 - z = x4633 - z = x4634 - z = x4635 - z = x4636 - z = x4637 - z = x4638 - z = x4639 - z = x4640 - z = x4641 - z = x4642 - z = x4643 - z = x4644 - z = x4645 - z = x4646 - z = x4647 - z = x4648 - z = x4649 - z = x4650 - z = x4651 - z = x4652 - z = x4653 - z = x4654 - z = x4655 - z = x4656 - z = x4657 - z = x4658 - z = x4659 - z = x4660 - z = x4661 - z = x4662 - z = x4663 - z = x4664 - z = x4665 - z = x4666 - z = x4667 - z = x4668 - z = x4669 - z = x4670 - z = x4671 - z = x4672 - z = x4673 - z = x4674 - z = x4675 - z = x4676 - z = x4677 - z = x4678 - z = x4679 - z = x4680 - z = x4681 - z = x4682 - z = x4683 - z = x4684 - z = x4685 - z = x4686 - z = x4687 - z = x4688 - z = x4689 - z = x4690 - z = x4691 - z = x4692 - z = x4693 - z = x4694 - z = x4695 - z = x4696 - z = x4697 - z = x4698 - z = x4699 - z = x4700 - z = x4701 - z = x4702 - z = x4703 - z = x4704 - z = x4705 - z = x4706 - z = x4707 - z = x4708 - z = x4709 - z = x4710 - z = x4711 - z = x4712 - z = x4713 - z = x4714 - z = x4715 - z = x4716 - z = x4717 - z = x4718 - z = x4719 - z = x4720 - z = x4721 - z = x4722 - z = x4723 - z = x4724 - z = x4725 - z = x4726 - z = x4727 - z = x4728 - z = x4729 - z = x4730 - z = x4731 - z = x4732 - z = x4733 - z = x4734 - z = x4735 - z = x4736 - z = x4737 - z = x4738 - z = x4739 - z = x4740 - z = x4741 - z = x4742 - z = x4743 - z = x4744 - z = x4745 - z = x4746 - z = x4747 - z = x4748 - z = x4749 - z = x4750 - z = x4751 - z = x4752 - z = x4753 - z = x4754 - z = x4755 - z = x4756 - z = x4757 - z = x4758 - z = x4759 - z = x4760 - z = x4761 - z = x4762 - z = x4763 - z = x4764 - z = x4765 - z = x4766 - z = x4767 - z = x4768 - z = x4769 - z = x4770 - z = x4771 - z = x4772 - z = x4773 - z = x4774 - z = x4775 - z = x4776 - z = x4777 - z = x4778 - z = x4779 - z = x4780 - z = x4781 - z = x4782 - z = x4783 - z = x4784 - z = x4785 - z = x4786 - z = x4787 - z = x4788 - z = x4789 - z = x4790 - z = x4791 - z = x4792 - z = x4793 - z = x4794 - z = x4795 - z = x4796 - z = x4797 - z = x4798 - z = x4799 - z = x4800 - z = x4801 - z = x4802 - z = x4803 - z = x4804 - z = x4805 - z = x4806 - z = x4807 - z = x4808 - z = x4809 - z = x4810 - z = x4811 - z = x4812 - z = x4813 - z = x4814 - z = x4815 - z = x4816 - z = x4817 - z = x4818 - z = x4819 - z = x4820 - z = x4821 - z = x4822 - z = x4823 - z = x4824 - z = x4825 - z = x4826 - z = x4827 - z = x4828 - z = x4829 - z = x4830 - z = x4831 - z = x4832 - z = x4833 - z = x4834 - z = x4835 - z = x4836 - z = x4837 - z = x4838 - z = x4839 - z = x4840 - z = x4841 - z = x4842 - z = x4843 - z = x4844 - z = x4845 - z = x4846 - z = x4847 - z = x4848 - z = x4849 - z = x4850 - z = x4851 - z = x4852 - z = x4853 - z = x4854 - z = x4855 - z = x4856 - z = x4857 - z = x4858 - z = x4859 - z = x4860 - z = x4861 - z = x4862 - z = x4863 - z = x4864 - z = x4865 - z = x4866 - z = x4867 - z = x4868 - z = x4869 - z = x4870 - z = x4871 - z = x4872 - z = x4873 - z = x4874 - z = x4875 - z = x4876 - z = x4877 - z = x4878 - z = x4879 - z = x4880 - z = x4881 - z = x4882 - z = x4883 - z = x4884 - z = x4885 - z = x4886 - z = x4887 - z = x4888 - z = x4889 - z = x4890 - z = x4891 - z = x4892 - z = x4893 - z = x4894 - z = x4895 - z = x4896 - z = x4897 - z = x4898 - z = x4899 - z = x4900 - z = x4901 - z = x4902 - z = x4903 - z = x4904 - z = x4905 - z = x4906 - z = x4907 - z = x4908 - z = x4909 - z = x4910 - z = x4911 - z = x4912 - z = x4913 - z = x4914 - z = x4915 - z = x4916 - z = x4917 - z = x4918 - z = x4919 - z = x4920 - z = x4921 - z = x4922 - z = x4923 - z = x4924 - z = x4925 - z = x4926 - z = x4927 - z = x4928 - z = x4929 - z = x4930 - z = x4931 - z = x4932 - z = x4933 - z = x4934 - z = x4935 - z = x4936 - z = x4937 - z = x4938 - z = x4939 - z = x4940 - z = x4941 - z = x4942 - z = x4943 - z = x4944 - z = x4945 - z = x4946 - z = x4947 - z = x4948 - z = x4949 - z = x4950 - z = x4951 - z = x4952 - z = x4953 - z = x4954 - z = x4955 - z = x4956 - z = x4957 - z = x4958 - z = x4959 - z = x4960 - z = x4961 - z = x4962 - z = x4963 - z = x4964 - z = x4965 - z = x4966 - z = x4967 - z = x4968 - z = x4969 - z = x4970 - z = x4971 - z = x4972 - z = x4973 - z = x4974 - z = x4975 - z = x4976 - z = x4977 - z = x4978 - z = x4979 - z = x4980 - z = x4981 - z = x4982 - z = x4983 - z = x4984 - z = x4985 - z = x4986 - z = x4987 - z = x4988 - z = x4989 - z = x4990 - z = x4991 - z = x4992 - z = x4993 - z = x4994 - z = x4995 - z = x4996 - z = x4997 - z = x4998 - z = x4999 - z = x5000 - z = x5001 - z = x5002 - z = x5003 - z = x5004 - z = x5005 - z = x5006 - z = x5007 - z = x5008 - z = x5009 - z = x5010 - z = x5011 - z = x5012 - z = x5013 - z = x5014 - z = x5015 - z = x5016 - z = x5017 - z = x5018 - z = x5019 - z = x5020 - z = x5021 - z = x5022 - z = x5023 - z = x5024 - z = x5025 - z = x5026 - z = x5027 - z = x5028 - z = x5029 - z = x5030 - z = x5031 - z = x5032 - z = x5033 - z = x5034 - z = x5035 - z = x5036 - z = x5037 - z = x5038 - z = x5039 - z = x5040 - z = x5041 - z = x5042 - z = x5043 - z = x5044 - z = x5045 - z = x5046 - z = x5047 - z = x5048 - z = x5049 - z = x5050 - z = x5051 - z = x5052 - z = x5053 - z = x5054 - z = x5055 - z = x5056 - z = x5057 - z = x5058 - z = x5059 - z = x5060 - z = x5061 - z = x5062 - z = x5063 - z = x5064 - z = x5065 - z = x5066 - z = x5067 - z = x5068 - z = x5069 - z = x5070 - z = x5071 - z = x5072 - z = x5073 - z = x5074 - z = x5075 - z = x5076 - z = x5077 - z = x5078 - z = x5079 - z = x5080 - z = x5081 - z = x5082 - z = x5083 - z = x5084 - z = x5085 - z = x5086 - z = x5087 - z = x5088 - z = x5089 - z = x5090 - z = x5091 - z = x5092 - z = x5093 - z = x5094 - z = x5095 - z = x5096 - z = x5097 - z = x5098 - z = x5099 - z = x5100 - z = x5101 - z = x5102 - z = x5103 - z = x5104 - z = x5105 - z = x5106 - z = x5107 - z = x5108 - z = x5109 - z = x5110 - z = x5111 - z = x5112 - z = x5113 - z = x5114 - z = x5115 - z = x5116 - z = x5117 - z = x5118 - z = x5119 - z = x5120 - z = x5121 - z = x5122 - z = x5123 - z = x5124 - z = x5125 - z = x5126 - z = x5127 - z = x5128 - z = x5129 - z = x5130 - z = x5131 - z = x5132 - z = x5133 - z = x5134 - z = x5135 - z = x5136 - z = x5137 - z = x5138 - z = x5139 - z = x5140 - z = x5141 - z = x5142 - z = x5143 - z = x5144 - z = x5145 - z = x5146 - z = x5147 - z = x5148 - z = x5149 - z = x5150 - z = x5151 - z = x5152 - z = x5153 - z = x5154 - z = x5155 - z = x5156 - z = x5157 - z = x5158 - z = x5159 - z = x5160 - z = x5161 - z = x5162 - z = x5163 - z = x5164 - z = x5165 - z = x5166 - z = x5167 - z = x5168 - z = x5169 - z = x5170 - z = x5171 - z = x5172 - z = x5173 - z = x5174 - z = x5175 - z = x5176 - z = x5177 - z = x5178 - z = x5179 - z = x5180 - z = x5181 - z = x5182 - z = x5183 - z = x5184 - z = x5185 - z = x5186 - z = x5187 - z = x5188 - z = x5189 - z = x5190 - z = x5191 - z = x5192 - z = x5193 - z = x5194 - z = x5195 - z = x5196 - z = x5197 - z = x5198 - z = x5199 - z = x5200 - z = x5201 - z = x5202 - z = x5203 - z = x5204 - z = x5205 - z = x5206 - z = x5207 - z = x5208 - z = x5209 - z = x5210 - z = x5211 - z = x5212 - z = x5213 - z = x5214 - z = x5215 - z = x5216 - z = x5217 - z = x5218 - z = x5219 - z = x5220 - z = x5221 - z = x5222 - z = x5223 - z = x5224 - z = x5225 - z = x5226 - z = x5227 - z = x5228 - z = x5229 - z = x5230 - z = x5231 - z = x5232 - z = x5233 - z = x5234 - z = x5235 - z = x5236 - z = x5237 - z = x5238 - z = x5239 - z = x5240 - z = x5241 - z = x5242 - z = x5243 - z = x5244 - z = x5245 - z = x5246 - z = x5247 - z = x5248 - z = x5249 - z = x5250 - z = x5251 - z = x5252 - z = x5253 - z = x5254 - z = x5255 - z = x5256 - z = x5257 - z = x5258 - z = x5259 - z = x5260 - z = x5261 - z = x5262 - z = x5263 - z = x5264 - z = x5265 - z = x5266 - z = x5267 - z = x5268 - z = x5269 - z = x5270 - z = x5271 - z = x5272 - z = x5273 - z = x5274 - z = x5275 - z = x5276 - z = x5277 - z = x5278 - z = x5279 - z = x5280 - z = x5281 - z = x5282 - z = x5283 - z = x5284 - z = x5285 - z = x5286 - z = x5287 - z = x5288 - z = x5289 - z = x5290 - z = x5291 - z = x5292 - z = x5293 - z = x5294 - z = x5295 - z = x5296 - z = x5297 - z = x5298 - z = x5299 - z = x5300 - z = x5301 - z = x5302 - z = x5303 - z = x5304 - z = x5305 - z = x5306 - z = x5307 - z = x5308 - z = x5309 - z = x5310 - z = x5311 - z = x5312 - z = x5313 - z = x5314 - z = x5315 - z = x5316 - z = x5317 - z = x5318 - z = x5319 - z = x5320 - z = x5321 - z = x5322 - z = x5323 - z = x5324 - z = x5325 - z = x5326 - z = x5327 - z = x5328 - z = x5329 - z = x5330 - z = x5331 - z = x5332 - z = x5333 - z = x5334 - z = x5335 - z = x5336 - z = x5337 - z = x5338 - z = x5339 - z = x5340 - z = x5341 - z = x5342 - z = x5343 - z = x5344 - z = x5345 - z = x5346 - z = x5347 - z = x5348 - z = x5349 - z = x5350 - z = x5351 - z = x5352 - z = x5353 - z = x5354 - z = x5355 - z = x5356 - z = x5357 - z = x5358 - z = x5359 - z = x5360 - z = x5361 - z = x5362 - z = x5363 - z = x5364 - z = x5365 - z = x5366 - z = x5367 - z = x5368 - z = x5369 - z = x5370 - z = x5371 - z = x5372 - z = x5373 - z = x5374 - z = x5375 - z = x5376 - z = x5377 - z = x5378 - z = x5379 - z = x5380 - z = x5381 - z = x5382 - z = x5383 - z = x5384 - z = x5385 - z = x5386 - z = x5387 - z = x5388 - z = x5389 - z = x5390 - z = x5391 - z = x5392 - z = x5393 - z = x5394 - z = x5395 - z = x5396 - z = x5397 - z = x5398 - z = x5399 - z = x5400 - z = x5401 - z = x5402 - z = x5403 - z = x5404 - z = x5405 - z = x5406 - z = x5407 - z = x5408 - z = x5409 - z = x5410 - z = x5411 - z = x5412 - z = x5413 - z = x5414 - z = x5415 - z = x5416 - z = x5417 - z = x5418 - z = x5419 - z = x5420 - z = x5421 - z = x5422 - z = x5423 - z = x5424 - z = x5425 - z = x5426 - z = x5427 - z = x5428 - z = x5429 - z = x5430 - z = x5431 - z = x5432 - z = x5433 - z = x5434 - z = x5435 - z = x5436 - z = x5437 - z = x5438 - z = x5439 - z = x5440 - z = x5441 - z = x5442 - z = x5443 - z = x5444 - z = x5445 - z = x5446 - z = x5447 - z = x5448 - z = x5449 - z = x5450 - z = x5451 - z = x5452 - z = x5453 - z = x5454 - z = x5455 - z = x5456 - z = x5457 - z = x5458 - z = x5459 - z = x5460 - z = x5461 - z = x5462 - z = x5463 - z = x5464 - z = x5465 - z = x5466 - z = x5467 - z = x5468 - z = x5469 - z = x5470 - z = x5471 - z = x5472 - z = x5473 - z = x5474 - z = x5475 - z = x5476 - z = x5477 - z = x5478 - z = x5479 - z = x5480 - z = x5481 - z = x5482 - z = x5483 - z = x5484 - z = x5485 - z = x5486 - z = x5487 - z = x5488 - z = x5489 - z = x5490 - z = x5491 - z = x5492 - z = x5493 - z = x5494 - z = x5495 - z = x5496 - z = x5497 - z = x5498 - z = x5499 - z = x5500 - z = x5501 - z = x5502 - z = x5503 - z = x5504 - z = x5505 - z = x5506 - z = x5507 - z = x5508 - z = x5509 - z = x5510 - z = x5511 - z = x5512 - z = x5513 - z = x5514 - z = x5515 - z = x5516 - z = x5517 - z = x5518 - z = x5519 - z = x5520 - z = x5521 - z = x5522 - z = x5523 - z = x5524 - z = x5525 - z = x5526 - z = x5527 - z = x5528 - z = x5529 - z = x5530 - z = x5531 - z = x5532 - z = x5533 - z = x5534 - z = x5535 - z = x5536 - z = x5537 - z = x5538 - z = x5539 - z = x5540 - z = x5541 - z = x5542 - z = x5543 - z = x5544 - z = x5545 - z = x5546 - z = x5547 - z = x5548 - z = x5549 - z = x5550 - z = x5551 - z = x5552 - z = x5553 - z = x5554 - z = x5555 - z = x5556 - z = x5557 - z = x5558 - z = x5559 - z = x5560 - z = x5561 - z = x5562 - z = x5563 - z = x5564 - z = x5565 - z = x5566 - z = x5567 - z = x5568 - z = x5569 - z = x5570 - z = x5571 - z = x5572 - z = x5573 - z = x5574 - z = x5575 - z = x5576 - z = x5577 - z = x5578 - z = x5579 - z = x5580 - z = x5581 - z = x5582 - z = x5583 - z = x5584 - z = x5585 - z = x5586 - z = x5587 - z = x5588 - z = x5589 - z = x5590 - z = x5591 - z = x5592 - z = x5593 - z = x5594 - z = x5595 - z = x5596 - z = x5597 - z = x5598 - z = x5599 - z = x5600 - z = x5601 - z = x5602 - z = x5603 - z = x5604 - z = x5605 - z = x5606 - z = x5607 - z = x5608 - z = x5609 - z = x5610 - z = x5611 - z = x5612 - z = x5613 - z = x5614 - z = x5615 - z = x5616 - z = x5617 - z = x5618 - z = x5619 - z = x5620 - z = x5621 - z = x5622 - z = x5623 - z = x5624 - z = x5625 - z = x5626 - z = x5627 - z = x5628 - z = x5629 - z = x5630 - z = x5631 - z = x5632 - z = x5633 - z = x5634 - z = x5635 - z = x5636 - z = x5637 - z = x5638 - z = x5639 - z = x5640 - z = x5641 - z = x5642 - z = x5643 - z = x5644 - z = x5645 - z = x5646 - z = x5647 - z = x5648 - z = x5649 - z = x5650 - z = x5651 - z = x5652 - z = x5653 - z = x5654 - z = x5655 - z = x5656 - z = x5657 - z = x5658 - z = x5659 - z = x5660 - z = x5661 - z = x5662 - z = x5663 - z = x5664 - z = x5665 - z = x5666 - z = x5667 - z = x5668 - z = x5669 - z = x5670 - z = x5671 - z = x5672 - z = x5673 - z = x5674 - z = x5675 - z = x5676 - z = x5677 - z = x5678 - z = x5679 - z = x5680 - z = x5681 - z = x5682 - z = x5683 - z = x5684 - z = x5685 - z = x5686 - z = x5687 - z = x5688 - z = x5689 - z = x5690 - z = x5691 - z = x5692 - z = x5693 - z = x5694 - z = x5695 - z = x5696 - z = x5697 - z = x5698 - z = x5699 - z = x5700 - z = x5701 - z = x5702 - z = x5703 - z = x5704 - z = x5705 - z = x5706 - z = x5707 - z = x5708 - z = x5709 - z = x5710 - z = x5711 - z = x5712 - z = x5713 - z = x5714 - z = x5715 - z = x5716 - z = x5717 - z = x5718 - z = x5719 - z = x5720 - z = x5721 - z = x5722 - z = x5723 - z = x5724 - z = x5725 - z = x5726 - z = x5727 - z = x5728 - z = x5729 - z = x5730 - z = x5731 - z = x5732 - z = x5733 - z = x5734 - z = x5735 - z = x5736 - z = x5737 - z = x5738 - z = x5739 - z = x5740 - z = x5741 - z = x5742 - z = x5743 - z = x5744 - z = x5745 - z = x5746 - z = x5747 - z = x5748 - z = x5749 - z = x5750 - z = x5751 - z = x5752 - z = x5753 - z = x5754 - z = x5755 - z = x5756 - z = x5757 - z = x5758 - z = x5759 - z = x5760 - z = x5761 - z = x5762 - z = x5763 - z = x5764 - z = x5765 - z = x5766 - z = x5767 - z = x5768 - z = x5769 - z = x5770 - z = x5771 - z = x5772 - z = x5773 - z = x5774 - z = x5775 - z = x5776 - z = x5777 - z = x5778 - z = x5779 - z = x5780 - z = x5781 - z = x5782 - z = x5783 - z = x5784 - z = x5785 - z = x5786 - z = x5787 - z = x5788 - z = x5789 - z = x5790 - z = x5791 - z = x5792 - z = x5793 - z = x5794 - z = x5795 - z = x5796 - z = x5797 - z = x5798 - z = x5799 - z = x5800 - z = x5801 - z = x5802 - z = x5803 - z = x5804 - z = x5805 - z = x5806 - z = x5807 - z = x5808 - z = x5809 - z = x5810 - z = x5811 - z = x5812 - z = x5813 - z = x5814 - z = x5815 - z = x5816 - z = x5817 - z = x5818 - z = x5819 - z = x5820 - z = x5821 - z = x5822 - z = x5823 - z = x5824 - z = x5825 - z = x5826 - z = x5827 - z = x5828 - z = x5829 - z = x5830 - z = x5831 - z = x5832 - z = x5833 - z = x5834 - z = x5835 - z = x5836 - z = x5837 - z = x5838 - z = x5839 - z = x5840 - z = x5841 - z = x5842 - z = x5843 - z = x5844 - z = x5845 - z = x5846 - z = x5847 - z = x5848 - z = x5849 - z = x5850 - z = x5851 - z = x5852 - z = x5853 - z = x5854 - z = x5855 - z = x5856 - z = x5857 - z = x5858 - z = x5859 - z = x5860 - z = x5861 - z = x5862 - z = x5863 - z = x5864 - z = x5865 - z = x5866 - z = x5867 - z = x5868 - z = x5869 - z = x5870 - z = x5871 - z = x5872 - z = x5873 - z = x5874 - z = x5875 - z = x5876 - z = x5877 - z = x5878 - z = x5879 - z = x5880 - z = x5881 - z = x5882 - z = x5883 - z = x5884 - z = x5885 - z = x5886 - z = x5887 - z = x5888 - z = x5889 - z = x5890 - z = x5891 - z = x5892 - z = x5893 - z = x5894 - z = x5895 - z = x5896 - z = x5897 - z = x5898 - z = x5899 - z = x5900 - z = x5901 - z = x5902 - z = x5903 - z = x5904 - z = x5905 - z = x5906 - z = x5907 - z = x5908 - z = x5909 - z = x5910 - z = x5911 - z = x5912 - z = x5913 - z = x5914 - z = x5915 - z = x5916 - z = x5917 - z = x5918 - z = x5919 - z = x5920 - z = x5921 - z = x5922 - z = x5923 - z = x5924 - z = x5925 - z = x5926 - z = x5927 - z = x5928 - z = x5929 - z = x5930 - z = x5931 - z = x5932 - z = x5933 - z = x5934 - z = x5935 - z = x5936 - z = x5937 - z = x5938 - z = x5939 - z = x5940 - z = x5941 - z = x5942 - z = x5943 - z = x5944 - z = x5945 - z = x5946 - z = x5947 - z = x5948 - z = x5949 - z = x5950 - z = x5951 - z = x5952 - z = x5953 - z = x5954 - z = x5955 - z = x5956 - z = x5957 - z = x5958 - z = x5959 - z = x5960 - z = x5961 - z = x5962 - z = x5963 - z = x5964 - z = x5965 - z = x5966 - z = x5967 - z = x5968 - z = x5969 - z = x5970 - z = x5971 - z = x5972 - z = x5973 - z = x5974 - z = x5975 - z = x5976 - z = x5977 - z = x5978 - z = x5979 - z = x5980 - z = x5981 - z = x5982 - z = x5983 - z = x5984 - z = x5985 - z = x5986 - z = x5987 - z = x5988 - z = x5989 - z = x5990 - z = x5991 - z = x5992 - z = x5993 - z = x5994 - z = x5995 - z = x5996 - z = x5997 - z = x5998 - z = x5999 - z = x6000 - z = x6001 - z = x6002 - z = x6003 - z = x6004 - z = x6005 - z = x6006 - z = x6007 - z = x6008 - z = x6009 - z = x6010 - z = x6011 - z = x6012 - z = x6013 - z = x6014 - z = x6015 - z = x6016 - z = x6017 - z = x6018 - z = x6019 - z = x6020 - z = x6021 - z = x6022 - z = x6023 - z = x6024 - z = x6025 - z = x6026 - z = x6027 - z = x6028 - z = x6029 - z = x6030 - z = x6031 - z = x6032 - z = x6033 - z = x6034 - z = x6035 - z = x6036 - z = x6037 - z = x6038 - z = x6039 - z = x6040 - z = x6041 - z = x6042 - z = x6043 - z = x6044 - z = x6045 - z = x6046 - z = x6047 - z = x6048 - z = x6049 - z = x6050 - z = x6051 - z = x6052 - z = x6053 - z = x6054 - z = x6055 - z = x6056 - z = x6057 - z = x6058 - z = x6059 - z = x6060 - z = x6061 - z = x6062 - z = x6063 - z = x6064 - z = x6065 - z = x6066 - z = x6067 - z = x6068 - z = x6069 - z = x6070 - z = x6071 - z = x6072 - z = x6073 - z = x6074 - z = x6075 - z = x6076 - z = x6077 - z = x6078 - z = x6079 - z = x6080 - z = x6081 - z = x6082 - z = x6083 - z = x6084 - z = x6085 - z = x6086 - z = x6087 - z = x6088 - z = x6089 - z = x6090 - z = x6091 - z = x6092 - z = x6093 - z = x6094 - z = x6095 - z = x6096 - z = x6097 - z = x6098 - z = x6099 - z = x6100 - z = x6101 - z = x6102 - z = x6103 - z = x6104 - z = x6105 - z = x6106 - z = x6107 - z = x6108 - z = x6109 - z = x6110 - z = x6111 - z = x6112 - z = x6113 - z = x6114 - z = x6115 - z = x6116 - z = x6117 - z = x6118 - z = x6119 - z = x6120 - z = x6121 - z = x6122 - z = x6123 - z = x6124 - z = x6125 - z = x6126 - z = x6127 - z = x6128 - z = x6129 - z = x6130 - z = x6131 - z = x6132 - z = x6133 - z = x6134 - z = x6135 - z = x6136 - z = x6137 - z = x6138 - z = x6139 - z = x6140 - z = x6141 - z = x6142 - z = x6143 - z = x6144 - z = x6145 - z = x6146 - z = x6147 - z = x6148 - z = x6149 - z = x6150 - z = x6151 - z = x6152 - z = x6153 - z = x6154 - z = x6155 - z = x6156 - z = x6157 - z = x6158 - z = x6159 - z = x6160 - z = x6161 - z = x6162 - z = x6163 - z = x6164 - z = x6165 - z = x6166 - z = x6167 - z = x6168 - z = x6169 - z = x6170 - z = x6171 - z = x6172 - z = x6173 - z = x6174 - z = x6175 - z = x6176 - z = x6177 - z = x6178 - z = x6179 - z = x6180 - z = x6181 - z = x6182 - z = x6183 - z = x6184 - z = x6185 - z = x6186 - z = x6187 - z = x6188 - z = x6189 - z = x6190 - z = x6191 - z = x6192 - z = x6193 - z = x6194 - z = x6195 - z = x6196 - z = x6197 - z = x6198 - z = x6199 - z = x6200 - z = x6201 - z = x6202 - z = x6203 - z = x6204 - z = x6205 - z = x6206 - z = x6207 - z = x6208 - z = x6209 - z = x6210 - z = x6211 - z = x6212 - z = x6213 - z = x6214 - z = x6215 - z = x6216 - z = x6217 - z = x6218 - z = x6219 - z = x6220 - z = x6221 - z = x6222 - z = x6223 - z = x6224 - z = x6225 - z = x6226 - z = x6227 - z = x6228 - z = x6229 - z = x6230 - z = x6231 - z = x6232 - z = x6233 - z = x6234 - z = x6235 - z = x6236 - z = x6237 - z = x6238 - z = x6239 - z = x6240 - z = x6241 - z = x6242 - z = x6243 - z = x6244 - z = x6245 - z = x6246 - z = x6247 - z = x6248 - z = x6249 - z = x6250 - z = x6251 - z = x6252 - z = x6253 - z = x6254 - z = x6255 - z = x6256 - z = x6257 - z = x6258 - z = x6259 - z = x6260 - z = x6261 - z = x6262 - z = x6263 - z = x6264 - z = x6265 - z = x6266 - z = x6267 - z = x6268 - z = x6269 - z = x6270 - z = x6271 - z = x6272 - z = x6273 - z = x6274 - z = x6275 - z = x6276 - z = x6277 - z = x6278 - z = x6279 - z = x6280 - z = x6281 - z = x6282 - z = x6283 - z = x6284 - z = x6285 - z = x6286 - z = x6287 - z = x6288 - z = x6289 - z = x6290 - z = x6291 - z = x6292 - z = x6293 - z = x6294 - z = x6295 - z = x6296 - z = x6297 - z = x6298 - z = x6299 - z = x6300 - z = x6301 - z = x6302 - z = x6303 - z = x6304 - z = x6305 - z = x6306 - z = x6307 - z = x6308 - z = x6309 - z = x6310 - z = x6311 - z = x6312 - z = x6313 - z = x6314 - z = x6315 - z = x6316 - z = x6317 - z = x6318 - z = x6319 - z = x6320 - z = x6321 - z = x6322 - z = x6323 - z = x6324 - z = x6325 - z = x6326 - z = x6327 - z = x6328 - z = x6329 - z = x6330 - z = x6331 - z = x6332 - z = x6333 - z = x6334 - z = x6335 - z = x6336 - z = x6337 - z = x6338 - z = x6339 - z = x6340 - z = x6341 - z = x6342 - z = x6343 - z = x6344 - z = x6345 - z = x6346 - z = x6347 - z = x6348 - z = x6349 - z = x6350 - z = x6351 - z = x6352 - z = x6353 - z = x6354 - z = x6355 - z = x6356 - z = x6357 - z = x6358 - z = x6359 - z = x6360 - z = x6361 - z = x6362 - z = x6363 - z = x6364 - z = x6365 - z = x6366 - z = x6367 - z = x6368 - z = x6369 - z = x6370 - z = x6371 - z = x6372 - z = x6373 - z = x6374 - z = x6375 - z = x6376 - z = x6377 - z = x6378 - z = x6379 - z = x6380 - z = x6381 - z = x6382 - z = x6383 - z = x6384 - z = x6385 - z = x6386 - z = x6387 - z = x6388 - z = x6389 - z = x6390 - z = x6391 - z = x6392 - z = x6393 - z = x6394 - z = x6395 - z = x6396 - z = x6397 - z = x6398 - z = x6399 - z = x6400 - z = x6401 - z = x6402 - z = x6403 - z = x6404 - z = x6405 - z = x6406 - z = x6407 - z = x6408 - z = x6409 - z = x6410 - z = x6411 - z = x6412 - z = x6413 - z = x6414 - z = x6415 - z = x6416 - z = x6417 - z = x6418 - z = x6419 - z = x6420 - z = x6421 - z = x6422 - z = x6423 - z = x6424 - z = x6425 - z = x6426 - z = x6427 - z = x6428 - z = x6429 - z = x6430 - z = x6431 - z = x6432 - z = x6433 - z = x6434 - z = x6435 - z = x6436 - z = x6437 - z = x6438 - z = x6439 - z = x6440 - z = x6441 - z = x6442 - z = x6443 - z = x6444 - z = x6445 - z = x6446 - z = x6447 - z = x6448 - z = x6449 - z = x6450 - z = x6451 - z = x6452 - z = x6453 - z = x6454 - z = x6455 - z = x6456 - z = x6457 - z = x6458 - z = x6459 - z = x6460 - z = x6461 - z = x6462 - z = x6463 - z = x6464 - z = x6465 - z = x6466 - z = x6467 - z = x6468 - z = x6469 - z = x6470 - z = x6471 - z = x6472 - z = x6473 - z = x6474 - z = x6475 - z = x6476 - z = x6477 - z = x6478 - z = x6479 - z = x6480 - z = x6481 - z = x6482 - z = x6483 - z = x6484 - z = x6485 - z = x6486 - z = x6487 - z = x6488 - z = x6489 - z = x6490 - z = x6491 - z = x6492 - z = x6493 - z = x6494 - z = x6495 - z = x6496 - z = x6497 - z = x6498 - z = x6499 - z = x6500 - z = x6501 - z = x6502 - z = x6503 - z = x6504 - z = x6505 - z = x6506 - z = x6507 - z = x6508 - z = x6509 - z = x6510 - z = x6511 - z = x6512 - z = x6513 - z = x6514 - z = x6515 - z = x6516 - z = x6517 - z = x6518 - z = x6519 - z = x6520 - z = x6521 - z = x6522 - z = x6523 - z = x6524 - z = x6525 - z = x6526 - z = x6527 - z = x6528 - z = x6529 - z = x6530 - z = x6531 - z = x6532 - z = x6533 - z = x6534 - z = x6535 - z = x6536 - z = x6537 - z = x6538 - z = x6539 - z = x6540 - z = x6541 - z = x6542 - z = x6543 - z = x6544 - z = x6545 - z = x6546 - z = x6547 - z = x6548 - z = x6549 - z = x6550 - z = x6551 - z = x6552 - z = x6553 - z = x6554 - z = x6555 - z = x6556 - z = x6557 - z = x6558 - z = x6559 - z = x6560 - z = x6561 - z = x6562 - z = x6563 - z = x6564 - z = x6565 - z = x6566 - z = x6567 - z = x6568 - z = x6569 - z = x6570 - z = x6571 - z = x6572 - z = x6573 - z = x6574 - z = x6575 - z = x6576 - z = x6577 - z = x6578 - z = x6579 - z = x6580 - z = x6581 - z = x6582 - z = x6583 - z = x6584 - z = x6585 - z = x6586 - z = x6587 - z = x6588 - z = x6589 - z = x6590 - z = x6591 - z = x6592 - z = x6593 - z = x6594 - z = x6595 - z = x6596 - z = x6597 - z = x6598 - z = x6599 - z = x6600 - z = x6601 - z = x6602 - z = x6603 - z = x6604 - z = x6605 - z = x6606 - z = x6607 - z = x6608 - z = x6609 - z = x6610 - z = x6611 - z = x6612 - z = x6613 - z = x6614 - z = x6615 - z = x6616 - z = x6617 - z = x6618 - z = x6619 - z = x6620 - z = x6621 - z = x6622 - z = x6623 - z = x6624 - z = x6625 - z = x6626 - z = x6627 - z = x6628 - z = x6629 - z = x6630 - z = x6631 - z = x6632 - z = x6633 - z = x6634 - z = x6635 - z = x6636 - z = x6637 - z = x6638 - z = x6639 - z = x6640 - z = x6641 - z = x6642 - z = x6643 - z = x6644 - z = x6645 - z = x6646 - z = x6647 - z = x6648 - z = x6649 - z = x6650 - z = x6651 - z = x6652 - z = x6653 - z = x6654 - z = x6655 - z = x6656 - z = x6657 - z = x6658 - z = x6659 - z = x6660 - z = x6661 - z = x6662 - z = x6663 - z = x6664 - z = x6665 - z = x6666 - z = x6667 - z = x6668 - z = x6669 - z = x6670 - z = x6671 - z = x6672 - z = x6673 - z = x6674 - z = x6675 - z = x6676 - z = x6677 - z = x6678 - z = x6679 - z = x6680 - z = x6681 - z = x6682 - z = x6683 - z = x6684 - z = x6685 - z = x6686 - z = x6687 - z = x6688 - z = x6689 - z = x6690 - z = x6691 - z = x6692 - z = x6693 - z = x6694 - z = x6695 - z = x6696 - z = x6697 - z = x6698 - z = x6699 - z = x6700 - z = x6701 - z = x6702 - z = x6703 - z = x6704 - z = x6705 - z = x6706 - z = x6707 - z = x6708 - z = x6709 - z = x6710 - z = x6711 - z = x6712 - z = x6713 - z = x6714 - z = x6715 - z = x6716 - z = x6717 - z = x6718 - z = x6719 - z = x6720 - z = x6721 - z = x6722 - z = x6723 - z = x6724 - z = x6725 - z = x6726 - z = x6727 - z = x6728 - z = x6729 - z = x6730 - z = x6731 - z = x6732 - z = x6733 - z = x6734 - z = x6735 - z = x6736 - z = x6737 - z = x6738 - z = x6739 - z = x6740 - z = x6741 - z = x6742 - z = x6743 - z = x6744 - z = x6745 - z = x6746 - z = x6747 - z = x6748 - z = x6749 - z = x6750 - z = x6751 - z = x6752 - z = x6753 - z = x6754 - z = x6755 - z = x6756 - z = x6757 - z = x6758 - z = x6759 - z = x6760 - z = x6761 - z = x6762 - z = x6763 - z = x6764 - z = x6765 - z = x6766 - z = x6767 - z = x6768 - z = x6769 - z = x6770 - z = x6771 - z = x6772 - z = x6773 - z = x6774 - z = x6775 - z = x6776 - z = x6777 - z = x6778 - z = x6779 - z = x6780 - z = x6781 - z = x6782 - z = x6783 - z = x6784 - z = x6785 - z = x6786 - z = x6787 - z = x6788 - z = x6789 - z = x6790 - z = x6791 - z = x6792 - z = x6793 - z = x6794 - z = x6795 - z = x6796 - z = x6797 - z = x6798 - z = x6799 - z = x6800 - z = x6801 - z = x6802 - z = x6803 - z = x6804 - z = x6805 - z = x6806 - z = x6807 - z = x6808 - z = x6809 - z = x6810 - z = x6811 - z = x6812 - z = x6813 - z = x6814 - z = x6815 - z = x6816 - z = x6817 - z = x6818 - z = x6819 - z = x6820 - z = x6821 - z = x6822 - z = x6823 - z = x6824 - z = x6825 - z = x6826 - z = x6827 - z = x6828 - z = x6829 - z = x6830 - z = x6831 - z = x6832 - z = x6833 - z = x6834 - z = x6835 - z = x6836 - z = x6837 - z = x6838 - z = x6839 - z = x6840 - z = x6841 - z = x6842 - z = x6843 - z = x6844 - z = x6845 - z = x6846 - z = x6847 - z = x6848 - z = x6849 - z = x6850 - z = x6851 - z = x6852 - z = x6853 - z = x6854 - z = x6855 - z = x6856 - z = x6857 - z = x6858 - z = x6859 - z = x6860 - z = x6861 - z = x6862 - z = x6863 - z = x6864 - z = x6865 - z = x6866 - z = x6867 - z = x6868 - z = x6869 - z = x6870 - z = x6871 - z = x6872 - z = x6873 - z = x6874 - z = x6875 - z = x6876 - z = x6877 - z = x6878 - z = x6879 - z = x6880 - z = x6881 - z = x6882 - z = x6883 - z = x6884 - z = x6885 - z = x6886 - z = x6887 - z = x6888 - z = x6889 - z = x6890 - z = x6891 - z = x6892 - z = x6893 - z = x6894 - z = x6895 - z = x6896 - z = x6897 - z = x6898 - z = x6899 - z = x6900 - z = x6901 - z = x6902 - z = x6903 - z = x6904 - z = x6905 - z = x6906 - z = x6907 - z = x6908 - z = x6909 - z = x6910 - z = x6911 - z = x6912 - z = x6913 - z = x6914 - z = x6915 - z = x6916 - z = x6917 - z = x6918 - z = x6919 - z = x6920 - z = x6921 - z = x6922 - z = x6923 - z = x6924 - z = x6925 - z = x6926 - z = x6927 - z = x6928 - z = x6929 - z = x6930 - z = x6931 - z = x6932 - z = x6933 - z = x6934 - z = x6935 - z = x6936 - z = x6937 - z = x6938 - z = x6939 - z = x6940 - z = x6941 - z = x6942 - z = x6943 - z = x6944 - z = x6945 - z = x6946 - z = x6947 - z = x6948 - z = x6949 - z = x6950 - z = x6951 - z = x6952 - z = x6953 - z = x6954 - z = x6955 - z = x6956 - z = x6957 - z = x6958 - z = x6959 - z = x6960 - z = x6961 - z = x6962 - z = x6963 - z = x6964 - z = x6965 - z = x6966 - z = x6967 - z = x6968 - z = x6969 - z = x6970 - z = x6971 - z = x6972 - z = x6973 - z = x6974 - z = x6975 - z = x6976 - z = x6977 - z = x6978 - z = x6979 - z = x6980 - z = x6981 - z = x6982 - z = x6983 - z = x6984 - z = x6985 - z = x6986 - z = x6987 - z = x6988 - z = x6989 - z = x6990 - z = x6991 - z = x6992 - z = x6993 - z = x6994 - z = x6995 - z = x6996 - z = x6997 - z = x6998 - z = x6999 - z = x7000 - z = x7001 - z = x7002 - z = x7003 - z = x7004 - z = x7005 - z = x7006 - z = x7007 - z = x7008 - z = x7009 - z = x7010 - z = x7011 - z = x7012 - z = x7013 - z = x7014 - z = x7015 - z = x7016 - z = x7017 - z = x7018 - z = x7019 - z = x7020 - z = x7021 - z = x7022 - z = x7023 - z = x7024 - z = x7025 - z = x7026 - z = x7027 - z = x7028 - z = x7029 - z = x7030 - z = x7031 - z = x7032 - z = x7033 - z = x7034 - z = x7035 - z = x7036 - z = x7037 - z = x7038 - z = x7039 - z = x7040 - z = x7041 - z = x7042 - z = x7043 - z = x7044 - z = x7045 - z = x7046 - z = x7047 - z = x7048 - z = x7049 - z = x7050 - z = x7051 - z = x7052 - z = x7053 - z = x7054 - z = x7055 - z = x7056 - z = x7057 - z = x7058 - z = x7059 - z = x7060 - z = x7061 - z = x7062 - z = x7063 - z = x7064 - z = x7065 - z = x7066 - z = x7067 - z = x7068 - z = x7069 - z = x7070 - z = x7071 - z = x7072 - z = x7073 - z = x7074 - z = x7075 - z = x7076 - z = x7077 - z = x7078 - z = x7079 - z = x7080 - z = x7081 - z = x7082 - z = x7083 - z = x7084 - z = x7085 - z = x7086 - z = x7087 - z = x7088 - z = x7089 - z = x7090 - z = x7091 - z = x7092 - z = x7093 - z = x7094 - z = x7095 - z = x7096 - z = x7097 - z = x7098 - z = x7099 - z = x7100 - z = x7101 - z = x7102 - z = x7103 - z = x7104 - z = x7105 - z = x7106 - z = x7107 - z = x7108 - z = x7109 - z = x7110 - z = x7111 - z = x7112 - z = x7113 - z = x7114 - z = x7115 - z = x7116 - z = x7117 - z = x7118 - z = x7119 - z = x7120 - z = x7121 - z = x7122 - z = x7123 - z = x7124 - z = x7125 - z = x7126 - z = x7127 - z = x7128 - z = x7129 - z = x7130 - z = x7131 - z = x7132 - z = x7133 - z = x7134 - z = x7135 - z = x7136 - z = x7137 - z = x7138 - z = x7139 - z = x7140 - z = x7141 - z = x7142 - z = x7143 - z = x7144 - z = x7145 - z = x7146 - z = x7147 - z = x7148 - z = x7149 - z = x7150 - z = x7151 - z = x7152 - z = x7153 - z = x7154 - z = x7155 - z = x7156 - z = x7157 - z = x7158 - z = x7159 - z = x7160 - z = x7161 - z = x7162 - z = x7163 - z = x7164 - z = x7165 - z = x7166 - z = x7167 - z = x7168 - z = x7169 - z = x7170 - z = x7171 - z = x7172 - z = x7173 - z = x7174 - z = x7175 - z = x7176 - z = x7177 - z = x7178 - z = x7179 - z = x7180 - z = x7181 - z = x7182 - z = x7183 - z = x7184 - z = x7185 - z = x7186 - z = x7187 - z = x7188 - z = x7189 - z = x7190 - z = x7191 - z = x7192 - z = x7193 - z = x7194 - z = x7195 - z = x7196 - z = x7197 - z = x7198 - z = x7199 - z = x7200 - z = x7201 - z = x7202 - z = x7203 - z = x7204 - z = x7205 - z = x7206 - z = x7207 - z = x7208 - z = x7209 - z = x7210 - z = x7211 - z = x7212 - z = x7213 - z = x7214 - z = x7215 - z = x7216 - z = x7217 - z = x7218 - z = x7219 - z = x7220 - z = x7221 - z = x7222 - z = x7223 - z = x7224 - z = x7225 - z = x7226 - z = x7227 - z = x7228 - z = x7229 - z = x7230 - z = x7231 - z = x7232 - z = x7233 - z = x7234 - z = x7235 - z = x7236 - z = x7237 - z = x7238 - z = x7239 - z = x7240 - z = x7241 - z = x7242 - z = x7243 - z = x7244 - z = x7245 - z = x7246 - z = x7247 - z = x7248 - z = x7249 - z = x7250 - z = x7251 - z = x7252 - z = x7253 - z = x7254 - z = x7255 - z = x7256 - z = x7257 - z = x7258 - z = x7259 - z = x7260 - z = x7261 - z = x7262 - z = x7263 - z = x7264 - z = x7265 - z = x7266 - z = x7267 - z = x7268 - z = x7269 - z = x7270 - z = x7271 - z = x7272 - z = x7273 - z = x7274 - z = x7275 - z = x7276 - z = x7277 - z = x7278 - z = x7279 - z = x7280 - z = x7281 - z = x7282 - z = x7283 - z = x7284 - z = x7285 - z = x7286 - z = x7287 - z = x7288 - z = x7289 - z = x7290 - z = x7291 - z = x7292 - z = x7293 - z = x7294 - z = x7295 - z = x7296 - z = x7297 - z = x7298 - z = x7299 - z = x7300 - z = x7301 - z = x7302 - z = x7303 - z = x7304 - z = x7305 - z = x7306 - z = x7307 - z = x7308 - z = x7309 - z = x7310 - z = x7311 - z = x7312 - z = x7313 - z = x7314 - z = x7315 - z = x7316 - z = x7317 - z = x7318 - z = x7319 - z = x7320 - z = x7321 - z = x7322 - z = x7323 - z = x7324 - z = x7325 - z = x7326 - z = x7327 - z = x7328 - z = x7329 - z = x7330 - z = x7331 - z = x7332 - z = x7333 - z = x7334 - z = x7335 - z = x7336 - z = x7337 - z = x7338 - z = x7339 - z = x7340 - z = x7341 - z = x7342 - z = x7343 - z = x7344 - z = x7345 - z = x7346 - z = x7347 - z = x7348 - z = x7349 - z = x7350 - z = x7351 - z = x7352 - z = x7353 - z = x7354 - z = x7355 - z = x7356 - z = x7357 - z = x7358 - z = x7359 - z = x7360 - z = x7361 - z = x7362 - z = x7363 - z = x7364 - z = x7365 - z = x7366 - z = x7367 - z = x7368 - z = x7369 - z = x7370 - z = x7371 - z = x7372 - z = x7373 - z = x7374 - z = x7375 - z = x7376 - z = x7377 - z = x7378 - z = x7379 - z = x7380 - z = x7381 - z = x7382 - z = x7383 - z = x7384 - z = x7385 - z = x7386 - z = x7387 - z = x7388 - z = x7389 - z = x7390 - z = x7391 - z = x7392 - z = x7393 - z = x7394 - z = x7395 - z = x7396 - z = x7397 - z = x7398 - z = x7399 - z = x7400 - z = x7401 - z = x7402 - z = x7403 - z = x7404 - z = x7405 - z = x7406 - z = x7407 - z = x7408 - z = x7409 - z = x7410 - z = x7411 - z = x7412 - z = x7413 - z = x7414 - z = x7415 - z = x7416 - z = x7417 - z = x7418 - z = x7419 - z = x7420 - z = x7421 - z = x7422 - z = x7423 - z = x7424 - z = x7425 - z = x7426 - z = x7427 - z = x7428 - z = x7429 - z = x7430 - z = x7431 - z = x7432 - z = x7433 - z = x7434 - z = x7435 - z = x7436 - z = x7437 - z = x7438 - z = x7439 - z = x7440 - z = x7441 - z = x7442 - z = x7443 - z = x7444 - z = x7445 - z = x7446 - z = x7447 - z = x7448 - z = x7449 - z = x7450 - z = x7451 - z = x7452 - z = x7453 - z = x7454 - z = x7455 - z = x7456 - z = x7457 - z = x7458 - z = x7459 - z = x7460 - z = x7461 - z = x7462 - z = x7463 - z = x7464 - z = x7465 - z = x7466 - z = x7467 - z = x7468 - z = x7469 - z = x7470 - z = x7471 - z = x7472 - z = x7473 - z = x7474 - z = x7475 - z = x7476 - z = x7477 - z = x7478 - z = x7479 - z = x7480 - z = x7481 - z = x7482 - z = x7483 - z = x7484 - z = x7485 - z = x7486 - z = x7487 - z = x7488 - z = x7489 - z = x7490 - z = x7491 - z = x7492 - z = x7493 - z = x7494 - z = x7495 - z = x7496 - z = x7497 - z = x7498 - z = x7499 - z = x7500 - z = x7501 - z = x7502 - z = x7503 - z = x7504 - z = x7505 - z = x7506 - z = x7507 - z = x7508 - z = x7509 - z = x7510 - z = x7511 - z = x7512 - z = x7513 - z = x7514 - z = x7515 - z = x7516 - z = x7517 - z = x7518 - z = x7519 - z = x7520 - z = x7521 - z = x7522 - z = x7523 - z = x7524 - z = x7525 - z = x7526 - z = x7527 - z = x7528 - z = x7529 - z = x7530 - z = x7531 - z = x7532 - z = x7533 - z = x7534 - z = x7535 - z = x7536 - z = x7537 - z = x7538 - z = x7539 - z = x7540 - z = x7541 - z = x7542 - z = x7543 - z = x7544 - z = x7545 - z = x7546 - z = x7547 - z = x7548 - z = x7549 - z = x7550 - z = x7551 - z = x7552 - z = x7553 - z = x7554 - z = x7555 - z = x7556 - z = x7557 - z = x7558 - z = x7559 - z = x7560 - z = x7561 - z = x7562 - z = x7563 - z = x7564 - z = x7565 - z = x7566 - z = x7567 - z = x7568 - z = x7569 - z = x7570 - z = x7571 - z = x7572 - z = x7573 - z = x7574 - z = x7575 - z = x7576 - z = x7577 - z = x7578 - z = x7579 - z = x7580 - z = x7581 - z = x7582 - z = x7583 - z = x7584 - z = x7585 - z = x7586 - z = x7587 - z = x7588 - z = x7589 - z = x7590 - z = x7591 - z = x7592 - z = x7593 - z = x7594 - z = x7595 - z = x7596 - z = x7597 - z = x7598 - z = x7599 - z = x7600 - z = x7601 - z = x7602 - z = x7603 - z = x7604 - z = x7605 - z = x7606 - z = x7607 - z = x7608 - z = x7609 - z = x7610 - z = x7611 - z = x7612 - z = x7613 - z = x7614 - z = x7615 - z = x7616 - z = x7617 - z = x7618 - z = x7619 - z = x7620 - z = x7621 - z = x7622 - z = x7623 - z = x7624 - z = x7625 - z = x7626 - z = x7627 - z = x7628 - z = x7629 - z = x7630 - z = x7631 - z = x7632 - z = x7633 - z = x7634 - z = x7635 - z = x7636 - z = x7637 - z = x7638 - z = x7639 - z = x7640 - z = x7641 - z = x7642 - z = x7643 - z = x7644 - z = x7645 - z = x7646 - z = x7647 - z = x7648 - z = x7649 - z = x7650 - z = x7651 - z = x7652 - z = x7653 - z = x7654 - z = x7655 - z = x7656 - z = x7657 - z = x7658 - z = x7659 - z = x7660 - z = x7661 - z = x7662 - z = x7663 - z = x7664 - z = x7665 - z = x7666 - z = x7667 - z = x7668 - z = x7669 - z = x7670 - z = x7671 - z = x7672 - z = x7673 - z = x7674 - z = x7675 - z = x7676 - z = x7677 - z = x7678 - z = x7679 - z = x7680 - z = x7681 - z = x7682 - z = x7683 - z = x7684 - z = x7685 - z = x7686 - z = x7687 - z = x7688 - z = x7689 - z = x7690 - z = x7691 - z = x7692 - z = x7693 - z = x7694 - z = x7695 - z = x7696 - z = x7697 - z = x7698 - z = x7699 - z = x7700 - z = x7701 - z = x7702 - z = x7703 - z = x7704 - z = x7705 - z = x7706 - z = x7707 - z = x7708 - z = x7709 - z = x7710 - z = x7711 - z = x7712 - z = x7713 - z = x7714 - z = x7715 - z = x7716 - z = x7717 - z = x7718 - z = x7719 - z = x7720 - z = x7721 - z = x7722 - z = x7723 - z = x7724 - z = x7725 - z = x7726 - z = x7727 - z = x7728 - z = x7729 - z = x7730 - z = x7731 - z = x7732 - z = x7733 - z = x7734 - z = x7735 - z = x7736 - z = x7737 - z = x7738 - z = x7739 - z = x7740 - z = x7741 - z = x7742 - z = x7743 - z = x7744 - z = x7745 - z = x7746 - z = x7747 - z = x7748 - z = x7749 - z = x7750 - z = x7751 - z = x7752 - z = x7753 - z = x7754 - z = x7755 - z = x7756 - z = x7757 - z = x7758 - z = x7759 - z = x7760 - z = x7761 - z = x7762 - z = x7763 - z = x7764 - z = x7765 - z = x7766 - z = x7767 - z = x7768 - z = x7769 - z = x7770 - z = x7771 - z = x7772 - z = x7773 - z = x7774 - z = x7775 - z = x7776 - z = x7777 - z = x7778 - z = x7779 - z = x7780 - z = x7781 - z = x7782 - z = x7783 - z = x7784 - z = x7785 - z = x7786 - z = x7787 - z = x7788 - z = x7789 - z = x7790 - z = x7791 - z = x7792 - z = x7793 - z = x7794 - z = x7795 - z = x7796 - z = x7797 - z = x7798 - z = x7799 - z = x7800 - z = x7801 - z = x7802 - z = x7803 - z = x7804 - z = x7805 - z = x7806 - z = x7807 - z = x7808 - z = x7809 - z = x7810 - z = x7811 - z = x7812 - z = x7813 - z = x7814 - z = x7815 - z = x7816 - z = x7817 - z = x7818 - z = x7819 - z = x7820 - z = x7821 - z = x7822 - z = x7823 - z = x7824 - z = x7825 - z = x7826 - z = x7827 - z = x7828 - z = x7829 - z = x7830 - z = x7831 - z = x7832 - z = x7833 - z = x7834 - z = x7835 - z = x7836 - z = x7837 - z = x7838 - z = x7839 - z = x7840 - z = x7841 - z = x7842 - z = x7843 - z = x7844 - z = x7845 - z = x7846 - z = x7847 - z = x7848 - z = x7849 - z = x7850 - z = x7851 - z = x7852 - z = x7853 - z = x7854 - z = x7855 - z = x7856 - z = x7857 - z = x7858 - z = x7859 - z = x7860 - z = x7861 - z = x7862 - z = x7863 - z = x7864 - z = x7865 - z = x7866 - z = x7867 - z = x7868 - z = x7869 - z = x7870 - z = x7871 - z = x7872 - z = x7873 - z = x7874 - z = x7875 - z = x7876 - z = x7877 - z = x7878 - z = x7879 - z = x7880 - z = x7881 - z = x7882 - z = x7883 - z = x7884 - z = x7885 - z = x7886 - z = x7887 - z = x7888 - z = x7889 - z = x7890 - z = x7891 - z = x7892 - z = x7893 - z = x7894 - z = x7895 - z = x7896 - z = x7897 - z = x7898 - z = x7899 - z = x7900 - z = x7901 - z = x7902 - z = x7903 - z = x7904 - z = x7905 - z = x7906 - z = x7907 - z = x7908 - z = x7909 - z = x7910 - z = x7911 - z = x7912 - z = x7913 - z = x7914 - z = x7915 - z = x7916 - z = x7917 - z = x7918 - z = x7919 - z = x7920 - z = x7921 - z = x7922 - z = x7923 - z = x7924 - z = x7925 - z = x7926 - z = x7927 - z = x7928 - z = x7929 - z = x7930 - z = x7931 - z = x7932 - z = x7933 - z = x7934 - z = x7935 - z = x7936 - z = x7937 - z = x7938 - z = x7939 - z = x7940 - z = x7941 - z = x7942 - z = x7943 - z = x7944 - z = x7945 - z = x7946 - z = x7947 - z = x7948 - z = x7949 - z = x7950 - z = x7951 - z = x7952 - z = x7953 - z = x7954 - z = x7955 - z = x7956 - z = x7957 - z = x7958 - z = x7959 - z = x7960 - z = x7961 - z = x7962 - z = x7963 - z = x7964 - z = x7965 - z = x7966 - z = x7967 - z = x7968 - z = x7969 - z = x7970 - z = x7971 - z = x7972 - z = x7973 - z = x7974 - z = x7975 - z = x7976 - z = x7977 - z = x7978 - z = x7979 - z = x7980 - z = x7981 - z = x7982 - z = x7983 - z = x7984 - z = x7985 - z = x7986 - z = x7987 - z = x7988 - z = x7989 - z = x7990 - z = x7991 - z = x7992 - z = x7993 - z = x7994 - z = x7995 - z = x7996 - z = x7997 - z = x7998 - z = x7999 - z = x8000 - z = x8001 - z = x8002 - z = x8003 - z = x8004 - z = x8005 - z = x8006 - z = x8007 - z = x8008 - z = x8009 - z = x8010 - z = x8011 - z = x8012 - z = x8013 - z = x8014 - z = x8015 - z = x8016 - z = x8017 - z = x8018 - z = x8019 - z = x8020 - z = x8021 - z = x8022 - z = x8023 - z = x8024 - z = x8025 - z = x8026 - z = x8027 - z = x8028 - z = x8029 - z = x8030 - z = x8031 - z = x8032 - z = x8033 - z = x8034 - z = x8035 - z = x8036 - z = x8037 - z = x8038 - z = x8039 - z = x8040 - z = x8041 - z = x8042 - z = x8043 - z = x8044 - z = x8045 - z = x8046 - z = x8047 - z = x8048 - z = x8049 - z = x8050 - z = x8051 - z = x8052 - z = x8053 - z = x8054 - z = x8055 - z = x8056 - z = x8057 - z = x8058 - z = x8059 - z = x8060 - z = x8061 - z = x8062 - z = x8063 - z = x8064 - z = x8065 - z = x8066 - z = x8067 - z = x8068 - z = x8069 - z = x8070 - z = x8071 - z = x8072 - z = x8073 - z = x8074 - z = x8075 - z = x8076 - z = x8077 - z = x8078 - z = x8079 - z = x8080 - z = x8081 - z = x8082 - z = x8083 - z = x8084 - z = x8085 - z = x8086 - z = x8087 - z = x8088 - z = x8089 - z = x8090 - z = x8091 - z = x8092 - z = x8093 - z = x8094 - z = x8095 - z = x8096 - z = x8097 - z = x8098 - z = x8099 - z = x8100 - z = x8101 - z = x8102 - z = x8103 - z = x8104 - z = x8105 - z = x8106 - z = x8107 - z = x8108 - z = x8109 - z = x8110 - z = x8111 - z = x8112 - z = x8113 - z = x8114 - z = x8115 - z = x8116 - z = x8117 - z = x8118 - z = x8119 - z = x8120 - z = x8121 - z = x8122 - z = x8123 - z = x8124 - z = x8125 - z = x8126 - z = x8127 - z = x8128 - z = x8129 - z = x8130 - z = x8131 - z = x8132 - z = x8133 - z = x8134 - z = x8135 - z = x8136 - z = x8137 - z = x8138 - z = x8139 - z = x8140 - z = x8141 - z = x8142 - z = x8143 - z = x8144 - z = x8145 - z = x8146 - z = x8147 - z = x8148 - z = x8149 - z = x8150 - z = x8151 - z = x8152 - z = x8153 - z = x8154 - z = x8155 - z = x8156 - z = x8157 - z = x8158 - z = x8159 - z = x8160 - z = x8161 - z = x8162 - z = x8163 - z = x8164 - z = x8165 - z = x8166 - z = x8167 - z = x8168 - z = x8169 - z = x8170 - z = x8171 - z = x8172 - z = x8173 - z = x8174 - z = x8175 - z = x8176 - z = x8177 - z = x8178 - z = x8179 - z = x8180 - z = x8181 - z = x8182 - z = x8183 - z = x8184 - z = x8185 - z = x8186 - z = x8187 - z = x8188 - z = x8189 - z = x8190 - z = x8191 - z = x8192 - z = x8193 - z = x8194 - z = x8195 - z = x8196 - z = x8197 - z = x8198 - z = x8199 - z = x8200 - z = x8201 - z = x8202 - z = x8203 - z = x8204 - z = x8205 - z = x8206 - z = x8207 - z = x8208 - z = x8209 - z = x8210 - z = x8211 - z = x8212 - z = x8213 - z = x8214 - z = x8215 - z = x8216 - z = x8217 - z = x8218 - z = x8219 - z = x8220 - z = x8221 - z = x8222 - z = x8223 - z = x8224 - z = x8225 - z = x8226 - z = x8227 - z = x8228 - z = x8229 - z = x8230 - z = x8231 - z = x8232 - z = x8233 - z = x8234 - z = x8235 - z = x8236 - z = x8237 - z = x8238 - z = x8239 - z = x8240 - z = x8241 - z = x8242 - z = x8243 - z = x8244 - z = x8245 - z = x8246 - z = x8247 - z = x8248 - z = x8249 - z = x8250 - z = x8251 - z = x8252 - z = x8253 - z = x8254 - z = x8255 - z = x8256 - z = x8257 - z = x8258 - z = x8259 - z = x8260 - z = x8261 - z = x8262 - z = x8263 - z = x8264 - z = x8265 - z = x8266 - z = x8267 - z = x8268 - z = x8269 - z = x8270 - z = x8271 - z = x8272 - z = x8273 - z = x8274 - z = x8275 - z = x8276 - z = x8277 - z = x8278 - z = x8279 - z = x8280 - z = x8281 - z = x8282 - z = x8283 - z = x8284 - z = x8285 - z = x8286 - z = x8287 - z = x8288 - z = x8289 - z = x8290 - z = x8291 - z = x8292 - z = x8293 - z = x8294 - z = x8295 - z = x8296 - z = x8297 - z = x8298 - z = x8299 - z = x8300 - z = x8301 - z = x8302 - z = x8303 - z = x8304 - z = x8305 - z = x8306 - z = x8307 - z = x8308 - z = x8309 - z = x8310 - z = x8311 - z = x8312 - z = x8313 - z = x8314 - z = x8315 - z = x8316 - z = x8317 - z = x8318 - z = x8319 - z = x8320 - z = x8321 - z = x8322 - z = x8323 - z = x8324 - z = x8325 - z = x8326 - z = x8327 - z = x8328 - z = x8329 - z = x8330 - z = x8331 - z = x8332 - z = x8333 - z = x8334 - z = x8335 - z = x8336 - z = x8337 - z = x8338 - z = x8339 - z = x8340 - z = x8341 - z = x8342 - z = x8343 - z = x8344 - z = x8345 - z = x8346 - z = x8347 - z = x8348 - z = x8349 - z = x8350 - z = x8351 - z = x8352 - z = x8353 - z = x8354 - z = x8355 - z = x8356 - z = x8357 - z = x8358 - z = x8359 - z = x8360 - z = x8361 - z = x8362 - z = x8363 - z = x8364 - z = x8365 - z = x8366 - z = x8367 - z = x8368 - z = x8369 - z = x8370 - z = x8371 - z = x8372 - z = x8373 - z = x8374 - z = x8375 - z = x8376 - z = x8377 - z = x8378 - z = x8379 - z = x8380 - z = x8381 - z = x8382 - z = x8383 - z = x8384 - z = x8385 - z = x8386 - z = x8387 - z = x8388 - z = x8389 - z = x8390 - z = x8391 - z = x8392 - z = x8393 - z = x8394 - z = x8395 - z = x8396 - z = x8397 - z = x8398 - z = x8399 - z = x8400 - z = x8401 - z = x8402 - z = x8403 - z = x8404 - z = x8405 - z = x8406 - z = x8407 - z = x8408 - z = x8409 - z = x8410 - z = x8411 - z = x8412 - z = x8413 - z = x8414 - z = x8415 - z = x8416 - z = x8417 - z = x8418 - z = x8419 - z = x8420 - z = x8421 - z = x8422 - z = x8423 - z = x8424 - z = x8425 - z = x8426 - z = x8427 - z = x8428 - z = x8429 - z = x8430 - z = x8431 - z = x8432 - z = x8433 - z = x8434 - z = x8435 - z = x8436 - z = x8437 - z = x8438 - z = x8439 - z = x8440 - z = x8441 - z = x8442 - z = x8443 - z = x8444 - z = x8445 - z = x8446 - z = x8447 - z = x8448 - z = x8449 - z = x8450 - z = x8451 - z = x8452 - z = x8453 - z = x8454 - z = x8455 - z = x8456 - z = x8457 - z = x8458 - z = x8459 - z = x8460 - z = x8461 - z = x8462 - z = x8463 - z = x8464 - z = x8465 - z = x8466 - z = x8467 - z = x8468 - z = x8469 - z = x8470 - z = x8471 - z = x8472 - z = x8473 - z = x8474 - z = x8475 - z = x8476 - z = x8477 - z = x8478 - z = x8479 - z = x8480 - z = x8481 - z = x8482 - z = x8483 - z = x8484 - z = x8485 - z = x8486 - z = x8487 - z = x8488 - z = x8489 - z = x8490 - z = x8491 - z = x8492 - z = x8493 - z = x8494 - z = x8495 - z = x8496 - z = x8497 - z = x8498 - z = x8499 - z = x8500 - z = x8501 - z = x8502 - z = x8503 - z = x8504 - z = x8505 - z = x8506 - z = x8507 - z = x8508 - z = x8509 - z = x8510 - z = x8511 - z = x8512 - z = x8513 - z = x8514 - z = x8515 - z = x8516 - z = x8517 - z = x8518 - z = x8519 - z = x8520 - z = x8521 - z = x8522 - z = x8523 - z = x8524 - z = x8525 - z = x8526 - z = x8527 - z = x8528 - z = x8529 - z = x8530 - z = x8531 - z = x8532 - z = x8533 - z = x8534 - z = x8535 - z = x8536 - z = x8537 - z = x8538 - z = x8539 - z = x8540 - z = x8541 - z = x8542 - z = x8543 - z = x8544 - z = x8545 - z = x8546 - z = x8547 - z = x8548 - z = x8549 - z = x8550 - z = x8551 - z = x8552 - z = x8553 - z = x8554 - z = x8555 - z = x8556 - z = x8557 - z = x8558 - z = x8559 - z = x8560 - z = x8561 - z = x8562 - z = x8563 - z = x8564 - z = x8565 - z = x8566 - z = x8567 - z = x8568 - z = x8569 - z = x8570 - z = x8571 - z = x8572 - z = x8573 - z = x8574 - z = x8575 - z = x8576 - z = x8577 - z = x8578 - z = x8579 - z = x8580 - z = x8581 - z = x8582 - z = x8583 - z = x8584 - z = x8585 - z = x8586 - z = x8587 - z = x8588 - z = x8589 - z = x8590 - z = x8591 - z = x8592 - z = x8593 - z = x8594 - z = x8595 - z = x8596 - z = x8597 - z = x8598 - z = x8599 - z = x8600 - z = x8601 - z = x8602 - z = x8603 - z = x8604 - z = x8605 - z = x8606 - z = x8607 - z = x8608 - z = x8609 - z = x8610 - z = x8611 - z = x8612 - z = x8613 - z = x8614 - z = x8615 - z = x8616 - z = x8617 - z = x8618 - z = x8619 - z = x8620 - z = x8621 - z = x8622 - z = x8623 - z = x8624 - z = x8625 - z = x8626 - z = x8627 - z = x8628 - z = x8629 - z = x8630 - z = x8631 - z = x8632 - z = x8633 - z = x8634 - z = x8635 - z = x8636 - z = x8637 - z = x8638 - z = x8639 - z = x8640 - z = x8641 - z = x8642 - z = x8643 - z = x8644 - z = x8645 - z = x8646 - z = x8647 - z = x8648 - z = x8649 - z = x8650 - z = x8651 - z = x8652 - z = x8653 - z = x8654 - z = x8655 - z = x8656 - z = x8657 - z = x8658 - z = x8659 - z = x8660 - z = x8661 - z = x8662 - z = x8663 - z = x8664 - z = x8665 - z = x8666 - z = x8667 - z = x8668 - z = x8669 - z = x8670 - z = x8671 - z = x8672 - z = x8673 - z = x8674 - z = x8675 - z = x8676 - z = x8677 - z = x8678 - z = x8679 - z = x8680 - z = x8681 - z = x8682 - z = x8683 - z = x8684 - z = x8685 - z = x8686 - z = x8687 - z = x8688 - z = x8689 - z = x8690 - z = x8691 - z = x8692 - z = x8693 - z = x8694 - z = x8695 - z = x8696 - z = x8697 - z = x8698 - z = x8699 - z = x8700 - z = x8701 - z = x8702 - z = x8703 - z = x8704 - z = x8705 - z = x8706 - z = x8707 - z = x8708 - z = x8709 - z = x8710 - z = x8711 - z = x8712 - z = x8713 - z = x8714 - z = x8715 - z = x8716 - z = x8717 - z = x8718 - z = x8719 - z = x8720 - z = x8721 - z = x8722 - z = x8723 - z = x8724 - z = x8725 - z = x8726 - z = x8727 - z = x8728 - z = x8729 - z = x8730 - z = x8731 - z = x8732 - z = x8733 - z = x8734 - z = x8735 - z = x8736 - z = x8737 - z = x8738 - z = x8739 - z = x8740 - z = x8741 - z = x8742 - z = x8743 - z = x8744 - z = x8745 - z = x8746 - z = x8747 - z = x8748 - z = x8749 - z = x8750 - z = x8751 - z = x8752 - z = x8753 - z = x8754 - z = x8755 - z = x8756 - z = x8757 - z = x8758 - z = x8759 - z = x8760 - z = x8761 - z = x8762 - z = x8763 - z = x8764 - z = x8765 - z = x8766 - z = x8767 - z = x8768 - z = x8769 - z = x8770 - z = x8771 - z = x8772 - z = x8773 - z = x8774 - z = x8775 - z = x8776 - z = x8777 - z = x8778 - z = x8779 - z = x8780 - z = x8781 - z = x8782 - z = x8783 - z = x8784 - z = x8785 - z = x8786 - z = x8787 - z = x8788 - z = x8789 - z = x8790 - z = x8791 - z = x8792 - z = x8793 - z = x8794 - z = x8795 - z = x8796 - z = x8797 - z = x8798 - z = x8799 - z = x8800 - z = x8801 - z = x8802 - z = x8803 - z = x8804 - z = x8805 - z = x8806 - z = x8807 - z = x8808 - z = x8809 - z = x8810 - z = x8811 - z = x8812 - z = x8813 - z = x8814 - z = x8815 - z = x8816 - z = x8817 - z = x8818 - z = x8819 - z = x8820 - z = x8821 - z = x8822 - z = x8823 - z = x8824 - z = x8825 - z = x8826 - z = x8827 - z = x8828 - z = x8829 - z = x8830 - z = x8831 - z = x8832 - z = x8833 - z = x8834 - z = x8835 - z = x8836 - z = x8837 - z = x8838 - z = x8839 - z = x8840 - z = x8841 - z = x8842 - z = x8843 - z = x8844 - z = x8845 - z = x8846 - z = x8847 - z = x8848 - z = x8849 - z = x8850 - z = x8851 - z = x8852 - z = x8853 - z = x8854 - z = x8855 - z = x8856 - z = x8857 - z = x8858 - z = x8859 - z = x8860 - z = x8861 - z = x8862 - z = x8863 - z = x8864 - z = x8865 - z = x8866 - z = x8867 - z = x8868 - z = x8869 - z = x8870 - z = x8871 - z = x8872 - z = x8873 - z = x8874 - z = x8875 - z = x8876 - z = x8877 - z = x8878 - z = x8879 - z = x8880 - z = x8881 - z = x8882 - z = x8883 - z = x8884 - z = x8885 - z = x8886 - z = x8887 - z = x8888 - z = x8889 - z = x8890 - z = x8891 - z = x8892 - z = x8893 - z = x8894 - z = x8895 - z = x8896 - z = x8897 - z = x8898 - z = x8899 - z = x8900 - z = x8901 - z = x8902 - z = x8903 - z = x8904 - z = x8905 - z = x8906 - z = x8907 - z = x8908 - z = x8909 - z = x8910 - z = x8911 - z = x8912 - z = x8913 - z = x8914 - z = x8915 - z = x8916 - z = x8917 - z = x8918 - z = x8919 - z = x8920 - z = x8921 - z = x8922 - z = x8923 - z = x8924 - z = x8925 - z = x8926 - z = x8927 - z = x8928 - z = x8929 - z = x8930 - z = x8931 - z = x8932 - z = x8933 - z = x8934 - z = x8935 - z = x8936 - z = x8937 - z = x8938 - z = x8939 - z = x8940 - z = x8941 - z = x8942 - z = x8943 - z = x8944 - z = x8945 - z = x8946 - z = x8947 - z = x8948 - z = x8949 - z = x8950 - z = x8951 - z = x8952 - z = x8953 - z = x8954 - z = x8955 - z = x8956 - z = x8957 - z = x8958 - z = x8959 - z = x8960 - z = x8961 - z = x8962 - z = x8963 - z = x8964 - z = x8965 - z = x8966 - z = x8967 - z = x8968 - z = x8969 - z = x8970 - z = x8971 - z = x8972 - z = x8973 - z = x8974 - z = x8975 - z = x8976 - z = x8977 - z = x8978 - z = x8979 - z = x8980 - z = x8981 - z = x8982 - z = x8983 - z = x8984 - z = x8985 - z = x8986 - z = x8987 - z = x8988 - z = x8989 - z = x8990 - z = x8991 - z = x8992 - z = x8993 - z = x8994 - z = x8995 - z = x8996 - z = x8997 - z = x8998 - z = x8999 - z = x9000 - z = x9001 - z = x9002 - z = x9003 - z = x9004 - z = x9005 - z = x9006 - z = x9007 - z = x9008 - z = x9009 - z = x9010 - z = x9011 - z = x9012 - z = x9013 - z = x9014 - z = x9015 - z = x9016 - z = x9017 - z = x9018 - z = x9019 - z = x9020 - z = x9021 - z = x9022 - z = x9023 - z = x9024 - z = x9025 - z = x9026 - z = x9027 - z = x9028 - z = x9029 - z = x9030 - z = x9031 - z = x9032 - z = x9033 - z = x9034 - z = x9035 - z = x9036 - z = x9037 - z = x9038 - z = x9039 - z = x9040 - z = x9041 - z = x9042 - z = x9043 - z = x9044 - z = x9045 - z = x9046 - z = x9047 - z = x9048 - z = x9049 - z = x9050 - z = x9051 - z = x9052 - z = x9053 - z = x9054 - z = x9055 - z = x9056 - z = x9057 - z = x9058 - z = x9059 - z = x9060 - z = x9061 - z = x9062 - z = x9063 - z = x9064 - z = x9065 - z = x9066 - z = x9067 - z = x9068 - z = x9069 - z = x9070 - z = x9071 - z = x9072 - z = x9073 - z = x9074 - z = x9075 - z = x9076 - z = x9077 - z = x9078 - z = x9079 - z = x9080 - z = x9081 - z = x9082 - z = x9083 - z = x9084 - z = x9085 - z = x9086 - z = x9087 - z = x9088 - z = x9089 - z = x9090 - z = x9091 - z = x9092 - z = x9093 - z = x9094 - z = x9095 - z = x9096 - z = x9097 - z = x9098 - z = x9099 - z = x9100 - z = x9101 - z = x9102 - z = x9103 - z = x9104 - z = x9105 - z = x9106 - z = x9107 - z = x9108 - z = x9109 - z = x9110 - z = x9111 - z = x9112 - z = x9113 - z = x9114 - z = x9115 - z = x9116 - z = x9117 - z = x9118 - z = x9119 - z = x9120 - z = x9121 - z = x9122 - z = x9123 - z = x9124 - z = x9125 - z = x9126 - z = x9127 - z = x9128 - z = x9129 - z = x9130 - z = x9131 - z = x9132 - z = x9133 - z = x9134 - z = x9135 - z = x9136 - z = x9137 - z = x9138 - z = x9139 - z = x9140 - z = x9141 - z = x9142 - z = x9143 - z = x9144 - z = x9145 - z = x9146 - z = x9147 - z = x9148 - z = x9149 - z = x9150 - z = x9151 - z = x9152 - z = x9153 - z = x9154 - z = x9155 - z = x9156 - z = x9157 - z = x9158 - z = x9159 - z = x9160 - z = x9161 - z = x9162 - z = x9163 - z = x9164 - z = x9165 - z = x9166 - z = x9167 - z = x9168 - z = x9169 - z = x9170 - z = x9171 - z = x9172 - z = x9173 - z = x9174 - z = x9175 - z = x9176 - z = x9177 - z = x9178 - z = x9179 - z = x9180 - z = x9181 - z = x9182 - z = x9183 - z = x9184 - z = x9185 - z = x9186 - z = x9187 - z = x9188 - z = x9189 - z = x9190 - z = x9191 - z = x9192 - z = x9193 - z = x9194 - z = x9195 - z = x9196 - z = x9197 - z = x9198 - z = x9199 - z = x9200 - z = x9201 - z = x9202 - z = x9203 - z = x9204 - z = x9205 - z = x9206 - z = x9207 - z = x9208 - z = x9209 - z = x9210 - z = x9211 - z = x9212 - z = x9213 - z = x9214 - z = x9215 - z = x9216 - z = x9217 - z = x9218 - z = x9219 - z = x9220 - z = x9221 - z = x9222 - z = x9223 - z = x9224 - z = x9225 - z = x9226 - z = x9227 - z = x9228 - z = x9229 - z = x9230 - z = x9231 - z = x9232 - z = x9233 - z = x9234 - z = x9235 - z = x9236 - z = x9237 - z = x9238 - z = x9239 - z = x9240 - z = x9241 - z = x9242 - z = x9243 - z = x9244 - z = x9245 - z = x9246 - z = x9247 - z = x9248 - z = x9249 - z = x9250 - z = x9251 - z = x9252 - z = x9253 - z = x9254 - z = x9255 - z = x9256 - z = x9257 - z = x9258 - z = x9259 - z = x9260 - z = x9261 - z = x9262 - z = x9263 - z = x9264 - z = x9265 - z = x9266 - z = x9267 - z = x9268 - z = x9269 - z = x9270 - z = x9271 - z = x9272 - z = x9273 - z = x9274 - z = x9275 - z = x9276 - z = x9277 - z = x9278 - z = x9279 - z = x9280 - z = x9281 - z = x9282 - z = x9283 - z = x9284 - z = x9285 - z = x9286 - z = x9287 - z = x9288 - z = x9289 - z = x9290 - z = x9291 - z = x9292 - z = x9293 - z = x9294 - z = x9295 - z = x9296 - z = x9297 - z = x9298 - z = x9299 - z = x9300 - z = x9301 - z = x9302 - z = x9303 - z = x9304 - z = x9305 - z = x9306 - z = x9307 - z = x9308 - z = x9309 - z = x9310 - z = x9311 - z = x9312 - z = x9313 - z = x9314 - z = x9315 - z = x9316 - z = x9317 - z = x9318 - z = x9319 - z = x9320 - z = x9321 - z = x9322 - z = x9323 - z = x9324 - z = x9325 - z = x9326 - z = x9327 - z = x9328 - z = x9329 - z = x9330 - z = x9331 - z = x9332 - z = x9333 - z = x9334 - z = x9335 - z = x9336 - z = x9337 - z = x9338 - z = x9339 - z = x9340 - z = x9341 - z = x9342 - z = x9343 - z = x9344 - z = x9345 - z = x9346 - z = x9347 - z = x9348 - z = x9349 - z = x9350 - z = x9351 - z = x9352 - z = x9353 - z = x9354 - z = x9355 - z = x9356 - z = x9357 - z = x9358 - z = x9359 - z = x9360 - z = x9361 - z = x9362 - z = x9363 - z = x9364 - z = x9365 - z = x9366 - z = x9367 - z = x9368 - z = x9369 - z = x9370 - z = x9371 - z = x9372 - z = x9373 - z = x9374 - z = x9375 - z = x9376 - z = x9377 - z = x9378 - z = x9379 - z = x9380 - z = x9381 - z = x9382 - z = x9383 - z = x9384 - z = x9385 - z = x9386 - z = x9387 - z = x9388 - z = x9389 - z = x9390 - z = x9391 - z = x9392 - z = x9393 - z = x9394 - z = x9395 - z = x9396 - z = x9397 - z = x9398 - z = x9399 - z = x9400 - z = x9401 - z = x9402 - z = x9403 - z = x9404 - z = x9405 - z = x9406 - z = x9407 - z = x9408 - z = x9409 - z = x9410 - z = x9411 - z = x9412 - z = x9413 - z = x9414 - z = x9415 - z = x9416 - z = x9417 - z = x9418 - z = x9419 - z = x9420 - z = x9421 - z = x9422 - z = x9423 - z = x9424 - z = x9425 - z = x9426 - z = x9427 - z = x9428 - z = x9429 - z = x9430 - z = x9431 - z = x9432 - z = x9433 - z = x9434 - z = x9435 - z = x9436 - z = x9437 - z = x9438 - z = x9439 - z = x9440 - z = x9441 - z = x9442 - z = x9443 - z = x9444 - z = x9445 - z = x9446 - z = x9447 - z = x9448 - z = x9449 - z = x9450 - z = x9451 - z = x9452 - z = x9453 - z = x9454 - z = x9455 - z = x9456 - z = x9457 - z = x9458 - z = x9459 - z = x9460 - z = x9461 - z = x9462 - z = x9463 - z = x9464 - z = x9465 - z = x9466 - z = x9467 - z = x9468 - z = x9469 - z = x9470 - z = x9471 - z = x9472 - z = x9473 - z = x9474 - z = x9475 - z = x9476 - z = x9477 - z = x9478 - z = x9479 - z = x9480 - z = x9481 - z = x9482 - z = x9483 - z = x9484 - z = x9485 - z = x9486 - z = x9487 - z = x9488 - z = x9489 - z = x9490 - z = x9491 - z = x9492 - z = x9493 - z = x9494 - z = x9495 - z = x9496 - z = x9497 - z = x9498 - z = x9499 - z = x9500 - z = x9501 - z = x9502 - z = x9503 - z = x9504 - z = x9505 - z = x9506 - z = x9507 - z = x9508 - z = x9509 - z = x9510 - z = x9511 - z = x9512 - z = x9513 - z = x9514 - z = x9515 - z = x9516 - z = x9517 - z = x9518 - z = x9519 - z = x9520 - z = x9521 - z = x9522 - z = x9523 - z = x9524 - z = x9525 - z = x9526 - z = x9527 - z = x9528 - z = x9529 - z = x9530 - z = x9531 - z = x9532 - z = x9533 - z = x9534 - z = x9535 - z = x9536 - z = x9537 - z = x9538 - z = x9539 - z = x9540 - z = x9541 - z = x9542 - z = x9543 - z = x9544 - z = x9545 - z = x9546 - z = x9547 - z = x9548 - z = x9549 - z = x9550 - z = x9551 - z = x9552 - z = x9553 - z = x9554 - z = x9555 - z = x9556 - z = x9557 - z = x9558 - z = x9559 - z = x9560 - z = x9561 - z = x9562 - z = x9563 - z = x9564 - z = x9565 - z = x9566 - z = x9567 - z = x9568 - z = x9569 - z = x9570 - z = x9571 - z = x9572 - z = x9573 - z = x9574 - z = x9575 - z = x9576 - z = x9577 - z = x9578 - z = x9579 - z = x9580 - z = x9581 - z = x9582 - z = x9583 - z = x9584 - z = x9585 - z = x9586 - z = x9587 - z = x9588 - z = x9589 - z = x9590 - z = x9591 - z = x9592 - z = x9593 - z = x9594 - z = x9595 - z = x9596 - z = x9597 - z = x9598 - z = x9599 - z = x9600 - z = x9601 - z = x9602 - z = x9603 - z = x9604 - z = x9605 - z = x9606 - z = x9607 - z = x9608 - z = x9609 - z = x9610 - z = x9611 - z = x9612 - z = x9613 - z = x9614 - z = x9615 - z = x9616 - z = x9617 - z = x9618 - z = x9619 - z = x9620 - z = x9621 - z = x9622 - z = x9623 - z = x9624 - z = x9625 - z = x9626 - z = x9627 - z = x9628 - z = x9629 - z = x9630 - z = x9631 - z = x9632 - z = x9633 - z = x9634 - z = x9635 - z = x9636 - z = x9637 - z = x9638 - z = x9639 - z = x9640 - z = x9641 - z = x9642 - z = x9643 - z = x9644 - z = x9645 - z = x9646 - z = x9647 - z = x9648 - z = x9649 - z = x9650 - z = x9651 - z = x9652 - z = x9653 - z = x9654 - z = x9655 - z = x9656 - z = x9657 - z = x9658 - z = x9659 - z = x9660 - z = x9661 - z = x9662 - z = x9663 - z = x9664 - z = x9665 - z = x9666 - z = x9667 - z = x9668 - z = x9669 - z = x9670 - z = x9671 - z = x9672 - z = x9673 - z = x9674 - z = x9675 - z = x9676 - z = x9677 - z = x9678 - z = x9679 - z = x9680 - z = x9681 - z = x9682 - z = x9683 - z = x9684 - z = x9685 - z = x9686 - z = x9687 - z = x9688 - z = x9689 - z = x9690 - z = x9691 - z = x9692 - z = x9693 - z = x9694 - z = x9695 - z = x9696 - z = x9697 - z = x9698 - z = x9699 - z = x9700 - z = x9701 - z = x9702 - z = x9703 - z = x9704 - z = x9705 - z = x9706 - z = x9707 - z = x9708 - z = x9709 - z = x9710 - z = x9711 - z = x9712 - z = x9713 - z = x9714 - z = x9715 - z = x9716 - z = x9717 - z = x9718 - z = x9719 - z = x9720 - z = x9721 - z = x9722 - z = x9723 - z = x9724 - z = x9725 - z = x9726 - z = x9727 - z = x9728 - z = x9729 - z = x9730 - z = x9731 - z = x9732 - z = x9733 - z = x9734 - z = x9735 - z = x9736 - z = x9737 - z = x9738 - z = x9739 - z = x9740 - z = x9741 - z = x9742 - z = x9743 - z = x9744 - z = x9745 - z = x9746 - z = x9747 - z = x9748 - z = x9749 - z = x9750 - z = x9751 - z = x9752 - z = x9753 - z = x9754 - z = x9755 - z = x9756 - z = x9757 - z = x9758 - z = x9759 - z = x9760 - z = x9761 - z = x9762 - z = x9763 - z = x9764 - z = x9765 - z = x9766 - z = x9767 - z = x9768 - z = x9769 - z = x9770 - z = x9771 - z = x9772 - z = x9773 - z = x9774 - z = x9775 - z = x9776 - z = x9777 - z = x9778 - z = x9779 - z = x9780 - z = x9781 - z = x9782 - z = x9783 - z = x9784 - z = x9785 - z = x9786 - z = x9787 - z = x9788 - z = x9789 - z = x9790 - z = x9791 - z = x9792 - z = x9793 - z = x9794 - z = x9795 - z = x9796 - z = x9797 - z = x9798 - z = x9799 - z = x9800 - z = x9801 - z = x9802 - z = x9803 - z = x9804 - z = x9805 - z = x9806 - z = x9807 - z = x9808 - z = x9809 - z = x9810 - z = x9811 - z = x9812 - z = x9813 - z = x9814 - z = x9815 - z = x9816 - z = x9817 - z = x9818 - z = x9819 - z = x9820 - z = x9821 - z = x9822 - z = x9823 - z = x9824 - z = x9825 - z = x9826 - z = x9827 - z = x9828 - z = x9829 - z = x9830 - z = x9831 - z = x9832 - z = x9833 - z = x9834 - z = x9835 - z = x9836 - z = x9837 - z = x9838 - z = x9839 - z = x9840 - z = x9841 - z = x9842 - z = x9843 - z = x9844 - z = x9845 - z = x9846 - z = x9847 - z = x9848 - z = x9849 - z = x9850 - z = x9851 - z = x9852 - z = x9853 - z = x9854 - z = x9855 - z = x9856 - z = x9857 - z = x9858 - z = x9859 - z = x9860 - z = x9861 - z = x9862 - z = x9863 - z = x9864 - z = x9865 - z = x9866 - z = x9867 - z = x9868 - z = x9869 - z = x9870 - z = x9871 - z = x9872 - z = x9873 - z = x9874 - z = x9875 - z = x9876 - z = x9877 - z = x9878 - z = x9879 - z = x9880 - z = x9881 - z = x9882 - z = x9883 - z = x9884 - z = x9885 - z = x9886 - z = x9887 - z = x9888 - z = x9889 - z = x9890 - z = x9891 - z = x9892 - z = x9893 - z = x9894 - z = x9895 - z = x9896 - z = x9897 - z = x9898 - z = x9899 - z = x9900 - z = x9901 - z = x9902 - z = x9903 - z = x9904 - z = x9905 - z = x9906 - z = x9907 - z = x9908 - z = x9909 - z = x9910 - z = x9911 - z = x9912 - z = x9913 - z = x9914 - z = x9915 - z = x9916 - z = x9917 - z = x9918 - z = x9919 - z = x9920 - z = x9921 - z = x9922 - z = x9923 - z = x9924 - z = x9925 - z = x9926 - z = x9927 - z = x9928 - z = x9929 - z = x9930 - z = x9931 - z = x9932 - z = x9933 - z = x9934 - z = x9935 - z = x9936 - z = x9937 - z = x9938 - z = x9939 - z = x9940 - z = x9941 - z = x9942 - z = x9943 - z = x9944 - z = x9945 - z = x9946 - z = x9947 - z = x9948 - z = x9949 - z = x9950 - z = x9951 - z = x9952 - z = x9953 - z = x9954 - z = x9955 - z = x9956 - z = x9957 - z = x9958 - z = x9959 - z = x9960 - z = x9961 - z = x9962 - z = x9963 - z = x9964 - z = x9965 - z = x9966 - z = x9967 - z = x9968 - z = x9969 - z = x9970 - z = x9971 - z = x9972 - z = x9973 - z = x9974 - z = x9975 - z = x9976 - z = x9977 - z = x9978 - z = x9979 - z = x9980 - z = x9981 - z = x9982 - z = x9983 - z = x9984 - z = x9985 - z = x9986 - z = x9987 - z = x9988 - z = x9989 - z = x9990 - z = x9991 - z = x9992 - z = x9993 - z = x9994 - z = x9995 - z = x9996 - z = x9997 - z = x9998 - z = x9999 - z = x10000 - z = x10001 - z = x10002 - z = x10003 - z = x10004 - z = x10005 - z = x10006 - z = x10007 - z = x10008 - z = x10009 - z = x10010 - z = x10011 - z = x10012 - z = x10013 - z = x10014 - z = x10015 - z = x10016 - z = x10017 - z = x10018 - z = x10019 - z = x10020 - z = x10021 - z = x10022 - z = x10023 - z = x10024 - z = x10025 - z = x10026 - z = x10027 - z = x10028 - z = x10029 - z = x10030 - z = x10031 - z = x10032 - z = x10033 - z = x10034 - z = x10035 - z = x10036 - z = x10037 - z = x10038 - z = x10039 - z = x10040 - z = x10041 - z = x10042 - z = x10043 - z = x10044 - z = x10045 - z = x10046 - z = x10047 - z = x10048 - z = x10049 - z = x10050 - z = x10051 - z = x10052 - z = x10053 - z = x10054 - z = x10055 - z = x10056 - z = x10057 - z = x10058 - z = x10059 - z = x10060 - z = x10061 - z = x10062 - z = x10063 - z = x10064 - z = x10065 - z = x10066 - z = x10067 - z = x10068 - z = x10069 - z = x10070 - z = x10071 - z = x10072 - z = x10073 - z = x10074 - z = x10075 - z = x10076 - z = x10077 - z = x10078 - z = x10079 - z = x10080 - z = x10081 - z = x10082 - z = x10083 - z = x10084 - z = x10085 - z = x10086 - z = x10087 - z = x10088 - z = x10089 - z = x10090 - z = x10091 - z = x10092 - z = x10093 - z = x10094 - z = x10095 - z = x10096 - z = x10097 - z = x10098 - z = x10099 - z = x10100 - z = x10101 - z = x10102 - z = x10103 - z = x10104 - z = x10105 - z = x10106 - z = x10107 - z = x10108 - z = x10109 - z = x10110 - z = x10111 - z = x10112 - z = x10113 - z = x10114 - z = x10115 - z = x10116 - z = x10117 - z = x10118 - z = x10119 - z = x10120 - z = x10121 - z = x10122 - z = x10123 - z = x10124 - z = x10125 - z = x10126 - z = x10127 - z = x10128 - z = x10129 - z = x10130 - z = x10131 - z = x10132 - z = x10133 - z = x10134 - z = x10135 - z = x10136 - z = x10137 - z = x10138 - z = x10139 - z = x10140 - z = x10141 - z = x10142 - z = x10143 - z = x10144 - z = x10145 - z = x10146 - z = x10147 - z = x10148 - z = x10149 - z = x10150 - z = x10151 - z = x10152 - z = x10153 - z = x10154 - z = x10155 - z = x10156 - z = x10157 - z = x10158 - z = x10159 - z = x10160 - z = x10161 - z = x10162 - z = x10163 - z = x10164 - z = x10165 - z = x10166 - z = x10167 - z = x10168 - z = x10169 - z = x10170 - z = x10171 - z = x10172 - z = x10173 - z = x10174 - z = x10175 - z = x10176 - z = x10177 - z = x10178 - z = x10179 - z = x10180 - z = x10181 - z = x10182 - z = x10183 - z = x10184 - z = x10185 - z = x10186 - z = x10187 - z = x10188 - z = x10189 - z = x10190 - z = x10191 - z = x10192 - z = x10193 - z = x10194 - z = x10195 - z = x10196 - z = x10197 - z = x10198 - z = x10199 - z = x10200 - z = x10201 - z = x10202 - z = x10203 - z = x10204 - z = x10205 - z = x10206 - z = x10207 - z = x10208 - z = x10209 - z = x10210 - z = x10211 - z = x10212 - z = x10213 - z = x10214 - z = x10215 - z = x10216 - z = x10217 - z = x10218 - z = x10219 - z = x10220 - z = x10221 - z = x10222 - z = x10223 - z = x10224 - z = x10225 - z = x10226 - z = x10227 - z = x10228 - z = x10229 - z = x10230 - z = x10231 - z = x10232 - z = x10233 - z = x10234 - z = x10235 - z = x10236 - z = x10237 - z = x10238 - z = x10239 - z = x10240 - z = x10241 - z = x10242 - z = x10243 - z = x10244 - z = x10245 - z = x10246 - z = x10247 - z = x10248 - z = x10249 - z = x10250 - z = x10251 - z = x10252 - z = x10253 - z = x10254 - z = x10255 - z = x10256 - z = x10257 - z = x10258 - z = x10259 - z = x10260 - z = x10261 - z = x10262 - z = x10263 - z = x10264 - z = x10265 - z = x10266 - z = x10267 - z = x10268 - z = x10269 - z = x10270 - z = x10271 - z = x10272 - z = x10273 - z = x10274 - z = x10275 - z = x10276 - z = x10277 - z = x10278 - z = x10279 - z = x10280 - z = x10281 - z = x10282 - z = x10283 - z = x10284 - z = x10285 - z = x10286 - z = x10287 - z = x10288 - z = x10289 - z = x10290 - z = x10291 - z = x10292 - z = x10293 - z = x10294 - z = x10295 - z = x10296 - z = x10297 - z = x10298 - z = x10299 - z = x10300 - z = x10301 - z = x10302 - z = x10303 - z = x10304 - z = x10305 - z = x10306 - z = x10307 - z = x10308 - z = x10309 - z = x10310 - z = x10311 - z = x10312 - z = x10313 - z = x10314 - z = x10315 - z = x10316 - z = x10317 - z = x10318 - z = x10319 - z = x10320 - z = x10321 - z = x10322 - z = x10323 - z = x10324 - z = x10325 - z = x10326 - z = x10327 - z = x10328 - z = x10329 - z = x10330 - z = x10331 - z = x10332 - z = x10333 - z = x10334 - z = x10335 - z = x10336 - z = x10337 - z = x10338 - z = x10339 - z = x10340 - z = x10341 - z = x10342 - z = x10343 - z = x10344 - z = x10345 - z = x10346 - z = x10347 - z = x10348 - z = x10349 - z = x10350 - z = x10351 - z = x10352 - z = x10353 - z = x10354 - z = x10355 - z = x10356 - z = x10357 - z = x10358 - z = x10359 - z = x10360 - z = x10361 - z = x10362 - z = x10363 - z = x10364 - z = x10365 - z = x10366 - z = x10367 - z = x10368 - z = x10369 - z = x10370 - z = x10371 - z = x10372 - z = x10373 - z = x10374 - z = x10375 - z = x10376 - z = x10377 - z = x10378 - z = x10379 - z = x10380 - z = x10381 - z = x10382 - z = x10383 - z = x10384 - z = x10385 - z = x10386 - z = x10387 - z = x10388 - z = x10389 - z = x10390 - z = x10391 - z = x10392 - z = x10393 - z = x10394 - z = x10395 - z = x10396 - z = x10397 - z = x10398 - z = x10399 - z = x10400 - z = x10401 - z = x10402 - z = x10403 - z = x10404 - z = x10405 - z = x10406 - z = x10407 - z = x10408 - z = x10409 - z = x10410 - z = x10411 - z = x10412 - z = x10413 - z = x10414 - z = x10415 - z = x10416 - z = x10417 - z = x10418 - z = x10419 - z = x10420 - z = x10421 - z = x10422 - z = x10423 - z = x10424 - z = x10425 - z = x10426 - z = x10427 - z = x10428 - z = x10429 - z = x10430 - z = x10431 - z = x10432 - z = x10433 - z = x10434 - z = x10435 - z = x10436 - z = x10437 - z = x10438 - z = x10439 - z = x10440 - z = x10441 - z = x10442 - z = x10443 - z = x10444 - z = x10445 - z = x10446 - z = x10447 - z = x10448 - z = x10449 - z = x10450 - z = x10451 - z = x10452 - z = x10453 - z = x10454 - z = x10455 - z = x10456 - z = x10457 - z = x10458 - z = x10459 - z = x10460 - z = x10461 - z = x10462 - z = x10463 - z = x10464 - z = x10465 - z = x10466 - z = x10467 - z = x10468 - z = x10469 - z = x10470 - z = x10471 - z = x10472 - z = x10473 - z = x10474 - z = x10475 - z = x10476 - z = x10477 - z = x10478 - z = x10479 - z = x10480 - z = x10481 - z = x10482 - z = x10483 - z = x10484 - z = x10485 - z = x10486 - z = x10487 - z = x10488 - z = x10489 - z = x10490 - z = x10491 - z = x10492 - z = x10493 - z = x10494 - z = x10495 - z = x10496 - z = x10497 - z = x10498 - z = x10499 - z = x10500 - z = x10501 - z = x10502 - z = x10503 - z = x10504 - z = x10505 - z = x10506 - z = x10507 - z = x10508 - z = x10509 - z = x10510 - z = x10511 - z = x10512 - z = x10513 - z = x10514 - z = x10515 - z = x10516 - z = x10517 - z = x10518 - z = x10519 - z = x10520 - z = x10521 - z = x10522 - z = x10523 - z = x10524 - z = x10525 - z = x10526 - z = x10527 - z = x10528 - z = x10529 - z = x10530 - z = x10531 - z = x10532 - z = x10533 - z = x10534 - z = x10535 - z = x10536 - z = x10537 - z = x10538 - z = x10539 - z = x10540 - z = x10541 - z = x10542 - z = x10543 - z = x10544 - z = x10545 - z = x10546 - z = x10547 - z = x10548 - z = x10549 - z = x10550 - z = x10551 - z = x10552 - z = x10553 - z = x10554 - z = x10555 - z = x10556 - z = x10557 - z = x10558 - z = x10559 - z = x10560 - z = x10561 - z = x10562 - z = x10563 - z = x10564 - z = x10565 - z = x10566 - z = x10567 - z = x10568 - z = x10569 - z = x10570 - z = x10571 - z = x10572 - z = x10573 - z = x10574 - z = x10575 - z = x10576 - z = x10577 - z = x10578 - z = x10579 - z = x10580 - z = x10581 - z = x10582 - z = x10583 - z = x10584 - z = x10585 - z = x10586 - z = x10587 - z = x10588 - z = x10589 - z = x10590 - z = x10591 - z = x10592 - z = x10593 - z = x10594 - z = x10595 - z = x10596 - z = x10597 - z = x10598 - z = x10599 - z = x10600 - z = x10601 - z = x10602 - z = x10603 - z = x10604 - z = x10605 - z = x10606 - z = x10607 - z = x10608 - z = x10609 - z = x10610 - z = x10611 - z = x10612 - z = x10613 - z = x10614 - z = x10615 - z = x10616 - z = x10617 - z = x10618 - z = x10619 - z = x10620 - z = x10621 - z = x10622 - z = x10623 - z = x10624 - z = x10625 - z = x10626 - z = x10627 - z = x10628 - z = x10629 - z = x10630 - z = x10631 - z = x10632 - z = x10633 - z = x10634 - z = x10635 - z = x10636 - z = x10637 - z = x10638 - z = x10639 - z = x10640 - z = x10641 - z = x10642 - z = x10643 - z = x10644 - z = x10645 - z = x10646 - z = x10647 - z = x10648 - z = x10649 - z = x10650 - z = x10651 - z = x10652 - z = x10653 - z = x10654 - z = x10655 - z = x10656 - z = x10657 - z = x10658 - z = x10659 - z = x10660 - z = x10661 - z = x10662 - z = x10663 - z = x10664 - z = x10665 - z = x10666 - z = x10667 - z = x10668 - z = x10669 - z = x10670 - z = x10671 - z = x10672 - z = x10673 - z = x10674 - z = x10675 - z = x10676 - z = x10677 - z = x10678 - z = x10679 - z = x10680 - z = x10681 - z = x10682 - z = x10683 - z = x10684 - z = x10685 - z = x10686 - z = x10687 - z = x10688 - z = x10689 - z = x10690 - z = x10691 - z = x10692 - z = x10693 - z = x10694 - z = x10695 - z = x10696 - z = x10697 - z = x10698 - z = x10699 - z = x10700 - z = x10701 - z = x10702 - z = x10703 - z = x10704 - z = x10705 - z = x10706 - z = x10707 - z = x10708 - z = x10709 - z = x10710 - z = x10711 - z = x10712 - z = x10713 - z = x10714 - z = x10715 - z = x10716 - z = x10717 - z = x10718 - z = x10719 - z = x10720 - z = x10721 - z = x10722 - z = x10723 - z = x10724 - z = x10725 - z = x10726 - z = x10727 - z = x10728 - z = x10729 - z = x10730 - z = x10731 - z = x10732 - z = x10733 - z = x10734 - z = x10735 - z = x10736 - z = x10737 - z = x10738 - z = x10739 - z = x10740 - z = x10741 - z = x10742 - z = x10743 - z = x10744 - z = x10745 - z = x10746 - z = x10747 - z = x10748 - z = x10749 - z = x10750 - z = x10751 - z = x10752 - z = x10753 - z = x10754 - z = x10755 - z = x10756 - z = x10757 - z = x10758 - z = x10759 - z = x10760 - z = x10761 - z = x10762 - z = x10763 - z = x10764 - z = x10765 - z = x10766 - z = x10767 - z = x10768 - z = x10769 - z = x10770 - z = x10771 - z = x10772 - z = x10773 - z = x10774 - z = x10775 - z = x10776 - z = x10777 - z = x10778 - z = x10779 - z = x10780 - z = x10781 - z = x10782 - z = x10783 - z = x10784 - z = x10785 - z = x10786 - z = x10787 - z = x10788 - z = x10789 - z = x10790 - z = x10791 - z = x10792 - z = x10793 - z = x10794 - z = x10795 - z = x10796 - z = x10797 - z = x10798 - z = x10799 - z = x10800 - z = x10801 - z = x10802 - z = x10803 - z = x10804 - z = x10805 - z = x10806 - z = x10807 - z = x10808 - z = x10809 - z = x10810 - z = x10811 - z = x10812 - z = x10813 - z = x10814 - z = x10815 - z = x10816 - z = x10817 - z = x10818 - z = x10819 - z = x10820 - z = x10821 - z = x10822 - z = x10823 - z = x10824 - z = x10825 - z = x10826 - z = x10827 - z = x10828 - z = x10829 - z = x10830 - z = x10831 - z = x10832 - z = x10833 - z = x10834 - z = x10835 - z = x10836 - z = x10837 - z = x10838 - z = x10839 - z = x10840 - z = x10841 - z = x10842 - z = x10843 - z = x10844 - z = x10845 - z = x10846 - z = x10847 - z = x10848 - z = x10849 - z = x10850 - z = x10851 - z = x10852 - z = x10853 - z = x10854 - z = x10855 - z = x10856 - z = x10857 - z = x10858 - z = x10859 - z = x10860 - z = x10861 - z = x10862 - z = x10863 - z = x10864 - z = x10865 - z = x10866 - z = x10867 - z = x10868 - z = x10869 - z = x10870 - z = x10871 - z = x10872 - z = x10873 - z = x10874 - z = x10875 - z = x10876 - z = x10877 - z = x10878 - z = x10879 - z = x10880 - z = x10881 - z = x10882 - z = x10883 - z = x10884 - z = x10885 - z = x10886 - z = x10887 - z = x10888 - z = x10889 - z = x10890 - z = x10891 - z = x10892 - z = x10893 - z = x10894 - z = x10895 - z = x10896 - z = x10897 - z = x10898 - z = x10899 - z = x10900 - z = x10901 - z = x10902 - z = x10903 - z = x10904 - z = x10905 - z = x10906 - z = x10907 - z = x10908 - z = x10909 - z = x10910 - z = x10911 - z = x10912 - z = x10913 - z = x10914 - z = x10915 - z = x10916 - z = x10917 - z = x10918 - z = x10919 - z = x10920 - z = x10921 - z = x10922 - z = x10923 - z = x10924 - z = x10925 - z = x10926 - z = x10927 - z = x10928 - z = x10929 - z = x10930 - z = x10931 - z = x10932 - z = x10933 - z = x10934 - z = x10935 - z = x10936 - z = x10937 - z = x10938 - z = x10939 - z = x10940 - z = x10941 - z = x10942 - z = x10943 - z = x10944 - z = x10945 - z = x10946 - z = x10947 - z = x10948 - z = x10949 - z = x10950 - z = x10951 - z = x10952 - z = x10953 - z = x10954 - z = x10955 - z = x10956 - z = x10957 - z = x10958 - z = x10959 - z = x10960 - z = x10961 - z = x10962 - z = x10963 - z = x10964 - z = x10965 - z = x10966 - z = x10967 - z = x10968 - z = x10969 - z = x10970 - z = x10971 - z = x10972 - z = x10973 - z = x10974 - z = x10975 - z = x10976 - z = x10977 - z = x10978 - z = x10979 - z = x10980 - z = x10981 - z = x10982 - z = x10983 - z = x10984 - z = x10985 - z = x10986 - z = x10987 - z = x10988 - z = x10989 - z = x10990 - z = x10991 - z = x10992 - z = x10993 - z = x10994 - z = x10995 - z = x10996 - z = x10997 - z = x10998 - z = x10999 - z = x11000 - z = x11001 - z = x11002 - z = x11003 - z = x11004 - z = x11005 - z = x11006 - z = x11007 - z = x11008 - z = x11009 - z = x11010 - z = x11011 - z = x11012 - z = x11013 - z = x11014 - z = x11015 - z = x11016 - z = x11017 - z = x11018 - z = x11019 - z = x11020 - z = x11021 - z = x11022 - z = x11023 - z = x11024 - z = x11025 - z = x11026 - z = x11027 - z = x11028 - z = x11029 - z = x11030 - z = x11031 - z = x11032 - z = x11033 - z = x11034 - z = x11035 - z = x11036 - z = x11037 - z = x11038 - z = x11039 - z = x11040 - z = x11041 - z = x11042 - z = x11043 - z = x11044 - z = x11045 - z = x11046 - z = x11047 - z = x11048 - z = x11049 - z = x11050 - z = x11051 - z = x11052 - z = x11053 - z = x11054 - z = x11055 - z = x11056 - z = x11057 - z = x11058 - z = x11059 - z = x11060 - z = x11061 - z = x11062 - z = x11063 - z = x11064 - z = x11065 - z = x11066 - z = x11067 - z = x11068 - z = x11069 - z = x11070 - z = x11071 - z = x11072 - z = x11073 - z = x11074 - z = x11075 - z = x11076 - z = x11077 - z = x11078 - z = x11079 - z = x11080 - z = x11081 - z = x11082 - z = x11083 - z = x11084 - z = x11085 - z = x11086 - z = x11087 - z = x11088 - z = x11089 - z = x11090 - z = x11091 - z = x11092 - z = x11093 - z = x11094 - z = x11095 - z = x11096 - z = x11097 - z = x11098 - z = x11099 - z = x11100 - z = x11101 - z = x11102 - z = x11103 - z = x11104 - z = x11105 - z = x11106 - z = x11107 - z = x11108 - z = x11109 - z = x11110 - z = x11111 - z = x11112 - z = x11113 - z = x11114 - z = x11115 - z = x11116 - z = x11117 - z = x11118 - z = x11119 - z = x11120 - z = x11121 - z = x11122 - z = x11123 - z = x11124 - z = x11125 - z = x11126 - z = x11127 - z = x11128 - z = x11129 - z = x11130 - z = x11131 - z = x11132 - z = x11133 - z = x11134 - z = x11135 - z = x11136 - z = x11137 - z = x11138 - z = x11139 - z = x11140 - z = x11141 - z = x11142 - z = x11143 - z = x11144 - z = x11145 - z = x11146 - z = x11147 - z = x11148 - z = x11149 - z = x11150 - z = x11151 - z = x11152 - z = x11153 - z = x11154 - z = x11155 - z = x11156 - z = x11157 - z = x11158 - z = x11159 - z = x11160 - z = x11161 - z = x11162 - z = x11163 - z = x11164 - z = x11165 - z = x11166 - z = x11167 - z = x11168 - z = x11169 - z = x11170 - z = x11171 - z = x11172 - z = x11173 - z = x11174 - z = x11175 - z = x11176 - z = x11177 - z = x11178 - z = x11179 - z = x11180 - z = x11181 - z = x11182 - z = x11183 - z = x11184 - z = x11185 - z = x11186 - z = x11187 - z = x11188 - z = x11189 - z = x11190 - z = x11191 - z = x11192 - z = x11193 - z = x11194 - z = x11195 - z = x11196 - z = x11197 - z = x11198 - z = x11199 - z = x11200 - z = x11201 - z = x11202 - z = x11203 - z = x11204 - z = x11205 - z = x11206 - z = x11207 - z = x11208 - z = x11209 - z = x11210 - z = x11211 - z = x11212 - z = x11213 - z = x11214 - z = x11215 - z = x11216 - z = x11217 - z = x11218 - z = x11219 - z = x11220 - z = x11221 - z = x11222 - z = x11223 - z = x11224 - z = x11225 - z = x11226 - z = x11227 - z = x11228 - z = x11229 - z = x11230 - z = x11231 - z = x11232 - z = x11233 - z = x11234 - z = x11235 - z = x11236 - z = x11237 - z = x11238 - z = x11239 - z = x11240 - z = x11241 - z = x11242 - z = x11243 - z = x11244 - z = x11245 - z = x11246 - z = x11247 - z = x11248 - z = x11249 - z = x11250 - z = x11251 - z = x11252 - z = x11253 - z = x11254 - z = x11255 - z = x11256 - z = x11257 - z = x11258 - z = x11259 - z = x11260 - z = x11261 - z = x11262 - z = x11263 - z = x11264 - z = x11265 - z = x11266 - z = x11267 - z = x11268 - z = x11269 - z = x11270 - z = x11271 - z = x11272 - z = x11273 - z = x11274 - z = x11275 - z = x11276 - z = x11277 - z = x11278 - z = x11279 - z = x11280 - z = x11281 - z = x11282 - z = x11283 - z = x11284 - z = x11285 - z = x11286 - z = x11287 - z = x11288 - z = x11289 - z = x11290 - z = x11291 - z = x11292 - z = x11293 - z = x11294 - z = x11295 - z = x11296 - z = x11297 - z = x11298 - z = x11299 - z = x11300 - z = x11301 - z = x11302 - z = x11303 - z = x11304 - z = x11305 - z = x11306 - z = x11307 - z = x11308 - z = x11309 - z = x11310 - z = x11311 - z = x11312 - z = x11313 - z = x11314 - z = x11315 - z = x11316 - z = x11317 - z = x11318 - z = x11319 - z = x11320 - z = x11321 - z = x11322 - z = x11323 - z = x11324 - z = x11325 - z = x11326 - z = x11327 - z = x11328 - z = x11329 - z = x11330 - z = x11331 - z = x11332 - z = x11333 - z = x11334 - z = x11335 - z = x11336 - z = x11337 - z = x11338 - z = x11339 - z = x11340 - z = x11341 - z = x11342 - z = x11343 - z = x11344 - z = x11345 - z = x11346 - z = x11347 - z = x11348 - z = x11349 - z = x11350 - z = x11351 - z = x11352 - z = x11353 - z = x11354 - z = x11355 - z = x11356 - z = x11357 - z = x11358 - z = x11359 - z = x11360 - z = x11361 - z = x11362 - z = x11363 - z = x11364 - z = x11365 - z = x11366 - z = x11367 - z = x11368 - z = x11369 - z = x11370 - z = x11371 - z = x11372 - z = x11373 - z = x11374 - z = x11375 - z = x11376 - z = x11377 - z = x11378 - z = x11379 - z = x11380 - z = x11381 - z = x11382 - z = x11383 - z = x11384 - z = x11385 - z = x11386 - z = x11387 - z = x11388 - z = x11389 - z = x11390 - z = x11391 - z = x11392 - z = x11393 - z = x11394 - z = x11395 - z = x11396 - z = x11397 - z = x11398 - z = x11399 - z = x11400 - z = x11401 - z = x11402 - z = x11403 - z = x11404 - z = x11405 - z = x11406 - z = x11407 - z = x11408 - z = x11409 - z = x11410 - z = x11411 - z = x11412 - z = x11413 - z = x11414 - z = x11415 - z = x11416 - z = x11417 - z = x11418 - z = x11419 - z = x11420 - z = x11421 - z = x11422 - z = x11423 - z = x11424 - z = x11425 - z = x11426 - z = x11427 - z = x11428 - z = x11429 - z = x11430 - z = x11431 - z = x11432 - z = x11433 - z = x11434 - z = x11435 - z = x11436 - z = x11437 - z = x11438 - z = x11439 - z = x11440 - z = x11441 - z = x11442 - z = x11443 - z = x11444 - z = x11445 - z = x11446 - z = x11447 - z = x11448 - z = x11449 - z = x11450 - z = x11451 - z = x11452 - z = x11453 - z = x11454 - z = x11455 - z = x11456 - z = x11457 - z = x11458 - z = x11459 - z = x11460 - z = x11461 - z = x11462 - z = x11463 - z = x11464 - z = x11465 - z = x11466 - z = x11467 - z = x11468 - z = x11469 - z = x11470 - z = x11471 - z = x11472 - z = x11473 - z = x11474 - z = x11475 - z = x11476 - z = x11477 - z = x11478 - z = x11479 - z = x11480 - z = x11481 - z = x11482 - z = x11483 - z = x11484 - z = x11485 - z = x11486 - z = x11487 - z = x11488 - z = x11489 - z = x11490 - z = x11491 - z = x11492 - z = x11493 - z = x11494 - z = x11495 - z = x11496 - z = x11497 - z = x11498 - z = x11499 - z = x11500 - z = x11501 - z = x11502 - z = x11503 - z = x11504 - z = x11505 - z = x11506 - z = x11507 - z = x11508 - z = x11509 - z = x11510 - z = x11511 - z = x11512 - z = x11513 - z = x11514 - z = x11515 - z = x11516 - z = x11517 - z = x11518 - z = x11519 - z = x11520 - z = x11521 - z = x11522 - z = x11523 - z = x11524 - z = x11525 - z = x11526 - z = x11527 - z = x11528 - z = x11529 - z = x11530 - z = x11531 - z = x11532 - z = x11533 - z = x11534 - z = x11535 - z = x11536 - z = x11537 - z = x11538 - z = x11539 - z = x11540 - z = x11541 - z = x11542 - z = x11543 - z = x11544 - z = x11545 - z = x11546 - z = x11547 - z = x11548 - z = x11549 - z = x11550 - z = x11551 - z = x11552 - z = x11553 - z = x11554 - z = x11555 - z = x11556 - z = x11557 - z = x11558 - z = x11559 - z = x11560 - z = x11561 - z = x11562 - z = x11563 - z = x11564 - z = x11565 - z = x11566 - z = x11567 - z = x11568 - z = x11569 - z = x11570 - z = x11571 - z = x11572 - z = x11573 - z = x11574 - z = x11575 - z = x11576 - z = x11577 - z = x11578 - z = x11579 - z = x11580 - z = x11581 - z = x11582 - z = x11583 - z = x11584 - z = x11585 - z = x11586 - z = x11587 - z = x11588 - z = x11589 - z = x11590 - z = x11591 - z = x11592 - z = x11593 - z = x11594 - z = x11595 - z = x11596 - z = x11597 - z = x11598 - z = x11599 - z = x11600 - z = x11601 - z = x11602 - z = x11603 - z = x11604 - z = x11605 - z = x11606 - z = x11607 - z = x11608 - z = x11609 - z = x11610 - z = x11611 - z = x11612 - z = x11613 - z = x11614 - z = x11615 - z = x11616 - z = x11617 - z = x11618 - z = x11619 - z = x11620 - z = x11621 - z = x11622 - z = x11623 - z = x11624 - z = x11625 - z = x11626 - z = x11627 - z = x11628 - z = x11629 - z = x11630 - z = x11631 - z = x11632 - z = x11633 - z = x11634 - z = x11635 - z = x11636 - z = x11637 - z = x11638 - z = x11639 - z = x11640 - z = x11641 - z = x11642 - z = x11643 - z = x11644 - z = x11645 - z = x11646 - z = x11647 - z = x11648 - z = x11649 - z = x11650 - z = x11651 - z = x11652 - z = x11653 - z = x11654 - z = x11655 - z = x11656 - z = x11657 - z = x11658 - z = x11659 - z = x11660 - z = x11661 - z = x11662 - z = x11663 - z = x11664 - z = x11665 - z = x11666 - z = x11667 - z = x11668 - z = x11669 - z = x11670 - z = x11671 - z = x11672 - z = x11673 - z = x11674 - z = x11675 - z = x11676 - z = x11677 - z = x11678 - z = x11679 - z = x11680 - z = x11681 - z = x11682 - z = x11683 - z = x11684 - z = x11685 - z = x11686 - z = x11687 - z = x11688 - z = x11689 - z = x11690 - z = x11691 - z = x11692 - z = x11693 - z = x11694 - z = x11695 - z = x11696 - z = x11697 - z = x11698 - z = x11699 - z = x11700 - z = x11701 - z = x11702 - z = x11703 - z = x11704 - z = x11705 - z = x11706 - z = x11707 - z = x11708 - z = x11709 - z = x11710 - z = x11711 - z = x11712 - z = x11713 - z = x11714 - z = x11715 - z = x11716 - z = x11717 - z = x11718 - z = x11719 - z = x11720 - z = x11721 - z = x11722 - z = x11723 - z = x11724 - z = x11725 - z = x11726 - z = x11727 - z = x11728 - z = x11729 - z = x11730 - z = x11731 - z = x11732 - z = x11733 - z = x11734 - z = x11735 - z = x11736 - z = x11737 - z = x11738 - z = x11739 - z = x11740 - z = x11741 - z = x11742 - z = x11743 - z = x11744 - z = x11745 - z = x11746 - z = x11747 - z = x11748 - z = x11749 - z = x11750 - z = x11751 - z = x11752 - z = x11753 - z = x11754 - z = x11755 - z = x11756 - z = x11757 - z = x11758 - z = x11759 - z = x11760 - z = x11761 - z = x11762 - z = x11763 - z = x11764 - z = x11765 - z = x11766 - z = x11767 - z = x11768 - z = x11769 - z = x11770 - z = x11771 - z = x11772 - z = x11773 - z = x11774 - z = x11775 - z = x11776 - z = x11777 - z = x11778 - z = x11779 - z = x11780 - z = x11781 - z = x11782 - z = x11783 - z = x11784 - z = x11785 - z = x11786 - z = x11787 - z = x11788 - z = x11789 - z = x11790 - z = x11791 - z = x11792 - z = x11793 - z = x11794 - z = x11795 - z = x11796 - z = x11797 - z = x11798 - z = x11799 - z = x11800 - z = x11801 - z = x11802 - z = x11803 - z = x11804 - z = x11805 - z = x11806 - z = x11807 - z = x11808 - z = x11809 - z = x11810 - z = x11811 - z = x11812 - z = x11813 - z = x11814 - z = x11815 - z = x11816 - z = x11817 - z = x11818 - z = x11819 - z = x11820 - z = x11821 - z = x11822 - z = x11823 - z = x11824 - z = x11825 - z = x11826 - z = x11827 - z = x11828 - z = x11829 - z = x11830 - z = x11831 - z = x11832 - z = x11833 - z = x11834 - z = x11835 - z = x11836 - z = x11837 - z = x11838 - z = x11839 - z = x11840 - z = x11841 - z = x11842 - z = x11843 - z = x11844 - z = x11845 - z = x11846 - z = x11847 - z = x11848 - z = x11849 - z = x11850 - z = x11851 - z = x11852 - z = x11853 - z = x11854 - z = x11855 - z = x11856 - z = x11857 - z = x11858 - z = x11859 - z = x11860 - z = x11861 - z = x11862 - z = x11863 - z = x11864 - z = x11865 - z = x11866 - z = x11867 - z = x11868 - z = x11869 - z = x11870 - z = x11871 - z = x11872 - z = x11873 - z = x11874 - z = x11875 - z = x11876 - z = x11877 - z = x11878 - z = x11879 - z = x11880 - z = x11881 - z = x11882 - z = x11883 - z = x11884 - z = x11885 - z = x11886 - z = x11887 - z = x11888 - z = x11889 - z = x11890 - z = x11891 - z = x11892 - z = x11893 - z = x11894 - z = x11895 - z = x11896 - z = x11897 - z = x11898 - z = x11899 - z = x11900 - z = x11901 - z = x11902 - z = x11903 - z = x11904 - z = x11905 - z = x11906 - z = x11907 - z = x11908 - z = x11909 - z = x11910 - z = x11911 - z = x11912 - z = x11913 - z = x11914 - z = x11915 - z = x11916 - z = x11917 - z = x11918 - z = x11919 - z = x11920 - z = x11921 - z = x11922 - z = x11923 - z = x11924 - z = x11925 - z = x11926 - z = x11927 - z = x11928 - z = x11929 - z = x11930 - z = x11931 - z = x11932 - z = x11933 - z = x11934 - z = x11935 - z = x11936 - z = x11937 - z = x11938 - z = x11939 - z = x11940 - z = x11941 - z = x11942 - z = x11943 - z = x11944 - z = x11945 - z = x11946 - z = x11947 - z = x11948 - z = x11949 - z = x11950 - z = x11951 - z = x11952 - z = x11953 - z = x11954 - z = x11955 - z = x11956 - z = x11957 - z = x11958 - z = x11959 - z = x11960 - z = x11961 - z = x11962 - z = x11963 - z = x11964 - z = x11965 - z = x11966 - z = x11967 - z = x11968 - z = x11969 - z = x11970 - z = x11971 - z = x11972 - z = x11973 - z = x11974 - z = x11975 - z = x11976 - z = x11977 - z = x11978 - z = x11979 - z = x11980 - z = x11981 - z = x11982 - z = x11983 - z = x11984 - z = x11985 - z = x11986 - z = x11987 - z = x11988 - z = x11989 - z = x11990 - z = x11991 - z = x11992 - z = x11993 - z = x11994 - z = x11995 - z = x11996 - z = x11997 - z = x11998 - z = x11999 - z = x12000 - z = x12001 - z = x12002 - z = x12003 - z = x12004 - z = x12005 - z = x12006 - z = x12007 - z = x12008 - z = x12009 - z = x12010 - z = x12011 - z = x12012 - z = x12013 - z = x12014 - z = x12015 - z = x12016 - z = x12017 - z = x12018 - z = x12019 - z = x12020 - z = x12021 - z = x12022 - z = x12023 - z = x12024 - z = x12025 - z = x12026 - z = x12027 - z = x12028 - z = x12029 - z = x12030 - z = x12031 - z = x12032 - z = x12033 - z = x12034 - z = x12035 - z = x12036 - z = x12037 - z = x12038 - z = x12039 - z = x12040 - z = x12041 - z = x12042 - z = x12043 - z = x12044 - z = x12045 - z = x12046 - z = x12047 - z = x12048 - z = x12049 - z = x12050 - z = x12051 - z = x12052 - z = x12053 - z = x12054 - z = x12055 - z = x12056 - z = x12057 - z = x12058 - z = x12059 - z = x12060 - z = x12061 - z = x12062 - z = x12063 - z = x12064 - z = x12065 - z = x12066 - z = x12067 - z = x12068 - z = x12069 - z = x12070 - z = x12071 - z = x12072 - z = x12073 - z = x12074 - z = x12075 - z = x12076 - z = x12077 - z = x12078 - z = x12079 - z = x12080 - z = x12081 - z = x12082 - z = x12083 - z = x12084 - z = x12085 - z = x12086 - z = x12087 - z = x12088 - z = x12089 - z = x12090 - z = x12091 - z = x12092 - z = x12093 - z = x12094 - z = x12095 - z = x12096 - z = x12097 - z = x12098 - z = x12099 - z = x12100 - z = x12101 - z = x12102 - z = x12103 - z = x12104 - z = x12105 - z = x12106 - z = x12107 - z = x12108 - z = x12109 - z = x12110 - z = x12111 - z = x12112 - z = x12113 - z = x12114 - z = x12115 - z = x12116 - z = x12117 - z = x12118 - z = x12119 - z = x12120 - z = x12121 - z = x12122 - z = x12123 - z = x12124 - z = x12125 - z = x12126 - z = x12127 - z = x12128 - z = x12129 - z = x12130 - z = x12131 - z = x12132 - z = x12133 - z = x12134 - z = x12135 - z = x12136 - z = x12137 - z = x12138 - z = x12139 - z = x12140 - z = x12141 - z = x12142 - z = x12143 - z = x12144 - z = x12145 - z = x12146 - z = x12147 - z = x12148 - z = x12149 - z = x12150 - z = x12151 - z = x12152 - z = x12153 - z = x12154 - z = x12155 - z = x12156 - z = x12157 - z = x12158 - z = x12159 - z = x12160 - z = x12161 - z = x12162 - z = x12163 - z = x12164 - z = x12165 - z = x12166 - z = x12167 - z = x12168 - z = x12169 - z = x12170 - z = x12171 - z = x12172 - z = x12173 - z = x12174 - z = x12175 - z = x12176 - z = x12177 - z = x12178 - z = x12179 - z = x12180 - z = x12181 - z = x12182 - z = x12183 - z = x12184 - z = x12185 - z = x12186 - z = x12187 - z = x12188 - z = x12189 - z = x12190 - z = x12191 - z = x12192 - z = x12193 - z = x12194 - z = x12195 - z = x12196 - z = x12197 - z = x12198 - z = x12199 - z = x12200 - z = x12201 - z = x12202 - z = x12203 - z = x12204 - z = x12205 - z = x12206 - z = x12207 - z = x12208 - z = x12209 - z = x12210 - z = x12211 - z = x12212 - z = x12213 - z = x12214 - z = x12215 - z = x12216 - z = x12217 - z = x12218 - z = x12219 - z = x12220 - z = x12221 - z = x12222 - z = x12223 - z = x12224 - z = x12225 - z = x12226 - z = x12227 - z = x12228 - z = x12229 - z = x12230 - z = x12231 - z = x12232 - z = x12233 - z = x12234 - z = x12235 - z = x12236 - z = x12237 - z = x12238 - z = x12239 - z = x12240 - z = x12241 - z = x12242 - z = x12243 - z = x12244 - z = x12245 - z = x12246 - z = x12247 - z = x12248 - z = x12249 - z = x12250 - z = x12251 - z = x12252 - z = x12253 - z = x12254 - z = x12255 - z = x12256 - z = x12257 - z = x12258 - z = x12259 - z = x12260 - z = x12261 - z = x12262 - z = x12263 - z = x12264 - z = x12265 - z = x12266 - z = x12267 - z = x12268 - z = x12269 - z = x12270 - z = x12271 - z = x12272 - z = x12273 - z = x12274 - z = x12275 - z = x12276 - z = x12277 - z = x12278 - z = x12279 - z = x12280 - z = x12281 - z = x12282 - z = x12283 - z = x12284 - z = x12285 - z = x12286 - z = x12287 - z = x12288 - z = x12289 - z = x12290 - z = x12291 - z = x12292 - z = x12293 - z = x12294 - z = x12295 - z = x12296 - z = x12297 - z = x12298 - z = x12299 - z = x12300 - z = x12301 - z = x12302 - z = x12303 - z = x12304 - z = x12305 - z = x12306 - z = x12307 - z = x12308 - z = x12309 - z = x12310 - z = x12311 - z = x12312 - z = x12313 - z = x12314 - z = x12315 - z = x12316 - z = x12317 - z = x12318 - z = x12319 - z = x12320 - z = x12321 - z = x12322 - z = x12323 - z = x12324 - z = x12325 - z = x12326 - z = x12327 - z = x12328 - z = x12329 - z = x12330 - z = x12331 - z = x12332 - z = x12333 - z = x12334 - z = x12335 - z = x12336 - z = x12337 - z = x12338 - z = x12339 - z = x12340 - z = x12341 - z = x12342 - z = x12343 - z = x12344 - z = x12345 - z = x12346 - z = x12347 - z = x12348 - z = x12349 - z = x12350 - z = x12351 - z = x12352 - z = x12353 - z = x12354 - z = x12355 - z = x12356 - z = x12357 - z = x12358 - z = x12359 - z = x12360 - z = x12361 - z = x12362 - z = x12363 - z = x12364 - z = x12365 - z = x12366 - z = x12367 - z = x12368 - z = x12369 - z = x12370 - z = x12371 - z = x12372 - z = x12373 - z = x12374 - z = x12375 - z = x12376 - z = x12377 - z = x12378 - z = x12379 - z = x12380 - z = x12381 - z = x12382 - z = x12383 - z = x12384 - z = x12385 - z = x12386 - z = x12387 - z = x12388 - z = x12389 - z = x12390 - z = x12391 - z = x12392 - z = x12393 - z = x12394 - z = x12395 - z = x12396 - z = x12397 - z = x12398 - z = x12399 - z = x12400 - z = x12401 - z = x12402 - z = x12403 - z = x12404 - z = x12405 - z = x12406 - z = x12407 - z = x12408 - z = x12409 - z = x12410 - z = x12411 - z = x12412 - z = x12413 - z = x12414 - z = x12415 - z = x12416 - z = x12417 - z = x12418 - z = x12419 - z = x12420 - z = x12421 - z = x12422 - z = x12423 - z = x12424 - z = x12425 - z = x12426 - z = x12427 - z = x12428 - z = x12429 - z = x12430 - z = x12431 - z = x12432 - z = x12433 - z = x12434 - z = x12435 - z = x12436 - z = x12437 - z = x12438 - z = x12439 - z = x12440 - z = x12441 - z = x12442 - z = x12443 - z = x12444 - z = x12445 - z = x12446 - z = x12447 - z = x12448 - z = x12449 - z = x12450 - z = x12451 - z = x12452 - z = x12453 - z = x12454 - z = x12455 - z = x12456 - z = x12457 - z = x12458 - z = x12459 - z = x12460 - z = x12461 - z = x12462 - z = x12463 - z = x12464 - z = x12465 - z = x12466 - z = x12467 - z = x12468 - z = x12469 - z = x12470 - z = x12471 - z = x12472 - z = x12473 - z = x12474 - z = x12475 - z = x12476 - z = x12477 - z = x12478 - z = x12479 - z = x12480 - z = x12481 - z = x12482 - z = x12483 - z = x12484 - z = x12485 - z = x12486 - z = x12487 - z = x12488 - z = x12489 - z = x12490 - z = x12491 - z = x12492 - z = x12493 - z = x12494 - z = x12495 - z = x12496 - z = x12497 - z = x12498 - z = x12499 - z = x12500 - z = x12501 - z = x12502 - z = x12503 - z = x12504 - z = x12505 - z = x12506 - z = x12507 - z = x12508 - z = x12509 - z = x12510 - z = x12511 - z = x12512 - z = x12513 - z = x12514 - z = x12515 - z = x12516 - z = x12517 - z = x12518 - z = x12519 - z = x12520 - z = x12521 - z = x12522 - z = x12523 - z = x12524 - z = x12525 - z = x12526 - z = x12527 - z = x12528 - z = x12529 - z = x12530 - z = x12531 - z = x12532 - z = x12533 - z = x12534 - z = x12535 - z = x12536 - z = x12537 - z = x12538 - z = x12539 - z = x12540 - z = x12541 - z = x12542 - z = x12543 - z = x12544 - z = x12545 - z = x12546 - z = x12547 - z = x12548 - z = x12549 - z = x12550 - z = x12551 - z = x12552 - z = x12553 - z = x12554 - z = x12555 - z = x12556 - z = x12557 - z = x12558 - z = x12559 - z = x12560 - z = x12561 - z = x12562 - z = x12563 - z = x12564 - z = x12565 - z = x12566 - z = x12567 - z = x12568 - z = x12569 - z = x12570 - z = x12571 - z = x12572 - z = x12573 - z = x12574 - z = x12575 - z = x12576 - z = x12577 - z = x12578 - z = x12579 - z = x12580 - z = x12581 - z = x12582 - z = x12583 - z = x12584 - z = x12585 - z = x12586 - z = x12587 - z = x12588 - z = x12589 - z = x12590 - z = x12591 - z = x12592 - z = x12593 - z = x12594 - z = x12595 - z = x12596 - z = x12597 - z = x12598 - z = x12599 - z = x12600 - z = x12601 - z = x12602 - z = x12603 - z = x12604 - z = x12605 - z = x12606 - z = x12607 - z = x12608 - z = x12609 - z = x12610 - z = x12611 - z = x12612 - z = x12613 - z = x12614 - z = x12615 - z = x12616 - z = x12617 - z = x12618 - z = x12619 - z = x12620 - z = x12621 - z = x12622 - z = x12623 - z = x12624 - z = x12625 - z = x12626 - z = x12627 - z = x12628 - z = x12629 - z = x12630 - z = x12631 - z = x12632 - z = x12633 - z = x12634 - z = x12635 - z = x12636 - z = x12637 - z = x12638 - z = x12639 - z = x12640 - z = x12641 - z = x12642 - z = x12643 - z = x12644 - z = x12645 - z = x12646 - z = x12647 - z = x12648 - z = x12649 - z = x12650 - z = x12651 - z = x12652 - z = x12653 - z = x12654 - z = x12655 - z = x12656 - z = x12657 - z = x12658 - z = x12659 - z = x12660 - z = x12661 - z = x12662 - z = x12663 - z = x12664 - z = x12665 - z = x12666 - z = x12667 - z = x12668 - z = x12669 - z = x12670 - z = x12671 - z = x12672 - z = x12673 - z = x12674 - z = x12675 - z = x12676 - z = x12677 - z = x12678 - z = x12679 - z = x12680 - z = x12681 - z = x12682 - z = x12683 - z = x12684 - z = x12685 - z = x12686 - z = x12687 - z = x12688 - z = x12689 - z = x12690 - z = x12691 - z = x12692 - z = x12693 - z = x12694 - z = x12695 - z = x12696 - z = x12697 - z = x12698 - z = x12699 - z = x12700 - z = x12701 - z = x12702 - z = x12703 - z = x12704 - z = x12705 - z = x12706 - z = x12707 - z = x12708 - z = x12709 - z = x12710 - z = x12711 - z = x12712 - z = x12713 - z = x12714 - z = x12715 - z = x12716 - z = x12717 - z = x12718 - z = x12719 - z = x12720 - z = x12721 - z = x12722 - z = x12723 - z = x12724 - z = x12725 - z = x12726 - z = x12727 - z = x12728 - z = x12729 - z = x12730 - z = x12731 - z = x12732 - z = x12733 - z = x12734 - z = x12735 - z = x12736 - z = x12737 - z = x12738 - z = x12739 - z = x12740 - z = x12741 - z = x12742 - z = x12743 - z = x12744 - z = x12745 - z = x12746 - z = x12747 - z = x12748 - z = x12749 - z = x12750 - z = x12751 - z = x12752 - z = x12753 - z = x12754 - z = x12755 - z = x12756 - z = x12757 - z = x12758 - z = x12759 - z = x12760 - z = x12761 - z = x12762 - z = x12763 - z = x12764 - z = x12765 - z = x12766 - z = x12767 - z = x12768 - z = x12769 - z = x12770 - z = x12771 - z = x12772 - z = x12773 - z = x12774 - z = x12775 - z = x12776 - z = x12777 - z = x12778 - z = x12779 - z = x12780 - z = x12781 - z = x12782 - z = x12783 - z = x12784 - z = x12785 - z = x12786 - z = x12787 - z = x12788 - z = x12789 - z = x12790 - z = x12791 - z = x12792 - z = x12793 - z = x12794 - z = x12795 - z = x12796 - z = x12797 - z = x12798 - z = x12799 - z = x12800 - z = x12801 - z = x12802 - z = x12803 - z = x12804 - z = x12805 - z = x12806 - z = x12807 - z = x12808 - z = x12809 - z = x12810 - z = x12811 - z = x12812 - z = x12813 - z = x12814 - z = x12815 - z = x12816 - z = x12817 - z = x12818 - z = x12819 - z = x12820 - z = x12821 - z = x12822 - z = x12823 - z = x12824 - z = x12825 - z = x12826 - z = x12827 - z = x12828 - z = x12829 - z = x12830 - z = x12831 - z = x12832 - z = x12833 - z = x12834 - z = x12835 - z = x12836 - z = x12837 - z = x12838 - z = x12839 - z = x12840 - z = x12841 - z = x12842 - z = x12843 - z = x12844 - z = x12845 - z = x12846 - z = x12847 - z = x12848 - z = x12849 - z = x12850 - z = x12851 - z = x12852 - z = x12853 - z = x12854 - z = x12855 - z = x12856 - z = x12857 - z = x12858 - z = x12859 - z = x12860 - z = x12861 - z = x12862 - z = x12863 - z = x12864 - z = x12865 - z = x12866 - z = x12867 - z = x12868 - z = x12869 - z = x12870 - z = x12871 - z = x12872 - z = x12873 - z = x12874 - z = x12875 - z = x12876 - z = x12877 - z = x12878 - z = x12879 - z = x12880 - z = x12881 - z = x12882 - z = x12883 - z = x12884 - z = x12885 - z = x12886 - z = x12887 - z = x12888 - z = x12889 - z = x12890 - z = x12891 - z = x12892 - z = x12893 - z = x12894 - z = x12895 - z = x12896 - z = x12897 - z = x12898 - z = x12899 - z = x12900 - z = x12901 - z = x12902 - z = x12903 - z = x12904 - z = x12905 - z = x12906 - z = x12907 - z = x12908 - z = x12909 - z = x12910 - z = x12911 - z = x12912 - z = x12913 - z = x12914 - z = x12915 - z = x12916 - z = x12917 - z = x12918 - z = x12919 - z = x12920 - z = x12921 - z = x12922 - z = x12923 - z = x12924 - z = x12925 - z = x12926 - z = x12927 - z = x12928 - z = x12929 - z = x12930 - z = x12931 - z = x12932 - z = x12933 - z = x12934 - z = x12935 - z = x12936 - z = x12937 - z = x12938 - z = x12939 - z = x12940 - z = x12941 - z = x12942 - z = x12943 - z = x12944 - z = x12945 - z = x12946 - z = x12947 - z = x12948 - z = x12949 - z = x12950 - z = x12951 - z = x12952 - z = x12953 - z = x12954 - z = x12955 - z = x12956 - z = x12957 - z = x12958 - z = x12959 - z = x12960 - z = x12961 - z = x12962 - z = x12963 - z = x12964 - z = x12965 - z = x12966 - z = x12967 - z = x12968 - z = x12969 - z = x12970 - z = x12971 - z = x12972 - z = x12973 - z = x12974 - z = x12975 - z = x12976 - z = x12977 - z = x12978 - z = x12979 - z = x12980 - z = x12981 - z = x12982 - z = x12983 - z = x12984 - z = x12985 - z = x12986 - z = x12987 - z = x12988 - z = x12989 - z = x12990 - z = x12991 - z = x12992 - z = x12993 - z = x12994 - z = x12995 - z = x12996 - z = x12997 - z = x12998 - z = x12999 - z = x13000 - z = x13001 - z = x13002 - z = x13003 - z = x13004 - z = x13005 - z = x13006 - z = x13007 - z = x13008 - z = x13009 - z = x13010 - z = x13011 - z = x13012 - z = x13013 - z = x13014 - z = x13015 - z = x13016 - z = x13017 - z = x13018 - z = x13019 - z = x13020 - z = x13021 - z = x13022 - z = x13023 - z = x13024 - z = x13025 - z = x13026 - z = x13027 - z = x13028 - z = x13029 - z = x13030 - z = x13031 - z = x13032 - z = x13033 - z = x13034 - z = x13035 - z = x13036 - z = x13037 - z = x13038 - z = x13039 - z = x13040 - z = x13041 - z = x13042 - z = x13043 - z = x13044 - z = x13045 - z = x13046 - z = x13047 - z = x13048 - z = x13049 - z = x13050 - z = x13051 - z = x13052 - z = x13053 - z = x13054 - z = x13055 - z = x13056 - z = x13057 - z = x13058 - z = x13059 - z = x13060 - z = x13061 - z = x13062 - z = x13063 - z = x13064 - z = x13065 - z = x13066 - z = x13067 - z = x13068 - z = x13069 - z = x13070 - z = x13071 - z = x13072 - z = x13073 - z = x13074 - z = x13075 - z = x13076 - z = x13077 - z = x13078 - z = x13079 - z = x13080 - z = x13081 - z = x13082 - z = x13083 - z = x13084 - z = x13085 - z = x13086 - z = x13087 - z = x13088 - z = x13089 - z = x13090 - z = x13091 - z = x13092 - z = x13093 - z = x13094 - z = x13095 - z = x13096 - z = x13097 - z = x13098 - z = x13099 - z = x13100 - z = x13101 - z = x13102 - z = x13103 - z = x13104 - z = x13105 - z = x13106 - z = x13107 - z = x13108 - z = x13109 - z = x13110 - z = x13111 - z = x13112 - z = x13113 - z = x13114 - z = x13115 - z = x13116 - z = x13117 - z = x13118 - z = x13119 - z = x13120 - z = x13121 - z = x13122 - z = x13123 - z = x13124 - z = x13125 - z = x13126 - z = x13127 - z = x13128 - z = x13129 - z = x13130 - z = x13131 - z = x13132 - z = x13133 - z = x13134 - z = x13135 - z = x13136 - z = x13137 - z = x13138 - z = x13139 - z = x13140 - z = x13141 - z = x13142 - z = x13143 - z = x13144 - z = x13145 - z = x13146 - z = x13147 - z = x13148 - z = x13149 - z = x13150 - z = x13151 - z = x13152 - z = x13153 - z = x13154 - z = x13155 - z = x13156 - z = x13157 - z = x13158 - z = x13159 - z = x13160 - z = x13161 - z = x13162 - z = x13163 - z = x13164 - z = x13165 - z = x13166 - z = x13167 - z = x13168 - z = x13169 - z = x13170 - z = x13171 - z = x13172 - z = x13173 - z = x13174 - z = x13175 - z = x13176 - z = x13177 - z = x13178 - z = x13179 - z = x13180 - z = x13181 - z = x13182 - z = x13183 - z = x13184 - z = x13185 - z = x13186 - z = x13187 - z = x13188 - z = x13189 - z = x13190 - z = x13191 - z = x13192 - z = x13193 - z = x13194 - z = x13195 - z = x13196 - z = x13197 - z = x13198 - z = x13199 - z = x13200 - z = x13201 - z = x13202 - z = x13203 - z = x13204 - z = x13205 - z = x13206 - z = x13207 - z = x13208 - z = x13209 - z = x13210 - z = x13211 - z = x13212 - z = x13213 - z = x13214 - z = x13215 - z = x13216 - z = x13217 - z = x13218 - z = x13219 - z = x13220 - z = x13221 - z = x13222 - z = x13223 - z = x13224 - z = x13225 - z = x13226 - z = x13227 - z = x13228 - z = x13229 - z = x13230 - z = x13231 - z = x13232 - z = x13233 - z = x13234 - z = x13235 - z = x13236 - z = x13237 - z = x13238 - z = x13239 - z = x13240 - z = x13241 - z = x13242 - z = x13243 - z = x13244 - z = x13245 - z = x13246 - z = x13247 - z = x13248 - z = x13249 - z = x13250 - z = x13251 - z = x13252 - z = x13253 - z = x13254 - z = x13255 - z = x13256 - z = x13257 - z = x13258 - z = x13259 - z = x13260 - z = x13261 - z = x13262 - z = x13263 - z = x13264 - z = x13265 - z = x13266 - z = x13267 - z = x13268 - z = x13269 - z = x13270 - z = x13271 - z = x13272 - z = x13273 - z = x13274 - z = x13275 - z = x13276 - z = x13277 - z = x13278 - z = x13279 - z = x13280 - z = x13281 - z = x13282 - z = x13283 - z = x13284 - z = x13285 - z = x13286 - z = x13287 - z = x13288 - z = x13289 - z = x13290 - z = x13291 - z = x13292 - z = x13293 - z = x13294 - z = x13295 - z = x13296 - z = x13297 - z = x13298 - z = x13299 - z = x13300 - z = x13301 - z = x13302 - z = x13303 - z = x13304 - z = x13305 - z = x13306 - z = x13307 - z = x13308 - z = x13309 - z = x13310 - z = x13311 - z = x13312 - z = x13313 - z = x13314 - z = x13315 - z = x13316 - z = x13317 - z = x13318 - z = x13319 - z = x13320 - z = x13321 - z = x13322 - z = x13323 - z = x13324 - z = x13325 - z = x13326 - z = x13327 - z = x13328 - z = x13329 - z = x13330 - z = x13331 - z = x13332 - z = x13333 - z = x13334 - z = x13335 - z = x13336 - z = x13337 - z = x13338 - z = x13339 - z = x13340 - z = x13341 - z = x13342 - z = x13343 - z = x13344 - z = x13345 - z = x13346 - z = x13347 - z = x13348 - z = x13349 - z = x13350 - z = x13351 - z = x13352 - z = x13353 - z = x13354 - z = x13355 - z = x13356 - z = x13357 - z = x13358 - z = x13359 - z = x13360 - z = x13361 - z = x13362 - z = x13363 - z = x13364 - z = x13365 - z = x13366 - z = x13367 - z = x13368 - z = x13369 - z = x13370 - z = x13371 - z = x13372 - z = x13373 - z = x13374 - z = x13375 - z = x13376 - z = x13377 - z = x13378 - z = x13379 - z = x13380 - z = x13381 - z = x13382 - z = x13383 - z = x13384 - z = x13385 - z = x13386 - z = x13387 - z = x13388 - z = x13389 - z = x13390 - z = x13391 - z = x13392 - z = x13393 - z = x13394 - z = x13395 - z = x13396 - z = x13397 - z = x13398 - z = x13399 - z = x13400 - z = x13401 - z = x13402 - z = x13403 - z = x13404 - z = x13405 - z = x13406 - z = x13407 - z = x13408 - z = x13409 - z = x13410 - z = x13411 - z = x13412 - z = x13413 - z = x13414 - z = x13415 - z = x13416 - z = x13417 - z = x13418 - z = x13419 - z = x13420 - z = x13421 - z = x13422 - z = x13423 - z = x13424 - z = x13425 - z = x13426 - z = x13427 - z = x13428 - z = x13429 - z = x13430 - z = x13431 - z = x13432 - z = x13433 - z = x13434 - z = x13435 - z = x13436 - z = x13437 - z = x13438 - z = x13439 - z = x13440 - z = x13441 - z = x13442 - z = x13443 - z = x13444 - z = x13445 - z = x13446 - z = x13447 - z = x13448 - z = x13449 - z = x13450 - z = x13451 - z = x13452 - z = x13453 - z = x13454 - z = x13455 - z = x13456 - z = x13457 - z = x13458 - z = x13459 - z = x13460 - z = x13461 - z = x13462 - z = x13463 - z = x13464 - z = x13465 - z = x13466 - z = x13467 - z = x13468 - z = x13469 - z = x13470 - z = x13471 - z = x13472 - z = x13473 - z = x13474 - z = x13475 - z = x13476 - z = x13477 - z = x13478 - z = x13479 - z = x13480 - z = x13481 - z = x13482 - z = x13483 - z = x13484 - z = x13485 - z = x13486 - z = x13487 - z = x13488 - z = x13489 - z = x13490 - z = x13491 - z = x13492 - z = x13493 - z = x13494 - z = x13495 - z = x13496 - z = x13497 - z = x13498 - z = x13499 - z = x13500 - z = x13501 - z = x13502 - z = x13503 - z = x13504 - z = x13505 - z = x13506 - z = x13507 - z = x13508 - z = x13509 - z = x13510 - z = x13511 - z = x13512 - z = x13513 - z = x13514 - z = x13515 - z = x13516 - z = x13517 - z = x13518 - z = x13519 - z = x13520 - z = x13521 - z = x13522 - z = x13523 - z = x13524 - z = x13525 - z = x13526 - z = x13527 - z = x13528 - z = x13529 - z = x13530 - z = x13531 - z = x13532 - z = x13533 - z = x13534 - z = x13535 - z = x13536 - z = x13537 - z = x13538 - z = x13539 - z = x13540 - z = x13541 - z = x13542 - z = x13543 - z = x13544 - z = x13545 - z = x13546 - z = x13547 - z = x13548 - z = x13549 - z = x13550 - z = x13551 - z = x13552 - z = x13553 - z = x13554 - z = x13555 - z = x13556 - z = x13557 - z = x13558 - z = x13559 - z = x13560 - z = x13561 - z = x13562 - z = x13563 - z = x13564 - z = x13565 - z = x13566 - z = x13567 - z = x13568 - z = x13569 - z = x13570 - z = x13571 - z = x13572 - z = x13573 - z = x13574 - z = x13575 - z = x13576 - z = x13577 - z = x13578 - z = x13579 - z = x13580 - z = x13581 - z = x13582 - z = x13583 - z = x13584 - z = x13585 - z = x13586 - z = x13587 - z = x13588 - z = x13589 - z = x13590 - z = x13591 - z = x13592 - z = x13593 - z = x13594 - z = x13595 - z = x13596 - z = x13597 - z = x13598 - z = x13599 - z = x13600 - z = x13601 - z = x13602 - z = x13603 - z = x13604 - z = x13605 - z = x13606 - z = x13607 - z = x13608 - z = x13609 - z = x13610 - z = x13611 - z = x13612 - z = x13613 - z = x13614 - z = x13615 - z = x13616 - z = x13617 - z = x13618 - z = x13619 - z = x13620 - z = x13621 - z = x13622 - z = x13623 - z = x13624 - z = x13625 - z = x13626 - z = x13627 - z = x13628 - z = x13629 - z = x13630 - z = x13631 - z = x13632 - z = x13633 - z = x13634 - z = x13635 - z = x13636 - z = x13637 - z = x13638 - z = x13639 - z = x13640 - z = x13641 - z = x13642 - z = x13643 - z = x13644 - z = x13645 - z = x13646 - z = x13647 - z = x13648 - z = x13649 - z = x13650 - z = x13651 - z = x13652 - z = x13653 - z = x13654 - z = x13655 - z = x13656 - z = x13657 - z = x13658 - z = x13659 - z = x13660 - z = x13661 - z = x13662 - z = x13663 - z = x13664 - z = x13665 - z = x13666 - z = x13667 - z = x13668 - z = x13669 - z = x13670 - z = x13671 - z = x13672 - z = x13673 - z = x13674 - z = x13675 - z = x13676 - z = x13677 - z = x13678 - z = x13679 - z = x13680 - z = x13681 - z = x13682 - z = x13683 - z = x13684 - z = x13685 - z = x13686 - z = x13687 - z = x13688 - z = x13689 - z = x13690 - z = x13691 - z = x13692 - z = x13693 - z = x13694 - z = x13695 - z = x13696 - z = x13697 - z = x13698 - z = x13699 - z = x13700 - z = x13701 - z = x13702 - z = x13703 - z = x13704 - z = x13705 - z = x13706 - z = x13707 - z = x13708 - z = x13709 - z = x13710 - z = x13711 - z = x13712 - z = x13713 - z = x13714 - z = x13715 - z = x13716 - z = x13717 - z = x13718 - z = x13719 - z = x13720 - z = x13721 - z = x13722 - z = x13723 - z = x13724 - z = x13725 - z = x13726 - z = x13727 - z = x13728 - z = x13729 - z = x13730 - z = x13731 - z = x13732 - z = x13733 - z = x13734 - z = x13735 - z = x13736 - z = x13737 - z = x13738 - z = x13739 - z = x13740 - z = x13741 - z = x13742 - z = x13743 - z = x13744 - z = x13745 - z = x13746 - z = x13747 - z = x13748 - z = x13749 - z = x13750 - z = x13751 - z = x13752 - z = x13753 - z = x13754 - z = x13755 - z = x13756 - z = x13757 - z = x13758 - z = x13759 - z = x13760 - z = x13761 - z = x13762 - z = x13763 - z = x13764 - z = x13765 - z = x13766 - z = x13767 - z = x13768 - z = x13769 - z = x13770 - z = x13771 - z = x13772 - z = x13773 - z = x13774 - z = x13775 - z = x13776 - z = x13777 - z = x13778 - z = x13779 - z = x13780 - z = x13781 - z = x13782 - z = x13783 - z = x13784 - z = x13785 - z = x13786 - z = x13787 - z = x13788 - z = x13789 - z = x13790 - z = x13791 - z = x13792 - z = x13793 - z = x13794 - z = x13795 - z = x13796 - z = x13797 - z = x13798 - z = x13799 - z = x13800 - z = x13801 - z = x13802 - z = x13803 - z = x13804 - z = x13805 - z = x13806 - z = x13807 - z = x13808 - z = x13809 - z = x13810 - z = x13811 - z = x13812 - z = x13813 - z = x13814 - z = x13815 - z = x13816 - z = x13817 - z = x13818 - z = x13819 - z = x13820 - z = x13821 - z = x13822 - z = x13823 - z = x13824 - z = x13825 - z = x13826 - z = x13827 - z = x13828 - z = x13829 - z = x13830 - z = x13831 - z = x13832 - z = x13833 - z = x13834 - z = x13835 - z = x13836 - z = x13837 - z = x13838 - z = x13839 - z = x13840 - z = x13841 - z = x13842 - z = x13843 - z = x13844 - z = x13845 - z = x13846 - z = x13847 - z = x13848 - z = x13849 - z = x13850 - z = x13851 - z = x13852 - z = x13853 - z = x13854 - z = x13855 - z = x13856 - z = x13857 - z = x13858 - z = x13859 - z = x13860 - z = x13861 - z = x13862 - z = x13863 - z = x13864 - z = x13865 - z = x13866 - z = x13867 - z = x13868 - z = x13869 - z = x13870 - z = x13871 - z = x13872 - z = x13873 - z = x13874 - z = x13875 - z = x13876 - z = x13877 - z = x13878 - z = x13879 - z = x13880 - z = x13881 - z = x13882 - z = x13883 - z = x13884 - z = x13885 - z = x13886 - z = x13887 - z = x13888 - z = x13889 - z = x13890 - z = x13891 - z = x13892 - z = x13893 - z = x13894 - z = x13895 - z = x13896 - z = x13897 - z = x13898 - z = x13899 - z = x13900 - z = x13901 - z = x13902 - z = x13903 - z = x13904 - z = x13905 - z = x13906 - z = x13907 - z = x13908 - z = x13909 - z = x13910 - z = x13911 - z = x13912 - z = x13913 - z = x13914 - z = x13915 - z = x13916 - z = x13917 - z = x13918 - z = x13919 - z = x13920 - z = x13921 - z = x13922 - z = x13923 - z = x13924 - z = x13925 - z = x13926 - z = x13927 - z = x13928 - z = x13929 - z = x13930 - z = x13931 - z = x13932 - z = x13933 - z = x13934 - z = x13935 - z = x13936 - z = x13937 - z = x13938 - z = x13939 - z = x13940 - z = x13941 - z = x13942 - z = x13943 - z = x13944 - z = x13945 - z = x13946 - z = x13947 - z = x13948 - z = x13949 - z = x13950 - z = x13951 - z = x13952 - z = x13953 - z = x13954 - z = x13955 - z = x13956 - z = x13957 - z = x13958 - z = x13959 - z = x13960 - z = x13961 - z = x13962 - z = x13963 - z = x13964 - z = x13965 - z = x13966 - z = x13967 - z = x13968 - z = x13969 - z = x13970 - z = x13971 - z = x13972 - z = x13973 - z = x13974 - z = x13975 - z = x13976 - z = x13977 - z = x13978 - z = x13979 - z = x13980 - z = x13981 - z = x13982 - z = x13983 - z = x13984 - z = x13985 - z = x13986 - z = x13987 - z = x13988 - z = x13989 - z = x13990 - z = x13991 - z = x13992 - z = x13993 - z = x13994 - z = x13995 - z = x13996 - z = x13997 - z = x13998 - z = x13999 - z = x14000 - z = x14001 - z = x14002 - z = x14003 - z = x14004 - z = x14005 - z = x14006 - z = x14007 - z = x14008 - z = x14009 - z = x14010 - z = x14011 - z = x14012 - z = x14013 - z = x14014 - z = x14015 - z = x14016 - z = x14017 - z = x14018 - z = x14019 - z = x14020 - z = x14021 - z = x14022 - z = x14023 - z = x14024 - z = x14025 - z = x14026 - z = x14027 - z = x14028 - z = x14029 - z = x14030 - z = x14031 - z = x14032 - z = x14033 - z = x14034 - z = x14035 - z = x14036 - z = x14037 - z = x14038 - z = x14039 - z = x14040 - z = x14041 - z = x14042 - z = x14043 - z = x14044 - z = x14045 - z = x14046 - z = x14047 - z = x14048 - z = x14049 - z = x14050 - z = x14051 - z = x14052 - z = x14053 - z = x14054 - z = x14055 - z = x14056 - z = x14057 - z = x14058 - z = x14059 - z = x14060 - z = x14061 - z = x14062 - z = x14063 - z = x14064 - z = x14065 - z = x14066 - z = x14067 - z = x14068 - z = x14069 - z = x14070 - z = x14071 - z = x14072 - z = x14073 - z = x14074 - z = x14075 - z = x14076 - z = x14077 - z = x14078 - z = x14079 - z = x14080 - z = x14081 - z = x14082 - z = x14083 - z = x14084 - z = x14085 - z = x14086 - z = x14087 - z = x14088 - z = x14089 - z = x14090 - z = x14091 - z = x14092 - z = x14093 - z = x14094 - z = x14095 - z = x14096 - z = x14097 - z = x14098 - z = x14099 - z = x14100 - z = x14101 - z = x14102 - z = x14103 - z = x14104 - z = x14105 - z = x14106 - z = x14107 - z = x14108 - z = x14109 - z = x14110 - z = x14111 - z = x14112 - z = x14113 - z = x14114 - z = x14115 - z = x14116 - z = x14117 - z = x14118 - z = x14119 - z = x14120 - z = x14121 - z = x14122 - z = x14123 - z = x14124 - z = x14125 - z = x14126 - z = x14127 - z = x14128 - z = x14129 - z = x14130 - z = x14131 - z = x14132 - z = x14133 - z = x14134 - z = x14135 - z = x14136 - z = x14137 - z = x14138 - z = x14139 - z = x14140 - z = x14141 - z = x14142 - z = x14143 - z = x14144 - z = x14145 - z = x14146 - z = x14147 - z = x14148 - z = x14149 - z = x14150 - z = x14151 - z = x14152 - z = x14153 - z = x14154 - z = x14155 - z = x14156 - z = x14157 - z = x14158 - z = x14159 - z = x14160 - z = x14161 - z = x14162 - z = x14163 - z = x14164 - z = x14165 - z = x14166 - z = x14167 - z = x14168 - z = x14169 - z = x14170 - z = x14171 - z = x14172 - z = x14173 - z = x14174 - z = x14175 - z = x14176 - z = x14177 - z = x14178 - z = x14179 - z = x14180 - z = x14181 - z = x14182 - z = x14183 - z = x14184 - z = x14185 - z = x14186 - z = x14187 - z = x14188 - z = x14189 - z = x14190 - z = x14191 - z = x14192 - z = x14193 - z = x14194 - z = x14195 - z = x14196 - z = x14197 - z = x14198 - z = x14199 - z = x14200 - z = x14201 - z = x14202 - z = x14203 - z = x14204 - z = x14205 - z = x14206 - z = x14207 - z = x14208 - z = x14209 - z = x14210 - z = x14211 - z = x14212 - z = x14213 - z = x14214 - z = x14215 - z = x14216 - z = x14217 - z = x14218 - z = x14219 - z = x14220 - z = x14221 - z = x14222 - z = x14223 - z = x14224 - z = x14225 - z = x14226 - z = x14227 - z = x14228 - z = x14229 - z = x14230 - z = x14231 - z = x14232 - z = x14233 - z = x14234 - z = x14235 - z = x14236 - z = x14237 - z = x14238 - z = x14239 - z = x14240 - z = x14241 - z = x14242 - z = x14243 - z = x14244 - z = x14245 - z = x14246 - z = x14247 - z = x14248 - z = x14249 - z = x14250 - z = x14251 - z = x14252 - z = x14253 - z = x14254 - z = x14255 - z = x14256 - z = x14257 - z = x14258 - z = x14259 - z = x14260 - z = x14261 - z = x14262 - z = x14263 - z = x14264 - z = x14265 - z = x14266 - z = x14267 - z = x14268 - z = x14269 - z = x14270 - z = x14271 - z = x14272 - z = x14273 - z = x14274 - z = x14275 - z = x14276 - z = x14277 - z = x14278 - z = x14279 - z = x14280 - z = x14281 - z = x14282 - z = x14283 - z = x14284 - z = x14285 - z = x14286 - z = x14287 - z = x14288 - z = x14289 - z = x14290 - z = x14291 - z = x14292 - z = x14293 - z = x14294 - z = x14295 - z = x14296 - z = x14297 - z = x14298 - z = x14299 - z = x14300 - z = x14301 - z = x14302 - z = x14303 - z = x14304 - z = x14305 - z = x14306 - z = x14307 - z = x14308 - z = x14309 - z = x14310 - z = x14311 - z = x14312 - z = x14313 - z = x14314 - z = x14315 - z = x14316 - z = x14317 - z = x14318 - z = x14319 - z = x14320 - z = x14321 - z = x14322 - z = x14323 - z = x14324 - z = x14325 - z = x14326 - z = x14327 - z = x14328 - z = x14329 - z = x14330 - z = x14331 - z = x14332 - z = x14333 - z = x14334 - z = x14335 - z = x14336 - z = x14337 - z = x14338 - z = x14339 - z = x14340 - z = x14341 - z = x14342 - z = x14343 - z = x14344 - z = x14345 - z = x14346 - z = x14347 - z = x14348 - z = x14349 - z = x14350 - z = x14351 - z = x14352 - z = x14353 - z = x14354 - z = x14355 - z = x14356 - z = x14357 - z = x14358 - z = x14359 - z = x14360 - z = x14361 - z = x14362 - z = x14363 - z = x14364 - z = x14365 - z = x14366 - z = x14367 - z = x14368 - z = x14369 - z = x14370 - z = x14371 - z = x14372 - z = x14373 - z = x14374 - z = x14375 - z = x14376 - z = x14377 - z = x14378 - z = x14379 - z = x14380 - z = x14381 - z = x14382 - z = x14383 - z = x14384 - z = x14385 - z = x14386 - z = x14387 - z = x14388 - z = x14389 - z = x14390 - z = x14391 - z = x14392 - z = x14393 - z = x14394 - z = x14395 - z = x14396 - z = x14397 - z = x14398 - z = x14399 - z = x14400 - z = x14401 - z = x14402 - z = x14403 - z = x14404 - z = x14405 - z = x14406 - z = x14407 - z = x14408 - z = x14409 - z = x14410 - z = x14411 - z = x14412 - z = x14413 - z = x14414 - z = x14415 - z = x14416 - z = x14417 - z = x14418 - z = x14419 - z = x14420 - z = x14421 - z = x14422 - z = x14423 - z = x14424 - z = x14425 - z = x14426 - z = x14427 - z = x14428 - z = x14429 - z = x14430 - z = x14431 - z = x14432 - z = x14433 - z = x14434 - z = x14435 - z = x14436 - z = x14437 - z = x14438 - z = x14439 - z = x14440 - z = x14441 - z = x14442 - z = x14443 - z = x14444 - z = x14445 - z = x14446 - z = x14447 - z = x14448 - z = x14449 - z = x14450 - z = x14451 - z = x14452 - z = x14453 - z = x14454 - z = x14455 - z = x14456 - z = x14457 - z = x14458 - z = x14459 - z = x14460 - z = x14461 - z = x14462 - z = x14463 - z = x14464 - z = x14465 - z = x14466 - z = x14467 - z = x14468 - z = x14469 - z = x14470 - z = x14471 - z = x14472 - z = x14473 - z = x14474 - z = x14475 - z = x14476 - z = x14477 - z = x14478 - z = x14479 - z = x14480 - z = x14481 - z = x14482 - z = x14483 - z = x14484 - z = x14485 - z = x14486 - z = x14487 - z = x14488 - z = x14489 - z = x14490 - z = x14491 - z = x14492 - z = x14493 - z = x14494 - z = x14495 - z = x14496 - z = x14497 - z = x14498 - z = x14499 - z = x14500 - z = x14501 - z = x14502 - z = x14503 - z = x14504 - z = x14505 - z = x14506 - z = x14507 - z = x14508 - z = x14509 - z = x14510 - z = x14511 - z = x14512 - z = x14513 - z = x14514 - z = x14515 - z = x14516 - z = x14517 - z = x14518 - z = x14519 - z = x14520 - z = x14521 - z = x14522 - z = x14523 - z = x14524 - z = x14525 - z = x14526 - z = x14527 - z = x14528 - z = x14529 - z = x14530 - z = x14531 - z = x14532 - z = x14533 - z = x14534 - z = x14535 - z = x14536 - z = x14537 - z = x14538 - z = x14539 - z = x14540 - z = x14541 - z = x14542 - z = x14543 - z = x14544 - z = x14545 - z = x14546 - z = x14547 - z = x14548 - z = x14549 - z = x14550 - z = x14551 - z = x14552 - z = x14553 - z = x14554 - z = x14555 - z = x14556 - z = x14557 - z = x14558 - z = x14559 - z = x14560 - z = x14561 - z = x14562 - z = x14563 - z = x14564 - z = x14565 - z = x14566 - z = x14567 - z = x14568 - z = x14569 - z = x14570 - z = x14571 - z = x14572 - z = x14573 - z = x14574 - z = x14575 - z = x14576 - z = x14577 - z = x14578 - z = x14579 - z = x14580 - z = x14581 - z = x14582 - z = x14583 - z = x14584 - z = x14585 - z = x14586 - z = x14587 - z = x14588 - z = x14589 - z = x14590 - z = x14591 - z = x14592 - z = x14593 - z = x14594 - z = x14595 - z = x14596 - z = x14597 - z = x14598 - z = x14599 - z = x14600 - z = x14601 - z = x14602 - z = x14603 - z = x14604 - z = x14605 - z = x14606 - z = x14607 - z = x14608 - z = x14609 - z = x14610 - z = x14611 - z = x14612 - z = x14613 - z = x14614 - z = x14615 - z = x14616 - z = x14617 - z = x14618 - z = x14619 - z = x14620 - z = x14621 - z = x14622 - z = x14623 - z = x14624 - z = x14625 - z = x14626 - z = x14627 - z = x14628 - z = x14629 - z = x14630 - z = x14631 - z = x14632 - z = x14633 - z = x14634 - z = x14635 - z = x14636 - z = x14637 - z = x14638 - z = x14639 - z = x14640 - z = x14641 - z = x14642 - z = x14643 - z = x14644 - z = x14645 - z = x14646 - z = x14647 - z = x14648 - z = x14649 - z = x14650 - z = x14651 - z = x14652 - z = x14653 - z = x14654 - z = x14655 - z = x14656 - z = x14657 - z = x14658 - z = x14659 - z = x14660 - z = x14661 - z = x14662 - z = x14663 - z = x14664 - z = x14665 - z = x14666 - z = x14667 - z = x14668 - z = x14669 - z = x14670 - z = x14671 - z = x14672 - z = x14673 - z = x14674 - z = x14675 - z = x14676 - z = x14677 - z = x14678 - z = x14679 - z = x14680 - z = x14681 - z = x14682 - z = x14683 - z = x14684 - z = x14685 - z = x14686 - z = x14687 - z = x14688 - z = x14689 - z = x14690 - z = x14691 - z = x14692 - z = x14693 - z = x14694 - z = x14695 - z = x14696 - z = x14697 - z = x14698 - z = x14699 - z = x14700 - z = x14701 - z = x14702 - z = x14703 - z = x14704 - z = x14705 - z = x14706 - z = x14707 - z = x14708 - z = x14709 - z = x14710 - z = x14711 - z = x14712 - z = x14713 - z = x14714 - z = x14715 - z = x14716 - z = x14717 - z = x14718 - z = x14719 - z = x14720 - z = x14721 - z = x14722 - z = x14723 - z = x14724 - z = x14725 - z = x14726 - z = x14727 - z = x14728 - z = x14729 - z = x14730 - z = x14731 - z = x14732 - z = x14733 - z = x14734 - z = x14735 - z = x14736 - z = x14737 - z = x14738 - z = x14739 - z = x14740 - z = x14741 - z = x14742 - z = x14743 - z = x14744 - z = x14745 - z = x14746 - z = x14747 - z = x14748 - z = x14749 - z = x14750 - z = x14751 - z = x14752 - z = x14753 - z = x14754 - z = x14755 - z = x14756 - z = x14757 - z = x14758 - z = x14759 - z = x14760 - z = x14761 - z = x14762 - z = x14763 - z = x14764 - z = x14765 - z = x14766 - z = x14767 - z = x14768 - z = x14769 - z = x14770 - z = x14771 - z = x14772 - z = x14773 - z = x14774 - z = x14775 - z = x14776 - z = x14777 - z = x14778 - z = x14779 - z = x14780 - z = x14781 - z = x14782 - z = x14783 - z = x14784 - z = x14785 - z = x14786 - z = x14787 - z = x14788 - z = x14789 - z = x14790 - z = x14791 - z = x14792 - z = x14793 - z = x14794 - z = x14795 - z = x14796 - z = x14797 - z = x14798 - z = x14799 - z = x14800 - z = x14801 - z = x14802 - z = x14803 - z = x14804 - z = x14805 - z = x14806 - z = x14807 - z = x14808 - z = x14809 - z = x14810 - z = x14811 - z = x14812 - z = x14813 - z = x14814 - z = x14815 - z = x14816 - z = x14817 - z = x14818 - z = x14819 - z = x14820 - z = x14821 - z = x14822 - z = x14823 - z = x14824 - z = x14825 - z = x14826 - z = x14827 - z = x14828 - z = x14829 - z = x14830 - z = x14831 - z = x14832 - z = x14833 - z = x14834 - z = x14835 - z = x14836 - z = x14837 - z = x14838 - z = x14839 - z = x14840 - z = x14841 - z = x14842 - z = x14843 - z = x14844 - z = x14845 - z = x14846 - z = x14847 - z = x14848 - z = x14849 - z = x14850 - z = x14851 - z = x14852 - z = x14853 - z = x14854 - z = x14855 - z = x14856 - z = x14857 - z = x14858 - z = x14859 - z = x14860 - z = x14861 - z = x14862 - z = x14863 - z = x14864 - z = x14865 - z = x14866 - z = x14867 - z = x14868 - z = x14869 - z = x14870 - z = x14871 - z = x14872 - z = x14873 - z = x14874 - z = x14875 - z = x14876 - z = x14877 - z = x14878 - z = x14879 - z = x14880 - z = x14881 - z = x14882 - z = x14883 - z = x14884 - z = x14885 - z = x14886 - z = x14887 - z = x14888 - z = x14889 - z = x14890 - z = x14891 - z = x14892 - z = x14893 - z = x14894 - z = x14895 - z = x14896 - z = x14897 - z = x14898 - z = x14899 - z = x14900 - z = x14901 - z = x14902 - z = x14903 - z = x14904 - z = x14905 - z = x14906 - z = x14907 - z = x14908 - z = x14909 - z = x14910 - z = x14911 - z = x14912 - z = x14913 - z = x14914 - z = x14915 - z = x14916 - z = x14917 - z = x14918 - z = x14919 - z = x14920 - z = x14921 - z = x14922 - z = x14923 - z = x14924 - z = x14925 - z = x14926 - z = x14927 - z = x14928 - z = x14929 - z = x14930 - z = x14931 - z = x14932 - z = x14933 - z = x14934 - z = x14935 - z = x14936 - z = x14937 - z = x14938 - z = x14939 - z = x14940 - z = x14941 - z = x14942 - z = x14943 - z = x14944 - z = x14945 - z = x14946 - z = x14947 - z = x14948 - z = x14949 - z = x14950 - z = x14951 - z = x14952 - z = x14953 - z = x14954 - z = x14955 - z = x14956 - z = x14957 - z = x14958 - z = x14959 - z = x14960 - z = x14961 - z = x14962 - z = x14963 - z = x14964 - z = x14965 - z = x14966 - z = x14967 - z = x14968 - z = x14969 - z = x14970 - z = x14971 - z = x14972 - z = x14973 - z = x14974 - z = x14975 - z = x14976 - z = x14977 - z = x14978 - z = x14979 - z = x14980 - z = x14981 - z = x14982 - z = x14983 - z = x14984 - z = x14985 - z = x14986 - z = x14987 - z = x14988 - z = x14989 - z = x14990 - z = x14991 - z = x14992 - z = x14993 - z = x14994 - z = x14995 - z = x14996 - z = x14997 - z = x14998 - z = x14999 - z = x15000 - z = x15001 - z = x15002 - z = x15003 - z = x15004 - z = x15005 - z = x15006 - z = x15007 - z = x15008 - z = x15009 - z = x15010 - z = x15011 - z = x15012 - z = x15013 - z = x15014 - z = x15015 - z = x15016 - z = x15017 - z = x15018 - z = x15019 - z = x15020 - z = x15021 - z = x15022 - z = x15023 - z = x15024 - z = x15025 - z = x15026 - z = x15027 - z = x15028 - z = x15029 - z = x15030 - z = x15031 - z = x15032 - z = x15033 - z = x15034 - z = x15035 - z = x15036 - z = x15037 - z = x15038 - z = x15039 - z = x15040 - z = x15041 - z = x15042 - z = x15043 - z = x15044 - z = x15045 - z = x15046 - z = x15047 - z = x15048 - z = x15049 - z = x15050 - z = x15051 - z = x15052 - z = x15053 - z = x15054 - z = x15055 - z = x15056 - z = x15057 - z = x15058 - z = x15059 - z = x15060 - z = x15061 - z = x15062 - z = x15063 - z = x15064 - z = x15065 - z = x15066 - z = x15067 - z = x15068 - z = x15069 - z = x15070 - z = x15071 - z = x15072 - z = x15073 - z = x15074 - z = x15075 - z = x15076 - z = x15077 - z = x15078 - z = x15079 - z = x15080 - z = x15081 - z = x15082 - z = x15083 - z = x15084 - z = x15085 - z = x15086 - z = x15087 - z = x15088 - z = x15089 - z = x15090 - z = x15091 - z = x15092 - z = x15093 - z = x15094 - z = x15095 - z = x15096 - z = x15097 - z = x15098 - z = x15099 - z = x15100 - z = x15101 - z = x15102 - z = x15103 - z = x15104 - z = x15105 - z = x15106 - z = x15107 - z = x15108 - z = x15109 - z = x15110 - z = x15111 - z = x15112 - z = x15113 - z = x15114 - z = x15115 - z = x15116 - z = x15117 - z = x15118 - z = x15119 - z = x15120 - z = x15121 - z = x15122 - z = x15123 - z = x15124 - z = x15125 - z = x15126 - z = x15127 - z = x15128 - z = x15129 - z = x15130 - z = x15131 - z = x15132 - z = x15133 - z = x15134 - z = x15135 - z = x15136 - z = x15137 - z = x15138 - z = x15139 - z = x15140 - z = x15141 - z = x15142 - z = x15143 - z = x15144 - z = x15145 - z = x15146 - z = x15147 - z = x15148 - z = x15149 - z = x15150 - z = x15151 - z = x15152 - z = x15153 - z = x15154 - z = x15155 - z = x15156 - z = x15157 - z = x15158 - z = x15159 - z = x15160 - z = x15161 - z = x15162 - z = x15163 - z = x15164 - z = x15165 - z = x15166 - z = x15167 - z = x15168 - z = x15169 - z = x15170 - z = x15171 - z = x15172 - z = x15173 - z = x15174 - z = x15175 - z = x15176 - z = x15177 - z = x15178 - z = x15179 - z = x15180 - z = x15181 - z = x15182 - z = x15183 - z = x15184 - z = x15185 - z = x15186 - z = x15187 - z = x15188 - z = x15189 - z = x15190 - z = x15191 - z = x15192 - z = x15193 - z = x15194 - z = x15195 - z = x15196 - z = x15197 - z = x15198 - z = x15199 - z = x15200 - z = x15201 - z = x15202 - z = x15203 - z = x15204 - z = x15205 - z = x15206 - z = x15207 - z = x15208 - z = x15209 - z = x15210 - z = x15211 - z = x15212 - z = x15213 - z = x15214 - z = x15215 - z = x15216 - z = x15217 - z = x15218 - z = x15219 - z = x15220 - z = x15221 - z = x15222 - z = x15223 - z = x15224 - z = x15225 - z = x15226 - z = x15227 - z = x15228 - z = x15229 - z = x15230 - z = x15231 - z = x15232 - z = x15233 - z = x15234 - z = x15235 - z = x15236 - z = x15237 - z = x15238 - z = x15239 - z = x15240 - z = x15241 - z = x15242 - z = x15243 - z = x15244 - z = x15245 - z = x15246 - z = x15247 - z = x15248 - z = x15249 - z = x15250 - z = x15251 - z = x15252 - z = x15253 - z = x15254 - z = x15255 - z = x15256 - z = x15257 - z = x15258 - z = x15259 - z = x15260 - z = x15261 - z = x15262 - z = x15263 - z = x15264 - z = x15265 - z = x15266 - z = x15267 - z = x15268 - z = x15269 - z = x15270 - z = x15271 - z = x15272 - z = x15273 - z = x15274 - z = x15275 - z = x15276 - z = x15277 - z = x15278 - z = x15279 - z = x15280 - z = x15281 - z = x15282 - z = x15283 - z = x15284 - z = x15285 - z = x15286 - z = x15287 - z = x15288 - z = x15289 - z = x15290 - z = x15291 - z = x15292 - z = x15293 - z = x15294 - z = x15295 - z = x15296 - z = x15297 - z = x15298 - z = x15299 - z = x15300 - z = x15301 - z = x15302 - z = x15303 - z = x15304 - z = x15305 - z = x15306 - z = x15307 - z = x15308 - z = x15309 - z = x15310 - z = x15311 - z = x15312 - z = x15313 - z = x15314 - z = x15315 - z = x15316 - z = x15317 - z = x15318 - z = x15319 - z = x15320 - z = x15321 - z = x15322 - z = x15323 - z = x15324 - z = x15325 - z = x15326 - z = x15327 - z = x15328 - z = x15329 - z = x15330 - z = x15331 - z = x15332 - z = x15333 - z = x15334 - z = x15335 - z = x15336 - z = x15337 - z = x15338 - z = x15339 - z = x15340 - z = x15341 - z = x15342 - z = x15343 - z = x15344 - z = x15345 - z = x15346 - z = x15347 - z = x15348 - z = x15349 - z = x15350 - z = x15351 - z = x15352 - z = x15353 - z = x15354 - z = x15355 - z = x15356 - z = x15357 - z = x15358 - z = x15359 - z = x15360 - z = x15361 - z = x15362 - z = x15363 - z = x15364 - z = x15365 - z = x15366 - z = x15367 - z = x15368 - z = x15369 - z = x15370 - z = x15371 - z = x15372 - z = x15373 - z = x15374 - z = x15375 - z = x15376 - z = x15377 - z = x15378 - z = x15379 - z = x15380 - z = x15381 - z = x15382 - z = x15383 - z = x15384 - z = x15385 - z = x15386 - z = x15387 - z = x15388 - z = x15389 - z = x15390 - z = x15391 - z = x15392 - z = x15393 - z = x15394 - z = x15395 - z = x15396 - z = x15397 - z = x15398 - z = x15399 - z = x15400 - z = x15401 - z = x15402 - z = x15403 - z = x15404 - z = x15405 - z = x15406 - z = x15407 - z = x15408 - z = x15409 - z = x15410 - z = x15411 - z = x15412 - z = x15413 - z = x15414 - z = x15415 - z = x15416 - z = x15417 - z = x15418 - z = x15419 - z = x15420 - z = x15421 - z = x15422 - z = x15423 - z = x15424 - z = x15425 - z = x15426 - z = x15427 - z = x15428 - z = x15429 - z = x15430 - z = x15431 - z = x15432 - z = x15433 - z = x15434 - z = x15435 - z = x15436 - z = x15437 - z = x15438 - z = x15439 - z = x15440 - z = x15441 - z = x15442 - z = x15443 - z = x15444 - z = x15445 - z = x15446 - z = x15447 - z = x15448 - z = x15449 - z = x15450 - z = x15451 - z = x15452 - z = x15453 - z = x15454 - z = x15455 - z = x15456 - z = x15457 - z = x15458 - z = x15459 - z = x15460 - z = x15461 - z = x15462 - z = x15463 - z = x15464 - z = x15465 - z = x15466 - z = x15467 - z = x15468 - z = x15469 - z = x15470 - z = x15471 - z = x15472 - z = x15473 - z = x15474 - z = x15475 - z = x15476 - z = x15477 - z = x15478 - z = x15479 - z = x15480 - z = x15481 - z = x15482 - z = x15483 - z = x15484 - z = x15485 - z = x15486 - z = x15487 - z = x15488 - z = x15489 - z = x15490 - z = x15491 - z = x15492 - z = x15493 - z = x15494 - z = x15495 - z = x15496 - z = x15497 - z = x15498 - z = x15499 - z = x15500 - z = x15501 - z = x15502 - z = x15503 - z = x15504 - z = x15505 - z = x15506 - z = x15507 - z = x15508 - z = x15509 - z = x15510 - z = x15511 - z = x15512 - z = x15513 - z = x15514 - z = x15515 - z = x15516 - z = x15517 - z = x15518 - z = x15519 - z = x15520 - z = x15521 - z = x15522 - z = x15523 - z = x15524 - z = x15525 - z = x15526 - z = x15527 - z = x15528 - z = x15529 - z = x15530 - z = x15531 - z = x15532 - z = x15533 - z = x15534 - z = x15535 - z = x15536 - z = x15537 - z = x15538 - z = x15539 - z = x15540 - z = x15541 - z = x15542 - z = x15543 - z = x15544 - z = x15545 - z = x15546 - z = x15547 - z = x15548 - z = x15549 - z = x15550 - z = x15551 - z = x15552 - z = x15553 - z = x15554 - z = x15555 - z = x15556 - z = x15557 - z = x15558 - z = x15559 - z = x15560 - z = x15561 - z = x15562 - z = x15563 - z = x15564 - z = x15565 - z = x15566 - z = x15567 - z = x15568 - z = x15569 - z = x15570 - z = x15571 - z = x15572 - z = x15573 - z = x15574 - z = x15575 - z = x15576 - z = x15577 - z = x15578 - z = x15579 - z = x15580 - z = x15581 - z = x15582 - z = x15583 - z = x15584 - z = x15585 - z = x15586 - z = x15587 - z = x15588 - z = x15589 - z = x15590 - z = x15591 - z = x15592 - z = x15593 - z = x15594 - z = x15595 - z = x15596 - z = x15597 - z = x15598 - z = x15599 - z = x15600 - z = x15601 - z = x15602 - z = x15603 - z = x15604 - z = x15605 - z = x15606 - z = x15607 - z = x15608 - z = x15609 - z = x15610 - z = x15611 - z = x15612 - z = x15613 - z = x15614 - z = x15615 - z = x15616 - z = x15617 - z = x15618 - z = x15619 - z = x15620 - z = x15621 - z = x15622 - z = x15623 - z = x15624 - z = x15625 - z = x15626 - z = x15627 - z = x15628 - z = x15629 - z = x15630 - z = x15631 - z = x15632 - z = x15633 - z = x15634 - z = x15635 - z = x15636 - z = x15637 - z = x15638 - z = x15639 - z = x15640 - z = x15641 - z = x15642 - z = x15643 - z = x15644 - z = x15645 - z = x15646 - z = x15647 - z = x15648 - z = x15649 - z = x15650 - z = x15651 - z = x15652 - z = x15653 - z = x15654 - z = x15655 - z = x15656 - z = x15657 - z = x15658 - z = x15659 - z = x15660 - z = x15661 - z = x15662 - z = x15663 - z = x15664 - z = x15665 - z = x15666 - z = x15667 - z = x15668 - z = x15669 - z = x15670 - z = x15671 - z = x15672 - z = x15673 - z = x15674 - z = x15675 - z = x15676 - z = x15677 - z = x15678 - z = x15679 - z = x15680 - z = x15681 - z = x15682 - z = x15683 - z = x15684 - z = x15685 - z = x15686 - z = x15687 - z = x15688 - z = x15689 - z = x15690 - z = x15691 - z = x15692 - z = x15693 - z = x15694 - z = x15695 - z = x15696 - z = x15697 - z = x15698 - z = x15699 - z = x15700 - z = x15701 - z = x15702 - z = x15703 - z = x15704 - z = x15705 - z = x15706 - z = x15707 - z = x15708 - z = x15709 - z = x15710 - z = x15711 - z = x15712 - z = x15713 - z = x15714 - z = x15715 - z = x15716 - z = x15717 - z = x15718 - z = x15719 - z = x15720 - z = x15721 - z = x15722 - z = x15723 - z = x15724 - z = x15725 - z = x15726 - z = x15727 - z = x15728 - z = x15729 - z = x15730 - z = x15731 - z = x15732 - z = x15733 - z = x15734 - z = x15735 - z = x15736 - z = x15737 - z = x15738 - z = x15739 - z = x15740 - z = x15741 - z = x15742 - z = x15743 - z = x15744 - z = x15745 - z = x15746 - z = x15747 - z = x15748 - z = x15749 - z = x15750 - z = x15751 - z = x15752 - z = x15753 - z = x15754 - z = x15755 - z = x15756 - z = x15757 - z = x15758 - z = x15759 - z = x15760 - z = x15761 - z = x15762 - z = x15763 - z = x15764 - z = x15765 - z = x15766 - z = x15767 - z = x15768 - z = x15769 - z = x15770 - z = x15771 - z = x15772 - z = x15773 - z = x15774 - z = x15775 - z = x15776 - z = x15777 - z = x15778 - z = x15779 - z = x15780 - z = x15781 - z = x15782 - z = x15783 - z = x15784 - z = x15785 - z = x15786 - z = x15787 - z = x15788 - z = x15789 - z = x15790 - z = x15791 - z = x15792 - z = x15793 - z = x15794 - z = x15795 - z = x15796 - z = x15797 - z = x15798 - z = x15799 - z = x15800 - z = x15801 - z = x15802 - z = x15803 - z = x15804 - z = x15805 - z = x15806 - z = x15807 - z = x15808 - z = x15809 - z = x15810 - z = x15811 - z = x15812 - z = x15813 - z = x15814 - z = x15815 - z = x15816 - z = x15817 - z = x15818 - z = x15819 - z = x15820 - z = x15821 - z = x15822 - z = x15823 - z = x15824 - z = x15825 - z = x15826 - z = x15827 - z = x15828 - z = x15829 - z = x15830 - z = x15831 - z = x15832 - z = x15833 - z = x15834 - z = x15835 - z = x15836 - z = x15837 - z = x15838 - z = x15839 - z = x15840 - z = x15841 - z = x15842 - z = x15843 - z = x15844 - z = x15845 - z = x15846 - z = x15847 - z = x15848 - z = x15849 - z = x15850 - z = x15851 - z = x15852 - z = x15853 - z = x15854 - z = x15855 - z = x15856 - z = x15857 - z = x15858 - z = x15859 - z = x15860 - z = x15861 - z = x15862 - z = x15863 - z = x15864 - z = x15865 - z = x15866 - z = x15867 - z = x15868 - z = x15869 - z = x15870 - z = x15871 - z = x15872 - z = x15873 - z = x15874 - z = x15875 - z = x15876 - z = x15877 - z = x15878 - z = x15879 - z = x15880 - z = x15881 - z = x15882 - z = x15883 - z = x15884 - z = x15885 - z = x15886 - z = x15887 - z = x15888 - z = x15889 - z = x15890 - z = x15891 - z = x15892 - z = x15893 - z = x15894 - z = x15895 - z = x15896 - z = x15897 - z = x15898 - z = x15899 - z = x15900 - z = x15901 - z = x15902 - z = x15903 - z = x15904 - z = x15905 - z = x15906 - z = x15907 - z = x15908 - z = x15909 - z = x15910 - z = x15911 - z = x15912 - z = x15913 - z = x15914 - z = x15915 - z = x15916 - z = x15917 - z = x15918 - z = x15919 - z = x15920 - z = x15921 - z = x15922 - z = x15923 - z = x15924 - z = x15925 - z = x15926 - z = x15927 - z = x15928 - z = x15929 - z = x15930 - z = x15931 - z = x15932 - z = x15933 - z = x15934 - z = x15935 - z = x15936 - z = x15937 - z = x15938 - z = x15939 - z = x15940 - z = x15941 - z = x15942 - z = x15943 - z = x15944 - z = x15945 - z = x15946 - z = x15947 - z = x15948 - z = x15949 - z = x15950 - z = x15951 - z = x15952 - z = x15953 - z = x15954 - z = x15955 - z = x15956 - z = x15957 - z = x15958 - z = x15959 - z = x15960 - z = x15961 - z = x15962 - z = x15963 - z = x15964 - z = x15965 - z = x15966 - z = x15967 - z = x15968 - z = x15969 - z = x15970 - z = x15971 - z = x15972 - z = x15973 - z = x15974 - z = x15975 - z = x15976 - z = x15977 - z = x15978 - z = x15979 - z = x15980 - z = x15981 - z = x15982 - z = x15983 - z = x15984 - z = x15985 - z = x15986 - z = x15987 - z = x15988 - z = x15989 - z = x15990 - z = x15991 - z = x15992 - z = x15993 - z = x15994 - z = x15995 - z = x15996 - z = x15997 - z = x15998 - z = x15999 - z = x16000 - z = x16001 - z = x16002 - z = x16003 - z = x16004 - z = x16005 - z = x16006 - z = x16007 - z = x16008 - z = x16009 - z = x16010 - z = x16011 - z = x16012 - z = x16013 - z = x16014 - z = x16015 - z = x16016 - z = x16017 - z = x16018 - z = x16019 - z = x16020 - z = x16021 - z = x16022 - z = x16023 - z = x16024 - z = x16025 - z = x16026 - z = x16027 - z = x16028 - z = x16029 - z = x16030 - z = x16031 - z = x16032 - z = x16033 - z = x16034 - z = x16035 - z = x16036 - z = x16037 - z = x16038 - z = x16039 - z = x16040 - z = x16041 - z = x16042 - z = x16043 - z = x16044 - z = x16045 - z = x16046 - z = x16047 - z = x16048 - z = x16049 - z = x16050 - z = x16051 - z = x16052 - z = x16053 - z = x16054 - z = x16055 - z = x16056 - z = x16057 - z = x16058 - z = x16059 - z = x16060 - z = x16061 - z = x16062 - z = x16063 - z = x16064 - z = x16065 - z = x16066 - z = x16067 - z = x16068 - z = x16069 - z = x16070 - z = x16071 - z = x16072 - z = x16073 - z = x16074 - z = x16075 - z = x16076 - z = x16077 - z = x16078 - z = x16079 - z = x16080 - z = x16081 - z = x16082 - z = x16083 - z = x16084 - z = x16085 - z = x16086 - z = x16087 - z = x16088 - z = x16089 - z = x16090 - z = x16091 - z = x16092 - z = x16093 - z = x16094 - z = x16095 - z = x16096 - z = x16097 - z = x16098 - z = x16099 - z = x16100 - z = x16101 - z = x16102 - z = x16103 - z = x16104 - z = x16105 - z = x16106 - z = x16107 - z = x16108 - z = x16109 - z = x16110 - z = x16111 - z = x16112 - z = x16113 - z = x16114 - z = x16115 - z = x16116 - z = x16117 - z = x16118 - z = x16119 - z = x16120 - z = x16121 - z = x16122 - z = x16123 - z = x16124 - z = x16125 - z = x16126 - z = x16127 - z = x16128 - z = x16129 - z = x16130 - z = x16131 - z = x16132 - z = x16133 - z = x16134 - z = x16135 - z = x16136 - z = x16137 - z = x16138 - z = x16139 - z = x16140 - z = x16141 - z = x16142 - z = x16143 - z = x16144 - z = x16145 - z = x16146 - z = x16147 - z = x16148 - z = x16149 - z = x16150 - z = x16151 - z = x16152 - z = x16153 - z = x16154 - z = x16155 - z = x16156 - z = x16157 - z = x16158 - z = x16159 - z = x16160 - z = x16161 - z = x16162 - z = x16163 - z = x16164 - z = x16165 - z = x16166 - z = x16167 - z = x16168 - z = x16169 - z = x16170 - z = x16171 - z = x16172 - z = x16173 - z = x16174 - z = x16175 - z = x16176 - z = x16177 - z = x16178 - z = x16179 - z = x16180 - z = x16181 - z = x16182 - z = x16183 - z = x16184 - z = x16185 - z = x16186 - z = x16187 - z = x16188 - z = x16189 - z = x16190 - z = x16191 - z = x16192 - z = x16193 - z = x16194 - z = x16195 - z = x16196 - z = x16197 - z = x16198 - z = x16199 - z = x16200 - z = x16201 - z = x16202 - z = x16203 - z = x16204 - z = x16205 - z = x16206 - z = x16207 - z = x16208 - z = x16209 - z = x16210 - z = x16211 - z = x16212 - z = x16213 - z = x16214 - z = x16215 - z = x16216 - z = x16217 - z = x16218 - z = x16219 - z = x16220 - z = x16221 - z = x16222 - z = x16223 - z = x16224 - z = x16225 - z = x16226 - z = x16227 - z = x16228 - z = x16229 - z = x16230 - z = x16231 - z = x16232 - z = x16233 - z = x16234 - z = x16235 - z = x16236 - z = x16237 - z = x16238 - z = x16239 - z = x16240 - z = x16241 - z = x16242 - z = x16243 - z = x16244 - z = x16245 - z = x16246 - z = x16247 - z = x16248 - z = x16249 - z = x16250 - z = x16251 - z = x16252 - z = x16253 - z = x16254 - z = x16255 - z = x16256 - z = x16257 - z = x16258 - z = x16259 - z = x16260 - z = x16261 - z = x16262 - z = x16263 - z = x16264 - z = x16265 - z = x16266 - z = x16267 - z = x16268 - z = x16269 - z = x16270 - z = x16271 - z = x16272 - z = x16273 - z = x16274 - z = x16275 - z = x16276 - z = x16277 - z = x16278 - z = x16279 - z = x16280 - z = x16281 - z = x16282 - z = x16283 - z = x16284 - z = x16285 - z = x16286 - z = x16287 - z = x16288 - z = x16289 - z = x16290 - z = x16291 - z = x16292 - z = x16293 - z = x16294 - z = x16295 - z = x16296 - z = x16297 - z = x16298 - z = x16299 - z = x16300 - z = x16301 - z = x16302 - z = x16303 - z = x16304 - z = x16305 - z = x16306 - z = x16307 - z = x16308 - z = x16309 - z = x16310 - z = x16311 - z = x16312 - z = x16313 - z = x16314 - z = x16315 - z = x16316 - z = x16317 - z = x16318 - z = x16319 - z = x16320 - z = x16321 - z = x16322 - z = x16323 - z = x16324 - z = x16325 - z = x16326 - z = x16327 - z = x16328 - z = x16329 - z = x16330 - z = x16331 - z = x16332 - z = x16333 - z = x16334 - z = x16335 - z = x16336 - z = x16337 - z = x16338 - z = x16339 - z = x16340 - z = x16341 - z = x16342 - z = x16343 - z = x16344 - z = x16345 - z = x16346 - z = x16347 - z = x16348 - z = x16349 - z = x16350 - z = x16351 - z = x16352 - z = x16353 - z = x16354 - z = x16355 - z = x16356 - z = x16357 - z = x16358 - z = x16359 - z = x16360 - z = x16361 - z = x16362 - z = x16363 - z = x16364 - z = x16365 - z = x16366 - z = x16367 - z = x16368 - z = x16369 - z = x16370 - z = x16371 - z = x16372 - z = x16373 - z = x16374 - z = x16375 - z = x16376 - z = x16377 - z = x16378 - z = x16379 - z = x16380 - z = x16381 - z = x16382 - z = x16383 - z = x16384 - z = x16385 - z = x16386 - z = x16387 - z = x16388 - z = x16389 - z = x16390 - z = x16391 - z = x16392 - z = x16393 - z = x16394 - z = x16395 - z = x16396 - z = x16397 - z = x16398 - z = x16399 - z = x16400 - z = x16401 - z = x16402 - z = x16403 - z = x16404 - z = x16405 - z = x16406 - z = x16407 - z = x16408 - z = x16409 - z = x16410 - z = x16411 - z = x16412 - z = x16413 - z = x16414 - z = x16415 - z = x16416 - z = x16417 - z = x16418 - z = x16419 - z = x16420 - z = x16421 - z = x16422 - z = x16423 - z = x16424 - z = x16425 - z = x16426 - z = x16427 - z = x16428 - z = x16429 - z = x16430 - z = x16431 - z = x16432 - z = x16433 - z = x16434 - z = x16435 - z = x16436 - z = x16437 - z = x16438 - z = x16439 - z = x16440 - z = x16441 - z = x16442 - z = x16443 - z = x16444 - z = x16445 - z = x16446 - z = x16447 - z = x16448 - z = x16449 - z = x16450 - z = x16451 - z = x16452 - z = x16453 - z = x16454 - z = x16455 - z = x16456 - z = x16457 - z = x16458 - z = x16459 - z = x16460 - z = x16461 - z = x16462 - z = x16463 - z = x16464 - z = x16465 - z = x16466 - z = x16467 - z = x16468 - z = x16469 - z = x16470 - z = x16471 - z = x16472 - z = x16473 - z = x16474 - z = x16475 - z = x16476 - z = x16477 - z = x16478 - z = x16479 - z = x16480 + z1 = x1 + z2 = x2 + z3 = x3 + z4 = x4 + z5 = x5 + z6 = x6 + z7 = x7 + z8 = x8 + z9 = x9 + z10 = x10 + z11 = x11 + z12 = x12 + z13 = x13 + z14 = x14 + z15 = x15 + z16 = x16 + z17 = x17 + z18 = x18 + z19 = x19 + z20 = x20 + z21 = x21 + z22 = x22 + z23 = x23 + z24 = x24 + z25 = x25 + z26 = x26 + z27 = x27 + z28 = x28 + z29 = x29 + z30 = x30 + z31 = x31 + z32 = x32 + z33 = x33 + z34 = x34 + z35 = x35 + z36 = x36 + z37 = x37 + z38 = x38 + z39 = x39 + z40 = x40 + z41 = x41 + z42 = x42 + z43 = x43 + z44 = x44 + z45 = x45 + z46 = x46 + z47 = x47 + z48 = x48 + z49 = x49 + z50 = x50 + z51 = x51 + z52 = x52 + z53 = x53 + z54 = x54 + z55 = x55 + z56 = x56 + z57 = x57 + z58 = x58 + z59 = x59 + z60 = x60 + z61 = x61 + z62 = x62 + z63 = x63 + z64 = x64 + z65 = x65 + z66 = x66 + z67 = x67 + z68 = x68 + z69 = x69 + z70 = x70 + z71 = x71 + z72 = x72 + z73 = x73 + z74 = x74 + z75 = x75 + z76 = x76 + z77 = x77 + z78 = x78 + z79 = x79 + z80 = x80 + z81 = x81 + z82 = x82 + z83 = x83 + z84 = x84 + z85 = x85 + z86 = x86 + z87 = x87 + z88 = x88 + z89 = x89 + z90 = x90 + z91 = x91 + z92 = x92 + z93 = x93 + z94 = x94 + z95 = x95 + z96 = x96 + z97 = x97 + z98 = x98 + z99 = x99 + z100 = x100 + z101 = x101 + z102 = x102 + z103 = x103 + z104 = x104 + z105 = x105 + z106 = x106 + z107 = x107 + z108 = x108 + z109 = x109 + z110 = x110 + z111 = x111 + z112 = x112 + z113 = x113 + z114 = x114 + z115 = x115 + z116 = x116 + z117 = x117 + z118 = x118 + z119 = x119 + z120 = x120 + z121 = x121 + z122 = x122 + z123 = x123 + z124 = x124 + z125 = x125 + z126 = x126 + z127 = x127 + z128 = x128 + z129 = x129 + z130 = x130 + z131 = x131 + z132 = x132 + z133 = x133 + z134 = x134 + z135 = x135 + z136 = x136 + z137 = x137 + z138 = x138 + z139 = x139 + z140 = x140 + z141 = x141 + z142 = x142 + z143 = x143 + z144 = x144 + z145 = x145 + z146 = x146 + z147 = x147 + z148 = x148 + z149 = x149 + z150 = x150 + z151 = x151 + z152 = x152 + z153 = x153 + z154 = x154 + z155 = x155 + z156 = x156 + z157 = x157 + z158 = x158 + z159 = x159 + z160 = x160 + z161 = x161 + z162 = x162 + z163 = x163 + z164 = x164 + z165 = x165 + z166 = x166 + z167 = x167 + z168 = x168 + z169 = x169 + z170 = x170 + z171 = x171 + z172 = x172 + z173 = x173 + z174 = x174 + z175 = x175 + z176 = x176 + z177 = x177 + z178 = x178 + z179 = x179 + z180 = x180 + z181 = x181 + z182 = x182 + z183 = x183 + z184 = x184 + z185 = x185 + z186 = x186 + z187 = x187 + z188 = x188 + z189 = x189 + z190 = x190 + z191 = x191 + z192 = x192 + z193 = x193 + z194 = x194 + z195 = x195 + z196 = x196 + z197 = x197 + z198 = x198 + z199 = x199 + z200 = x200 + z201 = x201 + z202 = x202 + z203 = x203 + z204 = x204 + z205 = x205 + z206 = x206 + z207 = x207 + z208 = x208 + z209 = x209 + z210 = x210 + z211 = x211 + z212 = x212 + z213 = x213 + z214 = x214 + z215 = x215 + z216 = x216 + z217 = x217 + z218 = x218 + z219 = x219 + z220 = x220 + z221 = x221 + z222 = x222 + z223 = x223 + z224 = x224 + z225 = x225 + z226 = x226 + z227 = x227 + z228 = x228 + z229 = x229 + z230 = x230 + z231 = x231 + z232 = x232 + z233 = x233 + z234 = x234 + z235 = x235 + z236 = x236 + z237 = x237 + z238 = x238 + z239 = x239 + z240 = x240 + z241 = x241 + z242 = x242 + z243 = x243 + z244 = x244 + z245 = x245 + z246 = x246 + z247 = x247 + z248 = x248 + z249 = x249 + z250 = x250 + z251 = x251 + z252 = x252 + z253 = x253 + z254 = x254 + z255 = x255 + z256 = x256 + z257 = x257 + z258 = x258 + z259 = x259 + z260 = x260 + z261 = x261 + z262 = x262 + z263 = x263 + z264 = x264 + z265 = x265 + z266 = x266 + z267 = x267 + z268 = x268 + z269 = x269 + z270 = x270 + z271 = x271 + z272 = x272 + z273 = x273 + z274 = x274 + z275 = x275 + z276 = x276 + z277 = x277 + z278 = x278 + z279 = x279 + z280 = x280 + z281 = x281 + z282 = x282 + z283 = x283 + z284 = x284 + z285 = x285 + z286 = x286 + z287 = x287 + z288 = x288 + z289 = x289 + z290 = x290 + z291 = x291 + z292 = x292 + z293 = x293 + z294 = x294 + z295 = x295 + z296 = x296 + z297 = x297 + z298 = x298 + z299 = x299 + z300 = x300 + z301 = x301 + z302 = x302 + z303 = x303 + z304 = x304 + z305 = x305 + z306 = x306 + z307 = x307 + z308 = x308 + z309 = x309 + z310 = x310 + z311 = x311 + z312 = x312 + z313 = x313 + z314 = x314 + z315 = x315 + z316 = x316 + z317 = x317 + z318 = x318 + z319 = x319 + z320 = x320 + z321 = x321 + z322 = x322 + z323 = x323 + z324 = x324 + z325 = x325 + z326 = x326 + z327 = x327 + z328 = x328 + z329 = x329 + z330 = x330 + z331 = x331 + z332 = x332 + z333 = x333 + z334 = x334 + z335 = x335 + z336 = x336 + z337 = x337 + z338 = x338 + z339 = x339 + z340 = x340 + z341 = x341 + z342 = x342 + z343 = x343 + z344 = x344 + z345 = x345 + z346 = x346 + z347 = x347 + z348 = x348 + z349 = x349 + z350 = x350 + z351 = x351 + z352 = x352 + z353 = x353 + z354 = x354 + z355 = x355 + z356 = x356 + z357 = x357 + z358 = x358 + z359 = x359 + z360 = x360 + z361 = x361 + z362 = x362 + z363 = x363 + z364 = x364 + z365 = x365 + z366 = x366 + z367 = x367 + z368 = x368 + z369 = x369 + z370 = x370 + z371 = x371 + z372 = x372 + z373 = x373 + z374 = x374 + z375 = x375 + z376 = x376 + z377 = x377 + z378 = x378 + z379 = x379 + z380 = x380 + z381 = x381 + z382 = x382 + z383 = x383 + z384 = x384 + z385 = x385 + z386 = x386 + z387 = x387 + z388 = x388 + z389 = x389 + z390 = x390 + z391 = x391 + z392 = x392 + z393 = x393 + z394 = x394 + z395 = x395 + z396 = x396 + z397 = x397 + z398 = x398 + z399 = x399 + z400 = x400 + z401 = x401 + z402 = x402 + z403 = x403 + z404 = x404 + z405 = x405 + z406 = x406 + z407 = x407 + z408 = x408 + z409 = x409 + z410 = x410 + z411 = x411 + z412 = x412 + z413 = x413 + z414 = x414 + z415 = x415 + z416 = x416 + z417 = x417 + z418 = x418 + z419 = x419 + z420 = x420 + z421 = x421 + z422 = x422 + z423 = x423 + z424 = x424 + z425 = x425 + z426 = x426 + z427 = x427 + z428 = x428 + z429 = x429 + z430 = x430 + z431 = x431 + z432 = x432 + z433 = x433 + z434 = x434 + z435 = x435 + z436 = x436 + z437 = x437 + z438 = x438 + z439 = x439 + z440 = x440 + z441 = x441 + z442 = x442 + z443 = x443 + z444 = x444 + z445 = x445 + z446 = x446 + z447 = x447 + z448 = x448 + z449 = x449 + z450 = x450 + z451 = x451 + z452 = x452 + z453 = x453 + z454 = x454 + z455 = x455 + z456 = x456 + z457 = x457 + z458 = x458 + z459 = x459 + z460 = x460 + z461 = x461 + z462 = x462 + z463 = x463 + z464 = x464 + z465 = x465 + z466 = x466 + z467 = x467 + z468 = x468 + z469 = x469 + z470 = x470 + z471 = x471 + z472 = x472 + z473 = x473 + z474 = x474 + z475 = x475 + z476 = x476 + z477 = x477 + z478 = x478 + z479 = x479 + z480 = x480 + z481 = x481 + z482 = x482 + z483 = x483 + z484 = x484 + z485 = x485 + z486 = x486 + z487 = x487 + z488 = x488 + z489 = x489 + z490 = x490 + z491 = x491 + z492 = x492 + z493 = x493 + z494 = x494 + z495 = x495 + z496 = x496 + z497 = x497 + z498 = x498 + z499 = x499 + z500 = x500 + z501 = x501 + z502 = x502 + z503 = x503 + z504 = x504 + z505 = x505 + z506 = x506 + z507 = x507 + z508 = x508 + z509 = x509 + z510 = x510 + z511 = x511 + z512 = x512 + z513 = x513 + z514 = x514 + z515 = x515 + z516 = x516 + z517 = x517 + z518 = x518 + z519 = x519 + z520 = x520 + z521 = x521 + z522 = x522 + z523 = x523 + z524 = x524 + z525 = x525 + z526 = x526 + z527 = x527 + z528 = x528 + z529 = x529 + z530 = x530 + z531 = x531 + z532 = x532 + z533 = x533 + z534 = x534 + z535 = x535 + z536 = x536 + z537 = x537 + z538 = x538 + z539 = x539 + z540 = x540 + z541 = x541 + z542 = x542 + z543 = x543 + z544 = x544 + z545 = x545 + z546 = x546 + z547 = x547 + z548 = x548 + z549 = x549 + z550 = x550 + z551 = x551 + z552 = x552 + z553 = x553 + z554 = x554 + z555 = x555 + z556 = x556 + z557 = x557 + z558 = x558 + z559 = x559 + z560 = x560 + z561 = x561 + z562 = x562 + z563 = x563 + z564 = x564 + z565 = x565 + z566 = x566 + z567 = x567 + z568 = x568 + z569 = x569 + z570 = x570 + z571 = x571 + z572 = x572 + z573 = x573 + z574 = x574 + z575 = x575 + z576 = x576 + z577 = x577 + z578 = x578 + z579 = x579 + z580 = x580 + z581 = x581 + z582 = x582 + z583 = x583 + z584 = x584 + z585 = x585 + z586 = x586 + z587 = x587 + z588 = x588 + z589 = x589 + z590 = x590 + z591 = x591 + z592 = x592 + z593 = x593 + z594 = x594 + z595 = x595 + z596 = x596 + z597 = x597 + z598 = x598 + z599 = x599 + z600 = x600 + z601 = x601 + z602 = x602 + z603 = x603 + z604 = x604 + z605 = x605 + z606 = x606 + z607 = x607 + z608 = x608 + z609 = x609 + z610 = x610 + z611 = x611 + z612 = x612 + z613 = x613 + z614 = x614 + z615 = x615 + z616 = x616 + z617 = x617 + z618 = x618 + z619 = x619 + z620 = x620 + z621 = x621 + z622 = x622 + z623 = x623 + z624 = x624 + z625 = x625 + z626 = x626 + z627 = x627 + z628 = x628 + z629 = x629 + z630 = x630 + z631 = x631 + z632 = x632 + z633 = x633 + z634 = x634 + z635 = x635 + z636 = x636 + z637 = x637 + z638 = x638 + z639 = x639 + z640 = x640 + z641 = x641 + z642 = x642 + z643 = x643 + z644 = x644 + z645 = x645 + z646 = x646 + z647 = x647 + z648 = x648 + z649 = x649 + z650 = x650 + z651 = x651 + z652 = x652 + z653 = x653 + z654 = x654 + z655 = x655 + z656 = x656 + z657 = x657 + z658 = x658 + z659 = x659 + z660 = x660 + z661 = x661 + z662 = x662 + z663 = x663 + z664 = x664 + z665 = x665 + z666 = x666 + z667 = x667 + z668 = x668 + z669 = x669 + z670 = x670 + z671 = x671 + z672 = x672 + z673 = x673 + z674 = x674 + z675 = x675 + z676 = x676 + z677 = x677 + z678 = x678 + z679 = x679 + z680 = x680 + z681 = x681 + z682 = x682 + z683 = x683 + z684 = x684 + z685 = x685 + z686 = x686 + z687 = x687 + z688 = x688 + z689 = x689 + z690 = x690 + z691 = x691 + z692 = x692 + z693 = x693 + z694 = x694 + z695 = x695 + z696 = x696 + z697 = x697 + z698 = x698 + z699 = x699 + z700 = x700 + z701 = x701 + z702 = x702 + z703 = x703 + z704 = x704 + z705 = x705 + z706 = x706 + z707 = x707 + z708 = x708 + z709 = x709 + z710 = x710 + z711 = x711 + z712 = x712 + z713 = x713 + z714 = x714 + z715 = x715 + z716 = x716 + z717 = x717 + z718 = x718 + z719 = x719 + z720 = x720 + z721 = x721 + z722 = x722 + z723 = x723 + z724 = x724 + z725 = x725 + z726 = x726 + z727 = x727 + z728 = x728 + z729 = x729 + z730 = x730 + z731 = x731 + z732 = x732 + z733 = x733 + z734 = x734 + z735 = x735 + z736 = x736 + z737 = x737 + z738 = x738 + z739 = x739 + z740 = x740 + z741 = x741 + z742 = x742 + z743 = x743 + z744 = x744 + z745 = x745 + z746 = x746 + z747 = x747 + z748 = x748 + z749 = x749 + z750 = x750 + z751 = x751 + z752 = x752 + z753 = x753 + z754 = x754 + z755 = x755 + z756 = x756 + z757 = x757 + z758 = x758 + z759 = x759 + z760 = x760 + z761 = x761 + z762 = x762 + z763 = x763 + z764 = x764 + z765 = x765 + z766 = x766 + z767 = x767 + z768 = x768 + z769 = x769 + z770 = x770 + z771 = x771 + z772 = x772 + z773 = x773 + z774 = x774 + z775 = x775 + z776 = x776 + z777 = x777 + z778 = x778 + z779 = x779 + z780 = x780 + z781 = x781 + z782 = x782 + z783 = x783 + z784 = x784 + z785 = x785 + z786 = x786 + z787 = x787 + z788 = x788 + z789 = x789 + z790 = x790 + z791 = x791 + z792 = x792 + z793 = x793 + z794 = x794 + z795 = x795 + z796 = x796 + z797 = x797 + z798 = x798 + z799 = x799 + z800 = x800 + z801 = x801 + z802 = x802 + z803 = x803 + z804 = x804 + z805 = x805 + z806 = x806 + z807 = x807 + z808 = x808 + z809 = x809 + z810 = x810 + z811 = x811 + z812 = x812 + z813 = x813 + z814 = x814 + z815 = x815 + z816 = x816 + z817 = x817 + z818 = x818 + z819 = x819 + z820 = x820 + z821 = x821 + z822 = x822 + z823 = x823 + z824 = x824 + z825 = x825 + z826 = x826 + z827 = x827 + z828 = x828 + z829 = x829 + z830 = x830 + z831 = x831 + z832 = x832 + z833 = x833 + z834 = x834 + z835 = x835 + z836 = x836 + z837 = x837 + z838 = x838 + z839 = x839 + z840 = x840 + z841 = x841 + z842 = x842 + z843 = x843 + z844 = x844 + z845 = x845 + z846 = x846 + z847 = x847 + z848 = x848 + z849 = x849 + z850 = x850 + z851 = x851 + z852 = x852 + z853 = x853 + z854 = x854 + z855 = x855 + z856 = x856 + z857 = x857 + z858 = x858 + z859 = x859 + z860 = x860 + z861 = x861 + z862 = x862 + z863 = x863 + z864 = x864 + z865 = x865 + z866 = x866 + z867 = x867 + z868 = x868 + z869 = x869 + z870 = x870 + z871 = x871 + z872 = x872 + z873 = x873 + z874 = x874 + z875 = x875 + z876 = x876 + z877 = x877 + z878 = x878 + z879 = x879 + z880 = x880 + z881 = x881 + z882 = x882 + z883 = x883 + z884 = x884 + z885 = x885 + z886 = x886 + z887 = x887 + z888 = x888 + z889 = x889 + z890 = x890 + z891 = x891 + z892 = x892 + z893 = x893 + z894 = x894 + z895 = x895 + z896 = x896 + z897 = x897 + z898 = x898 + z899 = x899 + z900 = x900 + z901 = x901 + z902 = x902 + z903 = x903 + z904 = x904 + z905 = x905 + z906 = x906 + z907 = x907 + z908 = x908 + z909 = x909 + z910 = x910 + z911 = x911 + z912 = x912 + z913 = x913 + z914 = x914 + z915 = x915 + z916 = x916 + z917 = x917 + z918 = x918 + z919 = x919 + z920 = x920 + z921 = x921 + z922 = x922 + z923 = x923 + z924 = x924 + z925 = x925 + z926 = x926 + z927 = x927 + z928 = x928 + z929 = x929 + z930 = x930 + z931 = x931 + z932 = x932 + z933 = x933 + z934 = x934 + z935 = x935 + z936 = x936 + z937 = x937 + z938 = x938 + z939 = x939 + z940 = x940 + z941 = x941 + z942 = x942 + z943 = x943 + z944 = x944 + z945 = x945 + z946 = x946 + z947 = x947 + z948 = x948 + z949 = x949 + z950 = x950 + z951 = x951 + z952 = x952 + z953 = x953 + z954 = x954 + z955 = x955 + z956 = x956 + z957 = x957 + z958 = x958 + z959 = x959 + z960 = x960 + z961 = x961 + z962 = x962 + z963 = x963 + z964 = x964 + z965 = x965 + z966 = x966 + z967 = x967 + z968 = x968 + z969 = x969 + z970 = x970 + z971 = x971 + z972 = x972 + z973 = x973 + z974 = x974 + z975 = x975 + z976 = x976 + z977 = x977 + z978 = x978 + z979 = x979 + z980 = x980 + z981 = x981 + z982 = x982 + z983 = x983 + z984 = x984 + z985 = x985 + z986 = x986 + z987 = x987 + z988 = x988 + z989 = x989 + z990 = x990 + z991 = x991 + z992 = x992 + z993 = x993 + z994 = x994 + z995 = x995 + z996 = x996 + z997 = x997 + z998 = x998 + z999 = x999 + z1000 = x1000 + z1001 = x1001 + z1002 = x1002 + z1003 = x1003 + z1004 = x1004 + z1005 = x1005 + z1006 = x1006 + z1007 = x1007 + z1008 = x1008 + z1009 = x1009 + z1010 = x1010 + z1011 = x1011 + z1012 = x1012 + z1013 = x1013 + z1014 = x1014 + z1015 = x1015 + z1016 = x1016 + z1017 = x1017 + z1018 = x1018 + z1019 = x1019 + z1020 = x1020 + z1021 = x1021 + z1022 = x1022 + z1023 = x1023 + z1024 = x1024 + z1025 = x1025 + z1026 = x1026 + z1027 = x1027 + z1028 = x1028 + z1029 = x1029 + z1030 = x1030 + z1031 = x1031 + z1032 = x1032 + z1033 = x1033 + z1034 = x1034 + z1035 = x1035 + z1036 = x1036 + z1037 = x1037 + z1038 = x1038 + z1039 = x1039 + z1040 = x1040 + z1041 = x1041 + z1042 = x1042 + z1043 = x1043 + z1044 = x1044 + z1045 = x1045 + z1046 = x1046 + z1047 = x1047 + z1048 = x1048 + z1049 = x1049 + z1050 = x1050 + z1051 = x1051 + z1052 = x1052 + z1053 = x1053 + z1054 = x1054 + z1055 = x1055 + z1056 = x1056 + z1057 = x1057 + z1058 = x1058 + z1059 = x1059 + z1060 = x1060 + z1061 = x1061 + z1062 = x1062 + z1063 = x1063 + z1064 = x1064 + z1065 = x1065 + z1066 = x1066 + z1067 = x1067 + z1068 = x1068 + z1069 = x1069 + z1070 = x1070 + z1071 = x1071 + z1072 = x1072 + z1073 = x1073 + z1074 = x1074 + z1075 = x1075 + z1076 = x1076 + z1077 = x1077 + z1078 = x1078 + z1079 = x1079 + z1080 = x1080 + z1081 = x1081 + z1082 = x1082 + z1083 = x1083 + z1084 = x1084 + z1085 = x1085 + z1086 = x1086 + z1087 = x1087 + z1088 = x1088 + z1089 = x1089 + z1090 = x1090 + z1091 = x1091 + z1092 = x1092 + z1093 = x1093 + z1094 = x1094 + z1095 = x1095 + z1096 = x1096 + z1097 = x1097 + z1098 = x1098 + z1099 = x1099 + z1100 = x1100 + z1101 = x1101 + z1102 = x1102 + z1103 = x1103 + z1104 = x1104 + z1105 = x1105 + z1106 = x1106 + z1107 = x1107 + z1108 = x1108 + z1109 = x1109 + z1110 = x1110 + z1111 = x1111 + z1112 = x1112 + z1113 = x1113 + z1114 = x1114 + z1115 = x1115 + z1116 = x1116 + z1117 = x1117 + z1118 = x1118 + z1119 = x1119 + z1120 = x1120 + z1121 = x1121 + z1122 = x1122 + z1123 = x1123 + z1124 = x1124 + z1125 = x1125 + z1126 = x1126 + z1127 = x1127 + z1128 = x1128 + z1129 = x1129 + z1130 = x1130 + z1131 = x1131 + z1132 = x1132 + z1133 = x1133 + z1134 = x1134 + z1135 = x1135 + z1136 = x1136 + z1137 = x1137 + z1138 = x1138 + z1139 = x1139 + z1140 = x1140 + z1141 = x1141 + z1142 = x1142 + z1143 = x1143 + z1144 = x1144 + z1145 = x1145 + z1146 = x1146 + z1147 = x1147 + z1148 = x1148 + z1149 = x1149 + z1150 = x1150 + z1151 = x1151 + z1152 = x1152 + z1153 = x1153 + z1154 = x1154 + z1155 = x1155 + z1156 = x1156 + z1157 = x1157 + z1158 = x1158 + z1159 = x1159 + z1160 = x1160 + z1161 = x1161 + z1162 = x1162 + z1163 = x1163 + z1164 = x1164 + z1165 = x1165 + z1166 = x1166 + z1167 = x1167 + z1168 = x1168 + z1169 = x1169 + z1170 = x1170 + z1171 = x1171 + z1172 = x1172 + z1173 = x1173 + z1174 = x1174 + z1175 = x1175 + z1176 = x1176 + z1177 = x1177 + z1178 = x1178 + z1179 = x1179 + z1180 = x1180 + z1181 = x1181 + z1182 = x1182 + z1183 = x1183 + z1184 = x1184 + z1185 = x1185 + z1186 = x1186 + z1187 = x1187 + z1188 = x1188 + z1189 = x1189 + z1190 = x1190 + z1191 = x1191 + z1192 = x1192 + z1193 = x1193 + z1194 = x1194 + z1195 = x1195 + z1196 = x1196 + z1197 = x1197 + z1198 = x1198 + z1199 = x1199 + z1200 = x1200 + z1201 = x1201 + z1202 = x1202 + z1203 = x1203 + z1204 = x1204 + z1205 = x1205 + z1206 = x1206 + z1207 = x1207 + z1208 = x1208 + z1209 = x1209 + z1210 = x1210 + z1211 = x1211 + z1212 = x1212 + z1213 = x1213 + z1214 = x1214 + z1215 = x1215 + z1216 = x1216 + z1217 = x1217 + z1218 = x1218 + z1219 = x1219 + z1220 = x1220 + z1221 = x1221 + z1222 = x1222 + z1223 = x1223 + z1224 = x1224 + z1225 = x1225 + z1226 = x1226 + z1227 = x1227 + z1228 = x1228 + z1229 = x1229 + z1230 = x1230 + z1231 = x1231 + z1232 = x1232 + z1233 = x1233 + z1234 = x1234 + z1235 = x1235 + z1236 = x1236 + z1237 = x1237 + z1238 = x1238 + z1239 = x1239 + z1240 = x1240 + z1241 = x1241 + z1242 = x1242 + z1243 = x1243 + z1244 = x1244 + z1245 = x1245 + z1246 = x1246 + z1247 = x1247 + z1248 = x1248 + z1249 = x1249 + z1250 = x1250 + z1251 = x1251 + z1252 = x1252 + z1253 = x1253 + z1254 = x1254 + z1255 = x1255 + z1256 = x1256 + z1257 = x1257 + z1258 = x1258 + z1259 = x1259 + z1260 = x1260 + z1261 = x1261 + z1262 = x1262 + z1263 = x1263 + z1264 = x1264 + z1265 = x1265 + z1266 = x1266 + z1267 = x1267 + z1268 = x1268 + z1269 = x1269 + z1270 = x1270 + z1271 = x1271 + z1272 = x1272 + z1273 = x1273 + z1274 = x1274 + z1275 = x1275 + z1276 = x1276 + z1277 = x1277 + z1278 = x1278 + z1279 = x1279 + z1280 = x1280 + z1281 = x1281 + z1282 = x1282 + z1283 = x1283 + z1284 = x1284 + z1285 = x1285 + z1286 = x1286 + z1287 = x1287 + z1288 = x1288 + z1289 = x1289 + z1290 = x1290 + z1291 = x1291 + z1292 = x1292 + z1293 = x1293 + z1294 = x1294 + z1295 = x1295 + z1296 = x1296 + z1297 = x1297 + z1298 = x1298 + z1299 = x1299 + z1300 = x1300 + z1301 = x1301 + z1302 = x1302 + z1303 = x1303 + z1304 = x1304 + z1305 = x1305 + z1306 = x1306 + z1307 = x1307 + z1308 = x1308 + z1309 = x1309 + z1310 = x1310 + z1311 = x1311 + z1312 = x1312 + z1313 = x1313 + z1314 = x1314 + z1315 = x1315 + z1316 = x1316 + z1317 = x1317 + z1318 = x1318 + z1319 = x1319 + z1320 = x1320 + z1321 = x1321 + z1322 = x1322 + z1323 = x1323 + z1324 = x1324 + z1325 = x1325 + z1326 = x1326 + z1327 = x1327 + z1328 = x1328 + z1329 = x1329 + z1330 = x1330 + z1331 = x1331 + z1332 = x1332 + z1333 = x1333 + z1334 = x1334 + z1335 = x1335 + z1336 = x1336 + z1337 = x1337 + z1338 = x1338 + z1339 = x1339 + z1340 = x1340 + z1341 = x1341 + z1342 = x1342 + z1343 = x1343 + z1344 = x1344 + z1345 = x1345 + z1346 = x1346 + z1347 = x1347 + z1348 = x1348 + z1349 = x1349 + z1350 = x1350 + z1351 = x1351 + z1352 = x1352 + z1353 = x1353 + z1354 = x1354 + z1355 = x1355 + z1356 = x1356 + z1357 = x1357 + z1358 = x1358 + z1359 = x1359 + z1360 = x1360 + z1361 = x1361 + z1362 = x1362 + z1363 = x1363 + z1364 = x1364 + z1365 = x1365 + z1366 = x1366 + z1367 = x1367 + z1368 = x1368 + z1369 = x1369 + z1370 = x1370 + z1371 = x1371 + z1372 = x1372 + z1373 = x1373 + z1374 = x1374 + z1375 = x1375 + z1376 = x1376 + z1377 = x1377 + z1378 = x1378 + z1379 = x1379 + z1380 = x1380 + z1381 = x1381 + z1382 = x1382 + z1383 = x1383 + z1384 = x1384 + z1385 = x1385 + z1386 = x1386 + z1387 = x1387 + z1388 = x1388 + z1389 = x1389 + z1390 = x1390 + z1391 = x1391 + z1392 = x1392 + z1393 = x1393 + z1394 = x1394 + z1395 = x1395 + z1396 = x1396 + z1397 = x1397 + z1398 = x1398 + z1399 = x1399 + z1400 = x1400 + z1401 = x1401 + z1402 = x1402 + z1403 = x1403 + z1404 = x1404 + z1405 = x1405 + z1406 = x1406 + z1407 = x1407 + z1408 = x1408 + z1409 = x1409 + z1410 = x1410 + z1411 = x1411 + z1412 = x1412 + z1413 = x1413 + z1414 = x1414 + z1415 = x1415 + z1416 = x1416 + z1417 = x1417 + z1418 = x1418 + z1419 = x1419 + z1420 = x1420 + z1421 = x1421 + z1422 = x1422 + z1423 = x1423 + z1424 = x1424 + z1425 = x1425 + z1426 = x1426 + z1427 = x1427 + z1428 = x1428 + z1429 = x1429 + z1430 = x1430 + z1431 = x1431 + z1432 = x1432 + z1433 = x1433 + z1434 = x1434 + z1435 = x1435 + z1436 = x1436 + z1437 = x1437 + z1438 = x1438 + z1439 = x1439 + z1440 = x1440 + z1441 = x1441 + z1442 = x1442 + z1443 = x1443 + z1444 = x1444 + z1445 = x1445 + z1446 = x1446 + z1447 = x1447 + z1448 = x1448 + z1449 = x1449 + z1450 = x1450 + z1451 = x1451 + z1452 = x1452 + z1453 = x1453 + z1454 = x1454 + z1455 = x1455 + z1456 = x1456 + z1457 = x1457 + z1458 = x1458 + z1459 = x1459 + z1460 = x1460 + z1461 = x1461 + z1462 = x1462 + z1463 = x1463 + z1464 = x1464 + z1465 = x1465 + z1466 = x1466 + z1467 = x1467 + z1468 = x1468 + z1469 = x1469 + z1470 = x1470 + z1471 = x1471 + z1472 = x1472 + z1473 = x1473 + z1474 = x1474 + z1475 = x1475 + z1476 = x1476 + z1477 = x1477 + z1478 = x1478 + z1479 = x1479 + z1480 = x1480 + z1481 = x1481 + z1482 = x1482 + z1483 = x1483 + z1484 = x1484 + z1485 = x1485 + z1486 = x1486 + z1487 = x1487 + z1488 = x1488 + z1489 = x1489 + z1490 = x1490 + z1491 = x1491 + z1492 = x1492 + z1493 = x1493 + z1494 = x1494 + z1495 = x1495 + z1496 = x1496 + z1497 = x1497 + z1498 = x1498 + z1499 = x1499 + z1500 = x1500 + z1501 = x1501 + z1502 = x1502 + z1503 = x1503 + z1504 = x1504 + z1505 = x1505 + z1506 = x1506 + z1507 = x1507 + z1508 = x1508 + z1509 = x1509 + z1510 = x1510 + z1511 = x1511 + z1512 = x1512 + z1513 = x1513 + z1514 = x1514 + z1515 = x1515 + z1516 = x1516 + z1517 = x1517 + z1518 = x1518 + z1519 = x1519 + z1520 = x1520 + z1521 = x1521 + z1522 = x1522 + z1523 = x1523 + z1524 = x1524 + z1525 = x1525 + z1526 = x1526 + z1527 = x1527 + z1528 = x1528 + z1529 = x1529 + z1530 = x1530 + z1531 = x1531 + z1532 = x1532 + z1533 = x1533 + z1534 = x1534 + z1535 = x1535 + z1536 = x1536 + z1537 = x1537 + z1538 = x1538 + z1539 = x1539 + z1540 = x1540 + z1541 = x1541 + z1542 = x1542 + z1543 = x1543 + z1544 = x1544 + z1545 = x1545 + z1546 = x1546 + z1547 = x1547 + z1548 = x1548 + z1549 = x1549 + z1550 = x1550 + z1551 = x1551 + z1552 = x1552 + z1553 = x1553 + z1554 = x1554 + z1555 = x1555 + z1556 = x1556 + z1557 = x1557 + z1558 = x1558 + z1559 = x1559 + z1560 = x1560 + z1561 = x1561 + z1562 = x1562 + z1563 = x1563 + z1564 = x1564 + z1565 = x1565 + z1566 = x1566 + z1567 = x1567 + z1568 = x1568 + z1569 = x1569 + z1570 = x1570 + z1571 = x1571 + z1572 = x1572 + z1573 = x1573 + z1574 = x1574 + z1575 = x1575 + z1576 = x1576 + z1577 = x1577 + z1578 = x1578 + z1579 = x1579 + z1580 = x1580 + z1581 = x1581 + z1582 = x1582 + z1583 = x1583 + z1584 = x1584 + z1585 = x1585 + z1586 = x1586 + z1587 = x1587 + z1588 = x1588 + z1589 = x1589 + z1590 = x1590 + z1591 = x1591 + z1592 = x1592 + z1593 = x1593 + z1594 = x1594 + z1595 = x1595 + z1596 = x1596 + z1597 = x1597 + z1598 = x1598 + z1599 = x1599 + z1600 = x1600 + z1601 = x1601 + z1602 = x1602 + z1603 = x1603 + z1604 = x1604 + z1605 = x1605 + z1606 = x1606 + z1607 = x1607 + z1608 = x1608 + z1609 = x1609 + z1610 = x1610 + z1611 = x1611 + z1612 = x1612 + z1613 = x1613 + z1614 = x1614 + z1615 = x1615 + z1616 = x1616 + z1617 = x1617 + z1618 = x1618 + z1619 = x1619 + z1620 = x1620 + z1621 = x1621 + z1622 = x1622 + z1623 = x1623 + z1624 = x1624 + z1625 = x1625 + z1626 = x1626 + z1627 = x1627 + z1628 = x1628 + z1629 = x1629 + z1630 = x1630 + z1631 = x1631 + z1632 = x1632 + z1633 = x1633 + z1634 = x1634 + z1635 = x1635 + z1636 = x1636 + z1637 = x1637 + z1638 = x1638 + z1639 = x1639 + z1640 = x1640 + z1641 = x1641 + z1642 = x1642 + z1643 = x1643 + z1644 = x1644 + z1645 = x1645 + z1646 = x1646 + z1647 = x1647 + z1648 = x1648 + z1649 = x1649 + z1650 = x1650 + z1651 = x1651 + z1652 = x1652 + z1653 = x1653 + z1654 = x1654 + z1655 = x1655 + z1656 = x1656 + z1657 = x1657 + z1658 = x1658 + z1659 = x1659 + z1660 = x1660 + z1661 = x1661 + z1662 = x1662 + z1663 = x1663 + z1664 = x1664 + z1665 = x1665 + z1666 = x1666 + z1667 = x1667 + z1668 = x1668 + z1669 = x1669 + z1670 = x1670 + z1671 = x1671 + z1672 = x1672 + z1673 = x1673 + z1674 = x1674 + z1675 = x1675 + z1676 = x1676 + z1677 = x1677 + z1678 = x1678 + z1679 = x1679 + z1680 = x1680 + z1681 = x1681 + z1682 = x1682 + z1683 = x1683 + z1684 = x1684 + z1685 = x1685 + z1686 = x1686 + z1687 = x1687 + z1688 = x1688 + z1689 = x1689 + z1690 = x1690 + z1691 = x1691 + z1692 = x1692 + z1693 = x1693 + z1694 = x1694 + z1695 = x1695 + z1696 = x1696 + z1697 = x1697 + z1698 = x1698 + z1699 = x1699 + z1700 = x1700 + z1701 = x1701 + z1702 = x1702 + z1703 = x1703 + z1704 = x1704 + z1705 = x1705 + z1706 = x1706 + z1707 = x1707 + z1708 = x1708 + z1709 = x1709 + z1710 = x1710 + z1711 = x1711 + z1712 = x1712 + z1713 = x1713 + z1714 = x1714 + z1715 = x1715 + z1716 = x1716 + z1717 = x1717 + z1718 = x1718 + z1719 = x1719 + z1720 = x1720 + z1721 = x1721 + z1722 = x1722 + z1723 = x1723 + z1724 = x1724 + z1725 = x1725 + z1726 = x1726 + z1727 = x1727 + z1728 = x1728 + z1729 = x1729 + z1730 = x1730 + z1731 = x1731 + z1732 = x1732 + z1733 = x1733 + z1734 = x1734 + z1735 = x1735 + z1736 = x1736 + z1737 = x1737 + z1738 = x1738 + z1739 = x1739 + z1740 = x1740 + z1741 = x1741 + z1742 = x1742 + z1743 = x1743 + z1744 = x1744 + z1745 = x1745 + z1746 = x1746 + z1747 = x1747 + z1748 = x1748 + z1749 = x1749 + z1750 = x1750 + z1751 = x1751 + z1752 = x1752 + z1753 = x1753 + z1754 = x1754 + z1755 = x1755 + z1756 = x1756 + z1757 = x1757 + z1758 = x1758 + z1759 = x1759 + z1760 = x1760 + z1761 = x1761 + z1762 = x1762 + z1763 = x1763 + z1764 = x1764 + z1765 = x1765 + z1766 = x1766 + z1767 = x1767 + z1768 = x1768 + z1769 = x1769 + z1770 = x1770 + z1771 = x1771 + z1772 = x1772 + z1773 = x1773 + z1774 = x1774 + z1775 = x1775 + z1776 = x1776 + z1777 = x1777 + z1778 = x1778 + z1779 = x1779 + z1780 = x1780 + z1781 = x1781 + z1782 = x1782 + z1783 = x1783 + z1784 = x1784 + z1785 = x1785 + z1786 = x1786 + z1787 = x1787 + z1788 = x1788 + z1789 = x1789 + z1790 = x1790 + z1791 = x1791 + z1792 = x1792 + z1793 = x1793 + z1794 = x1794 + z1795 = x1795 + z1796 = x1796 + z1797 = x1797 + z1798 = x1798 + z1799 = x1799 + z1800 = x1800 + z1801 = x1801 + z1802 = x1802 + z1803 = x1803 + z1804 = x1804 + z1805 = x1805 + z1806 = x1806 + z1807 = x1807 + z1808 = x1808 + z1809 = x1809 + z1810 = x1810 + z1811 = x1811 + z1812 = x1812 + z1813 = x1813 + z1814 = x1814 + z1815 = x1815 + z1816 = x1816 + z1817 = x1817 + z1818 = x1818 + z1819 = x1819 + z1820 = x1820 + z1821 = x1821 + z1822 = x1822 + z1823 = x1823 + z1824 = x1824 + z1825 = x1825 + z1826 = x1826 + z1827 = x1827 + z1828 = x1828 + z1829 = x1829 + z1830 = x1830 + z1831 = x1831 + z1832 = x1832 + z1833 = x1833 + z1834 = x1834 + z1835 = x1835 + z1836 = x1836 + z1837 = x1837 + z1838 = x1838 + z1839 = x1839 + z1840 = x1840 + z1841 = x1841 + z1842 = x1842 + z1843 = x1843 + z1844 = x1844 + z1845 = x1845 + z1846 = x1846 + z1847 = x1847 + z1848 = x1848 + z1849 = x1849 + z1850 = x1850 + z1851 = x1851 + z1852 = x1852 + z1853 = x1853 + z1854 = x1854 + z1855 = x1855 + z1856 = x1856 + z1857 = x1857 + z1858 = x1858 + z1859 = x1859 + z1860 = x1860 + z1861 = x1861 + z1862 = x1862 + z1863 = x1863 + z1864 = x1864 + z1865 = x1865 + z1866 = x1866 + z1867 = x1867 + z1868 = x1868 + z1869 = x1869 + z1870 = x1870 + z1871 = x1871 + z1872 = x1872 + z1873 = x1873 + z1874 = x1874 + z1875 = x1875 + z1876 = x1876 + z1877 = x1877 + z1878 = x1878 + z1879 = x1879 + z1880 = x1880 + z1881 = x1881 + z1882 = x1882 + z1883 = x1883 + z1884 = x1884 + z1885 = x1885 + z1886 = x1886 + z1887 = x1887 + z1888 = x1888 + z1889 = x1889 + z1890 = x1890 + z1891 = x1891 + z1892 = x1892 + z1893 = x1893 + z1894 = x1894 + z1895 = x1895 + z1896 = x1896 + z1897 = x1897 + z1898 = x1898 + z1899 = x1899 + z1900 = x1900 + z1901 = x1901 + z1902 = x1902 + z1903 = x1903 + z1904 = x1904 + z1905 = x1905 + z1906 = x1906 + z1907 = x1907 + z1908 = x1908 + z1909 = x1909 + z1910 = x1910 + z1911 = x1911 + z1912 = x1912 + z1913 = x1913 + z1914 = x1914 + z1915 = x1915 + z1916 = x1916 + z1917 = x1917 + z1918 = x1918 + z1919 = x1919 + z1920 = x1920 + z1921 = x1921 + z1922 = x1922 + z1923 = x1923 + z1924 = x1924 + z1925 = x1925 + z1926 = x1926 + z1927 = x1927 + z1928 = x1928 + z1929 = x1929 + z1930 = x1930 + z1931 = x1931 + z1932 = x1932 + z1933 = x1933 + z1934 = x1934 + z1935 = x1935 + z1936 = x1936 + z1937 = x1937 + z1938 = x1938 + z1939 = x1939 + z1940 = x1940 + z1941 = x1941 + z1942 = x1942 + z1943 = x1943 + z1944 = x1944 + z1945 = x1945 + z1946 = x1946 + z1947 = x1947 + z1948 = x1948 + z1949 = x1949 + z1950 = x1950 + z1951 = x1951 + z1952 = x1952 + z1953 = x1953 + z1954 = x1954 + z1955 = x1955 + z1956 = x1956 + z1957 = x1957 + z1958 = x1958 + z1959 = x1959 + z1960 = x1960 + z1961 = x1961 + z1962 = x1962 + z1963 = x1963 + z1964 = x1964 + z1965 = x1965 + z1966 = x1966 + z1967 = x1967 + z1968 = x1968 + z1969 = x1969 + z1970 = x1970 + z1971 = x1971 + z1972 = x1972 + z1973 = x1973 + z1974 = x1974 + z1975 = x1975 + z1976 = x1976 + z1977 = x1977 + z1978 = x1978 + z1979 = x1979 + z1980 = x1980 + z1981 = x1981 + z1982 = x1982 + z1983 = x1983 + z1984 = x1984 + z1985 = x1985 + z1986 = x1986 + z1987 = x1987 + z1988 = x1988 + z1989 = x1989 + z1990 = x1990 + z1991 = x1991 + z1992 = x1992 + z1993 = x1993 + z1994 = x1994 + z1995 = x1995 + z1996 = x1996 + z1997 = x1997 + z1998 = x1998 + z1999 = x1999 + z2000 = x2000 + z2001 = x2001 + z2002 = x2002 + z2003 = x2003 + z2004 = x2004 + z2005 = x2005 + z2006 = x2006 + z2007 = x2007 + z2008 = x2008 + z2009 = x2009 + z2010 = x2010 + z2011 = x2011 + z2012 = x2012 + z2013 = x2013 + z2014 = x2014 + z2015 = x2015 + z2016 = x2016 + z2017 = x2017 + z2018 = x2018 + z2019 = x2019 + z2020 = x2020 + z2021 = x2021 + z2022 = x2022 + z2023 = x2023 + z2024 = x2024 + z2025 = x2025 + z2026 = x2026 + z2027 = x2027 + z2028 = x2028 + z2029 = x2029 + z2030 = x2030 + z2031 = x2031 + z2032 = x2032 + z2033 = x2033 + z2034 = x2034 + z2035 = x2035 + z2036 = x2036 + z2037 = x2037 + z2038 = x2038 + z2039 = x2039 + z2040 = x2040 + z2041 = x2041 + z2042 = x2042 + z2043 = x2043 + z2044 = x2044 + z2045 = x2045 + z2046 = x2046 + z2047 = x2047 + z2048 = x2048 + z2049 = x2049 + z2050 = x2050 + z2051 = x2051 + z2052 = x2052 + z2053 = x2053 + z2054 = x2054 + z2055 = x2055 + z2056 = x2056 + z2057 = x2057 + z2058 = x2058 + z2059 = x2059 + z2060 = x2060 + z2061 = x2061 + z2062 = x2062 + z2063 = x2063 + z2064 = x2064 + z2065 = x2065 + z2066 = x2066 + z2067 = x2067 + z2068 = x2068 + z2069 = x2069 + z2070 = x2070 + z2071 = x2071 + z2072 = x2072 + z2073 = x2073 + z2074 = x2074 + z2075 = x2075 + z2076 = x2076 + z2077 = x2077 + z2078 = x2078 + z2079 = x2079 + z2080 = x2080 + z2081 = x2081 + z2082 = x2082 + z2083 = x2083 + z2084 = x2084 + z2085 = x2085 + z2086 = x2086 + z2087 = x2087 + z2088 = x2088 + z2089 = x2089 + z2090 = x2090 + z2091 = x2091 + z2092 = x2092 + z2093 = x2093 + z2094 = x2094 + z2095 = x2095 + z2096 = x2096 + z2097 = x2097 + z2098 = x2098 + z2099 = x2099 + z2100 = x2100 + z2101 = x2101 + z2102 = x2102 + z2103 = x2103 + z2104 = x2104 + z2105 = x2105 + z2106 = x2106 + z2107 = x2107 + z2108 = x2108 + z2109 = x2109 + z2110 = x2110 + z2111 = x2111 + z2112 = x2112 + z2113 = x2113 + z2114 = x2114 + z2115 = x2115 + z2116 = x2116 + z2117 = x2117 + z2118 = x2118 + z2119 = x2119 + z2120 = x2120 + z2121 = x2121 + z2122 = x2122 + z2123 = x2123 + z2124 = x2124 + z2125 = x2125 + z2126 = x2126 + z2127 = x2127 + z2128 = x2128 + z2129 = x2129 + z2130 = x2130 + z2131 = x2131 + z2132 = x2132 + z2133 = x2133 + z2134 = x2134 + z2135 = x2135 + z2136 = x2136 + z2137 = x2137 + z2138 = x2138 + z2139 = x2139 + z2140 = x2140 + z2141 = x2141 + z2142 = x2142 + z2143 = x2143 + z2144 = x2144 + z2145 = x2145 + z2146 = x2146 + z2147 = x2147 + z2148 = x2148 + z2149 = x2149 + z2150 = x2150 + z2151 = x2151 + z2152 = x2152 + z2153 = x2153 + z2154 = x2154 + z2155 = x2155 + z2156 = x2156 + z2157 = x2157 + z2158 = x2158 + z2159 = x2159 + z2160 = x2160 + z2161 = x2161 + z2162 = x2162 + z2163 = x2163 + z2164 = x2164 + z2165 = x2165 + z2166 = x2166 + z2167 = x2167 + z2168 = x2168 + z2169 = x2169 + z2170 = x2170 + z2171 = x2171 + z2172 = x2172 + z2173 = x2173 + z2174 = x2174 + z2175 = x2175 + z2176 = x2176 + z2177 = x2177 + z2178 = x2178 + z2179 = x2179 + z2180 = x2180 + z2181 = x2181 + z2182 = x2182 + z2183 = x2183 + z2184 = x2184 + z2185 = x2185 + z2186 = x2186 + z2187 = x2187 + z2188 = x2188 + z2189 = x2189 + z2190 = x2190 + z2191 = x2191 + z2192 = x2192 + z2193 = x2193 + z2194 = x2194 + z2195 = x2195 + z2196 = x2196 + z2197 = x2197 + z2198 = x2198 + z2199 = x2199 + z2200 = x2200 + z2201 = x2201 + z2202 = x2202 + z2203 = x2203 + z2204 = x2204 + z2205 = x2205 + z2206 = x2206 + z2207 = x2207 + z2208 = x2208 + z2209 = x2209 + z2210 = x2210 + z2211 = x2211 + z2212 = x2212 + z2213 = x2213 + z2214 = x2214 + z2215 = x2215 + z2216 = x2216 + z2217 = x2217 + z2218 = x2218 + z2219 = x2219 + z2220 = x2220 + z2221 = x2221 + z2222 = x2222 + z2223 = x2223 + z2224 = x2224 + z2225 = x2225 + z2226 = x2226 + z2227 = x2227 + z2228 = x2228 + z2229 = x2229 + z2230 = x2230 + z2231 = x2231 + z2232 = x2232 + z2233 = x2233 + z2234 = x2234 + z2235 = x2235 + z2236 = x2236 + z2237 = x2237 + z2238 = x2238 + z2239 = x2239 + z2240 = x2240 + z2241 = x2241 + z2242 = x2242 + z2243 = x2243 + z2244 = x2244 + z2245 = x2245 + z2246 = x2246 + z2247 = x2247 + z2248 = x2248 + z2249 = x2249 + z2250 = x2250 + z2251 = x2251 + z2252 = x2252 + z2253 = x2253 + z2254 = x2254 + z2255 = x2255 + z2256 = x2256 + z2257 = x2257 + z2258 = x2258 + z2259 = x2259 + z2260 = x2260 + z2261 = x2261 + z2262 = x2262 + z2263 = x2263 + z2264 = x2264 + z2265 = x2265 + z2266 = x2266 + z2267 = x2267 + z2268 = x2268 + z2269 = x2269 + z2270 = x2270 + z2271 = x2271 + z2272 = x2272 + z2273 = x2273 + z2274 = x2274 + z2275 = x2275 + z2276 = x2276 + z2277 = x2277 + z2278 = x2278 + z2279 = x2279 + z2280 = x2280 + z2281 = x2281 + z2282 = x2282 + z2283 = x2283 + z2284 = x2284 + z2285 = x2285 + z2286 = x2286 + z2287 = x2287 + z2288 = x2288 + z2289 = x2289 + z2290 = x2290 + z2291 = x2291 + z2292 = x2292 + z2293 = x2293 + z2294 = x2294 + z2295 = x2295 + z2296 = x2296 + z2297 = x2297 + z2298 = x2298 + z2299 = x2299 + z2300 = x2300 + z2301 = x2301 + z2302 = x2302 + z2303 = x2303 + z2304 = x2304 + z2305 = x2305 + z2306 = x2306 + z2307 = x2307 + z2308 = x2308 + z2309 = x2309 + z2310 = x2310 + z2311 = x2311 + z2312 = x2312 + z2313 = x2313 + z2314 = x2314 + z2315 = x2315 + z2316 = x2316 + z2317 = x2317 + z2318 = x2318 + z2319 = x2319 + z2320 = x2320 + z2321 = x2321 + z2322 = x2322 + z2323 = x2323 + z2324 = x2324 + z2325 = x2325 + z2326 = x2326 + z2327 = x2327 + z2328 = x2328 + z2329 = x2329 + z2330 = x2330 + z2331 = x2331 + z2332 = x2332 + z2333 = x2333 + z2334 = x2334 + z2335 = x2335 + z2336 = x2336 + z2337 = x2337 + z2338 = x2338 + z2339 = x2339 + z2340 = x2340 + z2341 = x2341 + z2342 = x2342 + z2343 = x2343 + z2344 = x2344 + z2345 = x2345 + z2346 = x2346 + z2347 = x2347 + z2348 = x2348 + z2349 = x2349 + z2350 = x2350 + z2351 = x2351 + z2352 = x2352 + z2353 = x2353 + z2354 = x2354 + z2355 = x2355 + z2356 = x2356 + z2357 = x2357 + z2358 = x2358 + z2359 = x2359 + z2360 = x2360 + z2361 = x2361 + z2362 = x2362 + z2363 = x2363 + z2364 = x2364 + z2365 = x2365 + z2366 = x2366 + z2367 = x2367 + z2368 = x2368 + z2369 = x2369 + z2370 = x2370 + z2371 = x2371 + z2372 = x2372 + z2373 = x2373 + z2374 = x2374 + z2375 = x2375 + z2376 = x2376 + z2377 = x2377 + z2378 = x2378 + z2379 = x2379 + z2380 = x2380 + z2381 = x2381 + z2382 = x2382 + z2383 = x2383 + z2384 = x2384 + z2385 = x2385 + z2386 = x2386 + z2387 = x2387 + z2388 = x2388 + z2389 = x2389 + z2390 = x2390 + z2391 = x2391 + z2392 = x2392 + z2393 = x2393 + z2394 = x2394 + z2395 = x2395 + z2396 = x2396 + z2397 = x2397 + z2398 = x2398 + z2399 = x2399 + z2400 = x2400 + z2401 = x2401 + z2402 = x2402 + z2403 = x2403 + z2404 = x2404 + z2405 = x2405 + z2406 = x2406 + z2407 = x2407 + z2408 = x2408 + z2409 = x2409 + z2410 = x2410 + z2411 = x2411 + z2412 = x2412 + z2413 = x2413 + z2414 = x2414 + z2415 = x2415 + z2416 = x2416 + z2417 = x2417 + z2418 = x2418 + z2419 = x2419 + z2420 = x2420 + z2421 = x2421 + z2422 = x2422 + z2423 = x2423 + z2424 = x2424 + z2425 = x2425 + z2426 = x2426 + z2427 = x2427 + z2428 = x2428 + z2429 = x2429 + z2430 = x2430 + z2431 = x2431 + z2432 = x2432 + z2433 = x2433 + z2434 = x2434 + z2435 = x2435 + z2436 = x2436 + z2437 = x2437 + z2438 = x2438 + z2439 = x2439 + z2440 = x2440 + z2441 = x2441 + z2442 = x2442 + z2443 = x2443 + z2444 = x2444 + z2445 = x2445 + z2446 = x2446 + z2447 = x2447 + z2448 = x2448 + z2449 = x2449 + z2450 = x2450 + z2451 = x2451 + z2452 = x2452 + z2453 = x2453 + z2454 = x2454 + z2455 = x2455 + z2456 = x2456 + z2457 = x2457 + z2458 = x2458 + z2459 = x2459 + z2460 = x2460 + z2461 = x2461 + z2462 = x2462 + z2463 = x2463 + z2464 = x2464 + z2465 = x2465 + z2466 = x2466 + z2467 = x2467 + z2468 = x2468 + z2469 = x2469 + z2470 = x2470 + z2471 = x2471 + z2472 = x2472 + z2473 = x2473 + z2474 = x2474 + z2475 = x2475 + z2476 = x2476 + z2477 = x2477 + z2478 = x2478 + z2479 = x2479 + z2480 = x2480 + z2481 = x2481 + z2482 = x2482 + z2483 = x2483 + z2484 = x2484 + z2485 = x2485 + z2486 = x2486 + z2487 = x2487 + z2488 = x2488 + z2489 = x2489 + z2490 = x2490 + z2491 = x2491 + z2492 = x2492 + z2493 = x2493 + z2494 = x2494 + z2495 = x2495 + z2496 = x2496 + z2497 = x2497 + z2498 = x2498 + z2499 = x2499 + z2500 = x2500 + z2501 = x2501 + z2502 = x2502 + z2503 = x2503 + z2504 = x2504 + z2505 = x2505 + z2506 = x2506 + z2507 = x2507 + z2508 = x2508 + z2509 = x2509 + z2510 = x2510 + z2511 = x2511 + z2512 = x2512 + z2513 = x2513 + z2514 = x2514 + z2515 = x2515 + z2516 = x2516 + z2517 = x2517 + z2518 = x2518 + z2519 = x2519 + z2520 = x2520 + z2521 = x2521 + z2522 = x2522 + z2523 = x2523 + z2524 = x2524 + z2525 = x2525 + z2526 = x2526 + z2527 = x2527 + z2528 = x2528 + z2529 = x2529 + z2530 = x2530 + z2531 = x2531 + z2532 = x2532 + z2533 = x2533 + z2534 = x2534 + z2535 = x2535 + z2536 = x2536 + z2537 = x2537 + z2538 = x2538 + z2539 = x2539 + z2540 = x2540 + z2541 = x2541 + z2542 = x2542 + z2543 = x2543 + z2544 = x2544 + z2545 = x2545 + z2546 = x2546 + z2547 = x2547 + z2548 = x2548 + z2549 = x2549 + z2550 = x2550 + z2551 = x2551 + z2552 = x2552 + z2553 = x2553 + z2554 = x2554 + z2555 = x2555 + z2556 = x2556 + z2557 = x2557 + z2558 = x2558 + z2559 = x2559 + z2560 = x2560 + z2561 = x2561 + z2562 = x2562 + z2563 = x2563 + z2564 = x2564 + z2565 = x2565 + z2566 = x2566 + z2567 = x2567 + z2568 = x2568 + z2569 = x2569 + z2570 = x2570 + z2571 = x2571 + z2572 = x2572 + z2573 = x2573 + z2574 = x2574 + z2575 = x2575 + z2576 = x2576 + z2577 = x2577 + z2578 = x2578 + z2579 = x2579 + z2580 = x2580 + z2581 = x2581 + z2582 = x2582 + z2583 = x2583 + z2584 = x2584 + z2585 = x2585 + z2586 = x2586 + z2587 = x2587 + z2588 = x2588 + z2589 = x2589 + z2590 = x2590 + z2591 = x2591 + z2592 = x2592 + z2593 = x2593 + z2594 = x2594 + z2595 = x2595 + z2596 = x2596 + z2597 = x2597 + z2598 = x2598 + z2599 = x2599 + z2600 = x2600 + z2601 = x2601 + z2602 = x2602 + z2603 = x2603 + z2604 = x2604 + z2605 = x2605 + z2606 = x2606 + z2607 = x2607 + z2608 = x2608 + z2609 = x2609 + z2610 = x2610 + z2611 = x2611 + z2612 = x2612 + z2613 = x2613 + z2614 = x2614 + z2615 = x2615 + z2616 = x2616 + z2617 = x2617 + z2618 = x2618 + z2619 = x2619 + z2620 = x2620 + z2621 = x2621 + z2622 = x2622 + z2623 = x2623 + z2624 = x2624 + z2625 = x2625 + z2626 = x2626 + z2627 = x2627 + z2628 = x2628 + z2629 = x2629 + z2630 = x2630 + z2631 = x2631 + z2632 = x2632 + z2633 = x2633 + z2634 = x2634 + z2635 = x2635 + z2636 = x2636 + z2637 = x2637 + z2638 = x2638 + z2639 = x2639 + z2640 = x2640 + z2641 = x2641 + z2642 = x2642 + z2643 = x2643 + z2644 = x2644 + z2645 = x2645 + z2646 = x2646 + z2647 = x2647 + z2648 = x2648 + z2649 = x2649 + z2650 = x2650 + z2651 = x2651 + z2652 = x2652 + z2653 = x2653 + z2654 = x2654 + z2655 = x2655 + z2656 = x2656 + z2657 = x2657 + z2658 = x2658 + z2659 = x2659 + z2660 = x2660 + z2661 = x2661 + z2662 = x2662 + z2663 = x2663 + z2664 = x2664 + z2665 = x2665 + z2666 = x2666 + z2667 = x2667 + z2668 = x2668 + z2669 = x2669 + z2670 = x2670 + z2671 = x2671 + z2672 = x2672 + z2673 = x2673 + z2674 = x2674 + z2675 = x2675 + z2676 = x2676 + z2677 = x2677 + z2678 = x2678 + z2679 = x2679 + z2680 = x2680 + z2681 = x2681 + z2682 = x2682 + z2683 = x2683 + z2684 = x2684 + z2685 = x2685 + z2686 = x2686 + z2687 = x2687 + z2688 = x2688 + z2689 = x2689 + z2690 = x2690 + z2691 = x2691 + z2692 = x2692 + z2693 = x2693 + z2694 = x2694 + z2695 = x2695 + z2696 = x2696 + z2697 = x2697 + z2698 = x2698 + z2699 = x2699 + z2700 = x2700 + z2701 = x2701 + z2702 = x2702 + z2703 = x2703 + z2704 = x2704 + z2705 = x2705 + z2706 = x2706 + z2707 = x2707 + z2708 = x2708 + z2709 = x2709 + z2710 = x2710 + z2711 = x2711 + z2712 = x2712 + z2713 = x2713 + z2714 = x2714 + z2715 = x2715 + z2716 = x2716 + z2717 = x2717 + z2718 = x2718 + z2719 = x2719 + z2720 = x2720 + z2721 = x2721 + z2722 = x2722 + z2723 = x2723 + z2724 = x2724 + z2725 = x2725 + z2726 = x2726 + z2727 = x2727 + z2728 = x2728 + z2729 = x2729 + z2730 = x2730 + z2731 = x2731 + z2732 = x2732 + z2733 = x2733 + z2734 = x2734 + z2735 = x2735 + z2736 = x2736 + z2737 = x2737 + z2738 = x2738 + z2739 = x2739 + z2740 = x2740 + z2741 = x2741 + z2742 = x2742 + z2743 = x2743 + z2744 = x2744 + z2745 = x2745 + z2746 = x2746 + z2747 = x2747 + z2748 = x2748 + z2749 = x2749 + z2750 = x2750 + z2751 = x2751 + z2752 = x2752 + z2753 = x2753 + z2754 = x2754 + z2755 = x2755 + z2756 = x2756 + z2757 = x2757 + z2758 = x2758 + z2759 = x2759 + z2760 = x2760 + z2761 = x2761 + z2762 = x2762 + z2763 = x2763 + z2764 = x2764 + z2765 = x2765 + z2766 = x2766 + z2767 = x2767 + z2768 = x2768 + z2769 = x2769 + z2770 = x2770 + z2771 = x2771 + z2772 = x2772 + z2773 = x2773 + z2774 = x2774 + z2775 = x2775 + z2776 = x2776 + z2777 = x2777 + z2778 = x2778 + z2779 = x2779 + z2780 = x2780 + z2781 = x2781 + z2782 = x2782 + z2783 = x2783 + z2784 = x2784 + z2785 = x2785 + z2786 = x2786 + z2787 = x2787 + z2788 = x2788 + z2789 = x2789 + z2790 = x2790 + z2791 = x2791 + z2792 = x2792 + z2793 = x2793 + z2794 = x2794 + z2795 = x2795 + z2796 = x2796 + z2797 = x2797 + z2798 = x2798 + z2799 = x2799 + z2800 = x2800 + z2801 = x2801 + z2802 = x2802 + z2803 = x2803 + z2804 = x2804 + z2805 = x2805 + z2806 = x2806 + z2807 = x2807 + z2808 = x2808 + z2809 = x2809 + z2810 = x2810 + z2811 = x2811 + z2812 = x2812 + z2813 = x2813 + z2814 = x2814 + z2815 = x2815 + z2816 = x2816 + z2817 = x2817 + z2818 = x2818 + z2819 = x2819 + z2820 = x2820 + z2821 = x2821 + z2822 = x2822 + z2823 = x2823 + z2824 = x2824 + z2825 = x2825 + z2826 = x2826 + z2827 = x2827 + z2828 = x2828 + z2829 = x2829 + z2830 = x2830 + z2831 = x2831 + z2832 = x2832 + z2833 = x2833 + z2834 = x2834 + z2835 = x2835 + z2836 = x2836 + z2837 = x2837 + z2838 = x2838 + z2839 = x2839 + z2840 = x2840 + z2841 = x2841 + z2842 = x2842 + z2843 = x2843 + z2844 = x2844 + z2845 = x2845 + z2846 = x2846 + z2847 = x2847 + z2848 = x2848 + z2849 = x2849 + z2850 = x2850 + z2851 = x2851 + z2852 = x2852 + z2853 = x2853 + z2854 = x2854 + z2855 = x2855 + z2856 = x2856 + z2857 = x2857 + z2858 = x2858 + z2859 = x2859 + z2860 = x2860 + z2861 = x2861 + z2862 = x2862 + z2863 = x2863 + z2864 = x2864 + z2865 = x2865 + z2866 = x2866 + z2867 = x2867 + z2868 = x2868 + z2869 = x2869 + z2870 = x2870 + z2871 = x2871 + z2872 = x2872 + z2873 = x2873 + z2874 = x2874 + z2875 = x2875 + z2876 = x2876 + z2877 = x2877 + z2878 = x2878 + z2879 = x2879 + z2880 = x2880 + z2881 = x2881 + z2882 = x2882 + z2883 = x2883 + z2884 = x2884 + z2885 = x2885 + z2886 = x2886 + z2887 = x2887 + z2888 = x2888 + z2889 = x2889 + z2890 = x2890 + z2891 = x2891 + z2892 = x2892 + z2893 = x2893 + z2894 = x2894 + z2895 = x2895 + z2896 = x2896 + z2897 = x2897 + z2898 = x2898 + z2899 = x2899 + z2900 = x2900 + z2901 = x2901 + z2902 = x2902 + z2903 = x2903 + z2904 = x2904 + z2905 = x2905 + z2906 = x2906 + z2907 = x2907 + z2908 = x2908 + z2909 = x2909 + z2910 = x2910 + z2911 = x2911 + z2912 = x2912 + z2913 = x2913 + z2914 = x2914 + z2915 = x2915 + z2916 = x2916 + z2917 = x2917 + z2918 = x2918 + z2919 = x2919 + z2920 = x2920 + z2921 = x2921 + z2922 = x2922 + z2923 = x2923 + z2924 = x2924 + z2925 = x2925 + z2926 = x2926 + z2927 = x2927 + z2928 = x2928 + z2929 = x2929 + z2930 = x2930 + z2931 = x2931 + z2932 = x2932 + z2933 = x2933 + z2934 = x2934 + z2935 = x2935 + z2936 = x2936 + z2937 = x2937 + z2938 = x2938 + z2939 = x2939 + z2940 = x2940 + z2941 = x2941 + z2942 = x2942 + z2943 = x2943 + z2944 = x2944 + z2945 = x2945 + z2946 = x2946 + z2947 = x2947 + z2948 = x2948 + z2949 = x2949 + z2950 = x2950 + z2951 = x2951 + z2952 = x2952 + z2953 = x2953 + z2954 = x2954 + z2955 = x2955 + z2956 = x2956 + z2957 = x2957 + z2958 = x2958 + z2959 = x2959 + z2960 = x2960 + z2961 = x2961 + z2962 = x2962 + z2963 = x2963 + z2964 = x2964 + z2965 = x2965 + z2966 = x2966 + z2967 = x2967 + z2968 = x2968 + z2969 = x2969 + z2970 = x2970 + z2971 = x2971 + z2972 = x2972 + z2973 = x2973 + z2974 = x2974 + z2975 = x2975 + z2976 = x2976 + z2977 = x2977 + z2978 = x2978 + z2979 = x2979 + z2980 = x2980 + z2981 = x2981 + z2982 = x2982 + z2983 = x2983 + z2984 = x2984 + z2985 = x2985 + z2986 = x2986 + z2987 = x2987 + z2988 = x2988 + z2989 = x2989 + z2990 = x2990 + z2991 = x2991 + z2992 = x2992 + z2993 = x2993 + z2994 = x2994 + z2995 = x2995 + z2996 = x2996 + z2997 = x2997 + z2998 = x2998 + z2999 = x2999 + z3000 = x3000 + z3001 = x3001 + z3002 = x3002 + z3003 = x3003 + z3004 = x3004 + z3005 = x3005 + z3006 = x3006 + z3007 = x3007 + z3008 = x3008 + z3009 = x3009 + z3010 = x3010 + z3011 = x3011 + z3012 = x3012 + z3013 = x3013 + z3014 = x3014 + z3015 = x3015 + z3016 = x3016 + z3017 = x3017 + z3018 = x3018 + z3019 = x3019 + z3020 = x3020 + z3021 = x3021 + z3022 = x3022 + z3023 = x3023 + z3024 = x3024 + z3025 = x3025 + z3026 = x3026 + z3027 = x3027 + z3028 = x3028 + z3029 = x3029 + z3030 = x3030 + z3031 = x3031 + z3032 = x3032 + z3033 = x3033 + z3034 = x3034 + z3035 = x3035 + z3036 = x3036 + z3037 = x3037 + z3038 = x3038 + z3039 = x3039 + z3040 = x3040 + z3041 = x3041 + z3042 = x3042 + z3043 = x3043 + z3044 = x3044 + z3045 = x3045 + z3046 = x3046 + z3047 = x3047 + z3048 = x3048 + z3049 = x3049 + z3050 = x3050 + z3051 = x3051 + z3052 = x3052 + z3053 = x3053 + z3054 = x3054 + z3055 = x3055 + z3056 = x3056 + z3057 = x3057 + z3058 = x3058 + z3059 = x3059 + z3060 = x3060 + z3061 = x3061 + z3062 = x3062 + z3063 = x3063 + z3064 = x3064 + z3065 = x3065 + z3066 = x3066 + z3067 = x3067 + z3068 = x3068 + z3069 = x3069 + z3070 = x3070 + z3071 = x3071 + z3072 = x3072 + z3073 = x3073 + z3074 = x3074 + z3075 = x3075 + z3076 = x3076 + z3077 = x3077 + z3078 = x3078 + z3079 = x3079 + z3080 = x3080 + z3081 = x3081 + z3082 = x3082 + z3083 = x3083 + z3084 = x3084 + z3085 = x3085 + z3086 = x3086 + z3087 = x3087 + z3088 = x3088 + z3089 = x3089 + z3090 = x3090 + z3091 = x3091 + z3092 = x3092 + z3093 = x3093 + z3094 = x3094 + z3095 = x3095 + z3096 = x3096 + z3097 = x3097 + z3098 = x3098 + z3099 = x3099 + z3100 = x3100 + z3101 = x3101 + z3102 = x3102 + z3103 = x3103 + z3104 = x3104 + z3105 = x3105 + z3106 = x3106 + z3107 = x3107 + z3108 = x3108 + z3109 = x3109 + z3110 = x3110 + z3111 = x3111 + z3112 = x3112 + z3113 = x3113 + z3114 = x3114 + z3115 = x3115 + z3116 = x3116 + z3117 = x3117 + z3118 = x3118 + z3119 = x3119 + z3120 = x3120 + z3121 = x3121 + z3122 = x3122 + z3123 = x3123 + z3124 = x3124 + z3125 = x3125 + z3126 = x3126 + z3127 = x3127 + z3128 = x3128 + z3129 = x3129 + z3130 = x3130 + z3131 = x3131 + z3132 = x3132 + z3133 = x3133 + z3134 = x3134 + z3135 = x3135 + z3136 = x3136 + z3137 = x3137 + z3138 = x3138 + z3139 = x3139 + z3140 = x3140 + z3141 = x3141 + z3142 = x3142 + z3143 = x3143 + z3144 = x3144 + z3145 = x3145 + z3146 = x3146 + z3147 = x3147 + z3148 = x3148 + z3149 = x3149 + z3150 = x3150 + z3151 = x3151 + z3152 = x3152 + z3153 = x3153 + z3154 = x3154 + z3155 = x3155 + z3156 = x3156 + z3157 = x3157 + z3158 = x3158 + z3159 = x3159 + z3160 = x3160 + z3161 = x3161 + z3162 = x3162 + z3163 = x3163 + z3164 = x3164 + z3165 = x3165 + z3166 = x3166 + z3167 = x3167 + z3168 = x3168 + z3169 = x3169 + z3170 = x3170 + z3171 = x3171 + z3172 = x3172 + z3173 = x3173 + z3174 = x3174 + z3175 = x3175 + z3176 = x3176 + z3177 = x3177 + z3178 = x3178 + z3179 = x3179 + z3180 = x3180 + z3181 = x3181 + z3182 = x3182 + z3183 = x3183 + z3184 = x3184 + z3185 = x3185 + z3186 = x3186 + z3187 = x3187 + z3188 = x3188 + z3189 = x3189 + z3190 = x3190 + z3191 = x3191 + z3192 = x3192 + z3193 = x3193 + z3194 = x3194 + z3195 = x3195 + z3196 = x3196 + z3197 = x3197 + z3198 = x3198 + z3199 = x3199 + z3200 = x3200 + z3201 = x3201 + z3202 = x3202 + z3203 = x3203 + z3204 = x3204 + z3205 = x3205 + z3206 = x3206 + z3207 = x3207 + z3208 = x3208 + z3209 = x3209 + z3210 = x3210 + z3211 = x3211 + z3212 = x3212 + z3213 = x3213 + z3214 = x3214 + z3215 = x3215 + z3216 = x3216 + z3217 = x3217 + z3218 = x3218 + z3219 = x3219 + z3220 = x3220 + z3221 = x3221 + z3222 = x3222 + z3223 = x3223 + z3224 = x3224 + z3225 = x3225 + z3226 = x3226 + z3227 = x3227 + z3228 = x3228 + z3229 = x3229 + z3230 = x3230 + z3231 = x3231 + z3232 = x3232 + z3233 = x3233 + z3234 = x3234 + z3235 = x3235 + z3236 = x3236 + z3237 = x3237 + z3238 = x3238 + z3239 = x3239 + z3240 = x3240 + z3241 = x3241 + z3242 = x3242 + z3243 = x3243 + z3244 = x3244 + z3245 = x3245 + z3246 = x3246 + z3247 = x3247 + z3248 = x3248 + z3249 = x3249 + z3250 = x3250 + z3251 = x3251 + z3252 = x3252 + z3253 = x3253 + z3254 = x3254 + z3255 = x3255 + z3256 = x3256 + z3257 = x3257 + z3258 = x3258 + z3259 = x3259 + z3260 = x3260 + z3261 = x3261 + z3262 = x3262 + z3263 = x3263 + z3264 = x3264 + z3265 = x3265 + z3266 = x3266 + z3267 = x3267 + z3268 = x3268 + z3269 = x3269 + z3270 = x3270 + z3271 = x3271 + z3272 = x3272 + z3273 = x3273 + z3274 = x3274 + z3275 = x3275 + z3276 = x3276 + z3277 = x3277 + z3278 = x3278 + z3279 = x3279 + z3280 = x3280 + z3281 = x3281 + z3282 = x3282 + z3283 = x3283 + z3284 = x3284 + z3285 = x3285 + z3286 = x3286 + z3287 = x3287 + z3288 = x3288 + z3289 = x3289 + z3290 = x3290 + z3291 = x3291 + z3292 = x3292 + z3293 = x3293 + z3294 = x3294 + z3295 = x3295 + z3296 = x3296 + z3297 = x3297 + z3298 = x3298 + z3299 = x3299 + z3300 = x3300 + z3301 = x3301 + z3302 = x3302 + z3303 = x3303 + z3304 = x3304 + z3305 = x3305 + z3306 = x3306 + z3307 = x3307 + z3308 = x3308 + z3309 = x3309 + z3310 = x3310 + z3311 = x3311 + z3312 = x3312 + z3313 = x3313 + z3314 = x3314 + z3315 = x3315 + z3316 = x3316 + z3317 = x3317 + z3318 = x3318 + z3319 = x3319 + z3320 = x3320 + z3321 = x3321 + z3322 = x3322 + z3323 = x3323 + z3324 = x3324 + z3325 = x3325 + z3326 = x3326 + z3327 = x3327 + z3328 = x3328 + z3329 = x3329 + z3330 = x3330 + z3331 = x3331 + z3332 = x3332 + z3333 = x3333 + z3334 = x3334 + z3335 = x3335 + z3336 = x3336 + z3337 = x3337 + z3338 = x3338 + z3339 = x3339 + z3340 = x3340 + z3341 = x3341 + z3342 = x3342 + z3343 = x3343 + z3344 = x3344 + z3345 = x3345 + z3346 = x3346 + z3347 = x3347 + z3348 = x3348 + z3349 = x3349 + z3350 = x3350 + z3351 = x3351 + z3352 = x3352 + z3353 = x3353 + z3354 = x3354 + z3355 = x3355 + z3356 = x3356 + z3357 = x3357 + z3358 = x3358 + z3359 = x3359 + z3360 = x3360 + z3361 = x3361 + z3362 = x3362 + z3363 = x3363 + z3364 = x3364 + z3365 = x3365 + z3366 = x3366 + z3367 = x3367 + z3368 = x3368 + z3369 = x3369 + z3370 = x3370 + z3371 = x3371 + z3372 = x3372 + z3373 = x3373 + z3374 = x3374 + z3375 = x3375 + z3376 = x3376 + z3377 = x3377 + z3378 = x3378 + z3379 = x3379 + z3380 = x3380 + z3381 = x3381 + z3382 = x3382 + z3383 = x3383 + z3384 = x3384 + z3385 = x3385 + z3386 = x3386 + z3387 = x3387 + z3388 = x3388 + z3389 = x3389 + z3390 = x3390 + z3391 = x3391 + z3392 = x3392 + z3393 = x3393 + z3394 = x3394 + z3395 = x3395 + z3396 = x3396 + z3397 = x3397 + z3398 = x3398 + z3399 = x3399 + z3400 = x3400 + z3401 = x3401 + z3402 = x3402 + z3403 = x3403 + z3404 = x3404 + z3405 = x3405 + z3406 = x3406 + z3407 = x3407 + z3408 = x3408 + z3409 = x3409 + z3410 = x3410 + z3411 = x3411 + z3412 = x3412 + z3413 = x3413 + z3414 = x3414 + z3415 = x3415 + z3416 = x3416 + z3417 = x3417 + z3418 = x3418 + z3419 = x3419 + z3420 = x3420 + z3421 = x3421 + z3422 = x3422 + z3423 = x3423 + z3424 = x3424 + z3425 = x3425 + z3426 = x3426 + z3427 = x3427 + z3428 = x3428 + z3429 = x3429 + z3430 = x3430 + z3431 = x3431 + z3432 = x3432 + z3433 = x3433 + z3434 = x3434 + z3435 = x3435 + z3436 = x3436 + z3437 = x3437 + z3438 = x3438 + z3439 = x3439 + z3440 = x3440 + z3441 = x3441 + z3442 = x3442 + z3443 = x3443 + z3444 = x3444 + z3445 = x3445 + z3446 = x3446 + z3447 = x3447 + z3448 = x3448 + z3449 = x3449 + z3450 = x3450 + z3451 = x3451 + z3452 = x3452 + z3453 = x3453 + z3454 = x3454 + z3455 = x3455 + z3456 = x3456 + z3457 = x3457 + z3458 = x3458 + z3459 = x3459 + z3460 = x3460 + z3461 = x3461 + z3462 = x3462 + z3463 = x3463 + z3464 = x3464 + z3465 = x3465 + z3466 = x3466 + z3467 = x3467 + z3468 = x3468 + z3469 = x3469 + z3470 = x3470 + z3471 = x3471 + z3472 = x3472 + z3473 = x3473 + z3474 = x3474 + z3475 = x3475 + z3476 = x3476 + z3477 = x3477 + z3478 = x3478 + z3479 = x3479 + z3480 = x3480 + z3481 = x3481 + z3482 = x3482 + z3483 = x3483 + z3484 = x3484 + z3485 = x3485 + z3486 = x3486 + z3487 = x3487 + z3488 = x3488 + z3489 = x3489 + z3490 = x3490 + z3491 = x3491 + z3492 = x3492 + z3493 = x3493 + z3494 = x3494 + z3495 = x3495 + z3496 = x3496 + z3497 = x3497 + z3498 = x3498 + z3499 = x3499 + z3500 = x3500 + z3501 = x3501 + z3502 = x3502 + z3503 = x3503 + z3504 = x3504 + z3505 = x3505 + z3506 = x3506 + z3507 = x3507 + z3508 = x3508 + z3509 = x3509 + z3510 = x3510 + z3511 = x3511 + z3512 = x3512 + z3513 = x3513 + z3514 = x3514 + z3515 = x3515 + z3516 = x3516 + z3517 = x3517 + z3518 = x3518 + z3519 = x3519 + z3520 = x3520 + z3521 = x3521 + z3522 = x3522 + z3523 = x3523 + z3524 = x3524 + z3525 = x3525 + z3526 = x3526 + z3527 = x3527 + z3528 = x3528 + z3529 = x3529 + z3530 = x3530 + z3531 = x3531 + z3532 = x3532 + z3533 = x3533 + z3534 = x3534 + z3535 = x3535 + z3536 = x3536 + z3537 = x3537 + z3538 = x3538 + z3539 = x3539 + z3540 = x3540 + z3541 = x3541 + z3542 = x3542 + z3543 = x3543 + z3544 = x3544 + z3545 = x3545 + z3546 = x3546 + z3547 = x3547 + z3548 = x3548 + z3549 = x3549 + z3550 = x3550 + z3551 = x3551 + z3552 = x3552 + z3553 = x3553 + z3554 = x3554 + z3555 = x3555 + z3556 = x3556 + z3557 = x3557 + z3558 = x3558 + z3559 = x3559 + z3560 = x3560 + z3561 = x3561 + z3562 = x3562 + z3563 = x3563 + z3564 = x3564 + z3565 = x3565 + z3566 = x3566 + z3567 = x3567 + z3568 = x3568 + z3569 = x3569 + z3570 = x3570 + z3571 = x3571 + z3572 = x3572 + z3573 = x3573 + z3574 = x3574 + z3575 = x3575 + z3576 = x3576 + z3577 = x3577 + z3578 = x3578 + z3579 = x3579 + z3580 = x3580 + z3581 = x3581 + z3582 = x3582 + z3583 = x3583 + z3584 = x3584 + z3585 = x3585 + z3586 = x3586 + z3587 = x3587 + z3588 = x3588 + z3589 = x3589 + z3590 = x3590 + z3591 = x3591 + z3592 = x3592 + z3593 = x3593 + z3594 = x3594 + z3595 = x3595 + z3596 = x3596 + z3597 = x3597 + z3598 = x3598 + z3599 = x3599 + z3600 = x3600 + z3601 = x3601 + z3602 = x3602 + z3603 = x3603 + z3604 = x3604 + z3605 = x3605 + z3606 = x3606 + z3607 = x3607 + z3608 = x3608 + z3609 = x3609 + z3610 = x3610 + z3611 = x3611 + z3612 = x3612 + z3613 = x3613 + z3614 = x3614 + z3615 = x3615 + z3616 = x3616 + z3617 = x3617 + z3618 = x3618 + z3619 = x3619 + z3620 = x3620 + z3621 = x3621 + z3622 = x3622 + z3623 = x3623 + z3624 = x3624 + z3625 = x3625 + z3626 = x3626 + z3627 = x3627 + z3628 = x3628 + z3629 = x3629 + z3630 = x3630 + z3631 = x3631 + z3632 = x3632 + z3633 = x3633 + z3634 = x3634 + z3635 = x3635 + z3636 = x3636 + z3637 = x3637 + z3638 = x3638 + z3639 = x3639 + z3640 = x3640 + z3641 = x3641 + z3642 = x3642 + z3643 = x3643 + z3644 = x3644 + z3645 = x3645 + z3646 = x3646 + z3647 = x3647 + z3648 = x3648 + z3649 = x3649 + z3650 = x3650 + z3651 = x3651 + z3652 = x3652 + z3653 = x3653 + z3654 = x3654 + z3655 = x3655 + z3656 = x3656 + z3657 = x3657 + z3658 = x3658 + z3659 = x3659 + z3660 = x3660 + z3661 = x3661 + z3662 = x3662 + z3663 = x3663 + z3664 = x3664 + z3665 = x3665 + z3666 = x3666 + z3667 = x3667 + z3668 = x3668 + z3669 = x3669 + z3670 = x3670 + z3671 = x3671 + z3672 = x3672 + z3673 = x3673 + z3674 = x3674 + z3675 = x3675 + z3676 = x3676 + z3677 = x3677 + z3678 = x3678 + z3679 = x3679 + z3680 = x3680 + z3681 = x3681 + z3682 = x3682 + z3683 = x3683 + z3684 = x3684 + z3685 = x3685 + z3686 = x3686 + z3687 = x3687 + z3688 = x3688 + z3689 = x3689 + z3690 = x3690 + z3691 = x3691 + z3692 = x3692 + z3693 = x3693 + z3694 = x3694 + z3695 = x3695 + z3696 = x3696 + z3697 = x3697 + z3698 = x3698 + z3699 = x3699 + z3700 = x3700 + z3701 = x3701 + z3702 = x3702 + z3703 = x3703 + z3704 = x3704 + z3705 = x3705 + z3706 = x3706 + z3707 = x3707 + z3708 = x3708 + z3709 = x3709 + z3710 = x3710 + z3711 = x3711 + z3712 = x3712 + z3713 = x3713 + z3714 = x3714 + z3715 = x3715 + z3716 = x3716 + z3717 = x3717 + z3718 = x3718 + z3719 = x3719 + z3720 = x3720 + z3721 = x3721 + z3722 = x3722 + z3723 = x3723 + z3724 = x3724 + z3725 = x3725 + z3726 = x3726 + z3727 = x3727 + z3728 = x3728 + z3729 = x3729 + z3730 = x3730 + z3731 = x3731 + z3732 = x3732 + z3733 = x3733 + z3734 = x3734 + z3735 = x3735 + z3736 = x3736 + z3737 = x3737 + z3738 = x3738 + z3739 = x3739 + z3740 = x3740 + z3741 = x3741 + z3742 = x3742 + z3743 = x3743 + z3744 = x3744 + z3745 = x3745 + z3746 = x3746 + z3747 = x3747 + z3748 = x3748 + z3749 = x3749 + z3750 = x3750 + z3751 = x3751 + z3752 = x3752 + z3753 = x3753 + z3754 = x3754 + z3755 = x3755 + z3756 = x3756 + z3757 = x3757 + z3758 = x3758 + z3759 = x3759 + z3760 = x3760 + z3761 = x3761 + z3762 = x3762 + z3763 = x3763 + z3764 = x3764 + z3765 = x3765 + z3766 = x3766 + z3767 = x3767 + z3768 = x3768 + z3769 = x3769 + z3770 = x3770 + z3771 = x3771 + z3772 = x3772 + z3773 = x3773 + z3774 = x3774 + z3775 = x3775 + z3776 = x3776 + z3777 = x3777 + z3778 = x3778 + z3779 = x3779 + z3780 = x3780 + z3781 = x3781 + z3782 = x3782 + z3783 = x3783 + z3784 = x3784 + z3785 = x3785 + z3786 = x3786 + z3787 = x3787 + z3788 = x3788 + z3789 = x3789 + z3790 = x3790 + z3791 = x3791 + z3792 = x3792 + z3793 = x3793 + z3794 = x3794 + z3795 = x3795 + z3796 = x3796 + z3797 = x3797 + z3798 = x3798 + z3799 = x3799 + z3800 = x3800 + z3801 = x3801 + z3802 = x3802 + z3803 = x3803 + z3804 = x3804 + z3805 = x3805 + z3806 = x3806 + z3807 = x3807 + z3808 = x3808 + z3809 = x3809 + z3810 = x3810 + z3811 = x3811 + z3812 = x3812 + z3813 = x3813 + z3814 = x3814 + z3815 = x3815 + z3816 = x3816 + z3817 = x3817 + z3818 = x3818 + z3819 = x3819 + z3820 = x3820 + z3821 = x3821 + z3822 = x3822 + z3823 = x3823 + z3824 = x3824 + z3825 = x3825 + z3826 = x3826 + z3827 = x3827 + z3828 = x3828 + z3829 = x3829 + z3830 = x3830 + z3831 = x3831 + z3832 = x3832 + z3833 = x3833 + z3834 = x3834 + z3835 = x3835 + z3836 = x3836 + z3837 = x3837 + z3838 = x3838 + z3839 = x3839 + z3840 = x3840 + z3841 = x3841 + z3842 = x3842 + z3843 = x3843 + z3844 = x3844 + z3845 = x3845 + z3846 = x3846 + z3847 = x3847 + z3848 = x3848 + z3849 = x3849 + z3850 = x3850 + z3851 = x3851 + z3852 = x3852 + z3853 = x3853 + z3854 = x3854 + z3855 = x3855 + z3856 = x3856 + z3857 = x3857 + z3858 = x3858 + z3859 = x3859 + z3860 = x3860 + z3861 = x3861 + z3862 = x3862 + z3863 = x3863 + z3864 = x3864 + z3865 = x3865 + z3866 = x3866 + z3867 = x3867 + z3868 = x3868 + z3869 = x3869 + z3870 = x3870 + z3871 = x3871 + z3872 = x3872 + z3873 = x3873 + z3874 = x3874 + z3875 = x3875 + z3876 = x3876 + z3877 = x3877 + z3878 = x3878 + z3879 = x3879 + z3880 = x3880 + z3881 = x3881 + z3882 = x3882 + z3883 = x3883 + z3884 = x3884 + z3885 = x3885 + z3886 = x3886 + z3887 = x3887 + z3888 = x3888 + z3889 = x3889 + z3890 = x3890 + z3891 = x3891 + z3892 = x3892 + z3893 = x3893 + z3894 = x3894 + z3895 = x3895 + z3896 = x3896 + z3897 = x3897 + z3898 = x3898 + z3899 = x3899 + z3900 = x3900 + z3901 = x3901 + z3902 = x3902 + z3903 = x3903 + z3904 = x3904 + z3905 = x3905 + z3906 = x3906 + z3907 = x3907 + z3908 = x3908 + z3909 = x3909 + z3910 = x3910 + z3911 = x3911 + z3912 = x3912 + z3913 = x3913 + z3914 = x3914 + z3915 = x3915 + z3916 = x3916 + z3917 = x3917 + z3918 = x3918 + z3919 = x3919 + z3920 = x3920 + z3921 = x3921 + z3922 = x3922 + z3923 = x3923 + z3924 = x3924 + z3925 = x3925 + z3926 = x3926 + z3927 = x3927 + z3928 = x3928 + z3929 = x3929 + z3930 = x3930 + z3931 = x3931 + z3932 = x3932 + z3933 = x3933 + z3934 = x3934 + z3935 = x3935 + z3936 = x3936 + z3937 = x3937 + z3938 = x3938 + z3939 = x3939 + z3940 = x3940 + z3941 = x3941 + z3942 = x3942 + z3943 = x3943 + z3944 = x3944 + z3945 = x3945 + z3946 = x3946 + z3947 = x3947 + z3948 = x3948 + z3949 = x3949 + z3950 = x3950 + z3951 = x3951 + z3952 = x3952 + z3953 = x3953 + z3954 = x3954 + z3955 = x3955 + z3956 = x3956 + z3957 = x3957 + z3958 = x3958 + z3959 = x3959 + z3960 = x3960 + z3961 = x3961 + z3962 = x3962 + z3963 = x3963 + z3964 = x3964 + z3965 = x3965 + z3966 = x3966 + z3967 = x3967 + z3968 = x3968 + z3969 = x3969 + z3970 = x3970 + z3971 = x3971 + z3972 = x3972 + z3973 = x3973 + z3974 = x3974 + z3975 = x3975 + z3976 = x3976 + z3977 = x3977 + z3978 = x3978 + z3979 = x3979 + z3980 = x3980 + z3981 = x3981 + z3982 = x3982 + z3983 = x3983 + z3984 = x3984 + z3985 = x3985 + z3986 = x3986 + z3987 = x3987 + z3988 = x3988 + z3989 = x3989 + z3990 = x3990 + z3991 = x3991 + z3992 = x3992 + z3993 = x3993 + z3994 = x3994 + z3995 = x3995 + z3996 = x3996 + z3997 = x3997 + z3998 = x3998 + z3999 = x3999 + z4000 = x4000 + z4001 = x4001 + z4002 = x4002 + z4003 = x4003 + z4004 = x4004 + z4005 = x4005 + z4006 = x4006 + z4007 = x4007 + z4008 = x4008 + z4009 = x4009 + z4010 = x4010 + z4011 = x4011 + z4012 = x4012 + z4013 = x4013 + z4014 = x4014 + z4015 = x4015 + z4016 = x4016 + z4017 = x4017 + z4018 = x4018 + z4019 = x4019 + z4020 = x4020 + z4021 = x4021 + z4022 = x4022 + z4023 = x4023 + z4024 = x4024 + z4025 = x4025 + z4026 = x4026 + z4027 = x4027 + z4028 = x4028 + z4029 = x4029 + z4030 = x4030 + z4031 = x4031 + z4032 = x4032 + z4033 = x4033 + z4034 = x4034 + z4035 = x4035 + z4036 = x4036 + z4037 = x4037 + z4038 = x4038 + z4039 = x4039 + z4040 = x4040 + z4041 = x4041 + z4042 = x4042 + z4043 = x4043 + z4044 = x4044 + z4045 = x4045 + z4046 = x4046 + z4047 = x4047 + z4048 = x4048 + z4049 = x4049 + z4050 = x4050 + z4051 = x4051 + z4052 = x4052 + z4053 = x4053 + z4054 = x4054 + z4055 = x4055 + z4056 = x4056 + z4057 = x4057 + z4058 = x4058 + z4059 = x4059 + z4060 = x4060 + z4061 = x4061 + z4062 = x4062 + z4063 = x4063 + z4064 = x4064 + z4065 = x4065 + z4066 = x4066 + z4067 = x4067 + z4068 = x4068 + z4069 = x4069 + z4070 = x4070 + z4071 = x4071 + z4072 = x4072 + z4073 = x4073 + z4074 = x4074 + z4075 = x4075 + z4076 = x4076 + z4077 = x4077 + z4078 = x4078 + z4079 = x4079 + z4080 = x4080 + z4081 = x4081 + z4082 = x4082 + z4083 = x4083 + z4084 = x4084 + z4085 = x4085 + z4086 = x4086 + z4087 = x4087 + z4088 = x4088 + z4089 = x4089 + z4090 = x4090 + z4091 = x4091 + z4092 = x4092 + z4093 = x4093 + z4094 = x4094 + z4095 = x4095 + z4096 = x4096 + z4097 = x4097 + z4098 = x4098 + z4099 = x4099 + z4100 = x4100 + z4101 = x4101 + z4102 = x4102 + z4103 = x4103 + z4104 = x4104 + z4105 = x4105 + z4106 = x4106 + z4107 = x4107 + z4108 = x4108 + z4109 = x4109 + z4110 = x4110 + z4111 = x4111 + z4112 = x4112 + z4113 = x4113 + z4114 = x4114 + z4115 = x4115 + z4116 = x4116 + z4117 = x4117 + z4118 = x4118 + z4119 = x4119 + z4120 = x4120 + z4121 = x4121 + z4122 = x4122 + z4123 = x4123 + z4124 = x4124 + z4125 = x4125 + z4126 = x4126 + z4127 = x4127 + z4128 = x4128 + z4129 = x4129 + z4130 = x4130 + z4131 = x4131 + z4132 = x4132 + z4133 = x4133 + z4134 = x4134 + z4135 = x4135 + z4136 = x4136 + z4137 = x4137 + z4138 = x4138 + z4139 = x4139 + z4140 = x4140 + z4141 = x4141 + z4142 = x4142 + z4143 = x4143 + z4144 = x4144 + z4145 = x4145 + z4146 = x4146 + z4147 = x4147 + z4148 = x4148 + z4149 = x4149 + z4150 = x4150 + z4151 = x4151 + z4152 = x4152 + z4153 = x4153 + z4154 = x4154 + z4155 = x4155 + z4156 = x4156 + z4157 = x4157 + z4158 = x4158 + z4159 = x4159 + z4160 = x4160 + z4161 = x4161 + z4162 = x4162 + z4163 = x4163 + z4164 = x4164 + z4165 = x4165 + z4166 = x4166 + z4167 = x4167 + z4168 = x4168 + z4169 = x4169 + z4170 = x4170 + z4171 = x4171 + z4172 = x4172 + z4173 = x4173 + z4174 = x4174 + z4175 = x4175 + z4176 = x4176 + z4177 = x4177 + z4178 = x4178 + z4179 = x4179 + z4180 = x4180 + z4181 = x4181 + z4182 = x4182 + z4183 = x4183 + z4184 = x4184 + z4185 = x4185 + z4186 = x4186 + z4187 = x4187 + z4188 = x4188 + z4189 = x4189 + z4190 = x4190 + z4191 = x4191 + z4192 = x4192 + z4193 = x4193 + z4194 = x4194 + z4195 = x4195 + z4196 = x4196 + z4197 = x4197 + z4198 = x4198 + z4199 = x4199 + z4200 = x4200 + z4201 = x4201 + z4202 = x4202 + z4203 = x4203 + z4204 = x4204 + z4205 = x4205 + z4206 = x4206 + z4207 = x4207 + z4208 = x4208 + z4209 = x4209 + z4210 = x4210 + z4211 = x4211 + z4212 = x4212 + z4213 = x4213 + z4214 = x4214 + z4215 = x4215 + z4216 = x4216 + z4217 = x4217 + z4218 = x4218 + z4219 = x4219 + z4220 = x4220 + z4221 = x4221 + z4222 = x4222 + z4223 = x4223 + z4224 = x4224 + z4225 = x4225 + z4226 = x4226 + z4227 = x4227 + z4228 = x4228 + z4229 = x4229 + z4230 = x4230 + z4231 = x4231 + z4232 = x4232 + z4233 = x4233 + z4234 = x4234 + z4235 = x4235 + z4236 = x4236 + z4237 = x4237 + z4238 = x4238 + z4239 = x4239 + z4240 = x4240 + z4241 = x4241 + z4242 = x4242 + z4243 = x4243 + z4244 = x4244 + z4245 = x4245 + z4246 = x4246 + z4247 = x4247 + z4248 = x4248 + z4249 = x4249 + z4250 = x4250 + z4251 = x4251 + z4252 = x4252 + z4253 = x4253 + z4254 = x4254 + z4255 = x4255 + z4256 = x4256 + z4257 = x4257 + z4258 = x4258 + z4259 = x4259 + z4260 = x4260 + z4261 = x4261 + z4262 = x4262 + z4263 = x4263 + z4264 = x4264 + z4265 = x4265 + z4266 = x4266 + z4267 = x4267 + z4268 = x4268 + z4269 = x4269 + z4270 = x4270 + z4271 = x4271 + z4272 = x4272 + z4273 = x4273 + z4274 = x4274 + z4275 = x4275 + z4276 = x4276 + z4277 = x4277 + z4278 = x4278 + z4279 = x4279 + z4280 = x4280 + z4281 = x4281 + z4282 = x4282 + z4283 = x4283 + z4284 = x4284 + z4285 = x4285 + z4286 = x4286 + z4287 = x4287 + z4288 = x4288 + z4289 = x4289 + z4290 = x4290 + z4291 = x4291 + z4292 = x4292 + z4293 = x4293 + z4294 = x4294 + z4295 = x4295 + z4296 = x4296 + z4297 = x4297 + z4298 = x4298 + z4299 = x4299 + z4300 = x4300 + z4301 = x4301 + z4302 = x4302 + z4303 = x4303 + z4304 = x4304 + z4305 = x4305 + z4306 = x4306 + z4307 = x4307 + z4308 = x4308 + z4309 = x4309 + z4310 = x4310 + z4311 = x4311 + z4312 = x4312 + z4313 = x4313 + z4314 = x4314 + z4315 = x4315 + z4316 = x4316 + z4317 = x4317 + z4318 = x4318 + z4319 = x4319 + z4320 = x4320 + z4321 = x4321 + z4322 = x4322 + z4323 = x4323 + z4324 = x4324 + z4325 = x4325 + z4326 = x4326 + z4327 = x4327 + z4328 = x4328 + z4329 = x4329 + z4330 = x4330 + z4331 = x4331 + z4332 = x4332 + z4333 = x4333 + z4334 = x4334 + z4335 = x4335 + z4336 = x4336 + z4337 = x4337 + z4338 = x4338 + z4339 = x4339 + z4340 = x4340 + z4341 = x4341 + z4342 = x4342 + z4343 = x4343 + z4344 = x4344 + z4345 = x4345 + z4346 = x4346 + z4347 = x4347 + z4348 = x4348 + z4349 = x4349 + z4350 = x4350 + z4351 = x4351 + z4352 = x4352 + z4353 = x4353 + z4354 = x4354 + z4355 = x4355 + z4356 = x4356 + z4357 = x4357 + z4358 = x4358 + z4359 = x4359 + z4360 = x4360 + z4361 = x4361 + z4362 = x4362 + z4363 = x4363 + z4364 = x4364 + z4365 = x4365 + z4366 = x4366 + z4367 = x4367 + z4368 = x4368 + z4369 = x4369 + z4370 = x4370 + z4371 = x4371 + z4372 = x4372 + z4373 = x4373 + z4374 = x4374 + z4375 = x4375 + z4376 = x4376 + z4377 = x4377 + z4378 = x4378 + z4379 = x4379 + z4380 = x4380 + z4381 = x4381 + z4382 = x4382 + z4383 = x4383 + z4384 = x4384 + z4385 = x4385 + z4386 = x4386 + z4387 = x4387 + z4388 = x4388 + z4389 = x4389 + z4390 = x4390 + z4391 = x4391 + z4392 = x4392 + z4393 = x4393 + z4394 = x4394 + z4395 = x4395 + z4396 = x4396 + z4397 = x4397 + z4398 = x4398 + z4399 = x4399 + z4400 = x4400 + z4401 = x4401 + z4402 = x4402 + z4403 = x4403 + z4404 = x4404 + z4405 = x4405 + z4406 = x4406 + z4407 = x4407 + z4408 = x4408 + z4409 = x4409 + z4410 = x4410 + z4411 = x4411 + z4412 = x4412 + z4413 = x4413 + z4414 = x4414 + z4415 = x4415 + z4416 = x4416 + z4417 = x4417 + z4418 = x4418 + z4419 = x4419 + z4420 = x4420 + z4421 = x4421 + z4422 = x4422 + z4423 = x4423 + z4424 = x4424 + z4425 = x4425 + z4426 = x4426 + z4427 = x4427 + z4428 = x4428 + z4429 = x4429 + z4430 = x4430 + z4431 = x4431 + z4432 = x4432 + z4433 = x4433 + z4434 = x4434 + z4435 = x4435 + z4436 = x4436 + z4437 = x4437 + z4438 = x4438 + z4439 = x4439 + z4440 = x4440 + z4441 = x4441 + z4442 = x4442 + z4443 = x4443 + z4444 = x4444 + z4445 = x4445 + z4446 = x4446 + z4447 = x4447 + z4448 = x4448 + z4449 = x4449 + z4450 = x4450 + z4451 = x4451 + z4452 = x4452 + z4453 = x4453 + z4454 = x4454 + z4455 = x4455 + z4456 = x4456 + z4457 = x4457 + z4458 = x4458 + z4459 = x4459 + z4460 = x4460 + z4461 = x4461 + z4462 = x4462 + z4463 = x4463 + z4464 = x4464 + z4465 = x4465 + z4466 = x4466 + z4467 = x4467 + z4468 = x4468 + z4469 = x4469 + z4470 = x4470 + z4471 = x4471 + z4472 = x4472 + z4473 = x4473 + z4474 = x4474 + z4475 = x4475 + z4476 = x4476 + z4477 = x4477 + z4478 = x4478 + z4479 = x4479 + z4480 = x4480 + z4481 = x4481 + z4482 = x4482 + z4483 = x4483 + z4484 = x4484 + z4485 = x4485 + z4486 = x4486 + z4487 = x4487 + z4488 = x4488 + z4489 = x4489 + z4490 = x4490 + z4491 = x4491 + z4492 = x4492 + z4493 = x4493 + z4494 = x4494 + z4495 = x4495 + z4496 = x4496 + z4497 = x4497 + z4498 = x4498 + z4499 = x4499 + z4500 = x4500 + z4501 = x4501 + z4502 = x4502 + z4503 = x4503 + z4504 = x4504 + z4505 = x4505 + z4506 = x4506 + z4507 = x4507 + z4508 = x4508 + z4509 = x4509 + z4510 = x4510 + z4511 = x4511 + z4512 = x4512 + z4513 = x4513 + z4514 = x4514 + z4515 = x4515 + z4516 = x4516 + z4517 = x4517 + z4518 = x4518 + z4519 = x4519 + z4520 = x4520 + z4521 = x4521 + z4522 = x4522 + z4523 = x4523 + z4524 = x4524 + z4525 = x4525 + z4526 = x4526 + z4527 = x4527 + z4528 = x4528 + z4529 = x4529 + z4530 = x4530 + z4531 = x4531 + z4532 = x4532 + z4533 = x4533 + z4534 = x4534 + z4535 = x4535 + z4536 = x4536 + z4537 = x4537 + z4538 = x4538 + z4539 = x4539 + z4540 = x4540 + z4541 = x4541 + z4542 = x4542 + z4543 = x4543 + z4544 = x4544 + z4545 = x4545 + z4546 = x4546 + z4547 = x4547 + z4548 = x4548 + z4549 = x4549 + z4550 = x4550 + z4551 = x4551 + z4552 = x4552 + z4553 = x4553 + z4554 = x4554 + z4555 = x4555 + z4556 = x4556 + z4557 = x4557 + z4558 = x4558 + z4559 = x4559 + z4560 = x4560 + z4561 = x4561 + z4562 = x4562 + z4563 = x4563 + z4564 = x4564 + z4565 = x4565 + z4566 = x4566 + z4567 = x4567 + z4568 = x4568 + z4569 = x4569 + z4570 = x4570 + z4571 = x4571 + z4572 = x4572 + z4573 = x4573 + z4574 = x4574 + z4575 = x4575 + z4576 = x4576 + z4577 = x4577 + z4578 = x4578 + z4579 = x4579 + z4580 = x4580 + z4581 = x4581 + z4582 = x4582 + z4583 = x4583 + z4584 = x4584 + z4585 = x4585 + z4586 = x4586 + z4587 = x4587 + z4588 = x4588 + z4589 = x4589 + z4590 = x4590 + z4591 = x4591 + z4592 = x4592 + z4593 = x4593 + z4594 = x4594 + z4595 = x4595 + z4596 = x4596 + z4597 = x4597 + z4598 = x4598 + z4599 = x4599 + z4600 = x4600 + z4601 = x4601 + z4602 = x4602 + z4603 = x4603 + z4604 = x4604 + z4605 = x4605 + z4606 = x4606 + z4607 = x4607 + z4608 = x4608 + z4609 = x4609 + z4610 = x4610 + z4611 = x4611 + z4612 = x4612 + z4613 = x4613 + z4614 = x4614 + z4615 = x4615 + z4616 = x4616 + z4617 = x4617 + z4618 = x4618 + z4619 = x4619 + z4620 = x4620 + z4621 = x4621 + z4622 = x4622 + z4623 = x4623 + z4624 = x4624 + z4625 = x4625 + z4626 = x4626 + z4627 = x4627 + z4628 = x4628 + z4629 = x4629 + z4630 = x4630 + z4631 = x4631 + z4632 = x4632 + z4633 = x4633 + z4634 = x4634 + z4635 = x4635 + z4636 = x4636 + z4637 = x4637 + z4638 = x4638 + z4639 = x4639 + z4640 = x4640 + z4641 = x4641 + z4642 = x4642 + z4643 = x4643 + z4644 = x4644 + z4645 = x4645 + z4646 = x4646 + z4647 = x4647 + z4648 = x4648 + z4649 = x4649 + z4650 = x4650 + z4651 = x4651 + z4652 = x4652 + z4653 = x4653 + z4654 = x4654 + z4655 = x4655 + z4656 = x4656 + z4657 = x4657 + z4658 = x4658 + z4659 = x4659 + z4660 = x4660 + z4661 = x4661 + z4662 = x4662 + z4663 = x4663 + z4664 = x4664 + z4665 = x4665 + z4666 = x4666 + z4667 = x4667 + z4668 = x4668 + z4669 = x4669 + z4670 = x4670 + z4671 = x4671 + z4672 = x4672 + z4673 = x4673 + z4674 = x4674 + z4675 = x4675 + z4676 = x4676 + z4677 = x4677 + z4678 = x4678 + z4679 = x4679 + z4680 = x4680 + z4681 = x4681 + z4682 = x4682 + z4683 = x4683 + z4684 = x4684 + z4685 = x4685 + z4686 = x4686 + z4687 = x4687 + z4688 = x4688 + z4689 = x4689 + z4690 = x4690 + z4691 = x4691 + z4692 = x4692 + z4693 = x4693 + z4694 = x4694 + z4695 = x4695 + z4696 = x4696 + z4697 = x4697 + z4698 = x4698 + z4699 = x4699 + z4700 = x4700 + z4701 = x4701 + z4702 = x4702 + z4703 = x4703 + z4704 = x4704 + z4705 = x4705 + z4706 = x4706 + z4707 = x4707 + z4708 = x4708 + z4709 = x4709 + z4710 = x4710 + z4711 = x4711 + z4712 = x4712 + z4713 = x4713 + z4714 = x4714 + z4715 = x4715 + z4716 = x4716 + z4717 = x4717 + z4718 = x4718 + z4719 = x4719 + z4720 = x4720 + z4721 = x4721 + z4722 = x4722 + z4723 = x4723 + z4724 = x4724 + z4725 = x4725 + z4726 = x4726 + z4727 = x4727 + z4728 = x4728 + z4729 = x4729 + z4730 = x4730 + z4731 = x4731 + z4732 = x4732 + z4733 = x4733 + z4734 = x4734 + z4735 = x4735 + z4736 = x4736 + z4737 = x4737 + z4738 = x4738 + z4739 = x4739 + z4740 = x4740 + z4741 = x4741 + z4742 = x4742 + z4743 = x4743 + z4744 = x4744 + z4745 = x4745 + z4746 = x4746 + z4747 = x4747 + z4748 = x4748 + z4749 = x4749 + z4750 = x4750 + z4751 = x4751 + z4752 = x4752 + z4753 = x4753 + z4754 = x4754 + z4755 = x4755 + z4756 = x4756 + z4757 = x4757 + z4758 = x4758 + z4759 = x4759 + z4760 = x4760 + z4761 = x4761 + z4762 = x4762 + z4763 = x4763 + z4764 = x4764 + z4765 = x4765 + z4766 = x4766 + z4767 = x4767 + z4768 = x4768 + z4769 = x4769 + z4770 = x4770 + z4771 = x4771 + z4772 = x4772 + z4773 = x4773 + z4774 = x4774 + z4775 = x4775 + z4776 = x4776 + z4777 = x4777 + z4778 = x4778 + z4779 = x4779 + z4780 = x4780 + z4781 = x4781 + z4782 = x4782 + z4783 = x4783 + z4784 = x4784 + z4785 = x4785 + z4786 = x4786 + z4787 = x4787 + z4788 = x4788 + z4789 = x4789 + z4790 = x4790 + z4791 = x4791 + z4792 = x4792 + z4793 = x4793 + z4794 = x4794 + z4795 = x4795 + z4796 = x4796 + z4797 = x4797 + z4798 = x4798 + z4799 = x4799 + z4800 = x4800 + z4801 = x4801 + z4802 = x4802 + z4803 = x4803 + z4804 = x4804 + z4805 = x4805 + z4806 = x4806 + z4807 = x4807 + z4808 = x4808 + z4809 = x4809 + z4810 = x4810 + z4811 = x4811 + z4812 = x4812 + z4813 = x4813 + z4814 = x4814 + z4815 = x4815 + z4816 = x4816 + z4817 = x4817 + z4818 = x4818 + z4819 = x4819 + z4820 = x4820 + z4821 = x4821 + z4822 = x4822 + z4823 = x4823 + z4824 = x4824 + z4825 = x4825 + z4826 = x4826 + z4827 = x4827 + z4828 = x4828 + z4829 = x4829 + z4830 = x4830 + z4831 = x4831 + z4832 = x4832 + z4833 = x4833 + z4834 = x4834 + z4835 = x4835 + z4836 = x4836 + z4837 = x4837 + z4838 = x4838 + z4839 = x4839 + z4840 = x4840 + z4841 = x4841 + z4842 = x4842 + z4843 = x4843 + z4844 = x4844 + z4845 = x4845 + z4846 = x4846 + z4847 = x4847 + z4848 = x4848 + z4849 = x4849 + z4850 = x4850 + z4851 = x4851 + z4852 = x4852 + z4853 = x4853 + z4854 = x4854 + z4855 = x4855 + z4856 = x4856 + z4857 = x4857 + z4858 = x4858 + z4859 = x4859 + z4860 = x4860 + z4861 = x4861 + z4862 = x4862 + z4863 = x4863 + z4864 = x4864 + z4865 = x4865 + z4866 = x4866 + z4867 = x4867 + z4868 = x4868 + z4869 = x4869 + z4870 = x4870 + z4871 = x4871 + z4872 = x4872 + z4873 = x4873 + z4874 = x4874 + z4875 = x4875 + z4876 = x4876 + z4877 = x4877 + z4878 = x4878 + z4879 = x4879 + z4880 = x4880 + z4881 = x4881 + z4882 = x4882 + z4883 = x4883 + z4884 = x4884 + z4885 = x4885 + z4886 = x4886 + z4887 = x4887 + z4888 = x4888 + z4889 = x4889 + z4890 = x4890 + z4891 = x4891 + z4892 = x4892 + z4893 = x4893 + z4894 = x4894 + z4895 = x4895 + z4896 = x4896 + z4897 = x4897 + z4898 = x4898 + z4899 = x4899 + z4900 = x4900 + z4901 = x4901 + z4902 = x4902 + z4903 = x4903 + z4904 = x4904 + z4905 = x4905 + z4906 = x4906 + z4907 = x4907 + z4908 = x4908 + z4909 = x4909 + z4910 = x4910 + z4911 = x4911 + z4912 = x4912 + z4913 = x4913 + z4914 = x4914 + z4915 = x4915 + z4916 = x4916 + z4917 = x4917 + z4918 = x4918 + z4919 = x4919 + z4920 = x4920 + z4921 = x4921 + z4922 = x4922 + z4923 = x4923 + z4924 = x4924 + z4925 = x4925 + z4926 = x4926 + z4927 = x4927 + z4928 = x4928 + z4929 = x4929 + z4930 = x4930 + z4931 = x4931 + z4932 = x4932 + z4933 = x4933 + z4934 = x4934 + z4935 = x4935 + z4936 = x4936 + z4937 = x4937 + z4938 = x4938 + z4939 = x4939 + z4940 = x4940 + z4941 = x4941 + z4942 = x4942 + z4943 = x4943 + z4944 = x4944 + z4945 = x4945 + z4946 = x4946 + z4947 = x4947 + z4948 = x4948 + z4949 = x4949 + z4950 = x4950 + z4951 = x4951 + z4952 = x4952 + z4953 = x4953 + z4954 = x4954 + z4955 = x4955 + z4956 = x4956 + z4957 = x4957 + z4958 = x4958 + z4959 = x4959 + z4960 = x4960 + z4961 = x4961 + z4962 = x4962 + z4963 = x4963 + z4964 = x4964 + z4965 = x4965 + z4966 = x4966 + z4967 = x4967 + z4968 = x4968 + z4969 = x4969 + z4970 = x4970 + z4971 = x4971 + z4972 = x4972 + z4973 = x4973 + z4974 = x4974 + z4975 = x4975 + z4976 = x4976 + z4977 = x4977 + z4978 = x4978 + z4979 = x4979 + z4980 = x4980 + z4981 = x4981 + z4982 = x4982 + z4983 = x4983 + z4984 = x4984 + z4985 = x4985 + z4986 = x4986 + z4987 = x4987 + z4988 = x4988 + z4989 = x4989 + z4990 = x4990 + z4991 = x4991 + z4992 = x4992 + z4993 = x4993 + z4994 = x4994 + z4995 = x4995 + z4996 = x4996 + z4997 = x4997 + z4998 = x4998 + z4999 = x4999 + z5000 = x5000 + z5001 = x5001 + z5002 = x5002 + z5003 = x5003 + z5004 = x5004 + z5005 = x5005 + z5006 = x5006 + z5007 = x5007 + z5008 = x5008 + z5009 = x5009 + z5010 = x5010 + z5011 = x5011 + z5012 = x5012 + z5013 = x5013 + z5014 = x5014 + z5015 = x5015 + z5016 = x5016 + z5017 = x5017 + z5018 = x5018 + z5019 = x5019 + z5020 = x5020 + z5021 = x5021 + z5022 = x5022 + z5023 = x5023 + z5024 = x5024 + z5025 = x5025 + z5026 = x5026 + z5027 = x5027 + z5028 = x5028 + z5029 = x5029 + z5030 = x5030 + z5031 = x5031 + z5032 = x5032 + z5033 = x5033 + z5034 = x5034 + z5035 = x5035 + z5036 = x5036 + z5037 = x5037 + z5038 = x5038 + z5039 = x5039 + z5040 = x5040 + z5041 = x5041 + z5042 = x5042 + z5043 = x5043 + z5044 = x5044 + z5045 = x5045 + z5046 = x5046 + z5047 = x5047 + z5048 = x5048 + z5049 = x5049 + z5050 = x5050 + z5051 = x5051 + z5052 = x5052 + z5053 = x5053 + z5054 = x5054 + z5055 = x5055 + z5056 = x5056 + z5057 = x5057 + z5058 = x5058 + z5059 = x5059 + z5060 = x5060 + z5061 = x5061 + z5062 = x5062 + z5063 = x5063 + z5064 = x5064 + z5065 = x5065 + z5066 = x5066 + z5067 = x5067 + z5068 = x5068 + z5069 = x5069 + z5070 = x5070 + z5071 = x5071 + z5072 = x5072 + z5073 = x5073 + z5074 = x5074 + z5075 = x5075 + z5076 = x5076 + z5077 = x5077 + z5078 = x5078 + z5079 = x5079 + z5080 = x5080 + z5081 = x5081 + z5082 = x5082 + z5083 = x5083 + z5084 = x5084 + z5085 = x5085 + z5086 = x5086 + z5087 = x5087 + z5088 = x5088 + z5089 = x5089 + z5090 = x5090 + z5091 = x5091 + z5092 = x5092 + z5093 = x5093 + z5094 = x5094 + z5095 = x5095 + z5096 = x5096 + z5097 = x5097 + z5098 = x5098 + z5099 = x5099 + z5100 = x5100 + z5101 = x5101 + z5102 = x5102 + z5103 = x5103 + z5104 = x5104 + z5105 = x5105 + z5106 = x5106 + z5107 = x5107 + z5108 = x5108 + z5109 = x5109 + z5110 = x5110 + z5111 = x5111 + z5112 = x5112 + z5113 = x5113 + z5114 = x5114 + z5115 = x5115 + z5116 = x5116 + z5117 = x5117 + z5118 = x5118 + z5119 = x5119 + z5120 = x5120 + z5121 = x5121 + z5122 = x5122 + z5123 = x5123 + z5124 = x5124 + z5125 = x5125 + z5126 = x5126 + z5127 = x5127 + z5128 = x5128 + z5129 = x5129 + z5130 = x5130 + z5131 = x5131 + z5132 = x5132 + z5133 = x5133 + z5134 = x5134 + z5135 = x5135 + z5136 = x5136 + z5137 = x5137 + z5138 = x5138 + z5139 = x5139 + z5140 = x5140 + z5141 = x5141 + z5142 = x5142 + z5143 = x5143 + z5144 = x5144 + z5145 = x5145 + z5146 = x5146 + z5147 = x5147 + z5148 = x5148 + z5149 = x5149 + z5150 = x5150 + z5151 = x5151 + z5152 = x5152 + z5153 = x5153 + z5154 = x5154 + z5155 = x5155 + z5156 = x5156 + z5157 = x5157 + z5158 = x5158 + z5159 = x5159 + z5160 = x5160 + z5161 = x5161 + z5162 = x5162 + z5163 = x5163 + z5164 = x5164 + z5165 = x5165 + z5166 = x5166 + z5167 = x5167 + z5168 = x5168 + z5169 = x5169 + z5170 = x5170 + z5171 = x5171 + z5172 = x5172 + z5173 = x5173 + z5174 = x5174 + z5175 = x5175 + z5176 = x5176 + z5177 = x5177 + z5178 = x5178 + z5179 = x5179 + z5180 = x5180 + z5181 = x5181 + z5182 = x5182 + z5183 = x5183 + z5184 = x5184 + z5185 = x5185 + z5186 = x5186 + z5187 = x5187 + z5188 = x5188 + z5189 = x5189 + z5190 = x5190 + z5191 = x5191 + z5192 = x5192 + z5193 = x5193 + z5194 = x5194 + z5195 = x5195 + z5196 = x5196 + z5197 = x5197 + z5198 = x5198 + z5199 = x5199 + z5200 = x5200 + z5201 = x5201 + z5202 = x5202 + z5203 = x5203 + z5204 = x5204 + z5205 = x5205 + z5206 = x5206 + z5207 = x5207 + z5208 = x5208 + z5209 = x5209 + z5210 = x5210 + z5211 = x5211 + z5212 = x5212 + z5213 = x5213 + z5214 = x5214 + z5215 = x5215 + z5216 = x5216 + z5217 = x5217 + z5218 = x5218 + z5219 = x5219 + z5220 = x5220 + z5221 = x5221 + z5222 = x5222 + z5223 = x5223 + z5224 = x5224 + z5225 = x5225 + z5226 = x5226 + z5227 = x5227 + z5228 = x5228 + z5229 = x5229 + z5230 = x5230 + z5231 = x5231 + z5232 = x5232 + z5233 = x5233 + z5234 = x5234 + z5235 = x5235 + z5236 = x5236 + z5237 = x5237 + z5238 = x5238 + z5239 = x5239 + z5240 = x5240 + z5241 = x5241 + z5242 = x5242 + z5243 = x5243 + z5244 = x5244 + z5245 = x5245 + z5246 = x5246 + z5247 = x5247 + z5248 = x5248 + z5249 = x5249 + z5250 = x5250 + z5251 = x5251 + z5252 = x5252 + z5253 = x5253 + z5254 = x5254 + z5255 = x5255 + z5256 = x5256 + z5257 = x5257 + z5258 = x5258 + z5259 = x5259 + z5260 = x5260 + z5261 = x5261 + z5262 = x5262 + z5263 = x5263 + z5264 = x5264 + z5265 = x5265 + z5266 = x5266 + z5267 = x5267 + z5268 = x5268 + z5269 = x5269 + z5270 = x5270 + z5271 = x5271 + z5272 = x5272 + z5273 = x5273 + z5274 = x5274 + z5275 = x5275 + z5276 = x5276 + z5277 = x5277 + z5278 = x5278 + z5279 = x5279 + z5280 = x5280 + z5281 = x5281 + z5282 = x5282 + z5283 = x5283 + z5284 = x5284 + z5285 = x5285 + z5286 = x5286 + z5287 = x5287 + z5288 = x5288 + z5289 = x5289 + z5290 = x5290 + z5291 = x5291 + z5292 = x5292 + z5293 = x5293 + z5294 = x5294 + z5295 = x5295 + z5296 = x5296 + z5297 = x5297 + z5298 = x5298 + z5299 = x5299 + z5300 = x5300 + z5301 = x5301 + z5302 = x5302 + z5303 = x5303 + z5304 = x5304 + z5305 = x5305 + z5306 = x5306 + z5307 = x5307 + z5308 = x5308 + z5309 = x5309 + z5310 = x5310 + z5311 = x5311 + z5312 = x5312 + z5313 = x5313 + z5314 = x5314 + z5315 = x5315 + z5316 = x5316 + z5317 = x5317 + z5318 = x5318 + z5319 = x5319 + z5320 = x5320 + z5321 = x5321 + z5322 = x5322 + z5323 = x5323 + z5324 = x5324 + z5325 = x5325 + z5326 = x5326 + z5327 = x5327 + z5328 = x5328 + z5329 = x5329 + z5330 = x5330 + z5331 = x5331 + z5332 = x5332 + z5333 = x5333 + z5334 = x5334 + z5335 = x5335 + z5336 = x5336 + z5337 = x5337 + z5338 = x5338 + z5339 = x5339 + z5340 = x5340 + z5341 = x5341 + z5342 = x5342 + z5343 = x5343 + z5344 = x5344 + z5345 = x5345 + z5346 = x5346 + z5347 = x5347 + z5348 = x5348 + z5349 = x5349 + z5350 = x5350 + z5351 = x5351 + z5352 = x5352 + z5353 = x5353 + z5354 = x5354 + z5355 = x5355 + z5356 = x5356 + z5357 = x5357 + z5358 = x5358 + z5359 = x5359 + z5360 = x5360 + z5361 = x5361 + z5362 = x5362 + z5363 = x5363 + z5364 = x5364 + z5365 = x5365 + z5366 = x5366 + z5367 = x5367 + z5368 = x5368 + z5369 = x5369 + z5370 = x5370 + z5371 = x5371 + z5372 = x5372 + z5373 = x5373 + z5374 = x5374 + z5375 = x5375 + z5376 = x5376 + z5377 = x5377 + z5378 = x5378 + z5379 = x5379 + z5380 = x5380 + z5381 = x5381 + z5382 = x5382 + z5383 = x5383 + z5384 = x5384 + z5385 = x5385 + z5386 = x5386 + z5387 = x5387 + z5388 = x5388 + z5389 = x5389 + z5390 = x5390 + z5391 = x5391 + z5392 = x5392 + z5393 = x5393 + z5394 = x5394 + z5395 = x5395 + z5396 = x5396 + z5397 = x5397 + z5398 = x5398 + z5399 = x5399 + z5400 = x5400 + z5401 = x5401 + z5402 = x5402 + z5403 = x5403 + z5404 = x5404 + z5405 = x5405 + z5406 = x5406 + z5407 = x5407 + z5408 = x5408 + z5409 = x5409 + z5410 = x5410 + z5411 = x5411 + z5412 = x5412 + z5413 = x5413 + z5414 = x5414 + z5415 = x5415 + z5416 = x5416 + z5417 = x5417 + z5418 = x5418 + z5419 = x5419 + z5420 = x5420 + z5421 = x5421 + z5422 = x5422 + z5423 = x5423 + z5424 = x5424 + z5425 = x5425 + z5426 = x5426 + z5427 = x5427 + z5428 = x5428 + z5429 = x5429 + z5430 = x5430 + z5431 = x5431 + z5432 = x5432 + z5433 = x5433 + z5434 = x5434 + z5435 = x5435 + z5436 = x5436 + z5437 = x5437 + z5438 = x5438 + z5439 = x5439 + z5440 = x5440 + z5441 = x5441 + z5442 = x5442 + z5443 = x5443 + z5444 = x5444 + z5445 = x5445 + z5446 = x5446 + z5447 = x5447 + z5448 = x5448 + z5449 = x5449 + z5450 = x5450 + z5451 = x5451 + z5452 = x5452 + z5453 = x5453 + z5454 = x5454 + z5455 = x5455 + z5456 = x5456 + z5457 = x5457 + z5458 = x5458 + z5459 = x5459 + z5460 = x5460 + z5461 = x5461 + z5462 = x5462 + z5463 = x5463 + z5464 = x5464 + z5465 = x5465 + z5466 = x5466 + z5467 = x5467 + z5468 = x5468 + z5469 = x5469 + z5470 = x5470 + z5471 = x5471 + z5472 = x5472 + z5473 = x5473 + z5474 = x5474 + z5475 = x5475 + z5476 = x5476 + z5477 = x5477 + z5478 = x5478 + z5479 = x5479 + z5480 = x5480 + z5481 = x5481 + z5482 = x5482 + z5483 = x5483 + z5484 = x5484 + z5485 = x5485 + z5486 = x5486 + z5487 = x5487 + z5488 = x5488 + z5489 = x5489 + z5490 = x5490 + z5491 = x5491 + z5492 = x5492 + z5493 = x5493 + z5494 = x5494 + z5495 = x5495 + z5496 = x5496 + z5497 = x5497 + z5498 = x5498 + z5499 = x5499 + z5500 = x5500 + z5501 = x5501 + z5502 = x5502 + z5503 = x5503 + z5504 = x5504 + z5505 = x5505 + z5506 = x5506 + z5507 = x5507 + z5508 = x5508 + z5509 = x5509 + z5510 = x5510 + z5511 = x5511 + z5512 = x5512 + z5513 = x5513 + z5514 = x5514 + z5515 = x5515 + z5516 = x5516 + z5517 = x5517 + z5518 = x5518 + z5519 = x5519 + z5520 = x5520 + z5521 = x5521 + z5522 = x5522 + z5523 = x5523 + z5524 = x5524 + z5525 = x5525 + z5526 = x5526 + z5527 = x5527 + z5528 = x5528 + z5529 = x5529 + z5530 = x5530 + z5531 = x5531 + z5532 = x5532 + z5533 = x5533 + z5534 = x5534 + z5535 = x5535 + z5536 = x5536 + z5537 = x5537 + z5538 = x5538 + z5539 = x5539 + z5540 = x5540 + z5541 = x5541 + z5542 = x5542 + z5543 = x5543 + z5544 = x5544 + z5545 = x5545 + z5546 = x5546 + z5547 = x5547 + z5548 = x5548 + z5549 = x5549 + z5550 = x5550 + z5551 = x5551 + z5552 = x5552 + z5553 = x5553 + z5554 = x5554 + z5555 = x5555 + z5556 = x5556 + z5557 = x5557 + z5558 = x5558 + z5559 = x5559 + z5560 = x5560 + z5561 = x5561 + z5562 = x5562 + z5563 = x5563 + z5564 = x5564 + z5565 = x5565 + z5566 = x5566 + z5567 = x5567 + z5568 = x5568 + z5569 = x5569 + z5570 = x5570 + z5571 = x5571 + z5572 = x5572 + z5573 = x5573 + z5574 = x5574 + z5575 = x5575 + z5576 = x5576 + z5577 = x5577 + z5578 = x5578 + z5579 = x5579 + z5580 = x5580 + z5581 = x5581 + z5582 = x5582 + z5583 = x5583 + z5584 = x5584 + z5585 = x5585 + z5586 = x5586 + z5587 = x5587 + z5588 = x5588 + z5589 = x5589 + z5590 = x5590 + z5591 = x5591 + z5592 = x5592 + z5593 = x5593 + z5594 = x5594 + z5595 = x5595 + z5596 = x5596 + z5597 = x5597 + z5598 = x5598 + z5599 = x5599 + z5600 = x5600 + z5601 = x5601 + z5602 = x5602 + z5603 = x5603 + z5604 = x5604 + z5605 = x5605 + z5606 = x5606 + z5607 = x5607 + z5608 = x5608 + z5609 = x5609 + z5610 = x5610 + z5611 = x5611 + z5612 = x5612 + z5613 = x5613 + z5614 = x5614 + z5615 = x5615 + z5616 = x5616 + z5617 = x5617 + z5618 = x5618 + z5619 = x5619 + z5620 = x5620 + z5621 = x5621 + z5622 = x5622 + z5623 = x5623 + z5624 = x5624 + z5625 = x5625 + z5626 = x5626 + z5627 = x5627 + z5628 = x5628 + z5629 = x5629 + z5630 = x5630 + z5631 = x5631 + z5632 = x5632 + z5633 = x5633 + z5634 = x5634 + z5635 = x5635 + z5636 = x5636 + z5637 = x5637 + z5638 = x5638 + z5639 = x5639 + z5640 = x5640 + z5641 = x5641 + z5642 = x5642 + z5643 = x5643 + z5644 = x5644 + z5645 = x5645 + z5646 = x5646 + z5647 = x5647 + z5648 = x5648 + z5649 = x5649 + z5650 = x5650 + z5651 = x5651 + z5652 = x5652 + z5653 = x5653 + z5654 = x5654 + z5655 = x5655 + z5656 = x5656 + z5657 = x5657 + z5658 = x5658 + z5659 = x5659 + z5660 = x5660 + z5661 = x5661 + z5662 = x5662 + z5663 = x5663 + z5664 = x5664 + z5665 = x5665 + z5666 = x5666 + z5667 = x5667 + z5668 = x5668 + z5669 = x5669 + z5670 = x5670 + z5671 = x5671 + z5672 = x5672 + z5673 = x5673 + z5674 = x5674 + z5675 = x5675 + z5676 = x5676 + z5677 = x5677 + z5678 = x5678 + z5679 = x5679 + z5680 = x5680 + z5681 = x5681 + z5682 = x5682 + z5683 = x5683 + z5684 = x5684 + z5685 = x5685 + z5686 = x5686 + z5687 = x5687 + z5688 = x5688 + z5689 = x5689 + z5690 = x5690 + z5691 = x5691 + z5692 = x5692 + z5693 = x5693 + z5694 = x5694 + z5695 = x5695 + z5696 = x5696 + z5697 = x5697 + z5698 = x5698 + z5699 = x5699 + z5700 = x5700 + z5701 = x5701 + z5702 = x5702 + z5703 = x5703 + z5704 = x5704 + z5705 = x5705 + z5706 = x5706 + z5707 = x5707 + z5708 = x5708 + z5709 = x5709 + z5710 = x5710 + z5711 = x5711 + z5712 = x5712 + z5713 = x5713 + z5714 = x5714 + z5715 = x5715 + z5716 = x5716 + z5717 = x5717 + z5718 = x5718 + z5719 = x5719 + z5720 = x5720 + z5721 = x5721 + z5722 = x5722 + z5723 = x5723 + z5724 = x5724 + z5725 = x5725 + z5726 = x5726 + z5727 = x5727 + z5728 = x5728 + z5729 = x5729 + z5730 = x5730 + z5731 = x5731 + z5732 = x5732 + z5733 = x5733 + z5734 = x5734 + z5735 = x5735 + z5736 = x5736 + z5737 = x5737 + z5738 = x5738 + z5739 = x5739 + z5740 = x5740 + z5741 = x5741 + z5742 = x5742 + z5743 = x5743 + z5744 = x5744 + z5745 = x5745 + z5746 = x5746 + z5747 = x5747 + z5748 = x5748 + z5749 = x5749 + z5750 = x5750 + z5751 = x5751 + z5752 = x5752 + z5753 = x5753 + z5754 = x5754 + z5755 = x5755 + z5756 = x5756 + z5757 = x5757 + z5758 = x5758 + z5759 = x5759 + z5760 = x5760 + z5761 = x5761 + z5762 = x5762 + z5763 = x5763 + z5764 = x5764 + z5765 = x5765 + z5766 = x5766 + z5767 = x5767 + z5768 = x5768 + z5769 = x5769 + z5770 = x5770 + z5771 = x5771 + z5772 = x5772 + z5773 = x5773 + z5774 = x5774 + z5775 = x5775 + z5776 = x5776 + z5777 = x5777 + z5778 = x5778 + z5779 = x5779 + z5780 = x5780 + z5781 = x5781 + z5782 = x5782 + z5783 = x5783 + z5784 = x5784 + z5785 = x5785 + z5786 = x5786 + z5787 = x5787 + z5788 = x5788 + z5789 = x5789 + z5790 = x5790 + z5791 = x5791 + z5792 = x5792 + z5793 = x5793 + z5794 = x5794 + z5795 = x5795 + z5796 = x5796 + z5797 = x5797 + z5798 = x5798 + z5799 = x5799 + z5800 = x5800 + z5801 = x5801 + z5802 = x5802 + z5803 = x5803 + z5804 = x5804 + z5805 = x5805 + z5806 = x5806 + z5807 = x5807 + z5808 = x5808 + z5809 = x5809 + z5810 = x5810 + z5811 = x5811 + z5812 = x5812 + z5813 = x5813 + z5814 = x5814 + z5815 = x5815 + z5816 = x5816 + z5817 = x5817 + z5818 = x5818 + z5819 = x5819 + z5820 = x5820 + z5821 = x5821 + z5822 = x5822 + z5823 = x5823 + z5824 = x5824 + z5825 = x5825 + z5826 = x5826 + z5827 = x5827 + z5828 = x5828 + z5829 = x5829 + z5830 = x5830 + z5831 = x5831 + z5832 = x5832 + z5833 = x5833 + z5834 = x5834 + z5835 = x5835 + z5836 = x5836 + z5837 = x5837 + z5838 = x5838 + z5839 = x5839 + z5840 = x5840 + z5841 = x5841 + z5842 = x5842 + z5843 = x5843 + z5844 = x5844 + z5845 = x5845 + z5846 = x5846 + z5847 = x5847 + z5848 = x5848 + z5849 = x5849 + z5850 = x5850 + z5851 = x5851 + z5852 = x5852 + z5853 = x5853 + z5854 = x5854 + z5855 = x5855 + z5856 = x5856 + z5857 = x5857 + z5858 = x5858 + z5859 = x5859 + z5860 = x5860 + z5861 = x5861 + z5862 = x5862 + z5863 = x5863 + z5864 = x5864 + z5865 = x5865 + z5866 = x5866 + z5867 = x5867 + z5868 = x5868 + z5869 = x5869 + z5870 = x5870 + z5871 = x5871 + z5872 = x5872 + z5873 = x5873 + z5874 = x5874 + z5875 = x5875 + z5876 = x5876 + z5877 = x5877 + z5878 = x5878 + z5879 = x5879 + z5880 = x5880 + z5881 = x5881 + z5882 = x5882 + z5883 = x5883 + z5884 = x5884 + z5885 = x5885 + z5886 = x5886 + z5887 = x5887 + z5888 = x5888 + z5889 = x5889 + z5890 = x5890 + z5891 = x5891 + z5892 = x5892 + z5893 = x5893 + z5894 = x5894 + z5895 = x5895 + z5896 = x5896 + z5897 = x5897 + z5898 = x5898 + z5899 = x5899 + z5900 = x5900 + z5901 = x5901 + z5902 = x5902 + z5903 = x5903 + z5904 = x5904 + z5905 = x5905 + z5906 = x5906 + z5907 = x5907 + z5908 = x5908 + z5909 = x5909 + z5910 = x5910 + z5911 = x5911 + z5912 = x5912 + z5913 = x5913 + z5914 = x5914 + z5915 = x5915 + z5916 = x5916 + z5917 = x5917 + z5918 = x5918 + z5919 = x5919 + z5920 = x5920 + z5921 = x5921 + z5922 = x5922 + z5923 = x5923 + z5924 = x5924 + z5925 = x5925 + z5926 = x5926 + z5927 = x5927 + z5928 = x5928 + z5929 = x5929 + z5930 = x5930 + z5931 = x5931 + z5932 = x5932 + z5933 = x5933 + z5934 = x5934 + z5935 = x5935 + z5936 = x5936 + z5937 = x5937 + z5938 = x5938 + z5939 = x5939 + z5940 = x5940 + z5941 = x5941 + z5942 = x5942 + z5943 = x5943 + z5944 = x5944 + z5945 = x5945 + z5946 = x5946 + z5947 = x5947 + z5948 = x5948 + z5949 = x5949 + z5950 = x5950 + z5951 = x5951 + z5952 = x5952 + z5953 = x5953 + z5954 = x5954 + z5955 = x5955 + z5956 = x5956 + z5957 = x5957 + z5958 = x5958 + z5959 = x5959 + z5960 = x5960 + z5961 = x5961 + z5962 = x5962 + z5963 = x5963 + z5964 = x5964 + z5965 = x5965 + z5966 = x5966 + z5967 = x5967 + z5968 = x5968 + z5969 = x5969 + z5970 = x5970 + z5971 = x5971 + z5972 = x5972 + z5973 = x5973 + z5974 = x5974 + z5975 = x5975 + z5976 = x5976 + z5977 = x5977 + z5978 = x5978 + z5979 = x5979 + z5980 = x5980 + z5981 = x5981 + z5982 = x5982 + z5983 = x5983 + z5984 = x5984 + z5985 = x5985 + z5986 = x5986 + z5987 = x5987 + z5988 = x5988 + z5989 = x5989 + z5990 = x5990 + z5991 = x5991 + z5992 = x5992 + z5993 = x5993 + z5994 = x5994 + z5995 = x5995 + z5996 = x5996 + z5997 = x5997 + z5998 = x5998 + z5999 = x5999 + z6000 = x6000 + z6001 = x6001 + z6002 = x6002 + z6003 = x6003 + z6004 = x6004 + z6005 = x6005 + z6006 = x6006 + z6007 = x6007 + z6008 = x6008 + z6009 = x6009 + z6010 = x6010 + z6011 = x6011 + z6012 = x6012 + z6013 = x6013 + z6014 = x6014 + z6015 = x6015 + z6016 = x6016 + z6017 = x6017 + z6018 = x6018 + z6019 = x6019 + z6020 = x6020 + z6021 = x6021 + z6022 = x6022 + z6023 = x6023 + z6024 = x6024 + z6025 = x6025 + z6026 = x6026 + z6027 = x6027 + z6028 = x6028 + z6029 = x6029 + z6030 = x6030 + z6031 = x6031 + z6032 = x6032 + z6033 = x6033 + z6034 = x6034 + z6035 = x6035 + z6036 = x6036 + z6037 = x6037 + z6038 = x6038 + z6039 = x6039 + z6040 = x6040 + z6041 = x6041 + z6042 = x6042 + z6043 = x6043 + z6044 = x6044 + z6045 = x6045 + z6046 = x6046 + z6047 = x6047 + z6048 = x6048 + z6049 = x6049 + z6050 = x6050 + z6051 = x6051 + z6052 = x6052 + z6053 = x6053 + z6054 = x6054 + z6055 = x6055 + z6056 = x6056 + z6057 = x6057 + z6058 = x6058 + z6059 = x6059 + z6060 = x6060 + z6061 = x6061 + z6062 = x6062 + z6063 = x6063 + z6064 = x6064 + z6065 = x6065 + z6066 = x6066 + z6067 = x6067 + z6068 = x6068 + z6069 = x6069 + z6070 = x6070 + z6071 = x6071 + z6072 = x6072 + z6073 = x6073 + z6074 = x6074 + z6075 = x6075 + z6076 = x6076 + z6077 = x6077 + z6078 = x6078 + z6079 = x6079 + z6080 = x6080 + z6081 = x6081 + z6082 = x6082 + z6083 = x6083 + z6084 = x6084 + z6085 = x6085 + z6086 = x6086 + z6087 = x6087 + z6088 = x6088 + z6089 = x6089 + z6090 = x6090 + z6091 = x6091 + z6092 = x6092 + z6093 = x6093 + z6094 = x6094 + z6095 = x6095 + z6096 = x6096 + z6097 = x6097 + z6098 = x6098 + z6099 = x6099 + z6100 = x6100 + z6101 = x6101 + z6102 = x6102 + z6103 = x6103 + z6104 = x6104 + z6105 = x6105 + z6106 = x6106 + z6107 = x6107 + z6108 = x6108 + z6109 = x6109 + z6110 = x6110 + z6111 = x6111 + z6112 = x6112 + z6113 = x6113 + z6114 = x6114 + z6115 = x6115 + z6116 = x6116 + z6117 = x6117 + z6118 = x6118 + z6119 = x6119 + z6120 = x6120 + z6121 = x6121 + z6122 = x6122 + z6123 = x6123 + z6124 = x6124 + z6125 = x6125 + z6126 = x6126 + z6127 = x6127 + z6128 = x6128 + z6129 = x6129 + z6130 = x6130 + z6131 = x6131 + z6132 = x6132 + z6133 = x6133 + z6134 = x6134 + z6135 = x6135 + z6136 = x6136 + z6137 = x6137 + z6138 = x6138 + z6139 = x6139 + z6140 = x6140 + z6141 = x6141 + z6142 = x6142 + z6143 = x6143 + z6144 = x6144 + z6145 = x6145 + z6146 = x6146 + z6147 = x6147 + z6148 = x6148 + z6149 = x6149 + z6150 = x6150 + z6151 = x6151 + z6152 = x6152 + z6153 = x6153 + z6154 = x6154 + z6155 = x6155 + z6156 = x6156 + z6157 = x6157 + z6158 = x6158 + z6159 = x6159 + z6160 = x6160 + z6161 = x6161 + z6162 = x6162 + z6163 = x6163 + z6164 = x6164 + z6165 = x6165 + z6166 = x6166 + z6167 = x6167 + z6168 = x6168 + z6169 = x6169 + z6170 = x6170 + z6171 = x6171 + z6172 = x6172 + z6173 = x6173 + z6174 = x6174 + z6175 = x6175 + z6176 = x6176 + z6177 = x6177 + z6178 = x6178 + z6179 = x6179 + z6180 = x6180 + z6181 = x6181 + z6182 = x6182 + z6183 = x6183 + z6184 = x6184 + z6185 = x6185 + z6186 = x6186 + z6187 = x6187 + z6188 = x6188 + z6189 = x6189 + z6190 = x6190 + z6191 = x6191 + z6192 = x6192 + z6193 = x6193 + z6194 = x6194 + z6195 = x6195 + z6196 = x6196 + z6197 = x6197 + z6198 = x6198 + z6199 = x6199 + z6200 = x6200 + z6201 = x6201 + z6202 = x6202 + z6203 = x6203 + z6204 = x6204 + z6205 = x6205 + z6206 = x6206 + z6207 = x6207 + z6208 = x6208 + z6209 = x6209 + z6210 = x6210 + z6211 = x6211 + z6212 = x6212 + z6213 = x6213 + z6214 = x6214 + z6215 = x6215 + z6216 = x6216 + z6217 = x6217 + z6218 = x6218 + z6219 = x6219 + z6220 = x6220 + z6221 = x6221 + z6222 = x6222 + z6223 = x6223 + z6224 = x6224 + z6225 = x6225 + z6226 = x6226 + z6227 = x6227 + z6228 = x6228 + z6229 = x6229 + z6230 = x6230 + z6231 = x6231 + z6232 = x6232 + z6233 = x6233 + z6234 = x6234 + z6235 = x6235 + z6236 = x6236 + z6237 = x6237 + z6238 = x6238 + z6239 = x6239 + z6240 = x6240 + z6241 = x6241 + z6242 = x6242 + z6243 = x6243 + z6244 = x6244 + z6245 = x6245 + z6246 = x6246 + z6247 = x6247 + z6248 = x6248 + z6249 = x6249 + z6250 = x6250 + z6251 = x6251 + z6252 = x6252 + z6253 = x6253 + z6254 = x6254 + z6255 = x6255 + z6256 = x6256 + z6257 = x6257 + z6258 = x6258 + z6259 = x6259 + z6260 = x6260 + z6261 = x6261 + z6262 = x6262 + z6263 = x6263 + z6264 = x6264 + z6265 = x6265 + z6266 = x6266 + z6267 = x6267 + z6268 = x6268 + z6269 = x6269 + z6270 = x6270 + z6271 = x6271 + z6272 = x6272 + z6273 = x6273 + z6274 = x6274 + z6275 = x6275 + z6276 = x6276 + z6277 = x6277 + z6278 = x6278 + z6279 = x6279 + z6280 = x6280 + z6281 = x6281 + z6282 = x6282 + z6283 = x6283 + z6284 = x6284 + z6285 = x6285 + z6286 = x6286 + z6287 = x6287 + z6288 = x6288 + z6289 = x6289 + z6290 = x6290 + z6291 = x6291 + z6292 = x6292 + z6293 = x6293 + z6294 = x6294 + z6295 = x6295 + z6296 = x6296 + z6297 = x6297 + z6298 = x6298 + z6299 = x6299 + z6300 = x6300 + z6301 = x6301 + z6302 = x6302 + z6303 = x6303 + z6304 = x6304 + z6305 = x6305 + z6306 = x6306 + z6307 = x6307 + z6308 = x6308 + z6309 = x6309 + z6310 = x6310 + z6311 = x6311 + z6312 = x6312 + z6313 = x6313 + z6314 = x6314 + z6315 = x6315 + z6316 = x6316 + z6317 = x6317 + z6318 = x6318 + z6319 = x6319 + z6320 = x6320 + z6321 = x6321 + z6322 = x6322 + z6323 = x6323 + z6324 = x6324 + z6325 = x6325 + z6326 = x6326 + z6327 = x6327 + z6328 = x6328 + z6329 = x6329 + z6330 = x6330 + z6331 = x6331 + z6332 = x6332 + z6333 = x6333 + z6334 = x6334 + z6335 = x6335 + z6336 = x6336 + z6337 = x6337 + z6338 = x6338 + z6339 = x6339 + z6340 = x6340 + z6341 = x6341 + z6342 = x6342 + z6343 = x6343 + z6344 = x6344 + z6345 = x6345 + z6346 = x6346 + z6347 = x6347 + z6348 = x6348 + z6349 = x6349 + z6350 = x6350 + z6351 = x6351 + z6352 = x6352 + z6353 = x6353 + z6354 = x6354 + z6355 = x6355 + z6356 = x6356 + z6357 = x6357 + z6358 = x6358 + z6359 = x6359 + z6360 = x6360 + z6361 = x6361 + z6362 = x6362 + z6363 = x6363 + z6364 = x6364 + z6365 = x6365 + z6366 = x6366 + z6367 = x6367 + z6368 = x6368 + z6369 = x6369 + z6370 = x6370 + z6371 = x6371 + z6372 = x6372 + z6373 = x6373 + z6374 = x6374 + z6375 = x6375 + z6376 = x6376 + z6377 = x6377 + z6378 = x6378 + z6379 = x6379 + z6380 = x6380 + z6381 = x6381 + z6382 = x6382 + z6383 = x6383 + z6384 = x6384 + z6385 = x6385 + z6386 = x6386 + z6387 = x6387 + z6388 = x6388 + z6389 = x6389 + z6390 = x6390 + z6391 = x6391 + z6392 = x6392 + z6393 = x6393 + z6394 = x6394 + z6395 = x6395 + z6396 = x6396 + z6397 = x6397 + z6398 = x6398 + z6399 = x6399 + z6400 = x6400 + z6401 = x6401 + z6402 = x6402 + z6403 = x6403 + z6404 = x6404 + z6405 = x6405 + z6406 = x6406 + z6407 = x6407 + z6408 = x6408 + z6409 = x6409 + z6410 = x6410 + z6411 = x6411 + z6412 = x6412 + z6413 = x6413 + z6414 = x6414 + z6415 = x6415 + z6416 = x6416 + z6417 = x6417 + z6418 = x6418 + z6419 = x6419 + z6420 = x6420 + z6421 = x6421 + z6422 = x6422 + z6423 = x6423 + z6424 = x6424 + z6425 = x6425 + z6426 = x6426 + z6427 = x6427 + z6428 = x6428 + z6429 = x6429 + z6430 = x6430 + z6431 = x6431 + z6432 = x6432 + z6433 = x6433 + z6434 = x6434 + z6435 = x6435 + z6436 = x6436 + z6437 = x6437 + z6438 = x6438 + z6439 = x6439 + z6440 = x6440 + z6441 = x6441 + z6442 = x6442 + z6443 = x6443 + z6444 = x6444 + z6445 = x6445 + z6446 = x6446 + z6447 = x6447 + z6448 = x6448 + z6449 = x6449 + z6450 = x6450 + z6451 = x6451 + z6452 = x6452 + z6453 = x6453 + z6454 = x6454 + z6455 = x6455 + z6456 = x6456 + z6457 = x6457 + z6458 = x6458 + z6459 = x6459 + z6460 = x6460 + z6461 = x6461 + z6462 = x6462 + z6463 = x6463 + z6464 = x6464 + z6465 = x6465 + z6466 = x6466 + z6467 = x6467 + z6468 = x6468 + z6469 = x6469 + z6470 = x6470 + z6471 = x6471 + z6472 = x6472 + z6473 = x6473 + z6474 = x6474 + z6475 = x6475 + z6476 = x6476 + z6477 = x6477 + z6478 = x6478 + z6479 = x6479 + z6480 = x6480 + z6481 = x6481 + z6482 = x6482 + z6483 = x6483 + z6484 = x6484 + z6485 = x6485 + z6486 = x6486 + z6487 = x6487 + z6488 = x6488 + z6489 = x6489 + z6490 = x6490 + z6491 = x6491 + z6492 = x6492 + z6493 = x6493 + z6494 = x6494 + z6495 = x6495 + z6496 = x6496 + z6497 = x6497 + z6498 = x6498 + z6499 = x6499 + z6500 = x6500 + z6501 = x6501 + z6502 = x6502 + z6503 = x6503 + z6504 = x6504 + z6505 = x6505 + z6506 = x6506 + z6507 = x6507 + z6508 = x6508 + z6509 = x6509 + z6510 = x6510 + z6511 = x6511 + z6512 = x6512 + z6513 = x6513 + z6514 = x6514 + z6515 = x6515 + z6516 = x6516 + z6517 = x6517 + z6518 = x6518 + z6519 = x6519 + z6520 = x6520 + z6521 = x6521 + z6522 = x6522 + z6523 = x6523 + z6524 = x6524 + z6525 = x6525 + z6526 = x6526 + z6527 = x6527 + z6528 = x6528 + z6529 = x6529 + z6530 = x6530 + z6531 = x6531 + z6532 = x6532 + z6533 = x6533 + z6534 = x6534 + z6535 = x6535 + z6536 = x6536 + z6537 = x6537 + z6538 = x6538 + z6539 = x6539 + z6540 = x6540 + z6541 = x6541 + z6542 = x6542 + z6543 = x6543 + z6544 = x6544 + z6545 = x6545 + z6546 = x6546 + z6547 = x6547 + z6548 = x6548 + z6549 = x6549 + z6550 = x6550 + z6551 = x6551 + z6552 = x6552 + z6553 = x6553 + z6554 = x6554 + z6555 = x6555 + z6556 = x6556 + z6557 = x6557 + z6558 = x6558 + z6559 = x6559 + z6560 = x6560 + z6561 = x6561 + z6562 = x6562 + z6563 = x6563 + z6564 = x6564 + z6565 = x6565 + z6566 = x6566 + z6567 = x6567 + z6568 = x6568 + z6569 = x6569 + z6570 = x6570 + z6571 = x6571 + z6572 = x6572 + z6573 = x6573 + z6574 = x6574 + z6575 = x6575 + z6576 = x6576 + z6577 = x6577 + z6578 = x6578 + z6579 = x6579 + z6580 = x6580 + z6581 = x6581 + z6582 = x6582 + z6583 = x6583 + z6584 = x6584 + z6585 = x6585 + z6586 = x6586 + z6587 = x6587 + z6588 = x6588 + z6589 = x6589 + z6590 = x6590 + z6591 = x6591 + z6592 = x6592 + z6593 = x6593 + z6594 = x6594 + z6595 = x6595 + z6596 = x6596 + z6597 = x6597 + z6598 = x6598 + z6599 = x6599 + z6600 = x6600 + z6601 = x6601 + z6602 = x6602 + z6603 = x6603 + z6604 = x6604 + z6605 = x6605 + z6606 = x6606 + z6607 = x6607 + z6608 = x6608 + z6609 = x6609 + z6610 = x6610 + z6611 = x6611 + z6612 = x6612 + z6613 = x6613 + z6614 = x6614 + z6615 = x6615 + z6616 = x6616 + z6617 = x6617 + z6618 = x6618 + z6619 = x6619 + z6620 = x6620 + z6621 = x6621 + z6622 = x6622 + z6623 = x6623 + z6624 = x6624 + z6625 = x6625 + z6626 = x6626 + z6627 = x6627 + z6628 = x6628 + z6629 = x6629 + z6630 = x6630 + z6631 = x6631 + z6632 = x6632 + z6633 = x6633 + z6634 = x6634 + z6635 = x6635 + z6636 = x6636 + z6637 = x6637 + z6638 = x6638 + z6639 = x6639 + z6640 = x6640 + z6641 = x6641 + z6642 = x6642 + z6643 = x6643 + z6644 = x6644 + z6645 = x6645 + z6646 = x6646 + z6647 = x6647 + z6648 = x6648 + z6649 = x6649 + z6650 = x6650 + z6651 = x6651 + z6652 = x6652 + z6653 = x6653 + z6654 = x6654 + z6655 = x6655 + z6656 = x6656 + z6657 = x6657 + z6658 = x6658 + z6659 = x6659 + z6660 = x6660 + z6661 = x6661 + z6662 = x6662 + z6663 = x6663 + z6664 = x6664 + z6665 = x6665 + z6666 = x6666 + z6667 = x6667 + z6668 = x6668 + z6669 = x6669 + z6670 = x6670 + z6671 = x6671 + z6672 = x6672 + z6673 = x6673 + z6674 = x6674 + z6675 = x6675 + z6676 = x6676 + z6677 = x6677 + z6678 = x6678 + z6679 = x6679 + z6680 = x6680 + z6681 = x6681 + z6682 = x6682 + z6683 = x6683 + z6684 = x6684 + z6685 = x6685 + z6686 = x6686 + z6687 = x6687 + z6688 = x6688 + z6689 = x6689 + z6690 = x6690 + z6691 = x6691 + z6692 = x6692 + z6693 = x6693 + z6694 = x6694 + z6695 = x6695 + z6696 = x6696 + z6697 = x6697 + z6698 = x6698 + z6699 = x6699 + z6700 = x6700 + z6701 = x6701 + z6702 = x6702 + z6703 = x6703 + z6704 = x6704 + z6705 = x6705 + z6706 = x6706 + z6707 = x6707 + z6708 = x6708 + z6709 = x6709 + z6710 = x6710 + z6711 = x6711 + z6712 = x6712 + z6713 = x6713 + z6714 = x6714 + z6715 = x6715 + z6716 = x6716 + z6717 = x6717 + z6718 = x6718 + z6719 = x6719 + z6720 = x6720 + z6721 = x6721 + z6722 = x6722 + z6723 = x6723 + z6724 = x6724 + z6725 = x6725 + z6726 = x6726 + z6727 = x6727 + z6728 = x6728 + z6729 = x6729 + z6730 = x6730 + z6731 = x6731 + z6732 = x6732 + z6733 = x6733 + z6734 = x6734 + z6735 = x6735 + z6736 = x6736 + z6737 = x6737 + z6738 = x6738 + z6739 = x6739 + z6740 = x6740 + z6741 = x6741 + z6742 = x6742 + z6743 = x6743 + z6744 = x6744 + z6745 = x6745 + z6746 = x6746 + z6747 = x6747 + z6748 = x6748 + z6749 = x6749 + z6750 = x6750 + z6751 = x6751 + z6752 = x6752 + z6753 = x6753 + z6754 = x6754 + z6755 = x6755 + z6756 = x6756 + z6757 = x6757 + z6758 = x6758 + z6759 = x6759 + z6760 = x6760 + z6761 = x6761 + z6762 = x6762 + z6763 = x6763 + z6764 = x6764 + z6765 = x6765 + z6766 = x6766 + z6767 = x6767 + z6768 = x6768 + z6769 = x6769 + z6770 = x6770 + z6771 = x6771 + z6772 = x6772 + z6773 = x6773 + z6774 = x6774 + z6775 = x6775 + z6776 = x6776 + z6777 = x6777 + z6778 = x6778 + z6779 = x6779 + z6780 = x6780 + z6781 = x6781 + z6782 = x6782 + z6783 = x6783 + z6784 = x6784 + z6785 = x6785 + z6786 = x6786 + z6787 = x6787 + z6788 = x6788 + z6789 = x6789 + z6790 = x6790 + z6791 = x6791 + z6792 = x6792 + z6793 = x6793 + z6794 = x6794 + z6795 = x6795 + z6796 = x6796 + z6797 = x6797 + z6798 = x6798 + z6799 = x6799 + z6800 = x6800 + z6801 = x6801 + z6802 = x6802 + z6803 = x6803 + z6804 = x6804 + z6805 = x6805 + z6806 = x6806 + z6807 = x6807 + z6808 = x6808 + z6809 = x6809 + z6810 = x6810 + z6811 = x6811 + z6812 = x6812 + z6813 = x6813 + z6814 = x6814 + z6815 = x6815 + z6816 = x6816 + z6817 = x6817 + z6818 = x6818 + z6819 = x6819 + z6820 = x6820 + z6821 = x6821 + z6822 = x6822 + z6823 = x6823 + z6824 = x6824 + z6825 = x6825 + z6826 = x6826 + z6827 = x6827 + z6828 = x6828 + z6829 = x6829 + z6830 = x6830 + z6831 = x6831 + z6832 = x6832 + z6833 = x6833 + z6834 = x6834 + z6835 = x6835 + z6836 = x6836 + z6837 = x6837 + z6838 = x6838 + z6839 = x6839 + z6840 = x6840 + z6841 = x6841 + z6842 = x6842 + z6843 = x6843 + z6844 = x6844 + z6845 = x6845 + z6846 = x6846 + z6847 = x6847 + z6848 = x6848 + z6849 = x6849 + z6850 = x6850 + z6851 = x6851 + z6852 = x6852 + z6853 = x6853 + z6854 = x6854 + z6855 = x6855 + z6856 = x6856 + z6857 = x6857 + z6858 = x6858 + z6859 = x6859 + z6860 = x6860 + z6861 = x6861 + z6862 = x6862 + z6863 = x6863 + z6864 = x6864 + z6865 = x6865 + z6866 = x6866 + z6867 = x6867 + z6868 = x6868 + z6869 = x6869 + z6870 = x6870 + z6871 = x6871 + z6872 = x6872 + z6873 = x6873 + z6874 = x6874 + z6875 = x6875 + z6876 = x6876 + z6877 = x6877 + z6878 = x6878 + z6879 = x6879 + z6880 = x6880 + z6881 = x6881 + z6882 = x6882 + z6883 = x6883 + z6884 = x6884 + z6885 = x6885 + z6886 = x6886 + z6887 = x6887 + z6888 = x6888 + z6889 = x6889 + z6890 = x6890 + z6891 = x6891 + z6892 = x6892 + z6893 = x6893 + z6894 = x6894 + z6895 = x6895 + z6896 = x6896 + z6897 = x6897 + z6898 = x6898 + z6899 = x6899 + z6900 = x6900 + z6901 = x6901 + z6902 = x6902 + z6903 = x6903 + z6904 = x6904 + z6905 = x6905 + z6906 = x6906 + z6907 = x6907 + z6908 = x6908 + z6909 = x6909 + z6910 = x6910 + z6911 = x6911 + z6912 = x6912 + z6913 = x6913 + z6914 = x6914 + z6915 = x6915 + z6916 = x6916 + z6917 = x6917 + z6918 = x6918 + z6919 = x6919 + z6920 = x6920 + z6921 = x6921 + z6922 = x6922 + z6923 = x6923 + z6924 = x6924 + z6925 = x6925 + z6926 = x6926 + z6927 = x6927 + z6928 = x6928 + z6929 = x6929 + z6930 = x6930 + z6931 = x6931 + z6932 = x6932 + z6933 = x6933 + z6934 = x6934 + z6935 = x6935 + z6936 = x6936 + z6937 = x6937 + z6938 = x6938 + z6939 = x6939 + z6940 = x6940 + z6941 = x6941 + z6942 = x6942 + z6943 = x6943 + z6944 = x6944 + z6945 = x6945 + z6946 = x6946 + z6947 = x6947 + z6948 = x6948 + z6949 = x6949 + z6950 = x6950 + z6951 = x6951 + z6952 = x6952 + z6953 = x6953 + z6954 = x6954 + z6955 = x6955 + z6956 = x6956 + z6957 = x6957 + z6958 = x6958 + z6959 = x6959 + z6960 = x6960 + z6961 = x6961 + z6962 = x6962 + z6963 = x6963 + z6964 = x6964 + z6965 = x6965 + z6966 = x6966 + z6967 = x6967 + z6968 = x6968 + z6969 = x6969 + z6970 = x6970 + z6971 = x6971 + z6972 = x6972 + z6973 = x6973 + z6974 = x6974 + z6975 = x6975 + z6976 = x6976 + z6977 = x6977 + z6978 = x6978 + z6979 = x6979 + z6980 = x6980 + z6981 = x6981 + z6982 = x6982 + z6983 = x6983 + z6984 = x6984 + z6985 = x6985 + z6986 = x6986 + z6987 = x6987 + z6988 = x6988 + z6989 = x6989 + z6990 = x6990 + z6991 = x6991 + z6992 = x6992 + z6993 = x6993 + z6994 = x6994 + z6995 = x6995 + z6996 = x6996 + z6997 = x6997 + z6998 = x6998 + z6999 = x6999 + z7000 = x7000 + z7001 = x7001 + z7002 = x7002 + z7003 = x7003 + z7004 = x7004 + z7005 = x7005 + z7006 = x7006 + z7007 = x7007 + z7008 = x7008 + z7009 = x7009 + z7010 = x7010 + z7011 = x7011 + z7012 = x7012 + z7013 = x7013 + z7014 = x7014 + z7015 = x7015 + z7016 = x7016 + z7017 = x7017 + z7018 = x7018 + z7019 = x7019 + z7020 = x7020 + z7021 = x7021 + z7022 = x7022 + z7023 = x7023 + z7024 = x7024 + z7025 = x7025 + z7026 = x7026 + z7027 = x7027 + z7028 = x7028 + z7029 = x7029 + z7030 = x7030 + z7031 = x7031 + z7032 = x7032 + z7033 = x7033 + z7034 = x7034 + z7035 = x7035 + z7036 = x7036 + z7037 = x7037 + z7038 = x7038 + z7039 = x7039 + z7040 = x7040 + z7041 = x7041 + z7042 = x7042 + z7043 = x7043 + z7044 = x7044 + z7045 = x7045 + z7046 = x7046 + z7047 = x7047 + z7048 = x7048 + z7049 = x7049 + z7050 = x7050 + z7051 = x7051 + z7052 = x7052 + z7053 = x7053 + z7054 = x7054 + z7055 = x7055 + z7056 = x7056 + z7057 = x7057 + z7058 = x7058 + z7059 = x7059 + z7060 = x7060 + z7061 = x7061 + z7062 = x7062 + z7063 = x7063 + z7064 = x7064 + z7065 = x7065 + z7066 = x7066 + z7067 = x7067 + z7068 = x7068 + z7069 = x7069 + z7070 = x7070 + z7071 = x7071 + z7072 = x7072 + z7073 = x7073 + z7074 = x7074 + z7075 = x7075 + z7076 = x7076 + z7077 = x7077 + z7078 = x7078 + z7079 = x7079 + z7080 = x7080 + z7081 = x7081 + z7082 = x7082 + z7083 = x7083 + z7084 = x7084 + z7085 = x7085 + z7086 = x7086 + z7087 = x7087 + z7088 = x7088 + z7089 = x7089 + z7090 = x7090 + z7091 = x7091 + z7092 = x7092 + z7093 = x7093 + z7094 = x7094 + z7095 = x7095 + z7096 = x7096 + z7097 = x7097 + z7098 = x7098 + z7099 = x7099 + z7100 = x7100 + z7101 = x7101 + z7102 = x7102 + z7103 = x7103 + z7104 = x7104 + z7105 = x7105 + z7106 = x7106 + z7107 = x7107 + z7108 = x7108 + z7109 = x7109 + z7110 = x7110 + z7111 = x7111 + z7112 = x7112 + z7113 = x7113 + z7114 = x7114 + z7115 = x7115 + z7116 = x7116 + z7117 = x7117 + z7118 = x7118 + z7119 = x7119 + z7120 = x7120 + z7121 = x7121 + z7122 = x7122 + z7123 = x7123 + z7124 = x7124 + z7125 = x7125 + z7126 = x7126 + z7127 = x7127 + z7128 = x7128 + z7129 = x7129 + z7130 = x7130 + z7131 = x7131 + z7132 = x7132 + z7133 = x7133 + z7134 = x7134 + z7135 = x7135 + z7136 = x7136 + z7137 = x7137 + z7138 = x7138 + z7139 = x7139 + z7140 = x7140 + z7141 = x7141 + z7142 = x7142 + z7143 = x7143 + z7144 = x7144 + z7145 = x7145 + z7146 = x7146 + z7147 = x7147 + z7148 = x7148 + z7149 = x7149 + z7150 = x7150 + z7151 = x7151 + z7152 = x7152 + z7153 = x7153 + z7154 = x7154 + z7155 = x7155 + z7156 = x7156 + z7157 = x7157 + z7158 = x7158 + z7159 = x7159 + z7160 = x7160 + z7161 = x7161 + z7162 = x7162 + z7163 = x7163 + z7164 = x7164 + z7165 = x7165 + z7166 = x7166 + z7167 = x7167 + z7168 = x7168 + z7169 = x7169 + z7170 = x7170 + z7171 = x7171 + z7172 = x7172 + z7173 = x7173 + z7174 = x7174 + z7175 = x7175 + z7176 = x7176 + z7177 = x7177 + z7178 = x7178 + z7179 = x7179 + z7180 = x7180 + z7181 = x7181 + z7182 = x7182 + z7183 = x7183 + z7184 = x7184 + z7185 = x7185 + z7186 = x7186 + z7187 = x7187 + z7188 = x7188 + z7189 = x7189 + z7190 = x7190 + z7191 = x7191 + z7192 = x7192 + z7193 = x7193 + z7194 = x7194 + z7195 = x7195 + z7196 = x7196 + z7197 = x7197 + z7198 = x7198 + z7199 = x7199 + z7200 = x7200 + z7201 = x7201 + z7202 = x7202 + z7203 = x7203 + z7204 = x7204 + z7205 = x7205 + z7206 = x7206 + z7207 = x7207 + z7208 = x7208 + z7209 = x7209 + z7210 = x7210 + z7211 = x7211 + z7212 = x7212 + z7213 = x7213 + z7214 = x7214 + z7215 = x7215 + z7216 = x7216 + z7217 = x7217 + z7218 = x7218 + z7219 = x7219 + z7220 = x7220 + z7221 = x7221 + z7222 = x7222 + z7223 = x7223 + z7224 = x7224 + z7225 = x7225 + z7226 = x7226 + z7227 = x7227 + z7228 = x7228 + z7229 = x7229 + z7230 = x7230 + z7231 = x7231 + z7232 = x7232 + z7233 = x7233 + z7234 = x7234 + z7235 = x7235 + z7236 = x7236 + z7237 = x7237 + z7238 = x7238 + z7239 = x7239 + z7240 = x7240 + z7241 = x7241 + z7242 = x7242 + z7243 = x7243 + z7244 = x7244 + z7245 = x7245 + z7246 = x7246 + z7247 = x7247 + z7248 = x7248 + z7249 = x7249 + z7250 = x7250 + z7251 = x7251 + z7252 = x7252 + z7253 = x7253 + z7254 = x7254 + z7255 = x7255 + z7256 = x7256 + z7257 = x7257 + z7258 = x7258 + z7259 = x7259 + z7260 = x7260 + z7261 = x7261 + z7262 = x7262 + z7263 = x7263 + z7264 = x7264 + z7265 = x7265 + z7266 = x7266 + z7267 = x7267 + z7268 = x7268 + z7269 = x7269 + z7270 = x7270 + z7271 = x7271 + z7272 = x7272 + z7273 = x7273 + z7274 = x7274 + z7275 = x7275 + z7276 = x7276 + z7277 = x7277 + z7278 = x7278 + z7279 = x7279 + z7280 = x7280 + z7281 = x7281 + z7282 = x7282 + z7283 = x7283 + z7284 = x7284 + z7285 = x7285 + z7286 = x7286 + z7287 = x7287 + z7288 = x7288 + z7289 = x7289 + z7290 = x7290 + z7291 = x7291 + z7292 = x7292 + z7293 = x7293 + z7294 = x7294 + z7295 = x7295 + z7296 = x7296 + z7297 = x7297 + z7298 = x7298 + z7299 = x7299 + z7300 = x7300 + z7301 = x7301 + z7302 = x7302 + z7303 = x7303 + z7304 = x7304 + z7305 = x7305 + z7306 = x7306 + z7307 = x7307 + z7308 = x7308 + z7309 = x7309 + z7310 = x7310 + z7311 = x7311 + z7312 = x7312 + z7313 = x7313 + z7314 = x7314 + z7315 = x7315 + z7316 = x7316 + z7317 = x7317 + z7318 = x7318 + z7319 = x7319 + z7320 = x7320 + z7321 = x7321 + z7322 = x7322 + z7323 = x7323 + z7324 = x7324 + z7325 = x7325 + z7326 = x7326 + z7327 = x7327 + z7328 = x7328 + z7329 = x7329 + z7330 = x7330 + z7331 = x7331 + z7332 = x7332 + z7333 = x7333 + z7334 = x7334 + z7335 = x7335 + z7336 = x7336 + z7337 = x7337 + z7338 = x7338 + z7339 = x7339 + z7340 = x7340 + z7341 = x7341 + z7342 = x7342 + z7343 = x7343 + z7344 = x7344 + z7345 = x7345 + z7346 = x7346 + z7347 = x7347 + z7348 = x7348 + z7349 = x7349 + z7350 = x7350 + z7351 = x7351 + z7352 = x7352 + z7353 = x7353 + z7354 = x7354 + z7355 = x7355 + z7356 = x7356 + z7357 = x7357 + z7358 = x7358 + z7359 = x7359 + z7360 = x7360 + z7361 = x7361 + z7362 = x7362 + z7363 = x7363 + z7364 = x7364 + z7365 = x7365 + z7366 = x7366 + z7367 = x7367 + z7368 = x7368 + z7369 = x7369 + z7370 = x7370 + z7371 = x7371 + z7372 = x7372 + z7373 = x7373 + z7374 = x7374 + z7375 = x7375 + z7376 = x7376 + z7377 = x7377 + z7378 = x7378 + z7379 = x7379 + z7380 = x7380 + z7381 = x7381 + z7382 = x7382 + z7383 = x7383 + z7384 = x7384 + z7385 = x7385 + z7386 = x7386 + z7387 = x7387 + z7388 = x7388 + z7389 = x7389 + z7390 = x7390 + z7391 = x7391 + z7392 = x7392 + z7393 = x7393 + z7394 = x7394 + z7395 = x7395 + z7396 = x7396 + z7397 = x7397 + z7398 = x7398 + z7399 = x7399 + z7400 = x7400 + z7401 = x7401 + z7402 = x7402 + z7403 = x7403 + z7404 = x7404 + z7405 = x7405 + z7406 = x7406 + z7407 = x7407 + z7408 = x7408 + z7409 = x7409 + z7410 = x7410 + z7411 = x7411 + z7412 = x7412 + z7413 = x7413 + z7414 = x7414 + z7415 = x7415 + z7416 = x7416 + z7417 = x7417 + z7418 = x7418 + z7419 = x7419 + z7420 = x7420 + z7421 = x7421 + z7422 = x7422 + z7423 = x7423 + z7424 = x7424 + z7425 = x7425 + z7426 = x7426 + z7427 = x7427 + z7428 = x7428 + z7429 = x7429 + z7430 = x7430 + z7431 = x7431 + z7432 = x7432 + z7433 = x7433 + z7434 = x7434 + z7435 = x7435 + z7436 = x7436 + z7437 = x7437 + z7438 = x7438 + z7439 = x7439 + z7440 = x7440 + z7441 = x7441 + z7442 = x7442 + z7443 = x7443 + z7444 = x7444 + z7445 = x7445 + z7446 = x7446 + z7447 = x7447 + z7448 = x7448 + z7449 = x7449 + z7450 = x7450 + z7451 = x7451 + z7452 = x7452 + z7453 = x7453 + z7454 = x7454 + z7455 = x7455 + z7456 = x7456 + z7457 = x7457 + z7458 = x7458 + z7459 = x7459 + z7460 = x7460 + z7461 = x7461 + z7462 = x7462 + z7463 = x7463 + z7464 = x7464 + z7465 = x7465 + z7466 = x7466 + z7467 = x7467 + z7468 = x7468 + z7469 = x7469 + z7470 = x7470 + z7471 = x7471 + z7472 = x7472 + z7473 = x7473 + z7474 = x7474 + z7475 = x7475 + z7476 = x7476 + z7477 = x7477 + z7478 = x7478 + z7479 = x7479 + z7480 = x7480 + z7481 = x7481 + z7482 = x7482 + z7483 = x7483 + z7484 = x7484 + z7485 = x7485 + z7486 = x7486 + z7487 = x7487 + z7488 = x7488 + z7489 = x7489 + z7490 = x7490 + z7491 = x7491 + z7492 = x7492 + z7493 = x7493 + z7494 = x7494 + z7495 = x7495 + z7496 = x7496 + z7497 = x7497 + z7498 = x7498 + z7499 = x7499 + z7500 = x7500 + z7501 = x7501 + z7502 = x7502 + z7503 = x7503 + z7504 = x7504 + z7505 = x7505 + z7506 = x7506 + z7507 = x7507 + z7508 = x7508 + z7509 = x7509 + z7510 = x7510 + z7511 = x7511 + z7512 = x7512 + z7513 = x7513 + z7514 = x7514 + z7515 = x7515 + z7516 = x7516 + z7517 = x7517 + z7518 = x7518 + z7519 = x7519 + z7520 = x7520 + z7521 = x7521 + z7522 = x7522 + z7523 = x7523 + z7524 = x7524 + z7525 = x7525 + z7526 = x7526 + z7527 = x7527 + z7528 = x7528 + z7529 = x7529 + z7530 = x7530 + z7531 = x7531 + z7532 = x7532 + z7533 = x7533 + z7534 = x7534 + z7535 = x7535 + z7536 = x7536 + z7537 = x7537 + z7538 = x7538 + z7539 = x7539 + z7540 = x7540 + z7541 = x7541 + z7542 = x7542 + z7543 = x7543 + z7544 = x7544 + z7545 = x7545 + z7546 = x7546 + z7547 = x7547 + z7548 = x7548 + z7549 = x7549 + z7550 = x7550 + z7551 = x7551 + z7552 = x7552 + z7553 = x7553 + z7554 = x7554 + z7555 = x7555 + z7556 = x7556 + z7557 = x7557 + z7558 = x7558 + z7559 = x7559 + z7560 = x7560 + z7561 = x7561 + z7562 = x7562 + z7563 = x7563 + z7564 = x7564 + z7565 = x7565 + z7566 = x7566 + z7567 = x7567 + z7568 = x7568 + z7569 = x7569 + z7570 = x7570 + z7571 = x7571 + z7572 = x7572 + z7573 = x7573 + z7574 = x7574 + z7575 = x7575 + z7576 = x7576 + z7577 = x7577 + z7578 = x7578 + z7579 = x7579 + z7580 = x7580 + z7581 = x7581 + z7582 = x7582 + z7583 = x7583 + z7584 = x7584 + z7585 = x7585 + z7586 = x7586 + z7587 = x7587 + z7588 = x7588 + z7589 = x7589 + z7590 = x7590 + z7591 = x7591 + z7592 = x7592 + z7593 = x7593 + z7594 = x7594 + z7595 = x7595 + z7596 = x7596 + z7597 = x7597 + z7598 = x7598 + z7599 = x7599 + z7600 = x7600 + z7601 = x7601 + z7602 = x7602 + z7603 = x7603 + z7604 = x7604 + z7605 = x7605 + z7606 = x7606 + z7607 = x7607 + z7608 = x7608 + z7609 = x7609 + z7610 = x7610 + z7611 = x7611 + z7612 = x7612 + z7613 = x7613 + z7614 = x7614 + z7615 = x7615 + z7616 = x7616 + z7617 = x7617 + z7618 = x7618 + z7619 = x7619 + z7620 = x7620 + z7621 = x7621 + z7622 = x7622 + z7623 = x7623 + z7624 = x7624 + z7625 = x7625 + z7626 = x7626 + z7627 = x7627 + z7628 = x7628 + z7629 = x7629 + z7630 = x7630 + z7631 = x7631 + z7632 = x7632 + z7633 = x7633 + z7634 = x7634 + z7635 = x7635 + z7636 = x7636 + z7637 = x7637 + z7638 = x7638 + z7639 = x7639 + z7640 = x7640 + z7641 = x7641 + z7642 = x7642 + z7643 = x7643 + z7644 = x7644 + z7645 = x7645 + z7646 = x7646 + z7647 = x7647 + z7648 = x7648 + z7649 = x7649 + z7650 = x7650 + z7651 = x7651 + z7652 = x7652 + z7653 = x7653 + z7654 = x7654 + z7655 = x7655 + z7656 = x7656 + z7657 = x7657 + z7658 = x7658 + z7659 = x7659 + z7660 = x7660 + z7661 = x7661 + z7662 = x7662 + z7663 = x7663 + z7664 = x7664 + z7665 = x7665 + z7666 = x7666 + z7667 = x7667 + z7668 = x7668 + z7669 = x7669 + z7670 = x7670 + z7671 = x7671 + z7672 = x7672 + z7673 = x7673 + z7674 = x7674 + z7675 = x7675 + z7676 = x7676 + z7677 = x7677 + z7678 = x7678 + z7679 = x7679 + z7680 = x7680 + z7681 = x7681 + z7682 = x7682 + z7683 = x7683 + z7684 = x7684 + z7685 = x7685 + z7686 = x7686 + z7687 = x7687 + z7688 = x7688 + z7689 = x7689 + z7690 = x7690 + z7691 = x7691 + z7692 = x7692 + z7693 = x7693 + z7694 = x7694 + z7695 = x7695 + z7696 = x7696 + z7697 = x7697 + z7698 = x7698 + z7699 = x7699 + z7700 = x7700 + z7701 = x7701 + z7702 = x7702 + z7703 = x7703 + z7704 = x7704 + z7705 = x7705 + z7706 = x7706 + z7707 = x7707 + z7708 = x7708 + z7709 = x7709 + z7710 = x7710 + z7711 = x7711 + z7712 = x7712 + z7713 = x7713 + z7714 = x7714 + z7715 = x7715 + z7716 = x7716 + z7717 = x7717 + z7718 = x7718 + z7719 = x7719 + z7720 = x7720 + z7721 = x7721 + z7722 = x7722 + z7723 = x7723 + z7724 = x7724 + z7725 = x7725 + z7726 = x7726 + z7727 = x7727 + z7728 = x7728 + z7729 = x7729 + z7730 = x7730 + z7731 = x7731 + z7732 = x7732 + z7733 = x7733 + z7734 = x7734 + z7735 = x7735 + z7736 = x7736 + z7737 = x7737 + z7738 = x7738 + z7739 = x7739 + z7740 = x7740 + z7741 = x7741 + z7742 = x7742 + z7743 = x7743 + z7744 = x7744 + z7745 = x7745 + z7746 = x7746 + z7747 = x7747 + z7748 = x7748 + z7749 = x7749 + z7750 = x7750 + z7751 = x7751 + z7752 = x7752 + z7753 = x7753 + z7754 = x7754 + z7755 = x7755 + z7756 = x7756 + z7757 = x7757 + z7758 = x7758 + z7759 = x7759 + z7760 = x7760 + z7761 = x7761 + z7762 = x7762 + z7763 = x7763 + z7764 = x7764 + z7765 = x7765 + z7766 = x7766 + z7767 = x7767 + z7768 = x7768 + z7769 = x7769 + z7770 = x7770 + z7771 = x7771 + z7772 = x7772 + z7773 = x7773 + z7774 = x7774 + z7775 = x7775 + z7776 = x7776 + z7777 = x7777 + z7778 = x7778 + z7779 = x7779 + z7780 = x7780 + z7781 = x7781 + z7782 = x7782 + z7783 = x7783 + z7784 = x7784 + z7785 = x7785 + z7786 = x7786 + z7787 = x7787 + z7788 = x7788 + z7789 = x7789 + z7790 = x7790 + z7791 = x7791 + z7792 = x7792 + z7793 = x7793 + z7794 = x7794 + z7795 = x7795 + z7796 = x7796 + z7797 = x7797 + z7798 = x7798 + z7799 = x7799 + z7800 = x7800 + z7801 = x7801 + z7802 = x7802 + z7803 = x7803 + z7804 = x7804 + z7805 = x7805 + z7806 = x7806 + z7807 = x7807 + z7808 = x7808 + z7809 = x7809 + z7810 = x7810 + z7811 = x7811 + z7812 = x7812 + z7813 = x7813 + z7814 = x7814 + z7815 = x7815 + z7816 = x7816 + z7817 = x7817 + z7818 = x7818 + z7819 = x7819 + z7820 = x7820 + z7821 = x7821 + z7822 = x7822 + z7823 = x7823 + z7824 = x7824 + z7825 = x7825 + z7826 = x7826 + z7827 = x7827 + z7828 = x7828 + z7829 = x7829 + z7830 = x7830 + z7831 = x7831 + z7832 = x7832 + z7833 = x7833 + z7834 = x7834 + z7835 = x7835 + z7836 = x7836 + z7837 = x7837 + z7838 = x7838 + z7839 = x7839 + z7840 = x7840 + z7841 = x7841 + z7842 = x7842 + z7843 = x7843 + z7844 = x7844 + z7845 = x7845 + z7846 = x7846 + z7847 = x7847 + z7848 = x7848 + z7849 = x7849 + z7850 = x7850 + z7851 = x7851 + z7852 = x7852 + z7853 = x7853 + z7854 = x7854 + z7855 = x7855 + z7856 = x7856 + z7857 = x7857 + z7858 = x7858 + z7859 = x7859 + z7860 = x7860 + z7861 = x7861 + z7862 = x7862 + z7863 = x7863 + z7864 = x7864 + z7865 = x7865 + z7866 = x7866 + z7867 = x7867 + z7868 = x7868 + z7869 = x7869 + z7870 = x7870 + z7871 = x7871 + z7872 = x7872 + z7873 = x7873 + z7874 = x7874 + z7875 = x7875 + z7876 = x7876 + z7877 = x7877 + z7878 = x7878 + z7879 = x7879 + z7880 = x7880 + z7881 = x7881 + z7882 = x7882 + z7883 = x7883 + z7884 = x7884 + z7885 = x7885 + z7886 = x7886 + z7887 = x7887 + z7888 = x7888 + z7889 = x7889 + z7890 = x7890 + z7891 = x7891 + z7892 = x7892 + z7893 = x7893 + z7894 = x7894 + z7895 = x7895 + z7896 = x7896 + z7897 = x7897 + z7898 = x7898 + z7899 = x7899 + z7900 = x7900 + z7901 = x7901 + z7902 = x7902 + z7903 = x7903 + z7904 = x7904 + z7905 = x7905 + z7906 = x7906 + z7907 = x7907 + z7908 = x7908 + z7909 = x7909 + z7910 = x7910 + z7911 = x7911 + z7912 = x7912 + z7913 = x7913 + z7914 = x7914 + z7915 = x7915 + z7916 = x7916 + z7917 = x7917 + z7918 = x7918 + z7919 = x7919 + z7920 = x7920 + z7921 = x7921 + z7922 = x7922 + z7923 = x7923 + z7924 = x7924 + z7925 = x7925 + z7926 = x7926 + z7927 = x7927 + z7928 = x7928 + z7929 = x7929 + z7930 = x7930 + z7931 = x7931 + z7932 = x7932 + z7933 = x7933 + z7934 = x7934 + z7935 = x7935 + z7936 = x7936 + z7937 = x7937 + z7938 = x7938 + z7939 = x7939 + z7940 = x7940 + z7941 = x7941 + z7942 = x7942 + z7943 = x7943 + z7944 = x7944 + z7945 = x7945 + z7946 = x7946 + z7947 = x7947 + z7948 = x7948 + z7949 = x7949 + z7950 = x7950 + z7951 = x7951 + z7952 = x7952 + z7953 = x7953 + z7954 = x7954 + z7955 = x7955 + z7956 = x7956 + z7957 = x7957 + z7958 = x7958 + z7959 = x7959 + z7960 = x7960 + z7961 = x7961 + z7962 = x7962 + z7963 = x7963 + z7964 = x7964 + z7965 = x7965 + z7966 = x7966 + z7967 = x7967 + z7968 = x7968 + z7969 = x7969 + z7970 = x7970 + z7971 = x7971 + z7972 = x7972 + z7973 = x7973 + z7974 = x7974 + z7975 = x7975 + z7976 = x7976 + z7977 = x7977 + z7978 = x7978 + z7979 = x7979 + z7980 = x7980 + z7981 = x7981 + z7982 = x7982 + z7983 = x7983 + z7984 = x7984 + z7985 = x7985 + z7986 = x7986 + z7987 = x7987 + z7988 = x7988 + z7989 = x7989 + z7990 = x7990 + z7991 = x7991 + z7992 = x7992 + z7993 = x7993 + z7994 = x7994 + z7995 = x7995 + z7996 = x7996 + z7997 = x7997 + z7998 = x7998 + z7999 = x7999 + z8000 = x8000 + z8001 = x8001 + z8002 = x8002 + z8003 = x8003 + z8004 = x8004 + z8005 = x8005 + z8006 = x8006 + z8007 = x8007 + z8008 = x8008 + z8009 = x8009 + z8010 = x8010 + z8011 = x8011 + z8012 = x8012 + z8013 = x8013 + z8014 = x8014 + z8015 = x8015 + z8016 = x8016 + z8017 = x8017 + z8018 = x8018 + z8019 = x8019 + z8020 = x8020 + z8021 = x8021 + z8022 = x8022 + z8023 = x8023 + z8024 = x8024 + z8025 = x8025 + z8026 = x8026 + z8027 = x8027 + z8028 = x8028 + z8029 = x8029 + z8030 = x8030 + z8031 = x8031 + z8032 = x8032 + z8033 = x8033 + z8034 = x8034 + z8035 = x8035 + z8036 = x8036 + z8037 = x8037 + z8038 = x8038 + z8039 = x8039 + z8040 = x8040 + z8041 = x8041 + z8042 = x8042 + z8043 = x8043 + z8044 = x8044 + z8045 = x8045 + z8046 = x8046 + z8047 = x8047 + z8048 = x8048 + z8049 = x8049 + z8050 = x8050 + z8051 = x8051 + z8052 = x8052 + z8053 = x8053 + z8054 = x8054 + z8055 = x8055 + z8056 = x8056 + z8057 = x8057 + z8058 = x8058 + z8059 = x8059 + z8060 = x8060 + z8061 = x8061 + z8062 = x8062 + z8063 = x8063 + z8064 = x8064 + z8065 = x8065 + z8066 = x8066 + z8067 = x8067 + z8068 = x8068 + z8069 = x8069 + z8070 = x8070 + z8071 = x8071 + z8072 = x8072 + z8073 = x8073 + z8074 = x8074 + z8075 = x8075 + z8076 = x8076 + z8077 = x8077 + z8078 = x8078 + z8079 = x8079 + z8080 = x8080 + z8081 = x8081 + z8082 = x8082 + z8083 = x8083 + z8084 = x8084 + z8085 = x8085 + z8086 = x8086 + z8087 = x8087 + z8088 = x8088 + z8089 = x8089 + z8090 = x8090 + z8091 = x8091 + z8092 = x8092 + z8093 = x8093 + z8094 = x8094 + z8095 = x8095 + z8096 = x8096 + z8097 = x8097 + z8098 = x8098 + z8099 = x8099 + z8100 = x8100 + z8101 = x8101 + z8102 = x8102 + z8103 = x8103 + z8104 = x8104 + z8105 = x8105 + z8106 = x8106 + z8107 = x8107 + z8108 = x8108 + z8109 = x8109 + z8110 = x8110 + z8111 = x8111 + z8112 = x8112 + z8113 = x8113 + z8114 = x8114 + z8115 = x8115 + z8116 = x8116 + z8117 = x8117 + z8118 = x8118 + z8119 = x8119 + z8120 = x8120 + z8121 = x8121 + z8122 = x8122 + z8123 = x8123 + z8124 = x8124 + z8125 = x8125 + z8126 = x8126 + z8127 = x8127 + z8128 = x8128 + z8129 = x8129 + z8130 = x8130 + z8131 = x8131 + z8132 = x8132 + z8133 = x8133 + z8134 = x8134 + z8135 = x8135 + z8136 = x8136 + z8137 = x8137 + z8138 = x8138 + z8139 = x8139 + z8140 = x8140 + z8141 = x8141 + z8142 = x8142 + z8143 = x8143 + z8144 = x8144 + z8145 = x8145 + z8146 = x8146 + z8147 = x8147 + z8148 = x8148 + z8149 = x8149 + z8150 = x8150 + z8151 = x8151 + z8152 = x8152 + z8153 = x8153 + z8154 = x8154 + z8155 = x8155 + z8156 = x8156 + z8157 = x8157 + z8158 = x8158 + z8159 = x8159 + z8160 = x8160 + z8161 = x8161 + z8162 = x8162 + z8163 = x8163 + z8164 = x8164 + z8165 = x8165 + z8166 = x8166 + z8167 = x8167 + z8168 = x8168 + z8169 = x8169 + z8170 = x8170 + z8171 = x8171 + z8172 = x8172 + z8173 = x8173 + z8174 = x8174 + z8175 = x8175 + z8176 = x8176 + z8177 = x8177 + z8178 = x8178 + z8179 = x8179 + z8180 = x8180 + z8181 = x8181 + z8182 = x8182 + z8183 = x8183 + z8184 = x8184 + z8185 = x8185 + z8186 = x8186 + z8187 = x8187 + z8188 = x8188 + z8189 = x8189 + z8190 = x8190 + z8191 = x8191 + z8192 = x8192 + z8193 = x8193 + z8194 = x8194 + z8195 = x8195 + z8196 = x8196 + z8197 = x8197 + z8198 = x8198 + z8199 = x8199 + z8200 = x8200 + z8201 = x8201 + z8202 = x8202 + z8203 = x8203 + z8204 = x8204 + z8205 = x8205 + z8206 = x8206 + z8207 = x8207 + z8208 = x8208 + z8209 = x8209 + z8210 = x8210 + z8211 = x8211 + z8212 = x8212 + z8213 = x8213 + z8214 = x8214 + z8215 = x8215 + z8216 = x8216 + z8217 = x8217 + z8218 = x8218 + z8219 = x8219 + z8220 = x8220 + z8221 = x8221 + z8222 = x8222 + z8223 = x8223 + z8224 = x8224 + z8225 = x8225 + z8226 = x8226 + z8227 = x8227 + z8228 = x8228 + z8229 = x8229 + z8230 = x8230 + z8231 = x8231 + z8232 = x8232 + z8233 = x8233 + z8234 = x8234 + z8235 = x8235 + z8236 = x8236 + z8237 = x8237 + z8238 = x8238 + z8239 = x8239 + z8240 = x8240 + z8241 = x8241 + z8242 = x8242 + z8243 = x8243 + z8244 = x8244 + z8245 = x8245 + z8246 = x8246 + z8247 = x8247 + z8248 = x8248 + z8249 = x8249 + z8250 = x8250 + z8251 = x8251 + z8252 = x8252 + z8253 = x8253 + z8254 = x8254 + z8255 = x8255 + z8256 = x8256 + z8257 = x8257 + z8258 = x8258 + z8259 = x8259 + z8260 = x8260 + z8261 = x8261 + z8262 = x8262 + z8263 = x8263 + z8264 = x8264 + z8265 = x8265 + z8266 = x8266 + z8267 = x8267 + z8268 = x8268 + z8269 = x8269 + z8270 = x8270 + z8271 = x8271 + z8272 = x8272 + z8273 = x8273 + z8274 = x8274 + z8275 = x8275 + z8276 = x8276 + z8277 = x8277 + z8278 = x8278 + z8279 = x8279 + z8280 = x8280 + z8281 = x8281 + z8282 = x8282 + z8283 = x8283 + z8284 = x8284 + z8285 = x8285 + z8286 = x8286 + z8287 = x8287 + z8288 = x8288 + z8289 = x8289 + z8290 = x8290 + z8291 = x8291 + z8292 = x8292 + z8293 = x8293 + z8294 = x8294 + z8295 = x8295 + z8296 = x8296 + z8297 = x8297 + z8298 = x8298 + z8299 = x8299 + z8300 = x8300 + z8301 = x8301 + z8302 = x8302 + z8303 = x8303 + z8304 = x8304 + z8305 = x8305 + z8306 = x8306 + z8307 = x8307 + z8308 = x8308 + z8309 = x8309 + z8310 = x8310 + z8311 = x8311 + z8312 = x8312 + z8313 = x8313 + z8314 = x8314 + z8315 = x8315 + z8316 = x8316 + z8317 = x8317 + z8318 = x8318 + z8319 = x8319 + z8320 = x8320 + z8321 = x8321 + z8322 = x8322 + z8323 = x8323 + z8324 = x8324 + z8325 = x8325 + z8326 = x8326 + z8327 = x8327 + z8328 = x8328 + z8329 = x8329 + z8330 = x8330 + z8331 = x8331 + z8332 = x8332 + z8333 = x8333 + z8334 = x8334 + z8335 = x8335 + z8336 = x8336 + z8337 = x8337 + z8338 = x8338 + z8339 = x8339 + z8340 = x8340 + z8341 = x8341 + z8342 = x8342 + z8343 = x8343 + z8344 = x8344 + z8345 = x8345 + z8346 = x8346 + z8347 = x8347 + z8348 = x8348 + z8349 = x8349 + z8350 = x8350 + z8351 = x8351 + z8352 = x8352 + z8353 = x8353 + z8354 = x8354 + z8355 = x8355 + z8356 = x8356 + z8357 = x8357 + z8358 = x8358 + z8359 = x8359 + z8360 = x8360 + z8361 = x8361 + z8362 = x8362 + z8363 = x8363 + z8364 = x8364 + z8365 = x8365 + z8366 = x8366 + z8367 = x8367 + z8368 = x8368 + z8369 = x8369 + z8370 = x8370 + z8371 = x8371 + z8372 = x8372 + z8373 = x8373 + z8374 = x8374 + z8375 = x8375 + z8376 = x8376 + z8377 = x8377 + z8378 = x8378 + z8379 = x8379 + z8380 = x8380 + z8381 = x8381 + z8382 = x8382 + z8383 = x8383 + z8384 = x8384 + z8385 = x8385 + z8386 = x8386 + z8387 = x8387 + z8388 = x8388 + z8389 = x8389 + z8390 = x8390 + z8391 = x8391 + z8392 = x8392 + z8393 = x8393 + z8394 = x8394 + z8395 = x8395 + z8396 = x8396 + z8397 = x8397 + z8398 = x8398 + z8399 = x8399 + z8400 = x8400 + z8401 = x8401 + z8402 = x8402 + z8403 = x8403 + z8404 = x8404 + z8405 = x8405 + z8406 = x8406 + z8407 = x8407 + z8408 = x8408 + z8409 = x8409 + z8410 = x8410 + z8411 = x8411 + z8412 = x8412 + z8413 = x8413 + z8414 = x8414 + z8415 = x8415 + z8416 = x8416 + z8417 = x8417 + z8418 = x8418 + z8419 = x8419 + z8420 = x8420 + z8421 = x8421 + z8422 = x8422 + z8423 = x8423 + z8424 = x8424 + z8425 = x8425 + z8426 = x8426 + z8427 = x8427 + z8428 = x8428 + z8429 = x8429 + z8430 = x8430 + z8431 = x8431 + z8432 = x8432 + z8433 = x8433 + z8434 = x8434 + z8435 = x8435 + z8436 = x8436 + z8437 = x8437 + z8438 = x8438 + z8439 = x8439 + z8440 = x8440 + z8441 = x8441 + z8442 = x8442 + z8443 = x8443 + z8444 = x8444 + z8445 = x8445 + z8446 = x8446 + z8447 = x8447 + z8448 = x8448 + z8449 = x8449 + z8450 = x8450 + z8451 = x8451 + z8452 = x8452 + z8453 = x8453 + z8454 = x8454 + z8455 = x8455 + z8456 = x8456 + z8457 = x8457 + z8458 = x8458 + z8459 = x8459 + z8460 = x8460 + z8461 = x8461 + z8462 = x8462 + z8463 = x8463 + z8464 = x8464 + z8465 = x8465 + z8466 = x8466 + z8467 = x8467 + z8468 = x8468 + z8469 = x8469 + z8470 = x8470 + z8471 = x8471 + z8472 = x8472 + z8473 = x8473 + z8474 = x8474 + z8475 = x8475 + z8476 = x8476 + z8477 = x8477 + z8478 = x8478 + z8479 = x8479 + z8480 = x8480 + z8481 = x8481 + z8482 = x8482 + z8483 = x8483 + z8484 = x8484 + z8485 = x8485 + z8486 = x8486 + z8487 = x8487 + z8488 = x8488 + z8489 = x8489 + z8490 = x8490 + z8491 = x8491 + z8492 = x8492 + z8493 = x8493 + z8494 = x8494 + z8495 = x8495 + z8496 = x8496 + z8497 = x8497 + z8498 = x8498 + z8499 = x8499 + z8500 = x8500 + z8501 = x8501 + z8502 = x8502 + z8503 = x8503 + z8504 = x8504 + z8505 = x8505 + z8506 = x8506 + z8507 = x8507 + z8508 = x8508 + z8509 = x8509 + z8510 = x8510 + z8511 = x8511 + z8512 = x8512 + z8513 = x8513 + z8514 = x8514 + z8515 = x8515 + z8516 = x8516 + z8517 = x8517 + z8518 = x8518 + z8519 = x8519 + z8520 = x8520 + z8521 = x8521 + z8522 = x8522 + z8523 = x8523 + z8524 = x8524 + z8525 = x8525 + z8526 = x8526 + z8527 = x8527 + z8528 = x8528 + z8529 = x8529 + z8530 = x8530 + z8531 = x8531 + z8532 = x8532 + z8533 = x8533 + z8534 = x8534 + z8535 = x8535 + z8536 = x8536 + z8537 = x8537 + z8538 = x8538 + z8539 = x8539 + z8540 = x8540 + z8541 = x8541 + z8542 = x8542 + z8543 = x8543 + z8544 = x8544 + z8545 = x8545 + z8546 = x8546 + z8547 = x8547 + z8548 = x8548 + z8549 = x8549 + z8550 = x8550 + z8551 = x8551 + z8552 = x8552 + z8553 = x8553 + z8554 = x8554 + z8555 = x8555 + z8556 = x8556 + z8557 = x8557 + z8558 = x8558 + z8559 = x8559 + z8560 = x8560 + z8561 = x8561 + z8562 = x8562 + z8563 = x8563 + z8564 = x8564 + z8565 = x8565 + z8566 = x8566 + z8567 = x8567 + z8568 = x8568 + z8569 = x8569 + z8570 = x8570 + z8571 = x8571 + z8572 = x8572 + z8573 = x8573 + z8574 = x8574 + z8575 = x8575 + z8576 = x8576 + z8577 = x8577 + z8578 = x8578 + z8579 = x8579 + z8580 = x8580 + z8581 = x8581 + z8582 = x8582 + z8583 = x8583 + z8584 = x8584 + z8585 = x8585 + z8586 = x8586 + z8587 = x8587 + z8588 = x8588 + z8589 = x8589 + z8590 = x8590 + z8591 = x8591 + z8592 = x8592 + z8593 = x8593 + z8594 = x8594 + z8595 = x8595 + z8596 = x8596 + z8597 = x8597 + z8598 = x8598 + z8599 = x8599 + z8600 = x8600 + z8601 = x8601 + z8602 = x8602 + z8603 = x8603 + z8604 = x8604 + z8605 = x8605 + z8606 = x8606 + z8607 = x8607 + z8608 = x8608 + z8609 = x8609 + z8610 = x8610 + z8611 = x8611 + z8612 = x8612 + z8613 = x8613 + z8614 = x8614 + z8615 = x8615 + z8616 = x8616 + z8617 = x8617 + z8618 = x8618 + z8619 = x8619 + z8620 = x8620 + z8621 = x8621 + z8622 = x8622 + z8623 = x8623 + z8624 = x8624 + z8625 = x8625 + z8626 = x8626 + z8627 = x8627 + z8628 = x8628 + z8629 = x8629 + z8630 = x8630 + z8631 = x8631 + z8632 = x8632 + z8633 = x8633 + z8634 = x8634 + z8635 = x8635 + z8636 = x8636 + z8637 = x8637 + z8638 = x8638 + z8639 = x8639 + z8640 = x8640 + z8641 = x8641 + z8642 = x8642 + z8643 = x8643 + z8644 = x8644 + z8645 = x8645 + z8646 = x8646 + z8647 = x8647 + z8648 = x8648 + z8649 = x8649 + z8650 = x8650 + z8651 = x8651 + z8652 = x8652 + z8653 = x8653 + z8654 = x8654 + z8655 = x8655 + z8656 = x8656 + z8657 = x8657 + z8658 = x8658 + z8659 = x8659 + z8660 = x8660 + z8661 = x8661 + z8662 = x8662 + z8663 = x8663 + z8664 = x8664 + z8665 = x8665 + z8666 = x8666 + z8667 = x8667 + z8668 = x8668 + z8669 = x8669 + z8670 = x8670 + z8671 = x8671 + z8672 = x8672 + z8673 = x8673 + z8674 = x8674 + z8675 = x8675 + z8676 = x8676 + z8677 = x8677 + z8678 = x8678 + z8679 = x8679 + z8680 = x8680 + z8681 = x8681 + z8682 = x8682 + z8683 = x8683 + z8684 = x8684 + z8685 = x8685 + z8686 = x8686 + z8687 = x8687 + z8688 = x8688 + z8689 = x8689 + z8690 = x8690 + z8691 = x8691 + z8692 = x8692 + z8693 = x8693 + z8694 = x8694 + z8695 = x8695 + z8696 = x8696 + z8697 = x8697 + z8698 = x8698 + z8699 = x8699 + z8700 = x8700 + z8701 = x8701 + z8702 = x8702 + z8703 = x8703 + z8704 = x8704 + z8705 = x8705 + z8706 = x8706 + z8707 = x8707 + z8708 = x8708 + z8709 = x8709 + z8710 = x8710 + z8711 = x8711 + z8712 = x8712 + z8713 = x8713 + z8714 = x8714 + z8715 = x8715 + z8716 = x8716 + z8717 = x8717 + z8718 = x8718 + z8719 = x8719 + z8720 = x8720 + z8721 = x8721 + z8722 = x8722 + z8723 = x8723 + z8724 = x8724 + z8725 = x8725 + z8726 = x8726 + z8727 = x8727 + z8728 = x8728 + z8729 = x8729 + z8730 = x8730 + z8731 = x8731 + z8732 = x8732 + z8733 = x8733 + z8734 = x8734 + z8735 = x8735 + z8736 = x8736 + z8737 = x8737 + z8738 = x8738 + z8739 = x8739 + z8740 = x8740 + z8741 = x8741 + z8742 = x8742 + z8743 = x8743 + z8744 = x8744 + z8745 = x8745 + z8746 = x8746 + z8747 = x8747 + z8748 = x8748 + z8749 = x8749 + z8750 = x8750 + z8751 = x8751 + z8752 = x8752 + z8753 = x8753 + z8754 = x8754 + z8755 = x8755 + z8756 = x8756 + z8757 = x8757 + z8758 = x8758 + z8759 = x8759 + z8760 = x8760 + z8761 = x8761 + z8762 = x8762 + z8763 = x8763 + z8764 = x8764 + z8765 = x8765 + z8766 = x8766 + z8767 = x8767 + z8768 = x8768 + z8769 = x8769 + z8770 = x8770 + z8771 = x8771 + z8772 = x8772 + z8773 = x8773 + z8774 = x8774 + z8775 = x8775 + z8776 = x8776 + z8777 = x8777 + z8778 = x8778 + z8779 = x8779 + z8780 = x8780 + z8781 = x8781 + z8782 = x8782 + z8783 = x8783 + z8784 = x8784 + z8785 = x8785 + z8786 = x8786 + z8787 = x8787 + z8788 = x8788 + z8789 = x8789 + z8790 = x8790 + z8791 = x8791 + z8792 = x8792 + z8793 = x8793 + z8794 = x8794 + z8795 = x8795 + z8796 = x8796 + z8797 = x8797 + z8798 = x8798 + z8799 = x8799 + z8800 = x8800 + z8801 = x8801 + z8802 = x8802 + z8803 = x8803 + z8804 = x8804 + z8805 = x8805 + z8806 = x8806 + z8807 = x8807 + z8808 = x8808 + z8809 = x8809 + z8810 = x8810 + z8811 = x8811 + z8812 = x8812 + z8813 = x8813 + z8814 = x8814 + z8815 = x8815 + z8816 = x8816 + z8817 = x8817 + z8818 = x8818 + z8819 = x8819 + z8820 = x8820 + z8821 = x8821 + z8822 = x8822 + z8823 = x8823 + z8824 = x8824 + z8825 = x8825 + z8826 = x8826 + z8827 = x8827 + z8828 = x8828 + z8829 = x8829 + z8830 = x8830 + z8831 = x8831 + z8832 = x8832 + z8833 = x8833 + z8834 = x8834 + z8835 = x8835 + z8836 = x8836 + z8837 = x8837 + z8838 = x8838 + z8839 = x8839 + z8840 = x8840 + z8841 = x8841 + z8842 = x8842 + z8843 = x8843 + z8844 = x8844 + z8845 = x8845 + z8846 = x8846 + z8847 = x8847 + z8848 = x8848 + z8849 = x8849 + z8850 = x8850 + z8851 = x8851 + z8852 = x8852 + z8853 = x8853 + z8854 = x8854 + z8855 = x8855 + z8856 = x8856 + z8857 = x8857 + z8858 = x8858 + z8859 = x8859 + z8860 = x8860 + z8861 = x8861 + z8862 = x8862 + z8863 = x8863 + z8864 = x8864 + z8865 = x8865 + z8866 = x8866 + z8867 = x8867 + z8868 = x8868 + z8869 = x8869 + z8870 = x8870 + z8871 = x8871 + z8872 = x8872 + z8873 = x8873 + z8874 = x8874 + z8875 = x8875 + z8876 = x8876 + z8877 = x8877 + z8878 = x8878 + z8879 = x8879 + z8880 = x8880 + z8881 = x8881 + z8882 = x8882 + z8883 = x8883 + z8884 = x8884 + z8885 = x8885 + z8886 = x8886 + z8887 = x8887 + z8888 = x8888 + z8889 = x8889 + z8890 = x8890 + z8891 = x8891 + z8892 = x8892 + z8893 = x8893 + z8894 = x8894 + z8895 = x8895 + z8896 = x8896 + z8897 = x8897 + z8898 = x8898 + z8899 = x8899 + z8900 = x8900 + z8901 = x8901 + z8902 = x8902 + z8903 = x8903 + z8904 = x8904 + z8905 = x8905 + z8906 = x8906 + z8907 = x8907 + z8908 = x8908 + z8909 = x8909 + z8910 = x8910 + z8911 = x8911 + z8912 = x8912 + z8913 = x8913 + z8914 = x8914 + z8915 = x8915 + z8916 = x8916 + z8917 = x8917 + z8918 = x8918 + z8919 = x8919 + z8920 = x8920 + z8921 = x8921 + z8922 = x8922 + z8923 = x8923 + z8924 = x8924 + z8925 = x8925 + z8926 = x8926 + z8927 = x8927 + z8928 = x8928 + z8929 = x8929 + z8930 = x8930 + z8931 = x8931 + z8932 = x8932 + z8933 = x8933 + z8934 = x8934 + z8935 = x8935 + z8936 = x8936 + z8937 = x8937 + z8938 = x8938 + z8939 = x8939 + z8940 = x8940 + z8941 = x8941 + z8942 = x8942 + z8943 = x8943 + z8944 = x8944 + z8945 = x8945 + z8946 = x8946 + z8947 = x8947 + z8948 = x8948 + z8949 = x8949 + z8950 = x8950 + z8951 = x8951 + z8952 = x8952 + z8953 = x8953 + z8954 = x8954 + z8955 = x8955 + z8956 = x8956 + z8957 = x8957 + z8958 = x8958 + z8959 = x8959 + z8960 = x8960 + z8961 = x8961 + z8962 = x8962 + z8963 = x8963 + z8964 = x8964 + z8965 = x8965 + z8966 = x8966 + z8967 = x8967 + z8968 = x8968 + z8969 = x8969 + z8970 = x8970 + z8971 = x8971 + z8972 = x8972 + z8973 = x8973 + z8974 = x8974 + z8975 = x8975 + z8976 = x8976 + z8977 = x8977 + z8978 = x8978 + z8979 = x8979 + z8980 = x8980 + z8981 = x8981 + z8982 = x8982 + z8983 = x8983 + z8984 = x8984 + z8985 = x8985 + z8986 = x8986 + z8987 = x8987 + z8988 = x8988 + z8989 = x8989 + z8990 = x8990 + z8991 = x8991 + z8992 = x8992 + z8993 = x8993 + z8994 = x8994 + z8995 = x8995 + z8996 = x8996 + z8997 = x8997 + z8998 = x8998 + z8999 = x8999 + z9000 = x9000 + z9001 = x9001 + z9002 = x9002 + z9003 = x9003 + z9004 = x9004 + z9005 = x9005 + z9006 = x9006 + z9007 = x9007 + z9008 = x9008 + z9009 = x9009 + z9010 = x9010 + z9011 = x9011 + z9012 = x9012 + z9013 = x9013 + z9014 = x9014 + z9015 = x9015 + z9016 = x9016 + z9017 = x9017 + z9018 = x9018 + z9019 = x9019 + z9020 = x9020 + z9021 = x9021 + z9022 = x9022 + z9023 = x9023 + z9024 = x9024 + z9025 = x9025 + z9026 = x9026 + z9027 = x9027 + z9028 = x9028 + z9029 = x9029 + z9030 = x9030 + z9031 = x9031 + z9032 = x9032 + z9033 = x9033 + z9034 = x9034 + z9035 = x9035 + z9036 = x9036 + z9037 = x9037 + z9038 = x9038 + z9039 = x9039 + z9040 = x9040 + z9041 = x9041 + z9042 = x9042 + z9043 = x9043 + z9044 = x9044 + z9045 = x9045 + z9046 = x9046 + z9047 = x9047 + z9048 = x9048 + z9049 = x9049 + z9050 = x9050 + z9051 = x9051 + z9052 = x9052 + z9053 = x9053 + z9054 = x9054 + z9055 = x9055 + z9056 = x9056 + z9057 = x9057 + z9058 = x9058 + z9059 = x9059 + z9060 = x9060 + z9061 = x9061 + z9062 = x9062 + z9063 = x9063 + z9064 = x9064 + z9065 = x9065 + z9066 = x9066 + z9067 = x9067 + z9068 = x9068 + z9069 = x9069 + z9070 = x9070 + z9071 = x9071 + z9072 = x9072 + z9073 = x9073 + z9074 = x9074 + z9075 = x9075 + z9076 = x9076 + z9077 = x9077 + z9078 = x9078 + z9079 = x9079 + z9080 = x9080 + z9081 = x9081 + z9082 = x9082 + z9083 = x9083 + z9084 = x9084 + z9085 = x9085 + z9086 = x9086 + z9087 = x9087 + z9088 = x9088 + z9089 = x9089 + z9090 = x9090 + z9091 = x9091 + z9092 = x9092 + z9093 = x9093 + z9094 = x9094 + z9095 = x9095 + z9096 = x9096 + z9097 = x9097 + z9098 = x9098 + z9099 = x9099 + z9100 = x9100 + z9101 = x9101 + z9102 = x9102 + z9103 = x9103 + z9104 = x9104 + z9105 = x9105 + z9106 = x9106 + z9107 = x9107 + z9108 = x9108 + z9109 = x9109 + z9110 = x9110 + z9111 = x9111 + z9112 = x9112 + z9113 = x9113 + z9114 = x9114 + z9115 = x9115 + z9116 = x9116 + z9117 = x9117 + z9118 = x9118 + z9119 = x9119 + z9120 = x9120 + z9121 = x9121 + z9122 = x9122 + z9123 = x9123 + z9124 = x9124 + z9125 = x9125 + z9126 = x9126 + z9127 = x9127 + z9128 = x9128 + z9129 = x9129 + z9130 = x9130 + z9131 = x9131 + z9132 = x9132 + z9133 = x9133 + z9134 = x9134 + z9135 = x9135 + z9136 = x9136 + z9137 = x9137 + z9138 = x9138 + z9139 = x9139 + z9140 = x9140 + z9141 = x9141 + z9142 = x9142 + z9143 = x9143 + z9144 = x9144 + z9145 = x9145 + z9146 = x9146 + z9147 = x9147 + z9148 = x9148 + z9149 = x9149 + z9150 = x9150 + z9151 = x9151 + z9152 = x9152 + z9153 = x9153 + z9154 = x9154 + z9155 = x9155 + z9156 = x9156 + z9157 = x9157 + z9158 = x9158 + z9159 = x9159 + z9160 = x9160 + z9161 = x9161 + z9162 = x9162 + z9163 = x9163 + z9164 = x9164 + z9165 = x9165 + z9166 = x9166 + z9167 = x9167 + z9168 = x9168 + z9169 = x9169 + z9170 = x9170 + z9171 = x9171 + z9172 = x9172 + z9173 = x9173 + z9174 = x9174 + z9175 = x9175 + z9176 = x9176 + z9177 = x9177 + z9178 = x9178 + z9179 = x9179 + z9180 = x9180 + z9181 = x9181 + z9182 = x9182 + z9183 = x9183 + z9184 = x9184 + z9185 = x9185 + z9186 = x9186 + z9187 = x9187 + z9188 = x9188 + z9189 = x9189 + z9190 = x9190 + z9191 = x9191 + z9192 = x9192 + z9193 = x9193 + z9194 = x9194 + z9195 = x9195 + z9196 = x9196 + z9197 = x9197 + z9198 = x9198 + z9199 = x9199 + z9200 = x9200 + z9201 = x9201 + z9202 = x9202 + z9203 = x9203 + z9204 = x9204 + z9205 = x9205 + z9206 = x9206 + z9207 = x9207 + z9208 = x9208 + z9209 = x9209 + z9210 = x9210 + z9211 = x9211 + z9212 = x9212 + z9213 = x9213 + z9214 = x9214 + z9215 = x9215 + z9216 = x9216 + z9217 = x9217 + z9218 = x9218 + z9219 = x9219 + z9220 = x9220 + z9221 = x9221 + z9222 = x9222 + z9223 = x9223 + z9224 = x9224 + z9225 = x9225 + z9226 = x9226 + z9227 = x9227 + z9228 = x9228 + z9229 = x9229 + z9230 = x9230 + z9231 = x9231 + z9232 = x9232 + z9233 = x9233 + z9234 = x9234 + z9235 = x9235 + z9236 = x9236 + z9237 = x9237 + z9238 = x9238 + z9239 = x9239 + z9240 = x9240 + z9241 = x9241 + z9242 = x9242 + z9243 = x9243 + z9244 = x9244 + z9245 = x9245 + z9246 = x9246 + z9247 = x9247 + z9248 = x9248 + z9249 = x9249 + z9250 = x9250 + z9251 = x9251 + z9252 = x9252 + z9253 = x9253 + z9254 = x9254 + z9255 = x9255 + z9256 = x9256 + z9257 = x9257 + z9258 = x9258 + z9259 = x9259 + z9260 = x9260 + z9261 = x9261 + z9262 = x9262 + z9263 = x9263 + z9264 = x9264 + z9265 = x9265 + z9266 = x9266 + z9267 = x9267 + z9268 = x9268 + z9269 = x9269 + z9270 = x9270 + z9271 = x9271 + z9272 = x9272 + z9273 = x9273 + z9274 = x9274 + z9275 = x9275 + z9276 = x9276 + z9277 = x9277 + z9278 = x9278 + z9279 = x9279 + z9280 = x9280 + z9281 = x9281 + z9282 = x9282 + z9283 = x9283 + z9284 = x9284 + z9285 = x9285 + z9286 = x9286 + z9287 = x9287 + z9288 = x9288 + z9289 = x9289 + z9290 = x9290 + z9291 = x9291 + z9292 = x9292 + z9293 = x9293 + z9294 = x9294 + z9295 = x9295 + z9296 = x9296 + z9297 = x9297 + z9298 = x9298 + z9299 = x9299 + z9300 = x9300 + z9301 = x9301 + z9302 = x9302 + z9303 = x9303 + z9304 = x9304 + z9305 = x9305 + z9306 = x9306 + z9307 = x9307 + z9308 = x9308 + z9309 = x9309 + z9310 = x9310 + z9311 = x9311 + z9312 = x9312 + z9313 = x9313 + z9314 = x9314 + z9315 = x9315 + z9316 = x9316 + z9317 = x9317 + z9318 = x9318 + z9319 = x9319 + z9320 = x9320 + z9321 = x9321 + z9322 = x9322 + z9323 = x9323 + z9324 = x9324 + z9325 = x9325 + z9326 = x9326 + z9327 = x9327 + z9328 = x9328 + z9329 = x9329 + z9330 = x9330 + z9331 = x9331 + z9332 = x9332 + z9333 = x9333 + z9334 = x9334 + z9335 = x9335 + z9336 = x9336 + z9337 = x9337 + z9338 = x9338 + z9339 = x9339 + z9340 = x9340 + z9341 = x9341 + z9342 = x9342 + z9343 = x9343 + z9344 = x9344 + z9345 = x9345 + z9346 = x9346 + z9347 = x9347 + z9348 = x9348 + z9349 = x9349 + z9350 = x9350 + z9351 = x9351 + z9352 = x9352 + z9353 = x9353 + z9354 = x9354 + z9355 = x9355 + z9356 = x9356 + z9357 = x9357 + z9358 = x9358 + z9359 = x9359 + z9360 = x9360 + z9361 = x9361 + z9362 = x9362 + z9363 = x9363 + z9364 = x9364 + z9365 = x9365 + z9366 = x9366 + z9367 = x9367 + z9368 = x9368 + z9369 = x9369 + z9370 = x9370 + z9371 = x9371 + z9372 = x9372 + z9373 = x9373 + z9374 = x9374 + z9375 = x9375 + z9376 = x9376 + z9377 = x9377 + z9378 = x9378 + z9379 = x9379 + z9380 = x9380 + z9381 = x9381 + z9382 = x9382 + z9383 = x9383 + z9384 = x9384 + z9385 = x9385 + z9386 = x9386 + z9387 = x9387 + z9388 = x9388 + z9389 = x9389 + z9390 = x9390 + z9391 = x9391 + z9392 = x9392 + z9393 = x9393 + z9394 = x9394 + z9395 = x9395 + z9396 = x9396 + z9397 = x9397 + z9398 = x9398 + z9399 = x9399 + z9400 = x9400 + z9401 = x9401 + z9402 = x9402 + z9403 = x9403 + z9404 = x9404 + z9405 = x9405 + z9406 = x9406 + z9407 = x9407 + z9408 = x9408 + z9409 = x9409 + z9410 = x9410 + z9411 = x9411 + z9412 = x9412 + z9413 = x9413 + z9414 = x9414 + z9415 = x9415 + z9416 = x9416 + z9417 = x9417 + z9418 = x9418 + z9419 = x9419 + z9420 = x9420 + z9421 = x9421 + z9422 = x9422 + z9423 = x9423 + z9424 = x9424 + z9425 = x9425 + z9426 = x9426 + z9427 = x9427 + z9428 = x9428 + z9429 = x9429 + z9430 = x9430 + z9431 = x9431 + z9432 = x9432 + z9433 = x9433 + z9434 = x9434 + z9435 = x9435 + z9436 = x9436 + z9437 = x9437 + z9438 = x9438 + z9439 = x9439 + z9440 = x9440 + z9441 = x9441 + z9442 = x9442 + z9443 = x9443 + z9444 = x9444 + z9445 = x9445 + z9446 = x9446 + z9447 = x9447 + z9448 = x9448 + z9449 = x9449 + z9450 = x9450 + z9451 = x9451 + z9452 = x9452 + z9453 = x9453 + z9454 = x9454 + z9455 = x9455 + z9456 = x9456 + z9457 = x9457 + z9458 = x9458 + z9459 = x9459 + z9460 = x9460 + z9461 = x9461 + z9462 = x9462 + z9463 = x9463 + z9464 = x9464 + z9465 = x9465 + z9466 = x9466 + z9467 = x9467 + z9468 = x9468 + z9469 = x9469 + z9470 = x9470 + z9471 = x9471 + z9472 = x9472 + z9473 = x9473 + z9474 = x9474 + z9475 = x9475 + z9476 = x9476 + z9477 = x9477 + z9478 = x9478 + z9479 = x9479 + z9480 = x9480 + z9481 = x9481 + z9482 = x9482 + z9483 = x9483 + z9484 = x9484 + z9485 = x9485 + z9486 = x9486 + z9487 = x9487 + z9488 = x9488 + z9489 = x9489 + z9490 = x9490 + z9491 = x9491 + z9492 = x9492 + z9493 = x9493 + z9494 = x9494 + z9495 = x9495 + z9496 = x9496 + z9497 = x9497 + z9498 = x9498 + z9499 = x9499 + z9500 = x9500 + z9501 = x9501 + z9502 = x9502 + z9503 = x9503 + z9504 = x9504 + z9505 = x9505 + z9506 = x9506 + z9507 = x9507 + z9508 = x9508 + z9509 = x9509 + z9510 = x9510 + z9511 = x9511 + z9512 = x9512 + z9513 = x9513 + z9514 = x9514 + z9515 = x9515 + z9516 = x9516 + z9517 = x9517 + z9518 = x9518 + z9519 = x9519 + z9520 = x9520 + z9521 = x9521 + z9522 = x9522 + z9523 = x9523 + z9524 = x9524 + z9525 = x9525 + z9526 = x9526 + z9527 = x9527 + z9528 = x9528 + z9529 = x9529 + z9530 = x9530 + z9531 = x9531 + z9532 = x9532 + z9533 = x9533 + z9534 = x9534 + z9535 = x9535 + z9536 = x9536 + z9537 = x9537 + z9538 = x9538 + z9539 = x9539 + z9540 = x9540 + z9541 = x9541 + z9542 = x9542 + z9543 = x9543 + z9544 = x9544 + z9545 = x9545 + z9546 = x9546 + z9547 = x9547 + z9548 = x9548 + z9549 = x9549 + z9550 = x9550 + z9551 = x9551 + z9552 = x9552 + z9553 = x9553 + z9554 = x9554 + z9555 = x9555 + z9556 = x9556 + z9557 = x9557 + z9558 = x9558 + z9559 = x9559 + z9560 = x9560 + z9561 = x9561 + z9562 = x9562 + z9563 = x9563 + z9564 = x9564 + z9565 = x9565 + z9566 = x9566 + z9567 = x9567 + z9568 = x9568 + z9569 = x9569 + z9570 = x9570 + z9571 = x9571 + z9572 = x9572 + z9573 = x9573 + z9574 = x9574 + z9575 = x9575 + z9576 = x9576 + z9577 = x9577 + z9578 = x9578 + z9579 = x9579 + z9580 = x9580 + z9581 = x9581 + z9582 = x9582 + z9583 = x9583 + z9584 = x9584 + z9585 = x9585 + z9586 = x9586 + z9587 = x9587 + z9588 = x9588 + z9589 = x9589 + z9590 = x9590 + z9591 = x9591 + z9592 = x9592 + z9593 = x9593 + z9594 = x9594 + z9595 = x9595 + z9596 = x9596 + z9597 = x9597 + z9598 = x9598 + z9599 = x9599 + z9600 = x9600 + z9601 = x9601 + z9602 = x9602 + z9603 = x9603 + z9604 = x9604 + z9605 = x9605 + z9606 = x9606 + z9607 = x9607 + z9608 = x9608 + z9609 = x9609 + z9610 = x9610 + z9611 = x9611 + z9612 = x9612 + z9613 = x9613 + z9614 = x9614 + z9615 = x9615 + z9616 = x9616 + z9617 = x9617 + z9618 = x9618 + z9619 = x9619 + z9620 = x9620 + z9621 = x9621 + z9622 = x9622 + z9623 = x9623 + z9624 = x9624 + z9625 = x9625 + z9626 = x9626 + z9627 = x9627 + z9628 = x9628 + z9629 = x9629 + z9630 = x9630 + z9631 = x9631 + z9632 = x9632 + z9633 = x9633 + z9634 = x9634 + z9635 = x9635 + z9636 = x9636 + z9637 = x9637 + z9638 = x9638 + z9639 = x9639 + z9640 = x9640 + z9641 = x9641 + z9642 = x9642 + z9643 = x9643 + z9644 = x9644 + z9645 = x9645 + z9646 = x9646 + z9647 = x9647 + z9648 = x9648 + z9649 = x9649 + z9650 = x9650 + z9651 = x9651 + z9652 = x9652 + z9653 = x9653 + z9654 = x9654 + z9655 = x9655 + z9656 = x9656 + z9657 = x9657 + z9658 = x9658 + z9659 = x9659 + z9660 = x9660 + z9661 = x9661 + z9662 = x9662 + z9663 = x9663 + z9664 = x9664 + z9665 = x9665 + z9666 = x9666 + z9667 = x9667 + z9668 = x9668 + z9669 = x9669 + z9670 = x9670 + z9671 = x9671 + z9672 = x9672 + z9673 = x9673 + z9674 = x9674 + z9675 = x9675 + z9676 = x9676 + z9677 = x9677 + z9678 = x9678 + z9679 = x9679 + z9680 = x9680 + z9681 = x9681 + z9682 = x9682 + z9683 = x9683 + z9684 = x9684 + z9685 = x9685 + z9686 = x9686 + z9687 = x9687 + z9688 = x9688 + z9689 = x9689 + z9690 = x9690 + z9691 = x9691 + z9692 = x9692 + z9693 = x9693 + z9694 = x9694 + z9695 = x9695 + z9696 = x9696 + z9697 = x9697 + z9698 = x9698 + z9699 = x9699 + z9700 = x9700 + z9701 = x9701 + z9702 = x9702 + z9703 = x9703 + z9704 = x9704 + z9705 = x9705 + z9706 = x9706 + z9707 = x9707 + z9708 = x9708 + z9709 = x9709 + z9710 = x9710 + z9711 = x9711 + z9712 = x9712 + z9713 = x9713 + z9714 = x9714 + z9715 = x9715 + z9716 = x9716 + z9717 = x9717 + z9718 = x9718 + z9719 = x9719 + z9720 = x9720 + z9721 = x9721 + z9722 = x9722 + z9723 = x9723 + z9724 = x9724 + z9725 = x9725 + z9726 = x9726 + z9727 = x9727 + z9728 = x9728 + z9729 = x9729 + z9730 = x9730 + z9731 = x9731 + z9732 = x9732 + z9733 = x9733 + z9734 = x9734 + z9735 = x9735 + z9736 = x9736 + z9737 = x9737 + z9738 = x9738 + z9739 = x9739 + z9740 = x9740 + z9741 = x9741 + z9742 = x9742 + z9743 = x9743 + z9744 = x9744 + z9745 = x9745 + z9746 = x9746 + z9747 = x9747 + z9748 = x9748 + z9749 = x9749 + z9750 = x9750 + z9751 = x9751 + z9752 = x9752 + z9753 = x9753 + z9754 = x9754 + z9755 = x9755 + z9756 = x9756 + z9757 = x9757 + z9758 = x9758 + z9759 = x9759 + z9760 = x9760 + z9761 = x9761 + z9762 = x9762 + z9763 = x9763 + z9764 = x9764 + z9765 = x9765 + z9766 = x9766 + z9767 = x9767 + z9768 = x9768 + z9769 = x9769 + z9770 = x9770 + z9771 = x9771 + z9772 = x9772 + z9773 = x9773 + z9774 = x9774 + z9775 = x9775 + z9776 = x9776 + z9777 = x9777 + z9778 = x9778 + z9779 = x9779 + z9780 = x9780 + z9781 = x9781 + z9782 = x9782 + z9783 = x9783 + z9784 = x9784 + z9785 = x9785 + z9786 = x9786 + z9787 = x9787 + z9788 = x9788 + z9789 = x9789 + z9790 = x9790 + z9791 = x9791 + z9792 = x9792 + z9793 = x9793 + z9794 = x9794 + z9795 = x9795 + z9796 = x9796 + z9797 = x9797 + z9798 = x9798 + z9799 = x9799 + z9800 = x9800 + z9801 = x9801 + z9802 = x9802 + z9803 = x9803 + z9804 = x9804 + z9805 = x9805 + z9806 = x9806 + z9807 = x9807 + z9808 = x9808 + z9809 = x9809 + z9810 = x9810 + z9811 = x9811 + z9812 = x9812 + z9813 = x9813 + z9814 = x9814 + z9815 = x9815 + z9816 = x9816 + z9817 = x9817 + z9818 = x9818 + z9819 = x9819 + z9820 = x9820 + z9821 = x9821 + z9822 = x9822 + z9823 = x9823 + z9824 = x9824 + z9825 = x9825 + z9826 = x9826 + z9827 = x9827 + z9828 = x9828 + z9829 = x9829 + z9830 = x9830 + z9831 = x9831 + z9832 = x9832 + z9833 = x9833 + z9834 = x9834 + z9835 = x9835 + z9836 = x9836 + z9837 = x9837 + z9838 = x9838 + z9839 = x9839 + z9840 = x9840 + z9841 = x9841 + z9842 = x9842 + z9843 = x9843 + z9844 = x9844 + z9845 = x9845 + z9846 = x9846 + z9847 = x9847 + z9848 = x9848 + z9849 = x9849 + z9850 = x9850 + z9851 = x9851 + z9852 = x9852 + z9853 = x9853 + z9854 = x9854 + z9855 = x9855 + z9856 = x9856 + z9857 = x9857 + z9858 = x9858 + z9859 = x9859 + z9860 = x9860 + z9861 = x9861 + z9862 = x9862 + z9863 = x9863 + z9864 = x9864 + z9865 = x9865 + z9866 = x9866 + z9867 = x9867 + z9868 = x9868 + z9869 = x9869 + z9870 = x9870 + z9871 = x9871 + z9872 = x9872 + z9873 = x9873 + z9874 = x9874 + z9875 = x9875 + z9876 = x9876 + z9877 = x9877 + z9878 = x9878 + z9879 = x9879 + z9880 = x9880 + z9881 = x9881 + z9882 = x9882 + z9883 = x9883 + z9884 = x9884 + z9885 = x9885 + z9886 = x9886 + z9887 = x9887 + z9888 = x9888 + z9889 = x9889 + z9890 = x9890 + z9891 = x9891 + z9892 = x9892 + z9893 = x9893 + z9894 = x9894 + z9895 = x9895 + z9896 = x9896 + z9897 = x9897 + z9898 = x9898 + z9899 = x9899 + z9900 = x9900 + z9901 = x9901 + z9902 = x9902 + z9903 = x9903 + z9904 = x9904 + z9905 = x9905 + z9906 = x9906 + z9907 = x9907 + z9908 = x9908 + z9909 = x9909 + z9910 = x9910 + z9911 = x9911 + z9912 = x9912 + z9913 = x9913 + z9914 = x9914 + z9915 = x9915 + z9916 = x9916 + z9917 = x9917 + z9918 = x9918 + z9919 = x9919 + z9920 = x9920 + z9921 = x9921 + z9922 = x9922 + z9923 = x9923 + z9924 = x9924 + z9925 = x9925 + z9926 = x9926 + z9927 = x9927 + z9928 = x9928 + z9929 = x9929 + z9930 = x9930 + z9931 = x9931 + z9932 = x9932 + z9933 = x9933 + z9934 = x9934 + z9935 = x9935 + z9936 = x9936 + z9937 = x9937 + z9938 = x9938 + z9939 = x9939 + z9940 = x9940 + z9941 = x9941 + z9942 = x9942 + z9943 = x9943 + z9944 = x9944 + z9945 = x9945 + z9946 = x9946 + z9947 = x9947 + z9948 = x9948 + z9949 = x9949 + z9950 = x9950 + z9951 = x9951 + z9952 = x9952 + z9953 = x9953 + z9954 = x9954 + z9955 = x9955 + z9956 = x9956 + z9957 = x9957 + z9958 = x9958 + z9959 = x9959 + z9960 = x9960 + z9961 = x9961 + z9962 = x9962 + z9963 = x9963 + z9964 = x9964 + z9965 = x9965 + z9966 = x9966 + z9967 = x9967 + z9968 = x9968 + z9969 = x9969 + z9970 = x9970 + z9971 = x9971 + z9972 = x9972 + z9973 = x9973 + z9974 = x9974 + z9975 = x9975 + z9976 = x9976 + z9977 = x9977 + z9978 = x9978 + z9979 = x9979 + z9980 = x9980 + z9981 = x9981 + z9982 = x9982 + z9983 = x9983 + z9984 = x9984 + z9985 = x9985 + z9986 = x9986 + z9987 = x9987 + z9988 = x9988 + z9989 = x9989 + z9990 = x9990 + z9991 = x9991 + z9992 = x9992 + z9993 = x9993 + z9994 = x9994 + z9995 = x9995 + z9996 = x9996 + z9997 = x9997 + z9998 = x9998 + z9999 = x9999 + z10000 = x10000 + z10001 = x10001 + z10002 = x10002 + z10003 = x10003 + z10004 = x10004 + z10005 = x10005 + z10006 = x10006 + z10007 = x10007 + z10008 = x10008 + z10009 = x10009 + z10010 = x10010 + z10011 = x10011 + z10012 = x10012 + z10013 = x10013 + z10014 = x10014 + z10015 = x10015 + z10016 = x10016 + z10017 = x10017 + z10018 = x10018 + z10019 = x10019 + z10020 = x10020 + z10021 = x10021 + z10022 = x10022 + z10023 = x10023 + z10024 = x10024 + z10025 = x10025 + z10026 = x10026 + z10027 = x10027 + z10028 = x10028 + z10029 = x10029 + z10030 = x10030 + z10031 = x10031 + z10032 = x10032 + z10033 = x10033 + z10034 = x10034 + z10035 = x10035 + z10036 = x10036 + z10037 = x10037 + z10038 = x10038 + z10039 = x10039 + z10040 = x10040 + z10041 = x10041 + z10042 = x10042 + z10043 = x10043 + z10044 = x10044 + z10045 = x10045 + z10046 = x10046 + z10047 = x10047 + z10048 = x10048 + z10049 = x10049 + z10050 = x10050 + z10051 = x10051 + z10052 = x10052 + z10053 = x10053 + z10054 = x10054 + z10055 = x10055 + z10056 = x10056 + z10057 = x10057 + z10058 = x10058 + z10059 = x10059 + z10060 = x10060 + z10061 = x10061 + z10062 = x10062 + z10063 = x10063 + z10064 = x10064 + z10065 = x10065 + z10066 = x10066 + z10067 = x10067 + z10068 = x10068 + z10069 = x10069 + z10070 = x10070 + z10071 = x10071 + z10072 = x10072 + z10073 = x10073 + z10074 = x10074 + z10075 = x10075 + z10076 = x10076 + z10077 = x10077 + z10078 = x10078 + z10079 = x10079 + z10080 = x10080 + z10081 = x10081 + z10082 = x10082 + z10083 = x10083 + z10084 = x10084 + z10085 = x10085 + z10086 = x10086 + z10087 = x10087 + z10088 = x10088 + z10089 = x10089 + z10090 = x10090 + z10091 = x10091 + z10092 = x10092 + z10093 = x10093 + z10094 = x10094 + z10095 = x10095 + z10096 = x10096 + z10097 = x10097 + z10098 = x10098 + z10099 = x10099 + z10100 = x10100 + z10101 = x10101 + z10102 = x10102 + z10103 = x10103 + z10104 = x10104 + z10105 = x10105 + z10106 = x10106 + z10107 = x10107 + z10108 = x10108 + z10109 = x10109 + z10110 = x10110 + z10111 = x10111 + z10112 = x10112 + z10113 = x10113 + z10114 = x10114 + z10115 = x10115 + z10116 = x10116 + z10117 = x10117 + z10118 = x10118 + z10119 = x10119 + z10120 = x10120 + z10121 = x10121 + z10122 = x10122 + z10123 = x10123 + z10124 = x10124 + z10125 = x10125 + z10126 = x10126 + z10127 = x10127 + z10128 = x10128 + z10129 = x10129 + z10130 = x10130 + z10131 = x10131 + z10132 = x10132 + z10133 = x10133 + z10134 = x10134 + z10135 = x10135 + z10136 = x10136 + z10137 = x10137 + z10138 = x10138 + z10139 = x10139 + z10140 = x10140 + z10141 = x10141 + z10142 = x10142 + z10143 = x10143 + z10144 = x10144 + z10145 = x10145 + z10146 = x10146 + z10147 = x10147 + z10148 = x10148 + z10149 = x10149 + z10150 = x10150 + z10151 = x10151 + z10152 = x10152 + z10153 = x10153 + z10154 = x10154 + z10155 = x10155 + z10156 = x10156 + z10157 = x10157 + z10158 = x10158 + z10159 = x10159 + z10160 = x10160 + z10161 = x10161 + z10162 = x10162 + z10163 = x10163 + z10164 = x10164 + z10165 = x10165 + z10166 = x10166 + z10167 = x10167 + z10168 = x10168 + z10169 = x10169 + z10170 = x10170 + z10171 = x10171 + z10172 = x10172 + z10173 = x10173 + z10174 = x10174 + z10175 = x10175 + z10176 = x10176 + z10177 = x10177 + z10178 = x10178 + z10179 = x10179 + z10180 = x10180 + z10181 = x10181 + z10182 = x10182 + z10183 = x10183 + z10184 = x10184 + z10185 = x10185 + z10186 = x10186 + z10187 = x10187 + z10188 = x10188 + z10189 = x10189 + z10190 = x10190 + z10191 = x10191 + z10192 = x10192 + z10193 = x10193 + z10194 = x10194 + z10195 = x10195 + z10196 = x10196 + z10197 = x10197 + z10198 = x10198 + z10199 = x10199 + z10200 = x10200 + z10201 = x10201 + z10202 = x10202 + z10203 = x10203 + z10204 = x10204 + z10205 = x10205 + z10206 = x10206 + z10207 = x10207 + z10208 = x10208 + z10209 = x10209 + z10210 = x10210 + z10211 = x10211 + z10212 = x10212 + z10213 = x10213 + z10214 = x10214 + z10215 = x10215 + z10216 = x10216 + z10217 = x10217 + z10218 = x10218 + z10219 = x10219 + z10220 = x10220 + z10221 = x10221 + z10222 = x10222 + z10223 = x10223 + z10224 = x10224 + z10225 = x10225 + z10226 = x10226 + z10227 = x10227 + z10228 = x10228 + z10229 = x10229 + z10230 = x10230 + z10231 = x10231 + z10232 = x10232 + z10233 = x10233 + z10234 = x10234 + z10235 = x10235 + z10236 = x10236 + z10237 = x10237 + z10238 = x10238 + z10239 = x10239 + z10240 = x10240 + z10241 = x10241 + z10242 = x10242 + z10243 = x10243 + z10244 = x10244 + z10245 = x10245 + z10246 = x10246 + z10247 = x10247 + z10248 = x10248 + z10249 = x10249 + z10250 = x10250 + z10251 = x10251 + z10252 = x10252 + z10253 = x10253 + z10254 = x10254 + z10255 = x10255 + z10256 = x10256 + z10257 = x10257 + z10258 = x10258 + z10259 = x10259 + z10260 = x10260 + z10261 = x10261 + z10262 = x10262 + z10263 = x10263 + z10264 = x10264 + z10265 = x10265 + z10266 = x10266 + z10267 = x10267 + z10268 = x10268 + z10269 = x10269 + z10270 = x10270 + z10271 = x10271 + z10272 = x10272 + z10273 = x10273 + z10274 = x10274 + z10275 = x10275 + z10276 = x10276 + z10277 = x10277 + z10278 = x10278 + z10279 = x10279 + z10280 = x10280 + z10281 = x10281 + z10282 = x10282 + z10283 = x10283 + z10284 = x10284 + z10285 = x10285 + z10286 = x10286 + z10287 = x10287 + z10288 = x10288 + z10289 = x10289 + z10290 = x10290 + z10291 = x10291 + z10292 = x10292 + z10293 = x10293 + z10294 = x10294 + z10295 = x10295 + z10296 = x10296 + z10297 = x10297 + z10298 = x10298 + z10299 = x10299 + z10300 = x10300 + z10301 = x10301 + z10302 = x10302 + z10303 = x10303 + z10304 = x10304 + z10305 = x10305 + z10306 = x10306 + z10307 = x10307 + z10308 = x10308 + z10309 = x10309 + z10310 = x10310 + z10311 = x10311 + z10312 = x10312 + z10313 = x10313 + z10314 = x10314 + z10315 = x10315 + z10316 = x10316 + z10317 = x10317 + z10318 = x10318 + z10319 = x10319 + z10320 = x10320 + z10321 = x10321 + z10322 = x10322 + z10323 = x10323 + z10324 = x10324 + z10325 = x10325 + z10326 = x10326 + z10327 = x10327 + z10328 = x10328 + z10329 = x10329 + z10330 = x10330 + z10331 = x10331 + z10332 = x10332 + z10333 = x10333 + z10334 = x10334 + z10335 = x10335 + z10336 = x10336 + z10337 = x10337 + z10338 = x10338 + z10339 = x10339 + z10340 = x10340 + z10341 = x10341 + z10342 = x10342 + z10343 = x10343 + z10344 = x10344 + z10345 = x10345 + z10346 = x10346 + z10347 = x10347 + z10348 = x10348 + z10349 = x10349 + z10350 = x10350 + z10351 = x10351 + z10352 = x10352 + z10353 = x10353 + z10354 = x10354 + z10355 = x10355 + z10356 = x10356 + z10357 = x10357 + z10358 = x10358 + z10359 = x10359 + z10360 = x10360 + z10361 = x10361 + z10362 = x10362 + z10363 = x10363 + z10364 = x10364 + z10365 = x10365 + z10366 = x10366 + z10367 = x10367 + z10368 = x10368 + z10369 = x10369 + z10370 = x10370 + z10371 = x10371 + z10372 = x10372 + z10373 = x10373 + z10374 = x10374 + z10375 = x10375 + z10376 = x10376 + z10377 = x10377 + z10378 = x10378 + z10379 = x10379 + z10380 = x10380 + z10381 = x10381 + z10382 = x10382 + z10383 = x10383 + z10384 = x10384 + z10385 = x10385 + z10386 = x10386 + z10387 = x10387 + z10388 = x10388 + z10389 = x10389 + z10390 = x10390 + z10391 = x10391 + z10392 = x10392 + z10393 = x10393 + z10394 = x10394 + z10395 = x10395 + z10396 = x10396 + z10397 = x10397 + z10398 = x10398 + z10399 = x10399 + z10400 = x10400 + z10401 = x10401 + z10402 = x10402 + z10403 = x10403 + z10404 = x10404 + z10405 = x10405 + z10406 = x10406 + z10407 = x10407 + z10408 = x10408 + z10409 = x10409 + z10410 = x10410 + z10411 = x10411 + z10412 = x10412 + z10413 = x10413 + z10414 = x10414 + z10415 = x10415 + z10416 = x10416 + z10417 = x10417 + z10418 = x10418 + z10419 = x10419 + z10420 = x10420 + z10421 = x10421 + z10422 = x10422 + z10423 = x10423 + z10424 = x10424 + z10425 = x10425 + z10426 = x10426 + z10427 = x10427 + z10428 = x10428 + z10429 = x10429 + z10430 = x10430 + z10431 = x10431 + z10432 = x10432 + z10433 = x10433 + z10434 = x10434 + z10435 = x10435 + z10436 = x10436 + z10437 = x10437 + z10438 = x10438 + z10439 = x10439 + z10440 = x10440 + z10441 = x10441 + z10442 = x10442 + z10443 = x10443 + z10444 = x10444 + z10445 = x10445 + z10446 = x10446 + z10447 = x10447 + z10448 = x10448 + z10449 = x10449 + z10450 = x10450 + z10451 = x10451 + z10452 = x10452 + z10453 = x10453 + z10454 = x10454 + z10455 = x10455 + z10456 = x10456 + z10457 = x10457 + z10458 = x10458 + z10459 = x10459 + z10460 = x10460 + z10461 = x10461 + z10462 = x10462 + z10463 = x10463 + z10464 = x10464 + z10465 = x10465 + z10466 = x10466 + z10467 = x10467 + z10468 = x10468 + z10469 = x10469 + z10470 = x10470 + z10471 = x10471 + z10472 = x10472 + z10473 = x10473 + z10474 = x10474 + z10475 = x10475 + z10476 = x10476 + z10477 = x10477 + z10478 = x10478 + z10479 = x10479 + z10480 = x10480 + z10481 = x10481 + z10482 = x10482 + z10483 = x10483 + z10484 = x10484 + z10485 = x10485 + z10486 = x10486 + z10487 = x10487 + z10488 = x10488 + z10489 = x10489 + z10490 = x10490 + z10491 = x10491 + z10492 = x10492 + z10493 = x10493 + z10494 = x10494 + z10495 = x10495 + z10496 = x10496 + z10497 = x10497 + z10498 = x10498 + z10499 = x10499 + z10500 = x10500 + z10501 = x10501 + z10502 = x10502 + z10503 = x10503 + z10504 = x10504 + z10505 = x10505 + z10506 = x10506 + z10507 = x10507 + z10508 = x10508 + z10509 = x10509 + z10510 = x10510 + z10511 = x10511 + z10512 = x10512 + z10513 = x10513 + z10514 = x10514 + z10515 = x10515 + z10516 = x10516 + z10517 = x10517 + z10518 = x10518 + z10519 = x10519 + z10520 = x10520 + z10521 = x10521 + z10522 = x10522 + z10523 = x10523 + z10524 = x10524 + z10525 = x10525 + z10526 = x10526 + z10527 = x10527 + z10528 = x10528 + z10529 = x10529 + z10530 = x10530 + z10531 = x10531 + z10532 = x10532 + z10533 = x10533 + z10534 = x10534 + z10535 = x10535 + z10536 = x10536 + z10537 = x10537 + z10538 = x10538 + z10539 = x10539 + z10540 = x10540 + z10541 = x10541 + z10542 = x10542 + z10543 = x10543 + z10544 = x10544 + z10545 = x10545 + z10546 = x10546 + z10547 = x10547 + z10548 = x10548 + z10549 = x10549 + z10550 = x10550 + z10551 = x10551 + z10552 = x10552 + z10553 = x10553 + z10554 = x10554 + z10555 = x10555 + z10556 = x10556 + z10557 = x10557 + z10558 = x10558 + z10559 = x10559 + z10560 = x10560 + z10561 = x10561 + z10562 = x10562 + z10563 = x10563 + z10564 = x10564 + z10565 = x10565 + z10566 = x10566 + z10567 = x10567 + z10568 = x10568 + z10569 = x10569 + z10570 = x10570 + z10571 = x10571 + z10572 = x10572 + z10573 = x10573 + z10574 = x10574 + z10575 = x10575 + z10576 = x10576 + z10577 = x10577 + z10578 = x10578 + z10579 = x10579 + z10580 = x10580 + z10581 = x10581 + z10582 = x10582 + z10583 = x10583 + z10584 = x10584 + z10585 = x10585 + z10586 = x10586 + z10587 = x10587 + z10588 = x10588 + z10589 = x10589 + z10590 = x10590 + z10591 = x10591 + z10592 = x10592 + z10593 = x10593 + z10594 = x10594 + z10595 = x10595 + z10596 = x10596 + z10597 = x10597 + z10598 = x10598 + z10599 = x10599 + z10600 = x10600 + z10601 = x10601 + z10602 = x10602 + z10603 = x10603 + z10604 = x10604 + z10605 = x10605 + z10606 = x10606 + z10607 = x10607 + z10608 = x10608 + z10609 = x10609 + z10610 = x10610 + z10611 = x10611 + z10612 = x10612 + z10613 = x10613 + z10614 = x10614 + z10615 = x10615 + z10616 = x10616 + z10617 = x10617 + z10618 = x10618 + z10619 = x10619 + z10620 = x10620 + z10621 = x10621 + z10622 = x10622 + z10623 = x10623 + z10624 = x10624 + z10625 = x10625 + z10626 = x10626 + z10627 = x10627 + z10628 = x10628 + z10629 = x10629 + z10630 = x10630 + z10631 = x10631 + z10632 = x10632 + z10633 = x10633 + z10634 = x10634 + z10635 = x10635 + z10636 = x10636 + z10637 = x10637 + z10638 = x10638 + z10639 = x10639 + z10640 = x10640 + z10641 = x10641 + z10642 = x10642 + z10643 = x10643 + z10644 = x10644 + z10645 = x10645 + z10646 = x10646 + z10647 = x10647 + z10648 = x10648 + z10649 = x10649 + z10650 = x10650 + z10651 = x10651 + z10652 = x10652 + z10653 = x10653 + z10654 = x10654 + z10655 = x10655 + z10656 = x10656 + z10657 = x10657 + z10658 = x10658 + z10659 = x10659 + z10660 = x10660 + z10661 = x10661 + z10662 = x10662 + z10663 = x10663 + z10664 = x10664 + z10665 = x10665 + z10666 = x10666 + z10667 = x10667 + z10668 = x10668 + z10669 = x10669 + z10670 = x10670 + z10671 = x10671 + z10672 = x10672 + z10673 = x10673 + z10674 = x10674 + z10675 = x10675 + z10676 = x10676 + z10677 = x10677 + z10678 = x10678 + z10679 = x10679 + z10680 = x10680 + z10681 = x10681 + z10682 = x10682 + z10683 = x10683 + z10684 = x10684 + z10685 = x10685 + z10686 = x10686 + z10687 = x10687 + z10688 = x10688 + z10689 = x10689 + z10690 = x10690 + z10691 = x10691 + z10692 = x10692 + z10693 = x10693 + z10694 = x10694 + z10695 = x10695 + z10696 = x10696 + z10697 = x10697 + z10698 = x10698 + z10699 = x10699 + z10700 = x10700 + z10701 = x10701 + z10702 = x10702 + z10703 = x10703 + z10704 = x10704 + z10705 = x10705 + z10706 = x10706 + z10707 = x10707 + z10708 = x10708 + z10709 = x10709 + z10710 = x10710 + z10711 = x10711 + z10712 = x10712 + z10713 = x10713 + z10714 = x10714 + z10715 = x10715 + z10716 = x10716 + z10717 = x10717 + z10718 = x10718 + z10719 = x10719 + z10720 = x10720 + z10721 = x10721 + z10722 = x10722 + z10723 = x10723 + z10724 = x10724 + z10725 = x10725 + z10726 = x10726 + z10727 = x10727 + z10728 = x10728 + z10729 = x10729 + z10730 = x10730 + z10731 = x10731 + z10732 = x10732 + z10733 = x10733 + z10734 = x10734 + z10735 = x10735 + z10736 = x10736 + z10737 = x10737 + z10738 = x10738 + z10739 = x10739 + z10740 = x10740 + z10741 = x10741 + z10742 = x10742 + z10743 = x10743 + z10744 = x10744 + z10745 = x10745 + z10746 = x10746 + z10747 = x10747 + z10748 = x10748 + z10749 = x10749 + z10750 = x10750 + z10751 = x10751 + z10752 = x10752 + z10753 = x10753 + z10754 = x10754 + z10755 = x10755 + z10756 = x10756 + z10757 = x10757 + z10758 = x10758 + z10759 = x10759 + z10760 = x10760 + z10761 = x10761 + z10762 = x10762 + z10763 = x10763 + z10764 = x10764 + z10765 = x10765 + z10766 = x10766 + z10767 = x10767 + z10768 = x10768 + z10769 = x10769 + z10770 = x10770 + z10771 = x10771 + z10772 = x10772 + z10773 = x10773 + z10774 = x10774 + z10775 = x10775 + z10776 = x10776 + z10777 = x10777 + z10778 = x10778 + z10779 = x10779 + z10780 = x10780 + z10781 = x10781 + z10782 = x10782 + z10783 = x10783 + z10784 = x10784 + z10785 = x10785 + z10786 = x10786 + z10787 = x10787 + z10788 = x10788 + z10789 = x10789 + z10790 = x10790 + z10791 = x10791 + z10792 = x10792 + z10793 = x10793 + z10794 = x10794 + z10795 = x10795 + z10796 = x10796 + z10797 = x10797 + z10798 = x10798 + z10799 = x10799 + z10800 = x10800 + z10801 = x10801 + z10802 = x10802 + z10803 = x10803 + z10804 = x10804 + z10805 = x10805 + z10806 = x10806 + z10807 = x10807 + z10808 = x10808 + z10809 = x10809 + z10810 = x10810 + z10811 = x10811 + z10812 = x10812 + z10813 = x10813 + z10814 = x10814 + z10815 = x10815 + z10816 = x10816 + z10817 = x10817 + z10818 = x10818 + z10819 = x10819 + z10820 = x10820 + z10821 = x10821 + z10822 = x10822 + z10823 = x10823 + z10824 = x10824 + z10825 = x10825 + z10826 = x10826 + z10827 = x10827 + z10828 = x10828 + z10829 = x10829 + z10830 = x10830 + z10831 = x10831 + z10832 = x10832 + z10833 = x10833 + z10834 = x10834 + z10835 = x10835 + z10836 = x10836 + z10837 = x10837 + z10838 = x10838 + z10839 = x10839 + z10840 = x10840 + z10841 = x10841 + z10842 = x10842 + z10843 = x10843 + z10844 = x10844 + z10845 = x10845 + z10846 = x10846 + z10847 = x10847 + z10848 = x10848 + z10849 = x10849 + z10850 = x10850 + z10851 = x10851 + z10852 = x10852 + z10853 = x10853 + z10854 = x10854 + z10855 = x10855 + z10856 = x10856 + z10857 = x10857 + z10858 = x10858 + z10859 = x10859 + z10860 = x10860 + z10861 = x10861 + z10862 = x10862 + z10863 = x10863 + z10864 = x10864 + z10865 = x10865 + z10866 = x10866 + z10867 = x10867 + z10868 = x10868 + z10869 = x10869 + z10870 = x10870 + z10871 = x10871 + z10872 = x10872 + z10873 = x10873 + z10874 = x10874 + z10875 = x10875 + z10876 = x10876 + z10877 = x10877 + z10878 = x10878 + z10879 = x10879 + z10880 = x10880 + z10881 = x10881 + z10882 = x10882 + z10883 = x10883 + z10884 = x10884 + z10885 = x10885 + z10886 = x10886 + z10887 = x10887 + z10888 = x10888 + z10889 = x10889 + z10890 = x10890 + z10891 = x10891 + z10892 = x10892 + z10893 = x10893 + z10894 = x10894 + z10895 = x10895 + z10896 = x10896 + z10897 = x10897 + z10898 = x10898 + z10899 = x10899 + z10900 = x10900 + z10901 = x10901 + z10902 = x10902 + z10903 = x10903 + z10904 = x10904 + z10905 = x10905 + z10906 = x10906 + z10907 = x10907 + z10908 = x10908 + z10909 = x10909 + z10910 = x10910 + z10911 = x10911 + z10912 = x10912 + z10913 = x10913 + z10914 = x10914 + z10915 = x10915 + z10916 = x10916 + z10917 = x10917 + z10918 = x10918 + z10919 = x10919 + z10920 = x10920 + z10921 = x10921 + z10922 = x10922 + z10923 = x10923 + z10924 = x10924 + z10925 = x10925 + z10926 = x10926 + z10927 = x10927 + z10928 = x10928 + z10929 = x10929 + z10930 = x10930 + z10931 = x10931 + z10932 = x10932 + z10933 = x10933 + z10934 = x10934 + z10935 = x10935 + z10936 = x10936 + z10937 = x10937 + z10938 = x10938 + z10939 = x10939 + z10940 = x10940 + z10941 = x10941 + z10942 = x10942 + z10943 = x10943 + z10944 = x10944 + z10945 = x10945 + z10946 = x10946 + z10947 = x10947 + z10948 = x10948 + z10949 = x10949 + z10950 = x10950 + z10951 = x10951 + z10952 = x10952 + z10953 = x10953 + z10954 = x10954 + z10955 = x10955 + z10956 = x10956 + z10957 = x10957 + z10958 = x10958 + z10959 = x10959 + z10960 = x10960 + z10961 = x10961 + z10962 = x10962 + z10963 = x10963 + z10964 = x10964 + z10965 = x10965 + z10966 = x10966 + z10967 = x10967 + z10968 = x10968 + z10969 = x10969 + z10970 = x10970 + z10971 = x10971 + z10972 = x10972 + z10973 = x10973 + z10974 = x10974 + z10975 = x10975 + z10976 = x10976 + z10977 = x10977 + z10978 = x10978 + z10979 = x10979 + z10980 = x10980 + z10981 = x10981 + z10982 = x10982 + z10983 = x10983 + z10984 = x10984 + z10985 = x10985 + z10986 = x10986 + z10987 = x10987 + z10988 = x10988 + z10989 = x10989 + z10990 = x10990 + z10991 = x10991 + z10992 = x10992 + z10993 = x10993 + z10994 = x10994 + z10995 = x10995 + z10996 = x10996 + z10997 = x10997 + z10998 = x10998 + z10999 = x10999 + z11000 = x11000 + z11001 = x11001 + z11002 = x11002 + z11003 = x11003 + z11004 = x11004 + z11005 = x11005 + z11006 = x11006 + z11007 = x11007 + z11008 = x11008 + z11009 = x11009 + z11010 = x11010 + z11011 = x11011 + z11012 = x11012 + z11013 = x11013 + z11014 = x11014 + z11015 = x11015 + z11016 = x11016 + z11017 = x11017 + z11018 = x11018 + z11019 = x11019 + z11020 = x11020 + z11021 = x11021 + z11022 = x11022 + z11023 = x11023 + z11024 = x11024 + z11025 = x11025 + z11026 = x11026 + z11027 = x11027 + z11028 = x11028 + z11029 = x11029 + z11030 = x11030 + z11031 = x11031 + z11032 = x11032 + z11033 = x11033 + z11034 = x11034 + z11035 = x11035 + z11036 = x11036 + z11037 = x11037 + z11038 = x11038 + z11039 = x11039 + z11040 = x11040 + z11041 = x11041 + z11042 = x11042 + z11043 = x11043 + z11044 = x11044 + z11045 = x11045 + z11046 = x11046 + z11047 = x11047 + z11048 = x11048 + z11049 = x11049 + z11050 = x11050 + z11051 = x11051 + z11052 = x11052 + z11053 = x11053 + z11054 = x11054 + z11055 = x11055 + z11056 = x11056 + z11057 = x11057 + z11058 = x11058 + z11059 = x11059 + z11060 = x11060 + z11061 = x11061 + z11062 = x11062 + z11063 = x11063 + z11064 = x11064 + z11065 = x11065 + z11066 = x11066 + z11067 = x11067 + z11068 = x11068 + z11069 = x11069 + z11070 = x11070 + z11071 = x11071 + z11072 = x11072 + z11073 = x11073 + z11074 = x11074 + z11075 = x11075 + z11076 = x11076 + z11077 = x11077 + z11078 = x11078 + z11079 = x11079 + z11080 = x11080 + z11081 = x11081 + z11082 = x11082 + z11083 = x11083 + z11084 = x11084 + z11085 = x11085 + z11086 = x11086 + z11087 = x11087 + z11088 = x11088 + z11089 = x11089 + z11090 = x11090 + z11091 = x11091 + z11092 = x11092 + z11093 = x11093 + z11094 = x11094 + z11095 = x11095 + z11096 = x11096 + z11097 = x11097 + z11098 = x11098 + z11099 = x11099 + z11100 = x11100 + z11101 = x11101 + z11102 = x11102 + z11103 = x11103 + z11104 = x11104 + z11105 = x11105 + z11106 = x11106 + z11107 = x11107 + z11108 = x11108 + z11109 = x11109 + z11110 = x11110 + z11111 = x11111 + z11112 = x11112 + z11113 = x11113 + z11114 = x11114 + z11115 = x11115 + z11116 = x11116 + z11117 = x11117 + z11118 = x11118 + z11119 = x11119 + z11120 = x11120 + z11121 = x11121 + z11122 = x11122 + z11123 = x11123 + z11124 = x11124 + z11125 = x11125 + z11126 = x11126 + z11127 = x11127 + z11128 = x11128 + z11129 = x11129 + z11130 = x11130 + z11131 = x11131 + z11132 = x11132 + z11133 = x11133 + z11134 = x11134 + z11135 = x11135 + z11136 = x11136 + z11137 = x11137 + z11138 = x11138 + z11139 = x11139 + z11140 = x11140 + z11141 = x11141 + z11142 = x11142 + z11143 = x11143 + z11144 = x11144 + z11145 = x11145 + z11146 = x11146 + z11147 = x11147 + z11148 = x11148 + z11149 = x11149 + z11150 = x11150 + z11151 = x11151 + z11152 = x11152 + z11153 = x11153 + z11154 = x11154 + z11155 = x11155 + z11156 = x11156 + z11157 = x11157 + z11158 = x11158 + z11159 = x11159 + z11160 = x11160 + z11161 = x11161 + z11162 = x11162 + z11163 = x11163 + z11164 = x11164 + z11165 = x11165 + z11166 = x11166 + z11167 = x11167 + z11168 = x11168 + z11169 = x11169 + z11170 = x11170 + z11171 = x11171 + z11172 = x11172 + z11173 = x11173 + z11174 = x11174 + z11175 = x11175 + z11176 = x11176 + z11177 = x11177 + z11178 = x11178 + z11179 = x11179 + z11180 = x11180 + z11181 = x11181 + z11182 = x11182 + z11183 = x11183 + z11184 = x11184 + z11185 = x11185 + z11186 = x11186 + z11187 = x11187 + z11188 = x11188 + z11189 = x11189 + z11190 = x11190 + z11191 = x11191 + z11192 = x11192 + z11193 = x11193 + z11194 = x11194 + z11195 = x11195 + z11196 = x11196 + z11197 = x11197 + z11198 = x11198 + z11199 = x11199 + z11200 = x11200 + z11201 = x11201 + z11202 = x11202 + z11203 = x11203 + z11204 = x11204 + z11205 = x11205 + z11206 = x11206 + z11207 = x11207 + z11208 = x11208 + z11209 = x11209 + z11210 = x11210 + z11211 = x11211 + z11212 = x11212 + z11213 = x11213 + z11214 = x11214 + z11215 = x11215 + z11216 = x11216 + z11217 = x11217 + z11218 = x11218 + z11219 = x11219 + z11220 = x11220 + z11221 = x11221 + z11222 = x11222 + z11223 = x11223 + z11224 = x11224 + z11225 = x11225 + z11226 = x11226 + z11227 = x11227 + z11228 = x11228 + z11229 = x11229 + z11230 = x11230 + z11231 = x11231 + z11232 = x11232 + z11233 = x11233 + z11234 = x11234 + z11235 = x11235 + z11236 = x11236 + z11237 = x11237 + z11238 = x11238 + z11239 = x11239 + z11240 = x11240 + z11241 = x11241 + z11242 = x11242 + z11243 = x11243 + z11244 = x11244 + z11245 = x11245 + z11246 = x11246 + z11247 = x11247 + z11248 = x11248 + z11249 = x11249 + z11250 = x11250 + z11251 = x11251 + z11252 = x11252 + z11253 = x11253 + z11254 = x11254 + z11255 = x11255 + z11256 = x11256 + z11257 = x11257 + z11258 = x11258 + z11259 = x11259 + z11260 = x11260 + z11261 = x11261 + z11262 = x11262 + z11263 = x11263 + z11264 = x11264 + z11265 = x11265 + z11266 = x11266 + z11267 = x11267 + z11268 = x11268 + z11269 = x11269 + z11270 = x11270 + z11271 = x11271 + z11272 = x11272 + z11273 = x11273 + z11274 = x11274 + z11275 = x11275 + z11276 = x11276 + z11277 = x11277 + z11278 = x11278 + z11279 = x11279 + z11280 = x11280 + z11281 = x11281 + z11282 = x11282 + z11283 = x11283 + z11284 = x11284 + z11285 = x11285 + z11286 = x11286 + z11287 = x11287 + z11288 = x11288 + z11289 = x11289 + z11290 = x11290 + z11291 = x11291 + z11292 = x11292 + z11293 = x11293 + z11294 = x11294 + z11295 = x11295 + z11296 = x11296 + z11297 = x11297 + z11298 = x11298 + z11299 = x11299 + z11300 = x11300 + z11301 = x11301 + z11302 = x11302 + z11303 = x11303 + z11304 = x11304 + z11305 = x11305 + z11306 = x11306 + z11307 = x11307 + z11308 = x11308 + z11309 = x11309 + z11310 = x11310 + z11311 = x11311 + z11312 = x11312 + z11313 = x11313 + z11314 = x11314 + z11315 = x11315 + z11316 = x11316 + z11317 = x11317 + z11318 = x11318 + z11319 = x11319 + z11320 = x11320 + z11321 = x11321 + z11322 = x11322 + z11323 = x11323 + z11324 = x11324 + z11325 = x11325 + z11326 = x11326 + z11327 = x11327 + z11328 = x11328 + z11329 = x11329 + z11330 = x11330 + z11331 = x11331 + z11332 = x11332 + z11333 = x11333 + z11334 = x11334 + z11335 = x11335 + z11336 = x11336 + z11337 = x11337 + z11338 = x11338 + z11339 = x11339 + z11340 = x11340 + z11341 = x11341 + z11342 = x11342 + z11343 = x11343 + z11344 = x11344 + z11345 = x11345 + z11346 = x11346 + z11347 = x11347 + z11348 = x11348 + z11349 = x11349 + z11350 = x11350 + z11351 = x11351 + z11352 = x11352 + z11353 = x11353 + z11354 = x11354 + z11355 = x11355 + z11356 = x11356 + z11357 = x11357 + z11358 = x11358 + z11359 = x11359 + z11360 = x11360 + z11361 = x11361 + z11362 = x11362 + z11363 = x11363 + z11364 = x11364 + z11365 = x11365 + z11366 = x11366 + z11367 = x11367 + z11368 = x11368 + z11369 = x11369 + z11370 = x11370 + z11371 = x11371 + z11372 = x11372 + z11373 = x11373 + z11374 = x11374 + z11375 = x11375 + z11376 = x11376 + z11377 = x11377 + z11378 = x11378 + z11379 = x11379 + z11380 = x11380 + z11381 = x11381 + z11382 = x11382 + z11383 = x11383 + z11384 = x11384 + z11385 = x11385 + z11386 = x11386 + z11387 = x11387 + z11388 = x11388 + z11389 = x11389 + z11390 = x11390 + z11391 = x11391 + z11392 = x11392 + z11393 = x11393 + z11394 = x11394 + z11395 = x11395 + z11396 = x11396 + z11397 = x11397 + z11398 = x11398 + z11399 = x11399 + z11400 = x11400 + z11401 = x11401 + z11402 = x11402 + z11403 = x11403 + z11404 = x11404 + z11405 = x11405 + z11406 = x11406 + z11407 = x11407 + z11408 = x11408 + z11409 = x11409 + z11410 = x11410 + z11411 = x11411 + z11412 = x11412 + z11413 = x11413 + z11414 = x11414 + z11415 = x11415 + z11416 = x11416 + z11417 = x11417 + z11418 = x11418 + z11419 = x11419 + z11420 = x11420 + z11421 = x11421 + z11422 = x11422 + z11423 = x11423 + z11424 = x11424 + z11425 = x11425 + z11426 = x11426 + z11427 = x11427 + z11428 = x11428 + z11429 = x11429 + z11430 = x11430 + z11431 = x11431 + z11432 = x11432 + z11433 = x11433 + z11434 = x11434 + z11435 = x11435 + z11436 = x11436 + z11437 = x11437 + z11438 = x11438 + z11439 = x11439 + z11440 = x11440 + z11441 = x11441 + z11442 = x11442 + z11443 = x11443 + z11444 = x11444 + z11445 = x11445 + z11446 = x11446 + z11447 = x11447 + z11448 = x11448 + z11449 = x11449 + z11450 = x11450 + z11451 = x11451 + z11452 = x11452 + z11453 = x11453 + z11454 = x11454 + z11455 = x11455 + z11456 = x11456 + z11457 = x11457 + z11458 = x11458 + z11459 = x11459 + z11460 = x11460 + z11461 = x11461 + z11462 = x11462 + z11463 = x11463 + z11464 = x11464 + z11465 = x11465 + z11466 = x11466 + z11467 = x11467 + z11468 = x11468 + z11469 = x11469 + z11470 = x11470 + z11471 = x11471 + z11472 = x11472 + z11473 = x11473 + z11474 = x11474 + z11475 = x11475 + z11476 = x11476 + z11477 = x11477 + z11478 = x11478 + z11479 = x11479 + z11480 = x11480 + z11481 = x11481 + z11482 = x11482 + z11483 = x11483 + z11484 = x11484 + z11485 = x11485 + z11486 = x11486 + z11487 = x11487 + z11488 = x11488 + z11489 = x11489 + z11490 = x11490 + z11491 = x11491 + z11492 = x11492 + z11493 = x11493 + z11494 = x11494 + z11495 = x11495 + z11496 = x11496 + z11497 = x11497 + z11498 = x11498 + z11499 = x11499 + z11500 = x11500 + z11501 = x11501 + z11502 = x11502 + z11503 = x11503 + z11504 = x11504 + z11505 = x11505 + z11506 = x11506 + z11507 = x11507 + z11508 = x11508 + z11509 = x11509 + z11510 = x11510 + z11511 = x11511 + z11512 = x11512 + z11513 = x11513 + z11514 = x11514 + z11515 = x11515 + z11516 = x11516 + z11517 = x11517 + z11518 = x11518 + z11519 = x11519 + z11520 = x11520 + z11521 = x11521 + z11522 = x11522 + z11523 = x11523 + z11524 = x11524 + z11525 = x11525 + z11526 = x11526 + z11527 = x11527 + z11528 = x11528 + z11529 = x11529 + z11530 = x11530 + z11531 = x11531 + z11532 = x11532 + z11533 = x11533 + z11534 = x11534 + z11535 = x11535 + z11536 = x11536 + z11537 = x11537 + z11538 = x11538 + z11539 = x11539 + z11540 = x11540 + z11541 = x11541 + z11542 = x11542 + z11543 = x11543 + z11544 = x11544 + z11545 = x11545 + z11546 = x11546 + z11547 = x11547 + z11548 = x11548 + z11549 = x11549 + z11550 = x11550 + z11551 = x11551 + z11552 = x11552 + z11553 = x11553 + z11554 = x11554 + z11555 = x11555 + z11556 = x11556 + z11557 = x11557 + z11558 = x11558 + z11559 = x11559 + z11560 = x11560 + z11561 = x11561 + z11562 = x11562 + z11563 = x11563 + z11564 = x11564 + z11565 = x11565 + z11566 = x11566 + z11567 = x11567 + z11568 = x11568 + z11569 = x11569 + z11570 = x11570 + z11571 = x11571 + z11572 = x11572 + z11573 = x11573 + z11574 = x11574 + z11575 = x11575 + z11576 = x11576 + z11577 = x11577 + z11578 = x11578 + z11579 = x11579 + z11580 = x11580 + z11581 = x11581 + z11582 = x11582 + z11583 = x11583 + z11584 = x11584 + z11585 = x11585 + z11586 = x11586 + z11587 = x11587 + z11588 = x11588 + z11589 = x11589 + z11590 = x11590 + z11591 = x11591 + z11592 = x11592 + z11593 = x11593 + z11594 = x11594 + z11595 = x11595 + z11596 = x11596 + z11597 = x11597 + z11598 = x11598 + z11599 = x11599 + z11600 = x11600 + z11601 = x11601 + z11602 = x11602 + z11603 = x11603 + z11604 = x11604 + z11605 = x11605 + z11606 = x11606 + z11607 = x11607 + z11608 = x11608 + z11609 = x11609 + z11610 = x11610 + z11611 = x11611 + z11612 = x11612 + z11613 = x11613 + z11614 = x11614 + z11615 = x11615 + z11616 = x11616 + z11617 = x11617 + z11618 = x11618 + z11619 = x11619 + z11620 = x11620 + z11621 = x11621 + z11622 = x11622 + z11623 = x11623 + z11624 = x11624 + z11625 = x11625 + z11626 = x11626 + z11627 = x11627 + z11628 = x11628 + z11629 = x11629 + z11630 = x11630 + z11631 = x11631 + z11632 = x11632 + z11633 = x11633 + z11634 = x11634 + z11635 = x11635 + z11636 = x11636 + z11637 = x11637 + z11638 = x11638 + z11639 = x11639 + z11640 = x11640 + z11641 = x11641 + z11642 = x11642 + z11643 = x11643 + z11644 = x11644 + z11645 = x11645 + z11646 = x11646 + z11647 = x11647 + z11648 = x11648 + z11649 = x11649 + z11650 = x11650 + z11651 = x11651 + z11652 = x11652 + z11653 = x11653 + z11654 = x11654 + z11655 = x11655 + z11656 = x11656 + z11657 = x11657 + z11658 = x11658 + z11659 = x11659 + z11660 = x11660 + z11661 = x11661 + z11662 = x11662 + z11663 = x11663 + z11664 = x11664 + z11665 = x11665 + z11666 = x11666 + z11667 = x11667 + z11668 = x11668 + z11669 = x11669 + z11670 = x11670 + z11671 = x11671 + z11672 = x11672 + z11673 = x11673 + z11674 = x11674 + z11675 = x11675 + z11676 = x11676 + z11677 = x11677 + z11678 = x11678 + z11679 = x11679 + z11680 = x11680 + z11681 = x11681 + z11682 = x11682 + z11683 = x11683 + z11684 = x11684 + z11685 = x11685 + z11686 = x11686 + z11687 = x11687 + z11688 = x11688 + z11689 = x11689 + z11690 = x11690 + z11691 = x11691 + z11692 = x11692 + z11693 = x11693 + z11694 = x11694 + z11695 = x11695 + z11696 = x11696 + z11697 = x11697 + z11698 = x11698 + z11699 = x11699 + z11700 = x11700 + z11701 = x11701 + z11702 = x11702 + z11703 = x11703 + z11704 = x11704 + z11705 = x11705 + z11706 = x11706 + z11707 = x11707 + z11708 = x11708 + z11709 = x11709 + z11710 = x11710 + z11711 = x11711 + z11712 = x11712 + z11713 = x11713 + z11714 = x11714 + z11715 = x11715 + z11716 = x11716 + z11717 = x11717 + z11718 = x11718 + z11719 = x11719 + z11720 = x11720 + z11721 = x11721 + z11722 = x11722 + z11723 = x11723 + z11724 = x11724 + z11725 = x11725 + z11726 = x11726 + z11727 = x11727 + z11728 = x11728 + z11729 = x11729 + z11730 = x11730 + z11731 = x11731 + z11732 = x11732 + z11733 = x11733 + z11734 = x11734 + z11735 = x11735 + z11736 = x11736 + z11737 = x11737 + z11738 = x11738 + z11739 = x11739 + z11740 = x11740 + z11741 = x11741 + z11742 = x11742 + z11743 = x11743 + z11744 = x11744 + z11745 = x11745 + z11746 = x11746 + z11747 = x11747 + z11748 = x11748 + z11749 = x11749 + z11750 = x11750 + z11751 = x11751 + z11752 = x11752 + z11753 = x11753 + z11754 = x11754 + z11755 = x11755 + z11756 = x11756 + z11757 = x11757 + z11758 = x11758 + z11759 = x11759 + z11760 = x11760 + z11761 = x11761 + z11762 = x11762 + z11763 = x11763 + z11764 = x11764 + z11765 = x11765 + z11766 = x11766 + z11767 = x11767 + z11768 = x11768 + z11769 = x11769 + z11770 = x11770 + z11771 = x11771 + z11772 = x11772 + z11773 = x11773 + z11774 = x11774 + z11775 = x11775 + z11776 = x11776 + z11777 = x11777 + z11778 = x11778 + z11779 = x11779 + z11780 = x11780 + z11781 = x11781 + z11782 = x11782 + z11783 = x11783 + z11784 = x11784 + z11785 = x11785 + z11786 = x11786 + z11787 = x11787 + z11788 = x11788 + z11789 = x11789 + z11790 = x11790 + z11791 = x11791 + z11792 = x11792 + z11793 = x11793 + z11794 = x11794 + z11795 = x11795 + z11796 = x11796 + z11797 = x11797 + z11798 = x11798 + z11799 = x11799 + z11800 = x11800 + z11801 = x11801 + z11802 = x11802 + z11803 = x11803 + z11804 = x11804 + z11805 = x11805 + z11806 = x11806 + z11807 = x11807 + z11808 = x11808 + z11809 = x11809 + z11810 = x11810 + z11811 = x11811 + z11812 = x11812 + z11813 = x11813 + z11814 = x11814 + z11815 = x11815 + z11816 = x11816 + z11817 = x11817 + z11818 = x11818 + z11819 = x11819 + z11820 = x11820 + z11821 = x11821 + z11822 = x11822 + z11823 = x11823 + z11824 = x11824 + z11825 = x11825 + z11826 = x11826 + z11827 = x11827 + z11828 = x11828 + z11829 = x11829 + z11830 = x11830 + z11831 = x11831 + z11832 = x11832 + z11833 = x11833 + z11834 = x11834 + z11835 = x11835 + z11836 = x11836 + z11837 = x11837 + z11838 = x11838 + z11839 = x11839 + z11840 = x11840 + z11841 = x11841 + z11842 = x11842 + z11843 = x11843 + z11844 = x11844 + z11845 = x11845 + z11846 = x11846 + z11847 = x11847 + z11848 = x11848 + z11849 = x11849 + z11850 = x11850 + z11851 = x11851 + z11852 = x11852 + z11853 = x11853 + z11854 = x11854 + z11855 = x11855 + z11856 = x11856 + z11857 = x11857 + z11858 = x11858 + z11859 = x11859 + z11860 = x11860 + z11861 = x11861 + z11862 = x11862 + z11863 = x11863 + z11864 = x11864 + z11865 = x11865 + z11866 = x11866 + z11867 = x11867 + z11868 = x11868 + z11869 = x11869 + z11870 = x11870 + z11871 = x11871 + z11872 = x11872 + z11873 = x11873 + z11874 = x11874 + z11875 = x11875 + z11876 = x11876 + z11877 = x11877 + z11878 = x11878 + z11879 = x11879 + z11880 = x11880 + z11881 = x11881 + z11882 = x11882 + z11883 = x11883 + z11884 = x11884 + z11885 = x11885 + z11886 = x11886 + z11887 = x11887 + z11888 = x11888 + z11889 = x11889 + z11890 = x11890 + z11891 = x11891 + z11892 = x11892 + z11893 = x11893 + z11894 = x11894 + z11895 = x11895 + z11896 = x11896 + z11897 = x11897 + z11898 = x11898 + z11899 = x11899 + z11900 = x11900 + z11901 = x11901 + z11902 = x11902 + z11903 = x11903 + z11904 = x11904 + z11905 = x11905 + z11906 = x11906 + z11907 = x11907 + z11908 = x11908 + z11909 = x11909 + z11910 = x11910 + z11911 = x11911 + z11912 = x11912 + z11913 = x11913 + z11914 = x11914 + z11915 = x11915 + z11916 = x11916 + z11917 = x11917 + z11918 = x11918 + z11919 = x11919 + z11920 = x11920 + z11921 = x11921 + z11922 = x11922 + z11923 = x11923 + z11924 = x11924 + z11925 = x11925 + z11926 = x11926 + z11927 = x11927 + z11928 = x11928 + z11929 = x11929 + z11930 = x11930 + z11931 = x11931 + z11932 = x11932 + z11933 = x11933 + z11934 = x11934 + z11935 = x11935 + z11936 = x11936 + z11937 = x11937 + z11938 = x11938 + z11939 = x11939 + z11940 = x11940 + z11941 = x11941 + z11942 = x11942 + z11943 = x11943 + z11944 = x11944 + z11945 = x11945 + z11946 = x11946 + z11947 = x11947 + z11948 = x11948 + z11949 = x11949 + z11950 = x11950 + z11951 = x11951 + z11952 = x11952 + z11953 = x11953 + z11954 = x11954 + z11955 = x11955 + z11956 = x11956 + z11957 = x11957 + z11958 = x11958 + z11959 = x11959 + z11960 = x11960 + z11961 = x11961 + z11962 = x11962 + z11963 = x11963 + z11964 = x11964 + z11965 = x11965 + z11966 = x11966 + z11967 = x11967 + z11968 = x11968 + z11969 = x11969 + z11970 = x11970 + z11971 = x11971 + z11972 = x11972 + z11973 = x11973 + z11974 = x11974 + z11975 = x11975 + z11976 = x11976 + z11977 = x11977 + z11978 = x11978 + z11979 = x11979 + z11980 = x11980 + z11981 = x11981 + z11982 = x11982 + z11983 = x11983 + z11984 = x11984 + z11985 = x11985 + z11986 = x11986 + z11987 = x11987 + z11988 = x11988 + z11989 = x11989 + z11990 = x11990 + z11991 = x11991 + z11992 = x11992 + z11993 = x11993 + z11994 = x11994 + z11995 = x11995 + z11996 = x11996 + z11997 = x11997 + z11998 = x11998 + z11999 = x11999 + z12000 = x12000 + z12001 = x12001 + z12002 = x12002 + z12003 = x12003 + z12004 = x12004 + z12005 = x12005 + z12006 = x12006 + z12007 = x12007 + z12008 = x12008 + z12009 = x12009 + z12010 = x12010 + z12011 = x12011 + z12012 = x12012 + z12013 = x12013 + z12014 = x12014 + z12015 = x12015 + z12016 = x12016 + z12017 = x12017 + z12018 = x12018 + z12019 = x12019 + z12020 = x12020 + z12021 = x12021 + z12022 = x12022 + z12023 = x12023 + z12024 = x12024 + z12025 = x12025 + z12026 = x12026 + z12027 = x12027 + z12028 = x12028 + z12029 = x12029 + z12030 = x12030 + z12031 = x12031 + z12032 = x12032 + z12033 = x12033 + z12034 = x12034 + z12035 = x12035 + z12036 = x12036 + z12037 = x12037 + z12038 = x12038 + z12039 = x12039 + z12040 = x12040 + z12041 = x12041 + z12042 = x12042 + z12043 = x12043 + z12044 = x12044 + z12045 = x12045 + z12046 = x12046 + z12047 = x12047 + z12048 = x12048 + z12049 = x12049 + z12050 = x12050 + z12051 = x12051 + z12052 = x12052 + z12053 = x12053 + z12054 = x12054 + z12055 = x12055 + z12056 = x12056 + z12057 = x12057 + z12058 = x12058 + z12059 = x12059 + z12060 = x12060 + z12061 = x12061 + z12062 = x12062 + z12063 = x12063 + z12064 = x12064 + z12065 = x12065 + z12066 = x12066 + z12067 = x12067 + z12068 = x12068 + z12069 = x12069 + z12070 = x12070 + z12071 = x12071 + z12072 = x12072 + z12073 = x12073 + z12074 = x12074 + z12075 = x12075 + z12076 = x12076 + z12077 = x12077 + z12078 = x12078 + z12079 = x12079 + z12080 = x12080 + z12081 = x12081 + z12082 = x12082 + z12083 = x12083 + z12084 = x12084 + z12085 = x12085 + z12086 = x12086 + z12087 = x12087 + z12088 = x12088 + z12089 = x12089 + z12090 = x12090 + z12091 = x12091 + z12092 = x12092 + z12093 = x12093 + z12094 = x12094 + z12095 = x12095 + z12096 = x12096 + z12097 = x12097 + z12098 = x12098 + z12099 = x12099 + z12100 = x12100 + z12101 = x12101 + z12102 = x12102 + z12103 = x12103 + z12104 = x12104 + z12105 = x12105 + z12106 = x12106 + z12107 = x12107 + z12108 = x12108 + z12109 = x12109 + z12110 = x12110 + z12111 = x12111 + z12112 = x12112 + z12113 = x12113 + z12114 = x12114 + z12115 = x12115 + z12116 = x12116 + z12117 = x12117 + z12118 = x12118 + z12119 = x12119 + z12120 = x12120 + z12121 = x12121 + z12122 = x12122 + z12123 = x12123 + z12124 = x12124 + z12125 = x12125 + z12126 = x12126 + z12127 = x12127 + z12128 = x12128 + z12129 = x12129 + z12130 = x12130 + z12131 = x12131 + z12132 = x12132 + z12133 = x12133 + z12134 = x12134 + z12135 = x12135 + z12136 = x12136 + z12137 = x12137 + z12138 = x12138 + z12139 = x12139 + z12140 = x12140 + z12141 = x12141 + z12142 = x12142 + z12143 = x12143 + z12144 = x12144 + z12145 = x12145 + z12146 = x12146 + z12147 = x12147 + z12148 = x12148 + z12149 = x12149 + z12150 = x12150 + z12151 = x12151 + z12152 = x12152 + z12153 = x12153 + z12154 = x12154 + z12155 = x12155 + z12156 = x12156 + z12157 = x12157 + z12158 = x12158 + z12159 = x12159 + z12160 = x12160 + z12161 = x12161 + z12162 = x12162 + z12163 = x12163 + z12164 = x12164 + z12165 = x12165 + z12166 = x12166 + z12167 = x12167 + z12168 = x12168 + z12169 = x12169 + z12170 = x12170 + z12171 = x12171 + z12172 = x12172 + z12173 = x12173 + z12174 = x12174 + z12175 = x12175 + z12176 = x12176 + z12177 = x12177 + z12178 = x12178 + z12179 = x12179 + z12180 = x12180 + z12181 = x12181 + z12182 = x12182 + z12183 = x12183 + z12184 = x12184 + z12185 = x12185 + z12186 = x12186 + z12187 = x12187 + z12188 = x12188 + z12189 = x12189 + z12190 = x12190 + z12191 = x12191 + z12192 = x12192 + z12193 = x12193 + z12194 = x12194 + z12195 = x12195 + z12196 = x12196 + z12197 = x12197 + z12198 = x12198 + z12199 = x12199 + z12200 = x12200 + z12201 = x12201 + z12202 = x12202 + z12203 = x12203 + z12204 = x12204 + z12205 = x12205 + z12206 = x12206 + z12207 = x12207 + z12208 = x12208 + z12209 = x12209 + z12210 = x12210 + z12211 = x12211 + z12212 = x12212 + z12213 = x12213 + z12214 = x12214 + z12215 = x12215 + z12216 = x12216 + z12217 = x12217 + z12218 = x12218 + z12219 = x12219 + z12220 = x12220 + z12221 = x12221 + z12222 = x12222 + z12223 = x12223 + z12224 = x12224 + z12225 = x12225 + z12226 = x12226 + z12227 = x12227 + z12228 = x12228 + z12229 = x12229 + z12230 = x12230 + z12231 = x12231 + z12232 = x12232 + z12233 = x12233 + z12234 = x12234 + z12235 = x12235 + z12236 = x12236 + z12237 = x12237 + z12238 = x12238 + z12239 = x12239 + z12240 = x12240 + z12241 = x12241 + z12242 = x12242 + z12243 = x12243 + z12244 = x12244 + z12245 = x12245 + z12246 = x12246 + z12247 = x12247 + z12248 = x12248 + z12249 = x12249 + z12250 = x12250 + z12251 = x12251 + z12252 = x12252 + z12253 = x12253 + z12254 = x12254 + z12255 = x12255 + z12256 = x12256 + z12257 = x12257 + z12258 = x12258 + z12259 = x12259 + z12260 = x12260 + z12261 = x12261 + z12262 = x12262 + z12263 = x12263 + z12264 = x12264 + z12265 = x12265 + z12266 = x12266 + z12267 = x12267 + z12268 = x12268 + z12269 = x12269 + z12270 = x12270 + z12271 = x12271 + z12272 = x12272 + z12273 = x12273 + z12274 = x12274 + z12275 = x12275 + z12276 = x12276 + z12277 = x12277 + z12278 = x12278 + z12279 = x12279 + z12280 = x12280 + z12281 = x12281 + z12282 = x12282 + z12283 = x12283 + z12284 = x12284 + z12285 = x12285 + z12286 = x12286 + z12287 = x12287 + z12288 = x12288 + z12289 = x12289 + z12290 = x12290 + z12291 = x12291 + z12292 = x12292 + z12293 = x12293 + z12294 = x12294 + z12295 = x12295 + z12296 = x12296 + z12297 = x12297 + z12298 = x12298 + z12299 = x12299 + z12300 = x12300 + z12301 = x12301 + z12302 = x12302 + z12303 = x12303 + z12304 = x12304 + z12305 = x12305 + z12306 = x12306 + z12307 = x12307 + z12308 = x12308 + z12309 = x12309 + z12310 = x12310 + z12311 = x12311 + z12312 = x12312 + z12313 = x12313 + z12314 = x12314 + z12315 = x12315 + z12316 = x12316 + z12317 = x12317 + z12318 = x12318 + z12319 = x12319 + z12320 = x12320 + z12321 = x12321 + z12322 = x12322 + z12323 = x12323 + z12324 = x12324 + z12325 = x12325 + z12326 = x12326 + z12327 = x12327 + z12328 = x12328 + z12329 = x12329 + z12330 = x12330 + z12331 = x12331 + z12332 = x12332 + z12333 = x12333 + z12334 = x12334 + z12335 = x12335 + z12336 = x12336 + z12337 = x12337 + z12338 = x12338 + z12339 = x12339 + z12340 = x12340 + z12341 = x12341 + z12342 = x12342 + z12343 = x12343 + z12344 = x12344 + z12345 = x12345 + z12346 = x12346 + z12347 = x12347 + z12348 = x12348 + z12349 = x12349 + z12350 = x12350 + z12351 = x12351 + z12352 = x12352 + z12353 = x12353 + z12354 = x12354 + z12355 = x12355 + z12356 = x12356 + z12357 = x12357 + z12358 = x12358 + z12359 = x12359 + z12360 = x12360 + z12361 = x12361 + z12362 = x12362 + z12363 = x12363 + z12364 = x12364 + z12365 = x12365 + z12366 = x12366 + z12367 = x12367 + z12368 = x12368 + z12369 = x12369 + z12370 = x12370 + z12371 = x12371 + z12372 = x12372 + z12373 = x12373 + z12374 = x12374 + z12375 = x12375 + z12376 = x12376 + z12377 = x12377 + z12378 = x12378 + z12379 = x12379 + z12380 = x12380 + z12381 = x12381 + z12382 = x12382 + z12383 = x12383 + z12384 = x12384 + z12385 = x12385 + z12386 = x12386 + z12387 = x12387 + z12388 = x12388 + z12389 = x12389 + z12390 = x12390 + z12391 = x12391 + z12392 = x12392 + z12393 = x12393 + z12394 = x12394 + z12395 = x12395 + z12396 = x12396 + z12397 = x12397 + z12398 = x12398 + z12399 = x12399 + z12400 = x12400 + z12401 = x12401 + z12402 = x12402 + z12403 = x12403 + z12404 = x12404 + z12405 = x12405 + z12406 = x12406 + z12407 = x12407 + z12408 = x12408 + z12409 = x12409 + z12410 = x12410 + z12411 = x12411 + z12412 = x12412 + z12413 = x12413 + z12414 = x12414 + z12415 = x12415 + z12416 = x12416 + z12417 = x12417 + z12418 = x12418 + z12419 = x12419 + z12420 = x12420 + z12421 = x12421 + z12422 = x12422 + z12423 = x12423 + z12424 = x12424 + z12425 = x12425 + z12426 = x12426 + z12427 = x12427 + z12428 = x12428 + z12429 = x12429 + z12430 = x12430 + z12431 = x12431 + z12432 = x12432 + z12433 = x12433 + z12434 = x12434 + z12435 = x12435 + z12436 = x12436 + z12437 = x12437 + z12438 = x12438 + z12439 = x12439 + z12440 = x12440 + z12441 = x12441 + z12442 = x12442 + z12443 = x12443 + z12444 = x12444 + z12445 = x12445 + z12446 = x12446 + z12447 = x12447 + z12448 = x12448 + z12449 = x12449 + z12450 = x12450 + z12451 = x12451 + z12452 = x12452 + z12453 = x12453 + z12454 = x12454 + z12455 = x12455 + z12456 = x12456 + z12457 = x12457 + z12458 = x12458 + z12459 = x12459 + z12460 = x12460 + z12461 = x12461 + z12462 = x12462 + z12463 = x12463 + z12464 = x12464 + z12465 = x12465 + z12466 = x12466 + z12467 = x12467 + z12468 = x12468 + z12469 = x12469 + z12470 = x12470 + z12471 = x12471 + z12472 = x12472 + z12473 = x12473 + z12474 = x12474 + z12475 = x12475 + z12476 = x12476 + z12477 = x12477 + z12478 = x12478 + z12479 = x12479 + z12480 = x12480 + z12481 = x12481 + z12482 = x12482 + z12483 = x12483 + z12484 = x12484 + z12485 = x12485 + z12486 = x12486 + z12487 = x12487 + z12488 = x12488 + z12489 = x12489 + z12490 = x12490 + z12491 = x12491 + z12492 = x12492 + z12493 = x12493 + z12494 = x12494 + z12495 = x12495 + z12496 = x12496 + z12497 = x12497 + z12498 = x12498 + z12499 = x12499 + z12500 = x12500 + z12501 = x12501 + z12502 = x12502 + z12503 = x12503 + z12504 = x12504 + z12505 = x12505 + z12506 = x12506 + z12507 = x12507 + z12508 = x12508 + z12509 = x12509 + z12510 = x12510 + z12511 = x12511 + z12512 = x12512 + z12513 = x12513 + z12514 = x12514 + z12515 = x12515 + z12516 = x12516 + z12517 = x12517 + z12518 = x12518 + z12519 = x12519 + z12520 = x12520 + z12521 = x12521 + z12522 = x12522 + z12523 = x12523 + z12524 = x12524 + z12525 = x12525 + z12526 = x12526 + z12527 = x12527 + z12528 = x12528 + z12529 = x12529 + z12530 = x12530 + z12531 = x12531 + z12532 = x12532 + z12533 = x12533 + z12534 = x12534 + z12535 = x12535 + z12536 = x12536 + z12537 = x12537 + z12538 = x12538 + z12539 = x12539 + z12540 = x12540 + z12541 = x12541 + z12542 = x12542 + z12543 = x12543 + z12544 = x12544 + z12545 = x12545 + z12546 = x12546 + z12547 = x12547 + z12548 = x12548 + z12549 = x12549 + z12550 = x12550 + z12551 = x12551 + z12552 = x12552 + z12553 = x12553 + z12554 = x12554 + z12555 = x12555 + z12556 = x12556 + z12557 = x12557 + z12558 = x12558 + z12559 = x12559 + z12560 = x12560 + z12561 = x12561 + z12562 = x12562 + z12563 = x12563 + z12564 = x12564 + z12565 = x12565 + z12566 = x12566 + z12567 = x12567 + z12568 = x12568 + z12569 = x12569 + z12570 = x12570 + z12571 = x12571 + z12572 = x12572 + z12573 = x12573 + z12574 = x12574 + z12575 = x12575 + z12576 = x12576 + z12577 = x12577 + z12578 = x12578 + z12579 = x12579 + z12580 = x12580 + z12581 = x12581 + z12582 = x12582 + z12583 = x12583 + z12584 = x12584 + z12585 = x12585 + z12586 = x12586 + z12587 = x12587 + z12588 = x12588 + z12589 = x12589 + z12590 = x12590 + z12591 = x12591 + z12592 = x12592 + z12593 = x12593 + z12594 = x12594 + z12595 = x12595 + z12596 = x12596 + z12597 = x12597 + z12598 = x12598 + z12599 = x12599 + z12600 = x12600 + z12601 = x12601 + z12602 = x12602 + z12603 = x12603 + z12604 = x12604 + z12605 = x12605 + z12606 = x12606 + z12607 = x12607 + z12608 = x12608 + z12609 = x12609 + z12610 = x12610 + z12611 = x12611 + z12612 = x12612 + z12613 = x12613 + z12614 = x12614 + z12615 = x12615 + z12616 = x12616 + z12617 = x12617 + z12618 = x12618 + z12619 = x12619 + z12620 = x12620 + z12621 = x12621 + z12622 = x12622 + z12623 = x12623 + z12624 = x12624 + z12625 = x12625 + z12626 = x12626 + z12627 = x12627 + z12628 = x12628 + z12629 = x12629 + z12630 = x12630 + z12631 = x12631 + z12632 = x12632 + z12633 = x12633 + z12634 = x12634 + z12635 = x12635 + z12636 = x12636 + z12637 = x12637 + z12638 = x12638 + z12639 = x12639 + z12640 = x12640 + z12641 = x12641 + z12642 = x12642 + z12643 = x12643 + z12644 = x12644 + z12645 = x12645 + z12646 = x12646 + z12647 = x12647 + z12648 = x12648 + z12649 = x12649 + z12650 = x12650 + z12651 = x12651 + z12652 = x12652 + z12653 = x12653 + z12654 = x12654 + z12655 = x12655 + z12656 = x12656 + z12657 = x12657 + z12658 = x12658 + z12659 = x12659 + z12660 = x12660 + z12661 = x12661 + z12662 = x12662 + z12663 = x12663 + z12664 = x12664 + z12665 = x12665 + z12666 = x12666 + z12667 = x12667 + z12668 = x12668 + z12669 = x12669 + z12670 = x12670 + z12671 = x12671 + z12672 = x12672 + z12673 = x12673 + z12674 = x12674 + z12675 = x12675 + z12676 = x12676 + z12677 = x12677 + z12678 = x12678 + z12679 = x12679 + z12680 = x12680 + z12681 = x12681 + z12682 = x12682 + z12683 = x12683 + z12684 = x12684 + z12685 = x12685 + z12686 = x12686 + z12687 = x12687 + z12688 = x12688 + z12689 = x12689 + z12690 = x12690 + z12691 = x12691 + z12692 = x12692 + z12693 = x12693 + z12694 = x12694 + z12695 = x12695 + z12696 = x12696 + z12697 = x12697 + z12698 = x12698 + z12699 = x12699 + z12700 = x12700 + z12701 = x12701 + z12702 = x12702 + z12703 = x12703 + z12704 = x12704 + z12705 = x12705 + z12706 = x12706 + z12707 = x12707 + z12708 = x12708 + z12709 = x12709 + z12710 = x12710 + z12711 = x12711 + z12712 = x12712 + z12713 = x12713 + z12714 = x12714 + z12715 = x12715 + z12716 = x12716 + z12717 = x12717 + z12718 = x12718 + z12719 = x12719 + z12720 = x12720 + z12721 = x12721 + z12722 = x12722 + z12723 = x12723 + z12724 = x12724 + z12725 = x12725 + z12726 = x12726 + z12727 = x12727 + z12728 = x12728 + z12729 = x12729 + z12730 = x12730 + z12731 = x12731 + z12732 = x12732 + z12733 = x12733 + z12734 = x12734 + z12735 = x12735 + z12736 = x12736 + z12737 = x12737 + z12738 = x12738 + z12739 = x12739 + z12740 = x12740 + z12741 = x12741 + z12742 = x12742 + z12743 = x12743 + z12744 = x12744 + z12745 = x12745 + z12746 = x12746 + z12747 = x12747 + z12748 = x12748 + z12749 = x12749 + z12750 = x12750 + z12751 = x12751 + z12752 = x12752 + z12753 = x12753 + z12754 = x12754 + z12755 = x12755 + z12756 = x12756 + z12757 = x12757 + z12758 = x12758 + z12759 = x12759 + z12760 = x12760 + z12761 = x12761 + z12762 = x12762 + z12763 = x12763 + z12764 = x12764 + z12765 = x12765 + z12766 = x12766 + z12767 = x12767 + z12768 = x12768 + z12769 = x12769 + z12770 = x12770 + z12771 = x12771 + z12772 = x12772 + z12773 = x12773 + z12774 = x12774 + z12775 = x12775 + z12776 = x12776 + z12777 = x12777 + z12778 = x12778 + z12779 = x12779 + z12780 = x12780 + z12781 = x12781 + z12782 = x12782 + z12783 = x12783 + z12784 = x12784 + z12785 = x12785 + z12786 = x12786 + z12787 = x12787 + z12788 = x12788 + z12789 = x12789 + z12790 = x12790 + z12791 = x12791 + z12792 = x12792 + z12793 = x12793 + z12794 = x12794 + z12795 = x12795 + z12796 = x12796 + z12797 = x12797 + z12798 = x12798 + z12799 = x12799 + z12800 = x12800 + z12801 = x12801 + z12802 = x12802 + z12803 = x12803 + z12804 = x12804 + z12805 = x12805 + z12806 = x12806 + z12807 = x12807 + z12808 = x12808 + z12809 = x12809 + z12810 = x12810 + z12811 = x12811 + z12812 = x12812 + z12813 = x12813 + z12814 = x12814 + z12815 = x12815 + z12816 = x12816 + z12817 = x12817 + z12818 = x12818 + z12819 = x12819 + z12820 = x12820 + z12821 = x12821 + z12822 = x12822 + z12823 = x12823 + z12824 = x12824 + z12825 = x12825 + z12826 = x12826 + z12827 = x12827 + z12828 = x12828 + z12829 = x12829 + z12830 = x12830 + z12831 = x12831 + z12832 = x12832 + z12833 = x12833 + z12834 = x12834 + z12835 = x12835 + z12836 = x12836 + z12837 = x12837 + z12838 = x12838 + z12839 = x12839 + z12840 = x12840 + z12841 = x12841 + z12842 = x12842 + z12843 = x12843 + z12844 = x12844 + z12845 = x12845 + z12846 = x12846 + z12847 = x12847 + z12848 = x12848 + z12849 = x12849 + z12850 = x12850 + z12851 = x12851 + z12852 = x12852 + z12853 = x12853 + z12854 = x12854 + z12855 = x12855 + z12856 = x12856 + z12857 = x12857 + z12858 = x12858 + z12859 = x12859 + z12860 = x12860 + z12861 = x12861 + z12862 = x12862 + z12863 = x12863 + z12864 = x12864 + z12865 = x12865 + z12866 = x12866 + z12867 = x12867 + z12868 = x12868 + z12869 = x12869 + z12870 = x12870 + z12871 = x12871 + z12872 = x12872 + z12873 = x12873 + z12874 = x12874 + z12875 = x12875 + z12876 = x12876 + z12877 = x12877 + z12878 = x12878 + z12879 = x12879 + z12880 = x12880 + z12881 = x12881 + z12882 = x12882 + z12883 = x12883 + z12884 = x12884 + z12885 = x12885 + z12886 = x12886 + z12887 = x12887 + z12888 = x12888 + z12889 = x12889 + z12890 = x12890 + z12891 = x12891 + z12892 = x12892 + z12893 = x12893 + z12894 = x12894 + z12895 = x12895 + z12896 = x12896 + z12897 = x12897 + z12898 = x12898 + z12899 = x12899 + z12900 = x12900 + z12901 = x12901 + z12902 = x12902 + z12903 = x12903 + z12904 = x12904 + z12905 = x12905 + z12906 = x12906 + z12907 = x12907 + z12908 = x12908 + z12909 = x12909 + z12910 = x12910 + z12911 = x12911 + z12912 = x12912 + z12913 = x12913 + z12914 = x12914 + z12915 = x12915 + z12916 = x12916 + z12917 = x12917 + z12918 = x12918 + z12919 = x12919 + z12920 = x12920 + z12921 = x12921 + z12922 = x12922 + z12923 = x12923 + z12924 = x12924 + z12925 = x12925 + z12926 = x12926 + z12927 = x12927 + z12928 = x12928 + z12929 = x12929 + z12930 = x12930 + z12931 = x12931 + z12932 = x12932 + z12933 = x12933 + z12934 = x12934 + z12935 = x12935 + z12936 = x12936 + z12937 = x12937 + z12938 = x12938 + z12939 = x12939 + z12940 = x12940 + z12941 = x12941 + z12942 = x12942 + z12943 = x12943 + z12944 = x12944 + z12945 = x12945 + z12946 = x12946 + z12947 = x12947 + z12948 = x12948 + z12949 = x12949 + z12950 = x12950 + z12951 = x12951 + z12952 = x12952 + z12953 = x12953 + z12954 = x12954 + z12955 = x12955 + z12956 = x12956 + z12957 = x12957 + z12958 = x12958 + z12959 = x12959 + z12960 = x12960 + z12961 = x12961 + z12962 = x12962 + z12963 = x12963 + z12964 = x12964 + z12965 = x12965 + z12966 = x12966 + z12967 = x12967 + z12968 = x12968 + z12969 = x12969 + z12970 = x12970 + z12971 = x12971 + z12972 = x12972 + z12973 = x12973 + z12974 = x12974 + z12975 = x12975 + z12976 = x12976 + z12977 = x12977 + z12978 = x12978 + z12979 = x12979 + z12980 = x12980 + z12981 = x12981 + z12982 = x12982 + z12983 = x12983 + z12984 = x12984 + z12985 = x12985 + z12986 = x12986 + z12987 = x12987 + z12988 = x12988 + z12989 = x12989 + z12990 = x12990 + z12991 = x12991 + z12992 = x12992 + z12993 = x12993 + z12994 = x12994 + z12995 = x12995 + z12996 = x12996 + z12997 = x12997 + z12998 = x12998 + z12999 = x12999 + z13000 = x13000 + z13001 = x13001 + z13002 = x13002 + z13003 = x13003 + z13004 = x13004 + z13005 = x13005 + z13006 = x13006 + z13007 = x13007 + z13008 = x13008 + z13009 = x13009 + z13010 = x13010 + z13011 = x13011 + z13012 = x13012 + z13013 = x13013 + z13014 = x13014 + z13015 = x13015 + z13016 = x13016 + z13017 = x13017 + z13018 = x13018 + z13019 = x13019 + z13020 = x13020 + z13021 = x13021 + z13022 = x13022 + z13023 = x13023 + z13024 = x13024 + z13025 = x13025 + z13026 = x13026 + z13027 = x13027 + z13028 = x13028 + z13029 = x13029 + z13030 = x13030 + z13031 = x13031 + z13032 = x13032 + z13033 = x13033 + z13034 = x13034 + z13035 = x13035 + z13036 = x13036 + z13037 = x13037 + z13038 = x13038 + z13039 = x13039 + z13040 = x13040 + z13041 = x13041 + z13042 = x13042 + z13043 = x13043 + z13044 = x13044 + z13045 = x13045 + z13046 = x13046 + z13047 = x13047 + z13048 = x13048 + z13049 = x13049 + z13050 = x13050 + z13051 = x13051 + z13052 = x13052 + z13053 = x13053 + z13054 = x13054 + z13055 = x13055 + z13056 = x13056 + z13057 = x13057 + z13058 = x13058 + z13059 = x13059 + z13060 = x13060 + z13061 = x13061 + z13062 = x13062 + z13063 = x13063 + z13064 = x13064 + z13065 = x13065 + z13066 = x13066 + z13067 = x13067 + z13068 = x13068 + z13069 = x13069 + z13070 = x13070 + z13071 = x13071 + z13072 = x13072 + z13073 = x13073 + z13074 = x13074 + z13075 = x13075 + z13076 = x13076 + z13077 = x13077 + z13078 = x13078 + z13079 = x13079 + z13080 = x13080 + z13081 = x13081 + z13082 = x13082 + z13083 = x13083 + z13084 = x13084 + z13085 = x13085 + z13086 = x13086 + z13087 = x13087 + z13088 = x13088 + z13089 = x13089 + z13090 = x13090 + z13091 = x13091 + z13092 = x13092 + z13093 = x13093 + z13094 = x13094 + z13095 = x13095 + z13096 = x13096 + z13097 = x13097 + z13098 = x13098 + z13099 = x13099 + z13100 = x13100 + z13101 = x13101 + z13102 = x13102 + z13103 = x13103 + z13104 = x13104 + z13105 = x13105 + z13106 = x13106 + z13107 = x13107 + z13108 = x13108 + z13109 = x13109 + z13110 = x13110 + z13111 = x13111 + z13112 = x13112 + z13113 = x13113 + z13114 = x13114 + z13115 = x13115 + z13116 = x13116 + z13117 = x13117 + z13118 = x13118 + z13119 = x13119 + z13120 = x13120 + z13121 = x13121 + z13122 = x13122 + z13123 = x13123 + z13124 = x13124 + z13125 = x13125 + z13126 = x13126 + z13127 = x13127 + z13128 = x13128 + z13129 = x13129 + z13130 = x13130 + z13131 = x13131 + z13132 = x13132 + z13133 = x13133 + z13134 = x13134 + z13135 = x13135 + z13136 = x13136 + z13137 = x13137 + z13138 = x13138 + z13139 = x13139 + z13140 = x13140 + z13141 = x13141 + z13142 = x13142 + z13143 = x13143 + z13144 = x13144 + z13145 = x13145 + z13146 = x13146 + z13147 = x13147 + z13148 = x13148 + z13149 = x13149 + z13150 = x13150 + z13151 = x13151 + z13152 = x13152 + z13153 = x13153 + z13154 = x13154 + z13155 = x13155 + z13156 = x13156 + z13157 = x13157 + z13158 = x13158 + z13159 = x13159 + z13160 = x13160 + z13161 = x13161 + z13162 = x13162 + z13163 = x13163 + z13164 = x13164 + z13165 = x13165 + z13166 = x13166 + z13167 = x13167 + z13168 = x13168 + z13169 = x13169 + z13170 = x13170 + z13171 = x13171 + z13172 = x13172 + z13173 = x13173 + z13174 = x13174 + z13175 = x13175 + z13176 = x13176 + z13177 = x13177 + z13178 = x13178 + z13179 = x13179 + z13180 = x13180 + z13181 = x13181 + z13182 = x13182 + z13183 = x13183 + z13184 = x13184 + z13185 = x13185 + z13186 = x13186 + z13187 = x13187 + z13188 = x13188 + z13189 = x13189 + z13190 = x13190 + z13191 = x13191 + z13192 = x13192 + z13193 = x13193 + z13194 = x13194 + z13195 = x13195 + z13196 = x13196 + z13197 = x13197 + z13198 = x13198 + z13199 = x13199 + z13200 = x13200 + z13201 = x13201 + z13202 = x13202 + z13203 = x13203 + z13204 = x13204 + z13205 = x13205 + z13206 = x13206 + z13207 = x13207 + z13208 = x13208 + z13209 = x13209 + z13210 = x13210 + z13211 = x13211 + z13212 = x13212 + z13213 = x13213 + z13214 = x13214 + z13215 = x13215 + z13216 = x13216 + z13217 = x13217 + z13218 = x13218 + z13219 = x13219 + z13220 = x13220 + z13221 = x13221 + z13222 = x13222 + z13223 = x13223 + z13224 = x13224 + z13225 = x13225 + z13226 = x13226 + z13227 = x13227 + z13228 = x13228 + z13229 = x13229 + z13230 = x13230 + z13231 = x13231 + z13232 = x13232 + z13233 = x13233 + z13234 = x13234 + z13235 = x13235 + z13236 = x13236 + z13237 = x13237 + z13238 = x13238 + z13239 = x13239 + z13240 = x13240 + z13241 = x13241 + z13242 = x13242 + z13243 = x13243 + z13244 = x13244 + z13245 = x13245 + z13246 = x13246 + z13247 = x13247 + z13248 = x13248 + z13249 = x13249 + z13250 = x13250 + z13251 = x13251 + z13252 = x13252 + z13253 = x13253 + z13254 = x13254 + z13255 = x13255 + z13256 = x13256 + z13257 = x13257 + z13258 = x13258 + z13259 = x13259 + z13260 = x13260 + z13261 = x13261 + z13262 = x13262 + z13263 = x13263 + z13264 = x13264 + z13265 = x13265 + z13266 = x13266 + z13267 = x13267 + z13268 = x13268 + z13269 = x13269 + z13270 = x13270 + z13271 = x13271 + z13272 = x13272 + z13273 = x13273 + z13274 = x13274 + z13275 = x13275 + z13276 = x13276 + z13277 = x13277 + z13278 = x13278 + z13279 = x13279 + z13280 = x13280 + z13281 = x13281 + z13282 = x13282 + z13283 = x13283 + z13284 = x13284 + z13285 = x13285 + z13286 = x13286 + z13287 = x13287 + z13288 = x13288 + z13289 = x13289 + z13290 = x13290 + z13291 = x13291 + z13292 = x13292 + z13293 = x13293 + z13294 = x13294 + z13295 = x13295 + z13296 = x13296 + z13297 = x13297 + z13298 = x13298 + z13299 = x13299 + z13300 = x13300 + z13301 = x13301 + z13302 = x13302 + z13303 = x13303 + z13304 = x13304 + z13305 = x13305 + z13306 = x13306 + z13307 = x13307 + z13308 = x13308 + z13309 = x13309 + z13310 = x13310 + z13311 = x13311 + z13312 = x13312 + z13313 = x13313 + z13314 = x13314 + z13315 = x13315 + z13316 = x13316 + z13317 = x13317 + z13318 = x13318 + z13319 = x13319 + z13320 = x13320 + z13321 = x13321 + z13322 = x13322 + z13323 = x13323 + z13324 = x13324 + z13325 = x13325 + z13326 = x13326 + z13327 = x13327 + z13328 = x13328 + z13329 = x13329 + z13330 = x13330 + z13331 = x13331 + z13332 = x13332 + z13333 = x13333 + z13334 = x13334 + z13335 = x13335 + z13336 = x13336 + z13337 = x13337 + z13338 = x13338 + z13339 = x13339 + z13340 = x13340 + z13341 = x13341 + z13342 = x13342 + z13343 = x13343 + z13344 = x13344 + z13345 = x13345 + z13346 = x13346 + z13347 = x13347 + z13348 = x13348 + z13349 = x13349 + z13350 = x13350 + z13351 = x13351 + z13352 = x13352 + z13353 = x13353 + z13354 = x13354 + z13355 = x13355 + z13356 = x13356 + z13357 = x13357 + z13358 = x13358 + z13359 = x13359 + z13360 = x13360 + z13361 = x13361 + z13362 = x13362 + z13363 = x13363 + z13364 = x13364 + z13365 = x13365 + z13366 = x13366 + z13367 = x13367 + z13368 = x13368 + z13369 = x13369 + z13370 = x13370 + z13371 = x13371 + z13372 = x13372 + z13373 = x13373 + z13374 = x13374 + z13375 = x13375 + z13376 = x13376 + z13377 = x13377 + z13378 = x13378 + z13379 = x13379 + z13380 = x13380 + z13381 = x13381 + z13382 = x13382 + z13383 = x13383 + z13384 = x13384 + z13385 = x13385 + z13386 = x13386 + z13387 = x13387 + z13388 = x13388 + z13389 = x13389 + z13390 = x13390 + z13391 = x13391 + z13392 = x13392 + z13393 = x13393 + z13394 = x13394 + z13395 = x13395 + z13396 = x13396 + z13397 = x13397 + z13398 = x13398 + z13399 = x13399 + z13400 = x13400 + z13401 = x13401 + z13402 = x13402 + z13403 = x13403 + z13404 = x13404 + z13405 = x13405 + z13406 = x13406 + z13407 = x13407 + z13408 = x13408 + z13409 = x13409 + z13410 = x13410 + z13411 = x13411 + z13412 = x13412 + z13413 = x13413 + z13414 = x13414 + z13415 = x13415 + z13416 = x13416 + z13417 = x13417 + z13418 = x13418 + z13419 = x13419 + z13420 = x13420 + z13421 = x13421 + z13422 = x13422 + z13423 = x13423 + z13424 = x13424 + z13425 = x13425 + z13426 = x13426 + z13427 = x13427 + z13428 = x13428 + z13429 = x13429 + z13430 = x13430 + z13431 = x13431 + z13432 = x13432 + z13433 = x13433 + z13434 = x13434 + z13435 = x13435 + z13436 = x13436 + z13437 = x13437 + z13438 = x13438 + z13439 = x13439 + z13440 = x13440 + z13441 = x13441 + z13442 = x13442 + z13443 = x13443 + z13444 = x13444 + z13445 = x13445 + z13446 = x13446 + z13447 = x13447 + z13448 = x13448 + z13449 = x13449 + z13450 = x13450 + z13451 = x13451 + z13452 = x13452 + z13453 = x13453 + z13454 = x13454 + z13455 = x13455 + z13456 = x13456 + z13457 = x13457 + z13458 = x13458 + z13459 = x13459 + z13460 = x13460 + z13461 = x13461 + z13462 = x13462 + z13463 = x13463 + z13464 = x13464 + z13465 = x13465 + z13466 = x13466 + z13467 = x13467 + z13468 = x13468 + z13469 = x13469 + z13470 = x13470 + z13471 = x13471 + z13472 = x13472 + z13473 = x13473 + z13474 = x13474 + z13475 = x13475 + z13476 = x13476 + z13477 = x13477 + z13478 = x13478 + z13479 = x13479 + z13480 = x13480 + z13481 = x13481 + z13482 = x13482 + z13483 = x13483 + z13484 = x13484 + z13485 = x13485 + z13486 = x13486 + z13487 = x13487 + z13488 = x13488 + z13489 = x13489 + z13490 = x13490 + z13491 = x13491 + z13492 = x13492 + z13493 = x13493 + z13494 = x13494 + z13495 = x13495 + z13496 = x13496 + z13497 = x13497 + z13498 = x13498 + z13499 = x13499 + z13500 = x13500 + z13501 = x13501 + z13502 = x13502 + z13503 = x13503 + z13504 = x13504 + z13505 = x13505 + z13506 = x13506 + z13507 = x13507 + z13508 = x13508 + z13509 = x13509 + z13510 = x13510 + z13511 = x13511 + z13512 = x13512 + z13513 = x13513 + z13514 = x13514 + z13515 = x13515 + z13516 = x13516 + z13517 = x13517 + z13518 = x13518 + z13519 = x13519 + z13520 = x13520 + z13521 = x13521 + z13522 = x13522 + z13523 = x13523 + z13524 = x13524 + z13525 = x13525 + z13526 = x13526 + z13527 = x13527 + z13528 = x13528 + z13529 = x13529 + z13530 = x13530 + z13531 = x13531 + z13532 = x13532 + z13533 = x13533 + z13534 = x13534 + z13535 = x13535 + z13536 = x13536 + z13537 = x13537 + z13538 = x13538 + z13539 = x13539 + z13540 = x13540 + z13541 = x13541 + z13542 = x13542 + z13543 = x13543 + z13544 = x13544 + z13545 = x13545 + z13546 = x13546 + z13547 = x13547 + z13548 = x13548 + z13549 = x13549 + z13550 = x13550 + z13551 = x13551 + z13552 = x13552 + z13553 = x13553 + z13554 = x13554 + z13555 = x13555 + z13556 = x13556 + z13557 = x13557 + z13558 = x13558 + z13559 = x13559 + z13560 = x13560 + z13561 = x13561 + z13562 = x13562 + z13563 = x13563 + z13564 = x13564 + z13565 = x13565 + z13566 = x13566 + z13567 = x13567 + z13568 = x13568 + z13569 = x13569 + z13570 = x13570 + z13571 = x13571 + z13572 = x13572 + z13573 = x13573 + z13574 = x13574 + z13575 = x13575 + z13576 = x13576 + z13577 = x13577 + z13578 = x13578 + z13579 = x13579 + z13580 = x13580 + z13581 = x13581 + z13582 = x13582 + z13583 = x13583 + z13584 = x13584 + z13585 = x13585 + z13586 = x13586 + z13587 = x13587 + z13588 = x13588 + z13589 = x13589 + z13590 = x13590 + z13591 = x13591 + z13592 = x13592 + z13593 = x13593 + z13594 = x13594 + z13595 = x13595 + z13596 = x13596 + z13597 = x13597 + z13598 = x13598 + z13599 = x13599 + z13600 = x13600 + z13601 = x13601 + z13602 = x13602 + z13603 = x13603 + z13604 = x13604 + z13605 = x13605 + z13606 = x13606 + z13607 = x13607 + z13608 = x13608 + z13609 = x13609 + z13610 = x13610 + z13611 = x13611 + z13612 = x13612 + z13613 = x13613 + z13614 = x13614 + z13615 = x13615 + z13616 = x13616 + z13617 = x13617 + z13618 = x13618 + z13619 = x13619 + z13620 = x13620 + z13621 = x13621 + z13622 = x13622 + z13623 = x13623 + z13624 = x13624 + z13625 = x13625 + z13626 = x13626 + z13627 = x13627 + z13628 = x13628 + z13629 = x13629 + z13630 = x13630 + z13631 = x13631 + z13632 = x13632 + z13633 = x13633 + z13634 = x13634 + z13635 = x13635 + z13636 = x13636 + z13637 = x13637 + z13638 = x13638 + z13639 = x13639 + z13640 = x13640 + z13641 = x13641 + z13642 = x13642 + z13643 = x13643 + z13644 = x13644 + z13645 = x13645 + z13646 = x13646 + z13647 = x13647 + z13648 = x13648 + z13649 = x13649 + z13650 = x13650 + z13651 = x13651 + z13652 = x13652 + z13653 = x13653 + z13654 = x13654 + z13655 = x13655 + z13656 = x13656 + z13657 = x13657 + z13658 = x13658 + z13659 = x13659 + z13660 = x13660 + z13661 = x13661 + z13662 = x13662 + z13663 = x13663 + z13664 = x13664 + z13665 = x13665 + z13666 = x13666 + z13667 = x13667 + z13668 = x13668 + z13669 = x13669 + z13670 = x13670 + z13671 = x13671 + z13672 = x13672 + z13673 = x13673 + z13674 = x13674 + z13675 = x13675 + z13676 = x13676 + z13677 = x13677 + z13678 = x13678 + z13679 = x13679 + z13680 = x13680 + z13681 = x13681 + z13682 = x13682 + z13683 = x13683 + z13684 = x13684 + z13685 = x13685 + z13686 = x13686 + z13687 = x13687 + z13688 = x13688 + z13689 = x13689 + z13690 = x13690 + z13691 = x13691 + z13692 = x13692 + z13693 = x13693 + z13694 = x13694 + z13695 = x13695 + z13696 = x13696 + z13697 = x13697 + z13698 = x13698 + z13699 = x13699 + z13700 = x13700 + z13701 = x13701 + z13702 = x13702 + z13703 = x13703 + z13704 = x13704 + z13705 = x13705 + z13706 = x13706 + z13707 = x13707 + z13708 = x13708 + z13709 = x13709 + z13710 = x13710 + z13711 = x13711 + z13712 = x13712 + z13713 = x13713 + z13714 = x13714 + z13715 = x13715 + z13716 = x13716 + z13717 = x13717 + z13718 = x13718 + z13719 = x13719 + z13720 = x13720 + z13721 = x13721 + z13722 = x13722 + z13723 = x13723 + z13724 = x13724 + z13725 = x13725 + z13726 = x13726 + z13727 = x13727 + z13728 = x13728 + z13729 = x13729 + z13730 = x13730 + z13731 = x13731 + z13732 = x13732 + z13733 = x13733 + z13734 = x13734 + z13735 = x13735 + z13736 = x13736 + z13737 = x13737 + z13738 = x13738 + z13739 = x13739 + z13740 = x13740 + z13741 = x13741 + z13742 = x13742 + z13743 = x13743 + z13744 = x13744 + z13745 = x13745 + z13746 = x13746 + z13747 = x13747 + z13748 = x13748 + z13749 = x13749 + z13750 = x13750 + z13751 = x13751 + z13752 = x13752 + z13753 = x13753 + z13754 = x13754 + z13755 = x13755 + z13756 = x13756 + z13757 = x13757 + z13758 = x13758 + z13759 = x13759 + z13760 = x13760 + z13761 = x13761 + z13762 = x13762 + z13763 = x13763 + z13764 = x13764 + z13765 = x13765 + z13766 = x13766 + z13767 = x13767 + z13768 = x13768 + z13769 = x13769 + z13770 = x13770 + z13771 = x13771 + z13772 = x13772 + z13773 = x13773 + z13774 = x13774 + z13775 = x13775 + z13776 = x13776 + z13777 = x13777 + z13778 = x13778 + z13779 = x13779 + z13780 = x13780 + z13781 = x13781 + z13782 = x13782 + z13783 = x13783 + z13784 = x13784 + z13785 = x13785 + z13786 = x13786 + z13787 = x13787 + z13788 = x13788 + z13789 = x13789 + z13790 = x13790 + z13791 = x13791 + z13792 = x13792 + z13793 = x13793 + z13794 = x13794 + z13795 = x13795 + z13796 = x13796 + z13797 = x13797 + z13798 = x13798 + z13799 = x13799 + z13800 = x13800 + z13801 = x13801 + z13802 = x13802 + z13803 = x13803 + z13804 = x13804 + z13805 = x13805 + z13806 = x13806 + z13807 = x13807 + z13808 = x13808 + z13809 = x13809 + z13810 = x13810 + z13811 = x13811 + z13812 = x13812 + z13813 = x13813 + z13814 = x13814 + z13815 = x13815 + z13816 = x13816 + z13817 = x13817 + z13818 = x13818 + z13819 = x13819 + z13820 = x13820 + z13821 = x13821 + z13822 = x13822 + z13823 = x13823 + z13824 = x13824 + z13825 = x13825 + z13826 = x13826 + z13827 = x13827 + z13828 = x13828 + z13829 = x13829 + z13830 = x13830 + z13831 = x13831 + z13832 = x13832 + z13833 = x13833 + z13834 = x13834 + z13835 = x13835 + z13836 = x13836 + z13837 = x13837 + z13838 = x13838 + z13839 = x13839 + z13840 = x13840 + z13841 = x13841 + z13842 = x13842 + z13843 = x13843 + z13844 = x13844 + z13845 = x13845 + z13846 = x13846 + z13847 = x13847 + z13848 = x13848 + z13849 = x13849 + z13850 = x13850 + z13851 = x13851 + z13852 = x13852 + z13853 = x13853 + z13854 = x13854 + z13855 = x13855 + z13856 = x13856 + z13857 = x13857 + z13858 = x13858 + z13859 = x13859 + z13860 = x13860 + z13861 = x13861 + z13862 = x13862 + z13863 = x13863 + z13864 = x13864 + z13865 = x13865 + z13866 = x13866 + z13867 = x13867 + z13868 = x13868 + z13869 = x13869 + z13870 = x13870 + z13871 = x13871 + z13872 = x13872 + z13873 = x13873 + z13874 = x13874 + z13875 = x13875 + z13876 = x13876 + z13877 = x13877 + z13878 = x13878 + z13879 = x13879 + z13880 = x13880 + z13881 = x13881 + z13882 = x13882 + z13883 = x13883 + z13884 = x13884 + z13885 = x13885 + z13886 = x13886 + z13887 = x13887 + z13888 = x13888 + z13889 = x13889 + z13890 = x13890 + z13891 = x13891 + z13892 = x13892 + z13893 = x13893 + z13894 = x13894 + z13895 = x13895 + z13896 = x13896 + z13897 = x13897 + z13898 = x13898 + z13899 = x13899 + z13900 = x13900 + z13901 = x13901 + z13902 = x13902 + z13903 = x13903 + z13904 = x13904 + z13905 = x13905 + z13906 = x13906 + z13907 = x13907 + z13908 = x13908 + z13909 = x13909 + z13910 = x13910 + z13911 = x13911 + z13912 = x13912 + z13913 = x13913 + z13914 = x13914 + z13915 = x13915 + z13916 = x13916 + z13917 = x13917 + z13918 = x13918 + z13919 = x13919 + z13920 = x13920 + z13921 = x13921 + z13922 = x13922 + z13923 = x13923 + z13924 = x13924 + z13925 = x13925 + z13926 = x13926 + z13927 = x13927 + z13928 = x13928 + z13929 = x13929 + z13930 = x13930 + z13931 = x13931 + z13932 = x13932 + z13933 = x13933 + z13934 = x13934 + z13935 = x13935 + z13936 = x13936 + z13937 = x13937 + z13938 = x13938 + z13939 = x13939 + z13940 = x13940 + z13941 = x13941 + z13942 = x13942 + z13943 = x13943 + z13944 = x13944 + z13945 = x13945 + z13946 = x13946 + z13947 = x13947 + z13948 = x13948 + z13949 = x13949 + z13950 = x13950 + z13951 = x13951 + z13952 = x13952 + z13953 = x13953 + z13954 = x13954 + z13955 = x13955 + z13956 = x13956 + z13957 = x13957 + z13958 = x13958 + z13959 = x13959 + z13960 = x13960 + z13961 = x13961 + z13962 = x13962 + z13963 = x13963 + z13964 = x13964 + z13965 = x13965 + z13966 = x13966 + z13967 = x13967 + z13968 = x13968 + z13969 = x13969 + z13970 = x13970 + z13971 = x13971 + z13972 = x13972 + z13973 = x13973 + z13974 = x13974 + z13975 = x13975 + z13976 = x13976 + z13977 = x13977 + z13978 = x13978 + z13979 = x13979 + z13980 = x13980 + z13981 = x13981 + z13982 = x13982 + z13983 = x13983 + z13984 = x13984 + z13985 = x13985 + z13986 = x13986 + z13987 = x13987 + z13988 = x13988 + z13989 = x13989 + z13990 = x13990 + z13991 = x13991 + z13992 = x13992 + z13993 = x13993 + z13994 = x13994 + z13995 = x13995 + z13996 = x13996 + z13997 = x13997 + z13998 = x13998 + z13999 = x13999 + z14000 = x14000 + z14001 = x14001 + z14002 = x14002 + z14003 = x14003 + z14004 = x14004 + z14005 = x14005 + z14006 = x14006 + z14007 = x14007 + z14008 = x14008 + z14009 = x14009 + z14010 = x14010 + z14011 = x14011 + z14012 = x14012 + z14013 = x14013 + z14014 = x14014 + z14015 = x14015 + z14016 = x14016 + z14017 = x14017 + z14018 = x14018 + z14019 = x14019 + z14020 = x14020 + z14021 = x14021 + z14022 = x14022 + z14023 = x14023 + z14024 = x14024 + z14025 = x14025 + z14026 = x14026 + z14027 = x14027 + z14028 = x14028 + z14029 = x14029 + z14030 = x14030 + z14031 = x14031 + z14032 = x14032 + z14033 = x14033 + z14034 = x14034 + z14035 = x14035 + z14036 = x14036 + z14037 = x14037 + z14038 = x14038 + z14039 = x14039 + z14040 = x14040 + z14041 = x14041 + z14042 = x14042 + z14043 = x14043 + z14044 = x14044 + z14045 = x14045 + z14046 = x14046 + z14047 = x14047 + z14048 = x14048 + z14049 = x14049 + z14050 = x14050 + z14051 = x14051 + z14052 = x14052 + z14053 = x14053 + z14054 = x14054 + z14055 = x14055 + z14056 = x14056 + z14057 = x14057 + z14058 = x14058 + z14059 = x14059 + z14060 = x14060 + z14061 = x14061 + z14062 = x14062 + z14063 = x14063 + z14064 = x14064 + z14065 = x14065 + z14066 = x14066 + z14067 = x14067 + z14068 = x14068 + z14069 = x14069 + z14070 = x14070 + z14071 = x14071 + z14072 = x14072 + z14073 = x14073 + z14074 = x14074 + z14075 = x14075 + z14076 = x14076 + z14077 = x14077 + z14078 = x14078 + z14079 = x14079 + z14080 = x14080 + z14081 = x14081 + z14082 = x14082 + z14083 = x14083 + z14084 = x14084 + z14085 = x14085 + z14086 = x14086 + z14087 = x14087 + z14088 = x14088 + z14089 = x14089 + z14090 = x14090 + z14091 = x14091 + z14092 = x14092 + z14093 = x14093 + z14094 = x14094 + z14095 = x14095 + z14096 = x14096 + z14097 = x14097 + z14098 = x14098 + z14099 = x14099 + z14100 = x14100 + z14101 = x14101 + z14102 = x14102 + z14103 = x14103 + z14104 = x14104 + z14105 = x14105 + z14106 = x14106 + z14107 = x14107 + z14108 = x14108 + z14109 = x14109 + z14110 = x14110 + z14111 = x14111 + z14112 = x14112 + z14113 = x14113 + z14114 = x14114 + z14115 = x14115 + z14116 = x14116 + z14117 = x14117 + z14118 = x14118 + z14119 = x14119 + z14120 = x14120 + z14121 = x14121 + z14122 = x14122 + z14123 = x14123 + z14124 = x14124 + z14125 = x14125 + z14126 = x14126 + z14127 = x14127 + z14128 = x14128 + z14129 = x14129 + z14130 = x14130 + z14131 = x14131 + z14132 = x14132 + z14133 = x14133 + z14134 = x14134 + z14135 = x14135 + z14136 = x14136 + z14137 = x14137 + z14138 = x14138 + z14139 = x14139 + z14140 = x14140 + z14141 = x14141 + z14142 = x14142 + z14143 = x14143 + z14144 = x14144 + z14145 = x14145 + z14146 = x14146 + z14147 = x14147 + z14148 = x14148 + z14149 = x14149 + z14150 = x14150 + z14151 = x14151 + z14152 = x14152 + z14153 = x14153 + z14154 = x14154 + z14155 = x14155 + z14156 = x14156 + z14157 = x14157 + z14158 = x14158 + z14159 = x14159 + z14160 = x14160 + z14161 = x14161 + z14162 = x14162 + z14163 = x14163 + z14164 = x14164 + z14165 = x14165 + z14166 = x14166 + z14167 = x14167 + z14168 = x14168 + z14169 = x14169 + z14170 = x14170 + z14171 = x14171 + z14172 = x14172 + z14173 = x14173 + z14174 = x14174 + z14175 = x14175 + z14176 = x14176 + z14177 = x14177 + z14178 = x14178 + z14179 = x14179 + z14180 = x14180 + z14181 = x14181 + z14182 = x14182 + z14183 = x14183 + z14184 = x14184 + z14185 = x14185 + z14186 = x14186 + z14187 = x14187 + z14188 = x14188 + z14189 = x14189 + z14190 = x14190 + z14191 = x14191 + z14192 = x14192 + z14193 = x14193 + z14194 = x14194 + z14195 = x14195 + z14196 = x14196 + z14197 = x14197 + z14198 = x14198 + z14199 = x14199 + z14200 = x14200 + z14201 = x14201 + z14202 = x14202 + z14203 = x14203 + z14204 = x14204 + z14205 = x14205 + z14206 = x14206 + z14207 = x14207 + z14208 = x14208 + z14209 = x14209 + z14210 = x14210 + z14211 = x14211 + z14212 = x14212 + z14213 = x14213 + z14214 = x14214 + z14215 = x14215 + z14216 = x14216 + z14217 = x14217 + z14218 = x14218 + z14219 = x14219 + z14220 = x14220 + z14221 = x14221 + z14222 = x14222 + z14223 = x14223 + z14224 = x14224 + z14225 = x14225 + z14226 = x14226 + z14227 = x14227 + z14228 = x14228 + z14229 = x14229 + z14230 = x14230 + z14231 = x14231 + z14232 = x14232 + z14233 = x14233 + z14234 = x14234 + z14235 = x14235 + z14236 = x14236 + z14237 = x14237 + z14238 = x14238 + z14239 = x14239 + z14240 = x14240 + z14241 = x14241 + z14242 = x14242 + z14243 = x14243 + z14244 = x14244 + z14245 = x14245 + z14246 = x14246 + z14247 = x14247 + z14248 = x14248 + z14249 = x14249 + z14250 = x14250 + z14251 = x14251 + z14252 = x14252 + z14253 = x14253 + z14254 = x14254 + z14255 = x14255 + z14256 = x14256 + z14257 = x14257 + z14258 = x14258 + z14259 = x14259 + z14260 = x14260 + z14261 = x14261 + z14262 = x14262 + z14263 = x14263 + z14264 = x14264 + z14265 = x14265 + z14266 = x14266 + z14267 = x14267 + z14268 = x14268 + z14269 = x14269 + z14270 = x14270 + z14271 = x14271 + z14272 = x14272 + z14273 = x14273 + z14274 = x14274 + z14275 = x14275 + z14276 = x14276 + z14277 = x14277 + z14278 = x14278 + z14279 = x14279 + z14280 = x14280 + z14281 = x14281 + z14282 = x14282 + z14283 = x14283 + z14284 = x14284 + z14285 = x14285 + z14286 = x14286 + z14287 = x14287 + z14288 = x14288 + z14289 = x14289 + z14290 = x14290 + z14291 = x14291 + z14292 = x14292 + z14293 = x14293 + z14294 = x14294 + z14295 = x14295 + z14296 = x14296 + z14297 = x14297 + z14298 = x14298 + z14299 = x14299 + z14300 = x14300 + z14301 = x14301 + z14302 = x14302 + z14303 = x14303 + z14304 = x14304 + z14305 = x14305 + z14306 = x14306 + z14307 = x14307 + z14308 = x14308 + z14309 = x14309 + z14310 = x14310 + z14311 = x14311 + z14312 = x14312 + z14313 = x14313 + z14314 = x14314 + z14315 = x14315 + z14316 = x14316 + z14317 = x14317 + z14318 = x14318 + z14319 = x14319 + z14320 = x14320 + z14321 = x14321 + z14322 = x14322 + z14323 = x14323 + z14324 = x14324 + z14325 = x14325 + z14326 = x14326 + z14327 = x14327 + z14328 = x14328 + z14329 = x14329 + z14330 = x14330 + z14331 = x14331 + z14332 = x14332 + z14333 = x14333 + z14334 = x14334 + z14335 = x14335 + z14336 = x14336 + z14337 = x14337 + z14338 = x14338 + z14339 = x14339 + z14340 = x14340 + z14341 = x14341 + z14342 = x14342 + z14343 = x14343 + z14344 = x14344 + z14345 = x14345 + z14346 = x14346 + z14347 = x14347 + z14348 = x14348 + z14349 = x14349 + z14350 = x14350 + z14351 = x14351 + z14352 = x14352 + z14353 = x14353 + z14354 = x14354 + z14355 = x14355 + z14356 = x14356 + z14357 = x14357 + z14358 = x14358 + z14359 = x14359 + z14360 = x14360 + z14361 = x14361 + z14362 = x14362 + z14363 = x14363 + z14364 = x14364 + z14365 = x14365 + z14366 = x14366 + z14367 = x14367 + z14368 = x14368 + z14369 = x14369 + z14370 = x14370 + z14371 = x14371 + z14372 = x14372 + z14373 = x14373 + z14374 = x14374 + z14375 = x14375 + z14376 = x14376 + z14377 = x14377 + z14378 = x14378 + z14379 = x14379 + z14380 = x14380 + z14381 = x14381 + z14382 = x14382 + z14383 = x14383 + z14384 = x14384 + z14385 = x14385 + z14386 = x14386 + z14387 = x14387 + z14388 = x14388 + z14389 = x14389 + z14390 = x14390 + z14391 = x14391 + z14392 = x14392 + z14393 = x14393 + z14394 = x14394 + z14395 = x14395 + z14396 = x14396 + z14397 = x14397 + z14398 = x14398 + z14399 = x14399 + z14400 = x14400 + z14401 = x14401 + z14402 = x14402 + z14403 = x14403 + z14404 = x14404 + z14405 = x14405 + z14406 = x14406 + z14407 = x14407 + z14408 = x14408 + z14409 = x14409 + z14410 = x14410 + z14411 = x14411 + z14412 = x14412 + z14413 = x14413 + z14414 = x14414 + z14415 = x14415 + z14416 = x14416 + z14417 = x14417 + z14418 = x14418 + z14419 = x14419 + z14420 = x14420 + z14421 = x14421 + z14422 = x14422 + z14423 = x14423 + z14424 = x14424 + z14425 = x14425 + z14426 = x14426 + z14427 = x14427 + z14428 = x14428 + z14429 = x14429 + z14430 = x14430 + z14431 = x14431 + z14432 = x14432 + z14433 = x14433 + z14434 = x14434 + z14435 = x14435 + z14436 = x14436 + z14437 = x14437 + z14438 = x14438 + z14439 = x14439 + z14440 = x14440 + z14441 = x14441 + z14442 = x14442 + z14443 = x14443 + z14444 = x14444 + z14445 = x14445 + z14446 = x14446 + z14447 = x14447 + z14448 = x14448 + z14449 = x14449 + z14450 = x14450 + z14451 = x14451 + z14452 = x14452 + z14453 = x14453 + z14454 = x14454 + z14455 = x14455 + z14456 = x14456 + z14457 = x14457 + z14458 = x14458 + z14459 = x14459 + z14460 = x14460 + z14461 = x14461 + z14462 = x14462 + z14463 = x14463 + z14464 = x14464 + z14465 = x14465 + z14466 = x14466 + z14467 = x14467 + z14468 = x14468 + z14469 = x14469 + z14470 = x14470 + z14471 = x14471 + z14472 = x14472 + z14473 = x14473 + z14474 = x14474 + z14475 = x14475 + z14476 = x14476 + z14477 = x14477 + z14478 = x14478 + z14479 = x14479 + z14480 = x14480 + z14481 = x14481 + z14482 = x14482 + z14483 = x14483 + z14484 = x14484 + z14485 = x14485 + z14486 = x14486 + z14487 = x14487 + z14488 = x14488 + z14489 = x14489 + z14490 = x14490 + z14491 = x14491 + z14492 = x14492 + z14493 = x14493 + z14494 = x14494 + z14495 = x14495 + z14496 = x14496 + z14497 = x14497 + z14498 = x14498 + z14499 = x14499 + z14500 = x14500 + z14501 = x14501 + z14502 = x14502 + z14503 = x14503 + z14504 = x14504 + z14505 = x14505 + z14506 = x14506 + z14507 = x14507 + z14508 = x14508 + z14509 = x14509 + z14510 = x14510 + z14511 = x14511 + z14512 = x14512 + z14513 = x14513 + z14514 = x14514 + z14515 = x14515 + z14516 = x14516 + z14517 = x14517 + z14518 = x14518 + z14519 = x14519 + z14520 = x14520 + z14521 = x14521 + z14522 = x14522 + z14523 = x14523 + z14524 = x14524 + z14525 = x14525 + z14526 = x14526 + z14527 = x14527 + z14528 = x14528 + z14529 = x14529 + z14530 = x14530 + z14531 = x14531 + z14532 = x14532 + z14533 = x14533 + z14534 = x14534 + z14535 = x14535 + z14536 = x14536 + z14537 = x14537 + z14538 = x14538 + z14539 = x14539 + z14540 = x14540 + z14541 = x14541 + z14542 = x14542 + z14543 = x14543 + z14544 = x14544 + z14545 = x14545 + z14546 = x14546 + z14547 = x14547 + z14548 = x14548 + z14549 = x14549 + z14550 = x14550 + z14551 = x14551 + z14552 = x14552 + z14553 = x14553 + z14554 = x14554 + z14555 = x14555 + z14556 = x14556 + z14557 = x14557 + z14558 = x14558 + z14559 = x14559 + z14560 = x14560 + z14561 = x14561 + z14562 = x14562 + z14563 = x14563 + z14564 = x14564 + z14565 = x14565 + z14566 = x14566 + z14567 = x14567 + z14568 = x14568 + z14569 = x14569 + z14570 = x14570 + z14571 = x14571 + z14572 = x14572 + z14573 = x14573 + z14574 = x14574 + z14575 = x14575 + z14576 = x14576 + z14577 = x14577 + z14578 = x14578 + z14579 = x14579 + z14580 = x14580 + z14581 = x14581 + z14582 = x14582 + z14583 = x14583 + z14584 = x14584 + z14585 = x14585 + z14586 = x14586 + z14587 = x14587 + z14588 = x14588 + z14589 = x14589 + z14590 = x14590 + z14591 = x14591 + z14592 = x14592 + z14593 = x14593 + z14594 = x14594 + z14595 = x14595 + z14596 = x14596 + z14597 = x14597 + z14598 = x14598 + z14599 = x14599 + z14600 = x14600 + z14601 = x14601 + z14602 = x14602 + z14603 = x14603 + z14604 = x14604 + z14605 = x14605 + z14606 = x14606 + z14607 = x14607 + z14608 = x14608 + z14609 = x14609 + z14610 = x14610 + z14611 = x14611 + z14612 = x14612 + z14613 = x14613 + z14614 = x14614 + z14615 = x14615 + z14616 = x14616 + z14617 = x14617 + z14618 = x14618 + z14619 = x14619 + z14620 = x14620 + z14621 = x14621 + z14622 = x14622 + z14623 = x14623 + z14624 = x14624 + z14625 = x14625 + z14626 = x14626 + z14627 = x14627 + z14628 = x14628 + z14629 = x14629 + z14630 = x14630 + z14631 = x14631 + z14632 = x14632 + z14633 = x14633 + z14634 = x14634 + z14635 = x14635 + z14636 = x14636 + z14637 = x14637 + z14638 = x14638 + z14639 = x14639 + z14640 = x14640 + z14641 = x14641 + z14642 = x14642 + z14643 = x14643 + z14644 = x14644 + z14645 = x14645 + z14646 = x14646 + z14647 = x14647 + z14648 = x14648 + z14649 = x14649 + z14650 = x14650 + z14651 = x14651 + z14652 = x14652 + z14653 = x14653 + z14654 = x14654 + z14655 = x14655 + z14656 = x14656 + z14657 = x14657 + z14658 = x14658 + z14659 = x14659 + z14660 = x14660 + z14661 = x14661 + z14662 = x14662 + z14663 = x14663 + z14664 = x14664 + z14665 = x14665 + z14666 = x14666 + z14667 = x14667 + z14668 = x14668 + z14669 = x14669 + z14670 = x14670 + z14671 = x14671 + z14672 = x14672 + z14673 = x14673 + z14674 = x14674 + z14675 = x14675 + z14676 = x14676 + z14677 = x14677 + z14678 = x14678 + z14679 = x14679 + z14680 = x14680 + z14681 = x14681 + z14682 = x14682 + z14683 = x14683 + z14684 = x14684 + z14685 = x14685 + z14686 = x14686 + z14687 = x14687 + z14688 = x14688 + z14689 = x14689 + z14690 = x14690 + z14691 = x14691 + z14692 = x14692 + z14693 = x14693 + z14694 = x14694 + z14695 = x14695 + z14696 = x14696 + z14697 = x14697 + z14698 = x14698 + z14699 = x14699 + z14700 = x14700 + z14701 = x14701 + z14702 = x14702 + z14703 = x14703 + z14704 = x14704 + z14705 = x14705 + z14706 = x14706 + z14707 = x14707 + z14708 = x14708 + z14709 = x14709 + z14710 = x14710 + z14711 = x14711 + z14712 = x14712 + z14713 = x14713 + z14714 = x14714 + z14715 = x14715 + z14716 = x14716 + z14717 = x14717 + z14718 = x14718 + z14719 = x14719 + z14720 = x14720 + z14721 = x14721 + z14722 = x14722 + z14723 = x14723 + z14724 = x14724 + z14725 = x14725 + z14726 = x14726 + z14727 = x14727 + z14728 = x14728 + z14729 = x14729 + z14730 = x14730 + z14731 = x14731 + z14732 = x14732 + z14733 = x14733 + z14734 = x14734 + z14735 = x14735 + z14736 = x14736 + z14737 = x14737 + z14738 = x14738 + z14739 = x14739 + z14740 = x14740 + z14741 = x14741 + z14742 = x14742 + z14743 = x14743 + z14744 = x14744 + z14745 = x14745 + z14746 = x14746 + z14747 = x14747 + z14748 = x14748 + z14749 = x14749 + z14750 = x14750 + z14751 = x14751 + z14752 = x14752 + z14753 = x14753 + z14754 = x14754 + z14755 = x14755 + z14756 = x14756 + z14757 = x14757 + z14758 = x14758 + z14759 = x14759 + z14760 = x14760 + z14761 = x14761 + z14762 = x14762 + z14763 = x14763 + z14764 = x14764 + z14765 = x14765 + z14766 = x14766 + z14767 = x14767 + z14768 = x14768 + z14769 = x14769 + z14770 = x14770 + z14771 = x14771 + z14772 = x14772 + z14773 = x14773 + z14774 = x14774 + z14775 = x14775 + z14776 = x14776 + z14777 = x14777 + z14778 = x14778 + z14779 = x14779 + z14780 = x14780 + z14781 = x14781 + z14782 = x14782 + z14783 = x14783 + z14784 = x14784 + z14785 = x14785 + z14786 = x14786 + z14787 = x14787 + z14788 = x14788 + z14789 = x14789 + z14790 = x14790 + z14791 = x14791 + z14792 = x14792 + z14793 = x14793 + z14794 = x14794 + z14795 = x14795 + z14796 = x14796 + z14797 = x14797 + z14798 = x14798 + z14799 = x14799 + z14800 = x14800 + z14801 = x14801 + z14802 = x14802 + z14803 = x14803 + z14804 = x14804 + z14805 = x14805 + z14806 = x14806 + z14807 = x14807 + z14808 = x14808 + z14809 = x14809 + z14810 = x14810 + z14811 = x14811 + z14812 = x14812 + z14813 = x14813 + z14814 = x14814 + z14815 = x14815 + z14816 = x14816 + z14817 = x14817 + z14818 = x14818 + z14819 = x14819 + z14820 = x14820 + z14821 = x14821 + z14822 = x14822 + z14823 = x14823 + z14824 = x14824 + z14825 = x14825 + z14826 = x14826 + z14827 = x14827 + z14828 = x14828 + z14829 = x14829 + z14830 = x14830 + z14831 = x14831 + z14832 = x14832 + z14833 = x14833 + z14834 = x14834 + z14835 = x14835 + z14836 = x14836 + z14837 = x14837 + z14838 = x14838 + z14839 = x14839 + z14840 = x14840 + z14841 = x14841 + z14842 = x14842 + z14843 = x14843 + z14844 = x14844 + z14845 = x14845 + z14846 = x14846 + z14847 = x14847 + z14848 = x14848 + z14849 = x14849 + z14850 = x14850 + z14851 = x14851 + z14852 = x14852 + z14853 = x14853 + z14854 = x14854 + z14855 = x14855 + z14856 = x14856 + z14857 = x14857 + z14858 = x14858 + z14859 = x14859 + z14860 = x14860 + z14861 = x14861 + z14862 = x14862 + z14863 = x14863 + z14864 = x14864 + z14865 = x14865 + z14866 = x14866 + z14867 = x14867 + z14868 = x14868 + z14869 = x14869 + z14870 = x14870 + z14871 = x14871 + z14872 = x14872 + z14873 = x14873 + z14874 = x14874 + z14875 = x14875 + z14876 = x14876 + z14877 = x14877 + z14878 = x14878 + z14879 = x14879 + z14880 = x14880 + z14881 = x14881 + z14882 = x14882 + z14883 = x14883 + z14884 = x14884 + z14885 = x14885 + z14886 = x14886 + z14887 = x14887 + z14888 = x14888 + z14889 = x14889 + z14890 = x14890 + z14891 = x14891 + z14892 = x14892 + z14893 = x14893 + z14894 = x14894 + z14895 = x14895 + z14896 = x14896 + z14897 = x14897 + z14898 = x14898 + z14899 = x14899 + z14900 = x14900 + z14901 = x14901 + z14902 = x14902 + z14903 = x14903 + z14904 = x14904 + z14905 = x14905 + z14906 = x14906 + z14907 = x14907 + z14908 = x14908 + z14909 = x14909 + z14910 = x14910 + z14911 = x14911 + z14912 = x14912 + z14913 = x14913 + z14914 = x14914 + z14915 = x14915 + z14916 = x14916 + z14917 = x14917 + z14918 = x14918 + z14919 = x14919 + z14920 = x14920 + z14921 = x14921 + z14922 = x14922 + z14923 = x14923 + z14924 = x14924 + z14925 = x14925 + z14926 = x14926 + z14927 = x14927 + z14928 = x14928 + z14929 = x14929 + z14930 = x14930 + z14931 = x14931 + z14932 = x14932 + z14933 = x14933 + z14934 = x14934 + z14935 = x14935 + z14936 = x14936 + z14937 = x14937 + z14938 = x14938 + z14939 = x14939 + z14940 = x14940 + z14941 = x14941 + z14942 = x14942 + z14943 = x14943 + z14944 = x14944 + z14945 = x14945 + z14946 = x14946 + z14947 = x14947 + z14948 = x14948 + z14949 = x14949 + z14950 = x14950 + z14951 = x14951 + z14952 = x14952 + z14953 = x14953 + z14954 = x14954 + z14955 = x14955 + z14956 = x14956 + z14957 = x14957 + z14958 = x14958 + z14959 = x14959 + z14960 = x14960 + z14961 = x14961 + z14962 = x14962 + z14963 = x14963 + z14964 = x14964 + z14965 = x14965 + z14966 = x14966 + z14967 = x14967 + z14968 = x14968 + z14969 = x14969 + z14970 = x14970 + z14971 = x14971 + z14972 = x14972 + z14973 = x14973 + z14974 = x14974 + z14975 = x14975 + z14976 = x14976 + z14977 = x14977 + z14978 = x14978 + z14979 = x14979 + z14980 = x14980 + z14981 = x14981 + z14982 = x14982 + z14983 = x14983 + z14984 = x14984 + z14985 = x14985 + z14986 = x14986 + z14987 = x14987 + z14988 = x14988 + z14989 = x14989 + z14990 = x14990 + z14991 = x14991 + z14992 = x14992 + z14993 = x14993 + z14994 = x14994 + z14995 = x14995 + z14996 = x14996 + z14997 = x14997 + z14998 = x14998 + z14999 = x14999 + z15000 = x15000 + z15001 = x15001 + z15002 = x15002 + z15003 = x15003 + z15004 = x15004 + z15005 = x15005 + z15006 = x15006 + z15007 = x15007 + z15008 = x15008 + z15009 = x15009 + z15010 = x15010 + z15011 = x15011 + z15012 = x15012 + z15013 = x15013 + z15014 = x15014 + z15015 = x15015 + z15016 = x15016 + z15017 = x15017 + z15018 = x15018 + z15019 = x15019 + z15020 = x15020 + z15021 = x15021 + z15022 = x15022 + z15023 = x15023 + z15024 = x15024 + z15025 = x15025 + z15026 = x15026 + z15027 = x15027 + z15028 = x15028 + z15029 = x15029 + z15030 = x15030 + z15031 = x15031 + z15032 = x15032 + z15033 = x15033 + z15034 = x15034 + z15035 = x15035 + z15036 = x15036 + z15037 = x15037 + z15038 = x15038 + z15039 = x15039 + z15040 = x15040 + z15041 = x15041 + z15042 = x15042 + z15043 = x15043 + z15044 = x15044 + z15045 = x15045 + z15046 = x15046 + z15047 = x15047 + z15048 = x15048 + z15049 = x15049 + z15050 = x15050 + z15051 = x15051 + z15052 = x15052 + z15053 = x15053 + z15054 = x15054 + z15055 = x15055 + z15056 = x15056 + z15057 = x15057 + z15058 = x15058 + z15059 = x15059 + z15060 = x15060 + z15061 = x15061 + z15062 = x15062 + z15063 = x15063 + z15064 = x15064 + z15065 = x15065 + z15066 = x15066 + z15067 = x15067 + z15068 = x15068 + z15069 = x15069 + z15070 = x15070 + z15071 = x15071 + z15072 = x15072 + z15073 = x15073 + z15074 = x15074 + z15075 = x15075 + z15076 = x15076 + z15077 = x15077 + z15078 = x15078 + z15079 = x15079 + z15080 = x15080 + z15081 = x15081 + z15082 = x15082 + z15083 = x15083 + z15084 = x15084 + z15085 = x15085 + z15086 = x15086 + z15087 = x15087 + z15088 = x15088 + z15089 = x15089 + z15090 = x15090 + z15091 = x15091 + z15092 = x15092 + z15093 = x15093 + z15094 = x15094 + z15095 = x15095 + z15096 = x15096 + z15097 = x15097 + z15098 = x15098 + z15099 = x15099 + z15100 = x15100 + z15101 = x15101 + z15102 = x15102 + z15103 = x15103 + z15104 = x15104 + z15105 = x15105 + z15106 = x15106 + z15107 = x15107 + z15108 = x15108 + z15109 = x15109 + z15110 = x15110 + z15111 = x15111 + z15112 = x15112 + z15113 = x15113 + z15114 = x15114 + z15115 = x15115 + z15116 = x15116 + z15117 = x15117 + z15118 = x15118 + z15119 = x15119 + z15120 = x15120 + z15121 = x15121 + z15122 = x15122 + z15123 = x15123 + z15124 = x15124 + z15125 = x15125 + z15126 = x15126 + z15127 = x15127 + z15128 = x15128 + z15129 = x15129 + z15130 = x15130 + z15131 = x15131 + z15132 = x15132 + z15133 = x15133 + z15134 = x15134 + z15135 = x15135 + z15136 = x15136 + z15137 = x15137 + z15138 = x15138 + z15139 = x15139 + z15140 = x15140 + z15141 = x15141 + z15142 = x15142 + z15143 = x15143 + z15144 = x15144 + z15145 = x15145 + z15146 = x15146 + z15147 = x15147 + z15148 = x15148 + z15149 = x15149 + z15150 = x15150 + z15151 = x15151 + z15152 = x15152 + z15153 = x15153 + z15154 = x15154 + z15155 = x15155 + z15156 = x15156 + z15157 = x15157 + z15158 = x15158 + z15159 = x15159 + z15160 = x15160 + z15161 = x15161 + z15162 = x15162 + z15163 = x15163 + z15164 = x15164 + z15165 = x15165 + z15166 = x15166 + z15167 = x15167 + z15168 = x15168 + z15169 = x15169 + z15170 = x15170 + z15171 = x15171 + z15172 = x15172 + z15173 = x15173 + z15174 = x15174 + z15175 = x15175 + z15176 = x15176 + z15177 = x15177 + z15178 = x15178 + z15179 = x15179 + z15180 = x15180 + z15181 = x15181 + z15182 = x15182 + z15183 = x15183 + z15184 = x15184 + z15185 = x15185 + z15186 = x15186 + z15187 = x15187 + z15188 = x15188 + z15189 = x15189 + z15190 = x15190 + z15191 = x15191 + z15192 = x15192 + z15193 = x15193 + z15194 = x15194 + z15195 = x15195 + z15196 = x15196 + z15197 = x15197 + z15198 = x15198 + z15199 = x15199 + z15200 = x15200 + z15201 = x15201 + z15202 = x15202 + z15203 = x15203 + z15204 = x15204 + z15205 = x15205 + z15206 = x15206 + z15207 = x15207 + z15208 = x15208 + z15209 = x15209 + z15210 = x15210 + z15211 = x15211 + z15212 = x15212 + z15213 = x15213 + z15214 = x15214 + z15215 = x15215 + z15216 = x15216 + z15217 = x15217 + z15218 = x15218 + z15219 = x15219 + z15220 = x15220 + z15221 = x15221 + z15222 = x15222 + z15223 = x15223 + z15224 = x15224 + z15225 = x15225 + z15226 = x15226 + z15227 = x15227 + z15228 = x15228 + z15229 = x15229 + z15230 = x15230 + z15231 = x15231 + z15232 = x15232 + z15233 = x15233 + z15234 = x15234 + z15235 = x15235 + z15236 = x15236 + z15237 = x15237 + z15238 = x15238 + z15239 = x15239 + z15240 = x15240 + z15241 = x15241 + z15242 = x15242 + z15243 = x15243 + z15244 = x15244 + z15245 = x15245 + z15246 = x15246 + z15247 = x15247 + z15248 = x15248 + z15249 = x15249 + z15250 = x15250 + z15251 = x15251 + z15252 = x15252 + z15253 = x15253 + z15254 = x15254 + z15255 = x15255 + z15256 = x15256 + z15257 = x15257 + z15258 = x15258 + z15259 = x15259 + z15260 = x15260 + z15261 = x15261 + z15262 = x15262 + z15263 = x15263 + z15264 = x15264 + z15265 = x15265 + z15266 = x15266 + z15267 = x15267 + z15268 = x15268 + z15269 = x15269 + z15270 = x15270 + z15271 = x15271 + z15272 = x15272 + z15273 = x15273 + z15274 = x15274 + z15275 = x15275 + z15276 = x15276 + z15277 = x15277 + z15278 = x15278 + z15279 = x15279 + z15280 = x15280 + z15281 = x15281 + z15282 = x15282 + z15283 = x15283 + z15284 = x15284 + z15285 = x15285 + z15286 = x15286 + z15287 = x15287 + z15288 = x15288 + z15289 = x15289 + z15290 = x15290 + z15291 = x15291 + z15292 = x15292 + z15293 = x15293 + z15294 = x15294 + z15295 = x15295 + z15296 = x15296 + z15297 = x15297 + z15298 = x15298 + z15299 = x15299 + z15300 = x15300 + z15301 = x15301 + z15302 = x15302 + z15303 = x15303 + z15304 = x15304 + z15305 = x15305 + z15306 = x15306 + z15307 = x15307 + z15308 = x15308 + z15309 = x15309 + z15310 = x15310 + z15311 = x15311 + z15312 = x15312 + z15313 = x15313 + z15314 = x15314 + z15315 = x15315 + z15316 = x15316 + z15317 = x15317 + z15318 = x15318 + z15319 = x15319 + z15320 = x15320 + z15321 = x15321 + z15322 = x15322 + z15323 = x15323 + z15324 = x15324 + z15325 = x15325 + z15326 = x15326 + z15327 = x15327 + z15328 = x15328 + z15329 = x15329 + z15330 = x15330 + z15331 = x15331 + z15332 = x15332 + z15333 = x15333 + z15334 = x15334 + z15335 = x15335 + z15336 = x15336 + z15337 = x15337 + z15338 = x15338 + z15339 = x15339 + z15340 = x15340 + z15341 = x15341 + z15342 = x15342 + z15343 = x15343 + z15344 = x15344 + z15345 = x15345 + z15346 = x15346 + z15347 = x15347 + z15348 = x15348 + z15349 = x15349 + z15350 = x15350 + z15351 = x15351 + z15352 = x15352 + z15353 = x15353 + z15354 = x15354 + z15355 = x15355 + z15356 = x15356 + z15357 = x15357 + z15358 = x15358 + z15359 = x15359 + z15360 = x15360 + z15361 = x15361 + z15362 = x15362 + z15363 = x15363 + z15364 = x15364 + z15365 = x15365 + z15366 = x15366 + z15367 = x15367 + z15368 = x15368 + z15369 = x15369 + z15370 = x15370 + z15371 = x15371 + z15372 = x15372 + z15373 = x15373 + z15374 = x15374 + z15375 = x15375 + z15376 = x15376 + z15377 = x15377 + z15378 = x15378 + z15379 = x15379 + z15380 = x15380 + z15381 = x15381 + z15382 = x15382 + z15383 = x15383 + z15384 = x15384 + z15385 = x15385 + z15386 = x15386 + z15387 = x15387 + z15388 = x15388 + z15389 = x15389 + z15390 = x15390 + z15391 = x15391 + z15392 = x15392 + z15393 = x15393 + z15394 = x15394 + z15395 = x15395 + z15396 = x15396 + z15397 = x15397 + z15398 = x15398 + z15399 = x15399 + z15400 = x15400 + z15401 = x15401 + z15402 = x15402 + z15403 = x15403 + z15404 = x15404 + z15405 = x15405 + z15406 = x15406 + z15407 = x15407 + z15408 = x15408 + z15409 = x15409 + z15410 = x15410 + z15411 = x15411 + z15412 = x15412 + z15413 = x15413 + z15414 = x15414 + z15415 = x15415 + z15416 = x15416 + z15417 = x15417 + z15418 = x15418 + z15419 = x15419 + z15420 = x15420 + z15421 = x15421 + z15422 = x15422 + z15423 = x15423 + z15424 = x15424 + z15425 = x15425 + z15426 = x15426 + z15427 = x15427 + z15428 = x15428 + z15429 = x15429 + z15430 = x15430 + z15431 = x15431 + z15432 = x15432 + z15433 = x15433 + z15434 = x15434 + z15435 = x15435 + z15436 = x15436 + z15437 = x15437 + z15438 = x15438 + z15439 = x15439 + z15440 = x15440 + z15441 = x15441 + z15442 = x15442 + z15443 = x15443 + z15444 = x15444 + z15445 = x15445 + z15446 = x15446 + z15447 = x15447 + z15448 = x15448 + z15449 = x15449 + z15450 = x15450 + z15451 = x15451 + z15452 = x15452 + z15453 = x15453 + z15454 = x15454 + z15455 = x15455 + z15456 = x15456 + z15457 = x15457 + z15458 = x15458 + z15459 = x15459 + z15460 = x15460 + z15461 = x15461 + z15462 = x15462 + z15463 = x15463 + z15464 = x15464 + z15465 = x15465 + z15466 = x15466 + z15467 = x15467 + z15468 = x15468 + z15469 = x15469 + z15470 = x15470 + z15471 = x15471 + z15472 = x15472 + z15473 = x15473 + z15474 = x15474 + z15475 = x15475 + z15476 = x15476 + z15477 = x15477 + z15478 = x15478 + z15479 = x15479 + z15480 = x15480 + z15481 = x15481 + z15482 = x15482 + z15483 = x15483 + z15484 = x15484 + z15485 = x15485 + z15486 = x15486 + z15487 = x15487 + z15488 = x15488 + z15489 = x15489 + z15490 = x15490 + z15491 = x15491 + z15492 = x15492 + z15493 = x15493 + z15494 = x15494 + z15495 = x15495 + z15496 = x15496 + z15497 = x15497 + z15498 = x15498 + z15499 = x15499 + z15500 = x15500 + z15501 = x15501 + z15502 = x15502 + z15503 = x15503 + z15504 = x15504 + z15505 = x15505 + z15506 = x15506 + z15507 = x15507 + z15508 = x15508 + z15509 = x15509 + z15510 = x15510 + z15511 = x15511 + z15512 = x15512 + z15513 = x15513 + z15514 = x15514 + z15515 = x15515 + z15516 = x15516 + z15517 = x15517 + z15518 = x15518 + z15519 = x15519 + z15520 = x15520 + z15521 = x15521 + z15522 = x15522 + z15523 = x15523 + z15524 = x15524 + z15525 = x15525 + z15526 = x15526 + z15527 = x15527 + z15528 = x15528 + z15529 = x15529 + z15530 = x15530 + z15531 = x15531 + z15532 = x15532 + z15533 = x15533 + z15534 = x15534 + z15535 = x15535 + z15536 = x15536 + z15537 = x15537 + z15538 = x15538 + z15539 = x15539 + z15540 = x15540 + z15541 = x15541 + z15542 = x15542 + z15543 = x15543 + z15544 = x15544 + z15545 = x15545 + z15546 = x15546 + z15547 = x15547 + z15548 = x15548 + z15549 = x15549 + z15550 = x15550 + z15551 = x15551 + z15552 = x15552 + z15553 = x15553 + z15554 = x15554 + z15555 = x15555 + z15556 = x15556 + z15557 = x15557 + z15558 = x15558 + z15559 = x15559 + z15560 = x15560 + z15561 = x15561 + z15562 = x15562 + z15563 = x15563 + z15564 = x15564 + z15565 = x15565 + z15566 = x15566 + z15567 = x15567 + z15568 = x15568 + z15569 = x15569 + z15570 = x15570 + z15571 = x15571 + z15572 = x15572 + z15573 = x15573 + z15574 = x15574 + z15575 = x15575 + z15576 = x15576 + z15577 = x15577 + z15578 = x15578 + z15579 = x15579 + z15580 = x15580 + z15581 = x15581 + z15582 = x15582 + z15583 = x15583 + z15584 = x15584 + z15585 = x15585 + z15586 = x15586 + z15587 = x15587 + z15588 = x15588 + z15589 = x15589 + z15590 = x15590 + z15591 = x15591 + z15592 = x15592 + z15593 = x15593 + z15594 = x15594 + z15595 = x15595 + z15596 = x15596 + z15597 = x15597 + z15598 = x15598 + z15599 = x15599 + z15600 = x15600 + z15601 = x15601 + z15602 = x15602 + z15603 = x15603 + z15604 = x15604 + z15605 = x15605 + z15606 = x15606 + z15607 = x15607 + z15608 = x15608 + z15609 = x15609 + z15610 = x15610 + z15611 = x15611 + z15612 = x15612 + z15613 = x15613 + z15614 = x15614 + z15615 = x15615 + z15616 = x15616 + z15617 = x15617 + z15618 = x15618 + z15619 = x15619 + z15620 = x15620 + z15621 = x15621 + z15622 = x15622 + z15623 = x15623 + z15624 = x15624 + z15625 = x15625 + z15626 = x15626 + z15627 = x15627 + z15628 = x15628 + z15629 = x15629 + z15630 = x15630 + z15631 = x15631 + z15632 = x15632 + z15633 = x15633 + z15634 = x15634 + z15635 = x15635 + z15636 = x15636 + z15637 = x15637 + z15638 = x15638 + z15639 = x15639 + z15640 = x15640 + z15641 = x15641 + z15642 = x15642 + z15643 = x15643 + z15644 = x15644 + z15645 = x15645 + z15646 = x15646 + z15647 = x15647 + z15648 = x15648 + z15649 = x15649 + z15650 = x15650 + z15651 = x15651 + z15652 = x15652 + z15653 = x15653 + z15654 = x15654 + z15655 = x15655 + z15656 = x15656 + z15657 = x15657 + z15658 = x15658 + z15659 = x15659 + z15660 = x15660 + z15661 = x15661 + z15662 = x15662 + z15663 = x15663 + z15664 = x15664 + z15665 = x15665 + z15666 = x15666 + z15667 = x15667 + z15668 = x15668 + z15669 = x15669 + z15670 = x15670 + z15671 = x15671 + z15672 = x15672 + z15673 = x15673 + z15674 = x15674 + z15675 = x15675 + z15676 = x15676 + z15677 = x15677 + z15678 = x15678 + z15679 = x15679 + z15680 = x15680 + z15681 = x15681 + z15682 = x15682 + z15683 = x15683 + z15684 = x15684 + z15685 = x15685 + z15686 = x15686 + z15687 = x15687 + z15688 = x15688 + z15689 = x15689 + z15690 = x15690 + z15691 = x15691 + z15692 = x15692 + z15693 = x15693 + z15694 = x15694 + z15695 = x15695 + z15696 = x15696 + z15697 = x15697 + z15698 = x15698 + z15699 = x15699 + z15700 = x15700 + z15701 = x15701 + z15702 = x15702 + z15703 = x15703 + z15704 = x15704 + z15705 = x15705 + z15706 = x15706 + z15707 = x15707 + z15708 = x15708 + z15709 = x15709 + z15710 = x15710 + z15711 = x15711 + z15712 = x15712 + z15713 = x15713 + z15714 = x15714 + z15715 = x15715 + z15716 = x15716 + z15717 = x15717 + z15718 = x15718 + z15719 = x15719 + z15720 = x15720 + z15721 = x15721 + z15722 = x15722 + z15723 = x15723 + z15724 = x15724 + z15725 = x15725 + z15726 = x15726 + z15727 = x15727 + z15728 = x15728 + z15729 = x15729 + z15730 = x15730 + z15731 = x15731 + z15732 = x15732 + z15733 = x15733 + z15734 = x15734 + z15735 = x15735 + z15736 = x15736 + z15737 = x15737 + z15738 = x15738 + z15739 = x15739 + z15740 = x15740 + z15741 = x15741 + z15742 = x15742 + z15743 = x15743 + z15744 = x15744 + z15745 = x15745 + z15746 = x15746 + z15747 = x15747 + z15748 = x15748 + z15749 = x15749 + z15750 = x15750 + z15751 = x15751 + z15752 = x15752 + z15753 = x15753 + z15754 = x15754 + z15755 = x15755 + z15756 = x15756 + z15757 = x15757 + z15758 = x15758 + z15759 = x15759 + z15760 = x15760 + z15761 = x15761 + z15762 = x15762 + z15763 = x15763 + z15764 = x15764 + z15765 = x15765 + z15766 = x15766 + z15767 = x15767 + z15768 = x15768 + z15769 = x15769 + z15770 = x15770 + z15771 = x15771 + z15772 = x15772 + z15773 = x15773 + z15774 = x15774 + z15775 = x15775 + z15776 = x15776 + z15777 = x15777 + z15778 = x15778 + z15779 = x15779 + z15780 = x15780 + z15781 = x15781 + z15782 = x15782 + z15783 = x15783 + z15784 = x15784 + z15785 = x15785 + z15786 = x15786 + z15787 = x15787 + z15788 = x15788 + z15789 = x15789 + z15790 = x15790 + z15791 = x15791 + z15792 = x15792 + z15793 = x15793 + z15794 = x15794 + z15795 = x15795 + z15796 = x15796 + z15797 = x15797 + z15798 = x15798 + z15799 = x15799 + z15800 = x15800 + z15801 = x15801 + z15802 = x15802 + z15803 = x15803 + z15804 = x15804 + z15805 = x15805 + z15806 = x15806 + z15807 = x15807 + z15808 = x15808 + z15809 = x15809 + z15810 = x15810 + z15811 = x15811 + z15812 = x15812 + z15813 = x15813 + z15814 = x15814 + z15815 = x15815 + z15816 = x15816 + z15817 = x15817 + z15818 = x15818 + z15819 = x15819 + z15820 = x15820 + z15821 = x15821 + z15822 = x15822 + z15823 = x15823 + z15824 = x15824 + z15825 = x15825 + z15826 = x15826 + z15827 = x15827 + z15828 = x15828 + z15829 = x15829 + z15830 = x15830 + z15831 = x15831 + z15832 = x15832 + z15833 = x15833 + z15834 = x15834 + z15835 = x15835 + z15836 = x15836 + z15837 = x15837 + z15838 = x15838 + z15839 = x15839 + z15840 = x15840 + z15841 = x15841 + z15842 = x15842 + z15843 = x15843 + z15844 = x15844 + z15845 = x15845 + z15846 = x15846 + z15847 = x15847 + z15848 = x15848 + z15849 = x15849 + z15850 = x15850 + z15851 = x15851 + z15852 = x15852 + z15853 = x15853 + z15854 = x15854 + z15855 = x15855 + z15856 = x15856 + z15857 = x15857 + z15858 = x15858 + z15859 = x15859 + z15860 = x15860 + z15861 = x15861 + z15862 = x15862 + z15863 = x15863 + z15864 = x15864 + z15865 = x15865 + z15866 = x15866 + z15867 = x15867 + z15868 = x15868 + z15869 = x15869 + z15870 = x15870 + z15871 = x15871 + z15872 = x15872 + z15873 = x15873 + z15874 = x15874 + z15875 = x15875 + z15876 = x15876 + z15877 = x15877 + z15878 = x15878 + z15879 = x15879 + z15880 = x15880 + z15881 = x15881 + z15882 = x15882 + z15883 = x15883 + z15884 = x15884 + z15885 = x15885 + z15886 = x15886 + z15887 = x15887 + z15888 = x15888 + z15889 = x15889 + z15890 = x15890 + z15891 = x15891 + z15892 = x15892 + z15893 = x15893 + z15894 = x15894 + z15895 = x15895 + z15896 = x15896 + z15897 = x15897 + z15898 = x15898 + z15899 = x15899 + z15900 = x15900 + z15901 = x15901 + z15902 = x15902 + z15903 = x15903 + z15904 = x15904 + z15905 = x15905 + z15906 = x15906 + z15907 = x15907 + z15908 = x15908 + z15909 = x15909 + z15910 = x15910 + z15911 = x15911 + z15912 = x15912 + z15913 = x15913 + z15914 = x15914 + z15915 = x15915 + z15916 = x15916 + z15917 = x15917 + z15918 = x15918 + z15919 = x15919 + z15920 = x15920 + z15921 = x15921 + z15922 = x15922 + z15923 = x15923 + z15924 = x15924 + z15925 = x15925 + z15926 = x15926 + z15927 = x15927 + z15928 = x15928 + z15929 = x15929 + z15930 = x15930 + z15931 = x15931 + z15932 = x15932 + z15933 = x15933 + z15934 = x15934 + z15935 = x15935 + z15936 = x15936 + z15937 = x15937 + z15938 = x15938 + z15939 = x15939 + z15940 = x15940 + z15941 = x15941 + z15942 = x15942 + z15943 = x15943 + z15944 = x15944 + z15945 = x15945 + z15946 = x15946 + z15947 = x15947 + z15948 = x15948 + z15949 = x15949 + z15950 = x15950 + z15951 = x15951 + z15952 = x15952 + z15953 = x15953 + z15954 = x15954 + z15955 = x15955 + z15956 = x15956 + z15957 = x15957 + z15958 = x15958 + z15959 = x15959 + z15960 = x15960 + z15961 = x15961 + z15962 = x15962 + z15963 = x15963 + z15964 = x15964 + z15965 = x15965 + z15966 = x15966 + z15967 = x15967 + z15968 = x15968 + z15969 = x15969 + z15970 = x15970 + z15971 = x15971 + z15972 = x15972 + z15973 = x15973 + z15974 = x15974 + z15975 = x15975 + z15976 = x15976 + z15977 = x15977 + z15978 = x15978 + z15979 = x15979 + z15980 = x15980 + z15981 = x15981 + z15982 = x15982 + z15983 = x15983 + z15984 = x15984 + z15985 = x15985 + z15986 = x15986 + z15987 = x15987 + z15988 = x15988 + z15989 = x15989 + z15990 = x15990 + z15991 = x15991 + z15992 = x15992 + z15993 = x15993 + z15994 = x15994 + z15995 = x15995 + z15996 = x15996 + z15997 = x15997 + z15998 = x15998 + z15999 = x15999 + z16000 = x16000 + z16001 = x16001 + z16002 = x16002 + z16003 = x16003 + z16004 = x16004 + z16005 = x16005 + z16006 = x16006 + z16007 = x16007 + z16008 = x16008 + z16009 = x16009 + z16010 = x16010 + z16011 = x16011 + z16012 = x16012 + z16013 = x16013 + z16014 = x16014 + z16015 = x16015 + z16016 = x16016 + z16017 = x16017 + z16018 = x16018 + z16019 = x16019 + z16020 = x16020 + z16021 = x16021 + z16022 = x16022 + z16023 = x16023 + z16024 = x16024 + z16025 = x16025 + z16026 = x16026 + z16027 = x16027 + z16028 = x16028 + z16029 = x16029 + z16030 = x16030 + z16031 = x16031 + z16032 = x16032 + z16033 = x16033 + z16034 = x16034 + z16035 = x16035 + z16036 = x16036 + z16037 = x16037 + z16038 = x16038 + z16039 = x16039 + z16040 = x16040 + z16041 = x16041 + z16042 = x16042 + z16043 = x16043 + z16044 = x16044 + z16045 = x16045 + z16046 = x16046 + z16047 = x16047 + z16048 = x16048 + z16049 = x16049 + z16050 = x16050 + z16051 = x16051 + z16052 = x16052 + z16053 = x16053 + z16054 = x16054 + z16055 = x16055 + z16056 = x16056 + z16057 = x16057 + z16058 = x16058 + z16059 = x16059 + z16060 = x16060 + z16061 = x16061 + z16062 = x16062 + z16063 = x16063 + z16064 = x16064 + z16065 = x16065 + z16066 = x16066 + z16067 = x16067 + z16068 = x16068 + z16069 = x16069 + z16070 = x16070 + z16071 = x16071 + z16072 = x16072 + z16073 = x16073 + z16074 = x16074 + z16075 = x16075 + z16076 = x16076 + z16077 = x16077 + z16078 = x16078 + z16079 = x16079 + z16080 = x16080 + z16081 = x16081 + z16082 = x16082 + z16083 = x16083 + z16084 = x16084 + z16085 = x16085 + z16086 = x16086 + z16087 = x16087 + z16088 = x16088 + z16089 = x16089 + z16090 = x16090 + z16091 = x16091 + z16092 = x16092 + z16093 = x16093 + z16094 = x16094 + z16095 = x16095 + z16096 = x16096 + z16097 = x16097 + z16098 = x16098 + z16099 = x16099 + z16100 = x16100 + z16101 = x16101 + z16102 = x16102 + z16103 = x16103 + z16104 = x16104 + z16105 = x16105 + z16106 = x16106 + z16107 = x16107 + z16108 = x16108 + z16109 = x16109 + z16110 = x16110 + z16111 = x16111 + z16112 = x16112 + z16113 = x16113 + z16114 = x16114 + z16115 = x16115 + z16116 = x16116 + z16117 = x16117 + z16118 = x16118 + z16119 = x16119 + z16120 = x16120 + z16121 = x16121 + z16122 = x16122 + z16123 = x16123 + z16124 = x16124 + z16125 = x16125 + z16126 = x16126 + z16127 = x16127 + z16128 = x16128 + z16129 = x16129 + z16130 = x16130 + z16131 = x16131 + z16132 = x16132 + z16133 = x16133 + z16134 = x16134 + z16135 = x16135 + z16136 = x16136 + z16137 = x16137 + z16138 = x16138 + z16139 = x16139 + z16140 = x16140 + z16141 = x16141 + z16142 = x16142 + z16143 = x16143 + z16144 = x16144 + z16145 = x16145 + z16146 = x16146 + z16147 = x16147 + z16148 = x16148 + z16149 = x16149 + z16150 = x16150 + z16151 = x16151 + z16152 = x16152 + z16153 = x16153 + z16154 = x16154 + z16155 = x16155 + z16156 = x16156 + z16157 = x16157 + z16158 = x16158 + z16159 = x16159 + z16160 = x16160 + z16161 = x16161 + z16162 = x16162 + z16163 = x16163 + z16164 = x16164 + z16165 = x16165 + z16166 = x16166 + z16167 = x16167 + z16168 = x16168 + z16169 = x16169 + z16170 = x16170 + z16171 = x16171 + z16172 = x16172 + z16173 = x16173 + z16174 = x16174 + z16175 = x16175 + z16176 = x16176 + z16177 = x16177 + z16178 = x16178 + z16179 = x16179 + z16180 = x16180 + z16181 = x16181 + z16182 = x16182 + z16183 = x16183 + z16184 = x16184 + z16185 = x16185 + z16186 = x16186 + z16187 = x16187 + z16188 = x16188 + z16189 = x16189 + z16190 = x16190 + z16191 = x16191 + z16192 = x16192 + z16193 = x16193 + z16194 = x16194 + z16195 = x16195 + z16196 = x16196 + z16197 = x16197 + z16198 = x16198 + z16199 = x16199 + z16200 = x16200 + z16201 = x16201 + z16202 = x16202 + z16203 = x16203 + z16204 = x16204 + z16205 = x16205 + z16206 = x16206 + z16207 = x16207 + z16208 = x16208 + z16209 = x16209 + z16210 = x16210 + z16211 = x16211 + z16212 = x16212 + z16213 = x16213 + z16214 = x16214 + z16215 = x16215 + z16216 = x16216 + z16217 = x16217 + z16218 = x16218 + z16219 = x16219 + z16220 = x16220 + z16221 = x16221 + z16222 = x16222 + z16223 = x16223 + z16224 = x16224 + z16225 = x16225 + z16226 = x16226 + z16227 = x16227 + z16228 = x16228 + z16229 = x16229 + z16230 = x16230 + z16231 = x16231 + z16232 = x16232 + z16233 = x16233 + z16234 = x16234 + z16235 = x16235 + z16236 = x16236 + z16237 = x16237 + z16238 = x16238 + z16239 = x16239 + z16240 = x16240 + z16241 = x16241 + z16242 = x16242 + z16243 = x16243 + z16244 = x16244 + z16245 = x16245 + z16246 = x16246 + z16247 = x16247 + z16248 = x16248 + z16249 = x16249 + z16250 = x16250 + z16251 = x16251 + z16252 = x16252 + z16253 = x16253 + z16254 = x16254 + z16255 = x16255 + z16256 = x16256 + z16257 = x16257 + z16258 = x16258 + z16259 = x16259 + z16260 = x16260 + z16261 = x16261 + z16262 = x16262 + z16263 = x16263 + z16264 = x16264 + z16265 = x16265 + z16266 = x16266 + z16267 = x16267 + z16268 = x16268 + z16269 = x16269 + z16270 = x16270 + z16271 = x16271 + z16272 = x16272 + z16273 = x16273 + z16274 = x16274 + z16275 = x16275 + z16276 = x16276 + z16277 = x16277 + z16278 = x16278 + z16279 = x16279 + z16280 = x16280 + z16281 = x16281 + z16282 = x16282 + z16283 = x16283 + z16284 = x16284 + z16285 = x16285 + z16286 = x16286 + z16287 = x16287 + z16288 = x16288 + z16289 = x16289 + z16290 = x16290 + z16291 = x16291 + z16292 = x16292 + z16293 = x16293 + z16294 = x16294 + z16295 = x16295 + z16296 = x16296 + z16297 = x16297 + z16298 = x16298 + z16299 = x16299 + z16300 = x16300 + z16301 = x16301 + z16302 = x16302 + z16303 = x16303 + z16304 = x16304 + z16305 = x16305 + z16306 = x16306 + z16307 = x16307 + z16308 = x16308 + z16309 = x16309 + z16310 = x16310 + z16311 = x16311 + z16312 = x16312 + z16313 = x16313 + z16314 = x16314 + z16315 = x16315 + z16316 = x16316 + z16317 = x16317 + z16318 = x16318 + z16319 = x16319 + z16320 = x16320 + z16321 = x16321 + z16322 = x16322 + z16323 = x16323 + z16324 = x16324 + z16325 = x16325 + z16326 = x16326 + z16327 = x16327 + z16328 = x16328 + z16329 = x16329 + z16330 = x16330 + z16331 = x16331 + z16332 = x16332 + z16333 = x16333 + z16334 = x16334 + z16335 = x16335 + z16336 = x16336 + z16337 = x16337 + z16338 = x16338 + z16339 = x16339 + z16340 = x16340 + z16341 = x16341 + z16342 = x16342 + z16343 = x16343 + z16344 = x16344 + z16345 = x16345 + z16346 = x16346 + z16347 = x16347 + z16348 = x16348 + z16349 = x16349 + z16350 = x16350 + z16351 = x16351 + z16352 = x16352 + z16353 = x16353 + z16354 = x16354 + z16355 = x16355 + z16356 = x16356 + z16357 = x16357 + z16358 = x16358 + z16359 = x16359 + z16360 = x16360 + z16361 = x16361 + z16362 = x16362 + z16363 = x16363 + z16364 = x16364 + z16365 = x16365 + z16366 = x16366 + z16367 = x16367 + z16368 = x16368 + z16369 = x16369 + z16370 = x16370 + z16371 = x16371 + z16372 = x16372 + z16373 = x16373 + z16374 = x16374 + z16375 = x16375 + z16376 = x16376 + z16377 = x16377 + z16378 = x16378 + z16379 = x16379 + z16380 = x16380 + z16381 = x16381 + z16382 = x16382 + z16383 = x16383 + z16384 = x16384 + z16385 = x16385 + z16386 = x16386 + z16387 = x16387 + z16388 = x16388 + z16389 = x16389 + z16390 = x16390 + z16391 = x16391 + z16392 = x16392 + z16393 = x16393 + z16394 = x16394 + z16395 = x16395 + z16396 = x16396 + z16397 = x16397 + z16398 = x16398 + z16399 = x16399 + z16400 = x16400 + z16401 = x16401 + z16402 = x16402 + z16403 = x16403 + z16404 = x16404 + z16405 = x16405 + z16406 = x16406 + z16407 = x16407 + z16408 = x16408 + z16409 = x16409 + z16410 = x16410 + z16411 = x16411 + z16412 = x16412 + z16413 = x16413 + z16414 = x16414 + z16415 = x16415 + z16416 = x16416 + z16417 = x16417 + z16418 = x16418 + z16419 = x16419 + z16420 = x16420 + z16421 = x16421 + z16422 = x16422 + z16423 = x16423 + z16424 = x16424 + z16425 = x16425 + z16426 = x16426 + z16427 = x16427 + z16428 = x16428 + z16429 = x16429 + z16430 = x16430 + z16431 = x16431 + z16432 = x16432 + z16433 = x16433 + z16434 = x16434 + z16435 = x16435 + z16436 = x16436 + z16437 = x16437 + z16438 = x16438 + z16439 = x16439 + z16440 = x16440 + z16441 = x16441 + z16442 = x16442 + z16443 = x16443 + z16444 = x16444 + z16445 = x16445 + z16446 = x16446 + z16447 = x16447 + z16448 = x16448 + z16449 = x16449 + z16450 = x16450 + z16451 = x16451 + z16452 = x16452 + z16453 = x16453 + z16454 = x16454 + z16455 = x16455 + z16456 = x16456 + z16457 = x16457 + z16458 = x16458 + z16459 = x16459 + z16460 = x16460 + z16461 = x16461 + z16462 = x16462 + z16463 = x16463 + z16464 = x16464 + z16465 = x16465 + z16466 = x16466 + z16467 = x16467 + z16468 = x16468 + z16469 = x16469 + z16470 = x16470 + z16471 = x16471 + z16472 = x16472 + z16473 = x16473 + z16474 = x16474 + z16475 = x16475 + z16476 = x16476 + z16477 = x16477 + z16478 = x16478 + z16479 = x16479 + z16480 = x16480 } 786799a1bbd0d9731b844779c9e607304b2c4164.paxheader00006660000000000000000000000240151600170720020151xustar00rootroot00000000000000160 path=diff-1.0.1/textdiff/testdata/go_ca14eaf77c86bd5492329d2be6f1a82afe7802f5_src_vendor_golang.org_x_crypto_chacha20poly1305_chacha20poly1305_amd64.s.test 786799a1bbd0d9731b844779c9e607304b2c4164.data000066400000000000000000033457151516001707200170350ustar00rootroot00000000000000From https://go.googlesource.com/go commit ca14eaf77c86bd5492329d2be6f1a82afe7802f5 file src/vendor/golang.org/x/crypto/chacha20poly1305/chacha20poly1305_amd64.s -- x -- // Copyright 2016 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // This file was originally from https://golang.org/cl/24717 by Vlad Krasnov of CloudFlare. //go:build gc && !purego #include "textflag.h" // General register allocation #define oup DI #define inp SI #define inl BX #define adp CX // free to reuse, after we hash the additional data #define keyp R8 // free to reuse, when we copy the key to stack #define itr2 R9 // general iterator #define itr1 CX // general iterator #define acc0 R10 #define acc1 R11 #define acc2 R12 #define t0 R13 #define t1 R14 #define t2 R15 #define t3 R8 // Register and stack allocation for the SSE code #define rStore (0*16)(BP) #define sStore (1*16)(BP) #define state1Store (2*16)(BP) #define state2Store (3*16)(BP) #define tmpStore (4*16)(BP) #define ctr0Store (5*16)(BP) #define ctr1Store (6*16)(BP) #define ctr2Store (7*16)(BP) #define ctr3Store (8*16)(BP) #define A0 X0 #define A1 X1 #define A2 X2 #define B0 X3 #define B1 X4 #define B2 X5 #define C0 X6 #define C1 X7 #define C2 X8 #define D0 X9 #define D1 X10 #define D2 X11 #define T0 X12 #define T1 X13 #define T2 X14 #define T3 X15 #define A3 T0 #define B3 T1 #define C3 T2 #define D3 T3 // Register and stack allocation for the AVX2 code #define rsStoreAVX2 (0*32)(BP) #define state1StoreAVX2 (1*32)(BP) #define state2StoreAVX2 (2*32)(BP) #define ctr0StoreAVX2 (3*32)(BP) #define ctr1StoreAVX2 (4*32)(BP) #define ctr2StoreAVX2 (5*32)(BP) #define ctr3StoreAVX2 (6*32)(BP) #define tmpStoreAVX2 (7*32)(BP) // 256 bytes on stack #define AA0 Y0 #define AA1 Y5 #define AA2 Y6 #define AA3 Y7 #define BB0 Y14 #define BB1 Y9 #define BB2 Y10 #define BB3 Y11 #define CC0 Y12 #define CC1 Y13 #define CC2 Y8 #define CC3 Y15 #define DD0 Y4 #define DD1 Y1 #define DD2 Y2 #define DD3 Y3 #define TT0 DD3 #define TT1 AA3 #define TT2 BB3 #define TT3 CC3 // ChaCha20 constants DATA ·chacha20Constants<>+0x00(SB)/4, $0x61707865 DATA ·chacha20Constants<>+0x04(SB)/4, $0x3320646e DATA ·chacha20Constants<>+0x08(SB)/4, $0x79622d32 DATA ·chacha20Constants<>+0x0c(SB)/4, $0x6b206574 DATA ·chacha20Constants<>+0x10(SB)/4, $0x61707865 DATA ·chacha20Constants<>+0x14(SB)/4, $0x3320646e DATA ·chacha20Constants<>+0x18(SB)/4, $0x79622d32 DATA ·chacha20Constants<>+0x1c(SB)/4, $0x6b206574 // <<< 16 with PSHUFB DATA ·rol16<>+0x00(SB)/8, $0x0504070601000302 DATA ·rol16<>+0x08(SB)/8, $0x0D0C0F0E09080B0A DATA ·rol16<>+0x10(SB)/8, $0x0504070601000302 DATA ·rol16<>+0x18(SB)/8, $0x0D0C0F0E09080B0A // <<< 8 with PSHUFB DATA ·rol8<>+0x00(SB)/8, $0x0605040702010003 DATA ·rol8<>+0x08(SB)/8, $0x0E0D0C0F0A09080B DATA ·rol8<>+0x10(SB)/8, $0x0605040702010003 DATA ·rol8<>+0x18(SB)/8, $0x0E0D0C0F0A09080B DATA ·avx2InitMask<>+0x00(SB)/8, $0x0 DATA ·avx2InitMask<>+0x08(SB)/8, $0x0 DATA ·avx2InitMask<>+0x10(SB)/8, $0x1 DATA ·avx2InitMask<>+0x18(SB)/8, $0x0 DATA ·avx2IncMask<>+0x00(SB)/8, $0x2 DATA ·avx2IncMask<>+0x08(SB)/8, $0x0 DATA ·avx2IncMask<>+0x10(SB)/8, $0x2 DATA ·avx2IncMask<>+0x18(SB)/8, $0x0 // Poly1305 key clamp DATA ·polyClampMask<>+0x00(SB)/8, $0x0FFFFFFC0FFFFFFF DATA ·polyClampMask<>+0x08(SB)/8, $0x0FFFFFFC0FFFFFFC DATA ·polyClampMask<>+0x10(SB)/8, $0xFFFFFFFFFFFFFFFF DATA ·polyClampMask<>+0x18(SB)/8, $0xFFFFFFFFFFFFFFFF DATA ·sseIncMask<>+0x00(SB)/8, $0x1 DATA ·sseIncMask<>+0x08(SB)/8, $0x0 // To load/store the last < 16 bytes in a buffer DATA ·andMask<>+0x00(SB)/8, $0x00000000000000ff DATA ·andMask<>+0x08(SB)/8, $0x0000000000000000 DATA ·andMask<>+0x10(SB)/8, $0x000000000000ffff DATA ·andMask<>+0x18(SB)/8, $0x0000000000000000 DATA ·andMask<>+0x20(SB)/8, $0x0000000000ffffff DATA ·andMask<>+0x28(SB)/8, $0x0000000000000000 DATA ·andMask<>+0x30(SB)/8, $0x00000000ffffffff DATA ·andMask<>+0x38(SB)/8, $0x0000000000000000 DATA ·andMask<>+0x40(SB)/8, $0x000000ffffffffff DATA ·andMask<>+0x48(SB)/8, $0x0000000000000000 DATA ·andMask<>+0x50(SB)/8, $0x0000ffffffffffff DATA ·andMask<>+0x58(SB)/8, $0x0000000000000000 DATA ·andMask<>+0x60(SB)/8, $0x00ffffffffffffff DATA ·andMask<>+0x68(SB)/8, $0x0000000000000000 DATA ·andMask<>+0x70(SB)/8, $0xffffffffffffffff DATA ·andMask<>+0x78(SB)/8, $0x0000000000000000 DATA ·andMask<>+0x80(SB)/8, $0xffffffffffffffff DATA ·andMask<>+0x88(SB)/8, $0x00000000000000ff DATA ·andMask<>+0x90(SB)/8, $0xffffffffffffffff DATA ·andMask<>+0x98(SB)/8, $0x000000000000ffff DATA ·andMask<>+0xa0(SB)/8, $0xffffffffffffffff DATA ·andMask<>+0xa8(SB)/8, $0x0000000000ffffff DATA ·andMask<>+0xb0(SB)/8, $0xffffffffffffffff DATA ·andMask<>+0xb8(SB)/8, $0x00000000ffffffff DATA ·andMask<>+0xc0(SB)/8, $0xffffffffffffffff DATA ·andMask<>+0xc8(SB)/8, $0x000000ffffffffff DATA ·andMask<>+0xd0(SB)/8, $0xffffffffffffffff DATA ·andMask<>+0xd8(SB)/8, $0x0000ffffffffffff DATA ·andMask<>+0xe0(SB)/8, $0xffffffffffffffff DATA ·andMask<>+0xe8(SB)/8, $0x00ffffffffffffff GLOBL ·chacha20Constants<>(SB), (NOPTR+RODATA), $32 GLOBL ·rol16<>(SB), (NOPTR+RODATA), $32 GLOBL ·rol8<>(SB), (NOPTR+RODATA), $32 GLOBL ·sseIncMask<>(SB), (NOPTR+RODATA), $16 GLOBL ·avx2IncMask<>(SB), (NOPTR+RODATA), $32 GLOBL ·avx2InitMask<>(SB), (NOPTR+RODATA), $32 GLOBL ·polyClampMask<>(SB), (NOPTR+RODATA), $32 GLOBL ·andMask<>(SB), (NOPTR+RODATA), $240 // No PALIGNR in Go ASM yet (but VPALIGNR is present). #define shiftB0Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xdb; BYTE $0x04 // PALIGNR $4, X3, X3 #define shiftB1Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xe4; BYTE $0x04 // PALIGNR $4, X4, X4 #define shiftB2Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xed; BYTE $0x04 // PALIGNR $4, X5, X5 #define shiftB3Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xed; BYTE $0x04 // PALIGNR $4, X13, X13 #define shiftC0Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xf6; BYTE $0x08 // PALIGNR $8, X6, X6 #define shiftC1Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xff; BYTE $0x08 // PALIGNR $8, X7, X7 #define shiftC2Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xc0; BYTE $0x08 // PALIGNR $8, X8, X8 #define shiftC3Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xf6; BYTE $0x08 // PALIGNR $8, X14, X14 #define shiftD0Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xc9; BYTE $0x0c // PALIGNR $12, X9, X9 #define shiftD1Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xd2; BYTE $0x0c // PALIGNR $12, X10, X10 #define shiftD2Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xdb; BYTE $0x0c // PALIGNR $12, X11, X11 #define shiftD3Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xff; BYTE $0x0c // PALIGNR $12, X15, X15 #define shiftB0Right BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xdb; BYTE $0x0c // PALIGNR $12, X3, X3 #define shiftB1Right BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xe4; BYTE $0x0c // PALIGNR $12, X4, X4 #define shiftB2Right BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xed; BYTE $0x0c // PALIGNR $12, X5, X5 #define shiftB3Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xed; BYTE $0x0c // PALIGNR $12, X13, X13 #define shiftC0Right shiftC0Left #define shiftC1Right shiftC1Left #define shiftC2Right shiftC2Left #define shiftC3Right shiftC3Left #define shiftD0Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xc9; BYTE $0x04 // PALIGNR $4, X9, X9 #define shiftD1Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xd2; BYTE $0x04 // PALIGNR $4, X10, X10 #define shiftD2Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xdb; BYTE $0x04 // PALIGNR $4, X11, X11 #define shiftD3Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xff; BYTE $0x04 // PALIGNR $4, X15, X15 // Some macros // ROL rotates the uint32s in register R left by N bits, using temporary T. #define ROL(N, R, T) \ MOVO R, T; PSLLL $(N), T; PSRLL $(32-(N)), R; PXOR T, R // ROL16 rotates the uint32s in register R left by 16, using temporary T if needed. #ifdef GOAMD64_v2 #define ROL16(R, T) PSHUFB ·rol16<>(SB), R #else #define ROL16(R, T) ROL(16, R, T) #endif // ROL8 rotates the uint32s in register R left by 8, using temporary T if needed. #ifdef GOAMD64_v2 #define ROL8(R, T) PSHUFB ·rol8<>(SB), R #else #define ROL8(R, T) ROL(8, R, T) #endif #define chachaQR(A, B, C, D, T) \ PADDD B, A; PXOR A, D; ROL16(D, T) \ PADDD D, C; PXOR C, B; MOVO B, T; PSLLL $12, T; PSRLL $20, B; PXOR T, B \ PADDD B, A; PXOR A, D; ROL8(D, T) \ PADDD D, C; PXOR C, B; MOVO B, T; PSLLL $7, T; PSRLL $25, B; PXOR T, B #define chachaQR_AVX2(A, B, C, D, T) \ VPADDD B, A, A; VPXOR A, D, D; VPSHUFB ·rol16<>(SB), D, D \ VPADDD D, C, C; VPXOR C, B, B; VPSLLD $12, B, T; VPSRLD $20, B, B; VPXOR T, B, B \ VPADDD B, A, A; VPXOR A, D, D; VPSHUFB ·rol8<>(SB), D, D \ VPADDD D, C, C; VPXOR C, B, B; VPSLLD $7, B, T; VPSRLD $25, B, B; VPXOR T, B, B #define polyAdd(S) ADDQ S, acc0; ADCQ 8+S, acc1; ADCQ $1, acc2 #define polyMulStage1 MOVQ (0*8)(BP), AX; MOVQ AX, t2; MULQ acc0; MOVQ AX, t0; MOVQ DX, t1; MOVQ (0*8)(BP), AX; MULQ acc1; IMULQ acc2, t2; ADDQ AX, t1; ADCQ DX, t2 #define polyMulStage2 MOVQ (1*8)(BP), AX; MOVQ AX, t3; MULQ acc0; ADDQ AX, t1; ADCQ $0, DX; MOVQ DX, acc0; MOVQ (1*8)(BP), AX; MULQ acc1; ADDQ AX, t2; ADCQ $0, DX #define polyMulStage3 IMULQ acc2, t3; ADDQ acc0, t2; ADCQ DX, t3 #define polyMulReduceStage MOVQ t0, acc0; MOVQ t1, acc1; MOVQ t2, acc2; ANDQ $3, acc2; MOVQ t2, t0; ANDQ $-4, t0; MOVQ t3, t1; SHRQ $2, t3, t2; SHRQ $2, t3; ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $0, acc2; ADDQ t2, acc0; ADCQ t3, acc1; ADCQ $0, acc2 #define polyMulStage1_AVX2 MOVQ (0*8)(BP), DX; MOVQ DX, t2; MULXQ acc0, t0, t1; IMULQ acc2, t2; MULXQ acc1, AX, DX; ADDQ AX, t1; ADCQ DX, t2 #define polyMulStage2_AVX2 MOVQ (1*8)(BP), DX; MULXQ acc0, acc0, AX; ADDQ acc0, t1; MULXQ acc1, acc1, t3; ADCQ acc1, t2; ADCQ $0, t3 #define polyMulStage3_AVX2 IMULQ acc2, DX; ADDQ AX, t2; ADCQ DX, t3 #define polyMul polyMulStage1; polyMulStage2; polyMulStage3; polyMulReduceStage #define polyMulAVX2 polyMulStage1_AVX2; polyMulStage2_AVX2; polyMulStage3_AVX2; polyMulReduceStage // ---------------------------------------------------------------------------- TEXT polyHashADInternal<>(SB), NOSPLIT, $0 // adp points to beginning of additional data // itr2 holds ad length XORQ acc0, acc0 XORQ acc1, acc1 XORQ acc2, acc2 CMPQ itr2, $13 JNE hashADLoop openFastTLSAD: // Special treatment for the TLS case of 13 bytes MOVQ (adp), acc0 MOVQ 5(adp), acc1 SHRQ $24, acc1 MOVQ $1, acc2 polyMul RET hashADLoop: // Hash in 16 byte chunks CMPQ itr2, $16 JB hashADTail polyAdd(0(adp)) LEAQ (1*16)(adp), adp SUBQ $16, itr2 polyMul JMP hashADLoop hashADTail: CMPQ itr2, $0 JE hashADDone // Hash last < 16 byte tail XORQ t0, t0 XORQ t1, t1 XORQ t2, t2 ADDQ itr2, adp hashADTailLoop: SHLQ $8, t0, t1 SHLQ $8, t0 MOVB -1(adp), t2 XORQ t2, t0 DECQ adp DECQ itr2 JNE hashADTailLoop hashADTailFinish: ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $1, acc2 polyMul // Finished AD hashADDone: RET // ---------------------------------------------------------------------------- // func chacha20Poly1305Open(dst, key, src, ad []byte) bool TEXT ·chacha20Poly1305Open(SB), 0, $288-97 // For aligned stack access MOVQ SP, BP ADDQ $32, BP ANDQ $-32, BP MOVQ dst+0(FP), oup MOVQ key+24(FP), keyp MOVQ src+48(FP), inp MOVQ src_len+56(FP), inl MOVQ ad+72(FP), adp // Check for AVX2 support CMPB ·useAVX2(SB), $1 JE chacha20Poly1305Open_AVX2 // Special optimization, for very short buffers CMPQ inl, $128 JBE openSSE128 // About 16% faster // For long buffers, prepare the poly key first MOVOU ·chacha20Constants<>(SB), A0 MOVOU (1*16)(keyp), B0 MOVOU (2*16)(keyp), C0 MOVOU (3*16)(keyp), D0 MOVO D0, T1 // Store state on stack for future use MOVO B0, state1Store MOVO C0, state2Store MOVO D0, ctr3Store MOVQ $10, itr2 openSSEPreparePolyKey: chachaQR(A0, B0, C0, D0, T0) shiftB0Left; shiftC0Left; shiftD0Left chachaQR(A0, B0, C0, D0, T0) shiftB0Right; shiftC0Right; shiftD0Right DECQ itr2 JNE openSSEPreparePolyKey // A0|B0 hold the Poly1305 32-byte key, C0,D0 can be discarded PADDL ·chacha20Constants<>(SB), A0; PADDL state1Store, B0 // Clamp and store the key PAND ·polyClampMask<>(SB), A0 MOVO A0, rStore; MOVO B0, sStore // Hash AAD MOVQ ad_len+80(FP), itr2 CALL polyHashADInternal<>(SB) openSSEMainLoop: CMPQ inl, $256 JB openSSEMainLoopDone // Load state, increment counter blocks MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0 MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 MOVO A2, A3; MOVO B2, B3; MOVO C2, C3; MOVO D2, D3; PADDL ·sseIncMask<>(SB), D3 // Store counters MOVO D0, ctr0Store; MOVO D1, ctr1Store; MOVO D2, ctr2Store; MOVO D3, ctr3Store // There are 10 ChaCha20 iterations of 2QR each, so for 6 iterations we hash 2 blocks, and for the remaining 4 only 1 block - for a total of 16 MOVQ $4, itr1 MOVQ inp, itr2 openSSEInternalLoop: MOVO C3, tmpStore chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) MOVO tmpStore, C3 MOVO C1, tmpStore chachaQR(A3, B3, C3, D3, C1) MOVO tmpStore, C1 polyAdd(0(itr2)) shiftB0Left; shiftB1Left; shiftB2Left; shiftB3Left shiftC0Left; shiftC1Left; shiftC2Left; shiftC3Left shiftD0Left; shiftD1Left; shiftD2Left; shiftD3Left polyMulStage1 polyMulStage2 LEAQ (2*8)(itr2), itr2 MOVO C3, tmpStore chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) MOVO tmpStore, C3 MOVO C1, tmpStore polyMulStage3 chachaQR(A3, B3, C3, D3, C1) MOVO tmpStore, C1 polyMulReduceStage shiftB0Right; shiftB1Right; shiftB2Right; shiftB3Right shiftC0Right; shiftC1Right; shiftC2Right; shiftC3Right shiftD0Right; shiftD1Right; shiftD2Right; shiftD3Right DECQ itr1 JGE openSSEInternalLoop polyAdd(0(itr2)) polyMul LEAQ (2*8)(itr2), itr2 CMPQ itr1, $-6 JG openSSEInternalLoop // Add in the state PADDD ·chacha20Constants<>(SB), A0; PADDD ·chacha20Constants<>(SB), A1; PADDD ·chacha20Constants<>(SB), A2; PADDD ·chacha20Constants<>(SB), A3 PADDD state1Store, B0; PADDD state1Store, B1; PADDD state1Store, B2; PADDD state1Store, B3 PADDD state2Store, C0; PADDD state2Store, C1; PADDD state2Store, C2; PADDD state2Store, C3 PADDD ctr0Store, D0; PADDD ctr1Store, D1; PADDD ctr2Store, D2; PADDD ctr3Store, D3 // Load - xor - store MOVO D3, tmpStore MOVOU (0*16)(inp), D3; PXOR D3, A0; MOVOU A0, (0*16)(oup) MOVOU (1*16)(inp), D3; PXOR D3, B0; MOVOU B0, (1*16)(oup) MOVOU (2*16)(inp), D3; PXOR D3, C0; MOVOU C0, (2*16)(oup) MOVOU (3*16)(inp), D3; PXOR D3, D0; MOVOU D0, (3*16)(oup) MOVOU (4*16)(inp), D0; PXOR D0, A1; MOVOU A1, (4*16)(oup) MOVOU (5*16)(inp), D0; PXOR D0, B1; MOVOU B1, (5*16)(oup) MOVOU (6*16)(inp), D0; PXOR D0, C1; MOVOU C1, (6*16)(oup) MOVOU (7*16)(inp), D0; PXOR D0, D1; MOVOU D1, (7*16)(oup) MOVOU (8*16)(inp), D0; PXOR D0, A2; MOVOU A2, (8*16)(oup) MOVOU (9*16)(inp), D0; PXOR D0, B2; MOVOU B2, (9*16)(oup) MOVOU (10*16)(inp), D0; PXOR D0, C2; MOVOU C2, (10*16)(oup) MOVOU (11*16)(inp), D0; PXOR D0, D2; MOVOU D2, (11*16)(oup) MOVOU (12*16)(inp), D0; PXOR D0, A3; MOVOU A3, (12*16)(oup) MOVOU (13*16)(inp), D0; PXOR D0, B3; MOVOU B3, (13*16)(oup) MOVOU (14*16)(inp), D0; PXOR D0, C3; MOVOU C3, (14*16)(oup) MOVOU (15*16)(inp), D0; PXOR tmpStore, D0; MOVOU D0, (15*16)(oup) LEAQ 256(inp), inp LEAQ 256(oup), oup SUBQ $256, inl JMP openSSEMainLoop openSSEMainLoopDone: // Handle the various tail sizes efficiently TESTQ inl, inl JE openSSEFinalize CMPQ inl, $64 JBE openSSETail64 CMPQ inl, $128 JBE openSSETail128 CMPQ inl, $192 JBE openSSETail192 JMP openSSETail256 openSSEFinalize: // Hash in the PT, AAD lengths ADDQ ad_len+80(FP), acc0; ADCQ src_len+56(FP), acc1; ADCQ $1, acc2 polyMul // Final reduce MOVQ acc0, t0 MOVQ acc1, t1 MOVQ acc2, t2 SUBQ $-5, acc0 SBBQ $-1, acc1 SBBQ $3, acc2 CMOVQCS t0, acc0 CMOVQCS t1, acc1 CMOVQCS t2, acc2 // Add in the "s" part of the key ADDQ 0+sStore, acc0 ADCQ 8+sStore, acc1 // Finally, constant time compare to the tag at the end of the message XORQ AX, AX MOVQ $1, DX XORQ (0*8)(inp), acc0 XORQ (1*8)(inp), acc1 ORQ acc1, acc0 CMOVQEQ DX, AX // Return true iff tags are equal MOVB AX, ret+96(FP) RET // ---------------------------------------------------------------------------- // Special optimization for buffers smaller than 129 bytes openSSE128: // For up to 128 bytes of ciphertext and 64 bytes for the poly key, we require to process three blocks MOVOU ·chacha20Constants<>(SB), A0; MOVOU (1*16)(keyp), B0; MOVOU (2*16)(keyp), C0; MOVOU (3*16)(keyp), D0 MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 MOVO B0, T1; MOVO C0, T2; MOVO D1, T3 MOVQ $10, itr2 openSSE128InnerCipherLoop: chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) shiftB0Left; shiftB1Left; shiftB2Left shiftC0Left; shiftC1Left; shiftC2Left shiftD0Left; shiftD1Left; shiftD2Left chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) shiftB0Right; shiftB1Right; shiftB2Right shiftC0Right; shiftC1Right; shiftC2Right shiftD0Right; shiftD1Right; shiftD2Right DECQ itr2 JNE openSSE128InnerCipherLoop // A0|B0 hold the Poly1305 32-byte key, C0,D0 can be discarded PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1; PADDL ·chacha20Constants<>(SB), A2 PADDL T1, B0; PADDL T1, B1; PADDL T1, B2 PADDL T2, C1; PADDL T2, C2 PADDL T3, D1; PADDL ·sseIncMask<>(SB), T3; PADDL T3, D2 // Clamp and store the key PAND ·polyClampMask<>(SB), A0 MOVOU A0, rStore; MOVOU B0, sStore // Hash MOVQ ad_len+80(FP), itr2 CALL polyHashADInternal<>(SB) openSSE128Open: CMPQ inl, $16 JB openSSETail16 SUBQ $16, inl // Load for hashing polyAdd(0(inp)) // Load for decryption MOVOU (inp), T0; PXOR T0, A1; MOVOU A1, (oup) LEAQ (1*16)(inp), inp LEAQ (1*16)(oup), oup polyMul // Shift the stream "left" MOVO B1, A1 MOVO C1, B1 MOVO D1, C1 MOVO A2, D1 MOVO B2, A2 MOVO C2, B2 MOVO D2, C2 JMP openSSE128Open openSSETail16: TESTQ inl, inl JE openSSEFinalize // We can safely load the CT from the end, because it is padded with the MAC MOVQ inl, itr2 SHLQ $4, itr2 LEAQ ·andMask<>(SB), t0 MOVOU (inp), T0 ADDQ inl, inp PAND -16(t0)(itr2*1), T0 MOVO T0, 0+tmpStore MOVQ T0, t0 MOVQ 8+tmpStore, t1 PXOR A1, T0 // We can only store one byte at a time, since plaintext can be shorter than 16 bytes openSSETail16Store: MOVQ T0, t3 MOVB t3, (oup) PSRLDQ $1, T0 INCQ oup DECQ inl JNE openSSETail16Store ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $1, acc2 polyMul JMP openSSEFinalize // ---------------------------------------------------------------------------- // Special optimization for the last 64 bytes of ciphertext openSSETail64: // Need to decrypt up to 64 bytes - prepare single block MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr0Store XORQ itr2, itr2 MOVQ inl, itr1 CMPQ itr1, $16 JB openSSETail64LoopB openSSETail64LoopA: // Perform ChaCha rounds, while hashing the remaining input polyAdd(0(inp)(itr2*1)) polyMul SUBQ $16, itr1 openSSETail64LoopB: ADDQ $16, itr2 chachaQR(A0, B0, C0, D0, T0) shiftB0Left; shiftC0Left; shiftD0Left chachaQR(A0, B0, C0, D0, T0) shiftB0Right; shiftC0Right; shiftD0Right CMPQ itr1, $16 JAE openSSETail64LoopA CMPQ itr2, $160 JNE openSSETail64LoopB PADDL ·chacha20Constants<>(SB), A0; PADDL state1Store, B0; PADDL state2Store, C0; PADDL ctr0Store, D0 openSSETail64DecLoop: CMPQ inl, $16 JB openSSETail64DecLoopDone SUBQ $16, inl MOVOU (inp), T0 PXOR T0, A0 MOVOU A0, (oup) LEAQ 16(inp), inp LEAQ 16(oup), oup MOVO B0, A0 MOVO C0, B0 MOVO D0, C0 JMP openSSETail64DecLoop openSSETail64DecLoopDone: MOVO A0, A1 JMP openSSETail16 // ---------------------------------------------------------------------------- // Special optimization for the last 128 bytes of ciphertext openSSETail128: // Need to decrypt up to 128 bytes - prepare two blocks MOVO ·chacha20Constants<>(SB), A1; MOVO state1Store, B1; MOVO state2Store, C1; MOVO ctr3Store, D1; PADDL ·sseIncMask<>(SB), D1; MOVO D1, ctr0Store MOVO A1, A0; MOVO B1, B0; MOVO C1, C0; MOVO D1, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr1Store XORQ itr2, itr2 MOVQ inl, itr1 ANDQ $-16, itr1 openSSETail128LoopA: // Perform ChaCha rounds, while hashing the remaining input polyAdd(0(inp)(itr2*1)) polyMul openSSETail128LoopB: ADDQ $16, itr2 chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0) shiftB0Left; shiftC0Left; shiftD0Left shiftB1Left; shiftC1Left; shiftD1Left chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0) shiftB0Right; shiftC0Right; shiftD0Right shiftB1Right; shiftC1Right; shiftD1Right CMPQ itr2, itr1 JB openSSETail128LoopA CMPQ itr2, $160 JNE openSSETail128LoopB PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1 PADDL state1Store, B0; PADDL state1Store, B1 PADDL state2Store, C0; PADDL state2Store, C1 PADDL ctr1Store, D0; PADDL ctr0Store, D1 MOVOU (0*16)(inp), T0; MOVOU (1*16)(inp), T1; MOVOU (2*16)(inp), T2; MOVOU (3*16)(inp), T3 PXOR T0, A1; PXOR T1, B1; PXOR T2, C1; PXOR T3, D1 MOVOU A1, (0*16)(oup); MOVOU B1, (1*16)(oup); MOVOU C1, (2*16)(oup); MOVOU D1, (3*16)(oup) SUBQ $64, inl LEAQ 64(inp), inp LEAQ 64(oup), oup JMP openSSETail64DecLoop // ---------------------------------------------------------------------------- // Special optimization for the last 192 bytes of ciphertext openSSETail192: // Need to decrypt up to 192 bytes - prepare three blocks MOVO ·chacha20Constants<>(SB), A2; MOVO state1Store, B2; MOVO state2Store, C2; MOVO ctr3Store, D2; PADDL ·sseIncMask<>(SB), D2; MOVO D2, ctr0Store MOVO A2, A1; MOVO B2, B1; MOVO C2, C1; MOVO D2, D1; PADDL ·sseIncMask<>(SB), D1; MOVO D1, ctr1Store MOVO A1, A0; MOVO B1, B0; MOVO C1, C0; MOVO D1, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr2Store MOVQ inl, itr1 MOVQ $160, itr2 CMPQ itr1, $160 CMOVQGT itr2, itr1 ANDQ $-16, itr1 XORQ itr2, itr2 openSSLTail192LoopA: // Perform ChaCha rounds, while hashing the remaining input polyAdd(0(inp)(itr2*1)) polyMul openSSLTail192LoopB: ADDQ $16, itr2 chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) shiftB0Left; shiftC0Left; shiftD0Left shiftB1Left; shiftC1Left; shiftD1Left shiftB2Left; shiftC2Left; shiftD2Left chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) shiftB0Right; shiftC0Right; shiftD0Right shiftB1Right; shiftC1Right; shiftD1Right shiftB2Right; shiftC2Right; shiftD2Right CMPQ itr2, itr1 JB openSSLTail192LoopA CMPQ itr2, $160 JNE openSSLTail192LoopB CMPQ inl, $176 JB openSSLTail192Store polyAdd(160(inp)) polyMul CMPQ inl, $192 JB openSSLTail192Store polyAdd(176(inp)) polyMul openSSLTail192Store: PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1; PADDL ·chacha20Constants<>(SB), A2 PADDL state1Store, B0; PADDL state1Store, B1; PADDL state1Store, B2 PADDL state2Store, C0; PADDL state2Store, C1; PADDL state2Store, C2 PADDL ctr2Store, D0; PADDL ctr1Store, D1; PADDL ctr0Store, D2 MOVOU (0*16)(inp), T0; MOVOU (1*16)(inp), T1; MOVOU (2*16)(inp), T2; MOVOU (3*16)(inp), T3 PXOR T0, A2; PXOR T1, B2; PXOR T2, C2; PXOR T3, D2 MOVOU A2, (0*16)(oup); MOVOU B2, (1*16)(oup); MOVOU C2, (2*16)(oup); MOVOU D2, (3*16)(oup) MOVOU (4*16)(inp), T0; MOVOU (5*16)(inp), T1; MOVOU (6*16)(inp), T2; MOVOU (7*16)(inp), T3 PXOR T0, A1; PXOR T1, B1; PXOR T2, C1; PXOR T3, D1 MOVOU A1, (4*16)(oup); MOVOU B1, (5*16)(oup); MOVOU C1, (6*16)(oup); MOVOU D1, (7*16)(oup) SUBQ $128, inl LEAQ 128(inp), inp LEAQ 128(oup), oup JMP openSSETail64DecLoop // ---------------------------------------------------------------------------- // Special optimization for the last 256 bytes of ciphertext openSSETail256: // Need to decrypt up to 256 bytes - prepare four blocks MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0 MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 MOVO A2, A3; MOVO B2, B3; MOVO C2, C3; MOVO D2, D3; PADDL ·sseIncMask<>(SB), D3 // Store counters MOVO D0, ctr0Store; MOVO D1, ctr1Store; MOVO D2, ctr2Store; MOVO D3, ctr3Store XORQ itr2, itr2 openSSETail256Loop: // This loop inteleaves 8 ChaCha quarter rounds with 1 poly multiplication polyAdd(0(inp)(itr2*1)) MOVO C3, tmpStore chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) MOVO tmpStore, C3 MOVO C1, tmpStore chachaQR(A3, B3, C3, D3, C1) MOVO tmpStore, C1 shiftB0Left; shiftB1Left; shiftB2Left; shiftB3Left shiftC0Left; shiftC1Left; shiftC2Left; shiftC3Left shiftD0Left; shiftD1Left; shiftD2Left; shiftD3Left polyMulStage1 polyMulStage2 MOVO C3, tmpStore chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) MOVO tmpStore, C3 MOVO C1, tmpStore chachaQR(A3, B3, C3, D3, C1) MOVO tmpStore, C1 polyMulStage3 polyMulReduceStage shiftB0Right; shiftB1Right; shiftB2Right; shiftB3Right shiftC0Right; shiftC1Right; shiftC2Right; shiftC3Right shiftD0Right; shiftD1Right; shiftD2Right; shiftD3Right ADDQ $2*8, itr2 CMPQ itr2, $160 JB openSSETail256Loop MOVQ inl, itr1 ANDQ $-16, itr1 openSSETail256HashLoop: polyAdd(0(inp)(itr2*1)) polyMul ADDQ $2*8, itr2 CMPQ itr2, itr1 JB openSSETail256HashLoop // Add in the state PADDD ·chacha20Constants<>(SB), A0; PADDD ·chacha20Constants<>(SB), A1; PADDD ·chacha20Constants<>(SB), A2; PADDD ·chacha20Constants<>(SB), A3 PADDD state1Store, B0; PADDD state1Store, B1; PADDD state1Store, B2; PADDD state1Store, B3 PADDD state2Store, C0; PADDD state2Store, C1; PADDD state2Store, C2; PADDD state2Store, C3 PADDD ctr0Store, D0; PADDD ctr1Store, D1; PADDD ctr2Store, D2; PADDD ctr3Store, D3 MOVO D3, tmpStore // Load - xor - store MOVOU (0*16)(inp), D3; PXOR D3, A0 MOVOU (1*16)(inp), D3; PXOR D3, B0 MOVOU (2*16)(inp), D3; PXOR D3, C0 MOVOU (3*16)(inp), D3; PXOR D3, D0 MOVOU A0, (0*16)(oup) MOVOU B0, (1*16)(oup) MOVOU C0, (2*16)(oup) MOVOU D0, (3*16)(oup) MOVOU (4*16)(inp), A0; MOVOU (5*16)(inp), B0; MOVOU (6*16)(inp), C0; MOVOU (7*16)(inp), D0 PXOR A0, A1; PXOR B0, B1; PXOR C0, C1; PXOR D0, D1 MOVOU A1, (4*16)(oup); MOVOU B1, (5*16)(oup); MOVOU C1, (6*16)(oup); MOVOU D1, (7*16)(oup) MOVOU (8*16)(inp), A0; MOVOU (9*16)(inp), B0; MOVOU (10*16)(inp), C0; MOVOU (11*16)(inp), D0 PXOR A0, A2; PXOR B0, B2; PXOR C0, C2; PXOR D0, D2 MOVOU A2, (8*16)(oup); MOVOU B2, (9*16)(oup); MOVOU C2, (10*16)(oup); MOVOU D2, (11*16)(oup) LEAQ 192(inp), inp LEAQ 192(oup), oup SUBQ $192, inl MOVO A3, A0 MOVO B3, B0 MOVO C3, C0 MOVO tmpStore, D0 JMP openSSETail64DecLoop // ---------------------------------------------------------------------------- // ------------------------- AVX2 Code ---------------------------------------- chacha20Poly1305Open_AVX2: VZEROUPPER VMOVDQU ·chacha20Constants<>(SB), AA0 BYTE $0xc4; BYTE $0x42; BYTE $0x7d; BYTE $0x5a; BYTE $0x70; BYTE $0x10 // broadcasti128 16(r8), ymm14 BYTE $0xc4; BYTE $0x42; BYTE $0x7d; BYTE $0x5a; BYTE $0x60; BYTE $0x20 // broadcasti128 32(r8), ymm12 BYTE $0xc4; BYTE $0xc2; BYTE $0x7d; BYTE $0x5a; BYTE $0x60; BYTE $0x30 // broadcasti128 48(r8), ymm4 VPADDD ·avx2InitMask<>(SB), DD0, DD0 // Special optimization, for very short buffers CMPQ inl, $192 JBE openAVX2192 CMPQ inl, $320 JBE openAVX2320 // For the general key prepare the key first - as a byproduct we have 64 bytes of cipher stream VMOVDQA BB0, state1StoreAVX2 VMOVDQA CC0, state2StoreAVX2 VMOVDQA DD0, ctr3StoreAVX2 MOVQ $10, itr2 openAVX2PreparePolyKey: chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0) VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $12, DD0, DD0, DD0 chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0) VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $4, DD0, DD0, DD0 DECQ itr2 JNE openAVX2PreparePolyKey VPADDD ·chacha20Constants<>(SB), AA0, AA0 VPADDD state1StoreAVX2, BB0, BB0 VPADDD state2StoreAVX2, CC0, CC0 VPADDD ctr3StoreAVX2, DD0, DD0 VPERM2I128 $0x02, AA0, BB0, TT0 // Clamp and store poly key VPAND ·polyClampMask<>(SB), TT0, TT0 VMOVDQA TT0, rsStoreAVX2 // Stream for the first 64 bytes VPERM2I128 $0x13, AA0, BB0, AA0 VPERM2I128 $0x13, CC0, DD0, BB0 // Hash AD + first 64 bytes MOVQ ad_len+80(FP), itr2 CALL polyHashADInternal<>(SB) XORQ itr1, itr1 openAVX2InitialHash64: polyAdd(0(inp)(itr1*1)) polyMulAVX2 ADDQ $16, itr1 CMPQ itr1, $64 JNE openAVX2InitialHash64 // Decrypt the first 64 bytes VPXOR (0*32)(inp), AA0, AA0 VPXOR (1*32)(inp), BB0, BB0 VMOVDQU AA0, (0*32)(oup) VMOVDQU BB0, (1*32)(oup) LEAQ (2*32)(inp), inp LEAQ (2*32)(oup), oup SUBQ $64, inl openAVX2MainLoop: CMPQ inl, $512 JB openAVX2MainLoopDone // Load state, increment counter blocks, store the incremented counters VMOVDQU ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 VMOVDQA ctr3StoreAVX2, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 XORQ itr1, itr1 openAVX2InternalLoop: // Lets just say this spaghetti loop interleaves 2 quarter rounds with 3 poly multiplications // Effectively per 512 bytes of stream we hash 480 bytes of ciphertext polyAdd(0*8(inp)(itr1*1)) VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 polyMulStage1_AVX2 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 polyMulStage2_AVX2 VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 polyMulStage3_AVX2 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 polyMulReduceStage VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 polyAdd(2*8(inp)(itr1*1)) VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 polyMulStage1_AVX2 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 polyMulStage2_AVX2 VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $4, BB3, BB3, BB3 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2; VPALIGNR $12, DD3, DD3, DD3 VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 polyMulStage3_AVX2 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 polyMulReduceStage VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 polyAdd(4*8(inp)(itr1*1)) LEAQ (6*8)(itr1), itr1 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 polyMulStage1_AVX2 VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 polyMulStage2_AVX2 VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 polyMulStage3_AVX2 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 polyMulReduceStage VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $12, BB3, BB3, BB3 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2; VPALIGNR $4, DD3, DD3, DD3 CMPQ itr1, $480 JNE openAVX2InternalLoop VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 VMOVDQA CC3, tmpStoreAVX2 // We only hashed 480 of the 512 bytes available - hash the remaining 32 here polyAdd(480(inp)) polyMulAVX2 VPERM2I128 $0x02, AA0, BB0, CC3; VPERM2I128 $0x13, AA0, BB0, BB0; VPERM2I128 $0x02, CC0, DD0, AA0; VPERM2I128 $0x13, CC0, DD0, CC0 VPXOR (0*32)(inp), CC3, CC3; VPXOR (1*32)(inp), AA0, AA0; VPXOR (2*32)(inp), BB0, BB0; VPXOR (3*32)(inp), CC0, CC0 VMOVDQU CC3, (0*32)(oup); VMOVDQU AA0, (1*32)(oup); VMOVDQU BB0, (2*32)(oup); VMOVDQU CC0, (3*32)(oup) VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 VPXOR (4*32)(inp), AA0, AA0; VPXOR (5*32)(inp), BB0, BB0; VPXOR (6*32)(inp), CC0, CC0; VPXOR (7*32)(inp), DD0, DD0 VMOVDQU AA0, (4*32)(oup); VMOVDQU BB0, (5*32)(oup); VMOVDQU CC0, (6*32)(oup); VMOVDQU DD0, (7*32)(oup) // and here polyAdd(496(inp)) polyMulAVX2 VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 VPXOR (8*32)(inp), AA0, AA0; VPXOR (9*32)(inp), BB0, BB0; VPXOR (10*32)(inp), CC0, CC0; VPXOR (11*32)(inp), DD0, DD0 VMOVDQU AA0, (8*32)(oup); VMOVDQU BB0, (9*32)(oup); VMOVDQU CC0, (10*32)(oup); VMOVDQU DD0, (11*32)(oup) VPERM2I128 $0x02, AA3, BB3, AA0; VPERM2I128 $0x02, tmpStoreAVX2, DD3, BB0; VPERM2I128 $0x13, AA3, BB3, CC0; VPERM2I128 $0x13, tmpStoreAVX2, DD3, DD0 VPXOR (12*32)(inp), AA0, AA0; VPXOR (13*32)(inp), BB0, BB0; VPXOR (14*32)(inp), CC0, CC0; VPXOR (15*32)(inp), DD0, DD0 VMOVDQU AA0, (12*32)(oup); VMOVDQU BB0, (13*32)(oup); VMOVDQU CC0, (14*32)(oup); VMOVDQU DD0, (15*32)(oup) LEAQ (32*16)(inp), inp LEAQ (32*16)(oup), oup SUBQ $(32*16), inl JMP openAVX2MainLoop openAVX2MainLoopDone: // Handle the various tail sizes efficiently TESTQ inl, inl JE openSSEFinalize CMPQ inl, $128 JBE openAVX2Tail128 CMPQ inl, $256 JBE openAVX2Tail256 CMPQ inl, $384 JBE openAVX2Tail384 JMP openAVX2Tail512 // ---------------------------------------------------------------------------- // Special optimization for buffers smaller than 193 bytes openAVX2192: // For up to 192 bytes of ciphertext and 64 bytes for the poly key, we process four blocks VMOVDQA AA0, AA1 VMOVDQA BB0, BB1 VMOVDQA CC0, CC1 VPADDD ·avx2IncMask<>(SB), DD0, DD1 VMOVDQA AA0, AA2 VMOVDQA BB0, BB2 VMOVDQA CC0, CC2 VMOVDQA DD0, DD2 VMOVDQA DD1, TT3 MOVQ $10, itr2 openAVX2192InnerCipherLoop: chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1 chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1 DECQ itr2 JNE openAVX2192InnerCipherLoop VPADDD AA2, AA0, AA0; VPADDD AA2, AA1, AA1 VPADDD BB2, BB0, BB0; VPADDD BB2, BB1, BB1 VPADDD CC2, CC0, CC0; VPADDD CC2, CC1, CC1 VPADDD DD2, DD0, DD0; VPADDD TT3, DD1, DD1 VPERM2I128 $0x02, AA0, BB0, TT0 // Clamp and store poly key VPAND ·polyClampMask<>(SB), TT0, TT0 VMOVDQA TT0, rsStoreAVX2 // Stream for up to 192 bytes VPERM2I128 $0x13, AA0, BB0, AA0 VPERM2I128 $0x13, CC0, DD0, BB0 VPERM2I128 $0x02, AA1, BB1, CC0 VPERM2I128 $0x02, CC1, DD1, DD0 VPERM2I128 $0x13, AA1, BB1, AA1 VPERM2I128 $0x13, CC1, DD1, BB1 openAVX2ShortOpen: // Hash MOVQ ad_len+80(FP), itr2 CALL polyHashADInternal<>(SB) openAVX2ShortOpenLoop: CMPQ inl, $32 JB openAVX2ShortTail32 SUBQ $32, inl // Load for hashing polyAdd(0*8(inp)) polyMulAVX2 polyAdd(2*8(inp)) polyMulAVX2 // Load for decryption VPXOR (inp), AA0, AA0 VMOVDQU AA0, (oup) LEAQ (1*32)(inp), inp LEAQ (1*32)(oup), oup // Shift stream left VMOVDQA BB0, AA0 VMOVDQA CC0, BB0 VMOVDQA DD0, CC0 VMOVDQA AA1, DD0 VMOVDQA BB1, AA1 VMOVDQA CC1, BB1 VMOVDQA DD1, CC1 VMOVDQA AA2, DD1 VMOVDQA BB2, AA2 JMP openAVX2ShortOpenLoop openAVX2ShortTail32: CMPQ inl, $16 VMOVDQA A0, A1 JB openAVX2ShortDone SUBQ $16, inl // Load for hashing polyAdd(0*8(inp)) polyMulAVX2 // Load for decryption VPXOR (inp), A0, T0 VMOVDQU T0, (oup) LEAQ (1*16)(inp), inp LEAQ (1*16)(oup), oup VPERM2I128 $0x11, AA0, AA0, AA0 VMOVDQA A0, A1 openAVX2ShortDone: VZEROUPPER JMP openSSETail16 // ---------------------------------------------------------------------------- // Special optimization for buffers smaller than 321 bytes openAVX2320: // For up to 320 bytes of ciphertext and 64 bytes for the poly key, we process six blocks VMOVDQA AA0, AA1; VMOVDQA BB0, BB1; VMOVDQA CC0, CC1; VPADDD ·avx2IncMask<>(SB), DD0, DD1 VMOVDQA AA0, AA2; VMOVDQA BB0, BB2; VMOVDQA CC0, CC2; VPADDD ·avx2IncMask<>(SB), DD1, DD2 VMOVDQA BB0, TT1; VMOVDQA CC0, TT2; VMOVDQA DD0, TT3 MOVQ $10, itr2 openAVX2320InnerCipherLoop: chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2 chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2 DECQ itr2 JNE openAVX2320InnerCipherLoop VMOVDQA ·chacha20Constants<>(SB), TT0 VPADDD TT0, AA0, AA0; VPADDD TT0, AA1, AA1; VPADDD TT0, AA2, AA2 VPADDD TT1, BB0, BB0; VPADDD TT1, BB1, BB1; VPADDD TT1, BB2, BB2 VPADDD TT2, CC0, CC0; VPADDD TT2, CC1, CC1; VPADDD TT2, CC2, CC2 VMOVDQA ·avx2IncMask<>(SB), TT0 VPADDD TT3, DD0, DD0; VPADDD TT0, TT3, TT3 VPADDD TT3, DD1, DD1; VPADDD TT0, TT3, TT3 VPADDD TT3, DD2, DD2 // Clamp and store poly key VPERM2I128 $0x02, AA0, BB0, TT0 VPAND ·polyClampMask<>(SB), TT0, TT0 VMOVDQA TT0, rsStoreAVX2 // Stream for up to 320 bytes VPERM2I128 $0x13, AA0, BB0, AA0 VPERM2I128 $0x13, CC0, DD0, BB0 VPERM2I128 $0x02, AA1, BB1, CC0 VPERM2I128 $0x02, CC1, DD1, DD0 VPERM2I128 $0x13, AA1, BB1, AA1 VPERM2I128 $0x13, CC1, DD1, BB1 VPERM2I128 $0x02, AA2, BB2, CC1 VPERM2I128 $0x02, CC2, DD2, DD1 VPERM2I128 $0x13, AA2, BB2, AA2 VPERM2I128 $0x13, CC2, DD2, BB2 JMP openAVX2ShortOpen // ---------------------------------------------------------------------------- // Special optimization for the last 128 bytes of ciphertext openAVX2Tail128: // Need to decrypt up to 128 bytes - prepare two blocks VMOVDQA ·chacha20Constants<>(SB), AA1 VMOVDQA state1StoreAVX2, BB1 VMOVDQA state2StoreAVX2, CC1 VMOVDQA ctr3StoreAVX2, DD1 VPADDD ·avx2IncMask<>(SB), DD1, DD1 VMOVDQA DD1, DD0 XORQ itr2, itr2 MOVQ inl, itr1 ANDQ $-16, itr1 TESTQ itr1, itr1 JE openAVX2Tail128LoopB openAVX2Tail128LoopA: // Perform ChaCha rounds, while hashing the remaining input polyAdd(0(inp)(itr2*1)) polyMulAVX2 openAVX2Tail128LoopB: ADDQ $16, itr2 chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) VPALIGNR $4, BB1, BB1, BB1 VPALIGNR $8, CC1, CC1, CC1 VPALIGNR $12, DD1, DD1, DD1 chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) VPALIGNR $12, BB1, BB1, BB1 VPALIGNR $8, CC1, CC1, CC1 VPALIGNR $4, DD1, DD1, DD1 CMPQ itr2, itr1 JB openAVX2Tail128LoopA CMPQ itr2, $160 JNE openAVX2Tail128LoopB VPADDD ·chacha20Constants<>(SB), AA1, AA1 VPADDD state1StoreAVX2, BB1, BB1 VPADDD state2StoreAVX2, CC1, CC1 VPADDD DD0, DD1, DD1 VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 openAVX2TailLoop: CMPQ inl, $32 JB openAVX2Tail SUBQ $32, inl // Load for decryption VPXOR (inp), AA0, AA0 VMOVDQU AA0, (oup) LEAQ (1*32)(inp), inp LEAQ (1*32)(oup), oup VMOVDQA BB0, AA0 VMOVDQA CC0, BB0 VMOVDQA DD0, CC0 JMP openAVX2TailLoop openAVX2Tail: CMPQ inl, $16 VMOVDQA A0, A1 JB openAVX2TailDone SUBQ $16, inl // Load for decryption VPXOR (inp), A0, T0 VMOVDQU T0, (oup) LEAQ (1*16)(inp), inp LEAQ (1*16)(oup), oup VPERM2I128 $0x11, AA0, AA0, AA0 VMOVDQA A0, A1 openAVX2TailDone: VZEROUPPER JMP openSSETail16 // ---------------------------------------------------------------------------- // Special optimization for the last 256 bytes of ciphertext openAVX2Tail256: // Need to decrypt up to 256 bytes - prepare four blocks VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1 VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1 VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1 VMOVDQA ctr3StoreAVX2, DD0 VPADDD ·avx2IncMask<>(SB), DD0, DD0 VPADDD ·avx2IncMask<>(SB), DD0, DD1 VMOVDQA DD0, TT1 VMOVDQA DD1, TT2 // Compute the number of iterations that will hash data MOVQ inl, tmpStoreAVX2 MOVQ inl, itr1 SUBQ $128, itr1 SHRQ $4, itr1 MOVQ $10, itr2 CMPQ itr1, $10 CMOVQGT itr2, itr1 MOVQ inp, inl XORQ itr2, itr2 openAVX2Tail256LoopA: polyAdd(0(inl)) polyMulAVX2 LEAQ 16(inl), inl // Perform ChaCha rounds, while hashing the remaining input openAVX2Tail256LoopB: chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1 INCQ itr2 chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1 CMPQ itr2, itr1 JB openAVX2Tail256LoopA CMPQ itr2, $10 JNE openAVX2Tail256LoopB MOVQ inl, itr2 SUBQ inp, inl MOVQ inl, itr1 MOVQ tmpStoreAVX2, inl // Hash the remainder of data (if any) openAVX2Tail256Hash: ADDQ $16, itr1 CMPQ itr1, inl JGT openAVX2Tail256HashEnd polyAdd (0(itr2)) polyMulAVX2 LEAQ 16(itr2), itr2 JMP openAVX2Tail256Hash // Store 128 bytes safely, then go to store loop openAVX2Tail256HashEnd: VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1 VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1 VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1 VPADDD TT1, DD0, DD0; VPADDD TT2, DD1, DD1 VPERM2I128 $0x02, AA0, BB0, AA2; VPERM2I128 $0x02, CC0, DD0, BB2; VPERM2I128 $0x13, AA0, BB0, CC2; VPERM2I128 $0x13, CC0, DD0, DD2 VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 VPXOR (0*32)(inp), AA2, AA2; VPXOR (1*32)(inp), BB2, BB2; VPXOR (2*32)(inp), CC2, CC2; VPXOR (3*32)(inp), DD2, DD2 VMOVDQU AA2, (0*32)(oup); VMOVDQU BB2, (1*32)(oup); VMOVDQU CC2, (2*32)(oup); VMOVDQU DD2, (3*32)(oup) LEAQ (4*32)(inp), inp LEAQ (4*32)(oup), oup SUBQ $4*32, inl JMP openAVX2TailLoop // ---------------------------------------------------------------------------- // Special optimization for the last 384 bytes of ciphertext openAVX2Tail384: // Need to decrypt up to 384 bytes - prepare six blocks VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2 VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2 VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2 VMOVDQA ctr3StoreAVX2, DD0 VPADDD ·avx2IncMask<>(SB), DD0, DD0 VPADDD ·avx2IncMask<>(SB), DD0, DD1 VPADDD ·avx2IncMask<>(SB), DD1, DD2 VMOVDQA DD0, ctr0StoreAVX2 VMOVDQA DD1, ctr1StoreAVX2 VMOVDQA DD2, ctr2StoreAVX2 // Compute the number of iterations that will hash two blocks of data MOVQ inl, tmpStoreAVX2 MOVQ inl, itr1 SUBQ $256, itr1 SHRQ $4, itr1 ADDQ $6, itr1 MOVQ $10, itr2 CMPQ itr1, $10 CMOVQGT itr2, itr1 MOVQ inp, inl XORQ itr2, itr2 // Perform ChaCha rounds, while hashing the remaining input openAVX2Tail384LoopB: polyAdd(0(inl)) polyMulAVX2 LEAQ 16(inl), inl openAVX2Tail384LoopA: chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2 polyAdd(0(inl)) polyMulAVX2 LEAQ 16(inl), inl INCQ itr2 chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2 CMPQ itr2, itr1 JB openAVX2Tail384LoopB CMPQ itr2, $10 JNE openAVX2Tail384LoopA MOVQ inl, itr2 SUBQ inp, inl MOVQ inl, itr1 MOVQ tmpStoreAVX2, inl openAVX2Tail384Hash: ADDQ $16, itr1 CMPQ itr1, inl JGT openAVX2Tail384HashEnd polyAdd(0(itr2)) polyMulAVX2 LEAQ 16(itr2), itr2 JMP openAVX2Tail384Hash // Store 256 bytes safely, then go to store loop openAVX2Tail384HashEnd: VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2 VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2 VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2 VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2 VPERM2I128 $0x02, AA0, BB0, TT0; VPERM2I128 $0x02, CC0, DD0, TT1; VPERM2I128 $0x13, AA0, BB0, TT2; VPERM2I128 $0x13, CC0, DD0, TT3 VPXOR (0*32)(inp), TT0, TT0; VPXOR (1*32)(inp), TT1, TT1; VPXOR (2*32)(inp), TT2, TT2; VPXOR (3*32)(inp), TT3, TT3 VMOVDQU TT0, (0*32)(oup); VMOVDQU TT1, (1*32)(oup); VMOVDQU TT2, (2*32)(oup); VMOVDQU TT3, (3*32)(oup) VPERM2I128 $0x02, AA1, BB1, TT0; VPERM2I128 $0x02, CC1, DD1, TT1; VPERM2I128 $0x13, AA1, BB1, TT2; VPERM2I128 $0x13, CC1, DD1, TT3 VPXOR (4*32)(inp), TT0, TT0; VPXOR (5*32)(inp), TT1, TT1; VPXOR (6*32)(inp), TT2, TT2; VPXOR (7*32)(inp), TT3, TT3 VMOVDQU TT0, (4*32)(oup); VMOVDQU TT1, (5*32)(oup); VMOVDQU TT2, (6*32)(oup); VMOVDQU TT3, (7*32)(oup) VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 LEAQ (8*32)(inp), inp LEAQ (8*32)(oup), oup SUBQ $8*32, inl JMP openAVX2TailLoop // ---------------------------------------------------------------------------- // Special optimization for the last 512 bytes of ciphertext openAVX2Tail512: VMOVDQU ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 VMOVDQA ctr3StoreAVX2, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 XORQ itr1, itr1 MOVQ inp, itr2 openAVX2Tail512LoopB: polyAdd(0(itr2)) polyMulAVX2 LEAQ (2*8)(itr2), itr2 openAVX2Tail512LoopA: VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 polyAdd(0*8(itr2)) polyMulAVX2 VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $4, BB3, BB3, BB3 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2; VPALIGNR $12, DD3, DD3, DD3 VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 polyAdd(2*8(itr2)) polyMulAVX2 LEAQ (4*8)(itr2), itr2 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $12, BB3, BB3, BB3 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2; VPALIGNR $4, DD3, DD3, DD3 INCQ itr1 CMPQ itr1, $4 JLT openAVX2Tail512LoopB CMPQ itr1, $10 JNE openAVX2Tail512LoopA MOVQ inl, itr1 SUBQ $384, itr1 ANDQ $-16, itr1 openAVX2Tail512HashLoop: TESTQ itr1, itr1 JE openAVX2Tail512HashEnd polyAdd(0(itr2)) polyMulAVX2 LEAQ 16(itr2), itr2 SUBQ $16, itr1 JMP openAVX2Tail512HashLoop openAVX2Tail512HashEnd: VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 VMOVDQA CC3, tmpStoreAVX2 VPERM2I128 $0x02, AA0, BB0, CC3; VPERM2I128 $0x13, AA0, BB0, BB0; VPERM2I128 $0x02, CC0, DD0, AA0; VPERM2I128 $0x13, CC0, DD0, CC0 VPXOR (0*32)(inp), CC3, CC3; VPXOR (1*32)(inp), AA0, AA0; VPXOR (2*32)(inp), BB0, BB0; VPXOR (3*32)(inp), CC0, CC0 VMOVDQU CC3, (0*32)(oup); VMOVDQU AA0, (1*32)(oup); VMOVDQU BB0, (2*32)(oup); VMOVDQU CC0, (3*32)(oup) VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 VPXOR (4*32)(inp), AA0, AA0; VPXOR (5*32)(inp), BB0, BB0; VPXOR (6*32)(inp), CC0, CC0; VPXOR (7*32)(inp), DD0, DD0 VMOVDQU AA0, (4*32)(oup); VMOVDQU BB0, (5*32)(oup); VMOVDQU CC0, (6*32)(oup); VMOVDQU DD0, (7*32)(oup) VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 VPXOR (8*32)(inp), AA0, AA0; VPXOR (9*32)(inp), BB0, BB0; VPXOR (10*32)(inp), CC0, CC0; VPXOR (11*32)(inp), DD0, DD0 VMOVDQU AA0, (8*32)(oup); VMOVDQU BB0, (9*32)(oup); VMOVDQU CC0, (10*32)(oup); VMOVDQU DD0, (11*32)(oup) VPERM2I128 $0x02, AA3, BB3, AA0; VPERM2I128 $0x02, tmpStoreAVX2, DD3, BB0; VPERM2I128 $0x13, AA3, BB3, CC0; VPERM2I128 $0x13, tmpStoreAVX2, DD3, DD0 LEAQ (12*32)(inp), inp LEAQ (12*32)(oup), oup SUBQ $12*32, inl JMP openAVX2TailLoop // ---------------------------------------------------------------------------- // ---------------------------------------------------------------------------- // func chacha20Poly1305Seal(dst, key, src, ad []byte) TEXT ·chacha20Poly1305Seal(SB), 0, $288-96 // For aligned stack access MOVQ SP, BP ADDQ $32, BP ANDQ $-32, BP MOVQ dst+0(FP), oup MOVQ key+24(FP), keyp MOVQ src+48(FP), inp MOVQ src_len+56(FP), inl MOVQ ad+72(FP), adp CMPB ·useAVX2(SB), $1 JE chacha20Poly1305Seal_AVX2 // Special optimization, for very short buffers CMPQ inl, $128 JBE sealSSE128 // About 15% faster // In the seal case - prepare the poly key + 3 blocks of stream in the first iteration MOVOU ·chacha20Constants<>(SB), A0 MOVOU (1*16)(keyp), B0 MOVOU (2*16)(keyp), C0 MOVOU (3*16)(keyp), D0 // Store state on stack for future use MOVO B0, state1Store MOVO C0, state2Store // Load state, increment counter blocks MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 MOVO A2, A3; MOVO B2, B3; MOVO C2, C3; MOVO D2, D3; PADDL ·sseIncMask<>(SB), D3 // Store counters MOVO D0, ctr0Store; MOVO D1, ctr1Store; MOVO D2, ctr2Store; MOVO D3, ctr3Store MOVQ $10, itr2 sealSSEIntroLoop: MOVO C3, tmpStore chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) MOVO tmpStore, C3 MOVO C1, tmpStore chachaQR(A3, B3, C3, D3, C1) MOVO tmpStore, C1 shiftB0Left; shiftB1Left; shiftB2Left; shiftB3Left shiftC0Left; shiftC1Left; shiftC2Left; shiftC3Left shiftD0Left; shiftD1Left; shiftD2Left; shiftD3Left MOVO C3, tmpStore chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) MOVO tmpStore, C3 MOVO C1, tmpStore chachaQR(A3, B3, C3, D3, C1) MOVO tmpStore, C1 shiftB0Right; shiftB1Right; shiftB2Right; shiftB3Right shiftC0Right; shiftC1Right; shiftC2Right; shiftC3Right shiftD0Right; shiftD1Right; shiftD2Right; shiftD3Right DECQ itr2 JNE sealSSEIntroLoop // Add in the state PADDD ·chacha20Constants<>(SB), A0; PADDD ·chacha20Constants<>(SB), A1; PADDD ·chacha20Constants<>(SB), A2; PADDD ·chacha20Constants<>(SB), A3 PADDD state1Store, B0; PADDD state1Store, B1; PADDD state1Store, B2; PADDD state1Store, B3 PADDD state2Store, C1; PADDD state2Store, C2; PADDD state2Store, C3 PADDD ctr1Store, D1; PADDD ctr2Store, D2; PADDD ctr3Store, D3 // Clamp and store the key PAND ·polyClampMask<>(SB), A0 MOVO A0, rStore MOVO B0, sStore // Hash AAD MOVQ ad_len+80(FP), itr2 CALL polyHashADInternal<>(SB) MOVOU (0*16)(inp), A0; MOVOU (1*16)(inp), B0; MOVOU (2*16)(inp), C0; MOVOU (3*16)(inp), D0 PXOR A0, A1; PXOR B0, B1; PXOR C0, C1; PXOR D0, D1 MOVOU A1, (0*16)(oup); MOVOU B1, (1*16)(oup); MOVOU C1, (2*16)(oup); MOVOU D1, (3*16)(oup) MOVOU (4*16)(inp), A0; MOVOU (5*16)(inp), B0; MOVOU (6*16)(inp), C0; MOVOU (7*16)(inp), D0 PXOR A0, A2; PXOR B0, B2; PXOR C0, C2; PXOR D0, D2 MOVOU A2, (4*16)(oup); MOVOU B2, (5*16)(oup); MOVOU C2, (6*16)(oup); MOVOU D2, (7*16)(oup) MOVQ $128, itr1 SUBQ $128, inl LEAQ 128(inp), inp MOVO A3, A1; MOVO B3, B1; MOVO C3, C1; MOVO D3, D1 CMPQ inl, $64 JBE sealSSE128SealHash MOVOU (0*16)(inp), A0; MOVOU (1*16)(inp), B0; MOVOU (2*16)(inp), C0; MOVOU (3*16)(inp), D0 PXOR A0, A3; PXOR B0, B3; PXOR C0, C3; PXOR D0, D3 MOVOU A3, (8*16)(oup); MOVOU B3, (9*16)(oup); MOVOU C3, (10*16)(oup); MOVOU D3, (11*16)(oup) ADDQ $64, itr1 SUBQ $64, inl LEAQ 64(inp), inp MOVQ $2, itr1 MOVQ $8, itr2 CMPQ inl, $64 JBE sealSSETail64 CMPQ inl, $128 JBE sealSSETail128 CMPQ inl, $192 JBE sealSSETail192 sealSSEMainLoop: // Load state, increment counter blocks MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0 MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 MOVO A2, A3; MOVO B2, B3; MOVO C2, C3; MOVO D2, D3; PADDL ·sseIncMask<>(SB), D3 // Store counters MOVO D0, ctr0Store; MOVO D1, ctr1Store; MOVO D2, ctr2Store; MOVO D3, ctr3Store sealSSEInnerLoop: MOVO C3, tmpStore chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) MOVO tmpStore, C3 MOVO C1, tmpStore chachaQR(A3, B3, C3, D3, C1) MOVO tmpStore, C1 polyAdd(0(oup)) shiftB0Left; shiftB1Left; shiftB2Left; shiftB3Left shiftC0Left; shiftC1Left; shiftC2Left; shiftC3Left shiftD0Left; shiftD1Left; shiftD2Left; shiftD3Left polyMulStage1 polyMulStage2 LEAQ (2*8)(oup), oup MOVO C3, tmpStore chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) MOVO tmpStore, C3 MOVO C1, tmpStore polyMulStage3 chachaQR(A3, B3, C3, D3, C1) MOVO tmpStore, C1 polyMulReduceStage shiftB0Right; shiftB1Right; shiftB2Right; shiftB3Right shiftC0Right; shiftC1Right; shiftC2Right; shiftC3Right shiftD0Right; shiftD1Right; shiftD2Right; shiftD3Right DECQ itr2 JGE sealSSEInnerLoop polyAdd(0(oup)) polyMul LEAQ (2*8)(oup), oup DECQ itr1 JG sealSSEInnerLoop // Add in the state PADDD ·chacha20Constants<>(SB), A0; PADDD ·chacha20Constants<>(SB), A1; PADDD ·chacha20Constants<>(SB), A2; PADDD ·chacha20Constants<>(SB), A3 PADDD state1Store, B0; PADDD state1Store, B1; PADDD state1Store, B2; PADDD state1Store, B3 PADDD state2Store, C0; PADDD state2Store, C1; PADDD state2Store, C2; PADDD state2Store, C3 PADDD ctr0Store, D0; PADDD ctr1Store, D1; PADDD ctr2Store, D2; PADDD ctr3Store, D3 MOVO D3, tmpStore // Load - xor - store MOVOU (0*16)(inp), D3; PXOR D3, A0 MOVOU (1*16)(inp), D3; PXOR D3, B0 MOVOU (2*16)(inp), D3; PXOR D3, C0 MOVOU (3*16)(inp), D3; PXOR D3, D0 MOVOU A0, (0*16)(oup) MOVOU B0, (1*16)(oup) MOVOU C0, (2*16)(oup) MOVOU D0, (3*16)(oup) MOVO tmpStore, D3 MOVOU (4*16)(inp), A0; MOVOU (5*16)(inp), B0; MOVOU (6*16)(inp), C0; MOVOU (7*16)(inp), D0 PXOR A0, A1; PXOR B0, B1; PXOR C0, C1; PXOR D0, D1 MOVOU A1, (4*16)(oup); MOVOU B1, (5*16)(oup); MOVOU C1, (6*16)(oup); MOVOU D1, (7*16)(oup) MOVOU (8*16)(inp), A0; MOVOU (9*16)(inp), B0; MOVOU (10*16)(inp), C0; MOVOU (11*16)(inp), D0 PXOR A0, A2; PXOR B0, B2; PXOR C0, C2; PXOR D0, D2 MOVOU A2, (8*16)(oup); MOVOU B2, (9*16)(oup); MOVOU C2, (10*16)(oup); MOVOU D2, (11*16)(oup) ADDQ $192, inp MOVQ $192, itr1 SUBQ $192, inl MOVO A3, A1 MOVO B3, B1 MOVO C3, C1 MOVO D3, D1 CMPQ inl, $64 JBE sealSSE128SealHash MOVOU (0*16)(inp), A0; MOVOU (1*16)(inp), B0; MOVOU (2*16)(inp), C0; MOVOU (3*16)(inp), D0 PXOR A0, A3; PXOR B0, B3; PXOR C0, C3; PXOR D0, D3 MOVOU A3, (12*16)(oup); MOVOU B3, (13*16)(oup); MOVOU C3, (14*16)(oup); MOVOU D3, (15*16)(oup) LEAQ 64(inp), inp SUBQ $64, inl MOVQ $6, itr1 MOVQ $4, itr2 CMPQ inl, $192 JG sealSSEMainLoop MOVQ inl, itr1 TESTQ inl, inl JE sealSSE128SealHash MOVQ $6, itr1 CMPQ inl, $64 JBE sealSSETail64 CMPQ inl, $128 JBE sealSSETail128 JMP sealSSETail192 // ---------------------------------------------------------------------------- // Special optimization for the last 64 bytes of plaintext sealSSETail64: // Need to encrypt up to 64 bytes - prepare single block, hash 192 or 256 bytes MOVO ·chacha20Constants<>(SB), A1 MOVO state1Store, B1 MOVO state2Store, C1 MOVO ctr3Store, D1 PADDL ·sseIncMask<>(SB), D1 MOVO D1, ctr0Store sealSSETail64LoopA: // Perform ChaCha rounds, while hashing the previously encrypted ciphertext polyAdd(0(oup)) polyMul LEAQ 16(oup), oup sealSSETail64LoopB: chachaQR(A1, B1, C1, D1, T1) shiftB1Left; shiftC1Left; shiftD1Left chachaQR(A1, B1, C1, D1, T1) shiftB1Right; shiftC1Right; shiftD1Right polyAdd(0(oup)) polyMul LEAQ 16(oup), oup DECQ itr1 JG sealSSETail64LoopA DECQ itr2 JGE sealSSETail64LoopB PADDL ·chacha20Constants<>(SB), A1 PADDL state1Store, B1 PADDL state2Store, C1 PADDL ctr0Store, D1 JMP sealSSE128Seal // ---------------------------------------------------------------------------- // Special optimization for the last 128 bytes of plaintext sealSSETail128: // Need to encrypt up to 128 bytes - prepare two blocks, hash 192 or 256 bytes MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr0Store MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1; MOVO D1, ctr1Store sealSSETail128LoopA: // Perform ChaCha rounds, while hashing the previously encrypted ciphertext polyAdd(0(oup)) polyMul LEAQ 16(oup), oup sealSSETail128LoopB: chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0) shiftB0Left; shiftC0Left; shiftD0Left shiftB1Left; shiftC1Left; shiftD1Left polyAdd(0(oup)) polyMul LEAQ 16(oup), oup chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0) shiftB0Right; shiftC0Right; shiftD0Right shiftB1Right; shiftC1Right; shiftD1Right DECQ itr1 JG sealSSETail128LoopA DECQ itr2 JGE sealSSETail128LoopB PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1 PADDL state1Store, B0; PADDL state1Store, B1 PADDL state2Store, C0; PADDL state2Store, C1 PADDL ctr0Store, D0; PADDL ctr1Store, D1 MOVOU (0*16)(inp), T0; MOVOU (1*16)(inp), T1; MOVOU (2*16)(inp), T2; MOVOU (3*16)(inp), T3 PXOR T0, A0; PXOR T1, B0; PXOR T2, C0; PXOR T3, D0 MOVOU A0, (0*16)(oup); MOVOU B0, (1*16)(oup); MOVOU C0, (2*16)(oup); MOVOU D0, (3*16)(oup) MOVQ $64, itr1 LEAQ 64(inp), inp SUBQ $64, inl JMP sealSSE128SealHash // ---------------------------------------------------------------------------- // Special optimization for the last 192 bytes of plaintext sealSSETail192: // Need to encrypt up to 192 bytes - prepare three blocks, hash 192 or 256 bytes MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr0Store MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1; MOVO D1, ctr1Store MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2; MOVO D2, ctr2Store sealSSETail192LoopA: // Perform ChaCha rounds, while hashing the previously encrypted ciphertext polyAdd(0(oup)) polyMul LEAQ 16(oup), oup sealSSETail192LoopB: chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) shiftB0Left; shiftC0Left; shiftD0Left shiftB1Left; shiftC1Left; shiftD1Left shiftB2Left; shiftC2Left; shiftD2Left polyAdd(0(oup)) polyMul LEAQ 16(oup), oup chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) shiftB0Right; shiftC0Right; shiftD0Right shiftB1Right; shiftC1Right; shiftD1Right shiftB2Right; shiftC2Right; shiftD2Right DECQ itr1 JG sealSSETail192LoopA DECQ itr2 JGE sealSSETail192LoopB PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1; PADDL ·chacha20Constants<>(SB), A2 PADDL state1Store, B0; PADDL state1Store, B1; PADDL state1Store, B2 PADDL state2Store, C0; PADDL state2Store, C1; PADDL state2Store, C2 PADDL ctr0Store, D0; PADDL ctr1Store, D1; PADDL ctr2Store, D2 MOVOU (0*16)(inp), T0; MOVOU (1*16)(inp), T1; MOVOU (2*16)(inp), T2; MOVOU (3*16)(inp), T3 PXOR T0, A0; PXOR T1, B0; PXOR T2, C0; PXOR T3, D0 MOVOU A0, (0*16)(oup); MOVOU B0, (1*16)(oup); MOVOU C0, (2*16)(oup); MOVOU D0, (3*16)(oup) MOVOU (4*16)(inp), T0; MOVOU (5*16)(inp), T1; MOVOU (6*16)(inp), T2; MOVOU (7*16)(inp), T3 PXOR T0, A1; PXOR T1, B1; PXOR T2, C1; PXOR T3, D1 MOVOU A1, (4*16)(oup); MOVOU B1, (5*16)(oup); MOVOU C1, (6*16)(oup); MOVOU D1, (7*16)(oup) MOVO A2, A1 MOVO B2, B1 MOVO C2, C1 MOVO D2, D1 MOVQ $128, itr1 LEAQ 128(inp), inp SUBQ $128, inl JMP sealSSE128SealHash // ---------------------------------------------------------------------------- // Special seal optimization for buffers smaller than 129 bytes sealSSE128: // For up to 128 bytes of ciphertext and 64 bytes for the poly key, we require to process three blocks MOVOU ·chacha20Constants<>(SB), A0; MOVOU (1*16)(keyp), B0; MOVOU (2*16)(keyp), C0; MOVOU (3*16)(keyp), D0 MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 MOVO B0, T1; MOVO C0, T2; MOVO D1, T3 MOVQ $10, itr2 sealSSE128InnerCipherLoop: chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) shiftB0Left; shiftB1Left; shiftB2Left shiftC0Left; shiftC1Left; shiftC2Left shiftD0Left; shiftD1Left; shiftD2Left chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) shiftB0Right; shiftB1Right; shiftB2Right shiftC0Right; shiftC1Right; shiftC2Right shiftD0Right; shiftD1Right; shiftD2Right DECQ itr2 JNE sealSSE128InnerCipherLoop // A0|B0 hold the Poly1305 32-byte key, C0,D0 can be discarded PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1; PADDL ·chacha20Constants<>(SB), A2 PADDL T1, B0; PADDL T1, B1; PADDL T1, B2 PADDL T2, C1; PADDL T2, C2 PADDL T3, D1; PADDL ·sseIncMask<>(SB), T3; PADDL T3, D2 PAND ·polyClampMask<>(SB), A0 MOVOU A0, rStore MOVOU B0, sStore // Hash MOVQ ad_len+80(FP), itr2 CALL polyHashADInternal<>(SB) XORQ itr1, itr1 sealSSE128SealHash: // itr1 holds the number of bytes encrypted but not yet hashed CMPQ itr1, $16 JB sealSSE128Seal polyAdd(0(oup)) polyMul SUBQ $16, itr1 ADDQ $16, oup JMP sealSSE128SealHash sealSSE128Seal: CMPQ inl, $16 JB sealSSETail SUBQ $16, inl // Load for decryption MOVOU (inp), T0 PXOR T0, A1 MOVOU A1, (oup) LEAQ (1*16)(inp), inp LEAQ (1*16)(oup), oup // Extract for hashing MOVQ A1, t0 PSRLDQ $8, A1 MOVQ A1, t1 ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $1, acc2 polyMul // Shift the stream "left" MOVO B1, A1 MOVO C1, B1 MOVO D1, C1 MOVO A2, D1 MOVO B2, A2 MOVO C2, B2 MOVO D2, C2 JMP sealSSE128Seal sealSSETail: TESTQ inl, inl JE sealSSEFinalize // We can only load the PT one byte at a time to avoid read after end of buffer MOVQ inl, itr2 SHLQ $4, itr2 LEAQ ·andMask<>(SB), t0 MOVQ inl, itr1 LEAQ -1(inp)(inl*1), inp XORQ t2, t2 XORQ t3, t3 XORQ AX, AX sealSSETailLoadLoop: SHLQ $8, t2, t3 SHLQ $8, t2 MOVB (inp), AX XORQ AX, t2 LEAQ -1(inp), inp DECQ itr1 JNE sealSSETailLoadLoop MOVQ t2, 0+tmpStore MOVQ t3, 8+tmpStore PXOR 0+tmpStore, A1 MOVOU A1, (oup) MOVOU -16(t0)(itr2*1), T0 PAND T0, A1 MOVQ A1, t0 PSRLDQ $8, A1 MOVQ A1, t1 ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $1, acc2 polyMul ADDQ inl, oup sealSSEFinalize: // Hash in the buffer lengths ADDQ ad_len+80(FP), acc0 ADCQ src_len+56(FP), acc1 ADCQ $1, acc2 polyMul // Final reduce MOVQ acc0, t0 MOVQ acc1, t1 MOVQ acc2, t2 SUBQ $-5, acc0 SBBQ $-1, acc1 SBBQ $3, acc2 CMOVQCS t0, acc0 CMOVQCS t1, acc1 CMOVQCS t2, acc2 // Add in the "s" part of the key ADDQ 0+sStore, acc0 ADCQ 8+sStore, acc1 // Finally store the tag at the end of the message MOVQ acc0, (0*8)(oup) MOVQ acc1, (1*8)(oup) RET // ---------------------------------------------------------------------------- // ------------------------- AVX2 Code ---------------------------------------- chacha20Poly1305Seal_AVX2: VZEROUPPER VMOVDQU ·chacha20Constants<>(SB), AA0 BYTE $0xc4; BYTE $0x42; BYTE $0x7d; BYTE $0x5a; BYTE $0x70; BYTE $0x10 // broadcasti128 16(r8), ymm14 BYTE $0xc4; BYTE $0x42; BYTE $0x7d; BYTE $0x5a; BYTE $0x60; BYTE $0x20 // broadcasti128 32(r8), ymm12 BYTE $0xc4; BYTE $0xc2; BYTE $0x7d; BYTE $0x5a; BYTE $0x60; BYTE $0x30 // broadcasti128 48(r8), ymm4 VPADDD ·avx2InitMask<>(SB), DD0, DD0 // Special optimizations, for very short buffers CMPQ inl, $192 JBE seal192AVX2 // 33% faster CMPQ inl, $320 JBE seal320AVX2 // 17% faster // For the general key prepare the key first - as a byproduct we have 64 bytes of cipher stream VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3; VMOVDQA BB0, state1StoreAVX2 VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3; VMOVDQA CC0, state2StoreAVX2 VPADDD ·avx2IncMask<>(SB), DD0, DD1; VMOVDQA DD0, ctr0StoreAVX2 VPADDD ·avx2IncMask<>(SB), DD1, DD2; VMOVDQA DD1, ctr1StoreAVX2 VPADDD ·avx2IncMask<>(SB), DD2, DD3; VMOVDQA DD2, ctr2StoreAVX2 VMOVDQA DD3, ctr3StoreAVX2 MOVQ $10, itr2 sealAVX2IntroLoop: VMOVDQA CC3, tmpStoreAVX2 chachaQR_AVX2(AA0, BB0, CC0, DD0, CC3); chachaQR_AVX2(AA1, BB1, CC1, DD1, CC3); chachaQR_AVX2(AA2, BB2, CC2, DD2, CC3) VMOVDQA tmpStoreAVX2, CC3 VMOVDQA CC1, tmpStoreAVX2 chachaQR_AVX2(AA3, BB3, CC3, DD3, CC1) VMOVDQA tmpStoreAVX2, CC1 VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $12, DD0, DD0, DD0 VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $12, DD1, DD1, DD1 VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $12, DD2, DD2, DD2 VPALIGNR $4, BB3, BB3, BB3; VPALIGNR $8, CC3, CC3, CC3; VPALIGNR $12, DD3, DD3, DD3 VMOVDQA CC3, tmpStoreAVX2 chachaQR_AVX2(AA0, BB0, CC0, DD0, CC3); chachaQR_AVX2(AA1, BB1, CC1, DD1, CC3); chachaQR_AVX2(AA2, BB2, CC2, DD2, CC3) VMOVDQA tmpStoreAVX2, CC3 VMOVDQA CC1, tmpStoreAVX2 chachaQR_AVX2(AA3, BB3, CC3, DD3, CC1) VMOVDQA tmpStoreAVX2, CC1 VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $4, DD0, DD0, DD0 VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $4, DD1, DD1, DD1 VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $4, DD2, DD2, DD2 VPALIGNR $12, BB3, BB3, BB3; VPALIGNR $8, CC3, CC3, CC3; VPALIGNR $4, DD3, DD3, DD3 DECQ itr2 JNE sealAVX2IntroLoop VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 VPERM2I128 $0x13, CC0, DD0, CC0 // Stream bytes 96 - 127 VPERM2I128 $0x02, AA0, BB0, DD0 // The Poly1305 key VPERM2I128 $0x13, AA0, BB0, AA0 // Stream bytes 64 - 95 // Clamp and store poly key VPAND ·polyClampMask<>(SB), DD0, DD0 VMOVDQA DD0, rsStoreAVX2 // Hash AD MOVQ ad_len+80(FP), itr2 CALL polyHashADInternal<>(SB) // Can store at least 320 bytes VPXOR (0*32)(inp), AA0, AA0 VPXOR (1*32)(inp), CC0, CC0 VMOVDQU AA0, (0*32)(oup) VMOVDQU CC0, (1*32)(oup) VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 VPXOR (2*32)(inp), AA0, AA0; VPXOR (3*32)(inp), BB0, BB0; VPXOR (4*32)(inp), CC0, CC0; VPXOR (5*32)(inp), DD0, DD0 VMOVDQU AA0, (2*32)(oup); VMOVDQU BB0, (3*32)(oup); VMOVDQU CC0, (4*32)(oup); VMOVDQU DD0, (5*32)(oup) VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 VPXOR (6*32)(inp), AA0, AA0; VPXOR (7*32)(inp), BB0, BB0; VPXOR (8*32)(inp), CC0, CC0; VPXOR (9*32)(inp), DD0, DD0 VMOVDQU AA0, (6*32)(oup); VMOVDQU BB0, (7*32)(oup); VMOVDQU CC0, (8*32)(oup); VMOVDQU DD0, (9*32)(oup) MOVQ $320, itr1 SUBQ $320, inl LEAQ 320(inp), inp VPERM2I128 $0x02, AA3, BB3, AA0; VPERM2I128 $0x02, CC3, DD3, BB0; VPERM2I128 $0x13, AA3, BB3, CC0; VPERM2I128 $0x13, CC3, DD3, DD0 CMPQ inl, $128 JBE sealAVX2SealHash VPXOR (0*32)(inp), AA0, AA0; VPXOR (1*32)(inp), BB0, BB0; VPXOR (2*32)(inp), CC0, CC0; VPXOR (3*32)(inp), DD0, DD0 VMOVDQU AA0, (10*32)(oup); VMOVDQU BB0, (11*32)(oup); VMOVDQU CC0, (12*32)(oup); VMOVDQU DD0, (13*32)(oup) SUBQ $128, inl LEAQ 128(inp), inp MOVQ $8, itr1 MOVQ $2, itr2 CMPQ inl, $128 JBE sealAVX2Tail128 CMPQ inl, $256 JBE sealAVX2Tail256 CMPQ inl, $384 JBE sealAVX2Tail384 CMPQ inl, $512 JBE sealAVX2Tail512 // We have 448 bytes to hash, but main loop hashes 512 bytes at a time - perform some rounds, before the main loop VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 VMOVDQA ctr3StoreAVX2, DD0 VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 VMOVDQA CC3, tmpStoreAVX2 chachaQR_AVX2(AA0, BB0, CC0, DD0, CC3); chachaQR_AVX2(AA1, BB1, CC1, DD1, CC3); chachaQR_AVX2(AA2, BB2, CC2, DD2, CC3) VMOVDQA tmpStoreAVX2, CC3 VMOVDQA CC1, tmpStoreAVX2 chachaQR_AVX2(AA3, BB3, CC3, DD3, CC1) VMOVDQA tmpStoreAVX2, CC1 VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $12, DD0, DD0, DD0 VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $12, DD1, DD1, DD1 VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $12, DD2, DD2, DD2 VPALIGNR $4, BB3, BB3, BB3; VPALIGNR $8, CC3, CC3, CC3; VPALIGNR $12, DD3, DD3, DD3 VMOVDQA CC3, tmpStoreAVX2 chachaQR_AVX2(AA0, BB0, CC0, DD0, CC3); chachaQR_AVX2(AA1, BB1, CC1, DD1, CC3); chachaQR_AVX2(AA2, BB2, CC2, DD2, CC3) VMOVDQA tmpStoreAVX2, CC3 VMOVDQA CC1, tmpStoreAVX2 chachaQR_AVX2(AA3, BB3, CC3, DD3, CC1) VMOVDQA tmpStoreAVX2, CC1 VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $4, DD0, DD0, DD0 VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $4, DD1, DD1, DD1 VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $4, DD2, DD2, DD2 VPALIGNR $12, BB3, BB3, BB3; VPALIGNR $8, CC3, CC3, CC3; VPALIGNR $4, DD3, DD3, DD3 VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 SUBQ $16, oup // Adjust the pointer MOVQ $9, itr1 JMP sealAVX2InternalLoopStart sealAVX2MainLoop: // Load state, increment counter blocks, store the incremented counters VMOVDQU ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 VMOVDQA ctr3StoreAVX2, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 MOVQ $10, itr1 sealAVX2InternalLoop: polyAdd(0*8(oup)) VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 polyMulStage1_AVX2 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 polyMulStage2_AVX2 VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 polyMulStage3_AVX2 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 polyMulReduceStage sealAVX2InternalLoopStart: VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 polyAdd(2*8(oup)) VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 polyMulStage1_AVX2 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 polyMulStage2_AVX2 VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $4, BB3, BB3, BB3 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2; VPALIGNR $12, DD3, DD3, DD3 VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 polyMulStage3_AVX2 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 polyMulReduceStage VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 polyAdd(4*8(oup)) LEAQ (6*8)(oup), oup VMOVDQA CC3, tmpStoreAVX2 VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 polyMulStage1_AVX2 VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 polyMulStage2_AVX2 VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 polyMulStage3_AVX2 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 polyMulReduceStage VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $12, BB3, BB3, BB3 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2; VPALIGNR $4, DD3, DD3, DD3 DECQ itr1 JNE sealAVX2InternalLoop VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 VMOVDQA CC3, tmpStoreAVX2 // We only hashed 480 of the 512 bytes available - hash the remaining 32 here polyAdd(0*8(oup)) polyMulAVX2 LEAQ (4*8)(oup), oup VPERM2I128 $0x02, AA0, BB0, CC3; VPERM2I128 $0x13, AA0, BB0, BB0; VPERM2I128 $0x02, CC0, DD0, AA0; VPERM2I128 $0x13, CC0, DD0, CC0 VPXOR (0*32)(inp), CC3, CC3; VPXOR (1*32)(inp), AA0, AA0; VPXOR (2*32)(inp), BB0, BB0; VPXOR (3*32)(inp), CC0, CC0 VMOVDQU CC3, (0*32)(oup); VMOVDQU AA0, (1*32)(oup); VMOVDQU BB0, (2*32)(oup); VMOVDQU CC0, (3*32)(oup) VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 VPXOR (4*32)(inp), AA0, AA0; VPXOR (5*32)(inp), BB0, BB0; VPXOR (6*32)(inp), CC0, CC0; VPXOR (7*32)(inp), DD0, DD0 VMOVDQU AA0, (4*32)(oup); VMOVDQU BB0, (5*32)(oup); VMOVDQU CC0, (6*32)(oup); VMOVDQU DD0, (7*32)(oup) // and here polyAdd(-2*8(oup)) polyMulAVX2 VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 VPXOR (8*32)(inp), AA0, AA0; VPXOR (9*32)(inp), BB0, BB0; VPXOR (10*32)(inp), CC0, CC0; VPXOR (11*32)(inp), DD0, DD0 VMOVDQU AA0, (8*32)(oup); VMOVDQU BB0, (9*32)(oup); VMOVDQU CC0, (10*32)(oup); VMOVDQU DD0, (11*32)(oup) VPERM2I128 $0x02, AA3, BB3, AA0; VPERM2I128 $0x02, tmpStoreAVX2, DD3, BB0; VPERM2I128 $0x13, AA3, BB3, CC0; VPERM2I128 $0x13, tmpStoreAVX2, DD3, DD0 VPXOR (12*32)(inp), AA0, AA0; VPXOR (13*32)(inp), BB0, BB0; VPXOR (14*32)(inp), CC0, CC0; VPXOR (15*32)(inp), DD0, DD0 VMOVDQU AA0, (12*32)(oup); VMOVDQU BB0, (13*32)(oup); VMOVDQU CC0, (14*32)(oup); VMOVDQU DD0, (15*32)(oup) LEAQ (32*16)(inp), inp SUBQ $(32*16), inl CMPQ inl, $512 JG sealAVX2MainLoop // Tail can only hash 480 bytes polyAdd(0*8(oup)) polyMulAVX2 polyAdd(2*8(oup)) polyMulAVX2 LEAQ 32(oup), oup MOVQ $10, itr1 MOVQ $0, itr2 CMPQ inl, $128 JBE sealAVX2Tail128 CMPQ inl, $256 JBE sealAVX2Tail256 CMPQ inl, $384 JBE sealAVX2Tail384 JMP sealAVX2Tail512 // ---------------------------------------------------------------------------- // Special optimization for buffers smaller than 193 bytes seal192AVX2: // For up to 192 bytes of ciphertext and 64 bytes for the poly key, we process four blocks VMOVDQA AA0, AA1 VMOVDQA BB0, BB1 VMOVDQA CC0, CC1 VPADDD ·avx2IncMask<>(SB), DD0, DD1 VMOVDQA AA0, AA2 VMOVDQA BB0, BB2 VMOVDQA CC0, CC2 VMOVDQA DD0, DD2 VMOVDQA DD1, TT3 MOVQ $10, itr2 sealAVX2192InnerCipherLoop: chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1 chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1 DECQ itr2 JNE sealAVX2192InnerCipherLoop VPADDD AA2, AA0, AA0; VPADDD AA2, AA1, AA1 VPADDD BB2, BB0, BB0; VPADDD BB2, BB1, BB1 VPADDD CC2, CC0, CC0; VPADDD CC2, CC1, CC1 VPADDD DD2, DD0, DD0; VPADDD TT3, DD1, DD1 VPERM2I128 $0x02, AA0, BB0, TT0 // Clamp and store poly key VPAND ·polyClampMask<>(SB), TT0, TT0 VMOVDQA TT0, rsStoreAVX2 // Stream for up to 192 bytes VPERM2I128 $0x13, AA0, BB0, AA0 VPERM2I128 $0x13, CC0, DD0, BB0 VPERM2I128 $0x02, AA1, BB1, CC0 VPERM2I128 $0x02, CC1, DD1, DD0 VPERM2I128 $0x13, AA1, BB1, AA1 VPERM2I128 $0x13, CC1, DD1, BB1 sealAVX2ShortSeal: // Hash aad MOVQ ad_len+80(FP), itr2 CALL polyHashADInternal<>(SB) XORQ itr1, itr1 sealAVX2SealHash: // itr1 holds the number of bytes encrypted but not yet hashed CMPQ itr1, $16 JB sealAVX2ShortSealLoop polyAdd(0(oup)) polyMul SUBQ $16, itr1 ADDQ $16, oup JMP sealAVX2SealHash sealAVX2ShortSealLoop: CMPQ inl, $32 JB sealAVX2ShortTail32 SUBQ $32, inl // Load for encryption VPXOR (inp), AA0, AA0 VMOVDQU AA0, (oup) LEAQ (1*32)(inp), inp // Now can hash polyAdd(0*8(oup)) polyMulAVX2 polyAdd(2*8(oup)) polyMulAVX2 LEAQ (1*32)(oup), oup // Shift stream left VMOVDQA BB0, AA0 VMOVDQA CC0, BB0 VMOVDQA DD0, CC0 VMOVDQA AA1, DD0 VMOVDQA BB1, AA1 VMOVDQA CC1, BB1 VMOVDQA DD1, CC1 VMOVDQA AA2, DD1 VMOVDQA BB2, AA2 JMP sealAVX2ShortSealLoop sealAVX2ShortTail32: CMPQ inl, $16 VMOVDQA A0, A1 JB sealAVX2ShortDone SUBQ $16, inl // Load for encryption VPXOR (inp), A0, T0 VMOVDQU T0, (oup) LEAQ (1*16)(inp), inp // Hash polyAdd(0*8(oup)) polyMulAVX2 LEAQ (1*16)(oup), oup VPERM2I128 $0x11, AA0, AA0, AA0 VMOVDQA A0, A1 sealAVX2ShortDone: VZEROUPPER JMP sealSSETail // ---------------------------------------------------------------------------- // Special optimization for buffers smaller than 321 bytes seal320AVX2: // For up to 320 bytes of ciphertext and 64 bytes for the poly key, we process six blocks VMOVDQA AA0, AA1; VMOVDQA BB0, BB1; VMOVDQA CC0, CC1; VPADDD ·avx2IncMask<>(SB), DD0, DD1 VMOVDQA AA0, AA2; VMOVDQA BB0, BB2; VMOVDQA CC0, CC2; VPADDD ·avx2IncMask<>(SB), DD1, DD2 VMOVDQA BB0, TT1; VMOVDQA CC0, TT2; VMOVDQA DD0, TT3 MOVQ $10, itr2 sealAVX2320InnerCipherLoop: chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2 chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2 DECQ itr2 JNE sealAVX2320InnerCipherLoop VMOVDQA ·chacha20Constants<>(SB), TT0 VPADDD TT0, AA0, AA0; VPADDD TT0, AA1, AA1; VPADDD TT0, AA2, AA2 VPADDD TT1, BB0, BB0; VPADDD TT1, BB1, BB1; VPADDD TT1, BB2, BB2 VPADDD TT2, CC0, CC0; VPADDD TT2, CC1, CC1; VPADDD TT2, CC2, CC2 VMOVDQA ·avx2IncMask<>(SB), TT0 VPADDD TT3, DD0, DD0; VPADDD TT0, TT3, TT3 VPADDD TT3, DD1, DD1; VPADDD TT0, TT3, TT3 VPADDD TT3, DD2, DD2 // Clamp and store poly key VPERM2I128 $0x02, AA0, BB0, TT0 VPAND ·polyClampMask<>(SB), TT0, TT0 VMOVDQA TT0, rsStoreAVX2 // Stream for up to 320 bytes VPERM2I128 $0x13, AA0, BB0, AA0 VPERM2I128 $0x13, CC0, DD0, BB0 VPERM2I128 $0x02, AA1, BB1, CC0 VPERM2I128 $0x02, CC1, DD1, DD0 VPERM2I128 $0x13, AA1, BB1, AA1 VPERM2I128 $0x13, CC1, DD1, BB1 VPERM2I128 $0x02, AA2, BB2, CC1 VPERM2I128 $0x02, CC2, DD2, DD1 VPERM2I128 $0x13, AA2, BB2, AA2 VPERM2I128 $0x13, CC2, DD2, BB2 JMP sealAVX2ShortSeal // ---------------------------------------------------------------------------- // Special optimization for the last 128 bytes of ciphertext sealAVX2Tail128: // Need to decrypt up to 128 bytes - prepare two blocks // If we got here after the main loop - there are 512 encrypted bytes waiting to be hashed // If we got here before the main loop - there are 448 encrpyred bytes waiting to be hashed VMOVDQA ·chacha20Constants<>(SB), AA0 VMOVDQA state1StoreAVX2, BB0 VMOVDQA state2StoreAVX2, CC0 VMOVDQA ctr3StoreAVX2, DD0 VPADDD ·avx2IncMask<>(SB), DD0, DD0 VMOVDQA DD0, DD1 sealAVX2Tail128LoopA: polyAdd(0(oup)) polyMul LEAQ 16(oup), oup sealAVX2Tail128LoopB: chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0) polyAdd(0(oup)) polyMul VPALIGNR $4, BB0, BB0, BB0 VPALIGNR $8, CC0, CC0, CC0 VPALIGNR $12, DD0, DD0, DD0 chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0) polyAdd(16(oup)) polyMul LEAQ 32(oup), oup VPALIGNR $12, BB0, BB0, BB0 VPALIGNR $8, CC0, CC0, CC0 VPALIGNR $4, DD0, DD0, DD0 DECQ itr1 JG sealAVX2Tail128LoopA DECQ itr2 JGE sealAVX2Tail128LoopB VPADDD ·chacha20Constants<>(SB), AA0, AA1 VPADDD state1StoreAVX2, BB0, BB1 VPADDD state2StoreAVX2, CC0, CC1 VPADDD DD1, DD0, DD1 VPERM2I128 $0x02, AA1, BB1, AA0 VPERM2I128 $0x02, CC1, DD1, BB0 VPERM2I128 $0x13, AA1, BB1, CC0 VPERM2I128 $0x13, CC1, DD1, DD0 JMP sealAVX2ShortSealLoop // ---------------------------------------------------------------------------- // Special optimization for the last 256 bytes of ciphertext sealAVX2Tail256: // Need to decrypt up to 256 bytes - prepare two blocks // If we got here after the main loop - there are 512 encrypted bytes waiting to be hashed // If we got here before the main loop - there are 448 encrpyred bytes waiting to be hashed VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA ·chacha20Constants<>(SB), AA1 VMOVDQA state1StoreAVX2, BB0; VMOVDQA state1StoreAVX2, BB1 VMOVDQA state2StoreAVX2, CC0; VMOVDQA state2StoreAVX2, CC1 VMOVDQA ctr3StoreAVX2, DD0 VPADDD ·avx2IncMask<>(SB), DD0, DD0 VPADDD ·avx2IncMask<>(SB), DD0, DD1 VMOVDQA DD0, TT1 VMOVDQA DD1, TT2 sealAVX2Tail256LoopA: polyAdd(0(oup)) polyMul LEAQ 16(oup), oup sealAVX2Tail256LoopB: chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) polyAdd(0(oup)) polyMul VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1 chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) polyAdd(16(oup)) polyMul LEAQ 32(oup), oup VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1 DECQ itr1 JG sealAVX2Tail256LoopA DECQ itr2 JGE sealAVX2Tail256LoopB VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1 VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1 VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1 VPADDD TT1, DD0, DD0; VPADDD TT2, DD1, DD1 VPERM2I128 $0x02, AA0, BB0, TT0 VPERM2I128 $0x02, CC0, DD0, TT1 VPERM2I128 $0x13, AA0, BB0, TT2 VPERM2I128 $0x13, CC0, DD0, TT3 VPXOR (0*32)(inp), TT0, TT0; VPXOR (1*32)(inp), TT1, TT1; VPXOR (2*32)(inp), TT2, TT2; VPXOR (3*32)(inp), TT3, TT3 VMOVDQU TT0, (0*32)(oup); VMOVDQU TT1, (1*32)(oup); VMOVDQU TT2, (2*32)(oup); VMOVDQU TT3, (3*32)(oup) MOVQ $128, itr1 LEAQ 128(inp), inp SUBQ $128, inl VPERM2I128 $0x02, AA1, BB1, AA0 VPERM2I128 $0x02, CC1, DD1, BB0 VPERM2I128 $0x13, AA1, BB1, CC0 VPERM2I128 $0x13, CC1, DD1, DD0 JMP sealAVX2SealHash // ---------------------------------------------------------------------------- // Special optimization for the last 384 bytes of ciphertext sealAVX2Tail384: // Need to decrypt up to 384 bytes - prepare two blocks // If we got here after the main loop - there are 512 encrypted bytes waiting to be hashed // If we got here before the main loop - there are 448 encrpyred bytes waiting to be hashed VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2 VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2 VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2 VMOVDQA ctr3StoreAVX2, DD0 VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2 VMOVDQA DD0, TT1; VMOVDQA DD1, TT2; VMOVDQA DD2, TT3 sealAVX2Tail384LoopA: polyAdd(0(oup)) polyMul LEAQ 16(oup), oup sealAVX2Tail384LoopB: chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) polyAdd(0(oup)) polyMul VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2 chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) polyAdd(16(oup)) polyMul LEAQ 32(oup), oup VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2 DECQ itr1 JG sealAVX2Tail384LoopA DECQ itr2 JGE sealAVX2Tail384LoopB VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2 VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2 VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2 VPADDD TT1, DD0, DD0; VPADDD TT2, DD1, DD1; VPADDD TT3, DD2, DD2 VPERM2I128 $0x02, AA0, BB0, TT0 VPERM2I128 $0x02, CC0, DD0, TT1 VPERM2I128 $0x13, AA0, BB0, TT2 VPERM2I128 $0x13, CC0, DD0, TT3 VPXOR (0*32)(inp), TT0, TT0; VPXOR (1*32)(inp), TT1, TT1; VPXOR (2*32)(inp), TT2, TT2; VPXOR (3*32)(inp), TT3, TT3 VMOVDQU TT0, (0*32)(oup); VMOVDQU TT1, (1*32)(oup); VMOVDQU TT2, (2*32)(oup); VMOVDQU TT3, (3*32)(oup) VPERM2I128 $0x02, AA1, BB1, TT0 VPERM2I128 $0x02, CC1, DD1, TT1 VPERM2I128 $0x13, AA1, BB1, TT2 VPERM2I128 $0x13, CC1, DD1, TT3 VPXOR (4*32)(inp), TT0, TT0; VPXOR (5*32)(inp), TT1, TT1; VPXOR (6*32)(inp), TT2, TT2; VPXOR (7*32)(inp), TT3, TT3 VMOVDQU TT0, (4*32)(oup); VMOVDQU TT1, (5*32)(oup); VMOVDQU TT2, (6*32)(oup); VMOVDQU TT3, (7*32)(oup) MOVQ $256, itr1 LEAQ 256(inp), inp SUBQ $256, inl VPERM2I128 $0x02, AA2, BB2, AA0 VPERM2I128 $0x02, CC2, DD2, BB0 VPERM2I128 $0x13, AA2, BB2, CC0 VPERM2I128 $0x13, CC2, DD2, DD0 JMP sealAVX2SealHash // ---------------------------------------------------------------------------- // Special optimization for the last 512 bytes of ciphertext sealAVX2Tail512: // Need to decrypt up to 512 bytes - prepare two blocks // If we got here after the main loop - there are 512 encrypted bytes waiting to be hashed // If we got here before the main loop - there are 448 encrpyred bytes waiting to be hashed VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 VMOVDQA ctr3StoreAVX2, DD0 VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 sealAVX2Tail512LoopA: polyAdd(0(oup)) polyMul LEAQ 16(oup), oup sealAVX2Tail512LoopB: VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 polyAdd(0*8(oup)) polyMulAVX2 VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $4, BB3, BB3, BB3 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2; VPALIGNR $12, DD3, DD3, DD3 VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 polyAdd(2*8(oup)) polyMulAVX2 LEAQ (4*8)(oup), oup VMOVDQA CC3, tmpStoreAVX2 VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 VMOVDQA CC3, tmpStoreAVX2 VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 VMOVDQA tmpStoreAVX2, CC3 VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $12, BB3, BB3, BB3 VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2; VPALIGNR $4, DD3, DD3, DD3 DECQ itr1 JG sealAVX2Tail512LoopA DECQ itr2 JGE sealAVX2Tail512LoopB VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 VMOVDQA CC3, tmpStoreAVX2 VPERM2I128 $0x02, AA0, BB0, CC3 VPXOR (0*32)(inp), CC3, CC3 VMOVDQU CC3, (0*32)(oup) VPERM2I128 $0x02, CC0, DD0, CC3 VPXOR (1*32)(inp), CC3, CC3 VMOVDQU CC3, (1*32)(oup) VPERM2I128 $0x13, AA0, BB0, CC3 VPXOR (2*32)(inp), CC3, CC3 VMOVDQU CC3, (2*32)(oup) VPERM2I128 $0x13, CC0, DD0, CC3 VPXOR (3*32)(inp), CC3, CC3 VMOVDQU CC3, (3*32)(oup) VPERM2I128 $0x02, AA1, BB1, AA0 VPERM2I128 $0x02, CC1, DD1, BB0 VPERM2I128 $0x13, AA1, BB1, CC0 VPERM2I128 $0x13, CC1, DD1, DD0 VPXOR (4*32)(inp), AA0, AA0; VPXOR (5*32)(inp), BB0, BB0; VPXOR (6*32)(inp), CC0, CC0; VPXOR (7*32)(inp), DD0, DD0 VMOVDQU AA0, (4*32)(oup); VMOVDQU BB0, (5*32)(oup); VMOVDQU CC0, (6*32)(oup); VMOVDQU DD0, (7*32)(oup) VPERM2I128 $0x02, AA2, BB2, AA0 VPERM2I128 $0x02, CC2, DD2, BB0 VPERM2I128 $0x13, AA2, BB2, CC0 VPERM2I128 $0x13, CC2, DD2, DD0 VPXOR (8*32)(inp), AA0, AA0; VPXOR (9*32)(inp), BB0, BB0; VPXOR (10*32)(inp), CC0, CC0; VPXOR (11*32)(inp), DD0, DD0 VMOVDQU AA0, (8*32)(oup); VMOVDQU BB0, (9*32)(oup); VMOVDQU CC0, (10*32)(oup); VMOVDQU DD0, (11*32)(oup) MOVQ $384, itr1 LEAQ 384(inp), inp SUBQ $384, inl VPERM2I128 $0x02, AA3, BB3, AA0 VPERM2I128 $0x02, tmpStoreAVX2, DD3, BB0 VPERM2I128 $0x13, AA3, BB3, CC0 VPERM2I128 $0x13, tmpStoreAVX2, DD3, DD0 JMP sealAVX2SealHash -- y -- // Code generated by command: go run chacha20poly1305_amd64_asm.go -out ../chacha20poly1305_amd64.s -pkg chacha20poly1305. DO NOT EDIT. //go:build gc && !purego #include "textflag.h" // func polyHashADInternal<>() TEXT polyHashADInternal<>(SB), NOSPLIT, $0 // Hack: Must declare #define macros inside of a function due to Avo constraints // ROL rotates the uint32s in register R left by N bits, using temporary T. #define ROL(N, R, T) \ MOVO R, T; \ PSLLL $(N), T; \ PSRLL $(32-(N)), R; \ PXOR T, R // ROL8 rotates the uint32s in register R left by 8, using temporary T if needed. #ifdef GOAMD64_v2 #define ROL8(R, T) PSHUFB ·rol8<>(SB), R #else #define ROL8(R, T) ROL(8, R, T) #endif // ROL16 rotates the uint32s in register R left by 16, using temporary T if needed. #ifdef GOAMD64_v2 #define ROL16(R, T) PSHUFB ·rol16<>(SB), R #else #define ROL16(R, T) ROL(16, R, T) #endif XORQ R10, R10 XORQ R11, R11 XORQ R12, R12 CMPQ R9, $0x0d JNE hashADLoop MOVQ (CX), R10 MOVQ 5(CX), R11 SHRQ $0x18, R11 MOVQ $0x00000001, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 RET hashADLoop: // Hash in 16 byte chunks CMPQ R9, $0x10 JB hashADTail ADDQ (CX), R10 ADCQ 8(CX), R11 ADCQ $0x01, R12 LEAQ 16(CX), CX SUBQ $0x10, R9 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 JMP hashADLoop hashADTail: CMPQ R9, $0x00 JE hashADDone // Hash last < 16 byte tail XORQ R13, R13 XORQ R14, R14 XORQ R15, R15 ADDQ R9, CX hashADTailLoop: SHLQ $0x08, R13, R14 SHLQ $0x08, R13 MOVB -1(CX), R15 XORQ R15, R13 DECQ CX DECQ R9 JNE hashADTailLoop ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 hashADDone: RET // func chacha20Poly1305Open(dst []byte, key []uint32, src []byte, ad []byte) bool // Requires: AVX, AVX2, BMI2, CMOV, SSE2 TEXT ·chacha20Poly1305Open(SB), $288-97 // For aligned stack access MOVQ SP, BP ADDQ $0x20, BP ANDQ $-32, BP MOVQ dst_base+0(FP), DI MOVQ key_base+24(FP), R8 MOVQ src_base+48(FP), SI MOVQ src_len+56(FP), BX MOVQ ad_base+72(FP), CX // Check for AVX2 support CMPB ·useAVX2+0(SB), $0x01 JE chacha20Poly1305Open_AVX2 // Special optimization, for very short buffers CMPQ BX, $0x80 JBE openSSE128 // For long buffers, prepare the poly key first MOVOU ·chacha20Constants<>+0(SB), X0 MOVOU 16(R8), X3 MOVOU 32(R8), X6 MOVOU 48(R8), X9 MOVO X9, X13 // Store state on stack for future use MOVO X3, 32(BP) MOVO X6, 48(BP) MOVO X9, 128(BP) MOVQ $0x0000000a, R9 openSSEPreparePolyKey: PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x0c PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x04 DECQ R9 JNE openSSEPreparePolyKey // A0|B0 hold the Poly1305 32-byte key, C0,D0 can be discarded PADDL ·chacha20Constants<>+0(SB), X0 PADDL 32(BP), X3 // Clamp and store the key PAND ·polyClampMask<>+0(SB), X0 MOVO X0, (BP) MOVO X3, 16(BP) // Hash AAD MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) openSSEMainLoop: CMPQ BX, $0x00000100 JB openSSEMainLoopDone // Load state, increment counter blocks MOVO ·chacha20Constants<>+0(SB), X0 MOVO 32(BP), X3 MOVO 48(BP), X6 MOVO 128(BP), X9 PADDL ·sseIncMask<>+0(SB), X9 MOVO X0, X1 MOVO X3, X4 MOVO X6, X7 MOVO X9, X10 PADDL ·sseIncMask<>+0(SB), X10 MOVO X1, X2 MOVO X4, X5 MOVO X7, X8 MOVO X10, X11 PADDL ·sseIncMask<>+0(SB), X11 MOVO X2, X12 MOVO X5, X13 MOVO X8, X14 MOVO X11, X15 PADDL ·sseIncMask<>+0(SB), X15 // Store counters MOVO X9, 80(BP) MOVO X10, 96(BP) MOVO X11, 112(BP) MOVO X15, 128(BP) // There are 10 ChaCha20 iterations of 2QR each, so for 6 iterations we hash // 2 blocks, and for the remaining 4 only 1 block - for a total of 16 MOVQ $0x00000004, CX MOVQ SI, R9 openSSEInternalLoop: MOVO X14, 64(BP) PADDD X3, X0 PXOR X0, X9 ROL16(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x0c, X14 PSRLL $0x14, X3 PXOR X14, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x07, X14 PSRLL $0x19, X3 PXOR X14, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x0c, X14 PSRLL $0x14, X4 PXOR X14, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x07, X14 PSRLL $0x19, X4 PXOR X14, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x0c, X14 PSRLL $0x14, X5 PXOR X14, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x07, X14 PSRLL $0x19, X5 PXOR X14, X5 MOVO 64(BP), X14 MOVO X7, 64(BP) PADDD X13, X12 PXOR X12, X15 ROL16(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x0c, X7 PSRLL $0x14, X13 PXOR X7, X13 PADDD X13, X12 PXOR X12, X15 ROL8(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x07, X7 PSRLL $0x19, X13 PXOR X7, X13 MOVO 64(BP), X7 ADDQ (R9), R10 ADCQ 8(R9), R11 ADCQ $0x01, R12 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x0c MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX LEAQ 16(R9), R9 MOVO X14, 64(BP) PADDD X3, X0 PXOR X0, X9 ROL16(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x0c, X14 PSRLL $0x14, X3 PXOR X14, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x07, X14 PSRLL $0x19, X3 PXOR X14, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x0c, X14 PSRLL $0x14, X4 PXOR X14, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x07, X14 PSRLL $0x19, X4 PXOR X14, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x0c, X14 PSRLL $0x14, X5 PXOR X14, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x07, X14 PSRLL $0x19, X5 PXOR X14, X5 MOVO 64(BP), X14 MOVO X7, 64(BP) IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 PADDD X13, X12 PXOR X12, X15 ROL16(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x0c, X7 PSRLL $0x14, X13 PXOR X7, X13 PADDD X13, X12 PXOR X12, X15 ROL8(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x07, X7 PSRLL $0x19, X13 PXOR X7, X13 MOVO 64(BP), X7 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x04 DECQ CX JGE openSSEInternalLoop ADDQ (R9), R10 ADCQ 8(R9), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(R9), R9 CMPQ CX, $-6 JG openSSEInternalLoop // Add in the state PADDD ·chacha20Constants<>+0(SB), X0 PADDD ·chacha20Constants<>+0(SB), X1 PADDD ·chacha20Constants<>+0(SB), X2 PADDD ·chacha20Constants<>+0(SB), X12 PADDD 32(BP), X3 PADDD 32(BP), X4 PADDD 32(BP), X5 PADDD 32(BP), X13 PADDD 48(BP), X6 PADDD 48(BP), X7 PADDD 48(BP), X8 PADDD 48(BP), X14 PADDD 80(BP), X9 PADDD 96(BP), X10 PADDD 112(BP), X11 PADDD 128(BP), X15 // Load - xor - store MOVO X15, 64(BP) MOVOU (SI), X15 PXOR X15, X0 MOVOU X0, (DI) MOVOU 16(SI), X15 PXOR X15, X3 MOVOU X3, 16(DI) MOVOU 32(SI), X15 PXOR X15, X6 MOVOU X6, 32(DI) MOVOU 48(SI), X15 PXOR X15, X9 MOVOU X9, 48(DI) MOVOU 64(SI), X9 PXOR X9, X1 MOVOU X1, 64(DI) MOVOU 80(SI), X9 PXOR X9, X4 MOVOU X4, 80(DI) MOVOU 96(SI), X9 PXOR X9, X7 MOVOU X7, 96(DI) MOVOU 112(SI), X9 PXOR X9, X10 MOVOU X10, 112(DI) MOVOU 128(SI), X9 PXOR X9, X2 MOVOU X2, 128(DI) MOVOU 144(SI), X9 PXOR X9, X5 MOVOU X5, 144(DI) MOVOU 160(SI), X9 PXOR X9, X8 MOVOU X8, 160(DI) MOVOU 176(SI), X9 PXOR X9, X11 MOVOU X11, 176(DI) MOVOU 192(SI), X9 PXOR X9, X12 MOVOU X12, 192(DI) MOVOU 208(SI), X9 PXOR X9, X13 MOVOU X13, 208(DI) MOVOU 224(SI), X9 PXOR X9, X14 MOVOU X14, 224(DI) MOVOU 240(SI), X9 PXOR 64(BP), X9 MOVOU X9, 240(DI) LEAQ 256(SI), SI LEAQ 256(DI), DI SUBQ $0x00000100, BX JMP openSSEMainLoop openSSEMainLoopDone: // Handle the various tail sizes efficiently TESTQ BX, BX JE openSSEFinalize CMPQ BX, $0x40 JBE openSSETail64 CMPQ BX, $0x80 JBE openSSETail128 CMPQ BX, $0xc0 JBE openSSETail192 JMP openSSETail256 openSSEFinalize: // Hash in the PT, AAD lengths ADDQ ad_len+80(FP), R10 ADCQ src_len+56(FP), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 // Final reduce MOVQ R10, R13 MOVQ R11, R14 MOVQ R12, R15 SUBQ $-5, R10 SBBQ $-1, R11 SBBQ $0x03, R12 CMOVQCS R13, R10 CMOVQCS R14, R11 CMOVQCS R15, R12 // Add in the "s" part of the key ADDQ 16(BP), R10 ADCQ 24(BP), R11 // Finally, constant time compare to the tag at the end of the message XORQ AX, AX MOVQ $0x00000001, DX XORQ (SI), R10 XORQ 8(SI), R11 ORQ R11, R10 CMOVQEQ DX, AX // Return true iff tags are equal MOVB AX, ret+96(FP) RET openSSE128: MOVOU ·chacha20Constants<>+0(SB), X0 MOVOU 16(R8), X3 MOVOU 32(R8), X6 MOVOU 48(R8), X9 MOVO X0, X1 MOVO X3, X4 MOVO X6, X7 MOVO X9, X10 PADDL ·sseIncMask<>+0(SB), X10 MOVO X1, X2 MOVO X4, X5 MOVO X7, X8 MOVO X10, X11 PADDL ·sseIncMask<>+0(SB), X11 MOVO X3, X13 MOVO X6, X14 MOVO X10, X15 MOVQ $0x0000000a, R9 openSSE128InnerCipherLoop: PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x0c, X12 PSRLL $0x14, X4 PXOR X12, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x07, X12 PSRLL $0x19, X4 PXOR X12, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x0c, X12 PSRLL $0x14, X5 PXOR X12, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x07, X12 PSRLL $0x19, X5 PXOR X12, X5 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x0c, X12 PSRLL $0x14, X4 PXOR X12, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x07, X12 PSRLL $0x19, X4 PXOR X12, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x0c, X12 PSRLL $0x14, X5 PXOR X12, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x07, X12 PSRLL $0x19, X5 PXOR X12, X5 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 DECQ R9 JNE openSSE128InnerCipherLoop // A0|B0 hold the Poly1305 32-byte key, C0,D0 can be discarded PADDL ·chacha20Constants<>+0(SB), X0 PADDL ·chacha20Constants<>+0(SB), X1 PADDL ·chacha20Constants<>+0(SB), X2 PADDL X13, X3 PADDL X13, X4 PADDL X13, X5 PADDL X14, X7 PADDL X14, X8 PADDL X15, X10 PADDL ·sseIncMask<>+0(SB), X15 PADDL X15, X11 // Clamp and store the key PAND ·polyClampMask<>+0(SB), X0 MOVOU X0, (BP) MOVOU X3, 16(BP) // Hash MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) openSSE128Open: CMPQ BX, $0x10 JB openSSETail16 SUBQ $0x10, BX // Load for hashing ADDQ (SI), R10 ADCQ 8(SI), R11 ADCQ $0x01, R12 // Load for decryption MOVOU (SI), X12 PXOR X12, X1 MOVOU X1, (DI) LEAQ 16(SI), SI LEAQ 16(DI), DI MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 // Shift the stream "left" MOVO X4, X1 MOVO X7, X4 MOVO X10, X7 MOVO X2, X10 MOVO X5, X2 MOVO X8, X5 MOVO X11, X8 JMP openSSE128Open openSSETail16: TESTQ BX, BX JE openSSEFinalize // We can safely load the CT from the end, because it is padded with the MAC MOVQ BX, R9 SHLQ $0x04, R9 LEAQ ·andMask<>+0(SB), R13 MOVOU (SI), X12 ADDQ BX, SI PAND -16(R13)(R9*1), X12 MOVO X12, 64(BP) MOVQ X12, R13 MOVQ 72(BP), R14 PXOR X1, X12 // We can only store one byte at a time, since plaintext can be shorter than 16 bytes openSSETail16Store: MOVQ X12, R8 MOVB R8, (DI) PSRLDQ $0x01, X12 INCQ DI DECQ BX JNE openSSETail16Store ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 JMP openSSEFinalize openSSETail64: MOVO ·chacha20Constants<>+0(SB), X0 MOVO 32(BP), X3 MOVO 48(BP), X6 MOVO 128(BP), X9 PADDL ·sseIncMask<>+0(SB), X9 MOVO X9, 80(BP) XORQ R9, R9 MOVQ BX, CX CMPQ CX, $0x10 JB openSSETail64LoopB openSSETail64LoopA: ADDQ (SI)(R9*1), R10 ADCQ 8(SI)(R9*1), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 SUBQ $0x10, CX openSSETail64LoopB: ADDQ $0x10, R9 PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x0c PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x04 CMPQ CX, $0x10 JAE openSSETail64LoopA CMPQ R9, $0xa0 JNE openSSETail64LoopB PADDL ·chacha20Constants<>+0(SB), X0 PADDL 32(BP), X3 PADDL 48(BP), X6 PADDL 80(BP), X9 openSSETail64DecLoop: CMPQ BX, $0x10 JB openSSETail64DecLoopDone SUBQ $0x10, BX MOVOU (SI), X12 PXOR X12, X0 MOVOU X0, (DI) LEAQ 16(SI), SI LEAQ 16(DI), DI MOVO X3, X0 MOVO X6, X3 MOVO X9, X6 JMP openSSETail64DecLoop openSSETail64DecLoopDone: MOVO X0, X1 JMP openSSETail16 openSSETail128: MOVO ·chacha20Constants<>+0(SB), X1 MOVO 32(BP), X4 MOVO 48(BP), X7 MOVO 128(BP), X10 PADDL ·sseIncMask<>+0(SB), X10 MOVO X10, 80(BP) MOVO X1, X0 MOVO X4, X3 MOVO X7, X6 MOVO X10, X9 PADDL ·sseIncMask<>+0(SB), X9 MOVO X9, 96(BP) XORQ R9, R9 MOVQ BX, CX ANDQ $-16, CX openSSETail128LoopA: ADDQ (SI)(R9*1), R10 ADCQ 8(SI)(R9*1), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 openSSETail128LoopB: ADDQ $0x10, R9 PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x0c, X12 PSRLL $0x14, X4 PXOR X12, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x07, X12 PSRLL $0x19, X4 PXOR X12, X4 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x0c PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x0c, X12 PSRLL $0x14, X4 PXOR X12, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x07, X12 PSRLL $0x19, X4 PXOR X12, X4 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x04 CMPQ R9, CX JB openSSETail128LoopA CMPQ R9, $0xa0 JNE openSSETail128LoopB PADDL ·chacha20Constants<>+0(SB), X0 PADDL ·chacha20Constants<>+0(SB), X1 PADDL 32(BP), X3 PADDL 32(BP), X4 PADDL 48(BP), X6 PADDL 48(BP), X7 PADDL 96(BP), X9 PADDL 80(BP), X10 MOVOU (SI), X12 MOVOU 16(SI), X13 MOVOU 32(SI), X14 MOVOU 48(SI), X15 PXOR X12, X1 PXOR X13, X4 PXOR X14, X7 PXOR X15, X10 MOVOU X1, (DI) MOVOU X4, 16(DI) MOVOU X7, 32(DI) MOVOU X10, 48(DI) SUBQ $0x40, BX LEAQ 64(SI), SI LEAQ 64(DI), DI JMP openSSETail64DecLoop openSSETail192: MOVO ·chacha20Constants<>+0(SB), X2 MOVO 32(BP), X5 MOVO 48(BP), X8 MOVO 128(BP), X11 PADDL ·sseIncMask<>+0(SB), X11 MOVO X11, 80(BP) MOVO X2, X1 MOVO X5, X4 MOVO X8, X7 MOVO X11, X10 PADDL ·sseIncMask<>+0(SB), X10 MOVO X10, 96(BP) MOVO X1, X0 MOVO X4, X3 MOVO X7, X6 MOVO X10, X9 PADDL ·sseIncMask<>+0(SB), X9 MOVO X9, 112(BP) MOVQ BX, CX MOVQ $0x000000a0, R9 CMPQ CX, $0xa0 CMOVQGT R9, CX ANDQ $-16, CX XORQ R9, R9 openSSLTail192LoopA: ADDQ (SI)(R9*1), R10 ADCQ 8(SI)(R9*1), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 openSSLTail192LoopB: ADDQ $0x10, R9 PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x0c, X12 PSRLL $0x14, X4 PXOR X12, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x07, X12 PSRLL $0x19, X4 PXOR X12, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x0c, X12 PSRLL $0x14, X5 PXOR X12, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x07, X12 PSRLL $0x19, X5 PXOR X12, X5 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x0c, X12 PSRLL $0x14, X4 PXOR X12, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x07, X12 PSRLL $0x19, X4 PXOR X12, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x0c, X12 PSRLL $0x14, X5 PXOR X12, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x07, X12 PSRLL $0x19, X5 PXOR X12, X5 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 CMPQ R9, CX JB openSSLTail192LoopA CMPQ R9, $0xa0 JNE openSSLTail192LoopB CMPQ BX, $0xb0 JB openSSLTail192Store ADDQ 160(SI), R10 ADCQ 168(SI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 CMPQ BX, $0xc0 JB openSSLTail192Store ADDQ 176(SI), R10 ADCQ 184(SI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 openSSLTail192Store: PADDL ·chacha20Constants<>+0(SB), X0 PADDL ·chacha20Constants<>+0(SB), X1 PADDL ·chacha20Constants<>+0(SB), X2 PADDL 32(BP), X3 PADDL 32(BP), X4 PADDL 32(BP), X5 PADDL 48(BP), X6 PADDL 48(BP), X7 PADDL 48(BP), X8 PADDL 112(BP), X9 PADDL 96(BP), X10 PADDL 80(BP), X11 MOVOU (SI), X12 MOVOU 16(SI), X13 MOVOU 32(SI), X14 MOVOU 48(SI), X15 PXOR X12, X2 PXOR X13, X5 PXOR X14, X8 PXOR X15, X11 MOVOU X2, (DI) MOVOU X5, 16(DI) MOVOU X8, 32(DI) MOVOU X11, 48(DI) MOVOU 64(SI), X12 MOVOU 80(SI), X13 MOVOU 96(SI), X14 MOVOU 112(SI), X15 PXOR X12, X1 PXOR X13, X4 PXOR X14, X7 PXOR X15, X10 MOVOU X1, 64(DI) MOVOU X4, 80(DI) MOVOU X7, 96(DI) MOVOU X10, 112(DI) SUBQ $0x80, BX LEAQ 128(SI), SI LEAQ 128(DI), DI JMP openSSETail64DecLoop openSSETail256: MOVO ·chacha20Constants<>+0(SB), X0 MOVO 32(BP), X3 MOVO 48(BP), X6 MOVO 128(BP), X9 PADDL ·sseIncMask<>+0(SB), X9 MOVO X0, X1 MOVO X3, X4 MOVO X6, X7 MOVO X9, X10 PADDL ·sseIncMask<>+0(SB), X10 MOVO X1, X2 MOVO X4, X5 MOVO X7, X8 MOVO X10, X11 PADDL ·sseIncMask<>+0(SB), X11 MOVO X2, X12 MOVO X5, X13 MOVO X8, X14 MOVO X11, X15 PADDL ·sseIncMask<>+0(SB), X15 // Store counters MOVO X9, 80(BP) MOVO X10, 96(BP) MOVO X11, 112(BP) MOVO X15, 128(BP) XORQ R9, R9 openSSETail256Loop: ADDQ (SI)(R9*1), R10 ADCQ 8(SI)(R9*1), R11 ADCQ $0x01, R12 MOVO X14, 64(BP) PADDD X3, X0 PXOR X0, X9 ROL16(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x0c, X14 PSRLL $0x14, X3 PXOR X14, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x07, X14 PSRLL $0x19, X3 PXOR X14, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x0c, X14 PSRLL $0x14, X4 PXOR X14, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x07, X14 PSRLL $0x19, X4 PXOR X14, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x0c, X14 PSRLL $0x14, X5 PXOR X14, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x07, X14 PSRLL $0x19, X5 PXOR X14, X5 MOVO 64(BP), X14 MOVO X7, 64(BP) PADDD X13, X12 PXOR X12, X15 ROL16(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x0c, X7 PSRLL $0x14, X13 PXOR X7, X13 PADDD X13, X12 PXOR X12, X15 ROL8(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x07, X7 PSRLL $0x19, X13 PXOR X7, X13 MOVO 64(BP), X7 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x0c MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX MOVO X14, 64(BP) PADDD X3, X0 PXOR X0, X9 ROL16(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x0c, X14 PSRLL $0x14, X3 PXOR X14, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x07, X14 PSRLL $0x19, X3 PXOR X14, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x0c, X14 PSRLL $0x14, X4 PXOR X14, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x07, X14 PSRLL $0x19, X4 PXOR X14, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x0c, X14 PSRLL $0x14, X5 PXOR X14, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x07, X14 PSRLL $0x19, X5 PXOR X14, X5 MOVO 64(BP), X14 MOVO X7, 64(BP) PADDD X13, X12 PXOR X12, X15 ROL16(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x0c, X7 PSRLL $0x14, X13 PXOR X7, X13 PADDD X13, X12 PXOR X12, X15 ROL8(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x07, X7 PSRLL $0x19, X13 PXOR X7, X13 MOVO 64(BP), X7 IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x04 ADDQ $0x10, R9 CMPQ R9, $0xa0 JB openSSETail256Loop MOVQ BX, CX ANDQ $-16, CX openSSETail256HashLoop: ADDQ (SI)(R9*1), R10 ADCQ 8(SI)(R9*1), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 ADDQ $0x10, R9 CMPQ R9, CX JB openSSETail256HashLoop // Add in the state PADDD ·chacha20Constants<>+0(SB), X0 PADDD ·chacha20Constants<>+0(SB), X1 PADDD ·chacha20Constants<>+0(SB), X2 PADDD ·chacha20Constants<>+0(SB), X12 PADDD 32(BP), X3 PADDD 32(BP), X4 PADDD 32(BP), X5 PADDD 32(BP), X13 PADDD 48(BP), X6 PADDD 48(BP), X7 PADDD 48(BP), X8 PADDD 48(BP), X14 PADDD 80(BP), X9 PADDD 96(BP), X10 PADDD 112(BP), X11 PADDD 128(BP), X15 MOVO X15, 64(BP) // Load - xor - store MOVOU (SI), X15 PXOR X15, X0 MOVOU 16(SI), X15 PXOR X15, X3 MOVOU 32(SI), X15 PXOR X15, X6 MOVOU 48(SI), X15 PXOR X15, X9 MOVOU X0, (DI) MOVOU X3, 16(DI) MOVOU X6, 32(DI) MOVOU X9, 48(DI) MOVOU 64(SI), X0 MOVOU 80(SI), X3 MOVOU 96(SI), X6 MOVOU 112(SI), X9 PXOR X0, X1 PXOR X3, X4 PXOR X6, X7 PXOR X9, X10 MOVOU X1, 64(DI) MOVOU X4, 80(DI) MOVOU X7, 96(DI) MOVOU X10, 112(DI) MOVOU 128(SI), X0 MOVOU 144(SI), X3 MOVOU 160(SI), X6 MOVOU 176(SI), X9 PXOR X0, X2 PXOR X3, X5 PXOR X6, X8 PXOR X9, X11 MOVOU X2, 128(DI) MOVOU X5, 144(DI) MOVOU X8, 160(DI) MOVOU X11, 176(DI) LEAQ 192(SI), SI LEAQ 192(DI), DI SUBQ $0xc0, BX MOVO X12, X0 MOVO X13, X3 MOVO X14, X6 MOVO 64(BP), X9 JMP openSSETail64DecLoop chacha20Poly1305Open_AVX2: VZEROUPPER VMOVDQU ·chacha20Constants<>+0(SB), Y0 BYTE $0xc4 BYTE $0x42 BYTE $0x7d BYTE $0x5a BYTE $0x70 BYTE $0x10 BYTE $0xc4 BYTE $0x42 BYTE $0x7d BYTE $0x5a BYTE $0x60 BYTE $0x20 BYTE $0xc4 BYTE $0xc2 BYTE $0x7d BYTE $0x5a BYTE $0x60 BYTE $0x30 VPADDD ·avx2InitMask<>+0(SB), Y4, Y4 // Special optimization, for very short buffers CMPQ BX, $0xc0 JBE openAVX2192 CMPQ BX, $0x00000140 JBE openAVX2320 // For the general key prepare the key first - as a byproduct we have 64 bytes of cipher stream VMOVDQA Y14, 32(BP) VMOVDQA Y12, 64(BP) VMOVDQA Y4, 192(BP) MOVQ $0x0000000a, R9 openAVX2PreparePolyKey: VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x0c, Y4, Y4, Y4 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x04, Y4, Y4, Y4 DECQ R9 JNE openAVX2PreparePolyKey VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 VPADDD 32(BP), Y14, Y14 VPADDD 64(BP), Y12, Y12 VPADDD 192(BP), Y4, Y4 VPERM2I128 $0x02, Y0, Y14, Y3 // Clamp and store poly key VPAND ·polyClampMask<>+0(SB), Y3, Y3 VMOVDQA Y3, (BP) // Stream for the first 64 bytes VPERM2I128 $0x13, Y0, Y14, Y0 VPERM2I128 $0x13, Y12, Y4, Y14 // Hash AD + first 64 bytes MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) XORQ CX, CX openAVX2InitialHash64: ADDQ (SI)(CX*1), R10 ADCQ 8(SI)(CX*1), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 ADDQ $0x10, CX CMPQ CX, $0x40 JNE openAVX2InitialHash64 // Decrypt the first 64 bytes VPXOR (SI), Y0, Y0 VPXOR 32(SI), Y14, Y14 VMOVDQU Y0, (DI) VMOVDQU Y14, 32(DI) LEAQ 64(SI), SI LEAQ 64(DI), DI SUBQ $0x40, BX openAVX2MainLoop: CMPQ BX, $0x00000200 JB openAVX2MainLoopDone // Load state, increment counter blocks, store the incremented counters VMOVDQU ·chacha20Constants<>+0(SB), Y0 VMOVDQA Y0, Y5 VMOVDQA Y0, Y6 VMOVDQA Y0, Y7 VMOVDQA 32(BP), Y14 VMOVDQA Y14, Y9 VMOVDQA Y14, Y10 VMOVDQA Y14, Y11 VMOVDQA 64(BP), Y12 VMOVDQA Y12, Y13 VMOVDQA Y12, Y8 VMOVDQA Y12, Y15 VMOVDQA 192(BP), Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 VMOVDQA Y4, 96(BP) VMOVDQA Y1, 128(BP) VMOVDQA Y2, 160(BP) VMOVDQA Y3, 192(BP) XORQ CX, CX openAVX2InternalLoop: ADDQ (SI)(CX*1), R10 ADCQ 8(SI)(CX*1), R11 ADCQ $0x01, R12 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y3, Y3 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 VMOVDQA Y15, 224(BP) VPSLLD $0x0c, Y14, Y15 VPSRLD $0x14, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x0c, Y9, Y15 VPSRLD $0x14, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x0c, Y10, Y15 VPSRLD $0x14, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x0c, Y11, Y15 VPSRLD $0x14, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y3, Y3 ADDQ 16(SI)(CX*1), R10 ADCQ 24(SI)(CX*1), R11 ADCQ $0x01, R12 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 VMOVDQA Y15, 224(BP) VPSLLD $0x07, Y14, Y15 VPSRLD $0x19, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x07, Y9, Y15 VPSRLD $0x19, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x07, Y10, Y15 VPSRLD $0x19, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x07, Y11, Y15 VPSRLD $0x19, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x04, Y10, Y10, Y10 VPALIGNR $0x04, Y11, Y11, Y11 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x08, Y15, Y15, Y15 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x0c, Y1, Y1, Y1 VPALIGNR $0x0c, Y2, Y2, Y2 VPALIGNR $0x0c, Y3, Y3, Y3 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y3, Y3 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 ADDQ 32(SI)(CX*1), R10 ADCQ 40(SI)(CX*1), R11 ADCQ $0x01, R12 LEAQ 48(CX), CX VMOVDQA Y15, 224(BP) VPSLLD $0x0c, Y14, Y15 VPSRLD $0x14, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x0c, Y9, Y15 VPSRLD $0x14, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x0c, Y10, Y15 VPSRLD $0x14, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x0c, Y11, Y15 VPSRLD $0x14, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y3, Y3 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 VMOVDQA Y15, 224(BP) VPSLLD $0x07, Y14, Y15 VPSRLD $0x19, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x07, Y9, Y15 VPSRLD $0x19, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x07, Y10, Y15 VPSRLD $0x19, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x07, Y11, Y15 VPSRLD $0x19, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x0c, Y10, Y10, Y10 VPALIGNR $0x0c, Y11, Y11, Y11 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x08, Y15, Y15, Y15 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x04, Y1, Y1, Y1 VPALIGNR $0x04, Y2, Y2, Y2 VPALIGNR $0x04, Y3, Y3, Y3 CMPQ CX, $0x000001e0 JNE openAVX2InternalLoop VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 VPADDD 32(BP), Y14, Y14 VPADDD 32(BP), Y9, Y9 VPADDD 32(BP), Y10, Y10 VPADDD 32(BP), Y11, Y11 VPADDD 64(BP), Y12, Y12 VPADDD 64(BP), Y13, Y13 VPADDD 64(BP), Y8, Y8 VPADDD 64(BP), Y15, Y15 VPADDD 96(BP), Y4, Y4 VPADDD 128(BP), Y1, Y1 VPADDD 160(BP), Y2, Y2 VPADDD 192(BP), Y3, Y3 VMOVDQA Y15, 224(BP) // We only hashed 480 of the 512 bytes available - hash the remaining 32 here ADDQ 480(SI), R10 ADCQ 488(SI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 VPERM2I128 $0x02, Y0, Y14, Y15 VPERM2I128 $0x13, Y0, Y14, Y14 VPERM2I128 $0x02, Y12, Y4, Y0 VPERM2I128 $0x13, Y12, Y4, Y12 VPXOR (SI), Y15, Y15 VPXOR 32(SI), Y0, Y0 VPXOR 64(SI), Y14, Y14 VPXOR 96(SI), Y12, Y12 VMOVDQU Y15, (DI) VMOVDQU Y0, 32(DI) VMOVDQU Y14, 64(DI) VMOVDQU Y12, 96(DI) VPERM2I128 $0x02, Y5, Y9, Y0 VPERM2I128 $0x02, Y13, Y1, Y14 VPERM2I128 $0x13, Y5, Y9, Y12 VPERM2I128 $0x13, Y13, Y1, Y4 VPXOR 128(SI), Y0, Y0 VPXOR 160(SI), Y14, Y14 VPXOR 192(SI), Y12, Y12 VPXOR 224(SI), Y4, Y4 VMOVDQU Y0, 128(DI) VMOVDQU Y14, 160(DI) VMOVDQU Y12, 192(DI) VMOVDQU Y4, 224(DI) // and here ADDQ 496(SI), R10 ADCQ 504(SI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 VPERM2I128 $0x02, Y6, Y10, Y0 VPERM2I128 $0x02, Y8, Y2, Y14 VPERM2I128 $0x13, Y6, Y10, Y12 VPERM2I128 $0x13, Y8, Y2, Y4 VPXOR 256(SI), Y0, Y0 VPXOR 288(SI), Y14, Y14 VPXOR 320(SI), Y12, Y12 VPXOR 352(SI), Y4, Y4 VMOVDQU Y0, 256(DI) VMOVDQU Y14, 288(DI) VMOVDQU Y12, 320(DI) VMOVDQU Y4, 352(DI) VPERM2I128 $0x02, Y7, Y11, Y0 VPERM2I128 $0x02, 224(BP), Y3, Y14 VPERM2I128 $0x13, Y7, Y11, Y12 VPERM2I128 $0x13, 224(BP), Y3, Y4 VPXOR 384(SI), Y0, Y0 VPXOR 416(SI), Y14, Y14 VPXOR 448(SI), Y12, Y12 VPXOR 480(SI), Y4, Y4 VMOVDQU Y0, 384(DI) VMOVDQU Y14, 416(DI) VMOVDQU Y12, 448(DI) VMOVDQU Y4, 480(DI) LEAQ 512(SI), SI LEAQ 512(DI), DI SUBQ $0x00000200, BX JMP openAVX2MainLoop openAVX2MainLoopDone: // Handle the various tail sizes efficiently TESTQ BX, BX JE openSSEFinalize CMPQ BX, $0x80 JBE openAVX2Tail128 CMPQ BX, $0x00000100 JBE openAVX2Tail256 CMPQ BX, $0x00000180 JBE openAVX2Tail384 JMP openAVX2Tail512 openAVX2192: VMOVDQA Y0, Y5 VMOVDQA Y14, Y9 VMOVDQA Y12, Y13 VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VMOVDQA Y0, Y6 VMOVDQA Y14, Y10 VMOVDQA Y12, Y8 VMOVDQA Y4, Y2 VMOVDQA Y1, Y15 MOVQ $0x0000000a, R9 openAVX2192InnerCipherLoop: VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x0c, Y1, Y1, Y1 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x04, Y1, Y1, Y1 DECQ R9 JNE openAVX2192InnerCipherLoop VPADDD Y6, Y0, Y0 VPADDD Y6, Y5, Y5 VPADDD Y10, Y14, Y14 VPADDD Y10, Y9, Y9 VPADDD Y8, Y12, Y12 VPADDD Y8, Y13, Y13 VPADDD Y2, Y4, Y4 VPADDD Y15, Y1, Y1 VPERM2I128 $0x02, Y0, Y14, Y3 // Clamp and store poly key VPAND ·polyClampMask<>+0(SB), Y3, Y3 VMOVDQA Y3, (BP) // Stream for up to 192 bytes VPERM2I128 $0x13, Y0, Y14, Y0 VPERM2I128 $0x13, Y12, Y4, Y14 VPERM2I128 $0x02, Y5, Y9, Y12 VPERM2I128 $0x02, Y13, Y1, Y4 VPERM2I128 $0x13, Y5, Y9, Y5 VPERM2I128 $0x13, Y13, Y1, Y9 openAVX2ShortOpen: // Hash MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) openAVX2ShortOpenLoop: CMPQ BX, $0x20 JB openAVX2ShortTail32 SUBQ $0x20, BX // Load for hashing ADDQ (SI), R10 ADCQ 8(SI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 ADDQ 16(SI), R10 ADCQ 24(SI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 // Load for decryption VPXOR (SI), Y0, Y0 VMOVDQU Y0, (DI) LEAQ 32(SI), SI LEAQ 32(DI), DI // Shift stream left VMOVDQA Y14, Y0 VMOVDQA Y12, Y14 VMOVDQA Y4, Y12 VMOVDQA Y5, Y4 VMOVDQA Y9, Y5 VMOVDQA Y13, Y9 VMOVDQA Y1, Y13 VMOVDQA Y6, Y1 VMOVDQA Y10, Y6 JMP openAVX2ShortOpenLoop openAVX2ShortTail32: CMPQ BX, $0x10 VMOVDQA X0, X1 JB openAVX2ShortDone SUBQ $0x10, BX // Load for hashing ADDQ (SI), R10 ADCQ 8(SI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 // Load for decryption VPXOR (SI), X0, X12 VMOVDQU X12, (DI) LEAQ 16(SI), SI LEAQ 16(DI), DI VPERM2I128 $0x11, Y0, Y0, Y0 VMOVDQA X0, X1 openAVX2ShortDone: VZEROUPPER JMP openSSETail16 openAVX2320: VMOVDQA Y0, Y5 VMOVDQA Y14, Y9 VMOVDQA Y12, Y13 VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VMOVDQA Y0, Y6 VMOVDQA Y14, Y10 VMOVDQA Y12, Y8 VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 VMOVDQA Y14, Y7 VMOVDQA Y12, Y11 VMOVDQA Y4, Y15 MOVQ $0x0000000a, R9 openAVX2320InnerCipherLoop: VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x0c, Y10, Y3 VPSRLD $0x14, Y10, Y10 VPXOR Y3, Y10, Y10 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x07, Y10, Y3 VPSRLD $0x19, Y10, Y10 VPXOR Y3, Y10, Y10 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x04, Y10, Y10, Y10 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x0c, Y1, Y1, Y1 VPALIGNR $0x0c, Y2, Y2, Y2 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x0c, Y10, Y3 VPSRLD $0x14, Y10, Y10 VPXOR Y3, Y10, Y10 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x07, Y10, Y3 VPSRLD $0x19, Y10, Y10 VPXOR Y3, Y10, Y10 VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x0c, Y10, Y10, Y10 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x04, Y1, Y1, Y1 VPALIGNR $0x04, Y2, Y2, Y2 DECQ R9 JNE openAVX2320InnerCipherLoop VMOVDQA ·chacha20Constants<>+0(SB), Y3 VPADDD Y3, Y0, Y0 VPADDD Y3, Y5, Y5 VPADDD Y3, Y6, Y6 VPADDD Y7, Y14, Y14 VPADDD Y7, Y9, Y9 VPADDD Y7, Y10, Y10 VPADDD Y11, Y12, Y12 VPADDD Y11, Y13, Y13 VPADDD Y11, Y8, Y8 VMOVDQA ·avx2IncMask<>+0(SB), Y3 VPADDD Y15, Y4, Y4 VPADDD Y3, Y15, Y15 VPADDD Y15, Y1, Y1 VPADDD Y3, Y15, Y15 VPADDD Y15, Y2, Y2 // Clamp and store poly key VPERM2I128 $0x02, Y0, Y14, Y3 VPAND ·polyClampMask<>+0(SB), Y3, Y3 VMOVDQA Y3, (BP) // Stream for up to 320 bytes VPERM2I128 $0x13, Y0, Y14, Y0 VPERM2I128 $0x13, Y12, Y4, Y14 VPERM2I128 $0x02, Y5, Y9, Y12 VPERM2I128 $0x02, Y13, Y1, Y4 VPERM2I128 $0x13, Y5, Y9, Y5 VPERM2I128 $0x13, Y13, Y1, Y9 VPERM2I128 $0x02, Y6, Y10, Y13 VPERM2I128 $0x02, Y8, Y2, Y1 VPERM2I128 $0x13, Y6, Y10, Y6 VPERM2I128 $0x13, Y8, Y2, Y10 JMP openAVX2ShortOpen openAVX2Tail128: // Need to decrypt up to 128 bytes - prepare two blocks VMOVDQA ·chacha20Constants<>+0(SB), Y5 VMOVDQA 32(BP), Y9 VMOVDQA 64(BP), Y13 VMOVDQA 192(BP), Y1 VPADDD ·avx2IncMask<>+0(SB), Y1, Y1 VMOVDQA Y1, Y4 XORQ R9, R9 MOVQ BX, CX ANDQ $-16, CX TESTQ CX, CX JE openAVX2Tail128LoopB openAVX2Tail128LoopA: ADDQ (SI)(R9*1), R10 ADCQ 8(SI)(R9*1), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 openAVX2Tail128LoopB: ADDQ $0x10, R9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x0c, Y1, Y1, Y1 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x04, Y1, Y1, Y1 CMPQ R9, CX JB openAVX2Tail128LoopA CMPQ R9, $0xa0 JNE openAVX2Tail128LoopB VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 VPADDD 32(BP), Y9, Y9 VPADDD 64(BP), Y13, Y13 VPADDD Y4, Y1, Y1 VPERM2I128 $0x02, Y5, Y9, Y0 VPERM2I128 $0x02, Y13, Y1, Y14 VPERM2I128 $0x13, Y5, Y9, Y12 VPERM2I128 $0x13, Y13, Y1, Y4 openAVX2TailLoop: CMPQ BX, $0x20 JB openAVX2Tail SUBQ $0x20, BX // Load for decryption VPXOR (SI), Y0, Y0 VMOVDQU Y0, (DI) LEAQ 32(SI), SI LEAQ 32(DI), DI VMOVDQA Y14, Y0 VMOVDQA Y12, Y14 VMOVDQA Y4, Y12 JMP openAVX2TailLoop openAVX2Tail: CMPQ BX, $0x10 VMOVDQA X0, X1 JB openAVX2TailDone SUBQ $0x10, BX // Load for decryption VPXOR (SI), X0, X12 VMOVDQU X12, (DI) LEAQ 16(SI), SI LEAQ 16(DI), DI VPERM2I128 $0x11, Y0, Y0, Y0 VMOVDQA X0, X1 openAVX2TailDone: VZEROUPPER JMP openSSETail16 openAVX2Tail256: VMOVDQA ·chacha20Constants<>+0(SB), Y0 VMOVDQA Y0, Y5 VMOVDQA 32(BP), Y14 VMOVDQA Y14, Y9 VMOVDQA 64(BP), Y12 VMOVDQA Y12, Y13 VMOVDQA 192(BP), Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VMOVDQA Y4, Y7 VMOVDQA Y1, Y11 // Compute the number of iterations that will hash data MOVQ BX, 224(BP) MOVQ BX, CX SUBQ $0x80, CX SHRQ $0x04, CX MOVQ $0x0000000a, R9 CMPQ CX, $0x0a CMOVQGT R9, CX MOVQ SI, BX XORQ R9, R9 openAVX2Tail256LoopA: ADDQ (BX), R10 ADCQ 8(BX), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(BX), BX openAVX2Tail256LoopB: VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x0c, Y1, Y1, Y1 INCQ R9 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x04, Y1, Y1, Y1 CMPQ R9, CX JB openAVX2Tail256LoopA CMPQ R9, $0x0a JNE openAVX2Tail256LoopB MOVQ BX, R9 SUBQ SI, BX MOVQ BX, CX MOVQ 224(BP), BX openAVX2Tail256Hash: ADDQ $0x10, CX CMPQ CX, BX JGT openAVX2Tail256HashEnd ADDQ (R9), R10 ADCQ 8(R9), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(R9), R9 JMP openAVX2Tail256Hash openAVX2Tail256HashEnd: VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 VPADDD 32(BP), Y14, Y14 VPADDD 32(BP), Y9, Y9 VPADDD 64(BP), Y12, Y12 VPADDD 64(BP), Y13, Y13 VPADDD Y7, Y4, Y4 VPADDD Y11, Y1, Y1 VPERM2I128 $0x02, Y0, Y14, Y6 VPERM2I128 $0x02, Y12, Y4, Y10 VPERM2I128 $0x13, Y0, Y14, Y8 VPERM2I128 $0x13, Y12, Y4, Y2 VPERM2I128 $0x02, Y5, Y9, Y0 VPERM2I128 $0x02, Y13, Y1, Y14 VPERM2I128 $0x13, Y5, Y9, Y12 VPERM2I128 $0x13, Y13, Y1, Y4 VPXOR (SI), Y6, Y6 VPXOR 32(SI), Y10, Y10 VPXOR 64(SI), Y8, Y8 VPXOR 96(SI), Y2, Y2 VMOVDQU Y6, (DI) VMOVDQU Y10, 32(DI) VMOVDQU Y8, 64(DI) VMOVDQU Y2, 96(DI) LEAQ 128(SI), SI LEAQ 128(DI), DI SUBQ $0x80, BX JMP openAVX2TailLoop openAVX2Tail384: // Need to decrypt up to 384 bytes - prepare six blocks VMOVDQA ·chacha20Constants<>+0(SB), Y0 VMOVDQA Y0, Y5 VMOVDQA Y0, Y6 VMOVDQA 32(BP), Y14 VMOVDQA Y14, Y9 VMOVDQA Y14, Y10 VMOVDQA 64(BP), Y12 VMOVDQA Y12, Y13 VMOVDQA Y12, Y8 VMOVDQA 192(BP), Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 VMOVDQA Y4, 96(BP) VMOVDQA Y1, 128(BP) VMOVDQA Y2, 160(BP) // Compute the number of iterations that will hash two blocks of data MOVQ BX, 224(BP) MOVQ BX, CX SUBQ $0x00000100, CX SHRQ $0x04, CX ADDQ $0x06, CX MOVQ $0x0000000a, R9 CMPQ CX, $0x0a CMOVQGT R9, CX MOVQ SI, BX XORQ R9, R9 openAVX2Tail384LoopB: ADDQ (BX), R10 ADCQ 8(BX), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(BX), BX openAVX2Tail384LoopA: VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x0c, Y10, Y3 VPSRLD $0x14, Y10, Y10 VPXOR Y3, Y10, Y10 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x07, Y10, Y3 VPSRLD $0x19, Y10, Y10 VPXOR Y3, Y10, Y10 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x04, Y10, Y10, Y10 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x0c, Y1, Y1, Y1 VPALIGNR $0x0c, Y2, Y2, Y2 ADDQ (BX), R10 ADCQ 8(BX), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(BX), BX INCQ R9 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x0c, Y10, Y3 VPSRLD $0x14, Y10, Y10 VPXOR Y3, Y10, Y10 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x07, Y10, Y3 VPSRLD $0x19, Y10, Y10 VPXOR Y3, Y10, Y10 VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x0c, Y10, Y10, Y10 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x04, Y1, Y1, Y1 VPALIGNR $0x04, Y2, Y2, Y2 CMPQ R9, CX JB openAVX2Tail384LoopB CMPQ R9, $0x0a JNE openAVX2Tail384LoopA MOVQ BX, R9 SUBQ SI, BX MOVQ BX, CX MOVQ 224(BP), BX openAVX2Tail384Hash: ADDQ $0x10, CX CMPQ CX, BX JGT openAVX2Tail384HashEnd ADDQ (R9), R10 ADCQ 8(R9), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(R9), R9 JMP openAVX2Tail384Hash openAVX2Tail384HashEnd: VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 VPADDD 32(BP), Y14, Y14 VPADDD 32(BP), Y9, Y9 VPADDD 32(BP), Y10, Y10 VPADDD 64(BP), Y12, Y12 VPADDD 64(BP), Y13, Y13 VPADDD 64(BP), Y8, Y8 VPADDD 96(BP), Y4, Y4 VPADDD 128(BP), Y1, Y1 VPADDD 160(BP), Y2, Y2 VPERM2I128 $0x02, Y0, Y14, Y3 VPERM2I128 $0x02, Y12, Y4, Y7 VPERM2I128 $0x13, Y0, Y14, Y11 VPERM2I128 $0x13, Y12, Y4, Y15 VPXOR (SI), Y3, Y3 VPXOR 32(SI), Y7, Y7 VPXOR 64(SI), Y11, Y11 VPXOR 96(SI), Y15, Y15 VMOVDQU Y3, (DI) VMOVDQU Y7, 32(DI) VMOVDQU Y11, 64(DI) VMOVDQU Y15, 96(DI) VPERM2I128 $0x02, Y5, Y9, Y3 VPERM2I128 $0x02, Y13, Y1, Y7 VPERM2I128 $0x13, Y5, Y9, Y11 VPERM2I128 $0x13, Y13, Y1, Y15 VPXOR 128(SI), Y3, Y3 VPXOR 160(SI), Y7, Y7 VPXOR 192(SI), Y11, Y11 VPXOR 224(SI), Y15, Y15 VMOVDQU Y3, 128(DI) VMOVDQU Y7, 160(DI) VMOVDQU Y11, 192(DI) VMOVDQU Y15, 224(DI) VPERM2I128 $0x02, Y6, Y10, Y0 VPERM2I128 $0x02, Y8, Y2, Y14 VPERM2I128 $0x13, Y6, Y10, Y12 VPERM2I128 $0x13, Y8, Y2, Y4 LEAQ 256(SI), SI LEAQ 256(DI), DI SUBQ $0x00000100, BX JMP openAVX2TailLoop openAVX2Tail512: VMOVDQU ·chacha20Constants<>+0(SB), Y0 VMOVDQA Y0, Y5 VMOVDQA Y0, Y6 VMOVDQA Y0, Y7 VMOVDQA 32(BP), Y14 VMOVDQA Y14, Y9 VMOVDQA Y14, Y10 VMOVDQA Y14, Y11 VMOVDQA 64(BP), Y12 VMOVDQA Y12, Y13 VMOVDQA Y12, Y8 VMOVDQA Y12, Y15 VMOVDQA 192(BP), Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 VMOVDQA Y4, 96(BP) VMOVDQA Y1, 128(BP) VMOVDQA Y2, 160(BP) VMOVDQA Y3, 192(BP) XORQ CX, CX MOVQ SI, R9 openAVX2Tail512LoopB: ADDQ (R9), R10 ADCQ 8(R9), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(R9), R9 openAVX2Tail512LoopA: VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y3, Y3 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 VMOVDQA Y15, 224(BP) VPSLLD $0x0c, Y14, Y15 VPSRLD $0x14, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x0c, Y9, Y15 VPSRLD $0x14, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x0c, Y10, Y15 VPSRLD $0x14, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x0c, Y11, Y15 VPSRLD $0x14, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 ADDQ (R9), R10 ADCQ 8(R9), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y3, Y3 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 VMOVDQA Y15, 224(BP) VPSLLD $0x07, Y14, Y15 VPSRLD $0x19, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x07, Y9, Y15 VPSRLD $0x19, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x07, Y10, Y15 VPSRLD $0x19, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x07, Y11, Y15 VPSRLD $0x19, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x04, Y10, Y10, Y10 VPALIGNR $0x04, Y11, Y11, Y11 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x08, Y15, Y15, Y15 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x0c, Y1, Y1, Y1 VPALIGNR $0x0c, Y2, Y2, Y2 VPALIGNR $0x0c, Y3, Y3, Y3 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y3, Y3 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 ADDQ 16(R9), R10 ADCQ 24(R9), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 32(R9), R9 VMOVDQA Y15, 224(BP) VPSLLD $0x0c, Y14, Y15 VPSRLD $0x14, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x0c, Y9, Y15 VPSRLD $0x14, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x0c, Y10, Y15 VPSRLD $0x14, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x0c, Y11, Y15 VPSRLD $0x14, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y3, Y3 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 VMOVDQA Y15, 224(BP) VPSLLD $0x07, Y14, Y15 VPSRLD $0x19, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x07, Y9, Y15 VPSRLD $0x19, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x07, Y10, Y15 VPSRLD $0x19, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x07, Y11, Y15 VPSRLD $0x19, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x0c, Y10, Y10, Y10 VPALIGNR $0x0c, Y11, Y11, Y11 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x08, Y15, Y15, Y15 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x04, Y1, Y1, Y1 VPALIGNR $0x04, Y2, Y2, Y2 VPALIGNR $0x04, Y3, Y3, Y3 INCQ CX CMPQ CX, $0x04 JLT openAVX2Tail512LoopB CMPQ CX, $0x0a JNE openAVX2Tail512LoopA MOVQ BX, CX SUBQ $0x00000180, CX ANDQ $-16, CX openAVX2Tail512HashLoop: TESTQ CX, CX JE openAVX2Tail512HashEnd ADDQ (R9), R10 ADCQ 8(R9), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(R9), R9 SUBQ $0x10, CX JMP openAVX2Tail512HashLoop openAVX2Tail512HashEnd: VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 VPADDD 32(BP), Y14, Y14 VPADDD 32(BP), Y9, Y9 VPADDD 32(BP), Y10, Y10 VPADDD 32(BP), Y11, Y11 VPADDD 64(BP), Y12, Y12 VPADDD 64(BP), Y13, Y13 VPADDD 64(BP), Y8, Y8 VPADDD 64(BP), Y15, Y15 VPADDD 96(BP), Y4, Y4 VPADDD 128(BP), Y1, Y1 VPADDD 160(BP), Y2, Y2 VPADDD 192(BP), Y3, Y3 VMOVDQA Y15, 224(BP) VPERM2I128 $0x02, Y0, Y14, Y15 VPERM2I128 $0x13, Y0, Y14, Y14 VPERM2I128 $0x02, Y12, Y4, Y0 VPERM2I128 $0x13, Y12, Y4, Y12 VPXOR (SI), Y15, Y15 VPXOR 32(SI), Y0, Y0 VPXOR 64(SI), Y14, Y14 VPXOR 96(SI), Y12, Y12 VMOVDQU Y15, (DI) VMOVDQU Y0, 32(DI) VMOVDQU Y14, 64(DI) VMOVDQU Y12, 96(DI) VPERM2I128 $0x02, Y5, Y9, Y0 VPERM2I128 $0x02, Y13, Y1, Y14 VPERM2I128 $0x13, Y5, Y9, Y12 VPERM2I128 $0x13, Y13, Y1, Y4 VPXOR 128(SI), Y0, Y0 VPXOR 160(SI), Y14, Y14 VPXOR 192(SI), Y12, Y12 VPXOR 224(SI), Y4, Y4 VMOVDQU Y0, 128(DI) VMOVDQU Y14, 160(DI) VMOVDQU Y12, 192(DI) VMOVDQU Y4, 224(DI) VPERM2I128 $0x02, Y6, Y10, Y0 VPERM2I128 $0x02, Y8, Y2, Y14 VPERM2I128 $0x13, Y6, Y10, Y12 VPERM2I128 $0x13, Y8, Y2, Y4 VPXOR 256(SI), Y0, Y0 VPXOR 288(SI), Y14, Y14 VPXOR 320(SI), Y12, Y12 VPXOR 352(SI), Y4, Y4 VMOVDQU Y0, 256(DI) VMOVDQU Y14, 288(DI) VMOVDQU Y12, 320(DI) VMOVDQU Y4, 352(DI) VPERM2I128 $0x02, Y7, Y11, Y0 VPERM2I128 $0x02, 224(BP), Y3, Y14 VPERM2I128 $0x13, Y7, Y11, Y12 VPERM2I128 $0x13, 224(BP), Y3, Y4 LEAQ 384(SI), SI LEAQ 384(DI), DI SUBQ $0x00000180, BX JMP openAVX2TailLoop DATA ·chacha20Constants<>+0(SB)/4, $0x61707865 DATA ·chacha20Constants<>+4(SB)/4, $0x3320646e DATA ·chacha20Constants<>+8(SB)/4, $0x79622d32 DATA ·chacha20Constants<>+12(SB)/4, $0x6b206574 DATA ·chacha20Constants<>+16(SB)/4, $0x61707865 DATA ·chacha20Constants<>+20(SB)/4, $0x3320646e DATA ·chacha20Constants<>+24(SB)/4, $0x79622d32 DATA ·chacha20Constants<>+28(SB)/4, $0x6b206574 GLOBL ·chacha20Constants<>(SB), RODATA|NOPTR, $32 DATA ·polyClampMask<>+0(SB)/8, $0x0ffffffc0fffffff DATA ·polyClampMask<>+8(SB)/8, $0x0ffffffc0ffffffc DATA ·polyClampMask<>+16(SB)/8, $0xffffffffffffffff DATA ·polyClampMask<>+24(SB)/8, $0xffffffffffffffff GLOBL ·polyClampMask<>(SB), RODATA|NOPTR, $32 DATA ·sseIncMask<>+0(SB)/8, $0x0000000000000001 DATA ·sseIncMask<>+8(SB)/8, $0x0000000000000000 GLOBL ·sseIncMask<>(SB), RODATA|NOPTR, $16 DATA ·andMask<>+0(SB)/8, $0x00000000000000ff DATA ·andMask<>+8(SB)/8, $0x0000000000000000 DATA ·andMask<>+16(SB)/8, $0x000000000000ffff DATA ·andMask<>+24(SB)/8, $0x0000000000000000 DATA ·andMask<>+32(SB)/8, $0x0000000000ffffff DATA ·andMask<>+40(SB)/8, $0x0000000000000000 DATA ·andMask<>+48(SB)/8, $0x00000000ffffffff DATA ·andMask<>+56(SB)/8, $0x0000000000000000 DATA ·andMask<>+64(SB)/8, $0x000000ffffffffff DATA ·andMask<>+72(SB)/8, $0x0000000000000000 DATA ·andMask<>+80(SB)/8, $0x0000ffffffffffff DATA ·andMask<>+88(SB)/8, $0x0000000000000000 DATA ·andMask<>+96(SB)/8, $0x00ffffffffffffff DATA ·andMask<>+104(SB)/8, $0x0000000000000000 DATA ·andMask<>+112(SB)/8, $0xffffffffffffffff DATA ·andMask<>+120(SB)/8, $0x0000000000000000 DATA ·andMask<>+128(SB)/8, $0xffffffffffffffff DATA ·andMask<>+136(SB)/8, $0x00000000000000ff DATA ·andMask<>+144(SB)/8, $0xffffffffffffffff DATA ·andMask<>+152(SB)/8, $0x000000000000ffff DATA ·andMask<>+160(SB)/8, $0xffffffffffffffff DATA ·andMask<>+168(SB)/8, $0x0000000000ffffff DATA ·andMask<>+176(SB)/8, $0xffffffffffffffff DATA ·andMask<>+184(SB)/8, $0x00000000ffffffff DATA ·andMask<>+192(SB)/8, $0xffffffffffffffff DATA ·andMask<>+200(SB)/8, $0x000000ffffffffff DATA ·andMask<>+208(SB)/8, $0xffffffffffffffff DATA ·andMask<>+216(SB)/8, $0x0000ffffffffffff DATA ·andMask<>+224(SB)/8, $0xffffffffffffffff DATA ·andMask<>+232(SB)/8, $0x00ffffffffffffff GLOBL ·andMask<>(SB), RODATA|NOPTR, $240 DATA ·avx2InitMask<>+0(SB)/8, $0x0000000000000000 DATA ·avx2InitMask<>+8(SB)/8, $0x0000000000000000 DATA ·avx2InitMask<>+16(SB)/8, $0x0000000000000001 DATA ·avx2InitMask<>+24(SB)/8, $0x0000000000000000 GLOBL ·avx2InitMask<>(SB), RODATA|NOPTR, $32 DATA ·rol16<>+0(SB)/8, $0x0504070601000302 DATA ·rol16<>+8(SB)/8, $0x0d0c0f0e09080b0a DATA ·rol16<>+16(SB)/8, $0x0504070601000302 DATA ·rol16<>+24(SB)/8, $0x0d0c0f0e09080b0a GLOBL ·rol16<>(SB), RODATA|NOPTR, $32 DATA ·rol8<>+0(SB)/8, $0x0605040702010003 DATA ·rol8<>+8(SB)/8, $0x0e0d0c0f0a09080b DATA ·rol8<>+16(SB)/8, $0x0605040702010003 DATA ·rol8<>+24(SB)/8, $0x0e0d0c0f0a09080b GLOBL ·rol8<>(SB), RODATA|NOPTR, $32 DATA ·avx2IncMask<>+0(SB)/8, $0x0000000000000002 DATA ·avx2IncMask<>+8(SB)/8, $0x0000000000000000 DATA ·avx2IncMask<>+16(SB)/8, $0x0000000000000002 DATA ·avx2IncMask<>+24(SB)/8, $0x0000000000000000 GLOBL ·avx2IncMask<>(SB), RODATA|NOPTR, $32 // func chacha20Poly1305Seal(dst []byte, key []uint32, src []byte, ad []byte) // Requires: AVX, AVX2, BMI2, CMOV, SSE2 TEXT ·chacha20Poly1305Seal(SB), $288-96 MOVQ SP, BP ADDQ $0x20, BP ANDQ $-32, BP MOVQ dst_base+0(FP), DI MOVQ key_base+24(FP), R8 MOVQ src_base+48(FP), SI MOVQ src_len+56(FP), BX MOVQ ad_base+72(FP), CX CMPB ·useAVX2+0(SB), $0x01 JE chacha20Poly1305Seal_AVX2 // Special optimization, for very short buffers CMPQ BX, $0x80 JBE sealSSE128 // In the seal case - prepare the poly key + 3 blocks of stream in the first iteration MOVOU ·chacha20Constants<>+0(SB), X0 MOVOU 16(R8), X3 MOVOU 32(R8), X6 MOVOU 48(R8), X9 // Store state on stack for future use MOVO X3, 32(BP) MOVO X6, 48(BP) // Load state, increment counter blocks MOVO X0, X1 MOVO X3, X4 MOVO X6, X7 MOVO X9, X10 PADDL ·sseIncMask<>+0(SB), X10 MOVO X1, X2 MOVO X4, X5 MOVO X7, X8 MOVO X10, X11 PADDL ·sseIncMask<>+0(SB), X11 MOVO X2, X12 MOVO X5, X13 MOVO X8, X14 MOVO X11, X15 PADDL ·sseIncMask<>+0(SB), X15 // Store counters MOVO X9, 80(BP) MOVO X10, 96(BP) MOVO X11, 112(BP) MOVO X15, 128(BP) MOVQ $0x0000000a, R9 sealSSEIntroLoop: MOVO X14, 64(BP) PADDD X3, X0 PXOR X0, X9 ROL16(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x0c, X14 PSRLL $0x14, X3 PXOR X14, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x07, X14 PSRLL $0x19, X3 PXOR X14, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x0c, X14 PSRLL $0x14, X4 PXOR X14, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x07, X14 PSRLL $0x19, X4 PXOR X14, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x0c, X14 PSRLL $0x14, X5 PXOR X14, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x07, X14 PSRLL $0x19, X5 PXOR X14, X5 MOVO 64(BP), X14 MOVO X7, 64(BP) PADDD X13, X12 PXOR X12, X15 ROL16(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x0c, X7 PSRLL $0x14, X13 PXOR X7, X13 PADDD X13, X12 PXOR X12, X15 ROL8(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x07, X7 PSRLL $0x19, X13 PXOR X7, X13 MOVO 64(BP), X7 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x0c MOVO X14, 64(BP) PADDD X3, X0 PXOR X0, X9 ROL16(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x0c, X14 PSRLL $0x14, X3 PXOR X14, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x07, X14 PSRLL $0x19, X3 PXOR X14, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x0c, X14 PSRLL $0x14, X4 PXOR X14, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x07, X14 PSRLL $0x19, X4 PXOR X14, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x0c, X14 PSRLL $0x14, X5 PXOR X14, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x07, X14 PSRLL $0x19, X5 PXOR X14, X5 MOVO 64(BP), X14 MOVO X7, 64(BP) PADDD X13, X12 PXOR X12, X15 ROL16(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x0c, X7 PSRLL $0x14, X13 PXOR X7, X13 PADDD X13, X12 PXOR X12, X15 ROL8(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x07, X7 PSRLL $0x19, X13 PXOR X7, X13 MOVO 64(BP), X7 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x04 DECQ R9 JNE sealSSEIntroLoop // Add in the state PADDD ·chacha20Constants<>+0(SB), X0 PADDD ·chacha20Constants<>+0(SB), X1 PADDD ·chacha20Constants<>+0(SB), X2 PADDD ·chacha20Constants<>+0(SB), X12 PADDD 32(BP), X3 PADDD 32(BP), X4 PADDD 32(BP), X5 PADDD 32(BP), X13 PADDD 48(BP), X7 PADDD 48(BP), X8 PADDD 48(BP), X14 PADDD 96(BP), X10 PADDD 112(BP), X11 PADDD 128(BP), X15 // Clamp and store the key PAND ·polyClampMask<>+0(SB), X0 MOVO X0, (BP) MOVO X3, 16(BP) // Hash AAD MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) MOVOU (SI), X0 MOVOU 16(SI), X3 MOVOU 32(SI), X6 MOVOU 48(SI), X9 PXOR X0, X1 PXOR X3, X4 PXOR X6, X7 PXOR X9, X10 MOVOU X1, (DI) MOVOU X4, 16(DI) MOVOU X7, 32(DI) MOVOU X10, 48(DI) MOVOU 64(SI), X0 MOVOU 80(SI), X3 MOVOU 96(SI), X6 MOVOU 112(SI), X9 PXOR X0, X2 PXOR X3, X5 PXOR X6, X8 PXOR X9, X11 MOVOU X2, 64(DI) MOVOU X5, 80(DI) MOVOU X8, 96(DI) MOVOU X11, 112(DI) MOVQ $0x00000080, CX SUBQ $0x80, BX LEAQ 128(SI), SI MOVO X12, X1 MOVO X13, X4 MOVO X14, X7 MOVO X15, X10 CMPQ BX, $0x40 JBE sealSSE128SealHash MOVOU (SI), X0 MOVOU 16(SI), X3 MOVOU 32(SI), X6 MOVOU 48(SI), X9 PXOR X0, X12 PXOR X3, X13 PXOR X6, X14 PXOR X9, X15 MOVOU X12, 128(DI) MOVOU X13, 144(DI) MOVOU X14, 160(DI) MOVOU X15, 176(DI) ADDQ $0x40, CX SUBQ $0x40, BX LEAQ 64(SI), SI MOVQ $0x00000002, CX MOVQ $0x00000008, R9 CMPQ BX, $0x40 JBE sealSSETail64 CMPQ BX, $0x80 JBE sealSSETail128 CMPQ BX, $0xc0 JBE sealSSETail192 sealSSEMainLoop: // Load state, increment counter blocks MOVO ·chacha20Constants<>+0(SB), X0 MOVO 32(BP), X3 MOVO 48(BP), X6 MOVO 128(BP), X9 PADDL ·sseIncMask<>+0(SB), X9 MOVO X0, X1 MOVO X3, X4 MOVO X6, X7 MOVO X9, X10 PADDL ·sseIncMask<>+0(SB), X10 MOVO X1, X2 MOVO X4, X5 MOVO X7, X8 MOVO X10, X11 PADDL ·sseIncMask<>+0(SB), X11 MOVO X2, X12 MOVO X5, X13 MOVO X8, X14 MOVO X11, X15 PADDL ·sseIncMask<>+0(SB), X15 // Store counters MOVO X9, 80(BP) MOVO X10, 96(BP) MOVO X11, 112(BP) MOVO X15, 128(BP) sealSSEInnerLoop: MOVO X14, 64(BP) PADDD X3, X0 PXOR X0, X9 ROL16(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x0c, X14 PSRLL $0x14, X3 PXOR X14, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x07, X14 PSRLL $0x19, X3 PXOR X14, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x0c, X14 PSRLL $0x14, X4 PXOR X14, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x07, X14 PSRLL $0x19, X4 PXOR X14, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x0c, X14 PSRLL $0x14, X5 PXOR X14, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x07, X14 PSRLL $0x19, X5 PXOR X14, X5 MOVO 64(BP), X14 MOVO X7, 64(BP) PADDD X13, X12 PXOR X12, X15 ROL16(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x0c, X7 PSRLL $0x14, X13 PXOR X7, X13 PADDD X13, X12 PXOR X12, X15 ROL8(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x07, X7 PSRLL $0x19, X13 PXOR X7, X13 MOVO 64(BP), X7 ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x0c MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX LEAQ 16(DI), DI MOVO X14, 64(BP) PADDD X3, X0 PXOR X0, X9 ROL16(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x0c, X14 PSRLL $0x14, X3 PXOR X14, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X14) PADDD X9, X6 PXOR X6, X3 MOVO X3, X14 PSLLL $0x07, X14 PSRLL $0x19, X3 PXOR X14, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x0c, X14 PSRLL $0x14, X4 PXOR X14, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X14) PADDD X10, X7 PXOR X7, X4 MOVO X4, X14 PSLLL $0x07, X14 PSRLL $0x19, X4 PXOR X14, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x0c, X14 PSRLL $0x14, X5 PXOR X14, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X14) PADDD X11, X8 PXOR X8, X5 MOVO X5, X14 PSLLL $0x07, X14 PSRLL $0x19, X5 PXOR X14, X5 MOVO 64(BP), X14 MOVO X7, 64(BP) IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 PADDD X13, X12 PXOR X12, X15 ROL16(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x0c, X7 PSRLL $0x14, X13 PXOR X7, X13 PADDD X13, X12 PXOR X12, X15 ROL8(X15, X7) PADDD X15, X14 PXOR X14, X13 MOVO X13, X7 PSLLL $0x07, X7 PSRLL $0x19, X13 PXOR X7, X13 MOVO 64(BP), X7 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x04 DECQ R9 JGE sealSSEInnerLoop ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(DI), DI DECQ CX JG sealSSEInnerLoop // Add in the state PADDD ·chacha20Constants<>+0(SB), X0 PADDD ·chacha20Constants<>+0(SB), X1 PADDD ·chacha20Constants<>+0(SB), X2 PADDD ·chacha20Constants<>+0(SB), X12 PADDD 32(BP), X3 PADDD 32(BP), X4 PADDD 32(BP), X5 PADDD 32(BP), X13 PADDD 48(BP), X6 PADDD 48(BP), X7 PADDD 48(BP), X8 PADDD 48(BP), X14 PADDD 80(BP), X9 PADDD 96(BP), X10 PADDD 112(BP), X11 PADDD 128(BP), X15 MOVO X15, 64(BP) // Load - xor - store MOVOU (SI), X15 PXOR X15, X0 MOVOU 16(SI), X15 PXOR X15, X3 MOVOU 32(SI), X15 PXOR X15, X6 MOVOU 48(SI), X15 PXOR X15, X9 MOVOU X0, (DI) MOVOU X3, 16(DI) MOVOU X6, 32(DI) MOVOU X9, 48(DI) MOVO 64(BP), X15 MOVOU 64(SI), X0 MOVOU 80(SI), X3 MOVOU 96(SI), X6 MOVOU 112(SI), X9 PXOR X0, X1 PXOR X3, X4 PXOR X6, X7 PXOR X9, X10 MOVOU X1, 64(DI) MOVOU X4, 80(DI) MOVOU X7, 96(DI) MOVOU X10, 112(DI) MOVOU 128(SI), X0 MOVOU 144(SI), X3 MOVOU 160(SI), X6 MOVOU 176(SI), X9 PXOR X0, X2 PXOR X3, X5 PXOR X6, X8 PXOR X9, X11 MOVOU X2, 128(DI) MOVOU X5, 144(DI) MOVOU X8, 160(DI) MOVOU X11, 176(DI) ADDQ $0xc0, SI MOVQ $0x000000c0, CX SUBQ $0xc0, BX MOVO X12, X1 MOVO X13, X4 MOVO X14, X7 MOVO X15, X10 CMPQ BX, $0x40 JBE sealSSE128SealHash MOVOU (SI), X0 MOVOU 16(SI), X3 MOVOU 32(SI), X6 MOVOU 48(SI), X9 PXOR X0, X12 PXOR X3, X13 PXOR X6, X14 PXOR X9, X15 MOVOU X12, 192(DI) MOVOU X13, 208(DI) MOVOU X14, 224(DI) MOVOU X15, 240(DI) LEAQ 64(SI), SI SUBQ $0x40, BX MOVQ $0x00000006, CX MOVQ $0x00000004, R9 CMPQ BX, $0xc0 JG sealSSEMainLoop MOVQ BX, CX TESTQ BX, BX JE sealSSE128SealHash MOVQ $0x00000006, CX CMPQ BX, $0x40 JBE sealSSETail64 CMPQ BX, $0x80 JBE sealSSETail128 JMP sealSSETail192 sealSSETail64: MOVO ·chacha20Constants<>+0(SB), X1 MOVO 32(BP), X4 MOVO 48(BP), X7 MOVO 128(BP), X10 PADDL ·sseIncMask<>+0(SB), X10 MOVO X10, 80(BP) sealSSETail64LoopA: ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(DI), DI sealSSETail64LoopB: PADDD X4, X1 PXOR X1, X10 ROL16(X10, X13) PADDD X10, X7 PXOR X7, X4 MOVO X4, X13 PSLLL $0x0c, X13 PSRLL $0x14, X4 PXOR X13, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X13) PADDD X10, X7 PXOR X7, X4 MOVO X4, X13 PSLLL $0x07, X13 PSRLL $0x19, X4 PXOR X13, X4 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x0c PADDD X4, X1 PXOR X1, X10 ROL16(X10, X13) PADDD X10, X7 PXOR X7, X4 MOVO X4, X13 PSLLL $0x0c, X13 PSRLL $0x14, X4 PXOR X13, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X13) PADDD X10, X7 PXOR X7, X4 MOVO X4, X13 PSLLL $0x07, X13 PSRLL $0x19, X4 PXOR X13, X4 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x04 ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(DI), DI DECQ CX JG sealSSETail64LoopA DECQ R9 JGE sealSSETail64LoopB PADDL ·chacha20Constants<>+0(SB), X1 PADDL 32(BP), X4 PADDL 48(BP), X7 PADDL 80(BP), X10 JMP sealSSE128Seal sealSSETail128: MOVO ·chacha20Constants<>+0(SB), X0 MOVO 32(BP), X3 MOVO 48(BP), X6 MOVO 128(BP), X9 PADDL ·sseIncMask<>+0(SB), X9 MOVO X9, 80(BP) MOVO X0, X1 MOVO X3, X4 MOVO X6, X7 MOVO X9, X10 PADDL ·sseIncMask<>+0(SB), X10 MOVO X10, 96(BP) sealSSETail128LoopA: ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(DI), DI sealSSETail128LoopB: PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x0c, X12 PSRLL $0x14, X4 PXOR X12, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x07, X12 PSRLL $0x19, X4 PXOR X12, X4 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x0c ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(DI), DI PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x0c, X12 PSRLL $0x14, X4 PXOR X12, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x07, X12 PSRLL $0x19, X4 PXOR X12, X4 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x04 DECQ CX JG sealSSETail128LoopA DECQ R9 JGE sealSSETail128LoopB PADDL ·chacha20Constants<>+0(SB), X0 PADDL ·chacha20Constants<>+0(SB), X1 PADDL 32(BP), X3 PADDL 32(BP), X4 PADDL 48(BP), X6 PADDL 48(BP), X7 PADDL 80(BP), X9 PADDL 96(BP), X10 MOVOU (SI), X12 MOVOU 16(SI), X13 MOVOU 32(SI), X14 MOVOU 48(SI), X15 PXOR X12, X0 PXOR X13, X3 PXOR X14, X6 PXOR X15, X9 MOVOU X0, (DI) MOVOU X3, 16(DI) MOVOU X6, 32(DI) MOVOU X9, 48(DI) MOVQ $0x00000040, CX LEAQ 64(SI), SI SUBQ $0x40, BX JMP sealSSE128SealHash sealSSETail192: MOVO ·chacha20Constants<>+0(SB), X0 MOVO 32(BP), X3 MOVO 48(BP), X6 MOVO 128(BP), X9 PADDL ·sseIncMask<>+0(SB), X9 MOVO X9, 80(BP) MOVO X0, X1 MOVO X3, X4 MOVO X6, X7 MOVO X9, X10 PADDL ·sseIncMask<>+0(SB), X10 MOVO X10, 96(BP) MOVO X1, X2 MOVO X4, X5 MOVO X7, X8 MOVO X10, X11 PADDL ·sseIncMask<>+0(SB), X11 MOVO X11, 112(BP) sealSSETail192LoopA: ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(DI), DI sealSSETail192LoopB: PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x0c, X12 PSRLL $0x14, X4 PXOR X12, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x07, X12 PSRLL $0x19, X4 PXOR X12, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x0c, X12 PSRLL $0x14, X5 PXOR X12, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x07, X12 PSRLL $0x19, X5 PXOR X12, X5 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(DI), DI PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x0c, X12 PSRLL $0x14, X4 PXOR X12, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x07, X12 PSRLL $0x19, X4 PXOR X12, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x0c, X12 PSRLL $0x14, X5 PXOR X12, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x07, X12 PSRLL $0x19, X5 PXOR X12, X5 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 DECQ CX JG sealSSETail192LoopA DECQ R9 JGE sealSSETail192LoopB PADDL ·chacha20Constants<>+0(SB), X0 PADDL ·chacha20Constants<>+0(SB), X1 PADDL ·chacha20Constants<>+0(SB), X2 PADDL 32(BP), X3 PADDL 32(BP), X4 PADDL 32(BP), X5 PADDL 48(BP), X6 PADDL 48(BP), X7 PADDL 48(BP), X8 PADDL 80(BP), X9 PADDL 96(BP), X10 PADDL 112(BP), X11 MOVOU (SI), X12 MOVOU 16(SI), X13 MOVOU 32(SI), X14 MOVOU 48(SI), X15 PXOR X12, X0 PXOR X13, X3 PXOR X14, X6 PXOR X15, X9 MOVOU X0, (DI) MOVOU X3, 16(DI) MOVOU X6, 32(DI) MOVOU X9, 48(DI) MOVOU 64(SI), X12 MOVOU 80(SI), X13 MOVOU 96(SI), X14 MOVOU 112(SI), X15 PXOR X12, X1 PXOR X13, X4 PXOR X14, X7 PXOR X15, X10 MOVOU X1, 64(DI) MOVOU X4, 80(DI) MOVOU X7, 96(DI) MOVOU X10, 112(DI) MOVO X2, X1 MOVO X5, X4 MOVO X8, X7 MOVO X11, X10 MOVQ $0x00000080, CX LEAQ 128(SI), SI SUBQ $0x80, BX JMP sealSSE128SealHash sealSSE128: MOVOU ·chacha20Constants<>+0(SB), X0 MOVOU 16(R8), X3 MOVOU 32(R8), X6 MOVOU 48(R8), X9 MOVO X0, X1 MOVO X3, X4 MOVO X6, X7 MOVO X9, X10 PADDL ·sseIncMask<>+0(SB), X10 MOVO X1, X2 MOVO X4, X5 MOVO X7, X8 MOVO X10, X11 PADDL ·sseIncMask<>+0(SB), X11 MOVO X3, X13 MOVO X6, X14 MOVO X10, X15 MOVQ $0x0000000a, R9 sealSSE128InnerCipherLoop: PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x0c, X12 PSRLL $0x14, X4 PXOR X12, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x07, X12 PSRLL $0x19, X4 PXOR X12, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x0c, X12 PSRLL $0x14, X5 PXOR X12, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x07, X12 PSRLL $0x19, X5 PXOR X12, X5 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x04 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x0c BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c PADDD X3, X0 PXOR X0, X9 ROL16(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x0c, X12 PSRLL $0x14, X3 PXOR X12, X3 PADDD X3, X0 PXOR X0, X9 ROL8(X9, X12) PADDD X9, X6 PXOR X6, X3 MOVO X3, X12 PSLLL $0x07, X12 PSRLL $0x19, X3 PXOR X12, X3 PADDD X4, X1 PXOR X1, X10 ROL16(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x0c, X12 PSRLL $0x14, X4 PXOR X12, X4 PADDD X4, X1 PXOR X1, X10 ROL8(X10, X12) PADDD X10, X7 PXOR X7, X4 MOVO X4, X12 PSLLL $0x07, X12 PSRLL $0x19, X4 PXOR X12, X4 PADDD X5, X2 PXOR X2, X11 ROL16(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x0c, X12 PSRLL $0x14, X5 PXOR X12, X5 PADDD X5, X2 PXOR X2, X11 ROL8(X11, X12) PADDD X11, X8 PXOR X8, X5 MOVO X5, X12 PSLLL $0x07, X12 PSRLL $0x19, X5 PXOR X12, X5 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xe4 BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xed BYTE $0x0c BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xf6 BYTE $0x08 BYTE $0x66 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xff BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc0 BYTE $0x08 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xc9 BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xd2 BYTE $0x04 BYTE $0x66 BYTE $0x45 BYTE $0x0f BYTE $0x3a BYTE $0x0f BYTE $0xdb BYTE $0x04 DECQ R9 JNE sealSSE128InnerCipherLoop // A0|B0 hold the Poly1305 32-byte key, C0,D0 can be discarded PADDL ·chacha20Constants<>+0(SB), X0 PADDL ·chacha20Constants<>+0(SB), X1 PADDL ·chacha20Constants<>+0(SB), X2 PADDL X13, X3 PADDL X13, X4 PADDL X13, X5 PADDL X14, X7 PADDL X14, X8 PADDL X15, X10 PADDL ·sseIncMask<>+0(SB), X15 PADDL X15, X11 PAND ·polyClampMask<>+0(SB), X0 MOVOU X0, (BP) MOVOU X3, 16(BP) // Hash MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) XORQ CX, CX sealSSE128SealHash: CMPQ CX, $0x10 JB sealSSE128Seal ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 SUBQ $0x10, CX ADDQ $0x10, DI JMP sealSSE128SealHash sealSSE128Seal: CMPQ BX, $0x10 JB sealSSETail SUBQ $0x10, BX // Load for decryption MOVOU (SI), X12 PXOR X12, X1 MOVOU X1, (DI) LEAQ 16(SI), SI LEAQ 16(DI), DI // Extract for hashing MOVQ X1, R13 PSRLDQ $0x08, X1 MOVQ X1, R14 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 // Shift the stream "left" MOVO X4, X1 MOVO X7, X4 MOVO X10, X7 MOVO X2, X10 MOVO X5, X2 MOVO X8, X5 MOVO X11, X8 JMP sealSSE128Seal sealSSETail: TESTQ BX, BX JE sealSSEFinalize // We can only load the PT one byte at a time to avoid read after end of buffer MOVQ BX, R9 SHLQ $0x04, R9 LEAQ ·andMask<>+0(SB), R13 MOVQ BX, CX LEAQ -1(SI)(BX*1), SI XORQ R15, R15 XORQ R8, R8 XORQ AX, AX sealSSETailLoadLoop: SHLQ $0x08, R15, R8 SHLQ $0x08, R15 MOVB (SI), AX XORQ AX, R15 LEAQ -1(SI), SI DECQ CX JNE sealSSETailLoadLoop MOVQ R15, 64(BP) MOVQ R8, 72(BP) PXOR 64(BP), X1 MOVOU X1, (DI) MOVOU -16(R13)(R9*1), X12 PAND X12, X1 MOVQ X1, R13 PSRLDQ $0x08, X1 MOVQ X1, R14 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 ADDQ BX, DI sealSSEFinalize: // Hash in the buffer lengths ADDQ ad_len+80(FP), R10 ADCQ src_len+56(FP), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 // Final reduce MOVQ R10, R13 MOVQ R11, R14 MOVQ R12, R15 SUBQ $-5, R10 SBBQ $-1, R11 SBBQ $0x03, R12 CMOVQCS R13, R10 CMOVQCS R14, R11 CMOVQCS R15, R12 // Add in the "s" part of the key ADDQ 16(BP), R10 ADCQ 24(BP), R11 // Finally store the tag at the end of the message MOVQ R10, (DI) MOVQ R11, 8(DI) RET chacha20Poly1305Seal_AVX2: VZEROUPPER VMOVDQU ·chacha20Constants<>+0(SB), Y0 BYTE $0xc4 BYTE $0x42 BYTE $0x7d BYTE $0x5a BYTE $0x70 BYTE $0x10 BYTE $0xc4 BYTE $0x42 BYTE $0x7d BYTE $0x5a BYTE $0x60 BYTE $0x20 BYTE $0xc4 BYTE $0xc2 BYTE $0x7d BYTE $0x5a BYTE $0x60 BYTE $0x30 VPADDD ·avx2InitMask<>+0(SB), Y4, Y4 // Special optimizations, for very short buffers CMPQ BX, $0x000000c0 JBE seal192AVX2 CMPQ BX, $0x00000140 JBE seal320AVX2 // For the general key prepare the key first - as a byproduct we have 64 bytes of cipher stream VMOVDQA Y0, Y5 VMOVDQA Y0, Y6 VMOVDQA Y0, Y7 VMOVDQA Y14, Y9 VMOVDQA Y14, Y10 VMOVDQA Y14, Y11 VMOVDQA Y14, 32(BP) VMOVDQA Y12, Y13 VMOVDQA Y12, Y8 VMOVDQA Y12, Y15 VMOVDQA Y12, 64(BP) VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VMOVDQA Y4, 96(BP) VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 VMOVDQA Y1, 128(BP) VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 VMOVDQA Y2, 160(BP) VMOVDQA Y3, 192(BP) MOVQ $0x0000000a, R9 sealAVX2IntroLoop: VMOVDQA Y15, 224(BP) VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y15 VPSRLD $0x14, Y14, Y14 VPXOR Y15, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y15 VPSRLD $0x19, Y14, Y14 VPXOR Y15, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y15 VPSRLD $0x14, Y9, Y9 VPXOR Y15, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y15 VPSRLD $0x19, Y9, Y9 VPXOR Y15, Y9, Y9 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x0c, Y10, Y15 VPSRLD $0x14, Y10, Y10 VPXOR Y15, Y10, Y10 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x07, Y10, Y15 VPSRLD $0x19, Y10, Y10 VPXOR Y15, Y10, Y10 VMOVDQA 224(BP), Y15 VMOVDQA Y13, 224(BP) VPADDD Y11, Y7, Y7 VPXOR Y7, Y3, Y3 VPSHUFB ·rol16<>+0(SB), Y3, Y3 VPADDD Y3, Y15, Y15 VPXOR Y15, Y11, Y11 VPSLLD $0x0c, Y11, Y13 VPSRLD $0x14, Y11, Y11 VPXOR Y13, Y11, Y11 VPADDD Y11, Y7, Y7 VPXOR Y7, Y3, Y3 VPSHUFB ·rol8<>+0(SB), Y3, Y3 VPADDD Y3, Y15, Y15 VPXOR Y15, Y11, Y11 VPSLLD $0x07, Y11, Y13 VPSRLD $0x19, Y11, Y11 VPXOR Y13, Y11, Y11 VMOVDQA 224(BP), Y13 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x0c, Y1, Y1, Y1 VPALIGNR $0x04, Y10, Y10, Y10 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x0c, Y2, Y2, Y2 VPALIGNR $0x04, Y11, Y11, Y11 VPALIGNR $0x08, Y15, Y15, Y15 VPALIGNR $0x0c, Y3, Y3, Y3 VMOVDQA Y15, 224(BP) VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y15 VPSRLD $0x14, Y14, Y14 VPXOR Y15, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y15 VPSRLD $0x19, Y14, Y14 VPXOR Y15, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y15 VPSRLD $0x14, Y9, Y9 VPXOR Y15, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y15 VPSRLD $0x19, Y9, Y9 VPXOR Y15, Y9, Y9 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x0c, Y10, Y15 VPSRLD $0x14, Y10, Y10 VPXOR Y15, Y10, Y10 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x07, Y10, Y15 VPSRLD $0x19, Y10, Y10 VPXOR Y15, Y10, Y10 VMOVDQA 224(BP), Y15 VMOVDQA Y13, 224(BP) VPADDD Y11, Y7, Y7 VPXOR Y7, Y3, Y3 VPSHUFB ·rol16<>+0(SB), Y3, Y3 VPADDD Y3, Y15, Y15 VPXOR Y15, Y11, Y11 VPSLLD $0x0c, Y11, Y13 VPSRLD $0x14, Y11, Y11 VPXOR Y13, Y11, Y11 VPADDD Y11, Y7, Y7 VPXOR Y7, Y3, Y3 VPSHUFB ·rol8<>+0(SB), Y3, Y3 VPADDD Y3, Y15, Y15 VPXOR Y15, Y11, Y11 VPSLLD $0x07, Y11, Y13 VPSRLD $0x19, Y11, Y11 VPXOR Y13, Y11, Y11 VMOVDQA 224(BP), Y13 VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x04, Y1, Y1, Y1 VPALIGNR $0x0c, Y10, Y10, Y10 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x04, Y2, Y2, Y2 VPALIGNR $0x0c, Y11, Y11, Y11 VPALIGNR $0x08, Y15, Y15, Y15 VPALIGNR $0x04, Y3, Y3, Y3 DECQ R9 JNE sealAVX2IntroLoop VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 VPADDD 32(BP), Y14, Y14 VPADDD 32(BP), Y9, Y9 VPADDD 32(BP), Y10, Y10 VPADDD 32(BP), Y11, Y11 VPADDD 64(BP), Y12, Y12 VPADDD 64(BP), Y13, Y13 VPADDD 64(BP), Y8, Y8 VPADDD 64(BP), Y15, Y15 VPADDD 96(BP), Y4, Y4 VPADDD 128(BP), Y1, Y1 VPADDD 160(BP), Y2, Y2 VPADDD 192(BP), Y3, Y3 VPERM2I128 $0x13, Y12, Y4, Y12 VPERM2I128 $0x02, Y0, Y14, Y4 VPERM2I128 $0x13, Y0, Y14, Y0 // Clamp and store poly key VPAND ·polyClampMask<>+0(SB), Y4, Y4 VMOVDQA Y4, (BP) // Hash AD MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) // Can store at least 320 bytes VPXOR (SI), Y0, Y0 VPXOR 32(SI), Y12, Y12 VMOVDQU Y0, (DI) VMOVDQU Y12, 32(DI) VPERM2I128 $0x02, Y5, Y9, Y0 VPERM2I128 $0x02, Y13, Y1, Y14 VPERM2I128 $0x13, Y5, Y9, Y12 VPERM2I128 $0x13, Y13, Y1, Y4 VPXOR 64(SI), Y0, Y0 VPXOR 96(SI), Y14, Y14 VPXOR 128(SI), Y12, Y12 VPXOR 160(SI), Y4, Y4 VMOVDQU Y0, 64(DI) VMOVDQU Y14, 96(DI) VMOVDQU Y12, 128(DI) VMOVDQU Y4, 160(DI) VPERM2I128 $0x02, Y6, Y10, Y0 VPERM2I128 $0x02, Y8, Y2, Y14 VPERM2I128 $0x13, Y6, Y10, Y12 VPERM2I128 $0x13, Y8, Y2, Y4 VPXOR 192(SI), Y0, Y0 VPXOR 224(SI), Y14, Y14 VPXOR 256(SI), Y12, Y12 VPXOR 288(SI), Y4, Y4 VMOVDQU Y0, 192(DI) VMOVDQU Y14, 224(DI) VMOVDQU Y12, 256(DI) VMOVDQU Y4, 288(DI) MOVQ $0x00000140, CX SUBQ $0x00000140, BX LEAQ 320(SI), SI VPERM2I128 $0x02, Y7, Y11, Y0 VPERM2I128 $0x02, Y15, Y3, Y14 VPERM2I128 $0x13, Y7, Y11, Y12 VPERM2I128 $0x13, Y15, Y3, Y4 CMPQ BX, $0x80 JBE sealAVX2SealHash VPXOR (SI), Y0, Y0 VPXOR 32(SI), Y14, Y14 VPXOR 64(SI), Y12, Y12 VPXOR 96(SI), Y4, Y4 VMOVDQU Y0, 320(DI) VMOVDQU Y14, 352(DI) VMOVDQU Y12, 384(DI) VMOVDQU Y4, 416(DI) SUBQ $0x80, BX LEAQ 128(SI), SI MOVQ $0x00000008, CX MOVQ $0x00000002, R9 CMPQ BX, $0x80 JBE sealAVX2Tail128 CMPQ BX, $0x00000100 JBE sealAVX2Tail256 CMPQ BX, $0x00000180 JBE sealAVX2Tail384 CMPQ BX, $0x00000200 JBE sealAVX2Tail512 // We have 448 bytes to hash, but main loop hashes 512 bytes at a time - perform some rounds, before the main loop VMOVDQA ·chacha20Constants<>+0(SB), Y0 VMOVDQA Y0, Y5 VMOVDQA Y0, Y6 VMOVDQA Y0, Y7 VMOVDQA 32(BP), Y14 VMOVDQA Y14, Y9 VMOVDQA Y14, Y10 VMOVDQA Y14, Y11 VMOVDQA 64(BP), Y12 VMOVDQA Y12, Y13 VMOVDQA Y12, Y8 VMOVDQA Y12, Y15 VMOVDQA 192(BP), Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 VMOVDQA Y4, 96(BP) VMOVDQA Y1, 128(BP) VMOVDQA Y2, 160(BP) VMOVDQA Y3, 192(BP) VMOVDQA Y15, 224(BP) VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y15 VPSRLD $0x14, Y14, Y14 VPXOR Y15, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y15 VPSRLD $0x19, Y14, Y14 VPXOR Y15, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y15 VPSRLD $0x14, Y9, Y9 VPXOR Y15, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y15 VPSRLD $0x19, Y9, Y9 VPXOR Y15, Y9, Y9 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x0c, Y10, Y15 VPSRLD $0x14, Y10, Y10 VPXOR Y15, Y10, Y10 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x07, Y10, Y15 VPSRLD $0x19, Y10, Y10 VPXOR Y15, Y10, Y10 VMOVDQA 224(BP), Y15 VMOVDQA Y13, 224(BP) VPADDD Y11, Y7, Y7 VPXOR Y7, Y3, Y3 VPSHUFB ·rol16<>+0(SB), Y3, Y3 VPADDD Y3, Y15, Y15 VPXOR Y15, Y11, Y11 VPSLLD $0x0c, Y11, Y13 VPSRLD $0x14, Y11, Y11 VPXOR Y13, Y11, Y11 VPADDD Y11, Y7, Y7 VPXOR Y7, Y3, Y3 VPSHUFB ·rol8<>+0(SB), Y3, Y3 VPADDD Y3, Y15, Y15 VPXOR Y15, Y11, Y11 VPSLLD $0x07, Y11, Y13 VPSRLD $0x19, Y11, Y11 VPXOR Y13, Y11, Y11 VMOVDQA 224(BP), Y13 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x0c, Y1, Y1, Y1 VPALIGNR $0x04, Y10, Y10, Y10 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x0c, Y2, Y2, Y2 VPALIGNR $0x04, Y11, Y11, Y11 VPALIGNR $0x08, Y15, Y15, Y15 VPALIGNR $0x0c, Y3, Y3, Y3 VMOVDQA Y15, 224(BP) VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y15 VPSRLD $0x14, Y14, Y14 VPXOR Y15, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y15 VPSRLD $0x19, Y14, Y14 VPXOR Y15, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y15 VPSRLD $0x14, Y9, Y9 VPXOR Y15, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y15 VPSRLD $0x19, Y9, Y9 VPXOR Y15, Y9, Y9 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x0c, Y10, Y15 VPSRLD $0x14, Y10, Y10 VPXOR Y15, Y10, Y10 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x07, Y10, Y15 VPSRLD $0x19, Y10, Y10 VPXOR Y15, Y10, Y10 VMOVDQA 224(BP), Y15 VMOVDQA Y13, 224(BP) VPADDD Y11, Y7, Y7 VPXOR Y7, Y3, Y3 VPSHUFB ·rol16<>+0(SB), Y3, Y3 VPADDD Y3, Y15, Y15 VPXOR Y15, Y11, Y11 VPSLLD $0x0c, Y11, Y13 VPSRLD $0x14, Y11, Y11 VPXOR Y13, Y11, Y11 VPADDD Y11, Y7, Y7 VPXOR Y7, Y3, Y3 VPSHUFB ·rol8<>+0(SB), Y3, Y3 VPADDD Y3, Y15, Y15 VPXOR Y15, Y11, Y11 VPSLLD $0x07, Y11, Y13 VPSRLD $0x19, Y11, Y11 VPXOR Y13, Y11, Y11 VMOVDQA 224(BP), Y13 VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x04, Y1, Y1, Y1 VPALIGNR $0x0c, Y10, Y10, Y10 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x04, Y2, Y2, Y2 VPALIGNR $0x0c, Y11, Y11, Y11 VPALIGNR $0x08, Y15, Y15, Y15 VPALIGNR $0x04, Y3, Y3, Y3 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y3, Y3 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 VMOVDQA Y15, 224(BP) VPSLLD $0x0c, Y14, Y15 VPSRLD $0x14, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x0c, Y9, Y15 VPSRLD $0x14, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x0c, Y10, Y15 VPSRLD $0x14, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x0c, Y11, Y15 VPSRLD $0x14, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 SUBQ $0x10, DI MOVQ $0x00000009, CX JMP sealAVX2InternalLoopStart sealAVX2MainLoop: VMOVDQU ·chacha20Constants<>+0(SB), Y0 VMOVDQA Y0, Y5 VMOVDQA Y0, Y6 VMOVDQA Y0, Y7 VMOVDQA 32(BP), Y14 VMOVDQA Y14, Y9 VMOVDQA Y14, Y10 VMOVDQA Y14, Y11 VMOVDQA 64(BP), Y12 VMOVDQA Y12, Y13 VMOVDQA Y12, Y8 VMOVDQA Y12, Y15 VMOVDQA 192(BP), Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 VMOVDQA Y4, 96(BP) VMOVDQA Y1, 128(BP) VMOVDQA Y2, 160(BP) VMOVDQA Y3, 192(BP) MOVQ $0x0000000a, CX sealAVX2InternalLoop: ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y3, Y3 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 VMOVDQA Y15, 224(BP) VPSLLD $0x0c, Y14, Y15 VPSRLD $0x14, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x0c, Y9, Y15 VPSRLD $0x14, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x0c, Y10, Y15 VPSRLD $0x14, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x0c, Y11, Y15 VPSRLD $0x14, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 sealAVX2InternalLoopStart: VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y3, Y3 ADDQ 16(DI), R10 ADCQ 24(DI), R11 ADCQ $0x01, R12 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 VMOVDQA Y15, 224(BP) VPSLLD $0x07, Y14, Y15 VPSRLD $0x19, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x07, Y9, Y15 VPSRLD $0x19, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x07, Y10, Y15 VPSRLD $0x19, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x07, Y11, Y15 VPSRLD $0x19, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x04, Y10, Y10, Y10 VPALIGNR $0x04, Y11, Y11, Y11 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x08, Y15, Y15, Y15 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x0c, Y1, Y1, Y1 VPALIGNR $0x0c, Y2, Y2, Y2 VPALIGNR $0x0c, Y3, Y3, Y3 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y3, Y3 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 ADDQ 32(DI), R10 ADCQ 40(DI), R11 ADCQ $0x01, R12 LEAQ 48(DI), DI VMOVDQA Y15, 224(BP) VPSLLD $0x0c, Y14, Y15 VPSRLD $0x14, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x0c, Y9, Y15 VPSRLD $0x14, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x0c, Y10, Y15 VPSRLD $0x14, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x0c, Y11, Y15 VPSRLD $0x14, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y3, Y3 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 VMOVDQA Y15, 224(BP) VPSLLD $0x07, Y14, Y15 VPSRLD $0x19, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x07, Y9, Y15 VPSRLD $0x19, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x07, Y10, Y15 VPSRLD $0x19, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x07, Y11, Y15 VPSRLD $0x19, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x0c, Y10, Y10, Y10 VPALIGNR $0x0c, Y11, Y11, Y11 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x08, Y15, Y15, Y15 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x04, Y1, Y1, Y1 VPALIGNR $0x04, Y2, Y2, Y2 VPALIGNR $0x04, Y3, Y3, Y3 DECQ CX JNE sealAVX2InternalLoop VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 VPADDD 32(BP), Y14, Y14 VPADDD 32(BP), Y9, Y9 VPADDD 32(BP), Y10, Y10 VPADDD 32(BP), Y11, Y11 VPADDD 64(BP), Y12, Y12 VPADDD 64(BP), Y13, Y13 VPADDD 64(BP), Y8, Y8 VPADDD 64(BP), Y15, Y15 VPADDD 96(BP), Y4, Y4 VPADDD 128(BP), Y1, Y1 VPADDD 160(BP), Y2, Y2 VPADDD 192(BP), Y3, Y3 VMOVDQA Y15, 224(BP) // We only hashed 480 of the 512 bytes available - hash the remaining 32 here ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 32(DI), DI VPERM2I128 $0x02, Y0, Y14, Y15 VPERM2I128 $0x13, Y0, Y14, Y14 VPERM2I128 $0x02, Y12, Y4, Y0 VPERM2I128 $0x13, Y12, Y4, Y12 VPXOR (SI), Y15, Y15 VPXOR 32(SI), Y0, Y0 VPXOR 64(SI), Y14, Y14 VPXOR 96(SI), Y12, Y12 VMOVDQU Y15, (DI) VMOVDQU Y0, 32(DI) VMOVDQU Y14, 64(DI) VMOVDQU Y12, 96(DI) VPERM2I128 $0x02, Y5, Y9, Y0 VPERM2I128 $0x02, Y13, Y1, Y14 VPERM2I128 $0x13, Y5, Y9, Y12 VPERM2I128 $0x13, Y13, Y1, Y4 VPXOR 128(SI), Y0, Y0 VPXOR 160(SI), Y14, Y14 VPXOR 192(SI), Y12, Y12 VPXOR 224(SI), Y4, Y4 VMOVDQU Y0, 128(DI) VMOVDQU Y14, 160(DI) VMOVDQU Y12, 192(DI) VMOVDQU Y4, 224(DI) // and here ADDQ -16(DI), R10 ADCQ -8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 VPERM2I128 $0x02, Y6, Y10, Y0 VPERM2I128 $0x02, Y8, Y2, Y14 VPERM2I128 $0x13, Y6, Y10, Y12 VPERM2I128 $0x13, Y8, Y2, Y4 VPXOR 256(SI), Y0, Y0 VPXOR 288(SI), Y14, Y14 VPXOR 320(SI), Y12, Y12 VPXOR 352(SI), Y4, Y4 VMOVDQU Y0, 256(DI) VMOVDQU Y14, 288(DI) VMOVDQU Y12, 320(DI) VMOVDQU Y4, 352(DI) VPERM2I128 $0x02, Y7, Y11, Y0 VPERM2I128 $0x02, 224(BP), Y3, Y14 VPERM2I128 $0x13, Y7, Y11, Y12 VPERM2I128 $0x13, 224(BP), Y3, Y4 VPXOR 384(SI), Y0, Y0 VPXOR 416(SI), Y14, Y14 VPXOR 448(SI), Y12, Y12 VPXOR 480(SI), Y4, Y4 VMOVDQU Y0, 384(DI) VMOVDQU Y14, 416(DI) VMOVDQU Y12, 448(DI) VMOVDQU Y4, 480(DI) LEAQ 512(SI), SI SUBQ $0x00000200, BX CMPQ BX, $0x00000200 JG sealAVX2MainLoop // Tail can only hash 480 bytes ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 ADDQ 16(DI), R10 ADCQ 24(DI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 32(DI), DI MOVQ $0x0000000a, CX MOVQ $0x00000000, R9 CMPQ BX, $0x80 JBE sealAVX2Tail128 CMPQ BX, $0x00000100 JBE sealAVX2Tail256 CMPQ BX, $0x00000180 JBE sealAVX2Tail384 JMP sealAVX2Tail512 seal192AVX2: VMOVDQA Y0, Y5 VMOVDQA Y14, Y9 VMOVDQA Y12, Y13 VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VMOVDQA Y0, Y6 VMOVDQA Y14, Y10 VMOVDQA Y12, Y8 VMOVDQA Y4, Y2 VMOVDQA Y1, Y15 MOVQ $0x0000000a, R9 sealAVX2192InnerCipherLoop: VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x0c, Y1, Y1, Y1 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x04, Y1, Y1, Y1 DECQ R9 JNE sealAVX2192InnerCipherLoop VPADDD Y6, Y0, Y0 VPADDD Y6, Y5, Y5 VPADDD Y10, Y14, Y14 VPADDD Y10, Y9, Y9 VPADDD Y8, Y12, Y12 VPADDD Y8, Y13, Y13 VPADDD Y2, Y4, Y4 VPADDD Y15, Y1, Y1 VPERM2I128 $0x02, Y0, Y14, Y3 // Clamp and store poly key VPAND ·polyClampMask<>+0(SB), Y3, Y3 VMOVDQA Y3, (BP) // Stream for up to 192 bytes VPERM2I128 $0x13, Y0, Y14, Y0 VPERM2I128 $0x13, Y12, Y4, Y14 VPERM2I128 $0x02, Y5, Y9, Y12 VPERM2I128 $0x02, Y13, Y1, Y4 VPERM2I128 $0x13, Y5, Y9, Y5 VPERM2I128 $0x13, Y13, Y1, Y9 sealAVX2ShortSeal: // Hash aad MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) XORQ CX, CX sealAVX2SealHash: // itr1 holds the number of bytes encrypted but not yet hashed CMPQ CX, $0x10 JB sealAVX2ShortSealLoop ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 SUBQ $0x10, CX ADDQ $0x10, DI JMP sealAVX2SealHash sealAVX2ShortSealLoop: CMPQ BX, $0x20 JB sealAVX2ShortTail32 SUBQ $0x20, BX // Load for encryption VPXOR (SI), Y0, Y0 VMOVDQU Y0, (DI) LEAQ 32(SI), SI // Now can hash ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 ADDQ 16(DI), R10 ADCQ 24(DI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 32(DI), DI // Shift stream left VMOVDQA Y14, Y0 VMOVDQA Y12, Y14 VMOVDQA Y4, Y12 VMOVDQA Y5, Y4 VMOVDQA Y9, Y5 VMOVDQA Y13, Y9 VMOVDQA Y1, Y13 VMOVDQA Y6, Y1 VMOVDQA Y10, Y6 JMP sealAVX2ShortSealLoop sealAVX2ShortTail32: CMPQ BX, $0x10 VMOVDQA X0, X1 JB sealAVX2ShortDone SUBQ $0x10, BX // Load for encryption VPXOR (SI), X0, X12 VMOVDQU X12, (DI) LEAQ 16(SI), SI // Hash ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(DI), DI VPERM2I128 $0x11, Y0, Y0, Y0 VMOVDQA X0, X1 sealAVX2ShortDone: VZEROUPPER JMP sealSSETail seal320AVX2: VMOVDQA Y0, Y5 VMOVDQA Y14, Y9 VMOVDQA Y12, Y13 VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VMOVDQA Y0, Y6 VMOVDQA Y14, Y10 VMOVDQA Y12, Y8 VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 VMOVDQA Y14, Y7 VMOVDQA Y12, Y11 VMOVDQA Y4, Y15 MOVQ $0x0000000a, R9 sealAVX2320InnerCipherLoop: VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x0c, Y10, Y3 VPSRLD $0x14, Y10, Y10 VPXOR Y3, Y10, Y10 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x07, Y10, Y3 VPSRLD $0x19, Y10, Y10 VPXOR Y3, Y10, Y10 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x04, Y10, Y10, Y10 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x0c, Y1, Y1, Y1 VPALIGNR $0x0c, Y2, Y2, Y2 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x0c, Y10, Y3 VPSRLD $0x14, Y10, Y10 VPXOR Y3, Y10, Y10 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x07, Y10, Y3 VPSRLD $0x19, Y10, Y10 VPXOR Y3, Y10, Y10 VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x0c, Y10, Y10, Y10 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x04, Y1, Y1, Y1 VPALIGNR $0x04, Y2, Y2, Y2 DECQ R9 JNE sealAVX2320InnerCipherLoop VMOVDQA ·chacha20Constants<>+0(SB), Y3 VPADDD Y3, Y0, Y0 VPADDD Y3, Y5, Y5 VPADDD Y3, Y6, Y6 VPADDD Y7, Y14, Y14 VPADDD Y7, Y9, Y9 VPADDD Y7, Y10, Y10 VPADDD Y11, Y12, Y12 VPADDD Y11, Y13, Y13 VPADDD Y11, Y8, Y8 VMOVDQA ·avx2IncMask<>+0(SB), Y3 VPADDD Y15, Y4, Y4 VPADDD Y3, Y15, Y15 VPADDD Y15, Y1, Y1 VPADDD Y3, Y15, Y15 VPADDD Y15, Y2, Y2 // Clamp and store poly key VPERM2I128 $0x02, Y0, Y14, Y3 VPAND ·polyClampMask<>+0(SB), Y3, Y3 VMOVDQA Y3, (BP) // Stream for up to 320 bytes VPERM2I128 $0x13, Y0, Y14, Y0 VPERM2I128 $0x13, Y12, Y4, Y14 VPERM2I128 $0x02, Y5, Y9, Y12 VPERM2I128 $0x02, Y13, Y1, Y4 VPERM2I128 $0x13, Y5, Y9, Y5 VPERM2I128 $0x13, Y13, Y1, Y9 VPERM2I128 $0x02, Y6, Y10, Y13 VPERM2I128 $0x02, Y8, Y2, Y1 VPERM2I128 $0x13, Y6, Y10, Y6 VPERM2I128 $0x13, Y8, Y2, Y10 JMP sealAVX2ShortSeal sealAVX2Tail128: VMOVDQA ·chacha20Constants<>+0(SB), Y0 VMOVDQA 32(BP), Y14 VMOVDQA 64(BP), Y12 VMOVDQA 192(BP), Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 VMOVDQA Y4, Y1 sealAVX2Tail128LoopA: ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(DI), DI sealAVX2Tail128LoopB: VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x0c, Y4, Y4, Y4 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 ADDQ 16(DI), R10 ADCQ 24(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 32(DI), DI VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x04, Y4, Y4, Y4 DECQ CX JG sealAVX2Tail128LoopA DECQ R9 JGE sealAVX2Tail128LoopB VPADDD ·chacha20Constants<>+0(SB), Y0, Y5 VPADDD 32(BP), Y14, Y9 VPADDD 64(BP), Y12, Y13 VPADDD Y1, Y4, Y1 VPERM2I128 $0x02, Y5, Y9, Y0 VPERM2I128 $0x02, Y13, Y1, Y14 VPERM2I128 $0x13, Y5, Y9, Y12 VPERM2I128 $0x13, Y13, Y1, Y4 JMP sealAVX2ShortSealLoop sealAVX2Tail256: VMOVDQA ·chacha20Constants<>+0(SB), Y0 VMOVDQA ·chacha20Constants<>+0(SB), Y5 VMOVDQA 32(BP), Y14 VMOVDQA 32(BP), Y9 VMOVDQA 64(BP), Y12 VMOVDQA 64(BP), Y13 VMOVDQA 192(BP), Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VMOVDQA Y4, Y7 VMOVDQA Y1, Y11 sealAVX2Tail256LoopA: ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(DI), DI sealAVX2Tail256LoopB: VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x0c, Y1, Y1, Y1 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 ADDQ 16(DI), R10 ADCQ 24(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 32(DI), DI VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x04, Y1, Y1, Y1 DECQ CX JG sealAVX2Tail256LoopA DECQ R9 JGE sealAVX2Tail256LoopB VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 VPADDD 32(BP), Y14, Y14 VPADDD 32(BP), Y9, Y9 VPADDD 64(BP), Y12, Y12 VPADDD 64(BP), Y13, Y13 VPADDD Y7, Y4, Y4 VPADDD Y11, Y1, Y1 VPERM2I128 $0x02, Y0, Y14, Y3 VPERM2I128 $0x02, Y12, Y4, Y7 VPERM2I128 $0x13, Y0, Y14, Y11 VPERM2I128 $0x13, Y12, Y4, Y15 VPXOR (SI), Y3, Y3 VPXOR 32(SI), Y7, Y7 VPXOR 64(SI), Y11, Y11 VPXOR 96(SI), Y15, Y15 VMOVDQU Y3, (DI) VMOVDQU Y7, 32(DI) VMOVDQU Y11, 64(DI) VMOVDQU Y15, 96(DI) MOVQ $0x00000080, CX LEAQ 128(SI), SI SUBQ $0x80, BX VPERM2I128 $0x02, Y5, Y9, Y0 VPERM2I128 $0x02, Y13, Y1, Y14 VPERM2I128 $0x13, Y5, Y9, Y12 VPERM2I128 $0x13, Y13, Y1, Y4 JMP sealAVX2SealHash sealAVX2Tail384: VMOVDQA ·chacha20Constants<>+0(SB), Y0 VMOVDQA Y0, Y5 VMOVDQA Y0, Y6 VMOVDQA 32(BP), Y14 VMOVDQA Y14, Y9 VMOVDQA Y14, Y10 VMOVDQA 64(BP), Y12 VMOVDQA Y12, Y13 VMOVDQA Y12, Y8 VMOVDQA 192(BP), Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 VMOVDQA Y4, Y7 VMOVDQA Y1, Y11 VMOVDQA Y2, Y15 sealAVX2Tail384LoopA: ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(DI), DI sealAVX2Tail384LoopB: VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x0c, Y10, Y3 VPSRLD $0x14, Y10, Y10 VPXOR Y3, Y10, Y10 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x07, Y10, Y3 VPSRLD $0x19, Y10, Y10 VPXOR Y3, Y10, Y10 ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x04, Y10, Y10, Y10 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x0c, Y1, Y1, Y1 VPALIGNR $0x0c, Y2, Y2, Y2 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x0c, Y14, Y3 VPSRLD $0x14, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y14, Y0, Y0 VPXOR Y0, Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPADDD Y4, Y12, Y12 VPXOR Y12, Y14, Y14 VPSLLD $0x07, Y14, Y3 VPSRLD $0x19, Y14, Y14 VPXOR Y3, Y14, Y14 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x0c, Y9, Y3 VPSRLD $0x14, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y9, Y5, Y5 VPXOR Y5, Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPADDD Y1, Y13, Y13 VPXOR Y13, Y9, Y9 VPSLLD $0x07, Y9, Y3 VPSRLD $0x19, Y9, Y9 VPXOR Y3, Y9, Y9 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x0c, Y10, Y3 VPSRLD $0x14, Y10, Y10 VPXOR Y3, Y10, Y10 VPADDD Y10, Y6, Y6 VPXOR Y6, Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPADDD Y2, Y8, Y8 VPXOR Y8, Y10, Y10 VPSLLD $0x07, Y10, Y3 VPSRLD $0x19, Y10, Y10 VPXOR Y3, Y10, Y10 ADDQ 16(DI), R10 ADCQ 24(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 32(DI), DI VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x0c, Y10, Y10, Y10 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x04, Y1, Y1, Y1 VPALIGNR $0x04, Y2, Y2, Y2 DECQ CX JG sealAVX2Tail384LoopA DECQ R9 JGE sealAVX2Tail384LoopB VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 VPADDD 32(BP), Y14, Y14 VPADDD 32(BP), Y9, Y9 VPADDD 32(BP), Y10, Y10 VPADDD 64(BP), Y12, Y12 VPADDD 64(BP), Y13, Y13 VPADDD 64(BP), Y8, Y8 VPADDD Y7, Y4, Y4 VPADDD Y11, Y1, Y1 VPADDD Y15, Y2, Y2 VPERM2I128 $0x02, Y0, Y14, Y3 VPERM2I128 $0x02, Y12, Y4, Y7 VPERM2I128 $0x13, Y0, Y14, Y11 VPERM2I128 $0x13, Y12, Y4, Y15 VPXOR (SI), Y3, Y3 VPXOR 32(SI), Y7, Y7 VPXOR 64(SI), Y11, Y11 VPXOR 96(SI), Y15, Y15 VMOVDQU Y3, (DI) VMOVDQU Y7, 32(DI) VMOVDQU Y11, 64(DI) VMOVDQU Y15, 96(DI) VPERM2I128 $0x02, Y5, Y9, Y3 VPERM2I128 $0x02, Y13, Y1, Y7 VPERM2I128 $0x13, Y5, Y9, Y11 VPERM2I128 $0x13, Y13, Y1, Y15 VPXOR 128(SI), Y3, Y3 VPXOR 160(SI), Y7, Y7 VPXOR 192(SI), Y11, Y11 VPXOR 224(SI), Y15, Y15 VMOVDQU Y3, 128(DI) VMOVDQU Y7, 160(DI) VMOVDQU Y11, 192(DI) VMOVDQU Y15, 224(DI) MOVQ $0x00000100, CX LEAQ 256(SI), SI SUBQ $0x00000100, BX VPERM2I128 $0x02, Y6, Y10, Y0 VPERM2I128 $0x02, Y8, Y2, Y14 VPERM2I128 $0x13, Y6, Y10, Y12 VPERM2I128 $0x13, Y8, Y2, Y4 JMP sealAVX2SealHash sealAVX2Tail512: VMOVDQA ·chacha20Constants<>+0(SB), Y0 VMOVDQA Y0, Y5 VMOVDQA Y0, Y6 VMOVDQA Y0, Y7 VMOVDQA 32(BP), Y14 VMOVDQA Y14, Y9 VMOVDQA Y14, Y10 VMOVDQA Y14, Y11 VMOVDQA 64(BP), Y12 VMOVDQA Y12, Y13 VMOVDQA Y12, Y8 VMOVDQA Y12, Y15 VMOVDQA 192(BP), Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 VMOVDQA Y4, 96(BP) VMOVDQA Y1, 128(BP) VMOVDQA Y2, 160(BP) VMOVDQA Y3, 192(BP) sealAVX2Tail512LoopA: ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), AX MOVQ AX, R15 MULQ R10 MOVQ AX, R13 MOVQ DX, R14 MOVQ (BP), AX MULQ R11 IMULQ R12, R15 ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), AX MOVQ AX, R8 MULQ R10 ADDQ AX, R14 ADCQ $0x00, DX MOVQ DX, R10 MOVQ 8(BP), AX MULQ R11 ADDQ AX, R15 ADCQ $0x00, DX IMULQ R12, R8 ADDQ R10, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 16(DI), DI sealAVX2Tail512LoopB: VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y3, Y3 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 VMOVDQA Y15, 224(BP) VPSLLD $0x0c, Y14, Y15 VPSRLD $0x14, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x0c, Y9, Y15 VPSRLD $0x14, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x0c, Y10, Y15 VPSRLD $0x14, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x0c, Y11, Y15 VPSRLD $0x14, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 ADDQ (DI), R10 ADCQ 8(DI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y3, Y3 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 VMOVDQA Y15, 224(BP) VPSLLD $0x07, Y14, Y15 VPSRLD $0x19, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x07, Y9, Y15 VPSRLD $0x19, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x07, Y10, Y15 VPSRLD $0x19, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x07, Y11, Y15 VPSRLD $0x19, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 VPALIGNR $0x04, Y14, Y14, Y14 VPALIGNR $0x04, Y9, Y9, Y9 VPALIGNR $0x04, Y10, Y10, Y10 VPALIGNR $0x04, Y11, Y11, Y11 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x08, Y15, Y15, Y15 VPALIGNR $0x0c, Y4, Y4, Y4 VPALIGNR $0x0c, Y1, Y1, Y1 VPALIGNR $0x0c, Y2, Y2, Y2 VPALIGNR $0x0c, Y3, Y3, Y3 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol16<>+0(SB), Y4, Y4 VPSHUFB ·rol16<>+0(SB), Y1, Y1 VPSHUFB ·rol16<>+0(SB), Y2, Y2 VPSHUFB ·rol16<>+0(SB), Y3, Y3 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 ADDQ 16(DI), R10 ADCQ 24(DI), R11 ADCQ $0x01, R12 MOVQ (BP), DX MOVQ DX, R15 MULXQ R10, R13, R14 IMULQ R12, R15 MULXQ R11, AX, DX ADDQ AX, R14 ADCQ DX, R15 MOVQ 8(BP), DX MULXQ R10, R10, AX ADDQ R10, R14 MULXQ R11, R11, R8 ADCQ R11, R15 ADCQ $0x00, R8 IMULQ R12, DX ADDQ AX, R15 ADCQ DX, R8 MOVQ R13, R10 MOVQ R14, R11 MOVQ R15, R12 ANDQ $0x03, R12 MOVQ R15, R13 ANDQ $-4, R13 MOVQ R8, R14 SHRQ $0x02, R8, R15 SHRQ $0x02, R8 ADDQ R13, R10 ADCQ R14, R11 ADCQ $0x00, R12 ADDQ R15, R10 ADCQ R8, R11 ADCQ $0x00, R12 LEAQ 32(DI), DI VMOVDQA Y15, 224(BP) VPSLLD $0x0c, Y14, Y15 VPSRLD $0x14, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x0c, Y9, Y15 VPSRLD $0x14, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x0c, Y10, Y15 VPSRLD $0x14, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x0c, Y11, Y15 VPSRLD $0x14, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 VPADDD Y14, Y0, Y0 VPADDD Y9, Y5, Y5 VPADDD Y10, Y6, Y6 VPADDD Y11, Y7, Y7 VPXOR Y0, Y4, Y4 VPXOR Y5, Y1, Y1 VPXOR Y6, Y2, Y2 VPXOR Y7, Y3, Y3 VPSHUFB ·rol8<>+0(SB), Y4, Y4 VPSHUFB ·rol8<>+0(SB), Y1, Y1 VPSHUFB ·rol8<>+0(SB), Y2, Y2 VPSHUFB ·rol8<>+0(SB), Y3, Y3 VPADDD Y4, Y12, Y12 VPADDD Y1, Y13, Y13 VPADDD Y2, Y8, Y8 VPADDD Y3, Y15, Y15 VPXOR Y12, Y14, Y14 VPXOR Y13, Y9, Y9 VPXOR Y8, Y10, Y10 VPXOR Y15, Y11, Y11 VMOVDQA Y15, 224(BP) VPSLLD $0x07, Y14, Y15 VPSRLD $0x19, Y14, Y14 VPXOR Y15, Y14, Y14 VPSLLD $0x07, Y9, Y15 VPSRLD $0x19, Y9, Y9 VPXOR Y15, Y9, Y9 VPSLLD $0x07, Y10, Y15 VPSRLD $0x19, Y10, Y10 VPXOR Y15, Y10, Y10 VPSLLD $0x07, Y11, Y15 VPSRLD $0x19, Y11, Y11 VPXOR Y15, Y11, Y11 VMOVDQA 224(BP), Y15 VPALIGNR $0x0c, Y14, Y14, Y14 VPALIGNR $0x0c, Y9, Y9, Y9 VPALIGNR $0x0c, Y10, Y10, Y10 VPALIGNR $0x0c, Y11, Y11, Y11 VPALIGNR $0x08, Y12, Y12, Y12 VPALIGNR $0x08, Y13, Y13, Y13 VPALIGNR $0x08, Y8, Y8, Y8 VPALIGNR $0x08, Y15, Y15, Y15 VPALIGNR $0x04, Y4, Y4, Y4 VPALIGNR $0x04, Y1, Y1, Y1 VPALIGNR $0x04, Y2, Y2, Y2 VPALIGNR $0x04, Y3, Y3, Y3 DECQ CX JG sealAVX2Tail512LoopA DECQ R9 JGE sealAVX2Tail512LoopB VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 VPADDD 32(BP), Y14, Y14 VPADDD 32(BP), Y9, Y9 VPADDD 32(BP), Y10, Y10 VPADDD 32(BP), Y11, Y11 VPADDD 64(BP), Y12, Y12 VPADDD 64(BP), Y13, Y13 VPADDD 64(BP), Y8, Y8 VPADDD 64(BP), Y15, Y15 VPADDD 96(BP), Y4, Y4 VPADDD 128(BP), Y1, Y1 VPADDD 160(BP), Y2, Y2 VPADDD 192(BP), Y3, Y3 VMOVDQA Y15, 224(BP) VPERM2I128 $0x02, Y0, Y14, Y15 VPXOR (SI), Y15, Y15 VMOVDQU Y15, (DI) VPERM2I128 $0x02, Y12, Y4, Y15 VPXOR 32(SI), Y15, Y15 VMOVDQU Y15, 32(DI) VPERM2I128 $0x13, Y0, Y14, Y15 VPXOR 64(SI), Y15, Y15 VMOVDQU Y15, 64(DI) VPERM2I128 $0x13, Y12, Y4, Y15 VPXOR 96(SI), Y15, Y15 VMOVDQU Y15, 96(DI) VPERM2I128 $0x02, Y5, Y9, Y0 VPERM2I128 $0x02, Y13, Y1, Y14 VPERM2I128 $0x13, Y5, Y9, Y12 VPERM2I128 $0x13, Y13, Y1, Y4 VPXOR 128(SI), Y0, Y0 VPXOR 160(SI), Y14, Y14 VPXOR 192(SI), Y12, Y12 VPXOR 224(SI), Y4, Y4 VMOVDQU Y0, 128(DI) VMOVDQU Y14, 160(DI) VMOVDQU Y12, 192(DI) VMOVDQU Y4, 224(DI) VPERM2I128 $0x02, Y6, Y10, Y0 VPERM2I128 $0x02, Y8, Y2, Y14 VPERM2I128 $0x13, Y6, Y10, Y12 VPERM2I128 $0x13, Y8, Y2, Y4 VPXOR 256(SI), Y0, Y0 VPXOR 288(SI), Y14, Y14 VPXOR 320(SI), Y12, Y12 VPXOR 352(SI), Y4, Y4 VMOVDQU Y0, 256(DI) VMOVDQU Y14, 288(DI) VMOVDQU Y12, 320(DI) VMOVDQU Y4, 352(DI) MOVQ $0x00000180, CX LEAQ 384(SI), SI SUBQ $0x00000180, BX VPERM2I128 $0x02, Y7, Y11, Y0 VPERM2I128 $0x02, 224(BP), Y3, Y14 VPERM2I128 $0x13, Y7, Y11, Y12 VPERM2I128 $0x13, 224(BP), Y3, Y4 JMP sealAVX2SealHash -- diff -- @@ -1,2715 +1,9762 @@ -// Copyright 2016 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. +// Code generated by command: go run chacha20poly1305_amd64_asm.go -out ../chacha20poly1305_amd64.s -pkg chacha20poly1305. DO NOT EDIT. -// This file was originally from https://golang.org/cl/24717 by Vlad Krasnov of CloudFlare. - //go:build gc && !purego #include "textflag.h" -// General register allocation -#define oup DI -#define inp SI -#define inl BX -#define adp CX // free to reuse, after we hash the additional data -#define keyp R8 // free to reuse, when we copy the key to stack -#define itr2 R9 // general iterator -#define itr1 CX // general iterator -#define acc0 R10 -#define acc1 R11 -#define acc2 R12 -#define t0 R13 -#define t1 R14 -#define t2 R15 -#define t3 R8 -// Register and stack allocation for the SSE code -#define rStore (0*16)(BP) -#define sStore (1*16)(BP) -#define state1Store (2*16)(BP) -#define state2Store (3*16)(BP) -#define tmpStore (4*16)(BP) -#define ctr0Store (5*16)(BP) -#define ctr1Store (6*16)(BP) -#define ctr2Store (7*16)(BP) -#define ctr3Store (8*16)(BP) -#define A0 X0 -#define A1 X1 -#define A2 X2 -#define B0 X3 -#define B1 X4 -#define B2 X5 -#define C0 X6 -#define C1 X7 -#define C2 X8 -#define D0 X9 -#define D1 X10 -#define D2 X11 -#define T0 X12 -#define T1 X13 -#define T2 X14 -#define T3 X15 -#define A3 T0 -#define B3 T1 -#define C3 T2 -#define D3 T3 -// Register and stack allocation for the AVX2 code -#define rsStoreAVX2 (0*32)(BP) -#define state1StoreAVX2 (1*32)(BP) -#define state2StoreAVX2 (2*32)(BP) -#define ctr0StoreAVX2 (3*32)(BP) -#define ctr1StoreAVX2 (4*32)(BP) -#define ctr2StoreAVX2 (5*32)(BP) -#define ctr3StoreAVX2 (6*32)(BP) -#define tmpStoreAVX2 (7*32)(BP) // 256 bytes on stack -#define AA0 Y0 -#define AA1 Y5 -#define AA2 Y6 -#define AA3 Y7 -#define BB0 Y14 -#define BB1 Y9 -#define BB2 Y10 -#define BB3 Y11 -#define CC0 Y12 -#define CC1 Y13 -#define CC2 Y8 -#define CC3 Y15 -#define DD0 Y4 -#define DD1 Y1 -#define DD2 Y2 -#define DD3 Y3 -#define TT0 DD3 -#define TT1 AA3 -#define TT2 BB3 -#define TT3 CC3 -// ChaCha20 constants -DATA ·chacha20Constants<>+0x00(SB)/4, $0x61707865 -DATA ·chacha20Constants<>+0x04(SB)/4, $0x3320646e -DATA ·chacha20Constants<>+0x08(SB)/4, $0x79622d32 -DATA ·chacha20Constants<>+0x0c(SB)/4, $0x6b206574 -DATA ·chacha20Constants<>+0x10(SB)/4, $0x61707865 -DATA ·chacha20Constants<>+0x14(SB)/4, $0x3320646e -DATA ·chacha20Constants<>+0x18(SB)/4, $0x79622d32 -DATA ·chacha20Constants<>+0x1c(SB)/4, $0x6b206574 -// <<< 16 with PSHUFB -DATA ·rol16<>+0x00(SB)/8, $0x0504070601000302 -DATA ·rol16<>+0x08(SB)/8, $0x0D0C0F0E09080B0A -DATA ·rol16<>+0x10(SB)/8, $0x0504070601000302 -DATA ·rol16<>+0x18(SB)/8, $0x0D0C0F0E09080B0A -// <<< 8 with PSHUFB -DATA ·rol8<>+0x00(SB)/8, $0x0605040702010003 -DATA ·rol8<>+0x08(SB)/8, $0x0E0D0C0F0A09080B -DATA ·rol8<>+0x10(SB)/8, $0x0605040702010003 -DATA ·rol8<>+0x18(SB)/8, $0x0E0D0C0F0A09080B -DATA ·avx2InitMask<>+0x00(SB)/8, $0x0 -DATA ·avx2InitMask<>+0x08(SB)/8, $0x0 -DATA ·avx2InitMask<>+0x10(SB)/8, $0x1 -DATA ·avx2InitMask<>+0x18(SB)/8, $0x0 - -DATA ·avx2IncMask<>+0x00(SB)/8, $0x2 -DATA ·avx2IncMask<>+0x08(SB)/8, $0x0 -DATA ·avx2IncMask<>+0x10(SB)/8, $0x2 -DATA ·avx2IncMask<>+0x18(SB)/8, $0x0 -// Poly1305 key clamp -DATA ·polyClampMask<>+0x00(SB)/8, $0x0FFFFFFC0FFFFFFF -DATA ·polyClampMask<>+0x08(SB)/8, $0x0FFFFFFC0FFFFFFC -DATA ·polyClampMask<>+0x10(SB)/8, $0xFFFFFFFFFFFFFFFF -DATA ·polyClampMask<>+0x18(SB)/8, $0xFFFFFFFFFFFFFFFF - -DATA ·sseIncMask<>+0x00(SB)/8, $0x1 -DATA ·sseIncMask<>+0x08(SB)/8, $0x0 -// To load/store the last < 16 bytes in a buffer -DATA ·andMask<>+0x00(SB)/8, $0x00000000000000ff -DATA ·andMask<>+0x08(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x10(SB)/8, $0x000000000000ffff -DATA ·andMask<>+0x18(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x20(SB)/8, $0x0000000000ffffff -DATA ·andMask<>+0x28(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x30(SB)/8, $0x00000000ffffffff -DATA ·andMask<>+0x38(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x40(SB)/8, $0x000000ffffffffff -DATA ·andMask<>+0x48(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x50(SB)/8, $0x0000ffffffffffff -DATA ·andMask<>+0x58(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x60(SB)/8, $0x00ffffffffffffff -DATA ·andMask<>+0x68(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x70(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0x78(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x80(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0x88(SB)/8, $0x00000000000000ff -DATA ·andMask<>+0x90(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0x98(SB)/8, $0x000000000000ffff -DATA ·andMask<>+0xa0(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0xa8(SB)/8, $0x0000000000ffffff -DATA ·andMask<>+0xb0(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0xb8(SB)/8, $0x00000000ffffffff -DATA ·andMask<>+0xc0(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0xc8(SB)/8, $0x000000ffffffffff -DATA ·andMask<>+0xd0(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0xd8(SB)/8, $0x0000ffffffffffff -DATA ·andMask<>+0xe0(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0xe8(SB)/8, $0x00ffffffffffffff - -GLOBL ·chacha20Constants<>(SB), (NOPTR+RODATA), $32 -GLOBL ·rol16<>(SB), (NOPTR+RODATA), $32 -GLOBL ·rol8<>(SB), (NOPTR+RODATA), $32 -GLOBL ·sseIncMask<>(SB), (NOPTR+RODATA), $16 -GLOBL ·avx2IncMask<>(SB), (NOPTR+RODATA), $32 -GLOBL ·avx2InitMask<>(SB), (NOPTR+RODATA), $32 -GLOBL ·polyClampMask<>(SB), (NOPTR+RODATA), $32 -GLOBL ·andMask<>(SB), (NOPTR+RODATA), $240 -// No PALIGNR in Go ASM yet (but VPALIGNR is present). -#define shiftB0Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xdb; BYTE $0x04 // PALIGNR $4, X3, X3 -#define shiftB1Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xe4; BYTE $0x04 // PALIGNR $4, X4, X4 -#define shiftB2Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xed; BYTE $0x04 // PALIGNR $4, X5, X5 -#define shiftB3Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xed; BYTE $0x04 // PALIGNR $4, X13, X13 -#define shiftC0Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xf6; BYTE $0x08 // PALIGNR $8, X6, X6 -#define shiftC1Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xff; BYTE $0x08 // PALIGNR $8, X7, X7 -#define shiftC2Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xc0; BYTE $0x08 // PALIGNR $8, X8, X8 -#define shiftC3Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xf6; BYTE $0x08 // PALIGNR $8, X14, X14 -#define shiftD0Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xc9; BYTE $0x0c // PALIGNR $12, X9, X9 -#define shiftD1Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xd2; BYTE $0x0c // PALIGNR $12, X10, X10 -#define shiftD2Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xdb; BYTE $0x0c // PALIGNR $12, X11, X11 -#define shiftD3Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xff; BYTE $0x0c // PALIGNR $12, X15, X15 -#define shiftB0Right BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xdb; BYTE $0x0c // PALIGNR $12, X3, X3 -#define shiftB1Right BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xe4; BYTE $0x0c // PALIGNR $12, X4, X4 -#define shiftB2Right BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xed; BYTE $0x0c // PALIGNR $12, X5, X5 -#define shiftB3Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xed; BYTE $0x0c // PALIGNR $12, X13, X13 -#define shiftC0Right shiftC0Left -#define shiftC1Right shiftC1Left -#define shiftC2Right shiftC2Left -#define shiftC3Right shiftC3Left -#define shiftD0Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xc9; BYTE $0x04 // PALIGNR $4, X9, X9 -#define shiftD1Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xd2; BYTE $0x04 // PALIGNR $4, X10, X10 -#define shiftD2Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xdb; BYTE $0x04 // PALIGNR $4, X11, X11 -#define shiftD3Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xff; BYTE $0x04 // PALIGNR $4, X15, X15 - -// Some macros - -// ROL rotates the uint32s in register R left by N bits, using temporary T. -#define ROL(N, R, T) \ - MOVO R, T; PSLLL $(N), T; PSRLL $(32-(N)), R; PXOR T, R - -// ROL16 rotates the uint32s in register R left by 16, using temporary T if needed. -#ifdef GOAMD64_v2 -#define ROL16(R, T) PSHUFB ·rol16<>(SB), R -#else -#define ROL16(R, T) ROL(16, R, T) -#endif - -// ROL8 rotates the uint32s in register R left by 8, using temporary T if needed. -#ifdef GOAMD64_v2 -#define ROL8(R, T) PSHUFB ·rol8<>(SB), R -#else -#define ROL8(R, T) ROL(8, R, T) -#endif - -#define chachaQR(A, B, C, D, T) \ - PADDD B, A; PXOR A, D; ROL16(D, T) \ - PADDD D, C; PXOR C, B; MOVO B, T; PSLLL $12, T; PSRLL $20, B; PXOR T, B \ - PADDD B, A; PXOR A, D; ROL8(D, T) \ - PADDD D, C; PXOR C, B; MOVO B, T; PSLLL $7, T; PSRLL $25, B; PXOR T, B +// func polyHashADInternal<>() +TEXT polyHashADInternal<>(SB), NOSPLIT, $0 + // Hack: Must declare #define macros inside of a function due to Avo constraints + // ROL rotates the uint32s in register R left by N bits, using temporary T. + #define ROL(N, R, T) \ + MOVO R, T; \ + PSLLL $(N), T; \ + PSRLL $(32-(N)), R; \ + PXOR T, R -#define chachaQR_AVX2(A, B, C, D, T) \ - VPADDD B, A, A; VPXOR A, D, D; VPSHUFB ·rol16<>(SB), D, D \ - VPADDD D, C, C; VPXOR C, B, B; VPSLLD $12, B, T; VPSRLD $20, B, B; VPXOR T, B, B \ - VPADDD B, A, A; VPXOR A, D, D; VPSHUFB ·rol8<>(SB), D, D \ - VPADDD D, C, C; VPXOR C, B, B; VPSLLD $7, B, T; VPSRLD $25, B, B; VPXOR T, B, B + // ROL8 rotates the uint32s in register R left by 8, using temporary T if needed. + #ifdef GOAMD64_v2 + #define ROL8(R, T) PSHUFB ·rol8<>(SB), R + #else + #define ROL8(R, T) ROL(8, R, T) + #endif -#define polyAdd(S) ADDQ S, acc0; ADCQ 8+S, acc1; ADCQ $1, acc2 -#define polyMulStage1 MOVQ (0*8)(BP), AX; MOVQ AX, t2; MULQ acc0; MOVQ AX, t0; MOVQ DX, t1; MOVQ (0*8)(BP), AX; MULQ acc1; IMULQ acc2, t2; ADDQ AX, t1; ADCQ DX, t2 -#define polyMulStage2 MOVQ (1*8)(BP), AX; MOVQ AX, t3; MULQ acc0; ADDQ AX, t1; ADCQ $0, DX; MOVQ DX, acc0; MOVQ (1*8)(BP), AX; MULQ acc1; ADDQ AX, t2; ADCQ $0, DX -#define polyMulStage3 IMULQ acc2, t3; ADDQ acc0, t2; ADCQ DX, t3 -#define polyMulReduceStage MOVQ t0, acc0; MOVQ t1, acc1; MOVQ t2, acc2; ANDQ $3, acc2; MOVQ t2, t0; ANDQ $-4, t0; MOVQ t3, t1; SHRQ $2, t3, t2; SHRQ $2, t3; ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $0, acc2; ADDQ t2, acc0; ADCQ t3, acc1; ADCQ $0, acc2 - -#define polyMulStage1_AVX2 MOVQ (0*8)(BP), DX; MOVQ DX, t2; MULXQ acc0, t0, t1; IMULQ acc2, t2; MULXQ acc1, AX, DX; ADDQ AX, t1; ADCQ DX, t2 -#define polyMulStage2_AVX2 MOVQ (1*8)(BP), DX; MULXQ acc0, acc0, AX; ADDQ acc0, t1; MULXQ acc1, acc1, t3; ADCQ acc1, t2; ADCQ $0, t3 -#define polyMulStage3_AVX2 IMULQ acc2, DX; ADDQ AX, t2; ADCQ DX, t3 - -#define polyMul polyMulStage1; polyMulStage2; polyMulStage3; polyMulReduceStage -#define polyMulAVX2 polyMulStage1_AVX2; polyMulStage2_AVX2; polyMulStage3_AVX2; polyMulReduceStage -// ---------------------------------------------------------------------------- -TEXT polyHashADInternal<>(SB), NOSPLIT, $0 - // adp points to beginning of additional data - // itr2 holds ad length - XORQ acc0, acc0 - XORQ acc1, acc1 - XORQ acc2, acc2 - CMPQ itr2, $13 - JNE hashADLoop - -openFastTLSAD: - // Special treatment for the TLS case of 13 bytes - MOVQ (adp), acc0 - MOVQ 5(adp), acc1 - SHRQ $24, acc1 - MOVQ $1, acc2 - polyMul + // ROL16 rotates the uint32s in register R left by 16, using temporary T if needed. + #ifdef GOAMD64_v2 + #define ROL16(R, T) PSHUFB ·rol16<>(SB), R + #else + #define ROL16(R, T) ROL(16, R, T) + #endif + XORQ R10, R10 + XORQ R11, R11 + XORQ R12, R12 + CMPQ R9, $0x0d + JNE hashADLoop + MOVQ (CX), R10 + MOVQ 5(CX), R11 + SHRQ $0x18, R11 + MOVQ $0x00000001, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 RET hashADLoop: // Hash in 16 byte chunks - CMPQ itr2, $16 - JB hashADTail - polyAdd(0(adp)) - LEAQ (1*16)(adp), adp - SUBQ $16, itr2 - polyMul - JMP hashADLoop + CMPQ R9, $0x10 + JB hashADTail + ADDQ (CX), R10 + ADCQ 8(CX), R11 + ADCQ $0x01, R12 + LEAQ 16(CX), CX + SUBQ $0x10, R9 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + JMP hashADLoop hashADTail: - CMPQ itr2, $0 + CMPQ R9, $0x00 JE hashADDone // Hash last < 16 byte tail - XORQ t0, t0 - XORQ t1, t1 - XORQ t2, t2 - ADDQ itr2, adp + XORQ R13, R13 + XORQ R14, R14 + XORQ R15, R15 + ADDQ R9, CX hashADTailLoop: - SHLQ $8, t0, t1 - SHLQ $8, t0 - MOVB -1(adp), t2 - XORQ t2, t0 - DECQ adp - DECQ itr2 - JNE hashADTailLoop + SHLQ $0x08, R13, R14 + SHLQ $0x08, R13 + MOVB -1(CX), R15 + XORQ R15, R13 + DECQ CX + DECQ R9 + JNE hashADTailLoop + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 -hashADTailFinish: - ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $1, acc2 - polyMul - - // Finished AD hashADDone: RET -// ---------------------------------------------------------------------------- -// func chacha20Poly1305Open(dst, key, src, ad []byte) bool -TEXT ·chacha20Poly1305Open(SB), 0, $288-97 +// func chacha20Poly1305Open(dst []byte, key []uint32, src []byte, ad []byte) bool +// Requires: AVX, AVX2, BMI2, CMOV, SSE2 +TEXT ·chacha20Poly1305Open(SB), $288-97 // For aligned stack access MOVQ SP, BP - ADDQ $32, BP + ADDQ $0x20, BP ANDQ $-32, BP - MOVQ dst+0(FP), oup - MOVQ key+24(FP), keyp - MOVQ src+48(FP), inp - MOVQ src_len+56(FP), inl - MOVQ ad+72(FP), adp + MOVQ dst_base+0(FP), DI + MOVQ key_base+24(FP), R8 + MOVQ src_base+48(FP), SI + MOVQ src_len+56(FP), BX + MOVQ ad_base+72(FP), CX // Check for AVX2 support - CMPB ·useAVX2(SB), $1 + CMPB ·useAVX2+0(SB), $0x01 JE chacha20Poly1305Open_AVX2 // Special optimization, for very short buffers - CMPQ inl, $128 - JBE openSSE128 // About 16% faster + CMPQ BX, $0x80 + JBE openSSE128 // For long buffers, prepare the poly key first - MOVOU ·chacha20Constants<>(SB), A0 - MOVOU (1*16)(keyp), B0 - MOVOU (2*16)(keyp), C0 - MOVOU (3*16)(keyp), D0 - MOVO D0, T1 + MOVOU ·chacha20Constants<>+0(SB), X0 + MOVOU 16(R8), X3 + MOVOU 32(R8), X6 + MOVOU 48(R8), X9 + MOVO X9, X13 // Store state on stack for future use - MOVO B0, state1Store - MOVO C0, state2Store - MOVO D0, ctr3Store - MOVQ $10, itr2 + MOVO X3, 32(BP) + MOVO X6, 48(BP) + MOVO X9, 128(BP) + MOVQ $0x0000000a, R9 openSSEPreparePolyKey: - chachaQR(A0, B0, C0, D0, T0) - shiftB0Left; shiftC0Left; shiftD0Left - chachaQR(A0, B0, C0, D0, T0) - shiftB0Right; shiftC0Right; shiftD0Right - DECQ itr2 - JNE openSSEPreparePolyKey + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + DECQ R9 + JNE openSSEPreparePolyKey // A0|B0 hold the Poly1305 32-byte key, C0,D0 can be discarded - PADDL ·chacha20Constants<>(SB), A0; PADDL state1Store, B0 + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL 32(BP), X3 // Clamp and store the key - PAND ·polyClampMask<>(SB), A0 - MOVO A0, rStore; MOVO B0, sStore + PAND ·polyClampMask<>+0(SB), X0 + MOVO X0, (BP) + MOVO X3, 16(BP) // Hash AAD - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) openSSEMainLoop: - CMPQ inl, $256 + CMPQ BX, $0x00000100 JB openSSEMainLoopDone // Load state, increment counter blocks - MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0 - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 - MOVO A2, A3; MOVO B2, B3; MOVO C2, C3; MOVO D2, D3; PADDL ·sseIncMask<>(SB), D3 + MOVO ·chacha20Constants<>+0(SB), X0 + MOVO 32(BP), X3 + MOVO 48(BP), X6 + MOVO 128(BP), X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X2, X12 + MOVO X5, X13 + MOVO X8, X14 + MOVO X11, X15 + PADDL ·sseIncMask<>+0(SB), X15 // Store counters - MOVO D0, ctr0Store; MOVO D1, ctr1Store; MOVO D2, ctr2Store; MOVO D3, ctr3Store + MOVO X9, 80(BP) + MOVO X10, 96(BP) + MOVO X11, 112(BP) + MOVO X15, 128(BP) - // There are 10 ChaCha20 iterations of 2QR each, so for 6 iterations we hash 2 blocks, and for the remaining 4 only 1 block - for a total of 16 - MOVQ $4, itr1 - MOVQ inp, itr2 + // There are 10 ChaCha20 iterations of 2QR each, so for 6 iterations we hash + // 2 blocks, and for the remaining 4 only 1 block - for a total of 16 + MOVQ $0x00000004, CX + MOVQ SI, R9 openSSEInternalLoop: - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - polyAdd(0(itr2)) - shiftB0Left; shiftB1Left; shiftB2Left; shiftB3Left - shiftC0Left; shiftC1Left; shiftC2Left; shiftC3Left - shiftD0Left; shiftD1Left; shiftD2Left; shiftD3Left - polyMulStage1 - polyMulStage2 - LEAQ (2*8)(itr2), itr2 - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - polyMulStage3 - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - polyMulReduceStage - shiftB0Right; shiftB1Right; shiftB2Right; shiftB3Right - shiftC0Right; shiftC1Right; shiftC2Right; shiftC3Right - shiftD0Right; shiftD1Right; shiftD2Right; shiftD3Right - DECQ itr1 - JGE openSSEInternalLoop - - polyAdd(0(itr2)) - polyMul - LEAQ (2*8)(itr2), itr2 - - CMPQ itr1, $-6 - JG openSSEInternalLoop + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x0c + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + LEAQ 16(R9), R9 + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x04 + DECQ CX + JGE openSSEInternalLoop + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(R9), R9 + CMPQ CX, $-6 + JG openSSEInternalLoop // Add in the state - PADDD ·chacha20Constants<>(SB), A0; PADDD ·chacha20Constants<>(SB), A1; PADDD ·chacha20Constants<>(SB), A2; PADDD ·chacha20Constants<>(SB), A3 - PADDD state1Store, B0; PADDD state1Store, B1; PADDD state1Store, B2; PADDD state1Store, B3 - PADDD state2Store, C0; PADDD state2Store, C1; PADDD state2Store, C2; PADDD state2Store, C3 - PADDD ctr0Store, D0; PADDD ctr1Store, D1; PADDD ctr2Store, D2; PADDD ctr3Store, D3 + PADDD ·chacha20Constants<>+0(SB), X0 + PADDD ·chacha20Constants<>+0(SB), X1 + PADDD ·chacha20Constants<>+0(SB), X2 + PADDD ·chacha20Constants<>+0(SB), X12 + PADDD 32(BP), X3 + PADDD 32(BP), X4 + PADDD 32(BP), X5 + PADDD 32(BP), X13 + PADDD 48(BP), X6 + PADDD 48(BP), X7 + PADDD 48(BP), X8 + PADDD 48(BP), X14 + PADDD 80(BP), X9 + PADDD 96(BP), X10 + PADDD 112(BP), X11 + PADDD 128(BP), X15 // Load - xor - store - MOVO D3, tmpStore - MOVOU (0*16)(inp), D3; PXOR D3, A0; MOVOU A0, (0*16)(oup) - MOVOU (1*16)(inp), D3; PXOR D3, B0; MOVOU B0, (1*16)(oup) - MOVOU (2*16)(inp), D3; PXOR D3, C0; MOVOU C0, (2*16)(oup) - MOVOU (3*16)(inp), D3; PXOR D3, D0; MOVOU D0, (3*16)(oup) - MOVOU (4*16)(inp), D0; PXOR D0, A1; MOVOU A1, (4*16)(oup) - MOVOU (5*16)(inp), D0; PXOR D0, B1; MOVOU B1, (5*16)(oup) - MOVOU (6*16)(inp), D0; PXOR D0, C1; MOVOU C1, (6*16)(oup) - MOVOU (7*16)(inp), D0; PXOR D0, D1; MOVOU D1, (7*16)(oup) - MOVOU (8*16)(inp), D0; PXOR D0, A2; MOVOU A2, (8*16)(oup) - MOVOU (9*16)(inp), D0; PXOR D0, B2; MOVOU B2, (9*16)(oup) - MOVOU (10*16)(inp), D0; PXOR D0, C2; MOVOU C2, (10*16)(oup) - MOVOU (11*16)(inp), D0; PXOR D0, D2; MOVOU D2, (11*16)(oup) - MOVOU (12*16)(inp), D0; PXOR D0, A3; MOVOU A3, (12*16)(oup) - MOVOU (13*16)(inp), D0; PXOR D0, B3; MOVOU B3, (13*16)(oup) - MOVOU (14*16)(inp), D0; PXOR D0, C3; MOVOU C3, (14*16)(oup) - MOVOU (15*16)(inp), D0; PXOR tmpStore, D0; MOVOU D0, (15*16)(oup) - LEAQ 256(inp), inp - LEAQ 256(oup), oup - SUBQ $256, inl + MOVO X15, 64(BP) + MOVOU (SI), X15 + PXOR X15, X0 + MOVOU X0, (DI) + MOVOU 16(SI), X15 + PXOR X15, X3 + MOVOU X3, 16(DI) + MOVOU 32(SI), X15 + PXOR X15, X6 + MOVOU X6, 32(DI) + MOVOU 48(SI), X15 + PXOR X15, X9 + MOVOU X9, 48(DI) + MOVOU 64(SI), X9 + PXOR X9, X1 + MOVOU X1, 64(DI) + MOVOU 80(SI), X9 + PXOR X9, X4 + MOVOU X4, 80(DI) + MOVOU 96(SI), X9 + PXOR X9, X7 + MOVOU X7, 96(DI) + MOVOU 112(SI), X9 + PXOR X9, X10 + MOVOU X10, 112(DI) + MOVOU 128(SI), X9 + PXOR X9, X2 + MOVOU X2, 128(DI) + MOVOU 144(SI), X9 + PXOR X9, X5 + MOVOU X5, 144(DI) + MOVOU 160(SI), X9 + PXOR X9, X8 + MOVOU X8, 160(DI) + MOVOU 176(SI), X9 + PXOR X9, X11 + MOVOU X11, 176(DI) + MOVOU 192(SI), X9 + PXOR X9, X12 + MOVOU X12, 192(DI) + MOVOU 208(SI), X9 + PXOR X9, X13 + MOVOU X13, 208(DI) + MOVOU 224(SI), X9 + PXOR X9, X14 + MOVOU X14, 224(DI) + MOVOU 240(SI), X9 + PXOR 64(BP), X9 + MOVOU X9, 240(DI) + LEAQ 256(SI), SI + LEAQ 256(DI), DI + SUBQ $0x00000100, BX JMP openSSEMainLoop openSSEMainLoopDone: // Handle the various tail sizes efficiently - TESTQ inl, inl + TESTQ BX, BX JE openSSEFinalize - CMPQ inl, $64 + CMPQ BX, $0x40 JBE openSSETail64 - CMPQ inl, $128 + CMPQ BX, $0x80 JBE openSSETail128 - CMPQ inl, $192 + CMPQ BX, $0xc0 JBE openSSETail192 JMP openSSETail256 openSSEFinalize: // Hash in the PT, AAD lengths - ADDQ ad_len+80(FP), acc0; ADCQ src_len+56(FP), acc1; ADCQ $1, acc2 - polyMul + ADDQ ad_len+80(FP), R10 + ADCQ src_len+56(FP), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 // Final reduce - MOVQ acc0, t0 - MOVQ acc1, t1 - MOVQ acc2, t2 - SUBQ $-5, acc0 - SBBQ $-1, acc1 - SBBQ $3, acc2 - CMOVQCS t0, acc0 - CMOVQCS t1, acc1 - CMOVQCS t2, acc2 + MOVQ R10, R13 + MOVQ R11, R14 + MOVQ R12, R15 + SUBQ $-5, R10 + SBBQ $-1, R11 + SBBQ $0x03, R12 + CMOVQCS R13, R10 + CMOVQCS R14, R11 + CMOVQCS R15, R12 // Add in the "s" part of the key - ADDQ 0+sStore, acc0 - ADCQ 8+sStore, acc1 + ADDQ 16(BP), R10 + ADCQ 24(BP), R11 // Finally, constant time compare to the tag at the end of the message XORQ AX, AX - MOVQ $1, DX - XORQ (0*8)(inp), acc0 - XORQ (1*8)(inp), acc1 - ORQ acc1, acc0 + MOVQ $0x00000001, DX + XORQ (SI), R10 + XORQ 8(SI), R11 + ORQ R11, R10 CMOVQEQ DX, AX // Return true iff tags are equal MOVB AX, ret+96(FP) RET -// ---------------------------------------------------------------------------- -// Special optimization for buffers smaller than 129 bytes openSSE128: - // For up to 128 bytes of ciphertext and 64 bytes for the poly key, we require to process three blocks - MOVOU ·chacha20Constants<>(SB), A0; MOVOU (1*16)(keyp), B0; MOVOU (2*16)(keyp), C0; MOVOU (3*16)(keyp), D0 - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 - MOVO B0, T1; MOVO C0, T2; MOVO D1, T3 - MOVQ $10, itr2 + MOVOU ·chacha20Constants<>+0(SB), X0 + MOVOU 16(R8), X3 + MOVOU 32(R8), X6 + MOVOU 48(R8), X9 + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X3, X13 + MOVO X6, X14 + MOVO X10, X15 + MOVQ $0x0000000a, R9 openSSE128InnerCipherLoop: - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Left; shiftB1Left; shiftB2Left - shiftC0Left; shiftC1Left; shiftC2Left - shiftD0Left; shiftD1Left; shiftD2Left - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Right; shiftB1Right; shiftB2Right - shiftC0Right; shiftC1Right; shiftC2Right - shiftD0Right; shiftD1Right; shiftD2Right - DECQ itr2 - JNE openSSE128InnerCipherLoop + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + DECQ R9 + JNE openSSE128InnerCipherLoop // A0|B0 hold the Poly1305 32-byte key, C0,D0 can be discarded - PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1; PADDL ·chacha20Constants<>(SB), A2 - PADDL T1, B0; PADDL T1, B1; PADDL T1, B2 - PADDL T2, C1; PADDL T2, C2 - PADDL T3, D1; PADDL ·sseIncMask<>(SB), T3; PADDL T3, D2 + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL ·chacha20Constants<>+0(SB), X2 + PADDL X13, X3 + PADDL X13, X4 + PADDL X13, X5 + PADDL X14, X7 + PADDL X14, X8 + PADDL X15, X10 + PADDL ·sseIncMask<>+0(SB), X15 + PADDL X15, X11 // Clamp and store the key - PAND ·polyClampMask<>(SB), A0 - MOVOU A0, rStore; MOVOU B0, sStore + PAND ·polyClampMask<>+0(SB), X0 + MOVOU X0, (BP) + MOVOU X3, 16(BP) // Hash - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) openSSE128Open: - CMPQ inl, $16 + CMPQ BX, $0x10 JB openSSETail16 - SUBQ $16, inl + SUBQ $0x10, BX // Load for hashing - polyAdd(0(inp)) + ADDQ (SI), R10 + ADCQ 8(SI), R11 + ADCQ $0x01, R12 // Load for decryption - MOVOU (inp), T0; PXOR T0, A1; MOVOU A1, (oup) - LEAQ (1*16)(inp), inp - LEAQ (1*16)(oup), oup - polyMul + MOVOU (SI), X12 + PXOR X12, X1 + MOVOU X1, (DI) + LEAQ 16(SI), SI + LEAQ 16(DI), DI + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 // Shift the stream "left" - MOVO B1, A1 - MOVO C1, B1 - MOVO D1, C1 - MOVO A2, D1 - MOVO B2, A2 - MOVO C2, B2 - MOVO D2, C2 + MOVO X4, X1 + MOVO X7, X4 + MOVO X10, X7 + MOVO X2, X10 + MOVO X5, X2 + MOVO X8, X5 + MOVO X11, X8 JMP openSSE128Open openSSETail16: - TESTQ inl, inl + TESTQ BX, BX JE openSSEFinalize // We can safely load the CT from the end, because it is padded with the MAC - MOVQ inl, itr2 - SHLQ $4, itr2 - LEAQ ·andMask<>(SB), t0 - MOVOU (inp), T0 - ADDQ inl, inp - PAND -16(t0)(itr2*1), T0 - MOVO T0, 0+tmpStore - MOVQ T0, t0 - MOVQ 8+tmpStore, t1 - PXOR A1, T0 + MOVQ BX, R9 + SHLQ $0x04, R9 + LEAQ ·andMask<>+0(SB), R13 + MOVOU (SI), X12 + ADDQ BX, SI + PAND -16(R13)(R9*1), X12 + MOVO X12, 64(BP) + MOVQ X12, R13 + MOVQ 72(BP), R14 + PXOR X1, X12 // We can only store one byte at a time, since plaintext can be shorter than 16 bytes openSSETail16Store: - MOVQ T0, t3 - MOVB t3, (oup) - PSRLDQ $1, T0 - INCQ oup - DECQ inl + MOVQ X12, R8 + MOVB R8, (DI) + PSRLDQ $0x01, X12 + INCQ DI + DECQ BX JNE openSSETail16Store - ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $1, acc2 - polyMul + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 JMP openSSEFinalize -// ---------------------------------------------------------------------------- -// Special optimization for the last 64 bytes of ciphertext openSSETail64: - // Need to decrypt up to 64 bytes - prepare single block - MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr0Store - XORQ itr2, itr2 - MOVQ inl, itr1 - CMPQ itr1, $16 - JB openSSETail64LoopB + MOVO ·chacha20Constants<>+0(SB), X0 + MOVO 32(BP), X3 + MOVO 48(BP), X6 + MOVO 128(BP), X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X9, 80(BP) + XORQ R9, R9 + MOVQ BX, CX + CMPQ CX, $0x10 + JB openSSETail64LoopB openSSETail64LoopA: - // Perform ChaCha rounds, while hashing the remaining input - polyAdd(0(inp)(itr2*1)) - polyMul - SUBQ $16, itr1 + ADDQ (SI)(R9*1), R10 + ADCQ 8(SI)(R9*1), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + SUBQ $0x10, CX openSSETail64LoopB: - ADDQ $16, itr2 - chachaQR(A0, B0, C0, D0, T0) - shiftB0Left; shiftC0Left; shiftD0Left - chachaQR(A0, B0, C0, D0, T0) - shiftB0Right; shiftC0Right; shiftD0Right + ADDQ $0x10, R9 + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + CMPQ CX, $0x10 + JAE openSSETail64LoopA + CMPQ R9, $0xa0 + JNE openSSETail64LoopB + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL 32(BP), X3 + PADDL 48(BP), X6 + PADDL 80(BP), X9 - CMPQ itr1, $16 - JAE openSSETail64LoopA - - CMPQ itr2, $160 - JNE openSSETail64LoopB - - PADDL ·chacha20Constants<>(SB), A0; PADDL state1Store, B0; PADDL state2Store, C0; PADDL ctr0Store, D0 - openSSETail64DecLoop: - CMPQ inl, $16 + CMPQ BX, $0x10 JB openSSETail64DecLoopDone - SUBQ $16, inl - MOVOU (inp), T0 - PXOR T0, A0 - MOVOU A0, (oup) - LEAQ 16(inp), inp - LEAQ 16(oup), oup - MOVO B0, A0 - MOVO C0, B0 - MOVO D0, C0 + SUBQ $0x10, BX + MOVOU (SI), X12 + PXOR X12, X0 + MOVOU X0, (DI) + LEAQ 16(SI), SI + LEAQ 16(DI), DI + MOVO X3, X0 + MOVO X6, X3 + MOVO X9, X6 JMP openSSETail64DecLoop openSSETail64DecLoopDone: - MOVO A0, A1 + MOVO X0, X1 JMP openSSETail16 -// ---------------------------------------------------------------------------- -// Special optimization for the last 128 bytes of ciphertext openSSETail128: - // Need to decrypt up to 128 bytes - prepare two blocks - MOVO ·chacha20Constants<>(SB), A1; MOVO state1Store, B1; MOVO state2Store, C1; MOVO ctr3Store, D1; PADDL ·sseIncMask<>(SB), D1; MOVO D1, ctr0Store - MOVO A1, A0; MOVO B1, B0; MOVO C1, C0; MOVO D1, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr1Store - XORQ itr2, itr2 - MOVQ inl, itr1 - ANDQ $-16, itr1 + MOVO ·chacha20Constants<>+0(SB), X1 + MOVO 32(BP), X4 + MOVO 48(BP), X7 + MOVO 128(BP), X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X10, 80(BP) + MOVO X1, X0 + MOVO X4, X3 + MOVO X7, X6 + MOVO X10, X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X9, 96(BP) + XORQ R9, R9 + MOVQ BX, CX + ANDQ $-16, CX openSSETail128LoopA: - // Perform ChaCha rounds, while hashing the remaining input - polyAdd(0(inp)(itr2*1)) - polyMul + ADDQ (SI)(R9*1), R10 + ADCQ 8(SI)(R9*1), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 openSSETail128LoopB: - ADDQ $16, itr2 - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0) - shiftB0Left; shiftC0Left; shiftD0Left - shiftB1Left; shiftC1Left; shiftD1Left - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0) - shiftB0Right; shiftC0Right; shiftD0Right - shiftB1Right; shiftC1Right; shiftD1Right + ADDQ $0x10, R9 + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + CMPQ R9, CX + JB openSSETail128LoopA + CMPQ R9, $0xa0 + JNE openSSETail128LoopB + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL 32(BP), X3 + PADDL 32(BP), X4 + PADDL 48(BP), X6 + PADDL 48(BP), X7 + PADDL 96(BP), X9 + PADDL 80(BP), X10 + MOVOU (SI), X12 + MOVOU 16(SI), X13 + MOVOU 32(SI), X14 + MOVOU 48(SI), X15 + PXOR X12, X1 + PXOR X13, X4 + PXOR X14, X7 + PXOR X15, X10 + MOVOU X1, (DI) + MOVOU X4, 16(DI) + MOVOU X7, 32(DI) + MOVOU X10, 48(DI) + SUBQ $0x40, BX + LEAQ 64(SI), SI + LEAQ 64(DI), DI + JMP openSSETail64DecLoop - CMPQ itr2, itr1 - JB openSSETail128LoopA - - CMPQ itr2, $160 - JNE openSSETail128LoopB - - PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1 - PADDL state1Store, B0; PADDL state1Store, B1 - PADDL state2Store, C0; PADDL state2Store, C1 - PADDL ctr1Store, D0; PADDL ctr0Store, D1 - - MOVOU (0*16)(inp), T0; MOVOU (1*16)(inp), T1; MOVOU (2*16)(inp), T2; MOVOU (3*16)(inp), T3 - PXOR T0, A1; PXOR T1, B1; PXOR T2, C1; PXOR T3, D1 - MOVOU A1, (0*16)(oup); MOVOU B1, (1*16)(oup); MOVOU C1, (2*16)(oup); MOVOU D1, (3*16)(oup) - - SUBQ $64, inl - LEAQ 64(inp), inp - LEAQ 64(oup), oup - JMP openSSETail64DecLoop - -// ---------------------------------------------------------------------------- -// Special optimization for the last 192 bytes of ciphertext openSSETail192: - // Need to decrypt up to 192 bytes - prepare three blocks - MOVO ·chacha20Constants<>(SB), A2; MOVO state1Store, B2; MOVO state2Store, C2; MOVO ctr3Store, D2; PADDL ·sseIncMask<>(SB), D2; MOVO D2, ctr0Store - MOVO A2, A1; MOVO B2, B1; MOVO C2, C1; MOVO D2, D1; PADDL ·sseIncMask<>(SB), D1; MOVO D1, ctr1Store - MOVO A1, A0; MOVO B1, B0; MOVO C1, C0; MOVO D1, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr2Store + MOVO ·chacha20Constants<>+0(SB), X2 + MOVO 32(BP), X5 + MOVO 48(BP), X8 + MOVO 128(BP), X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X11, 80(BP) + MOVO X2, X1 + MOVO X5, X4 + MOVO X8, X7 + MOVO X11, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X10, 96(BP) + MOVO X1, X0 + MOVO X4, X3 + MOVO X7, X6 + MOVO X10, X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X9, 112(BP) + MOVQ BX, CX + MOVQ $0x000000a0, R9 + CMPQ CX, $0xa0 + CMOVQGT R9, CX + ANDQ $-16, CX + XORQ R9, R9 - MOVQ inl, itr1 - MOVQ $160, itr2 - CMPQ itr1, $160 - CMOVQGT itr2, itr1 - ANDQ $-16, itr1 - XORQ itr2, itr2 - openSSLTail192LoopA: - // Perform ChaCha rounds, while hashing the remaining input - polyAdd(0(inp)(itr2*1)) - polyMul + ADDQ (SI)(R9*1), R10 + ADCQ 8(SI)(R9*1), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 openSSLTail192LoopB: - ADDQ $16, itr2 - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Left; shiftC0Left; shiftD0Left - shiftB1Left; shiftC1Left; shiftD1Left - shiftB2Left; shiftC2Left; shiftD2Left - - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Right; shiftC0Right; shiftD0Right - shiftB1Right; shiftC1Right; shiftD1Right - shiftB2Right; shiftC2Right; shiftD2Right - - CMPQ itr2, itr1 - JB openSSLTail192LoopA - - CMPQ itr2, $160 - JNE openSSLTail192LoopB - - CMPQ inl, $176 - JB openSSLTail192Store - - polyAdd(160(inp)) - polyMul - - CMPQ inl, $192 - JB openSSLTail192Store + ADDQ $0x10, R9 + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + CMPQ R9, CX + JB openSSLTail192LoopA + CMPQ R9, $0xa0 + JNE openSSLTail192LoopB + CMPQ BX, $0xb0 + JB openSSLTail192Store + ADDQ 160(SI), R10 + ADCQ 168(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + CMPQ BX, $0xc0 + JB openSSLTail192Store + ADDQ 176(SI), R10 + ADCQ 184(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 - polyAdd(176(inp)) - polyMul - openSSLTail192Store: - PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1; PADDL ·chacha20Constants<>(SB), A2 - PADDL state1Store, B0; PADDL state1Store, B1; PADDL state1Store, B2 - PADDL state2Store, C0; PADDL state2Store, C1; PADDL state2Store, C2 - PADDL ctr2Store, D0; PADDL ctr1Store, D1; PADDL ctr0Store, D2 + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL ·chacha20Constants<>+0(SB), X2 + PADDL 32(BP), X3 + PADDL 32(BP), X4 + PADDL 32(BP), X5 + PADDL 48(BP), X6 + PADDL 48(BP), X7 + PADDL 48(BP), X8 + PADDL 112(BP), X9 + PADDL 96(BP), X10 + PADDL 80(BP), X11 + MOVOU (SI), X12 + MOVOU 16(SI), X13 + MOVOU 32(SI), X14 + MOVOU 48(SI), X15 + PXOR X12, X2 + PXOR X13, X5 + PXOR X14, X8 + PXOR X15, X11 + MOVOU X2, (DI) + MOVOU X5, 16(DI) + MOVOU X8, 32(DI) + MOVOU X11, 48(DI) + MOVOU 64(SI), X12 + MOVOU 80(SI), X13 + MOVOU 96(SI), X14 + MOVOU 112(SI), X15 + PXOR X12, X1 + PXOR X13, X4 + PXOR X14, X7 + PXOR X15, X10 + MOVOU X1, 64(DI) + MOVOU X4, 80(DI) + MOVOU X7, 96(DI) + MOVOU X10, 112(DI) + SUBQ $0x80, BX + LEAQ 128(SI), SI + LEAQ 128(DI), DI + JMP openSSETail64DecLoop - MOVOU (0*16)(inp), T0; MOVOU (1*16)(inp), T1; MOVOU (2*16)(inp), T2; MOVOU (3*16)(inp), T3 - PXOR T0, A2; PXOR T1, B2; PXOR T2, C2; PXOR T3, D2 - MOVOU A2, (0*16)(oup); MOVOU B2, (1*16)(oup); MOVOU C2, (2*16)(oup); MOVOU D2, (3*16)(oup) - - MOVOU (4*16)(inp), T0; MOVOU (5*16)(inp), T1; MOVOU (6*16)(inp), T2; MOVOU (7*16)(inp), T3 - PXOR T0, A1; PXOR T1, B1; PXOR T2, C1; PXOR T3, D1 - MOVOU A1, (4*16)(oup); MOVOU B1, (5*16)(oup); MOVOU C1, (6*16)(oup); MOVOU D1, (7*16)(oup) - - SUBQ $128, inl - LEAQ 128(inp), inp - LEAQ 128(oup), oup - JMP openSSETail64DecLoop - -// ---------------------------------------------------------------------------- -// Special optimization for the last 256 bytes of ciphertext openSSETail256: - // Need to decrypt up to 256 bytes - prepare four blocks - MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0 - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 - MOVO A2, A3; MOVO B2, B3; MOVO C2, C3; MOVO D2, D3; PADDL ·sseIncMask<>(SB), D3 + MOVO ·chacha20Constants<>+0(SB), X0 + MOVO 32(BP), X3 + MOVO 48(BP), X6 + MOVO 128(BP), X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X2, X12 + MOVO X5, X13 + MOVO X8, X14 + MOVO X11, X15 + PADDL ·sseIncMask<>+0(SB), X15 // Store counters - MOVO D0, ctr0Store; MOVO D1, ctr1Store; MOVO D2, ctr2Store; MOVO D3, ctr3Store - XORQ itr2, itr2 + MOVO X9, 80(BP) + MOVO X10, 96(BP) + MOVO X11, 112(BP) + MOVO X15, 128(BP) + XORQ R9, R9 openSSETail256Loop: - // This loop inteleaves 8 ChaCha quarter rounds with 1 poly multiplication - polyAdd(0(inp)(itr2*1)) - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - shiftB0Left; shiftB1Left; shiftB2Left; shiftB3Left - shiftC0Left; shiftC1Left; shiftC2Left; shiftC3Left - shiftD0Left; shiftD1Left; shiftD2Left; shiftD3Left - polyMulStage1 - polyMulStage2 - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - polyMulStage3 - polyMulReduceStage - shiftB0Right; shiftB1Right; shiftB2Right; shiftB3Right - shiftC0Right; shiftC1Right; shiftC2Right; shiftC3Right - shiftD0Right; shiftD1Right; shiftD2Right; shiftD3Right - ADDQ $2*8, itr2 - CMPQ itr2, $160 - JB openSSETail256Loop - MOVQ inl, itr1 - ANDQ $-16, itr1 + ADDQ (SI)(R9*1), R10 + ADCQ 8(SI)(R9*1), R11 + ADCQ $0x01, R12 + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x0c + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x04 + ADDQ $0x10, R9 + CMPQ R9, $0xa0 + JB openSSETail256Loop + MOVQ BX, CX + ANDQ $-16, CX openSSETail256HashLoop: - polyAdd(0(inp)(itr2*1)) - polyMul - ADDQ $2*8, itr2 - CMPQ itr2, itr1 - JB openSSETail256HashLoop + ADDQ (SI)(R9*1), R10 + ADCQ 8(SI)(R9*1), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + ADDQ $0x10, R9 + CMPQ R9, CX + JB openSSETail256HashLoop // Add in the state - PADDD ·chacha20Constants<>(SB), A0; PADDD ·chacha20Constants<>(SB), A1; PADDD ·chacha20Constants<>(SB), A2; PADDD ·chacha20Constants<>(SB), A3 - PADDD state1Store, B0; PADDD state1Store, B1; PADDD state1Store, B2; PADDD state1Store, B3 - PADDD state2Store, C0; PADDD state2Store, C1; PADDD state2Store, C2; PADDD state2Store, C3 - PADDD ctr0Store, D0; PADDD ctr1Store, D1; PADDD ctr2Store, D2; PADDD ctr3Store, D3 - MOVO D3, tmpStore + PADDD ·chacha20Constants<>+0(SB), X0 + PADDD ·chacha20Constants<>+0(SB), X1 + PADDD ·chacha20Constants<>+0(SB), X2 + PADDD ·chacha20Constants<>+0(SB), X12 + PADDD 32(BP), X3 + PADDD 32(BP), X4 + PADDD 32(BP), X5 + PADDD 32(BP), X13 + PADDD 48(BP), X6 + PADDD 48(BP), X7 + PADDD 48(BP), X8 + PADDD 48(BP), X14 + PADDD 80(BP), X9 + PADDD 96(BP), X10 + PADDD 112(BP), X11 + PADDD 128(BP), X15 + MOVO X15, 64(BP) // Load - xor - store - MOVOU (0*16)(inp), D3; PXOR D3, A0 - MOVOU (1*16)(inp), D3; PXOR D3, B0 - MOVOU (2*16)(inp), D3; PXOR D3, C0 - MOVOU (3*16)(inp), D3; PXOR D3, D0 - MOVOU A0, (0*16)(oup) - MOVOU B0, (1*16)(oup) - MOVOU C0, (2*16)(oup) - MOVOU D0, (3*16)(oup) - MOVOU (4*16)(inp), A0; MOVOU (5*16)(inp), B0; MOVOU (6*16)(inp), C0; MOVOU (7*16)(inp), D0 - PXOR A0, A1; PXOR B0, B1; PXOR C0, C1; PXOR D0, D1 - MOVOU A1, (4*16)(oup); MOVOU B1, (5*16)(oup); MOVOU C1, (6*16)(oup); MOVOU D1, (7*16)(oup) - MOVOU (8*16)(inp), A0; MOVOU (9*16)(inp), B0; MOVOU (10*16)(inp), C0; MOVOU (11*16)(inp), D0 - PXOR A0, A2; PXOR B0, B2; PXOR C0, C2; PXOR D0, D2 - MOVOU A2, (8*16)(oup); MOVOU B2, (9*16)(oup); MOVOU C2, (10*16)(oup); MOVOU D2, (11*16)(oup) - LEAQ 192(inp), inp - LEAQ 192(oup), oup - SUBQ $192, inl - MOVO A3, A0 - MOVO B3, B0 - MOVO C3, C0 - MOVO tmpStore, D0 + MOVOU (SI), X15 + PXOR X15, X0 + MOVOU 16(SI), X15 + PXOR X15, X3 + MOVOU 32(SI), X15 + PXOR X15, X6 + MOVOU 48(SI), X15 + PXOR X15, X9 + MOVOU X0, (DI) + MOVOU X3, 16(DI) + MOVOU X6, 32(DI) + MOVOU X9, 48(DI) + MOVOU 64(SI), X0 + MOVOU 80(SI), X3 + MOVOU 96(SI), X6 + MOVOU 112(SI), X9 + PXOR X0, X1 + PXOR X3, X4 + PXOR X6, X7 + PXOR X9, X10 + MOVOU X1, 64(DI) + MOVOU X4, 80(DI) + MOVOU X7, 96(DI) + MOVOU X10, 112(DI) + MOVOU 128(SI), X0 + MOVOU 144(SI), X3 + MOVOU 160(SI), X6 + MOVOU 176(SI), X9 + PXOR X0, X2 + PXOR X3, X5 + PXOR X6, X8 + PXOR X9, X11 + MOVOU X2, 128(DI) + MOVOU X5, 144(DI) + MOVOU X8, 160(DI) + MOVOU X11, 176(DI) + LEAQ 192(SI), SI + LEAQ 192(DI), DI + SUBQ $0xc0, BX + MOVO X12, X0 + MOVO X13, X3 + MOVO X14, X6 + MOVO 64(BP), X9 + JMP openSSETail64DecLoop - JMP openSSETail64DecLoop - -// ---------------------------------------------------------------------------- -// ------------------------- AVX2 Code ---------------------------------------- chacha20Poly1305Open_AVX2: VZEROUPPER - VMOVDQU ·chacha20Constants<>(SB), AA0 - BYTE $0xc4; BYTE $0x42; BYTE $0x7d; BYTE $0x5a; BYTE $0x70; BYTE $0x10 // broadcasti128 16(r8), ymm14 - BYTE $0xc4; BYTE $0x42; BYTE $0x7d; BYTE $0x5a; BYTE $0x60; BYTE $0x20 // broadcasti128 32(r8), ymm12 - BYTE $0xc4; BYTE $0xc2; BYTE $0x7d; BYTE $0x5a; BYTE $0x60; BYTE $0x30 // broadcasti128 48(r8), ymm4 - VPADDD ·avx2InitMask<>(SB), DD0, DD0 + VMOVDQU ·chacha20Constants<>+0(SB), Y0 + BYTE $0xc4 + BYTE $0x42 + BYTE $0x7d + BYTE $0x5a + BYTE $0x70 + BYTE $0x10 + BYTE $0xc4 + BYTE $0x42 + BYTE $0x7d + BYTE $0x5a + BYTE $0x60 + BYTE $0x20 + BYTE $0xc4 + BYTE $0xc2 + BYTE $0x7d + BYTE $0x5a + BYTE $0x60 + BYTE $0x30 + VPADDD ·avx2InitMask<>+0(SB), Y4, Y4 // Special optimization, for very short buffers - CMPQ inl, $192 + CMPQ BX, $0xc0 JBE openAVX2192 - CMPQ inl, $320 + CMPQ BX, $0x00000140 JBE openAVX2320 // For the general key prepare the key first - as a byproduct we have 64 bytes of cipher stream - VMOVDQA BB0, state1StoreAVX2 - VMOVDQA CC0, state2StoreAVX2 - VMOVDQA DD0, ctr3StoreAVX2 - MOVQ $10, itr2 + VMOVDQA Y14, 32(BP) + VMOVDQA Y12, 64(BP) + VMOVDQA Y4, 192(BP) + MOVQ $0x0000000a, R9 openAVX2PreparePolyKey: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $12, DD0, DD0, DD0 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $4, DD0, DD0, DD0 - DECQ itr2 - JNE openAVX2PreparePolyKey - - VPADDD ·chacha20Constants<>(SB), AA0, AA0 - VPADDD state1StoreAVX2, BB0, BB0 - VPADDD state2StoreAVX2, CC0, CC0 - VPADDD ctr3StoreAVX2, DD0, DD0 - - VPERM2I128 $0x02, AA0, BB0, TT0 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x04, Y4, Y4, Y4 + DECQ R9 + JNE openAVX2PreparePolyKey + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD 32(BP), Y14, Y14 + VPADDD 64(BP), Y12, Y12 + VPADDD 192(BP), Y4, Y4 + VPERM2I128 $0x02, Y0, Y14, Y3 // Clamp and store poly key - VPAND ·polyClampMask<>(SB), TT0, TT0 - VMOVDQA TT0, rsStoreAVX2 + VPAND ·polyClampMask<>+0(SB), Y3, Y3 + VMOVDQA Y3, (BP) // Stream for the first 64 bytes - VPERM2I128 $0x13, AA0, BB0, AA0 - VPERM2I128 $0x13, CC0, DD0, BB0 + VPERM2I128 $0x13, Y0, Y14, Y0 + VPERM2I128 $0x13, Y12, Y4, Y14 // Hash AD + first 64 bytes - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) - XORQ itr1, itr1 + XORQ CX, CX openAVX2InitialHash64: - polyAdd(0(inp)(itr1*1)) - polyMulAVX2 - ADDQ $16, itr1 - CMPQ itr1, $64 - JNE openAVX2InitialHash64 + ADDQ (SI)(CX*1), R10 + ADCQ 8(SI)(CX*1), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + ADDQ $0x10, CX + CMPQ CX, $0x40 + JNE openAVX2InitialHash64 // Decrypt the first 64 bytes - VPXOR (0*32)(inp), AA0, AA0 - VPXOR (1*32)(inp), BB0, BB0 - VMOVDQU AA0, (0*32)(oup) - VMOVDQU BB0, (1*32)(oup) - LEAQ (2*32)(inp), inp - LEAQ (2*32)(oup), oup - SUBQ $64, inl + VPXOR (SI), Y0, Y0 + VPXOR 32(SI), Y14, Y14 + VMOVDQU Y0, (DI) + VMOVDQU Y14, 32(DI) + LEAQ 64(SI), SI + LEAQ 64(DI), DI + SUBQ $0x40, BX openAVX2MainLoop: - CMPQ inl, $512 + CMPQ BX, $0x00000200 JB openAVX2MainLoopDone // Load state, increment counter blocks, store the incremented counters - VMOVDQU ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 - VMOVDQA ctr3StoreAVX2, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 - VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 - XORQ itr1, itr1 + VMOVDQU ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA Y0, Y7 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA Y14, Y11 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA Y12, Y15 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 + VMOVDQA Y4, 96(BP) + VMOVDQA Y1, 128(BP) + VMOVDQA Y2, 160(BP) + VMOVDQA Y3, 192(BP) + XORQ CX, CX openAVX2InternalLoop: - // Lets just say this spaghetti loop interleaves 2 quarter rounds with 3 poly multiplications - // Effectively per 512 bytes of stream we hash 480 bytes of ciphertext - polyAdd(0*8(inp)(itr1*1)) - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - polyMulStage1_AVX2 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - polyMulStage2_AVX2 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - polyMulStage3_AVX2 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulReduceStage - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - polyAdd(2*8(inp)(itr1*1)) - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - polyMulStage1_AVX2 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulStage2_AVX2 - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $4, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2; VPALIGNR $12, DD3, DD3, DD3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - polyMulStage3_AVX2 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - polyMulReduceStage - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - polyAdd(4*8(inp)(itr1*1)) - LEAQ (6*8)(itr1), itr1 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulStage1_AVX2 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - polyMulStage2_AVX2 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - polyMulStage3_AVX2 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulReduceStage - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $12, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2; VPALIGNR $4, DD3, DD3, DD3 - CMPQ itr1, $480 + ADDQ (SI)(CX*1), R10 + ADCQ 8(SI)(CX*1), R11 + ADCQ $0x01, R12 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + ADDQ 16(SI)(CX*1), R10 + ADCQ 24(SI)(CX*1), R11 + ADCQ $0x01, R12 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x04, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPALIGNR $0x0c, Y3, Y3, Y3 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + ADDQ 32(SI)(CX*1), R10 + ADCQ 40(SI)(CX*1), R11 + ADCQ $0x01, R12 + LEAQ 48(CX), CX + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x0c, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + VPALIGNR $0x04, Y3, Y3, Y3 + CMPQ CX, $0x000001e0 JNE openAVX2InternalLoop + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 32(BP), Y11, Y11 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD 64(BP), Y15, Y15 + VPADDD 96(BP), Y4, Y4 + VPADDD 128(BP), Y1, Y1 + VPADDD 160(BP), Y2, Y2 + VPADDD 192(BP), Y3, Y3 + VMOVDQA Y15, 224(BP) - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 - VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 - VMOVDQA CC3, tmpStoreAVX2 - // We only hashed 480 of the 512 bytes available - hash the remaining 32 here - polyAdd(480(inp)) - polyMulAVX2 - VPERM2I128 $0x02, AA0, BB0, CC3; VPERM2I128 $0x13, AA0, BB0, BB0; VPERM2I128 $0x02, CC0, DD0, AA0; VPERM2I128 $0x13, CC0, DD0, CC0 - VPXOR (0*32)(inp), CC3, CC3; VPXOR (1*32)(inp), AA0, AA0; VPXOR (2*32)(inp), BB0, BB0; VPXOR (3*32)(inp), CC0, CC0 - VMOVDQU CC3, (0*32)(oup); VMOVDQU AA0, (1*32)(oup); VMOVDQU BB0, (2*32)(oup); VMOVDQU CC0, (3*32)(oup) - VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 - VPXOR (4*32)(inp), AA0, AA0; VPXOR (5*32)(inp), BB0, BB0; VPXOR (6*32)(inp), CC0, CC0; VPXOR (7*32)(inp), DD0, DD0 - VMOVDQU AA0, (4*32)(oup); VMOVDQU BB0, (5*32)(oup); VMOVDQU CC0, (6*32)(oup); VMOVDQU DD0, (7*32)(oup) + ADDQ 480(SI), R10 + ADCQ 488(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPERM2I128 $0x02, Y0, Y14, Y15 + VPERM2I128 $0x13, Y0, Y14, Y14 + VPERM2I128 $0x02, Y12, Y4, Y0 + VPERM2I128 $0x13, Y12, Y4, Y12 + VPXOR (SI), Y15, Y15 + VPXOR 32(SI), Y0, Y0 + VPXOR 64(SI), Y14, Y14 + VPXOR 96(SI), Y12, Y12 + VMOVDQU Y15, (DI) + VMOVDQU Y0, 32(DI) + VMOVDQU Y14, 64(DI) + VMOVDQU Y12, 96(DI) + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + VPXOR 128(SI), Y0, Y0 + VPXOR 160(SI), Y14, Y14 + VPXOR 192(SI), Y12, Y12 + VPXOR 224(SI), Y4, Y4 + VMOVDQU Y0, 128(DI) + VMOVDQU Y14, 160(DI) + VMOVDQU Y12, 192(DI) + VMOVDQU Y4, 224(DI) // and here - polyAdd(496(inp)) - polyMulAVX2 - VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 - VPXOR (8*32)(inp), AA0, AA0; VPXOR (9*32)(inp), BB0, BB0; VPXOR (10*32)(inp), CC0, CC0; VPXOR (11*32)(inp), DD0, DD0 - VMOVDQU AA0, (8*32)(oup); VMOVDQU BB0, (9*32)(oup); VMOVDQU CC0, (10*32)(oup); VMOVDQU DD0, (11*32)(oup) - VPERM2I128 $0x02, AA3, BB3, AA0; VPERM2I128 $0x02, tmpStoreAVX2, DD3, BB0; VPERM2I128 $0x13, AA3, BB3, CC0; VPERM2I128 $0x13, tmpStoreAVX2, DD3, DD0 - VPXOR (12*32)(inp), AA0, AA0; VPXOR (13*32)(inp), BB0, BB0; VPXOR (14*32)(inp), CC0, CC0; VPXOR (15*32)(inp), DD0, DD0 - VMOVDQU AA0, (12*32)(oup); VMOVDQU BB0, (13*32)(oup); VMOVDQU CC0, (14*32)(oup); VMOVDQU DD0, (15*32)(oup) - LEAQ (32*16)(inp), inp - LEAQ (32*16)(oup), oup - SUBQ $(32*16), inl + ADDQ 496(SI), R10 + ADCQ 504(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + VPXOR 256(SI), Y0, Y0 + VPXOR 288(SI), Y14, Y14 + VPXOR 320(SI), Y12, Y12 + VPXOR 352(SI), Y4, Y4 + VMOVDQU Y0, 256(DI) + VMOVDQU Y14, 288(DI) + VMOVDQU Y12, 320(DI) + VMOVDQU Y4, 352(DI) + VPERM2I128 $0x02, Y7, Y11, Y0 + VPERM2I128 $0x02, 224(BP), Y3, Y14 + VPERM2I128 $0x13, Y7, Y11, Y12 + VPERM2I128 $0x13, 224(BP), Y3, Y4 + VPXOR 384(SI), Y0, Y0 + VPXOR 416(SI), Y14, Y14 + VPXOR 448(SI), Y12, Y12 + VPXOR 480(SI), Y4, Y4 + VMOVDQU Y0, 384(DI) + VMOVDQU Y14, 416(DI) + VMOVDQU Y12, 448(DI) + VMOVDQU Y4, 480(DI) + LEAQ 512(SI), SI + LEAQ 512(DI), DI + SUBQ $0x00000200, BX JMP openAVX2MainLoop openAVX2MainLoopDone: // Handle the various tail sizes efficiently - TESTQ inl, inl + TESTQ BX, BX JE openSSEFinalize - CMPQ inl, $128 + CMPQ BX, $0x80 JBE openAVX2Tail128 - CMPQ inl, $256 + CMPQ BX, $0x00000100 JBE openAVX2Tail256 - CMPQ inl, $384 + CMPQ BX, $0x00000180 JBE openAVX2Tail384 JMP openAVX2Tail512 -// ---------------------------------------------------------------------------- -// Special optimization for buffers smaller than 193 bytes openAVX2192: - // For up to 192 bytes of ciphertext and 64 bytes for the poly key, we process four blocks - VMOVDQA AA0, AA1 - VMOVDQA BB0, BB1 - VMOVDQA CC0, CC1 - VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VMOVDQA AA0, AA2 - VMOVDQA BB0, BB2 - VMOVDQA CC0, CC2 - VMOVDQA DD0, DD2 - VMOVDQA DD1, TT3 - MOVQ $10, itr2 + VMOVDQA Y0, Y5 + VMOVDQA Y14, Y9 + VMOVDQA Y12, Y13 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y0, Y6 + VMOVDQA Y14, Y10 + VMOVDQA Y12, Y8 + VMOVDQA Y4, Y2 + VMOVDQA Y1, Y15 + MOVQ $0x0000000a, R9 openAVX2192InnerCipherLoop: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1 - DECQ itr2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + DECQ R9 JNE openAVX2192InnerCipherLoop - VPADDD AA2, AA0, AA0; VPADDD AA2, AA1, AA1 - VPADDD BB2, BB0, BB0; VPADDD BB2, BB1, BB1 - VPADDD CC2, CC0, CC0; VPADDD CC2, CC1, CC1 - VPADDD DD2, DD0, DD0; VPADDD TT3, DD1, DD1 - VPERM2I128 $0x02, AA0, BB0, TT0 + VPADDD Y6, Y0, Y0 + VPADDD Y6, Y5, Y5 + VPADDD Y10, Y14, Y14 + VPADDD Y10, Y9, Y9 + VPADDD Y8, Y12, Y12 + VPADDD Y8, Y13, Y13 + VPADDD Y2, Y4, Y4 + VPADDD Y15, Y1, Y1 + VPERM2I128 $0x02, Y0, Y14, Y3 // Clamp and store poly key - VPAND ·polyClampMask<>(SB), TT0, TT0 - VMOVDQA TT0, rsStoreAVX2 + VPAND ·polyClampMask<>+0(SB), Y3, Y3 + VMOVDQA Y3, (BP) // Stream for up to 192 bytes - VPERM2I128 $0x13, AA0, BB0, AA0 - VPERM2I128 $0x13, CC0, DD0, BB0 - VPERM2I128 $0x02, AA1, BB1, CC0 - VPERM2I128 $0x02, CC1, DD1, DD0 - VPERM2I128 $0x13, AA1, BB1, AA1 - VPERM2I128 $0x13, CC1, DD1, BB1 + VPERM2I128 $0x13, Y0, Y14, Y0 + VPERM2I128 $0x13, Y12, Y4, Y14 + VPERM2I128 $0x02, Y5, Y9, Y12 + VPERM2I128 $0x02, Y13, Y1, Y4 + VPERM2I128 $0x13, Y5, Y9, Y5 + VPERM2I128 $0x13, Y13, Y1, Y9 openAVX2ShortOpen: // Hash - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) openAVX2ShortOpenLoop: - CMPQ inl, $32 + CMPQ BX, $0x20 JB openAVX2ShortTail32 - SUBQ $32, inl + SUBQ $0x20, BX // Load for hashing - polyAdd(0*8(inp)) - polyMulAVX2 - polyAdd(2*8(inp)) - polyMulAVX2 + ADDQ (SI), R10 + ADCQ 8(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + ADDQ 16(SI), R10 + ADCQ 24(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 // Load for decryption - VPXOR (inp), AA0, AA0 - VMOVDQU AA0, (oup) - LEAQ (1*32)(inp), inp - LEAQ (1*32)(oup), oup + VPXOR (SI), Y0, Y0 + VMOVDQU Y0, (DI) + LEAQ 32(SI), SI + LEAQ 32(DI), DI // Shift stream left - VMOVDQA BB0, AA0 - VMOVDQA CC0, BB0 - VMOVDQA DD0, CC0 - VMOVDQA AA1, DD0 - VMOVDQA BB1, AA1 - VMOVDQA CC1, BB1 - VMOVDQA DD1, CC1 - VMOVDQA AA2, DD1 - VMOVDQA BB2, AA2 + VMOVDQA Y14, Y0 + VMOVDQA Y12, Y14 + VMOVDQA Y4, Y12 + VMOVDQA Y5, Y4 + VMOVDQA Y9, Y5 + VMOVDQA Y13, Y9 + VMOVDQA Y1, Y13 + VMOVDQA Y6, Y1 + VMOVDQA Y10, Y6 JMP openAVX2ShortOpenLoop openAVX2ShortTail32: - CMPQ inl, $16 - VMOVDQA A0, A1 + CMPQ BX, $0x10 + VMOVDQA X0, X1 JB openAVX2ShortDone + SUBQ $0x10, BX - SUBQ $16, inl - // Load for hashing - polyAdd(0*8(inp)) - polyMulAVX2 + ADDQ (SI), R10 + ADCQ 8(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 // Load for decryption - VPXOR (inp), A0, T0 - VMOVDQU T0, (oup) - LEAQ (1*16)(inp), inp - LEAQ (1*16)(oup), oup - VPERM2I128 $0x11, AA0, AA0, AA0 - VMOVDQA A0, A1 + VPXOR (SI), X0, X12 + VMOVDQU X12, (DI) + LEAQ 16(SI), SI + LEAQ 16(DI), DI + VPERM2I128 $0x11, Y0, Y0, Y0 + VMOVDQA X0, X1 openAVX2ShortDone: VZEROUPPER JMP openSSETail16 -// ---------------------------------------------------------------------------- -// Special optimization for buffers smaller than 321 bytes openAVX2320: - // For up to 320 bytes of ciphertext and 64 bytes for the poly key, we process six blocks - VMOVDQA AA0, AA1; VMOVDQA BB0, BB1; VMOVDQA CC0, CC1; VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VMOVDQA AA0, AA2; VMOVDQA BB0, BB2; VMOVDQA CC0, CC2; VPADDD ·avx2IncMask<>(SB), DD1, DD2 - VMOVDQA BB0, TT1; VMOVDQA CC0, TT2; VMOVDQA DD0, TT3 - MOVQ $10, itr2 + VMOVDQA Y0, Y5 + VMOVDQA Y14, Y9 + VMOVDQA Y12, Y13 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y0, Y6 + VMOVDQA Y14, Y10 + VMOVDQA Y12, Y8 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VMOVDQA Y14, Y7 + VMOVDQA Y12, Y11 + VMOVDQA Y4, Y15 + MOVQ $0x0000000a, R9 openAVX2320InnerCipherLoop: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2 - DECQ itr2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + DECQ R9 JNE openAVX2320InnerCipherLoop - - VMOVDQA ·chacha20Constants<>(SB), TT0 - VPADDD TT0, AA0, AA0; VPADDD TT0, AA1, AA1; VPADDD TT0, AA2, AA2 - VPADDD TT1, BB0, BB0; VPADDD TT1, BB1, BB1; VPADDD TT1, BB2, BB2 - VPADDD TT2, CC0, CC0; VPADDD TT2, CC1, CC1; VPADDD TT2, CC2, CC2 - VMOVDQA ·avx2IncMask<>(SB), TT0 - VPADDD TT3, DD0, DD0; VPADDD TT0, TT3, TT3 - VPADDD TT3, DD1, DD1; VPADDD TT0, TT3, TT3 - VPADDD TT3, DD2, DD2 + VMOVDQA ·chacha20Constants<>+0(SB), Y3 + VPADDD Y3, Y0, Y0 + VPADDD Y3, Y5, Y5 + VPADDD Y3, Y6, Y6 + VPADDD Y7, Y14, Y14 + VPADDD Y7, Y9, Y9 + VPADDD Y7, Y10, Y10 + VPADDD Y11, Y12, Y12 + VPADDD Y11, Y13, Y13 + VPADDD Y11, Y8, Y8 + VMOVDQA ·avx2IncMask<>+0(SB), Y3 + VPADDD Y15, Y4, Y4 + VPADDD Y3, Y15, Y15 + VPADDD Y15, Y1, Y1 + VPADDD Y3, Y15, Y15 + VPADDD Y15, Y2, Y2 // Clamp and store poly key - VPERM2I128 $0x02, AA0, BB0, TT0 - VPAND ·polyClampMask<>(SB), TT0, TT0 - VMOVDQA TT0, rsStoreAVX2 + VPERM2I128 $0x02, Y0, Y14, Y3 + VPAND ·polyClampMask<>+0(SB), Y3, Y3 + VMOVDQA Y3, (BP) // Stream for up to 320 bytes - VPERM2I128 $0x13, AA0, BB0, AA0 - VPERM2I128 $0x13, CC0, DD0, BB0 - VPERM2I128 $0x02, AA1, BB1, CC0 - VPERM2I128 $0x02, CC1, DD1, DD0 - VPERM2I128 $0x13, AA1, BB1, AA1 - VPERM2I128 $0x13, CC1, DD1, BB1 - VPERM2I128 $0x02, AA2, BB2, CC1 - VPERM2I128 $0x02, CC2, DD2, DD1 - VPERM2I128 $0x13, AA2, BB2, AA2 - VPERM2I128 $0x13, CC2, DD2, BB2 + VPERM2I128 $0x13, Y0, Y14, Y0 + VPERM2I128 $0x13, Y12, Y4, Y14 + VPERM2I128 $0x02, Y5, Y9, Y12 + VPERM2I128 $0x02, Y13, Y1, Y4 + VPERM2I128 $0x13, Y5, Y9, Y5 + VPERM2I128 $0x13, Y13, Y1, Y9 + VPERM2I128 $0x02, Y6, Y10, Y13 + VPERM2I128 $0x02, Y8, Y2, Y1 + VPERM2I128 $0x13, Y6, Y10, Y6 + VPERM2I128 $0x13, Y8, Y2, Y10 JMP openAVX2ShortOpen -// ---------------------------------------------------------------------------- -// Special optimization for the last 128 bytes of ciphertext openAVX2Tail128: // Need to decrypt up to 128 bytes - prepare two blocks - VMOVDQA ·chacha20Constants<>(SB), AA1 - VMOVDQA state1StoreAVX2, BB1 - VMOVDQA state2StoreAVX2, CC1 - VMOVDQA ctr3StoreAVX2, DD1 - VPADDD ·avx2IncMask<>(SB), DD1, DD1 - VMOVDQA DD1, DD0 - - XORQ itr2, itr2 - MOVQ inl, itr1 - ANDQ $-16, itr1 - TESTQ itr1, itr1 - JE openAVX2Tail128LoopB + VMOVDQA ·chacha20Constants<>+0(SB), Y5 + VMOVDQA 32(BP), Y9 + VMOVDQA 64(BP), Y13 + VMOVDQA 192(BP), Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y1 + VMOVDQA Y1, Y4 + XORQ R9, R9 + MOVQ BX, CX + ANDQ $-16, CX + TESTQ CX, CX + JE openAVX2Tail128LoopB openAVX2Tail128LoopA: - // Perform ChaCha rounds, while hashing the remaining input - polyAdd(0(inp)(itr2*1)) - polyMulAVX2 + ADDQ (SI)(R9*1), R10 + ADCQ 8(SI)(R9*1), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 openAVX2Tail128LoopB: - ADDQ $16, itr2 - chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $4, BB1, BB1, BB1 - VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $12, DD1, DD1, DD1 - chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $12, BB1, BB1, BB1 - VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $4, DD1, DD1, DD1 - CMPQ itr2, itr1 - JB openAVX2Tail128LoopA - CMPQ itr2, $160 - JNE openAVX2Tail128LoopB - - VPADDD ·chacha20Constants<>(SB), AA1, AA1 - VPADDD state1StoreAVX2, BB1, BB1 - VPADDD state2StoreAVX2, CC1, CC1 - VPADDD DD0, DD1, DD1 - VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 + ADDQ $0x10, R9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y1, Y1, Y1 + CMPQ R9, CX + JB openAVX2Tail128LoopA + CMPQ R9, $0xa0 + JNE openAVX2Tail128LoopB + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD 32(BP), Y9, Y9 + VPADDD 64(BP), Y13, Y13 + VPADDD Y4, Y1, Y1 + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 openAVX2TailLoop: - CMPQ inl, $32 + CMPQ BX, $0x20 JB openAVX2Tail - SUBQ $32, inl + SUBQ $0x20, BX // Load for decryption - VPXOR (inp), AA0, AA0 - VMOVDQU AA0, (oup) - LEAQ (1*32)(inp), inp - LEAQ (1*32)(oup), oup - VMOVDQA BB0, AA0 - VMOVDQA CC0, BB0 - VMOVDQA DD0, CC0 + VPXOR (SI), Y0, Y0 + VMOVDQU Y0, (DI) + LEAQ 32(SI), SI + LEAQ 32(DI), DI + VMOVDQA Y14, Y0 + VMOVDQA Y12, Y14 + VMOVDQA Y4, Y12 JMP openAVX2TailLoop openAVX2Tail: - CMPQ inl, $16 - VMOVDQA A0, A1 + CMPQ BX, $0x10 + VMOVDQA X0, X1 JB openAVX2TailDone - SUBQ $16, inl + SUBQ $0x10, BX // Load for decryption - VPXOR (inp), A0, T0 - VMOVDQU T0, (oup) - LEAQ (1*16)(inp), inp - LEAQ (1*16)(oup), oup - VPERM2I128 $0x11, AA0, AA0, AA0 - VMOVDQA A0, A1 + VPXOR (SI), X0, X12 + VMOVDQU X12, (DI) + LEAQ 16(SI), SI + LEAQ 16(DI), DI + VPERM2I128 $0x11, Y0, Y0, Y0 + VMOVDQA X0, X1 openAVX2TailDone: VZEROUPPER JMP openSSETail16 -// ---------------------------------------------------------------------------- -// Special optimization for the last 256 bytes of ciphertext openAVX2Tail256: - // Need to decrypt up to 256 bytes - prepare four blocks - VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VMOVDQA DD0, TT1 - VMOVDQA DD1, TT2 + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y4, Y7 + VMOVDQA Y1, Y11 // Compute the number of iterations that will hash data - MOVQ inl, tmpStoreAVX2 - MOVQ inl, itr1 - SUBQ $128, itr1 - SHRQ $4, itr1 - MOVQ $10, itr2 - CMPQ itr1, $10 - CMOVQGT itr2, itr1 - MOVQ inp, inl - XORQ itr2, itr2 + MOVQ BX, 224(BP) + MOVQ BX, CX + SUBQ $0x80, CX + SHRQ $0x04, CX + MOVQ $0x0000000a, R9 + CMPQ CX, $0x0a + CMOVQGT R9, CX + MOVQ SI, BX + XORQ R9, R9 openAVX2Tail256LoopA: - polyAdd(0(inl)) - polyMulAVX2 - LEAQ 16(inl), inl + ADDQ (BX), R10 + ADCQ 8(BX), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(BX), BX - // Perform ChaCha rounds, while hashing the remaining input openAVX2Tail256LoopB: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1 - INCQ itr2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1 - CMPQ itr2, itr1 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + INCQ R9 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + CMPQ R9, CX JB openAVX2Tail256LoopA - - CMPQ itr2, $10 - JNE openAVX2Tail256LoopB - - MOVQ inl, itr2 - SUBQ inp, inl - MOVQ inl, itr1 - MOVQ tmpStoreAVX2, inl + CMPQ R9, $0x0a + JNE openAVX2Tail256LoopB + MOVQ BX, R9 + SUBQ SI, BX + MOVQ BX, CX + MOVQ 224(BP), BX - // Hash the remainder of data (if any) openAVX2Tail256Hash: - ADDQ $16, itr1 - CMPQ itr1, inl - JGT openAVX2Tail256HashEnd - polyAdd (0(itr2)) - polyMulAVX2 - LEAQ 16(itr2), itr2 - JMP openAVX2Tail256Hash + ADDQ $0x10, CX + CMPQ CX, BX + JGT openAVX2Tail256HashEnd + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(R9), R9 + JMP openAVX2Tail256Hash -// Store 128 bytes safely, then go to store loop openAVX2Tail256HashEnd: - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1 - VPADDD TT1, DD0, DD0; VPADDD TT2, DD1, DD1 - VPERM2I128 $0x02, AA0, BB0, AA2; VPERM2I128 $0x02, CC0, DD0, BB2; VPERM2I128 $0x13, AA0, BB0, CC2; VPERM2I128 $0x13, CC0, DD0, DD2 - VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 - - VPXOR (0*32)(inp), AA2, AA2; VPXOR (1*32)(inp), BB2, BB2; VPXOR (2*32)(inp), CC2, CC2; VPXOR (3*32)(inp), DD2, DD2 - VMOVDQU AA2, (0*32)(oup); VMOVDQU BB2, (1*32)(oup); VMOVDQU CC2, (2*32)(oup); VMOVDQU DD2, (3*32)(oup) - LEAQ (4*32)(inp), inp - LEAQ (4*32)(oup), oup - SUBQ $4*32, inl - - JMP openAVX2TailLoop + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD Y7, Y4, Y4 + VPADDD Y11, Y1, Y1 + VPERM2I128 $0x02, Y0, Y14, Y6 + VPERM2I128 $0x02, Y12, Y4, Y10 + VPERM2I128 $0x13, Y0, Y14, Y8 + VPERM2I128 $0x13, Y12, Y4, Y2 + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + VPXOR (SI), Y6, Y6 + VPXOR 32(SI), Y10, Y10 + VPXOR 64(SI), Y8, Y8 + VPXOR 96(SI), Y2, Y2 + VMOVDQU Y6, (DI) + VMOVDQU Y10, 32(DI) + VMOVDQU Y8, 64(DI) + VMOVDQU Y2, 96(DI) + LEAQ 128(SI), SI + LEAQ 128(DI), DI + SUBQ $0x80, BX + JMP openAVX2TailLoop -// ---------------------------------------------------------------------------- -// Special optimization for the last 384 bytes of ciphertext openAVX2Tail384: // Need to decrypt up to 384 bytes - prepare six blocks - VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VPADDD ·avx2IncMask<>(SB), DD1, DD2 - VMOVDQA DD0, ctr0StoreAVX2 - VMOVDQA DD1, ctr1StoreAVX2 - VMOVDQA DD2, ctr2StoreAVX2 + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VMOVDQA Y4, 96(BP) + VMOVDQA Y1, 128(BP) + VMOVDQA Y2, 160(BP) // Compute the number of iterations that will hash two blocks of data - MOVQ inl, tmpStoreAVX2 - MOVQ inl, itr1 - SUBQ $256, itr1 - SHRQ $4, itr1 - ADDQ $6, itr1 - MOVQ $10, itr2 - CMPQ itr1, $10 - CMOVQGT itr2, itr1 - MOVQ inp, inl - XORQ itr2, itr2 + MOVQ BX, 224(BP) + MOVQ BX, CX + SUBQ $0x00000100, CX + SHRQ $0x04, CX + ADDQ $0x06, CX + MOVQ $0x0000000a, R9 + CMPQ CX, $0x0a + CMOVQGT R9, CX + MOVQ SI, BX + XORQ R9, R9 - // Perform ChaCha rounds, while hashing the remaining input openAVX2Tail384LoopB: - polyAdd(0(inl)) - polyMulAVX2 - LEAQ 16(inl), inl + ADDQ (BX), R10 + ADCQ 8(BX), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(BX), BX openAVX2Tail384LoopA: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2 - polyAdd(0(inl)) - polyMulAVX2 - LEAQ 16(inl), inl - INCQ itr2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + ADDQ (BX), R10 + ADCQ 8(BX), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(BX), BX + INCQ R9 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + CMPQ R9, CX + JB openAVX2Tail384LoopB + CMPQ R9, $0x0a + JNE openAVX2Tail384LoopA + MOVQ BX, R9 + SUBQ SI, BX + MOVQ BX, CX + MOVQ 224(BP), BX - CMPQ itr2, itr1 - JB openAVX2Tail384LoopB - - CMPQ itr2, $10 - JNE openAVX2Tail384LoopA - - MOVQ inl, itr2 - SUBQ inp, inl - MOVQ inl, itr1 - MOVQ tmpStoreAVX2, inl - openAVX2Tail384Hash: - ADDQ $16, itr1 - CMPQ itr1, inl - JGT openAVX2Tail384HashEnd - polyAdd(0(itr2)) - polyMulAVX2 - LEAQ 16(itr2), itr2 - JMP openAVX2Tail384Hash + ADDQ $0x10, CX + CMPQ CX, BX + JGT openAVX2Tail384HashEnd + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(R9), R9 + JMP openAVX2Tail384Hash -// Store 256 bytes safely, then go to store loop openAVX2Tail384HashEnd: - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2 - VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2 - VPERM2I128 $0x02, AA0, BB0, TT0; VPERM2I128 $0x02, CC0, DD0, TT1; VPERM2I128 $0x13, AA0, BB0, TT2; VPERM2I128 $0x13, CC0, DD0, TT3 - VPXOR (0*32)(inp), TT0, TT0; VPXOR (1*32)(inp), TT1, TT1; VPXOR (2*32)(inp), TT2, TT2; VPXOR (3*32)(inp), TT3, TT3 - VMOVDQU TT0, (0*32)(oup); VMOVDQU TT1, (1*32)(oup); VMOVDQU TT2, (2*32)(oup); VMOVDQU TT3, (3*32)(oup) - VPERM2I128 $0x02, AA1, BB1, TT0; VPERM2I128 $0x02, CC1, DD1, TT1; VPERM2I128 $0x13, AA1, BB1, TT2; VPERM2I128 $0x13, CC1, DD1, TT3 - VPXOR (4*32)(inp), TT0, TT0; VPXOR (5*32)(inp), TT1, TT1; VPXOR (6*32)(inp), TT2, TT2; VPXOR (7*32)(inp), TT3, TT3 - VMOVDQU TT0, (4*32)(oup); VMOVDQU TT1, (5*32)(oup); VMOVDQU TT2, (6*32)(oup); VMOVDQU TT3, (7*32)(oup) - VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 - LEAQ (8*32)(inp), inp - LEAQ (8*32)(oup), oup - SUBQ $8*32, inl + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD 96(BP), Y4, Y4 + VPADDD 128(BP), Y1, Y1 + VPADDD 160(BP), Y2, Y2 + VPERM2I128 $0x02, Y0, Y14, Y3 + VPERM2I128 $0x02, Y12, Y4, Y7 + VPERM2I128 $0x13, Y0, Y14, Y11 + VPERM2I128 $0x13, Y12, Y4, Y15 + VPXOR (SI), Y3, Y3 + VPXOR 32(SI), Y7, Y7 + VPXOR 64(SI), Y11, Y11 + VPXOR 96(SI), Y15, Y15 + VMOVDQU Y3, (DI) + VMOVDQU Y7, 32(DI) + VMOVDQU Y11, 64(DI) + VMOVDQU Y15, 96(DI) + VPERM2I128 $0x02, Y5, Y9, Y3 + VPERM2I128 $0x02, Y13, Y1, Y7 + VPERM2I128 $0x13, Y5, Y9, Y11 + VPERM2I128 $0x13, Y13, Y1, Y15 + VPXOR 128(SI), Y3, Y3 + VPXOR 160(SI), Y7, Y7 + VPXOR 192(SI), Y11, Y11 + VPXOR 224(SI), Y15, Y15 + VMOVDQU Y3, 128(DI) + VMOVDQU Y7, 160(DI) + VMOVDQU Y11, 192(DI) + VMOVDQU Y15, 224(DI) + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + LEAQ 256(SI), SI + LEAQ 256(DI), DI + SUBQ $0x00000100, BX JMP openAVX2TailLoop -// ---------------------------------------------------------------------------- -// Special optimization for the last 512 bytes of ciphertext openAVX2Tail512: - VMOVDQU ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 - VMOVDQA ctr3StoreAVX2, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 - VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 - XORQ itr1, itr1 - MOVQ inp, itr2 + VMOVDQU ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA Y0, Y7 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA Y14, Y11 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA Y12, Y15 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 + VMOVDQA Y4, 96(BP) + VMOVDQA Y1, 128(BP) + VMOVDQA Y2, 160(BP) + VMOVDQA Y3, 192(BP) + XORQ CX, CX + MOVQ SI, R9 openAVX2Tail512LoopB: - polyAdd(0(itr2)) - polyMulAVX2 - LEAQ (2*8)(itr2), itr2 + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(R9), R9 openAVX2Tail512LoopA: - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyAdd(0*8(itr2)) - polyMulAVX2 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $4, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2; VPALIGNR $12, DD3, DD3, DD3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - polyAdd(2*8(itr2)) - polyMulAVX2 - LEAQ (4*8)(itr2), itr2 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $12, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2; VPALIGNR $4, DD3, DD3, DD3 - INCQ itr1 - CMPQ itr1, $4 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x04, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPALIGNR $0x0c, Y3, Y3, Y3 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + ADDQ 16(R9), R10 + ADCQ 24(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(R9), R9 + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x0c, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + VPALIGNR $0x04, Y3, Y3, Y3 + INCQ CX + CMPQ CX, $0x04 JLT openAVX2Tail512LoopB + CMPQ CX, $0x0a + JNE openAVX2Tail512LoopA + MOVQ BX, CX + SUBQ $0x00000180, CX + ANDQ $-16, CX - CMPQ itr1, $10 - JNE openAVX2Tail512LoopA - - MOVQ inl, itr1 - SUBQ $384, itr1 - ANDQ $-16, itr1 - openAVX2Tail512HashLoop: - TESTQ itr1, itr1 + TESTQ CX, CX JE openAVX2Tail512HashEnd - polyAdd(0(itr2)) - polyMulAVX2 - LEAQ 16(itr2), itr2 - SUBQ $16, itr1 + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(R9), R9 + SUBQ $0x10, CX JMP openAVX2Tail512HashLoop openAVX2Tail512HashEnd: - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 - VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 - VMOVDQA CC3, tmpStoreAVX2 - VPERM2I128 $0x02, AA0, BB0, CC3; VPERM2I128 $0x13, AA0, BB0, BB0; VPERM2I128 $0x02, CC0, DD0, AA0; VPERM2I128 $0x13, CC0, DD0, CC0 - VPXOR (0*32)(inp), CC3, CC3; VPXOR (1*32)(inp), AA0, AA0; VPXOR (2*32)(inp), BB0, BB0; VPXOR (3*32)(inp), CC0, CC0 - VMOVDQU CC3, (0*32)(oup); VMOVDQU AA0, (1*32)(oup); VMOVDQU BB0, (2*32)(oup); VMOVDQU CC0, (3*32)(oup) - VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 - VPXOR (4*32)(inp), AA0, AA0; VPXOR (5*32)(inp), BB0, BB0; VPXOR (6*32)(inp), CC0, CC0; VPXOR (7*32)(inp), DD0, DD0 - VMOVDQU AA0, (4*32)(oup); VMOVDQU BB0, (5*32)(oup); VMOVDQU CC0, (6*32)(oup); VMOVDQU DD0, (7*32)(oup) - VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 - VPXOR (8*32)(inp), AA0, AA0; VPXOR (9*32)(inp), BB0, BB0; VPXOR (10*32)(inp), CC0, CC0; VPXOR (11*32)(inp), DD0, DD0 - VMOVDQU AA0, (8*32)(oup); VMOVDQU BB0, (9*32)(oup); VMOVDQU CC0, (10*32)(oup); VMOVDQU DD0, (11*32)(oup) - VPERM2I128 $0x02, AA3, BB3, AA0; VPERM2I128 $0x02, tmpStoreAVX2, DD3, BB0; VPERM2I128 $0x13, AA3, BB3, CC0; VPERM2I128 $0x13, tmpStoreAVX2, DD3, DD0 + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 32(BP), Y11, Y11 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD 64(BP), Y15, Y15 + VPADDD 96(BP), Y4, Y4 + VPADDD 128(BP), Y1, Y1 + VPADDD 160(BP), Y2, Y2 + VPADDD 192(BP), Y3, Y3 + VMOVDQA Y15, 224(BP) + VPERM2I128 $0x02, Y0, Y14, Y15 + VPERM2I128 $0x13, Y0, Y14, Y14 + VPERM2I128 $0x02, Y12, Y4, Y0 + VPERM2I128 $0x13, Y12, Y4, Y12 + VPXOR (SI), Y15, Y15 + VPXOR 32(SI), Y0, Y0 + VPXOR 64(SI), Y14, Y14 + VPXOR 96(SI), Y12, Y12 + VMOVDQU Y15, (DI) + VMOVDQU Y0, 32(DI) + VMOVDQU Y14, 64(DI) + VMOVDQU Y12, 96(DI) + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + VPXOR 128(SI), Y0, Y0 + VPXOR 160(SI), Y14, Y14 + VPXOR 192(SI), Y12, Y12 + VPXOR 224(SI), Y4, Y4 + VMOVDQU Y0, 128(DI) + VMOVDQU Y14, 160(DI) + VMOVDQU Y12, 192(DI) + VMOVDQU Y4, 224(DI) + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + VPXOR 256(SI), Y0, Y0 + VPXOR 288(SI), Y14, Y14 + VPXOR 320(SI), Y12, Y12 + VPXOR 352(SI), Y4, Y4 + VMOVDQU Y0, 256(DI) + VMOVDQU Y14, 288(DI) + VMOVDQU Y12, 320(DI) + VMOVDQU Y4, 352(DI) + VPERM2I128 $0x02, Y7, Y11, Y0 + VPERM2I128 $0x02, 224(BP), Y3, Y14 + VPERM2I128 $0x13, Y7, Y11, Y12 + VPERM2I128 $0x13, 224(BP), Y3, Y4 + LEAQ 384(SI), SI + LEAQ 384(DI), DI + SUBQ $0x00000180, BX + JMP openAVX2TailLoop + +DATA ·chacha20Constants<>+0(SB)/4, $0x61707865 +DATA ·chacha20Constants<>+4(SB)/4, $0x3320646e +DATA ·chacha20Constants<>+8(SB)/4, $0x79622d32 +DATA ·chacha20Constants<>+12(SB)/4, $0x6b206574 +DATA ·chacha20Constants<>+16(SB)/4, $0x61707865 +DATA ·chacha20Constants<>+20(SB)/4, $0x3320646e +DATA ·chacha20Constants<>+24(SB)/4, $0x79622d32 +DATA ·chacha20Constants<>+28(SB)/4, $0x6b206574 +GLOBL ·chacha20Constants<>(SB), RODATA|NOPTR, $32 - LEAQ (12*32)(inp), inp - LEAQ (12*32)(oup), oup - SUBQ $12*32, inl +DATA ·polyClampMask<>+0(SB)/8, $0x0ffffffc0fffffff +DATA ·polyClampMask<>+8(SB)/8, $0x0ffffffc0ffffffc +DATA ·polyClampMask<>+16(SB)/8, $0xffffffffffffffff +DATA ·polyClampMask<>+24(SB)/8, $0xffffffffffffffff +GLOBL ·polyClampMask<>(SB), RODATA|NOPTR, $32 - JMP openAVX2TailLoop +DATA ·sseIncMask<>+0(SB)/8, $0x0000000000000001 +DATA ·sseIncMask<>+8(SB)/8, $0x0000000000000000 +GLOBL ·sseIncMask<>(SB), RODATA|NOPTR, $16 -// ---------------------------------------------------------------------------- -// ---------------------------------------------------------------------------- -// func chacha20Poly1305Seal(dst, key, src, ad []byte) -TEXT ·chacha20Poly1305Seal(SB), 0, $288-96 - // For aligned stack access +DATA ·andMask<>+0(SB)/8, $0x00000000000000ff +DATA ·andMask<>+8(SB)/8, $0x0000000000000000 +DATA ·andMask<>+16(SB)/8, $0x000000000000ffff +DATA ·andMask<>+24(SB)/8, $0x0000000000000000 +DATA ·andMask<>+32(SB)/8, $0x0000000000ffffff +DATA ·andMask<>+40(SB)/8, $0x0000000000000000 +DATA ·andMask<>+48(SB)/8, $0x00000000ffffffff +DATA ·andMask<>+56(SB)/8, $0x0000000000000000 +DATA ·andMask<>+64(SB)/8, $0x000000ffffffffff +DATA ·andMask<>+72(SB)/8, $0x0000000000000000 +DATA ·andMask<>+80(SB)/8, $0x0000ffffffffffff +DATA ·andMask<>+88(SB)/8, $0x0000000000000000 +DATA ·andMask<>+96(SB)/8, $0x00ffffffffffffff +DATA ·andMask<>+104(SB)/8, $0x0000000000000000 +DATA ·andMask<>+112(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+120(SB)/8, $0x0000000000000000 +DATA ·andMask<>+128(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+136(SB)/8, $0x00000000000000ff +DATA ·andMask<>+144(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+152(SB)/8, $0x000000000000ffff +DATA ·andMask<>+160(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+168(SB)/8, $0x0000000000ffffff +DATA ·andMask<>+176(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+184(SB)/8, $0x00000000ffffffff +DATA ·andMask<>+192(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+200(SB)/8, $0x000000ffffffffff +DATA ·andMask<>+208(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+216(SB)/8, $0x0000ffffffffffff +DATA ·andMask<>+224(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+232(SB)/8, $0x00ffffffffffffff +GLOBL ·andMask<>(SB), RODATA|NOPTR, $240 + +DATA ·avx2InitMask<>+0(SB)/8, $0x0000000000000000 +DATA ·avx2InitMask<>+8(SB)/8, $0x0000000000000000 +DATA ·avx2InitMask<>+16(SB)/8, $0x0000000000000001 +DATA ·avx2InitMask<>+24(SB)/8, $0x0000000000000000 +GLOBL ·avx2InitMask<>(SB), RODATA|NOPTR, $32 + +DATA ·rol16<>+0(SB)/8, $0x0504070601000302 +DATA ·rol16<>+8(SB)/8, $0x0d0c0f0e09080b0a +DATA ·rol16<>+16(SB)/8, $0x0504070601000302 +DATA ·rol16<>+24(SB)/8, $0x0d0c0f0e09080b0a +GLOBL ·rol16<>(SB), RODATA|NOPTR, $32 + +DATA ·rol8<>+0(SB)/8, $0x0605040702010003 +DATA ·rol8<>+8(SB)/8, $0x0e0d0c0f0a09080b +DATA ·rol8<>+16(SB)/8, $0x0605040702010003 +DATA ·rol8<>+24(SB)/8, $0x0e0d0c0f0a09080b +GLOBL ·rol8<>(SB), RODATA|NOPTR, $32 + +DATA ·avx2IncMask<>+0(SB)/8, $0x0000000000000002 +DATA ·avx2IncMask<>+8(SB)/8, $0x0000000000000000 +DATA ·avx2IncMask<>+16(SB)/8, $0x0000000000000002 +DATA ·avx2IncMask<>+24(SB)/8, $0x0000000000000000 +GLOBL ·avx2IncMask<>(SB), RODATA|NOPTR, $32 + +// func chacha20Poly1305Seal(dst []byte, key []uint32, src []byte, ad []byte) +// Requires: AVX, AVX2, BMI2, CMOV, SSE2 +TEXT ·chacha20Poly1305Seal(SB), $288-96 MOVQ SP, BP - ADDQ $32, BP + ADDQ $0x20, BP ANDQ $-32, BP - MOVQ dst+0(FP), oup - MOVQ key+24(FP), keyp - MOVQ src+48(FP), inp - MOVQ src_len+56(FP), inl - MOVQ ad+72(FP), adp - - CMPB ·useAVX2(SB), $1 + MOVQ dst_base+0(FP), DI + MOVQ key_base+24(FP), R8 + MOVQ src_base+48(FP), SI + MOVQ src_len+56(FP), BX + MOVQ ad_base+72(FP), CX + CMPB ·useAVX2+0(SB), $0x01 JE chacha20Poly1305Seal_AVX2 // Special optimization, for very short buffers - CMPQ inl, $128 - JBE sealSSE128 // About 15% faster + CMPQ BX, $0x80 + JBE sealSSE128 // In the seal case - prepare the poly key + 3 blocks of stream in the first iteration - MOVOU ·chacha20Constants<>(SB), A0 - MOVOU (1*16)(keyp), B0 - MOVOU (2*16)(keyp), C0 - MOVOU (3*16)(keyp), D0 + MOVOU ·chacha20Constants<>+0(SB), X0 + MOVOU 16(R8), X3 + MOVOU 32(R8), X6 + MOVOU 48(R8), X9 // Store state on stack for future use - MOVO B0, state1Store - MOVO C0, state2Store + MOVO X3, 32(BP) + MOVO X6, 48(BP) // Load state, increment counter blocks - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 - MOVO A2, A3; MOVO B2, B3; MOVO C2, C3; MOVO D2, D3; PADDL ·sseIncMask<>(SB), D3 + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X2, X12 + MOVO X5, X13 + MOVO X8, X14 + MOVO X11, X15 + PADDL ·sseIncMask<>+0(SB), X15 // Store counters - MOVO D0, ctr0Store; MOVO D1, ctr1Store; MOVO D2, ctr2Store; MOVO D3, ctr3Store - MOVQ $10, itr2 + MOVO X9, 80(BP) + MOVO X10, 96(BP) + MOVO X11, 112(BP) + MOVO X15, 128(BP) + MOVQ $0x0000000a, R9 sealSSEIntroLoop: - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - shiftB0Left; shiftB1Left; shiftB2Left; shiftB3Left - shiftC0Left; shiftC1Left; shiftC2Left; shiftC3Left - shiftD0Left; shiftD1Left; shiftD2Left; shiftD3Left - - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - shiftB0Right; shiftB1Right; shiftB2Right; shiftB3Right - shiftC0Right; shiftC1Right; shiftC2Right; shiftC3Right - shiftD0Right; shiftD1Right; shiftD2Right; shiftD3Right - DECQ itr2 - JNE sealSSEIntroLoop + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x0c + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x04 + DECQ R9 + JNE sealSSEIntroLoop // Add in the state - PADDD ·chacha20Constants<>(SB), A0; PADDD ·chacha20Constants<>(SB), A1; PADDD ·chacha20Constants<>(SB), A2; PADDD ·chacha20Constants<>(SB), A3 - PADDD state1Store, B0; PADDD state1Store, B1; PADDD state1Store, B2; PADDD state1Store, B3 - PADDD state2Store, C1; PADDD state2Store, C2; PADDD state2Store, C3 - PADDD ctr1Store, D1; PADDD ctr2Store, D2; PADDD ctr3Store, D3 + PADDD ·chacha20Constants<>+0(SB), X0 + PADDD ·chacha20Constants<>+0(SB), X1 + PADDD ·chacha20Constants<>+0(SB), X2 + PADDD ·chacha20Constants<>+0(SB), X12 + PADDD 32(BP), X3 + PADDD 32(BP), X4 + PADDD 32(BP), X5 + PADDD 32(BP), X13 + PADDD 48(BP), X7 + PADDD 48(BP), X8 + PADDD 48(BP), X14 + PADDD 96(BP), X10 + PADDD 112(BP), X11 + PADDD 128(BP), X15 // Clamp and store the key - PAND ·polyClampMask<>(SB), A0 - MOVO A0, rStore - MOVO B0, sStore + PAND ·polyClampMask<>+0(SB), X0 + MOVO X0, (BP) + MOVO X3, 16(BP) // Hash AAD - MOVQ ad_len+80(FP), itr2 - CALL polyHashADInternal<>(SB) + MOVQ ad_len+80(FP), R9 + CALL polyHashADInternal<>(SB) + MOVOU (SI), X0 + MOVOU 16(SI), X3 + MOVOU 32(SI), X6 + MOVOU 48(SI), X9 + PXOR X0, X1 + PXOR X3, X4 + PXOR X6, X7 + PXOR X9, X10 + MOVOU X1, (DI) + MOVOU X4, 16(DI) + MOVOU X7, 32(DI) + MOVOU X10, 48(DI) + MOVOU 64(SI), X0 + MOVOU 80(SI), X3 + MOVOU 96(SI), X6 + MOVOU 112(SI), X9 + PXOR X0, X2 + PXOR X3, X5 + PXOR X6, X8 + PXOR X9, X11 + MOVOU X2, 64(DI) + MOVOU X5, 80(DI) + MOVOU X8, 96(DI) + MOVOU X11, 112(DI) + MOVQ $0x00000080, CX + SUBQ $0x80, BX + LEAQ 128(SI), SI + MOVO X12, X1 + MOVO X13, X4 + MOVO X14, X7 + MOVO X15, X10 + CMPQ BX, $0x40 + JBE sealSSE128SealHash + MOVOU (SI), X0 + MOVOU 16(SI), X3 + MOVOU 32(SI), X6 + MOVOU 48(SI), X9 + PXOR X0, X12 + PXOR X3, X13 + PXOR X6, X14 + PXOR X9, X15 + MOVOU X12, 128(DI) + MOVOU X13, 144(DI) + MOVOU X14, 160(DI) + MOVOU X15, 176(DI) + ADDQ $0x40, CX + SUBQ $0x40, BX + LEAQ 64(SI), SI + MOVQ $0x00000002, CX + MOVQ $0x00000008, R9 + CMPQ BX, $0x40 + JBE sealSSETail64 + CMPQ BX, $0x80 + JBE sealSSETail128 + CMPQ BX, $0xc0 + JBE sealSSETail192 - MOVOU (0*16)(inp), A0; MOVOU (1*16)(inp), B0; MOVOU (2*16)(inp), C0; MOVOU (3*16)(inp), D0 - PXOR A0, A1; PXOR B0, B1; PXOR C0, C1; PXOR D0, D1 - MOVOU A1, (0*16)(oup); MOVOU B1, (1*16)(oup); MOVOU C1, (2*16)(oup); MOVOU D1, (3*16)(oup) - MOVOU (4*16)(inp), A0; MOVOU (5*16)(inp), B0; MOVOU (6*16)(inp), C0; MOVOU (7*16)(inp), D0 - PXOR A0, A2; PXOR B0, B2; PXOR C0, C2; PXOR D0, D2 - MOVOU A2, (4*16)(oup); MOVOU B2, (5*16)(oup); MOVOU C2, (6*16)(oup); MOVOU D2, (7*16)(oup) - - MOVQ $128, itr1 - SUBQ $128, inl - LEAQ 128(inp), inp - - MOVO A3, A1; MOVO B3, B1; MOVO C3, C1; MOVO D3, D1 - - CMPQ inl, $64 - JBE sealSSE128SealHash - - MOVOU (0*16)(inp), A0; MOVOU (1*16)(inp), B0; MOVOU (2*16)(inp), C0; MOVOU (3*16)(inp), D0 - PXOR A0, A3; PXOR B0, B3; PXOR C0, C3; PXOR D0, D3 - MOVOU A3, (8*16)(oup); MOVOU B3, (9*16)(oup); MOVOU C3, (10*16)(oup); MOVOU D3, (11*16)(oup) - - ADDQ $64, itr1 - SUBQ $64, inl - LEAQ 64(inp), inp - - MOVQ $2, itr1 - MOVQ $8, itr2 - - CMPQ inl, $64 - JBE sealSSETail64 - CMPQ inl, $128 - JBE sealSSETail128 - CMPQ inl, $192 - JBE sealSSETail192 - sealSSEMainLoop: // Load state, increment counter blocks - MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0 - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 - MOVO A2, A3; MOVO B2, B3; MOVO C2, C3; MOVO D2, D3; PADDL ·sseIncMask<>(SB), D3 + MOVO ·chacha20Constants<>+0(SB), X0 + MOVO 32(BP), X3 + MOVO 48(BP), X6 + MOVO 128(BP), X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X2, X12 + MOVO X5, X13 + MOVO X8, X14 + MOVO X11, X15 + PADDL ·sseIncMask<>+0(SB), X15 // Store counters - MOVO D0, ctr0Store; MOVO D1, ctr1Store; MOVO D2, ctr2Store; MOVO D3, ctr3Store + MOVO X9, 80(BP) + MOVO X10, 96(BP) + MOVO X11, 112(BP) + MOVO X15, 128(BP) sealSSEInnerLoop: - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - polyAdd(0(oup)) - shiftB0Left; shiftB1Left; shiftB2Left; shiftB3Left - shiftC0Left; shiftC1Left; shiftC2Left; shiftC3Left - shiftD0Left; shiftD1Left; shiftD2Left; shiftD3Left - polyMulStage1 - polyMulStage2 - LEAQ (2*8)(oup), oup - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - polyMulStage3 - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - polyMulReduceStage - shiftB0Right; shiftB1Right; shiftB2Right; shiftB3Right - shiftC0Right; shiftC1Right; shiftC2Right; shiftC3Right - shiftD0Right; shiftD1Right; shiftD2Right; shiftD3Right - DECQ itr2 - JGE sealSSEInnerLoop - polyAdd(0(oup)) - polyMul - LEAQ (2*8)(oup), oup - DECQ itr1 - JG sealSSEInnerLoop + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x0c + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + LEAQ 16(DI), DI + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x04 + DECQ R9 + JGE sealSSEInnerLoop + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI + DECQ CX + JG sealSSEInnerLoop // Add in the state - PADDD ·chacha20Constants<>(SB), A0; PADDD ·chacha20Constants<>(SB), A1; PADDD ·chacha20Constants<>(SB), A2; PADDD ·chacha20Constants<>(SB), A3 - PADDD state1Store, B0; PADDD state1Store, B1; PADDD state1Store, B2; PADDD state1Store, B3 - PADDD state2Store, C0; PADDD state2Store, C1; PADDD state2Store, C2; PADDD state2Store, C3 - PADDD ctr0Store, D0; PADDD ctr1Store, D1; PADDD ctr2Store, D2; PADDD ctr3Store, D3 - MOVO D3, tmpStore + PADDD ·chacha20Constants<>+0(SB), X0 + PADDD ·chacha20Constants<>+0(SB), X1 + PADDD ·chacha20Constants<>+0(SB), X2 + PADDD ·chacha20Constants<>+0(SB), X12 + PADDD 32(BP), X3 + PADDD 32(BP), X4 + PADDD 32(BP), X5 + PADDD 32(BP), X13 + PADDD 48(BP), X6 + PADDD 48(BP), X7 + PADDD 48(BP), X8 + PADDD 48(BP), X14 + PADDD 80(BP), X9 + PADDD 96(BP), X10 + PADDD 112(BP), X11 + PADDD 128(BP), X15 + MOVO X15, 64(BP) // Load - xor - store - MOVOU (0*16)(inp), D3; PXOR D3, A0 - MOVOU (1*16)(inp), D3; PXOR D3, B0 - MOVOU (2*16)(inp), D3; PXOR D3, C0 - MOVOU (3*16)(inp), D3; PXOR D3, D0 - MOVOU A0, (0*16)(oup) - MOVOU B0, (1*16)(oup) - MOVOU C0, (2*16)(oup) - MOVOU D0, (3*16)(oup) - MOVO tmpStore, D3 - - MOVOU (4*16)(inp), A0; MOVOU (5*16)(inp), B0; MOVOU (6*16)(inp), C0; MOVOU (7*16)(inp), D0 - PXOR A0, A1; PXOR B0, B1; PXOR C0, C1; PXOR D0, D1 - MOVOU A1, (4*16)(oup); MOVOU B1, (5*16)(oup); MOVOU C1, (6*16)(oup); MOVOU D1, (7*16)(oup) - MOVOU (8*16)(inp), A0; MOVOU (9*16)(inp), B0; MOVOU (10*16)(inp), C0; MOVOU (11*16)(inp), D0 - PXOR A0, A2; PXOR B0, B2; PXOR C0, C2; PXOR D0, D2 - MOVOU A2, (8*16)(oup); MOVOU B2, (9*16)(oup); MOVOU C2, (10*16)(oup); MOVOU D2, (11*16)(oup) - ADDQ $192, inp - MOVQ $192, itr1 - SUBQ $192, inl - MOVO A3, A1 - MOVO B3, B1 - MOVO C3, C1 - MOVO D3, D1 - CMPQ inl, $64 + MOVOU (SI), X15 + PXOR X15, X0 + MOVOU 16(SI), X15 + PXOR X15, X3 + MOVOU 32(SI), X15 + PXOR X15, X6 + MOVOU 48(SI), X15 + PXOR X15, X9 + MOVOU X0, (DI) + MOVOU X3, 16(DI) + MOVOU X6, 32(DI) + MOVOU X9, 48(DI) + MOVO 64(BP), X15 + MOVOU 64(SI), X0 + MOVOU 80(SI), X3 + MOVOU 96(SI), X6 + MOVOU 112(SI), X9 + PXOR X0, X1 + PXOR X3, X4 + PXOR X6, X7 + PXOR X9, X10 + MOVOU X1, 64(DI) + MOVOU X4, 80(DI) + MOVOU X7, 96(DI) + MOVOU X10, 112(DI) + MOVOU 128(SI), X0 + MOVOU 144(SI), X3 + MOVOU 160(SI), X6 + MOVOU 176(SI), X9 + PXOR X0, X2 + PXOR X3, X5 + PXOR X6, X8 + PXOR X9, X11 + MOVOU X2, 128(DI) + MOVOU X5, 144(DI) + MOVOU X8, 160(DI) + MOVOU X11, 176(DI) + ADDQ $0xc0, SI + MOVQ $0x000000c0, CX + SUBQ $0xc0, BX + MOVO X12, X1 + MOVO X13, X4 + MOVO X14, X7 + MOVO X15, X10 + CMPQ BX, $0x40 JBE sealSSE128SealHash - MOVOU (0*16)(inp), A0; MOVOU (1*16)(inp), B0; MOVOU (2*16)(inp), C0; MOVOU (3*16)(inp), D0 - PXOR A0, A3; PXOR B0, B3; PXOR C0, C3; PXOR D0, D3 - MOVOU A3, (12*16)(oup); MOVOU B3, (13*16)(oup); MOVOU C3, (14*16)(oup); MOVOU D3, (15*16)(oup) - LEAQ 64(inp), inp - SUBQ $64, inl - MOVQ $6, itr1 - MOVQ $4, itr2 - CMPQ inl, $192 + MOVOU (SI), X0 + MOVOU 16(SI), X3 + MOVOU 32(SI), X6 + MOVOU 48(SI), X9 + PXOR X0, X12 + PXOR X3, X13 + PXOR X6, X14 + PXOR X9, X15 + MOVOU X12, 192(DI) + MOVOU X13, 208(DI) + MOVOU X14, 224(DI) + MOVOU X15, 240(DI) + LEAQ 64(SI), SI + SUBQ $0x40, BX + MOVQ $0x00000006, CX + MOVQ $0x00000004, R9 + CMPQ BX, $0xc0 JG sealSSEMainLoop - - MOVQ inl, itr1 - TESTQ inl, inl + MOVQ BX, CX + TESTQ BX, BX JE sealSSE128SealHash - MOVQ $6, itr1 - CMPQ inl, $64 + MOVQ $0x00000006, CX + CMPQ BX, $0x40 JBE sealSSETail64 - CMPQ inl, $128 + CMPQ BX, $0x80 JBE sealSSETail128 JMP sealSSETail192 -// ---------------------------------------------------------------------------- -// Special optimization for the last 64 bytes of plaintext sealSSETail64: - // Need to encrypt up to 64 bytes - prepare single block, hash 192 or 256 bytes - MOVO ·chacha20Constants<>(SB), A1 - MOVO state1Store, B1 - MOVO state2Store, C1 - MOVO ctr3Store, D1 - PADDL ·sseIncMask<>(SB), D1 - MOVO D1, ctr0Store + MOVO ·chacha20Constants<>+0(SB), X1 + MOVO 32(BP), X4 + MOVO 48(BP), X7 + MOVO 128(BP), X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X10, 80(BP) sealSSETail64LoopA: - // Perform ChaCha rounds, while hashing the previously encrypted ciphertext - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealSSETail64LoopB: - chachaQR(A1, B1, C1, D1, T1) - shiftB1Left; shiftC1Left; shiftD1Left - chachaQR(A1, B1, C1, D1, T1) - shiftB1Right; shiftC1Right; shiftD1Right - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup - - DECQ itr1 - JG sealSSETail64LoopA - - DECQ itr2 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X13) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X13 + PSLLL $0x0c, X13 + PSRLL $0x14, X4 + PXOR X13, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X13) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X13 + PSLLL $0x07, X13 + PSRLL $0x19, X4 + PXOR X13, X4 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X13) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X13 + PSLLL $0x0c, X13 + PSRLL $0x14, X4 + PXOR X13, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X13) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X13 + PSLLL $0x07, X13 + PSRLL $0x19, X4 + PXOR X13, X4 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI + DECQ CX + JG sealSSETail64LoopA + DECQ R9 JGE sealSSETail64LoopB - PADDL ·chacha20Constants<>(SB), A1 - PADDL state1Store, B1 - PADDL state2Store, C1 - PADDL ctr0Store, D1 - - JMP sealSSE128Seal + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL 32(BP), X4 + PADDL 48(BP), X7 + PADDL 80(BP), X10 + JMP sealSSE128Seal -// ---------------------------------------------------------------------------- -// Special optimization for the last 128 bytes of plaintext sealSSETail128: - // Need to encrypt up to 128 bytes - prepare two blocks, hash 192 or 256 bytes - MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr0Store - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1; MOVO D1, ctr1Store + MOVO ·chacha20Constants<>+0(SB), X0 + MOVO 32(BP), X3 + MOVO 48(BP), X6 + MOVO 128(BP), X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X9, 80(BP) + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X10, 96(BP) sealSSETail128LoopA: - // Perform ChaCha rounds, while hashing the previously encrypted ciphertext - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealSSETail128LoopB: - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0) - shiftB0Left; shiftC0Left; shiftD0Left - shiftB1Left; shiftC1Left; shiftD1Left - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0) - shiftB0Right; shiftC0Right; shiftD0Right - shiftB1Right; shiftC1Right; shiftD1Right - - DECQ itr1 - JG sealSSETail128LoopA - - DECQ itr2 - JGE sealSSETail128LoopB + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + DECQ CX + JG sealSSETail128LoopA + DECQ R9 + JGE sealSSETail128LoopB + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL 32(BP), X3 + PADDL 32(BP), X4 + PADDL 48(BP), X6 + PADDL 48(BP), X7 + PADDL 80(BP), X9 + PADDL 96(BP), X10 + MOVOU (SI), X12 + MOVOU 16(SI), X13 + MOVOU 32(SI), X14 + MOVOU 48(SI), X15 + PXOR X12, X0 + PXOR X13, X3 + PXOR X14, X6 + PXOR X15, X9 + MOVOU X0, (DI) + MOVOU X3, 16(DI) + MOVOU X6, 32(DI) + MOVOU X9, 48(DI) + MOVQ $0x00000040, CX + LEAQ 64(SI), SI + SUBQ $0x40, BX + JMP sealSSE128SealHash - PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1 - PADDL state1Store, B0; PADDL state1Store, B1 - PADDL state2Store, C0; PADDL state2Store, C1 - PADDL ctr0Store, D0; PADDL ctr1Store, D1 - - MOVOU (0*16)(inp), T0; MOVOU (1*16)(inp), T1; MOVOU (2*16)(inp), T2; MOVOU (3*16)(inp), T3 - PXOR T0, A0; PXOR T1, B0; PXOR T2, C0; PXOR T3, D0 - MOVOU A0, (0*16)(oup); MOVOU B0, (1*16)(oup); MOVOU C0, (2*16)(oup); MOVOU D0, (3*16)(oup) - - MOVQ $64, itr1 - LEAQ 64(inp), inp - SUBQ $64, inl - - JMP sealSSE128SealHash - -// ---------------------------------------------------------------------------- -// Special optimization for the last 192 bytes of plaintext sealSSETail192: - // Need to encrypt up to 192 bytes - prepare three blocks, hash 192 or 256 bytes - MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr0Store - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1; MOVO D1, ctr1Store - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2; MOVO D2, ctr2Store + MOVO ·chacha20Constants<>+0(SB), X0 + MOVO 32(BP), X3 + MOVO 48(BP), X6 + MOVO 128(BP), X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X9, 80(BP) + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X10, 96(BP) + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X11, 112(BP) sealSSETail192LoopA: - // Perform ChaCha rounds, while hashing the previously encrypted ciphertext - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealSSETail192LoopB: - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Left; shiftC0Left; shiftD0Left - shiftB1Left; shiftC1Left; shiftD1Left - shiftB2Left; shiftC2Left; shiftD2Left + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + DECQ CX + JG sealSSETail192LoopA + DECQ R9 + JGE sealSSETail192LoopB + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL ·chacha20Constants<>+0(SB), X2 + PADDL 32(BP), X3 + PADDL 32(BP), X4 + PADDL 32(BP), X5 + PADDL 48(BP), X6 + PADDL 48(BP), X7 + PADDL 48(BP), X8 + PADDL 80(BP), X9 + PADDL 96(BP), X10 + PADDL 112(BP), X11 + MOVOU (SI), X12 + MOVOU 16(SI), X13 + MOVOU 32(SI), X14 + MOVOU 48(SI), X15 + PXOR X12, X0 + PXOR X13, X3 + PXOR X14, X6 + PXOR X15, X9 + MOVOU X0, (DI) + MOVOU X3, 16(DI) + MOVOU X6, 32(DI) + MOVOU X9, 48(DI) + MOVOU 64(SI), X12 + MOVOU 80(SI), X13 + MOVOU 96(SI), X14 + MOVOU 112(SI), X15 + PXOR X12, X1 + PXOR X13, X4 + PXOR X14, X7 + PXOR X15, X10 + MOVOU X1, 64(DI) + MOVOU X4, 80(DI) + MOVOU X7, 96(DI) + MOVOU X10, 112(DI) + MOVO X2, X1 + MOVO X5, X4 + MOVO X8, X7 + MOVO X11, X10 + MOVQ $0x00000080, CX + LEAQ 128(SI), SI + SUBQ $0x80, BX + JMP sealSSE128SealHash - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup - - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Right; shiftC0Right; shiftD0Right - shiftB1Right; shiftC1Right; shiftD1Right - shiftB2Right; shiftC2Right; shiftD2Right - - DECQ itr1 - JG sealSSETail192LoopA - - DECQ itr2 - JGE sealSSETail192LoopB - - PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1; PADDL ·chacha20Constants<>(SB), A2 - PADDL state1Store, B0; PADDL state1Store, B1; PADDL state1Store, B2 - PADDL state2Store, C0; PADDL state2Store, C1; PADDL state2Store, C2 - PADDL ctr0Store, D0; PADDL ctr1Store, D1; PADDL ctr2Store, D2 - - MOVOU (0*16)(inp), T0; MOVOU (1*16)(inp), T1; MOVOU (2*16)(inp), T2; MOVOU (3*16)(inp), T3 - PXOR T0, A0; PXOR T1, B0; PXOR T2, C0; PXOR T3, D0 - MOVOU A0, (0*16)(oup); MOVOU B0, (1*16)(oup); MOVOU C0, (2*16)(oup); MOVOU D0, (3*16)(oup) - MOVOU (4*16)(inp), T0; MOVOU (5*16)(inp), T1; MOVOU (6*16)(inp), T2; MOVOU (7*16)(inp), T3 - PXOR T0, A1; PXOR T1, B1; PXOR T2, C1; PXOR T3, D1 - MOVOU A1, (4*16)(oup); MOVOU B1, (5*16)(oup); MOVOU C1, (6*16)(oup); MOVOU D1, (7*16)(oup) - - MOVO A2, A1 - MOVO B2, B1 - MOVO C2, C1 - MOVO D2, D1 - MOVQ $128, itr1 - LEAQ 128(inp), inp - SUBQ $128, inl - - JMP sealSSE128SealHash - -// ---------------------------------------------------------------------------- -// Special seal optimization for buffers smaller than 129 bytes sealSSE128: - // For up to 128 bytes of ciphertext and 64 bytes for the poly key, we require to process three blocks - MOVOU ·chacha20Constants<>(SB), A0; MOVOU (1*16)(keyp), B0; MOVOU (2*16)(keyp), C0; MOVOU (3*16)(keyp), D0 - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 - MOVO B0, T1; MOVO C0, T2; MOVO D1, T3 - MOVQ $10, itr2 + MOVOU ·chacha20Constants<>+0(SB), X0 + MOVOU 16(R8), X3 + MOVOU 32(R8), X6 + MOVOU 48(R8), X9 + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X3, X13 + MOVO X6, X14 + MOVO X10, X15 + MOVQ $0x0000000a, R9 sealSSE128InnerCipherLoop: - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Left; shiftB1Left; shiftB2Left - shiftC0Left; shiftC1Left; shiftC2Left - shiftD0Left; shiftD1Left; shiftD2Left - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Right; shiftB1Right; shiftB2Right - shiftC0Right; shiftC1Right; shiftC2Right - shiftD0Right; shiftD1Right; shiftD2Right - DECQ itr2 - JNE sealSSE128InnerCipherLoop + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + DECQ R9 + JNE sealSSE128InnerCipherLoop // A0|B0 hold the Poly1305 32-byte key, C0,D0 can be discarded - PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1; PADDL ·chacha20Constants<>(SB), A2 - PADDL T1, B0; PADDL T1, B1; PADDL T1, B2 - PADDL T2, C1; PADDL T2, C2 - PADDL T3, D1; PADDL ·sseIncMask<>(SB), T3; PADDL T3, D2 - PAND ·polyClampMask<>(SB), A0 - MOVOU A0, rStore - MOVOU B0, sStore + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL ·chacha20Constants<>+0(SB), X2 + PADDL X13, X3 + PADDL X13, X4 + PADDL X13, X5 + PADDL X14, X7 + PADDL X14, X8 + PADDL X15, X10 + PADDL ·sseIncMask<>+0(SB), X15 + PADDL X15, X11 + PAND ·polyClampMask<>+0(SB), X0 + MOVOU X0, (BP) + MOVOU X3, 16(BP) // Hash - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) - XORQ itr1, itr1 + XORQ CX, CX sealSSE128SealHash: - // itr1 holds the number of bytes encrypted but not yet hashed - CMPQ itr1, $16 - JB sealSSE128Seal - polyAdd(0(oup)) - polyMul - - SUBQ $16, itr1 - ADDQ $16, oup - - JMP sealSSE128SealHash + CMPQ CX, $0x10 + JB sealSSE128Seal + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + SUBQ $0x10, CX + ADDQ $0x10, DI + JMP sealSSE128SealHash sealSSE128Seal: - CMPQ inl, $16 + CMPQ BX, $0x10 JB sealSSETail - SUBQ $16, inl + SUBQ $0x10, BX // Load for decryption - MOVOU (inp), T0 - PXOR T0, A1 - MOVOU A1, (oup) - LEAQ (1*16)(inp), inp - LEAQ (1*16)(oup), oup + MOVOU (SI), X12 + PXOR X12, X1 + MOVOU X1, (DI) + LEAQ 16(SI), SI + LEAQ 16(DI), DI // Extract for hashing - MOVQ A1, t0 - PSRLDQ $8, A1 - MOVQ A1, t1 - ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $1, acc2 - polyMul + MOVQ X1, R13 + PSRLDQ $0x08, X1 + MOVQ X1, R14 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 // Shift the stream "left" - MOVO B1, A1 - MOVO C1, B1 - MOVO D1, C1 - MOVO A2, D1 - MOVO B2, A2 - MOVO C2, B2 - MOVO D2, C2 + MOVO X4, X1 + MOVO X7, X4 + MOVO X10, X7 + MOVO X2, X10 + MOVO X5, X2 + MOVO X8, X5 + MOVO X11, X8 JMP sealSSE128Seal sealSSETail: - TESTQ inl, inl + TESTQ BX, BX JE sealSSEFinalize // We can only load the PT one byte at a time to avoid read after end of buffer - MOVQ inl, itr2 - SHLQ $4, itr2 - LEAQ ·andMask<>(SB), t0 - MOVQ inl, itr1 - LEAQ -1(inp)(inl*1), inp - XORQ t2, t2 - XORQ t3, t3 + MOVQ BX, R9 + SHLQ $0x04, R9 + LEAQ ·andMask<>+0(SB), R13 + MOVQ BX, CX + LEAQ -1(SI)(BX*1), SI + XORQ R15, R15 + XORQ R8, R8 XORQ AX, AX sealSSETailLoadLoop: - SHLQ $8, t2, t3 - SHLQ $8, t2 - MOVB (inp), AX - XORQ AX, t2 - LEAQ -1(inp), inp - DECQ itr1 + SHLQ $0x08, R15, R8 + SHLQ $0x08, R15 + MOVB (SI), AX + XORQ AX, R15 + LEAQ -1(SI), SI + DECQ CX JNE sealSSETailLoadLoop - MOVQ t2, 0+tmpStore - MOVQ t3, 8+tmpStore - PXOR 0+tmpStore, A1 - MOVOU A1, (oup) - MOVOU -16(t0)(itr2*1), T0 - PAND T0, A1 - MOVQ A1, t0 - PSRLDQ $8, A1 - MOVQ A1, t1 - ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $1, acc2 - polyMul - - ADDQ inl, oup + MOVQ R15, 64(BP) + MOVQ R8, 72(BP) + PXOR 64(BP), X1 + MOVOU X1, (DI) + MOVOU -16(R13)(R9*1), X12 + PAND X12, X1 + MOVQ X1, R13 + PSRLDQ $0x08, X1 + MOVQ X1, R14 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + ADDQ BX, DI sealSSEFinalize: // Hash in the buffer lengths - ADDQ ad_len+80(FP), acc0 - ADCQ src_len+56(FP), acc1 - ADCQ $1, acc2 - polyMul + ADDQ ad_len+80(FP), R10 + ADCQ src_len+56(FP), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 // Final reduce - MOVQ acc0, t0 - MOVQ acc1, t1 - MOVQ acc2, t2 - SUBQ $-5, acc0 - SBBQ $-1, acc1 - SBBQ $3, acc2 - CMOVQCS t0, acc0 - CMOVQCS t1, acc1 - CMOVQCS t2, acc2 + MOVQ R10, R13 + MOVQ R11, R14 + MOVQ R12, R15 + SUBQ $-5, R10 + SBBQ $-1, R11 + SBBQ $0x03, R12 + CMOVQCS R13, R10 + CMOVQCS R14, R11 + CMOVQCS R15, R12 // Add in the "s" part of the key - ADDQ 0+sStore, acc0 - ADCQ 8+sStore, acc1 + ADDQ 16(BP), R10 + ADCQ 24(BP), R11 // Finally store the tag at the end of the message - MOVQ acc0, (0*8)(oup) - MOVQ acc1, (1*8)(oup) + MOVQ R10, (DI) + MOVQ R11, 8(DI) RET -// ---------------------------------------------------------------------------- -// ------------------------- AVX2 Code ---------------------------------------- chacha20Poly1305Seal_AVX2: VZEROUPPER - VMOVDQU ·chacha20Constants<>(SB), AA0 - BYTE $0xc4; BYTE $0x42; BYTE $0x7d; BYTE $0x5a; BYTE $0x70; BYTE $0x10 // broadcasti128 16(r8), ymm14 - BYTE $0xc4; BYTE $0x42; BYTE $0x7d; BYTE $0x5a; BYTE $0x60; BYTE $0x20 // broadcasti128 32(r8), ymm12 - BYTE $0xc4; BYTE $0xc2; BYTE $0x7d; BYTE $0x5a; BYTE $0x60; BYTE $0x30 // broadcasti128 48(r8), ymm4 - VPADDD ·avx2InitMask<>(SB), DD0, DD0 + VMOVDQU ·chacha20Constants<>+0(SB), Y0 + BYTE $0xc4 + BYTE $0x42 + BYTE $0x7d + BYTE $0x5a + BYTE $0x70 + BYTE $0x10 + BYTE $0xc4 + BYTE $0x42 + BYTE $0x7d + BYTE $0x5a + BYTE $0x60 + BYTE $0x20 + BYTE $0xc4 + BYTE $0xc2 + BYTE $0x7d + BYTE $0x5a + BYTE $0x60 + BYTE $0x30 + VPADDD ·avx2InitMask<>+0(SB), Y4, Y4 // Special optimizations, for very short buffers - CMPQ inl, $192 - JBE seal192AVX2 // 33% faster - CMPQ inl, $320 - JBE seal320AVX2 // 17% faster + CMPQ BX, $0x000000c0 + JBE seal192AVX2 + CMPQ BX, $0x00000140 + JBE seal320AVX2 // For the general key prepare the key first - as a byproduct we have 64 bytes of cipher stream - VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 - VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3; VMOVDQA BB0, state1StoreAVX2 - VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3; VMOVDQA CC0, state2StoreAVX2 - VPADDD ·avx2IncMask<>(SB), DD0, DD1; VMOVDQA DD0, ctr0StoreAVX2 - VPADDD ·avx2IncMask<>(SB), DD1, DD2; VMOVDQA DD1, ctr1StoreAVX2 - VPADDD ·avx2IncMask<>(SB), DD2, DD3; VMOVDQA DD2, ctr2StoreAVX2 - VMOVDQA DD3, ctr3StoreAVX2 - MOVQ $10, itr2 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA Y0, Y7 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA Y14, Y11 + VMOVDQA Y14, 32(BP) + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA Y12, Y15 + VMOVDQA Y12, 64(BP) + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y4, 96(BP) + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VMOVDQA Y1, 128(BP) + VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 + VMOVDQA Y2, 160(BP) + VMOVDQA Y3, 192(BP) + MOVQ $0x0000000a, R9 sealAVX2IntroLoop: - VMOVDQA CC3, tmpStoreAVX2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, CC3); chachaQR_AVX2(AA1, BB1, CC1, DD1, CC3); chachaQR_AVX2(AA2, BB2, CC2, DD2, CC3) - VMOVDQA tmpStoreAVX2, CC3 - VMOVDQA CC1, tmpStoreAVX2 - chachaQR_AVX2(AA3, BB3, CC3, DD3, CC1) - VMOVDQA tmpStoreAVX2, CC1 - - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $12, DD0, DD0, DD0 - VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $12, DD1, DD1, DD1 - VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $12, DD2, DD2, DD2 - VPALIGNR $4, BB3, BB3, BB3; VPALIGNR $8, CC3, CC3, CC3; VPALIGNR $12, DD3, DD3, DD3 + VMOVDQA Y15, 224(BP) + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VMOVDQA 224(BP), Y15 + VMOVDQA Y13, 224(BP) + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x0c, Y11, Y13 + VPSRLD $0x14, Y11, Y11 + VPXOR Y13, Y11, Y11 + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x07, Y11, Y13 + VPSRLD $0x19, Y11, Y11 + VPXOR Y13, Y11, Y11 + VMOVDQA 224(BP), Y13 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPALIGNR $0x04, Y11, Y11, Y11 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x0c, Y3, Y3, Y3 + VMOVDQA Y15, 224(BP) + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VMOVDQA 224(BP), Y15 + VMOVDQA Y13, 224(BP) + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x0c, Y11, Y13 + VPSRLD $0x14, Y11, Y11 + VPXOR Y13, Y11, Y11 + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x07, Y11, Y13 + VPSRLD $0x19, Y11, Y11 + VPXOR Y13, Y11, Y11 + VMOVDQA 224(BP), Y13 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x04, Y2, Y2, Y2 + VPALIGNR $0x0c, Y11, Y11, Y11 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x04, Y3, Y3, Y3 + DECQ R9 + JNE sealAVX2IntroLoop + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 32(BP), Y11, Y11 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD 64(BP), Y15, Y15 + VPADDD 96(BP), Y4, Y4 + VPADDD 128(BP), Y1, Y1 + VPADDD 160(BP), Y2, Y2 + VPADDD 192(BP), Y3, Y3 + VPERM2I128 $0x13, Y12, Y4, Y12 + VPERM2I128 $0x02, Y0, Y14, Y4 + VPERM2I128 $0x13, Y0, Y14, Y0 - VMOVDQA CC3, tmpStoreAVX2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, CC3); chachaQR_AVX2(AA1, BB1, CC1, DD1, CC3); chachaQR_AVX2(AA2, BB2, CC2, DD2, CC3) - VMOVDQA tmpStoreAVX2, CC3 - VMOVDQA CC1, tmpStoreAVX2 - chachaQR_AVX2(AA3, BB3, CC3, DD3, CC1) - VMOVDQA tmpStoreAVX2, CC1 - - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $4, DD0, DD0, DD0 - VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $4, DD1, DD1, DD1 - VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $4, DD2, DD2, DD2 - VPALIGNR $12, BB3, BB3, BB3; VPALIGNR $8, CC3, CC3, CC3; VPALIGNR $4, DD3, DD3, DD3 - DECQ itr2 - JNE sealAVX2IntroLoop - - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 - VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 - - VPERM2I128 $0x13, CC0, DD0, CC0 // Stream bytes 96 - 127 - VPERM2I128 $0x02, AA0, BB0, DD0 // The Poly1305 key - VPERM2I128 $0x13, AA0, BB0, AA0 // Stream bytes 64 - 95 - // Clamp and store poly key - VPAND ·polyClampMask<>(SB), DD0, DD0 - VMOVDQA DD0, rsStoreAVX2 + VPAND ·polyClampMask<>+0(SB), Y4, Y4 + VMOVDQA Y4, (BP) // Hash AD - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) // Can store at least 320 bytes - VPXOR (0*32)(inp), AA0, AA0 - VPXOR (1*32)(inp), CC0, CC0 - VMOVDQU AA0, (0*32)(oup) - VMOVDQU CC0, (1*32)(oup) - - VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 - VPXOR (2*32)(inp), AA0, AA0; VPXOR (3*32)(inp), BB0, BB0; VPXOR (4*32)(inp), CC0, CC0; VPXOR (5*32)(inp), DD0, DD0 - VMOVDQU AA0, (2*32)(oup); VMOVDQU BB0, (3*32)(oup); VMOVDQU CC0, (4*32)(oup); VMOVDQU DD0, (5*32)(oup) - VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 - VPXOR (6*32)(inp), AA0, AA0; VPXOR (7*32)(inp), BB0, BB0; VPXOR (8*32)(inp), CC0, CC0; VPXOR (9*32)(inp), DD0, DD0 - VMOVDQU AA0, (6*32)(oup); VMOVDQU BB0, (7*32)(oup); VMOVDQU CC0, (8*32)(oup); VMOVDQU DD0, (9*32)(oup) - - MOVQ $320, itr1 - SUBQ $320, inl - LEAQ 320(inp), inp - - VPERM2I128 $0x02, AA3, BB3, AA0; VPERM2I128 $0x02, CC3, DD3, BB0; VPERM2I128 $0x13, AA3, BB3, CC0; VPERM2I128 $0x13, CC3, DD3, DD0 - CMPQ inl, $128 + VPXOR (SI), Y0, Y0 + VPXOR 32(SI), Y12, Y12 + VMOVDQU Y0, (DI) + VMOVDQU Y12, 32(DI) + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + VPXOR 64(SI), Y0, Y0 + VPXOR 96(SI), Y14, Y14 + VPXOR 128(SI), Y12, Y12 + VPXOR 160(SI), Y4, Y4 + VMOVDQU Y0, 64(DI) + VMOVDQU Y14, 96(DI) + VMOVDQU Y12, 128(DI) + VMOVDQU Y4, 160(DI) + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + VPXOR 192(SI), Y0, Y0 + VPXOR 224(SI), Y14, Y14 + VPXOR 256(SI), Y12, Y12 + VPXOR 288(SI), Y4, Y4 + VMOVDQU Y0, 192(DI) + VMOVDQU Y14, 224(DI) + VMOVDQU Y12, 256(DI) + VMOVDQU Y4, 288(DI) + MOVQ $0x00000140, CX + SUBQ $0x00000140, BX + LEAQ 320(SI), SI + VPERM2I128 $0x02, Y7, Y11, Y0 + VPERM2I128 $0x02, Y15, Y3, Y14 + VPERM2I128 $0x13, Y7, Y11, Y12 + VPERM2I128 $0x13, Y15, Y3, Y4 + CMPQ BX, $0x80 JBE sealAVX2SealHash + VPXOR (SI), Y0, Y0 + VPXOR 32(SI), Y14, Y14 + VPXOR 64(SI), Y12, Y12 + VPXOR 96(SI), Y4, Y4 + VMOVDQU Y0, 320(DI) + VMOVDQU Y14, 352(DI) + VMOVDQU Y12, 384(DI) + VMOVDQU Y4, 416(DI) + SUBQ $0x80, BX + LEAQ 128(SI), SI + MOVQ $0x00000008, CX + MOVQ $0x00000002, R9 + CMPQ BX, $0x80 + JBE sealAVX2Tail128 + CMPQ BX, $0x00000100 + JBE sealAVX2Tail256 + CMPQ BX, $0x00000180 + JBE sealAVX2Tail384 + CMPQ BX, $0x00000200 + JBE sealAVX2Tail512 - VPXOR (0*32)(inp), AA0, AA0; VPXOR (1*32)(inp), BB0, BB0; VPXOR (2*32)(inp), CC0, CC0; VPXOR (3*32)(inp), DD0, DD0 - VMOVDQU AA0, (10*32)(oup); VMOVDQU BB0, (11*32)(oup); VMOVDQU CC0, (12*32)(oup); VMOVDQU DD0, (13*32)(oup) - SUBQ $128, inl - LEAQ 128(inp), inp - - MOVQ $8, itr1 - MOVQ $2, itr2 - - CMPQ inl, $128 - JBE sealAVX2Tail128 - CMPQ inl, $256 - JBE sealAVX2Tail256 - CMPQ inl, $384 - JBE sealAVX2Tail384 - CMPQ inl, $512 - JBE sealAVX2Tail512 - // We have 448 bytes to hash, but main loop hashes 512 bytes at a time - perform some rounds, before the main loop - VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 - VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 - - VMOVDQA CC3, tmpStoreAVX2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, CC3); chachaQR_AVX2(AA1, BB1, CC1, DD1, CC3); chachaQR_AVX2(AA2, BB2, CC2, DD2, CC3) - VMOVDQA tmpStoreAVX2, CC3 - VMOVDQA CC1, tmpStoreAVX2 - chachaQR_AVX2(AA3, BB3, CC3, DD3, CC1) - VMOVDQA tmpStoreAVX2, CC1 - - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $12, DD0, DD0, DD0 - VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $12, DD1, DD1, DD1 - VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $12, DD2, DD2, DD2 - VPALIGNR $4, BB3, BB3, BB3; VPALIGNR $8, CC3, CC3, CC3; VPALIGNR $12, DD3, DD3, DD3 - - VMOVDQA CC3, tmpStoreAVX2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, CC3); chachaQR_AVX2(AA1, BB1, CC1, DD1, CC3); chachaQR_AVX2(AA2, BB2, CC2, DD2, CC3) - VMOVDQA tmpStoreAVX2, CC3 - VMOVDQA CC1, tmpStoreAVX2 - chachaQR_AVX2(AA3, BB3, CC3, DD3, CC1) - VMOVDQA tmpStoreAVX2, CC1 - - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $4, DD0, DD0, DD0 - VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $4, DD1, DD1, DD1 - VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $4, DD2, DD2, DD2 - VPALIGNR $12, BB3, BB3, BB3; VPALIGNR $8, CC3, CC3, CC3; VPALIGNR $4, DD3, DD3, DD3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - - SUBQ $16, oup // Adjust the pointer - MOVQ $9, itr1 - JMP sealAVX2InternalLoopStart + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA Y0, Y7 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA Y14, Y11 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA Y12, Y15 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 + VMOVDQA Y4, 96(BP) + VMOVDQA Y1, 128(BP) + VMOVDQA Y2, 160(BP) + VMOVDQA Y3, 192(BP) + VMOVDQA Y15, 224(BP) + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VMOVDQA 224(BP), Y15 + VMOVDQA Y13, 224(BP) + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x0c, Y11, Y13 + VPSRLD $0x14, Y11, Y11 + VPXOR Y13, Y11, Y11 + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x07, Y11, Y13 + VPSRLD $0x19, Y11, Y11 + VPXOR Y13, Y11, Y11 + VMOVDQA 224(BP), Y13 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPALIGNR $0x04, Y11, Y11, Y11 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x0c, Y3, Y3, Y3 + VMOVDQA Y15, 224(BP) + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VMOVDQA 224(BP), Y15 + VMOVDQA Y13, 224(BP) + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x0c, Y11, Y13 + VPSRLD $0x14, Y11, Y11 + VPXOR Y13, Y11, Y11 + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x07, Y11, Y13 + VPSRLD $0x19, Y11, Y11 + VPXOR Y13, Y11, Y11 + VMOVDQA 224(BP), Y13 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x04, Y2, Y2, Y2 + VPALIGNR $0x0c, Y11, Y11, Y11 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x04, Y3, Y3, Y3 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + SUBQ $0x10, DI + MOVQ $0x00000009, CX + JMP sealAVX2InternalLoopStart sealAVX2MainLoop: - // Load state, increment counter blocks, store the incremented counters - VMOVDQU ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 - VMOVDQA ctr3StoreAVX2, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 - VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 - MOVQ $10, itr1 + VMOVDQU ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA Y0, Y7 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA Y14, Y11 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA Y12, Y15 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 + VMOVDQA Y4, 96(BP) + VMOVDQA Y1, 128(BP) + VMOVDQA Y2, 160(BP) + VMOVDQA Y3, 192(BP) + MOVQ $0x0000000a, CX sealAVX2InternalLoop: - polyAdd(0*8(oup)) - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - polyMulStage1_AVX2 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - polyMulStage2_AVX2 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - polyMulStage3_AVX2 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulReduceStage + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 sealAVX2InternalLoopStart: - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - polyAdd(2*8(oup)) - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - polyMulStage1_AVX2 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulStage2_AVX2 - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $4, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2; VPALIGNR $12, DD3, DD3, DD3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - polyMulStage3_AVX2 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - polyMulReduceStage - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - polyAdd(4*8(oup)) - LEAQ (6*8)(oup), oup - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulStage1_AVX2 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - polyMulStage2_AVX2 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - polyMulStage3_AVX2 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulReduceStage - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $12, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2; VPALIGNR $4, DD3, DD3, DD3 - DECQ itr1 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x04, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPALIGNR $0x0c, Y3, Y3, Y3 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + ADDQ 32(DI), R10 + ADCQ 40(DI), R11 + ADCQ $0x01, R12 + LEAQ 48(DI), DI + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x0c, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + VPALIGNR $0x04, Y3, Y3, Y3 + DECQ CX JNE sealAVX2InternalLoop - - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 - VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 - VMOVDQA CC3, tmpStoreAVX2 + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 32(BP), Y11, Y11 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD 64(BP), Y15, Y15 + VPADDD 96(BP), Y4, Y4 + VPADDD 128(BP), Y1, Y1 + VPADDD 160(BP), Y2, Y2 + VPADDD 192(BP), Y3, Y3 + VMOVDQA Y15, 224(BP) // We only hashed 480 of the 512 bytes available - hash the remaining 32 here - polyAdd(0*8(oup)) - polyMulAVX2 - LEAQ (4*8)(oup), oup - VPERM2I128 $0x02, AA0, BB0, CC3; VPERM2I128 $0x13, AA0, BB0, BB0; VPERM2I128 $0x02, CC0, DD0, AA0; VPERM2I128 $0x13, CC0, DD0, CC0 - VPXOR (0*32)(inp), CC3, CC3; VPXOR (1*32)(inp), AA0, AA0; VPXOR (2*32)(inp), BB0, BB0; VPXOR (3*32)(inp), CC0, CC0 - VMOVDQU CC3, (0*32)(oup); VMOVDQU AA0, (1*32)(oup); VMOVDQU BB0, (2*32)(oup); VMOVDQU CC0, (3*32)(oup) - VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 - VPXOR (4*32)(inp), AA0, AA0; VPXOR (5*32)(inp), BB0, BB0; VPXOR (6*32)(inp), CC0, CC0; VPXOR (7*32)(inp), DD0, DD0 - VMOVDQU AA0, (4*32)(oup); VMOVDQU BB0, (5*32)(oup); VMOVDQU CC0, (6*32)(oup); VMOVDQU DD0, (7*32)(oup) + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI + VPERM2I128 $0x02, Y0, Y14, Y15 + VPERM2I128 $0x13, Y0, Y14, Y14 + VPERM2I128 $0x02, Y12, Y4, Y0 + VPERM2I128 $0x13, Y12, Y4, Y12 + VPXOR (SI), Y15, Y15 + VPXOR 32(SI), Y0, Y0 + VPXOR 64(SI), Y14, Y14 + VPXOR 96(SI), Y12, Y12 + VMOVDQU Y15, (DI) + VMOVDQU Y0, 32(DI) + VMOVDQU Y14, 64(DI) + VMOVDQU Y12, 96(DI) + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + VPXOR 128(SI), Y0, Y0 + VPXOR 160(SI), Y14, Y14 + VPXOR 192(SI), Y12, Y12 + VPXOR 224(SI), Y4, Y4 + VMOVDQU Y0, 128(DI) + VMOVDQU Y14, 160(DI) + VMOVDQU Y12, 192(DI) + VMOVDQU Y4, 224(DI) // and here - polyAdd(-2*8(oup)) - polyMulAVX2 - VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 - VPXOR (8*32)(inp), AA0, AA0; VPXOR (9*32)(inp), BB0, BB0; VPXOR (10*32)(inp), CC0, CC0; VPXOR (11*32)(inp), DD0, DD0 - VMOVDQU AA0, (8*32)(oup); VMOVDQU BB0, (9*32)(oup); VMOVDQU CC0, (10*32)(oup); VMOVDQU DD0, (11*32)(oup) - VPERM2I128 $0x02, AA3, BB3, AA0; VPERM2I128 $0x02, tmpStoreAVX2, DD3, BB0; VPERM2I128 $0x13, AA3, BB3, CC0; VPERM2I128 $0x13, tmpStoreAVX2, DD3, DD0 - VPXOR (12*32)(inp), AA0, AA0; VPXOR (13*32)(inp), BB0, BB0; VPXOR (14*32)(inp), CC0, CC0; VPXOR (15*32)(inp), DD0, DD0 - VMOVDQU AA0, (12*32)(oup); VMOVDQU BB0, (13*32)(oup); VMOVDQU CC0, (14*32)(oup); VMOVDQU DD0, (15*32)(oup) - LEAQ (32*16)(inp), inp - SUBQ $(32*16), inl - CMPQ inl, $512 + ADDQ -16(DI), R10 + ADCQ -8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + VPXOR 256(SI), Y0, Y0 + VPXOR 288(SI), Y14, Y14 + VPXOR 320(SI), Y12, Y12 + VPXOR 352(SI), Y4, Y4 + VMOVDQU Y0, 256(DI) + VMOVDQU Y14, 288(DI) + VMOVDQU Y12, 320(DI) + VMOVDQU Y4, 352(DI) + VPERM2I128 $0x02, Y7, Y11, Y0 + VPERM2I128 $0x02, 224(BP), Y3, Y14 + VPERM2I128 $0x13, Y7, Y11, Y12 + VPERM2I128 $0x13, 224(BP), Y3, Y4 + VPXOR 384(SI), Y0, Y0 + VPXOR 416(SI), Y14, Y14 + VPXOR 448(SI), Y12, Y12 + VPXOR 480(SI), Y4, Y4 + VMOVDQU Y0, 384(DI) + VMOVDQU Y14, 416(DI) + VMOVDQU Y12, 448(DI) + VMOVDQU Y4, 480(DI) + LEAQ 512(SI), SI + SUBQ $0x00000200, BX + CMPQ BX, $0x00000200 JG sealAVX2MainLoop // Tail can only hash 480 bytes - polyAdd(0*8(oup)) - polyMulAVX2 - polyAdd(2*8(oup)) - polyMulAVX2 - LEAQ 32(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI + MOVQ $0x0000000a, CX + MOVQ $0x00000000, R9 + CMPQ BX, $0x80 + JBE sealAVX2Tail128 + CMPQ BX, $0x00000100 + JBE sealAVX2Tail256 + CMPQ BX, $0x00000180 + JBE sealAVX2Tail384 + JMP sealAVX2Tail512 - MOVQ $10, itr1 - MOVQ $0, itr2 - CMPQ inl, $128 - JBE sealAVX2Tail128 - CMPQ inl, $256 - JBE sealAVX2Tail256 - CMPQ inl, $384 - JBE sealAVX2Tail384 - JMP sealAVX2Tail512 - -// ---------------------------------------------------------------------------- -// Special optimization for buffers smaller than 193 bytes seal192AVX2: - // For up to 192 bytes of ciphertext and 64 bytes for the poly key, we process four blocks - VMOVDQA AA0, AA1 - VMOVDQA BB0, BB1 - VMOVDQA CC0, CC1 - VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VMOVDQA AA0, AA2 - VMOVDQA BB0, BB2 - VMOVDQA CC0, CC2 - VMOVDQA DD0, DD2 - VMOVDQA DD1, TT3 - MOVQ $10, itr2 + VMOVDQA Y0, Y5 + VMOVDQA Y14, Y9 + VMOVDQA Y12, Y13 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y0, Y6 + VMOVDQA Y14, Y10 + VMOVDQA Y12, Y8 + VMOVDQA Y4, Y2 + VMOVDQA Y1, Y15 + MOVQ $0x0000000a, R9 sealAVX2192InnerCipherLoop: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1 - DECQ itr2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + DECQ R9 JNE sealAVX2192InnerCipherLoop - VPADDD AA2, AA0, AA0; VPADDD AA2, AA1, AA1 - VPADDD BB2, BB0, BB0; VPADDD BB2, BB1, BB1 - VPADDD CC2, CC0, CC0; VPADDD CC2, CC1, CC1 - VPADDD DD2, DD0, DD0; VPADDD TT3, DD1, DD1 - VPERM2I128 $0x02, AA0, BB0, TT0 + VPADDD Y6, Y0, Y0 + VPADDD Y6, Y5, Y5 + VPADDD Y10, Y14, Y14 + VPADDD Y10, Y9, Y9 + VPADDD Y8, Y12, Y12 + VPADDD Y8, Y13, Y13 + VPADDD Y2, Y4, Y4 + VPADDD Y15, Y1, Y1 + VPERM2I128 $0x02, Y0, Y14, Y3 // Clamp and store poly key - VPAND ·polyClampMask<>(SB), TT0, TT0 - VMOVDQA TT0, rsStoreAVX2 + VPAND ·polyClampMask<>+0(SB), Y3, Y3 + VMOVDQA Y3, (BP) // Stream for up to 192 bytes - VPERM2I128 $0x13, AA0, BB0, AA0 - VPERM2I128 $0x13, CC0, DD0, BB0 - VPERM2I128 $0x02, AA1, BB1, CC0 - VPERM2I128 $0x02, CC1, DD1, DD0 - VPERM2I128 $0x13, AA1, BB1, AA1 - VPERM2I128 $0x13, CC1, DD1, BB1 + VPERM2I128 $0x13, Y0, Y14, Y0 + VPERM2I128 $0x13, Y12, Y4, Y14 + VPERM2I128 $0x02, Y5, Y9, Y12 + VPERM2I128 $0x02, Y13, Y1, Y4 + VPERM2I128 $0x13, Y5, Y9, Y5 + VPERM2I128 $0x13, Y13, Y1, Y9 sealAVX2ShortSeal: // Hash aad - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) - XORQ itr1, itr1 + XORQ CX, CX sealAVX2SealHash: // itr1 holds the number of bytes encrypted but not yet hashed - CMPQ itr1, $16 - JB sealAVX2ShortSealLoop - polyAdd(0(oup)) - polyMul - SUBQ $16, itr1 - ADDQ $16, oup - JMP sealAVX2SealHash + CMPQ CX, $0x10 + JB sealAVX2ShortSealLoop + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + SUBQ $0x10, CX + ADDQ $0x10, DI + JMP sealAVX2SealHash sealAVX2ShortSealLoop: - CMPQ inl, $32 + CMPQ BX, $0x20 JB sealAVX2ShortTail32 - SUBQ $32, inl + SUBQ $0x20, BX // Load for encryption - VPXOR (inp), AA0, AA0 - VMOVDQU AA0, (oup) - LEAQ (1*32)(inp), inp + VPXOR (SI), Y0, Y0 + VMOVDQU Y0, (DI) + LEAQ 32(SI), SI // Now can hash - polyAdd(0*8(oup)) - polyMulAVX2 - polyAdd(2*8(oup)) - polyMulAVX2 - LEAQ (1*32)(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI // Shift stream left - VMOVDQA BB0, AA0 - VMOVDQA CC0, BB0 - VMOVDQA DD0, CC0 - VMOVDQA AA1, DD0 - VMOVDQA BB1, AA1 - VMOVDQA CC1, BB1 - VMOVDQA DD1, CC1 - VMOVDQA AA2, DD1 - VMOVDQA BB2, AA2 + VMOVDQA Y14, Y0 + VMOVDQA Y12, Y14 + VMOVDQA Y4, Y12 + VMOVDQA Y5, Y4 + VMOVDQA Y9, Y5 + VMOVDQA Y13, Y9 + VMOVDQA Y1, Y13 + VMOVDQA Y6, Y1 + VMOVDQA Y10, Y6 JMP sealAVX2ShortSealLoop sealAVX2ShortTail32: - CMPQ inl, $16 - VMOVDQA A0, A1 + CMPQ BX, $0x10 + VMOVDQA X0, X1 JB sealAVX2ShortDone + SUBQ $0x10, BX - SUBQ $16, inl - // Load for encryption - VPXOR (inp), A0, T0 - VMOVDQU T0, (oup) - LEAQ (1*16)(inp), inp + VPXOR (SI), X0, X12 + VMOVDQU X12, (DI) + LEAQ 16(SI), SI // Hash - polyAdd(0*8(oup)) - polyMulAVX2 - LEAQ (1*16)(oup), oup - VPERM2I128 $0x11, AA0, AA0, AA0 - VMOVDQA A0, A1 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI + VPERM2I128 $0x11, Y0, Y0, Y0 + VMOVDQA X0, X1 sealAVX2ShortDone: VZEROUPPER JMP sealSSETail -// ---------------------------------------------------------------------------- -// Special optimization for buffers smaller than 321 bytes seal320AVX2: - // For up to 320 bytes of ciphertext and 64 bytes for the poly key, we process six blocks - VMOVDQA AA0, AA1; VMOVDQA BB0, BB1; VMOVDQA CC0, CC1; VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VMOVDQA AA0, AA2; VMOVDQA BB0, BB2; VMOVDQA CC0, CC2; VPADDD ·avx2IncMask<>(SB), DD1, DD2 - VMOVDQA BB0, TT1; VMOVDQA CC0, TT2; VMOVDQA DD0, TT3 - MOVQ $10, itr2 + VMOVDQA Y0, Y5 + VMOVDQA Y14, Y9 + VMOVDQA Y12, Y13 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y0, Y6 + VMOVDQA Y14, Y10 + VMOVDQA Y12, Y8 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VMOVDQA Y14, Y7 + VMOVDQA Y12, Y11 + VMOVDQA Y4, Y15 + MOVQ $0x0000000a, R9 sealAVX2320InnerCipherLoop: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2 - DECQ itr2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + DECQ R9 JNE sealAVX2320InnerCipherLoop + VMOVDQA ·chacha20Constants<>+0(SB), Y3 + VPADDD Y3, Y0, Y0 + VPADDD Y3, Y5, Y5 + VPADDD Y3, Y6, Y6 + VPADDD Y7, Y14, Y14 + VPADDD Y7, Y9, Y9 + VPADDD Y7, Y10, Y10 + VPADDD Y11, Y12, Y12 + VPADDD Y11, Y13, Y13 + VPADDD Y11, Y8, Y8 + VMOVDQA ·avx2IncMask<>+0(SB), Y3 + VPADDD Y15, Y4, Y4 + VPADDD Y3, Y15, Y15 + VPADDD Y15, Y1, Y1 + VPADDD Y3, Y15, Y15 + VPADDD Y15, Y2, Y2 - VMOVDQA ·chacha20Constants<>(SB), TT0 - VPADDD TT0, AA0, AA0; VPADDD TT0, AA1, AA1; VPADDD TT0, AA2, AA2 - VPADDD TT1, BB0, BB0; VPADDD TT1, BB1, BB1; VPADDD TT1, BB2, BB2 - VPADDD TT2, CC0, CC0; VPADDD TT2, CC1, CC1; VPADDD TT2, CC2, CC2 - VMOVDQA ·avx2IncMask<>(SB), TT0 - VPADDD TT3, DD0, DD0; VPADDD TT0, TT3, TT3 - VPADDD TT3, DD1, DD1; VPADDD TT0, TT3, TT3 - VPADDD TT3, DD2, DD2 - // Clamp and store poly key - VPERM2I128 $0x02, AA0, BB0, TT0 - VPAND ·polyClampMask<>(SB), TT0, TT0 - VMOVDQA TT0, rsStoreAVX2 + VPERM2I128 $0x02, Y0, Y14, Y3 + VPAND ·polyClampMask<>+0(SB), Y3, Y3 + VMOVDQA Y3, (BP) // Stream for up to 320 bytes - VPERM2I128 $0x13, AA0, BB0, AA0 - VPERM2I128 $0x13, CC0, DD0, BB0 - VPERM2I128 $0x02, AA1, BB1, CC0 - VPERM2I128 $0x02, CC1, DD1, DD0 - VPERM2I128 $0x13, AA1, BB1, AA1 - VPERM2I128 $0x13, CC1, DD1, BB1 - VPERM2I128 $0x02, AA2, BB2, CC1 - VPERM2I128 $0x02, CC2, DD2, DD1 - VPERM2I128 $0x13, AA2, BB2, AA2 - VPERM2I128 $0x13, CC2, DD2, BB2 + VPERM2I128 $0x13, Y0, Y14, Y0 + VPERM2I128 $0x13, Y12, Y4, Y14 + VPERM2I128 $0x02, Y5, Y9, Y12 + VPERM2I128 $0x02, Y13, Y1, Y4 + VPERM2I128 $0x13, Y5, Y9, Y5 + VPERM2I128 $0x13, Y13, Y1, Y9 + VPERM2I128 $0x02, Y6, Y10, Y13 + VPERM2I128 $0x02, Y8, Y2, Y1 + VPERM2I128 $0x13, Y6, Y10, Y6 + VPERM2I128 $0x13, Y8, Y2, Y10 JMP sealAVX2ShortSeal -// ---------------------------------------------------------------------------- -// Special optimization for the last 128 bytes of ciphertext sealAVX2Tail128: - // Need to decrypt up to 128 bytes - prepare two blocks - // If we got here after the main loop - there are 512 encrypted bytes waiting to be hashed - // If we got here before the main loop - there are 448 encrpyred bytes waiting to be hashed - VMOVDQA ·chacha20Constants<>(SB), AA0 - VMOVDQA state1StoreAVX2, BB0 - VMOVDQA state2StoreAVX2, CC0 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0 - VMOVDQA DD0, DD1 + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA 32(BP), Y14 + VMOVDQA 64(BP), Y12 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VMOVDQA Y4, Y1 sealAVX2Tail128LoopA: - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealAVX2Tail128LoopB: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0) - polyAdd(0(oup)) - polyMul - VPALIGNR $4, BB0, BB0, BB0 - VPALIGNR $8, CC0, CC0, CC0 - VPALIGNR $12, DD0, DD0, DD0 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0) - polyAdd(16(oup)) - polyMul - LEAQ 32(oup), oup - VPALIGNR $12, BB0, BB0, BB0 - VPALIGNR $8, CC0, CC0, CC0 - VPALIGNR $4, DD0, DD0, DD0 - DECQ itr1 - JG sealAVX2Tail128LoopA - DECQ itr2 - JGE sealAVX2Tail128LoopB - - VPADDD ·chacha20Constants<>(SB), AA0, AA1 - VPADDD state1StoreAVX2, BB0, BB1 - VPADDD state2StoreAVX2, CC0, CC1 - VPADDD DD1, DD0, DD1 - - VPERM2I128 $0x02, AA1, BB1, AA0 - VPERM2I128 $0x02, CC1, DD1, BB0 - VPERM2I128 $0x13, AA1, BB1, CC0 - VPERM2I128 $0x13, CC1, DD1, DD0 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x04, Y4, Y4, Y4 + DECQ CX + JG sealAVX2Tail128LoopA + DECQ R9 + JGE sealAVX2Tail128LoopB + VPADDD ·chacha20Constants<>+0(SB), Y0, Y5 + VPADDD 32(BP), Y14, Y9 + VPADDD 64(BP), Y12, Y13 + VPADDD Y1, Y4, Y1 + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 JMP sealAVX2ShortSealLoop -// ---------------------------------------------------------------------------- -// Special optimization for the last 256 bytes of ciphertext sealAVX2Tail256: - // Need to decrypt up to 256 bytes - prepare two blocks - // If we got here after the main loop - there are 512 encrypted bytes waiting to be hashed - // If we got here before the main loop - there are 448 encrpyred bytes waiting to be hashed - VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA ·chacha20Constants<>(SB), AA1 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA state1StoreAVX2, BB1 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA state2StoreAVX2, CC1 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VMOVDQA DD0, TT1 - VMOVDQA DD1, TT2 + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA ·chacha20Constants<>+0(SB), Y5 + VMOVDQA 32(BP), Y14 + VMOVDQA 32(BP), Y9 + VMOVDQA 64(BP), Y12 + VMOVDQA 64(BP), Y13 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y4, Y7 + VMOVDQA Y1, Y11 sealAVX2Tail256LoopA: - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealAVX2Tail256LoopB: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - polyAdd(0(oup)) - polyMul - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - polyAdd(16(oup)) - polyMul - LEAQ 32(oup), oup - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1 - DECQ itr1 - JG sealAVX2Tail256LoopA - DECQ itr2 - JGE sealAVX2Tail256LoopB - - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1 - VPADDD TT1, DD0, DD0; VPADDD TT2, DD1, DD1 - VPERM2I128 $0x02, AA0, BB0, TT0 - VPERM2I128 $0x02, CC0, DD0, TT1 - VPERM2I128 $0x13, AA0, BB0, TT2 - VPERM2I128 $0x13, CC0, DD0, TT3 - VPXOR (0*32)(inp), TT0, TT0; VPXOR (1*32)(inp), TT1, TT1; VPXOR (2*32)(inp), TT2, TT2; VPXOR (3*32)(inp), TT3, TT3 - VMOVDQU TT0, (0*32)(oup); VMOVDQU TT1, (1*32)(oup); VMOVDQU TT2, (2*32)(oup); VMOVDQU TT3, (3*32)(oup) - MOVQ $128, itr1 - LEAQ 128(inp), inp - SUBQ $128, inl - VPERM2I128 $0x02, AA1, BB1, AA0 - VPERM2I128 $0x02, CC1, DD1, BB0 - VPERM2I128 $0x13, AA1, BB1, CC0 - VPERM2I128 $0x13, CC1, DD1, DD0 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + DECQ CX + JG sealAVX2Tail256LoopA + DECQ R9 + JGE sealAVX2Tail256LoopB + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD Y7, Y4, Y4 + VPADDD Y11, Y1, Y1 + VPERM2I128 $0x02, Y0, Y14, Y3 + VPERM2I128 $0x02, Y12, Y4, Y7 + VPERM2I128 $0x13, Y0, Y14, Y11 + VPERM2I128 $0x13, Y12, Y4, Y15 + VPXOR (SI), Y3, Y3 + VPXOR 32(SI), Y7, Y7 + VPXOR 64(SI), Y11, Y11 + VPXOR 96(SI), Y15, Y15 + VMOVDQU Y3, (DI) + VMOVDQU Y7, 32(DI) + VMOVDQU Y11, 64(DI) + VMOVDQU Y15, 96(DI) + MOVQ $0x00000080, CX + LEAQ 128(SI), SI + SUBQ $0x80, BX + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + JMP sealAVX2SealHash - JMP sealAVX2SealHash - -// ---------------------------------------------------------------------------- -// Special optimization for the last 384 bytes of ciphertext sealAVX2Tail384: - // Need to decrypt up to 384 bytes - prepare two blocks - // If we got here after the main loop - there are 512 encrypted bytes waiting to be hashed - // If we got here before the main loop - there are 448 encrpyred bytes waiting to be hashed - VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2 - VMOVDQA DD0, TT1; VMOVDQA DD1, TT2; VMOVDQA DD2, TT3 + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VMOVDQA Y4, Y7 + VMOVDQA Y1, Y11 + VMOVDQA Y2, Y15 sealAVX2Tail384LoopA: - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealAVX2Tail384LoopB: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - polyAdd(0(oup)) - polyMul - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - polyAdd(16(oup)) - polyMul - LEAQ 32(oup), oup - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2 - DECQ itr1 - JG sealAVX2Tail384LoopA - DECQ itr2 - JGE sealAVX2Tail384LoopB + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + DECQ CX + JG sealAVX2Tail384LoopA + DECQ R9 + JGE sealAVX2Tail384LoopB + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD Y7, Y4, Y4 + VPADDD Y11, Y1, Y1 + VPADDD Y15, Y2, Y2 + VPERM2I128 $0x02, Y0, Y14, Y3 + VPERM2I128 $0x02, Y12, Y4, Y7 + VPERM2I128 $0x13, Y0, Y14, Y11 + VPERM2I128 $0x13, Y12, Y4, Y15 + VPXOR (SI), Y3, Y3 + VPXOR 32(SI), Y7, Y7 + VPXOR 64(SI), Y11, Y11 + VPXOR 96(SI), Y15, Y15 + VMOVDQU Y3, (DI) + VMOVDQU Y7, 32(DI) + VMOVDQU Y11, 64(DI) + VMOVDQU Y15, 96(DI) + VPERM2I128 $0x02, Y5, Y9, Y3 + VPERM2I128 $0x02, Y13, Y1, Y7 + VPERM2I128 $0x13, Y5, Y9, Y11 + VPERM2I128 $0x13, Y13, Y1, Y15 + VPXOR 128(SI), Y3, Y3 + VPXOR 160(SI), Y7, Y7 + VPXOR 192(SI), Y11, Y11 + VPXOR 224(SI), Y15, Y15 + VMOVDQU Y3, 128(DI) + VMOVDQU Y7, 160(DI) + VMOVDQU Y11, 192(DI) + VMOVDQU Y15, 224(DI) + MOVQ $0x00000100, CX + LEAQ 256(SI), SI + SUBQ $0x00000100, BX + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + JMP sealAVX2SealHash - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2 - VPADDD TT1, DD0, DD0; VPADDD TT2, DD1, DD1; VPADDD TT3, DD2, DD2 - VPERM2I128 $0x02, AA0, BB0, TT0 - VPERM2I128 $0x02, CC0, DD0, TT1 - VPERM2I128 $0x13, AA0, BB0, TT2 - VPERM2I128 $0x13, CC0, DD0, TT3 - VPXOR (0*32)(inp), TT0, TT0; VPXOR (1*32)(inp), TT1, TT1; VPXOR (2*32)(inp), TT2, TT2; VPXOR (3*32)(inp), TT3, TT3 - VMOVDQU TT0, (0*32)(oup); VMOVDQU TT1, (1*32)(oup); VMOVDQU TT2, (2*32)(oup); VMOVDQU TT3, (3*32)(oup) - VPERM2I128 $0x02, AA1, BB1, TT0 - VPERM2I128 $0x02, CC1, DD1, TT1 - VPERM2I128 $0x13, AA1, BB1, TT2 - VPERM2I128 $0x13, CC1, DD1, TT3 - VPXOR (4*32)(inp), TT0, TT0; VPXOR (5*32)(inp), TT1, TT1; VPXOR (6*32)(inp), TT2, TT2; VPXOR (7*32)(inp), TT3, TT3 - VMOVDQU TT0, (4*32)(oup); VMOVDQU TT1, (5*32)(oup); VMOVDQU TT2, (6*32)(oup); VMOVDQU TT3, (7*32)(oup) - MOVQ $256, itr1 - LEAQ 256(inp), inp - SUBQ $256, inl - VPERM2I128 $0x02, AA2, BB2, AA0 - VPERM2I128 $0x02, CC2, DD2, BB0 - VPERM2I128 $0x13, AA2, BB2, CC0 - VPERM2I128 $0x13, CC2, DD2, DD0 - - JMP sealAVX2SealHash - -// ---------------------------------------------------------------------------- -// Special optimization for the last 512 bytes of ciphertext sealAVX2Tail512: - // Need to decrypt up to 512 bytes - prepare two blocks - // If we got here after the main loop - there are 512 encrypted bytes waiting to be hashed - // If we got here before the main loop - there are 448 encrpyred bytes waiting to be hashed - VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 - VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA Y0, Y7 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA Y14, Y11 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA Y12, Y15 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 + VMOVDQA Y4, 96(BP) + VMOVDQA Y1, 128(BP) + VMOVDQA Y2, 160(BP) + VMOVDQA Y3, 192(BP) sealAVX2Tail512LoopA: - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealAVX2Tail512LoopB: - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyAdd(0*8(oup)) - polyMulAVX2 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $4, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2; VPALIGNR $12, DD3, DD3, DD3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - polyAdd(2*8(oup)) - polyMulAVX2 - LEAQ (4*8)(oup), oup - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $12, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2; VPALIGNR $4, DD3, DD3, DD3 - - DECQ itr1 - JG sealAVX2Tail512LoopA - DECQ itr2 - JGE sealAVX2Tail512LoopB - - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 - VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 - VMOVDQA CC3, tmpStoreAVX2 - VPERM2I128 $0x02, AA0, BB0, CC3 - VPXOR (0*32)(inp), CC3, CC3 - VMOVDQU CC3, (0*32)(oup) - VPERM2I128 $0x02, CC0, DD0, CC3 - VPXOR (1*32)(inp), CC3, CC3 - VMOVDQU CC3, (1*32)(oup) - VPERM2I128 $0x13, AA0, BB0, CC3 - VPXOR (2*32)(inp), CC3, CC3 - VMOVDQU CC3, (2*32)(oup) - VPERM2I128 $0x13, CC0, DD0, CC3 - VPXOR (3*32)(inp), CC3, CC3 - VMOVDQU CC3, (3*32)(oup) - - VPERM2I128 $0x02, AA1, BB1, AA0 - VPERM2I128 $0x02, CC1, DD1, BB0 - VPERM2I128 $0x13, AA1, BB1, CC0 - VPERM2I128 $0x13, CC1, DD1, DD0 - VPXOR (4*32)(inp), AA0, AA0; VPXOR (5*32)(inp), BB0, BB0; VPXOR (6*32)(inp), CC0, CC0; VPXOR (7*32)(inp), DD0, DD0 - VMOVDQU AA0, (4*32)(oup); VMOVDQU BB0, (5*32)(oup); VMOVDQU CC0, (6*32)(oup); VMOVDQU DD0, (7*32)(oup) - - VPERM2I128 $0x02, AA2, BB2, AA0 - VPERM2I128 $0x02, CC2, DD2, BB0 - VPERM2I128 $0x13, AA2, BB2, CC0 - VPERM2I128 $0x13, CC2, DD2, DD0 - VPXOR (8*32)(inp), AA0, AA0; VPXOR (9*32)(inp), BB0, BB0; VPXOR (10*32)(inp), CC0, CC0; VPXOR (11*32)(inp), DD0, DD0 - VMOVDQU AA0, (8*32)(oup); VMOVDQU BB0, (9*32)(oup); VMOVDQU CC0, (10*32)(oup); VMOVDQU DD0, (11*32)(oup) - - MOVQ $384, itr1 - LEAQ 384(inp), inp - SUBQ $384, inl - VPERM2I128 $0x02, AA3, BB3, AA0 - VPERM2I128 $0x02, tmpStoreAVX2, DD3, BB0 - VPERM2I128 $0x13, AA3, BB3, CC0 - VPERM2I128 $0x13, tmpStoreAVX2, DD3, DD0 - - JMP sealAVX2SealHash + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x04, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPALIGNR $0x0c, Y3, Y3, Y3 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x0c, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + VPALIGNR $0x04, Y3, Y3, Y3 + DECQ CX + JG sealAVX2Tail512LoopA + DECQ R9 + JGE sealAVX2Tail512LoopB + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 32(BP), Y11, Y11 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD 64(BP), Y15, Y15 + VPADDD 96(BP), Y4, Y4 + VPADDD 128(BP), Y1, Y1 + VPADDD 160(BP), Y2, Y2 + VPADDD 192(BP), Y3, Y3 + VMOVDQA Y15, 224(BP) + VPERM2I128 $0x02, Y0, Y14, Y15 + VPXOR (SI), Y15, Y15 + VMOVDQU Y15, (DI) + VPERM2I128 $0x02, Y12, Y4, Y15 + VPXOR 32(SI), Y15, Y15 + VMOVDQU Y15, 32(DI) + VPERM2I128 $0x13, Y0, Y14, Y15 + VPXOR 64(SI), Y15, Y15 + VMOVDQU Y15, 64(DI) + VPERM2I128 $0x13, Y12, Y4, Y15 + VPXOR 96(SI), Y15, Y15 + VMOVDQU Y15, 96(DI) + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + VPXOR 128(SI), Y0, Y0 + VPXOR 160(SI), Y14, Y14 + VPXOR 192(SI), Y12, Y12 + VPXOR 224(SI), Y4, Y4 + VMOVDQU Y0, 128(DI) + VMOVDQU Y14, 160(DI) + VMOVDQU Y12, 192(DI) + VMOVDQU Y4, 224(DI) + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + VPXOR 256(SI), Y0, Y0 + VPXOR 288(SI), Y14, Y14 + VPXOR 320(SI), Y12, Y12 + VPXOR 352(SI), Y4, Y4 + VMOVDQU Y0, 256(DI) + VMOVDQU Y14, 288(DI) + VMOVDQU Y12, 320(DI) + VMOVDQU Y4, 352(DI) + MOVQ $0x00000180, CX + LEAQ 384(SI), SI + SUBQ $0x00000180, BX + VPERM2I128 $0x02, Y7, Y11, Y0 + VPERM2I128 $0x02, 224(BP), Y3, Y14 + VPERM2I128 $0x13, Y7, Y11, Y12 + VPERM2I128 $0x13, 224(BP), Y3, Y4 + JMP sealAVX2SealHash -- diff -- # indent-heuristic: true @@ -1,2715 +1,9762 @@ -// Copyright 2016 The Go Authors. All rights reserved. -// Use of this source code is governed by a BSD-style -// license that can be found in the LICENSE file. - -// This file was originally from https://golang.org/cl/24717 by Vlad Krasnov of CloudFlare. +// Code generated by command: go run chacha20poly1305_amd64_asm.go -out ../chacha20poly1305_amd64.s -pkg chacha20poly1305. DO NOT EDIT. //go:build gc && !purego #include "textflag.h" -// General register allocation -#define oup DI -#define inp SI -#define inl BX -#define adp CX // free to reuse, after we hash the additional data -#define keyp R8 // free to reuse, when we copy the key to stack -#define itr2 R9 // general iterator -#define itr1 CX // general iterator -#define acc0 R10 -#define acc1 R11 -#define acc2 R12 -#define t0 R13 -#define t1 R14 -#define t2 R15 -#define t3 R8 -// Register and stack allocation for the SSE code -#define rStore (0*16)(BP) -#define sStore (1*16)(BP) -#define state1Store (2*16)(BP) -#define state2Store (3*16)(BP) -#define tmpStore (4*16)(BP) -#define ctr0Store (5*16)(BP) -#define ctr1Store (6*16)(BP) -#define ctr2Store (7*16)(BP) -#define ctr3Store (8*16)(BP) -#define A0 X0 -#define A1 X1 -#define A2 X2 -#define B0 X3 -#define B1 X4 -#define B2 X5 -#define C0 X6 -#define C1 X7 -#define C2 X8 -#define D0 X9 -#define D1 X10 -#define D2 X11 -#define T0 X12 -#define T1 X13 -#define T2 X14 -#define T3 X15 -#define A3 T0 -#define B3 T1 -#define C3 T2 -#define D3 T3 -// Register and stack allocation for the AVX2 code -#define rsStoreAVX2 (0*32)(BP) -#define state1StoreAVX2 (1*32)(BP) -#define state2StoreAVX2 (2*32)(BP) -#define ctr0StoreAVX2 (3*32)(BP) -#define ctr1StoreAVX2 (4*32)(BP) -#define ctr2StoreAVX2 (5*32)(BP) -#define ctr3StoreAVX2 (6*32)(BP) -#define tmpStoreAVX2 (7*32)(BP) // 256 bytes on stack -#define AA0 Y0 -#define AA1 Y5 -#define AA2 Y6 -#define AA3 Y7 -#define BB0 Y14 -#define BB1 Y9 -#define BB2 Y10 -#define BB3 Y11 -#define CC0 Y12 -#define CC1 Y13 -#define CC2 Y8 -#define CC3 Y15 -#define DD0 Y4 -#define DD1 Y1 -#define DD2 Y2 -#define DD3 Y3 -#define TT0 DD3 -#define TT1 AA3 -#define TT2 BB3 -#define TT3 CC3 -// ChaCha20 constants -DATA ·chacha20Constants<>+0x00(SB)/4, $0x61707865 -DATA ·chacha20Constants<>+0x04(SB)/4, $0x3320646e -DATA ·chacha20Constants<>+0x08(SB)/4, $0x79622d32 -DATA ·chacha20Constants<>+0x0c(SB)/4, $0x6b206574 -DATA ·chacha20Constants<>+0x10(SB)/4, $0x61707865 -DATA ·chacha20Constants<>+0x14(SB)/4, $0x3320646e -DATA ·chacha20Constants<>+0x18(SB)/4, $0x79622d32 -DATA ·chacha20Constants<>+0x1c(SB)/4, $0x6b206574 -// <<< 16 with PSHUFB -DATA ·rol16<>+0x00(SB)/8, $0x0504070601000302 -DATA ·rol16<>+0x08(SB)/8, $0x0D0C0F0E09080B0A -DATA ·rol16<>+0x10(SB)/8, $0x0504070601000302 -DATA ·rol16<>+0x18(SB)/8, $0x0D0C0F0E09080B0A -// <<< 8 with PSHUFB -DATA ·rol8<>+0x00(SB)/8, $0x0605040702010003 -DATA ·rol8<>+0x08(SB)/8, $0x0E0D0C0F0A09080B -DATA ·rol8<>+0x10(SB)/8, $0x0605040702010003 -DATA ·rol8<>+0x18(SB)/8, $0x0E0D0C0F0A09080B -DATA ·avx2InitMask<>+0x00(SB)/8, $0x0 -DATA ·avx2InitMask<>+0x08(SB)/8, $0x0 -DATA ·avx2InitMask<>+0x10(SB)/8, $0x1 -DATA ·avx2InitMask<>+0x18(SB)/8, $0x0 - -DATA ·avx2IncMask<>+0x00(SB)/8, $0x2 -DATA ·avx2IncMask<>+0x08(SB)/8, $0x0 -DATA ·avx2IncMask<>+0x10(SB)/8, $0x2 -DATA ·avx2IncMask<>+0x18(SB)/8, $0x0 -// Poly1305 key clamp -DATA ·polyClampMask<>+0x00(SB)/8, $0x0FFFFFFC0FFFFFFF -DATA ·polyClampMask<>+0x08(SB)/8, $0x0FFFFFFC0FFFFFFC -DATA ·polyClampMask<>+0x10(SB)/8, $0xFFFFFFFFFFFFFFFF -DATA ·polyClampMask<>+0x18(SB)/8, $0xFFFFFFFFFFFFFFFF - -DATA ·sseIncMask<>+0x00(SB)/8, $0x1 -DATA ·sseIncMask<>+0x08(SB)/8, $0x0 -// To load/store the last < 16 bytes in a buffer -DATA ·andMask<>+0x00(SB)/8, $0x00000000000000ff -DATA ·andMask<>+0x08(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x10(SB)/8, $0x000000000000ffff -DATA ·andMask<>+0x18(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x20(SB)/8, $0x0000000000ffffff -DATA ·andMask<>+0x28(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x30(SB)/8, $0x00000000ffffffff -DATA ·andMask<>+0x38(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x40(SB)/8, $0x000000ffffffffff -DATA ·andMask<>+0x48(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x50(SB)/8, $0x0000ffffffffffff -DATA ·andMask<>+0x58(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x60(SB)/8, $0x00ffffffffffffff -DATA ·andMask<>+0x68(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x70(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0x78(SB)/8, $0x0000000000000000 -DATA ·andMask<>+0x80(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0x88(SB)/8, $0x00000000000000ff -DATA ·andMask<>+0x90(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0x98(SB)/8, $0x000000000000ffff -DATA ·andMask<>+0xa0(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0xa8(SB)/8, $0x0000000000ffffff -DATA ·andMask<>+0xb0(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0xb8(SB)/8, $0x00000000ffffffff -DATA ·andMask<>+0xc0(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0xc8(SB)/8, $0x000000ffffffffff -DATA ·andMask<>+0xd0(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0xd8(SB)/8, $0x0000ffffffffffff -DATA ·andMask<>+0xe0(SB)/8, $0xffffffffffffffff -DATA ·andMask<>+0xe8(SB)/8, $0x00ffffffffffffff - -GLOBL ·chacha20Constants<>(SB), (NOPTR+RODATA), $32 -GLOBL ·rol16<>(SB), (NOPTR+RODATA), $32 -GLOBL ·rol8<>(SB), (NOPTR+RODATA), $32 -GLOBL ·sseIncMask<>(SB), (NOPTR+RODATA), $16 -GLOBL ·avx2IncMask<>(SB), (NOPTR+RODATA), $32 -GLOBL ·avx2InitMask<>(SB), (NOPTR+RODATA), $32 -GLOBL ·polyClampMask<>(SB), (NOPTR+RODATA), $32 -GLOBL ·andMask<>(SB), (NOPTR+RODATA), $240 -// No PALIGNR in Go ASM yet (but VPALIGNR is present). -#define shiftB0Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xdb; BYTE $0x04 // PALIGNR $4, X3, X3 -#define shiftB1Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xe4; BYTE $0x04 // PALIGNR $4, X4, X4 -#define shiftB2Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xed; BYTE $0x04 // PALIGNR $4, X5, X5 -#define shiftB3Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xed; BYTE $0x04 // PALIGNR $4, X13, X13 -#define shiftC0Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xf6; BYTE $0x08 // PALIGNR $8, X6, X6 -#define shiftC1Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xff; BYTE $0x08 // PALIGNR $8, X7, X7 -#define shiftC2Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xc0; BYTE $0x08 // PALIGNR $8, X8, X8 -#define shiftC3Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xf6; BYTE $0x08 // PALIGNR $8, X14, X14 -#define shiftD0Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xc9; BYTE $0x0c // PALIGNR $12, X9, X9 -#define shiftD1Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xd2; BYTE $0x0c // PALIGNR $12, X10, X10 -#define shiftD2Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xdb; BYTE $0x0c // PALIGNR $12, X11, X11 -#define shiftD3Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xff; BYTE $0x0c // PALIGNR $12, X15, X15 -#define shiftB0Right BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xdb; BYTE $0x0c // PALIGNR $12, X3, X3 -#define shiftB1Right BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xe4; BYTE $0x0c // PALIGNR $12, X4, X4 -#define shiftB2Right BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xed; BYTE $0x0c // PALIGNR $12, X5, X5 -#define shiftB3Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xed; BYTE $0x0c // PALIGNR $12, X13, X13 -#define shiftC0Right shiftC0Left -#define shiftC1Right shiftC1Left -#define shiftC2Right shiftC2Left -#define shiftC3Right shiftC3Left -#define shiftD0Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xc9; BYTE $0x04 // PALIGNR $4, X9, X9 -#define shiftD1Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xd2; BYTE $0x04 // PALIGNR $4, X10, X10 -#define shiftD2Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xdb; BYTE $0x04 // PALIGNR $4, X11, X11 -#define shiftD3Right BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xff; BYTE $0x04 // PALIGNR $4, X15, X15 - -// Some macros - -// ROL rotates the uint32s in register R left by N bits, using temporary T. -#define ROL(N, R, T) \ - MOVO R, T; PSLLL $(N), T; PSRLL $(32-(N)), R; PXOR T, R - -// ROL16 rotates the uint32s in register R left by 16, using temporary T if needed. -#ifdef GOAMD64_v2 -#define ROL16(R, T) PSHUFB ·rol16<>(SB), R -#else -#define ROL16(R, T) ROL(16, R, T) -#endif - -// ROL8 rotates the uint32s in register R left by 8, using temporary T if needed. -#ifdef GOAMD64_v2 -#define ROL8(R, T) PSHUFB ·rol8<>(SB), R -#else -#define ROL8(R, T) ROL(8, R, T) -#endif - -#define chachaQR(A, B, C, D, T) \ - PADDD B, A; PXOR A, D; ROL16(D, T) \ - PADDD D, C; PXOR C, B; MOVO B, T; PSLLL $12, T; PSRLL $20, B; PXOR T, B \ - PADDD B, A; PXOR A, D; ROL8(D, T) \ - PADDD D, C; PXOR C, B; MOVO B, T; PSLLL $7, T; PSRLL $25, B; PXOR T, B +// func polyHashADInternal<>() +TEXT polyHashADInternal<>(SB), NOSPLIT, $0 + // Hack: Must declare #define macros inside of a function due to Avo constraints + // ROL rotates the uint32s in register R left by N bits, using temporary T. + #define ROL(N, R, T) \ + MOVO R, T; \ + PSLLL $(N), T; \ + PSRLL $(32-(N)), R; \ + PXOR T, R -#define chachaQR_AVX2(A, B, C, D, T) \ - VPADDD B, A, A; VPXOR A, D, D; VPSHUFB ·rol16<>(SB), D, D \ - VPADDD D, C, C; VPXOR C, B, B; VPSLLD $12, B, T; VPSRLD $20, B, B; VPXOR T, B, B \ - VPADDD B, A, A; VPXOR A, D, D; VPSHUFB ·rol8<>(SB), D, D \ - VPADDD D, C, C; VPXOR C, B, B; VPSLLD $7, B, T; VPSRLD $25, B, B; VPXOR T, B, B + // ROL8 rotates the uint32s in register R left by 8, using temporary T if needed. + #ifdef GOAMD64_v2 + #define ROL8(R, T) PSHUFB ·rol8<>(SB), R + #else + #define ROL8(R, T) ROL(8, R, T) + #endif -#define polyAdd(S) ADDQ S, acc0; ADCQ 8+S, acc1; ADCQ $1, acc2 -#define polyMulStage1 MOVQ (0*8)(BP), AX; MOVQ AX, t2; MULQ acc0; MOVQ AX, t0; MOVQ DX, t1; MOVQ (0*8)(BP), AX; MULQ acc1; IMULQ acc2, t2; ADDQ AX, t1; ADCQ DX, t2 -#define polyMulStage2 MOVQ (1*8)(BP), AX; MOVQ AX, t3; MULQ acc0; ADDQ AX, t1; ADCQ $0, DX; MOVQ DX, acc0; MOVQ (1*8)(BP), AX; MULQ acc1; ADDQ AX, t2; ADCQ $0, DX -#define polyMulStage3 IMULQ acc2, t3; ADDQ acc0, t2; ADCQ DX, t3 -#define polyMulReduceStage MOVQ t0, acc0; MOVQ t1, acc1; MOVQ t2, acc2; ANDQ $3, acc2; MOVQ t2, t0; ANDQ $-4, t0; MOVQ t3, t1; SHRQ $2, t3, t2; SHRQ $2, t3; ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $0, acc2; ADDQ t2, acc0; ADCQ t3, acc1; ADCQ $0, acc2 - -#define polyMulStage1_AVX2 MOVQ (0*8)(BP), DX; MOVQ DX, t2; MULXQ acc0, t0, t1; IMULQ acc2, t2; MULXQ acc1, AX, DX; ADDQ AX, t1; ADCQ DX, t2 -#define polyMulStage2_AVX2 MOVQ (1*8)(BP), DX; MULXQ acc0, acc0, AX; ADDQ acc0, t1; MULXQ acc1, acc1, t3; ADCQ acc1, t2; ADCQ $0, t3 -#define polyMulStage3_AVX2 IMULQ acc2, DX; ADDQ AX, t2; ADCQ DX, t3 - -#define polyMul polyMulStage1; polyMulStage2; polyMulStage3; polyMulReduceStage -#define polyMulAVX2 polyMulStage1_AVX2; polyMulStage2_AVX2; polyMulStage3_AVX2; polyMulReduceStage -// ---------------------------------------------------------------------------- -TEXT polyHashADInternal<>(SB), NOSPLIT, $0 - // adp points to beginning of additional data - // itr2 holds ad length - XORQ acc0, acc0 - XORQ acc1, acc1 - XORQ acc2, acc2 - CMPQ itr2, $13 - JNE hashADLoop - -openFastTLSAD: - // Special treatment for the TLS case of 13 bytes - MOVQ (adp), acc0 - MOVQ 5(adp), acc1 - SHRQ $24, acc1 - MOVQ $1, acc2 - polyMul + // ROL16 rotates the uint32s in register R left by 16, using temporary T if needed. + #ifdef GOAMD64_v2 + #define ROL16(R, T) PSHUFB ·rol16<>(SB), R + #else + #define ROL16(R, T) ROL(16, R, T) + #endif + XORQ R10, R10 + XORQ R11, R11 + XORQ R12, R12 + CMPQ R9, $0x0d + JNE hashADLoop + MOVQ (CX), R10 + MOVQ 5(CX), R11 + SHRQ $0x18, R11 + MOVQ $0x00000001, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 RET hashADLoop: // Hash in 16 byte chunks - CMPQ itr2, $16 - JB hashADTail - polyAdd(0(adp)) - LEAQ (1*16)(adp), adp - SUBQ $16, itr2 - polyMul - JMP hashADLoop + CMPQ R9, $0x10 + JB hashADTail + ADDQ (CX), R10 + ADCQ 8(CX), R11 + ADCQ $0x01, R12 + LEAQ 16(CX), CX + SUBQ $0x10, R9 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + JMP hashADLoop hashADTail: - CMPQ itr2, $0 + CMPQ R9, $0x00 JE hashADDone // Hash last < 16 byte tail - XORQ t0, t0 - XORQ t1, t1 - XORQ t2, t2 - ADDQ itr2, adp + XORQ R13, R13 + XORQ R14, R14 + XORQ R15, R15 + ADDQ R9, CX hashADTailLoop: - SHLQ $8, t0, t1 - SHLQ $8, t0 - MOVB -1(adp), t2 - XORQ t2, t0 - DECQ adp - DECQ itr2 - JNE hashADTailLoop + SHLQ $0x08, R13, R14 + SHLQ $0x08, R13 + MOVB -1(CX), R15 + XORQ R15, R13 + DECQ CX + DECQ R9 + JNE hashADTailLoop + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 -hashADTailFinish: - ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $1, acc2 - polyMul - - // Finished AD hashADDone: RET -// ---------------------------------------------------------------------------- -// func chacha20Poly1305Open(dst, key, src, ad []byte) bool -TEXT ·chacha20Poly1305Open(SB), 0, $288-97 +// func chacha20Poly1305Open(dst []byte, key []uint32, src []byte, ad []byte) bool +// Requires: AVX, AVX2, BMI2, CMOV, SSE2 +TEXT ·chacha20Poly1305Open(SB), $288-97 // For aligned stack access MOVQ SP, BP - ADDQ $32, BP + ADDQ $0x20, BP ANDQ $-32, BP - MOVQ dst+0(FP), oup - MOVQ key+24(FP), keyp - MOVQ src+48(FP), inp - MOVQ src_len+56(FP), inl - MOVQ ad+72(FP), adp + MOVQ dst_base+0(FP), DI + MOVQ key_base+24(FP), R8 + MOVQ src_base+48(FP), SI + MOVQ src_len+56(FP), BX + MOVQ ad_base+72(FP), CX // Check for AVX2 support - CMPB ·useAVX2(SB), $1 + CMPB ·useAVX2+0(SB), $0x01 JE chacha20Poly1305Open_AVX2 // Special optimization, for very short buffers - CMPQ inl, $128 - JBE openSSE128 // About 16% faster + CMPQ BX, $0x80 + JBE openSSE128 // For long buffers, prepare the poly key first - MOVOU ·chacha20Constants<>(SB), A0 - MOVOU (1*16)(keyp), B0 - MOVOU (2*16)(keyp), C0 - MOVOU (3*16)(keyp), D0 - MOVO D0, T1 + MOVOU ·chacha20Constants<>+0(SB), X0 + MOVOU 16(R8), X3 + MOVOU 32(R8), X6 + MOVOU 48(R8), X9 + MOVO X9, X13 // Store state on stack for future use - MOVO B0, state1Store - MOVO C0, state2Store - MOVO D0, ctr3Store - MOVQ $10, itr2 + MOVO X3, 32(BP) + MOVO X6, 48(BP) + MOVO X9, 128(BP) + MOVQ $0x0000000a, R9 openSSEPreparePolyKey: - chachaQR(A0, B0, C0, D0, T0) - shiftB0Left; shiftC0Left; shiftD0Left - chachaQR(A0, B0, C0, D0, T0) - shiftB0Right; shiftC0Right; shiftD0Right - DECQ itr2 - JNE openSSEPreparePolyKey + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + DECQ R9 + JNE openSSEPreparePolyKey // A0|B0 hold the Poly1305 32-byte key, C0,D0 can be discarded - PADDL ·chacha20Constants<>(SB), A0; PADDL state1Store, B0 + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL 32(BP), X3 // Clamp and store the key - PAND ·polyClampMask<>(SB), A0 - MOVO A0, rStore; MOVO B0, sStore + PAND ·polyClampMask<>+0(SB), X0 + MOVO X0, (BP) + MOVO X3, 16(BP) // Hash AAD - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) openSSEMainLoop: - CMPQ inl, $256 + CMPQ BX, $0x00000100 JB openSSEMainLoopDone // Load state, increment counter blocks - MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0 - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 - MOVO A2, A3; MOVO B2, B3; MOVO C2, C3; MOVO D2, D3; PADDL ·sseIncMask<>(SB), D3 + MOVO ·chacha20Constants<>+0(SB), X0 + MOVO 32(BP), X3 + MOVO 48(BP), X6 + MOVO 128(BP), X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X2, X12 + MOVO X5, X13 + MOVO X8, X14 + MOVO X11, X15 + PADDL ·sseIncMask<>+0(SB), X15 // Store counters - MOVO D0, ctr0Store; MOVO D1, ctr1Store; MOVO D2, ctr2Store; MOVO D3, ctr3Store + MOVO X9, 80(BP) + MOVO X10, 96(BP) + MOVO X11, 112(BP) + MOVO X15, 128(BP) - // There are 10 ChaCha20 iterations of 2QR each, so for 6 iterations we hash 2 blocks, and for the remaining 4 only 1 block - for a total of 16 - MOVQ $4, itr1 - MOVQ inp, itr2 + // There are 10 ChaCha20 iterations of 2QR each, so for 6 iterations we hash + // 2 blocks, and for the remaining 4 only 1 block - for a total of 16 + MOVQ $0x00000004, CX + MOVQ SI, R9 openSSEInternalLoop: - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - polyAdd(0(itr2)) - shiftB0Left; shiftB1Left; shiftB2Left; shiftB3Left - shiftC0Left; shiftC1Left; shiftC2Left; shiftC3Left - shiftD0Left; shiftD1Left; shiftD2Left; shiftD3Left - polyMulStage1 - polyMulStage2 - LEAQ (2*8)(itr2), itr2 - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - polyMulStage3 - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - polyMulReduceStage - shiftB0Right; shiftB1Right; shiftB2Right; shiftB3Right - shiftC0Right; shiftC1Right; shiftC2Right; shiftC3Right - shiftD0Right; shiftD1Right; shiftD2Right; shiftD3Right - DECQ itr1 - JGE openSSEInternalLoop - - polyAdd(0(itr2)) - polyMul - LEAQ (2*8)(itr2), itr2 - - CMPQ itr1, $-6 - JG openSSEInternalLoop + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x0c + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + LEAQ 16(R9), R9 + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x04 + DECQ CX + JGE openSSEInternalLoop + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(R9), R9 + CMPQ CX, $-6 + JG openSSEInternalLoop // Add in the state - PADDD ·chacha20Constants<>(SB), A0; PADDD ·chacha20Constants<>(SB), A1; PADDD ·chacha20Constants<>(SB), A2; PADDD ·chacha20Constants<>(SB), A3 - PADDD state1Store, B0; PADDD state1Store, B1; PADDD state1Store, B2; PADDD state1Store, B3 - PADDD state2Store, C0; PADDD state2Store, C1; PADDD state2Store, C2; PADDD state2Store, C3 - PADDD ctr0Store, D0; PADDD ctr1Store, D1; PADDD ctr2Store, D2; PADDD ctr3Store, D3 + PADDD ·chacha20Constants<>+0(SB), X0 + PADDD ·chacha20Constants<>+0(SB), X1 + PADDD ·chacha20Constants<>+0(SB), X2 + PADDD ·chacha20Constants<>+0(SB), X12 + PADDD 32(BP), X3 + PADDD 32(BP), X4 + PADDD 32(BP), X5 + PADDD 32(BP), X13 + PADDD 48(BP), X6 + PADDD 48(BP), X7 + PADDD 48(BP), X8 + PADDD 48(BP), X14 + PADDD 80(BP), X9 + PADDD 96(BP), X10 + PADDD 112(BP), X11 + PADDD 128(BP), X15 // Load - xor - store - MOVO D3, tmpStore - MOVOU (0*16)(inp), D3; PXOR D3, A0; MOVOU A0, (0*16)(oup) - MOVOU (1*16)(inp), D3; PXOR D3, B0; MOVOU B0, (1*16)(oup) - MOVOU (2*16)(inp), D3; PXOR D3, C0; MOVOU C0, (2*16)(oup) - MOVOU (3*16)(inp), D3; PXOR D3, D0; MOVOU D0, (3*16)(oup) - MOVOU (4*16)(inp), D0; PXOR D0, A1; MOVOU A1, (4*16)(oup) - MOVOU (5*16)(inp), D0; PXOR D0, B1; MOVOU B1, (5*16)(oup) - MOVOU (6*16)(inp), D0; PXOR D0, C1; MOVOU C1, (6*16)(oup) - MOVOU (7*16)(inp), D0; PXOR D0, D1; MOVOU D1, (7*16)(oup) - MOVOU (8*16)(inp), D0; PXOR D0, A2; MOVOU A2, (8*16)(oup) - MOVOU (9*16)(inp), D0; PXOR D0, B2; MOVOU B2, (9*16)(oup) - MOVOU (10*16)(inp), D0; PXOR D0, C2; MOVOU C2, (10*16)(oup) - MOVOU (11*16)(inp), D0; PXOR D0, D2; MOVOU D2, (11*16)(oup) - MOVOU (12*16)(inp), D0; PXOR D0, A3; MOVOU A3, (12*16)(oup) - MOVOU (13*16)(inp), D0; PXOR D0, B3; MOVOU B3, (13*16)(oup) - MOVOU (14*16)(inp), D0; PXOR D0, C3; MOVOU C3, (14*16)(oup) - MOVOU (15*16)(inp), D0; PXOR tmpStore, D0; MOVOU D0, (15*16)(oup) - LEAQ 256(inp), inp - LEAQ 256(oup), oup - SUBQ $256, inl + MOVO X15, 64(BP) + MOVOU (SI), X15 + PXOR X15, X0 + MOVOU X0, (DI) + MOVOU 16(SI), X15 + PXOR X15, X3 + MOVOU X3, 16(DI) + MOVOU 32(SI), X15 + PXOR X15, X6 + MOVOU X6, 32(DI) + MOVOU 48(SI), X15 + PXOR X15, X9 + MOVOU X9, 48(DI) + MOVOU 64(SI), X9 + PXOR X9, X1 + MOVOU X1, 64(DI) + MOVOU 80(SI), X9 + PXOR X9, X4 + MOVOU X4, 80(DI) + MOVOU 96(SI), X9 + PXOR X9, X7 + MOVOU X7, 96(DI) + MOVOU 112(SI), X9 + PXOR X9, X10 + MOVOU X10, 112(DI) + MOVOU 128(SI), X9 + PXOR X9, X2 + MOVOU X2, 128(DI) + MOVOU 144(SI), X9 + PXOR X9, X5 + MOVOU X5, 144(DI) + MOVOU 160(SI), X9 + PXOR X9, X8 + MOVOU X8, 160(DI) + MOVOU 176(SI), X9 + PXOR X9, X11 + MOVOU X11, 176(DI) + MOVOU 192(SI), X9 + PXOR X9, X12 + MOVOU X12, 192(DI) + MOVOU 208(SI), X9 + PXOR X9, X13 + MOVOU X13, 208(DI) + MOVOU 224(SI), X9 + PXOR X9, X14 + MOVOU X14, 224(DI) + MOVOU 240(SI), X9 + PXOR 64(BP), X9 + MOVOU X9, 240(DI) + LEAQ 256(SI), SI + LEAQ 256(DI), DI + SUBQ $0x00000100, BX JMP openSSEMainLoop openSSEMainLoopDone: // Handle the various tail sizes efficiently - TESTQ inl, inl + TESTQ BX, BX JE openSSEFinalize - CMPQ inl, $64 + CMPQ BX, $0x40 JBE openSSETail64 - CMPQ inl, $128 + CMPQ BX, $0x80 JBE openSSETail128 - CMPQ inl, $192 + CMPQ BX, $0xc0 JBE openSSETail192 JMP openSSETail256 openSSEFinalize: // Hash in the PT, AAD lengths - ADDQ ad_len+80(FP), acc0; ADCQ src_len+56(FP), acc1; ADCQ $1, acc2 - polyMul + ADDQ ad_len+80(FP), R10 + ADCQ src_len+56(FP), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 // Final reduce - MOVQ acc0, t0 - MOVQ acc1, t1 - MOVQ acc2, t2 - SUBQ $-5, acc0 - SBBQ $-1, acc1 - SBBQ $3, acc2 - CMOVQCS t0, acc0 - CMOVQCS t1, acc1 - CMOVQCS t2, acc2 + MOVQ R10, R13 + MOVQ R11, R14 + MOVQ R12, R15 + SUBQ $-5, R10 + SBBQ $-1, R11 + SBBQ $0x03, R12 + CMOVQCS R13, R10 + CMOVQCS R14, R11 + CMOVQCS R15, R12 // Add in the "s" part of the key - ADDQ 0+sStore, acc0 - ADCQ 8+sStore, acc1 + ADDQ 16(BP), R10 + ADCQ 24(BP), R11 // Finally, constant time compare to the tag at the end of the message XORQ AX, AX - MOVQ $1, DX - XORQ (0*8)(inp), acc0 - XORQ (1*8)(inp), acc1 - ORQ acc1, acc0 + MOVQ $0x00000001, DX + XORQ (SI), R10 + XORQ 8(SI), R11 + ORQ R11, R10 CMOVQEQ DX, AX // Return true iff tags are equal MOVB AX, ret+96(FP) RET -// ---------------------------------------------------------------------------- -// Special optimization for buffers smaller than 129 bytes openSSE128: - // For up to 128 bytes of ciphertext and 64 bytes for the poly key, we require to process three blocks - MOVOU ·chacha20Constants<>(SB), A0; MOVOU (1*16)(keyp), B0; MOVOU (2*16)(keyp), C0; MOVOU (3*16)(keyp), D0 - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 - MOVO B0, T1; MOVO C0, T2; MOVO D1, T3 - MOVQ $10, itr2 + MOVOU ·chacha20Constants<>+0(SB), X0 + MOVOU 16(R8), X3 + MOVOU 32(R8), X6 + MOVOU 48(R8), X9 + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X3, X13 + MOVO X6, X14 + MOVO X10, X15 + MOVQ $0x0000000a, R9 openSSE128InnerCipherLoop: - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Left; shiftB1Left; shiftB2Left - shiftC0Left; shiftC1Left; shiftC2Left - shiftD0Left; shiftD1Left; shiftD2Left - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Right; shiftB1Right; shiftB2Right - shiftC0Right; shiftC1Right; shiftC2Right - shiftD0Right; shiftD1Right; shiftD2Right - DECQ itr2 - JNE openSSE128InnerCipherLoop + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + DECQ R9 + JNE openSSE128InnerCipherLoop // A0|B0 hold the Poly1305 32-byte key, C0,D0 can be discarded - PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1; PADDL ·chacha20Constants<>(SB), A2 - PADDL T1, B0; PADDL T1, B1; PADDL T1, B2 - PADDL T2, C1; PADDL T2, C2 - PADDL T3, D1; PADDL ·sseIncMask<>(SB), T3; PADDL T3, D2 + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL ·chacha20Constants<>+0(SB), X2 + PADDL X13, X3 + PADDL X13, X4 + PADDL X13, X5 + PADDL X14, X7 + PADDL X14, X8 + PADDL X15, X10 + PADDL ·sseIncMask<>+0(SB), X15 + PADDL X15, X11 // Clamp and store the key - PAND ·polyClampMask<>(SB), A0 - MOVOU A0, rStore; MOVOU B0, sStore + PAND ·polyClampMask<>+0(SB), X0 + MOVOU X0, (BP) + MOVOU X3, 16(BP) // Hash - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) openSSE128Open: - CMPQ inl, $16 + CMPQ BX, $0x10 JB openSSETail16 - SUBQ $16, inl + SUBQ $0x10, BX // Load for hashing - polyAdd(0(inp)) + ADDQ (SI), R10 + ADCQ 8(SI), R11 + ADCQ $0x01, R12 // Load for decryption - MOVOU (inp), T0; PXOR T0, A1; MOVOU A1, (oup) - LEAQ (1*16)(inp), inp - LEAQ (1*16)(oup), oup - polyMul + MOVOU (SI), X12 + PXOR X12, X1 + MOVOU X1, (DI) + LEAQ 16(SI), SI + LEAQ 16(DI), DI + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 // Shift the stream "left" - MOVO B1, A1 - MOVO C1, B1 - MOVO D1, C1 - MOVO A2, D1 - MOVO B2, A2 - MOVO C2, B2 - MOVO D2, C2 + MOVO X4, X1 + MOVO X7, X4 + MOVO X10, X7 + MOVO X2, X10 + MOVO X5, X2 + MOVO X8, X5 + MOVO X11, X8 JMP openSSE128Open openSSETail16: - TESTQ inl, inl + TESTQ BX, BX JE openSSEFinalize // We can safely load the CT from the end, because it is padded with the MAC - MOVQ inl, itr2 - SHLQ $4, itr2 - LEAQ ·andMask<>(SB), t0 - MOVOU (inp), T0 - ADDQ inl, inp - PAND -16(t0)(itr2*1), T0 - MOVO T0, 0+tmpStore - MOVQ T0, t0 - MOVQ 8+tmpStore, t1 - PXOR A1, T0 + MOVQ BX, R9 + SHLQ $0x04, R9 + LEAQ ·andMask<>+0(SB), R13 + MOVOU (SI), X12 + ADDQ BX, SI + PAND -16(R13)(R9*1), X12 + MOVO X12, 64(BP) + MOVQ X12, R13 + MOVQ 72(BP), R14 + PXOR X1, X12 // We can only store one byte at a time, since plaintext can be shorter than 16 bytes openSSETail16Store: - MOVQ T0, t3 - MOVB t3, (oup) - PSRLDQ $1, T0 - INCQ oup - DECQ inl + MOVQ X12, R8 + MOVB R8, (DI) + PSRLDQ $0x01, X12 + INCQ DI + DECQ BX JNE openSSETail16Store - ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $1, acc2 - polyMul + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 JMP openSSEFinalize -// ---------------------------------------------------------------------------- -// Special optimization for the last 64 bytes of ciphertext openSSETail64: - // Need to decrypt up to 64 bytes - prepare single block - MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr0Store - XORQ itr2, itr2 - MOVQ inl, itr1 - CMPQ itr1, $16 - JB openSSETail64LoopB + MOVO ·chacha20Constants<>+0(SB), X0 + MOVO 32(BP), X3 + MOVO 48(BP), X6 + MOVO 128(BP), X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X9, 80(BP) + XORQ R9, R9 + MOVQ BX, CX + CMPQ CX, $0x10 + JB openSSETail64LoopB openSSETail64LoopA: - // Perform ChaCha rounds, while hashing the remaining input - polyAdd(0(inp)(itr2*1)) - polyMul - SUBQ $16, itr1 + ADDQ (SI)(R9*1), R10 + ADCQ 8(SI)(R9*1), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + SUBQ $0x10, CX openSSETail64LoopB: - ADDQ $16, itr2 - chachaQR(A0, B0, C0, D0, T0) - shiftB0Left; shiftC0Left; shiftD0Left - chachaQR(A0, B0, C0, D0, T0) - shiftB0Right; shiftC0Right; shiftD0Right - - CMPQ itr1, $16 - JAE openSSETail64LoopA - - CMPQ itr2, $160 - JNE openSSETail64LoopB - - PADDL ·chacha20Constants<>(SB), A0; PADDL state1Store, B0; PADDL state2Store, C0; PADDL ctr0Store, D0 + ADDQ $0x10, R9 + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + CMPQ CX, $0x10 + JAE openSSETail64LoopA + CMPQ R9, $0xa0 + JNE openSSETail64LoopB + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL 32(BP), X3 + PADDL 48(BP), X6 + PADDL 80(BP), X9 openSSETail64DecLoop: - CMPQ inl, $16 + CMPQ BX, $0x10 JB openSSETail64DecLoopDone - SUBQ $16, inl - MOVOU (inp), T0 - PXOR T0, A0 - MOVOU A0, (oup) - LEAQ 16(inp), inp - LEAQ 16(oup), oup - MOVO B0, A0 - MOVO C0, B0 - MOVO D0, C0 + SUBQ $0x10, BX + MOVOU (SI), X12 + PXOR X12, X0 + MOVOU X0, (DI) + LEAQ 16(SI), SI + LEAQ 16(DI), DI + MOVO X3, X0 + MOVO X6, X3 + MOVO X9, X6 JMP openSSETail64DecLoop openSSETail64DecLoopDone: - MOVO A0, A1 + MOVO X0, X1 JMP openSSETail16 -// ---------------------------------------------------------------------------- -// Special optimization for the last 128 bytes of ciphertext openSSETail128: - // Need to decrypt up to 128 bytes - prepare two blocks - MOVO ·chacha20Constants<>(SB), A1; MOVO state1Store, B1; MOVO state2Store, C1; MOVO ctr3Store, D1; PADDL ·sseIncMask<>(SB), D1; MOVO D1, ctr0Store - MOVO A1, A0; MOVO B1, B0; MOVO C1, C0; MOVO D1, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr1Store - XORQ itr2, itr2 - MOVQ inl, itr1 - ANDQ $-16, itr1 + MOVO ·chacha20Constants<>+0(SB), X1 + MOVO 32(BP), X4 + MOVO 48(BP), X7 + MOVO 128(BP), X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X10, 80(BP) + MOVO X1, X0 + MOVO X4, X3 + MOVO X7, X6 + MOVO X10, X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X9, 96(BP) + XORQ R9, R9 + MOVQ BX, CX + ANDQ $-16, CX openSSETail128LoopA: - // Perform ChaCha rounds, while hashing the remaining input - polyAdd(0(inp)(itr2*1)) - polyMul + ADDQ (SI)(R9*1), R10 + ADCQ 8(SI)(R9*1), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 openSSETail128LoopB: - ADDQ $16, itr2 - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0) - shiftB0Left; shiftC0Left; shiftD0Left - shiftB1Left; shiftC1Left; shiftD1Left - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0) - shiftB0Right; shiftC0Right; shiftD0Right - shiftB1Right; shiftC1Right; shiftD1Right + ADDQ $0x10, R9 + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + CMPQ R9, CX + JB openSSETail128LoopA + CMPQ R9, $0xa0 + JNE openSSETail128LoopB + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL 32(BP), X3 + PADDL 32(BP), X4 + PADDL 48(BP), X6 + PADDL 48(BP), X7 + PADDL 96(BP), X9 + PADDL 80(BP), X10 + MOVOU (SI), X12 + MOVOU 16(SI), X13 + MOVOU 32(SI), X14 + MOVOU 48(SI), X15 + PXOR X12, X1 + PXOR X13, X4 + PXOR X14, X7 + PXOR X15, X10 + MOVOU X1, (DI) + MOVOU X4, 16(DI) + MOVOU X7, 32(DI) + MOVOU X10, 48(DI) + SUBQ $0x40, BX + LEAQ 64(SI), SI + LEAQ 64(DI), DI + JMP openSSETail64DecLoop - CMPQ itr2, itr1 - JB openSSETail128LoopA - - CMPQ itr2, $160 - JNE openSSETail128LoopB - - PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1 - PADDL state1Store, B0; PADDL state1Store, B1 - PADDL state2Store, C0; PADDL state2Store, C1 - PADDL ctr1Store, D0; PADDL ctr0Store, D1 - - MOVOU (0*16)(inp), T0; MOVOU (1*16)(inp), T1; MOVOU (2*16)(inp), T2; MOVOU (3*16)(inp), T3 - PXOR T0, A1; PXOR T1, B1; PXOR T2, C1; PXOR T3, D1 - MOVOU A1, (0*16)(oup); MOVOU B1, (1*16)(oup); MOVOU C1, (2*16)(oup); MOVOU D1, (3*16)(oup) - - SUBQ $64, inl - LEAQ 64(inp), inp - LEAQ 64(oup), oup - JMP openSSETail64DecLoop - -// ---------------------------------------------------------------------------- -// Special optimization for the last 192 bytes of ciphertext openSSETail192: - // Need to decrypt up to 192 bytes - prepare three blocks - MOVO ·chacha20Constants<>(SB), A2; MOVO state1Store, B2; MOVO state2Store, C2; MOVO ctr3Store, D2; PADDL ·sseIncMask<>(SB), D2; MOVO D2, ctr0Store - MOVO A2, A1; MOVO B2, B1; MOVO C2, C1; MOVO D2, D1; PADDL ·sseIncMask<>(SB), D1; MOVO D1, ctr1Store - MOVO A1, A0; MOVO B1, B0; MOVO C1, C0; MOVO D1, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr2Store - - MOVQ inl, itr1 - MOVQ $160, itr2 - CMPQ itr1, $160 - CMOVQGT itr2, itr1 - ANDQ $-16, itr1 - XORQ itr2, itr2 + MOVO ·chacha20Constants<>+0(SB), X2 + MOVO 32(BP), X5 + MOVO 48(BP), X8 + MOVO 128(BP), X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X11, 80(BP) + MOVO X2, X1 + MOVO X5, X4 + MOVO X8, X7 + MOVO X11, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X10, 96(BP) + MOVO X1, X0 + MOVO X4, X3 + MOVO X7, X6 + MOVO X10, X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X9, 112(BP) + MOVQ BX, CX + MOVQ $0x000000a0, R9 + CMPQ CX, $0xa0 + CMOVQGT R9, CX + ANDQ $-16, CX + XORQ R9, R9 openSSLTail192LoopA: - // Perform ChaCha rounds, while hashing the remaining input - polyAdd(0(inp)(itr2*1)) - polyMul + ADDQ (SI)(R9*1), R10 + ADCQ 8(SI)(R9*1), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 openSSLTail192LoopB: - ADDQ $16, itr2 - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Left; shiftC0Left; shiftD0Left - shiftB1Left; shiftC1Left; shiftD1Left - shiftB2Left; shiftC2Left; shiftD2Left - - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Right; shiftC0Right; shiftD0Right - shiftB1Right; shiftC1Right; shiftD1Right - shiftB2Right; shiftC2Right; shiftD2Right - - CMPQ itr2, itr1 - JB openSSLTail192LoopA - - CMPQ itr2, $160 - JNE openSSLTail192LoopB - - CMPQ inl, $176 - JB openSSLTail192Store - - polyAdd(160(inp)) - polyMul - - CMPQ inl, $192 - JB openSSLTail192Store - - polyAdd(176(inp)) - polyMul + ADDQ $0x10, R9 + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + CMPQ R9, CX + JB openSSLTail192LoopA + CMPQ R9, $0xa0 + JNE openSSLTail192LoopB + CMPQ BX, $0xb0 + JB openSSLTail192Store + ADDQ 160(SI), R10 + ADCQ 168(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + CMPQ BX, $0xc0 + JB openSSLTail192Store + ADDQ 176(SI), R10 + ADCQ 184(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 openSSLTail192Store: - PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1; PADDL ·chacha20Constants<>(SB), A2 - PADDL state1Store, B0; PADDL state1Store, B1; PADDL state1Store, B2 - PADDL state2Store, C0; PADDL state2Store, C1; PADDL state2Store, C2 - PADDL ctr2Store, D0; PADDL ctr1Store, D1; PADDL ctr0Store, D2 + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL ·chacha20Constants<>+0(SB), X2 + PADDL 32(BP), X3 + PADDL 32(BP), X4 + PADDL 32(BP), X5 + PADDL 48(BP), X6 + PADDL 48(BP), X7 + PADDL 48(BP), X8 + PADDL 112(BP), X9 + PADDL 96(BP), X10 + PADDL 80(BP), X11 + MOVOU (SI), X12 + MOVOU 16(SI), X13 + MOVOU 32(SI), X14 + MOVOU 48(SI), X15 + PXOR X12, X2 + PXOR X13, X5 + PXOR X14, X8 + PXOR X15, X11 + MOVOU X2, (DI) + MOVOU X5, 16(DI) + MOVOU X8, 32(DI) + MOVOU X11, 48(DI) + MOVOU 64(SI), X12 + MOVOU 80(SI), X13 + MOVOU 96(SI), X14 + MOVOU 112(SI), X15 + PXOR X12, X1 + PXOR X13, X4 + PXOR X14, X7 + PXOR X15, X10 + MOVOU X1, 64(DI) + MOVOU X4, 80(DI) + MOVOU X7, 96(DI) + MOVOU X10, 112(DI) + SUBQ $0x80, BX + LEAQ 128(SI), SI + LEAQ 128(DI), DI + JMP openSSETail64DecLoop - MOVOU (0*16)(inp), T0; MOVOU (1*16)(inp), T1; MOVOU (2*16)(inp), T2; MOVOU (3*16)(inp), T3 - PXOR T0, A2; PXOR T1, B2; PXOR T2, C2; PXOR T3, D2 - MOVOU A2, (0*16)(oup); MOVOU B2, (1*16)(oup); MOVOU C2, (2*16)(oup); MOVOU D2, (3*16)(oup) - - MOVOU (4*16)(inp), T0; MOVOU (5*16)(inp), T1; MOVOU (6*16)(inp), T2; MOVOU (7*16)(inp), T3 - PXOR T0, A1; PXOR T1, B1; PXOR T2, C1; PXOR T3, D1 - MOVOU A1, (4*16)(oup); MOVOU B1, (5*16)(oup); MOVOU C1, (6*16)(oup); MOVOU D1, (7*16)(oup) - - SUBQ $128, inl - LEAQ 128(inp), inp - LEAQ 128(oup), oup - JMP openSSETail64DecLoop - -// ---------------------------------------------------------------------------- -// Special optimization for the last 256 bytes of ciphertext openSSETail256: - // Need to decrypt up to 256 bytes - prepare four blocks - MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0 - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 - MOVO A2, A3; MOVO B2, B3; MOVO C2, C3; MOVO D2, D3; PADDL ·sseIncMask<>(SB), D3 + MOVO ·chacha20Constants<>+0(SB), X0 + MOVO 32(BP), X3 + MOVO 48(BP), X6 + MOVO 128(BP), X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X2, X12 + MOVO X5, X13 + MOVO X8, X14 + MOVO X11, X15 + PADDL ·sseIncMask<>+0(SB), X15 // Store counters - MOVO D0, ctr0Store; MOVO D1, ctr1Store; MOVO D2, ctr2Store; MOVO D3, ctr3Store - XORQ itr2, itr2 + MOVO X9, 80(BP) + MOVO X10, 96(BP) + MOVO X11, 112(BP) + MOVO X15, 128(BP) + XORQ R9, R9 openSSETail256Loop: - // This loop inteleaves 8 ChaCha quarter rounds with 1 poly multiplication - polyAdd(0(inp)(itr2*1)) - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - shiftB0Left; shiftB1Left; shiftB2Left; shiftB3Left - shiftC0Left; shiftC1Left; shiftC2Left; shiftC3Left - shiftD0Left; shiftD1Left; shiftD2Left; shiftD3Left - polyMulStage1 - polyMulStage2 - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - polyMulStage3 - polyMulReduceStage - shiftB0Right; shiftB1Right; shiftB2Right; shiftB3Right - shiftC0Right; shiftC1Right; shiftC2Right; shiftC3Right - shiftD0Right; shiftD1Right; shiftD2Right; shiftD3Right - ADDQ $2*8, itr2 - CMPQ itr2, $160 - JB openSSETail256Loop - MOVQ inl, itr1 - ANDQ $-16, itr1 + ADDQ (SI)(R9*1), R10 + ADCQ 8(SI)(R9*1), R11 + ADCQ $0x01, R12 + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x0c + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x04 + ADDQ $0x10, R9 + CMPQ R9, $0xa0 + JB openSSETail256Loop + MOVQ BX, CX + ANDQ $-16, CX openSSETail256HashLoop: - polyAdd(0(inp)(itr2*1)) - polyMul - ADDQ $2*8, itr2 - CMPQ itr2, itr1 - JB openSSETail256HashLoop + ADDQ (SI)(R9*1), R10 + ADCQ 8(SI)(R9*1), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + ADDQ $0x10, R9 + CMPQ R9, CX + JB openSSETail256HashLoop // Add in the state - PADDD ·chacha20Constants<>(SB), A0; PADDD ·chacha20Constants<>(SB), A1; PADDD ·chacha20Constants<>(SB), A2; PADDD ·chacha20Constants<>(SB), A3 - PADDD state1Store, B0; PADDD state1Store, B1; PADDD state1Store, B2; PADDD state1Store, B3 - PADDD state2Store, C0; PADDD state2Store, C1; PADDD state2Store, C2; PADDD state2Store, C3 - PADDD ctr0Store, D0; PADDD ctr1Store, D1; PADDD ctr2Store, D2; PADDD ctr3Store, D3 - MOVO D3, tmpStore + PADDD ·chacha20Constants<>+0(SB), X0 + PADDD ·chacha20Constants<>+0(SB), X1 + PADDD ·chacha20Constants<>+0(SB), X2 + PADDD ·chacha20Constants<>+0(SB), X12 + PADDD 32(BP), X3 + PADDD 32(BP), X4 + PADDD 32(BP), X5 + PADDD 32(BP), X13 + PADDD 48(BP), X6 + PADDD 48(BP), X7 + PADDD 48(BP), X8 + PADDD 48(BP), X14 + PADDD 80(BP), X9 + PADDD 96(BP), X10 + PADDD 112(BP), X11 + PADDD 128(BP), X15 + MOVO X15, 64(BP) // Load - xor - store - MOVOU (0*16)(inp), D3; PXOR D3, A0 - MOVOU (1*16)(inp), D3; PXOR D3, B0 - MOVOU (2*16)(inp), D3; PXOR D3, C0 - MOVOU (3*16)(inp), D3; PXOR D3, D0 - MOVOU A0, (0*16)(oup) - MOVOU B0, (1*16)(oup) - MOVOU C0, (2*16)(oup) - MOVOU D0, (3*16)(oup) - MOVOU (4*16)(inp), A0; MOVOU (5*16)(inp), B0; MOVOU (6*16)(inp), C0; MOVOU (7*16)(inp), D0 - PXOR A0, A1; PXOR B0, B1; PXOR C0, C1; PXOR D0, D1 - MOVOU A1, (4*16)(oup); MOVOU B1, (5*16)(oup); MOVOU C1, (6*16)(oup); MOVOU D1, (7*16)(oup) - MOVOU (8*16)(inp), A0; MOVOU (9*16)(inp), B0; MOVOU (10*16)(inp), C0; MOVOU (11*16)(inp), D0 - PXOR A0, A2; PXOR B0, B2; PXOR C0, C2; PXOR D0, D2 - MOVOU A2, (8*16)(oup); MOVOU B2, (9*16)(oup); MOVOU C2, (10*16)(oup); MOVOU D2, (11*16)(oup) - LEAQ 192(inp), inp - LEAQ 192(oup), oup - SUBQ $192, inl - MOVO A3, A0 - MOVO B3, B0 - MOVO C3, C0 - MOVO tmpStore, D0 + MOVOU (SI), X15 + PXOR X15, X0 + MOVOU 16(SI), X15 + PXOR X15, X3 + MOVOU 32(SI), X15 + PXOR X15, X6 + MOVOU 48(SI), X15 + PXOR X15, X9 + MOVOU X0, (DI) + MOVOU X3, 16(DI) + MOVOU X6, 32(DI) + MOVOU X9, 48(DI) + MOVOU 64(SI), X0 + MOVOU 80(SI), X3 + MOVOU 96(SI), X6 + MOVOU 112(SI), X9 + PXOR X0, X1 + PXOR X3, X4 + PXOR X6, X7 + PXOR X9, X10 + MOVOU X1, 64(DI) + MOVOU X4, 80(DI) + MOVOU X7, 96(DI) + MOVOU X10, 112(DI) + MOVOU 128(SI), X0 + MOVOU 144(SI), X3 + MOVOU 160(SI), X6 + MOVOU 176(SI), X9 + PXOR X0, X2 + PXOR X3, X5 + PXOR X6, X8 + PXOR X9, X11 + MOVOU X2, 128(DI) + MOVOU X5, 144(DI) + MOVOU X8, 160(DI) + MOVOU X11, 176(DI) + LEAQ 192(SI), SI + LEAQ 192(DI), DI + SUBQ $0xc0, BX + MOVO X12, X0 + MOVO X13, X3 + MOVO X14, X6 + MOVO 64(BP), X9 + JMP openSSETail64DecLoop - JMP openSSETail64DecLoop - -// ---------------------------------------------------------------------------- -// ------------------------- AVX2 Code ---------------------------------------- chacha20Poly1305Open_AVX2: VZEROUPPER - VMOVDQU ·chacha20Constants<>(SB), AA0 - BYTE $0xc4; BYTE $0x42; BYTE $0x7d; BYTE $0x5a; BYTE $0x70; BYTE $0x10 // broadcasti128 16(r8), ymm14 - BYTE $0xc4; BYTE $0x42; BYTE $0x7d; BYTE $0x5a; BYTE $0x60; BYTE $0x20 // broadcasti128 32(r8), ymm12 - BYTE $0xc4; BYTE $0xc2; BYTE $0x7d; BYTE $0x5a; BYTE $0x60; BYTE $0x30 // broadcasti128 48(r8), ymm4 - VPADDD ·avx2InitMask<>(SB), DD0, DD0 + VMOVDQU ·chacha20Constants<>+0(SB), Y0 + BYTE $0xc4 + BYTE $0x42 + BYTE $0x7d + BYTE $0x5a + BYTE $0x70 + BYTE $0x10 + BYTE $0xc4 + BYTE $0x42 + BYTE $0x7d + BYTE $0x5a + BYTE $0x60 + BYTE $0x20 + BYTE $0xc4 + BYTE $0xc2 + BYTE $0x7d + BYTE $0x5a + BYTE $0x60 + BYTE $0x30 + VPADDD ·avx2InitMask<>+0(SB), Y4, Y4 // Special optimization, for very short buffers - CMPQ inl, $192 + CMPQ BX, $0xc0 JBE openAVX2192 - CMPQ inl, $320 + CMPQ BX, $0x00000140 JBE openAVX2320 // For the general key prepare the key first - as a byproduct we have 64 bytes of cipher stream - VMOVDQA BB0, state1StoreAVX2 - VMOVDQA CC0, state2StoreAVX2 - VMOVDQA DD0, ctr3StoreAVX2 - MOVQ $10, itr2 + VMOVDQA Y14, 32(BP) + VMOVDQA Y12, 64(BP) + VMOVDQA Y4, 192(BP) + MOVQ $0x0000000a, R9 openAVX2PreparePolyKey: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $12, DD0, DD0, DD0 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $4, DD0, DD0, DD0 - DECQ itr2 - JNE openAVX2PreparePolyKey - - VPADDD ·chacha20Constants<>(SB), AA0, AA0 - VPADDD state1StoreAVX2, BB0, BB0 - VPADDD state2StoreAVX2, CC0, CC0 - VPADDD ctr3StoreAVX2, DD0, DD0 - - VPERM2I128 $0x02, AA0, BB0, TT0 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x04, Y4, Y4, Y4 + DECQ R9 + JNE openAVX2PreparePolyKey + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD 32(BP), Y14, Y14 + VPADDD 64(BP), Y12, Y12 + VPADDD 192(BP), Y4, Y4 + VPERM2I128 $0x02, Y0, Y14, Y3 // Clamp and store poly key - VPAND ·polyClampMask<>(SB), TT0, TT0 - VMOVDQA TT0, rsStoreAVX2 + VPAND ·polyClampMask<>+0(SB), Y3, Y3 + VMOVDQA Y3, (BP) // Stream for the first 64 bytes - VPERM2I128 $0x13, AA0, BB0, AA0 - VPERM2I128 $0x13, CC0, DD0, BB0 + VPERM2I128 $0x13, Y0, Y14, Y0 + VPERM2I128 $0x13, Y12, Y4, Y14 // Hash AD + first 64 bytes - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) - XORQ itr1, itr1 + XORQ CX, CX openAVX2InitialHash64: - polyAdd(0(inp)(itr1*1)) - polyMulAVX2 - ADDQ $16, itr1 - CMPQ itr1, $64 - JNE openAVX2InitialHash64 + ADDQ (SI)(CX*1), R10 + ADCQ 8(SI)(CX*1), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + ADDQ $0x10, CX + CMPQ CX, $0x40 + JNE openAVX2InitialHash64 // Decrypt the first 64 bytes - VPXOR (0*32)(inp), AA0, AA0 - VPXOR (1*32)(inp), BB0, BB0 - VMOVDQU AA0, (0*32)(oup) - VMOVDQU BB0, (1*32)(oup) - LEAQ (2*32)(inp), inp - LEAQ (2*32)(oup), oup - SUBQ $64, inl + VPXOR (SI), Y0, Y0 + VPXOR 32(SI), Y14, Y14 + VMOVDQU Y0, (DI) + VMOVDQU Y14, 32(DI) + LEAQ 64(SI), SI + LEAQ 64(DI), DI + SUBQ $0x40, BX openAVX2MainLoop: - CMPQ inl, $512 + CMPQ BX, $0x00000200 JB openAVX2MainLoopDone // Load state, increment counter blocks, store the incremented counters - VMOVDQU ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 - VMOVDQA ctr3StoreAVX2, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 - VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 - XORQ itr1, itr1 + VMOVDQU ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA Y0, Y7 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA Y14, Y11 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA Y12, Y15 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 + VMOVDQA Y4, 96(BP) + VMOVDQA Y1, 128(BP) + VMOVDQA Y2, 160(BP) + VMOVDQA Y3, 192(BP) + XORQ CX, CX openAVX2InternalLoop: - // Lets just say this spaghetti loop interleaves 2 quarter rounds with 3 poly multiplications - // Effectively per 512 bytes of stream we hash 480 bytes of ciphertext - polyAdd(0*8(inp)(itr1*1)) - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - polyMulStage1_AVX2 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - polyMulStage2_AVX2 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - polyMulStage3_AVX2 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulReduceStage - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - polyAdd(2*8(inp)(itr1*1)) - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - polyMulStage1_AVX2 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulStage2_AVX2 - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $4, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2; VPALIGNR $12, DD3, DD3, DD3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - polyMulStage3_AVX2 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - polyMulReduceStage - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - polyAdd(4*8(inp)(itr1*1)) - LEAQ (6*8)(itr1), itr1 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulStage1_AVX2 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - polyMulStage2_AVX2 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - polyMulStage3_AVX2 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulReduceStage - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $12, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2; VPALIGNR $4, DD3, DD3, DD3 - CMPQ itr1, $480 + ADDQ (SI)(CX*1), R10 + ADCQ 8(SI)(CX*1), R11 + ADCQ $0x01, R12 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + ADDQ 16(SI)(CX*1), R10 + ADCQ 24(SI)(CX*1), R11 + ADCQ $0x01, R12 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x04, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPALIGNR $0x0c, Y3, Y3, Y3 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + ADDQ 32(SI)(CX*1), R10 + ADCQ 40(SI)(CX*1), R11 + ADCQ $0x01, R12 + LEAQ 48(CX), CX + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x0c, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + VPALIGNR $0x04, Y3, Y3, Y3 + CMPQ CX, $0x000001e0 JNE openAVX2InternalLoop - - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 - VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 - VMOVDQA CC3, tmpStoreAVX2 + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 32(BP), Y11, Y11 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD 64(BP), Y15, Y15 + VPADDD 96(BP), Y4, Y4 + VPADDD 128(BP), Y1, Y1 + VPADDD 160(BP), Y2, Y2 + VPADDD 192(BP), Y3, Y3 + VMOVDQA Y15, 224(BP) // We only hashed 480 of the 512 bytes available - hash the remaining 32 here - polyAdd(480(inp)) - polyMulAVX2 - VPERM2I128 $0x02, AA0, BB0, CC3; VPERM2I128 $0x13, AA0, BB0, BB0; VPERM2I128 $0x02, CC0, DD0, AA0; VPERM2I128 $0x13, CC0, DD0, CC0 - VPXOR (0*32)(inp), CC3, CC3; VPXOR (1*32)(inp), AA0, AA0; VPXOR (2*32)(inp), BB0, BB0; VPXOR (3*32)(inp), CC0, CC0 - VMOVDQU CC3, (0*32)(oup); VMOVDQU AA0, (1*32)(oup); VMOVDQU BB0, (2*32)(oup); VMOVDQU CC0, (3*32)(oup) - VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 - VPXOR (4*32)(inp), AA0, AA0; VPXOR (5*32)(inp), BB0, BB0; VPXOR (6*32)(inp), CC0, CC0; VPXOR (7*32)(inp), DD0, DD0 - VMOVDQU AA0, (4*32)(oup); VMOVDQU BB0, (5*32)(oup); VMOVDQU CC0, (6*32)(oup); VMOVDQU DD0, (7*32)(oup) + ADDQ 480(SI), R10 + ADCQ 488(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPERM2I128 $0x02, Y0, Y14, Y15 + VPERM2I128 $0x13, Y0, Y14, Y14 + VPERM2I128 $0x02, Y12, Y4, Y0 + VPERM2I128 $0x13, Y12, Y4, Y12 + VPXOR (SI), Y15, Y15 + VPXOR 32(SI), Y0, Y0 + VPXOR 64(SI), Y14, Y14 + VPXOR 96(SI), Y12, Y12 + VMOVDQU Y15, (DI) + VMOVDQU Y0, 32(DI) + VMOVDQU Y14, 64(DI) + VMOVDQU Y12, 96(DI) + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + VPXOR 128(SI), Y0, Y0 + VPXOR 160(SI), Y14, Y14 + VPXOR 192(SI), Y12, Y12 + VPXOR 224(SI), Y4, Y4 + VMOVDQU Y0, 128(DI) + VMOVDQU Y14, 160(DI) + VMOVDQU Y12, 192(DI) + VMOVDQU Y4, 224(DI) // and here - polyAdd(496(inp)) - polyMulAVX2 - VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 - VPXOR (8*32)(inp), AA0, AA0; VPXOR (9*32)(inp), BB0, BB0; VPXOR (10*32)(inp), CC0, CC0; VPXOR (11*32)(inp), DD0, DD0 - VMOVDQU AA0, (8*32)(oup); VMOVDQU BB0, (9*32)(oup); VMOVDQU CC0, (10*32)(oup); VMOVDQU DD0, (11*32)(oup) - VPERM2I128 $0x02, AA3, BB3, AA0; VPERM2I128 $0x02, tmpStoreAVX2, DD3, BB0; VPERM2I128 $0x13, AA3, BB3, CC0; VPERM2I128 $0x13, tmpStoreAVX2, DD3, DD0 - VPXOR (12*32)(inp), AA0, AA0; VPXOR (13*32)(inp), BB0, BB0; VPXOR (14*32)(inp), CC0, CC0; VPXOR (15*32)(inp), DD0, DD0 - VMOVDQU AA0, (12*32)(oup); VMOVDQU BB0, (13*32)(oup); VMOVDQU CC0, (14*32)(oup); VMOVDQU DD0, (15*32)(oup) - LEAQ (32*16)(inp), inp - LEAQ (32*16)(oup), oup - SUBQ $(32*16), inl + ADDQ 496(SI), R10 + ADCQ 504(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + VPXOR 256(SI), Y0, Y0 + VPXOR 288(SI), Y14, Y14 + VPXOR 320(SI), Y12, Y12 + VPXOR 352(SI), Y4, Y4 + VMOVDQU Y0, 256(DI) + VMOVDQU Y14, 288(DI) + VMOVDQU Y12, 320(DI) + VMOVDQU Y4, 352(DI) + VPERM2I128 $0x02, Y7, Y11, Y0 + VPERM2I128 $0x02, 224(BP), Y3, Y14 + VPERM2I128 $0x13, Y7, Y11, Y12 + VPERM2I128 $0x13, 224(BP), Y3, Y4 + VPXOR 384(SI), Y0, Y0 + VPXOR 416(SI), Y14, Y14 + VPXOR 448(SI), Y12, Y12 + VPXOR 480(SI), Y4, Y4 + VMOVDQU Y0, 384(DI) + VMOVDQU Y14, 416(DI) + VMOVDQU Y12, 448(DI) + VMOVDQU Y4, 480(DI) + LEAQ 512(SI), SI + LEAQ 512(DI), DI + SUBQ $0x00000200, BX JMP openAVX2MainLoop openAVX2MainLoopDone: // Handle the various tail sizes efficiently - TESTQ inl, inl + TESTQ BX, BX JE openSSEFinalize - CMPQ inl, $128 + CMPQ BX, $0x80 JBE openAVX2Tail128 - CMPQ inl, $256 + CMPQ BX, $0x00000100 JBE openAVX2Tail256 - CMPQ inl, $384 + CMPQ BX, $0x00000180 JBE openAVX2Tail384 JMP openAVX2Tail512 -// ---------------------------------------------------------------------------- -// Special optimization for buffers smaller than 193 bytes openAVX2192: - // For up to 192 bytes of ciphertext and 64 bytes for the poly key, we process four blocks - VMOVDQA AA0, AA1 - VMOVDQA BB0, BB1 - VMOVDQA CC0, CC1 - VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VMOVDQA AA0, AA2 - VMOVDQA BB0, BB2 - VMOVDQA CC0, CC2 - VMOVDQA DD0, DD2 - VMOVDQA DD1, TT3 - MOVQ $10, itr2 + VMOVDQA Y0, Y5 + VMOVDQA Y14, Y9 + VMOVDQA Y12, Y13 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y0, Y6 + VMOVDQA Y14, Y10 + VMOVDQA Y12, Y8 + VMOVDQA Y4, Y2 + VMOVDQA Y1, Y15 + MOVQ $0x0000000a, R9 openAVX2192InnerCipherLoop: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1 - DECQ itr2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + DECQ R9 JNE openAVX2192InnerCipherLoop - VPADDD AA2, AA0, AA0; VPADDD AA2, AA1, AA1 - VPADDD BB2, BB0, BB0; VPADDD BB2, BB1, BB1 - VPADDD CC2, CC0, CC0; VPADDD CC2, CC1, CC1 - VPADDD DD2, DD0, DD0; VPADDD TT3, DD1, DD1 - VPERM2I128 $0x02, AA0, BB0, TT0 + VPADDD Y6, Y0, Y0 + VPADDD Y6, Y5, Y5 + VPADDD Y10, Y14, Y14 + VPADDD Y10, Y9, Y9 + VPADDD Y8, Y12, Y12 + VPADDD Y8, Y13, Y13 + VPADDD Y2, Y4, Y4 + VPADDD Y15, Y1, Y1 + VPERM2I128 $0x02, Y0, Y14, Y3 // Clamp and store poly key - VPAND ·polyClampMask<>(SB), TT0, TT0 - VMOVDQA TT0, rsStoreAVX2 + VPAND ·polyClampMask<>+0(SB), Y3, Y3 + VMOVDQA Y3, (BP) // Stream for up to 192 bytes - VPERM2I128 $0x13, AA0, BB0, AA0 - VPERM2I128 $0x13, CC0, DD0, BB0 - VPERM2I128 $0x02, AA1, BB1, CC0 - VPERM2I128 $0x02, CC1, DD1, DD0 - VPERM2I128 $0x13, AA1, BB1, AA1 - VPERM2I128 $0x13, CC1, DD1, BB1 + VPERM2I128 $0x13, Y0, Y14, Y0 + VPERM2I128 $0x13, Y12, Y4, Y14 + VPERM2I128 $0x02, Y5, Y9, Y12 + VPERM2I128 $0x02, Y13, Y1, Y4 + VPERM2I128 $0x13, Y5, Y9, Y5 + VPERM2I128 $0x13, Y13, Y1, Y9 openAVX2ShortOpen: // Hash - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) openAVX2ShortOpenLoop: - CMPQ inl, $32 + CMPQ BX, $0x20 JB openAVX2ShortTail32 - SUBQ $32, inl + SUBQ $0x20, BX // Load for hashing - polyAdd(0*8(inp)) - polyMulAVX2 - polyAdd(2*8(inp)) - polyMulAVX2 + ADDQ (SI), R10 + ADCQ 8(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + ADDQ 16(SI), R10 + ADCQ 24(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 // Load for decryption - VPXOR (inp), AA0, AA0 - VMOVDQU AA0, (oup) - LEAQ (1*32)(inp), inp - LEAQ (1*32)(oup), oup + VPXOR (SI), Y0, Y0 + VMOVDQU Y0, (DI) + LEAQ 32(SI), SI + LEAQ 32(DI), DI // Shift stream left - VMOVDQA BB0, AA0 - VMOVDQA CC0, BB0 - VMOVDQA DD0, CC0 - VMOVDQA AA1, DD0 - VMOVDQA BB1, AA1 - VMOVDQA CC1, BB1 - VMOVDQA DD1, CC1 - VMOVDQA AA2, DD1 - VMOVDQA BB2, AA2 + VMOVDQA Y14, Y0 + VMOVDQA Y12, Y14 + VMOVDQA Y4, Y12 + VMOVDQA Y5, Y4 + VMOVDQA Y9, Y5 + VMOVDQA Y13, Y9 + VMOVDQA Y1, Y13 + VMOVDQA Y6, Y1 + VMOVDQA Y10, Y6 JMP openAVX2ShortOpenLoop openAVX2ShortTail32: - CMPQ inl, $16 - VMOVDQA A0, A1 + CMPQ BX, $0x10 + VMOVDQA X0, X1 JB openAVX2ShortDone - - SUBQ $16, inl + SUBQ $0x10, BX // Load for hashing - polyAdd(0*8(inp)) - polyMulAVX2 + ADDQ (SI), R10 + ADCQ 8(SI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 // Load for decryption - VPXOR (inp), A0, T0 - VMOVDQU T0, (oup) - LEAQ (1*16)(inp), inp - LEAQ (1*16)(oup), oup - VPERM2I128 $0x11, AA0, AA0, AA0 - VMOVDQA A0, A1 + VPXOR (SI), X0, X12 + VMOVDQU X12, (DI) + LEAQ 16(SI), SI + LEAQ 16(DI), DI + VPERM2I128 $0x11, Y0, Y0, Y0 + VMOVDQA X0, X1 openAVX2ShortDone: VZEROUPPER JMP openSSETail16 -// ---------------------------------------------------------------------------- -// Special optimization for buffers smaller than 321 bytes openAVX2320: - // For up to 320 bytes of ciphertext and 64 bytes for the poly key, we process six blocks - VMOVDQA AA0, AA1; VMOVDQA BB0, BB1; VMOVDQA CC0, CC1; VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VMOVDQA AA0, AA2; VMOVDQA BB0, BB2; VMOVDQA CC0, CC2; VPADDD ·avx2IncMask<>(SB), DD1, DD2 - VMOVDQA BB0, TT1; VMOVDQA CC0, TT2; VMOVDQA DD0, TT3 - MOVQ $10, itr2 + VMOVDQA Y0, Y5 + VMOVDQA Y14, Y9 + VMOVDQA Y12, Y13 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y0, Y6 + VMOVDQA Y14, Y10 + VMOVDQA Y12, Y8 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VMOVDQA Y14, Y7 + VMOVDQA Y12, Y11 + VMOVDQA Y4, Y15 + MOVQ $0x0000000a, R9 openAVX2320InnerCipherLoop: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2 - DECQ itr2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + DECQ R9 JNE openAVX2320InnerCipherLoop - - VMOVDQA ·chacha20Constants<>(SB), TT0 - VPADDD TT0, AA0, AA0; VPADDD TT0, AA1, AA1; VPADDD TT0, AA2, AA2 - VPADDD TT1, BB0, BB0; VPADDD TT1, BB1, BB1; VPADDD TT1, BB2, BB2 - VPADDD TT2, CC0, CC0; VPADDD TT2, CC1, CC1; VPADDD TT2, CC2, CC2 - VMOVDQA ·avx2IncMask<>(SB), TT0 - VPADDD TT3, DD0, DD0; VPADDD TT0, TT3, TT3 - VPADDD TT3, DD1, DD1; VPADDD TT0, TT3, TT3 - VPADDD TT3, DD2, DD2 + VMOVDQA ·chacha20Constants<>+0(SB), Y3 + VPADDD Y3, Y0, Y0 + VPADDD Y3, Y5, Y5 + VPADDD Y3, Y6, Y6 + VPADDD Y7, Y14, Y14 + VPADDD Y7, Y9, Y9 + VPADDD Y7, Y10, Y10 + VPADDD Y11, Y12, Y12 + VPADDD Y11, Y13, Y13 + VPADDD Y11, Y8, Y8 + VMOVDQA ·avx2IncMask<>+0(SB), Y3 + VPADDD Y15, Y4, Y4 + VPADDD Y3, Y15, Y15 + VPADDD Y15, Y1, Y1 + VPADDD Y3, Y15, Y15 + VPADDD Y15, Y2, Y2 // Clamp and store poly key - VPERM2I128 $0x02, AA0, BB0, TT0 - VPAND ·polyClampMask<>(SB), TT0, TT0 - VMOVDQA TT0, rsStoreAVX2 + VPERM2I128 $0x02, Y0, Y14, Y3 + VPAND ·polyClampMask<>+0(SB), Y3, Y3 + VMOVDQA Y3, (BP) // Stream for up to 320 bytes - VPERM2I128 $0x13, AA0, BB0, AA0 - VPERM2I128 $0x13, CC0, DD0, BB0 - VPERM2I128 $0x02, AA1, BB1, CC0 - VPERM2I128 $0x02, CC1, DD1, DD0 - VPERM2I128 $0x13, AA1, BB1, AA1 - VPERM2I128 $0x13, CC1, DD1, BB1 - VPERM2I128 $0x02, AA2, BB2, CC1 - VPERM2I128 $0x02, CC2, DD2, DD1 - VPERM2I128 $0x13, AA2, BB2, AA2 - VPERM2I128 $0x13, CC2, DD2, BB2 + VPERM2I128 $0x13, Y0, Y14, Y0 + VPERM2I128 $0x13, Y12, Y4, Y14 + VPERM2I128 $0x02, Y5, Y9, Y12 + VPERM2I128 $0x02, Y13, Y1, Y4 + VPERM2I128 $0x13, Y5, Y9, Y5 + VPERM2I128 $0x13, Y13, Y1, Y9 + VPERM2I128 $0x02, Y6, Y10, Y13 + VPERM2I128 $0x02, Y8, Y2, Y1 + VPERM2I128 $0x13, Y6, Y10, Y6 + VPERM2I128 $0x13, Y8, Y2, Y10 JMP openAVX2ShortOpen -// ---------------------------------------------------------------------------- -// Special optimization for the last 128 bytes of ciphertext openAVX2Tail128: // Need to decrypt up to 128 bytes - prepare two blocks - VMOVDQA ·chacha20Constants<>(SB), AA1 - VMOVDQA state1StoreAVX2, BB1 - VMOVDQA state2StoreAVX2, CC1 - VMOVDQA ctr3StoreAVX2, DD1 - VPADDD ·avx2IncMask<>(SB), DD1, DD1 - VMOVDQA DD1, DD0 - - XORQ itr2, itr2 - MOVQ inl, itr1 - ANDQ $-16, itr1 - TESTQ itr1, itr1 - JE openAVX2Tail128LoopB + VMOVDQA ·chacha20Constants<>+0(SB), Y5 + VMOVDQA 32(BP), Y9 + VMOVDQA 64(BP), Y13 + VMOVDQA 192(BP), Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y1 + VMOVDQA Y1, Y4 + XORQ R9, R9 + MOVQ BX, CX + ANDQ $-16, CX + TESTQ CX, CX + JE openAVX2Tail128LoopB openAVX2Tail128LoopA: - // Perform ChaCha rounds, while hashing the remaining input - polyAdd(0(inp)(itr2*1)) - polyMulAVX2 + ADDQ (SI)(R9*1), R10 + ADCQ 8(SI)(R9*1), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 openAVX2Tail128LoopB: - ADDQ $16, itr2 - chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $4, BB1, BB1, BB1 - VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $12, DD1, DD1, DD1 - chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $12, BB1, BB1, BB1 - VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $4, DD1, DD1, DD1 - CMPQ itr2, itr1 - JB openAVX2Tail128LoopA - CMPQ itr2, $160 - JNE openAVX2Tail128LoopB - - VPADDD ·chacha20Constants<>(SB), AA1, AA1 - VPADDD state1StoreAVX2, BB1, BB1 - VPADDD state2StoreAVX2, CC1, CC1 - VPADDD DD0, DD1, DD1 - VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 + ADDQ $0x10, R9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y1, Y1, Y1 + CMPQ R9, CX + JB openAVX2Tail128LoopA + CMPQ R9, $0xa0 + JNE openAVX2Tail128LoopB + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD 32(BP), Y9, Y9 + VPADDD 64(BP), Y13, Y13 + VPADDD Y4, Y1, Y1 + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 openAVX2TailLoop: - CMPQ inl, $32 + CMPQ BX, $0x20 JB openAVX2Tail - SUBQ $32, inl + SUBQ $0x20, BX // Load for decryption - VPXOR (inp), AA0, AA0 - VMOVDQU AA0, (oup) - LEAQ (1*32)(inp), inp - LEAQ (1*32)(oup), oup - VMOVDQA BB0, AA0 - VMOVDQA CC0, BB0 - VMOVDQA DD0, CC0 + VPXOR (SI), Y0, Y0 + VMOVDQU Y0, (DI) + LEAQ 32(SI), SI + LEAQ 32(DI), DI + VMOVDQA Y14, Y0 + VMOVDQA Y12, Y14 + VMOVDQA Y4, Y12 JMP openAVX2TailLoop openAVX2Tail: - CMPQ inl, $16 - VMOVDQA A0, A1 + CMPQ BX, $0x10 + VMOVDQA X0, X1 JB openAVX2TailDone - SUBQ $16, inl + SUBQ $0x10, BX // Load for decryption - VPXOR (inp), A0, T0 - VMOVDQU T0, (oup) - LEAQ (1*16)(inp), inp - LEAQ (1*16)(oup), oup - VPERM2I128 $0x11, AA0, AA0, AA0 - VMOVDQA A0, A1 + VPXOR (SI), X0, X12 + VMOVDQU X12, (DI) + LEAQ 16(SI), SI + LEAQ 16(DI), DI + VPERM2I128 $0x11, Y0, Y0, Y0 + VMOVDQA X0, X1 openAVX2TailDone: VZEROUPPER JMP openSSETail16 -// ---------------------------------------------------------------------------- -// Special optimization for the last 256 bytes of ciphertext openAVX2Tail256: - // Need to decrypt up to 256 bytes - prepare four blocks - VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VMOVDQA DD0, TT1 - VMOVDQA DD1, TT2 + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y4, Y7 + VMOVDQA Y1, Y11 // Compute the number of iterations that will hash data - MOVQ inl, tmpStoreAVX2 - MOVQ inl, itr1 - SUBQ $128, itr1 - SHRQ $4, itr1 - MOVQ $10, itr2 - CMPQ itr1, $10 - CMOVQGT itr2, itr1 - MOVQ inp, inl - XORQ itr2, itr2 + MOVQ BX, 224(BP) + MOVQ BX, CX + SUBQ $0x80, CX + SHRQ $0x04, CX + MOVQ $0x0000000a, R9 + CMPQ CX, $0x0a + CMOVQGT R9, CX + MOVQ SI, BX + XORQ R9, R9 openAVX2Tail256LoopA: - polyAdd(0(inl)) - polyMulAVX2 - LEAQ 16(inl), inl + ADDQ (BX), R10 + ADCQ 8(BX), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(BX), BX - // Perform ChaCha rounds, while hashing the remaining input openAVX2Tail256LoopB: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1 - INCQ itr2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1 - CMPQ itr2, itr1 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + INCQ R9 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + CMPQ R9, CX JB openAVX2Tail256LoopA + CMPQ R9, $0x0a + JNE openAVX2Tail256LoopB + MOVQ BX, R9 + SUBQ SI, BX + MOVQ BX, CX + MOVQ 224(BP), BX - CMPQ itr2, $10 - JNE openAVX2Tail256LoopB - - MOVQ inl, itr2 - SUBQ inp, inl - MOVQ inl, itr1 - MOVQ tmpStoreAVX2, inl - - // Hash the remainder of data (if any) openAVX2Tail256Hash: - ADDQ $16, itr1 - CMPQ itr1, inl - JGT openAVX2Tail256HashEnd - polyAdd (0(itr2)) - polyMulAVX2 - LEAQ 16(itr2), itr2 - JMP openAVX2Tail256Hash + ADDQ $0x10, CX + CMPQ CX, BX + JGT openAVX2Tail256HashEnd + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(R9), R9 + JMP openAVX2Tail256Hash -// Store 128 bytes safely, then go to store loop openAVX2Tail256HashEnd: - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1 - VPADDD TT1, DD0, DD0; VPADDD TT2, DD1, DD1 - VPERM2I128 $0x02, AA0, BB0, AA2; VPERM2I128 $0x02, CC0, DD0, BB2; VPERM2I128 $0x13, AA0, BB0, CC2; VPERM2I128 $0x13, CC0, DD0, DD2 - VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 - - VPXOR (0*32)(inp), AA2, AA2; VPXOR (1*32)(inp), BB2, BB2; VPXOR (2*32)(inp), CC2, CC2; VPXOR (3*32)(inp), DD2, DD2 - VMOVDQU AA2, (0*32)(oup); VMOVDQU BB2, (1*32)(oup); VMOVDQU CC2, (2*32)(oup); VMOVDQU DD2, (3*32)(oup) - LEAQ (4*32)(inp), inp - LEAQ (4*32)(oup), oup - SUBQ $4*32, inl - - JMP openAVX2TailLoop + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD Y7, Y4, Y4 + VPADDD Y11, Y1, Y1 + VPERM2I128 $0x02, Y0, Y14, Y6 + VPERM2I128 $0x02, Y12, Y4, Y10 + VPERM2I128 $0x13, Y0, Y14, Y8 + VPERM2I128 $0x13, Y12, Y4, Y2 + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + VPXOR (SI), Y6, Y6 + VPXOR 32(SI), Y10, Y10 + VPXOR 64(SI), Y8, Y8 + VPXOR 96(SI), Y2, Y2 + VMOVDQU Y6, (DI) + VMOVDQU Y10, 32(DI) + VMOVDQU Y8, 64(DI) + VMOVDQU Y2, 96(DI) + LEAQ 128(SI), SI + LEAQ 128(DI), DI + SUBQ $0x80, BX + JMP openAVX2TailLoop -// ---------------------------------------------------------------------------- -// Special optimization for the last 384 bytes of ciphertext openAVX2Tail384: // Need to decrypt up to 384 bytes - prepare six blocks - VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VPADDD ·avx2IncMask<>(SB), DD1, DD2 - VMOVDQA DD0, ctr0StoreAVX2 - VMOVDQA DD1, ctr1StoreAVX2 - VMOVDQA DD2, ctr2StoreAVX2 + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VMOVDQA Y4, 96(BP) + VMOVDQA Y1, 128(BP) + VMOVDQA Y2, 160(BP) // Compute the number of iterations that will hash two blocks of data - MOVQ inl, tmpStoreAVX2 - MOVQ inl, itr1 - SUBQ $256, itr1 - SHRQ $4, itr1 - ADDQ $6, itr1 - MOVQ $10, itr2 - CMPQ itr1, $10 - CMOVQGT itr2, itr1 - MOVQ inp, inl - XORQ itr2, itr2 + MOVQ BX, 224(BP) + MOVQ BX, CX + SUBQ $0x00000100, CX + SHRQ $0x04, CX + ADDQ $0x06, CX + MOVQ $0x0000000a, R9 + CMPQ CX, $0x0a + CMOVQGT R9, CX + MOVQ SI, BX + XORQ R9, R9 - // Perform ChaCha rounds, while hashing the remaining input openAVX2Tail384LoopB: - polyAdd(0(inl)) - polyMulAVX2 - LEAQ 16(inl), inl + ADDQ (BX), R10 + ADCQ 8(BX), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(BX), BX openAVX2Tail384LoopA: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2 - polyAdd(0(inl)) - polyMulAVX2 - LEAQ 16(inl), inl - INCQ itr2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2 - - CMPQ itr2, itr1 - JB openAVX2Tail384LoopB - - CMPQ itr2, $10 - JNE openAVX2Tail384LoopA - - MOVQ inl, itr2 - SUBQ inp, inl - MOVQ inl, itr1 - MOVQ tmpStoreAVX2, inl + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + ADDQ (BX), R10 + ADCQ 8(BX), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(BX), BX + INCQ R9 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + CMPQ R9, CX + JB openAVX2Tail384LoopB + CMPQ R9, $0x0a + JNE openAVX2Tail384LoopA + MOVQ BX, R9 + SUBQ SI, BX + MOVQ BX, CX + MOVQ 224(BP), BX openAVX2Tail384Hash: - ADDQ $16, itr1 - CMPQ itr1, inl - JGT openAVX2Tail384HashEnd - polyAdd(0(itr2)) - polyMulAVX2 - LEAQ 16(itr2), itr2 - JMP openAVX2Tail384Hash + ADDQ $0x10, CX + CMPQ CX, BX + JGT openAVX2Tail384HashEnd + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(R9), R9 + JMP openAVX2Tail384Hash -// Store 256 bytes safely, then go to store loop openAVX2Tail384HashEnd: - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2 - VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2 - VPERM2I128 $0x02, AA0, BB0, TT0; VPERM2I128 $0x02, CC0, DD0, TT1; VPERM2I128 $0x13, AA0, BB0, TT2; VPERM2I128 $0x13, CC0, DD0, TT3 - VPXOR (0*32)(inp), TT0, TT0; VPXOR (1*32)(inp), TT1, TT1; VPXOR (2*32)(inp), TT2, TT2; VPXOR (3*32)(inp), TT3, TT3 - VMOVDQU TT0, (0*32)(oup); VMOVDQU TT1, (1*32)(oup); VMOVDQU TT2, (2*32)(oup); VMOVDQU TT3, (3*32)(oup) - VPERM2I128 $0x02, AA1, BB1, TT0; VPERM2I128 $0x02, CC1, DD1, TT1; VPERM2I128 $0x13, AA1, BB1, TT2; VPERM2I128 $0x13, CC1, DD1, TT3 - VPXOR (4*32)(inp), TT0, TT0; VPXOR (5*32)(inp), TT1, TT1; VPXOR (6*32)(inp), TT2, TT2; VPXOR (7*32)(inp), TT3, TT3 - VMOVDQU TT0, (4*32)(oup); VMOVDQU TT1, (5*32)(oup); VMOVDQU TT2, (6*32)(oup); VMOVDQU TT3, (7*32)(oup) - VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 - LEAQ (8*32)(inp), inp - LEAQ (8*32)(oup), oup - SUBQ $8*32, inl + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD 96(BP), Y4, Y4 + VPADDD 128(BP), Y1, Y1 + VPADDD 160(BP), Y2, Y2 + VPERM2I128 $0x02, Y0, Y14, Y3 + VPERM2I128 $0x02, Y12, Y4, Y7 + VPERM2I128 $0x13, Y0, Y14, Y11 + VPERM2I128 $0x13, Y12, Y4, Y15 + VPXOR (SI), Y3, Y3 + VPXOR 32(SI), Y7, Y7 + VPXOR 64(SI), Y11, Y11 + VPXOR 96(SI), Y15, Y15 + VMOVDQU Y3, (DI) + VMOVDQU Y7, 32(DI) + VMOVDQU Y11, 64(DI) + VMOVDQU Y15, 96(DI) + VPERM2I128 $0x02, Y5, Y9, Y3 + VPERM2I128 $0x02, Y13, Y1, Y7 + VPERM2I128 $0x13, Y5, Y9, Y11 + VPERM2I128 $0x13, Y13, Y1, Y15 + VPXOR 128(SI), Y3, Y3 + VPXOR 160(SI), Y7, Y7 + VPXOR 192(SI), Y11, Y11 + VPXOR 224(SI), Y15, Y15 + VMOVDQU Y3, 128(DI) + VMOVDQU Y7, 160(DI) + VMOVDQU Y11, 192(DI) + VMOVDQU Y15, 224(DI) + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + LEAQ 256(SI), SI + LEAQ 256(DI), DI + SUBQ $0x00000100, BX JMP openAVX2TailLoop -// ---------------------------------------------------------------------------- -// Special optimization for the last 512 bytes of ciphertext openAVX2Tail512: - VMOVDQU ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 - VMOVDQA ctr3StoreAVX2, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 - VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 - XORQ itr1, itr1 - MOVQ inp, itr2 + VMOVDQU ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA Y0, Y7 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA Y14, Y11 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA Y12, Y15 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 + VMOVDQA Y4, 96(BP) + VMOVDQA Y1, 128(BP) + VMOVDQA Y2, 160(BP) + VMOVDQA Y3, 192(BP) + XORQ CX, CX + MOVQ SI, R9 openAVX2Tail512LoopB: - polyAdd(0(itr2)) - polyMulAVX2 - LEAQ (2*8)(itr2), itr2 + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(R9), R9 openAVX2Tail512LoopA: - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyAdd(0*8(itr2)) - polyMulAVX2 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $4, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2; VPALIGNR $12, DD3, DD3, DD3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - polyAdd(2*8(itr2)) - polyMulAVX2 - LEAQ (4*8)(itr2), itr2 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $12, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2; VPALIGNR $4, DD3, DD3, DD3 - INCQ itr1 - CMPQ itr1, $4 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x04, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPALIGNR $0x0c, Y3, Y3, Y3 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + ADDQ 16(R9), R10 + ADCQ 24(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(R9), R9 + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x0c, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + VPALIGNR $0x04, Y3, Y3, Y3 + INCQ CX + CMPQ CX, $0x04 JLT openAVX2Tail512LoopB - - CMPQ itr1, $10 - JNE openAVX2Tail512LoopA - - MOVQ inl, itr1 - SUBQ $384, itr1 - ANDQ $-16, itr1 + CMPQ CX, $0x0a + JNE openAVX2Tail512LoopA + MOVQ BX, CX + SUBQ $0x00000180, CX + ANDQ $-16, CX openAVX2Tail512HashLoop: - TESTQ itr1, itr1 + TESTQ CX, CX JE openAVX2Tail512HashEnd - polyAdd(0(itr2)) - polyMulAVX2 - LEAQ 16(itr2), itr2 - SUBQ $16, itr1 + ADDQ (R9), R10 + ADCQ 8(R9), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(R9), R9 + SUBQ $0x10, CX JMP openAVX2Tail512HashLoop openAVX2Tail512HashEnd: - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 - VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 - VMOVDQA CC3, tmpStoreAVX2 - VPERM2I128 $0x02, AA0, BB0, CC3; VPERM2I128 $0x13, AA0, BB0, BB0; VPERM2I128 $0x02, CC0, DD0, AA0; VPERM2I128 $0x13, CC0, DD0, CC0 - VPXOR (0*32)(inp), CC3, CC3; VPXOR (1*32)(inp), AA0, AA0; VPXOR (2*32)(inp), BB0, BB0; VPXOR (3*32)(inp), CC0, CC0 - VMOVDQU CC3, (0*32)(oup); VMOVDQU AA0, (1*32)(oup); VMOVDQU BB0, (2*32)(oup); VMOVDQU CC0, (3*32)(oup) - VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 - VPXOR (4*32)(inp), AA0, AA0; VPXOR (5*32)(inp), BB0, BB0; VPXOR (6*32)(inp), CC0, CC0; VPXOR (7*32)(inp), DD0, DD0 - VMOVDQU AA0, (4*32)(oup); VMOVDQU BB0, (5*32)(oup); VMOVDQU CC0, (6*32)(oup); VMOVDQU DD0, (7*32)(oup) - VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 - VPXOR (8*32)(inp), AA0, AA0; VPXOR (9*32)(inp), BB0, BB0; VPXOR (10*32)(inp), CC0, CC0; VPXOR (11*32)(inp), DD0, DD0 - VMOVDQU AA0, (8*32)(oup); VMOVDQU BB0, (9*32)(oup); VMOVDQU CC0, (10*32)(oup); VMOVDQU DD0, (11*32)(oup) - VPERM2I128 $0x02, AA3, BB3, AA0; VPERM2I128 $0x02, tmpStoreAVX2, DD3, BB0; VPERM2I128 $0x13, AA3, BB3, CC0; VPERM2I128 $0x13, tmpStoreAVX2, DD3, DD0 + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 32(BP), Y11, Y11 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD 64(BP), Y15, Y15 + VPADDD 96(BP), Y4, Y4 + VPADDD 128(BP), Y1, Y1 + VPADDD 160(BP), Y2, Y2 + VPADDD 192(BP), Y3, Y3 + VMOVDQA Y15, 224(BP) + VPERM2I128 $0x02, Y0, Y14, Y15 + VPERM2I128 $0x13, Y0, Y14, Y14 + VPERM2I128 $0x02, Y12, Y4, Y0 + VPERM2I128 $0x13, Y12, Y4, Y12 + VPXOR (SI), Y15, Y15 + VPXOR 32(SI), Y0, Y0 + VPXOR 64(SI), Y14, Y14 + VPXOR 96(SI), Y12, Y12 + VMOVDQU Y15, (DI) + VMOVDQU Y0, 32(DI) + VMOVDQU Y14, 64(DI) + VMOVDQU Y12, 96(DI) + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + VPXOR 128(SI), Y0, Y0 + VPXOR 160(SI), Y14, Y14 + VPXOR 192(SI), Y12, Y12 + VPXOR 224(SI), Y4, Y4 + VMOVDQU Y0, 128(DI) + VMOVDQU Y14, 160(DI) + VMOVDQU Y12, 192(DI) + VMOVDQU Y4, 224(DI) + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + VPXOR 256(SI), Y0, Y0 + VPXOR 288(SI), Y14, Y14 + VPXOR 320(SI), Y12, Y12 + VPXOR 352(SI), Y4, Y4 + VMOVDQU Y0, 256(DI) + VMOVDQU Y14, 288(DI) + VMOVDQU Y12, 320(DI) + VMOVDQU Y4, 352(DI) + VPERM2I128 $0x02, Y7, Y11, Y0 + VPERM2I128 $0x02, 224(BP), Y3, Y14 + VPERM2I128 $0x13, Y7, Y11, Y12 + VPERM2I128 $0x13, 224(BP), Y3, Y4 + LEAQ 384(SI), SI + LEAQ 384(DI), DI + SUBQ $0x00000180, BX + JMP openAVX2TailLoop + +DATA ·chacha20Constants<>+0(SB)/4, $0x61707865 +DATA ·chacha20Constants<>+4(SB)/4, $0x3320646e +DATA ·chacha20Constants<>+8(SB)/4, $0x79622d32 +DATA ·chacha20Constants<>+12(SB)/4, $0x6b206574 +DATA ·chacha20Constants<>+16(SB)/4, $0x61707865 +DATA ·chacha20Constants<>+20(SB)/4, $0x3320646e +DATA ·chacha20Constants<>+24(SB)/4, $0x79622d32 +DATA ·chacha20Constants<>+28(SB)/4, $0x6b206574 +GLOBL ·chacha20Constants<>(SB), RODATA|NOPTR, $32 - LEAQ (12*32)(inp), inp - LEAQ (12*32)(oup), oup - SUBQ $12*32, inl +DATA ·polyClampMask<>+0(SB)/8, $0x0ffffffc0fffffff +DATA ·polyClampMask<>+8(SB)/8, $0x0ffffffc0ffffffc +DATA ·polyClampMask<>+16(SB)/8, $0xffffffffffffffff +DATA ·polyClampMask<>+24(SB)/8, $0xffffffffffffffff +GLOBL ·polyClampMask<>(SB), RODATA|NOPTR, $32 - JMP openAVX2TailLoop +DATA ·sseIncMask<>+0(SB)/8, $0x0000000000000001 +DATA ·sseIncMask<>+8(SB)/8, $0x0000000000000000 +GLOBL ·sseIncMask<>(SB), RODATA|NOPTR, $16 -// ---------------------------------------------------------------------------- -// ---------------------------------------------------------------------------- -// func chacha20Poly1305Seal(dst, key, src, ad []byte) -TEXT ·chacha20Poly1305Seal(SB), 0, $288-96 - // For aligned stack access +DATA ·andMask<>+0(SB)/8, $0x00000000000000ff +DATA ·andMask<>+8(SB)/8, $0x0000000000000000 +DATA ·andMask<>+16(SB)/8, $0x000000000000ffff +DATA ·andMask<>+24(SB)/8, $0x0000000000000000 +DATA ·andMask<>+32(SB)/8, $0x0000000000ffffff +DATA ·andMask<>+40(SB)/8, $0x0000000000000000 +DATA ·andMask<>+48(SB)/8, $0x00000000ffffffff +DATA ·andMask<>+56(SB)/8, $0x0000000000000000 +DATA ·andMask<>+64(SB)/8, $0x000000ffffffffff +DATA ·andMask<>+72(SB)/8, $0x0000000000000000 +DATA ·andMask<>+80(SB)/8, $0x0000ffffffffffff +DATA ·andMask<>+88(SB)/8, $0x0000000000000000 +DATA ·andMask<>+96(SB)/8, $0x00ffffffffffffff +DATA ·andMask<>+104(SB)/8, $0x0000000000000000 +DATA ·andMask<>+112(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+120(SB)/8, $0x0000000000000000 +DATA ·andMask<>+128(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+136(SB)/8, $0x00000000000000ff +DATA ·andMask<>+144(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+152(SB)/8, $0x000000000000ffff +DATA ·andMask<>+160(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+168(SB)/8, $0x0000000000ffffff +DATA ·andMask<>+176(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+184(SB)/8, $0x00000000ffffffff +DATA ·andMask<>+192(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+200(SB)/8, $0x000000ffffffffff +DATA ·andMask<>+208(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+216(SB)/8, $0x0000ffffffffffff +DATA ·andMask<>+224(SB)/8, $0xffffffffffffffff +DATA ·andMask<>+232(SB)/8, $0x00ffffffffffffff +GLOBL ·andMask<>(SB), RODATA|NOPTR, $240 + +DATA ·avx2InitMask<>+0(SB)/8, $0x0000000000000000 +DATA ·avx2InitMask<>+8(SB)/8, $0x0000000000000000 +DATA ·avx2InitMask<>+16(SB)/8, $0x0000000000000001 +DATA ·avx2InitMask<>+24(SB)/8, $0x0000000000000000 +GLOBL ·avx2InitMask<>(SB), RODATA|NOPTR, $32 + +DATA ·rol16<>+0(SB)/8, $0x0504070601000302 +DATA ·rol16<>+8(SB)/8, $0x0d0c0f0e09080b0a +DATA ·rol16<>+16(SB)/8, $0x0504070601000302 +DATA ·rol16<>+24(SB)/8, $0x0d0c0f0e09080b0a +GLOBL ·rol16<>(SB), RODATA|NOPTR, $32 + +DATA ·rol8<>+0(SB)/8, $0x0605040702010003 +DATA ·rol8<>+8(SB)/8, $0x0e0d0c0f0a09080b +DATA ·rol8<>+16(SB)/8, $0x0605040702010003 +DATA ·rol8<>+24(SB)/8, $0x0e0d0c0f0a09080b +GLOBL ·rol8<>(SB), RODATA|NOPTR, $32 + +DATA ·avx2IncMask<>+0(SB)/8, $0x0000000000000002 +DATA ·avx2IncMask<>+8(SB)/8, $0x0000000000000000 +DATA ·avx2IncMask<>+16(SB)/8, $0x0000000000000002 +DATA ·avx2IncMask<>+24(SB)/8, $0x0000000000000000 +GLOBL ·avx2IncMask<>(SB), RODATA|NOPTR, $32 + +// func chacha20Poly1305Seal(dst []byte, key []uint32, src []byte, ad []byte) +// Requires: AVX, AVX2, BMI2, CMOV, SSE2 +TEXT ·chacha20Poly1305Seal(SB), $288-96 MOVQ SP, BP - ADDQ $32, BP + ADDQ $0x20, BP ANDQ $-32, BP - MOVQ dst+0(FP), oup - MOVQ key+24(FP), keyp - MOVQ src+48(FP), inp - MOVQ src_len+56(FP), inl - MOVQ ad+72(FP), adp - - CMPB ·useAVX2(SB), $1 + MOVQ dst_base+0(FP), DI + MOVQ key_base+24(FP), R8 + MOVQ src_base+48(FP), SI + MOVQ src_len+56(FP), BX + MOVQ ad_base+72(FP), CX + CMPB ·useAVX2+0(SB), $0x01 JE chacha20Poly1305Seal_AVX2 // Special optimization, for very short buffers - CMPQ inl, $128 - JBE sealSSE128 // About 15% faster + CMPQ BX, $0x80 + JBE sealSSE128 // In the seal case - prepare the poly key + 3 blocks of stream in the first iteration - MOVOU ·chacha20Constants<>(SB), A0 - MOVOU (1*16)(keyp), B0 - MOVOU (2*16)(keyp), C0 - MOVOU (3*16)(keyp), D0 + MOVOU ·chacha20Constants<>+0(SB), X0 + MOVOU 16(R8), X3 + MOVOU 32(R8), X6 + MOVOU 48(R8), X9 // Store state on stack for future use - MOVO B0, state1Store - MOVO C0, state2Store + MOVO X3, 32(BP) + MOVO X6, 48(BP) // Load state, increment counter blocks - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 - MOVO A2, A3; MOVO B2, B3; MOVO C2, C3; MOVO D2, D3; PADDL ·sseIncMask<>(SB), D3 + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X2, X12 + MOVO X5, X13 + MOVO X8, X14 + MOVO X11, X15 + PADDL ·sseIncMask<>+0(SB), X15 // Store counters - MOVO D0, ctr0Store; MOVO D1, ctr1Store; MOVO D2, ctr2Store; MOVO D3, ctr3Store - MOVQ $10, itr2 + MOVO X9, 80(BP) + MOVO X10, 96(BP) + MOVO X11, 112(BP) + MOVO X15, 128(BP) + MOVQ $0x0000000a, R9 sealSSEIntroLoop: - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - shiftB0Left; shiftB1Left; shiftB2Left; shiftB3Left - shiftC0Left; shiftC1Left; shiftC2Left; shiftC3Left - shiftD0Left; shiftD1Left; shiftD2Left; shiftD3Left - - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - shiftB0Right; shiftB1Right; shiftB2Right; shiftB3Right - shiftC0Right; shiftC1Right; shiftC2Right; shiftC3Right - shiftD0Right; shiftD1Right; shiftD2Right; shiftD3Right - DECQ itr2 - JNE sealSSEIntroLoop + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x0c + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x04 + DECQ R9 + JNE sealSSEIntroLoop // Add in the state - PADDD ·chacha20Constants<>(SB), A0; PADDD ·chacha20Constants<>(SB), A1; PADDD ·chacha20Constants<>(SB), A2; PADDD ·chacha20Constants<>(SB), A3 - PADDD state1Store, B0; PADDD state1Store, B1; PADDD state1Store, B2; PADDD state1Store, B3 - PADDD state2Store, C1; PADDD state2Store, C2; PADDD state2Store, C3 - PADDD ctr1Store, D1; PADDD ctr2Store, D2; PADDD ctr3Store, D3 + PADDD ·chacha20Constants<>+0(SB), X0 + PADDD ·chacha20Constants<>+0(SB), X1 + PADDD ·chacha20Constants<>+0(SB), X2 + PADDD ·chacha20Constants<>+0(SB), X12 + PADDD 32(BP), X3 + PADDD 32(BP), X4 + PADDD 32(BP), X5 + PADDD 32(BP), X13 + PADDD 48(BP), X7 + PADDD 48(BP), X8 + PADDD 48(BP), X14 + PADDD 96(BP), X10 + PADDD 112(BP), X11 + PADDD 128(BP), X15 // Clamp and store the key - PAND ·polyClampMask<>(SB), A0 - MOVO A0, rStore - MOVO B0, sStore + PAND ·polyClampMask<>+0(SB), X0 + MOVO X0, (BP) + MOVO X3, 16(BP) // Hash AAD - MOVQ ad_len+80(FP), itr2 - CALL polyHashADInternal<>(SB) - - MOVOU (0*16)(inp), A0; MOVOU (1*16)(inp), B0; MOVOU (2*16)(inp), C0; MOVOU (3*16)(inp), D0 - PXOR A0, A1; PXOR B0, B1; PXOR C0, C1; PXOR D0, D1 - MOVOU A1, (0*16)(oup); MOVOU B1, (1*16)(oup); MOVOU C1, (2*16)(oup); MOVOU D1, (3*16)(oup) - MOVOU (4*16)(inp), A0; MOVOU (5*16)(inp), B0; MOVOU (6*16)(inp), C0; MOVOU (7*16)(inp), D0 - PXOR A0, A2; PXOR B0, B2; PXOR C0, C2; PXOR D0, D2 - MOVOU A2, (4*16)(oup); MOVOU B2, (5*16)(oup); MOVOU C2, (6*16)(oup); MOVOU D2, (7*16)(oup) - - MOVQ $128, itr1 - SUBQ $128, inl - LEAQ 128(inp), inp - - MOVO A3, A1; MOVO B3, B1; MOVO C3, C1; MOVO D3, D1 - - CMPQ inl, $64 - JBE sealSSE128SealHash - - MOVOU (0*16)(inp), A0; MOVOU (1*16)(inp), B0; MOVOU (2*16)(inp), C0; MOVOU (3*16)(inp), D0 - PXOR A0, A3; PXOR B0, B3; PXOR C0, C3; PXOR D0, D3 - MOVOU A3, (8*16)(oup); MOVOU B3, (9*16)(oup); MOVOU C3, (10*16)(oup); MOVOU D3, (11*16)(oup) - - ADDQ $64, itr1 - SUBQ $64, inl - LEAQ 64(inp), inp - - MOVQ $2, itr1 - MOVQ $8, itr2 - - CMPQ inl, $64 - JBE sealSSETail64 - CMPQ inl, $128 - JBE sealSSETail128 - CMPQ inl, $192 - JBE sealSSETail192 + MOVQ ad_len+80(FP), R9 + CALL polyHashADInternal<>(SB) + MOVOU (SI), X0 + MOVOU 16(SI), X3 + MOVOU 32(SI), X6 + MOVOU 48(SI), X9 + PXOR X0, X1 + PXOR X3, X4 + PXOR X6, X7 + PXOR X9, X10 + MOVOU X1, (DI) + MOVOU X4, 16(DI) + MOVOU X7, 32(DI) + MOVOU X10, 48(DI) + MOVOU 64(SI), X0 + MOVOU 80(SI), X3 + MOVOU 96(SI), X6 + MOVOU 112(SI), X9 + PXOR X0, X2 + PXOR X3, X5 + PXOR X6, X8 + PXOR X9, X11 + MOVOU X2, 64(DI) + MOVOU X5, 80(DI) + MOVOU X8, 96(DI) + MOVOU X11, 112(DI) + MOVQ $0x00000080, CX + SUBQ $0x80, BX + LEAQ 128(SI), SI + MOVO X12, X1 + MOVO X13, X4 + MOVO X14, X7 + MOVO X15, X10 + CMPQ BX, $0x40 + JBE sealSSE128SealHash + MOVOU (SI), X0 + MOVOU 16(SI), X3 + MOVOU 32(SI), X6 + MOVOU 48(SI), X9 + PXOR X0, X12 + PXOR X3, X13 + PXOR X6, X14 + PXOR X9, X15 + MOVOU X12, 128(DI) + MOVOU X13, 144(DI) + MOVOU X14, 160(DI) + MOVOU X15, 176(DI) + ADDQ $0x40, CX + SUBQ $0x40, BX + LEAQ 64(SI), SI + MOVQ $0x00000002, CX + MOVQ $0x00000008, R9 + CMPQ BX, $0x40 + JBE sealSSETail64 + CMPQ BX, $0x80 + JBE sealSSETail128 + CMPQ BX, $0xc0 + JBE sealSSETail192 sealSSEMainLoop: // Load state, increment counter blocks - MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0 - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 - MOVO A2, A3; MOVO B2, B3; MOVO C2, C3; MOVO D2, D3; PADDL ·sseIncMask<>(SB), D3 + MOVO ·chacha20Constants<>+0(SB), X0 + MOVO 32(BP), X3 + MOVO 48(BP), X6 + MOVO 128(BP), X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X2, X12 + MOVO X5, X13 + MOVO X8, X14 + MOVO X11, X15 + PADDL ·sseIncMask<>+0(SB), X15 // Store counters - MOVO D0, ctr0Store; MOVO D1, ctr1Store; MOVO D2, ctr2Store; MOVO D3, ctr3Store + MOVO X9, 80(BP) + MOVO X10, 96(BP) + MOVO X11, 112(BP) + MOVO X15, 128(BP) sealSSEInnerLoop: - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - polyAdd(0(oup)) - shiftB0Left; shiftB1Left; shiftB2Left; shiftB3Left - shiftC0Left; shiftC1Left; shiftC2Left; shiftC3Left - shiftD0Left; shiftD1Left; shiftD2Left; shiftD3Left - polyMulStage1 - polyMulStage2 - LEAQ (2*8)(oup), oup - MOVO C3, tmpStore - chachaQR(A0, B0, C0, D0, C3); chachaQR(A1, B1, C1, D1, C3); chachaQR(A2, B2, C2, D2, C3) - MOVO tmpStore, C3 - MOVO C1, tmpStore - polyMulStage3 - chachaQR(A3, B3, C3, D3, C1) - MOVO tmpStore, C1 - polyMulReduceStage - shiftB0Right; shiftB1Right; shiftB2Right; shiftB3Right - shiftC0Right; shiftC1Right; shiftC2Right; shiftC3Right - shiftD0Right; shiftD1Right; shiftD2Right; shiftD3Right - DECQ itr2 - JGE sealSSEInnerLoop - polyAdd(0(oup)) - polyMul - LEAQ (2*8)(oup), oup - DECQ itr1 - JG sealSSEInnerLoop + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x0c + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + LEAQ 16(DI), DI + MOVO X14, 64(BP) + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X3 + PXOR X14, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X14) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X3 + PXOR X14, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X4 + PXOR X14, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X14) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X4 + PXOR X14, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x0c, X14 + PSRLL $0x14, X5 + PXOR X14, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X14) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X14 + PSLLL $0x07, X14 + PSRLL $0x19, X5 + PXOR X14, X5 + MOVO 64(BP), X14 + MOVO X7, 64(BP) + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + PADDD X13, X12 + PXOR X12, X15 + ROL16(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x0c, X7 + PSRLL $0x14, X13 + PXOR X7, X13 + PADDD X13, X12 + PXOR X12, X15 + ROL8(X15, X7) + PADDD X15, X14 + PXOR X14, X13 + MOVO X13, X7 + PSLLL $0x07, X7 + PSRLL $0x19, X13 + PXOR X7, X13 + MOVO 64(BP), X7 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x04 + DECQ R9 + JGE sealSSEInnerLoop + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI + DECQ CX + JG sealSSEInnerLoop // Add in the state - PADDD ·chacha20Constants<>(SB), A0; PADDD ·chacha20Constants<>(SB), A1; PADDD ·chacha20Constants<>(SB), A2; PADDD ·chacha20Constants<>(SB), A3 - PADDD state1Store, B0; PADDD state1Store, B1; PADDD state1Store, B2; PADDD state1Store, B3 - PADDD state2Store, C0; PADDD state2Store, C1; PADDD state2Store, C2; PADDD state2Store, C3 - PADDD ctr0Store, D0; PADDD ctr1Store, D1; PADDD ctr2Store, D2; PADDD ctr3Store, D3 - MOVO D3, tmpStore + PADDD ·chacha20Constants<>+0(SB), X0 + PADDD ·chacha20Constants<>+0(SB), X1 + PADDD ·chacha20Constants<>+0(SB), X2 + PADDD ·chacha20Constants<>+0(SB), X12 + PADDD 32(BP), X3 + PADDD 32(BP), X4 + PADDD 32(BP), X5 + PADDD 32(BP), X13 + PADDD 48(BP), X6 + PADDD 48(BP), X7 + PADDD 48(BP), X8 + PADDD 48(BP), X14 + PADDD 80(BP), X9 + PADDD 96(BP), X10 + PADDD 112(BP), X11 + PADDD 128(BP), X15 + MOVO X15, 64(BP) // Load - xor - store - MOVOU (0*16)(inp), D3; PXOR D3, A0 - MOVOU (1*16)(inp), D3; PXOR D3, B0 - MOVOU (2*16)(inp), D3; PXOR D3, C0 - MOVOU (3*16)(inp), D3; PXOR D3, D0 - MOVOU A0, (0*16)(oup) - MOVOU B0, (1*16)(oup) - MOVOU C0, (2*16)(oup) - MOVOU D0, (3*16)(oup) - MOVO tmpStore, D3 - - MOVOU (4*16)(inp), A0; MOVOU (5*16)(inp), B0; MOVOU (6*16)(inp), C0; MOVOU (7*16)(inp), D0 - PXOR A0, A1; PXOR B0, B1; PXOR C0, C1; PXOR D0, D1 - MOVOU A1, (4*16)(oup); MOVOU B1, (5*16)(oup); MOVOU C1, (6*16)(oup); MOVOU D1, (7*16)(oup) - MOVOU (8*16)(inp), A0; MOVOU (9*16)(inp), B0; MOVOU (10*16)(inp), C0; MOVOU (11*16)(inp), D0 - PXOR A0, A2; PXOR B0, B2; PXOR C0, C2; PXOR D0, D2 - MOVOU A2, (8*16)(oup); MOVOU B2, (9*16)(oup); MOVOU C2, (10*16)(oup); MOVOU D2, (11*16)(oup) - ADDQ $192, inp - MOVQ $192, itr1 - SUBQ $192, inl - MOVO A3, A1 - MOVO B3, B1 - MOVO C3, C1 - MOVO D3, D1 - CMPQ inl, $64 + MOVOU (SI), X15 + PXOR X15, X0 + MOVOU 16(SI), X15 + PXOR X15, X3 + MOVOU 32(SI), X15 + PXOR X15, X6 + MOVOU 48(SI), X15 + PXOR X15, X9 + MOVOU X0, (DI) + MOVOU X3, 16(DI) + MOVOU X6, 32(DI) + MOVOU X9, 48(DI) + MOVO 64(BP), X15 + MOVOU 64(SI), X0 + MOVOU 80(SI), X3 + MOVOU 96(SI), X6 + MOVOU 112(SI), X9 + PXOR X0, X1 + PXOR X3, X4 + PXOR X6, X7 + PXOR X9, X10 + MOVOU X1, 64(DI) + MOVOU X4, 80(DI) + MOVOU X7, 96(DI) + MOVOU X10, 112(DI) + MOVOU 128(SI), X0 + MOVOU 144(SI), X3 + MOVOU 160(SI), X6 + MOVOU 176(SI), X9 + PXOR X0, X2 + PXOR X3, X5 + PXOR X6, X8 + PXOR X9, X11 + MOVOU X2, 128(DI) + MOVOU X5, 144(DI) + MOVOU X8, 160(DI) + MOVOU X11, 176(DI) + ADDQ $0xc0, SI + MOVQ $0x000000c0, CX + SUBQ $0xc0, BX + MOVO X12, X1 + MOVO X13, X4 + MOVO X14, X7 + MOVO X15, X10 + CMPQ BX, $0x40 JBE sealSSE128SealHash - MOVOU (0*16)(inp), A0; MOVOU (1*16)(inp), B0; MOVOU (2*16)(inp), C0; MOVOU (3*16)(inp), D0 - PXOR A0, A3; PXOR B0, B3; PXOR C0, C3; PXOR D0, D3 - MOVOU A3, (12*16)(oup); MOVOU B3, (13*16)(oup); MOVOU C3, (14*16)(oup); MOVOU D3, (15*16)(oup) - LEAQ 64(inp), inp - SUBQ $64, inl - MOVQ $6, itr1 - MOVQ $4, itr2 - CMPQ inl, $192 + MOVOU (SI), X0 + MOVOU 16(SI), X3 + MOVOU 32(SI), X6 + MOVOU 48(SI), X9 + PXOR X0, X12 + PXOR X3, X13 + PXOR X6, X14 + PXOR X9, X15 + MOVOU X12, 192(DI) + MOVOU X13, 208(DI) + MOVOU X14, 224(DI) + MOVOU X15, 240(DI) + LEAQ 64(SI), SI + SUBQ $0x40, BX + MOVQ $0x00000006, CX + MOVQ $0x00000004, R9 + CMPQ BX, $0xc0 JG sealSSEMainLoop - - MOVQ inl, itr1 - TESTQ inl, inl + MOVQ BX, CX + TESTQ BX, BX JE sealSSE128SealHash - MOVQ $6, itr1 - CMPQ inl, $64 + MOVQ $0x00000006, CX + CMPQ BX, $0x40 JBE sealSSETail64 - CMPQ inl, $128 + CMPQ BX, $0x80 JBE sealSSETail128 JMP sealSSETail192 -// ---------------------------------------------------------------------------- -// Special optimization for the last 64 bytes of plaintext sealSSETail64: - // Need to encrypt up to 64 bytes - prepare single block, hash 192 or 256 bytes - MOVO ·chacha20Constants<>(SB), A1 - MOVO state1Store, B1 - MOVO state2Store, C1 - MOVO ctr3Store, D1 - PADDL ·sseIncMask<>(SB), D1 - MOVO D1, ctr0Store + MOVO ·chacha20Constants<>+0(SB), X1 + MOVO 32(BP), X4 + MOVO 48(BP), X7 + MOVO 128(BP), X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X10, 80(BP) sealSSETail64LoopA: - // Perform ChaCha rounds, while hashing the previously encrypted ciphertext - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealSSETail64LoopB: - chachaQR(A1, B1, C1, D1, T1) - shiftB1Left; shiftC1Left; shiftD1Left - chachaQR(A1, B1, C1, D1, T1) - shiftB1Right; shiftC1Right; shiftD1Right - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup - - DECQ itr1 - JG sealSSETail64LoopA - - DECQ itr2 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X13) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X13 + PSLLL $0x0c, X13 + PSRLL $0x14, X4 + PXOR X13, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X13) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X13 + PSLLL $0x07, X13 + PSRLL $0x19, X4 + PXOR X13, X4 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X13) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X13 + PSLLL $0x0c, X13 + PSRLL $0x14, X4 + PXOR X13, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X13) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X13 + PSLLL $0x07, X13 + PSRLL $0x19, X4 + PXOR X13, X4 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI + DECQ CX + JG sealSSETail64LoopA + DECQ R9 JGE sealSSETail64LoopB - PADDL ·chacha20Constants<>(SB), A1 - PADDL state1Store, B1 - PADDL state2Store, C1 - PADDL ctr0Store, D1 - - JMP sealSSE128Seal + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL 32(BP), X4 + PADDL 48(BP), X7 + PADDL 80(BP), X10 + JMP sealSSE128Seal -// ---------------------------------------------------------------------------- -// Special optimization for the last 128 bytes of plaintext sealSSETail128: - // Need to encrypt up to 128 bytes - prepare two blocks, hash 192 or 256 bytes - MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr0Store - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1; MOVO D1, ctr1Store + MOVO ·chacha20Constants<>+0(SB), X0 + MOVO 32(BP), X3 + MOVO 48(BP), X6 + MOVO 128(BP), X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X9, 80(BP) + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X10, 96(BP) sealSSETail128LoopA: - // Perform ChaCha rounds, while hashing the previously encrypted ciphertext - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealSSETail128LoopB: - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0) - shiftB0Left; shiftC0Left; shiftD0Left - shiftB1Left; shiftC1Left; shiftD1Left - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0) - shiftB0Right; shiftC0Right; shiftD0Right - shiftB1Right; shiftC1Right; shiftD1Right - - DECQ itr1 - JG sealSSETail128LoopA - - DECQ itr2 - JGE sealSSETail128LoopB + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + DECQ CX + JG sealSSETail128LoopA + DECQ R9 + JGE sealSSETail128LoopB + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL 32(BP), X3 + PADDL 32(BP), X4 + PADDL 48(BP), X6 + PADDL 48(BP), X7 + PADDL 80(BP), X9 + PADDL 96(BP), X10 + MOVOU (SI), X12 + MOVOU 16(SI), X13 + MOVOU 32(SI), X14 + MOVOU 48(SI), X15 + PXOR X12, X0 + PXOR X13, X3 + PXOR X14, X6 + PXOR X15, X9 + MOVOU X0, (DI) + MOVOU X3, 16(DI) + MOVOU X6, 32(DI) + MOVOU X9, 48(DI) + MOVQ $0x00000040, CX + LEAQ 64(SI), SI + SUBQ $0x40, BX + JMP sealSSE128SealHash - PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1 - PADDL state1Store, B0; PADDL state1Store, B1 - PADDL state2Store, C0; PADDL state2Store, C1 - PADDL ctr0Store, D0; PADDL ctr1Store, D1 - - MOVOU (0*16)(inp), T0; MOVOU (1*16)(inp), T1; MOVOU (2*16)(inp), T2; MOVOU (3*16)(inp), T3 - PXOR T0, A0; PXOR T1, B0; PXOR T2, C0; PXOR T3, D0 - MOVOU A0, (0*16)(oup); MOVOU B0, (1*16)(oup); MOVOU C0, (2*16)(oup); MOVOU D0, (3*16)(oup) - - MOVQ $64, itr1 - LEAQ 64(inp), inp - SUBQ $64, inl - - JMP sealSSE128SealHash - -// ---------------------------------------------------------------------------- -// Special optimization for the last 192 bytes of plaintext sealSSETail192: - // Need to encrypt up to 192 bytes - prepare three blocks, hash 192 or 256 bytes - MOVO ·chacha20Constants<>(SB), A0; MOVO state1Store, B0; MOVO state2Store, C0; MOVO ctr3Store, D0; PADDL ·sseIncMask<>(SB), D0; MOVO D0, ctr0Store - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1; MOVO D1, ctr1Store - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2; MOVO D2, ctr2Store + MOVO ·chacha20Constants<>+0(SB), X0 + MOVO 32(BP), X3 + MOVO 48(BP), X6 + MOVO 128(BP), X9 + PADDL ·sseIncMask<>+0(SB), X9 + MOVO X9, 80(BP) + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X10, 96(BP) + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X11, 112(BP) sealSSETail192LoopA: - // Perform ChaCha rounds, while hashing the previously encrypted ciphertext - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealSSETail192LoopB: - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Left; shiftC0Left; shiftD0Left - shiftB1Left; shiftC1Left; shiftD1Left - shiftB2Left; shiftC2Left; shiftD2Left + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + DECQ CX + JG sealSSETail192LoopA + DECQ R9 + JGE sealSSETail192LoopB + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL ·chacha20Constants<>+0(SB), X2 + PADDL 32(BP), X3 + PADDL 32(BP), X4 + PADDL 32(BP), X5 + PADDL 48(BP), X6 + PADDL 48(BP), X7 + PADDL 48(BP), X8 + PADDL 80(BP), X9 + PADDL 96(BP), X10 + PADDL 112(BP), X11 + MOVOU (SI), X12 + MOVOU 16(SI), X13 + MOVOU 32(SI), X14 + MOVOU 48(SI), X15 + PXOR X12, X0 + PXOR X13, X3 + PXOR X14, X6 + PXOR X15, X9 + MOVOU X0, (DI) + MOVOU X3, 16(DI) + MOVOU X6, 32(DI) + MOVOU X9, 48(DI) + MOVOU 64(SI), X12 + MOVOU 80(SI), X13 + MOVOU 96(SI), X14 + MOVOU 112(SI), X15 + PXOR X12, X1 + PXOR X13, X4 + PXOR X14, X7 + PXOR X15, X10 + MOVOU X1, 64(DI) + MOVOU X4, 80(DI) + MOVOU X7, 96(DI) + MOVOU X10, 112(DI) + MOVO X2, X1 + MOVO X5, X4 + MOVO X8, X7 + MOVO X11, X10 + MOVQ $0x00000080, CX + LEAQ 128(SI), SI + SUBQ $0x80, BX + JMP sealSSE128SealHash - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup - - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Right; shiftC0Right; shiftD0Right - shiftB1Right; shiftC1Right; shiftD1Right - shiftB2Right; shiftC2Right; shiftD2Right - - DECQ itr1 - JG sealSSETail192LoopA - - DECQ itr2 - JGE sealSSETail192LoopB - - PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1; PADDL ·chacha20Constants<>(SB), A2 - PADDL state1Store, B0; PADDL state1Store, B1; PADDL state1Store, B2 - PADDL state2Store, C0; PADDL state2Store, C1; PADDL state2Store, C2 - PADDL ctr0Store, D0; PADDL ctr1Store, D1; PADDL ctr2Store, D2 - - MOVOU (0*16)(inp), T0; MOVOU (1*16)(inp), T1; MOVOU (2*16)(inp), T2; MOVOU (3*16)(inp), T3 - PXOR T0, A0; PXOR T1, B0; PXOR T2, C0; PXOR T3, D0 - MOVOU A0, (0*16)(oup); MOVOU B0, (1*16)(oup); MOVOU C0, (2*16)(oup); MOVOU D0, (3*16)(oup) - MOVOU (4*16)(inp), T0; MOVOU (5*16)(inp), T1; MOVOU (6*16)(inp), T2; MOVOU (7*16)(inp), T3 - PXOR T0, A1; PXOR T1, B1; PXOR T2, C1; PXOR T3, D1 - MOVOU A1, (4*16)(oup); MOVOU B1, (5*16)(oup); MOVOU C1, (6*16)(oup); MOVOU D1, (7*16)(oup) - - MOVO A2, A1 - MOVO B2, B1 - MOVO C2, C1 - MOVO D2, D1 - MOVQ $128, itr1 - LEAQ 128(inp), inp - SUBQ $128, inl - - JMP sealSSE128SealHash - -// ---------------------------------------------------------------------------- -// Special seal optimization for buffers smaller than 129 bytes sealSSE128: - // For up to 128 bytes of ciphertext and 64 bytes for the poly key, we require to process three blocks - MOVOU ·chacha20Constants<>(SB), A0; MOVOU (1*16)(keyp), B0; MOVOU (2*16)(keyp), C0; MOVOU (3*16)(keyp), D0 - MOVO A0, A1; MOVO B0, B1; MOVO C0, C1; MOVO D0, D1; PADDL ·sseIncMask<>(SB), D1 - MOVO A1, A2; MOVO B1, B2; MOVO C1, C2; MOVO D1, D2; PADDL ·sseIncMask<>(SB), D2 - MOVO B0, T1; MOVO C0, T2; MOVO D1, T3 - MOVQ $10, itr2 + MOVOU ·chacha20Constants<>+0(SB), X0 + MOVOU 16(R8), X3 + MOVOU 32(R8), X6 + MOVOU 48(R8), X9 + MOVO X0, X1 + MOVO X3, X4 + MOVO X6, X7 + MOVO X9, X10 + PADDL ·sseIncMask<>+0(SB), X10 + MOVO X1, X2 + MOVO X4, X5 + MOVO X7, X8 + MOVO X10, X11 + PADDL ·sseIncMask<>+0(SB), X11 + MOVO X3, X13 + MOVO X6, X14 + MOVO X10, X15 + MOVQ $0x0000000a, R9 sealSSE128InnerCipherLoop: - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Left; shiftB1Left; shiftB2Left - shiftC0Left; shiftC1Left; shiftC2Left - shiftD0Left; shiftD1Left; shiftD2Left - chachaQR(A0, B0, C0, D0, T0); chachaQR(A1, B1, C1, D1, T0); chachaQR(A2, B2, C2, D2, T0) - shiftB0Right; shiftB1Right; shiftB2Right - shiftC0Right; shiftC1Right; shiftC2Right - shiftD0Right; shiftD1Right; shiftD2Right - DECQ itr2 - JNE sealSSE128InnerCipherLoop + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x04 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x0c + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + PADDD X3, X0 + PXOR X0, X9 + ROL16(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X3 + PXOR X12, X3 + PADDD X3, X0 + PXOR X0, X9 + ROL8(X9, X12) + PADDD X9, X6 + PXOR X6, X3 + MOVO X3, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X3 + PXOR X12, X3 + PADDD X4, X1 + PXOR X1, X10 + ROL16(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X4 + PXOR X12, X4 + PADDD X4, X1 + PXOR X1, X10 + ROL8(X10, X12) + PADDD X10, X7 + PXOR X7, X4 + MOVO X4, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X4 + PXOR X12, X4 + PADDD X5, X2 + PXOR X2, X11 + ROL16(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x0c, X12 + PSRLL $0x14, X5 + PXOR X12, X5 + PADDD X5, X2 + PXOR X2, X11 + ROL8(X11, X12) + PADDD X11, X8 + PXOR X8, X5 + MOVO X5, X12 + PSLLL $0x07, X12 + PSRLL $0x19, X5 + PXOR X12, X5 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xe4 + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xed + BYTE $0x0c + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xf6 + BYTE $0x08 + BYTE $0x66 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xff + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc0 + BYTE $0x08 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xc9 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xd2 + BYTE $0x04 + BYTE $0x66 + BYTE $0x45 + BYTE $0x0f + BYTE $0x3a + BYTE $0x0f + BYTE $0xdb + BYTE $0x04 + DECQ R9 + JNE sealSSE128InnerCipherLoop // A0|B0 hold the Poly1305 32-byte key, C0,D0 can be discarded - PADDL ·chacha20Constants<>(SB), A0; PADDL ·chacha20Constants<>(SB), A1; PADDL ·chacha20Constants<>(SB), A2 - PADDL T1, B0; PADDL T1, B1; PADDL T1, B2 - PADDL T2, C1; PADDL T2, C2 - PADDL T3, D1; PADDL ·sseIncMask<>(SB), T3; PADDL T3, D2 - PAND ·polyClampMask<>(SB), A0 - MOVOU A0, rStore - MOVOU B0, sStore + PADDL ·chacha20Constants<>+0(SB), X0 + PADDL ·chacha20Constants<>+0(SB), X1 + PADDL ·chacha20Constants<>+0(SB), X2 + PADDL X13, X3 + PADDL X13, X4 + PADDL X13, X5 + PADDL X14, X7 + PADDL X14, X8 + PADDL X15, X10 + PADDL ·sseIncMask<>+0(SB), X15 + PADDL X15, X11 + PAND ·polyClampMask<>+0(SB), X0 + MOVOU X0, (BP) + MOVOU X3, 16(BP) // Hash - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) - XORQ itr1, itr1 + XORQ CX, CX sealSSE128SealHash: - // itr1 holds the number of bytes encrypted but not yet hashed - CMPQ itr1, $16 - JB sealSSE128Seal - polyAdd(0(oup)) - polyMul - - SUBQ $16, itr1 - ADDQ $16, oup - - JMP sealSSE128SealHash + CMPQ CX, $0x10 + JB sealSSE128Seal + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + SUBQ $0x10, CX + ADDQ $0x10, DI + JMP sealSSE128SealHash sealSSE128Seal: - CMPQ inl, $16 + CMPQ BX, $0x10 JB sealSSETail - SUBQ $16, inl + SUBQ $0x10, BX // Load for decryption - MOVOU (inp), T0 - PXOR T0, A1 - MOVOU A1, (oup) - LEAQ (1*16)(inp), inp - LEAQ (1*16)(oup), oup + MOVOU (SI), X12 + PXOR X12, X1 + MOVOU X1, (DI) + LEAQ 16(SI), SI + LEAQ 16(DI), DI // Extract for hashing - MOVQ A1, t0 - PSRLDQ $8, A1 - MOVQ A1, t1 - ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $1, acc2 - polyMul + MOVQ X1, R13 + PSRLDQ $0x08, X1 + MOVQ X1, R14 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 // Shift the stream "left" - MOVO B1, A1 - MOVO C1, B1 - MOVO D1, C1 - MOVO A2, D1 - MOVO B2, A2 - MOVO C2, B2 - MOVO D2, C2 + MOVO X4, X1 + MOVO X7, X4 + MOVO X10, X7 + MOVO X2, X10 + MOVO X5, X2 + MOVO X8, X5 + MOVO X11, X8 JMP sealSSE128Seal sealSSETail: - TESTQ inl, inl + TESTQ BX, BX JE sealSSEFinalize // We can only load the PT one byte at a time to avoid read after end of buffer - MOVQ inl, itr2 - SHLQ $4, itr2 - LEAQ ·andMask<>(SB), t0 - MOVQ inl, itr1 - LEAQ -1(inp)(inl*1), inp - XORQ t2, t2 - XORQ t3, t3 + MOVQ BX, R9 + SHLQ $0x04, R9 + LEAQ ·andMask<>+0(SB), R13 + MOVQ BX, CX + LEAQ -1(SI)(BX*1), SI + XORQ R15, R15 + XORQ R8, R8 XORQ AX, AX sealSSETailLoadLoop: - SHLQ $8, t2, t3 - SHLQ $8, t2 - MOVB (inp), AX - XORQ AX, t2 - LEAQ -1(inp), inp - DECQ itr1 + SHLQ $0x08, R15, R8 + SHLQ $0x08, R15 + MOVB (SI), AX + XORQ AX, R15 + LEAQ -1(SI), SI + DECQ CX JNE sealSSETailLoadLoop - MOVQ t2, 0+tmpStore - MOVQ t3, 8+tmpStore - PXOR 0+tmpStore, A1 - MOVOU A1, (oup) - MOVOU -16(t0)(itr2*1), T0 - PAND T0, A1 - MOVQ A1, t0 - PSRLDQ $8, A1 - MOVQ A1, t1 - ADDQ t0, acc0; ADCQ t1, acc1; ADCQ $1, acc2 - polyMul - - ADDQ inl, oup + MOVQ R15, 64(BP) + MOVQ R8, 72(BP) + PXOR 64(BP), X1 + MOVOU X1, (DI) + MOVOU -16(R13)(R9*1), X12 + PAND X12, X1 + MOVQ X1, R13 + PSRLDQ $0x08, X1 + MOVQ X1, R14 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + ADDQ BX, DI sealSSEFinalize: // Hash in the buffer lengths - ADDQ ad_len+80(FP), acc0 - ADCQ src_len+56(FP), acc1 - ADCQ $1, acc2 - polyMul + ADDQ ad_len+80(FP), R10 + ADCQ src_len+56(FP), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 // Final reduce - MOVQ acc0, t0 - MOVQ acc1, t1 - MOVQ acc2, t2 - SUBQ $-5, acc0 - SBBQ $-1, acc1 - SBBQ $3, acc2 - CMOVQCS t0, acc0 - CMOVQCS t1, acc1 - CMOVQCS t2, acc2 + MOVQ R10, R13 + MOVQ R11, R14 + MOVQ R12, R15 + SUBQ $-5, R10 + SBBQ $-1, R11 + SBBQ $0x03, R12 + CMOVQCS R13, R10 + CMOVQCS R14, R11 + CMOVQCS R15, R12 // Add in the "s" part of the key - ADDQ 0+sStore, acc0 - ADCQ 8+sStore, acc1 + ADDQ 16(BP), R10 + ADCQ 24(BP), R11 // Finally store the tag at the end of the message - MOVQ acc0, (0*8)(oup) - MOVQ acc1, (1*8)(oup) + MOVQ R10, (DI) + MOVQ R11, 8(DI) RET -// ---------------------------------------------------------------------------- -// ------------------------- AVX2 Code ---------------------------------------- chacha20Poly1305Seal_AVX2: VZEROUPPER - VMOVDQU ·chacha20Constants<>(SB), AA0 - BYTE $0xc4; BYTE $0x42; BYTE $0x7d; BYTE $0x5a; BYTE $0x70; BYTE $0x10 // broadcasti128 16(r8), ymm14 - BYTE $0xc4; BYTE $0x42; BYTE $0x7d; BYTE $0x5a; BYTE $0x60; BYTE $0x20 // broadcasti128 32(r8), ymm12 - BYTE $0xc4; BYTE $0xc2; BYTE $0x7d; BYTE $0x5a; BYTE $0x60; BYTE $0x30 // broadcasti128 48(r8), ymm4 - VPADDD ·avx2InitMask<>(SB), DD0, DD0 + VMOVDQU ·chacha20Constants<>+0(SB), Y0 + BYTE $0xc4 + BYTE $0x42 + BYTE $0x7d + BYTE $0x5a + BYTE $0x70 + BYTE $0x10 + BYTE $0xc4 + BYTE $0x42 + BYTE $0x7d + BYTE $0x5a + BYTE $0x60 + BYTE $0x20 + BYTE $0xc4 + BYTE $0xc2 + BYTE $0x7d + BYTE $0x5a + BYTE $0x60 + BYTE $0x30 + VPADDD ·avx2InitMask<>+0(SB), Y4, Y4 // Special optimizations, for very short buffers - CMPQ inl, $192 - JBE seal192AVX2 // 33% faster - CMPQ inl, $320 - JBE seal320AVX2 // 17% faster + CMPQ BX, $0x000000c0 + JBE seal192AVX2 + CMPQ BX, $0x00000140 + JBE seal320AVX2 // For the general key prepare the key first - as a byproduct we have 64 bytes of cipher stream - VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 - VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3; VMOVDQA BB0, state1StoreAVX2 - VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3; VMOVDQA CC0, state2StoreAVX2 - VPADDD ·avx2IncMask<>(SB), DD0, DD1; VMOVDQA DD0, ctr0StoreAVX2 - VPADDD ·avx2IncMask<>(SB), DD1, DD2; VMOVDQA DD1, ctr1StoreAVX2 - VPADDD ·avx2IncMask<>(SB), DD2, DD3; VMOVDQA DD2, ctr2StoreAVX2 - VMOVDQA DD3, ctr3StoreAVX2 - MOVQ $10, itr2 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA Y0, Y7 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA Y14, Y11 + VMOVDQA Y14, 32(BP) + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA Y12, Y15 + VMOVDQA Y12, 64(BP) + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y4, 96(BP) + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VMOVDQA Y1, 128(BP) + VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 + VMOVDQA Y2, 160(BP) + VMOVDQA Y3, 192(BP) + MOVQ $0x0000000a, R9 sealAVX2IntroLoop: - VMOVDQA CC3, tmpStoreAVX2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, CC3); chachaQR_AVX2(AA1, BB1, CC1, DD1, CC3); chachaQR_AVX2(AA2, BB2, CC2, DD2, CC3) - VMOVDQA tmpStoreAVX2, CC3 - VMOVDQA CC1, tmpStoreAVX2 - chachaQR_AVX2(AA3, BB3, CC3, DD3, CC1) - VMOVDQA tmpStoreAVX2, CC1 - - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $12, DD0, DD0, DD0 - VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $12, DD1, DD1, DD1 - VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $12, DD2, DD2, DD2 - VPALIGNR $4, BB3, BB3, BB3; VPALIGNR $8, CC3, CC3, CC3; VPALIGNR $12, DD3, DD3, DD3 - - VMOVDQA CC3, tmpStoreAVX2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, CC3); chachaQR_AVX2(AA1, BB1, CC1, DD1, CC3); chachaQR_AVX2(AA2, BB2, CC2, DD2, CC3) - VMOVDQA tmpStoreAVX2, CC3 - VMOVDQA CC1, tmpStoreAVX2 - chachaQR_AVX2(AA3, BB3, CC3, DD3, CC1) - VMOVDQA tmpStoreAVX2, CC1 - - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $4, DD0, DD0, DD0 - VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $4, DD1, DD1, DD1 - VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $4, DD2, DD2, DD2 - VPALIGNR $12, BB3, BB3, BB3; VPALIGNR $8, CC3, CC3, CC3; VPALIGNR $4, DD3, DD3, DD3 - DECQ itr2 - JNE sealAVX2IntroLoop - - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 - VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 - - VPERM2I128 $0x13, CC0, DD0, CC0 // Stream bytes 96 - 127 - VPERM2I128 $0x02, AA0, BB0, DD0 // The Poly1305 key - VPERM2I128 $0x13, AA0, BB0, AA0 // Stream bytes 64 - 95 + VMOVDQA Y15, 224(BP) + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VMOVDQA 224(BP), Y15 + VMOVDQA Y13, 224(BP) + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x0c, Y11, Y13 + VPSRLD $0x14, Y11, Y11 + VPXOR Y13, Y11, Y11 + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x07, Y11, Y13 + VPSRLD $0x19, Y11, Y11 + VPXOR Y13, Y11, Y11 + VMOVDQA 224(BP), Y13 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPALIGNR $0x04, Y11, Y11, Y11 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x0c, Y3, Y3, Y3 + VMOVDQA Y15, 224(BP) + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VMOVDQA 224(BP), Y15 + VMOVDQA Y13, 224(BP) + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x0c, Y11, Y13 + VPSRLD $0x14, Y11, Y11 + VPXOR Y13, Y11, Y11 + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x07, Y11, Y13 + VPSRLD $0x19, Y11, Y11 + VPXOR Y13, Y11, Y11 + VMOVDQA 224(BP), Y13 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x04, Y2, Y2, Y2 + VPALIGNR $0x0c, Y11, Y11, Y11 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x04, Y3, Y3, Y3 + DECQ R9 + JNE sealAVX2IntroLoop + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 32(BP), Y11, Y11 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD 64(BP), Y15, Y15 + VPADDD 96(BP), Y4, Y4 + VPADDD 128(BP), Y1, Y1 + VPADDD 160(BP), Y2, Y2 + VPADDD 192(BP), Y3, Y3 + VPERM2I128 $0x13, Y12, Y4, Y12 + VPERM2I128 $0x02, Y0, Y14, Y4 + VPERM2I128 $0x13, Y0, Y14, Y0 // Clamp and store poly key - VPAND ·polyClampMask<>(SB), DD0, DD0 - VMOVDQA DD0, rsStoreAVX2 + VPAND ·polyClampMask<>+0(SB), Y4, Y4 + VMOVDQA Y4, (BP) // Hash AD - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) // Can store at least 320 bytes - VPXOR (0*32)(inp), AA0, AA0 - VPXOR (1*32)(inp), CC0, CC0 - VMOVDQU AA0, (0*32)(oup) - VMOVDQU CC0, (1*32)(oup) - - VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 - VPXOR (2*32)(inp), AA0, AA0; VPXOR (3*32)(inp), BB0, BB0; VPXOR (4*32)(inp), CC0, CC0; VPXOR (5*32)(inp), DD0, DD0 - VMOVDQU AA0, (2*32)(oup); VMOVDQU BB0, (3*32)(oup); VMOVDQU CC0, (4*32)(oup); VMOVDQU DD0, (5*32)(oup) - VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 - VPXOR (6*32)(inp), AA0, AA0; VPXOR (7*32)(inp), BB0, BB0; VPXOR (8*32)(inp), CC0, CC0; VPXOR (9*32)(inp), DD0, DD0 - VMOVDQU AA0, (6*32)(oup); VMOVDQU BB0, (7*32)(oup); VMOVDQU CC0, (8*32)(oup); VMOVDQU DD0, (9*32)(oup) - - MOVQ $320, itr1 - SUBQ $320, inl - LEAQ 320(inp), inp - - VPERM2I128 $0x02, AA3, BB3, AA0; VPERM2I128 $0x02, CC3, DD3, BB0; VPERM2I128 $0x13, AA3, BB3, CC0; VPERM2I128 $0x13, CC3, DD3, DD0 - CMPQ inl, $128 + VPXOR (SI), Y0, Y0 + VPXOR 32(SI), Y12, Y12 + VMOVDQU Y0, (DI) + VMOVDQU Y12, 32(DI) + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + VPXOR 64(SI), Y0, Y0 + VPXOR 96(SI), Y14, Y14 + VPXOR 128(SI), Y12, Y12 + VPXOR 160(SI), Y4, Y4 + VMOVDQU Y0, 64(DI) + VMOVDQU Y14, 96(DI) + VMOVDQU Y12, 128(DI) + VMOVDQU Y4, 160(DI) + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + VPXOR 192(SI), Y0, Y0 + VPXOR 224(SI), Y14, Y14 + VPXOR 256(SI), Y12, Y12 + VPXOR 288(SI), Y4, Y4 + VMOVDQU Y0, 192(DI) + VMOVDQU Y14, 224(DI) + VMOVDQU Y12, 256(DI) + VMOVDQU Y4, 288(DI) + MOVQ $0x00000140, CX + SUBQ $0x00000140, BX + LEAQ 320(SI), SI + VPERM2I128 $0x02, Y7, Y11, Y0 + VPERM2I128 $0x02, Y15, Y3, Y14 + VPERM2I128 $0x13, Y7, Y11, Y12 + VPERM2I128 $0x13, Y15, Y3, Y4 + CMPQ BX, $0x80 JBE sealAVX2SealHash - - VPXOR (0*32)(inp), AA0, AA0; VPXOR (1*32)(inp), BB0, BB0; VPXOR (2*32)(inp), CC0, CC0; VPXOR (3*32)(inp), DD0, DD0 - VMOVDQU AA0, (10*32)(oup); VMOVDQU BB0, (11*32)(oup); VMOVDQU CC0, (12*32)(oup); VMOVDQU DD0, (13*32)(oup) - SUBQ $128, inl - LEAQ 128(inp), inp - - MOVQ $8, itr1 - MOVQ $2, itr2 - - CMPQ inl, $128 - JBE sealAVX2Tail128 - CMPQ inl, $256 - JBE sealAVX2Tail256 - CMPQ inl, $384 - JBE sealAVX2Tail384 - CMPQ inl, $512 - JBE sealAVX2Tail512 + VPXOR (SI), Y0, Y0 + VPXOR 32(SI), Y14, Y14 + VPXOR 64(SI), Y12, Y12 + VPXOR 96(SI), Y4, Y4 + VMOVDQU Y0, 320(DI) + VMOVDQU Y14, 352(DI) + VMOVDQU Y12, 384(DI) + VMOVDQU Y4, 416(DI) + SUBQ $0x80, BX + LEAQ 128(SI), SI + MOVQ $0x00000008, CX + MOVQ $0x00000002, R9 + CMPQ BX, $0x80 + JBE sealAVX2Tail128 + CMPQ BX, $0x00000100 + JBE sealAVX2Tail256 + CMPQ BX, $0x00000180 + JBE sealAVX2Tail384 + CMPQ BX, $0x00000200 + JBE sealAVX2Tail512 // We have 448 bytes to hash, but main loop hashes 512 bytes at a time - perform some rounds, before the main loop - VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 - VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 - - VMOVDQA CC3, tmpStoreAVX2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, CC3); chachaQR_AVX2(AA1, BB1, CC1, DD1, CC3); chachaQR_AVX2(AA2, BB2, CC2, DD2, CC3) - VMOVDQA tmpStoreAVX2, CC3 - VMOVDQA CC1, tmpStoreAVX2 - chachaQR_AVX2(AA3, BB3, CC3, DD3, CC1) - VMOVDQA tmpStoreAVX2, CC1 - - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $12, DD0, DD0, DD0 - VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $12, DD1, DD1, DD1 - VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $12, DD2, DD2, DD2 - VPALIGNR $4, BB3, BB3, BB3; VPALIGNR $8, CC3, CC3, CC3; VPALIGNR $12, DD3, DD3, DD3 - - VMOVDQA CC3, tmpStoreAVX2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, CC3); chachaQR_AVX2(AA1, BB1, CC1, DD1, CC3); chachaQR_AVX2(AA2, BB2, CC2, DD2, CC3) - VMOVDQA tmpStoreAVX2, CC3 - VMOVDQA CC1, tmpStoreAVX2 - chachaQR_AVX2(AA3, BB3, CC3, DD3, CC1) - VMOVDQA tmpStoreAVX2, CC1 - - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $4, DD0, DD0, DD0 - VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $4, DD1, DD1, DD1 - VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $4, DD2, DD2, DD2 - VPALIGNR $12, BB3, BB3, BB3; VPALIGNR $8, CC3, CC3, CC3; VPALIGNR $4, DD3, DD3, DD3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - - SUBQ $16, oup // Adjust the pointer - MOVQ $9, itr1 - JMP sealAVX2InternalLoopStart + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA Y0, Y7 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA Y14, Y11 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA Y12, Y15 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 + VMOVDQA Y4, 96(BP) + VMOVDQA Y1, 128(BP) + VMOVDQA Y2, 160(BP) + VMOVDQA Y3, 192(BP) + VMOVDQA Y15, 224(BP) + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VMOVDQA 224(BP), Y15 + VMOVDQA Y13, 224(BP) + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x0c, Y11, Y13 + VPSRLD $0x14, Y11, Y11 + VPXOR Y13, Y11, Y11 + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x07, Y11, Y13 + VPSRLD $0x19, Y11, Y11 + VPXOR Y13, Y11, Y11 + VMOVDQA 224(BP), Y13 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPALIGNR $0x04, Y11, Y11, Y11 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x0c, Y3, Y3, Y3 + VMOVDQA Y15, 224(BP) + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VMOVDQA 224(BP), Y15 + VMOVDQA Y13, 224(BP) + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x0c, Y11, Y13 + VPSRLD $0x14, Y11, Y11 + VPXOR Y13, Y11, Y11 + VPADDD Y11, Y7, Y7 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y3, Y15, Y15 + VPXOR Y15, Y11, Y11 + VPSLLD $0x07, Y11, Y13 + VPSRLD $0x19, Y11, Y11 + VPXOR Y13, Y11, Y11 + VMOVDQA 224(BP), Y13 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x04, Y2, Y2, Y2 + VPALIGNR $0x0c, Y11, Y11, Y11 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x04, Y3, Y3, Y3 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + SUBQ $0x10, DI + MOVQ $0x00000009, CX + JMP sealAVX2InternalLoopStart sealAVX2MainLoop: - // Load state, increment counter blocks, store the incremented counters - VMOVDQU ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 - VMOVDQA ctr3StoreAVX2, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 - VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 - MOVQ $10, itr1 + VMOVDQU ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA Y0, Y7 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA Y14, Y11 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA Y12, Y15 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 + VMOVDQA Y4, 96(BP) + VMOVDQA Y1, 128(BP) + VMOVDQA Y2, 160(BP) + VMOVDQA Y3, 192(BP) + MOVQ $0x0000000a, CX sealAVX2InternalLoop: - polyAdd(0*8(oup)) - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - polyMulStage1_AVX2 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - polyMulStage2_AVX2 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - polyMulStage3_AVX2 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulReduceStage + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 sealAVX2InternalLoopStart: - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - polyAdd(2*8(oup)) - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - polyMulStage1_AVX2 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulStage2_AVX2 - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $4, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2; VPALIGNR $12, DD3, DD3, DD3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - polyMulStage3_AVX2 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - polyMulReduceStage - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - polyAdd(4*8(oup)) - LEAQ (6*8)(oup), oup - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulStage1_AVX2 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - polyMulStage2_AVX2 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - polyMulStage3_AVX2 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyMulReduceStage - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $12, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2; VPALIGNR $4, DD3, DD3, DD3 - DECQ itr1 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x04, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPALIGNR $0x0c, Y3, Y3, Y3 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + ADDQ 32(DI), R10 + ADCQ 40(DI), R11 + ADCQ $0x01, R12 + LEAQ 48(DI), DI + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x0c, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + VPALIGNR $0x04, Y3, Y3, Y3 + DECQ CX JNE sealAVX2InternalLoop - - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 - VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 - VMOVDQA CC3, tmpStoreAVX2 + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 32(BP), Y11, Y11 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD 64(BP), Y15, Y15 + VPADDD 96(BP), Y4, Y4 + VPADDD 128(BP), Y1, Y1 + VPADDD 160(BP), Y2, Y2 + VPADDD 192(BP), Y3, Y3 + VMOVDQA Y15, 224(BP) // We only hashed 480 of the 512 bytes available - hash the remaining 32 here - polyAdd(0*8(oup)) - polyMulAVX2 - LEAQ (4*8)(oup), oup - VPERM2I128 $0x02, AA0, BB0, CC3; VPERM2I128 $0x13, AA0, BB0, BB0; VPERM2I128 $0x02, CC0, DD0, AA0; VPERM2I128 $0x13, CC0, DD0, CC0 - VPXOR (0*32)(inp), CC3, CC3; VPXOR (1*32)(inp), AA0, AA0; VPXOR (2*32)(inp), BB0, BB0; VPXOR (3*32)(inp), CC0, CC0 - VMOVDQU CC3, (0*32)(oup); VMOVDQU AA0, (1*32)(oup); VMOVDQU BB0, (2*32)(oup); VMOVDQU CC0, (3*32)(oup) - VPERM2I128 $0x02, AA1, BB1, AA0; VPERM2I128 $0x02, CC1, DD1, BB0; VPERM2I128 $0x13, AA1, BB1, CC0; VPERM2I128 $0x13, CC1, DD1, DD0 - VPXOR (4*32)(inp), AA0, AA0; VPXOR (5*32)(inp), BB0, BB0; VPXOR (6*32)(inp), CC0, CC0; VPXOR (7*32)(inp), DD0, DD0 - VMOVDQU AA0, (4*32)(oup); VMOVDQU BB0, (5*32)(oup); VMOVDQU CC0, (6*32)(oup); VMOVDQU DD0, (7*32)(oup) + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI + VPERM2I128 $0x02, Y0, Y14, Y15 + VPERM2I128 $0x13, Y0, Y14, Y14 + VPERM2I128 $0x02, Y12, Y4, Y0 + VPERM2I128 $0x13, Y12, Y4, Y12 + VPXOR (SI), Y15, Y15 + VPXOR 32(SI), Y0, Y0 + VPXOR 64(SI), Y14, Y14 + VPXOR 96(SI), Y12, Y12 + VMOVDQU Y15, (DI) + VMOVDQU Y0, 32(DI) + VMOVDQU Y14, 64(DI) + VMOVDQU Y12, 96(DI) + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + VPXOR 128(SI), Y0, Y0 + VPXOR 160(SI), Y14, Y14 + VPXOR 192(SI), Y12, Y12 + VPXOR 224(SI), Y4, Y4 + VMOVDQU Y0, 128(DI) + VMOVDQU Y14, 160(DI) + VMOVDQU Y12, 192(DI) + VMOVDQU Y4, 224(DI) // and here - polyAdd(-2*8(oup)) - polyMulAVX2 - VPERM2I128 $0x02, AA2, BB2, AA0; VPERM2I128 $0x02, CC2, DD2, BB0; VPERM2I128 $0x13, AA2, BB2, CC0; VPERM2I128 $0x13, CC2, DD2, DD0 - VPXOR (8*32)(inp), AA0, AA0; VPXOR (9*32)(inp), BB0, BB0; VPXOR (10*32)(inp), CC0, CC0; VPXOR (11*32)(inp), DD0, DD0 - VMOVDQU AA0, (8*32)(oup); VMOVDQU BB0, (9*32)(oup); VMOVDQU CC0, (10*32)(oup); VMOVDQU DD0, (11*32)(oup) - VPERM2I128 $0x02, AA3, BB3, AA0; VPERM2I128 $0x02, tmpStoreAVX2, DD3, BB0; VPERM2I128 $0x13, AA3, BB3, CC0; VPERM2I128 $0x13, tmpStoreAVX2, DD3, DD0 - VPXOR (12*32)(inp), AA0, AA0; VPXOR (13*32)(inp), BB0, BB0; VPXOR (14*32)(inp), CC0, CC0; VPXOR (15*32)(inp), DD0, DD0 - VMOVDQU AA0, (12*32)(oup); VMOVDQU BB0, (13*32)(oup); VMOVDQU CC0, (14*32)(oup); VMOVDQU DD0, (15*32)(oup) - LEAQ (32*16)(inp), inp - SUBQ $(32*16), inl - CMPQ inl, $512 + ADDQ -16(DI), R10 + ADCQ -8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + VPXOR 256(SI), Y0, Y0 + VPXOR 288(SI), Y14, Y14 + VPXOR 320(SI), Y12, Y12 + VPXOR 352(SI), Y4, Y4 + VMOVDQU Y0, 256(DI) + VMOVDQU Y14, 288(DI) + VMOVDQU Y12, 320(DI) + VMOVDQU Y4, 352(DI) + VPERM2I128 $0x02, Y7, Y11, Y0 + VPERM2I128 $0x02, 224(BP), Y3, Y14 + VPERM2I128 $0x13, Y7, Y11, Y12 + VPERM2I128 $0x13, 224(BP), Y3, Y4 + VPXOR 384(SI), Y0, Y0 + VPXOR 416(SI), Y14, Y14 + VPXOR 448(SI), Y12, Y12 + VPXOR 480(SI), Y4, Y4 + VMOVDQU Y0, 384(DI) + VMOVDQU Y14, 416(DI) + VMOVDQU Y12, 448(DI) + VMOVDQU Y4, 480(DI) + LEAQ 512(SI), SI + SUBQ $0x00000200, BX + CMPQ BX, $0x00000200 JG sealAVX2MainLoop // Tail can only hash 480 bytes - polyAdd(0*8(oup)) - polyMulAVX2 - polyAdd(2*8(oup)) - polyMulAVX2 - LEAQ 32(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI + MOVQ $0x0000000a, CX + MOVQ $0x00000000, R9 + CMPQ BX, $0x80 + JBE sealAVX2Tail128 + CMPQ BX, $0x00000100 + JBE sealAVX2Tail256 + CMPQ BX, $0x00000180 + JBE sealAVX2Tail384 + JMP sealAVX2Tail512 - MOVQ $10, itr1 - MOVQ $0, itr2 - CMPQ inl, $128 - JBE sealAVX2Tail128 - CMPQ inl, $256 - JBE sealAVX2Tail256 - CMPQ inl, $384 - JBE sealAVX2Tail384 - JMP sealAVX2Tail512 - -// ---------------------------------------------------------------------------- -// Special optimization for buffers smaller than 193 bytes seal192AVX2: - // For up to 192 bytes of ciphertext and 64 bytes for the poly key, we process four blocks - VMOVDQA AA0, AA1 - VMOVDQA BB0, BB1 - VMOVDQA CC0, CC1 - VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VMOVDQA AA0, AA2 - VMOVDQA BB0, BB2 - VMOVDQA CC0, CC2 - VMOVDQA DD0, DD2 - VMOVDQA DD1, TT3 - MOVQ $10, itr2 + VMOVDQA Y0, Y5 + VMOVDQA Y14, Y9 + VMOVDQA Y12, Y13 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y0, Y6 + VMOVDQA Y14, Y10 + VMOVDQA Y12, Y8 + VMOVDQA Y4, Y2 + VMOVDQA Y1, Y15 + MOVQ $0x0000000a, R9 sealAVX2192InnerCipherLoop: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1 - DECQ itr2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + DECQ R9 JNE sealAVX2192InnerCipherLoop - VPADDD AA2, AA0, AA0; VPADDD AA2, AA1, AA1 - VPADDD BB2, BB0, BB0; VPADDD BB2, BB1, BB1 - VPADDD CC2, CC0, CC0; VPADDD CC2, CC1, CC1 - VPADDD DD2, DD0, DD0; VPADDD TT3, DD1, DD1 - VPERM2I128 $0x02, AA0, BB0, TT0 + VPADDD Y6, Y0, Y0 + VPADDD Y6, Y5, Y5 + VPADDD Y10, Y14, Y14 + VPADDD Y10, Y9, Y9 + VPADDD Y8, Y12, Y12 + VPADDD Y8, Y13, Y13 + VPADDD Y2, Y4, Y4 + VPADDD Y15, Y1, Y1 + VPERM2I128 $0x02, Y0, Y14, Y3 // Clamp and store poly key - VPAND ·polyClampMask<>(SB), TT0, TT0 - VMOVDQA TT0, rsStoreAVX2 + VPAND ·polyClampMask<>+0(SB), Y3, Y3 + VMOVDQA Y3, (BP) // Stream for up to 192 bytes - VPERM2I128 $0x13, AA0, BB0, AA0 - VPERM2I128 $0x13, CC0, DD0, BB0 - VPERM2I128 $0x02, AA1, BB1, CC0 - VPERM2I128 $0x02, CC1, DD1, DD0 - VPERM2I128 $0x13, AA1, BB1, AA1 - VPERM2I128 $0x13, CC1, DD1, BB1 + VPERM2I128 $0x13, Y0, Y14, Y0 + VPERM2I128 $0x13, Y12, Y4, Y14 + VPERM2I128 $0x02, Y5, Y9, Y12 + VPERM2I128 $0x02, Y13, Y1, Y4 + VPERM2I128 $0x13, Y5, Y9, Y5 + VPERM2I128 $0x13, Y13, Y1, Y9 sealAVX2ShortSeal: // Hash aad - MOVQ ad_len+80(FP), itr2 + MOVQ ad_len+80(FP), R9 CALL polyHashADInternal<>(SB) - XORQ itr1, itr1 + XORQ CX, CX sealAVX2SealHash: // itr1 holds the number of bytes encrypted but not yet hashed - CMPQ itr1, $16 - JB sealAVX2ShortSealLoop - polyAdd(0(oup)) - polyMul - SUBQ $16, itr1 - ADDQ $16, oup - JMP sealAVX2SealHash + CMPQ CX, $0x10 + JB sealAVX2ShortSealLoop + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + SUBQ $0x10, CX + ADDQ $0x10, DI + JMP sealAVX2SealHash sealAVX2ShortSealLoop: - CMPQ inl, $32 + CMPQ BX, $0x20 JB sealAVX2ShortTail32 - SUBQ $32, inl + SUBQ $0x20, BX // Load for encryption - VPXOR (inp), AA0, AA0 - VMOVDQU AA0, (oup) - LEAQ (1*32)(inp), inp + VPXOR (SI), Y0, Y0 + VMOVDQU Y0, (DI) + LEAQ 32(SI), SI // Now can hash - polyAdd(0*8(oup)) - polyMulAVX2 - polyAdd(2*8(oup)) - polyMulAVX2 - LEAQ (1*32)(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI // Shift stream left - VMOVDQA BB0, AA0 - VMOVDQA CC0, BB0 - VMOVDQA DD0, CC0 - VMOVDQA AA1, DD0 - VMOVDQA BB1, AA1 - VMOVDQA CC1, BB1 - VMOVDQA DD1, CC1 - VMOVDQA AA2, DD1 - VMOVDQA BB2, AA2 + VMOVDQA Y14, Y0 + VMOVDQA Y12, Y14 + VMOVDQA Y4, Y12 + VMOVDQA Y5, Y4 + VMOVDQA Y9, Y5 + VMOVDQA Y13, Y9 + VMOVDQA Y1, Y13 + VMOVDQA Y6, Y1 + VMOVDQA Y10, Y6 JMP sealAVX2ShortSealLoop sealAVX2ShortTail32: - CMPQ inl, $16 - VMOVDQA A0, A1 + CMPQ BX, $0x10 + VMOVDQA X0, X1 JB sealAVX2ShortDone - - SUBQ $16, inl + SUBQ $0x10, BX // Load for encryption - VPXOR (inp), A0, T0 - VMOVDQU T0, (oup) - LEAQ (1*16)(inp), inp + VPXOR (SI), X0, X12 + VMOVDQU X12, (DI) + LEAQ 16(SI), SI // Hash - polyAdd(0*8(oup)) - polyMulAVX2 - LEAQ (1*16)(oup), oup - VPERM2I128 $0x11, AA0, AA0, AA0 - VMOVDQA A0, A1 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI + VPERM2I128 $0x11, Y0, Y0, Y0 + VMOVDQA X0, X1 sealAVX2ShortDone: VZEROUPPER JMP sealSSETail -// ---------------------------------------------------------------------------- -// Special optimization for buffers smaller than 321 bytes seal320AVX2: - // For up to 320 bytes of ciphertext and 64 bytes for the poly key, we process six blocks - VMOVDQA AA0, AA1; VMOVDQA BB0, BB1; VMOVDQA CC0, CC1; VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VMOVDQA AA0, AA2; VMOVDQA BB0, BB2; VMOVDQA CC0, CC2; VPADDD ·avx2IncMask<>(SB), DD1, DD2 - VMOVDQA BB0, TT1; VMOVDQA CC0, TT2; VMOVDQA DD0, TT3 - MOVQ $10, itr2 + VMOVDQA Y0, Y5 + VMOVDQA Y14, Y9 + VMOVDQA Y12, Y13 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y0, Y6 + VMOVDQA Y14, Y10 + VMOVDQA Y12, Y8 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VMOVDQA Y14, Y7 + VMOVDQA Y12, Y11 + VMOVDQA Y4, Y15 + MOVQ $0x0000000a, R9 sealAVX2320InnerCipherLoop: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2 - DECQ itr2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + DECQ R9 JNE sealAVX2320InnerCipherLoop - - VMOVDQA ·chacha20Constants<>(SB), TT0 - VPADDD TT0, AA0, AA0; VPADDD TT0, AA1, AA1; VPADDD TT0, AA2, AA2 - VPADDD TT1, BB0, BB0; VPADDD TT1, BB1, BB1; VPADDD TT1, BB2, BB2 - VPADDD TT2, CC0, CC0; VPADDD TT2, CC1, CC1; VPADDD TT2, CC2, CC2 - VMOVDQA ·avx2IncMask<>(SB), TT0 - VPADDD TT3, DD0, DD0; VPADDD TT0, TT3, TT3 - VPADDD TT3, DD1, DD1; VPADDD TT0, TT3, TT3 - VPADDD TT3, DD2, DD2 + VMOVDQA ·chacha20Constants<>+0(SB), Y3 + VPADDD Y3, Y0, Y0 + VPADDD Y3, Y5, Y5 + VPADDD Y3, Y6, Y6 + VPADDD Y7, Y14, Y14 + VPADDD Y7, Y9, Y9 + VPADDD Y7, Y10, Y10 + VPADDD Y11, Y12, Y12 + VPADDD Y11, Y13, Y13 + VPADDD Y11, Y8, Y8 + VMOVDQA ·avx2IncMask<>+0(SB), Y3 + VPADDD Y15, Y4, Y4 + VPADDD Y3, Y15, Y15 + VPADDD Y15, Y1, Y1 + VPADDD Y3, Y15, Y15 + VPADDD Y15, Y2, Y2 // Clamp and store poly key - VPERM2I128 $0x02, AA0, BB0, TT0 - VPAND ·polyClampMask<>(SB), TT0, TT0 - VMOVDQA TT0, rsStoreAVX2 + VPERM2I128 $0x02, Y0, Y14, Y3 + VPAND ·polyClampMask<>+0(SB), Y3, Y3 + VMOVDQA Y3, (BP) // Stream for up to 320 bytes - VPERM2I128 $0x13, AA0, BB0, AA0 - VPERM2I128 $0x13, CC0, DD0, BB0 - VPERM2I128 $0x02, AA1, BB1, CC0 - VPERM2I128 $0x02, CC1, DD1, DD0 - VPERM2I128 $0x13, AA1, BB1, AA1 - VPERM2I128 $0x13, CC1, DD1, BB1 - VPERM2I128 $0x02, AA2, BB2, CC1 - VPERM2I128 $0x02, CC2, DD2, DD1 - VPERM2I128 $0x13, AA2, BB2, AA2 - VPERM2I128 $0x13, CC2, DD2, BB2 + VPERM2I128 $0x13, Y0, Y14, Y0 + VPERM2I128 $0x13, Y12, Y4, Y14 + VPERM2I128 $0x02, Y5, Y9, Y12 + VPERM2I128 $0x02, Y13, Y1, Y4 + VPERM2I128 $0x13, Y5, Y9, Y5 + VPERM2I128 $0x13, Y13, Y1, Y9 + VPERM2I128 $0x02, Y6, Y10, Y13 + VPERM2I128 $0x02, Y8, Y2, Y1 + VPERM2I128 $0x13, Y6, Y10, Y6 + VPERM2I128 $0x13, Y8, Y2, Y10 JMP sealAVX2ShortSeal -// ---------------------------------------------------------------------------- -// Special optimization for the last 128 bytes of ciphertext sealAVX2Tail128: - // Need to decrypt up to 128 bytes - prepare two blocks - // If we got here after the main loop - there are 512 encrypted bytes waiting to be hashed - // If we got here before the main loop - there are 448 encrpyred bytes waiting to be hashed - VMOVDQA ·chacha20Constants<>(SB), AA0 - VMOVDQA state1StoreAVX2, BB0 - VMOVDQA state2StoreAVX2, CC0 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0 - VMOVDQA DD0, DD1 + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA 32(BP), Y14 + VMOVDQA 64(BP), Y12 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VMOVDQA Y4, Y1 sealAVX2Tail128LoopA: - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealAVX2Tail128LoopB: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0) - polyAdd(0(oup)) - polyMul - VPALIGNR $4, BB0, BB0, BB0 - VPALIGNR $8, CC0, CC0, CC0 - VPALIGNR $12, DD0, DD0, DD0 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0) - polyAdd(16(oup)) - polyMul - LEAQ 32(oup), oup - VPALIGNR $12, BB0, BB0, BB0 - VPALIGNR $8, CC0, CC0, CC0 - VPALIGNR $4, DD0, DD0, DD0 - DECQ itr1 - JG sealAVX2Tail128LoopA - DECQ itr2 - JGE sealAVX2Tail128LoopB - - VPADDD ·chacha20Constants<>(SB), AA0, AA1 - VPADDD state1StoreAVX2, BB0, BB1 - VPADDD state2StoreAVX2, CC0, CC1 - VPADDD DD1, DD0, DD1 - - VPERM2I128 $0x02, AA1, BB1, AA0 - VPERM2I128 $0x02, CC1, DD1, BB0 - VPERM2I128 $0x13, AA1, BB1, CC0 - VPERM2I128 $0x13, CC1, DD1, DD0 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x04, Y4, Y4, Y4 + DECQ CX + JG sealAVX2Tail128LoopA + DECQ R9 + JGE sealAVX2Tail128LoopB + VPADDD ·chacha20Constants<>+0(SB), Y0, Y5 + VPADDD 32(BP), Y14, Y9 + VPADDD 64(BP), Y12, Y13 + VPADDD Y1, Y4, Y1 + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 JMP sealAVX2ShortSealLoop -// ---------------------------------------------------------------------------- -// Special optimization for the last 256 bytes of ciphertext sealAVX2Tail256: - // Need to decrypt up to 256 bytes - prepare two blocks - // If we got here after the main loop - there are 512 encrypted bytes waiting to be hashed - // If we got here before the main loop - there are 448 encrpyred bytes waiting to be hashed - VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA ·chacha20Constants<>(SB), AA1 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA state1StoreAVX2, BB1 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA state2StoreAVX2, CC1 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD1 - VMOVDQA DD0, TT1 - VMOVDQA DD1, TT2 + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA ·chacha20Constants<>+0(SB), Y5 + VMOVDQA 32(BP), Y14 + VMOVDQA 32(BP), Y9 + VMOVDQA 64(BP), Y12 + VMOVDQA 64(BP), Y13 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VMOVDQA Y4, Y7 + VMOVDQA Y1, Y11 sealAVX2Tail256LoopA: - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealAVX2Tail256LoopB: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - polyAdd(0(oup)) - polyMul - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) - polyAdd(16(oup)) - polyMul - LEAQ 32(oup), oup - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1 - DECQ itr1 - JG sealAVX2Tail256LoopA - DECQ itr2 - JGE sealAVX2Tail256LoopB - - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1 - VPADDD TT1, DD0, DD0; VPADDD TT2, DD1, DD1 - VPERM2I128 $0x02, AA0, BB0, TT0 - VPERM2I128 $0x02, CC0, DD0, TT1 - VPERM2I128 $0x13, AA0, BB0, TT2 - VPERM2I128 $0x13, CC0, DD0, TT3 - VPXOR (0*32)(inp), TT0, TT0; VPXOR (1*32)(inp), TT1, TT1; VPXOR (2*32)(inp), TT2, TT2; VPXOR (3*32)(inp), TT3, TT3 - VMOVDQU TT0, (0*32)(oup); VMOVDQU TT1, (1*32)(oup); VMOVDQU TT2, (2*32)(oup); VMOVDQU TT3, (3*32)(oup) - MOVQ $128, itr1 - LEAQ 128(inp), inp - SUBQ $128, inl - VPERM2I128 $0x02, AA1, BB1, AA0 - VPERM2I128 $0x02, CC1, DD1, BB0 - VPERM2I128 $0x13, AA1, BB1, CC0 - VPERM2I128 $0x13, CC1, DD1, DD0 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + DECQ CX + JG sealAVX2Tail256LoopA + DECQ R9 + JGE sealAVX2Tail256LoopB + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD Y7, Y4, Y4 + VPADDD Y11, Y1, Y1 + VPERM2I128 $0x02, Y0, Y14, Y3 + VPERM2I128 $0x02, Y12, Y4, Y7 + VPERM2I128 $0x13, Y0, Y14, Y11 + VPERM2I128 $0x13, Y12, Y4, Y15 + VPXOR (SI), Y3, Y3 + VPXOR 32(SI), Y7, Y7 + VPXOR 64(SI), Y11, Y11 + VPXOR 96(SI), Y15, Y15 + VMOVDQU Y3, (DI) + VMOVDQU Y7, 32(DI) + VMOVDQU Y11, 64(DI) + VMOVDQU Y15, 96(DI) + MOVQ $0x00000080, CX + LEAQ 128(SI), SI + SUBQ $0x80, BX + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + JMP sealAVX2SealHash - JMP sealAVX2SealHash - -// ---------------------------------------------------------------------------- -// Special optimization for the last 384 bytes of ciphertext sealAVX2Tail384: - // Need to decrypt up to 384 bytes - prepare two blocks - // If we got here after the main loop - there are 512 encrypted bytes waiting to be hashed - // If we got here before the main loop - there are 448 encrpyred bytes waiting to be hashed - VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2 - VMOVDQA DD0, TT1; VMOVDQA DD1, TT2; VMOVDQA DD2, TT3 + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VMOVDQA Y4, Y7 + VMOVDQA Y1, Y11 + VMOVDQA Y2, Y15 sealAVX2Tail384LoopA: - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealAVX2Tail384LoopB: - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - polyAdd(0(oup)) - polyMul - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2 - chachaQR_AVX2(AA0, BB0, CC0, DD0, TT0); chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0); chachaQR_AVX2(AA2, BB2, CC2, DD2, TT0) - polyAdd(16(oup)) - polyMul - LEAQ 32(oup), oup - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2 - DECQ itr1 - JG sealAVX2Tail384LoopA - DECQ itr2 - JGE sealAVX2Tail384LoopB + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x0c, Y14, Y3 + VPSRLD $0x14, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y14, Y0, Y0 + VPXOR Y0, Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPADDD Y4, Y12, Y12 + VPXOR Y12, Y14, Y14 + VPSLLD $0x07, Y14, Y3 + VPSRLD $0x19, Y14, Y14 + VPXOR Y3, Y14, Y14 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x0c, Y9, Y3 + VPSRLD $0x14, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y9, Y5, Y5 + VPXOR Y5, Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPADDD Y1, Y13, Y13 + VPXOR Y13, Y9, Y9 + VPSLLD $0x07, Y9, Y3 + VPSRLD $0x19, Y9, Y9 + VPXOR Y3, Y9, Y9 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x0c, Y10, Y3 + VPSRLD $0x14, Y10, Y10 + VPXOR Y3, Y10, Y10 + VPADDD Y10, Y6, Y6 + VPXOR Y6, Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPADDD Y2, Y8, Y8 + VPXOR Y8, Y10, Y10 + VPSLLD $0x07, Y10, Y3 + VPSRLD $0x19, Y10, Y10 + VPXOR Y3, Y10, Y10 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + DECQ CX + JG sealAVX2Tail384LoopA + DECQ R9 + JGE sealAVX2Tail384LoopB + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD Y7, Y4, Y4 + VPADDD Y11, Y1, Y1 + VPADDD Y15, Y2, Y2 + VPERM2I128 $0x02, Y0, Y14, Y3 + VPERM2I128 $0x02, Y12, Y4, Y7 + VPERM2I128 $0x13, Y0, Y14, Y11 + VPERM2I128 $0x13, Y12, Y4, Y15 + VPXOR (SI), Y3, Y3 + VPXOR 32(SI), Y7, Y7 + VPXOR 64(SI), Y11, Y11 + VPXOR 96(SI), Y15, Y15 + VMOVDQU Y3, (DI) + VMOVDQU Y7, 32(DI) + VMOVDQU Y11, 64(DI) + VMOVDQU Y15, 96(DI) + VPERM2I128 $0x02, Y5, Y9, Y3 + VPERM2I128 $0x02, Y13, Y1, Y7 + VPERM2I128 $0x13, Y5, Y9, Y11 + VPERM2I128 $0x13, Y13, Y1, Y15 + VPXOR 128(SI), Y3, Y3 + VPXOR 160(SI), Y7, Y7 + VPXOR 192(SI), Y11, Y11 + VPXOR 224(SI), Y15, Y15 + VMOVDQU Y3, 128(DI) + VMOVDQU Y7, 160(DI) + VMOVDQU Y11, 192(DI) + VMOVDQU Y15, 224(DI) + MOVQ $0x00000100, CX + LEAQ 256(SI), SI + SUBQ $0x00000100, BX + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + JMP sealAVX2SealHash - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2 - VPADDD TT1, DD0, DD0; VPADDD TT2, DD1, DD1; VPADDD TT3, DD2, DD2 - VPERM2I128 $0x02, AA0, BB0, TT0 - VPERM2I128 $0x02, CC0, DD0, TT1 - VPERM2I128 $0x13, AA0, BB0, TT2 - VPERM2I128 $0x13, CC0, DD0, TT3 - VPXOR (0*32)(inp), TT0, TT0; VPXOR (1*32)(inp), TT1, TT1; VPXOR (2*32)(inp), TT2, TT2; VPXOR (3*32)(inp), TT3, TT3 - VMOVDQU TT0, (0*32)(oup); VMOVDQU TT1, (1*32)(oup); VMOVDQU TT2, (2*32)(oup); VMOVDQU TT3, (3*32)(oup) - VPERM2I128 $0x02, AA1, BB1, TT0 - VPERM2I128 $0x02, CC1, DD1, TT1 - VPERM2I128 $0x13, AA1, BB1, TT2 - VPERM2I128 $0x13, CC1, DD1, TT3 - VPXOR (4*32)(inp), TT0, TT0; VPXOR (5*32)(inp), TT1, TT1; VPXOR (6*32)(inp), TT2, TT2; VPXOR (7*32)(inp), TT3, TT3 - VMOVDQU TT0, (4*32)(oup); VMOVDQU TT1, (5*32)(oup); VMOVDQU TT2, (6*32)(oup); VMOVDQU TT3, (7*32)(oup) - MOVQ $256, itr1 - LEAQ 256(inp), inp - SUBQ $256, inl - VPERM2I128 $0x02, AA2, BB2, AA0 - VPERM2I128 $0x02, CC2, DD2, BB0 - VPERM2I128 $0x13, AA2, BB2, CC0 - VPERM2I128 $0x13, CC2, DD2, DD0 - - JMP sealAVX2SealHash - -// ---------------------------------------------------------------------------- -// Special optimization for the last 512 bytes of ciphertext sealAVX2Tail512: - // Need to decrypt up to 512 bytes - prepare two blocks - // If we got here after the main loop - there are 512 encrypted bytes waiting to be hashed - // If we got here before the main loop - there are 448 encrpyred bytes waiting to be hashed - VMOVDQA ·chacha20Constants<>(SB), AA0; VMOVDQA AA0, AA1; VMOVDQA AA0, AA2; VMOVDQA AA0, AA3 - VMOVDQA state1StoreAVX2, BB0; VMOVDQA BB0, BB1; VMOVDQA BB0, BB2; VMOVDQA BB0, BB3 - VMOVDQA state2StoreAVX2, CC0; VMOVDQA CC0, CC1; VMOVDQA CC0, CC2; VMOVDQA CC0, CC3 - VMOVDQA ctr3StoreAVX2, DD0 - VPADDD ·avx2IncMask<>(SB), DD0, DD0; VPADDD ·avx2IncMask<>(SB), DD0, DD1; VPADDD ·avx2IncMask<>(SB), DD1, DD2; VPADDD ·avx2IncMask<>(SB), DD2, DD3 - VMOVDQA DD0, ctr0StoreAVX2; VMOVDQA DD1, ctr1StoreAVX2; VMOVDQA DD2, ctr2StoreAVX2; VMOVDQA DD3, ctr3StoreAVX2 + VMOVDQA ·chacha20Constants<>+0(SB), Y0 + VMOVDQA Y0, Y5 + VMOVDQA Y0, Y6 + VMOVDQA Y0, Y7 + VMOVDQA 32(BP), Y14 + VMOVDQA Y14, Y9 + VMOVDQA Y14, Y10 + VMOVDQA Y14, Y11 + VMOVDQA 64(BP), Y12 + VMOVDQA Y12, Y13 + VMOVDQA Y12, Y8 + VMOVDQA Y12, Y15 + VMOVDQA 192(BP), Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y4 + VPADDD ·avx2IncMask<>+0(SB), Y4, Y1 + VPADDD ·avx2IncMask<>+0(SB), Y1, Y2 + VPADDD ·avx2IncMask<>+0(SB), Y2, Y3 + VMOVDQA Y4, 96(BP) + VMOVDQA Y1, 128(BP) + VMOVDQA Y2, 160(BP) + VMOVDQA Y3, 192(BP) sealAVX2Tail512LoopA: - polyAdd(0(oup)) - polyMul - LEAQ 16(oup), oup + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), AX + MOVQ AX, R15 + MULQ R10 + MOVQ AX, R13 + MOVQ DX, R14 + MOVQ (BP), AX + MULQ R11 + IMULQ R12, R15 + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), AX + MOVQ AX, R8 + MULQ R10 + ADDQ AX, R14 + ADCQ $0x00, DX + MOVQ DX, R10 + MOVQ 8(BP), AX + MULQ R11 + ADDQ AX, R15 + ADCQ $0x00, DX + IMULQ R12, R8 + ADDQ R10, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 16(DI), DI sealAVX2Tail512LoopB: - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - polyAdd(0*8(oup)) - polyMulAVX2 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - VPALIGNR $4, BB0, BB0, BB0; VPALIGNR $4, BB1, BB1, BB1; VPALIGNR $4, BB2, BB2, BB2; VPALIGNR $4, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $12, DD0, DD0, DD0; VPALIGNR $12, DD1, DD1, DD1; VPALIGNR $12, DD2, DD2, DD2; VPALIGNR $12, DD3, DD3, DD3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol16<>(SB), DD0, DD0; VPSHUFB ·rol16<>(SB), DD1, DD1; VPSHUFB ·rol16<>(SB), DD2, DD2; VPSHUFB ·rol16<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - polyAdd(2*8(oup)) - polyMulAVX2 - LEAQ (4*8)(oup), oup - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $12, BB0, CC3; VPSRLD $20, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $12, BB1, CC3; VPSRLD $20, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $12, BB2, CC3; VPSRLD $20, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $12, BB3, CC3; VPSRLD $20, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - VPADDD BB0, AA0, AA0; VPADDD BB1, AA1, AA1; VPADDD BB2, AA2, AA2; VPADDD BB3, AA3, AA3 - VPXOR AA0, DD0, DD0; VPXOR AA1, DD1, DD1; VPXOR AA2, DD2, DD2; VPXOR AA3, DD3, DD3 - VPSHUFB ·rol8<>(SB), DD0, DD0; VPSHUFB ·rol8<>(SB), DD1, DD1; VPSHUFB ·rol8<>(SB), DD2, DD2; VPSHUFB ·rol8<>(SB), DD3, DD3 - VPADDD DD0, CC0, CC0; VPADDD DD1, CC1, CC1; VPADDD DD2, CC2, CC2; VPADDD DD3, CC3, CC3 - VPXOR CC0, BB0, BB0; VPXOR CC1, BB1, BB1; VPXOR CC2, BB2, BB2; VPXOR CC3, BB3, BB3 - VMOVDQA CC3, tmpStoreAVX2 - VPSLLD $7, BB0, CC3; VPSRLD $25, BB0, BB0; VPXOR CC3, BB0, BB0 - VPSLLD $7, BB1, CC3; VPSRLD $25, BB1, BB1; VPXOR CC3, BB1, BB1 - VPSLLD $7, BB2, CC3; VPSRLD $25, BB2, BB2; VPXOR CC3, BB2, BB2 - VPSLLD $7, BB3, CC3; VPSRLD $25, BB3, BB3; VPXOR CC3, BB3, BB3 - VMOVDQA tmpStoreAVX2, CC3 - VPALIGNR $12, BB0, BB0, BB0; VPALIGNR $12, BB1, BB1, BB1; VPALIGNR $12, BB2, BB2, BB2; VPALIGNR $12, BB3, BB3, BB3 - VPALIGNR $8, CC0, CC0, CC0; VPALIGNR $8, CC1, CC1, CC1; VPALIGNR $8, CC2, CC2, CC2; VPALIGNR $8, CC3, CC3, CC3 - VPALIGNR $4, DD0, DD0, DD0; VPALIGNR $4, DD1, DD1, DD1; VPALIGNR $4, DD2, DD2, DD2; VPALIGNR $4, DD3, DD3, DD3 - - DECQ itr1 - JG sealAVX2Tail512LoopA - DECQ itr2 - JGE sealAVX2Tail512LoopB - - VPADDD ·chacha20Constants<>(SB), AA0, AA0; VPADDD ·chacha20Constants<>(SB), AA1, AA1; VPADDD ·chacha20Constants<>(SB), AA2, AA2; VPADDD ·chacha20Constants<>(SB), AA3, AA3 - VPADDD state1StoreAVX2, BB0, BB0; VPADDD state1StoreAVX2, BB1, BB1; VPADDD state1StoreAVX2, BB2, BB2; VPADDD state1StoreAVX2, BB3, BB3 - VPADDD state2StoreAVX2, CC0, CC0; VPADDD state2StoreAVX2, CC1, CC1; VPADDD state2StoreAVX2, CC2, CC2; VPADDD state2StoreAVX2, CC3, CC3 - VPADDD ctr0StoreAVX2, DD0, DD0; VPADDD ctr1StoreAVX2, DD1, DD1; VPADDD ctr2StoreAVX2, DD2, DD2; VPADDD ctr3StoreAVX2, DD3, DD3 - VMOVDQA CC3, tmpStoreAVX2 - VPERM2I128 $0x02, AA0, BB0, CC3 - VPXOR (0*32)(inp), CC3, CC3 - VMOVDQU CC3, (0*32)(oup) - VPERM2I128 $0x02, CC0, DD0, CC3 - VPXOR (1*32)(inp), CC3, CC3 - VMOVDQU CC3, (1*32)(oup) - VPERM2I128 $0x13, AA0, BB0, CC3 - VPXOR (2*32)(inp), CC3, CC3 - VMOVDQU CC3, (2*32)(oup) - VPERM2I128 $0x13, CC0, DD0, CC3 - VPXOR (3*32)(inp), CC3, CC3 - VMOVDQU CC3, (3*32)(oup) - - VPERM2I128 $0x02, AA1, BB1, AA0 - VPERM2I128 $0x02, CC1, DD1, BB0 - VPERM2I128 $0x13, AA1, BB1, CC0 - VPERM2I128 $0x13, CC1, DD1, DD0 - VPXOR (4*32)(inp), AA0, AA0; VPXOR (5*32)(inp), BB0, BB0; VPXOR (6*32)(inp), CC0, CC0; VPXOR (7*32)(inp), DD0, DD0 - VMOVDQU AA0, (4*32)(oup); VMOVDQU BB0, (5*32)(oup); VMOVDQU CC0, (6*32)(oup); VMOVDQU DD0, (7*32)(oup) - - VPERM2I128 $0x02, AA2, BB2, AA0 - VPERM2I128 $0x02, CC2, DD2, BB0 - VPERM2I128 $0x13, AA2, BB2, CC0 - VPERM2I128 $0x13, CC2, DD2, DD0 - VPXOR (8*32)(inp), AA0, AA0; VPXOR (9*32)(inp), BB0, BB0; VPXOR (10*32)(inp), CC0, CC0; VPXOR (11*32)(inp), DD0, DD0 - VMOVDQU AA0, (8*32)(oup); VMOVDQU BB0, (9*32)(oup); VMOVDQU CC0, (10*32)(oup); VMOVDQU DD0, (11*32)(oup) - - MOVQ $384, itr1 - LEAQ 384(inp), inp - SUBQ $384, inl - VPERM2I128 $0x02, AA3, BB3, AA0 - VPERM2I128 $0x02, tmpStoreAVX2, DD3, BB0 - VPERM2I128 $0x13, AA3, BB3, CC0 - VPERM2I128 $0x13, tmpStoreAVX2, DD3, DD0 - - JMP sealAVX2SealHash + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + ADDQ (DI), R10 + ADCQ 8(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + VPALIGNR $0x04, Y14, Y14, Y14 + VPALIGNR $0x04, Y9, Y9, Y9 + VPALIGNR $0x04, Y10, Y10, Y10 + VPALIGNR $0x04, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x0c, Y4, Y4, Y4 + VPALIGNR $0x0c, Y1, Y1, Y1 + VPALIGNR $0x0c, Y2, Y2, Y2 + VPALIGNR $0x0c, Y3, Y3, Y3 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol16<>+0(SB), Y4, Y4 + VPSHUFB ·rol16<>+0(SB), Y1, Y1 + VPSHUFB ·rol16<>+0(SB), Y2, Y2 + VPSHUFB ·rol16<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + ADDQ 16(DI), R10 + ADCQ 24(DI), R11 + ADCQ $0x01, R12 + MOVQ (BP), DX + MOVQ DX, R15 + MULXQ R10, R13, R14 + IMULQ R12, R15 + MULXQ R11, AX, DX + ADDQ AX, R14 + ADCQ DX, R15 + MOVQ 8(BP), DX + MULXQ R10, R10, AX + ADDQ R10, R14 + MULXQ R11, R11, R8 + ADCQ R11, R15 + ADCQ $0x00, R8 + IMULQ R12, DX + ADDQ AX, R15 + ADCQ DX, R8 + MOVQ R13, R10 + MOVQ R14, R11 + MOVQ R15, R12 + ANDQ $0x03, R12 + MOVQ R15, R13 + ANDQ $-4, R13 + MOVQ R8, R14 + SHRQ $0x02, R8, R15 + SHRQ $0x02, R8 + ADDQ R13, R10 + ADCQ R14, R11 + ADCQ $0x00, R12 + ADDQ R15, R10 + ADCQ R8, R11 + ADCQ $0x00, R12 + LEAQ 32(DI), DI + VMOVDQA Y15, 224(BP) + VPSLLD $0x0c, Y14, Y15 + VPSRLD $0x14, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x0c, Y9, Y15 + VPSRLD $0x14, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x0c, Y10, Y15 + VPSRLD $0x14, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x0c, Y11, Y15 + VPSRLD $0x14, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + VPADDD Y14, Y0, Y0 + VPADDD Y9, Y5, Y5 + VPADDD Y10, Y6, Y6 + VPADDD Y11, Y7, Y7 + VPXOR Y0, Y4, Y4 + VPXOR Y5, Y1, Y1 + VPXOR Y6, Y2, Y2 + VPXOR Y7, Y3, Y3 + VPSHUFB ·rol8<>+0(SB), Y4, Y4 + VPSHUFB ·rol8<>+0(SB), Y1, Y1 + VPSHUFB ·rol8<>+0(SB), Y2, Y2 + VPSHUFB ·rol8<>+0(SB), Y3, Y3 + VPADDD Y4, Y12, Y12 + VPADDD Y1, Y13, Y13 + VPADDD Y2, Y8, Y8 + VPADDD Y3, Y15, Y15 + VPXOR Y12, Y14, Y14 + VPXOR Y13, Y9, Y9 + VPXOR Y8, Y10, Y10 + VPXOR Y15, Y11, Y11 + VMOVDQA Y15, 224(BP) + VPSLLD $0x07, Y14, Y15 + VPSRLD $0x19, Y14, Y14 + VPXOR Y15, Y14, Y14 + VPSLLD $0x07, Y9, Y15 + VPSRLD $0x19, Y9, Y9 + VPXOR Y15, Y9, Y9 + VPSLLD $0x07, Y10, Y15 + VPSRLD $0x19, Y10, Y10 + VPXOR Y15, Y10, Y10 + VPSLLD $0x07, Y11, Y15 + VPSRLD $0x19, Y11, Y11 + VPXOR Y15, Y11, Y11 + VMOVDQA 224(BP), Y15 + VPALIGNR $0x0c, Y14, Y14, Y14 + VPALIGNR $0x0c, Y9, Y9, Y9 + VPALIGNR $0x0c, Y10, Y10, Y10 + VPALIGNR $0x0c, Y11, Y11, Y11 + VPALIGNR $0x08, Y12, Y12, Y12 + VPALIGNR $0x08, Y13, Y13, Y13 + VPALIGNR $0x08, Y8, Y8, Y8 + VPALIGNR $0x08, Y15, Y15, Y15 + VPALIGNR $0x04, Y4, Y4, Y4 + VPALIGNR $0x04, Y1, Y1, Y1 + VPALIGNR $0x04, Y2, Y2, Y2 + VPALIGNR $0x04, Y3, Y3, Y3 + DECQ CX + JG sealAVX2Tail512LoopA + DECQ R9 + JGE sealAVX2Tail512LoopB + VPADDD ·chacha20Constants<>+0(SB), Y0, Y0 + VPADDD ·chacha20Constants<>+0(SB), Y5, Y5 + VPADDD ·chacha20Constants<>+0(SB), Y6, Y6 + VPADDD ·chacha20Constants<>+0(SB), Y7, Y7 + VPADDD 32(BP), Y14, Y14 + VPADDD 32(BP), Y9, Y9 + VPADDD 32(BP), Y10, Y10 + VPADDD 32(BP), Y11, Y11 + VPADDD 64(BP), Y12, Y12 + VPADDD 64(BP), Y13, Y13 + VPADDD 64(BP), Y8, Y8 + VPADDD 64(BP), Y15, Y15 + VPADDD 96(BP), Y4, Y4 + VPADDD 128(BP), Y1, Y1 + VPADDD 160(BP), Y2, Y2 + VPADDD 192(BP), Y3, Y3 + VMOVDQA Y15, 224(BP) + VPERM2I128 $0x02, Y0, Y14, Y15 + VPXOR (SI), Y15, Y15 + VMOVDQU Y15, (DI) + VPERM2I128 $0x02, Y12, Y4, Y15 + VPXOR 32(SI), Y15, Y15 + VMOVDQU Y15, 32(DI) + VPERM2I128 $0x13, Y0, Y14, Y15 + VPXOR 64(SI), Y15, Y15 + VMOVDQU Y15, 64(DI) + VPERM2I128 $0x13, Y12, Y4, Y15 + VPXOR 96(SI), Y15, Y15 + VMOVDQU Y15, 96(DI) + VPERM2I128 $0x02, Y5, Y9, Y0 + VPERM2I128 $0x02, Y13, Y1, Y14 + VPERM2I128 $0x13, Y5, Y9, Y12 + VPERM2I128 $0x13, Y13, Y1, Y4 + VPXOR 128(SI), Y0, Y0 + VPXOR 160(SI), Y14, Y14 + VPXOR 192(SI), Y12, Y12 + VPXOR 224(SI), Y4, Y4 + VMOVDQU Y0, 128(DI) + VMOVDQU Y14, 160(DI) + VMOVDQU Y12, 192(DI) + VMOVDQU Y4, 224(DI) + VPERM2I128 $0x02, Y6, Y10, Y0 + VPERM2I128 $0x02, Y8, Y2, Y14 + VPERM2I128 $0x13, Y6, Y10, Y12 + VPERM2I128 $0x13, Y8, Y2, Y4 + VPXOR 256(SI), Y0, Y0 + VPXOR 288(SI), Y14, Y14 + VPXOR 320(SI), Y12, Y12 + VPXOR 352(SI), Y4, Y4 + VMOVDQU Y0, 256(DI) + VMOVDQU Y14, 288(DI) + VMOVDQU Y12, 320(DI) + VMOVDQU Y4, 352(DI) + MOVQ $0x00000180, CX + LEAQ 384(SI), SI + SUBQ $0x00000180, BX + VPERM2I128 $0x02, Y7, Y11, Y0 + VPERM2I128 $0x02, 224(BP), Y3, Y14 + VPERM2I128 $0x13, Y7, Y11, Y12 + VPERM2I128 $0x13, 224(BP), Y3, Y4 + JMP sealAVX2SealHash go_cc119ee391575fb11bdefaeac7155bcb9c2652be_src_cmd_compile_internal_noder_doc.go.test000066400000000000000000000637441516001707200351210ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit cc119ee391575fb11bdefaeac7155bcb9c2652be file src/cmd/compile/internal/noder/doc.go -- x -- // Copyright 2025 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. /* The Unified IR (UIR) format is implicitly defined by the package noder. At the highest level, a package encoded in UIR follows the grammar below. File = Header Payload fingerprint . Header = version [ flags ] sectionEnds elementEnds . version = uint32 . // used for backward compatibility flags = uint32 . // feature flags used across versions sectionEnds = [10]uint32 . // defines section boundaries elementEnds = []uint32 . // defines element boundaries fingerprint = [8]byte . // sha256 fingerprint The payload is a series of sections. Each section has a kind which determines its index in the series. SectionKind = Uint64 . Payload = SectionString SectionMeta SectionPosBase SectionPkg SectionName SectionType // TODO(markfreeman) Define. SectionObj SectionObjExt // TODO(markfreeman) Define. SectionObjDict // TODO(markfreeman) Define. SectionBody // TODO(markfreeman) Define. . # Sections A section is a series of elements of a type determined by the section's kind. Go constructs are mapped onto one or more elements with possibly different types; in that case, the elements are in different sections. Elements are accessed using an element index relative to the start of the section. RelElemIdx = Uint64 . ## String Section String values are stored as elements in the string section. Elements outside the string section access string values by reference. SectionString = { String } . ## Meta Section The meta section provides fundamental information for a package. It contains exactly two elements — a public root and a private root. SectionMeta = PublicRoot PrivateRoot // TODO(markfreeman): Define. . The public root element identifies the package and provides references for all exported objects it contains. PublicRoot = RefTable [ Sync ] PkgRef [ HasInit ] ObjectRefCount // TODO(markfreeman): Define. { ObjectRef } // TODO(markfreeman): Define. . HasInit = Bool . // Whether the package uses any // initialization functions. ## PosBase Section This section provides position information. It is a series of PosBase elements. SectionPosBase = { PosBase } . A base is either a file base or line base (produced by a line directive). Every base has a position, line, and column; these are constant for file bases and hence not encoded. PosBase = RefTable [ Sync ] StringRef // the (absolute) file name for the base Bool // true if a file base, else a line base // The below is ommitted for file bases. [ Pos Uint64 // line Uint64 ] // column . A source position Pos represents a file-absolute (line, column) pair and a PosBase indicating the position Pos is relative to. Positions without a PosBase have no line or column. Pos = [ Sync ] Bool // true if the position has a base // The below is ommitted if the position has no base. [ Ref[PosBase] Uint64 // line Uint64 ] // column . ## Package Section The package section holds package information. It is a series of Pkg elements. SectionPkg = { Pkg } . A Pkg element contains a (path, name) pair and a series of imported packages. The below package paths have special meaning. +--------------+-----------------------------------+ | package path | indicates | +--------------+-----------------------------------+ | "" | the current package | | "builtin" | the fake builtin package | | "unsafe" | the compiler-known unsafe package | +--------------+-----------------------------------+ Pkg = RefTable [ Sync ] StringRef // path // The below is ommitted for the special package paths // "builtin" and "unsafe". [ StringRef // name Imports ] . Imports = Uint64 // the number of declared imports { PkgRef } // references to declared imports . Note, a PkgRef is *not* equivalent to Ref[Pkg] due to an extra marker. PkgRef = [ Sync ] Ref[Pkg] . ## Object Sections Information about an object (e.g. variable, function, type name, etc.) is split into multiple elements in different sections. Those elements have the same section-relative element index. ### Name Section The name section holds a series of names. SectionName = { Name } . Names are elements holding qualified identifiers and type information for objects. Name = RefTable [ Sync ] [ Sync ] PkgRef // the object's package StringRef // the object's package-local name [ Sync ] Uint64 // the object's type (e.g. Var, Func, etc.) . ### Definition Section The definition section holds definitions for objects defined by the target package; it does not contain definitions for imported objects. SectionObj = { ObjectDef } . Object definitions can be one of several formats. To determine the correct format, the name section must be referenced for the object's type. ObjectDef = ObjectDefConst // TODO(markfreeman) Define. | ObjectDefFunc // TODO(markfreeman) Define. | ObjectDefAlias // TODO(markfreeman) Define. | ObjectDefNamedType // TODO(markfreeman) Define. | ObjectDefVar // TODO(markfreeman) Define. . # References A reference table precedes every element. Each entry in the table contains a (section, index) pair denoting the location of the referenced element. RefTable = [ Sync ] Uint64 // the number of table entries { RefTableEntry } . RefTableEntry = [ Sync ] SectionKind RelElemIdx . Elements encode references to other elements as an index in the reference table — not the location of the referenced element directly. // TODO(markfreeman): Rename to RefUse. UseReloc = [ Sync ] RelElemIdx . # Primitives Primitive encoding is handled separately by the pkgbits package. Check there for definitions of the below productions. * Bool * Int64 * Uint64 * String * Ref[T] * Sync */ package noder -- y -- // Copyright 2025 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. /* The Unified IR (UIR) format is implicitly defined by the package noder. At the highest level, a package encoded in UIR follows the grammar below. File = Header Payload fingerprint . Header = version [ flags ] sectionEnds elementEnds . version = uint32 . // used for backward compatibility flags = uint32 . // feature flags used across versions sectionEnds = [10]uint32 . // defines section boundaries elementEnds = []uint32 . // defines element boundaries fingerprint = [8]byte . // sha256 fingerprint The payload is a series of sections. Each section has a kind which determines its index in the series. SectionKind = Uint64 . Payload = SectionString SectionMeta SectionPosBase SectionPkg SectionName SectionType SectionObj SectionObjExt // TODO(markfreeman) Define. SectionObjDict // TODO(markfreeman) Define. SectionBody // TODO(markfreeman) Define. . # Sections A section is a series of elements of a type determined by the section's kind. Go constructs are mapped onto one or more elements with possibly different types; in that case, the elements are in different sections. Elements are accessed using an element index relative to the start of the section. RelElemIdx = Uint64 . ## String Section String values are stored as elements in the string section. Elements outside the string section access string values by reference. SectionString = { String } . ## Meta Section The meta section provides fundamental information for a package. It contains exactly two elements — a public root and a private root. SectionMeta = PublicRoot PrivateRoot // TODO(markfreeman): Define. . The public root element identifies the package and provides references for all exported objects it contains. PublicRoot = RefTable [ Sync ] PkgRef [ HasInit ] ObjectRefCount // TODO(markfreeman): Define. { ObjectRef } // TODO(markfreeman): Define. . HasInit = Bool . // Whether the package uses any // initialization functions. ## PosBase Section This section provides position information. It is a series of PosBase elements. SectionPosBase = { PosBase } . A base is either a file base or line base (produced by a line directive). Every base has a position, line, and column; these are constant for file bases and hence not encoded. PosBase = RefTable [ Sync ] StringRef // the (absolute) file name for the base Bool // true if a file base, else a line base // The below is ommitted for file bases. [ Pos Uint64 // line Uint64 ] // column . A source position Pos represents a file-absolute (line, column) pair and a PosBase indicating the position Pos is relative to. Positions without a PosBase have no line or column. Pos = [ Sync ] Bool // true if the position has a base // The below is ommitted if the position has no base. [ Ref[PosBase] Uint64 // line Uint64 ] // column . ## Package Section The package section holds package information. It is a series of Pkg elements. SectionPkg = { Pkg } . A Pkg element contains a (path, name) pair and a series of imported packages. The below package paths have special meaning. +--------------+-----------------------------------+ | package path | indicates | +--------------+-----------------------------------+ | "" | the current package | | "builtin" | the fake builtin package | | "unsafe" | the compiler-known unsafe package | +--------------+-----------------------------------+ Pkg = RefTable [ Sync ] StringRef // path // The below is ommitted for the special package paths // "builtin" and "unsafe". [ StringRef // name Imports ] . Imports = Uint64 // the number of declared imports { PkgRef } // references to declared imports . Note, a PkgRef is *not* equivalent to Ref[Pkg] due to an extra marker. PkgRef = [ Sync ] Ref[Pkg] . ## Type Section The type section is a series of type definition elements. SectionType = { TypeDef } . A type definition can be in one of several formats, which are identified by their TypeSpec code. TypeDef = RefTable [ Sync ] [ Sync ] Uint64 // denotes which TypeSpec to use TypeSpec . TypeSpec = TypeSpecBasic // TODO(markfreeman): Define. | TypeSpecNamed // TODO(markfreeman): Define. | TypeSpecPointer // TODO(markfreeman): Define. | TypeSpecSlice // TODO(markfreeman): Define. | TypeSpecArray // TODO(markfreeman): Define. | TypeSpecChan // TODO(markfreeman): Define. | TypeSpecMap // TODO(markfreeman): Define. | TypeSpecSignature // TODO(markfreeman): Define. | TypeSpecStruct // TODO(markfreeman): Define. | TypeSpecInterface // TODO(markfreeman): Define. | TypeSpecUnion // TODO(markfreeman): Define. | TypeSpecTypeParam // TODO(markfreeman): Define. . // TODO(markfreeman): Document the reader dictionary once we understand it more. To use a type elsewhere, a TypeUse is encoded. TypeUse = [ Sync ] Bool // whether it is a derived type [ Uint64 ] // if derived, an index into the reader dictionary [ Ref[TypeDef] ] // else, a reference to the type . ## Object Sections Information about an object (e.g. variable, function, type name, etc.) is split into multiple elements in different sections. Those elements have the same section-relative element index. ### Name Section The name section holds a series of names. SectionName = { Name } . Names are elements holding qualified identifiers and type information for objects. Name = RefTable [ Sync ] [ Sync ] PkgRef // the object's package StringRef // the object's package-local name [ Sync ] Uint64 // the object's type (e.g. Var, Func, etc.) . ### Definition Section The definition section holds definitions for objects defined by the target package; it does not contain definitions for imported objects. SectionObj = { ObjectDef } . Object definitions can be in one of several formats. To determine the correct format, the name section must be referenced; it contains a code indicating the object's type. ObjectDef = RefTable [ Sync ] ObjectSpec . ObjectSpec = ObjectSpecConst // TODO(markfreeman) Define. | ObjectSpecFunc // TODO(markfreeman) Define. | ObjectSpecAlias // TODO(markfreeman) Define. | ObjectSpecNamedType // TODO(markfreeman) Define. | ObjectSpecVar // TODO(markfreeman) Define. . To use an object definition elsewhere, an ObjectUse is encoded. ObjectUse = [ Sync ] [ Bool ] Ref[ObjectDef] Uint64 // the number of type arguments { TypeUse } // references to the type arguments . # References A reference table precedes every element. Each entry in the table contains a (section, index) pair denoting the location of the referenced element. RefTable = [ Sync ] Uint64 // the number of table entries { RefTableEntry } . RefTableEntry = [ Sync ] SectionKind RelElemIdx . Elements encode references to other elements as an index in the reference table — not the location of the referenced element directly. RefTableIdx = Uint64 . To do this, the Ref[T] primitive is used as below; note that this is the same shape as provided by package pkgbits, just with new interpretation applied. Ref[T] = [ Sync ] RefTableIdx // the Uint64 . # Primitives Primitive encoding is handled separately by the pkgbits package. Check there for definitions of the below productions. * Bool * Int64 * Uint64 * String * Ref[T] * Sync */ package noder -- diff -- @@ -26,7 +26,7 @@ SectionPosBase SectionPkg SectionName - SectionType // TODO(markfreeman) Define. + SectionType SectionObj SectionObjExt // TODO(markfreeman) Define. SectionObjDict // TODO(markfreeman) Define. @@ -137,6 +137,44 @@ Ref[Pkg] . +## Type Section +The type section is a series of type definition elements. + + SectionType = { TypeDef } . + +A type definition can be in one of several formats, which are identified +by their TypeSpec code. + + TypeDef = RefTable + [ Sync ] + [ Sync ] + Uint64 // denotes which TypeSpec to use + TypeSpec + . + + TypeSpec = TypeSpecBasic // TODO(markfreeman): Define. + | TypeSpecNamed // TODO(markfreeman): Define. + | TypeSpecPointer // TODO(markfreeman): Define. + | TypeSpecSlice // TODO(markfreeman): Define. + | TypeSpecArray // TODO(markfreeman): Define. + | TypeSpecChan // TODO(markfreeman): Define. + | TypeSpecMap // TODO(markfreeman): Define. + | TypeSpecSignature // TODO(markfreeman): Define. + | TypeSpecStruct // TODO(markfreeman): Define. + | TypeSpecInterface // TODO(markfreeman): Define. + | TypeSpecUnion // TODO(markfreeman): Define. + | TypeSpecTypeParam // TODO(markfreeman): Define. + . + +// TODO(markfreeman): Document the reader dictionary once we understand it more. +To use a type elsewhere, a TypeUse is encoded. + + TypeUse = [ Sync ] + Bool // whether it is a derived type + [ Uint64 ] // if derived, an index into the reader dictionary + [ Ref[TypeDef] ] // else, a reference to the type + . + ## Object Sections Information about an object (e.g. variable, function, type name, etc.) is split into multiple elements in different sections. Those elements @@ -160,21 +198,35 @@ . ### Definition Section -The definition section holds definitions for objects defined by the -target package; it does not contain definitions for imported objects. +The definition section holds definitions for objects defined by the target +package; it does not contain definitions for imported objects. SectionObj = { ObjectDef } . -Object definitions can be one of several formats. To determine the -correct format, the name section must be referenced for the object's -type. +Object definitions can be in one of several formats. To determine the correct +format, the name section must be referenced; it contains a code indicating +the object's type. - ObjectDef = ObjectDefConst // TODO(markfreeman) Define. - | ObjectDefFunc // TODO(markfreeman) Define. - | ObjectDefAlias // TODO(markfreeman) Define. - | ObjectDefNamedType // TODO(markfreeman) Define. - | ObjectDefVar // TODO(markfreeman) Define. + ObjectDef = RefTable + [ Sync ] + ObjectSpec . + + ObjectSpec = ObjectSpecConst // TODO(markfreeman) Define. + | ObjectSpecFunc // TODO(markfreeman) Define. + | ObjectSpecAlias // TODO(markfreeman) Define. + | ObjectSpecNamedType // TODO(markfreeman) Define. + | ObjectSpecVar // TODO(markfreeman) Define. + . + +To use an object definition elsewhere, an ObjectUse is encoded. + + ObjectUse = [ Sync ] + [ Bool ] + Ref[ObjectDef] + Uint64 // the number of type arguments + { TypeUse } // references to the type arguments + . # References A reference table precedes every element. Each entry in the table @@ -193,10 +245,15 @@ Elements encode references to other elements as an index in the reference table — not the location of the referenced element directly. - // TODO(markfreeman): Rename to RefUse. - UseReloc = [ Sync ] - RelElemIdx - . + RefTableIdx = Uint64 . + +To do this, the Ref[T] primitive is used as below; note that this is +the same shape as provided by package pkgbits, just with new +interpretation applied. + + Ref[T] = [ Sync ] + RefTableIdx // the Uint64 + . # Primitives Primitive encoding is handled separately by the pkgbits package. Check -- diff -- # indent-heuristic: true @@ -26,7 +26,7 @@ SectionPosBase SectionPkg SectionName - SectionType // TODO(markfreeman) Define. + SectionType SectionObj SectionObjExt // TODO(markfreeman) Define. SectionObjDict // TODO(markfreeman) Define. @@ -137,6 +137,44 @@ Ref[Pkg] . +## Type Section +The type section is a series of type definition elements. + + SectionType = { TypeDef } . + +A type definition can be in one of several formats, which are identified +by their TypeSpec code. + + TypeDef = RefTable + [ Sync ] + [ Sync ] + Uint64 // denotes which TypeSpec to use + TypeSpec + . + + TypeSpec = TypeSpecBasic // TODO(markfreeman): Define. + | TypeSpecNamed // TODO(markfreeman): Define. + | TypeSpecPointer // TODO(markfreeman): Define. + | TypeSpecSlice // TODO(markfreeman): Define. + | TypeSpecArray // TODO(markfreeman): Define. + | TypeSpecChan // TODO(markfreeman): Define. + | TypeSpecMap // TODO(markfreeman): Define. + | TypeSpecSignature // TODO(markfreeman): Define. + | TypeSpecStruct // TODO(markfreeman): Define. + | TypeSpecInterface // TODO(markfreeman): Define. + | TypeSpecUnion // TODO(markfreeman): Define. + | TypeSpecTypeParam // TODO(markfreeman): Define. + . + +// TODO(markfreeman): Document the reader dictionary once we understand it more. +To use a type elsewhere, a TypeUse is encoded. + + TypeUse = [ Sync ] + Bool // whether it is a derived type + [ Uint64 ] // if derived, an index into the reader dictionary + [ Ref[TypeDef] ] // else, a reference to the type + . + ## Object Sections Information about an object (e.g. variable, function, type name, etc.) is split into multiple elements in different sections. Those elements @@ -160,22 +198,36 @@ . ### Definition Section -The definition section holds definitions for objects defined by the -target package; it does not contain definitions for imported objects. +The definition section holds definitions for objects defined by the target +package; it does not contain definitions for imported objects. SectionObj = { ObjectDef } . -Object definitions can be one of several formats. To determine the -correct format, the name section must be referenced for the object's -type. +Object definitions can be in one of several formats. To determine the correct +format, the name section must be referenced; it contains a code indicating +the object's type. - ObjectDef = ObjectDefConst // TODO(markfreeman) Define. - | ObjectDefFunc // TODO(markfreeman) Define. - | ObjectDefAlias // TODO(markfreeman) Define. - | ObjectDefNamedType // TODO(markfreeman) Define. - | ObjectDefVar // TODO(markfreeman) Define. + ObjectDef = RefTable + [ Sync ] + ObjectSpec . + ObjectSpec = ObjectSpecConst // TODO(markfreeman) Define. + | ObjectSpecFunc // TODO(markfreeman) Define. + | ObjectSpecAlias // TODO(markfreeman) Define. + | ObjectSpecNamedType // TODO(markfreeman) Define. + | ObjectSpecVar // TODO(markfreeman) Define. + . + +To use an object definition elsewhere, an ObjectUse is encoded. + + ObjectUse = [ Sync ] + [ Bool ] + Ref[ObjectDef] + Uint64 // the number of type arguments + { TypeUse } // references to the type arguments + . + # References A reference table precedes every element. Each entry in the table contains a (section, index) pair denoting the location of the @@ -193,10 +245,15 @@ Elements encode references to other elements as an index in the reference table — not the location of the referenced element directly. - // TODO(markfreeman): Rename to RefUse. - UseReloc = [ Sync ] - RelElemIdx - . + RefTableIdx = Uint64 . + +To do this, the Ref[T] primitive is used as below; note that this is +the same shape as provided by package pkgbits, just with new +interpretation applied. + + Ref[T] = [ Sync ] + RefTableIdx // the Uint64 + . # Primitives Primitive encoding is handled separately by the pkgbits package. Check go_cedf5008a84d3726f98fac551a4016bf0a91157f_src_cmd_compile_internal_ssa_rewriteAMD64.go.test000066400000000000000000066003421516001707200356340ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit cedf5008a84d3726f98fac551a4016bf0a91157f file src/cmd/compile/internal/ssa/rewriteAMD64.go -- x -- // Code generated from _gen/AMD64.rules using 'go generate'; DO NOT EDIT. package ssa import "internal/buildcfg" import "math" import "cmd/internal/obj" import "cmd/compile/internal/types" func rewriteValueAMD64(v *Value) bool { switch v.Op { case OpAMD64ADCQ: return rewriteValueAMD64_OpAMD64ADCQ(v) case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst(v) case OpAMD64ADDL: return rewriteValueAMD64_OpAMD64ADDL(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst(v) case OpAMD64ADDLconstmodify: return rewriteValueAMD64_OpAMD64ADDLconstmodify(v) case OpAMD64ADDLload: return rewriteValueAMD64_OpAMD64ADDLload(v) case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify(v) case OpAMD64ADDQ: return rewriteValueAMD64_OpAMD64ADDQ(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry(v) case OpAMD64ADDQconst: return rewriteValueAMD64_OpAMD64ADDQconst(v) case OpAMD64ADDQconstmodify: return rewriteValueAMD64_OpAMD64ADDQconstmodify(v) case OpAMD64ADDQload: return rewriteValueAMD64_OpAMD64ADDQload(v) case OpAMD64ADDQmodify: return rewriteValueAMD64_OpAMD64ADDQmodify(v) case OpAMD64ADDSD: return rewriteValueAMD64_OpAMD64ADDSD(v) case OpAMD64ADDSDload: return rewriteValueAMD64_OpAMD64ADDSDload(v) case OpAMD64ADDSS: return rewriteValueAMD64_OpAMD64ADDSS(v) case OpAMD64ADDSSload: return rewriteValueAMD64_OpAMD64ADDSSload(v) case OpAMD64ANDL: return rewriteValueAMD64_OpAMD64ANDL(v) case OpAMD64ANDLconst: return rewriteValueAMD64_OpAMD64ANDLconst(v) case OpAMD64ANDLconstmodify: return rewriteValueAMD64_OpAMD64ANDLconstmodify(v) case OpAMD64ANDLload: return rewriteValueAMD64_OpAMD64ANDLload(v) case OpAMD64ANDLmodify: return rewriteValueAMD64_OpAMD64ANDLmodify(v) case OpAMD64ANDNL: return rewriteValueAMD64_OpAMD64ANDNL(v) case OpAMD64ANDNQ: return rewriteValueAMD64_OpAMD64ANDNQ(v) case OpAMD64ANDQ: return rewriteValueAMD64_OpAMD64ANDQ(v) case OpAMD64ANDQconst: return rewriteValueAMD64_OpAMD64ANDQconst(v) case OpAMD64ANDQconstmodify: return rewriteValueAMD64_OpAMD64ANDQconstmodify(v) case OpAMD64ANDQload: return rewriteValueAMD64_OpAMD64ANDQload(v) case OpAMD64ANDQmodify: return rewriteValueAMD64_OpAMD64ANDQmodify(v) case OpAMD64BSFQ: return rewriteValueAMD64_OpAMD64BSFQ(v) case OpAMD64BSWAPL: return rewriteValueAMD64_OpAMD64BSWAPL(v) case OpAMD64BSWAPQ: return rewriteValueAMD64_OpAMD64BSWAPQ(v) case OpAMD64BTCLconst: return rewriteValueAMD64_OpAMD64BTCLconst(v) case OpAMD64BTCQconst: return rewriteValueAMD64_OpAMD64BTCQconst(v) case OpAMD64BTLconst: return rewriteValueAMD64_OpAMD64BTLconst(v) case OpAMD64BTQconst: return rewriteValueAMD64_OpAMD64BTQconst(v) case OpAMD64BTRLconst: return rewriteValueAMD64_OpAMD64BTRLconst(v) case OpAMD64BTRQconst: return rewriteValueAMD64_OpAMD64BTRQconst(v) case OpAMD64BTSLconst: return rewriteValueAMD64_OpAMD64BTSLconst(v) case OpAMD64BTSQconst: return rewriteValueAMD64_OpAMD64BTSQconst(v) case OpAMD64CMOVLCC: return rewriteValueAMD64_OpAMD64CMOVLCC(v) case OpAMD64CMOVLCS: return rewriteValueAMD64_OpAMD64CMOVLCS(v) case OpAMD64CMOVLEQ: return rewriteValueAMD64_OpAMD64CMOVLEQ(v) case OpAMD64CMOVLGE: return rewriteValueAMD64_OpAMD64CMOVLGE(v) case OpAMD64CMOVLGT: return rewriteValueAMD64_OpAMD64CMOVLGT(v) case OpAMD64CMOVLHI: return rewriteValueAMD64_OpAMD64CMOVLHI(v) case OpAMD64CMOVLLE: return rewriteValueAMD64_OpAMD64CMOVLLE(v) case OpAMD64CMOVLLS: return rewriteValueAMD64_OpAMD64CMOVLLS(v) case OpAMD64CMOVLLT: return rewriteValueAMD64_OpAMD64CMOVLLT(v) case OpAMD64CMOVLNE: return rewriteValueAMD64_OpAMD64CMOVLNE(v) case OpAMD64CMOVQCC: return rewriteValueAMD64_OpAMD64CMOVQCC(v) case OpAMD64CMOVQCS: return rewriteValueAMD64_OpAMD64CMOVQCS(v) case OpAMD64CMOVQEQ: return rewriteValueAMD64_OpAMD64CMOVQEQ(v) case OpAMD64CMOVQGE: return rewriteValueAMD64_OpAMD64CMOVQGE(v) case OpAMD64CMOVQGT: return rewriteValueAMD64_OpAMD64CMOVQGT(v) case OpAMD64CMOVQHI: return rewriteValueAMD64_OpAMD64CMOVQHI(v) case OpAMD64CMOVQLE: return rewriteValueAMD64_OpAMD64CMOVQLE(v) case OpAMD64CMOVQLS: return rewriteValueAMD64_OpAMD64CMOVQLS(v) case OpAMD64CMOVQLT: return rewriteValueAMD64_OpAMD64CMOVQLT(v) case OpAMD64CMOVQNE: return rewriteValueAMD64_OpAMD64CMOVQNE(v) case OpAMD64CMOVWCC: return rewriteValueAMD64_OpAMD64CMOVWCC(v) case OpAMD64CMOVWCS: return rewriteValueAMD64_OpAMD64CMOVWCS(v) case OpAMD64CMOVWEQ: return rewriteValueAMD64_OpAMD64CMOVWEQ(v) case OpAMD64CMOVWGE: return rewriteValueAMD64_OpAMD64CMOVWGE(v) case OpAMD64CMOVWGT: return rewriteValueAMD64_OpAMD64CMOVWGT(v) case OpAMD64CMOVWHI: return rewriteValueAMD64_OpAMD64CMOVWHI(v) case OpAMD64CMOVWLE: return rewriteValueAMD64_OpAMD64CMOVWLE(v) case OpAMD64CMOVWLS: return rewriteValueAMD64_OpAMD64CMOVWLS(v) case OpAMD64CMOVWLT: return rewriteValueAMD64_OpAMD64CMOVWLT(v) case OpAMD64CMOVWNE: return rewriteValueAMD64_OpAMD64CMOVWNE(v) case OpAMD64CMPB: return rewriteValueAMD64_OpAMD64CMPB(v) case OpAMD64CMPBconst: return rewriteValueAMD64_OpAMD64CMPBconst(v) case OpAMD64CMPBconstload: return rewriteValueAMD64_OpAMD64CMPBconstload(v) case OpAMD64CMPBload: return rewriteValueAMD64_OpAMD64CMPBload(v) case OpAMD64CMPL: return rewriteValueAMD64_OpAMD64CMPL(v) case OpAMD64CMPLconst: return rewriteValueAMD64_OpAMD64CMPLconst(v) case OpAMD64CMPLconstload: return rewriteValueAMD64_OpAMD64CMPLconstload(v) case OpAMD64CMPLload: return rewriteValueAMD64_OpAMD64CMPLload(v) case OpAMD64CMPQ: return rewriteValueAMD64_OpAMD64CMPQ(v) case OpAMD64CMPQconst: return rewriteValueAMD64_OpAMD64CMPQconst(v) case OpAMD64CMPQconstload: return rewriteValueAMD64_OpAMD64CMPQconstload(v) case OpAMD64CMPQload: return rewriteValueAMD64_OpAMD64CMPQload(v) case OpAMD64CMPW: return rewriteValueAMD64_OpAMD64CMPW(v) case OpAMD64CMPWconst: return rewriteValueAMD64_OpAMD64CMPWconst(v) case OpAMD64CMPWconstload: return rewriteValueAMD64_OpAMD64CMPWconstload(v) case OpAMD64CMPWload: return rewriteValueAMD64_OpAMD64CMPWload(v) case OpAMD64CMPXCHGLlock: return rewriteValueAMD64_OpAMD64CMPXCHGLlock(v) case OpAMD64CMPXCHGQlock: return rewriteValueAMD64_OpAMD64CMPXCHGQlock(v) case OpAMD64DIVSD: return rewriteValueAMD64_OpAMD64DIVSD(v) case OpAMD64DIVSDload: return rewriteValueAMD64_OpAMD64DIVSDload(v) case OpAMD64DIVSS: return rewriteValueAMD64_OpAMD64DIVSS(v) case OpAMD64DIVSSload: return rewriteValueAMD64_OpAMD64DIVSSload(v) case OpAMD64HMULL: return rewriteValueAMD64_OpAMD64HMULL(v) case OpAMD64HMULLU: return rewriteValueAMD64_OpAMD64HMULLU(v) case OpAMD64HMULQ: return rewriteValueAMD64_OpAMD64HMULQ(v) case OpAMD64HMULQU: return rewriteValueAMD64_OpAMD64HMULQU(v) case OpAMD64LEAL: return rewriteValueAMD64_OpAMD64LEAL(v) case OpAMD64LEAL1: return rewriteValueAMD64_OpAMD64LEAL1(v) case OpAMD64LEAL2: return rewriteValueAMD64_OpAMD64LEAL2(v) case OpAMD64LEAL4: return rewriteValueAMD64_OpAMD64LEAL4(v) case OpAMD64LEAL8: return rewriteValueAMD64_OpAMD64LEAL8(v) case OpAMD64LEAQ: return rewriteValueAMD64_OpAMD64LEAQ(v) case OpAMD64LEAQ1: return rewriteValueAMD64_OpAMD64LEAQ1(v) case OpAMD64LEAQ2: return rewriteValueAMD64_OpAMD64LEAQ2(v) case OpAMD64LEAQ4: return rewriteValueAMD64_OpAMD64LEAQ4(v) case OpAMD64LEAQ8: return rewriteValueAMD64_OpAMD64LEAQ8(v) case OpAMD64MOVBELstore: return rewriteValueAMD64_OpAMD64MOVBELstore(v) case OpAMD64MOVBEQstore: return rewriteValueAMD64_OpAMD64MOVBEQstore(v) case OpAMD64MOVBEWstore: return rewriteValueAMD64_OpAMD64MOVBEWstore(v) case OpAMD64MOVBQSX: return rewriteValueAMD64_OpAMD64MOVBQSX(v) case OpAMD64MOVBQSXload: return rewriteValueAMD64_OpAMD64MOVBQSXload(v) case OpAMD64MOVBQZX: return rewriteValueAMD64_OpAMD64MOVBQZX(v) case OpAMD64MOVBatomicload: return rewriteValueAMD64_OpAMD64MOVBatomicload(v) case OpAMD64MOVBload: return rewriteValueAMD64_OpAMD64MOVBload(v) case OpAMD64MOVBstore: return rewriteValueAMD64_OpAMD64MOVBstore(v) case OpAMD64MOVBstoreconst: return rewriteValueAMD64_OpAMD64MOVBstoreconst(v) case OpAMD64MOVLQSX: return rewriteValueAMD64_OpAMD64MOVLQSX(v) case OpAMD64MOVLQSXload: return rewriteValueAMD64_OpAMD64MOVLQSXload(v) case OpAMD64MOVLQZX: return rewriteValueAMD64_OpAMD64MOVLQZX(v) case OpAMD64MOVLatomicload: return rewriteValueAMD64_OpAMD64MOVLatomicload(v) case OpAMD64MOVLf2i: return rewriteValueAMD64_OpAMD64MOVLf2i(v) case OpAMD64MOVLi2f: return rewriteValueAMD64_OpAMD64MOVLi2f(v) case OpAMD64MOVLload: return rewriteValueAMD64_OpAMD64MOVLload(v) case OpAMD64MOVLstore: return rewriteValueAMD64_OpAMD64MOVLstore(v) case OpAMD64MOVLstoreconst: return rewriteValueAMD64_OpAMD64MOVLstoreconst(v) case OpAMD64MOVOload: return rewriteValueAMD64_OpAMD64MOVOload(v) case OpAMD64MOVOstore: return rewriteValueAMD64_OpAMD64MOVOstore(v) case OpAMD64MOVOstoreconst: return rewriteValueAMD64_OpAMD64MOVOstoreconst(v) case OpAMD64MOVQatomicload: return rewriteValueAMD64_OpAMD64MOVQatomicload(v) case OpAMD64MOVQf2i: return rewriteValueAMD64_OpAMD64MOVQf2i(v) case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f(v) case OpAMD64MOVQload: return rewriteValueAMD64_OpAMD64MOVQload(v) case OpAMD64MOVQstore: return rewriteValueAMD64_OpAMD64MOVQstore(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst(v) case OpAMD64MOVSDload: return rewriteValueAMD64_OpAMD64MOVSDload(v) case OpAMD64MOVSDstore: return rewriteValueAMD64_OpAMD64MOVSDstore(v) case OpAMD64MOVSSload: return rewriteValueAMD64_OpAMD64MOVSSload(v) case OpAMD64MOVSSstore: return rewriteValueAMD64_OpAMD64MOVSSstore(v) case OpAMD64MOVWQSX: return rewriteValueAMD64_OpAMD64MOVWQSX(v) case OpAMD64MOVWQSXload: return rewriteValueAMD64_OpAMD64MOVWQSXload(v) case OpAMD64MOVWQZX: return rewriteValueAMD64_OpAMD64MOVWQZX(v) case OpAMD64MOVWload: return rewriteValueAMD64_OpAMD64MOVWload(v) case OpAMD64MOVWstore: return rewriteValueAMD64_OpAMD64MOVWstore(v) case OpAMD64MOVWstoreconst: return rewriteValueAMD64_OpAMD64MOVWstoreconst(v) case OpAMD64MULL: return rewriteValueAMD64_OpAMD64MULL(v) case OpAMD64MULLconst: return rewriteValueAMD64_OpAMD64MULLconst(v) case OpAMD64MULQ: return rewriteValueAMD64_OpAMD64MULQ(v) case OpAMD64MULQconst: return rewriteValueAMD64_OpAMD64MULQconst(v) case OpAMD64MULSD: return rewriteValueAMD64_OpAMD64MULSD(v) case OpAMD64MULSDload: return rewriteValueAMD64_OpAMD64MULSDload(v) case OpAMD64MULSS: return rewriteValueAMD64_OpAMD64MULSS(v) case OpAMD64MULSSload: return rewriteValueAMD64_OpAMD64MULSSload(v) case OpAMD64NEGL: return rewriteValueAMD64_OpAMD64NEGL(v) case OpAMD64NEGQ: return rewriteValueAMD64_OpAMD64NEGQ(v) case OpAMD64NOTL: return rewriteValueAMD64_OpAMD64NOTL(v) case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ(v) case OpAMD64ORL: return rewriteValueAMD64_OpAMD64ORL(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst(v) case OpAMD64ORLconstmodify: return rewriteValueAMD64_OpAMD64ORLconstmodify(v) case OpAMD64ORLload: return rewriteValueAMD64_OpAMD64ORLload(v) case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify(v) case OpAMD64ORQ: return rewriteValueAMD64_OpAMD64ORQ(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst(v) case OpAMD64ORQconstmodify: return rewriteValueAMD64_OpAMD64ORQconstmodify(v) case OpAMD64ORQload: return rewriteValueAMD64_OpAMD64ORQload(v) case OpAMD64ORQmodify: return rewriteValueAMD64_OpAMD64ORQmodify(v) case OpAMD64ROLB: return rewriteValueAMD64_OpAMD64ROLB(v) case OpAMD64ROLBconst: return rewriteValueAMD64_OpAMD64ROLBconst(v) case OpAMD64ROLL: return rewriteValueAMD64_OpAMD64ROLL(v) case OpAMD64ROLLconst: return rewriteValueAMD64_OpAMD64ROLLconst(v) case OpAMD64ROLQ: return rewriteValueAMD64_OpAMD64ROLQ(v) case OpAMD64ROLQconst: return rewriteValueAMD64_OpAMD64ROLQconst(v) case OpAMD64ROLW: return rewriteValueAMD64_OpAMD64ROLW(v) case OpAMD64ROLWconst: return rewriteValueAMD64_OpAMD64ROLWconst(v) case OpAMD64RORB: return rewriteValueAMD64_OpAMD64RORB(v) case OpAMD64RORL: return rewriteValueAMD64_OpAMD64RORL(v) case OpAMD64RORQ: return rewriteValueAMD64_OpAMD64RORQ(v) case OpAMD64RORW: return rewriteValueAMD64_OpAMD64RORW(v) case OpAMD64SARB: return rewriteValueAMD64_OpAMD64SARB(v) case OpAMD64SARBconst: return rewriteValueAMD64_OpAMD64SARBconst(v) case OpAMD64SARL: return rewriteValueAMD64_OpAMD64SARL(v) case OpAMD64SARLconst: return rewriteValueAMD64_OpAMD64SARLconst(v) case OpAMD64SARQ: return rewriteValueAMD64_OpAMD64SARQ(v) case OpAMD64SARQconst: return rewriteValueAMD64_OpAMD64SARQconst(v) case OpAMD64SARW: return rewriteValueAMD64_OpAMD64SARW(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst(v) case OpAMD64SARXLload: return rewriteValueAMD64_OpAMD64SARXLload(v) case OpAMD64SARXQload: return rewriteValueAMD64_OpAMD64SARXQload(v) case OpAMD64SBBLcarrymask: return rewriteValueAMD64_OpAMD64SBBLcarrymask(v) case OpAMD64SBBQ: return rewriteValueAMD64_OpAMD64SBBQ(v) case OpAMD64SBBQcarrymask: return rewriteValueAMD64_OpAMD64SBBQcarrymask(v) case OpAMD64SBBQconst: return rewriteValueAMD64_OpAMD64SBBQconst(v) case OpAMD64SETA: return rewriteValueAMD64_OpAMD64SETA(v) case OpAMD64SETAE: return rewriteValueAMD64_OpAMD64SETAE(v) case OpAMD64SETAEstore: return rewriteValueAMD64_OpAMD64SETAEstore(v) case OpAMD64SETAstore: return rewriteValueAMD64_OpAMD64SETAstore(v) case OpAMD64SETB: return rewriteValueAMD64_OpAMD64SETB(v) case OpAMD64SETBE: return rewriteValueAMD64_OpAMD64SETBE(v) case OpAMD64SETBEstore: return rewriteValueAMD64_OpAMD64SETBEstore(v) case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore(v) case OpAMD64SETEQ: return rewriteValueAMD64_OpAMD64SETEQ(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore(v) case OpAMD64SETG: return rewriteValueAMD64_OpAMD64SETG(v) case OpAMD64SETGE: return rewriteValueAMD64_OpAMD64SETGE(v) case OpAMD64SETGEstore: return rewriteValueAMD64_OpAMD64SETGEstore(v) case OpAMD64SETGstore: return rewriteValueAMD64_OpAMD64SETGstore(v) case OpAMD64SETL: return rewriteValueAMD64_OpAMD64SETL(v) case OpAMD64SETLE: return rewriteValueAMD64_OpAMD64SETLE(v) case OpAMD64SETLEstore: return rewriteValueAMD64_OpAMD64SETLEstore(v) case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore(v) case OpAMD64SETNE: return rewriteValueAMD64_OpAMD64SETNE(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore(v) case OpAMD64SHLL: return rewriteValueAMD64_OpAMD64SHLL(v) case OpAMD64SHLLconst: return rewriteValueAMD64_OpAMD64SHLLconst(v) case OpAMD64SHLQ: return rewriteValueAMD64_OpAMD64SHLQ(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst(v) case OpAMD64SHLXLload: return rewriteValueAMD64_OpAMD64SHLXLload(v) case OpAMD64SHLXQload: return rewriteValueAMD64_OpAMD64SHLXQload(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB(v) case OpAMD64SHRBconst: return rewriteValueAMD64_OpAMD64SHRBconst(v) case OpAMD64SHRL: return rewriteValueAMD64_OpAMD64SHRL(v) case OpAMD64SHRLconst: return rewriteValueAMD64_OpAMD64SHRLconst(v) case OpAMD64SHRQ: return rewriteValueAMD64_OpAMD64SHRQ(v) case OpAMD64SHRQconst: return rewriteValueAMD64_OpAMD64SHRQconst(v) case OpAMD64SHRW: return rewriteValueAMD64_OpAMD64SHRW(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst(v) case OpAMD64SHRXLload: return rewriteValueAMD64_OpAMD64SHRXLload(v) case OpAMD64SHRXQload: return rewriteValueAMD64_OpAMD64SHRXQload(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL(v) case OpAMD64SUBLconst: return rewriteValueAMD64_OpAMD64SUBLconst(v) case OpAMD64SUBLload: return rewriteValueAMD64_OpAMD64SUBLload(v) case OpAMD64SUBLmodify: return rewriteValueAMD64_OpAMD64SUBLmodify(v) case OpAMD64SUBQ: return rewriteValueAMD64_OpAMD64SUBQ(v) case OpAMD64SUBQborrow: return rewriteValueAMD64_OpAMD64SUBQborrow(v) case OpAMD64SUBQconst: return rewriteValueAMD64_OpAMD64SUBQconst(v) case OpAMD64SUBQload: return rewriteValueAMD64_OpAMD64SUBQload(v) case OpAMD64SUBQmodify: return rewriteValueAMD64_OpAMD64SUBQmodify(v) case OpAMD64SUBSD: return rewriteValueAMD64_OpAMD64SUBSD(v) case OpAMD64SUBSDload: return rewriteValueAMD64_OpAMD64SUBSDload(v) case OpAMD64SUBSS: return rewriteValueAMD64_OpAMD64SUBSS(v) case OpAMD64SUBSSload: return rewriteValueAMD64_OpAMD64SUBSSload(v) case OpAMD64TESTB: return rewriteValueAMD64_OpAMD64TESTB(v) case OpAMD64TESTBconst: return rewriteValueAMD64_OpAMD64TESTBconst(v) case OpAMD64TESTL: return rewriteValueAMD64_OpAMD64TESTL(v) case OpAMD64TESTLconst: return rewriteValueAMD64_OpAMD64TESTLconst(v) case OpAMD64TESTQ: return rewriteValueAMD64_OpAMD64TESTQ(v) case OpAMD64TESTQconst: return rewriteValueAMD64_OpAMD64TESTQconst(v) case OpAMD64TESTW: return rewriteValueAMD64_OpAMD64TESTW(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock(v) case OpAMD64XADDQlock: return rewriteValueAMD64_OpAMD64XADDQlock(v) case OpAMD64XCHGL: return rewriteValueAMD64_OpAMD64XCHGL(v) case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ(v) case OpAMD64XORL: return rewriteValueAMD64_OpAMD64XORL(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst(v) case OpAMD64XORLconstmodify: return rewriteValueAMD64_OpAMD64XORLconstmodify(v) case OpAMD64XORLload: return rewriteValueAMD64_OpAMD64XORLload(v) case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify(v) case OpAMD64XORQ: return rewriteValueAMD64_OpAMD64XORQ(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst(v) case OpAMD64XORQconstmodify: return rewriteValueAMD64_OpAMD64XORQconstmodify(v) case OpAMD64XORQload: return rewriteValueAMD64_OpAMD64XORQload(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify(v) case OpAdd16: v.Op = OpAMD64ADDL return true case OpAdd32: v.Op = OpAMD64ADDL return true case OpAdd32F: v.Op = OpAMD64ADDSS return true case OpAdd64: v.Op = OpAMD64ADDQ return true case OpAdd64F: v.Op = OpAMD64ADDSD return true case OpAdd8: v.Op = OpAMD64ADDL return true case OpAddPtr: v.Op = OpAMD64ADDQ return true case OpAddr: return rewriteValueAMD64_OpAddr(v) case OpAnd16: v.Op = OpAMD64ANDL return true case OpAnd32: v.Op = OpAMD64ANDL return true case OpAnd64: v.Op = OpAMD64ANDQ return true case OpAnd8: v.Op = OpAMD64ANDL return true case OpAndB: v.Op = OpAMD64ANDL return true case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32(v) case OpAtomicAdd64: return rewriteValueAMD64_OpAtomicAdd64(v) case OpAtomicAnd32: return rewriteValueAMD64_OpAtomicAnd32(v) case OpAtomicAnd8: return rewriteValueAMD64_OpAtomicAnd8(v) case OpAtomicCompareAndSwap32: return rewriteValueAMD64_OpAtomicCompareAndSwap32(v) case OpAtomicCompareAndSwap64: return rewriteValueAMD64_OpAtomicCompareAndSwap64(v) case OpAtomicExchange32: return rewriteValueAMD64_OpAtomicExchange32(v) case OpAtomicExchange64: return rewriteValueAMD64_OpAtomicExchange64(v) case OpAtomicLoad32: return rewriteValueAMD64_OpAtomicLoad32(v) case OpAtomicLoad64: return rewriteValueAMD64_OpAtomicLoad64(v) case OpAtomicLoad8: return rewriteValueAMD64_OpAtomicLoad8(v) case OpAtomicLoadPtr: return rewriteValueAMD64_OpAtomicLoadPtr(v) case OpAtomicOr32: return rewriteValueAMD64_OpAtomicOr32(v) case OpAtomicOr8: return rewriteValueAMD64_OpAtomicOr8(v) case OpAtomicStore32: return rewriteValueAMD64_OpAtomicStore32(v) case OpAtomicStore64: return rewriteValueAMD64_OpAtomicStore64(v) case OpAtomicStore8: return rewriteValueAMD64_OpAtomicStore8(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB(v) case OpAvg64u: v.Op = OpAMD64AVGQU return true case OpBitLen16: return rewriteValueAMD64_OpBitLen16(v) case OpBitLen32: return rewriteValueAMD64_OpBitLen32(v) case OpBitLen64: return rewriteValueAMD64_OpBitLen64(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8(v) case OpBswap32: v.Op = OpAMD64BSWAPL return true case OpBswap64: v.Op = OpAMD64BSWAPQ return true case OpCeil: return rewriteValueAMD64_OpCeil(v) case OpClosureCall: v.Op = OpAMD64CALLclosure return true case OpCom16: v.Op = OpAMD64NOTL return true case OpCom32: v.Op = OpAMD64NOTL return true case OpCom64: v.Op = OpAMD64NOTQ return true case OpCom8: v.Op = OpAMD64NOTL return true case OpCondSelect: return rewriteValueAMD64_OpCondSelect(v) case OpConst16: return rewriteValueAMD64_OpConst16(v) case OpConst32: v.Op = OpAMD64MOVLconst return true case OpConst32F: v.Op = OpAMD64MOVSSconst return true case OpConst64: v.Op = OpAMD64MOVQconst return true case OpConst64F: v.Op = OpAMD64MOVSDconst return true case OpConst8: return rewriteValueAMD64_OpConst8(v) case OpConstBool: return rewriteValueAMD64_OpConstBool(v) case OpConstNil: return rewriteValueAMD64_OpConstNil(v) case OpCtz16: return rewriteValueAMD64_OpCtz16(v) case OpCtz16NonZero: return rewriteValueAMD64_OpCtz16NonZero(v) case OpCtz32: return rewriteValueAMD64_OpCtz32(v) case OpCtz32NonZero: return rewriteValueAMD64_OpCtz32NonZero(v) case OpCtz64: return rewriteValueAMD64_OpCtz64(v) case OpCtz64NonZero: return rewriteValueAMD64_OpCtz64NonZero(v) case OpCtz8: return rewriteValueAMD64_OpCtz8(v) case OpCtz8NonZero: return rewriteValueAMD64_OpCtz8NonZero(v) case OpCvt32Fto32: v.Op = OpAMD64CVTTSS2SL return true case OpCvt32Fto64: v.Op = OpAMD64CVTTSS2SQ return true case OpCvt32Fto64F: v.Op = OpAMD64CVTSS2SD return true case OpCvt32to32F: v.Op = OpAMD64CVTSL2SS return true case OpCvt32to64F: v.Op = OpAMD64CVTSL2SD return true case OpCvt64Fto32: v.Op = OpAMD64CVTTSD2SL return true case OpCvt64Fto32F: v.Op = OpAMD64CVTSD2SS return true case OpCvt64Fto64: v.Op = OpAMD64CVTTSD2SQ return true case OpCvt64to32F: v.Op = OpAMD64CVTSQ2SS return true case OpCvt64to64F: v.Op = OpAMD64CVTSQ2SD return true case OpCvtBoolToUint8: v.Op = OpCopy return true case OpDiv128u: v.Op = OpAMD64DIVQU2 return true case OpDiv16: return rewriteValueAMD64_OpDiv16(v) case OpDiv16u: return rewriteValueAMD64_OpDiv16u(v) case OpDiv32: return rewriteValueAMD64_OpDiv32(v) case OpDiv32F: v.Op = OpAMD64DIVSS return true case OpDiv32u: return rewriteValueAMD64_OpDiv32u(v) case OpDiv64: return rewriteValueAMD64_OpDiv64(v) case OpDiv64F: v.Op = OpAMD64DIVSD return true case OpDiv64u: return rewriteValueAMD64_OpDiv64u(v) case OpDiv8: return rewriteValueAMD64_OpDiv8(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u(v) case OpEq16: return rewriteValueAMD64_OpEq16(v) case OpEq32: return rewriteValueAMD64_OpEq32(v) case OpEq32F: return rewriteValueAMD64_OpEq32F(v) case OpEq64: return rewriteValueAMD64_OpEq64(v) case OpEq64F: return rewriteValueAMD64_OpEq64F(v) case OpEq8: return rewriteValueAMD64_OpEq8(v) case OpEqB: return rewriteValueAMD64_OpEqB(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr(v) case OpFMA: return rewriteValueAMD64_OpFMA(v) case OpFloor: return rewriteValueAMD64_OpFloor(v) case OpGetCallerPC: v.Op = OpAMD64LoweredGetCallerPC return true case OpGetCallerSP: v.Op = OpAMD64LoweredGetCallerSP return true case OpGetClosurePtr: v.Op = OpAMD64LoweredGetClosurePtr return true case OpGetG: return rewriteValueAMD64_OpGetG(v) case OpHasCPUFeature: return rewriteValueAMD64_OpHasCPUFeature(v) case OpHmul32: v.Op = OpAMD64HMULL return true case OpHmul32u: v.Op = OpAMD64HMULLU return true case OpHmul64: v.Op = OpAMD64HMULQ return true case OpHmul64u: v.Op = OpAMD64HMULQU return true case OpInterCall: v.Op = OpAMD64CALLinter return true case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueAMD64_OpIsSliceInBounds(v) case OpLeq16: return rewriteValueAMD64_OpLeq16(v) case OpLeq16U: return rewriteValueAMD64_OpLeq16U(v) case OpLeq32: return rewriteValueAMD64_OpLeq32(v) case OpLeq32F: return rewriteValueAMD64_OpLeq32F(v) case OpLeq32U: return rewriteValueAMD64_OpLeq32U(v) case OpLeq64: return rewriteValueAMD64_OpLeq64(v) case OpLeq64F: return rewriteValueAMD64_OpLeq64F(v) case OpLeq64U: return rewriteValueAMD64_OpLeq64U(v) case OpLeq8: return rewriteValueAMD64_OpLeq8(v) case OpLeq8U: return rewriteValueAMD64_OpLeq8U(v) case OpLess16: return rewriteValueAMD64_OpLess16(v) case OpLess16U: return rewriteValueAMD64_OpLess16U(v) case OpLess32: return rewriteValueAMD64_OpLess32(v) case OpLess32F: return rewriteValueAMD64_OpLess32F(v) case OpLess32U: return rewriteValueAMD64_OpLess32U(v) case OpLess64: return rewriteValueAMD64_OpLess64(v) case OpLess64F: return rewriteValueAMD64_OpLess64F(v) case OpLess64U: return rewriteValueAMD64_OpLess64U(v) case OpLess8: return rewriteValueAMD64_OpLess8(v) case OpLess8U: return rewriteValueAMD64_OpLess8U(v) case OpLoad: return rewriteValueAMD64_OpLoad(v) case OpLocalAddr: return rewriteValueAMD64_OpLocalAddr(v) case OpLsh16x16: return rewriteValueAMD64_OpLsh16x16(v) case OpLsh16x32: return rewriteValueAMD64_OpLsh16x32(v) case OpLsh16x64: return rewriteValueAMD64_OpLsh16x64(v) case OpLsh16x8: return rewriteValueAMD64_OpLsh16x8(v) case OpLsh32x16: return rewriteValueAMD64_OpLsh32x16(v) case OpLsh32x32: return rewriteValueAMD64_OpLsh32x32(v) case OpLsh32x64: return rewriteValueAMD64_OpLsh32x64(v) case OpLsh32x8: return rewriteValueAMD64_OpLsh32x8(v) case OpLsh64x16: return rewriteValueAMD64_OpLsh64x16(v) case OpLsh64x32: return rewriteValueAMD64_OpLsh64x32(v) case OpLsh64x64: return rewriteValueAMD64_OpLsh64x64(v) case OpLsh64x8: return rewriteValueAMD64_OpLsh64x8(v) case OpLsh8x16: return rewriteValueAMD64_OpLsh8x16(v) case OpLsh8x32: return rewriteValueAMD64_OpLsh8x32(v) case OpLsh8x64: return rewriteValueAMD64_OpLsh8x64(v) case OpLsh8x8: return rewriteValueAMD64_OpLsh8x8(v) case OpMod16: return rewriteValueAMD64_OpMod16(v) case OpMod16u: return rewriteValueAMD64_OpMod16u(v) case OpMod32: return rewriteValueAMD64_OpMod32(v) case OpMod32u: return rewriteValueAMD64_OpMod32u(v) case OpMod64: return rewriteValueAMD64_OpMod64(v) case OpMod64u: return rewriteValueAMD64_OpMod64u(v) case OpMod8: return rewriteValueAMD64_OpMod8(v) case OpMod8u: return rewriteValueAMD64_OpMod8u(v) case OpMove: return rewriteValueAMD64_OpMove(v) case OpMul16: v.Op = OpAMD64MULL return true case OpMul32: v.Op = OpAMD64MULL return true case OpMul32F: v.Op = OpAMD64MULSS return true case OpMul64: v.Op = OpAMD64MULQ return true case OpMul64F: v.Op = OpAMD64MULSD return true case OpMul64uhilo: v.Op = OpAMD64MULQU2 return true case OpMul8: v.Op = OpAMD64MULL return true case OpNeg16: v.Op = OpAMD64NEGL return true case OpNeg32: v.Op = OpAMD64NEGL return true case OpNeg32F: return rewriteValueAMD64_OpNeg32F(v) case OpNeg64: v.Op = OpAMD64NEGQ return true case OpNeg64F: return rewriteValueAMD64_OpNeg64F(v) case OpNeg8: v.Op = OpAMD64NEGL return true case OpNeq16: return rewriteValueAMD64_OpNeq16(v) case OpNeq32: return rewriteValueAMD64_OpNeq32(v) case OpNeq32F: return rewriteValueAMD64_OpNeq32F(v) case OpNeq64: return rewriteValueAMD64_OpNeq64(v) case OpNeq64F: return rewriteValueAMD64_OpNeq64F(v) case OpNeq8: return rewriteValueAMD64_OpNeq8(v) case OpNeqB: return rewriteValueAMD64_OpNeqB(v) case OpNeqPtr: return rewriteValueAMD64_OpNeqPtr(v) case OpNilCheck: v.Op = OpAMD64LoweredNilCheck return true case OpNot: return rewriteValueAMD64_OpNot(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr(v) case OpOr16: v.Op = OpAMD64ORL return true case OpOr32: v.Op = OpAMD64ORL return true case OpOr64: v.Op = OpAMD64ORQ return true case OpOr8: v.Op = OpAMD64ORL return true case OpOrB: v.Op = OpAMD64ORL return true case OpPanicBounds: return rewriteValueAMD64_OpPanicBounds(v) case OpPopCount16: return rewriteValueAMD64_OpPopCount16(v) case OpPopCount32: v.Op = OpAMD64POPCNTL return true case OpPopCount64: v.Op = OpAMD64POPCNTQ return true case OpPopCount8: return rewriteValueAMD64_OpPopCount8(v) case OpPrefetchCache: v.Op = OpAMD64PrefetchT0 return true case OpPrefetchCacheStreamed: v.Op = OpAMD64PrefetchNTA return true case OpRotateLeft16: v.Op = OpAMD64ROLW return true case OpRotateLeft32: v.Op = OpAMD64ROLL return true case OpRotateLeft64: v.Op = OpAMD64ROLQ return true case OpRotateLeft8: v.Op = OpAMD64ROLB return true case OpRound32F: v.Op = OpCopy return true case OpRound64F: v.Op = OpCopy return true case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven(v) case OpRsh16Ux16: return rewriteValueAMD64_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValueAMD64_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValueAMD64_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValueAMD64_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValueAMD64_OpRsh16x16(v) case OpRsh16x32: return rewriteValueAMD64_OpRsh16x32(v) case OpRsh16x64: return rewriteValueAMD64_OpRsh16x64(v) case OpRsh16x8: return rewriteValueAMD64_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValueAMD64_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValueAMD64_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValueAMD64_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValueAMD64_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValueAMD64_OpRsh32x16(v) case OpRsh32x32: return rewriteValueAMD64_OpRsh32x32(v) case OpRsh32x64: return rewriteValueAMD64_OpRsh32x64(v) case OpRsh32x8: return rewriteValueAMD64_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValueAMD64_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValueAMD64_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValueAMD64_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValueAMD64_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValueAMD64_OpRsh64x16(v) case OpRsh64x32: return rewriteValueAMD64_OpRsh64x32(v) case OpRsh64x64: return rewriteValueAMD64_OpRsh64x64(v) case OpRsh64x8: return rewriteValueAMD64_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValueAMD64_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValueAMD64_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValueAMD64_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValueAMD64_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValueAMD64_OpRsh8x16(v) case OpRsh8x32: return rewriteValueAMD64_OpRsh8x32(v) case OpRsh8x64: return rewriteValueAMD64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8(v) case OpSelect0: return rewriteValueAMD64_OpSelect0(v) case OpSelect1: return rewriteValueAMD64_OpSelect1(v) case OpSelectN: return rewriteValueAMD64_OpSelectN(v) case OpSignExt16to32: v.Op = OpAMD64MOVWQSX return true case OpSignExt16to64: v.Op = OpAMD64MOVWQSX return true case OpSignExt32to64: v.Op = OpAMD64MOVLQSX return true case OpSignExt8to16: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to32: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to64: v.Op = OpAMD64MOVBQSX return true case OpSlicemask: return rewriteValueAMD64_OpSlicemask(v) case OpSpectreIndex: return rewriteValueAMD64_OpSpectreIndex(v) case OpSpectreSliceIndex: return rewriteValueAMD64_OpSpectreSliceIndex(v) case OpSqrt: v.Op = OpAMD64SQRTSD return true case OpSqrt32: v.Op = OpAMD64SQRTSS return true case OpStaticCall: v.Op = OpAMD64CALLstatic return true case OpStore: return rewriteValueAMD64_OpStore(v) case OpSub16: v.Op = OpAMD64SUBL return true case OpSub32: v.Op = OpAMD64SUBL return true case OpSub32F: v.Op = OpAMD64SUBSS return true case OpSub64: v.Op = OpAMD64SUBQ return true case OpSub64F: v.Op = OpAMD64SUBSD return true case OpSub8: v.Op = OpAMD64SUBL return true case OpSubPtr: v.Op = OpAMD64SUBQ return true case OpTailCall: v.Op = OpAMD64CALLtail return true case OpTrunc: return rewriteValueAMD64_OpTrunc(v) case OpTrunc16to8: v.Op = OpCopy return true case OpTrunc32to16: v.Op = OpCopy return true case OpTrunc32to8: v.Op = OpCopy return true case OpTrunc64to16: v.Op = OpCopy return true case OpTrunc64to32: v.Op = OpCopy return true case OpTrunc64to8: v.Op = OpCopy return true case OpWB: v.Op = OpAMD64LoweredWB return true case OpXor16: v.Op = OpAMD64XORL return true case OpXor32: v.Op = OpAMD64XORL return true case OpXor64: v.Op = OpAMD64XORQ return true case OpXor8: v.Op = OpAMD64XORL return true case OpZero: return rewriteValueAMD64_OpZero(v) case OpZeroExt16to32: v.Op = OpAMD64MOVWQZX return true case OpZeroExt16to64: v.Op = OpAMD64MOVWQZX return true case OpZeroExt32to64: v.Op = OpAMD64MOVLQZX return true case OpZeroExt8to16: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to32: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to64: v.Op = OpAMD64MOVBQZX return true } return false } func rewriteValueAMD64_OpAMD64ADCQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) // result: (ADCQconst x [int32(c)] carry) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) carry := v_2 if !(is32Bit(c)) { continue } v.reset(OpAMD64ADCQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, carry) return true } break } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQcarry) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64ADCQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQconst x [c] (FlagEQ)) // result: (ADDQconstcarry x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDL x (MOVLconst [c])) // result: (ADDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAL2) v.AddArg2(y, x) return true } } break } // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAL { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL { continue } y := v_1.Args[0] v.reset(OpAMD64SUBL) v.AddArg2(x, y) return true } break } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDLconst [c] (ADDL x y)) // result: (LEAL1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (SHLLconst [1] x)) // result: (LEAL1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // result: (MOVLconst [c+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c + d) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // result: (ADDLconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDLconst [off] x:(SP)) // result: (LEAL [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (ADDL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQ x (MOVQconst [c])) // cond: is32Bit(c) && !t.IsPtr() // result: (ADDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c) && !t.IsPtr()) { continue } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ADDQ x (MOVLconst [c])) // result: (ADDQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAQ2) v.AddArg2(y, x) return true } } break } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ { continue } y := v_1.Args[0] v.reset(OpAMD64SUBQ) v.AddArg2(x, y) return true } break } // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQcarry(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQcarry x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconstcarry x [int32(c)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDQconst [c] (ADDQ x y)) // result: (LEAQ1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (SHLQconst [1] x)) // result: (LEAQ1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDQconst [c] (LEAQ [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ADDQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) + d) return true } // match: (ADDQconst [c] (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (ADDQconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDQconst [off] x:(SP)) // result: (LEAQ [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (ADDQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (ADDSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (ADDSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ANDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTRL) v.AddArg2(x, y) return true } break } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } break } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ANDL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDL x (NOTL y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTL { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNL) v.AddArg2(x, y) return true } break } // match: (ANDL x (NEGL x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIL) v.AddArg(x) return true } break } // match: (ANDL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (Select0 (BLSRL x)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpSelect0) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64BLSRL, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDLconst [c] x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDLconst [c] (BTRLconst [d] x)) // result: (ANDLconst [c &^ (1<= 128 // result: (BTRQconst [int8(log64(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log64(^c))) v.AddArg(x) return true } break } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ANDQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDQ x (NOTQ y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTQ { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNQ) v.AddArg2(x, y) return true } break } // match: (ANDQ x (NEGQ x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIQ) v.AddArg(x) return true } break } // match: (ANDQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (Select0 (BLSRQ x)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpSelect0) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64BLSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDQconst [c] x) // cond: isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRQconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDQconst [c] (ANDQconst [d] x)) // result: (ANDQconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDQconst [c] (BTRQconst [d] x)) // cond: is32Bit(int64(c) &^ (1< [1<<8] (MOVBQZX x))) // result: (BSFQ (ORQconst [1<<8] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVBQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 8) v0.AddArg(x) v.AddArg(v0) return true } // match: (BSFQ (ORQconst [1<<16] (MOVWQZX x))) // result: (BSFQ (ORQconst [1<<16] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVWQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPL(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPL (BSWAPL p)) // result: p for { if v_0.Op != OpAMD64BSWAPL { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPL x:(MOVLload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPL (MOVBELload [i] {s} p m)) // result: (MOVLload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBELload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPQ(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPQ (BSWAPQ p)) // result: p for { if v_0.Op != OpAMD64BSWAPQ { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPQ x:(MOVQload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPQ (MOVBEQload [i] {s} p m)) // result: (MOVQload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBEQload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BTCLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTCLconst [c] (XORLconst [d] x)) // result: (XORLconst [d ^ 1<d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 32) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTLconst [c] (SHLLconst [d] x)) // cond: c>d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } // match: (BTLconst [0] s:(SHRXL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTQconst(v *Value) bool { v_0 := v.Args[0] // match: (BTQconst [c] (SHRQconst [d] x)) // cond: (c+d)<64 // result: (BTQconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 64) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTQconst [c] (SHLQconst [d] x)) // cond: c>d // result: (BTQconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTQconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTRLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTRLconst [c] (BTSLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTSLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (BTCLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTCLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [d &^ (1< blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTQ { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { continue } v.reset(OpAMD64CMOVLEQ) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } // match: (CMOVLEQ x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) // result: (CMOVLEQ x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTL { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_2_1 { continue } v.reset(OpAMD64CMOVLEQ) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } return false } func rewriteValueAMD64_OpAMD64CMOVLGE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVLGE x y (InvertFlags cond)) // result: (CMOVLLE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLLE) v.AddArg3(x, y, cond) return true } // match: (CMOVLGE _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVLGE _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVLGE _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVLGE y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVLGE y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVLGT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVLGT x y (InvertFlags cond)) // result: (CMOVLLT x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLLT) v.AddArg3(x, y, cond) return true } // match: (CMOVLGT y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVLGT _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVLGT _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVLGT y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVLGT y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVLHI(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVLHI x y (InvertFlags cond)) // result: (CMOVLCS x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLCS) v.AddArg3(x, y, cond) return true } // match: (CMOVLHI y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVLHI _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVLHI y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVLHI y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVLHI _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVLLE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVLLE x y (InvertFlags cond)) // result: (CMOVLGE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLGE) v.AddArg3(x, y, cond) return true } // match: (CMOVLLE _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVLLE y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVLLE y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVLLE _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVLLE _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVLLS(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVLLS x y (InvertFlags cond)) // result: (CMOVLCC x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLCC) v.AddArg3(x, y, cond) return true } // match: (CMOVLLS _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVLLS y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVLLS _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVLLS _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVLLS y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVLLT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVLLT x y (InvertFlags cond)) // result: (CMOVLGT x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLGT) v.AddArg3(x, y, cond) return true } // match: (CMOVLLT y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVLLT y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVLLT y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVLLT _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVLLT _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVLNE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMOVLNE x y (InvertFlags cond)) // result: (CMOVLNE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLNE) v.AddArg3(x, y, cond) return true } // match: (CMOVLNE y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVLNE _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVLNE _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVLNE _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVLNE _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } // match: (CMOVLNE x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) // result: (CMOVLNE x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTQ { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { continue } v.reset(OpAMD64CMOVLNE) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } // match: (CMOVLNE x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) // result: (CMOVLNE x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTL { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_2_1 { continue } v.reset(OpAMD64CMOVLNE) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } return false } func rewriteValueAMD64_OpAMD64CMOVQCC(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQCC x y (InvertFlags cond)) // result: (CMOVQLS x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQLS) v.AddArg3(x, y, cond) return true } // match: (CMOVQCC _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVQCC _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVQCC y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVQCC y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVQCC _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQCS(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQCS x y (InvertFlags cond)) // result: (CMOVQHI x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQHI) v.AddArg3(x, y, cond) return true } // match: (CMOVQCS y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVQCS y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVQCS _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVQCS _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVQCS y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQEQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMOVQEQ x y (InvertFlags cond)) // result: (CMOVQEQ x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQEQ) v.AddArg3(x, y, cond) return true } // match: (CMOVQEQ _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVQEQ y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVQEQ y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVQEQ y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVQEQ y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } // match: (CMOVQEQ x _ (Select1 (BSFQ (ORQconst [c] _)))) // cond: c != 0 // result: x for { x := v_0 if v_2.Op != OpSelect1 { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpAMD64BSFQ { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpAMD64ORQconst { break } c := auxIntToInt32(v_2_0_0.AuxInt) if !(c != 0) { break } v.copyOf(x) return true } // match: (CMOVQEQ x _ (Select1 (BSRQ (ORQconst [c] _)))) // cond: c != 0 // result: x for { x := v_0 if v_2.Op != OpSelect1 { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpAMD64BSRQ { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpAMD64ORQconst { break } c := auxIntToInt32(v_2_0_0.AuxInt) if !(c != 0) { break } v.copyOf(x) return true } // match: (CMOVQEQ x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) // result: (CMOVQEQ x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTQ { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { continue } v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } // match: (CMOVQEQ x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) // result: (CMOVQEQ x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTL { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_2_1 { continue } v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } return false } func rewriteValueAMD64_OpAMD64CMOVQGE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQGE x y (InvertFlags cond)) // result: (CMOVQLE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQLE) v.AddArg3(x, y, cond) return true } // match: (CMOVQGE _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVQGE _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVQGE _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVQGE y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVQGE y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQGT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQGT x y (InvertFlags cond)) // result: (CMOVQLT x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQLT) v.AddArg3(x, y, cond) return true } // match: (CMOVQGT y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVQGT _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVQGT _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVQGT y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVQGT y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQHI(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQHI x y (InvertFlags cond)) // result: (CMOVQCS x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQCS) v.AddArg3(x, y, cond) return true } // match: (CMOVQHI y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVQHI _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVQHI y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVQHI y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVQHI _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQLE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQLE x y (InvertFlags cond)) // result: (CMOVQGE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQGE) v.AddArg3(x, y, cond) return true } // match: (CMOVQLE _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVQLE y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVQLE y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVQLE _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVQLE _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQLS(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQLS x y (InvertFlags cond)) // result: (CMOVQCC x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQCC) v.AddArg3(x, y, cond) return true } // match: (CMOVQLS _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVQLS y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVQLS _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVQLS _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVQLS y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQLT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQLT x y (InvertFlags cond)) // result: (CMOVQGT x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQGT) v.AddArg3(x, y, cond) return true } // match: (CMOVQLT y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVQLT y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVQLT y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVQLT _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVQLT _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQNE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMOVQNE x y (InvertFlags cond)) // result: (CMOVQNE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQNE) v.AddArg3(x, y, cond) return true } // match: (CMOVQNE y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVQNE _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVQNE _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVQNE _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVQNE _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } // match: (CMOVQNE x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) // result: (CMOVQNE x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTQ { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { continue } v.reset(OpAMD64CMOVQNE) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } // match: (CMOVQNE x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) // result: (CMOVQNE x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTL { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_2_1 { continue } v.reset(OpAMD64CMOVQNE) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } return false } func rewriteValueAMD64_OpAMD64CMOVWCC(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWCC x y (InvertFlags cond)) // result: (CMOVWLS x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWLS) v.AddArg3(x, y, cond) return true } // match: (CMOVWCC _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVWCC _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVWCC y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVWCC y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVWCC _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWCS(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWCS x y (InvertFlags cond)) // result: (CMOVWHI x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWHI) v.AddArg3(x, y, cond) return true } // match: (CMOVWCS y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVWCS y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVWCS _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVWCS _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVWCS y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWEQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWEQ x y (InvertFlags cond)) // result: (CMOVWEQ x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWEQ) v.AddArg3(x, y, cond) return true } // match: (CMOVWEQ _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVWEQ y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVWEQ y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVWEQ y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVWEQ y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWGE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWGE x y (InvertFlags cond)) // result: (CMOVWLE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWLE) v.AddArg3(x, y, cond) return true } // match: (CMOVWGE _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVWGE _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVWGE _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVWGE y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVWGE y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWGT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWGT x y (InvertFlags cond)) // result: (CMOVWLT x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWLT) v.AddArg3(x, y, cond) return true } // match: (CMOVWGT y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVWGT _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVWGT _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVWGT y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVWGT y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWHI(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWHI x y (InvertFlags cond)) // result: (CMOVWCS x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWCS) v.AddArg3(x, y, cond) return true } // match: (CMOVWHI y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVWHI _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVWHI y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVWHI y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVWHI _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWLE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWLE x y (InvertFlags cond)) // result: (CMOVWGE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWGE) v.AddArg3(x, y, cond) return true } // match: (CMOVWLE _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVWLE y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVWLE y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVWLE _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVWLE _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWLS(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWLS x y (InvertFlags cond)) // result: (CMOVWCC x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWCC) v.AddArg3(x, y, cond) return true } // match: (CMOVWLS _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVWLS y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVWLS _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVWLS _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVWLS y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWLT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWLT x y (InvertFlags cond)) // result: (CMOVWGT x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWGT) v.AddArg3(x, y, cond) return true } // match: (CMOVWLT y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVWLT y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVWLT y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVWLT _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVWLT _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWNE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWNE x y (InvertFlags cond)) // result: (CMOVWNE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWNE) v.AddArg3(x, y, cond) return true } // match: (CMOVWNE y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVWNE _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVWNE _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVWNE _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVWNE _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMPB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPB x (MOVLconst [c])) // result: (CMPBconst x [int8(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64CMPBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } // match: (CMPB (MOVLconst [c]) x) // result: (InvertFlags (CMPBconst x [int8(c)])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPB x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPB y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMPB l:(MOVBload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPBload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVBload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPB x l:(MOVBload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPBload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVBload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPBload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)==y // result: (FlagEQ) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) == y) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)uint8(y) // result: (FlagLT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) < y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x) y && uint8(x) < uint8(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) > y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int8(m) && int8(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPBconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTB x y) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, y) return true } // match: (CMPBconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTBconst [int8(c)] x) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt8(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVBload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPBload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPL x (MOVLconst [c])) // result: (CMPLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64CMPLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // result: (InvertFlags (CMPLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPL y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x==y // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x == y) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: xuint32(y) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x < y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x) y && uint32(x) < uint32(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x > y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) // result: (FlagLT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x < y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x)>uint64(y) // result: (FlagGT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x > y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQ l:(MOVQload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPQload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPQ x l:(MOVQload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPQload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPQload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x==int64(y) // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x == int64(y)) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: xuint64(int64(y)) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x < int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x) int64(y) && uint64(x) < uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x)>uint64(int64(y)) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x > int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQconst (MOVBQZX _) [c]) // cond: 0xFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVWQZX _) [c]) // cond: 0xFFFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (SHRQconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 64 && (1<uint16(y) // result: (FlagLT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) < y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x) y && uint16(x) < uint16(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) > y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int16(m) && int16(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPWconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTW x y) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, y) return true } // match: (CMPWconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTWconst [int16(c)] x) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt16(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVWload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPWload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGLlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGQlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64HMULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULL x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULL y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULLU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULLU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULLU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULLU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQ x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQ y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64LEAL(v *Value) bool { v_0 := v.Args[0] // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { v_0 := v.Args[0] // match: (LEAQ [c] {s} (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAQ [c] {s} (ADDQ x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg(x) return true } // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ2 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ4 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ8 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64LEAQ { continue } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(y, x) return true } } break } // match: (LEAQ1 [0] x y) // cond: v.Aux == nil // result: (ADDQ x y) for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 y := v_1 if !(v.Aux == nil) { break } v.reset(OpAMD64ADDQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAQ2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil // result: (LEAQ4 [off1+2*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + 2*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ2 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ2 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAQ4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil // result: (LEAQ8 [off1+4*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + 4*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ4 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ4 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAQ8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ8 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ8 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBELstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBELstore [i] {s} p (BSWAPL x) m) // result: (MOVLstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPL { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEQstore [i] {s} p (BSWAPQ x) m) // result: (MOVQstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPQ { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7f) v.AddArg(x) return true } // match: (MOVBQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x) // cond: zeroUpper56Bits(x,3) // result: x for { x := v_0 if !(zeroUpper56Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVBQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xff) v.AddArg(x) return true } // match: (MOVBQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read8(sym, int64(off)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read8(sym, int64(off)))) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) // cond: y.Uses == 1 // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETL { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) // cond: y.Uses == 1 // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETLE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) // cond: y.Uses == 1 // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETG { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) // cond: y.Uses == 1 // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETGE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) // cond: y.Uses == 1 // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETEQ { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) // cond: y.Uses == 1 // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETNE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) // cond: y.Uses == 1 // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETB { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) // cond: y.Uses == 1 // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETBE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) // cond: y.Uses == 1 // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETA { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) // cond: y.Uses == 1 // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETAE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && clobber(x0) // result: (MOVWstore [i-1] {s} p (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p1 w x0:(MOVBstore [i] {s} p0 (SHRWconst [8] w) mem)) // cond: x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0) // result: (MOVWstore [i] {s} p0 (ROLWconst [8] w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 w := v_1 x0 := v_2 if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-1 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-3 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 3) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p3 w x2:(MOVBstore [i] {s} p2 (SHRLconst [8] w) x1:(MOVBstore [i] {s} p1 (SHRLconst [16] w) x0:(MOVBstore [i] {s} p0 (SHRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2) // result: (MOVLstore [i] {s} p0 (BSWAPL w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p3 := v_0 w := v_1 x2 := v_2 if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i-1 || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] if p != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i-2 || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] if p != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i-3 || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i-4 || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-5 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-6 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-7 || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 7) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, typ.UInt64) v0.AddArg(w) v.AddArg3(p, v0, mem) return true } // match: (MOVBstore [i] {s} p7 w x6:(MOVBstore [i] {s} p6 (SHRQconst [8] w) x5:(MOVBstore [i] {s} p5 (SHRQconst [16] w) x4:(MOVBstore [i] {s} p4 (SHRQconst [24] w) x3:(MOVBstore [i] {s} p3 (SHRQconst [32] w) x2:(MOVBstore [i] {s} p2 (SHRQconst [40] w) x1:(MOVBstore [i] {s} p1 (SHRQconst [48] w) x0:(MOVBstore [i] {s} p0 (SHRQconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVQstore [i] {s} p0 (BSWAPQ w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p7 := v_0 w := v_1 x6 := v_2 if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i || auxToSym(x6.Aux) != s { break } _ = x6.Args[2] p6 := x6.Args[0] x6_1 := x6.Args[1] if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { break } x5 := x6.Args[2] if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] p5 := x5.Args[0] x5_1 := x5.Args[1] if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { break } x4 := x5.Args[2] if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] p4 := x4.Args[0] x4_1 := x4.Args[1] if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { break } x3 := x4.Args[2] if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] p3 := x3.Args[0] x3_1 := x3.Args[1] if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x2 := x3.Args[2] if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p2 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { break } x1 := x2.Args[2] if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { break } x0 := x1.Args[2] if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { break } mem := x0.Args[2] p0 := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, typ.UInt64) v0.AddArg(w) v.AddArg3(p0, v0, mem) return true } // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstore [i-1] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRWconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRWconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRLconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRQconst [8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 w := v_1 x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p1 := x.Args[0] x_1 := x.Args[1] if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRLconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRLconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [i] {s} p1 (SHRQconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRQconst [j-8] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) // result: (MOVWstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVBstore [c3] {s} p3 (SHRQconst [56] w) x1:(MOVWstore [c2] {s} p2 (SHRQconst [40] w) x2:(MOVLstore [c1] {s} p1 (SHRQconst [8] w) x3:(MOVBstore [c0] {s} p0 w mem)))) // cond: x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1 + c0 - c1)) && sequentialAddresses(p0, p2, int64(5 + c0 - c2)) && sequentialAddresses(p0, p3, int64(7 + c0 - c3)) && clobber(x1, x2, x3) // result: (MOVQstore [c0] {s} p0 w mem) for { c3 := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p3 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 56 { break } w := v_1.Args[0] x1 := v_2 if x1.Op != OpAMD64MOVWstore { break } c2 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p2 := x1.Args[0] x1_1 := x1.Args[1] if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 40 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpAMD64MOVLstore { break } c1 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { break } _ = x2.Args[2] p1 := x2.Args[0] x2_1 := x2.Args[1] if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpAMD64MOVBstore { break } c0 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { break } mem := x3.Args[2] p0 := x3.Args[0] if w != x3.Args[1] || !(x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1+c0-c1)) && sequentialAddresses(p0, p2, int64(5+c0-c2)) && sequentialAddresses(p0, p3, int64(7+c0-c3)) && clobber(x1, x2, x3)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(c0) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVBload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVBstore || auxIntToInt32(mem2.AuxInt) != i-1 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVBload || auxIntToInt32(x2.AuxInt) != j-1 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(j - 1) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [c] {s} p1 x:(MOVBstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVBstoreconst [a] {s} p0 x:(MOVBstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVBstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX (ANDLconst [c] x)) // cond: uint32(c) & 0x80000000 == 0 // result: (ANDLconst [c & 0x7fffffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(uint32(c)&0x80000000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fffffff) v.AddArg(x) return true } // match: (MOVLQSX (MOVLQSX x)) // result: (MOVLQSX x) for { if v_0.Op != OpAMD64MOVLQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x) // cond: zeroUpper32Bits(x,3) // result: x for { x := v_0 if !(zeroUpper32Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVLQZX (ANDLconst [c] x)) // result: (ANDLconst [c] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (MOVLQZX (MOVLQZX x)) // result: (MOVLQZX x) for { if v_0.Op != OpAMD64MOVLQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLf2i) v.AddArg(val) return true } // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstore [i-4] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [32] w) x:(MOVLstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVLstore [i] {s} p1 (SHRQconst [j] w) x:(MOVLstore [i] {s} p0 w0:(SHRQconst [j-32] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) // result: (MOVQstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVLload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVLstore || auxIntToInt32(mem2.AuxInt) != i-4 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVLload || auxIntToInt32(x2.AuxInt) != j-4 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(j - 4) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) // result: (MOVSSstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [i] {s} p x:(BSWAPL w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPL { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [c] {s} p1 x:(MOVLstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p0, v0, mem) return true } // match: (MOVLstoreconst [a] {s} p0 x:(MOVLstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVLstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(a.Off()) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) v.AddArg3(p0, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) // cond: symIsRO(srcSym) // result: (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))]) (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))]) mem)) for { dstOff := auxIntToInt32(v.AuxInt) dstSym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVOload { break } srcOff := auxIntToInt32(v_1.AuxInt) srcSym := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } mem := v_2 if !(symIsRO(srcSym)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(dstOff + 8) v.Aux = symToAux(dstSym) v0 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))) v1 := b.NewValue0(v_1.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AuxInt = int32ToAuxInt(dstOff) v1.Aux = symToAux(dstSym) v2 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))) v1.AddArg3(ptr, v2, mem) v.AddArg3(ptr, v0, v1) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVOstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.copyOf(x) return true } // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) // result: (MOVQf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQf2i) v.AddArg(val) return true } // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validVal(c) // result: (MOVQstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(validVal(c)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) // result: (MOVSDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [i] {s} p x:(BSWAPQ w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPQ { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [c] {s} p1 x:(MOVQstoreconst [a] {s} p0 mem)) // cond: config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVQstoreconst [a] {s} p0 x:(MOVQstoreconst [c] {s} p1 mem)) // cond: config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fff) v.AddArg(x) return true } // match: (MOVWQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x) // cond: zeroUpper48Bits(x,3) // result: x for { x := v_0 if !(zeroUpper48Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVWQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xffff) v.AddArg(x) return true } // match: (MOVWQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVLstore [i-2] {s} p w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if p != x.Args[0] { break } w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(p, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRLconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRLconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRLconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p1 (SHRQconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRQconst [j-16] w) mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) // result: (MOVLstore [i] {s} p0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 if v_1.Op != OpAMD64SHRQconst { break } j := auxIntToInt8(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { break } mem := x.Args[2] p0 := x.Args[0] w0 := x.Args[1] if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p0, w0, mem) return true } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVWload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVWstore || auxIntToInt32(mem2.AuxInt) != i-2 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVWload || auxIntToInt32(x2.AuxInt) != j-2 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(j - 2) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [c] {s} p1 x:(MOVWstoreconst [a] {s} p0 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVWstoreconst [a] {s} p0 x:(MOVWstoreconst [c] {s} p1 mem)) // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVWstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULL x (MOVLconst [c])) // result: (MULLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULLconst [c] (MULLconst [d] x)) // result: (MULLconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULLconst [-9] x) // result: (NEGL (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // result: (NEGL (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // result: (NEGL (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // result: (NEGL x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGL) v.AddArg(x) return true } // match: (MULLconst [ 0] _) // result: (MOVLconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (MULLconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULLconst [ 3] x) // result: (LEAL2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAL2) v.AddArg2(x, x) return true } // match: (MULLconst [ 5] x) // result: (LEAL4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAL4) v.AddArg2(x, x) return true } // match: (MULLconst [ 7] x) // result: (LEAL2 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [ 9] x) // result: (LEAL8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAL8) v.AddArg2(x, x) return true } // match: (MULLconst [11] x) // result: (LEAL2 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [13] x) // result: (LEAL4 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [19] x) // result: (LEAL2 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [21] x) // result: (LEAL4 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [25] x) // result: (LEAL8 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [27] x) // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [37] x) // result: (LEAL4 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [41] x) // result: (LEAL8 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [45] x) // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [73] x) // result: (LEAL8 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [81] x) // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBL (SHLLconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAL1) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLLconst [int8(log32(c/3))] (LEAL2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLLconst [int8(log32(c/5))] (LEAL4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLLconst [int8(log32(c/9))] (LEAL8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] (MOVLconst [d])) // result: (MOVLconst [c*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c * d) return true } return false } func rewriteValueAMD64_OpAMD64MULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (MULQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULQconst [c] (MULQconst [d] x)) // cond: is32Bit(int64(c)*int64(d)) // result: (MULQconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) * int64(d))) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULQconst [-9] x) // result: (NEGQ (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-5] x) // result: (NEGQ (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-3] x) // result: (NEGQ (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-1] x) // result: (NEGQ x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGQ) v.AddArg(x) return true } // match: (MULQconst [ 0] _) // result: (MOVQconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MULQconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULQconst [ 3] x) // result: (LEAQ2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAQ2) v.AddArg2(x, x) return true } // match: (MULQconst [ 5] x) // result: (LEAQ4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAQ4) v.AddArg2(x, x) return true } // match: (MULQconst [ 7] x) // result: (LEAQ2 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [ 9] x) // result: (LEAQ8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAQ8) v.AddArg2(x, x) return true } // match: (MULQconst [11] x) // result: (LEAQ2 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [13] x) // result: (LEAQ4 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [19] x) // result: (LEAQ2 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [21] x) // result: (LEAQ4 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [25] x) // result: (LEAQ8 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [27] x) // result: (LEAQ8 (LEAQ2 x x) (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [37] x) // result: (LEAQ4 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [41] x) // result: (LEAQ8 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [45] x) // result: (LEAQ8 (LEAQ4 x x) (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [73] x) // result: (LEAQ8 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [81] x) // result: (LEAQ8 (LEAQ8 x x) (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBQ (SHLQconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAQ1 (SHLQconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAQ1) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAQ2 (SHLQconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAQ4 (SHLQconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAQ8 (SHLQconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLQconst [int8(log32(c/3))] (LEAQ2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLQconst [int8(log32(c/5))] (LEAQ4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLQconst [int8(log32(c/9))] (LEAQ8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) * d) return true } // match: (MULQconst [c] (NEGQ x)) // cond: c != -(1<<31) // result: (MULQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (MULSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64MULSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (MULSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64NEGL(v *Value) bool { v_0 := v.Args[0] // match: (NEGL (NEGL x)) // result: x for { if v_0.Op != OpAMD64NEGL { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGL s:(SUBL x y)) // cond: s.Uses == 1 // result: (SUBL y x) for { s := v_0 if s.Op != OpAMD64SUBL { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBL) v.AddArg2(y, x) return true } // match: (NEGL (MOVLconst [c])) // result: (MOVLconst [-c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-c) return true } return false } func rewriteValueAMD64_OpAMD64NEGQ(v *Value) bool { v_0 := v.Args[0] // match: (NEGQ (NEGQ x)) // result: x for { if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGQ s:(SUBQ x y)) // cond: s.Uses == 1 // result: (SUBQ y x) for { s := v_0 if s.Op != OpAMD64SUBQ { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBQ) v.AddArg2(y, x) return true } // match: (NEGQ (MOVQconst [c])) // result: (MOVQconst [-c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-c) return true } // match: (NEGQ (ADDQconst [c] (NEGQ x))) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { if v_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } x := v_0_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64NOTL(v *Value) bool { v_0 := v.Args[0] // match: (NOTL (MOVLconst [c])) // result: (MOVLconst [^c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64NOTQ(v *Value) bool { v_0 := v.Args[0] // match: (NOTQ (MOVQconst [c])) // result: (MOVQconst [^c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64ORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTSL) v.AddArg2(x, y) return true } break } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORL x0:(MOVBload [i0] {s} p mem) sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVBload [i] {s} p0 mem) sh:(SHLLconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORL x0:(MOVWload [i] {s} p0 mem) sh:(SHLLconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL x1:(MOVBload [i] {s} p1 mem) sh:(SHLLconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLLconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORL { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLLconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORLconst(v *Value) bool { v_0 := v.Args[0] // match: (ORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORLconst [c] (ORLconst [d] x)) // result: (ORLconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORLconst [c] (BTSLconst [d] x)) // result: (ORLconst [c | 1<= 128 // result: (BTSQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ORQ x (MOVLconst [c])) // result: (ORQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORQ (SHRQ lo bits) (SHLQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLQ lo bits) (SHRQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHRXQ lo bits) (SHLXQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLXQ lo bits) (SHRXQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (MOVQconst [c]) (MOVQconst [d])) // result: (MOVQconst [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c | d) return true } break } // match: (ORQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORQ x0:(MOVBload [i0] {s} p mem) sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBload [i] {s} p0 mem) sh:(SHLQconst [8] x1:(MOVBload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVWload [i] {s} p0 mem) sh:(SHLQconst [16] x1:(MOVWload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i0) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVLload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVLload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVQload [i] {s} p0 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVLload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p0, mem) return true } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i0) v2.Aux = symToAux(s) v2.AddArg2(p, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i] {s} p0 mem)) y)) // cond: j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i] {s} p0 mem)) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s1 := v_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s0 := or_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] { continue } y := or_1 if !(j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j0) v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v2.AuxInt = int32ToAuxInt(i) v2.Aux = symToAux(s) v2.AddArg2(p0, mem) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ x1:(MOVBload [i] {s} p1 mem) sh:(SHLQconst [8] x0:(MOVBload [i] {s} p0 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x1 := v_0 if x1.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { continue } x0 := sh.Args[0] if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) v.copyOf(v0) v0.AuxInt = int8ToAuxInt(8) v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i1 := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload { continue } i0 := auxIntToInt32(x0.AuxInt) if auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } break } // match: (ORQ r1:(BSWAPL x1:(MOVLload [i] {s} p1 mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i] {s} p0 mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i] {s} p0 mem)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { r1 := v_0 if r1.Op != OpAMD64BSWAPL { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVLload { continue } i := auxIntToInt32(x1.AuxInt) s := auxToSym(x1.Aux) mem := x1.Args[1] p1 := x1.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } r0 := sh.Args[0] if r0.Op != OpAMD64BSWAPL { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVLload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { continue } _ = x0.Args[1] p0 := x0.Args[0] if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) v1.AuxInt = int32ToAuxInt(i) v1.Aux = symToAux(s) v1.AddArg2(p0, mem) v0.AddArg(v1) return true } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) x0 := s0.Args[0] if x0.Op != OpAMD64MOVBload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) x1 := s1.Args[0] if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) v2.AuxInt = int8ToAuxInt(8) v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y := or_1 if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i0) v3.Aux = symToAux(s) v3.AddArg2(p, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem))) y)) // cond: j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i] {s} p0 mem))) y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { s0 := v_0 if s0.Op != OpAMD64SHLQconst { continue } j0 := auxIntToInt8(s0.AuxInt) r0 := s0.Args[0] if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { continue } x0 := r0.Args[0] if x0.Op != OpAMD64MOVWload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] or := v_1 if or.Op != OpAMD64ORQ { continue } _ = or.Args[1] or_0 := or.Args[0] or_1 := or.Args[1] for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { s1 := or_0 if s1.Op != OpAMD64SHLQconst { continue } j1 := auxIntToInt8(s1.AuxInt) r1 := s1.Args[0] if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { continue } x1 := r1.Args[0] if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] { continue } y := or_1 if !(j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { continue } b = mergePoint(b, x0, x1, y) v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) v1.AuxInt = int8ToAuxInt(j1) v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) v3.AuxInt = int32ToAuxInt(i) v3.Aux = symToAux(s) v3.AddArg2(p0, mem) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(v1, y) return true } } break } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ORQ x0:(MOVBELload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVBELload [i1] {s} p mem))) // cond: i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i1] {s} p mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i1) v0.Aux = symToAux(s) v0.AddArg2(p, mem) return true } break } // match: (ORQ x0:(MOVBELload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVBELload [i] {s} p1 mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) // result: @mergePoint(b,x0,x1) (MOVBEQload [i] {s} p1 mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 if x0.Op != OpAMD64MOVBELload { continue } i := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p0 := x0.Args[0] sh := v_1 if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { continue } x1 := sh.Args[0] if x1.Op != OpAMD64MOVBELload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] p1 := x1.Args[0] if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(i) v0.Aux = symToAux(s) v0.AddArg2(p1, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQconst(v *Value) bool { v_0 := v.Args[0] // match: (ORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORQconst [c] (ORQconst [d] x)) // result: (ORQconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORQconst [c] (BTSQconst [d] x)) // cond: is32Bit(int64(c) | 1<>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int8(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (MOVLconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL l:(MOVLload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SARXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARLconst(v *Value) bool { v_0 := v.Args[0] // match: (SARLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARLconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int32(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int32(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (MOVLconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ l:(MOVQload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SARXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARQconst(v *Value) bool { v_0 := v.Args[0] // match: (SARQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARQconst [c] (MOVQconst [d])) // result: (MOVQconst [d>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SARW x (MOVQconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } // match: (SARW x (MOVLconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SARWconst(v *Value) bool { v_0 := v.Args[0] // match: (SARWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARWconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int16(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int16(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SARXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SARLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SARXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SARXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SBBLcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBLcarrymask (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagLT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagGT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQ x (MOVQconst [c]) borrow) // cond: is32Bit(c) // result: (SBBQconst x [int32(c)] borrow) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) borrow := v_2 if !(is32Bit(c)) { break } v.reset(OpAMD64SBBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, borrow) return true } // match: (SBBQ x y (FlagEQ)) // result: (SUBQborrow x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQborrow) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64SBBQcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBQcarrymask (FlagEQ)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagLT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagLT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagGT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagGT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQconst x [c] (FlagEQ)) // result: (SUBQconstborrow x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SETA(v *Value) bool { v_0 := v.Args[0] // match: (SETA (InvertFlags x)) // result: (SETB x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETA (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAE(v *Value) bool { v_0 := v.Args[0] // match: (SETAE (TESTQ x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTL x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTW x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTB x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (InvertFlags x)) // result: (SETBE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETAstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETB(v *Value) bool { v_0 := v.Args[0] // match: (SETB (TESTQ x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTL x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTW x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTB x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (BTLconst [0] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64BTLconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (BTQconst [0] x)) // result: (ANDQconst [1] x) for { if v_0.Op != OpAMD64BTQconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (InvertFlags x)) // result: (SETA x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBE(v *Value) bool { v_0 := v.Args[0] // match: (SETBE (InvertFlags x)) // result: (SETAE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETBE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAE (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAE (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETNE (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETEQ (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) // result: (SETEQ (Select1 blsr)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { continue } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL s:(Select0 blsr:(BLSRL _)) s)) // result: (SETEQ (Select1 blsr)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_0_1 { continue } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg(v0) return true } break } return false } func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETEQstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETG(v *Value) bool { v_0 := v.Args[0] // match: (SETG (InvertFlags x)) // result: (SETL x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETG (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGE(v *Value) bool { v_0 := v.Args[0] // match: (SETGE (InvertFlags x)) // result: (SETLE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETL(v *Value) bool { v_0 := v.Args[0] // match: (SETL (InvertFlags x)) // result: (SETG x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLE(v *Value) bool { v_0 := v.Args[0] // match: (SETLE (InvertFlags x)) // result: (SETGE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETLE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNE(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETNE (TESTBconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTBconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTWconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTWconst || auxIntToInt16(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETB (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETB (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETEQ (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (InvertFlags x)) // result: (SETNE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETNE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) // result: (SETNE (Select1 blsr)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { continue } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg(v0) return true } break } // match: (SETNE (TESTL s:(Select0 blsr:(BLSRL _)) s)) // result: (SETNE (Select1 blsr)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_0_1 { continue } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg(v0) return true } break } return false } func rewriteValueAMD64_OpAMD64SETNEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETNEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (MOVLconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL l:(MOVLload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHLXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLLconst [1] (SHRLconst [1] x)) // result: (BTRLconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLLconst [d] (MOVLconst [c])) // result: (MOVLconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (MOVLconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ l:(MOVQload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHLXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLQconst [1] (SHRQconst [1] x)) // result: (BTRQconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLQconst [d] (MOVQconst [c])) // result: (MOVQconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c << uint64(d)) return true } // match: (SHLQconst [d] (MOVLconst [c])) // result: (MOVQconst [int64(c) << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHLXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHLLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHLXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SHLXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRB x (MOVQconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB _ (MOVQconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRBconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRBconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (MOVLconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL l:(MOVLload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHRXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRLconst [1] (SHLLconst [1] x)) // result: (BTRLconst [31] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(31) v.AddArg(x) return true } // match: (SHRLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (MOVLconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ l:(MOVQload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHRXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRQconst [1] (SHLQconst [1] x)) // result: (BTRQconst [63] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(63) v.AddArg(x) return true } // match: (SHRQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRW x (MOVQconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW _ (MOVQconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRWconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHRXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHRLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHRXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SHRXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBL x (MOVLconst [c])) // result: (SUBLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SUBLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // result: (NEGL (SUBLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBLconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (SUBLconst [c] x) // result: (ADDLconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } } func rewriteValueAMD64_OpAMD64SUBLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (SUBL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconst x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } // match: (SUBQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (NEGQ (SUBQconst x [int32(c)])) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBQload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQborrow(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQborrow x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconstborrow x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SUBQconst [c] x) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } // match: (SUBQconst (MOVQconst [d]) [c]) // result: (MOVQconst [d-int64(c)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d - int64(c)) return true } // match: (SUBQconst (SUBQconst x [d]) [c]) // cond: is32Bit(int64(-c)-int64(d)) // result: (ADDQconst [-c-d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SUBQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(-c) - int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c - d) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (SUBQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (SUBSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (SUBSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64TESTB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [int8(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } break } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVBload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTBconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTBconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTL a:(ANDLload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTL (MOVLload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDLload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTL) v0 := b.NewValue0(a.Pos, OpAMD64MOVLload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTLconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTLconst [c] (MOVLconst [c])) // cond: c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTLconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTL x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTL) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (TESTQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { continue } v.reset(OpAMD64TESTQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTQ a:(ANDQload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTQ (MOVQload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDQload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTQ) v0 := b.NewValue0(a.Pos, OpAMD64MOVQload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTQconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTQconst [-1] x) // cond: x.Op != OpAMD64MOVQconst // result: (TESTQ x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVQconst) { break } v.reset(OpAMD64TESTQ) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [int16(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } break } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVWload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTWconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTWconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64XADDLlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDLlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XADDQlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDQlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGL(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGL [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGQ [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTCL) v.AddArg2(x, y) return true } break } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORLconst(v *Value) bool { v_0 := v.Args[0] // match: (XORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORLconst [1] (SETNE x)) // result: (SETEQ x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETNE { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (XORLconst [1] (SETEQ x)) // result: (SETNE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETEQ { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (XORLconst [1] (SETL x)) // result: (SETGE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETL { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (XORLconst [1] (SETGE x)) // result: (SETL x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETGE { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (XORLconst [1] (SETLE x)) // result: (SETG x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETLE { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (XORLconst [1] (SETG x)) // result: (SETLE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETG { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (XORLconst [1] (SETB x)) // result: (SETAE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETB { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (XORLconst [1] (SETAE x)) // result: (SETB x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETAE { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (XORLconst [1] (SETBE x)) // result: (SETA x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETBE { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (XORLconst [1] (SETA x)) // result: (SETBE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETA { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (XORLconst [c] (XORLconst [d] x)) // result: (XORLconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORLconst [c] (BTCLconst [d] x)) // result: (XORLconst [c ^ 1<= 128 // result: (BTCQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (XORQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORQconst(v *Value) bool { v_0 := v.Args[0] // match: (XORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORQconst [c] (XORQconst [d] x)) // result: (XORQconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORQconst [c] (BTCQconst [d] x)) // cond: is32Bit(int64(c) ^ 1< val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore64(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore64 ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore8 ptr val mem) // result: (Select1 (XCHGB val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStorePtrNoWB(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStorePtrNoWB ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen16 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen16 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVWQZX x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, x.Type) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) v1.AuxInt = int32ToAuxInt(1) v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v2.AddArg(x) v1.AddArg2(v2, v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (BitLen32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // cond: buildcfg.GOAMD64 < 3 // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(1) v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) v1 := b.NewValue0(v.Pos, OpSelect0, t) v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v3.AuxInt = int64ToAuxInt(-1) v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4.AddArg(v2) v0.AddArg3(v1, v3, v4) v.AddArg(v0) return true } // match: (BitLen64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-64] (LZCNTQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-64) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTQ, typ.UInt64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen8 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen8 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVBQZX x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, x.Type) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCeil(v *Value) bool { v_0 := v.Args[0] // match: (Ceil x) // result: (ROUNDSD [2] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(2) v.AddArg(x) return true } } func rewriteValueAMD64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (CondSelect x y (SETEQ cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is32BitInt(t) // result: (CMOVLEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is32BitInt(t) // result: (CMOVLNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is32BitInt(t) // result: (CMOVLLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is32BitInt(t) // result: (CMOVLGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is32BitInt(t) // result: (CMOVLLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is32BitInt(t) // result: (CMOVLGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is32BitInt(t) // result: (CMOVLHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is32BitInt(t) // result: (CMOVLCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is32BitInt(t) // result: (CMOVLCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is32BitInt(t) // result: (CMOVLLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is32BitInt(t) // result: (CMOVLEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is32BitInt(t) // result: (CMOVLNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is32BitInt(t) // result: (CMOVLGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is32BitInt(t) // result: (CMOVLGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is16BitInt(t) // result: (CMOVWEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is16BitInt(t) // result: (CMOVWNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is16BitInt(t) // result: (CMOVWLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is16BitInt(t) // result: (CMOVWGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is16BitInt(t) // result: (CMOVWLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is16BitInt(t) // result: (CMOVWGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is16BitInt(t) // result: (CMOVWHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is16BitInt(t) // result: (CMOVWCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is16BitInt(t) // result: (CMOVWCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is16BitInt(t) // result: (CMOVWLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is16BitInt(t) // result: (CMOVWEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is16BitInt(t) // result: (CMOVWNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is16BitInt(t) // result: (CMOVWGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is16BitInt(t) // result: (CMOVWGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 1 // result: (CondSelect x y (MOVBQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 1) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 2 // result: (CondSelect x y (MOVWQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 2) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 4 // result: (CondSelect x y (MOVLQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 4) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { break } v.reset(OpAMD64CMOVQNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) // result: (CMOVLNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) // result: (CMOVWNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } return false } func rewriteValueAMD64_OpConst16(v *Value) bool { // match: (Const16 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt16(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConst8(v *Value) bool { // match: (Const8 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt8(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConstBool(v *Value) bool { // match: (ConstBool [c]) // result: (MOVLconst [b2i32(c)]) for { c := auxIntToBool(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(b2i32(c)) return true } } func rewriteValueAMD64_OpConstNil(v *Value) bool { // match: (ConstNil ) // result: (MOVQconst [0]) for { v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } } func rewriteValueAMD64_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (BSFL (BTSLconst [16] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(16) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz16NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ (BTSQconst [32] x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) v1.AuxInt = int8ToAuxInt(32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz32NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64 x) // cond: buildcfg.GOAMD64 < 3 // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v3.AddArg(v1) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueAMD64_OpCtz64NonZero(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ x)) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (BSFL (BTSLconst [ 8] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 [a] x y) // result: (Select0 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (Select0 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32 [a] x y) // result: (Select0 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32u x y) // result: (Select0 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64 [a] x y) // result: (Select0 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64u x y) // result: (Select0 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq16 x y) // result: (SETEQ (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32 x y) // result: (SETEQ (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32F x y) // result: (SETEQF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64 x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64F x y) // result: (SETEQF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq8 x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqB x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqPtr x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpFMA(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMA x y z) // result: (VFMADD231SD z x y) for { x := v_0 y := v_1 z := v_2 v.reset(OpAMD64VFMADD231SD) v.AddArg3(z, x, y) return true } } func rewriteValueAMD64_OpFloor(v *Value) bool { v_0 := v.Args[0] // match: (Floor x) // result: (ROUNDSD [1] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpGetG(v *Value) bool { v_0 := v.Args[0] // match: (GetG mem) // cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal // result: (LoweredGetG mem) for { mem := v_0 if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) { break } v.reset(OpAMD64LoweredGetG) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (HasCPUFeature {s}) // result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s}))) for { s := auxToSym(v.Aux) v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64) v1.Aux = symToAux(s) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsInBounds idx len) // result: (SETB (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsNonNil(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (IsNonNil p) // result: (SETNE (TESTQ p p)) for { p := v_0 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) v0.AddArg2(p, p) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsSliceInBounds idx len) // result: (SETBE (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16 x y) // result: (SETLE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16U x y) // result: (SETBE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32 x y) // result: (SETLE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32F x y) // result: (SETGEF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32U x y) // result: (SETBE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64 x y) // result: (SETLE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64F x y) // result: (SETGEF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64U x y) // result: (SETBE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8 x y) // result: (SETLE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8U x y) // result: (SETBE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16 x y) // result: (SETL (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16U x y) // result: (SETB (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 x y) // result: (SETL (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32F x y) // result: (SETGF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32U x y) // result: (SETB (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 x y) // result: (SETL (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64F x y) // result: (SETGF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64U x y) // result: (SETB (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8 x y) // result: (SETL (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8U x y) // result: (SETB (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVQload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64MOVQload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) // result: (MOVLload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t)) { break } v.reset(OpAMD64MOVLload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t)) { break } v.reset(OpAMD64MOVWload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(OpAMD64MOVBload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitFloat(t)) { break } v.reset(OpAMD64MOVSSload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitFloat(t)) { break } v.reset(OpAMD64MOVSDload) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpLocalAddr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (LocalAddr {sym} base mem) // cond: t.Elem().HasPointers() // result: (LEAQ {sym} (SPanchored base mem)) for { t := v.Type sym := auxToSym(v.Aux) base := v_0 mem := v_1 if !(t.Elem().HasPointers()) { break } v.reset(OpAMD64LEAQ) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr) v0.AddArg2(base, mem) v.AddArg(v0) return true } // match: (LocalAddr {sym} base _) // cond: !t.Elem().HasPointers() // result: (LEAQ {sym} base) for { t := v.Type sym := auxToSym(v.Aux) base := v_0 if !(!t.Elem().HasPointers()) { break } v.reset(OpAMD64LEAQ) v.Aux = symToAux(sym) v.AddArg(base) return true } return false } func rewriteValueAMD64_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16 [a] x y) // result: (Select1 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Select1 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32 [a] x y) // result: (Select1 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (Select1 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64 [a] x y) // result: (Select1 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (Select1 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [2] dst src mem) // result: (MOVWstore dst (MOVWload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [4] dst src mem) // result: (MOVLstore dst (MOVLload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [8] dst src mem) // result: (MOVQstore dst (MOVQload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVQstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: config.useSSE // result: (MOVOstore dst (MOVOload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: !config.useSSE // result: (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [32] dst src mem) // result: (Move [16] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpMove) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [48] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 48 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [64] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [32]) (OffPtr src [32]) (Move [32] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 64 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(32) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(32) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(32) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(2) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [6] dst src mem) // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [7] dst src mem) // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [10] dst src mem) // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [12] dst src mem) // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s == 11 || s >= 13 && s <= 15 // result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s == 11 || s >= 13 && s <= 15) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(int32(s - 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(int32(s - 8)) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 <= 8 // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 <= 8) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVOstore dst (MOVOload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AuxInt = int32ToAuxInt(8) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AuxInt = int32ToAuxInt(8) v3.AddArg2(src, mem) v4 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v5 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v5.AddArg2(src, mem) v4.AddArg3(dst, v5, mem) v2.AddArg3(dst, v3, v4) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s) // result: (DUFFCOPY [s] dst src mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s)) { break } v.reset(OpAMD64DUFFCOPY) v.AuxInt = int64ToAuxInt(s) v.AddArg3(dst, src, mem) return true } // match: (Move [s] dst src mem) // cond: (s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s) // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !((s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s)) { break } v.reset(OpAMD64REPMOVSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v.AddArg4(dst, src, v0, mem) return true } return false } func rewriteValueAMD64_OpNeg32F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg32F x) // result: (PXOR x (MOVSSconst [float32(math.Copysign(0, -1))])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1))) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeg64F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg64F x) // result: (PXOR x (MOVSDconst [math.Copysign(0, -1)])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) v0.AuxInt = float64ToAuxInt(math.Copysign(0, -1)) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq16 x y) // result: (SETNE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32 x y) // result: (SETNE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32F x y) // result: (SETNEF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64 x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64F x y) // result: (SETNEF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq8 x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqB x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqPtr x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNot(v *Value) bool { v_0 := v.Args[0] // match: (Not x) // result: (XORLconst [1] x) for { x := v_0 v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // cond: is32Bit(off) // result: (ADDQconst [int32(off)] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 if !(is32Bit(off)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(off)) v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDQ (MOVQconst [off]) ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(off) v.AddArg2(v0, ptr) return true } } func rewriteValueAMD64_OpPanicBounds(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 0) { break } v.reset(OpAMD64LoweredPanicBoundsA) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 1) { break } v.reset(OpAMD64LoweredPanicBoundsB) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 2) { break } v.reset(OpAMD64LoweredPanicBoundsC) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } return false } func rewriteValueAMD64_OpPopCount16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTL (MOVWQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpPopCount8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTL (MOVBQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpRoundToEven(v *Value) bool { v_0 := v.Args[0] // match: (RoundToEven x) // result: (ROUNDSD [0] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } } func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpSelect0(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uover x y)) // result: (Select0 (MULQU x y)) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Mul32uover x y)) // result: (Select0 (MULLU x y)) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y c)) // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst32 val tuple)) // result: (ADDL val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDL) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } // match: (Select0 (AddTupleFirst64 val tuple)) // result: (ADDQ val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } return false } func rewriteValueAMD64_OpSelect1(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uover x y)) // result: (SETO (Select1 (MULQU x y))) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul32uover x y)) // result: (SETO (Select1 (MULLU x y))) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Add64carry x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (NEGLflags (MOVQconst [0]))) // result: (FlagEQ) for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 0 { break } v.reset(OpAMD64FlagEQ) return true } // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) // result: x for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64SBBQcarrymask { break } x := v_0_0_0.Args[0] v.copyOf(x) return true } // match: (Select1 (AddTupleFirst32 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } // match: (Select1 (AddTupleFirst64 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } return false } func rewriteValueAMD64_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem))))) // cond: sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call) // result: (Move [sc.Val64()] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpAMD64MOVQstoreconst { break } sc := auxIntToValAndOff(s1.AuxInt) _ = s1.Args[1] s2 := s1.Args[1] if s2.Op != OpAMD64MOVQstore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpAMD64MOVQstore { break } mem := s3.Args[2] dst := s3.Args[1] if !(sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sc.Val64()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem)) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpAMD64MOVQconst { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } return false } func rewriteValueAMD64_OpSlicemask(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Slicemask x) // result: (SARQconst (NEGQ x) [63]) for { t := v.Type x := v_0 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(63) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpSpectreIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreIndex x y) // result: (CMOVQCC x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQCC) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpSpectreSliceIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreSliceIndex x y) // result: (CMOVQHI x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQHI) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && t.IsFloat() // result: (MOVSDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && t.IsFloat()) { break } v.reset(OpAMD64MOVSDstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && t.IsFloat() // result: (MOVSSstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && t.IsFloat()) { break } v.reset(OpAMD64MOVSSstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && !t.IsFloat() // result: (MOVQstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && !t.IsFloat()) { break } v.reset(OpAMD64MOVQstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && !t.IsFloat() // result: (MOVLstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && !t.IsFloat()) { break } v.reset(OpAMD64MOVLstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 2 // result: (MOVWstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 2) { break } v.reset(OpAMD64MOVWstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 1 // result: (MOVBstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 1) { break } v.reset(OpAMD64MOVBstore) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpTrunc(v *Value) bool { v_0 := v.Args[0] // match: (Trunc x) // result: (ROUNDSD [3] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(3) v.AddArg(x) return true } } func rewriteValueAMD64_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [0] _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_1 v.copyOf(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [2] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [4] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [8] destptr mem) // result: (MOVQstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 2)) v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [5] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [6] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [7] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 3)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%8 != 0 && s > 8 && !config.useSSE // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%8 != 0 && s > 8 && !config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%8) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [24] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 24 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [32] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 24)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 8 && s < 16 && config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,int32(s-8))] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 8 && s < 16 && config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, int32(s-8))) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [32] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [48] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [64] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,48)] destptr (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 48)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice // result: (DUFFZERO [s] destptr mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFZERO) v.AuxInt = int64ToAuxInt(s) v.AddArg2(destptr, mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0 // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !((s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0) { break } v.reset(OpAMD64REPSTOSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(0) v.AddArg4(destptr, v0, v1, mem) return true } return false } func rewriteBlockAMD64(b *Block) bool { typ := &b.Func.Config.Types switch b.Kind { case BlockAMD64EQ: // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (UGE (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (UGE (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (TESTQ s:(Select0 blsr:(BLSRQ _)) s) yes no) // result: (EQ (Select1 blsr) yes no) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { continue } v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) b.resetWithControl(BlockAMD64EQ, v0) return true } break } // match: (EQ (TESTL s:(Select0 blsr:(BLSRL _)) s) yes no) // result: (EQ (Select1 blsr) yes no) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_0_1 { continue } v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) b.resetWithControl(BlockAMD64EQ, v0) return true } break } case BlockAMD64GE: // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64GT: // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockIf: // match: (If (SETL cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64SETL { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (If (SETLE cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64SETLE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (If (SETG cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64SETG { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (If (SETGE cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64SETGE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (If (SETEQ cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64SETEQ { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (If (SETNE cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64SETNE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (If (SETB cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64SETB { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (If (SETBE cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64SETBE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (If (SETA cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETA { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETAE cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETAE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETO cmp) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64SETO { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (If (SETGF cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETGF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETGEF cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETGEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETEQF cmp) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64SETEQF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (If (SETNEF cmp) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64SETNEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (If cond yes no) // result: (NE (TESTB cond cond) yes no) for { cond := b.Controls[0] v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) v0.AddArg2(cond, cond) b.resetWithControl(BlockAMD64NE, v0) return true } case BlockJumpTable: // match: (JumpTable idx) // result: (JUMPTABLE {makeJumpTableSym(b)} idx (LEAQ {makeJumpTableSym(b)} (SB))) for { idx := b.Controls[0] v0 := b.NewValue0(b.Pos, OpAMD64LEAQ, typ.Uintptr) v0.Aux = symToAux(makeJumpTableSym(b)) v1 := b.NewValue0(b.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) b.resetWithControl2(BlockAMD64JUMPTABLE, idx, v0) b.Aux = symToAux(makeJumpTableSym(b)) return true } case BlockAMD64LE: // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64LT: // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETL { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETLE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETG { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQ { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETB { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETBE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETA { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETAE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETO { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (ULT (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (ULT (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } // match: (NE (TESTQ s:(Select0 blsr:(BLSRQ _)) s) yes no) // result: (NE (Select1 blsr) yes no) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { continue } v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) b.resetWithControl(BlockAMD64NE, v0) return true } break } // match: (NE (TESTL s:(Select0 blsr:(BLSRL _)) s) yes no) // result: (NE (Select1 blsr) yes no) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_0_1 { continue } v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) b.resetWithControl(BlockAMD64NE, v0) return true } break } case BlockAMD64UGE: // match: (UGE (TESTQ x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTL x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTW x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTB x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (UGE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (UGE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGT: // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (UGT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64ULE: // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (ULE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64ULT: // match: (ULT (TESTQ x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTL x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTW x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTB x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (ULT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- y -- // Code generated from _gen/AMD64.rules using 'go generate'; DO NOT EDIT. package ssa import "internal/buildcfg" import "math" import "cmd/internal/obj" import "cmd/compile/internal/types" func rewriteValueAMD64(v *Value) bool { switch v.Op { case OpAMD64ADCQ: return rewriteValueAMD64_OpAMD64ADCQ(v) case OpAMD64ADCQconst: return rewriteValueAMD64_OpAMD64ADCQconst(v) case OpAMD64ADDL: return rewriteValueAMD64_OpAMD64ADDL(v) case OpAMD64ADDLconst: return rewriteValueAMD64_OpAMD64ADDLconst(v) case OpAMD64ADDLconstmodify: return rewriteValueAMD64_OpAMD64ADDLconstmodify(v) case OpAMD64ADDLload: return rewriteValueAMD64_OpAMD64ADDLload(v) case OpAMD64ADDLmodify: return rewriteValueAMD64_OpAMD64ADDLmodify(v) case OpAMD64ADDQ: return rewriteValueAMD64_OpAMD64ADDQ(v) case OpAMD64ADDQcarry: return rewriteValueAMD64_OpAMD64ADDQcarry(v) case OpAMD64ADDQconst: return rewriteValueAMD64_OpAMD64ADDQconst(v) case OpAMD64ADDQconstmodify: return rewriteValueAMD64_OpAMD64ADDQconstmodify(v) case OpAMD64ADDQload: return rewriteValueAMD64_OpAMD64ADDQload(v) case OpAMD64ADDQmodify: return rewriteValueAMD64_OpAMD64ADDQmodify(v) case OpAMD64ADDSD: return rewriteValueAMD64_OpAMD64ADDSD(v) case OpAMD64ADDSDload: return rewriteValueAMD64_OpAMD64ADDSDload(v) case OpAMD64ADDSS: return rewriteValueAMD64_OpAMD64ADDSS(v) case OpAMD64ADDSSload: return rewriteValueAMD64_OpAMD64ADDSSload(v) case OpAMD64ANDL: return rewriteValueAMD64_OpAMD64ANDL(v) case OpAMD64ANDLconst: return rewriteValueAMD64_OpAMD64ANDLconst(v) case OpAMD64ANDLconstmodify: return rewriteValueAMD64_OpAMD64ANDLconstmodify(v) case OpAMD64ANDLload: return rewriteValueAMD64_OpAMD64ANDLload(v) case OpAMD64ANDLmodify: return rewriteValueAMD64_OpAMD64ANDLmodify(v) case OpAMD64ANDNL: return rewriteValueAMD64_OpAMD64ANDNL(v) case OpAMD64ANDNQ: return rewriteValueAMD64_OpAMD64ANDNQ(v) case OpAMD64ANDQ: return rewriteValueAMD64_OpAMD64ANDQ(v) case OpAMD64ANDQconst: return rewriteValueAMD64_OpAMD64ANDQconst(v) case OpAMD64ANDQconstmodify: return rewriteValueAMD64_OpAMD64ANDQconstmodify(v) case OpAMD64ANDQload: return rewriteValueAMD64_OpAMD64ANDQload(v) case OpAMD64ANDQmodify: return rewriteValueAMD64_OpAMD64ANDQmodify(v) case OpAMD64BSFQ: return rewriteValueAMD64_OpAMD64BSFQ(v) case OpAMD64BSWAPL: return rewriteValueAMD64_OpAMD64BSWAPL(v) case OpAMD64BSWAPQ: return rewriteValueAMD64_OpAMD64BSWAPQ(v) case OpAMD64BTCLconst: return rewriteValueAMD64_OpAMD64BTCLconst(v) case OpAMD64BTCQconst: return rewriteValueAMD64_OpAMD64BTCQconst(v) case OpAMD64BTLconst: return rewriteValueAMD64_OpAMD64BTLconst(v) case OpAMD64BTQconst: return rewriteValueAMD64_OpAMD64BTQconst(v) case OpAMD64BTRLconst: return rewriteValueAMD64_OpAMD64BTRLconst(v) case OpAMD64BTRQconst: return rewriteValueAMD64_OpAMD64BTRQconst(v) case OpAMD64BTSLconst: return rewriteValueAMD64_OpAMD64BTSLconst(v) case OpAMD64BTSQconst: return rewriteValueAMD64_OpAMD64BTSQconst(v) case OpAMD64CMOVLCC: return rewriteValueAMD64_OpAMD64CMOVLCC(v) case OpAMD64CMOVLCS: return rewriteValueAMD64_OpAMD64CMOVLCS(v) case OpAMD64CMOVLEQ: return rewriteValueAMD64_OpAMD64CMOVLEQ(v) case OpAMD64CMOVLGE: return rewriteValueAMD64_OpAMD64CMOVLGE(v) case OpAMD64CMOVLGT: return rewriteValueAMD64_OpAMD64CMOVLGT(v) case OpAMD64CMOVLHI: return rewriteValueAMD64_OpAMD64CMOVLHI(v) case OpAMD64CMOVLLE: return rewriteValueAMD64_OpAMD64CMOVLLE(v) case OpAMD64CMOVLLS: return rewriteValueAMD64_OpAMD64CMOVLLS(v) case OpAMD64CMOVLLT: return rewriteValueAMD64_OpAMD64CMOVLLT(v) case OpAMD64CMOVLNE: return rewriteValueAMD64_OpAMD64CMOVLNE(v) case OpAMD64CMOVQCC: return rewriteValueAMD64_OpAMD64CMOVQCC(v) case OpAMD64CMOVQCS: return rewriteValueAMD64_OpAMD64CMOVQCS(v) case OpAMD64CMOVQEQ: return rewriteValueAMD64_OpAMD64CMOVQEQ(v) case OpAMD64CMOVQGE: return rewriteValueAMD64_OpAMD64CMOVQGE(v) case OpAMD64CMOVQGT: return rewriteValueAMD64_OpAMD64CMOVQGT(v) case OpAMD64CMOVQHI: return rewriteValueAMD64_OpAMD64CMOVQHI(v) case OpAMD64CMOVQLE: return rewriteValueAMD64_OpAMD64CMOVQLE(v) case OpAMD64CMOVQLS: return rewriteValueAMD64_OpAMD64CMOVQLS(v) case OpAMD64CMOVQLT: return rewriteValueAMD64_OpAMD64CMOVQLT(v) case OpAMD64CMOVQNE: return rewriteValueAMD64_OpAMD64CMOVQNE(v) case OpAMD64CMOVWCC: return rewriteValueAMD64_OpAMD64CMOVWCC(v) case OpAMD64CMOVWCS: return rewriteValueAMD64_OpAMD64CMOVWCS(v) case OpAMD64CMOVWEQ: return rewriteValueAMD64_OpAMD64CMOVWEQ(v) case OpAMD64CMOVWGE: return rewriteValueAMD64_OpAMD64CMOVWGE(v) case OpAMD64CMOVWGT: return rewriteValueAMD64_OpAMD64CMOVWGT(v) case OpAMD64CMOVWHI: return rewriteValueAMD64_OpAMD64CMOVWHI(v) case OpAMD64CMOVWLE: return rewriteValueAMD64_OpAMD64CMOVWLE(v) case OpAMD64CMOVWLS: return rewriteValueAMD64_OpAMD64CMOVWLS(v) case OpAMD64CMOVWLT: return rewriteValueAMD64_OpAMD64CMOVWLT(v) case OpAMD64CMOVWNE: return rewriteValueAMD64_OpAMD64CMOVWNE(v) case OpAMD64CMPB: return rewriteValueAMD64_OpAMD64CMPB(v) case OpAMD64CMPBconst: return rewriteValueAMD64_OpAMD64CMPBconst(v) case OpAMD64CMPBconstload: return rewriteValueAMD64_OpAMD64CMPBconstload(v) case OpAMD64CMPBload: return rewriteValueAMD64_OpAMD64CMPBload(v) case OpAMD64CMPL: return rewriteValueAMD64_OpAMD64CMPL(v) case OpAMD64CMPLconst: return rewriteValueAMD64_OpAMD64CMPLconst(v) case OpAMD64CMPLconstload: return rewriteValueAMD64_OpAMD64CMPLconstload(v) case OpAMD64CMPLload: return rewriteValueAMD64_OpAMD64CMPLload(v) case OpAMD64CMPQ: return rewriteValueAMD64_OpAMD64CMPQ(v) case OpAMD64CMPQconst: return rewriteValueAMD64_OpAMD64CMPQconst(v) case OpAMD64CMPQconstload: return rewriteValueAMD64_OpAMD64CMPQconstload(v) case OpAMD64CMPQload: return rewriteValueAMD64_OpAMD64CMPQload(v) case OpAMD64CMPW: return rewriteValueAMD64_OpAMD64CMPW(v) case OpAMD64CMPWconst: return rewriteValueAMD64_OpAMD64CMPWconst(v) case OpAMD64CMPWconstload: return rewriteValueAMD64_OpAMD64CMPWconstload(v) case OpAMD64CMPWload: return rewriteValueAMD64_OpAMD64CMPWload(v) case OpAMD64CMPXCHGLlock: return rewriteValueAMD64_OpAMD64CMPXCHGLlock(v) case OpAMD64CMPXCHGQlock: return rewriteValueAMD64_OpAMD64CMPXCHGQlock(v) case OpAMD64DIVSD: return rewriteValueAMD64_OpAMD64DIVSD(v) case OpAMD64DIVSDload: return rewriteValueAMD64_OpAMD64DIVSDload(v) case OpAMD64DIVSS: return rewriteValueAMD64_OpAMD64DIVSS(v) case OpAMD64DIVSSload: return rewriteValueAMD64_OpAMD64DIVSSload(v) case OpAMD64HMULL: return rewriteValueAMD64_OpAMD64HMULL(v) case OpAMD64HMULLU: return rewriteValueAMD64_OpAMD64HMULLU(v) case OpAMD64HMULQ: return rewriteValueAMD64_OpAMD64HMULQ(v) case OpAMD64HMULQU: return rewriteValueAMD64_OpAMD64HMULQU(v) case OpAMD64LEAL: return rewriteValueAMD64_OpAMD64LEAL(v) case OpAMD64LEAL1: return rewriteValueAMD64_OpAMD64LEAL1(v) case OpAMD64LEAL2: return rewriteValueAMD64_OpAMD64LEAL2(v) case OpAMD64LEAL4: return rewriteValueAMD64_OpAMD64LEAL4(v) case OpAMD64LEAL8: return rewriteValueAMD64_OpAMD64LEAL8(v) case OpAMD64LEAQ: return rewriteValueAMD64_OpAMD64LEAQ(v) case OpAMD64LEAQ1: return rewriteValueAMD64_OpAMD64LEAQ1(v) case OpAMD64LEAQ2: return rewriteValueAMD64_OpAMD64LEAQ2(v) case OpAMD64LEAQ4: return rewriteValueAMD64_OpAMD64LEAQ4(v) case OpAMD64LEAQ8: return rewriteValueAMD64_OpAMD64LEAQ8(v) case OpAMD64MOVBELstore: return rewriteValueAMD64_OpAMD64MOVBELstore(v) case OpAMD64MOVBEQstore: return rewriteValueAMD64_OpAMD64MOVBEQstore(v) case OpAMD64MOVBEWstore: return rewriteValueAMD64_OpAMD64MOVBEWstore(v) case OpAMD64MOVBQSX: return rewriteValueAMD64_OpAMD64MOVBQSX(v) case OpAMD64MOVBQSXload: return rewriteValueAMD64_OpAMD64MOVBQSXload(v) case OpAMD64MOVBQZX: return rewriteValueAMD64_OpAMD64MOVBQZX(v) case OpAMD64MOVBatomicload: return rewriteValueAMD64_OpAMD64MOVBatomicload(v) case OpAMD64MOVBload: return rewriteValueAMD64_OpAMD64MOVBload(v) case OpAMD64MOVBstore: return rewriteValueAMD64_OpAMD64MOVBstore(v) case OpAMD64MOVBstoreconst: return rewriteValueAMD64_OpAMD64MOVBstoreconst(v) case OpAMD64MOVLQSX: return rewriteValueAMD64_OpAMD64MOVLQSX(v) case OpAMD64MOVLQSXload: return rewriteValueAMD64_OpAMD64MOVLQSXload(v) case OpAMD64MOVLQZX: return rewriteValueAMD64_OpAMD64MOVLQZX(v) case OpAMD64MOVLatomicload: return rewriteValueAMD64_OpAMD64MOVLatomicload(v) case OpAMD64MOVLf2i: return rewriteValueAMD64_OpAMD64MOVLf2i(v) case OpAMD64MOVLi2f: return rewriteValueAMD64_OpAMD64MOVLi2f(v) case OpAMD64MOVLload: return rewriteValueAMD64_OpAMD64MOVLload(v) case OpAMD64MOVLstore: return rewriteValueAMD64_OpAMD64MOVLstore(v) case OpAMD64MOVLstoreconst: return rewriteValueAMD64_OpAMD64MOVLstoreconst(v) case OpAMD64MOVOload: return rewriteValueAMD64_OpAMD64MOVOload(v) case OpAMD64MOVOstore: return rewriteValueAMD64_OpAMD64MOVOstore(v) case OpAMD64MOVOstoreconst: return rewriteValueAMD64_OpAMD64MOVOstoreconst(v) case OpAMD64MOVQatomicload: return rewriteValueAMD64_OpAMD64MOVQatomicload(v) case OpAMD64MOVQf2i: return rewriteValueAMD64_OpAMD64MOVQf2i(v) case OpAMD64MOVQi2f: return rewriteValueAMD64_OpAMD64MOVQi2f(v) case OpAMD64MOVQload: return rewriteValueAMD64_OpAMD64MOVQload(v) case OpAMD64MOVQstore: return rewriteValueAMD64_OpAMD64MOVQstore(v) case OpAMD64MOVQstoreconst: return rewriteValueAMD64_OpAMD64MOVQstoreconst(v) case OpAMD64MOVSDload: return rewriteValueAMD64_OpAMD64MOVSDload(v) case OpAMD64MOVSDstore: return rewriteValueAMD64_OpAMD64MOVSDstore(v) case OpAMD64MOVSSload: return rewriteValueAMD64_OpAMD64MOVSSload(v) case OpAMD64MOVSSstore: return rewriteValueAMD64_OpAMD64MOVSSstore(v) case OpAMD64MOVWQSX: return rewriteValueAMD64_OpAMD64MOVWQSX(v) case OpAMD64MOVWQSXload: return rewriteValueAMD64_OpAMD64MOVWQSXload(v) case OpAMD64MOVWQZX: return rewriteValueAMD64_OpAMD64MOVWQZX(v) case OpAMD64MOVWload: return rewriteValueAMD64_OpAMD64MOVWload(v) case OpAMD64MOVWstore: return rewriteValueAMD64_OpAMD64MOVWstore(v) case OpAMD64MOVWstoreconst: return rewriteValueAMD64_OpAMD64MOVWstoreconst(v) case OpAMD64MULL: return rewriteValueAMD64_OpAMD64MULL(v) case OpAMD64MULLconst: return rewriteValueAMD64_OpAMD64MULLconst(v) case OpAMD64MULQ: return rewriteValueAMD64_OpAMD64MULQ(v) case OpAMD64MULQconst: return rewriteValueAMD64_OpAMD64MULQconst(v) case OpAMD64MULSD: return rewriteValueAMD64_OpAMD64MULSD(v) case OpAMD64MULSDload: return rewriteValueAMD64_OpAMD64MULSDload(v) case OpAMD64MULSS: return rewriteValueAMD64_OpAMD64MULSS(v) case OpAMD64MULSSload: return rewriteValueAMD64_OpAMD64MULSSload(v) case OpAMD64NEGL: return rewriteValueAMD64_OpAMD64NEGL(v) case OpAMD64NEGQ: return rewriteValueAMD64_OpAMD64NEGQ(v) case OpAMD64NOTL: return rewriteValueAMD64_OpAMD64NOTL(v) case OpAMD64NOTQ: return rewriteValueAMD64_OpAMD64NOTQ(v) case OpAMD64ORL: return rewriteValueAMD64_OpAMD64ORL(v) case OpAMD64ORLconst: return rewriteValueAMD64_OpAMD64ORLconst(v) case OpAMD64ORLconstmodify: return rewriteValueAMD64_OpAMD64ORLconstmodify(v) case OpAMD64ORLload: return rewriteValueAMD64_OpAMD64ORLload(v) case OpAMD64ORLmodify: return rewriteValueAMD64_OpAMD64ORLmodify(v) case OpAMD64ORQ: return rewriteValueAMD64_OpAMD64ORQ(v) case OpAMD64ORQconst: return rewriteValueAMD64_OpAMD64ORQconst(v) case OpAMD64ORQconstmodify: return rewriteValueAMD64_OpAMD64ORQconstmodify(v) case OpAMD64ORQload: return rewriteValueAMD64_OpAMD64ORQload(v) case OpAMD64ORQmodify: return rewriteValueAMD64_OpAMD64ORQmodify(v) case OpAMD64ROLB: return rewriteValueAMD64_OpAMD64ROLB(v) case OpAMD64ROLBconst: return rewriteValueAMD64_OpAMD64ROLBconst(v) case OpAMD64ROLL: return rewriteValueAMD64_OpAMD64ROLL(v) case OpAMD64ROLLconst: return rewriteValueAMD64_OpAMD64ROLLconst(v) case OpAMD64ROLQ: return rewriteValueAMD64_OpAMD64ROLQ(v) case OpAMD64ROLQconst: return rewriteValueAMD64_OpAMD64ROLQconst(v) case OpAMD64ROLW: return rewriteValueAMD64_OpAMD64ROLW(v) case OpAMD64ROLWconst: return rewriteValueAMD64_OpAMD64ROLWconst(v) case OpAMD64RORB: return rewriteValueAMD64_OpAMD64RORB(v) case OpAMD64RORL: return rewriteValueAMD64_OpAMD64RORL(v) case OpAMD64RORQ: return rewriteValueAMD64_OpAMD64RORQ(v) case OpAMD64RORW: return rewriteValueAMD64_OpAMD64RORW(v) case OpAMD64SARB: return rewriteValueAMD64_OpAMD64SARB(v) case OpAMD64SARBconst: return rewriteValueAMD64_OpAMD64SARBconst(v) case OpAMD64SARL: return rewriteValueAMD64_OpAMD64SARL(v) case OpAMD64SARLconst: return rewriteValueAMD64_OpAMD64SARLconst(v) case OpAMD64SARQ: return rewriteValueAMD64_OpAMD64SARQ(v) case OpAMD64SARQconst: return rewriteValueAMD64_OpAMD64SARQconst(v) case OpAMD64SARW: return rewriteValueAMD64_OpAMD64SARW(v) case OpAMD64SARWconst: return rewriteValueAMD64_OpAMD64SARWconst(v) case OpAMD64SARXLload: return rewriteValueAMD64_OpAMD64SARXLload(v) case OpAMD64SARXQload: return rewriteValueAMD64_OpAMD64SARXQload(v) case OpAMD64SBBLcarrymask: return rewriteValueAMD64_OpAMD64SBBLcarrymask(v) case OpAMD64SBBQ: return rewriteValueAMD64_OpAMD64SBBQ(v) case OpAMD64SBBQcarrymask: return rewriteValueAMD64_OpAMD64SBBQcarrymask(v) case OpAMD64SBBQconst: return rewriteValueAMD64_OpAMD64SBBQconst(v) case OpAMD64SETA: return rewriteValueAMD64_OpAMD64SETA(v) case OpAMD64SETAE: return rewriteValueAMD64_OpAMD64SETAE(v) case OpAMD64SETAEstore: return rewriteValueAMD64_OpAMD64SETAEstore(v) case OpAMD64SETAstore: return rewriteValueAMD64_OpAMD64SETAstore(v) case OpAMD64SETB: return rewriteValueAMD64_OpAMD64SETB(v) case OpAMD64SETBE: return rewriteValueAMD64_OpAMD64SETBE(v) case OpAMD64SETBEstore: return rewriteValueAMD64_OpAMD64SETBEstore(v) case OpAMD64SETBstore: return rewriteValueAMD64_OpAMD64SETBstore(v) case OpAMD64SETEQ: return rewriteValueAMD64_OpAMD64SETEQ(v) case OpAMD64SETEQstore: return rewriteValueAMD64_OpAMD64SETEQstore(v) case OpAMD64SETG: return rewriteValueAMD64_OpAMD64SETG(v) case OpAMD64SETGE: return rewriteValueAMD64_OpAMD64SETGE(v) case OpAMD64SETGEstore: return rewriteValueAMD64_OpAMD64SETGEstore(v) case OpAMD64SETGstore: return rewriteValueAMD64_OpAMD64SETGstore(v) case OpAMD64SETL: return rewriteValueAMD64_OpAMD64SETL(v) case OpAMD64SETLE: return rewriteValueAMD64_OpAMD64SETLE(v) case OpAMD64SETLEstore: return rewriteValueAMD64_OpAMD64SETLEstore(v) case OpAMD64SETLstore: return rewriteValueAMD64_OpAMD64SETLstore(v) case OpAMD64SETNE: return rewriteValueAMD64_OpAMD64SETNE(v) case OpAMD64SETNEstore: return rewriteValueAMD64_OpAMD64SETNEstore(v) case OpAMD64SHLL: return rewriteValueAMD64_OpAMD64SHLL(v) case OpAMD64SHLLconst: return rewriteValueAMD64_OpAMD64SHLLconst(v) case OpAMD64SHLQ: return rewriteValueAMD64_OpAMD64SHLQ(v) case OpAMD64SHLQconst: return rewriteValueAMD64_OpAMD64SHLQconst(v) case OpAMD64SHLXLload: return rewriteValueAMD64_OpAMD64SHLXLload(v) case OpAMD64SHLXQload: return rewriteValueAMD64_OpAMD64SHLXQload(v) case OpAMD64SHRB: return rewriteValueAMD64_OpAMD64SHRB(v) case OpAMD64SHRBconst: return rewriteValueAMD64_OpAMD64SHRBconst(v) case OpAMD64SHRL: return rewriteValueAMD64_OpAMD64SHRL(v) case OpAMD64SHRLconst: return rewriteValueAMD64_OpAMD64SHRLconst(v) case OpAMD64SHRQ: return rewriteValueAMD64_OpAMD64SHRQ(v) case OpAMD64SHRQconst: return rewriteValueAMD64_OpAMD64SHRQconst(v) case OpAMD64SHRW: return rewriteValueAMD64_OpAMD64SHRW(v) case OpAMD64SHRWconst: return rewriteValueAMD64_OpAMD64SHRWconst(v) case OpAMD64SHRXLload: return rewriteValueAMD64_OpAMD64SHRXLload(v) case OpAMD64SHRXQload: return rewriteValueAMD64_OpAMD64SHRXQload(v) case OpAMD64SUBL: return rewriteValueAMD64_OpAMD64SUBL(v) case OpAMD64SUBLconst: return rewriteValueAMD64_OpAMD64SUBLconst(v) case OpAMD64SUBLload: return rewriteValueAMD64_OpAMD64SUBLload(v) case OpAMD64SUBLmodify: return rewriteValueAMD64_OpAMD64SUBLmodify(v) case OpAMD64SUBQ: return rewriteValueAMD64_OpAMD64SUBQ(v) case OpAMD64SUBQborrow: return rewriteValueAMD64_OpAMD64SUBQborrow(v) case OpAMD64SUBQconst: return rewriteValueAMD64_OpAMD64SUBQconst(v) case OpAMD64SUBQload: return rewriteValueAMD64_OpAMD64SUBQload(v) case OpAMD64SUBQmodify: return rewriteValueAMD64_OpAMD64SUBQmodify(v) case OpAMD64SUBSD: return rewriteValueAMD64_OpAMD64SUBSD(v) case OpAMD64SUBSDload: return rewriteValueAMD64_OpAMD64SUBSDload(v) case OpAMD64SUBSS: return rewriteValueAMD64_OpAMD64SUBSS(v) case OpAMD64SUBSSload: return rewriteValueAMD64_OpAMD64SUBSSload(v) case OpAMD64TESTB: return rewriteValueAMD64_OpAMD64TESTB(v) case OpAMD64TESTBconst: return rewriteValueAMD64_OpAMD64TESTBconst(v) case OpAMD64TESTL: return rewriteValueAMD64_OpAMD64TESTL(v) case OpAMD64TESTLconst: return rewriteValueAMD64_OpAMD64TESTLconst(v) case OpAMD64TESTQ: return rewriteValueAMD64_OpAMD64TESTQ(v) case OpAMD64TESTQconst: return rewriteValueAMD64_OpAMD64TESTQconst(v) case OpAMD64TESTW: return rewriteValueAMD64_OpAMD64TESTW(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock(v) case OpAMD64XADDQlock: return rewriteValueAMD64_OpAMD64XADDQlock(v) case OpAMD64XCHGL: return rewriteValueAMD64_OpAMD64XCHGL(v) case OpAMD64XCHGQ: return rewriteValueAMD64_OpAMD64XCHGQ(v) case OpAMD64XORL: return rewriteValueAMD64_OpAMD64XORL(v) case OpAMD64XORLconst: return rewriteValueAMD64_OpAMD64XORLconst(v) case OpAMD64XORLconstmodify: return rewriteValueAMD64_OpAMD64XORLconstmodify(v) case OpAMD64XORLload: return rewriteValueAMD64_OpAMD64XORLload(v) case OpAMD64XORLmodify: return rewriteValueAMD64_OpAMD64XORLmodify(v) case OpAMD64XORQ: return rewriteValueAMD64_OpAMD64XORQ(v) case OpAMD64XORQconst: return rewriteValueAMD64_OpAMD64XORQconst(v) case OpAMD64XORQconstmodify: return rewriteValueAMD64_OpAMD64XORQconstmodify(v) case OpAMD64XORQload: return rewriteValueAMD64_OpAMD64XORQload(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify(v) case OpAdd16: v.Op = OpAMD64ADDL return true case OpAdd32: v.Op = OpAMD64ADDL return true case OpAdd32F: v.Op = OpAMD64ADDSS return true case OpAdd64: v.Op = OpAMD64ADDQ return true case OpAdd64F: v.Op = OpAMD64ADDSD return true case OpAdd8: v.Op = OpAMD64ADDL return true case OpAddPtr: v.Op = OpAMD64ADDQ return true case OpAddr: return rewriteValueAMD64_OpAddr(v) case OpAnd16: v.Op = OpAMD64ANDL return true case OpAnd32: v.Op = OpAMD64ANDL return true case OpAnd64: v.Op = OpAMD64ANDQ return true case OpAnd8: v.Op = OpAMD64ANDL return true case OpAndB: v.Op = OpAMD64ANDL return true case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32(v) case OpAtomicAdd64: return rewriteValueAMD64_OpAtomicAdd64(v) case OpAtomicAnd32: return rewriteValueAMD64_OpAtomicAnd32(v) case OpAtomicAnd8: return rewriteValueAMD64_OpAtomicAnd8(v) case OpAtomicCompareAndSwap32: return rewriteValueAMD64_OpAtomicCompareAndSwap32(v) case OpAtomicCompareAndSwap64: return rewriteValueAMD64_OpAtomicCompareAndSwap64(v) case OpAtomicExchange32: return rewriteValueAMD64_OpAtomicExchange32(v) case OpAtomicExchange64: return rewriteValueAMD64_OpAtomicExchange64(v) case OpAtomicLoad32: return rewriteValueAMD64_OpAtomicLoad32(v) case OpAtomicLoad64: return rewriteValueAMD64_OpAtomicLoad64(v) case OpAtomicLoad8: return rewriteValueAMD64_OpAtomicLoad8(v) case OpAtomicLoadPtr: return rewriteValueAMD64_OpAtomicLoadPtr(v) case OpAtomicOr32: return rewriteValueAMD64_OpAtomicOr32(v) case OpAtomicOr8: return rewriteValueAMD64_OpAtomicOr8(v) case OpAtomicStore32: return rewriteValueAMD64_OpAtomicStore32(v) case OpAtomicStore64: return rewriteValueAMD64_OpAtomicStore64(v) case OpAtomicStore8: return rewriteValueAMD64_OpAtomicStore8(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB(v) case OpAvg64u: v.Op = OpAMD64AVGQU return true case OpBitLen16: return rewriteValueAMD64_OpBitLen16(v) case OpBitLen32: return rewriteValueAMD64_OpBitLen32(v) case OpBitLen64: return rewriteValueAMD64_OpBitLen64(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8(v) case OpBswap16: return rewriteValueAMD64_OpBswap16(v) case OpBswap32: v.Op = OpAMD64BSWAPL return true case OpBswap64: v.Op = OpAMD64BSWAPQ return true case OpCeil: return rewriteValueAMD64_OpCeil(v) case OpClosureCall: v.Op = OpAMD64CALLclosure return true case OpCom16: v.Op = OpAMD64NOTL return true case OpCom32: v.Op = OpAMD64NOTL return true case OpCom64: v.Op = OpAMD64NOTQ return true case OpCom8: v.Op = OpAMD64NOTL return true case OpCondSelect: return rewriteValueAMD64_OpCondSelect(v) case OpConst16: return rewriteValueAMD64_OpConst16(v) case OpConst32: v.Op = OpAMD64MOVLconst return true case OpConst32F: v.Op = OpAMD64MOVSSconst return true case OpConst64: v.Op = OpAMD64MOVQconst return true case OpConst64F: v.Op = OpAMD64MOVSDconst return true case OpConst8: return rewriteValueAMD64_OpConst8(v) case OpConstBool: return rewriteValueAMD64_OpConstBool(v) case OpConstNil: return rewriteValueAMD64_OpConstNil(v) case OpCtz16: return rewriteValueAMD64_OpCtz16(v) case OpCtz16NonZero: return rewriteValueAMD64_OpCtz16NonZero(v) case OpCtz32: return rewriteValueAMD64_OpCtz32(v) case OpCtz32NonZero: return rewriteValueAMD64_OpCtz32NonZero(v) case OpCtz64: return rewriteValueAMD64_OpCtz64(v) case OpCtz64NonZero: return rewriteValueAMD64_OpCtz64NonZero(v) case OpCtz8: return rewriteValueAMD64_OpCtz8(v) case OpCtz8NonZero: return rewriteValueAMD64_OpCtz8NonZero(v) case OpCvt32Fto32: v.Op = OpAMD64CVTTSS2SL return true case OpCvt32Fto64: v.Op = OpAMD64CVTTSS2SQ return true case OpCvt32Fto64F: v.Op = OpAMD64CVTSS2SD return true case OpCvt32to32F: v.Op = OpAMD64CVTSL2SS return true case OpCvt32to64F: v.Op = OpAMD64CVTSL2SD return true case OpCvt64Fto32: v.Op = OpAMD64CVTTSD2SL return true case OpCvt64Fto32F: v.Op = OpAMD64CVTSD2SS return true case OpCvt64Fto64: v.Op = OpAMD64CVTTSD2SQ return true case OpCvt64to32F: v.Op = OpAMD64CVTSQ2SS return true case OpCvt64to64F: v.Op = OpAMD64CVTSQ2SD return true case OpCvtBoolToUint8: v.Op = OpCopy return true case OpDiv128u: v.Op = OpAMD64DIVQU2 return true case OpDiv16: return rewriteValueAMD64_OpDiv16(v) case OpDiv16u: return rewriteValueAMD64_OpDiv16u(v) case OpDiv32: return rewriteValueAMD64_OpDiv32(v) case OpDiv32F: v.Op = OpAMD64DIVSS return true case OpDiv32u: return rewriteValueAMD64_OpDiv32u(v) case OpDiv64: return rewriteValueAMD64_OpDiv64(v) case OpDiv64F: v.Op = OpAMD64DIVSD return true case OpDiv64u: return rewriteValueAMD64_OpDiv64u(v) case OpDiv8: return rewriteValueAMD64_OpDiv8(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u(v) case OpEq16: return rewriteValueAMD64_OpEq16(v) case OpEq32: return rewriteValueAMD64_OpEq32(v) case OpEq32F: return rewriteValueAMD64_OpEq32F(v) case OpEq64: return rewriteValueAMD64_OpEq64(v) case OpEq64F: return rewriteValueAMD64_OpEq64F(v) case OpEq8: return rewriteValueAMD64_OpEq8(v) case OpEqB: return rewriteValueAMD64_OpEqB(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr(v) case OpFMA: return rewriteValueAMD64_OpFMA(v) case OpFloor: return rewriteValueAMD64_OpFloor(v) case OpGetCallerPC: v.Op = OpAMD64LoweredGetCallerPC return true case OpGetCallerSP: v.Op = OpAMD64LoweredGetCallerSP return true case OpGetClosurePtr: v.Op = OpAMD64LoweredGetClosurePtr return true case OpGetG: return rewriteValueAMD64_OpGetG(v) case OpHasCPUFeature: return rewriteValueAMD64_OpHasCPUFeature(v) case OpHmul32: v.Op = OpAMD64HMULL return true case OpHmul32u: v.Op = OpAMD64HMULLU return true case OpHmul64: v.Op = OpAMD64HMULQ return true case OpHmul64u: v.Op = OpAMD64HMULQU return true case OpInterCall: v.Op = OpAMD64CALLinter return true case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueAMD64_OpIsSliceInBounds(v) case OpLeq16: return rewriteValueAMD64_OpLeq16(v) case OpLeq16U: return rewriteValueAMD64_OpLeq16U(v) case OpLeq32: return rewriteValueAMD64_OpLeq32(v) case OpLeq32F: return rewriteValueAMD64_OpLeq32F(v) case OpLeq32U: return rewriteValueAMD64_OpLeq32U(v) case OpLeq64: return rewriteValueAMD64_OpLeq64(v) case OpLeq64F: return rewriteValueAMD64_OpLeq64F(v) case OpLeq64U: return rewriteValueAMD64_OpLeq64U(v) case OpLeq8: return rewriteValueAMD64_OpLeq8(v) case OpLeq8U: return rewriteValueAMD64_OpLeq8U(v) case OpLess16: return rewriteValueAMD64_OpLess16(v) case OpLess16U: return rewriteValueAMD64_OpLess16U(v) case OpLess32: return rewriteValueAMD64_OpLess32(v) case OpLess32F: return rewriteValueAMD64_OpLess32F(v) case OpLess32U: return rewriteValueAMD64_OpLess32U(v) case OpLess64: return rewriteValueAMD64_OpLess64(v) case OpLess64F: return rewriteValueAMD64_OpLess64F(v) case OpLess64U: return rewriteValueAMD64_OpLess64U(v) case OpLess8: return rewriteValueAMD64_OpLess8(v) case OpLess8U: return rewriteValueAMD64_OpLess8U(v) case OpLoad: return rewriteValueAMD64_OpLoad(v) case OpLocalAddr: return rewriteValueAMD64_OpLocalAddr(v) case OpLsh16x16: return rewriteValueAMD64_OpLsh16x16(v) case OpLsh16x32: return rewriteValueAMD64_OpLsh16x32(v) case OpLsh16x64: return rewriteValueAMD64_OpLsh16x64(v) case OpLsh16x8: return rewriteValueAMD64_OpLsh16x8(v) case OpLsh32x16: return rewriteValueAMD64_OpLsh32x16(v) case OpLsh32x32: return rewriteValueAMD64_OpLsh32x32(v) case OpLsh32x64: return rewriteValueAMD64_OpLsh32x64(v) case OpLsh32x8: return rewriteValueAMD64_OpLsh32x8(v) case OpLsh64x16: return rewriteValueAMD64_OpLsh64x16(v) case OpLsh64x32: return rewriteValueAMD64_OpLsh64x32(v) case OpLsh64x64: return rewriteValueAMD64_OpLsh64x64(v) case OpLsh64x8: return rewriteValueAMD64_OpLsh64x8(v) case OpLsh8x16: return rewriteValueAMD64_OpLsh8x16(v) case OpLsh8x32: return rewriteValueAMD64_OpLsh8x32(v) case OpLsh8x64: return rewriteValueAMD64_OpLsh8x64(v) case OpLsh8x8: return rewriteValueAMD64_OpLsh8x8(v) case OpMod16: return rewriteValueAMD64_OpMod16(v) case OpMod16u: return rewriteValueAMD64_OpMod16u(v) case OpMod32: return rewriteValueAMD64_OpMod32(v) case OpMod32u: return rewriteValueAMD64_OpMod32u(v) case OpMod64: return rewriteValueAMD64_OpMod64(v) case OpMod64u: return rewriteValueAMD64_OpMod64u(v) case OpMod8: return rewriteValueAMD64_OpMod8(v) case OpMod8u: return rewriteValueAMD64_OpMod8u(v) case OpMove: return rewriteValueAMD64_OpMove(v) case OpMul16: v.Op = OpAMD64MULL return true case OpMul32: v.Op = OpAMD64MULL return true case OpMul32F: v.Op = OpAMD64MULSS return true case OpMul64: v.Op = OpAMD64MULQ return true case OpMul64F: v.Op = OpAMD64MULSD return true case OpMul64uhilo: v.Op = OpAMD64MULQU2 return true case OpMul8: v.Op = OpAMD64MULL return true case OpNeg16: v.Op = OpAMD64NEGL return true case OpNeg32: v.Op = OpAMD64NEGL return true case OpNeg32F: return rewriteValueAMD64_OpNeg32F(v) case OpNeg64: v.Op = OpAMD64NEGQ return true case OpNeg64F: return rewriteValueAMD64_OpNeg64F(v) case OpNeg8: v.Op = OpAMD64NEGL return true case OpNeq16: return rewriteValueAMD64_OpNeq16(v) case OpNeq32: return rewriteValueAMD64_OpNeq32(v) case OpNeq32F: return rewriteValueAMD64_OpNeq32F(v) case OpNeq64: return rewriteValueAMD64_OpNeq64(v) case OpNeq64F: return rewriteValueAMD64_OpNeq64F(v) case OpNeq8: return rewriteValueAMD64_OpNeq8(v) case OpNeqB: return rewriteValueAMD64_OpNeqB(v) case OpNeqPtr: return rewriteValueAMD64_OpNeqPtr(v) case OpNilCheck: v.Op = OpAMD64LoweredNilCheck return true case OpNot: return rewriteValueAMD64_OpNot(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr(v) case OpOr16: v.Op = OpAMD64ORL return true case OpOr32: v.Op = OpAMD64ORL return true case OpOr64: v.Op = OpAMD64ORQ return true case OpOr8: v.Op = OpAMD64ORL return true case OpOrB: v.Op = OpAMD64ORL return true case OpPanicBounds: return rewriteValueAMD64_OpPanicBounds(v) case OpPopCount16: return rewriteValueAMD64_OpPopCount16(v) case OpPopCount32: v.Op = OpAMD64POPCNTL return true case OpPopCount64: v.Op = OpAMD64POPCNTQ return true case OpPopCount8: return rewriteValueAMD64_OpPopCount8(v) case OpPrefetchCache: v.Op = OpAMD64PrefetchT0 return true case OpPrefetchCacheStreamed: v.Op = OpAMD64PrefetchNTA return true case OpRotateLeft16: v.Op = OpAMD64ROLW return true case OpRotateLeft32: v.Op = OpAMD64ROLL return true case OpRotateLeft64: v.Op = OpAMD64ROLQ return true case OpRotateLeft8: v.Op = OpAMD64ROLB return true case OpRound32F: v.Op = OpCopy return true case OpRound64F: v.Op = OpCopy return true case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven(v) case OpRsh16Ux16: return rewriteValueAMD64_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValueAMD64_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValueAMD64_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValueAMD64_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValueAMD64_OpRsh16x16(v) case OpRsh16x32: return rewriteValueAMD64_OpRsh16x32(v) case OpRsh16x64: return rewriteValueAMD64_OpRsh16x64(v) case OpRsh16x8: return rewriteValueAMD64_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValueAMD64_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValueAMD64_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValueAMD64_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValueAMD64_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValueAMD64_OpRsh32x16(v) case OpRsh32x32: return rewriteValueAMD64_OpRsh32x32(v) case OpRsh32x64: return rewriteValueAMD64_OpRsh32x64(v) case OpRsh32x8: return rewriteValueAMD64_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValueAMD64_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValueAMD64_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValueAMD64_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValueAMD64_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValueAMD64_OpRsh64x16(v) case OpRsh64x32: return rewriteValueAMD64_OpRsh64x32(v) case OpRsh64x64: return rewriteValueAMD64_OpRsh64x64(v) case OpRsh64x8: return rewriteValueAMD64_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValueAMD64_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValueAMD64_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValueAMD64_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValueAMD64_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValueAMD64_OpRsh8x16(v) case OpRsh8x32: return rewriteValueAMD64_OpRsh8x32(v) case OpRsh8x64: return rewriteValueAMD64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8(v) case OpSelect0: return rewriteValueAMD64_OpSelect0(v) case OpSelect1: return rewriteValueAMD64_OpSelect1(v) case OpSelectN: return rewriteValueAMD64_OpSelectN(v) case OpSignExt16to32: v.Op = OpAMD64MOVWQSX return true case OpSignExt16to64: v.Op = OpAMD64MOVWQSX return true case OpSignExt32to64: v.Op = OpAMD64MOVLQSX return true case OpSignExt8to16: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to32: v.Op = OpAMD64MOVBQSX return true case OpSignExt8to64: v.Op = OpAMD64MOVBQSX return true case OpSlicemask: return rewriteValueAMD64_OpSlicemask(v) case OpSpectreIndex: return rewriteValueAMD64_OpSpectreIndex(v) case OpSpectreSliceIndex: return rewriteValueAMD64_OpSpectreSliceIndex(v) case OpSqrt: v.Op = OpAMD64SQRTSD return true case OpSqrt32: v.Op = OpAMD64SQRTSS return true case OpStaticCall: v.Op = OpAMD64CALLstatic return true case OpStore: return rewriteValueAMD64_OpStore(v) case OpSub16: v.Op = OpAMD64SUBL return true case OpSub32: v.Op = OpAMD64SUBL return true case OpSub32F: v.Op = OpAMD64SUBSS return true case OpSub64: v.Op = OpAMD64SUBQ return true case OpSub64F: v.Op = OpAMD64SUBSD return true case OpSub8: v.Op = OpAMD64SUBL return true case OpSubPtr: v.Op = OpAMD64SUBQ return true case OpTailCall: v.Op = OpAMD64CALLtail return true case OpTrunc: return rewriteValueAMD64_OpTrunc(v) case OpTrunc16to8: v.Op = OpCopy return true case OpTrunc32to16: v.Op = OpCopy return true case OpTrunc32to8: v.Op = OpCopy return true case OpTrunc64to16: v.Op = OpCopy return true case OpTrunc64to32: v.Op = OpCopy return true case OpTrunc64to8: v.Op = OpCopy return true case OpWB: v.Op = OpAMD64LoweredWB return true case OpXor16: v.Op = OpAMD64XORL return true case OpXor32: v.Op = OpAMD64XORL return true case OpXor64: v.Op = OpAMD64XORQ return true case OpXor8: v.Op = OpAMD64XORL return true case OpZero: return rewriteValueAMD64_OpZero(v) case OpZeroExt16to32: v.Op = OpAMD64MOVWQZX return true case OpZeroExt16to64: v.Op = OpAMD64MOVWQZX return true case OpZeroExt32to64: v.Op = OpAMD64MOVLQZX return true case OpZeroExt8to16: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to32: v.Op = OpAMD64MOVBQZX return true case OpZeroExt8to64: v.Op = OpAMD64MOVBQZX return true } return false } func rewriteValueAMD64_OpAMD64ADCQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) // result: (ADCQconst x [int32(c)] carry) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) carry := v_2 if !(is32Bit(c)) { continue } v.reset(OpAMD64ADCQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, carry) return true } break } // match: (ADCQ x y (FlagEQ)) // result: (ADDQcarry x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQcarry) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64ADCQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQconst x [c] (FlagEQ)) // result: (ADDQconstcarry x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDL x (MOVLconst [c])) // result: (ADDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDL x (SHLLconst [3] y)) // result: (LEAL8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [2] y)) // result: (LEAL4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AddArg2(x, y) return true } break } // match: (ADDL x (SHLLconst [1] y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL x y)) // result: (LEAL2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDL { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAL2) v.AddArg2(y, x) return true } } break } // match: (ADDL (ADDLconst [c] x) y) // result: (LEAL1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDL x (LEAL [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAL { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDL x (NEGL y)) // result: (SUBL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL { continue } y := v_1.Args[0] v.reset(OpAMD64SUBL) v.AddArg2(x, y) return true } break } // match: (ADDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDLconst [c] (ADDL x y)) // result: (LEAL1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (SHLLconst [1] x)) // result: (LEAL1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDLconst [c] (LEAL [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDLconst [c] (LEAL1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] (LEAL8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAL8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (ADDLconst [c] (MOVLconst [d])) // result: (MOVLconst [c+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c + d) return true } // match: (ADDLconst [c] (ADDLconst [d] x)) // result: (ADDLconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDLconst [off] x:(SP)) // result: (LEAL [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDLconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDLconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (ADDL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQ x (MOVQconst [c])) // cond: is32Bit(c) && !t.IsPtr() // result: (ADDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c) && !t.IsPtr()) { continue } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ADDQ x (MOVLconst [c])) // result: (ADDQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADDQ x (SHLQconst [3] y)) // result: (LEAQ8 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [2] y)) // result: (LEAQ4 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AddArg2(x, y) return true } break } // match: (ADDQ x (SHLQconst [1] y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ y y)) // result: (LEAQ2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } y := v_1.Args[1] if y != v_1.Args[0] { continue } v.reset(OpAMD64LEAQ2) v.AddArg2(x, y) return true } break } // match: (ADDQ x (ADDQ x y)) // result: (LEAQ2 y x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQ { continue } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 v.reset(OpAMD64LEAQ2) v.AddArg2(y, x) return true } } break } // match: (ADDQ (ADDQconst [c] x) y) // result: (LEAQ1 [c] x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } break } // match: (ADDQ x (LEAQ [c] {s} y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ { continue } c := auxIntToInt32(v_1.AuxInt) s := auxToSym(v_1.Aux) y := v_1.Args[0] if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (ADDQ x (NEGQ y)) // result: (SUBQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ { continue } y := v_1.Args[0] v.reset(OpAMD64SUBQ) v.AddArg2(x, y) return true } break } // match: (ADDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQcarry(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQcarry x (MOVQconst [c])) // cond: is32Bit(c) // result: (ADDQconstcarry x [int32(c)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ADDQconstcarry) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDQconst [c] (ADDQ x y)) // result: (LEAQ1 [c] x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQ { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (SHLQconst [1] x)) // result: (LEAQ1 [c] x x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.AddArg2(x, x) return true } // match: (ADDQconst [c] (LEAQ [d] {s} x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (ADDQconst [c] (LEAQ1 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ1 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ2 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ2 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ4 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ4 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [c] (LEAQ8 [d] {s} x y)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64LEAQ8 { break } d := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (ADDQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ADDQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)+d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) + d) return true } // match: (ADDQconst [c] (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (ADDQconst [c+d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDQconst [off] x:(SP)) // result: (LEAQ [off] x) for { off := auxIntToInt32(v.AuxInt) x := v_0 if x.Op != OpSP { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64ADDQconstmodify(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (ADDQconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (ADDQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64ADDSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (ADDSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ADDSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ADDSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ADDSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (ADDSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64ADDSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (ADDSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64ADDSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64ANDL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x) // result: (BTRL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64NOTL { continue } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SHLL { continue } y := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTRL) v.AddArg2(x, y) return true } break } // match: (ANDL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } break } // match: (ANDL x (MOVLconst [c])) // result: (ANDLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ANDL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDL x (NOTL y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTL { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNL) v.AddArg2(x, y) return true } break } // match: (ANDL x (NEGL x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGL || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIL) v.AddArg(x) return true } break } // match: (ANDL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (Select0 (BLSRL x)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpSelect0) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64BLSRL, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDLconst [c] x) // cond: isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRLconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDLconst [c] (BTRLconst [d] x)) // result: (ANDLconst [c &^ (1<= 128 // result: (BTRQconst [int8(log64(^c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(^c) && uint64(^c) >= 128) { continue } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log64(^c))) v.AddArg(x) return true } break } // match: (ANDQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ANDQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ANDQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ANDQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ANDQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ANDQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (ANDQ x (NOTQ y)) // cond: buildcfg.GOAMD64 >= 3 // result: (ANDNQ x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NOTQ { continue } y := v_1.Args[0] if !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64ANDNQ) v.AddArg2(x, y) return true } break } // match: (ANDQ x (NEGQ x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSIQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64NEGQ || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSIQ) v.AddArg(x) return true } break } // match: (ANDQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (Select0 (BLSRQ x)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpSelect0) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64BLSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDQconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDQconst [c] x) // cond: isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128 // result: (BTRQconst [int8(log32(^c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(^c)) && uint64(^c) >= 128) { break } v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(int8(log32(^c))) v.AddArg(x) return true } // match: (ANDQconst [c] (ANDQconst [d] x)) // result: (ANDQconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDQconst [c] (BTRQconst [d] x)) // cond: is32Bit(int64(c) &^ (1< [1<<8] (MOVBQZX x))) // result: (BSFQ (ORQconst [1<<8] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVBQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 8) v0.AddArg(x) v.AddArg(v0) return true } // match: (BSFQ (ORQconst [1<<16] (MOVWQZX x))) // result: (BSFQ (ORQconst [1<<16] x)) for { if v_0.Op != OpAMD64ORQconst { break } t := v_0.Type if auxIntToInt32(v_0.AuxInt) != 1<<16 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVWQZX { break } x := v_0_0.Args[0] v.reset(OpAMD64BSFQ) v0 := b.NewValue0(v.Pos, OpAMD64ORQconst, t) v0.AuxInt = int32ToAuxInt(1 << 16) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPL(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPL (BSWAPL p)) // result: p for { if v_0.Op != OpAMD64BSWAPL { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPL x:(MOVLload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPL (MOVBELload [i] {s} p m)) // result: (MOVLload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBELload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BSWAPQ(v *Value) bool { v_0 := v.Args[0] // match: (BSWAPQ (BSWAPQ p)) // result: p for { if v_0.Op != OpAMD64BSWAPQ { break } p := v_0.Args[0] v.copyOf(p) return true } // match: (BSWAPQ x:(MOVQload [i] {s} p mem)) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQload [i] {s} p mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } i := auxIntToInt32(x.AuxInt) s := auxToSym(x.Aux) mem := x.Args[1] p := x.Args[0] if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, mem) return true } // match: (BSWAPQ (MOVBEQload [i] {s} p m)) // result: (MOVQload [i] {s} p m) for { if v_0.Op != OpAMD64MOVBEQload { break } i := auxIntToInt32(v_0.AuxInt) s := auxToSym(v_0.Aux) m := v_0.Args[1] p := v_0.Args[0] v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(p, m) return true } return false } func rewriteValueAMD64_OpAMD64BTCLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTCLconst [c] (XORLconst [d] x)) // result: (XORLconst [d ^ 1<d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } // match: (BTLconst [c] (SHRLconst [d] x)) // cond: (c+d)<32 // result: (BTLconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 32) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTLconst [c] (SHLLconst [d] x)) // cond: c>d // result: (BTLconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLLconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTLconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTLconst [0] s:(SHRL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } // match: (BTLconst [0] s:(SHRXL x y)) // result: (BTL y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRXL { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTQconst(v *Value) bool { v_0 := v.Args[0] // match: (BTQconst [c] (SHRQconst [d] x)) // cond: (c+d)<64 // result: (BTQconst [c+d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHRQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !((c + d) < 64) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c + d) v.AddArg(x) return true } // match: (BTQconst [c] (SHLQconst [d] x)) // cond: c>d // result: (BTQconst [c-d] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64SHLQconst { break } d := auxIntToInt8(v_0.AuxInt) x := v_0.Args[0] if !(c > d) { break } v.reset(OpAMD64BTQconst) v.AuxInt = int8ToAuxInt(c - d) v.AddArg(x) return true } // match: (BTQconst [0] s:(SHRQ x y)) // result: (BTQ y x) for { if auxIntToInt8(v.AuxInt) != 0 { break } s := v_0 if s.Op != OpAMD64SHRQ { break } y := s.Args[1] x := s.Args[0] v.reset(OpAMD64BTQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64BTRLconst(v *Value) bool { v_0 := v.Args[0] // match: (BTRLconst [c] (BTSLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTSLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (BTCLconst [c] x)) // result: (BTRLconst [c] x) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64BTCLconst || auxIntToInt8(v_0.AuxInt) != c { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(c) v.AddArg(x) return true } // match: (BTRLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [d &^ (1< blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTQ { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { continue } v.reset(OpAMD64CMOVLEQ) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } // match: (CMOVLEQ x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) // result: (CMOVLEQ x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTL { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_2_1 { continue } v.reset(OpAMD64CMOVLEQ) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } return false } func rewriteValueAMD64_OpAMD64CMOVLGE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVLGE x y (InvertFlags cond)) // result: (CMOVLLE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLLE) v.AddArg3(x, y, cond) return true } // match: (CMOVLGE _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVLGE _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVLGE _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVLGE y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVLGE y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVLGT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVLGT x y (InvertFlags cond)) // result: (CMOVLLT x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLLT) v.AddArg3(x, y, cond) return true } // match: (CMOVLGT y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVLGT _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVLGT _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVLGT y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVLGT y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVLHI(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVLHI x y (InvertFlags cond)) // result: (CMOVLCS x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLCS) v.AddArg3(x, y, cond) return true } // match: (CMOVLHI y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVLHI _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVLHI y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVLHI y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVLHI _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVLLE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVLLE x y (InvertFlags cond)) // result: (CMOVLGE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLGE) v.AddArg3(x, y, cond) return true } // match: (CMOVLLE _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVLLE y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVLLE y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVLLE _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVLLE _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVLLS(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVLLS x y (InvertFlags cond)) // result: (CMOVLCC x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLCC) v.AddArg3(x, y, cond) return true } // match: (CMOVLLS _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVLLS y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVLLS _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVLLS _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVLLS y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVLLT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVLLT x y (InvertFlags cond)) // result: (CMOVLGT x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLGT) v.AddArg3(x, y, cond) return true } // match: (CMOVLLT y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVLLT y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVLLT y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVLLT _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVLLT _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVLNE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMOVLNE x y (InvertFlags cond)) // result: (CMOVLNE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLNE) v.AddArg3(x, y, cond) return true } // match: (CMOVLNE y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVLNE _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVLNE _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVLNE _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVLNE _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } // match: (CMOVLNE x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) // result: (CMOVLNE x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTQ { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { continue } v.reset(OpAMD64CMOVLNE) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } // match: (CMOVLNE x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) // result: (CMOVLNE x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTL { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_2_1 { continue } v.reset(OpAMD64CMOVLNE) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } return false } func rewriteValueAMD64_OpAMD64CMOVQCC(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQCC x y (InvertFlags cond)) // result: (CMOVQLS x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQLS) v.AddArg3(x, y, cond) return true } // match: (CMOVQCC _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVQCC _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVQCC y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVQCC y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVQCC _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQCS(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQCS x y (InvertFlags cond)) // result: (CMOVQHI x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQHI) v.AddArg3(x, y, cond) return true } // match: (CMOVQCS y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVQCS y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVQCS _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVQCS _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVQCS y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQEQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMOVQEQ x y (InvertFlags cond)) // result: (CMOVQEQ x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQEQ) v.AddArg3(x, y, cond) return true } // match: (CMOVQEQ _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVQEQ y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVQEQ y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVQEQ y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVQEQ y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } // match: (CMOVQEQ x _ (Select1 (BSFQ (ORQconst [c] _)))) // cond: c != 0 // result: x for { x := v_0 if v_2.Op != OpSelect1 { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpAMD64BSFQ { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpAMD64ORQconst { break } c := auxIntToInt32(v_2_0_0.AuxInt) if !(c != 0) { break } v.copyOf(x) return true } // match: (CMOVQEQ x _ (Select1 (BSRQ (ORQconst [c] _)))) // cond: c != 0 // result: x for { x := v_0 if v_2.Op != OpSelect1 { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpAMD64BSRQ { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpAMD64ORQconst { break } c := auxIntToInt32(v_2_0_0.AuxInt) if !(c != 0) { break } v.copyOf(x) return true } // match: (CMOVQEQ x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) // result: (CMOVQEQ x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTQ { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { continue } v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } // match: (CMOVQEQ x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) // result: (CMOVQEQ x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTL { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_2_1 { continue } v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } return false } func rewriteValueAMD64_OpAMD64CMOVQGE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQGE x y (InvertFlags cond)) // result: (CMOVQLE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQLE) v.AddArg3(x, y, cond) return true } // match: (CMOVQGE _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVQGE _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVQGE _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVQGE y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVQGE y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQGT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQGT x y (InvertFlags cond)) // result: (CMOVQLT x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQLT) v.AddArg3(x, y, cond) return true } // match: (CMOVQGT y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVQGT _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVQGT _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVQGT y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVQGT y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQHI(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQHI x y (InvertFlags cond)) // result: (CMOVQCS x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQCS) v.AddArg3(x, y, cond) return true } // match: (CMOVQHI y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVQHI _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVQHI y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVQHI y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVQHI _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQLE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQLE x y (InvertFlags cond)) // result: (CMOVQGE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQGE) v.AddArg3(x, y, cond) return true } // match: (CMOVQLE _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVQLE y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVQLE y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVQLE _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVQLE _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQLS(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQLS x y (InvertFlags cond)) // result: (CMOVQCC x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQCC) v.AddArg3(x, y, cond) return true } // match: (CMOVQLS _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVQLS y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVQLS _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVQLS _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVQLS y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQLT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVQLT x y (InvertFlags cond)) // result: (CMOVQGT x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQGT) v.AddArg3(x, y, cond) return true } // match: (CMOVQLT y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVQLT y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVQLT y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVQLT _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVQLT _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVQNE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMOVQNE x y (InvertFlags cond)) // result: (CMOVQNE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVQNE) v.AddArg3(x, y, cond) return true } // match: (CMOVQNE y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVQNE _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVQNE _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVQNE _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVQNE _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } // match: (CMOVQNE x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) // result: (CMOVQNE x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTQ { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_2_1 { continue } v.reset(OpAMD64CMOVQNE) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } // match: (CMOVQNE x y (TESTL s:(Select0 blsr:(BLSRL _)) s)) // result: (CMOVQNE x y (Select1 blsr)) for { x := v_0 y := v_1 if v_2.Op != OpAMD64TESTL { break } _ = v_2.Args[1] v_2_0 := v_2.Args[0] v_2_1 := v_2.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 { s := v_2_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_2_1 { continue } v.reset(OpAMD64CMOVQNE) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg3(x, y, v0) return true } break } return false } func rewriteValueAMD64_OpAMD64CMOVWCC(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWCC x y (InvertFlags cond)) // result: (CMOVWLS x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWLS) v.AddArg3(x, y, cond) return true } // match: (CMOVWCC _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVWCC _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVWCC y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVWCC y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVWCC _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWCS(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWCS x y (InvertFlags cond)) // result: (CMOVWHI x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWHI) v.AddArg3(x, y, cond) return true } // match: (CMOVWCS y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVWCS y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVWCS _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVWCS _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVWCS y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWEQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWEQ x y (InvertFlags cond)) // result: (CMOVWEQ x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWEQ) v.AddArg3(x, y, cond) return true } // match: (CMOVWEQ _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVWEQ y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVWEQ y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVWEQ y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVWEQ y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWGE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWGE x y (InvertFlags cond)) // result: (CMOVWLE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWLE) v.AddArg3(x, y, cond) return true } // match: (CMOVWGE _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVWGE _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVWGE _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVWGE y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVWGE y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWGT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWGT x y (InvertFlags cond)) // result: (CMOVWLT x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWLT) v.AddArg3(x, y, cond) return true } // match: (CMOVWGT y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVWGT _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVWGT _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVWGT y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVWGT y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWHI(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWHI x y (InvertFlags cond)) // result: (CMOVWCS x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWCS) v.AddArg3(x, y, cond) return true } // match: (CMOVWHI y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVWHI _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVWHI y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVWHI y _ (FlagLT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(y) return true } // match: (CMOVWHI _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWLE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWLE x y (InvertFlags cond)) // result: (CMOVWGE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWGE) v.AddArg3(x, y, cond) return true } // match: (CMOVWLE _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVWLE y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVWLE y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVWLE _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVWLE _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWLS(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWLS x y (InvertFlags cond)) // result: (CMOVWCC x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWCC) v.AddArg3(x, y, cond) return true } // match: (CMOVWLS _ x (FlagEQ)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(x) return true } // match: (CMOVWLS y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVWLS _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVWLS _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVWLS y _ (FlagLT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(y) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWLT(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWLT x y (InvertFlags cond)) // result: (CMOVWGT x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWGT) v.AddArg3(x, y, cond) return true } // match: (CMOVWLT y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVWLT y _ (FlagGT_UGT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(y) return true } // match: (CMOVWLT y _ (FlagGT_ULT)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(y) return true } // match: (CMOVWLT _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVWLT _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMOVWNE(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWNE x y (InvertFlags cond)) // result: (CMOVWNE x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWNE) v.AddArg3(x, y, cond) return true } // match: (CMOVWNE y _ (FlagEQ)) // result: y for { y := v_0 if v_2.Op != OpAMD64FlagEQ { break } v.copyOf(y) return true } // match: (CMOVWNE _ x (FlagGT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_UGT { break } v.copyOf(x) return true } // match: (CMOVWNE _ x (FlagGT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagGT_ULT { break } v.copyOf(x) return true } // match: (CMOVWNE _ x (FlagLT_ULT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_ULT { break } v.copyOf(x) return true } // match: (CMOVWNE _ x (FlagLT_UGT)) // result: x for { x := v_1 if v_2.Op != OpAMD64FlagLT_UGT { break } v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64CMPB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPB x (MOVLconst [c])) // result: (CMPBconst x [int8(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64CMPBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } // match: (CMPB (MOVLconst [c]) x) // result: (InvertFlags (CMPBconst x [int8(c)])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPB x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPB y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMPB l:(MOVBload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPBload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVBload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPB x l:(MOVBload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPBload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVBload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPBload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)==y // result: (FlagEQ) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) == y) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)uint8(y) // result: (FlagLT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) < y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x) y && uint8(x) < uint8(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPBconst (MOVLconst [x]) [y]) // cond: int8(x)>y && uint8(x)>uint8(y) // result: (FlagGT_UGT) for { y := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int8(x) > y && uint8(x) > uint8(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPBconst (ANDLconst _ [m]) [n]) // cond: 0 <= int8(m) && int8(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int8(m) && int8(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPBconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTB x y) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, y) return true } // match: (CMPBconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTBconst [int8(c)] x) for { if auxIntToInt8(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } // match: (CMPBconst x [0]) // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } // match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt8(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVBload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPBconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPBload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPBload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPBload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPBconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPL x (MOVLconst [c])) // result: (CMPLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64CMPLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (CMPL (MOVLconst [c]) x) // result: (InvertFlags (CMPLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPL x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPL y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMPL l:(MOVLload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPLload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPL x l:(MOVLload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPLload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPLload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x==y // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x == y) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: xuint32(y) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x < y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x) y && uint32(x) < uint32(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPLconst (MOVLconst [x]) [y]) // cond: x>y && uint32(x)>uint32(y) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(x > y && uint32(x) > uint32(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPLconst (SHRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 32 && (1<uint64(y) // result: (FlagLT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x < y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x) y && uint64(x) < uint64(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQ (MOVQconst [x]) (MOVQconst [y])) // cond: x>y && uint64(x)>uint64(y) // result: (FlagGT_UGT) for { if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { break } y := auxIntToInt64(v_1.AuxInt) if !(x > y && uint64(x) > uint64(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQ l:(MOVQload {sym} [off] ptr mem) x) // cond: canMergeLoad(v, l) && clobber(l) // result: (CMPQload {sym} [off] ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64CMPQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (CMPQ x l:(MOVQload {sym} [off] ptr mem)) // cond: canMergeLoad(v, l) && clobber(l) // result: (InvertFlags (CMPQload {sym} [off] ptr x mem)) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64InvertFlags) v0 := b.NewValue0(l.Pos, OpAMD64CMPQload, types.TypeFlags) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg3(ptr, x, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64CMPQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x==int64(y) // result: (FlagEQ) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x == int64(y)) { break } v.reset(OpAMD64FlagEQ) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: xuint64(int64(y)) // result: (FlagLT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x < int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x) int64(y) && uint64(x) < uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPQconst (MOVQconst [x]) [y]) // cond: x>int64(y) && uint64(x)>uint64(int64(y)) // result: (FlagGT_UGT) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } x := auxIntToInt64(v_0.AuxInt) if !(x > int64(y) && uint64(x) > uint64(int64(y))) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPQconst (MOVBQZX _) [c]) // cond: 0xFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVBQZX || !(0xFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (MOVWQZX _) [c]) // cond: 0xFFFF < c // result: (FlagLT_ULT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVWQZX || !(0xFFFF < c) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPQconst (SHRQconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 64 && (1<uint16(y) // result: (FlagLT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) < y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x) y && uint16(x) < uint16(y)) { break } v.reset(OpAMD64FlagGT_ULT) return true } // match: (CMPWconst (MOVLconst [x]) [y]) // cond: int16(x)>y && uint16(x)>uint16(y) // result: (FlagGT_UGT) for { y := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } x := auxIntToInt32(v_0.AuxInt) if !(int16(x) > y && uint16(x) > uint16(y)) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (CMPWconst (ANDLconst _ [m]) [n]) // cond: 0 <= int16(m) && int16(m) < n // result: (FlagLT_ULT) for { n := auxIntToInt16(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } m := auxIntToInt32(v_0.AuxInt) if !(0 <= int16(m) && int16(m) < n) { break } v.reset(OpAMD64FlagLT_ULT) return true } // match: (CMPWconst a:(ANDL x y) [0]) // cond: a.Uses == 1 // result: (TESTW x y) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDL { break } y := a.Args[1] x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, y) return true } // match: (CMPWconst a:(ANDLconst [c] x) [0]) // cond: a.Uses == 1 // result: (TESTWconst [int16(c)] x) for { if auxIntToInt16(v.AuxInt) != 0 { break } a := v_0 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) x := a.Args[0] if !(a.Uses == 1) { break } v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } // match: (CMPWconst x [0]) // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != 0 { break } x := v_0 v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } // match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c]) // cond: l.Uses == 1 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(int32(c),off)] ptr mem) for { c := auxIntToInt16(v.AuxInt) l := v_0 if l.Op != OpAMD64MOVWload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(sym) v.AddArg2(base, mem) return true } // match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) // result: (CMPWconstload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) for { valoff1 := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(ValAndOff(valoff1).addOffset32(off2)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPWload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPWload [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (CMPWload [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64CMPWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) // result: (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64CMPWconstload) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGLlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64CMPXCHGQlock(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] old := v_1 new_ := v_2 mem := v_3 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64CMPXCHGQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg4(ptr, old, new_, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (DIVSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64DIVSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (DIVSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (DIVSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64DIVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } return false } func rewriteValueAMD64_OpAMD64HMULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULL x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULL y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULL) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULLU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULLU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULLU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULLU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQ x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQ y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQ) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64HMULQU(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (HMULQU x y) // cond: !x.rematerializeable() && y.rematerializeable() // result: (HMULQU y x) for { x := v_0 y := v_1 if !(!x.rematerializeable() && y.rematerializeable()) { break } v.reset(OpAMD64HMULQU) v.AddArg2(y, x) return true } return false } func rewriteValueAMD64_OpAMD64LEAL(v *Value) bool { v_0 := v.Args[0] // match: (LEAL [c] {s} (ADDLconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAL [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAL) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAL [c] {s} (ADDL x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAL1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL1 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDLconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAL1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [1] y)) // result: (LEAL2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [2] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAL1 [c] {s} x (SHLLconst [3] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } return false } func rewriteValueAMD64_OpAMD64LEAL2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL2 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAL2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [1] y)) // result: (LEAL4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL2 [c] {s} x (SHLLconst [2] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL4 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAL4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL4 [c] {s} x (SHLLconst [1] y)) // result: (LEAL8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAL8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAL8 [c] {s} (ADDLconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAL8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAL8 [c] {s} x (ADDLconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAL8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDLconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAL8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ(v *Value) bool { v_0 := v.Args[0] // match: (LEAQ [c] {s} (ADDQconst [d] x)) // cond: is32Bit(int64(c)+int64(d)) // result: (LEAQ [c+d] {s} x) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) + int64(d))) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg(x) return true } // match: (LEAQ [c] {s} (ADDQ x y)) // cond: x.Op != OpSB && y.Op != OpSB // result: (LEAQ1 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { x := v_0_0 y := v_0_1 if !(x.Op != OpSB && y.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg(x) return true } // match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ2 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ4 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ8 { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) y := v_0.Args[1] x := v_0.Args[0] if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ1(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ1 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ1 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64ADDQconst { continue } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ2 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [c] {s} x (SHLQconst [3] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 3 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64LEAQ { continue } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { continue } v.reset(OpAMD64LEAQ1) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } break } // match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64LEAQ1 { continue } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 { if x != v_1_0 { continue } y := v_1_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { continue } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(y, x) return true } } break } // match: (LEAQ1 [0] x y) // cond: v.Aux == nil // result: (ADDQ x y) for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 y := v_1 if !(v.Aux == nil) { break } v.reset(OpAMD64ADDQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ2 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ2 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB // result: (LEAQ2 [c+2*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(c + 2*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ4 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [c] {s} x (SHLQconst [2] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 2 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ2) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil // result: (LEAQ4 [off1+2*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + 2*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ2 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ2 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*2) // result: (LEAQ [off+int32(scale)*2] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*2)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*2) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ4 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ4 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB // result: (LEAQ4 [c+4*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(c + 4*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [c] {s} x (SHLQconst [1] y)) // result: (LEAQ8 [c] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64SHLQconst || auxIntToInt8(v_1.AuxInt) != 1 { break } y := v_1.Args[0] v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ4) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) // cond: is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil // result: (LEAQ8 [off1+4*off2] {sym1} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64LEAQ1 { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) y := v_1.Args[1] if y != v_1.Args[0] || !(is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + 4*off2) v.Aux = symToAux(sym1) v.AddArg2(x, y) return true } // match: (LEAQ4 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ4 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*4) // result: (LEAQ [off+int32(scale)*4] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*4)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*4) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64LEAQ8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (LEAQ8 [c] {s} (ADDQconst [d] x) y) // cond: is32Bit(int64(c)+int64(d)) && x.Op != OpSB // result: (LEAQ8 [c+d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(c)+int64(d)) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [c] {s} x (ADDQconst [d] y)) // cond: is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB // result: (LEAQ8 [c+8*d] {s} x y) for { c := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64ADDQconst { break } d := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(c + 8*d) v.Aux = symToAux(s) v.AddArg2(x, y) return true } // match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB // result: (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) x := v_0.Args[0] y := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB) { break } v.reset(OpAMD64LEAQ8) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(x, y) return true } // match: (LEAQ8 [off] {sym} x (MOVQconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVQconst { break } scale := auxIntToInt64(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } // match: (LEAQ8 [off] {sym} x (MOVLconst [scale])) // cond: is32Bit(int64(off)+int64(scale)*8) // result: (LEAQ [off+int32(scale)*8] {sym} x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 if v_1.Op != OpAMD64MOVLconst { break } scale := auxIntToInt32(v_1.AuxInt) if !(is32Bit(int64(off) + int64(scale)*8)) { break } v.reset(OpAMD64LEAQ) v.AuxInt = int32ToAuxInt(off + int32(scale)*8) v.Aux = symToAux(sym) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBELstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBELstore [i] {s} p (BSWAPL x) m) // result: (MOVLstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPL { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEQstore [i] {s} p (BSWAPQ x) m) // result: (MOVQstore [i] {s} p x m) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 if v_1.Op != OpAMD64BSWAPQ { break } x := v_1.Args[0] m := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, x, m) return true } return false } func rewriteValueAMD64_OpAMD64MOVBEWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 // result: (MOVWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQSX (ANDLconst [c] x)) // cond: c & 0x80 == 0 // result: (ANDLconst [c & 0x7f] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x80 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7f) v.AddArg(x) return true } // match: (MOVBQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } // match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVBload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVBload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVBload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVBQZX x) // cond: zeroUpper56Bits(x,3) // result: x for { x := v_0 if !(zeroUpper56Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVBQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xff) v.AddArg(x) return true } // match: (MOVBQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVBatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVBQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } // match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVBload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read8(sym, int64(off)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read8(sym, int64(off)))) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVBstore [off] {sym} ptr y:(SETL x) mem) // cond: y.Uses == 1 // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETL { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem) // cond: y.Uses == 1 // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETLE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETG x) mem) // cond: y.Uses == 1 // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETG { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem) // cond: y.Uses == 1 // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETGE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) // cond: y.Uses == 1 // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETEQ { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem) // cond: y.Uses == 1 // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETNE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETB x) mem) // cond: y.Uses == 1 // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETB { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem) // cond: y.Uses == 1 // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETBE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETA x) mem) // cond: y.Uses == 1 // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETA { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem) // cond: y.Uses == 1 // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SETAE { break } x := y.Args[0] mem := v_2 if !(y.Uses == 1) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVBQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int8(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVBload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVBstore || auxIntToInt32(mem2.AuxInt) != i-1 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVBload || auxIntToInt32(x2.AuxInt) != j-1 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(j - 1) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVBstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVBstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQSX (ANDLconst [c] x)) // cond: uint32(c) & 0x80000000 == 0 // result: (ANDLconst [c & 0x7fffffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(uint32(c)&0x80000000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fffffff) v.AddArg(x) return true } // match: (MOVLQSX (MOVLQSX x)) // result: (MOVLQSX x) for { if v_0.Op != OpAMD64MOVLQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVLQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQSX) v.AddArg(x) return true } // match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVLload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVLload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVLQZX x) // cond: zeroUpper32Bits(x,3) // result: x for { x := v_0 if !(zeroUpper32Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVLQZX (ANDLconst [c] x)) // result: (ANDLconst [c] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (MOVLQZX (MOVLQZX x)) // result: (MOVLQZX x) for { if v_0.Op != OpAMD64MOVLQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVLQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVLatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVLi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVLload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVLQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVLQZX) v.AddArg(x) return true } // match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) // result: (MOVLf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLf2i) v.AddArg(val) return true } // match: (MOVLload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) // result: (MOVLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVLstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVLload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVLstore || auxIntToInt32(mem2.AuxInt) != i-4 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVLload || auxIntToInt32(x2.AuxInt) != j-4 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(j - 4) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORLload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBL { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORLmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORL { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORLmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORLconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORLconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVLload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORLconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) // result: (MOVSSstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVLstore [i] {s} p x:(BSWAPL w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBELstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPL { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBELstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVOstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVOstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVOstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) // cond: symIsRO(srcSym) // result: (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))]) (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))]) mem)) for { dstOff := auxIntToInt32(v.AuxInt) dstSym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVOload { break } srcOff := auxIntToInt32(v_1.AuxInt) srcSym := auxToSym(v_1.Aux) v_1_0 := v_1.Args[0] if v_1_0.Op != OpSB { break } mem := v_2 if !(symIsRO(srcSym)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(dstOff + 8) v.Aux = symToAux(dstSym) v0 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))) v1 := b.NewValue0(v_1.Pos, OpAMD64MOVQstore, types.TypeMem) v1.AuxInt = int32ToAuxInt(dstOff) v1.Aux = symToAux(dstSym) v2 := b.NewValue0(v_1.Pos, OpAMD64MOVQconst, typ.UInt64) v2.AuxInt = int64ToAuxInt(int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))) v1.AddArg3(ptr, v2, mem) v.AddArg3(ptr, v0, v1) return true } return false } func rewriteValueAMD64_OpAMD64MOVOstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVOstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVOstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVOstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQatomicload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQatomicload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQatomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQatomicload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQf2i(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQf2i (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQi2f(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVQi2f (Arg [off] {sym})) // cond: t.Size() == u.Size() // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } u := v_0.Type off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) if !(t.Size() == u.Size()) { break } b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueAMD64_OpAMD64MOVQload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: x for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.copyOf(x) return true } // match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) // result: (MOVQf2i val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVSDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQf2i) v.AddArg(val) return true } // match: (MOVQload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVQconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVQstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) // cond: validVal(c) // result: (MOVQstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(validVal(c)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem) // cond: y.Uses==1 && clobber(y) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQload || auxIntToInt32(y.AuxInt) != off || auxToSym(y.Aux) != sym { break } mem := y.Args[2] x := y.Args[0] if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && clobber(y)) { break } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ADDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ADDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ADDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (SUBQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64SUBQ { break } x := y.Args[1] l := y.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ANDQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ANDQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ANDQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (ORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64ORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64ORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem) // cond: y.Uses==1 && l.Uses==1 && clobber(y, l) // result: (XORQmodify [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 y := v_1 if y.Op != OpAMD64XORQ { break } _ = y.Args[1] y_0 := y.Args[0] y_1 := y.Args[1] for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 { l := y_0 if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { continue } mem := l.Args[1] if ptr != l.Args[0] { continue } x := y_1 if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && clobber(y, l)) { continue } v.reset(OpAMD64XORQmodify) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } break } // match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ADDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ADDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ANDQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ANDQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (ORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64ORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64ORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem) // cond: isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) // result: (XORQconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 a := v_1 if a.Op != OpAMD64XORQconst { break } c := auxIntToInt32(a.AuxInt) l := a.Args[0] if l.Op != OpAMD64MOVQload || auxIntToInt32(l.AuxInt) != off || auxToSym(l.Aux) != sym { break } mem := l.Args[1] ptr2 := l.Args[0] if mem != v_2 || !(isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a)) { break } v.reset(OpAMD64XORQconstmodify) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(c), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) // result: (MOVSDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQf2i { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVQstore [i] {s} p x:(BSWAPQ w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEQstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64BSWAPQ { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEQstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVQstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVQstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVQstoreconst [c] {s} p1 x:(MOVQstoreconst [a] {s} p0 mem)) // cond: config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { c := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p1 := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } a := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p0 := x.Args[0] if !(config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } // match: (MOVQstoreconst [a] {s} p0 x:(MOVQstoreconst [c] {s} p1 mem)) // cond: config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x) // result: (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem) for { a := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) p0 := v_0 x := v_1 if x.Op != OpAMD64MOVQstoreconst { break } c := auxIntToValAndOff(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] p1 := x.Args[0] if !(config.useSSE && x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && clobber(x)) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, a.Off())) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) // result: (MOVQi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVQi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSDstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) // result: (MOVQstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) // result: (MOVLi2f val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpAMD64MOVLi2f) v.AddArg(val) return true } return false } func rewriteValueAMD64_OpAMD64MOVSSstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVSSstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVSSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVSSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) // result: (MOVLstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLi2f { break } val := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWQSXload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWQSXload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQSX (ANDLconst [c] x)) // cond: c & 0x8000 == 0 // result: (ANDLconst [c & 0x7fff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(c&0x8000 == 0) { break } v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0x7fff) v.AddArg(x) return true } // match: (MOVWQSX (MOVWQSX x)) // result: (MOVWQSX x) for { if v_0.Op != OpAMD64MOVWQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSX (MOVBQSX x)) // result: (MOVBQSX x) for { if v_0.Op != OpAMD64MOVBQSX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQSX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQSXload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQSX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQSX) v.AddArg(x) return true } // match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWQSXload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVWload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVLload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: @x.Block (MOVWload [off] {sym} ptr mem) for { x := v_0 if x.Op != OpAMD64MOVQload { break } off := auxIntToInt32(x.AuxInt) sym := auxToSym(x.Aux) mem := x.Args[1] ptr := x.Args[0] if !(x.Uses == 1 && clobber(x)) { break } b = x.Block v0 := b.NewValue0(x.Pos, OpAMD64MOVWload, v.Type) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } // match: (MOVWQZX x) // cond: zeroUpper48Bits(x,3) // result: x for { x := v_0 if !(zeroUpper48Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVWQZX (ANDLconst [c] x)) // result: (ANDLconst [c & 0xffff] x) for { if v_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(c & 0xffff) v.AddArg(x) return true } // match: (MOVWQZX (MOVWQZX x)) // result: (MOVWQZX x) for { if v_0.Op != OpAMD64MOVWQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWQZX (MOVBQZX x)) // result: (MOVBQZX x) for { if v_0.Op != OpAMD64MOVBQZX { break } x := v_0.Args[0] v.reset(OpAMD64MOVBQZX) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MOVWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVWQZX x) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWstore { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) x := v_1.Args[1] ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpAMD64MOVWQZX) v.AddArg(x) return true } // match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWload [off1+off2] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(base, mem) return true } // match: (MOVWload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQSX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVWQZX { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MOVWstore [off1+off2] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem) // result: (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(int16(c)), off)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x1 := v_1 if x1.Op != OpAMD64MOVWload { break } j := auxIntToInt32(x1.AuxInt) s2 := auxToSym(x1.Aux) mem := x1.Args[1] p2 := x1.Args[0] mem2 := v_2 if mem2.Op != OpAMD64MOVWstore || auxIntToInt32(mem2.AuxInt) != i-2 || auxToSym(mem2.Aux) != s { break } _ = mem2.Args[2] if p != mem2.Args[0] { break } x2 := mem2.Args[1] if x2.Op != OpAMD64MOVWload || auxIntToInt32(x2.AuxInt) != j-2 || auxToSym(x2.Aux) != s2 { break } _ = x2.Args[1] if p2 != x2.Args[0] || mem != x2.Args[1] || mem != mem2.Args[2] || !(x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2)) { break } v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(j - 2) v0.Aux = symToAux(s2) v0.AddArg2(p2, mem) v.AddArg3(p, v0, mem) return true } // match: (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem) // cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3 // result: (MOVBEWstore [i] {s} p w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) p := v_0 x := v_1 if x.Op != OpAMD64ROLWconst || auxIntToInt8(x.AuxInt) != 8 { break } w := x.Args[0] mem := v_2 if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64MOVBEWstore) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg3(p, w, mem) return true } return false } func rewriteValueAMD64_OpAMD64MOVWstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) s := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off := auxIntToInt32(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) // cond: canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) // result: (MOVWstoreconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) for { sc := auxIntToValAndOff(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off)) { break } v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(ValAndOff(sc).addOffset32(off)) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64MULL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULL x (MOVLconst [c])) // result: (MULLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULLconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULLconst [c] (MULLconst [d] x)) // result: (MULLconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64MULLconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULLconst [-9] x) // result: (NEGL (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-5] x) // result: (NEGL (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-3] x) // result: (NEGL (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [-1] x) // result: (NEGL x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGL) v.AddArg(x) return true } // match: (MULLconst [ 0] _) // result: (MOVLconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (MULLconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULLconst [ 3] x) // result: (LEAL2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAL2) v.AddArg2(x, x) return true } // match: (MULLconst [ 5] x) // result: (LEAL4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAL4) v.AddArg2(x, x) return true } // match: (MULLconst [ 7] x) // result: (LEAL2 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [ 9] x) // result: (LEAL8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAL8) v.AddArg2(x, x) return true } // match: (MULLconst [11] x) // result: (LEAL2 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [13] x) // result: (LEAL4 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [19] x) // result: (LEAL2 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [21] x) // result: (LEAL4 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [25] x) // result: (LEAL8 x (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [27] x) // result: (LEAL8 (LEAL2 x x) (LEAL2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [37] x) // result: (LEAL4 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [41] x) // result: (LEAL8 x (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [45] x) // result: (LEAL8 (LEAL4 x x) (LEAL4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [73] x) // result: (LEAL8 x (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULLconst [81] x) // result: (LEAL8 (LEAL8 x x) (LEAL8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBL (SHLLconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAL1 (SHLLconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAL1) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAL2 (SHLLconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAL2) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAL4 (SHLLconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAL4) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAL8 (SHLLconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAL8) v0 := b.NewValue0(v.Pos, OpAMD64SHLLconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULLconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLLconst [int8(log32(c/3))] (LEAL2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLLconst [int8(log32(c/5))] (LEAL4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLLconst [int8(log32(c/9))] (LEAL8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAL8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULLconst [c] (MOVLconst [d])) // result: (MOVLconst [c*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } d := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c * d) return true } return false } func rewriteValueAMD64_OpAMD64MULQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (MULQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64MULQconst(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (MULQconst [c] (MULQconst [d] x)) // cond: is32Bit(int64(c)*int64(d)) // result: (MULQconst [c * d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MULQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(c) * int64(d))) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(c * d) v.AddArg(x) return true } // match: (MULQconst [-9] x) // result: (NEGQ (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != -9 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-5] x) // result: (NEGQ (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != -5 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-3] x) // result: (NEGQ (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != -3 { break } x := v_0 v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [-1] x) // result: (NEGQ x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 v.reset(OpAMD64NEGQ) v.AddArg(x) return true } // match: (MULQconst [ 0] _) // result: (MOVQconst [0]) for { if auxIntToInt32(v.AuxInt) != 0 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MULQconst [ 1] x) // result: x for { if auxIntToInt32(v.AuxInt) != 1 { break } x := v_0 v.copyOf(x) return true } // match: (MULQconst [ 3] x) // result: (LEAQ2 x x) for { if auxIntToInt32(v.AuxInt) != 3 { break } x := v_0 v.reset(OpAMD64LEAQ2) v.AddArg2(x, x) return true } // match: (MULQconst [ 5] x) // result: (LEAQ4 x x) for { if auxIntToInt32(v.AuxInt) != 5 { break } x := v_0 v.reset(OpAMD64LEAQ4) v.AddArg2(x, x) return true } // match: (MULQconst [ 7] x) // result: (LEAQ2 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 7 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [ 9] x) // result: (LEAQ8 x x) for { if auxIntToInt32(v.AuxInt) != 9 { break } x := v_0 v.reset(OpAMD64LEAQ8) v.AddArg2(x, x) return true } // match: (MULQconst [11] x) // result: (LEAQ2 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 11 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [13] x) // result: (LEAQ4 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 13 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [19] x) // result: (LEAQ2 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 19 { break } x := v_0 v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [21] x) // result: (LEAQ4 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 21 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [25] x) // result: (LEAQ8 x (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 25 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [27] x) // result: (LEAQ8 (LEAQ2 x x) (LEAQ2 x x)) for { if auxIntToInt32(v.AuxInt) != 27 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [37] x) // result: (LEAQ4 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 37 { break } x := v_0 v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [41] x) // result: (LEAQ8 x (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 41 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [45] x) // result: (LEAQ8 (LEAQ4 x x) (LEAQ4 x x)) for { if auxIntToInt32(v.AuxInt) != 45 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [73] x) // result: (LEAQ8 x (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 73 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(x, v0) return true } // match: (MULQconst [81] x) // result: (LEAQ8 (LEAQ8 x x) (LEAQ8 x x)) for { if auxIntToInt32(v.AuxInt) != 81 { break } x := v_0 v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg2(v0, v0) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo64(int64(c)+1) && c >= 15 // result: (SUBQ (SHLQconst [int8(log64(int64(c)+1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo64(int64(c)+1) && c >= 15) { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log64(int64(c) + 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-1) && c >= 17 // result: (LEAQ1 (SHLQconst [int8(log32(c-1))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-1) && c >= 17) { break } v.reset(OpAMD64LEAQ1) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 1))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-2) && c >= 34 // result: (LEAQ2 (SHLQconst [int8(log32(c-2))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-2) && c >= 34) { break } v.reset(OpAMD64LEAQ2) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 2))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-4) && c >= 68 // result: (LEAQ4 (SHLQconst [int8(log32(c-4))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-4) && c >= 68) { break } v.reset(OpAMD64LEAQ4) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 4))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: isPowerOfTwo32(c-8) && c >= 136 // result: (LEAQ8 (SHLQconst [int8(log32(c-8))] x) x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isPowerOfTwo32(c-8) && c >= 136) { break } v.reset(OpAMD64LEAQ8) v0 := b.NewValue0(v.Pos, OpAMD64SHLQconst, v.Type) v0.AuxInt = int8ToAuxInt(int8(log32(c - 8))) v0.AddArg(x) v.AddArg2(v0, x) return true } // match: (MULQconst [c] x) // cond: c%3 == 0 && isPowerOfTwo32(c/3) // result: (SHLQconst [int8(log32(c/3))] (LEAQ2 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%3 == 0 && isPowerOfTwo32(c/3)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 3))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ2, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%5 == 0 && isPowerOfTwo32(c/5) // result: (SHLQconst [int8(log32(c/5))] (LEAQ4 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%5 == 0 && isPowerOfTwo32(c/5)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 5))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ4, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] x) // cond: c%9 == 0 && isPowerOfTwo32(c/9) // result: (SHLQconst [int8(log32(c/9))] (LEAQ8 x x)) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c%9 == 0 && isPowerOfTwo32(c/9)) { break } v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(log32(c / 9))) v0 := b.NewValue0(v.Pos, OpAMD64LEAQ8, v.Type) v0.AddArg2(x, x) v.AddArg(v0) return true } // match: (MULQconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(c)*d]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) * d) return true } // match: (MULQconst [c] (NEGQ x)) // cond: c != -(1<<31) // result: (MULQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64MULQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64MULSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSDload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (MULSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64MULSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MULSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (MULSSload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64MULSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64MULSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (MULSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64MULSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64NEGL(v *Value) bool { v_0 := v.Args[0] // match: (NEGL (NEGL x)) // result: x for { if v_0.Op != OpAMD64NEGL { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGL s:(SUBL x y)) // cond: s.Uses == 1 // result: (SUBL y x) for { s := v_0 if s.Op != OpAMD64SUBL { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBL) v.AddArg2(y, x) return true } // match: (NEGL (MOVLconst [c])) // result: (MOVLconst [-c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-c) return true } return false } func rewriteValueAMD64_OpAMD64NEGQ(v *Value) bool { v_0 := v.Args[0] // match: (NEGQ (NEGQ x)) // result: x for { if v_0.Op != OpAMD64NEGQ { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEGQ s:(SUBQ x y)) // cond: s.Uses == 1 // result: (SUBQ y x) for { s := v_0 if s.Op != OpAMD64SUBQ { break } y := s.Args[1] x := s.Args[0] if !(s.Uses == 1) { break } v.reset(OpAMD64SUBQ) v.AddArg2(y, x) return true } // match: (NEGQ (MOVQconst [c])) // result: (MOVQconst [-c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-c) return true } // match: (NEGQ (ADDQconst [c] (NEGQ x))) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { if v_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } x := v_0_0.Args[0] if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64NOTL(v *Value) bool { v_0 := v.Args[0] // match: (NOTL (MOVLconst [c])) // result: (MOVLconst [^c]) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64NOTQ(v *Value) bool { v_0 := v.Args[0] // match: (NOTQ (MOVQconst [c])) // result: (MOVQconst [^c]) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(^c) return true } return false } func rewriteValueAMD64_OpAMD64ORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTSL) v.AddArg2(x, y) return true } break } // match: (ORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (ORL x (MOVLconst [c])) // result: (ORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORL x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORLconst(v *Value) bool { v_0 := v.Args[0] // match: (ORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORLconst [c] (ORLconst [d] x)) // result: (ORLconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORLconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORLconst [c] (BTSLconst [d] x)) // result: (ORLconst [c | 1<= 128 // result: (BTSQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (ORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (ORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (ORQ x (MOVLconst [c])) // result: (ORQconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (ORQ (SHRQ lo bits) (SHLQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLQ lo bits) (SHRQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHRXQ lo bits) (SHLXQ hi (NEGQ bits))) // result: (SHRDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHRXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHLXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHRDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (SHLXQ lo bits) (SHRXQ hi (NEGQ bits))) // result: (SHLDQ lo hi bits) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLXQ { continue } bits := v_0.Args[1] lo := v_0.Args[0] if v_1.Op != OpAMD64SHRXQ { continue } _ = v_1.Args[1] hi := v_1.Args[0] v_1_1 := v_1.Args[1] if v_1_1.Op != OpAMD64NEGQ || bits != v_1_1.Args[0] { continue } v.reset(OpAMD64SHLDQ) v.AddArg3(lo, hi, bits) return true } break } // match: (ORQ (MOVQconst [c]) (MOVQconst [d])) // result: (MOVQconst [c|d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpAMD64MOVQconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c | d) return true } break } // match: (ORQ x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64ORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64ORQconst(v *Value) bool { v_0 := v.Args[0] // match: (ORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTSQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTSQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (ORQconst [c] (ORQconst [d] x)) // result: (ORQconst [c | d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64ORQconst) v.AuxInt = int32ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORQconst [c] (BTSQconst [d] x)) // cond: is32Bit(int64(c) | 1<>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int8(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARL x (MOVQconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (MOVLconst [c])) // result: (SARLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SARL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SARL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } // match: (SARL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SARL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SARL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARL l:(MOVLload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SARXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARLconst(v *Value) bool { v_0 := v.Args[0] // match: (SARLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARLconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int32(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int32(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SARQ x (MOVQconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (MOVLconst [c])) // result: (SARQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SARQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SARQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } // match: (SARQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SARQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SARQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SARQ l:(MOVQload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SARXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SARXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SARQconst(v *Value) bool { v_0 := v.Args[0] // match: (SARQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARQconst [c] (MOVQconst [d])) // result: (MOVQconst [d>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SARW x (MOVQconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } // match: (SARW x (MOVLconst [c])) // result: (SARWconst [int8(min(int64(c)&31,15))] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SARWconst) v.AuxInt = int8ToAuxInt(int8(min(int64(c)&31, 15))) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SARWconst(v *Value) bool { v_0 := v.Args[0] // match: (SARWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SARWconst [c] (MOVQconst [d])) // result: (MOVQconst [int64(int16(d))>>uint64(c)]) for { c := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(int16(d)) >> uint64(c)) return true } return false } func rewriteValueAMD64_OpAMD64SARXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SARXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SARLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SARXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SARXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SARXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SBBLcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBLcarrymask (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagLT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SBBLcarrymask (FlagGT_ULT)) // result: (MOVLconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(-1) return true } // match: (SBBLcarrymask (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQ x (MOVQconst [c]) borrow) // cond: is32Bit(c) // result: (SBBQconst x [int32(c)] borrow) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) borrow := v_2 if !(is32Bit(c)) { break } v.reset(OpAMD64SBBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(x, borrow) return true } // match: (SBBQ x y (FlagEQ)) // result: (SUBQborrow x y) for { x := v_0 y := v_1 if v_2.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQborrow) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpAMD64SBBQcarrymask(v *Value) bool { v_0 := v.Args[0] // match: (SBBQcarrymask (FlagEQ)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagLT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagLT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SBBQcarrymask (FlagGT_ULT)) // result: (MOVQconst [-1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (SBBQcarrymask (FlagGT_UGT)) // result: (MOVQconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SBBQconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SBBQconst x [c] (FlagEQ)) // result: (SUBQconstborrow x [c]) for { c := auxIntToInt32(v.AuxInt) x := v_0 if v_1.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SETA(v *Value) bool { v_0 := v.Args[0] // match: (SETA (InvertFlags x)) // result: (SETB x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (SETA (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETA (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETA (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAE(v *Value) bool { v_0 := v.Args[0] // match: (SETAE (TESTQ x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTL x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTW x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (TESTB x x)) // result: (ConstBool [true]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(true) return true } // match: (SETAE (InvertFlags x)) // result: (SETBE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (SETAE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETAE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETAE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETAEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETAstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETAstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETAstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETAstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETB(v *Value) bool { v_0 := v.Args[0] // match: (SETB (TESTQ x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTQ { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTL x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTL { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTW x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTW { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (TESTB x x)) // result: (ConstBool [false]) for { if v_0.Op != OpAMD64TESTB { break } x := v_0.Args[1] if x != v_0.Args[0] { break } v.reset(OpConstBool) v.AuxInt = boolToAuxInt(false) return true } // match: (SETB (BTLconst [0] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64BTLconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (BTQconst [0] x)) // result: (ANDQconst [1] x) for { if v_0.Op != OpAMD64BTQconst || auxIntToInt8(v_0.AuxInt) != 0 { break } x := v_0.Args[0] v.reset(OpAMD64ANDQconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETB (InvertFlags x)) // result: (SETA x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (SETB (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETB (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETB (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBE(v *Value) bool { v_0 := v.Args[0] // match: (SETBE (InvertFlags x)) // result: (SETAE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (SETBE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETBE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETBE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETBEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETBstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETAstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETAstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETBstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETEQ(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETAE (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETAE (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETEQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAE (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAE (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETEQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETAE (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETNE (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETNE (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETAE (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETAE (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETAE) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETEQ (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETEQ (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) // result: (SETEQ (Select1 blsr)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { continue } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg(v0) return true } break } // match: (SETEQ (TESTL s:(Select0 blsr:(BLSRL _)) s)) // result: (SETEQ (Select1 blsr)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_0_1 { continue } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg(v0) return true } break } return false } func rewriteValueAMD64_OpAMD64SETEQstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETAEstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETAEstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETAEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETEQstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETEQstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETEQstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETG(v *Value) bool { v_0 := v.Args[0] // match: (SETG (InvertFlags x)) // result: (SETL x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (SETG (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETG (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETG (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGE(v *Value) bool { v_0 := v.Args[0] // match: (SETGE (InvertFlags x)) // result: (SETLE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (SETGE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagLT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagLT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETGE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETGE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } return false } func rewriteValueAMD64_OpAMD64SETGEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETGstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETGstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETLstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETGstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETGstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETL(v *Value) bool { v_0 := v.Args[0] // match: (SETL (InvertFlags x)) // result: (SETG x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (SETL (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETL (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETL (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLE(v *Value) bool { v_0 := v.Args[0] // match: (SETLE (InvertFlags x)) // result: (SETGE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (SETLE (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETLE (FlagGT_ULT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETLE (FlagGT_UGT)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SETLEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETLstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETLstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETGstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETGstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETLstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETLstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETLstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SETNE(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (SETNE (TESTBconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTBconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTWconst [1] x)) // result: (ANDLconst [1] x) for { if v_0.Op != OpAMD64TESTWconst || auxIntToInt16(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64ANDLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } // match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (SETB (BTL x y)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (SETB (BTQ x y)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } break } // match: (SETNE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETB (BTLconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETB (BTQconst [int8(log32(c))] x)) for { if v_0.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg(v0) return true } // match: (SETNE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (SETB (BTQconst [int8(log64(c))] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _))) // result: (SETEQ (CMPLconst [0] s)) for { if v_0.Op != OpAMD64CMPLconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _))) // result: (SETEQ (CMPQconst [0] s)) for { if v_0.Op != OpAMD64CMPQconst || auxIntToInt32(v_0.AuxInt) != 1 { break } s := v_0.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg(v0) return true } // match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (SETB (BTQconst [0] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (SETB (BTLconst [0] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (SETB (BTQconst [63] x)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (SETB (BTLconst [31] x)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (SETNE (InvertFlags x)) // result: (SETNE x) for { if v_0.Op != OpAMD64InvertFlags { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (SETNE (FlagEQ)) // result: (MOVLconst [0]) for { if v_0.Op != OpAMD64FlagEQ { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SETNE (FlagLT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagLT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagLT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_ULT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_ULT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (FlagGT_UGT)) // result: (MOVLconst [1]) for { if v_0.Op != OpAMD64FlagGT_UGT { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(1) return true } // match: (SETNE (TESTQ s:(Select0 blsr:(BLSRQ _)) s)) // result: (SETNE (Select1 blsr)) for { if v_0.Op != OpAMD64TESTQ { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { continue } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg(v0) return true } break } // match: (SETNE (TESTL s:(Select0 blsr:(BLSRL _)) s)) // result: (SETNE (Select1 blsr)) for { if v_0.Op != OpAMD64TESTL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_0_1 { continue } v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) v.AddArg(v0) return true } break } return false } func rewriteValueAMD64_OpAMD64SETNEstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTL x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLL { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) // result: (SETBstore [off] {sym} ptr (BTQ x y) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64SHLQ { continue } x := v_1_0.Args[1] v_1_0_0 := v_1_0.Args[0] if v_1_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_1_0_0.AuxInt) != 1 { continue } y := v_1_1 mem := v_2 v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem) // cond: isUint32PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTLconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint32PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem) // cond: isUint64PowerOfTwo(int64(c)) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQconst { break } c := auxIntToInt32(v_1.AuxInt) x := v_1.Args[0] mem := v_2 if !(isUint64PowerOfTwo(int64(c))) { break } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) // cond: isUint64PowerOfTwo(c) // result: (SETBstore [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { if v_1_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1_0.AuxInt) x := v_1_1 mem := v_2 if !(isUint64PowerOfTwo(c)) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPLconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDLconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) // result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64CMPQconst || auxIntToInt32(v_1.AuxInt) != 1 { break } s := v_1.Args[0] if s.Op != OpAMD64ANDQconst || auxIntToInt32(s.AuxInt) != 1 { break } mem := v_2 v.reset(OpAMD64SETEQstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(s) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTQ { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) // cond: z1==z2 // result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64TESTL { break } _ = v_1.Args[1] v_1_0 := v_1.Args[0] v_1_1 := v_1.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 { z1 := v_1_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_1_1 mem := v_2 if !(z1 == z2) { continue } v.reset(OpAMD64SETBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) v.AddArg3(ptr, v0, mem) return true } break } // match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem) // result: (SETNEstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64InvertFlags { break } x := v_1.Args[0] mem := v_2 v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SETNEstore [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SETNEstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SETNEstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagEQ) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [0]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagEQ { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagLT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_ULT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } // match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) // result: (MOVBstore [off] {sym} ptr (MOVLconst [1]) mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64FlagGT_UGT { break } mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpAMD64MOVLconst, typ.UInt8) v0.AuxInt = int32ToAuxInt(1) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLL x (MOVQconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (MOVLconst [c])) // result: (SHLLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHLL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHLL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } // match: (SHLL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHLL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHLL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLL l:(MOVLload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHLXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLLconst [1] (SHRLconst [1] x)) // result: (BTRLconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLLconst [d] (MOVLconst [c])) // result: (MOVLconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(c << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHLQ x (MOVQconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (MOVLconst [c])) // result: (SHLQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHLQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHLQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } // match: (SHLQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHLQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHLQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHLQ l:(MOVQload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHLXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHLXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHLQconst [1] (SHRQconst [1] x)) // result: (BTRQconst [0] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHRQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } // match: (SHLQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SHLQconst [d] (MOVQconst [c])) // result: (MOVQconst [c << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(c << uint64(d)) return true } // match: (SHLQconst [d] (MOVLconst [c])) // result: (MOVQconst [int64(c) << uint64(d)]) for { d := auxIntToInt8(v.AuxInt) if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(int64(c) << uint64(d)) return true } return false } func rewriteValueAMD64_OpAMD64SHLXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHLXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHLLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHLXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHLXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SHLXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHLQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRB x (MOVQconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB x (MOVLconst [c])) // cond: c&31 < 8 // result: (SHRBconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 8) { break } v.reset(OpAMD64SHRBconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRB _ (MOVQconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRB _ (MOVLconst [c])) // cond: c&31 >= 8 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 8) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRBconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRBconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRL x (MOVQconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (MOVLconst [c])) // result: (SHRLconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRL x (ADDQconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ADDQconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDQconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGQ (ANDQconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ADDLconst [c] y)) // cond: c & 31 == 0 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ADDLconst [c] y))) // cond: c & 31 == 0 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 0) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL x (ANDLconst [c] y)) // cond: c & 31 == 31 // result: (SHRL x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } // match: (SHRL x (NEGL (ANDLconst [c] y))) // cond: c & 31 == 31 // result: (SHRL x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&31 == 31) { break } v.reset(OpAMD64SHRL) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRL l:(MOVLload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHRXLload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRLconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRLconst [1] (SHLLconst [1] x)) // result: (BTRLconst [31] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLLconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRLconst) v.AuxInt = int8ToAuxInt(31) v.AddArg(x) return true } // match: (SHRLconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SHRQ x (MOVQconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (MOVLconst [c])) // result: (SHRQconst [int8(c&63)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v.AddArg(x) return true } // match: (SHRQ x (ADDQconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ADDQconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDQconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGQ (ANDQconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGQ y)) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDQconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ADDLconst [c] y)) // cond: c & 63 == 0 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ADDLconst [c] y))) // cond: c & 63 == 0 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ADDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 0) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ x (ANDLconst [c] y)) // cond: c & 63 == 63 // result: (SHRQ x y) for { x := v_0 if v_1.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1.AuxInt) y := v_1.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } // match: (SHRQ x (NEGL (ANDLconst [c] y))) // cond: c & 63 == 63 // result: (SHRQ x (NEGL y)) for { x := v_0 if v_1.Op != OpAMD64NEGL { break } t := v_1.Type v_1_0 := v_1.Args[0] if v_1_0.Op != OpAMD64ANDLconst { break } c := auxIntToInt32(v_1_0.AuxInt) y := v_1_0.Args[0] if !(c&63 == 63) { break } v.reset(OpAMD64SHRQ) v0 := b.NewValue0(v.Pos, OpAMD64NEGL, t) v0.AddArg(y) v.AddArg2(x, v0) return true } // match: (SHRQ l:(MOVQload [off] {sym} ptr mem) x) // cond: buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) // result: (SHRXQload [off] {sym} ptr x mem) for { l := v_0 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] x := v_1 if !(buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l)) { break } v.reset(OpAMD64SHRXQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRQconst [1] (SHLQconst [1] x)) // result: (BTRQconst [63] x) for { if auxIntToInt8(v.AuxInt) != 1 || v_0.Op != OpAMD64SHLQconst || auxIntToInt8(v_0.AuxInt) != 1 { break } x := v_0.Args[0] v.reset(OpAMD64BTRQconst) v.AuxInt = int8ToAuxInt(63) v.AddArg(x) return true } // match: (SHRQconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHRW x (MOVQconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW x (MOVLconst [c])) // cond: c&31 < 16 // result: (SHRWconst [int8(c&31)] x) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 < 16) { break } v.reset(OpAMD64SHRWconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v.AddArg(x) return true } // match: (SHRW _ (MOVQconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SHRW _ (MOVLconst [c])) // cond: c&31 >= 16 // result: (MOVLconst [0]) for { if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) if !(c&31 >= 16) { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } return false } func rewriteValueAMD64_OpAMD64SHRWconst(v *Value) bool { v_0 := v.Args[0] // match: (SHRWconst x [0]) // result: x for { if auxIntToInt8(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } return false } func rewriteValueAMD64_OpAMD64SHRXLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHRXLload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHRLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRLconst) v.AuxInt = int8ToAuxInt(int8(c & 31)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SHRXQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SHRXQload [off] {sym} ptr (MOVQconst [c]) mem) // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } // match: (SHRXQload [off] {sym} ptr (MOVLconst [c]) mem) // result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpAMD64SHRQconst) v.AuxInt = int8ToAuxInt(int8(c & 63)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBL x (MOVLconst [c])) // result: (SUBLconst x [c]) for { x := v_0 if v_1.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64SUBLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } // match: (SUBL (MOVLconst [c]) x) // result: (NEGL (SUBLconst x [c])) for { if v_0.Op != OpAMD64MOVLconst { break } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64NEGL) v0 := b.NewValue0(v.Pos, OpAMD64SUBLconst, v.Type) v0.AuxInt = int32ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (SUBL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBLload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBLconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBLconst [c] x) // cond: c==0 // result: x for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c == 0) { break } v.copyOf(x) return true } // match: (SUBLconst [c] x) // result: (ADDLconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 v.reset(OpAMD64ADDLconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } } func rewriteValueAMD64_OpAMD64SUBLload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) // result: (SUBL x (MOVLf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSSstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBL) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLf2i, typ.UInt32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBLmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBLmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBLmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUBQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconst x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } // match: (SUBQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (NEGQ (SUBQconst x [int32(c)])) for { if v_0.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64SUBQconst, v.Type) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (SUBQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SUBQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBQload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBQborrow(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQborrow x (MOVQconst [c])) // cond: is32Bit(c) // result: (SUBQconstborrow x [int32(c)]) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { break } v.reset(OpAMD64SUBQconstborrow) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBQconst [0] x) // result: x for { if auxIntToInt32(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SUBQconst [c] x) // cond: c != -(1<<31) // result: (ADDQconst [-c] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(c != -(1 << 31)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(x) return true } // match: (SUBQconst (MOVQconst [d]) [c]) // result: (MOVQconst [d-int64(c)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(d - int64(c)) return true } // match: (SUBQconst (SUBQconst x [d]) [c]) // cond: is32Bit(int64(-c)-int64(d)) // result: (ADDQconst [-c-d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64SUBQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(is32Bit(int64(-c) - int64(d))) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(-c - d) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpAMD64SUBQload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) // result: (SUBQ x (MOVQf2i y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVSDstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBQ) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQf2i, typ.UInt64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBQmodify(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBQmodify [off1+off2] {sym} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_0.AuxInt) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(base, val, mem) return true } // match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBQmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) base := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBQmodify) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(base, val, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSDload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSDload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSDload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSDload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) // result: (SUBSD x (MOVQi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVQstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSD) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVQi2f, typ.Float64) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64SUBSS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (SUBSSload x [off] {sym} ptr mem) for { x := v_0 l := v_1 if l.Op != OpAMD64MOVSSload { break } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64SUBSSload(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (SUBSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, base, mem) return true } // match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) // result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) base := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)) { break } v.reset(OpAMD64SUBSSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, base, mem) return true } // match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) // result: (SUBSS x (MOVLi2f y)) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) x := v_0 ptr := v_1 if v_2.Op != OpAMD64MOVLstore || auxIntToInt32(v_2.AuxInt) != off || auxToSym(v_2.Aux) != sym { break } y := v_2.Args[1] if ptr != v_2.Args[0] { break } v.reset(OpAMD64SUBSS) v0 := b.NewValue0(v_2.Pos, OpAMD64MOVLi2f, typ.Float32) v0.AddArg(y) v.AddArg2(x, v0) return true } return false } func rewriteValueAMD64_OpAMD64TESTB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTB (MOVLconst [c]) x) // result: (TESTBconst [int8(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTBconst) v.AuxInt = int8ToAuxInt(int8(c)) v.AddArg(x) return true } break } // match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPBconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVBload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPBconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTBconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTBconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTB x x) for { if auxIntToInt8(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTB) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTL (MOVLconst [c]) x) // result: (TESTLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPLconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPLconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTL a:(ANDLload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTL (MOVLload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDLload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTL) v0 := b.NewValue0(a.Pos, OpAMD64MOVLload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTLconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTLconst [c] (MOVLconst [c])) // cond: c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTLconst [c] (MOVLconst [c])) // cond: c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0.AuxInt) != c || !(c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTLconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTL x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTL) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTQ (MOVQconst [c]) x) // cond: is32Bit(c) // result: (TESTQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(is32Bit(c)) { continue } v.reset(OpAMD64TESTQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPQconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPQconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } // match: (TESTQ a:(ANDQload [off] {sym} x ptr mem) a) // cond: a.Uses == 2 && a.Block == v.Block && clobber(a) // result: (TESTQ (MOVQload [off] {sym} ptr mem) x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if a.Op != OpAMD64ANDQload { continue } off := auxIntToInt32(a.AuxInt) sym := auxToSym(a.Aux) mem := a.Args[2] x := a.Args[0] ptr := a.Args[1] if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && clobber(a)) { continue } v.reset(OpAMD64TESTQ) v0 := b.NewValue0(a.Pos, OpAMD64MOVQload, a.Type) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTQconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c == 0 // result: (FlagEQ) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c == 0) { break } v.reset(OpAMD64FlagEQ) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c < 0 // result: (FlagLT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c < 0) { break } v.reset(OpAMD64FlagLT_UGT) return true } // match: (TESTQconst [c] (MOVQconst [d])) // cond: int64(c) == d && c > 0 // result: (FlagGT_UGT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64MOVQconst { break } d := auxIntToInt64(v_0.AuxInt) if !(int64(c) == d && c > 0) { break } v.reset(OpAMD64FlagGT_UGT) return true } // match: (TESTQconst [-1] x) // cond: x.Op != OpAMD64MOVQconst // result: (TESTQ x x) for { if auxIntToInt32(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVQconst) { break } v.reset(OpAMD64TESTQ) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64TESTW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TESTW (MOVLconst [c]) x) // result: (TESTWconst [int16(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 v.reset(OpAMD64TESTWconst) v.AuxInt = int16ToAuxInt(int16(c)) v.AddArg(x) return true } break } // match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2) // cond: l == l2 && l.Uses == 2 && clobber(l) // result: @l.Block (CMPWconstload {sym} [makeValAndOff(0, off)] ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { l := v_0 if l.Op != OpAMD64MOVWload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] l2 := v_1 if !(l == l2 && l.Uses == 2 && clobber(l)) { continue } b = l.Block v0 := b.NewValue0(l.Pos, OpAMD64CMPWconstload, types.TypeFlags) v.copyOf(v0) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, off)) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) return true } break } return false } func rewriteValueAMD64_OpAMD64TESTWconst(v *Value) bool { v_0 := v.Args[0] // match: (TESTWconst [-1] x) // cond: x.Op != OpAMD64MOVLconst // result: (TESTW x x) for { if auxIntToInt16(v.AuxInt) != -1 { break } x := v_0 if !(x.Op != OpAMD64MOVLconst) { break } v.reset(OpAMD64TESTW) v.AddArg2(x, x) return true } return false } func rewriteValueAMD64_OpAMD64XADDLlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDLlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDLlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XADDQlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XADDQlock [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XADDQlock) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGL(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGL [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGL) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XCHGQ(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (XCHGQ [off1+off2] {sym} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst { break } off2 := auxIntToInt32(v_1.AuxInt) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1) + int64(off2))) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(sym) v.AddArg3(val, ptr, mem) return true } // match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) // cond: is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB // result: (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64LEAQ { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr := v_1.Args[0] mem := v_2 if !(is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB) { break } v.reset(OpAMD64XCHGQ) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(val, ptr, mem) return true } return false } func rewriteValueAMD64_OpAMD64XORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (XORL (SHLL (MOVLconst [1]) y) x) // result: (BTCL x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64SHLL { continue } y := v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0.AuxInt) != 1 { continue } x := v_1 v.reset(OpAMD64BTCL) v.AddArg2(x, y) return true } break } // match: (XORL (MOVLconst [c]) x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_0.AuxInt) x := v_1 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } break } // match: (XORL x (MOVLconst [c])) // result: (XORLconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVLconst { continue } c := auxIntToInt32(v_1.AuxInt) v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c) v.AddArg(x) return true } break } // match: (XORL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORLload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVLload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORLload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORL x (ADDLconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKL x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDLconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKL) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORLconst(v *Value) bool { v_0 := v.Args[0] // match: (XORLconst [c] x) // cond: isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCLconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint32PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCLconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORLconst [1] (SETNE x)) // result: (SETEQ x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETNE { break } x := v_0.Args[0] v.reset(OpAMD64SETEQ) v.AddArg(x) return true } // match: (XORLconst [1] (SETEQ x)) // result: (SETNE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETEQ { break } x := v_0.Args[0] v.reset(OpAMD64SETNE) v.AddArg(x) return true } // match: (XORLconst [1] (SETL x)) // result: (SETGE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETL { break } x := v_0.Args[0] v.reset(OpAMD64SETGE) v.AddArg(x) return true } // match: (XORLconst [1] (SETGE x)) // result: (SETL x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETGE { break } x := v_0.Args[0] v.reset(OpAMD64SETL) v.AddArg(x) return true } // match: (XORLconst [1] (SETLE x)) // result: (SETG x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETLE { break } x := v_0.Args[0] v.reset(OpAMD64SETG) v.AddArg(x) return true } // match: (XORLconst [1] (SETG x)) // result: (SETLE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETG { break } x := v_0.Args[0] v.reset(OpAMD64SETLE) v.AddArg(x) return true } // match: (XORLconst [1] (SETB x)) // result: (SETAE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETB { break } x := v_0.Args[0] v.reset(OpAMD64SETAE) v.AddArg(x) return true } // match: (XORLconst [1] (SETAE x)) // result: (SETB x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETAE { break } x := v_0.Args[0] v.reset(OpAMD64SETB) v.AddArg(x) return true } // match: (XORLconst [1] (SETBE x)) // result: (SETA x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETBE { break } x := v_0.Args[0] v.reset(OpAMD64SETA) v.AddArg(x) return true } // match: (XORLconst [1] (SETA x)) // result: (SETBE x) for { if auxIntToInt32(v.AuxInt) != 1 || v_0.Op != OpAMD64SETA { break } x := v_0.Args[0] v.reset(OpAMD64SETBE) v.AddArg(x) return true } // match: (XORLconst [c] (XORLconst [d] x)) // result: (XORLconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORLconst [c] (BTCLconst [d] x)) // result: (XORLconst [c ^ 1<= 128 // result: (BTCQconst [int8(log64(c))] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0.AuxInt) x := v_1 if !(isUint64PowerOfTwo(c) && uint64(c) >= 128) { continue } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log64(c))) v.AddArg(x) return true } break } // match: (XORQ x (MOVQconst [c])) // cond: is32Bit(c) // result: (XORQconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(is32Bit(c)) { continue } v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } // match: (XORQ x x) // result: (MOVQconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (XORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (XORQload x [off] {sym} ptr mem) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 l := v_1 if l.Op != OpAMD64MOVQload { continue } off := auxIntToInt32(l.AuxInt) sym := auxToSym(l.Aux) mem := l.Args[1] ptr := l.Args[0] if !(canMergeLoadClobber(v, l, x) && clobber(l)) { continue } v.reset(OpAMD64XORQload) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(x, ptr, mem) return true } break } // match: (XORQ x (ADDQconst [-1] x)) // cond: buildcfg.GOAMD64 >= 3 // result: (BLSMSKQ x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64ADDQconst || auxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) { continue } v.reset(OpAMD64BLSMSKQ) v.AddArg(x) return true } break } return false } func rewriteValueAMD64_OpAMD64XORQconst(v *Value) bool { v_0 := v.Args[0] // match: (XORQconst [c] x) // cond: isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128 // result: (BTCQconst [int8(log32(c))] x) for { c := auxIntToInt32(v.AuxInt) x := v_0 if !(isUint64PowerOfTwo(int64(c)) && uint64(c) >= 128) { break } v.reset(OpAMD64BTCQconst) v.AuxInt = int8ToAuxInt(int8(log32(c))) v.AddArg(x) return true } // match: (XORQconst [c] (XORQconst [d] x)) // result: (XORQconst [c ^ d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64XORQconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(OpAMD64XORQconst) v.AuxInt = int32ToAuxInt(c ^ d) v.AddArg(x) return true } // match: (XORQconst [c] (BTCQconst [d] x)) // cond: is32Bit(int64(c) ^ 1< val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore64(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore64 ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStore8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStore8 ptr val mem) // result: (Select1 (XCHGB val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpAtomicStorePtrNoWB(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicStorePtrNoWB ptr val mem) // result: (Select1 (XCHGQ val ptr mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem)) v0.AddArg3(val, ptr, mem) v.AddArg(v0) return true } } func rewriteValueAMD64_OpBitLen16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen16 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVWQZX x) (MOVWQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen16 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVWQZX x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v2 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, x.Type) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSRQ (LEAQ1 [1] (MOVLQZX x) (MOVLQZX x)))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64LEAQ1, typ.UInt64) v1.AuxInt = int32ToAuxInt(1) v2 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v2.AddArg(x) v1.AddArg2(v2, v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (BitLen32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // cond: buildcfg.GOAMD64 < 3 // result: (ADDQconst [1] (CMOVQEQ (Select0 (BSRQ x)) (MOVQconst [-1]) (Select1 (BSRQ x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(1) v0 := b.NewValue0(v.Pos, OpAMD64CMOVQEQ, t) v1 := b.NewValue0(v.Pos, OpSelect0, t) v2 := b.NewValue0(v.Pos, OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(x) v1.AddArg(v2) v3 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v3.AuxInt = int64ToAuxInt(-1) v4 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4.AddArg(v2) v0.AddArg3(v1, v3, v4) v.AddArg(v0) return true } // match: (BitLen64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-64] (LZCNTQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-64) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTQ, typ.UInt64) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBitLen8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen8 x) // cond: buildcfg.GOAMD64 < 3 // result: (BSRL (LEAL1 [1] (MOVBQZX x) (MOVBQZX x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSRL) v0 := b.NewValue0(v.Pos, OpAMD64LEAL1, typ.UInt32) v0.AuxInt = int32ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v.AddArg(v0) return true } // match: (BitLen8 x) // cond: buildcfg.GOAMD64 >= 3 // result: (NEGQ (ADDQconst [-32] (LZCNTL (MOVBQZX x)))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64NEGQ) v0 := b.NewValue0(v.Pos, OpAMD64ADDQconst, t) v0.AuxInt = int32ToAuxInt(-32) v1 := b.NewValue0(v.Pos, OpAMD64LZCNTL, typ.UInt32) v2 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, x.Type) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpBswap16(v *Value) bool { v_0 := v.Args[0] // match: (Bswap16 x) // result: (ROLWconst [8] x) for { x := v_0 v.reset(OpAMD64ROLWconst) v.AuxInt = int8ToAuxInt(8) v.AddArg(x) return true } } func rewriteValueAMD64_OpCeil(v *Value) bool { v_0 := v.Args[0] // match: (Ceil x) // result: (ROUNDSD [2] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(2) v.AddArg(x) return true } } func rewriteValueAMD64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (CondSelect x y (SETEQ cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: (is64BitInt(t) || isPtr(t)) // result: (CMOVQGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64CMOVQGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is32BitInt(t) // result: (CMOVLEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is32BitInt(t) // result: (CMOVLNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is32BitInt(t) // result: (CMOVLLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is32BitInt(t) // result: (CMOVLGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is32BitInt(t) // result: (CMOVLLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is32BitInt(t) // result: (CMOVLGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is32BitInt(t) // result: (CMOVLHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is32BitInt(t) // result: (CMOVLCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is32BitInt(t) // result: (CMOVLCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is32BitInt(t) // result: (CMOVLLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is32BitInt(t) // result: (CMOVLEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is32BitInt(t) // result: (CMOVLNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is32BitInt(t) // result: (CMOVLGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is32BitInt(t) // result: (CMOVLGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is32BitInt(t)) { break } v.reset(OpAMD64CMOVLGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQ cond)) // cond: is16BitInt(t) // result: (CMOVWEQ y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQ { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQ) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNE cond)) // cond: is16BitInt(t) // result: (CMOVWNE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETL cond)) // cond: is16BitInt(t) // result: (CMOVWLT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETL { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETG cond)) // cond: is16BitInt(t) // result: (CMOVWGT y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETG { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGT) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETLE cond)) // cond: is16BitInt(t) // result: (CMOVWLE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETLE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGE cond)) // cond: is16BitInt(t) // result: (CMOVWGE y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGE) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETA cond)) // cond: is16BitInt(t) // result: (CMOVWHI y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETA { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWHI) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETB cond)) // cond: is16BitInt(t) // result: (CMOVWCS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETB { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETAE cond)) // cond: is16BitInt(t) // result: (CMOVWCC y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETAE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWCC) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETBE cond)) // cond: is16BitInt(t) // result: (CMOVWLS y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETBE { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWLS) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETEQF cond)) // cond: is16BitInt(t) // result: (CMOVWEQF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETEQF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWEQF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETNEF cond)) // cond: is16BitInt(t) // result: (CMOVWNEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETNEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGF cond)) // cond: is16BitInt(t) // result: (CMOVWGTF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGTF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y (SETGEF cond)) // cond: is16BitInt(t) // result: (CMOVWGEF y x cond) for { t := v.Type x := v_0 y := v_1 if v_2.Op != OpAMD64SETGEF { break } cond := v_2.Args[0] if !(is16BitInt(t)) { break } v.reset(OpAMD64CMOVWGEF) v.AddArg3(y, x, cond) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 1 // result: (CondSelect x y (MOVBQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 1) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 2 // result: (CondSelect x y (MOVWQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 2) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 4 // result: (CondSelect x y (MOVLQZX check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 4) { break } v.reset(OpCondSelect) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64MOVLQZX, typ.UInt64) v0.AddArg(check) v.AddArg3(x, y, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t)) // result: (CMOVQNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))) { break } v.reset(OpAMD64CMOVQNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t) // result: (CMOVLNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)) { break } v.reset(OpAMD64CMOVLNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } // match: (CondSelect x y check) // cond: !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t) // result: (CMOVWNE y x (CMPQconst [0] check)) for { t := v.Type x := v_0 y := v_1 check := v_2 if !(!check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)) { break } v.reset(OpAMD64CMOVWNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v0.AddArg(check) v.AddArg3(y, x, v0) return true } return false } func rewriteValueAMD64_OpConst16(v *Value) bool { // match: (Const16 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt16(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConst8(v *Value) bool { // match: (Const8 [c]) // result: (MOVLconst [int32(c)]) for { c := auxIntToInt8(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(int32(c)) return true } } func rewriteValueAMD64_OpConstBool(v *Value) bool { // match: (ConstBool [c]) // result: (MOVLconst [b2i32(c)]) for { c := auxIntToBool(v.AuxInt) v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(b2i32(c)) return true } } func rewriteValueAMD64_OpConstNil(v *Value) bool { // match: (ConstNil ) // result: (MOVQconst [0]) for { v.reset(OpAMD64MOVQconst) v.AuxInt = int64ToAuxInt(0) return true } } func rewriteValueAMD64_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (BSFL (BTSLconst [16] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(16) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz16NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz16NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz32 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32 x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ (BTSQconst [32] x))) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpAMD64BTSQconst, typ.UInt64) v1.AuxInt = int8ToAuxInt(32) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz32NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz32NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64 x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64 x) // cond: buildcfg.GOAMD64 < 3 // result: (CMOVQEQ (Select0 (BSFQ x)) (MOVQconst [64]) (Select1 (BSFQ x))) for { t := v.Type x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64CMOVQEQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v1 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg(x) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpAMD64MOVQconst, t) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v3.AddArg(v1) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueAMD64_OpCtz64NonZero(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTQ x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTQ) v.AddArg(x) return true } // match: (Ctz64NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (Select0 (BSFQ x)) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueAMD64_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (BSFL (BTSLconst [ 8] x)) for { x := v_0 v.reset(OpAMD64BSFL) v0 := b.NewValue0(v.Pos, OpAMD64BTSLconst, typ.UInt32) v0.AuxInt = int8ToAuxInt(8) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool { v_0 := v.Args[0] // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 >= 3 // result: (TZCNTL x) for { x := v_0 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64TZCNTL) v.AddArg(x) return true } // match: (Ctz8NonZero x) // cond: buildcfg.GOAMD64 < 3 // result: (BSFL x) for { x := v_0 if !(buildcfg.GOAMD64 < 3) { break } v.reset(OpAMD64BSFL) v.AddArg(x) return true } return false } func rewriteValueAMD64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 [a] x y) // result: (Select0 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (Select0 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32 [a] x y) // result: (Select0 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div32u x y) // result: (Select0 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64 [a] x y) // result: (Select0 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div64u x y) // result: (Select0 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect0) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq16 x y) // result: (SETEQ (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32 x y) // result: (SETEQ (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32F x y) // result: (SETEQF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64 x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64F x y) // result: (SETEQF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq8 x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqB x y) // result: (SETEQ (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqPtr x y) // result: (SETEQ (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETEQ) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpFMA(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMA x y z) // result: (VFMADD231SD z x y) for { x := v_0 y := v_1 z := v_2 v.reset(OpAMD64VFMADD231SD) v.AddArg3(z, x, y) return true } } func rewriteValueAMD64_OpFloor(v *Value) bool { v_0 := v.Args[0] // match: (Floor x) // result: (ROUNDSD [1] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpGetG(v *Value) bool { v_0 := v.Args[0] // match: (GetG mem) // cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal // result: (LoweredGetG mem) for { mem := v_0 if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) { break } v.reset(OpAMD64LoweredGetG) v.AddArg(mem) return true } return false } func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool { b := v.Block typ := &b.Func.Config.Types // match: (HasCPUFeature {s}) // result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s}))) for { s := auxToSym(v.Aux) v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64) v1.Aux = symToAux(s) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsInBounds idx len) // result: (SETB (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsNonNil(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (IsNonNil p) // result: (SETNE (TESTQ p p)) for { p := v_0 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) v0.AddArg2(p, p) v.AddArg(v0) return true } } func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsSliceInBounds idx len) // result: (SETBE (CMPQ idx len)) for { idx := v_0 len := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16 x y) // result: (SETLE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq16U x y) // result: (SETBE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32 x y) // result: (SETLE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32F x y) // result: (SETGEF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32U x y) // result: (SETBE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64 x y) // result: (SETLE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64F x y) // result: (SETGEF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64U x y) // result: (SETBE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8 x y) // result: (SETLE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETLE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq8U x y) // result: (SETBE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETBE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16 x y) // result: (SETL (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less16U x y) // result: (SETB (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 x y) // result: (SETL (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32F x y) // result: (SETGF (UCOMISS y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32U x y) // result: (SETB (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 x y) // result: (SETL (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64F x y) // result: (SETGF (UCOMISD y x)) for { x := v_0 y := v_1 v.reset(OpAMD64SETGF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64U x y) // result: (SETB (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8 x y) // result: (SETL (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETL) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less8U x y) // result: (SETB (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETB) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVQload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpAMD64MOVQload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitInt(t) // result: (MOVLload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t)) { break } v.reset(OpAMD64MOVLload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is16BitInt(t) // result: (MOVWload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t)) { break } v.reset(OpAMD64MOVWload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (t.IsBoolean() || is8BitInt(t)) // result: (MOVBload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsBoolean() || is8BitInt(t)) { break } v.reset(OpAMD64MOVBload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (MOVSSload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitFloat(t)) { break } v.reset(OpAMD64MOVSSload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (MOVSDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitFloat(t)) { break } v.reset(OpAMD64MOVSDload) v.AddArg2(ptr, mem) return true } return false } func rewriteValueAMD64_OpLocalAddr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (LocalAddr {sym} base mem) // cond: t.Elem().HasPointers() // result: (LEAQ {sym} (SPanchored base mem)) for { t := v.Type sym := auxToSym(v.Aux) base := v_0 mem := v_1 if !(t.Elem().HasPointers()) { break } v.reset(OpAMD64LEAQ) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr) v0.AddArg2(base, mem) v.AddArg(v0) return true } // match: (LocalAddr {sym} base _) // cond: !t.Elem().HasPointers() // result: (LEAQ {sym} base) for { t := v.Type sym := auxToSym(v.Aux) base := v_0 if !(!t.Elem().HasPointers()) { break } v.reset(OpAMD64LEAQ) v.Aux = symToAux(sym) v.AddArg(base) return true } return false } func rewriteValueAMD64_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SHLQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SHLL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHLL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16 [a] x y) // result: (Select1 (DIVW [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (Select1 (DIVWU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32 [a] x y) // result: (Select1 (DIVL [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod32u x y) // result: (Select1 (DIVLU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64 [a] x y) // result: (Select1 (DIVQ [a] x y)) for { a := auxIntToBool(v.AuxInt) x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64)) v0.AuxInt = boolToAuxInt(a) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod64u x y) // result: (Select1 (DIVQU x y)) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64)) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16)) v1 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to16, typ.Int16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) for { x := v_0 y := v_1 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16)) v1 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to16, typ.UInt16) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueAMD64_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [2] dst src mem) // result: (MOVWstore dst (MOVWload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [4] dst src mem) // result: (MOVLstore dst (MOVLload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [8] dst src mem) // result: (MOVQstore dst (MOVQload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVQstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: config.useSSE // result: (MOVOstore dst (MOVOload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstore) v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [16] dst src mem) // cond: !config.useSSE // result: (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [32] dst src mem) // result: (Move [16] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpMove) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [48] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [16]) (OffPtr src [16]) (Move [16] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 48 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [64] dst src mem) // cond: config.useSSE // result: (Move [32] (OffPtr dst [32]) (OffPtr src [32]) (Move [32] dst src mem)) for { if auxIntToInt64(v.AuxInt) != 64 { break } dst := v_0 src := v_1 mem := v_2 if !(config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(32) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(32) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(32) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(2) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [6] dst src mem) // result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [7] dst src mem) // result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVLstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [10] dst src mem) // result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, typ.UInt16) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [12] dst src mem) // result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpAMD64MOVLstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, typ.UInt32) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s == 11 || s >= 13 && s <= 15 // result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s == 11 || s >= 13 && s <= 15) { break } v.reset(OpAMD64MOVQstore) v.AuxInt = int32ToAuxInt(int32(s - 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v0.AuxInt = int32ToAuxInt(int32(s - 8)) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 <= 8 // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore dst (MOVQload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 <= 8) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVOstore dst (MOVOload src mem) mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, types.TypeMem) v3 := b.NewValue0(v.Pos, OpAMD64MOVOload, types.TypeInt128) v3.AddArg2(src, mem) v2.AddArg3(dst, v3, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE // result: (Move [s-s%16] (OffPtr dst [s%16]) (OffPtr src [s%16]) (MOVQstore [8] dst (MOVQload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s % 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v2.AuxInt = int32ToAuxInt(8) v3 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v3.AuxInt = int32ToAuxInt(8) v3.AddArg2(src, mem) v4 := b.NewValue0(v.Pos, OpAMD64MOVQstore, types.TypeMem) v5 := b.NewValue0(v.Pos, OpAMD64MOVQload, typ.UInt64) v5.AddArg2(src, mem) v4.AddArg3(dst, v5, mem) v2.AddArg3(dst, v3, v4) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s) // result: (DUFFCOPY [s] dst src mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s)) { break } v.reset(OpAMD64DUFFCOPY) v.AuxInt = int64ToAuxInt(s) v.AddArg3(dst, src, mem) return true } // match: (Move [s] dst src mem) // cond: (s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s) // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !((s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s)) { break } v.reset(OpAMD64REPMOVSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v.AddArg4(dst, src, v0, mem) return true } return false } func rewriteValueAMD64_OpNeg32F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg32F x) // result: (PXOR x (MOVSSconst [float32(math.Copysign(0, -1))])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSSconst, typ.Float32) v0.AuxInt = float32ToAuxInt(float32(math.Copysign(0, -1))) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeg64F(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neg64F x) // result: (PXOR x (MOVSDconst [math.Copysign(0, -1)])) for { x := v_0 v.reset(OpAMD64PXOR) v0 := b.NewValue0(v.Pos, OpAMD64MOVSDconst, typ.Float64) v0.AuxInt = float64ToAuxInt(math.Copysign(0, -1)) v.AddArg2(x, v0) return true } } func rewriteValueAMD64_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq16 x y) // result: (SETNE (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32 x y) // result: (SETNE (CMPL x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32F x y) // result: (SETNEF (UCOMISS x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64 x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64F x y) // result: (SETNEF (UCOMISD x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNEF) v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq8 x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqB x y) // result: (SETNE (CMPB x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqPtr x y) // result: (SETNE (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64SETNE) v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueAMD64_OpNot(v *Value) bool { v_0 := v.Args[0] // match: (Not x) // result: (XORLconst [1] x) for { x := v_0 v.reset(OpAMD64XORLconst) v.AuxInt = int32ToAuxInt(1) v.AddArg(x) return true } } func rewriteValueAMD64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (OffPtr [off] ptr) // cond: is32Bit(off) // result: (ADDQconst [int32(off)] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 if !(is32Bit(off)) { break } v.reset(OpAMD64ADDQconst) v.AuxInt = int32ToAuxInt(int32(off)) v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDQ (MOVQconst [off]) ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(off) v.AddArg2(v0, ptr) return true } } func rewriteValueAMD64_OpPanicBounds(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 0) { break } v.reset(OpAMD64LoweredPanicBoundsA) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 1) { break } v.reset(OpAMD64LoweredPanicBoundsB) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 2) { break } v.reset(OpAMD64LoweredPanicBoundsC) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } return false } func rewriteValueAMD64_OpPopCount16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (POPCNTL (MOVWQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVWQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpPopCount8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount8 x) // result: (POPCNTL (MOVBQZX x)) for { x := v_0 v.reset(OpAMD64POPCNTL) v0 := b.NewValue0(v.Pos, OpAMD64MOVBQZX, typ.UInt32) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpRoundToEven(v *Value) bool { v_0 := v.Args[0] // match: (RoundToEven x) // result: (ROUNDSD [0] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(0) v.AddArg(x) return true } } func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPWconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPLconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPQconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRW x y) (SBBLcarrymask (CMPBconst y [16]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRW, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(16) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SARW x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [16]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(16) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SARW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARW) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPWconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPLconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPQconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRL x y) (SBBLcarrymask (CMPBconst y [32]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(32) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SARL x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [32]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(32) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SARL x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPWconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPLconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPQconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDQ (SHRQ x y) (SBBQcarrymask (CMPBconst y [64]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDQ) v0 := b.NewValue0(v.Pos, OpAMD64SHRQ, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(64) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SARQ x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [64]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(64) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SARQ x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARQ) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPWconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v2.AuxInt = int16ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPLconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPQconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v2.AuxInt = int32ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (ANDL (SHRB x y) (SBBLcarrymask (CMPBconst y [8]))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64ANDL) v0 := b.NewValue0(v.Pos, OpAMD64SHRB, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v2.AuxInt = int8ToAuxInt(8) v2.AddArg(y) v1.AddArg(v2) v.AddArg2(v0, v1) return true } // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SHRB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SHRB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPWconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) v3.AuxInt = int16ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPLconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORQ y (NOTQ (SBBQcarrymask (CMPQconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORQ, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTQ, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) v3.AuxInt = int32ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SARB x (ORL y (NOTL (SBBLcarrymask (CMPBconst y [8]))))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.Type = t v0 := b.NewValue0(v.Pos, OpAMD64ORL, y.Type) v1 := b.NewValue0(v.Pos, OpAMD64NOTL, y.Type) v2 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, y.Type) v3 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) v3.AuxInt = int8ToAuxInt(8) v3.AddArg(y) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg2(y, v1) v.AddArg2(x, v0) return true } // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SARB x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpAMD64SARB) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64_OpSelect0(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uover x y)) // result: (Select0 (MULQU x y)) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Mul32uover x y)) // result: (Select0 (MULLU x y)) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpSelect0) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y c)) // result: (Select0 (SBBQ x y (Select1 (NEGLflags c)))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (AddTupleFirst32 val tuple)) // result: (ADDL val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDL) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } // match: (Select0 (AddTupleFirst64 val tuple)) // result: (ADDQ val (Select0 tuple)) for { t := v.Type if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] val := v_0.Args[0] v.reset(OpAMD64ADDQ) v0 := b.NewValue0(v.Pos, OpSelect0, t) v0.AddArg(tuple) v.AddArg2(val, v0) return true } return false } func rewriteValueAMD64_OpSelect1(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uover x y)) // result: (SETO (Select1 (MULQU x y))) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul32uover x y)) // result: (SETO (Select1 (MULLU x y))) for { if v_0.Op != OpMul32uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpAMD64SETO) v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags)) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Add64carry x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (ADCQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y c)) // result: (NEGQ (SBBQcarrymask (Select1 (SBBQ x y (Select1 (NEGLflags c)))))) for { if v_0.Op != OpSub64borrow { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpAMD64NEGQ) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags)) v4.AddArg(c) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (NEGLflags (MOVQconst [0]))) // result: (FlagEQ) for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0.AuxInt) != 0 { break } v.reset(OpAMD64FlagEQ) return true } // match: (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) // result: x for { if v_0.Op != OpAMD64NEGLflags { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64NEGQ { break } v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64SBBQcarrymask { break } x := v_0_0_0.Args[0] v.copyOf(x) return true } // match: (Select1 (AddTupleFirst32 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst32 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } // match: (Select1 (AddTupleFirst64 _ tuple)) // result: (Select1 tuple) for { if v_0.Op != OpAMD64AddTupleFirst64 { break } tuple := v_0.Args[1] v.reset(OpSelect1) v.AddArg(tuple) return true } return false } func rewriteValueAMD64_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem))))) // cond: sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call) // result: (Move [sc.Val64()] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpAMD64MOVQstoreconst { break } sc := auxIntToValAndOff(s1.AuxInt) _ = s1.Args[1] s2 := s1.Args[1] if s2.Op != OpAMD64MOVQstore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpAMD64MOVQstore { break } mem := s3.Args[2] dst := s3.Args[1] if !(sc.Val64() >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sc.Val64(), config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sc.Val64()) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem)) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpAMD64CALLstatic || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpAMD64MOVQconst { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } return false } func rewriteValueAMD64_OpSlicemask(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Slicemask x) // result: (SARQconst (NEGQ x) [63]) for { t := v.Type x := v_0 v.reset(OpAMD64SARQconst) v.AuxInt = int8ToAuxInt(63) v0 := b.NewValue0(v.Pos, OpAMD64NEGQ, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueAMD64_OpSpectreIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreIndex x y) // result: (CMOVQCC x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQCC) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpSpectreSliceIndex(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SpectreSliceIndex x y) // result: (CMOVQHI x (MOVQconst [0]) (CMPQ x y)) for { x := v_0 y := v_1 v.reset(OpAMD64CMOVQHI) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) v1.AddArg2(x, y) v.AddArg3(x, v0, v1) return true } } func rewriteValueAMD64_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && t.IsFloat() // result: (MOVSDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && t.IsFloat()) { break } v.reset(OpAMD64MOVSDstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && t.IsFloat() // result: (MOVSSstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && t.IsFloat()) { break } v.reset(OpAMD64MOVSSstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && !t.IsFloat() // result: (MOVQstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && !t.IsFloat()) { break } v.reset(OpAMD64MOVQstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && !t.IsFloat() // result: (MOVLstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && !t.IsFloat()) { break } v.reset(OpAMD64MOVLstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 2 // result: (MOVWstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 2) { break } v.reset(OpAMD64MOVWstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 1 // result: (MOVBstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 1) { break } v.reset(OpAMD64MOVBstore) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueAMD64_OpTrunc(v *Value) bool { v_0 := v.Args[0] // match: (Trunc x) // result: (ROUNDSD [3] x) for { x := v_0 v.reset(OpAMD64ROUNDSD) v.AuxInt = int8ToAuxInt(3) v.AddArg(x) return true } } func rewriteValueAMD64_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [0] _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_1 v.copyOf(mem) return true } // match: (Zero [1] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [2] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [4] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [8] destptr mem) // result: (MOVQstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [3] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 2)) v0 := b.NewValue0(v.Pos, OpAMD64MOVWstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [5] destptr mem) // result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVBstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [6] destptr mem) // result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVWstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 4)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [7] destptr mem) // result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } destptr := v_0 mem := v_1 v.reset(OpAMD64MOVLstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 3)) v0 := b.NewValue0(v.Pos, OpAMD64MOVLstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%8 != 0 && s > 8 && !config.useSSE // result: (Zero [s-s%8] (OffPtr destptr [s%8]) (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%8 != 0 && s > 8 && !config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%8) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 8) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [24] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 24 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [32] destptr mem) // cond: !config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(!config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 24)) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 8)) v2 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 8 && s < 16 && config.useSSE // result: (MOVQstoreconst [makeValAndOff(0,int32(s-8))] destptr (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 8 && s < 16 && config.useSSE) { break } v.reset(OpAMD64MOVQstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, int32(s-8))) v0 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] destptr mem) // cond: s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE // result: (Zero [s-s%16] (OffPtr destptr [s%16]) (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(s - s%16) v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type) v0.AuxInt = int64ToAuxInt(s % 16) v0.AddArg(destptr) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [16] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,0)] destptr mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v.AddArg2(destptr, mem) return true } // match: (Zero [32] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v0.AddArg2(destptr, mem) v.AddArg2(destptr, v0) return true } // match: (Zero [48] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v1.AddArg2(destptr, mem) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [64] destptr mem) // cond: config.useSSE // result: (MOVOstoreconst [makeValAndOff(0,48)] destptr (MOVOstoreconst [makeValAndOff(0,32)] destptr (MOVOstoreconst [makeValAndOff(0,16)] destptr (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } destptr := v_0 mem := v_1 if !(config.useSSE) { break } v.reset(OpAMD64MOVOstoreconst) v.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 48)) v0 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v0.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 32)) v1 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v1.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 16)) v2 := b.NewValue0(v.Pos, OpAMD64MOVOstoreconst, types.TypeMem) v2.AuxInt = valAndOffToAuxInt(makeValAndOff(0, 0)) v2.AddArg2(destptr, mem) v1.AddArg2(destptr, v2) v0.AddArg2(destptr, v1) v.AddArg2(destptr, v0) return true } // match: (Zero [s] destptr mem) // cond: s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice // result: (DUFFZERO [s] destptr mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !(s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice) { break } v.reset(OpAMD64DUFFZERO) v.AuxInt = int64ToAuxInt(s) v.AddArg2(destptr, mem) return true } // match: (Zero [s] destptr mem) // cond: (s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0 // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem) for { s := auxIntToInt64(v.AuxInt) destptr := v_0 mem := v_1 if !((s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32)) && s%8 == 0) { break } v.reset(OpAMD64REPSTOSQ) v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(s / 8) v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(0) v.AddArg4(destptr, v0, v1, mem) return true } return false } func rewriteBlockAMD64(b *Block) bool { typ := &b.Func.Config.Types switch b.Kind { case BlockAMD64EQ: // match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (UGE (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (UGE (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (UGE (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (UGE (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } // match: (EQ (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (UGE (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (UGE (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (UGE (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (UGE (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (UGE (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64UGE, v0) return true } break } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (EQ (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (EQ (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (TESTQ s:(Select0 blsr:(BLSRQ _)) s) yes no) // result: (EQ (Select1 blsr) yes no) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { continue } v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) b.resetWithControl(BlockAMD64EQ, v0) return true } break } // match: (EQ (TESTL s:(Select0 blsr:(BLSRL _)) s) yes no) // result: (EQ (Select1 blsr) yes no) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_0_1 { continue } v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) b.resetWithControl(BlockAMD64EQ, v0) return true } break } case BlockAMD64GE: // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (GE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (GE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64GT: // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (GT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (GT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockIf: // match: (If (SETL cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64SETL { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (If (SETLE cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64SETLE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (If (SETG cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64SETG { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (If (SETGE cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64SETGE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (If (SETEQ cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64SETEQ { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (If (SETNE cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64SETNE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (If (SETB cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64SETB { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (If (SETBE cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64SETBE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (If (SETA cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETA { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETAE cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETAE { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETO cmp) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64SETO { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (If (SETGF cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64SETGF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (If (SETGEF cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64SETGEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (If (SETEQF cmp) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64SETEQF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (If (SETNEF cmp) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64SETNEF { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (If cond yes no) // result: (NE (TESTB cond cond) yes no) for { cond := b.Controls[0] v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags) v0.AddArg2(cond, cond) b.resetWithControl(BlockAMD64NE, v0) return true } case BlockJumpTable: // match: (JumpTable idx) // result: (JUMPTABLE {makeJumpTableSym(b)} idx (LEAQ {makeJumpTableSym(b)} (SB))) for { idx := b.Controls[0] v0 := b.NewValue0(b.Pos, OpAMD64LEAQ, typ.Uintptr) v0.Aux = symToAux(makeJumpTableSym(b)) v1 := b.NewValue0(b.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) b.resetWithControl2(BlockAMD64JUMPTABLE, idx, v0) b.Aux = symToAux(makeJumpTableSym(b)) return true } case BlockAMD64LE: // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (LE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64LT: // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (LT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (LT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (LT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64NE: // match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETL { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LT, cmp) return true } // match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETLE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64LE, cmp) return true } // match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETG { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GT, cmp) return true } // match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64GE, cmp) return true } // match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQ { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQ, cmp) return true } // match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETB { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETBE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETA { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETAE { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no) // result: (OS cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETO { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64OS, cmp) return true } // match: (NE (TESTL (SHLL (MOVLconst [1]) x) y)) // result: (ULT (BTL x y)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLL { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y)) // result: (ULT (BTQ x y)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64SHLQ { continue } x := v_0_0.Args[1] v_0_0_0 := v_0_0.Args[0] if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 { continue } y := v_0_1 v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTLconst [c] x)) // cond: isUint32PowerOfTwo(int64(c)) // result: (ULT (BTLconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTLconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint32PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQconst [c] x)) // cond: isUint64PowerOfTwo(int64(c)) // result: (ULT (BTQconst [int8(log32(c))] x)) for b.Controls[0].Op == OpAMD64TESTQconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(isUint64PowerOfTwo(int64(c))) { break } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log32(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } // match: (NE (TESTQ (MOVQconst [c]) x)) // cond: isUint64PowerOfTwo(c) // result: (ULT (BTQconst [int8(log64(c))] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { if v_0_0.Op != OpAMD64MOVQconst { continue } c := auxIntToInt64(v_0_0.AuxInt) x := v_0_1 if !(isUint64PowerOfTwo(c)) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(int8(log64(c))) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) // cond: z1==z2 // result: (ULT (BTQconst [0] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) // cond: z1==z2 // result: (ULT (BTLconst [0] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } z1_0 := z1.Args[0] if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 { continue } x := z1_0.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(0) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTQ z1:(SHRQconst [63] x) z2)) // cond: z1==z2 // result: (ULT (BTQconst [63] x)) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(63) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTL z1:(SHRLconst [31] x) z2)) // cond: z1==z2 // result: (ULT (BTLconst [31] x)) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { z1 := v_0_0 if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 { continue } x := z1.Args[0] z2 := v_0_1 if !(z1 == z2) { continue } v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags) v0.AuxInt = int8ToAuxInt(31) v0.AddArg(x) b.resetWithControl(BlockAMD64ULT, v0) return true } break } // match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETGEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) // result: (EQF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETEQF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64EQF, cmp) return true } // match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) // result: (NEF cmp yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] if v_0_0.Op != OpAMD64SETNEF { break } cmp := v_0_0.Args[0] v_0_1 := v_0.Args[1] if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] { break } b.resetWithControl(BlockAMD64NEF, cmp) return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64NE, cmp) return true } // match: (NE (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (NE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } // match: (NE (TESTQ s:(Select0 blsr:(BLSRQ _)) s) yes no) // result: (NE (Select1 blsr) yes no) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRQ || s != v_0_1 { continue } v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) b.resetWithControl(BlockAMD64NE, v0) return true } break } // match: (NE (TESTL s:(Select0 blsr:(BLSRL _)) s) yes no) // result: (NE (Select1 blsr) yes no) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { s := v_0_0 if s.Op != OpSelect0 { continue } blsr := s.Args[0] if blsr.Op != OpAMD64BLSRL || s != v_0_1 { continue } v0 := b.NewValue0(v_0.Pos, OpSelect1, types.TypeFlags) v0.AddArg(blsr) b.resetWithControl(BlockAMD64NE, v0) return true } break } case BlockAMD64UGE: // match: (UGE (TESTQ x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTL x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTW x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (TESTB x x) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) return true } // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULE, cmp) return true } // match: (UGE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (UGE (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGE (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64UGT: // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64ULT, cmp) return true } // match: (UGT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagLT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) return true } // match: (UGT (FlagGT_ULT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (FlagGT_UGT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) return true } case BlockAMD64ULE: // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGE, cmp) return true } // match: (ULE (FlagEQ) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULE (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockAMD64ULT: // match: (ULT (TESTQ x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTQ { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTL x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTL { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTW x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTW { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (TESTB x x) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64TESTB { v_0 := b.Controls[0] x := v_0.Args[1] if x != v_0.Args[0] { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpAMD64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockAMD64UGT, cmp) return true } // match: (ULT (FlagEQ) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagEQ { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagLT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagLT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagLT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagLT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (FlagGT_ULT) yes no) // result: (First yes no) for b.Controls[0].Op == OpAMD64FlagGT_ULT { b.Reset(BlockFirst) return true } // match: (ULT (FlagGT_UGT) yes no) // result: (First no yes) for b.Controls[0].Op == OpAMD64FlagGT_UGT { b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- diff -- @@ -620,6 +620,8 @@ return rewriteValueAMD64_OpBitLen64(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8(v) + case OpBswap16: + return rewriteValueAMD64_OpBswap16(v) case OpBswap32: v.Op = OpAMD64BSWAPL return true @@ -10482,823 +10484,6 @@ v.AddArg3(base, val, mem) return true } - // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) - // cond: x0.Uses == 1 && clobber(x0) - // result: (MOVWstore [i-1] {s} p (ROLWconst [8] w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { - break - } - mem := x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) - v0.AuxInt = int8ToAuxInt(8) - v0.AddArg(w) - v.AddArg3(p, v0, mem) - return true - } - // match: (MOVBstore [i] {s} p1 w x0:(MOVBstore [i] {s} p0 (SHRWconst [8] w) mem)) - // cond: x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0) - // result: (MOVWstore [i] {s} p0 (ROLWconst [8] w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - break - } - mem := x0.Args[2] - p0 := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) - v0.AuxInt = int8ToAuxInt(8) - v0.AddArg(w) - v.AddArg3(p0, v0, mem) - return true - } - // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) - // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x2 := v_2 - if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-1 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - if p != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { - break - } - x1 := x2.Args[2] - if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { - break - } - x0 := x1.Args[2] - if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-3 || auxToSym(x0.Aux) != s { - break - } - mem := x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i - 3) - v.Aux = symToAux(s) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) - v0.AddArg(w) - v.AddArg3(p, v0, mem) - return true - } - // match: (MOVBstore [i] {s} p3 w x2:(MOVBstore [i] {s} p2 (SHRLconst [8] w) x1:(MOVBstore [i] {s} p1 (SHRLconst [16] w) x0:(MOVBstore [i] {s} p0 (SHRLconst [24] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2) - // result: (MOVLstore [i] {s} p0 (BSWAPL w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p3 := v_0 - w := v_1 - x2 := v_2 - if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - p2 := x2.Args[0] - x2_1 := x2.Args[1] - if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { - break - } - x1 := x2.Args[2] - if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - p1 := x1.Args[0] - x1_1 := x1.Args[1] - if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { - break - } - x0 := x1.Args[2] - if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - break - } - mem := x0.Args[2] - p0 := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) - v0.AddArg(w) - v.AddArg3(p0, v0, mem) - return true - } - // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6) - // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x6 := v_2 - if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i-1 || auxToSym(x6.Aux) != s { - break - } - _ = x6.Args[2] - if p != x6.Args[0] { - break - } - x6_1 := x6.Args[1] - if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { - break - } - x5 := x6.Args[2] - if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i-2 || auxToSym(x5.Aux) != s { - break - } - _ = x5.Args[2] - if p != x5.Args[0] { - break - } - x5_1 := x5.Args[1] - if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { - break - } - x4 := x5.Args[2] - if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i-3 || auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[2] - if p != x4.Args[0] { - break - } - x4_1 := x4.Args[1] - if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { - break - } - x3 := x4.Args[2] - if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i-4 || auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[2] - if p != x3.Args[0] { - break - } - x3_1 := x3.Args[1] - if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { - break - } - x2 := x3.Args[2] - if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-5 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - if p != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { - break - } - x1 := x2.Args[2] - if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-6 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { - break - } - x0 := x1.Args[2] - if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-7 || auxToSym(x0.Aux) != s { - break - } - mem := x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(i - 7) - v.Aux = symToAux(s) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, typ.UInt64) - v0.AddArg(w) - v.AddArg3(p, v0, mem) - return true - } - // match: (MOVBstore [i] {s} p7 w x6:(MOVBstore [i] {s} p6 (SHRQconst [8] w) x5:(MOVBstore [i] {s} p5 (SHRQconst [16] w) x4:(MOVBstore [i] {s} p4 (SHRQconst [24] w) x3:(MOVBstore [i] {s} p3 (SHRQconst [32] w) x2:(MOVBstore [i] {s} p2 (SHRQconst [40] w) x1:(MOVBstore [i] {s} p1 (SHRQconst [48] w) x0:(MOVBstore [i] {s} p0 (SHRQconst [56] w) mem)))))))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6) - // result: (MOVQstore [i] {s} p0 (BSWAPQ w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p7 := v_0 - w := v_1 - x6 := v_2 - if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i || auxToSym(x6.Aux) != s { - break - } - _ = x6.Args[2] - p6 := x6.Args[0] - x6_1 := x6.Args[1] - if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { - break - } - x5 := x6.Args[2] - if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i || auxToSym(x5.Aux) != s { - break - } - _ = x5.Args[2] - p5 := x5.Args[0] - x5_1 := x5.Args[1] - if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { - break - } - x4 := x5.Args[2] - if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i || auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[2] - p4 := x4.Args[0] - x4_1 := x4.Args[1] - if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { - break - } - x3 := x4.Args[2] - if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i || auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[2] - p3 := x3.Args[0] - x3_1 := x3.Args[1] - if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { - break - } - x2 := x3.Args[2] - if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - p2 := x2.Args[0] - x2_1 := x2.Args[1] - if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { - break - } - x1 := x2.Args[2] - if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - p1 := x1.Args[0] - x1_1 := x1.Args[1] - if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { - break - } - x0 := x1.Args[2] - if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - break - } - mem := x0.Args[2] - p0 := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, typ.UInt64) - v0.AddArg(w) - v.AddArg3(p0, v0, mem) - return true - } - // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i-1] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i-1] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i-1] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i-1] {s} p w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRLconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - w0 := x.Args[1] - if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(p, w0, mem) - return true - } - // match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i-1] {s} p w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRQconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - w0 := x.Args[1] - if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(p, w0, mem) - return true - } - // match: (MOVBstore [i] {s} p1 (SHRWconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVBstore [i] {s} p1 (SHRLconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVBstore [i] {s} p1 (SHRQconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRWconst [8] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p0 := v_0 - w := v_1 - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p1 := x.Args[0] - x_1 := x.Args[1] - if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRLconst [8] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p0 := v_0 - w := v_1 - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p1 := x.Args[0] - x_1 := x.Args[1] - if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRQconst [8] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p0 := v_0 - w := v_1 - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p1 := x.Args[0] - x_1 := x.Args[1] - if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVBstore [i] {s} p1 (SHRLconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRLconst [j-8] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRLconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w0, mem) - return true - } - // match: (MOVBstore [i] {s} p1 (SHRQconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRQconst [j-8] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRQconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w0, mem) - return true - } - // match: (MOVBstore [c3] {s} p3 (SHRQconst [56] w) x1:(MOVWstore [c2] {s} p2 (SHRQconst [40] w) x2:(MOVLstore [c1] {s} p1 (SHRQconst [8] w) x3:(MOVBstore [c0] {s} p0 w mem)))) - // cond: x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1 + c0 - c1)) && sequentialAddresses(p0, p2, int64(5 + c0 - c2)) && sequentialAddresses(p0, p3, int64(7 + c0 - c3)) && clobber(x1, x2, x3) - // result: (MOVQstore [c0] {s} p0 w mem) - for { - c3 := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p3 := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 56 { - break - } - w := v_1.Args[0] - x1 := v_2 - if x1.Op != OpAMD64MOVWstore { - break - } - c2 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - p2 := x1.Args[0] - x1_1 := x1.Args[1] - if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 40 || w != x1_1.Args[0] { - break - } - x2 := x1.Args[2] - if x2.Op != OpAMD64MOVLstore { - break - } - c1 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - p1 := x2.Args[0] - x2_1 := x2.Args[1] - if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { - break - } - x3 := x2.Args[2] - if x3.Op != OpAMD64MOVBstore { - break - } - c0 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - break - } - mem := x3.Args[2] - p0 := x3.Args[0] - if w != x3.Args[1] || !(x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1+c0-c1)) && sequentialAddresses(p0, p2, int64(5+c0-c2)) && sequentialAddresses(p0, p3, int64(7+c0-c3)) && clobber(x1, x2, x3)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(c0) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) @@ -11388,58 +10573,6 @@ v.AddArg2(ptr, mem) return true } - // match: (MOVBstoreconst [c] {s} p1 x:(MOVBstoreconst [a] {s} p0 mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) - // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) - for { - c := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - x := v_1 - if x.Op != OpAMD64MOVBstoreconst { - break - } - a := auxIntToValAndOff(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - p0 := x.Args[0] - if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) - v.Aux = symToAux(s) - v.AddArg2(p0, mem) - return true - } - // match: (MOVBstoreconst [a] {s} p0 x:(MOVBstoreconst [c] {s} p1 mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) - // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) - for { - a := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - p0 := v_0 - x := v_1 - if x.Op != OpAMD64MOVBstoreconst { - break - } - c := auxIntToValAndOff(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - p1 := x.Args[0] - if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) - v.Aux = symToAux(s) - v.AddArg2(p0, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64MOVLQSX(v *Value) bool { @@ -12019,115 +11152,6 @@ v.AddArg3(base, val, mem) return true } - // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVQstore [i-4] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(i - 4) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVQstore [i-4] {s} p w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRQconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - w0 := x.Args[1] - if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(i - 4) - v.Aux = symToAux(s) - v.AddArg3(p, w0, mem) - return true - } - // match: (MOVLstore [i] {s} p1 (SHRQconst [32] w) x:(MOVLstore [i] {s} p0 w mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) - // result: (MOVQstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVLstore [i] {s} p1 (SHRQconst [j] w) x:(MOVLstore [i] {s} p0 w0:(SHRQconst [j-32] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) - // result: (MOVQstore [i] {s} p0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRQconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w0, mem) - return true - } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) @@ -12575,8 +11599,6 @@ func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) @@ -12620,62 +11642,6 @@ v.AddArg2(ptr, mem) return true } - // match: (MOVLstoreconst [c] {s} p1 x:(MOVLstoreconst [a] {s} p0 mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) - // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) - for { - c := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - x := v_1 - if x.Op != OpAMD64MOVLstoreconst { - break - } - a := auxIntToValAndOff(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - p0 := x.Args[0] - if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(a.Off()) - v.Aux = symToAux(s) - v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) - v.AddArg3(p0, v0, mem) - return true - } - // match: (MOVLstoreconst [a] {s} p0 x:(MOVLstoreconst [c] {s} p1 mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) - // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) - for { - a := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - p0 := v_0 - x := v_1 - if x.Op != OpAMD64MOVLstoreconst { - break - } - c := auxIntToValAndOff(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - p1 := x.Args[0] - if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(a.Off()) - v.Aux = symToAux(s) - v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) - v.AddArg3(p0, v0, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { @@ -14387,224 +13353,6 @@ v.AddArg3(base, val, mem) return true } - // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVLstore [i-2] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVLstore [i-2] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVLstore [i-2] {s} p w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRLconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - w0 := x.Args[1] - if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(p, w0, mem) - return true - } - // match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVLstore [i-2] {s} p w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRQconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - w0 := x.Args[1] - if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(p, w0, mem) - return true - } - // match: (MOVWstore [i] {s} p1 (SHRLconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) - // result: (MOVLstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVWstore [i] {s} p1 (SHRQconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) - // result: (MOVLstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVWstore [i] {s} p1 (SHRLconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRLconst [j-16] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) - // result: (MOVLstore [i] {s} p0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRLconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w0, mem) - return true - } - // match: (MOVWstore [i] {s} p1 (SHRQconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRQconst [j-16] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) - // result: (MOVLstore [i] {s} p0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRQconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w0, mem) - return true - } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) @@ -14716,58 +13464,6 @@ v.AddArg2(ptr, mem) return true } - // match: (MOVWstoreconst [c] {s} p1 x:(MOVWstoreconst [a] {s} p0 mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) - // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) - for { - c := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - x := v_1 - if x.Op != OpAMD64MOVWstoreconst { - break - } - a := auxIntToValAndOff(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - p0 := x.Args[0] - if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) - v.Aux = symToAux(s) - v.AddArg2(p0, mem) - return true - } - // match: (MOVWstoreconst [a] {s} p0 x:(MOVWstoreconst [c] {s} p1 mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) - // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) - for { - a := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - p0 := v_0 - x := v_1 - if x.Op != OpAMD64MOVWstoreconst { - break - } - c := auxIntToValAndOff(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - p1 := x.Args[0] - if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) - v.Aux = symToAux(s) - v.AddArg2(p0, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64MULL(v *Value) bool { @@ -16017,8 +14713,6 @@ func rewriteValueAMD64_OpAMD64ORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { @@ -16084,584 +14778,6 @@ v.copyOf(x) return true } - // match: (ORL x0:(MOVBload [i0] {s} p mem) sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i0) - v0.Aux = symToAux(s) - v0.AddArg2(p, mem) - return true - } - break - } - // match: (ORL x0:(MOVBload [i] {s} p0 mem) sh:(SHLLconst [8] x1:(MOVBload [i] {s} p1 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i) - v0.Aux = symToAux(s) - v0.AddArg2(p0, mem) - return true - } - break - } - // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVWload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i0) - v0.Aux = symToAux(s) - v0.AddArg2(p, mem) - return true - } - break - } - // match: (ORL x0:(MOVWload [i] {s} p0 mem) sh:(SHLLconst [16] x1:(MOVWload [i] {s} p1 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVWload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i) - v0.Aux = symToAux(s) - v0.AddArg2(p0, mem) - return true - } - break - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s1 := v_0 - if s1.Op != OpAMD64SHLLconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - or := v_1 - if or.Op != OpAMD64ORL { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s0 := or_0 - if s0.Op != OpAMD64SHLLconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - continue - } - y := or_1 - if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = int8ToAuxInt(j0) - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = int32ToAuxInt(i0) - v2.Aux = symToAux(s) - v2.AddArg2(p, mem) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) - // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i] {s} p0 mem)) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s1 := v_0 - if s1.Op != OpAMD64SHLLconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - or := v_1 - if or.Op != OpAMD64ORL { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s0 := or_0 - if s0.Op != OpAMD64SHLLconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] { - continue - } - y := or_1 - if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = int8ToAuxInt(j0) - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = int32ToAuxInt(i) - v2.Aux = symToAux(s) - v2.AddArg2(p0, mem) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x1 := v_0 - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) - v.copyOf(v0) - v0.AuxInt = int8ToAuxInt(8) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = int32ToAuxInt(i0) - v1.Aux = symToAux(s) - v1.AddArg2(p, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORL x1:(MOVBload [i] {s} p1 mem) sh:(SHLLconst [8] x0:(MOVBload [i] {s} p0 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x1 := v_0 - if x1.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) - v.copyOf(v0) - v0.AuxInt = int8ToAuxInt(8) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = int32ToAuxInt(i) - v1.Aux = symToAux(s) - v1.AddArg2(p0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - r1 := v_0 - if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = int32ToAuxInt(i0) - v1.Aux = symToAux(s) - v1.AddArg2(p, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - r1 := v_0 - if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = int32ToAuxInt(i) - v1.Aux = symToAux(s) - v1.AddArg2(p0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s0 := v_0 - if s0.Op != OpAMD64SHLLconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - or := v_1 - if or.Op != OpAMD64ORL { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s1 := or_0 - if s1.Op != OpAMD64SHLLconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y := or_1 - if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = int8ToAuxInt(j1) - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = int8ToAuxInt(8) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = int32ToAuxInt(i0) - v3.Aux = symToAux(s) - v3.AddArg2(p, mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) - // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s0 := v_0 - if s0.Op != OpAMD64SHLLconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - or := v_1 - if or.Op != OpAMD64ORL { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s1 := or_0 - if s1.Op != OpAMD64SHLLconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] { - continue - } - y := or_1 - if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = int8ToAuxInt(j1) - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = int8ToAuxInt(8) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = int32ToAuxInt(i) - v3.Aux = symToAux(s) - v3.AddArg2(p0, mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) @@ -16946,8 +15062,6 @@ func rewriteValueAMD64_OpAMD64ORQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types // match: (ORQ (SHLQ (MOVQconst [1]) y) x) // result: (BTSQ x y) for { @@ -17147,1020 +15261,6 @@ v.copyOf(x) return true } - // match: (ORQ x0:(MOVBload [i0] {s} p mem) sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i0) - v0.Aux = symToAux(s) - v0.AddArg2(p, mem) - return true - } - break - } - // match: (ORQ x0:(MOVBload [i] {s} p0 mem) sh:(SHLQconst [8] x1:(MOVBload [i] {s} p1 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i) - v0.Aux = symToAux(s) - v0.AddArg2(p0, mem) - return true - } - break - } - // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVWload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i0) - v0.Aux = symToAux(s) - v0.AddArg2(p, mem) - return true - } - break - } - // match: (ORQ x0:(MOVWload [i] {s} p0 mem) sh:(SHLQconst [16] x1:(MOVWload [i] {s} p1 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVWload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i) - v0.Aux = symToAux(s) - v0.AddArg2(p0, mem) - return true - } - break - } - // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVLload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i0) - v0.Aux = symToAux(s) - v0.AddArg2(p, mem) - return true - } - break - } - // match: (ORQ x0:(MOVLload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVLload [i] {s} p1 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVQload [i] {s} p0 mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVLload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i) - v0.Aux = symToAux(s) - v0.AddArg2(p0, mem) - return true - } - break - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s1 := v_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s0 := or_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - continue - } - y := or_1 - if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j0) - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = int32ToAuxInt(i0) - v2.Aux = symToAux(s) - v2.AddArg2(p, mem) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) - // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i] {s} p0 mem)) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s1 := v_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s0 := or_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] { - continue - } - y := or_1 - if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j0) - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = int32ToAuxInt(i) - v2.Aux = symToAux(s) - v2.AddArg2(p0, mem) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s1 := v_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s0 := or_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - continue - } - y := or_1 - if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j0) - v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AuxInt = int32ToAuxInt(i0) - v2.Aux = symToAux(s) - v2.AddArg2(p, mem) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i] {s} p0 mem)) y)) - // cond: j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i] {s} p0 mem)) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s1 := v_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s0 := or_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] { - continue - } - y := or_1 - if !(j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j0) - v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AuxInt = int32ToAuxInt(i) - v2.Aux = symToAux(s) - v2.AddArg2(p0, mem) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x1 := v_0 - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) - v.copyOf(v0) - v0.AuxInt = int8ToAuxInt(8) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = int32ToAuxInt(i0) - v1.Aux = symToAux(s) - v1.AddArg2(p, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORQ x1:(MOVBload [i] {s} p1 mem) sh:(SHLQconst [8] x0:(MOVBload [i] {s} p0 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x1 := v_0 - if x1.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) - v.copyOf(v0) - v0.AuxInt = int8ToAuxInt(8) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = int32ToAuxInt(i) - v1.Aux = symToAux(s) - v1.AddArg2(p0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - r1 := v_0 - if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = int32ToAuxInt(i0) - v1.Aux = symToAux(s) - v1.AddArg2(p, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - r1 := v_0 - if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = int32ToAuxInt(i) - v1.Aux = symToAux(s) - v1.AddArg2(p0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - r1 := v_0 - if r1.Op != OpAMD64BSWAPL { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { - continue - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) - v1.AuxInt = int32ToAuxInt(i0) - v1.Aux = symToAux(s) - v1.AddArg2(p, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORQ r1:(BSWAPL x1:(MOVLload [i] {s} p1 mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i] {s} p0 mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i] {s} p0 mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - r1 := v_0 - if r1.Op != OpAMD64BSWAPL { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { - continue - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) - v1.AuxInt = int32ToAuxInt(i) - v1.Aux = symToAux(s) - v1.AddArg2(p0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s0 := v_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s1 := or_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y := or_1 - if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j1) - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = int8ToAuxInt(8) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = int32ToAuxInt(i0) - v3.Aux = symToAux(s) - v3.AddArg2(p, mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) - // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s0 := v_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s1 := or_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] { - continue - } - y := or_1 - if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j1) - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = int8ToAuxInt(8) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = int32ToAuxInt(i) - v3.Aux = symToAux(s) - v3.AddArg2(p0, mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s0 := v_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s1 := or_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y := or_1 - if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j1) - v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v3.AuxInt = int32ToAuxInt(i0) - v3.Aux = symToAux(s) - v3.AddArg2(p, mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem))) y)) - // cond: j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i] {s} p0 mem))) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s0 := v_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s1 := or_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] { - continue - } - y := or_1 - if !(j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j1) - v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v3.AuxInt = int32ToAuxInt(i) - v3.Aux = symToAux(s) - v3.AddArg2(p0, mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) @@ -18186,81 +15286,6 @@ } break } - // match: (ORQ x0:(MOVBELload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVBELload [i1] {s} p mem))) - // cond: i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVBEQload [i1] {s} p mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVBELload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBELload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i1) - v0.Aux = symToAux(s) - v0.AddArg2(p, mem) - return true - } - break - } - // match: (ORQ x0:(MOVBELload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVBELload [i] {s} p1 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVBEQload [i] {s} p1 mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVBELload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBELload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i) - v0.Aux = symToAux(s) - v0.AddArg2(p1, mem) - return true - } - break - } return false } func rewriteValueAMD64_OpAMD64ORQconst(v *Value) bool { @@ -27793,6 +24818,18 @@ return true } return false +} +func rewriteValueAMD64_OpBswap16(v *Value) bool { + v_0 := v.Args[0] + // match: (Bswap16 x) + // result: (ROLWconst [8] x) + for { + x := v_0 + v.reset(OpAMD64ROLWconst) + v.AuxInt = int8ToAuxInt(8) + v.AddArg(x) + return true + } } func rewriteValueAMD64_OpCeil(v *Value) bool { v_0 := v.Args[0] -- diff -- # indent-heuristic: true @@ -620,6 +620,8 @@ return rewriteValueAMD64_OpBitLen64(v) case OpBitLen8: return rewriteValueAMD64_OpBitLen8(v) + case OpBswap16: + return rewriteValueAMD64_OpBswap16(v) case OpBswap32: v.Op = OpAMD64BSWAPL return true @@ -10482,823 +10484,6 @@ v.AddArg3(base, val, mem) return true } - // match: (MOVBstore [i] {s} p w x0:(MOVBstore [i-1] {s} p (SHRWconst [8] w) mem)) - // cond: x0.Uses == 1 && clobber(x0) - // result: (MOVWstore [i-1] {s} p (ROLWconst [8] w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { - break - } - mem := x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && clobber(x0)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) - v0.AuxInt = int8ToAuxInt(8) - v0.AddArg(w) - v.AddArg3(p, v0, mem) - return true - } - // match: (MOVBstore [i] {s} p1 w x0:(MOVBstore [i] {s} p0 (SHRWconst [8] w) mem)) - // cond: x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0) - // result: (MOVWstore [i] {s} p0 (ROLWconst [8] w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - break - } - mem := x0.Args[2] - p0 := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpAMD64SHRWconst || auxIntToInt8(x0_1.AuxInt) != 8 || w != x0_1.Args[0] || !(x0.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x0)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, typ.UInt16) - v0.AuxInt = int8ToAuxInt(8) - v0.AddArg(w) - v.AddArg3(p0, v0, mem) - return true - } - // match: (MOVBstore [i] {s} p w x2:(MOVBstore [i-1] {s} p (SHRLconst [8] w) x1:(MOVBstore [i-2] {s} p (SHRLconst [16] w) x0:(MOVBstore [i-3] {s} p (SHRLconst [24] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) - // result: (MOVLstore [i-3] {s} p (BSWAPL w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x2 := v_2 - if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-1 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - if p != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { - break - } - x1 := x2.Args[2] - if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { - break - } - x0 := x1.Args[2] - if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-3 || auxToSym(x0.Aux) != s { - break - } - mem := x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i - 3) - v.Aux = symToAux(s) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) - v0.AddArg(w) - v.AddArg3(p, v0, mem) - return true - } - // match: (MOVBstore [i] {s} p3 w x2:(MOVBstore [i] {s} p2 (SHRLconst [8] w) x1:(MOVBstore [i] {s} p1 (SHRLconst [16] w) x0:(MOVBstore [i] {s} p0 (SHRLconst [24] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2) - // result: (MOVLstore [i] {s} p0 (BSWAPL w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p3 := v_0 - w := v_1 - x2 := v_2 - if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - p2 := x2.Args[0] - x2_1 := x2.Args[1] - if x2_1.Op != OpAMD64SHRLconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { - break - } - x1 := x2.Args[2] - if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - p1 := x1.Args[0] - x1_1 := x1.Args[1] - if x1_1.Op != OpAMD64SHRLconst || auxIntToInt8(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { - break - } - x0 := x1.Args[2] - if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - break - } - mem := x0.Args[2] - p0 := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpAMD64SHRLconst || auxIntToInt8(x0_1.AuxInt) != 24 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && clobber(x0, x1, x2)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, typ.UInt32) - v0.AddArg(w) - v.AddArg3(p0, v0, mem) - return true - } - // match: (MOVBstore [i] {s} p w x6:(MOVBstore [i-1] {s} p (SHRQconst [8] w) x5:(MOVBstore [i-2] {s} p (SHRQconst [16] w) x4:(MOVBstore [i-3] {s} p (SHRQconst [24] w) x3:(MOVBstore [i-4] {s} p (SHRQconst [32] w) x2:(MOVBstore [i-5] {s} p (SHRQconst [40] w) x1:(MOVBstore [i-6] {s} p (SHRQconst [48] w) x0:(MOVBstore [i-7] {s} p (SHRQconst [56] w) mem)))))))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6) - // result: (MOVQstore [i-7] {s} p (BSWAPQ w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x6 := v_2 - if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i-1 || auxToSym(x6.Aux) != s { - break - } - _ = x6.Args[2] - if p != x6.Args[0] { - break - } - x6_1 := x6.Args[1] - if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { - break - } - x5 := x6.Args[2] - if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i-2 || auxToSym(x5.Aux) != s { - break - } - _ = x5.Args[2] - if p != x5.Args[0] { - break - } - x5_1 := x5.Args[1] - if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { - break - } - x4 := x5.Args[2] - if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i-3 || auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[2] - if p != x4.Args[0] { - break - } - x4_1 := x4.Args[1] - if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { - break - } - x3 := x4.Args[2] - if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i-4 || auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[2] - if p != x3.Args[0] { - break - } - x3_1 := x3.Args[1] - if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { - break - } - x2 := x3.Args[2] - if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i-5 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - if p != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { - break - } - x1 := x2.Args[2] - if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i-6 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { - break - } - x0 := x1.Args[2] - if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i-7 || auxToSym(x0.Aux) != s { - break - } - mem := x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(i - 7) - v.Aux = symToAux(s) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, typ.UInt64) - v0.AddArg(w) - v.AddArg3(p, v0, mem) - return true - } - // match: (MOVBstore [i] {s} p7 w x6:(MOVBstore [i] {s} p6 (SHRQconst [8] w) x5:(MOVBstore [i] {s} p5 (SHRQconst [16] w) x4:(MOVBstore [i] {s} p4 (SHRQconst [24] w) x3:(MOVBstore [i] {s} p3 (SHRQconst [32] w) x2:(MOVBstore [i] {s} p2 (SHRQconst [40] w) x1:(MOVBstore [i] {s} p1 (SHRQconst [48] w) x0:(MOVBstore [i] {s} p0 (SHRQconst [56] w) mem)))))))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6) - // result: (MOVQstore [i] {s} p0 (BSWAPQ w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p7 := v_0 - w := v_1 - x6 := v_2 - if x6.Op != OpAMD64MOVBstore || auxIntToInt32(x6.AuxInt) != i || auxToSym(x6.Aux) != s { - break - } - _ = x6.Args[2] - p6 := x6.Args[0] - x6_1 := x6.Args[1] - if x6_1.Op != OpAMD64SHRQconst || auxIntToInt8(x6_1.AuxInt) != 8 || w != x6_1.Args[0] { - break - } - x5 := x6.Args[2] - if x5.Op != OpAMD64MOVBstore || auxIntToInt32(x5.AuxInt) != i || auxToSym(x5.Aux) != s { - break - } - _ = x5.Args[2] - p5 := x5.Args[0] - x5_1 := x5.Args[1] - if x5_1.Op != OpAMD64SHRQconst || auxIntToInt8(x5_1.AuxInt) != 16 || w != x5_1.Args[0] { - break - } - x4 := x5.Args[2] - if x4.Op != OpAMD64MOVBstore || auxIntToInt32(x4.AuxInt) != i || auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[2] - p4 := x4.Args[0] - x4_1 := x4.Args[1] - if x4_1.Op != OpAMD64SHRQconst || auxIntToInt8(x4_1.AuxInt) != 24 || w != x4_1.Args[0] { - break - } - x3 := x4.Args[2] - if x3.Op != OpAMD64MOVBstore || auxIntToInt32(x3.AuxInt) != i || auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[2] - p3 := x3.Args[0] - x3_1 := x3.Args[1] - if x3_1.Op != OpAMD64SHRQconst || auxIntToInt8(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { - break - } - x2 := x3.Args[2] - if x2.Op != OpAMD64MOVBstore || auxIntToInt32(x2.AuxInt) != i || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - p2 := x2.Args[0] - x2_1 := x2.Args[1] - if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 40 || w != x2_1.Args[0] { - break - } - x1 := x2.Args[2] - if x1.Op != OpAMD64MOVBstore || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - p1 := x1.Args[0] - x1_1 := x1.Args[1] - if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 48 || w != x1_1.Args[0] { - break - } - x0 := x1.Args[2] - if x0.Op != OpAMD64MOVBstore || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - break - } - mem := x0.Args[2] - p0 := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpAMD64SHRQconst || auxIntToInt8(x0_1.AuxInt) != 56 || w != x0_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && sequentialAddresses(p0, p1, 1) && sequentialAddresses(p1, p2, 1) && sequentialAddresses(p2, p3, 1) && sequentialAddresses(p3, p4, 1) && sequentialAddresses(p4, p5, 1) && sequentialAddresses(p5, p6, 1) && sequentialAddresses(p6, p7, 1) && clobber(x0, x1, x2, x3, x4, x5, x6)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, typ.UInt64) - v0.AddArg(w) - v.AddArg3(p0, v0, mem) - return true - } - // match: (MOVBstore [i] {s} p (SHRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i-1] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVBstore [i] {s} p (SHRLconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i-1] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVBstore [i] {s} p (SHRQconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i-1] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRWconst [8] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRLconst [8] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVBstore [i] {s} p w x:(MOVBstore [i+1] {s} p (SHRQconst [8] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i+1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVBstore [i] {s} p (SHRLconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRLconst [j-8] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i-1] {s} p w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRLconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - w0 := x.Args[1] - if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(p, w0, mem) - return true - } - // match: (MOVBstore [i] {s} p (SHRQconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SHRQconst [j-8] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstore [i-1] {s} p w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRQconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - w0 := x.Args[1] - if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(p, w0, mem) - return true - } - // match: (MOVBstore [i] {s} p1 (SHRWconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRWconst || auxIntToInt8(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVBstore [i] {s} p1 (SHRLconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVBstore [i] {s} p1 (SHRQconst [8] w) x:(MOVBstore [i] {s} p0 w mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRWconst [8] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p0 := v_0 - w := v_1 - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p1 := x.Args[0] - x_1 := x.Args[1] - if x_1.Op != OpAMD64SHRWconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRLconst [8] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p0 := v_0 - w := v_1 - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p1 := x.Args[0] - x_1 := x.Args[1] - if x_1.Op != OpAMD64SHRLconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVBstore [i] {s} p0 w x:(MOVBstore [i] {s} p1 (SHRQconst [8] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p0 := v_0 - w := v_1 - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p1 := x.Args[0] - x_1 := x.Args[1] - if x_1.Op != OpAMD64SHRQconst || auxIntToInt8(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVBstore [i] {s} p1 (SHRLconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRLconst [j-8] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRLconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w0, mem) - return true - } - // match: (MOVBstore [i] {s} p1 (SHRQconst [j] w) x:(MOVBstore [i] {s} p0 w0:(SHRQconst [j-8] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x) - // result: (MOVWstore [i] {s} p0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRQconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVBstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 1) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w0, mem) - return true - } - // match: (MOVBstore [c3] {s} p3 (SHRQconst [56] w) x1:(MOVWstore [c2] {s} p2 (SHRQconst [40] w) x2:(MOVLstore [c1] {s} p1 (SHRQconst [8] w) x3:(MOVBstore [c0] {s} p0 w mem)))) - // cond: x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1 + c0 - c1)) && sequentialAddresses(p0, p2, int64(5 + c0 - c2)) && sequentialAddresses(p0, p3, int64(7 + c0 - c3)) && clobber(x1, x2, x3) - // result: (MOVQstore [c0] {s} p0 w mem) - for { - c3 := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p3 := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 56 { - break - } - w := v_1.Args[0] - x1 := v_2 - if x1.Op != OpAMD64MOVWstore { - break - } - c2 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - p2 := x1.Args[0] - x1_1 := x1.Args[1] - if x1_1.Op != OpAMD64SHRQconst || auxIntToInt8(x1_1.AuxInt) != 40 || w != x1_1.Args[0] { - break - } - x2 := x1.Args[2] - if x2.Op != OpAMD64MOVLstore { - break - } - c1 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - p1 := x2.Args[0] - x2_1 := x2.Args[1] - if x2_1.Op != OpAMD64SHRQconst || auxIntToInt8(x2_1.AuxInt) != 8 || w != x2_1.Args[0] { - break - } - x3 := x2.Args[2] - if x3.Op != OpAMD64MOVBstore { - break - } - c0 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - break - } - mem := x3.Args[2] - p0 := x3.Args[0] - if w != x3.Args[1] || !(x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && sequentialAddresses(p0, p1, int64(1+c0-c1)) && sequentialAddresses(p0, p2, int64(5+c0-c2)) && sequentialAddresses(p0, p3, int64(7+c0-c3)) && clobber(x1, x2, x3)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(c0) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } // match: (MOVBstore [i] {s} p x1:(MOVBload [j] {s2} p2 mem) mem2:(MOVBstore [i-1] {s} p x2:(MOVBload [j-1] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVWstore [i-1] {s} p (MOVWload [j-1] {s2} p2 mem) mem) @@ -11388,58 +10573,6 @@ v.AddArg2(ptr, mem) return true } - // match: (MOVBstoreconst [c] {s} p1 x:(MOVBstoreconst [a] {s} p0 mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) - // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) - for { - c := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - x := v_1 - if x.Op != OpAMD64MOVBstoreconst { - break - } - a := auxIntToValAndOff(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - p0 := x.Args[0] - if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) - v.Aux = symToAux(s) - v.AddArg2(p0, mem) - return true - } - // match: (MOVBstoreconst [a] {s} p0 x:(MOVBstoreconst [c] {s} p1 mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x) - // result: (MOVWstoreconst [makeValAndOff(a.Val()&0xff | c.Val()<<8, a.Off())] {s} p0 mem) - for { - a := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - p0 := v_0 - x := v_1 - if x.Op != OpAMD64MOVBstoreconst { - break - } - c := auxIntToValAndOff(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - p1 := x.Args[0] - if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+1-c.Off())) && clobber(x)) { - break - } - v.reset(OpAMD64MOVWstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xff|c.Val()<<8, a.Off())) - v.Aux = symToAux(s) - v.AddArg2(p0, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64MOVLQSX(v *Value) bool { @@ -12019,115 +11152,6 @@ v.AddArg3(base, val, mem) return true } - // match: (MOVLstore [i] {s} p (SHRQconst [32] w) x:(MOVLstore [i-4] {s} p w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVQstore [i-4] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(i - 4) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVLstore [i] {s} p (SHRQconst [j] w) x:(MOVLstore [i-4] {s} p w0:(SHRQconst [j-32] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVQstore [i-4] {s} p w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRQconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - w0 := x.Args[1] - if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(i - 4) - v.Aux = symToAux(s) - v.AddArg3(p, w0, mem) - return true - } - // match: (MOVLstore [i] {s} p1 (SHRQconst [32] w) x:(MOVLstore [i] {s} p0 w mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) - // result: (MOVQstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 32 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVLstore [i] {s} p1 (SHRQconst [j] w) x:(MOVLstore [i] {s} p0 w0:(SHRQconst [j-32] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x) - // result: (MOVQstore [i] {s} p0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRQconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVLstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 4) && clobber(x)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w0, mem) - return true - } // match: (MOVLstore [i] {s} p x1:(MOVLload [j] {s2} p2 mem) mem2:(MOVLstore [i-4] {s} p x2:(MOVLload [j-4] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVQstore [i-4] {s} p (MOVQload [j-4] {s2} p2 mem) mem) @@ -12575,8 +11599,6 @@ func rewriteValueAMD64_OpAMD64MOVLstoreconst(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types // match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem) // cond: ValAndOff(sc).canAdd32(off) // result: (MOVLstoreconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem) @@ -12620,62 +11642,6 @@ v.AddArg2(ptr, mem) return true } - // match: (MOVLstoreconst [c] {s} p1 x:(MOVLstoreconst [a] {s} p0 mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) - // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) - for { - c := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - x := v_1 - if x.Op != OpAMD64MOVLstoreconst { - break - } - a := auxIntToValAndOff(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - p0 := x.Args[0] - if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(a.Off()) - v.Aux = symToAux(s) - v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) - v.AddArg3(p0, v0, mem) - return true - } - // match: (MOVLstoreconst [a] {s} p0 x:(MOVLstoreconst [c] {s} p1 mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x) - // result: (MOVQstore [a.Off()] {s} p0 (MOVQconst [a.Val64()&0xffffffff | c.Val64()<<32]) mem) - for { - a := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - p0 := v_0 - x := v_1 - if x.Op != OpAMD64MOVLstoreconst { - break - } - c := auxIntToValAndOff(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - p1 := x.Args[0] - if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+4-c.Off())) && clobber(x)) { - break - } - v.reset(OpAMD64MOVQstore) - v.AuxInt = int32ToAuxInt(a.Off()) - v.Aux = symToAux(s) - v0 := b.NewValue0(x.Pos, OpAMD64MOVQconst, typ.UInt64) - v0.AuxInt = int64ToAuxInt(a.Val64()&0xffffffff | c.Val64()<<32) - v.AddArg3(p0, v0, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64MOVOload(v *Value) bool { @@ -14387,224 +13353,6 @@ v.AddArg3(base, val, mem) return true } - // match: (MOVWstore [i] {s} p (SHRLconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVLstore [i-2] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVWstore [i] {s} p (SHRQconst [16] w) x:(MOVWstore [i-2] {s} p w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVLstore [i-2] {s} p w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] || w != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(p, w, mem) - return true - } - // match: (MOVWstore [i] {s} p (SHRLconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRLconst [j-16] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVLstore [i-2] {s} p w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRLconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - w0 := x.Args[1] - if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(p, w0, mem) - return true - } - // match: (MOVWstore [i] {s} p (SHRQconst [j] w) x:(MOVWstore [i-2] {s} p w0:(SHRQconst [j-16] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVLstore [i-2] {s} p w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p := v_0 - if v_1.Op != OpAMD64SHRQconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if p != x.Args[0] { - break - } - w0 := x.Args[1] - if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(p, w0, mem) - return true - } - // match: (MOVWstore [i] {s} p1 (SHRLconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) - // result: (MOVLstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRLconst || auxIntToInt8(v_1.AuxInt) != 16 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVWstore [i] {s} p1 (SHRQconst [16] w) x:(MOVWstore [i] {s} p0 w mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) - // result: (MOVLstore [i] {s} p0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRQconst || auxIntToInt8(v_1.AuxInt) != 16 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w, mem) - return true - } - // match: (MOVWstore [i] {s} p1 (SHRLconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRLconst [j-16] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) - // result: (MOVLstore [i] {s} p0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRLconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpAMD64SHRLconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w0, mem) - return true - } - // match: (MOVWstore [i] {s} p1 (SHRQconst [j] w) x:(MOVWstore [i] {s} p0 w0:(SHRQconst [j-16] w) mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x) - // result: (MOVLstore [i] {s} p0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - if v_1.Op != OpAMD64SHRQconst { - break - } - j := auxIntToInt8(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpAMD64MOVWstore || auxIntToInt32(x.AuxInt) != i || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - p0 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpAMD64SHRQconst || auxIntToInt8(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && sequentialAddresses(p0, p1, 2) && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstore) - v.AuxInt = int32ToAuxInt(i) - v.Aux = symToAux(s) - v.AddArg3(p0, w0, mem) - return true - } // match: (MOVWstore [i] {s} p x1:(MOVWload [j] {s2} p2 mem) mem2:(MOVWstore [i-2] {s} p x2:(MOVWload [j-2] {s2} p2 mem) mem)) // cond: x1.Uses == 1 && x2.Uses == 1 && mem2.Uses == 1 && clobber(x1, x2, mem2) // result: (MOVLstore [i-2] {s} p (MOVLload [j-2] {s2} p2 mem) mem) @@ -14716,58 +13464,6 @@ v.AddArg2(ptr, mem) return true } - // match: (MOVWstoreconst [c] {s} p1 x:(MOVWstoreconst [a] {s} p0 mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) - // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) - for { - c := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - p1 := v_0 - x := v_1 - if x.Op != OpAMD64MOVWstoreconst { - break - } - a := auxIntToValAndOff(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - p0 := x.Args[0] - if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) - v.Aux = symToAux(s) - v.AddArg2(p0, mem) - return true - } - // match: (MOVWstoreconst [a] {s} p0 x:(MOVWstoreconst [c] {s} p1 mem)) - // cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x) - // result: (MOVLstoreconst [makeValAndOff(a.Val()&0xffff | c.Val()<<16, a.Off())] {s} p0 mem) - for { - a := auxIntToValAndOff(v.AuxInt) - s := auxToSym(v.Aux) - p0 := v_0 - x := v_1 - if x.Op != OpAMD64MOVWstoreconst { - break - } - c := auxIntToValAndOff(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - p1 := x.Args[0] - if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+2-c.Off())) && clobber(x)) { - break - } - v.reset(OpAMD64MOVLstoreconst) - v.AuxInt = valAndOffToAuxInt(makeValAndOff(a.Val()&0xffff|c.Val()<<16, a.Off())) - v.Aux = symToAux(s) - v.AddArg2(p0, mem) - return true - } return false } func rewriteValueAMD64_OpAMD64MULL(v *Value) bool { @@ -16017,8 +14713,6 @@ func rewriteValueAMD64_OpAMD64ORL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types // match: (ORL (SHLL (MOVLconst [1]) y) x) // result: (BTSL x y) for { @@ -16084,584 +14778,6 @@ v.copyOf(x) return true } - // match: (ORL x0:(MOVBload [i0] {s} p mem) sh:(SHLLconst [8] x1:(MOVBload [i1] {s} p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i0) - v0.Aux = symToAux(s) - v0.AddArg2(p, mem) - return true - } - break - } - // match: (ORL x0:(MOVBload [i] {s} p0 mem) sh:(SHLLconst [8] x1:(MOVBload [i] {s} p1 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i) - v0.Aux = symToAux(s) - v0.AddArg2(p0, mem) - return true - } - break - } - // match: (ORL x0:(MOVWload [i0] {s} p mem) sh:(SHLLconst [16] x1:(MOVWload [i1] {s} p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVWload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i0) - v0.Aux = symToAux(s) - v0.AddArg2(p, mem) - return true - } - break - } - // match: (ORL x0:(MOVWload [i] {s} p0 mem) sh:(SHLLconst [16] x1:(MOVWload [i] {s} p1 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVWload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i) - v0.Aux = symToAux(s) - v0.AddArg2(p0, mem) - return true - } - break - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s1 := v_0 - if s1.Op != OpAMD64SHLLconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - or := v_1 - if or.Op != OpAMD64ORL { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s0 := or_0 - if s0.Op != OpAMD64SHLLconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - continue - } - y := or_1 - if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = int8ToAuxInt(j0) - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = int32ToAuxInt(i0) - v2.Aux = symToAux(s) - v2.AddArg2(p, mem) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) - // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j0] (MOVWload [i] {s} p0 mem)) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s1 := v_0 - if s1.Op != OpAMD64SHLLconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - or := v_1 - if or.Op != OpAMD64ORL { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s0 := or_0 - if s0.Op != OpAMD64SHLLconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] { - continue - } - y := or_1 - if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = int8ToAuxInt(j0) - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = int32ToAuxInt(i) - v2.Aux = symToAux(s) - v2.AddArg2(p0, mem) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORL x1:(MOVBload [i1] {s} p mem) sh:(SHLLconst [8] x0:(MOVBload [i0] {s} p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x1 := v_0 - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) - v.copyOf(v0) - v0.AuxInt = int8ToAuxInt(8) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = int32ToAuxInt(i0) - v1.Aux = symToAux(s) - v1.AddArg2(p, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORL x1:(MOVBload [i] {s} p1 mem) sh:(SHLLconst [8] x0:(MOVBload [i] {s} p0 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x1 := v_0 - if x1.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) - v.copyOf(v0) - v0.AuxInt = int8ToAuxInt(8) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = int32ToAuxInt(i) - v1.Aux = symToAux(s) - v1.AddArg2(p0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - r1 := v_0 - if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = int32ToAuxInt(i0) - v1.Aux = symToAux(s) - v1.AddArg2(p, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORL r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLLconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - r1 := v_0 - if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLLconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = int32ToAuxInt(i) - v1.Aux = symToAux(s) - v1.AddArg2(p0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s0 := v_0 - if s0.Op != OpAMD64SHLLconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - or := v_1 - if or.Op != OpAMD64ORL { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s1 := or_0 - if s1.Op != OpAMD64SHLLconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y := or_1 - if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = int8ToAuxInt(j1) - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = int8ToAuxInt(8) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = int32ToAuxInt(i0) - v3.Aux = symToAux(s) - v3.AddArg2(p, mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORL s0:(SHLLconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORL s1:(SHLLconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) - // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORL (SHLLconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s0 := v_0 - if s0.Op != OpAMD64SHLLconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - or := v_1 - if or.Op != OpAMD64ORL { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s1 := or_0 - if s1.Op != OpAMD64SHLLconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] { - continue - } - y := or_1 - if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLLconst, v.Type) - v1.AuxInt = int8ToAuxInt(j1) - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = int8ToAuxInt(8) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = int32ToAuxInt(i) - v3.Aux = symToAux(s) - v3.AddArg2(p0, mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } // match: (ORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORLload x [off] {sym} ptr mem) @@ -16946,8 +15062,6 @@ func rewriteValueAMD64_OpAMD64ORQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types // match: (ORQ (SHLQ (MOVQconst [1]) y) x) // result: (BTSQ x y) for { @@ -17147,1020 +15261,6 @@ v.copyOf(x) return true } - // match: (ORQ x0:(MOVBload [i0] {s} p mem) sh:(SHLQconst [8] x1:(MOVBload [i1] {s} p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVWload [i0] {s} p mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i0) - v0.Aux = symToAux(s) - v0.AddArg2(p, mem) - return true - } - break - } - // match: (ORQ x0:(MOVBload [i] {s} p0 mem) sh:(SHLQconst [8] x1:(MOVBload [i] {s} p1 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVWload [i] {s} p0 mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i) - v0.Aux = symToAux(s) - v0.AddArg2(p0, mem) - return true - } - break - } - // match: (ORQ x0:(MOVWload [i0] {s} p mem) sh:(SHLQconst [16] x1:(MOVWload [i1] {s} p mem))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVLload [i0] {s} p mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVWload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i0) - v0.Aux = symToAux(s) - v0.AddArg2(p, mem) - return true - } - break - } - // match: (ORQ x0:(MOVWload [i] {s} p0 mem) sh:(SHLQconst [16] x1:(MOVWload [i] {s} p1 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVLload [i] {s} p0 mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVWload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i) - v0.Aux = symToAux(s) - v0.AddArg2(p0, mem) - return true - } - break - } - // match: (ORQ x0:(MOVLload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVLload [i1] {s} p mem))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVQload [i0] {s} p mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVLload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i0) - v0.Aux = symToAux(s) - v0.AddArg2(p, mem) - return true - } - break - } - // match: (ORQ x0:(MOVLload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVLload [i] {s} p1 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVQload [i] {s} p0 mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVLload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVLload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVQload, typ.UInt64) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i) - v0.Aux = symToAux(s) - v0.AddArg2(p0, mem) - return true - } - break - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) y)) - // cond: i1 == i0+1 && j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i0] {s} p mem)) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s1 := v_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s0 := or_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - continue - } - y := or_1 - if !(i1 == i0+1 && j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j0) - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = int32ToAuxInt(i0) - v2.Aux = symToAux(s) - v2.AddArg2(p, mem) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) y)) - // cond: j1 == j0+8 && j0 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVWload [i] {s} p0 mem)) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s1 := v_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s0 := or_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] { - continue - } - y := or_1 - if !(j1 == j0+8 && j0%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j0) - v2 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v2.AuxInt = int32ToAuxInt(i) - v2.Aux = symToAux(s) - v2.AddArg2(p0, mem) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i1] {s} p mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i0] {s} p mem)) y)) - // cond: i1 == i0+2 && j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i0] {s} p mem)) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s1 := v_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s0 := or_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] { - continue - } - y := or_1 - if !(i1 == i0+2 && j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j0) - v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AuxInt = int32ToAuxInt(i0) - v2.Aux = symToAux(s) - v2.AddArg2(p, mem) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ s1:(SHLQconst [j1] x1:(MOVWload [i] {s} p1 mem)) or:(ORQ s0:(SHLQconst [j0] x0:(MOVWload [i] {s} p0 mem)) y)) - // cond: j1 == j0+16 && j0 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j0] (MOVLload [i] {s} p0 mem)) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s1 := v_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s0 := or_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] { - continue - } - y := or_1 - if !(j1 == j0+16 && j0%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x0.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j0) - v2 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v2.AuxInt = int32ToAuxInt(i) - v2.Aux = symToAux(s) - v2.AddArg2(p0, mem) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ x1:(MOVBload [i1] {s} p mem) sh:(SHLQconst [8] x0:(MOVBload [i0] {s} p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i0] {s} p mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x1 := v_0 - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) - v.copyOf(v0) - v0.AuxInt = int8ToAuxInt(8) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = int32ToAuxInt(i0) - v1.Aux = symToAux(s) - v1.AddArg2(p, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORQ x1:(MOVBload [i] {s} p1 mem) sh:(SHLQconst [8] x0:(MOVBload [i] {s} p0 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (ROLWconst [8] (MOVWload [i] {s} p0 mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x1 := v_0 - if x1.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 8 { - continue - } - x0 := sh.Args[0] - if x0.Op != OpAMD64MOVBload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64ROLWconst, v.Type) - v.copyOf(v0) - v0.AuxInt = int8ToAuxInt(8) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVWload, typ.UInt16) - v1.AuxInt = int32ToAuxInt(i) - v1.Aux = symToAux(s) - v1.AddArg2(p0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem)))) - // cond: i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i0] {s} p mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - r1 := v_0 - if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = int32ToAuxInt(i0) - v1.Aux = symToAux(s) - v1.AddArg2(p, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORQ r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem)) sh:(SHLQconst [16] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) - // result: @mergePoint(b,x0,x1) (BSWAPL (MOVLload [i] {s} p0 mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - r1 := v_0 - if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 16 { - continue - } - r0 := sh.Args[0] - if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPL, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVLload, typ.UInt32) - v1.AuxInt = int32ToAuxInt(i) - v1.Aux = symToAux(s) - v1.AddArg2(p0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORQ r1:(BSWAPL x1:(MOVLload [i1] {s} p mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i0] {s} p mem)))) - // cond: i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i0] {s} p mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - r1 := v_0 - if r1.Op != OpAMD64BSWAPL { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { - continue - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - if auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - if p != x0.Args[0] || mem != x0.Args[1] || !(i1 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) - v1.AuxInt = int32ToAuxInt(i0) - v1.Aux = symToAux(s) - v1.AddArg2(p, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORQ r1:(BSWAPL x1:(MOVLload [i] {s} p1 mem)) sh:(SHLQconst [32] r0:(BSWAPL x0:(MOVLload [i] {s} p0 mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, r0, r1, sh) - // result: @mergePoint(b,x0,x1) (BSWAPQ (MOVQload [i] {s} p0 mem)) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - r1 := v_0 - if r1.Op != OpAMD64BSWAPL { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVLload { - continue - } - i := auxIntToInt32(x1.AuxInt) - s := auxToSym(x1.Aux) - mem := x1.Args[1] - p1 := x1.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { - continue - } - r0 := sh.Args[0] - if r0.Op != OpAMD64BSWAPL { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVLload || auxIntToInt32(x0.AuxInt) != i || auxToSym(x0.Aux) != s { - continue - } - _ = x0.Args[1] - p0 := x0.Args[0] - if mem != x0.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p0, p1, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, r0, r1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpAMD64BSWAPQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpAMD64MOVQload, typ.UInt64) - v1.AuxInt = int32ToAuxInt(i) - v1.Aux = symToAux(s) - v1.AddArg2(p0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i0] {s} p mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i1] {s} p mem)) y)) - // cond: i1 == i0+1 && j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i0] {s} p mem))) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s0 := v_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s1 := or_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y := or_1 - if !(i1 == i0+1 && j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j1) - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = int8ToAuxInt(8) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = int32ToAuxInt(i0) - v3.Aux = symToAux(s) - v3.AddArg2(p, mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ s0:(SHLQconst [j0] x0:(MOVBload [i] {s} p0 mem)) or:(ORQ s1:(SHLQconst [j1] x1:(MOVBload [i] {s} p1 mem)) y)) - // cond: j1 == j0-8 && j1 % 16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (ROLWconst [8] (MOVWload [i] {s} p0 mem))) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s0 := v_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - x0 := s0.Args[0] - if x0.Op != OpAMD64MOVBload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s1 := or_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - x1 := s1.Args[0] - if x1.Op != OpAMD64MOVBload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] { - continue - } - y := or_1 - if !(j1 == j0-8 && j1%16 == 0 && x0.Uses == 1 && x1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 1) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j1) - v2 := b.NewValue0(x1.Pos, OpAMD64ROLWconst, typ.UInt16) - v2.AuxInt = int8ToAuxInt(8) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVWload, typ.UInt16) - v3.AuxInt = int32ToAuxInt(i) - v3.Aux = symToAux(s) - v3.AddArg2(p0, mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i0] {s} p mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i1] {s} p mem))) y)) - // cond: i1 == i0+2 && j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i0] {s} p mem))) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s0 := v_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s1 := or_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y := or_1 - if !(i1 == i0+2 && j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j1) - v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v3.AuxInt = int32ToAuxInt(i0) - v3.Aux = symToAux(s) - v3.AddArg2(p, mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } - // match: (ORQ s0:(SHLQconst [j0] r0:(ROLWconst [8] x0:(MOVWload [i] {s} p0 mem))) or:(ORQ s1:(SHLQconst [j1] r1:(ROLWconst [8] x1:(MOVWload [i] {s} p1 mem))) y)) - // cond: j1 == j0-16 && j1 % 32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b,x0,x1,y) != nil && clobber(x0, x1, r0, r1, s0, s1, or) - // result: @mergePoint(b,x0,x1,y) (ORQ (SHLQconst [j1] (BSWAPL (MOVLload [i] {s} p0 mem))) y) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - s0 := v_0 - if s0.Op != OpAMD64SHLQconst { - continue - } - j0 := auxIntToInt8(s0.AuxInt) - r0 := s0.Args[0] - if r0.Op != OpAMD64ROLWconst || auxIntToInt8(r0.AuxInt) != 8 { - continue - } - x0 := r0.Args[0] - if x0.Op != OpAMD64MOVWload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - or := v_1 - if or.Op != OpAMD64ORQ { - continue - } - _ = or.Args[1] - or_0 := or.Args[0] - or_1 := or.Args[1] - for _i1 := 0; _i1 <= 1; _i1, or_0, or_1 = _i1+1, or_1, or_0 { - s1 := or_0 - if s1.Op != OpAMD64SHLQconst { - continue - } - j1 := auxIntToInt8(s1.AuxInt) - r1 := s1.Args[0] - if r1.Op != OpAMD64ROLWconst || auxIntToInt8(r1.AuxInt) != 8 { - continue - } - x1 := r1.Args[0] - if x1.Op != OpAMD64MOVWload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] { - continue - } - y := or_1 - if !(j1 == j0-16 && j1%32 == 0 && x0.Uses == 1 && x1.Uses == 1 && r0.Uses == 1 && r1.Uses == 1 && s0.Uses == 1 && s1.Uses == 1 && or.Uses == 1 && sequentialAddresses(p0, p1, 2) && mergePoint(b, x0, x1, y) != nil && clobber(x0, x1, r0, r1, s0, s1, or)) { - continue - } - b = mergePoint(b, x0, x1, y) - v0 := b.NewValue0(x1.Pos, OpAMD64ORQ, v.Type) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpAMD64SHLQconst, v.Type) - v1.AuxInt = int8ToAuxInt(j1) - v2 := b.NewValue0(x1.Pos, OpAMD64BSWAPL, typ.UInt32) - v3 := b.NewValue0(x1.Pos, OpAMD64MOVLload, typ.UInt32) - v3.AuxInt = int32ToAuxInt(i) - v3.Aux = symToAux(s) - v3.AddArg2(p0, mem) - v2.AddArg(v3) - v1.AddArg(v2) - v0.AddArg2(v1, y) - return true - } - } - break - } // match: (ORQ x l:(MOVQload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l) // result: (ORQload x [off] {sym} ptr mem) @@ -18186,81 +15286,6 @@ } break } - // match: (ORQ x0:(MOVBELload [i0] {s} p mem) sh:(SHLQconst [32] x1:(MOVBELload [i1] {s} p mem))) - // cond: i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVBEQload [i1] {s} p mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVBELload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBELload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i0 == i1+4 && x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i1) - v0.Aux = symToAux(s) - v0.AddArg2(p, mem) - return true - } - break - } - // match: (ORQ x0:(MOVBELload [i] {s} p0 mem) sh:(SHLQconst [32] x1:(MOVBELload [i] {s} p1 mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b,x0,x1) != nil && clobber(x0, x1, sh) - // result: @mergePoint(b,x0,x1) (MOVBEQload [i] {s} p1 mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x0 := v_0 - if x0.Op != OpAMD64MOVBELload { - continue - } - i := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p0 := x0.Args[0] - sh := v_1 - if sh.Op != OpAMD64SHLQconst || auxIntToInt8(sh.AuxInt) != 32 { - continue - } - x1 := sh.Args[0] - if x1.Op != OpAMD64MOVBELload || auxIntToInt32(x1.AuxInt) != i || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - p1 := x1.Args[0] - if mem != x1.Args[1] || !(x0.Uses == 1 && x1.Uses == 1 && sh.Uses == 1 && sequentialAddresses(p1, p0, 4) && mergePoint(b, x0, x1) != nil && clobber(x0, x1, sh)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpAMD64MOVBEQload, typ.UInt64) - v.copyOf(v0) - v0.AuxInt = int32ToAuxInt(i) - v0.Aux = symToAux(s) - v0.AddArg2(p1, mem) - return true - } - break - } return false } func rewriteValueAMD64_OpAMD64ORQconst(v *Value) bool { @@ -27794,6 +24819,18 @@ } return false } +func rewriteValueAMD64_OpBswap16(v *Value) bool { + v_0 := v.Args[0] + // match: (Bswap16 x) + // result: (ROLWconst [8] x) + for { + x := v_0 + v.reset(OpAMD64ROLWconst) + v.AuxInt = int8ToAuxInt(8) + v.AddArg(x) + return true + } +} func rewriteValueAMD64_OpCeil(v *Value) bool { v_0 := v.Args[0] // match: (Ceil x) go_cedf5008a84d3726f98fac551a4016bf0a91157f_src_cmd_compile_internal_ssa_rewriteARM64.go.test000066400000000000000000066711471516001707200356650ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit cedf5008a84d3726f98fac551a4016bf0a91157f file src/cmd/compile/internal/ssa/rewriteARM64.go -- x -- // Code generated from _gen/ARM64.rules using 'go generate'; DO NOT EDIT. package ssa import "cmd/compile/internal/types" func rewriteValueARM64(v *Value) bool { switch v.Op { case OpARM64ADCSflags: return rewriteValueARM64_OpARM64ADCSflags(v) case OpARM64ADD: return rewriteValueARM64_OpARM64ADD(v) case OpARM64ADDSflags: return rewriteValueARM64_OpARM64ADDSflags(v) case OpARM64ADDconst: return rewriteValueARM64_OpARM64ADDconst(v) case OpARM64ADDshiftLL: return rewriteValueARM64_OpARM64ADDshiftLL(v) case OpARM64ADDshiftRA: return rewriteValueARM64_OpARM64ADDshiftRA(v) case OpARM64ADDshiftRL: return rewriteValueARM64_OpARM64ADDshiftRL(v) case OpARM64AND: return rewriteValueARM64_OpARM64AND(v) case OpARM64ANDconst: return rewriteValueARM64_OpARM64ANDconst(v) case OpARM64ANDshiftLL: return rewriteValueARM64_OpARM64ANDshiftLL(v) case OpARM64ANDshiftRA: return rewriteValueARM64_OpARM64ANDshiftRA(v) case OpARM64ANDshiftRL: return rewriteValueARM64_OpARM64ANDshiftRL(v) case OpARM64ANDshiftRO: return rewriteValueARM64_OpARM64ANDshiftRO(v) case OpARM64BIC: return rewriteValueARM64_OpARM64BIC(v) case OpARM64BICshiftLL: return rewriteValueARM64_OpARM64BICshiftLL(v) case OpARM64BICshiftRA: return rewriteValueARM64_OpARM64BICshiftRA(v) case OpARM64BICshiftRL: return rewriteValueARM64_OpARM64BICshiftRL(v) case OpARM64BICshiftRO: return rewriteValueARM64_OpARM64BICshiftRO(v) case OpARM64CMN: return rewriteValueARM64_OpARM64CMN(v) case OpARM64CMNW: return rewriteValueARM64_OpARM64CMNW(v) case OpARM64CMNWconst: return rewriteValueARM64_OpARM64CMNWconst(v) case OpARM64CMNconst: return rewriteValueARM64_OpARM64CMNconst(v) case OpARM64CMNshiftLL: return rewriteValueARM64_OpARM64CMNshiftLL(v) case OpARM64CMNshiftRA: return rewriteValueARM64_OpARM64CMNshiftRA(v) case OpARM64CMNshiftRL: return rewriteValueARM64_OpARM64CMNshiftRL(v) case OpARM64CMP: return rewriteValueARM64_OpARM64CMP(v) case OpARM64CMPW: return rewriteValueARM64_OpARM64CMPW(v) case OpARM64CMPWconst: return rewriteValueARM64_OpARM64CMPWconst(v) case OpARM64CMPconst: return rewriteValueARM64_OpARM64CMPconst(v) case OpARM64CMPshiftLL: return rewriteValueARM64_OpARM64CMPshiftLL(v) case OpARM64CMPshiftRA: return rewriteValueARM64_OpARM64CMPshiftRA(v) case OpARM64CMPshiftRL: return rewriteValueARM64_OpARM64CMPshiftRL(v) case OpARM64CSEL: return rewriteValueARM64_OpARM64CSEL(v) case OpARM64CSEL0: return rewriteValueARM64_OpARM64CSEL0(v) case OpARM64CSETM: return rewriteValueARM64_OpARM64CSETM(v) case OpARM64CSINC: return rewriteValueARM64_OpARM64CSINC(v) case OpARM64CSINV: return rewriteValueARM64_OpARM64CSINV(v) case OpARM64CSNEG: return rewriteValueARM64_OpARM64CSNEG(v) case OpARM64DIV: return rewriteValueARM64_OpARM64DIV(v) case OpARM64DIVW: return rewriteValueARM64_OpARM64DIVW(v) case OpARM64EON: return rewriteValueARM64_OpARM64EON(v) case OpARM64EONshiftLL: return rewriteValueARM64_OpARM64EONshiftLL(v) case OpARM64EONshiftRA: return rewriteValueARM64_OpARM64EONshiftRA(v) case OpARM64EONshiftRL: return rewriteValueARM64_OpARM64EONshiftRL(v) case OpARM64EONshiftRO: return rewriteValueARM64_OpARM64EONshiftRO(v) case OpARM64Equal: return rewriteValueARM64_OpARM64Equal(v) case OpARM64FADDD: return rewriteValueARM64_OpARM64FADDD(v) case OpARM64FADDS: return rewriteValueARM64_OpARM64FADDS(v) case OpARM64FCMPD: return rewriteValueARM64_OpARM64FCMPD(v) case OpARM64FCMPS: return rewriteValueARM64_OpARM64FCMPS(v) case OpARM64FMOVDfpgp: return rewriteValueARM64_OpARM64FMOVDfpgp(v) case OpARM64FMOVDgpfp: return rewriteValueARM64_OpARM64FMOVDgpfp(v) case OpARM64FMOVDload: return rewriteValueARM64_OpARM64FMOVDload(v) case OpARM64FMOVDloadidx: return rewriteValueARM64_OpARM64FMOVDloadidx(v) case OpARM64FMOVDloadidx8: return rewriteValueARM64_OpARM64FMOVDloadidx8(v) case OpARM64FMOVDstore: return rewriteValueARM64_OpARM64FMOVDstore(v) case OpARM64FMOVDstoreidx: return rewriteValueARM64_OpARM64FMOVDstoreidx(v) case OpARM64FMOVDstoreidx8: return rewriteValueARM64_OpARM64FMOVDstoreidx8(v) case OpARM64FMOVSload: return rewriteValueARM64_OpARM64FMOVSload(v) case OpARM64FMOVSloadidx: return rewriteValueARM64_OpARM64FMOVSloadidx(v) case OpARM64FMOVSloadidx4: return rewriteValueARM64_OpARM64FMOVSloadidx4(v) case OpARM64FMOVSstore: return rewriteValueARM64_OpARM64FMOVSstore(v) case OpARM64FMOVSstoreidx: return rewriteValueARM64_OpARM64FMOVSstoreidx(v) case OpARM64FMOVSstoreidx4: return rewriteValueARM64_OpARM64FMOVSstoreidx4(v) case OpARM64FMULD: return rewriteValueARM64_OpARM64FMULD(v) case OpARM64FMULS: return rewriteValueARM64_OpARM64FMULS(v) case OpARM64FNEGD: return rewriteValueARM64_OpARM64FNEGD(v) case OpARM64FNEGS: return rewriteValueARM64_OpARM64FNEGS(v) case OpARM64FNMULD: return rewriteValueARM64_OpARM64FNMULD(v) case OpARM64FNMULS: return rewriteValueARM64_OpARM64FNMULS(v) case OpARM64FSUBD: return rewriteValueARM64_OpARM64FSUBD(v) case OpARM64FSUBS: return rewriteValueARM64_OpARM64FSUBS(v) case OpARM64GreaterEqual: return rewriteValueARM64_OpARM64GreaterEqual(v) case OpARM64GreaterEqualF: return rewriteValueARM64_OpARM64GreaterEqualF(v) case OpARM64GreaterEqualU: return rewriteValueARM64_OpARM64GreaterEqualU(v) case OpARM64GreaterThan: return rewriteValueARM64_OpARM64GreaterThan(v) case OpARM64GreaterThanF: return rewriteValueARM64_OpARM64GreaterThanF(v) case OpARM64GreaterThanU: return rewriteValueARM64_OpARM64GreaterThanU(v) case OpARM64LDP: return rewriteValueARM64_OpARM64LDP(v) case OpARM64LessEqual: return rewriteValueARM64_OpARM64LessEqual(v) case OpARM64LessEqualF: return rewriteValueARM64_OpARM64LessEqualF(v) case OpARM64LessEqualU: return rewriteValueARM64_OpARM64LessEqualU(v) case OpARM64LessThan: return rewriteValueARM64_OpARM64LessThan(v) case OpARM64LessThanF: return rewriteValueARM64_OpARM64LessThanF(v) case OpARM64LessThanU: return rewriteValueARM64_OpARM64LessThanU(v) case OpARM64MADD: return rewriteValueARM64_OpARM64MADD(v) case OpARM64MADDW: return rewriteValueARM64_OpARM64MADDW(v) case OpARM64MNEG: return rewriteValueARM64_OpARM64MNEG(v) case OpARM64MNEGW: return rewriteValueARM64_OpARM64MNEGW(v) case OpARM64MOD: return rewriteValueARM64_OpARM64MOD(v) case OpARM64MODW: return rewriteValueARM64_OpARM64MODW(v) case OpARM64MOVBUload: return rewriteValueARM64_OpARM64MOVBUload(v) case OpARM64MOVBUloadidx: return rewriteValueARM64_OpARM64MOVBUloadidx(v) case OpARM64MOVBUreg: return rewriteValueARM64_OpARM64MOVBUreg(v) case OpARM64MOVBload: return rewriteValueARM64_OpARM64MOVBload(v) case OpARM64MOVBloadidx: return rewriteValueARM64_OpARM64MOVBloadidx(v) case OpARM64MOVBreg: return rewriteValueARM64_OpARM64MOVBreg(v) case OpARM64MOVBstore: return rewriteValueARM64_OpARM64MOVBstore(v) case OpARM64MOVBstoreidx: return rewriteValueARM64_OpARM64MOVBstoreidx(v) case OpARM64MOVBstorezero: return rewriteValueARM64_OpARM64MOVBstorezero(v) case OpARM64MOVBstorezeroidx: return rewriteValueARM64_OpARM64MOVBstorezeroidx(v) case OpARM64MOVDload: return rewriteValueARM64_OpARM64MOVDload(v) case OpARM64MOVDloadidx: return rewriteValueARM64_OpARM64MOVDloadidx(v) case OpARM64MOVDloadidx8: return rewriteValueARM64_OpARM64MOVDloadidx8(v) case OpARM64MOVDnop: return rewriteValueARM64_OpARM64MOVDnop(v) case OpARM64MOVDreg: return rewriteValueARM64_OpARM64MOVDreg(v) case OpARM64MOVDstore: return rewriteValueARM64_OpARM64MOVDstore(v) case OpARM64MOVDstoreidx: return rewriteValueARM64_OpARM64MOVDstoreidx(v) case OpARM64MOVDstoreidx8: return rewriteValueARM64_OpARM64MOVDstoreidx8(v) case OpARM64MOVDstorezero: return rewriteValueARM64_OpARM64MOVDstorezero(v) case OpARM64MOVDstorezeroidx: return rewriteValueARM64_OpARM64MOVDstorezeroidx(v) case OpARM64MOVDstorezeroidx8: return rewriteValueARM64_OpARM64MOVDstorezeroidx8(v) case OpARM64MOVHUload: return rewriteValueARM64_OpARM64MOVHUload(v) case OpARM64MOVHUloadidx: return rewriteValueARM64_OpARM64MOVHUloadidx(v) case OpARM64MOVHUloadidx2: return rewriteValueARM64_OpARM64MOVHUloadidx2(v) case OpARM64MOVHUreg: return rewriteValueARM64_OpARM64MOVHUreg(v) case OpARM64MOVHload: return rewriteValueARM64_OpARM64MOVHload(v) case OpARM64MOVHloadidx: return rewriteValueARM64_OpARM64MOVHloadidx(v) case OpARM64MOVHloadidx2: return rewriteValueARM64_OpARM64MOVHloadidx2(v) case OpARM64MOVHreg: return rewriteValueARM64_OpARM64MOVHreg(v) case OpARM64MOVHstore: return rewriteValueARM64_OpARM64MOVHstore(v) case OpARM64MOVHstoreidx: return rewriteValueARM64_OpARM64MOVHstoreidx(v) case OpARM64MOVHstoreidx2: return rewriteValueARM64_OpARM64MOVHstoreidx2(v) case OpARM64MOVHstorezero: return rewriteValueARM64_OpARM64MOVHstorezero(v) case OpARM64MOVHstorezeroidx: return rewriteValueARM64_OpARM64MOVHstorezeroidx(v) case OpARM64MOVHstorezeroidx2: return rewriteValueARM64_OpARM64MOVHstorezeroidx2(v) case OpARM64MOVQstorezero: return rewriteValueARM64_OpARM64MOVQstorezero(v) case OpARM64MOVWUload: return rewriteValueARM64_OpARM64MOVWUload(v) case OpARM64MOVWUloadidx: return rewriteValueARM64_OpARM64MOVWUloadidx(v) case OpARM64MOVWUloadidx4: return rewriteValueARM64_OpARM64MOVWUloadidx4(v) case OpARM64MOVWUreg: return rewriteValueARM64_OpARM64MOVWUreg(v) case OpARM64MOVWload: return rewriteValueARM64_OpARM64MOVWload(v) case OpARM64MOVWloadidx: return rewriteValueARM64_OpARM64MOVWloadidx(v) case OpARM64MOVWloadidx4: return rewriteValueARM64_OpARM64MOVWloadidx4(v) case OpARM64MOVWreg: return rewriteValueARM64_OpARM64MOVWreg(v) case OpARM64MOVWstore: return rewriteValueARM64_OpARM64MOVWstore(v) case OpARM64MOVWstoreidx: return rewriteValueARM64_OpARM64MOVWstoreidx(v) case OpARM64MOVWstoreidx4: return rewriteValueARM64_OpARM64MOVWstoreidx4(v) case OpARM64MOVWstorezero: return rewriteValueARM64_OpARM64MOVWstorezero(v) case OpARM64MOVWstorezeroidx: return rewriteValueARM64_OpARM64MOVWstorezeroidx(v) case OpARM64MOVWstorezeroidx4: return rewriteValueARM64_OpARM64MOVWstorezeroidx4(v) case OpARM64MSUB: return rewriteValueARM64_OpARM64MSUB(v) case OpARM64MSUBW: return rewriteValueARM64_OpARM64MSUBW(v) case OpARM64MUL: return rewriteValueARM64_OpARM64MUL(v) case OpARM64MULW: return rewriteValueARM64_OpARM64MULW(v) case OpARM64MVN: return rewriteValueARM64_OpARM64MVN(v) case OpARM64MVNshiftLL: return rewriteValueARM64_OpARM64MVNshiftLL(v) case OpARM64MVNshiftRA: return rewriteValueARM64_OpARM64MVNshiftRA(v) case OpARM64MVNshiftRL: return rewriteValueARM64_OpARM64MVNshiftRL(v) case OpARM64MVNshiftRO: return rewriteValueARM64_OpARM64MVNshiftRO(v) case OpARM64NEG: return rewriteValueARM64_OpARM64NEG(v) case OpARM64NEGshiftLL: return rewriteValueARM64_OpARM64NEGshiftLL(v) case OpARM64NEGshiftRA: return rewriteValueARM64_OpARM64NEGshiftRA(v) case OpARM64NEGshiftRL: return rewriteValueARM64_OpARM64NEGshiftRL(v) case OpARM64NotEqual: return rewriteValueARM64_OpARM64NotEqual(v) case OpARM64OR: return rewriteValueARM64_OpARM64OR(v) case OpARM64ORN: return rewriteValueARM64_OpARM64ORN(v) case OpARM64ORNshiftLL: return rewriteValueARM64_OpARM64ORNshiftLL(v) case OpARM64ORNshiftRA: return rewriteValueARM64_OpARM64ORNshiftRA(v) case OpARM64ORNshiftRL: return rewriteValueARM64_OpARM64ORNshiftRL(v) case OpARM64ORNshiftRO: return rewriteValueARM64_OpARM64ORNshiftRO(v) case OpARM64ORconst: return rewriteValueARM64_OpARM64ORconst(v) case OpARM64ORshiftLL: return rewriteValueARM64_OpARM64ORshiftLL(v) case OpARM64ORshiftRA: return rewriteValueARM64_OpARM64ORshiftRA(v) case OpARM64ORshiftRL: return rewriteValueARM64_OpARM64ORshiftRL(v) case OpARM64ORshiftRO: return rewriteValueARM64_OpARM64ORshiftRO(v) case OpARM64REV: return rewriteValueARM64_OpARM64REV(v) case OpARM64REVW: return rewriteValueARM64_OpARM64REVW(v) case OpARM64ROR: return rewriteValueARM64_OpARM64ROR(v) case OpARM64RORW: return rewriteValueARM64_OpARM64RORW(v) case OpARM64SBCSflags: return rewriteValueARM64_OpARM64SBCSflags(v) case OpARM64SLL: return rewriteValueARM64_OpARM64SLL(v) case OpARM64SLLconst: return rewriteValueARM64_OpARM64SLLconst(v) case OpARM64SRA: return rewriteValueARM64_OpARM64SRA(v) case OpARM64SRAconst: return rewriteValueARM64_OpARM64SRAconst(v) case OpARM64SRL: return rewriteValueARM64_OpARM64SRL(v) case OpARM64SRLconst: return rewriteValueARM64_OpARM64SRLconst(v) case OpARM64STP: return rewriteValueARM64_OpARM64STP(v) case OpARM64SUB: return rewriteValueARM64_OpARM64SUB(v) case OpARM64SUBconst: return rewriteValueARM64_OpARM64SUBconst(v) case OpARM64SUBshiftLL: return rewriteValueARM64_OpARM64SUBshiftLL(v) case OpARM64SUBshiftRA: return rewriteValueARM64_OpARM64SUBshiftRA(v) case OpARM64SUBshiftRL: return rewriteValueARM64_OpARM64SUBshiftRL(v) case OpARM64TST: return rewriteValueARM64_OpARM64TST(v) case OpARM64TSTW: return rewriteValueARM64_OpARM64TSTW(v) case OpARM64TSTWconst: return rewriteValueARM64_OpARM64TSTWconst(v) case OpARM64TSTconst: return rewriteValueARM64_OpARM64TSTconst(v) case OpARM64TSTshiftLL: return rewriteValueARM64_OpARM64TSTshiftLL(v) case OpARM64TSTshiftRA: return rewriteValueARM64_OpARM64TSTshiftRA(v) case OpARM64TSTshiftRL: return rewriteValueARM64_OpARM64TSTshiftRL(v) case OpARM64TSTshiftRO: return rewriteValueARM64_OpARM64TSTshiftRO(v) case OpARM64UBFIZ: return rewriteValueARM64_OpARM64UBFIZ(v) case OpARM64UBFX: return rewriteValueARM64_OpARM64UBFX(v) case OpARM64UDIV: return rewriteValueARM64_OpARM64UDIV(v) case OpARM64UDIVW: return rewriteValueARM64_OpARM64UDIVW(v) case OpARM64UMOD: return rewriteValueARM64_OpARM64UMOD(v) case OpARM64UMODW: return rewriteValueARM64_OpARM64UMODW(v) case OpARM64XOR: return rewriteValueARM64_OpARM64XOR(v) case OpARM64XORconst: return rewriteValueARM64_OpARM64XORconst(v) case OpARM64XORshiftLL: return rewriteValueARM64_OpARM64XORshiftLL(v) case OpARM64XORshiftRA: return rewriteValueARM64_OpARM64XORshiftRA(v) case OpARM64XORshiftRL: return rewriteValueARM64_OpARM64XORshiftRL(v) case OpARM64XORshiftRO: return rewriteValueARM64_OpARM64XORshiftRO(v) case OpAbs: v.Op = OpARM64FABSD return true case OpAdd16: v.Op = OpARM64ADD return true case OpAdd32: v.Op = OpARM64ADD return true case OpAdd32F: v.Op = OpARM64FADDS return true case OpAdd64: v.Op = OpARM64ADD return true case OpAdd64F: v.Op = OpARM64FADDD return true case OpAdd8: v.Op = OpARM64ADD return true case OpAddPtr: v.Op = OpARM64ADD return true case OpAddr: return rewriteValueARM64_OpAddr(v) case OpAnd16: v.Op = OpARM64AND return true case OpAnd32: v.Op = OpARM64AND return true case OpAnd64: v.Op = OpARM64AND return true case OpAnd8: v.Op = OpARM64AND return true case OpAndB: v.Op = OpARM64AND return true case OpAtomicAdd32: v.Op = OpARM64LoweredAtomicAdd32 return true case OpAtomicAdd32Variant: v.Op = OpARM64LoweredAtomicAdd32Variant return true case OpAtomicAdd64: v.Op = OpARM64LoweredAtomicAdd64 return true case OpAtomicAdd64Variant: v.Op = OpARM64LoweredAtomicAdd64Variant return true case OpAtomicAnd32: return rewriteValueARM64_OpAtomicAnd32(v) case OpAtomicAnd32Variant: return rewriteValueARM64_OpAtomicAnd32Variant(v) case OpAtomicAnd8: return rewriteValueARM64_OpAtomicAnd8(v) case OpAtomicAnd8Variant: return rewriteValueARM64_OpAtomicAnd8Variant(v) case OpAtomicCompareAndSwap32: v.Op = OpARM64LoweredAtomicCas32 return true case OpAtomicCompareAndSwap32Variant: v.Op = OpARM64LoweredAtomicCas32Variant return true case OpAtomicCompareAndSwap64: v.Op = OpARM64LoweredAtomicCas64 return true case OpAtomicCompareAndSwap64Variant: v.Op = OpARM64LoweredAtomicCas64Variant return true case OpAtomicExchange32: v.Op = OpARM64LoweredAtomicExchange32 return true case OpAtomicExchange32Variant: v.Op = OpARM64LoweredAtomicExchange32Variant return true case OpAtomicExchange64: v.Op = OpARM64LoweredAtomicExchange64 return true case OpAtomicExchange64Variant: v.Op = OpARM64LoweredAtomicExchange64Variant return true case OpAtomicLoad32: v.Op = OpARM64LDARW return true case OpAtomicLoad64: v.Op = OpARM64LDAR return true case OpAtomicLoad8: v.Op = OpARM64LDARB return true case OpAtomicLoadPtr: v.Op = OpARM64LDAR return true case OpAtomicOr32: return rewriteValueARM64_OpAtomicOr32(v) case OpAtomicOr32Variant: return rewriteValueARM64_OpAtomicOr32Variant(v) case OpAtomicOr8: return rewriteValueARM64_OpAtomicOr8(v) case OpAtomicOr8Variant: return rewriteValueARM64_OpAtomicOr8Variant(v) case OpAtomicStore32: v.Op = OpARM64STLRW return true case OpAtomicStore64: v.Op = OpARM64STLR return true case OpAtomicStore8: v.Op = OpARM64STLRB return true case OpAtomicStorePtrNoWB: v.Op = OpARM64STLR return true case OpAvg64u: return rewriteValueARM64_OpAvg64u(v) case OpBitLen32: return rewriteValueARM64_OpBitLen32(v) case OpBitLen64: return rewriteValueARM64_OpBitLen64(v) case OpBitRev16: return rewriteValueARM64_OpBitRev16(v) case OpBitRev32: v.Op = OpARM64RBITW return true case OpBitRev64: v.Op = OpARM64RBIT return true case OpBitRev8: return rewriteValueARM64_OpBitRev8(v) case OpBswap32: v.Op = OpARM64REVW return true case OpBswap64: v.Op = OpARM64REV return true case OpCeil: v.Op = OpARM64FRINTPD return true case OpClosureCall: v.Op = OpARM64CALLclosure return true case OpCom16: v.Op = OpARM64MVN return true case OpCom32: v.Op = OpARM64MVN return true case OpCom64: v.Op = OpARM64MVN return true case OpCom8: v.Op = OpARM64MVN return true case OpCondSelect: return rewriteValueARM64_OpCondSelect(v) case OpConst16: return rewriteValueARM64_OpConst16(v) case OpConst32: return rewriteValueARM64_OpConst32(v) case OpConst32F: return rewriteValueARM64_OpConst32F(v) case OpConst64: return rewriteValueARM64_OpConst64(v) case OpConst64F: return rewriteValueARM64_OpConst64F(v) case OpConst8: return rewriteValueARM64_OpConst8(v) case OpConstBool: return rewriteValueARM64_OpConstBool(v) case OpConstNil: return rewriteValueARM64_OpConstNil(v) case OpCtz16: return rewriteValueARM64_OpCtz16(v) case OpCtz16NonZero: v.Op = OpCtz32 return true case OpCtz32: return rewriteValueARM64_OpCtz32(v) case OpCtz32NonZero: v.Op = OpCtz32 return true case OpCtz64: return rewriteValueARM64_OpCtz64(v) case OpCtz64NonZero: v.Op = OpCtz64 return true case OpCtz8: return rewriteValueARM64_OpCtz8(v) case OpCtz8NonZero: v.Op = OpCtz32 return true case OpCvt32Fto32: v.Op = OpARM64FCVTZSSW return true case OpCvt32Fto32U: v.Op = OpARM64FCVTZUSW return true case OpCvt32Fto64: v.Op = OpARM64FCVTZSS return true case OpCvt32Fto64F: v.Op = OpARM64FCVTSD return true case OpCvt32Fto64U: v.Op = OpARM64FCVTZUS return true case OpCvt32Uto32F: v.Op = OpARM64UCVTFWS return true case OpCvt32Uto64F: v.Op = OpARM64UCVTFWD return true case OpCvt32to32F: v.Op = OpARM64SCVTFWS return true case OpCvt32to64F: v.Op = OpARM64SCVTFWD return true case OpCvt64Fto32: v.Op = OpARM64FCVTZSDW return true case OpCvt64Fto32F: v.Op = OpARM64FCVTDS return true case OpCvt64Fto32U: v.Op = OpARM64FCVTZUDW return true case OpCvt64Fto64: v.Op = OpARM64FCVTZSD return true case OpCvt64Fto64U: v.Op = OpARM64FCVTZUD return true case OpCvt64Uto32F: v.Op = OpARM64UCVTFS return true case OpCvt64Uto64F: v.Op = OpARM64UCVTFD return true case OpCvt64to32F: v.Op = OpARM64SCVTFS return true case OpCvt64to64F: v.Op = OpARM64SCVTFD return true case OpCvtBoolToUint8: v.Op = OpCopy return true case OpDiv16: return rewriteValueARM64_OpDiv16(v) case OpDiv16u: return rewriteValueARM64_OpDiv16u(v) case OpDiv32: return rewriteValueARM64_OpDiv32(v) case OpDiv32F: v.Op = OpARM64FDIVS return true case OpDiv32u: v.Op = OpARM64UDIVW return true case OpDiv64: return rewriteValueARM64_OpDiv64(v) case OpDiv64F: v.Op = OpARM64FDIVD return true case OpDiv64u: v.Op = OpARM64UDIV return true case OpDiv8: return rewriteValueARM64_OpDiv8(v) case OpDiv8u: return rewriteValueARM64_OpDiv8u(v) case OpEq16: return rewriteValueARM64_OpEq16(v) case OpEq32: return rewriteValueARM64_OpEq32(v) case OpEq32F: return rewriteValueARM64_OpEq32F(v) case OpEq64: return rewriteValueARM64_OpEq64(v) case OpEq64F: return rewriteValueARM64_OpEq64F(v) case OpEq8: return rewriteValueARM64_OpEq8(v) case OpEqB: return rewriteValueARM64_OpEqB(v) case OpEqPtr: return rewriteValueARM64_OpEqPtr(v) case OpFMA: return rewriteValueARM64_OpFMA(v) case OpFloor: v.Op = OpARM64FRINTMD return true case OpGetCallerPC: v.Op = OpARM64LoweredGetCallerPC return true case OpGetCallerSP: v.Op = OpARM64LoweredGetCallerSP return true case OpGetClosurePtr: v.Op = OpARM64LoweredGetClosurePtr return true case OpHmul32: return rewriteValueARM64_OpHmul32(v) case OpHmul32u: return rewriteValueARM64_OpHmul32u(v) case OpHmul64: v.Op = OpARM64MULH return true case OpHmul64u: v.Op = OpARM64UMULH return true case OpInterCall: v.Op = OpARM64CALLinter return true case OpIsInBounds: return rewriteValueARM64_OpIsInBounds(v) case OpIsNonNil: return rewriteValueARM64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueARM64_OpIsSliceInBounds(v) case OpLeq16: return rewriteValueARM64_OpLeq16(v) case OpLeq16U: return rewriteValueARM64_OpLeq16U(v) case OpLeq32: return rewriteValueARM64_OpLeq32(v) case OpLeq32F: return rewriteValueARM64_OpLeq32F(v) case OpLeq32U: return rewriteValueARM64_OpLeq32U(v) case OpLeq64: return rewriteValueARM64_OpLeq64(v) case OpLeq64F: return rewriteValueARM64_OpLeq64F(v) case OpLeq64U: return rewriteValueARM64_OpLeq64U(v) case OpLeq8: return rewriteValueARM64_OpLeq8(v) case OpLeq8U: return rewriteValueARM64_OpLeq8U(v) case OpLess16: return rewriteValueARM64_OpLess16(v) case OpLess16U: return rewriteValueARM64_OpLess16U(v) case OpLess32: return rewriteValueARM64_OpLess32(v) case OpLess32F: return rewriteValueARM64_OpLess32F(v) case OpLess32U: return rewriteValueARM64_OpLess32U(v) case OpLess64: return rewriteValueARM64_OpLess64(v) case OpLess64F: return rewriteValueARM64_OpLess64F(v) case OpLess64U: return rewriteValueARM64_OpLess64U(v) case OpLess8: return rewriteValueARM64_OpLess8(v) case OpLess8U: return rewriteValueARM64_OpLess8U(v) case OpLoad: return rewriteValueARM64_OpLoad(v) case OpLocalAddr: return rewriteValueARM64_OpLocalAddr(v) case OpLsh16x16: return rewriteValueARM64_OpLsh16x16(v) case OpLsh16x32: return rewriteValueARM64_OpLsh16x32(v) case OpLsh16x64: return rewriteValueARM64_OpLsh16x64(v) case OpLsh16x8: return rewriteValueARM64_OpLsh16x8(v) case OpLsh32x16: return rewriteValueARM64_OpLsh32x16(v) case OpLsh32x32: return rewriteValueARM64_OpLsh32x32(v) case OpLsh32x64: return rewriteValueARM64_OpLsh32x64(v) case OpLsh32x8: return rewriteValueARM64_OpLsh32x8(v) case OpLsh64x16: return rewriteValueARM64_OpLsh64x16(v) case OpLsh64x32: return rewriteValueARM64_OpLsh64x32(v) case OpLsh64x64: return rewriteValueARM64_OpLsh64x64(v) case OpLsh64x8: return rewriteValueARM64_OpLsh64x8(v) case OpLsh8x16: return rewriteValueARM64_OpLsh8x16(v) case OpLsh8x32: return rewriteValueARM64_OpLsh8x32(v) case OpLsh8x64: return rewriteValueARM64_OpLsh8x64(v) case OpLsh8x8: return rewriteValueARM64_OpLsh8x8(v) case OpMod16: return rewriteValueARM64_OpMod16(v) case OpMod16u: return rewriteValueARM64_OpMod16u(v) case OpMod32: return rewriteValueARM64_OpMod32(v) case OpMod32u: v.Op = OpARM64UMODW return true case OpMod64: return rewriteValueARM64_OpMod64(v) case OpMod64u: v.Op = OpARM64UMOD return true case OpMod8: return rewriteValueARM64_OpMod8(v) case OpMod8u: return rewriteValueARM64_OpMod8u(v) case OpMove: return rewriteValueARM64_OpMove(v) case OpMul16: v.Op = OpARM64MULW return true case OpMul32: v.Op = OpARM64MULW return true case OpMul32F: v.Op = OpARM64FMULS return true case OpMul64: v.Op = OpARM64MUL return true case OpMul64F: v.Op = OpARM64FMULD return true case OpMul8: v.Op = OpARM64MULW return true case OpNeg16: v.Op = OpARM64NEG return true case OpNeg32: v.Op = OpARM64NEG return true case OpNeg32F: v.Op = OpARM64FNEGS return true case OpNeg64: v.Op = OpARM64NEG return true case OpNeg64F: v.Op = OpARM64FNEGD return true case OpNeg8: v.Op = OpARM64NEG return true case OpNeq16: return rewriteValueARM64_OpNeq16(v) case OpNeq32: return rewriteValueARM64_OpNeq32(v) case OpNeq32F: return rewriteValueARM64_OpNeq32F(v) case OpNeq64: return rewriteValueARM64_OpNeq64(v) case OpNeq64F: return rewriteValueARM64_OpNeq64F(v) case OpNeq8: return rewriteValueARM64_OpNeq8(v) case OpNeqB: v.Op = OpARM64XOR return true case OpNeqPtr: return rewriteValueARM64_OpNeqPtr(v) case OpNilCheck: v.Op = OpARM64LoweredNilCheck return true case OpNot: return rewriteValueARM64_OpNot(v) case OpOffPtr: return rewriteValueARM64_OpOffPtr(v) case OpOr16: v.Op = OpARM64OR return true case OpOr32: v.Op = OpARM64OR return true case OpOr64: v.Op = OpARM64OR return true case OpOr8: v.Op = OpARM64OR return true case OpOrB: v.Op = OpARM64OR return true case OpPanicBounds: return rewriteValueARM64_OpPanicBounds(v) case OpPopCount16: return rewriteValueARM64_OpPopCount16(v) case OpPopCount32: return rewriteValueARM64_OpPopCount32(v) case OpPopCount64: return rewriteValueARM64_OpPopCount64(v) case OpPrefetchCache: return rewriteValueARM64_OpPrefetchCache(v) case OpPrefetchCacheStreamed: return rewriteValueARM64_OpPrefetchCacheStreamed(v) case OpPubBarrier: return rewriteValueARM64_OpPubBarrier(v) case OpRotateLeft16: return rewriteValueARM64_OpRotateLeft16(v) case OpRotateLeft32: return rewriteValueARM64_OpRotateLeft32(v) case OpRotateLeft64: return rewriteValueARM64_OpRotateLeft64(v) case OpRotateLeft8: return rewriteValueARM64_OpRotateLeft8(v) case OpRound: v.Op = OpARM64FRINTAD return true case OpRound32F: v.Op = OpARM64LoweredRound32F return true case OpRound64F: v.Op = OpARM64LoweredRound64F return true case OpRoundToEven: v.Op = OpARM64FRINTND return true case OpRsh16Ux16: return rewriteValueARM64_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValueARM64_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValueARM64_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValueARM64_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValueARM64_OpRsh16x16(v) case OpRsh16x32: return rewriteValueARM64_OpRsh16x32(v) case OpRsh16x64: return rewriteValueARM64_OpRsh16x64(v) case OpRsh16x8: return rewriteValueARM64_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValueARM64_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValueARM64_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValueARM64_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValueARM64_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValueARM64_OpRsh32x16(v) case OpRsh32x32: return rewriteValueARM64_OpRsh32x32(v) case OpRsh32x64: return rewriteValueARM64_OpRsh32x64(v) case OpRsh32x8: return rewriteValueARM64_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValueARM64_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValueARM64_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValueARM64_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValueARM64_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValueARM64_OpRsh64x16(v) case OpRsh64x32: return rewriteValueARM64_OpRsh64x32(v) case OpRsh64x64: return rewriteValueARM64_OpRsh64x64(v) case OpRsh64x8: return rewriteValueARM64_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValueARM64_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValueARM64_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValueARM64_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValueARM64_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValueARM64_OpRsh8x16(v) case OpRsh8x32: return rewriteValueARM64_OpRsh8x32(v) case OpRsh8x64: return rewriteValueARM64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueARM64_OpRsh8x8(v) case OpSelect0: return rewriteValueARM64_OpSelect0(v) case OpSelect1: return rewriteValueARM64_OpSelect1(v) case OpSelectN: return rewriteValueARM64_OpSelectN(v) case OpSignExt16to32: v.Op = OpARM64MOVHreg return true case OpSignExt16to64: v.Op = OpARM64MOVHreg return true case OpSignExt32to64: v.Op = OpARM64MOVWreg return true case OpSignExt8to16: v.Op = OpARM64MOVBreg return true case OpSignExt8to32: v.Op = OpARM64MOVBreg return true case OpSignExt8to64: v.Op = OpARM64MOVBreg return true case OpSlicemask: return rewriteValueARM64_OpSlicemask(v) case OpSqrt: v.Op = OpARM64FSQRTD return true case OpSqrt32: v.Op = OpARM64FSQRTS return true case OpStaticCall: v.Op = OpARM64CALLstatic return true case OpStore: return rewriteValueARM64_OpStore(v) case OpSub16: v.Op = OpARM64SUB return true case OpSub32: v.Op = OpARM64SUB return true case OpSub32F: v.Op = OpARM64FSUBS return true case OpSub64: v.Op = OpARM64SUB return true case OpSub64F: v.Op = OpARM64FSUBD return true case OpSub8: v.Op = OpARM64SUB return true case OpSubPtr: v.Op = OpARM64SUB return true case OpTailCall: v.Op = OpARM64CALLtail return true case OpTrunc: v.Op = OpARM64FRINTZD return true case OpTrunc16to8: v.Op = OpCopy return true case OpTrunc32to16: v.Op = OpCopy return true case OpTrunc32to8: v.Op = OpCopy return true case OpTrunc64to16: v.Op = OpCopy return true case OpTrunc64to32: v.Op = OpCopy return true case OpTrunc64to8: v.Op = OpCopy return true case OpWB: v.Op = OpARM64LoweredWB return true case OpXor16: v.Op = OpARM64XOR return true case OpXor32: v.Op = OpARM64XOR return true case OpXor64: v.Op = OpARM64XOR return true case OpXor8: v.Op = OpARM64XOR return true case OpZero: return rewriteValueARM64_OpZero(v) case OpZeroExt16to32: v.Op = OpARM64MOVHUreg return true case OpZeroExt16to64: v.Op = OpARM64MOVHUreg return true case OpZeroExt32to64: v.Op = OpARM64MOVWUreg return true case OpZeroExt8to16: v.Op = OpARM64MOVBUreg return true case OpZeroExt8to32: v.Op = OpARM64MOVBUreg return true case OpZeroExt8to64: v.Op = OpARM64MOVBUreg return true } return false } func rewriteValueARM64_OpARM64ADCSflags(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADCSflags x y (Select1 (ADDSconstflags [-1] (ADCzerocarry c)))) // result: (ADCSflags x y c) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64ADDSconstflags || auxIntToInt64(v_2_0.AuxInt) != -1 { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64ADCzerocarry || v_2_0_0.Type != typ.UInt64 { break } c := v_2_0_0.Args[0] v.reset(OpARM64ADCSflags) v.AddArg3(x, y, c) return true } // match: (ADCSflags x y (Select1 (ADDSconstflags [-1] (MOVDconst [0])))) // result: (ADDSflags x y) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64ADDSconstflags || auxIntToInt64(v_2_0.AuxInt) != -1 { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64MOVDconst || auxIntToInt64(v_2_0_0.AuxInt) != 0 { break } v.reset(OpARM64ADDSflags) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64ADD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADD x (MOVDconst [c])) // cond: !t.IsPtr() // result: (ADDconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(!t.IsPtr()) { continue } v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADD a l:(MUL x y)) // cond: l.Uses==1 && clobber(l) // result: (MADD a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MUL { continue } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MADD) v.AddArg3(a, x, y) return true } break } // match: (ADD a l:(MNEG x y)) // cond: l.Uses==1 && clobber(l) // result: (MSUB a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MNEG { continue } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MSUB) v.AddArg3(a, x, y) return true } break } // match: (ADD a l:(MULW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MADDW a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MULW { continue } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MADDW) v.AddArg3(a, x, y) return true } break } // match: (ADD a l:(MNEGW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MSUBW a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MNEGW { continue } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MSUBW) v.AddArg3(a, x, y) return true } break } // match: (ADD x (NEG y)) // result: (SUB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64NEG { continue } y := v_1.Args[0] v.reset(OpARM64SUB) v.AddArg2(x, y) return true } break } // match: (ADD x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ADDshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (ADD x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ADDshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ADDshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (ADD x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ADDshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ADDshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64ADDSflags(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSflags x (MOVDconst [c])) // result: (ADDSconstflags [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ADDSconstflags) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } return false } func rewriteValueARM64_OpARM64ADDconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDconst [off1] (MOVDaddr [off2] {sym} ptr)) // cond: is32Bit(off1+int64(off2)) // result: (MOVDaddr [int32(off1)+off2] {sym} ptr) for { off1 := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) ptr := v_0.Args[0] if !(is32Bit(off1 + int64(off2))) { break } v.reset(OpARM64MOVDaddr) v.AuxInt = int32ToAuxInt(int32(off1) + off2) v.Aux = symToAux(sym) v.AddArg(ptr) return true } // match: (ADDconst [c] y) // cond: c < 0 // result: (SUBconst [-c] y) for { c := auxIntToInt64(v.AuxInt) y := v_0 if !(c < 0) { break } v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(-c) v.AddArg(y) return true } // match: (ADDconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ADDconst [c] (MOVDconst [d])) // result: (MOVDconst [c+d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c + d) return true } // match: (ADDconst [c] (ADDconst [d] x)) // result: (ADDconst [c+d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ADDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDconst [c] (SUBconst [d] x)) // result: (ADDconst [c-d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SUBconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c - d) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ADDshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDshiftLL (MOVDconst [c]) x [d]) // result: (ADDconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftLL x (MOVDconst [c]) [d]) // result: (ADDconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) // result: (REV16W x) for { if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ADDshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff // result: (REV16W x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ADDshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) // result: (REV16 x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { break } v.reset(OpARM64REV16) v.AddArg(x) return true } // match: (ADDshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) // result: (REV16 (ANDconst [0xffffffff] x)) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16) v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) v0.AuxInt = int64ToAuxInt(0xffffffff) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftLL [c] (SRLconst x [64-c]) x2) // result: (EXTRconst [64-c] x2 x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { break } x := v_0.Args[0] x2 := v_1 v.reset(OpARM64EXTRconst) v.AuxInt = int64ToAuxInt(64 - c) v.AddArg2(x2, x) return true } // match: (ADDshiftLL [c] (UBFX [bfc] x) x2) // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) // result: (EXTRWconst [32-c] x2 x) for { t := v.Type c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] x2 := v_1 if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { break } v.reset(OpARM64EXTRWconst) v.AuxInt = int64ToAuxInt(32 - c) v.AddArg2(x2, x) return true } return false } func rewriteValueARM64_OpARM64ADDshiftRA(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ADDshiftRA (MOVDconst [c]) x [d]) // result: (ADDconst [c] (SRAconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftRA x (MOVDconst [c]) [d]) // result: (ADDconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ADDshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ADDshiftRL (MOVDconst [c]) x [d]) // result: (ADDconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftRL x (MOVDconst [c]) [d]) // result: (ADDconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64AND(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (AND x (MOVDconst [c])) // result: (ANDconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (AND x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (AND x (MVN y)) // result: (BIC x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MVN { continue } y := v_1.Args[0] v.reset(OpARM64BIC) v.AddArg2(x, y) return true } break } // match: (AND x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (AND x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (AND x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (AND x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64ANDconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDconst [0] _) // result: (MOVDconst [0]) for { if auxIntToInt64(v.AuxInt) != 0 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (ANDconst [-1] x) // result: x for { if auxIntToInt64(v.AuxInt) != -1 { break } x := v_0 v.copyOf(x) return true } // match: (ANDconst [c] (MOVDconst [d])) // result: (MOVDconst [c&d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c & d) return true } // match: (ANDconst [c] (ANDconst [d] x)) // result: (ANDconst [c&d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDconst [c] (MOVWUreg x)) // result: (ANDconst [c&(1<<32-1)] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg { break } x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<32 - 1)) v.AddArg(x) return true } // match: (ANDconst [c] (MOVHUreg x)) // result: (ANDconst [c&(1<<16-1)] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg { break } x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<16 - 1)) v.AddArg(x) return true } // match: (ANDconst [c] (MOVBUreg x)) // result: (ANDconst [c&(1<<8-1)] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg { break } x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<8 - 1)) v.AddArg(x) return true } // match: (ANDconst [ac] (SLLconst [sc] x)) // cond: isARM64BFMask(sc, ac, sc) // result: (UBFIZ [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x) for { ac := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(sc, ac, sc)) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc, arm64BFWidth(ac, sc))) v.AddArg(x) return true } // match: (ANDconst [ac] (SRLconst [sc] x)) // cond: isARM64BFMask(sc, ac, 0) // result: (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, 0))] x) for { ac := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(sc, ac, 0)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc, arm64BFWidth(ac, 0))) v.AddArg(x) return true } // match: (ANDconst [c] (UBFX [bfc] x)) // cond: isARM64BFMask(0, c, 0) // result: (UBFX [armBFAuxInt(bfc.getARM64BFlsb(), min(bfc.getARM64BFwidth(), arm64BFWidth(c, 0)))] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(0, c, 0)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb(), min(bfc.getARM64BFwidth(), arm64BFWidth(c, 0)))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ANDshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ANDshiftLL (MOVDconst [c]) x [d]) // result: (ANDconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftLL x (MOVDconst [c]) [d]) // result: (ANDconst x [int64(uint64(c)< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftRA x (MOVDconst [c]) [d]) // result: (ANDconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (ANDshiftRA y:(SRAconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRAconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64ANDshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ANDshiftRL (MOVDconst [c]) x [d]) // result: (ANDconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftRL x (MOVDconst [c]) [d]) // result: (ANDconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (ANDshiftRL y:(SRLconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRLconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64ANDshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ANDshiftRO (MOVDconst [c]) x [d]) // result: (ANDconst [c] (RORconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftRO x (MOVDconst [c]) [d]) // result: (ANDconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } // match: (ANDshiftRO y:(RORconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64RORconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64BIC(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BIC x (MOVDconst [c])) // result: (ANDconst [^c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^c) v.AddArg(x) return true } // match: (BIC x x) // result: (MOVDconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (BIC x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (BIC x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (BIC x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (BIC x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftRO x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64BICshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BICshiftLL x (MOVDconst [c]) [d]) // result: (ANDconst x [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) v.AddArg(x) return true } // match: (BICshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64BICshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BICshiftRL x (MOVDconst [c]) [d]) // result: (ANDconst x [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (BICshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64BICshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BICshiftRO x (MOVDconst [c]) [d]) // result: (ANDconst x [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) v.AddArg(x) return true } // match: (BICshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64CMN(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMN x (MOVDconst [c])) // result: (CMNconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (CMN x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMNshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64CMNshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (CMN x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMNshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64CMNshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (CMN x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (CMNshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64CMNshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64CMNW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMNW x (MOVDconst [c])) // result: (CMNWconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNWconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueARM64_OpARM64CMNWconst(v *Value) bool { v_0 := v.Args[0] // match: (CMNWconst [c] y) // cond: c < 0 && c != -1<<31 // result: (CMPWconst [-c] y) for { c := auxIntToInt32(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<31) { break } v.reset(OpARM64CMPWconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(y) return true } // match: (CMNWconst (MOVDconst [x]) [y]) // result: (FlagConstant [addFlags32(int32(x),y)]) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(addFlags32(int32(x), y)) return true } return false } func rewriteValueARM64_OpARM64CMNconst(v *Value) bool { v_0 := v.Args[0] // match: (CMNconst [c] y) // cond: c < 0 && c != -1<<63 // result: (CMPconst [-c] y) for { c := auxIntToInt64(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<63) { break } v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(-c) v.AddArg(y) return true } // match: (CMNconst (MOVDconst [x]) [y]) // result: (FlagConstant [addFlags64(x,y)]) for { y := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(addFlags64(x, y)) return true } return false } func rewriteValueARM64_OpARM64CMNshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMNshiftLL (MOVDconst [c]) x [d]) // result: (CMNconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMNshiftLL x (MOVDconst [c]) [d]) // result: (CMNconst x [int64(uint64(c)< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMNshiftRA x (MOVDconst [c]) [d]) // result: (CMNconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CMNshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMNshiftRL (MOVDconst [c]) x [d]) // result: (CMNconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMNshiftRL x (MOVDconst [c]) [d]) // result: (CMNconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CMP(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMP x (MOVDconst [c])) // result: (CMPconst [c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (CMP (MOVDconst [c]) x) // result: (InvertFlags (CMPconst [c] x)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMP x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMP y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMP x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMPshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64CMPshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (CMP x0:(SLLconst [c] y) x1) // cond: clobberIfDead(x0) // result: (InvertFlags (CMPshiftLL x1 y [c])) for { x0 := v_0 if x0.Op != OpARM64SLLconst { break } c := auxIntToInt64(x0.AuxInt) y := x0.Args[0] x1 := v_1 if !(clobberIfDead(x0)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPshiftLL, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg2(x1, y) v.AddArg(v0) return true } // match: (CMP x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMPshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64CMPshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (CMP x0:(SRLconst [c] y) x1) // cond: clobberIfDead(x0) // result: (InvertFlags (CMPshiftRL x1 y [c])) for { x0 := v_0 if x0.Op != OpARM64SRLconst { break } c := auxIntToInt64(x0.AuxInt) y := x0.Args[0] x1 := v_1 if !(clobberIfDead(x0)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRL, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg2(x1, y) v.AddArg(v0) return true } // match: (CMP x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (CMPshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64CMPshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (CMP x0:(SRAconst [c] y) x1) // cond: clobberIfDead(x0) // result: (InvertFlags (CMPshiftRA x1 y [c])) for { x0 := v_0 if x0.Op != OpARM64SRAconst { break } c := auxIntToInt64(x0.AuxInt) y := x0.Args[0] x1 := v_1 if !(clobberIfDead(x0)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRA, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg2(x1, y) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64CMPW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPW x (MOVDconst [c])) // result: (CMPWconst [int32(c)] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPWconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } // match: (CMPW (MOVDconst [c]) x) // result: (InvertFlags (CMPWconst [int32(c)] x)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPW x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPW y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64CMPWconst(v *Value) bool { v_0 := v.Args[0] // match: (CMPWconst [c] y) // cond: c < 0 && c != -1<<31 // result: (CMNWconst [-c] y) for { c := auxIntToInt32(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<31) { break } v.reset(OpARM64CMNWconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(y) return true } // match: (CMPWconst (MOVDconst [x]) [y]) // result: (FlagConstant [subFlags32(int32(x),y)]) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags32(int32(x), y)) return true } // match: (CMPWconst (MOVBUreg _) [c]) // cond: 0xff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVBUreg || !(0xff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPWconst (MOVHUreg _) [c]) // cond: 0xffff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVHUreg || !(0xffff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } return false } func rewriteValueARM64_OpARM64CMPconst(v *Value) bool { v_0 := v.Args[0] // match: (CMPconst [c] y) // cond: c < 0 && c != -1<<63 // result: (CMNconst [-c] y) for { c := auxIntToInt64(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<63) { break } v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(-c) v.AddArg(y) return true } // match: (CMPconst (MOVDconst [x]) [y]) // result: (FlagConstant [subFlags64(x,y)]) for { y := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(x, y)) return true } // match: (CMPconst (MOVBUreg _) [c]) // cond: 0xff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg || !(0xff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (MOVHUreg _) [c]) // cond: 0xffff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg || !(0xffff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (MOVWUreg _) [c]) // cond: 0xffffffff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg || !(0xffffffff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (ANDconst _ [m]) [n]) // cond: 0 <= m && m < n // result: (FlagConstant [subFlags64(0,1)]) for { n := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } m := auxIntToInt64(v_0.AuxInt) if !(0 <= m && m < n) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (SRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 63 && (1< x [d]))) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v1 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v1.AuxInt = int64ToAuxInt(d) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (CMPshiftLL x (MOVDconst [c]) [d]) // result: (CMPconst x [int64(uint64(c)< x [d]))) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v1 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v1.AuxInt = int64ToAuxInt(d) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (CMPshiftRA x (MOVDconst [c]) [d]) // result: (CMPconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CMPshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPshiftRL (MOVDconst [c]) x [d]) // result: (InvertFlags (CMPconst [c] (SRLconst x [d]))) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v1 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v1.AuxInt = int64ToAuxInt(d) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (CMPshiftRL x (MOVDconst [c]) [d]) // result: (CMPconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CSEL(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSEL [cc] (MOVDconst [-1]) (MOVDconst [0]) flag) // result: (CSETM [cc] flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != -1 || v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } flag := v_2 v.reset(OpARM64CSETM) v.AuxInt = opToAuxInt(cc) v.AddArg(flag) return true } // match: (CSEL [cc] (MOVDconst [0]) (MOVDconst [-1]) flag) // result: (CSETM [arm64Negate(cc)] flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 0 || v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { break } flag := v_2 v.reset(OpARM64CSETM) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg(flag) return true } // match: (CSEL [cc] x (MOVDconst [0]) flag) // result: (CSEL0 [cc] x flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } flag := v_2 v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(cc) v.AddArg2(x, flag) return true } // match: (CSEL [cc] (MOVDconst [0]) y flag) // result: (CSEL0 [arm64Negate(cc)] y flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 0 { break } y := v_1 flag := v_2 v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg2(y, flag) return true } // match: (CSEL [cc] x (ADDconst [1] a) flag) // result: (CSINC [cc] x a flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } a := v_1.Args[0] flag := v_2 v.reset(OpARM64CSINC) v.AuxInt = opToAuxInt(cc) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] (ADDconst [1] a) x flag) // result: (CSINC [arm64Negate(cc)] x a flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64ADDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } a := v_0.Args[0] x := v_1 flag := v_2 v.reset(OpARM64CSINC) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] x (MVN a) flag) // result: (CSINV [cc] x a flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64MVN { break } a := v_1.Args[0] flag := v_2 v.reset(OpARM64CSINV) v.AuxInt = opToAuxInt(cc) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] (MVN a) x flag) // result: (CSINV [arm64Negate(cc)] x a flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MVN { break } a := v_0.Args[0] x := v_1 flag := v_2 v.reset(OpARM64CSINV) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] x (NEG a) flag) // result: (CSNEG [cc] x a flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64NEG { break } a := v_1.Args[0] flag := v_2 v.reset(OpARM64CSNEG) v.AuxInt = opToAuxInt(cc) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] (NEG a) x flag) // result: (CSNEG [arm64Negate(cc)] x a flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64NEG { break } a := v_0.Args[0] x := v_1 flag := v_2 v.reset(OpARM64CSNEG) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] x y (InvertFlags cmp)) // result: (CSEL [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSEL [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSEL [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: y for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.copyOf(y) return true } // match: (CSEL [cc] x y (CMPWconst [0] boolval)) // cond: cc == OpARM64NotEqual && flagArg(boolval) != nil // result: (CSEL [boolval.Op] x y flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64CMPWconst || auxIntToInt32(v_2.AuxInt) != 0 { break } boolval := v_2.Args[0] if !(cc == OpARM64NotEqual && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(boolval.Op) v.AddArg3(x, y, flagArg(boolval)) return true } // match: (CSEL [cc] x y (CMPWconst [0] boolval)) // cond: cc == OpARM64Equal && flagArg(boolval) != nil // result: (CSEL [arm64Negate(boolval.Op)] x y flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64CMPWconst || auxIntToInt32(v_2.AuxInt) != 0 { break } boolval := v_2.Args[0] if !(cc == OpARM64Equal && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(arm64Negate(boolval.Op)) v.AddArg3(x, y, flagArg(boolval)) return true } return false } func rewriteValueARM64_OpARM64CSEL0(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSEL0 [cc] x (InvertFlags cmp)) // result: (CSEL0 [arm64Invert(cc)] x cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64InvertFlags { break } cmp := v_1.Args[0] v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg2(x, cmp) return true } // match: (CSEL0 [cc] x flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_1 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSEL0 [cc] _ flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (MOVDconst [0]) for { cc := auxIntToOp(v.AuxInt) flag := v_1 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (CSEL0 [cc] x (CMPWconst [0] boolval)) // cond: cc == OpARM64NotEqual && flagArg(boolval) != nil // result: (CSEL0 [boolval.Op] x flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64CMPWconst || auxIntToInt32(v_1.AuxInt) != 0 { break } boolval := v_1.Args[0] if !(cc == OpARM64NotEqual && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(boolval.Op) v.AddArg2(x, flagArg(boolval)) return true } // match: (CSEL0 [cc] x (CMPWconst [0] boolval)) // cond: cc == OpARM64Equal && flagArg(boolval) != nil // result: (CSEL0 [arm64Negate(boolval.Op)] x flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64CMPWconst || auxIntToInt32(v_1.AuxInt) != 0 { break } boolval := v_1.Args[0] if !(cc == OpARM64Equal && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(arm64Negate(boolval.Op)) v.AddArg2(x, flagArg(boolval)) return true } return false } func rewriteValueARM64_OpARM64CSETM(v *Value) bool { v_0 := v.Args[0] // match: (CSETM [cc] (InvertFlags cmp)) // result: (CSETM [arm64Invert(cc)] cmp) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64InvertFlags { break } cmp := v_0.Args[0] v.reset(OpARM64CSETM) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg(cmp) return true } // match: (CSETM [cc] flag) // cond: ccARM64Eval(cc, flag) > 0 // result: (MOVDconst [-1]) for { cc := auxIntToOp(v.AuxInt) flag := v_0 if !(ccARM64Eval(cc, flag) > 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (CSETM [cc] flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (MOVDconst [0]) for { cc := auxIntToOp(v.AuxInt) flag := v_0 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64CSINC(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSINC [cc] x y (InvertFlags cmp)) // result: (CSINC [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSINC) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSINC [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSINC [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (ADDconst [1] y) for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(1) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64CSINV(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSINV [cc] x y (InvertFlags cmp)) // result: (CSINV [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSINV) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSINV [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSINV [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (Not y) for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpNot) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64CSNEG(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSNEG [cc] x y (InvertFlags cmp)) // result: (CSNEG [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSNEG) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSNEG [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSNEG [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (NEG y) for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64NEG) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64DIV(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIV (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [c/d]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c / d) return true } return false } func rewriteValueARM64_OpARM64DIVW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(int32(c)/int32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) / int32(d))) return true } return false } func rewriteValueARM64_OpARM64EON(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EON x (MOVDconst [c])) // result: (XORconst [^c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^c) v.AddArg(x) return true } // match: (EON x x) // result: (MOVDconst [-1]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (EON x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (EON x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (EON x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (EON x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftRO x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64EONshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EONshiftLL x (MOVDconst [c]) [d]) // result: (XORconst x [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) v.AddArg(x) return true } // match: (EONshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64EONshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EONshiftRL x (MOVDconst [c]) [d]) // result: (XORconst x [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (EONshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64EONshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EONshiftRO x (MOVDconst [c]) [d]) // result: (XORconst x [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) v.AddArg(x) return true } // match: (EONshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64Equal(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Equal (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (Equal (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (Equal (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMP x z:(NEG y))) // cond: z.Uses == 1 // result: (Equal (CMN x y)) for { if v_0.Op != OpARM64CMP { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPW x z:(NEG y))) // cond: z.Uses == 1 // result: (Equal (CMNW x y)) for { if v_0.Op != OpARM64CMPW { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (Equal (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (Equal (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (Equal (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (Equal (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (Equal (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (Equal (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.eq())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.eq())) return true } // match: (Equal (InvertFlags x)) // result: (Equal x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64Equal) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64FADDD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FADDD a (FMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDD a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FMULD { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMADDD) v.AddArg3(a, x, y) return true } break } // match: (FADDD a (FNMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBD a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FNMULD { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMSUBD) v.AddArg3(a, x, y) return true } break } return false } func rewriteValueARM64_OpARM64FADDS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FADDS a (FMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDS a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FMULS { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMADDS) v.AddArg3(a, x, y) return true } break } // match: (FADDS a (FNMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBS a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FNMULS { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMSUBS) v.AddArg3(a, x, y) return true } break } return false } func rewriteValueARM64_OpARM64FCMPD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (FCMPD x (FMOVDconst [0])) // result: (FCMPD0 x) for { x := v_0 if v_1.Op != OpARM64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != 0 { break } v.reset(OpARM64FCMPD0) v.AddArg(x) return true } // match: (FCMPD (FMOVDconst [0]) x) // result: (InvertFlags (FCMPD0 x)) for { if v_0.Op != OpARM64FMOVDconst || auxIntToFloat64(v_0.AuxInt) != 0 { break } x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64FCMPD0, types.TypeFlags) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64FCMPS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (FCMPS x (FMOVSconst [0])) // result: (FCMPS0 x) for { x := v_0 if v_1.Op != OpARM64FMOVSconst || auxIntToFloat64(v_1.AuxInt) != 0 { break } v.reset(OpARM64FCMPS0) v.AddArg(x) return true } // match: (FCMPS (FMOVSconst [0]) x) // result: (InvertFlags (FCMPS0 x)) for { if v_0.Op != OpARM64FMOVSconst || auxIntToFloat64(v_0.AuxInt) != 0 { break } x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64FCMPS0, types.TypeFlags) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64FMOVDfpgp(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (FMOVDfpgp (Arg [off] {sym})) // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueARM64_OpARM64FMOVDgpfp(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (FMOVDgpfp (Arg [off] {sym})) // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueARM64_OpARM64FMOVDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _)) // result: (FMOVDgpfp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVDgpfp) v.AddArg(val) return true } // match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (FMOVDload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVDloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVDloadidx8 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (FMOVDload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVDloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (FMOVDload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVDloadidx ptr (SLLconst [3] idx) mem) // result: (FMOVDloadidx8 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVDloadidx (SLLconst [3] idx) ptr mem) // result: (FMOVDloadidx8 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64FMOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDloadidx8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDloadidx8 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<3) // result: (FMOVDload ptr [int32(c)<<3] mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 3)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVDstore [off] {sym} ptr (FMOVDgpfp val) mem) // result: (MOVDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVDgpfp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVDstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVDstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVDstoreidx8 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (FMOVDstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (FMOVDstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (FMOVDstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (FMOVDstoreidx ptr (SLLconst [3] idx) val mem) // result: (FMOVDstoreidx8 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64FMOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVDstoreidx (SLLconst [3] idx) ptr val mem) // result: (FMOVDstoreidx8 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64FMOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDstoreidx8(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDstoreidx8 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<3) // result: (FMOVDstore [int32(c)<<3] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 3)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVSload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) // result: (FMOVSgpfp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVSgpfp) v.AddArg(val) return true } // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (FMOVSload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVSloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVSload [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVSloadidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (FMOVSload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVSloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (FMOVSload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVSloadidx ptr (SLLconst [2] idx) mem) // result: (FMOVSloadidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVSloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVSloadidx (SLLconst [2] idx) ptr mem) // result: (FMOVSloadidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64FMOVSloadidx4) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSloadidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSloadidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (FMOVSload ptr [int32(c)<<2] mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVSstore [off] {sym} ptr (FMOVSgpfp val) mem) // result: (MOVWstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVSgpfp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVSstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVSstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVSstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVSstoreidx4 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (FMOVSstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (FMOVSstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (FMOVSstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (FMOVSstoreidx ptr (SLLconst [2] idx) val mem) // result: (FMOVSstoreidx4 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64FMOVSstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVSstoreidx (SLLconst [2] idx) ptr val mem) // result: (FMOVSstoreidx4 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64FMOVSstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSstoreidx4(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSstoreidx4 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<2) // result: (FMOVSstore [int32(c)<<2] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 2)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMULD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMULD (FNEGD x) y) // result: (FNMULD x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGD { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FNMULD) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FMULS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMULS (FNEGS x) y) // result: (FNMULS x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGS { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FNMULS) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FNEGD(v *Value) bool { v_0 := v.Args[0] // match: (FNEGD (FMULD x y)) // result: (FNMULD x y) for { if v_0.Op != OpARM64FMULD { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FNMULD) v.AddArg2(x, y) return true } // match: (FNEGD (FNMULD x y)) // result: (FMULD x y) for { if v_0.Op != OpARM64FNMULD { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FMULD) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64FNEGS(v *Value) bool { v_0 := v.Args[0] // match: (FNEGS (FMULS x y)) // result: (FNMULS x y) for { if v_0.Op != OpARM64FMULS { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FNMULS) v.AddArg2(x, y) return true } // match: (FNEGS (FNMULS x y)) // result: (FMULS x y) for { if v_0.Op != OpARM64FNMULS { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FMULS) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64FNMULD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FNMULD (FNEGD x) y) // result: (FMULD x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGD { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FMULD) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FNMULS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FNMULS (FNEGS x) y) // result: (FMULS x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGS { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FMULS) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FSUBD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FSUBD a (FMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBD a x y) for { a := v_0 if v_1.Op != OpARM64FMULD { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMSUBD) v.AddArg3(a, x, y) return true } // match: (FSUBD (FMULD x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMSUBD a x y) for { if v_0.Op != OpARM64FMULD { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMSUBD) v.AddArg3(a, x, y) return true } // match: (FSUBD a (FNMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDD a x y) for { a := v_0 if v_1.Op != OpARM64FNMULD { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMADDD) v.AddArg3(a, x, y) return true } // match: (FSUBD (FNMULD x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMADDD a x y) for { if v_0.Op != OpARM64FNMULD { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMADDD) v.AddArg3(a, x, y) return true } return false } func rewriteValueARM64_OpARM64FSUBS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FSUBS a (FMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBS a x y) for { a := v_0 if v_1.Op != OpARM64FMULS { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMSUBS) v.AddArg3(a, x, y) return true } // match: (FSUBS (FMULS x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMSUBS a x y) for { if v_0.Op != OpARM64FMULS { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMSUBS) v.AddArg3(a, x, y) return true } // match: (FSUBS a (FNMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDS a x y) for { a := v_0 if v_1.Op != OpARM64FNMULS { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMADDS) v.AddArg3(a, x, y) return true } // match: (FSUBS (FNMULS x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMADDS a x y) for { if v_0.Op != OpARM64FNMULS { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMADDS) v.AddArg3(a, x, y) return true } return false } func rewriteValueARM64_OpARM64GreaterEqual(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (GreaterEqual (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterEqual (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqual (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterEqual (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqual (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqualNoov (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqualNoov (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ge())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ge())) return true } // match: (GreaterEqual (InvertFlags x)) // result: (LessEqual x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessEqual) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterEqualF(v *Value) bool { v_0 := v.Args[0] // match: (GreaterEqualF (InvertFlags x)) // result: (LessEqualF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessEqualF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterEqualU(v *Value) bool { v_0 := v.Args[0] // match: (GreaterEqualU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.uge())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.uge())) return true } // match: (GreaterEqualU (InvertFlags x)) // result: (LessEqualU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessEqualU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterThan(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (GreaterThan (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterThan (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterThan (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterThan (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterThan (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterThan (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterThan (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterThan (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterThan (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.gt())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.gt())) return true } // match: (GreaterThan (InvertFlags x)) // result: (LessThan x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessThan) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterThanF(v *Value) bool { v_0 := v.Args[0] // match: (GreaterThanF (InvertFlags x)) // result: (LessThanF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessThanF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterThanU(v *Value) bool { v_0 := v.Args[0] // match: (GreaterThanU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ugt())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ugt())) return true } // match: (GreaterThanU (InvertFlags x)) // result: (LessThanU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessThanU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LDP(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (LDP [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (LDP [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64LDP) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (LDP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (LDP [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64LDP) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64LessEqual(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (LessEqual (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessEqual (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessEqual (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessEqual (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessEqual (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessEqual (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessEqual (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessEqual (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessEqual (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.le())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.le())) return true } // match: (LessEqual (InvertFlags x)) // result: (GreaterEqual x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterEqual) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessEqualF(v *Value) bool { v_0 := v.Args[0] // match: (LessEqualF (InvertFlags x)) // result: (GreaterEqualF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterEqualF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessEqualU(v *Value) bool { v_0 := v.Args[0] // match: (LessEqualU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ule())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ule())) return true } // match: (LessEqualU (InvertFlags x)) // result: (GreaterEqualU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterEqualU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessThan(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (LessThan (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessThan (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessThan (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessThan (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessThan (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (LessThanNoov (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (LessThanNoov (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.lt())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.lt())) return true } // match: (LessThan (InvertFlags x)) // result: (GreaterThan x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterThan) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessThanF(v *Value) bool { v_0 := v.Args[0] // match: (LessThanF (InvertFlags x)) // result: (GreaterThanF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterThanF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessThanU(v *Value) bool { v_0 := v.Args[0] // match: (LessThanU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ult())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ult())) return true } // match: (LessThanU (InvertFlags x)) // result: (GreaterThanU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterThanU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MADD(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MADD a x (MOVDconst [-1])) // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != -1 { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADD a _ (MOVDconst [0])) // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MADD a x (MOVDconst [1])) // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 1 { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADD a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADD a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [-1]) x) // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { break } x := v_2 v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADD a (MOVDconst [0]) _) // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MADD a (MOVDconst [1]) x) // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } x := v_2 v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADD a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADD a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD (MOVDconst [c]) x y) // result: (ADDconst [c] (MUL x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MADD a (MOVDconst [c]) (MOVDconst [d])) // result: (ADDconst [c*d] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c * d) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MADDW(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MADDW a x (MOVDconst [c])) // cond: int32(c)==-1 // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == -1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADDW a _ (MOVDconst [c])) // cond: int32(c)==0 // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MADDW a x (MOVDconst [c])) // cond: int32(c)==1 // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADDW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADDW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: int32(c)==-1 // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == -1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADDW a (MOVDconst [c]) _) // cond: int32(c)==0 // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: int32(c)==1 // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == 1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW (MOVDconst [c]) x y) // result: (ADDconst [c] (MULW x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MADDW a (MOVDconst [c]) (MOVDconst [d])) // result: (ADDconst [int64(int32(c)*int32(d))] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) * int32(d))) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MNEG(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MNEG x (MOVDconst [-1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { continue } v.copyOf(x) return true } break } // match: (MNEG _ (MOVDconst [0])) // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MNEG x (MOVDconst [1])) // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (NEG (SLLconst [log64(c)] x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c)) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c >= 3 // result: (NEG (ADDshiftLL x x [log64(c-1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c >= 7 // result: (NEG (ADDshiftLL (NEG x) x [log64(c+1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SLLconst [log64(c/3)] (SUBshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (NEG (SLLconst [log64(c/5)] (ADDshiftLL x x [2]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 5)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(2) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SLLconst [log64(c/7)] (SUBshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (NEG (SLLconst [log64(c/9)] (ADDshiftLL x x [3]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 9)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(3) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEG (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [-c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-c * d) return true } break } return false } func rewriteValueARM64_OpARM64MNEGW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MNEGW x (MOVDconst [c])) // cond: int32(c)==-1 // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == -1) { continue } v.copyOf(x) return true } break } // match: (MNEGW _ (MOVDconst [c])) // cond: int32(c)==0 // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: int32(c)==1 // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 1) { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (NEG (SLLconst [log64(c)] x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c)) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c) >= 3 // result: (NEG (ADDshiftLL x x [log64(c-1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c) >= 7 // result: (NEG (ADDshiftLL (NEG x) x [log64(c+1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SLLconst [log64(c/3)] (SUBshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (NEG (SLLconst [log64(c/5)] (ADDshiftLL x x [2]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 5)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(2) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SLLconst [log64(c/7)] (SUBshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (NEG (SLLconst [log64(c/9)] (ADDshiftLL x x [3]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 9)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(3) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEGW (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [-int64(int32(c)*int32(d))]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-int64(int32(c) * int32(d))) return true } break } return false } func rewriteValueARM64_OpARM64MOD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOD (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [c%d]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c % d) return true } return false } func rewriteValueARM64_OpARM64MODW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MODW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(int32(c)%int32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) % int32(d))) return true } return false } func rewriteValueARM64_OpARM64MOVBUload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBUload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBUload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVBUloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBUloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBUload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVBUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read8(sym, int64(off)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read8(sym, int64(off)))) return true } return false } func rewriteValueARM64_OpARM64MOVBUloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBUloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVBUload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBUloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVBUload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBUloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVBUreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVBUreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<8-1)] x) for { if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<8 - 1)) v.AddArg(x) return true } // match: (MOVBUreg (MOVDconst [c])) // result: (MOVDconst [int64(uint8(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint8(c))) return true } // match: (MOVBUreg x:(Equal _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64Equal { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(NotEqual _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64NotEqual { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessThan _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessThan { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessThanU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessThanU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessThanF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessThanF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessEqual _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessEqual { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessEqualU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessEqualU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessEqualF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessEqualF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterThan _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterThan { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterThanU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterThanU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterThanF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterThanF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterEqual _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterEqual { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterEqualU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterEqualU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterEqualF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterEqualF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg (SLLconst [lc] x)) // cond: lc >= 8 // result: (MOVDconst [0]) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) if !(lc >= 8) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVBUreg (SLLconst [lc] x)) // cond: lc < 8 // result: (UBFIZ [armBFAuxInt(lc, 8-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 8) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 8-lc)) v.AddArg(x) return true } // match: (MOVBUreg (SRLconst [rc] x)) // cond: rc < 8 // result: (UBFX [armBFAuxInt(rc, 8)] x) for { if v_0.Op != OpARM64SRLconst { break } rc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(rc < 8) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8)) v.AddArg(x) return true } // match: (MOVBUreg (UBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 8 // result: (UBFX [bfc] x) for { if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 8) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVBloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVBloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVBload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVBload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVBreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVBreg x:(MOVBload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBreg x:(MOVBloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBreg x:(MOVBreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBreg (MOVDconst [c])) // result: (MOVDconst [int64(int8(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int8(c))) return true } // match: (MOVBreg (ANDconst x [c])) // cond: uint64(c) & uint64(0xffffffffffffff80) == 0 // result: (ANDconst x [c]) for { t := v.Type if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(uint64(c)&uint64(0xffffffffffffff80) == 0) { break } v.reset(OpARM64ANDconst) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (MOVBreg (SLLconst [lc] x)) // cond: lc < 8 // result: (SBFIZ [armBFAuxInt(lc, 8-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 8) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 8-lc)) v.AddArg(x) return true } // match: (MOVBreg (SBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 8 // result: (SBFX [bfc] x) for { if v_0.Op != OpARM64SBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 8) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVBstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVBstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [i] {s} ptr0 (SRLconst [8] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] w) x:(MOVBstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { continue } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVBstore [i] {s} ptr0 (UBFX [armBFAuxInt(8, 8)] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 8) { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 8)] w) x:(MOVBstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 8) { continue } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVBstore [i] {s} ptr0 (UBFX [armBFAuxInt(8, 24)] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 24) { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 24)] w) x:(MOVBstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 24) { continue } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVBstore [i] {s} ptr0 (SRLconst [8] (MOVDreg w)) x:(MOVBstore [i-1] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { break } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { continue } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVBstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVBstore [i-1] {s} ptr1 w0:(SRLconst [j-8] w) mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst { break } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] w0 := x.Args[1] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w0 mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst { continue } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w0, mem) return true } break } // match: (MOVBstore [i] {s} ptr0 (UBFX [bfc] w) x:(MOVBstore [i-1] {s} ptr1 w0:(UBFX [bfc2] w) mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && bfc.getARM64BFwidth() == 32 - bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32 - bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb() - 8 && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] w0 := x.Args[1] if w0.Op != OpARM64UBFX { break } bfc2 := auxIntToArm64BitField(w0.AuxInt) if w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && bfc.getARM64BFwidth() == 32-bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32-bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb()-8 && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [bfc] w) x:(MOVBstoreidx ptr1 idx1 w0:(UBFX [bfc2] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && bfc.getARM64BFwidth() == 32 - bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32 - bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb() - 8 && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w0 mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64UBFX { continue } bfc := auxIntToArm64BitField(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64UBFX { continue } bfc2 := auxIntToArm64BitField(w0.AuxInt) if w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && bfc.getARM64BFwidth() == 32-bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32-bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb()-8 && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w0, mem) return true } break } // match: (MOVBstore [i] {s} ptr0 (SRLconst [j] (MOVDreg w)) x:(MOVBstore [i-1] {s} ptr1 w0:(SRLconst [j-8] (MOVDreg w)) mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstore [i-1] {s} ptr0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst { break } j := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { break } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] w0 := x.Args[1] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 { break } w0_0 := w0.Args[0] if w0_0.Op != OpARM64MOVDreg || w != w0_0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v.AddArg3(ptr0, w0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] (MOVDreg w)) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr1 idx1 w0 mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst { continue } j := auxIntToInt64(v_1.AuxInt) v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { continue } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 { continue } w0_0 := w0.Args[0] if w0_0.Op != OpARM64MOVDreg || w != w0_0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr1, idx1, w0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] w) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] w) x3:(MOVBstore [i-4] {s} ptr (SRLconst [32] w) x4:(MOVBstore [i-5] {s} ptr (SRLconst [40] w) x5:(MOVBstore [i-6] {s} ptr (SRLconst [48] w) x6:(MOVBstore [i-7] {s} ptr (SRLconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVDstore [i-7] {s} ptr (REV w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if ptr != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpARM64MOVBstore || auxIntToInt32(x3.AuxInt) != i-4 || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] if ptr != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpARM64SRLconst || auxIntToInt64(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x4 := x3.Args[2] if x4.Op != OpARM64MOVBstore || auxIntToInt32(x4.AuxInt) != i-5 || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] if ptr != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpARM64SRLconst || auxIntToInt64(x4_1.AuxInt) != 40 || w != x4_1.Args[0] { break } x5 := x4.Args[2] if x5.Op != OpARM64MOVBstore || auxIntToInt32(x5.AuxInt) != i-6 || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] if ptr != x5.Args[0] { break } x5_1 := x5.Args[1] if x5_1.Op != OpARM64SRLconst || auxIntToInt64(x5_1.AuxInt) != 48 || w != x5_1.Args[0] { break } x6 := x5.Args[2] if x6.Op != OpARM64MOVBstore || auxIntToInt32(x6.AuxInt) != i-7 || auxToSym(x6.Aux) != s { break } mem := x6.Args[2] if ptr != x6.Args[0] { break } x6_1 := x6.Args[1] if x6_1.Op != OpARM64SRLconst || auxIntToInt64(x6_1.AuxInt) != 56 || w != x6_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(i - 7) v.Aux = symToAux(s) v0 := b.NewValue0(x6.Pos, OpARM64REV, typ.UInt64) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [7] {s} p w x0:(MOVBstore [6] {s} p (SRLconst [8] w) x1:(MOVBstore [5] {s} p (SRLconst [16] w) x2:(MOVBstore [4] {s} p (SRLconst [24] w) x3:(MOVBstore [3] {s} p (SRLconst [32] w) x4:(MOVBstore [2] {s} p (SRLconst [40] w) x5:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [48] w) x6:(MOVBstoreidx ptr0 idx0 (SRLconst [56] w) mem)))))))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6) // result: (MOVDstoreidx ptr0 idx0 (REV w) mem) for { if auxIntToInt32(v.AuxInt) != 7 { break } s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 6 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 5 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if p != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != 4 || auxToSym(x2.Aux) != s { break } _ = x2.Args[2] if p != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 || w != x2_1.Args[0] { break } x3 := x2.Args[2] if x3.Op != OpARM64MOVBstore || auxIntToInt32(x3.AuxInt) != 3 || auxToSym(x3.Aux) != s { break } _ = x3.Args[2] if p != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpARM64SRLconst || auxIntToInt64(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { break } x4 := x3.Args[2] if x4.Op != OpARM64MOVBstore || auxIntToInt32(x4.AuxInt) != 2 || auxToSym(x4.Aux) != s { break } _ = x4.Args[2] if p != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpARM64SRLconst || auxIntToInt64(x4_1.AuxInt) != 40 || w != x4_1.Args[0] { break } x5 := x4.Args[2] if x5.Op != OpARM64MOVBstore || auxIntToInt32(x5.AuxInt) != 1 || auxToSym(x5.Aux) != s { break } _ = x5.Args[2] p1 := x5.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 x5_1 := x5.Args[1] if x5_1.Op != OpARM64SRLconst || auxIntToInt64(x5_1.AuxInt) != 48 || w != x5_1.Args[0] { continue } x6 := x5.Args[2] if x6.Op != OpARM64MOVBstoreidx { continue } mem := x6.Args[3] ptr0 := x6.Args[0] idx0 := x6.Args[1] x6_2 := x6.Args[2] if x6_2.Op != OpARM64SRLconst || auxIntToInt64(x6_2.AuxInt) != 56 || w != x6_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6)) { continue } v.reset(OpARM64MOVDstoreidx) v0 := b.NewValue0(x5.Pos, OpARM64REV, typ.UInt64) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstore [i-2] {s} ptr (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstore [i-3] {s} ptr (UBFX [armBFAuxInt(24, 8)] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVWstore [i-3] {s} ptr (REVW w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if ptr != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64UBFX || auxIntToArm64BitField(x0_1.AuxInt) != armBFAuxInt(8, 24) || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64UBFX || auxIntToArm64BitField(x1_1.AuxInt) != armBFAuxInt(16, 16) || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { break } mem := x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64UBFX || auxIntToArm64BitField(x2_1.AuxInt) != armBFAuxInt(24, 8) || w != x2_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 3) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(24, 8)] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2) // result: (MOVWstoreidx ptr0 idx0 (REVW w) mem) for { if auxIntToInt32(v.AuxInt) != 3 { break } s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 2 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64UBFX || auxIntToArm64BitField(x0_1.AuxInt) != armBFAuxInt(8, 24) || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 x1_1 := x1.Args[1] if x1_1.Op != OpARM64UBFX || auxIntToArm64BitField(x1_1.AuxInt) != armBFAuxInt(16, 16) || w != x1_1.Args[0] { continue } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstoreidx { continue } mem := x2.Args[3] ptr0 := x2.Args[0] idx0 := x2.Args[1] x2_2 := x2.Args[2] if x2_2.Op != OpARM64UBFX || auxIntToArm64BitField(x2_2.AuxInt) != armBFAuxInt(24, 8) || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2)) { continue } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(x1.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] (MOVDreg w)) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] (MOVDreg w)) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVWstore [i-3] {s} ptr (REVW w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if ptr != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 { break } x0_1_0 := x0_1.Args[0] if x0_1_0.Op != OpARM64MOVDreg || w != x0_1_0.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 { break } x1_1_0 := x1_1.Args[0] if x1_1_0.Op != OpARM64MOVDreg || w != x1_1_0.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { break } mem := x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 { break } x2_1_0 := x2_1.Args[0] if x2_1_0.Op != OpARM64MOVDreg || w != x2_1_0.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 3) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] (MOVDreg w)) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] (MOVDreg w)) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] (MOVDreg w)) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2) // result: (MOVWstoreidx ptr0 idx0 (REVW w) mem) for { if auxIntToInt32(v.AuxInt) != 3 { break } s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 2 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 { break } x0_1_0 := x0_1.Args[0] if x0_1_0.Op != OpARM64MOVDreg || w != x0_1_0.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 x1_1 := x1.Args[1] if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 { continue } x1_1_0 := x1_1.Args[0] if x1_1_0.Op != OpARM64MOVDreg || w != x1_1_0.Args[0] { continue } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstoreidx { continue } mem := x2.Args[3] ptr0 := x2.Args[0] idx0 := x2.Args[1] x2_2 := x2.Args[2] if x2_2.Op != OpARM64SRLconst || auxIntToInt64(x2_2.AuxInt) != 24 { continue } x2_2_0 := x2_2.Args[0] if x2_2_0.Op != OpARM64MOVDreg || w != x2_2_0.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2)) { continue } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(x1.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] w) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVWstore [i-3] {s} ptr (REVW w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if ptr != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { break } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { break } mem := x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 || w != x2_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 3) v.Aux = symToAux(s) v0 := b.NewValue0(x2.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] w) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2) // result: (MOVWstoreidx ptr0 idx0 (REVW w) mem) for { if auxIntToInt32(v.AuxInt) != 3 { break } s := auxToSym(v.Aux) p := v_0 w := v_1 x0 := v_2 if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 2 || auxToSym(x0.Aux) != s { break } _ = x0.Args[2] if p != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { break } x1 := x0.Args[2] if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { break } _ = x1.Args[2] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 x1_1 := x1.Args[1] if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { continue } x2 := x1.Args[2] if x2.Op != OpARM64MOVBstoreidx { continue } mem := x2.Args[3] ptr0 := x2.Args[0] idx0 := x2.Args[1] x2_2 := x2.Args[2] if x2_2.Op != OpARM64SRLconst || auxIntToInt64(x2_2.AuxInt) != 24 || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2)) { continue } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(x1.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if ptr != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpARM64SRLconst || auxIntToInt64(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr1 := v_0_0 idx1 := v_0_1 w := v_1 x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr0 := x.Args[0] idx0 := x.Args[1] x_2 := x.Args[2] if x_2.Op != OpARM64SRLconst || auxIntToInt64(x_2.AuxInt) != 8 || w != x_2.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 8)] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if ptr != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpARM64UBFX || auxIntToArm64BitField(x_1.AuxInt) != armBFAuxInt(8, 8) || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 8)] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr1 := v_0_0 idx1 := v_0_1 w := v_1 x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr0 := x.Args[0] idx0 := x.Args[1] x_2 := x.Args[2] if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 8) || w != x_2.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if ptr != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpARM64SRLconst || auxIntToInt64(x_1.AuxInt) != 8 { break } x_1_0 := x_1.Args[0] if x_1_0.Op != OpARM64MOVDreg || w != x_1_0.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] (MOVDreg w)) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr1 := v_0_0 idx1 := v_0_1 w := v_1 x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr0 := x.Args[0] idx0 := x.Args[1] x_2 := x.Args[2] if x_2.Op != OpARM64SRLconst || auxIntToInt64(x_2.AuxInt) != 8 { continue } x_2_0 := x_2.Args[0] if x_2_0.Op != OpARM64MOVDreg || w != x_2_0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 24)] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 w := v_1 x := v_2 if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { break } mem := x.Args[2] if ptr != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpARM64UBFX || auxIntToArm64BitField(x_1.AuxInt) != armBFAuxInt(8, 24) || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(i - 1) v.Aux = symToAux(s) v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg3(ptr, v0, mem) return true } // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 24)] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr1 := v_0_0 idx1 := v_0_1 w := v_1 x := v_2 if x.Op != OpARM64MOVBstoreidx { continue } mem := x.Args[3] ptr0 := x.Args[0] idx0 := x.Args[1] x_2 := x.Args[2] if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 24) || w != x_2.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstoreidx) v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg4(ptr0, idx0, v0, mem) return true } break } return false } func rewriteValueARM64_OpARM64MOVBstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MOVBstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVBstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVBstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVBstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVBstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVBstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBstoreidx ptr idx (MOVBreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVBUreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVHreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVHUreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVWreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVWUreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr (ADDconst [1] idx) (SRLconst [8] w) x:(MOVBstoreidx ptr idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstoreidx ptr idx w mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] if v_2.Op != OpARM64SRLconst || auxIntToInt64(v_2.AuxInt) != 8 { break } w := v_2.Args[0] x := v_3 if x.Op != OpARM64MOVBstoreidx { break } mem := x.Args[3] if ptr != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, w, mem) return true } // match: (MOVBstoreidx ptr (ADDconst [3] idx) w x0:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(24, 8)] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVWstoreidx ptr idx (REVW w) mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] w := v_2 x0 := v_3 if x0.Op != OpARM64MOVBstoreidx { break } _ = x0.Args[3] if ptr != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 2 || idx != x0_1.Args[0] { break } x0_2 := x0.Args[2] if x0_2.Op != OpARM64UBFX || auxIntToArm64BitField(x0_2.AuxInt) != armBFAuxInt(8, 24) || w != x0_2.Args[0] { break } x1 := x0.Args[3] if x1.Op != OpARM64MOVBstoreidx { break } _ = x1.Args[3] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] { break } x1_2 := x1.Args[2] if x1_2.Op != OpARM64UBFX || auxIntToArm64BitField(x1_2.AuxInt) != armBFAuxInt(16, 16) || w != x1_2.Args[0] { break } x2 := x1.Args[3] if x2.Op != OpARM64MOVBstoreidx { break } mem := x2.Args[3] if ptr != x2.Args[0] || idx != x2.Args[1] { break } x2_2 := x2.Args[2] if x2_2.Op != OpARM64UBFX || auxIntToArm64BitField(x2_2.AuxInt) != armBFAuxInt(24, 8) || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(v.Pos, OpARM64REVW, typ.UInt32) v0.AddArg(w) v.AddArg4(ptr, idx, v0, mem) return true } // match: (MOVBstoreidx ptr idx w x0:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr (ADDconst [3] idx) (UBFX [armBFAuxInt(24, 8)] w) mem)))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) // result: (MOVWstoreidx ptr idx w mem) for { ptr := v_0 idx := v_1 w := v_2 x0 := v_3 if x0.Op != OpARM64MOVBstoreidx { break } _ = x0.Args[3] if ptr != x0.Args[0] { break } x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 1 || idx != x0_1.Args[0] { break } x0_2 := x0.Args[2] if x0_2.Op != OpARM64UBFX || auxIntToArm64BitField(x0_2.AuxInt) != armBFAuxInt(8, 24) || w != x0_2.Args[0] { break } x1 := x0.Args[3] if x1.Op != OpARM64MOVBstoreidx { break } _ = x1.Args[3] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 2 || idx != x1_1.Args[0] { break } x1_2 := x1.Args[2] if x1_2.Op != OpARM64UBFX || auxIntToArm64BitField(x1_2.AuxInt) != armBFAuxInt(16, 16) || w != x1_2.Args[0] { break } x2 := x1.Args[3] if x2.Op != OpARM64MOVBstoreidx { break } mem := x2.Args[3] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 3 || idx != x2_1.Args[0] { break } x2_2 := x2.Args[2] if x2_2.Op != OpARM64UBFX || auxIntToArm64BitField(x2_2.AuxInt) != armBFAuxInt(24, 8) || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { break } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, w, mem) return true } // match: (MOVBstoreidx ptr (ADDconst [1] idx) w x:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(8, 8)] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstoreidx ptr idx (REV16W w) mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] w := v_2 x := v_3 if x.Op != OpARM64MOVBstoreidx { break } mem := x.Args[3] if ptr != x.Args[0] || idx != x.Args[1] { break } x_2 := x.Args[2] if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 8) || w != x_2.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstoreidx) v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) v0.AddArg(w) v.AddArg4(ptr, idx, v0, mem) return true } // match: (MOVBstoreidx ptr idx w x:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 8)] w) mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstoreidx ptr idx w mem) for { ptr := v_0 idx := v_1 w := v_2 x := v_3 if x.Op != OpARM64MOVBstoreidx { break } mem := x.Args[3] if ptr != x.Args[0] { break } x_1 := x.Args[1] if x_1.Op != OpARM64ADDconst || auxIntToInt64(x_1.AuxInt) != 1 || idx != x_1.Args[0] { break } x_2 := x.Args[2] if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 8) || w != x_2.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, w, mem) return true } return false } func rewriteValueARM64_OpARM64MOVBstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVBstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBstorezero [i] {s} ptr0 x:(MOVBstorezero [j] {s} ptr1 mem)) // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),1) && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVHstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 x := v_1 if x.Op != OpARM64MOVBstorezero { break } j := auxIntToInt32(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] ptr1 := x.Args[0] if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 1) && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) v.Aux = symToAux(s) v.AddArg2(ptr0, mem) return true } // match: (MOVBstorezero [1] {s} (ADD ptr0 idx0) x:(MOVBstorezeroidx ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVHstorezeroidx ptr1 idx1 mem) for { if auxIntToInt32(v.AuxInt) != 1 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 x := v_1 if x.Op != OpARM64MOVBstorezeroidx { continue } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVHstorezeroidx) v.AddArg3(ptr1, idx1, mem) return true } break } return false } func rewriteValueARM64_OpARM64MOVBstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVBstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVBstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVBstorezeroidx ptr (ADDconst [1] idx) x:(MOVBstorezeroidx ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVHstorezeroidx ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVBstorezeroidx { break } mem := x.Args[2] if ptr != x.Args[0] || idx != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVHstorezeroidx) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr val _)) // result: (FMOVDfpgp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVDfpgp) v.AddArg(val) return true } // match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVDload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDloadidx8 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVDload [off] {sym} ptr (MOVDstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVDload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueARM64_OpARM64MOVDloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVDload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVDloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVDload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVDloadidx ptr (SLLconst [3] idx) mem) // result: (MOVDloadidx8 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDloadidx (SLLconst [3] idx) ptr mem) // result: (MOVDloadidx8 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDloadidx ptr idx (MOVDstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVDloadidx8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDloadidx8 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<3) // result: (MOVDload [int32(c)<<3] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 3)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg2(ptr, mem) return true } // match: (MOVDloadidx8 ptr idx (MOVDstorezeroidx8 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDstorezeroidx8 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVDnop(v *Value) bool { v_0 := v.Args[0] // match: (MOVDnop (MOVDconst [c])) // result: (MOVDconst [c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValueARM64_OpARM64MOVDreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVDreg x) // cond: x.Uses == 1 // result: (MOVDnop x) for { x := v_0 if !(x.Uses == 1) { break } v.reset(OpARM64MOVDnop) v.AddArg(x) return true } // match: (MOVDreg (MOVDconst [c])) // result: (MOVDconst [c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValueARM64_OpARM64MOVDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVDstore [off] {sym} ptr (FMOVDfpgp val) mem) // result: (FMOVDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVDfpgp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVDstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVDstoreidx8 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVDstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVDstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVDstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVDstoreidx ptr (SLLconst [3] idx) val mem) // result: (MOVDstoreidx8 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64MOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstoreidx (SLLconst [3] idx) ptr val mem) // result: (MOVDstoreidx8 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVDstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVDstorezeroidx) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstoreidx8(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstoreidx8 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<3) // result: (MOVDstore [int32(c)<<3] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 3)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstoreidx8 ptr idx (MOVDconst [0]) mem) // result: (MOVDstorezeroidx8 ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDstorezero [off] {sym} (ADDshiftLL [3] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDstorezeroidx8 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDstorezero [i] {s} ptr0 x:(MOVDstorezero [j] {s} ptr1 mem)) // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),8) && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVQstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 x := v_1 if x.Op != OpARM64MOVDstorezero { break } j := auxIntToInt32(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] ptr1 := x.Args[0] if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 8) && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) v.Aux = symToAux(s) v.AddArg2(ptr0, mem) return true } // match: (MOVDstorezero [8] {s} p0:(ADD ptr0 idx0) x:(MOVDstorezeroidx ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVQstorezero [0] {s} p0 mem) for { if auxIntToInt32(v.AuxInt) != 8 { break } s := auxToSym(v.Aux) p0 := v_0 if p0.Op != OpARM64ADD { break } _ = p0.Args[1] p0_0 := p0.Args[0] p0_1 := p0.Args[1] for _i0 := 0; _i0 <= 1; _i0, p0_0, p0_1 = _i0+1, p0_1, p0_0 { ptr0 := p0_0 idx0 := p0_1 x := v_1 if x.Op != OpARM64MOVDstorezeroidx { continue } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(0) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } break } // match: (MOVDstorezero [8] {s} p0:(ADDshiftLL [3] ptr0 idx0) x:(MOVDstorezeroidx8 ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVQstorezero [0] {s} p0 mem) for { if auxIntToInt32(v.AuxInt) != 8 { break } s := auxToSym(v.Aux) p0 := v_0 if p0.Op != OpARM64ADDshiftLL || auxIntToInt64(p0.AuxInt) != 3 { break } idx0 := p0.Args[1] ptr0 := p0.Args[0] x := v_1 if x.Op != OpARM64MOVDstorezeroidx8 { break } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(0) v.Aux = symToAux(s) v.AddArg2(p0, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVDstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVDstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVDstorezeroidx ptr (SLLconst [3] idx) mem) // result: (MOVDstorezeroidx8 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDstorezeroidx (SLLconst [3] idx) ptr mem) // result: (MOVDstorezeroidx8 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstorezeroidx8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstorezeroidx8 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<3) // result: (MOVDstorezero [int32(c<<3)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 3)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(c << 3)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHUload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHUload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHUload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHUloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHUloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUload [off] {sym} (ADDshiftLL [1] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHUloadidx2 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVHUload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVHUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueARM64_OpARM64MOVHUloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHUloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVHUload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHUloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVHUload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHUloadidx ptr (SLLconst [1] idx) mem) // result: (MOVHUloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUloadidx ptr (ADD idx idx) mem) // result: (MOVHUloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } mem := v_2 v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUloadidx (ADD idx idx) ptr mem) // result: (MOVHUloadidx2 ptr idx mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 mem := v_2 v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHUloadidx2(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHUloadidx2 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<1) // result: (MOVHUload [int32(c)<<1] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(int32(c) << 1) v.AddArg2(ptr, mem) return true } // match: (MOVHUloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx2 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHUreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVHUreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<16-1)] x) for { if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<16 - 1)) v.AddArg(x) return true } // match: (MOVHUreg (MOVDconst [c])) // result: (MOVDconst [int64(uint16(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint16(c))) return true } // match: (MOVHUreg (SLLconst [lc] x)) // cond: lc >= 16 // result: (MOVDconst [0]) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) if !(lc >= 16) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVHUreg (SLLconst [lc] x)) // cond: lc < 16 // result: (UBFIZ [armBFAuxInt(lc, 16-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 16) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 16-lc)) v.AddArg(x) return true } // match: (MOVHUreg (SRLconst [rc] x)) // cond: rc < 16 // result: (UBFX [armBFAuxInt(rc, 16)] x) for { if v_0.Op != OpARM64SRLconst { break } rc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(rc < 16) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 16)) v.AddArg(x) return true } // match: (MOVHUreg (UBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 16 // result: (UBFX [bfc] x) for { if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 16) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVHload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHload [off] {sym} (ADDshiftLL [1] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHloadidx2 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVHload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVHload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVHload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHloadidx ptr (SLLconst [1] idx) mem) // result: (MOVHloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHloadidx ptr (ADD idx idx) mem) // result: (MOVHloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } mem := v_2 v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHloadidx (ADD idx idx) ptr mem) // result: (MOVHloadidx2 ptr idx mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 mem := v_2 v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHloadidx2(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHloadidx2 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<1) // result: (MOVHload [int32(c)<<1] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(int32(c) << 1) v.AddArg2(ptr, mem) return true } // match: (MOVHloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx2 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVHreg x:(MOVBload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg (MOVDconst [c])) // result: (MOVDconst [int64(int16(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int16(c))) return true } // match: (MOVHreg (ANDconst x [c])) // cond: uint64(c) & uint64(0xffffffffffff8000) == 0 // result: (ANDconst x [c]) for { t := v.Type if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(uint64(c)&uint64(0xffffffffffff8000) == 0) { break } v.reset(OpARM64ANDconst) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (MOVHreg (SLLconst [lc] x)) // cond: lc < 16 // result: (SBFIZ [armBFAuxInt(lc, 16-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 16) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 16-lc)) v.AddArg(x) return true } // match: (MOVHreg (SBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 16 // result: (SBFX [bfc] x) for { if v_0.Op != OpARM64SBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 16) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVHstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVHstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstore [off] {sym} (ADDshiftLL [1] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVHstoreidx2 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVHstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [i] {s} ptr0 (SRLconst [16] w) x:(MOVHstore [i-2] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVWstore [i-2] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [16] w) x:(MOVHstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVWstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { continue } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [16] w) x:(MOVHstoreidx2 ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx2 { break } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg(idx1) v.AddArg4(ptr1, v0, w, mem) return true } // match: (MOVHstore [i] {s} ptr0 (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstore [i-2] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVWstore [i-2] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(16, 16) { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVWstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(16, 16) { continue } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstoreidx2 ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(16, 16) { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx2 { break } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg(idx1) v.AddArg4(ptr1, v0, w, mem) return true } // match: (MOVHstore [i] {s} ptr0 (SRLconst [16] (MOVDreg w)) x:(MOVHstore [i-2] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVWstore [i-2] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { break } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [16] (MOVDreg w)) x:(MOVHstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVWstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { continue } v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { continue } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [16] (MOVDreg w)) x:(MOVHstoreidx2 ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { break } v_1_0 := v_1.Args[0] if v_1_0.Op != OpARM64MOVDreg { break } w := v_1_0.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx2 { break } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg(idx1) v.AddArg4(ptr1, v0, w, mem) return true } // match: (MOVHstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVHstore [i-2] {s} ptr1 w0:(SRLconst [j-16] w) mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVWstore [i-2] {s} ptr0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst { break } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] w0 := x.Args[1] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(i - 2) v.Aux = symToAux(s) v.AddArg3(ptr0, w0, mem) return true } // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVHstoreidx ptr1 idx1 w0:(SRLconst [j-16] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVWstoreidx ptr1 idx1 w0 mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst { continue } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr1, idx1, w0, mem) return true } break } // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [j] w) x:(MOVHstoreidx2 ptr1 idx1 w0:(SRLconst [j-16] w) mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w0 mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] if v_1.Op != OpARM64SRLconst { break } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstoreidx2 { break } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVWstoreidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg(idx1) v.AddArg4(ptr1, v0, w0, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVHstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVHstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVHstoreidx ptr (SLLconst [1] idx) val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx ptr (ADD idx idx) val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx (SLLconst [1] idx) ptr val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx (ADD idx idx) ptr val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVHstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVHstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstoreidx ptr idx (MOVHreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr idx (MOVHUreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr idx (MOVWreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr idx (MOVWUreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr (ADDconst [2] idx) (SRLconst [16] w) x:(MOVHstoreidx ptr idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstoreidx ptr idx w mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] if v_2.Op != OpARM64SRLconst || auxIntToInt64(v_2.AuxInt) != 16 { break } w := v_2.Args[0] x := v_3 if x.Op != OpARM64MOVHstoreidx { break } mem := x.Args[3] if ptr != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, w, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstoreidx2(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstoreidx2 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<1) // result: (MOVHstore [int32(c)<<1] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(int32(c) << 1) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVDconst [0]) mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVHreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVHUreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVWreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVWUreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVHstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezero [off] {sym} (ADDshiftLL [1] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHstorezeroidx2 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezero [i] {s} ptr0 x:(MOVHstorezero [j] {s} ptr1 mem)) // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),2) && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVWstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 x := v_1 if x.Op != OpARM64MOVHstorezero { break } j := auxIntToInt32(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] ptr1 := x.Args[0] if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 2) && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) v.Aux = symToAux(s) v.AddArg2(ptr0, mem) return true } // match: (MOVHstorezero [2] {s} (ADD ptr0 idx0) x:(MOVHstorezeroidx ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVWstorezeroidx ptr1 idx1 mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 x := v_1 if x.Op != OpARM64MOVHstorezeroidx { continue } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVWstorezeroidx) v.AddArg3(ptr1, idx1, mem) return true } break } // match: (MOVHstorezero [2] {s} (ADDshiftLL [1] ptr0 idx0) x:(MOVHstorezeroidx2 ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVWstorezeroidx ptr1 (SLLconst [1] idx1) mem) for { if auxIntToInt32(v.AuxInt) != 2 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] x := v_1 if x.Op != OpARM64MOVHstorezeroidx2 { break } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVWstorezeroidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg(idx1) v.AddArg3(ptr1, v0, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVHstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVHstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVHstorezeroidx ptr (SLLconst [1] idx) mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx ptr (ADD idx idx) mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx (SLLconst [1] idx) ptr mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx (ADD idx idx) ptr mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx ptr (ADDconst [2] idx) x:(MOVHstorezeroidx ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVWstorezeroidx ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVHstorezeroidx { break } mem := x.Args[2] if ptr != x.Args[0] || idx != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVWstorezeroidx) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstorezeroidx2(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstorezeroidx2 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<1) // result: (MOVHstorezero [int32(c<<1)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(c << 1)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVQstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVQstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWUload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWUload [off] {sym} ptr (FMOVSstore [off] {sym} ptr val _)) // result: (FMOVSfpgp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVSfpgp) v.AddArg(val) return true } // match: (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWUload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWUload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWUloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWUloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUload [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWUloadidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWUloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWUload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVWUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueARM64_OpARM64MOVWUloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWUloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVWUload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWUloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVWUload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWUloadidx ptr (SLLconst [2] idx) mem) // result: (MOVWUloadidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWUloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUloadidx (SLLconst [2] idx) ptr mem) // result: (MOVWUloadidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVWUloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWUloadidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWUloadidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (MOVWUload [int32(c)<<2] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg2(ptr, mem) return true } // match: (MOVWUloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx4 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWUreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVWUreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUloadidx4 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUloadidx4 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<32-1)] x) for { if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<32 - 1)) v.AddArg(x) return true } // match: (MOVWUreg (MOVDconst [c])) // result: (MOVDconst [int64(uint32(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint32(c))) return true } // match: (MOVWUreg x) // cond: zeroUpper32Bits(x, 3) // result: x for { x := v_0 if !(zeroUpper32Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVWUreg (SLLconst [lc] x)) // cond: lc >= 32 // result: (MOVDconst [0]) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) if !(lc >= 32) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVWUreg (SLLconst [lc] x)) // cond: lc < 32 // result: (UBFIZ [armBFAuxInt(lc, 32-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 32) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 32-lc)) v.AddArg(x) return true } // match: (MOVWUreg (SRLconst [rc] x)) // cond: rc < 32 // result: (UBFX [armBFAuxInt(rc, 32)] x) for { if v_0.Op != OpARM64SRLconst { break } rc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(rc < 32) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 32)) v.AddArg(x) return true } // match: (MOVWUreg (UBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 32 // result: (UBFX [bfc] x) for { if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 32) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWload [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWloadidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVWload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVWload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWloadidx ptr (SLLconst [2] idx) mem) // result: (MOVWloadidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWloadidx (SLLconst [2] idx) ptr mem) // result: (MOVWloadidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVWloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWloadidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWloadidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (MOVWload [int32(c)<<2] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg2(ptr, mem) return true } // match: (MOVWloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx4 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVWreg x:(MOVBload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHUloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWloadidx4 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWloadidx4 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg (MOVDconst [c])) // result: (MOVDconst [int64(int32(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c))) return true } // match: (MOVWreg (ANDconst x [c])) // cond: uint64(c) & uint64(0xffffffff80000000) == 0 // result: (ANDconst x [c]) for { t := v.Type if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(uint64(c)&uint64(0xffffffff80000000) == 0) { break } v.reset(OpARM64ANDconst) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (MOVWreg (SLLconst [lc] x)) // cond: lc < 32 // result: (SBFIZ [armBFAuxInt(lc, 32-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 32) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 32-lc)) v.AddArg(x) return true } // match: (MOVWreg (SBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 32 // result: (SBFX [bfc] x) for { if v_0.Op != OpARM64SBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 32) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWstore [off] {sym} ptr (FMOVSfpgp val) mem) // result: (FMOVSstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVSfpgp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVWstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVWstoreidx4 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVWstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [i] {s} ptr0 (SRLconst [32] w) x:(MOVWstore [i-4] {s} ptr1 w mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVDstore [i-4] {s} ptr0 w mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(ptr0, w, mem) return true } // match: (MOVWstore [4] {s} (ADD ptr0 idx0) (SRLconst [32] w) x:(MOVWstoreidx ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVDstoreidx ptr1 idx1 w mem) for { if auxIntToInt32(v.AuxInt) != 4 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 32 { continue } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVDstoreidx) v.AddArg4(ptr1, idx1, w, mem) return true } break } // match: (MOVWstore [4] {s} (ADDshiftLL [2] ptr0 idx0) (SRLconst [32] w) x:(MOVWstoreidx4 ptr1 idx1 w mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVDstoreidx ptr1 (SLLconst [2] idx1) w mem) for { if auxIntToInt32(v.AuxInt) != 4 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 32 { break } w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstoreidx4 { break } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVDstoreidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg(idx1) v.AddArg4(ptr1, v0, w, mem) return true } // match: (MOVWstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVWstore [i-4] {s} ptr1 w0:(SRLconst [j-32] w) mem)) // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVDstore [i-4] {s} ptr0 w0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 if v_1.Op != OpARM64SRLconst { break } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { break } mem := x.Args[2] ptr1 := x.Args[0] w0 := x.Args[1] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(i - 4) v.Aux = symToAux(s) v.AddArg3(ptr0, w0, mem) return true } // match: (MOVWstore [4] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVWstoreidx ptr1 idx1 w0:(SRLconst [j-32] w) mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVDstoreidx ptr1 idx1 w0 mem) for { if auxIntToInt32(v.AuxInt) != 4 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 if v_1.Op != OpARM64SRLconst { continue } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstoreidx { continue } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVDstoreidx) v.AddArg4(ptr1, idx1, w0, mem) return true } break } // match: (MOVWstore [4] {s} (ADDshiftLL [2] ptr0 idx0) (SRLconst [j] w) x:(MOVWstoreidx4 ptr1 idx1 w0:(SRLconst [j-32] w) mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVDstoreidx ptr1 (SLLconst [2] idx1) w0 mem) for { if auxIntToInt32(v.AuxInt) != 4 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] if v_1.Op != OpARM64SRLconst { break } j := auxIntToInt64(v_1.AuxInt) w := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstoreidx4 { break } mem := x.Args[3] ptr1 := x.Args[0] idx1 := x.Args[1] w0 := x.Args[2] if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVDstoreidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg(idx1) v.AddArg4(ptr1, v0, w0, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVWstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVWstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVWstoreidx ptr (SLLconst [2] idx) val mem) // result: (MOVWstoreidx4 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstoreidx (SLLconst [2] idx) ptr val mem) // result: (MOVWstoreidx4 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVWstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVWstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstoreidx ptr idx (MOVWreg x) mem) // result: (MOVWstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVWstoreidx ptr idx (MOVWUreg x) mem) // result: (MOVWstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVWstoreidx ptr (ADDconst [4] idx) (SRLconst [32] w) x:(MOVWstoreidx ptr idx w mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVDstoreidx ptr idx w mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 4 { break } idx := v_1.Args[0] if v_2.Op != OpARM64SRLconst || auxIntToInt64(v_2.AuxInt) != 32 { break } w := v_2.Args[0] x := v_3 if x.Op != OpARM64MOVWstoreidx { break } mem := x.Args[3] if ptr != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVDstoreidx) v.AddArg4(ptr, idx, w, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstoreidx4(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreidx4 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<2) // result: (MOVWstore [int32(c)<<2] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstoreidx4 ptr idx (MOVDconst [0]) mem) // result: (MOVWstorezeroidx4 ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstoreidx4 ptr idx (MOVWreg x) mem) // result: (MOVWstoreidx4 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVWstoreidx4 ptr idx (MOVWUreg x) mem) // result: (MOVWstoreidx4 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstorezero [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWstorezeroidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstorezero [i] {s} ptr0 x:(MOVWstorezero [j] {s} ptr1 mem)) // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),4) && isSamePtr(ptr0, ptr1) && clobber(x) // result: (MOVDstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr0 := v_0 x := v_1 if x.Op != OpARM64MOVWstorezero { break } j := auxIntToInt32(x.AuxInt) if auxToSym(x.Aux) != s { break } mem := x.Args[1] ptr1 := x.Args[0] if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 4) && isSamePtr(ptr0, ptr1) && clobber(x)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) v.Aux = symToAux(s) v.AddArg2(ptr0, mem) return true } // match: (MOVWstorezero [4] {s} (ADD ptr0 idx0) x:(MOVWstorezeroidx ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) // result: (MOVDstorezeroidx ptr1 idx1 mem) for { if auxIntToInt32(v.AuxInt) != 4 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1] for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { ptr0 := v_0_0 idx0 := v_0_1 x := v_1 if x.Op != OpARM64MOVWstorezeroidx { continue } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { continue } v.reset(OpARM64MOVDstorezeroidx) v.AddArg3(ptr1, idx1, mem) return true } break } // match: (MOVWstorezero [4] {s} (ADDshiftLL [2] ptr0 idx0) x:(MOVWstorezeroidx4 ptr1 idx1 mem)) // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) // result: (MOVDstorezeroidx ptr1 (SLLconst [2] idx1) mem) for { if auxIntToInt32(v.AuxInt) != 4 { break } s := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx0 := v_0.Args[1] ptr0 := v_0.Args[0] x := v_1 if x.Op != OpARM64MOVWstorezeroidx4 { break } mem := x.Args[2] ptr1 := x.Args[0] idx1 := x.Args[1] if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { break } v.reset(OpARM64MOVDstorezeroidx) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg(idx1) v.AddArg3(ptr1, v0, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVWstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVWstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVWstorezeroidx ptr (SLLconst [2] idx) mem) // result: (MOVWstorezeroidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstorezeroidx (SLLconst [2] idx) ptr mem) // result: (MOVWstorezeroidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstorezeroidx ptr (ADDconst [4] idx) x:(MOVWstorezeroidx ptr idx mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVDstorezeroidx ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 4 { break } idx := v_1.Args[0] x := v_2 if x.Op != OpARM64MOVWstorezeroidx { break } mem := x.Args[2] if ptr != x.Args[0] || idx != x.Args[1] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVDstorezeroidx) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstorezeroidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstorezeroidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (MOVWstorezero [int32(c<<2)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(c << 2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MSUB(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MSUB a x (MOVDconst [-1])) // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != -1 { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUB a _ (MOVDconst [0])) // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MSUB a x (MOVDconst [1])) // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 1 { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUB a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUB a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [-1]) x) // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { break } x := v_2 v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUB a (MOVDconst [0]) _) // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MSUB a (MOVDconst [1]) x) // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } x := v_2 v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB (MOVDconst [c]) x y) // result: (ADDconst [c] (MNEG x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MNEG, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MSUB a (MOVDconst [c]) (MOVDconst [d])) // result: (SUBconst [c*d] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(c * d) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MSUBW(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MSUBW a x (MOVDconst [c])) // cond: int32(c)==-1 // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == -1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUBW a _ (MOVDconst [c])) // cond: int32(c)==0 // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: int32(c)==1 // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: int32(c)==-1 // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == -1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUBW a (MOVDconst [c]) _) // cond: int32(c)==0 // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: int32(c)==1 // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == 1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW (MOVDconst [c]) x y) // result: (ADDconst [c] (MNEGW x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MNEGW, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MSUBW a (MOVDconst [c]) (MOVDconst [d])) // result: (SUBconst [int64(int32(c)*int32(d))] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(int64(int32(c) * int32(d))) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MUL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MUL (NEG x) y) // result: (MNEG x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64NEG { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64MNEG) v.AddArg2(x, y) return true } break } // match: (MUL x (MOVDconst [-1])) // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MUL _ (MOVDconst [0])) // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MUL x (MOVDconst [1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { continue } v.copyOf(x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SLLconst [log64(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c >= 3 // result: (ADDshiftLL x x [log64(c-1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c - 1)) v.AddArg2(x, x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c >= 7 // result: (ADDshiftLL (NEG x) x [log64(c+1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c + 1)) v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v0.AddArg(x) v.AddArg2(v0, x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SLLconst [log64(c/3)] (ADDshiftLL x x [1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (SLLconst [log64(c/5)] (ADDshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SLLconst [log64(c/7)] (ADDshiftLL (NEG x) x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (SLLconst [log64(c/9)] (ADDshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MUL (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c * d) return true } break } return false } func rewriteValueARM64_OpARM64MULW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MULW (NEG x) y) // result: (MNEGW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64NEG { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64MNEGW) v.AddArg2(x, y) return true } break } // match: (MULW x (MOVDconst [c])) // cond: int32(c)==-1 // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == -1) { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MULW _ (MOVDconst [c])) // cond: int32(c)==0 // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: int32(c)==1 // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 1) { continue } v.copyOf(x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SLLconst [log64(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c) >= 3 // result: (ADDshiftLL x x [log64(c-1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c - 1)) v.AddArg2(x, x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c) >= 7 // result: (ADDshiftLL (NEG x) x [log64(c+1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c + 1)) v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v0.AddArg(x) v.AddArg2(v0, x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SLLconst [log64(c/3)] (ADDshiftLL x x [1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (SLLconst [log64(c/5)] (ADDshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SLLconst [log64(c/7)] (ADDshiftLL (NEG x) x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (SLLconst [log64(c/9)] (ADDshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MULW (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [int64(int32(c)*int32(d))]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) * int32(d))) return true } break } return false } func rewriteValueARM64_OpARM64MVN(v *Value) bool { v_0 := v.Args[0] // match: (MVN (XOR x y)) // result: (EON x y) for { if v_0.Op != OpARM64XOR { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64EON) v.AddArg2(x, y) return true } // match: (MVN (MOVDconst [c])) // result: (MOVDconst [^c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^c) return true } // match: (MVN x:(SLLconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftLL [c] y) for { x := v_0 if x.Op != OpARM64SLLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (MVN x:(SRLconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftRL [c] y) for { x := v_0 if x.Op != OpARM64SRLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (MVN x:(SRAconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftRA [c] y) for { x := v_0 if x.Op != OpARM64SRAconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (MVN x:(RORconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftRO [c] y) for { x := v_0 if x.Op != OpARM64RORconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64MVNshiftLL(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftLL (MOVDconst [c]) [d]) // result: (MOVDconst [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64MVNshiftRL(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftRL (MOVDconst [c]) [d]) // result: (MOVDconst [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64MVNshiftRO(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftRO (MOVDconst [c]) [d]) // result: (MOVDconst [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) return true } return false } func rewriteValueARM64_OpARM64NEG(v *Value) bool { v_0 := v.Args[0] // match: (NEG (MUL x y)) // result: (MNEG x y) for { if v_0.Op != OpARM64MUL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MNEG) v.AddArg2(x, y) return true } // match: (NEG (MULW x y)) // result: (MNEGW x y) for { if v_0.Op != OpARM64MULW { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MNEGW) v.AddArg2(x, y) return true } // match: (NEG (NEG x)) // result: x for { if v_0.Op != OpARM64NEG { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEG (MOVDconst [c])) // result: (MOVDconst [-c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-c) return true } // match: (NEG x:(SLLconst [c] y)) // cond: clobberIfDead(x) // result: (NEGshiftLL [c] y) for { x := v_0 if x.Op != OpARM64SLLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64NEGshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (NEG x:(SRLconst [c] y)) // cond: clobberIfDead(x) // result: (NEGshiftRL [c] y) for { x := v_0 if x.Op != OpARM64SRLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64NEGshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (NEG x:(SRAconst [c] y)) // cond: clobberIfDead(x) // result: (NEGshiftRA [c] y) for { x := v_0 if x.Op != OpARM64SRAconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64NEGshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64NEGshiftLL(v *Value) bool { v_0 := v.Args[0] // match: (NEGshiftLL (MOVDconst [c]) [d]) // result: (MOVDconst [-int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-(c >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64NEGshiftRL(v *Value) bool { v_0 := v.Args[0] // match: (NEGshiftRL (MOVDconst [c]) [d]) // result: (MOVDconst [-int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-int64(uint64(c) >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64NotEqual(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (NotEqual (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (NotEqual (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (NotEqual (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMP x z:(NEG y))) // cond: z.Uses == 1 // result: (NotEqual (CMN x y)) for { if v_0.Op != OpARM64CMP { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPW x z:(NEG y))) // cond: z.Uses == 1 // result: (NotEqual (CMNW x y)) for { if v_0.Op != OpARM64CMPW { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (NotEqual (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (NotEqual (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ne())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ne())) return true } // match: (NotEqual (InvertFlags x)) // result: (NotEqual x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64NotEqual) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64OR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (OR x (MOVDconst [c])) // result: (ORconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (OR x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (OR x (MVN y)) // result: (ORN x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MVN { continue } y := v_1.Args[0] v.reset(OpARM64ORN) v.AddArg2(x, y) return true } break } // match: (OR x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR (UBFIZ [bfc] x) (ANDconst [ac] y)) // cond: ac == ^((1< o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [i3] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i1] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i0] {s} p mem))) // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUload {s} (OffPtr [int64(i0)] p) mem) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] s0 := o1.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload { continue } i3 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o1.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { continue } i2 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y2 := o0.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { continue } i1 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { continue } y3 := v_1 if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload { continue } i0 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3) v0 := b.NewValue0(x3.Pos, OpARM64MOVWUload, t) v.copyOf(v0) v0.Aux = symToAux(s) v1 := b.NewValue0(x3.Pos, OpOffPtr, p.Type) v1.AuxInt = int64ToAuxInt(int64(i0)) v1.AddArg(p) v0.AddArg2(v1, mem) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [3] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr0 idx0 mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUloadidx ptr0 idx0 mem) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] s0 := o1.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload || auxIntToInt32(x0.AuxInt) != 3 { continue } s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o1.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 2 || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y2 := o0.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 1 || auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] p1 := x2.Args[0] if p1.Op != OpARM64ADD { continue } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x2.Args[1] { continue } y3 := v_1 if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { continue } _ = x3.Args[2] ptr0 := x3.Args[0] idx0 := x3.Args[1] if mem != x3.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3) v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) v.copyOf(v0) v0.AddArg3(ptr0, idx0, mem) return true } } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr idx mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUloadidx ptr idx mem) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] s0 := o1.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { continue } mem := x0.Args[2] ptr := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 3 { continue } idx := x0_1.Args[0] y1 := o1.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { continue } _ = x1.Args[2] if ptr != x1.Args[0] { continue } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 2 || idx != x1_1.Args[0] || mem != x1.Args[2] { continue } y2 := o0.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { continue } _ = x2.Args[2] if ptr != x2.Args[0] { continue } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 1 || idx != x2_1.Args[0] || mem != x2.Args[2] { continue } y3 := v_1 if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { continue } _ = x3.Args[2] if ptr != x3.Args[0] || idx != x3.Args[1] || mem != x3.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3) v0 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) v.copyOf(v0) v0.AddArg3(ptr, idx, mem) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUload [i7] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i6] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i4] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i3] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [i2] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [i1] {s} p mem))) y7:(MOVDnop x7:(MOVBUload [i0] {s} p mem))) // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} (OffPtr [int64(i0)] p) mem) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { continue } _ = o2.Args[1] o3 := o2.Args[0] if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { continue } _ = o3.Args[1] o4 := o3.Args[0] if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { continue } _ = o4.Args[1] o5 := o4.Args[0] if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { continue } _ = o5.Args[1] s0 := o5.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload { continue } i7 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o5.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { continue } i6 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y2 := o4.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { continue } i5 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { continue } y3 := o3.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload { continue } i4 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { continue } y4 := o2.Args[1] if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload { continue } i3 := auxIntToInt32(x4.AuxInt) if auxToSym(x4.Aux) != s { continue } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { continue } y5 := o1.Args[1] if y5.Op != OpARM64MOVDnop { continue } x5 := y5.Args[0] if x5.Op != OpARM64MOVBUload { continue } i2 := auxIntToInt32(x5.AuxInt) if auxToSym(x5.Aux) != s { continue } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { continue } y6 := o0.Args[1] if y6.Op != OpARM64MOVDnop { continue } x6 := y6.Args[0] if x6.Op != OpARM64MOVBUload { continue } i1 := auxIntToInt32(x6.AuxInt) if auxToSym(x6.Aux) != s { continue } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { continue } y7 := v_1 if y7.Op != OpARM64MOVDnop { continue } x7 := y7.Args[0] if x7.Op != OpARM64MOVBUload { continue } i0 := auxIntToInt32(x7.AuxInt) if auxToSym(x7.Aux) != s { continue } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpARM64MOVDload, t) v.copyOf(v0) v0.Aux = symToAux(s) v1 := b.NewValue0(x7.Pos, OpOffPtr, p.Type) v1.AuxInt = int64ToAuxInt(int64(i0)) v1.AddArg(p) v0.AddArg2(v1, mem) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUload [7] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [6] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [4] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [3] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [2] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y7:(MOVDnop x7:(MOVBUloadidx ptr0 idx0 mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDloadidx ptr0 idx0 mem) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { continue } _ = o2.Args[1] o3 := o2.Args[0] if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { continue } _ = o3.Args[1] o4 := o3.Args[0] if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { continue } _ = o4.Args[1] o5 := o4.Args[0] if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { continue } _ = o5.Args[1] s0 := o5.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload || auxIntToInt32(x0.AuxInt) != 7 { continue } s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o5.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 6 || auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y2 := o4.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 5 || auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { continue } y3 := o3.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 4 || auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { continue } y4 := o2.Args[1] if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 3 || auxToSym(x4.Aux) != s { continue } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { continue } y5 := o1.Args[1] if y5.Op != OpARM64MOVDnop { continue } x5 := y5.Args[0] if x5.Op != OpARM64MOVBUload || auxIntToInt32(x5.AuxInt) != 2 || auxToSym(x5.Aux) != s { continue } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { continue } y6 := o0.Args[1] if y6.Op != OpARM64MOVDnop { continue } x6 := y6.Args[0] if x6.Op != OpARM64MOVBUload || auxIntToInt32(x6.AuxInt) != 1 || auxToSym(x6.Aux) != s { continue } _ = x6.Args[1] p1 := x6.Args[0] if p1.Op != OpARM64ADD { continue } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x6.Args[1] { continue } y7 := v_1 if y7.Op != OpARM64MOVDnop { continue } x7 := y7.Args[0] if x7.Op != OpARM64MOVBUloadidx { continue } _ = x7.Args[2] ptr0 := x7.Args[0] idx0 := x7.Args[1] if mem != x7.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(x6.Pos, OpARM64MOVDloadidx, t) v.copyOf(v0) v0.AddArg3(ptr0, idx0, mem) return true } } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [7] idx) mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [6] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [5] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [4] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y5:(MOVDnop x5:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y6:(MOVDnop x6:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y7:(MOVDnop x7:(MOVBUloadidx ptr idx mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDloadidx ptr idx mem) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { continue } _ = o2.Args[1] o3 := o2.Args[0] if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { continue } _ = o3.Args[1] o4 := o3.Args[0] if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { continue } _ = o4.Args[1] o5 := o4.Args[0] if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { continue } _ = o5.Args[1] s0 := o5.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { continue } mem := x0.Args[2] ptr := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 7 { continue } idx := x0_1.Args[0] y1 := o5.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { continue } _ = x1.Args[2] if ptr != x1.Args[0] { continue } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 6 || idx != x1_1.Args[0] || mem != x1.Args[2] { continue } y2 := o4.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { continue } _ = x2.Args[2] if ptr != x2.Args[0] { continue } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 5 || idx != x2_1.Args[0] || mem != x2.Args[2] { continue } y3 := o3.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { continue } _ = x3.Args[2] if ptr != x3.Args[0] { continue } x3_1 := x3.Args[1] if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 4 || idx != x3_1.Args[0] || mem != x3.Args[2] { continue } y4 := o2.Args[1] if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUloadidx { continue } _ = x4.Args[2] if ptr != x4.Args[0] { continue } x4_1 := x4.Args[1] if x4_1.Op != OpARM64ADDconst || auxIntToInt64(x4_1.AuxInt) != 3 || idx != x4_1.Args[0] || mem != x4.Args[2] { continue } y5 := o1.Args[1] if y5.Op != OpARM64MOVDnop { continue } x5 := y5.Args[0] if x5.Op != OpARM64MOVBUloadidx { continue } _ = x5.Args[2] if ptr != x5.Args[0] { continue } x5_1 := x5.Args[1] if x5_1.Op != OpARM64ADDconst || auxIntToInt64(x5_1.AuxInt) != 2 || idx != x5_1.Args[0] || mem != x5.Args[2] { continue } y6 := o0.Args[1] if y6.Op != OpARM64MOVDnop { continue } x6 := y6.Args[0] if x6.Op != OpARM64MOVBUloadidx { continue } _ = x6.Args[2] if ptr != x6.Args[0] { continue } x6_1 := x6.Args[1] if x6_1.Op != OpARM64ADDconst || auxIntToInt64(x6_1.AuxInt) != 1 || idx != x6_1.Args[0] || mem != x6.Args[2] { continue } y7 := v_1 if y7.Op != OpARM64MOVDnop { continue } x7 := y7.Args[0] if x7.Op != OpARM64MOVBUloadidx { continue } _ = x7.Args[2] if ptr != x7.Args[0] || idx != x7.Args[1] || mem != x7.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) v.copyOf(v0) v0.AddArg3(ptr, idx, mem) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [i0] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i3] {s} p mem))) // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) // result: @mergePoint(b,x0,x1,x2,x3) (REVW (MOVWUload {s} (OffPtr [int64(i0)] p) mem)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] s0 := o1.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o1.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y2 := o0.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { continue } i2 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { continue } y3 := v_1 if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload { continue } i3 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3) v0 := b.NewValue0(x3.Pos, OpARM64REVW, t) v.copyOf(v0) v1 := b.NewValue0(x3.Pos, OpARM64MOVWUload, t) v1.Aux = symToAux(s) v2 := b.NewValue0(x3.Pos, OpOffPtr, p.Type) v2.AuxInt = int64ToAuxInt(int64(i0)) v2.AddArg(p) v1.AddArg2(v2, mem) v0.AddArg(v1) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr0 idx0 mem))) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [3] {s} p mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) // result: @mergePoint(b,x0,x1,x2,x3) (REVW (MOVWUloadidx ptr0 idx0 mem)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] s0 := o1.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { continue } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := o1.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 { continue } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADD { continue } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x1.Args[1] { continue } y2 := o0.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 2 || auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] p := x2.Args[0] if mem != x2.Args[1] { continue } y3 := v_1 if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 3 || auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3) v0 := b.NewValue0(x3.Pos, OpARM64REVW, t) v.copyOf(v0) v1 := b.NewValue0(x3.Pos, OpARM64MOVWUloadidx, t) v1.AddArg3(ptr0, idx0, mem) v0.AddArg(v1) return true } } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr idx mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) // result: @mergePoint(b,x0,x1,x2,x3) (REVW (MOVWUloadidx ptr idx mem)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] s0 := o1.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { continue } mem := x0.Args[2] ptr := x0.Args[0] idx := x0.Args[1] y1 := o1.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { continue } _ = x1.Args[2] if ptr != x1.Args[0] { continue } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] { continue } y2 := o0.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { continue } _ = x2.Args[2] if ptr != x2.Args[0] { continue } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 2 || idx != x2_1.Args[0] || mem != x2.Args[2] { continue } y3 := v_1 if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { continue } _ = x3.Args[2] if ptr != x3.Args[0] { continue } x3_1 := x3.Args[1] if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 3 || idx != x3_1.Args[0] || mem != x3.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3) v0 := b.NewValue0(v.Pos, OpARM64REVW, t) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) v1.AddArg3(ptr, idx, mem) v0.AddArg(v1) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUload [i0] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i3] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i4] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [i5] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [i6] {s} p mem))) y7:(MOVDnop x7:(MOVBUload [i7] {s} p mem))) // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (REV (MOVDload {s} (OffPtr [int64(i0)] p) mem)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { continue } _ = o2.Args[1] o3 := o2.Args[0] if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { continue } _ = o3.Args[1] o4 := o3.Args[0] if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { continue } _ = o4.Args[1] o5 := o4.Args[0] if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { continue } _ = o5.Args[1] s0 := o5.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload { continue } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o5.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { continue } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { continue } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { continue } y2 := o4.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { continue } i2 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { continue } y3 := o3.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload { continue } i3 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { continue } y4 := o2.Args[1] if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload { continue } i4 := auxIntToInt32(x4.AuxInt) if auxToSym(x4.Aux) != s { continue } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { continue } y5 := o1.Args[1] if y5.Op != OpARM64MOVDnop { continue } x5 := y5.Args[0] if x5.Op != OpARM64MOVBUload { continue } i5 := auxIntToInt32(x5.AuxInt) if auxToSym(x5.Aux) != s { continue } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { continue } y6 := o0.Args[1] if y6.Op != OpARM64MOVDnop { continue } x6 := y6.Args[0] if x6.Op != OpARM64MOVBUload { continue } i6 := auxIntToInt32(x6.AuxInt) if auxToSym(x6.Aux) != s { continue } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { continue } y7 := v_1 if y7.Op != OpARM64MOVDnop { continue } x7 := y7.Args[0] if x7.Op != OpARM64MOVBUload { continue } i7 := auxIntToInt32(x7.AuxInt) if auxToSym(x7.Aux) != s { continue } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpARM64REV, t) v.copyOf(v0) v1 := b.NewValue0(x7.Pos, OpARM64MOVDload, t) v1.Aux = symToAux(s) v2 := b.NewValue0(x7.Pos, OpOffPtr, p.Type) v2.AuxInt = int64ToAuxInt(int64(i0)) v2.AddArg(p) v1.AddArg2(v2, mem) v0.AddArg(v1) return true } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUloadidx ptr0 idx0 mem))) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [3] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [4] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [5] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [6] {s} p mem))) y7:(MOVDnop x7:(MOVBUload [7] {s} p mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (REV (MOVDloadidx ptr0 idx0 mem)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { continue } _ = o2.Args[1] o3 := o2.Args[0] if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { continue } _ = o3.Args[1] o4 := o3.Args[0] if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { continue } _ = o4.Args[1] o5 := o4.Args[0] if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { continue } _ = o5.Args[1] s0 := o5.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { continue } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := o5.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 { continue } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADD { continue } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x1.Args[1] { continue } y2 := o4.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 2 || auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] p := x2.Args[0] if mem != x2.Args[1] { continue } y3 := o3.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 3 || auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { continue } y4 := o2.Args[1] if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 4 || auxToSym(x4.Aux) != s { continue } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] { continue } y5 := o1.Args[1] if y5.Op != OpARM64MOVDnop { continue } x5 := y5.Args[0] if x5.Op != OpARM64MOVBUload || auxIntToInt32(x5.AuxInt) != 5 || auxToSym(x5.Aux) != s { continue } _ = x5.Args[1] if p != x5.Args[0] || mem != x5.Args[1] { continue } y6 := o0.Args[1] if y6.Op != OpARM64MOVDnop { continue } x6 := y6.Args[0] if x6.Op != OpARM64MOVBUload || auxIntToInt32(x6.AuxInt) != 6 || auxToSym(x6.Aux) != s { continue } _ = x6.Args[1] if p != x6.Args[0] || mem != x6.Args[1] { continue } y7 := v_1 if y7.Op != OpARM64MOVDnop { continue } x7 := y7.Args[0] if x7.Op != OpARM64MOVBUload || auxIntToInt32(x7.AuxInt) != 7 || auxToSym(x7.Aux) != s { continue } _ = x7.Args[1] if p != x7.Args[0] || mem != x7.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(x7.Pos, OpARM64REV, t) v.copyOf(v0) v1 := b.NewValue0(x7.Pos, OpARM64MOVDloadidx, t) v1.AddArg3(ptr0, idx0, mem) v0.AddArg(v1) return true } } break } // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUloadidx ptr idx mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr (ADDconst [4] idx) mem))) y5:(MOVDnop x5:(MOVBUloadidx ptr (ADDconst [5] idx) mem))) y6:(MOVDnop x6:(MOVBUloadidx ptr (ADDconst [6] idx) mem))) y7:(MOVDnop x7:(MOVBUloadidx ptr (ADDconst [7] idx) mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (REV (MOVDloadidx ptr idx mem)) for { t := v.Type for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { continue } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { continue } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { continue } _ = o2.Args[1] o3 := o2.Args[0] if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { continue } _ = o3.Args[1] o4 := o3.Args[0] if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { continue } _ = o4.Args[1] o5 := o4.Args[0] if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { continue } _ = o5.Args[1] s0 := o5.Args[0] if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { continue } y0 := s0.Args[0] if y0.Op != OpARM64MOVDnop { continue } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { continue } mem := x0.Args[2] ptr := x0.Args[0] idx := x0.Args[1] y1 := o5.Args[1] if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { continue } _ = x1.Args[2] if ptr != x1.Args[0] { continue } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] { continue } y2 := o4.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { continue } _ = x2.Args[2] if ptr != x2.Args[0] { continue } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 2 || idx != x2_1.Args[0] || mem != x2.Args[2] { continue } y3 := o3.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { continue } _ = x3.Args[2] if ptr != x3.Args[0] { continue } x3_1 := x3.Args[1] if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 3 || idx != x3_1.Args[0] || mem != x3.Args[2] { continue } y4 := o2.Args[1] if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUloadidx { continue } _ = x4.Args[2] if ptr != x4.Args[0] { continue } x4_1 := x4.Args[1] if x4_1.Op != OpARM64ADDconst || auxIntToInt64(x4_1.AuxInt) != 4 || idx != x4_1.Args[0] || mem != x4.Args[2] { continue } y5 := o1.Args[1] if y5.Op != OpARM64MOVDnop { continue } x5 := y5.Args[0] if x5.Op != OpARM64MOVBUloadidx { continue } _ = x5.Args[2] if ptr != x5.Args[0] { continue } x5_1 := x5.Args[1] if x5_1.Op != OpARM64ADDconst || auxIntToInt64(x5_1.AuxInt) != 5 || idx != x5_1.Args[0] || mem != x5.Args[2] { continue } y6 := o0.Args[1] if y6.Op != OpARM64MOVDnop { continue } x6 := y6.Args[0] if x6.Op != OpARM64MOVBUloadidx { continue } _ = x6.Args[2] if ptr != x6.Args[0] { continue } x6_1 := x6.Args[1] if x6_1.Op != OpARM64ADDconst || auxIntToInt64(x6_1.AuxInt) != 6 || idx != x6_1.Args[0] || mem != x6.Args[2] { continue } y7 := v_1 if y7.Op != OpARM64MOVDnop { continue } x7 := y7.Args[0] if x7.Op != OpARM64MOVBUloadidx { continue } _ = x7.Args[2] if ptr != x7.Args[0] { continue } x7_1 := x7.Args[1] if x7_1.Op != OpARM64ADDconst || auxIntToInt64(x7_1.AuxInt) != 7 || idx != x7_1.Args[0] || mem != x7.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) v0 := b.NewValue0(v.Pos, OpARM64REV, t) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) v1.AddArg3(ptr, idx, mem) v0.AddArg(v1) return true } break } return false } func rewriteValueARM64_OpARM64ORN(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ORN x (MOVDconst [c])) // result: (ORconst [^c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^c) v.AddArg(x) return true } // match: (ORN x x) // result: (MOVDconst [-1]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (ORN x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ORNshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64ORNshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (ORN x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ORNshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64ORNshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (ORN x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ORNshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64ORNshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (ORN x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (ORNshiftRO x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64ORNshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64ORNshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ORNshiftLL x (MOVDconst [c]) [d]) // result: (ORconst x [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) v.AddArg(x) return true } // match: (ORNshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64ORNshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ORNshiftRL x (MOVDconst [c]) [d]) // result: (ORconst x [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (ORNshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64ORNshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ORNshiftRO x (MOVDconst [c]) [d]) // result: (ORconst x [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) v.AddArg(x) return true } // match: (ORNshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64ORconst(v *Value) bool { v_0 := v.Args[0] // match: (ORconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ORconst [-1] _) // result: (MOVDconst [-1]) for { if auxIntToInt64(v.AuxInt) != -1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (ORconst [c] (MOVDconst [d])) // result: (MOVDconst [c|d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c | d) return true } // match: (ORconst [c] (ORconst [d] x)) // result: (ORconst [c|d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ORconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORconst [c1] (ANDconst [c2] x)) // cond: c2|c1 == ^0 // result: (ORconst [c1] x) for { c1 := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(c2|c1 == ^0) { break } v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c1) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ORshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ORshiftLL (MOVDconst [c]) x [d]) // result: (ORconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftLL x (MOVDconst [c]) [d]) // result: (ORconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) // result: (REV16W x) for { if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ORshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff // result: (REV16W x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) // result: (REV16 x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { break } v.reset(OpARM64REV16) v.AddArg(x) return true } // match: (ORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) // result: (REV16 (ANDconst [0xffffffff] x)) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16) v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) v0.AuxInt = int64ToAuxInt(0xffffffff) v0.AddArg(x) v.AddArg(v0) return true } // match: ( ORshiftLL [c] (SRLconst x [64-c]) x2) // result: (EXTRconst [64-c] x2 x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { break } x := v_0.Args[0] x2 := v_1 v.reset(OpARM64EXTRconst) v.AuxInt = int64ToAuxInt(64 - c) v.AddArg2(x2, x) return true } // match: ( ORshiftLL [c] (UBFX [bfc] x) x2) // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) // result: (EXTRWconst [32-c] x2 x) for { t := v.Type c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] x2 := v_1 if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { break } v.reset(OpARM64EXTRWconst) v.AuxInt = int64ToAuxInt(32 - c) v.AddArg2(x2, x) return true } // match: (ORshiftLL [sc] (UBFX [bfc] x) (SRLconst [sc] y)) // cond: sc == bfc.getARM64BFwidth() // result: (BFXIL [bfc] y x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != sc { break } y := v_1.Args[0] if !(sc == bfc.getARM64BFwidth()) { break } v.reset(OpARM64BFXIL) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg2(y, x) return true } // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUload [i0] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) // result: @mergePoint(b,x0,x1) (MOVHUload {s} (OffPtr [int64(i0)] p) mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 8 { break } y0 := v_0 if y0.Op != OpARM64MOVDnop { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload { break } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := v_1 if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { break } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpARM64MOVHUload, t) v.copyOf(v0) v0.Aux = symToAux(s) v1 := b.NewValue0(x1.Pos, OpOffPtr, p.Type) v1.AuxInt = int64ToAuxInt(int64(i0)) v1.AddArg(p) v0.AddArg2(v1, mem) return true } // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUloadidx ptr0 idx0 mem)) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1) // result: @mergePoint(b,x0,x1) (MOVHUloadidx ptr0 idx0 mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 8 { break } y0 := v_0 if y0.Op != OpARM64MOVDnop { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { break } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := v_1 if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 { break } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x1.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpARM64MOVHUloadidx, t) v.copyOf(v0) v0.AddArg3(ptr0, idx0, mem) return true } break } // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUloadidx ptr idx mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) // result: @mergePoint(b,x0,x1) (MOVHUloadidx ptr idx mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 8 { break } y0 := v_0 if y0.Op != OpARM64MOVDnop { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { break } mem := x0.Args[2] ptr := x0.Args[0] idx := x0.Args[1] y1 := v_1 if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpARM64MOVHUloadidx, t) v.copyOf(v0) v0.AddArg3(ptr, idx, mem) return true } // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUload [i0] {s} p mem) y1:(MOVDnop x1:(MOVBUload [i2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i3] {s} p mem))) // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (MOVWUload {s} (OffPtr [int64(i0)] p) mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpARM64MOVHUload { break } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { break } i2 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } y2 := v_1 if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { break } i3 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y1, y2, o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpARM64MOVWUload, t) v.copyOf(v0) v0.Aux = symToAux(s) v1 := b.NewValue0(x2.Pos, OpOffPtr, p.Type) v1.AuxInt = int64ToAuxInt(int64(i0)) v1.AddArg(p) v0.AddArg2(v1, mem) return true } // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [2] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [3] {s} p mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (MOVWUloadidx ptr0 idx0 mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpARM64MOVHUloadidx { break } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 2 { break } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x1.Args[1] { continue } y2 := v_1 if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 3 || auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] p := x2.Args[0] if mem != x2.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0)) { continue } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) v.copyOf(v0) v0.AddArg3(ptr0, idx0, mem) return true } break } // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx ptr idx mem) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (MOVWUloadidx ptr idx mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpARM64MOVHUloadidx { break } mem := x0.Args[2] ptr := x0.Args[0] idx := x0.Args[1] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 2 || idx != x1_1.Args[0] || mem != x1.Args[2] { break } y2 := v_1 if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { break } _ = x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 3 || idx != x2_1.Args[0] || mem != x2.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y1, y2, o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) v.copyOf(v0) v0.AddArg3(ptr, idx, mem) return true } // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx2 ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [2] {s} p1:(ADDshiftLL [1] ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [3] {s} p mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (MOVWUloadidx ptr0 (SLLconst [1] idx0) mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] x0 := o0.Args[0] if x0.Op != OpARM64MOVHUloadidx2 { break } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 2 { break } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADDshiftLL || auxIntToInt64(p1.AuxInt) != 1 { break } idx1 := p1.Args[1] ptr1 := p1.Args[0] if mem != x1.Args[1] { break } y2 := v_1 if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 3 || auxToSym(x2.Aux) != s { break } _ = x2.Args[1] p := x2.Args[0] if mem != x2.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) v.copyOf(v0) v1 := b.NewValue0(x2.Pos, OpARM64SLLconst, idx0.Type) v1.AuxInt = int64ToAuxInt(1) v1.AddArg(idx0) v0.AddArg3(ptr0, v1, mem) return true } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUload [i0] {s} p mem) y1:(MOVDnop x1:(MOVBUload [i4] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i7] {s} p mem))) // cond: i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDload {s} (OffPtr [int64(i0)] p) mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] x0 := o2.Args[0] if x0.Op != OpARM64MOVWUload { break } i0 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { break } i4 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { break } i5 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { break } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload { break } i6 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } y4 := v_1 if y4.Op != OpARM64MOVDnop { break } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload { break } i7 := auxIntToInt32(x4.AuxInt) if auxToSym(x4.Aux) != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] || !(i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x4.Pos, OpARM64MOVDload, t) v.copyOf(v0) v0.Aux = symToAux(s) v1 := b.NewValue0(x4.Pos, OpOffPtr, p.Type) v1.AuxInt = int64ToAuxInt(int64(i0)) v1.AddArg(p) v0.AddArg2(v1, mem) return true } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [4] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [7] {s} p mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDloadidx ptr0 idx0 mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] x0 := o2.Args[0] if x0.Op != OpARM64MOVWUloadidx { break } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 4 { break } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x1.Args[1] { continue } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 5 || auxToSym(x2.Aux) != s { continue } _ = x2.Args[1] p := x2.Args[0] if mem != x2.Args[1] { continue } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { continue } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 6 || auxToSym(x3.Aux) != s { continue } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { continue } y4 := v_1 if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 7 || auxToSym(x4.Aux) != s { continue } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x4.Pos, OpARM64MOVDloadidx, t) v.copyOf(v0) v0.AddArg3(ptr0, idx0, mem) return true } break } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx4 ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [4] {s} p1:(ADDshiftLL [2] ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [7] {s} p mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDloadidx ptr0 (SLLconst [2] idx0) mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] x0 := o2.Args[0] if x0.Op != OpARM64MOVWUloadidx4 { break } mem := x0.Args[2] ptr0 := x0.Args[0] idx0 := x0.Args[1] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 4 { break } s := auxToSym(x1.Aux) _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADDshiftLL || auxIntToInt64(p1.AuxInt) != 2 { break } idx1 := p1.Args[1] ptr1 := p1.Args[0] if mem != x1.Args[1] { break } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 5 || auxToSym(x2.Aux) != s { break } _ = x2.Args[1] p := x2.Args[0] if mem != x2.Args[1] { break } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { break } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 6 || auxToSym(x3.Aux) != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } y4 := v_1 if y4.Op != OpARM64MOVDnop { break } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 7 || auxToSym(x4.Aux) != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x4.Pos, OpARM64MOVDloadidx, t) v.copyOf(v0) v1 := b.NewValue0(x4.Pos, OpARM64SLLconst, idx0.Type) v1.AuxInt = int64ToAuxInt(2) v1.AddArg(idx0) v0.AddArg3(ptr0, v1, mem) return true } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx ptr idx mem) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [4] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [5] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [6] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr (ADDconst [7] idx) mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDloadidx ptr idx mem) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] x0 := o2.Args[0] if x0.Op != OpARM64MOVWUloadidx { break } mem := x0.Args[2] ptr := x0.Args[0] idx := x0.Args[1] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 4 || idx != x1_1.Args[0] || mem != x1.Args[2] { break } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { break } _ = x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 5 || idx != x2_1.Args[0] || mem != x2.Args[2] { break } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { break } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { break } _ = x3.Args[2] if ptr != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 6 || idx != x3_1.Args[0] || mem != x3.Args[2] { break } y4 := v_1 if y4.Op != OpARM64MOVDnop { break } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUloadidx { break } _ = x4.Args[2] if ptr != x4.Args[0] { break } x4_1 := x4.Args[1] if x4_1.Op != OpARM64ADDconst || auxIntToInt64(x4_1.AuxInt) != 7 || idx != x4_1.Args[0] || mem != x4.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) v.copyOf(v0) v0.AddArg3(ptr, idx, mem) return true } // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUload [i1] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i0] {s} p mem))) // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) // result: @mergePoint(b,x0,x1) (REV16W (MOVHUload [i0] {s} p mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 8 { break } y0 := v_0 if y0.Op != OpARM64MOVDnop { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload { break } i1 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := v_1 if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { break } i0 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x1.Pos, OpARM64REV16W, t) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpARM64MOVHUload, t) v1.AuxInt = int32ToAuxInt(i0) v1.Aux = symToAux(s) v1.AddArg2(p, mem) v0.AddArg(v1) return true } // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr0 idx0 mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1) // result: @mergePoint(b,x0,x1) (REV16W (MOVHUloadidx ptr0 idx0 mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 8 { break } y0 := v_0 if y0.Op != OpARM64MOVDnop { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUload || auxIntToInt32(x0.AuxInt) != 1 { break } s := auxToSym(x0.Aux) mem := x0.Args[1] p1 := x0.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 y1 := v_1 if y1.Op != OpARM64MOVDnop { continue } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { continue } _ = x1.Args[2] ptr0 := x1.Args[0] idx0 := x1.Args[1] if mem != x1.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1)) { continue } b = mergePoint(b, x0, x1) v0 := b.NewValue0(x0.Pos, OpARM64REV16W, t) v.copyOf(v0) v1 := b.NewValue0(x0.Pos, OpARM64MOVHUloadidx, t) v1.AddArg3(ptr0, idx0, mem) v0.AddArg(v1) return true } break } // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [1] idx) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr idx mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) // result: @mergePoint(b,x0,x1) (REV16W (MOVHUloadidx ptr idx mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 8 { break } y0 := v_0 if y0.Op != OpARM64MOVDnop { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVBUloadidx { break } mem := x0.Args[2] ptr := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 1 { break } idx := x0_1.Args[0] y1 := v_1 if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { break } _ = x1.Args[2] if ptr != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { break } b = mergePoint(b, x0, x1) v0 := b.NewValue0(v.Pos, OpARM64REV16W, t) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpARM64MOVHUloadidx, t) v1.AddArg3(ptr, idx, mem) v0.AddArg(v1) return true } // match: (ORshiftLL [24] o0:(ORshiftLL [16] y0:(REV16W x0:(MOVHUload [i2] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i0] {s} p mem))) // cond: i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (REVW (MOVWUload {s} (OffPtr [int64(i0)] p) mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] y0 := o0.Args[0] if y0.Op != OpARM64REV16W { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVHUload { break } i2 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { break } i1 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } y2 := v_1 if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { break } i0 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] || !(i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x2.Pos, OpARM64REVW, t) v.copyOf(v0) v1 := b.NewValue0(x2.Pos, OpARM64MOVWUload, t) v1.Aux = symToAux(s) v2 := b.NewValue0(x2.Pos, OpOffPtr, p.Type) v2.AuxInt = int64ToAuxInt(int64(i0)) v2.AddArg(p) v1.AddArg2(v2, mem) v0.AddArg(v1) return true } // match: (ORshiftLL [24] o0:(ORshiftLL [16] y0:(REV16W x0:(MOVHUload [2] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr0 idx0 mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y0, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (REVW (MOVWUloadidx ptr0 idx0 mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] y0 := o0.Args[0] if y0.Op != OpARM64REV16W { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVHUload || auxIntToInt32(x0.AuxInt) != 2 { break } s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { break } _ = x1.Args[1] p1 := x1.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x1.Args[1] { continue } y2 := v_1 if y2.Op != OpARM64MOVDnop { continue } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { continue } _ = x2.Args[2] ptr0 := x2.Args[0] idx0 := x2.Args[1] if mem != x2.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y0, y1, y2, o0)) { continue } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(x1.Pos, OpARM64REVW, t) v.copyOf(v0) v1 := b.NewValue0(x1.Pos, OpARM64MOVWUloadidx, t) v1.AddArg3(ptr0, idx0, mem) v0.AddArg(v1) return true } break } // match: (ORshiftLL [24] o0:(ORshiftLL [16] y0:(REV16W x0:(MOVHUloadidx ptr (ADDconst [2] idx) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr idx mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0) // result: @mergePoint(b,x0,x1,x2) (REVW (MOVWUloadidx ptr idx mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 24 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { break } _ = o0.Args[1] y0 := o0.Args[0] if y0.Op != OpARM64REV16W { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVHUloadidx { break } mem := x0.Args[2] ptr := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 2 { break } idx := x0_1.Args[0] y1 := o0.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] { break } y2 := v_1 if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { break } _ = x2.Args[2] if ptr != x2.Args[0] || idx != x2.Args[1] || mem != x2.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0)) { break } b = mergePoint(b, x0, x1, x2) v0 := b.NewValue0(v.Pos, OpARM64REVW, t) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) v1.AddArg3(ptr, idx, mem) v0.AddArg(v1) return true } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] y0:(REVW x0:(MOVWUload [i4] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i3] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i1] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i0] {s} p mem))) // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (REV (MOVDload {s} (OffPtr [int64(i0)] p) mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] y0 := o2.Args[0] if y0.Op != OpARM64REVW { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVWUload { break } i4 := auxIntToInt32(x0.AuxInt) s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload { break } i3 := auxIntToInt32(x1.AuxInt) if auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload { break } i2 := auxIntToInt32(x2.AuxInt) if auxToSym(x2.Aux) != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { break } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload { break } i1 := auxIntToInt32(x3.AuxInt) if auxToSym(x3.Aux) != s { break } _ = x3.Args[1] if p != x3.Args[0] || mem != x3.Args[1] { break } y4 := v_1 if y4.Op != OpARM64MOVDnop { break } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUload { break } i0 := auxIntToInt32(x4.AuxInt) if auxToSym(x4.Aux) != s { break } _ = x4.Args[1] if p != x4.Args[0] || mem != x4.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x4.Pos, OpARM64REV, t) v.copyOf(v0) v1 := b.NewValue0(x4.Pos, OpARM64MOVDload, t) v1.Aux = symToAux(s) v2 := b.NewValue0(x4.Pos, OpOffPtr, p.Type) v2.AuxInt = int64ToAuxInt(int64(i0)) v2.AddArg(p) v1.AddArg2(v2, mem) v0.AddArg(v1) return true } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] y0:(REVW x0:(MOVWUload [4] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [3] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr0 idx0 mem))) // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (REV (MOVDloadidx ptr0 idx0 mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] y0 := o2.Args[0] if y0.Op != OpARM64REVW { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVWUload || auxIntToInt32(x0.AuxInt) != 4 { break } s := auxToSym(x0.Aux) mem := x0.Args[1] p := x0.Args[0] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 3 || auxToSym(x1.Aux) != s { break } _ = x1.Args[1] if p != x1.Args[0] || mem != x1.Args[1] { break } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 2 || auxToSym(x2.Aux) != s { break } _ = x2.Args[1] if p != x2.Args[0] || mem != x2.Args[1] { break } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { break } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 1 || auxToSym(x3.Aux) != s { break } _ = x3.Args[1] p1 := x3.Args[0] if p1.Op != OpARM64ADD { break } _ = p1.Args[1] p1_0 := p1.Args[0] p1_1 := p1.Args[1] for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { ptr1 := p1_0 idx1 := p1_1 if mem != x3.Args[1] { continue } y4 := v_1 if y4.Op != OpARM64MOVDnop { continue } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUloadidx { continue } _ = x4.Args[2] ptr0 := x4.Args[0] idx0 := x4.Args[1] if mem != x4.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2)) { continue } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(x3.Pos, OpARM64REV, t) v.copyOf(v0) v1 := b.NewValue0(x3.Pos, OpARM64MOVDloadidx, t) v1.AddArg3(ptr0, idx0, mem) v0.AddArg(v1) return true } break } // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] y0:(REVW x0:(MOVWUloadidx ptr (ADDconst [4] idx) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr idx mem))) // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2) // result: @mergePoint(b,x0,x1,x2,x3,x4) (REV (MOVDloadidx ptr idx mem)) for { t := v.Type if auxIntToInt64(v.AuxInt) != 56 { break } o0 := v_0 if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { break } _ = o0.Args[1] o1 := o0.Args[0] if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { break } _ = o1.Args[1] o2 := o1.Args[0] if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { break } _ = o2.Args[1] y0 := o2.Args[0] if y0.Op != OpARM64REVW { break } x0 := y0.Args[0] if x0.Op != OpARM64MOVWUloadidx { break } mem := x0.Args[2] ptr := x0.Args[0] x0_1 := x0.Args[1] if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 4 { break } idx := x0_1.Args[0] y1 := o2.Args[1] if y1.Op != OpARM64MOVDnop { break } x1 := y1.Args[0] if x1.Op != OpARM64MOVBUloadidx { break } _ = x1.Args[2] if ptr != x1.Args[0] { break } x1_1 := x1.Args[1] if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 3 || idx != x1_1.Args[0] || mem != x1.Args[2] { break } y2 := o1.Args[1] if y2.Op != OpARM64MOVDnop { break } x2 := y2.Args[0] if x2.Op != OpARM64MOVBUloadidx { break } _ = x2.Args[2] if ptr != x2.Args[0] { break } x2_1 := x2.Args[1] if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 2 || idx != x2_1.Args[0] || mem != x2.Args[2] { break } y3 := o0.Args[1] if y3.Op != OpARM64MOVDnop { break } x3 := y3.Args[0] if x3.Op != OpARM64MOVBUloadidx { break } _ = x3.Args[2] if ptr != x3.Args[0] { break } x3_1 := x3.Args[1] if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 1 || idx != x3_1.Args[0] || mem != x3.Args[2] { break } y4 := v_1 if y4.Op != OpARM64MOVDnop { break } x4 := y4.Args[0] if x4.Op != OpARM64MOVBUloadidx { break } _ = x4.Args[2] if ptr != x4.Args[0] || idx != x4.Args[1] || mem != x4.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2)) { break } b = mergePoint(b, x0, x1, x2, x3, x4) v0 := b.NewValue0(v.Pos, OpARM64REV, t) v.copyOf(v0) v1 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) v1.AddArg3(ptr, idx, mem) v0.AddArg(v1) return true } return false } func rewriteValueARM64_OpARM64ORshiftRA(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ORshiftRA (MOVDconst [c]) x [d]) // result: (ORconst [c] (SRAconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftRA x (MOVDconst [c]) [d]) // result: (ORconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (ORshiftRA y:(SRAconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRAconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64ORshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ORshiftRL (MOVDconst [c]) x [d]) // result: (ORconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftRL x (MOVDconst [c]) [d]) // result: (ORconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (ORshiftRL y:(SRLconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRLconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } // match: (ORshiftRL [rc] (ANDconst [ac] x) (SLLconst [lc] y)) // cond: lc > rc && ac == ^((1< rc && ac == ^((1< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftRO x (MOVDconst [c]) [d]) // result: (ORconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } // match: (ORshiftRO y:(RORconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64RORconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64REV(v *Value) bool { v_0 := v.Args[0] // match: (REV (REV p)) // result: p for { if v_0.Op != OpARM64REV { break } p := v_0.Args[0] v.copyOf(p) return true } return false } func rewriteValueARM64_OpARM64REVW(v *Value) bool { v_0 := v.Args[0] // match: (REVW (REVW p)) // result: p for { if v_0.Op != OpARM64REVW { break } p := v_0.Args[0] v.copyOf(p) return true } return false } func rewriteValueARM64_OpARM64ROR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ROR x (MOVDconst [c])) // result: (RORconst x [c&63]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64RORconst) v.AuxInt = int64ToAuxInt(c & 63) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64RORW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (RORW x (MOVDconst [c])) // result: (RORWconst x [c&31]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64RORWconst) v.AuxInt = int64ToAuxInt(c & 31) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64SBCSflags(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SBCSflags x y (Select1 (NEGSflags (NEG (NGCzerocarry bo))))) // result: (SBCSflags x y bo) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64NEGSflags { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64NEG || v_2_0_0.Type != typ.UInt64 { break } v_2_0_0_0 := v_2_0_0.Args[0] if v_2_0_0_0.Op != OpARM64NGCzerocarry || v_2_0_0_0.Type != typ.UInt64 { break } bo := v_2_0_0_0.Args[0] v.reset(OpARM64SBCSflags) v.AddArg3(x, y, bo) return true } // match: (SBCSflags x y (Select1 (NEGSflags (MOVDconst [0])))) // result: (SUBSflags x y) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64NEGSflags { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64MOVDconst || auxIntToInt64(v_2_0_0.AuxInt) != 0 { break } v.reset(OpARM64SUBSflags) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64SLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SLL x (MOVDconst [c])) // result: (SLLconst x [c&63]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(c & 63) v.AddArg(x) return true } // match: (SLL x (ANDconst [63] y)) // result: (SLL x y) for { x := v_0 if v_1.Op != OpARM64ANDconst || auxIntToInt64(v_1.AuxInt) != 63 { break } y := v_1.Args[0] v.reset(OpARM64SLL) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64SLLconst(v *Value) bool { v_0 := v.Args[0] // match: (SLLconst [c] (MOVDconst [d])) // result: (MOVDconst [d<>uint64(c)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(d >> uint64(c)) return true } // match: (SRAconst [rc] (SLLconst [lc] x)) // cond: lc > rc // result: (SBFIZ [armBFAuxInt(lc-rc, 64-lc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc > rc) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc-rc, 64-lc)) v.AddArg(x) return true } // match: (SRAconst [rc] (SLLconst [lc] x)) // cond: lc <= rc // result: (SBFX [armBFAuxInt(rc-lc, 64-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc <= rc) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc-lc, 64-rc)) v.AddArg(x) return true } // match: (SRAconst [rc] (MOVWreg x)) // cond: rc < 32 // result: (SBFX [armBFAuxInt(rc, 32-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWreg { break } x := v_0.Args[0] if !(rc < 32) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 32-rc)) v.AddArg(x) return true } // match: (SRAconst [rc] (MOVHreg x)) // cond: rc < 16 // result: (SBFX [armBFAuxInt(rc, 16-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHreg { break } x := v_0.Args[0] if !(rc < 16) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 16-rc)) v.AddArg(x) return true } // match: (SRAconst [rc] (MOVBreg x)) // cond: rc < 8 // result: (SBFX [armBFAuxInt(rc, 8-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBreg { break } x := v_0.Args[0] if !(rc < 8) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8-rc)) v.AddArg(x) return true } // match: (SRAconst [sc] (SBFIZ [bfc] x)) // cond: sc < bfc.getARM64BFlsb() // result: (SBFIZ [armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SBFIZ { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc < bfc.getARM64BFlsb()) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())) v.AddArg(x) return true } // match: (SRAconst [sc] (SBFIZ [bfc] x)) // cond: sc >= bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() // result: (SBFX [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SBFIZ { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc >= bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth()) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64SRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SRL x (MOVDconst [c])) // result: (SRLconst x [c&63]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(c & 63) v.AddArg(x) return true } // match: (SRL x (ANDconst [63] y)) // result: (SRL x y) for { x := v_0 if v_1.Op != OpARM64ANDconst || auxIntToInt64(v_1.AuxInt) != 63 { break } y := v_1.Args[0] v.reset(OpARM64SRL) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64SRLconst(v *Value) bool { v_0 := v.Args[0] // match: (SRLconst [c] (MOVDconst [d])) // result: (MOVDconst [int64(uint64(d)>>uint64(c))]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint64(d) >> uint64(c))) return true } // match: (SRLconst [c] (SLLconst [c] x)) // cond: 0 < c && c < 64 // result: (ANDconst [1<= 32 // result: (MOVDconst [0]) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg { break } if !(rc >= 32) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SRLconst [rc] (MOVHUreg x)) // cond: rc >= 16 // result: (MOVDconst [0]) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg { break } if !(rc >= 16) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SRLconst [rc] (MOVBUreg x)) // cond: rc >= 8 // result: (MOVDconst [0]) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg { break } if !(rc >= 8) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SRLconst [rc] (SLLconst [lc] x)) // cond: lc > rc // result: (UBFIZ [armBFAuxInt(lc-rc, 64-lc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc > rc) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc-rc, 64-lc)) v.AddArg(x) return true } // match: (SRLconst [rc] (SLLconst [lc] x)) // cond: lc < rc // result: (UBFX [armBFAuxInt(rc-lc, 64-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < rc) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc-lc, 64-rc)) v.AddArg(x) return true } // match: (SRLconst [rc] (MOVWUreg x)) // cond: rc < 32 // result: (UBFX [armBFAuxInt(rc, 32-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg { break } x := v_0.Args[0] if !(rc < 32) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 32-rc)) v.AddArg(x) return true } // match: (SRLconst [rc] (MOVHUreg x)) // cond: rc < 16 // result: (UBFX [armBFAuxInt(rc, 16-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg { break } x := v_0.Args[0] if !(rc < 16) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 16-rc)) v.AddArg(x) return true } // match: (SRLconst [rc] (MOVBUreg x)) // cond: rc < 8 // result: (UBFX [armBFAuxInt(rc, 8-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg { break } x := v_0.Args[0] if !(rc < 8) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8-rc)) v.AddArg(x) return true } // match: (SRLconst [sc] (ANDconst [ac] x)) // cond: isARM64BFMask(sc, ac, sc) // result: (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } ac := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(sc, ac, sc)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc, arm64BFWidth(ac, sc))) v.AddArg(x) return true } // match: (SRLconst [sc] (UBFX [bfc] x)) // cond: sc < bfc.getARM64BFwidth() // result: (UBFX [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc < bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } // match: (SRLconst [sc] (UBFIZ [bfc] x)) // cond: sc == bfc.getARM64BFlsb() // result: (ANDconst [1< bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() // result: (UBFX [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFIZ { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc > bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64STP(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (STP [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (STP [off1+int32(off2)] {sym} ptr val1 val2 mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val1 := v_1 val2 := v_2 mem := v_3 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg4(ptr, val1, val2, mem) return true } // match: (STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (STP [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val1 := v_1 val2 := v_2 mem := v_3 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg4(ptr, val1, val2, mem) return true } // match: (STP [off] {sym} ptr (MOVDconst [0]) (MOVDconst [0]) mem) // result: (MOVQstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 || v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64SUB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUB x (MOVDconst [c])) // result: (SUBconst [c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (SUB a l:(MUL x y)) // cond: l.Uses==1 && clobber(l) // result: (MSUB a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MUL { break } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MSUB) v.AddArg3(a, x, y) return true } // match: (SUB a l:(MNEG x y)) // cond: l.Uses==1 && clobber(l) // result: (MADD a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MNEG { break } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MADD) v.AddArg3(a, x, y) return true } // match: (SUB a l:(MULW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MSUBW a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MULW { break } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MSUBW) v.AddArg3(a, x, y) return true } // match: (SUB a l:(MNEGW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MADDW a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MNEGW { break } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MADDW) v.AddArg3(a, x, y) return true } // match: (SUB x x) // result: (MOVDconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SUB x (SUB y z)) // result: (SUB (ADD x z) y) for { x := v_0 if v_1.Op != OpARM64SUB { break } z := v_1.Args[1] y := v_1.Args[0] v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADD, v.Type) v0.AddArg2(x, z) v.AddArg2(v0, y) return true } // match: (SUB (SUB x y) z) // result: (SUB x (ADD y z)) for { if v_0.Op != OpARM64SUB { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADD, y.Type) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } // match: (SUB x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (SUBshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (SUB x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (SUBshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64SUBshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (SUB x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (SUBshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64SUBshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64SUBconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SUBconst [c] (MOVDconst [d])) // result: (MOVDconst [d-c]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(d - c) return true } // match: (SUBconst [c] (SUBconst [d] x)) // result: (ADDconst [-c-d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SUBconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(-c - d) v.AddArg(x) return true } // match: (SUBconst [c] (ADDconst [d] x)) // result: (ADDconst [-c+d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ADDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(-c + d) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64SUBshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBshiftLL x (MOVDconst [c]) [d]) // result: (SUBconst x [int64(uint64(c)<>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (SUBshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64SUBshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBshiftRL x (MOVDconst [c]) [d]) // result: (SUBconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (SUBshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64TST(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (TST x (MOVDconst [c])) // result: (TSTconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (TST x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (TST x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (TST x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (TST x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64TSTW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (TSTW x (MOVDconst [c])) // result: (TSTWconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTWconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueARM64_OpARM64TSTWconst(v *Value) bool { v_0 := v.Args[0] // match: (TSTWconst (MOVDconst [x]) [y]) // result: (FlagConstant [logicFlags32(int32(x)&y)]) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(logicFlags32(int32(x) & y)) return true } return false } func rewriteValueARM64_OpARM64TSTconst(v *Value) bool { v_0 := v.Args[0] // match: (TSTconst (MOVDconst [x]) [y]) // result: (FlagConstant [logicFlags64(x&y)]) for { y := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(logicFlags64(x & y)) return true } return false } func rewriteValueARM64_OpARM64TSTshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TSTshiftLL (MOVDconst [c]) x [d]) // result: (TSTconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftLL x (MOVDconst [c]) [d]) // result: (TSTconst x [int64(uint64(c)< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftRA x (MOVDconst [c]) [d]) // result: (TSTconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64TSTshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TSTshiftRL (MOVDconst [c]) x [d]) // result: (TSTconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftRL x (MOVDconst [c]) [d]) // result: (TSTconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64TSTshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TSTshiftRO (MOVDconst [c]) x [d]) // result: (TSTconst [c] (RORconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftRO x (MOVDconst [c]) [d]) // result: (TSTconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64UBFIZ(v *Value) bool { v_0 := v.Args[0] // match: (UBFIZ [bfc] (SLLconst [sc] x)) // cond: sc < bfc.getARM64BFwidth() // result: (UBFIZ [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(sc < bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64UBFX(v *Value) bool { v_0 := v.Args[0] // match: (UBFX [bfc] (ANDconst [c] x)) // cond: isARM64BFMask(0, c, 0) && bfc.getARM64BFlsb() + bfc.getARM64BFwidth() <= arm64BFWidth(c, 0) // result: (UBFX [bfc] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(0, c, 0) && bfc.getARM64BFlsb()+bfc.getARM64BFwidth() <= arm64BFWidth(c, 0)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } // match: (UBFX [bfc] (SRLconst [sc] x)) // cond: sc+bfc.getARM64BFwidth()+bfc.getARM64BFlsb() < 64 // result: (UBFX [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth())] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64SRLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(sc+bfc.getARM64BFwidth()+bfc.getARM64BFlsb() < 64) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth())) v.AddArg(x) return true } // match: (UBFX [bfc] (SLLconst [sc] x)) // cond: sc == bfc.getARM64BFlsb() // result: (ANDconst [1< bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() // result: (UBFIZ [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(sc > bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64UDIV(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (UDIV x (MOVDconst [1])) // result: x for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.copyOf(x) return true } // match: (UDIV x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SRLconst [log64(c)] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } // match: (UDIV (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint64(c)/uint64(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) / uint64(d))) return true } return false } func rewriteValueARM64_OpARM64UDIVW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (UDIVW x (MOVDconst [c])) // cond: uint32(c)==1 // result: x for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(uint32(c) == 1) { break } v.copyOf(x) return true } // match: (UDIVW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) && is32Bit(c) // result: (SRLconst [log64(c)] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c) && is32Bit(c)) { break } v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } // match: (UDIVW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint32(c)/uint32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint32(c) / uint32(d))) return true } return false } func rewriteValueARM64_OpARM64UMOD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (UMOD x y) // result: (MSUB x y (UDIV x y)) for { if v.Type != typ.UInt64 { break } x := v_0 y := v_1 v.reset(OpARM64MSUB) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64UDIV, typ.UInt64) v0.AddArg2(x, y) v.AddArg3(x, y, v0) return true } // match: (UMOD _ (MOVDconst [1])) // result: (MOVDconst [0]) for { if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (UMOD x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (ANDconst [c-1] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c - 1) v.AddArg(x) return true } // match: (UMOD (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint64(c)%uint64(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) % uint64(d))) return true } return false } func rewriteValueARM64_OpARM64UMODW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (UMODW x y) // result: (MSUBW x y (UDIVW x y)) for { if v.Type != typ.UInt32 { break } x := v_0 y := v_1 v.reset(OpARM64MSUBW) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpARM64UDIVW, typ.UInt32) v0.AddArg2(x, y) v.AddArg3(x, y, v0) return true } // match: (UMODW _ (MOVDconst [c])) // cond: uint32(c)==1 // result: (MOVDconst [0]) for { if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(uint32(c) == 1) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (UMODW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) && is32Bit(c) // result: (ANDconst [c-1] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c) && is32Bit(c)) { break } v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c - 1) v.AddArg(x) return true } // match: (UMODW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint32(c)%uint32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint32(c) % uint32(d))) return true } return false } func rewriteValueARM64_OpARM64XOR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (XOR x (MOVDconst [c])) // result: (XORconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (XOR x x) // result: (MOVDconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (XOR x (MVN y)) // result: (EON x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MVN { continue } y := v_1.Args[0] v.reset(OpARM64EON) v.AddArg2(x, y) return true } break } // match: (XOR x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (XOR x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (XOR x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (XOR x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64XORconst(v *Value) bool { v_0 := v.Args[0] // match: (XORconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (XORconst [-1] x) // result: (MVN x) for { if auxIntToInt64(v.AuxInt) != -1 { break } x := v_0 v.reset(OpARM64MVN) v.AddArg(x) return true } // match: (XORconst [c] (MOVDconst [d])) // result: (MOVDconst [c^d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c ^ d) return true } // match: (XORconst [c] (XORconst [d] x)) // result: (XORconst [c^d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64XORconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c ^ d) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64XORshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (XORshiftLL (MOVDconst [c]) x [d]) // result: (XORconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftLL x (MOVDconst [c]) [d]) // result: (XORconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) // result: (REV16W x) for { if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (XORshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff // result: (REV16W x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (XORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) // result: (REV16 x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { break } v.reset(OpARM64REV16) v.AddArg(x) return true } // match: (XORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) // result: (REV16 (ANDconst [0xffffffff] x)) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16) v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) v0.AuxInt = int64ToAuxInt(0xffffffff) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftLL [c] (SRLconst x [64-c]) x2) // result: (EXTRconst [64-c] x2 x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { break } x := v_0.Args[0] x2 := v_1 v.reset(OpARM64EXTRconst) v.AuxInt = int64ToAuxInt(64 - c) v.AddArg2(x2, x) return true } // match: (XORshiftLL [c] (UBFX [bfc] x) x2) // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) // result: (EXTRWconst [32-c] x2 x) for { t := v.Type c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] x2 := v_1 if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { break } v.reset(OpARM64EXTRWconst) v.AuxInt = int64ToAuxInt(32 - c) v.AddArg2(x2, x) return true } return false } func rewriteValueARM64_OpARM64XORshiftRA(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (XORshiftRA (MOVDconst [c]) x [d]) // result: (XORconst [c] (SRAconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftRA x (MOVDconst [c]) [d]) // result: (XORconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (XORshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64XORshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (XORshiftRL (MOVDconst [c]) x [d]) // result: (XORconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftRL x (MOVDconst [c]) [d]) // result: (XORconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (XORshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64XORshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (XORshiftRO (MOVDconst [c]) x [d]) // result: (XORconst [c] (RORconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftRO x (MOVDconst [c]) [d]) // result: (XORconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } // match: (XORshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpAddr(v *Value) bool { v_0 := v.Args[0] // match: (Addr {sym} base) // result: (MOVDaddr {sym} base) for { sym := auxToSym(v.Aux) base := v_0 v.reset(OpARM64MOVDaddr) v.Aux = symToAux(sym) v.AddArg(base) return true } } func rewriteValueARM64_OpAtomicAnd32(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd32 ptr val mem) // result: (Select1 (LoweredAtomicAnd32 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd32, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicAnd32Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd32Variant ptr val mem) // result: (Select1 (LoweredAtomicAnd32Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd32Variant, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicAnd8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd8 ptr val mem) // result: (Select1 (LoweredAtomicAnd8 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd8, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicAnd8Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd8Variant ptr val mem) // result: (Select1 (LoweredAtomicAnd8Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd8Variant, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr32(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr32 ptr val mem) // result: (Select1 (LoweredAtomicOr32 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr32, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr32Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr32Variant ptr val mem) // result: (Select1 (LoweredAtomicOr32Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr32Variant, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr8 ptr val mem) // result: (Select1 (LoweredAtomicOr8 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr8, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr8Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr8Variant ptr val mem) // result: (Select1 (LoweredAtomicOr8Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr8Variant, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAvg64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Avg64u x y) // result: (ADD (SRLconst (SUB x y) [1]) y) for { t := v.Type x := v_0 y := v_1 v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, t) v0.AuxInt = int64ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpARM64SUB, t) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg2(v0, y) return true } } func rewriteValueARM64_OpBitLen32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // result: (SUB (MOVDconst [32]) (CLZW x)) for { x := v_0 v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(32) v1 := b.NewValue0(v.Pos, OpARM64CLZW, typ.Int) v1.AddArg(x) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpBitLen64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // result: (SUB (MOVDconst [64]) (CLZ x)) for { x := v_0 v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(64) v1 := b.NewValue0(v.Pos, OpARM64CLZ, typ.Int) v1.AddArg(x) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpBitRev16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitRev16 x) // result: (SRLconst [48] (RBIT x)) for { x := v_0 v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(48) v0 := b.NewValue0(v.Pos, OpARM64RBIT, typ.UInt64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpBitRev8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitRev8 x) // result: (SRLconst [56] (RBIT x)) for { x := v_0 v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(56) v0 := b.NewValue0(v.Pos, OpARM64RBIT, typ.UInt64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CondSelect x y boolval) // cond: flagArg(boolval) != nil // result: (CSEL [boolval.Op] x y flagArg(boolval)) for { x := v_0 y := v_1 boolval := v_2 if !(flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(boolval.Op) v.AddArg3(x, y, flagArg(boolval)) return true } // match: (CondSelect x y boolval) // cond: flagArg(boolval) == nil // result: (CSEL [OpARM64NotEqual] x y (TSTWconst [1] boolval)) for { x := v_0 y := v_1 boolval := v_2 if !(flagArg(boolval) == nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(1) v0.AddArg(boolval) v.AddArg3(x, y, v0) return true } return false } func rewriteValueARM64_OpConst16(v *Value) bool { // match: (Const16 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt16(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConst32(v *Value) bool { // match: (Const32 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt32(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConst32F(v *Value) bool { // match: (Const32F [val]) // result: (FMOVSconst [float64(val)]) for { val := auxIntToFloat32(v.AuxInt) v.reset(OpARM64FMOVSconst) v.AuxInt = float64ToAuxInt(float64(val)) return true } } func rewriteValueARM64_OpConst64(v *Value) bool { // match: (Const64 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt64(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConst64F(v *Value) bool { // match: (Const64F [val]) // result: (FMOVDconst [float64(val)]) for { val := auxIntToFloat64(v.AuxInt) v.reset(OpARM64FMOVDconst) v.AuxInt = float64ToAuxInt(float64(val)) return true } } func rewriteValueARM64_OpConst8(v *Value) bool { // match: (Const8 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt8(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConstBool(v *Value) bool { // match: (ConstBool [t]) // result: (MOVDconst [b2i(t)]) for { t := auxIntToBool(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(t)) return true } } func rewriteValueARM64_OpConstNil(v *Value) bool { // match: (ConstNil) // result: (MOVDconst [0]) for { v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } } func rewriteValueARM64_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (CLZW (RBITW (ORconst [0x10000] x))) for { t := v.Type x := v_0 v.reset(OpARM64CLZW) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64RBITW, typ.UInt32) v1 := b.NewValue0(v.Pos, OpARM64ORconst, typ.UInt32) v1.AuxInt = int64ToAuxInt(0x10000) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Ctz32 x) // result: (CLZW (RBITW x)) for { t := v.Type x := v_0 v.reset(OpARM64CLZW) v0 := b.NewValue0(v.Pos, OpARM64RBITW, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Ctz64 x) // result: (CLZ (RBIT x)) for { t := v.Type x := v_0 v.reset(OpARM64CLZ) v0 := b.NewValue0(v.Pos, OpARM64RBIT, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (CLZW (RBITW (ORconst [0x100] x))) for { t := v.Type x := v_0 v.reset(OpARM64CLZW) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64RBITW, typ.UInt32) v1 := b.NewValue0(v.Pos, OpARM64ORconst, typ.UInt32) v1.AuxInt = int64ToAuxInt(0x100) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 [false] x y) // result: (DIVW (SignExt16to32 x) (SignExt16to32 y)) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpARM64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (UDIVW (ZeroExt16to32 x) (ZeroExt16to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UDIVW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Div32 [false] x y) // result: (DIVW x y) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpARM64DIVW) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Div64 [false] x y) // result: (DIV x y) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpARM64DIV) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (DIVW (SignExt8to32 x) (SignExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (UDIVW (ZeroExt8to32 x) (ZeroExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UDIVW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq16 x y) // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32 x y) // result: (Equal (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32F x y) // result: (Equal (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64 x y) // result: (Equal (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64F x y) // result: (Equal (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq8 x y) // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqB x y) // result: (XOR (MOVDconst [1]) (XOR x y)) for { x := v_0 y := v_1 v.reset(OpARM64XOR) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpARM64XOR, typ.Bool) v1.AddArg2(x, y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqPtr x y) // result: (Equal (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpFMA(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMA x y z) // result: (FMADDD z x y) for { x := v_0 y := v_1 z := v_2 v.reset(OpARM64FMADDD) v.AddArg3(z, x, y) return true } } func rewriteValueARM64_OpHmul32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Hmul32 x y) // result: (SRAconst (MULL x y) [32]) for { x := v_0 y := v_1 v.reset(OpARM64SRAconst) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpARM64MULL, typ.Int64) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpHmul32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Hmul32u x y) // result: (SRAconst (UMULL x y) [32]) for { x := v_0 y := v_1 v.reset(OpARM64SRAconst) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpARM64UMULL, typ.UInt64) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsInBounds idx len) // result: (LessThanU (CMP idx len)) for { idx := v_0 len := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueARM64_OpIsNonNil(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (IsNonNil ptr) // result: (NotEqual (CMPconst [0] ptr)) for { ptr := v_0 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(0) v0.AddArg(ptr) v.AddArg(v0) return true } } func rewriteValueARM64_OpIsSliceInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsSliceInBounds idx len) // result: (LessEqualU (CMP idx len)) for { idx := v_0 len := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq16 x y) // result: (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq16U x zero:(MOVDconst [0])) // result: (Eq16 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq16) v.AddArg2(x, zero) return true } // match: (Leq16U (MOVDconst [1]) x) // result: (Neq16 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq16U x y) // result: (LessEqualU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32 x y) // result: (LessEqual (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32F x y) // result: (LessEqualF (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualF) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq32U x zero:(MOVDconst [0])) // result: (Eq32 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq32) v.AddArg2(x, zero) return true } // match: (Leq32U (MOVDconst [1]) x) // result: (Neq32 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq32U x y) // result: (LessEqualU (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64 x y) // result: (LessEqual (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64F x y) // result: (LessEqualF (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualF) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq64U x zero:(MOVDconst [0])) // result: (Eq64 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq64) v.AddArg2(x, zero) return true } // match: (Leq64U (MOVDconst [1]) x) // result: (Neq64 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq64U x y) // result: (LessEqualU (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq8 x y) // result: (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq8U x zero:(MOVDconst [0])) // result: (Eq8 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq8) v.AddArg2(x, zero) return true } // match: (Leq8U (MOVDconst [1]) x) // result: (Neq8 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq8U x y) // result: (LessEqualU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less16 x y) // result: (LessThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less16U zero:(MOVDconst [0]) x) // result: (Neq16 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq16) v.AddArg2(zero, x) return true } // match: (Less16U x (MOVDconst [1])) // result: (Eq16 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less16U x y) // result: (LessThanU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 x y) // result: (LessThan (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32F x y) // result: (LessThanF (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanF) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less32U zero:(MOVDconst [0]) x) // result: (Neq32 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq32) v.AddArg2(zero, x) return true } // match: (Less32U x (MOVDconst [1])) // result: (Eq32 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less32U x y) // result: (LessThanU (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 x y) // result: (LessThan (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64F x y) // result: (LessThanF (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanF) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less64U zero:(MOVDconst [0]) x) // result: (Neq64 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq64) v.AddArg2(zero, x) return true } // match: (Less64U x (MOVDconst [1])) // result: (Eq64 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less64U x y) // result: (LessThanU (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less8 x y) // result: (LessThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less8U zero:(MOVDconst [0]) x) // result: (Neq8 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq8) v.AddArg2(zero, x) return true } // match: (Less8U x (MOVDconst [1])) // result: (Eq8 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less8U x y) // result: (LessThanU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Load ptr mem) // cond: t.IsBoolean() // result: (MOVBUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsBoolean()) { break } v.reset(OpARM64MOVBUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is8BitInt(t) && t.IsSigned()) // result: (MOVBload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is8BitInt(t) && t.IsSigned()) { break } v.reset(OpARM64MOVBload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is8BitInt(t) && !t.IsSigned()) // result: (MOVBUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is8BitInt(t) && !t.IsSigned()) { break } v.reset(OpARM64MOVBUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is16BitInt(t) && t.IsSigned()) // result: (MOVHload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t) && t.IsSigned()) { break } v.reset(OpARM64MOVHload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is16BitInt(t) && !t.IsSigned()) // result: (MOVHUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t) && !t.IsSigned()) { break } v.reset(OpARM64MOVHUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is32BitInt(t) && t.IsSigned()) // result: (MOVWload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t) && t.IsSigned()) { break } v.reset(OpARM64MOVWload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is32BitInt(t) && !t.IsSigned()) // result: (MOVWUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t) && !t.IsSigned()) { break } v.reset(OpARM64MOVWUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpARM64MOVDload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (FMOVSload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitFloat(t)) { break } v.reset(OpARM64FMOVSload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (FMOVDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitFloat(t)) { break } v.reset(OpARM64FMOVDload) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpLocalAddr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (LocalAddr {sym} base mem) // cond: t.Elem().HasPointers() // result: (MOVDaddr {sym} (SPanchored base mem)) for { t := v.Type sym := auxToSym(v.Aux) base := v_0 mem := v_1 if !(t.Elem().HasPointers()) { break } v.reset(OpARM64MOVDaddr) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr) v0.AddArg2(base, mem) v.AddArg(v0) return true } // match: (LocalAddr {sym} base _) // cond: !t.Elem().HasPointers() // result: (MOVDaddr {sym} base) for { t := v.Type sym := auxToSym(v.Aux) base := v_0 if !(!t.Elem().HasPointers()) { break } v.reset(OpARM64MOVDaddr) v.Aux = symToAux(sym) v.AddArg(base) return true } return false } func rewriteValueARM64_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16 x y) // result: (MODW (SignExt16to32 x) (SignExt16to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64MODW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (UMODW (ZeroExt16to32 x) (ZeroExt16to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UMODW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mod32 x y) // result: (MODW x y) for { x := v_0 y := v_1 v.reset(OpARM64MODW) v.AddArg2(x, y) return true } } func rewriteValueARM64_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mod64 x y) // result: (MOD x y) for { x := v_0 y := v_1 v.reset(OpARM64MOD) v.AddArg2(x, y) return true } } func rewriteValueARM64_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (MODW (SignExt8to32 x) (SignExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64MODW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (UMODW (ZeroExt8to32 x) (ZeroExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UMODW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBUload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [2] dst src mem) // result: (MOVHstore dst (MOVHUload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVHstore) v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBUload [2] src mem) (MOVHstore dst (MOVHUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AuxInt = int32ToAuxInt(2) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [4] dst src mem) // result: (MOVWstore dst (MOVWUload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVWstore) v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBUload [4] src mem) (MOVWstore dst (MOVWUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [6] dst src mem) // result: (MOVHstore [4] dst (MOVHUload [4] src mem) (MOVWstore dst (MOVWUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [7] dst src mem) // result: (MOVWstore [3] dst (MOVWUload [3] src mem) (MOVWstore dst (MOVWUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [8] dst src mem) // result: (MOVDstore dst (MOVDload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBUload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [10] dst src mem) // result: (MOVHstore [8] dst (MOVHUload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [11] dst src mem) // result: (MOVDstore [3] dst (MOVDload [3] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 11 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [12] dst src mem) // result: (MOVWstore [8] dst (MOVWUload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [13] dst src mem) // result: (MOVDstore [5] dst (MOVDload [5] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 13 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(5) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(5) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [14] dst src mem) // result: (MOVDstore [6] dst (MOVDload [6] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 14 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(6) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(6) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [15] dst src mem) // result: (MOVDstore [7] dst (MOVDload [7] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 15 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(7) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(7) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [16] dst src mem) // result: (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v.AddArg4(dst, v0, v2, mem) return true } // match: (Move [32] dst src mem) // result: (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AuxInt = int32ToAuxInt(16) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v5.AddArg2(src, mem) v4.AddArg(v5) v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v6.AddArg(v5) v3.AddArg4(dst, v4, v6, mem) v.AddArg4(dst, v0, v2, v3) return true } // match: (Move [48] dst src mem) // result: (STP [32] dst (Select0 (LDP [32] src mem)) (Select1 (LDP [32] src mem)) (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AuxInt = int32ToAuxInt(32) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v3.AuxInt = int32ToAuxInt(16) v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v5.AuxInt = int32ToAuxInt(16) v5.AddArg2(src, mem) v4.AddArg(v5) v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v6.AddArg(v5) v7 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v9 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v9.AddArg2(src, mem) v8.AddArg(v9) v10 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v10.AddArg(v9) v7.AddArg4(dst, v8, v10, mem) v3.AddArg4(dst, v4, v6, v7) v.AddArg4(dst, v0, v2, v3) return true } // match: (Move [64] dst src mem) // result: (STP [48] dst (Select0 (LDP [48] src mem)) (Select1 (LDP [48] src mem)) (STP [32] dst (Select0 (LDP [32] src mem)) (Select1 (LDP [32] src mem)) (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(48) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AuxInt = int32ToAuxInt(48) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v3.AuxInt = int32ToAuxInt(32) v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v5.AuxInt = int32ToAuxInt(32) v5.AddArg2(src, mem) v4.AddArg(v5) v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v6.AddArg(v5) v7 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v7.AuxInt = int32ToAuxInt(16) v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v9 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v9.AuxInt = int32ToAuxInt(16) v9.AddArg2(src, mem) v8.AddArg(v9) v10 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v10.AddArg(v9) v11 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v12 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v13 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v13.AddArg2(src, mem) v12.AddArg(v13) v14 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v14.AddArg(v13) v11.AddArg4(dst, v12, v14, mem) v7.AddArg4(dst, v8, v10, v11) v3.AddArg4(dst, v4, v6, v7) v.AddArg4(dst, v0, v2, v3) return true } // match: (Move [s] dst src mem) // cond: s%16 != 0 && s%16 <= 8 && s > 16 // result: (Move [8] (OffPtr dst [s-8]) (OffPtr src [s-8]) (Move [s-s%16] dst src mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s%16 != 0 && s%16 <= 8 && s > 16) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s - 8) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s - 8) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(s - s%16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s%16 != 0 && s%16 > 8 && s > 16 // result: (Move [16] (OffPtr dst [s-16]) (OffPtr src [s-16]) (Move [s-s%16] dst src mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s%16 != 0 && s%16 > 8 && s > 16) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s - 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(s - s%16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s) // result: (DUFFCOPY [8 * (64 - s/16)] dst src mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s)) { break } v.reset(OpARM64DUFFCOPY) v.AuxInt = int64ToAuxInt(8 * (64 - s/16)) v.AddArg3(dst, src, mem) return true } // match: (Move [s] dst src mem) // cond: s%16 == 0 && (s > 16*64 || config.noDuffDevice) && logLargeCopy(v, s) // result: (LoweredMove dst src (ADDconst src [s-16]) mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s%16 == 0 && (s > 16*64 || config.noDuffDevice) && logLargeCopy(v, s)) { break } v.reset(OpARM64LoweredMove) v0 := b.NewValue0(v.Pos, OpARM64ADDconst, src.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(src) v.AddArg4(dst, src, v0, mem) return true } return false } func rewriteValueARM64_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq16 x y) // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32 x y) // result: (NotEqual (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32F x y) // result: (NotEqual (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64 x y) // result: (NotEqual (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64F x y) // result: (NotEqual (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq8 x y) // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqPtr x y) // result: (NotEqual (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNot(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Not x) // result: (XOR (MOVDconst [1]) x) for { x := v_0 v.reset(OpARM64XOR) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(1) v.AddArg2(v0, x) return true } } func rewriteValueARM64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] // match: (OffPtr [off] ptr:(SP)) // cond: is32Bit(off) // result: (MOVDaddr [int32(off)] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 if ptr.Op != OpSP || !(is32Bit(off)) { break } v.reset(OpARM64MOVDaddr) v.AuxInt = int32ToAuxInt(int32(off)) v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDconst [off] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(off) v.AddArg(ptr) return true } } func rewriteValueARM64_OpPanicBounds(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 0) { break } v.reset(OpARM64LoweredPanicBoundsA) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 1) { break } v.reset(OpARM64LoweredPanicBoundsB) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 2) { break } v.reset(OpARM64LoweredPanicBoundsC) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } return false } func rewriteValueARM64_OpPopCount16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (FMOVDfpgp (VUADDLV (VCNT (FMOVDgpfp (ZeroExt16to64 x))))) for { t := v.Type x := v_0 v.reset(OpARM64FMOVDfpgp) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64) v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64) v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(x) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpPopCount32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount32 x) // result: (FMOVDfpgp (VUADDLV (VCNT (FMOVDgpfp (ZeroExt32to64 x))))) for { t := v.Type x := v_0 v.reset(OpARM64FMOVDfpgp) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64) v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64) v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpPopCount64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount64 x) // result: (FMOVDfpgp (VUADDLV (VCNT (FMOVDgpfp x)))) for { t := v.Type x := v_0 v.reset(OpARM64FMOVDfpgp) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64) v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64) v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpPrefetchCache(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (PrefetchCache addr mem) // result: (PRFM [0] addr mem) for { addr := v_0 mem := v_1 v.reset(OpARM64PRFM) v.AuxInt = int64ToAuxInt(0) v.AddArg2(addr, mem) return true } } func rewriteValueARM64_OpPrefetchCacheStreamed(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (PrefetchCacheStreamed addr mem) // result: (PRFM [1] addr mem) for { addr := v_0 mem := v_1 v.reset(OpARM64PRFM) v.AuxInt = int64ToAuxInt(1) v.AddArg2(addr, mem) return true } } func rewriteValueARM64_OpPubBarrier(v *Value) bool { v_0 := v.Args[0] // match: (PubBarrier mem) // result: (DMB [0xe] mem) for { mem := v_0 v.reset(OpARM64DMB) v.AuxInt = int64ToAuxInt(0xe) v.AddArg(mem) return true } } func rewriteValueARM64_OpRotateLeft16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (RotateLeft16 x (MOVDconst [c])) // result: (Or16 (Lsh16x64 x (MOVDconst [c&15])) (Rsh16Ux64 x (MOVDconst [-c&15]))) for { t := v.Type x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(c & 15) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpRsh16Ux64, t) v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v3.AuxInt = int64ToAuxInt(-c & 15) v2.AddArg2(x, v3) v.AddArg2(v0, v2) return true } // match: (RotateLeft16 x y) // result: (RORW (ORshiftLL (ZeroExt16to32 x) (ZeroExt16to32 x) [16]) (NEG y)) for { t := v.Type x := v_0 y := v_1 v.reset(OpARM64RORW) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64ORshiftLL, typ.UInt32) v0.AuxInt = int64ToAuxInt(16) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v2 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) v2.AddArg(y) v.AddArg2(v0, v2) return true } } func rewriteValueARM64_OpRotateLeft32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (RotateLeft32 x y) // result: (RORW x (NEG y)) for { x := v_0 y := v_1 v.reset(OpARM64RORW) v0 := b.NewValue0(v.Pos, OpARM64NEG, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } } func rewriteValueARM64_OpRotateLeft64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (RotateLeft64 x y) // result: (ROR x (NEG y)) for { x := v_0 y := v_1 v.reset(OpARM64ROR) v0 := b.NewValue0(v.Pos, OpARM64NEG, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } } func rewriteValueARM64_OpRotateLeft8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (RotateLeft8 x (MOVDconst [c])) // result: (Or8 (Lsh8x64 x (MOVDconst [c&7])) (Rsh8Ux64 x (MOVDconst [-c&7]))) for { t := v.Type x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(c & 7) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpRsh8Ux64, t) v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v3.AuxInt = int64ToAuxInt(-c & 7) v2.AddArg2(x, v3) v.AddArg2(v0, v2) return true } // match: (RotateLeft8 x y) // result: (OR (SLL x (ANDconst [7] y)) (SRL (ZeroExt8to64 x) (ANDconst [7] (NEG y)))) for { t := v.Type x := v_0 y := v_1 v.reset(OpARM64OR) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v1 := b.NewValue0(v.Pos, OpARM64ANDconst, typ.Int64) v1.AuxInt = int64ToAuxInt(7) v1.AddArg(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpARM64SRL, t) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(x) v4 := b.NewValue0(v.Pos, OpARM64ANDconst, typ.Int64) v4.AuxInt = int64ToAuxInt(7) v5 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) v5.AddArg(y) v4.AddArg(v5) v2.AddArg2(v3, v4) v.AddArg2(v0, v2) return true } } func rewriteValueARM64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpSelect0(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uhilo x y)) // result: (UMULH x y) for { if v_0.Op != OpMul64uhilo { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64UMULH) v.AddArg2(x, y) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCSflags x y (Select1 (ADDSconstflags [-1] c)))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64ADCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpARM64ADDSconstflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AuxInt = int64ToAuxInt(-1) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y bo)) // result: (Select0 (SBCSflags x y (Select1 (NEGSflags bo)))) for { if v_0.Op != OpSub64borrow { break } bo := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64SBCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpARM64NEGSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(bo) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Mul64uover x y)) // result: (MUL x y) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MUL) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpSelect1(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uhilo x y)) // result: (MUL x y) for { if v_0.Op != OpMul64uhilo { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MUL) v.AddArg2(x, y) return true } // match: (Select1 (Add64carry x y c)) // result: (ADCzerocarry (Select1 (ADCSflags x y (Select1 (ADDSconstflags [-1] c))))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpARM64ADCzerocarry) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64ADCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v2 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v3 := b.NewValue0(v.Pos, OpARM64ADDSconstflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v3.AuxInt = int64ToAuxInt(-1) v3.AddArg(c) v2.AddArg(v3) v1.AddArg3(x, y, v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y bo)) // result: (NEG (NGCzerocarry (Select1 (SBCSflags x y (Select1 (NEGSflags bo)))))) for { if v_0.Op != OpSub64borrow { break } bo := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpARM64NEG) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64NGCzerocarry, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpARM64SBCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpARM64NEGSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v4.AddArg(bo) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul64uover x y)) // result: (NotEqual (CMPconst (UMULH x y) [0])) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64UMULH, typ.UInt64) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVDstore _ (MOVDconst [sz]) s2:(MOVDstore _ src s3:(MOVDstore {t} _ dst mem))))) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(s1, s2, s3, call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpARM64CALLstatic || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpARM64MOVDstore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpARM64MOVDconst { break } sz := auxIntToInt64(s1_1.AuxInt) s2 := s1.Args[2] if s2.Op != OpARM64MOVDstore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpARM64MOVDstore { break } mem := s3.Args[2] dst := s3.Args[1] if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVDconst [sz]) mem)) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpARM64CALLstatic || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpARM64MOVDconst { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } return false } func rewriteValueARM64_OpSlicemask(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Slicemask x) // result: (SRAconst (NEG x) [63]) for { t := v.Type x := v_0 v.reset(OpARM64SRAconst) v.AuxInt = int64ToAuxInt(63) v0 := b.NewValue0(v.Pos, OpARM64NEG, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (Store {t} ptr val mem) // cond: t.Size() == 1 // result: (MOVBstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 1) { break } v.reset(OpARM64MOVBstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 2 // result: (MOVHstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 2) { break } v.reset(OpARM64MOVHstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && !t.IsFloat() // result: (MOVWstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && !t.IsFloat()) { break } v.reset(OpARM64MOVWstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && !t.IsFloat() // result: (MOVDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && !t.IsFloat()) { break } v.reset(OpARM64MOVDstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && t.IsFloat() // result: (FMOVSstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && t.IsFloat()) { break } v.reset(OpARM64FMOVSstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && t.IsFloat() // result: (FMOVDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && t.IsFloat()) { break } v.reset(OpARM64FMOVDstore) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [0] _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_1 v.copyOf(mem) return true } // match: (Zero [1] ptr mem) // result: (MOVBstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [2] ptr mem) // result: (MOVHstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVHstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [4] ptr mem) // result: (MOVWstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVWstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [3] ptr mem) // result: (MOVBstore [2] ptr (MOVDconst [0]) (MOVHstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [5] ptr mem) // result: (MOVBstore [4] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [6] ptr mem) // result: (MOVHstore [4] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [7] ptr mem) // result: (MOVWstore [3] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [8] ptr mem) // result: (MOVDstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [9] ptr mem) // result: (MOVBstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [10] ptr mem) // result: (MOVHstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [11] ptr mem) // result: (MOVDstore [3] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 11 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [12] ptr mem) // result: (MOVWstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [13] ptr mem) // result: (MOVDstore [5] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 13 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(5) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [14] ptr mem) // result: (MOVDstore [6] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 14 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(6) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [15] ptr mem) // result: (MOVDstore [7] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 15 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(7) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [16] ptr mem) // result: (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(0) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg4(ptr, v0, v0, mem) return true } // match: (Zero [32] ptr mem) // result: (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v1.AuxInt = int32ToAuxInt(0) v1.AddArg4(ptr, v0, v0, mem) v.AddArg4(ptr, v0, v0, v1) return true } // match: (Zero [48] ptr mem) // result: (STP [32] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v1.AuxInt = int32ToAuxInt(16) v2 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v2.AuxInt = int32ToAuxInt(0) v2.AddArg4(ptr, v0, v0, mem) v1.AddArg4(ptr, v0, v0, v2) v.AddArg4(ptr, v0, v0, v1) return true } // match: (Zero [64] ptr mem) // result: (STP [48] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [32] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(48) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v1.AuxInt = int32ToAuxInt(32) v2 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v2.AuxInt = int32ToAuxInt(16) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v3.AuxInt = int32ToAuxInt(0) v3.AddArg4(ptr, v0, v0, mem) v2.AddArg4(ptr, v0, v0, v3) v1.AddArg4(ptr, v0, v0, v2) v.AddArg4(ptr, v0, v0, v1) return true } // match: (Zero [s] ptr mem) // cond: s%16 != 0 && s%16 <= 8 && s > 16 // result: (Zero [8] (OffPtr ptr [s-8]) (Zero [s-s%16] ptr mem)) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 != 0 && s%16 <= 8 && s > 16) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpOffPtr, ptr.Type) v0.AuxInt = int64ToAuxInt(s - 8) v0.AddArg(ptr) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(s - s%16) v1.AddArg2(ptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] ptr mem) // cond: s%16 != 0 && s%16 > 8 && s > 16 // result: (Zero [16] (OffPtr ptr [s-16]) (Zero [s-s%16] ptr mem)) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 != 0 && s%16 > 8 && s > 16) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, ptr.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(ptr) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(s - s%16) v1.AddArg2(ptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] ptr mem) // cond: s%16 == 0 && s > 64 && s <= 16*64 && !config.noDuffDevice // result: (DUFFZERO [4 * (64 - s/16)] ptr mem) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 == 0 && s > 64 && s <= 16*64 && !config.noDuffDevice) { break } v.reset(OpARM64DUFFZERO) v.AuxInt = int64ToAuxInt(4 * (64 - s/16)) v.AddArg2(ptr, mem) return true } // match: (Zero [s] ptr mem) // cond: s%16 == 0 && (s > 16*64 || config.noDuffDevice) // result: (LoweredZero ptr (ADDconst [s-16] ptr) mem) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 == 0 && (s > 16*64 || config.noDuffDevice)) { break } v.reset(OpARM64LoweredZero) v0 := b.NewValue0(v.Pos, OpARM64ADDconst, ptr.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(ptr) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteBlockARM64(b *Block) bool { typ := &b.Func.Config.Types switch b.Kind { case BlockARM64EQ: // match: (EQ (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (EQ (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (EQ (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMP x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMP { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPW x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPW { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] x) yes no) // result: (Z x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64Z, x) return true } // match: (EQ (CMPWconst [0] x) yes no) // result: (ZW x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64ZW, x) return true } // match: (EQ (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (TSTconst [c] x) yes no) // cond: oneBit(c) // result: (TBZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64TSTconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (EQ (TSTWconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64TSTWconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (EQ (FlagConstant [fc]) yes no) // cond: fc.eq() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.eq()) { break } b.Reset(BlockFirst) return true } // match: (EQ (FlagConstant [fc]) yes no) // cond: !fc.eq() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.eq()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64EQ, cmp) return true } case BlockARM64FGE: // match: (FGE (InvertFlags cmp) yes no) // result: (FLE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FLE, cmp) return true } case BlockARM64FGT: // match: (FGT (InvertFlags cmp) yes no) // result: (FLT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FLT, cmp) return true } case BlockARM64FLE: // match: (FLE (InvertFlags cmp) yes no) // result: (FGE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FGE, cmp) return true } case BlockARM64FLT: // match: (FLT (InvertFlags cmp) yes no) // result: (FGT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FGT, cmp) return true } case BlockARM64GE: // match: (GE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GE (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GE, v0) return true } break } // match: (GE (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GE (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GE, v0) return true } // match: (GE (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GE (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GE, v0) return true } break } // match: (GE (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GE (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GE, v0) return true } // match: (GE (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GEnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GEnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GEnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GEnoov, v0) return true } break } // match: (GE (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GEnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GEnoov, v0) return true } break } // match: (GE (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] x) yes no) // result: (TBZ [31] x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(31) return true } // match: (GE (CMPconst [0] x) yes no) // result: (TBZ [63] x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(63) return true } // match: (GE (FlagConstant [fc]) yes no) // cond: fc.ge() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ge()) { break } b.Reset(BlockFirst) return true } // match: (GE (FlagConstant [fc]) yes no) // cond: !fc.ge() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ge()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LE, cmp) return true } case BlockARM64GEnoov: // match: (GEnoov (FlagConstant [fc]) yes no) // cond: fc.geNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.geNoov()) { break } b.Reset(BlockFirst) return true } // match: (GEnoov (FlagConstant [fc]) yes no) // cond: !fc.geNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.geNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GEnoov (InvertFlags cmp) yes no) // result: (LEnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LEnoov, cmp) return true } case BlockARM64GT: // match: (GT (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GT (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GT, v0) return true } break } // match: (GT (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GT (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GT, v0) return true } // match: (GT (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GT (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GT, v0) return true } break } // match: (GT (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GT (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GT, v0) return true } // match: (GT (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GTnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GTnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GTnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GTnoov, v0) return true } break } // match: (GT (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GTnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GTnoov, v0) return true } break } // match: (GT (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (FlagConstant [fc]) yes no) // cond: fc.gt() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.gt()) { break } b.Reset(BlockFirst) return true } // match: (GT (FlagConstant [fc]) yes no) // cond: !fc.gt() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.gt()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LT, cmp) return true } case BlockARM64GTnoov: // match: (GTnoov (FlagConstant [fc]) yes no) // cond: fc.gtNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.gtNoov()) { break } b.Reset(BlockFirst) return true } // match: (GTnoov (FlagConstant [fc]) yes no) // cond: !fc.gtNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.gtNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GTnoov (InvertFlags cmp) yes no) // result: (LTnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LTnoov, cmp) return true } case BlockIf: // match: (If (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpARM64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64EQ, cc) return true } // match: (If (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpARM64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64NE, cc) return true } // match: (If (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpARM64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LT, cc) return true } // match: (If (LessThanU cc) yes no) // result: (ULT cc yes no) for b.Controls[0].Op == OpARM64LessThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULT, cc) return true } // match: (If (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpARM64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LE, cc) return true } // match: (If (LessEqualU cc) yes no) // result: (ULE cc yes no) for b.Controls[0].Op == OpARM64LessEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULE, cc) return true } // match: (If (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpARM64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GT, cc) return true } // match: (If (GreaterThanU cc) yes no) // result: (UGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGT, cc) return true } // match: (If (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GE, cc) return true } // match: (If (GreaterEqualU cc) yes no) // result: (UGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGE, cc) return true } // match: (If (LessThanF cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpARM64LessThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLT, cc) return true } // match: (If (LessEqualF cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpARM64LessEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLE, cc) return true } // match: (If (GreaterThanF cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGT, cc) return true } // match: (If (GreaterEqualF cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGE, cc) return true } // match: (If cond yes no) // result: (TBNZ [0] cond yes no) for { cond := b.Controls[0] b.resetWithControl(BlockARM64TBNZ, cond) b.AuxInt = int64ToAuxInt(0) return true } case BlockJumpTable: // match: (JumpTable idx) // result: (JUMPTABLE {makeJumpTableSym(b)} idx (MOVDaddr {makeJumpTableSym(b)} (SB))) for { idx := b.Controls[0] v0 := b.NewValue0(b.Pos, OpARM64MOVDaddr, typ.Uintptr) v0.Aux = symToAux(makeJumpTableSym(b)) v1 := b.NewValue0(b.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) b.resetWithControl2(BlockARM64JUMPTABLE, idx, v0) b.Aux = symToAux(makeJumpTableSym(b)) return true } case BlockARM64LE: // match: (LE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LE (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LE, v0) return true } break } // match: (LE (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LE (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LE, v0) return true } // match: (LE (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LE (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LE, v0) return true } break } // match: (LE (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LE (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LE, v0) return true } // match: (LE (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LEnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LEnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LEnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LEnoov, v0) return true } break } // match: (LE (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LEnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LEnoov, v0) return true } break } // match: (LE (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (FlagConstant [fc]) yes no) // cond: fc.le() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.le()) { break } b.Reset(BlockFirst) return true } // match: (LE (FlagConstant [fc]) yes no) // cond: !fc.le() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.le()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GE, cmp) return true } case BlockARM64LEnoov: // match: (LEnoov (FlagConstant [fc]) yes no) // cond: fc.leNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.leNoov()) { break } b.Reset(BlockFirst) return true } // match: (LEnoov (FlagConstant [fc]) yes no) // cond: !fc.leNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.leNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LEnoov (InvertFlags cmp) yes no) // result: (GEnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GEnoov, cmp) return true } case BlockARM64LT: // match: (LT (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LT (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LT, v0) return true } break } // match: (LT (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LT (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LT, v0) return true } // match: (LT (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LT (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LT, v0) return true } break } // match: (LT (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LT (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LT, v0) return true } // match: (LT (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LTnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LTnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LTnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LTnoov, v0) return true } break } // match: (LT (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LTnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LTnoov, v0) return true } break } // match: (LT (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] x) yes no) // result: (TBNZ [31] x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(31) return true } // match: (LT (CMPconst [0] x) yes no) // result: (TBNZ [63] x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(63) return true } // match: (LT (FlagConstant [fc]) yes no) // cond: fc.lt() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.lt()) { break } b.Reset(BlockFirst) return true } // match: (LT (FlagConstant [fc]) yes no) // cond: !fc.lt() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.lt()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GT, cmp) return true } case BlockARM64LTnoov: // match: (LTnoov (FlagConstant [fc]) yes no) // cond: fc.ltNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ltNoov()) { break } b.Reset(BlockFirst) return true } // match: (LTnoov (FlagConstant [fc]) yes no) // cond: !fc.ltNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ltNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LTnoov (InvertFlags cmp) yes no) // result: (GTnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GTnoov, cmp) return true } case BlockARM64NE: // match: (NE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (NE (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (NE (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (NE (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (NE (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMP x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (NE (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMP { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPW x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (NE (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPW { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] x) yes no) // result: (NZ x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64NZ, x) return true } // match: (NE (CMPWconst [0] x) yes no) // result: (NZW x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64NZW, x) return true } // match: (NE (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (TSTconst [c] x) yes no) // cond: oneBit(c) // result: (TBNZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64TSTconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (NE (TSTWconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBNZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64TSTWconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (NE (FlagConstant [fc]) yes no) // cond: fc.ne() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ne()) { break } b.Reset(BlockFirst) return true } // match: (NE (FlagConstant [fc]) yes no) // cond: !fc.ne() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ne()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64NE, cmp) return true } case BlockARM64NZ: // match: (NZ (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpARM64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64EQ, cc) return true } // match: (NZ (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpARM64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64NE, cc) return true } // match: (NZ (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpARM64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LT, cc) return true } // match: (NZ (LessThanU cc) yes no) // result: (ULT cc yes no) for b.Controls[0].Op == OpARM64LessThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULT, cc) return true } // match: (NZ (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpARM64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LE, cc) return true } // match: (NZ (LessEqualU cc) yes no) // result: (ULE cc yes no) for b.Controls[0].Op == OpARM64LessEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULE, cc) return true } // match: (NZ (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpARM64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GT, cc) return true } // match: (NZ (GreaterThanU cc) yes no) // result: (UGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGT, cc) return true } // match: (NZ (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GE, cc) return true } // match: (NZ (GreaterEqualU cc) yes no) // result: (UGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGE, cc) return true } // match: (NZ (LessThanF cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpARM64LessThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLT, cc) return true } // match: (NZ (LessEqualF cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpARM64LessEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLE, cc) return true } // match: (NZ (GreaterThanF cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGT, cc) return true } // match: (NZ (GreaterEqualF cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGE, cc) return true } // match: (NZ (ANDconst [c] x) yes no) // cond: oneBit(c) // result: (TBNZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (NZ (MOVDconst [0]) yes no) // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NZ (MOVDconst [c]) yes no) // cond: c != 0 // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(c != 0) { break } b.Reset(BlockFirst) return true } case BlockARM64NZW: // match: (NZW (ANDconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBNZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (NZW (MOVDconst [c]) yes no) // cond: int32(c) == 0 // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) == 0) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NZW (MOVDconst [c]) yes no) // cond: int32(c) != 0 // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) != 0) { break } b.Reset(BlockFirst) return true } case BlockARM64TBNZ: // match: (TBNZ [0] (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpARM64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64EQ, cc) return true } // match: (TBNZ [0] (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpARM64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64NE, cc) return true } // match: (TBNZ [0] (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpARM64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64LT, cc) return true } // match: (TBNZ [0] (LessThanU cc) yes no) // result: (ULT cc yes no) for b.Controls[0].Op == OpARM64LessThanU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64ULT, cc) return true } // match: (TBNZ [0] (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpARM64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64LE, cc) return true } // match: (TBNZ [0] (LessEqualU cc) yes no) // result: (ULE cc yes no) for b.Controls[0].Op == OpARM64LessEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64ULE, cc) return true } // match: (TBNZ [0] (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpARM64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64GT, cc) return true } // match: (TBNZ [0] (GreaterThanU cc) yes no) // result: (UGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64UGT, cc) return true } // match: (TBNZ [0] (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64GE, cc) return true } // match: (TBNZ [0] (GreaterEqualU cc) yes no) // result: (UGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64UGE, cc) return true } // match: (TBNZ [0] (LessThanF cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpARM64LessThanF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FLT, cc) return true } // match: (TBNZ [0] (LessEqualF cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpARM64LessEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FLE, cc) return true } // match: (TBNZ [0] (GreaterThanF cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FGT, cc) return true } // match: (TBNZ [0] (GreaterEqualF cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FGE, cc) return true } case BlockARM64UGE: // match: (UGE (FlagConstant [fc]) yes no) // cond: fc.uge() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.uge()) { break } b.Reset(BlockFirst) return true } // match: (UGE (FlagConstant [fc]) yes no) // cond: !fc.uge() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.uge()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64ULE, cmp) return true } case BlockARM64UGT: // match: (UGT (FlagConstant [fc]) yes no) // cond: fc.ugt() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ugt()) { break } b.Reset(BlockFirst) return true } // match: (UGT (FlagConstant [fc]) yes no) // cond: !fc.ugt() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ugt()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64ULT, cmp) return true } case BlockARM64ULE: // match: (ULE (FlagConstant [fc]) yes no) // cond: fc.ule() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ule()) { break } b.Reset(BlockFirst) return true } // match: (ULE (FlagConstant [fc]) yes no) // cond: !fc.ule() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ule()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64UGE, cmp) return true } case BlockARM64ULT: // match: (ULT (FlagConstant [fc]) yes no) // cond: fc.ult() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ult()) { break } b.Reset(BlockFirst) return true } // match: (ULT (FlagConstant [fc]) yes no) // cond: !fc.ult() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ult()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64UGT, cmp) return true } case BlockARM64Z: // match: (Z (ANDconst [c] x) yes no) // cond: oneBit(c) // result: (TBZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (Z (MOVDconst [0]) yes no) // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } b.Reset(BlockFirst) return true } // match: (Z (MOVDconst [c]) yes no) // cond: c != 0 // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(c != 0) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockARM64ZW: // match: (ZW (ANDconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (ZW (MOVDconst [c]) yes no) // cond: int32(c) == 0 // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) == 0) { break } b.Reset(BlockFirst) return true } // match: (ZW (MOVDconst [c]) yes no) // cond: int32(c) != 0 // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) != 0) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- y -- // Code generated from _gen/ARM64.rules using 'go generate'; DO NOT EDIT. package ssa import "cmd/compile/internal/types" func rewriteValueARM64(v *Value) bool { switch v.Op { case OpARM64ADCSflags: return rewriteValueARM64_OpARM64ADCSflags(v) case OpARM64ADD: return rewriteValueARM64_OpARM64ADD(v) case OpARM64ADDSflags: return rewriteValueARM64_OpARM64ADDSflags(v) case OpARM64ADDconst: return rewriteValueARM64_OpARM64ADDconst(v) case OpARM64ADDshiftLL: return rewriteValueARM64_OpARM64ADDshiftLL(v) case OpARM64ADDshiftRA: return rewriteValueARM64_OpARM64ADDshiftRA(v) case OpARM64ADDshiftRL: return rewriteValueARM64_OpARM64ADDshiftRL(v) case OpARM64AND: return rewriteValueARM64_OpARM64AND(v) case OpARM64ANDconst: return rewriteValueARM64_OpARM64ANDconst(v) case OpARM64ANDshiftLL: return rewriteValueARM64_OpARM64ANDshiftLL(v) case OpARM64ANDshiftRA: return rewriteValueARM64_OpARM64ANDshiftRA(v) case OpARM64ANDshiftRL: return rewriteValueARM64_OpARM64ANDshiftRL(v) case OpARM64ANDshiftRO: return rewriteValueARM64_OpARM64ANDshiftRO(v) case OpARM64BIC: return rewriteValueARM64_OpARM64BIC(v) case OpARM64BICshiftLL: return rewriteValueARM64_OpARM64BICshiftLL(v) case OpARM64BICshiftRA: return rewriteValueARM64_OpARM64BICshiftRA(v) case OpARM64BICshiftRL: return rewriteValueARM64_OpARM64BICshiftRL(v) case OpARM64BICshiftRO: return rewriteValueARM64_OpARM64BICshiftRO(v) case OpARM64CMN: return rewriteValueARM64_OpARM64CMN(v) case OpARM64CMNW: return rewriteValueARM64_OpARM64CMNW(v) case OpARM64CMNWconst: return rewriteValueARM64_OpARM64CMNWconst(v) case OpARM64CMNconst: return rewriteValueARM64_OpARM64CMNconst(v) case OpARM64CMNshiftLL: return rewriteValueARM64_OpARM64CMNshiftLL(v) case OpARM64CMNshiftRA: return rewriteValueARM64_OpARM64CMNshiftRA(v) case OpARM64CMNshiftRL: return rewriteValueARM64_OpARM64CMNshiftRL(v) case OpARM64CMP: return rewriteValueARM64_OpARM64CMP(v) case OpARM64CMPW: return rewriteValueARM64_OpARM64CMPW(v) case OpARM64CMPWconst: return rewriteValueARM64_OpARM64CMPWconst(v) case OpARM64CMPconst: return rewriteValueARM64_OpARM64CMPconst(v) case OpARM64CMPshiftLL: return rewriteValueARM64_OpARM64CMPshiftLL(v) case OpARM64CMPshiftRA: return rewriteValueARM64_OpARM64CMPshiftRA(v) case OpARM64CMPshiftRL: return rewriteValueARM64_OpARM64CMPshiftRL(v) case OpARM64CSEL: return rewriteValueARM64_OpARM64CSEL(v) case OpARM64CSEL0: return rewriteValueARM64_OpARM64CSEL0(v) case OpARM64CSETM: return rewriteValueARM64_OpARM64CSETM(v) case OpARM64CSINC: return rewriteValueARM64_OpARM64CSINC(v) case OpARM64CSINV: return rewriteValueARM64_OpARM64CSINV(v) case OpARM64CSNEG: return rewriteValueARM64_OpARM64CSNEG(v) case OpARM64DIV: return rewriteValueARM64_OpARM64DIV(v) case OpARM64DIVW: return rewriteValueARM64_OpARM64DIVW(v) case OpARM64EON: return rewriteValueARM64_OpARM64EON(v) case OpARM64EONshiftLL: return rewriteValueARM64_OpARM64EONshiftLL(v) case OpARM64EONshiftRA: return rewriteValueARM64_OpARM64EONshiftRA(v) case OpARM64EONshiftRL: return rewriteValueARM64_OpARM64EONshiftRL(v) case OpARM64EONshiftRO: return rewriteValueARM64_OpARM64EONshiftRO(v) case OpARM64Equal: return rewriteValueARM64_OpARM64Equal(v) case OpARM64FADDD: return rewriteValueARM64_OpARM64FADDD(v) case OpARM64FADDS: return rewriteValueARM64_OpARM64FADDS(v) case OpARM64FCMPD: return rewriteValueARM64_OpARM64FCMPD(v) case OpARM64FCMPS: return rewriteValueARM64_OpARM64FCMPS(v) case OpARM64FMOVDfpgp: return rewriteValueARM64_OpARM64FMOVDfpgp(v) case OpARM64FMOVDgpfp: return rewriteValueARM64_OpARM64FMOVDgpfp(v) case OpARM64FMOVDload: return rewriteValueARM64_OpARM64FMOVDload(v) case OpARM64FMOVDloadidx: return rewriteValueARM64_OpARM64FMOVDloadidx(v) case OpARM64FMOVDloadidx8: return rewriteValueARM64_OpARM64FMOVDloadidx8(v) case OpARM64FMOVDstore: return rewriteValueARM64_OpARM64FMOVDstore(v) case OpARM64FMOVDstoreidx: return rewriteValueARM64_OpARM64FMOVDstoreidx(v) case OpARM64FMOVDstoreidx8: return rewriteValueARM64_OpARM64FMOVDstoreidx8(v) case OpARM64FMOVSload: return rewriteValueARM64_OpARM64FMOVSload(v) case OpARM64FMOVSloadidx: return rewriteValueARM64_OpARM64FMOVSloadidx(v) case OpARM64FMOVSloadidx4: return rewriteValueARM64_OpARM64FMOVSloadidx4(v) case OpARM64FMOVSstore: return rewriteValueARM64_OpARM64FMOVSstore(v) case OpARM64FMOVSstoreidx: return rewriteValueARM64_OpARM64FMOVSstoreidx(v) case OpARM64FMOVSstoreidx4: return rewriteValueARM64_OpARM64FMOVSstoreidx4(v) case OpARM64FMULD: return rewriteValueARM64_OpARM64FMULD(v) case OpARM64FMULS: return rewriteValueARM64_OpARM64FMULS(v) case OpARM64FNEGD: return rewriteValueARM64_OpARM64FNEGD(v) case OpARM64FNEGS: return rewriteValueARM64_OpARM64FNEGS(v) case OpARM64FNMULD: return rewriteValueARM64_OpARM64FNMULD(v) case OpARM64FNMULS: return rewriteValueARM64_OpARM64FNMULS(v) case OpARM64FSUBD: return rewriteValueARM64_OpARM64FSUBD(v) case OpARM64FSUBS: return rewriteValueARM64_OpARM64FSUBS(v) case OpARM64GreaterEqual: return rewriteValueARM64_OpARM64GreaterEqual(v) case OpARM64GreaterEqualF: return rewriteValueARM64_OpARM64GreaterEqualF(v) case OpARM64GreaterEqualU: return rewriteValueARM64_OpARM64GreaterEqualU(v) case OpARM64GreaterThan: return rewriteValueARM64_OpARM64GreaterThan(v) case OpARM64GreaterThanF: return rewriteValueARM64_OpARM64GreaterThanF(v) case OpARM64GreaterThanU: return rewriteValueARM64_OpARM64GreaterThanU(v) case OpARM64LDP: return rewriteValueARM64_OpARM64LDP(v) case OpARM64LessEqual: return rewriteValueARM64_OpARM64LessEqual(v) case OpARM64LessEqualF: return rewriteValueARM64_OpARM64LessEqualF(v) case OpARM64LessEqualU: return rewriteValueARM64_OpARM64LessEqualU(v) case OpARM64LessThan: return rewriteValueARM64_OpARM64LessThan(v) case OpARM64LessThanF: return rewriteValueARM64_OpARM64LessThanF(v) case OpARM64LessThanU: return rewriteValueARM64_OpARM64LessThanU(v) case OpARM64MADD: return rewriteValueARM64_OpARM64MADD(v) case OpARM64MADDW: return rewriteValueARM64_OpARM64MADDW(v) case OpARM64MNEG: return rewriteValueARM64_OpARM64MNEG(v) case OpARM64MNEGW: return rewriteValueARM64_OpARM64MNEGW(v) case OpARM64MOD: return rewriteValueARM64_OpARM64MOD(v) case OpARM64MODW: return rewriteValueARM64_OpARM64MODW(v) case OpARM64MOVBUload: return rewriteValueARM64_OpARM64MOVBUload(v) case OpARM64MOVBUloadidx: return rewriteValueARM64_OpARM64MOVBUloadidx(v) case OpARM64MOVBUreg: return rewriteValueARM64_OpARM64MOVBUreg(v) case OpARM64MOVBload: return rewriteValueARM64_OpARM64MOVBload(v) case OpARM64MOVBloadidx: return rewriteValueARM64_OpARM64MOVBloadidx(v) case OpARM64MOVBreg: return rewriteValueARM64_OpARM64MOVBreg(v) case OpARM64MOVBstore: return rewriteValueARM64_OpARM64MOVBstore(v) case OpARM64MOVBstoreidx: return rewriteValueARM64_OpARM64MOVBstoreidx(v) case OpARM64MOVBstorezero: return rewriteValueARM64_OpARM64MOVBstorezero(v) case OpARM64MOVBstorezeroidx: return rewriteValueARM64_OpARM64MOVBstorezeroidx(v) case OpARM64MOVDload: return rewriteValueARM64_OpARM64MOVDload(v) case OpARM64MOVDloadidx: return rewriteValueARM64_OpARM64MOVDloadidx(v) case OpARM64MOVDloadidx8: return rewriteValueARM64_OpARM64MOVDloadidx8(v) case OpARM64MOVDnop: return rewriteValueARM64_OpARM64MOVDnop(v) case OpARM64MOVDreg: return rewriteValueARM64_OpARM64MOVDreg(v) case OpARM64MOVDstore: return rewriteValueARM64_OpARM64MOVDstore(v) case OpARM64MOVDstoreidx: return rewriteValueARM64_OpARM64MOVDstoreidx(v) case OpARM64MOVDstoreidx8: return rewriteValueARM64_OpARM64MOVDstoreidx8(v) case OpARM64MOVDstorezero: return rewriteValueARM64_OpARM64MOVDstorezero(v) case OpARM64MOVDstorezeroidx: return rewriteValueARM64_OpARM64MOVDstorezeroidx(v) case OpARM64MOVDstorezeroidx8: return rewriteValueARM64_OpARM64MOVDstorezeroidx8(v) case OpARM64MOVHUload: return rewriteValueARM64_OpARM64MOVHUload(v) case OpARM64MOVHUloadidx: return rewriteValueARM64_OpARM64MOVHUloadidx(v) case OpARM64MOVHUloadidx2: return rewriteValueARM64_OpARM64MOVHUloadidx2(v) case OpARM64MOVHUreg: return rewriteValueARM64_OpARM64MOVHUreg(v) case OpARM64MOVHload: return rewriteValueARM64_OpARM64MOVHload(v) case OpARM64MOVHloadidx: return rewriteValueARM64_OpARM64MOVHloadidx(v) case OpARM64MOVHloadidx2: return rewriteValueARM64_OpARM64MOVHloadidx2(v) case OpARM64MOVHreg: return rewriteValueARM64_OpARM64MOVHreg(v) case OpARM64MOVHstore: return rewriteValueARM64_OpARM64MOVHstore(v) case OpARM64MOVHstoreidx: return rewriteValueARM64_OpARM64MOVHstoreidx(v) case OpARM64MOVHstoreidx2: return rewriteValueARM64_OpARM64MOVHstoreidx2(v) case OpARM64MOVHstorezero: return rewriteValueARM64_OpARM64MOVHstorezero(v) case OpARM64MOVHstorezeroidx: return rewriteValueARM64_OpARM64MOVHstorezeroidx(v) case OpARM64MOVHstorezeroidx2: return rewriteValueARM64_OpARM64MOVHstorezeroidx2(v) case OpARM64MOVQstorezero: return rewriteValueARM64_OpARM64MOVQstorezero(v) case OpARM64MOVWUload: return rewriteValueARM64_OpARM64MOVWUload(v) case OpARM64MOVWUloadidx: return rewriteValueARM64_OpARM64MOVWUloadidx(v) case OpARM64MOVWUloadidx4: return rewriteValueARM64_OpARM64MOVWUloadidx4(v) case OpARM64MOVWUreg: return rewriteValueARM64_OpARM64MOVWUreg(v) case OpARM64MOVWload: return rewriteValueARM64_OpARM64MOVWload(v) case OpARM64MOVWloadidx: return rewriteValueARM64_OpARM64MOVWloadidx(v) case OpARM64MOVWloadidx4: return rewriteValueARM64_OpARM64MOVWloadidx4(v) case OpARM64MOVWreg: return rewriteValueARM64_OpARM64MOVWreg(v) case OpARM64MOVWstore: return rewriteValueARM64_OpARM64MOVWstore(v) case OpARM64MOVWstoreidx: return rewriteValueARM64_OpARM64MOVWstoreidx(v) case OpARM64MOVWstoreidx4: return rewriteValueARM64_OpARM64MOVWstoreidx4(v) case OpARM64MOVWstorezero: return rewriteValueARM64_OpARM64MOVWstorezero(v) case OpARM64MOVWstorezeroidx: return rewriteValueARM64_OpARM64MOVWstorezeroidx(v) case OpARM64MOVWstorezeroidx4: return rewriteValueARM64_OpARM64MOVWstorezeroidx4(v) case OpARM64MSUB: return rewriteValueARM64_OpARM64MSUB(v) case OpARM64MSUBW: return rewriteValueARM64_OpARM64MSUBW(v) case OpARM64MUL: return rewriteValueARM64_OpARM64MUL(v) case OpARM64MULW: return rewriteValueARM64_OpARM64MULW(v) case OpARM64MVN: return rewriteValueARM64_OpARM64MVN(v) case OpARM64MVNshiftLL: return rewriteValueARM64_OpARM64MVNshiftLL(v) case OpARM64MVNshiftRA: return rewriteValueARM64_OpARM64MVNshiftRA(v) case OpARM64MVNshiftRL: return rewriteValueARM64_OpARM64MVNshiftRL(v) case OpARM64MVNshiftRO: return rewriteValueARM64_OpARM64MVNshiftRO(v) case OpARM64NEG: return rewriteValueARM64_OpARM64NEG(v) case OpARM64NEGshiftLL: return rewriteValueARM64_OpARM64NEGshiftLL(v) case OpARM64NEGshiftRA: return rewriteValueARM64_OpARM64NEGshiftRA(v) case OpARM64NEGshiftRL: return rewriteValueARM64_OpARM64NEGshiftRL(v) case OpARM64NotEqual: return rewriteValueARM64_OpARM64NotEqual(v) case OpARM64OR: return rewriteValueARM64_OpARM64OR(v) case OpARM64ORN: return rewriteValueARM64_OpARM64ORN(v) case OpARM64ORNshiftLL: return rewriteValueARM64_OpARM64ORNshiftLL(v) case OpARM64ORNshiftRA: return rewriteValueARM64_OpARM64ORNshiftRA(v) case OpARM64ORNshiftRL: return rewriteValueARM64_OpARM64ORNshiftRL(v) case OpARM64ORNshiftRO: return rewriteValueARM64_OpARM64ORNshiftRO(v) case OpARM64ORconst: return rewriteValueARM64_OpARM64ORconst(v) case OpARM64ORshiftLL: return rewriteValueARM64_OpARM64ORshiftLL(v) case OpARM64ORshiftRA: return rewriteValueARM64_OpARM64ORshiftRA(v) case OpARM64ORshiftRL: return rewriteValueARM64_OpARM64ORshiftRL(v) case OpARM64ORshiftRO: return rewriteValueARM64_OpARM64ORshiftRO(v) case OpARM64REV: return rewriteValueARM64_OpARM64REV(v) case OpARM64REVW: return rewriteValueARM64_OpARM64REVW(v) case OpARM64ROR: return rewriteValueARM64_OpARM64ROR(v) case OpARM64RORW: return rewriteValueARM64_OpARM64RORW(v) case OpARM64SBCSflags: return rewriteValueARM64_OpARM64SBCSflags(v) case OpARM64SLL: return rewriteValueARM64_OpARM64SLL(v) case OpARM64SLLconst: return rewriteValueARM64_OpARM64SLLconst(v) case OpARM64SRA: return rewriteValueARM64_OpARM64SRA(v) case OpARM64SRAconst: return rewriteValueARM64_OpARM64SRAconst(v) case OpARM64SRL: return rewriteValueARM64_OpARM64SRL(v) case OpARM64SRLconst: return rewriteValueARM64_OpARM64SRLconst(v) case OpARM64STP: return rewriteValueARM64_OpARM64STP(v) case OpARM64SUB: return rewriteValueARM64_OpARM64SUB(v) case OpARM64SUBconst: return rewriteValueARM64_OpARM64SUBconst(v) case OpARM64SUBshiftLL: return rewriteValueARM64_OpARM64SUBshiftLL(v) case OpARM64SUBshiftRA: return rewriteValueARM64_OpARM64SUBshiftRA(v) case OpARM64SUBshiftRL: return rewriteValueARM64_OpARM64SUBshiftRL(v) case OpARM64TST: return rewriteValueARM64_OpARM64TST(v) case OpARM64TSTW: return rewriteValueARM64_OpARM64TSTW(v) case OpARM64TSTWconst: return rewriteValueARM64_OpARM64TSTWconst(v) case OpARM64TSTconst: return rewriteValueARM64_OpARM64TSTconst(v) case OpARM64TSTshiftLL: return rewriteValueARM64_OpARM64TSTshiftLL(v) case OpARM64TSTshiftRA: return rewriteValueARM64_OpARM64TSTshiftRA(v) case OpARM64TSTshiftRL: return rewriteValueARM64_OpARM64TSTshiftRL(v) case OpARM64TSTshiftRO: return rewriteValueARM64_OpARM64TSTshiftRO(v) case OpARM64UBFIZ: return rewriteValueARM64_OpARM64UBFIZ(v) case OpARM64UBFX: return rewriteValueARM64_OpARM64UBFX(v) case OpARM64UDIV: return rewriteValueARM64_OpARM64UDIV(v) case OpARM64UDIVW: return rewriteValueARM64_OpARM64UDIVW(v) case OpARM64UMOD: return rewriteValueARM64_OpARM64UMOD(v) case OpARM64UMODW: return rewriteValueARM64_OpARM64UMODW(v) case OpARM64XOR: return rewriteValueARM64_OpARM64XOR(v) case OpARM64XORconst: return rewriteValueARM64_OpARM64XORconst(v) case OpARM64XORshiftLL: return rewriteValueARM64_OpARM64XORshiftLL(v) case OpARM64XORshiftRA: return rewriteValueARM64_OpARM64XORshiftRA(v) case OpARM64XORshiftRL: return rewriteValueARM64_OpARM64XORshiftRL(v) case OpARM64XORshiftRO: return rewriteValueARM64_OpARM64XORshiftRO(v) case OpAbs: v.Op = OpARM64FABSD return true case OpAdd16: v.Op = OpARM64ADD return true case OpAdd32: v.Op = OpARM64ADD return true case OpAdd32F: v.Op = OpARM64FADDS return true case OpAdd64: v.Op = OpARM64ADD return true case OpAdd64F: v.Op = OpARM64FADDD return true case OpAdd8: v.Op = OpARM64ADD return true case OpAddPtr: v.Op = OpARM64ADD return true case OpAddr: return rewriteValueARM64_OpAddr(v) case OpAnd16: v.Op = OpARM64AND return true case OpAnd32: v.Op = OpARM64AND return true case OpAnd64: v.Op = OpARM64AND return true case OpAnd8: v.Op = OpARM64AND return true case OpAndB: v.Op = OpARM64AND return true case OpAtomicAdd32: v.Op = OpARM64LoweredAtomicAdd32 return true case OpAtomicAdd32Variant: v.Op = OpARM64LoweredAtomicAdd32Variant return true case OpAtomicAdd64: v.Op = OpARM64LoweredAtomicAdd64 return true case OpAtomicAdd64Variant: v.Op = OpARM64LoweredAtomicAdd64Variant return true case OpAtomicAnd32: return rewriteValueARM64_OpAtomicAnd32(v) case OpAtomicAnd32Variant: return rewriteValueARM64_OpAtomicAnd32Variant(v) case OpAtomicAnd8: return rewriteValueARM64_OpAtomicAnd8(v) case OpAtomicAnd8Variant: return rewriteValueARM64_OpAtomicAnd8Variant(v) case OpAtomicCompareAndSwap32: v.Op = OpARM64LoweredAtomicCas32 return true case OpAtomicCompareAndSwap32Variant: v.Op = OpARM64LoweredAtomicCas32Variant return true case OpAtomicCompareAndSwap64: v.Op = OpARM64LoweredAtomicCas64 return true case OpAtomicCompareAndSwap64Variant: v.Op = OpARM64LoweredAtomicCas64Variant return true case OpAtomicExchange32: v.Op = OpARM64LoweredAtomicExchange32 return true case OpAtomicExchange32Variant: v.Op = OpARM64LoweredAtomicExchange32Variant return true case OpAtomicExchange64: v.Op = OpARM64LoweredAtomicExchange64 return true case OpAtomicExchange64Variant: v.Op = OpARM64LoweredAtomicExchange64Variant return true case OpAtomicLoad32: v.Op = OpARM64LDARW return true case OpAtomicLoad64: v.Op = OpARM64LDAR return true case OpAtomicLoad8: v.Op = OpARM64LDARB return true case OpAtomicLoadPtr: v.Op = OpARM64LDAR return true case OpAtomicOr32: return rewriteValueARM64_OpAtomicOr32(v) case OpAtomicOr32Variant: return rewriteValueARM64_OpAtomicOr32Variant(v) case OpAtomicOr8: return rewriteValueARM64_OpAtomicOr8(v) case OpAtomicOr8Variant: return rewriteValueARM64_OpAtomicOr8Variant(v) case OpAtomicStore32: v.Op = OpARM64STLRW return true case OpAtomicStore64: v.Op = OpARM64STLR return true case OpAtomicStore8: v.Op = OpARM64STLRB return true case OpAtomicStorePtrNoWB: v.Op = OpARM64STLR return true case OpAvg64u: return rewriteValueARM64_OpAvg64u(v) case OpBitLen32: return rewriteValueARM64_OpBitLen32(v) case OpBitLen64: return rewriteValueARM64_OpBitLen64(v) case OpBitRev16: return rewriteValueARM64_OpBitRev16(v) case OpBitRev32: v.Op = OpARM64RBITW return true case OpBitRev64: v.Op = OpARM64RBIT return true case OpBitRev8: return rewriteValueARM64_OpBitRev8(v) case OpBswap16: v.Op = OpARM64REV16W return true case OpBswap32: v.Op = OpARM64REVW return true case OpBswap64: v.Op = OpARM64REV return true case OpCeil: v.Op = OpARM64FRINTPD return true case OpClosureCall: v.Op = OpARM64CALLclosure return true case OpCom16: v.Op = OpARM64MVN return true case OpCom32: v.Op = OpARM64MVN return true case OpCom64: v.Op = OpARM64MVN return true case OpCom8: v.Op = OpARM64MVN return true case OpCondSelect: return rewriteValueARM64_OpCondSelect(v) case OpConst16: return rewriteValueARM64_OpConst16(v) case OpConst32: return rewriteValueARM64_OpConst32(v) case OpConst32F: return rewriteValueARM64_OpConst32F(v) case OpConst64: return rewriteValueARM64_OpConst64(v) case OpConst64F: return rewriteValueARM64_OpConst64F(v) case OpConst8: return rewriteValueARM64_OpConst8(v) case OpConstBool: return rewriteValueARM64_OpConstBool(v) case OpConstNil: return rewriteValueARM64_OpConstNil(v) case OpCtz16: return rewriteValueARM64_OpCtz16(v) case OpCtz16NonZero: v.Op = OpCtz32 return true case OpCtz32: return rewriteValueARM64_OpCtz32(v) case OpCtz32NonZero: v.Op = OpCtz32 return true case OpCtz64: return rewriteValueARM64_OpCtz64(v) case OpCtz64NonZero: v.Op = OpCtz64 return true case OpCtz8: return rewriteValueARM64_OpCtz8(v) case OpCtz8NonZero: v.Op = OpCtz32 return true case OpCvt32Fto32: v.Op = OpARM64FCVTZSSW return true case OpCvt32Fto32U: v.Op = OpARM64FCVTZUSW return true case OpCvt32Fto64: v.Op = OpARM64FCVTZSS return true case OpCvt32Fto64F: v.Op = OpARM64FCVTSD return true case OpCvt32Fto64U: v.Op = OpARM64FCVTZUS return true case OpCvt32Uto32F: v.Op = OpARM64UCVTFWS return true case OpCvt32Uto64F: v.Op = OpARM64UCVTFWD return true case OpCvt32to32F: v.Op = OpARM64SCVTFWS return true case OpCvt32to64F: v.Op = OpARM64SCVTFWD return true case OpCvt64Fto32: v.Op = OpARM64FCVTZSDW return true case OpCvt64Fto32F: v.Op = OpARM64FCVTDS return true case OpCvt64Fto32U: v.Op = OpARM64FCVTZUDW return true case OpCvt64Fto64: v.Op = OpARM64FCVTZSD return true case OpCvt64Fto64U: v.Op = OpARM64FCVTZUD return true case OpCvt64Uto32F: v.Op = OpARM64UCVTFS return true case OpCvt64Uto64F: v.Op = OpARM64UCVTFD return true case OpCvt64to32F: v.Op = OpARM64SCVTFS return true case OpCvt64to64F: v.Op = OpARM64SCVTFD return true case OpCvtBoolToUint8: v.Op = OpCopy return true case OpDiv16: return rewriteValueARM64_OpDiv16(v) case OpDiv16u: return rewriteValueARM64_OpDiv16u(v) case OpDiv32: return rewriteValueARM64_OpDiv32(v) case OpDiv32F: v.Op = OpARM64FDIVS return true case OpDiv32u: v.Op = OpARM64UDIVW return true case OpDiv64: return rewriteValueARM64_OpDiv64(v) case OpDiv64F: v.Op = OpARM64FDIVD return true case OpDiv64u: v.Op = OpARM64UDIV return true case OpDiv8: return rewriteValueARM64_OpDiv8(v) case OpDiv8u: return rewriteValueARM64_OpDiv8u(v) case OpEq16: return rewriteValueARM64_OpEq16(v) case OpEq32: return rewriteValueARM64_OpEq32(v) case OpEq32F: return rewriteValueARM64_OpEq32F(v) case OpEq64: return rewriteValueARM64_OpEq64(v) case OpEq64F: return rewriteValueARM64_OpEq64F(v) case OpEq8: return rewriteValueARM64_OpEq8(v) case OpEqB: return rewriteValueARM64_OpEqB(v) case OpEqPtr: return rewriteValueARM64_OpEqPtr(v) case OpFMA: return rewriteValueARM64_OpFMA(v) case OpFloor: v.Op = OpARM64FRINTMD return true case OpGetCallerPC: v.Op = OpARM64LoweredGetCallerPC return true case OpGetCallerSP: v.Op = OpARM64LoweredGetCallerSP return true case OpGetClosurePtr: v.Op = OpARM64LoweredGetClosurePtr return true case OpHmul32: return rewriteValueARM64_OpHmul32(v) case OpHmul32u: return rewriteValueARM64_OpHmul32u(v) case OpHmul64: v.Op = OpARM64MULH return true case OpHmul64u: v.Op = OpARM64UMULH return true case OpInterCall: v.Op = OpARM64CALLinter return true case OpIsInBounds: return rewriteValueARM64_OpIsInBounds(v) case OpIsNonNil: return rewriteValueARM64_OpIsNonNil(v) case OpIsSliceInBounds: return rewriteValueARM64_OpIsSliceInBounds(v) case OpLeq16: return rewriteValueARM64_OpLeq16(v) case OpLeq16U: return rewriteValueARM64_OpLeq16U(v) case OpLeq32: return rewriteValueARM64_OpLeq32(v) case OpLeq32F: return rewriteValueARM64_OpLeq32F(v) case OpLeq32U: return rewriteValueARM64_OpLeq32U(v) case OpLeq64: return rewriteValueARM64_OpLeq64(v) case OpLeq64F: return rewriteValueARM64_OpLeq64F(v) case OpLeq64U: return rewriteValueARM64_OpLeq64U(v) case OpLeq8: return rewriteValueARM64_OpLeq8(v) case OpLeq8U: return rewriteValueARM64_OpLeq8U(v) case OpLess16: return rewriteValueARM64_OpLess16(v) case OpLess16U: return rewriteValueARM64_OpLess16U(v) case OpLess32: return rewriteValueARM64_OpLess32(v) case OpLess32F: return rewriteValueARM64_OpLess32F(v) case OpLess32U: return rewriteValueARM64_OpLess32U(v) case OpLess64: return rewriteValueARM64_OpLess64(v) case OpLess64F: return rewriteValueARM64_OpLess64F(v) case OpLess64U: return rewriteValueARM64_OpLess64U(v) case OpLess8: return rewriteValueARM64_OpLess8(v) case OpLess8U: return rewriteValueARM64_OpLess8U(v) case OpLoad: return rewriteValueARM64_OpLoad(v) case OpLocalAddr: return rewriteValueARM64_OpLocalAddr(v) case OpLsh16x16: return rewriteValueARM64_OpLsh16x16(v) case OpLsh16x32: return rewriteValueARM64_OpLsh16x32(v) case OpLsh16x64: return rewriteValueARM64_OpLsh16x64(v) case OpLsh16x8: return rewriteValueARM64_OpLsh16x8(v) case OpLsh32x16: return rewriteValueARM64_OpLsh32x16(v) case OpLsh32x32: return rewriteValueARM64_OpLsh32x32(v) case OpLsh32x64: return rewriteValueARM64_OpLsh32x64(v) case OpLsh32x8: return rewriteValueARM64_OpLsh32x8(v) case OpLsh64x16: return rewriteValueARM64_OpLsh64x16(v) case OpLsh64x32: return rewriteValueARM64_OpLsh64x32(v) case OpLsh64x64: return rewriteValueARM64_OpLsh64x64(v) case OpLsh64x8: return rewriteValueARM64_OpLsh64x8(v) case OpLsh8x16: return rewriteValueARM64_OpLsh8x16(v) case OpLsh8x32: return rewriteValueARM64_OpLsh8x32(v) case OpLsh8x64: return rewriteValueARM64_OpLsh8x64(v) case OpLsh8x8: return rewriteValueARM64_OpLsh8x8(v) case OpMod16: return rewriteValueARM64_OpMod16(v) case OpMod16u: return rewriteValueARM64_OpMod16u(v) case OpMod32: return rewriteValueARM64_OpMod32(v) case OpMod32u: v.Op = OpARM64UMODW return true case OpMod64: return rewriteValueARM64_OpMod64(v) case OpMod64u: v.Op = OpARM64UMOD return true case OpMod8: return rewriteValueARM64_OpMod8(v) case OpMod8u: return rewriteValueARM64_OpMod8u(v) case OpMove: return rewriteValueARM64_OpMove(v) case OpMul16: v.Op = OpARM64MULW return true case OpMul32: v.Op = OpARM64MULW return true case OpMul32F: v.Op = OpARM64FMULS return true case OpMul64: v.Op = OpARM64MUL return true case OpMul64F: v.Op = OpARM64FMULD return true case OpMul8: v.Op = OpARM64MULW return true case OpNeg16: v.Op = OpARM64NEG return true case OpNeg32: v.Op = OpARM64NEG return true case OpNeg32F: v.Op = OpARM64FNEGS return true case OpNeg64: v.Op = OpARM64NEG return true case OpNeg64F: v.Op = OpARM64FNEGD return true case OpNeg8: v.Op = OpARM64NEG return true case OpNeq16: return rewriteValueARM64_OpNeq16(v) case OpNeq32: return rewriteValueARM64_OpNeq32(v) case OpNeq32F: return rewriteValueARM64_OpNeq32F(v) case OpNeq64: return rewriteValueARM64_OpNeq64(v) case OpNeq64F: return rewriteValueARM64_OpNeq64F(v) case OpNeq8: return rewriteValueARM64_OpNeq8(v) case OpNeqB: v.Op = OpARM64XOR return true case OpNeqPtr: return rewriteValueARM64_OpNeqPtr(v) case OpNilCheck: v.Op = OpARM64LoweredNilCheck return true case OpNot: return rewriteValueARM64_OpNot(v) case OpOffPtr: return rewriteValueARM64_OpOffPtr(v) case OpOr16: v.Op = OpARM64OR return true case OpOr32: v.Op = OpARM64OR return true case OpOr64: v.Op = OpARM64OR return true case OpOr8: v.Op = OpARM64OR return true case OpOrB: v.Op = OpARM64OR return true case OpPanicBounds: return rewriteValueARM64_OpPanicBounds(v) case OpPopCount16: return rewriteValueARM64_OpPopCount16(v) case OpPopCount32: return rewriteValueARM64_OpPopCount32(v) case OpPopCount64: return rewriteValueARM64_OpPopCount64(v) case OpPrefetchCache: return rewriteValueARM64_OpPrefetchCache(v) case OpPrefetchCacheStreamed: return rewriteValueARM64_OpPrefetchCacheStreamed(v) case OpPubBarrier: return rewriteValueARM64_OpPubBarrier(v) case OpRotateLeft16: return rewriteValueARM64_OpRotateLeft16(v) case OpRotateLeft32: return rewriteValueARM64_OpRotateLeft32(v) case OpRotateLeft64: return rewriteValueARM64_OpRotateLeft64(v) case OpRotateLeft8: return rewriteValueARM64_OpRotateLeft8(v) case OpRound: v.Op = OpARM64FRINTAD return true case OpRound32F: v.Op = OpARM64LoweredRound32F return true case OpRound64F: v.Op = OpARM64LoweredRound64F return true case OpRoundToEven: v.Op = OpARM64FRINTND return true case OpRsh16Ux16: return rewriteValueARM64_OpRsh16Ux16(v) case OpRsh16Ux32: return rewriteValueARM64_OpRsh16Ux32(v) case OpRsh16Ux64: return rewriteValueARM64_OpRsh16Ux64(v) case OpRsh16Ux8: return rewriteValueARM64_OpRsh16Ux8(v) case OpRsh16x16: return rewriteValueARM64_OpRsh16x16(v) case OpRsh16x32: return rewriteValueARM64_OpRsh16x32(v) case OpRsh16x64: return rewriteValueARM64_OpRsh16x64(v) case OpRsh16x8: return rewriteValueARM64_OpRsh16x8(v) case OpRsh32Ux16: return rewriteValueARM64_OpRsh32Ux16(v) case OpRsh32Ux32: return rewriteValueARM64_OpRsh32Ux32(v) case OpRsh32Ux64: return rewriteValueARM64_OpRsh32Ux64(v) case OpRsh32Ux8: return rewriteValueARM64_OpRsh32Ux8(v) case OpRsh32x16: return rewriteValueARM64_OpRsh32x16(v) case OpRsh32x32: return rewriteValueARM64_OpRsh32x32(v) case OpRsh32x64: return rewriteValueARM64_OpRsh32x64(v) case OpRsh32x8: return rewriteValueARM64_OpRsh32x8(v) case OpRsh64Ux16: return rewriteValueARM64_OpRsh64Ux16(v) case OpRsh64Ux32: return rewriteValueARM64_OpRsh64Ux32(v) case OpRsh64Ux64: return rewriteValueARM64_OpRsh64Ux64(v) case OpRsh64Ux8: return rewriteValueARM64_OpRsh64Ux8(v) case OpRsh64x16: return rewriteValueARM64_OpRsh64x16(v) case OpRsh64x32: return rewriteValueARM64_OpRsh64x32(v) case OpRsh64x64: return rewriteValueARM64_OpRsh64x64(v) case OpRsh64x8: return rewriteValueARM64_OpRsh64x8(v) case OpRsh8Ux16: return rewriteValueARM64_OpRsh8Ux16(v) case OpRsh8Ux32: return rewriteValueARM64_OpRsh8Ux32(v) case OpRsh8Ux64: return rewriteValueARM64_OpRsh8Ux64(v) case OpRsh8Ux8: return rewriteValueARM64_OpRsh8Ux8(v) case OpRsh8x16: return rewriteValueARM64_OpRsh8x16(v) case OpRsh8x32: return rewriteValueARM64_OpRsh8x32(v) case OpRsh8x64: return rewriteValueARM64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueARM64_OpRsh8x8(v) case OpSelect0: return rewriteValueARM64_OpSelect0(v) case OpSelect1: return rewriteValueARM64_OpSelect1(v) case OpSelectN: return rewriteValueARM64_OpSelectN(v) case OpSignExt16to32: v.Op = OpARM64MOVHreg return true case OpSignExt16to64: v.Op = OpARM64MOVHreg return true case OpSignExt32to64: v.Op = OpARM64MOVWreg return true case OpSignExt8to16: v.Op = OpARM64MOVBreg return true case OpSignExt8to32: v.Op = OpARM64MOVBreg return true case OpSignExt8to64: v.Op = OpARM64MOVBreg return true case OpSlicemask: return rewriteValueARM64_OpSlicemask(v) case OpSqrt: v.Op = OpARM64FSQRTD return true case OpSqrt32: v.Op = OpARM64FSQRTS return true case OpStaticCall: v.Op = OpARM64CALLstatic return true case OpStore: return rewriteValueARM64_OpStore(v) case OpSub16: v.Op = OpARM64SUB return true case OpSub32: v.Op = OpARM64SUB return true case OpSub32F: v.Op = OpARM64FSUBS return true case OpSub64: v.Op = OpARM64SUB return true case OpSub64F: v.Op = OpARM64FSUBD return true case OpSub8: v.Op = OpARM64SUB return true case OpSubPtr: v.Op = OpARM64SUB return true case OpTailCall: v.Op = OpARM64CALLtail return true case OpTrunc: v.Op = OpARM64FRINTZD return true case OpTrunc16to8: v.Op = OpCopy return true case OpTrunc32to16: v.Op = OpCopy return true case OpTrunc32to8: v.Op = OpCopy return true case OpTrunc64to16: v.Op = OpCopy return true case OpTrunc64to32: v.Op = OpCopy return true case OpTrunc64to8: v.Op = OpCopy return true case OpWB: v.Op = OpARM64LoweredWB return true case OpXor16: v.Op = OpARM64XOR return true case OpXor32: v.Op = OpARM64XOR return true case OpXor64: v.Op = OpARM64XOR return true case OpXor8: v.Op = OpARM64XOR return true case OpZero: return rewriteValueARM64_OpZero(v) case OpZeroExt16to32: v.Op = OpARM64MOVHUreg return true case OpZeroExt16to64: v.Op = OpARM64MOVHUreg return true case OpZeroExt32to64: v.Op = OpARM64MOVWUreg return true case OpZeroExt8to16: v.Op = OpARM64MOVBUreg return true case OpZeroExt8to32: v.Op = OpARM64MOVBUreg return true case OpZeroExt8to64: v.Op = OpARM64MOVBUreg return true } return false } func rewriteValueARM64_OpARM64ADCSflags(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADCSflags x y (Select1 (ADDSconstflags [-1] (ADCzerocarry c)))) // result: (ADCSflags x y c) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64ADDSconstflags || auxIntToInt64(v_2_0.AuxInt) != -1 { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64ADCzerocarry || v_2_0_0.Type != typ.UInt64 { break } c := v_2_0_0.Args[0] v.reset(OpARM64ADCSflags) v.AddArg3(x, y, c) return true } // match: (ADCSflags x y (Select1 (ADDSconstflags [-1] (MOVDconst [0])))) // result: (ADDSflags x y) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64ADDSconstflags || auxIntToInt64(v_2_0.AuxInt) != -1 { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64MOVDconst || auxIntToInt64(v_2_0_0.AuxInt) != 0 { break } v.reset(OpARM64ADDSflags) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64ADD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADD x (MOVDconst [c])) // cond: !t.IsPtr() // result: (ADDconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } t := v_1.Type c := auxIntToInt64(v_1.AuxInt) if !(!t.IsPtr()) { continue } v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (ADD a l:(MUL x y)) // cond: l.Uses==1 && clobber(l) // result: (MADD a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MUL { continue } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MADD) v.AddArg3(a, x, y) return true } break } // match: (ADD a l:(MNEG x y)) // cond: l.Uses==1 && clobber(l) // result: (MSUB a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MNEG { continue } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MSUB) v.AddArg3(a, x, y) return true } break } // match: (ADD a l:(MULW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MADDW a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MULW { continue } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MADDW) v.AddArg3(a, x, y) return true } break } // match: (ADD a l:(MNEGW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MSUBW a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 l := v_1 if l.Op != OpARM64MNEGW { continue } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { continue } v.reset(OpARM64MSUBW) v.AddArg3(a, x, y) return true } break } // match: (ADD x (NEG y)) // result: (SUB x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64NEG { continue } y := v_1.Args[0] v.reset(OpARM64SUB) v.AddArg2(x, y) return true } break } // match: (ADD x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ADDshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (ADD x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ADDshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ADDshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (ADD x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ADDshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ADDshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64ADDSflags(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADDSflags x (MOVDconst [c])) // result: (ADDSconstflags [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ADDSconstflags) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } return false } func rewriteValueARM64_OpARM64ADDconst(v *Value) bool { v_0 := v.Args[0] // match: (ADDconst [off1] (MOVDaddr [off2] {sym} ptr)) // cond: is32Bit(off1+int64(off2)) // result: (MOVDaddr [int32(off1)+off2] {sym} ptr) for { off1 := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) ptr := v_0.Args[0] if !(is32Bit(off1 + int64(off2))) { break } v.reset(OpARM64MOVDaddr) v.AuxInt = int32ToAuxInt(int32(off1) + off2) v.Aux = symToAux(sym) v.AddArg(ptr) return true } // match: (ADDconst [c] y) // cond: c < 0 // result: (SUBconst [-c] y) for { c := auxIntToInt64(v.AuxInt) y := v_0 if !(c < 0) { break } v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(-c) v.AddArg(y) return true } // match: (ADDconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ADDconst [c] (MOVDconst [d])) // result: (MOVDconst [c+d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c + d) return true } // match: (ADDconst [c] (ADDconst [d] x)) // result: (ADDconst [c+d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ADDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c + d) v.AddArg(x) return true } // match: (ADDconst [c] (SUBconst [d] x)) // result: (ADDconst [c-d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SUBconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c - d) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ADDshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ADDshiftLL (MOVDconst [c]) x [d]) // result: (ADDconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftLL x (MOVDconst [c]) [d]) // result: (ADDconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) // result: (REV16W x) for { if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ADDshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff // result: (REV16W x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ADDshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) // result: (REV16 x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { break } v.reset(OpARM64REV16) v.AddArg(x) return true } // match: (ADDshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) // result: (REV16 (ANDconst [0xffffffff] x)) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16) v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) v0.AuxInt = int64ToAuxInt(0xffffffff) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftLL [c] (SRLconst x [64-c]) x2) // result: (EXTRconst [64-c] x2 x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { break } x := v_0.Args[0] x2 := v_1 v.reset(OpARM64EXTRconst) v.AuxInt = int64ToAuxInt(64 - c) v.AddArg2(x2, x) return true } // match: (ADDshiftLL [c] (UBFX [bfc] x) x2) // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) // result: (EXTRWconst [32-c] x2 x) for { t := v.Type c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] x2 := v_1 if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { break } v.reset(OpARM64EXTRWconst) v.AuxInt = int64ToAuxInt(32 - c) v.AddArg2(x2, x) return true } return false } func rewriteValueARM64_OpARM64ADDshiftRA(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ADDshiftRA (MOVDconst [c]) x [d]) // result: (ADDconst [c] (SRAconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftRA x (MOVDconst [c]) [d]) // result: (ADDconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ADDshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ADDshiftRL (MOVDconst [c]) x [d]) // result: (ADDconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ADDshiftRL x (MOVDconst [c]) [d]) // result: (ADDconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64AND(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (AND x (MOVDconst [c])) // result: (ANDconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (AND x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (AND x (MVN y)) // result: (BIC x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MVN { continue } y := v_1.Args[0] v.reset(OpARM64BIC) v.AddArg2(x, y) return true } break } // match: (AND x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (AND x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (AND x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (AND x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (ANDshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ANDshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64ANDconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDconst [0] _) // result: (MOVDconst [0]) for { if auxIntToInt64(v.AuxInt) != 0 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (ANDconst [-1] x) // result: x for { if auxIntToInt64(v.AuxInt) != -1 { break } x := v_0 v.copyOf(x) return true } // match: (ANDconst [c] (MOVDconst [d])) // result: (MOVDconst [c&d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c & d) return true } // match: (ANDconst [c] (ANDconst [d] x)) // result: (ANDconst [c&d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDconst [c] (MOVWUreg x)) // result: (ANDconst [c&(1<<32-1)] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg { break } x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<32 - 1)) v.AddArg(x) return true } // match: (ANDconst [c] (MOVHUreg x)) // result: (ANDconst [c&(1<<16-1)] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg { break } x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<16 - 1)) v.AddArg(x) return true } // match: (ANDconst [c] (MOVBUreg x)) // result: (ANDconst [c&(1<<8-1)] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg { break } x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<8 - 1)) v.AddArg(x) return true } // match: (ANDconst [ac] (SLLconst [sc] x)) // cond: isARM64BFMask(sc, ac, sc) // result: (UBFIZ [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x) for { ac := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(sc, ac, sc)) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc, arm64BFWidth(ac, sc))) v.AddArg(x) return true } // match: (ANDconst [ac] (SRLconst [sc] x)) // cond: isARM64BFMask(sc, ac, 0) // result: (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, 0))] x) for { ac := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(sc, ac, 0)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc, arm64BFWidth(ac, 0))) v.AddArg(x) return true } // match: (ANDconst [c] (UBFX [bfc] x)) // cond: isARM64BFMask(0, c, 0) // result: (UBFX [armBFAuxInt(bfc.getARM64BFlsb(), min(bfc.getARM64BFwidth(), arm64BFWidth(c, 0)))] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(0, c, 0)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb(), min(bfc.getARM64BFwidth(), arm64BFWidth(c, 0)))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ANDshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ANDshiftLL (MOVDconst [c]) x [d]) // result: (ANDconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftLL x (MOVDconst [c]) [d]) // result: (ANDconst x [int64(uint64(c)< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftRA x (MOVDconst [c]) [d]) // result: (ANDconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (ANDshiftRA y:(SRAconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRAconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64ANDshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ANDshiftRL (MOVDconst [c]) x [d]) // result: (ANDconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftRL x (MOVDconst [c]) [d]) // result: (ANDconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (ANDshiftRL y:(SRLconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRLconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64ANDshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ANDshiftRO (MOVDconst [c]) x [d]) // result: (ANDconst [c] (RORconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ANDshiftRO x (MOVDconst [c]) [d]) // result: (ANDconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } // match: (ANDshiftRO y:(RORconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64RORconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64BIC(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BIC x (MOVDconst [c])) // result: (ANDconst [^c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^c) v.AddArg(x) return true } // match: (BIC x x) // result: (MOVDconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (BIC x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (BIC x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (BIC x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (BIC x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (BICshiftRO x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64BICshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64BICshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BICshiftLL x (MOVDconst [c]) [d]) // result: (ANDconst x [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) v.AddArg(x) return true } // match: (BICshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64BICshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BICshiftRL x (MOVDconst [c]) [d]) // result: (ANDconst x [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (BICshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64BICshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (BICshiftRO x (MOVDconst [c]) [d]) // result: (ANDconst x [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) v.AddArg(x) return true } // match: (BICshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64CMN(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMN x (MOVDconst [c])) // result: (CMNconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (CMN x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMNshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64CMNshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (CMN x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMNshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64CMNshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (CMN x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (CMNshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64CMNshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64CMNW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMNW x (MOVDconst [c])) // result: (CMNWconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNWconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueARM64_OpARM64CMNWconst(v *Value) bool { v_0 := v.Args[0] // match: (CMNWconst [c] y) // cond: c < 0 && c != -1<<31 // result: (CMPWconst [-c] y) for { c := auxIntToInt32(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<31) { break } v.reset(OpARM64CMPWconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(y) return true } // match: (CMNWconst (MOVDconst [x]) [y]) // result: (FlagConstant [addFlags32(int32(x),y)]) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(addFlags32(int32(x), y)) return true } return false } func rewriteValueARM64_OpARM64CMNconst(v *Value) bool { v_0 := v.Args[0] // match: (CMNconst [c] y) // cond: c < 0 && c != -1<<63 // result: (CMPconst [-c] y) for { c := auxIntToInt64(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<63) { break } v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(-c) v.AddArg(y) return true } // match: (CMNconst (MOVDconst [x]) [y]) // result: (FlagConstant [addFlags64(x,y)]) for { y := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(addFlags64(x, y)) return true } return false } func rewriteValueARM64_OpARM64CMNshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMNshiftLL (MOVDconst [c]) x [d]) // result: (CMNconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMNshiftLL x (MOVDconst [c]) [d]) // result: (CMNconst x [int64(uint64(c)< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMNshiftRA x (MOVDconst [c]) [d]) // result: (CMNconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CMNshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMNshiftRL (MOVDconst [c]) x [d]) // result: (CMNconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMNshiftRL x (MOVDconst [c]) [d]) // result: (CMNconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CMP(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMP x (MOVDconst [c])) // result: (CMPconst [c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (CMP (MOVDconst [c]) x) // result: (InvertFlags (CMPconst [c] x)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMP x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMP y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } // match: (CMP x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMPshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64CMPshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (CMP x0:(SLLconst [c] y) x1) // cond: clobberIfDead(x0) // result: (InvertFlags (CMPshiftLL x1 y [c])) for { x0 := v_0 if x0.Op != OpARM64SLLconst { break } c := auxIntToInt64(x0.AuxInt) y := x0.Args[0] x1 := v_1 if !(clobberIfDead(x0)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPshiftLL, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg2(x1, y) v.AddArg(v0) return true } // match: (CMP x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (CMPshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64CMPshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (CMP x0:(SRLconst [c] y) x1) // cond: clobberIfDead(x0) // result: (InvertFlags (CMPshiftRL x1 y [c])) for { x0 := v_0 if x0.Op != OpARM64SRLconst { break } c := auxIntToInt64(x0.AuxInt) y := x0.Args[0] x1 := v_1 if !(clobberIfDead(x0)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRL, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg2(x1, y) v.AddArg(v0) return true } // match: (CMP x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (CMPshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64CMPshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (CMP x0:(SRAconst [c] y) x1) // cond: clobberIfDead(x0) // result: (InvertFlags (CMPshiftRA x1 y [c])) for { x0 := v_0 if x0.Op != OpARM64SRAconst { break } c := auxIntToInt64(x0.AuxInt) y := x0.Args[0] x1 := v_1 if !(clobberIfDead(x0)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRA, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg2(x1, y) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64CMPW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPW x (MOVDconst [c])) // result: (CMPWconst [int32(c)] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPWconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } // match: (CMPW (MOVDconst [c]) x) // result: (InvertFlags (CMPWconst [int32(c)] x)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(x) v.AddArg(v0) return true } // match: (CMPW x y) // cond: canonLessThan(x,y) // result: (InvertFlags (CMPW y x)) for { x := v_0 y := v_1 if !(canonLessThan(x, y)) { break } v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(y, x) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64CMPWconst(v *Value) bool { v_0 := v.Args[0] // match: (CMPWconst [c] y) // cond: c < 0 && c != -1<<31 // result: (CMNWconst [-c] y) for { c := auxIntToInt32(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<31) { break } v.reset(OpARM64CMNWconst) v.AuxInt = int32ToAuxInt(-c) v.AddArg(y) return true } // match: (CMPWconst (MOVDconst [x]) [y]) // result: (FlagConstant [subFlags32(int32(x),y)]) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags32(int32(x), y)) return true } // match: (CMPWconst (MOVBUreg _) [c]) // cond: 0xff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVBUreg || !(0xff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPWconst (MOVHUreg _) [c]) // cond: 0xffff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVHUreg || !(0xffff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } return false } func rewriteValueARM64_OpARM64CMPconst(v *Value) bool { v_0 := v.Args[0] // match: (CMPconst [c] y) // cond: c < 0 && c != -1<<63 // result: (CMNconst [-c] y) for { c := auxIntToInt64(v.AuxInt) y := v_0 if !(c < 0 && c != -1<<63) { break } v.reset(OpARM64CMNconst) v.AuxInt = int64ToAuxInt(-c) v.AddArg(y) return true } // match: (CMPconst (MOVDconst [x]) [y]) // result: (FlagConstant [subFlags64(x,y)]) for { y := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(x, y)) return true } // match: (CMPconst (MOVBUreg _) [c]) // cond: 0xff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg || !(0xff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (MOVHUreg _) [c]) // cond: 0xffff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg || !(0xffff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (MOVWUreg _) [c]) // cond: 0xffffffff < c // result: (FlagConstant [subFlags64(0,1)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg || !(0xffffffff < c) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (ANDconst _ [m]) [n]) // cond: 0 <= m && m < n // result: (FlagConstant [subFlags64(0,1)]) for { n := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } m := auxIntToInt64(v_0.AuxInt) if !(0 <= m && m < n) { break } v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(subFlags64(0, 1)) return true } // match: (CMPconst (SRLconst _ [c]) [n]) // cond: 0 <= n && 0 < c && c <= 63 && (1< x [d]))) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v1 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v1.AuxInt = int64ToAuxInt(d) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (CMPshiftLL x (MOVDconst [c]) [d]) // result: (CMPconst x [int64(uint64(c)< x [d]))) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v1 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v1.AuxInt = int64ToAuxInt(d) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (CMPshiftRA x (MOVDconst [c]) [d]) // result: (CMPconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CMPshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CMPshiftRL (MOVDconst [c]) x [d]) // result: (InvertFlags (CMPconst [c] (SRLconst x [d]))) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v1 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v1.AuxInt = int64ToAuxInt(d) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } // match: (CMPshiftRL x (MOVDconst [c]) [d]) // result: (CMPconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64CMPconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64CSEL(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSEL [cc] (MOVDconst [-1]) (MOVDconst [0]) flag) // result: (CSETM [cc] flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != -1 || v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } flag := v_2 v.reset(OpARM64CSETM) v.AuxInt = opToAuxInt(cc) v.AddArg(flag) return true } // match: (CSEL [cc] (MOVDconst [0]) (MOVDconst [-1]) flag) // result: (CSETM [arm64Negate(cc)] flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 0 || v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { break } flag := v_2 v.reset(OpARM64CSETM) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg(flag) return true } // match: (CSEL [cc] x (MOVDconst [0]) flag) // result: (CSEL0 [cc] x flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } flag := v_2 v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(cc) v.AddArg2(x, flag) return true } // match: (CSEL [cc] (MOVDconst [0]) y flag) // result: (CSEL0 [arm64Negate(cc)] y flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 0 { break } y := v_1 flag := v_2 v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg2(y, flag) return true } // match: (CSEL [cc] x (ADDconst [1] a) flag) // result: (CSINC [cc] x a flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } a := v_1.Args[0] flag := v_2 v.reset(OpARM64CSINC) v.AuxInt = opToAuxInt(cc) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] (ADDconst [1] a) x flag) // result: (CSINC [arm64Negate(cc)] x a flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64ADDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } a := v_0.Args[0] x := v_1 flag := v_2 v.reset(OpARM64CSINC) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] x (MVN a) flag) // result: (CSINV [cc] x a flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64MVN { break } a := v_1.Args[0] flag := v_2 v.reset(OpARM64CSINV) v.AuxInt = opToAuxInt(cc) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] (MVN a) x flag) // result: (CSINV [arm64Negate(cc)] x a flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64MVN { break } a := v_0.Args[0] x := v_1 flag := v_2 v.reset(OpARM64CSINV) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] x (NEG a) flag) // result: (CSNEG [cc] x a flag) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64NEG { break } a := v_1.Args[0] flag := v_2 v.reset(OpARM64CSNEG) v.AuxInt = opToAuxInt(cc) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] (NEG a) x flag) // result: (CSNEG [arm64Negate(cc)] x a flag) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64NEG { break } a := v_0.Args[0] x := v_1 flag := v_2 v.reset(OpARM64CSNEG) v.AuxInt = opToAuxInt(arm64Negate(cc)) v.AddArg3(x, a, flag) return true } // match: (CSEL [cc] x y (InvertFlags cmp)) // result: (CSEL [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSEL [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSEL [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: y for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.copyOf(y) return true } // match: (CSEL [cc] x y (CMPWconst [0] boolval)) // cond: cc == OpARM64NotEqual && flagArg(boolval) != nil // result: (CSEL [boolval.Op] x y flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64CMPWconst || auxIntToInt32(v_2.AuxInt) != 0 { break } boolval := v_2.Args[0] if !(cc == OpARM64NotEqual && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(boolval.Op) v.AddArg3(x, y, flagArg(boolval)) return true } // match: (CSEL [cc] x y (CMPWconst [0] boolval)) // cond: cc == OpARM64Equal && flagArg(boolval) != nil // result: (CSEL [arm64Negate(boolval.Op)] x y flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64CMPWconst || auxIntToInt32(v_2.AuxInt) != 0 { break } boolval := v_2.Args[0] if !(cc == OpARM64Equal && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(arm64Negate(boolval.Op)) v.AddArg3(x, y, flagArg(boolval)) return true } return false } func rewriteValueARM64_OpARM64CSEL0(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSEL0 [cc] x (InvertFlags cmp)) // result: (CSEL0 [arm64Invert(cc)] x cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64InvertFlags { break } cmp := v_1.Args[0] v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg2(x, cmp) return true } // match: (CSEL0 [cc] x flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_1 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSEL0 [cc] _ flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (MOVDconst [0]) for { cc := auxIntToOp(v.AuxInt) flag := v_1 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (CSEL0 [cc] x (CMPWconst [0] boolval)) // cond: cc == OpARM64NotEqual && flagArg(boolval) != nil // result: (CSEL0 [boolval.Op] x flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64CMPWconst || auxIntToInt32(v_1.AuxInt) != 0 { break } boolval := v_1.Args[0] if !(cc == OpARM64NotEqual && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(boolval.Op) v.AddArg2(x, flagArg(boolval)) return true } // match: (CSEL0 [cc] x (CMPWconst [0] boolval)) // cond: cc == OpARM64Equal && flagArg(boolval) != nil // result: (CSEL0 [arm64Negate(boolval.Op)] x flagArg(boolval)) for { cc := auxIntToOp(v.AuxInt) x := v_0 if v_1.Op != OpARM64CMPWconst || auxIntToInt32(v_1.AuxInt) != 0 { break } boolval := v_1.Args[0] if !(cc == OpARM64Equal && flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL0) v.AuxInt = opToAuxInt(arm64Negate(boolval.Op)) v.AddArg2(x, flagArg(boolval)) return true } return false } func rewriteValueARM64_OpARM64CSETM(v *Value) bool { v_0 := v.Args[0] // match: (CSETM [cc] (InvertFlags cmp)) // result: (CSETM [arm64Invert(cc)] cmp) for { cc := auxIntToOp(v.AuxInt) if v_0.Op != OpARM64InvertFlags { break } cmp := v_0.Args[0] v.reset(OpARM64CSETM) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg(cmp) return true } // match: (CSETM [cc] flag) // cond: ccARM64Eval(cc, flag) > 0 // result: (MOVDconst [-1]) for { cc := auxIntToOp(v.AuxInt) flag := v_0 if !(ccARM64Eval(cc, flag) > 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (CSETM [cc] flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (MOVDconst [0]) for { cc := auxIntToOp(v.AuxInt) flag := v_0 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64CSINC(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSINC [cc] x y (InvertFlags cmp)) // result: (CSINC [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSINC) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSINC [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSINC [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (ADDconst [1] y) for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(1) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64CSINV(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSINV [cc] x y (InvertFlags cmp)) // result: (CSINV [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSINV) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSINV [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSINV [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (Not y) for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpNot) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64CSNEG(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CSNEG [cc] x y (InvertFlags cmp)) // result: (CSNEG [arm64Invert(cc)] x y cmp) for { cc := auxIntToOp(v.AuxInt) x := v_0 y := v_1 if v_2.Op != OpARM64InvertFlags { break } cmp := v_2.Args[0] v.reset(OpARM64CSNEG) v.AuxInt = opToAuxInt(arm64Invert(cc)) v.AddArg3(x, y, cmp) return true } // match: (CSNEG [cc] x _ flag) // cond: ccARM64Eval(cc, flag) > 0 // result: x for { cc := auxIntToOp(v.AuxInt) x := v_0 flag := v_2 if !(ccARM64Eval(cc, flag) > 0) { break } v.copyOf(x) return true } // match: (CSNEG [cc] _ y flag) // cond: ccARM64Eval(cc, flag) < 0 // result: (NEG y) for { cc := auxIntToOp(v.AuxInt) y := v_1 flag := v_2 if !(ccARM64Eval(cc, flag) < 0) { break } v.reset(OpARM64NEG) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64DIV(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIV (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [c/d]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c / d) return true } return false } func rewriteValueARM64_OpARM64DIVW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (DIVW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(int32(c)/int32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) / int32(d))) return true } return false } func rewriteValueARM64_OpARM64EON(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EON x (MOVDconst [c])) // result: (XORconst [^c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^c) v.AddArg(x) return true } // match: (EON x x) // result: (MOVDconst [-1]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (EON x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (EON x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (EON x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (EON x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (EONshiftRO x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64EONshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64EONshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EONshiftLL x (MOVDconst [c]) [d]) // result: (XORconst x [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) v.AddArg(x) return true } // match: (EONshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64EONshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EONshiftRL x (MOVDconst [c]) [d]) // result: (XORconst x [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (EONshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64EONshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (EONshiftRO x (MOVDconst [c]) [d]) // result: (XORconst x [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) v.AddArg(x) return true } // match: (EONshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64Equal(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Equal (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (Equal (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (Equal (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMP x z:(NEG y))) // cond: z.Uses == 1 // result: (Equal (CMN x y)) for { if v_0.Op != OpARM64CMP { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPW x z:(NEG y))) // cond: z.Uses == 1 // result: (Equal (CMNW x y)) for { if v_0.Op != OpARM64CMPW { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (Equal (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (Equal (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (Equal (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (Equal (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (Equal (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (Equal (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (Equal (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (Equal (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.eq())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.eq())) return true } // match: (Equal (InvertFlags x)) // result: (Equal x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64Equal) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64FADDD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FADDD a (FMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDD a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FMULD { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMADDD) v.AddArg3(a, x, y) return true } break } // match: (FADDD a (FNMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBD a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FNMULD { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMSUBD) v.AddArg3(a, x, y) return true } break } return false } func rewriteValueARM64_OpARM64FADDS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FADDS a (FMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDS a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FMULS { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMADDS) v.AddArg3(a, x, y) return true } break } // match: (FADDS a (FNMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBS a x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { a := v_0 if v_1.Op != OpARM64FNMULS { continue } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { continue } v.reset(OpARM64FMSUBS) v.AddArg3(a, x, y) return true } break } return false } func rewriteValueARM64_OpARM64FCMPD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (FCMPD x (FMOVDconst [0])) // result: (FCMPD0 x) for { x := v_0 if v_1.Op != OpARM64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != 0 { break } v.reset(OpARM64FCMPD0) v.AddArg(x) return true } // match: (FCMPD (FMOVDconst [0]) x) // result: (InvertFlags (FCMPD0 x)) for { if v_0.Op != OpARM64FMOVDconst || auxIntToFloat64(v_0.AuxInt) != 0 { break } x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64FCMPD0, types.TypeFlags) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64FCMPS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (FCMPS x (FMOVSconst [0])) // result: (FCMPS0 x) for { x := v_0 if v_1.Op != OpARM64FMOVSconst || auxIntToFloat64(v_1.AuxInt) != 0 { break } v.reset(OpARM64FCMPS0) v.AddArg(x) return true } // match: (FCMPS (FMOVSconst [0]) x) // result: (InvertFlags (FCMPS0 x)) for { if v_0.Op != OpARM64FMOVSconst || auxIntToFloat64(v_0.AuxInt) != 0 { break } x := v_1 v.reset(OpARM64InvertFlags) v0 := b.NewValue0(v.Pos, OpARM64FCMPS0, types.TypeFlags) v0.AddArg(x) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpARM64FMOVDfpgp(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (FMOVDfpgp (Arg [off] {sym})) // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueARM64_OpARM64FMOVDgpfp(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (FMOVDgpfp (Arg [off] {sym})) // result: @b.Func.Entry (Arg [off] {sym}) for { t := v.Type if v_0.Op != OpArg { break } off := auxIntToInt32(v_0.AuxInt) sym := auxToSym(v_0.Aux) b = b.Func.Entry v0 := b.NewValue0(v.Pos, OpArg, t) v.copyOf(v0) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) return true } return false } func rewriteValueARM64_OpARM64FMOVDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _)) // result: (FMOVDgpfp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVDgpfp) v.AddArg(val) return true } // match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (FMOVDload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVDloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVDloadidx8 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (FMOVDload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVDloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (FMOVDload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVDloadidx ptr (SLLconst [3] idx) mem) // result: (FMOVDloadidx8 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVDloadidx (SLLconst [3] idx) ptr mem) // result: (FMOVDloadidx8 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64FMOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDloadidx8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDloadidx8 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<3) // result: (FMOVDload ptr [int32(c)<<3] mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 3)) { break } v.reset(OpARM64FMOVDload) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVDstore [off] {sym} ptr (FMOVDgpfp val) mem) // result: (MOVDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVDgpfp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVDstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVDstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVDstoreidx8 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (FMOVDstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (FMOVDstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (FMOVDstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (FMOVDstoreidx ptr (SLLconst [3] idx) val mem) // result: (FMOVDstoreidx8 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64FMOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVDstoreidx (SLLconst [3] idx) ptr val mem) // result: (FMOVDstoreidx8 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64FMOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVDstoreidx8(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVDstoreidx8 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<3) // result: (FMOVDstore [int32(c)<<3] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 3)) { break } v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVSload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) // result: (FMOVSgpfp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVSgpfp) v.AddArg(val) return true } // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (FMOVSload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVSloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVSload [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (FMOVSloadidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (FMOVSload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVSloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (FMOVSload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (FMOVSloadidx ptr (SLLconst [2] idx) mem) // result: (FMOVSloadidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVSloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (FMOVSloadidx (SLLconst [2] idx) ptr mem) // result: (FMOVSloadidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64FMOVSloadidx4) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSloadidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSloadidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (FMOVSload ptr [int32(c)<<2] mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64FMOVSload) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (FMOVSstore [off] {sym} ptr (FMOVSgpfp val) mem) // result: (MOVWstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVSgpfp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (FMOVSstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVSstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVSstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (FMOVSstoreidx4 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64FMOVSstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (FMOVSstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (FMOVSstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (FMOVSstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (FMOVSstoreidx ptr (SLLconst [2] idx) val mem) // result: (FMOVSstoreidx4 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64FMOVSstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (FMOVSstoreidx (SLLconst [2] idx) ptr val mem) // result: (FMOVSstoreidx4 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64FMOVSstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMOVSstoreidx4(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMOVSstoreidx4 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<2) // result: (FMOVSstore [int32(c)<<2] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 2)) { break } v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpARM64FMULD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMULD (FNEGD x) y) // result: (FNMULD x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGD { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FNMULD) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FMULS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMULS (FNEGS x) y) // result: (FNMULS x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGS { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FNMULS) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FNEGD(v *Value) bool { v_0 := v.Args[0] // match: (FNEGD (FMULD x y)) // result: (FNMULD x y) for { if v_0.Op != OpARM64FMULD { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FNMULD) v.AddArg2(x, y) return true } // match: (FNEGD (FNMULD x y)) // result: (FMULD x y) for { if v_0.Op != OpARM64FNMULD { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FMULD) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64FNEGS(v *Value) bool { v_0 := v.Args[0] // match: (FNEGS (FMULS x y)) // result: (FNMULS x y) for { if v_0.Op != OpARM64FMULS { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FNMULS) v.AddArg2(x, y) return true } // match: (FNEGS (FNMULS x y)) // result: (FMULS x y) for { if v_0.Op != OpARM64FNMULS { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64FMULS) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64FNMULD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FNMULD (FNEGD x) y) // result: (FMULD x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGD { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FMULD) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FNMULS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FNMULS (FNEGS x) y) // result: (FMULS x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64FNEGS { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64FMULS) v.AddArg2(x, y) return true } break } return false } func rewriteValueARM64_OpARM64FSUBD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FSUBD a (FMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBD a x y) for { a := v_0 if v_1.Op != OpARM64FMULD { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMSUBD) v.AddArg3(a, x, y) return true } // match: (FSUBD (FMULD x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMSUBD a x y) for { if v_0.Op != OpARM64FMULD { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMSUBD) v.AddArg3(a, x, y) return true } // match: (FSUBD a (FNMULD x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDD a x y) for { a := v_0 if v_1.Op != OpARM64FNMULD { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMADDD) v.AddArg3(a, x, y) return true } // match: (FSUBD (FNMULD x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMADDD a x y) for { if v_0.Op != OpARM64FNMULD { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMADDD) v.AddArg3(a, x, y) return true } return false } func rewriteValueARM64_OpARM64FSUBS(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FSUBS a (FMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMSUBS a x y) for { a := v_0 if v_1.Op != OpARM64FMULS { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMSUBS) v.AddArg3(a, x, y) return true } // match: (FSUBS (FMULS x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMSUBS a x y) for { if v_0.Op != OpARM64FMULS { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMSUBS) v.AddArg3(a, x, y) return true } // match: (FSUBS a (FNMULS x y)) // cond: a.Block.Func.useFMA(v) // result: (FMADDS a x y) for { a := v_0 if v_1.Op != OpARM64FNMULS { break } y := v_1.Args[1] x := v_1.Args[0] if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FMADDS) v.AddArg3(a, x, y) return true } // match: (FSUBS (FNMULS x y) a) // cond: a.Block.Func.useFMA(v) // result: (FNMADDS a x y) for { if v_0.Op != OpARM64FNMULS { break } y := v_0.Args[1] x := v_0.Args[0] a := v_1 if !(a.Block.Func.useFMA(v)) { break } v.reset(OpARM64FNMADDS) v.AddArg3(a, x, y) return true } return false } func rewriteValueARM64_OpARM64GreaterEqual(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (GreaterEqual (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterEqual (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqual (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterEqual (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqual (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqualNoov (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterEqualNoov (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (GreaterEqualNoov (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterEqualNoov) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (GreaterEqual (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ge())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ge())) return true } // match: (GreaterEqual (InvertFlags x)) // result: (LessEqual x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessEqual) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterEqualF(v *Value) bool { v_0 := v.Args[0] // match: (GreaterEqualF (InvertFlags x)) // result: (LessEqualF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessEqualF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterEqualU(v *Value) bool { v_0 := v.Args[0] // match: (GreaterEqualU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.uge())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.uge())) return true } // match: (GreaterEqualU (InvertFlags x)) // result: (LessEqualU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessEqualU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterThan(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (GreaterThan (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterThan (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterThan (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterThan (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterThan (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (GreaterThan (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (GreaterThan (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (GreaterThan (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64GreaterThan) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (GreaterThan (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.gt())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.gt())) return true } // match: (GreaterThan (InvertFlags x)) // result: (LessThan x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessThan) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterThanF(v *Value) bool { v_0 := v.Args[0] // match: (GreaterThanF (InvertFlags x)) // result: (LessThanF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessThanF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64GreaterThanU(v *Value) bool { v_0 := v.Args[0] // match: (GreaterThanU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ugt())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ugt())) return true } // match: (GreaterThanU (InvertFlags x)) // result: (LessThanU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64LessThanU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LDP(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (LDP [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (LDP [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64LDP) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (LDP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (LDP [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64LDP) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64LessEqual(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (LessEqual (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessEqual (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessEqual (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessEqual (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessEqual (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessEqual (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessEqual (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessEqual (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessEqual (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.le())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.le())) return true } // match: (LessEqual (InvertFlags x)) // result: (GreaterEqual x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterEqual) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessEqualF(v *Value) bool { v_0 := v.Args[0] // match: (LessEqualF (InvertFlags x)) // result: (GreaterEqualF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterEqualF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessEqualU(v *Value) bool { v_0 := v.Args[0] // match: (LessEqualU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ule())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ule())) return true } // match: (LessEqualU (InvertFlags x)) // result: (GreaterEqualU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterEqualU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessThan(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (LessThan (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessThan (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessThan (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (LessThan (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (LessThan (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (LessThanNoov (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (LessThanNoov (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (LessThanNoov (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64LessThanNoov) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (LessThan (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.lt())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.lt())) return true } // match: (LessThan (InvertFlags x)) // result: (GreaterThan x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterThan) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessThanF(v *Value) bool { v_0 := v.Args[0] // match: (LessThanF (InvertFlags x)) // result: (GreaterThanF x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterThanF) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64LessThanU(v *Value) bool { v_0 := v.Args[0] // match: (LessThanU (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ult())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ult())) return true } // match: (LessThanU (InvertFlags x)) // result: (GreaterThanU x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64GreaterThanU) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MADD(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MADD a x (MOVDconst [-1])) // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != -1 { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADD a _ (MOVDconst [0])) // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MADD a x (MOVDconst [1])) // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 1 { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADD a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADD a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [-1]) x) // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { break } x := v_2 v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADD a (MOVDconst [0]) _) // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MADD a (MOVDconst [1]) x) // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } x := v_2 v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADD a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADD a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADD (MOVDconst [c]) x y) // result: (ADDconst [c] (MUL x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MADD a (MOVDconst [c]) (MOVDconst [d])) // result: (ADDconst [c*d] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c * d) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MADDW(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MADDW a x (MOVDconst [c])) // cond: int32(c)==-1 // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == -1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADDW a _ (MOVDconst [c])) // cond: int32(c)==0 // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MADDW a x (MOVDconst [c])) // cond: int32(c)==1 // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADDW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADDW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: int32(c)==-1 // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == -1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MADDW a (MOVDconst [c]) _) // cond: int32(c)==0 // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: int32(c)==1 // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == 1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (ADDshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (ADD a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (SUB a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SUBshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (ADDshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MADDW (MOVDconst [c]) x y) // result: (ADDconst [c] (MULW x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MADDW a (MOVDconst [c]) (MOVDconst [d])) // result: (ADDconst [int64(int32(c)*int32(d))] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) * int32(d))) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MNEG(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MNEG x (MOVDconst [-1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { continue } v.copyOf(x) return true } break } // match: (MNEG _ (MOVDconst [0])) // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MNEG x (MOVDconst [1])) // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (NEG (SLLconst [log64(c)] x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c)) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c >= 3 // result: (NEG (ADDshiftLL x x [log64(c-1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c >= 7 // result: (NEG (ADDshiftLL (NEG x) x [log64(c+1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SLLconst [log64(c/3)] (SUBshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (NEG (SLLconst [log64(c/5)] (ADDshiftLL x x [2]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 5)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(2) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SLLconst [log64(c/7)] (SUBshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEG x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (NEG (SLLconst [log64(c/9)] (ADDshiftLL x x [3]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 9)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(3) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEG (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [-c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-c * d) return true } break } return false } func rewriteValueARM64_OpARM64MNEGW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MNEGW x (MOVDconst [c])) // cond: int32(c)==-1 // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == -1) { continue } v.copyOf(x) return true } break } // match: (MNEGW _ (MOVDconst [c])) // cond: int32(c)==0 // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: int32(c)==1 // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 1) { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (NEG (SLLconst [log64(c)] x)) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c)) v0.AddArg(x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c) >= 3 // result: (NEG (ADDshiftLL x x [log64(c-1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c) >= 7 // result: (NEG (ADDshiftLL (NEG x) x [log64(c+1)])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SLLconst [log64(c/3)] (SUBshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (NEG (SLLconst [log64(c/5)] (ADDshiftLL x x [2]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 5)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(2) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SLLconst [log64(c/7)] (SUBshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.Type = x.Type v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MNEGW x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (NEG (SLLconst [log64(c/9)] (ADDshiftLL x x [3]))) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { continue } v.reset(OpARM64NEG) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(log64(c / 9)) v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v1.AuxInt = int64ToAuxInt(3) v1.AddArg2(x, x) v0.AddArg(v1) v.AddArg(v0) return true } break } // match: (MNEGW (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [-int64(int32(c)*int32(d))]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-int64(int32(c) * int32(d))) return true } break } return false } func rewriteValueARM64_OpARM64MOD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOD (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [c%d]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c % d) return true } return false } func rewriteValueARM64_OpARM64MODW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MODW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(int32(c)%int32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) % int32(d))) return true } return false } func rewriteValueARM64_OpARM64MOVBUload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBUload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBUload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVBUloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBUloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBUload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVBUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read8(sym, int64(off)))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read8(sym, int64(off)))) return true } return false } func rewriteValueARM64_OpARM64MOVBUloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBUloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVBUload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBUloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVBUload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBUloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVBUreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVBUreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<8-1)] x) for { if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<8 - 1)) v.AddArg(x) return true } // match: (MOVBUreg (MOVDconst [c])) // result: (MOVDconst [int64(uint8(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint8(c))) return true } // match: (MOVBUreg x:(Equal _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64Equal { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(NotEqual _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64NotEqual { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessThan _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessThan { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessThanU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessThanU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessThanF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessThanF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessEqual _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessEqual { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessEqualU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessEqualU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(LessEqualF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64LessEqualF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterThan _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterThan { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterThanU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterThanU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterThanF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterThanF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterEqual _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterEqual { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterEqualU _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterEqualU { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(GreaterEqualF _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64GreaterEqualF { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg (SLLconst [lc] x)) // cond: lc >= 8 // result: (MOVDconst [0]) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) if !(lc >= 8) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVBUreg (SLLconst [lc] x)) // cond: lc < 8 // result: (UBFIZ [armBFAuxInt(lc, 8-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 8) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 8-lc)) v.AddArg(x) return true } // match: (MOVBUreg (SRLconst [rc] x)) // cond: rc < 8 // result: (UBFX [armBFAuxInt(rc, 8)] x) for { if v_0.Op != OpARM64SRLconst { break } rc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(rc < 8) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8)) v.AddArg(x) return true } // match: (MOVBUreg (UBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 8 // result: (UBFX [bfc] x) for { if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 8) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVBload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVBloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVBloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVBload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVBload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVBreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVBreg x:(MOVBload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBreg x:(MOVBloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBreg x:(MOVBreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBreg (MOVDconst [c])) // result: (MOVDconst [int64(int8(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int8(c))) return true } // match: (MOVBreg (ANDconst x [c])) // cond: uint64(c) & uint64(0xffffffffffffff80) == 0 // result: (ANDconst x [c]) for { t := v.Type if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(uint64(c)&uint64(0xffffffffffffff80) == 0) { break } v.reset(OpARM64ANDconst) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (MOVBreg (SLLconst [lc] x)) // cond: lc < 8 // result: (SBFIZ [armBFAuxInt(lc, 8-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 8) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 8-lc)) v.AddArg(x) return true } // match: (MOVBreg (SBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 8 // result: (SBFX [bfc] x) for { if v_0.Op != OpARM64SBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 8) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVBstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVBstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVBstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVBUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) // result: (MOVBstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVBstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVBstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVBstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVBstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVBstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVBstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVBstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVBstoreidx ptr idx (MOVBreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVBUreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVBUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVHreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVHUreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVWreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVBstoreidx ptr idx (MOVWUreg x) mem) // result: (MOVBstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVBstoreidx) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVBstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVBstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVBstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVBstorezeroidx) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVBstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVBstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVBstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVBstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVBstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVBstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr val _)) // result: (FMOVDfpgp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVDstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVDfpgp) v.AddArg(val) return true } // match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVDload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDloadidx8 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVDload [off] {sym} ptr (MOVDstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVDload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueARM64_OpARM64MOVDloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVDload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVDloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVDload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVDloadidx ptr (SLLconst [3] idx) mem) // result: (MOVDloadidx8 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDloadidx (SLLconst [3] idx) ptr mem) // result: (MOVDloadidx8 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVDloadidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDloadidx ptr idx (MOVDstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVDloadidx8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDloadidx8 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<3) // result: (MOVDload [int32(c)<<3] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 3)) { break } v.reset(OpARM64MOVDload) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg2(ptr, mem) return true } // match: (MOVDloadidx8 ptr idx (MOVDstorezeroidx8 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDstorezeroidx8 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVDnop(v *Value) bool { v_0 := v.Args[0] // match: (MOVDnop (MOVDconst [c])) // result: (MOVDconst [c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValueARM64_OpARM64MOVDreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVDreg x) // cond: x.Uses == 1 // result: (MOVDnop x) for { x := v_0 if !(x.Uses == 1) { break } v.reset(OpARM64MOVDnop) v.AddArg(x) return true } // match: (MOVDreg (MOVDconst [c])) // result: (MOVDconst [c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c) return true } return false } func rewriteValueARM64_OpARM64MOVDstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVDstore [off] {sym} ptr (FMOVDfpgp val) mem) // result: (FMOVDstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVDfpgp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVDstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVDstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVDstoreidx8 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVDstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVDstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVDstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVDstoreidx ptr (SLLconst [3] idx) val mem) // result: (MOVDstoreidx8 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64MOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstoreidx (SLLconst [3] idx) ptr val mem) // result: (MOVDstoreidx8 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVDstoreidx8) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVDstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVDstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVDstorezeroidx) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstoreidx8(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstoreidx8 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<3) // result: (MOVDstore [int32(c)<<3] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 3)) { break } v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(int32(c) << 3) v.AddArg3(ptr, val, mem) return true } // match: (MOVDstoreidx8 ptr idx (MOVDconst [0]) mem) // result: (MOVDstorezeroidx8 ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVDstorezero {s} [i] ptr x:(MOVDstorezero {s} [i+8] ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstorezero {s} [i] ptr mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 x := v_1 if x.Op != OpARM64MOVDstorezero || auxIntToInt32(x.AuxInt) != i+8 || auxToSym(x.Aux) != s { break } mem := x.Args[1] if ptr != x.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(i) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezero {s} [i] ptr x:(MOVDstorezero {s} [i-8] ptr mem)) // cond: x.Uses == 1 && clobber(x) // result: (MOVQstorezero {s} [i-8] ptr mem) for { i := auxIntToInt32(v.AuxInt) s := auxToSym(v.Aux) ptr := v_0 x := v_1 if x.Op != OpARM64MOVDstorezero || auxIntToInt32(x.AuxInt) != i-8 || auxToSym(x.Aux) != s { break } mem := x.Args[1] if ptr != x.Args[0] || !(x.Uses == 1 && clobber(x)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(i - 8) v.Aux = symToAux(s) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDstorezero [off] {sym} (ADDshiftLL [3] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVDstorezeroidx8 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVDstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVDstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVDstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVDstorezeroidx ptr (SLLconst [3] idx) mem) // result: (MOVDstorezeroidx8 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 3 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } // match: (MOVDstorezeroidx (SLLconst [3] idx) ptr mem) // result: (MOVDstorezeroidx8 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 3 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVDstorezeroidx8) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVDstorezeroidx8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVDstorezeroidx8 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<3) // result: (MOVDstorezero [int32(c<<3)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 3)) { break } v.reset(OpARM64MOVDstorezero) v.AuxInt = int32ToAuxInt(int32(c << 3)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHUload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHUload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHUload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHUloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHUloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUload [off] {sym} (ADDshiftLL [1] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHUloadidx2 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVHUload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVHUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueARM64_OpARM64MOVHUloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHUloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVHUload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHUloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVHUload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHUloadidx ptr (SLLconst [1] idx) mem) // result: (MOVHUloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUloadidx ptr (ADD idx idx) mem) // result: (MOVHUloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } mem := v_2 v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUloadidx (ADD idx idx) ptr mem) // result: (MOVHUloadidx2 ptr idx mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 mem := v_2 v.reset(OpARM64MOVHUloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHUloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHUloadidx2(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHUloadidx2 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<1) // result: (MOVHUload [int32(c)<<1] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHUload) v.AuxInt = int32ToAuxInt(int32(c) << 1) v.AddArg2(ptr, mem) return true } // match: (MOVHUloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx2 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHUreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVHUreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg x:(MOVHUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<16-1)] x) for { if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<16 - 1)) v.AddArg(x) return true } // match: (MOVHUreg (MOVDconst [c])) // result: (MOVDconst [int64(uint16(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint16(c))) return true } // match: (MOVHUreg (SLLconst [lc] x)) // cond: lc >= 16 // result: (MOVDconst [0]) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) if !(lc >= 16) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVHUreg (SLLconst [lc] x)) // cond: lc < 16 // result: (UBFIZ [armBFAuxInt(lc, 16-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 16) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 16-lc)) v.AddArg(x) return true } // match: (MOVHUreg (SRLconst [rc] x)) // cond: rc < 16 // result: (UBFX [armBFAuxInt(rc, 16)] x) for { if v_0.Op != OpARM64SRLconst { break } rc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(rc < 16) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 16)) v.AddArg(x) return true } // match: (MOVHUreg (UBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 16 // result: (UBFX [bfc] x) for { if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 16) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVHload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHload [off] {sym} (ADDshiftLL [1] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHloadidx2 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVHload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVHload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVHload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHloadidx ptr (SLLconst [1] idx) mem) // result: (MOVHloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHloadidx ptr (ADD idx idx) mem) // result: (MOVHloadidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } mem := v_2 v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHloadidx (ADD idx idx) ptr mem) // result: (MOVHloadidx2 ptr idx mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 mem := v_2 v.reset(OpARM64MOVHloadidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHloadidx2(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHloadidx2 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<1) // result: (MOVHload [int32(c)<<1] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHload) v.AuxInt = int32ToAuxInt(int32(c) << 1) v.AddArg2(ptr, mem) return true } // match: (MOVHloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHstorezeroidx2 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVHreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVHreg x:(MOVBload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg x:(MOVHreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVHreg (MOVDconst [c])) // result: (MOVDconst [int64(int16(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int16(c))) return true } // match: (MOVHreg (ANDconst x [c])) // cond: uint64(c) & uint64(0xffffffffffff8000) == 0 // result: (ANDconst x [c]) for { t := v.Type if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(uint64(c)&uint64(0xffffffffffff8000) == 0) { break } v.reset(OpARM64ANDconst) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (MOVHreg (SLLconst [lc] x)) // cond: lc < 16 // result: (SBFIZ [armBFAuxInt(lc, 16-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 16) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 16-lc)) v.AddArg(x) return true } // match: (MOVHreg (SBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 16 // result: (SBFX [bfc] x) for { if v_0.Op != OpARM64SBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 16) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVHstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVHstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstore [off] {sym} (ADDshiftLL [1] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVHstoreidx2 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVHstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVHUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) // result: (MOVHstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVHstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVHstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVHstoreidx ptr (SLLconst [1] idx) val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx ptr (ADD idx idx) val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx (SLLconst [1] idx) ptr val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx (ADD idx idx) ptr val mem) // result: (MOVHstoreidx2 ptr idx val mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVHstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVHstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVHstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstoreidx ptr idx (MOVHreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr idx (MOVHUreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr idx (MOVWreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx ptr idx (MOVWUreg x) mem) // result: (MOVHstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstoreidx2(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstoreidx2 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<1) // result: (MOVHstore [int32(c)<<1] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(int32(c) << 1) v.AddArg3(ptr, val, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVDconst [0]) mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVHreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVHUreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVHUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVWreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVHstoreidx2 ptr idx (MOVWUreg x) mem) // result: (MOVHstoreidx2 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVHstoreidx2) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVHstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezero [off] {sym} (ADDshiftLL [1] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVHstorezeroidx2 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVHstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVHstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVHstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVHstorezeroidx ptr (SLLconst [1] idx) mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 1 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx ptr (ADD idx idx) mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64ADD { break } idx := v_1.Args[1] if idx != v_1.Args[0] { break } mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx (SLLconst [1] idx) ptr mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 1 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } // match: (MOVHstorezeroidx (ADD idx idx) ptr mem) // result: (MOVHstorezeroidx2 ptr idx mem) for { if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] if idx != v_0.Args[0] { break } ptr := v_1 mem := v_2 v.reset(OpARM64MOVHstorezeroidx2) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVHstorezeroidx2(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVHstorezeroidx2 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<1) // result: (MOVHstorezero [int32(c<<1)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 1)) { break } v.reset(OpARM64MOVHstorezero) v.AuxInt = int32ToAuxInt(int32(c << 1)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVQstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVQstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVQstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWUload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWUload [off] {sym} ptr (FMOVSstore [off] {sym} ptr val _)) // result: (FMOVSfpgp val) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVSstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym { break } val := v_1.Args[1] if ptr != v_1.Args[0] { break } v.reset(OpARM64FMOVSfpgp) v.AddArg(val) return true } // match: (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWUload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWUload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWUloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWUloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUload [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWUloadidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWUloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWUload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVWUload [off] {sym} (SB) _) // cond: symIsRO(sym) // result: (MOVDconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpSB || !(symIsRO(sym)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))) return true } return false } func rewriteValueARM64_OpARM64MOVWUloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWUloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVWUload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWUloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVWUload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWUloadidx ptr (SLLconst [2] idx) mem) // result: (MOVWUloadidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWUloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUloadidx (SLLconst [2] idx) ptr mem) // result: (MOVWUloadidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVWUloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWUloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWUloadidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWUloadidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (MOVWUload [int32(c)<<2] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWUload) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg2(ptr, mem) return true } // match: (MOVWUloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx4 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWUreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVWUreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUloadidx4 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUloadidx4 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVHUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg (ANDconst [c] x)) // result: (ANDconst [c&(1<<32-1)] x) for { if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c & (1<<32 - 1)) v.AddArg(x) return true } // match: (MOVWUreg (MOVDconst [c])) // result: (MOVDconst [int64(uint32(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint32(c))) return true } // match: (MOVWUreg x) // cond: zeroUpper32Bits(x, 3) // result: x for { x := v_0 if !(zeroUpper32Bits(x, 3)) { break } v.copyOf(x) return true } // match: (MOVWUreg (SLLconst [lc] x)) // cond: lc >= 32 // result: (MOVDconst [0]) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) if !(lc >= 32) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (MOVWUreg (SLLconst [lc] x)) // cond: lc < 32 // result: (UBFIZ [armBFAuxInt(lc, 32-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 32) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 32-lc)) v.AddArg(x) return true } // match: (MOVWUreg (SRLconst [rc] x)) // cond: rc < 32 // result: (UBFX [armBFAuxInt(rc, 32)] x) for { if v_0.Op != OpARM64SRLconst { break } rc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(rc < 32) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 32)) v.AddArg(x) return true } // match: (MOVWUreg (UBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 32 // result: (UBFX [bfc] x) for { if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 32) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVWload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWload [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWloadidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWloadidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWload [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWloadidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) // result: (MOVDconst [0]) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWstorezero { break } off2 := auxIntToInt32(v_1.AuxInt) sym2 := auxToSym(v_1.Aux) ptr2 := v_1.Args[0] if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWloadidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWloadidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVWload [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWloadidx (MOVDconst [c]) ptr mem) // cond: is32Bit(c) // result: (MOVWload [int32(c)] ptr mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) ptr := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWloadidx ptr (SLLconst [2] idx) mem) // result: (MOVWloadidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWloadidx (SLLconst [2] idx) ptr mem) // result: (MOVWloadidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVWloadidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _)) // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWloadidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWloadidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (MOVWload [int32(c)<<2] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWload) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg2(ptr, mem) return true } // match: (MOVWloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) // result: (MOVDconst [0]) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWstorezeroidx4 { break } idx2 := v_2.Args[1] ptr2 := v_2.Args[0] if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64MOVWreg(v *Value) bool { v_0 := v.Args[0] // match: (MOVWreg x:(MOVBload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHUload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWload _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHUloadidx2 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUloadidx2 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWloadidx4 _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWloadidx4 { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVBUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVHreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg x:(MOVWreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWreg (MOVDconst [c])) // result: (MOVDconst [int64(int32(c))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c))) return true } // match: (MOVWreg (ANDconst x [c])) // cond: uint64(c) & uint64(0xffffffff80000000) == 0 // result: (ANDconst x [c]) for { t := v.Type if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(uint64(c)&uint64(0xffffffff80000000) == 0) { break } v.reset(OpARM64ANDconst) v.Type = t v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (MOVWreg (SLLconst [lc] x)) // cond: lc < 32 // result: (SBFIZ [armBFAuxInt(lc, 32-lc)] x) for { if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < 32) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc, 32-lc)) v.AddArg(x) return true } // match: (MOVWreg (SBFX [bfc] x)) // cond: bfc.getARM64BFwidth() <= 32 // result: (SBFX [bfc] x) for { if v_0.Op != OpARM64SBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(bfc.getARM64BFwidth() <= 32) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64MOVWstore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWstore [off] {sym} ptr (FMOVSfpgp val) mem) // result: (FMOVSstore [off] {sym} ptr val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64FMOVSfpgp { break } val := v_1.Args[0] mem := v_2 v.reset(OpARM64FMOVSstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstore [off1+int32(off2)] {sym} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} (ADD ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVWstoreidx ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) // cond: off == 0 && sym == nil // result: (MOVWstoreidx4 ptr idx val mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] val := v_1 mem := v_2 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val := v_1 mem := v_2 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVDconst [0]) mem) // result: (MOVWstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } mem := v_2 v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } // match: (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) // result: (MOVWstore [off] {sym} ptr x mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVWUreg { break } x := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg3(ptr, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstoreidx(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVWstore [int32(c)] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstoreidx (MOVDconst [c]) idx val mem) // cond: is32Bit(c) // result: (MOVWstore [int32(c)] idx val mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 val := v_2 mem := v_3 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg3(idx, val, mem) return true } // match: (MOVWstoreidx ptr (SLLconst [2] idx) val mem) // result: (MOVWstoreidx4 ptr idx val mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] val := v_2 mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstoreidx (SLLconst [2] idx) ptr val mem) // result: (MOVWstoreidx4 ptr idx val mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 val := v_2 mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, val, mem) return true } // match: (MOVWstoreidx ptr idx (MOVDconst [0]) mem) // result: (MOVWstorezeroidx ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVWstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstoreidx ptr idx (MOVWreg x) mem) // result: (MOVWstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVWstoreidx ptr idx (MOVWUreg x) mem) // result: (MOVWstoreidx ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstoreidx4(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreidx4 ptr (MOVDconst [c]) val mem) // cond: is32Bit(c<<2) // result: (MOVWstore [int32(c)<<2] ptr val mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) val := v_2 mem := v_3 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(int32(c) << 2) v.AddArg3(ptr, val, mem) return true } // match: (MOVWstoreidx4 ptr idx (MOVDconst [0]) mem) // result: (MOVWstorezeroidx4 ptr idx mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstoreidx4 ptr idx (MOVWreg x) mem) // result: (MOVWstoreidx4 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, x, mem) return true } // match: (MOVWstoreidx4 ptr idx (MOVWUreg x) mem) // result: (MOVWstoreidx4 ptr idx x mem) for { ptr := v_0 idx := v_1 if v_2.Op != OpARM64MOVWUreg { break } x := v_2.Args[0] mem := v_3 v.reset(OpARM64MOVWstoreidx4) v.AddArg4(ptr, idx, x, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstorezero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstorezero [off1+int32(off2)] {sym} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] mem := v_1 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } // match: (MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] mem := v_1 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg2(ptr, mem) return true } // match: (MOVWstorezero [off] {sym} (ADD ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWstorezeroidx ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADD { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstorezeroidx) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstorezero [off] {sym} (ADDshiftLL [2] ptr idx) mem) // cond: off == 0 && sym == nil // result: (MOVWstorezeroidx4 ptr idx mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[1] ptr := v_0.Args[0] mem := v_1 if !(off == 0 && sym == nil) { break } v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstorezeroidx(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstorezeroidx ptr (MOVDconst [c]) mem) // cond: is32Bit(c) // result: (MOVWstorezero [int32(c)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(ptr, mem) return true } // match: (MOVWstorezeroidx (MOVDconst [c]) idx mem) // cond: is32Bit(c) // result: (MOVWstorezero [int32(c)] idx mem) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) idx := v_1 mem := v_2 if !(is32Bit(c)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg2(idx, mem) return true } // match: (MOVWstorezeroidx ptr (SLLconst [2] idx) mem) // result: (MOVWstorezeroidx4 ptr idx mem) for { ptr := v_0 if v_1.Op != OpARM64SLLconst || auxIntToInt64(v_1.AuxInt) != 2 { break } idx := v_1.Args[0] mem := v_2 v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } // match: (MOVWstorezeroidx (SLLconst [2] idx) ptr mem) // result: (MOVWstorezeroidx4 ptr idx mem) for { if v_0.Op != OpARM64SLLconst || auxIntToInt64(v_0.AuxInt) != 2 { break } idx := v_0.Args[0] ptr := v_1 mem := v_2 v.reset(OpARM64MOVWstorezeroidx4) v.AddArg3(ptr, idx, mem) return true } return false } func rewriteValueARM64_OpARM64MOVWstorezeroidx4(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstorezeroidx4 ptr (MOVDconst [c]) mem) // cond: is32Bit(c<<2) // result: (MOVWstorezero [int32(c<<2)] ptr mem) for { ptr := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) mem := v_2 if !(is32Bit(c << 2)) { break } v.reset(OpARM64MOVWstorezero) v.AuxInt = int32ToAuxInt(int32(c << 2)) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64MSUB(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MSUB a x (MOVDconst [-1])) // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != -1 { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUB a _ (MOVDconst [0])) // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MSUB a x (MOVDconst [1])) // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 1 { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUB a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUB a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [-1]) x) // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { break } x := v_2 v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUB a (MOVDconst [0]) _) // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } v.copyOf(a) return true } // match: (MSUB a (MOVDconst [1]) x) // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } x := v_2 v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && c>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && c >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && c>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && c >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUB (MOVDconst [c]) x y) // result: (ADDconst [c] (MNEG x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MNEG, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MSUB a (MOVDconst [c]) (MOVDconst [d])) // result: (SUBconst [c*d] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(c * d) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MSUBW(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MSUBW a x (MOVDconst [c])) // cond: int32(c)==-1 // result: (ADD a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == -1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUBW a _ (MOVDconst [c])) // cond: int32(c)==0 // result: a for { a := v_0 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: int32(c)==1 // result: (SUB a x) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 x := v_1 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: int32(c)==-1 // result: (ADD a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == -1) { break } v.reset(OpARM64ADD) v.AddArg2(a, x) return true } // match: (MSUBW a (MOVDconst [c]) _) // cond: int32(c)==0 // result: a for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { break } v.copyOf(a) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: int32(c)==1 // result: (SUB a x) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(int32(c) == 1) { break } v.reset(OpARM64SUB) v.AddArg2(a, x) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c) // result: (SUBshiftLL a x [log64(c)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg2(a, x) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c-1) && int32(c)>=3 // result: (SUB a (ADDshiftLL x x [log64(c-1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { break } v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c - 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: isPowerOfTwo64(c+1) && int32(c)>=7 // result: (ADD a (SUBshiftLL x x [log64(c+1)])) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { break } v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(log64(c + 1)) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [2]) [log64(c/3)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [2]) [log64(c/5)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (ADDshiftLL a (SUBshiftLL x x [3]) [log64(c/7)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { break } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW a (MOVDconst [c]) x) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (SUBshiftLL a (ADDshiftLL x x [3]) [log64(c/9)]) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) x := v_2 if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg2(a, v0) return true } // match: (MSUBW (MOVDconst [c]) x y) // result: (ADDconst [c] (MNEGW x y)) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 y := v_2 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64MNEGW, x.Type) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (MSUBW a (MOVDconst [c]) (MOVDconst [d])) // result: (SUBconst [int64(int32(c)*int32(d))] a) for { a := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if v_2.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_2.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(int64(int32(c) * int32(d))) v.AddArg(a) return true } return false } func rewriteValueARM64_OpARM64MUL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MUL (NEG x) y) // result: (MNEG x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64NEG { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64MNEG) v.AddArg2(x, y) return true } break } // match: (MUL x (MOVDconst [-1])) // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != -1 { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MUL _ (MOVDconst [0])) // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MUL x (MOVDconst [1])) // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { continue } v.copyOf(x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SLLconst [log64(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && c >= 3 // result: (ADDshiftLL x x [log64(c-1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && c >= 3) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c - 1)) v.AddArg2(x, x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && c >= 7 // result: (ADDshiftLL (NEG x) x [log64(c+1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && c >= 7) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c + 1)) v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v0.AddArg(x) v.AddArg2(v0, x) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) // result: (SLLconst [log64(c/3)] (ADDshiftLL x x [1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) // result: (SLLconst [log64(c/5)] (ADDshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) // result: (SLLconst [log64(c/7)] (ADDshiftLL (NEG x) x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MUL x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) // result: (SLLconst [log64(c/9)] (ADDshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MUL (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [c*d]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c * d) return true } break } return false } func rewriteValueARM64_OpARM64MULW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (MULW (NEG x) y) // result: (MNEGW x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64NEG { continue } x := v_0.Args[0] y := v_1 v.reset(OpARM64MNEGW) v.AddArg2(x, y) return true } break } // match: (MULW x (MOVDconst [c])) // cond: int32(c)==-1 // result: (NEG x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == -1) { continue } v.reset(OpARM64NEG) v.AddArg(x) return true } break } // match: (MULW _ (MOVDconst [c])) // cond: int32(c)==0 // result: (MOVDconst [0]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 0) { continue } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: int32(c)==1 // result: x for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(int32(c) == 1) { continue } v.copyOf(x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SLLconst [log64(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: isPowerOfTwo64(c-1) && int32(c) >= 3 // result: (ADDshiftLL x x [log64(c-1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c-1) && int32(c) >= 3) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c - 1)) v.AddArg2(x, x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: isPowerOfTwo64(c+1) && int32(c) >= 7 // result: (ADDshiftLL (NEG x) x [log64(c+1)]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c+1) && int32(c) >= 7) { continue } v.reset(OpARM64ADDshiftLL) v.AuxInt = int64ToAuxInt(log64(c + 1)) v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v0.AddArg(x) v.AddArg2(v0, x) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) // result: (SLLconst [log64(c/3)] (ADDshiftLL x x [1])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 3)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(1) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) // result: (SLLconst [log64(c/5)] (ADDshiftLL x x [2])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 5)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(2) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) // result: (SLLconst [log64(c/7)] (ADDshiftLL (NEG x) x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 7)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) v1.AddArg(x) v0.AddArg2(v1, x) v.AddArg(v0) return true } break } // match: (MULW x (MOVDconst [c])) // cond: c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) // result: (SLLconst [log64(c/9)] (ADDshiftLL x x [3])) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) if !(c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c)) { continue } v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(log64(c / 9)) v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) v0.AuxInt = int64ToAuxInt(3) v0.AddArg2(x, x) v.AddArg(v0) return true } break } // match: (MULW (MOVDconst [c]) (MOVDconst [d])) // result: (MOVDconst [int64(int32(c)*int32(d))]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { continue } d := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(int32(c) * int32(d))) return true } break } return false } func rewriteValueARM64_OpARM64MVN(v *Value) bool { v_0 := v.Args[0] // match: (MVN (XOR x y)) // result: (EON x y) for { if v_0.Op != OpARM64XOR { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64EON) v.AddArg2(x, y) return true } // match: (MVN (MOVDconst [c])) // result: (MOVDconst [^c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^c) return true } // match: (MVN x:(SLLconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftLL [c] y) for { x := v_0 if x.Op != OpARM64SLLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (MVN x:(SRLconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftRL [c] y) for { x := v_0 if x.Op != OpARM64SRLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (MVN x:(SRAconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftRA [c] y) for { x := v_0 if x.Op != OpARM64SRAconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (MVN x:(RORconst [c] y)) // cond: clobberIfDead(x) // result: (MVNshiftRO [c] y) for { x := v_0 if x.Op != OpARM64RORconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64MVNshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64MVNshiftLL(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftLL (MOVDconst [c]) [d]) // result: (MOVDconst [^int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64MVNshiftRL(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftRL (MOVDconst [c]) [d]) // result: (MOVDconst [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64MVNshiftRO(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftRO (MOVDconst [c]) [d]) // result: (MOVDconst [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) return true } return false } func rewriteValueARM64_OpARM64NEG(v *Value) bool { v_0 := v.Args[0] // match: (NEG (MUL x y)) // result: (MNEG x y) for { if v_0.Op != OpARM64MUL { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MNEG) v.AddArg2(x, y) return true } // match: (NEG (MULW x y)) // result: (MNEGW x y) for { if v_0.Op != OpARM64MULW { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MNEGW) v.AddArg2(x, y) return true } // match: (NEG (NEG x)) // result: x for { if v_0.Op != OpARM64NEG { break } x := v_0.Args[0] v.copyOf(x) return true } // match: (NEG (MOVDconst [c])) // result: (MOVDconst [-c]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-c) return true } // match: (NEG x:(SLLconst [c] y)) // cond: clobberIfDead(x) // result: (NEGshiftLL [c] y) for { x := v_0 if x.Op != OpARM64SLLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64NEGshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (NEG x:(SRLconst [c] y)) // cond: clobberIfDead(x) // result: (NEGshiftRL [c] y) for { x := v_0 if x.Op != OpARM64SRLconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64NEGshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } // match: (NEG x:(SRAconst [c] y)) // cond: clobberIfDead(x) // result: (NEGshiftRA [c] y) for { x := v_0 if x.Op != OpARM64SRAconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(clobberIfDead(x)) { break } v.reset(OpARM64NEGshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg(y) return true } return false } func rewriteValueARM64_OpARM64NEGshiftLL(v *Value) bool { v_0 := v.Args[0] // match: (NEGshiftLL (MOVDconst [c]) [d]) // result: (MOVDconst [-int64(uint64(c)<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-(c >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64NEGshiftRL(v *Value) bool { v_0 := v.Args[0] // match: (NEGshiftRL (MOVDconst [c]) [d]) // result: (MOVDconst [-int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-int64(uint64(c) >> uint64(d))) return true } return false } func rewriteValueARM64_OpARM64NotEqual(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (NotEqual (CMPconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (NotEqual (TST x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (TSTWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(AND x y))) // cond: z.Uses == 1 // result: (NotEqual (TSTW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] x:(ANDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (TSTconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMP x z:(NEG y))) // cond: z.Uses == 1 // result: (NotEqual (CMN x y)) for { if v_0.Op != OpARM64CMP { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPW x z:(NEG y))) // cond: z.Uses == 1 // result: (NotEqual (CMNW x y)) for { if v_0.Op != OpARM64CMPW { break } _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (CMNconst [c] y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] x:(ADDconst [c] y))) // cond: x.Uses == 1 // result: (NotEqual (CMNWconst [int32(c)] y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (NotEqual (CMN x y)) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(ADD x y))) // cond: z.Uses == 1 // result: (NotEqual (CMNW x y)) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } y := z.Args[1] x := z.Args[0] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] z:(MADD a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMN a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (CMPconst [0] z:(MSUB a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMP a (MUL x y))) for { if v_0.Op != OpARM64CMPconst || auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(MADDW a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMNW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (CMPWconst [0] z:(MSUBW a x y))) // cond: z.Uses == 1 // result: (NotEqual (CMPW a (MULW x y))) for { if v_0.Op != OpARM64CMPWconst || auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) v.AddArg(v0) return true } // match: (NotEqual (FlagConstant [fc])) // result: (MOVDconst [b2i(fc.ne())]) for { if v_0.Op != OpARM64FlagConstant { break } fc := auxIntToFlagConstant(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(fc.ne())) return true } // match: (NotEqual (InvertFlags x)) // result: (NotEqual x) for { if v_0.Op != OpARM64InvertFlags { break } x := v_0.Args[0] v.reset(OpARM64NotEqual) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64OR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (OR x (MOVDconst [c])) // result: (ORconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (OR x x) // result: x for { x := v_0 if x != v_1 { break } v.copyOf(x) return true } // match: (OR x (MVN y)) // result: (ORN x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MVN { continue } y := v_1.Args[0] v.reset(OpARM64ORN) v.AddArg2(x, y) return true } break } // match: (OR x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (ORshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64ORshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (OR (UBFIZ [bfc] x) (ANDconst [ac] y)) // cond: ac == ^((1<>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^(c >> uint64(d))) v.AddArg(x) return true } // match: (ORNshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64ORNshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ORNshiftRL x (MOVDconst [c]) [d]) // result: (ORconst x [^int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (ORNshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64ORNshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ORNshiftRO x (MOVDconst [c]) [d]) // result: (ORconst x [^rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(^rotateRight64(c, d)) v.AddArg(x) return true } // match: (ORNshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [-1]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } return false } func rewriteValueARM64_OpARM64ORconst(v *Value) bool { v_0 := v.Args[0] // match: (ORconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (ORconst [-1] _) // result: (MOVDconst [-1]) for { if auxIntToInt64(v.AuxInt) != -1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(-1) return true } // match: (ORconst [c] (MOVDconst [d])) // result: (MOVDconst [c|d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c | d) return true } // match: (ORconst [c] (ORconst [d] x)) // result: (ORconst [c|d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ORconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c | d) v.AddArg(x) return true } // match: (ORconst [c1] (ANDconst [c2] x)) // cond: c2|c1 == ^0 // result: (ORconst [c1] x) for { c1 := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(c2|c1 == ^0) { break } v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c1) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64ORshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (ORshiftLL (MOVDconst [c]) x [d]) // result: (ORconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftLL x (MOVDconst [c]) [d]) // result: (ORconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) // result: (REV16W x) for { if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ORshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff // result: (REV16W x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (ORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) // result: (REV16 x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { break } v.reset(OpARM64REV16) v.AddArg(x) return true } // match: (ORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) // result: (REV16 (ANDconst [0xffffffff] x)) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16) v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) v0.AuxInt = int64ToAuxInt(0xffffffff) v0.AddArg(x) v.AddArg(v0) return true } // match: ( ORshiftLL [c] (SRLconst x [64-c]) x2) // result: (EXTRconst [64-c] x2 x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { break } x := v_0.Args[0] x2 := v_1 v.reset(OpARM64EXTRconst) v.AuxInt = int64ToAuxInt(64 - c) v.AddArg2(x2, x) return true } // match: ( ORshiftLL [c] (UBFX [bfc] x) x2) // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) // result: (EXTRWconst [32-c] x2 x) for { t := v.Type c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] x2 := v_1 if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { break } v.reset(OpARM64EXTRWconst) v.AuxInt = int64ToAuxInt(32 - c) v.AddArg2(x2, x) return true } // match: (ORshiftLL [sc] (UBFX [bfc] x) (SRLconst [sc] y)) // cond: sc == bfc.getARM64BFwidth() // result: (BFXIL [bfc] y x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != sc { break } y := v_1.Args[0] if !(sc == bfc.getARM64BFwidth()) { break } v.reset(OpARM64BFXIL) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg2(y, x) return true } return false } func rewriteValueARM64_OpARM64ORshiftRA(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ORshiftRA (MOVDconst [c]) x [d]) // result: (ORconst [c] (SRAconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftRA x (MOVDconst [c]) [d]) // result: (ORconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (ORshiftRA y:(SRAconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRAconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64ORshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (ORshiftRL (MOVDconst [c]) x [d]) // result: (ORconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftRL x (MOVDconst [c]) [d]) // result: (ORconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (ORshiftRL y:(SRLconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64SRLconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } // match: (ORshiftRL [rc] (ANDconst [ac] x) (SLLconst [lc] y)) // cond: lc > rc && ac == ^((1< rc && ac == ^((1< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (ORshiftRO x (MOVDconst [c]) [d]) // result: (ORconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64ORconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } // match: (ORshiftRO y:(RORconst x [c]) x [c]) // result: y for { c := auxIntToInt64(v.AuxInt) y := v_0 if y.Op != OpARM64RORconst || auxIntToInt64(y.AuxInt) != c { break } x := y.Args[0] if x != v_1 { break } v.copyOf(y) return true } return false } func rewriteValueARM64_OpARM64REV(v *Value) bool { v_0 := v.Args[0] // match: (REV (REV p)) // result: p for { if v_0.Op != OpARM64REV { break } p := v_0.Args[0] v.copyOf(p) return true } return false } func rewriteValueARM64_OpARM64REVW(v *Value) bool { v_0 := v.Args[0] // match: (REVW (REVW p)) // result: p for { if v_0.Op != OpARM64REVW { break } p := v_0.Args[0] v.copyOf(p) return true } return false } func rewriteValueARM64_OpARM64ROR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (ROR x (MOVDconst [c])) // result: (RORconst x [c&63]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64RORconst) v.AuxInt = int64ToAuxInt(c & 63) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64RORW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (RORW x (MOVDconst [c])) // result: (RORWconst x [c&31]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64RORWconst) v.AuxInt = int64ToAuxInt(c & 31) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64SBCSflags(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (SBCSflags x y (Select1 (NEGSflags (NEG (NGCzerocarry bo))))) // result: (SBCSflags x y bo) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64NEGSflags { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64NEG || v_2_0_0.Type != typ.UInt64 { break } v_2_0_0_0 := v_2_0_0.Args[0] if v_2_0_0_0.Op != OpARM64NGCzerocarry || v_2_0_0_0.Type != typ.UInt64 { break } bo := v_2_0_0_0.Args[0] v.reset(OpARM64SBCSflags) v.AddArg3(x, y, bo) return true } // match: (SBCSflags x y (Select1 (NEGSflags (MOVDconst [0])))) // result: (SUBSflags x y) for { x := v_0 y := v_1 if v_2.Op != OpSelect1 || v_2.Type != types.TypeFlags { break } v_2_0 := v_2.Args[0] if v_2_0.Op != OpARM64NEGSflags { break } v_2_0_0 := v_2_0.Args[0] if v_2_0_0.Op != OpARM64MOVDconst || auxIntToInt64(v_2_0_0.AuxInt) != 0 { break } v.reset(OpARM64SUBSflags) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64SLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SLL x (MOVDconst [c])) // result: (SLLconst x [c&63]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SLLconst) v.AuxInt = int64ToAuxInt(c & 63) v.AddArg(x) return true } // match: (SLL x (ANDconst [63] y)) // result: (SLL x y) for { x := v_0 if v_1.Op != OpARM64ANDconst || auxIntToInt64(v_1.AuxInt) != 63 { break } y := v_1.Args[0] v.reset(OpARM64SLL) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64SLLconst(v *Value) bool { v_0 := v.Args[0] // match: (SLLconst [c] (MOVDconst [d])) // result: (MOVDconst [d<>uint64(c)]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(d >> uint64(c)) return true } // match: (SRAconst [rc] (SLLconst [lc] x)) // cond: lc > rc // result: (SBFIZ [armBFAuxInt(lc-rc, 64-lc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc > rc) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc-rc, 64-lc)) v.AddArg(x) return true } // match: (SRAconst [rc] (SLLconst [lc] x)) // cond: lc <= rc // result: (SBFX [armBFAuxInt(rc-lc, 64-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc <= rc) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc-lc, 64-rc)) v.AddArg(x) return true } // match: (SRAconst [rc] (MOVWreg x)) // cond: rc < 32 // result: (SBFX [armBFAuxInt(rc, 32-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWreg { break } x := v_0.Args[0] if !(rc < 32) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 32-rc)) v.AddArg(x) return true } // match: (SRAconst [rc] (MOVHreg x)) // cond: rc < 16 // result: (SBFX [armBFAuxInt(rc, 16-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHreg { break } x := v_0.Args[0] if !(rc < 16) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 16-rc)) v.AddArg(x) return true } // match: (SRAconst [rc] (MOVBreg x)) // cond: rc < 8 // result: (SBFX [armBFAuxInt(rc, 8-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBreg { break } x := v_0.Args[0] if !(rc < 8) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8-rc)) v.AddArg(x) return true } // match: (SRAconst [sc] (SBFIZ [bfc] x)) // cond: sc < bfc.getARM64BFlsb() // result: (SBFIZ [armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SBFIZ { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc < bfc.getARM64BFlsb()) { break } v.reset(OpARM64SBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())) v.AddArg(x) return true } // match: (SRAconst [sc] (SBFIZ [bfc] x)) // cond: sc >= bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() // result: (SBFX [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SBFIZ { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc >= bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth()) { break } v.reset(OpARM64SBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64SRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SRL x (MOVDconst [c])) // result: (SRLconst x [c&63]) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(c & 63) v.AddArg(x) return true } // match: (SRL x (ANDconst [63] y)) // result: (SRL x y) for { x := v_0 if v_1.Op != OpARM64ANDconst || auxIntToInt64(v_1.AuxInt) != 63 { break } y := v_1.Args[0] v.reset(OpARM64SRL) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpARM64SRLconst(v *Value) bool { v_0 := v.Args[0] // match: (SRLconst [c] (MOVDconst [d])) // result: (MOVDconst [int64(uint64(d)>>uint64(c))]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint64(d) >> uint64(c))) return true } // match: (SRLconst [c] (SLLconst [c] x)) // cond: 0 < c && c < 64 // result: (ANDconst [1<= 32 // result: (MOVDconst [0]) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg { break } if !(rc >= 32) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SRLconst [rc] (MOVHUreg x)) // cond: rc >= 16 // result: (MOVDconst [0]) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg { break } if !(rc >= 16) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SRLconst [rc] (MOVBUreg x)) // cond: rc >= 8 // result: (MOVDconst [0]) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg { break } if !(rc >= 8) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SRLconst [rc] (SLLconst [lc] x)) // cond: lc > rc // result: (UBFIZ [armBFAuxInt(lc-rc, 64-lc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc > rc) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(lc-rc, 64-lc)) v.AddArg(x) return true } // match: (SRLconst [rc] (SLLconst [lc] x)) // cond: lc < rc // result: (UBFX [armBFAuxInt(rc-lc, 64-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } lc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(lc < rc) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc-lc, 64-rc)) v.AddArg(x) return true } // match: (SRLconst [rc] (MOVWUreg x)) // cond: rc < 32 // result: (UBFX [armBFAuxInt(rc, 32-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVWUreg { break } x := v_0.Args[0] if !(rc < 32) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 32-rc)) v.AddArg(x) return true } // match: (SRLconst [rc] (MOVHUreg x)) // cond: rc < 16 // result: (UBFX [armBFAuxInt(rc, 16-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVHUreg { break } x := v_0.Args[0] if !(rc < 16) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 16-rc)) v.AddArg(x) return true } // match: (SRLconst [rc] (MOVBUreg x)) // cond: rc < 8 // result: (UBFX [armBFAuxInt(rc, 8-rc)] x) for { rc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVBUreg { break } x := v_0.Args[0] if !(rc < 8) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(rc, 8-rc)) v.AddArg(x) return true } // match: (SRLconst [sc] (ANDconst [ac] x)) // cond: isARM64BFMask(sc, ac, sc) // result: (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } ac := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(sc, ac, sc)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc, arm64BFWidth(ac, sc))) v.AddArg(x) return true } // match: (SRLconst [sc] (UBFX [bfc] x)) // cond: sc < bfc.getARM64BFwidth() // result: (UBFX [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc < bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } // match: (SRLconst [sc] (UBFIZ [bfc] x)) // cond: sc == bfc.getARM64BFlsb() // result: (ANDconst [1< bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() // result: (UBFX [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFIZ { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc > bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64STP(v *Value) bool { v_3 := v.Args[3] v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (STP [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (STP [off1+int32(off2)] {sym} ptr val1 val2 mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) if v_0.Op != OpARM64ADDconst { break } off2 := auxIntToInt64(v_0.AuxInt) ptr := v_0.Args[0] val1 := v_1 val2 := v_2 mem := v_3 if !(is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(off1 + int32(off2)) v.Aux = symToAux(sym) v.AddArg4(ptr, val1, val2, mem) return true } // match: (STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem) // cond: canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (STP [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem) for { off1 := auxIntToInt32(v.AuxInt) sym1 := auxToSym(v.Aux) if v_0.Op != OpARM64MOVDaddr { break } off2 := auxIntToInt32(v_0.AuxInt) sym2 := auxToSym(v_0.Aux) ptr := v_0.Args[0] val1 := v_1 val2 := v_2 mem := v_3 if !(canMergeSym(sym1, sym2) && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)) { break } v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(off1 + off2) v.Aux = symToAux(mergeSym(sym1, sym2)) v.AddArg4(ptr, val1, val2, mem) return true } // match: (STP [off] {sym} ptr (MOVDconst [0]) (MOVDconst [0]) mem) // result: (MOVQstorezero [off] {sym} ptr mem) for { off := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) ptr := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 || v_2.Op != OpARM64MOVDconst || auxIntToInt64(v_2.AuxInt) != 0 { break } mem := v_3 v.reset(OpARM64MOVQstorezero) v.AuxInt = int32ToAuxInt(off) v.Aux = symToAux(sym) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpARM64SUB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (SUB x (MOVDconst [c])) // result: (SUBconst [c] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } // match: (SUB a l:(MUL x y)) // cond: l.Uses==1 && clobber(l) // result: (MSUB a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MUL { break } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MSUB) v.AddArg3(a, x, y) return true } // match: (SUB a l:(MNEG x y)) // cond: l.Uses==1 && clobber(l) // result: (MADD a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MNEG { break } y := l.Args[1] x := l.Args[0] if !(l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MADD) v.AddArg3(a, x, y) return true } // match: (SUB a l:(MULW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MSUBW a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MULW { break } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MSUBW) v.AddArg3(a, x, y) return true } // match: (SUB a l:(MNEGW x y)) // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) // result: (MADDW a x y) for { a := v_0 l := v_1 if l.Op != OpARM64MNEGW { break } y := l.Args[1] x := l.Args[0] if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { break } v.reset(OpARM64MADDW) v.AddArg3(a, x, y) return true } // match: (SUB x x) // result: (MOVDconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (SUB x (SUB y z)) // result: (SUB (ADD x z) y) for { x := v_0 if v_1.Op != OpARM64SUB { break } z := v_1.Args[1] y := v_1.Args[0] v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADD, v.Type) v0.AddArg2(x, z) v.AddArg2(v0, y) return true } // match: (SUB (SUB x y) z) // result: (SUB x (ADD y z)) for { if v_0.Op != OpARM64SUB { break } y := v_0.Args[1] x := v_0.Args[0] z := v_1 v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64ADD, y.Type) v0.AddArg2(y, z) v.AddArg2(x, v0) return true } // match: (SUB x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (SUBshiftLL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64SUBshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (SUB x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (SUBshiftRL x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64SUBshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } // match: (SUB x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (SUBshiftRA x0 y [c]) for { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { break } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { break } v.reset(OpARM64SUBshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } return false } func rewriteValueARM64_OpARM64SUBconst(v *Value) bool { v_0 := v.Args[0] // match: (SUBconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (SUBconst [c] (MOVDconst [d])) // result: (MOVDconst [d-c]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(d - c) return true } // match: (SUBconst [c] (SUBconst [d] x)) // result: (ADDconst [-c-d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SUBconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(-c - d) v.AddArg(x) return true } // match: (SUBconst [c] (ADDconst [d] x)) // result: (ADDconst [-c+d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64ADDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(-c + d) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64SUBshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBshiftLL x (MOVDconst [c]) [d]) // result: (SUBconst x [int64(uint64(c)<>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (SUBshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64SUBshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBshiftRL x (MOVDconst [c]) [d]) // result: (SUBconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64SUBconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (SUBshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64TST(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (TST x (MOVDconst [c])) // result: (TSTconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (TST x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (TST x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (TST x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (TST x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (TSTshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64TSTshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64TSTW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (TSTW x (MOVDconst [c])) // result: (TSTWconst [int32(c)] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTWconst) v.AuxInt = int32ToAuxInt(int32(c)) v.AddArg(x) return true } break } return false } func rewriteValueARM64_OpARM64TSTWconst(v *Value) bool { v_0 := v.Args[0] // match: (TSTWconst (MOVDconst [x]) [y]) // result: (FlagConstant [logicFlags32(int32(x)&y)]) for { y := auxIntToInt32(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(logicFlags32(int32(x) & y)) return true } return false } func rewriteValueARM64_OpARM64TSTconst(v *Value) bool { v_0 := v.Args[0] // match: (TSTconst (MOVDconst [x]) [y]) // result: (FlagConstant [logicFlags64(x&y)]) for { y := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } x := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64FlagConstant) v.AuxInt = flagConstantToAuxInt(logicFlags64(x & y)) return true } return false } func rewriteValueARM64_OpARM64TSTshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TSTshiftLL (MOVDconst [c]) x [d]) // result: (TSTconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftLL x (MOVDconst [c]) [d]) // result: (TSTconst x [int64(uint64(c)< x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftRA x (MOVDconst [c]) [d]) // result: (TSTconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64TSTshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TSTshiftRL (MOVDconst [c]) x [d]) // result: (TSTconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftRL x (MOVDconst [c]) [d]) // result: (TSTconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64TSTshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (TSTshiftRO (MOVDconst [c]) x [d]) // result: (TSTconst [c] (RORconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (TSTshiftRO x (MOVDconst [c]) [d]) // result: (TSTconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64TSTconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64UBFIZ(v *Value) bool { v_0 := v.Args[0] // match: (UBFIZ [bfc] (SLLconst [sc] x)) // cond: sc < bfc.getARM64BFwidth() // result: (UBFIZ [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(sc < bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64UBFX(v *Value) bool { v_0 := v.Args[0] // match: (UBFX [bfc] (ANDconst [c] x)) // cond: isARM64BFMask(0, c, 0) && bfc.getARM64BFlsb() + bfc.getARM64BFwidth() <= arm64BFWidth(c, 0) // result: (UBFX [bfc] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64ANDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(isARM64BFMask(0, c, 0) && bfc.getARM64BFlsb()+bfc.getARM64BFwidth() <= arm64BFWidth(c, 0)) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg(x) return true } // match: (UBFX [bfc] (SRLconst [sc] x)) // cond: sc+bfc.getARM64BFwidth()+bfc.getARM64BFlsb() < 64 // result: (UBFX [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth())] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64SRLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(sc+bfc.getARM64BFwidth()+bfc.getARM64BFlsb() < 64) { break } v.reset(OpARM64UBFX) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth())) v.AddArg(x) return true } // match: (UBFX [bfc] (SLLconst [sc] x)) // cond: sc == bfc.getARM64BFlsb() // result: (ANDconst [1< bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() // result: (UBFIZ [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) for { bfc := auxIntToArm64BitField(v.AuxInt) if v_0.Op != OpARM64SLLconst { break } sc := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(sc > bfc.getARM64BFlsb() && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth()) { break } v.reset(OpARM64UBFIZ) v.AuxInt = arm64BitFieldToAuxInt(armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64UDIV(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (UDIV x (MOVDconst [1])) // result: x for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.copyOf(x) return true } // match: (UDIV x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (SRLconst [log64(c)] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } // match: (UDIV (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint64(c)/uint64(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) / uint64(d))) return true } return false } func rewriteValueARM64_OpARM64UDIVW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (UDIVW x (MOVDconst [c])) // cond: uint32(c)==1 // result: x for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(uint32(c) == 1) { break } v.copyOf(x) return true } // match: (UDIVW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) && is32Bit(c) // result: (SRLconst [log64(c)] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c) && is32Bit(c)) { break } v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(log64(c)) v.AddArg(x) return true } // match: (UDIVW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint32(c)/uint32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint32(c) / uint32(d))) return true } return false } func rewriteValueARM64_OpARM64UMOD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (UMOD x y) // result: (MSUB x y (UDIV x y)) for { if v.Type != typ.UInt64 { break } x := v_0 y := v_1 v.reset(OpARM64MSUB) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64UDIV, typ.UInt64) v0.AddArg2(x, y) v.AddArg3(x, y, v0) return true } // match: (UMOD _ (MOVDconst [1])) // result: (MOVDconst [0]) for { if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (UMOD x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (ANDconst [c-1] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c)) { break } v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c - 1) v.AddArg(x) return true } // match: (UMOD (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint64(c)%uint64(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) % uint64(d))) return true } return false } func rewriteValueARM64_OpARM64UMODW(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (UMODW x y) // result: (MSUBW x y (UDIVW x y)) for { if v.Type != typ.UInt32 { break } x := v_0 y := v_1 v.reset(OpARM64MSUBW) v.Type = typ.UInt32 v0 := b.NewValue0(v.Pos, OpARM64UDIVW, typ.UInt32) v0.AddArg2(x, y) v.AddArg3(x, y, v0) return true } // match: (UMODW _ (MOVDconst [c])) // cond: uint32(c)==1 // result: (MOVDconst [0]) for { if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(uint32(c) == 1) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (UMODW x (MOVDconst [c])) // cond: isPowerOfTwo64(c) && is32Bit(c) // result: (ANDconst [c-1] x) for { x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) if !(isPowerOfTwo64(c) && is32Bit(c)) { break } v.reset(OpARM64ANDconst) v.AuxInt = int64ToAuxInt(c - 1) v.AddArg(x) return true } // match: (UMODW (MOVDconst [c]) (MOVDconst [d])) // cond: d != 0 // result: (MOVDconst [int64(uint32(c)%uint32(d))]) for { if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) if v_1.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_1.AuxInt) if !(d != 0) { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(uint32(c) % uint32(d))) return true } return false } func rewriteValueARM64_OpARM64XOR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (XOR x (MOVDconst [c])) // result: (XORconst [c] x) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MOVDconst { continue } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v.AddArg(x) return true } break } // match: (XOR x x) // result: (MOVDconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (XOR x (MVN y)) // result: (EON x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpARM64MVN { continue } y := v_1.Args[0] v.reset(OpARM64EON) v.AddArg2(x, y) return true } break } // match: (XOR x0 x1:(SLLconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftLL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SLLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftLL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (XOR x0 x1:(SRLconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftRL x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRLconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftRL) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (XOR x0 x1:(SRAconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftRA x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64SRAconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftRA) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } // match: (XOR x0 x1:(RORconst [c] y)) // cond: clobberIfDead(x1) // result: (XORshiftRO x0 y [c]) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x0 := v_0 x1 := v_1 if x1.Op != OpARM64RORconst { continue } c := auxIntToInt64(x1.AuxInt) y := x1.Args[0] if !(clobberIfDead(x1)) { continue } v.reset(OpARM64XORshiftRO) v.AuxInt = int64ToAuxInt(c) v.AddArg2(x0, y) return true } break } return false } func rewriteValueARM64_OpARM64XORconst(v *Value) bool { v_0 := v.Args[0] // match: (XORconst [0] x) // result: x for { if auxIntToInt64(v.AuxInt) != 0 { break } x := v_0 v.copyOf(x) return true } // match: (XORconst [-1] x) // result: (MVN x) for { if auxIntToInt64(v.AuxInt) != -1 { break } x := v_0 v.reset(OpARM64MVN) v.AddArg(x) return true } // match: (XORconst [c] (MOVDconst [d])) // result: (MOVDconst [c^d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c ^ d) return true } // match: (XORconst [c] (XORconst [d] x)) // result: (XORconst [c^d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64XORconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c ^ d) v.AddArg(x) return true } return false } func rewriteValueARM64_OpARM64XORshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (XORshiftLL (MOVDconst [c]) x [d]) // result: (XORconst [c] (SLLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftLL x (MOVDconst [c]) [d]) // result: (XORconst x [int64(uint64(c)< [8] (UBFX [armBFAuxInt(8, 8)] x) x) // result: (REV16W x) for { if v.Type != typ.UInt16 || auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || v_0.Type != typ.UInt16 || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 8) { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (XORshiftLL [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff // result: (REV16W x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64UBFX || auxIntToArm64BitField(v_0.AuxInt) != armBFAuxInt(8, 24) { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16W) v.AddArg(x) return true } // match: (XORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) // result: (REV16 x) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) { break } v.reset(OpARM64REV16) v.AddArg(x) return true } // match: (XORshiftLL [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) // cond: (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) // result: (REV16 (ANDconst [0xffffffff] x)) for { if auxIntToInt64(v.AuxInt) != 8 || v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 8 { break } v_0_0 := v_0.Args[0] if v_0_0.Op != OpARM64ANDconst { break } c1 := auxIntToInt64(v_0_0.AuxInt) x := v_0_0.Args[0] if v_1.Op != OpARM64ANDconst { break } c2 := auxIntToInt64(v_1.AuxInt) if x != v_1.Args[0] || !(uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) { break } v.reset(OpARM64REV16) v0 := b.NewValue0(v.Pos, OpARM64ANDconst, x.Type) v0.AuxInt = int64ToAuxInt(0xffffffff) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftLL [c] (SRLconst x [64-c]) x2) // result: (EXTRconst [64-c] x2 x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != 64-c { break } x := v_0.Args[0] x2 := v_1 v.reset(OpARM64EXTRconst) v.AuxInt = int64ToAuxInt(64 - c) v.AddArg2(x2, x) return true } // match: (XORshiftLL [c] (UBFX [bfc] x) x2) // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) // result: (EXTRWconst [32-c] x2 x) for { t := v.Type c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFX { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] x2 := v_1 if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { break } v.reset(OpARM64EXTRWconst) v.AuxInt = int64ToAuxInt(32 - c) v.AddArg2(x2, x) return true } return false } func rewriteValueARM64_OpARM64XORshiftRA(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (XORshiftRA (MOVDconst [c]) x [d]) // result: (XORconst [c] (SRAconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftRA x (MOVDconst [c]) [d]) // result: (XORconst x [c>>uint64(d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c >> uint64(d)) v.AddArg(x) return true } // match: (XORshiftRA (SRAconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRAconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64XORshiftRL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (XORshiftRL (MOVDconst [c]) x [d]) // result: (XORconst [c] (SRLconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftRL x (MOVDconst [c]) [d]) // result: (XORconst x [int64(uint64(c)>>uint64(d))]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(int64(uint64(c) >> uint64(d))) v.AddArg(x) return true } // match: (XORshiftRL (SRLconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64SRLconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpARM64XORshiftRO(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (XORshiftRO (MOVDconst [c]) x [d]) // result: (XORconst [c] (RORconst x [d])) for { d := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_0.AuxInt) x := v_1 v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(c) v0 := b.NewValue0(v.Pos, OpARM64RORconst, x.Type) v0.AuxInt = int64ToAuxInt(d) v0.AddArg(x) v.AddArg(v0) return true } // match: (XORshiftRO x (MOVDconst [c]) [d]) // result: (XORconst x [rotateRight64(c, d)]) for { d := auxIntToInt64(v.AuxInt) x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpARM64XORconst) v.AuxInt = int64ToAuxInt(rotateRight64(c, d)) v.AddArg(x) return true } // match: (XORshiftRO (RORconst x [c]) x [c]) // result: (MOVDconst [0]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64RORconst || auxIntToInt64(v_0.AuxInt) != c { break } x := v_0.Args[0] if x != v_1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } return false } func rewriteValueARM64_OpAddr(v *Value) bool { v_0 := v.Args[0] // match: (Addr {sym} base) // result: (MOVDaddr {sym} base) for { sym := auxToSym(v.Aux) base := v_0 v.reset(OpARM64MOVDaddr) v.Aux = symToAux(sym) v.AddArg(base) return true } } func rewriteValueARM64_OpAtomicAnd32(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd32 ptr val mem) // result: (Select1 (LoweredAtomicAnd32 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd32, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicAnd32Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd32Variant ptr val mem) // result: (Select1 (LoweredAtomicAnd32Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd32Variant, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicAnd8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd8 ptr val mem) // result: (Select1 (LoweredAtomicAnd8 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd8, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicAnd8Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicAnd8Variant ptr val mem) // result: (Select1 (LoweredAtomicAnd8Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicAnd8Variant, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr32(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr32 ptr val mem) // result: (Select1 (LoweredAtomicOr32 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr32, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr32Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr32Variant ptr val mem) // result: (Select1 (LoweredAtomicOr32Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr32Variant, types.NewTuple(typ.UInt32, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr8(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr8 ptr val mem) // result: (Select1 (LoweredAtomicOr8 ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr8, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAtomicOr8Variant(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (AtomicOr8Variant ptr val mem) // result: (Select1 (LoweredAtomicOr8Variant ptr val mem)) for { ptr := v_0 val := v_1 mem := v_2 v.reset(OpSelect1) v0 := b.NewValue0(v.Pos, OpARM64LoweredAtomicOr8Variant, types.NewTuple(typ.UInt8, types.TypeMem)) v0.AddArg3(ptr, val, mem) v.AddArg(v0) return true } } func rewriteValueARM64_OpAvg64u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Avg64u x y) // result: (ADD (SRLconst (SUB x y) [1]) y) for { t := v.Type x := v_0 y := v_1 v.reset(OpARM64ADD) v0 := b.NewValue0(v.Pos, OpARM64SRLconst, t) v0.AuxInt = int64ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpARM64SUB, t) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg2(v0, y) return true } } func rewriteValueARM64_OpBitLen32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen32 x) // result: (SUB (MOVDconst [32]) (CLZW x)) for { x := v_0 v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(32) v1 := b.NewValue0(v.Pos, OpARM64CLZW, typ.Int) v1.AddArg(x) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpBitLen64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitLen64 x) // result: (SUB (MOVDconst [64]) (CLZ x)) for { x := v_0 v.reset(OpARM64SUB) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(64) v1 := b.NewValue0(v.Pos, OpARM64CLZ, typ.Int) v1.AddArg(x) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpBitRev16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitRev16 x) // result: (SRLconst [48] (RBIT x)) for { x := v_0 v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(48) v0 := b.NewValue0(v.Pos, OpARM64RBIT, typ.UInt64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpBitRev8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (BitRev8 x) // result: (SRLconst [56] (RBIT x)) for { x := v_0 v.reset(OpARM64SRLconst) v.AuxInt = int64ToAuxInt(56) v0 := b.NewValue0(v.Pos, OpARM64RBIT, typ.UInt64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (CondSelect x y boolval) // cond: flagArg(boolval) != nil // result: (CSEL [boolval.Op] x y flagArg(boolval)) for { x := v_0 y := v_1 boolval := v_2 if !(flagArg(boolval) != nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(boolval.Op) v.AddArg3(x, y, flagArg(boolval)) return true } // match: (CondSelect x y boolval) // cond: flagArg(boolval) == nil // result: (CSEL [OpARM64NotEqual] x y (TSTWconst [1] boolval)) for { x := v_0 y := v_1 boolval := v_2 if !(flagArg(boolval) == nil) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(1) v0.AddArg(boolval) v.AddArg3(x, y, v0) return true } return false } func rewriteValueARM64_OpConst16(v *Value) bool { // match: (Const16 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt16(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConst32(v *Value) bool { // match: (Const32 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt32(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConst32F(v *Value) bool { // match: (Const32F [val]) // result: (FMOVSconst [float64(val)]) for { val := auxIntToFloat32(v.AuxInt) v.reset(OpARM64FMOVSconst) v.AuxInt = float64ToAuxInt(float64(val)) return true } } func rewriteValueARM64_OpConst64(v *Value) bool { // match: (Const64 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt64(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConst64F(v *Value) bool { // match: (Const64F [val]) // result: (FMOVDconst [float64(val)]) for { val := auxIntToFloat64(v.AuxInt) v.reset(OpARM64FMOVDconst) v.AuxInt = float64ToAuxInt(float64(val)) return true } } func rewriteValueARM64_OpConst8(v *Value) bool { // match: (Const8 [val]) // result: (MOVDconst [int64(val)]) for { val := auxIntToInt8(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(int64(val)) return true } } func rewriteValueARM64_OpConstBool(v *Value) bool { // match: (ConstBool [t]) // result: (MOVDconst [b2i(t)]) for { t := auxIntToBool(v.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(b2i(t)) return true } } func rewriteValueARM64_OpConstNil(v *Value) bool { // match: (ConstNil) // result: (MOVDconst [0]) for { v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } } func rewriteValueARM64_OpCtz16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz16 x) // result: (CLZW (RBITW (ORconst [0x10000] x))) for { t := v.Type x := v_0 v.reset(OpARM64CLZW) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64RBITW, typ.UInt32) v1 := b.NewValue0(v.Pos, OpARM64ORconst, typ.UInt32) v1.AuxInt = int64ToAuxInt(0x10000) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpCtz32(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Ctz32 x) // result: (CLZW (RBITW x)) for { t := v.Type x := v_0 v.reset(OpARM64CLZW) v0 := b.NewValue0(v.Pos, OpARM64RBITW, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpCtz64(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Ctz64 x) // result: (CLZ (RBIT x)) for { t := v.Type x := v_0 v.reset(OpARM64CLZ) v0 := b.NewValue0(v.Pos, OpARM64RBIT, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpCtz8(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Ctz8 x) // result: (CLZW (RBITW (ORconst [0x100] x))) for { t := v.Type x := v_0 v.reset(OpARM64CLZW) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64RBITW, typ.UInt32) v1 := b.NewValue0(v.Pos, OpARM64ORconst, typ.UInt32) v1.AuxInt = int64ToAuxInt(0x100) v1.AddArg(x) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16 [false] x y) // result: (DIVW (SignExt16to32 x) (SignExt16to32 y)) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpARM64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpDiv16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div16u x y) // result: (UDIVW (ZeroExt16to32 x) (ZeroExt16to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UDIVW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpDiv32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Div32 [false] x y) // result: (DIVW x y) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpARM64DIVW) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpDiv64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Div64 [false] x y) // result: (DIV x y) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpARM64DIV) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpDiv8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8 x y) // result: (DIVW (SignExt8to32 x) (SignExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64DIVW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpDiv8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Div8u x y) // result: (UDIVW (ZeroExt8to32 x) (ZeroExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UDIVW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq16 x y) // result: (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32 x y) // result: (Equal (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq32F x y) // result: (Equal (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64 x y) // result: (Equal (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Eq64F x y) // result: (Equal (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpEq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Eq8 x y) // result: (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpEqB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (EqB x y) // result: (XOR (MOVDconst [1]) (XOR x y)) for { x := v_0 y := v_1 v.reset(OpARM64XOR) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(1) v1 := b.NewValue0(v.Pos, OpARM64XOR, typ.Bool) v1.AddArg2(x, y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpEqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (EqPtr x y) // result: (Equal (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64Equal) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpFMA(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (FMA x y z) // result: (FMADDD z x y) for { x := v_0 y := v_1 z := v_2 v.reset(OpARM64FMADDD) v.AddArg3(z, x, y) return true } } func rewriteValueARM64_OpHmul32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Hmul32 x y) // result: (SRAconst (MULL x y) [32]) for { x := v_0 y := v_1 v.reset(OpARM64SRAconst) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpARM64MULL, typ.Int64) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpHmul32u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Hmul32u x y) // result: (SRAconst (UMULL x y) [32]) for { x := v_0 y := v_1 v.reset(OpARM64SRAconst) v.AuxInt = int64ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpARM64UMULL, typ.UInt64) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpIsInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsInBounds idx len) // result: (LessThanU (CMP idx len)) for { idx := v_0 len := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueARM64_OpIsNonNil(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (IsNonNil ptr) // result: (NotEqual (CMPconst [0] ptr)) for { ptr := v_0 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(0) v0.AddArg(ptr) v.AddArg(v0) return true } } func rewriteValueARM64_OpIsSliceInBounds(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (IsSliceInBounds idx len) // result: (LessEqualU (CMP idx len)) for { idx := v_0 len := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(idx, len) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq16 x y) // result: (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq16U x zero:(MOVDconst [0])) // result: (Eq16 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq16) v.AddArg2(x, zero) return true } // match: (Leq16U (MOVDconst [1]) x) // result: (Neq16 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq16) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq16U x y) // result: (LessEqualU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32 x y) // result: (LessEqual (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32F x y) // result: (LessEqualF (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualF) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq32U x zero:(MOVDconst [0])) // result: (Eq32 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq32) v.AddArg2(x, zero) return true } // match: (Leq32U (MOVDconst [1]) x) // result: (Neq32 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq32) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq32U x y) // result: (LessEqualU (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64 x y) // result: (LessEqual (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq64F x y) // result: (LessEqualF (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualF) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq64U x zero:(MOVDconst [0])) // result: (Eq64 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq64) v.AddArg2(x, zero) return true } // match: (Leq64U (MOVDconst [1]) x) // result: (Neq64 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq64) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq64U x y) // result: (LessEqualU (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq8 x y) // result: (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLeq8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Leq8U x zero:(MOVDconst [0])) // result: (Eq8 x zero) for { x := v_0 zero := v_1 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } v.reset(OpEq8) v.AddArg2(x, zero) return true } // match: (Leq8U (MOVDconst [1]) x) // result: (Neq8 (MOVDconst [0]) x) for { if v_0.Op != OpARM64MOVDconst || auxIntToInt64(v_0.AuxInt) != 1 { break } x := v_1 v.reset(OpNeq8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(v0, x) return true } // match: (Leq8U x y) // result: (LessEqualU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessEqualU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less16 x y) // result: (LessThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess16U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less16U zero:(MOVDconst [0]) x) // result: (Neq16 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq16) v.AddArg2(zero, x) return true } // match: (Less16U x (MOVDconst [1])) // result: (Eq16 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq16) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less16U x y) // result: (LessThanU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32 x y) // result: (LessThan (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less32F x y) // result: (LessThanF (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanF) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess32U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less32U zero:(MOVDconst [0]) x) // result: (Neq32 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq32) v.AddArg2(zero, x) return true } // match: (Less32U x (MOVDconst [1])) // result: (Eq32 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq32) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less32U x y) // result: (LessThanU (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64 x y) // result: (LessThan (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Less64F x y) // result: (LessThanF (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanF) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess64U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less64U zero:(MOVDconst [0]) x) // result: (Neq64 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq64) v.AddArg2(zero, x) return true } // match: (Less64U x (MOVDconst [1])) // result: (Eq64 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq64) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less64U x y) // result: (LessThanU (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less8 x y) // result: (LessThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThan) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLess8U(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Less8U zero:(MOVDconst [0]) x) // result: (Neq8 zero x) for { zero := v_0 if zero.Op != OpARM64MOVDconst || auxIntToInt64(zero.AuxInt) != 0 { break } x := v_1 v.reset(OpNeq8) v.AddArg2(zero, x) return true } // match: (Less8U x (MOVDconst [1])) // result: (Eq8 x (MOVDconst [0])) for { x := v_0 if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpEq8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg2(x, v0) return true } // match: (Less8U x y) // result: (LessThanU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpLoad(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Load ptr mem) // cond: t.IsBoolean() // result: (MOVBUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(t.IsBoolean()) { break } v.reset(OpARM64MOVBUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is8BitInt(t) && t.IsSigned()) // result: (MOVBload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is8BitInt(t) && t.IsSigned()) { break } v.reset(OpARM64MOVBload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is8BitInt(t) && !t.IsSigned()) // result: (MOVBUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is8BitInt(t) && !t.IsSigned()) { break } v.reset(OpARM64MOVBUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is16BitInt(t) && t.IsSigned()) // result: (MOVHload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t) && t.IsSigned()) { break } v.reset(OpARM64MOVHload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is16BitInt(t) && !t.IsSigned()) // result: (MOVHUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is16BitInt(t) && !t.IsSigned()) { break } v.reset(OpARM64MOVHUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is32BitInt(t) && t.IsSigned()) // result: (MOVWload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t) && t.IsSigned()) { break } v.reset(OpARM64MOVWload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is32BitInt(t) && !t.IsSigned()) // result: (MOVWUload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitInt(t) && !t.IsSigned()) { break } v.reset(OpARM64MOVWUload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: (is64BitInt(t) || isPtr(t)) // result: (MOVDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitInt(t) || isPtr(t)) { break } v.reset(OpARM64MOVDload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is32BitFloat(t) // result: (FMOVSload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is32BitFloat(t)) { break } v.reset(OpARM64FMOVSload) v.AddArg2(ptr, mem) return true } // match: (Load ptr mem) // cond: is64BitFloat(t) // result: (FMOVDload ptr mem) for { t := v.Type ptr := v_0 mem := v_1 if !(is64BitFloat(t)) { break } v.reset(OpARM64FMOVDload) v.AddArg2(ptr, mem) return true } return false } func rewriteValueARM64_OpLocalAddr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (LocalAddr {sym} base mem) // cond: t.Elem().HasPointers() // result: (MOVDaddr {sym} (SPanchored base mem)) for { t := v.Type sym := auxToSym(v.Aux) base := v_0 mem := v_1 if !(t.Elem().HasPointers()) { break } v.reset(OpARM64MOVDaddr) v.Aux = symToAux(sym) v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr) v0.AddArg2(base, mem) v.AddArg(v0) return true } // match: (LocalAddr {sym} base _) // cond: !t.Elem().HasPointers() // result: (MOVDaddr {sym} base) for { t := v.Type sym := auxToSym(v.Aux) base := v_0 if !(!t.Elem().HasPointers()) { break } v.reset(OpARM64MOVDaddr) v.Aux = symToAux(sym) v.AddArg(base) return true } return false } func rewriteValueARM64_OpLsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh16x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh16x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh16x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh32x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh32x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh32x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh64x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh64x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh64x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x16 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x32 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Lsh8x64 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpLsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Lsh8x8 x y) // cond: shiftIsBounded(v) // result: (SLL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SLL) v.Type = t v.AddArg2(x, y) return true } // match: (Lsh8x8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SLL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpMod16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16 x y) // result: (MODW (SignExt16to32 x) (SignExt16to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64MODW) v0 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt16to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMod16u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod16u x y) // result: (UMODW (ZeroExt16to32 x) (ZeroExt16to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UMODW) v0 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMod32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mod32 x y) // result: (MODW x y) for { x := v_0 y := v_1 v.reset(OpARM64MODW) v.AddArg2(x, y) return true } } func rewriteValueARM64_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mod64 x y) // result: (MOD x y) for { x := v_0 y := v_1 v.reset(OpARM64MOD) v.AddArg2(x, y) return true } } func rewriteValueARM64_OpMod8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8 x y) // result: (MODW (SignExt8to32 x) (SignExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64MODW) v0 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpSignExt8to32, typ.Int32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMod8u(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Mod8u x y) // result: (UMODW (ZeroExt8to32 x) (ZeroExt8to32 y)) for { x := v_0 y := v_1 v.reset(OpARM64UMODW) v0 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueARM64_OpMove(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Move [0] _ _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_2 v.copyOf(mem) return true } // match: (Move [1] dst src mem) // result: (MOVBstore dst (MOVBUload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [2] dst src mem) // result: (MOVHstore dst (MOVHUload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVHstore) v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [3] dst src mem) // result: (MOVBstore [2] dst (MOVBUload [2] src mem) (MOVHstore dst (MOVHUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AuxInt = int32ToAuxInt(2) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [4] dst src mem) // result: (MOVWstore dst (MOVWUload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVWstore) v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [5] dst src mem) // result: (MOVBstore [4] dst (MOVBUload [4] src mem) (MOVWstore dst (MOVWUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [6] dst src mem) // result: (MOVHstore [4] dst (MOVHUload [4] src mem) (MOVWstore dst (MOVWUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v0.AuxInt = int32ToAuxInt(4) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [7] dst src mem) // result: (MOVWstore [3] dst (MOVWUload [3] src mem) (MOVWstore dst (MOVWUload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [8] dst src mem) // result: (MOVDstore dst (MOVDload src mem) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AddArg2(src, mem) v.AddArg3(dst, v0, mem) return true } // match: (Move [9] dst src mem) // result: (MOVBstore [8] dst (MOVBUload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, typ.UInt8) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [10] dst src mem) // result: (MOVHstore [8] dst (MOVHUload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, typ.UInt16) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [11] dst src mem) // result: (MOVDstore [3] dst (MOVDload [3] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 11 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(3) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [12] dst src mem) // result: (MOVWstore [8] dst (MOVWUload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, typ.UInt32) v0.AuxInt = int32ToAuxInt(8) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [13] dst src mem) // result: (MOVDstore [5] dst (MOVDload [5] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 13 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(5) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(5) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [14] dst src mem) // result: (MOVDstore [6] dst (MOVDload [6] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 14 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(6) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(6) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [15] dst src mem) // result: (MOVDstore [7] dst (MOVDload [7] src mem) (MOVDstore dst (MOVDload src mem) mem)) for { if auxIntToInt64(v.AuxInt) != 15 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(7) v0 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v0.AuxInt = int32ToAuxInt(7) v0.AddArg2(src, mem) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v2 := b.NewValue0(v.Pos, OpARM64MOVDload, typ.UInt64) v2.AddArg2(src, mem) v1.AddArg3(dst, v2, mem) v.AddArg3(dst, v0, v1) return true } // match: (Move [16] dst src mem) // result: (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v.AddArg4(dst, v0, v2, mem) return true } // match: (Move [32] dst src mem) // result: (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AuxInt = int32ToAuxInt(16) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v5.AddArg2(src, mem) v4.AddArg(v5) v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v6.AddArg(v5) v3.AddArg4(dst, v4, v6, mem) v.AddArg4(dst, v0, v2, v3) return true } // match: (Move [48] dst src mem) // result: (STP [32] dst (Select0 (LDP [32] src mem)) (Select1 (LDP [32] src mem)) (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AuxInt = int32ToAuxInt(32) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v3.AuxInt = int32ToAuxInt(16) v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v5.AuxInt = int32ToAuxInt(16) v5.AddArg2(src, mem) v4.AddArg(v5) v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v6.AddArg(v5) v7 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v9 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v9.AddArg2(src, mem) v8.AddArg(v9) v10 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v10.AddArg(v9) v7.AddArg4(dst, v8, v10, mem) v3.AddArg4(dst, v4, v6, v7) v.AddArg4(dst, v0, v2, v3) return true } // match: (Move [64] dst src mem) // result: (STP [48] dst (Select0 (LDP [48] src mem)) (Select1 (LDP [48] src mem)) (STP [32] dst (Select0 (LDP [32] src mem)) (Select1 (LDP [32] src mem)) (STP [16] dst (Select0 (LDP [16] src mem)) (Select1 (LDP [16] src mem)) (STP dst (Select0 (LDP src mem)) (Select1 (LDP src mem)) mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } dst := v_0 src := v_1 mem := v_2 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(48) v0 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v1 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v1.AuxInt = int32ToAuxInt(48) v1.AddArg2(src, mem) v0.AddArg(v1) v2 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v2.AddArg(v1) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v3.AuxInt = int32ToAuxInt(32) v4 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v5 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v5.AuxInt = int32ToAuxInt(32) v5.AddArg2(src, mem) v4.AddArg(v5) v6 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v6.AddArg(v5) v7 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v7.AuxInt = int32ToAuxInt(16) v8 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v9 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v9.AuxInt = int32ToAuxInt(16) v9.AddArg2(src, mem) v8.AddArg(v9) v10 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v10.AddArg(v9) v11 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v12 := b.NewValue0(v.Pos, OpSelect0, typ.UInt64) v13 := b.NewValue0(v.Pos, OpARM64LDP, types.NewTuple(typ.UInt64, typ.UInt64)) v13.AddArg2(src, mem) v12.AddArg(v13) v14 := b.NewValue0(v.Pos, OpSelect1, typ.UInt64) v14.AddArg(v13) v11.AddArg4(dst, v12, v14, mem) v7.AddArg4(dst, v8, v10, v11) v3.AddArg4(dst, v4, v6, v7) v.AddArg4(dst, v0, v2, v3) return true } // match: (Move [s] dst src mem) // cond: s%16 != 0 && s%16 <= 8 && s > 16 // result: (Move [8] (OffPtr dst [s-8]) (OffPtr src [s-8]) (Move [s-s%16] dst src mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s%16 != 0 && s%16 <= 8 && s > 16) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s - 8) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s - 8) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(s - s%16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s%16 != 0 && s%16 > 8 && s > 16 // result: (Move [16] (OffPtr dst [s-16]) (OffPtr src [s-16]) (Move [s-s%16] dst src mem)) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s%16 != 0 && s%16 > 8 && s > 16) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(dst) v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type) v1.AuxInt = int64ToAuxInt(s - 16) v1.AddArg(src) v2 := b.NewValue0(v.Pos, OpMove, types.TypeMem) v2.AuxInt = int64ToAuxInt(s - s%16) v2.AddArg3(dst, src, mem) v.AddArg3(v0, v1, v2) return true } // match: (Move [s] dst src mem) // cond: s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s) // result: (DUFFCOPY [8 * (64 - s/16)] dst src mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s > 64 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice && logLargeCopy(v, s)) { break } v.reset(OpARM64DUFFCOPY) v.AuxInt = int64ToAuxInt(8 * (64 - s/16)) v.AddArg3(dst, src, mem) return true } // match: (Move [s] dst src mem) // cond: s%16 == 0 && (s > 16*64 || config.noDuffDevice) && logLargeCopy(v, s) // result: (LoweredMove dst src (ADDconst src [s-16]) mem) for { s := auxIntToInt64(v.AuxInt) dst := v_0 src := v_1 mem := v_2 if !(s%16 == 0 && (s > 16*64 || config.noDuffDevice) && logLargeCopy(v, s)) { break } v.reset(OpARM64LoweredMove) v0 := b.NewValue0(v.Pos, OpARM64ADDconst, src.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(src) v.AddArg4(dst, src, v0, mem) return true } return false } func rewriteValueARM64_OpNeq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq16 x y) // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32 x y) // result: (NotEqual (CMPW x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq32F x y) // result: (NotEqual (FCMPS x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64FCMPS, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64 x y) // result: (NotEqual (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq64F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Neq64F x y) // result: (NotEqual (FCMPD x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64FCMPD, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeq8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Neq8 x y) // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v1.AddArg(x) v2 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32) v2.AddArg(y) v0.AddArg2(v1, v2) v.AddArg(v0) return true } } func rewriteValueARM64_OpNeqPtr(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (NeqPtr x y) // result: (NotEqual (CMP x y)) for { x := v_0 y := v_1 v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } } func rewriteValueARM64_OpNot(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Not x) // result: (XOR (MOVDconst [1]) x) for { x := v_0 v.reset(OpARM64XOR) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(1) v.AddArg2(v0, x) return true } } func rewriteValueARM64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] // match: (OffPtr [off] ptr:(SP)) // cond: is32Bit(off) // result: (MOVDaddr [int32(off)] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 if ptr.Op != OpSP || !(is32Bit(off)) { break } v.reset(OpARM64MOVDaddr) v.AuxInt = int32ToAuxInt(int32(off)) v.AddArg(ptr) return true } // match: (OffPtr [off] ptr) // result: (ADDconst [off] ptr) for { off := auxIntToInt64(v.AuxInt) ptr := v_0 v.reset(OpARM64ADDconst) v.AuxInt = int64ToAuxInt(off) v.AddArg(ptr) return true } } func rewriteValueARM64_OpPanicBounds(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 0 // result: (LoweredPanicBoundsA [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 0) { break } v.reset(OpARM64LoweredPanicBoundsA) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 1 // result: (LoweredPanicBoundsB [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 1) { break } v.reset(OpARM64LoweredPanicBoundsB) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } // match: (PanicBounds [kind] x y mem) // cond: boundsABI(kind) == 2 // result: (LoweredPanicBoundsC [kind] x y mem) for { kind := auxIntToInt64(v.AuxInt) x := v_0 y := v_1 mem := v_2 if !(boundsABI(kind) == 2) { break } v.reset(OpARM64LoweredPanicBoundsC) v.AuxInt = int64ToAuxInt(kind) v.AddArg3(x, y, mem) return true } return false } func rewriteValueARM64_OpPopCount16(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount16 x) // result: (FMOVDfpgp (VUADDLV (VCNT (FMOVDgpfp (ZeroExt16to64 x))))) for { t := v.Type x := v_0 v.reset(OpARM64FMOVDfpgp) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64) v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64) v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(x) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpPopCount32(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount32 x) // result: (FMOVDfpgp (VUADDLV (VCNT (FMOVDgpfp (ZeroExt32to64 x))))) for { t := v.Type x := v_0 v.reset(OpARM64FMOVDfpgp) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64) v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64) v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(x) v2.AddArg(v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpPopCount64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (PopCount64 x) // result: (FMOVDfpgp (VUADDLV (VCNT (FMOVDgpfp x)))) for { t := v.Type x := v_0 v.reset(OpARM64FMOVDfpgp) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64VUADDLV, typ.Float64) v1 := b.NewValue0(v.Pos, OpARM64VCNT, typ.Float64) v2 := b.NewValue0(v.Pos, OpARM64FMOVDgpfp, typ.Float64) v2.AddArg(x) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } } func rewriteValueARM64_OpPrefetchCache(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (PrefetchCache addr mem) // result: (PRFM [0] addr mem) for { addr := v_0 mem := v_1 v.reset(OpARM64PRFM) v.AuxInt = int64ToAuxInt(0) v.AddArg2(addr, mem) return true } } func rewriteValueARM64_OpPrefetchCacheStreamed(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (PrefetchCacheStreamed addr mem) // result: (PRFM [1] addr mem) for { addr := v_0 mem := v_1 v.reset(OpARM64PRFM) v.AuxInt = int64ToAuxInt(1) v.AddArg2(addr, mem) return true } } func rewriteValueARM64_OpPubBarrier(v *Value) bool { v_0 := v.Args[0] // match: (PubBarrier mem) // result: (DMB [0xe] mem) for { mem := v_0 v.reset(OpARM64DMB) v.AuxInt = int64ToAuxInt(0xe) v.AddArg(mem) return true } } func rewriteValueARM64_OpRotateLeft16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (RotateLeft16 x (MOVDconst [c])) // result: (Or16 (Lsh16x64 x (MOVDconst [c&15])) (Rsh16Ux64 x (MOVDconst [-c&15]))) for { t := v.Type x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpOr16) v0 := b.NewValue0(v.Pos, OpLsh16x64, t) v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(c & 15) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpRsh16Ux64, t) v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v3.AuxInt = int64ToAuxInt(-c & 15) v2.AddArg2(x, v3) v.AddArg2(v0, v2) return true } // match: (RotateLeft16 x y) // result: (RORW (ORshiftLL (ZeroExt16to32 x) (ZeroExt16to32 x) [16]) (NEG y)) for { t := v.Type x := v_0 y := v_1 v.reset(OpARM64RORW) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64ORshiftLL, typ.UInt32) v0.AuxInt = int64ToAuxInt(16) v1 := b.NewValue0(v.Pos, OpZeroExt16to32, typ.UInt32) v1.AddArg(x) v0.AddArg2(v1, v1) v2 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) v2.AddArg(y) v.AddArg2(v0, v2) return true } } func rewriteValueARM64_OpRotateLeft32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (RotateLeft32 x y) // result: (RORW x (NEG y)) for { x := v_0 y := v_1 v.reset(OpARM64RORW) v0 := b.NewValue0(v.Pos, OpARM64NEG, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } } func rewriteValueARM64_OpRotateLeft64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (RotateLeft64 x y) // result: (ROR x (NEG y)) for { x := v_0 y := v_1 v.reset(OpARM64ROR) v0 := b.NewValue0(v.Pos, OpARM64NEG, y.Type) v0.AddArg(y) v.AddArg2(x, v0) return true } } func rewriteValueARM64_OpRotateLeft8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (RotateLeft8 x (MOVDconst [c])) // result: (Or8 (Lsh8x64 x (MOVDconst [c&7])) (Rsh8Ux64 x (MOVDconst [-c&7]))) for { t := v.Type x := v_0 if v_1.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpOr8) v0 := b.NewValue0(v.Pos, OpLsh8x64, t) v1 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v1.AuxInt = int64ToAuxInt(c & 7) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpRsh8Ux64, t) v3 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v3.AuxInt = int64ToAuxInt(-c & 7) v2.AddArg2(x, v3) v.AddArg2(v0, v2) return true } // match: (RotateLeft8 x y) // result: (OR (SLL x (ANDconst [7] y)) (SRL (ZeroExt8to64 x) (ANDconst [7] (NEG y)))) for { t := v.Type x := v_0 y := v_1 v.reset(OpARM64OR) v.Type = t v0 := b.NewValue0(v.Pos, OpARM64SLL, t) v1 := b.NewValue0(v.Pos, OpARM64ANDconst, typ.Int64) v1.AuxInt = int64ToAuxInt(7) v1.AddArg(y) v0.AddArg2(x, v1) v2 := b.NewValue0(v.Pos, OpARM64SRL, t) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(x) v4 := b.NewValue0(v.Pos, OpARM64ANDconst, typ.Int64) v4.AuxInt = int64ToAuxInt(7) v5 := b.NewValue0(v.Pos, OpARM64NEG, typ.Int64) v5.AddArg(y) v4.AddArg(v5) v2.AddArg2(v3, v4) v.AddArg2(v0, v2) return true } } func rewriteValueARM64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x16 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x16 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x32 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x32 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh16x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x64 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x64 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh16x8 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt16to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh16x8 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt16to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x16 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x16 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x32 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x32 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x64 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x64 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh32x8 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt32to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh32x8 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt32to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh64Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL x y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v0.AddArg2(x, y) v1 := b.NewValue0(v.Pos, OpConst64, t) v1.AuxInt = int64ToAuxInt(0) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v.AddArg3(v0, v1, v2) return true } return false } func rewriteValueARM64_OpRsh64x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x16 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x16 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh64x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x32 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x32 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh64x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Rsh64x64 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x64 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v2.AddArg(y) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh64x8 x y) // cond: shiftIsBounded(v) // result: (SRA x y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v.AddArg2(x, y) return true } // match: (Rsh64x8 x y) // cond: !shiftIsBounded(v) // result: (SRA x (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v0.AuxInt = opToAuxInt(OpARM64LessThanU) v1 := b.NewValue0(v.Pos, OpConst64, y.Type) v1.AuxInt = int64ToAuxInt(63) v2 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v2.AuxInt = int64ToAuxInt(64) v3 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v3.AddArg(y) v2.AddArg(v3) v0.AddArg3(y, v1, v2) v.AddArg2(x, v0) return true } return false } func rewriteValueARM64_OpRsh8Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux16 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux16 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8Ux32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux32 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux32 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8Ux64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux64 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux64 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8Ux8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8Ux8 x y) // cond: shiftIsBounded(v) // result: (SRL (ZeroExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRL) v.Type = t v0 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8Ux8 x y) // cond: !shiftIsBounded(v) // result: (CSEL [OpARM64LessThanU] (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { t := v.Type x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64CSEL) v.AuxInt = opToAuxInt(OpARM64LessThanU) v0 := b.NewValue0(v.Pos, OpARM64SRL, t) v1 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v1.AddArg(x) v0.AddArg2(v1, y) v2 := b.NewValue0(v.Pos, OpConst64, t) v2.AuxInt = int64ToAuxInt(0) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v.AddArg3(v0, v2, v3) return true } return false } func rewriteValueARM64_OpRsh8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x16 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x16 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt16to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x32 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x32 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt32to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x64 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x64 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] y))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v3.AddArg(y) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpRsh8x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Rsh8x8 x y) // cond: shiftIsBounded(v) // result: (SRA (SignExt8to64 x) y) for { t := v.Type x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v.Type = t v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v.AddArg2(v0, y) return true } // match: (Rsh8x8 x y) // cond: !shiftIsBounded(v) // result: (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] y (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v_0 y := v_1 if !(!shiftIsBounded(v)) { break } v.reset(OpARM64SRA) v0 := b.NewValue0(v.Pos, OpSignExt8to64, typ.Int64) v0.AddArg(x) v1 := b.NewValue0(v.Pos, OpARM64CSEL, y.Type) v1.AuxInt = opToAuxInt(OpARM64LessThanU) v2 := b.NewValue0(v.Pos, OpConst64, y.Type) v2.AuxInt = int64ToAuxInt(63) v3 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v3.AuxInt = int64ToAuxInt(64) v4 := b.NewValue0(v.Pos, OpZeroExt8to64, typ.UInt64) v4.AddArg(y) v3.AddArg(v4) v1.AddArg3(y, v2, v3) v.AddArg2(v0, v1) return true } return false } func rewriteValueARM64_OpSelect0(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select0 (Mul64uhilo x y)) // result: (UMULH x y) for { if v_0.Op != OpMul64uhilo { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64UMULH) v.AddArg2(x, y) return true } // match: (Select0 (Add64carry x y c)) // result: (Select0 (ADCSflags x y (Select1 (ADDSconstflags [-1] c)))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64ADCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpARM64ADDSconstflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AuxInt = int64ToAuxInt(-1) v2.AddArg(c) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Sub64borrow x y bo)) // result: (Select0 (SBCSflags x y (Select1 (NEGSflags bo)))) for { if v_0.Op != OpSub64borrow { break } bo := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpSelect0) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64SBCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpARM64NEGSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v2.AddArg(bo) v1.AddArg(v2) v0.AddArg3(x, y, v1) v.AddArg(v0) return true } // match: (Select0 (Mul64uover x y)) // result: (MUL x y) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MUL) v.AddArg2(x, y) return true } return false } func rewriteValueARM64_OpSelect1(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Select1 (Mul64uhilo x y)) // result: (MUL x y) for { if v_0.Op != OpMul64uhilo { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64MUL) v.AddArg2(x, y) return true } // match: (Select1 (Add64carry x y c)) // result: (ADCzerocarry (Select1 (ADCSflags x y (Select1 (ADDSconstflags [-1] c))))) for { if v_0.Op != OpAdd64carry { break } c := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpARM64ADCzerocarry) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v1 := b.NewValue0(v.Pos, OpARM64ADCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v2 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v3 := b.NewValue0(v.Pos, OpARM64ADDSconstflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v3.AuxInt = int64ToAuxInt(-1) v3.AddArg(c) v2.AddArg(v3) v1.AddArg3(x, y, v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Sub64borrow x y bo)) // result: (NEG (NGCzerocarry (Select1 (SBCSflags x y (Select1 (NEGSflags bo)))))) for { if v_0.Op != OpSub64borrow { break } bo := v_0.Args[2] x := v_0.Args[0] y := v_0.Args[1] v.reset(OpARM64NEG) v.Type = typ.UInt64 v0 := b.NewValue0(v.Pos, OpARM64NGCzerocarry, typ.UInt64) v1 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v2 := b.NewValue0(v.Pos, OpARM64SBCSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v3 := b.NewValue0(v.Pos, OpSelect1, types.TypeFlags) v4 := b.NewValue0(v.Pos, OpARM64NEGSflags, types.NewTuple(typ.UInt64, types.TypeFlags)) v4.AddArg(bo) v3.AddArg(v4) v2.AddArg3(x, y, v3) v1.AddArg(v2) v0.AddArg(v1) v.AddArg(v0) return true } // match: (Select1 (Mul64uover x y)) // result: (NotEqual (CMPconst (UMULH x y) [0])) for { if v_0.Op != OpMul64uover { break } y := v_0.Args[1] x := v_0.Args[0] v.reset(OpARM64NotEqual) v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64UMULH, typ.UInt64) v1.AddArg2(x, y) v0.AddArg(v1) v.AddArg(v0) return true } return false } func rewriteValueARM64_OpSelectN(v *Value) bool { v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVDstore _ (MOVDconst [sz]) s2:(MOVDstore _ src s3:(MOVDstore {t} _ dst mem))))) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(s1, s2, s3, call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpARM64CALLstatic || len(call.Args) != 1 { break } sym := auxToCall(call.Aux) s1 := call.Args[0] if s1.Op != OpARM64MOVDstore { break } _ = s1.Args[2] s1_1 := s1.Args[1] if s1_1.Op != OpARM64MOVDconst { break } sz := auxIntToInt64(s1_1.AuxInt) s2 := s1.Args[2] if s2.Op != OpARM64MOVDstore { break } _ = s2.Args[2] src := s2.Args[1] s3 := s2.Args[2] if s3.Op != OpARM64MOVDstore { break } mem := s3.Args[2] dst := s3.Args[1] if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(s1, s2, s3, call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } // match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVDconst [sz]) mem)) // cond: sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call) // result: (Move [sz] dst src mem) for { if auxIntToInt64(v.AuxInt) != 0 { break } call := v_0 if call.Op != OpARM64CALLstatic || len(call.Args) != 4 { break } sym := auxToCall(call.Aux) mem := call.Args[3] dst := call.Args[0] src := call.Args[1] call_2 := call.Args[2] if call_2.Op != OpARM64MOVDconst { break } sz := auxIntToInt64(call_2.AuxInt) if !(sz >= 0 && isSameCall(sym, "runtime.memmove") && call.Uses == 1 && isInlinableMemmove(dst, src, sz, config) && clobber(call)) { break } v.reset(OpMove) v.AuxInt = int64ToAuxInt(sz) v.AddArg3(dst, src, mem) return true } return false } func rewriteValueARM64_OpSlicemask(v *Value) bool { v_0 := v.Args[0] b := v.Block // match: (Slicemask x) // result: (SRAconst (NEG x) [63]) for { t := v.Type x := v_0 v.reset(OpARM64SRAconst) v.AuxInt = int64ToAuxInt(63) v0 := b.NewValue0(v.Pos, OpARM64NEG, t) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValueARM64_OpStore(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (Store {t} ptr val mem) // cond: t.Size() == 1 // result: (MOVBstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 1) { break } v.reset(OpARM64MOVBstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 2 // result: (MOVHstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 2) { break } v.reset(OpARM64MOVHstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && !t.IsFloat() // result: (MOVWstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && !t.IsFloat()) { break } v.reset(OpARM64MOVWstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && !t.IsFloat() // result: (MOVDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && !t.IsFloat()) { break } v.reset(OpARM64MOVDstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 4 && t.IsFloat() // result: (FMOVSstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 4 && t.IsFloat()) { break } v.reset(OpARM64FMOVSstore) v.AddArg3(ptr, val, mem) return true } // match: (Store {t} ptr val mem) // cond: t.Size() == 8 && t.IsFloat() // result: (FMOVDstore ptr val mem) for { t := auxToType(v.Aux) ptr := v_0 val := v_1 mem := v_2 if !(t.Size() == 8 && t.IsFloat()) { break } v.reset(OpARM64FMOVDstore) v.AddArg3(ptr, val, mem) return true } return false } func rewriteValueARM64_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config typ := &b.Func.Config.Types // match: (Zero [0] _ mem) // result: mem for { if auxIntToInt64(v.AuxInt) != 0 { break } mem := v_1 v.copyOf(mem) return true } // match: (Zero [1] ptr mem) // result: (MOVBstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 1 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [2] ptr mem) // result: (MOVHstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 2 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVHstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [4] ptr mem) // result: (MOVWstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 4 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVWstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [3] ptr mem) // result: (MOVBstore [2] ptr (MOVDconst [0]) (MOVHstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 3 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(2) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVHstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [5] ptr mem) // result: (MOVBstore [4] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 5 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [6] ptr mem) // result: (MOVHstore [4] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 6 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(4) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [7] ptr mem) // result: (MOVWstore [3] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 7 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVWstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [8] ptr mem) // result: (MOVDstore ptr (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 8 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg3(ptr, v0, mem) return true } // match: (Zero [9] ptr mem) // result: (MOVBstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 9 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVBstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [10] ptr mem) // result: (MOVHstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 10 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVHstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [11] ptr mem) // result: (MOVDstore [3] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 11 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(3) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [12] ptr mem) // result: (MOVWstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 12 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVWstore) v.AuxInt = int32ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [13] ptr mem) // result: (MOVDstore [5] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 13 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(5) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [14] ptr mem) // result: (MOVDstore [6] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 14 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(6) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [15] ptr mem) // result: (MOVDstore [7] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 15 { break } ptr := v_0 mem := v_1 v.reset(OpARM64MOVDstore) v.AuxInt = int32ToAuxInt(7) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64MOVDstore, types.TypeMem) v1.AddArg3(ptr, v0, mem) v.AddArg3(ptr, v0, v1) return true } // match: (Zero [16] ptr mem) // result: (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem) for { if auxIntToInt64(v.AuxInt) != 16 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(0) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v.AddArg4(ptr, v0, v0, mem) return true } // match: (Zero [32] ptr mem) // result: (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem)) for { if auxIntToInt64(v.AuxInt) != 32 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v1.AuxInt = int32ToAuxInt(0) v1.AddArg4(ptr, v0, v0, mem) v.AddArg4(ptr, v0, v0, v1) return true } // match: (Zero [48] ptr mem) // result: (STP [32] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem))) for { if auxIntToInt64(v.AuxInt) != 48 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(32) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v1.AuxInt = int32ToAuxInt(16) v2 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v2.AuxInt = int32ToAuxInt(0) v2.AddArg4(ptr, v0, v0, mem) v1.AddArg4(ptr, v0, v0, v2) v.AddArg4(ptr, v0, v0, v1) return true } // match: (Zero [64] ptr mem) // result: (STP [48] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [32] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem)))) for { if auxIntToInt64(v.AuxInt) != 64 { break } ptr := v_0 mem := v_1 v.reset(OpARM64STP) v.AuxInt = int32ToAuxInt(48) v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64) v0.AuxInt = int64ToAuxInt(0) v1 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v1.AuxInt = int32ToAuxInt(32) v2 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v2.AuxInt = int32ToAuxInt(16) v3 := b.NewValue0(v.Pos, OpARM64STP, types.TypeMem) v3.AuxInt = int32ToAuxInt(0) v3.AddArg4(ptr, v0, v0, mem) v2.AddArg4(ptr, v0, v0, v3) v1.AddArg4(ptr, v0, v0, v2) v.AddArg4(ptr, v0, v0, v1) return true } // match: (Zero [s] ptr mem) // cond: s%16 != 0 && s%16 <= 8 && s > 16 // result: (Zero [8] (OffPtr ptr [s-8]) (Zero [s-s%16] ptr mem)) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 != 0 && s%16 <= 8 && s > 16) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(8) v0 := b.NewValue0(v.Pos, OpOffPtr, ptr.Type) v0.AuxInt = int64ToAuxInt(s - 8) v0.AddArg(ptr) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(s - s%16) v1.AddArg2(ptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] ptr mem) // cond: s%16 != 0 && s%16 > 8 && s > 16 // result: (Zero [16] (OffPtr ptr [s-16]) (Zero [s-s%16] ptr mem)) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 != 0 && s%16 > 8 && s > 16) { break } v.reset(OpZero) v.AuxInt = int64ToAuxInt(16) v0 := b.NewValue0(v.Pos, OpOffPtr, ptr.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(ptr) v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem) v1.AuxInt = int64ToAuxInt(s - s%16) v1.AddArg2(ptr, mem) v.AddArg2(v0, v1) return true } // match: (Zero [s] ptr mem) // cond: s%16 == 0 && s > 64 && s <= 16*64 && !config.noDuffDevice // result: (DUFFZERO [4 * (64 - s/16)] ptr mem) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 == 0 && s > 64 && s <= 16*64 && !config.noDuffDevice) { break } v.reset(OpARM64DUFFZERO) v.AuxInt = int64ToAuxInt(4 * (64 - s/16)) v.AddArg2(ptr, mem) return true } // match: (Zero [s] ptr mem) // cond: s%16 == 0 && (s > 16*64 || config.noDuffDevice) // result: (LoweredZero ptr (ADDconst [s-16] ptr) mem) for { s := auxIntToInt64(v.AuxInt) ptr := v_0 mem := v_1 if !(s%16 == 0 && (s > 16*64 || config.noDuffDevice)) { break } v.reset(OpARM64LoweredZero) v0 := b.NewValue0(v.Pos, OpARM64ADDconst, ptr.Type) v0.AuxInt = int64ToAuxInt(s - 16) v0.AddArg(ptr) v.AddArg3(ptr, v0, mem) return true } return false } func rewriteBlockARM64(b *Block) bool { typ := &b.Func.Config.Types switch b.Kind { case BlockARM64EQ: // match: (EQ (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (EQ (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (EQ (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (EQ (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } break } // match: (EQ (CMP x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMP { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPW x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (EQ (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPW { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] x) yes no) // result: (Z x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64Z, x) return true } // match: (EQ (CMPWconst [0] x) yes no) // result: (ZW x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64ZW, x) return true } // match: (EQ (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (EQ (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64EQ, v0) return true } // match: (EQ (TSTconst [c] x) yes no) // cond: oneBit(c) // result: (TBZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64TSTconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (EQ (TSTWconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64TSTWconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (EQ (FlagConstant [fc]) yes no) // cond: fc.eq() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.eq()) { break } b.Reset(BlockFirst) return true } // match: (EQ (FlagConstant [fc]) yes no) // cond: !fc.eq() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.eq()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (EQ (InvertFlags cmp) yes no) // result: (EQ cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64EQ, cmp) return true } case BlockARM64FGE: // match: (FGE (InvertFlags cmp) yes no) // result: (FLE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FLE, cmp) return true } case BlockARM64FGT: // match: (FGT (InvertFlags cmp) yes no) // result: (FLT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FLT, cmp) return true } case BlockARM64FLE: // match: (FLE (InvertFlags cmp) yes no) // result: (FGE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FGE, cmp) return true } case BlockARM64FLT: // match: (FLT (InvertFlags cmp) yes no) // result: (FGT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64FGT, cmp) return true } case BlockARM64GE: // match: (GE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GE (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GE, v0) return true } break } // match: (GE (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GE (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GE, v0) return true } // match: (GE (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GE (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GE, v0) return true } break } // match: (GE (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GE (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GE, v0) return true } // match: (GE (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GEnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GEnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GEnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GEnoov, v0) return true } break } // match: (GE (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GEnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GEnoov, v0) return true } break } // match: (GE (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (GEnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GEnoov, v0) return true } // match: (GE (CMPWconst [0] x) yes no) // result: (TBZ [31] x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(31) return true } // match: (GE (CMPconst [0] x) yes no) // result: (TBZ [63] x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(63) return true } // match: (GE (FlagConstant [fc]) yes no) // cond: fc.ge() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ge()) { break } b.Reset(BlockFirst) return true } // match: (GE (FlagConstant [fc]) yes no) // cond: !fc.ge() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ge()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GE (InvertFlags cmp) yes no) // result: (LE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LE, cmp) return true } case BlockARM64GEnoov: // match: (GEnoov (FlagConstant [fc]) yes no) // cond: fc.geNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.geNoov()) { break } b.Reset(BlockFirst) return true } // match: (GEnoov (FlagConstant [fc]) yes no) // cond: !fc.geNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.geNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GEnoov (InvertFlags cmp) yes no) // result: (LEnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LEnoov, cmp) return true } case BlockARM64GT: // match: (GT (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GT (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GT, v0) return true } break } // match: (GT (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GT (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GT, v0) return true } // match: (GT (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (GT (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GT, v0) return true } break } // match: (GT (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GT (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GT, v0) return true } // match: (GT (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GTnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (GTnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GTnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GTnoov, v0) return true } break } // match: (GT (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (GTnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64GTnoov, v0) return true } break } // match: (GT (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (GTnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64GTnoov, v0) return true } // match: (GT (FlagConstant [fc]) yes no) // cond: fc.gt() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.gt()) { break } b.Reset(BlockFirst) return true } // match: (GT (FlagConstant [fc]) yes no) // cond: !fc.gt() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.gt()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GT (InvertFlags cmp) yes no) // result: (LT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LT, cmp) return true } case BlockARM64GTnoov: // match: (GTnoov (FlagConstant [fc]) yes no) // cond: fc.gtNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.gtNoov()) { break } b.Reset(BlockFirst) return true } // match: (GTnoov (FlagConstant [fc]) yes no) // cond: !fc.gtNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.gtNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (GTnoov (InvertFlags cmp) yes no) // result: (LTnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64LTnoov, cmp) return true } case BlockIf: // match: (If (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpARM64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64EQ, cc) return true } // match: (If (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpARM64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64NE, cc) return true } // match: (If (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpARM64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LT, cc) return true } // match: (If (LessThanU cc) yes no) // result: (ULT cc yes no) for b.Controls[0].Op == OpARM64LessThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULT, cc) return true } // match: (If (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpARM64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LE, cc) return true } // match: (If (LessEqualU cc) yes no) // result: (ULE cc yes no) for b.Controls[0].Op == OpARM64LessEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULE, cc) return true } // match: (If (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpARM64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GT, cc) return true } // match: (If (GreaterThanU cc) yes no) // result: (UGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGT, cc) return true } // match: (If (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GE, cc) return true } // match: (If (GreaterEqualU cc) yes no) // result: (UGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGE, cc) return true } // match: (If (LessThanF cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpARM64LessThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLT, cc) return true } // match: (If (LessEqualF cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpARM64LessEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLE, cc) return true } // match: (If (GreaterThanF cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGT, cc) return true } // match: (If (GreaterEqualF cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGE, cc) return true } // match: (If cond yes no) // result: (TBNZ [0] cond yes no) for { cond := b.Controls[0] b.resetWithControl(BlockARM64TBNZ, cond) b.AuxInt = int64ToAuxInt(0) return true } case BlockJumpTable: // match: (JumpTable idx) // result: (JUMPTABLE {makeJumpTableSym(b)} idx (MOVDaddr {makeJumpTableSym(b)} (SB))) for { idx := b.Controls[0] v0 := b.NewValue0(b.Pos, OpARM64MOVDaddr, typ.Uintptr) v0.Aux = symToAux(makeJumpTableSym(b)) v1 := b.NewValue0(b.Pos, OpSB, typ.Uintptr) v0.AddArg(v1) b.resetWithControl2(BlockARM64JUMPTABLE, idx, v0) b.Aux = symToAux(makeJumpTableSym(b)) return true } case BlockARM64LE: // match: (LE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LE (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LE, v0) return true } break } // match: (LE (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LE (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LE, v0) return true } // match: (LE (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LE (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LE, v0) return true } break } // match: (LE (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LE (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LE, v0) return true } // match: (LE (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LEnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LEnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LEnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LEnoov, v0) return true } break } // match: (LE (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LEnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LEnoov, v0) return true } break } // match: (LE (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (LEnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LEnoov, v0) return true } // match: (LE (FlagConstant [fc]) yes no) // cond: fc.le() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.le()) { break } b.Reset(BlockFirst) return true } // match: (LE (FlagConstant [fc]) yes no) // cond: !fc.le() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.le()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LE (InvertFlags cmp) yes no) // result: (GE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GE, cmp) return true } case BlockARM64LEnoov: // match: (LEnoov (FlagConstant [fc]) yes no) // cond: fc.leNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.leNoov()) { break } b.Reset(BlockFirst) return true } // match: (LEnoov (FlagConstant [fc]) yes no) // cond: !fc.leNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.leNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LEnoov (InvertFlags cmp) yes no) // result: (GEnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GEnoov, cmp) return true } case BlockARM64LT: // match: (LT (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LT (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LT, v0) return true } break } // match: (LT (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LT (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LT, v0) return true } // match: (LT (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (LT (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LT, v0) return true } break } // match: (LT (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LT (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LT, v0) return true } // match: (LT (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LTnoov (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (LTnoov (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LTnoov (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LTnoov, v0) return true } break } // match: (LT (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (LTnoov (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64LTnoov, v0) return true } break } // match: (LT (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (LTnoov (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64LTnoov, v0) return true } // match: (LT (CMPWconst [0] x) yes no) // result: (TBNZ [31] x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(31) return true } // match: (LT (CMPconst [0] x) yes no) // result: (TBNZ [63] x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(63) return true } // match: (LT (FlagConstant [fc]) yes no) // cond: fc.lt() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.lt()) { break } b.Reset(BlockFirst) return true } // match: (LT (FlagConstant [fc]) yes no) // cond: !fc.lt() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.lt()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LT (InvertFlags cmp) yes no) // result: (GT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GT, cmp) return true } case BlockARM64LTnoov: // match: (LTnoov (FlagConstant [fc]) yes no) // cond: fc.ltNoov() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ltNoov()) { break } b.Reset(BlockFirst) return true } // match: (LTnoov (FlagConstant [fc]) yes no) // cond: !fc.ltNoov() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ltNoov()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (LTnoov (InvertFlags cmp) yes no) // result: (GTnoov cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64GTnoov, cmp) return true } case BlockARM64NE: // match: (NE (CMPconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (NE (TST x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TST, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMPconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (TSTconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] z:(AND x y)) yes no) // cond: z.Uses == 1 // result: (NE (TSTW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64AND { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64TSTW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMPWconst [0] x:(ANDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (TSTWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ANDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64TSTWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (CMNconst [c] y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNconst, types.TypeFlags) v0.AuxInt = int64ToAuxInt(c) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] x:(ADDconst [c] y)) yes no) // cond: x.Uses == 1 // result: (NE (CMNWconst [int32(c)] y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] if x.Op != OpARM64ADDconst { break } c := auxIntToInt64(x.AuxInt) y := x.Args[0] if !(x.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNWconst, types.TypeFlags) v0.AuxInt = int32ToAuxInt(int32(c)) v0.AddArg(y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (NE (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMPWconst [0] z:(ADD x y)) yes no) // cond: z.Uses == 1 // result: (NE (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64ADD { break } _ = z.Args[1] z_0 := z.Args[0] z_1 := z.Args[1] for _i0 := 0; _i0 <= 1; _i0, z_0, z_1 = _i0+1, z_1, z_0 { x := z_0 y := z_1 if !(z.Uses == 1) { continue } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } break } // match: (NE (CMP x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (NE (CMN x y) yes no) for b.Controls[0].Op == OpARM64CMP { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPW x z:(NEG y)) yes no) // cond: z.Uses == 1 // result: (NE (CMNW x y) yes no) for b.Controls[0].Op == OpARM64CMPW { v_0 := b.Controls[0] _ = v_0.Args[1] x := v_0.Args[0] z := v_0.Args[1] if z.Op != OpARM64NEG { break } y := z.Args[0] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v0.AddArg2(x, y) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] x) yes no) // result: (NZ x yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64NZ, x) return true } // match: (NE (CMPWconst [0] x) yes no) // result: (NZW x yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } x := v_0.Args[0] b.resetWithControl(BlockARM64NZW, x) return true } // match: (NE (CMPconst [0] z:(MADD a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMN a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADD { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMN, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPconst [0] z:(MSUB a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMP a (MUL x y)) yes no) for b.Controls[0].Op == OpARM64CMPconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUB { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMP, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MUL, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] z:(MADDW a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMNW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MADDW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMNW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (CMPWconst [0] z:(MSUBW a x y)) yes no) // cond: z.Uses==1 // result: (NE (CMPW a (MULW x y)) yes no) for b.Controls[0].Op == OpARM64CMPWconst { v_0 := b.Controls[0] if auxIntToInt32(v_0.AuxInt) != 0 { break } z := v_0.Args[0] if z.Op != OpARM64MSUBW { break } y := z.Args[2] a := z.Args[0] x := z.Args[1] if !(z.Uses == 1) { break } v0 := b.NewValue0(v_0.Pos, OpARM64CMPW, types.TypeFlags) v1 := b.NewValue0(v_0.Pos, OpARM64MULW, x.Type) v1.AddArg2(x, y) v0.AddArg2(a, v1) b.resetWithControl(BlockARM64NE, v0) return true } // match: (NE (TSTconst [c] x) yes no) // cond: oneBit(c) // result: (TBNZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64TSTconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (NE (TSTWconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBNZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64TSTWconst { v_0 := b.Controls[0] c := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (NE (FlagConstant [fc]) yes no) // cond: fc.ne() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ne()) { break } b.Reset(BlockFirst) return true } // match: (NE (FlagConstant [fc]) yes no) // cond: !fc.ne() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ne()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NE (InvertFlags cmp) yes no) // result: (NE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64NE, cmp) return true } case BlockARM64NZ: // match: (NZ (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpARM64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64EQ, cc) return true } // match: (NZ (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpARM64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64NE, cc) return true } // match: (NZ (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpARM64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LT, cc) return true } // match: (NZ (LessThanU cc) yes no) // result: (ULT cc yes no) for b.Controls[0].Op == OpARM64LessThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULT, cc) return true } // match: (NZ (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpARM64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64LE, cc) return true } // match: (NZ (LessEqualU cc) yes no) // result: (ULE cc yes no) for b.Controls[0].Op == OpARM64LessEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64ULE, cc) return true } // match: (NZ (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpARM64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GT, cc) return true } // match: (NZ (GreaterThanU cc) yes no) // result: (UGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGT, cc) return true } // match: (NZ (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64GE, cc) return true } // match: (NZ (GreaterEqualU cc) yes no) // result: (UGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64UGE, cc) return true } // match: (NZ (LessThanF cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpARM64LessThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLT, cc) return true } // match: (NZ (LessEqualF cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpARM64LessEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FLE, cc) return true } // match: (NZ (GreaterThanF cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGT, cc) return true } // match: (NZ (GreaterEqualF cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] b.resetWithControl(BlockARM64FGE, cc) return true } // match: (NZ (ANDconst [c] x) yes no) // cond: oneBit(c) // result: (TBNZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (NZ (MOVDconst [0]) yes no) // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NZ (MOVDconst [c]) yes no) // cond: c != 0 // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(c != 0) { break } b.Reset(BlockFirst) return true } case BlockARM64NZW: // match: (NZW (ANDconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBNZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBNZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (NZW (MOVDconst [c]) yes no) // cond: int32(c) == 0 // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) == 0) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (NZW (MOVDconst [c]) yes no) // cond: int32(c) != 0 // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) != 0) { break } b.Reset(BlockFirst) return true } case BlockARM64TBNZ: // match: (TBNZ [0] (Equal cc) yes no) // result: (EQ cc yes no) for b.Controls[0].Op == OpARM64Equal { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64EQ, cc) return true } // match: (TBNZ [0] (NotEqual cc) yes no) // result: (NE cc yes no) for b.Controls[0].Op == OpARM64NotEqual { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64NE, cc) return true } // match: (TBNZ [0] (LessThan cc) yes no) // result: (LT cc yes no) for b.Controls[0].Op == OpARM64LessThan { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64LT, cc) return true } // match: (TBNZ [0] (LessThanU cc) yes no) // result: (ULT cc yes no) for b.Controls[0].Op == OpARM64LessThanU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64ULT, cc) return true } // match: (TBNZ [0] (LessEqual cc) yes no) // result: (LE cc yes no) for b.Controls[0].Op == OpARM64LessEqual { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64LE, cc) return true } // match: (TBNZ [0] (LessEqualU cc) yes no) // result: (ULE cc yes no) for b.Controls[0].Op == OpARM64LessEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64ULE, cc) return true } // match: (TBNZ [0] (GreaterThan cc) yes no) // result: (GT cc yes no) for b.Controls[0].Op == OpARM64GreaterThan { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64GT, cc) return true } // match: (TBNZ [0] (GreaterThanU cc) yes no) // result: (UGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64UGT, cc) return true } // match: (TBNZ [0] (GreaterEqual cc) yes no) // result: (GE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqual { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64GE, cc) return true } // match: (TBNZ [0] (GreaterEqualU cc) yes no) // result: (UGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualU { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64UGE, cc) return true } // match: (TBNZ [0] (LessThanF cc) yes no) // result: (FLT cc yes no) for b.Controls[0].Op == OpARM64LessThanF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FLT, cc) return true } // match: (TBNZ [0] (LessEqualF cc) yes no) // result: (FLE cc yes no) for b.Controls[0].Op == OpARM64LessEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FLE, cc) return true } // match: (TBNZ [0] (GreaterThanF cc) yes no) // result: (FGT cc yes no) for b.Controls[0].Op == OpARM64GreaterThanF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FGT, cc) return true } // match: (TBNZ [0] (GreaterEqualF cc) yes no) // result: (FGE cc yes no) for b.Controls[0].Op == OpARM64GreaterEqualF { v_0 := b.Controls[0] cc := v_0.Args[0] if auxIntToInt64(b.AuxInt) != 0 { break } b.resetWithControl(BlockARM64FGE, cc) return true } case BlockARM64UGE: // match: (UGE (FlagConstant [fc]) yes no) // cond: fc.uge() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.uge()) { break } b.Reset(BlockFirst) return true } // match: (UGE (FlagConstant [fc]) yes no) // cond: !fc.uge() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.uge()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGE (InvertFlags cmp) yes no) // result: (ULE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64ULE, cmp) return true } case BlockARM64UGT: // match: (UGT (FlagConstant [fc]) yes no) // cond: fc.ugt() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ugt()) { break } b.Reset(BlockFirst) return true } // match: (UGT (FlagConstant [fc]) yes no) // cond: !fc.ugt() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ugt()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (UGT (InvertFlags cmp) yes no) // result: (ULT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64ULT, cmp) return true } case BlockARM64ULE: // match: (ULE (FlagConstant [fc]) yes no) // cond: fc.ule() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ule()) { break } b.Reset(BlockFirst) return true } // match: (ULE (FlagConstant [fc]) yes no) // cond: !fc.ule() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ule()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULE (InvertFlags cmp) yes no) // result: (UGE cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64UGE, cmp) return true } case BlockARM64ULT: // match: (ULT (FlagConstant [fc]) yes no) // cond: fc.ult() // result: (First yes no) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(fc.ult()) { break } b.Reset(BlockFirst) return true } // match: (ULT (FlagConstant [fc]) yes no) // cond: !fc.ult() // result: (First no yes) for b.Controls[0].Op == OpARM64FlagConstant { v_0 := b.Controls[0] fc := auxIntToFlagConstant(v_0.AuxInt) if !(!fc.ult()) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } // match: (ULT (InvertFlags cmp) yes no) // result: (UGT cmp yes no) for b.Controls[0].Op == OpARM64InvertFlags { v_0 := b.Controls[0] cmp := v_0.Args[0] b.resetWithControl(BlockARM64UGT, cmp) return true } case BlockARM64Z: // match: (Z (ANDconst [c] x) yes no) // cond: oneBit(c) // result: (TBZ [int64(ntz64(c))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(c)) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(c))) return true } // match: (Z (MOVDconst [0]) yes no) // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } b.Reset(BlockFirst) return true } // match: (Z (MOVDconst [c]) yes no) // cond: c != 0 // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(c != 0) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } case BlockARM64ZW: // match: (ZW (ANDconst [c] x) yes no) // cond: oneBit(int64(uint32(c))) // result: (TBZ [int64(ntz64(int64(uint32(c))))] x yes no) for b.Controls[0].Op == OpARM64ANDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] if !(oneBit(int64(uint32(c)))) { break } b.resetWithControl(BlockARM64TBZ, x) b.AuxInt = int64ToAuxInt(int64(ntz64(int64(uint32(c))))) return true } // match: (ZW (MOVDconst [c]) yes no) // cond: int32(c) == 0 // result: (First yes no) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) == 0) { break } b.Reset(BlockFirst) return true } // match: (ZW (MOVDconst [c]) yes no) // cond: int32(c) != 0 // result: (First no yes) for b.Controls[0].Op == OpARM64MOVDconst { v_0 := b.Controls[0] c := auxIntToInt64(v_0.AuxInt) if !(int32(c) != 0) { break } b.Reset(BlockFirst) b.swapSuccessors() return true } } return false } -- diff -- @@ -545,6 +545,9 @@ return true case OpBitRev8: return rewriteValueARM64_OpBitRev8(v) + case OpBswap16: + v.Op = OpARM64REV16W + return true case OpBswap32: v.Op = OpARM64REVW return true @@ -8726,7 +8729,6 @@ v_0 := v.Args[0] b := v.Block config := b.Func.Config - typ := &b.Func.Config.Types // match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstore [off1+int32(off2)] {sym} ptr val mem) @@ -8910,1327 +8912,6 @@ v.AddArg3(ptr, x, mem) return true } - // match: (MOVBstore [i] {s} ptr0 (SRLconst [8] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] w) x:(MOVBstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { - continue - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr0 (UBFX [armBFAuxInt(8, 8)] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 8) { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 8)] w) x:(MOVBstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 8) { - continue - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr0 (UBFX [armBFAuxInt(8, 24)] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 24) { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 24)] w) x:(MOVBstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 24) { - continue - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr0 (SRLconst [8] (MOVDreg w)) x:(MOVBstore [i-1] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { - break - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - break - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { - continue - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - continue - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVBstore [i-1] {s} ptr1 w0:(SRLconst [j-8] w) mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst { - break - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst { - continue - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr0 (UBFX [bfc] w) x:(MOVBstore [i-1] {s} ptr1 w0:(UBFX [bfc2] w) mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && bfc.getARM64BFwidth() == 32 - bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32 - bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb() - 8 && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64UBFX { - break - } - bfc := auxIntToArm64BitField(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpARM64UBFX { - break - } - bfc2 := auxIntToArm64BitField(w0.AuxInt) - if w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && bfc.getARM64BFwidth() == 32-bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32-bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb()-8 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [bfc] w) x:(MOVBstoreidx ptr1 idx1 w0:(UBFX [bfc2] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && bfc.getARM64BFwidth() == 32 - bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32 - bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb() - 8 && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64UBFX { - continue - } - bfc := auxIntToArm64BitField(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64UBFX { - continue - } - bfc2 := auxIntToArm64BitField(w0.AuxInt) - if w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && bfc.getARM64BFwidth() == 32-bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32-bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb()-8 && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr0 (SRLconst [j] (MOVDreg w)) x:(MOVBstore [i-1] {s} ptr1 w0:(SRLconst [j-8] (MOVDreg w)) mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst { - break - } - j := auxIntToInt64(v_1.AuxInt) - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - break - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 { - break - } - w0_0 := w0.Args[0] - if w0_0.Op != OpARM64MOVDreg || w != w0_0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] (MOVDreg w)) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst { - continue - } - j := auxIntToInt64(v_1.AuxInt) - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - continue - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 { - continue - } - w0_0 := w0.Args[0] - if w0_0.Op != OpARM64MOVDreg || w != w0_0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] w) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] w) x3:(MOVBstore [i-4] {s} ptr (SRLconst [32] w) x4:(MOVBstore [i-5] {s} ptr (SRLconst [40] w) x5:(MOVBstore [i-6] {s} ptr (SRLconst [48] w) x6:(MOVBstore [i-7] {s} ptr (SRLconst [56] w) mem)))))))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6) - // result: (MOVDstore [i-7] {s} ptr (REV w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if ptr != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { - break - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 || w != x2_1.Args[0] { - break - } - x3 := x2.Args[2] - if x3.Op != OpARM64MOVBstore || auxIntToInt32(x3.AuxInt) != i-4 || auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[2] - if ptr != x3.Args[0] { - break - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64SRLconst || auxIntToInt64(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { - break - } - x4 := x3.Args[2] - if x4.Op != OpARM64MOVBstore || auxIntToInt32(x4.AuxInt) != i-5 || auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[2] - if ptr != x4.Args[0] { - break - } - x4_1 := x4.Args[1] - if x4_1.Op != OpARM64SRLconst || auxIntToInt64(x4_1.AuxInt) != 40 || w != x4_1.Args[0] { - break - } - x5 := x4.Args[2] - if x5.Op != OpARM64MOVBstore || auxIntToInt32(x5.AuxInt) != i-6 || auxToSym(x5.Aux) != s { - break - } - _ = x5.Args[2] - if ptr != x5.Args[0] { - break - } - x5_1 := x5.Args[1] - if x5_1.Op != OpARM64SRLconst || auxIntToInt64(x5_1.AuxInt) != 48 || w != x5_1.Args[0] { - break - } - x6 := x5.Args[2] - if x6.Op != OpARM64MOVBstore || auxIntToInt32(x6.AuxInt) != i-7 || auxToSym(x6.Aux) != s { - break - } - mem := x6.Args[2] - if ptr != x6.Args[0] { - break - } - x6_1 := x6.Args[1] - if x6_1.Op != OpARM64SRLconst || auxIntToInt64(x6_1.AuxInt) != 56 || w != x6_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6)) { - break - } - v.reset(OpARM64MOVDstore) - v.AuxInt = int32ToAuxInt(i - 7) - v.Aux = symToAux(s) - v0 := b.NewValue0(x6.Pos, OpARM64REV, typ.UInt64) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [7] {s} p w x0:(MOVBstore [6] {s} p (SRLconst [8] w) x1:(MOVBstore [5] {s} p (SRLconst [16] w) x2:(MOVBstore [4] {s} p (SRLconst [24] w) x3:(MOVBstore [3] {s} p (SRLconst [32] w) x4:(MOVBstore [2] {s} p (SRLconst [40] w) x5:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [48] w) x6:(MOVBstoreidx ptr0 idx0 (SRLconst [56] w) mem)))))))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6) - // result: (MOVDstoreidx ptr0 idx0 (REV w) mem) - for { - if auxIntToInt32(v.AuxInt) != 7 { - break - } - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 6 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 5 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { - break - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != 4 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - if p != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 || w != x2_1.Args[0] { - break - } - x3 := x2.Args[2] - if x3.Op != OpARM64MOVBstore || auxIntToInt32(x3.AuxInt) != 3 || auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[2] - if p != x3.Args[0] { - break - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64SRLconst || auxIntToInt64(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { - break - } - x4 := x3.Args[2] - if x4.Op != OpARM64MOVBstore || auxIntToInt32(x4.AuxInt) != 2 || auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[2] - if p != x4.Args[0] { - break - } - x4_1 := x4.Args[1] - if x4_1.Op != OpARM64SRLconst || auxIntToInt64(x4_1.AuxInt) != 40 || w != x4_1.Args[0] { - break - } - x5 := x4.Args[2] - if x5.Op != OpARM64MOVBstore || auxIntToInt32(x5.AuxInt) != 1 || auxToSym(x5.Aux) != s { - break - } - _ = x5.Args[2] - p1 := x5.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - x5_1 := x5.Args[1] - if x5_1.Op != OpARM64SRLconst || auxIntToInt64(x5_1.AuxInt) != 48 || w != x5_1.Args[0] { - continue - } - x6 := x5.Args[2] - if x6.Op != OpARM64MOVBstoreidx { - continue - } - mem := x6.Args[3] - ptr0 := x6.Args[0] - idx0 := x6.Args[1] - x6_2 := x6.Args[2] - if x6_2.Op != OpARM64SRLconst || auxIntToInt64(x6_2.AuxInt) != 56 || w != x6_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6)) { - continue - } - v.reset(OpARM64MOVDstoreidx) - v0 := b.NewValue0(x5.Pos, OpARM64REV, typ.UInt64) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstore [i-2] {s} ptr (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstore [i-3] {s} ptr (UBFX [armBFAuxInt(24, 8)] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) - // result: (MOVWstore [i-3] {s} ptr (REVW w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if ptr != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64UBFX || auxIntToArm64BitField(x0_1.AuxInt) != armBFAuxInt(8, 24) || w != x0_1.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64UBFX || auxIntToArm64BitField(x1_1.AuxInt) != armBFAuxInt(16, 16) || w != x1_1.Args[0] { - break - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { - break - } - mem := x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64UBFX || auxIntToArm64BitField(x2_1.AuxInt) != armBFAuxInt(24, 8) || w != x2_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 3) - v.Aux = symToAux(s) - v0 := b.NewValue0(x2.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(24, 8)] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2) - // result: (MOVWstoreidx ptr0 idx0 (REVW w) mem) - for { - if auxIntToInt32(v.AuxInt) != 3 { - break - } - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 2 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64UBFX || auxIntToArm64BitField(x0_1.AuxInt) != armBFAuxInt(8, 24) || w != x0_1.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64UBFX || auxIntToArm64BitField(x1_1.AuxInt) != armBFAuxInt(16, 16) || w != x1_1.Args[0] { - continue - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstoreidx { - continue - } - mem := x2.Args[3] - ptr0 := x2.Args[0] - idx0 := x2.Args[1] - x2_2 := x2.Args[2] - if x2_2.Op != OpARM64UBFX || auxIntToArm64BitField(x2_2.AuxInt) != armBFAuxInt(24, 8) || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(x1.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] (MOVDreg w)) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] (MOVDreg w)) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) - // result: (MOVWstore [i-3] {s} ptr (REVW w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if ptr != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 { - break - } - x0_1_0 := x0_1.Args[0] - if x0_1_0.Op != OpARM64MOVDreg || w != x0_1_0.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 { - break - } - x1_1_0 := x1_1.Args[0] - if x1_1_0.Op != OpARM64MOVDreg || w != x1_1_0.Args[0] { - break - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { - break - } - mem := x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 { - break - } - x2_1_0 := x2_1.Args[0] - if x2_1_0.Op != OpARM64MOVDreg || w != x2_1_0.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 3) - v.Aux = symToAux(s) - v0 := b.NewValue0(x2.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] (MOVDreg w)) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] (MOVDreg w)) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] (MOVDreg w)) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2) - // result: (MOVWstoreidx ptr0 idx0 (REVW w) mem) - for { - if auxIntToInt32(v.AuxInt) != 3 { - break - } - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 2 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 { - break - } - x0_1_0 := x0_1.Args[0] - if x0_1_0.Op != OpARM64MOVDreg || w != x0_1_0.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 { - continue - } - x1_1_0 := x1_1.Args[0] - if x1_1_0.Op != OpARM64MOVDreg || w != x1_1_0.Args[0] { - continue - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstoreidx { - continue - } - mem := x2.Args[3] - ptr0 := x2.Args[0] - idx0 := x2.Args[1] - x2_2 := x2.Args[2] - if x2_2.Op != OpARM64SRLconst || auxIntToInt64(x2_2.AuxInt) != 24 { - continue - } - x2_2_0 := x2_2.Args[0] - if x2_2_0.Op != OpARM64MOVDreg || w != x2_2_0.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(x1.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] w) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) - // result: (MOVWstore [i-3] {s} ptr (REVW w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if ptr != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { - break - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { - break - } - mem := x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 || w != x2_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 3) - v.Aux = symToAux(s) - v0 := b.NewValue0(x2.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] w) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2) - // result: (MOVWstoreidx ptr0 idx0 (REVW w) mem) - for { - if auxIntToInt32(v.AuxInt) != 3 { - break - } - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 2 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { - continue - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstoreidx { - continue - } - mem := x2.Args[3] - ptr0 := x2.Args[0] - idx0 := x2.Args[1] - x2_2 := x2.Args[2] - if x2_2.Op != OpARM64SRLconst || auxIntToInt64(x2_2.AuxInt) != 24 || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(x1.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if ptr != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpARM64SRLconst || auxIntToInt64(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr1 := v_0_0 - idx1 := v_0_1 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr0 := x.Args[0] - idx0 := x.Args[1] - x_2 := x.Args[2] - if x_2.Op != OpARM64SRLconst || auxIntToInt64(x_2.AuxInt) != 8 || w != x_2.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 8)] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if ptr != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpARM64UBFX || auxIntToArm64BitField(x_1.AuxInt) != armBFAuxInt(8, 8) || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 8)] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr1 := v_0_0 - idx1 := v_0_1 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr0 := x.Args[0] - idx0 := x.Args[1] - x_2 := x.Args[2] - if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 8) || w != x_2.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if ptr != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpARM64SRLconst || auxIntToInt64(x_1.AuxInt) != 8 { - break - } - x_1_0 := x_1.Args[0] - if x_1_0.Op != OpARM64MOVDreg || w != x_1_0.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] (MOVDreg w)) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr1 := v_0_0 - idx1 := v_0_1 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr0 := x.Args[0] - idx0 := x.Args[1] - x_2 := x.Args[2] - if x_2.Op != OpARM64SRLconst || auxIntToInt64(x_2.AuxInt) != 8 { - continue - } - x_2_0 := x_2.Args[0] - if x_2_0.Op != OpARM64MOVDreg || w != x_2_0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 24)] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if ptr != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpARM64UBFX || auxIntToArm64BitField(x_1.AuxInt) != armBFAuxInt(8, 24) || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 24)] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr1 := v_0_0 - idx1 := v_0_1 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr0 := x.Args[0] - idx0 := x.Args[1] - x_2 := x.Args[2] - if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 24) || w != x_2.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } return false } func rewriteValueARM64_OpARM64MOVBstoreidx(v *Value) bool { @@ -10238,8 +8919,6 @@ v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types // match: (MOVBstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVBstore [int32(c)] ptr val mem) @@ -10375,205 +9054,6 @@ v.AddArg4(ptr, idx, x, mem) return true } - // match: (MOVBstoreidx ptr (ADDconst [1] idx) (SRLconst [8] w) x:(MOVBstoreidx ptr idx w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstoreidx ptr idx w mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { - break - } - idx := v_1.Args[0] - if v_2.Op != OpARM64SRLconst || auxIntToInt64(v_2.AuxInt) != 8 { - break - } - w := v_2.Args[0] - x := v_3 - if x.Op != OpARM64MOVBstoreidx { - break - } - mem := x.Args[3] - if ptr != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr, idx, w, mem) - return true - } - // match: (MOVBstoreidx ptr (ADDconst [3] idx) w x0:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(24, 8)] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) - // result: (MOVWstoreidx ptr idx (REVW w) mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 3 { - break - } - idx := v_1.Args[0] - w := v_2 - x0 := v_3 - if x0.Op != OpARM64MOVBstoreidx { - break - } - _ = x0.Args[3] - if ptr != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 2 || idx != x0_1.Args[0] { - break - } - x0_2 := x0.Args[2] - if x0_2.Op != OpARM64UBFX || auxIntToArm64BitField(x0_2.AuxInt) != armBFAuxInt(8, 24) || w != x0_2.Args[0] { - break - } - x1 := x0.Args[3] - if x1.Op != OpARM64MOVBstoreidx { - break - } - _ = x1.Args[3] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] { - break - } - x1_2 := x1.Args[2] - if x1_2.Op != OpARM64UBFX || auxIntToArm64BitField(x1_2.AuxInt) != armBFAuxInt(16, 16) || w != x1_2.Args[0] { - break - } - x2 := x1.Args[3] - if x2.Op != OpARM64MOVBstoreidx { - break - } - mem := x2.Args[3] - if ptr != x2.Args[0] || idx != x2.Args[1] { - break - } - x2_2 := x2.Args[2] - if x2_2.Op != OpARM64UBFX || auxIntToArm64BitField(x2_2.AuxInt) != armBFAuxInt(24, 8) || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg4(ptr, idx, v0, mem) - return true - } - // match: (MOVBstoreidx ptr idx w x0:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr (ADDconst [3] idx) (UBFX [armBFAuxInt(24, 8)] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) - // result: (MOVWstoreidx ptr idx w mem) - for { - ptr := v_0 - idx := v_1 - w := v_2 - x0 := v_3 - if x0.Op != OpARM64MOVBstoreidx { - break - } - _ = x0.Args[3] - if ptr != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 1 || idx != x0_1.Args[0] { - break - } - x0_2 := x0.Args[2] - if x0_2.Op != OpARM64UBFX || auxIntToArm64BitField(x0_2.AuxInt) != armBFAuxInt(8, 24) || w != x0_2.Args[0] { - break - } - x1 := x0.Args[3] - if x1.Op != OpARM64MOVBstoreidx { - break - } - _ = x1.Args[3] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 2 || idx != x1_1.Args[0] { - break - } - x1_2 := x1.Args[2] - if x1_2.Op != OpARM64UBFX || auxIntToArm64BitField(x1_2.AuxInt) != armBFAuxInt(16, 16) || w != x1_2.Args[0] { - break - } - x2 := x1.Args[3] - if x2.Op != OpARM64MOVBstoreidx { - break - } - mem := x2.Args[3] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 3 || idx != x2_1.Args[0] { - break - } - x2_2 := x2.Args[2] - if x2_2.Op != OpARM64UBFX || auxIntToArm64BitField(x2_2.AuxInt) != armBFAuxInt(24, 8) || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v.AddArg4(ptr, idx, w, mem) - return true - } - // match: (MOVBstoreidx ptr (ADDconst [1] idx) w x:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(8, 8)] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstoreidx ptr idx (REV16W w) mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { - break - } - idx := v_1.Args[0] - w := v_2 - x := v_3 - if x.Op != OpARM64MOVBstoreidx { - break - } - mem := x.Args[3] - if ptr != x.Args[0] || idx != x.Args[1] { - break - } - x_2 := x.Args[2] - if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 8) || w != x_2.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg4(ptr, idx, v0, mem) - return true - } - // match: (MOVBstoreidx ptr idx w x:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 8)] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstoreidx ptr idx w mem) - for { - ptr := v_0 - idx := v_1 - w := v_2 - x := v_3 - if x.Op != OpARM64MOVBstoreidx { - break - } - mem := x.Args[3] - if ptr != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpARM64ADDconst || auxIntToInt64(x_1.AuxInt) != 1 || idx != x_1.Args[0] { - break - } - x_2 := x.Args[2] - if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 8) || w != x_2.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr, idx, w, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVBstorezero(v *Value) bool { @@ -10643,65 +9123,6 @@ v.AddArg3(ptr, idx, mem) return true } - // match: (MOVBstorezero [i] {s} ptr0 x:(MOVBstorezero [j] {s} ptr1 mem)) - // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),1) && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - x := v_1 - if x.Op != OpARM64MOVBstorezero { - break - } - j := auxIntToInt32(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - ptr1 := x.Args[0] - if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 1) && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstorezero) - v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) - v.Aux = symToAux(s) - v.AddArg2(ptr0, mem) - return true - } - // match: (MOVBstorezero [1] {s} (ADD ptr0 idx0) x:(MOVBstorezeroidx ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstorezeroidx ptr1 idx1 mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - x := v_1 - if x.Op != OpARM64MOVBstorezeroidx { - continue - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstorezeroidx) - v.AddArg3(ptr1, idx1, mem) - return true - } - break - } return false } func rewriteValueARM64_OpARM64MOVBstorezeroidx(v *Value) bool { @@ -10744,27 +9165,6 @@ v.AddArg2(idx, mem) return true } - // match: (MOVBstorezeroidx ptr (ADDconst [1] idx) x:(MOVBstorezeroidx ptr idx mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstorezeroidx ptr idx mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { - break - } - idx := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstorezeroidx { - break - } - mem := x.Args[2] - if ptr != x.Args[0] || idx != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstorezeroidx) - v.AddArg3(ptr, idx, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVDload(v *Value) bool { @@ -11331,6 +9731,48 @@ v_0 := v.Args[0] b := v.Block config := b.Func.Config + // match: (MOVDstorezero {s} [i] ptr x:(MOVDstorezero {s} [i+8] ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVQstorezero {s} [i] ptr mem) + for { + i := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + ptr := v_0 + x := v_1 + if x.Op != OpARM64MOVDstorezero || auxIntToInt32(x.AuxInt) != i+8 || auxToSym(x.Aux) != s { + break + } + mem := x.Args[1] + if ptr != x.Args[0] || !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(OpARM64MOVQstorezero) + v.AuxInt = int32ToAuxInt(i) + v.Aux = symToAux(s) + v.AddArg2(ptr, mem) + return true + } + // match: (MOVDstorezero {s} [i] ptr x:(MOVDstorezero {s} [i-8] ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVQstorezero {s} [i-8] ptr mem) + for { + i := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + ptr := v_0 + x := v_1 + if x.Op != OpARM64MOVDstorezero || auxIntToInt32(x.AuxInt) != i-8 || auxToSym(x.Aux) != s { + break + } + mem := x.Args[1] + if ptr != x.Args[0] || !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(OpARM64MOVQstorezero) + v.AuxInt = int32ToAuxInt(i - 8) + v.Aux = symToAux(s) + v.AddArg2(ptr, mem) + return true + } // match: (MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstorezero [off1+int32(off2)] {sym} ptr mem) @@ -11412,98 +9854,6 @@ v.AddArg3(ptr, idx, mem) return true } - // match: (MOVDstorezero [i] {s} ptr0 x:(MOVDstorezero [j] {s} ptr1 mem)) - // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),8) && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVQstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - x := v_1 - if x.Op != OpARM64MOVDstorezero { - break - } - j := auxIntToInt32(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - ptr1 := x.Args[0] - if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 8) && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVQstorezero) - v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) - v.Aux = symToAux(s) - v.AddArg2(ptr0, mem) - return true - } - // match: (MOVDstorezero [8] {s} p0:(ADD ptr0 idx0) x:(MOVDstorezeroidx ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVQstorezero [0] {s} p0 mem) - for { - if auxIntToInt32(v.AuxInt) != 8 { - break - } - s := auxToSym(v.Aux) - p0 := v_0 - if p0.Op != OpARM64ADD { - break - } - _ = p0.Args[1] - p0_0 := p0.Args[0] - p0_1 := p0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p0_0, p0_1 = _i0+1, p0_1, p0_0 { - ptr0 := p0_0 - idx0 := p0_1 - x := v_1 - if x.Op != OpARM64MOVDstorezeroidx { - continue - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVQstorezero) - v.AuxInt = int32ToAuxInt(0) - v.Aux = symToAux(s) - v.AddArg2(p0, mem) - return true - } - break - } - // match: (MOVDstorezero [8] {s} p0:(ADDshiftLL [3] ptr0 idx0) x:(MOVDstorezeroidx8 ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVQstorezero [0] {s} p0 mem) - for { - if auxIntToInt32(v.AuxInt) != 8 { - break - } - s := auxToSym(v.Aux) - p0 := v_0 - if p0.Op != OpARM64ADDshiftLL || auxIntToInt64(p0.AuxInt) != 3 { - break - } - idx0 := p0.Args[1] - ptr0 := p0.Args[0] - x := v_1 - if x.Op != OpARM64MOVDstorezeroidx8 { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVQstorezero) - v.AuxInt = int32ToAuxInt(0) - v.Aux = symToAux(s) - v.AddArg2(p0, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVDstorezeroidx(v *Value) bool { @@ -12645,412 +10995,6 @@ v.AddArg3(ptr, x, mem) return true } - // match: (MOVHstore [i] {s} ptr0 (SRLconst [16] w) x:(MOVHstore [i-2] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVWstore [i-2] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [16] w) x:(MOVHstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVWstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { - continue - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [16] w) x:(MOVHstoreidx2 ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx2 { - break - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(1) - v0.AddArg(idx1) - v.AddArg4(ptr1, v0, w, mem) - return true - } - // match: (MOVHstore [i] {s} ptr0 (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstore [i-2] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVWstore [i-2] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(16, 16) { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVWstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(16, 16) { - continue - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstoreidx2 ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(16, 16) { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx2 { - break - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(1) - v0.AddArg(idx1) - v.AddArg4(ptr1, v0, w, mem) - return true - } - // match: (MOVHstore [i] {s} ptr0 (SRLconst [16] (MOVDreg w)) x:(MOVHstore [i-2] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVWstore [i-2] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { - break - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - break - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [16] (MOVDreg w)) x:(MOVHstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVWstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { - continue - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - continue - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [16] (MOVDreg w)) x:(MOVHstoreidx2 ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { - break - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - break - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx2 { - break - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(1) - v0.AddArg(idx1) - v.AddArg4(ptr1, v0, w, mem) - return true - } - // match: (MOVHstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVHstore [i-2] {s} ptr1 w0:(SRLconst [j-16] w) mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVWstore [i-2] {s} ptr0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst { - break - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w0, mem) - return true - } - // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVHstoreidx ptr1 idx1 w0:(SRLconst [j-16] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVWstoreidx ptr1 idx1 w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst { - continue - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v.AddArg4(ptr1, idx1, w0, mem) - return true - } - break - } - // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [j] w) x:(MOVHstoreidx2 ptr1 idx1 w0:(SRLconst [j-16] w) mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - if v_1.Op != OpARM64SRLconst { - break - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx2 { - break - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(1) - v0.AddArg(idx1) - v.AddArg4(ptr1, v0, w0, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVHstoreidx(v *Value) bool { @@ -13227,31 +11171,6 @@ v.AddArg4(ptr, idx, x, mem) return true } - // match: (MOVHstoreidx ptr (ADDconst [2] idx) (SRLconst [16] w) x:(MOVHstoreidx ptr idx w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstoreidx ptr idx w mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 2 { - break - } - idx := v_1.Args[0] - if v_2.Op != OpARM64SRLconst || auxIntToInt64(v_2.AuxInt) != 16 { - break - } - w := v_2.Args[0] - x := v_3 - if x.Op != OpARM64MOVHstoreidx { - break - } - mem := x.Args[3] - if ptr != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v.AddArg4(ptr, idx, w, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVHstoreidx2(v *Value) bool { @@ -13435,95 +11354,6 @@ v.AddArg3(ptr, idx, mem) return true } - // match: (MOVHstorezero [i] {s} ptr0 x:(MOVHstorezero [j] {s} ptr1 mem)) - // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),2) && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVWstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - x := v_1 - if x.Op != OpARM64MOVHstorezero { - break - } - j := auxIntToInt32(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - ptr1 := x.Args[0] - if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 2) && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstorezero) - v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) - v.Aux = symToAux(s) - v.AddArg2(ptr0, mem) - return true - } - // match: (MOVHstorezero [2] {s} (ADD ptr0 idx0) x:(MOVHstorezeroidx ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVWstorezeroidx ptr1 idx1 mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - x := v_1 - if x.Op != OpARM64MOVHstorezeroidx { - continue - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVWstorezeroidx) - v.AddArg3(ptr1, idx1, mem) - return true - } - break - } - // match: (MOVHstorezero [2] {s} (ADDshiftLL [1] ptr0 idx0) x:(MOVHstorezeroidx2 ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVWstorezeroidx ptr1 (SLLconst [1] idx1) mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - x := v_1 - if x.Op != OpARM64MOVHstorezeroidx2 { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstorezeroidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(1) - v0.AddArg(idx1) - v.AddArg3(ptr1, v0, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVHstorezeroidx(v *Value) bool { @@ -13624,27 +11454,6 @@ v.AddArg3(ptr, idx, mem) return true } - // match: (MOVHstorezeroidx ptr (ADDconst [2] idx) x:(MOVHstorezeroidx ptr idx mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstorezeroidx ptr idx mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 2 { - break - } - idx := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstorezeroidx { - break - } - mem := x.Args[2] - if ptr != x.Args[0] || idx != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVWstorezeroidx) - v.AddArg3(ptr, idx, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVHstorezeroidx2(v *Value) bool { @@ -14862,206 +12671,6 @@ v.AddArg3(ptr, x, mem) return true } - // match: (MOVWstore [i] {s} ptr0 (SRLconst [32] w) x:(MOVWstore [i-4] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVDstore [i-4] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 32 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVDstore) - v.AuxInt = int32ToAuxInt(i - 4) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVWstore [4] {s} (ADD ptr0 idx0) (SRLconst [32] w) x:(MOVWstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVDstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 4 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 32 { - continue - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVDstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVWstore [4] {s} (ADDshiftLL [2] ptr0 idx0) (SRLconst [32] w) x:(MOVWstoreidx4 ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVDstoreidx ptr1 (SLLconst [2] idx1) w mem) - for { - if auxIntToInt32(v.AuxInt) != 4 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 32 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstoreidx4 { - break - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVDstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(2) - v0.AddArg(idx1) - v.AddArg4(ptr1, v0, w, mem) - return true - } - // match: (MOVWstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVWstore [i-4] {s} ptr1 w0:(SRLconst [j-32] w) mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVDstore [i-4] {s} ptr0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst { - break - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVDstore) - v.AuxInt = int32ToAuxInt(i - 4) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w0, mem) - return true - } - // match: (MOVWstore [4] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVWstoreidx ptr1 idx1 w0:(SRLconst [j-32] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVDstoreidx ptr1 idx1 w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 4 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst { - continue - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVDstoreidx) - v.AddArg4(ptr1, idx1, w0, mem) - return true - } - break - } - // match: (MOVWstore [4] {s} (ADDshiftLL [2] ptr0 idx0) (SRLconst [j] w) x:(MOVWstoreidx4 ptr1 idx1 w0:(SRLconst [j-32] w) mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVDstoreidx ptr1 (SLLconst [2] idx1) w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 4 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - if v_1.Op != OpARM64SRLconst { - break - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstoreidx4 { - break - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVDstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(2) - v0.AddArg(idx1) - v.AddArg4(ptr1, v0, w0, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVWstoreidx(v *Value) bool { @@ -15176,31 +12785,6 @@ v.AddArg4(ptr, idx, x, mem) return true } - // match: (MOVWstoreidx ptr (ADDconst [4] idx) (SRLconst [32] w) x:(MOVWstoreidx ptr idx w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVDstoreidx ptr idx w mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 4 { - break - } - idx := v_1.Args[0] - if v_2.Op != OpARM64SRLconst || auxIntToInt64(v_2.AuxInt) != 32 { - break - } - w := v_2.Args[0] - x := v_3 - if x.Op != OpARM64MOVWstoreidx { - break - } - mem := x.Args[3] - if ptr != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVDstoreidx) - v.AddArg4(ptr, idx, w, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVWstoreidx4(v *Value) bool { @@ -15356,95 +12940,6 @@ v.AddArg3(ptr, idx, mem) return true } - // match: (MOVWstorezero [i] {s} ptr0 x:(MOVWstorezero [j] {s} ptr1 mem)) - // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),4) && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVDstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - x := v_1 - if x.Op != OpARM64MOVWstorezero { - break - } - j := auxIntToInt32(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - ptr1 := x.Args[0] - if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 4) && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVDstorezero) - v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) - v.Aux = symToAux(s) - v.AddArg2(ptr0, mem) - return true - } - // match: (MOVWstorezero [4] {s} (ADD ptr0 idx0) x:(MOVWstorezeroidx ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVDstorezeroidx ptr1 idx1 mem) - for { - if auxIntToInt32(v.AuxInt) != 4 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - x := v_1 - if x.Op != OpARM64MOVWstorezeroidx { - continue - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVDstorezeroidx) - v.AddArg3(ptr1, idx1, mem) - return true - } - break - } - // match: (MOVWstorezero [4] {s} (ADDshiftLL [2] ptr0 idx0) x:(MOVWstorezeroidx4 ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVDstorezeroidx ptr1 (SLLconst [2] idx1) mem) - for { - if auxIntToInt32(v.AuxInt) != 4 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - x := v_1 - if x.Op != OpARM64MOVWstorezeroidx4 { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVDstorezeroidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(2) - v0.AddArg(idx1) - v.AddArg3(ptr1, v0, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVWstorezeroidx(v *Value) bool { @@ -15513,27 +13008,6 @@ v.AddArg3(ptr, idx, mem) return true } - // match: (MOVWstorezeroidx ptr (ADDconst [4] idx) x:(MOVWstorezeroidx ptr idx mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVDstorezeroidx ptr idx mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 4 { - break - } - idx := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstorezeroidx { - break - } - mem := x.Args[2] - if ptr != x.Args[0] || idx != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVDstorezeroidx) - v.AddArg3(ptr, idx, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVWstorezeroidx4(v *Value) bool { @@ -17529,7 +15003,6 @@ func rewriteValueARM64_OpARM64OR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block // match: (OR x (MOVDconst [c])) // result: (ORconst [c] x) for { @@ -17709,1558 +15182,6 @@ } break } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [i3] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i1] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i0] {s} p mem))) - // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) - // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUload {s} (OffPtr [int64(i0)] p) mem) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - s0 := o1.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload { - continue - } - i3 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o1.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - continue - } - i2 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y2 := o0.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - continue - } - i1 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - continue - } - y3 := v_1 - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload { - continue - } - i0 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3) - v0 := b.NewValue0(x3.Pos, OpARM64MOVWUload, t) - v.copyOf(v0) - v0.Aux = symToAux(s) - v1 := b.NewValue0(x3.Pos, OpOffPtr, p.Type) - v1.AuxInt = int64ToAuxInt(int64(i0)) - v1.AddArg(p) - v0.AddArg2(v1, mem) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [3] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr0 idx0 mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) - // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUloadidx ptr0 idx0 mem) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - s0 := o1.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload || auxIntToInt32(x0.AuxInt) != 3 { - continue - } - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o1.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 2 || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y2 := o0.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 1 || auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - p1 := x2.Args[0] - if p1.Op != OpARM64ADD { - continue - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x2.Args[1] { - continue - } - y3 := v_1 - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - continue - } - _ = x3.Args[2] - ptr0 := x3.Args[0] - idx0 := x3.Args[1] - if mem != x3.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3) - v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr0, idx0, mem) - return true - } - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr idx mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) - // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUloadidx ptr idx mem) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - s0 := o1.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - continue - } - mem := x0.Args[2] - ptr := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 3 { - continue - } - idx := x0_1.Args[0] - y1 := o1.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - continue - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - continue - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 2 || idx != x1_1.Args[0] || mem != x1.Args[2] { - continue - } - y2 := o0.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - continue - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - continue - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 1 || idx != x2_1.Args[0] || mem != x2.Args[2] { - continue - } - y3 := v_1 - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - continue - } - _ = x3.Args[2] - if ptr != x3.Args[0] || idx != x3.Args[1] || mem != x3.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3) - v0 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr, idx, mem) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUload [i7] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i6] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i4] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i3] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [i2] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [i1] {s} p mem))) y7:(MOVDnop x7:(MOVBUload [i0] {s} p mem))) - // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) - // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} (OffPtr [int64(i0)] p) mem) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { - continue - } - _ = o2.Args[1] - o3 := o2.Args[0] - if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { - continue - } - _ = o3.Args[1] - o4 := o3.Args[0] - if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { - continue - } - _ = o4.Args[1] - o5 := o4.Args[0] - if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { - continue - } - _ = o5.Args[1] - s0 := o5.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload { - continue - } - i7 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o5.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - continue - } - i6 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y2 := o4.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - continue - } - i5 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - continue - } - y3 := o3.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload { - continue - } - i4 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - continue - } - y4 := o2.Args[1] - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload { - continue - } - i3 := auxIntToInt32(x4.AuxInt) - if auxToSym(x4.Aux) != s { - continue - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - continue - } - y5 := o1.Args[1] - if y5.Op != OpARM64MOVDnop { - continue - } - x5 := y5.Args[0] - if x5.Op != OpARM64MOVBUload { - continue - } - i2 := auxIntToInt32(x5.AuxInt) - if auxToSym(x5.Aux) != s { - continue - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - continue - } - y6 := o0.Args[1] - if y6.Op != OpARM64MOVDnop { - continue - } - x6 := y6.Args[0] - if x6.Op != OpARM64MOVBUload { - continue - } - i1 := auxIntToInt32(x6.AuxInt) - if auxToSym(x6.Aux) != s { - continue - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - continue - } - y7 := v_1 - if y7.Op != OpARM64MOVDnop { - continue - } - x7 := y7.Args[0] - if x7.Op != OpARM64MOVBUload { - continue - } - i0 := auxIntToInt32(x7.AuxInt) - if auxToSym(x7.Aux) != s { - continue - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpARM64MOVDload, t) - v.copyOf(v0) - v0.Aux = symToAux(s) - v1 := b.NewValue0(x7.Pos, OpOffPtr, p.Type) - v1.AuxInt = int64ToAuxInt(int64(i0)) - v1.AddArg(p) - v0.AddArg2(v1, mem) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUload [7] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [6] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [4] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [3] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [2] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y7:(MOVDnop x7:(MOVBUloadidx ptr0 idx0 mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) - // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDloadidx ptr0 idx0 mem) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { - continue - } - _ = o2.Args[1] - o3 := o2.Args[0] - if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { - continue - } - _ = o3.Args[1] - o4 := o3.Args[0] - if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { - continue - } - _ = o4.Args[1] - o5 := o4.Args[0] - if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { - continue - } - _ = o5.Args[1] - s0 := o5.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload || auxIntToInt32(x0.AuxInt) != 7 { - continue - } - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o5.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 6 || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y2 := o4.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 5 || auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - continue - } - y3 := o3.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 4 || auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - continue - } - y4 := o2.Args[1] - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 3 || auxToSym(x4.Aux) != s { - continue - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - continue - } - y5 := o1.Args[1] - if y5.Op != OpARM64MOVDnop { - continue - } - x5 := y5.Args[0] - if x5.Op != OpARM64MOVBUload || auxIntToInt32(x5.AuxInt) != 2 || auxToSym(x5.Aux) != s { - continue - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - continue - } - y6 := o0.Args[1] - if y6.Op != OpARM64MOVDnop { - continue - } - x6 := y6.Args[0] - if x6.Op != OpARM64MOVBUload || auxIntToInt32(x6.AuxInt) != 1 || auxToSym(x6.Aux) != s { - continue - } - _ = x6.Args[1] - p1 := x6.Args[0] - if p1.Op != OpARM64ADD { - continue - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x6.Args[1] { - continue - } - y7 := v_1 - if y7.Op != OpARM64MOVDnop { - continue - } - x7 := y7.Args[0] - if x7.Op != OpARM64MOVBUloadidx { - continue - } - _ = x7.Args[2] - ptr0 := x7.Args[0] - idx0 := x7.Args[1] - if mem != x7.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpARM64MOVDloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr0, idx0, mem) - return true - } - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [7] idx) mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [6] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [5] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [4] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y5:(MOVDnop x5:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y6:(MOVDnop x6:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y7:(MOVDnop x7:(MOVBUloadidx ptr idx mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) - // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDloadidx ptr idx mem) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { - continue - } - _ = o2.Args[1] - o3 := o2.Args[0] - if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { - continue - } - _ = o3.Args[1] - o4 := o3.Args[0] - if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { - continue - } - _ = o4.Args[1] - o5 := o4.Args[0] - if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { - continue - } - _ = o5.Args[1] - s0 := o5.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - continue - } - mem := x0.Args[2] - ptr := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 7 { - continue - } - idx := x0_1.Args[0] - y1 := o5.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - continue - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - continue - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 6 || idx != x1_1.Args[0] || mem != x1.Args[2] { - continue - } - y2 := o4.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - continue - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - continue - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 5 || idx != x2_1.Args[0] || mem != x2.Args[2] { - continue - } - y3 := o3.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - continue - } - _ = x3.Args[2] - if ptr != x3.Args[0] { - continue - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 4 || idx != x3_1.Args[0] || mem != x3.Args[2] { - continue - } - y4 := o2.Args[1] - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUloadidx { - continue - } - _ = x4.Args[2] - if ptr != x4.Args[0] { - continue - } - x4_1 := x4.Args[1] - if x4_1.Op != OpARM64ADDconst || auxIntToInt64(x4_1.AuxInt) != 3 || idx != x4_1.Args[0] || mem != x4.Args[2] { - continue - } - y5 := o1.Args[1] - if y5.Op != OpARM64MOVDnop { - continue - } - x5 := y5.Args[0] - if x5.Op != OpARM64MOVBUloadidx { - continue - } - _ = x5.Args[2] - if ptr != x5.Args[0] { - continue - } - x5_1 := x5.Args[1] - if x5_1.Op != OpARM64ADDconst || auxIntToInt64(x5_1.AuxInt) != 2 || idx != x5_1.Args[0] || mem != x5.Args[2] { - continue - } - y6 := o0.Args[1] - if y6.Op != OpARM64MOVDnop { - continue - } - x6 := y6.Args[0] - if x6.Op != OpARM64MOVBUloadidx { - continue - } - _ = x6.Args[2] - if ptr != x6.Args[0] { - continue - } - x6_1 := x6.Args[1] - if x6_1.Op != OpARM64ADDconst || auxIntToInt64(x6_1.AuxInt) != 1 || idx != x6_1.Args[0] || mem != x6.Args[2] { - continue - } - y7 := v_1 - if y7.Op != OpARM64MOVDnop { - continue - } - x7 := y7.Args[0] - if x7.Op != OpARM64MOVBUloadidx { - continue - } - _ = x7.Args[2] - if ptr != x7.Args[0] || idx != x7.Args[1] || mem != x7.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) - v0 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr, idx, mem) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [i0] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i3] {s} p mem))) - // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) - // result: @mergePoint(b,x0,x1,x2,x3) (REVW (MOVWUload {s} (OffPtr [int64(i0)] p) mem)) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - s0 := o1.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o1.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y2 := o0.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - continue - } - i2 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - continue - } - y3 := v_1 - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload { - continue - } - i3 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3) - v0 := b.NewValue0(x3.Pos, OpARM64REVW, t) - v.copyOf(v0) - v1 := b.NewValue0(x3.Pos, OpARM64MOVWUload, t) - v1.Aux = symToAux(s) - v2 := b.NewValue0(x3.Pos, OpOffPtr, p.Type) - v2.AuxInt = int64ToAuxInt(int64(i0)) - v2.AddArg(p) - v1.AddArg2(v2, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr0 idx0 mem))) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [3] {s} p mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) - // result: @mergePoint(b,x0,x1,x2,x3) (REVW (MOVWUloadidx ptr0 idx0 mem)) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - s0 := o1.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - continue - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := o1.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 { - continue - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - continue - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x1.Args[1] { - continue - } - y2 := o0.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 2 || auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - p := x2.Args[0] - if mem != x2.Args[1] { - continue - } - y3 := v_1 - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 3 || auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3) - v0 := b.NewValue0(x3.Pos, OpARM64REVW, t) - v.copyOf(v0) - v1 := b.NewValue0(x3.Pos, OpARM64MOVWUloadidx, t) - v1.AddArg3(ptr0, idx0, mem) - v0.AddArg(v1) - return true - } - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr idx mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) - // result: @mergePoint(b,x0,x1,x2,x3) (REVW (MOVWUloadidx ptr idx mem)) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - s0 := o1.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - continue - } - mem := x0.Args[2] - ptr := x0.Args[0] - idx := x0.Args[1] - y1 := o1.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - continue - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - continue - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] { - continue - } - y2 := o0.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - continue - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - continue - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 2 || idx != x2_1.Args[0] || mem != x2.Args[2] { - continue - } - y3 := v_1 - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - continue - } - _ = x3.Args[2] - if ptr != x3.Args[0] { - continue - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 3 || idx != x3_1.Args[0] || mem != x3.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3) - v0 := b.NewValue0(v.Pos, OpARM64REVW, t) - v.copyOf(v0) - v1 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) - v1.AddArg3(ptr, idx, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUload [i0] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i3] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i4] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [i5] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [i6] {s} p mem))) y7:(MOVDnop x7:(MOVBUload [i7] {s} p mem))) - // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) - // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (REV (MOVDload {s} (OffPtr [int64(i0)] p) mem)) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { - continue - } - _ = o2.Args[1] - o3 := o2.Args[0] - if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { - continue - } - _ = o3.Args[1] - o4 := o3.Args[0] - if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { - continue - } - _ = o4.Args[1] - o5 := o4.Args[0] - if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { - continue - } - _ = o5.Args[1] - s0 := o5.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o5.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y2 := o4.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - continue - } - i2 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - continue - } - y3 := o3.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload { - continue - } - i3 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - continue - } - y4 := o2.Args[1] - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload { - continue - } - i4 := auxIntToInt32(x4.AuxInt) - if auxToSym(x4.Aux) != s { - continue - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - continue - } - y5 := o1.Args[1] - if y5.Op != OpARM64MOVDnop { - continue - } - x5 := y5.Args[0] - if x5.Op != OpARM64MOVBUload { - continue - } - i5 := auxIntToInt32(x5.AuxInt) - if auxToSym(x5.Aux) != s { - continue - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - continue - } - y6 := o0.Args[1] - if y6.Op != OpARM64MOVDnop { - continue - } - x6 := y6.Args[0] - if x6.Op != OpARM64MOVBUload { - continue - } - i6 := auxIntToInt32(x6.AuxInt) - if auxToSym(x6.Aux) != s { - continue - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - continue - } - y7 := v_1 - if y7.Op != OpARM64MOVDnop { - continue - } - x7 := y7.Args[0] - if x7.Op != OpARM64MOVBUload { - continue - } - i7 := auxIntToInt32(x7.AuxInt) - if auxToSym(x7.Aux) != s { - continue - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpARM64REV, t) - v.copyOf(v0) - v1 := b.NewValue0(x7.Pos, OpARM64MOVDload, t) - v1.Aux = symToAux(s) - v2 := b.NewValue0(x7.Pos, OpOffPtr, p.Type) - v2.AuxInt = int64ToAuxInt(int64(i0)) - v2.AddArg(p) - v1.AddArg2(v2, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUloadidx ptr0 idx0 mem))) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [3] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [4] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [5] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [6] {s} p mem))) y7:(MOVDnop x7:(MOVBUload [7] {s} p mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) - // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (REV (MOVDloadidx ptr0 idx0 mem)) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { - continue - } - _ = o2.Args[1] - o3 := o2.Args[0] - if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { - continue - } - _ = o3.Args[1] - o4 := o3.Args[0] - if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { - continue - } - _ = o4.Args[1] - o5 := o4.Args[0] - if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { - continue - } - _ = o5.Args[1] - s0 := o5.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - continue - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := o5.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 { - continue - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - continue - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x1.Args[1] { - continue - } - y2 := o4.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 2 || auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - p := x2.Args[0] - if mem != x2.Args[1] { - continue - } - y3 := o3.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 3 || auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - continue - } - y4 := o2.Args[1] - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 4 || auxToSym(x4.Aux) != s { - continue - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - continue - } - y5 := o1.Args[1] - if y5.Op != OpARM64MOVDnop { - continue - } - x5 := y5.Args[0] - if x5.Op != OpARM64MOVBUload || auxIntToInt32(x5.AuxInt) != 5 || auxToSym(x5.Aux) != s { - continue - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - continue - } - y6 := o0.Args[1] - if y6.Op != OpARM64MOVDnop { - continue - } - x6 := y6.Args[0] - if x6.Op != OpARM64MOVBUload || auxIntToInt32(x6.AuxInt) != 6 || auxToSym(x6.Aux) != s { - continue - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - continue - } - y7 := v_1 - if y7.Op != OpARM64MOVDnop { - continue - } - x7 := y7.Args[0] - if x7.Op != OpARM64MOVBUload || auxIntToInt32(x7.AuxInt) != 7 || auxToSym(x7.Aux) != s { - continue - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpARM64REV, t) - v.copyOf(v0) - v1 := b.NewValue0(x7.Pos, OpARM64MOVDloadidx, t) - v1.AddArg3(ptr0, idx0, mem) - v0.AddArg(v1) - return true - } - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUloadidx ptr idx mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr (ADDconst [4] idx) mem))) y5:(MOVDnop x5:(MOVBUloadidx ptr (ADDconst [5] idx) mem))) y6:(MOVDnop x6:(MOVBUloadidx ptr (ADDconst [6] idx) mem))) y7:(MOVDnop x7:(MOVBUloadidx ptr (ADDconst [7] idx) mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) - // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (REV (MOVDloadidx ptr idx mem)) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { - continue - } - _ = o2.Args[1] - o3 := o2.Args[0] - if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { - continue - } - _ = o3.Args[1] - o4 := o3.Args[0] - if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { - continue - } - _ = o4.Args[1] - o5 := o4.Args[0] - if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { - continue - } - _ = o5.Args[1] - s0 := o5.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - continue - } - mem := x0.Args[2] - ptr := x0.Args[0] - idx := x0.Args[1] - y1 := o5.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - continue - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - continue - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] { - continue - } - y2 := o4.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - continue - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - continue - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 2 || idx != x2_1.Args[0] || mem != x2.Args[2] { - continue - } - y3 := o3.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - continue - } - _ = x3.Args[2] - if ptr != x3.Args[0] { - continue - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 3 || idx != x3_1.Args[0] || mem != x3.Args[2] { - continue - } - y4 := o2.Args[1] - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUloadidx { - continue - } - _ = x4.Args[2] - if ptr != x4.Args[0] { - continue - } - x4_1 := x4.Args[1] - if x4_1.Op != OpARM64ADDconst || auxIntToInt64(x4_1.AuxInt) != 4 || idx != x4_1.Args[0] || mem != x4.Args[2] { - continue - } - y5 := o1.Args[1] - if y5.Op != OpARM64MOVDnop { - continue - } - x5 := y5.Args[0] - if x5.Op != OpARM64MOVBUloadidx { - continue - } - _ = x5.Args[2] - if ptr != x5.Args[0] { - continue - } - x5_1 := x5.Args[1] - if x5_1.Op != OpARM64ADDconst || auxIntToInt64(x5_1.AuxInt) != 5 || idx != x5_1.Args[0] || mem != x5.Args[2] { - continue - } - y6 := o0.Args[1] - if y6.Op != OpARM64MOVDnop { - continue - } - x6 := y6.Args[0] - if x6.Op != OpARM64MOVBUloadidx { - continue - } - _ = x6.Args[2] - if ptr != x6.Args[0] { - continue - } - x6_1 := x6.Args[1] - if x6_1.Op != OpARM64ADDconst || auxIntToInt64(x6_1.AuxInt) != 6 || idx != x6_1.Args[0] || mem != x6.Args[2] { - continue - } - y7 := v_1 - if y7.Op != OpARM64MOVDnop { - continue - } - x7 := y7.Args[0] - if x7.Op != OpARM64MOVBUloadidx { - continue - } - _ = x7.Args[2] - if ptr != x7.Args[0] { - continue - } - x7_1 := x7.Args[1] - if x7_1.Op != OpARM64ADDconst || auxIntToInt64(x7_1.AuxInt) != 7 || idx != x7_1.Args[0] || mem != x7.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) - v0 := b.NewValue0(v.Pos, OpARM64REV, t) - v.copyOf(v0) - v1 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) - v1.AddArg3(ptr, idx, mem) - v0.AddArg(v1) - return true - } - break - } return false } func rewriteValueARM64_OpARM64ORN(v *Value) bool { @@ -19766,1452 +15687,6 @@ v.reset(OpARM64BFXIL) v.AuxInt = arm64BitFieldToAuxInt(bfc) v.AddArg2(y, x) - return true - } - // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUload [i0] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) - // result: @mergePoint(b,x0,x1) (MOVHUload {s} (OffPtr [int64(i0)] p) mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 8 { - break - } - y0 := v_0 - if y0.Op != OpARM64MOVDnop { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload { - break - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := v_1 - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - break - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpARM64MOVHUload, t) - v.copyOf(v0) - v0.Aux = symToAux(s) - v1 := b.NewValue0(x1.Pos, OpOffPtr, p.Type) - v1.AuxInt = int64ToAuxInt(int64(i0)) - v1.AddArg(p) - v0.AddArg2(v1, mem) - return true - } - // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUloadidx ptr0 idx0 mem)) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1) - // result: @mergePoint(b,x0,x1) (MOVHUloadidx ptr0 idx0 mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 8 { - break - } - y0 := v_0 - if y0.Op != OpARM64MOVDnop { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - break - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := v_1 - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 { - break - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x1.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpARM64MOVHUloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr0, idx0, mem) - return true - } - break - } - // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUloadidx ptr idx mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) - // result: @mergePoint(b,x0,x1) (MOVHUloadidx ptr idx mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 8 { - break - } - y0 := v_0 - if y0.Op != OpARM64MOVDnop { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - break - } - mem := x0.Args[2] - ptr := x0.Args[0] - idx := x0.Args[1] - y1 := v_1 - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpARM64MOVHUloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr, idx, mem) - return true - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUload [i0] {s} p mem) y1:(MOVDnop x1:(MOVBUload [i2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i3] {s} p mem))) - // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWUload {s} (OffPtr [int64(i0)] p) mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpARM64MOVHUload { - break - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - break - } - i2 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - break - } - i3 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y1, y2, o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpARM64MOVWUload, t) - v.copyOf(v0) - v0.Aux = symToAux(s) - v1 := b.NewValue0(x2.Pos, OpOffPtr, p.Type) - v1.AuxInt = int64ToAuxInt(int64(i0)) - v1.AddArg(p) - v0.AddArg2(v1, mem) - return true - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [2] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [3] {s} p mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWUloadidx ptr0 idx0 mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpARM64MOVHUloadidx { - break - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 2 { - break - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x1.Args[1] { - continue - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 3 || auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - p := x2.Args[0] - if mem != x2.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0)) { - continue - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr0, idx0, mem) - return true - } - break - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx ptr idx mem) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWUloadidx ptr idx mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpARM64MOVHUloadidx { - break - } - mem := x0.Args[2] - ptr := x0.Args[0] - idx := x0.Args[1] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 2 || idx != x1_1.Args[0] || mem != x1.Args[2] { - break - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - break - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 3 || idx != x2_1.Args[0] || mem != x2.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y1, y2, o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr, idx, mem) - return true - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx2 ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [2] {s} p1:(ADDshiftLL [1] ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [3] {s} p mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWUloadidx ptr0 (SLLconst [1] idx0) mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpARM64MOVHUloadidx2 { - break - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 2 { - break - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADDshiftLL || auxIntToInt64(p1.AuxInt) != 1 { - break - } - idx1 := p1.Args[1] - ptr1 := p1.Args[0] - if mem != x1.Args[1] { - break - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 3 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - p := x2.Args[0] - if mem != x2.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) - v.copyOf(v0) - v1 := b.NewValue0(x2.Pos, OpARM64SLLconst, idx0.Type) - v1.AuxInt = int64ToAuxInt(1) - v1.AddArg(idx0) - v0.AddArg3(ptr0, v1, mem) - return true - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUload [i0] {s} p mem) y1:(MOVDnop x1:(MOVBUload [i4] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i7] {s} p mem))) - // cond: i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDload {s} (OffPtr [int64(i0)] p) mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - x0 := o2.Args[0] - if x0.Op != OpARM64MOVWUload { - break - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - break - } - i4 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - break - } - i5 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - break - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload { - break - } - i6 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - break - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload { - break - } - i7 := auxIntToInt32(x4.AuxInt) - if auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x4.Pos, OpARM64MOVDload, t) - v.copyOf(v0) - v0.Aux = symToAux(s) - v1 := b.NewValue0(x4.Pos, OpOffPtr, p.Type) - v1.AuxInt = int64ToAuxInt(int64(i0)) - v1.AddArg(p) - v0.AddArg2(v1, mem) - return true - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [4] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [7] {s} p mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDloadidx ptr0 idx0 mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - x0 := o2.Args[0] - if x0.Op != OpARM64MOVWUloadidx { - break - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 4 { - break - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x1.Args[1] { - continue - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 5 || auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - p := x2.Args[0] - if mem != x2.Args[1] { - continue - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 6 || auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - continue - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 7 || auxToSym(x4.Aux) != s { - continue - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x4.Pos, OpARM64MOVDloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr0, idx0, mem) - return true - } - break - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx4 ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [4] {s} p1:(ADDshiftLL [2] ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [7] {s} p mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDloadidx ptr0 (SLLconst [2] idx0) mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - x0 := o2.Args[0] - if x0.Op != OpARM64MOVWUloadidx4 { - break - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 4 { - break - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADDshiftLL || auxIntToInt64(p1.AuxInt) != 2 { - break - } - idx1 := p1.Args[1] - ptr1 := p1.Args[0] - if mem != x1.Args[1] { - break - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 5 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - p := x2.Args[0] - if mem != x2.Args[1] { - break - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - break - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 6 || auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - break - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 7 || auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x4.Pos, OpARM64MOVDloadidx, t) - v.copyOf(v0) - v1 := b.NewValue0(x4.Pos, OpARM64SLLconst, idx0.Type) - v1.AuxInt = int64ToAuxInt(2) - v1.AddArg(idx0) - v0.AddArg3(ptr0, v1, mem) - return true - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx ptr idx mem) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [4] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [5] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [6] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr (ADDconst [7] idx) mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDloadidx ptr idx mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - x0 := o2.Args[0] - if x0.Op != OpARM64MOVWUloadidx { - break - } - mem := x0.Args[2] - ptr := x0.Args[0] - idx := x0.Args[1] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 4 || idx != x1_1.Args[0] || mem != x1.Args[2] { - break - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - break - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 5 || idx != x2_1.Args[0] || mem != x2.Args[2] { - break - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - break - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - break - } - _ = x3.Args[2] - if ptr != x3.Args[0] { - break - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 6 || idx != x3_1.Args[0] || mem != x3.Args[2] { - break - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - break - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUloadidx { - break - } - _ = x4.Args[2] - if ptr != x4.Args[0] { - break - } - x4_1 := x4.Args[1] - if x4_1.Op != OpARM64ADDconst || auxIntToInt64(x4_1.AuxInt) != 7 || idx != x4_1.Args[0] || mem != x4.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr, idx, mem) - return true - } - // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUload [i1] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i0] {s} p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) - // result: @mergePoint(b,x0,x1) (REV16W (MOVHUload [i0] {s} p mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 8 { - break - } - y0 := v_0 - if y0.Op != OpARM64MOVDnop { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload { - break - } - i1 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := v_1 - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - break - } - i0 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpARM64REV16W, t) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpARM64MOVHUload, t) - v1.AuxInt = int32ToAuxInt(i0) - v1.Aux = symToAux(s) - v1.AddArg2(p, mem) - v0.AddArg(v1) - return true - } - // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr0 idx0 mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1) - // result: @mergePoint(b,x0,x1) (REV16W (MOVHUloadidx ptr0 idx0 mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 8 { - break - } - y0 := v_0 - if y0.Op != OpARM64MOVDnop { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload || auxIntToInt32(x0.AuxInt) != 1 { - break - } - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p1 := x0.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - y1 := v_1 - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - continue - } - _ = x1.Args[2] - ptr0 := x1.Args[0] - idx0 := x1.Args[1] - if mem != x1.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpARM64REV16W, t) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpARM64MOVHUloadidx, t) - v1.AddArg3(ptr0, idx0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [1] idx) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr idx mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) - // result: @mergePoint(b,x0,x1) (REV16W (MOVHUloadidx ptr idx mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 8 { - break - } - y0 := v_0 - if y0.Op != OpARM64MOVDnop { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - break - } - mem := x0.Args[2] - ptr := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 1 { - break - } - idx := x0_1.Args[0] - y1 := v_1 - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpARM64REV16W, t) - v.copyOf(v0) - v1 := b.NewValue0(v.Pos, OpARM64MOVHUloadidx, t) - v1.AddArg3(ptr, idx, mem) - v0.AddArg(v1) - return true - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] y0:(REV16W x0:(MOVHUload [i2] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i0] {s} p mem))) - // cond: i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (REVW (MOVWUload {s} (OffPtr [int64(i0)] p) mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - y0 := o0.Args[0] - if y0.Op != OpARM64REV16W { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVHUload { - break - } - i2 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - break - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - break - } - i0 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpARM64REVW, t) - v.copyOf(v0) - v1 := b.NewValue0(x2.Pos, OpARM64MOVWUload, t) - v1.Aux = symToAux(s) - v2 := b.NewValue0(x2.Pos, OpOffPtr, p.Type) - v2.AuxInt = int64ToAuxInt(int64(i0)) - v2.AddArg(p) - v1.AddArg2(v2, mem) - v0.AddArg(v1) - return true - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] y0:(REV16W x0:(MOVHUload [2] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr0 idx0 mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y0, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (REVW (MOVWUloadidx ptr0 idx0 mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - y0 := o0.Args[0] - if y0.Op != OpARM64REV16W { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVHUload || auxIntToInt32(x0.AuxInt) != 2 { - break - } - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x1.Args[1] { - continue - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - continue - } - _ = x2.Args[2] - ptr0 := x2.Args[0] - idx0 := x2.Args[1] - if mem != x2.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y0, y1, y2, o0)) { - continue - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpARM64REVW, t) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpARM64MOVWUloadidx, t) - v1.AddArg3(ptr0, idx0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] y0:(REV16W x0:(MOVHUloadidx ptr (ADDconst [2] idx) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr idx mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (REVW (MOVWUloadidx ptr idx mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - y0 := o0.Args[0] - if y0.Op != OpARM64REV16W { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVHUloadidx { - break - } - mem := x0.Args[2] - ptr := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 2 { - break - } - idx := x0_1.Args[0] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] { - break - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - break - } - _ = x2.Args[2] - if ptr != x2.Args[0] || idx != x2.Args[1] || mem != x2.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(v.Pos, OpARM64REVW, t) - v.copyOf(v0) - v1 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) - v1.AddArg3(ptr, idx, mem) - v0.AddArg(v1) - return true - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] y0:(REVW x0:(MOVWUload [i4] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i3] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i1] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i0] {s} p mem))) - // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (REV (MOVDload {s} (OffPtr [int64(i0)] p) mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - y0 := o2.Args[0] - if y0.Op != OpARM64REVW { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVWUload { - break - } - i4 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - break - } - i3 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - break - } - i2 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - break - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload { - break - } - i1 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - break - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload { - break - } - i0 := auxIntToInt32(x4.AuxInt) - if auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x4.Pos, OpARM64REV, t) - v.copyOf(v0) - v1 := b.NewValue0(x4.Pos, OpARM64MOVDload, t) - v1.Aux = symToAux(s) - v2 := b.NewValue0(x4.Pos, OpOffPtr, p.Type) - v2.AuxInt = int64ToAuxInt(int64(i0)) - v2.AddArg(p) - v1.AddArg2(v2, mem) - v0.AddArg(v1) - return true - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] y0:(REVW x0:(MOVWUload [4] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [3] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr0 idx0 mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (REV (MOVDloadidx ptr0 idx0 mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - y0 := o2.Args[0] - if y0.Op != OpARM64REVW { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVWUload || auxIntToInt32(x0.AuxInt) != 4 { - break - } - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 3 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 2 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - break - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 1 || auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[1] - p1 := x3.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x3.Args[1] { - continue - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUloadidx { - continue - } - _ = x4.Args[2] - ptr0 := x4.Args[0] - idx0 := x4.Args[1] - if mem != x4.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x3.Pos, OpARM64REV, t) - v.copyOf(v0) - v1 := b.NewValue0(x3.Pos, OpARM64MOVDloadidx, t) - v1.AddArg3(ptr0, idx0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] y0:(REVW x0:(MOVWUloadidx ptr (ADDconst [4] idx) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr idx mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (REV (MOVDloadidx ptr idx mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - y0 := o2.Args[0] - if y0.Op != OpARM64REVW { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVWUloadidx { - break - } - mem := x0.Args[2] - ptr := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 4 { - break - } - idx := x0_1.Args[0] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 3 || idx != x1_1.Args[0] || mem != x1.Args[2] { - break - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - break - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 2 || idx != x2_1.Args[0] || mem != x2.Args[2] { - break - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - break - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - break - } - _ = x3.Args[2] - if ptr != x3.Args[0] { - break - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 1 || idx != x3_1.Args[0] || mem != x3.Args[2] { - break - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - break - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUloadidx { - break - } - _ = x4.Args[2] - if ptr != x4.Args[0] || idx != x4.Args[1] || mem != x4.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(v.Pos, OpARM64REV, t) - v.copyOf(v0) - v1 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) - v1.AddArg3(ptr, idx, mem) - v0.AddArg(v1) return true } return false -- diff -- # indent-heuristic: true @@ -545,6 +545,9 @@ return true case OpBitRev8: return rewriteValueARM64_OpBitRev8(v) + case OpBswap16: + v.Op = OpARM64REV16W + return true case OpBswap32: v.Op = OpARM64REVW return true @@ -8726,7 +8729,6 @@ v_0 := v.Args[0] b := v.Block config := b.Func.Config - typ := &b.Func.Config.Types // match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVBstore [off1+int32(off2)] {sym} ptr val mem) @@ -8910,1327 +8912,6 @@ v.AddArg3(ptr, x, mem) return true } - // match: (MOVBstore [i] {s} ptr0 (SRLconst [8] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] w) x:(MOVBstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { - continue - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr0 (UBFX [armBFAuxInt(8, 8)] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 8) { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 8)] w) x:(MOVBstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 8) { - continue - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr0 (UBFX [armBFAuxInt(8, 24)] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 24) { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 24)] w) x:(MOVBstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(8, 24) { - continue - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr0 (SRLconst [8] (MOVDreg w)) x:(MOVBstore [i-1] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { - break - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - break - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 8 { - continue - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - continue - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVBstore [i-1] {s} ptr1 w0:(SRLconst [j-8] w) mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst { - break - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst { - continue - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr0 (UBFX [bfc] w) x:(MOVBstore [i-1] {s} ptr1 w0:(UBFX [bfc2] w) mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && bfc.getARM64BFwidth() == 32 - bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32 - bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb() - 8 && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64UBFX { - break - } - bfc := auxIntToArm64BitField(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpARM64UBFX { - break - } - bfc2 := auxIntToArm64BitField(w0.AuxInt) - if w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && bfc.getARM64BFwidth() == 32-bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32-bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb()-8 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [bfc] w) x:(MOVBstoreidx ptr1 idx1 w0:(UBFX [bfc2] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && bfc.getARM64BFwidth() == 32 - bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32 - bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb() - 8 && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64UBFX { - continue - } - bfc := auxIntToArm64BitField(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64UBFX { - continue - } - bfc2 := auxIntToArm64BitField(w0.AuxInt) - if w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && bfc.getARM64BFwidth() == 32-bfc.getARM64BFlsb() && bfc2.getARM64BFwidth() == 32-bfc2.getARM64BFlsb() && bfc2.getARM64BFlsb() == bfc.getARM64BFlsb()-8 && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr0 (SRLconst [j] (MOVDreg w)) x:(MOVBstore [i-1] {s} ptr1 w0:(SRLconst [j-8] (MOVDreg w)) mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstore [i-1] {s} ptr0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst { - break - } - j := auxIntToInt64(v_1.AuxInt) - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - break - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 { - break - } - w0_0 := w0.Args[0] - if w0_0.Op != OpARM64MOVDreg || w != w0_0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] (MOVDreg w)) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr1 idx1 w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst { - continue - } - j := auxIntToInt64(v_1.AuxInt) - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - continue - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-8 { - continue - } - w0_0 := w0.Args[0] - if w0_0.Op != OpARM64MOVDreg || w != w0_0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr1, idx1, w0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] w) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] w) x3:(MOVBstore [i-4] {s} ptr (SRLconst [32] w) x4:(MOVBstore [i-5] {s} ptr (SRLconst [40] w) x5:(MOVBstore [i-6] {s} ptr (SRLconst [48] w) x6:(MOVBstore [i-7] {s} ptr (SRLconst [56] w) mem)))))))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6) - // result: (MOVDstore [i-7] {s} ptr (REV w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if ptr != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { - break - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 || w != x2_1.Args[0] { - break - } - x3 := x2.Args[2] - if x3.Op != OpARM64MOVBstore || auxIntToInt32(x3.AuxInt) != i-4 || auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[2] - if ptr != x3.Args[0] { - break - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64SRLconst || auxIntToInt64(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { - break - } - x4 := x3.Args[2] - if x4.Op != OpARM64MOVBstore || auxIntToInt32(x4.AuxInt) != i-5 || auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[2] - if ptr != x4.Args[0] { - break - } - x4_1 := x4.Args[1] - if x4_1.Op != OpARM64SRLconst || auxIntToInt64(x4_1.AuxInt) != 40 || w != x4_1.Args[0] { - break - } - x5 := x4.Args[2] - if x5.Op != OpARM64MOVBstore || auxIntToInt32(x5.AuxInt) != i-6 || auxToSym(x5.Aux) != s { - break - } - _ = x5.Args[2] - if ptr != x5.Args[0] { - break - } - x5_1 := x5.Args[1] - if x5_1.Op != OpARM64SRLconst || auxIntToInt64(x5_1.AuxInt) != 48 || w != x5_1.Args[0] { - break - } - x6 := x5.Args[2] - if x6.Op != OpARM64MOVBstore || auxIntToInt32(x6.AuxInt) != i-7 || auxToSym(x6.Aux) != s { - break - } - mem := x6.Args[2] - if ptr != x6.Args[0] { - break - } - x6_1 := x6.Args[1] - if x6_1.Op != OpARM64SRLconst || auxIntToInt64(x6_1.AuxInt) != 56 || w != x6_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0, x1, x2, x3, x4, x5, x6)) { - break - } - v.reset(OpARM64MOVDstore) - v.AuxInt = int32ToAuxInt(i - 7) - v.Aux = symToAux(s) - v0 := b.NewValue0(x6.Pos, OpARM64REV, typ.UInt64) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [7] {s} p w x0:(MOVBstore [6] {s} p (SRLconst [8] w) x1:(MOVBstore [5] {s} p (SRLconst [16] w) x2:(MOVBstore [4] {s} p (SRLconst [24] w) x3:(MOVBstore [3] {s} p (SRLconst [32] w) x4:(MOVBstore [2] {s} p (SRLconst [40] w) x5:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [48] w) x6:(MOVBstoreidx ptr0 idx0 (SRLconst [56] w) mem)))))))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6) - // result: (MOVDstoreidx ptr0 idx0 (REV w) mem) - for { - if auxIntToInt32(v.AuxInt) != 7 { - break - } - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 6 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 5 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if p != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { - break - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != 4 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[2] - if p != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 || w != x2_1.Args[0] { - break - } - x3 := x2.Args[2] - if x3.Op != OpARM64MOVBstore || auxIntToInt32(x3.AuxInt) != 3 || auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[2] - if p != x3.Args[0] { - break - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64SRLconst || auxIntToInt64(x3_1.AuxInt) != 32 || w != x3_1.Args[0] { - break - } - x4 := x3.Args[2] - if x4.Op != OpARM64MOVBstore || auxIntToInt32(x4.AuxInt) != 2 || auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[2] - if p != x4.Args[0] { - break - } - x4_1 := x4.Args[1] - if x4_1.Op != OpARM64SRLconst || auxIntToInt64(x4_1.AuxInt) != 40 || w != x4_1.Args[0] { - break - } - x5 := x4.Args[2] - if x5.Op != OpARM64MOVBstore || auxIntToInt32(x5.AuxInt) != 1 || auxToSym(x5.Aux) != s { - break - } - _ = x5.Args[2] - p1 := x5.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - x5_1 := x5.Args[1] - if x5_1.Op != OpARM64SRLconst || auxIntToInt64(x5_1.AuxInt) != 48 || w != x5_1.Args[0] { - continue - } - x6 := x5.Args[2] - if x6.Op != OpARM64MOVBstoreidx { - continue - } - mem := x6.Args[3] - ptr0 := x6.Args[0] - idx0 := x6.Args[1] - x6_2 := x6.Args[2] - if x6_2.Op != OpARM64SRLconst || auxIntToInt64(x6_2.AuxInt) != 56 || w != x6_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6)) { - continue - } - v.reset(OpARM64MOVDstoreidx) - v0 := b.NewValue0(x5.Pos, OpARM64REV, typ.UInt64) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstore [i-2] {s} ptr (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstore [i-3] {s} ptr (UBFX [armBFAuxInt(24, 8)] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) - // result: (MOVWstore [i-3] {s} ptr (REVW w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if ptr != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64UBFX || auxIntToArm64BitField(x0_1.AuxInt) != armBFAuxInt(8, 24) || w != x0_1.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64UBFX || auxIntToArm64BitField(x1_1.AuxInt) != armBFAuxInt(16, 16) || w != x1_1.Args[0] { - break - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { - break - } - mem := x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64UBFX || auxIntToArm64BitField(x2_1.AuxInt) != armBFAuxInt(24, 8) || w != x2_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 3) - v.Aux = symToAux(s) - v0 := b.NewValue0(x2.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(24, 8)] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2) - // result: (MOVWstoreidx ptr0 idx0 (REVW w) mem) - for { - if auxIntToInt32(v.AuxInt) != 3 { - break - } - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 2 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64UBFX || auxIntToArm64BitField(x0_1.AuxInt) != armBFAuxInt(8, 24) || w != x0_1.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64UBFX || auxIntToArm64BitField(x1_1.AuxInt) != armBFAuxInt(16, 16) || w != x1_1.Args[0] { - continue - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstoreidx { - continue - } - mem := x2.Args[3] - ptr0 := x2.Args[0] - idx0 := x2.Args[1] - x2_2 := x2.Args[2] - if x2_2.Op != OpARM64UBFX || auxIntToArm64BitField(x2_2.AuxInt) != armBFAuxInt(24, 8) || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(x1.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] (MOVDreg w)) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] (MOVDreg w)) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) - // result: (MOVWstore [i-3] {s} ptr (REVW w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if ptr != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 { - break - } - x0_1_0 := x0_1.Args[0] - if x0_1_0.Op != OpARM64MOVDreg || w != x0_1_0.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 { - break - } - x1_1_0 := x1_1.Args[0] - if x1_1_0.Op != OpARM64MOVDreg || w != x1_1_0.Args[0] { - break - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { - break - } - mem := x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 { - break - } - x2_1_0 := x2_1.Args[0] - if x2_1_0.Op != OpARM64MOVDreg || w != x2_1_0.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 3) - v.Aux = symToAux(s) - v0 := b.NewValue0(x2.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] (MOVDreg w)) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] (MOVDreg w)) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] (MOVDreg w)) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2) - // result: (MOVWstoreidx ptr0 idx0 (REVW w) mem) - for { - if auxIntToInt32(v.AuxInt) != 3 { - break - } - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 2 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 { - break - } - x0_1_0 := x0_1.Args[0] - if x0_1_0.Op != OpARM64MOVDreg || w != x0_1_0.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 { - continue - } - x1_1_0 := x1_1.Args[0] - if x1_1_0.Op != OpARM64MOVDreg || w != x1_1_0.Args[0] { - continue - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstoreidx { - continue - } - mem := x2.Args[3] - ptr0 := x2.Args[0] - idx0 := x2.Args[1] - x2_2 := x2.Args[2] - if x2_2.Op != OpARM64SRLconst || auxIntToInt64(x2_2.AuxInt) != 24 { - continue - } - x2_2_0 := x2_2.Args[0] - if x2_2_0.Op != OpARM64MOVDreg || w != x2_2_0.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(x1.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] w) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) - // result: (MOVWstore [i-3] {s} ptr (REVW w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != i-1 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if ptr != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != i-2 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { - break - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstore || auxIntToInt32(x2.AuxInt) != i-3 || auxToSym(x2.Aux) != s { - break - } - mem := x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64SRLconst || auxIntToInt64(x2_1.AuxInt) != 24 || w != x2_1.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 3) - v.Aux = symToAux(s) - v0 := b.NewValue0(x2.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] w) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2) - // result: (MOVWstoreidx ptr0 idx0 (REVW w) mem) - for { - if auxIntToInt32(v.AuxInt) != 3 { - break - } - s := auxToSym(v.Aux) - p := v_0 - w := v_1 - x0 := v_2 - if x0.Op != OpARM64MOVBstore || auxIntToInt32(x0.AuxInt) != 2 || auxToSym(x0.Aux) != s { - break - } - _ = x0.Args[2] - if p != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64SRLconst || auxIntToInt64(x0_1.AuxInt) != 8 || w != x0_1.Args[0] { - break - } - x1 := x0.Args[2] - if x1.Op != OpARM64MOVBstore || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[2] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64SRLconst || auxIntToInt64(x1_1.AuxInt) != 16 || w != x1_1.Args[0] { - continue - } - x2 := x1.Args[2] - if x2.Op != OpARM64MOVBstoreidx { - continue - } - mem := x2.Args[3] - ptr0 := x2.Args[0] - idx0 := x2.Args[1] - x2_2 := x2.Args[2] - if x2_2.Op != OpARM64SRLconst || auxIntToInt64(x2_2.AuxInt) != 24 || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(x1.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if ptr != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpARM64SRLconst || auxIntToInt64(x_1.AuxInt) != 8 || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr1 := v_0_0 - idx1 := v_0_1 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr0 := x.Args[0] - idx0 := x.Args[1] - x_2 := x.Args[2] - if x_2.Op != OpARM64SRLconst || auxIntToInt64(x_2.AuxInt) != 8 || w != x_2.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 8)] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if ptr != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpARM64UBFX || auxIntToArm64BitField(x_1.AuxInt) != armBFAuxInt(8, 8) || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 8)] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr1 := v_0_0 - idx1 := v_0_1 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr0 := x.Args[0] - idx0 := x.Args[1] - x_2 := x.Args[2] - if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 8) || w != x_2.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if ptr != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpARM64SRLconst || auxIntToInt64(x_1.AuxInt) != 8 { - break - } - x_1_0 := x_1.Args[0] - if x_1_0.Op != OpARM64MOVDreg || w != x_1_0.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] (MOVDreg w)) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr1 := v_0_0 - idx1 := v_0_1 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr0 := x.Args[0] - idx0 := x.Args[1] - x_2 := x.Args[2] - if x_2.Op != OpARM64SRLconst || auxIntToInt64(x_2.AuxInt) != 8 { - continue - } - x_2_0 := x_2.Args[0] - if x_2_0.Op != OpARM64MOVDreg || w != x_2_0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } - // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 24)] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstore [i-1] {s} ptr (REV16W w) mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr := v_0 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstore || auxIntToInt32(x.AuxInt) != i-1 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - if ptr != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpARM64UBFX || auxIntToArm64BitField(x_1.AuxInt) != armBFAuxInt(8, 24) || w != x_1.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstore) - v.AuxInt = int32ToAuxInt(i - 1) - v.Aux = symToAux(s) - v0 := b.NewValue0(x.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg3(ptr, v0, mem) - return true - } - // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 24)] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstoreidx ptr0 idx0 (REV16W w) mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr1 := v_0_0 - idx1 := v_0_1 - w := v_1 - x := v_2 - if x.Op != OpARM64MOVBstoreidx { - continue - } - mem := x.Args[3] - ptr0 := x.Args[0] - idx0 := x.Args[1] - x_2 := x.Args[2] - if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 24) || w != x_2.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg4(ptr0, idx0, v0, mem) - return true - } - break - } return false } func rewriteValueARM64_OpARM64MOVBstoreidx(v *Value) bool { @@ -10238,8 +8919,6 @@ v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types // match: (MOVBstoreidx ptr (MOVDconst [c]) val mem) // cond: is32Bit(c) // result: (MOVBstore [int32(c)] ptr val mem) @@ -10375,205 +9054,6 @@ v.AddArg4(ptr, idx, x, mem) return true } - // match: (MOVBstoreidx ptr (ADDconst [1] idx) (SRLconst [8] w) x:(MOVBstoreidx ptr idx w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstoreidx ptr idx w mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { - break - } - idx := v_1.Args[0] - if v_2.Op != OpARM64SRLconst || auxIntToInt64(v_2.AuxInt) != 8 { - break - } - w := v_2.Args[0] - x := v_3 - if x.Op != OpARM64MOVBstoreidx { - break - } - mem := x.Args[3] - if ptr != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr, idx, w, mem) - return true - } - // match: (MOVBstoreidx ptr (ADDconst [3] idx) w x0:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(24, 8)] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) - // result: (MOVWstoreidx ptr idx (REVW w) mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 3 { - break - } - idx := v_1.Args[0] - w := v_2 - x0 := v_3 - if x0.Op != OpARM64MOVBstoreidx { - break - } - _ = x0.Args[3] - if ptr != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 2 || idx != x0_1.Args[0] { - break - } - x0_2 := x0.Args[2] - if x0_2.Op != OpARM64UBFX || auxIntToArm64BitField(x0_2.AuxInt) != armBFAuxInt(8, 24) || w != x0_2.Args[0] { - break - } - x1 := x0.Args[3] - if x1.Op != OpARM64MOVBstoreidx { - break - } - _ = x1.Args[3] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] { - break - } - x1_2 := x1.Args[2] - if x1_2.Op != OpARM64UBFX || auxIntToArm64BitField(x1_2.AuxInt) != armBFAuxInt(16, 16) || w != x1_2.Args[0] { - break - } - x2 := x1.Args[3] - if x2.Op != OpARM64MOVBstoreidx { - break - } - mem := x2.Args[3] - if ptr != x2.Args[0] || idx != x2.Args[1] { - break - } - x2_2 := x2.Args[2] - if x2_2.Op != OpARM64UBFX || auxIntToArm64BitField(x2_2.AuxInt) != armBFAuxInt(24, 8) || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64REVW, typ.UInt32) - v0.AddArg(w) - v.AddArg4(ptr, idx, v0, mem) - return true - } - // match: (MOVBstoreidx ptr idx w x0:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr (ADDconst [3] idx) (UBFX [armBFAuxInt(24, 8)] w) mem)))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2) - // result: (MOVWstoreidx ptr idx w mem) - for { - ptr := v_0 - idx := v_1 - w := v_2 - x0 := v_3 - if x0.Op != OpARM64MOVBstoreidx { - break - } - _ = x0.Args[3] - if ptr != x0.Args[0] { - break - } - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 1 || idx != x0_1.Args[0] { - break - } - x0_2 := x0.Args[2] - if x0_2.Op != OpARM64UBFX || auxIntToArm64BitField(x0_2.AuxInt) != armBFAuxInt(8, 24) || w != x0_2.Args[0] { - break - } - x1 := x0.Args[3] - if x1.Op != OpARM64MOVBstoreidx { - break - } - _ = x1.Args[3] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 2 || idx != x1_1.Args[0] { - break - } - x1_2 := x1.Args[2] - if x1_2.Op != OpARM64UBFX || auxIntToArm64BitField(x1_2.AuxInt) != armBFAuxInt(16, 16) || w != x1_2.Args[0] { - break - } - x2 := x1.Args[3] - if x2.Op != OpARM64MOVBstoreidx { - break - } - mem := x2.Args[3] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 3 || idx != x2_1.Args[0] { - break - } - x2_2 := x2.Args[2] - if x2_2.Op != OpARM64UBFX || auxIntToArm64BitField(x2_2.AuxInt) != armBFAuxInt(24, 8) || w != x2_2.Args[0] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0, x1, x2)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v.AddArg4(ptr, idx, w, mem) - return true - } - // match: (MOVBstoreidx ptr (ADDconst [1] idx) w x:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(8, 8)] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstoreidx ptr idx (REV16W w) mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { - break - } - idx := v_1.Args[0] - w := v_2 - x := v_3 - if x.Op != OpARM64MOVBstoreidx { - break - } - mem := x.Args[3] - if ptr != x.Args[0] || idx != x.Args[1] { - break - } - x_2 := x.Args[2] - if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 8) || w != x_2.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64REV16W, typ.UInt16) - v0.AddArg(w) - v.AddArg4(ptr, idx, v0, mem) - return true - } - // match: (MOVBstoreidx ptr idx w x:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 8)] w) mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstoreidx ptr idx w mem) - for { - ptr := v_0 - idx := v_1 - w := v_2 - x := v_3 - if x.Op != OpARM64MOVBstoreidx { - break - } - mem := x.Args[3] - if ptr != x.Args[0] { - break - } - x_1 := x.Args[1] - if x_1.Op != OpARM64ADDconst || auxIntToInt64(x_1.AuxInt) != 1 || idx != x_1.Args[0] { - break - } - x_2 := x.Args[2] - if x_2.Op != OpARM64UBFX || auxIntToArm64BitField(x_2.AuxInt) != armBFAuxInt(8, 8) || w != x_2.Args[0] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstoreidx) - v.AddArg4(ptr, idx, w, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVBstorezero(v *Value) bool { @@ -10643,65 +9123,6 @@ v.AddArg3(ptr, idx, mem) return true } - // match: (MOVBstorezero [i] {s} ptr0 x:(MOVBstorezero [j] {s} ptr1 mem)) - // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),1) && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVHstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - x := v_1 - if x.Op != OpARM64MOVBstorezero { - break - } - j := auxIntToInt32(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - ptr1 := x.Args[0] - if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 1) && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVHstorezero) - v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) - v.Aux = symToAux(s) - v.AddArg2(ptr0, mem) - return true - } - // match: (MOVBstorezero [1] {s} (ADD ptr0 idx0) x:(MOVBstorezeroidx ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVHstorezeroidx ptr1 idx1 mem) - for { - if auxIntToInt32(v.AuxInt) != 1 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - x := v_1 - if x.Op != OpARM64MOVBstorezeroidx { - continue - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVHstorezeroidx) - v.AddArg3(ptr1, idx1, mem) - return true - } - break - } return false } func rewriteValueARM64_OpARM64MOVBstorezeroidx(v *Value) bool { @@ -10744,27 +9165,6 @@ v.AddArg2(idx, mem) return true } - // match: (MOVBstorezeroidx ptr (ADDconst [1] idx) x:(MOVBstorezeroidx ptr idx mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVHstorezeroidx ptr idx mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 1 { - break - } - idx := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVBstorezeroidx { - break - } - mem := x.Args[2] - if ptr != x.Args[0] || idx != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVHstorezeroidx) - v.AddArg3(ptr, idx, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVDload(v *Value) bool { @@ -11331,6 +9731,48 @@ v_0 := v.Args[0] b := v.Block config := b.Func.Config + // match: (MOVDstorezero {s} [i] ptr x:(MOVDstorezero {s} [i+8] ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVQstorezero {s} [i] ptr mem) + for { + i := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + ptr := v_0 + x := v_1 + if x.Op != OpARM64MOVDstorezero || auxIntToInt32(x.AuxInt) != i+8 || auxToSym(x.Aux) != s { + break + } + mem := x.Args[1] + if ptr != x.Args[0] || !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(OpARM64MOVQstorezero) + v.AuxInt = int32ToAuxInt(i) + v.Aux = symToAux(s) + v.AddArg2(ptr, mem) + return true + } + // match: (MOVDstorezero {s} [i] ptr x:(MOVDstorezero {s} [i-8] ptr mem)) + // cond: x.Uses == 1 && clobber(x) + // result: (MOVQstorezero {s} [i-8] ptr mem) + for { + i := auxIntToInt32(v.AuxInt) + s := auxToSym(v.Aux) + ptr := v_0 + x := v_1 + if x.Op != OpARM64MOVDstorezero || auxIntToInt32(x.AuxInt) != i-8 || auxToSym(x.Aux) != s { + break + } + mem := x.Args[1] + if ptr != x.Args[0] || !(x.Uses == 1 && clobber(x)) { + break + } + v.reset(OpARM64MOVQstorezero) + v.AuxInt = int32ToAuxInt(i - 8) + v.Aux = symToAux(s) + v.AddArg2(ptr, mem) + return true + } // match: (MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) // cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) // result: (MOVDstorezero [off1+int32(off2)] {sym} ptr mem) @@ -11412,98 +9854,6 @@ v.AddArg3(ptr, idx, mem) return true } - // match: (MOVDstorezero [i] {s} ptr0 x:(MOVDstorezero [j] {s} ptr1 mem)) - // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),8) && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVQstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - x := v_1 - if x.Op != OpARM64MOVDstorezero { - break - } - j := auxIntToInt32(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - ptr1 := x.Args[0] - if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 8) && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVQstorezero) - v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) - v.Aux = symToAux(s) - v.AddArg2(ptr0, mem) - return true - } - // match: (MOVDstorezero [8] {s} p0:(ADD ptr0 idx0) x:(MOVDstorezeroidx ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVQstorezero [0] {s} p0 mem) - for { - if auxIntToInt32(v.AuxInt) != 8 { - break - } - s := auxToSym(v.Aux) - p0 := v_0 - if p0.Op != OpARM64ADD { - break - } - _ = p0.Args[1] - p0_0 := p0.Args[0] - p0_1 := p0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p0_0, p0_1 = _i0+1, p0_1, p0_0 { - ptr0 := p0_0 - idx0 := p0_1 - x := v_1 - if x.Op != OpARM64MOVDstorezeroidx { - continue - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVQstorezero) - v.AuxInt = int32ToAuxInt(0) - v.Aux = symToAux(s) - v.AddArg2(p0, mem) - return true - } - break - } - // match: (MOVDstorezero [8] {s} p0:(ADDshiftLL [3] ptr0 idx0) x:(MOVDstorezeroidx8 ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVQstorezero [0] {s} p0 mem) - for { - if auxIntToInt32(v.AuxInt) != 8 { - break - } - s := auxToSym(v.Aux) - p0 := v_0 - if p0.Op != OpARM64ADDshiftLL || auxIntToInt64(p0.AuxInt) != 3 { - break - } - idx0 := p0.Args[1] - ptr0 := p0.Args[0] - x := v_1 - if x.Op != OpARM64MOVDstorezeroidx8 { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVQstorezero) - v.AuxInt = int32ToAuxInt(0) - v.Aux = symToAux(s) - v.AddArg2(p0, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVDstorezeroidx(v *Value) bool { @@ -12645,412 +10995,6 @@ v.AddArg3(ptr, x, mem) return true } - // match: (MOVHstore [i] {s} ptr0 (SRLconst [16] w) x:(MOVHstore [i-2] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVWstore [i-2] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [16] w) x:(MOVHstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVWstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { - continue - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [16] w) x:(MOVHstoreidx2 ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx2 { - break - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(1) - v0.AddArg(idx1) - v.AddArg4(ptr1, v0, w, mem) - return true - } - // match: (MOVHstore [i] {s} ptr0 (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstore [i-2] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVWstore [i-2] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(16, 16) { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVWstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(16, 16) { - continue - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstoreidx2 ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - if v_1.Op != OpARM64UBFX || auxIntToArm64BitField(v_1.AuxInt) != armBFAuxInt(16, 16) { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx2 { - break - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(1) - v0.AddArg(idx1) - v.AddArg4(ptr1, v0, w, mem) - return true - } - // match: (MOVHstore [i] {s} ptr0 (SRLconst [16] (MOVDreg w)) x:(MOVHstore [i-2] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVWstore [i-2] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { - break - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - break - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [16] (MOVDreg w)) x:(MOVHstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVWstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { - continue - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - continue - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [16] (MOVDreg w)) x:(MOVHstoreidx2 ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 16 { - break - } - v_1_0 := v_1.Args[0] - if v_1_0.Op != OpARM64MOVDreg { - break - } - w := v_1_0.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx2 { - break - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(1) - v0.AddArg(idx1) - v.AddArg4(ptr1, v0, w, mem) - return true - } - // match: (MOVHstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVHstore [i-2] {s} ptr1 w0:(SRLconst [j-16] w) mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVWstore [i-2] {s} ptr0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst { - break - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstore || auxIntToInt32(x.AuxInt) != i-2 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstore) - v.AuxInt = int32ToAuxInt(i - 2) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w0, mem) - return true - } - // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVHstoreidx ptr1 idx1 w0:(SRLconst [j-16] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVWstoreidx ptr1 idx1 w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst { - continue - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVWstoreidx) - v.AddArg4(ptr1, idx1, w0, mem) - return true - } - break - } - // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [j] w) x:(MOVHstoreidx2 ptr1 idx1 w0:(SRLconst [j-16] w) mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVWstoreidx ptr1 (SLLconst [1] idx1) w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - if v_1.Op != OpARM64SRLconst { - break - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstoreidx2 { - break - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-16 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(1) - v0.AddArg(idx1) - v.AddArg4(ptr1, v0, w0, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVHstoreidx(v *Value) bool { @@ -13227,31 +11171,6 @@ v.AddArg4(ptr, idx, x, mem) return true } - // match: (MOVHstoreidx ptr (ADDconst [2] idx) (SRLconst [16] w) x:(MOVHstoreidx ptr idx w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstoreidx ptr idx w mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 2 { - break - } - idx := v_1.Args[0] - if v_2.Op != OpARM64SRLconst || auxIntToInt64(v_2.AuxInt) != 16 { - break - } - w := v_2.Args[0] - x := v_3 - if x.Op != OpARM64MOVHstoreidx { - break - } - mem := x.Args[3] - if ptr != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVWstoreidx) - v.AddArg4(ptr, idx, w, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVHstoreidx2(v *Value) bool { @@ -13435,95 +11354,6 @@ v.AddArg3(ptr, idx, mem) return true } - // match: (MOVHstorezero [i] {s} ptr0 x:(MOVHstorezero [j] {s} ptr1 mem)) - // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),2) && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVWstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - x := v_1 - if x.Op != OpARM64MOVHstorezero { - break - } - j := auxIntToInt32(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - ptr1 := x.Args[0] - if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 2) && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstorezero) - v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) - v.Aux = symToAux(s) - v.AddArg2(ptr0, mem) - return true - } - // match: (MOVHstorezero [2] {s} (ADD ptr0 idx0) x:(MOVHstorezeroidx ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVWstorezeroidx ptr1 idx1 mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - x := v_1 - if x.Op != OpARM64MOVHstorezeroidx { - continue - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVWstorezeroidx) - v.AddArg3(ptr1, idx1, mem) - return true - } - break - } - // match: (MOVHstorezero [2] {s} (ADDshiftLL [1] ptr0 idx0) x:(MOVHstorezeroidx2 ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVWstorezeroidx ptr1 (SLLconst [1] idx1) mem) - for { - if auxIntToInt32(v.AuxInt) != 2 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 1 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - x := v_1 - if x.Op != OpARM64MOVHstorezeroidx2 { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVWstorezeroidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(1) - v0.AddArg(idx1) - v.AddArg3(ptr1, v0, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVHstorezeroidx(v *Value) bool { @@ -13624,27 +11454,6 @@ v.AddArg3(ptr, idx, mem) return true } - // match: (MOVHstorezeroidx ptr (ADDconst [2] idx) x:(MOVHstorezeroidx ptr idx mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVWstorezeroidx ptr idx mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 2 { - break - } - idx := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVHstorezeroidx { - break - } - mem := x.Args[2] - if ptr != x.Args[0] || idx != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVWstorezeroidx) - v.AddArg3(ptr, idx, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVHstorezeroidx2(v *Value) bool { @@ -14862,206 +12671,6 @@ v.AddArg3(ptr, x, mem) return true } - // match: (MOVWstore [i] {s} ptr0 (SRLconst [32] w) x:(MOVWstore [i-4] {s} ptr1 w mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVDstore [i-4] {s} ptr0 w mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 32 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - if w != x.Args[1] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVDstore) - v.AuxInt = int32ToAuxInt(i - 4) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w, mem) - return true - } - // match: (MOVWstore [4] {s} (ADD ptr0 idx0) (SRLconst [32] w) x:(MOVWstoreidx ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVDstoreidx ptr1 idx1 w mem) - for { - if auxIntToInt32(v.AuxInt) != 4 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 32 { - continue - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVDstoreidx) - v.AddArg4(ptr1, idx1, w, mem) - return true - } - break - } - // match: (MOVWstore [4] {s} (ADDshiftLL [2] ptr0 idx0) (SRLconst [32] w) x:(MOVWstoreidx4 ptr1 idx1 w mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVDstoreidx ptr1 (SLLconst [2] idx1) w mem) - for { - if auxIntToInt32(v.AuxInt) != 4 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - if v_1.Op != OpARM64SRLconst || auxIntToInt64(v_1.AuxInt) != 32 { - break - } - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstoreidx4 { - break - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if w != x.Args[2] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVDstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(2) - v0.AddArg(idx1) - v.AddArg4(ptr1, v0, w, mem) - return true - } - // match: (MOVWstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVWstore [i-4] {s} ptr1 w0:(SRLconst [j-32] w) mem)) - // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVDstore [i-4] {s} ptr0 w0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - if v_1.Op != OpARM64SRLconst { - break - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstore || auxIntToInt32(x.AuxInt) != i-4 || auxToSym(x.Aux) != s { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - w0 := x.Args[1] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVDstore) - v.AuxInt = int32ToAuxInt(i - 4) - v.Aux = symToAux(s) - v.AddArg3(ptr0, w0, mem) - return true - } - // match: (MOVWstore [4] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVWstoreidx ptr1 idx1 w0:(SRLconst [j-32] w) mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVDstoreidx ptr1 idx1 w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 4 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - if v_1.Op != OpARM64SRLconst { - continue - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstoreidx { - continue - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVDstoreidx) - v.AddArg4(ptr1, idx1, w0, mem) - return true - } - break - } - // match: (MOVWstore [4] {s} (ADDshiftLL [2] ptr0 idx0) (SRLconst [j] w) x:(MOVWstoreidx4 ptr1 idx1 w0:(SRLconst [j-32] w) mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVDstoreidx ptr1 (SLLconst [2] idx1) w0 mem) - for { - if auxIntToInt32(v.AuxInt) != 4 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - if v_1.Op != OpARM64SRLconst { - break - } - j := auxIntToInt64(v_1.AuxInt) - w := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstoreidx4 { - break - } - mem := x.Args[3] - ptr1 := x.Args[0] - idx1 := x.Args[1] - w0 := x.Args[2] - if w0.Op != OpARM64SRLconst || auxIntToInt64(w0.AuxInt) != j-32 || w != w0.Args[0] || !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVDstoreidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(2) - v0.AddArg(idx1) - v.AddArg4(ptr1, v0, w0, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVWstoreidx(v *Value) bool { @@ -15176,31 +12785,6 @@ v.AddArg4(ptr, idx, x, mem) return true } - // match: (MOVWstoreidx ptr (ADDconst [4] idx) (SRLconst [32] w) x:(MOVWstoreidx ptr idx w mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVDstoreidx ptr idx w mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 4 { - break - } - idx := v_1.Args[0] - if v_2.Op != OpARM64SRLconst || auxIntToInt64(v_2.AuxInt) != 32 { - break - } - w := v_2.Args[0] - x := v_3 - if x.Op != OpARM64MOVWstoreidx { - break - } - mem := x.Args[3] - if ptr != x.Args[0] || idx != x.Args[1] || w != x.Args[2] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVDstoreidx) - v.AddArg4(ptr, idx, w, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVWstoreidx4(v *Value) bool { @@ -15356,95 +12940,6 @@ v.AddArg3(ptr, idx, mem) return true } - // match: (MOVWstorezero [i] {s} ptr0 x:(MOVWstorezero [j] {s} ptr1 mem)) - // cond: x.Uses == 1 && areAdjacentOffsets(int64(i),int64(j),4) && isSamePtr(ptr0, ptr1) && clobber(x) - // result: (MOVDstorezero [int32(min(int64(i),int64(j)))] {s} ptr0 mem) - for { - i := auxIntToInt32(v.AuxInt) - s := auxToSym(v.Aux) - ptr0 := v_0 - x := v_1 - if x.Op != OpARM64MOVWstorezero { - break - } - j := auxIntToInt32(x.AuxInt) - if auxToSym(x.Aux) != s { - break - } - mem := x.Args[1] - ptr1 := x.Args[0] - if !(x.Uses == 1 && areAdjacentOffsets(int64(i), int64(j), 4) && isSamePtr(ptr0, ptr1) && clobber(x)) { - break - } - v.reset(OpARM64MOVDstorezero) - v.AuxInt = int32ToAuxInt(int32(min(int64(i), int64(j)))) - v.Aux = symToAux(s) - v.AddArg2(ptr0, mem) - return true - } - // match: (MOVWstorezero [4] {s} (ADD ptr0 idx0) x:(MOVWstorezeroidx ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) - // result: (MOVDstorezeroidx ptr1 idx1 mem) - for { - if auxIntToInt32(v.AuxInt) != 4 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADD { - break - } - _ = v_0.Args[1] - v_0_0 := v_0.Args[0] - v_0_1 := v_0.Args[1] - for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 { - ptr0 := v_0_0 - idx0 := v_0_1 - x := v_1 - if x.Op != OpARM64MOVWstorezeroidx { - continue - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { - continue - } - v.reset(OpARM64MOVDstorezeroidx) - v.AddArg3(ptr1, idx1, mem) - return true - } - break - } - // match: (MOVWstorezero [4] {s} (ADDshiftLL [2] ptr0 idx0) x:(MOVWstorezeroidx4 ptr1 idx1 mem)) - // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) - // result: (MOVDstorezeroidx ptr1 (SLLconst [2] idx1) mem) - for { - if auxIntToInt32(v.AuxInt) != 4 { - break - } - s := auxToSym(v.Aux) - if v_0.Op != OpARM64ADDshiftLL || auxIntToInt64(v_0.AuxInt) != 2 { - break - } - idx0 := v_0.Args[1] - ptr0 := v_0.Args[0] - x := v_1 - if x.Op != OpARM64MOVWstorezeroidx4 { - break - } - mem := x.Args[2] - ptr1 := x.Args[0] - idx1 := x.Args[1] - if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { - break - } - v.reset(OpARM64MOVDstorezeroidx) - v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) - v0.AuxInt = int64ToAuxInt(2) - v0.AddArg(idx1) - v.AddArg3(ptr1, v0, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVWstorezeroidx(v *Value) bool { @@ -15513,27 +13008,6 @@ v.AddArg3(ptr, idx, mem) return true } - // match: (MOVWstorezeroidx ptr (ADDconst [4] idx) x:(MOVWstorezeroidx ptr idx mem)) - // cond: x.Uses == 1 && clobber(x) - // result: (MOVDstorezeroidx ptr idx mem) - for { - ptr := v_0 - if v_1.Op != OpARM64ADDconst || auxIntToInt64(v_1.AuxInt) != 4 { - break - } - idx := v_1.Args[0] - x := v_2 - if x.Op != OpARM64MOVWstorezeroidx { - break - } - mem := x.Args[2] - if ptr != x.Args[0] || idx != x.Args[1] || !(x.Uses == 1 && clobber(x)) { - break - } - v.reset(OpARM64MOVDstorezeroidx) - v.AddArg3(ptr, idx, mem) - return true - } return false } func rewriteValueARM64_OpARM64MOVWstorezeroidx4(v *Value) bool { @@ -17529,7 +15003,6 @@ func rewriteValueARM64_OpARM64OR(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block // match: (OR x (MOVDconst [c])) // result: (ORconst [c] x) for { @@ -17709,1558 +15182,6 @@ } break } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [i3] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i1] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i0] {s} p mem))) - // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) - // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUload {s} (OffPtr [int64(i0)] p) mem) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - s0 := o1.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload { - continue - } - i3 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o1.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - continue - } - i2 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y2 := o0.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - continue - } - i1 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - continue - } - y3 := v_1 - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload { - continue - } - i0 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3) - v0 := b.NewValue0(x3.Pos, OpARM64MOVWUload, t) - v.copyOf(v0) - v0.Aux = symToAux(s) - v1 := b.NewValue0(x3.Pos, OpOffPtr, p.Type) - v1.AuxInt = int64ToAuxInt(int64(i0)) - v1.AddArg(p) - v0.AddArg2(v1, mem) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [3] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr0 idx0 mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) - // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUloadidx ptr0 idx0 mem) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - s0 := o1.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload || auxIntToInt32(x0.AuxInt) != 3 { - continue - } - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o1.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 2 || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y2 := o0.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 1 || auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - p1 := x2.Args[0] - if p1.Op != OpARM64ADD { - continue - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x2.Args[1] { - continue - } - y3 := v_1 - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - continue - } - _ = x3.Args[2] - ptr0 := x3.Args[0] - idx0 := x3.Args[1] - if mem != x3.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3) - v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr0, idx0, mem) - return true - } - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr idx mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) - // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUloadidx ptr idx mem) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - s0 := o1.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - continue - } - mem := x0.Args[2] - ptr := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 3 { - continue - } - idx := x0_1.Args[0] - y1 := o1.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - continue - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - continue - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 2 || idx != x1_1.Args[0] || mem != x1.Args[2] { - continue - } - y2 := o0.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - continue - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - continue - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 1 || idx != x2_1.Args[0] || mem != x2.Args[2] { - continue - } - y3 := v_1 - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - continue - } - _ = x3.Args[2] - if ptr != x3.Args[0] || idx != x3.Args[1] || mem != x3.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3) - v0 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr, idx, mem) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUload [i7] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i6] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i4] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i3] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [i2] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [i1] {s} p mem))) y7:(MOVDnop x7:(MOVBUload [i0] {s} p mem))) - // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) - // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload {s} (OffPtr [int64(i0)] p) mem) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { - continue - } - _ = o2.Args[1] - o3 := o2.Args[0] - if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { - continue - } - _ = o3.Args[1] - o4 := o3.Args[0] - if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { - continue - } - _ = o4.Args[1] - o5 := o4.Args[0] - if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { - continue - } - _ = o5.Args[1] - s0 := o5.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload { - continue - } - i7 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o5.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - continue - } - i6 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y2 := o4.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - continue - } - i5 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - continue - } - y3 := o3.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload { - continue - } - i4 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - continue - } - y4 := o2.Args[1] - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload { - continue - } - i3 := auxIntToInt32(x4.AuxInt) - if auxToSym(x4.Aux) != s { - continue - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - continue - } - y5 := o1.Args[1] - if y5.Op != OpARM64MOVDnop { - continue - } - x5 := y5.Args[0] - if x5.Op != OpARM64MOVBUload { - continue - } - i2 := auxIntToInt32(x5.AuxInt) - if auxToSym(x5.Aux) != s { - continue - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - continue - } - y6 := o0.Args[1] - if y6.Op != OpARM64MOVDnop { - continue - } - x6 := y6.Args[0] - if x6.Op != OpARM64MOVBUload { - continue - } - i1 := auxIntToInt32(x6.AuxInt) - if auxToSym(x6.Aux) != s { - continue - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - continue - } - y7 := v_1 - if y7.Op != OpARM64MOVDnop { - continue - } - x7 := y7.Args[0] - if x7.Op != OpARM64MOVBUload { - continue - } - i0 := auxIntToInt32(x7.AuxInt) - if auxToSym(x7.Aux) != s { - continue - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpARM64MOVDload, t) - v.copyOf(v0) - v0.Aux = symToAux(s) - v1 := b.NewValue0(x7.Pos, OpOffPtr, p.Type) - v1.AuxInt = int64ToAuxInt(int64(i0)) - v1.AddArg(p) - v0.AddArg2(v1, mem) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUload [7] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [6] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [4] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [3] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [2] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y7:(MOVDnop x7:(MOVBUloadidx ptr0 idx0 mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) - // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDloadidx ptr0 idx0 mem) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { - continue - } - _ = o2.Args[1] - o3 := o2.Args[0] - if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { - continue - } - _ = o3.Args[1] - o4 := o3.Args[0] - if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { - continue - } - _ = o4.Args[1] - o5 := o4.Args[0] - if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { - continue - } - _ = o5.Args[1] - s0 := o5.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload || auxIntToInt32(x0.AuxInt) != 7 { - continue - } - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o5.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 6 || auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y2 := o4.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 5 || auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - continue - } - y3 := o3.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 4 || auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - continue - } - y4 := o2.Args[1] - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 3 || auxToSym(x4.Aux) != s { - continue - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - continue - } - y5 := o1.Args[1] - if y5.Op != OpARM64MOVDnop { - continue - } - x5 := y5.Args[0] - if x5.Op != OpARM64MOVBUload || auxIntToInt32(x5.AuxInt) != 2 || auxToSym(x5.Aux) != s { - continue - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - continue - } - y6 := o0.Args[1] - if y6.Op != OpARM64MOVDnop { - continue - } - x6 := y6.Args[0] - if x6.Op != OpARM64MOVBUload || auxIntToInt32(x6.AuxInt) != 1 || auxToSym(x6.Aux) != s { - continue - } - _ = x6.Args[1] - p1 := x6.Args[0] - if p1.Op != OpARM64ADD { - continue - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x6.Args[1] { - continue - } - y7 := v_1 - if y7.Op != OpARM64MOVDnop { - continue - } - x7 := y7.Args[0] - if x7.Op != OpARM64MOVBUloadidx { - continue - } - _ = x7.Args[2] - ptr0 := x7.Args[0] - idx0 := x7.Args[1] - if mem != x7.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x6.Pos, OpARM64MOVDloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr0, idx0, mem) - return true - } - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [7] idx) mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [6] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [5] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [4] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y5:(MOVDnop x5:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y6:(MOVDnop x6:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y7:(MOVDnop x7:(MOVBUloadidx ptr idx mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) - // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDloadidx ptr idx mem) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { - continue - } - _ = o2.Args[1] - o3 := o2.Args[0] - if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { - continue - } - _ = o3.Args[1] - o4 := o3.Args[0] - if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { - continue - } - _ = o4.Args[1] - o5 := o4.Args[0] - if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { - continue - } - _ = o5.Args[1] - s0 := o5.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - continue - } - mem := x0.Args[2] - ptr := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 7 { - continue - } - idx := x0_1.Args[0] - y1 := o5.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - continue - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - continue - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 6 || idx != x1_1.Args[0] || mem != x1.Args[2] { - continue - } - y2 := o4.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - continue - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - continue - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 5 || idx != x2_1.Args[0] || mem != x2.Args[2] { - continue - } - y3 := o3.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - continue - } - _ = x3.Args[2] - if ptr != x3.Args[0] { - continue - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 4 || idx != x3_1.Args[0] || mem != x3.Args[2] { - continue - } - y4 := o2.Args[1] - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUloadidx { - continue - } - _ = x4.Args[2] - if ptr != x4.Args[0] { - continue - } - x4_1 := x4.Args[1] - if x4_1.Op != OpARM64ADDconst || auxIntToInt64(x4_1.AuxInt) != 3 || idx != x4_1.Args[0] || mem != x4.Args[2] { - continue - } - y5 := o1.Args[1] - if y5.Op != OpARM64MOVDnop { - continue - } - x5 := y5.Args[0] - if x5.Op != OpARM64MOVBUloadidx { - continue - } - _ = x5.Args[2] - if ptr != x5.Args[0] { - continue - } - x5_1 := x5.Args[1] - if x5_1.Op != OpARM64ADDconst || auxIntToInt64(x5_1.AuxInt) != 2 || idx != x5_1.Args[0] || mem != x5.Args[2] { - continue - } - y6 := o0.Args[1] - if y6.Op != OpARM64MOVDnop { - continue - } - x6 := y6.Args[0] - if x6.Op != OpARM64MOVBUloadidx { - continue - } - _ = x6.Args[2] - if ptr != x6.Args[0] { - continue - } - x6_1 := x6.Args[1] - if x6_1.Op != OpARM64ADDconst || auxIntToInt64(x6_1.AuxInt) != 1 || idx != x6_1.Args[0] || mem != x6.Args[2] { - continue - } - y7 := v_1 - if y7.Op != OpARM64MOVDnop { - continue - } - x7 := y7.Args[0] - if x7.Op != OpARM64MOVBUloadidx { - continue - } - _ = x7.Args[2] - if ptr != x7.Args[0] || idx != x7.Args[1] || mem != x7.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) - v0 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr, idx, mem) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [i0] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i3] {s} p mem))) - // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) - // result: @mergePoint(b,x0,x1,x2,x3) (REVW (MOVWUload {s} (OffPtr [int64(i0)] p) mem)) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - s0 := o1.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o1.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y2 := o0.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - continue - } - i2 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - continue - } - y3 := v_1 - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload { - continue - } - i3 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3) - v0 := b.NewValue0(x3.Pos, OpARM64REVW, t) - v.copyOf(v0) - v1 := b.NewValue0(x3.Pos, OpARM64MOVWUload, t) - v1.Aux = symToAux(s) - v2 := b.NewValue0(x3.Pos, OpOffPtr, p.Type) - v2.AuxInt = int64ToAuxInt(int64(i0)) - v2.AddArg(p) - v1.AddArg2(v2, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr0 idx0 mem))) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [3] {s} p mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) - // result: @mergePoint(b,x0,x1,x2,x3) (REVW (MOVWUloadidx ptr0 idx0 mem)) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - s0 := o1.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - continue - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := o1.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 { - continue - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - continue - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x1.Args[1] { - continue - } - y2 := o0.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 2 || auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - p := x2.Args[0] - if mem != x2.Args[1] { - continue - } - y3 := v_1 - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 3 || auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3) - v0 := b.NewValue0(x3.Pos, OpARM64REVW, t) - v.copyOf(v0) - v1 := b.NewValue0(x3.Pos, OpARM64MOVWUloadidx, t) - v1.AddArg3(ptr0, idx0, mem) - v0.AddArg(v1) - return true - } - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr idx mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0) - // result: @mergePoint(b,x0,x1,x2,x3) (REVW (MOVWUloadidx ptr idx mem)) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - s0 := o1.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 24 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - continue - } - mem := x0.Args[2] - ptr := x0.Args[0] - idx := x0.Args[1] - y1 := o1.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - continue - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - continue - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] { - continue - } - y2 := o0.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - continue - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - continue - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 2 || idx != x2_1.Args[0] || mem != x2.Args[2] { - continue - } - y3 := v_1 - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - continue - } - _ = x3.Args[2] - if ptr != x3.Args[0] { - continue - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 3 || idx != x3_1.Args[0] || mem != x3.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0, x1, x2, x3, y0, y1, y2, y3, o0, o1, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3) - v0 := b.NewValue0(v.Pos, OpARM64REVW, t) - v.copyOf(v0) - v1 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) - v1.AddArg3(ptr, idx, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUload [i0] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i3] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i4] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [i5] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [i6] {s} p mem))) y7:(MOVDnop x7:(MOVBUload [i7] {s} p mem))) - // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) - // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (REV (MOVDload {s} (OffPtr [int64(i0)] p) mem)) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { - continue - } - _ = o2.Args[1] - o3 := o2.Args[0] - if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { - continue - } - _ = o3.Args[1] - o4 := o3.Args[0] - if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { - continue - } - _ = o4.Args[1] - o5 := o4.Args[0] - if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { - continue - } - _ = o5.Args[1] - s0 := o5.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload { - continue - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o5.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - continue - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - continue - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - continue - } - y2 := o4.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - continue - } - i2 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - continue - } - y3 := o3.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload { - continue - } - i3 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - continue - } - y4 := o2.Args[1] - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload { - continue - } - i4 := auxIntToInt32(x4.AuxInt) - if auxToSym(x4.Aux) != s { - continue - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - continue - } - y5 := o1.Args[1] - if y5.Op != OpARM64MOVDnop { - continue - } - x5 := y5.Args[0] - if x5.Op != OpARM64MOVBUload { - continue - } - i5 := auxIntToInt32(x5.AuxInt) - if auxToSym(x5.Aux) != s { - continue - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - continue - } - y6 := o0.Args[1] - if y6.Op != OpARM64MOVDnop { - continue - } - x6 := y6.Args[0] - if x6.Op != OpARM64MOVBUload { - continue - } - i6 := auxIntToInt32(x6.AuxInt) - if auxToSym(x6.Aux) != s { - continue - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - continue - } - y7 := v_1 - if y7.Op != OpARM64MOVDnop { - continue - } - x7 := y7.Args[0] - if x7.Op != OpARM64MOVBUload { - continue - } - i7 := auxIntToInt32(x7.AuxInt) - if auxToSym(x7.Aux) != s { - continue - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpARM64REV, t) - v.copyOf(v0) - v1 := b.NewValue0(x7.Pos, OpARM64MOVDload, t) - v1.Aux = symToAux(s) - v2 := b.NewValue0(x7.Pos, OpOffPtr, p.Type) - v2.AuxInt = int64ToAuxInt(int64(i0)) - v2.AddArg(p) - v1.AddArg2(v2, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUloadidx ptr0 idx0 mem))) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [3] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [4] {s} p mem))) y5:(MOVDnop x5:(MOVBUload [5] {s} p mem))) y6:(MOVDnop x6:(MOVBUload [6] {s} p mem))) y7:(MOVDnop x7:(MOVBUload [7] {s} p mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) - // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (REV (MOVDloadidx ptr0 idx0 mem)) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { - continue - } - _ = o2.Args[1] - o3 := o2.Args[0] - if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { - continue - } - _ = o3.Args[1] - o4 := o3.Args[0] - if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { - continue - } - _ = o4.Args[1] - o5 := o4.Args[0] - if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { - continue - } - _ = o5.Args[1] - s0 := o5.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - continue - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := o5.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 { - continue - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - continue - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i1 := 0; _i1 <= 1; _i1, p1_0, p1_1 = _i1+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x1.Args[1] { - continue - } - y2 := o4.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 2 || auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - p := x2.Args[0] - if mem != x2.Args[1] { - continue - } - y3 := o3.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 3 || auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - continue - } - y4 := o2.Args[1] - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 4 || auxToSym(x4.Aux) != s { - continue - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] { - continue - } - y5 := o1.Args[1] - if y5.Op != OpARM64MOVDnop { - continue - } - x5 := y5.Args[0] - if x5.Op != OpARM64MOVBUload || auxIntToInt32(x5.AuxInt) != 5 || auxToSym(x5.Aux) != s { - continue - } - _ = x5.Args[1] - if p != x5.Args[0] || mem != x5.Args[1] { - continue - } - y6 := o0.Args[1] - if y6.Op != OpARM64MOVDnop { - continue - } - x6 := y6.Args[0] - if x6.Op != OpARM64MOVBUload || auxIntToInt32(x6.AuxInt) != 6 || auxToSym(x6.Aux) != s { - continue - } - _ = x6.Args[1] - if p != x6.Args[0] || mem != x6.Args[1] { - continue - } - y7 := v_1 - if y7.Op != OpARM64MOVDnop { - continue - } - x7 := y7.Args[0] - if x7.Op != OpARM64MOVBUload || auxIntToInt32(x7.AuxInt) != 7 || auxToSym(x7.Aux) != s { - continue - } - _ = x7.Args[1] - if p != x7.Args[0] || mem != x7.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) - v0 := b.NewValue0(x7.Pos, OpARM64REV, t) - v.copyOf(v0) - v1 := b.NewValue0(x7.Pos, OpARM64MOVDloadidx, t) - v1.AddArg3(ptr0, idx0, mem) - v0.AddArg(v1) - return true - } - } - break - } - // match: (OR o0:(ORshiftLL [8] o1:(ORshiftLL [16] o2:(ORshiftLL [24] o3:(ORshiftLL [32] o4:(ORshiftLL [40] o5:(ORshiftLL [48] s0:(SLLconst [56] y0:(MOVDnop x0:(MOVBUloadidx ptr idx mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr (ADDconst [4] idx) mem))) y5:(MOVDnop x5:(MOVBUloadidx ptr (ADDconst [5] idx) mem))) y6:(MOVDnop x6:(MOVBUloadidx ptr (ADDconst [6] idx) mem))) y7:(MOVDnop x7:(MOVBUloadidx ptr (ADDconst [7] idx) mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0) - // result: @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (REV (MOVDloadidx ptr idx mem)) - for { - t := v.Type - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 8 { - continue - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 16 { - continue - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 24 { - continue - } - _ = o2.Args[1] - o3 := o2.Args[0] - if o3.Op != OpARM64ORshiftLL || auxIntToInt64(o3.AuxInt) != 32 { - continue - } - _ = o3.Args[1] - o4 := o3.Args[0] - if o4.Op != OpARM64ORshiftLL || auxIntToInt64(o4.AuxInt) != 40 { - continue - } - _ = o4.Args[1] - o5 := o4.Args[0] - if o5.Op != OpARM64ORshiftLL || auxIntToInt64(o5.AuxInt) != 48 { - continue - } - _ = o5.Args[1] - s0 := o5.Args[0] - if s0.Op != OpARM64SLLconst || auxIntToInt64(s0.AuxInt) != 56 { - continue - } - y0 := s0.Args[0] - if y0.Op != OpARM64MOVDnop { - continue - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - continue - } - mem := x0.Args[2] - ptr := x0.Args[0] - idx := x0.Args[1] - y1 := o5.Args[1] - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - continue - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - continue - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] { - continue - } - y2 := o4.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - continue - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - continue - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 2 || idx != x2_1.Args[0] || mem != x2.Args[2] { - continue - } - y3 := o3.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - continue - } - _ = x3.Args[2] - if ptr != x3.Args[0] { - continue - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 3 || idx != x3_1.Args[0] || mem != x3.Args[2] { - continue - } - y4 := o2.Args[1] - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUloadidx { - continue - } - _ = x4.Args[2] - if ptr != x4.Args[0] { - continue - } - x4_1 := x4.Args[1] - if x4_1.Op != OpARM64ADDconst || auxIntToInt64(x4_1.AuxInt) != 4 || idx != x4_1.Args[0] || mem != x4.Args[2] { - continue - } - y5 := o1.Args[1] - if y5.Op != OpARM64MOVDnop { - continue - } - x5 := y5.Args[0] - if x5.Op != OpARM64MOVBUloadidx { - continue - } - _ = x5.Args[2] - if ptr != x5.Args[0] { - continue - } - x5_1 := x5.Args[1] - if x5_1.Op != OpARM64ADDconst || auxIntToInt64(x5_1.AuxInt) != 5 || idx != x5_1.Args[0] || mem != x5.Args[2] { - continue - } - y6 := o0.Args[1] - if y6.Op != OpARM64MOVDnop { - continue - } - x6 := y6.Args[0] - if x6.Op != OpARM64MOVBUloadidx { - continue - } - _ = x6.Args[2] - if ptr != x6.Args[0] { - continue - } - x6_1 := x6.Args[1] - if x6_1.Op != OpARM64ADDconst || auxIntToInt64(x6_1.AuxInt) != 6 || idx != x6_1.Args[0] || mem != x6.Args[2] { - continue - } - y7 := v_1 - if y7.Op != OpARM64MOVDnop { - continue - } - x7 := y7.Args[0] - if x7.Op != OpARM64MOVBUloadidx { - continue - } - _ = x7.Args[2] - if ptr != x7.Args[0] { - continue - } - x7_1 := x7.Args[1] - if x7_1.Op != OpARM64ADDconst || auxIntToInt64(x7_1.AuxInt) != 7 || idx != x7_1.Args[0] || mem != x7.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && x7.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && y5.Uses == 1 && y6.Uses == 1 && y7.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && o3.Uses == 1 && o4.Uses == 1 && o5.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) != nil && clobber(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, y6, y7, o0, o1, o2, o3, o4, o5, s0)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4, x5, x6, x7) - v0 := b.NewValue0(v.Pos, OpARM64REV, t) - v.copyOf(v0) - v1 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) - v1.AddArg3(ptr, idx, mem) - v0.AddArg(v1) - return true - } - break - } return false } func rewriteValueARM64_OpARM64ORN(v *Value) bool { @@ -19768,1452 +15689,6 @@ v.AddArg2(y, x) return true } - // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUload [i0] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) - // result: @mergePoint(b,x0,x1) (MOVHUload {s} (OffPtr [int64(i0)] p) mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 8 { - break - } - y0 := v_0 - if y0.Op != OpARM64MOVDnop { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload { - break - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := v_1 - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - break - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpARM64MOVHUload, t) - v.copyOf(v0) - v0.Aux = symToAux(s) - v1 := b.NewValue0(x1.Pos, OpOffPtr, p.Type) - v1.AuxInt = int64ToAuxInt(int64(i0)) - v1.AddArg(p) - v0.AddArg2(v1, mem) - return true - } - // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUloadidx ptr0 idx0 mem)) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1) - // result: @mergePoint(b,x0,x1) (MOVHUloadidx ptr0 idx0 mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 8 { - break - } - y0 := v_0 - if y0.Op != OpARM64MOVDnop { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - break - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := v_1 - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 { - break - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x1.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpARM64MOVHUloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr0, idx0, mem) - return true - } - break - } - // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUloadidx ptr idx mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) - // result: @mergePoint(b,x0,x1) (MOVHUloadidx ptr idx mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 8 { - break - } - y0 := v_0 - if y0.Op != OpARM64MOVDnop { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - break - } - mem := x0.Args[2] - ptr := x0.Args[0] - idx := x0.Args[1] - y1 := v_1 - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpARM64MOVHUloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr, idx, mem) - return true - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUload [i0] {s} p mem) y1:(MOVDnop x1:(MOVBUload [i2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i3] {s} p mem))) - // cond: i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWUload {s} (OffPtr [int64(i0)] p) mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpARM64MOVHUload { - break - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - break - } - i2 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - break - } - i3 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y1, y2, o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpARM64MOVWUload, t) - v.copyOf(v0) - v0.Aux = symToAux(s) - v1 := b.NewValue0(x2.Pos, OpOffPtr, p.Type) - v1.AuxInt = int64ToAuxInt(int64(i0)) - v1.AddArg(p) - v0.AddArg2(v1, mem) - return true - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [2] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [3] {s} p mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWUloadidx ptr0 idx0 mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpARM64MOVHUloadidx { - break - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 2 { - break - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x1.Args[1] { - continue - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 3 || auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - p := x2.Args[0] - if mem != x2.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0)) { - continue - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr0, idx0, mem) - return true - } - break - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx ptr idx mem) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWUloadidx ptr idx mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpARM64MOVHUloadidx { - break - } - mem := x0.Args[2] - ptr := x0.Args[0] - idx := x0.Args[1] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 2 || idx != x1_1.Args[0] || mem != x1.Args[2] { - break - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - break - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 3 || idx != x2_1.Args[0] || mem != x2.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y1, y2, o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr, idx, mem) - return true - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] x0:(MOVHUloadidx2 ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [2] {s} p1:(ADDshiftLL [1] ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [3] {s} p mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (MOVWUloadidx ptr0 (SLLconst [1] idx0) mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - x0 := o0.Args[0] - if x0.Op != OpARM64MOVHUloadidx2 { - break - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 2 { - break - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADDshiftLL || auxIntToInt64(p1.AuxInt) != 1 { - break - } - idx1 := p1.Args[1] - ptr1 := p1.Args[0] - if mem != x1.Args[1] { - break - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 3 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - p := x2.Args[0] - if mem != x2.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, y1, y2, o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) - v.copyOf(v0) - v1 := b.NewValue0(x2.Pos, OpARM64SLLconst, idx0.Type) - v1.AuxInt = int64ToAuxInt(1) - v1.AddArg(idx0) - v0.AddArg3(ptr0, v1, mem) - return true - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUload [i0] {s} p mem) y1:(MOVDnop x1:(MOVBUload [i4] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i7] {s} p mem))) - // cond: i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDload {s} (OffPtr [int64(i0)] p) mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - x0 := o2.Args[0] - if x0.Op != OpARM64MOVWUload { - break - } - i0 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - break - } - i4 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - break - } - i5 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - break - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload { - break - } - i6 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - break - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload { - break - } - i7 := auxIntToInt32(x4.AuxInt) - if auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(i4 == i0+4 && i5 == i0+5 && i6 == i0+6 && i7 == i0+7 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x4.Pos, OpARM64MOVDload, t) - v.copyOf(v0) - v0.Aux = symToAux(s) - v1 := b.NewValue0(x4.Pos, OpOffPtr, p.Type) - v1.AuxInt = int64ToAuxInt(int64(i0)) - v1.AddArg(p) - v0.AddArg2(v1, mem) - return true - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [4] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [7] {s} p mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDloadidx ptr0 idx0 mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - x0 := o2.Args[0] - if x0.Op != OpARM64MOVWUloadidx { - break - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 4 { - break - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x1.Args[1] { - continue - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 5 || auxToSym(x2.Aux) != s { - continue - } - _ = x2.Args[1] - p := x2.Args[0] - if mem != x2.Args[1] { - continue - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - continue - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 6 || auxToSym(x3.Aux) != s { - continue - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - continue - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 7 || auxToSym(x4.Aux) != s { - continue - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x4.Pos, OpARM64MOVDloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr0, idx0, mem) - return true - } - break - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx4 ptr0 idx0 mem) y1:(MOVDnop x1:(MOVBUload [4] {s} p1:(ADDshiftLL [2] ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUload [5] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [6] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [7] {s} p mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDloadidx ptr0 (SLLconst [2] idx0) mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - x0 := o2.Args[0] - if x0.Op != OpARM64MOVWUloadidx4 { - break - } - mem := x0.Args[2] - ptr0 := x0.Args[0] - idx0 := x0.Args[1] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 4 { - break - } - s := auxToSym(x1.Aux) - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADDshiftLL || auxIntToInt64(p1.AuxInt) != 2 { - break - } - idx1 := p1.Args[1] - ptr1 := p1.Args[0] - if mem != x1.Args[1] { - break - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 5 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - p := x2.Args[0] - if mem != x2.Args[1] { - break - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - break - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 6 || auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - break - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload || auxIntToInt32(x4.AuxInt) != 7 || auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x4.Pos, OpARM64MOVDloadidx, t) - v.copyOf(v0) - v1 := b.NewValue0(x4.Pos, OpARM64SLLconst, idx0.Type) - v1.AuxInt = int64ToAuxInt(2) - v1.AddArg(idx0) - v0.AddArg3(ptr0, v1, mem) - return true - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] x0:(MOVWUloadidx ptr idx mem) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [4] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [5] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [6] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr (ADDconst [7] idx) mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (MOVDloadidx ptr idx mem) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - x0 := o2.Args[0] - if x0.Op != OpARM64MOVWUloadidx { - break - } - mem := x0.Args[2] - ptr := x0.Args[0] - idx := x0.Args[1] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 4 || idx != x1_1.Args[0] || mem != x1.Args[2] { - break - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - break - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 5 || idx != x2_1.Args[0] || mem != x2.Args[2] { - break - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - break - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - break - } - _ = x3.Args[2] - if ptr != x3.Args[0] { - break - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 6 || idx != x3_1.Args[0] || mem != x3.Args[2] { - break - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - break - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUloadidx { - break - } - _ = x4.Args[2] - if ptr != x4.Args[0] { - break - } - x4_1 := x4.Args[1] - if x4_1.Op != OpARM64ADDconst || auxIntToInt64(x4_1.AuxInt) != 7 || idx != x4_1.Args[0] || mem != x4.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y1, y2, y3, y4, o0, o1, o2)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) - v.copyOf(v0) - v0.AddArg3(ptr, idx, mem) - return true - } - // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUload [i1] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i0] {s} p mem))) - // cond: i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) - // result: @mergePoint(b,x0,x1) (REV16W (MOVHUload [i0] {s} p mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 8 { - break - } - y0 := v_0 - if y0.Op != OpARM64MOVDnop { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload { - break - } - i1 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := v_1 - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - break - } - i0 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] || !(i1 == i0+1 && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x1.Pos, OpARM64REV16W, t) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpARM64MOVHUload, t) - v1.AuxInt = int32ToAuxInt(i0) - v1.Aux = symToAux(s) - v1.AddArg2(p, mem) - v0.AddArg(v1) - return true - } - // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr0 idx0 mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1) - // result: @mergePoint(b,x0,x1) (REV16W (MOVHUloadidx ptr0 idx0 mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 8 { - break - } - y0 := v_0 - if y0.Op != OpARM64MOVDnop { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUload || auxIntToInt32(x0.AuxInt) != 1 { - break - } - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p1 := x0.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - y1 := v_1 - if y1.Op != OpARM64MOVDnop { - continue - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - continue - } - _ = x1.Args[2] - ptr0 := x1.Args[0] - idx0 := x1.Args[1] - if mem != x1.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x0, x1, y0, y1)) { - continue - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(x0.Pos, OpARM64REV16W, t) - v.copyOf(v0) - v1 := b.NewValue0(x0.Pos, OpARM64MOVHUloadidx, t) - v1.AddArg3(ptr0, idx0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORshiftLL [8] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [1] idx) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr idx mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b,x0,x1) != nil && clobber(x0, x1, y0, y1) - // result: @mergePoint(b,x0,x1) (REV16W (MOVHUloadidx ptr idx mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 8 { - break - } - y0 := v_0 - if y0.Op != OpARM64MOVDnop { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVBUloadidx { - break - } - mem := x0.Args[2] - ptr := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 1 { - break - } - idx := x0_1.Args[0] - y1 := v_1 - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] || idx != x1.Args[1] || mem != x1.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && mergePoint(b, x0, x1) != nil && clobber(x0, x1, y0, y1)) { - break - } - b = mergePoint(b, x0, x1) - v0 := b.NewValue0(v.Pos, OpARM64REV16W, t) - v.copyOf(v0) - v1 := b.NewValue0(v.Pos, OpARM64MOVHUloadidx, t) - v1.AddArg3(ptr, idx, mem) - v0.AddArg(v1) - return true - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] y0:(REV16W x0:(MOVHUload [i2] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i1] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i0] {s} p mem))) - // cond: i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (REVW (MOVWUload {s} (OffPtr [int64(i0)] p) mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - y0 := o0.Args[0] - if y0.Op != OpARM64REV16W { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVHUload { - break - } - i2 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - break - } - i1 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - break - } - i0 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] || !(i1 == i0+1 && i2 == i0+2 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x2.Pos, OpARM64REVW, t) - v.copyOf(v0) - v1 := b.NewValue0(x2.Pos, OpARM64MOVWUload, t) - v1.Aux = symToAux(s) - v2 := b.NewValue0(x2.Pos, OpOffPtr, p.Type) - v2.AuxInt = int64ToAuxInt(int64(i0)) - v2.AddArg(p) - v1.AddArg2(v2, mem) - v0.AddArg(v1) - return true - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] y0:(REV16W x0:(MOVHUload [2] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr0 idx0 mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y0, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (REVW (MOVWUloadidx ptr0 idx0 mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - y0 := o0.Args[0] - if y0.Op != OpARM64REV16W { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVHUload || auxIntToInt32(x0.AuxInt) != 2 { - break - } - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 1 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - p1 := x1.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x1.Args[1] { - continue - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - continue - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - continue - } - _ = x2.Args[2] - ptr0 := x2.Args[0] - idx0 := x2.Args[1] - if mem != x2.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, y0, y1, y2, o0)) { - continue - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(x1.Pos, OpARM64REVW, t) - v.copyOf(v0) - v1 := b.NewValue0(x1.Pos, OpARM64MOVWUloadidx, t) - v1.AddArg3(ptr0, idx0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORshiftLL [24] o0:(ORshiftLL [16] y0:(REV16W x0:(MOVHUloadidx ptr (ADDconst [2] idx) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr idx mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b,x0,x1,x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0) - // result: @mergePoint(b,x0,x1,x2) (REVW (MOVWUloadidx ptr idx mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 24 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 16 { - break - } - _ = o0.Args[1] - y0 := o0.Args[0] - if y0.Op != OpARM64REV16W { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVHUloadidx { - break - } - mem := x0.Args[2] - ptr := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 2 { - break - } - idx := x0_1.Args[0] - y1 := o0.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 1 || idx != x1_1.Args[0] || mem != x1.Args[2] { - break - } - y2 := v_1 - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - break - } - _ = x2.Args[2] - if ptr != x2.Args[0] || idx != x2.Args[1] || mem != x2.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && o0.Uses == 1 && mergePoint(b, x0, x1, x2) != nil && clobber(x0, x1, x2, y0, y1, y2, o0)) { - break - } - b = mergePoint(b, x0, x1, x2) - v0 := b.NewValue0(v.Pos, OpARM64REVW, t) - v.copyOf(v0) - v1 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) - v1.AddArg3(ptr, idx, mem) - v0.AddArg(v1) - return true - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] y0:(REVW x0:(MOVWUload [i4] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [i3] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i1] {s} p mem))) y4:(MOVDnop x4:(MOVBUload [i0] {s} p mem))) - // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (REV (MOVDload {s} (OffPtr [int64(i0)] p) mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - y0 := o2.Args[0] - if y0.Op != OpARM64REVW { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVWUload { - break - } - i4 := auxIntToInt32(x0.AuxInt) - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload { - break - } - i3 := auxIntToInt32(x1.AuxInt) - if auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload { - break - } - i2 := auxIntToInt32(x2.AuxInt) - if auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - break - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload { - break - } - i1 := auxIntToInt32(x3.AuxInt) - if auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[1] - if p != x3.Args[0] || mem != x3.Args[1] { - break - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - break - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUload { - break - } - i0 := auxIntToInt32(x4.AuxInt) - if auxToSym(x4.Aux) != s { - break - } - _ = x4.Args[1] - if p != x4.Args[0] || mem != x4.Args[1] || !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && i4 == i0+4 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x4.Pos, OpARM64REV, t) - v.copyOf(v0) - v1 := b.NewValue0(x4.Pos, OpARM64MOVDload, t) - v1.Aux = symToAux(s) - v2 := b.NewValue0(x4.Pos, OpOffPtr, p.Type) - v2.AuxInt = int64ToAuxInt(int64(i0)) - v2.AddArg(p) - v1.AddArg2(v2, mem) - v0.AddArg(v1) - return true - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] y0:(REVW x0:(MOVWUload [4] {s} p mem)) y1:(MOVDnop x1:(MOVBUload [3] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [2] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr0 idx0 mem))) - // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (REV (MOVDloadidx ptr0 idx0 mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - y0 := o2.Args[0] - if y0.Op != OpARM64REVW { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVWUload || auxIntToInt32(x0.AuxInt) != 4 { - break - } - s := auxToSym(x0.Aux) - mem := x0.Args[1] - p := x0.Args[0] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUload || auxIntToInt32(x1.AuxInt) != 3 || auxToSym(x1.Aux) != s { - break - } - _ = x1.Args[1] - if p != x1.Args[0] || mem != x1.Args[1] { - break - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUload || auxIntToInt32(x2.AuxInt) != 2 || auxToSym(x2.Aux) != s { - break - } - _ = x2.Args[1] - if p != x2.Args[0] || mem != x2.Args[1] { - break - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - break - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUload || auxIntToInt32(x3.AuxInt) != 1 || auxToSym(x3.Aux) != s { - break - } - _ = x3.Args[1] - p1 := x3.Args[0] - if p1.Op != OpARM64ADD { - break - } - _ = p1.Args[1] - p1_0 := p1.Args[0] - p1_1 := p1.Args[1] - for _i0 := 0; _i0 <= 1; _i0, p1_0, p1_1 = _i0+1, p1_1, p1_0 { - ptr1 := p1_0 - idx1 := p1_1 - if mem != x3.Args[1] { - continue - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - continue - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUloadidx { - continue - } - _ = x4.Args[2] - ptr0 := x4.Args[0] - idx0 := x4.Args[1] - if mem != x4.Args[2] || !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2)) { - continue - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(x3.Pos, OpARM64REV, t) - v.copyOf(v0) - v1 := b.NewValue0(x3.Pos, OpARM64MOVDloadidx, t) - v1.AddArg3(ptr0, idx0, mem) - v0.AddArg(v1) - return true - } - break - } - // match: (ORshiftLL [56] o0:(ORshiftLL [48] o1:(ORshiftLL [40] o2:(ORshiftLL [32] y0:(REVW x0:(MOVWUloadidx ptr (ADDconst [4] idx) mem)) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y4:(MOVDnop x4:(MOVBUloadidx ptr idx mem))) - // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b,x0,x1,x2,x3,x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2) - // result: @mergePoint(b,x0,x1,x2,x3,x4) (REV (MOVDloadidx ptr idx mem)) - for { - t := v.Type - if auxIntToInt64(v.AuxInt) != 56 { - break - } - o0 := v_0 - if o0.Op != OpARM64ORshiftLL || auxIntToInt64(o0.AuxInt) != 48 { - break - } - _ = o0.Args[1] - o1 := o0.Args[0] - if o1.Op != OpARM64ORshiftLL || auxIntToInt64(o1.AuxInt) != 40 { - break - } - _ = o1.Args[1] - o2 := o1.Args[0] - if o2.Op != OpARM64ORshiftLL || auxIntToInt64(o2.AuxInt) != 32 { - break - } - _ = o2.Args[1] - y0 := o2.Args[0] - if y0.Op != OpARM64REVW { - break - } - x0 := y0.Args[0] - if x0.Op != OpARM64MOVWUloadidx { - break - } - mem := x0.Args[2] - ptr := x0.Args[0] - x0_1 := x0.Args[1] - if x0_1.Op != OpARM64ADDconst || auxIntToInt64(x0_1.AuxInt) != 4 { - break - } - idx := x0_1.Args[0] - y1 := o2.Args[1] - if y1.Op != OpARM64MOVDnop { - break - } - x1 := y1.Args[0] - if x1.Op != OpARM64MOVBUloadidx { - break - } - _ = x1.Args[2] - if ptr != x1.Args[0] { - break - } - x1_1 := x1.Args[1] - if x1_1.Op != OpARM64ADDconst || auxIntToInt64(x1_1.AuxInt) != 3 || idx != x1_1.Args[0] || mem != x1.Args[2] { - break - } - y2 := o1.Args[1] - if y2.Op != OpARM64MOVDnop { - break - } - x2 := y2.Args[0] - if x2.Op != OpARM64MOVBUloadidx { - break - } - _ = x2.Args[2] - if ptr != x2.Args[0] { - break - } - x2_1 := x2.Args[1] - if x2_1.Op != OpARM64ADDconst || auxIntToInt64(x2_1.AuxInt) != 2 || idx != x2_1.Args[0] || mem != x2.Args[2] { - break - } - y3 := o0.Args[1] - if y3.Op != OpARM64MOVDnop { - break - } - x3 := y3.Args[0] - if x3.Op != OpARM64MOVBUloadidx { - break - } - _ = x3.Args[2] - if ptr != x3.Args[0] { - break - } - x3_1 := x3.Args[1] - if x3_1.Op != OpARM64ADDconst || auxIntToInt64(x3_1.AuxInt) != 1 || idx != x3_1.Args[0] || mem != x3.Args[2] { - break - } - y4 := v_1 - if y4.Op != OpARM64MOVDnop { - break - } - x4 := y4.Args[0] - if x4.Op != OpARM64MOVBUloadidx { - break - } - _ = x4.Args[2] - if ptr != x4.Args[0] || idx != x4.Args[1] || mem != x4.Args[2] || !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && y4.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && o2.Uses == 1 && mergePoint(b, x0, x1, x2, x3, x4) != nil && clobber(x0, x1, x2, x3, x4, y0, y1, y2, y3, y4, o0, o1, o2)) { - break - } - b = mergePoint(b, x0, x1, x2, x3, x4) - v0 := b.NewValue0(v.Pos, OpARM64REV, t) - v.copyOf(v0) - v1 := b.NewValue0(v.Pos, OpARM64MOVDloadidx, t) - v1.AddArg3(ptr, idx, mem) - v0.AddArg(v1) - return true - } return false } func rewriteValueARM64_OpARM64ORshiftRA(v *Value) bool { go_ec5bdefd0a8f4a4dc7ba8d6ab4e1cf393384d03c_src_cmd_compile_internal_ssa_opGen.go.test000066400000000000000000102274441516001707200352450ustar00rootroot00000000000000diff-1.0.1/textdiff/testdataFrom https://go.googlesource.com/go commit ec5bdefd0a8f4a4dc7ba8d6ab4e1cf393384d03c file src/cmd/compile/internal/ssa/opGen.go -- x -- // Code generated from gen/*Ops.go; DO NOT EDIT. package ssa import ( "cmd/internal/obj" "cmd/internal/obj/arm" "cmd/internal/obj/arm64" "cmd/internal/obj/mips" "cmd/internal/obj/ppc64" "cmd/internal/obj/riscv" "cmd/internal/obj/s390x" "cmd/internal/obj/wasm" "cmd/internal/obj/x86" ) const ( BlockInvalid BlockKind = iota Block386EQ Block386NE Block386LT Block386LE Block386GT Block386GE Block386OS Block386OC Block386ULT Block386ULE Block386UGT Block386UGE Block386EQF Block386NEF Block386ORD Block386NAN BlockAMD64EQ BlockAMD64NE BlockAMD64LT BlockAMD64LE BlockAMD64GT BlockAMD64GE BlockAMD64OS BlockAMD64OC BlockAMD64ULT BlockAMD64ULE BlockAMD64UGT BlockAMD64UGE BlockAMD64EQF BlockAMD64NEF BlockAMD64ORD BlockAMD64NAN BlockAMD64JUMPTABLE BlockARMEQ BlockARMNE BlockARMLT BlockARMLE BlockARMGT BlockARMGE BlockARMULT BlockARMULE BlockARMUGT BlockARMUGE BlockARMLTnoov BlockARMLEnoov BlockARMGTnoov BlockARMGEnoov BlockARM64EQ BlockARM64NE BlockARM64LT BlockARM64LE BlockARM64GT BlockARM64GE BlockARM64ULT BlockARM64ULE BlockARM64UGT BlockARM64UGE BlockARM64Z BlockARM64NZ BlockARM64ZW BlockARM64NZW BlockARM64TBZ BlockARM64TBNZ BlockARM64FLT BlockARM64FLE BlockARM64FGT BlockARM64FGE BlockARM64LTnoov BlockARM64LEnoov BlockARM64GTnoov BlockARM64GEnoov BlockMIPSEQ BlockMIPSNE BlockMIPSLTZ BlockMIPSLEZ BlockMIPSGTZ BlockMIPSGEZ BlockMIPSFPT BlockMIPSFPF BlockMIPS64EQ BlockMIPS64NE BlockMIPS64LTZ BlockMIPS64LEZ BlockMIPS64GTZ BlockMIPS64GEZ BlockMIPS64FPT BlockMIPS64FPF BlockPPC64EQ BlockPPC64NE BlockPPC64LT BlockPPC64LE BlockPPC64GT BlockPPC64GE BlockPPC64FLT BlockPPC64FLE BlockPPC64FGT BlockPPC64FGE BlockRISCV64BEQ BlockRISCV64BNE BlockRISCV64BLT BlockRISCV64BGE BlockRISCV64BLTU BlockRISCV64BGEU BlockRISCV64BEQZ BlockRISCV64BNEZ BlockRISCV64BLEZ BlockRISCV64BGEZ BlockRISCV64BLTZ BlockRISCV64BGTZ BlockS390XBRC BlockS390XCRJ BlockS390XCGRJ BlockS390XCLRJ BlockS390XCLGRJ BlockS390XCIJ BlockS390XCGIJ BlockS390XCLIJ BlockS390XCLGIJ BlockPlain BlockIf BlockDefer BlockRet BlockRetJmp BlockExit BlockJumpTable BlockFirst ) var blockString = [...]string{ BlockInvalid: "BlockInvalid", Block386EQ: "EQ", Block386NE: "NE", Block386LT: "LT", Block386LE: "LE", Block386GT: "GT", Block386GE: "GE", Block386OS: "OS", Block386OC: "OC", Block386ULT: "ULT", Block386ULE: "ULE", Block386UGT: "UGT", Block386UGE: "UGE", Block386EQF: "EQF", Block386NEF: "NEF", Block386ORD: "ORD", Block386NAN: "NAN", BlockAMD64EQ: "EQ", BlockAMD64NE: "NE", BlockAMD64LT: "LT", BlockAMD64LE: "LE", BlockAMD64GT: "GT", BlockAMD64GE: "GE", BlockAMD64OS: "OS", BlockAMD64OC: "OC", BlockAMD64ULT: "ULT", BlockAMD64ULE: "ULE", BlockAMD64UGT: "UGT", BlockAMD64UGE: "UGE", BlockAMD64EQF: "EQF", BlockAMD64NEF: "NEF", BlockAMD64ORD: "ORD", BlockAMD64NAN: "NAN", BlockAMD64JUMPTABLE: "JUMPTABLE", BlockARMEQ: "EQ", BlockARMNE: "NE", BlockARMLT: "LT", BlockARMLE: "LE", BlockARMGT: "GT", BlockARMGE: "GE", BlockARMULT: "ULT", BlockARMULE: "ULE", BlockARMUGT: "UGT", BlockARMUGE: "UGE", BlockARMLTnoov: "LTnoov", BlockARMLEnoov: "LEnoov", BlockARMGTnoov: "GTnoov", BlockARMGEnoov: "GEnoov", BlockARM64EQ: "EQ", BlockARM64NE: "NE", BlockARM64LT: "LT", BlockARM64LE: "LE", BlockARM64GT: "GT", BlockARM64GE: "GE", BlockARM64ULT: "ULT", BlockARM64ULE: "ULE", BlockARM64UGT: "UGT", BlockARM64UGE: "UGE", BlockARM64Z: "Z", BlockARM64NZ: "NZ", BlockARM64ZW: "ZW", BlockARM64NZW: "NZW", BlockARM64TBZ: "TBZ", BlockARM64TBNZ: "TBNZ", BlockARM64FLT: "FLT", BlockARM64FLE: "FLE", BlockARM64FGT: "FGT", BlockARM64FGE: "FGE", BlockARM64LTnoov: "LTnoov", BlockARM64LEnoov: "LEnoov", BlockARM64GTnoov: "GTnoov", BlockARM64GEnoov: "GEnoov", BlockMIPSEQ: "EQ", BlockMIPSNE: "NE", BlockMIPSLTZ: "LTZ", BlockMIPSLEZ: "LEZ", BlockMIPSGTZ: "GTZ", BlockMIPSGEZ: "GEZ", BlockMIPSFPT: "FPT", BlockMIPSFPF: "FPF", BlockMIPS64EQ: "EQ", BlockMIPS64NE: "NE", BlockMIPS64LTZ: "LTZ", BlockMIPS64LEZ: "LEZ", BlockMIPS64GTZ: "GTZ", BlockMIPS64GEZ: "GEZ", BlockMIPS64FPT: "FPT", BlockMIPS64FPF: "FPF", BlockPPC64EQ: "EQ", BlockPPC64NE: "NE", BlockPPC64LT: "LT", BlockPPC64LE: "LE", BlockPPC64GT: "GT", BlockPPC64GE: "GE", BlockPPC64FLT: "FLT", BlockPPC64FLE: "FLE", BlockPPC64FGT: "FGT", BlockPPC64FGE: "FGE", BlockRISCV64BEQ: "BEQ", BlockRISCV64BNE: "BNE", BlockRISCV64BLT: "BLT", BlockRISCV64BGE: "BGE", BlockRISCV64BLTU: "BLTU", BlockRISCV64BGEU: "BGEU", BlockRISCV64BEQZ: "BEQZ", BlockRISCV64BNEZ: "BNEZ", BlockRISCV64BLEZ: "BLEZ", BlockRISCV64BGEZ: "BGEZ", BlockRISCV64BLTZ: "BLTZ", BlockRISCV64BGTZ: "BGTZ", BlockS390XBRC: "BRC", BlockS390XCRJ: "CRJ", BlockS390XCGRJ: "CGRJ", BlockS390XCLRJ: "CLRJ", BlockS390XCLGRJ: "CLGRJ", BlockS390XCIJ: "CIJ", BlockS390XCGIJ: "CGIJ", BlockS390XCLIJ: "CLIJ", BlockS390XCLGIJ: "CLGIJ", BlockPlain: "Plain", BlockIf: "If", BlockDefer: "Defer", BlockRet: "Ret", BlockRetJmp: "RetJmp", BlockExit: "Exit", BlockJumpTable: "JumpTable", BlockFirst: "First", } func (k BlockKind) String() string { return blockString[k] } func (k BlockKind) AuxIntType() string { switch k { case BlockARM64TBZ: return "int64" case BlockARM64TBNZ: return "int64" case BlockS390XCIJ: return "int8" case BlockS390XCGIJ: return "int8" case BlockS390XCLIJ: return "uint8" case BlockS390XCLGIJ: return "uint8" } return "" } const ( OpInvalid Op = iota Op386ADDSS Op386ADDSD Op386SUBSS Op386SUBSD Op386MULSS Op386MULSD Op386DIVSS Op386DIVSD Op386MOVSSload Op386MOVSDload Op386MOVSSconst Op386MOVSDconst Op386MOVSSloadidx1 Op386MOVSSloadidx4 Op386MOVSDloadidx1 Op386MOVSDloadidx8 Op386MOVSSstore Op386MOVSDstore Op386MOVSSstoreidx1 Op386MOVSSstoreidx4 Op386MOVSDstoreidx1 Op386MOVSDstoreidx8 Op386ADDSSload Op386ADDSDload Op386SUBSSload Op386SUBSDload Op386MULSSload Op386MULSDload Op386DIVSSload Op386DIVSDload Op386ADDL Op386ADDLconst Op386ADDLcarry Op386ADDLconstcarry Op386ADCL Op386ADCLconst Op386SUBL Op386SUBLconst Op386SUBLcarry Op386SUBLconstcarry Op386SBBL Op386SBBLconst Op386MULL Op386MULLconst Op386MULLU Op386HMULL Op386HMULLU Op386MULLQU Op386AVGLU Op386DIVL Op386DIVW Op386DIVLU Op386DIVWU Op386MODL Op386MODW Op386MODLU Op386MODWU Op386ANDL Op386ANDLconst Op386ORL Op386ORLconst Op386XORL Op386XORLconst Op386CMPL Op386CMPW Op386CMPB Op386CMPLconst Op386CMPWconst Op386CMPBconst Op386CMPLload Op386CMPWload Op386CMPBload Op386CMPLconstload Op386CMPWconstload Op386CMPBconstload Op386UCOMISS Op386UCOMISD Op386TESTL Op386TESTW Op386TESTB Op386TESTLconst Op386TESTWconst Op386TESTBconst Op386SHLL Op386SHLLconst Op386SHRL Op386SHRW Op386SHRB Op386SHRLconst Op386SHRWconst Op386SHRBconst Op386SARL Op386SARW Op386SARB Op386SARLconst Op386SARWconst Op386SARBconst Op386ROLLconst Op386ROLWconst Op386ROLBconst Op386ADDLload Op386SUBLload Op386MULLload Op386ANDLload Op386ORLload Op386XORLload Op386ADDLloadidx4 Op386SUBLloadidx4 Op386MULLloadidx4 Op386ANDLloadidx4 Op386ORLloadidx4 Op386XORLloadidx4 Op386NEGL Op386NOTL Op386BSFL Op386BSFW Op386BSRL Op386BSRW Op386BSWAPL Op386SQRTSD Op386SQRTSS Op386SBBLcarrymask Op386SETEQ Op386SETNE Op386SETL Op386SETLE Op386SETG Op386SETGE Op386SETB Op386SETBE Op386SETA Op386SETAE Op386SETO Op386SETEQF Op386SETNEF Op386SETORD Op386SETNAN Op386SETGF Op386SETGEF Op386MOVBLSX Op386MOVBLZX Op386MOVWLSX Op386MOVWLZX Op386MOVLconst Op386CVTTSD2SL Op386CVTTSS2SL Op386CVTSL2SS Op386CVTSL2SD Op386CVTSD2SS Op386CVTSS2SD Op386PXOR Op386LEAL Op386LEAL1 Op386LEAL2 Op386LEAL4 Op386LEAL8 Op386MOVBload Op386MOVBLSXload Op386MOVWload Op386MOVWLSXload Op386MOVLload Op386MOVBstore Op386MOVWstore Op386MOVLstore Op386ADDLmodify Op386SUBLmodify Op386ANDLmodify Op386ORLmodify Op386XORLmodify Op386ADDLmodifyidx4 Op386SUBLmodifyidx4 Op386ANDLmodifyidx4 Op386ORLmodifyidx4 Op386XORLmodifyidx4 Op386ADDLconstmodify Op386ANDLconstmodify Op386ORLconstmodify Op386XORLconstmodify Op386ADDLconstmodifyidx4 Op386ANDLconstmodifyidx4 Op386ORLconstmodifyidx4 Op386XORLconstmodifyidx4 Op386MOVBloadidx1 Op386MOVWloadidx1 Op386MOVWloadidx2 Op386MOVLloadidx1 Op386MOVLloadidx4 Op386MOVBstoreidx1 Op386MOVWstoreidx1 Op386MOVWstoreidx2 Op386MOVLstoreidx1 Op386MOVLstoreidx4 Op386MOVBstoreconst Op386MOVWstoreconst Op386MOVLstoreconst Op386MOVBstoreconstidx1 Op386MOVWstoreconstidx1 Op386MOVWstoreconstidx2 Op386MOVLstoreconstidx1 Op386MOVLstoreconstidx4 Op386DUFFZERO Op386REPSTOSL Op386CALLstatic Op386CALLtail Op386CALLclosure Op386CALLinter Op386DUFFCOPY Op386REPMOVSL Op386InvertFlags Op386LoweredGetG Op386LoweredGetClosurePtr Op386LoweredGetCallerPC Op386LoweredGetCallerSP Op386LoweredNilCheck Op386LoweredWB Op386LoweredPanicBoundsA Op386LoweredPanicBoundsB Op386LoweredPanicBoundsC Op386LoweredPanicExtendA Op386LoweredPanicExtendB Op386LoweredPanicExtendC Op386FlagEQ Op386FlagLT_ULT Op386FlagLT_UGT Op386FlagGT_UGT Op386FlagGT_ULT Op386MOVSSconst1 Op386MOVSDconst1 Op386MOVSSconst2 Op386MOVSDconst2 OpAMD64ADDSS OpAMD64ADDSD OpAMD64SUBSS OpAMD64SUBSD OpAMD64MULSS OpAMD64MULSD OpAMD64DIVSS OpAMD64DIVSD OpAMD64MOVSSload OpAMD64MOVSDload OpAMD64MOVSSconst OpAMD64MOVSDconst OpAMD64MOVSSloadidx1 OpAMD64MOVSSloadidx4 OpAMD64MOVSDloadidx1 OpAMD64MOVSDloadidx8 OpAMD64MOVSSstore OpAMD64MOVSDstore OpAMD64MOVSSstoreidx1 OpAMD64MOVSSstoreidx4 OpAMD64MOVSDstoreidx1 OpAMD64MOVSDstoreidx8 OpAMD64ADDSSload OpAMD64ADDSDload OpAMD64SUBSSload OpAMD64SUBSDload OpAMD64MULSSload OpAMD64MULSDload OpAMD64DIVSSload OpAMD64DIVSDload OpAMD64ADDSSloadidx1 OpAMD64ADDSSloadidx4 OpAMD64ADDSDloadidx1 OpAMD64ADDSDloadidx8 OpAMD64SUBSSloadidx1 OpAMD64SUBSSloadidx4 OpAMD64SUBSDloadidx1 OpAMD64SUBSDloadidx8 OpAMD64MULSSloadidx1 OpAMD64MULSSloadidx4 OpAMD64MULSDloadidx1 OpAMD64MULSDloadidx8 OpAMD64DIVSSloadidx1 OpAMD64DIVSSloadidx4 OpAMD64DIVSDloadidx1 OpAMD64DIVSDloadidx8 OpAMD64ADDQ OpAMD64ADDL OpAMD64ADDQconst OpAMD64ADDLconst OpAMD64ADDQconstmodify OpAMD64ADDLconstmodify OpAMD64SUBQ OpAMD64SUBL OpAMD64SUBQconst OpAMD64SUBLconst OpAMD64MULQ OpAMD64MULL OpAMD64MULQconst OpAMD64MULLconst OpAMD64MULLU OpAMD64MULQU OpAMD64HMULQ OpAMD64HMULL OpAMD64HMULQU OpAMD64HMULLU OpAMD64AVGQU OpAMD64DIVQ OpAMD64DIVL OpAMD64DIVW OpAMD64DIVQU OpAMD64DIVLU OpAMD64DIVWU OpAMD64NEGLflags OpAMD64ADDQcarry OpAMD64ADCQ OpAMD64ADDQconstcarry OpAMD64ADCQconst OpAMD64SUBQborrow OpAMD64SBBQ OpAMD64SUBQconstborrow OpAMD64SBBQconst OpAMD64MULQU2 OpAMD64DIVQU2 OpAMD64ANDQ OpAMD64ANDL OpAMD64ANDQconst OpAMD64ANDLconst OpAMD64ANDQconstmodify OpAMD64ANDLconstmodify OpAMD64ORQ OpAMD64ORL OpAMD64ORQconst OpAMD64ORLconst OpAMD64ORQconstmodify OpAMD64ORLconstmodify OpAMD64XORQ OpAMD64XORL OpAMD64XORQconst OpAMD64XORLconst OpAMD64XORQconstmodify OpAMD64XORLconstmodify OpAMD64CMPQ OpAMD64CMPL OpAMD64CMPW OpAMD64CMPB OpAMD64CMPQconst OpAMD64CMPLconst OpAMD64CMPWconst OpAMD64CMPBconst OpAMD64CMPQload OpAMD64CMPLload OpAMD64CMPWload OpAMD64CMPBload OpAMD64CMPQconstload OpAMD64CMPLconstload OpAMD64CMPWconstload OpAMD64CMPBconstload OpAMD64CMPQloadidx8 OpAMD64CMPQloadidx1 OpAMD64CMPLloadidx4 OpAMD64CMPLloadidx1 OpAMD64CMPWloadidx2 OpAMD64CMPWloadidx1 OpAMD64CMPBloadidx1 OpAMD64CMPQconstloadidx8 OpAMD64CMPQconstloadidx1 OpAMD64CMPLconstloadidx4 OpAMD64CMPLconstloadidx1 OpAMD64CMPWconstloadidx2 OpAMD64CMPWconstloadidx1 OpAMD64CMPBconstloadidx1 OpAMD64UCOMISS OpAMD64UCOMISD OpAMD64BTL OpAMD64BTQ OpAMD64BTCL OpAMD64BTCQ OpAMD64BTRL OpAMD64BTRQ OpAMD64BTSL OpAMD64BTSQ OpAMD64BTLconst OpAMD64BTQconst OpAMD64BTCLconst OpAMD64BTCQconst OpAMD64BTRLconst OpAMD64BTRQconst OpAMD64BTSLconst OpAMD64BTSQconst OpAMD64TESTQ OpAMD64TESTL OpAMD64TESTW OpAMD64TESTB OpAMD64TESTQconst OpAMD64TESTLconst OpAMD64TESTWconst OpAMD64TESTBconst OpAMD64SHLQ OpAMD64SHLL OpAMD64SHLQconst OpAMD64SHLLconst OpAMD64SHRQ OpAMD64SHRL OpAMD64SHRW OpAMD64SHRB OpAMD64SHRQconst OpAMD64SHRLconst OpAMD64SHRWconst OpAMD64SHRBconst OpAMD64SARQ OpAMD64SARL OpAMD64SARW OpAMD64SARB OpAMD64SARQconst OpAMD64SARLconst OpAMD64SARWconst OpAMD64SARBconst OpAMD64SHRDQ OpAMD64SHLDQ OpAMD64ROLQ OpAMD64ROLL OpAMD64ROLW OpAMD64ROLB OpAMD64RORQ OpAMD64RORL OpAMD64RORW OpAMD64RORB OpAMD64ROLQconst OpAMD64ROLLconst OpAMD64ROLWconst OpAMD64ROLBconst OpAMD64ADDLload OpAMD64ADDQload OpAMD64SUBQload OpAMD64SUBLload OpAMD64ANDLload OpAMD64ANDQload OpAMD64ORQload OpAMD64ORLload OpAMD64XORQload OpAMD64XORLload OpAMD64ADDLloadidx1 OpAMD64ADDLloadidx4 OpAMD64ADDLloadidx8 OpAMD64ADDQloadidx1 OpAMD64ADDQloadidx8 OpAMD64SUBLloadidx1 OpAMD64SUBLloadidx4 OpAMD64SUBLloadidx8 OpAMD64SUBQloadidx1 OpAMD64SUBQloadidx8 OpAMD64ANDLloadidx1 OpAMD64ANDLloadidx4 OpAMD64ANDLloadidx8 OpAMD64ANDQloadidx1 OpAMD64ANDQloadidx8 OpAMD64ORLloadidx1 OpAMD64ORLloadidx4 OpAMD64ORLloadidx8 OpAMD64ORQloadidx1 OpAMD64ORQloadidx8 OpAMD64XORLloadidx1 OpAMD64XORLloadidx4 OpAMD64XORLloadidx8 OpAMD64XORQloadidx1 OpAMD64XORQloadidx8 OpAMD64ADDQmodify OpAMD64SUBQmodify OpAMD64ANDQmodify OpAMD64ORQmodify OpAMD64XORQmodify OpAMD64ADDLmodify OpAMD64SUBLmodify OpAMD64ANDLmodify OpAMD64ORLmodify OpAMD64XORLmodify OpAMD64ADDQmodifyidx1 OpAMD64ADDQmodifyidx8 OpAMD64SUBQmodifyidx1 OpAMD64SUBQmodifyidx8 OpAMD64ANDQmodifyidx1 OpAMD64ANDQmodifyidx8 OpAMD64ORQmodifyidx1 OpAMD64ORQmodifyidx8 OpAMD64XORQmodifyidx1 OpAMD64XORQmodifyidx8 OpAMD64ADDLmodifyidx1 OpAMD64ADDLmodifyidx4 OpAMD64ADDLmodifyidx8 OpAMD64SUBLmodifyidx1 OpAMD64SUBLmodifyidx4 OpAMD64SUBLmodifyidx8 OpAMD64ANDLmodifyidx1 OpAMD64ANDLmodifyidx4 OpAMD64ANDLmodifyidx8 OpAMD64ORLmodifyidx1 OpAMD64ORLmodifyidx4 OpAMD64ORLmodifyidx8 OpAMD64XORLmodifyidx1 OpAMD64XORLmodifyidx4 OpAMD64XORLmodifyidx8 OpAMD64ADDQconstmodifyidx1 OpAMD64ADDQconstmodifyidx8 OpAMD64ANDQconstmodifyidx1 OpAMD64ANDQconstmodifyidx8 OpAMD64ORQconstmodifyidx1 OpAMD64ORQconstmodifyidx8 OpAMD64XORQconstmodifyidx1 OpAMD64XORQconstmodifyidx8 OpAMD64ADDLconstmodifyidx1 OpAMD64ADDLconstmodifyidx4 OpAMD64ADDLconstmodifyidx8 OpAMD64ANDLconstmodifyidx1 OpAMD64ANDLconstmodifyidx4 OpAMD64ANDLconstmodifyidx8 OpAMD64ORLconstmodifyidx1 OpAMD64ORLconstmodifyidx4 OpAMD64ORLconstmodifyidx8 OpAMD64XORLconstmodifyidx1 OpAMD64XORLconstmodifyidx4 OpAMD64XORLconstmodifyidx8 OpAMD64NEGQ OpAMD64NEGL OpAMD64NOTQ OpAMD64NOTL OpAMD64BSFQ OpAMD64BSFL OpAMD64BSRQ OpAMD64BSRL OpAMD64CMOVQEQ OpAMD64CMOVQNE OpAMD64CMOVQLT OpAMD64CMOVQGT OpAMD64CMOVQLE OpAMD64CMOVQGE OpAMD64CMOVQLS OpAMD64CMOVQHI OpAMD64CMOVQCC OpAMD64CMOVQCS OpAMD64CMOVLEQ OpAMD64CMOVLNE OpAMD64CMOVLLT OpAMD64CMOVLGT OpAMD64CMOVLLE OpAMD64CMOVLGE OpAMD64CMOVLLS OpAMD64CMOVLHI OpAMD64CMOVLCC OpAMD64CMOVLCS OpAMD64CMOVWEQ OpAMD64CMOVWNE OpAMD64CMOVWLT OpAMD64CMOVWGT OpAMD64CMOVWLE OpAMD64CMOVWGE OpAMD64CMOVWLS OpAMD64CMOVWHI OpAMD64CMOVWCC OpAMD64CMOVWCS OpAMD64CMOVQEQF OpAMD64CMOVQNEF OpAMD64CMOVQGTF OpAMD64CMOVQGEF OpAMD64CMOVLEQF OpAMD64CMOVLNEF OpAMD64CMOVLGTF OpAMD64CMOVLGEF OpAMD64CMOVWEQF OpAMD64CMOVWNEF OpAMD64CMOVWGTF OpAMD64CMOVWGEF OpAMD64BSWAPQ OpAMD64BSWAPL OpAMD64POPCNTQ OpAMD64POPCNTL OpAMD64SQRTSD OpAMD64SQRTSS OpAMD64ROUNDSD OpAMD64VFMADD231SD OpAMD64SBBQcarrymask OpAMD64SBBLcarrymask OpAMD64SETEQ OpAMD64SETNE OpAMD64SETL OpAMD64SETLE OpAMD64SETG OpAMD64SETGE OpAMD64SETB OpAMD64SETBE OpAMD64SETA OpAMD64SETAE OpAMD64SETO OpAMD64SETEQstore OpAMD64SETNEstore OpAMD64SETLstore OpAMD64SETLEstore OpAMD64SETGstore OpAMD64SETGEstore OpAMD64SETBstore OpAMD64SETBEstore OpAMD64SETAstore OpAMD64SETAEstore OpAMD64SETEQF OpAMD64SETNEF OpAMD64SETORD OpAMD64SETNAN OpAMD64SETGF OpAMD64SETGEF OpAMD64MOVBQSX OpAMD64MOVBQZX OpAMD64MOVWQSX OpAMD64MOVWQZX OpAMD64MOVLQSX OpAMD64MOVLQZX OpAMD64MOVLconst OpAMD64MOVQconst OpAMD64CVTTSD2SL OpAMD64CVTTSD2SQ OpAMD64CVTTSS2SL OpAMD64CVTTSS2SQ OpAMD64CVTSL2SS OpAMD64CVTSL2SD OpAMD64CVTSQ2SS OpAMD64CVTSQ2SD OpAMD64CVTSD2SS OpAMD64CVTSS2SD OpAMD64MOVQi2f OpAMD64MOVQf2i OpAMD64MOVLi2f OpAMD64MOVLf2i OpAMD64PXOR OpAMD64LEAQ OpAMD64LEAL OpAMD64LEAW OpAMD64LEAQ1 OpAMD64LEAL1 OpAMD64LEAW1 OpAMD64LEAQ2 OpAMD64LEAL2 OpAMD64LEAW2 OpAMD64LEAQ4 OpAMD64LEAL4 OpAMD64LEAW4 OpAMD64LEAQ8 OpAMD64LEAL8 OpAMD64LEAW8 OpAMD64MOVBload OpAMD64MOVBQSXload OpAMD64MOVWload OpAMD64MOVWQSXload OpAMD64MOVLload OpAMD64MOVLQSXload OpAMD64MOVQload OpAMD64MOVBstore OpAMD64MOVWstore OpAMD64MOVLstore OpAMD64MOVQstore OpAMD64MOVOload OpAMD64MOVOstore OpAMD64MOVBloadidx1 OpAMD64MOVWloadidx1 OpAMD64MOVWloadidx2 OpAMD64MOVLloadidx1 OpAMD64MOVLloadidx4 OpAMD64MOVLloadidx8 OpAMD64MOVQloadidx1 OpAMD64MOVQloadidx8 OpAMD64MOVBstoreidx1 OpAMD64MOVWstoreidx1 OpAMD64MOVWstoreidx2 OpAMD64MOVLstoreidx1 OpAMD64MOVLstoreidx4 OpAMD64MOVLstoreidx8 OpAMD64MOVQstoreidx1 OpAMD64MOVQstoreidx8 OpAMD64MOVBstoreconst OpAMD64MOVWstoreconst OpAMD64MOVLstoreconst OpAMD64MOVQstoreconst OpAMD64MOVOstoreconst OpAMD64MOVBstoreconstidx1 OpAMD64MOVWstoreconstidx1 OpAMD64MOVWstoreconstidx2 OpAMD64MOVLstoreconstidx1 OpAMD64MOVLstoreconstidx4 OpAMD64MOVQstoreconstidx1 OpAMD64MOVQstoreconstidx8 OpAMD64DUFFZERO OpAMD64REPSTOSQ OpAMD64CALLstatic OpAMD64CALLtail OpAMD64CALLclosure OpAMD64CALLinter OpAMD64DUFFCOPY OpAMD64REPMOVSQ OpAMD64InvertFlags OpAMD64LoweredGetG OpAMD64LoweredGetClosurePtr OpAMD64LoweredGetCallerPC OpAMD64LoweredGetCallerSP OpAMD64LoweredNilCheck OpAMD64LoweredWB OpAMD64LoweredHasCPUFeature OpAMD64LoweredPanicBoundsA OpAMD64LoweredPanicBoundsB OpAMD64LoweredPanicBoundsC OpAMD64FlagEQ OpAMD64FlagLT_ULT OpAMD64FlagLT_UGT OpAMD64FlagGT_UGT OpAMD64FlagGT_ULT OpAMD64MOVBatomicload OpAMD64MOVLatomicload OpAMD64MOVQatomicload OpAMD64XCHGB OpAMD64XCHGL OpAMD64XCHGQ OpAMD64XADDLlock OpAMD64XADDQlock OpAMD64AddTupleFirst32 OpAMD64AddTupleFirst64 OpAMD64CMPXCHGLlock OpAMD64CMPXCHGQlock OpAMD64ANDBlock OpAMD64ANDLlock OpAMD64ORBlock OpAMD64ORLlock OpAMD64PrefetchT0 OpAMD64PrefetchNTA OpAMD64ANDNQ OpAMD64ANDNL OpAMD64BLSIQ OpAMD64BLSIL OpAMD64BLSMSKQ OpAMD64BLSMSKL OpAMD64BLSRQ OpAMD64BLSRL OpAMD64TZCNTQ OpAMD64TZCNTL OpAMD64LZCNTQ OpAMD64LZCNTL OpAMD64MOVBEWstore OpAMD64MOVBELload OpAMD64MOVBELstore OpAMD64MOVBEQload OpAMD64MOVBEQstore OpAMD64MOVBELloadidx1 OpAMD64MOVBELloadidx4 OpAMD64MOVBELloadidx8 OpAMD64MOVBEQloadidx1 OpAMD64MOVBEQloadidx8 OpAMD64MOVBEWstoreidx1 OpAMD64MOVBEWstoreidx2 OpAMD64MOVBELstoreidx1 OpAMD64MOVBELstoreidx4 OpAMD64MOVBELstoreidx8 OpAMD64MOVBEQstoreidx1 OpAMD64MOVBEQstoreidx8 OpAMD64SARXQ OpAMD64SARXL OpAMD64SHLXQ OpAMD64SHLXL OpAMD64SHRXQ OpAMD64SHRXL OpAMD64SARXLload OpAMD64SARXQload OpAMD64SHLXLload OpAMD64SHLXQload OpAMD64SHRXLload OpAMD64SHRXQload OpAMD64SARXLloadidx1 OpAMD64SARXLloadidx4 OpAMD64SARXLloadidx8 OpAMD64SARXQloadidx1 OpAMD64SARXQloadidx8 OpAMD64SHLXLloadidx1 OpAMD64SHLXLloadidx4 OpAMD64SHLXLloadidx8 OpAMD64SHLXQloadidx1 OpAMD64SHLXQloadidx8 OpAMD64SHRXLloadidx1 OpAMD64SHRXLloadidx4 OpAMD64SHRXLloadidx8 OpAMD64SHRXQloadidx1 OpAMD64SHRXQloadidx8 OpARMADD OpARMADDconst OpARMSUB OpARMSUBconst OpARMRSB OpARMRSBconst OpARMMUL OpARMHMUL OpARMHMULU OpARMCALLudiv OpARMADDS OpARMADDSconst OpARMADC OpARMADCconst OpARMSUBS OpARMSUBSconst OpARMRSBSconst OpARMSBC OpARMSBCconst OpARMRSCconst OpARMMULLU OpARMMULA OpARMMULS OpARMADDF OpARMADDD OpARMSUBF OpARMSUBD OpARMMULF OpARMMULD OpARMNMULF OpARMNMULD OpARMDIVF OpARMDIVD OpARMMULAF OpARMMULAD OpARMMULSF OpARMMULSD OpARMFMULAD OpARMAND OpARMANDconst OpARMOR OpARMORconst OpARMXOR OpARMXORconst OpARMBIC OpARMBICconst OpARMBFX OpARMBFXU OpARMMVN OpARMNEGF OpARMNEGD OpARMSQRTD OpARMSQRTF OpARMABSD OpARMCLZ OpARMREV OpARMREV16 OpARMRBIT OpARMSLL OpARMSLLconst OpARMSRL OpARMSRLconst OpARMSRA OpARMSRAconst OpARMSRR OpARMSRRconst OpARMADDshiftLL OpARMADDshiftRL OpARMADDshiftRA OpARMSUBshiftLL OpARMSUBshiftRL OpARMSUBshiftRA OpARMRSBshiftLL OpARMRSBshiftRL OpARMRSBshiftRA OpARMANDshiftLL OpARMANDshiftRL OpARMANDshiftRA OpARMORshiftLL OpARMORshiftRL OpARMORshiftRA OpARMXORshiftLL OpARMXORshiftRL OpARMXORshiftRA OpARMXORshiftRR OpARMBICshiftLL OpARMBICshiftRL OpARMBICshiftRA OpARMMVNshiftLL OpARMMVNshiftRL OpARMMVNshiftRA OpARMADCshiftLL OpARMADCshiftRL OpARMADCshiftRA OpARMSBCshiftLL OpARMSBCshiftRL OpARMSBCshiftRA OpARMRSCshiftLL OpARMRSCshiftRL OpARMRSCshiftRA OpARMADDSshiftLL OpARMADDSshiftRL OpARMADDSshiftRA OpARMSUBSshiftLL OpARMSUBSshiftRL OpARMSUBSshiftRA OpARMRSBSshiftLL OpARMRSBSshiftRL OpARMRSBSshiftRA OpARMADDshiftLLreg OpARMADDshiftRLreg OpARMADDshiftRAreg OpARMSUBshiftLLreg OpARMSUBshiftRLreg OpARMSUBshiftRAreg OpARMRSBshiftLLreg OpARMRSBshiftRLreg OpARMRSBshiftRAreg OpARMANDshiftLLreg OpARMANDshiftRLreg OpARMANDshiftRAreg OpARMORshiftLLreg OpARMORshiftRLreg OpARMORshiftRAreg OpARMXORshiftLLreg OpARMXORshiftRLreg OpARMXORshiftRAreg OpARMBICshiftLLreg OpARMBICshiftRLreg OpARMBICshiftRAreg OpARMMVNshiftLLreg OpARMMVNshiftRLreg OpARMMVNshiftRAreg OpARMADCshiftLLreg OpARMADCshiftRLreg OpARMADCshiftRAreg OpARMSBCshiftLLreg OpARMSBCshiftRLreg OpARMSBCshiftRAreg OpARMRSCshiftLLreg OpARMRSCshiftRLreg OpARMRSCshiftRAreg OpARMADDSshiftLLreg OpARMADDSshiftRLreg OpARMADDSshiftRAreg OpARMSUBSshiftLLreg OpARMSUBSshiftRLreg OpARMSUBSshiftRAreg OpARMRSBSshiftLLreg OpARMRSBSshiftRLreg OpARMRSBSshiftRAreg OpARMCMP OpARMCMPconst OpARMCMN OpARMCMNconst OpARMTST OpARMTSTconst OpARMTEQ OpARMTEQconst OpARMCMPF OpARMCMPD OpARMCMPshiftLL OpARMCMPshiftRL OpARMCMPshiftRA OpARMCMNshiftLL OpARMCMNshiftRL OpARMCMNshiftRA OpARMTSTshiftLL OpARMTSTshiftRL OpARMTSTshiftRA OpARMTEQshiftLL OpARMTEQshiftRL OpARMTEQshiftRA OpARMCMPshiftLLreg OpARMCMPshiftRLreg OpARMCMPshiftRAreg OpARMCMNshiftLLreg OpARMCMNshiftRLreg OpARMCMNshiftRAreg OpARMTSTshiftLLreg OpARMTSTshiftRLreg OpARMTSTshiftRAreg OpARMTEQshiftLLreg OpARMTEQshiftRLreg OpARMTEQshiftRAreg OpARMCMPF0 OpARMCMPD0 OpARMMOVWconst OpARMMOVFconst OpARMMOVDconst OpARMMOVWaddr OpARMMOVBload OpARMMOVBUload OpARMMOVHload OpARMMOVHUload OpARMMOVWload OpARMMOVFload OpARMMOVDload OpARMMOVBstore OpARMMOVHstore OpARMMOVWstore OpARMMOVFstore OpARMMOVDstore OpARMMOVWloadidx OpARMMOVWloadshiftLL OpARMMOVWloadshiftRL OpARMMOVWloadshiftRA OpARMMOVBUloadidx OpARMMOVBloadidx OpARMMOVHUloadidx OpARMMOVHloadidx OpARMMOVWstoreidx OpARMMOVWstoreshiftLL OpARMMOVWstoreshiftRL OpARMMOVWstoreshiftRA OpARMMOVBstoreidx OpARMMOVHstoreidx OpARMMOVBreg OpARMMOVBUreg OpARMMOVHreg OpARMMOVHUreg OpARMMOVWreg OpARMMOVWnop OpARMMOVWF OpARMMOVWD OpARMMOVWUF OpARMMOVWUD OpARMMOVFW OpARMMOVDW OpARMMOVFWU OpARMMOVDWU OpARMMOVFD OpARMMOVDF OpARMCMOVWHSconst OpARMCMOVWLSconst OpARMSRAcond OpARMCALLstatic OpARMCALLtail OpARMCALLclosure OpARMCALLinter OpARMLoweredNilCheck OpARMEqual OpARMNotEqual OpARMLessThan OpARMLessEqual OpARMGreaterThan OpARMGreaterEqual OpARMLessThanU OpARMLessEqualU OpARMGreaterThanU OpARMGreaterEqualU OpARMDUFFZERO OpARMDUFFCOPY OpARMLoweredZero OpARMLoweredMove OpARMLoweredGetClosurePtr OpARMLoweredGetCallerSP OpARMLoweredGetCallerPC OpARMLoweredPanicBoundsA OpARMLoweredPanicBoundsB OpARMLoweredPanicBoundsC OpARMLoweredPanicExtendA OpARMLoweredPanicExtendB OpARMLoweredPanicExtendC OpARMFlagConstant OpARMInvertFlags OpARMLoweredWB OpARM64ADCSflags OpARM64ADCzerocarry OpARM64ADD OpARM64ADDconst OpARM64ADDSconstflags OpARM64ADDSflags OpARM64SUB OpARM64SUBconst OpARM64SBCSflags OpARM64SUBSflags OpARM64MUL OpARM64MULW OpARM64MNEG OpARM64MNEGW OpARM64MULH OpARM64UMULH OpARM64MULL OpARM64UMULL OpARM64DIV OpARM64UDIV OpARM64DIVW OpARM64UDIVW OpARM64MOD OpARM64UMOD OpARM64MODW OpARM64UMODW OpARM64FADDS OpARM64FADDD OpARM64FSUBS OpARM64FSUBD OpARM64FMULS OpARM64FMULD OpARM64FNMULS OpARM64FNMULD OpARM64FDIVS OpARM64FDIVD OpARM64AND OpARM64ANDconst OpARM64OR OpARM64ORconst OpARM64XOR OpARM64XORconst OpARM64BIC OpARM64EON OpARM64ORN OpARM64LoweredMuluhilo OpARM64MVN OpARM64NEG OpARM64NEGSflags OpARM64NGCzerocarry OpARM64FABSD OpARM64FNEGS OpARM64FNEGD OpARM64FSQRTD OpARM64FSQRTS OpARM64REV OpARM64REVW OpARM64REV16 OpARM64REV16W OpARM64RBIT OpARM64RBITW OpARM64CLZ OpARM64CLZW OpARM64VCNT OpARM64VUADDLV OpARM64LoweredRound32F OpARM64LoweredRound64F OpARM64FMADDS OpARM64FMADDD OpARM64FNMADDS OpARM64FNMADDD OpARM64FMSUBS OpARM64FMSUBD OpARM64FNMSUBS OpARM64FNMSUBD OpARM64MADD OpARM64MADDW OpARM64MSUB OpARM64MSUBW OpARM64SLL OpARM64SLLconst OpARM64SRL OpARM64SRLconst OpARM64SRA OpARM64SRAconst OpARM64ROR OpARM64RORW OpARM64RORconst OpARM64RORWconst OpARM64EXTRconst OpARM64EXTRWconst OpARM64CMP OpARM64CMPconst OpARM64CMPW OpARM64CMPWconst OpARM64CMN OpARM64CMNconst OpARM64CMNW OpARM64CMNWconst OpARM64TST OpARM64TSTconst OpARM64TSTW OpARM64TSTWconst OpARM64FCMPS OpARM64FCMPD OpARM64FCMPS0 OpARM64FCMPD0 OpARM64MVNshiftLL OpARM64MVNshiftRL OpARM64MVNshiftRA OpARM64MVNshiftRO OpARM64NEGshiftLL OpARM64NEGshiftRL OpARM64NEGshiftRA OpARM64ADDshiftLL OpARM64ADDshiftRL OpARM64ADDshiftRA OpARM64SUBshiftLL OpARM64SUBshiftRL OpARM64SUBshiftRA OpARM64ANDshiftLL OpARM64ANDshiftRL OpARM64ANDshiftRA OpARM64ANDshiftRO OpARM64ORshiftLL OpARM64ORshiftRL OpARM64ORshiftRA OpARM64ORshiftRO OpARM64XORshiftLL OpARM64XORshiftRL OpARM64XORshiftRA OpARM64XORshiftRO OpARM64BICshiftLL OpARM64BICshiftRL OpARM64BICshiftRA OpARM64BICshiftRO OpARM64EONshiftLL OpARM64EONshiftRL OpARM64EONshiftRA OpARM64EONshiftRO OpARM64ORNshiftLL OpARM64ORNshiftRL OpARM64ORNshiftRA OpARM64ORNshiftRO OpARM64CMPshiftLL OpARM64CMPshiftRL OpARM64CMPshiftRA OpARM64CMNshiftLL OpARM64CMNshiftRL OpARM64CMNshiftRA OpARM64TSTshiftLL OpARM64TSTshiftRL OpARM64TSTshiftRA OpARM64TSTshiftRO OpARM64BFI OpARM64BFXIL OpARM64SBFIZ OpARM64SBFX OpARM64UBFIZ OpARM64UBFX OpARM64MOVDconst OpARM64FMOVSconst OpARM64FMOVDconst OpARM64MOVDaddr OpARM64MOVBload OpARM64MOVBUload OpARM64MOVHload OpARM64MOVHUload OpARM64MOVWload OpARM64MOVWUload OpARM64MOVDload OpARM64FMOVSload OpARM64FMOVDload OpARM64MOVDloadidx OpARM64MOVWloadidx OpARM64MOVWUloadidx OpARM64MOVHloadidx OpARM64MOVHUloadidx OpARM64MOVBloadidx OpARM64MOVBUloadidx OpARM64FMOVSloadidx OpARM64FMOVDloadidx OpARM64MOVHloadidx2 OpARM64MOVHUloadidx2 OpARM64MOVWloadidx4 OpARM64MOVWUloadidx4 OpARM64MOVDloadidx8 OpARM64FMOVSloadidx4 OpARM64FMOVDloadidx8 OpARM64MOVBstore OpARM64MOVHstore OpARM64MOVWstore OpARM64MOVDstore OpARM64STP OpARM64FMOVSstore OpARM64FMOVDstore OpARM64MOVBstoreidx OpARM64MOVHstoreidx OpARM64MOVWstoreidx OpARM64MOVDstoreidx OpARM64FMOVSstoreidx OpARM64FMOVDstoreidx OpARM64MOVHstoreidx2 OpARM64MOVWstoreidx4 OpARM64MOVDstoreidx8 OpARM64FMOVSstoreidx4 OpARM64FMOVDstoreidx8 OpARM64MOVBstorezero OpARM64MOVHstorezero OpARM64MOVWstorezero OpARM64MOVDstorezero OpARM64MOVQstorezero OpARM64MOVBstorezeroidx OpARM64MOVHstorezeroidx OpARM64MOVWstorezeroidx OpARM64MOVDstorezeroidx OpARM64MOVHstorezeroidx2 OpARM64MOVWstorezeroidx4 OpARM64MOVDstorezeroidx8 OpARM64FMOVDgpfp OpARM64FMOVDfpgp OpARM64FMOVSgpfp OpARM64FMOVSfpgp OpARM64MOVBreg OpARM64MOVBUreg OpARM64MOVHreg OpARM64MOVHUreg OpARM64MOVWreg OpARM64MOVWUreg OpARM64MOVDreg OpARM64MOVDnop OpARM64SCVTFWS OpARM64SCVTFWD OpARM64UCVTFWS OpARM64UCVTFWD OpARM64SCVTFS OpARM64SCVTFD OpARM64UCVTFS OpARM64UCVTFD OpARM64FCVTZSSW OpARM64FCVTZSDW OpARM64FCVTZUSW OpARM64FCVTZUDW OpARM64FCVTZSS OpARM64FCVTZSD OpARM64FCVTZUS OpARM64FCVTZUD OpARM64FCVTSD OpARM64FCVTDS OpARM64FRINTAD OpARM64FRINTMD OpARM64FRINTND OpARM64FRINTPD OpARM64FRINTZD OpARM64CSEL OpARM64CSEL0 OpARM64CSINC OpARM64CSINV OpARM64CSNEG OpARM64CSETM OpARM64CALLstatic OpARM64CALLtail OpARM64CALLclosure OpARM64CALLinter OpARM64LoweredNilCheck OpARM64Equal OpARM64NotEqual OpARM64LessThan OpARM64LessEqual OpARM64GreaterThan OpARM64GreaterEqual OpARM64LessThanU OpARM64LessEqualU OpARM64GreaterThanU OpARM64GreaterEqualU OpARM64LessThanF OpARM64LessEqualF OpARM64GreaterThanF OpARM64GreaterEqualF OpARM64NotLessThanF OpARM64NotLessEqualF OpARM64NotGreaterThanF OpARM64NotGreaterEqualF OpARM64DUFFZERO OpARM64LoweredZero OpARM64DUFFCOPY OpARM64LoweredMove OpARM64LoweredGetClosurePtr OpARM64LoweredGetCallerSP OpARM64LoweredGetCallerPC OpARM64FlagConstant OpARM64InvertFlags OpARM64LDAR OpARM64LDARB OpARM64LDARW OpARM64STLRB OpARM64STLR OpARM64STLRW OpARM64LoweredAtomicExchange64 OpARM64LoweredAtomicExchange32 OpARM64LoweredAtomicExchange64Variant OpARM64LoweredAtomicExchange32Variant OpARM64LoweredAtomicAdd64 OpARM64LoweredAtomicAdd32 OpARM64LoweredAtomicAdd64Variant OpARM64LoweredAtomicAdd32Variant OpARM64LoweredAtomicCas64 OpARM64LoweredAtomicCas32 OpARM64LoweredAtomicCas64Variant OpARM64LoweredAtomicCas32Variant OpARM64LoweredAtomicAnd8 OpARM64LoweredAtomicAnd32 OpARM64LoweredAtomicOr8 OpARM64LoweredAtomicOr32 OpARM64LoweredAtomicAnd8Variant OpARM64LoweredAtomicAnd32Variant OpARM64LoweredAtomicOr8Variant OpARM64LoweredAtomicOr32Variant OpARM64LoweredWB OpARM64LoweredPanicBoundsA OpARM64LoweredPanicBoundsB OpARM64LoweredPanicBoundsC OpARM64PRFM OpARM64DMB OpMIPSADD OpMIPSADDconst OpMIPSSUB OpMIPSSUBconst OpMIPSMUL OpMIPSMULT OpMIPSMULTU OpMIPSDIV OpMIPSDIVU OpMIPSADDF OpMIPSADDD OpMIPSSUBF OpMIPSSUBD OpMIPSMULF OpMIPSMULD OpMIPSDIVF OpMIPSDIVD OpMIPSAND OpMIPSANDconst OpMIPSOR OpMIPSORconst OpMIPSXOR OpMIPSXORconst OpMIPSNOR OpMIPSNORconst OpMIPSNEG OpMIPSNEGF OpMIPSNEGD OpMIPSSQRTD OpMIPSSQRTF OpMIPSSLL OpMIPSSLLconst OpMIPSSRL OpMIPSSRLconst OpMIPSSRA OpMIPSSRAconst OpMIPSCLZ OpMIPSSGT OpMIPSSGTconst OpMIPSSGTzero OpMIPSSGTU OpMIPSSGTUconst OpMIPSSGTUzero OpMIPSCMPEQF OpMIPSCMPEQD OpMIPSCMPGEF OpMIPSCMPGED OpMIPSCMPGTF OpMIPSCMPGTD OpMIPSMOVWconst OpMIPSMOVFconst OpMIPSMOVDconst OpMIPSMOVWaddr OpMIPSMOVBload OpMIPSMOVBUload OpMIPSMOVHload OpMIPSMOVHUload OpMIPSMOVWload OpMIPSMOVFload OpMIPSMOVDload OpMIPSMOVBstore OpMIPSMOVHstore OpMIPSMOVWstore OpMIPSMOVFstore OpMIPSMOVDstore OpMIPSMOVBstorezero OpMIPSMOVHstorezero OpMIPSMOVWstorezero OpMIPSMOVBreg OpMIPSMOVBUreg OpMIPSMOVHreg OpMIPSMOVHUreg OpMIPSMOVWreg OpMIPSMOVWnop OpMIPSCMOVZ OpMIPSCMOVZzero OpMIPSMOVWF OpMIPSMOVWD OpMIPSTRUNCFW OpMIPSTRUNCDW OpMIPSMOVFD OpMIPSMOVDF OpMIPSCALLstatic OpMIPSCALLtail OpMIPSCALLclosure OpMIPSCALLinter OpMIPSLoweredAtomicLoad8 OpMIPSLoweredAtomicLoad32 OpMIPSLoweredAtomicStore8 OpMIPSLoweredAtomicStore32 OpMIPSLoweredAtomicStorezero OpMIPSLoweredAtomicExchange OpMIPSLoweredAtomicAdd OpMIPSLoweredAtomicAddconst OpMIPSLoweredAtomicCas OpMIPSLoweredAtomicAnd OpMIPSLoweredAtomicOr OpMIPSLoweredZero OpMIPSLoweredMove OpMIPSLoweredNilCheck OpMIPSFPFlagTrue OpMIPSFPFlagFalse OpMIPSLoweredGetClosurePtr OpMIPSLoweredGetCallerSP OpMIPSLoweredGetCallerPC OpMIPSLoweredWB OpMIPSLoweredPanicBoundsA OpMIPSLoweredPanicBoundsB OpMIPSLoweredPanicBoundsC OpMIPSLoweredPanicExtendA OpMIPSLoweredPanicExtendB OpMIPSLoweredPanicExtendC OpMIPS64ADDV OpMIPS64ADDVconst OpMIPS64SUBV OpMIPS64SUBVconst OpMIPS64MULV OpMIPS64MULVU OpMIPS64DIVV OpMIPS64DIVVU OpMIPS64ADDF OpMIPS64ADDD OpMIPS64SUBF OpMIPS64SUBD OpMIPS64MULF OpMIPS64MULD OpMIPS64DIVF OpMIPS64DIVD OpMIPS64AND OpMIPS64ANDconst OpMIPS64OR OpMIPS64ORconst OpMIPS64XOR OpMIPS64XORconst OpMIPS64NOR OpMIPS64NORconst OpMIPS64NEGV OpMIPS64NEGF OpMIPS64NEGD OpMIPS64SQRTD OpMIPS64SQRTF OpMIPS64SLLV OpMIPS64SLLVconst OpMIPS64SRLV OpMIPS64SRLVconst OpMIPS64SRAV OpMIPS64SRAVconst OpMIPS64SGT OpMIPS64SGTconst OpMIPS64SGTU OpMIPS64SGTUconst OpMIPS64CMPEQF OpMIPS64CMPEQD OpMIPS64CMPGEF OpMIPS64CMPGED OpMIPS64CMPGTF OpMIPS64CMPGTD OpMIPS64MOVVconst OpMIPS64MOVFconst OpMIPS64MOVDconst OpMIPS64MOVVaddr OpMIPS64MOVBload OpMIPS64MOVBUload OpMIPS64MOVHload OpMIPS64MOVHUload OpMIPS64MOVWload OpMIPS64MOVWUload OpMIPS64MOVVload OpMIPS64MOVFload OpMIPS64MOVDload OpMIPS64MOVBstore OpMIPS64MOVHstore OpMIPS64MOVWstore OpMIPS64MOVVstore OpMIPS64MOVFstore OpMIPS64MOVDstore OpMIPS64MOVBstorezero OpMIPS64MOVHstorezero OpMIPS64MOVWstorezero OpMIPS64MOVVstorezero OpMIPS64MOVBreg OpMIPS64MOVBUreg OpMIPS64MOVHreg OpMIPS64MOVHUreg OpMIPS64MOVWreg OpMIPS64MOVWUreg OpMIPS64MOVVreg OpMIPS64MOVVnop OpMIPS64MOVWF OpMIPS64MOVWD OpMIPS64MOVVF OpMIPS64MOVVD OpMIPS64TRUNCFW OpMIPS64TRUNCDW OpMIPS64TRUNCFV OpMIPS64TRUNCDV OpMIPS64MOVFD OpMIPS64MOVDF OpMIPS64CALLstatic OpMIPS64CALLtail OpMIPS64CALLclosure OpMIPS64CALLinter OpMIPS64DUFFZERO OpMIPS64DUFFCOPY OpMIPS64LoweredZero OpMIPS64LoweredMove OpMIPS64LoweredAtomicLoad8 OpMIPS64LoweredAtomicLoad32 OpMIPS64LoweredAtomicLoad64 OpMIPS64LoweredAtomicStore8 OpMIPS64LoweredAtomicStore32 OpMIPS64LoweredAtomicStore64 OpMIPS64LoweredAtomicStorezero32 OpMIPS64LoweredAtomicStorezero64 OpMIPS64LoweredAtomicExchange32 OpMIPS64LoweredAtomicExchange64 OpMIPS64LoweredAtomicAdd32 OpMIPS64LoweredAtomicAdd64 OpMIPS64LoweredAtomicAddconst32 OpMIPS64LoweredAtomicAddconst64 OpMIPS64LoweredAtomicCas32 OpMIPS64LoweredAtomicCas64 OpMIPS64LoweredNilCheck OpMIPS64FPFlagTrue OpMIPS64FPFlagFalse OpMIPS64LoweredGetClosurePtr OpMIPS64LoweredGetCallerSP OpMIPS64LoweredGetCallerPC OpMIPS64LoweredWB OpMIPS64LoweredPanicBoundsA OpMIPS64LoweredPanicBoundsB OpMIPS64LoweredPanicBoundsC OpPPC64ADD OpPPC64ADDconst OpPPC64FADD OpPPC64FADDS OpPPC64SUB OpPPC64SUBFCconst OpPPC64FSUB OpPPC64FSUBS OpPPC64MULLD OpPPC64MULLW OpPPC64MULLDconst OpPPC64MULLWconst OpPPC64MADDLD OpPPC64MULHD OpPPC64MULHW OpPPC64MULHDU OpPPC64MULHWU OpPPC64LoweredMuluhilo OpPPC64FMUL OpPPC64FMULS OpPPC64FMADD OpPPC64FMADDS OpPPC64FMSUB OpPPC64FMSUBS OpPPC64SRAD OpPPC64SRAW OpPPC64SRD OpPPC64SRW OpPPC64SLD OpPPC64SLW OpPPC64ROTL OpPPC64ROTLW OpPPC64RLDICL OpPPC64CLRLSLWI OpPPC64CLRLSLDI OpPPC64ADDC OpPPC64SUBC OpPPC64ADDCconst OpPPC64SUBCconst OpPPC64ADDE OpPPC64SUBE OpPPC64ADDZEzero OpPPC64SUBZEzero OpPPC64SRADconst OpPPC64SRAWconst OpPPC64SRDconst OpPPC64SRWconst OpPPC64SLDconst OpPPC64SLWconst OpPPC64ROTLconst OpPPC64ROTLWconst OpPPC64EXTSWSLconst OpPPC64RLWINM OpPPC64RLWNM OpPPC64RLWMI OpPPC64CNTLZD OpPPC64CNTLZW OpPPC64CNTTZD OpPPC64CNTTZW OpPPC64POPCNTD OpPPC64POPCNTW OpPPC64POPCNTB OpPPC64FDIV OpPPC64FDIVS OpPPC64DIVD OpPPC64DIVW OpPPC64DIVDU OpPPC64DIVWU OpPPC64MODUD OpPPC64MODSD OpPPC64MODUW OpPPC64MODSW OpPPC64FCTIDZ OpPPC64FCTIWZ OpPPC64FCFID OpPPC64FCFIDS OpPPC64FRSP OpPPC64MFVSRD OpPPC64MTVSRD OpPPC64AND OpPPC64ANDN OpPPC64ANDCC OpPPC64OR OpPPC64ORN OpPPC64ORCC OpPPC64NOR OpPPC64XOR OpPPC64XORCC OpPPC64EQV OpPPC64NEG OpPPC64FNEG OpPPC64FSQRT OpPPC64FSQRTS OpPPC64FFLOOR OpPPC64FCEIL OpPPC64FTRUNC OpPPC64FROUND OpPPC64FABS OpPPC64FNABS OpPPC64FCPSGN OpPPC64ORconst OpPPC64XORconst OpPPC64ANDconst OpPPC64ANDCCconst OpPPC64MOVBreg OpPPC64MOVBZreg OpPPC64MOVHreg OpPPC64MOVHZreg OpPPC64MOVWreg OpPPC64MOVWZreg OpPPC64MOVBZload OpPPC64MOVHload OpPPC64MOVHZload OpPPC64MOVWload OpPPC64MOVWZload OpPPC64MOVDload OpPPC64MOVDBRload OpPPC64MOVWBRload OpPPC64MOVHBRload OpPPC64MOVBZloadidx OpPPC64MOVHloadidx OpPPC64MOVHZloadidx OpPPC64MOVWloadidx OpPPC64MOVWZloadidx OpPPC64MOVDloadidx OpPPC64MOVHBRloadidx OpPPC64MOVWBRloadidx OpPPC64MOVDBRloadidx OpPPC64FMOVDloadidx OpPPC64FMOVSloadidx OpPPC64DCBT OpPPC64MOVDBRstore OpPPC64MOVWBRstore OpPPC64MOVHBRstore OpPPC64FMOVDload OpPPC64FMOVSload OpPPC64MOVBstore OpPPC64MOVHstore OpPPC64MOVWstore OpPPC64MOVDstore OpPPC64FMOVDstore OpPPC64FMOVSstore OpPPC64MOVBstoreidx OpPPC64MOVHstoreidx OpPPC64MOVWstoreidx OpPPC64MOVDstoreidx OpPPC64FMOVDstoreidx OpPPC64FMOVSstoreidx OpPPC64MOVHBRstoreidx OpPPC64MOVWBRstoreidx OpPPC64MOVDBRstoreidx OpPPC64MOVBstorezero OpPPC64MOVHstorezero OpPPC64MOVWstorezero OpPPC64MOVDstorezero OpPPC64MOVDaddr OpPPC64MOVDconst OpPPC64FMOVDconst OpPPC64FMOVSconst OpPPC64FCMPU OpPPC64CMP OpPPC64CMPU OpPPC64CMPW OpPPC64CMPWU OpPPC64CMPconst OpPPC64CMPUconst OpPPC64CMPWconst OpPPC64CMPWUconst OpPPC64ISEL OpPPC64ISELB OpPPC64Equal OpPPC64NotEqual OpPPC64LessThan OpPPC64FLessThan OpPPC64LessEqual OpPPC64FLessEqual OpPPC64GreaterThan OpPPC64FGreaterThan OpPPC64GreaterEqual OpPPC64FGreaterEqual OpPPC64LoweredGetClosurePtr OpPPC64LoweredGetCallerSP OpPPC64LoweredGetCallerPC OpPPC64LoweredNilCheck OpPPC64LoweredRound32F OpPPC64LoweredRound64F OpPPC64CALLstatic OpPPC64CALLtail OpPPC64CALLclosure OpPPC64CALLinter OpPPC64LoweredZero OpPPC64LoweredZeroShort OpPPC64LoweredQuadZeroShort OpPPC64LoweredQuadZero OpPPC64LoweredMove OpPPC64LoweredMoveShort OpPPC64LoweredQuadMove OpPPC64LoweredQuadMoveShort OpPPC64LoweredAtomicStore8 OpPPC64LoweredAtomicStore32 OpPPC64LoweredAtomicStore64 OpPPC64LoweredAtomicLoad8 OpPPC64LoweredAtomicLoad32 OpPPC64LoweredAtomicLoad64 OpPPC64LoweredAtomicLoadPtr OpPPC64LoweredAtomicAdd32 OpPPC64LoweredAtomicAdd64 OpPPC64LoweredAtomicExchange32 OpPPC64LoweredAtomicExchange64 OpPPC64LoweredAtomicCas64 OpPPC64LoweredAtomicCas32 OpPPC64LoweredAtomicAnd8 OpPPC64LoweredAtomicAnd32 OpPPC64LoweredAtomicOr8 OpPPC64LoweredAtomicOr32 OpPPC64LoweredWB OpPPC64LoweredPubBarrier OpPPC64LoweredPanicBoundsA OpPPC64LoweredPanicBoundsB OpPPC64LoweredPanicBoundsC OpPPC64InvertFlags OpPPC64FlagEQ OpPPC64FlagLT OpPPC64FlagGT OpRISCV64ADD OpRISCV64ADDI OpRISCV64ADDIW OpRISCV64NEG OpRISCV64NEGW OpRISCV64SUB OpRISCV64SUBW OpRISCV64MUL OpRISCV64MULW OpRISCV64MULH OpRISCV64MULHU OpRISCV64LoweredMuluhilo OpRISCV64LoweredMuluover OpRISCV64DIV OpRISCV64DIVU OpRISCV64DIVW OpRISCV64DIVUW OpRISCV64REM OpRISCV64REMU OpRISCV64REMW OpRISCV64REMUW OpRISCV64MOVaddr OpRISCV64MOVDconst OpRISCV64MOVBload OpRISCV64MOVHload OpRISCV64MOVWload OpRISCV64MOVDload OpRISCV64MOVBUload OpRISCV64MOVHUload OpRISCV64MOVWUload OpRISCV64MOVBstore OpRISCV64MOVHstore OpRISCV64MOVWstore OpRISCV64MOVDstore OpRISCV64MOVBstorezero OpRISCV64MOVHstorezero OpRISCV64MOVWstorezero OpRISCV64MOVDstorezero OpRISCV64MOVBreg OpRISCV64MOVHreg OpRISCV64MOVWreg OpRISCV64MOVDreg OpRISCV64MOVBUreg OpRISCV64MOVHUreg OpRISCV64MOVWUreg OpRISCV64MOVDnop OpRISCV64SLL OpRISCV64SRA OpRISCV64SRL OpRISCV64SLLI OpRISCV64SRAI OpRISCV64SRLI OpRISCV64XOR OpRISCV64XORI OpRISCV64OR OpRISCV64ORI OpRISCV64AND OpRISCV64ANDI OpRISCV64NOT OpRISCV64SEQZ OpRISCV64SNEZ OpRISCV64SLT OpRISCV64SLTI OpRISCV64SLTU OpRISCV64SLTIU OpRISCV64MOVconvert OpRISCV64CALLstatic OpRISCV64CALLtail OpRISCV64CALLclosure OpRISCV64CALLinter OpRISCV64DUFFZERO OpRISCV64DUFFCOPY OpRISCV64LoweredZero OpRISCV64LoweredMove OpRISCV64LoweredAtomicLoad8 OpRISCV64LoweredAtomicLoad32 OpRISCV64LoweredAtomicLoad64 OpRISCV64LoweredAtomicStore8 OpRISCV64LoweredAtomicStore32 OpRISCV64LoweredAtomicStore64 OpRISCV64LoweredAtomicExchange32 OpRISCV64LoweredAtomicExchange64 OpRISCV64LoweredAtomicAdd32 OpRISCV64LoweredAtomicAdd64 OpRISCV64LoweredAtomicCas32 OpRISCV64LoweredAtomicCas64 OpRISCV64LoweredAtomicAnd32 OpRISCV64LoweredAtomicOr32 OpRISCV64LoweredNilCheck OpRISCV64LoweredGetClosurePtr OpRISCV64LoweredGetCallerSP OpRISCV64LoweredGetCallerPC OpRISCV64LoweredWB OpRISCV64LoweredPanicBoundsA OpRISCV64LoweredPanicBoundsB OpRISCV64LoweredPanicBoundsC OpRISCV64FADDS OpRISCV64FSUBS OpRISCV64FMULS OpRISCV64FDIVS OpRISCV64FSQRTS OpRISCV64FNEGS OpRISCV64FMVSX OpRISCV64FCVTSW OpRISCV64FCVTSL OpRISCV64FCVTWS OpRISCV64FCVTLS OpRISCV64FMOVWload OpRISCV64FMOVWstore OpRISCV64FEQS OpRISCV64FNES OpRISCV64FLTS OpRISCV64FLES OpRISCV64FADDD OpRISCV64FSUBD OpRISCV64FMULD OpRISCV64FDIVD OpRISCV64FMADDD OpRISCV64FMSUBD OpRISCV64FNMADDD OpRISCV64FNMSUBD OpRISCV64FSQRTD OpRISCV64FNEGD OpRISCV64FABSD OpRISCV64FSGNJD OpRISCV64FMVDX OpRISCV64FCVTDW OpRISCV64FCVTDL OpRISCV64FCVTWD OpRISCV64FCVTLD OpRISCV64FCVTDS OpRISCV64FCVTSD OpRISCV64FMOVDload OpRISCV64FMOVDstore OpRISCV64FEQD OpRISCV64FNED OpRISCV64FLTD OpRISCV64FLED OpS390XFADDS OpS390XFADD OpS390XFSUBS OpS390XFSUB OpS390XFMULS OpS390XFMUL OpS390XFDIVS OpS390XFDIV OpS390XFNEGS OpS390XFNEG OpS390XFMADDS OpS390XFMADD OpS390XFMSUBS OpS390XFMSUB OpS390XLPDFR OpS390XLNDFR OpS390XCPSDR OpS390XFIDBR OpS390XFMOVSload OpS390XFMOVDload OpS390XFMOVSconst OpS390XFMOVDconst OpS390XFMOVSloadidx OpS390XFMOVDloadidx OpS390XFMOVSstore OpS390XFMOVDstore OpS390XFMOVSstoreidx OpS390XFMOVDstoreidx OpS390XADD OpS390XADDW OpS390XADDconst OpS390XADDWconst OpS390XADDload OpS390XADDWload OpS390XSUB OpS390XSUBW OpS390XSUBconst OpS390XSUBWconst OpS390XSUBload OpS390XSUBWload OpS390XMULLD OpS390XMULLW OpS390XMULLDconst OpS390XMULLWconst OpS390XMULLDload OpS390XMULLWload OpS390XMULHD OpS390XMULHDU OpS390XDIVD OpS390XDIVW OpS390XDIVDU OpS390XDIVWU OpS390XMODD OpS390XMODW OpS390XMODDU OpS390XMODWU OpS390XAND OpS390XANDW OpS390XANDconst OpS390XANDWconst OpS390XANDload OpS390XANDWload OpS390XOR OpS390XORW OpS390XORconst OpS390XORWconst OpS390XORload OpS390XORWload OpS390XXOR OpS390XXORW OpS390XXORconst OpS390XXORWconst OpS390XXORload OpS390XXORWload OpS390XADDC OpS390XADDCconst OpS390XADDE OpS390XSUBC OpS390XSUBE OpS390XCMP OpS390XCMPW OpS390XCMPU OpS390XCMPWU OpS390XCMPconst OpS390XCMPWconst OpS390XCMPUconst OpS390XCMPWUconst OpS390XFCMPS OpS390XFCMP OpS390XLTDBR OpS390XLTEBR OpS390XSLD OpS390XSLW OpS390XSLDconst OpS390XSLWconst OpS390XSRD OpS390XSRW OpS390XSRDconst OpS390XSRWconst OpS390XSRAD OpS390XSRAW OpS390XSRADconst OpS390XSRAWconst OpS390XRLLG OpS390XRLL OpS390XRLLconst OpS390XRXSBG OpS390XRISBGZ OpS390XNEG OpS390XNEGW OpS390XNOT OpS390XNOTW OpS390XFSQRT OpS390XFSQRTS OpS390XLOCGR OpS390XMOVBreg OpS390XMOVBZreg OpS390XMOVHreg OpS390XMOVHZreg OpS390XMOVWreg OpS390XMOVWZreg OpS390XMOVDconst OpS390XLDGR OpS390XLGDR OpS390XCFDBRA OpS390XCGDBRA OpS390XCFEBRA OpS390XCGEBRA OpS390XCEFBRA OpS390XCDFBRA OpS390XCEGBRA OpS390XCDGBRA OpS390XCLFEBR OpS390XCLFDBR OpS390XCLGEBR OpS390XCLGDBR OpS390XCELFBR OpS390XCDLFBR OpS390XCELGBR OpS390XCDLGBR OpS390XLEDBR OpS390XLDEBR OpS390XMOVDaddr OpS390XMOVDaddridx OpS390XMOVBZload OpS390XMOVBload OpS390XMOVHZload OpS390XMOVHload OpS390XMOVWZload OpS390XMOVWload OpS390XMOVDload OpS390XMOVWBR OpS390XMOVDBR OpS390XMOVHBRload OpS390XMOVWBRload OpS390XMOVDBRload OpS390XMOVBstore OpS390XMOVHstore OpS390XMOVWstore OpS390XMOVDstore OpS390XMOVHBRstore OpS390XMOVWBRstore OpS390XMOVDBRstore OpS390XMVC OpS390XMOVBZloadidx OpS390XMOVBloadidx OpS390XMOVHZloadidx OpS390XMOVHloadidx OpS390XMOVWZloadidx OpS390XMOVWloadidx OpS390XMOVDloadidx OpS390XMOVHBRloadidx OpS390XMOVWBRloadidx OpS390XMOVDBRloadidx OpS390XMOVBstoreidx OpS390XMOVHstoreidx OpS390XMOVWstoreidx OpS390XMOVDstoreidx OpS390XMOVHBRstoreidx OpS390XMOVWBRstoreidx OpS390XMOVDBRstoreidx OpS390XMOVBstoreconst OpS390XMOVHstoreconst OpS390XMOVWstoreconst OpS390XMOVDstoreconst OpS390XCLEAR OpS390XCALLstatic OpS390XCALLtail OpS390XCALLclosure OpS390XCALLinter OpS390XInvertFlags OpS390XLoweredGetG OpS390XLoweredGetClosurePtr OpS390XLoweredGetCallerSP OpS390XLoweredGetCallerPC OpS390XLoweredNilCheck OpS390XLoweredRound32F OpS390XLoweredRound64F OpS390XLoweredWB OpS390XLoweredPanicBoundsA OpS390XLoweredPanicBoundsB OpS390XLoweredPanicBoundsC OpS390XFlagEQ OpS390XFlagLT OpS390XFlagGT OpS390XFlagOV OpS390XSYNC OpS390XMOVBZatomicload OpS390XMOVWZatomicload OpS390XMOVDatomicload OpS390XMOVBatomicstore OpS390XMOVWatomicstore OpS390XMOVDatomicstore OpS390XLAA OpS390XLAAG OpS390XAddTupleFirst32 OpS390XAddTupleFirst64 OpS390XLAN OpS390XLANfloor OpS390XLAO OpS390XLAOfloor OpS390XLoweredAtomicCas32 OpS390XLoweredAtomicCas64 OpS390XLoweredAtomicExchange32 OpS390XLoweredAtomicExchange64 OpS390XFLOGR OpS390XPOPCNT OpS390XMLGR OpS390XSumBytes2 OpS390XSumBytes4 OpS390XSumBytes8 OpS390XSTMG2 OpS390XSTMG3 OpS390XSTMG4 OpS390XSTM2 OpS390XSTM3 OpS390XSTM4 OpS390XLoweredMove OpS390XLoweredZero OpWasmLoweredStaticCall OpWasmLoweredTailCall OpWasmLoweredClosureCall OpWasmLoweredInterCall OpWasmLoweredAddr OpWasmLoweredMove OpWasmLoweredZero OpWasmLoweredGetClosurePtr OpWasmLoweredGetCallerPC OpWasmLoweredGetCallerSP OpWasmLoweredNilCheck OpWasmLoweredWB OpWasmLoweredConvert OpWasmSelect OpWasmI64Load8U OpWasmI64Load8S OpWasmI64Load16U OpWasmI64Load16S OpWasmI64Load32U OpWasmI64Load32S OpWasmI64Load OpWasmI64Store8 OpWasmI64Store16 OpWasmI64Store32 OpWasmI64Store OpWasmF32Load OpWasmF64Load OpWasmF32Store OpWasmF64Store OpWasmI64Const OpWasmF32Const OpWasmF64Const OpWasmI64Eqz OpWasmI64Eq OpWasmI64Ne OpWasmI64LtS OpWasmI64LtU OpWasmI64GtS OpWasmI64GtU OpWasmI64LeS OpWasmI64LeU OpWasmI64GeS OpWasmI64GeU OpWasmF32Eq OpWasmF32Ne OpWasmF32Lt OpWasmF32Gt OpWasmF32Le OpWasmF32Ge OpWasmF64Eq OpWasmF64Ne OpWasmF64Lt OpWasmF64Gt OpWasmF64Le OpWasmF64Ge OpWasmI64Add OpWasmI64AddConst OpWasmI64Sub OpWasmI64Mul OpWasmI64DivS OpWasmI64DivU OpWasmI64RemS OpWasmI64RemU OpWasmI64And OpWasmI64Or OpWasmI64Xor OpWasmI64Shl OpWasmI64ShrS OpWasmI64ShrU OpWasmF32Neg OpWasmF32Add OpWasmF32Sub OpWasmF32Mul OpWasmF32Div OpWasmF64Neg OpWasmF64Add OpWasmF64Sub OpWasmF64Mul OpWasmF64Div OpWasmI64TruncSatF64S OpWasmI64TruncSatF64U OpWasmI64TruncSatF32S OpWasmI64TruncSatF32U OpWasmF32ConvertI64S OpWasmF32ConvertI64U OpWasmF64ConvertI64S OpWasmF64ConvertI64U OpWasmF32DemoteF64 OpWasmF64PromoteF32 OpWasmI64Extend8S OpWasmI64Extend16S OpWasmI64Extend32S OpWasmF32Sqrt OpWasmF32Trunc OpWasmF32Ceil OpWasmF32Floor OpWasmF32Nearest OpWasmF32Abs OpWasmF32Copysign OpWasmF64Sqrt OpWasmF64Trunc OpWasmF64Ceil OpWasmF64Floor OpWasmF64Nearest OpWasmF64Abs OpWasmF64Copysign OpWasmI64Ctz OpWasmI64Clz OpWasmI32Rotl OpWasmI64Rotl OpWasmI64Popcnt OpAdd8 OpAdd16 OpAdd32 OpAdd64 OpAddPtr OpAdd32F OpAdd64F OpSub8 OpSub16 OpSub32 OpSub64 OpSubPtr OpSub32F OpSub64F OpMul8 OpMul16 OpMul32 OpMul64 OpMul32F OpMul64F OpDiv32F OpDiv64F OpHmul32 OpHmul32u OpHmul64 OpHmul64u OpMul32uhilo OpMul64uhilo OpMul32uover OpMul64uover OpAvg32u OpAvg64u OpDiv8 OpDiv8u OpDiv16 OpDiv16u OpDiv32 OpDiv32u OpDiv64 OpDiv64u OpDiv128u OpMod8 OpMod8u OpMod16 OpMod16u OpMod32 OpMod32u OpMod64 OpMod64u OpAnd8 OpAnd16 OpAnd32 OpAnd64 OpOr8 OpOr16 OpOr32 OpOr64 OpXor8 OpXor16 OpXor32 OpXor64 OpLsh8x8 OpLsh8x16 OpLsh8x32 OpLsh8x64 OpLsh16x8 OpLsh16x16 OpLsh16x32 OpLsh16x64 OpLsh32x8 OpLsh32x16 OpLsh32x32 OpLsh32x64 OpLsh64x8 OpLsh64x16 OpLsh64x32 OpLsh64x64 OpRsh8x8 OpRsh8x16 OpRsh8x32 OpRsh8x64 OpRsh16x8 OpRsh16x16 OpRsh16x32 OpRsh16x64 OpRsh32x8 OpRsh32x16 OpRsh32x32 OpRsh32x64 OpRsh64x8 OpRsh64x16 OpRsh64x32 OpRsh64x64 OpRsh8Ux8 OpRsh8Ux16 OpRsh8Ux32 OpRsh8Ux64 OpRsh16Ux8 OpRsh16Ux16 OpRsh16Ux32 OpRsh16Ux64 OpRsh32Ux8 OpRsh32Ux16 OpRsh32Ux32 OpRsh32Ux64 OpRsh64Ux8 OpRsh64Ux16 OpRsh64Ux32 OpRsh64Ux64 OpEq8 OpEq16 OpEq32 OpEq64 OpEqPtr OpEqInter OpEqSlice OpEq32F OpEq64F OpNeq8 OpNeq16 OpNeq32 OpNeq64 OpNeqPtr OpNeqInter OpNeqSlice OpNeq32F OpNeq64F OpLess8 OpLess8U OpLess16 OpLess16U OpLess32 OpLess32U OpLess64 OpLess64U OpLess32F OpLess64F OpLeq8 OpLeq8U OpLeq16 OpLeq16U OpLeq32 OpLeq32U OpLeq64 OpLeq64U OpLeq32F OpLeq64F OpCondSelect OpAndB OpOrB OpEqB OpNeqB OpNot OpNeg8 OpNeg16 OpNeg32 OpNeg64 OpNeg32F OpNeg64F OpCom8 OpCom16 OpCom32 OpCom64 OpCtz8 OpCtz16 OpCtz32 OpCtz64 OpCtz8NonZero OpCtz16NonZero OpCtz32NonZero OpCtz64NonZero OpBitLen8 OpBitLen16 OpBitLen32 OpBitLen64 OpBswap32 OpBswap64 OpBitRev8 OpBitRev16 OpBitRev32 OpBitRev64 OpPopCount8 OpPopCount16 OpPopCount32 OpPopCount64 OpRotateLeft8 OpRotateLeft16 OpRotateLeft32 OpRotateLeft64 OpSqrt OpSqrt32 OpFloor OpCeil OpTrunc OpRound OpRoundToEven OpAbs OpCopysign OpFMA OpPhi OpCopy OpConvert OpConstBool OpConstString OpConstNil OpConst8 OpConst16 OpConst32 OpConst64 OpConst32F OpConst64F OpConstInterface OpConstSlice OpInitMem OpArg OpArgIntReg OpArgFloatReg OpAddr OpLocalAddr OpSP OpSB OpLoad OpDereference OpStore OpMove OpZero OpStoreWB OpMoveWB OpZeroWB OpWB OpHasCPUFeature OpPanicBounds OpPanicExtend OpClosureCall OpStaticCall OpInterCall OpTailCall OpClosureLECall OpStaticLECall OpInterLECall OpTailLECall OpSignExt8to16 OpSignExt8to32 OpSignExt8to64 OpSignExt16to32 OpSignExt16to64 OpSignExt32to64 OpZeroExt8to16 OpZeroExt8to32 OpZeroExt8to64 OpZeroExt16to32 OpZeroExt16to64 OpZeroExt32to64 OpTrunc16to8 OpTrunc32to8 OpTrunc32to16 OpTrunc64to8 OpTrunc64to16 OpTrunc64to32 OpCvt32to32F OpCvt32to64F OpCvt64to32F OpCvt64to64F OpCvt32Fto32 OpCvt32Fto64 OpCvt64Fto32 OpCvt64Fto64 OpCvt32Fto64F OpCvt64Fto32F OpCvtBoolToUint8 OpRound32F OpRound64F OpIsNonNil OpIsInBounds OpIsSliceInBounds OpNilCheck OpGetG OpGetClosurePtr OpGetCallerPC OpGetCallerSP OpPtrIndex OpOffPtr OpSliceMake OpSlicePtr OpSliceLen OpSliceCap OpSlicePtrUnchecked OpComplexMake OpComplexReal OpComplexImag OpStringMake OpStringPtr OpStringLen OpIMake OpITab OpIData OpStructMake0 OpStructMake1 OpStructMake2 OpStructMake3 OpStructMake4 OpStructSelect OpArrayMake0 OpArrayMake1 OpArraySelect OpStoreReg OpLoadReg OpFwdRef OpUnknown OpVarDef OpVarKill OpVarLive OpKeepAlive OpInlMark OpInt64Make OpInt64Hi OpInt64Lo OpAdd32carry OpAdd32withcarry OpSub32carry OpSub32withcarry OpAdd64carry OpSub64borrow OpSignmask OpZeromask OpSlicemask OpSpectreIndex OpSpectreSliceIndex OpCvt32Uto32F OpCvt32Uto64F OpCvt32Fto32U OpCvt64Fto32U OpCvt64Uto32F OpCvt64Uto64F OpCvt32Fto64U OpCvt64Fto64U OpSelect0 OpSelect1 OpSelectN OpSelectNAddr OpMakeResult OpAtomicLoad8 OpAtomicLoad32 OpAtomicLoad64 OpAtomicLoadPtr OpAtomicLoadAcq32 OpAtomicLoadAcq64 OpAtomicStore8 OpAtomicStore32 OpAtomicStore64 OpAtomicStorePtrNoWB OpAtomicStoreRel32 OpAtomicStoreRel64 OpAtomicExchange32 OpAtomicExchange64 OpAtomicAdd32 OpAtomicAdd64 OpAtomicCompareAndSwap32 OpAtomicCompareAndSwap64 OpAtomicCompareAndSwapRel32 OpAtomicAnd8 OpAtomicAnd32 OpAtomicOr8 OpAtomicOr32 OpAtomicAdd32Variant OpAtomicAdd64Variant OpAtomicExchange32Variant OpAtomicExchange64Variant OpAtomicCompareAndSwap32Variant OpAtomicCompareAndSwap64Variant OpAtomicAnd8Variant OpAtomicAnd32Variant OpAtomicOr8Variant OpAtomicOr32Variant OpPubBarrier OpClobber OpClobberReg OpPrefetchCache OpPrefetchCacheStreamed ) var opcodeTable = [...]opInfo{ {name: "OpInvalid"}, { name: "ADDSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSS", argLen: 2, resultInArg0: true, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSD", argLen: 2, resultInArg0: true, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSS", argLen: 2, resultInArg0: true, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSD", argLen: 2, resultInArg0: true, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: x86.AMOVSS, reg: regInfo{ outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: x86.AMOVSD, reg: regInfo{ outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSSstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSSstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 239}, // AX CX DX BX BP SI DI {0, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLcarry", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADCL", argLen: 3, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AADCL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADCLconst", auxType: auxInt32, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AADCL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLcarry", argLen: 2, resultInArg0: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SBBL", argLen: 3, resultInArg0: true, clobberFlags: true, asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SBBLconst", auxType: auxInt32, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AIMUL3L, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "HMULL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULLU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MULLQU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 4}, // DX {1, 1}, // AX }, }, }, { name: "AVGLU", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "DIVL", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVW", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "MODL", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODW", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "ANDL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CMPL", argLen: 2, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPW", argLen: 2, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPB", argLen: 2, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPLconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPWconst", auxType: auxInt16, argLen: 1, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPBconst", auxType: auxInt8, argLen: 1, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPWload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPBload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPLconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPWconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPBconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "UCOMISS", argLen: 2, asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "UCOMISD", argLen: 2, asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "TESTL", argLen: 2, commutative: true, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTW", argLen: 2, commutative: true, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTB", argLen: 2, commutative: true, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTLconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTWconst", auxType: auxInt16, argLen: 1, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTBconst", auxType: auxInt8, argLen: 1, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "SHLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "NEGL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "NOTL", argLen: 1, resultInArg0: true, asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSFL", argLen: 1, clobberFlags: true, asm: x86.ABSFL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSFW", argLen: 1, clobberFlags: true, asm: x86.ABSFW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSRL", argLen: 1, clobberFlags: true, asm: x86.ABSRL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSRW", argLen: 1, clobberFlags: true, asm: x86.ABSRW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSWAPL", argLen: 1, resultInArg0: true, asm: x86.ABSWAPL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SQRTSD", argLen: 1, asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SQRTSS", argLen: 1, asm: x86.ASQRTSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SBBLcarrymask", argLen: 1, asm: x86.ASBBL, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETEQ", argLen: 1, asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETNE", argLen: 1, asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETL", argLen: 1, asm: x86.ASETLT, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETLE", argLen: 1, asm: x86.ASETLE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETG", argLen: 1, asm: x86.ASETGT, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGE", argLen: 1, asm: x86.ASETGE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETB", argLen: 1, asm: x86.ASETCS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETBE", argLen: 1, asm: x86.ASETLS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETA", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETAE", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETO", argLen: 1, asm: x86.ASETOS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETEQF", argLen: 1, clobberFlags: true, asm: x86.ASETEQ, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 238}, // CX DX BX BP SI DI }, }, }, { name: "SETNEF", argLen: 1, clobberFlags: true, asm: x86.ASETNE, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 238}, // CX DX BX BP SI DI }, }, }, { name: "SETORD", argLen: 1, asm: x86.ASETPC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETNAN", argLen: 1, asm: x86.ASETPS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGF", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGEF", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLSX", argLen: 1, asm: x86.AMOVBLSX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLZX", argLen: 1, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLSX", argLen: 1, asm: x86.AMOVWLSX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLZX", argLen: 1, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: x86.AMOVL, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTTSD2SL", argLen: 1, asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTTSS2SL", argLen: 1, asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTSL2SS", argLen: 1, asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSL2SD", argLen: 1, asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSD2SS", argLen: 1, asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSS2SD", argLen: 1, asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "PXOR", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "LEAL", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBLSX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWLSX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "SUBLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "SUBLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWloadidx2", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreidx2", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconstidx2", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconstidx4", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "REPSTOSL", argLen: 4, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 2}, // CX {2, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4}, // DX {0, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI }, clobbers: 194, // CX SI DI }, }, { name: "REPMOVSL", argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI {2, 2}, // CX }, clobbers: 194, // CX SI DI }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 1}, // AX }, clobbers: 65280, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // DX {1, 8}, // BX }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // CX {1, 4}, // DX }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 2}, // CX }, }, }, { name: "LoweredPanicExtendA", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // SI {1, 4}, // DX {2, 8}, // BX }, }, }, { name: "LoweredPanicExtendB", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // SI {1, 2}, // CX {2, 4}, // DX }, }, }, { name: "LoweredPanicExtendC", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // SI {1, 1}, // AX {2, 2}, // CX }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_ULT", argLen: 0, reg: regInfo{}, }, { name: "MOVSSconst1", auxType: auxFloat32, argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVSDconst1", auxType: auxFloat64, argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVSSconst2", argLen: 1, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDconst2", argLen: 1, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSS", argLen: 2, resultInArg0: true, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSD", argLen: 2, resultInArg0: true, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSS", argLen: 2, resultInArg0: true, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSD", argLen: 2, resultInArg0: true, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: x86.AMOVSS, reg: regInfo{ outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: x86.AMOVSD, reg: regInfo{ outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSSstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSSstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSDstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSDstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "ADDSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDQ", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULQconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AIMUL3Q, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AIMUL3L, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULLU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 4, // DX outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "MULQU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 4, // DX outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "HMULQ", argLen: 2, clobberFlags: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULL", argLen: 2, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULQU", argLen: 2, clobberFlags: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULLU", argLen: 2, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "AVGQU", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "DIVQ", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVL", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVW", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVQU", argLen: 2, clobberFlags: true, asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "NEGLflags", argLen: 1, resultInArg0: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQcarry", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADCQ", argLen: 3, commutative: true, resultInArg0: true, asm: x86.AADCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADCQconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: x86.AADCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQborrow", argLen: 2, resultInArg0: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SBBQ", argLen: 3, resultInArg0: true, asm: x86.ASBBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQconstborrow", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SBBQconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: x86.ASBBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULQU2", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 4}, // DX {1, 1}, // AX }, }, }, { name: "DIVQU2", argLen: 3, clobberFlags: true, asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // DX {1, 1}, // AX {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "ANDQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQ", argLen: 2, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPL", argLen: 2, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPW", argLen: 2, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPB", argLen: 2, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPQconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPLconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPWconst", auxType: auxInt16, argLen: 1, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPBconst", auxType: auxInt8, argLen: 1, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQloadidx8", auxType: auxSymOff, argLen: 4, symEffect: SymRead, asm: x86.ACMPQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLloadidx4", auxType: auxSymOff, argLen: 4, symEffect: SymRead, asm: x86.ACMPL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWloadidx2", auxType: auxSymOff, argLen: 4, symEffect: SymRead, asm: x86.ACMPW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQconstloadidx8", auxType: auxSymValAndOff, argLen: 3, symEffect: SymRead, asm: x86.ACMPQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLconstloadidx4", auxType: auxSymValAndOff, argLen: 3, symEffect: SymRead, asm: x86.ACMPL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWconstloadidx2", auxType: auxSymValAndOff, argLen: 3, symEffect: SymRead, asm: x86.ACMPW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "UCOMISS", argLen: 2, asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "UCOMISD", argLen: 2, asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "BTL", argLen: 2, asm: x86.ABTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTQ", argLen: 2, asm: x86.ABTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTCL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTSL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTLconst", auxType: auxInt8, argLen: 1, asm: x86.ABTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTQconst", auxType: auxInt8, argLen: 1, asm: x86.ABTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTCL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTSL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTQ", argLen: 2, commutative: true, asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTL", argLen: 2, commutative: true, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTW", argLen: 2, commutative: true, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTB", argLen: 2, commutative: true, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTQconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTLconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTWconst", auxType: auxInt16, argLen: 1, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTBconst", auxType: auxInt8, argLen: 1, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRWconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARWconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRDQ", argLen: 3, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {2, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLDQ", argLen: 3, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {2, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLWconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "NEGQ", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "NEGL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "NOTQ", argLen: 1, resultInArg0: true, asm: x86.ANOTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "NOTL", argLen: 1, resultInArg0: true, asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSFQ", argLen: 1, asm: x86.ABSFQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSFL", argLen: 1, clobberFlags: true, asm: x86.ABSFL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSRQ", argLen: 1, asm: x86.ABSRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSRL", argLen: 1, clobberFlags: true, asm: x86.ABSRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQEQ", argLen: 3, resultInArg0: true, asm: x86.ACMOVQEQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQNE", argLen: 3, resultInArg0: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQLT", argLen: 3, resultInArg0: true, asm: x86.ACMOVQLT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGT", argLen: 3, resultInArg0: true, asm: x86.ACMOVQGT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQLE", argLen: 3, resultInArg0: true, asm: x86.ACMOVQLE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGE", argLen: 3, resultInArg0: true, asm: x86.ACMOVQGE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQLS", argLen: 3, resultInArg0: true, asm: x86.ACMOVQLS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQHI", argLen: 3, resultInArg0: true, asm: x86.ACMOVQHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQCC", argLen: 3, resultInArg0: true, asm: x86.ACMOVQCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQCS", argLen: 3, resultInArg0: true, asm: x86.ACMOVQCS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLEQ", argLen: 3, resultInArg0: true, asm: x86.ACMOVLEQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLNE", argLen: 3, resultInArg0: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLLT", argLen: 3, resultInArg0: true, asm: x86.ACMOVLLT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGT", argLen: 3, resultInArg0: true, asm: x86.ACMOVLGT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLLE", argLen: 3, resultInArg0: true, asm: x86.ACMOVLLE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGE", argLen: 3, resultInArg0: true, asm: x86.ACMOVLGE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLLS", argLen: 3, resultInArg0: true, asm: x86.ACMOVLLS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLHI", argLen: 3, resultInArg0: true, asm: x86.ACMOVLHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLCC", argLen: 3, resultInArg0: true, asm: x86.ACMOVLCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLCS", argLen: 3, resultInArg0: true, asm: x86.ACMOVLCS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWEQ", argLen: 3, resultInArg0: true, asm: x86.ACMOVWEQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWNE", argLen: 3, resultInArg0: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWLT", argLen: 3, resultInArg0: true, asm: x86.ACMOVWLT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGT", argLen: 3, resultInArg0: true, asm: x86.ACMOVWGT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWLE", argLen: 3, resultInArg0: true, asm: x86.ACMOVWLE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGE", argLen: 3, resultInArg0: true, asm: x86.ACMOVWGE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWLS", argLen: 3, resultInArg0: true, asm: x86.ACMOVWLS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWHI", argLen: 3, resultInArg0: true, asm: x86.ACMOVWHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWCC", argLen: 3, resultInArg0: true, asm: x86.ACMOVWCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWCS", argLen: 3, resultInArg0: true, asm: x86.ACMOVWCS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQEQF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQNEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGTF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLEQF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLNEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGTF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWEQF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWNEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGTF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSWAPQ", argLen: 1, resultInArg0: true, asm: x86.ABSWAPQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSWAPL", argLen: 1, resultInArg0: true, asm: x86.ABSWAPL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "POPCNTQ", argLen: 1, clobberFlags: true, asm: x86.APOPCNTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "POPCNTL", argLen: 1, clobberFlags: true, asm: x86.APOPCNTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SQRTSD", argLen: 1, asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SQRTSS", argLen: 1, asm: x86.ASQRTSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ROUNDSD", auxType: auxInt8, argLen: 1, asm: x86.AROUNDSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "VFMADD231SD", argLen: 3, resultInArg0: true, asm: x86.AVFMADD231SD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SBBQcarrymask", argLen: 1, asm: x86.ASBBQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SBBLcarrymask", argLen: 1, asm: x86.ASBBL, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETEQ", argLen: 1, asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETNE", argLen: 1, asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETL", argLen: 1, asm: x86.ASETLT, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETLE", argLen: 1, asm: x86.ASETLE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETG", argLen: 1, asm: x86.ASETGT, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETGE", argLen: 1, asm: x86.ASETGE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETB", argLen: 1, asm: x86.ASETCS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETBE", argLen: 1, asm: x86.ASETLS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETA", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETAE", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETO", argLen: 1, asm: x86.ASETOS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETEQstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETEQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETNEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETNE, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETLstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETLT, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETLEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETLE, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETGstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETGT, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETGEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETGE, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETCS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETBEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETLS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETAstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETHI, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETAEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETCC, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETEQF", argLen: 1, clobberFlags: true, asm: x86.ASETEQ, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETNEF", argLen: 1, clobberFlags: true, asm: x86.ASETNE, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETORD", argLen: 1, asm: x86.ASETPC, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETNAN", argLen: 1, asm: x86.ASETPS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETGF", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETGEF", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBQSX", argLen: 1, asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBQZX", argLen: 1, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWQSX", argLen: 1, asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWQZX", argLen: 1, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLQSX", argLen: 1, asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLQZX", argLen: 1, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: x86.AMOVL, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: x86.AMOVQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSD2SL", argLen: 1, asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSD2SQ", argLen: 1, asm: x86.ACVTTSD2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSS2SL", argLen: 1, asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSS2SQ", argLen: 1, asm: x86.ACVTTSS2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTSL2SS", argLen: 1, asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSL2SD", argLen: 1, asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSQ2SS", argLen: 1, asm: x86.ACVTSQ2SS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSQ2SD", argLen: 1, asm: x86.ACVTSQ2SD, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSD2SS", argLen: 1, asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSS2SD", argLen: 1, asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVQi2f", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVQf2i", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLi2f", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVLf2i", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "PXOR", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "LEAQ", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: x86.ALEAQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: x86.ALEAL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: x86.ALEAW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, asm: x86.ALEAQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, asm: x86.ALEAL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, asm: x86.ALEAW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAQ, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAL, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAQ, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAW, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAW, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBQSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWQSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLQSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVOload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVOstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVBloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBLZX, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVWLZX, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWloadidx2", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVWLZX, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreidx2", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVOstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreconstidx2", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreconstidx4", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreconstidx8", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI }, clobbers: 128, // DI }, }, { name: "REPSTOSQ", argLen: 4, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 2}, // CX {2, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4}, // DX {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI }, clobbers: 65728, // SI DI X0 }, }, { name: "REPMOVSQ", argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI {2, 2}, // CX }, clobbers: 194, // CX SI DI }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 879}, // AX CX DX BX BP SI R8 R9 }, clobbers: 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "LoweredHasCPUFeature", auxType: auxSym, argLen: 0, rematerializeable: true, symEffect: SymNone, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // DX {1, 8}, // BX }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // CX {1, 4}, // DX }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 2}, // CX }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_ULT", argLen: 0, reg: regInfo{}, }, { name: "MOVBatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XCHGB", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXCHGB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XCHGL", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXCHGL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XCHGQ", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXCHGQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XADDLlock", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXADDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XADDQlock", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "AddTupleFirst32", argLen: 2, reg: regInfo{}, }, { name: "AddTupleFirst64", argLen: 2, reg: regInfo{}, }, { name: "CMPXCHGLlock", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.ACMPXCHGL, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // AX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPXCHGQlock", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.ACMPXCHGQ, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // AX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDBlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AANDB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORBlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AORB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "PrefetchT0", argLen: 2, hasSideEffects: true, asm: x86.APREFETCHT0, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "PrefetchNTA", argLen: 2, hasSideEffects: true, asm: x86.APREFETCHNTA, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDNQ", argLen: 2, clobberFlags: true, asm: x86.AANDNQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDNL", argLen: 2, clobberFlags: true, asm: x86.AANDNL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSIQ", argLen: 1, clobberFlags: true, asm: x86.ABLSIQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSIL", argLen: 1, clobberFlags: true, asm: x86.ABLSIL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSMSKQ", argLen: 1, clobberFlags: true, asm: x86.ABLSMSKQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSMSKL", argLen: 1, clobberFlags: true, asm: x86.ABLSMSKL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSRQ", argLen: 1, clobberFlags: true, asm: x86.ABLSRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSRL", argLen: 1, clobberFlags: true, asm: x86.ABLSRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TZCNTQ", argLen: 1, clobberFlags: true, asm: x86.ATZCNTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TZCNTL", argLen: 1, clobberFlags: true, asm: x86.ATZCNTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LZCNTQ", argLen: 1, clobberFlags: true, asm: x86.ALZCNTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LZCNTL", argLen: 1, clobberFlags: true, asm: x86.ALZCNTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVBEW, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBEL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBELstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVBEL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEQload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBEQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEQstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVBEQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBEL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBELloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVBEL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBELloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVBEL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEQloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBEQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEQloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVBEQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEWstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVBEW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEWstoreidx2", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVBEL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEQstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVBEQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEQstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SARXQ", argLen: 2, asm: x86.ASARXQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXL", argLen: 2, asm: x86.ASARXL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQ", argLen: 2, asm: x86.ASHLXQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXL", argLen: 2, asm: x86.ASHLXL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQ", argLen: 2, asm: x86.ASHRXQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXL", argLen: 2, asm: x86.ASHRXL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLloadidx4", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXQloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXQloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLloadidx4", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLloadidx4", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUB", argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSB", argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBconst", auxType: auxInt32, argLen: 1, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: arm.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "HMUL", argLen: 2, commutative: true, asm: arm.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "HMULU", argLen: 2, commutative: true, asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CALLudiv", argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 1}, // R0 }, clobbers: 20492, // R2 R3 R12 R14 outputs: []outputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "ADDS", argLen: 2, commutative: true, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSconst", auxType: auxInt32, argLen: 1, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADC", argLen: 3, commutative: true, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCconst", auxType: auxInt32, argLen: 2, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBS", argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSconst", auxType: auxInt32, argLen: 1, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSconst", auxType: auxInt32, argLen: 1, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBC", argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCconst", auxType: auxInt32, argLen: 2, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCconst", auxType: auxInt32, argLen: 2, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULLU", argLen: 2, commutative: true, asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULA", argLen: 3, asm: arm.AMULA, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULS", argLen: 3, asm: arm.AMULS, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: arm.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: arm.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SUBF", argLen: 2, asm: arm.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SUBD", argLen: 2, asm: arm.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: arm.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: arm.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "NMULF", argLen: 2, commutative: true, asm: arm.ANMULF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "NMULD", argLen: 2, commutative: true, asm: arm.ANMULD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "DIVF", argLen: 2, asm: arm.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "DIVD", argLen: 2, asm: arm.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULAF", argLen: 3, resultInArg0: true, asm: arm.AMULAF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULAD", argLen: 3, resultInArg0: true, asm: arm.AMULAD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULSF", argLen: 3, resultInArg0: true, asm: arm.AMULSF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULSD", argLen: 3, resultInArg0: true, asm: arm.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMULAD", argLen: 3, resultInArg0: true, asm: arm.AFMULAD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDconst", auxType: auxInt32, argLen: 1, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORconst", auxType: auxInt32, argLen: 1, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORconst", auxType: auxInt32, argLen: 1, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BIC", argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICconst", auxType: auxInt32, argLen: 1, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BFX", auxType: auxInt32, argLen: 1, asm: arm.ABFX, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BFXU", auxType: auxInt32, argLen: 1, asm: arm.ABFXU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVN", argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "NEGF", argLen: 1, asm: arm.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "NEGD", argLen: 1, asm: arm.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SQRTD", argLen: 1, asm: arm.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SQRTF", argLen: 1, asm: arm.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ABSD", argLen: 1, asm: arm.AABSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CLZ", argLen: 1, asm: arm.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "REV", argLen: 1, asm: arm.AREV, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "REV16", argLen: 1, asm: arm.AREV16, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RBIT", argLen: 1, asm: arm.ARBIT, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SLL", argLen: 2, asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SLLconst", auxType: auxInt32, argLen: 1, asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRL", argLen: 2, asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRLconst", auxType: auxInt32, argLen: 1, asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRA", argLen: 2, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRAconst", auxType: auxInt32, argLen: 1, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRR", argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRRconst", auxType: auxInt32, argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRR", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftLL", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRL", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRA", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftLLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRAreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftLLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRAreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftLLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRAreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftLLreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRLreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRAreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftLLreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRLreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRAreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftLLreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRLreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRAreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftLLreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRLreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRAreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftLLreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRLreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRAreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftLLreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRLreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRAreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftLLreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRLreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRAreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftLLreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRLreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRAreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftLLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRAreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftLLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRAreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftLLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRAreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMP", argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPconst", auxType: auxInt32, argLen: 1, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMN", argLen: 2, commutative: true, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNconst", auxType: auxInt32, argLen: 1, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TST", argLen: 2, commutative: true, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTconst", auxType: auxInt32, argLen: 1, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQ", argLen: 2, commutative: true, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQconst", auxType: auxInt32, argLen: 1, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPF", argLen: 2, asm: arm.ACMPF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPD", argLen: 2, asm: arm.ACMPD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPshiftLLreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMPshiftRLreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMPshiftRAreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMNshiftLLreg", argLen: 3, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMNshiftRLreg", argLen: 3, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMNshiftRAreg", argLen: 3, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TSTshiftLLreg", argLen: 3, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TSTshiftRLreg", argLen: 3, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TSTshiftRAreg", argLen: 3, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TEQshiftLLreg", argLen: 3, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TEQshiftRLreg", argLen: 3, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TEQshiftRAreg", argLen: 3, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMPF0", argLen: 1, asm: arm.ACMPF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPD0", argLen: 1, asm: arm.ACMPD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: arm.AMOVW, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4294975488}, // SP SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWloadshiftLL", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWloadshiftRL", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWloadshiftRA", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBUloadidx", argLen: 3, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBloadidx", argLen: 3, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHUloadidx", argLen: 3, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstoreshiftLL", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstoreshiftRL", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstoreshiftRA", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVBreg", argLen: 1, asm: arm.AMOVBS, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBUreg", argLen: 1, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHreg", argLen: 1, asm: arm.AMOVHS, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHUreg", argLen: 1, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWreg", argLen: 1, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWF", argLen: 1, asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWD", argLen: 1, asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWUF", argLen: 1, asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWUD", argLen: 1, asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVFW", argLen: 1, asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVDW", argLen: 1, asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFWU", argLen: 1, asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVDWU", argLen: 1, asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFD", argLen: 1, asm: arm.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDF", argLen: 1, asm: arm.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMOVWHSconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMOVWLSconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRAcond", argLen: 3, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 128}, // R7 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 }, clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 1}, // R0 }, clobbers: 20482, // R1 R12 R14 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 }, clobbers: 20487, // R0 R1 R2 R12 R14 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2, // R1 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 6, // R1 R2 }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 128}, // R7 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "LoweredPanicExtendA", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 4}, // R2 {2, 8}, // R3 }, }, }, { name: "LoweredPanicExtendB", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 2}, // R1 {2, 4}, // R2 }, }, }, { name: "LoweredPanicExtendC", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 1}, // R0 {2, 2}, // R1 }, }, }, { name: "FlagConstant", auxType: auxFlagConstant, argLen: 0, reg: regInfo{}, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "ADCSflags", argLen: 3, commutative: true, asm: arm64.AADCS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADCzerocarry", argLen: 1, asm: arm64.AADC, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDconst", auxType: auxInt64, argLen: 1, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDSconstflags", auxType: auxInt64, argLen: 1, asm: arm64.AADDS, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {1, 0}, {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDSflags", argLen: 2, commutative: true, asm: arm64.AADDS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUB", argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBconst", auxType: auxInt64, argLen: 1, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SBCSflags", argLen: 3, asm: arm64.ASBCS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBSflags", argLen: 2, asm: arm64.ASUBS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: arm64.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MULW", argLen: 2, commutative: true, asm: arm64.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MNEG", argLen: 2, commutative: true, asm: arm64.AMNEG, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MNEGW", argLen: 2, commutative: true, asm: arm64.AMNEGW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MULH", argLen: 2, commutative: true, asm: arm64.ASMULH, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMULH", argLen: 2, commutative: true, asm: arm64.AUMULH, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MULL", argLen: 2, commutative: true, asm: arm64.ASMULL, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMULL", argLen: 2, commutative: true, asm: arm64.AUMULL, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "DIV", argLen: 2, asm: arm64.ASDIV, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UDIV", argLen: 2, asm: arm64.AUDIV, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "DIVW", argLen: 2, asm: arm64.ASDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UDIVW", argLen: 2, asm: arm64.AUDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOD", argLen: 2, asm: arm64.AREM, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMOD", argLen: 2, asm: arm64.AUREM, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MODW", argLen: 2, asm: arm64.AREMW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMODW", argLen: 2, asm: arm64.AUREMW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: arm64.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FADDD", argLen: 2, commutative: true, asm: arm64.AFADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBS", argLen: 2, asm: arm64.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBD", argLen: 2, asm: arm64.AFSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: arm64.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULD", argLen: 2, commutative: true, asm: arm64.AFMULD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMULS", argLen: 2, commutative: true, asm: arm64.AFNMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMULD", argLen: 2, commutative: true, asm: arm64.AFNMULD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVS", argLen: 2, asm: arm64.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVD", argLen: 2, asm: arm64.AFDIVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BIC", argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EON", argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORN", argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredMuluhilo", argLen: 2, resultNotInArgs: true, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVN", argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEG", argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGSflags", argLen: 1, asm: arm64.ANEGS, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {1, 0}, {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NGCzerocarry", argLen: 1, asm: arm64.ANGC, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FABSD", argLen: 1, asm: arm64.AFABSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGS", argLen: 1, asm: arm64.AFNEGS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGD", argLen: 1, asm: arm64.AFNEGD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTD", argLen: 1, asm: arm64.AFSQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTS", argLen: 1, asm: arm64.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "REV", argLen: 1, asm: arm64.AREV, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "REVW", argLen: 1, asm: arm64.AREVW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "REV16", argLen: 1, asm: arm64.AREV16, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "REV16W", argLen: 1, asm: arm64.AREV16W, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RBIT", argLen: 1, asm: arm64.ARBIT, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RBITW", argLen: 1, asm: arm64.ARBITW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CLZ", argLen: 1, asm: arm64.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CLZW", argLen: 1, asm: arm64.ACLZW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "VCNT", argLen: 1, asm: arm64.AVCNT, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "VUADDLV", argLen: 1, asm: arm64.AVUADDLV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDS", argLen: 3, asm: arm64.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDD", argLen: 3, asm: arm64.AFMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDS", argLen: 3, asm: arm64.AFNMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDD", argLen: 3, asm: arm64.AFNMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBS", argLen: 3, asm: arm64.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBD", argLen: 3, asm: arm64.AFMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBS", argLen: 3, asm: arm64.AFNMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBD", argLen: 3, asm: arm64.AFNMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MADD", argLen: 3, asm: arm64.AMADD, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MADDW", argLen: 3, asm: arm64.AMADDW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MSUB", argLen: 3, asm: arm64.AMSUB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MSUBW", argLen: 3, asm: arm64.AMSUBW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SLL", argLen: 2, asm: arm64.ALSL, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SLLconst", auxType: auxInt64, argLen: 1, asm: arm64.ALSL, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRL", argLen: 2, asm: arm64.ALSR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRLconst", auxType: auxInt64, argLen: 1, asm: arm64.ALSR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRA", argLen: 2, asm: arm64.AASR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRAconst", auxType: auxInt64, argLen: 1, asm: arm64.AASR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ROR", argLen: 2, asm: arm64.AROR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RORW", argLen: 2, asm: arm64.ARORW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RORconst", auxType: auxInt64, argLen: 1, asm: arm64.AROR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RORWconst", auxType: auxInt64, argLen: 1, asm: arm64.ARORW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EXTRconst", auxType: auxInt64, argLen: 2, asm: arm64.AEXTR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EXTRWconst", auxType: auxInt64, argLen: 2, asm: arm64.AEXTRW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CMP", argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPconst", auxType: auxInt64, argLen: 1, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPW", argLen: 2, asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMN", argLen: 2, commutative: true, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNconst", auxType: auxInt64, argLen: 1, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNW", argLen: 2, commutative: true, asm: arm64.ACMNW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNWconst", auxType: auxInt32, argLen: 1, asm: arm64.ACMNW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TST", argLen: 2, commutative: true, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTconst", auxType: auxInt64, argLen: 1, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTW", argLen: 2, commutative: true, asm: arm64.ATSTW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTWconst", auxType: auxInt32, argLen: 1, asm: arm64.ATSTW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "FCMPS", argLen: 2, asm: arm64.AFCMPS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCMPD", argLen: 2, asm: arm64.AFCMPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCMPS0", argLen: 1, asm: arm64.AFCMPS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCMPD0", argLen: 1, asm: arm64.AFCMPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MVNshiftLL", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVNshiftRL", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVNshiftRA", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVNshiftRO", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGshiftLL", auxType: auxInt64, argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGshiftRL", auxType: auxInt64, argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGshiftRA", auxType: auxInt64, argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CMPshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "BFI", auxType: auxARM64BitField, argLen: 2, resultInArg0: true, asm: arm64.ABFI, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BFXIL", auxType: auxARM64BitField, argLen: 2, resultInArg0: true, asm: arm64.ABFXIL, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SBFIZ", auxType: auxARM64BitField, argLen: 1, asm: arm64.ASBFIZ, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SBFX", auxType: auxARM64BitField, argLen: 1, asm: arm64.ASBFX, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UBFIZ", auxType: auxARM64BitField, argLen: 1, asm: arm64.AUBFIZ, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UBFX", auxType: auxARM64BitField, argLen: 1, asm: arm64.AUBFX, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: arm64.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm64.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm64.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037928517632}, // SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDloadidx", argLen: 3, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUloadidx", argLen: 3, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUloadidx", argLen: 3, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBloadidx", argLen: 3, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBUloadidx", argLen: 3, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSloadidx", argLen: 3, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDloadidx", argLen: 3, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVHloadidx2", argLen: 3, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUloadidx2", argLen: 3, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWloadidx4", argLen: 3, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUloadidx4", argLen: 3, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDloadidx8", argLen: 3, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSloadidx4", argLen: 3, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDloadidx8", argLen: 3, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "STP", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.ASTP, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstoreidx", argLen: 4, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVSstoreidx", argLen: 4, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstoreidx", argLen: 4, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVHstoreidx2", argLen: 4, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstoreidx4", argLen: 4, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstoreidx8", argLen: 4, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVSstoreidx4", argLen: 4, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstoreidx8", argLen: 4, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVQstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.ASTP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVBstorezeroidx", argLen: 3, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstorezeroidx", argLen: 3, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstorezeroidx", argLen: 3, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstorezeroidx", argLen: 3, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstorezeroidx2", argLen: 3, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstorezeroidx4", argLen: 3, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstorezeroidx8", argLen: 3, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVDgpfp", argLen: 1, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDfpgp", argLen: 1, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSgpfp", argLen: 1, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVSfpgp", argLen: 1, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBreg", argLen: 1, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBUreg", argLen: 1, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHreg", argLen: 1, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUreg", argLen: 1, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWreg", argLen: 1, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUreg", argLen: 1, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDreg", argLen: 1, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SCVTFWS", argLen: 1, asm: arm64.ASCVTFWS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SCVTFWD", argLen: 1, asm: arm64.ASCVTFWD, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFWS", argLen: 1, asm: arm64.AUCVTFWS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFWD", argLen: 1, asm: arm64.AUCVTFWD, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SCVTFS", argLen: 1, asm: arm64.ASCVTFS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SCVTFD", argLen: 1, asm: arm64.ASCVTFD, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFS", argLen: 1, asm: arm64.AUCVTFS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFD", argLen: 1, asm: arm64.AUCVTFD, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTZSSW", argLen: 1, asm: arm64.AFCVTZSSW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZSDW", argLen: 1, asm: arm64.AFCVTZSDW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUSW", argLen: 1, asm: arm64.AFCVTZUSW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUDW", argLen: 1, asm: arm64.AFCVTZUDW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZSS", argLen: 1, asm: arm64.AFCVTZSS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZSD", argLen: 1, asm: arm64.AFCVTZSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUS", argLen: 1, asm: arm64.AFCVTZUS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUD", argLen: 1, asm: arm64.AFCVTZUD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTSD", argLen: 1, asm: arm64.AFCVTSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTDS", argLen: 1, asm: arm64.AFCVTDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTAD", argLen: 1, asm: arm64.AFRINTAD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTMD", argLen: 1, asm: arm64.AFRINTMD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTND", argLen: 1, asm: arm64.AFRINTND, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTPD", argLen: 1, asm: arm64.AFRINTPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTZD", argLen: 1, asm: arm64.AFRINTZD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CSEL", auxType: auxCCop, argLen: 3, asm: arm64.ACSEL, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSEL0", auxType: auxCCop, argLen: 2, asm: arm64.ACSEL, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSINC", auxType: auxCCop, argLen: 3, asm: arm64.ACSINC, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSINV", auxType: auxCCop, argLen: 3, asm: arm64.ACSINV, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSNEG", auxType: auxCCop, argLen: 3, asm: arm64.ACSNEG, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSETM", auxType: auxCCop, argLen: 1, asm: arm64.ACSETM, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 67108864}, // R26 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP }, clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotLessThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotLessEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotGreaterThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotGreaterEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 }, clobbers: 538116096, // R16 R17 R20 R30 }, }, { name: "LoweredZero", argLen: 3, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 65536}, // R16 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, clobbers: 65536, // R16 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 2097152}, // R21 {1, 1048576}, // R20 }, clobbers: 607322112, // R16 R17 R20 R21 R26 R30 }, }, { name: "LoweredMove", argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 131072}, // R17 {1, 65536}, // R16 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, clobbers: 196608, // R16 R17 }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 67108864}, // R26 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FlagConstant", auxType: auxFlagConstant, argLen: 0, reg: regInfo{}, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LDAR", argLen: 2, faultOnNilArg0: true, asm: arm64.ALDAR, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LDARB", argLen: 2, faultOnNilArg0: true, asm: arm64.ALDARB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LDARW", argLen: 2, faultOnNilArg0: true, asm: arm64.ALDARW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "STLRB", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: arm64.ASTLRB, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "STLR", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: arm64.ASTLR, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "STLRW", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: arm64.ASTLRW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange64Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd64Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas64Variant", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas32Variant", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd8", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr8", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd8Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr8Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, clobbers: 9223372035244359680, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "PRFM", auxType: auxInt64, argLen: 2, hasSideEffects: true, asm: arm64.APRFM, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "DMB", auxType: auxInt64, argLen: 1, hasSideEffects: true, asm: arm64.ADMB, reg: regInfo{}, }, { name: "ADD", argLen: 2, commutative: true, asm: mips.AADDU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, asm: mips.AADDU, reg: regInfo{ inputs: []inputInfo{ {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SUB", argLen: 2, asm: mips.ASUBU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, asm: mips.ASUBU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: mips.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, clobbers: 105553116266496, // HI LO outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MULT", argLen: 2, commutative: true, asm: mips.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "MULTU", argLen: 2, commutative: true, asm: mips.AMULU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "DIV", argLen: 2, asm: mips.ADIV, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "DIVU", argLen: 2, asm: mips.ADIVU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: mips.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: mips.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SUBF", argLen: 2, asm: mips.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SUBD", argLen: 2, asm: mips.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: mips.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: mips.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "DIVF", argLen: 2, asm: mips.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "DIVD", argLen: 2, asm: mips.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "ANDconst", auxType: auxInt32, argLen: 1, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "ORconst", auxType: auxInt32, argLen: 1, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "XORconst", auxType: auxInt32, argLen: 1, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NORconst", auxType: auxInt32, argLen: 1, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NEG", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NEGF", argLen: 1, asm: mips.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "NEGD", argLen: 1, asm: mips.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SQRTD", argLen: 1, asm: mips.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SQRTF", argLen: 1, asm: mips.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SLL", argLen: 2, asm: mips.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SLLconst", auxType: auxInt32, argLen: 1, asm: mips.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRL", argLen: 2, asm: mips.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRLconst", auxType: auxInt32, argLen: 1, asm: mips.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRA", argLen: 2, asm: mips.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRAconst", auxType: auxInt32, argLen: 1, asm: mips.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CLZ", argLen: 1, asm: mips.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGT", argLen: 2, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTconst", auxType: auxInt32, argLen: 1, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTzero", argLen: 1, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTU", argLen: 2, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTUconst", auxType: auxInt32, argLen: 1, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTUzero", argLen: 1, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CMPEQF", argLen: 2, asm: mips.ACMPEQF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPEQD", argLen: 2, asm: mips.ACMPEQD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGEF", argLen: 2, asm: mips.ACMPGEF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGED", argLen: 2, asm: mips.ACMPGED, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGTF", argLen: 2, asm: mips.ACMPGTF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGTD", argLen: 2, asm: mips.ACMPGTD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVWconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: mips.AMOVW, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVFconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: mips.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: mips.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVWaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 140737555464192}, // SP SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVBreg", argLen: 1, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVBUreg", argLen: 1, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHreg", argLen: 1, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHUreg", argLen: 1, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWreg", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CMOVZ", argLen: 3, resultInArg0: true, asm: mips.ACMOVZ, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CMOVZzero", argLen: 2, resultInArg0: true, asm: mips.ACMOVZ, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWF", argLen: 1, asm: mips.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVWD", argLen: 1, asm: mips.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "TRUNCFW", argLen: 1, asm: mips.ATRUNCFW, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "TRUNCDW", argLen: 1, asm: mips.ATRUNCDW, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVFD", argLen: 1, asm: mips.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVDF", argLen: 1, asm: mips.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4194304}, // R22 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 }, clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicStorezero", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicExchange", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicAdd", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicAddconst", auxType: auxInt32, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicCas", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicAnd", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicOr", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredZero", auxType: auxInt32, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, clobbers: 2, // R1 }, }, { name: "LoweredMove", auxType: auxInt32, argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, clobbers: 6, // R1 R2 }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, }, }, { name: "FPFlagTrue", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "FPFlagFalse", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4194304}, // R22 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 8}, // R3 {1, 16}, // R4 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicExtendA", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 8}, // R3 {2, 16}, // R4 }, }, }, { name: "LoweredPanicExtendB", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 4}, // R2 {2, 8}, // R3 }, }, }, { name: "LoweredPanicExtendC", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 2}, // R1 {2, 4}, // R2 }, }, }, { name: "ADDV", argLen: 2, commutative: true, asm: mips.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "ADDVconst", auxType: auxInt64, argLen: 1, asm: mips.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SUBV", argLen: 2, asm: mips.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SUBVconst", auxType: auxInt64, argLen: 1, asm: mips.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MULV", argLen: 2, commutative: true, asm: mips.AMULV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "MULVU", argLen: 2, commutative: true, asm: mips.AMULVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "DIVV", argLen: 2, asm: mips.ADIVV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "DIVVU", argLen: 2, asm: mips.ADIVVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: mips.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: mips.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBF", argLen: 2, asm: mips.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBD", argLen: 2, asm: mips.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: mips.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: mips.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVF", argLen: 2, asm: mips.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVD", argLen: 2, asm: mips.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NORconst", auxType: auxInt64, argLen: 1, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NEGV", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NEGF", argLen: 1, asm: mips.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "NEGD", argLen: 1, asm: mips.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTD", argLen: 1, asm: mips.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTF", argLen: 1, asm: mips.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SLLV", argLen: 2, asm: mips.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SLLVconst", auxType: auxInt64, argLen: 1, asm: mips.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRLV", argLen: 2, asm: mips.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRLVconst", auxType: auxInt64, argLen: 1, asm: mips.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRAV", argLen: 2, asm: mips.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRAVconst", auxType: auxInt64, argLen: 1, asm: mips.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGT", argLen: 2, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGTconst", auxType: auxInt64, argLen: 1, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGTU", argLen: 2, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGTUconst", auxType: auxInt64, argLen: 1, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "CMPEQF", argLen: 2, asm: mips.ACMPEQF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPEQD", argLen: 2, asm: mips.ACMPEQD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGEF", argLen: 2, asm: mips.ACMPGEF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGED", argLen: 2, asm: mips.ACMPGED, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTF", argLen: 2, asm: mips.ACMPGTF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTD", argLen: 2, asm: mips.ACMPGTD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: mips.AMOVV, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVFconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: mips.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: mips.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018460942336}, // SP SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVVstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVVstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVBreg", argLen: 1, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVBUreg", argLen: 1, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHreg", argLen: 1, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHUreg", argLen: 1, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWreg", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWUreg", argLen: 1, asm: mips.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVreg", argLen: 1, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWF", argLen: 1, asm: mips.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVWD", argLen: 1, asm: mips.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVF", argLen: 1, asm: mips.AMOVVF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVD", argLen: 1, asm: mips.AMOVVD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFW", argLen: 1, asm: mips.ATRUNCFW, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDW", argLen: 1, asm: mips.ATRUNCDW, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFV", argLen: 1, asm: mips.ATRUNCFV, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDV", argLen: 1, asm: mips.ATRUNCDV, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVFD", argLen: 1, asm: mips.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDF", argLen: 1, asm: mips.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4194304}, // R22 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 }, clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 134217730, // R1 R31 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 }, clobbers: 134217734, // R1 R2 R31 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 2, // R1 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 6, // R1 R2 }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicLoad64", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStore64", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStorezero32", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStorezero64", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAddconst32", auxType: auxInt32, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAddconst64", auxType: auxInt64, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, }, }, { name: "FPFlagTrue", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "FPFlagFalse", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4194304}, // R22 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 8}, // R3 {1, 16}, // R4 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: ppc64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDconst", auxType: auxInt64, argLen: 1, asm: ppc64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FADD", argLen: 2, commutative: true, asm: ppc64.AFADD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: ppc64.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "SUB", argLen: 2, asm: ppc64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBFCconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FSUB", argLen: 2, asm: ppc64.AFSUB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FSUBS", argLen: 2, asm: ppc64.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MULLD", argLen: 2, commutative: true, asm: ppc64.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLW", argLen: 2, commutative: true, asm: ppc64.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLDconst", auxType: auxInt32, argLen: 1, asm: ppc64.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLWconst", auxType: auxInt32, argLen: 1, asm: ppc64.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MADDLD", argLen: 3, asm: ppc64.AMADDLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHD", argLen: 2, commutative: true, asm: ppc64.AMULHD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHW", argLen: 2, commutative: true, asm: ppc64.AMULHW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHDU", argLen: 2, commutative: true, asm: ppc64.AMULHDU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHWU", argLen: 2, commutative: true, asm: ppc64.AMULHWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredMuluhilo", argLen: 2, resultNotInArgs: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMUL", argLen: 2, commutative: true, asm: ppc64.AFMUL, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: ppc64.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMADD", argLen: 3, asm: ppc64.AFMADD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMADDS", argLen: 3, asm: ppc64.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMSUB", argLen: 3, asm: ppc64.AFMSUB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMSUBS", argLen: 3, asm: ppc64.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "SRAD", argLen: 2, asm: ppc64.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRAW", argLen: 2, asm: ppc64.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRD", argLen: 2, asm: ppc64.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRW", argLen: 2, asm: ppc64.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLD", argLen: 2, asm: ppc64.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLW", argLen: 2, asm: ppc64.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTL", argLen: 2, asm: ppc64.AROTL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTLW", argLen: 2, asm: ppc64.AROTLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLDICL", auxType: auxInt32, argLen: 1, asm: ppc64.ARLDICL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CLRLSLWI", auxType: auxInt32, argLen: 1, asm: ppc64.ACLRLSLWI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CLRLSLDI", auxType: auxInt32, argLen: 1, asm: ppc64.ACLRLSLDI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDC", argLen: 2, commutative: true, asm: ppc64.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBC", argLen: 2, asm: ppc64.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDCconst", auxType: auxInt64, argLen: 1, asm: ppc64.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBCconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDE", argLen: 3, commutative: true, asm: ppc64.AADDE, reg: regInfo{ inputs: []inputInfo{ {2, 9223372036854775808}, // XER {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBE", argLen: 3, asm: ppc64.ASUBE, reg: regInfo{ inputs: []inputInfo{ {2, 9223372036854775808}, // XER {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDZEzero", argLen: 1, asm: ppc64.AADDZE, reg: regInfo{ inputs: []inputInfo{ {0, 9223372036854775808}, // XER }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBZEzero", argLen: 1, asm: ppc64.ASUBZE, reg: regInfo{ inputs: []inputInfo{ {0, 9223372036854775808}, // XER }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRADconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRAWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRDconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLDconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTLconst", auxType: auxInt64, argLen: 1, asm: ppc64.AROTL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTLWconst", auxType: auxInt64, argLen: 1, asm: ppc64.AROTLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "EXTSWSLconst", auxType: auxInt64, argLen: 1, asm: ppc64.AEXTSWSLI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLWINM", auxType: auxInt64, argLen: 1, asm: ppc64.ARLWNM, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLWNM", auxType: auxInt64, argLen: 2, asm: ppc64.ARLWNM, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLWMI", auxType: auxInt64, argLen: 2, resultInArg0: true, asm: ppc64.ARLWMI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTLZD", argLen: 1, clobberFlags: true, asm: ppc64.ACNTLZD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTLZW", argLen: 1, clobberFlags: true, asm: ppc64.ACNTLZW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTTZD", argLen: 1, asm: ppc64.ACNTTZD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTTZW", argLen: 1, asm: ppc64.ACNTTZW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "POPCNTD", argLen: 1, asm: ppc64.APOPCNTD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "POPCNTW", argLen: 1, asm: ppc64.APOPCNTW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "POPCNTB", argLen: 1, asm: ppc64.APOPCNTB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FDIV", argLen: 2, asm: ppc64.AFDIV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FDIVS", argLen: 2, asm: ppc64.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "DIVD", argLen: 2, asm: ppc64.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVW", argLen: 2, asm: ppc64.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVDU", argLen: 2, asm: ppc64.ADIVDU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVWU", argLen: 2, asm: ppc64.ADIVWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODUD", argLen: 2, asm: ppc64.AMODUD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODSD", argLen: 2, asm: ppc64.AMODSD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODUW", argLen: 2, asm: ppc64.AMODUW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODSW", argLen: 2, asm: ppc64.AMODSW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FCTIDZ", argLen: 1, asm: ppc64.AFCTIDZ, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCTIWZ", argLen: 1, asm: ppc64.AFCTIWZ, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCFID", argLen: 1, asm: ppc64.AFCFID, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCFIDS", argLen: 1, asm: ppc64.AFCFIDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FRSP", argLen: 1, asm: ppc64.AFRSP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MFVSRD", argLen: 1, asm: ppc64.AMFVSRD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MTVSRD", argLen: 1, asm: ppc64.AMTVSRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDN", argLen: 2, asm: ppc64.AANDN, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDCC", argLen: 2, commutative: true, asm: ppc64.AANDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ORN", argLen: 2, asm: ppc64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ORCC", argLen: 2, commutative: true, asm: ppc64.AORCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: ppc64.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: ppc64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XORCC", argLen: 2, commutative: true, asm: ppc64.AXORCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "EQV", argLen: 2, commutative: true, asm: ppc64.AEQV, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NEG", argLen: 1, asm: ppc64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FNEG", argLen: 1, asm: ppc64.AFNEG, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FSQRT", argLen: 1, asm: ppc64.AFSQRT, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FSQRTS", argLen: 1, asm: ppc64.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FFLOOR", argLen: 1, asm: ppc64.AFRIM, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCEIL", argLen: 1, asm: ppc64.AFRIP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FTRUNC", argLen: 1, asm: ppc64.AFRIZ, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FROUND", argLen: 1, asm: ppc64.AFRIN, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FABS", argLen: 1, asm: ppc64.AFABS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FNABS", argLen: 1, asm: ppc64.AFNABS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCPSGN", argLen: 2, asm: ppc64.AFCPSGN, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: ppc64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, clobberFlags: true, asm: ppc64.AANDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDCCconst", auxType: auxInt64, argLen: 1, asm: ppc64.AANDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBreg", argLen: 1, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZreg", argLen: 1, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHreg", argLen: 1, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZreg", argLen: 1, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWreg", argLen: 1, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZreg", argLen: 1, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZloadidx", argLen: 3, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZloadidx", argLen: 3, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZloadidx", argLen: 3, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDloadidx", argLen: 3, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHBRloadidx", argLen: 3, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRloadidx", argLen: 3, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRloadidx", argLen: 3, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDloadidx", argLen: 3, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSloadidx", argLen: 3, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "DCBT", auxType: auxInt64, argLen: 2, hasSideEffects: true, asm: ppc64.ADCBT, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRstore", auxType: auxSym, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRstore", auxType: auxSym, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHBRstore", auxType: auxSym, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstoreidx", argLen: 4, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDstoreidx", argLen: 4, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSstoreidx", argLen: 4, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MOVHBRstoreidx", argLen: 4, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRstoreidx", argLen: 4, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRstoreidx", argLen: 4, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: ppc64.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: ppc64.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: ppc64.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCMPU", argLen: 2, asm: ppc64.AFCMPU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "CMP", argLen: 2, asm: ppc64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPU", argLen: 2, asm: ppc64.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPW", argLen: 2, asm: ppc64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWU", argLen: 2, asm: ppc64.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPconst", auxType: auxInt64, argLen: 1, asm: ppc64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPUconst", auxType: auxInt64, argLen: 1, asm: ppc64.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: ppc64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWUconst", auxType: auxInt32, argLen: 1, asm: ppc64.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ISEL", auxType: auxInt32, argLen: 3, asm: ppc64.AISEL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ISELB", auxType: auxInt32, argLen: 2, asm: ppc64.AISEL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FLessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FLessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FGreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FGreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 2048}, // R11 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 2147483648, // R31 }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4096}, // R12 {1, 2048}, // R11 }, clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4096}, // R12 }, clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 }, clobbers: 1048576, // R20 }, }, { name: "LoweredZeroShort", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredQuadZeroShort", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredQuadZero", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 }, clobbers: 1048576, // R20 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 3145728, // R20 R21 }, }, { name: "LoweredMoveShort", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredQuadMove", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 3145728, // R20 R21 }, }, { name: "LoweredQuadMoveShort", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicStore8", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicStore32", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicStore64", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoad8", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoad32", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoad64", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoadPtr", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicCas64", auxType: auxInt64, argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicCas32", auxType: auxInt64, argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAnd8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicOr8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicOr32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "LoweredPubBarrier", argLen: 1, hasSideEffects: true, asm: ppc64.ALWSYNC, reg: regInfo{}, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 64}, // R6 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 32}, // R5 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 8}, // R3 {1, 16}, // R4 }, }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT", argLen: 0, reg: regInfo{}, }, { name: "ADD", argLen: 2, commutative: true, asm: riscv.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ADDI", auxType: auxInt64, argLen: 1, asm: riscv.AADDI, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ADDIW", auxType: auxInt64, argLen: 1, asm: riscv.AADDIW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "NEG", argLen: 1, asm: riscv.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "NEGW", argLen: 1, asm: riscv.ANEGW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SUB", argLen: 2, asm: riscv.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SUBW", argLen: 2, asm: riscv.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: riscv.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MULW", argLen: 2, commutative: true, asm: riscv.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MULH", argLen: 2, commutative: true, asm: riscv.AMULH, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MULHU", argLen: 2, commutative: true, asm: riscv.AMULHU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredMuluhilo", argLen: 2, resultNotInArgs: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredMuluover", argLen: 2, resultNotInArgs: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIV", argLen: 2, asm: riscv.ADIV, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIVU", argLen: 2, asm: riscv.ADIVU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIVW", argLen: 2, asm: riscv.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIVUW", argLen: 2, asm: riscv.ADIVUW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REM", argLen: 2, asm: riscv.AREM, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REMU", argLen: 2, asm: riscv.AREMU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REMW", argLen: 2, asm: riscv.AREMW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REMUW", argLen: 2, asm: riscv.AREMUW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymRdWr, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: riscv.AMOV, reg: regInfo{ outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVDstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVBreg", argLen: 1, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHreg", argLen: 1, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWreg", argLen: 1, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDreg", argLen: 1, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBUreg", argLen: 1, asm: riscv.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHUreg", argLen: 1, asm: riscv.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWUreg", argLen: 1, asm: riscv.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLL", argLen: 2, asm: riscv.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRA", argLen: 2, asm: riscv.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRL", argLen: 2, asm: riscv.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLLI", auxType: auxInt64, argLen: 1, asm: riscv.ASLLI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRAI", auxType: auxInt64, argLen: 1, asm: riscv.ASRAI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRLI", auxType: auxInt64, argLen: 1, asm: riscv.ASRLI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: riscv.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "XORI", auxType: auxInt64, argLen: 1, asm: riscv.AXORI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: riscv.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ORI", auxType: auxInt64, argLen: 1, asm: riscv.AORI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: riscv.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ANDI", auxType: auxInt64, argLen: 1, asm: riscv.AANDI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "NOT", argLen: 1, asm: riscv.ANOT, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SEQZ", argLen: 1, asm: riscv.ASEQZ, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SNEZ", argLen: 1, asm: riscv.ASNEZ, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLT", argLen: 2, asm: riscv.ASLT, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLTI", auxType: auxInt64, argLen: 1, asm: riscv.ASLTI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLTU", argLen: 2, asm: riscv.ASLTU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLTIU", auxType: auxInt64, argLen: 1, asm: riscv.ASLTIU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVconvert", argLen: 2, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, call: true, reg: regInfo{ clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, call: true, tailCall: true, reg: regInfo{ clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 33554432}, // X26 {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 16777216}, // X25 }, clobbers: 16777216, // X25 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 16777216}, // X25 {1, 8388608}, // X24 }, clobbers: 25165824, // X24 X25 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 16, // X5 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 32}, // X6 {2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 112, // X5 X6 X7 }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicLoad64", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "LoweredAtomicStore64", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: riscv.AAMOANDW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, }, }, { name: "LoweredAtomicOr32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: riscv.AAMOORW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 33554432}, // X26 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 32}, // X6 }, clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // X7 {1, 134217728}, // X28 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // X6 {1, 64}, // X7 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 32}, // X6 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: riscv.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBS", argLen: 2, asm: riscv.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: riscv.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVS", argLen: 2, asm: riscv.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTS", argLen: 1, asm: riscv.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGS", argLen: 1, asm: riscv.AFNEGS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMVSX", argLen: 1, asm: riscv.AFMVSX, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTSW", argLen: 1, asm: riscv.AFCVTSW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTSL", argLen: 1, asm: riscv.AFCVTSL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTWS", argLen: 1, asm: riscv.AFCVTWS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FCVTLS", argLen: 1, asm: riscv.AFCVTLS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FMOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FEQS", argLen: 2, commutative: true, asm: riscv.AFEQS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FNES", argLen: 2, commutative: true, asm: riscv.AFNES, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLTS", argLen: 2, asm: riscv.AFLTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLES", argLen: 2, asm: riscv.AFLES, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FADDD", argLen: 2, commutative: true, asm: riscv.AFADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBD", argLen: 2, asm: riscv.AFSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULD", argLen: 2, commutative: true, asm: riscv.AFMULD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVD", argLen: 2, asm: riscv.AFDIVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDD", argLen: 3, commutative: true, asm: riscv.AFMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBD", argLen: 3, commutative: true, asm: riscv.AFMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDD", argLen: 3, commutative: true, asm: riscv.AFNMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBD", argLen: 3, commutative: true, asm: riscv.AFNMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTD", argLen: 1, asm: riscv.AFSQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGD", argLen: 1, asm: riscv.AFNEGD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FABSD", argLen: 1, asm: riscv.AFABSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSGNJD", argLen: 2, asm: riscv.AFSGNJD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMVDX", argLen: 1, asm: riscv.AFMVDX, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTDW", argLen: 1, asm: riscv.AFCVTDW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTDL", argLen: 1, asm: riscv.AFCVTDL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTWD", argLen: 1, asm: riscv.AFCVTWD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FCVTLD", argLen: 1, asm: riscv.AFCVTLD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FCVTDS", argLen: 1, asm: riscv.AFCVTDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTSD", argLen: 1, asm: riscv.AFCVTSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FEQD", argLen: 2, commutative: true, asm: riscv.AFEQD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FNED", argLen: 2, commutative: true, asm: riscv.AFNED, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLTD", argLen: 2, asm: riscv.AFLTD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLED", argLen: 2, asm: riscv.AFLED, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FADDS", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FADD", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFADD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FSUBS", argLen: 2, resultInArg0: true, asm: s390x.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FSUB", argLen: 2, resultInArg0: true, asm: s390x.AFSUB, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMULS", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMUL", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFMUL, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FDIVS", argLen: 2, resultInArg0: true, asm: s390x.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FDIV", argLen: 2, resultInArg0: true, asm: s390x.AFDIV, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FNEGS", argLen: 1, clobberFlags: true, asm: s390x.AFNEGS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FNEG", argLen: 1, clobberFlags: true, asm: s390x.AFNEG, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMADDS", argLen: 3, resultInArg0: true, asm: s390x.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMADD", argLen: 3, resultInArg0: true, asm: s390x.AFMADD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMSUBS", argLen: 3, resultInArg0: true, asm: s390x.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMSUB", argLen: 3, resultInArg0: true, asm: s390x.AFMSUB, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LPDFR", argLen: 1, asm: s390x.ALPDFR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LNDFR", argLen: 1, asm: s390x.ALNDFR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CPSDR", argLen: 2, asm: s390x.ACPSDR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FIDBR", auxType: auxInt8, argLen: 1, asm: s390x.AFIDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: s390x.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: s390x.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSloadidx", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDloadidx", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSstoreidx", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDstoreidx", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ADD", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AADD, reg: regInfo{ inputs: []inputInfo{ {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AADDW, reg: regInfo{ inputs: []inputInfo{ {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: s390x.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDWconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: s390x.AADDW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AADDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUB", argLen: 2, clobberFlags: true, asm: s390x.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBW", argLen: 2, clobberFlags: true, asm: s390x.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLD", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLW", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLDconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULHD", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULHD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULHDU", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULHDU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVD", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVDU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVDU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVWU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVWU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODD", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODDU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODDU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODWU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODWU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "AND", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "OR", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XOR", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDC", argLen: 2, commutative: true, asm: s390x.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDCconst", auxType: auxInt16, argLen: 1, asm: s390x.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDE", argLen: 3, commutative: true, resultInArg0: true, asm: s390x.AADDE, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBC", argLen: 2, asm: s390x.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBE", argLen: 3, resultInArg0: true, asm: s390x.ASUBE, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CMP", argLen: 2, asm: s390x.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPW", argLen: 2, asm: s390x.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPU", argLen: 2, asm: s390x.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPWU", argLen: 2, asm: s390x.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPUconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPWUconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "FCMPS", argLen: 2, asm: s390x.ACEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FCMP", argLen: 2, asm: s390x.AFCMPU, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LTDBR", argLen: 1, asm: s390x.ALTDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LTEBR", argLen: 1, asm: s390x.ALTEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SLD", argLen: 2, asm: s390x.ASLD, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SLW", argLen: 2, asm: s390x.ASLW, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SLDconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SLWconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRD", argLen: 2, asm: s390x.ASRD, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRW", argLen: 2, asm: s390x.ASRW, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRDconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRWconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRAD", argLen: 2, clobberFlags: true, asm: s390x.ASRAD, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRAW", argLen: 2, clobberFlags: true, asm: s390x.ASRAW, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRADconst", auxType: auxUInt8, argLen: 1, clobberFlags: true, asm: s390x.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRAWconst", auxType: auxUInt8, argLen: 1, clobberFlags: true, asm: s390x.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RLLG", argLen: 2, asm: s390x.ARLLG, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RLL", argLen: 2, asm: s390x.ARLL, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RLLconst", auxType: auxUInt8, argLen: 1, asm: s390x.ARLL, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RXSBG", auxType: auxS390XRotateParams, argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ARXSBG, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RISBGZ", auxType: auxS390XRotateParams, argLen: 1, clobberFlags: true, asm: s390x.ARISBGZ, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NEG", argLen: 1, clobberFlags: true, asm: s390x.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NEGW", argLen: 1, clobberFlags: true, asm: s390x.ANEGW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NOT", argLen: 1, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NOTW", argLen: 1, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "FSQRT", argLen: 1, asm: s390x.AFSQRT, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FSQRTS", argLen: 1, asm: s390x.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LOCGR", auxType: auxS390XCCMask, argLen: 3, resultInArg0: true, asm: s390x.ALOCGR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBreg", argLen: 1, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBZreg", argLen: 1, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHreg", argLen: 1, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHZreg", argLen: 1, asm: s390x.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWreg", argLen: 1, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZreg", argLen: 1, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: s390x.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LDGR", argLen: 1, asm: s390x.ALDGR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LGDR", argLen: 1, asm: s390x.ALGDR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CFDBRA", argLen: 1, clobberFlags: true, asm: s390x.ACFDBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CGDBRA", argLen: 1, clobberFlags: true, asm: s390x.ACGDBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CFEBRA", argLen: 1, clobberFlags: true, asm: s390x.ACFEBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CGEBRA", argLen: 1, clobberFlags: true, asm: s390x.ACGEBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CEFBRA", argLen: 1, clobberFlags: true, asm: s390x.ACEFBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDFBRA", argLen: 1, clobberFlags: true, asm: s390x.ACDFBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CEGBRA", argLen: 1, clobberFlags: true, asm: s390x.ACEGBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDGBRA", argLen: 1, clobberFlags: true, asm: s390x.ACDGBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CLFEBR", argLen: 1, clobberFlags: true, asm: s390x.ACLFEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CLFDBR", argLen: 1, clobberFlags: true, asm: s390x.ACLFDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CLGEBR", argLen: 1, clobberFlags: true, asm: s390x.ACLGEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CLGDBR", argLen: 1, clobberFlags: true, asm: s390x.ACLGDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CELFBR", argLen: 1, clobberFlags: true, asm: s390x.ACELFBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDLFBR", argLen: 1, clobberFlags: true, asm: s390x.ACDLFBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CELGBR", argLen: 1, clobberFlags: true, asm: s390x.ACELGBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDLGBR", argLen: 1, clobberFlags: true, asm: s390x.ACDLGBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LEDBR", argLen: 1, asm: s390x.ALEDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LDEBR", argLen: 1, asm: s390x.ALDEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymRead, reg: regInfo{ inputs: []inputInfo{ {0, 4295000064}, // SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDaddridx", auxType: auxSymOff, argLen: 2, symEffect: SymRead, reg: regInfo{ inputs: []inputInfo{ {0, 4295000064}, // SP SB {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWBR", argLen: 1, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDBR", argLen: 1, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHBRstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWBRstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDBRstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MVC", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, symEffect: SymNone, asm: s390x.AMVC, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVBZloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHZloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHBRloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWBRloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDBRloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHBRstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWBRstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDBRstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "MOVHstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "MOVDstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "CLEAR", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ACLEAR, reg: regInfo{ inputs: []inputInfo{ {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4096}, // R12 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4096}, // R12 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT", argLen: 0, reg: regInfo{}, }, { name: "FlagOV", argLen: 0, reg: regInfo{}, }, { name: "SYNC", argLen: 1, asm: s390x.ASYNC, reg: regInfo{}, }, { name: "MOVBZatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBatomicstore", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWatomicstore", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDatomicstore", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LAA", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ALAA, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LAAG", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ALAAG, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "AddTupleFirst32", argLen: 2, reg: regInfo{}, }, { name: "AddTupleFirst64", argLen: 2, reg: regInfo{}, }, { name: "LAN", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAN, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LANfloor", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAN, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 2, // R1 }, }, { name: "LAO", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAO, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LAOfloor", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAO, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 2, // R1 }, }, { name: "LoweredAtomicCas32", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACS, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // R0 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 1, // R0 outputs: []outputInfo{ {1, 0}, {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredAtomicCas64", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACSG, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // R0 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 1, // R0 outputs: []outputInfo{ {1, 0}, {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredAtomicExchange32", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACS, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {1, 0}, {0, 1}, // R0 }, }, }, { name: "LoweredAtomicExchange64", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACSG, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {1, 0}, {0, 1}, // R0 }, }, }, { name: "FLOGR", argLen: 1, clobberFlags: true, asm: s390x.AFLOGR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, clobbers: 2, // R1 outputs: []outputInfo{ {0, 1}, // R0 }, }, }, { name: "POPCNT", argLen: 1, clobberFlags: true, asm: s390x.APOPCNT, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MLGR", argLen: 2, asm: s390x.AMLGR, reg: regInfo{ inputs: []inputInfo{ {1, 8}, // R3 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "SumBytes2", argLen: 1, reg: regInfo{}, }, { name: "SumBytes4", argLen: 1, reg: regInfo{}, }, { name: "SumBytes8", argLen: 1, reg: regInfo{}, }, { name: "STMG2", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMG, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STMG3", auxType: auxSymOff, argLen: 5, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMG, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STMG4", auxType: auxSymOff, argLen: 6, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMG, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {4, 16}, // R4 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STM2", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMY, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STM3", auxType: auxSymOff, argLen: 5, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMY, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STM4", auxType: auxSymOff, argLen: 6, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMY, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {4, 16}, // R4 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 6, // R1 R2 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 2, // R1 }, }, { name: "LoweredStaticCall", auxType: auxCallOff, argLen: 1, call: true, reg: regInfo{ clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredTailCall", auxType: auxCallOff, argLen: 1, call: true, tailCall: true, reg: regInfo{ clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredClosureCall", auxType: auxCallOff, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredInterCall", auxType: auxCallOff, argLen: 2, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredAddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 3, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredConvert", argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "Select", argLen: 3, asm: wasm.ASelect, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load8U", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load8U, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load8S", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load8S, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load16U", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load16U, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load16S", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load16S, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load32U", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load32U, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load32S", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load32S, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Store8", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store8, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Store16", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store16, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Store32", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store32, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Store", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "F32Load", auxType: auxInt64, argLen: 2, asm: wasm.AF32Load, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Load", auxType: auxInt64, argLen: 2, asm: wasm.AF64Load, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F32Store", auxType: auxInt64, argLen: 3, asm: wasm.AF32Store, reg: regInfo{ inputs: []inputInfo{ {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "F64Store", auxType: auxInt64, argLen: 3, asm: wasm.AF64Store, reg: regInfo{ inputs: []inputInfo{ {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Const", auxType: auxInt64, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Const", auxType: auxFloat32, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Const", auxType: auxFloat64, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64Eqz", argLen: 1, asm: wasm.AI64Eqz, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Eq", argLen: 2, asm: wasm.AI64Eq, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Ne", argLen: 2, asm: wasm.AI64Ne, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LtS", argLen: 2, asm: wasm.AI64LtS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LtU", argLen: 2, asm: wasm.AI64LtU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GtS", argLen: 2, asm: wasm.AI64GtS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GtU", argLen: 2, asm: wasm.AI64GtU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LeS", argLen: 2, asm: wasm.AI64LeS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LeU", argLen: 2, asm: wasm.AI64LeU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GeS", argLen: 2, asm: wasm.AI64GeS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GeU", argLen: 2, asm: wasm.AI64GeU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Eq", argLen: 2, asm: wasm.AF32Eq, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Ne", argLen: 2, asm: wasm.AF32Ne, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Lt", argLen: 2, asm: wasm.AF32Lt, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Gt", argLen: 2, asm: wasm.AF32Gt, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Le", argLen: 2, asm: wasm.AF32Le, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Ge", argLen: 2, asm: wasm.AF32Ge, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Eq", argLen: 2, asm: wasm.AF64Eq, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Ne", argLen: 2, asm: wasm.AF64Ne, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Lt", argLen: 2, asm: wasm.AF64Lt, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Gt", argLen: 2, asm: wasm.AF64Gt, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Le", argLen: 2, asm: wasm.AF64Le, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Ge", argLen: 2, asm: wasm.AF64Ge, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Add", argLen: 2, asm: wasm.AI64Add, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64AddConst", auxType: auxInt64, argLen: 1, asm: wasm.AI64Add, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Sub", argLen: 2, asm: wasm.AI64Sub, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Mul", argLen: 2, asm: wasm.AI64Mul, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64DivS", argLen: 2, asm: wasm.AI64DivS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64DivU", argLen: 2, asm: wasm.AI64DivU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64RemS", argLen: 2, asm: wasm.AI64RemS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64RemU", argLen: 2, asm: wasm.AI64RemU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64And", argLen: 2, asm: wasm.AI64And, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Or", argLen: 2, asm: wasm.AI64Or, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Xor", argLen: 2, asm: wasm.AI64Xor, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Shl", argLen: 2, asm: wasm.AI64Shl, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64ShrS", argLen: 2, asm: wasm.AI64ShrS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64ShrU", argLen: 2, asm: wasm.AI64ShrU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Neg", argLen: 1, asm: wasm.AF32Neg, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Add", argLen: 2, asm: wasm.AF32Add, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Sub", argLen: 2, asm: wasm.AF32Sub, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Mul", argLen: 2, asm: wasm.AF32Mul, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Div", argLen: 2, asm: wasm.AF32Div, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Neg", argLen: 1, asm: wasm.AF64Neg, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Add", argLen: 2, asm: wasm.AF64Add, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Sub", argLen: 2, asm: wasm.AF64Sub, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Mul", argLen: 2, asm: wasm.AF64Mul, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Div", argLen: 2, asm: wasm.AF64Div, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64TruncSatF64S", argLen: 1, asm: wasm.AI64TruncSatF64S, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64TruncSatF64U", argLen: 1, asm: wasm.AI64TruncSatF64U, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64TruncSatF32S", argLen: 1, asm: wasm.AI64TruncSatF32S, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64TruncSatF32U", argLen: 1, asm: wasm.AI64TruncSatF32U, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32ConvertI64S", argLen: 1, asm: wasm.AF32ConvertI64S, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32ConvertI64U", argLen: 1, asm: wasm.AF32ConvertI64U, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64ConvertI64S", argLen: 1, asm: wasm.AF64ConvertI64S, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64ConvertI64U", argLen: 1, asm: wasm.AF64ConvertI64U, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F32DemoteF64", argLen: 1, asm: wasm.AF32DemoteF64, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64PromoteF32", argLen: 1, asm: wasm.AF64PromoteF32, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64Extend8S", argLen: 1, asm: wasm.AI64Extend8S, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Extend16S", argLen: 1, asm: wasm.AI64Extend16S, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Extend32S", argLen: 1, asm: wasm.AI64Extend32S, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Sqrt", argLen: 1, asm: wasm.AF32Sqrt, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Trunc", argLen: 1, asm: wasm.AF32Trunc, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Ceil", argLen: 1, asm: wasm.AF32Ceil, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Floor", argLen: 1, asm: wasm.AF32Floor, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Nearest", argLen: 1, asm: wasm.AF32Nearest, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Abs", argLen: 1, asm: wasm.AF32Abs, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Copysign", argLen: 2, asm: wasm.AF32Copysign, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Sqrt", argLen: 1, asm: wasm.AF64Sqrt, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Trunc", argLen: 1, asm: wasm.AF64Trunc, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Ceil", argLen: 1, asm: wasm.AF64Ceil, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Floor", argLen: 1, asm: wasm.AF64Floor, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Nearest", argLen: 1, asm: wasm.AF64Nearest, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Abs", argLen: 1, asm: wasm.AF64Abs, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Copysign", argLen: 2, asm: wasm.AF64Copysign, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64Ctz", argLen: 1, asm: wasm.AI64Ctz, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Clz", argLen: 1, asm: wasm.AI64Clz, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I32Rotl", argLen: 2, asm: wasm.AI32Rotl, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Rotl", argLen: 2, asm: wasm.AI64Rotl, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Popcnt", argLen: 1, asm: wasm.AI64Popcnt, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "Add8", argLen: 2, commutative: true, generic: true, }, { name: "Add16", argLen: 2, commutative: true, generic: true, }, { name: "Add32", argLen: 2, commutative: true, generic: true, }, { name: "Add64", argLen: 2, commutative: true, generic: true, }, { name: "AddPtr", argLen: 2, generic: true, }, { name: "Add32F", argLen: 2, commutative: true, generic: true, }, { name: "Add64F", argLen: 2, commutative: true, generic: true, }, { name: "Sub8", argLen: 2, generic: true, }, { name: "Sub16", argLen: 2, generic: true, }, { name: "Sub32", argLen: 2, generic: true, }, { name: "Sub64", argLen: 2, generic: true, }, { name: "SubPtr", argLen: 2, generic: true, }, { name: "Sub32F", argLen: 2, generic: true, }, { name: "Sub64F", argLen: 2, generic: true, }, { name: "Mul8", argLen: 2, commutative: true, generic: true, }, { name: "Mul16", argLen: 2, commutative: true, generic: true, }, { name: "Mul32", argLen: 2, commutative: true, generic: true, }, { name: "Mul64", argLen: 2, commutative: true, generic: true, }, { name: "Mul32F", argLen: 2, commutative: true, generic: true, }, { name: "Mul64F", argLen: 2, commutative: true, generic: true, }, { name: "Div32F", argLen: 2, generic: true, }, { name: "Div64F", argLen: 2, generic: true, }, { name: "Hmul32", argLen: 2, commutative: true, generic: true, }, { name: "Hmul32u", argLen: 2, commutative: true, generic: true, }, { name: "Hmul64", argLen: 2, commutative: true, generic: true, }, { name: "Hmul64u", argLen: 2, commutative: true, generic: true, }, { name: "Mul32uhilo", argLen: 2, commutative: true, generic: true, }, { name: "Mul64uhilo", argLen: 2, commutative: true, generic: true, }, { name: "Mul32uover", argLen: 2, commutative: true, generic: true, }, { name: "Mul64uover", argLen: 2, commutative: true, generic: true, }, { name: "Avg32u", argLen: 2, generic: true, }, { name: "Avg64u", argLen: 2, generic: true, }, { name: "Div8", argLen: 2, generic: true, }, { name: "Div8u", argLen: 2, generic: true, }, { name: "Div16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Div16u", argLen: 2, generic: true, }, { name: "Div32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Div32u", argLen: 2, generic: true, }, { name: "Div64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Div64u", argLen: 2, generic: true, }, { name: "Div128u", argLen: 3, generic: true, }, { name: "Mod8", argLen: 2, generic: true, }, { name: "Mod8u", argLen: 2, generic: true, }, { name: "Mod16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Mod16u", argLen: 2, generic: true, }, { name: "Mod32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Mod32u", argLen: 2, generic: true, }, { name: "Mod64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Mod64u", argLen: 2, generic: true, }, { name: "And8", argLen: 2, commutative: true, generic: true, }, { name: "And16", argLen: 2, commutative: true, generic: true, }, { name: "And32", argLen: 2, commutative: true, generic: true, }, { name: "And64", argLen: 2, commutative: true, generic: true, }, { name: "Or8", argLen: 2, commutative: true, generic: true, }, { name: "Or16", argLen: 2, commutative: true, generic: true, }, { name: "Or32", argLen: 2, commutative: true, generic: true, }, { name: "Or64", argLen: 2, commutative: true, generic: true, }, { name: "Xor8", argLen: 2, commutative: true, generic: true, }, { name: "Xor16", argLen: 2, commutative: true, generic: true, }, { name: "Xor32", argLen: 2, commutative: true, generic: true, }, { name: "Xor64", argLen: 2, commutative: true, generic: true, }, { name: "Lsh8x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh8x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh8x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh8x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Eq8", argLen: 2, commutative: true, generic: true, }, { name: "Eq16", argLen: 2, commutative: true, generic: true, }, { name: "Eq32", argLen: 2, commutative: true, generic: true, }, { name: "Eq64", argLen: 2, commutative: true, generic: true, }, { name: "EqPtr", argLen: 2, commutative: true, generic: true, }, { name: "EqInter", argLen: 2, generic: true, }, { name: "EqSlice", argLen: 2, generic: true, }, { name: "Eq32F", argLen: 2, commutative: true, generic: true, }, { name: "Eq64F", argLen: 2, commutative: true, generic: true, }, { name: "Neq8", argLen: 2, commutative: true, generic: true, }, { name: "Neq16", argLen: 2, commutative: true, generic: true, }, { name: "Neq32", argLen: 2, commutative: true, generic: true, }, { name: "Neq64", argLen: 2, commutative: true, generic: true, }, { name: "NeqPtr", argLen: 2, commutative: true, generic: true, }, { name: "NeqInter", argLen: 2, generic: true, }, { name: "NeqSlice", argLen: 2, generic: true, }, { name: "Neq32F", argLen: 2, commutative: true, generic: true, }, { name: "Neq64F", argLen: 2, commutative: true, generic: true, }, { name: "Less8", argLen: 2, generic: true, }, { name: "Less8U", argLen: 2, generic: true, }, { name: "Less16", argLen: 2, generic: true, }, { name: "Less16U", argLen: 2, generic: true, }, { name: "Less32", argLen: 2, generic: true, }, { name: "Less32U", argLen: 2, generic: true, }, { name: "Less64", argLen: 2, generic: true, }, { name: "Less64U", argLen: 2, generic: true, }, { name: "Less32F", argLen: 2, generic: true, }, { name: "Less64F", argLen: 2, generic: true, }, { name: "Leq8", argLen: 2, generic: true, }, { name: "Leq8U", argLen: 2, generic: true, }, { name: "Leq16", argLen: 2, generic: true, }, { name: "Leq16U", argLen: 2, generic: true, }, { name: "Leq32", argLen: 2, generic: true, }, { name: "Leq32U", argLen: 2, generic: true, }, { name: "Leq64", argLen: 2, generic: true, }, { name: "Leq64U", argLen: 2, generic: true, }, { name: "Leq32F", argLen: 2, generic: true, }, { name: "Leq64F", argLen: 2, generic: true, }, { name: "CondSelect", argLen: 3, generic: true, }, { name: "AndB", argLen: 2, commutative: true, generic: true, }, { name: "OrB", argLen: 2, commutative: true, generic: true, }, { name: "EqB", argLen: 2, commutative: true, generic: true, }, { name: "NeqB", argLen: 2, commutative: true, generic: true, }, { name: "Not", argLen: 1, generic: true, }, { name: "Neg8", argLen: 1, generic: true, }, { name: "Neg16", argLen: 1, generic: true, }, { name: "Neg32", argLen: 1, generic: true, }, { name: "Neg64", argLen: 1, generic: true, }, { name: "Neg32F", argLen: 1, generic: true, }, { name: "Neg64F", argLen: 1, generic: true, }, { name: "Com8", argLen: 1, generic: true, }, { name: "Com16", argLen: 1, generic: true, }, { name: "Com32", argLen: 1, generic: true, }, { name: "Com64", argLen: 1, generic: true, }, { name: "Ctz8", argLen: 1, generic: true, }, { name: "Ctz16", argLen: 1, generic: true, }, { name: "Ctz32", argLen: 1, generic: true, }, { name: "Ctz64", argLen: 1, generic: true, }, { name: "Ctz8NonZero", argLen: 1, generic: true, }, { name: "Ctz16NonZero", argLen: 1, generic: true, }, { name: "Ctz32NonZero", argLen: 1, generic: true, }, { name: "Ctz64NonZero", argLen: 1, generic: true, }, { name: "BitLen8", argLen: 1, generic: true, }, { name: "BitLen16", argLen: 1, generic: true, }, { name: "BitLen32", argLen: 1, generic: true, }, { name: "BitLen64", argLen: 1, generic: true, }, { name: "Bswap32", argLen: 1, generic: true, }, { name: "Bswap64", argLen: 1, generic: true, }, { name: "BitRev8", argLen: 1, generic: true, }, { name: "BitRev16", argLen: 1, generic: true, }, { name: "BitRev32", argLen: 1, generic: true, }, { name: "BitRev64", argLen: 1, generic: true, }, { name: "PopCount8", argLen: 1, generic: true, }, { name: "PopCount16", argLen: 1, generic: true, }, { name: "PopCount32", argLen: 1, generic: true, }, { name: "PopCount64", argLen: 1, generic: true, }, { name: "RotateLeft8", argLen: 2, generic: true, }, { name: "RotateLeft16", argLen: 2, generic: true, }, { name: "RotateLeft32", argLen: 2, generic: true, }, { name: "RotateLeft64", argLen: 2, generic: true, }, { name: "Sqrt", argLen: 1, generic: true, }, { name: "Sqrt32", argLen: 1, generic: true, }, { name: "Floor", argLen: 1, generic: true, }, { name: "Ceil", argLen: 1, generic: true, }, { name: "Trunc", argLen: 1, generic: true, }, { name: "Round", argLen: 1, generic: true, }, { name: "RoundToEven", argLen: 1, generic: true, }, { name: "Abs", argLen: 1, generic: true, }, { name: "Copysign", argLen: 2, generic: true, }, { name: "FMA", argLen: 3, generic: true, }, { name: "Phi", argLen: -1, zeroWidth: true, generic: true, }, { name: "Copy", argLen: 1, generic: true, }, { name: "Convert", argLen: 2, resultInArg0: true, zeroWidth: true, generic: true, }, { name: "ConstBool", auxType: auxBool, argLen: 0, generic: true, }, { name: "ConstString", auxType: auxString, argLen: 0, generic: true, }, { name: "ConstNil", argLen: 0, generic: true, }, { name: "Const8", auxType: auxInt8, argLen: 0, generic: true, }, { name: "Const16", auxType: auxInt16, argLen: 0, generic: true, }, { name: "Const32", auxType: auxInt32, argLen: 0, generic: true, }, { name: "Const64", auxType: auxInt64, argLen: 0, generic: true, }, { name: "Const32F", auxType: auxFloat32, argLen: 0, generic: true, }, { name: "Const64F", auxType: auxFloat64, argLen: 0, generic: true, }, { name: "ConstInterface", argLen: 0, generic: true, }, { name: "ConstSlice", argLen: 0, generic: true, }, { name: "InitMem", argLen: 0, zeroWidth: true, generic: true, }, { name: "Arg", auxType: auxSymOff, argLen: 0, zeroWidth: true, symEffect: SymRead, generic: true, }, { name: "ArgIntReg", auxType: auxNameOffsetInt8, argLen: 0, zeroWidth: true, generic: true, }, { name: "ArgFloatReg", auxType: auxNameOffsetInt8, argLen: 0, zeroWidth: true, generic: true, }, { name: "Addr", auxType: auxSym, argLen: 1, symEffect: SymAddr, generic: true, }, { name: "LocalAddr", auxType: auxSym, argLen: 2, symEffect: SymAddr, generic: true, }, { name: "SP", argLen: 0, zeroWidth: true, generic: true, }, { name: "SB", argLen: 0, zeroWidth: true, generic: true, }, { name: "Load", argLen: 2, generic: true, }, { name: "Dereference", argLen: 2, generic: true, }, { name: "Store", auxType: auxTyp, argLen: 3, generic: true, }, { name: "Move", auxType: auxTypSize, argLen: 3, generic: true, }, { name: "Zero", auxType: auxTypSize, argLen: 2, generic: true, }, { name: "StoreWB", auxType: auxTyp, argLen: 3, generic: true, }, { name: "MoveWB", auxType: auxTypSize, argLen: 3, generic: true, }, { name: "ZeroWB", auxType: auxTypSize, argLen: 2, generic: true, }, { name: "WB", auxType: auxSym, argLen: 3, symEffect: SymNone, generic: true, }, { name: "HasCPUFeature", auxType: auxSym, argLen: 0, symEffect: SymNone, generic: true, }, { name: "PanicBounds", auxType: auxInt64, argLen: 3, call: true, generic: true, }, { name: "PanicExtend", auxType: auxInt64, argLen: 4, call: true, generic: true, }, { name: "ClosureCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "StaticCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "InterCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "TailCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "ClosureLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "StaticLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "InterLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "TailLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "SignExt8to16", argLen: 1, generic: true, }, { name: "SignExt8to32", argLen: 1, generic: true, }, { name: "SignExt8to64", argLen: 1, generic: true, }, { name: "SignExt16to32", argLen: 1, generic: true, }, { name: "SignExt16to64", argLen: 1, generic: true, }, { name: "SignExt32to64", argLen: 1, generic: true, }, { name: "ZeroExt8to16", argLen: 1, generic: true, }, { name: "ZeroExt8to32", argLen: 1, generic: true, }, { name: "ZeroExt8to64", argLen: 1, generic: true, }, { name: "ZeroExt16to32", argLen: 1, generic: true, }, { name: "ZeroExt16to64", argLen: 1, generic: true, }, { name: "ZeroExt32to64", argLen: 1, generic: true, }, { name: "Trunc16to8", argLen: 1, generic: true, }, { name: "Trunc32to8", argLen: 1, generic: true, }, { name: "Trunc32to16", argLen: 1, generic: true, }, { name: "Trunc64to8", argLen: 1, generic: true, }, { name: "Trunc64to16", argLen: 1, generic: true, }, { name: "Trunc64to32", argLen: 1, generic: true, }, { name: "Cvt32to32F", argLen: 1, generic: true, }, { name: "Cvt32to64F", argLen: 1, generic: true, }, { name: "Cvt64to32F", argLen: 1, generic: true, }, { name: "Cvt64to64F", argLen: 1, generic: true, }, { name: "Cvt32Fto32", argLen: 1, generic: true, }, { name: "Cvt32Fto64", argLen: 1, generic: true, }, { name: "Cvt64Fto32", argLen: 1, generic: true, }, { name: "Cvt64Fto64", argLen: 1, generic: true, }, { name: "Cvt32Fto64F", argLen: 1, generic: true, }, { name: "Cvt64Fto32F", argLen: 1, generic: true, }, { name: "CvtBoolToUint8", argLen: 1, generic: true, }, { name: "Round32F", argLen: 1, generic: true, }, { name: "Round64F", argLen: 1, generic: true, }, { name: "IsNonNil", argLen: 1, generic: true, }, { name: "IsInBounds", argLen: 2, generic: true, }, { name: "IsSliceInBounds", argLen: 2, generic: true, }, { name: "NilCheck", argLen: 2, generic: true, }, { name: "GetG", argLen: 1, zeroWidth: true, generic: true, }, { name: "GetClosurePtr", argLen: 0, generic: true, }, { name: "GetCallerPC", argLen: 0, generic: true, }, { name: "GetCallerSP", argLen: 0, generic: true, }, { name: "PtrIndex", argLen: 2, generic: true, }, { name: "OffPtr", auxType: auxInt64, argLen: 1, generic: true, }, { name: "SliceMake", argLen: 3, generic: true, }, { name: "SlicePtr", argLen: 1, generic: true, }, { name: "SliceLen", argLen: 1, generic: true, }, { name: "SliceCap", argLen: 1, generic: true, }, { name: "SlicePtrUnchecked", argLen: 1, generic: true, }, { name: "ComplexMake", argLen: 2, generic: true, }, { name: "ComplexReal", argLen: 1, generic: true, }, { name: "ComplexImag", argLen: 1, generic: true, }, { name: "StringMake", argLen: 2, generic: true, }, { name: "StringPtr", argLen: 1, generic: true, }, { name: "StringLen", argLen: 1, generic: true, }, { name: "IMake", argLen: 2, generic: true, }, { name: "ITab", argLen: 1, generic: true, }, { name: "IData", argLen: 1, generic: true, }, { name: "StructMake0", argLen: 0, generic: true, }, { name: "StructMake1", argLen: 1, generic: true, }, { name: "StructMake2", argLen: 2, generic: true, }, { name: "StructMake3", argLen: 3, generic: true, }, { name: "StructMake4", argLen: 4, generic: true, }, { name: "StructSelect", auxType: auxInt64, argLen: 1, generic: true, }, { name: "ArrayMake0", argLen: 0, generic: true, }, { name: "ArrayMake1", argLen: 1, generic: true, }, { name: "ArraySelect", auxType: auxInt64, argLen: 1, generic: true, }, { name: "StoreReg", argLen: 1, generic: true, }, { name: "LoadReg", argLen: 1, generic: true, }, { name: "FwdRef", auxType: auxSym, argLen: 0, symEffect: SymNone, generic: true, }, { name: "Unknown", argLen: 0, generic: true, }, { name: "VarDef", auxType: auxSym, argLen: 1, zeroWidth: true, symEffect: SymNone, generic: true, }, { name: "VarKill", auxType: auxSym, argLen: 1, symEffect: SymNone, generic: true, }, { name: "VarLive", auxType: auxSym, argLen: 1, zeroWidth: true, symEffect: SymRead, generic: true, }, { name: "KeepAlive", argLen: 2, zeroWidth: true, generic: true, }, { name: "InlMark", auxType: auxInt32, argLen: 1, generic: true, }, { name: "Int64Make", argLen: 2, generic: true, }, { name: "Int64Hi", argLen: 1, generic: true, }, { name: "Int64Lo", argLen: 1, generic: true, }, { name: "Add32carry", argLen: 2, commutative: true, generic: true, }, { name: "Add32withcarry", argLen: 3, commutative: true, generic: true, }, { name: "Sub32carry", argLen: 2, generic: true, }, { name: "Sub32withcarry", argLen: 3, generic: true, }, { name: "Add64carry", argLen: 3, commutative: true, generic: true, }, { name: "Sub64borrow", argLen: 3, generic: true, }, { name: "Signmask", argLen: 1, generic: true, }, { name: "Zeromask", argLen: 1, generic: true, }, { name: "Slicemask", argLen: 1, generic: true, }, { name: "SpectreIndex", argLen: 2, generic: true, }, { name: "SpectreSliceIndex", argLen: 2, generic: true, }, { name: "Cvt32Uto32F", argLen: 1, generic: true, }, { name: "Cvt32Uto64F", argLen: 1, generic: true, }, { name: "Cvt32Fto32U", argLen: 1, generic: true, }, { name: "Cvt64Fto32U", argLen: 1, generic: true, }, { name: "Cvt64Uto32F", argLen: 1, generic: true, }, { name: "Cvt64Uto64F", argLen: 1, generic: true, }, { name: "Cvt32Fto64U", argLen: 1, generic: true, }, { name: "Cvt64Fto64U", argLen: 1, generic: true, }, { name: "Select0", argLen: 1, zeroWidth: true, generic: true, }, { name: "Select1", argLen: 1, zeroWidth: true, generic: true, }, { name: "SelectN", auxType: auxInt64, argLen: 1, generic: true, }, { name: "SelectNAddr", auxType: auxInt64, argLen: 1, generic: true, }, { name: "MakeResult", argLen: -1, generic: true, }, { name: "AtomicLoad8", argLen: 2, generic: true, }, { name: "AtomicLoad32", argLen: 2, generic: true, }, { name: "AtomicLoad64", argLen: 2, generic: true, }, { name: "AtomicLoadPtr", argLen: 2, generic: true, }, { name: "AtomicLoadAcq32", argLen: 2, generic: true, }, { name: "AtomicLoadAcq64", argLen: 2, generic: true, }, { name: "AtomicStore8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStorePtrNoWB", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStoreRel32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStoreRel64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap32", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap64", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwapRel32", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicAnd8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd64Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange64Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap32Variant", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap64Variant", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicAnd8Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr8Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "PubBarrier", argLen: 1, hasSideEffects: true, generic: true, }, { name: "Clobber", auxType: auxSymOff, argLen: 0, symEffect: SymNone, generic: true, }, { name: "ClobberReg", argLen: 0, generic: true, }, { name: "PrefetchCache", argLen: 2, hasSideEffects: true, generic: true, }, { name: "PrefetchCacheStreamed", argLen: 2, hasSideEffects: true, generic: true, }, } func (o Op) Asm() obj.As { return opcodeTable[o].asm } func (o Op) Scale() int16 { return int16(opcodeTable[o].scale) } func (o Op) String() string { return opcodeTable[o].name } func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } func (o Op) IsCall() bool { return opcodeTable[o].call } func (o Op) IsTailCall() bool { return opcodeTable[o].tailCall } func (o Op) HasSideEffects() bool { return opcodeTable[o].hasSideEffects } func (o Op) UnsafePoint() bool { return opcodeTable[o].unsafePoint } func (o Op) ResultInArg0() bool { return opcodeTable[o].resultInArg0 } var registers386 = [...]Register{ {0, x86.REG_AX, 0, "AX"}, {1, x86.REG_CX, 1, "CX"}, {2, x86.REG_DX, 2, "DX"}, {3, x86.REG_BX, 3, "BX"}, {4, x86.REGSP, -1, "SP"}, {5, x86.REG_BP, 4, "BP"}, {6, x86.REG_SI, 5, "SI"}, {7, x86.REG_DI, 6, "DI"}, {8, x86.REG_X0, -1, "X0"}, {9, x86.REG_X1, -1, "X1"}, {10, x86.REG_X2, -1, "X2"}, {11, x86.REG_X3, -1, "X3"}, {12, x86.REG_X4, -1, "X4"}, {13, x86.REG_X5, -1, "X5"}, {14, x86.REG_X6, -1, "X6"}, {15, x86.REG_X7, -1, "X7"}, {16, 0, -1, "SB"}, } var paramIntReg386 = []int8(nil) var paramFloatReg386 = []int8(nil) var gpRegMask386 = regMask(239) var fpRegMask386 = regMask(65280) var specialRegMask386 = regMask(0) var framepointerReg386 = int8(5) var linkReg386 = int8(-1) var registersAMD64 = [...]Register{ {0, x86.REG_AX, 0, "AX"}, {1, x86.REG_CX, 1, "CX"}, {2, x86.REG_DX, 2, "DX"}, {3, x86.REG_BX, 3, "BX"}, {4, x86.REGSP, -1, "SP"}, {5, x86.REG_BP, 4, "BP"}, {6, x86.REG_SI, 5, "SI"}, {7, x86.REG_DI, 6, "DI"}, {8, x86.REG_R8, 7, "R8"}, {9, x86.REG_R9, 8, "R9"}, {10, x86.REG_R10, 9, "R10"}, {11, x86.REG_R11, 10, "R11"}, {12, x86.REG_R12, 11, "R12"}, {13, x86.REG_R13, 12, "R13"}, {14, x86.REGG, -1, "g"}, {15, x86.REG_R15, 13, "R15"}, {16, x86.REG_X0, -1, "X0"}, {17, x86.REG_X1, -1, "X1"}, {18, x86.REG_X2, -1, "X2"}, {19, x86.REG_X3, -1, "X3"}, {20, x86.REG_X4, -1, "X4"}, {21, x86.REG_X5, -1, "X5"}, {22, x86.REG_X6, -1, "X6"}, {23, x86.REG_X7, -1, "X7"}, {24, x86.REG_X8, -1, "X8"}, {25, x86.REG_X9, -1, "X9"}, {26, x86.REG_X10, -1, "X10"}, {27, x86.REG_X11, -1, "X11"}, {28, x86.REG_X12, -1, "X12"}, {29, x86.REG_X13, -1, "X13"}, {30, x86.REG_X14, -1, "X14"}, {31, x86.REG_X15, -1, "X15"}, {32, 0, -1, "SB"}, } var paramIntRegAMD64 = []int8{0, 3, 1, 7, 6, 8, 9, 10, 11} var paramFloatRegAMD64 = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30} var gpRegMaskAMD64 = regMask(49135) var fpRegMaskAMD64 = regMask(2147418112) var specialRegMaskAMD64 = regMask(2147483648) var framepointerRegAMD64 = int8(5) var linkRegAMD64 = int8(-1) var registersARM = [...]Register{ {0, arm.REG_R0, 0, "R0"}, {1, arm.REG_R1, 1, "R1"}, {2, arm.REG_R2, 2, "R2"}, {3, arm.REG_R3, 3, "R3"}, {4, arm.REG_R4, 4, "R4"}, {5, arm.REG_R5, 5, "R5"}, {6, arm.REG_R6, 6, "R6"}, {7, arm.REG_R7, 7, "R7"}, {8, arm.REG_R8, 8, "R8"}, {9, arm.REG_R9, 9, "R9"}, {10, arm.REGG, -1, "g"}, {11, arm.REG_R11, -1, "R11"}, {12, arm.REG_R12, 10, "R12"}, {13, arm.REGSP, -1, "SP"}, {14, arm.REG_R14, 11, "R14"}, {15, arm.REG_R15, -1, "R15"}, {16, arm.REG_F0, -1, "F0"}, {17, arm.REG_F1, -1, "F1"}, {18, arm.REG_F2, -1, "F2"}, {19, arm.REG_F3, -1, "F3"}, {20, arm.REG_F4, -1, "F4"}, {21, arm.REG_F5, -1, "F5"}, {22, arm.REG_F6, -1, "F6"}, {23, arm.REG_F7, -1, "F7"}, {24, arm.REG_F8, -1, "F8"}, {25, arm.REG_F9, -1, "F9"}, {26, arm.REG_F10, -1, "F10"}, {27, arm.REG_F11, -1, "F11"}, {28, arm.REG_F12, -1, "F12"}, {29, arm.REG_F13, -1, "F13"}, {30, arm.REG_F14, -1, "F14"}, {31, arm.REG_F15, -1, "F15"}, {32, 0, -1, "SB"}, } var paramIntRegARM = []int8(nil) var paramFloatRegARM = []int8(nil) var gpRegMaskARM = regMask(21503) var fpRegMaskARM = regMask(4294901760) var specialRegMaskARM = regMask(0) var framepointerRegARM = int8(-1) var linkRegARM = int8(14) var registersARM64 = [...]Register{ {0, arm64.REG_R0, 0, "R0"}, {1, arm64.REG_R1, 1, "R1"}, {2, arm64.REG_R2, 2, "R2"}, {3, arm64.REG_R3, 3, "R3"}, {4, arm64.REG_R4, 4, "R4"}, {5, arm64.REG_R5, 5, "R5"}, {6, arm64.REG_R6, 6, "R6"}, {7, arm64.REG_R7, 7, "R7"}, {8, arm64.REG_R8, 8, "R8"}, {9, arm64.REG_R9, 9, "R9"}, {10, arm64.REG_R10, 10, "R10"}, {11, arm64.REG_R11, 11, "R11"}, {12, arm64.REG_R12, 12, "R12"}, {13, arm64.REG_R13, 13, "R13"}, {14, arm64.REG_R14, 14, "R14"}, {15, arm64.REG_R15, 15, "R15"}, {16, arm64.REG_R16, 16, "R16"}, {17, arm64.REG_R17, 17, "R17"}, {18, arm64.REG_R18, -1, "R18"}, {19, arm64.REG_R19, 18, "R19"}, {20, arm64.REG_R20, 19, "R20"}, {21, arm64.REG_R21, 20, "R21"}, {22, arm64.REG_R22, 21, "R22"}, {23, arm64.REG_R23, 22, "R23"}, {24, arm64.REG_R24, 23, "R24"}, {25, arm64.REG_R25, 24, "R25"}, {26, arm64.REG_R26, 25, "R26"}, {27, arm64.REGG, -1, "g"}, {28, arm64.REG_R29, -1, "R29"}, {29, arm64.REG_R30, 26, "R30"}, {30, arm64.REGSP, -1, "SP"}, {31, arm64.REG_F0, -1, "F0"}, {32, arm64.REG_F1, -1, "F1"}, {33, arm64.REG_F2, -1, "F2"}, {34, arm64.REG_F3, -1, "F3"}, {35, arm64.REG_F4, -1, "F4"}, {36, arm64.REG_F5, -1, "F5"}, {37, arm64.REG_F6, -1, "F6"}, {38, arm64.REG_F7, -1, "F7"}, {39, arm64.REG_F8, -1, "F8"}, {40, arm64.REG_F9, -1, "F9"}, {41, arm64.REG_F10, -1, "F10"}, {42, arm64.REG_F11, -1, "F11"}, {43, arm64.REG_F12, -1, "F12"}, {44, arm64.REG_F13, -1, "F13"}, {45, arm64.REG_F14, -1, "F14"}, {46, arm64.REG_F15, -1, "F15"}, {47, arm64.REG_F16, -1, "F16"}, {48, arm64.REG_F17, -1, "F17"}, {49, arm64.REG_F18, -1, "F18"}, {50, arm64.REG_F19, -1, "F19"}, {51, arm64.REG_F20, -1, "F20"}, {52, arm64.REG_F21, -1, "F21"}, {53, arm64.REG_F22, -1, "F22"}, {54, arm64.REG_F23, -1, "F23"}, {55, arm64.REG_F24, -1, "F24"}, {56, arm64.REG_F25, -1, "F25"}, {57, arm64.REG_F26, -1, "F26"}, {58, arm64.REG_F27, -1, "F27"}, {59, arm64.REG_F28, -1, "F28"}, {60, arm64.REG_F29, -1, "F29"}, {61, arm64.REG_F30, -1, "F30"}, {62, arm64.REG_F31, -1, "F31"}, {63, 0, -1, "SB"}, } var paramIntRegARM64 = []int8{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} var paramFloatRegARM64 = []int8{31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46} var gpRegMaskARM64 = regMask(670826495) var fpRegMaskARM64 = regMask(9223372034707292160) var specialRegMaskARM64 = regMask(0) var framepointerRegARM64 = int8(-1) var linkRegARM64 = int8(29) var registersMIPS = [...]Register{ {0, mips.REG_R0, -1, "R0"}, {1, mips.REG_R1, 0, "R1"}, {2, mips.REG_R2, 1, "R2"}, {3, mips.REG_R3, 2, "R3"}, {4, mips.REG_R4, 3, "R4"}, {5, mips.REG_R5, 4, "R5"}, {6, mips.REG_R6, 5, "R6"}, {7, mips.REG_R7, 6, "R7"}, {8, mips.REG_R8, 7, "R8"}, {9, mips.REG_R9, 8, "R9"}, {10, mips.REG_R10, 9, "R10"}, {11, mips.REG_R11, 10, "R11"}, {12, mips.REG_R12, 11, "R12"}, {13, mips.REG_R13, 12, "R13"}, {14, mips.REG_R14, 13, "R14"}, {15, mips.REG_R15, 14, "R15"}, {16, mips.REG_R16, 15, "R16"}, {17, mips.REG_R17, 16, "R17"}, {18, mips.REG_R18, 17, "R18"}, {19, mips.REG_R19, 18, "R19"}, {20, mips.REG_R20, 19, "R20"}, {21, mips.REG_R21, 20, "R21"}, {22, mips.REG_R22, 21, "R22"}, {23, mips.REG_R24, 22, "R24"}, {24, mips.REG_R25, 23, "R25"}, {25, mips.REG_R28, 24, "R28"}, {26, mips.REGSP, -1, "SP"}, {27, mips.REGG, -1, "g"}, {28, mips.REG_R31, 25, "R31"}, {29, mips.REG_F0, -1, "F0"}, {30, mips.REG_F2, -1, "F2"}, {31, mips.REG_F4, -1, "F4"}, {32, mips.REG_F6, -1, "F6"}, {33, mips.REG_F8, -1, "F8"}, {34, mips.REG_F10, -1, "F10"}, {35, mips.REG_F12, -1, "F12"}, {36, mips.REG_F14, -1, "F14"}, {37, mips.REG_F16, -1, "F16"}, {38, mips.REG_F18, -1, "F18"}, {39, mips.REG_F20, -1, "F20"}, {40, mips.REG_F22, -1, "F22"}, {41, mips.REG_F24, -1, "F24"}, {42, mips.REG_F26, -1, "F26"}, {43, mips.REG_F28, -1, "F28"}, {44, mips.REG_F30, -1, "F30"}, {45, mips.REG_HI, -1, "HI"}, {46, mips.REG_LO, -1, "LO"}, {47, 0, -1, "SB"}, } var paramIntRegMIPS = []int8(nil) var paramFloatRegMIPS = []int8(nil) var gpRegMaskMIPS = regMask(335544318) var fpRegMaskMIPS = regMask(35183835217920) var specialRegMaskMIPS = regMask(105553116266496) var framepointerRegMIPS = int8(-1) var linkRegMIPS = int8(28) var registersMIPS64 = [...]Register{ {0, mips.REG_R0, -1, "R0"}, {1, mips.REG_R1, 0, "R1"}, {2, mips.REG_R2, 1, "R2"}, {3, mips.REG_R3, 2, "R3"}, {4, mips.REG_R4, 3, "R4"}, {5, mips.REG_R5, 4, "R5"}, {6, mips.REG_R6, 5, "R6"}, {7, mips.REG_R7, 6, "R7"}, {8, mips.REG_R8, 7, "R8"}, {9, mips.REG_R9, 8, "R9"}, {10, mips.REG_R10, 9, "R10"}, {11, mips.REG_R11, 10, "R11"}, {12, mips.REG_R12, 11, "R12"}, {13, mips.REG_R13, 12, "R13"}, {14, mips.REG_R14, 13, "R14"}, {15, mips.REG_R15, 14, "R15"}, {16, mips.REG_R16, 15, "R16"}, {17, mips.REG_R17, 16, "R17"}, {18, mips.REG_R18, 17, "R18"}, {19, mips.REG_R19, 18, "R19"}, {20, mips.REG_R20, 19, "R20"}, {21, mips.REG_R21, 20, "R21"}, {22, mips.REG_R22, 21, "R22"}, {23, mips.REG_R24, 22, "R24"}, {24, mips.REG_R25, 23, "R25"}, {25, mips.REGSP, -1, "SP"}, {26, mips.REGG, -1, "g"}, {27, mips.REG_R31, 24, "R31"}, {28, mips.REG_F0, -1, "F0"}, {29, mips.REG_F1, -1, "F1"}, {30, mips.REG_F2, -1, "F2"}, {31, mips.REG_F3, -1, "F3"}, {32, mips.REG_F4, -1, "F4"}, {33, mips.REG_F5, -1, "F5"}, {34, mips.REG_F6, -1, "F6"}, {35, mips.REG_F7, -1, "F7"}, {36, mips.REG_F8, -1, "F8"}, {37, mips.REG_F9, -1, "F9"}, {38, mips.REG_F10, -1, "F10"}, {39, mips.REG_F11, -1, "F11"}, {40, mips.REG_F12, -1, "F12"}, {41, mips.REG_F13, -1, "F13"}, {42, mips.REG_F14, -1, "F14"}, {43, mips.REG_F15, -1, "F15"}, {44, mips.REG_F16, -1, "F16"}, {45, mips.REG_F17, -1, "F17"}, {46, mips.REG_F18, -1, "F18"}, {47, mips.REG_F19, -1, "F19"}, {48, mips.REG_F20, -1, "F20"}, {49, mips.REG_F21, -1, "F21"}, {50, mips.REG_F22, -1, "F22"}, {51, mips.REG_F23, -1, "F23"}, {52, mips.REG_F24, -1, "F24"}, {53, mips.REG_F25, -1, "F25"}, {54, mips.REG_F26, -1, "F26"}, {55, mips.REG_F27, -1, "F27"}, {56, mips.REG_F28, -1, "F28"}, {57, mips.REG_F29, -1, "F29"}, {58, mips.REG_F30, -1, "F30"}, {59, mips.REG_F31, -1, "F31"}, {60, mips.REG_HI, -1, "HI"}, {61, mips.REG_LO, -1, "LO"}, {62, 0, -1, "SB"}, } var paramIntRegMIPS64 = []int8(nil) var paramFloatRegMIPS64 = []int8(nil) var gpRegMaskMIPS64 = regMask(167772158) var fpRegMaskMIPS64 = regMask(1152921504338411520) var specialRegMaskMIPS64 = regMask(3458764513820540928) var framepointerRegMIPS64 = int8(-1) var linkRegMIPS64 = int8(27) var registersPPC64 = [...]Register{ {0, ppc64.REG_R0, -1, "R0"}, {1, ppc64.REGSP, -1, "SP"}, {2, 0, -1, "SB"}, {3, ppc64.REG_R3, 0, "R3"}, {4, ppc64.REG_R4, 1, "R4"}, {5, ppc64.REG_R5, 2, "R5"}, {6, ppc64.REG_R6, 3, "R6"}, {7, ppc64.REG_R7, 4, "R7"}, {8, ppc64.REG_R8, 5, "R8"}, {9, ppc64.REG_R9, 6, "R9"}, {10, ppc64.REG_R10, 7, "R10"}, {11, ppc64.REG_R11, 8, "R11"}, {12, ppc64.REG_R12, 9, "R12"}, {13, ppc64.REG_R13, -1, "R13"}, {14, ppc64.REG_R14, 10, "R14"}, {15, ppc64.REG_R15, 11, "R15"}, {16, ppc64.REG_R16, 12, "R16"}, {17, ppc64.REG_R17, 13, "R17"}, {18, ppc64.REG_R18, 14, "R18"}, {19, ppc64.REG_R19, 15, "R19"}, {20, ppc64.REG_R20, 16, "R20"}, {21, ppc64.REG_R21, 17, "R21"}, {22, ppc64.REG_R22, 18, "R22"}, {23, ppc64.REG_R23, 19, "R23"}, {24, ppc64.REG_R24, 20, "R24"}, {25, ppc64.REG_R25, 21, "R25"}, {26, ppc64.REG_R26, 22, "R26"}, {27, ppc64.REG_R27, 23, "R27"}, {28, ppc64.REG_R28, 24, "R28"}, {29, ppc64.REG_R29, 25, "R29"}, {30, ppc64.REGG, -1, "g"}, {31, ppc64.REG_R31, -1, "R31"}, {32, ppc64.REG_F0, -1, "F0"}, {33, ppc64.REG_F1, -1, "F1"}, {34, ppc64.REG_F2, -1, "F2"}, {35, ppc64.REG_F3, -1, "F3"}, {36, ppc64.REG_F4, -1, "F4"}, {37, ppc64.REG_F5, -1, "F5"}, {38, ppc64.REG_F6, -1, "F6"}, {39, ppc64.REG_F7, -1, "F7"}, {40, ppc64.REG_F8, -1, "F8"}, {41, ppc64.REG_F9, -1, "F9"}, {42, ppc64.REG_F10, -1, "F10"}, {43, ppc64.REG_F11, -1, "F11"}, {44, ppc64.REG_F12, -1, "F12"}, {45, ppc64.REG_F13, -1, "F13"}, {46, ppc64.REG_F14, -1, "F14"}, {47, ppc64.REG_F15, -1, "F15"}, {48, ppc64.REG_F16, -1, "F16"}, {49, ppc64.REG_F17, -1, "F17"}, {50, ppc64.REG_F18, -1, "F18"}, {51, ppc64.REG_F19, -1, "F19"}, {52, ppc64.REG_F20, -1, "F20"}, {53, ppc64.REG_F21, -1, "F21"}, {54, ppc64.REG_F22, -1, "F22"}, {55, ppc64.REG_F23, -1, "F23"}, {56, ppc64.REG_F24, -1, "F24"}, {57, ppc64.REG_F25, -1, "F25"}, {58, ppc64.REG_F26, -1, "F26"}, {59, ppc64.REG_F27, -1, "F27"}, {60, ppc64.REG_F28, -1, "F28"}, {61, ppc64.REG_F29, -1, "F29"}, {62, ppc64.REG_F30, -1, "F30"}, {63, ppc64.REG_XER, -1, "XER"}, } var paramIntRegPPC64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 16, 17} var paramFloatRegPPC64 = []int8{33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44} var gpRegMaskPPC64 = regMask(1073733624) var fpRegMaskPPC64 = regMask(9223372032559808512) var specialRegMaskPPC64 = regMask(9223372036854775808) var framepointerRegPPC64 = int8(-1) var linkRegPPC64 = int8(-1) var registersRISCV64 = [...]Register{ {0, riscv.REG_X0, -1, "X0"}, {1, riscv.REGSP, -1, "SP"}, {2, riscv.REG_X3, -1, "X3"}, {3, riscv.REG_X4, -1, "X4"}, {4, riscv.REG_X5, 0, "X5"}, {5, riscv.REG_X6, 1, "X6"}, {6, riscv.REG_X7, 2, "X7"}, {7, riscv.REG_X8, 3, "X8"}, {8, riscv.REG_X9, 4, "X9"}, {9, riscv.REG_X10, 5, "X10"}, {10, riscv.REG_X11, 6, "X11"}, {11, riscv.REG_X12, 7, "X12"}, {12, riscv.REG_X13, 8, "X13"}, {13, riscv.REG_X14, 9, "X14"}, {14, riscv.REG_X15, 10, "X15"}, {15, riscv.REG_X16, 11, "X16"}, {16, riscv.REG_X17, 12, "X17"}, {17, riscv.REG_X18, 13, "X18"}, {18, riscv.REG_X19, 14, "X19"}, {19, riscv.REG_X20, 15, "X20"}, {20, riscv.REG_X21, 16, "X21"}, {21, riscv.REG_X22, 17, "X22"}, {22, riscv.REG_X23, 18, "X23"}, {23, riscv.REG_X24, 19, "X24"}, {24, riscv.REG_X25, 20, "X25"}, {25, riscv.REG_X26, 21, "X26"}, {26, riscv.REGG, -1, "g"}, {27, riscv.REG_X28, 22, "X28"}, {28, riscv.REG_X29, 23, "X29"}, {29, riscv.REG_X30, 24, "X30"}, {30, riscv.REG_X31, -1, "X31"}, {31, riscv.REG_F0, -1, "F0"}, {32, riscv.REG_F1, -1, "F1"}, {33, riscv.REG_F2, -1, "F2"}, {34, riscv.REG_F3, -1, "F3"}, {35, riscv.REG_F4, -1, "F4"}, {36, riscv.REG_F5, -1, "F5"}, {37, riscv.REG_F6, -1, "F6"}, {38, riscv.REG_F7, -1, "F7"}, {39, riscv.REG_F8, -1, "F8"}, {40, riscv.REG_F9, -1, "F9"}, {41, riscv.REG_F10, -1, "F10"}, {42, riscv.REG_F11, -1, "F11"}, {43, riscv.REG_F12, -1, "F12"}, {44, riscv.REG_F13, -1, "F13"}, {45, riscv.REG_F14, -1, "F14"}, {46, riscv.REG_F15, -1, "F15"}, {47, riscv.REG_F16, -1, "F16"}, {48, riscv.REG_F17, -1, "F17"}, {49, riscv.REG_F18, -1, "F18"}, {50, riscv.REG_F19, -1, "F19"}, {51, riscv.REG_F20, -1, "F20"}, {52, riscv.REG_F21, -1, "F21"}, {53, riscv.REG_F22, -1, "F22"}, {54, riscv.REG_F23, -1, "F23"}, {55, riscv.REG_F24, -1, "F24"}, {56, riscv.REG_F25, -1, "F25"}, {57, riscv.REG_F26, -1, "F26"}, {58, riscv.REG_F27, -1, "F27"}, {59, riscv.REG_F28, -1, "F28"}, {60, riscv.REG_F29, -1, "F29"}, {61, riscv.REG_F30, -1, "F30"}, {62, riscv.REG_F31, -1, "F31"}, {63, 0, -1, "SB"}, } var paramIntRegRISCV64 = []int8{9, 10, 11, 12, 13, 14, 15, 16, 7, 8, 17, 18, 19, 20, 21, 22} var paramFloatRegRISCV64 = []int8{41, 42, 43, 44, 45, 46, 47, 48, 39, 40, 49, 50, 51, 52, 53, 54} var gpRegMaskRISCV64 = regMask(1006632944) var fpRegMaskRISCV64 = regMask(9223372034707292160) var specialRegMaskRISCV64 = regMask(0) var framepointerRegRISCV64 = int8(-1) var linkRegRISCV64 = int8(0) var registersS390X = [...]Register{ {0, s390x.REG_R0, 0, "R0"}, {1, s390x.REG_R1, 1, "R1"}, {2, s390x.REG_R2, 2, "R2"}, {3, s390x.REG_R3, 3, "R3"}, {4, s390x.REG_R4, 4, "R4"}, {5, s390x.REG_R5, 5, "R5"}, {6, s390x.REG_R6, 6, "R6"}, {7, s390x.REG_R7, 7, "R7"}, {8, s390x.REG_R8, 8, "R8"}, {9, s390x.REG_R9, 9, "R9"}, {10, s390x.REG_R10, -1, "R10"}, {11, s390x.REG_R11, 10, "R11"}, {12, s390x.REG_R12, 11, "R12"}, {13, s390x.REGG, -1, "g"}, {14, s390x.REG_R14, 12, "R14"}, {15, s390x.REGSP, -1, "SP"}, {16, s390x.REG_F0, -1, "F0"}, {17, s390x.REG_F1, -1, "F1"}, {18, s390x.REG_F2, -1, "F2"}, {19, s390x.REG_F3, -1, "F3"}, {20, s390x.REG_F4, -1, "F4"}, {21, s390x.REG_F5, -1, "F5"}, {22, s390x.REG_F6, -1, "F6"}, {23, s390x.REG_F7, -1, "F7"}, {24, s390x.REG_F8, -1, "F8"}, {25, s390x.REG_F9, -1, "F9"}, {26, s390x.REG_F10, -1, "F10"}, {27, s390x.REG_F11, -1, "F11"}, {28, s390x.REG_F12, -1, "F12"}, {29, s390x.REG_F13, -1, "F13"}, {30, s390x.REG_F14, -1, "F14"}, {31, s390x.REG_F15, -1, "F15"}, {32, 0, -1, "SB"}, } var paramIntRegS390X = []int8(nil) var paramFloatRegS390X = []int8(nil) var gpRegMaskS390X = regMask(23551) var fpRegMaskS390X = regMask(4294901760) var specialRegMaskS390X = regMask(0) var framepointerRegS390X = int8(-1) var linkRegS390X = int8(14) var registersWasm = [...]Register{ {0, wasm.REG_R0, 0, "R0"}, {1, wasm.REG_R1, 1, "R1"}, {2, wasm.REG_R2, 2, "R2"}, {3, wasm.REG_R3, 3, "R3"}, {4, wasm.REG_R4, 4, "R4"}, {5, wasm.REG_R5, 5, "R5"}, {6, wasm.REG_R6, 6, "R6"}, {7, wasm.REG_R7, 7, "R7"}, {8, wasm.REG_R8, 8, "R8"}, {9, wasm.REG_R9, 9, "R9"}, {10, wasm.REG_R10, 10, "R10"}, {11, wasm.REG_R11, 11, "R11"}, {12, wasm.REG_R12, 12, "R12"}, {13, wasm.REG_R13, 13, "R13"}, {14, wasm.REG_R14, 14, "R14"}, {15, wasm.REG_R15, 15, "R15"}, {16, wasm.REG_F0, -1, "F0"}, {17, wasm.REG_F1, -1, "F1"}, {18, wasm.REG_F2, -1, "F2"}, {19, wasm.REG_F3, -1, "F3"}, {20, wasm.REG_F4, -1, "F4"}, {21, wasm.REG_F5, -1, "F5"}, {22, wasm.REG_F6, -1, "F6"}, {23, wasm.REG_F7, -1, "F7"}, {24, wasm.REG_F8, -1, "F8"}, {25, wasm.REG_F9, -1, "F9"}, {26, wasm.REG_F10, -1, "F10"}, {27, wasm.REG_F11, -1, "F11"}, {28, wasm.REG_F12, -1, "F12"}, {29, wasm.REG_F13, -1, "F13"}, {30, wasm.REG_F14, -1, "F14"}, {31, wasm.REG_F15, -1, "F15"}, {32, wasm.REG_F16, -1, "F16"}, {33, wasm.REG_F17, -1, "F17"}, {34, wasm.REG_F18, -1, "F18"}, {35, wasm.REG_F19, -1, "F19"}, {36, wasm.REG_F20, -1, "F20"}, {37, wasm.REG_F21, -1, "F21"}, {38, wasm.REG_F22, -1, "F22"}, {39, wasm.REG_F23, -1, "F23"}, {40, wasm.REG_F24, -1, "F24"}, {41, wasm.REG_F25, -1, "F25"}, {42, wasm.REG_F26, -1, "F26"}, {43, wasm.REG_F27, -1, "F27"}, {44, wasm.REG_F28, -1, "F28"}, {45, wasm.REG_F29, -1, "F29"}, {46, wasm.REG_F30, -1, "F30"}, {47, wasm.REG_F31, -1, "F31"}, {48, wasm.REGSP, -1, "SP"}, {49, wasm.REGG, -1, "g"}, {50, 0, -1, "SB"}, } var paramIntRegWasm = []int8(nil) var paramFloatRegWasm = []int8(nil) var gpRegMaskWasm = regMask(65535) var fpRegMaskWasm = regMask(281474976645120) var fp32RegMaskWasm = regMask(4294901760) var fp64RegMaskWasm = regMask(281470681743360) var specialRegMaskWasm = regMask(0) var framepointerRegWasm = int8(-1) var linkRegWasm = int8(-1) -- y -- // Code generated from gen/*Ops.go; DO NOT EDIT. package ssa import ( "cmd/internal/obj" "cmd/internal/obj/arm" "cmd/internal/obj/arm64" "cmd/internal/obj/loong64" "cmd/internal/obj/mips" "cmd/internal/obj/ppc64" "cmd/internal/obj/riscv" "cmd/internal/obj/s390x" "cmd/internal/obj/wasm" "cmd/internal/obj/x86" ) const ( BlockInvalid BlockKind = iota Block386EQ Block386NE Block386LT Block386LE Block386GT Block386GE Block386OS Block386OC Block386ULT Block386ULE Block386UGT Block386UGE Block386EQF Block386NEF Block386ORD Block386NAN BlockAMD64EQ BlockAMD64NE BlockAMD64LT BlockAMD64LE BlockAMD64GT BlockAMD64GE BlockAMD64OS BlockAMD64OC BlockAMD64ULT BlockAMD64ULE BlockAMD64UGT BlockAMD64UGE BlockAMD64EQF BlockAMD64NEF BlockAMD64ORD BlockAMD64NAN BlockAMD64JUMPTABLE BlockARMEQ BlockARMNE BlockARMLT BlockARMLE BlockARMGT BlockARMGE BlockARMULT BlockARMULE BlockARMUGT BlockARMUGE BlockARMLTnoov BlockARMLEnoov BlockARMGTnoov BlockARMGEnoov BlockARM64EQ BlockARM64NE BlockARM64LT BlockARM64LE BlockARM64GT BlockARM64GE BlockARM64ULT BlockARM64ULE BlockARM64UGT BlockARM64UGE BlockARM64Z BlockARM64NZ BlockARM64ZW BlockARM64NZW BlockARM64TBZ BlockARM64TBNZ BlockARM64FLT BlockARM64FLE BlockARM64FGT BlockARM64FGE BlockARM64LTnoov BlockARM64LEnoov BlockARM64GTnoov BlockARM64GEnoov BlockLOONG64EQ BlockLOONG64NE BlockLOONG64LTZ BlockLOONG64LEZ BlockLOONG64GTZ BlockLOONG64GEZ BlockLOONG64FPT BlockLOONG64FPF BlockMIPSEQ BlockMIPSNE BlockMIPSLTZ BlockMIPSLEZ BlockMIPSGTZ BlockMIPSGEZ BlockMIPSFPT BlockMIPSFPF BlockMIPS64EQ BlockMIPS64NE BlockMIPS64LTZ BlockMIPS64LEZ BlockMIPS64GTZ BlockMIPS64GEZ BlockMIPS64FPT BlockMIPS64FPF BlockPPC64EQ BlockPPC64NE BlockPPC64LT BlockPPC64LE BlockPPC64GT BlockPPC64GE BlockPPC64FLT BlockPPC64FLE BlockPPC64FGT BlockPPC64FGE BlockRISCV64BEQ BlockRISCV64BNE BlockRISCV64BLT BlockRISCV64BGE BlockRISCV64BLTU BlockRISCV64BGEU BlockRISCV64BEQZ BlockRISCV64BNEZ BlockRISCV64BLEZ BlockRISCV64BGEZ BlockRISCV64BLTZ BlockRISCV64BGTZ BlockS390XBRC BlockS390XCRJ BlockS390XCGRJ BlockS390XCLRJ BlockS390XCLGRJ BlockS390XCIJ BlockS390XCGIJ BlockS390XCLIJ BlockS390XCLGIJ BlockPlain BlockIf BlockDefer BlockRet BlockRetJmp BlockExit BlockJumpTable BlockFirst ) var blockString = [...]string{ BlockInvalid: "BlockInvalid", Block386EQ: "EQ", Block386NE: "NE", Block386LT: "LT", Block386LE: "LE", Block386GT: "GT", Block386GE: "GE", Block386OS: "OS", Block386OC: "OC", Block386ULT: "ULT", Block386ULE: "ULE", Block386UGT: "UGT", Block386UGE: "UGE", Block386EQF: "EQF", Block386NEF: "NEF", Block386ORD: "ORD", Block386NAN: "NAN", BlockAMD64EQ: "EQ", BlockAMD64NE: "NE", BlockAMD64LT: "LT", BlockAMD64LE: "LE", BlockAMD64GT: "GT", BlockAMD64GE: "GE", BlockAMD64OS: "OS", BlockAMD64OC: "OC", BlockAMD64ULT: "ULT", BlockAMD64ULE: "ULE", BlockAMD64UGT: "UGT", BlockAMD64UGE: "UGE", BlockAMD64EQF: "EQF", BlockAMD64NEF: "NEF", BlockAMD64ORD: "ORD", BlockAMD64NAN: "NAN", BlockAMD64JUMPTABLE: "JUMPTABLE", BlockARMEQ: "EQ", BlockARMNE: "NE", BlockARMLT: "LT", BlockARMLE: "LE", BlockARMGT: "GT", BlockARMGE: "GE", BlockARMULT: "ULT", BlockARMULE: "ULE", BlockARMUGT: "UGT", BlockARMUGE: "UGE", BlockARMLTnoov: "LTnoov", BlockARMLEnoov: "LEnoov", BlockARMGTnoov: "GTnoov", BlockARMGEnoov: "GEnoov", BlockARM64EQ: "EQ", BlockARM64NE: "NE", BlockARM64LT: "LT", BlockARM64LE: "LE", BlockARM64GT: "GT", BlockARM64GE: "GE", BlockARM64ULT: "ULT", BlockARM64ULE: "ULE", BlockARM64UGT: "UGT", BlockARM64UGE: "UGE", BlockARM64Z: "Z", BlockARM64NZ: "NZ", BlockARM64ZW: "ZW", BlockARM64NZW: "NZW", BlockARM64TBZ: "TBZ", BlockARM64TBNZ: "TBNZ", BlockARM64FLT: "FLT", BlockARM64FLE: "FLE", BlockARM64FGT: "FGT", BlockARM64FGE: "FGE", BlockARM64LTnoov: "LTnoov", BlockARM64LEnoov: "LEnoov", BlockARM64GTnoov: "GTnoov", BlockARM64GEnoov: "GEnoov", BlockLOONG64EQ: "EQ", BlockLOONG64NE: "NE", BlockLOONG64LTZ: "LTZ", BlockLOONG64LEZ: "LEZ", BlockLOONG64GTZ: "GTZ", BlockLOONG64GEZ: "GEZ", BlockLOONG64FPT: "FPT", BlockLOONG64FPF: "FPF", BlockMIPSEQ: "EQ", BlockMIPSNE: "NE", BlockMIPSLTZ: "LTZ", BlockMIPSLEZ: "LEZ", BlockMIPSGTZ: "GTZ", BlockMIPSGEZ: "GEZ", BlockMIPSFPT: "FPT", BlockMIPSFPF: "FPF", BlockMIPS64EQ: "EQ", BlockMIPS64NE: "NE", BlockMIPS64LTZ: "LTZ", BlockMIPS64LEZ: "LEZ", BlockMIPS64GTZ: "GTZ", BlockMIPS64GEZ: "GEZ", BlockMIPS64FPT: "FPT", BlockMIPS64FPF: "FPF", BlockPPC64EQ: "EQ", BlockPPC64NE: "NE", BlockPPC64LT: "LT", BlockPPC64LE: "LE", BlockPPC64GT: "GT", BlockPPC64GE: "GE", BlockPPC64FLT: "FLT", BlockPPC64FLE: "FLE", BlockPPC64FGT: "FGT", BlockPPC64FGE: "FGE", BlockRISCV64BEQ: "BEQ", BlockRISCV64BNE: "BNE", BlockRISCV64BLT: "BLT", BlockRISCV64BGE: "BGE", BlockRISCV64BLTU: "BLTU", BlockRISCV64BGEU: "BGEU", BlockRISCV64BEQZ: "BEQZ", BlockRISCV64BNEZ: "BNEZ", BlockRISCV64BLEZ: "BLEZ", BlockRISCV64BGEZ: "BGEZ", BlockRISCV64BLTZ: "BLTZ", BlockRISCV64BGTZ: "BGTZ", BlockS390XBRC: "BRC", BlockS390XCRJ: "CRJ", BlockS390XCGRJ: "CGRJ", BlockS390XCLRJ: "CLRJ", BlockS390XCLGRJ: "CLGRJ", BlockS390XCIJ: "CIJ", BlockS390XCGIJ: "CGIJ", BlockS390XCLIJ: "CLIJ", BlockS390XCLGIJ: "CLGIJ", BlockPlain: "Plain", BlockIf: "If", BlockDefer: "Defer", BlockRet: "Ret", BlockRetJmp: "RetJmp", BlockExit: "Exit", BlockJumpTable: "JumpTable", BlockFirst: "First", } func (k BlockKind) String() string { return blockString[k] } func (k BlockKind) AuxIntType() string { switch k { case BlockARM64TBZ: return "int64" case BlockARM64TBNZ: return "int64" case BlockS390XCIJ: return "int8" case BlockS390XCGIJ: return "int8" case BlockS390XCLIJ: return "uint8" case BlockS390XCLGIJ: return "uint8" } return "" } const ( OpInvalid Op = iota Op386ADDSS Op386ADDSD Op386SUBSS Op386SUBSD Op386MULSS Op386MULSD Op386DIVSS Op386DIVSD Op386MOVSSload Op386MOVSDload Op386MOVSSconst Op386MOVSDconst Op386MOVSSloadidx1 Op386MOVSSloadidx4 Op386MOVSDloadidx1 Op386MOVSDloadidx8 Op386MOVSSstore Op386MOVSDstore Op386MOVSSstoreidx1 Op386MOVSSstoreidx4 Op386MOVSDstoreidx1 Op386MOVSDstoreidx8 Op386ADDSSload Op386ADDSDload Op386SUBSSload Op386SUBSDload Op386MULSSload Op386MULSDload Op386DIVSSload Op386DIVSDload Op386ADDL Op386ADDLconst Op386ADDLcarry Op386ADDLconstcarry Op386ADCL Op386ADCLconst Op386SUBL Op386SUBLconst Op386SUBLcarry Op386SUBLconstcarry Op386SBBL Op386SBBLconst Op386MULL Op386MULLconst Op386MULLU Op386HMULL Op386HMULLU Op386MULLQU Op386AVGLU Op386DIVL Op386DIVW Op386DIVLU Op386DIVWU Op386MODL Op386MODW Op386MODLU Op386MODWU Op386ANDL Op386ANDLconst Op386ORL Op386ORLconst Op386XORL Op386XORLconst Op386CMPL Op386CMPW Op386CMPB Op386CMPLconst Op386CMPWconst Op386CMPBconst Op386CMPLload Op386CMPWload Op386CMPBload Op386CMPLconstload Op386CMPWconstload Op386CMPBconstload Op386UCOMISS Op386UCOMISD Op386TESTL Op386TESTW Op386TESTB Op386TESTLconst Op386TESTWconst Op386TESTBconst Op386SHLL Op386SHLLconst Op386SHRL Op386SHRW Op386SHRB Op386SHRLconst Op386SHRWconst Op386SHRBconst Op386SARL Op386SARW Op386SARB Op386SARLconst Op386SARWconst Op386SARBconst Op386ROLLconst Op386ROLWconst Op386ROLBconst Op386ADDLload Op386SUBLload Op386MULLload Op386ANDLload Op386ORLload Op386XORLload Op386ADDLloadidx4 Op386SUBLloadidx4 Op386MULLloadidx4 Op386ANDLloadidx4 Op386ORLloadidx4 Op386XORLloadidx4 Op386NEGL Op386NOTL Op386BSFL Op386BSFW Op386BSRL Op386BSRW Op386BSWAPL Op386SQRTSD Op386SQRTSS Op386SBBLcarrymask Op386SETEQ Op386SETNE Op386SETL Op386SETLE Op386SETG Op386SETGE Op386SETB Op386SETBE Op386SETA Op386SETAE Op386SETO Op386SETEQF Op386SETNEF Op386SETORD Op386SETNAN Op386SETGF Op386SETGEF Op386MOVBLSX Op386MOVBLZX Op386MOVWLSX Op386MOVWLZX Op386MOVLconst Op386CVTTSD2SL Op386CVTTSS2SL Op386CVTSL2SS Op386CVTSL2SD Op386CVTSD2SS Op386CVTSS2SD Op386PXOR Op386LEAL Op386LEAL1 Op386LEAL2 Op386LEAL4 Op386LEAL8 Op386MOVBload Op386MOVBLSXload Op386MOVWload Op386MOVWLSXload Op386MOVLload Op386MOVBstore Op386MOVWstore Op386MOVLstore Op386ADDLmodify Op386SUBLmodify Op386ANDLmodify Op386ORLmodify Op386XORLmodify Op386ADDLmodifyidx4 Op386SUBLmodifyidx4 Op386ANDLmodifyidx4 Op386ORLmodifyidx4 Op386XORLmodifyidx4 Op386ADDLconstmodify Op386ANDLconstmodify Op386ORLconstmodify Op386XORLconstmodify Op386ADDLconstmodifyidx4 Op386ANDLconstmodifyidx4 Op386ORLconstmodifyidx4 Op386XORLconstmodifyidx4 Op386MOVBloadidx1 Op386MOVWloadidx1 Op386MOVWloadidx2 Op386MOVLloadidx1 Op386MOVLloadidx4 Op386MOVBstoreidx1 Op386MOVWstoreidx1 Op386MOVWstoreidx2 Op386MOVLstoreidx1 Op386MOVLstoreidx4 Op386MOVBstoreconst Op386MOVWstoreconst Op386MOVLstoreconst Op386MOVBstoreconstidx1 Op386MOVWstoreconstidx1 Op386MOVWstoreconstidx2 Op386MOVLstoreconstidx1 Op386MOVLstoreconstidx4 Op386DUFFZERO Op386REPSTOSL Op386CALLstatic Op386CALLtail Op386CALLclosure Op386CALLinter Op386DUFFCOPY Op386REPMOVSL Op386InvertFlags Op386LoweredGetG Op386LoweredGetClosurePtr Op386LoweredGetCallerPC Op386LoweredGetCallerSP Op386LoweredNilCheck Op386LoweredWB Op386LoweredPanicBoundsA Op386LoweredPanicBoundsB Op386LoweredPanicBoundsC Op386LoweredPanicExtendA Op386LoweredPanicExtendB Op386LoweredPanicExtendC Op386FlagEQ Op386FlagLT_ULT Op386FlagLT_UGT Op386FlagGT_UGT Op386FlagGT_ULT Op386MOVSSconst1 Op386MOVSDconst1 Op386MOVSSconst2 Op386MOVSDconst2 OpAMD64ADDSS OpAMD64ADDSD OpAMD64SUBSS OpAMD64SUBSD OpAMD64MULSS OpAMD64MULSD OpAMD64DIVSS OpAMD64DIVSD OpAMD64MOVSSload OpAMD64MOVSDload OpAMD64MOVSSconst OpAMD64MOVSDconst OpAMD64MOVSSloadidx1 OpAMD64MOVSSloadidx4 OpAMD64MOVSDloadidx1 OpAMD64MOVSDloadidx8 OpAMD64MOVSSstore OpAMD64MOVSDstore OpAMD64MOVSSstoreidx1 OpAMD64MOVSSstoreidx4 OpAMD64MOVSDstoreidx1 OpAMD64MOVSDstoreidx8 OpAMD64ADDSSload OpAMD64ADDSDload OpAMD64SUBSSload OpAMD64SUBSDload OpAMD64MULSSload OpAMD64MULSDload OpAMD64DIVSSload OpAMD64DIVSDload OpAMD64ADDSSloadidx1 OpAMD64ADDSSloadidx4 OpAMD64ADDSDloadidx1 OpAMD64ADDSDloadidx8 OpAMD64SUBSSloadidx1 OpAMD64SUBSSloadidx4 OpAMD64SUBSDloadidx1 OpAMD64SUBSDloadidx8 OpAMD64MULSSloadidx1 OpAMD64MULSSloadidx4 OpAMD64MULSDloadidx1 OpAMD64MULSDloadidx8 OpAMD64DIVSSloadidx1 OpAMD64DIVSSloadidx4 OpAMD64DIVSDloadidx1 OpAMD64DIVSDloadidx8 OpAMD64ADDQ OpAMD64ADDL OpAMD64ADDQconst OpAMD64ADDLconst OpAMD64ADDQconstmodify OpAMD64ADDLconstmodify OpAMD64SUBQ OpAMD64SUBL OpAMD64SUBQconst OpAMD64SUBLconst OpAMD64MULQ OpAMD64MULL OpAMD64MULQconst OpAMD64MULLconst OpAMD64MULLU OpAMD64MULQU OpAMD64HMULQ OpAMD64HMULL OpAMD64HMULQU OpAMD64HMULLU OpAMD64AVGQU OpAMD64DIVQ OpAMD64DIVL OpAMD64DIVW OpAMD64DIVQU OpAMD64DIVLU OpAMD64DIVWU OpAMD64NEGLflags OpAMD64ADDQcarry OpAMD64ADCQ OpAMD64ADDQconstcarry OpAMD64ADCQconst OpAMD64SUBQborrow OpAMD64SBBQ OpAMD64SUBQconstborrow OpAMD64SBBQconst OpAMD64MULQU2 OpAMD64DIVQU2 OpAMD64ANDQ OpAMD64ANDL OpAMD64ANDQconst OpAMD64ANDLconst OpAMD64ANDQconstmodify OpAMD64ANDLconstmodify OpAMD64ORQ OpAMD64ORL OpAMD64ORQconst OpAMD64ORLconst OpAMD64ORQconstmodify OpAMD64ORLconstmodify OpAMD64XORQ OpAMD64XORL OpAMD64XORQconst OpAMD64XORLconst OpAMD64XORQconstmodify OpAMD64XORLconstmodify OpAMD64CMPQ OpAMD64CMPL OpAMD64CMPW OpAMD64CMPB OpAMD64CMPQconst OpAMD64CMPLconst OpAMD64CMPWconst OpAMD64CMPBconst OpAMD64CMPQload OpAMD64CMPLload OpAMD64CMPWload OpAMD64CMPBload OpAMD64CMPQconstload OpAMD64CMPLconstload OpAMD64CMPWconstload OpAMD64CMPBconstload OpAMD64CMPQloadidx8 OpAMD64CMPQloadidx1 OpAMD64CMPLloadidx4 OpAMD64CMPLloadidx1 OpAMD64CMPWloadidx2 OpAMD64CMPWloadidx1 OpAMD64CMPBloadidx1 OpAMD64CMPQconstloadidx8 OpAMD64CMPQconstloadidx1 OpAMD64CMPLconstloadidx4 OpAMD64CMPLconstloadidx1 OpAMD64CMPWconstloadidx2 OpAMD64CMPWconstloadidx1 OpAMD64CMPBconstloadidx1 OpAMD64UCOMISS OpAMD64UCOMISD OpAMD64BTL OpAMD64BTQ OpAMD64BTCL OpAMD64BTCQ OpAMD64BTRL OpAMD64BTRQ OpAMD64BTSL OpAMD64BTSQ OpAMD64BTLconst OpAMD64BTQconst OpAMD64BTCLconst OpAMD64BTCQconst OpAMD64BTRLconst OpAMD64BTRQconst OpAMD64BTSLconst OpAMD64BTSQconst OpAMD64TESTQ OpAMD64TESTL OpAMD64TESTW OpAMD64TESTB OpAMD64TESTQconst OpAMD64TESTLconst OpAMD64TESTWconst OpAMD64TESTBconst OpAMD64SHLQ OpAMD64SHLL OpAMD64SHLQconst OpAMD64SHLLconst OpAMD64SHRQ OpAMD64SHRL OpAMD64SHRW OpAMD64SHRB OpAMD64SHRQconst OpAMD64SHRLconst OpAMD64SHRWconst OpAMD64SHRBconst OpAMD64SARQ OpAMD64SARL OpAMD64SARW OpAMD64SARB OpAMD64SARQconst OpAMD64SARLconst OpAMD64SARWconst OpAMD64SARBconst OpAMD64SHRDQ OpAMD64SHLDQ OpAMD64ROLQ OpAMD64ROLL OpAMD64ROLW OpAMD64ROLB OpAMD64RORQ OpAMD64RORL OpAMD64RORW OpAMD64RORB OpAMD64ROLQconst OpAMD64ROLLconst OpAMD64ROLWconst OpAMD64ROLBconst OpAMD64ADDLload OpAMD64ADDQload OpAMD64SUBQload OpAMD64SUBLload OpAMD64ANDLload OpAMD64ANDQload OpAMD64ORQload OpAMD64ORLload OpAMD64XORQload OpAMD64XORLload OpAMD64ADDLloadidx1 OpAMD64ADDLloadidx4 OpAMD64ADDLloadidx8 OpAMD64ADDQloadidx1 OpAMD64ADDQloadidx8 OpAMD64SUBLloadidx1 OpAMD64SUBLloadidx4 OpAMD64SUBLloadidx8 OpAMD64SUBQloadidx1 OpAMD64SUBQloadidx8 OpAMD64ANDLloadidx1 OpAMD64ANDLloadidx4 OpAMD64ANDLloadidx8 OpAMD64ANDQloadidx1 OpAMD64ANDQloadidx8 OpAMD64ORLloadidx1 OpAMD64ORLloadidx4 OpAMD64ORLloadidx8 OpAMD64ORQloadidx1 OpAMD64ORQloadidx8 OpAMD64XORLloadidx1 OpAMD64XORLloadidx4 OpAMD64XORLloadidx8 OpAMD64XORQloadidx1 OpAMD64XORQloadidx8 OpAMD64ADDQmodify OpAMD64SUBQmodify OpAMD64ANDQmodify OpAMD64ORQmodify OpAMD64XORQmodify OpAMD64ADDLmodify OpAMD64SUBLmodify OpAMD64ANDLmodify OpAMD64ORLmodify OpAMD64XORLmodify OpAMD64ADDQmodifyidx1 OpAMD64ADDQmodifyidx8 OpAMD64SUBQmodifyidx1 OpAMD64SUBQmodifyidx8 OpAMD64ANDQmodifyidx1 OpAMD64ANDQmodifyidx8 OpAMD64ORQmodifyidx1 OpAMD64ORQmodifyidx8 OpAMD64XORQmodifyidx1 OpAMD64XORQmodifyidx8 OpAMD64ADDLmodifyidx1 OpAMD64ADDLmodifyidx4 OpAMD64ADDLmodifyidx8 OpAMD64SUBLmodifyidx1 OpAMD64SUBLmodifyidx4 OpAMD64SUBLmodifyidx8 OpAMD64ANDLmodifyidx1 OpAMD64ANDLmodifyidx4 OpAMD64ANDLmodifyidx8 OpAMD64ORLmodifyidx1 OpAMD64ORLmodifyidx4 OpAMD64ORLmodifyidx8 OpAMD64XORLmodifyidx1 OpAMD64XORLmodifyidx4 OpAMD64XORLmodifyidx8 OpAMD64ADDQconstmodifyidx1 OpAMD64ADDQconstmodifyidx8 OpAMD64ANDQconstmodifyidx1 OpAMD64ANDQconstmodifyidx8 OpAMD64ORQconstmodifyidx1 OpAMD64ORQconstmodifyidx8 OpAMD64XORQconstmodifyidx1 OpAMD64XORQconstmodifyidx8 OpAMD64ADDLconstmodifyidx1 OpAMD64ADDLconstmodifyidx4 OpAMD64ADDLconstmodifyidx8 OpAMD64ANDLconstmodifyidx1 OpAMD64ANDLconstmodifyidx4 OpAMD64ANDLconstmodifyidx8 OpAMD64ORLconstmodifyidx1 OpAMD64ORLconstmodifyidx4 OpAMD64ORLconstmodifyidx8 OpAMD64XORLconstmodifyidx1 OpAMD64XORLconstmodifyidx4 OpAMD64XORLconstmodifyidx8 OpAMD64NEGQ OpAMD64NEGL OpAMD64NOTQ OpAMD64NOTL OpAMD64BSFQ OpAMD64BSFL OpAMD64BSRQ OpAMD64BSRL OpAMD64CMOVQEQ OpAMD64CMOVQNE OpAMD64CMOVQLT OpAMD64CMOVQGT OpAMD64CMOVQLE OpAMD64CMOVQGE OpAMD64CMOVQLS OpAMD64CMOVQHI OpAMD64CMOVQCC OpAMD64CMOVQCS OpAMD64CMOVLEQ OpAMD64CMOVLNE OpAMD64CMOVLLT OpAMD64CMOVLGT OpAMD64CMOVLLE OpAMD64CMOVLGE OpAMD64CMOVLLS OpAMD64CMOVLHI OpAMD64CMOVLCC OpAMD64CMOVLCS OpAMD64CMOVWEQ OpAMD64CMOVWNE OpAMD64CMOVWLT OpAMD64CMOVWGT OpAMD64CMOVWLE OpAMD64CMOVWGE OpAMD64CMOVWLS OpAMD64CMOVWHI OpAMD64CMOVWCC OpAMD64CMOVWCS OpAMD64CMOVQEQF OpAMD64CMOVQNEF OpAMD64CMOVQGTF OpAMD64CMOVQGEF OpAMD64CMOVLEQF OpAMD64CMOVLNEF OpAMD64CMOVLGTF OpAMD64CMOVLGEF OpAMD64CMOVWEQF OpAMD64CMOVWNEF OpAMD64CMOVWGTF OpAMD64CMOVWGEF OpAMD64BSWAPQ OpAMD64BSWAPL OpAMD64POPCNTQ OpAMD64POPCNTL OpAMD64SQRTSD OpAMD64SQRTSS OpAMD64ROUNDSD OpAMD64VFMADD231SD OpAMD64SBBQcarrymask OpAMD64SBBLcarrymask OpAMD64SETEQ OpAMD64SETNE OpAMD64SETL OpAMD64SETLE OpAMD64SETG OpAMD64SETGE OpAMD64SETB OpAMD64SETBE OpAMD64SETA OpAMD64SETAE OpAMD64SETO OpAMD64SETEQstore OpAMD64SETNEstore OpAMD64SETLstore OpAMD64SETLEstore OpAMD64SETGstore OpAMD64SETGEstore OpAMD64SETBstore OpAMD64SETBEstore OpAMD64SETAstore OpAMD64SETAEstore OpAMD64SETEQF OpAMD64SETNEF OpAMD64SETORD OpAMD64SETNAN OpAMD64SETGF OpAMD64SETGEF OpAMD64MOVBQSX OpAMD64MOVBQZX OpAMD64MOVWQSX OpAMD64MOVWQZX OpAMD64MOVLQSX OpAMD64MOVLQZX OpAMD64MOVLconst OpAMD64MOVQconst OpAMD64CVTTSD2SL OpAMD64CVTTSD2SQ OpAMD64CVTTSS2SL OpAMD64CVTTSS2SQ OpAMD64CVTSL2SS OpAMD64CVTSL2SD OpAMD64CVTSQ2SS OpAMD64CVTSQ2SD OpAMD64CVTSD2SS OpAMD64CVTSS2SD OpAMD64MOVQi2f OpAMD64MOVQf2i OpAMD64MOVLi2f OpAMD64MOVLf2i OpAMD64PXOR OpAMD64LEAQ OpAMD64LEAL OpAMD64LEAW OpAMD64LEAQ1 OpAMD64LEAL1 OpAMD64LEAW1 OpAMD64LEAQ2 OpAMD64LEAL2 OpAMD64LEAW2 OpAMD64LEAQ4 OpAMD64LEAL4 OpAMD64LEAW4 OpAMD64LEAQ8 OpAMD64LEAL8 OpAMD64LEAW8 OpAMD64MOVBload OpAMD64MOVBQSXload OpAMD64MOVWload OpAMD64MOVWQSXload OpAMD64MOVLload OpAMD64MOVLQSXload OpAMD64MOVQload OpAMD64MOVBstore OpAMD64MOVWstore OpAMD64MOVLstore OpAMD64MOVQstore OpAMD64MOVOload OpAMD64MOVOstore OpAMD64MOVBloadidx1 OpAMD64MOVWloadidx1 OpAMD64MOVWloadidx2 OpAMD64MOVLloadidx1 OpAMD64MOVLloadidx4 OpAMD64MOVLloadidx8 OpAMD64MOVQloadidx1 OpAMD64MOVQloadidx8 OpAMD64MOVBstoreidx1 OpAMD64MOVWstoreidx1 OpAMD64MOVWstoreidx2 OpAMD64MOVLstoreidx1 OpAMD64MOVLstoreidx4 OpAMD64MOVLstoreidx8 OpAMD64MOVQstoreidx1 OpAMD64MOVQstoreidx8 OpAMD64MOVBstoreconst OpAMD64MOVWstoreconst OpAMD64MOVLstoreconst OpAMD64MOVQstoreconst OpAMD64MOVOstoreconst OpAMD64MOVBstoreconstidx1 OpAMD64MOVWstoreconstidx1 OpAMD64MOVWstoreconstidx2 OpAMD64MOVLstoreconstidx1 OpAMD64MOVLstoreconstidx4 OpAMD64MOVQstoreconstidx1 OpAMD64MOVQstoreconstidx8 OpAMD64DUFFZERO OpAMD64REPSTOSQ OpAMD64CALLstatic OpAMD64CALLtail OpAMD64CALLclosure OpAMD64CALLinter OpAMD64DUFFCOPY OpAMD64REPMOVSQ OpAMD64InvertFlags OpAMD64LoweredGetG OpAMD64LoweredGetClosurePtr OpAMD64LoweredGetCallerPC OpAMD64LoweredGetCallerSP OpAMD64LoweredNilCheck OpAMD64LoweredWB OpAMD64LoweredHasCPUFeature OpAMD64LoweredPanicBoundsA OpAMD64LoweredPanicBoundsB OpAMD64LoweredPanicBoundsC OpAMD64FlagEQ OpAMD64FlagLT_ULT OpAMD64FlagLT_UGT OpAMD64FlagGT_UGT OpAMD64FlagGT_ULT OpAMD64MOVBatomicload OpAMD64MOVLatomicload OpAMD64MOVQatomicload OpAMD64XCHGB OpAMD64XCHGL OpAMD64XCHGQ OpAMD64XADDLlock OpAMD64XADDQlock OpAMD64AddTupleFirst32 OpAMD64AddTupleFirst64 OpAMD64CMPXCHGLlock OpAMD64CMPXCHGQlock OpAMD64ANDBlock OpAMD64ANDLlock OpAMD64ORBlock OpAMD64ORLlock OpAMD64PrefetchT0 OpAMD64PrefetchNTA OpAMD64ANDNQ OpAMD64ANDNL OpAMD64BLSIQ OpAMD64BLSIL OpAMD64BLSMSKQ OpAMD64BLSMSKL OpAMD64BLSRQ OpAMD64BLSRL OpAMD64TZCNTQ OpAMD64TZCNTL OpAMD64LZCNTQ OpAMD64LZCNTL OpAMD64MOVBEWstore OpAMD64MOVBELload OpAMD64MOVBELstore OpAMD64MOVBEQload OpAMD64MOVBEQstore OpAMD64MOVBELloadidx1 OpAMD64MOVBELloadidx4 OpAMD64MOVBELloadidx8 OpAMD64MOVBEQloadidx1 OpAMD64MOVBEQloadidx8 OpAMD64MOVBEWstoreidx1 OpAMD64MOVBEWstoreidx2 OpAMD64MOVBELstoreidx1 OpAMD64MOVBELstoreidx4 OpAMD64MOVBELstoreidx8 OpAMD64MOVBEQstoreidx1 OpAMD64MOVBEQstoreidx8 OpAMD64SARXQ OpAMD64SARXL OpAMD64SHLXQ OpAMD64SHLXL OpAMD64SHRXQ OpAMD64SHRXL OpAMD64SARXLload OpAMD64SARXQload OpAMD64SHLXLload OpAMD64SHLXQload OpAMD64SHRXLload OpAMD64SHRXQload OpAMD64SARXLloadidx1 OpAMD64SARXLloadidx4 OpAMD64SARXLloadidx8 OpAMD64SARXQloadidx1 OpAMD64SARXQloadidx8 OpAMD64SHLXLloadidx1 OpAMD64SHLXLloadidx4 OpAMD64SHLXLloadidx8 OpAMD64SHLXQloadidx1 OpAMD64SHLXQloadidx8 OpAMD64SHRXLloadidx1 OpAMD64SHRXLloadidx4 OpAMD64SHRXLloadidx8 OpAMD64SHRXQloadidx1 OpAMD64SHRXQloadidx8 OpARMADD OpARMADDconst OpARMSUB OpARMSUBconst OpARMRSB OpARMRSBconst OpARMMUL OpARMHMUL OpARMHMULU OpARMCALLudiv OpARMADDS OpARMADDSconst OpARMADC OpARMADCconst OpARMSUBS OpARMSUBSconst OpARMRSBSconst OpARMSBC OpARMSBCconst OpARMRSCconst OpARMMULLU OpARMMULA OpARMMULS OpARMADDF OpARMADDD OpARMSUBF OpARMSUBD OpARMMULF OpARMMULD OpARMNMULF OpARMNMULD OpARMDIVF OpARMDIVD OpARMMULAF OpARMMULAD OpARMMULSF OpARMMULSD OpARMFMULAD OpARMAND OpARMANDconst OpARMOR OpARMORconst OpARMXOR OpARMXORconst OpARMBIC OpARMBICconst OpARMBFX OpARMBFXU OpARMMVN OpARMNEGF OpARMNEGD OpARMSQRTD OpARMSQRTF OpARMABSD OpARMCLZ OpARMREV OpARMREV16 OpARMRBIT OpARMSLL OpARMSLLconst OpARMSRL OpARMSRLconst OpARMSRA OpARMSRAconst OpARMSRR OpARMSRRconst OpARMADDshiftLL OpARMADDshiftRL OpARMADDshiftRA OpARMSUBshiftLL OpARMSUBshiftRL OpARMSUBshiftRA OpARMRSBshiftLL OpARMRSBshiftRL OpARMRSBshiftRA OpARMANDshiftLL OpARMANDshiftRL OpARMANDshiftRA OpARMORshiftLL OpARMORshiftRL OpARMORshiftRA OpARMXORshiftLL OpARMXORshiftRL OpARMXORshiftRA OpARMXORshiftRR OpARMBICshiftLL OpARMBICshiftRL OpARMBICshiftRA OpARMMVNshiftLL OpARMMVNshiftRL OpARMMVNshiftRA OpARMADCshiftLL OpARMADCshiftRL OpARMADCshiftRA OpARMSBCshiftLL OpARMSBCshiftRL OpARMSBCshiftRA OpARMRSCshiftLL OpARMRSCshiftRL OpARMRSCshiftRA OpARMADDSshiftLL OpARMADDSshiftRL OpARMADDSshiftRA OpARMSUBSshiftLL OpARMSUBSshiftRL OpARMSUBSshiftRA OpARMRSBSshiftLL OpARMRSBSshiftRL OpARMRSBSshiftRA OpARMADDshiftLLreg OpARMADDshiftRLreg OpARMADDshiftRAreg OpARMSUBshiftLLreg OpARMSUBshiftRLreg OpARMSUBshiftRAreg OpARMRSBshiftLLreg OpARMRSBshiftRLreg OpARMRSBshiftRAreg OpARMANDshiftLLreg OpARMANDshiftRLreg OpARMANDshiftRAreg OpARMORshiftLLreg OpARMORshiftRLreg OpARMORshiftRAreg OpARMXORshiftLLreg OpARMXORshiftRLreg OpARMXORshiftRAreg OpARMBICshiftLLreg OpARMBICshiftRLreg OpARMBICshiftRAreg OpARMMVNshiftLLreg OpARMMVNshiftRLreg OpARMMVNshiftRAreg OpARMADCshiftLLreg OpARMADCshiftRLreg OpARMADCshiftRAreg OpARMSBCshiftLLreg OpARMSBCshiftRLreg OpARMSBCshiftRAreg OpARMRSCshiftLLreg OpARMRSCshiftRLreg OpARMRSCshiftRAreg OpARMADDSshiftLLreg OpARMADDSshiftRLreg OpARMADDSshiftRAreg OpARMSUBSshiftLLreg OpARMSUBSshiftRLreg OpARMSUBSshiftRAreg OpARMRSBSshiftLLreg OpARMRSBSshiftRLreg OpARMRSBSshiftRAreg OpARMCMP OpARMCMPconst OpARMCMN OpARMCMNconst OpARMTST OpARMTSTconst OpARMTEQ OpARMTEQconst OpARMCMPF OpARMCMPD OpARMCMPshiftLL OpARMCMPshiftRL OpARMCMPshiftRA OpARMCMNshiftLL OpARMCMNshiftRL OpARMCMNshiftRA OpARMTSTshiftLL OpARMTSTshiftRL OpARMTSTshiftRA OpARMTEQshiftLL OpARMTEQshiftRL OpARMTEQshiftRA OpARMCMPshiftLLreg OpARMCMPshiftRLreg OpARMCMPshiftRAreg OpARMCMNshiftLLreg OpARMCMNshiftRLreg OpARMCMNshiftRAreg OpARMTSTshiftLLreg OpARMTSTshiftRLreg OpARMTSTshiftRAreg OpARMTEQshiftLLreg OpARMTEQshiftRLreg OpARMTEQshiftRAreg OpARMCMPF0 OpARMCMPD0 OpARMMOVWconst OpARMMOVFconst OpARMMOVDconst OpARMMOVWaddr OpARMMOVBload OpARMMOVBUload OpARMMOVHload OpARMMOVHUload OpARMMOVWload OpARMMOVFload OpARMMOVDload OpARMMOVBstore OpARMMOVHstore OpARMMOVWstore OpARMMOVFstore OpARMMOVDstore OpARMMOVWloadidx OpARMMOVWloadshiftLL OpARMMOVWloadshiftRL OpARMMOVWloadshiftRA OpARMMOVBUloadidx OpARMMOVBloadidx OpARMMOVHUloadidx OpARMMOVHloadidx OpARMMOVWstoreidx OpARMMOVWstoreshiftLL OpARMMOVWstoreshiftRL OpARMMOVWstoreshiftRA OpARMMOVBstoreidx OpARMMOVHstoreidx OpARMMOVBreg OpARMMOVBUreg OpARMMOVHreg OpARMMOVHUreg OpARMMOVWreg OpARMMOVWnop OpARMMOVWF OpARMMOVWD OpARMMOVWUF OpARMMOVWUD OpARMMOVFW OpARMMOVDW OpARMMOVFWU OpARMMOVDWU OpARMMOVFD OpARMMOVDF OpARMCMOVWHSconst OpARMCMOVWLSconst OpARMSRAcond OpARMCALLstatic OpARMCALLtail OpARMCALLclosure OpARMCALLinter OpARMLoweredNilCheck OpARMEqual OpARMNotEqual OpARMLessThan OpARMLessEqual OpARMGreaterThan OpARMGreaterEqual OpARMLessThanU OpARMLessEqualU OpARMGreaterThanU OpARMGreaterEqualU OpARMDUFFZERO OpARMDUFFCOPY OpARMLoweredZero OpARMLoweredMove OpARMLoweredGetClosurePtr OpARMLoweredGetCallerSP OpARMLoweredGetCallerPC OpARMLoweredPanicBoundsA OpARMLoweredPanicBoundsB OpARMLoweredPanicBoundsC OpARMLoweredPanicExtendA OpARMLoweredPanicExtendB OpARMLoweredPanicExtendC OpARMFlagConstant OpARMInvertFlags OpARMLoweredWB OpARM64ADCSflags OpARM64ADCzerocarry OpARM64ADD OpARM64ADDconst OpARM64ADDSconstflags OpARM64ADDSflags OpARM64SUB OpARM64SUBconst OpARM64SBCSflags OpARM64SUBSflags OpARM64MUL OpARM64MULW OpARM64MNEG OpARM64MNEGW OpARM64MULH OpARM64UMULH OpARM64MULL OpARM64UMULL OpARM64DIV OpARM64UDIV OpARM64DIVW OpARM64UDIVW OpARM64MOD OpARM64UMOD OpARM64MODW OpARM64UMODW OpARM64FADDS OpARM64FADDD OpARM64FSUBS OpARM64FSUBD OpARM64FMULS OpARM64FMULD OpARM64FNMULS OpARM64FNMULD OpARM64FDIVS OpARM64FDIVD OpARM64AND OpARM64ANDconst OpARM64OR OpARM64ORconst OpARM64XOR OpARM64XORconst OpARM64BIC OpARM64EON OpARM64ORN OpARM64LoweredMuluhilo OpARM64MVN OpARM64NEG OpARM64NEGSflags OpARM64NGCzerocarry OpARM64FABSD OpARM64FNEGS OpARM64FNEGD OpARM64FSQRTD OpARM64FSQRTS OpARM64REV OpARM64REVW OpARM64REV16 OpARM64REV16W OpARM64RBIT OpARM64RBITW OpARM64CLZ OpARM64CLZW OpARM64VCNT OpARM64VUADDLV OpARM64LoweredRound32F OpARM64LoweredRound64F OpARM64FMADDS OpARM64FMADDD OpARM64FNMADDS OpARM64FNMADDD OpARM64FMSUBS OpARM64FMSUBD OpARM64FNMSUBS OpARM64FNMSUBD OpARM64MADD OpARM64MADDW OpARM64MSUB OpARM64MSUBW OpARM64SLL OpARM64SLLconst OpARM64SRL OpARM64SRLconst OpARM64SRA OpARM64SRAconst OpARM64ROR OpARM64RORW OpARM64RORconst OpARM64RORWconst OpARM64EXTRconst OpARM64EXTRWconst OpARM64CMP OpARM64CMPconst OpARM64CMPW OpARM64CMPWconst OpARM64CMN OpARM64CMNconst OpARM64CMNW OpARM64CMNWconst OpARM64TST OpARM64TSTconst OpARM64TSTW OpARM64TSTWconst OpARM64FCMPS OpARM64FCMPD OpARM64FCMPS0 OpARM64FCMPD0 OpARM64MVNshiftLL OpARM64MVNshiftRL OpARM64MVNshiftRA OpARM64MVNshiftRO OpARM64NEGshiftLL OpARM64NEGshiftRL OpARM64NEGshiftRA OpARM64ADDshiftLL OpARM64ADDshiftRL OpARM64ADDshiftRA OpARM64SUBshiftLL OpARM64SUBshiftRL OpARM64SUBshiftRA OpARM64ANDshiftLL OpARM64ANDshiftRL OpARM64ANDshiftRA OpARM64ANDshiftRO OpARM64ORshiftLL OpARM64ORshiftRL OpARM64ORshiftRA OpARM64ORshiftRO OpARM64XORshiftLL OpARM64XORshiftRL OpARM64XORshiftRA OpARM64XORshiftRO OpARM64BICshiftLL OpARM64BICshiftRL OpARM64BICshiftRA OpARM64BICshiftRO OpARM64EONshiftLL OpARM64EONshiftRL OpARM64EONshiftRA OpARM64EONshiftRO OpARM64ORNshiftLL OpARM64ORNshiftRL OpARM64ORNshiftRA OpARM64ORNshiftRO OpARM64CMPshiftLL OpARM64CMPshiftRL OpARM64CMPshiftRA OpARM64CMNshiftLL OpARM64CMNshiftRL OpARM64CMNshiftRA OpARM64TSTshiftLL OpARM64TSTshiftRL OpARM64TSTshiftRA OpARM64TSTshiftRO OpARM64BFI OpARM64BFXIL OpARM64SBFIZ OpARM64SBFX OpARM64UBFIZ OpARM64UBFX OpARM64MOVDconst OpARM64FMOVSconst OpARM64FMOVDconst OpARM64MOVDaddr OpARM64MOVBload OpARM64MOVBUload OpARM64MOVHload OpARM64MOVHUload OpARM64MOVWload OpARM64MOVWUload OpARM64MOVDload OpARM64FMOVSload OpARM64FMOVDload OpARM64MOVDloadidx OpARM64MOVWloadidx OpARM64MOVWUloadidx OpARM64MOVHloadidx OpARM64MOVHUloadidx OpARM64MOVBloadidx OpARM64MOVBUloadidx OpARM64FMOVSloadidx OpARM64FMOVDloadidx OpARM64MOVHloadidx2 OpARM64MOVHUloadidx2 OpARM64MOVWloadidx4 OpARM64MOVWUloadidx4 OpARM64MOVDloadidx8 OpARM64FMOVSloadidx4 OpARM64FMOVDloadidx8 OpARM64MOVBstore OpARM64MOVHstore OpARM64MOVWstore OpARM64MOVDstore OpARM64STP OpARM64FMOVSstore OpARM64FMOVDstore OpARM64MOVBstoreidx OpARM64MOVHstoreidx OpARM64MOVWstoreidx OpARM64MOVDstoreidx OpARM64FMOVSstoreidx OpARM64FMOVDstoreidx OpARM64MOVHstoreidx2 OpARM64MOVWstoreidx4 OpARM64MOVDstoreidx8 OpARM64FMOVSstoreidx4 OpARM64FMOVDstoreidx8 OpARM64MOVBstorezero OpARM64MOVHstorezero OpARM64MOVWstorezero OpARM64MOVDstorezero OpARM64MOVQstorezero OpARM64MOVBstorezeroidx OpARM64MOVHstorezeroidx OpARM64MOVWstorezeroidx OpARM64MOVDstorezeroidx OpARM64MOVHstorezeroidx2 OpARM64MOVWstorezeroidx4 OpARM64MOVDstorezeroidx8 OpARM64FMOVDgpfp OpARM64FMOVDfpgp OpARM64FMOVSgpfp OpARM64FMOVSfpgp OpARM64MOVBreg OpARM64MOVBUreg OpARM64MOVHreg OpARM64MOVHUreg OpARM64MOVWreg OpARM64MOVWUreg OpARM64MOVDreg OpARM64MOVDnop OpARM64SCVTFWS OpARM64SCVTFWD OpARM64UCVTFWS OpARM64UCVTFWD OpARM64SCVTFS OpARM64SCVTFD OpARM64UCVTFS OpARM64UCVTFD OpARM64FCVTZSSW OpARM64FCVTZSDW OpARM64FCVTZUSW OpARM64FCVTZUDW OpARM64FCVTZSS OpARM64FCVTZSD OpARM64FCVTZUS OpARM64FCVTZUD OpARM64FCVTSD OpARM64FCVTDS OpARM64FRINTAD OpARM64FRINTMD OpARM64FRINTND OpARM64FRINTPD OpARM64FRINTZD OpARM64CSEL OpARM64CSEL0 OpARM64CSINC OpARM64CSINV OpARM64CSNEG OpARM64CSETM OpARM64CALLstatic OpARM64CALLtail OpARM64CALLclosure OpARM64CALLinter OpARM64LoweredNilCheck OpARM64Equal OpARM64NotEqual OpARM64LessThan OpARM64LessEqual OpARM64GreaterThan OpARM64GreaterEqual OpARM64LessThanU OpARM64LessEqualU OpARM64GreaterThanU OpARM64GreaterEqualU OpARM64LessThanF OpARM64LessEqualF OpARM64GreaterThanF OpARM64GreaterEqualF OpARM64NotLessThanF OpARM64NotLessEqualF OpARM64NotGreaterThanF OpARM64NotGreaterEqualF OpARM64DUFFZERO OpARM64LoweredZero OpARM64DUFFCOPY OpARM64LoweredMove OpARM64LoweredGetClosurePtr OpARM64LoweredGetCallerSP OpARM64LoweredGetCallerPC OpARM64FlagConstant OpARM64InvertFlags OpARM64LDAR OpARM64LDARB OpARM64LDARW OpARM64STLRB OpARM64STLR OpARM64STLRW OpARM64LoweredAtomicExchange64 OpARM64LoweredAtomicExchange32 OpARM64LoweredAtomicExchange64Variant OpARM64LoweredAtomicExchange32Variant OpARM64LoweredAtomicAdd64 OpARM64LoweredAtomicAdd32 OpARM64LoweredAtomicAdd64Variant OpARM64LoweredAtomicAdd32Variant OpARM64LoweredAtomicCas64 OpARM64LoweredAtomicCas32 OpARM64LoweredAtomicCas64Variant OpARM64LoweredAtomicCas32Variant OpARM64LoweredAtomicAnd8 OpARM64LoweredAtomicAnd32 OpARM64LoweredAtomicOr8 OpARM64LoweredAtomicOr32 OpARM64LoweredAtomicAnd8Variant OpARM64LoweredAtomicAnd32Variant OpARM64LoweredAtomicOr8Variant OpARM64LoweredAtomicOr32Variant OpARM64LoweredWB OpARM64LoweredPanicBoundsA OpARM64LoweredPanicBoundsB OpARM64LoweredPanicBoundsC OpARM64PRFM OpARM64DMB OpLOONG64ADDV OpLOONG64ADDVconst OpLOONG64SUBV OpLOONG64SUBVconst OpLOONG64MULV OpLOONG64MULVU OpLOONG64DIVV OpLOONG64DIVVU OpLOONG64ADDF OpLOONG64ADDD OpLOONG64SUBF OpLOONG64SUBD OpLOONG64MULF OpLOONG64MULD OpLOONG64DIVF OpLOONG64DIVD OpLOONG64AND OpLOONG64ANDconst OpLOONG64OR OpLOONG64ORconst OpLOONG64XOR OpLOONG64XORconst OpLOONG64NOR OpLOONG64NORconst OpLOONG64NEGV OpLOONG64NEGF OpLOONG64NEGD OpLOONG64SQRTD OpLOONG64SQRTF OpLOONG64SLLV OpLOONG64SLLVconst OpLOONG64SRLV OpLOONG64SRLVconst OpLOONG64SRAV OpLOONG64SRAVconst OpLOONG64SGT OpLOONG64SGTconst OpLOONG64SGTU OpLOONG64SGTUconst OpLOONG64CMPEQF OpLOONG64CMPEQD OpLOONG64CMPGEF OpLOONG64CMPGED OpLOONG64CMPGTF OpLOONG64CMPGTD OpLOONG64MOVVconst OpLOONG64MOVFconst OpLOONG64MOVDconst OpLOONG64MOVVaddr OpLOONG64MOVBload OpLOONG64MOVBUload OpLOONG64MOVHload OpLOONG64MOVHUload OpLOONG64MOVWload OpLOONG64MOVWUload OpLOONG64MOVVload OpLOONG64MOVFload OpLOONG64MOVDload OpLOONG64MOVBstore OpLOONG64MOVHstore OpLOONG64MOVWstore OpLOONG64MOVVstore OpLOONG64MOVFstore OpLOONG64MOVDstore OpLOONG64MOVBstorezero OpLOONG64MOVHstorezero OpLOONG64MOVWstorezero OpLOONG64MOVVstorezero OpLOONG64MOVBreg OpLOONG64MOVBUreg OpLOONG64MOVHreg OpLOONG64MOVHUreg OpLOONG64MOVWreg OpLOONG64MOVWUreg OpLOONG64MOVVreg OpLOONG64MOVVnop OpLOONG64MOVWF OpLOONG64MOVWD OpLOONG64MOVVF OpLOONG64MOVVD OpLOONG64TRUNCFW OpLOONG64TRUNCDW OpLOONG64TRUNCFV OpLOONG64TRUNCDV OpLOONG64MOVFD OpLOONG64MOVDF OpLOONG64CALLstatic OpLOONG64CALLtail OpLOONG64CALLclosure OpLOONG64CALLinter OpLOONG64DUFFZERO OpLOONG64DUFFCOPY OpLOONG64LoweredZero OpLOONG64LoweredMove OpLOONG64LoweredAtomicLoad8 OpLOONG64LoweredAtomicLoad32 OpLOONG64LoweredAtomicLoad64 OpLOONG64LoweredAtomicStore8 OpLOONG64LoweredAtomicStore32 OpLOONG64LoweredAtomicStore64 OpLOONG64LoweredAtomicStorezero32 OpLOONG64LoweredAtomicStorezero64 OpLOONG64LoweredAtomicExchange32 OpLOONG64LoweredAtomicExchange64 OpLOONG64LoweredAtomicAdd32 OpLOONG64LoweredAtomicAdd64 OpLOONG64LoweredAtomicAddconst32 OpLOONG64LoweredAtomicAddconst64 OpLOONG64LoweredAtomicCas32 OpLOONG64LoweredAtomicCas64 OpLOONG64LoweredNilCheck OpLOONG64FPFlagTrue OpLOONG64FPFlagFalse OpLOONG64LoweredGetClosurePtr OpLOONG64LoweredGetCallerSP OpLOONG64LoweredGetCallerPC OpLOONG64LoweredWB OpLOONG64LoweredPanicBoundsA OpLOONG64LoweredPanicBoundsB OpLOONG64LoweredPanicBoundsC OpMIPSADD OpMIPSADDconst OpMIPSSUB OpMIPSSUBconst OpMIPSMUL OpMIPSMULT OpMIPSMULTU OpMIPSDIV OpMIPSDIVU OpMIPSADDF OpMIPSADDD OpMIPSSUBF OpMIPSSUBD OpMIPSMULF OpMIPSMULD OpMIPSDIVF OpMIPSDIVD OpMIPSAND OpMIPSANDconst OpMIPSOR OpMIPSORconst OpMIPSXOR OpMIPSXORconst OpMIPSNOR OpMIPSNORconst OpMIPSNEG OpMIPSNEGF OpMIPSNEGD OpMIPSSQRTD OpMIPSSQRTF OpMIPSSLL OpMIPSSLLconst OpMIPSSRL OpMIPSSRLconst OpMIPSSRA OpMIPSSRAconst OpMIPSCLZ OpMIPSSGT OpMIPSSGTconst OpMIPSSGTzero OpMIPSSGTU OpMIPSSGTUconst OpMIPSSGTUzero OpMIPSCMPEQF OpMIPSCMPEQD OpMIPSCMPGEF OpMIPSCMPGED OpMIPSCMPGTF OpMIPSCMPGTD OpMIPSMOVWconst OpMIPSMOVFconst OpMIPSMOVDconst OpMIPSMOVWaddr OpMIPSMOVBload OpMIPSMOVBUload OpMIPSMOVHload OpMIPSMOVHUload OpMIPSMOVWload OpMIPSMOVFload OpMIPSMOVDload OpMIPSMOVBstore OpMIPSMOVHstore OpMIPSMOVWstore OpMIPSMOVFstore OpMIPSMOVDstore OpMIPSMOVBstorezero OpMIPSMOVHstorezero OpMIPSMOVWstorezero OpMIPSMOVBreg OpMIPSMOVBUreg OpMIPSMOVHreg OpMIPSMOVHUreg OpMIPSMOVWreg OpMIPSMOVWnop OpMIPSCMOVZ OpMIPSCMOVZzero OpMIPSMOVWF OpMIPSMOVWD OpMIPSTRUNCFW OpMIPSTRUNCDW OpMIPSMOVFD OpMIPSMOVDF OpMIPSCALLstatic OpMIPSCALLtail OpMIPSCALLclosure OpMIPSCALLinter OpMIPSLoweredAtomicLoad8 OpMIPSLoweredAtomicLoad32 OpMIPSLoweredAtomicStore8 OpMIPSLoweredAtomicStore32 OpMIPSLoweredAtomicStorezero OpMIPSLoweredAtomicExchange OpMIPSLoweredAtomicAdd OpMIPSLoweredAtomicAddconst OpMIPSLoweredAtomicCas OpMIPSLoweredAtomicAnd OpMIPSLoweredAtomicOr OpMIPSLoweredZero OpMIPSLoweredMove OpMIPSLoweredNilCheck OpMIPSFPFlagTrue OpMIPSFPFlagFalse OpMIPSLoweredGetClosurePtr OpMIPSLoweredGetCallerSP OpMIPSLoweredGetCallerPC OpMIPSLoweredWB OpMIPSLoweredPanicBoundsA OpMIPSLoweredPanicBoundsB OpMIPSLoweredPanicBoundsC OpMIPSLoweredPanicExtendA OpMIPSLoweredPanicExtendB OpMIPSLoweredPanicExtendC OpMIPS64ADDV OpMIPS64ADDVconst OpMIPS64SUBV OpMIPS64SUBVconst OpMIPS64MULV OpMIPS64MULVU OpMIPS64DIVV OpMIPS64DIVVU OpMIPS64ADDF OpMIPS64ADDD OpMIPS64SUBF OpMIPS64SUBD OpMIPS64MULF OpMIPS64MULD OpMIPS64DIVF OpMIPS64DIVD OpMIPS64AND OpMIPS64ANDconst OpMIPS64OR OpMIPS64ORconst OpMIPS64XOR OpMIPS64XORconst OpMIPS64NOR OpMIPS64NORconst OpMIPS64NEGV OpMIPS64NEGF OpMIPS64NEGD OpMIPS64SQRTD OpMIPS64SQRTF OpMIPS64SLLV OpMIPS64SLLVconst OpMIPS64SRLV OpMIPS64SRLVconst OpMIPS64SRAV OpMIPS64SRAVconst OpMIPS64SGT OpMIPS64SGTconst OpMIPS64SGTU OpMIPS64SGTUconst OpMIPS64CMPEQF OpMIPS64CMPEQD OpMIPS64CMPGEF OpMIPS64CMPGED OpMIPS64CMPGTF OpMIPS64CMPGTD OpMIPS64MOVVconst OpMIPS64MOVFconst OpMIPS64MOVDconst OpMIPS64MOVVaddr OpMIPS64MOVBload OpMIPS64MOVBUload OpMIPS64MOVHload OpMIPS64MOVHUload OpMIPS64MOVWload OpMIPS64MOVWUload OpMIPS64MOVVload OpMIPS64MOVFload OpMIPS64MOVDload OpMIPS64MOVBstore OpMIPS64MOVHstore OpMIPS64MOVWstore OpMIPS64MOVVstore OpMIPS64MOVFstore OpMIPS64MOVDstore OpMIPS64MOVBstorezero OpMIPS64MOVHstorezero OpMIPS64MOVWstorezero OpMIPS64MOVVstorezero OpMIPS64MOVBreg OpMIPS64MOVBUreg OpMIPS64MOVHreg OpMIPS64MOVHUreg OpMIPS64MOVWreg OpMIPS64MOVWUreg OpMIPS64MOVVreg OpMIPS64MOVVnop OpMIPS64MOVWF OpMIPS64MOVWD OpMIPS64MOVVF OpMIPS64MOVVD OpMIPS64TRUNCFW OpMIPS64TRUNCDW OpMIPS64TRUNCFV OpMIPS64TRUNCDV OpMIPS64MOVFD OpMIPS64MOVDF OpMIPS64CALLstatic OpMIPS64CALLtail OpMIPS64CALLclosure OpMIPS64CALLinter OpMIPS64DUFFZERO OpMIPS64DUFFCOPY OpMIPS64LoweredZero OpMIPS64LoweredMove OpMIPS64LoweredAtomicLoad8 OpMIPS64LoweredAtomicLoad32 OpMIPS64LoweredAtomicLoad64 OpMIPS64LoweredAtomicStore8 OpMIPS64LoweredAtomicStore32 OpMIPS64LoweredAtomicStore64 OpMIPS64LoweredAtomicStorezero32 OpMIPS64LoweredAtomicStorezero64 OpMIPS64LoweredAtomicExchange32 OpMIPS64LoweredAtomicExchange64 OpMIPS64LoweredAtomicAdd32 OpMIPS64LoweredAtomicAdd64 OpMIPS64LoweredAtomicAddconst32 OpMIPS64LoweredAtomicAddconst64 OpMIPS64LoweredAtomicCas32 OpMIPS64LoweredAtomicCas64 OpMIPS64LoweredNilCheck OpMIPS64FPFlagTrue OpMIPS64FPFlagFalse OpMIPS64LoweredGetClosurePtr OpMIPS64LoweredGetCallerSP OpMIPS64LoweredGetCallerPC OpMIPS64LoweredWB OpMIPS64LoweredPanicBoundsA OpMIPS64LoweredPanicBoundsB OpMIPS64LoweredPanicBoundsC OpPPC64ADD OpPPC64ADDconst OpPPC64FADD OpPPC64FADDS OpPPC64SUB OpPPC64SUBFCconst OpPPC64FSUB OpPPC64FSUBS OpPPC64MULLD OpPPC64MULLW OpPPC64MULLDconst OpPPC64MULLWconst OpPPC64MADDLD OpPPC64MULHD OpPPC64MULHW OpPPC64MULHDU OpPPC64MULHWU OpPPC64LoweredMuluhilo OpPPC64FMUL OpPPC64FMULS OpPPC64FMADD OpPPC64FMADDS OpPPC64FMSUB OpPPC64FMSUBS OpPPC64SRAD OpPPC64SRAW OpPPC64SRD OpPPC64SRW OpPPC64SLD OpPPC64SLW OpPPC64ROTL OpPPC64ROTLW OpPPC64RLDICL OpPPC64CLRLSLWI OpPPC64CLRLSLDI OpPPC64ADDC OpPPC64SUBC OpPPC64ADDCconst OpPPC64SUBCconst OpPPC64ADDE OpPPC64SUBE OpPPC64ADDZEzero OpPPC64SUBZEzero OpPPC64SRADconst OpPPC64SRAWconst OpPPC64SRDconst OpPPC64SRWconst OpPPC64SLDconst OpPPC64SLWconst OpPPC64ROTLconst OpPPC64ROTLWconst OpPPC64EXTSWSLconst OpPPC64RLWINM OpPPC64RLWNM OpPPC64RLWMI OpPPC64CNTLZD OpPPC64CNTLZW OpPPC64CNTTZD OpPPC64CNTTZW OpPPC64POPCNTD OpPPC64POPCNTW OpPPC64POPCNTB OpPPC64FDIV OpPPC64FDIVS OpPPC64DIVD OpPPC64DIVW OpPPC64DIVDU OpPPC64DIVWU OpPPC64MODUD OpPPC64MODSD OpPPC64MODUW OpPPC64MODSW OpPPC64FCTIDZ OpPPC64FCTIWZ OpPPC64FCFID OpPPC64FCFIDS OpPPC64FRSP OpPPC64MFVSRD OpPPC64MTVSRD OpPPC64AND OpPPC64ANDN OpPPC64ANDCC OpPPC64OR OpPPC64ORN OpPPC64ORCC OpPPC64NOR OpPPC64XOR OpPPC64XORCC OpPPC64EQV OpPPC64NEG OpPPC64FNEG OpPPC64FSQRT OpPPC64FSQRTS OpPPC64FFLOOR OpPPC64FCEIL OpPPC64FTRUNC OpPPC64FROUND OpPPC64FABS OpPPC64FNABS OpPPC64FCPSGN OpPPC64ORconst OpPPC64XORconst OpPPC64ANDconst OpPPC64ANDCCconst OpPPC64MOVBreg OpPPC64MOVBZreg OpPPC64MOVHreg OpPPC64MOVHZreg OpPPC64MOVWreg OpPPC64MOVWZreg OpPPC64MOVBZload OpPPC64MOVHload OpPPC64MOVHZload OpPPC64MOVWload OpPPC64MOVWZload OpPPC64MOVDload OpPPC64MOVDBRload OpPPC64MOVWBRload OpPPC64MOVHBRload OpPPC64MOVBZloadidx OpPPC64MOVHloadidx OpPPC64MOVHZloadidx OpPPC64MOVWloadidx OpPPC64MOVWZloadidx OpPPC64MOVDloadidx OpPPC64MOVHBRloadidx OpPPC64MOVWBRloadidx OpPPC64MOVDBRloadidx OpPPC64FMOVDloadidx OpPPC64FMOVSloadidx OpPPC64DCBT OpPPC64MOVDBRstore OpPPC64MOVWBRstore OpPPC64MOVHBRstore OpPPC64FMOVDload OpPPC64FMOVSload OpPPC64MOVBstore OpPPC64MOVHstore OpPPC64MOVWstore OpPPC64MOVDstore OpPPC64FMOVDstore OpPPC64FMOVSstore OpPPC64MOVBstoreidx OpPPC64MOVHstoreidx OpPPC64MOVWstoreidx OpPPC64MOVDstoreidx OpPPC64FMOVDstoreidx OpPPC64FMOVSstoreidx OpPPC64MOVHBRstoreidx OpPPC64MOVWBRstoreidx OpPPC64MOVDBRstoreidx OpPPC64MOVBstorezero OpPPC64MOVHstorezero OpPPC64MOVWstorezero OpPPC64MOVDstorezero OpPPC64MOVDaddr OpPPC64MOVDconst OpPPC64FMOVDconst OpPPC64FMOVSconst OpPPC64FCMPU OpPPC64CMP OpPPC64CMPU OpPPC64CMPW OpPPC64CMPWU OpPPC64CMPconst OpPPC64CMPUconst OpPPC64CMPWconst OpPPC64CMPWUconst OpPPC64ISEL OpPPC64ISELB OpPPC64Equal OpPPC64NotEqual OpPPC64LessThan OpPPC64FLessThan OpPPC64LessEqual OpPPC64FLessEqual OpPPC64GreaterThan OpPPC64FGreaterThan OpPPC64GreaterEqual OpPPC64FGreaterEqual OpPPC64LoweredGetClosurePtr OpPPC64LoweredGetCallerSP OpPPC64LoweredGetCallerPC OpPPC64LoweredNilCheck OpPPC64LoweredRound32F OpPPC64LoweredRound64F OpPPC64CALLstatic OpPPC64CALLtail OpPPC64CALLclosure OpPPC64CALLinter OpPPC64LoweredZero OpPPC64LoweredZeroShort OpPPC64LoweredQuadZeroShort OpPPC64LoweredQuadZero OpPPC64LoweredMove OpPPC64LoweredMoveShort OpPPC64LoweredQuadMove OpPPC64LoweredQuadMoveShort OpPPC64LoweredAtomicStore8 OpPPC64LoweredAtomicStore32 OpPPC64LoweredAtomicStore64 OpPPC64LoweredAtomicLoad8 OpPPC64LoweredAtomicLoad32 OpPPC64LoweredAtomicLoad64 OpPPC64LoweredAtomicLoadPtr OpPPC64LoweredAtomicAdd32 OpPPC64LoweredAtomicAdd64 OpPPC64LoweredAtomicExchange32 OpPPC64LoweredAtomicExchange64 OpPPC64LoweredAtomicCas64 OpPPC64LoweredAtomicCas32 OpPPC64LoweredAtomicAnd8 OpPPC64LoweredAtomicAnd32 OpPPC64LoweredAtomicOr8 OpPPC64LoweredAtomicOr32 OpPPC64LoweredWB OpPPC64LoweredPubBarrier OpPPC64LoweredPanicBoundsA OpPPC64LoweredPanicBoundsB OpPPC64LoweredPanicBoundsC OpPPC64InvertFlags OpPPC64FlagEQ OpPPC64FlagLT OpPPC64FlagGT OpRISCV64ADD OpRISCV64ADDI OpRISCV64ADDIW OpRISCV64NEG OpRISCV64NEGW OpRISCV64SUB OpRISCV64SUBW OpRISCV64MUL OpRISCV64MULW OpRISCV64MULH OpRISCV64MULHU OpRISCV64LoweredMuluhilo OpRISCV64LoweredMuluover OpRISCV64DIV OpRISCV64DIVU OpRISCV64DIVW OpRISCV64DIVUW OpRISCV64REM OpRISCV64REMU OpRISCV64REMW OpRISCV64REMUW OpRISCV64MOVaddr OpRISCV64MOVDconst OpRISCV64MOVBload OpRISCV64MOVHload OpRISCV64MOVWload OpRISCV64MOVDload OpRISCV64MOVBUload OpRISCV64MOVHUload OpRISCV64MOVWUload OpRISCV64MOVBstore OpRISCV64MOVHstore OpRISCV64MOVWstore OpRISCV64MOVDstore OpRISCV64MOVBstorezero OpRISCV64MOVHstorezero OpRISCV64MOVWstorezero OpRISCV64MOVDstorezero OpRISCV64MOVBreg OpRISCV64MOVHreg OpRISCV64MOVWreg OpRISCV64MOVDreg OpRISCV64MOVBUreg OpRISCV64MOVHUreg OpRISCV64MOVWUreg OpRISCV64MOVDnop OpRISCV64SLL OpRISCV64SRA OpRISCV64SRL OpRISCV64SLLI OpRISCV64SRAI OpRISCV64SRLI OpRISCV64XOR OpRISCV64XORI OpRISCV64OR OpRISCV64ORI OpRISCV64AND OpRISCV64ANDI OpRISCV64NOT OpRISCV64SEQZ OpRISCV64SNEZ OpRISCV64SLT OpRISCV64SLTI OpRISCV64SLTU OpRISCV64SLTIU OpRISCV64MOVconvert OpRISCV64CALLstatic OpRISCV64CALLtail OpRISCV64CALLclosure OpRISCV64CALLinter OpRISCV64DUFFZERO OpRISCV64DUFFCOPY OpRISCV64LoweredZero OpRISCV64LoweredMove OpRISCV64LoweredAtomicLoad8 OpRISCV64LoweredAtomicLoad32 OpRISCV64LoweredAtomicLoad64 OpRISCV64LoweredAtomicStore8 OpRISCV64LoweredAtomicStore32 OpRISCV64LoweredAtomicStore64 OpRISCV64LoweredAtomicExchange32 OpRISCV64LoweredAtomicExchange64 OpRISCV64LoweredAtomicAdd32 OpRISCV64LoweredAtomicAdd64 OpRISCV64LoweredAtomicCas32 OpRISCV64LoweredAtomicCas64 OpRISCV64LoweredAtomicAnd32 OpRISCV64LoweredAtomicOr32 OpRISCV64LoweredNilCheck OpRISCV64LoweredGetClosurePtr OpRISCV64LoweredGetCallerSP OpRISCV64LoweredGetCallerPC OpRISCV64LoweredWB OpRISCV64LoweredPanicBoundsA OpRISCV64LoweredPanicBoundsB OpRISCV64LoweredPanicBoundsC OpRISCV64FADDS OpRISCV64FSUBS OpRISCV64FMULS OpRISCV64FDIVS OpRISCV64FSQRTS OpRISCV64FNEGS OpRISCV64FMVSX OpRISCV64FCVTSW OpRISCV64FCVTSL OpRISCV64FCVTWS OpRISCV64FCVTLS OpRISCV64FMOVWload OpRISCV64FMOVWstore OpRISCV64FEQS OpRISCV64FNES OpRISCV64FLTS OpRISCV64FLES OpRISCV64FADDD OpRISCV64FSUBD OpRISCV64FMULD OpRISCV64FDIVD OpRISCV64FMADDD OpRISCV64FMSUBD OpRISCV64FNMADDD OpRISCV64FNMSUBD OpRISCV64FSQRTD OpRISCV64FNEGD OpRISCV64FABSD OpRISCV64FSGNJD OpRISCV64FMVDX OpRISCV64FCVTDW OpRISCV64FCVTDL OpRISCV64FCVTWD OpRISCV64FCVTLD OpRISCV64FCVTDS OpRISCV64FCVTSD OpRISCV64FMOVDload OpRISCV64FMOVDstore OpRISCV64FEQD OpRISCV64FNED OpRISCV64FLTD OpRISCV64FLED OpS390XFADDS OpS390XFADD OpS390XFSUBS OpS390XFSUB OpS390XFMULS OpS390XFMUL OpS390XFDIVS OpS390XFDIV OpS390XFNEGS OpS390XFNEG OpS390XFMADDS OpS390XFMADD OpS390XFMSUBS OpS390XFMSUB OpS390XLPDFR OpS390XLNDFR OpS390XCPSDR OpS390XFIDBR OpS390XFMOVSload OpS390XFMOVDload OpS390XFMOVSconst OpS390XFMOVDconst OpS390XFMOVSloadidx OpS390XFMOVDloadidx OpS390XFMOVSstore OpS390XFMOVDstore OpS390XFMOVSstoreidx OpS390XFMOVDstoreidx OpS390XADD OpS390XADDW OpS390XADDconst OpS390XADDWconst OpS390XADDload OpS390XADDWload OpS390XSUB OpS390XSUBW OpS390XSUBconst OpS390XSUBWconst OpS390XSUBload OpS390XSUBWload OpS390XMULLD OpS390XMULLW OpS390XMULLDconst OpS390XMULLWconst OpS390XMULLDload OpS390XMULLWload OpS390XMULHD OpS390XMULHDU OpS390XDIVD OpS390XDIVW OpS390XDIVDU OpS390XDIVWU OpS390XMODD OpS390XMODW OpS390XMODDU OpS390XMODWU OpS390XAND OpS390XANDW OpS390XANDconst OpS390XANDWconst OpS390XANDload OpS390XANDWload OpS390XOR OpS390XORW OpS390XORconst OpS390XORWconst OpS390XORload OpS390XORWload OpS390XXOR OpS390XXORW OpS390XXORconst OpS390XXORWconst OpS390XXORload OpS390XXORWload OpS390XADDC OpS390XADDCconst OpS390XADDE OpS390XSUBC OpS390XSUBE OpS390XCMP OpS390XCMPW OpS390XCMPU OpS390XCMPWU OpS390XCMPconst OpS390XCMPWconst OpS390XCMPUconst OpS390XCMPWUconst OpS390XFCMPS OpS390XFCMP OpS390XLTDBR OpS390XLTEBR OpS390XSLD OpS390XSLW OpS390XSLDconst OpS390XSLWconst OpS390XSRD OpS390XSRW OpS390XSRDconst OpS390XSRWconst OpS390XSRAD OpS390XSRAW OpS390XSRADconst OpS390XSRAWconst OpS390XRLLG OpS390XRLL OpS390XRLLconst OpS390XRXSBG OpS390XRISBGZ OpS390XNEG OpS390XNEGW OpS390XNOT OpS390XNOTW OpS390XFSQRT OpS390XFSQRTS OpS390XLOCGR OpS390XMOVBreg OpS390XMOVBZreg OpS390XMOVHreg OpS390XMOVHZreg OpS390XMOVWreg OpS390XMOVWZreg OpS390XMOVDconst OpS390XLDGR OpS390XLGDR OpS390XCFDBRA OpS390XCGDBRA OpS390XCFEBRA OpS390XCGEBRA OpS390XCEFBRA OpS390XCDFBRA OpS390XCEGBRA OpS390XCDGBRA OpS390XCLFEBR OpS390XCLFDBR OpS390XCLGEBR OpS390XCLGDBR OpS390XCELFBR OpS390XCDLFBR OpS390XCELGBR OpS390XCDLGBR OpS390XLEDBR OpS390XLDEBR OpS390XMOVDaddr OpS390XMOVDaddridx OpS390XMOVBZload OpS390XMOVBload OpS390XMOVHZload OpS390XMOVHload OpS390XMOVWZload OpS390XMOVWload OpS390XMOVDload OpS390XMOVWBR OpS390XMOVDBR OpS390XMOVHBRload OpS390XMOVWBRload OpS390XMOVDBRload OpS390XMOVBstore OpS390XMOVHstore OpS390XMOVWstore OpS390XMOVDstore OpS390XMOVHBRstore OpS390XMOVWBRstore OpS390XMOVDBRstore OpS390XMVC OpS390XMOVBZloadidx OpS390XMOVBloadidx OpS390XMOVHZloadidx OpS390XMOVHloadidx OpS390XMOVWZloadidx OpS390XMOVWloadidx OpS390XMOVDloadidx OpS390XMOVHBRloadidx OpS390XMOVWBRloadidx OpS390XMOVDBRloadidx OpS390XMOVBstoreidx OpS390XMOVHstoreidx OpS390XMOVWstoreidx OpS390XMOVDstoreidx OpS390XMOVHBRstoreidx OpS390XMOVWBRstoreidx OpS390XMOVDBRstoreidx OpS390XMOVBstoreconst OpS390XMOVHstoreconst OpS390XMOVWstoreconst OpS390XMOVDstoreconst OpS390XCLEAR OpS390XCALLstatic OpS390XCALLtail OpS390XCALLclosure OpS390XCALLinter OpS390XInvertFlags OpS390XLoweredGetG OpS390XLoweredGetClosurePtr OpS390XLoweredGetCallerSP OpS390XLoweredGetCallerPC OpS390XLoweredNilCheck OpS390XLoweredRound32F OpS390XLoweredRound64F OpS390XLoweredWB OpS390XLoweredPanicBoundsA OpS390XLoweredPanicBoundsB OpS390XLoweredPanicBoundsC OpS390XFlagEQ OpS390XFlagLT OpS390XFlagGT OpS390XFlagOV OpS390XSYNC OpS390XMOVBZatomicload OpS390XMOVWZatomicload OpS390XMOVDatomicload OpS390XMOVBatomicstore OpS390XMOVWatomicstore OpS390XMOVDatomicstore OpS390XLAA OpS390XLAAG OpS390XAddTupleFirst32 OpS390XAddTupleFirst64 OpS390XLAN OpS390XLANfloor OpS390XLAO OpS390XLAOfloor OpS390XLoweredAtomicCas32 OpS390XLoweredAtomicCas64 OpS390XLoweredAtomicExchange32 OpS390XLoweredAtomicExchange64 OpS390XFLOGR OpS390XPOPCNT OpS390XMLGR OpS390XSumBytes2 OpS390XSumBytes4 OpS390XSumBytes8 OpS390XSTMG2 OpS390XSTMG3 OpS390XSTMG4 OpS390XSTM2 OpS390XSTM3 OpS390XSTM4 OpS390XLoweredMove OpS390XLoweredZero OpWasmLoweredStaticCall OpWasmLoweredTailCall OpWasmLoweredClosureCall OpWasmLoweredInterCall OpWasmLoweredAddr OpWasmLoweredMove OpWasmLoweredZero OpWasmLoweredGetClosurePtr OpWasmLoweredGetCallerPC OpWasmLoweredGetCallerSP OpWasmLoweredNilCheck OpWasmLoweredWB OpWasmLoweredConvert OpWasmSelect OpWasmI64Load8U OpWasmI64Load8S OpWasmI64Load16U OpWasmI64Load16S OpWasmI64Load32U OpWasmI64Load32S OpWasmI64Load OpWasmI64Store8 OpWasmI64Store16 OpWasmI64Store32 OpWasmI64Store OpWasmF32Load OpWasmF64Load OpWasmF32Store OpWasmF64Store OpWasmI64Const OpWasmF32Const OpWasmF64Const OpWasmI64Eqz OpWasmI64Eq OpWasmI64Ne OpWasmI64LtS OpWasmI64LtU OpWasmI64GtS OpWasmI64GtU OpWasmI64LeS OpWasmI64LeU OpWasmI64GeS OpWasmI64GeU OpWasmF32Eq OpWasmF32Ne OpWasmF32Lt OpWasmF32Gt OpWasmF32Le OpWasmF32Ge OpWasmF64Eq OpWasmF64Ne OpWasmF64Lt OpWasmF64Gt OpWasmF64Le OpWasmF64Ge OpWasmI64Add OpWasmI64AddConst OpWasmI64Sub OpWasmI64Mul OpWasmI64DivS OpWasmI64DivU OpWasmI64RemS OpWasmI64RemU OpWasmI64And OpWasmI64Or OpWasmI64Xor OpWasmI64Shl OpWasmI64ShrS OpWasmI64ShrU OpWasmF32Neg OpWasmF32Add OpWasmF32Sub OpWasmF32Mul OpWasmF32Div OpWasmF64Neg OpWasmF64Add OpWasmF64Sub OpWasmF64Mul OpWasmF64Div OpWasmI64TruncSatF64S OpWasmI64TruncSatF64U OpWasmI64TruncSatF32S OpWasmI64TruncSatF32U OpWasmF32ConvertI64S OpWasmF32ConvertI64U OpWasmF64ConvertI64S OpWasmF64ConvertI64U OpWasmF32DemoteF64 OpWasmF64PromoteF32 OpWasmI64Extend8S OpWasmI64Extend16S OpWasmI64Extend32S OpWasmF32Sqrt OpWasmF32Trunc OpWasmF32Ceil OpWasmF32Floor OpWasmF32Nearest OpWasmF32Abs OpWasmF32Copysign OpWasmF64Sqrt OpWasmF64Trunc OpWasmF64Ceil OpWasmF64Floor OpWasmF64Nearest OpWasmF64Abs OpWasmF64Copysign OpWasmI64Ctz OpWasmI64Clz OpWasmI32Rotl OpWasmI64Rotl OpWasmI64Popcnt OpAdd8 OpAdd16 OpAdd32 OpAdd64 OpAddPtr OpAdd32F OpAdd64F OpSub8 OpSub16 OpSub32 OpSub64 OpSubPtr OpSub32F OpSub64F OpMul8 OpMul16 OpMul32 OpMul64 OpMul32F OpMul64F OpDiv32F OpDiv64F OpHmul32 OpHmul32u OpHmul64 OpHmul64u OpMul32uhilo OpMul64uhilo OpMul32uover OpMul64uover OpAvg32u OpAvg64u OpDiv8 OpDiv8u OpDiv16 OpDiv16u OpDiv32 OpDiv32u OpDiv64 OpDiv64u OpDiv128u OpMod8 OpMod8u OpMod16 OpMod16u OpMod32 OpMod32u OpMod64 OpMod64u OpAnd8 OpAnd16 OpAnd32 OpAnd64 OpOr8 OpOr16 OpOr32 OpOr64 OpXor8 OpXor16 OpXor32 OpXor64 OpLsh8x8 OpLsh8x16 OpLsh8x32 OpLsh8x64 OpLsh16x8 OpLsh16x16 OpLsh16x32 OpLsh16x64 OpLsh32x8 OpLsh32x16 OpLsh32x32 OpLsh32x64 OpLsh64x8 OpLsh64x16 OpLsh64x32 OpLsh64x64 OpRsh8x8 OpRsh8x16 OpRsh8x32 OpRsh8x64 OpRsh16x8 OpRsh16x16 OpRsh16x32 OpRsh16x64 OpRsh32x8 OpRsh32x16 OpRsh32x32 OpRsh32x64 OpRsh64x8 OpRsh64x16 OpRsh64x32 OpRsh64x64 OpRsh8Ux8 OpRsh8Ux16 OpRsh8Ux32 OpRsh8Ux64 OpRsh16Ux8 OpRsh16Ux16 OpRsh16Ux32 OpRsh16Ux64 OpRsh32Ux8 OpRsh32Ux16 OpRsh32Ux32 OpRsh32Ux64 OpRsh64Ux8 OpRsh64Ux16 OpRsh64Ux32 OpRsh64Ux64 OpEq8 OpEq16 OpEq32 OpEq64 OpEqPtr OpEqInter OpEqSlice OpEq32F OpEq64F OpNeq8 OpNeq16 OpNeq32 OpNeq64 OpNeqPtr OpNeqInter OpNeqSlice OpNeq32F OpNeq64F OpLess8 OpLess8U OpLess16 OpLess16U OpLess32 OpLess32U OpLess64 OpLess64U OpLess32F OpLess64F OpLeq8 OpLeq8U OpLeq16 OpLeq16U OpLeq32 OpLeq32U OpLeq64 OpLeq64U OpLeq32F OpLeq64F OpCondSelect OpAndB OpOrB OpEqB OpNeqB OpNot OpNeg8 OpNeg16 OpNeg32 OpNeg64 OpNeg32F OpNeg64F OpCom8 OpCom16 OpCom32 OpCom64 OpCtz8 OpCtz16 OpCtz32 OpCtz64 OpCtz8NonZero OpCtz16NonZero OpCtz32NonZero OpCtz64NonZero OpBitLen8 OpBitLen16 OpBitLen32 OpBitLen64 OpBswap32 OpBswap64 OpBitRev8 OpBitRev16 OpBitRev32 OpBitRev64 OpPopCount8 OpPopCount16 OpPopCount32 OpPopCount64 OpRotateLeft8 OpRotateLeft16 OpRotateLeft32 OpRotateLeft64 OpSqrt OpSqrt32 OpFloor OpCeil OpTrunc OpRound OpRoundToEven OpAbs OpCopysign OpFMA OpPhi OpCopy OpConvert OpConstBool OpConstString OpConstNil OpConst8 OpConst16 OpConst32 OpConst64 OpConst32F OpConst64F OpConstInterface OpConstSlice OpInitMem OpArg OpArgIntReg OpArgFloatReg OpAddr OpLocalAddr OpSP OpSB OpLoad OpDereference OpStore OpMove OpZero OpStoreWB OpMoveWB OpZeroWB OpWB OpHasCPUFeature OpPanicBounds OpPanicExtend OpClosureCall OpStaticCall OpInterCall OpTailCall OpClosureLECall OpStaticLECall OpInterLECall OpTailLECall OpSignExt8to16 OpSignExt8to32 OpSignExt8to64 OpSignExt16to32 OpSignExt16to64 OpSignExt32to64 OpZeroExt8to16 OpZeroExt8to32 OpZeroExt8to64 OpZeroExt16to32 OpZeroExt16to64 OpZeroExt32to64 OpTrunc16to8 OpTrunc32to8 OpTrunc32to16 OpTrunc64to8 OpTrunc64to16 OpTrunc64to32 OpCvt32to32F OpCvt32to64F OpCvt64to32F OpCvt64to64F OpCvt32Fto32 OpCvt32Fto64 OpCvt64Fto32 OpCvt64Fto64 OpCvt32Fto64F OpCvt64Fto32F OpCvtBoolToUint8 OpRound32F OpRound64F OpIsNonNil OpIsInBounds OpIsSliceInBounds OpNilCheck OpGetG OpGetClosurePtr OpGetCallerPC OpGetCallerSP OpPtrIndex OpOffPtr OpSliceMake OpSlicePtr OpSliceLen OpSliceCap OpSlicePtrUnchecked OpComplexMake OpComplexReal OpComplexImag OpStringMake OpStringPtr OpStringLen OpIMake OpITab OpIData OpStructMake0 OpStructMake1 OpStructMake2 OpStructMake3 OpStructMake4 OpStructSelect OpArrayMake0 OpArrayMake1 OpArraySelect OpStoreReg OpLoadReg OpFwdRef OpUnknown OpVarDef OpVarKill OpVarLive OpKeepAlive OpInlMark OpInt64Make OpInt64Hi OpInt64Lo OpAdd32carry OpAdd32withcarry OpSub32carry OpSub32withcarry OpAdd64carry OpSub64borrow OpSignmask OpZeromask OpSlicemask OpSpectreIndex OpSpectreSliceIndex OpCvt32Uto32F OpCvt32Uto64F OpCvt32Fto32U OpCvt64Fto32U OpCvt64Uto32F OpCvt64Uto64F OpCvt32Fto64U OpCvt64Fto64U OpSelect0 OpSelect1 OpSelectN OpSelectNAddr OpMakeResult OpAtomicLoad8 OpAtomicLoad32 OpAtomicLoad64 OpAtomicLoadPtr OpAtomicLoadAcq32 OpAtomicLoadAcq64 OpAtomicStore8 OpAtomicStore32 OpAtomicStore64 OpAtomicStorePtrNoWB OpAtomicStoreRel32 OpAtomicStoreRel64 OpAtomicExchange32 OpAtomicExchange64 OpAtomicAdd32 OpAtomicAdd64 OpAtomicCompareAndSwap32 OpAtomicCompareAndSwap64 OpAtomicCompareAndSwapRel32 OpAtomicAnd8 OpAtomicAnd32 OpAtomicOr8 OpAtomicOr32 OpAtomicAdd32Variant OpAtomicAdd64Variant OpAtomicExchange32Variant OpAtomicExchange64Variant OpAtomicCompareAndSwap32Variant OpAtomicCompareAndSwap64Variant OpAtomicAnd8Variant OpAtomicAnd32Variant OpAtomicOr8Variant OpAtomicOr32Variant OpPubBarrier OpClobber OpClobberReg OpPrefetchCache OpPrefetchCacheStreamed ) var opcodeTable = [...]opInfo{ {name: "OpInvalid"}, { name: "ADDSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSS", argLen: 2, resultInArg0: true, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSD", argLen: 2, resultInArg0: true, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSS", argLen: 2, resultInArg0: true, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSD", argLen: 2, resultInArg0: true, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: x86.AMOVSS, reg: regInfo{ outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: x86.AMOVSD, reg: regInfo{ outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSSstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSSstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVSDstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SUBSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "DIVSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 239}, // AX CX DX BX BP SI DI {0, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLcarry", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADCL", argLen: 3, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AADCL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADCLconst", auxType: auxInt32, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AADCL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLcarry", argLen: 2, resultInArg0: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {1, 0}, {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SBBL", argLen: 3, resultInArg0: true, clobberFlags: true, asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SBBLconst", auxType: auxInt32, argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AIMUL3L, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "HMULL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULLU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MULLQU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 255}, // AX CX DX BX SP BP SI DI }, outputs: []outputInfo{ {0, 4}, // DX {1, 1}, // AX }, }, }, { name: "AVGLU", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "DIVL", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVW", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "DIVWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 4, // DX outputs: []outputInfo{ {0, 1}, // AX }, }, }, { name: "MODL", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODW", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "MODWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 251}, // AX CX BX SP BP SI DI }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "ANDL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CMPL", argLen: 2, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPW", argLen: 2, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPB", argLen: 2, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPLconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPWconst", auxType: auxInt16, argLen: 1, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPBconst", auxType: auxInt8, argLen: 1, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "CMPLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPWload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPBload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPLconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPWconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "CMPBconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "UCOMISS", argLen: 2, asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "UCOMISD", argLen: 2, asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "TESTL", argLen: 2, commutative: true, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTW", argLen: 2, commutative: true, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTB", argLen: 2, commutative: true, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI {1, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTLconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTWconst", auxType: auxInt16, argLen: 1, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "TESTBconst", auxType: auxInt8, argLen: 1, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "SHLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SHRBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SARBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ADDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SUBLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MULLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "NEGL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "NOTL", argLen: 1, resultInArg0: true, asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSFL", argLen: 1, clobberFlags: true, asm: x86.ABSFL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSFW", argLen: 1, clobberFlags: true, asm: x86.ABSFW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSRL", argLen: 1, clobberFlags: true, asm: x86.ABSRL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSRW", argLen: 1, clobberFlags: true, asm: x86.ABSRW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "BSWAPL", argLen: 1, resultInArg0: true, asm: x86.ABSWAPL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SQRTSD", argLen: 1, asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SQRTSS", argLen: 1, asm: x86.ASQRTSS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "SBBLcarrymask", argLen: 1, asm: x86.ASBBL, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETEQ", argLen: 1, asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETNE", argLen: 1, asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETL", argLen: 1, asm: x86.ASETLT, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETLE", argLen: 1, asm: x86.ASETLE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETG", argLen: 1, asm: x86.ASETGT, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGE", argLen: 1, asm: x86.ASETGE, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETB", argLen: 1, asm: x86.ASETCS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETBE", argLen: 1, asm: x86.ASETLS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETA", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETAE", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETO", argLen: 1, asm: x86.ASETOS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETEQF", argLen: 1, clobberFlags: true, asm: x86.ASETEQ, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 238}, // CX DX BX BP SI DI }, }, }, { name: "SETNEF", argLen: 1, clobberFlags: true, asm: x86.ASETNE, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 238}, // CX DX BX BP SI DI }, }, }, { name: "SETORD", argLen: 1, asm: x86.ASETPC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETNAN", argLen: 1, asm: x86.ASETPS, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGF", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "SETGEF", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLSX", argLen: 1, asm: x86.AMOVBLSX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLZX", argLen: 1, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLSX", argLen: 1, asm: x86.AMOVWLSX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLZX", argLen: 1, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: x86.AMOVL, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTTSD2SL", argLen: 1, asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTTSS2SL", argLen: 1, asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "CVTSL2SS", argLen: 1, asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSL2SD", argLen: 1, asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSD2SS", argLen: 1, asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "CVTSS2SD", argLen: 1, asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "PXOR", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "LEAL", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LEAL8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBLSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBLSX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWLSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWLSX, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "SUBLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "SUBLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ADDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ANDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "ORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "XORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVWloadidx2", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVLloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVBstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreidx2", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {2, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVBstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVWstoreconstidx2", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "MOVLstoreconstidx4", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 255}, // AX CX DX BX SP BP SI DI {0, 65791}, // AX CX DX BX SP BP SI DI SB }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "REPSTOSL", argLen: 4, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 2}, // CX {2, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4}, // DX {0, 255}, // AX CX DX BX SP BP SI DI }, clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI }, clobbers: 194, // CX SI DI }, }, { name: "REPMOVSL", argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI {2, 2}, // CX }, clobbers: 194, // CX SI DI }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 255}, // AX CX DX BX SP BP SI DI }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 1}, // AX }, clobbers: 65280, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // DX {1, 8}, // BX }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // CX {1, 4}, // DX }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 2}, // CX }, }, }, { name: "LoweredPanicExtendA", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // SI {1, 4}, // DX {2, 8}, // BX }, }, }, { name: "LoweredPanicExtendB", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // SI {1, 2}, // CX {2, 4}, // DX }, }, }, { name: "LoweredPanicExtendC", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // SI {1, 1}, // AX {2, 2}, // CX }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_ULT", argLen: 0, reg: regInfo{}, }, { name: "MOVSSconst1", auxType: auxFloat32, argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVSDconst1", auxType: auxFloat64, argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "MOVSSconst2", argLen: 1, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MOVSDconst2", argLen: 1, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSS", argLen: 2, resultInArg0: true, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSD", argLen: 2, resultInArg0: true, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSS", argLen: 2, resultInArg0: true, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSD", argLen: 2, resultInArg0: true, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: x86.AMOVSS, reg: regInfo{ outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: x86.AMOVSD, reg: regInfo{ outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDloadidx1", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSDloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSSstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSSstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSDstoreidx1", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVSDstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "ADDSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AADDSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ASUBSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.AMULSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSSloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSS, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSSloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSS, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSDloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSD, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSDloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, symEffect: SymRead, asm: x86.ADIVSD, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ADDQ", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULQconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AIMUL3Q, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULLconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: x86.AIMUL3L, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULLU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 4, // DX outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "MULQU", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 4, // DX outputs: []outputInfo{ {1, 0}, {0, 1}, // AX }, }, }, { name: "HMULQ", argLen: 2, clobberFlags: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULL", argLen: 2, clobberFlags: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULQU", argLen: 2, clobberFlags: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "HMULLU", argLen: 2, clobberFlags: true, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "AVGQU", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "DIVQ", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVL", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVW", auxType: auxBool, argLen: 2, clobberFlags: true, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVQU", argLen: 2, clobberFlags: true, asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVLU", argLen: 2, clobberFlags: true, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "DIVWU", argLen: 2, clobberFlags: true, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "NEGLflags", argLen: 1, resultInArg0: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQcarry", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADCQ", argLen: 3, commutative: true, resultInArg0: true, asm: x86.AADCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQconstcarry", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADCQconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: x86.AADCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQborrow", argLen: 2, resultInArg0: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SBBQ", argLen: 3, resultInArg0: true, asm: x86.ASBBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQconstborrow", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SBBQconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: x86.ASBBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MULQU2", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 4}, // DX {1, 1}, // AX }, }, }, { name: "DIVQU2", argLen: 3, clobberFlags: true, asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // DX {1, 1}, // AX {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 1}, // AX {1, 4}, // DX }, }, }, { name: "ANDQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQ", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodify", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQ", argLen: 2, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPL", argLen: 2, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPW", argLen: 2, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPB", argLen: 2, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPQconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPLconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPWconst", auxType: auxInt16, argLen: 1, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPBconst", auxType: auxInt8, argLen: 1, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBconstload", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQloadidx8", auxType: auxSymOff, argLen: 4, symEffect: SymRead, asm: x86.ACMPQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLloadidx4", auxType: auxSymOff, argLen: 4, symEffect: SymRead, asm: x86.ACMPL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWloadidx2", auxType: auxSymOff, argLen: 4, symEffect: SymRead, asm: x86.ACMPW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBloadidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymRead, asm: x86.ACMPB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQconstloadidx8", auxType: auxSymValAndOff, argLen: 3, symEffect: SymRead, asm: x86.ACMPQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPQconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLconstloadidx4", auxType: auxSymValAndOff, argLen: 3, symEffect: SymRead, asm: x86.ACMPL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPLconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWconstloadidx2", auxType: auxSymValAndOff, argLen: 3, symEffect: SymRead, asm: x86.ACMPW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPWconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "CMPBconstloadidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.ACMPB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "UCOMISS", argLen: 2, asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "UCOMISD", argLen: 2, asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "BTL", argLen: 2, asm: x86.ABTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTQ", argLen: 2, asm: x86.ABTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTCL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTSL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTLconst", auxType: auxInt8, argLen: 1, asm: x86.ABTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTQconst", auxType: auxInt8, argLen: 1, asm: x86.ABTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTCL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTCQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTRQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTSL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BTSQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTQ", argLen: 2, commutative: true, asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTL", argLen: 2, commutative: true, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTW", argLen: 2, commutative: true, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTB", argLen: 2, commutative: true, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTQconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTLconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTWconst", auxType: auxInt16, argLen: 1, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TESTBconst", auxType: auxInt8, argLen: 1, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRWconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARWconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRDQ", argLen: 3, resultInArg0: true, clobberFlags: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {2, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLDQ", argLen: 3, resultInArg0: true, clobberFlags: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {2, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORL", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORB", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLQconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLLconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLWconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ROLBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SUBQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.ASUBQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ORQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLloadidx4", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORLloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQloadidx1", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XORQloadidx8", auxType: auxSymOff, argLen: 4, resultInArg0: true, clobberFlags: true, symEffect: SymRead, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADDQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodify", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SUBLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.ASUBL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodifyidx1", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodifyidx4", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLmodifyidx8", auxType: auxSymOff, argLen: 4, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORQconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ADDLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AADDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AANDL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodifyidx1", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodifyidx4", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "XORLconstmodifyidx8", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, symEffect: SymRead | SymWrite, asm: x86.AXORL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "NEGQ", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "NEGL", argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "NOTQ", argLen: 1, resultInArg0: true, asm: x86.ANOTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "NOTL", argLen: 1, resultInArg0: true, asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSFQ", argLen: 1, asm: x86.ABSFQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSFL", argLen: 1, clobberFlags: true, asm: x86.ABSFL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSRQ", argLen: 1, asm: x86.ABSRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSRL", argLen: 1, clobberFlags: true, asm: x86.ABSRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQEQ", argLen: 3, resultInArg0: true, asm: x86.ACMOVQEQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQNE", argLen: 3, resultInArg0: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQLT", argLen: 3, resultInArg0: true, asm: x86.ACMOVQLT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGT", argLen: 3, resultInArg0: true, asm: x86.ACMOVQGT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQLE", argLen: 3, resultInArg0: true, asm: x86.ACMOVQLE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGE", argLen: 3, resultInArg0: true, asm: x86.ACMOVQGE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQLS", argLen: 3, resultInArg0: true, asm: x86.ACMOVQLS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQHI", argLen: 3, resultInArg0: true, asm: x86.ACMOVQHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQCC", argLen: 3, resultInArg0: true, asm: x86.ACMOVQCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQCS", argLen: 3, resultInArg0: true, asm: x86.ACMOVQCS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLEQ", argLen: 3, resultInArg0: true, asm: x86.ACMOVLEQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLNE", argLen: 3, resultInArg0: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLLT", argLen: 3, resultInArg0: true, asm: x86.ACMOVLLT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGT", argLen: 3, resultInArg0: true, asm: x86.ACMOVLGT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLLE", argLen: 3, resultInArg0: true, asm: x86.ACMOVLLE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGE", argLen: 3, resultInArg0: true, asm: x86.ACMOVLGE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLLS", argLen: 3, resultInArg0: true, asm: x86.ACMOVLLS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLHI", argLen: 3, resultInArg0: true, asm: x86.ACMOVLHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLCC", argLen: 3, resultInArg0: true, asm: x86.ACMOVLCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLCS", argLen: 3, resultInArg0: true, asm: x86.ACMOVLCS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWEQ", argLen: 3, resultInArg0: true, asm: x86.ACMOVWEQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWNE", argLen: 3, resultInArg0: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWLT", argLen: 3, resultInArg0: true, asm: x86.ACMOVWLT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGT", argLen: 3, resultInArg0: true, asm: x86.ACMOVWGT, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWLE", argLen: 3, resultInArg0: true, asm: x86.ACMOVWLE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGE", argLen: 3, resultInArg0: true, asm: x86.ACMOVWGE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWLS", argLen: 3, resultInArg0: true, asm: x86.ACMOVWLS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWHI", argLen: 3, resultInArg0: true, asm: x86.ACMOVWHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWCC", argLen: 3, resultInArg0: true, asm: x86.ACMOVWCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWCS", argLen: 3, resultInArg0: true, asm: x86.ACMOVWCS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQEQF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQNEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGTF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVQGEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVQCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLEQF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLNEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGTF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVLGEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVLCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWEQF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWNEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWNE, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGTF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWHI, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWGEF", argLen: 3, resultInArg0: true, asm: x86.ACMOVWCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSWAPQ", argLen: 1, resultInArg0: true, asm: x86.ABSWAPQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BSWAPL", argLen: 1, resultInArg0: true, asm: x86.ABSWAPL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "POPCNTQ", argLen: 1, clobberFlags: true, asm: x86.APOPCNTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "POPCNTL", argLen: 1, clobberFlags: true, asm: x86.APOPCNTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SQRTSD", argLen: 1, asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SQRTSS", argLen: 1, asm: x86.ASQRTSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "ROUNDSD", auxType: auxInt8, argLen: 1, asm: x86.AROUNDSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "VFMADD231SD", argLen: 3, resultInArg0: true, asm: x86.AVFMADD231SD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SBBQcarrymask", argLen: 1, asm: x86.ASBBQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SBBLcarrymask", argLen: 1, asm: x86.ASBBL, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETEQ", argLen: 1, asm: x86.ASETEQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETNE", argLen: 1, asm: x86.ASETNE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETL", argLen: 1, asm: x86.ASETLT, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETLE", argLen: 1, asm: x86.ASETLE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETG", argLen: 1, asm: x86.ASETGT, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETGE", argLen: 1, asm: x86.ASETGE, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETB", argLen: 1, asm: x86.ASETCS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETBE", argLen: 1, asm: x86.ASETLS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETA", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETAE", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETO", argLen: 1, asm: x86.ASETOS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETEQstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETEQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETNEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETNE, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETLstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETLT, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETLEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETLE, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETGstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETGT, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETGEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETGE, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETCS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETBEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETLS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETAstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETHI, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETAEstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.ASETCC, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SETEQF", argLen: 1, clobberFlags: true, asm: x86.ASETEQ, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETNEF", argLen: 1, clobberFlags: true, asm: x86.ASETNE, reg: regInfo{ clobbers: 1, // AX outputs: []outputInfo{ {0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETORD", argLen: 1, asm: x86.ASETPC, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETNAN", argLen: 1, asm: x86.ASETPS, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETGF", argLen: 1, asm: x86.ASETHI, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SETGEF", argLen: 1, asm: x86.ASETCC, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBQSX", argLen: 1, asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBQZX", argLen: 1, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWQSX", argLen: 1, asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWQZX", argLen: 1, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLQSX", argLen: 1, asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLQZX", argLen: 1, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: x86.AMOVL, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: x86.AMOVQ, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSD2SL", argLen: 1, asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSD2SQ", argLen: 1, asm: x86.ACVTTSD2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSS2SL", argLen: 1, asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTTSS2SQ", argLen: 1, asm: x86.ACVTTSS2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CVTSL2SS", argLen: 1, asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSL2SD", argLen: 1, asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSQ2SS", argLen: 1, asm: x86.ACVTSQ2SS, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSQ2SD", argLen: 1, asm: x86.ACVTSQ2SD, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSD2SS", argLen: 1, asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "CVTSS2SD", argLen: 1, asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVQi2f", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVQf2i", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLi2f", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVLf2i", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "PXOR", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "LEAQ", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: x86.ALEAQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: x86.ALEAL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: x86.ALEAW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, asm: x86.ALEAQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, asm: x86.ALEAL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW1", auxType: auxSymOff, argLen: 2, commutative: true, symEffect: SymAddr, asm: x86.ALEAW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAQ, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAL, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW2", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAQ, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW4", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAW, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAQ8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAL8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LEAW8", auxType: auxSymOff, argLen: 2, symEffect: SymAddr, asm: x86.ALEAW, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBQSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWQSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLQSXload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVOload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVOstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, { name: "MOVBloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBLZX, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVWLZX, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVWloadidx2", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVWLZX, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreidx2", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVOstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVB, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVWstoreconstidx2", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVLstoreconstidx4", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, commutative: true, symEffect: SymWrite, asm: x86.AMOVQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVQstoreconstidx8", auxType: auxSymValAndOff, argLen: 3, symEffect: SymWrite, asm: x86.AMOVQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI }, clobbers: 128, // DI }, }, { name: "REPSTOSQ", argLen: 4, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 2}, // CX {2, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4}, // DX {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI }, clobbers: 65728, // SI DI X0 }, }, { name: "REPMOVSQ", argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI {2, 2}, // CX }, clobbers: 194, // CX SI DI }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4}, // DX }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 879}, // AX CX DX BX BP SI R8 R9 }, clobbers: 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, { name: "LoweredHasCPUFeature", auxType: auxSym, argLen: 0, rematerializeable: true, symEffect: SymNone, reg: regInfo{ outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // DX {1, 8}, // BX }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // CX {1, 4}, // DX }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 2}, // CX }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_ULT", argLen: 0, reg: regInfo{}, }, { name: "MOVBatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVLatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVQatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XCHGB", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXCHGB, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XCHGL", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXCHGL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XCHGQ", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXCHGQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XADDLlock", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXADDL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "XADDQlock", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AXADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "AddTupleFirst32", argLen: 2, reg: regInfo{}, }, { name: "AddTupleFirst64", argLen: 2, reg: regInfo{}, }, { name: "CMPXCHGLlock", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.ACMPXCHGL, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // AX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPXCHGQlock", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.ACMPXCHGQ, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // AX {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, clobbers: 1, // AX outputs: []outputInfo{ {1, 0}, {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDBlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AANDB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDLlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORBlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AORB, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ORLlock", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "PrefetchT0", argLen: 2, hasSideEffects: true, asm: x86.APREFETCHT0, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "PrefetchNTA", argLen: 2, hasSideEffects: true, asm: x86.APREFETCHNTA, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "ANDNQ", argLen: 2, clobberFlags: true, asm: x86.AANDNQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ANDNL", argLen: 2, clobberFlags: true, asm: x86.AANDNL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSIQ", argLen: 1, clobberFlags: true, asm: x86.ABLSIQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSIL", argLen: 1, clobberFlags: true, asm: x86.ABLSIL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSMSKQ", argLen: 1, clobberFlags: true, asm: x86.ABLSMSKQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSMSKL", argLen: 1, clobberFlags: true, asm: x86.ABLSMSKL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSRQ", argLen: 1, clobberFlags: true, asm: x86.ABLSRQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "BLSRL", argLen: 1, clobberFlags: true, asm: x86.ABLSRL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TZCNTQ", argLen: 1, clobberFlags: true, asm: x86.ATZCNTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "TZCNTL", argLen: 1, clobberFlags: true, asm: x86.ATZCNTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LZCNTQ", argLen: 1, clobberFlags: true, asm: x86.ALZCNTQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "LZCNTL", argLen: 1, clobberFlags: true, asm: x86.ALZCNTL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVBEW, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBEL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBELstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVBEL, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEQload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: x86.AMOVBEQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEQstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: x86.AMOVBEQ, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBEL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBELloadidx4", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVBEL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBELloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVBEL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEQloadidx1", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: x86.AMOVBEQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEQloadidx8", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: x86.AMOVBEQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "MOVBEWstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVBEW, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEWstoreidx2", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEW, scale: 2, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVBEL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELstoreidx4", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBELstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEQstoreidx1", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: x86.AMOVBEQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "MOVBEQstoreidx8", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: x86.AMOVBEQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, { name: "SARXQ", argLen: 2, asm: x86.ASARXQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXL", argLen: 2, asm: x86.ASARXL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQ", argLen: 2, asm: x86.ASHLXQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXL", argLen: 2, asm: x86.ASHLXL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQ", argLen: 2, asm: x86.ASHRXQ, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXL", argLen: 2, asm: x86.ASHRXL, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQload", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, reg: regInfo{ inputs: []inputInfo{ {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLloadidx4", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXLloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXQloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SARXQloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASARXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLloadidx4", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXLloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHLXQloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHLXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLloadidx4", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 4, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXLloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXL, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQloadidx1", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, scale: 1, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "SHRXQloadidx8", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymRead, asm: x86.ASHRXQ, scale: 8, reg: regInfo{ inputs: []inputInfo{ {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUB", argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSB", argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBconst", auxType: auxInt32, argLen: 1, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: arm.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "HMUL", argLen: 2, commutative: true, asm: arm.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "HMULU", argLen: 2, commutative: true, asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CALLudiv", argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 1}, // R0 }, clobbers: 20492, // R2 R3 R12 R14 outputs: []outputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "ADDS", argLen: 2, commutative: true, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSconst", auxType: auxInt32, argLen: 1, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADC", argLen: 3, commutative: true, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCconst", auxType: auxInt32, argLen: 2, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBS", argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSconst", auxType: auxInt32, argLen: 1, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSconst", auxType: auxInt32, argLen: 1, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBC", argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCconst", auxType: auxInt32, argLen: 2, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCconst", auxType: auxInt32, argLen: 2, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULLU", argLen: 2, commutative: true, asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULA", argLen: 3, asm: arm.AMULA, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULS", argLen: 3, asm: arm.AMULS, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: arm.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: arm.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SUBF", argLen: 2, asm: arm.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SUBD", argLen: 2, asm: arm.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: arm.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: arm.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "NMULF", argLen: 2, commutative: true, asm: arm.ANMULF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "NMULD", argLen: 2, commutative: true, asm: arm.ANMULD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "DIVF", argLen: 2, asm: arm.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "DIVD", argLen: 2, asm: arm.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULAF", argLen: 3, resultInArg0: true, asm: arm.AMULAF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULAD", argLen: 3, resultInArg0: true, asm: arm.AMULAD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULSF", argLen: 3, resultInArg0: true, asm: arm.AMULSF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULSD", argLen: 3, resultInArg0: true, asm: arm.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMULAD", argLen: 3, resultInArg0: true, asm: arm.AFMULAD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDconst", auxType: auxInt32, argLen: 1, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORconst", auxType: auxInt32, argLen: 1, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORconst", auxType: auxInt32, argLen: 1, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BIC", argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICconst", auxType: auxInt32, argLen: 1, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BFX", auxType: auxInt32, argLen: 1, asm: arm.ABFX, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BFXU", auxType: auxInt32, argLen: 1, asm: arm.ABFXU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVN", argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "NEGF", argLen: 1, asm: arm.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "NEGD", argLen: 1, asm: arm.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SQRTD", argLen: 1, asm: arm.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SQRTF", argLen: 1, asm: arm.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ABSD", argLen: 1, asm: arm.AABSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CLZ", argLen: 1, asm: arm.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "REV", argLen: 1, asm: arm.AREV, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "REV16", argLen: 1, asm: arm.AREV16, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RBIT", argLen: 1, asm: arm.ARBIT, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SLL", argLen: 2, asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SLLconst", auxType: auxInt32, argLen: 1, asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRL", argLen: 2, asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRLconst", auxType: auxInt32, argLen: 1, asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRA", argLen: 2, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRAconst", auxType: auxInt32, argLen: 1, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRR", argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRRconst", auxType: auxInt32, argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRR", auxType: auxInt32, argLen: 2, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftLL", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRL", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRA", auxType: auxInt32, argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftLL", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRL", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRA", auxType: auxInt32, argLen: 3, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftLLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDshiftRAreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftLLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRAreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftLLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBshiftRAreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftLLreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRLreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ANDshiftRAreg", argLen: 3, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftLLreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRLreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ORshiftRAreg", argLen: 3, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftLLreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRLreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "XORshiftRAreg", argLen: 3, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftLLreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRLreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "BICshiftRAreg", argLen: 3, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftLLreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRLreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MVNshiftRAreg", argLen: 2, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftLLreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRLreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADCshiftRAreg", argLen: 4, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftLLreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRLreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SBCshiftRAreg", argLen: 4, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftLLreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRLreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSCshiftRAreg", argLen: 4, asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftLLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRLreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "ADDSshiftRAreg", argLen: 3, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftLLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRLreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBSshiftRAreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftLLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRLreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "RSBSshiftRAreg", argLen: 3, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {1, 0}, {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMP", argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPconst", auxType: auxInt32, argLen: 1, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMN", argLen: 2, commutative: true, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNconst", auxType: auxInt32, argLen: 1, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TST", argLen: 2, commutative: true, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTconst", auxType: auxInt32, argLen: 1, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQ", argLen: 2, commutative: true, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQconst", auxType: auxInt32, argLen: 1, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPF", argLen: 2, asm: arm.ACMPF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPD", argLen: 2, asm: arm.ACMPD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMNshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TSTshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQshiftLL", auxType: auxInt32, argLen: 2, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQshiftRL", auxType: auxInt32, argLen: 2, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "TEQshiftRA", auxType: auxInt32, argLen: 2, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "CMPshiftLLreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMPshiftRLreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMPshiftRAreg", argLen: 3, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMNshiftLLreg", argLen: 3, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMNshiftRLreg", argLen: 3, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMNshiftRAreg", argLen: 3, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TSTshiftLLreg", argLen: 3, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TSTshiftRLreg", argLen: 3, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TSTshiftRAreg", argLen: 3, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TEQshiftLLreg", argLen: 3, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TEQshiftRLreg", argLen: 3, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "TEQshiftRAreg", argLen: 3, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMPF0", argLen: 1, asm: arm.ACMPF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMPD0", argLen: 1, asm: arm.ACMPD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: arm.AMOVW, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4294975488}, // SP SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWloadshiftLL", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWloadshiftRL", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWloadshiftRA", auxType: auxInt32, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBUloadidx", argLen: 3, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBloadidx", argLen: 3, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHUloadidx", argLen: 3, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstoreshiftLL", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstoreshiftRL", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVWstoreshiftRA", auxType: auxInt32, argLen: 4, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { name: "MOVBreg", argLen: 1, asm: arm.AMOVBS, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVBUreg", argLen: 1, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHreg", argLen: 1, asm: arm.AMOVHS, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVHUreg", argLen: 1, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWreg", argLen: 1, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVWF", argLen: 1, asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWD", argLen: 1, asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWUF", argLen: 1, asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWUD", argLen: 1, asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVFW", argLen: 1, asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVDW", argLen: 1, asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFWU", argLen: 1, asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVDWU", argLen: 1, asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, clobbers: 2147483648, // F15 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MOVFD", argLen: 1, asm: arm.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDF", argLen: 1, asm: arm.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CMOVWHSconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CMOVWLSconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SRAcond", argLen: 3, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 128}, // R7 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 }, clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LessEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "GreaterEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 1}, // R0 }, clobbers: 20482, // R1 R12 R14 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 }, clobbers: 20487, // R0 R1 R2 R12 R14 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2, // R1 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 6, // R1 R2 }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 128}, // R7 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "LoweredPanicExtendA", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 4}, // R2 {2, 8}, // R3 }, }, }, { name: "LoweredPanicExtendB", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 2}, // R1 {2, 4}, // R2 }, }, }, { name: "LoweredPanicExtendC", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 1}, // R0 {2, 2}, // R1 }, }, }, { name: "FlagConstant", auxType: auxFlagConstant, argLen: 0, reg: regInfo{}, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "ADCSflags", argLen: 3, commutative: true, asm: arm64.AADCS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADCzerocarry", argLen: 1, asm: arm64.AADC, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDconst", auxType: auxInt64, argLen: 1, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDSconstflags", auxType: auxInt64, argLen: 1, asm: arm64.AADDS, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {1, 0}, {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDSflags", argLen: 2, commutative: true, asm: arm64.AADDS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUB", argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBconst", auxType: auxInt64, argLen: 1, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SBCSflags", argLen: 3, asm: arm64.ASBCS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBSflags", argLen: 2, asm: arm64.ASUBS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {1, 0}, {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: arm64.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MULW", argLen: 2, commutative: true, asm: arm64.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MNEG", argLen: 2, commutative: true, asm: arm64.AMNEG, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MNEGW", argLen: 2, commutative: true, asm: arm64.AMNEGW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MULH", argLen: 2, commutative: true, asm: arm64.ASMULH, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMULH", argLen: 2, commutative: true, asm: arm64.AUMULH, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MULL", argLen: 2, commutative: true, asm: arm64.ASMULL, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMULL", argLen: 2, commutative: true, asm: arm64.AUMULL, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "DIV", argLen: 2, asm: arm64.ASDIV, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UDIV", argLen: 2, asm: arm64.AUDIV, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "DIVW", argLen: 2, asm: arm64.ASDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UDIVW", argLen: 2, asm: arm64.AUDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOD", argLen: 2, asm: arm64.AREM, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMOD", argLen: 2, asm: arm64.AUREM, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MODW", argLen: 2, asm: arm64.AREMW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMODW", argLen: 2, asm: arm64.AUREMW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: arm64.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FADDD", argLen: 2, commutative: true, asm: arm64.AFADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBS", argLen: 2, asm: arm64.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBD", argLen: 2, asm: arm64.AFSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: arm64.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULD", argLen: 2, commutative: true, asm: arm64.AFMULD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMULS", argLen: 2, commutative: true, asm: arm64.AFNMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMULD", argLen: 2, commutative: true, asm: arm64.AFNMULD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVS", argLen: 2, asm: arm64.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVD", argLen: 2, asm: arm64.AFDIVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BIC", argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EON", argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORN", argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredMuluhilo", argLen: 2, resultNotInArgs: true, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVN", argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEG", argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGSflags", argLen: 1, asm: arm64.ANEGS, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {1, 0}, {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NGCzerocarry", argLen: 1, asm: arm64.ANGC, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FABSD", argLen: 1, asm: arm64.AFABSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGS", argLen: 1, asm: arm64.AFNEGS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGD", argLen: 1, asm: arm64.AFNEGD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTD", argLen: 1, asm: arm64.AFSQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTS", argLen: 1, asm: arm64.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "REV", argLen: 1, asm: arm64.AREV, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "REVW", argLen: 1, asm: arm64.AREVW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "REV16", argLen: 1, asm: arm64.AREV16, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "REV16W", argLen: 1, asm: arm64.AREV16W, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RBIT", argLen: 1, asm: arm64.ARBIT, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RBITW", argLen: 1, asm: arm64.ARBITW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CLZ", argLen: 1, asm: arm64.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CLZW", argLen: 1, asm: arm64.ACLZW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "VCNT", argLen: 1, asm: arm64.AVCNT, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "VUADDLV", argLen: 1, asm: arm64.AVUADDLV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDS", argLen: 3, asm: arm64.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDD", argLen: 3, asm: arm64.AFMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDS", argLen: 3, asm: arm64.AFNMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDD", argLen: 3, asm: arm64.AFNMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBS", argLen: 3, asm: arm64.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBD", argLen: 3, asm: arm64.AFMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBS", argLen: 3, asm: arm64.AFNMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBD", argLen: 3, asm: arm64.AFNMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MADD", argLen: 3, asm: arm64.AMADD, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MADDW", argLen: 3, asm: arm64.AMADDW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MSUB", argLen: 3, asm: arm64.AMSUB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MSUBW", argLen: 3, asm: arm64.AMSUBW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SLL", argLen: 2, asm: arm64.ALSL, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SLLconst", auxType: auxInt64, argLen: 1, asm: arm64.ALSL, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRL", argLen: 2, asm: arm64.ALSR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRLconst", auxType: auxInt64, argLen: 1, asm: arm64.ALSR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRA", argLen: 2, asm: arm64.AASR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SRAconst", auxType: auxInt64, argLen: 1, asm: arm64.AASR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ROR", argLen: 2, asm: arm64.AROR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RORW", argLen: 2, asm: arm64.ARORW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RORconst", auxType: auxInt64, argLen: 1, asm: arm64.AROR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "RORWconst", auxType: auxInt64, argLen: 1, asm: arm64.ARORW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EXTRconst", auxType: auxInt64, argLen: 2, asm: arm64.AEXTR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EXTRWconst", auxType: auxInt64, argLen: 2, asm: arm64.AEXTRW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CMP", argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPconst", auxType: auxInt64, argLen: 1, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPW", argLen: 2, asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMN", argLen: 2, commutative: true, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNconst", auxType: auxInt64, argLen: 1, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNW", argLen: 2, commutative: true, asm: arm64.ACMNW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNWconst", auxType: auxInt32, argLen: 1, asm: arm64.ACMNW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TST", argLen: 2, commutative: true, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTconst", auxType: auxInt64, argLen: 1, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTW", argLen: 2, commutative: true, asm: arm64.ATSTW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTWconst", auxType: auxInt32, argLen: 1, asm: arm64.ATSTW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "FCMPS", argLen: 2, asm: arm64.AFCMPS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCMPD", argLen: 2, asm: arm64.AFCMPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCMPS0", argLen: 1, asm: arm64.AFCMPS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCMPD0", argLen: 1, asm: arm64.AFCMPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MVNshiftLL", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVNshiftRL", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVNshiftRA", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MVNshiftRO", auxType: auxInt64, argLen: 1, asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGshiftLL", auxType: auxInt64, argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGshiftRL", auxType: auxInt64, argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NEGshiftRA", auxType: auxInt64, argLen: 1, asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ADDshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SUBshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ANDshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "XORshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BICshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "EONshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "ORNshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CMPshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMPshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "CMNshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftLL", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftRL", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftRA", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "TSTshiftRO", auxType: auxInt64, argLen: 2, asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "BFI", auxType: auxARM64BitField, argLen: 2, resultInArg0: true, asm: arm64.ABFI, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "BFXIL", auxType: auxARM64BitField, argLen: 2, resultInArg0: true, asm: arm64.ABFXIL, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SBFIZ", auxType: auxARM64BitField, argLen: 1, asm: arm64.ASBFIZ, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SBFX", auxType: auxARM64BitField, argLen: 1, asm: arm64.ASBFX, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UBFIZ", auxType: auxARM64BitField, argLen: 1, asm: arm64.AUBFIZ, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UBFX", auxType: auxARM64BitField, argLen: 1, asm: arm64.AUBFX, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: arm64.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm64.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm64.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037928517632}, // SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDloadidx", argLen: 3, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUloadidx", argLen: 3, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUloadidx", argLen: 3, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBloadidx", argLen: 3, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBUloadidx", argLen: 3, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSloadidx", argLen: 3, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDloadidx", argLen: 3, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVHloadidx2", argLen: 3, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUloadidx2", argLen: 3, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWloadidx4", argLen: 3, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUloadidx4", argLen: 3, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDloadidx8", argLen: 3, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSloadidx4", argLen: 3, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDloadidx8", argLen: 3, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "STP", auxType: auxSymOff, argLen: 4, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.ASTP, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstoreidx", argLen: 4, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVSstoreidx", argLen: 4, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstoreidx", argLen: 4, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVHstoreidx2", argLen: 4, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstoreidx4", argLen: 4, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstoreidx8", argLen: 4, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVSstoreidx4", argLen: 4, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstoreidx8", argLen: 4, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVQstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: arm64.ASTP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVBstorezeroidx", argLen: 3, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstorezeroidx", argLen: 3, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstorezeroidx", argLen: 3, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstorezeroidx", argLen: 3, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVHstorezeroidx2", argLen: 3, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVWstorezeroidx4", argLen: 3, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "MOVDstorezeroidx8", argLen: 3, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "FMOVDgpfp", argLen: 1, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDfpgp", argLen: 1, asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FMOVSgpfp", argLen: 1, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVSfpgp", argLen: 1, asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBreg", argLen: 1, asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVBUreg", argLen: 1, asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHreg", argLen: 1, asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVHUreg", argLen: 1, asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWreg", argLen: 1, asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVWUreg", argLen: 1, asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDreg", argLen: 1, asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "MOVDnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "SCVTFWS", argLen: 1, asm: arm64.ASCVTFWS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SCVTFWD", argLen: 1, asm: arm64.ASCVTFWD, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFWS", argLen: 1, asm: arm64.AUCVTFWS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFWD", argLen: 1, asm: arm64.AUCVTFWD, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SCVTFS", argLen: 1, asm: arm64.ASCVTFS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SCVTFD", argLen: 1, asm: arm64.ASCVTFD, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFS", argLen: 1, asm: arm64.AUCVTFS, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "UCVTFD", argLen: 1, asm: arm64.AUCVTFD, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTZSSW", argLen: 1, asm: arm64.AFCVTZSSW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZSDW", argLen: 1, asm: arm64.AFCVTZSDW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUSW", argLen: 1, asm: arm64.AFCVTZUSW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUDW", argLen: 1, asm: arm64.AFCVTZUDW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZSS", argLen: 1, asm: arm64.AFCVTZSS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZSD", argLen: 1, asm: arm64.AFCVTZSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUS", argLen: 1, asm: arm64.AFCVTZUS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTZUD", argLen: 1, asm: arm64.AFCVTZUD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FCVTSD", argLen: 1, asm: arm64.AFCVTSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTDS", argLen: 1, asm: arm64.AFCVTDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTAD", argLen: 1, asm: arm64.AFRINTAD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTMD", argLen: 1, asm: arm64.AFRINTMD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTND", argLen: 1, asm: arm64.AFRINTND, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTPD", argLen: 1, asm: arm64.AFRINTPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FRINTZD", argLen: 1, asm: arm64.AFRINTZD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CSEL", auxType: auxCCop, argLen: 3, asm: arm64.ACSEL, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSEL0", auxType: auxCCop, argLen: 2, asm: arm64.ACSEL, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSINC", auxType: auxCCop, argLen: 3, asm: arm64.ACSINC, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSINV", auxType: auxCCop, argLen: 3, asm: arm64.ACSINV, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSNEG", auxType: auxCCop, argLen: 3, asm: arm64.ACSNEG, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CSETM", auxType: auxCCop, argLen: 1, asm: arm64.ACSETM, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 67108864}, // R26 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP }, clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterThanU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqualU", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LessEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "GreaterEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotLessThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotLessEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotGreaterThanF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "NotGreaterEqualF", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 }, clobbers: 538116096, // R16 R17 R20 R30 }, }, { name: "LoweredZero", argLen: 3, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 65536}, // R16 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, clobbers: 65536, // R16 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 2097152}, // R21 {1, 1048576}, // R20 }, clobbers: 607322112, // R16 R17 R20 R21 R26 R30 }, }, { name: "LoweredMove", argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 131072}, // R17 {1, 65536}, // R16 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, clobbers: 196608, // R16 R17 }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 67108864}, // R26 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "FlagConstant", auxType: auxFlagConstant, argLen: 0, reg: regInfo{}, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LDAR", argLen: 2, faultOnNilArg0: true, asm: arm64.ALDAR, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LDARB", argLen: 2, faultOnNilArg0: true, asm: arm64.ALDARB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LDARW", argLen: 2, faultOnNilArg0: true, asm: arm64.ALDARW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "STLRB", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: arm64.ASTLRB, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "STLR", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: arm64.ASTLR, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "STLRW", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: arm64.ASTLRW, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange64Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicExchange32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd64Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAdd32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas64Variant", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicCas32Variant", argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd8", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr8", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd8Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicAnd32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr8Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredAtomicOr32Variant", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, clobbers: 9223372035244359680, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "PRFM", auxType: auxInt64, argLen: 2, hasSideEffects: true, asm: arm64.APRFM, reg: regInfo{ inputs: []inputInfo{ {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { name: "DMB", auxType: auxInt64, argLen: 1, hasSideEffects: true, asm: arm64.ADMB, reg: regInfo{}, }, { name: "ADDV", argLen: 2, commutative: true, asm: loong64.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ADDVconst", auxType: auxInt64, argLen: 1, asm: loong64.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 1072693244}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SUBV", argLen: 2, asm: loong64.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SUBVconst", auxType: auxInt64, argLen: 1, asm: loong64.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MULV", argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 196608, // R17 R18 outputs: []outputInfo{ {0, 65536}, // R17 {1, 131072}, // R18 }, }, }, { name: "MULVU", argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 196608, // R17 R18 outputs: []outputInfo{ {0, 65536}, // R17 {1, 131072}, // R18 }, }, }, { name: "DIVV", argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 196608, // R17 R18 outputs: []outputInfo{ {0, 65536}, // R17 {1, 131072}, // R18 }, }, }, { name: "DIVVU", argLen: 2, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 196608, // R17 R18 outputs: []outputInfo{ {0, 65536}, // R17 {1, 131072}, // R18 }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: loong64.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: loong64.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBF", argLen: 2, asm: loong64.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBD", argLen: 2, asm: loong64.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: loong64.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: loong64.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVF", argLen: 2, asm: loong64.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVD", argLen: 2, asm: loong64.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: loong64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, asm: loong64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: loong64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: loong64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: loong64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: loong64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: loong64.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "NORconst", auxType: auxInt64, argLen: 1, asm: loong64.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "NEGV", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "NEGF", argLen: 1, asm: loong64.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "NEGD", argLen: 1, asm: loong64.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTD", argLen: 1, asm: loong64.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTF", argLen: 1, asm: loong64.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SLLV", argLen: 2, asm: loong64.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SLLVconst", auxType: auxInt64, argLen: 1, asm: loong64.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRLV", argLen: 2, asm: loong64.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRLVconst", auxType: auxInt64, argLen: 1, asm: loong64.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRAV", argLen: 2, asm: loong64.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SRAVconst", auxType: auxInt64, argLen: 1, asm: loong64.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SGT", argLen: 2, asm: loong64.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SGTconst", auxType: auxInt64, argLen: 1, asm: loong64.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SGTU", argLen: 2, asm: loong64.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "SGTUconst", auxType: auxInt64, argLen: 1, asm: loong64.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "CMPEQF", argLen: 2, asm: loong64.ACMPEQF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPEQD", argLen: 2, asm: loong64.ACMPEQD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGEF", argLen: 2, asm: loong64.ACMPGEF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGED", argLen: 2, asm: loong64.ACMPGED, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTF", argLen: 2, asm: loong64.ACMPGTF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTD", argLen: 2, asm: loong64.ACMPGTD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: loong64.AMOVV, reg: regInfo{ outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVFconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: loong64.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: loong64.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018427387908}, // SP SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVVload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVVstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVVstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "MOVBreg", argLen: 1, asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVBUreg", argLen: 1, asm: loong64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHreg", argLen: 1, asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVHUreg", argLen: 1, asm: loong64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWreg", argLen: 1, asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWUreg", argLen: 1, asm: loong64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVVreg", argLen: 1, asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVVnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "MOVWF", argLen: 1, asm: loong64.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVWD", argLen: 1, asm: loong64.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVF", argLen: 1, asm: loong64.AMOVVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVD", argLen: 1, asm: loong64.AMOVVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFW", argLen: 1, asm: loong64.ATRUNCFW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDW", argLen: 1, asm: loong64.ATRUNCDW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFV", argLen: 1, asm: loong64.ATRUNCFV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDV", argLen: 1, asm: loong64.ATRUNCDV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVFD", argLen: 1, asm: loong64.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDF", argLen: 1, asm: loong64.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 268435456}, // R29 {0, 1070596092}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 262146, // R1 R19 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 524288}, // R20 {1, 262144}, // R19 }, clobbers: 786434, // R1 R19 R20 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 262144}, // R19 {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 262144, // R19 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 8}, // R4 {1, 262144}, // R19 {2, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, clobbers: 262152, // R4 R19 }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicLoad64", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStore64", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStorezero32", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicStorezero64", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAddconst32", auxType: auxInt32, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicAddconst64", auxType: auxInt64, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {2, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "FPFlagTrue", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "FPFlagFalse", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 268435456}, // R29 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 67108864}, // R27 {1, 134217728}, // R28 }, clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 65536}, // R17 {1, 8}, // R4 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 131072}, // R18 {1, 65536}, // R17 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 262144}, // R19 {1, 131072}, // R18 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: mips.AADDU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, asm: mips.AADDU, reg: regInfo{ inputs: []inputInfo{ {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SUB", argLen: 2, asm: mips.ASUBU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, asm: mips.ASUBU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: mips.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, clobbers: 105553116266496, // HI LO outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MULT", argLen: 2, commutative: true, asm: mips.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "MULTU", argLen: 2, commutative: true, asm: mips.AMULU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "DIV", argLen: 2, asm: mips.ADIV, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "DIVU", argLen: 2, asm: mips.ADIVU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 35184372088832}, // HI {1, 70368744177664}, // LO }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: mips.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: mips.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SUBF", argLen: 2, asm: mips.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SUBD", argLen: 2, asm: mips.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: mips.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: mips.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "DIVF", argLen: 2, asm: mips.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "DIVD", argLen: 2, asm: mips.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "ANDconst", auxType: auxInt32, argLen: 1, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "ORconst", auxType: auxInt32, argLen: 1, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "XORconst", auxType: auxInt32, argLen: 1, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NORconst", auxType: auxInt32, argLen: 1, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NEG", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "NEGF", argLen: 1, asm: mips.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "NEGD", argLen: 1, asm: mips.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SQRTD", argLen: 1, asm: mips.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SQRTF", argLen: 1, asm: mips.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "SLL", argLen: 2, asm: mips.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SLLconst", auxType: auxInt32, argLen: 1, asm: mips.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRL", argLen: 2, asm: mips.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRLconst", auxType: auxInt32, argLen: 1, asm: mips.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRA", argLen: 2, asm: mips.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SRAconst", auxType: auxInt32, argLen: 1, asm: mips.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CLZ", argLen: 1, asm: mips.ACLZ, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGT", argLen: 2, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTconst", auxType: auxInt32, argLen: 1, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTzero", argLen: 1, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTU", argLen: 2, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTUconst", auxType: auxInt32, argLen: 1, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "SGTUzero", argLen: 1, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CMPEQF", argLen: 2, asm: mips.ACMPEQF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPEQD", argLen: 2, asm: mips.ACMPEQD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGEF", argLen: 2, asm: mips.ACMPGEF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGED", argLen: 2, asm: mips.ACMPGED, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGTF", argLen: 2, asm: mips.ACMPGTF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CMPGTD", argLen: 2, asm: mips.ACMPGTD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVWconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: mips.AMOVW, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVFconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: mips.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: mips.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVWaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 140737555464192}, // SP SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "MOVBreg", argLen: 1, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVBUreg", argLen: 1, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHreg", argLen: 1, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVHUreg", argLen: 1, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWreg", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CMOVZ", argLen: 3, resultInArg0: true, asm: mips.ACMOVZ, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "CMOVZzero", argLen: 2, resultInArg0: true, asm: mips.ACMOVZ, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "MOVWF", argLen: 1, asm: mips.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVWD", argLen: 1, asm: mips.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "TRUNCFW", argLen: 1, asm: mips.ATRUNCFW, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "TRUNCDW", argLen: 1, asm: mips.ATRUNCDW, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVFD", argLen: 1, asm: mips.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "MOVDF", argLen: 1, asm: mips.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4194304}, // R22 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 }, clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicStorezero", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicExchange", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicAdd", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicAddconst", auxType: auxInt32, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicCas", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredAtomicAnd", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredAtomicOr", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, }, }, { name: "LoweredZero", auxType: auxInt32, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, clobbers: 2, // R1 }, }, { name: "LoweredMove", auxType: auxInt32, argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, clobbers: 6, // R1 R2 }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, }, }, { name: "FPFlagTrue", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "FPFlagFalse", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4194304}, // R22 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 8}, // R3 {1, 16}, // R4 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicExtendA", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 8}, // R3 {2, 16}, // R4 }, }, }, { name: "LoweredPanicExtendB", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 4}, // R2 {2, 8}, // R3 }, }, }, { name: "LoweredPanicExtendC", auxType: auxInt64, argLen: 4, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 2}, // R1 {2, 4}, // R2 }, }, }, { name: "ADDV", argLen: 2, commutative: true, asm: mips.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "ADDVconst", auxType: auxInt64, argLen: 1, asm: mips.AADDVU, reg: regInfo{ inputs: []inputInfo{ {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SUBV", argLen: 2, asm: mips.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SUBVconst", auxType: auxInt64, argLen: 1, asm: mips.ASUBVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MULV", argLen: 2, commutative: true, asm: mips.AMULV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "MULVU", argLen: 2, commutative: true, asm: mips.AMULVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "DIVV", argLen: 2, asm: mips.ADIVV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "DIVVU", argLen: 2, asm: mips.ADIVVU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 1152921504606846976}, // HI {1, 2305843009213693952}, // LO }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: mips.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: mips.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBF", argLen: 2, asm: mips.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SUBD", argLen: 2, asm: mips.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: mips.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: mips.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVF", argLen: 2, asm: mips.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "DIVD", argLen: 2, asm: mips.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NORconst", auxType: auxInt64, argLen: 1, asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NEGV", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "NEGF", argLen: 1, asm: mips.ANEGF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "NEGD", argLen: 1, asm: mips.ANEGD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTD", argLen: 1, asm: mips.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SQRTF", argLen: 1, asm: mips.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "SLLV", argLen: 2, asm: mips.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SLLVconst", auxType: auxInt64, argLen: 1, asm: mips.ASLLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRLV", argLen: 2, asm: mips.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRLVconst", auxType: auxInt64, argLen: 1, asm: mips.ASRLV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRAV", argLen: 2, asm: mips.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SRAVconst", auxType: auxInt64, argLen: 1, asm: mips.ASRAV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGT", argLen: 2, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGTconst", auxType: auxInt64, argLen: 1, asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGTU", argLen: 2, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "SGTUconst", auxType: auxInt64, argLen: 1, asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "CMPEQF", argLen: 2, asm: mips.ACMPEQF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPEQD", argLen: 2, asm: mips.ACMPEQD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGEF", argLen: 2, asm: mips.ACMPGEF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGED", argLen: 2, asm: mips.ACMPGED, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTF", argLen: 2, asm: mips.ACMPGTF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CMPGTD", argLen: 2, asm: mips.ACMPGTD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: mips.AMOVV, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVFconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: mips.AMOVF, reg: regInfo{ outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: mips.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018460942336}, // SP SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVVstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVVstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "MOVBreg", argLen: 1, asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVBUreg", argLen: 1, asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHreg", argLen: 1, asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVHUreg", argLen: 1, asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWreg", argLen: 1, asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWUreg", argLen: 1, asm: mips.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVreg", argLen: 1, asm: mips.AMOVV, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVVnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "MOVWF", argLen: 1, asm: mips.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVWD", argLen: 1, asm: mips.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVF", argLen: 1, asm: mips.AMOVVF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVVD", argLen: 1, asm: mips.AMOVVD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFW", argLen: 1, asm: mips.ATRUNCFW, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDW", argLen: 1, asm: mips.ATRUNCDW, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCFV", argLen: 1, asm: mips.ATRUNCFV, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "TRUNCDV", argLen: 1, asm: mips.ATRUNCDV, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVFD", argLen: 1, asm: mips.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "MOVDF", argLen: 1, asm: mips.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4194304}, // R22 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 }, clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 134217730, // R1 R31 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 }, clobbers: 134217734, // R1 R2 R31 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 2, // R1 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, clobbers: 6, // R1 R2 }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicLoad64", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStore64", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStorezero32", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicStorezero64", argLen: 2, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAddconst32", auxType: auxInt32, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicAddconst64", auxType: auxInt64, argLen: 2, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB }, outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 }, }, }, { name: "FPFlagTrue", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "FPFlagFalse", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4194304}, // R22 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 8}, // R3 {1, 16}, // R4 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "ADD", argLen: 2, commutative: true, asm: ppc64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDconst", auxType: auxInt64, argLen: 1, asm: ppc64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FADD", argLen: 2, commutative: true, asm: ppc64.AFADD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: ppc64.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "SUB", argLen: 2, asm: ppc64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBFCconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FSUB", argLen: 2, asm: ppc64.AFSUB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FSUBS", argLen: 2, asm: ppc64.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MULLD", argLen: 2, commutative: true, asm: ppc64.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLW", argLen: 2, commutative: true, asm: ppc64.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLDconst", auxType: auxInt32, argLen: 1, asm: ppc64.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLWconst", auxType: auxInt32, argLen: 1, asm: ppc64.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MADDLD", argLen: 3, asm: ppc64.AMADDLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHD", argLen: 2, commutative: true, asm: ppc64.AMULHD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHW", argLen: 2, commutative: true, asm: ppc64.AMULHW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHDU", argLen: 2, commutative: true, asm: ppc64.AMULHDU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULHWU", argLen: 2, commutative: true, asm: ppc64.AMULHWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredMuluhilo", argLen: 2, resultNotInArgs: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMUL", argLen: 2, commutative: true, asm: ppc64.AFMUL, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: ppc64.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMADD", argLen: 3, asm: ppc64.AFMADD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMADDS", argLen: 3, asm: ppc64.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMSUB", argLen: 3, asm: ppc64.AFMSUB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMSUBS", argLen: 3, asm: ppc64.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "SRAD", argLen: 2, asm: ppc64.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRAW", argLen: 2, asm: ppc64.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRD", argLen: 2, asm: ppc64.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRW", argLen: 2, asm: ppc64.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLD", argLen: 2, asm: ppc64.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLW", argLen: 2, asm: ppc64.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTL", argLen: 2, asm: ppc64.AROTL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTLW", argLen: 2, asm: ppc64.AROTLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLDICL", auxType: auxInt32, argLen: 1, asm: ppc64.ARLDICL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CLRLSLWI", auxType: auxInt32, argLen: 1, asm: ppc64.ACLRLSLWI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CLRLSLDI", auxType: auxInt32, argLen: 1, asm: ppc64.ACLRLSLDI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDC", argLen: 2, commutative: true, asm: ppc64.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBC", argLen: 2, asm: ppc64.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDCconst", auxType: auxInt64, argLen: 1, asm: ppc64.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBCconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDE", argLen: 3, commutative: true, asm: ppc64.AADDE, reg: regInfo{ inputs: []inputInfo{ {2, 9223372036854775808}, // XER {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBE", argLen: 3, asm: ppc64.ASUBE, reg: regInfo{ inputs: []inputInfo{ {2, 9223372036854775808}, // XER {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {1, 9223372036854775808}, // XER {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDZEzero", argLen: 1, asm: ppc64.AADDZE, reg: regInfo{ inputs: []inputInfo{ {0, 9223372036854775808}, // XER }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SUBZEzero", argLen: 1, asm: ppc64.ASUBZE, reg: regInfo{ inputs: []inputInfo{ {0, 9223372036854775808}, // XER }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRADconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRAWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 9223372036854775808, // XER outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRDconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLDconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTLconst", auxType: auxInt64, argLen: 1, asm: ppc64.AROTL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ROTLWconst", auxType: auxInt64, argLen: 1, asm: ppc64.AROTLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "EXTSWSLconst", auxType: auxInt64, argLen: 1, asm: ppc64.AEXTSWSLI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLWINM", auxType: auxInt64, argLen: 1, asm: ppc64.ARLWNM, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLWNM", auxType: auxInt64, argLen: 2, asm: ppc64.ARLWNM, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "RLWMI", auxType: auxInt64, argLen: 2, resultInArg0: true, asm: ppc64.ARLWMI, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTLZD", argLen: 1, clobberFlags: true, asm: ppc64.ACNTLZD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTLZW", argLen: 1, clobberFlags: true, asm: ppc64.ACNTLZW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTTZD", argLen: 1, asm: ppc64.ACNTTZD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CNTTZW", argLen: 1, asm: ppc64.ACNTTZW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "POPCNTD", argLen: 1, asm: ppc64.APOPCNTD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "POPCNTW", argLen: 1, asm: ppc64.APOPCNTW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "POPCNTB", argLen: 1, asm: ppc64.APOPCNTB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FDIV", argLen: 2, asm: ppc64.AFDIV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FDIVS", argLen: 2, asm: ppc64.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "DIVD", argLen: 2, asm: ppc64.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVW", argLen: 2, asm: ppc64.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVDU", argLen: 2, asm: ppc64.ADIVDU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "DIVWU", argLen: 2, asm: ppc64.ADIVWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODUD", argLen: 2, asm: ppc64.AMODUD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODSD", argLen: 2, asm: ppc64.AMODSD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODUW", argLen: 2, asm: ppc64.AMODUW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MODSW", argLen: 2, asm: ppc64.AMODSW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FCTIDZ", argLen: 1, asm: ppc64.AFCTIDZ, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCTIWZ", argLen: 1, asm: ppc64.AFCTIWZ, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCFID", argLen: 1, asm: ppc64.AFCFID, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCFIDS", argLen: 1, asm: ppc64.AFCFIDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FRSP", argLen: 1, asm: ppc64.AFRSP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MFVSRD", argLen: 1, asm: ppc64.AMFVSRD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MTVSRD", argLen: 1, asm: ppc64.AMTVSRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDN", argLen: 2, asm: ppc64.AANDN, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDCC", argLen: 2, commutative: true, asm: ppc64.AANDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ORN", argLen: 2, asm: ppc64.AORN, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ORCC", argLen: 2, commutative: true, asm: ppc64.AORCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NOR", argLen: 2, commutative: true, asm: ppc64.ANOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: ppc64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XORCC", argLen: 2, commutative: true, asm: ppc64.AXORCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "EQV", argLen: 2, commutative: true, asm: ppc64.AEQV, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NEG", argLen: 1, asm: ppc64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FNEG", argLen: 1, asm: ppc64.AFNEG, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FSQRT", argLen: 1, asm: ppc64.AFSQRT, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FSQRTS", argLen: 1, asm: ppc64.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FFLOOR", argLen: 1, asm: ppc64.AFRIM, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCEIL", argLen: 1, asm: ppc64.AFRIP, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FTRUNC", argLen: 1, asm: ppc64.AFRIZ, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FROUND", argLen: 1, asm: ppc64.AFRIN, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FABS", argLen: 1, asm: ppc64.AFABS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FNABS", argLen: 1, asm: ppc64.AFNABS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCPSGN", argLen: 2, asm: ppc64.AFCPSGN, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, asm: ppc64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, clobberFlags: true, asm: ppc64.AANDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDCCconst", auxType: auxInt64, argLen: 1, asm: ppc64.AANDCC, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBreg", argLen: 1, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZreg", argLen: 1, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHreg", argLen: 1, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZreg", argLen: 1, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWreg", argLen: 1, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZreg", argLen: 1, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZloadidx", argLen: 3, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHloadidx", argLen: 3, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZloadidx", argLen: 3, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWloadidx", argLen: 3, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZloadidx", argLen: 3, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDloadidx", argLen: 3, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHBRloadidx", argLen: 3, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRloadidx", argLen: 3, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRloadidx", argLen: 3, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDloadidx", argLen: 3, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSloadidx", argLen: 3, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "DCBT", auxType: auxInt64, argLen: 2, hasSideEffects: true, asm: ppc64.ADCBT, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRstore", auxType: auxSym, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRstore", auxType: auxSym, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHBRstore", auxType: auxSym, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MOVBstoreidx", argLen: 4, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstoreidx", argLen: 4, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstoreidx", argLen: 4, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstoreidx", argLen: 4, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDstoreidx", argLen: 4, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSstoreidx", argLen: 4, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "MOVHBRstoreidx", argLen: 4, asm: ppc64.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWBRstoreidx", argLen: 4, asm: ppc64.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDBRstoreidx", argLen: 4, asm: ppc64.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: ppc64.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: ppc64.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMOVSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: ppc64.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FCMPU", argLen: 2, asm: ppc64.AFCMPU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "CMP", argLen: 2, asm: ppc64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPU", argLen: 2, asm: ppc64.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPW", argLen: 2, asm: ppc64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWU", argLen: 2, asm: ppc64.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPconst", auxType: auxInt64, argLen: 1, asm: ppc64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPUconst", auxType: auxInt64, argLen: 1, asm: ppc64.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: ppc64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "CMPWUconst", auxType: auxInt32, argLen: 1, asm: ppc64.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ISEL", auxType: auxInt32, argLen: 3, asm: ppc64.AISEL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ISELB", auxType: auxInt32, argLen: 2, asm: ppc64.AISEL, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FLessThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FLessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FGreaterThan", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FGreaterEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 2048}, // R11 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, clobbers: 2147483648, // R31 }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, outputs: []outputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4096}, // R12 {1, 2048}, // R11 }, clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4096}, // R12 }, clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 }, clobbers: 1048576, // R20 }, }, { name: "LoweredZeroShort", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredQuadZeroShort", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredQuadZero", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 }, clobbers: 1048576, // R20 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 3145728, // R20 R21 }, }, { name: "LoweredMoveShort", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredQuadMove", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 3145728, // R20 R21 }, }, { name: "LoweredQuadMoveShort", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicStore8", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicStore32", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicStore64", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoad8", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoad32", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoad64", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicLoadPtr", auxType: auxInt64, argLen: 2, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicCas64", auxType: auxInt64, argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicCas32", auxType: auxInt64, argLen: 4, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAnd8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicOr8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredAtomicOr32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 1048576}, // R20 {1, 2097152}, // R21 }, clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { name: "LoweredPubBarrier", argLen: 1, hasSideEffects: true, asm: ppc64.ALWSYNC, reg: regInfo{}, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // R5 {1, 64}, // R6 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // R4 {1, 32}, // R5 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 8}, // R3 {1, 16}, // R4 }, }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT", argLen: 0, reg: regInfo{}, }, { name: "ADD", argLen: 2, commutative: true, asm: riscv.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ADDI", auxType: auxInt64, argLen: 1, asm: riscv.AADDI, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ADDIW", auxType: auxInt64, argLen: 1, asm: riscv.AADDIW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "NEG", argLen: 1, asm: riscv.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "NEGW", argLen: 1, asm: riscv.ANEGW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SUB", argLen: 2, asm: riscv.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SUBW", argLen: 2, asm: riscv.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: riscv.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MULW", argLen: 2, commutative: true, asm: riscv.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MULH", argLen: 2, commutative: true, asm: riscv.AMULH, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MULHU", argLen: 2, commutative: true, asm: riscv.AMULHU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredMuluhilo", argLen: 2, resultNotInArgs: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredMuluover", argLen: 2, resultNotInArgs: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIV", argLen: 2, asm: riscv.ADIV, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIVU", argLen: 2, asm: riscv.ADIVU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIVW", argLen: 2, asm: riscv.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "DIVUW", argLen: 2, asm: riscv.ADIVUW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REM", argLen: 2, asm: riscv.AREM, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REMU", argLen: 2, asm: riscv.AREMU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REMW", argLen: 2, asm: riscv.AREMW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "REMUW", argLen: 2, asm: riscv.AREMUW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymRdWr, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: riscv.AMOV, reg: regInfo{ outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVBstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVHstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVWstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVDstorezero", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "MOVBreg", argLen: 1, asm: riscv.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHreg", argLen: 1, asm: riscv.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWreg", argLen: 1, asm: riscv.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDreg", argLen: 1, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVBUreg", argLen: 1, asm: riscv.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVHUreg", argLen: 1, asm: riscv.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVWUreg", argLen: 1, asm: riscv.AMOVWU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVDnop", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLL", argLen: 2, asm: riscv.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRA", argLen: 2, asm: riscv.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRL", argLen: 2, asm: riscv.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLLI", auxType: auxInt64, argLen: 1, asm: riscv.ASLLI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRAI", auxType: auxInt64, argLen: 1, asm: riscv.ASRAI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SRLI", auxType: auxInt64, argLen: 1, asm: riscv.ASRLI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: riscv.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "XORI", auxType: auxInt64, argLen: 1, asm: riscv.AXORI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: riscv.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ORI", auxType: auxInt64, argLen: 1, asm: riscv.AORI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: riscv.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "ANDI", auxType: auxInt64, argLen: 1, asm: riscv.AANDI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "NOT", argLen: 1, asm: riscv.ANOT, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SEQZ", argLen: 1, asm: riscv.ASEQZ, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SNEZ", argLen: 1, asm: riscv.ASNEZ, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLT", argLen: 2, asm: riscv.ASLT, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLTI", auxType: auxInt64, argLen: 1, asm: riscv.ASLTI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLTU", argLen: 2, asm: riscv.ASLTU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SLTIU", auxType: auxInt64, argLen: 1, asm: riscv.ASLTIU, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "MOVconvert", argLen: 2, asm: riscv.AMOV, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: -1, call: true, reg: regInfo{ clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: -1, call: true, tailCall: true, reg: regInfo{ clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: -1, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 33554432}, // X26 {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: -1, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 16777216}, // X25 }, clobbers: 16777216, // X25 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 16777216}, // X25 {1, 8388608}, // X24 }, clobbers: 25165824, // X24 X25 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 16, // X5 }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 32}, // X6 {2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, clobbers: 112, // X5 X6 X7 }, }, { name: "LoweredAtomicLoad8", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicLoad32", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicLoad64", argLen: 2, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicStore8", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "LoweredAtomicStore32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "LoweredAtomicStore64", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, }, }, { name: "LoweredAtomicExchange32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicExchange64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicAdd32", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicAdd64", argLen: 3, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicCas32", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicCas64", argLen: 4, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredAtomicAnd32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: riscv.AAMOANDW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, }, }, { name: "LoweredAtomicOr32", argLen: 3, faultOnNilArg0: true, hasSideEffects: true, asm: riscv.AAMOORW, reg: regInfo{ inputs: []inputInfo{ {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 33554432}, // X26 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 32}, // X6 }, clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 64}, // X7 {1, 134217728}, // X28 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 32}, // X6 {1, 64}, // X7 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 16}, // X5 {1, 32}, // X6 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: riscv.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBS", argLen: 2, asm: riscv.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: riscv.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVS", argLen: 2, asm: riscv.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTS", argLen: 1, asm: riscv.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGS", argLen: 1, asm: riscv.AFNEGS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMVSX", argLen: 1, asm: riscv.AFMVSX, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTSW", argLen: 1, asm: riscv.AFCVTSW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTSL", argLen: 1, asm: riscv.AFCVTSL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTWS", argLen: 1, asm: riscv.AFCVTWS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FCVTLS", argLen: 1, asm: riscv.AFCVTLS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FMOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FEQS", argLen: 2, commutative: true, asm: riscv.AFEQS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FNES", argLen: 2, commutative: true, asm: riscv.AFNES, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLTS", argLen: 2, asm: riscv.AFLTS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLES", argLen: 2, asm: riscv.AFLES, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FADDD", argLen: 2, commutative: true, asm: riscv.AFADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSUBD", argLen: 2, asm: riscv.AFSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMULD", argLen: 2, commutative: true, asm: riscv.AFMULD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FDIVD", argLen: 2, asm: riscv.AFDIVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMADDD", argLen: 3, commutative: true, asm: riscv.AFMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMSUBD", argLen: 3, commutative: true, asm: riscv.AFMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMADDD", argLen: 3, commutative: true, asm: riscv.AFNMADDD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNMSUBD", argLen: 3, commutative: true, asm: riscv.AFNMSUBD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSQRTD", argLen: 1, asm: riscv.AFSQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FNEGD", argLen: 1, asm: riscv.AFNEGD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FABSD", argLen: 1, asm: riscv.AFABSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FSGNJD", argLen: 2, asm: riscv.AFSGNJD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMVDX", argLen: 1, asm: riscv.AFMVDX, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTDW", argLen: 1, asm: riscv.AFCVTDW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTDL", argLen: 1, asm: riscv.AFCVTDL, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTWD", argLen: 1, asm: riscv.AFCVTWD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FCVTLD", argLen: 1, asm: riscv.AFCVTLD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FCVTDS", argLen: 1, asm: riscv.AFCVTDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FCVTSD", argLen: 1, asm: riscv.AFCVTSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: riscv.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: riscv.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "FEQD", argLen: 2, commutative: true, asm: riscv.AFEQD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FNED", argLen: 2, commutative: true, asm: riscv.AFNED, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLTD", argLen: 2, asm: riscv.AFLTD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FLED", argLen: 2, asm: riscv.AFLED, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "FADDS", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FADD", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFADD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FSUBS", argLen: 2, resultInArg0: true, asm: s390x.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FSUB", argLen: 2, resultInArg0: true, asm: s390x.AFSUB, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMULS", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMUL", argLen: 2, commutative: true, resultInArg0: true, asm: s390x.AFMUL, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FDIVS", argLen: 2, resultInArg0: true, asm: s390x.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FDIV", argLen: 2, resultInArg0: true, asm: s390x.AFDIV, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FNEGS", argLen: 1, clobberFlags: true, asm: s390x.AFNEGS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FNEG", argLen: 1, clobberFlags: true, asm: s390x.AFNEG, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMADDS", argLen: 3, resultInArg0: true, asm: s390x.AFMADDS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMADD", argLen: 3, resultInArg0: true, asm: s390x.AFMADD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMSUBS", argLen: 3, resultInArg0: true, asm: s390x.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMSUB", argLen: 3, resultInArg0: true, asm: s390x.AFMSUB, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LPDFR", argLen: 1, asm: s390x.ALPDFR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LNDFR", argLen: 1, asm: s390x.ALNDFR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CPSDR", argLen: 2, asm: s390x.ACPSDR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FIDBR", auxType: auxInt8, argLen: 1, asm: s390x.AFIDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: s390x.AFMOVS, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: s390x.AFMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSloadidx", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDloadidx", auxType: auxSymOff, argLen: 3, symEffect: SymRead, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVSstoreidx", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: s390x.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FMOVDstoreidx", auxType: auxSymOff, argLen: 4, symEffect: SymWrite, asm: s390x.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ADD", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AADD, reg: regInfo{ inputs: []inputInfo{ {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AADDW, reg: regInfo{ inputs: []inputInfo{ {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: s390x.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDWconst", auxType: auxInt32, argLen: 1, clobberFlags: true, asm: s390x.AADDW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AADDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUB", argLen: 2, clobberFlags: true, asm: s390x.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBW", argLen: 2, clobberFlags: true, asm: s390x.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLD", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLW", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLDconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULLWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MULHD", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULHD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MULHDU", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: s390x.AMULHDU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVD", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVDU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVDU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "DIVWU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ADIVWU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODD", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODD, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODW", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODW, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODDU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODDU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "MODWU", argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.AMODWU, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, clobbers: 2048, // R11 outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "AND", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ANDWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "OR", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ORWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XOR", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORW", argLen: 2, commutative: true, clobberFlags: true, asm: s390x.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORconst", auxType: auxInt64, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORWconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: s390x.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "XORWload", auxType: auxSymOff, argLen: 3, resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: SymRead, asm: s390x.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDC", argLen: 2, commutative: true, asm: s390x.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDCconst", auxType: auxInt16, argLen: 1, asm: s390x.AADDC, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "ADDE", argLen: 3, commutative: true, resultInArg0: true, asm: s390x.AADDE, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBC", argLen: 2, asm: s390x.ASUBC, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SUBE", argLen: 3, resultInArg0: true, asm: s390x.ASUBE, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CMP", argLen: 2, asm: s390x.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPW", argLen: 2, asm: s390x.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPU", argLen: 2, asm: s390x.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPWU", argLen: 2, asm: s390x.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPWconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPUconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "CMPWUconst", auxType: auxInt32, argLen: 1, asm: s390x.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "FCMPS", argLen: 2, asm: s390x.ACEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FCMP", argLen: 2, asm: s390x.AFCMPU, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LTDBR", argLen: 1, asm: s390x.ALTDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LTEBR", argLen: 1, asm: s390x.ALTEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SLD", argLen: 2, asm: s390x.ASLD, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SLW", argLen: 2, asm: s390x.ASLW, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SLDconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASLD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SLWconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRD", argLen: 2, asm: s390x.ASRD, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRW", argLen: 2, asm: s390x.ASRW, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRDconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASRD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRWconst", auxType: auxUInt8, argLen: 1, asm: s390x.ASRW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRAD", argLen: 2, clobberFlags: true, asm: s390x.ASRAD, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRAW", argLen: 2, clobberFlags: true, asm: s390x.ASRAW, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRADconst", auxType: auxUInt8, argLen: 1, clobberFlags: true, asm: s390x.ASRAD, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "SRAWconst", auxType: auxUInt8, argLen: 1, clobberFlags: true, asm: s390x.ASRAW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RLLG", argLen: 2, asm: s390x.ARLLG, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RLL", argLen: 2, asm: s390x.ARLL, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RLLconst", auxType: auxUInt8, argLen: 1, asm: s390x.ARLL, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RXSBG", auxType: auxS390XRotateParams, argLen: 2, resultInArg0: true, clobberFlags: true, asm: s390x.ARXSBG, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RISBGZ", auxType: auxS390XRotateParams, argLen: 1, clobberFlags: true, asm: s390x.ARISBGZ, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NEG", argLen: 1, clobberFlags: true, asm: s390x.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NEGW", argLen: 1, clobberFlags: true, asm: s390x.ANEGW, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NOT", argLen: 1, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "NOTW", argLen: 1, resultInArg0: true, clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "FSQRT", argLen: 1, asm: s390x.AFSQRT, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "FSQRTS", argLen: 1, asm: s390x.AFSQRTS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LOCGR", auxType: auxS390XCCMask, argLen: 3, resultInArg0: true, asm: s390x.ALOCGR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBreg", argLen: 1, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBZreg", argLen: 1, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHreg", argLen: 1, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHZreg", argLen: 1, asm: s390x.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWreg", argLen: 1, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZreg", argLen: 1, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: s390x.AMOVD, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LDGR", argLen: 1, asm: s390x.ALDGR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LGDR", argLen: 1, asm: s390x.ALGDR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CFDBRA", argLen: 1, clobberFlags: true, asm: s390x.ACFDBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CGDBRA", argLen: 1, clobberFlags: true, asm: s390x.ACGDBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CFEBRA", argLen: 1, clobberFlags: true, asm: s390x.ACFEBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CGEBRA", argLen: 1, clobberFlags: true, asm: s390x.ACGEBRA, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CEFBRA", argLen: 1, clobberFlags: true, asm: s390x.ACEFBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDFBRA", argLen: 1, clobberFlags: true, asm: s390x.ACDFBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CEGBRA", argLen: 1, clobberFlags: true, asm: s390x.ACEGBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDGBRA", argLen: 1, clobberFlags: true, asm: s390x.ACDGBRA, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CLFEBR", argLen: 1, clobberFlags: true, asm: s390x.ACLFEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CLFDBR", argLen: 1, clobberFlags: true, asm: s390x.ACLFDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CLGEBR", argLen: 1, clobberFlags: true, asm: s390x.ACLGEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CLGDBR", argLen: 1, clobberFlags: true, asm: s390x.ACLGDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CELFBR", argLen: 1, clobberFlags: true, asm: s390x.ACELFBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDLFBR", argLen: 1, clobberFlags: true, asm: s390x.ACDLFBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CELGBR", argLen: 1, clobberFlags: true, asm: s390x.ACELGBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CDLGBR", argLen: 1, clobberFlags: true, asm: s390x.ACDLGBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LEDBR", argLen: 1, asm: s390x.ALEDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LDEBR", argLen: 1, asm: s390x.ALDEBR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymRead, reg: regInfo{ inputs: []inputInfo{ {0, 4295000064}, // SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDaddridx", auxType: auxSymOff, argLen: 2, symEffect: SymRead, reg: regInfo{ inputs: []inputInfo{ {0, 4295000064}, // SP SB {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWBR", argLen: 1, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDBR", argLen: 1, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDBRload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHBRstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWBRstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDBRstore", auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MVC", auxType: auxSymValAndOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, symEffect: SymNone, asm: s390x.AMVC, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVBZloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHZloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVHBRloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWBRloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDBRloadidx", auxType: auxSymOff, argLen: 3, commutative: true, symEffect: SymRead, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVHBRstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVHBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWBRstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVWBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDBRstoreidx", auxType: auxSymOff, argLen: 4, commutative: true, symEffect: SymWrite, asm: s390x.AMOVDBR, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "MOVHstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "MOVDstoreconst", auxType: auxSymValAndOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, }, }, { name: "CLEAR", auxType: auxSymValAndOff, argLen: 2, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ACLEAR, reg: regInfo{ inputs: []inputInfo{ {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "CALLstatic", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, reg: regInfo{ clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLtail", auxType: auxCallOff, argLen: 1, clobberFlags: true, call: true, tailCall: true, reg: regInfo{ clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLclosure", auxType: auxCallOff, argLen: 3, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {1, 4096}, // R12 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "CALLinter", auxType: auxCallOff, argLen: 2, clobberFlags: true, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, zeroWidth: true, reg: regInfo{ outputs: []outputInfo{ {0, 4096}, // R12 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredNilCheck", argLen: 2, clobberFlags: true, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LoweredRound32F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LoweredRound64F", argLen: 1, resultInArg0: true, zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, clobberFlags: true, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 }, }, }, { name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // R0 {1, 2}, // R1 }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT", argLen: 0, reg: regInfo{}, }, { name: "FlagOV", argLen: 0, reg: regInfo{}, }, { name: "SYNC", argLen: 1, asm: s390x.ASYNC, reg: regInfo{}, }, { name: "MOVBZatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVWZatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVDatomicload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MOVBatomicstore", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymWrite, asm: s390x.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVWatomicstore", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymWrite, asm: s390x.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "MOVDatomicstore", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymWrite, asm: s390x.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LAA", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ALAA, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LAAG", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ALAAG, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "AddTupleFirst32", argLen: 2, reg: regInfo{}, }, { name: "AddTupleFirst64", argLen: 2, reg: regInfo{}, }, { name: "LAN", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAN, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LANfloor", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAN, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 2, // R1 }, }, { name: "LAO", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAO, reg: regInfo{ inputs: []inputInfo{ {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LAOfloor", argLen: 3, clobberFlags: true, hasSideEffects: true, asm: s390x.ALAO, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 2, // R1 }, }, { name: "LoweredAtomicCas32", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACS, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // R0 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 1, // R0 outputs: []outputInfo{ {1, 0}, {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredAtomicCas64", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACSG, reg: regInfo{ inputs: []inputInfo{ {1, 1}, // R0 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 1, // R0 outputs: []outputInfo{ {1, 0}, {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "LoweredAtomicExchange32", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACS, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {1, 0}, {0, 1}, // R0 }, }, }, { name: "LoweredAtomicExchange64", auxType: auxSymOff, argLen: 3, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true, symEffect: SymRdWr, asm: s390x.ACSG, reg: regInfo{ inputs: []inputInfo{ {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, outputs: []outputInfo{ {1, 0}, {0, 1}, // R0 }, }, }, { name: "FLOGR", argLen: 1, clobberFlags: true, asm: s390x.AFLOGR, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, clobbers: 2, // R1 outputs: []outputInfo{ {0, 1}, // R0 }, }, }, { name: "POPCNT", argLen: 1, clobberFlags: true, asm: s390x.APOPCNT, reg: regInfo{ inputs: []inputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "MLGR", argLen: 2, asm: s390x.AMLGR, reg: regInfo{ inputs: []inputInfo{ {1, 8}, // R3 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 4}, // R2 {1, 8}, // R3 }, }, }, { name: "SumBytes2", argLen: 1, reg: regInfo{}, }, { name: "SumBytes4", argLen: 1, reg: regInfo{}, }, { name: "SumBytes8", argLen: 1, reg: regInfo{}, }, { name: "STMG2", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMG, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STMG3", auxType: auxSymOff, argLen: 5, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMG, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STMG4", auxType: auxSymOff, argLen: 6, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMG, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {4, 16}, // R4 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STM2", auxType: auxSymOff, argLen: 4, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMY, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STM3", auxType: auxSymOff, argLen: 5, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMY, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "STM4", auxType: auxSymOff, argLen: 6, clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, asm: s390x.ASTMY, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // R1 {2, 4}, // R2 {3, 8}, // R3 {4, 16}, // R4 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 4, clobberFlags: true, faultOnNilArg0: true, faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 4}, // R2 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 6, // R1 R2 }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 3, clobberFlags: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP }, clobbers: 2, // R1 }, }, { name: "LoweredStaticCall", auxType: auxCallOff, argLen: 1, call: true, reg: regInfo{ clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredTailCall", auxType: auxCallOff, argLen: 1, call: true, tailCall: true, reg: regInfo{ clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredClosureCall", auxType: auxCallOff, argLen: 3, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredInterCall", auxType: auxCallOff, argLen: 2, call: true, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { name: "LoweredAddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, symEffect: SymAddr, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredMove", auxType: auxInt64, argLen: 3, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredZero", auxType: auxInt64, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetCallerSP", argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredNilCheck", argLen: 2, nilCheck: true, faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredWB", auxType: auxSym, argLen: 3, symEffect: SymNone, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredConvert", argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "Select", argLen: 3, asm: wasm.ASelect, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load8U", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load8U, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load8S", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load8S, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load16U", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load16U, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load16S", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load16S, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load32U", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load32U, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load32S", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load32S, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Load", auxType: auxInt64, argLen: 2, asm: wasm.AI64Load, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Store8", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store8, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Store16", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store16, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Store32", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store32, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Store", auxType: auxInt64, argLen: 3, asm: wasm.AI64Store, reg: regInfo{ inputs: []inputInfo{ {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "F32Load", auxType: auxInt64, argLen: 2, asm: wasm.AF32Load, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Load", auxType: auxInt64, argLen: 2, asm: wasm.AF64Load, reg: regInfo{ inputs: []inputInfo{ {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F32Store", auxType: auxInt64, argLen: 3, asm: wasm.AF32Store, reg: regInfo{ inputs: []inputInfo{ {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "F64Store", auxType: auxInt64, argLen: 3, asm: wasm.AF64Store, reg: regInfo{ inputs: []inputInfo{ {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB }, }, }, { name: "I64Const", auxType: auxInt64, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Const", auxType: auxFloat32, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Const", auxType: auxFloat64, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64Eqz", argLen: 1, asm: wasm.AI64Eqz, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Eq", argLen: 2, asm: wasm.AI64Eq, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Ne", argLen: 2, asm: wasm.AI64Ne, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LtS", argLen: 2, asm: wasm.AI64LtS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LtU", argLen: 2, asm: wasm.AI64LtU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GtS", argLen: 2, asm: wasm.AI64GtS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GtU", argLen: 2, asm: wasm.AI64GtU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LeS", argLen: 2, asm: wasm.AI64LeS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64LeU", argLen: 2, asm: wasm.AI64LeU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GeS", argLen: 2, asm: wasm.AI64GeS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64GeU", argLen: 2, asm: wasm.AI64GeU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Eq", argLen: 2, asm: wasm.AF32Eq, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Ne", argLen: 2, asm: wasm.AF32Ne, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Lt", argLen: 2, asm: wasm.AF32Lt, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Gt", argLen: 2, asm: wasm.AF32Gt, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Le", argLen: 2, asm: wasm.AF32Le, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Ge", argLen: 2, asm: wasm.AF32Ge, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Eq", argLen: 2, asm: wasm.AF64Eq, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Ne", argLen: 2, asm: wasm.AF64Ne, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Lt", argLen: 2, asm: wasm.AF64Lt, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Gt", argLen: 2, asm: wasm.AF64Gt, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Le", argLen: 2, asm: wasm.AF64Le, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F64Ge", argLen: 2, asm: wasm.AF64Ge, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Add", argLen: 2, asm: wasm.AI64Add, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64AddConst", auxType: auxInt64, argLen: 1, asm: wasm.AI64Add, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Sub", argLen: 2, asm: wasm.AI64Sub, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Mul", argLen: 2, asm: wasm.AI64Mul, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64DivS", argLen: 2, asm: wasm.AI64DivS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64DivU", argLen: 2, asm: wasm.AI64DivU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64RemS", argLen: 2, asm: wasm.AI64RemS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64RemU", argLen: 2, asm: wasm.AI64RemU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64And", argLen: 2, asm: wasm.AI64And, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Or", argLen: 2, asm: wasm.AI64Or, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Xor", argLen: 2, asm: wasm.AI64Xor, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Shl", argLen: 2, asm: wasm.AI64Shl, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64ShrS", argLen: 2, asm: wasm.AI64ShrS, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64ShrU", argLen: 2, asm: wasm.AI64ShrU, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Neg", argLen: 1, asm: wasm.AF32Neg, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Add", argLen: 2, asm: wasm.AF32Add, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Sub", argLen: 2, asm: wasm.AF32Sub, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Mul", argLen: 2, asm: wasm.AF32Mul, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Div", argLen: 2, asm: wasm.AF32Div, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Neg", argLen: 1, asm: wasm.AF64Neg, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Add", argLen: 2, asm: wasm.AF64Add, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Sub", argLen: 2, asm: wasm.AF64Sub, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Mul", argLen: 2, asm: wasm.AF64Mul, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Div", argLen: 2, asm: wasm.AF64Div, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64TruncSatF64S", argLen: 1, asm: wasm.AI64TruncSatF64S, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64TruncSatF64U", argLen: 1, asm: wasm.AI64TruncSatF64U, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64TruncSatF32S", argLen: 1, asm: wasm.AI64TruncSatF32S, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64TruncSatF32U", argLen: 1, asm: wasm.AI64TruncSatF32U, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32ConvertI64S", argLen: 1, asm: wasm.AF32ConvertI64S, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32ConvertI64U", argLen: 1, asm: wasm.AF32ConvertI64U, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64ConvertI64S", argLen: 1, asm: wasm.AF64ConvertI64S, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64ConvertI64U", argLen: 1, asm: wasm.AF64ConvertI64U, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F32DemoteF64", argLen: 1, asm: wasm.AF32DemoteF64, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64PromoteF32", argLen: 1, asm: wasm.AF64PromoteF32, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64Extend8S", argLen: 1, asm: wasm.AI64Extend8S, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Extend16S", argLen: 1, asm: wasm.AI64Extend16S, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Extend32S", argLen: 1, asm: wasm.AI64Extend32S, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "F32Sqrt", argLen: 1, asm: wasm.AF32Sqrt, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Trunc", argLen: 1, asm: wasm.AF32Trunc, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Ceil", argLen: 1, asm: wasm.AF32Ceil, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Floor", argLen: 1, asm: wasm.AF32Floor, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Nearest", argLen: 1, asm: wasm.AF32Nearest, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Abs", argLen: 1, asm: wasm.AF32Abs, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F32Copysign", argLen: 2, asm: wasm.AF32Copysign, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "F64Sqrt", argLen: 1, asm: wasm.AF64Sqrt, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Trunc", argLen: 1, asm: wasm.AF64Trunc, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Ceil", argLen: 1, asm: wasm.AF64Ceil, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Floor", argLen: 1, asm: wasm.AF64Floor, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Nearest", argLen: 1, asm: wasm.AF64Nearest, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Abs", argLen: 1, asm: wasm.AF64Abs, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "F64Copysign", argLen: 2, asm: wasm.AF64Copysign, reg: regInfo{ inputs: []inputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { name: "I64Ctz", argLen: 1, asm: wasm.AI64Ctz, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Clz", argLen: 1, asm: wasm.AI64Clz, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I32Rotl", argLen: 2, asm: wasm.AI32Rotl, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Rotl", argLen: 2, asm: wasm.AI64Rotl, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "I64Popcnt", argLen: 1, asm: wasm.AI64Popcnt, reg: regInfo{ inputs: []inputInfo{ {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP }, outputs: []outputInfo{ {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "Add8", argLen: 2, commutative: true, generic: true, }, { name: "Add16", argLen: 2, commutative: true, generic: true, }, { name: "Add32", argLen: 2, commutative: true, generic: true, }, { name: "Add64", argLen: 2, commutative: true, generic: true, }, { name: "AddPtr", argLen: 2, generic: true, }, { name: "Add32F", argLen: 2, commutative: true, generic: true, }, { name: "Add64F", argLen: 2, commutative: true, generic: true, }, { name: "Sub8", argLen: 2, generic: true, }, { name: "Sub16", argLen: 2, generic: true, }, { name: "Sub32", argLen: 2, generic: true, }, { name: "Sub64", argLen: 2, generic: true, }, { name: "SubPtr", argLen: 2, generic: true, }, { name: "Sub32F", argLen: 2, generic: true, }, { name: "Sub64F", argLen: 2, generic: true, }, { name: "Mul8", argLen: 2, commutative: true, generic: true, }, { name: "Mul16", argLen: 2, commutative: true, generic: true, }, { name: "Mul32", argLen: 2, commutative: true, generic: true, }, { name: "Mul64", argLen: 2, commutative: true, generic: true, }, { name: "Mul32F", argLen: 2, commutative: true, generic: true, }, { name: "Mul64F", argLen: 2, commutative: true, generic: true, }, { name: "Div32F", argLen: 2, generic: true, }, { name: "Div64F", argLen: 2, generic: true, }, { name: "Hmul32", argLen: 2, commutative: true, generic: true, }, { name: "Hmul32u", argLen: 2, commutative: true, generic: true, }, { name: "Hmul64", argLen: 2, commutative: true, generic: true, }, { name: "Hmul64u", argLen: 2, commutative: true, generic: true, }, { name: "Mul32uhilo", argLen: 2, commutative: true, generic: true, }, { name: "Mul64uhilo", argLen: 2, commutative: true, generic: true, }, { name: "Mul32uover", argLen: 2, commutative: true, generic: true, }, { name: "Mul64uover", argLen: 2, commutative: true, generic: true, }, { name: "Avg32u", argLen: 2, generic: true, }, { name: "Avg64u", argLen: 2, generic: true, }, { name: "Div8", argLen: 2, generic: true, }, { name: "Div8u", argLen: 2, generic: true, }, { name: "Div16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Div16u", argLen: 2, generic: true, }, { name: "Div32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Div32u", argLen: 2, generic: true, }, { name: "Div64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Div64u", argLen: 2, generic: true, }, { name: "Div128u", argLen: 3, generic: true, }, { name: "Mod8", argLen: 2, generic: true, }, { name: "Mod8u", argLen: 2, generic: true, }, { name: "Mod16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Mod16u", argLen: 2, generic: true, }, { name: "Mod32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Mod32u", argLen: 2, generic: true, }, { name: "Mod64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Mod64u", argLen: 2, generic: true, }, { name: "And8", argLen: 2, commutative: true, generic: true, }, { name: "And16", argLen: 2, commutative: true, generic: true, }, { name: "And32", argLen: 2, commutative: true, generic: true, }, { name: "And64", argLen: 2, commutative: true, generic: true, }, { name: "Or8", argLen: 2, commutative: true, generic: true, }, { name: "Or16", argLen: 2, commutative: true, generic: true, }, { name: "Or32", argLen: 2, commutative: true, generic: true, }, { name: "Or64", argLen: 2, commutative: true, generic: true, }, { name: "Xor8", argLen: 2, commutative: true, generic: true, }, { name: "Xor16", argLen: 2, commutative: true, generic: true, }, { name: "Xor32", argLen: 2, commutative: true, generic: true, }, { name: "Xor64", argLen: 2, commutative: true, generic: true, }, { name: "Lsh8x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh8x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh8x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh8x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh16x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh32x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Lsh64x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64x64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh8Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh16Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh32Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux8", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux16", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux32", auxType: auxBool, argLen: 2, generic: true, }, { name: "Rsh64Ux64", auxType: auxBool, argLen: 2, generic: true, }, { name: "Eq8", argLen: 2, commutative: true, generic: true, }, { name: "Eq16", argLen: 2, commutative: true, generic: true, }, { name: "Eq32", argLen: 2, commutative: true, generic: true, }, { name: "Eq64", argLen: 2, commutative: true, generic: true, }, { name: "EqPtr", argLen: 2, commutative: true, generic: true, }, { name: "EqInter", argLen: 2, generic: true, }, { name: "EqSlice", argLen: 2, generic: true, }, { name: "Eq32F", argLen: 2, commutative: true, generic: true, }, { name: "Eq64F", argLen: 2, commutative: true, generic: true, }, { name: "Neq8", argLen: 2, commutative: true, generic: true, }, { name: "Neq16", argLen: 2, commutative: true, generic: true, }, { name: "Neq32", argLen: 2, commutative: true, generic: true, }, { name: "Neq64", argLen: 2, commutative: true, generic: true, }, { name: "NeqPtr", argLen: 2, commutative: true, generic: true, }, { name: "NeqInter", argLen: 2, generic: true, }, { name: "NeqSlice", argLen: 2, generic: true, }, { name: "Neq32F", argLen: 2, commutative: true, generic: true, }, { name: "Neq64F", argLen: 2, commutative: true, generic: true, }, { name: "Less8", argLen: 2, generic: true, }, { name: "Less8U", argLen: 2, generic: true, }, { name: "Less16", argLen: 2, generic: true, }, { name: "Less16U", argLen: 2, generic: true, }, { name: "Less32", argLen: 2, generic: true, }, { name: "Less32U", argLen: 2, generic: true, }, { name: "Less64", argLen: 2, generic: true, }, { name: "Less64U", argLen: 2, generic: true, }, { name: "Less32F", argLen: 2, generic: true, }, { name: "Less64F", argLen: 2, generic: true, }, { name: "Leq8", argLen: 2, generic: true, }, { name: "Leq8U", argLen: 2, generic: true, }, { name: "Leq16", argLen: 2, generic: true, }, { name: "Leq16U", argLen: 2, generic: true, }, { name: "Leq32", argLen: 2, generic: true, }, { name: "Leq32U", argLen: 2, generic: true, }, { name: "Leq64", argLen: 2, generic: true, }, { name: "Leq64U", argLen: 2, generic: true, }, { name: "Leq32F", argLen: 2, generic: true, }, { name: "Leq64F", argLen: 2, generic: true, }, { name: "CondSelect", argLen: 3, generic: true, }, { name: "AndB", argLen: 2, commutative: true, generic: true, }, { name: "OrB", argLen: 2, commutative: true, generic: true, }, { name: "EqB", argLen: 2, commutative: true, generic: true, }, { name: "NeqB", argLen: 2, commutative: true, generic: true, }, { name: "Not", argLen: 1, generic: true, }, { name: "Neg8", argLen: 1, generic: true, }, { name: "Neg16", argLen: 1, generic: true, }, { name: "Neg32", argLen: 1, generic: true, }, { name: "Neg64", argLen: 1, generic: true, }, { name: "Neg32F", argLen: 1, generic: true, }, { name: "Neg64F", argLen: 1, generic: true, }, { name: "Com8", argLen: 1, generic: true, }, { name: "Com16", argLen: 1, generic: true, }, { name: "Com32", argLen: 1, generic: true, }, { name: "Com64", argLen: 1, generic: true, }, { name: "Ctz8", argLen: 1, generic: true, }, { name: "Ctz16", argLen: 1, generic: true, }, { name: "Ctz32", argLen: 1, generic: true, }, { name: "Ctz64", argLen: 1, generic: true, }, { name: "Ctz8NonZero", argLen: 1, generic: true, }, { name: "Ctz16NonZero", argLen: 1, generic: true, }, { name: "Ctz32NonZero", argLen: 1, generic: true, }, { name: "Ctz64NonZero", argLen: 1, generic: true, }, { name: "BitLen8", argLen: 1, generic: true, }, { name: "BitLen16", argLen: 1, generic: true, }, { name: "BitLen32", argLen: 1, generic: true, }, { name: "BitLen64", argLen: 1, generic: true, }, { name: "Bswap32", argLen: 1, generic: true, }, { name: "Bswap64", argLen: 1, generic: true, }, { name: "BitRev8", argLen: 1, generic: true, }, { name: "BitRev16", argLen: 1, generic: true, }, { name: "BitRev32", argLen: 1, generic: true, }, { name: "BitRev64", argLen: 1, generic: true, }, { name: "PopCount8", argLen: 1, generic: true, }, { name: "PopCount16", argLen: 1, generic: true, }, { name: "PopCount32", argLen: 1, generic: true, }, { name: "PopCount64", argLen: 1, generic: true, }, { name: "RotateLeft8", argLen: 2, generic: true, }, { name: "RotateLeft16", argLen: 2, generic: true, }, { name: "RotateLeft32", argLen: 2, generic: true, }, { name: "RotateLeft64", argLen: 2, generic: true, }, { name: "Sqrt", argLen: 1, generic: true, }, { name: "Sqrt32", argLen: 1, generic: true, }, { name: "Floor", argLen: 1, generic: true, }, { name: "Ceil", argLen: 1, generic: true, }, { name: "Trunc", argLen: 1, generic: true, }, { name: "Round", argLen: 1, generic: true, }, { name: "RoundToEven", argLen: 1, generic: true, }, { name: "Abs", argLen: 1, generic: true, }, { name: "Copysign", argLen: 2, generic: true, }, { name: "FMA", argLen: 3, generic: true, }, { name: "Phi", argLen: -1, zeroWidth: true, generic: true, }, { name: "Copy", argLen: 1, generic: true, }, { name: "Convert", argLen: 2, resultInArg0: true, zeroWidth: true, generic: true, }, { name: "ConstBool", auxType: auxBool, argLen: 0, generic: true, }, { name: "ConstString", auxType: auxString, argLen: 0, generic: true, }, { name: "ConstNil", argLen: 0, generic: true, }, { name: "Const8", auxType: auxInt8, argLen: 0, generic: true, }, { name: "Const16", auxType: auxInt16, argLen: 0, generic: true, }, { name: "Const32", auxType: auxInt32, argLen: 0, generic: true, }, { name: "Const64", auxType: auxInt64, argLen: 0, generic: true, }, { name: "Const32F", auxType: auxFloat32, argLen: 0, generic: true, }, { name: "Const64F", auxType: auxFloat64, argLen: 0, generic: true, }, { name: "ConstInterface", argLen: 0, generic: true, }, { name: "ConstSlice", argLen: 0, generic: true, }, { name: "InitMem", argLen: 0, zeroWidth: true, generic: true, }, { name: "Arg", auxType: auxSymOff, argLen: 0, zeroWidth: true, symEffect: SymRead, generic: true, }, { name: "ArgIntReg", auxType: auxNameOffsetInt8, argLen: 0, zeroWidth: true, generic: true, }, { name: "ArgFloatReg", auxType: auxNameOffsetInt8, argLen: 0, zeroWidth: true, generic: true, }, { name: "Addr", auxType: auxSym, argLen: 1, symEffect: SymAddr, generic: true, }, { name: "LocalAddr", auxType: auxSym, argLen: 2, symEffect: SymAddr, generic: true, }, { name: "SP", argLen: 0, zeroWidth: true, generic: true, }, { name: "SB", argLen: 0, zeroWidth: true, generic: true, }, { name: "Load", argLen: 2, generic: true, }, { name: "Dereference", argLen: 2, generic: true, }, { name: "Store", auxType: auxTyp, argLen: 3, generic: true, }, { name: "Move", auxType: auxTypSize, argLen: 3, generic: true, }, { name: "Zero", auxType: auxTypSize, argLen: 2, generic: true, }, { name: "StoreWB", auxType: auxTyp, argLen: 3, generic: true, }, { name: "MoveWB", auxType: auxTypSize, argLen: 3, generic: true, }, { name: "ZeroWB", auxType: auxTypSize, argLen: 2, generic: true, }, { name: "WB", auxType: auxSym, argLen: 3, symEffect: SymNone, generic: true, }, { name: "HasCPUFeature", auxType: auxSym, argLen: 0, symEffect: SymNone, generic: true, }, { name: "PanicBounds", auxType: auxInt64, argLen: 3, call: true, generic: true, }, { name: "PanicExtend", auxType: auxInt64, argLen: 4, call: true, generic: true, }, { name: "ClosureCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "StaticCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "InterCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "TailCall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "ClosureLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "StaticLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "InterLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "TailLECall", auxType: auxCallOff, argLen: -1, call: true, generic: true, }, { name: "SignExt8to16", argLen: 1, generic: true, }, { name: "SignExt8to32", argLen: 1, generic: true, }, { name: "SignExt8to64", argLen: 1, generic: true, }, { name: "SignExt16to32", argLen: 1, generic: true, }, { name: "SignExt16to64", argLen: 1, generic: true, }, { name: "SignExt32to64", argLen: 1, generic: true, }, { name: "ZeroExt8to16", argLen: 1, generic: true, }, { name: "ZeroExt8to32", argLen: 1, generic: true, }, { name: "ZeroExt8to64", argLen: 1, generic: true, }, { name: "ZeroExt16to32", argLen: 1, generic: true, }, { name: "ZeroExt16to64", argLen: 1, generic: true, }, { name: "ZeroExt32to64", argLen: 1, generic: true, }, { name: "Trunc16to8", argLen: 1, generic: true, }, { name: "Trunc32to8", argLen: 1, generic: true, }, { name: "Trunc32to16", argLen: 1, generic: true, }, { name: "Trunc64to8", argLen: 1, generic: true, }, { name: "Trunc64to16", argLen: 1, generic: true, }, { name: "Trunc64to32", argLen: 1, generic: true, }, { name: "Cvt32to32F", argLen: 1, generic: true, }, { name: "Cvt32to64F", argLen: 1, generic: true, }, { name: "Cvt64to32F", argLen: 1, generic: true, }, { name: "Cvt64to64F", argLen: 1, generic: true, }, { name: "Cvt32Fto32", argLen: 1, generic: true, }, { name: "Cvt32Fto64", argLen: 1, generic: true, }, { name: "Cvt64Fto32", argLen: 1, generic: true, }, { name: "Cvt64Fto64", argLen: 1, generic: true, }, { name: "Cvt32Fto64F", argLen: 1, generic: true, }, { name: "Cvt64Fto32F", argLen: 1, generic: true, }, { name: "CvtBoolToUint8", argLen: 1, generic: true, }, { name: "Round32F", argLen: 1, generic: true, }, { name: "Round64F", argLen: 1, generic: true, }, { name: "IsNonNil", argLen: 1, generic: true, }, { name: "IsInBounds", argLen: 2, generic: true, }, { name: "IsSliceInBounds", argLen: 2, generic: true, }, { name: "NilCheck", argLen: 2, generic: true, }, { name: "GetG", argLen: 1, zeroWidth: true, generic: true, }, { name: "GetClosurePtr", argLen: 0, generic: true, }, { name: "GetCallerPC", argLen: 0, generic: true, }, { name: "GetCallerSP", argLen: 0, generic: true, }, { name: "PtrIndex", argLen: 2, generic: true, }, { name: "OffPtr", auxType: auxInt64, argLen: 1, generic: true, }, { name: "SliceMake", argLen: 3, generic: true, }, { name: "SlicePtr", argLen: 1, generic: true, }, { name: "SliceLen", argLen: 1, generic: true, }, { name: "SliceCap", argLen: 1, generic: true, }, { name: "SlicePtrUnchecked", argLen: 1, generic: true, }, { name: "ComplexMake", argLen: 2, generic: true, }, { name: "ComplexReal", argLen: 1, generic: true, }, { name: "ComplexImag", argLen: 1, generic: true, }, { name: "StringMake", argLen: 2, generic: true, }, { name: "StringPtr", argLen: 1, generic: true, }, { name: "StringLen", argLen: 1, generic: true, }, { name: "IMake", argLen: 2, generic: true, }, { name: "ITab", argLen: 1, generic: true, }, { name: "IData", argLen: 1, generic: true, }, { name: "StructMake0", argLen: 0, generic: true, }, { name: "StructMake1", argLen: 1, generic: true, }, { name: "StructMake2", argLen: 2, generic: true, }, { name: "StructMake3", argLen: 3, generic: true, }, { name: "StructMake4", argLen: 4, generic: true, }, { name: "StructSelect", auxType: auxInt64, argLen: 1, generic: true, }, { name: "ArrayMake0", argLen: 0, generic: true, }, { name: "ArrayMake1", argLen: 1, generic: true, }, { name: "ArraySelect", auxType: auxInt64, argLen: 1, generic: true, }, { name: "StoreReg", argLen: 1, generic: true, }, { name: "LoadReg", argLen: 1, generic: true, }, { name: "FwdRef", auxType: auxSym, argLen: 0, symEffect: SymNone, generic: true, }, { name: "Unknown", argLen: 0, generic: true, }, { name: "VarDef", auxType: auxSym, argLen: 1, zeroWidth: true, symEffect: SymNone, generic: true, }, { name: "VarKill", auxType: auxSym, argLen: 1, symEffect: SymNone, generic: true, }, { name: "VarLive", auxType: auxSym, argLen: 1, zeroWidth: true, symEffect: SymRead, generic: true, }, { name: "KeepAlive", argLen: 2, zeroWidth: true, generic: true, }, { name: "InlMark", auxType: auxInt32, argLen: 1, generic: true, }, { name: "Int64Make", argLen: 2, generic: true, }, { name: "Int64Hi", argLen: 1, generic: true, }, { name: "Int64Lo", argLen: 1, generic: true, }, { name: "Add32carry", argLen: 2, commutative: true, generic: true, }, { name: "Add32withcarry", argLen: 3, commutative: true, generic: true, }, { name: "Sub32carry", argLen: 2, generic: true, }, { name: "Sub32withcarry", argLen: 3, generic: true, }, { name: "Add64carry", argLen: 3, commutative: true, generic: true, }, { name: "Sub64borrow", argLen: 3, generic: true, }, { name: "Signmask", argLen: 1, generic: true, }, { name: "Zeromask", argLen: 1, generic: true, }, { name: "Slicemask", argLen: 1, generic: true, }, { name: "SpectreIndex", argLen: 2, generic: true, }, { name: "SpectreSliceIndex", argLen: 2, generic: true, }, { name: "Cvt32Uto32F", argLen: 1, generic: true, }, { name: "Cvt32Uto64F", argLen: 1, generic: true, }, { name: "Cvt32Fto32U", argLen: 1, generic: true, }, { name: "Cvt64Fto32U", argLen: 1, generic: true, }, { name: "Cvt64Uto32F", argLen: 1, generic: true, }, { name: "Cvt64Uto64F", argLen: 1, generic: true, }, { name: "Cvt32Fto64U", argLen: 1, generic: true, }, { name: "Cvt64Fto64U", argLen: 1, generic: true, }, { name: "Select0", argLen: 1, zeroWidth: true, generic: true, }, { name: "Select1", argLen: 1, zeroWidth: true, generic: true, }, { name: "SelectN", auxType: auxInt64, argLen: 1, generic: true, }, { name: "SelectNAddr", auxType: auxInt64, argLen: 1, generic: true, }, { name: "MakeResult", argLen: -1, generic: true, }, { name: "AtomicLoad8", argLen: 2, generic: true, }, { name: "AtomicLoad32", argLen: 2, generic: true, }, { name: "AtomicLoad64", argLen: 2, generic: true, }, { name: "AtomicLoadPtr", argLen: 2, generic: true, }, { name: "AtomicLoadAcq32", argLen: 2, generic: true, }, { name: "AtomicLoadAcq64", argLen: 2, generic: true, }, { name: "AtomicStore8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStore64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStorePtrNoWB", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStoreRel32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicStoreRel64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd64", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap32", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap64", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwapRel32", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicAnd8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr8", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr32", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAdd64Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicExchange64Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap32Variant", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicCompareAndSwap64Variant", argLen: 4, hasSideEffects: true, generic: true, }, { name: "AtomicAnd8Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicAnd32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr8Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "AtomicOr32Variant", argLen: 3, hasSideEffects: true, generic: true, }, { name: "PubBarrier", argLen: 1, hasSideEffects: true, generic: true, }, { name: "Clobber", auxType: auxSymOff, argLen: 0, symEffect: SymNone, generic: true, }, { name: "ClobberReg", argLen: 0, generic: true, }, { name: "PrefetchCache", argLen: 2, hasSideEffects: true, generic: true, }, { name: "PrefetchCacheStreamed", argLen: 2, hasSideEffects: true, generic: true, }, } func (o Op) Asm() obj.As { return opcodeTable[o].asm } func (o Op) Scale() int16 { return int16(opcodeTable[o].scale) } func (o Op) String() string { return opcodeTable[o].name } func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } func (o Op) IsCall() bool { return opcodeTable[o].call } func (o Op) IsTailCall() bool { return opcodeTable[o].tailCall } func (o Op) HasSideEffects() bool { return opcodeTable[o].hasSideEffects } func (o Op) UnsafePoint() bool { return opcodeTable[o].unsafePoint } func (o Op) ResultInArg0() bool { return opcodeTable[o].resultInArg0 } var registers386 = [...]Register{ {0, x86.REG_AX, 0, "AX"}, {1, x86.REG_CX, 1, "CX"}, {2, x86.REG_DX, 2, "DX"}, {3, x86.REG_BX, 3, "BX"}, {4, x86.REGSP, -1, "SP"}, {5, x86.REG_BP, 4, "BP"}, {6, x86.REG_SI, 5, "SI"}, {7, x86.REG_DI, 6, "DI"}, {8, x86.REG_X0, -1, "X0"}, {9, x86.REG_X1, -1, "X1"}, {10, x86.REG_X2, -1, "X2"}, {11, x86.REG_X3, -1, "X3"}, {12, x86.REG_X4, -1, "X4"}, {13, x86.REG_X5, -1, "X5"}, {14, x86.REG_X6, -1, "X6"}, {15, x86.REG_X7, -1, "X7"}, {16, 0, -1, "SB"}, } var paramIntReg386 = []int8(nil) var paramFloatReg386 = []int8(nil) var gpRegMask386 = regMask(239) var fpRegMask386 = regMask(65280) var specialRegMask386 = regMask(0) var framepointerReg386 = int8(5) var linkReg386 = int8(-1) var registersAMD64 = [...]Register{ {0, x86.REG_AX, 0, "AX"}, {1, x86.REG_CX, 1, "CX"}, {2, x86.REG_DX, 2, "DX"}, {3, x86.REG_BX, 3, "BX"}, {4, x86.REGSP, -1, "SP"}, {5, x86.REG_BP, 4, "BP"}, {6, x86.REG_SI, 5, "SI"}, {7, x86.REG_DI, 6, "DI"}, {8, x86.REG_R8, 7, "R8"}, {9, x86.REG_R9, 8, "R9"}, {10, x86.REG_R10, 9, "R10"}, {11, x86.REG_R11, 10, "R11"}, {12, x86.REG_R12, 11, "R12"}, {13, x86.REG_R13, 12, "R13"}, {14, x86.REGG, -1, "g"}, {15, x86.REG_R15, 13, "R15"}, {16, x86.REG_X0, -1, "X0"}, {17, x86.REG_X1, -1, "X1"}, {18, x86.REG_X2, -1, "X2"}, {19, x86.REG_X3, -1, "X3"}, {20, x86.REG_X4, -1, "X4"}, {21, x86.REG_X5, -1, "X5"}, {22, x86.REG_X6, -1, "X6"}, {23, x86.REG_X7, -1, "X7"}, {24, x86.REG_X8, -1, "X8"}, {25, x86.REG_X9, -1, "X9"}, {26, x86.REG_X10, -1, "X10"}, {27, x86.REG_X11, -1, "X11"}, {28, x86.REG_X12, -1, "X12"}, {29, x86.REG_X13, -1, "X13"}, {30, x86.REG_X14, -1, "X14"}, {31, x86.REG_X15, -1, "X15"}, {32, 0, -1, "SB"}, } var paramIntRegAMD64 = []int8{0, 3, 1, 7, 6, 8, 9, 10, 11} var paramFloatRegAMD64 = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30} var gpRegMaskAMD64 = regMask(49135) var fpRegMaskAMD64 = regMask(2147418112) var specialRegMaskAMD64 = regMask(2147483648) var framepointerRegAMD64 = int8(5) var linkRegAMD64 = int8(-1) var registersARM = [...]Register{ {0, arm.REG_R0, 0, "R0"}, {1, arm.REG_R1, 1, "R1"}, {2, arm.REG_R2, 2, "R2"}, {3, arm.REG_R3, 3, "R3"}, {4, arm.REG_R4, 4, "R4"}, {5, arm.REG_R5, 5, "R5"}, {6, arm.REG_R6, 6, "R6"}, {7, arm.REG_R7, 7, "R7"}, {8, arm.REG_R8, 8, "R8"}, {9, arm.REG_R9, 9, "R9"}, {10, arm.REGG, -1, "g"}, {11, arm.REG_R11, -1, "R11"}, {12, arm.REG_R12, 10, "R12"}, {13, arm.REGSP, -1, "SP"}, {14, arm.REG_R14, 11, "R14"}, {15, arm.REG_R15, -1, "R15"}, {16, arm.REG_F0, -1, "F0"}, {17, arm.REG_F1, -1, "F1"}, {18, arm.REG_F2, -1, "F2"}, {19, arm.REG_F3, -1, "F3"}, {20, arm.REG_F4, -1, "F4"}, {21, arm.REG_F5, -1, "F5"}, {22, arm.REG_F6, -1, "F6"}, {23, arm.REG_F7, -1, "F7"}, {24, arm.REG_F8, -1, "F8"}, {25, arm.REG_F9, -1, "F9"}, {26, arm.REG_F10, -1, "F10"}, {27, arm.REG_F11, -1, "F11"}, {28, arm.REG_F12, -1, "F12"}, {29, arm.REG_F13, -1, "F13"}, {30, arm.REG_F14, -1, "F14"}, {31, arm.REG_F15, -1, "F15"}, {32, 0, -1, "SB"}, } var paramIntRegARM = []int8(nil) var paramFloatRegARM = []int8(nil) var gpRegMaskARM = regMask(21503) var fpRegMaskARM = regMask(4294901760) var specialRegMaskARM = regMask(0) var framepointerRegARM = int8(-1) var linkRegARM = int8(14) var registersARM64 = [...]Register{ {0, arm64.REG_R0, 0, "R0"}, {1, arm64.REG_R1, 1, "R1"}, {2, arm64.REG_R2, 2, "R2"}, {3, arm64.REG_R3, 3, "R3"}, {4, arm64.REG_R4, 4, "R4"}, {5, arm64.REG_R5, 5, "R5"}, {6, arm64.REG_R6, 6, "R6"}, {7, arm64.REG_R7, 7, "R7"}, {8, arm64.REG_R8, 8, "R8"}, {9, arm64.REG_R9, 9, "R9"}, {10, arm64.REG_R10, 10, "R10"}, {11, arm64.REG_R11, 11, "R11"}, {12, arm64.REG_R12, 12, "R12"}, {13, arm64.REG_R13, 13, "R13"}, {14, arm64.REG_R14, 14, "R14"}, {15, arm64.REG_R15, 15, "R15"}, {16, arm64.REG_R16, 16, "R16"}, {17, arm64.REG_R17, 17, "R17"}, {18, arm64.REG_R18, -1, "R18"}, {19, arm64.REG_R19, 18, "R19"}, {20, arm64.REG_R20, 19, "R20"}, {21, arm64.REG_R21, 20, "R21"}, {22, arm64.REG_R22, 21, "R22"}, {23, arm64.REG_R23, 22, "R23"}, {24, arm64.REG_R24, 23, "R24"}, {25, arm64.REG_R25, 24, "R25"}, {26, arm64.REG_R26, 25, "R26"}, {27, arm64.REGG, -1, "g"}, {28, arm64.REG_R29, -1, "R29"}, {29, arm64.REG_R30, 26, "R30"}, {30, arm64.REGSP, -1, "SP"}, {31, arm64.REG_F0, -1, "F0"}, {32, arm64.REG_F1, -1, "F1"}, {33, arm64.REG_F2, -1, "F2"}, {34, arm64.REG_F3, -1, "F3"}, {35, arm64.REG_F4, -1, "F4"}, {36, arm64.REG_F5, -1, "F5"}, {37, arm64.REG_F6, -1, "F6"}, {38, arm64.REG_F7, -1, "F7"}, {39, arm64.REG_F8, -1, "F8"}, {40, arm64.REG_F9, -1, "F9"}, {41, arm64.REG_F10, -1, "F10"}, {42, arm64.REG_F11, -1, "F11"}, {43, arm64.REG_F12, -1, "F12"}, {44, arm64.REG_F13, -1, "F13"}, {45, arm64.REG_F14, -1, "F14"}, {46, arm64.REG_F15, -1, "F15"}, {47, arm64.REG_F16, -1, "F16"}, {48, arm64.REG_F17, -1, "F17"}, {49, arm64.REG_F18, -1, "F18"}, {50, arm64.REG_F19, -1, "F19"}, {51, arm64.REG_F20, -1, "F20"}, {52, arm64.REG_F21, -1, "F21"}, {53, arm64.REG_F22, -1, "F22"}, {54, arm64.REG_F23, -1, "F23"}, {55, arm64.REG_F24, -1, "F24"}, {56, arm64.REG_F25, -1, "F25"}, {57, arm64.REG_F26, -1, "F26"}, {58, arm64.REG_F27, -1, "F27"}, {59, arm64.REG_F28, -1, "F28"}, {60, arm64.REG_F29, -1, "F29"}, {61, arm64.REG_F30, -1, "F30"}, {62, arm64.REG_F31, -1, "F31"}, {63, 0, -1, "SB"}, } var paramIntRegARM64 = []int8{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} var paramFloatRegARM64 = []int8{31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46} var gpRegMaskARM64 = regMask(670826495) var fpRegMaskARM64 = regMask(9223372034707292160) var specialRegMaskARM64 = regMask(0) var framepointerRegARM64 = int8(-1) var linkRegARM64 = int8(29) var registersLOONG64 = [...]Register{ {0, loong64.REG_R0, -1, "R0"}, {1, loong64.REG_R1, -1, "R1"}, {2, loong64.REGSP, -1, "SP"}, {3, loong64.REG_R4, 0, "R4"}, {4, loong64.REG_R5, 1, "R5"}, {5, loong64.REG_R6, 2, "R6"}, {6, loong64.REG_R7, 3, "R7"}, {7, loong64.REG_R8, 4, "R8"}, {8, loong64.REG_R9, 5, "R9"}, {9, loong64.REG_R10, 6, "R10"}, {10, loong64.REG_R11, 7, "R11"}, {11, loong64.REG_R12, 8, "R12"}, {12, loong64.REG_R13, 9, "R13"}, {13, loong64.REG_R14, 10, "R14"}, {14, loong64.REG_R15, 11, "R15"}, {15, loong64.REG_R16, 12, "R16"}, {16, loong64.REG_R17, 13, "R17"}, {17, loong64.REG_R18, 14, "R18"}, {18, loong64.REG_R19, 15, "R19"}, {19, loong64.REG_R20, 16, "R20"}, {20, loong64.REG_R21, -1, "R21"}, {21, loong64.REGG, -1, "g"}, {22, loong64.REG_R23, 17, "R23"}, {23, loong64.REG_R24, 18, "R24"}, {24, loong64.REG_R25, 19, "R25"}, {25, loong64.REG_R26, 20, "R26"}, {26, loong64.REG_R27, 21, "R27"}, {27, loong64.REG_R28, 22, "R28"}, {28, loong64.REG_R29, 23, "R29"}, {29, loong64.REG_R31, 24, "R31"}, {30, loong64.REG_F0, -1, "F0"}, {31, loong64.REG_F1, -1, "F1"}, {32, loong64.REG_F2, -1, "F2"}, {33, loong64.REG_F3, -1, "F3"}, {34, loong64.REG_F4, -1, "F4"}, {35, loong64.REG_F5, -1, "F5"}, {36, loong64.REG_F6, -1, "F6"}, {37, loong64.REG_F7, -1, "F7"}, {38, loong64.REG_F8, -1, "F8"}, {39, loong64.REG_F9, -1, "F9"}, {40, loong64.REG_F10, -1, "F10"}, {41, loong64.REG_F11, -1, "F11"}, {42, loong64.REG_F12, -1, "F12"}, {43, loong64.REG_F13, -1, "F13"}, {44, loong64.REG_F14, -1, "F14"}, {45, loong64.REG_F15, -1, "F15"}, {46, loong64.REG_F16, -1, "F16"}, {47, loong64.REG_F17, -1, "F17"}, {48, loong64.REG_F18, -1, "F18"}, {49, loong64.REG_F19, -1, "F19"}, {50, loong64.REG_F20, -1, "F20"}, {51, loong64.REG_F21, -1, "F21"}, {52, loong64.REG_F22, -1, "F22"}, {53, loong64.REG_F23, -1, "F23"}, {54, loong64.REG_F24, -1, "F24"}, {55, loong64.REG_F25, -1, "F25"}, {56, loong64.REG_F26, -1, "F26"}, {57, loong64.REG_F27, -1, "F27"}, {58, loong64.REG_F28, -1, "F28"}, {59, loong64.REG_F29, -1, "F29"}, {60, loong64.REG_F30, -1, "F30"}, {61, loong64.REG_F31, -1, "F31"}, {62, 0, -1, "SB"}, } var paramIntRegLOONG64 = []int8{3, 4, 5, 6, 7, 8, 9, 10} var paramFloatRegLOONG64 = []int8{30, 31, 32, 33, 34, 35, 36, 37} var gpRegMaskLOONG64 = regMask(1070596088) var fpRegMaskLOONG64 = regMask(4611686017353646080) var specialRegMaskLOONG64 = regMask(0) var framepointerRegLOONG64 = int8(-1) var linkRegLOONG64 = int8(1) var registersMIPS = [...]Register{ {0, mips.REG_R0, -1, "R0"}, {1, mips.REG_R1, 0, "R1"}, {2, mips.REG_R2, 1, "R2"}, {3, mips.REG_R3, 2, "R3"}, {4, mips.REG_R4, 3, "R4"}, {5, mips.REG_R5, 4, "R5"}, {6, mips.REG_R6, 5, "R6"}, {7, mips.REG_R7, 6, "R7"}, {8, mips.REG_R8, 7, "R8"}, {9, mips.REG_R9, 8, "R9"}, {10, mips.REG_R10, 9, "R10"}, {11, mips.REG_R11, 10, "R11"}, {12, mips.REG_R12, 11, "R12"}, {13, mips.REG_R13, 12, "R13"}, {14, mips.REG_R14, 13, "R14"}, {15, mips.REG_R15, 14, "R15"}, {16, mips.REG_R16, 15, "R16"}, {17, mips.REG_R17, 16, "R17"}, {18, mips.REG_R18, 17, "R18"}, {19, mips.REG_R19, 18, "R19"}, {20, mips.REG_R20, 19, "R20"}, {21, mips.REG_R21, 20, "R21"}, {22, mips.REG_R22, 21, "R22"}, {23, mips.REG_R24, 22, "R24"}, {24, mips.REG_R25, 23, "R25"}, {25, mips.REG_R28, 24, "R28"}, {26, mips.REGSP, -1, "SP"}, {27, mips.REGG, -1, "g"}, {28, mips.REG_R31, 25, "R31"}, {29, mips.REG_F0, -1, "F0"}, {30, mips.REG_F2, -1, "F2"}, {31, mips.REG_F4, -1, "F4"}, {32, mips.REG_F6, -1, "F6"}, {33, mips.REG_F8, -1, "F8"}, {34, mips.REG_F10, -1, "F10"}, {35, mips.REG_F12, -1, "F12"}, {36, mips.REG_F14, -1, "F14"}, {37, mips.REG_F16, -1, "F16"}, {38, mips.REG_F18, -1, "F18"}, {39, mips.REG_F20, -1, "F20"}, {40, mips.REG_F22, -1, "F22"}, {41, mips.REG_F24, -1, "F24"}, {42, mips.REG_F26, -1, "F26"}, {43, mips.REG_F28, -1, "F28"}, {44, mips.REG_F30, -1, "F30"}, {45, mips.REG_HI, -1, "HI"}, {46, mips.REG_LO, -1, "LO"}, {47, 0, -1, "SB"}, } var paramIntRegMIPS = []int8(nil) var paramFloatRegMIPS = []int8(nil) var gpRegMaskMIPS = regMask(335544318) var fpRegMaskMIPS = regMask(35183835217920) var specialRegMaskMIPS = regMask(105553116266496) var framepointerRegMIPS = int8(-1) var linkRegMIPS = int8(28) var registersMIPS64 = [...]Register{ {0, mips.REG_R0, -1, "R0"}, {1, mips.REG_R1, 0, "R1"}, {2, mips.REG_R2, 1, "R2"}, {3, mips.REG_R3, 2, "R3"}, {4, mips.REG_R4, 3, "R4"}, {5, mips.REG_R5, 4, "R5"}, {6, mips.REG_R6, 5, "R6"}, {7, mips.REG_R7, 6, "R7"}, {8, mips.REG_R8, 7, "R8"}, {9, mips.REG_R9, 8, "R9"}, {10, mips.REG_R10, 9, "R10"}, {11, mips.REG_R11, 10, "R11"}, {12, mips.REG_R12, 11, "R12"}, {13, mips.REG_R13, 12, "R13"}, {14, mips.REG_R14, 13, "R14"}, {15, mips.REG_R15, 14, "R15"}, {16, mips.REG_R16, 15, "R16"}, {17, mips.REG_R17, 16, "R17"}, {18, mips.REG_R18, 17, "R18"}, {19, mips.REG_R19, 18, "R19"}, {20, mips.REG_R20, 19, "R20"}, {21, mips.REG_R21, 20, "R21"}, {22, mips.REG_R22, 21, "R22"}, {23, mips.REG_R24, 22, "R24"}, {24, mips.REG_R25, 23, "R25"}, {25, mips.REGSP, -1, "SP"}, {26, mips.REGG, -1, "g"}, {27, mips.REG_R31, 24, "R31"}, {28, mips.REG_F0, -1, "F0"}, {29, mips.REG_F1, -1, "F1"}, {30, mips.REG_F2, -1, "F2"}, {31, mips.REG_F3, -1, "F3"}, {32, mips.REG_F4, -1, "F4"}, {33, mips.REG_F5, -1, "F5"}, {34, mips.REG_F6, -1, "F6"}, {35, mips.REG_F7, -1, "F7"}, {36, mips.REG_F8, -1, "F8"}, {37, mips.REG_F9, -1, "F9"}, {38, mips.REG_F10, -1, "F10"}, {39, mips.REG_F11, -1, "F11"}, {40, mips.REG_F12, -1, "F12"}, {41, mips.REG_F13, -1, "F13"}, {42, mips.REG_F14, -1, "F14"}, {43, mips.REG_F15, -1, "F15"}, {44, mips.REG_F16, -1, "F16"}, {45, mips.REG_F17, -1, "F17"}, {46, mips.REG_F18, -1, "F18"}, {47, mips.REG_F19, -1, "F19"}, {48, mips.REG_F20, -1, "F20"}, {49, mips.REG_F21, -1, "F21"}, {50, mips.REG_F22, -1, "F22"}, {51, mips.REG_F23, -1, "F23"}, {52, mips.REG_F24, -1, "F24"}, {53, mips.REG_F25, -1, "F25"}, {54, mips.REG_F26, -1, "F26"}, {55, mips.REG_F27, -1, "F27"}, {56, mips.REG_F28, -1, "F28"}, {57, mips.REG_F29, -1, "F29"}, {58, mips.REG_F30, -1, "F30"}, {59, mips.REG_F31, -1, "F31"}, {60, mips.REG_HI, -1, "HI"}, {61, mips.REG_LO, -1, "LO"}, {62, 0, -1, "SB"}, } var paramIntRegMIPS64 = []int8(nil) var paramFloatRegMIPS64 = []int8(nil) var gpRegMaskMIPS64 = regMask(167772158) var fpRegMaskMIPS64 = regMask(1152921504338411520) var specialRegMaskMIPS64 = regMask(3458764513820540928) var framepointerRegMIPS64 = int8(-1) var linkRegMIPS64 = int8(27) var registersPPC64 = [...]Register{ {0, ppc64.REG_R0, -1, "R0"}, {1, ppc64.REGSP, -1, "SP"}, {2, 0, -1, "SB"}, {3, ppc64.REG_R3, 0, "R3"}, {4, ppc64.REG_R4, 1, "R4"}, {5, ppc64.REG_R5, 2, "R5"}, {6, ppc64.REG_R6, 3, "R6"}, {7, ppc64.REG_R7, 4, "R7"}, {8, ppc64.REG_R8, 5, "R8"}, {9, ppc64.REG_R9, 6, "R9"}, {10, ppc64.REG_R10, 7, "R10"}, {11, ppc64.REG_R11, 8, "R11"}, {12, ppc64.REG_R12, 9, "R12"}, {13, ppc64.REG_R13, -1, "R13"}, {14, ppc64.REG_R14, 10, "R14"}, {15, ppc64.REG_R15, 11, "R15"}, {16, ppc64.REG_R16, 12, "R16"}, {17, ppc64.REG_R17, 13, "R17"}, {18, ppc64.REG_R18, 14, "R18"}, {19, ppc64.REG_R19, 15, "R19"}, {20, ppc64.REG_R20, 16, "R20"}, {21, ppc64.REG_R21, 17, "R21"}, {22, ppc64.REG_R22, 18, "R22"}, {23, ppc64.REG_R23, 19, "R23"}, {24, ppc64.REG_R24, 20, "R24"}, {25, ppc64.REG_R25, 21, "R25"}, {26, ppc64.REG_R26, 22, "R26"}, {27, ppc64.REG_R27, 23, "R27"}, {28, ppc64.REG_R28, 24, "R28"}, {29, ppc64.REG_R29, 25, "R29"}, {30, ppc64.REGG, -1, "g"}, {31, ppc64.REG_R31, -1, "R31"}, {32, ppc64.REG_F0, -1, "F0"}, {33, ppc64.REG_F1, -1, "F1"}, {34, ppc64.REG_F2, -1, "F2"}, {35, ppc64.REG_F3, -1, "F3"}, {36, ppc64.REG_F4, -1, "F4"}, {37, ppc64.REG_F5, -1, "F5"}, {38, ppc64.REG_F6, -1, "F6"}, {39, ppc64.REG_F7, -1, "F7"}, {40, ppc64.REG_F8, -1, "F8"}, {41, ppc64.REG_F9, -1, "F9"}, {42, ppc64.REG_F10, -1, "F10"}, {43, ppc64.REG_F11, -1, "F11"}, {44, ppc64.REG_F12, -1, "F12"}, {45, ppc64.REG_F13, -1, "F13"}, {46, ppc64.REG_F14, -1, "F14"}, {47, ppc64.REG_F15, -1, "F15"}, {48, ppc64.REG_F16, -1, "F16"}, {49, ppc64.REG_F17, -1, "F17"}, {50, ppc64.REG_F18, -1, "F18"}, {51, ppc64.REG_F19, -1, "F19"}, {52, ppc64.REG_F20, -1, "F20"}, {53, ppc64.REG_F21, -1, "F21"}, {54, ppc64.REG_F22, -1, "F22"}, {55, ppc64.REG_F23, -1, "F23"}, {56, ppc64.REG_F24, -1, "F24"}, {57, ppc64.REG_F25, -1, "F25"}, {58, ppc64.REG_F26, -1, "F26"}, {59, ppc64.REG_F27, -1, "F27"}, {60, ppc64.REG_F28, -1, "F28"}, {61, ppc64.REG_F29, -1, "F29"}, {62, ppc64.REG_F30, -1, "F30"}, {63, ppc64.REG_XER, -1, "XER"}, } var paramIntRegPPC64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 16, 17} var paramFloatRegPPC64 = []int8{33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44} var gpRegMaskPPC64 = regMask(1073733624) var fpRegMaskPPC64 = regMask(9223372032559808512) var specialRegMaskPPC64 = regMask(9223372036854775808) var framepointerRegPPC64 = int8(-1) var linkRegPPC64 = int8(-1) var registersRISCV64 = [...]Register{ {0, riscv.REG_X0, -1, "X0"}, {1, riscv.REGSP, -1, "SP"}, {2, riscv.REG_X3, -1, "X3"}, {3, riscv.REG_X4, -1, "X4"}, {4, riscv.REG_X5, 0, "X5"}, {5, riscv.REG_X6, 1, "X6"}, {6, riscv.REG_X7, 2, "X7"}, {7, riscv.REG_X8, 3, "X8"}, {8, riscv.REG_X9, 4, "X9"}, {9, riscv.REG_X10, 5, "X10"}, {10, riscv.REG_X11, 6, "X11"}, {11, riscv.REG_X12, 7, "X12"}, {12, riscv.REG_X13, 8, "X13"}, {13, riscv.REG_X14, 9, "X14"}, {14, riscv.REG_X15, 10, "X15"}, {15, riscv.REG_X16, 11, "X16"}, {16, riscv.REG_X17, 12, "X17"}, {17, riscv.REG_X18, 13, "X18"}, {18, riscv.REG_X19, 14, "X19"}, {19, riscv.REG_X20, 15, "X20"}, {20, riscv.REG_X21, 16, "X21"}, {21, riscv.REG_X22, 17, "X22"}, {22, riscv.REG_X23, 18, "X23"}, {23, riscv.REG_X24, 19, "X24"}, {24, riscv.REG_X25, 20, "X25"}, {25, riscv.REG_X26, 21, "X26"}, {26, riscv.REGG, -1, "g"}, {27, riscv.REG_X28, 22, "X28"}, {28, riscv.REG_X29, 23, "X29"}, {29, riscv.REG_X30, 24, "X30"}, {30, riscv.REG_X31, -1, "X31"}, {31, riscv.REG_F0, -1, "F0"}, {32, riscv.REG_F1, -1, "F1"}, {33, riscv.REG_F2, -1, "F2"}, {34, riscv.REG_F3, -1, "F3"}, {35, riscv.REG_F4, -1, "F4"}, {36, riscv.REG_F5, -1, "F5"}, {37, riscv.REG_F6, -1, "F6"}, {38, riscv.REG_F7, -1, "F7"}, {39, riscv.REG_F8, -1, "F8"}, {40, riscv.REG_F9, -1, "F9"}, {41, riscv.REG_F10, -1, "F10"}, {42, riscv.REG_F11, -1, "F11"}, {43, riscv.REG_F12, -1, "F12"}, {44, riscv.REG_F13, -1, "F13"}, {45, riscv.REG_F14, -1, "F14"}, {46, riscv.REG_F15, -1, "F15"}, {47, riscv.REG_F16, -1, "F16"}, {48, riscv.REG_F17, -1, "F17"}, {49, riscv.REG_F18, -1, "F18"}, {50, riscv.REG_F19, -1, "F19"}, {51, riscv.REG_F20, -1, "F20"}, {52, riscv.REG_F21, -1, "F21"}, {53, riscv.REG_F22, -1, "F22"}, {54, riscv.REG_F23, -1, "F23"}, {55, riscv.REG_F24, -1, "F24"}, {56, riscv.REG_F25, -1, "F25"}, {57, riscv.REG_F26, -1, "F26"}, {58, riscv.REG_F27, -1, "F27"}, {59, riscv.REG_F28, -1, "F28"}, {60, riscv.REG_F29, -1, "F29"}, {61, riscv.REG_F30, -1, "F30"}, {62, riscv.REG_F31, -1, "F31"}, {63, 0, -1, "SB"}, } var paramIntRegRISCV64 = []int8{9, 10, 11, 12, 13, 14, 15, 16, 7, 8, 17, 18, 19, 20, 21, 22} var paramFloatRegRISCV64 = []int8{41, 42, 43, 44, 45, 46, 47, 48, 39, 40, 49, 50, 51, 52, 53, 54} var gpRegMaskRISCV64 = regMask(1006632944) var fpRegMaskRISCV64 = regMask(9223372034707292160) var specialRegMaskRISCV64 = regMask(0) var framepointerRegRISCV64 = int8(-1) var linkRegRISCV64 = int8(0) var registersS390X = [...]Register{ {0, s390x.REG_R0, 0, "R0"}, {1, s390x.REG_R1, 1, "R1"}, {2, s390x.REG_R2, 2, "R2"}, {3, s390x.REG_R3, 3, "R3"}, {4, s390x.REG_R4, 4, "R4"}, {5, s390x.REG_R5, 5, "R5"}, {6, s390x.REG_R6, 6, "R6"}, {7, s390x.REG_R7, 7, "R7"}, {8, s390x.REG_R8, 8, "R8"}, {9, s390x.REG_R9, 9, "R9"}, {10, s390x.REG_R10, -1, "R10"}, {11, s390x.REG_R11, 10, "R11"}, {12, s390x.REG_R12, 11, "R12"}, {13, s390x.REGG, -1, "g"}, {14, s390x.REG_R14, 12, "R14"}, {15, s390x.REGSP, -1, "SP"}, {16, s390x.REG_F0, -1, "F0"}, {17, s390x.REG_F1, -1, "F1"}, {18, s390x.REG_F2, -1, "F2"}, {19, s390x.REG_F3, -1, "F3"}, {20, s390x.REG_F4, -1, "F4"}, {21, s390x.REG_F5, -1, "F5"}, {22, s390x.REG_F6, -1, "F6"}, {23, s390x.REG_F7, -1, "F7"}, {24, s390x.REG_F8, -1, "F8"}, {25, s390x.REG_F9, -1, "F9"}, {26, s390x.REG_F10, -1, "F10"}, {27, s390x.REG_F11, -1, "F11"}, {28, s390x.REG_F12, -1, "F12"}, {29, s390x.REG_F13, -1, "F13"}, {30, s390x.REG_F14, -1, "F14"}, {31, s390x.REG_F15, -1, "F15"}, {32, 0, -1, "SB"}, } var paramIntRegS390X = []int8(nil) var paramFloatRegS390X = []int8(nil) var gpRegMaskS390X = regMask(23551) var fpRegMaskS390X = regMask(4294901760) var specialRegMaskS390X = regMask(0) var framepointerRegS390X = int8(-1) var linkRegS390X = int8(14) var registersWasm = [...]Register{ {0, wasm.REG_R0, 0, "R0"}, {1, wasm.REG_R1, 1, "R1"}, {2, wasm.REG_R2, 2, "R2"}, {3, wasm.REG_R3, 3, "R3"}, {4, wasm.REG_R4, 4, "R4"}, {5, wasm.REG_R5, 5, "R5"}, {6, wasm.REG_R6, 6, "R6"}, {7, wasm.REG_R7, 7, "R7"}, {8, wasm.REG_R8, 8, "R8"}, {9, wasm.REG_R9, 9, "R9"}, {10, wasm.REG_R10, 10, "R10"}, {11, wasm.REG_R11, 11, "R11"}, {12, wasm.REG_R12, 12, "R12"}, {13, wasm.REG_R13, 13, "R13"}, {14, wasm.REG_R14, 14, "R14"}, {15, wasm.REG_R15, 15, "R15"}, {16, wasm.REG_F0, -1, "F0"}, {17, wasm.REG_F1, -1, "F1"}, {18, wasm.REG_F2, -1, "F2"}, {19, wasm.REG_F3, -1, "F3"}, {20, wasm.REG_F4, -1, "F4"}, {21, wasm.REG_F5, -1, "F5"}, {22, wasm.REG_F6, -1, "F6"}, {23, wasm.REG_F7, -1, "F7"}, {24, wasm.REG_F8, -1, "F8"}, {25, wasm.REG_F9, -1, "F9"}, {26, wasm.REG_F10, -1, "F10"}, {27, wasm.REG_F11, -1, "F11"}, {28, wasm.REG_F12, -1, "F12"}, {29, wasm.REG_F13, -1, "F13"}, {30, wasm.REG_F14, -1, "F14"}, {31, wasm.REG_F15, -1, "F15"}, {32, wasm.REG_F16, -1, "F16"}, {33, wasm.REG_F17, -1, "F17"}, {34, wasm.REG_F18, -1, "F18"}, {35, wasm.REG_F19, -1, "F19"}, {36, wasm.REG_F20, -1, "F20"}, {37, wasm.REG_F21, -1, "F21"}, {38, wasm.REG_F22, -1, "F22"}, {39, wasm.REG_F23, -1, "F23"}, {40, wasm.REG_F24, -1, "F24"}, {41, wasm.REG_F25, -1, "F25"}, {42, wasm.REG_F26, -1, "F26"}, {43, wasm.REG_F27, -1, "F27"}, {44, wasm.REG_F28, -1, "F28"}, {45, wasm.REG_F29, -1, "F29"}, {46, wasm.REG_F30, -1, "F30"}, {47, wasm.REG_F31, -1, "F31"}, {48, wasm.REGSP, -1, "SP"}, {49, wasm.REGG, -1, "g"}, {50, 0, -1, "SB"}, } var paramIntRegWasm = []int8(nil) var paramFloatRegWasm = []int8(nil) var gpRegMaskWasm = regMask(65535) var fpRegMaskWasm = regMask(281474976645120) var fp32RegMaskWasm = regMask(4294901760) var fp64RegMaskWasm = regMask(281470681743360) var specialRegMaskWasm = regMask(0) var framepointerRegWasm = int8(-1) var linkRegWasm = int8(-1) -- diff -- @@ -6,6 +6,7 @@ "cmd/internal/obj" "cmd/internal/obj/arm" "cmd/internal/obj/arm64" + "cmd/internal/obj/loong64" "cmd/internal/obj/mips" "cmd/internal/obj/ppc64" "cmd/internal/obj/riscv" @@ -92,6 +93,15 @@ BlockARM64GTnoov BlockARM64GEnoov + BlockLOONG64EQ + BlockLOONG64NE + BlockLOONG64LTZ + BlockLOONG64LEZ + BlockLOONG64GTZ + BlockLOONG64GEZ + BlockLOONG64FPT + BlockLOONG64FPF + BlockMIPSEQ BlockMIPSNE BlockMIPSLTZ @@ -232,6 +242,15 @@ BlockARM64GTnoov: "GTnoov", BlockARM64GEnoov: "GEnoov", + BlockLOONG64EQ: "EQ", + BlockLOONG64NE: "NE", + BlockLOONG64LTZ: "LTZ", + BlockLOONG64LEZ: "LEZ", + BlockLOONG64GTZ: "GTZ", + BlockLOONG64GEZ: "GEZ", + BlockLOONG64FPT: "FPT", + BlockLOONG64FPF: "FPF", + BlockMIPSEQ: "EQ", BlockMIPSNE: "NE", BlockMIPSLTZ: "LTZ", @@ -1687,6 +1706,127 @@ OpARM64PRFM OpARM64DMB + OpLOONG64ADDV + OpLOONG64ADDVconst + OpLOONG64SUBV + OpLOONG64SUBVconst + OpLOONG64MULV + OpLOONG64MULVU + OpLOONG64DIVV + OpLOONG64DIVVU + OpLOONG64ADDF + OpLOONG64ADDD + OpLOONG64SUBF + OpLOONG64SUBD + OpLOONG64MULF + OpLOONG64MULD + OpLOONG64DIVF + OpLOONG64DIVD + OpLOONG64AND + OpLOONG64ANDconst + OpLOONG64OR + OpLOONG64ORconst + OpLOONG64XOR + OpLOONG64XORconst + OpLOONG64NOR + OpLOONG64NORconst + OpLOONG64NEGV + OpLOONG64NEGF + OpLOONG64NEGD + OpLOONG64SQRTD + OpLOONG64SQRTF + OpLOONG64SLLV + OpLOONG64SLLVconst + OpLOONG64SRLV + OpLOONG64SRLVconst + OpLOONG64SRAV + OpLOONG64SRAVconst + OpLOONG64SGT + OpLOONG64SGTconst + OpLOONG64SGTU + OpLOONG64SGTUconst + OpLOONG64CMPEQF + OpLOONG64CMPEQD + OpLOONG64CMPGEF + OpLOONG64CMPGED + OpLOONG64CMPGTF + OpLOONG64CMPGTD + OpLOONG64MOVVconst + OpLOONG64MOVFconst + OpLOONG64MOVDconst + OpLOONG64MOVVaddr + OpLOONG64MOVBload + OpLOONG64MOVBUload + OpLOONG64MOVHload + OpLOONG64MOVHUload + OpLOONG64MOVWload + OpLOONG64MOVWUload + OpLOONG64MOVVload + OpLOONG64MOVFload + OpLOONG64MOVDload + OpLOONG64MOVBstore + OpLOONG64MOVHstore + OpLOONG64MOVWstore + OpLOONG64MOVVstore + OpLOONG64MOVFstore + OpLOONG64MOVDstore + OpLOONG64MOVBstorezero + OpLOONG64MOVHstorezero + OpLOONG64MOVWstorezero + OpLOONG64MOVVstorezero + OpLOONG64MOVBreg + OpLOONG64MOVBUreg + OpLOONG64MOVHreg + OpLOONG64MOVHUreg + OpLOONG64MOVWreg + OpLOONG64MOVWUreg + OpLOONG64MOVVreg + OpLOONG64MOVVnop + OpLOONG64MOVWF + OpLOONG64MOVWD + OpLOONG64MOVVF + OpLOONG64MOVVD + OpLOONG64TRUNCFW + OpLOONG64TRUNCDW + OpLOONG64TRUNCFV + OpLOONG64TRUNCDV + OpLOONG64MOVFD + OpLOONG64MOVDF + OpLOONG64CALLstatic + OpLOONG64CALLtail + OpLOONG64CALLclosure + OpLOONG64CALLinter + OpLOONG64DUFFZERO + OpLOONG64DUFFCOPY + OpLOONG64LoweredZero + OpLOONG64LoweredMove + OpLOONG64LoweredAtomicLoad8 + OpLOONG64LoweredAtomicLoad32 + OpLOONG64LoweredAtomicLoad64 + OpLOONG64LoweredAtomicStore8 + OpLOONG64LoweredAtomicStore32 + OpLOONG64LoweredAtomicStore64 + OpLOONG64LoweredAtomicStorezero32 + OpLOONG64LoweredAtomicStorezero64 + OpLOONG64LoweredAtomicExchange32 + OpLOONG64LoweredAtomicExchange64 + OpLOONG64LoweredAtomicAdd32 + OpLOONG64LoweredAtomicAdd64 + OpLOONG64LoweredAtomicAddconst32 + OpLOONG64LoweredAtomicAddconst64 + OpLOONG64LoweredAtomicCas32 + OpLOONG64LoweredAtomicCas64 + OpLOONG64LoweredNilCheck + OpLOONG64FPFlagTrue + OpLOONG64FPFlagFalse + OpLOONG64LoweredGetClosurePtr + OpLOONG64LoweredGetCallerSP + OpLOONG64LoweredGetCallerPC + OpLOONG64LoweredWB + OpLOONG64LoweredPanicBoundsA + OpLOONG64LoweredPanicBoundsB + OpLOONG64LoweredPanicBoundsC + OpMIPSADD OpMIPSADDconst OpMIPSSUB @@ -22657,6 +22797,1643 @@ }, { + name: "ADDV", + argLen: 2, + commutative: true, + asm: loong64.AADDVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ADDVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.AADDVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693244}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SUBV", + argLen: 2, + asm: loong64.ASUBVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SUBVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASUBVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MULV", + argLen: 2, + clobberFlags: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 196608, // R17 R18 + outputs: []outputInfo{ + {0, 65536}, // R17 + {1, 131072}, // R18 + }, + }, + }, + { + name: "MULVU", + argLen: 2, + clobberFlags: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 196608, // R17 R18 + outputs: []outputInfo{ + {0, 65536}, // R17 + {1, 131072}, // R18 + }, + }, + }, + { + name: "DIVV", + argLen: 2, + clobberFlags: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 196608, // R17 R18 + outputs: []outputInfo{ + {0, 65536}, // R17 + {1, 131072}, // R18 + }, + }, + }, + { + name: "DIVVU", + argLen: 2, + clobberFlags: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 196608, // R17 R18 + outputs: []outputInfo{ + {0, 65536}, // R17 + {1, 131072}, // R18 + }, + }, + }, + { + name: "ADDF", + argLen: 2, + commutative: true, + asm: loong64.AADDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "ADDD", + argLen: 2, + commutative: true, + asm: loong64.AADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SUBF", + argLen: 2, + asm: loong64.ASUBF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SUBD", + argLen: 2, + asm: loong64.ASUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MULF", + argLen: 2, + commutative: true, + asm: loong64.AMULF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MULD", + argLen: 2, + commutative: true, + asm: loong64.AMULD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "DIVF", + argLen: 2, + asm: loong64.ADIVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "DIVD", + argLen: 2, + asm: loong64.ADIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + asm: loong64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ANDconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + asm: loong64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ORconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + asm: loong64.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "XORconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "NOR", + argLen: 2, + commutative: true, + asm: loong64.ANOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "NORconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ANOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "NEGV", + argLen: 1, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "NEGF", + argLen: 1, + asm: loong64.ANEGF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "NEGD", + argLen: 1, + asm: loong64.ANEGD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SQRTD", + argLen: 1, + asm: loong64.ASQRTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SQRTF", + argLen: 1, + asm: loong64.ASQRTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SLLV", + argLen: 2, + asm: loong64.ASLLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SLLVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASLLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRLV", + argLen: 2, + asm: loong64.ASRLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRLVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASRLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRAV", + argLen: 2, + asm: loong64.ASRAV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRAVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASRAV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SGT", + argLen: 2, + asm: loong64.ASGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SGTconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SGTU", + argLen: 2, + asm: loong64.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SGTUconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "CMPEQF", + argLen: 2, + asm: loong64.ACMPEQF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPEQD", + argLen: 2, + asm: loong64.ACMPEQD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGEF", + argLen: 2, + asm: loong64.ACMPGEF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGED", + argLen: 2, + asm: loong64.ACMPGED, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGTF", + argLen: 2, + asm: loong64.ACMPGTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGTD", + argLen: 2, + asm: loong64.ACMPGTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + asm: loong64.AMOVV, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVFconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: loong64.AMOVF, + reg: regInfo{ + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: loong64.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + symEffect: SymAddr, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018427387908}, // SP SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVBUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVVload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVFload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVVstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVFstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVHstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVWstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVVstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVBUreg", + argLen: 1, + asm: loong64.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHUreg", + argLen: 1, + asm: loong64.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWUreg", + argLen: 1, + asm: loong64.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVVreg", + argLen: 1, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVVnop", + argLen: 1, + resultInArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWF", + argLen: 1, + asm: loong64.AMOVWF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVWD", + argLen: 1, + asm: loong64.AMOVWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVF", + argLen: 1, + asm: loong64.AMOVVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVD", + argLen: 1, + asm: loong64.AMOVVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCFW", + argLen: 1, + asm: loong64.ATRUNCFW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCDW", + argLen: 1, + asm: loong64.ATRUNCDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCFV", + argLen: 1, + asm: loong64.ATRUNCFV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCDV", + argLen: 1, + asm: loong64.ATRUNCDV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVFD", + argLen: 1, + asm: loong64.AMOVFD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDF", + argLen: 1, + asm: loong64.AMOVDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: 3, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 268435456}, // R29 + {0, 1070596092}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: 2, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "DUFFZERO", + auxType: auxInt64, + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 262146, // R1 R19 + }, + }, + { + name: "DUFFCOPY", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 524288}, // R20 + {1, 262144}, // R19 + }, + clobbers: 786434, // R1 R19 R20 + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 262144}, // R19 + {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 262144, // R19 + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8}, // R4 + {1, 262144}, // R19 + {2, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 262152, // R4 R19 + }, + }, + { + name: "LoweredAtomicLoad8", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicLoad32", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicLoad64", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicStore8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore64", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicStorezero32", + argLen: 2, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicStorezero64", + argLen: 2, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicExchange32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicExchange64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicAdd32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicAdd64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicAddconst32", + auxType: auxInt32, + argLen: 2, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicAddconst64", + auxType: auxInt64, + argLen: 2, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicCas32", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicCas64", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "FPFlagTrue", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "FPFlagFalse", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 268435456}, // R29 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxSym, + argLen: 3, + clobberFlags: true, + symEffect: SymNone, + reg: regInfo{ + inputs: []inputInfo{ + {0, 67108864}, // R27 + {1, 134217728}, // R28 + }, + clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "LoweredPanicBoundsA", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65536}, // R17 + {1, 8}, // R4 + }, + }, + }, + { + name: "LoweredPanicBoundsB", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 131072}, // R18 + {1, 65536}, // R17 + }, + }, + }, + { + name: "LoweredPanicBoundsC", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 262144}, // R19 + {1, 131072}, // R18 + }, + }, + }, + + { name: "ADD", argLen: 2, commutative: true, @@ -37969,6 +39746,78 @@ var specialRegMaskARM64 = regMask(0) var framepointerRegARM64 = int8(-1) var linkRegARM64 = int8(29) +var registersLOONG64 = [...]Register{ + {0, loong64.REG_R0, -1, "R0"}, + {1, loong64.REG_R1, -1, "R1"}, + {2, loong64.REGSP, -1, "SP"}, + {3, loong64.REG_R4, 0, "R4"}, + {4, loong64.REG_R5, 1, "R5"}, + {5, loong64.REG_R6, 2, "R6"}, + {6, loong64.REG_R7, 3, "R7"}, + {7, loong64.REG_R8, 4, "R8"}, + {8, loong64.REG_R9, 5, "R9"}, + {9, loong64.REG_R10, 6, "R10"}, + {10, loong64.REG_R11, 7, "R11"}, + {11, loong64.REG_R12, 8, "R12"}, + {12, loong64.REG_R13, 9, "R13"}, + {13, loong64.REG_R14, 10, "R14"}, + {14, loong64.REG_R15, 11, "R15"}, + {15, loong64.REG_R16, 12, "R16"}, + {16, loong64.REG_R17, 13, "R17"}, + {17, loong64.REG_R18, 14, "R18"}, + {18, loong64.REG_R19, 15, "R19"}, + {19, loong64.REG_R20, 16, "R20"}, + {20, loong64.REG_R21, -1, "R21"}, + {21, loong64.REGG, -1, "g"}, + {22, loong64.REG_R23, 17, "R23"}, + {23, loong64.REG_R24, 18, "R24"}, + {24, loong64.REG_R25, 19, "R25"}, + {25, loong64.REG_R26, 20, "R26"}, + {26, loong64.REG_R27, 21, "R27"}, + {27, loong64.REG_R28, 22, "R28"}, + {28, loong64.REG_R29, 23, "R29"}, + {29, loong64.REG_R31, 24, "R31"}, + {30, loong64.REG_F0, -1, "F0"}, + {31, loong64.REG_F1, -1, "F1"}, + {32, loong64.REG_F2, -1, "F2"}, + {33, loong64.REG_F3, -1, "F3"}, + {34, loong64.REG_F4, -1, "F4"}, + {35, loong64.REG_F5, -1, "F5"}, + {36, loong64.REG_F6, -1, "F6"}, + {37, loong64.REG_F7, -1, "F7"}, + {38, loong64.REG_F8, -1, "F8"}, + {39, loong64.REG_F9, -1, "F9"}, + {40, loong64.REG_F10, -1, "F10"}, + {41, loong64.REG_F11, -1, "F11"}, + {42, loong64.REG_F12, -1, "F12"}, + {43, loong64.REG_F13, -1, "F13"}, + {44, loong64.REG_F14, -1, "F14"}, + {45, loong64.REG_F15, -1, "F15"}, + {46, loong64.REG_F16, -1, "F16"}, + {47, loong64.REG_F17, -1, "F17"}, + {48, loong64.REG_F18, -1, "F18"}, + {49, loong64.REG_F19, -1, "F19"}, + {50, loong64.REG_F20, -1, "F20"}, + {51, loong64.REG_F21, -1, "F21"}, + {52, loong64.REG_F22, -1, "F22"}, + {53, loong64.REG_F23, -1, "F23"}, + {54, loong64.REG_F24, -1, "F24"}, + {55, loong64.REG_F25, -1, "F25"}, + {56, loong64.REG_F26, -1, "F26"}, + {57, loong64.REG_F27, -1, "F27"}, + {58, loong64.REG_F28, -1, "F28"}, + {59, loong64.REG_F29, -1, "F29"}, + {60, loong64.REG_F30, -1, "F30"}, + {61, loong64.REG_F31, -1, "F31"}, + {62, 0, -1, "SB"}, +} +var paramIntRegLOONG64 = []int8{3, 4, 5, 6, 7, 8, 9, 10} +var paramFloatRegLOONG64 = []int8{30, 31, 32, 33, 34, 35, 36, 37} +var gpRegMaskLOONG64 = regMask(1070596088) +var fpRegMaskLOONG64 = regMask(4611686017353646080) +var specialRegMaskLOONG64 = regMask(0) +var framepointerRegLOONG64 = int8(-1) +var linkRegLOONG64 = int8(1) var registersMIPS = [...]Register{ {0, mips.REG_R0, -1, "R0"}, {1, mips.REG_R1, 0, "R1"}, -- diff -- # indent-heuristic: true @@ -6,6 +6,7 @@ "cmd/internal/obj" "cmd/internal/obj/arm" "cmd/internal/obj/arm64" + "cmd/internal/obj/loong64" "cmd/internal/obj/mips" "cmd/internal/obj/ppc64" "cmd/internal/obj/riscv" @@ -92,6 +93,15 @@ BlockARM64GTnoov BlockARM64GEnoov + BlockLOONG64EQ + BlockLOONG64NE + BlockLOONG64LTZ + BlockLOONG64LEZ + BlockLOONG64GTZ + BlockLOONG64GEZ + BlockLOONG64FPT + BlockLOONG64FPF + BlockMIPSEQ BlockMIPSNE BlockMIPSLTZ @@ -232,6 +242,15 @@ BlockARM64GTnoov: "GTnoov", BlockARM64GEnoov: "GEnoov", + BlockLOONG64EQ: "EQ", + BlockLOONG64NE: "NE", + BlockLOONG64LTZ: "LTZ", + BlockLOONG64LEZ: "LEZ", + BlockLOONG64GTZ: "GTZ", + BlockLOONG64GEZ: "GEZ", + BlockLOONG64FPT: "FPT", + BlockLOONG64FPF: "FPF", + BlockMIPSEQ: "EQ", BlockMIPSNE: "NE", BlockMIPSLTZ: "LTZ", @@ -1687,6 +1706,127 @@ OpARM64PRFM OpARM64DMB + OpLOONG64ADDV + OpLOONG64ADDVconst + OpLOONG64SUBV + OpLOONG64SUBVconst + OpLOONG64MULV + OpLOONG64MULVU + OpLOONG64DIVV + OpLOONG64DIVVU + OpLOONG64ADDF + OpLOONG64ADDD + OpLOONG64SUBF + OpLOONG64SUBD + OpLOONG64MULF + OpLOONG64MULD + OpLOONG64DIVF + OpLOONG64DIVD + OpLOONG64AND + OpLOONG64ANDconst + OpLOONG64OR + OpLOONG64ORconst + OpLOONG64XOR + OpLOONG64XORconst + OpLOONG64NOR + OpLOONG64NORconst + OpLOONG64NEGV + OpLOONG64NEGF + OpLOONG64NEGD + OpLOONG64SQRTD + OpLOONG64SQRTF + OpLOONG64SLLV + OpLOONG64SLLVconst + OpLOONG64SRLV + OpLOONG64SRLVconst + OpLOONG64SRAV + OpLOONG64SRAVconst + OpLOONG64SGT + OpLOONG64SGTconst + OpLOONG64SGTU + OpLOONG64SGTUconst + OpLOONG64CMPEQF + OpLOONG64CMPEQD + OpLOONG64CMPGEF + OpLOONG64CMPGED + OpLOONG64CMPGTF + OpLOONG64CMPGTD + OpLOONG64MOVVconst + OpLOONG64MOVFconst + OpLOONG64MOVDconst + OpLOONG64MOVVaddr + OpLOONG64MOVBload + OpLOONG64MOVBUload + OpLOONG64MOVHload + OpLOONG64MOVHUload + OpLOONG64MOVWload + OpLOONG64MOVWUload + OpLOONG64MOVVload + OpLOONG64MOVFload + OpLOONG64MOVDload + OpLOONG64MOVBstore + OpLOONG64MOVHstore + OpLOONG64MOVWstore + OpLOONG64MOVVstore + OpLOONG64MOVFstore + OpLOONG64MOVDstore + OpLOONG64MOVBstorezero + OpLOONG64MOVHstorezero + OpLOONG64MOVWstorezero + OpLOONG64MOVVstorezero + OpLOONG64MOVBreg + OpLOONG64MOVBUreg + OpLOONG64MOVHreg + OpLOONG64MOVHUreg + OpLOONG64MOVWreg + OpLOONG64MOVWUreg + OpLOONG64MOVVreg + OpLOONG64MOVVnop + OpLOONG64MOVWF + OpLOONG64MOVWD + OpLOONG64MOVVF + OpLOONG64MOVVD + OpLOONG64TRUNCFW + OpLOONG64TRUNCDW + OpLOONG64TRUNCFV + OpLOONG64TRUNCDV + OpLOONG64MOVFD + OpLOONG64MOVDF + OpLOONG64CALLstatic + OpLOONG64CALLtail + OpLOONG64CALLclosure + OpLOONG64CALLinter + OpLOONG64DUFFZERO + OpLOONG64DUFFCOPY + OpLOONG64LoweredZero + OpLOONG64LoweredMove + OpLOONG64LoweredAtomicLoad8 + OpLOONG64LoweredAtomicLoad32 + OpLOONG64LoweredAtomicLoad64 + OpLOONG64LoweredAtomicStore8 + OpLOONG64LoweredAtomicStore32 + OpLOONG64LoweredAtomicStore64 + OpLOONG64LoweredAtomicStorezero32 + OpLOONG64LoweredAtomicStorezero64 + OpLOONG64LoweredAtomicExchange32 + OpLOONG64LoweredAtomicExchange64 + OpLOONG64LoweredAtomicAdd32 + OpLOONG64LoweredAtomicAdd64 + OpLOONG64LoweredAtomicAddconst32 + OpLOONG64LoweredAtomicAddconst64 + OpLOONG64LoweredAtomicCas32 + OpLOONG64LoweredAtomicCas64 + OpLOONG64LoweredNilCheck + OpLOONG64FPFlagTrue + OpLOONG64FPFlagFalse + OpLOONG64LoweredGetClosurePtr + OpLOONG64LoweredGetCallerSP + OpLOONG64LoweredGetCallerPC + OpLOONG64LoweredWB + OpLOONG64LoweredPanicBoundsA + OpLOONG64LoweredPanicBoundsB + OpLOONG64LoweredPanicBoundsC + OpMIPSADD OpMIPSADDconst OpMIPSSUB @@ -22656,6 +22796,1643 @@ reg: regInfo{}, }, + { + name: "ADDV", + argLen: 2, + commutative: true, + asm: loong64.AADDVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ADDVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.AADDVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693244}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SUBV", + argLen: 2, + asm: loong64.ASUBVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SUBVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASUBVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MULV", + argLen: 2, + clobberFlags: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 196608, // R17 R18 + outputs: []outputInfo{ + {0, 65536}, // R17 + {1, 131072}, // R18 + }, + }, + }, + { + name: "MULVU", + argLen: 2, + clobberFlags: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 196608, // R17 R18 + outputs: []outputInfo{ + {0, 65536}, // R17 + {1, 131072}, // R18 + }, + }, + }, + { + name: "DIVV", + argLen: 2, + clobberFlags: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 196608, // R17 R18 + outputs: []outputInfo{ + {0, 65536}, // R17 + {1, 131072}, // R18 + }, + }, + }, + { + name: "DIVVU", + argLen: 2, + clobberFlags: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 196608, // R17 R18 + outputs: []outputInfo{ + {0, 65536}, // R17 + {1, 131072}, // R18 + }, + }, + }, + { + name: "ADDF", + argLen: 2, + commutative: true, + asm: loong64.AADDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "ADDD", + argLen: 2, + commutative: true, + asm: loong64.AADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SUBF", + argLen: 2, + asm: loong64.ASUBF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SUBD", + argLen: 2, + asm: loong64.ASUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MULF", + argLen: 2, + commutative: true, + asm: loong64.AMULF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MULD", + argLen: 2, + commutative: true, + asm: loong64.AMULD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "DIVF", + argLen: 2, + asm: loong64.ADIVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "DIVD", + argLen: 2, + asm: loong64.ADIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + asm: loong64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ANDconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + asm: loong64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "ORconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + asm: loong64.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "XORconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "NOR", + argLen: 2, + commutative: true, + asm: loong64.ANOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "NORconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ANOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "NEGV", + argLen: 1, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "NEGF", + argLen: 1, + asm: loong64.ANEGF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "NEGD", + argLen: 1, + asm: loong64.ANEGD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SQRTD", + argLen: 1, + asm: loong64.ASQRTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SQRTF", + argLen: 1, + asm: loong64.ASQRTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SLLV", + argLen: 2, + asm: loong64.ASLLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SLLVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASLLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRLV", + argLen: 2, + asm: loong64.ASRLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRLVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASRLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRAV", + argLen: 2, + asm: loong64.ASRAV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SRAVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASRAV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SGT", + argLen: 2, + asm: loong64.ASGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SGTconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SGTU", + argLen: 2, + asm: loong64.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "SGTUconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "CMPEQF", + argLen: 2, + asm: loong64.ACMPEQF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPEQD", + argLen: 2, + asm: loong64.ACMPEQD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGEF", + argLen: 2, + asm: loong64.ACMPGEF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGED", + argLen: 2, + asm: loong64.ACMPGED, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGTF", + argLen: 2, + asm: loong64.ACMPGTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGTD", + argLen: 2, + asm: loong64.ACMPGTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + asm: loong64.AMOVV, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVFconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: loong64.AMOVF, + reg: regInfo{ + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: loong64.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + symEffect: SymAddr, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018427387908}, // SP SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVBUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVVload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVFload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: loong64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVVstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVFstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVHstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVWstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVVstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVBUreg", + argLen: 1, + asm: loong64.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVHUreg", + argLen: 1, + asm: loong64.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWUreg", + argLen: 1, + asm: loong64.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVVreg", + argLen: 1, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVVnop", + argLen: 1, + resultInArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "MOVWF", + argLen: 1, + asm: loong64.AMOVWF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVWD", + argLen: 1, + asm: loong64.AMOVWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVF", + argLen: 1, + asm: loong64.AMOVVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVD", + argLen: 1, + asm: loong64.AMOVVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCFW", + argLen: 1, + asm: loong64.ATRUNCFW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCDW", + argLen: 1, + asm: loong64.ATRUNCDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCFV", + argLen: 1, + asm: loong64.ATRUNCFV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCDV", + argLen: 1, + asm: loong64.ATRUNCDV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVFD", + argLen: 1, + asm: loong64.AMOVFD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDF", + argLen: 1, + asm: loong64.AMOVDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: 3, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 268435456}, // R29 + {0, 1070596092}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: 2, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "DUFFZERO", + auxType: auxInt64, + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 262146, // R1 R19 + }, + }, + { + name: "DUFFCOPY", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 524288}, // R20 + {1, 262144}, // R19 + }, + clobbers: 786434, // R1 R19 R20 + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 262144}, // R19 + {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 262144, // R19 + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8}, // R4 + {1, 262144}, // R19 + {2, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + clobbers: 262152, // R4 R19 + }, + }, + { + name: "LoweredAtomicLoad8", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicLoad32", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicLoad64", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicStore8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore64", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicStorezero32", + argLen: 2, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicStorezero64", + argLen: 2, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, + { + name: "LoweredAtomicExchange32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicExchange64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicAdd32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicAdd64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicAddconst32", + auxType: auxInt32, + argLen: 2, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicAddconst64", + auxType: auxInt64, + argLen: 2, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicCas32", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredAtomicCas64", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "FPFlagTrue", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "FPFlagFalse", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 268435456}, // R29 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxSym, + argLen: 3, + clobberFlags: true, + symEffect: SymNone, + reg: regInfo{ + inputs: []inputInfo{ + {0, 67108864}, // R27 + {1, 134217728}, // R28 + }, + clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "LoweredPanicBoundsA", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65536}, // R17 + {1, 8}, // R4 + }, + }, + }, + { + name: "LoweredPanicBoundsB", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 131072}, // R18 + {1, 65536}, // R17 + }, + }, + }, + { + name: "LoweredPanicBoundsC", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 262144}, // R19 + {1, 131072}, // R18 + }, + }, + }, + { name: "ADD", argLen: 2, @@ -37969,6 +39746,78 @@ var specialRegMaskARM64 = regMask(0) var framepointerRegARM64 = int8(-1) var linkRegARM64 = int8(29) +var registersLOONG64 = [...]Register{ + {0, loong64.REG_R0, -1, "R0"}, + {1, loong64.REG_R1, -1, "R1"}, + {2, loong64.REGSP, -1, "SP"}, + {3, loong64.REG_R4, 0, "R4"}, + {4, loong64.REG_R5, 1, "R5"}, + {5, loong64.REG_R6, 2, "R6"}, + {6, loong64.REG_R7, 3, "R7"}, + {7, loong64.REG_R8, 4, "R8"}, + {8, loong64.REG_R9, 5, "R9"}, + {9, loong64.REG_R10, 6, "R10"}, + {10, loong64.REG_R11, 7, "R11"}, + {11, loong64.REG_R12, 8, "R12"}, + {12, loong64.REG_R13, 9, "R13"}, + {13, loong64.REG_R14, 10, "R14"}, + {14, loong64.REG_R15, 11, "R15"}, + {15, loong64.REG_R16, 12, "R16"}, + {16, loong64.REG_R17, 13, "R17"}, + {17, loong64.REG_R18, 14, "R18"}, + {18, loong64.REG_R19, 15, "R19"}, + {19, loong64.REG_R20, 16, "R20"}, + {20, loong64.REG_R21, -1, "R21"}, + {21, loong64.REGG, -1, "g"}, + {22, loong64.REG_R23, 17, "R23"}, + {23, loong64.REG_R24, 18, "R24"}, + {24, loong64.REG_R25, 19, "R25"}, + {25, loong64.REG_R26, 20, "R26"}, + {26, loong64.REG_R27, 21, "R27"}, + {27, loong64.REG_R28, 22, "R28"}, + {28, loong64.REG_R29, 23, "R29"}, + {29, loong64.REG_R31, 24, "R31"}, + {30, loong64.REG_F0, -1, "F0"}, + {31, loong64.REG_F1, -1, "F1"}, + {32, loong64.REG_F2, -1, "F2"}, + {33, loong64.REG_F3, -1, "F3"}, + {34, loong64.REG_F4, -1, "F4"}, + {35, loong64.REG_F5, -1, "F5"}, + {36, loong64.REG_F6, -1, "F6"}, + {37, loong64.REG_F7, -1, "F7"}, + {38, loong64.REG_F8, -1, "F8"}, + {39, loong64.REG_F9, -1, "F9"}, + {40, loong64.REG_F10, -1, "F10"}, + {41, loong64.REG_F11, -1, "F11"}, + {42, loong64.REG_F12, -1, "F12"}, + {43, loong64.REG_F13, -1, "F13"}, + {44, loong64.REG_F14, -1, "F14"}, + {45, loong64.REG_F15, -1, "F15"}, + {46, loong64.REG_F16, -1, "F16"}, + {47, loong64.REG_F17, -1, "F17"}, + {48, loong64.REG_F18, -1, "F18"}, + {49, loong64.REG_F19, -1, "F19"}, + {50, loong64.REG_F20, -1, "F20"}, + {51, loong64.REG_F21, -1, "F21"}, + {52, loong64.REG_F22, -1, "F22"}, + {53, loong64.REG_F23, -1, "F23"}, + {54, loong64.REG_F24, -1, "F24"}, + {55, loong64.REG_F25, -1, "F25"}, + {56, loong64.REG_F26, -1, "F26"}, + {57, loong64.REG_F27, -1, "F27"}, + {58, loong64.REG_F28, -1, "F28"}, + {59, loong64.REG_F29, -1, "F29"}, + {60, loong64.REG_F30, -1, "F30"}, + {61, loong64.REG_F31, -1, "F31"}, + {62, 0, -1, "SB"}, +} +var paramIntRegLOONG64 = []int8{3, 4, 5, 6, 7, 8, 9, 10} +var paramFloatRegLOONG64 = []int8{30, 31, 32, 33, 34, 35, 36, 37} +var gpRegMaskLOONG64 = regMask(1070596088) +var fpRegMaskLOONG64 = regMask(4611686017353646080) +var specialRegMaskLOONG64 = regMask(0) +var framepointerRegLOONG64 = int8(-1) +var linkRegLOONG64 = int8(1) var registersMIPS = [...]Register{ {0, mips.REG_R0, -1, "R0"}, {1, mips.REG_R1, 0, "R1"}, diff-1.0.1/textdiff/testdata/if_chain.test000066400000000000000000000015671516001707200205200ustar00rootroot00000000000000-- x -- package main import "os" func main() { if os.Args[1] == "fizz" { fizz() } if os.Args[1] == "help" { help() } } -- y -- package main import "os" func main() { if os.Args[1] == "fizz" { fizz() } if os.Args[1] == "buzz" { buzz() } if os.Args[1] == "help" { help() } } -- diff -- @@ -7,6 +7,10 @@ fizz() } + if os.Args[1] == "buzz" { + buzz() + } + if os.Args[1] == "help" { help() } -- diff -- # fast: true @@ -7,6 +7,10 @@ fizz() } + if os.Args[1] == "buzz" { + buzz() + } + if os.Args[1] == "help" { help() } -- diff -- # indent-heuristic: true @@ -7,6 +7,10 @@ fizz() } + if os.Args[1] == "buzz" { + buzz() + } + if os.Args[1] == "help" { help() } diff-1.0.1/textdiff/testdata/if_chain_repeated_check.test000066400000000000000000000016541516001707200235230ustar00rootroot00000000000000-- x -- package main import "os" func main() { if os.Args[1] == "foo" { foo() } } -- y -- package main import "os" func main() { if os.Args[1] == "foo" { // ... } if os.Args[1] == "foo" { foo() } } -- diff -- @@ -4,6 +4,9 @@ func main() { if os.Args[1] == "foo" { + // ... + } + if os.Args[1] == "foo" { foo() } } -- diff -- # force-anchoring-heuristic: true @@ -4,6 +4,9 @@ func main() { if os.Args[1] == "foo" { + // ... + } + if os.Args[1] == "foo" { foo() } } -- diff -- # fast: true @@ -4,6 +4,9 @@ func main() { if os.Args[1] == "foo" { + // ... + } + if os.Args[1] == "foo" { foo() } } -- diff -- # indent-heuristic: true @@ -3,6 +3,9 @@ import "os" func main() { + if os.Args[1] == "foo" { + // ... + } if os.Args[1] == "foo" { foo() } diff-1.0.1/textdiff/testdata/map_do.test000066400000000000000000000020031516001707200202010ustar00rootroot00000000000000From https://stackoverflow.com/questions/37895083/new-git-diff-compaction-heuristic-isnt-working -- x -- ["foo", "bar", "baz"].map do |i| i.upcase end -- y -- ["foo", "bar", "baz"].map do |i| i end ["foo", "bar", "baz"].map do |i| i.upcase end -- diff -- @@ -1,3 +1,7 @@ ["foo", "bar", "baz"].map do |i| + i +end + +["foo", "bar", "baz"].map do |i| i.upcase end -- diff -- # indent-heuristic: true @@ -1,3 +1,7 @@ +["foo", "bar", "baz"].map do |i| + i +end + ["foo", "bar", "baz"].map do |i| i.upcase end -- diff -- # force-anchoring-heuristic: true @@ -1,3 +1,7 @@ ["foo", "bar", "baz"].map do |i| + i +end + +["foo", "bar", "baz"].map do |i| i.upcase end -- diff -- # force-anchoring-heuristic: true # indent-heuristic: true @@ -1,3 +1,7 @@ +["foo", "bar", "baz"].map do |i| + i +end + ["foo", "bar", "baz"].map do |i| i.upcase end -- diff -- # fast: true # indent-heuristic: true @@ -1,3 +1,7 @@ +["foo", "bar", "baz"].map do |i| + i +end + ["foo", "bar", "baz"].map do |i| i.upcase end diff-1.0.1/textdiff/textdiff.go000066400000000000000000000236711516001707200164120ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // Package textdiff provides functions to efficiently compare text line-by-line. // // This package is specialized for text comparison and provides unified diff output like the Unix // diff command. The main functions are [Hunks] for grouped changes, [Edits] for individual changes, // and [Unified] for standard diff format output. // // Performance: Default complexity is O(N^1.5 log N) time and O(N) space. With [diff.Minimal], time // complexity becomes O(ND) where N = len(x) + len(y) and D is the number of edits. package textdiff import ( "fmt" "slices" "znkr.io/diff" "znkr.io/diff/internal/byteview" "znkr.io/diff/internal/config" "znkr.io/diff/internal/impl" "znkr.io/diff/internal/indentheuristic" "znkr.io/diff/internal/rvecs" ) // Edit describes a single edit of a line-by-line diff. // // - For Match, Line contains the matching line. LineNoX and LineNoY contain the respective // line numbers (zero-based) in the input. // - For Delete, Line contains the deleted line from x. LineNoX contains the line number in x // and LineNoY is -1. // - For Insert, Line contains the inserted line from y. LineNoY contains the line number in y // and LineNoX is -1. type Edit[T string | []byte] struct { Op diff.Op LineNoX, LineNoY int Line T } // Hunk describes a sequence of consecutive edits. type Hunk[T string | []byte] struct { LineNoX, EndLineNoX int // Start and end line in x (zero-based). LineNoY, EndLineNoY int // Start and end line in y (zero-based). Edits []Edit[T] // Edits to transform x lines LineNoX..EndLineNoX to y lines LineNoY..EndLineNoY } // Hunks compares the lines in x and y and returns the changes necessary to convert from one to the // other. // // The output is a sequence of hunks that each describe a number of consecutive edits. Hunks include // a number of matching elements before and after the last delete or insert operation. The number of // elements can be configured using [diff.Context]. // // If x and y are identical, the output has length zero. // // The following options are supported: [diff.Context], [diff.Minimal], [diff.Fast], // [IndentHeuristic] // // Important: The output is not guaranteed to be stable and may change with minor version upgrades. // DO NOT rely on the output being stable. func Hunks[T string | []byte](x, y T, opts ...Option) []Hunk[T] { cfg := config.FromOptions(opts, config.Context|config.Minimal|config.Fast|config.IndentHeuristic) xlines, _ := byteview.SplitLines(byteview.From(x)) ylines, _ := byteview.SplitLines(byteview.From(y)) rx, ry := impl.Diff(xlines, ylines, cfg) if cfg.IndentHeuristic { indentheuristic.Apply(xlines, ylines, rx, ry) } return hunks[T](xlines, ylines, rx, ry, cfg) } func hunks[T string | []byte](x, y []byteview.ByteView, rx, ry []bool, cfg config.Config) []Hunk[T] { // Compute the number of hunks and edits, this is relatively cheap and allows us to preallocate // the return values. var nhunks, nedits int for hunk := range rvecs.Hunks(rx, ry, cfg) { nhunks++ nedits += hunk.Edits } if nhunks == 0 { return nil } eout := make([]Edit[T], 0, nedits) hout := make([]Hunk[T], 0, nhunks) for hunk := range rvecs.Hunks(rx, ry, cfg) { for s, t := hunk.S0, hunk.T0; s < hunk.S1 || t < hunk.T1; { for s < hunk.S1 && rx[s] { eout = append(eout, Edit[T]{ Op: diff.Delete, Line: byteview.UnsafeAs[T](x[s]), LineNoX: s, LineNoY: -1, }) s++ } for t < hunk.T1 && ry[t] { eout = append(eout, Edit[T]{ Op: diff.Insert, Line: byteview.UnsafeAs[T](y[t]), LineNoX: -1, LineNoY: t, }) t++ } for s < hunk.S1 && t < hunk.T1 && !rx[s] && !ry[t] { eout = append(eout, Edit[T]{ Op: diff.Match, Line: byteview.UnsafeAs[T](x[s]), LineNoX: s, LineNoY: t, }) s++ t++ } } hout = append(hout, Hunk[T]{ LineNoX: hunk.S0, EndLineNoX: hunk.S1, LineNoY: hunk.T0, EndLineNoY: hunk.T1, Edits: slices.Clip(eout), }) eout = eout[len(eout):] } return hout } // Edits compares the lines in x and y and returns the changes necessary to convert from one to the // other. // // Edits returns edits for every element in the input. If x and y are identical, the output will // consist of a match edit for every input element. // // The following options are supported: [diff.Minimal], [diff.Fast], [IndentHeuristic] // // Important: The output is not guaranteed to be stable and may change with minor version upgrades. // DO NOT rely on the output being stable. func Edits[T string | []byte](x, y T, opts ...Option) []Edit[T] { cfg := config.FromOptions(opts, config.Minimal|config.Fast|config.IndentHeuristic) xlines, _ := byteview.SplitLines(byteview.From(x)) ylines, _ := byteview.SplitLines(byteview.From(y)) rx, ry := impl.Diff(xlines, ylines, cfg) if cfg.IndentHeuristic { indentheuristic.Apply(xlines, ylines, rx, ry) } return edits[T](xlines, ylines, rx, ry) } func edits[T string | []byte](x, y []byteview.ByteView, rx, ry []bool) []Edit[T] { // Compute the number of edits, this is relatively cheap and allows us to preallocate the return // value. n, m := len(rx)-1, len(ry)-1 var nedits int for s, t := 0, 0; s < n || t < m; { for s < n && rx[s] { nedits++ s++ } for t < m && ry[t] { nedits++ t++ } for s < n && t < m && !rx[s] && !ry[t] { nedits++ s++ t++ } } if nedits == 0 { return nil } eout := make([]Edit[T], 0, nedits) for s, t := 0, 0; s < n || t < m; { for s < n && rx[s] { eout = append(eout, Edit[T]{ Op: diff.Delete, Line: byteview.UnsafeAs[T](x[s]), LineNoX: s, LineNoY: -1, }) s++ } for t < m && ry[t] { eout = append(eout, Edit[T]{ Op: diff.Insert, Line: byteview.UnsafeAs[T](y[t]), LineNoX: -1, LineNoY: t, }) t++ } for s < n && t < m && !rx[s] && !ry[t] { eout = append(eout, Edit[T]{ Op: diff.Match, Line: byteview.UnsafeAs[T](x[s]), LineNoX: s, LineNoY: t, }) s++ t++ } } return eout } const ( prefixMatch = " " prefixDelete = "-" prefixInsert = "+" ) const missingNewline = "\n\\ No newline at end of file\n" // Unified compares the lines in x and y and returns the changes necessary to convert from one to // the other in unified format. // // The following options are supported: [diff.Context], [diff.Minimal], [diff.Fast], // [IndentHeuristic], [TerminalColors] // // Important: The output is not guaranteed to be stable and may change with minor version upgrades. // DO NOT rely on the output being stable. func Unified[T string | []byte](x, y T, opts ...Option) T { cfg := config.FromOptions(opts, config.Context|config.Minimal|config.Fast|config.IndentHeuristic|config.TerminalColors) xlines, xMissingNewline := byteview.SplitLines(byteview.From(x)) ylines, yMissingNewline := byteview.SplitLines(byteview.From(y)) rx, ry := impl.Diff(xlines, ylines, cfg) if cfg.IndentHeuristic { indentheuristic.Apply(xlines, ylines, rx, ry) } var colors config.ColorConfig if cfg.Colors != nil { colors = *cfg.Colors } // Precompute output buffer size. n := 0 for h := range rvecs.Hunks(rx, ry, cfg) { n += len("@@ -, +, @@\n") n += numDigits(h.S0+1) + numDigits(h.S1-h.S0) + numDigits(h.T0+1) + numDigits(h.T1-h.T0) n += len(colors.HunkHeader) + len(colors.Reset) for s, t := h.S0, h.T0; s < h.S1 || t < h.T1; { if s < h.S1 && rx[s] { n += len(colors.Delete) + len(colors.Reset) for s < h.S1 && rx[s] { n += 1 + xlines[s].Len() s++ } } if t < h.T1 && ry[t] { n += len(colors.Insert) + len(colors.Reset) for t < h.T1 && ry[t] { n += 1 + ylines[t].Len() t++ } } if s < h.S1 && t < h.T1 && !rx[s] && !ry[t] { n += len(colors.Match) + len(colors.Reset) for s < h.S1 && t < h.T1 && !rx[s] && !ry[t] { n += 1 + xlines[s].Len() s++ t++ } } } } if xMissingNewline >= 0 { n += len(missingNewline) } if yMissingNewline >= 0 { n += len(missingNewline) } // Format output. var b byteview.Builder[T] b.Grow(n) for h := range rvecs.Hunks(rx, ry, cfg) { fmt.Fprintf(&b, "%s@@ -%d,%d +%d,%d @@%s\n", colors.HunkHeader, h.S0+1, h.S1-h.S0, h.T0+1, h.T1-h.T0, colors.Reset) for s, t := h.S0, h.T0; s < h.S1 || t < h.T1; { if s < h.S1 && rx[s] { b.WriteString(colors.Delete) for s < h.S1 && rx[s] { b.WriteString(prefixDelete) b.WriteByteView(xlines[s]) if s == xMissingNewline { b.WriteString(missingNewline) } s++ } b.WriteString(colors.Reset) } if t < h.T1 && ry[t] { b.WriteString(colors.Insert) for t < h.T1 && ry[t] { b.WriteString(prefixInsert) b.WriteByteView(ylines[t]) if t == yMissingNewline { b.WriteString(missingNewline) } t++ } b.WriteString(colors.Reset) } if s < h.S1 && t < h.T1 && !rx[s] && !ry[t] { b.WriteString(colors.Match) for s < h.S1 && t < h.T1 && !rx[s] && !ry[t] { b.WriteString(prefixMatch) b.WriteByteView(xlines[s]) if s == xMissingNewline { b.WriteString(missingNewline) } s++ t++ } b.WriteString(colors.Reset) } } } return b.Build() } func numDigits(v int) (n int) { switch { case v < 10: return 1 case v < 100: return 2 case v < 1000: return 3 case v < 10_000: return 4 case v < 100_000: return 5 default: for ; v > 0; v /= 10 { n++ } return n } } diff-1.0.1/textdiff/textdiff_test.go000066400000000000000000000450431516001707200174460ustar00rootroot00000000000000// Copyright 2025 Florian Zenker (flo@znkr.io) // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. package textdiff import ( "bytes" "flag" "os" "path/filepath" "strconv" "strings" "testing" "github.com/google/go-cmp/cmp" "golang.org/x/tools/txtar" "znkr.io/diff" "znkr.io/diff/internal/config" "znkr.io/diff/internal/unixpatch" "znkr.io/diff/textdiff/color" ) var ( update = flag.Bool("update", false, "update golden files") validate = flag.Bool("validate", false, "perform validation using the unix patch cli tool") ) func TestUnified(t *testing.T) { for _, tt := range parseTests(t) { t.Run(tt.name, func(t *testing.T) { t.Parallel() for sti, st := range tt.subtests { t.Run(st.name, func(t *testing.T) { t.Parallel() got := Unified(tt.x, tt.y, st.opts...) if diff := cmp.Diff(st.want, got); diff != "" { t.Errorf("Unified(...) result are different:\ngot:\n%s\nwant:\n%s\ndiff [-got,+want]:\n%s", got, st.want, diff) } if *validate && len(got) > 0 { patched, err := unixpatch.Patch(string(tt.x), string(got)) if err != nil { t.Fatalf("failed to run patch: %v", err) } if diff := cmp.Diff(tt.y, []byte(patched)); diff != "" { t.Errorf("file is different after applying patch [-got,+want]:\n%s", diff) } } if *update { tt.subtests[sti].want = got } }) } // Run in a cleanup to makes sure to runs after the subtests have finished. t.Cleanup(func() { if *update { f, err := os.CreateTemp("", "test-unified-*") if err != nil { t.Fatalf("failed to create temporary file: %v", err) } defer f.Close() write := func(b []byte) { t.Helper() _, err := f.Write(b) if err != nil { t.Fatalf("error writing golden file: %v", err) } } write(tt.comment) write([]byte("-- x --\n")) write(tt.x) write([]byte("-- y --\n")) write(tt.y) for _, st := range tt.subtests { write([]byte("-- diff --\n")) write(st.pragmas) write(st.want) } if err := f.Close(); err != nil { t.Fatalf("error closing golden file: %v", err) } if err := os.Rename(f.Name(), tt.filename); err != nil { t.Fatalf("error renaming golden file: %v", err) } } }) }) } } func TestUnifiedEdgeCases(t *testing.T) { tests := []struct { name string x, y string want string }{ { name: "empty", x: "", y: "", want: "", }, { name: "identical", x: "first line\n", y: "first line\n", want: "", }, { name: "new-lines-only", x: "\n", y: "\n", want: "", }, { name: "x-empty", x: "", y: "one-line\n", want: "@@ -1,0 +1,1 @@\n+one-line\n", }, { name: "y-empty", x: "one-line\n", y: "", want: "@@ -1,1 +1,0 @@\n-one-line\n", }, { name: "missing-newline-x", x: "first line", y: "first line\n", want: "@@ -1,1 +1,1 @@\n-first line\n\\ No newline at end of file\n+first line\n", }, { name: "missing-newline-y", x: "first line\n", y: "first line", want: "@@ -1,1 +1,1 @@\n-first line\n+first line\n\\ No newline at end of file\n", }, { name: "missing-newline-both", x: "a\nsecond line", y: "b\nsecond line", want: "@@ -1,2 +1,2 @@\n-a\n+b\n second line\n\\ No newline at end of file\n", }, { name: "missing-newline-empty-x", x: "", y: "\n", want: "@@ -1,0 +1,1 @@\n+\n", // no missing newline note here }, { name: "missing-newline-empty-y", x: "\n", y: "", want: "@@ -1,1 +1,0 @@\n-\n", // no missing newline note here }, } for _, tt := range tests { t.Run(tt.name, func(t *testing.T) { got := Unified(tt.x, tt.y) if got != tt.want { t.Errorf("Unified(...) if different:\ngot: %q\nwant: %q", got, tt.want) } if *validate && len(got) > 0 { patched, err := unixpatch.Patch(tt.x, got) if err != nil { t.Fatalf("failed to run patch: %v", err) } if diff := cmp.Diff(tt.y, patched); diff != "" { t.Errorf("file is different after applying patch [-got,+want]:\n%s", diff) } } }) } } func TestUnifiedColors(t *testing.T) { tests := []struct { name string x, y string opts []diff.Option want string }{ { name: "no-colors", x: `this paragraph stays but is not long enough to create a new hunk this paragraph is going to be removed `, y: `this is a new paragraph that is inserted at the top this paragraph stays but is not long enough to create a new hunk `, want: `@@ -1,9 +1,8 @@ +this is a new paragraph +that is inserted at the top + this paragraph stays but is not long enough to create a new hunk - -this paragraph -is going to be -removed `, }, { name: "default-colors", x: `this paragraph stays but is not long enough to create a new hunk this paragraph is going to be removed `, y: `this is a new paragraph that is inserted at the top this paragraph stays but is not long enough to create a new hunk `, opts: []diff.Option{TerminalColors()}, want: "\x1b[36m" + `@@ -1,9 +1,8 @@` + "\x1b[m" + ` ` + "\x1b[32m" + `+this is a new paragraph +that is inserted at the top + ` + "\x1b[m" + ` this paragraph stays but is not long enough to create a new hunk ` + "\x1b[m\x1b[31m" + `- -this paragraph -is going to be -removed ` + "\x1b[m", }, { name: "custom-colors", x: `this paragraph stays but is not long enough to create a new hunk this paragraph is going to be removed `, y: `this is a new paragraph that is inserted at the top this paragraph stays but is not long enough to create a new hunk `, opts: []diff.Option{TerminalColors( color.HunkHeaders(33), // Yellow color.Matches(1, 33), // Bold Yellow color.Deletes(34), // Blue color.Inserts(35), // Magenta )}, want: "\x1b[33m" + `@@ -1,9 +1,8 @@` + "\x1b[m" + ` ` + "\x1b[35m" + `+this is a new paragraph +that is inserted at the top + ` + "\x1b[m\x1b[1;33m" + ` this paragraph stays but is not long enough to create a new hunk ` + "\x1b[m\x1b[34m" + `- -this paragraph -is going to be -removed ` + "\x1b[m", }, } for _, tt := range tests { t.Run(tt.name, func(t *testing.T) { got := Unified(tt.x, tt.y, tt.opts...) if diff := cmp.Diff(tt.want, got); diff != "" { t.Errorf("Unified(...) result are different:\ngot:\n%s\nwant:\n%s\ndiff [-got,+want]:\n%s", got, tt.want, diff) } }) } } func BenchmarkUnified(b *testing.B) { for _, tt := range parseTests(b) { b.Run(tt.name, func(b *testing.B) { for _, st := range tt.subtests { b.Run(st.name, func(b *testing.B) { b.ReportAllocs() for b.Loop() { _ = Unified(tt.x, tt.y, st.opts...) } }) } }) } } func TestHunks(t *testing.T) { tests := []struct { name string x, y string opts []diff.Option want []Hunk[string] }{ { name: "identical", x: "foo\nbar\nbaz\n", y: "foo\nbar\nbaz\n", want: nil, }, { name: "empty", want: nil, }, { name: "x-empty", y: "foo\nbar\nbaz\n", want: []Hunk[string]{ { LineNoX: 0, LineNoY: 0, EndLineNoX: 0, EndLineNoY: 3, Edits: []Edit[string]{ {diff.Insert, -1, 0, "foo\n"}, {diff.Insert, -1, 1, "bar\n"}, {diff.Insert, -1, 2, "baz\n"}, }, }, }, }, { name: "y-empty", x: "foo\nbar\nbaz\n", want: []Hunk[string]{ { LineNoX: 0, LineNoY: 0, EndLineNoX: 3, EndLineNoY: 0, Edits: []Edit[string]{ {diff.Delete, 0, -1, "foo\n"}, {diff.Delete, 1, -1, "bar\n"}, {diff.Delete, 2, -1, "baz\n"}, }, }, }, }, { name: "same-prefix", x: "foo\nbar\n", y: "foo\nbaz\n", want: []Hunk[string]{ { LineNoX: 0, EndLineNoX: 2, LineNoY: 0, EndLineNoY: 2, Edits: []Edit[string]{ {diff.Match, 0, 0, "foo\n"}, {diff.Delete, 1, -1, "bar\n"}, {diff.Insert, -1, 1, "baz\n"}, }, }, }, }, { name: "same-suffix", x: "foo\nbar\n", y: "loo\nbar\n", want: []Hunk[string]{ { LineNoX: 0, EndLineNoX: 2, LineNoY: 0, EndLineNoY: 2, Edits: []Edit[string]{ {diff.Delete, 0, -1, "foo\n"}, {diff.Insert, -1, 0, "loo\n"}, {diff.Match, 1, 1, "bar\n"}, }, }, }, }, { name: "ABCABBA_to_CBABAC", x: "A\nB\nC\nA\nB\nB\nA\n", y: "C\nB\nA\nB\nA\nC\n", want: []Hunk[string]{ { LineNoX: 0, LineNoY: 0, EndLineNoX: 7, EndLineNoY: 6, Edits: []Edit[string]{ {diff.Delete, 0, -1, "A\n"}, {diff.Insert, -1, 0, "C\n"}, {diff.Match, 1, 1, "B\n"}, {diff.Delete, 2, -1, "C\n"}, {diff.Match, 3, 2, "A\n"}, {diff.Match, 4, 3, "B\n"}, {diff.Delete, 5, -1, "B\n"}, {diff.Match, 6, 4, "A\n"}, {diff.Insert, -1, 5, "C\n"}, }, }, }, }, { name: "ABCABBA_to_CBABAC_no_context", x: "A\nB\nC\nA\nB\nB\nA\n", y: "C\nB\nA\nB\nA\nC\n", opts: []diff.Option{diff.Context(0)}, want: []Hunk[string]{ { LineNoX: 0, LineNoY: 0, EndLineNoX: 1, EndLineNoY: 1, Edits: []Edit[string]{ {diff.Delete, 0, -1, "A\n"}, {diff.Insert, -1, 0, "C\n"}, }, }, { LineNoX: 2, LineNoY: 2, EndLineNoX: 3, EndLineNoY: 2, Edits: []Edit[string]{ {diff.Delete, 2, -1, "C\n"}, }, }, { LineNoX: 5, LineNoY: 4, EndLineNoX: 6, EndLineNoY: 4, Edits: []Edit[string]{ {diff.Delete, 5, -1, "B\n"}, }, }, { LineNoX: 7, LineNoY: 5, EndLineNoX: 7, EndLineNoY: 6, Edits: []Edit[string]{ {diff.Insert, -1, 5, "C\n"}, }, }, }, }, { name: "two-hunks", x: `this paragraph is not changed and barely long enough to create a new hunk this paragraph is going to be removed `, y: `this is a new paragraph that is inserted at the top this paragraph is not changed and barely long enough to create a new hunk `, want: []Hunk[string]{ { LineNoX: 0, EndLineNoX: 3, LineNoY: 0, EndLineNoY: 6, Edits: []Edit[string]{ {diff.Insert, -1, 0, "this is a new paragraph\n"}, {diff.Insert, -1, 1, "that is inserted at the top\n"}, {diff.Insert, -1, 2, "\n"}, {diff.Match, 0, 3, "this paragraph\n"}, {diff.Match, 1, 4, "is not\n"}, {diff.Match, 2, 5, "changed and\n"}, }, }, { LineNoX: 4, EndLineNoX: 11, LineNoY: 7, EndLineNoY: 10, Edits: []Edit[string]{ {diff.Match, 4, 7, "enough to\n"}, {diff.Match, 5, 8, "create a\n"}, {diff.Match, 6, 9, "new hunk\n"}, {diff.Delete, 7, -1, "\n"}, {diff.Delete, 8, -1, "this paragraph\n"}, {diff.Delete, 9, -1, "is going to be\n"}, {diff.Delete, 10, -1, "removed\n"}, }, }, }, }, { name: "overlapping-consecutive-hunks-are-merged", x: `this paragraph stays but is not long enough to create a new hunk this paragraph is going to be removed `, y: `this is a new paragraph that is inserted at the top this paragraph stays but is not long enough to create a new hunk `, want: []Hunk[string]{ { LineNoX: 0, EndLineNoX: 9, LineNoY: 0, EndLineNoY: 8, Edits: []Edit[string]{ {diff.Insert, -1, 0, "this is a new paragraph\n"}, {diff.Insert, -1, 1, "that is inserted at the top\n"}, {diff.Insert, -1, 2, "\n"}, {diff.Match, 0, 3, "this paragraph\n"}, {diff.Match, 1, 4, "stays but is\n"}, {diff.Match, 2, 5, "not long enough\n"}, {diff.Match, 3, 6, "to create a\n"}, {diff.Match, 4, 7, "new hunk\n"}, {diff.Delete, 5, -1, "\n"}, {diff.Delete, 6, -1, "this paragraph\n"}, {diff.Delete, 7, -1, "is going to be\n"}, {diff.Delete, 8, -1, "removed\n"}, }, }, }, }, { name: "indent-heuristic", x: `["foo", "bar", "baz"].map do |i| i.upcase end `, y: `["foo", "bar", "baz"].map do |i| i end ["foo", "bar", "baz"].map do |i| i.upcase end `, opts: []diff.Option{IndentHeuristic()}, want: []Hunk[string]{ { LineNoX: 0, EndLineNoX: 3, LineNoY: 0, EndLineNoY: 7, Edits: []Edit[string]{ {diff.Insert, -1, 0, `["foo", "bar", "baz"].map do |i|` + "\n"}, {diff.Insert, -1, 1, ` i` + "\n"}, {diff.Insert, -1, 2, `end` + "\n"}, {diff.Insert, -1, 3, "\n"}, {diff.Match, 0, 4, `["foo", "bar", "baz"].map do |i|` + "\n"}, {diff.Match, 1, 5, ` i.upcase` + "\n"}, {diff.Match, 2, 6, `end` + "\n"}, }, }, }, }, } for _, tt := range tests { t.Run(tt.name, func(t *testing.T) { got := Hunks(tt.x, tt.y, tt.opts...) if diff := cmp.Diff(tt.want, got); diff != "" { t.Errorf("HunksFunc(...) result is different [-want, +got]:\n%s", diff) } }) } } func TestEdits(t *testing.T) { tests := []struct { name string x, y string opts []diff.Option want []Edit[string] }{ { name: "identical", x: "foo\nbar\nbaz\n", y: "foo\nbar\nbaz\n", want: []Edit[string]{ {diff.Match, 0, 0, "foo\n"}, {diff.Match, 1, 1, "bar\n"}, {diff.Match, 2, 2, "baz\n"}, }, }, { name: "empty", }, { name: "x-empty", y: "foo\nbar\nbaz\n", want: []Edit[string]{ {diff.Insert, -1, 0, "foo\n"}, {diff.Insert, -1, 1, "bar\n"}, {diff.Insert, -1, 2, "baz\n"}, }, }, { name: "y-empty", x: "foo\nbar\nbaz\n", want: []Edit[string]{ {diff.Delete, 0, -1, "foo\n"}, {diff.Delete, 1, -1, "bar\n"}, {diff.Delete, 2, -1, "baz\n"}, }, }, { name: "ABCABBA_to_CBABAC", x: "A\nB\nC\nA\nB\nB\nA\n", y: "C\nB\nA\nB\nA\nC\n", want: []Edit[string]{ {diff.Delete, 0, -1, "A\n"}, {diff.Insert, -1, 0, "C\n"}, {diff.Match, 1, 1, "B\n"}, {diff.Delete, 2, -1, "C\n"}, {diff.Match, 3, 2, "A\n"}, {diff.Match, 4, 3, "B\n"}, {diff.Delete, 5, -1, "B\n"}, {diff.Match, 6, 4, "A\n"}, {diff.Insert, -1, 5, "C\n"}, }, }, { name: "same-prefix", x: "foo\nbar\n", y: "foo\nbaz\n", want: []Edit[string]{ {diff.Match, 0, 0, "foo\n"}, {diff.Delete, 1, -1, "bar\n"}, {diff.Insert, -1, 1, "baz\n"}, }, }, { name: "same-suffix", x: "foo\nbar\n", y: "loo\nbar\n", want: []Edit[string]{ {diff.Delete, 0, -1, "foo\n"}, {diff.Insert, -1, 0, "loo\n"}, {diff.Match, 1, 1, "bar\n"}, }, }, { name: "indent-heuristic", x: `["foo", "bar", "baz"].map do |i| i.upcase end `, y: `["foo", "bar", "baz"].map do |i| i end ["foo", "bar", "baz"].map do |i| i.upcase end `, opts: []diff.Option{IndentHeuristic()}, want: []Edit[string]{ {diff.Insert, -1, 0, `["foo", "bar", "baz"].map do |i|` + "\n"}, {diff.Insert, -1, 1, ` i` + "\n"}, {diff.Insert, -1, 2, `end` + "\n"}, {diff.Insert, -1, 3, "\n"}, {diff.Match, 0, 4, `["foo", "bar", "baz"].map do |i|` + "\n"}, {diff.Match, 1, 5, ` i.upcase` + "\n"}, {diff.Match, 2, 6, `end` + "\n"}, }, }, } for _, tt := range tests { t.Run(tt.name, func(t *testing.T) { got := Edits(tt.x, tt.y, tt.opts...) if diff := cmp.Diff(tt.want, got); diff != "" { t.Errorf("Edits(...) result is different (-want, +got):\n%s", diff) } }) } } type test struct { name string filename string comment []byte x, y []byte subtests []subtest } type subtest struct { name string opts []config.Option pragmas []byte want []byte } func parseTests(t testing.TB) []test { t.Helper() testFiles, err := filepath.Glob("testdata/*.test") if err != nil { t.Fatalf("Failed to read testdata: %v", err) } var tests []test for _, filename := range testFiles { ar, err := txtar.ParseFile(filename) if err != nil { t.Fatalf("failed to parse test case: %v", err) } name := strings.TrimPrefix(filename, "testdata/") test := test{ name: name, filename: filename, comment: ar.Comment, } for _, f := range ar.Files { switch f.Name { case "x": test.x = f.Data case "y": test.y = f.Data case "diff": data := f.Data var st subtest var name []string i := 0 for ; i < len(data); i++ { if data[i] != '#' { break } i++ eol := i + bytes.IndexByte(data[i:], '\n') if eol < i { t.Fatal("failed to parse test case: missing newline after pragma line") } k, v, found := bytes.Cut(data[i:eol], []byte{':'}) if !found { t.Fatal("failed to parse test case: missing ':' in pragma line") } switch k, v := strings.TrimSpace(string(k)), strings.TrimSpace(string(v)); k { case "indent-heuristic": switch v { case "true": st.opts = append(st.opts, IndentHeuristic()) case "false": // do nothing default: t.Fatalf("invalid value for indent-heuristic: %q", v) } name = append(name, k) case "force-anchoring-heuristic": switch v { case "true": // The inline function definition is necessary, because the anchoring // heuristic is not exported as an option. st.opts = append(st.opts, func(cfg *config.Config) config.Flag { cfg.ForceAnchoringHeuristic = true return 0 }) case "false": // do nothing default: t.Fatalf("invalid value for force-anchoring-heuristic: %q", v) } name = append(name, k) case "fast": switch v { case "true": st.opts = append(st.opts, diff.Fast()) case "false": // do nothing default: t.Fatalf("invalid value for fast: %q", v) } case "context": n, err := strconv.ParseInt(v, 10, 64) if err != nil { t.Fatalf("invalid value for context: %v", err.Error()) } st.opts = append(st.opts, diff.Context(int(n))) name = append(name, k+"="+v) default: t.Fatalf("unknown option: %q", k) } i = eol } if len(name) == 0 { name = append(name, "default") } st.name = strings.Join(name, ":") st.pragmas = data[:i] st.want = data[i:] test.subtests = append(test.subtests, st) default: t.Fatalf("unknown file in archive: %v", f) } } tests = append(tests, test) } return tests }